diff --git a/arch/arm/arm-v6m/cortex-m0/armcc/port_c.c b/arch/arm/arm-v6m/cortex-m0/armcc/port_c.c index 5a5b1c6a1..6d0cf1c81 100644 --- a/arch/arm/arm-v6m/cortex-m0/armcc/port_c.c +++ b/arch/arm/arm-v6m/cortex-m0/armcc/port_c.c @@ -1,3 +1,20 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + #include "tos_k.h" #include "core_cm0.h" diff --git a/arch/arm/arm-v6m/cortex-m0/gcc/port_c.c b/arch/arm/arm-v6m/cortex-m0/gcc/port_c.c index 8316e60ec..db1bcd826 100644 --- a/arch/arm/arm-v6m/cortex-m0/gcc/port_c.c +++ b/arch/arm/arm-v6m/cortex-m0/gcc/port_c.c @@ -1,3 +1,20 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + #include "tos_k.h" #include "core_cm0.h" diff --git a/arch/arm/arm-v6m/cortex-m0/iccarm/port_c.c b/arch/arm/arm-v6m/cortex-m0/iccarm/port_c.c index 106bb319c..1e1cc2d7f 100644 --- a/arch/arm/arm-v6m/cortex-m0/iccarm/port_c.c +++ b/arch/arm/arm-v6m/cortex-m0/iccarm/port_c.c @@ -1,3 +1,20 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + #include "tos_k.h" #include "core_cm0.h" diff --git a/arch/arm/arm-v8m/star-mc1/gcc/port.h b/arch/arm/arm-v8m/star-mc1/gcc/port.h new file mode 100644 index 000000000..ccc1329fd --- /dev/null +++ b/arch/arm/arm-v8m/star-mc1/gcc/port.h @@ -0,0 +1,311 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +/* + * The MIT License (MIT) + * + * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com) + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * 'Software'), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _PORT_H_ +#define _PORT_H_ + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u +typedef struct port_fault_regs { + union { + /* System Handler Control and State Register (0xE000ED24) */ + uint32_t value; + struct { + /* Read as 1 if memory management fault is active */ + uint32_t MEMFAULTACT : 1; + /* Read as 1 if bus fault exception is active */ + uint32_t BUSFAULTACT : 1; + uint32_t UnusedBits1 : 1; + /* Read as 1 if usage fault exception is active */ + uint32_t USGFAULTACT : 1; + uint32_t UnusedBits2 : 3; + /* Read as 1 if SVC exception is active */ + uint32_t SVCALLACT : 1; + /* Read as 1 if debug monitor exception is active */ + uint32_t MONITORACT : 1; + uint32_t UnusedBits3 : 1; + /* Read as 1 if PendSV exception is active */ + uint32_t PENDSVACT : 1; + /* Read as 1 if SYSTICK exception is active */ + uint32_t SYSTICKACT : 1; + /* Usage fault pended; usage fault started but was replaced by a higher-priority exception */ + uint32_t USGFAULTPENDED : 1; + /* Memory management fault pended; memory management fault started but was replaced by a + higher-priority exception */ + uint32_t MEMFAULTPENDED : 1; + /* Bus fault pended; bus fault handler was started but was replaced by a higher-priority + exception */ + uint32_t BUSFAULTPENDED : 1; + /* SVC pended; SVC was started but was replaced by a higher-priority exception */ + uint32_t SVCALLPENDED : 1; + /* Memory management fault handler enable */ + uint32_t MEMFAULTENA : 1; + /* Bus fault handler enable */ + uint32_t BUSFAULTENA : 1; + /* Usage fault handler enable */ + uint32_t USGFAULTENA : 1; + } bits; + } syshndctrl; + + union { + uint32_t value; + + struct { + union { + /* Memory Management Fault Status Register (0xE000ED28) */ + uint8_t value; + struct { + /* Instruction access violation */ + uint8_t IACCVIOL : 1; + /* Data access violation */ + uint8_t DACCVIOL : 1; + uint8_t UnusedBits : 1; + /* Unstacking error */ + uint8_t MUNSTKERR : 1; + /* Stacking error */ + uint8_t MSTKERR : 1; + /* Floating-point lazy state preservation (M4/M7) */ + uint8_t MLSPERR : 1; + uint8_t UnusedBits2 : 1; + /* Indicates the MMAR is valid */ + uint8_t MMARVALID : 1; + } bits; + } mfsr; + + union { + /* Bus Fault Status Register (0xE000ED29) */ + uint8_t value; + struct { + /* Instruction access violation */ + uint8_t IBUSERR : 1; + /* Precise data access violation */ + uint8_t PRECISERR : 1; + /* Imprecise data access violation */ + uint8_t IMPREISERR : 1; + /* Unstacking error */ + uint8_t UNSTKERR : 1; + /* Stacking error */ + uint8_t STKERR : 1; + /* Floating-point lazy state preservation (M4/M7) */ + uint8_t LSPERR : 1; + uint8_t UnusedBits : 1; + /* Indicates BFAR is valid */ + uint8_t BFARVALID : 1; + } bits; + } bfsr; + + union { + /* Usage Fault Status Register (0xE000ED2A) */ + uint16_t value; + struct { + /* Attempts to execute an undefined instruction */ + uint16_t UNDEFINSTR : 1; + /* Attempts to switch to an invalid state (e.g., ARM) */ + uint16_t INVSTATE : 1; + /* Attempts to do an exception with a bad value in the EXC_RETURN number */ + uint16_t INVPC : 1; + /* Attempts to execute a coprocessor instruction */ + uint16_t NOCP : 1; + uint16_t UnusedBits : 4; + /* Indicates that an unaligned access fault has taken place */ + uint16_t UNALIGNED : 1; + /* Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set) */ + uint16_t DIVBYZERO0 : 1; + } bits; + } ufsr; + } part; + } cfsr; + + /* Memory Management Fault Address Register (0xE000ED34) */ + uint32_t mmar; + + /* Bus Fault Manage Address Register (0xE000ED38) */ + uint32_t bfar; + + union { + /* Hard Fault Status Register (0xE000ED2C) */ + uint32_t value; + struct { + uint32_t UnusedBits : 1; + /* Indicates hard fault is caused by failed vector fetch */ + uint32_t VECTBL : 1; + uint32_t UnusedBits2 : 28; + /* Indicates hard fault is taken because of bus fault/memory management fault/usage fault */ + uint32_t FORCED : 1; + /* Indicates hard fault is triggered by debug event */ + uint32_t DEBUGEVT : 1; + } bits; + } hfsr; + + union { + /* Debug Fault Status Register (0xE000ED30) */ + uint32_t value; + struct { + /* Halt requested in NVIC */ + uint32_t HALTED : 1; + /* BKPT instruction executed */ + uint32_t BKPT : 1; + /* DWT match occurred */ + uint32_t DWTTRAP : 1; + /* Vector fetch occurred */ + uint32_t VCATCH : 1; + /* EDBGRQ signal asserted */ + uint32_t EXTERNAL : 1; + } bits; + } dfsr; + + /* Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional) */ + uint32_t afsr; +} port_fault_regs_t; + +enum fault_info { + FAULT_INFO_ASSERT_ON_THREAD, + FAULT_INFO_HFSR_VECTBL, + FAULT_INFO_MFSR_IACCVIOL, + FAULT_INFO_MFSR_DACCVIOL, + FAULT_INFO_MFSR_MUNSTKERR, + FAULT_INFO_MFSR_MSTKERR, + FAULT_INFO_MFSR_MLSPERR, + FAULT_INFO_BFSR_IBUSERR, + FAULT_INFO_BFSR_PRECISERR, + FAULT_INFO_BFSR_IMPREISERR, + FAULT_INFO_BFSR_UNSTKERR, + FAULT_INFO_BFSR_STKERR, + FAULT_INFO_BFSR_LSPERR, + FAULT_INFO_UFSR_UNDEFINSTR, + FAULT_INFO_UFSR_INVSTATE, + FAULT_INFO_UFSR_INVPC, + FAULT_INFO_UFSR_NOCP, + FAULT_INFO_UFSR_UNALIGNED, + FAULT_INFO_UFSR_DIVBYZERO0, + FAULT_INFO_DFSR_HALTED, + FAULT_INFO_DFSR_BKPT, + FAULT_INFO_DFSR_DWTTRAP, + FAULT_INFO_DFSR_VCATCH, + FAULT_INFO_DFSR_EXTERNAL, + FAULT_INFO_MMAR, + FAULT_INFO_BFAR, +}; + +static const char *const fault_msg[] = { + [FAULT_INFO_ASSERT_ON_THREAD] = "Assert on thread %s\n", + [FAULT_INFO_HFSR_VECTBL] = "Hard fault is caused by failed vector fetch\n", + [FAULT_INFO_MFSR_IACCVIOL] = "Memory management fault: instruction access violation\n", + [FAULT_INFO_MFSR_DACCVIOL] = "Memory management fault: data access violation\n", + [FAULT_INFO_MFSR_MUNSTKERR] = "Memory management fault: unstacking error\n", + [FAULT_INFO_MFSR_MSTKERR] = "Memory management fault: stacking error\n", + [FAULT_INFO_MFSR_MLSPERR] = "Memory management fault: floating-point lazy state preservation\n", + [FAULT_INFO_BFSR_IBUSERR] = "Bus fault: instruction access violation\n", + [FAULT_INFO_BFSR_PRECISERR] = "Bus fault: precise data access violation\n", + [FAULT_INFO_BFSR_IMPREISERR] = "Bus fault: imprecise data access violation\n", + [FAULT_INFO_BFSR_UNSTKERR] = "Bus fault: unstacking error\n", + [FAULT_INFO_BFSR_STKERR] = "Bus fault: stacking error\n", + [FAULT_INFO_BFSR_LSPERR] = "Bus fault: floating-point lazy state preservation\n", + [FAULT_INFO_UFSR_UNDEFINSTR] = "Usage fault: undefined instruction\n", + [FAULT_INFO_UFSR_INVSTATE] = "Usage fault: invalid state (e.g., ARM)\n", + [FAULT_INFO_UFSR_INVPC] = "Usage fault: invalid EXC_RETURN\n", + [FAULT_INFO_UFSR_NOCP] = "Usage fault: coprocessor instruction\n", + [FAULT_INFO_UFSR_UNALIGNED] = "Usage fault: unaligned access\n", + [FAULT_INFO_UFSR_DIVBYZERO0] = "Usage fault: divide by zero(can be set only if DIV_0_TRP is set)\n", + [FAULT_INFO_DFSR_HALTED] = "Debug fault: halt requested in NVIC\n", + [FAULT_INFO_DFSR_BKPT] = "Debug fault: BKPT instruction executed\n", + [FAULT_INFO_DFSR_DWTTRAP] = "Debug fault: DWT match occurred\n", + [FAULT_INFO_DFSR_VCATCH] = "Debug fault: Vector fetch occurred\n", + [FAULT_INFO_DFSR_EXTERNAL] = "Debug fault: EDBGRQ signal asserted\n", + [FAULT_INFO_MMAR] = "The memory management fault occurred address is %08x\n", + [FAULT_INFO_BFAR] = "The bus fault occurred address is %08x\n", +}; + +__PORT__ void HardFault_Handler(void); + +__PORT__ void port_fault_diagnosis(void); +#endif + +#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 1u) +__PORT__ uint32_t port_clz(uint32_t val); +#endif + +__PORT__ void port_int_disable(void); + +__PORT__ void port_int_enable(void); + +__PORT__ cpu_cpsr_t port_cpsr_save(void); + +__PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr); + +__PORT__ void port_cpu_reset(void); + +__PORT__ void port_sched_start(void) __NO_RETURN__; + +__PORT__ void port_context_switch(void); + +__PORT__ void port_irq_context_switch(void); + +__PORT__ void port_systick_config(uint32_t cycle_per_tick); + +__PORT__ void port_systick_priority_set(uint32_t prio); + +#if TOS_CFG_TICKLESS_EN > 0u + +__PORT__ void port_systick_resume(void); + +__PORT__ void port_systick_suspend(void); + +__PORT__ void port_systick_reload(uint32_t cycle_per_tick); + +__PORT__ void port_systick_pending_reset(void); + +__PORT__ k_time_t port_systick_max_delay_millisecond(void); + +#endif + +#if TOS_CFG_PWR_MGR_EN > 0u + +__PORT__ void port_sleep_mode_enter(void); + +__PORT__ void port_stop_mode_enter(void); + +__PORT__ void port_standby_mode_enter(void); + +#endif + +#endif /* _PORT_H_ */ + diff --git a/arch/arm/arm-v8m/star-mc1/gcc/port_c.c b/arch/arm/arm-v8m/star-mc1/gcc/port_c.c new file mode 100644 index 000000000..b2952b440 --- /dev/null +++ b/arch/arm/arm-v8m/star-mc1/gcc/port_c.c @@ -0,0 +1,255 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +/* + * The MIT License (MIT) + * + * Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com) + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * 'Software'), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "tos_k.h" +#include "core_star.h" + +__PORT__ void port_cpu_reset(void) +{ + NVIC_SystemReset(); +} + +__PORT__ void port_systick_config(uint32_t cycle_per_tick) +{ + (void)SysTick_Config(cycle_per_tick); +} + +__PORT__ void port_systick_priority_set(uint32_t prio) +{ + NVIC_SetPriority(SysTick_IRQn, prio); +} + +#if TOS_CFG_TICKLESS_EN > 0u + +__PORT__ k_time_t port_systick_max_delay_millisecond(void) +{ + k_time_t max_millisecond; + uint32_t max_cycle; + + max_cycle = SysTick_LOAD_RELOAD_Msk; // 24 bit + max_millisecond = (k_time_t)((uint64_t)max_cycle * K_TIME_MILLISEC_PER_SEC / TOS_CFG_CPU_CLOCK); // CLOCK: cycle per second + return max_millisecond; +} + +__PORT__ void port_systick_resume(void) +{ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; +} + +__PORT__ void port_systick_suspend(void) +{ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +__PORT__ void port_systick_reload(uint32_t cycle_per_tick) +{ + port_systick_config(cycle_per_tick); +} + +__PORT__ void port_systick_pending_reset(void) +{ + SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk; +} + +#endif + +#if TOS_CFG_PWR_MGR_EN > 0u + +__PORT__ void port_sleep_mode_enter(void) +{ +#if 1 + HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI); +#else + HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); +#endif +} + +__PORT__ void port_stop_mode_enter(void) +{ + HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); +} + +__PORT__ void port_standby_mode_enter(void) +{ + HAL_PWR_EnterSTANDBYMode(); +} + +#endif + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u +__STATIC__ void port_fault_do_diagnosis(port_fault_regs_t *regs) +{ + k_fault_log_writer("\n\n====================== Fault Diagnosis =====================\n"); + + if (regs->hfsr.bits.VECTBL) { + k_fault_log_writer(fault_msg[FAULT_INFO_HFSR_VECTBL]); + } + if (regs->hfsr.bits.FORCED) { + /* Memory Management Fault */ + if (regs->cfsr.part.mfsr.value) { + if (regs->cfsr.part.mfsr.bits.IACCVIOL) { + k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_IACCVIOL]); + } + if (regs->cfsr.part.mfsr.bits.DACCVIOL) { + k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_DACCVIOL]); + } + if (regs->cfsr.part.mfsr.bits.MUNSTKERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MUNSTKERR]); + } + if (regs->cfsr.part.mfsr.bits.MSTKERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MSTKERR]); + } + + if (regs->cfsr.part.mfsr.bits.MLSPERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_MFSR_MLSPERR]); + } + + if (regs->cfsr.part.mfsr.bits.MMARVALID) { + if (regs->cfsr.part.mfsr.bits.IACCVIOL || regs->cfsr.part.mfsr.bits.DACCVIOL) { + k_fault_log_writer(fault_msg[FAULT_INFO_MMAR], regs->mmar); + } + } + } + /* Bus Fault */ + if (regs->cfsr.part.bfsr.value) { + if (regs->cfsr.part.bfsr.bits.IBUSERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IBUSERR]); + } + if (regs->cfsr.part.bfsr.bits.PRECISERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_PRECISERR]); + } + if (regs->cfsr.part.bfsr.bits.IMPREISERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_IMPREISERR]); + } + if (regs->cfsr.part.bfsr.bits.UNSTKERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_UNSTKERR]); + } + if (regs->cfsr.part.bfsr.bits.STKERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_STKERR]); + } + + if (regs->cfsr.part.bfsr.bits.LSPERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_BFSR_LSPERR]); + } + + if (regs->cfsr.part.bfsr.bits.BFARVALID) { + if (regs->cfsr.part.bfsr.bits.PRECISERR) { + k_fault_log_writer(fault_msg[FAULT_INFO_BFAR], regs->bfar); + } + } + + } + /* Usage Fault */ + if (regs->cfsr.part.ufsr.value) { + if (regs->cfsr.part.ufsr.bits.UNDEFINSTR) { + k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNDEFINSTR]); + } + if (regs->cfsr.part.ufsr.bits.INVSTATE) { + k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVSTATE]); + } + if (regs->cfsr.part.ufsr.bits.INVPC) { + k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_INVPC]); + } + if (regs->cfsr.part.ufsr.bits.NOCP) { + k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_NOCP]); + } + if (regs->cfsr.part.ufsr.bits.UNALIGNED) { + k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_UNALIGNED]); + } + if (regs->cfsr.part.ufsr.bits.DIVBYZERO0) { + k_fault_log_writer(fault_msg[FAULT_INFO_UFSR_DIVBYZERO0]); + } + } + } + /* Debug Fault */ + if (regs->hfsr.bits.DEBUGEVT) { + if (regs->dfsr.value) { + if (regs->dfsr.bits.HALTED) { + k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_HALTED]); + } + if (regs->dfsr.bits.BKPT) { + k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_BKPT]); + } + if (regs->dfsr.bits.DWTTRAP) { + k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_DWTTRAP]); + } + if (regs->dfsr.bits.VCATCH) { + k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_VCATCH]); + } + if (regs->dfsr.bits.EXTERNAL) { + k_fault_log_writer(fault_msg[FAULT_INFO_DFSR_EXTERNAL]); + } + } + } +} + +__PORT__ void port_fault_diagnosis(void) +{ + port_fault_regs_t regs; + + regs.syshndctrl.value = SCB->SHCSR; + regs.cfsr.value = SCB->CFSR; + regs.mmar = SCB->MMFAR; + regs.bfar = SCB->BFAR; + regs.hfsr.value = SCB->HFSR; + regs.dfsr.value = SCB->DFSR; + regs.afsr = SCB->AFSR; + + port_fault_do_diagnosis(®s); +} + +__PORT__ void __NAKED__ HardFault_Handler(void) +{ + __ASM__ __VOLATILE__ ( + "MOV r0, lr\n\t" + "TST lr, #0x04\n\t" + "ITE EQ\n\t" + "MRSEQ r1, MSP\n\t" + "MRSNE r1, PSP\n\t" + "BL fault_backtrace\n\t" + ); +} + +#endif /* TOS_CFG_FAULT_BACKTRACE_EN */ + diff --git a/arch/arm/arm-v8m/star-mc1/gcc/port_config.h b/arch/arm/arm-v8m/star-mc1/gcc/port_config.h new file mode 100644 index 000000000..9145f29f1 --- /dev/null +++ b/arch/arm/arm-v8m/star-mc1/gcc/port_config.h @@ -0,0 +1,36 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _PORT_CONFIG_H_ +#define _PORT_CONFIG_H_ + +#define TOS_CFG_CPU_ADDR_SIZE CPU_WORD_SIZE_32 +#define TOS_CFG_CPU_DATA_SIZE CPU_WORD_SIZE_32 +#define TOS_CFG_CPU_STK_GROWTH CPU_STK_GROWTH_DESCENDING +// #define TOS_CFG_CPU_HRTIMER_SIZE CPU_WORD_SIZE_32 +#define TOS_CFG_CPU_HRTIMER_EN 0u +#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 1u +#define TOS_CFG_CPU_BYTE_ORDER CPU_BYTE_ORDER_LITTLE_ENDIAN + +#if (defined(__VFP_FP__) && !defined(__SOFTFP__)) +#define TOS_CFG_CPU_ARM_FPU_EN 1u +#else +#define TOS_CFG_CPU_ARM_FPU_EN 0u +#endif + +#endif /* _PORT_CONFIG_H_ */ + diff --git a/arch/arm/arm-v8m/star-mc1/gcc/port_s.S b/arch/arm/arm-v8m/star-mc1/gcc/port_s.S new file mode 100644 index 000000000..84a2528da --- /dev/null +++ b/arch/arm/arm-v8m/star-mc1/gcc/port_s.S @@ -0,0 +1,202 @@ + .global port_int_disable + .global port_int_enable + + .global port_cpsr_save + .global port_cpsr_restore + + .global port_sched_start + .global port_context_switch + .global port_irq_context_switch + + .global port_clz + + .global PendSV_Handler + + .extern k_curr_task + .extern k_next_task + + +.equ SCB_VTOR, 0xE000ED08 +.equ NVIC_INT_CTRL, 0xE000ED04 +.equ NVIC_SYSPRI14, 0xE000ED22 +.equ NVIC_PENDSV_PRI, 0xFF +.equ NVIC_PENDSVSET, 0x10000000 + + + .text + .align 2 + .thumb + .syntax unified + + +.type port_int_disable, %function +port_int_disable: + CPSID I + BX LR + + +.type port_int_enable, %function +port_int_enable: + CPSIE I + BX LR + + +.type port_cpsr_save, %function +port_cpsr_save: + MRS R0, PRIMASK + CPSID I + BX LR + + +.type port_cpsr_restore, %function +port_cpsr_restore: + MSR PRIMASK, R0 + BX LR + + +.type port_clz, %function +port_clz: + CLZ R0, R0 + BX LR + + +.thumb_func +.type port_sched_start, %function +port_sched_start: + CPSID I + + @ set pendsv priority lowest + @ otherwise trigger pendsv in port_irq_context_switch will cause a context switch in irq + @ that would be a disaster + MOVW R0, #:lower16:NVIC_SYSPRI14 + MOVT R0, #:upper16:NVIC_SYSPRI14 + + MOVW R1, #:lower16:NVIC_PENDSV_PRI + MOVT R1, #:upper16:NVIC_PENDSV_PRI + STRB R1, [R0] + + MOVW R0, #:lower16:SCB_VTOR + MOVT R0, #:upper16:SCB_VTOR + LDR R0, [R0] + LDR R0, [R0] + MSR MSP, R0 + + MOVW R0, #:lower16:k_curr_task + MOVT R0, #:upper16:k_curr_task + + @ k_curr_task = k_next_task; + MOVW R1, #:lower16:k_next_task + MOVT R1, #:upper16:k_next_task + LDR R2, [R1] + STR R2, [R0] + + @ sp = k_next_task->sp + LDR R0, [R2] + @ PSP = sp + MSR PSP, R0 + + MRS R0, CONTROL + ORR R0, R0, #2 + MSR CONTROL, R0 + + ISB + + @ restore r4-11 from new process stack + LDMFD SP!, {R4 - R11} + + #if (defined(__VFP_FP__) && !defined(__SOFTFP__)) + @ ignore EXC_RETURN the first switch + LDMFD SP!, {R0} + #endif + + @ restore r0, r3 + LDMFD SP!, {R0 - R3} + @ load R12 and LR + LDMFD SP!, {R12, LR} + @ load PC and discard xPSR + LDMFD SP!, {R1, R2} + + CPSIE I + BX R1 + + +.thumb_func +.type port_context_switch, %function +port_context_switch: + LDR R0, =NVIC_INT_CTRL + LDR R1, =NVIC_PENDSVSET + STR R1, [R0] + BX LR + + +.thumb_func +.type port_irq_context_switch, %function +port_irq_context_switch: + LDR R0, =NVIC_INT_CTRL + LDR R1, =NVIC_PENDSVSET + STR R1, [R0] + BX LR + + +.thumb_func +.type PendSV_Handler, %function +PendSV_Handler: + CPSID I + MRS R0, PSP + +_context_save: + @ R0-R3, R12, LR, PC, xPSR is saved automatically here + #if (defined(__VFP_FP__) && !defined(__SOFTFP__)) + @ is it extended frame? + TST LR, #0x10 + IT EQ + VSTMDBEQ R0!, {S16 - S31} + @ S0 - S16, FPSCR saved automatically here + + @ save EXC_RETURN + STMFD R0!, {LR} + #endif + + @ save remaining regs r4 - 11 on process stack + STMFD R0!, {R4 - R11} + + @ k_curr_task->sp = PSP; + MOVW R5, #:lower16:k_curr_task + MOVT R5, #:upper16:k_curr_task + LDR R6, [R5] + @ R0 is SP of process being switched out + STR R0, [R6] + +_context_restore: + @ k_curr_task = k_next_task; + MOVW R1, #:lower16:k_next_task + MOVT R1, #:upper16:k_next_task + LDR R2, [R1] + STR R2, [R5] + + @ R0 = k_next_task->sp + LDR R0, [R2] + + @ restore R4 - R11 + LDMFD R0!, {R4 - R11} + + #if (defined(__VFP_FP__) && !defined(__SOFTFP__)) + @ restore EXC_RETURN + LDMFD R0!, {LR} + @ is it extended frame? + TST LR, #0x10 + IT EQ + VLDMIAEQ R0!, {S16 - S31} + #endif + + @ Load PSP with new process SP + MSR PSP, R0 + + CPSIE I + + @ R0-R3, R12, LR, PC, xPSR restored automatically here + @ S0 - S16, FPSCR restored automatically here if FPCA = 1 + BX LR + +.end + diff --git a/board/ALIENTEK_EXPLORER_STM32F407ZGT6/KEIL/modbus/ALIENTEK_EXPLORER_STM32F407ZGT6.uvoptx b/board/ALIENTEK_EXPLORER_STM32F407ZGT6/KEIL/modbus/ALIENTEK_EXPLORER_STM32F407ZGT6.uvoptx deleted file mode 100644 index 779208777..000000000 --- a/board/ALIENTEK_EXPLORER_STM32F407ZGT6/KEIL/modbus/ALIENTEK_EXPLORER_STM32F407ZGT6.uvoptx +++ /dev/null @@ -1,1105 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - ALIENTEK_EXPLORER_STM32F407ZGT6 - 0x4 - ARM-ADS - - 168000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 18 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 4 - - - - - - - - - - - Segger\JL2CM3.dll - - - - 0 - JL2CM3 - -U29999997 -O14 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06413041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F407ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM) - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM)) - - - 0 - ST-LINKIII-KEIL_SWO - -U003900513137510B39383538 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F407ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM) - - - - - 0 - - - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - 1 - 1 - 0 - 2 - 10000000 - - - - - - Application/MDK-ARM - 0 - 0 - 0 - 0 - - 1 - 1 - 2 - 0 - 0 - 0 - startup_stm32f407xx.s - startup_stm32f407xx.s - 0 - 0 - - - - - Application/User - 1 - 0 - 0 - 0 - - 2 - 2 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\gpio.c - gpio.c - 0 - 0 - - - 2 - 3 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\main.c - main.c - 0 - 0 - - - 2 - 4 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\mcu_init.c - mcu_init.c - 0 - 0 - - - 2 - 5 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\stm32f4xx_hal_msp.c - stm32f4xx_hal_msp.c - 0 - 0 - - - 2 - 6 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\stm32f4xx_it.c - stm32f4xx_it.c - 0 - 0 - - - 2 - 7 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\usart.c - usart.c - 0 - 0 - - - 2 - 8 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\tim.c - tim.c - 0 - 0 - - - - - Drivers/STM32F4xx_HAL_Driver - 0 - 0 - 0 - 0 - - 3 - 9 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c - stm32f4xx_hal.c - 0 - 0 - - - 3 - 10 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c - stm32f4xx_hal_cortex.c - 0 - 0 - - - 3 - 11 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c - stm32f4xx_hal_dma.c - 0 - 0 - - - 3 - 12 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c - stm32f4xx_hal_dma_ex.c - 0 - 0 - - - 3 - 13 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c - stm32f4xx_hal_exti.c - 0 - 0 - - - 3 - 14 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c - stm32f4xx_hal_flash.c - 0 - 0 - - - 3 - 15 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c - stm32f4xx_hal_flash_ex.c - 0 - 0 - - - 3 - 16 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c - stm32f4xx_hal_flash_ramfunc.c - 0 - 0 - - - 3 - 17 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c - stm32f4xx_hal_gpio.c - 0 - 0 - - - 3 - 18 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c - stm32f4xx_hal_pwr.c - 0 - 0 - - - 3 - 19 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c - stm32f4xx_hal_pwr_ex.c - 0 - 0 - - - 3 - 20 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c - stm32f4xx_hal_rcc.c - 0 - 0 - - - 3 - 21 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c - stm32f4xx_hal_rcc_ex.c - 0 - 0 - - - 3 - 22 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c - stm32f4xx_hal_uart.c - 0 - 0 - - - 3 - 23 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c - stm32f4xx_hal_tim.c - 0 - 0 - - - 3 - 24 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c - stm32f4xx_hal_tim_ex.c - 0 - 0 - - - - - Drivers/CMSIS - 0 - 0 - 0 - 0 - - 4 - 25 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\system_stm32f4xx.c - system_stm32f4xx.c - 0 - 0 - - - - - tos/arch - 0 - 0 - 0 - 0 - - 5 - 26 - 1 - 0 - 0 - 0 - ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c - tos_cpu.c - 0 - 0 - - - 5 - 27 - 1 - 0 - 0 - 0 - ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_c.c - port_c.c - 0 - 0 - - - 5 - 28 - 2 - 0 - 0 - 0 - ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_s.S - port_s.S - 0 - 0 - - - - - tos/kernel - 0 - 0 - 0 - 0 - - 6 - 29 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_event.c - tos_event.c - 0 - 0 - - - 6 - 30 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_global.c - tos_global.c - 0 - 0 - - - 6 - 31 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_mmblk.c - tos_mmblk.c - 0 - 0 - - - 6 - 32 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_mmheap.c - tos_mmheap.c - 0 - 0 - - - 6 - 33 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_mutex.c - tos_mutex.c - 0 - 0 - - - 6 - 34 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_pend.c - tos_pend.c - 0 - 0 - - - 6 - 35 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_robin.c - tos_robin.c - 0 - 0 - - - 6 - 36 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_sched.c - tos_sched.c - 0 - 0 - - - 6 - 37 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_sem.c - tos_sem.c - 0 - 0 - - - 6 - 38 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_sys.c - tos_sys.c - 0 - 0 - - - 6 - 39 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_task.c - tos_task.c - 0 - 0 - - - 6 - 40 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_tick.c - tos_tick.c - 0 - 0 - - - 6 - 41 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_time.c - tos_time.c - 0 - 0 - - - 6 - 42 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_timer.c - tos_timer.c - 0 - 0 - - - 6 - 43 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_binary_heap.c - tos_binary_heap.c - 0 - 0 - - - 6 - 44 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_char_fifo.c - tos_char_fifo.c - 0 - 0 - - - 6 - 45 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_completion.c - tos_completion.c - 0 - 0 - - - 6 - 46 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_countdownlatch.c - tos_countdownlatch.c - 0 - 0 - - - 6 - 47 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_mail_queue.c - tos_mail_queue.c - 0 - 0 - - - 6 - 48 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_message_queue.c - tos_message_queue.c - 0 - 0 - - - 6 - 49 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_priority_mail_queue.c - tos_priority_mail_queue.c - 0 - 0 - - - 6 - 50 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_priority_message_queue.c - tos_priority_message_queue.c - 0 - 0 - - - 6 - 51 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_priority_queue.c - tos_priority_queue.c - 0 - 0 - - - 6 - 52 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_ring_queue.c - tos_ring_queue.c - 0 - 0 - - - - - tos/cmsis - 0 - 0 - 0 - 0 - - 7 - 53 - 1 - 0 - 0 - 0 - ..\..\..\..\osal\cmsis_os\cmsis_os.c - cmsis_os.c - 0 - 0 - - - - - examples - 1 - 0 - 0 - 0 - - 8 - 54 - 1 - 0 - 0 - 0 - ..\..\..\..\examples\modbus\modbus.c - modbus.c - 0 - 0 - - - - - modbus_src - 0 - 0 - 0 - 0 - - 9 - 55 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\ascii\mbascii.c - mbascii.c - 0 - 0 - - - 9 - 56 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfunccoils.c - mbfunccoils.c - 0 - 0 - - - 9 - 57 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncdiag.c - mbfuncdiag.c - 0 - 0 - - - 9 - 58 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncdisc.c - mbfuncdisc.c - 0 - 0 - - - 9 - 59 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncholding.c - mbfuncholding.c - 0 - 0 - - - 9 - 60 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncinput.c - mbfuncinput.c - 0 - 0 - - - 9 - 61 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncother.c - mbfuncother.c - 0 - 0 - - - 9 - 62 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbutils.c - mbutils.c - 0 - 0 - - - 9 - 63 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\rtu\mbcrc.c - mbcrc.c - 0 - 0 - - - 9 - 64 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\rtu\mbrtu.c - mbrtu.c - 0 - 0 - - - 9 - 65 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\mb.c - mb.c - 0 - 0 - - - 9 - 66 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\tcp\mbtcp.c - mbtcp.c - 0 - 0 - - - - - modbus_port - 1 - 0 - 0 - 0 - - 10 - 67 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\porting\TencentOS_Tiny\portevent.c - portevent.c - 0 - 0 - - - 10 - 68 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\porting\TencentOS_Tiny\portserial.c - portserial.c - 0 - 0 - - - 10 - 69 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\porting\TencentOS_Tiny\porttimer.c - porttimer.c - 0 - 0 - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - -
diff --git a/board/ALIENTEK_EXPLORER_STM32F407ZGT6/KEIL/modbus/ALIENTEK_EXPLORER_STM32F407ZGT6.uvprojx b/board/ALIENTEK_EXPLORER_STM32F407ZGT6/KEIL/modbus/ALIENTEK_EXPLORER_STM32F407ZGT6.uvprojx deleted file mode 100644 index b6d05544a..000000000 --- a/board/ALIENTEK_EXPLORER_STM32F407ZGT6/KEIL/modbus/ALIENTEK_EXPLORER_STM32F407ZGT6.uvprojx +++ /dev/null @@ -1,797 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - ALIENTEK_EXPLORER_STM32F407ZGT6 - 0x4 - ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC - 0 - - - STM32F407ZGTx - STMicroelectronics - Keil.STM32F4xx_DFP.2.14.0 - http://www.keil.com/pack/ - IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) FPU2 CPUTYPE("Cortex-M4") - - - - - - - - - - - - - - - $$Device:STM32F407ZGTx$CMSIS\SVD\STM32F40x.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - ALIENTEK_EXPLORER_STM32F407ZGT6\ - ALIENTEK_EXPLORER_STM32F407ZGT6 - 1 - 0 - 0 - 1 - 0 - - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 0 - - - SARMCM3.DLL - -REMAP -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4101 - - 1 - STLink\ST-LINKIII-KEIL_SWO.dll - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 0 - 1 - 0 - 8 - 1 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 1 - 0x8000000 - 0x100000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x100000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x20000 - - - 0 - 0x10000000 - 0x10000 - - - - - - 1 - 4 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - USE_HAL_DRIVER,STM32F407xx,USE_HAL_DRIVER,STM32F407xx,USE_MODBUS - - ..\..\BSP\Inc;..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Inc;..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Inc\Legacy;..\..\..\..\platform\vendor_bsp\st\CMSIS\Device\ST\STM32F4xx\Include;..\..\..\..\platform\vendor_bsp\st\CMSIS\Include;..\..\..\..\arch\arm\arm-v7m\common\include;..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc;..\..\..\..\kernel\core\include;..\..\..\..\kernel\pm\include;..\..\..\..\osal\cmsis_os;..\..\TOS_CONFIG;..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\ascii;..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions;..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\include;..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\rtu;..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\tcp;..\..\..\..\components\connectivity\Modbus\porting\TencentOS_Tiny - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - - - - - - Application/MDK-ARM - - - startup_stm32f407xx.s - 2 - startup_stm32f407xx.s - - - - - Application/User - - - gpio.c - 1 - ..\..\BSP\Src\gpio.c - - - main.c - 1 - ..\..\BSP\Src\main.c - - - mcu_init.c - 1 - ..\..\BSP\Src\mcu_init.c - - - stm32f4xx_hal_msp.c - 1 - ..\..\BSP\Src\stm32f4xx_hal_msp.c - - - stm32f4xx_it.c - 1 - ..\..\BSP\Src\stm32f4xx_it.c - - - usart.c - 1 - ..\..\BSP\Src\usart.c - - - tim.c - 1 - ..\..\BSP\Src\tim.c - - - - - Drivers/STM32F4xx_HAL_Driver - - - stm32f4xx_hal.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c - - - stm32f4xx_hal_cortex.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c - - - stm32f4xx_hal_dma.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c - - - stm32f4xx_hal_dma_ex.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c - - - stm32f4xx_hal_exti.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c - - - stm32f4xx_hal_flash.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c - - - stm32f4xx_hal_flash_ex.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c - - - stm32f4xx_hal_flash_ramfunc.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c - - - stm32f4xx_hal_gpio.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c - - - stm32f4xx_hal_pwr.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c - - - stm32f4xx_hal_pwr_ex.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c - - - stm32f4xx_hal_rcc.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c - - - stm32f4xx_hal_rcc_ex.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c - - - stm32f4xx_hal_uart.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c - - - stm32f4xx_hal_tim.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c - - - stm32f4xx_hal_tim_ex.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c - - - - - Drivers/CMSIS - - - system_stm32f4xx.c - 1 - ..\..\BSP\Src\system_stm32f4xx.c - - - - - tos/arch - - - tos_cpu.c - 1 - ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c - - - port_c.c - 1 - ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_c.c - - - port_s.S - 2 - ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_s.S - - - - - tos/kernel - - - tos_event.c - 1 - ..\..\..\..\kernel\core\tos_event.c - - - tos_global.c - 1 - ..\..\..\..\kernel\core\tos_global.c - - - tos_mmblk.c - 1 - ..\..\..\..\kernel\core\tos_mmblk.c - - - tos_mmheap.c - 1 - ..\..\..\..\kernel\core\tos_mmheap.c - - - tos_mutex.c - 1 - ..\..\..\..\kernel\core\tos_mutex.c - - - tos_pend.c - 1 - ..\..\..\..\kernel\core\tos_pend.c - - - tos_robin.c - 1 - ..\..\..\..\kernel\core\tos_robin.c - - - tos_sched.c - 1 - ..\..\..\..\kernel\core\tos_sched.c - - - tos_sem.c - 1 - ..\..\..\..\kernel\core\tos_sem.c - - - tos_sys.c - 1 - ..\..\..\..\kernel\core\tos_sys.c - - - tos_task.c - 1 - ..\..\..\..\kernel\core\tos_task.c - - - tos_tick.c - 1 - ..\..\..\..\kernel\core\tos_tick.c - - - tos_time.c - 1 - ..\..\..\..\kernel\core\tos_time.c - - - tos_timer.c - 1 - ..\..\..\..\kernel\core\tos_timer.c - - - tos_binary_heap.c - 1 - ..\..\..\..\kernel\core\tos_binary_heap.c - - - tos_char_fifo.c - 1 - ..\..\..\..\kernel\core\tos_char_fifo.c - - - tos_completion.c - 1 - ..\..\..\..\kernel\core\tos_completion.c - - - tos_countdownlatch.c - 1 - ..\..\..\..\kernel\core\tos_countdownlatch.c - - - tos_mail_queue.c - 1 - ..\..\..\..\kernel\core\tos_mail_queue.c - - - tos_message_queue.c - 1 - ..\..\..\..\kernel\core\tos_message_queue.c - - - tos_priority_mail_queue.c - 1 - ..\..\..\..\kernel\core\tos_priority_mail_queue.c - - - tos_priority_message_queue.c - 1 - ..\..\..\..\kernel\core\tos_priority_message_queue.c - - - tos_priority_queue.c - 1 - ..\..\..\..\kernel\core\tos_priority_queue.c - - - tos_ring_queue.c - 1 - ..\..\..\..\kernel\core\tos_ring_queue.c - - - - - tos/cmsis - - - cmsis_os.c - 1 - ..\..\..\..\osal\cmsis_os\cmsis_os.c - - - - - examples - - - modbus.c - 1 - ..\..\..\..\examples\modbus\modbus.c - - - - - modbus_src - - - mbascii.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\ascii\mbascii.c - - - mbfunccoils.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfunccoils.c - - - mbfuncdiag.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncdiag.c - - - mbfuncdisc.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncdisc.c - - - mbfuncholding.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncholding.c - - - mbfuncinput.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncinput.c - - - mbfuncother.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncother.c - - - mbutils.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbutils.c - - - mbcrc.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\rtu\mbcrc.c - - - mbrtu.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\rtu\mbrtu.c - - - mb.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\mb.c - - - mbtcp.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\tcp\mbtcp.c - - - - - modbus_port - - - portevent.c - 1 - ..\..\..\..\components\connectivity\Modbus\porting\TencentOS_Tiny\portevent.c - - - portserial.c - 1 - ..\..\..\..\components\connectivity\Modbus\porting\TencentOS_Tiny\portserial.c - - - porttimer.c - 1 - ..\..\..\..\components\connectivity\Modbus\porting\TencentOS_Tiny\porttimer.c - - - - - ::CMSIS - - - - - - - - - - - - - - - - - - -
diff --git a/board/ALIENTEK_EXPLORER_STM32F407ZGT6/KEIL/modbus/startup_stm32f407xx.s b/board/ALIENTEK_EXPLORER_STM32F407ZGT6/KEIL/modbus/startup_stm32f407xx.s deleted file mode 100644 index 148a64aae..000000000 --- a/board/ALIENTEK_EXPLORER_STM32F407ZGT6/KEIL/modbus/startup_stm32f407xx.s +++ /dev/null @@ -1,438 +0,0 @@ -;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** -;* File Name : startup_stm32f407xx.s -;* Author : MCD Application Team -;* Description : STM32F407xx devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -HASH_RNG_IRQHandler -FPU_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/board/BDW01-STM32L496VG/BSP/app/mqttclient_iot_explorer.c b/board/BDW01-STM32L496VG/BSP/app/mqttclient_iot_explorer.c index 372b308ad..5bb4d30e3 100644 --- a/board/BDW01-STM32L496VG/BSP/app/mqttclient_iot_explorer.c +++ b/board/BDW01-STM32L496VG/BSP/app/mqttclient_iot_explorer.c @@ -2,7 +2,7 @@ #include "mcu_init.h" #include "tos_k.h" #include "mqttclient.h" -#include "cjson.h" +#include "cJSON.h" #include "sal_module_wrapper.h" diff --git a/board/BearPi_STM32L562RE/KEIL/mqttclient_iot_explorer/demo/mqttclient_iot_explorer.c b/board/BearPi_STM32L562RE/KEIL/mqttclient_iot_explorer/demo/mqttclient_iot_explorer.c index 80a856447..aa9dc566d 100644 --- a/board/BearPi_STM32L562RE/KEIL/mqttclient_iot_explorer/demo/mqttclient_iot_explorer.c +++ b/board/BearPi_STM32L562RE/KEIL/mqttclient_iot_explorer/demo/mqttclient_iot_explorer.c @@ -2,7 +2,7 @@ #include "mcu_init.h" #include "tos_k.h" #include "mqttclient.h" -#include "cjson.h" +#include "cJSON.h" #include "sal_module_wrapper.h" #define USE_ESP8266 diff --git a/board/Fire_STM32H743IIT6/BSP/.mxproject b/board/Fire_STM32H743IIT6/BSP/.mxproject new file mode 100644 index 000000000..132d00a6b --- /dev/null +++ b/board/Fire_STM32H743IIT6/BSP/.mxproject @@ -0,0 +1,29 @@ +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=5 +HeaderFiles#0=D:/MCU/Fire-STM32H743II/project/TencentOS-Tiny/Core/Inc/gpio.h +HeaderFiles#1=D:/MCU/Fire-STM32H743II/project/TencentOS-Tiny/Core/Inc/usart.h +HeaderFiles#2=D:/MCU/Fire-STM32H743II/project/TencentOS-Tiny/Core/Inc/stm32h7xx_it.h +HeaderFiles#3=D:/MCU/Fire-STM32H743II/project/TencentOS-Tiny/Core/Inc/stm32h7xx_hal_conf.h +HeaderFiles#4=D:/MCU/Fire-STM32H743II/project/TencentOS-Tiny/Core/Inc/main.h +HeaderFolderListSize=1 +HeaderPath#0=D:/MCU/Fire-STM32H743II/project/TencentOS-Tiny/Core/Inc +HeaderFiles=; +SourceFileListSize=5 +SourceFiles#0=D:/MCU/Fire-STM32H743II/project/TencentOS-Tiny/Core/Src/gpio.c +SourceFiles#1=D:/MCU/Fire-STM32H743II/project/TencentOS-Tiny/Core/Src/usart.c +SourceFiles#2=D:/MCU/Fire-STM32H743II/project/TencentOS-Tiny/Core/Src/stm32h7xx_it.c +SourceFiles#3=D:/MCU/Fire-STM32H743II/project/TencentOS-Tiny/Core/Src/stm32h7xx_hal_msp.c +SourceFiles#4=D:/MCU/Fire-STM32H743II/project/TencentOS-Tiny/Core/Src/main.c +SourceFolderListSize=1 +SourcePath#0=D:/MCU/Fire-STM32H743II/project/TencentOS-Tiny/Core/Src +SourceFiles=; + +[PreviousLibFiles] +LibFiles=Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_uart.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_uart_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h;Drivers\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_uart.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_uart_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h;Drivers\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\stm32h743xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h; + +[PreviousUsedKeilFiles] +SourceFiles=..\Core\Src\main.c;..\Core\Src\gpio.c;..\Core\Src\usart.c;..\Core\Src\stm32h7xx_it.c;..\Core\Src\stm32h7xx_hal_msp.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c;..\Drivers\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c;..\Core\Src\system_stm32h7xx.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c;..\Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c;..\Drivers\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c;..\Core\Src\system_stm32h7xx.c;;; +HeaderPath=..\Drivers\STM32H7xx_HAL_Driver\Inc;..\Drivers\STM32H7xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32H7xx\Include;..\Drivers\CMSIS\Include;..\Core\Inc; +CDefines=USE_HAL_DRIVER;STM32H743xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + diff --git a/board/Fire_STM32H743IIT6/BSP/Core/Inc/gpio.h b/board/Fire_STM32H743IIT6/BSP/Core/Inc/gpio.h new file mode 100644 index 000000000..45e27b1e0 --- /dev/null +++ b/board/Fire_STM32H743IIT6/BSP/Core/Inc/gpio.h @@ -0,0 +1,49 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ GPIO_H__ */ + diff --git a/board/Fire_STM32H743IIT6/BSP/Core/Inc/main.h b/board/Fire_STM32H743IIT6/BSP/Core/Inc/main.h new file mode 100644 index 000000000..c4c7a7be3 --- /dev/null +++ b/board/Fire_STM32H743IIT6/BSP/Core/Inc/main.h @@ -0,0 +1,68 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/board/Fire_STM32H743IIT6/BSP/Core/Inc/mcu_init.h b/board/Fire_STM32H743IIT6/BSP/Core/Inc/mcu_init.h new file mode 100644 index 000000000..524da99f3 --- /dev/null +++ b/board/Fire_STM32H743IIT6/BSP/Core/Inc/mcu_init.h @@ -0,0 +1,21 @@ +#ifndef __MCU_INIT_H +#define __MCU_INIT_H +#ifdef __cplusplus + extern "C" { +#endif + +#include + +#include "main.h" +#include "usart.h" +#include "gpio.h" + +#include "tos_k.h" + +void board_init(void); +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif +#endif /*__ __MCU_INIT_H */ diff --git a/board/Fire_STM32H743IIT6/BSP/Core/Inc/stm32h7xx_hal_conf.h b/board/Fire_STM32H743IIT6/BSP/Core/Inc/stm32h7xx_hal_conf.h new file mode 100644 index 000000000..f28498517 --- /dev/null +++ b/board/Fire_STM32H743IIT6/BSP/Core/Inc/stm32h7xx_hal_conf.h @@ -0,0 +1,510 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_CONF_H +#define STM32H7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_FDCAN_MODULE_ENABLED */ +/* #define HAL_FMAC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_COMP_MODULE_ENABLED */ +/* #define HAL_CORDIC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_OTFDEC_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HRTIM_MODULE_ENABLED */ +/* #define HAL_HSEM_MODULE_ENABLED */ +/* #define HAL_GFXMMU_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_OPAMP_MODULE_ENABLED */ +/* #define HAL_OSPI_MODULE_ENABLED */ +/* #define HAL_OSPI_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_RAMECC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_SWPMI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_PSSI_MODULE_ENABLED */ +/* #define HAL_DTS_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_MDMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_HSEM_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (25000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal oscillator (CSI) default value. + * This value is the default CSI value after Reset. + */ +#if !defined (CSI_VALUE) + #define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */ +#define USE_SPI_CRC 0U /*!< use CRC in SPI */ + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */ +#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################### Ethernet Configuration ######################### */ +#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */ +#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */ + +#define ETH_MAC_ADDR0 (0x02UL) +#define ETH_MAC_ADDR1 (0x00UL) +#define ETH_MAC_ADDR2 (0x00UL) +#define ETH_MAC_ADDR3 (0x00UL) +#define ETH_MAC_ADDR4 (0x00UL) +#define ETH_MAC_ADDR5 (0x00UL) + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32h7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32h7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32h7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_MDMA_MODULE_ENABLED + #include "stm32h7xx_hal_mdma.h" +#endif /* HAL_MDMA_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32h7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32h7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32h7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32h7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32h7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED + #include "stm32h7xx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32h7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32h7xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32h7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32h7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + #include "stm32h7xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32h7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32h7xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED + #include "stm32h7xx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32h7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32h7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32h7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32h7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32h7xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_FMAC_MODULE_ENABLED + #include "stm32h7xx_hal_fmac.h" +#endif /* HAL_FMAC_MODULE_ENABLED */ + +#ifdef HAL_HRTIM_MODULE_ENABLED + #include "stm32h7xx_hal_hrtim.h" +#endif /* HAL_HRTIM_MODULE_ENABLED */ + +#ifdef HAL_HSEM_MODULE_ENABLED + #include "stm32h7xx_hal_hsem.h" +#endif /* HAL_HSEM_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32h7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32h7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32h7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32h7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32h7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32h7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32h7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32h7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32h7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32h7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED +#include "stm32h7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED +#include "stm32h7xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32h7xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + +#ifdef HAL_OTFDEC_MODULE_ENABLED +#include "stm32h7xx_hal_otfdec.h" +#endif /* HAL_OTFDEC_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32h7xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32h7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32h7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RAMECC_MODULE_ENABLED + #include "stm32h7xx_hal_ramecc.h" +#endif /* HAL_RAMECC_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32h7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32h7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32h7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32h7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32h7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32h7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32h7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SWPMI_MODULE_ENABLED + #include "stm32h7xx_hal_swpmi.h" +#endif /* HAL_SWPMI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32h7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32h7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32h7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32h7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32h7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32h7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32h7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32h7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32h7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_CONF_H */ diff --git a/board/Fire_STM32H743IIT6/BSP/Core/Inc/stm32h7xx_it.h b/board/Fire_STM32H743IIT6/BSP/Core/Inc/stm32h7xx_it.h new file mode 100644 index 000000000..7c8db8ac9 --- /dev/null +++ b/board/Fire_STM32H743IIT6/BSP/Core/Inc/stm32h7xx_it.h @@ -0,0 +1,68 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7xx_IT_H +#define __STM32H7xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void USART1_IRQHandler(void); +void USART2_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_IT_H */ diff --git a/board/Fire_STM32H743IIT6/BSP/Core/Inc/usart.h b/board/Fire_STM32H743IIT6/BSP/Core/Inc/usart.h new file mode 100644 index 000000000..a429df360 --- /dev/null +++ b/board/Fire_STM32H743IIT6/BSP/Core/Inc/usart.h @@ -0,0 +1,55 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.h + * @brief This file contains all the function prototypes for + * the usart.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USART_H__ +#define __USART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern UART_HandleTypeDef huart1; + +extern UART_HandleTypeDef huart2; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_USART1_UART_Init(void); +void MX_USART2_UART_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USART_H__ */ + diff --git a/board/Fire_STM32H743IIT6/BSP/Core/Src/gpio.c b/board/Fire_STM32H743IIT6/BSP/Core/Src/gpio.c new file mode 100644 index 000000000..605427a8b --- /dev/null +++ b/board/Fire_STM32H743IIT6/BSP/Core/Src/gpio.c @@ -0,0 +1,53 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** Configure pins + PC14-OSC32_IN (OSC32_IN) ------> RCC_OSC32_IN + PC15-OSC32_OUT (OSC32_OUT) ------> RCC_OSC32_OUT + PH0-OSC_IN (PH0) ------> RCC_OSC_IN + PH1-OSC_OUT (PH1) ------> RCC_OSC_OUT +*/ +void MX_GPIO_Init(void) +{ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ diff --git a/board/Fire_STM32H743IIT6/BSP/Core/Src/main.c b/board/Fire_STM32H743IIT6/BSP/Core/Src/main.c new file mode 100644 index 000000000..037a63a8b --- /dev/null +++ b/board/Fire_STM32H743IIT6/BSP/Core/Src/main.c @@ -0,0 +1,25 @@ +#include "mcu_init.h" + +#define APPLICATION_TASK_STK_SIZE 4096 +k_task_t application_task; +uint8_t application_task_stk[APPLICATION_TASK_STK_SIZE]; + +extern void application_entry(void *arg); + +__weak void application_entry(void *arg) +{ + while (1) { + printf("This is a demo task,please use your task entry!\r\n"); + tos_task_delay(1000); + } +} + +int main(void) +{ + board_init(); + printf("Welcome to TencentOS tiny(%s)\r\n", TOS_VERSION); + tos_knl_init(); // TencentOS Tiny kernel initialize + tos_task_create(&application_task, "application_task", application_entry, NULL, 4, application_task_stk, APPLICATION_TASK_STK_SIZE, 0); + tos_knl_start(); +} + diff --git a/board/Fire_STM32H743IIT6/BSP/Core/Src/mcu_init.c b/board/Fire_STM32H743IIT6/BSP/Core/Src/mcu_init.c new file mode 100644 index 000000000..bafad4abe --- /dev/null +++ b/board/Fire_STM32H743IIT6/BSP/Core/Src/mcu_init.c @@ -0,0 +1,157 @@ +#include "mcu_init.h" + +static void MPU_Config(void); + +int fputc(int ch, FILE *f) +{ + while((USART1->ISR & 0X40) == 0); + USART1->TDR = (uint8_t) ch; + return ch; +} + +int _write(int fd, char *ptr, int len) +{ + (void)HAL_UART_Transmit(&huart1, (uint8_t *)ptr, len, 0xFFFF); + return len; +} + +int fgetc(FILE *f) +{ + /* Place your implementation of fgetc here */ + /* e.g. readwrite a character to the USART2 and Loop until the end of transmission */ + uint8_t ch = 0; + HAL_UART_Receive(&huart1, &ch, 1,30000); + return ch; +} + +void board_init(void) +{ + MPU_Config(); + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + SystemClock_Config(); + + MX_GPIO_Init(); + MX_USART1_UART_Init(); + MX_USART2_UART_Init(); +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 10; + RCC_OscInitStruct.PLL.PLLN = 360; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) + { + Error_Handler(); + } +} + +/* MPU Configuration */ + +void MPU_Config(void) +{ + MPU_Region_InitTypeDef MPU_InitStruct = {0}; + + /* Disables the MPU */ + HAL_MPU_Disable(); + + /** Initializes and configures the Region and the memory to be protected + */ + MPU_InitStruct.Enable = MPU_REGION_ENABLE; + MPU_InitStruct.Number = MPU_REGION_NUMBER0; + MPU_InitStruct.BaseAddress = 0x0; + MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; + MPU_InitStruct.SubRegionDisable = 0x87; + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; + MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; + MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; + MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + /* Enables the MPU */ + HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); + +} + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/board/Fire_STM32H743IIT6/BSP/Core/Src/stm32h7xx_hal_msp.c b/board/Fire_STM32H743IIT6/BSP/Core/Src/stm32h7xx_hal_msp.c new file mode 100644 index 000000000..13f8ea67d --- /dev/null +++ b/board/Fire_STM32H743IIT6/BSP/Core/Src/stm32h7xx_hal_msp.c @@ -0,0 +1,80 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/board/Fire_STM32H743IIT6/BSP/Core/Src/stm32h7xx_it.c b/board/Fire_STM32H743IIT6/BSP/Core/Src/stm32h7xx_it.c new file mode 100644 index 000000000..efa626d03 --- /dev/null +++ b/board/Fire_STM32H743IIT6/BSP/Core/Src/stm32h7xx_it.c @@ -0,0 +1,238 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32h7xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "tos_k.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern UART_HandleTypeDef huart1; +extern UART_HandleTypeDef huart2; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +__weak void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + if (tos_knl_is_running()) { + tos_knl_irq_enter(); + tos_tick_handler(); + tos_knl_irq_leave(); + } + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32H7xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32h7xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles USART1 global interrupt. + */ +void USART1_IRQHandler(void) +{ + /* USER CODE BEGIN USART1_IRQn 0 */ + + /* USER CODE END USART1_IRQn 0 */ + HAL_UART_IRQHandler(&huart1); + /* USER CODE BEGIN USART1_IRQn 1 */ + + /* USER CODE END USART1_IRQn 1 */ +} + +/** + * @brief This function handles USART2 global interrupt. + */ +void USART2_IRQHandler(void) +{ + /* USER CODE BEGIN USART2_IRQn 0 */ + + /* USER CODE END USART2_IRQn 0 */ + HAL_UART_IRQHandler(&huart2); + /* USER CODE BEGIN USART2_IRQn 1 */ + + /* USER CODE END USART2_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/board/Fire_STM32H743IIT6/BSP/Core/Src/stm32h7xx_it_module.c b/board/Fire_STM32H743IIT6/BSP/Core/Src/stm32h7xx_it_module.c new file mode 100644 index 000000000..88bf541b4 --- /dev/null +++ b/board/Fire_STM32H743IIT6/BSP/Core/Src/stm32h7xx_it_module.c @@ -0,0 +1,246 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32h7xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "tos_k.h" +#include "tos_at.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern UART_HandleTypeDef huart1; +extern UART_HandleTypeDef huart2; +/* USER CODE BEGIN EV */ +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +__weak void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + if (tos_knl_is_running()) { + tos_knl_irq_enter(); + tos_tick_handler(); + tos_knl_irq_leave(); + } + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32H7xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32h7xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles USART1 global interrupt. + */ +void USART1_IRQHandler(void) +{ + /* USER CODE BEGIN USART1_IRQn 0 */ + + /* USER CODE END USART1_IRQn 0 */ + HAL_UART_IRQHandler(&huart1); + /* USER CODE BEGIN USART1_IRQn 1 */ + + /* USER CODE END USART1_IRQn 1 */ +} + +/** + * @brief This function handles USART2 global interrupt. + */ +void USART2_IRQHandler(void) +{ + /* USER CODE BEGIN USART2_IRQn 0 */ + tos_knl_irq_enter(); + /* USER CODE END USART2_IRQn 0 */ + HAL_UART_IRQHandler(&huart2); + /* USER CODE BEGIN USART2_IRQn 1 */ + tos_knl_irq_leave(); + /* USER CODE END USART2_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + extern uint8_t data; + + if (huart->Instance == USART2) { + HAL_UART_Receive_IT(&huart2, &data, 1); + tos_at_uart_input_byte(data); + } +} +/* USER CODE END 1 */ diff --git a/board/Fire_STM32H743IIT6/BSP/Core/Src/system_stm32h7xx.c b/board/Fire_STM32H743IIT6/BSP/Core/Src/system_stm32h7xx.c new file mode 100644 index 000000000..c99a7b1db --- /dev/null +++ b/board/Fire_STM32H743IIT6/BSP/Core/Src/system_stm32h7xx.c @@ -0,0 +1,450 @@ +/** + ****************************************************************************** + * @file system_stm32h7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock, it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32h7xx_system + * @{ + */ + +/** @addtogroup STM32H7xx_System_Private_Includes + * @{ + */ + +#include "stm32h7xx.h" +#include + +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */ +/* #define DATA_IN_D2_SRAM */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +#if defined(DUAL_CORE) && defined(CORE_CM4) +/*!< Uncomment the following line if you need to relocate your vector Table + in D2 AXI SRAM else user remap will be done in FLASH BANK2. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x300. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x300. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x300. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x300. */ +#endif /* VECT_TAB_SRAM */ +#else +/*!< Uncomment the following line if you need to relocate your vector Table + in D1 AXI SRAM else user remap will be done in FLASH BANK1. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x300. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x300. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x300. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x300. */ +#endif /* VECT_TAB_SRAM */ +#endif /* DUAL_CORE && CORE_CM4 */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 64000000; + uint32_t SystemD2Clock = 64000000; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting and vector table location + * configuration. + * @param None + * @retval None + */ +void SystemInit (void) +{ +#if defined (DATA_IN_D2_SRAM) + __IO uint32_t tmpreg; +#endif /* DATA_IN_D2_SRAM */ + + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + + /* Increasing the CPU frequency */ + if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } + + /* Set HSION bit */ + RCC->CR |= RCC_CR_HSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ + RCC->CR &= 0xEAF6ED7FU; + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } + +#if defined(D3_SRAM_BASE) + /* Reset D1CFGR register */ + RCC->D1CFGR = 0x00000000; + + /* Reset D2CFGR register */ + RCC->D2CFGR = 0x00000000; + + /* Reset D3CFGR register */ + RCC->D3CFGR = 0x00000000; +#else + /* Reset CDCFGR1 register */ + RCC->CDCFGR1 = 0x00000000; + + /* Reset CDCFGR2 register */ + RCC->CDCFGR2 = 0x00000000; + + /* Reset SRDCFGR register */ + RCC->SRDCFGR = 0x00000000; +#endif + /* Reset PLLCKSELR register */ + RCC->PLLCKSELR = 0x02020200; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x01FF0000; + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x01010280; + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000; + + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x01010280; + + /* Reset PLL2FRACR register */ + + RCC->PLL2FRACR = 0x00000000; + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x01010280; + + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + +#if (STM32H7_DEV_ID == 0x450UL) + /* dual core CM7 or single core line */ + if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) + { + /* if stm32h7 revY*/ + /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + *((__IO uint32_t*)0x51008108) = 0x000000001U; + } +#endif /* STM32H7_DEV_ID */ + +#if defined(DATA_IN_D2_SRAM) + /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); +#elif defined(RCC_AHB2ENR_D2SRAM2EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); +#else + RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); +#endif /* RCC_AHB2ENR_D2SRAM3EN */ + + tmpreg = RCC->AHB2ENR; + (void) tmpreg; +#endif /* DATA_IN_D2_SRAM */ + +#if defined(DUAL_CORE) && defined(CORE_CM4) + /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */ +#endif /* USER_VECT_TAB_ADDRESS */ + +#else + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ +#endif /* USER_VECT_TAB_ADDRESS */ + +#endif /*DUAL_CORE && CORE_CM4*/ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock , it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * + * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + uint32_t common_system_clock; + float_t fracn1, pllvco; + + + /* Get SYSCLK source -------------------------------------------------------*/ + + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + common_system_clock = CSI_VALUE; + break; + + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + common_system_clock = HSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; + pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + + if (pllm != 0U) + { + switch (pllsource) + { + case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ + + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + + break; + + case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + default: + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; + common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + } + else + { + common_system_clock = 0U; + } + break; + + default: + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + } + + /* Compute SystemClock frequency --------------------------------------------------*/ +#if defined (RCC_D1CFGR_D1CPRE) + tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; + + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; + + /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + +#else + tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]; + + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; + + /* SystemD2Clock frequency : AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); + +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/board/Fire_STM32H743IIT6/BSP/Core/Src/usart.c b/board/Fire_STM32H743IIT6/BSP/Core/Src/usart.c new file mode 100644 index 000000000..4cc1fd27a --- /dev/null +++ b/board/Fire_STM32H743IIT6/BSP/Core/Src/usart.c @@ -0,0 +1,247 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.c + * @brief This file provides code for the configuration + * of the USART instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "usart.h" + +/* USER CODE BEGIN 0 */ +uint8_t data; +/* USER CODE END 0 */ + +UART_HandleTypeDef huart1; +UART_HandleTypeDef huart2; + +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} +/* USART2 init function */ + +void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 115200; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ + HAL_UART_Receive_IT(&huart2, &data, 1); + /* USER CODE END USART2_Init 2 */ + +} + +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; + PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* USART1 clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USART1 interrupt Init */ + HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + else if(uartHandle->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART2; + PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* USART2 clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF7_USART2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USART2 interrupt Init */ + HAL_NVIC_SetPriority(USART2_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USART2_IRQn); + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } +} + +void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) +{ + + if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); + + /* USART1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + else if(uartHandle->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_3); + + /* USART2 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART2_IRQn); + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/board/Fire_STM32H743IIT6/BSP/TencentOS-Tiny.ioc b/board/Fire_STM32H743IIT6/BSP/TencentOS-Tiny.ioc new file mode 100644 index 000000000..642f38a6a --- /dev/null +++ b/board/Fire_STM32H743IIT6/BSP/TencentOS-Tiny.ioc @@ -0,0 +1,174 @@ +#MicroXplorer Configuration settings - do not modify +CORTEX_M7.IPParameters=default_mode_Activation +CORTEX_M7.default_mode_Activation=1 +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.CPN=STM32H743IIT6 +Mcu.Family=STM32H7 +Mcu.IP0=CORTEX_M7 +Mcu.IP1=NVIC +Mcu.IP2=RCC +Mcu.IP3=SYS +Mcu.IP4=USART1 +Mcu.IP5=USART2 +Mcu.IPNb=6 +Mcu.Name=STM32H743IITx +Mcu.Package=LQFP176 +Mcu.Pin0=PC14-OSC32_IN (OSC32_IN) +Mcu.Pin1=PC15-OSC32_OUT (OSC32_OUT) +Mcu.Pin2=PH0-OSC_IN (PH0) +Mcu.Pin3=PH1-OSC_OUT (PH1) +Mcu.Pin4=PA2 +Mcu.Pin5=PA3 +Mcu.Pin6=PA9 +Mcu.Pin7=PA10 +Mcu.Pin8=VP_SYS_VS_Systick +Mcu.PinsNb=9 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32H743IITx +MxCube.Version=6.5.0 +MxDb.Version=DB.6.0.50 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:true +NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true +NVIC.USART2_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true +PA10.Locked=true +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX +PA2.Mode=Asynchronous +PA2.Signal=USART2_TX +PA3.Mode=Asynchronous +PA3.Signal=USART2_RX +PA9.Locked=true +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PC14-OSC32_IN\ (OSC32_IN).Mode=LSE-External-Oscillator +PC14-OSC32_IN\ (OSC32_IN).Signal=RCC_OSC32_IN +PC15-OSC32_OUT\ (OSC32_OUT).Mode=LSE-External-Oscillator +PC15-OSC32_OUT\ (OSC32_OUT).Signal=RCC_OSC32_OUT +PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator +PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN +PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator +PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=true +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32H743IITx +ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.10.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=TencentOS-Tiny.ioc +ProjectManager.ProjectName=TencentOS-Tiny +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=MDK-ARM V5.27 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_USART2_UART_Init-USART2-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +RCC.ADCFreq_Value=50390625 +RCC.AHB12Freq_Value=225000000 +RCC.AHB4Freq_Value=225000000 +RCC.APB1Freq_Value=112500000 +RCC.APB2Freq_Value=112500000 +RCC.APB3Freq_Value=112500000 +RCC.APB4Freq_Value=112500000 +RCC.AXIClockFreq_Value=225000000 +RCC.CECFreq_Value=32000 +RCC.CKPERFreq_Value=64000000 +RCC.CortexFreq_Value=450000000 +RCC.CpuClockFreq_Value=450000000 +RCC.D1CPREFreq_Value=450000000 +RCC.D1PPRE=RCC_APB3_DIV2 +RCC.D2PPRE1=RCC_APB1_DIV2 +RCC.D2PPRE2=RCC_APB2_DIV2 +RCC.D3PPRE=RCC_APB4_DIV2 +RCC.DFSDMACLkFreq_Value=450000000 +RCC.DFSDMFreq_Value=112500000 +RCC.DIVM1=10 +RCC.DIVN1=360 +RCC.DIVP1Freq_Value=450000000 +RCC.DIVP2Freq_Value=50390625 +RCC.DIVP3Freq_Value=50390625 +RCC.DIVQ1Freq_Value=450000000 +RCC.DIVQ2Freq_Value=50390625 +RCC.DIVQ3Freq_Value=50390625 +RCC.DIVR1Freq_Value=450000000 +RCC.DIVR2Freq_Value=50390625 +RCC.DIVR3Freq_Value=50390625 +RCC.FDCANFreq_Value=450000000 +RCC.FMCFreq_Value=225000000 +RCC.FamilyName=M +RCC.HCLK3ClockFreq_Value=225000000 +RCC.HCLKFreq_Value=225000000 +RCC.HPRE=RCC_HCLK_DIV2 +RCC.HRTIMFreq_Value=225000000 +RCC.I2C123Freq_Value=112500000 +RCC.I2C4Freq_Value=112500000 +RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVN1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value +RCC.LPTIM1Freq_Value=112500000 +RCC.LPTIM2Freq_Value=112500000 +RCC.LPTIM345Freq_Value=112500000 +RCC.LPUART1Freq_Value=112500000 +RCC.LTDCFreq_Value=50390625 +RCC.MCO1PinFreq_Value=64000000 +RCC.MCO2PinFreq_Value=450000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.QSPIFreq_Value=225000000 +RCC.RNGFreq_Value=48000000 +RCC.RTCFreq_Value=32000 +RCC.SAI1Freq_Value=450000000 +RCC.SAI23Freq_Value=450000000 +RCC.SAI4AFreq_Value=450000000 +RCC.SAI4BFreq_Value=450000000 +RCC.SDMMCFreq_Value=450000000 +RCC.SPDIFRXFreq_Value=450000000 +RCC.SPI123Freq_Value=450000000 +RCC.SPI45Freq_Value=112500000 +RCC.SPI6Freq_Value=112500000 +RCC.SWPMI1Freq_Value=112500000 +RCC.SYSCLKFreq_VALUE=450000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.Tim1OutputFreq_Value=225000000 +RCC.Tim2OutputFreq_Value=225000000 +RCC.TraceFreq_Value=64000000 +RCC.USART16Freq_Value=112500000 +RCC.USART234578Freq_Value=112500000 +RCC.USBFreq_Value=450000000 +RCC.VCO1OutputFreq_Value=900000000 +RCC.VCO2OutputFreq_Value=100781250 +RCC.VCO3OutputFreq_Value=100781250 +RCC.VCOInput1Freq_Value=2500000 +RCC.VCOInput2Freq_Value=781250 +RCC.VCOInput3Freq_Value=781250 +USART1.IPParameters=VirtualMode-Asynchronous +USART1.VirtualMode-Asynchronous=VM_ASYNC +USART2.IPParameters=VirtualMode-Asynchronous +USART2.VirtualMode-Asynchronous=VM_ASYNC +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom diff --git a/board/Fire_STM32H743IIT6/KEIL/hello_world/TencentOS-Tiny.uvoptx b/board/Fire_STM32H743IIT6/KEIL/hello_world/TencentOS-Tiny.uvoptx new file mode 100644 index 000000000..3b89a50df --- /dev/null +++ b/board/Fire_STM32H743IIT6/KEIL/hello_world/TencentOS-Tiny.uvoptx @@ -0,0 +1,1828 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + TencentOS-Tiny + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048 -FS08000000 -FL0200000 -FP0($$Device:STM32H743IITx$CMSIS\Flash\STM32H7x_2048.FLM)) + + + 0 + ST-LINKIII-KEIL_SWO + -U48FF70067084554817342567 -O2254 -SF400000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(6BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H743IITx$CMSIS\Flash\STM32H7x_2048.FLM) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 0 + 0 + 0 + 2 + 400000000 + + + + + + Application/MDK-ARM + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + startup_stm32h743xx.s + startup_stm32h743xx.s + 0 + 0 + + + + + Application/User/Core + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\BSP\Core\Src\gpio.c + gpio.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\BSP\Core\Src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\BSP\Core\Src\stm32h7xx_hal_msp.c + stm32h7xx_hal_msp.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\BSP\Core\Src\stm32h7xx_it.c + stm32h7xx_it.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\BSP\Core\Src\usart.c + usart.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\..\BSP\Core\Src\mcu_init.c + mcu_init.c + 0 + 0 + + + + + Drivers/STM32H7xx_HAL_Driver + 0 + 0 + 0 + 0 + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c + stm32h7xx_hal.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc.c + stm32h7xx_hal_adc.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc_ex.c + stm32h7xx_hal_adc_ex.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cec.c + stm32h7xx_hal_cec.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_comp.c + stm32h7xx_hal_comp.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cordic.c + stm32h7xx_hal_cordic.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c + stm32h7xx_hal_cortex.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc.c + stm32h7xx_hal_crc.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc_ex.c + stm32h7xx_hal_crc_ex.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp.c + stm32h7xx_hal_cryp.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp_ex.c + stm32h7xx_hal_cryp_ex.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac.c + stm32h7xx_hal_dac.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac_ex.c + stm32h7xx_hal_dac_ex.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dcmi.c + stm32h7xx_hal_dcmi.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dfsdm.c + stm32h7xx_hal_dfsdm.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dfsdm_ex.c + stm32h7xx_hal_dfsdm_ex.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c + stm32h7xx_hal_dma.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c + stm32h7xx_hal_dma_ex.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma2d.c + stm32h7xx_hal_dma2d.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dsi.c + stm32h7xx_hal_dsi.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dts.c + stm32h7xx_hal_dts.c + 0 + 0 + + + 3 + 29 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_eth.c + stm32h7xx_hal_eth.c + 0 + 0 + + + 3 + 30 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_eth_ex.c + stm32h7xx_hal_eth_ex.c + 0 + 0 + + + 3 + 31 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c + stm32h7xx_hal_exti.c + 0 + 0 + + + 3 + 32 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c + stm32h7xx_hal_fdcan.c + 0 + 0 + + + 3 + 33 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c + stm32h7xx_hal_flash.c + 0 + 0 + + + 3 + 34 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c + stm32h7xx_hal_flash_ex.c + 0 + 0 + + + 3 + 35 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fmac.c + stm32h7xx_hal_fmac.c + 0 + 0 + + + 3 + 36 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gfxmmu.c + stm32h7xx_hal_gfxmmu.c + 0 + 0 + + + 3 + 37 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c + stm32h7xx_hal_gpio.c + 0 + 0 + + + 3 + 38 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hash.c + stm32h7xx_hal_hash.c + 0 + 0 + + + 3 + 39 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hash_ex.c + stm32h7xx_hal_hash_ex.c + 0 + 0 + + + 3 + 40 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hcd.c + stm32h7xx_hal_hcd.c + 0 + 0 + + + 3 + 41 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hrtim.c + stm32h7xx_hal_hrtim.c + 0 + 0 + + + 3 + 42 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c + stm32h7xx_hal_hsem.c + 0 + 0 + + + 3 + 43 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c + stm32h7xx_hal_i2c.c + 0 + 0 + + + 3 + 44 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c + stm32h7xx_hal_i2c_ex.c + 0 + 0 + + + 3 + 45 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2s.c + stm32h7xx_hal_i2s.c + 0 + 0 + + + 3 + 46 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2s_ex.c + stm32h7xx_hal_i2s_ex.c + 0 + 0 + + + 3 + 47 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_irda.c + stm32h7xx_hal_irda.c + 0 + 0 + + + 3 + 48 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_iwdg.c + stm32h7xx_hal_iwdg.c + 0 + 0 + + + 3 + 49 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_jpeg.c + stm32h7xx_hal_jpeg.c + 0 + 0 + + + 3 + 50 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_lptim.c + stm32h7xx_hal_lptim.c + 0 + 0 + + + 3 + 51 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ltdc.c + stm32h7xx_hal_ltdc.c + 0 + 0 + + + 3 + 52 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ltdc_ex.c + stm32h7xx_hal_ltdc_ex.c + 0 + 0 + + + 3 + 53 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdios.c + stm32h7xx_hal_mdios.c + 0 + 0 + + + 3 + 54 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c + stm32h7xx_hal_mdma.c + 0 + 0 + + + 3 + 55 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc.c + stm32h7xx_hal_mmc.c + 0 + 0 + + + 3 + 56 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc_ex.c + stm32h7xx_hal_mmc_ex.c + 0 + 0 + + + 3 + 57 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nand.c + stm32h7xx_hal_nand.c + 0 + 0 + + + 3 + 58 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nor.c + stm32h7xx_hal_nor.c + 0 + 0 + + + 3 + 59 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_opamp.c + stm32h7xx_hal_opamp.c + 0 + 0 + + + 3 + 60 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_opamp_ex.c + stm32h7xx_hal_opamp_ex.c + 0 + 0 + + + 3 + 61 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ospi.c + stm32h7xx_hal_ospi.c + 0 + 0 + + + 3 + 62 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_otfdec.c + stm32h7xx_hal_otfdec.c + 0 + 0 + + + 3 + 63 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd.c + stm32h7xx_hal_pcd.c + 0 + 0 + + + 3 + 64 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd_ex.c + stm32h7xx_hal_pcd_ex.c + 0 + 0 + + + 3 + 65 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pssi.c + stm32h7xx_hal_pssi.c + 0 + 0 + + + 3 + 66 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c + stm32h7xx_hal_pwr.c + 0 + 0 + + + 3 + 67 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c + stm32h7xx_hal_pwr_ex.c + 0 + 0 + + + 3 + 68 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_qspi.c + stm32h7xx_hal_qspi.c + 0 + 0 + + + 3 + 69 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ramecc.c + stm32h7xx_hal_ramecc.c + 0 + 0 + + + 3 + 70 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c + stm32h7xx_hal_rcc.c + 0 + 0 + + + 3 + 71 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c + stm32h7xx_hal_rcc_ex.c + 0 + 0 + + + 3 + 72 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rng.c + stm32h7xx_hal_rng.c + 0 + 0 + + + 3 + 73 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rng_ex.c + stm32h7xx_hal_rng_ex.c + 0 + 0 + + + 3 + 74 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rtc.c + stm32h7xx_hal_rtc.c + 0 + 0 + + + 3 + 75 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rtc_ex.c + stm32h7xx_hal_rtc_ex.c + 0 + 0 + + + 3 + 76 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sai.c + stm32h7xx_hal_sai.c + 0 + 0 + + + 3 + 77 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sai_ex.c + stm32h7xx_hal_sai_ex.c + 0 + 0 + + + 3 + 78 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd.c + stm32h7xx_hal_sd.c + 0 + 0 + + + 3 + 79 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd_ex.c + stm32h7xx_hal_sd_ex.c + 0 + 0 + + + 3 + 80 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sdram.c + stm32h7xx_hal_sdram.c + 0 + 0 + + + 3 + 81 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smartcard.c + stm32h7xx_hal_smartcard.c + 0 + 0 + + + 3 + 82 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smartcard_ex.c + stm32h7xx_hal_smartcard_ex.c + 0 + 0 + + + 3 + 83 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smbus.c + stm32h7xx_hal_smbus.c + 0 + 0 + + + 3 + 84 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smbus_ex.c + stm32h7xx_hal_smbus_ex.c + 0 + 0 + + + 3 + 85 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spdifrx.c + stm32h7xx_hal_spdifrx.c + 0 + 0 + + + 3 + 86 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c + stm32h7xx_hal_spi.c + 0 + 0 + + + 3 + 87 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi_ex.c + stm32h7xx_hal_spi_ex.c + 0 + 0 + + + 3 + 88 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sram.c + stm32h7xx_hal_sram.c + 0 + 0 + + + 3 + 89 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_swpmi.c + stm32h7xx_hal_swpmi.c + 0 + 0 + + + 3 + 90 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c + stm32h7xx_hal_tim.c + 0 + 0 + + + 3 + 91 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c + stm32h7xx_hal_tim_ex.c + 0 + 0 + + + 3 + 92 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c + stm32h7xx_hal_uart.c + 0 + 0 + + + 3 + 93 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c + stm32h7xx_hal_uart_ex.c + 0 + 0 + + + 3 + 94 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_usart.c + stm32h7xx_hal_usart.c + 0 + 0 + + + 3 + 95 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_usart_ex.c + stm32h7xx_hal_usart_ex.c + 0 + 0 + + + 3 + 96 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_wwdg.c + stm32h7xx_hal_wwdg.c + 0 + 0 + + + + + Drivers/CMSIS + 0 + 0 + 0 + 0 + + 4 + 97 + 1 + 0 + 0 + 0 + ..\..\BSP\Core\Src\system_stm32h7xx.c + system_stm32h7xx.c + 0 + 0 + + + + + tos/arch + 0 + 0 + 0 + 0 + + 5 + 98 + 1 + 0 + 0 + 0 + ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c + tos_cpu.c + 0 + 0 + + + 5 + 99 + 1 + 0 + 0 + 0 + ..\..\..\..\arch\arm\arm-v7m\common\tos_fault.c + tos_fault.c + 0 + 0 + + + 5 + 100 + 1 + 0 + 0 + 0 + ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_c.c + port_c.c + 0 + 0 + + + 5 + 101 + 2 + 0 + 0 + 0 + ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_s.S + port_s.S + 0 + 0 + + + + + tos/kernel + 0 + 0 + 0 + 0 + + 6 + 102 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_barrier.c + tos_barrier.c + 0 + 0 + + + 6 + 103 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_binary_heap.c + tos_binary_heap.c + 0 + 0 + + + 6 + 104 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_bitmap.c + tos_bitmap.c + 0 + 0 + + + 6 + 105 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_char_fifo.c + tos_char_fifo.c + 0 + 0 + + + 6 + 106 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_completion.c + tos_completion.c + 0 + 0 + + + 6 + 107 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_countdownlatch.c + tos_countdownlatch.c + 0 + 0 + + + 6 + 108 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_event.c + tos_event.c + 0 + 0 + + + 6 + 109 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_global.c + tos_global.c + 0 + 0 + + + 6 + 110 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_mail_queue.c + tos_mail_queue.c + 0 + 0 + + + 6 + 111 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_message_queue.c + tos_message_queue.c + 0 + 0 + + + 6 + 112 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_mmblk.c + tos_mmblk.c + 0 + 0 + + + 6 + 113 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_mmheap.c + tos_mmheap.c + 0 + 0 + + + 6 + 114 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_mutex.c + tos_mutex.c + 0 + 0 + + + 6 + 115 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_pend.c + tos_pend.c + 0 + 0 + + + 6 + 116 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_priority_mail_queue.c + tos_priority_mail_queue.c + 0 + 0 + + + 6 + 117 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_priority_message_queue.c + tos_priority_message_queue.c + 0 + 0 + + + 6 + 118 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_priority_queue.c + tos_priority_queue.c + 0 + 0 + + + 6 + 119 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_ring_queue.c + tos_ring_queue.c + 0 + 0 + + + 6 + 120 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_robin.c + tos_robin.c + 0 + 0 + + + 6 + 121 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_rwlock.c + tos_rwlock.c + 0 + 0 + + + 6 + 122 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_sched.c + tos_sched.c + 0 + 0 + + + 6 + 123 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_sem.c + tos_sem.c + 0 + 0 + + + 6 + 124 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_stopwatch.c + tos_stopwatch.c + 0 + 0 + + + 6 + 125 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_sys.c + tos_sys.c + 0 + 0 + + + 6 + 126 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_task.c + tos_task.c + 0 + 0 + + + 6 + 127 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_tick.c + tos_tick.c + 0 + 0 + + + 6 + 128 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_time.c + tos_time.c + 0 + 0 + + + 6 + 129 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_timer.c + tos_timer.c + 0 + 0 + + + + + tos/config + 0 + 0 + 0 + 0 + + 7 + 130 + 5 + 0 + 0 + 0 + ..\..\TOS_CONFIG\tos_config.h + tos_config.h + 0 + 0 + + + + + example + 0 + 0 + 0 + 0 + + 8 + 131 + 1 + 0 + 0 + 0 + ..\..\..\..\examples\hello_world\hello_world.c + hello_world.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + +
diff --git a/board/Fire_STM32H743IIT6/KEIL/hello_world/TencentOS-Tiny.uvprojx b/board/Fire_STM32H743IIT6/KEIL/hello_world/TencentOS-Tiny.uvprojx new file mode 100644 index 000000000..4329e1674 --- /dev/null +++ b/board/Fire_STM32H743IIT6/KEIL/hello_world/TencentOS-Tiny.uvprojx @@ -0,0 +1,1113 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + TencentOS-Tiny + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + STM32H743IITx + STMicroelectronics + Keil.STM32H7xx_DFP.3.0.0 + http://www.keil.com/pack/ + IRAM(0x20000000-0x2001FFFF) IRAM2(0x24000000-0x2407FFFF) IROM(0x8000000-0x81FFFFF) CLOCK(12000000) FPU3(DFPU) CPUTYPE("Cortex-M7") ELITTLE TZ + + + + 0 + + + + + + + + + + + $$Device:STM32H743IITx$CMSIS\SVD\STM32H743.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + TencentOS-Tiny\ + TencentOS-Tiny + 1 + 0 + 1 + 1 + 0 + + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x200000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x24000000 + 0x80000 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 1 + 0 + 5 + 3 + 1 + 1 + 0 + 0 + 0 + + + USE_HAL_DRIVER,STM32H743xx + + ..\..\BSP\Core\Inc;..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Inc;..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Inc\Legacy;..\..\..\..\platform\vendor_bsp\st\CMSIS\Device\ST\STM32H7xx\Include;..\..\..\..\platform\vendor_bsp\st\CMSIS\Include;..\..\..\..\arch\arm\arm-v7m\common\include;..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc;..\..\..\..\kernel\core\include;..\..\TOS_CONFIG + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + + + + + + + + + + + + + + + Application/MDK-ARM + + + startup_stm32h743xx.s + 2 + startup_stm32h743xx.s + + + + + Application/User/Core + + + gpio.c + 1 + ..\..\BSP\Core\Src\gpio.c + + + main.c + 1 + ..\..\BSP\Core\Src\main.c + + + stm32h7xx_hal_msp.c + 1 + ..\..\BSP\Core\Src\stm32h7xx_hal_msp.c + + + stm32h7xx_it.c + 1 + ..\..\BSP\Core\Src\stm32h7xx_it.c + + + usart.c + 1 + ..\..\BSP\Core\Src\usart.c + + + mcu_init.c + 1 + ..\..\BSP\Core\Src\mcu_init.c + + + + + Drivers/STM32H7xx_HAL_Driver + + + stm32h7xx_hal.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c + + + stm32h7xx_hal_adc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc.c + + + stm32h7xx_hal_adc_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc_ex.c + + + stm32h7xx_hal_cec.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cec.c + + + stm32h7xx_hal_comp.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_comp.c + + + stm32h7xx_hal_cordic.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cordic.c + + + stm32h7xx_hal_cortex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c + + + stm32h7xx_hal_crc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc.c + + + stm32h7xx_hal_crc_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc_ex.c + + + stm32h7xx_hal_cryp.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp.c + + + stm32h7xx_hal_cryp_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp_ex.c + + + stm32h7xx_hal_dac.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac.c + + + stm32h7xx_hal_dac_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac_ex.c + + + stm32h7xx_hal_dcmi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dcmi.c + + + stm32h7xx_hal_dfsdm.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dfsdm.c + + + stm32h7xx_hal_dfsdm_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dfsdm_ex.c + + + stm32h7xx_hal_dma.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c + + + stm32h7xx_hal_dma_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c + + + stm32h7xx_hal_dma2d.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma2d.c + + + stm32h7xx_hal_dsi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dsi.c + + + stm32h7xx_hal_dts.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dts.c + + + stm32h7xx_hal_eth.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_eth.c + + + stm32h7xx_hal_eth_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_eth_ex.c + + + stm32h7xx_hal_exti.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c + + + stm32h7xx_hal_fdcan.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c + + + stm32h7xx_hal_flash.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c + + + stm32h7xx_hal_flash_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c + + + stm32h7xx_hal_fmac.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fmac.c + + + stm32h7xx_hal_gfxmmu.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gfxmmu.c + + + stm32h7xx_hal_gpio.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c + + + stm32h7xx_hal_hash.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hash.c + + + stm32h7xx_hal_hash_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hash_ex.c + + + stm32h7xx_hal_hcd.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hcd.c + + + stm32h7xx_hal_hrtim.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hrtim.c + + + stm32h7xx_hal_hsem.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c + + + stm32h7xx_hal_i2c.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c + + + stm32h7xx_hal_i2c_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c + + + stm32h7xx_hal_i2s.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2s.c + + + stm32h7xx_hal_i2s_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2s_ex.c + + + stm32h7xx_hal_irda.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_irda.c + + + stm32h7xx_hal_iwdg.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_iwdg.c + + + stm32h7xx_hal_jpeg.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_jpeg.c + + + stm32h7xx_hal_lptim.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_lptim.c + + + stm32h7xx_hal_ltdc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ltdc.c + + + stm32h7xx_hal_ltdc_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ltdc_ex.c + + + stm32h7xx_hal_mdios.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdios.c + + + stm32h7xx_hal_mdma.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c + + + stm32h7xx_hal_mmc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc.c + + + stm32h7xx_hal_mmc_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc_ex.c + + + stm32h7xx_hal_nand.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nand.c + + + stm32h7xx_hal_nor.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nor.c + + + stm32h7xx_hal_opamp.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_opamp.c + + + stm32h7xx_hal_opamp_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_opamp_ex.c + + + stm32h7xx_hal_ospi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ospi.c + + + stm32h7xx_hal_otfdec.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_otfdec.c + + + stm32h7xx_hal_pcd.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd.c + + + stm32h7xx_hal_pcd_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd_ex.c + + + stm32h7xx_hal_pssi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pssi.c + + + stm32h7xx_hal_pwr.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c + + + stm32h7xx_hal_pwr_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c + + + stm32h7xx_hal_qspi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_qspi.c + + + stm32h7xx_hal_ramecc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ramecc.c + + + stm32h7xx_hal_rcc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c + + + stm32h7xx_hal_rcc_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c + + + stm32h7xx_hal_rng.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rng.c + + + stm32h7xx_hal_rng_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rng_ex.c + + + stm32h7xx_hal_rtc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rtc.c + + + stm32h7xx_hal_rtc_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rtc_ex.c + + + stm32h7xx_hal_sai.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sai.c + + + stm32h7xx_hal_sai_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sai_ex.c + + + stm32h7xx_hal_sd.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd.c + + + stm32h7xx_hal_sd_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd_ex.c + + + stm32h7xx_hal_sdram.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sdram.c + + + stm32h7xx_hal_smartcard.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smartcard.c + + + stm32h7xx_hal_smartcard_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smartcard_ex.c + + + stm32h7xx_hal_smbus.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smbus.c + + + stm32h7xx_hal_smbus_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smbus_ex.c + + + stm32h7xx_hal_spdifrx.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spdifrx.c + + + stm32h7xx_hal_spi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c + + + stm32h7xx_hal_spi_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi_ex.c + + + stm32h7xx_hal_sram.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sram.c + + + stm32h7xx_hal_swpmi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_swpmi.c + + + stm32h7xx_hal_tim.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c + + + stm32h7xx_hal_tim_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c + + + stm32h7xx_hal_uart.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c + + + stm32h7xx_hal_uart_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c + + + stm32h7xx_hal_usart.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_usart.c + + + stm32h7xx_hal_usart_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_usart_ex.c + + + stm32h7xx_hal_wwdg.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_wwdg.c + + + + + Drivers/CMSIS + + + system_stm32h7xx.c + 1 + ..\..\BSP\Core\Src\system_stm32h7xx.c + + + + + tos/arch + + + tos_cpu.c + 1 + ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c + + + tos_fault.c + 1 + ..\..\..\..\arch\arm\arm-v7m\common\tos_fault.c + + + port_c.c + 1 + ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_c.c + + + port_s.S + 2 + ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_s.S + + + + + tos/kernel + + + tos_barrier.c + 1 + ..\..\..\..\kernel\core\tos_barrier.c + + + tos_binary_heap.c + 1 + ..\..\..\..\kernel\core\tos_binary_heap.c + + + tos_bitmap.c + 1 + ..\..\..\..\kernel\core\tos_bitmap.c + + + tos_char_fifo.c + 1 + ..\..\..\..\kernel\core\tos_char_fifo.c + + + tos_completion.c + 1 + ..\..\..\..\kernel\core\tos_completion.c + + + tos_countdownlatch.c + 1 + ..\..\..\..\kernel\core\tos_countdownlatch.c + + + tos_event.c + 1 + ..\..\..\..\kernel\core\tos_event.c + + + tos_global.c + 1 + ..\..\..\..\kernel\core\tos_global.c + + + tos_mail_queue.c + 1 + ..\..\..\..\kernel\core\tos_mail_queue.c + + + tos_message_queue.c + 1 + ..\..\..\..\kernel\core\tos_message_queue.c + + + tos_mmblk.c + 1 + ..\..\..\..\kernel\core\tos_mmblk.c + + + tos_mmheap.c + 1 + ..\..\..\..\kernel\core\tos_mmheap.c + + + tos_mutex.c + 1 + ..\..\..\..\kernel\core\tos_mutex.c + + + tos_pend.c + 1 + ..\..\..\..\kernel\core\tos_pend.c + + + tos_priority_mail_queue.c + 1 + ..\..\..\..\kernel\core\tos_priority_mail_queue.c + + + tos_priority_message_queue.c + 1 + ..\..\..\..\kernel\core\tos_priority_message_queue.c + + + tos_priority_queue.c + 1 + ..\..\..\..\kernel\core\tos_priority_queue.c + + + tos_ring_queue.c + 1 + ..\..\..\..\kernel\core\tos_ring_queue.c + + + tos_robin.c + 1 + ..\..\..\..\kernel\core\tos_robin.c + + + tos_rwlock.c + 1 + ..\..\..\..\kernel\core\tos_rwlock.c + + + tos_sched.c + 1 + ..\..\..\..\kernel\core\tos_sched.c + + + tos_sem.c + 1 + ..\..\..\..\kernel\core\tos_sem.c + + + tos_stopwatch.c + 1 + ..\..\..\..\kernel\core\tos_stopwatch.c + + + tos_sys.c + 1 + ..\..\..\..\kernel\core\tos_sys.c + + + tos_task.c + 1 + ..\..\..\..\kernel\core\tos_task.c + + + tos_tick.c + 1 + ..\..\..\..\kernel\core\tos_tick.c + + + tos_time.c + 1 + ..\..\..\..\kernel\core\tos_time.c + + + tos_timer.c + 1 + ..\..\..\..\kernel\core\tos_timer.c + + + + + tos/config + + + tos_config.h + 5 + ..\..\TOS_CONFIG\tos_config.h + + + + + example + + + hello_world.c + 1 + ..\..\..\..\examples\hello_world\hello_world.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + +
diff --git a/board/Fire_STM32H743IIT6/KEIL/hello_world/startup_stm32h743xx.s b/board/Fire_STM32H743IIT6/KEIL/hello_world/startup_stm32h743xx.s new file mode 100644 index 000000000..aed79afe3 --- /dev/null +++ b/board/Fire_STM32H743IIT6/KEIL/hello_world/startup_stm32h743xx.s @@ -0,0 +1,609 @@ +;******************************************************************************** +;* File Name : startup_stm32h743xx.s +;* @author MCD Application Team +;* Description : STM32H7xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2017 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_AVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT FDCAN_CAL_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT HRTIM1_Master_IRQHandler [WEAK] + EXPORT HRTIM1_TIMA_IRQHandler [WEAK] + EXPORT HRTIM1_TIMB_IRQHandler [WEAK] + EXPORT HRTIM1_TIMC_IRQHandler [WEAK] + EXPORT HRTIM1_TIMD_IRQHandler [WEAK] + EXPORT HRTIM1_TIME_IRQHandler [WEAK] + EXPORT HRTIM1_FLT_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SAI3_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT MDIOS_WKUP_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT MDMA_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT HSEM1_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT DMAMUX2_OVR_IRQHandler [WEAK] + EXPORT BDMA_Channel0_IRQHandler [WEAK] + EXPORT BDMA_Channel1_IRQHandler [WEAK] + EXPORT BDMA_Channel2_IRQHandler [WEAK] + EXPORT BDMA_Channel3_IRQHandler [WEAK] + EXPORT BDMA_Channel4_IRQHandler [WEAK] + EXPORT BDMA_Channel5_IRQHandler [WEAK] + EXPORT BDMA_Channel6_IRQHandler [WEAK] + EXPORT BDMA_Channel7_IRQHandler [WEAK] + EXPORT COMP1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT ECC_IRQHandler [WEAK] + EXPORT SAI4_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_AVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +FDCAN_CAL_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +OTG_FS_EP1_OUT_IRQHandler +OTG_FS_EP1_IN_IRQHandler +OTG_FS_WKUP_IRQHandler +OTG_FS_IRQHandler +DMAMUX1_OVR_IRQHandler +HRTIM1_Master_IRQHandler +HRTIM1_TIMA_IRQHandler +HRTIM1_TIMB_IRQHandler +HRTIM1_TIMC_IRQHandler +HRTIM1_TIMD_IRQHandler +HRTIM1_TIME_IRQHandler +HRTIM1_FLT_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SAI3_IRQHandler +SWPMI1_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +MDIOS_WKUP_IRQHandler +MDIOS_IRQHandler +JPEG_IRQHandler +MDMA_IRQHandler +SDMMC2_IRQHandler +HSEM1_IRQHandler +ADC3_IRQHandler +DMAMUX2_OVR_IRQHandler +BDMA_Channel0_IRQHandler +BDMA_Channel1_IRQHandler +BDMA_Channel2_IRQHandler +BDMA_Channel3_IRQHandler +BDMA_Channel4_IRQHandler +BDMA_Channel5_IRQHandler +BDMA_Channel6_IRQHandler +BDMA_Channel7_IRQHandler +COMP1_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +LPUART1_IRQHandler +CRS_IRQHandler +ECC_IRQHandler +SAI4_IRQHandler +WAKEUP_PIN_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/board/Fire_STM32H743IIT6/KEIL/mqtt_client_iot_exporer/TencentOS-Tiny.uvoptx b/board/Fire_STM32H743IIT6/KEIL/mqtt_client_iot_exporer/TencentOS-Tiny.uvoptx new file mode 100644 index 000000000..001291faa --- /dev/null +++ b/board/Fire_STM32H743IIT6/KEIL/mqtt_client_iot_exporer/TencentOS-Tiny.uvoptx @@ -0,0 +1,2232 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + TencentOS-Tiny + 0x4 + ARM-ADS + + 25000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048 -FS08000000 -FL0200000 -FP0($$Device:STM32H743IITx$CMSIS\Flash\STM32H7x_2048.FLM)) + + + 0 + ST-LINKIII-KEIL_SWO + -U48FF70067084554817342567 -O2254 -SF400000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(6BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H743IITx$CMSIS\Flash\STM32H7x_2048.FLM) + + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 0 + 0 + 0 + 2 + 400000000 + + + + + + Application/MDK-ARM + 0 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + startup_stm32h743xx.s + startup_stm32h743xx.s + 0 + 0 + + + + + Application/User/Core + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\BSP\Core\Src\gpio.c + gpio.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\BSP\Core\Src\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\BSP\Core\Src\stm32h7xx_hal_msp.c + stm32h7xx_hal_msp.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\BSP\Core\Src\usart.c + usart.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\BSP\Core\Src\mcu_init.c + mcu_init.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\..\BSP\Core\Src\stm32h7xx_it_module.c + stm32h7xx_it_module.c + 0 + 0 + + + + + Drivers/STM32H7xx_HAL_Driver + 0 + 0 + 0 + 0 + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c + stm32h7xx_hal.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc.c + stm32h7xx_hal_adc.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc_ex.c + stm32h7xx_hal_adc_ex.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cec.c + stm32h7xx_hal_cec.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_comp.c + stm32h7xx_hal_comp.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cordic.c + stm32h7xx_hal_cordic.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c + stm32h7xx_hal_cortex.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc.c + stm32h7xx_hal_crc.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc_ex.c + stm32h7xx_hal_crc_ex.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp.c + stm32h7xx_hal_cryp.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp_ex.c + stm32h7xx_hal_cryp_ex.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac.c + stm32h7xx_hal_dac.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac_ex.c + stm32h7xx_hal_dac_ex.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dcmi.c + stm32h7xx_hal_dcmi.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dfsdm.c + stm32h7xx_hal_dfsdm.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dfsdm_ex.c + stm32h7xx_hal_dfsdm_ex.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c + stm32h7xx_hal_dma.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c + stm32h7xx_hal_dma_ex.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma2d.c + stm32h7xx_hal_dma2d.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dsi.c + stm32h7xx_hal_dsi.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dts.c + stm32h7xx_hal_dts.c + 0 + 0 + + + 3 + 29 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_eth.c + stm32h7xx_hal_eth.c + 0 + 0 + + + 3 + 30 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_eth_ex.c + stm32h7xx_hal_eth_ex.c + 0 + 0 + + + 3 + 31 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c + stm32h7xx_hal_exti.c + 0 + 0 + + + 3 + 32 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c + stm32h7xx_hal_fdcan.c + 0 + 0 + + + 3 + 33 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c + stm32h7xx_hal_flash.c + 0 + 0 + + + 3 + 34 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c + stm32h7xx_hal_flash_ex.c + 0 + 0 + + + 3 + 35 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fmac.c + stm32h7xx_hal_fmac.c + 0 + 0 + + + 3 + 36 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gfxmmu.c + stm32h7xx_hal_gfxmmu.c + 0 + 0 + + + 3 + 37 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c + stm32h7xx_hal_gpio.c + 0 + 0 + + + 3 + 38 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hash.c + stm32h7xx_hal_hash.c + 0 + 0 + + + 3 + 39 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hash_ex.c + stm32h7xx_hal_hash_ex.c + 0 + 0 + + + 3 + 40 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hcd.c + stm32h7xx_hal_hcd.c + 0 + 0 + + + 3 + 41 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hrtim.c + stm32h7xx_hal_hrtim.c + 0 + 0 + + + 3 + 42 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c + stm32h7xx_hal_hsem.c + 0 + 0 + + + 3 + 43 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c + stm32h7xx_hal_i2c.c + 0 + 0 + + + 3 + 44 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c + stm32h7xx_hal_i2c_ex.c + 0 + 0 + + + 3 + 45 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2s.c + stm32h7xx_hal_i2s.c + 0 + 0 + + + 3 + 46 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2s_ex.c + stm32h7xx_hal_i2s_ex.c + 0 + 0 + + + 3 + 47 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_irda.c + stm32h7xx_hal_irda.c + 0 + 0 + + + 3 + 48 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_iwdg.c + stm32h7xx_hal_iwdg.c + 0 + 0 + + + 3 + 49 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_jpeg.c + stm32h7xx_hal_jpeg.c + 0 + 0 + + + 3 + 50 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_lptim.c + stm32h7xx_hal_lptim.c + 0 + 0 + + + 3 + 51 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ltdc.c + stm32h7xx_hal_ltdc.c + 0 + 0 + + + 3 + 52 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ltdc_ex.c + stm32h7xx_hal_ltdc_ex.c + 0 + 0 + + + 3 + 53 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdios.c + stm32h7xx_hal_mdios.c + 0 + 0 + + + 3 + 54 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c + stm32h7xx_hal_mdma.c + 0 + 0 + + + 3 + 55 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc.c + stm32h7xx_hal_mmc.c + 0 + 0 + + + 3 + 56 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc_ex.c + stm32h7xx_hal_mmc_ex.c + 0 + 0 + + + 3 + 57 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nand.c + stm32h7xx_hal_nand.c + 0 + 0 + + + 3 + 58 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nor.c + stm32h7xx_hal_nor.c + 0 + 0 + + + 3 + 59 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_opamp.c + stm32h7xx_hal_opamp.c + 0 + 0 + + + 3 + 60 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_opamp_ex.c + stm32h7xx_hal_opamp_ex.c + 0 + 0 + + + 3 + 61 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ospi.c + stm32h7xx_hal_ospi.c + 0 + 0 + + + 3 + 62 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_otfdec.c + stm32h7xx_hal_otfdec.c + 0 + 0 + + + 3 + 63 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd.c + stm32h7xx_hal_pcd.c + 0 + 0 + + + 3 + 64 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd_ex.c + stm32h7xx_hal_pcd_ex.c + 0 + 0 + + + 3 + 65 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pssi.c + stm32h7xx_hal_pssi.c + 0 + 0 + + + 3 + 66 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c + stm32h7xx_hal_pwr.c + 0 + 0 + + + 3 + 67 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c + stm32h7xx_hal_pwr_ex.c + 0 + 0 + + + 3 + 68 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_qspi.c + stm32h7xx_hal_qspi.c + 0 + 0 + + + 3 + 69 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ramecc.c + stm32h7xx_hal_ramecc.c + 0 + 0 + + + 3 + 70 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c + stm32h7xx_hal_rcc.c + 0 + 0 + + + 3 + 71 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c + stm32h7xx_hal_rcc_ex.c + 0 + 0 + + + 3 + 72 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rng.c + stm32h7xx_hal_rng.c + 0 + 0 + + + 3 + 73 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rng_ex.c + stm32h7xx_hal_rng_ex.c + 0 + 0 + + + 3 + 74 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rtc.c + stm32h7xx_hal_rtc.c + 0 + 0 + + + 3 + 75 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rtc_ex.c + stm32h7xx_hal_rtc_ex.c + 0 + 0 + + + 3 + 76 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sai.c + stm32h7xx_hal_sai.c + 0 + 0 + + + 3 + 77 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sai_ex.c + stm32h7xx_hal_sai_ex.c + 0 + 0 + + + 3 + 78 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd.c + stm32h7xx_hal_sd.c + 0 + 0 + + + 3 + 79 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd_ex.c + stm32h7xx_hal_sd_ex.c + 0 + 0 + + + 3 + 80 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sdram.c + stm32h7xx_hal_sdram.c + 0 + 0 + + + 3 + 81 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smartcard.c + stm32h7xx_hal_smartcard.c + 0 + 0 + + + 3 + 82 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smartcard_ex.c + stm32h7xx_hal_smartcard_ex.c + 0 + 0 + + + 3 + 83 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smbus.c + stm32h7xx_hal_smbus.c + 0 + 0 + + + 3 + 84 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smbus_ex.c + stm32h7xx_hal_smbus_ex.c + 0 + 0 + + + 3 + 85 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spdifrx.c + stm32h7xx_hal_spdifrx.c + 0 + 0 + + + 3 + 86 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c + stm32h7xx_hal_spi.c + 0 + 0 + + + 3 + 87 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi_ex.c + stm32h7xx_hal_spi_ex.c + 0 + 0 + + + 3 + 88 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sram.c + stm32h7xx_hal_sram.c + 0 + 0 + + + 3 + 89 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_swpmi.c + stm32h7xx_hal_swpmi.c + 0 + 0 + + + 3 + 90 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c + stm32h7xx_hal_tim.c + 0 + 0 + + + 3 + 91 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c + stm32h7xx_hal_tim_ex.c + 0 + 0 + + + 3 + 92 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c + stm32h7xx_hal_uart.c + 0 + 0 + + + 3 + 93 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c + stm32h7xx_hal_uart_ex.c + 0 + 0 + + + 3 + 94 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_usart.c + stm32h7xx_hal_usart.c + 0 + 0 + + + 3 + 95 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_usart_ex.c + stm32h7xx_hal_usart_ex.c + 0 + 0 + + + 3 + 96 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_wwdg.c + stm32h7xx_hal_wwdg.c + 0 + 0 + + + + + Drivers/CMSIS + 0 + 0 + 0 + 0 + + 4 + 97 + 1 + 0 + 0 + 0 + ..\..\BSP\Core\Src\system_stm32h7xx.c + system_stm32h7xx.c + 0 + 0 + + + + + tos/arch + 0 + 0 + 0 + 0 + + 5 + 98 + 1 + 0 + 0 + 0 + ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c + tos_cpu.c + 0 + 0 + + + 5 + 99 + 1 + 0 + 0 + 0 + ..\..\..\..\arch\arm\arm-v7m\common\tos_fault.c + tos_fault.c + 0 + 0 + + + 5 + 100 + 1 + 0 + 0 + 0 + ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_c.c + port_c.c + 0 + 0 + + + 5 + 101 + 2 + 0 + 0 + 0 + ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_s.S + port_s.S + 0 + 0 + + + + + tos/kernel + 0 + 0 + 0 + 0 + + 6 + 102 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_barrier.c + tos_barrier.c + 0 + 0 + + + 6 + 103 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_binary_heap.c + tos_binary_heap.c + 0 + 0 + + + 6 + 104 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_bitmap.c + tos_bitmap.c + 0 + 0 + + + 6 + 105 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_char_fifo.c + tos_char_fifo.c + 0 + 0 + + + 6 + 106 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_completion.c + tos_completion.c + 0 + 0 + + + 6 + 107 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_countdownlatch.c + tos_countdownlatch.c + 0 + 0 + + + 6 + 108 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_event.c + tos_event.c + 0 + 0 + + + 6 + 109 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_global.c + tos_global.c + 0 + 0 + + + 6 + 110 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_mail_queue.c + tos_mail_queue.c + 0 + 0 + + + 6 + 111 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_message_queue.c + tos_message_queue.c + 0 + 0 + + + 6 + 112 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_mmblk.c + tos_mmblk.c + 0 + 0 + + + 6 + 113 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_mmheap.c + tos_mmheap.c + 0 + 0 + + + 6 + 114 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_mutex.c + tos_mutex.c + 0 + 0 + + + 6 + 115 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_pend.c + tos_pend.c + 0 + 0 + + + 6 + 116 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_priority_mail_queue.c + tos_priority_mail_queue.c + 0 + 0 + + + 6 + 117 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_priority_message_queue.c + tos_priority_message_queue.c + 0 + 0 + + + 6 + 118 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_priority_queue.c + tos_priority_queue.c + 0 + 0 + + + 6 + 119 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_ring_queue.c + tos_ring_queue.c + 0 + 0 + + + 6 + 120 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_robin.c + tos_robin.c + 0 + 0 + + + 6 + 121 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_rwlock.c + tos_rwlock.c + 0 + 0 + + + 6 + 122 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_sched.c + tos_sched.c + 0 + 0 + + + 6 + 123 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_sem.c + tos_sem.c + 0 + 0 + + + 6 + 124 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_stopwatch.c + tos_stopwatch.c + 0 + 0 + + + 6 + 125 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_sys.c + tos_sys.c + 0 + 0 + + + 6 + 126 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_task.c + tos_task.c + 0 + 0 + + + 6 + 127 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_tick.c + tos_tick.c + 0 + 0 + + + 6 + 128 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_time.c + tos_time.c + 0 + 0 + + + 6 + 129 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_timer.c + tos_timer.c + 0 + 0 + + + + + tos/config + 0 + 0 + 0 + 0 + + 7 + 130 + 5 + 0 + 0 + 0 + ..\..\TOS_CONFIG\tos_config.h + tos_config.h + 0 + 0 + + + + + example + 1 + 0 + 0 + 0 + + 8 + 131 + 1 + 0 + 0 + 0 + ..\..\..\..\examples\mqttclient_iot_explorer\mqttclient_iot_explorer.c + mqttclient_iot_explorer.c + 0 + 0 + + + + + hal + 0 + 0 + 0 + 0 + + 9 + 132 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\hal\st\stm32h7xx\src\tos_hal_uart.c + tos_hal_uart.c + 0 + 0 + + + + + net + 0 + 0 + 0 + 0 + + 10 + 133 + 1 + 0 + 0 + 0 + ..\..\..\..\net\at\src\tos_at.c + tos_at.c + 0 + 0 + + + 10 + 134 + 1 + 0 + 0 + 0 + ..\..\..\..\net\sal_module_wrapper\sal_module_wrapper.c + sal_module_wrapper.c + 0 + 0 + + + + + devices + 0 + 0 + 0 + 0 + + 11 + 135 + 1 + 0 + 0 + 0 + ..\..\..\..\devices\esp8266\esp8266.c + esp8266.c + 0 + 0 + + + + + mqttclient/common + 0 + 0 + 0 + 0 + + 12 + 136 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\common\mqtt_list.c + mqtt_list.c + 0 + 0 + + + 12 + 137 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\common\random.c + random.c + 0 + 0 + + + + + mqttclient/mqtt + 0 + 0 + 0 + 0 + + 13 + 138 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTConnectClient.c + MQTTConnectClient.c + 0 + 0 + + + 13 + 139 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTConnectServer.c + MQTTConnectServer.c + 0 + 0 + + + 13 + 140 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTDeserializePublish.c + MQTTDeserializePublish.c + 0 + 0 + + + 13 + 141 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTFormat.c + MQTTFormat.c + 0 + 0 + + + 13 + 142 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTPacket.c + MQTTPacket.c + 0 + 0 + + + 13 + 143 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTSerializePublish.c + MQTTSerializePublish.c + 0 + 0 + + + 13 + 144 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTSubscribeClient.c + MQTTSubscribeClient.c + 0 + 0 + + + 13 + 145 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTSubscribeServer.c + MQTTSubscribeServer.c + 0 + 0 + + + 13 + 146 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTUnsubscribeClient.c + MQTTUnsubscribeClient.c + 0 + 0 + + + 13 + 147 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTUnsubscribeServer.c + MQTTUnsubscribeServer.c + 0 + 0 + + + + + mqttclient + 0 + 0 + 0 + 0 + + 14 + 148 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\mqttclient\mqttclient.c + mqttclient.c + 0 + 0 + + + + + mqttclient/network + 0 + 0 + 0 + 0 + + 15 + 149 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\network\nettype_tcp.c + nettype_tcp.c + 0 + 0 + + + 15 + 150 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\network\nettype_tls.c + nettype_tls.c + 0 + 0 + + + 15 + 151 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\network\network.c + network.c + 0 + 0 + + + + + mqttclient/platform + 0 + 0 + 0 + 0 + + 16 + 152 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_memory.c + platform_memory.c + 0 + 0 + + + 16 + 153 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_mutex.c + platform_mutex.c + 0 + 0 + + + 16 + 154 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_net_socket.c + platform_net_socket.c + 0 + 0 + + + 16 + 155 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_thread.c + platform_thread.c + 0 + 0 + + + 16 + 156 + 1 + 0 + 0 + 0 + ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_timer.c + platform_timer.c + 0 + 0 + + + + + mqttclient/config + 0 + 0 + 0 + 0 + + 17 + 157 + 5 + 0 + 0 + 0 + ..\..\TOS_CONFIG\mqtt_config.h + mqtt_config.h + 0 + 0 + + + + + utils/cjson + 0 + 0 + 0 + 0 + + 18 + 158 + 1 + 0 + 0 + 0 + ..\..\..\..\components\utils\JSON\src\cJSON.c + cJSON.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + +
diff --git a/board/Fire_STM32H743IIT6/KEIL/mqtt_client_iot_exporer/TencentOS-Tiny.uvprojx b/board/Fire_STM32H743IIT6/KEIL/mqtt_client_iot_exporer/TencentOS-Tiny.uvprojx new file mode 100644 index 000000000..3f8445dd7 --- /dev/null +++ b/board/Fire_STM32H743IIT6/KEIL/mqtt_client_iot_exporer/TencentOS-Tiny.uvprojx @@ -0,0 +1,1298 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + TencentOS-Tiny + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + STM32H743IITx + STMicroelectronics + Keil.STM32H7xx_DFP.3.0.0 + http://www.keil.com/pack/ + IRAM(0x20000000-0x2001FFFF) IRAM2(0x24000000-0x2407FFFF) IROM(0x8000000-0x81FFFFF) CLOCK(12000000) FPU3(DFPU) CPUTYPE("Cortex-M7") ELITTLE TZ + + + + 0 + + + + + + + + + + + $$Device:STM32H743IITx$CMSIS\SVD\STM32H743.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + TencentOS-Tiny\ + TencentOS-Tiny + 1 + 0 + 1 + 1 + 0 + + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4101 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x200000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x24000000 + 0x80000 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 1 + 0 + 5 + 3 + 1 + 1 + 0 + 0 + 0 + + + USE_HAL_DRIVER,STM32H743xx + + ..\..\BSP\Core\Inc;..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Inc;..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Inc\Legacy;..\..\..\..\platform\vendor_bsp\st\CMSIS\Device\ST\STM32H7xx\Include;..\..\..\..\platform\vendor_bsp\st\CMSIS\Include;..\..\..\..\arch\arm\arm-v7m\common\include;..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc;..\..\..\..\kernel\core\include;..\..\TOS_CONFIG;..\..\..\..\kernel\hal\include;..\..\..\..\net\at\include;..\..\..\..\net\sal_module_wrapper;..\..\..\..\devices\esp8266;..\..\..\..\components\connectivity\mqttclient\common;..\..\..\..\components\connectivity\mqttclient\mqtt;..\..\..\..\components\connectivity\mqttclient\mqttclient;..\..\..\..\components\connectivity\mqttclient\network;..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny;..\..\..\..\components\utils\JSON\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + + + + + + + + + + + + + + + Application/MDK-ARM + + + startup_stm32h743xx.s + 2 + startup_stm32h743xx.s + + + + + Application/User/Core + + + gpio.c + 1 + ..\..\BSP\Core\Src\gpio.c + + + main.c + 1 + ..\..\BSP\Core\Src\main.c + + + stm32h7xx_hal_msp.c + 1 + ..\..\BSP\Core\Src\stm32h7xx_hal_msp.c + + + usart.c + 1 + ..\..\BSP\Core\Src\usart.c + + + mcu_init.c + 1 + ..\..\BSP\Core\Src\mcu_init.c + + + stm32h7xx_it_module.c + 1 + ..\..\BSP\Core\Src\stm32h7xx_it_module.c + + + + + Drivers/STM32H7xx_HAL_Driver + + + stm32h7xx_hal.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c + + + stm32h7xx_hal_adc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc.c + + + stm32h7xx_hal_adc_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_adc_ex.c + + + stm32h7xx_hal_cec.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cec.c + + + stm32h7xx_hal_comp.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_comp.c + + + stm32h7xx_hal_cordic.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cordic.c + + + stm32h7xx_hal_cortex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c + + + stm32h7xx_hal_crc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc.c + + + stm32h7xx_hal_crc_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc_ex.c + + + stm32h7xx_hal_cryp.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp.c + + + stm32h7xx_hal_cryp_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp_ex.c + + + stm32h7xx_hal_dac.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac.c + + + stm32h7xx_hal_dac_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dac_ex.c + + + stm32h7xx_hal_dcmi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dcmi.c + + + stm32h7xx_hal_dfsdm.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dfsdm.c + + + stm32h7xx_hal_dfsdm_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dfsdm_ex.c + + + stm32h7xx_hal_dma.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c + + + stm32h7xx_hal_dma_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c + + + stm32h7xx_hal_dma2d.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma2d.c + + + stm32h7xx_hal_dsi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dsi.c + + + stm32h7xx_hal_dts.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dts.c + + + stm32h7xx_hal_eth.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_eth.c + + + stm32h7xx_hal_eth_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_eth_ex.c + + + stm32h7xx_hal_exti.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_exti.c + + + stm32h7xx_hal_fdcan.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fdcan.c + + + stm32h7xx_hal_flash.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash.c + + + stm32h7xx_hal_flash_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_flash_ex.c + + + stm32h7xx_hal_fmac.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_fmac.c + + + stm32h7xx_hal_gfxmmu.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gfxmmu.c + + + stm32h7xx_hal_gpio.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c + + + stm32h7xx_hal_hash.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hash.c + + + stm32h7xx_hal_hash_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hash_ex.c + + + stm32h7xx_hal_hcd.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hcd.c + + + stm32h7xx_hal_hrtim.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hrtim.c + + + stm32h7xx_hal_hsem.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_hsem.c + + + stm32h7xx_hal_i2c.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c.c + + + stm32h7xx_hal_i2c_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2c_ex.c + + + stm32h7xx_hal_i2s.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2s.c + + + stm32h7xx_hal_i2s_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_i2s_ex.c + + + stm32h7xx_hal_irda.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_irda.c + + + stm32h7xx_hal_iwdg.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_iwdg.c + + + stm32h7xx_hal_jpeg.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_jpeg.c + + + stm32h7xx_hal_lptim.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_lptim.c + + + stm32h7xx_hal_ltdc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ltdc.c + + + stm32h7xx_hal_ltdc_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ltdc_ex.c + + + stm32h7xx_hal_mdios.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdios.c + + + stm32h7xx_hal_mdma.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c + + + stm32h7xx_hal_mmc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc.c + + + stm32h7xx_hal_mmc_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mmc_ex.c + + + stm32h7xx_hal_nand.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nand.c + + + stm32h7xx_hal_nor.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_nor.c + + + stm32h7xx_hal_opamp.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_opamp.c + + + stm32h7xx_hal_opamp_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_opamp_ex.c + + + stm32h7xx_hal_ospi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ospi.c + + + stm32h7xx_hal_otfdec.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_otfdec.c + + + stm32h7xx_hal_pcd.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd.c + + + stm32h7xx_hal_pcd_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pcd_ex.c + + + stm32h7xx_hal_pssi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pssi.c + + + stm32h7xx_hal_pwr.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c + + + stm32h7xx_hal_pwr_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c + + + stm32h7xx_hal_qspi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_qspi.c + + + stm32h7xx_hal_ramecc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ramecc.c + + + stm32h7xx_hal_rcc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c + + + stm32h7xx_hal_rcc_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c + + + stm32h7xx_hal_rng.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rng.c + + + stm32h7xx_hal_rng_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rng_ex.c + + + stm32h7xx_hal_rtc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rtc.c + + + stm32h7xx_hal_rtc_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rtc_ex.c + + + stm32h7xx_hal_sai.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sai.c + + + stm32h7xx_hal_sai_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sai_ex.c + + + stm32h7xx_hal_sd.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd.c + + + stm32h7xx_hal_sd_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sd_ex.c + + + stm32h7xx_hal_sdram.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sdram.c + + + stm32h7xx_hal_smartcard.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smartcard.c + + + stm32h7xx_hal_smartcard_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smartcard_ex.c + + + stm32h7xx_hal_smbus.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smbus.c + + + stm32h7xx_hal_smbus_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_smbus_ex.c + + + stm32h7xx_hal_spdifrx.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spdifrx.c + + + stm32h7xx_hal_spi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c + + + stm32h7xx_hal_spi_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi_ex.c + + + stm32h7xx_hal_sram.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sram.c + + + stm32h7xx_hal_swpmi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_swpmi.c + + + stm32h7xx_hal_tim.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c + + + stm32h7xx_hal_tim_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c + + + stm32h7xx_hal_uart.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c + + + stm32h7xx_hal_uart_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c + + + stm32h7xx_hal_usart.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_usart.c + + + stm32h7xx_hal_usart_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_usart_ex.c + + + stm32h7xx_hal_wwdg.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_wwdg.c + + + + + Drivers/CMSIS + + + system_stm32h7xx.c + 1 + ..\..\BSP\Core\Src\system_stm32h7xx.c + + + + + tos/arch + + + tos_cpu.c + 1 + ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c + + + tos_fault.c + 1 + ..\..\..\..\arch\arm\arm-v7m\common\tos_fault.c + + + port_c.c + 1 + ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_c.c + + + port_s.S + 2 + ..\..\..\..\arch\arm\arm-v7m\cortex-m7\armcc\port_s.S + + + + + tos/kernel + + + tos_barrier.c + 1 + ..\..\..\..\kernel\core\tos_barrier.c + + + tos_binary_heap.c + 1 + ..\..\..\..\kernel\core\tos_binary_heap.c + + + tos_bitmap.c + 1 + ..\..\..\..\kernel\core\tos_bitmap.c + + + tos_char_fifo.c + 1 + ..\..\..\..\kernel\core\tos_char_fifo.c + + + tos_completion.c + 1 + ..\..\..\..\kernel\core\tos_completion.c + + + tos_countdownlatch.c + 1 + ..\..\..\..\kernel\core\tos_countdownlatch.c + + + tos_event.c + 1 + ..\..\..\..\kernel\core\tos_event.c + + + tos_global.c + 1 + ..\..\..\..\kernel\core\tos_global.c + + + tos_mail_queue.c + 1 + ..\..\..\..\kernel\core\tos_mail_queue.c + + + tos_message_queue.c + 1 + ..\..\..\..\kernel\core\tos_message_queue.c + + + tos_mmblk.c + 1 + ..\..\..\..\kernel\core\tos_mmblk.c + + + tos_mmheap.c + 1 + ..\..\..\..\kernel\core\tos_mmheap.c + + + tos_mutex.c + 1 + ..\..\..\..\kernel\core\tos_mutex.c + + + tos_pend.c + 1 + ..\..\..\..\kernel\core\tos_pend.c + + + tos_priority_mail_queue.c + 1 + ..\..\..\..\kernel\core\tos_priority_mail_queue.c + + + tos_priority_message_queue.c + 1 + ..\..\..\..\kernel\core\tos_priority_message_queue.c + + + tos_priority_queue.c + 1 + ..\..\..\..\kernel\core\tos_priority_queue.c + + + tos_ring_queue.c + 1 + ..\..\..\..\kernel\core\tos_ring_queue.c + + + tos_robin.c + 1 + ..\..\..\..\kernel\core\tos_robin.c + + + tos_rwlock.c + 1 + ..\..\..\..\kernel\core\tos_rwlock.c + + + tos_sched.c + 1 + ..\..\..\..\kernel\core\tos_sched.c + + + tos_sem.c + 1 + ..\..\..\..\kernel\core\tos_sem.c + + + tos_stopwatch.c + 1 + ..\..\..\..\kernel\core\tos_stopwatch.c + + + tos_sys.c + 1 + ..\..\..\..\kernel\core\tos_sys.c + + + tos_task.c + 1 + ..\..\..\..\kernel\core\tos_task.c + + + tos_tick.c + 1 + ..\..\..\..\kernel\core\tos_tick.c + + + tos_time.c + 1 + ..\..\..\..\kernel\core\tos_time.c + + + tos_timer.c + 1 + ..\..\..\..\kernel\core\tos_timer.c + + + + + tos/config + + + tos_config.h + 5 + ..\..\TOS_CONFIG\tos_config.h + + + + + example + + + mqttclient_iot_explorer.c + 1 + ..\..\..\..\examples\mqttclient_iot_explorer\mqttclient_iot_explorer.c + + + + + hal + + + tos_hal_uart.c + 1 + ..\..\..\..\platform\hal\st\stm32h7xx\src\tos_hal_uart.c + + + + + net + + + tos_at.c + 1 + ..\..\..\..\net\at\src\tos_at.c + + + sal_module_wrapper.c + 1 + ..\..\..\..\net\sal_module_wrapper\sal_module_wrapper.c + + + + + devices + + + esp8266.c + 1 + ..\..\..\..\devices\esp8266\esp8266.c + + + + + mqttclient/common + + + mqtt_list.c + 1 + ..\..\..\..\components\connectivity\mqttclient\common\mqtt_list.c + + + random.c + 1 + ..\..\..\..\components\connectivity\mqttclient\common\random.c + + + + + mqttclient/mqtt + + + MQTTConnectClient.c + 1 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTConnectClient.c + + + MQTTConnectServer.c + 1 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTConnectServer.c + + + MQTTDeserializePublish.c + 1 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTDeserializePublish.c + + + MQTTFormat.c + 1 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTFormat.c + + + MQTTPacket.c + 1 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTPacket.c + + + MQTTSerializePublish.c + 1 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTSerializePublish.c + + + MQTTSubscribeClient.c + 1 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTSubscribeClient.c + + + MQTTSubscribeServer.c + 1 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTSubscribeServer.c + + + MQTTUnsubscribeClient.c + 1 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTUnsubscribeClient.c + + + MQTTUnsubscribeServer.c + 1 + ..\..\..\..\components\connectivity\mqttclient\mqtt\MQTTUnsubscribeServer.c + + + + + mqttclient + + + mqttclient.c + 1 + ..\..\..\..\components\connectivity\mqttclient\mqttclient\mqttclient.c + + + + + mqttclient/network + + + nettype_tcp.c + 1 + ..\..\..\..\components\connectivity\mqttclient\network\nettype_tcp.c + + + nettype_tls.c + 1 + ..\..\..\..\components\connectivity\mqttclient\network\nettype_tls.c + + + network.c + 1 + ..\..\..\..\components\connectivity\mqttclient\network\network.c + + + + + mqttclient/platform + + + platform_memory.c + 1 + ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_memory.c + + + platform_mutex.c + 1 + ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_mutex.c + + + platform_net_socket.c + 1 + ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_net_socket.c + + + platform_thread.c + 1 + ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_thread.c + + + platform_timer.c + 1 + ..\..\..\..\components\connectivity\mqttclient\platform\TencentOS-tiny\platform_timer.c + + + + + mqttclient/config + + + mqtt_config.h + 5 + ..\..\TOS_CONFIG\mqtt_config.h + + + + + utils/cjson + + + cJSON.c + 1 + ..\..\..\..\components\utils\JSON\src\cJSON.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + +
diff --git a/board/Fire_STM32H743IIT6/KEIL/mqtt_client_iot_exporer/startup_stm32h743xx.s b/board/Fire_STM32H743IIT6/KEIL/mqtt_client_iot_exporer/startup_stm32h743xx.s new file mode 100644 index 000000000..aed79afe3 --- /dev/null +++ b/board/Fire_STM32H743IIT6/KEIL/mqtt_client_iot_exporer/startup_stm32h743xx.s @@ -0,0 +1,609 @@ +;******************************************************************************** +;* File Name : startup_stm32h743xx.s +;* @author MCD Application Team +;* Description : STM32H7xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2017 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_AVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT FDCAN_CAL_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT HRTIM1_Master_IRQHandler [WEAK] + EXPORT HRTIM1_TIMA_IRQHandler [WEAK] + EXPORT HRTIM1_TIMB_IRQHandler [WEAK] + EXPORT HRTIM1_TIMC_IRQHandler [WEAK] + EXPORT HRTIM1_TIMD_IRQHandler [WEAK] + EXPORT HRTIM1_TIME_IRQHandler [WEAK] + EXPORT HRTIM1_FLT_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SAI3_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT MDIOS_WKUP_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT MDMA_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT HSEM1_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT DMAMUX2_OVR_IRQHandler [WEAK] + EXPORT BDMA_Channel0_IRQHandler [WEAK] + EXPORT BDMA_Channel1_IRQHandler [WEAK] + EXPORT BDMA_Channel2_IRQHandler [WEAK] + EXPORT BDMA_Channel3_IRQHandler [WEAK] + EXPORT BDMA_Channel4_IRQHandler [WEAK] + EXPORT BDMA_Channel5_IRQHandler [WEAK] + EXPORT BDMA_Channel6_IRQHandler [WEAK] + EXPORT BDMA_Channel7_IRQHandler [WEAK] + EXPORT COMP1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT ECC_IRQHandler [WEAK] + EXPORT SAI4_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_AVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +FDCAN_CAL_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +OTG_FS_EP1_OUT_IRQHandler +OTG_FS_EP1_IN_IRQHandler +OTG_FS_WKUP_IRQHandler +OTG_FS_IRQHandler +DMAMUX1_OVR_IRQHandler +HRTIM1_Master_IRQHandler +HRTIM1_TIMA_IRQHandler +HRTIM1_TIMB_IRQHandler +HRTIM1_TIMC_IRQHandler +HRTIM1_TIMD_IRQHandler +HRTIM1_TIME_IRQHandler +HRTIM1_FLT_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SAI3_IRQHandler +SWPMI1_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +MDIOS_WKUP_IRQHandler +MDIOS_IRQHandler +JPEG_IRQHandler +MDMA_IRQHandler +SDMMC2_IRQHandler +HSEM1_IRQHandler +ADC3_IRQHandler +DMAMUX2_OVR_IRQHandler +BDMA_Channel0_IRQHandler +BDMA_Channel1_IRQHandler +BDMA_Channel2_IRQHandler +BDMA_Channel3_IRQHandler +BDMA_Channel4_IRQHandler +BDMA_Channel5_IRQHandler +BDMA_Channel6_IRQHandler +BDMA_Channel7_IRQHandler +COMP1_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +LPUART1_IRQHandler +CRS_IRQHandler +ECC_IRQHandler +SAI4_IRQHandler +WAKEUP_PIN_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/board/Fire_STM32H743IIT6/TOS_CONFIG/mqtt_config.h b/board/Fire_STM32H743IIT6/TOS_CONFIG/mqtt_config.h new file mode 100644 index 000000000..cfc0c976b --- /dev/null +++ b/board/Fire_STM32H743IIT6/TOS_CONFIG/mqtt_config.h @@ -0,0 +1,48 @@ +/* + * @Author: jiejie + * @Github: https://github.com/jiejieTop + * @LastEditTime: 2020-06-17 19:31:41 + * @Description: the code belongs to jiejie, please keep the author information and source code according to the license. + */ +#ifndef _MQTT_CONFIG_H_ +#define _MQTT_CONFIG_H_ + +//#define MQTT_LOG_IS_SALOF + +#define MQTT_NETSOCKET_USING_AT + +#define MQTT_LOG_LEVEL MQTT_LOG_DEBUG_LEVEL //MQTT_LOG_WARN_LEVEL MQTT_LOG_DEBUG_LEVEL + +#ifdef MQTT_LOG_IS_SALOF + #define SALOF_USING_LOG (1U) + #define SALOF_USING_SALOF (1U) + #define SALOF_LOG_LEVEL MQTT_LOG_LEVEL + #define SALOF_OS SALOF_USING_TENCENTOS + #define SALOF_USING_IDLE_HOOK (0U) + #define SALOF_LOG_COLOR (1U) + #define SALOF_LOG_TS (0U) + #define SALOF_LOG_TAR (0U) + #define SALOF_BUFF_SIZE 512 + #define SALOF_FIFO_SIZE 4096 + #define SALOF_TASK_STACK_SIZE 1024 + #define SALOF_TASK_TICK 50 +#endif + +#define MQTT_MAX_PACKET_ID (0xFFFF - 1) +#define MQTT_TOPIC_LEN_MAX 64 +#define MQTT_ACK_HANDLER_NUM_MAX 64 +#define MQTT_DEFAULT_BUF_SIZE 1024 +#define MQTT_DEFAULT_CMD_TIMEOUT 10000 +#define MQTT_MAX_CMD_TIMEOUT 20000 +#define MQTT_MIN_CMD_TIMEOUT 10000 +#define MQTT_KEEP_ALIVE_INTERVAL 50 // unit: second +#define MQTT_VERSION 4 // 4 is mqtt 3.1.1 +#define MQTT_RECONNECT_DEFAULT_DURATION 1000 +#define MQTT_THREAD_STACK_SIZE 2048 +#define MQTT_THREAD_PRIO 5 +#define MQTT_THREAD_TICK 50 + + +#define MQTT_NETWORK_TYPE_NO_TLS + +#endif /* _MQTT_CONFIG_H_ */ diff --git a/board/Fire_STM32H743IIT6/TOS_CONFIG/tos_config.h b/board/Fire_STM32H743IIT6/TOS_CONFIG/tos_config.h new file mode 100644 index 000000000..792e6bf45 --- /dev/null +++ b/board/Fire_STM32H743IIT6/TOS_CONFIG/tos_config.h @@ -0,0 +1,39 @@ +#ifndef _TOS_CONFIG_H_ +#define _TOS_CONFIG_H_ + +#include "stm32h7xx.h" + +#define TOS_CFG_TASK_PRIO_MAX 10u + +#define TOS_CFG_ROUND_ROBIN_EN 1u + +#define TOS_CFG_OBJECT_VERIFY_EN 1u + +#define TOS_CFG_OBJ_DYNAMIC_CREATE_EN 1u + +#define TOS_CFG_EVENT_EN 1u + +#define TOS_CFG_MMBLK_EN 1u + +#define TOS_CFG_MMHEAP_EN 1u + +#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x20000 + +#define TOS_CFG_MUTEX_EN 1u + +#define TOS_CFG_TIMER_EN 1u + +#define TOS_CFG_SEM_EN 1u + +#define TOS_CFG_IDLE_TASK_STK_SIZE 128u + +#define TOS_CFG_CPU_TICK_PER_SECOND 1000u + +#define TOS_CFG_CPU_CLOCK (SystemCoreClock) + +#define TOS_CFG_TIMER_AS_PROC 1u + +#define TOS_CFG_MAIL_QUEUE_EN 1u + +#endif + diff --git a/board/GD32F310G_START/BSP/Inc/gd32f3x0_it.h b/board/GD32F310G_START/BSP/Inc/gd32f3x0_it.h new file mode 100644 index 000000000..4eabb0431 --- /dev/null +++ b/board/GD32F310G_START/BSP/Inc/gd32f3x0_it.h @@ -0,0 +1,60 @@ +/*! + \file gd32f3x0_it.h + \brief the header file of the ISR + + \version 2022-03-06, V1.0.0, demo for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_IT_H +#define GD32F3X0_IT_H + +#include "gd32f3x0.h" + +/* function declarations */ +/* this function handles NMI exception */ +void NMI_Handler(void); +/* this function handles HardFault exception */ +void HardFault_Handler(void); +/* this function handles MemManage exception */ +void MemManage_Handler(void); +/* this function handles BusFault exception */ +void BusFault_Handler(void); +/* this function handles UsageFault exception */ +void UsageFault_Handler(void); +/* this function handles SVC exception */ +void SVC_Handler(void); +/* this function handles DebugMon exception */ +void DebugMon_Handler(void); +/* this function handles PendSV exception */ +void PendSV_Handler(void); +/* this function handles SysTick exception */ +void SysTick_Handler(void); + +#endif /* GD32F3X0_IT_H */ diff --git a/board/GD32F310G_START/BSP/Inc/gd32f3x0_libopt.h b/board/GD32F310G_START/BSP/Inc/gd32f3x0_libopt.h new file mode 100644 index 000000000..5073be9cf --- /dev/null +++ b/board/GD32F310G_START/BSP/Inc/gd32f3x0_libopt.h @@ -0,0 +1,65 @@ +/*! + \file gd32f3x0_libopt.h + \brief library optional for gd32f3x0 + + \version 2022-03-06, V1.0.0, demo for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_LIBOPT_H +#define GD32F3X0_LIBOPT_H + +#include "gd32f3x0_adc.h" +#include "gd32f3x0_crc.h" +#include "gd32f3x0_ctc.h" +#include "gd32f3x0_dbg.h" +#include "gd32f3x0_dma.h" +#include "gd32f3x0_exti.h" +#include "gd32f3x0_fmc.h" +#include "gd32f3x0_gpio.h" +#include "gd32f3x0_syscfg.h" +#include "gd32f3x0_i2c.h" +#include "gd32f3x0_fwdgt.h" +#include "gd32f3x0_pmu.h" +#include "gd32f3x0_rcu.h" +#include "gd32f3x0_rtc.h" +#include "gd32f3x0_spi.h" +#include "gd32f3x0_timer.h" +#include "gd32f3x0_usart.h" +#include "gd32f3x0_wwdgt.h" +#include "gd32f3x0_misc.h" +#include "gd32f3x0_tsi.h" + +#ifdef GD32F350 +#include "gd32f3x0_cec.h" +#include "gd32f3x0_cmp.h" +#include "gd32f3x0_dac.h" +#endif /* GD32F350 */ + +#endif /* GD32F3X0_LIBOPT_H */ diff --git a/board/GD32F310G_START/BSP/Inc/gpio.h b/board/GD32F310G_START/BSP/Inc/gpio.h new file mode 100644 index 000000000..60ffe1e9a --- /dev/null +++ b/board/GD32F310G_START/BSP/Inc/gpio.h @@ -0,0 +1,30 @@ +/****************************************************************************** +* File: gpio.h +* +* Author: iysheng@163.com +* Created: 04/14/22 +*****************************************************************************/ + +#ifndef __GPIO_H__ +#define __GPIO_H__ +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "gd32f3x0_libopt.h" + +#define LED_Pin GPIO_PIN_1 +#define LED_GPIO_Port GPIOA + +/** + * @brief GPIO inint + * @param void: + * retval N/A. + */ +void board_gpio_init(void); + +#ifdef __cplusplus +} +#endif +#endif /*__PINOUT_H__ */ diff --git a/board/GD32F310G_START/BSP/Inc/main.h b/board/GD32F310G_START/BSP/Inc/main.h new file mode 100644 index 000000000..bf6c2d3d2 --- /dev/null +++ b/board/GD32F310G_START/BSP/Inc/main.h @@ -0,0 +1,36 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/board/GD32F310G_START/BSP/Inc/mcu_init.h b/board/GD32F310G_START/BSP/Inc/mcu_init.h new file mode 100644 index 000000000..ec4a137b3 --- /dev/null +++ b/board/GD32F310G_START/BSP/Inc/mcu_init.h @@ -0,0 +1,18 @@ +#ifndef __MCU_INIT_H +#define __MCU_INIT_H +#ifdef __cplusplus + extern "C" { +#endif + +#include "main.h" +#include "usart.h" +#include "gpio.h" +#include "tos_k.h" + +void board_init(void); +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif +#endif /*__ __MCU_INIT_H */ diff --git a/board/GD32F310G_START/BSP/Inc/tickless/bsp_pm_device.h b/board/GD32F310G_START/BSP/Inc/tickless/bsp_pm_device.h new file mode 100644 index 000000000..40efb2e16 --- /dev/null +++ b/board/GD32F310G_START/BSP/Inc/tickless/bsp_pm_device.h @@ -0,0 +1,11 @@ +#ifndef _PM_DEVICE_H_ +#define _PM_DEVICE_H_ + +#if TOS_CFG_PWR_MGR_EN > 0u + +extern k_pm_device_t pm_device_uart; + +#endif + +#endif + diff --git a/board/GD32F310G_START/BSP/Inc/tickless/bsp_tickless_alarm.h b/board/GD32F310G_START/BSP/Inc/tickless/bsp_tickless_alarm.h new file mode 100644 index 000000000..02cb3e8a0 --- /dev/null +++ b/board/GD32F310G_START/BSP/Inc/tickless/bsp_tickless_alarm.h @@ -0,0 +1,17 @@ +#ifndef _TICKLESS_ALARM_H_ +#define _TICKLESS_ALARM_H_ + +#if TOS_CFG_TICKLESS_EN > 0u + +extern k_tickless_wkup_alarm_t tickless_wkup_alarm_systick; + +extern k_tickless_wkup_alarm_t tickless_wkup_alarm_tim; + +extern k_tickless_wkup_alarm_t tickless_wkup_alarm_rtc_wkupirq; + +extern k_tickless_wkup_alarm_t tickless_wkup_alarm_rtc_alarmirq; + +#endif + +#endif + diff --git a/board/GD32F310G_START/BSP/Inc/usart.h b/board/GD32F310G_START/BSP/Inc/usart.h new file mode 100644 index 000000000..dfe0b3372 --- /dev/null +++ b/board/GD32F310G_START/BSP/Inc/usart.h @@ -0,0 +1,25 @@ +/****************************************************************************** +* File: usart.h +* +* Author: iysheng@163.com +* Created: 04/14/22 +* Description: +*****************************************************************************/ +#ifndef __USART_H__ +#define __USART_H__ +#ifdef __cplusplus +extern "C" { +#endif +#include "gd32f3x0_libopt.h" + +/** + * @brief 板级 usart 硬件初始化 + * @param void: + * retval N/A. + */ +int board_usart_init(void); + +#ifdef __cplusplus +} +#endif +#endif /*__USART_H__ */ diff --git a/board/GD32F310G_START/BSP/Src/gd32f3x0_it.c b/board/GD32F310G_START/BSP/Src/gd32f3x0_it.c new file mode 100644 index 000000000..fca2d443b --- /dev/null +++ b/board/GD32F310G_START/BSP/Src/gd32f3x0_it.c @@ -0,0 +1,151 @@ +/*! + \file gd32f3x0_it.c + \brief interrupt service routines + + \version 2022-03-06, V1.0.0, demo for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_it.h" +#include "tos_k.h" +#include "tos_shell.h" + +/*! + \brief this function handles NMI exception + \param[in] none + \param[out] none + \retval none +*/ +void NMI_Handler(void) +{ +} + +/*! + \brief this function handles HardFault exception + \param[in] none + \param[out] none + \retval none +*/ +void HardFault_Handler(void) +{ + /* if Hard Fault exception occurs, go to infinite loop */ + while(1){ + } +} + +/*! + \brief this function handles MemManage exception + \param[in] none + \param[out] none + \retval none +*/ +void MemManage_Handler(void) +{ + /* if Memory Manage exception occurs, go to infinite loop */ + while(1){ + } +} + +/*! + \brief this function handles BusFault exception + \param[in] none + \param[out] none + \retval none +*/ +void BusFault_Handler(void) +{ + /* if Bus Fault exception occurs, go to infinite loop */ + while(1){ + } +} + +/*! + \brief this function handles UsageFault exception + \param[in] none + \param[out] none + \retval none +*/ +void UsageFault_Handler(void) +{ + /* if Usage Fault exception occurs, go to infinite loop */ + while(1){ + } +} + +/*! + \brief this function handles SVC exception + \param[in] none + \param[out] none + \retval none +*/ +void SVC_Handler(void) +{ +} + +/*! + \brief this function handles DebugMon exception + \param[in] none + \param[out] none + \retval none +*/ +void DebugMon_Handler(void) +{ +} + +/*! + \brief this function handles SysTick exception + \param[in] none + \param[out] none + \retval none +*/ +void SysTick_Handler(void) +{ + if (tos_knl_is_running()) + { + tos_knl_irq_enter(); + tos_tick_handler(); + tos_knl_irq_leave(); + } +} + +void USART0_IRQHandler(void) +{ + tos_knl_irq_enter(); + if (SET == usart_interrupt_flag_get(USART0, USART_INT_FLAG_RBNE)) + { + usart_flag_clear(USART0, USART_FLAG_ORERR); + tos_shell_input_byte((uint8_t)usart_data_receive(USART0)); + } + if (SET == usart_interrupt_flag_get(USART0, USART_INT_FLAG_RBNE_ORERR)) + { + usart_interrupt_flag_clear(USART0, USART_INT_FLAG_RBNE_ORERR); + } + tos_knl_irq_leave(); +} + diff --git a/board/GD32F310G_START/BSP/Src/gpio.c b/board/GD32F310G_START/BSP/Src/gpio.c new file mode 100644 index 000000000..790b2a609 --- /dev/null +++ b/board/GD32F310G_START/BSP/Src/gpio.c @@ -0,0 +1,29 @@ +/****************************************************************************** +* File: gpio.c +* +* Author: iysheng@163.com +* Created: 04/14/22 +* gpio hardware init +*****************************************************************************/ + +#include "gpio.h" + +/** + * @brief GPIO inint + * @param void: + * retval N/A. + */ +void board_gpio_init(void) +{ + rcu_periph_clock_enable(RCU_GPIOA); + rcu_periph_clock_enable(RCU_GPIOA); + gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_9); + gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_10); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, GPIO_PIN_10); + gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, GPIO_PIN_9); + gpio_af_set(GPIOA, GPIO_AF_1, GPIO_PIN_9); + gpio_af_set(GPIOA, GPIO_AF_1, GPIO_PIN_10); + gpio_mode_set(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO_PIN_1); + gpio_bit_set(GPIOA, GPIO_PIN_1); +} + diff --git a/board/GD32F310G_START/BSP/Src/main.c b/board/GD32F310G_START/BSP/Src/main.c new file mode 100644 index 000000000..4e05a8375 --- /dev/null +++ b/board/GD32F310G_START/BSP/Src/main.c @@ -0,0 +1,37 @@ +#include "mcu_init.h" +#include "tos_shell.h" + +#define APPLICATION_TASK_STK_SIZE 0x100 +k_task_t application_task; +uint8_t application_task_stk[APPLICATION_TASK_STK_SIZE]; +static char gs_cmd_buffer[32]; + +__attribute__ ((__weak__)) void application_entry(void *arg) +{ + while (1) { + gpio_bit_toggle(LED_GPIO_Port, LED_Pin); + tos_task_delay(1000); + } +} + +static void board_shell_output_t(const char ch) +{ + if (ch == '\n') + { + while(RESET == usart_flag_get(USART0, USART_FLAG_TBE)); + usart_data_transmit(USART0, '\r'); + } + while(RESET == usart_flag_get(USART0, USART_FLAG_TBE)); + usart_data_transmit(USART0, ch); +} + +int main(void) +{ + board_init(); + printf("Welcome to TencentOS tiny(%s)\r\n", TOS_VERSION); + tos_knl_init(); + tos_task_create(&application_task, "application_task", application_entry, NULL, 4, application_task_stk, APPLICATION_TASK_STK_SIZE, 0); + tos_shell_init(gs_cmd_buffer, sizeof(gs_cmd_buffer), board_shell_output_t, NULL); + tos_knl_start(); +} + diff --git a/board/GD32F310G_START/BSP/Src/mcu_init.c b/board/GD32F310G_START/BSP/Src/mcu_init.c new file mode 100644 index 000000000..381d805f8 --- /dev/null +++ b/board/GD32F310G_START/BSP/Src/mcu_init.c @@ -0,0 +1,36 @@ +#include "mcu_init.h" + +#define USART_CONSOLE (USART0) +int fputc(int ch, FILE *f) +{ + if (ch == '\n') { + while(RESET == usart_flag_get(USART_CONSOLE, USART_FLAG_TBE)); + /* Auto complete return char */ + usart_data_transmit(USART_CONSOLE, '\r'); + } + while(RESET == usart_flag_get(USART_CONSOLE, USART_FLAG_TBE)); + usart_data_transmit(USART_CONSOLE, ch); + return ch; +} + +int _write(int fd, char *ptr, int len) +{ + int i = 0; + for (; i < len; i++) + { + if (*(ptr + i) == '\n') { + while(RESET == usart_flag_get(USART_CONSOLE, USART_FLAG_TBE)); + /* Auto complete return char */ + usart_data_transmit(USART_CONSOLE, '\r'); + } + while(RESET == usart_flag_get(USART_CONSOLE, USART_FLAG_TBE)); + usart_data_transmit(USART_CONSOLE, *(ptr + i)); + } + return len; +} + +void board_init(void) +{ + board_gpio_init(); + board_usart_init(); +} diff --git a/board/GD32F310G_START/BSP/Src/tickless/bsp_pm_device.c b/board/GD32F310G_START/BSP/Src/tickless/bsp_pm_device.c new file mode 100644 index 000000000..bc95c8135 --- /dev/null +++ b/board/GD32F310G_START/BSP/Src/tickless/bsp_pm_device.c @@ -0,0 +1,31 @@ +#include "tos_k.h" +#include "mcu_init.h" + +#if TOS_CFG_PWR_MGR_EN > 0u + +static int pm_device_uart_init(void) +{ + return 0; +} + +static int pm_device_uart_suspend(void) +{ + return 0; +} + +static int pm_device_uart_resume(void) +{ + SystemClock_Config(); + + return 0; +} + +k_pm_device_t pm_device_uart = { + .name = "uart", + .init = pm_device_uart_init, + .suspend = pm_device_uart_suspend, + .resume = pm_device_uart_resume, +}; + +#endif + diff --git a/board/GD32F310G_START/BSP/Src/tickless/bsp_pwr_mgr.c b/board/GD32F310G_START/BSP/Src/tickless/bsp_pwr_mgr.c new file mode 100644 index 000000000..a8df35a86 --- /dev/null +++ b/board/GD32F310G_START/BSP/Src/tickless/bsp_pwr_mgr.c @@ -0,0 +1,26 @@ +#include "tos_k.h" +#include "tickless/bsp_pm_device.h" +#include "tickless/bsp_tickless_alarm.h" + +int tos_bsp_tickless_setup(void) +{ +#if TOS_CFG_TICKLESS_EN > 0u + tos_pm_device_register(&pm_device_uart); + + /* we set a default one shot timer here(systick) */ + // tos_tickless_wkup_alarm_install(TOS_LOW_POWER_MODE_SLEEP, &tickless_wkup_alarm_systick); + tos_tickless_wkup_alarm_install(TOS_LOW_POWER_MODE_SLEEP, &tickless_wkup_alarm_tim); + tos_tickless_wkup_alarm_init(TOS_LOW_POWER_MODE_SLEEP); + + tos_tickless_wkup_alarm_install(TOS_LOW_POWER_MODE_STOP, &tickless_wkup_alarm_rtc_wkupirq); + tos_tickless_wkup_alarm_init(TOS_LOW_POWER_MODE_STOP); + + tos_tickless_wkup_alarm_install(TOS_LOW_POWER_MODE_STANDBY, &tickless_wkup_alarm_rtc_alarmirq); + tos_tickless_wkup_alarm_init(TOS_LOW_POWER_MODE_STANDBY); + + tos_pm_cpu_lpwr_mode_set(TOS_LOW_POWER_MODE_SLEEP); +#endif + + return 0; +} + diff --git a/board/GD32F310G_START/BSP/Src/tickless/bsp_tickless_alarm.c b/board/GD32F310G_START/BSP/Src/tickless/bsp_tickless_alarm.c new file mode 100644 index 000000000..99c31edb1 --- /dev/null +++ b/board/GD32F310G_START/BSP/Src/tickless/bsp_tickless_alarm.c @@ -0,0 +1,440 @@ +#include "tos_k.h" + +#include "stm32l4xx_hal.h" +#include "stm32l4xx_hal_tim.h" +#include "stm32l4xx_hal_rtc.h" + +#if TOS_CFG_TICKLESS_EN > 0u + +/* + systickҲʵΪticklessĻӣʵԭǣϵͳҪticklessģʽʱ + systickĴʱ + ˵һʱ6000msִУô6000mssystickûбҪһֱ + ԰systickжϼΪ6000msʵsystickڲļʱĴֻ24λsystick + жϼʵСԲοtickless_systick_wkup_alarm_max_delayʵ֣ʹ + ȻڽidleʱʹcpusleepģʽҪͣΪsystickˣcpusleep + ģʽͣã + + ʵϣtickless_systick_wkup_alarm_dismisstickless_wkup_alarm_dismissӿȱݵģ + ΪCPUticklessܲΪʱ䵽ˣпⲿжCPUѣһ + Ϊ걸ʵӦǣtickless_wkup_alarm_dismissӿڷʵ˯ߵʱ䣨ͨӵļʱĴ + ֵȱݺڻ޸ֽ׶ζӲвϤ + + ע⣬systickֻΪsleepģʽµĻӡοtos_pm.h + + Ŀǰһʵв걸кܶⷽѻӭͽ~ + */ +static void tickless_systick_suspend(void) +{ + cpu_systick_suspend(); + cpu_systick_pending_reset(); +} + +static void tickless_systick_resume(void) +{ + cpu_systick_resume(); +} + +static void tickless_systick_wkup_alarm_expires_set(k_time_t millisecond) +{ + cpu_systick_expires_set(millisecond); +} + +static int tickless_systick_wkup_alarm_setup(k_time_t millisecond) +{ + tickless_systick_suspend(); + tickless_systick_wkup_alarm_expires_set(millisecond); + tickless_systick_resume(); + return 0; +} + +static int tickless_systick_wkup_alarm_dismiss(void) +{ + // TODO: + // if not wakeup by systick(that's say another interrupt), need to identify this and fix + return 0; +} + +static k_time_t tickless_systick_wkup_alarm_max_delay(void) +{ + return cpu_systick_max_delay_millisecond(); +} + +k_tickless_wkup_alarm_t tickless_wkup_alarm_systick = { + .init = K_NULL, + .setup = tickless_systick_wkup_alarm_setup, + .dismiss = tickless_systick_wkup_alarm_dismiss, + .max_delay = tickless_systick_wkup_alarm_max_delay, +}; + + +///////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////// +/* + timer6ʵֵticklessӣΪSLEEPģʽµĻԴοtos_pm.h + Ŀǰһʵв걸кܶⷽѻӭͽ~ + */ +static TIM_HandleTypeDef tim6; + +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *tim_handler) +{ + if (tim_handler->Instance == TIM6) { + __HAL_RCC_TIM6_CLK_ENABLE(); + + /* TIM6 interrupt Init */ + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); + } +} + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *tim_handler) +{ + if (tim_handler->Instance == TIM6) { + /* Peripheral clock disable */ + __HAL_RCC_TIM6_CLK_DISABLE(); + + /* TIM6 interrupt Deinit */ + HAL_NVIC_DisableIRQ(TIM6_DAC_IRQn); + } +} + +static int tickless_tim6_wkup_alarm_init(void) +{ + tim6.Instance = TIM6; + tim6.Init.Prescaler = 0; + tim6.Init.CounterMode = TIM_COUNTERMODE_UP; + tim6.Init.Period = 0; + tim6.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + tim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + HAL_TIM_Base_Init(&tim6); + return 0; +} + +static int tickless_tim6_wkup_alarm_setup(k_time_t millisecond) +{ + tim6.Init.Prescaler = 8000 - 1; + tim6.Init.Period = (millisecond * 10) - 1; + + HAL_TIM_Base_Stop(&tim6); + __HAL_TIM_CLEAR_IT(&tim6, TIM_IT_UPDATE); + + HAL_TIM_Base_Init(&tim6); + HAL_TIM_Base_Start_IT(&tim6); + return 0; +} + +static int tickless_tim6_wkup_alarm_dismiss(void) +{ + TOS_CPU_CPSR_ALLOC(); + + TOS_CPU_INT_DISABLE(); + + HAL_TIM_Base_Stop(&tim6); + HAL_TIM_Base_Stop_IT(&tim6); + + TOS_CPU_INT_ENABLE(); + return 0; +} + +static k_time_t tickless_tim6_wkup_alarm_max_delay(void) +{ + k_time_t millisecond; + uint32_t max_period; + + max_period = ~((uint32_t)0u); + millisecond = (max_period - 1) / 10; + return millisecond; +} + +void TIM6_DAC_IRQHandler(void) +{ + HAL_TIM_IRQHandler(&tim6); +} + +k_tickless_wkup_alarm_t tickless_wkup_alarm_tim = { + .init = tickless_tim6_wkup_alarm_init, + .setup = tickless_tim6_wkup_alarm_setup, + .dismiss = tickless_tim6_wkup_alarm_dismiss, + .max_delay = tickless_tim6_wkup_alarm_max_delay, +}; + + +///////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////// +/* + rtc wakeupжʵֵticklessӣΪSLEEPSTOPģʽµĻԴοtos_pm.h + Ŀǰһʵв걸кܶⷽѻӭͽ~ + */ +static RTC_HandleTypeDef rtc_handler; + +static HAL_StatusTypeDef tickless_rtc_time_set(uint8_t hour, uint8_t minu, uint8_t sec, uint8_t format) +{ + RTC_TimeTypeDef rtc_time; + + rtc_time.Hours = hour; + rtc_time.Minutes = minu; + rtc_time.Seconds = sec; + rtc_time.TimeFormat = format; + rtc_time.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; + rtc_time.StoreOperation = RTC_STOREOPERATION_RESET; + return HAL_RTC_SetTime(&rtc_handler, &rtc_time, RTC_FORMAT_BIN); +} + +static HAL_StatusTypeDef tickless_rtc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t week) +{ + RTC_DateTypeDef rtc_date; + + rtc_date.Date = date; + rtc_date.Month = month; + rtc_date.WeekDay = week; + rtc_date.Year = year; + return HAL_RTC_SetDate(&rtc_handler, &rtc_date, RTC_FORMAT_BIN); +} + +static int tickless_rtc_wkup_alarm_init(void) +{ + rtc_handler.Instance = RTC; + rtc_handler.Init.HourFormat = RTC_HOURFORMAT_24; + rtc_handler.Init.AsynchPrediv = 0X7F; + rtc_handler.Init.SynchPrediv = 0XFF; + rtc_handler.Init.OutPut = RTC_OUTPUT_DISABLE; + rtc_handler.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + rtc_handler.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + + if (HAL_RTC_Init(&rtc_handler) != HAL_OK) { + return -1; + } + + if (HAL_RTCEx_BKUPRead(&rtc_handler, RTC_BKP_DR0) != 0X5050) { + tickless_rtc_time_set(23, 59, 56, RTC_HOURFORMAT12_PM); + tickless_rtc_date_set(15, 12, 27, 7); + HAL_RTCEx_BKUPWrite(&rtc_handler, RTC_BKP_DR0,0X5050); + } + + return 0; +} + +static int tickless_rtc_wkupirq_wkup_alarm_setup(k_time_t millisecond) +{ + uint32_t wkup_clock = RTC_WAKEUPCLOCK_CK_SPRE_16BITS; + if (millisecond < 1000) { + millisecond = 1000; + } + uint32_t wkup_count = (millisecond / 1000) - 1; + + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&rtc_handler, RTC_FLAG_WUTF); + + HAL_RTCEx_SetWakeUpTimer_IT(&rtc_handler, wkup_count, wkup_clock); + + HAL_NVIC_SetPriority(RTC_WKUP_IRQn, 0x02, 0x02); + HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn); + return 0; +} + +static int tickless_rtc_wkupirq_wkup_alarm_dismiss(void) +{ +#if defined(STM32F4) || defined(STM32L4) + __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU); +#endif + + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&rtc_handler, RTC_FLAG_WUTF); + + if (HAL_RTCEx_DeactivateWakeUpTimer(&rtc_handler) != HAL_OK) { + return -1; + } + + HAL_NVIC_DisableIRQ(RTC_WKUP_IRQn); + return 0; +} + +static k_time_t tickless_rtc_wkupirq_wkup_alarm_max_delay(void) +{ + return 0xFFFF * K_TIME_MILLISEC_PER_SEC; +} + +void HAL_RTC_MspInit(RTC_HandleTypeDef *rtc_handler) +{ + RCC_OscInitTypeDef rcc_osc; + RCC_PeriphCLKInitTypeDef periph_clock; + + __HAL_RCC_PWR_CLK_ENABLE(); + HAL_PWR_EnableBkUpAccess(); + + rcc_osc.OscillatorType = RCC_OSCILLATORTYPE_LSE; + rcc_osc.PLL.PLLState = RCC_PLL_NONE; + rcc_osc.LSEState = RCC_LSE_ON; + HAL_RCC_OscConfig(&rcc_osc); + + periph_clock.PeriphClockSelection = RCC_PERIPHCLK_RTC; + periph_clock.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + HAL_RCCEx_PeriphCLKConfig(&periph_clock); + + __HAL_RCC_RTC_ENABLE(); +} + +void RTC_WKUP_IRQHandler(void) +{ + HAL_RTCEx_WakeUpTimerIRQHandler(&rtc_handler); +} + +void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *rtc_handler) +{ +} + +k_tickless_wkup_alarm_t tickless_wkup_alarm_rtc_wkupirq = { + .init = tickless_rtc_wkup_alarm_init, + .setup = tickless_rtc_wkupirq_wkup_alarm_setup, + .dismiss = tickless_rtc_wkupirq_wkup_alarm_dismiss, + .max_delay = tickless_rtc_wkupirq_wkup_alarm_max_delay, +}; + + + +///////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////// +/* + rtc alarmжʵֵticklessӣΪSLEEPSTOPSTANDBYģʽµĻԴοtos_pm.h + Ŀǰһʵв걸кܶⷽѻӭͽ~ + */ +static int tickless_rtc_alarmirq_wkup_alarm_setup(k_time_t millisecond) +{ + uint8_t hour, minute, second, subsecond, date; + + RTC_AlarmTypeDef rtc_alarm; + RTC_TimeTypeDef rtc_time; + RTC_DateTypeDef rtc_date; + + HAL_RTC_GetTime(&rtc_handler, &rtc_time, RTC_FORMAT_BIN); + HAL_RTC_GetDate(&rtc_handler, &rtc_date, RTC_FORMAT_BIN); + + hour = rtc_time.Hours; + minute = rtc_time.Minutes; + second = rtc_time.Seconds; +#if 0 + date = rtc_date.Date; +#else + date = rtc_date.WeekDay; +#endif + + printf("before >>> %d %d %d %d\n", date, hour, minute, second); + + /* I know it's ugly, I will find a elegant way. Welcome to tell me, 3ks~ */ + second += millisecond / K_TIME_MILLISEC_PER_SEC; + if (second >= 60) { + minute += 1; + second -= 60; + } + if (minute >= 60) { + hour += 1; + minute -= 60; + } + if (hour >= 24) { + date += 1; + hour -= 24; + } + + printf("after >>> %d %d %d %d\n", date, hour, minute, second); + + rtc_alarm.AlarmTime.Hours = hour; + rtc_alarm.AlarmTime.Minutes = minute; + rtc_alarm.AlarmTime.Seconds = second; + rtc_alarm.AlarmTime.SubSeconds = 0; + rtc_alarm.AlarmTime.TimeFormat = RTC_HOURFORMAT12_AM; + + rtc_alarm.AlarmMask = RTC_ALARMMASK_NONE; + rtc_alarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDMASK_NONE; + rtc_alarm.AlarmDateWeekDaySel = RTC_ALARMDATEWEEKDAYSEL_WEEKDAY; // RTC_ALARMDATEWEEKDAYSEL_DATE; // RTC_ALARMDATEWEEKDAYSEL_WEEKDAY; + rtc_alarm.AlarmDateWeekDay = date; + rtc_alarm.Alarm = RTC_ALARM_A; + HAL_RTC_SetAlarm_IT(&rtc_handler, &rtc_alarm, RTC_FORMAT_BIN); + + HAL_NVIC_SetPriority(RTC_Alarm_IRQn, 0x01, 0x02); + HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); + + + // __HAL_PWR_GET_FLAG(PWR_FLAG_WU) + + + __HAL_RCC_AHB1_FORCE_RESET(); //λIO + __HAL_RCC_PWR_CLK_ENABLE(); //ʹPWRʱ + + // __HAL_RCC_BACKUPRESET_FORCE(); //λ + HAL_PWR_EnableBkUpAccess(); //ʹ + + __HAL_PWR_CLEAR_FLAG(PWR_FLAG_SB); + __HAL_RTC_WRITEPROTECTION_DISABLE(&rtc_handler);//رRTCд + + //رRTCж + __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&rtc_handler,RTC_IT_WUT); +#if 0 + __HAL_RTC_TIMESTAMP_DISABLE_IT(&rtc_handler,RTC_IT_TS); + __HAL_RTC_ALARM_DISABLE_IT(&rtc_handler,RTC_IT_ALRA|RTC_IT_ALRB); +#endif + + //RTCжϱ־λ + __HAL_RTC_ALARM_CLEAR_FLAG(&rtc_handler,RTC_FLAG_ALRAF|RTC_FLAG_ALRBF); + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(&rtc_handler,RTC_FLAG_TSF); + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&rtc_handler,RTC_FLAG_WUTF); + + // __HAL_RCC_BACKUPRESET_RELEASE(); //λ + __HAL_RTC_WRITEPROTECTION_ENABLE(&rtc_handler); //ʹRTCд + + +#ifdef STM32F4 + __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU); //Wake_UP־ +#endif + +#ifdef STM32F7 + // __HAL_PWR_CLEAR_WAKEUP_FLAG(PWR_WAKEUP_PIN_FLAG1); //Wake_UP־ +#endif + + // HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN1); //WKUPڻ + + return 0; +} + +static int tickless_rtc_alarmirq_wkup_alarm_dismiss(void) +{ +#if 1 + // __HAL_PWR_GET_FLAG(PWR_FLAG_WU); + + __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU); + + // __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&rtc_handler, RTC_FLAG_ALRAF); + + __HAL_RTC_ALARM_CLEAR_FLAG(&rtc_handler, RTC_FLAG_ALRAF); + +#if 0 + if (HAL_RTCEx_DeactivateWakeUpTimer(&rtc_handler) != HAL_OK) { + return -1; + } +#endif + + HAL_NVIC_DisableIRQ(RTC_Alarm_IRQn); + return 0; +#endif +} + +static k_time_t tickless_rtc_alarmirq_wkup_alarm_max_delay(void) +{ + return 0xFFFF; // just kidding, I will fix it out. Welcome to tell me, 3ks~ */ +} + +void RTC_Alarm_IRQHandler(void) +{ + HAL_RTC_AlarmIRQHandler(&rtc_handler); +} + +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *rtc_handler) +{ +} + +k_tickless_wkup_alarm_t tickless_wkup_alarm_rtc_alarmirq = { + .init = tickless_rtc_wkup_alarm_init, + .setup = tickless_rtc_alarmirq_wkup_alarm_setup, + .dismiss = tickless_rtc_alarmirq_wkup_alarm_dismiss, + .max_delay = tickless_rtc_alarmirq_wkup_alarm_max_delay, +}; + +#endif + diff --git a/board/GD32F310G_START/BSP/Src/usart.c b/board/GD32F310G_START/BSP/Src/usart.c new file mode 100644 index 000000000..e86602482 --- /dev/null +++ b/board/GD32F310G_START/BSP/Src/usart.c @@ -0,0 +1,43 @@ +/** + ****************************************************************************** + * File Name : USART.c + * Description : This file provides code for the configuration + * of the USART instances. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usart.h" + +/** + * @brief 板级 usart 硬件初始化 + * @param void: + * retval N/A. + */ +int board_usart_init(void) +{ + rcu_periph_clock_enable(RCU_USART0); + usart_deinit(RCU_USART0); + usart_baudrate_set(USART0, 115200); + usart_stop_bit_set(USART0, USART_STB_1BIT); + usart_word_length_set(USART0, USART_WL_8BIT); + usart_parity_config(USART0, USART_PM_NONE); + usart_transmit_config(USART0, USART_TRANSMIT_ENABLE); + usart_receive_config(USART0, USART_RECEIVE_ENABLE); + usart_interrupt_enable(USART0, USART_INT_RBNE); + usart_enable(USART0); + nvic_irq_enable(USART0_IRQn, 0, 0); + + return 0; +} diff --git a/board/GD32F310G_START/GCC/hello_world/Makefile b/board/GD32F310G_START/GCC/hello_world/Makefile new file mode 100644 index 000000000..219a8fc91 --- /dev/null +++ b/board/GD32F310G_START/GCC/hello_world/Makefile @@ -0,0 +1,226 @@ +########################################################################################################################## +# File automatically-generated by tool: [projectgenerator] version: [3.3.0] date: [Mon Aug 05 10:29:11 CST 2019] +########################################################################################################################## + +# ------------------------------------------------ +# Generic Makefile (based on gcc) +# +# ChangeLog : +# 2022-04-13 - Port to GD32F310-START +# 2017-02-10 - Several enhancements + project update mode +# 2015-07-22 - first version +# ------------------------------------------------ + +###################################### +# target +###################################### +TARGET = TencentOS_tiny + + +###################################### +# building variables +###################################### +# debug build? +DEBUG = 1 +# optimization +OPT = -O2 + +TOP_DIR = ../../../.. +####################################### +# paths +####################################### +# Build path +BUILD_DIR = build + +###################################### +# source +###################################### +# C sources +KERNEL_SRC = \ + ${wildcard $(TOP_DIR)/kernel/core/*.c} + C_SOURCES += $(KERNEL_SRC) + +ARCH_SRC = \ + ${wildcard $(TOP_DIR)/arch/arm/arm-v7m/cortex-m4/gcc/*.c} \ + ${wildcard $(TOP_DIR)/arch/arm/arm-v7m/common/*.c} + C_SOURCES += $(ARCH_SRC) + +HAL_DRIVER_SRC = \ + $(TOP_DIR)/board/GD32F310G_START/BSP/Src/main.c \ + $(TOP_DIR)/board/GD32F310G_START/BSP/Src/mcu_init.c \ + $(TOP_DIR)/board/GD32F310G_START/BSP/Src/gd32f3x0_it.c \ + $(TOP_DIR)/board/GD32F310G_START/BSP/Src/gpio.c \ + $(TOP_DIR)/board/GD32F310G_START/BSP/Src/usart.c \ + $(TOP_DIR)/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Source/system_gd32f3x0.c \ + $(TOP_DIR)/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_dbg.c \ + $(TOP_DIR)/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_dma.c \ + $(TOP_DIR)/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_exti.c \ + $(TOP_DIR)/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_fmc.c \ + $(TOP_DIR)/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_gpio.c \ + $(TOP_DIR)/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_misc.c \ + $(TOP_DIR)/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_pmu.c \ + $(TOP_DIR)/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_rcu.c \ + $(TOP_DIR)/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_syscfg.c \ + $(TOP_DIR)/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_timer.c \ + $(TOP_DIR)/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_usart.c + C_SOURCES += $(HAL_DRIVER_SRC) + +# ASM sources +ASM_SOURCES = \ +$(TOP_DIR)/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Source/GCC/startup_gd32f3x0.s + +ASM_SOURCES_S = \ +$(TOP_DIR)/arch/arm/arm-v7m/cortex-m4/gcc/port_s.S + +COMPONENTS_SRC = \ + $(TOP_DIR)/components/shell/tos_shell.c \ + $(TOP_DIR)/components/shell/tos_shell_commands.c + C_SOURCES += $(COMPONENTS_SRC) + +####################################### +# binaries +####################################### +PREFIX = arm-none-eabi- +# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) +# either it can be added to the PATH environment variable. +ifdef GCC_PATH +CC = $(GCC_PATH)/$(PREFIX)gcc +AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp +CP = $(GCC_PATH)/$(PREFIX)objcopy +SZ = $(GCC_PATH)/$(PREFIX)size +else +CC = $(PREFIX)gcc +AS = $(PREFIX)gcc -x assembler-with-cpp +CP = $(PREFIX)objcopy +SZ = $(PREFIX)size +endif +HEX = $(CP) -O ihex +BIN = $(CP) -O binary -S + +####################################### +# CFLAGS +####################################### +# cpu +CPU = -mcpu=cortex-m4 + +# fpu +FPU = -mfpu=fpv4-sp-d16 + +# float-abi +FLOAT-ABI = -mfloat-abi=hard + +# mcu +MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) + +# macros for gcc +# AS defines +AS_DEFS = + +# C defines +C_DEFS = \ +-DGD32F310 + +# AS includes +AS_INCLUDES = + +# C includes +KERNEL_INC = \ + -I $(TOP_DIR)/kernel/core/include \ + -I $(TOP_DIR)/kernel/pm/include \ + -I $(TOP_DIR)/kernel/hal/include \ + -I $(TOP_DIR)/arch/arm/arm-v7m/common/include \ + -I $(TOP_DIR)/arch/arm/arm-v7m/cortex-m4/gcc \ + -I $(TOP_DIR)/board/GD32F310G_START/TOS-CONFIG +C_INCLUDES += $(KERNEL_INC) + +CMSIS_INC = \ + -I $(TOP_DIR)/osal/cmsis_os \ + -I $(TOP_DIR)/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS +C_INCLUDES += $(CMSIS_INC) + +HAL_DRIVER_INC = \ + -I $(TOP_DIR)/board/GD32F310G_START/BSP/Inc \ + -I $(TOP_DIR)/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Include \ + -I $(TOP_DIR)/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include +C_INCLUDES += $(HAL_DRIVER_INC) + +COMPONENTS_INC = \ + -I $(TOP_DIR)/components/shell/include +C_INCLUDES += $(COMPONENTS_INC) + +# compile gcc flags +ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +ifeq ($(DEBUG), 1) +CFLAGS += -g -gdwarf-2 +endif + + +# Generate dependency information +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" + + +####################################### +# LDFLAGS +####################################### +# link script +LDSCRIPT = gd32f310_flash.ld + +# libraries +LIBS = -lc -lm -lnosys +LIBDIR = +LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections + +# default action: build all +all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin + + +####################################### +# build the application +####################################### +# list of objects +OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) +vpath %.c $(sort $(dir $(C_SOURCES))) +# list of ASM program objects +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o))) +vpath %.s $(sort $(dir $(ASM_SOURCES))) +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES_S:.S=.o))) +vpath %.S $(sort $(dir $(ASM_SOURCES_S))) + +$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) + $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ + +$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) + $(AS) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/%.o: %.S Makefile | $(BUILD_DIR) + $(AS) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile + $(CC) $(OBJECTS) $(LDFLAGS) -o $@ + $(SZ) $@ + +$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(HEX) $< $@ + +$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(BIN) $< $@ + @cp $@ ./$(notdir $@) + +$(BUILD_DIR): + mkdir $@ + +####################################### +# clean up +####################################### +clean: + -rm -fR $(BUILD_DIR) + +####################################### +# dependencies +####################################### +-include $(wildcard $(BUILD_DIR)/*.d) + +# *** EOF *** diff --git a/board/GD32F310G_START/GCC/hello_world/gd32f310_flash.ld b/board/GD32F310G_START/GCC/hello_world/gd32f310_flash.ld new file mode 100644 index 000000000..a91c1e547 --- /dev/null +++ b/board/GD32F310G_START/GCC/hello_world/gd32f310_flash.ld @@ -0,0 +1,156 @@ +/* + * linker script for GD32F3x0 with GNU ld + * bernard.xiong 2009-10-14 + * iysheng 2022-04-14 + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +ENTRY(Reset_Handler) +FLASH_SIZE = 0x10000; +SRAM_SIZE = 0x2000; +HEAP_SIZE = 0x800; +STACK_SIZE = 0x200; + +MEMORY +{ + CODE (rx) : ORIGIN = 0x08000000, LENGTH = FLASH_SIZE + DATA (rw) : ORIGIN = 0x20000000, LENGTH = SRAM_SIZE + HEAP (rw) : ORIGIN = 0x20000000 + SRAM_SIZE - HEAP_SIZE, LENGTH = HEAP_SIZE +} + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = . + STACK_SIZE; + . = ALIGN(4); + _estack = .; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + *(.bss.init) + } > DATA + __bss_end = .; + + .heap : { + __heap_start__ = .; + end = __heap_start__; + _end = end; + __end = end; + . = . + HEAP_SIZE; + /* . = . + Min_Heap_Size; */ + __heap_end__ = .; + __HeapLimit = __heap_end__; + } > HEAP + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/board/GD32F310G_START/TOS-CONFIG/tickless/tos_config.h b/board/GD32F310G_START/TOS-CONFIG/tickless/tos_config.h new file mode 100644 index 000000000..e02e32a2c --- /dev/null +++ b/board/GD32F310G_START/TOS-CONFIG/tickless/tos_config.h @@ -0,0 +1,41 @@ +#ifndef _TOS_CONFIG_H_ +#define _TOS_CONFIG_H_ + +#include "stm32l4xx.h" + +#define TOS_CFG_TASK_PRIO_MAX 10u + +#define TOS_CFG_ROUND_ROBIN_EN 1u + +#define TOS_CFG_OBJECT_VERIFY_EN 1u + +#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 0u + +#define TOS_CFG_EVENT_EN 1u + +#define TOS_CFG_MMBLK_EN 1u + +#define TOS_CFG_MMHEAP_EN 1u + +#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x6000 + +#define TOS_CFG_MUTEX_EN 1u + +#define TOS_CFG_TIMER_EN 1u + +#define TOS_CFG_PWR_MGR_EN 1u + +#define TOS_CFG_TICKLESS_EN 1u + +#define TOS_CFG_SEM_EN 1u + +#define TOS_CFG_IDLE_TASK_STK_SIZE 512u + +#define TOS_CFG_CPU_TICK_PER_SECOND 1000u + +#define TOS_CFG_CPU_CLOCK (SystemCoreClock) + +#define TOS_CFG_TIMER_AS_PROC 1u + +#endif + diff --git a/board/GD32F310G_START/TOS-CONFIG/tos_config.h b/board/GD32F310G_START/TOS-CONFIG/tos_config.h new file mode 100644 index 000000000..7cf0dd30b --- /dev/null +++ b/board/GD32F310G_START/TOS-CONFIG/tos_config.h @@ -0,0 +1,47 @@ +#ifndef _TOS_CONFIG_H_ +#define _TOS_CONFIG_H_ + +#include "gd32f3x0.h" + +#define TOS_CFG_TASK_PRIO_MAX 10u + +#define TOS_CFG_ROUND_ROBIN_EN 1u + +#define TOS_CFG_OBJECT_VERIFY_EN 1u + +#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 0u + +#define TOS_CFG_EVENT_EN 1u + +#define TOS_CFG_MMBLK_EN 1u + +#define TOS_CFG_MMHEAP_EN 0u + +#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x400 + +#define TOS_CFG_MUTEX_EN 1u + +#define TOS_CFG_TIMER_EN 1u + +#define TOS_CFG_PWR_MGR_EN 0u + +#define TOS_CFG_TICKLESS_EN 0u + +#define TOS_CFG_SEM_EN 1u + +#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN 1u + +#define TOS_CFG_FAULT_BACKTRACE_EN 0u + +#define TOS_CFG_IDLE_TASK_STK_SIZE 128u + +#define TOS_CFG_CPU_TICK_PER_SECOND 1000u + +#define TOS_CFG_CPU_CLOCK (SystemCoreClock) + +#define TOS_CFG_TIMER_AS_PROC 1u + +#define TOS_CFG_MAIL_QUEUE_EN 1u + +#endif + diff --git a/board/IoTClub_EVB_L2/KEIL/mqttclient_iot_explorer/demo/mqttclient_iot_explorer.c b/board/IoTClub_EVB_L2/KEIL/mqttclient_iot_explorer/demo/mqttclient_iot_explorer.c index ff76d0ec0..a87509e77 100644 --- a/board/IoTClub_EVB_L2/KEIL/mqttclient_iot_explorer/demo/mqttclient_iot_explorer.c +++ b/board/IoTClub_EVB_L2/KEIL/mqttclient_iot_explorer/demo/mqttclient_iot_explorer.c @@ -2,7 +2,7 @@ #include "mcu_init.h" #include "tos_k.h" #include "mqttclient.h" -#include "cjson.h" +#include "cJSON.h" #include "sal_module_wrapper.h" //#define USE_ESP8266 diff --git a/board/MM32F5270/BSP/Inc/board_init.h b/board/MM32F5270/BSP/Inc/board_init.h new file mode 100644 index 000000000..9af055f0f --- /dev/null +++ b/board/MM32F5270/BSP/Inc/board_init.h @@ -0,0 +1,30 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __BOARD_INIT_H__ +#define __BOARD_INIT_H__ + +#include +#include + +#include "hal_common.h" +#include "hal_rcc.h" +#include "hal_uart.h" + +#include "clock_init.h" +#include "pin_init.h" + +/* DEBUG UART. */ +#define BOARD_DEBUG_UART_PORT UART1 +#define BOARD_DEBUG_UART_IRQ UART1_IRQn +#define BOARD_DEBUG_UART_BAUDRATE 115200u +#define BOARD_DEBUG_UART_FREQ CLOCK_APB2_FREQ + +void BOARD_Init(void); + +#endif /* __BOARD_INIT_H__ */ + diff --git a/board/MM32F5270/BSP/Inc/clock_init.h b/board/MM32F5270/BSP/Inc/clock_init.h new file mode 100644 index 000000000..180c2169d --- /dev/null +++ b/board/MM32F5270/BSP/Inc/clock_init.h @@ -0,0 +1,21 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CLOCK_INIT_H__ +#define __CLOCK_INIT_H__ + +#include "hal_common.h" + +#define CLOCK_SYS_FREQ 120000000u +#define CLOCK_SYSTICK_FREQ (CLOCK_SYS_FREQ/8u) +#define CLOCK_AHB1_FREQ 120000000u +#define CLOCK_APB1_FREQ 60000000u +#define CLOCK_APB2_FREQ 60000000u + +void BOARD_InitBootClocks(void); + +#endif /* __CLOCK_INIT_H__ */ diff --git a/board/MM32F5270/BSP/Inc/pin_init.h b/board/MM32F5270/BSP/Inc/pin_init.h new file mode 100644 index 000000000..e28b7a8c1 --- /dev/null +++ b/board/MM32F5270/BSP/Inc/pin_init.h @@ -0,0 +1,14 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PIN_INIT_H__ +#define __PIN_INIT_H__ + +void BOARD_InitPins(void); + +#endif /* __PIN_INIT_H__ */ + diff --git a/board/MM32F5270/BSP/Src/board_init.c b/board/MM32F5270/BSP/Src/board_init.c new file mode 100644 index 000000000..cc4f5e201 --- /dev/null +++ b/board/MM32F5270/BSP/Src/board_init.c @@ -0,0 +1,179 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#include "board_init.h" +#include "hal_gpio.h" +#include "tos_shell.h" + +/* +* Definitions. +*/ + +/* +* Declerations. +*/ +void BOARD_InitDebugConsole(void); + +/* +* Functions. +*/ +void BOARD_Init(void) +{ + BOARD_InitBootClocks(); + BOARD_InitPins(); + + BOARD_InitDebugConsole(); +} + +void BOARD_InitDebugConsole(void) +{ + UART_Init_Type uart_init; + + uart_init.ClockFreqHz = BOARD_DEBUG_UART_FREQ; + uart_init.BaudRate = BOARD_DEBUG_UART_BAUDRATE; + uart_init.WordLength = UART_WordLength_8b; + uart_init.StopBits = UART_StopBits_1; + uart_init.Parity = UART_Parity_None; + uart_init.XferMode = UART_XferMode_RxTx; + uart_init.HwFlowControl = UART_HwFlowControl_None; + UART_Init(BOARD_DEBUG_UART_PORT, &uart_init); + UART_EnableInterrupts(BOARD_DEBUG_UART_PORT, UART_ISR_RXINTF_MASK, true); + UART_Enable(BOARD_DEBUG_UART_PORT, true); + + NVIC_SetPriority(BOARD_DEBUG_UART_IRQ, (1UL << __NVIC_PRIO_BITS) - 2UL); +} + +#if defined(__ARMCC_VERSION) +int fputc(int c, FILE *f) +{ + (void)(f); + while ( 0u == (UART_STATUS_TX_EMPTY & UART_GetStatus(BOARD_DEBUG_UART_PORT)) ) + {} + UART_PutData(BOARD_DEBUG_UART_PORT, (uint8_t)(c)); + return c; +} + +int fgetc(FILE *f) +{ + (void)(f); + while ( 0u == (UART_STATUS_RX_DONE & UART_GetStatus(BOARD_DEBUG_UART_PORT)) ) + {} + return UART_GetData(BOARD_DEBUG_UART_PORT); +} + +#elif defined(__GNUC__) + +/* + * Called by libc stdio fwrite functions + */ +int _write(int fd, char *ptr, int len) +{ + int i = 0; + + /* + * write "len" of char from "ptr" to file id "fd" + * Return number of char written. + * + * Only work for STDOUT, STDIN, and STDERR + */ + if (fd > 2) + { + return -1; + } + + while (*ptr && (i < len)) + { + while ( 0u == (UART_STATUS_TX_EMPTY & UART_GetStatus(BOARD_DEBUG_UART_PORT)) ) + {} + UART_PutData(BOARD_DEBUG_UART_PORT, (uint8_t)(*ptr)); + i++; + ptr++; + } + + return i; +} + +/* + * Called by the libc stdio fread fucntions + * + * Implements a buffered read with line editing. + */ +int _read(int fd, char *ptr, int len) +{ + int my_len; + + if (fd > 2) + { + return -1; + } + + my_len = 0; + while (len > 0) + { + while ( 0u == (UART_STATUS_RX_DONE & UART_GetStatus(BOARD_DEBUG_UART_PORT)) ) + {} + *ptr = UART_GetData(BOARD_DEBUG_UART_PORT); + len--; + my_len++; + + if ( (*ptr == '\r') || (*ptr == '\n') || (*ptr == '\0') ) + { + break; + } + + ptr++; + } + + return my_len; /* return the length we got */ +} + + +int putchar(int c) +{ + while ( 0u == (UART_STATUS_TX_EMPTY & UART_GetStatus(BOARD_DEBUG_UART_PORT)) ) + {} + UART_PutData(BOARD_DEBUG_UART_PORT, (uint8_t)(c)); + return c; +} + +int getchar(void) +{ + while ( 0u == (UART_STATUS_RX_DONE & UART_GetStatus(BOARD_DEBUG_UART_PORT)) ) + {} + return UART_GetData(BOARD_DEBUG_UART_PORT); +} + +#elif (defined(__ICCARM__)) +/* These function __write and __read is used to support IAR toolchain to printf and scanf. */ + +int fputc(int ch, FILE *f) +{ + while ( 0u == (UART_STATUS_TX_EMPTY & UART_GetStatus(BOARD_DEBUG_UART_PORT)) ) + {} + UART_PutData(BOARD_DEBUG_UART_PORT, (uint8_t)(ch)); + return ch; +} + +int fgetc(FILE *f) +{ + while ( 0u == (UART_STATUS_RX_DONE & UART_GetStatus(BOARD_DEBUG_UART_PORT)) ) + {} + return UART_GetData(BOARD_DEBUG_UART_PORT); +} + +#endif +void UART1_IRQHandler(void) +{ + uint8_t data = 0; + if (UART_ISR_RXINTF_MASK & UART_GetInterruptStatus(BOARD_DEBUG_UART_PORT)) + { + data = UART_GetData(BOARD_DEBUG_UART_PORT); + tos_shell_input_byte(data); + } +} +/* EOF. */ diff --git a/board/MM32F5270/BSP/Src/clock_init.c b/board/MM32F5270/BSP/Src/clock_init.c new file mode 100644 index 000000000..8034d335c --- /dev/null +++ b/board/MM32F5270/BSP/Src/clock_init.c @@ -0,0 +1,117 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_common.h" +#include "clock_init.h" +#include "tos_k.h" +#include "tos_shell.h" + +#include "hal_rcc.h" + +void CLOCK_ResetToDefault(void); +void CLOCK_BootToHSI96MHz(void); +void CLOCK_BootToHSE96MHz(void); +void CLOCK_BootToHSE120MHz(void); + +void BOARD_InitBootClocks(void) +{ + CLOCK_ResetToDefault(); + CLOCK_BootToHSE120MHz(); + + /* UART1. */ + RCC_EnableAPB2Periphs(RCC_APB2_PERIPH_UART1, true); + RCC_ResetAPB2Periphs(RCC_APB2_PERIPH_UART1); + + /* GPIOB. */ + RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOB, true); + RCC_ResetAHB1Periphs(RCC_AHB1_PERIPH_GPIOB); + + /* GPIOI. */ + RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOI, true); + RCC_ResetAHB1Periphs(RCC_AHB1_PERIPH_GPIOI); +} + +/* Switch to HSI. */ +void CLOCK_ResetToDefault(void) +{ + /* Switch to HSI. */ + RCC->CR |= RCC_CR_HSION_MASK; /* Make sure the HSI is enabled. */ + while ( RCC_CR_HSIRDY_MASK != (RCC->CR & RCC_CR_HSIRDY_MASK) ) + { + } + RCC->CFGR = RCC_CFGR_SW(0u); /* Reset other clock sources and switch to HSI. */ + while ( RCC_CFGR_SWS(0u) != (RCC->CFGR & RCC_CFGR_SWS_MASK) ) /* Wait while the SYSCLK is switch to the HSI. */ + { + } + + /* Reset all other clock sources. */ + RCC->CR = RCC_CR_HSION_MASK; + + /* Disable all interrupts and clear pending bits. */ + RCC->CIR = RCC->CIR; /* clear flags. */ + RCC->CIR = 0u; /* disable interrupts. */ +} + +/* Enable the PLL1 and use the HSE as input clock source. */ +void CLOCK_BootToHSE120MHz(void) +{ + RCC->APB1ENR |= (1u << 28u); /* enable PWR/DBG. */ + PWR->CR1 = (PWR->CR1 & ~PWR_CR1_VOS_MASK) | PWR_CR1_VOS(3u); /* 1.7V. */ + + /* enable HSE. */ + RCC->CR |= RCC_CR_HSEON_MASK; + while ( RCC_CR_HSERDY_MASK != (RCC->CR & RCC_CR_HSERDY_MASK) ) + { + } + + RCC->PLL1CFGR = RCC_PLL1CFGR_PLL1SRC(1) /* (pllsrc == 1) ? HSE : HSI. */ + | RCC_PLL1CFGR_PLL1MUL(19) /* (12 * (19 + 1)) / 2 = 120. */ + | RCC_PLL1CFGR_PLL1DIV(1) + | RCC_PLL1CFGR_PLL1LDS(1) + | RCC_PLL1CFGR_PLL1ICTRL(3) + ; + + /* Enable PLL1. */ + RCC->CR |= RCC_CR_PLL1ON_MASK; + while((RCC->CR & RCC_CR_PLL1RDY_MASK) == 0) + { + } + + /* Enable the FLASH prefetch. */ + RCC->AHB1ENR |= (1u << 13u); /* enable the access to FLASH. */ + FLASH->ACR = FLASH_ACR_LATENCY(4u) /* setup divider. */ + | FLASH_ACR_PRFTBE_MASK /* enable flash prefetch. */ + ; + + /* Setup the dividers for each bus. */ + RCC->CFGR = RCC_CFGR_HPRE(0) /* div=1 for AHB freq. */ + | RCC_CFGR_PPRE1(0x4) /* div=2 for APB1 freq. */ + | RCC_CFGR_PPRE2(0x4) /* div=2 for APB2 freq. */ + | RCC_CFGR_MCO(7) /* use PLL1 as output. */ + ; + + /* Switch the system clock source to PLL. */ + RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW(2); /* use PLL as SYSCLK */ + + + /* Wait till PLL is used as system clock source. */ + while ( (RCC->CFGR & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS(2) ) + { + } +} + +void SysTick_Handler(void) +{ + if (tos_knl_is_running()) + { + tos_knl_irq_enter(); + tos_tick_handler(); + tos_knl_irq_leave(); + } +} + +/* EOF. */ diff --git a/board/MM32F5270/BSP/Src/pin_init.c b/board/MM32F5270/BSP/Src/pin_init.c new file mode 100644 index 000000000..b08037f9d --- /dev/null +++ b/board/MM32F5270/BSP/Src/pin_init.c @@ -0,0 +1,37 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "pin_init.h" +#include "hal_rcc.h" +#include "hal_gpio.h" + +void BOARD_InitPins(void) +{ + /* PB7 - UART1_TX. */ + GPIO_Init_Type gpio_init; + gpio_init.Pins = GPIO_PIN_6; + gpio_init.PinMode = GPIO_PinMode_AF_PushPull; //GPIO_PinMode_AF_PushPull + gpio_init.Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOB, &gpio_init); + GPIO_PinAFConf(GPIOB, gpio_init.Pins, GPIO_AF_7); + + /* PB6 - UART1_RX. */ + gpio_init.Pins = GPIO_PIN_7; + gpio_init.PinMode = GPIO_PinMode_In_Floating; //GPIO_PinMode_In_Floating + gpio_init.Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOB, &gpio_init); + GPIO_PinAFConf(GPIOB, gpio_init.Pins, GPIO_AF_7); + + /* PI0 - GPIO. */ + gpio_init.Pins = GPIO_PIN_0; + gpio_init.PinMode = GPIO_PinMode_Out_PushPull; + gpio_init.Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOI, &gpio_init); + GPIO_WriteBit(GPIOI, GPIO_PIN_0, 1); +} + +/* EOF. */ diff --git a/board/MM32F5270/BSP/Src/syscalls.c b/board/MM32F5270/BSP/Src/syscalls.c new file mode 100644 index 000000000..9f32dad0e --- /dev/null +++ b/board/MM32F5270/BSP/Src/syscalls.c @@ -0,0 +1,184 @@ +/** +***************************************************************************** +** +** File : syscalls.c +** +** Author : Auto-generated by STM32CubeIDE +** +** Abstract : STM32CubeIDE Minimal System calls file +** +** For more information about which c-functions +** need which of these lowlevel functions +** please consult the Newlib libc-manual +** +** Environment : STM32CubeIDE MCU +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +***************************************************************************** +** +**

© COPYRIGHT(c) 2018 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +***************************************************************************** +*/ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +//#undef errno +extern int errno; +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + +register char * stack_ptr asm("sp"); + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + +return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + return 0; +} + +int _open(char *path, int flags, ...) +{ + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + return -1; +} + +int _stat(char *file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + errno = ENOMEM; + return -1; +} diff --git a/board/MM32F5270/GCC/hello_world/Makefile b/board/MM32F5270/GCC/hello_world/Makefile new file mode 100644 index 000000000..00da3a0cc --- /dev/null +++ b/board/MM32F5270/GCC/hello_world/Makefile @@ -0,0 +1,234 @@ +########################################################################################################################## +# File automatically-generated by tool: [projectgenerator] version: [3.3.0] date: [Mon Aug 05 10:29:11 CST 2019] +########################################################################################################################## + +# ------------------------------------------------ +# Generic Makefile (based on gcc) +# +# ChangeLog : +# 2022-08-17 - Port to MM32F250 +# 2022-04-13 - Port to GD32F310-START +# 2017-02-10 - Several enhancements + project update mode +# 2015-07-22 - first version +# ------------------------------------------------ + +###################################### +# target +###################################### +TARGET = TencentOS_tiny + + +###################################### +# building variables +###################################### +# debug build? +DEBUG = 1 +# optimization +OPT = -O0 + +TOP_DIR = ../../../.. +####################################### +# paths +####################################### +# Build path +BUILD_DIR = build + +###################################### +# source +###################################### +# C sources +KERNEL_SRC = \ + ${wildcard $(TOP_DIR)/kernel/core/*.c} + C_SOURCES += $(KERNEL_SRC) + +ARCH_SRC = \ + ${wildcard $(TOP_DIR)/arch/arm/arm-v8m/star-mc1/gcc/*.c} \ + ${wildcard $(TOP_DIR)/arch/arm/arm-v8m/common/*.c} + C_SOURCES += $(ARCH_SRC) + +BOARD_SRC = \ + ${wildcard $(TOP_DIR)/board/MM32F5270/BSP/Src/*.c} \ + ${wildcard $(TOP_DIR)/board/MM32F5270/GCC/hello_world/main.c} + +HAL_DRIVER_SRC = $(BOARD_SRC) \ + $(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/system_mm32f5277e.c \ + $(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_dma.c \ + $(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_exti.c \ + $(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_gpio.c \ + $(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_power.c \ + $(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_rcc.c \ + $(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_syscfg.c \ + $(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_tim.c \ + $(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_uart.c + +C_SOURCES += $(HAL_DRIVER_SRC) + +# ASM sources +ASM_SOURCES_S = \ +$(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/armgcc/startup_mm32f5277e.S + +ASM_SOURCES_S += \ +$(TOP_DIR)/arch/arm/arm-v8m/star-mc1/gcc/port_s.S + +COMPONENTS_SRC = \ + $(TOP_DIR)/components/shell/tos_shell.c \ + $(TOP_DIR)/components/shell/tos_shell_commands.c + C_SOURCES += $(COMPONENTS_SRC) + +####################################### +# binaries +####################################### +PREFIX = arm-none-eabi- +# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) +# either it can be added to the PATH environment variable. +ifdef GCC_PATH +CC = $(GCC_PATH)/$(PREFIX)gcc +AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp +CP = $(GCC_PATH)/$(PREFIX)objcopy +SZ = $(GCC_PATH)/$(PREFIX)size +else +CC = $(PREFIX)gcc +AS = $(PREFIX)gcc -x assembler-with-cpp +CP = $(PREFIX)objcopy +SZ = $(PREFIX)size +endif +HEX = $(CP) -O ihex +BIN = $(CP) -O binary -S + +####################################### +# CFLAGS +####################################### +# cpu +CPU = -mcpu=cortex-m33 + +# fpu +FPU = -mfpu=fpv4-sp-d16 + +# float-abi +FLOAT-ABI = -mfloat-abi=hard + +# asm extra flags +ASM_EXTRA_FLAGS = -DDEBUG -D__STARTUP_CLEAR_BSS -D__STARTUP_INITIALIZE_NONCACHEDATA -g -fno-common -ffreestanding -fno-builtin -mapcs -std=gnu99 + +# C extra flags +C_EXTRA_FLAGS = -MMD -MP -fno-common -ffreestanding -fno-builtin -mapcs -std=gnu99 + +# C++ extra flags +CXX_EXTRA_FLAGS = -MMD -MP -fno-common -ffreestanding -fno-builtin -mapcs -fno-rtti -fno-exceptions + +# mcu +MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) + +# macros for gcc +# AS defines +AS_DEFS = + +# C defines +C_DEFS = \ +-DMM32F5270 + +# AS includes +AS_INCLUDES = + +# C includes +KERNEL_INC = \ + -I $(TOP_DIR)/kernel/core/include \ + -I $(TOP_DIR)/kernel/pm/include \ + -I $(TOP_DIR)/kernel/hal/include \ + -I $(TOP_DIR)/arch/arm/arm-v8m/common/include \ + -I $(TOP_DIR)/arch/arm/arm-v8m/star-mc1/gcc \ + -I $(TOP_DIR)/board/MM32F5270/TOS-CONFIG +C_INCLUDES += $(KERNEL_INC) + +CMSIS_INC = \ + -I $(TOP_DIR)/osal/cmsis_os \ + -I $(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527 \ + -I $(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include + +C_INCLUDES += $(CMSIS_INC) + +HAL_DRIVER_INC = \ + -I $(TOP_DIR)/board/MM32F5270/BSP/Inc \ + -I $(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/drivers +C_INCLUDES += $(HAL_DRIVER_INC) + +COMPONENTS_INC = \ + -I $(TOP_DIR)/components/shell/include +C_INCLUDES += $(COMPONENTS_INC) + +# compile gcc flags +ASFLAGS = $(MCU) $(ASM_EXTRA_FLAGS) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CFLAGS = $(MCU) $(C_EXTRA_FLAGS) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +ifeq ($(DEBUG), 1) +CFLAGS += -g -gdwarf-2 +endif + + +# Generate dependency information +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" + + +####################################### +# LDFLAGS +####################################### +# link script +LDSCRIPT = $(TOP_DIR)/platform/vendor_bsp/MindMotion/MM32F527/armgcc/linker/mm32f5277e_flash.ld + +# libraries +LIBS = -lc -lm -lnosys +LIBDIR = +LDFLAGS = $(MCU) -specs=nosys.specs -specs=nano.specs -fno-common -ffunction-sections -fdata-sections -ffreestanding -fno-builtin -mthumb -mapcs -Xlinker --gc-sections -Xlinker -static -Xlinker -z -Xlinker muldefs -Xlinker -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections + +# default action: build all +all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin + + +####################################### +# build the application +####################################### +# list of objects +OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) +vpath %.c $(sort $(dir $(C_SOURCES))) +# list of ASM program objects +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o))) +vpath %.s $(sort $(dir $(ASM_SOURCES))) +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES_S:.S=.o))) +vpath %.S $(sort $(dir $(ASM_SOURCES_S))) + +$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) + $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ + +$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) + $(AS) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/%.o: %.S Makefile | $(BUILD_DIR) + $(AS) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile + $(CC) $(OBJECTS) $(LDFLAGS) -o $@ + $(SZ) $@ + +$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(HEX) $< $@ + +$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(BIN) $< $@ + @cp $@ ./$(notdir $@) + +$(BUILD_DIR): + mkdir $@ + +####################################### +# clean up +####################################### +clean: + -rm -fR $(BUILD_DIR) + +####################################### +# dependencies +####################################### +-include $(wildcard $(BUILD_DIR)/*.d) + +# *** EOF *** diff --git a/board/MM32F5270/GCC/hello_world/main.c b/board/MM32F5270/GCC/hello_world/main.c new file mode 100644 index 000000000..6caaa0dbf --- /dev/null +++ b/board/MM32F5270/GCC/hello_world/main.c @@ -0,0 +1,57 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "board_init.h" +#include "tos_shell.h" +#include "hal_gpio.h" + +#define APPLICATION_TASK_STK_SIZE 0x1000 +k_task_t application_task; +uint8_t application_task_stk[APPLICATION_TASK_STK_SIZE]; +static char gs_cmd_buffer[32]; + +__attribute__ ((__weak__)) void application_entry(void *arg) +{ + NVIC_EnableIRQ(BOARD_DEBUG_UART_IRQ); + while (1) { + GPIO_WriteBit(GPIOI, GPIO_PIN_0, 0); + tos_task_delay(1000); + GPIO_WriteBit(GPIOI, GPIO_PIN_0, 1); + tos_task_delay(1000); + } +} + +static void board_shell_output_t(const char ch) +{ + if (ch == '\n') + { + while ( 0u == (UART_STATUS_TX_EMPTY & UART_GetStatus(BOARD_DEBUG_UART_PORT)) ) + {} + UART_PutData(BOARD_DEBUG_UART_PORT, '\r'); + } + while ( 0u == (UART_STATUS_TX_EMPTY & UART_GetStatus(BOARD_DEBUG_UART_PORT)) ) + {} + UART_PutData(BOARD_DEBUG_UART_PORT, ch); +} + +/* + * Functions. + */ +int main(void) +{ + BOARD_Init(); + + tos_knl_init(); + tos_task_create(&application_task, "main_task", application_entry, NULL, 1, application_task_stk, APPLICATION_TASK_STK_SIZE, 0); + tos_shell_init(gs_cmd_buffer, sizeof(gs_cmd_buffer), board_shell_output_t, NULL); + tos_knl_start(); + + return 0; +} + +/* EOF. */ + diff --git a/board/MM32F5270/GCC/hello_world/readme.md b/board/MM32F5270/GCC/hello_world/readme.md new file mode 100644 index 000000000..4db4a9554 --- /dev/null +++ b/board/MM32F5270/GCC/hello_world/readme.md @@ -0,0 +1,12 @@ +# hello_world + +## 实验过程 + ++ 打印“tshell>” ++ 用户通过串口向设备发送任意字符,设备通过串口返回用户发送的字符。 + +## 实验结果 + +tshell>ps + +LED4 以周期 1s 闪烁 diff --git a/board/MM32F5270/TOS-CONFIG/tickless/tos_config.h b/board/MM32F5270/TOS-CONFIG/tickless/tos_config.h new file mode 100644 index 000000000..e02e32a2c --- /dev/null +++ b/board/MM32F5270/TOS-CONFIG/tickless/tos_config.h @@ -0,0 +1,41 @@ +#ifndef _TOS_CONFIG_H_ +#define _TOS_CONFIG_H_ + +#include "stm32l4xx.h" + +#define TOS_CFG_TASK_PRIO_MAX 10u + +#define TOS_CFG_ROUND_ROBIN_EN 1u + +#define TOS_CFG_OBJECT_VERIFY_EN 1u + +#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 0u + +#define TOS_CFG_EVENT_EN 1u + +#define TOS_CFG_MMBLK_EN 1u + +#define TOS_CFG_MMHEAP_EN 1u + +#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x6000 + +#define TOS_CFG_MUTEX_EN 1u + +#define TOS_CFG_TIMER_EN 1u + +#define TOS_CFG_PWR_MGR_EN 1u + +#define TOS_CFG_TICKLESS_EN 1u + +#define TOS_CFG_SEM_EN 1u + +#define TOS_CFG_IDLE_TASK_STK_SIZE 512u + +#define TOS_CFG_CPU_TICK_PER_SECOND 1000u + +#define TOS_CFG_CPU_CLOCK (SystemCoreClock) + +#define TOS_CFG_TIMER_AS_PROC 1u + +#endif + diff --git a/board/MM32F5270/TOS-CONFIG/tos_config.h b/board/MM32F5270/TOS-CONFIG/tos_config.h new file mode 100644 index 000000000..67a699818 --- /dev/null +++ b/board/MM32F5270/TOS-CONFIG/tos_config.h @@ -0,0 +1,47 @@ +#ifndef _TOS_CONFIG_H_ +#define _TOS_CONFIG_H_ + +#include "mm32f5277e.h" + +#define TOS_CFG_TASK_PRIO_MAX 10u + +#define TOS_CFG_ROUND_ROBIN_EN 1u + +#define TOS_CFG_OBJECT_VERIFY_EN 1u + +#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 0u + +#define TOS_CFG_EVENT_EN 1u + +#define TOS_CFG_MMBLK_EN 1u + +#define TOS_CFG_MMHEAP_EN 0u + +#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x400 + +#define TOS_CFG_MUTEX_EN 1u + +#define TOS_CFG_TIMER_EN 1u + +#define TOS_CFG_PWR_MGR_EN 0u + +#define TOS_CFG_TICKLESS_EN 0u + +#define TOS_CFG_SEM_EN 1u + +#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN 1u + +#define TOS_CFG_FAULT_BACKTRACE_EN 1u + +#define TOS_CFG_IDLE_TASK_STK_SIZE 1024u + +#define TOS_CFG_CPU_TICK_PER_SECOND 1000u + +#define TOS_CFG_CPU_CLOCK (120000000) + +#define TOS_CFG_TIMER_AS_PROC 1u + +#define TOS_CFG_MAIL_QUEUE_EN 1u + +#endif + diff --git a/board/NUCLEO_STM32L496ZG/KEIL/hello_world/TencentOS_tiny.uvoptx b/board/NUCLEO_STM32L496ZG/KEIL/hello_world/TencentOS_tiny.uvoptx index 0e380e212..98d67ccec 100644 --- a/board/NUCLEO_STM32L496ZG/KEIL/hello_world/TencentOS_tiny.uvoptx +++ b/board/NUCLEO_STM32L496ZG/KEIL/hello_world/TencentOS_tiny.uvoptx @@ -12,7 +12,7 @@ *.lib *.txt; *.h; *.inc *.plm - *.cpp + *.cpp;*.cc 0 @@ -26,7 +26,7 @@ 0x4 ARM-ADS - 80000000 + 8000000 1 1 @@ -93,7 +93,7 @@ 1 1 1 - 1 + 0 1 1 1 @@ -119,72 +119,28 @@ 0 - ARMRTXEVENTFLAGS - -L70 -Z18 -C0 -M0 -T1 - - - 0 - DLGTARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) - - - 0 - ARMDBGFLAGS - - - - 0 - DLGUARM - (105=-1,-1,-1,-1,0) + ST-LINKIII-KEIL_SWO + -U0667FF343339415043053749 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(2BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32L496ZGTx$CMSIS\Flash\STM32L4xx_1024.FLM) 0 UL2CM3 UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32L496ZGTx$CMSIS\Flash\STM32L4xx_1024.FLM)) - - 0 - ST-LINKIII-KEIL_SWO - -U0674FF525750877267153432 -O2254 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32L496ZGTx$CMSIS\Flash\STM32L4xx_1024.FLM) - - - - 0 - 0 - 573 - 1 -
134226432
- 0 - 0 - 0 - 0 - 0 - 1 - ..\..\..\..\kernel\core\tos_mmheap.c - - \\TencentOS_tiny\../../../../kernel/core/tos_mmheap.c\573 -
-
- - - 0 - 1 - k_mmheap_default_pool - - + 0 0 - 1 - 1 + 0 + 0 0 0 0 0 - 1 + 0 0 0 0 @@ -247,7 +203,7 @@ Application/User - 1 + 0 0 0 0 @@ -258,8 +214,8 @@ 0 0 0 - ..\..\BSP\Src\gpio.c - gpio.c + ..\..\BSP\Src\main.c + main.c 0 0 @@ -270,8 +226,8 @@ 0 0 0 - ..\..\BSP\Src\main.c - main.c + ..\..\BSP\Src\gpio.c + gpio.c 0 0 @@ -335,6 +291,66 @@ 0 0 + + 2 + 9 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\dcmi.c + dcmi.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\dma.c + dma.c + 0 + 0 + + + 2 + 11 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\i2c.c + i2c.c + 0 + 0 + + + 2 + 12 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\spi.c + spi.c + 0 + 0 + + + 2 + 13 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\tim.c + tim.c + 0 + 0 + @@ -345,7 +361,7 @@ 0 3 - 9 + 14 1 0 0 @@ -357,7 +373,7 @@ 3 - 10 + 15 1 0 0 @@ -369,7 +385,7 @@ 3 - 11 + 16 1 0 0 @@ -381,7 +397,7 @@ 3 - 12 + 17 1 0 0 @@ -393,7 +409,7 @@ 3 - 13 + 18 1 0 0 @@ -405,7 +421,7 @@ 3 - 14 + 19 1 0 0 @@ -417,7 +433,7 @@ 3 - 15 + 20 1 0 0 @@ -429,7 +445,7 @@ 3 - 16 + 21 1 0 0 @@ -441,7 +457,7 @@ 3 - 17 + 22 1 0 0 @@ -453,7 +469,7 @@ 3 - 18 + 23 1 0 0 @@ -465,7 +481,7 @@ 3 - 19 + 24 1 0 0 @@ -477,7 +493,7 @@ 3 - 20 + 25 1 0 0 @@ -489,7 +505,7 @@ 3 - 21 + 26 1 0 0 @@ -501,7 +517,7 @@ 3 - 22 + 27 1 0 0 @@ -513,7 +529,7 @@ 3 - 23 + 28 1 0 0 @@ -525,7 +541,7 @@ 3 - 24 + 29 1 0 0 @@ -537,7 +553,7 @@ 3 - 25 + 30 1 0 0 @@ -549,7 +565,7 @@ 3 - 26 + 31 1 0 0 @@ -561,7 +577,7 @@ 3 - 27 + 32 1 0 0 @@ -571,6 +587,42 @@ 0 0 + + 3 + 33 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dcmi.c + stm32l4xx_hal_dcmi.c + 0 + 0 + + + 3 + 34 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c + stm32l4xx_hal_spi.c + 0 + 0 + + + 3 + 35 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c + stm32l4xx_hal_spi_ex.c + 0 + 0 + @@ -581,7 +633,7 @@ 0 4 - 28 + 36 1 0 0 @@ -601,7 +653,7 @@ 0 5 - 29 + 37 1 0 0 @@ -613,7 +665,7 @@ 5 - 30 + 38 1 0 0 @@ -625,7 +677,7 @@ 5 - 31 + 39 2 0 0 @@ -645,7 +697,7 @@ 0 6 - 32 + 40 1 0 0 @@ -657,7 +709,7 @@ 6 - 33 + 41 1 0 0 @@ -669,7 +721,7 @@ 6 - 34 + 42 1 0 0 @@ -681,7 +733,7 @@ 6 - 35 + 43 1 0 0 @@ -693,7 +745,7 @@ 6 - 36 + 44 1 0 0 @@ -705,7 +757,7 @@ 6 - 37 + 45 1 0 0 @@ -717,7 +769,7 @@ 6 - 38 + 46 1 0 0 @@ -729,7 +781,7 @@ 6 - 39 + 47 1 0 0 @@ -741,7 +793,7 @@ 6 - 40 + 48 1 0 0 @@ -753,7 +805,7 @@ 6 - 41 + 49 1 0 0 @@ -765,7 +817,7 @@ 6 - 42 + 50 1 0 0 @@ -777,7 +829,7 @@ 6 - 43 + 51 1 0 0 @@ -789,7 +841,7 @@ 6 - 44 + 52 1 0 0 @@ -801,7 +853,7 @@ 6 - 45 + 53 1 0 0 @@ -813,7 +865,7 @@ 6 - 46 + 54 1 0 0 @@ -825,7 +877,7 @@ 6 - 47 + 55 1 0 0 @@ -837,7 +889,7 @@ 6 - 48 + 56 1 0 0 @@ -849,7 +901,7 @@ 6 - 49 + 57 1 0 0 @@ -861,7 +913,7 @@ 6 - 50 + 58 1 0 0 @@ -873,7 +925,7 @@ 6 - 51 + 59 1 0 0 @@ -885,7 +937,7 @@ 6 - 52 + 60 1 0 0 @@ -897,7 +949,7 @@ 6 - 53 + 61 1 0 0 @@ -909,7 +961,7 @@ 6 - 54 + 62 1 0 0 @@ -921,7 +973,7 @@ 6 - 55 + 63 1 0 0 @@ -941,7 +993,7 @@ 0 7 - 56 + 64 1 0 0 @@ -954,14 +1006,82 @@ - examples + hal 0 0 0 0 8 - 57 + 65 + 1 + 0 + 0 + 0 + ..\..\BSP\Hardware\Src\delay.c + delay.c + 0 + 0 + + + 8 + 66 + 1 + 0 + 0 + 0 + ..\..\BSP\Hardware\Src\lcd_2inch4.c + lcd_2inch4.c + 0 + 0 + + + 8 + 67 + 1 + 0 + 0 + 0 + ..\..\BSP\Hardware\Src\lcd_config.c + lcd_config.c + 0 + 0 + + + 8 + 68 + 1 + 0 + 0 + 0 + ..\..\BSP\Hardware\Src\ov2640.c + ov2640.c + 0 + 0 + + + 8 + 69 + 1 + 0 + 0 + 0 + ..\..\BSP\Hardware\Src\sccb.c + sccb.c + 0 + 0 + + + + + examples + 1 + 0 + 0 + 0 + + 9 + 70 1 0 0 diff --git a/board/NUCLEO_STM32L496ZG/KEIL/hello_world/TencentOS_tiny.uvprojx b/board/NUCLEO_STM32L496ZG/KEIL/hello_world/TencentOS_tiny.uvprojx index 061d5924b..177e44a33 100644 --- a/board/NUCLEO_STM32L496ZG/KEIL/hello_world/TencentOS_tiny.uvprojx +++ b/board/NUCLEO_STM32L496ZG/KEIL/hello_world/TencentOS_tiny.uvprojx @@ -10,14 +10,14 @@ TencentOS_tiny 0x4 ARM-ADS - 5060750::V5.06 update 6 (build 750)::.\ARMCC - 0 + 6140000::V6.14::ARMCLANG + 1 STM32L496ZGTx STMicroelectronics - Keil.STM32L4xx_DFP.2.4.0 - http://www.keil.com/pack/ + Keil.STM32L4xx_DFP.2.5.0 + https://www.keil.com/pack/ IRAM(0x20000000-0x2004FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4") @@ -54,7 +54,7 @@ 0 1 1 - 0 + 1 1 0 @@ -137,7 +137,7 @@ 4107 1 - STLink\ST-LINKIII-KEIL_SWO.dll + BIN\UL2CM3.DLL @@ -322,14 +322,14 @@ 0 0 0 - 2 + 3 0 0 1 0 0 - 1 - 1 + 3 + 3 1 1 0 @@ -337,9 +337,9 @@ 0 - USE_HAL_DRIVER,STM32L496xx + USE_HAL_DRIVER,STM32L496xx,NUCLEO_STM32L496ZG - ..\..\BSP\Inc;..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Inc;..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Inc\Legacy;..\..\..\..\platform\vendor_bsp\st\CMSIS\Device\ST\STM32L4xx\Include;..\..\..\..\platform\vendor_bsp\st\CMSIS\Include;..\..\..\..\arch\arm\arm-v7m\common\include;..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc;..\..\..\..\kernel\core\include;..\..\..\..\kernel\pm\include;..\..\..\..\osal\cmsis_os;..\..\..\..\examples\hello_world;..\..\TOS_CONFIG;..\..\..\..\net\at\include;..\..\..\..\kernel\hal\include + ..\..\BSP\Inc;..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Inc;..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Inc\Legacy;..\..\..\..\platform\vendor_bsp\st\CMSIS\Device\ST\STM32L4xx\Include;..\..\..\..\platform\vendor_bsp\st\CMSIS\Include;..\..\..\..\arch\arm\arm-v7m\common\include;..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc;..\..\..\..\kernel\core\include;..\..\..\..\kernel\pm\include;..\..\..\..\osal\cmsis_os;..\..\..\..\examples\hello_world;..\..\TOS_CONFIG;..\..\..\..\net\at\include;..\..\..\..\kernel\hal\include;..\..\BSP\Hardware\Inc @@ -394,14 +394,14 @@ Application/User - gpio.c + main.c 1 - ..\..\BSP\Src\gpio.c + ..\..\BSP\Src\main.c - main.c + gpio.c 1 - ..\..\BSP\Src\main.c + ..\..\BSP\Src\gpio.c stm32l4xx_hal_msp.c @@ -428,6 +428,31 @@ 1 ..\..\BSP\Src\mcu_init.c + + dcmi.c + 1 + ..\..\BSP\Src\dcmi.c + + + dma.c + 1 + ..\..\BSP\Src\dma.c + + + i2c.c + 1 + ..\..\BSP\Src\i2c.c + + + spi.c + 1 + ..\..\BSP\Src\spi.c + + + tim.c + 1 + ..\..\BSP\Src\tim.c + @@ -528,6 +553,21 @@ 1 ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c + + stm32l4xx_hal_dcmi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dcmi.c + + + stm32l4xx_hal_spi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c + + + stm32l4xx_hal_spi_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c + @@ -695,6 +735,36 @@ + + hal + + + delay.c + 1 + ..\..\BSP\Hardware\Src\delay.c + + + lcd_2inch4.c + 1 + ..\..\BSP\Hardware\Src\lcd_2inch4.c + + + lcd_config.c + 1 + ..\..\BSP\Hardware\Src\lcd_config.c + + + ov2640.c + 1 + ..\..\BSP\Hardware\Src\ov2640.c + + + sccb.c + 1 + ..\..\BSP\Hardware\Src\sccb.c + + + examples @@ -715,8 +785,8 @@ - - + + diff --git a/board/NUCLEO_STM32L496ZG/KEIL/nnom_mnist/TencentOS_tiny.uvoptx b/board/NUCLEO_STM32L496ZG/KEIL/nnom_mnist/TencentOS_tiny.uvoptx new file mode 100644 index 000000000..371596860 --- /dev/null +++ b/board/NUCLEO_STM32L496ZG/KEIL/nnom_mnist/TencentOS_tiny.uvoptx @@ -0,0 +1,1492 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp;*.cc + 0 + + + + 0 + 0 + + + + TencentOS_tiny + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U0667FF343339415043053749 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(2BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO31 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32L496ZGTx$CMSIS\Flash\STM32L4xx_1024.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32L496ZGTx$CMSIS\Flash\STM32L4xx_1024.FLM)) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Application/MDK-ARM + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + startup_stm32l496xx.s + startup_stm32l496xx.s + 0 + 0 + + + + + Application/User + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\main.c + main.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\gpio.c + gpio.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\stm32l4xx_hal_msp.c + stm32l4xx_hal_msp.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\stm32l4xx_it.c + stm32l4xx_it.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\sys.c + sys.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\usart.c + usart.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\mcu_init.c + mcu_init.c + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\dcmi.c + dcmi.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\dma.c + dma.c + 0 + 0 + + + 2 + 11 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\i2c.c + i2c.c + 0 + 0 + + + 2 + 12 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\spi.c + spi.c + 0 + 0 + + + 2 + 13 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\tim.c + tim.c + 0 + 0 + + + + + Drivers/STM32L4xx_HAL_Driver + 0 + 0 + 0 + 0 + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c + stm32l4xx_hal_uart.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c + stm32l4xx_hal_uart_ex.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c + stm32l4xx_hal.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c + stm32l4xx_hal_i2c.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c + stm32l4xx_hal_i2c_ex.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c + stm32l4xx_hal_rcc.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c + stm32l4xx_hal_rcc_ex.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c + stm32l4xx_hal_flash.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c + stm32l4xx_hal_flash_ex.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c + stm32l4xx_hal_flash_ramfunc.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c + stm32l4xx_hal_gpio.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c + stm32l4xx_hal_dma.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c + stm32l4xx_hal_dma_ex.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c + stm32l4xx_hal_pwr.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c + stm32l4xx_hal_pwr_ex.c + 0 + 0 + + + 3 + 29 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c + stm32l4xx_hal_cortex.c + 0 + 0 + + + 3 + 30 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c + stm32l4xx_hal_exti.c + 0 + 0 + + + 3 + 31 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c + stm32l4xx_hal_tim.c + 0 + 0 + + + 3 + 32 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c + stm32l4xx_hal_tim_ex.c + 0 + 0 + + + 3 + 33 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dcmi.c + stm32l4xx_hal_dcmi.c + 0 + 0 + + + 3 + 34 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c + stm32l4xx_hal_spi.c + 0 + 0 + + + 3 + 35 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c + stm32l4xx_hal_spi_ex.c + 0 + 0 + + + + + Drivers/CMSIS + 0 + 0 + 0 + 0 + + 4 + 36 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\system_stm32l4xx.c + system_stm32l4xx.c + 0 + 0 + + + + + tos/arch + 0 + 0 + 0 + 0 + + 5 + 37 + 1 + 0 + 0 + 0 + ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c + tos_cpu.c + 0 + 0 + + + 5 + 38 + 1 + 0 + 0 + 0 + ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_c.c + port_c.c + 0 + 0 + + + 5 + 39 + 2 + 0 + 0 + 0 + ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_s.S + port_s.S + 0 + 0 + + + + + tos/kernel + 0 + 0 + 0 + 0 + + 6 + 40 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_binary_heap.c + tos_binary_heap.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_char_fifo.c + tos_char_fifo.c + 0 + 0 + + + 6 + 42 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_completion.c + tos_completion.c + 0 + 0 + + + 6 + 43 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_countdownlatch.c + tos_countdownlatch.c + 0 + 0 + + + 6 + 44 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_event.c + tos_event.c + 0 + 0 + + + 6 + 45 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_global.c + tos_global.c + 0 + 0 + + + 6 + 46 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_mail_queue.c + tos_mail_queue.c + 0 + 0 + + + 6 + 47 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_message_queue.c + tos_message_queue.c + 0 + 0 + + + 6 + 48 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_mmblk.c + tos_mmblk.c + 0 + 0 + + + 6 + 49 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_mmheap.c + tos_mmheap.c + 0 + 0 + + + 6 + 50 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_mutex.c + tos_mutex.c + 0 + 0 + + + 6 + 51 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_pend.c + tos_pend.c + 0 + 0 + + + 6 + 52 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_priority_mail_queue.c + tos_priority_mail_queue.c + 0 + 0 + + + 6 + 53 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_priority_message_queue.c + tos_priority_message_queue.c + 0 + 0 + + + 6 + 54 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_priority_queue.c + tos_priority_queue.c + 0 + 0 + + + 6 + 55 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_ring_queue.c + tos_ring_queue.c + 0 + 0 + + + 6 + 56 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_robin.c + tos_robin.c + 0 + 0 + + + 6 + 57 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_sched.c + tos_sched.c + 0 + 0 + + + 6 + 58 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_sem.c + tos_sem.c + 0 + 0 + + + 6 + 59 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_sys.c + tos_sys.c + 0 + 0 + + + 6 + 60 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_task.c + tos_task.c + 0 + 0 + + + 6 + 61 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_tick.c + tos_tick.c + 0 + 0 + + + 6 + 62 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_time.c + tos_time.c + 0 + 0 + + + 6 + 63 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_timer.c + tos_timer.c + 0 + 0 + + + + + tos/cmsis_os + 0 + 0 + 0 + 0 + + 7 + 64 + 1 + 0 + 0 + 0 + ..\..\..\..\osal\cmsis_os\cmsis_os.c + cmsis_os.c + 0 + 0 + + + + + hal + 0 + 0 + 0 + 0 + + 8 + 65 + 1 + 0 + 0 + 0 + ..\..\BSP\Hardware\Src\delay.c + delay.c + 0 + 0 + + + 8 + 66 + 1 + 0 + 0 + 0 + ..\..\BSP\Hardware\Src\lcd_2inch4.c + lcd_2inch4.c + 0 + 0 + + + 8 + 67 + 1 + 0 + 0 + 0 + ..\..\BSP\Hardware\Src\lcd_config.c + lcd_config.c + 0 + 0 + + + 8 + 68 + 1 + 0 + 0 + 0 + ..\..\BSP\Hardware\Src\ov2640.c + ov2640.c + 0 + 0 + + + 8 + 69 + 1 + 0 + 0 + 0 + ..\..\BSP\Hardware\Src\sccb.c + sccb.c + 0 + 0 + + + + + examples + 1 + 0 + 0 + 0 + + 9 + 70 + 1 + 0 + 0 + 0 + ..\..\..\..\examples\nnom_mnist\nnom_mnsit_example.c + nnom_mnsit_example.c + 0 + 0 + + + + + nnom + 0 + 0 + 0 + 0 + + 10 + 71 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\backends\nnom_local.c + nnom_local.c + 0 + 0 + + + 10 + 72 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\core\nnom.c + nnom.c + 0 + 0 + + + 10 + 73 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\core\nnom_layers.c + nnom_layers.c + 0 + 0 + + + 10 + 74 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\core\nnom_tensor.c + nnom_tensor.c + 0 + 0 + + + 10 + 75 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\core\nnom_utils.c + nnom_utils.c + 0 + 0 + + + 10 + 76 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_activation.c + nnom_activation.c + 0 + 0 + + + 10 + 77 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_avgpool.c + nnom_avgpool.c + 0 + 0 + + + 10 + 78 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_baselayer.c + nnom_baselayer.c + 0 + 0 + + + 10 + 79 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_concat.c + nnom_concat.c + 0 + 0 + + + 10 + 80 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_conv2d.c + nnom_conv2d.c + 0 + 0 + + + 10 + 81 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_conv2d_trans.c + nnom_conv2d_trans.c + 0 + 0 + + + 10 + 82 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_cropping.c + nnom_cropping.c + 0 + 0 + + + 10 + 83 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_dense.c + nnom_dense.c + 0 + 0 + + + 10 + 84 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_dw_conv2d.c + nnom_dw_conv2d.c + 0 + 0 + + + 10 + 85 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_flatten.c + nnom_flatten.c + 0 + 0 + + + 10 + 86 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_global_pool.c + nnom_global_pool.c + 0 + 0 + + + 10 + 87 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_gru_cell.c + nnom_gru_cell.c + 0 + 0 + + + 10 + 88 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_input.c + nnom_input.c + 0 + 0 + + + 10 + 89 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_lambda.c + nnom_lambda.c + 0 + 0 + + + 10 + 90 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_lstm_cell.c + nnom_lstm_cell.c + 0 + 0 + + + 10 + 91 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_matrix.c + nnom_matrix.c + 0 + 0 + + + 10 + 92 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_maxpool.c + nnom_maxpool.c + 0 + 0 + + + 10 + 93 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_output.c + nnom_output.c + 0 + 0 + + + 10 + 94 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_rnn.c + nnom_rnn.c + 0 + 0 + + + 10 + 95 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_simple_cell.c + nnom_simple_cell.c + 0 + 0 + + + 10 + 96 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_softmax.c + nnom_softmax.c + 0 + 0 + + + 10 + 97 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_sumpool.c + nnom_sumpool.c + 0 + 0 + + + 10 + 98 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_upsample.c + nnom_upsample.c + 0 + 0 + + + 10 + 99 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\layers\nnom_zero_padding.c + nnom_zero_padding.c + 0 + 0 + + + 10 + 100 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\nnom\src\backends\nnom_local_q15.c + nnom_local_q15.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + +
diff --git a/board/NUCLEO_STM32L496ZG/KEIL/nnom_mnist/TencentOS_tiny.uvprojx b/board/NUCLEO_STM32L496ZG/KEIL/nnom_mnist/TencentOS_tiny.uvprojx new file mode 100644 index 000000000..e0049a351 --- /dev/null +++ b/board/NUCLEO_STM32L496ZG/KEIL/nnom_mnist/TencentOS_tiny.uvprojx @@ -0,0 +1,968 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + TencentOS_tiny + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + STM32L496ZGTx + STMicroelectronics + Keil.STM32L4xx_DFP.2.5.0 + https://www.keil.com/pack/ + IRAM(0x20000000-0x2004FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4") + + + + + + + + + + + + + + + $$Device:STM32L496ZGTx$CMSIS\SVD\STM32L4x6.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + TencentOS_tiny\ + TencentOS_tiny + 1 + 0 + 1 + 1 + 1 + + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4107 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x50000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x50000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + USE_HAL_DRIVER,STM32L496xx,NUCLEO_STM32L496ZG + + ..\..\BSP\Inc;..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Inc;..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Inc\Legacy;..\..\..\..\platform\vendor_bsp\st\CMSIS\Device\ST\STM32L4xx\Include;..\..\..\..\platform\vendor_bsp\st\CMSIS\Include;..\..\..\..\arch\arm\arm-v7m\common\include;..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc;..\..\..\..\kernel\core\include;..\..\..\..\kernel\pm\include;..\..\..\..\osal\cmsis_os;..\..\..\..\examples\hello_world;..\..\TOS_CONFIG;..\..\..\..\net\at\include;..\..\..\..\kernel\hal\include;..\..\BSP\Hardware\Inc;..\..\..\..\components\ai\nnom\inc;..\..\..\..\components\ai\nnom\inc\layers;..\..\..\..\components\ai\nnom\port;..\..\..\..\examples\nnom_mnist\data + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Application/MDK-ARM + + + startup_stm32l496xx.s + 2 + startup_stm32l496xx.s + + + + + Application/User + + + main.c + 1 + ..\..\BSP\Src\main.c + + + gpio.c + 1 + ..\..\BSP\Src\gpio.c + + + stm32l4xx_hal_msp.c + 1 + ..\..\BSP\Src\stm32l4xx_hal_msp.c + + + stm32l4xx_it.c + 1 + ..\..\BSP\Src\stm32l4xx_it.c + + + sys.c + 1 + ..\..\BSP\Src\sys.c + + + usart.c + 1 + ..\..\BSP\Src\usart.c + + + mcu_init.c + 1 + ..\..\BSP\Src\mcu_init.c + + + dcmi.c + 1 + ..\..\BSP\Src\dcmi.c + + + dma.c + 1 + ..\..\BSP\Src\dma.c + + + i2c.c + 1 + ..\..\BSP\Src\i2c.c + + + spi.c + 1 + ..\..\BSP\Src\spi.c + + + tim.c + 1 + ..\..\BSP\Src\tim.c + + + + + Drivers/STM32L4xx_HAL_Driver + + + stm32l4xx_hal_uart.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c + + + stm32l4xx_hal_uart_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c + + + stm32l4xx_hal.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c + + + stm32l4xx_hal_i2c.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c + + + stm32l4xx_hal_i2c_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c + + + stm32l4xx_hal_rcc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c + + + stm32l4xx_hal_rcc_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c + + + stm32l4xx_hal_flash.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c + + + stm32l4xx_hal_flash_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c + + + stm32l4xx_hal_flash_ramfunc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c + + + stm32l4xx_hal_gpio.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c + + + stm32l4xx_hal_dma.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c + + + stm32l4xx_hal_dma_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c + + + stm32l4xx_hal_pwr.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c + + + stm32l4xx_hal_pwr_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c + + + stm32l4xx_hal_cortex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c + + + stm32l4xx_hal_exti.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c + + + stm32l4xx_hal_tim.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c + + + stm32l4xx_hal_tim_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c + + + stm32l4xx_hal_dcmi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dcmi.c + + + stm32l4xx_hal_spi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c + + + stm32l4xx_hal_spi_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c + + + + + Drivers/CMSIS + + + system_stm32l4xx.c + 1 + ..\..\BSP\Src\system_stm32l4xx.c + + + + + tos/arch + + + tos_cpu.c + 1 + ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c + + + port_c.c + 1 + ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_c.c + + + port_s.S + 2 + ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_s.S + + + + + tos/kernel + + + tos_binary_heap.c + 1 + ..\..\..\..\kernel\core\tos_binary_heap.c + + + tos_char_fifo.c + 1 + ..\..\..\..\kernel\core\tos_char_fifo.c + + + tos_completion.c + 1 + ..\..\..\..\kernel\core\tos_completion.c + + + tos_countdownlatch.c + 1 + ..\..\..\..\kernel\core\tos_countdownlatch.c + + + tos_event.c + 1 + ..\..\..\..\kernel\core\tos_event.c + + + tos_global.c + 1 + ..\..\..\..\kernel\core\tos_global.c + + + tos_mail_queue.c + 1 + ..\..\..\..\kernel\core\tos_mail_queue.c + + + tos_message_queue.c + 1 + ..\..\..\..\kernel\core\tos_message_queue.c + + + tos_mmblk.c + 1 + ..\..\..\..\kernel\core\tos_mmblk.c + + + tos_mmheap.c + 1 + ..\..\..\..\kernel\core\tos_mmheap.c + + + tos_mutex.c + 1 + ..\..\..\..\kernel\core\tos_mutex.c + + + tos_pend.c + 1 + ..\..\..\..\kernel\core\tos_pend.c + + + tos_priority_mail_queue.c + 1 + ..\..\..\..\kernel\core\tos_priority_mail_queue.c + + + tos_priority_message_queue.c + 1 + ..\..\..\..\kernel\core\tos_priority_message_queue.c + + + tos_priority_queue.c + 1 + ..\..\..\..\kernel\core\tos_priority_queue.c + + + tos_ring_queue.c + 1 + ..\..\..\..\kernel\core\tos_ring_queue.c + + + tos_robin.c + 1 + ..\..\..\..\kernel\core\tos_robin.c + + + tos_sched.c + 1 + ..\..\..\..\kernel\core\tos_sched.c + + + tos_sem.c + 1 + ..\..\..\..\kernel\core\tos_sem.c + + + tos_sys.c + 1 + ..\..\..\..\kernel\core\tos_sys.c + + + tos_task.c + 1 + ..\..\..\..\kernel\core\tos_task.c + + + tos_tick.c + 1 + ..\..\..\..\kernel\core\tos_tick.c + + + tos_time.c + 1 + ..\..\..\..\kernel\core\tos_time.c + + + tos_timer.c + 1 + ..\..\..\..\kernel\core\tos_timer.c + + + + + tos/cmsis_os + + + cmsis_os.c + 1 + ..\..\..\..\osal\cmsis_os\cmsis_os.c + + + + + hal + + + delay.c + 1 + ..\..\BSP\Hardware\Src\delay.c + + + lcd_2inch4.c + 1 + ..\..\BSP\Hardware\Src\lcd_2inch4.c + + + lcd_config.c + 1 + ..\..\BSP\Hardware\Src\lcd_config.c + + + ov2640.c + 1 + ..\..\BSP\Hardware\Src\ov2640.c + + + sccb.c + 1 + ..\..\BSP\Hardware\Src\sccb.c + + + + + examples + + + nnom_mnsit_example.c + 1 + ..\..\..\..\examples\nnom_mnist\nnom_mnsit_example.c + + + + + nnom + + + nnom_local.c + 1 + ..\..\..\..\components\ai\nnom\src\backends\nnom_local.c + + + nnom.c + 1 + ..\..\..\..\components\ai\nnom\src\core\nnom.c + + + nnom_layers.c + 1 + ..\..\..\..\components\ai\nnom\src\core\nnom_layers.c + + + nnom_tensor.c + 1 + ..\..\..\..\components\ai\nnom\src\core\nnom_tensor.c + + + nnom_utils.c + 1 + ..\..\..\..\components\ai\nnom\src\core\nnom_utils.c + + + nnom_activation.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_activation.c + + + nnom_avgpool.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_avgpool.c + + + nnom_baselayer.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_baselayer.c + + + nnom_concat.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_concat.c + + + nnom_conv2d.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_conv2d.c + + + nnom_conv2d_trans.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_conv2d_trans.c + + + nnom_cropping.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_cropping.c + + + nnom_dense.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_dense.c + + + nnom_dw_conv2d.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_dw_conv2d.c + + + nnom_flatten.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_flatten.c + + + nnom_global_pool.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_global_pool.c + + + nnom_gru_cell.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_gru_cell.c + + + nnom_input.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_input.c + + + nnom_lambda.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_lambda.c + + + nnom_lstm_cell.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_lstm_cell.c + + + nnom_matrix.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_matrix.c + + + nnom_maxpool.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_maxpool.c + + + nnom_output.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_output.c + + + nnom_rnn.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_rnn.c + + + nnom_simple_cell.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_simple_cell.c + + + nnom_softmax.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_softmax.c + + + nnom_sumpool.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_sumpool.c + + + nnom_upsample.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_upsample.c + + + nnom_zero_padding.c + 1 + ..\..\..\..\components\ai\nnom\src\layers\nnom_zero_padding.c + + + nnom_local_q15.c + 1 + ..\..\..\..\components\ai\nnom\src\backends\nnom_local_q15.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + +
diff --git a/board/NUCLEO_STM32L496ZG/KEIL/nnom_mnist/startup_stm32l496xx.s b/board/NUCLEO_STM32L496ZG/KEIL/nnom_mnist/startup_stm32l496xx.s new file mode 100644 index 000000000..3ebfcc32a --- /dev/null +++ b/board/NUCLEO_STM32L496ZG/KEIL/nnom_mnist/startup_stm32l496xx.s @@ -0,0 +1,450 @@ +;******************************************************************************* +;* File Name : startup_stm32l496xx.s +;* Author : MCD Application Team +;* Description : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + DCD CRS_IRQHandler ; CRS error + DCD I2C4_EV_IRQHandler ; I2C4 event + DCD I2C4_ER_IRQHandler ; I2C4 error + DCD DCMI_IRQHandler ; DCMI global interrupt + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD DMA2D_IRQHandler ; DMA2D global interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DFSDM1_FLT3_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +OTG_FS_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +QUADSPI_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +SWPMI1_IRQHandler +TSC_IRQHandler +LCD_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +CRS_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +DCMI_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +DMA2D_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/board/NUCLEO_STM32L496ZG/KEIL/tflitemicro_person_detection/TencentOS_tiny.uvoptx b/board/NUCLEO_STM32L496ZG/KEIL/tflitemicro_person_detection/TencentOS_tiny.uvoptx index b49158a40..5ddb9723f 100644 --- a/board/NUCLEO_STM32L496ZG/KEIL/tflitemicro_person_detection/TencentOS_tiny.uvoptx +++ b/board/NUCLEO_STM32L496ZG/KEIL/tflitemicro_person_detection/TencentOS_tiny.uvoptx @@ -117,6 +117,11 @@ STLink\ST-LINKIII-KEIL_SWO.dll + + 0 + ST-LINKIII-KEIL_SWO + -U0667FF343339415043053749 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(2BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32L496ZGTx$CMSIS\Flash\STM32L4xx_1024.FLM) + 0 UL2CM3 @@ -168,7 +173,7 @@ 1 - 1 + 0 0 2 10000000 @@ -198,7 +203,7 @@ Application/User - 0 + 1 0 0 0 @@ -622,7 +627,7 @@ Drivers/CMSIS - 1 + 0 0 0 0 @@ -642,7 +647,7 @@ tos/arch - 1 + 0 0 0 0 @@ -982,7 +987,7 @@ tos/cmsis_os - 1 + 0 0 0 0 @@ -1002,7 +1007,7 @@ hal - 1 + 0 0 0 0 @@ -1090,7 +1095,7 @@ tensorflow - 1 + 0 0 0 0 @@ -1146,7 +1151,7 @@ 10 75 8 - 0 + 1 0 0 ..\..\..\..\examples\tflitemicro_person_detection\tflu_person_detection\main_functions.cc diff --git a/board/NUCLEO_STM32L496ZG/KEIL/tflitemicro_speech_detection/TencentOS_tiny.uvoptx b/board/NUCLEO_STM32L496ZG/KEIL/tflitemicro_speech_detection/TencentOS_tiny.uvoptx new file mode 100644 index 000000000..30bd0d98a --- /dev/null +++ b/board/NUCLEO_STM32L496ZG/KEIL/tflitemicro_speech_detection/TencentOS_tiny.uvoptx @@ -0,0 +1,1184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp;*.cc + 0 + + + + 0 + 0 + + + + TencentOS_tiny + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U0667FF343339415043053749 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(2BA01477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32L496ZGTx$CMSIS\Flash\STM32L4xx_1024.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32L496ZGTx$CMSIS\Flash\STM32L4xx_1024.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Application/MDK-ARM + 0 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + startup_stm32l496xx.s + startup_stm32l496xx.s + 0 + 0 + + + + + Application/User + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\main.c + main.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\gpio.c + gpio.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\stm32l4xx_hal_msp.c + stm32l4xx_hal_msp.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\stm32l4xx_it.c + stm32l4xx_it.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\sys.c + sys.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\usart.c + usart.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\mcu_init.c + mcu_init.c + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\dcmi.c + dcmi.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\dma.c + dma.c + 0 + 0 + + + 2 + 11 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\i2c.c + i2c.c + 0 + 0 + + + 2 + 12 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\spi.c + spi.c + 0 + 0 + + + 2 + 13 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\tim.c + tim.c + 0 + 0 + + + + + Drivers/STM32L4xx_HAL_Driver + 0 + 0 + 0 + 0 + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c + stm32l4xx_hal_uart.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c + stm32l4xx_hal_uart_ex.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c + stm32l4xx_hal.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c + stm32l4xx_hal_i2c.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c + stm32l4xx_hal_i2c_ex.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c + stm32l4xx_hal_rcc.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c + stm32l4xx_hal_rcc_ex.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c + stm32l4xx_hal_flash.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c + stm32l4xx_hal_flash_ex.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c + stm32l4xx_hal_flash_ramfunc.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c + stm32l4xx_hal_gpio.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c + stm32l4xx_hal_dma.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c + stm32l4xx_hal_dma_ex.c + 0 + 0 + + + 3 + 27 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c + stm32l4xx_hal_pwr.c + 0 + 0 + + + 3 + 28 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c + stm32l4xx_hal_pwr_ex.c + 0 + 0 + + + 3 + 29 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c + stm32l4xx_hal_cortex.c + 0 + 0 + + + 3 + 30 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c + stm32l4xx_hal_exti.c + 0 + 0 + + + 3 + 31 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c + stm32l4xx_hal_tim.c + 0 + 0 + + + 3 + 32 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c + stm32l4xx_hal_tim_ex.c + 0 + 0 + + + 3 + 33 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dcmi.c + stm32l4xx_hal_dcmi.c + 0 + 0 + + + 3 + 34 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c + stm32l4xx_hal_spi.c + 0 + 0 + + + 3 + 35 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c + stm32l4xx_hal_spi_ex.c + 0 + 0 + + + + + Drivers/CMSIS + 0 + 0 + 0 + 0 + + 4 + 36 + 1 + 0 + 0 + 0 + ..\..\BSP\Src\system_stm32l4xx.c + system_stm32l4xx.c + 0 + 0 + + + + + tos/arch + 0 + 0 + 0 + 0 + + 5 + 37 + 1 + 0 + 0 + 0 + ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c + tos_cpu.c + 0 + 0 + + + 5 + 38 + 1 + 0 + 0 + 0 + ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_c.c + port_c.c + 0 + 0 + + + 5 + 39 + 2 + 0 + 0 + 0 + ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_s.S + port_s.S + 0 + 0 + + + + + tos/kernel + 0 + 0 + 0 + 0 + + 6 + 40 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_binary_heap.c + tos_binary_heap.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_char_fifo.c + tos_char_fifo.c + 0 + 0 + + + 6 + 42 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_completion.c + tos_completion.c + 0 + 0 + + + 6 + 43 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_countdownlatch.c + tos_countdownlatch.c + 0 + 0 + + + 6 + 44 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_event.c + tos_event.c + 0 + 0 + + + 6 + 45 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_global.c + tos_global.c + 0 + 0 + + + 6 + 46 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_mail_queue.c + tos_mail_queue.c + 0 + 0 + + + 6 + 47 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_message_queue.c + tos_message_queue.c + 0 + 0 + + + 6 + 48 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_mmblk.c + tos_mmblk.c + 0 + 0 + + + 6 + 49 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_mmheap.c + tos_mmheap.c + 0 + 0 + + + 6 + 50 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_mutex.c + tos_mutex.c + 0 + 0 + + + 6 + 51 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_pend.c + tos_pend.c + 0 + 0 + + + 6 + 52 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_priority_mail_queue.c + tos_priority_mail_queue.c + 0 + 0 + + + 6 + 53 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_priority_message_queue.c + tos_priority_message_queue.c + 0 + 0 + + + 6 + 54 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_priority_queue.c + tos_priority_queue.c + 0 + 0 + + + 6 + 55 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_ring_queue.c + tos_ring_queue.c + 0 + 0 + + + 6 + 56 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_robin.c + tos_robin.c + 0 + 0 + + + 6 + 57 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_sched.c + tos_sched.c + 0 + 0 + + + 6 + 58 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_sem.c + tos_sem.c + 0 + 0 + + + 6 + 59 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_sys.c + tos_sys.c + 0 + 0 + + + 6 + 60 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_task.c + tos_task.c + 0 + 0 + + + 6 + 61 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_tick.c + tos_tick.c + 0 + 0 + + + 6 + 62 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_time.c + tos_time.c + 0 + 0 + + + 6 + 63 + 1 + 0 + 0 + 0 + ..\..\..\..\kernel\core\tos_timer.c + tos_timer.c + 0 + 0 + + + + + tos/cmsis_os + 0 + 0 + 0 + 0 + + 7 + 64 + 1 + 0 + 0 + 0 + ..\..\..\..\osal\cmsis_os\cmsis_os.c + cmsis_os.c + 0 + 0 + + + + + hal + 0 + 0 + 0 + 0 + + 8 + 65 + 1 + 0 + 0 + 0 + ..\..\BSP\Hardware\Src\delay.c + delay.c + 0 + 0 + + + 8 + 66 + 1 + 0 + 0 + 0 + ..\..\BSP\Hardware\Src\lcd_2inch4.c + lcd_2inch4.c + 0 + 0 + + + 8 + 67 + 1 + 0 + 0 + 0 + ..\..\BSP\Hardware\Src\lcd_config.c + lcd_config.c + 0 + 0 + + + 8 + 68 + 1 + 0 + 0 + 0 + ..\..\BSP\Hardware\Src\ov2640.c + ov2640.c + 0 + 0 + + + 8 + 69 + 1 + 0 + 0 + 0 + ..\..\BSP\Hardware\Src\sccb.c + sccb.c + 0 + 0 + + + + + examples + 1 + 0 + 0 + 0 + + 9 + 70 + 1 + 0 + 0 + 0 + ..\..\..\..\examples\tflitemicro_speech_detection\tflitemicro_speech_detection.c + tflitemicro_speech_detection.c + 0 + 0 + + + + + tensorflow + 1 + 0 + 0 + 0 + + 10 + 71 + 1 + 0 + 0 + 0 + ..\..\..\..\components\ai\tflite_micro\KEIL\retarget.c + retarget.c + 0 + 0 + + + 10 + 72 + 4 + 0 + 0 + 0 + ..\..\..\..\components\ai\tflite_micro\ARM_CortexM4_lib\tensorflow_lite_micro_M4.lib + tensorflow_lite_micro_M4.lib + 0 + 0 + + + 10 + 73 + 8 + 0 + 0 + 0 + ..\..\..\..\examples\tflitemicro_speech_detection\tflu_speech_yes_or_no\micro_features\model.cc + model.cc + 0 + 0 + + + 10 + 74 + 8 + 0 + 0 + 0 + ..\..\..\..\examples\tflitemicro_speech_detection\tflu_speech_yes_or_no\micro_features\no_micro_features_data.cc + no_micro_features_data.cc + 0 + 0 + + + 10 + 75 + 8 + 0 + 0 + 0 + ..\..\..\..\examples\tflitemicro_speech_detection\tflu_speech_yes_or_no\micro_features\yes_micro_features_data.cc + yes_micro_features_data.cc + 0 + 0 + + + 10 + 76 + 8 + 0 + 0 + 0 + ..\..\..\..\examples\tflitemicro_speech_detection\tflu_speech_yes_or_no\micro_speech.cc + micro_speech.cc + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + +
diff --git a/board/NUCLEO_STM32L496ZG/KEIL/tflitemicro_speech_detection/TencentOS_tiny.uvprojx b/board/NUCLEO_STM32L496ZG/KEIL/tflitemicro_speech_detection/TencentOS_tiny.uvprojx new file mode 100644 index 000000000..924b18bd8 --- /dev/null +++ b/board/NUCLEO_STM32L496ZG/KEIL/tflitemicro_speech_detection/TencentOS_tiny.uvprojx @@ -0,0 +1,848 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + TencentOS_tiny + 0x4 + ARM-ADS + 6140000::V6.14::ARMCLANG + 1 + + + STM32L496ZGTx + STMicroelectronics + Keil.STM32L4xx_DFP.2.5.0 + https://www.keil.com/pack/ + IRAM(0x20000000-0x2004FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4") + + + + + + + + + + + + + + + $$Device:STM32L496ZGTx$CMSIS\SVD\STM32L4x6.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + TencentOS_tiny\ + TencentOS_tiny + 1 + 0 + 1 + 1 + 1 + + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 0 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4107 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x50000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x50000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + USE_HAL_DRIVER,STM32L496xx,NUCLEO_STM32L496ZG + + ..\..\BSP\Inc;..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Inc;..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Inc\Legacy;..\..\..\..\platform\vendor_bsp\st\CMSIS\Device\ST\STM32L4xx\Include;..\..\..\..\platform\vendor_bsp\st\CMSIS\Include;..\..\..\..\arch\arm\arm-v7m\common\include;..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc;..\..\..\..\kernel\core\include;..\..\..\..\kernel\pm\include;..\..\..\..\osal\cmsis_os;..\..\..\..\examples\hello_world;..\..\TOS_CONFIG;..\..\..\..\net\at\include;..\..\..\..\kernel\hal\include;..\..\BSP\Hardware\Inc;..\..\..\..\components\ai\tflite_micro\ARM_CortexM4_lib;..\..\..\..\components\ai\tflite_micro\ARM_CortexM4_lib\third_party\flatbuffers\include;..\..\..\..\components\ai\tflite_micro\ARM_CortexM4_lib\third_party\gemmlowp;..\..\..\..\components\ai\tflite_micro\ARM_CortexM4_lib\third_party\kissfft;..\..\..\..\components\ai\tflite_micro\ARM_CortexM4_lib\third_party\ruy;..\..\..\..\components\ai\tflite_micro\ARM_CortexM4_lib\tensorflow\lite\micro\tools\make\downloads;..\..\..\..\examples\tflitemicro_person_detection\tflu_person_detection;..\..\..\..\examples\tflitemicro_speech_detection\tflu_speech_yes_or_no;..\..\..\..\examples\tflitemicro_speech_detection\tflu_speech_yes_or_no\micro_features + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Application/MDK-ARM + + + startup_stm32l496xx.s + 2 + startup_stm32l496xx.s + + + + + Application/User + + + main.c + 1 + ..\..\BSP\Src\main.c + + + gpio.c + 1 + ..\..\BSP\Src\gpio.c + + + stm32l4xx_hal_msp.c + 1 + ..\..\BSP\Src\stm32l4xx_hal_msp.c + + + stm32l4xx_it.c + 1 + ..\..\BSP\Src\stm32l4xx_it.c + + + sys.c + 1 + ..\..\BSP\Src\sys.c + + + usart.c + 1 + ..\..\BSP\Src\usart.c + + + mcu_init.c + 1 + ..\..\BSP\Src\mcu_init.c + + + dcmi.c + 1 + ..\..\BSP\Src\dcmi.c + + + dma.c + 1 + ..\..\BSP\Src\dma.c + + + i2c.c + 1 + ..\..\BSP\Src\i2c.c + + + spi.c + 1 + ..\..\BSP\Src\spi.c + + + tim.c + 1 + ..\..\BSP\Src\tim.c + + + + + Drivers/STM32L4xx_HAL_Driver + + + stm32l4xx_hal_uart.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c + + + stm32l4xx_hal_uart_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c + + + stm32l4xx_hal.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c + + + stm32l4xx_hal_i2c.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c + + + stm32l4xx_hal_i2c_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c + + + stm32l4xx_hal_rcc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c + + + stm32l4xx_hal_rcc_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c + + + stm32l4xx_hal_flash.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c + + + stm32l4xx_hal_flash_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c + + + stm32l4xx_hal_flash_ramfunc.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c + + + stm32l4xx_hal_gpio.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c + + + stm32l4xx_hal_dma.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c + + + stm32l4xx_hal_dma_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c + + + stm32l4xx_hal_pwr.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c + + + stm32l4xx_hal_pwr_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c + + + stm32l4xx_hal_cortex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c + + + stm32l4xx_hal_exti.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c + + + stm32l4xx_hal_tim.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c + + + stm32l4xx_hal_tim_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c + + + stm32l4xx_hal_dcmi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dcmi.c + + + stm32l4xx_hal_spi.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c + + + stm32l4xx_hal_spi_ex.c + 1 + ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c + + + + + Drivers/CMSIS + + + system_stm32l4xx.c + 1 + ..\..\BSP\Src\system_stm32l4xx.c + + + + + tos/arch + + + tos_cpu.c + 1 + ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c + + + port_c.c + 1 + ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_c.c + + + port_s.S + 2 + ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_s.S + + + + + tos/kernel + + + tos_binary_heap.c + 1 + ..\..\..\..\kernel\core\tos_binary_heap.c + + + tos_char_fifo.c + 1 + ..\..\..\..\kernel\core\tos_char_fifo.c + + + tos_completion.c + 1 + ..\..\..\..\kernel\core\tos_completion.c + + + tos_countdownlatch.c + 1 + ..\..\..\..\kernel\core\tos_countdownlatch.c + + + tos_event.c + 1 + ..\..\..\..\kernel\core\tos_event.c + + + tos_global.c + 1 + ..\..\..\..\kernel\core\tos_global.c + + + tos_mail_queue.c + 1 + ..\..\..\..\kernel\core\tos_mail_queue.c + + + tos_message_queue.c + 1 + ..\..\..\..\kernel\core\tos_message_queue.c + + + tos_mmblk.c + 1 + ..\..\..\..\kernel\core\tos_mmblk.c + + + tos_mmheap.c + 1 + ..\..\..\..\kernel\core\tos_mmheap.c + + + tos_mutex.c + 1 + ..\..\..\..\kernel\core\tos_mutex.c + + + tos_pend.c + 1 + ..\..\..\..\kernel\core\tos_pend.c + + + tos_priority_mail_queue.c + 1 + ..\..\..\..\kernel\core\tos_priority_mail_queue.c + + + tos_priority_message_queue.c + 1 + ..\..\..\..\kernel\core\tos_priority_message_queue.c + + + tos_priority_queue.c + 1 + ..\..\..\..\kernel\core\tos_priority_queue.c + + + tos_ring_queue.c + 1 + ..\..\..\..\kernel\core\tos_ring_queue.c + + + tos_robin.c + 1 + ..\..\..\..\kernel\core\tos_robin.c + + + tos_sched.c + 1 + ..\..\..\..\kernel\core\tos_sched.c + + + tos_sem.c + 1 + ..\..\..\..\kernel\core\tos_sem.c + + + tos_sys.c + 1 + ..\..\..\..\kernel\core\tos_sys.c + + + tos_task.c + 1 + ..\..\..\..\kernel\core\tos_task.c + + + tos_tick.c + 1 + ..\..\..\..\kernel\core\tos_tick.c + + + tos_time.c + 1 + ..\..\..\..\kernel\core\tos_time.c + + + tos_timer.c + 1 + ..\..\..\..\kernel\core\tos_timer.c + + + + + tos/cmsis_os + + + cmsis_os.c + 1 + ..\..\..\..\osal\cmsis_os\cmsis_os.c + + + + + hal + + + delay.c + 1 + ..\..\BSP\Hardware\Src\delay.c + + + lcd_2inch4.c + 1 + ..\..\BSP\Hardware\Src\lcd_2inch4.c + + + lcd_config.c + 1 + ..\..\BSP\Hardware\Src\lcd_config.c + + + ov2640.c + 1 + ..\..\BSP\Hardware\Src\ov2640.c + + + sccb.c + 1 + ..\..\BSP\Hardware\Src\sccb.c + + + + + examples + + + tflitemicro_speech_detection.c + 1 + ..\..\..\..\examples\tflitemicro_speech_detection\tflitemicro_speech_detection.c + + + + + tensorflow + + + retarget.c + 1 + ..\..\..\..\components\ai\tflite_micro\KEIL\retarget.c + + + tensorflow_lite_micro_M4.lib + 4 + ..\..\..\..\components\ai\tflite_micro\ARM_CortexM4_lib\tensorflow_lite_micro_M4.lib + + + model.cc + 8 + ..\..\..\..\examples\tflitemicro_speech_detection\tflu_speech_yes_or_no\micro_features\model.cc + + + no_micro_features_data.cc + 8 + ..\..\..\..\examples\tflitemicro_speech_detection\tflu_speech_yes_or_no\micro_features\no_micro_features_data.cc + + + yes_micro_features_data.cc + 8 + ..\..\..\..\examples\tflitemicro_speech_detection\tflu_speech_yes_or_no\micro_features\yes_micro_features_data.cc + + + micro_speech.cc + 8 + ..\..\..\..\examples\tflitemicro_speech_detection\tflu_speech_yes_or_no\micro_speech.cc + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + +
diff --git a/board/NUCLEO_STM32L496ZG/KEIL/tflitemicro_speech_detection/startup_stm32l496xx.s b/board/NUCLEO_STM32L496ZG/KEIL/tflitemicro_speech_detection/startup_stm32l496xx.s new file mode 100644 index 000000000..3ebfcc32a --- /dev/null +++ b/board/NUCLEO_STM32L496ZG/KEIL/tflitemicro_speech_detection/startup_stm32l496xx.s @@ -0,0 +1,450 @@ +;******************************************************************************* +;* File Name : startup_stm32l496xx.s +;* Author : MCD Application Team +;* Description : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + DCD CRS_IRQHandler ; CRS error + DCD I2C4_EV_IRQHandler ; I2C4 event + DCD I2C4_ER_IRQHandler ; I2C4 error + DCD DCMI_IRQHandler ; DCMI global interrupt + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD DMA2D_IRQHandler ; DMA2D global interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DFSDM1_FLT3_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +OTG_FS_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +QUADSPI_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +SWPMI1_IRQHandler +TSC_IRQHandler +LCD_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +CRS_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +DCMI_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +DMA2D_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/board/TencentOS_tiny_EVB_G0/KEIL/mqtt_iot_explorer_e53_light/demo/mqtt_iot_explorer_e53_light.c b/board/TencentOS_tiny_EVB_G0/KEIL/mqtt_iot_explorer_e53_light/demo/mqtt_iot_explorer_e53_light.c index 8fc5b696d..3b449f246 100644 --- a/board/TencentOS_tiny_EVB_G0/KEIL/mqtt_iot_explorer_e53_light/demo/mqtt_iot_explorer_e53_light.c +++ b/board/TencentOS_tiny_EVB_G0/KEIL/mqtt_iot_explorer_e53_light/demo/mqtt_iot_explorer_e53_light.c @@ -305,9 +305,6 @@ void application_entry(void *arg) { char *str = "TencentOS-tiny"; - // 初始化tencent-os tiny定时器模块 - timer_init(); - // 初始化按键检测模块 stm32g0xx_key_init(); diff --git a/board/TencentOS_tiny_EVB_MX_Plus/BSP/Hardware/Modbus_Port/mod_port.h b/board/TencentOS_tiny_EVB_MX_Plus/BSP/Hardware/Modbus_Port/mod_port.h deleted file mode 100644 index e527a3ca8..000000000 --- a/board/TencentOS_tiny_EVB_MX_Plus/BSP/Hardware/Modbus_Port/mod_port.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * FreeModbus Libary: BARE Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _MOD_PORT_H -#define _MOD_PORT_H - -#include -#include - -#define INLINE inline -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#define ENTER_CRITICAL_SECTION( ) __disable_irq() -#define EXIT_CRITICAL_SECTION( ) __enable_irq() - -typedef uint8_t BOOL; - -typedef unsigned char UCHAR; -typedef char CHAR; - -typedef uint16_t USHORT; -typedef int16_t SHORT; - -typedef uint32_t ULONG; -typedef int32_t LONG; - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#endif diff --git a/board/TencentOS_tiny_EVB_MX_Plus/BSP/Hardware/Modbus_Port/portevent.c b/board/TencentOS_tiny_EVB_MX_Plus/BSP/Hardware/Modbus_Port/portevent.c deleted file mode 100644 index e700a471c..000000000 --- a/board/TencentOS_tiny_EVB_MX_Plus/BSP/Hardware/Modbus_Port/portevent.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * FreeModbus Libary: BARE Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static eMBEventType eQueuedEvent; -static BOOL xEventInQueue; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - xEventInQueue = FALSE; - return TRUE; -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - xEventInQueue = TRUE; - eQueuedEvent = eEvent; - return TRUE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - BOOL xEventHappened = FALSE; - - if( xEventInQueue ) - { - *eEvent = eQueuedEvent; - xEventInQueue = FALSE; - xEventHappened = TRUE; - } - return xEventHappened; -} diff --git a/board/TencentOS_tiny_EVB_MX_Plus/BSP/Hardware/Modbus_Port/portserial.c b/board/TencentOS_tiny_EVB_MX_Plus/BSP/Hardware/Modbus_Port/portserial.c deleted file mode 100644 index 4fafca19e..000000000 --- a/board/TencentOS_tiny_EVB_MX_Plus/BSP/Hardware/Modbus_Port/portserial.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * FreeModbus Libary: BARE Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#include "mod_port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" -#include "mcu_init.h" - -extern UART_HandleTypeDef huart3; -/* ----------------------- static functions ---------------------------------*/ -void prvvUARTTxReadyISR( void ); -void prvvUARTRxISR( void ); - -/* ----------------------- Start implementation -----------------------------*/ -void -vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable ) -{ - /* If xRXEnable enable serial receive interrupts. If xTxENable enable - * transmitter empty interrupts. - */ - if (xRxEnable) { - __HAL_UART_ENABLE_IT(&huart3, UART_IT_RXNE); - } else { - __HAL_UART_DISABLE_IT(&huart3, UART_IT_RXNE); - } - - if (xTxEnable) { - __HAL_UART_ENABLE_IT(&huart3, UART_IT_TXE); - } else { - __HAL_UART_DISABLE_IT(&huart3, UART_IT_TXE); - } -} - -BOOL -xMBPortSerialInit( UCHAR ucPORT, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity ) -{ - /* - Do nothing, Initialization is handled by MX_USART3_UART_Init() - Fixed port, baudrate, databit and parity - */ - return TRUE; -} - -BOOL -xMBPortSerialPutByte( CHAR ucByte ) -{ - /* Put a byte in the UARTs transmit buffer. This function is called - * by the protocol stack if pxMBFrameCBTransmitterEmpty( ) has been - * called. */ - return (HAL_OK == HAL_UART_Transmit(&huart3, (uint8_t*)&ucByte, 1, 10)); -} - -BOOL -xMBPortSerialGetByte( CHAR * pucByte ) -{ - /* Return the byte in the UARTs receive buffer. This function is called - * by the protocol stack after pxMBFrameCBByteReceived( ) has been called. - */ - *pucByte = (uint8_t)(huart3.Instance->RDR & (uint8_t)0x00FF); - return TRUE; -} - -/* Create an interrupt handler for the transmit buffer empty interrupt - * (or an equivalent) for your target processor. This function should then - * call pxMBFrameCBTransmitterEmpty( ) which tells the protocol stack that - * a new character can be sent. The protocol stack will then call - * xMBPortSerialPutByte( ) to send the character. - */ -//void prvvUARTTxReadyISR( void ) -//{ -// pxMBFrameCBTransmitterEmpty( ); -//} - -/* Create an interrupt handler for the receive interrupt for your target - * processor. This function should then call pxMBFrameCBByteReceived( ). The - * protocol stack will then call xMBPortSerialGetByte( ) to retrieve the - * character. - */ -//void prvvUARTRxISR( void ) -//{ -// pxMBFrameCBByteReceived( ); -//} diff --git a/board/TencentOS_tiny_EVB_MX_Plus/BSP/Hardware/Modbus_Port/porttimer.c b/board/TencentOS_tiny_EVB_MX_Plus/BSP/Hardware/Modbus_Port/porttimer.c deleted file mode 100644 index 7879b5162..000000000 --- a/board/TencentOS_tiny_EVB_MX_Plus/BSP/Hardware/Modbus_Port/porttimer.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * FreeModbus Libary: BARE Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Platform includes --------------------------------*/ -#include "mod_port.h" -#include "mcu_init.h" -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- static functions ---------------------------------*/ -void prvvTIMERExpiredISR( void ); -extern TIM_HandleTypeDef htim6; -uint16_t timeout = 0; -uint16_t downcounter = 0; -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortTimersInit( USHORT usTim1Timerout50us ) -{ - TIM_MasterConfigTypeDef sMasterConfig; - - htim6.Instance = TIM6; - htim6.Init.Prescaler = (HAL_RCC_GetPCLK1Freq() / 1000000) - 1; - htim6.Init.CounterMode = TIM_COUNTERMODE_UP; - htim6.Init.Period = 50 - 1; - - timeout = usTim1Timerout50us; - - if (HAL_TIM_Base_Init(&htim6) != HAL_OK) - { - return FALSE; - } - - sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) - { - return FALSE; - } - - return TRUE; -} - - -inline void -vMBPortTimersEnable( ) -{ - /* Enable the timer with the timeout passed to xMBPortTimersInit( ) */ - downcounter = timeout; - HAL_TIM_Base_Start_IT(&htim6); - - -} - -inline void -vMBPortTimersDisable( ) -{ - /* Disable any pending timers. */ - HAL_TIM_Base_Stop_IT(&htim6); -} - -/* Create an ISR which is called whenever the timer has expired. This function - * must then call pxMBPortCBTimerExpired( ) to notify the protocol stack that - * the timer has expired. - */ -//void prvvTIMERExpiredISR( void ) -//{ -// ( void )pxMBPortCBTimerExpired( ); -//} - diff --git a/board/TencentOS_tiny_EVB_MX_Plus/KEIL/modbus/TencentOS_tiny.uvoptx b/board/TencentOS_tiny_EVB_MX_Plus/KEIL/modbus/TencentOS_tiny.uvoptx deleted file mode 100644 index ecb68d469..000000000 --- a/board/TencentOS_tiny_EVB_MX_Plus/KEIL/modbus/TencentOS_tiny.uvoptx +++ /dev/null @@ -1,1420 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - TencentOS_tiny - 0x4 - ARM-ADS - - 80000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\list\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 18 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 6 - - - - - - - - - - - STLink\ST-LINKIII-KEIL_SWO.dll - - - - 0 - ARMRTXEVENTFLAGS - -L70 -Z18 -C0 -M0 -T1 - - - 0 - DLGTARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) - - - 0 - ARMDBGFLAGS - - - - 0 - DLGUARM - (105=-1,-1,-1,-1,0) - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_256 -FS08000000 -FL040000 -FP0($$Device:STM32L431RCTx$CMSIS\Flash\STM32L4xx_256.FLM)) - - - 0 - ST-LINKIII-KEIL_SWO - -U303030303030303030303031 -O10446 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_256.FLM -FS08000000 -FL040000 -FP0($$Device:STM32L431RCTx$CMSIS\Flash\STM32L4xx_256.FLM) - - - - - 0 - 0 - 295 - 1 -
134228324
- 0 - 0 - 0 - 0 - 0 - 1 - ..\..\BSP\Src\stm32l4xx_it_modbus.c - - \\TencentOS_tiny\../../BSP/Src/stm32l4xx_it_modbus.c\295 -
- - 1 - 0 - 278 - 1 -
134230314
- 0 - 0 - 0 - 0 - 0 - 1 - ..\..\BSP\Src\stm32l4xx_it_modbus.c - - \\TencentOS_tiny\../../BSP/Src/stm32l4xx_it_modbus.c\278 -
- - 2 - 0 - 287 - 1 -
134230340
- 0 - 0 - 0 - 0 - 0 - 1 - ..\..\BSP\Src\stm32l4xx_it_modbus.c - - \\TencentOS_tiny\../../BSP/Src/stm32l4xx_it_modbus.c\287 -
-
- - - 0 - 1 - tos_next_task - - - 1 - 1 - tos_rdyq.highest_prio - - - 2 - 1 - task_list - - - 3 - 1 - 0x20000280 - - - 4 - 1 - tos_rdyq.highest_prio - - - 5 - 1 - owner - - - 6 - 1 - tos_curr_task - - - 7 - 1 - highest_pending_prio - - - 8 - 1 - task - - - - - 1 - 0 - 0x200016F4 - 0 - - - - 0 - - - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - 1 - 1 - 0 - 2 - 10000000 - -
-
- - - Application/MDK-ARM - 0 - 0 - 0 - 0 - - 1 - 1 - 2 - 0 - 0 - 0 - startup_stm32l431xx.s - startup_stm32l431xx.s - 0 - 0 - - - - - Application/User - 1 - 0 - 0 - 0 - - 2 - 2 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\gpio.c - gpio.c - 0 - 0 - - - 2 - 3 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\main.c - main.c - 0 - 0 - - - 2 - 4 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\mcu_init.c - mcu_init.c - 0 - 0 - - - 2 - 5 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\stm32l4xx_hal_msp.c - stm32l4xx_hal_msp.c - 0 - 0 - - - 2 - 6 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\usart.c - usart.c - 0 - 0 - - - 2 - 7 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\adc.c - adc.c - 0 - 0 - - - 2 - 8 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\dac.c - dac.c - 0 - 0 - - - 2 - 9 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\i2c.c - i2c.c - 0 - 0 - - - 2 - 10 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\spi.c - spi.c - 0 - 0 - - - 2 - 11 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\stm32l4xx_it_modbus.c - stm32l4xx_it_modbus.c - 0 - 0 - - - 2 - 12 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\tim.c - tim.c - 0 - 0 - - - - - examples - 1 - 0 - 0 - 0 - - 3 - 13 - 1 - 0 - 0 - 0 - ..\..\..\..\examples\modbus\modbus.c - modbus.c - 0 - 0 - - - - - Drivers/STM32L4xx_HAL_Driver - 0 - 0 - 0 - 0 - - 4 - 14 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c - stm32l4xx_hal_tim.c - 0 - 0 - - - 4 - 15 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c - stm32l4xx_hal_tim_ex.c - 0 - 0 - - - 4 - 16 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c - stm32l4xx_hal_uart.c - 0 - 0 - - - 4 - 17 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c - stm32l4xx_hal_uart_ex.c - 0 - 0 - - - 4 - 18 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c - stm32l4xx_hal.c - 0 - 0 - - - 4 - 19 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c - stm32l4xx_hal_i2c.c - 0 - 0 - - - 4 - 20 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c - stm32l4xx_hal_i2c_ex.c - 0 - 0 - - - 4 - 21 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c - stm32l4xx_hal_rcc.c - 0 - 0 - - - 4 - 22 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c - stm32l4xx_hal_rcc_ex.c - 0 - 0 - - - 4 - 23 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c - stm32l4xx_hal_flash.c - 0 - 0 - - - 4 - 24 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c - stm32l4xx_hal_flash_ex.c - 0 - 0 - - - 4 - 25 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c - stm32l4xx_hal_flash_ramfunc.c - 0 - 0 - - - 4 - 26 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c - stm32l4xx_hal_gpio.c - 0 - 0 - - - 4 - 27 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c - stm32l4xx_hal_dma.c - 0 - 0 - - - 4 - 28 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c - stm32l4xx_hal_dma_ex.c - 0 - 0 - - - 4 - 29 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c - stm32l4xx_hal_pwr.c - 0 - 0 - - - 4 - 30 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c - stm32l4xx_hal_pwr_ex.c - 0 - 0 - - - 4 - 31 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c - stm32l4xx_hal_cortex.c - 0 - 0 - - - 4 - 32 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc_ex.c - stm32l4xx_hal_adc_ex.c - 0 - 0 - - - 4 - 33 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc.c - stm32l4xx_hal_adc.c - 0 - 0 - - - 4 - 34 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac.c - stm32l4xx_hal_dac.c - 0 - 0 - - - 4 - 35 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac_ex.c - stm32l4xx_hal_dac_ex.c - 0 - 0 - - - 4 - 36 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c - stm32l4xx_hal_spi.c - 0 - 0 - - - 4 - 37 - 1 - 0 - 0 - 0 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c - stm32l4xx_hal_spi_ex.c - 0 - 0 - - - - - Drivers/CMSIS - 0 - 0 - 0 - 0 - - 5 - 38 - 1 - 0 - 0 - 0 - ..\..\BSP\Src\system_stm32l4xx.c - system_stm32l4xx.c - 0 - 0 - - - - - Hardware - 0 - 0 - 0 - 0 - - 6 - 39 - 1 - 0 - 0 - 0 - ..\..\BSP\Hardware\DHT11\DHT11_BUS.c - DHT11_BUS.c - 0 - 0 - - - 6 - 40 - 1 - 0 - 0 - 0 - ..\..\BSP\Hardware\OLED\oled.c - oled.c - 0 - 0 - - - - - kernel - 0 - 0 - 0 - 0 - - 7 - 41 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_binary_heap.c - tos_binary_heap.c - 0 - 0 - - - 7 - 42 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_char_fifo.c - tos_char_fifo.c - 0 - 0 - - - 7 - 43 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_completion.c - tos_completion.c - 0 - 0 - - - 7 - 44 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_countdownlatch.c - tos_countdownlatch.c - 0 - 0 - - - 7 - 45 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_event.c - tos_event.c - 0 - 0 - - - 7 - 46 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_global.c - tos_global.c - 0 - 0 - - - 7 - 47 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_mail_queue.c - tos_mail_queue.c - 0 - 0 - - - 7 - 48 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_message_queue.c - tos_message_queue.c - 0 - 0 - - - 7 - 49 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_mmblk.c - tos_mmblk.c - 0 - 0 - - - 7 - 50 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_mmheap.c - tos_mmheap.c - 0 - 0 - - - 7 - 51 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_mutex.c - tos_mutex.c - 0 - 0 - - - 7 - 52 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_pend.c - tos_pend.c - 0 - 0 - - - 7 - 53 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_priority_mail_queue.c - tos_priority_mail_queue.c - 0 - 0 - - - 7 - 54 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_priority_message_queue.c - tos_priority_message_queue.c - 0 - 0 - - - 7 - 55 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_priority_queue.c - tos_priority_queue.c - 0 - 0 - - - 7 - 56 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_ring_queue.c - tos_ring_queue.c - 0 - 0 - - - 7 - 57 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_robin.c - tos_robin.c - 0 - 0 - - - 7 - 58 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_sched.c - tos_sched.c - 0 - 0 - - - 7 - 59 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_sem.c - tos_sem.c - 0 - 0 - - - 7 - 60 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_sys.c - tos_sys.c - 0 - 0 - - - 7 - 61 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_task.c - tos_task.c - 0 - 0 - - - 7 - 62 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_tick.c - tos_tick.c - 0 - 0 - - - 7 - 63 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_time.c - tos_time.c - 0 - 0 - - - 7 - 64 - 1 - 0 - 0 - 0 - ..\..\..\..\kernel\core\tos_timer.c - tos_timer.c - 0 - 0 - - - - - cpu - 0 - 0 - 0 - 0 - - 8 - 65 - 2 - 0 - 0 - 0 - ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_s.S - port_s.S - 0 - 0 - - - 8 - 66 - 1 - 0 - 0 - 0 - ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c - tos_cpu.c - 0 - 0 - - - 8 - 67 - 1 - 0 - 0 - 0 - ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_c.c - port_c.c - 0 - 0 - - - - - cmsis - 0 - 0 - 0 - 0 - - 9 - 68 - 1 - 0 - 0 - 0 - ..\..\..\..\osal\cmsis_os\cmsis_os.c - cmsis_os.c - 0 - 0 - - - - - config - 1 - 0 - 0 - 0 - - 10 - 69 - 5 - 0 - 0 - 0 - ..\..\TOS-CONFIG\tos_config.h - tos_config.h - 0 - 0 - - - - - modbus_src - 1 - 0 - 0 - 0 - - 11 - 70 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\ascii\mbascii.c - mbascii.c - 0 - 0 - - - 11 - 71 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfunccoils.c - mbfunccoils.c - 0 - 0 - - - 11 - 72 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncdiag.c - mbfuncdiag.c - 0 - 0 - - - 11 - 73 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncdisc.c - mbfuncdisc.c - 0 - 0 - - - 11 - 74 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncholding.c - mbfuncholding.c - 0 - 0 - - - 11 - 75 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncinput.c - mbfuncinput.c - 0 - 0 - - - 11 - 76 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncother.c - mbfuncother.c - 0 - 0 - - - 11 - 77 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbutils.c - mbutils.c - 0 - 0 - - - 11 - 78 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\rtu\mbcrc.c - mbcrc.c - 0 - 0 - - - 11 - 79 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\rtu\mbrtu.c - mbrtu.c - 0 - 0 - - - 11 - 80 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\tcp\mbtcp.c - mbtcp.c - 0 - 0 - - - 11 - 81 - 1 - 0 - 0 - 0 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\mb.c - mb.c - 0 - 0 - - - - - modbus_port - 1 - 0 - 0 - 0 - - 12 - 82 - 1 - 0 - 0 - 0 - ..\..\BSP\Hardware\Modbus_Port\portevent.c - portevent.c - 0 - 0 - - - 12 - 83 - 1 - 0 - 0 - 0 - ..\..\BSP\Hardware\Modbus_Port\portserial.c - portserial.c - 0 - 0 - - - 12 - 84 - 1 - 0 - 0 - 0 - ..\..\BSP\Hardware\Modbus_Port\porttimer.c - porttimer.c - 0 - 0 - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - -
diff --git a/board/TencentOS_tiny_EVB_MX_Plus/KEIL/modbus/TencentOS_tiny.uvprojx b/board/TencentOS_tiny_EVB_MX_Plus/KEIL/modbus/TencentOS_tiny.uvprojx deleted file mode 100644 index ba6a68939..000000000 --- a/board/TencentOS_tiny_EVB_MX_Plus/KEIL/modbus/TencentOS_tiny.uvprojx +++ /dev/null @@ -1,882 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - TencentOS_tiny - 0x4 - ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC - 0 - - - STM32L431RCTx - STMicroelectronics - Keil.STM32L4xx_DFP.2.2.0 - http://www.keil.com/pack - IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x803FFFF) CLOCK(8000000) FPU2 CPUTYPE("Cortex-M4") - - - - - - - - - - - - - - - $$Device:STM32L431RCTx$CMSIS\SVD\STM32L4x1.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\obj\ - TencentOS_tiny - 1 - 0 - 1 - 1 - 0 - .\list\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 0 - - - SARMCM3.DLL - -REMAP -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4107 - - 1 - STLink\ST-LINKIII-KEIL_SWO.dll - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 0 - 0 - 0 - 8 - 1 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x10000 - - - 1 - 0x8000000 - 0x40000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x40000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x10000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - USE_HAL_DRIVER,STM32L431xx,NDEBUG - - ..\..\BSP\Inc;..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Inc;..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Legacy;..\..\..\..\platform\vendor_bsp\st\CMSIS\Device\ST\STM32L4xx\Include;..\..\..\..\platform\vendor_bsp\st\CMSIS\Include;..\..\..\..\kernel\core\include;..\..\TOS-CONFIG;..\..\..\..\platform\arch\arm\cortex-m4\keil;..\..\..\..\kernel\pm\include;..\..\..\..\osal\cmsis_os;..\..\..\..\arch\arm\arm-v7m\common\include;..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc;..\..\BSP\Hardware\DHT11;..\..\BSP\Hardware\OLED;..\..\BSP\Hardware\BH1750;..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\ascii;..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions;..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\include;..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\rtu;..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\tcp;..\..\BSP\Hardware\Modbus_Port - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - - - - - - Application/MDK-ARM - - - startup_stm32l431xx.s - 2 - startup_stm32l431xx.s - - - - - Application/User - - - gpio.c - 1 - ..\..\BSP\Src\gpio.c - - - main.c - 1 - ..\..\BSP\Src\main.c - - - mcu_init.c - 1 - ..\..\BSP\Src\mcu_init.c - - - stm32l4xx_hal_msp.c - 1 - ..\..\BSP\Src\stm32l4xx_hal_msp.c - - - usart.c - 1 - ..\..\BSP\Src\usart.c - - - adc.c - 1 - ..\..\BSP\Src\adc.c - - - dac.c - 1 - ..\..\BSP\Src\dac.c - - - i2c.c - 1 - ..\..\BSP\Src\i2c.c - - - spi.c - 1 - ..\..\BSP\Src\spi.c - - - stm32l4xx_it_modbus.c - 1 - ..\..\BSP\Src\stm32l4xx_it_modbus.c - - - tim.c - 1 - ..\..\BSP\Src\tim.c - - - - - examples - - - modbus.c - 1 - ..\..\..\..\examples\modbus\modbus.c - - - - - Drivers/STM32L4xx_HAL_Driver - - - stm32l4xx_hal_tim.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c - - - stm32l4xx_hal_tim_ex.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c - - - stm32l4xx_hal_uart.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c - - - stm32l4xx_hal_uart_ex.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c - - - stm32l4xx_hal.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c - - - stm32l4xx_hal_i2c.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c - - - stm32l4xx_hal_i2c_ex.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c - - - stm32l4xx_hal_rcc.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c - - - stm32l4xx_hal_rcc_ex.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c - - - stm32l4xx_hal_flash.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c - - - stm32l4xx_hal_flash_ex.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c - - - stm32l4xx_hal_flash_ramfunc.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c - - - stm32l4xx_hal_gpio.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c - - - stm32l4xx_hal_dma.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c - - - stm32l4xx_hal_dma_ex.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c - - - stm32l4xx_hal_pwr.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c - - - stm32l4xx_hal_pwr_ex.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c - - - stm32l4xx_hal_cortex.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c - - - stm32l4xx_hal_adc_ex.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc_ex.c - - - stm32l4xx_hal_adc.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc.c - - - stm32l4xx_hal_dac.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac.c - - - stm32l4xx_hal_dac_ex.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac_ex.c - - - stm32l4xx_hal_spi.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c - - - stm32l4xx_hal_spi_ex.c - 1 - ..\..\..\..\platform\vendor_bsp\st\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c - - - - - Drivers/CMSIS - - - system_stm32l4xx.c - 1 - ..\..\BSP\Src\system_stm32l4xx.c - - - - - Hardware - - - DHT11_BUS.c - 1 - ..\..\BSP\Hardware\DHT11\DHT11_BUS.c - - - oled.c - 1 - ..\..\BSP\Hardware\OLED\oled.c - - - - - kernel - - - tos_binary_heap.c - 1 - ..\..\..\..\kernel\core\tos_binary_heap.c - - - tos_char_fifo.c - 1 - ..\..\..\..\kernel\core\tos_char_fifo.c - - - tos_completion.c - 1 - ..\..\..\..\kernel\core\tos_completion.c - - - tos_countdownlatch.c - 1 - ..\..\..\..\kernel\core\tos_countdownlatch.c - - - tos_event.c - 1 - ..\..\..\..\kernel\core\tos_event.c - - - tos_global.c - 1 - ..\..\..\..\kernel\core\tos_global.c - - - tos_mail_queue.c - 1 - ..\..\..\..\kernel\core\tos_mail_queue.c - - - tos_message_queue.c - 1 - ..\..\..\..\kernel\core\tos_message_queue.c - - - tos_mmblk.c - 1 - ..\..\..\..\kernel\core\tos_mmblk.c - - - tos_mmheap.c - 1 - ..\..\..\..\kernel\core\tos_mmheap.c - - - tos_mutex.c - 1 - ..\..\..\..\kernel\core\tos_mutex.c - - - tos_pend.c - 1 - ..\..\..\..\kernel\core\tos_pend.c - - - tos_priority_mail_queue.c - 1 - ..\..\..\..\kernel\core\tos_priority_mail_queue.c - - - tos_priority_message_queue.c - 1 - ..\..\..\..\kernel\core\tos_priority_message_queue.c - - - tos_priority_queue.c - 1 - ..\..\..\..\kernel\core\tos_priority_queue.c - - - tos_ring_queue.c - 1 - ..\..\..\..\kernel\core\tos_ring_queue.c - - - tos_robin.c - 1 - ..\..\..\..\kernel\core\tos_robin.c - - - tos_sched.c - 1 - ..\..\..\..\kernel\core\tos_sched.c - - - tos_sem.c - 1 - ..\..\..\..\kernel\core\tos_sem.c - - - tos_sys.c - 1 - ..\..\..\..\kernel\core\tos_sys.c - - - tos_task.c - 1 - ..\..\..\..\kernel\core\tos_task.c - - - tos_tick.c - 1 - ..\..\..\..\kernel\core\tos_tick.c - - - tos_time.c - 1 - ..\..\..\..\kernel\core\tos_time.c - - - tos_timer.c - 1 - ..\..\..\..\kernel\core\tos_timer.c - - - - - cpu - - - port_s.S - 2 - ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_s.S - - - tos_cpu.c - 1 - ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c - - - port_c.c - 1 - ..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_c.c - - - - - cmsis - - - cmsis_os.c - 1 - ..\..\..\..\osal\cmsis_os\cmsis_os.c - - - - - config - - - tos_config.h - 5 - ..\..\TOS-CONFIG\tos_config.h - - - - - modbus_src - - - mbascii.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\ascii\mbascii.c - - - mbfunccoils.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfunccoils.c - - - mbfuncdiag.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncdiag.c - - - mbfuncdisc.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncdisc.c - - - mbfuncholding.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncholding.c - - - mbfuncinput.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncinput.c - - - mbfuncother.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbfuncother.c - - - mbutils.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\functions\mbutils.c - - - mbcrc.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\rtu\mbcrc.c - - - mbrtu.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\rtu\mbrtu.c - - - mbtcp.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\tcp\mbtcp.c - - - mb.c - 1 - ..\..\..\..\components\connectivity\Modbus\3rdparty\freemodbus-v1.6\modbus\mb.c - - - - - modbus_port - - - portevent.c - 1 - ..\..\BSP\Hardware\Modbus_Port\portevent.c - - - portserial.c - 1 - ..\..\BSP\Hardware\Modbus_Port\portserial.c - - - porttimer.c - 1 - ..\..\BSP\Hardware\Modbus_Port\porttimer.c - - - - - ::CMSIS - - - - - - - - - - - - - - - - - - -
diff --git a/board/TencentOS_tiny_EVB_MX_Plus/KEIL/modbus/startup_stm32l431xx.s b/board/TencentOS_tiny_EVB_MX_Plus/KEIL/modbus/startup_stm32l431xx.s deleted file mode 100644 index 6a5c15a58..000000000 --- a/board/TencentOS_tiny_EVB_MX_Plus/KEIL/modbus/startup_stm32l431xx.s +++ /dev/null @@ -1,404 +0,0 @@ -;********************** COPYRIGHT(c) 2017 STMicroelectronics ****************** -;* File Name : startup_stm32l431xx.s -;* Author : MCD Application Team -;* Description : STM32L431xx Ultra Low Power devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x100 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x100 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 - DCD ADC1_IRQHandler ; ADC1 - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 - DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD 0 ; Reserved - DCD SPI3_IRQHandler ; SPI3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 - DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 - DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 - DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 - DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD COMP_IRQHandler ; COMP Interrupt - DCD LPTIM1_IRQHandler ; LP TIM1 interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 interrupt - DCD 0 ; Reserved - DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 - DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD QUADSPI_IRQHandler ; Quad SPI global interrupt - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt - DCD 0 ; Reserved - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TSC_IRQHandler ; Touch Sense Controller global interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD RNG_IRQHandler ; RNG global interrupt - DCD FPU_IRQHandler ; FPU - DCD CRS_IRQHandler ; CRS interrupt - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_PVM_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT SDMMC1_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Channel1_IRQHandler [WEAK] - EXPORT DMA2_Channel2_IRQHandler [WEAK] - EXPORT DMA2_Channel3_IRQHandler [WEAK] - EXPORT DMA2_Channel4_IRQHandler [WEAK] - EXPORT DMA2_Channel5_IRQHandler [WEAK] - EXPORT COMP_IRQHandler [WEAK] - EXPORT LPTIM1_IRQHandler [WEAK] - EXPORT LPTIM2_IRQHandler [WEAK] - EXPORT DMA2_Channel6_IRQHandler [WEAK] - EXPORT DMA2_Channel7_IRQHandler [WEAK] - EXPORT LPUART1_IRQHandler [WEAK] - EXPORT QUADSPI_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT SWPMI1_IRQHandler [WEAK] - EXPORT TSC_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT CRS_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_PVM_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -ADC1_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM15_IRQHandler -TIM1_UP_TIM16_IRQHandler -TIM1_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -SDMMC1_IRQHandler -SPI3_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Channel1_IRQHandler -DMA2_Channel2_IRQHandler -DMA2_Channel3_IRQHandler -DMA2_Channel4_IRQHandler -DMA2_Channel5_IRQHandler -COMP_IRQHandler -LPTIM1_IRQHandler -LPTIM2_IRQHandler -DMA2_Channel6_IRQHandler -DMA2_Channel7_IRQHandler -LPUART1_IRQHandler -QUADSPI_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -SAI1_IRQHandler -SWPMI1_IRQHandler -TSC_IRQHandler -RNG_IRQHandler -FPU_IRQHandler -CRS_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/board/TencentOS_tiny_STM32H750/KEIL/mqtt_client_iot_exporer/demo/mqttclient_iot_explorer.c b/board/TencentOS_tiny_STM32H750/KEIL/mqtt_client_iot_exporer/demo/mqttclient_iot_explorer.c index 30fbd63b1..3b4bcc11b 100644 --- a/board/TencentOS_tiny_STM32H750/KEIL/mqtt_client_iot_exporer/demo/mqttclient_iot_explorer.c +++ b/board/TencentOS_tiny_STM32H750/KEIL/mqtt_client_iot_exporer/demo/mqttclient_iot_explorer.c @@ -2,7 +2,7 @@ #include "mcu_init.h" #include "tos_k.h" #include "mqttclient.h" -#include "cjson.h" +#include "cJSON.h" #include "sal_module_wrapper.h" #define USE_ESP8266 diff --git a/components/ai/nnom/LICENSE b/components/ai/nnom/LICENSE new file mode 100644 index 000000000..f4f87bd4e --- /dev/null +++ b/components/ai/nnom/LICENSE @@ -0,0 +1,203 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. For the purposes of this definition, + "control" means (i) the power, direct or indirect, to cause the + direction or management of such entity, whether by contract or + otherwise, or (ii) ownership of fifty percent (50%) or more of the + outstanding shares, or (iii) beneficial ownership of such entity. + + "You" (or "Your") shall mean an individual or Legal Entity + exercising permissions granted by this License. + + "Source" form shall mean the preferred form for making modifications, + including but not limited to software source code, documentation + source, and configuration files. + + "Object" form shall mean any form resulting from mechanical + transformation or translation of a Source form, including but + not limited to compiled object code, generated documentation, + and conversions to other media types. + + "Work" shall mean the work of authorship, whether in Source or + Object form, made available under the License, as indicated by a + copyright notice that is included in or attached to the work + (an example is provided in the Appendix below). + + "Derivative Works" shall mean any work, whether in Source or Object + form, that is based on (or derived from) the Work and for which the + editorial revisions, annotations, elaborations, or other modifications + represent, as a whole, an original work of authorship. For the purposes + of this License, Derivative Works shall not include works that remain + separable from, or merely link (or bind by name) to the interfaces of, + the Work and Derivative Works thereof. + + "Contribution" shall mean any work of authorship, including + the original version of the Work and any modifications or additions + to that Work or Derivative Works thereof, that is intentionally + submitted to Licensor for inclusion in the Work by the copyright owner + or by an individual or Legal Entity authorized to submit on behalf of + the copyright owner. For the purposes of this definition, "submitted" + means any form of electronic, verbal, or written communication sent + to the Licensor or its representatives, including but not limited to + communication on electronic mailing lists, source code control systems, + and issue tracking systems that are managed by, or on behalf of, the + Licensor for the purpose of discussing and improving the Work, but + excluding communication that is conspicuously marked or otherwise + designated in writing by the copyright owner as "Not a Contribution." + + "Contributor" shall mean Licensor and any individual or Legal Entity + on behalf of whom a Contribution has been received by Licensor and + subsequently incorporated within the Work. + + 2. Grant of Copyright License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + copyright license to reproduce, prepare Derivative Works of, + publicly display, publicly perform, sublicense, and distribute the + Work and such Derivative Works in Source or Object form. + + 3. Grant of Patent License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + (except as stated in this section) patent license to make, have made, + use, offer to sell, sell, import, and otherwise transfer the Work, + where such license applies only to those patent claims licensable + by such Contributor that are necessarily infringed by their + Contribution(s) alone or by combination of their Contribution(s) + with the Work to which such Contribution(s) was submitted. If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + + 4. Redistribution. You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. The contents + of the NOTICE file are for informational purposes only and + do not modify the License. You may add Your own attribution + notices within Derivative Works that You distribute, alongside + or as an addendum to the NOTICE text from the Work, provided + that such additional attribution notices cannot be construed + as modifying the License. + + You may add Your own copyright statement to Your modifications and + may provide additional or different license terms and conditions + for use, reproduction, or distribution of Your modifications, or + for any such Derivative Works as a whole, provided Your use, + reproduction, and distribution of the Work otherwise complies with + the conditions stated in this License. + + 5. Submission of Contributions. Unless You explicitly state otherwise, + any Contribution intentionally submitted for inclusion in the Work + by You to the Licensor shall be under the terms and conditions of + this License, without any additional terms or conditions. + Notwithstanding the above, nothing herein shall supersede or modify + the terms of any separate license agreement you may have executed + with Licensor regarding such Contributions. + + 6. Trademarks. This License does not grant permission to use the trade + names, trademarks, service marks, or product names of the Licensor, + except as required for reasonable and customary use in describing the + origin of the Work and reproducing the content of the NOTICE file. + + 7. Disclaimer of Warranty. Unless required by applicable law or + agreed to in writing, Licensor provides the Work (and each + Contributor provides its Contributions) on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied, including, without limitation, any warranties or conditions + of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A + PARTICULAR PURPOSE. You are solely responsible for determining the + appropriateness of using or redistributing the Work and assume any + risks associated with Your exercise of permissions under this License. + + 8. Limitation of Liability. In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + \ No newline at end of file diff --git a/components/ai/nnom/README.md b/components/ai/nnom/README.md new file mode 100644 index 000000000..aff1acc62 --- /dev/null +++ b/components/ai/nnom/README.md @@ -0,0 +1,39 @@ + +# Neural Network on Microcontroller (NNoM) +[![Build Status](https://travis-ci.com/majianjia/nnom.svg?branch=master)](https://travis-ci.com/majianjia/nnom) +[![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) +[![DOI](https://zenodo.org/badge/166869630.svg)](https://zenodo.org/badge/latestdoi/166869630) + +NNoM is a high-level inference Neural Network library specifically for microcontrollers. + +介绍详情可以参考:https://github.com/majianjia/nnom + +原作者提供了基于keras的训练模型方法,以及如何配置NNoM的详细文档介绍 + + + +本项目提供一个基于NNoM的软件包,方便在tos上的快捷移植(测试通过平台为stm32l496ZG) + +mnist示例可以参考board/NUCLEO_STM32L496ZG/KEIL/nnom_mnist + +## 在TencentOS-tiny上的使用说明 + +1. 在keil工程里添加components / ai / nnom中的src文件夹下的backends、core、layers三个文件夹中的全部.c文件 +2. 在keil工程中包含inc和port文件夹中的全部头文件 +3. 在nnom_port.h指定内存使用方法(测试示例中开启了 NNOM_USING_STATIC_MEMORY宏 ),若使用非静态内存方法需要将nnom_malloc(n)和nnom_free(n)定义为os本身的内存api,对tos是tos_mmheap_alloc(n)和tos_mmheap_free(n) +4. 若使用静态内存,则需要定义static_buf[size]并使用nnom_set_static_buf(static_buf, sizeof(static_buf))函数去指定静态内存地址与大小,并根据模型需要调整静态内存大小。 +5. 编写示例函数,参考:example/nnom_mnsit中的nnom_mnist_example写法,按照需要实现系统api,比如使用tos_systick_get()去获取系统tick,从而计算推理时间。 + + + +## 注意事项 + +在keil下确认printf已经成功实现(检查microlib选项),并注意选择ARM Compiler为Use default compiler version 5 + + + +## Licenses + +NNoM is released under Apache License 2.0 since nnom-V0.2.0. +License and copyright information can be found within the code. + diff --git a/components/ai/nnom/inc/layers/nnom_activation.h b/components/ai/nnom/inc/layers/nnom_activation.h new file mode 100644 index 000000000..7cda07ce3 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_activation.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_ACTIVATION_H__ +#define __NNOM_ACTIVATION_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + + +// activation layer +typedef struct _nnom_activation_layer_t +{ + nnom_layer_t super; + nnom_activation_t *act; +} nnom_activation_layer_t; + + +// activation with fixed q format (tanh and sigmoid) +typedef struct _nnom_activation_fixed_q_t +{ + nnom_activation_t super; + uint8_t dec_bit; +} nnom_activation_fixed_q_t; + +// leaky relu +typedef struct _nnom_activation_leaky_relu_t +{ + nnom_activation_t super; + q7_t alpha; // alpha is present by q0.7 format. (-128 = -1) +} nnom_activation_leaky_relu_t; + +// advance relu (full ReLU) +typedef struct _nnom_activation_adv_relu_t +{ + nnom_activation_t super; + q7_t negative_slope; // negative_slope is present by q0.7 format. (-128 = -1) + float max; // cap of the max value + float threshold; // threshold +} nnom_activation_adv_relu_t; + +// method +nnom_status_t activation_run(nnom_layer_t* layer); +nnom_status_t activation_free(nnom_layer_t *layer); + +// activation delete +void act_delete(nnom_activation_t* act); + +// a direct api on tensor +nnom_status_t act_tensor_run(nnom_activation_t* act, nnom_tensor_t* tensor); + + +// Layer API +nnom_layer_t *Activation(nnom_activation_t *act); +nnom_layer_t *ReLU(void); +nnom_layer_t *LeakyReLU(float alpha); +nnom_layer_t *AdvReLU(float alpha, float max, float threshold); +nnom_layer_t *Sigmoid(int32_t dec_bit); +nnom_layer_t *TanH(int32_t dec_bit); + +// Activation API. +nnom_activation_t* act_relu(void); +nnom_activation_t* act_leaky_relu(float alpha); +nnom_activation_t* act_adv_relu(float negative_slope, float max, float threshold); +nnom_activation_t* act_tanh(int32_t dec_bit); +nnom_activation_t* act_sigmoid(int32_t dec_bit); +nnom_activation_t* act_hard_tanh(int32_t dec_bit); +nnom_activation_t* act_hard_sigmoid(int32_t dec_bit); + +// utils +int32_t act_get_dec_bit(nnom_activation_type_t type, int32_t dec_bit); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_ACTIVATION_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_avgpool.h b/components/ai/nnom/inc/layers/nnom_avgpool.h new file mode 100644 index 000000000..6f8354630 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_avgpool.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_AVGPOOL_H__ +#define __NNOM_AVGPOOL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +#include "layers/nnom_maxpool.h" + +// Avg Pooling +typedef nnom_maxpool_layer_t nnom_avgpool_layer_t; + +// method +nnom_status_t avgpooling_build(nnom_layer_t *layer); +nnom_status_t avgpool_run(nnom_layer_t *layer); + +// API +nnom_layer_t *avgpool_s(const nnom_pool_config_t * config); +nnom_layer_t *AvgPool(nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_padding_t pad_type); + + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_AVGPOOL_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_baselayer.h b/components/ai/nnom/inc/layers/nnom_baselayer.h new file mode 100644 index 000000000..940bce578 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_baselayer.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_BASELAYER_H__ +#define __NNOM_BASELAYER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +#include "layers/nnom_input.h" + +// method +nnom_status_t default_build(nnom_layer_t *layer); +nnom_status_t default_run(nnom_layer_t *layer); + +// API +nnom_layer_t *baselayer_s(const nnom_layer_config_t * config); +nnom_layer_t *BaseLayer(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_BASELAYER_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_concat.h b/components/ai/nnom/inc/layers/nnom_concat.h new file mode 100644 index 000000000..d47b26365 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_concat.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_CONCAT_H__ +#define __NNOM_CONCAT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +// concatenate layer +typedef struct _nnom_concat_layer +{ + nnom_layer_t super; + int8_t axis; +} nnom_concat_layer_t; + +typedef struct _nnom_concat_config_t +{ + nnom_layer_config_t super; + int8_t axis; +} nnom_concat_config_t; + +// method +nnom_status_t concat_build(nnom_layer_t *layer); +nnom_status_t concat_run(nnom_layer_t *layer); + +// API +nnom_layer_t *concat_s(const nnom_concat_config_t *config); +nnom_layer_t *Concat(int8_t axis); + + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_CONCAT_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_conv2d.h b/components/ai/nnom/inc/layers/nnom_conv2d.h new file mode 100644 index 000000000..2b6efb198 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_conv2d.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_CONV2D_H__ +#define __NNOM_CONV2D_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +// child layers parameters +typedef struct _nnom_conv2d_layer_t +{ + nnom_layer_t super; + nnom_3d_shape_t kernel; + nnom_3d_shape_t stride; + nnom_3d_shape_t pad; + nnom_3d_shape_t dilation; + nnom_padding_t padding_type; + uint32_t filter_mult; // filter size (for conv) or multilplier (for depthwise) + + nnom_tensor_t *weight; + nnom_tensor_t *bias; + + // test + nnom_qformat_param_t * output_rshift; + nnom_qformat_param_t * bias_lshift; +} nnom_conv2d_layer_t; + +// a machine interface for configuration +typedef struct _nnom_conv2d_config_t +{ + nnom_layer_config_t super; + nnom_qtype_t qtype; //quantisation type(per channel or per layer) + nnom_tensor_t *weight; + nnom_tensor_t *bias; + nnom_qformat_param_t *output_shift; + nnom_qformat_param_t *bias_shift; + uint32_t filter_size; + int8_t kernel_size[2]; + int8_t stride_size[2]; + int8_t padding_size[2]; + int8_t dilation_size[2]; + nnom_padding_t padding_type; +} nnom_conv2d_config_t; + +// method +nnom_status_t conv2d_run(nnom_layer_t *layer); +nnom_status_t conv2d_build(nnom_layer_t *layer); +nnom_status_t conv2d_free(nnom_layer_t *layer); + +// utils +uint32_t conv_output_length(uint32_t input_length, uint32_t filter_size, nnom_padding_t padding, uint32_t stride, uint32_t dilation); + +// API +nnom_layer_t *conv2d_s(const nnom_conv2d_config_t *config); +nnom_layer_t *Conv2D(uint32_t filters, nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_3d_shape_t d, nnom_padding_t pad_type, + const nnom_weight_t *w, const nnom_bias_t *b); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_CONV2D_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_conv2d_trans.h b/components/ai/nnom/inc/layers/nnom_conv2d_trans.h new file mode 100644 index 000000000..26249f3d9 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_conv2d_trans.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-30 Jianjia Ma The first version + */ + +#ifndef __NNOM_DECONV2D_H__ +#define __NNOM_DECONV2D_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" +#include "layers/nnom_conv2d.h" + +// child layers parameters +typedef nnom_conv2d_layer_t nnom_conv2d_trans_layer_t; + +typedef nnom_conv2d_config_t nnom_conv2d_trans_config_t; + +// method +nnom_status_t conv2d_trans_run(nnom_layer_t *layer); +nnom_status_t conv2d_trans_build(nnom_layer_t *layer); + +// utils +uint32_t conv_trans_output_length(uint32_t input_length, uint32_t filter_size, nnom_padding_t padding, uint32_t stride, uint32_t dilation); + +// API +nnom_layer_t *conv2d_trans_s(const nnom_conv2d_config_t *config); +nnom_layer_t *Conv2DTrans(uint32_t filters, nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_3d_shape_t d, nnom_padding_t pad_type, + const nnom_weight_t *w, const nnom_bias_t *b); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_DECONV2D_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_cropping.h b/components/ai/nnom/inc/layers/nnom_cropping.h new file mode 100644 index 000000000..252357481 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_cropping.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_CROPPING_H__ +#define __NNOM_CROPPING_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +#include "layers/nnom_zero_padding.h" + +// Cropping, same as zeropadding +typedef nnom_zero_padding_layer_t nnom_cropping_layer_t; + +typedef nnom_zero_padding_config_t nnom_cropping_config_t; + +// method +nnom_status_t cropping_build(nnom_layer_t *layer); +nnom_status_t cropping_run(nnom_layer_t *layer); + +// API +nnom_layer_t * cropping_s(const nnom_cropping_config_t *config); +nnom_layer_t *Cropping(nnom_border_t pad); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_CROPPING_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_dense.h b/components/ai/nnom/inc/layers/nnom_dense.h new file mode 100644 index 000000000..a0504a317 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_dense.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_DENSE_H__ +#define __NNOM_DENSE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +typedef struct _nnom_dense_layer_t +{ + nnom_layer_t super; + size_t output_unit; + nnom_tensor_t *weight; + nnom_tensor_t *bias; + nnom_qformat_param_t *output_rshift; + nnom_qformat_param_t *bias_lshift; +} nnom_dense_layer_t; + +// a machine interface for configuration +typedef struct _nnom_dense_config_t +{ + nnom_layer_config_t super; + nnom_qtype_t qtype; //quantisation type(per channel or per layer) + nnom_tensor_t *weight; + nnom_tensor_t *bias; + nnom_qformat_param_t *output_shift; + nnom_qformat_param_t *bias_shift; +} nnom_dense_config_t; + +// method +nnom_status_t dense_free(nnom_layer_t *layer); +nnom_status_t dense_build(nnom_layer_t *layer); +nnom_status_t dense_run(nnom_layer_t *layer); + +// API +nnom_layer_t *dense_s(const nnom_dense_config_t *config); +nnom_layer_t *Dense(size_t output_unit, const nnom_weight_t *w, const nnom_bias_t *b); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_DENSE_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_dw_conv2d.h b/components/ai/nnom/inc/layers/nnom_dw_conv2d.h new file mode 100644 index 000000000..5a9b58b25 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_dw_conv2d.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_DW_CONV2D_H__ +#define __NNOM_DW_CONV2D_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +#include "layers/nnom_conv2d.h" + +// method +nnom_status_t dw_conv2d_build(nnom_layer_t *layer); +nnom_status_t dw_conv2d_run(nnom_layer_t *layer); + +//API +nnom_layer_t *dw_conv2d_s(const nnom_conv2d_config_t *config); +nnom_layer_t *DW_Conv2D(uint32_t multiplier, nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_3d_shape_t d, nnom_padding_t pad_type, + const nnom_weight_t *w, const nnom_bias_t *b); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_DW_CONV2D_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_flatten.h b/components/ai/nnom/inc/layers/nnom_flatten.h new file mode 100644 index 000000000..c77160fca --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_flatten.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_FLATTEN_H__ +#define __NNOM_FLATTEN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +// no special parameters but we need it. +typedef struct _nnom_flatten_config_t{ + nnom_layer_config_t super; +} nnom_flatten_config_t; + +// method +nnom_status_t flatten_build(nnom_layer_t *layer); +nnom_status_t flatten_run(nnom_layer_t *layer); + +// API +nnom_layer_t *flatten_s(const nnom_flatten_config_t *config); +nnom_layer_t *Flatten(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_FLATTEN_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_global_pool.h b/components/ai/nnom/inc/layers/nnom_global_pool.h new file mode 100644 index 000000000..febccb0e8 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_global_pool.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_GLOBAL_POOL_H__ +#define __NNOM_GLOBAL_POOL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +#include "layers/nnom_maxpool.h" + +typedef struct _nnom_global_pool_config_t +{ + nnom_layer_config_t super; + int16_t output_shift; +}nnom_global_pool_config_t; + +// method +nnom_status_t global_pool_build(nnom_layer_t *layer); + +// API +nnom_layer_t * global_maxpool_s(const nnom_global_pool_config_t *config); +nnom_layer_t * global_avgpool_s(const nnom_global_pool_config_t *config); +nnom_layer_t * global_sumpool_s(const nnom_global_pool_config_t *config); + +nnom_layer_t *GlobalMaxPool(void); +nnom_layer_t *GlobalAvgPool(void); +nnom_layer_t *GlobalSumPool(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_GLOBAL_POOL_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_gru_cell.h b/components/ai/nnom/inc/layers/nnom_gru_cell.h new file mode 100644 index 000000000..8ba459624 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_gru_cell.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-27 Jianjia Ma The first version + */ + +#ifndef __NNOM_GRU_CELL_H__ +#define __NNOM_GRU_CELL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nnom_rnn.h" +#include "nnom_activation.h" + +typedef struct _nnom_gru_cell_config_t +{ + nnom_layer_config_t super; + nnom_tensor_t *weights; + nnom_tensor_t* recurrent_weights; + nnom_tensor_t *bias; + nnom_qformat_param_t q_dec_z, q_dec_h; // z, r, h + uint16_t units; +} nnom_gru_cell_config_t; + + +typedef struct _nnom_gru_cell_t +{ + nnom_rnn_cell_t super; + + nnom_tensor_t* weights; + nnom_tensor_t* recurrent_weights; + nnom_tensor_t* bias; + + // decide later. + // z, r, h + nnom_qformat_param_t q_dec_z, q_dec_h; + nnom_qformat_param_t oshift_iw, oshift_hw, bias_shift; + +} nnom_gru_cell_t; + +// gru +nnom_rnn_cell_t *gru_cell_s(const nnom_gru_cell_config_t* config); + +nnom_status_t gru_cell_free(nnom_rnn_cell_t* cell); +nnom_status_t gru_cell_build(nnom_rnn_cell_t* cell); +nnom_status_t gru_cell_run(nnom_rnn_cell_t* cell); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_GRU_CELL_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_input.h b/components/ai/nnom/inc/layers/nnom_input.h new file mode 100644 index 000000000..42322a61f --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_input.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_INPUT_H__ +#define __NNOM_INPUT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +// IO layer +typedef struct _nnom_io_layer +{ + nnom_layer_t super; + nnom_3d_shape_t shape; + nnom_qformat_param_t dec_bit; + void *buf; //input or output +} nnom_io_layer_t; + +typedef struct _nnom_io_config_t +{ + nnom_layer_config_t super; + nnom_tensor_t *tensor; +}nnom_io_config_t; + +// method +nnom_status_t input_build(nnom_layer_t *layer); +nnom_status_t input_run(nnom_layer_t *layer); + +// API +nnom_layer_t *input_s(const nnom_io_config_t* config); +nnom_layer_t *Input(nnom_3d_shape_t input_shape, void *p_buf); + + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_INPUT_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_lambda.h b/components/ai/nnom/inc/layers/nnom_lambda.h new file mode 100644 index 000000000..80c5e6915 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_lambda.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_LAMBDA_H__ +#define __NNOM_LAMBDA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +#include "layers/nnom_input.h" + +// lambda layer +typedef struct _nnom_lambda_layer_t +{ + nnom_layer_t super; + void *parameters; // parameters for lambda +} nnom_lambda_layer_t; + +// lambda layer +typedef struct _nnom_lambda_config_t +{ + nnom_layer_config_t super; + nnom_status_t (*run_func_name)(nnom_layer_t *layer); // run method. required + nnom_status_t (*build_func_name)(nnom_layer_t *layer);// compute output buffer shape. can be left null, will call default_build() + nnom_status_t (*free_func_name)(nnom_layer_t *layer); // a callback to free private resources (comp buf not included) can be left null + void *parameters; // parameters for lambda +} nnom_lambda_config_t; + + + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_LAMBDA_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_lstm_cell.h b/components/ai/nnom/inc/layers/nnom_lstm_cell.h new file mode 100644 index 000000000..f0563fc91 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_lstm_cell.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-24 Jianjia Ma The first version + */ + +#ifndef __NNOM_LSTM_CELL_H__ +#define __NNOM_LSTM_CELL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nnom_rnn.h" +#include "nnom_activation.h" + +// a machine interface for configuration +typedef struct _nnom_lstm_cell_config_t +{ + nnom_layer_config_t super; + nnom_tensor_t *weights; + nnom_tensor_t* recurrent_weights; + nnom_tensor_t *bias; + nnom_qformat_param_t q_dec_z, q_dec_h, q_dec_c; // z = iw + hw, c = cell state; h=output and memory + uint16_t units; +} nnom_lstm_cell_config_t; + + +typedef struct _nnom_lstm_cell_t +{ + nnom_rnn_cell_t super; + + nnom_tensor_t* weights; + nnom_tensor_t* recurrent_weights; + nnom_tensor_t* bias; + + // experimental, + // iw: input x weight + // hw: hidden state x recurrent weight + // h: hidden state (memor) + // c: cell state + nnom_qformat_param_t q_dec_z, q_dec_h, q_dec_c; + nnom_qformat_param_t oshift_iw, oshift_hw, oshift_zc, bias_shift; + +} nnom_lstm_cell_t; + +// LSTM +nnom_rnn_cell_t *lstm_cell_s(const nnom_lstm_cell_config_t* config); + +nnom_status_t lstm_cell_free(nnom_rnn_cell_t* cell); +nnom_status_t lstm_cell_q7_q15_build(nnom_rnn_cell_t* cell); +nnom_status_t lstm_cell_q7_q15_run(nnom_rnn_cell_t* cell); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_LSTM_CELL_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_matrix.h b/components/ai/nnom/inc/layers/nnom_matrix.h new file mode 100644 index 000000000..11b775bbe --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_matrix.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_MATRIX_H__ +#define __NNOM_MATRIX_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +// the maximum input layer hooked to this layer +#define MAX_INPUT_LAYER 8 + +// matrix layer +typedef struct _nnom_matrix_layer_t +{ + nnom_layer_t super; + int16_t oshift; // output right shift +} nnom_matrix_layer_t; + +typedef struct _nnom_matrix_config_t +{ + nnom_layer_config_t super; + int16_t output_shift; // output right shift +} nnom_matrix_config_t; + +// methods +nnom_layer_t* _same_shape_matrix_layer(void); +nnom_status_t add_run(nnom_layer_t *layer); +nnom_status_t sub_run(nnom_layer_t *layer); +nnom_status_t mult_run(nnom_layer_t *layer); + +// API +nnom_layer_t *add_s(const nnom_matrix_config_t * config); +nnom_layer_t *sub_s(const nnom_matrix_config_t * config); +nnom_layer_t *mult_s(const nnom_matrix_config_t * config); +nnom_layer_t *Add(int16_t oshift); +nnom_layer_t *Sub(int16_t oshift); +nnom_layer_t *Mult(int16_t oshift); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_MATRIX_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_maxpool.h b/components/ai/nnom/inc/layers/nnom_maxpool.h new file mode 100644 index 000000000..690a02d2f --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_maxpool.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_MAXPOOL_H__ +#define __NNOM_MAXPOOL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +// Max Pooling +typedef struct _nnom_maxpool_layer_t +{ + nnom_layer_t super; + nnom_3d_shape_t kernel; + nnom_3d_shape_t stride; + nnom_3d_shape_t pad; + nnom_padding_t padding_type; + int16_t output_shift; // reserve +} nnom_maxpool_layer_t; + +// a machine interface for configuration +typedef struct _nnom_pool_config_t +{ + nnom_layer_config_t super; + nnom_padding_t padding_type; + int16_t output_shift; + int8_t kernel_size[2]; + int8_t stride_size[2]; + int8_t num_dim; +} nnom_pool_config_t; + +// method +nnom_status_t maxpool_build(nnom_layer_t *layer); +nnom_status_t maxpool_run(nnom_layer_t *layer); + +// API +nnom_layer_t *maxpool_s(const nnom_pool_config_t * config); +nnom_layer_t *MaxPool(nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_padding_t pad_type); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_MATRIX_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_output.h b/components/ai/nnom/inc/layers/nnom_output.h new file mode 100644 index 000000000..8e62e22f2 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_output.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_OUTPUT_H__ +#define __NNOM_OUTPUT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +#include "layers/nnom_input.h" + +// method +nnom_status_t output_build(nnom_layer_t *layer); +nnom_status_t output_run(nnom_layer_t *layer); + +// API +nnom_layer_t *output_s(const nnom_io_config_t* config); +nnom_layer_t *Output(nnom_3d_shape_t output_shape, void *p_buf); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_OUTPUT_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_rnn.h b/components/ai/nnom/inc/layers/nnom_rnn.h new file mode 100644 index 000000000..6a9d6efb6 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_rnn.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_RNN_H__ +#define __NNOM_RNN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +// a machine interface for configuration +typedef struct _nnom_rnn_config_t +{ + nnom_layer_config_t super; + bool return_sequence; + bool stateful; + bool go_backwards; +} nnom_rnn_config_t; + +// RNN cell base type +typedef struct _nnom_rnn_cell_t +{ + nnom_status_t (*run)(struct _nnom_rnn_cell_t* cell); // cell runner + nnom_status_t (*build)(struct _nnom_rnn_cell_t* cell); // cell builder, calculate buffer size, output data size + nnom_status_t (*free)(struct _nnom_rnn_cell_t* cell); // + nnom_layer_t *layer; // pointer to its layer holder + nnom_layer_config_t *config; // config for the cell event it is a layer type + nnom_rnn_cell_type_t type; + + void *in_data; // input data + void *out_data; // output data + void *in_state; // input state data (or hidden state) + void *out_state; // output state data + + size_t comp_buf_size; // the size of temporary buffer. + size_t state_size; // the size of hidden state + uint16_t units; // the output units + uint16_t feature_size; // the input feature size (vector size) + + size_t macc; // stat of MAC count. +} nnom_rnn_cell_t; + +typedef struct _nnom_rnn_layer_t +{ + nnom_layer_t super; + nnom_rnn_cell_t *cell; + void *state_buf; // memory allocated to store state, size = 2 x size of state required by cell. + + uint16_t timestamp_size;// size of timestamp + bool return_sequence; // whether to return the output for each unit (sequence) + bool stateful; // whether the states are kept after one inteference + bool go_backwards; // whether go backwards timestamping +} nnom_rnn_layer_t; + + +// rnn layer +nnom_layer_t *rnn_s(nnom_rnn_cell_t *cell, const nnom_rnn_config_t* config); + +nnom_status_t rnn_run(nnom_layer_t* layer); +nnom_status_t rnn_build(nnom_layer_t* layer); +nnom_status_t rnn_free(nnom_layer_t* layer); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_RNN_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_simple_cell.h b/components/ai/nnom/inc/layers/nnom_simple_cell.h new file mode 100644 index 000000000..87977ed8f --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_simple_cell.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-20 Jianjia Ma The first version + */ + +#ifndef __NNOM_SIMPLE_CELL_H__ +#define __NNOM_SIMPLE_CELL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nnom_rnn.h" +#include "nnom_activation.h" + + +// This Simple Cell replicate the Keras's SimpleCell as blow +/* + def call(self, inputs, states, training=None): + prev_output = states[0] if nest.is_sequence(states) else states + + h = K.dot(inputs, self.kernel) + h = K.bias_add(h, self.bias) + + output = h + K.dot(prev_output, self.recurrent_kernel) + output = self.activation(output) + + new_state = [output] if nest.is_sequence(states) else output + return output, new_state +*/ + +// a machine interface for configuration +typedef struct _nnom_simple_cell_config_t +{ + nnom_layer_config_t super; + nnom_tensor_t *weights; + nnom_tensor_t* recurrent_weights; + nnom_tensor_t *bias; + nnom_qformat_param_t q_dec_iw, q_dec_hw, q_dec_h; + nnom_activation_type_t act_type; // type of the activation + uint16_t units; +} nnom_simple_cell_config_t; + + +typedef struct _nnom_simple_cell_t +{ + nnom_rnn_cell_t super; + nnom_activation_type_t act_type; + + nnom_tensor_t* weights; + nnom_tensor_t* recurrent_weights; + nnom_tensor_t* bias; + + // experimental, + // iw: input x weight + // hw: hidden state x recurrent weight + // h: hidden state + nnom_qformat_param_t q_dec_iw, q_dec_hw, q_dec_h; + nnom_qformat_param_t oshift_iw, oshift_hw, bias_shift; + +} nnom_simple_cell_t; + + +// RNN cells +// The shape for RNN input is (batch, timestamp, feature), where batch is always 1. +// +// SimpleCell +nnom_rnn_cell_t *simple_cell_s(const nnom_simple_cell_config_t* config); + +nnom_status_t simple_cell_free(nnom_rnn_cell_t* cell); +nnom_status_t simple_cell_build(nnom_rnn_cell_t* cell); +nnom_status_t simple_cell_run(nnom_rnn_cell_t* cell); + + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_SIMPLE_CELL_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_softmax.h b/components/ai/nnom/inc/layers/nnom_softmax.h new file mode 100644 index 000000000..230be3277 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_softmax.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_SOFTMAX_H__ +#define __NNOM_SOFTMAX_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +typedef struct _nnom_softmax_config_t +{ + nnom_layer_config_t super; +} nnom_softmax_config_t; + + +// method +nnom_status_t softmax_run(nnom_layer_t *layer); +nnom_status_t softmax_build(nnom_layer_t *layer); + +// API +nnom_layer_t *softmax_s(const nnom_softmax_config_t * config); +nnom_layer_t *Softmax(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_SOFTMAX_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_sumpool.h b/components/ai/nnom/inc/layers/nnom_sumpool.h new file mode 100644 index 000000000..927615e82 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_sumpool.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_SUMPOOL_H__ +#define __NNOM_SUMPOOL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +#include "layers/nnom_maxpool.h" + +// Sum Pooling +typedef nnom_maxpool_layer_t nnom_sumpool_layer_t; + +// method +nnom_status_t sumpool_build(nnom_layer_t *layer); +nnom_status_t sumpool_run(nnom_layer_t *layer); + +// API +nnom_layer_t *sumpool_s(const nnom_pool_config_t * config); +nnom_layer_t *SumPool(nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_padding_t pad_type); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_SUMPOOL_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_upsample.h b/components/ai/nnom/inc/layers/nnom_upsample.h new file mode 100644 index 000000000..5db7c9708 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_upsample.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_UPSAMPLE_H__ +#define __NNOM_UPSAMPLE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +// Up Sampling layer (UnPooling) +typedef struct _nnom_upsample_layer_t +{ + nnom_layer_t super; + nnom_3d_shape_t kernel; +} nnom_upsample_layer_t; + +typedef struct _nnom_upsample_config_t +{ + nnom_layer_config_t super; + nnom_shape_data_t kernel[2]; +} nnom_upsample_config_t; + +// API +nnom_layer_t *upsample_s(const nnom_upsample_config_t *config); +nnom_layer_t *UpSample(nnom_3d_shape_t kernel); + +// Methods +nnom_status_t upsample_build(nnom_layer_t *layer); +nnom_status_t upsample_run(nnom_layer_t *layer); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_UPSAMPLE_H__ */ diff --git a/components/ai/nnom/inc/layers/nnom_zero_padding.h b/components/ai/nnom/inc/layers/nnom_zero_padding.h new file mode 100644 index 000000000..9aefd6d03 --- /dev/null +++ b/components/ai/nnom/inc/layers/nnom_zero_padding.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-03 Jianjia Ma The first version + */ + +#ifndef __NNOM_ZERO_PADDING_H__ +#define __NNOM_ZERO_PADDING_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#include "nnom.h" +#include "nnom_layers.h" +#include "nnom_local.h" +#include "nnom_tensor.h" + +typedef struct _nnom_zero_padding_config_t +{ + nnom_layer_config_t super; + nnom_border_t pad; +} nnom_zero_padding_config_t; + +// zero padding +typedef struct _nnom_zero_padding_layer_t +{ + nnom_layer_t super; + nnom_border_t pad; +} nnom_zero_padding_layer_t; + +// API +nnom_layer_t *zeropadding_s(const nnom_zero_padding_config_t* config); +nnom_layer_t *ZeroPadding(nnom_border_t pad); + +// method +nnom_status_t zero_padding_build(nnom_layer_t *layer); +nnom_status_t zero_padding_run(nnom_layer_t *layer); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_ZERO_PADDING_H__ */ diff --git a/components/ai/nnom/inc/nnom.h b/components/ai/nnom/inc/nnom.h new file mode 100644 index 000000000..063175c1b --- /dev/null +++ b/components/ai/nnom/inc/nnom.h @@ -0,0 +1,413 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-02-05 Jianjia Ma The first version + * 2019-02-10 Jianjia Ma Compiler supports dense net connection + */ + +#ifndef __NNOM_H__ +#define __NNOM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#include +#include +#include +#include +#include + +#include "nnom_port.h" + +#define NNOM_ALIGN (sizeof(char*)) // alignment when doing memory ops. Equal to size of pointer in byte. +#define q7_t int8_t +#define q15_t int16_t +#define q31_t int32_t +#define q63_t int64_t + +/* version */ +#define NNOM_MAJORVERSION 0 /**< major version number */ +#define NNOM_SUBVERSION 4 /**< minor version number */ +#define NNOM_REVISION 3 /**< revise version number */ +#define NNOM_VERSION ((NNOM_MAJORVERSION * 10000) + (NNOM_SUBVERSION * 100) + NNOM_REVISION) + +#ifdef ARM_NN_TRUNCATE +#define NNOM_TRUNCATE +#endif + +#ifndef NNOM_TRUNCATE + #define NNOM_ROUND(out_shift) ((0x1 << out_shift) >> 1 ) +#else + #define NNOM_ROUND(out_shift) 0 +#endif + +typedef enum +{ + NN_SUCCESS = 0, /**< No error */ + NN_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + NN_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + NN_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + NN_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + NN_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + NN_TEST_FAILURE = -6, /**< Test Failed */ + NN_NO_MEMORY = -7, + NN_MORE_TODO = -8 +} nnom_status_t; + +typedef enum +{ + NNOM_INVALID = 0, + NNOM_BASE, + NNOM_INPUT, + NNOM_OUTPUT, + NNOM_CONV_2D, + NNOM_DW_CONV_2D, + NNOM_CONV2D_TRANS, + NNOM_BATCHNORM, + NNOM_DENSE, + NNOM_ZERO_PADDING, + NNOM_CROPPING, + NNOM_RNN, + NNOM_ACTIVATION, + NNOM_RELU, + NNOM_LEAKY_RELU, + NNOM_ADV_RELU, + NNOM_SIGMOID, + NNOM_TANH, + NNOM_SOFTMAX, + NNOM_MAXPOOL, + NNOM_GLOBAL_MAXPOOL, + NNOM_AVGPOOL, + NNOM_GLOBAL_AVGPOOL, + NNOM_SUMPOOL, + NNOM_GLOBAL_SUMPOOL, + NNOM_UPSAMPLE, + NNOM_FLATTEN, + NNOM_LAMBDA, + NNOM_CONCAT, + NNOM_ADD, + NNOM_SUB, + NNOM_MULT, + NNOM_TYPE_MAX + +} nnom_layer_type_t; + +#define DEFUALT_LAYER_NAMES \ + { \ + "Unknown", \ + "Base", \ + "Input", \ + "Output", \ + "Conv2D", \ + "DW_Conv2D", \ + "Conv2DTrsp", \ + "BatchNorm", \ + "Dense", \ + "ZeroPad", \ + "Cropping", \ + "RNN", \ + "Activation", \ + "ReLU", \ + "Leaky_ReLU", \ + "Adv_ReLU", \ + "Sigmoid", \ + "Tanh", \ + "Softmax", \ + "MaxPool", \ + "GL_MaxPool", \ + "AvgPool", \ + "GL_AvgPool", \ + "SumPool", \ + "GL_SumPool", \ + "UpSample", \ + "Flatten", \ + "Lambda", \ + "Concat", \ + "Add", \ + "Sub", \ + "Mult", \ + } +extern const char default_layer_names[][12]; + +// We dont count softmax an activation here, softmax is instanced as a layer +typedef enum +{ + ACT_UNKNOWN = 0, + ACT_RELU, + ACT_LEAKY_RELU, + ACT_ADV_RELU, + ACT_TANH, + ACT_SIGMOID, + ACT_HARD_TANH, + ACT_HARD_SIGMOID +} nnom_activation_type_t; + +#define ACTIVATION_NAMES \ + { \ + "Unknown", \ + "ReLU", \ + "LkyReLU", \ + "AdvReLU", \ + "TanH", \ + "Sigmoid", \ + "HrdTanH", \ + "HrdSigd", \ + } +extern const char default_activation_names[][8]; + +// RNN cell type +typedef enum +{ + NNOM_UNKOWN_CELL = 0, + NNOM_SIMPLE_CELL, + NNOM_GRU_CELL, + NNOM_LSTM_CELL, + NNOM_CELL_TYPE_MAX +} nnom_rnn_cell_type_t; + +#define DEFUALT_CELL_NAMES \ + { \ + "Unknown", \ + "Simple", \ + "GRU", \ + "LSTM", \ + } +extern const char default_cell_names[][8]; + + +// parameters +typedef enum +{ + PADDING_VALID = 0, + PADDING_SAME +} nnom_padding_t; + +#define NNOM_TENSOR_BUF_NULL (0) // This buffer is not in used +#define NNOM_TENSOR_BUF_TEMP (1) // The memory in IO is temporary occupided, can be reused by other layer once the computation is done. +#define NNOM_TENSOR_BUF_RESERVED (2) // the mem is reserve for this layer only (not to be reused by other layer. + +// currently used in compiling. +#define NNOM_BUF_EMPTY (0) +#define NNOM_BUF_FILLED (1) + +// basic types +#define nnom_qformat_param_t int32_t // this should match the backend, need a better way to do it. +#define nnom_shape_data_t uint16_t + +typedef struct _nnom_3d_shape_t +{ + nnom_shape_data_t h, w, c; +} nnom_3d_shape_t; + +typedef struct _nnom_border_t +{ + nnom_shape_data_t top, bottom, left, right; +} nnom_border_t; + +// nnom_3d_shape_axis_t type provide the axis[] format access to nnom_3d_shape_t +typedef union { + nnom_3d_shape_t s; + nnom_shape_data_t axis[sizeof(nnom_3d_shape_t) / sizeof(nnom_shape_data_t)]; +} nnom_3d_shape_axis_t; + +// tensor quantisation types +typedef enum +{ + NNOM_QTYPE_PER_TENSOR = 0, + NNOM_QTYPE_PER_AXIS = 1 +} nnom_qtype_t; + +typedef struct _nnom_weights +{ + const void *p_value; + nnom_qformat_param_t shift; +} nnom_weight_t; + +typedef struct _nnom_bias +{ + const void *p_value; + nnom_qformat_param_t shift; +} nnom_bias_t; + +// experimental +typedef struct _nnom_tensor_t +{ + void* p_data; // value + nnom_shape_data_t *dim; // dimension of this tensor + nnom_qformat_param_t *q_dec; // number of decimal bit for Q format (scale) + nnom_qformat_param_t *q_offset; // offset for each channel + nnom_qtype_t qtype; // the quantisation type + uint8_t num_dim; // the number of dimension + uint8_t bitwidth; // the data bit width, only support 8bit now +} nnom_tensor_t; + +// nn wrappers +typedef struct _nnom_layer_t nnom_layer_t; +typedef struct _nnom_layer_io_t nnom_layer_io_t; +typedef struct _nnom_layer_hook_t nnom_layer_hook_t; +typedef struct _nnom_mem_block_t nnom_mem_block_t; + +// activation wrapper +typedef struct _nnom_activation_t nnom_activation_t; + +typedef struct _nnom_buf +{ + nnom_mem_block_t *mem; + size_t size; + uint8_t type; +} nnom_buf_t; + +// a memory block to store pre-assign memories during compiling. then assigned to each tensor after. +struct _nnom_mem_block_t +{ + void *blk; // data block location + size_t size; // the maximum size for this block + uint8_t owners; // how many layers own this block + uint8_t state; // empty? filled? for static nn, currently only used in compiling +}; + +typedef struct _nnom_stat_t +{ + size_t macc; //num. of mac operation + uint32_t time; +} nnom_layer_stat_t; + +struct _nnom_layer_hook_t +{ + nnom_layer_io_t *io; // hooked io + nnom_layer_hook_t *next; // next hook include secondary hooked layer +}; + +struct _nnom_layer_io_t +{ + nnom_layer_hook_t hook; // for example: (layer->out)--hook--(layer->in) + nnom_layer_io_t *aux; // point to auxilary I/O (multiple I/O layer) + nnom_tensor_t *tensor; // experimental + nnom_mem_block_t *mem; // memory blocks handles for compiling only. The memory are now pass by tensor. trying to remove it. + nnom_layer_t *owner; // which layer owns this io. + uint8_t type; +}; + +// structured configuration base type +typedef struct _nnom_layer_config_t +{ + char* name; // the name of the layer prequantiesd model (the model trained by user before converted to nnom) +} nnom_layer_config_t; + +// layers base +struct _nnom_layer_t +{ + nnom_layer_t *shortcut; // shortcut points to the next layer, applied on compiling + + nnom_status_t (*run)(nnom_layer_t *layer); // run method. required + nnom_status_t (*build)(nnom_layer_t *layer); // compute output buffer shape. can be left null, will call default_build() + nnom_status_t (*free)(nnom_layer_t *layer); // a callback to free private resources (comp buf not included) can be left null + nnom_buf_t *comp; // computational buf + nnom_activation_t *actail; // I have an activation, I have a tail, wooo haaaa, act-tail!!! + + nnom_layer_config_t *config; // point to the configuration of the layers. for machine api only. + nnom_layer_type_t type; // layer types + nnom_layer_io_t *in; // IO buff, last*layer, states + nnom_layer_io_t *out; // IO buff, next*layer, states + nnom_layer_stat_t stat; // stats, timing, ops +}; + +// activation base +struct _nnom_activation_t +{ + nnom_status_t (*run)(struct _nnom_activation_t *act); + nnom_tensor_t *tensor; + nnom_activation_type_t type; +}; + +// local static functions when libc is not available +#ifdef NNOM_USING_STATIC_MEMORY + void nnom_set_static_buf(void* buf, size_t size); + void *nnom_malloc(size_t size); + void nnom_free(void* p); +#endif //NNOM_USING_STATIC_BUF + +typedef struct _nnom_model nnom_model_t; + +#include "nnom_tensor.h" +#include "nnom_layers.h" +#include "nnom_utils.h" + +// models, I dont want to make model class as a child of layer class yet +struct _nnom_model +{ + nnom_layer_t *head; + nnom_layer_t *tail; + + // model constructor + nnom_status_t (*add)(struct _nnom_model *m, nnom_layer_t *layer); // has too pass a raw value + nnom_layer_t *(*hook)(nnom_layer_t *curr, nnom_layer_t *last); // create hook between 2 layers' primary IO. + nnom_layer_t *(*merge)(nnom_layer_t *method, nnom_layer_t *in1, nnom_layer_t *in2); // an older interface of merge 2 inputs. + nnom_layer_t *(*mergex)(nnom_layer_t *method, int num, ...); // merge a few layers using mutiple input method (concate, add, ...) + nnom_layer_t *(*active)(nnom_activation_t *act, nnom_layer_t *target_layer); // add the activation to the existing layer's tail + + // callback + nnom_status_t (*layer_callback)(nnom_model_t *m, nnom_layer_t *layer); // layer callback will be called after each layer(after actail). + + // block memory for layers + nnom_mem_block_t blocks[NNOM_BLOCK_NUM]; + + size_t total_ops; + + bool is_inited; // is this structure initialized + bool is_allocated; // is this structure allocated by nnom (not by user) +}; + +#define NNOM_NULL_CHECK(p) \ + if ((p) == NULL) \ + { \ + NNOM_LOG("Error: NULL object.\n"); \ + return NN_ARGUMENT_ERROR; \ + } + + +// utils +size_t nnom_alignto(size_t value, uint32_t alignment); +size_t nnom_io_length(nnom_layer_io_t *io); +size_t nnom_hook_length(nnom_layer_hook_t *hook); + +// memory (malloc + memeset 0) +void *nnom_mem(size_t size); + +// get how much memory has been taken +size_t nnom_mem_stat(void); + +// Model APIs +// create or init a model +nnom_model_t *new_model(nnom_model_t *m); +// compile as sequencial model +nnom_status_t sequencial_compile(nnom_model_t *m); +// compile as functional model +nnom_status_t model_compile(nnom_model_t *m, nnom_layer_t *input, nnom_layer_t *output); +// run a prediction +nnom_status_t model_run(nnom_model_t *m); +// delete model. +void model_delete(nnom_model_t *m); +// check version +nnom_status_t check_model_version(unsigned long model_version); + +// callback, called after each layer has finished the calculation. +// this callback must return NN_SUCCESS for continually run the model. otherwise, model will be returned with the ERROR code. +// this function return NN_LENGTH_ERROR if the callback is already set to other. +nnom_status_t model_set_callback(nnom_model_t *m, nnom_status_t (*layer_callback)(nnom_model_t *m, nnom_layer_t *layer)); +// delete callback. +void model_delete_callback(nnom_model_t *m); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_H__ */ diff --git a/components/ai/nnom/inc/nnom_layers.h b/components/ai/nnom/inc/nnom_layers.h new file mode 100644 index 000000000..de9aeb46b --- /dev/null +++ b/components/ai/nnom/inc/nnom_layers.h @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-02-05 Jianjia Ma The first version + */ + +#ifndef __NNOM_LAYERS_H__ +#define __NNOM_LAYERS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#include +#include +#include + +#include "nnom.h" + +// properties +nnom_3d_shape_t shape(size_t h, size_t w, size_t c); +nnom_3d_shape_t kernel(size_t h, size_t w); +nnom_3d_shape_t stride(size_t h, size_t w); +nnom_3d_shape_t dilation(size_t h, size_t w); +nnom_border_t border(size_t top, size_t bottom, size_t left, size_t right); +//nnom_qformat_t qformat(int8_t m, int8_t n); +size_t shape_size(nnom_3d_shape_t* s); + +// this function is to add a new IO to current inited IO +// input, the targeted IO that the new IO will be added to +// output , the new IO +nnom_layer_io_t* io_add_aux(nnom_layer_io_t* targeted_io); +nnom_layer_io_t *io_init(void *owner_layer, nnom_layer_io_t *io); + +#define NN_CEILIF(x,y) ((x+y-1)/y) + +#include "layers/nnom_activation.h" +#include "layers/nnom_concat.h" +#include "layers/nnom_conv2d.h" +#include "layers/nnom_cropping.h" +#include "layers/nnom_conv2d_trans.h" +#include "layers/nnom_dense.h" +#include "layers/nnom_dw_conv2d.h" +#include "layers/nnom_flatten.h" +#include "layers/nnom_global_pool.h" +#include "layers/nnom_input.h" +#include "layers/nnom_lambda.h" +#include "layers/nnom_matrix.h" +#include "layers/nnom_maxpool.h" +#include "layers/nnom_avgpool.h" +#include "layers/nnom_output.h" +#include "layers/nnom_rnn.h" +#include "layers/nnom_softmax.h" +#include "layers/nnom_sumpool.h" +#include "layers/nnom_upsample.h" +#include "layers/nnom_zero_padding.h" +#include "layers/nnom_rnn.h" +#include "layers/nnom_simple_cell.h" +#include "layers/nnom_lstm_cell.h" +#include "layers/nnom_gru_cell.h" + +// Layer APIs ****** +// (a summary for each individual layer's files) + +// input/output +nnom_layer_t *Input(nnom_3d_shape_t input_shape, void *p_buf); +nnom_layer_t *Output(nnom_3d_shape_t output_shape, void *p_buf); + +// Pooling +nnom_layer_t *MaxPool(nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_padding_t pad); +nnom_layer_t *AvgPool(nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_padding_t pad); +nnom_layer_t *SumPool(nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_padding_t pad); +nnom_layer_t *GlobalMaxPool(void); +nnom_layer_t *GlobalAvgPool(void); +nnom_layer_t *GlobalSumPool(void); + +// padding, cropping, upsample +nnom_layer_t *UpSample(nnom_3d_shape_t kernel); +nnom_layer_t *ZeroPadding(nnom_border_t pad); +nnom_layer_t *Cropping(nnom_border_t pad); + +// Activation +nnom_layer_t *Activation(nnom_activation_t *act); +nnom_layer_t *ReLU(void); +nnom_layer_t *LeakyReLU(float alpha); +nnom_layer_t *Softmax(void); +nnom_layer_t *Sigmoid(int32_t dec_bit); // input dec bit +nnom_layer_t *TanH(int32_t dec_bit); // input dec bit + +// Matrix +nnom_layer_t *Add(int16_t oshift); // output shift +nnom_layer_t *Sub(int16_t oshift); // output shift +nnom_layer_t *Mult(int16_t oshift); // output shift + +nnom_layer_t *Flatten(void); +nnom_layer_t *Concat(int8_t axis); +// -- NN Constructers -- +// conv2d +nnom_layer_t *Conv2D(uint32_t filters, nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_3d_shape_t d, nnom_padding_t pad, + const nnom_weight_t *w, const nnom_bias_t *b); + +// deconv2d +nnom_layer_t *Conv2DTrans(uint32_t filters, nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_3d_shape_t d, nnom_padding_t pad, + const nnom_weight_t *w, const nnom_bias_t *b); + +// depthwise_convolution +nnom_layer_t *DW_Conv2D(uint32_t multiplier, nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_3d_shape_t d, nnom_padding_t pad, + const nnom_weight_t *w, const nnom_bias_t *b); + +// fully connected, dense +nnom_layer_t *Dense(size_t output_unit, const nnom_weight_t *w, const nnom_bias_t *b); + + +// Lambda Layers +nnom_layer_t *Lambda(nnom_status_t (*run)(nnom_layer_t *), // run method, required + nnom_status_t (*build)(nnom_layer_t *), // optional, call default_build() if left null + nnom_status_t (*free)(nnom_layer_t *), // not required if no resources needs to be deleted, can be left null. + void *parameters); // user private parameters for run method, left null if not needed. + +// building methods +nnom_status_t default_build(nnom_layer_t* layer); +nnom_status_t input_build(nnom_layer_t* layer); + +nnom_status_t conv2d_build(nnom_layer_t* layer); +nnom_status_t dw_conv2d_build(nnom_layer_t* layer); +nnom_status_t conv2d_trans_build(nnom_layer_t* layer); +nnom_status_t dense_build(nnom_layer_t* layer); +nnom_status_t rnn_build(nnom_layer_t* layer); + +nnom_status_t upsample_build(nnom_layer_t* layer); +nnom_status_t zero_padding_build(nnom_layer_t* layer); +nnom_status_t cropping_build(nnom_layer_t* layer); + +nnom_status_t maxpool_build(nnom_layer_t* layer); +nnom_status_t avgpool_build(nnom_layer_t* layer); +nnom_status_t sumpool_build(nnom_layer_t* layer); +nnom_status_t global_pool_build(nnom_layer_t* layer); + +nnom_status_t flatten_build(nnom_layer_t* layer); +nnom_status_t concat_build(nnom_layer_t* layer); + +// run +nnom_status_t input_run(nnom_layer_t* layer); +nnom_status_t output_run(nnom_layer_t* layer); +nnom_status_t flatten_run(nnom_layer_t* layer); +nnom_status_t default_run(nnom_layer_t* layer); // simply copy data from input to output + +nnom_status_t dw_conv2d_run(nnom_layer_t* layer); +nnom_status_t conv2d_run(nnom_layer_t* layer); +nnom_status_t conv2d_trans_run(nnom_layer_t* layer); +nnom_status_t dense_run(nnom_layer_t* layer); +nnom_status_t rnn_run(nnom_layer_t* layer); + +nnom_status_t upsample_run(nnom_layer_t* layer); +nnom_status_t zero_padding_run(nnom_layer_t* layer); +nnom_status_t cropping_run(nnom_layer_t* layer); + +nnom_status_t activation_run(nnom_layer_t* layer); +nnom_status_t softmax_run(nnom_layer_t* layer); + +nnom_status_t maxpool_run(nnom_layer_t* layer); +nnom_status_t avgpool_run(nnom_layer_t* layer); +nnom_status_t sumpool_run(nnom_layer_t* layer); + +nnom_status_t concat_run(nnom_layer_t* layer); +nnom_status_t add_run(nnom_layer_t* layer); +nnom_status_t sub_run(nnom_layer_t* layer); +nnom_status_t mult_run(nnom_layer_t* layer); + +// Activation APIs +// Softmax is not considered as activation in NNoM, Softmax is in layer API. +nnom_activation_t* act_relu(void); +nnom_activation_t* act_leaky_relu(float alpha); +nnom_activation_t* act_sigmoid(int32_t dec_bit); +nnom_activation_t* act_tanh(int32_t dec_bit); + +// direct API +nnom_status_t act_tensor_run(nnom_activation_t* act, nnom_tensor_t* tensor); + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_LAYERS_H__ */ diff --git a/components/ai/nnom/inc/nnom_local.h b/components/ai/nnom/inc/nnom_local.h new file mode 100644 index 000000000..35845a564 --- /dev/null +++ b/components/ai/nnom/inc/nnom_local.h @@ -0,0 +1,974 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Notice: + * Code in this file inlcudes derivative works from CMSIS, which is released under alternative license. + * Please check the LICENSE file for detial. + * + * Change Logs: + * Date Author Notes + * 2019-02-05 Jianjia Ma The first version + * 2019-03-19 Jianjia Ma Local C implementation partly from CMSIS-NN + */ + +#ifndef __NNOM_LOCAL_H__ +#define __NNOM_LOCAL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#include "stdint.h" +#include "nnom_port.h" + +#ifdef ARM_NN_TRUNCATE +#define NNOM_TRUNCATE +#endif + +// SSAT implementation with C code +#ifndef __NNOM_SSAT +static inline int __NNOM_SSAT(int32_t value, int32_t bit) { + int32_t min = -(1<<(bit-1)); + int32_t max = (1<<(bit-1)) - 1; + if (value < min) + return min; + else if (value > max) + return max; + else + return value; +} +#endif + +// USAT implementation with C code +#ifndef __NNOM_USAT +static inline int __NNOM_USAT(int32_t value, int32_t bit) { + int32_t max = (1<<(bit-1)) - 1; + if (value < 0) + return 0; + else if (value > max) + return max; + else + return value; +} +#endif + +#define MAX(A, B) ((A) > (B) ? (A) : (B)) +#define MIN(A, B) ((A) < (B) ? (A) : (B)) + + +// Those functions/tables below are partially modifed from CMSIS-NN lib +// https://github.com/ARM-software/CMSIS_5 +// +void local_avepool_q7_HWC(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + const uint16_t output_shift, // output right shift + q7_t *bufferA, // a buffer for local storage, NULL by now + q7_t *Im_out); + +void local_avepool_q7_CHW(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + const uint16_t output_shift, // output right shift + q7_t *bufferA, // a buffer for local storage, NULL by now + q7_t *Im_out); + +// modified from CMSIS-NN test_ref +void local_maxpool_q7_HWC(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t * bufferA, // a buffer for local storage, NULL by now + q7_t * Im_out); + +void local_maxpool_q7_CHW(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t * bufferA, // a buffer for local storage, NULL by now + q7_t * Im_out); + +void local_sumpool_q7_HWC(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t * bufferA, // a buffer for local storage, size = 4*output_size + q7_t * Im_out); + +void local_sumpool_q7_CHW(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t * bufferA, // a buffer for local storage, size = 4*output_size + q7_t * Im_out); + +// customised up sample pooling +void local_up_sampling_q7_HWC(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t *bufferA, // NULL + q7_t *Im_out); + +void local_up_sampling_q7_CHW(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t *bufferA, // NULL + q7_t *Im_out); + +void local_convolve_HWC_q7_nonsquare(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const nnom_qformat_param_t *bias_shift, // bias shifts + const nnom_qformat_param_t *out_shift, // output shift + const nnom_qtype_t q_type, // per channel or per tensor + q7_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +); + +void local_convolve_CHW_q7_nonsquare(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const nnom_qformat_param_t *bias_shift, // bias shifts + const nnom_qformat_param_t *out_shift, // output shift + const nnom_qtype_t q_type, // per channel or per tensor + q7_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +); + +void local_conv_trans_HWC_q7_nonsquare(const int8_t * Im_in, + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q7_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +); + +void local_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t *Im_in,// input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const nnom_qformat_param_t *bias_shift, // bias shifts + const nnom_qformat_param_t *out_shift, // output shift + const nnom_qtype_t q_type, // per channel or per tensor + q7_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +); + +void local_depthwise_separable_conv_CHW_q7_nonsquare(const q7_t *Im_in,// input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const nnom_qformat_param_t *bias_shift, // bias shifts + const nnom_qformat_param_t *out_shift, // output shift + const nnom_qtype_t q_type, // per channel or per tensor + q7_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +); + +void local_zero_padding_HWC_q7(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const uint16_t padding_top, // padding sizes y + const uint16_t padding_bottom, // padding sizes y + const uint16_t padding_left, // padding sizes x + const uint16_t padding_right, // padding sizes x + q7_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y); // output image dimension y + +void local_zero_padding_CHW_q7(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const uint16_t padding_top, // padding sizes y + const uint16_t padding_bottom, // padding sizes y + const uint16_t padding_left, // padding sizes x + const uint16_t padding_right, // padding sizes x + q7_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y); // output image dimension y + +void local_cropping_HWC_q7(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const uint16_t padding_top, // padding sizes y + const uint16_t padding_bottom, // padding sizes y + const uint16_t padding_left, // padding sizes x + const uint16_t padding_right, // padding sizes x + q7_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y); // output image dimension y + +void local_cropping_CHW_q7(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const uint16_t padding_top, // padding sizes y + const uint16_t padding_bottom, // padding sizes y + const uint16_t padding_left, // padding sizes x + const uint16_t padding_right, // padding sizes x + q7_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y); // output image dimension y + +void local_fully_connected_q7_opt(const q7_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q7_t * pOut, // output operand + q15_t * vec_buffer); + + +void local_fully_connected_q7(const q7_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q7_t * pOut, // output operand + q15_t * vec_buffer); + +// matrix dot, +// it takes reorderd weight as input, (see dense layer for detail. this is basiclly a dense opt without bias) +void local_dot_q7_opt(const q7_t *pV, // pointer to vector + const q7_t *pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t out_shift, // amount of right-shift for output + q7_t *pOut); // result buffer + +void local_dot_q7(const q7_t *pV, // pointer to vector + const q7_t *pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t out_shift, // amount of right-shift for output + q7_t *pOut); // output operand) + + + +// softmax +void local_softmax_q7(const q7_t * vec_in, const uint32_t dim_vec, q7_t * p_out); + +// sigmoid +void local_sigmoid_q7(q7_t * data, uint32_t size, int16_t int_width); + +// tanh +void local_tanh_q7(q7_t * data, uint32_t size, int16_t int_width); + +// relu +void local_relu_q7(q7_t * data, uint32_t size); + +// leaky relu +void local_leaky_relu_q7(q7_t *data, q7_t alpha, uint32_t size); + +// alpha in q7 format with dec_bit=7 +// max and threshold has the same Q format with the activation +void local_adv_relu_q7(q7_t *data, q7_t alpha, q7_t max, q7_t threshold, uint32_t size); + +// hard sigmoid, +// y=-1 if x < -2.5 +// y=1 if x > 2.5 +// otherwise y = 0.2 * x + 0.5 (y=0.20315 * x + 0.5) +void local_hard_sigmoid_q7(q7_t *data, uint32_t size, int16_t dec_bit); + +// hard tanh +// y=-1 if x < -1 +// y=1 if x > 1 +// otherwise y = x +void local_hard_tanh_q7(q7_t *data, uint32_t size, int16_t dec_bit); + +// matrix ops +void local_mult_q7(q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, const uint16_t out_shift, uint32_t blockSize); + +// add +void local_add_q7(q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, const uint16_t out_shift, uint32_t blockSize); + +// sub +void local_sub_q7(q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, const uint16_t out_shift, uint32_t blockSize); + +// take multiple blocks (>2) as input +void local_multiple_add_q7( q7_t *p_dst, + const int16_t out_shift, + uint32_t block_size, + uint32_t num_block, + q7_t **p_src); + +void local_multiple_mult_q7( q7_t *p_dst, + const int16_t out_shift, + uint32_t block_size, + uint32_t num_block, + q7_t **p_src); + +void local_multiple_sub_q7( q7_t *p_dst, + const int16_t out_shift, + uint32_t block_size, + uint32_t num_block, + q7_t **p_src); + + +// Below tables credit to CMSIS +// For more info. check CMSIS-NN lib +// https://github.com/ARM-software/CMSIS_5/blob/develop/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c +static const q7_t nnom_sigmoid_table_q7[256] = { + 0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e, + 0x50, 0x52, 0x53, 0x55, 0x57, 0x59, 0x5a, 0x5c, + 0x5e, 0x5f, 0x61, 0x62, 0x63, 0x65, 0x66, 0x67, + 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, + 0x71, 0x72, 0x72, 0x73, 0x74, 0x74, 0x75, 0x76, + 0x76, 0x77, 0x77, 0x78, 0x78, 0x79, 0x79, 0x7a, + 0x7a, 0x7a, 0x7b, 0x7b, 0x7b, 0x7c, 0x7c, 0x7c, + 0x7c, 0x7c, 0x7d, 0x7d, 0x7d, 0x7d, 0x7d, 0x7e, + 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, + 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x04, + 0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05, 0x06, + 0x06, 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, + 0x0a, 0x0a, 0x0b, 0x0c, 0x0c, 0x0d, 0x0e, 0x0e, + 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, + 0x17, 0x19, 0x1a, 0x1b, 0x1d, 0x1e, 0x1f, 0x21, + 0x22, 0x24, 0x26, 0x27, 0x29, 0x2b, 0x2d, 0x2e, + 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e, +}; + + +static const q7_t nnom_tanh_table_q7[256] = { + 0x00, 0x08, 0x10, 0x18, 0x1f, 0x27, 0x2e, 0x35, + 0x3b, 0x41, 0x47, 0x4c, 0x51, 0x56, 0x5a, 0x5e, + 0x61, 0x65, 0x68, 0x6a, 0x6d, 0x6f, 0x71, 0x72, + 0x74, 0x75, 0x76, 0x78, 0x78, 0x79, 0x7a, 0x7b, + 0x7b, 0x7c, 0x7c, 0x7d, 0x7d, 0x7e, 0x7e, 0x7e, + 0x7e, 0x7e, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, + 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x82, + 0x82, 0x82, 0x82, 0x82, 0x83, 0x83, 0x84, 0x84, + 0x85, 0x85, 0x86, 0x87, 0x88, 0x88, 0x8a, 0x8b, + 0x8c, 0x8e, 0x8f, 0x91, 0x93, 0x96, 0x98, 0x9b, + 0x9f, 0xa2, 0xa6, 0xaa, 0xaf, 0xb4, 0xb9, 0xbf, + 0xc5, 0xcb, 0xd2, 0xd9, 0xe1, 0xe8, 0xf0, 0xf8, +}; + + +// ------------ 16bit ops -------------------- + +void local_avepool_q15_HWC(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + const uint16_t output_shift, // output right shift + q7_t *bufferA, // a buffer for local storage, NULL by now + q15_t *Im_out); + +void local_avepool_q15_CHW(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + const uint16_t output_shift, // output right shift + q7_t *bufferA, // a buffer for local storage, NULL by now + q15_t *Im_out); + +void local_maxpool_q15_HWC(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t *bufferA, // a buffer for local storage, NULL by now + q15_t *Im_out); + +void local_maxpool_q15_CHW(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t *bufferA, // a buffer for local storage, NULL by now + q15_t *Im_out); + +void local_sumpool_q15_HWC(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + const uint16_t output_shift, // output right shift + q7_t *bufferA, // a buffer for local storage, size = 4*output_size + q15_t *Im_out); + +void local_sumpool_q15_CHW(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + const uint16_t output_shift, // output right shift + q7_t *bufferA, // a buffer for local storage, size = 4*output_size + q15_t *Im_out); + +void local_up_sampling_q15_HWC(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t *bufferA, // a buffer for local storage, NULL by now + q15_t *Im_out); + + void local_up_sampling_q15_CHW(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t *bufferA, // a buffer for local storage, NULL by now + q15_t *Im_out); + +void local_convolve_HWC_q15_nonsquare(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const nnom_qformat_param_t *bias_shift, // bias shifts + const nnom_qformat_param_t *out_shift, // output shift + const nnom_qtype_t q_type, // per channel or per tensor + q15_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +); +void local_convolve_CHW_q15_nonsquare(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const nnom_qformat_param_t *bias_shift, // bias shifts + const nnom_qformat_param_t *out_shift, // output shift + const nnom_qtype_t q_type, // per channel or per tensor + q15_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +); + +void local_conv_trans_HWC_q15_nonsquare(const int8_t * Im_in, + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q15_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +); + +void local_depthwise_separable_conv_HWC_q15_nonsquare(const q15_t *Im_in,// input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const nnom_qformat_param_t *bias_shift, // bias shifts + const nnom_qformat_param_t *out_shift, // output shift + const nnom_qtype_t q_type, // per channel or per tensor + q15_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +); + +void local_depthwise_separable_conv_CHW_q15_nonsquare(const q15_t *Im_in,// input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const nnom_qformat_param_t *bias_shift, // bias shifts + const nnom_qformat_param_t *out_shift, // output shift + const nnom_qtype_t q_type, // per channel or per tensor + q15_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +); + +void local_zero_padding_HWC_q15(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const uint16_t padding_top, // padding sizes y + const uint16_t padding_bottom, // padding sizes y + const uint16_t padding_left, // padding sizes x + const uint16_t padding_right, // padding sizes x + q15_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y); // output image dimension y + +void local_zero_padding_CHW_q15(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const uint16_t padding_top, // padding sizes y + const uint16_t padding_bottom, // padding sizes y + const uint16_t padding_left, // padding sizes x + const uint16_t padding_right, // padding sizes x + q15_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y); // output image dimension y + +void local_cropping_HWC_q15(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const uint16_t padding_top, // padding sizes y + const uint16_t padding_bottom, // padding sizes y + const uint16_t padding_left, // padding sizes x + const uint16_t padding_right, // padding sizes x + q15_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y); // output image dimension y + +void local_cropping_CHW_q15(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const uint16_t padding_top, // padding sizes y + const uint16_t padding_bottom, // padding sizes y + const uint16_t padding_left, // padding sizes x + const uint16_t padding_right, // padding sizes x + q15_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y); // output image dimension y + + +void local_dot_q15(const q15_t *pV, // pointer to vector + const q15_t *pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t out_shift, // amount of right-shift for output + q15_t *pOut); // output operand) + +void local_dot_q15_opt(const q15_t * pV, + const q15_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t out_shift, + q15_t * pOut); + +// original implementation +// this support none bias, the it will perform like a dot. +// set the `bias=NULL` to work +void local_fully_connected_mat_q7_vec_q15(const q15_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, // bias + q15_t * pOut, // output + q15_t * vec_buffer); // not used but to keep the interface same as the ARM's version + +// work on recorder matrix +// this support none bias, set the bias=NULL to work +void local_fully_connected_mat_q7_vec_q15_opt(const q15_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q15_t * pOut, + q15_t * vec_buffer); + +// matrix operation Q15 +void local_multiple_add_q15( q15_t *p_dst, + const int16_t out_shift, + uint32_t block_size, + uint32_t num_block, + q15_t **p_src); + +void local_multiple_mult_q15( q15_t *p_dst, + const int16_t out_shift, + uint32_t block_size, + uint32_t num_block, + q15_t **p_src); + +void local_multiple_sub_q15( q15_t *p_dst, + const int16_t out_shift, + uint32_t block_size, + uint32_t num_block, + q15_t **p_src); + +void local_mult_q15(q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, const uint16_t out_shift, uint32_t blockSize); + +// add +void local_add_q15(q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, const uint16_t out_shift, uint32_t blockSize); + +// sub +void local_sub_q15(q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, const uint16_t out_shift, uint32_t blockSize); + +// Convert Q7 to Q15 +void local_q7_to_q15_no_shift(const q7_t *src, q15_t *des, uint32_t size); +void local_q7_to_q15(const q7_t *src, q15_t *des, uint32_t size); + +// q15 shift to q7 +void local_q15_to_q7(const q15_t *src, q7_t *des, uint32_t shift, uint32_t size); + +// y = 1 - x +void local_1_minor_z_q15(q15_t *src, q15_t *des, uint16_t dec_bit, uint32_t size); + +void local_softmax_q15(const q15_t * vec_in, const uint16_t dim_vec, q15_t * p_out); +void local_hard_sigmoid_q15(q15_t *data, uint32_t size, int16_t dec_bit); +void local_hard_tanh_q15(q15_t *data, uint32_t size, int16_t dec_bit); +void local_relu_q15(q15_t *data, uint32_t size); +void local_leaky_relu_q15(q15_t *data, q7_t alpha, uint32_t size); +void local_adv_relu_q15(q15_t *data, q7_t negative_slope, q15_t max, q15_t threshold, uint32_t size); +void local_sigmoid_q15(q15_t * data, uint32_t size, uint16_t int_width); +void local_tanh_q15(q15_t * data, uint32_t size, uint16_t int_width); + + +static const q15_t nnom_sigmoid_table_q15[256] = { + 0x4000, 0x4200, 0x43ff, 0x45fc, 0x47f5, 0x49eb, 0x4bdc, 0x4dc8, + 0x4fad, 0x518a, 0x5360, 0x552c, 0x56ef, 0x58a8, 0x5a57, 0x5bfb, + 0x5d93, 0x5f20, 0x60a1, 0x6216, 0x637f, 0x64db, 0x662b, 0x676f, + 0x68a6, 0x69d2, 0x6af1, 0x6c05, 0x6d0d, 0x6e09, 0x6efb, 0x6fe2, + 0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7, + 0x764a, 0x76d6, 0x775b, 0x77d8, 0x784f, 0x78c0, 0x792a, 0x798f, + 0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03, + 0x7c3f, 0x7c78, 0x7cad, 0x7ce0, 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d, + 0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, 0x7e69, 0x7e81, + 0x7e98, 0x7eae, 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17, + 0x7f25, 0x7f32, 0x7f3e, 0x7f4a, 0x7f55, 0x7f5f, 0x7f69, 0x7f72, + 0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa, + 0x7faf, 0x7fb4, 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, 0x7fc8, 0x7fcc, + 0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0, + 0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, 0x7fe9, 0x7fea, 0x7feb, 0x7fed, + 0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, 0x7ff4, 0x7ff4, + 0x000b, 0x000c, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, + 0x0012, 0x0013, 0x0015, 0x0016, 0x0017, 0x0019, 0x001a, 0x001c, + 0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e, + 0x0031, 0x0034, 0x0038, 0x003b, 0x003f, 0x0043, 0x0048, 0x004c, + 0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d, + 0x0085, 0x008e, 0x0097, 0x00a1, 0x00ab, 0x00b6, 0x00c2, 0x00ce, + 0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, 0x013e, 0x0152, + 0x0168, 0x017f, 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a, + 0x024d, 0x0273, 0x029a, 0x02c4, 0x02f1, 0x0320, 0x0353, 0x0388, + 0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8, + 0x0612, 0x0671, 0x06d6, 0x0740, 0x07b1, 0x0828, 0x08a5, 0x092a, + 0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70, + 0x0f42, 0x101e, 0x1105, 0x11f7, 0x12f3, 0x13fb, 0x150f, 0x162e, + 0x175a, 0x1891, 0x19d5, 0x1b25, 0x1c81, 0x1dea, 0x1f5f, 0x20e0, + 0x226d, 0x2405, 0x25a9, 0x2758, 0x2911, 0x2ad4, 0x2ca0, 0x2e76, + 0x3053, 0x3238, 0x3424, 0x3615, 0x380b, 0x3a04, 0x3c01, 0x3e00, +}; + + +static const q15_t nnom_tanh_table_q15[256] = { + 0x0000, 0x07fd, 0x0feb, 0x17b9, 0x1f59, 0x26bf, 0x2ddf, 0x34ae, + 0x3b27, 0x4142, 0x46fd, 0x4c56, 0x514d, 0x55e2, 0x5a1a, 0x5df6, + 0x617c, 0x64b0, 0x6797, 0x6a37, 0x6c95, 0x6eb5, 0x709e, 0x7254, + 0x73dc, 0x753a, 0x7672, 0x7788, 0x787f, 0x795b, 0x7a1e, 0x7acb, + 0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f, + 0x7e49, 0x7e7d, 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, 0x7f30, 0x7f48, + 0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc, + 0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7, + 0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, 0x7ff6, 0x7ff7, + 0x7ff8, 0x7ff9, 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd, + 0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, + 0x8001, 0x8001, 0x8001, 0x8002, 0x8002, 0x8002, 0x8002, 0x8003, + 0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, 0x8006, 0x8007, + 0x8008, 0x8009, 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013, + 0x8016, 0x8019, 0x801c, 0x8020, 0x8024, 0x8029, 0x802f, 0x8035, + 0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f, + 0x80a2, 0x80b8, 0x80d0, 0x80ec, 0x810b, 0x812e, 0x8156, 0x8183, + 0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412, + 0x849b, 0x8535, 0x85e2, 0x86a5, 0x8781, 0x8878, 0x898e, 0x8ac6, + 0x8c24, 0x8dac, 0x8f62, 0x914b, 0x936b, 0x95c9, 0x9869, 0x9b50, + 0x9e84, 0xa20a, 0xa5e6, 0xaa1e, 0xaeb3, 0xb3aa, 0xb903, 0xbebe, + 0xc4d9, 0xcb52, 0xd221, 0xd941, 0xe0a7, 0xe847, 0xf015, 0xf803, +}; + +#ifdef __cplusplus +} +#endif + +#endif /* __NNOM_LOCAL_H__ */ diff --git a/components/ai/nnom/inc/nnom_tensor.h b/components/ai/nnom/inc/nnom_tensor.h new file mode 100644 index 000000000..6853da868 --- /dev/null +++ b/components/ai/nnom/inc/nnom_tensor.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-02-05 Jianjia Ma The first version + * 2019-02-10 Jianjia Ma Compiler supports dense net connection + */ + +#ifndef __NNOM_TENSOR_H__ +#define __NNOM_TENSOR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nnom.h" + + +void delete_tensor(nnom_tensor_t* t); +nnom_tensor_t* new_tensor(nnom_qtype_t type, uint32_t num_dim, uint32_t num_channel); +// set tensor by value +// for tensor with quantized type NNOM_QTYPE_PER_TENSOR +nnom_tensor_t* tensor_set_attr_v(nnom_tensor_t* t, + nnom_qformat_param_t dec_bit, nnom_qformat_param_t offset, nnom_shape_data_t* dim, uint32_t num_dim, uint8_t bitwidth); +nnom_tensor_t* tensor_set_attr(nnom_tensor_t* t, + nnom_qformat_param_t*dec_bit, nnom_qformat_param_t *offset, nnom_shape_data_t* dim, uint32_t num_dim, uint8_t bitwidth); +nnom_tensor_t* tensor_cpy_attr(nnom_tensor_t* des, nnom_tensor_t* src); +size_t tensor_get_num_channel(nnom_tensor_t* t); +size_t tensor_size(nnom_tensor_t* t); +size_t tensor_size_byte(nnom_tensor_t* t); + +// only support 3d tensor +// change format from CHW to HWC +// the shape of the data, input data, output data +void tensor_hwc2chw_q7(nnom_tensor_t* des, nnom_tensor_t* src); + +// change format from CHW to HWC +// the shape of the data, input data, output data +void tensor_chw2hwc_q7(nnom_tensor_t* des, nnom_tensor_t* src); + +// deprecated. +void hwc2chw_q7(nnom_3d_shape_t shape, q7_t* p_in, q7_t* p_out); +void chw2hwc_q7(nnom_3d_shape_t shape, q7_t* p_in, q7_t* p_out); + +#ifdef __cplusplus +} +#endif + +#endif /*__NNOM_TENSOR_H__ */ diff --git a/components/ai/nnom/inc/nnom_utils.h b/components/ai/nnom/inc/nnom_utils.h new file mode 100644 index 000000000..88c5067d3 --- /dev/null +++ b/components/ai/nnom/inc/nnom_utils.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-02-05 Jianjia Ma The first version + */ + +#ifndef __NNOM_UTILS_H__ +#define __NNOM_UTILS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +#include +#include +#include + +#include "nnom.h" + +typedef struct _nnom_predict_t +{ + uint16_t *confusion_mat; // confusiong matrix + uint32_t *top_k; // which stored the num of prediction in rank_k, example: Top-2 = top_k[0]+top_k[1] + nnom_model_t *model; // the model to run + int8_t *buf_prediction; // the pointer to the output of softmax layer(normally the end of classifier). + + // setting + uint32_t label_num; // number of types in classification + uint32_t top_k_size; // number of k that wants to know. + + // running + uint32_t predict_count; // how many prediction is done + + //timing + uint32_t t_run_total; // total running time + uint32_t t_predict_start; // when it is initial + uint32_t t_predict_total; // total time of the whole test +} nnom_predict_t; + +// create a prediction +// input model, the buf pointer to the softwmax output (Temporary, this can be extract from model) +// the size of softmax output (the num of lable) +// the top k that wants to record. +nnom_predict_t *prediction_create(nnom_model_t *m, int8_t *buf_prediction, size_t label_num, size_t top_k_size); // currently int8_t + +// after a new data is set in input +// feed data to prediction +// input the current label, (range from 0 to total number of label -1) +// (the current input data should be set by user manully to the input buffer of the model.) +// return NN_ARGUMENT_ERROR if parameter error +nnom_status_t prediction_run(nnom_predict_t *pre, uint32_t true_label, uint32_t* predict_label, float* prob); + +// to mark prediction finished +void prediction_end(nnom_predict_t *pre); + +// free all resources +void prediction_delete(nnom_predict_t *pre); + +// print matrix +void prediction_matrix(nnom_predict_t *pre); + +// print top-k +void prediction_top_k(nnom_predict_t *pre); + +// this function is to print sumarry +void prediction_summary(nnom_predict_t *pre); + +// ------------------------------- + +// stand alone prediction API +// this api test one set of data, return the prediction +// return the predicted label +// return NN_ARGUMENT_ERROR if parameter error +nnom_status_t nnom_predict(nnom_model_t *m, uint32_t *label, float *prob); + +void model_stat(nnom_model_t *m); + +void model_io_format(nnom_model_t *m); + +#ifdef __cplusplus +} +#endif + +#endif /*__NNOM_UTILS_H__ */ diff --git a/components/ai/nnom/port/nnom_port.h b/components/ai/nnom/port/nnom_port.h new file mode 100644 index 000000000..d7822b7e0 --- /dev/null +++ b/components/ai/nnom/port/nnom_port.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-02-05 Jianjia Ma The first version + * 2021-09-08 derekduke add tos support + */ + +#ifndef __NNOM_PORT_H__ +#define __NNOM_PORT_H__ + +#include +#include + +/* use static memory */ +#define NNOM_USING_STATIC_MEMORY // enable to use built in memory allocation on a large static memory block + // must set buf using "nnom_set_static_buf()" before creating a model. + +/* dynamic memory interfaces */ +/* when libc is not available, you shall implement the below memory interfaces (libc equivalents). */ +#ifndef NNOM_USING_STATIC_MEMORY + //#define nnom_malloc(n) malloc(n) + //#define nnom_free(p) free(p) + #define nnom_malloc(n) tos_mmheap_alloc(n) + #define nnom_free(n) tos_mmheap_free(n) +#endif + +/* memory interface */ +/* when libc is not available, you shall implement your equivalent functions here */ +#define nnom_memset(p,v,s) memset(p,v,s) +#define nnom_memcpy(dst,src,len) memcpy(dst,src,len) + +/* runtime & debug */ +#define nnom_us_get() 0 // return a microsecond timestamp +#define nnom_ms_get() 0 // return a millisecond timestamp +#define NNOM_LOG(...) printf(__VA_ARGS__) + +/* NNoM configuration */ +#define NNOM_BLOCK_NUM (16) // maximum number of memory blocks, increase it when log request. +#define DENSE_WEIGHT_OPT (1) // if used fully connected layer optimized weights. + +//#define NNOM_TRUNCATE // disable: backend ops use round to the nearest int (default). enable: floor + +/* Backend format configuration */ +//#define NNOM_USING_CHW // uncomment if using CHW format. otherwise using default HWC format. + // Notes, CHW is incompatible with CMSIS-NN. + // CHW must be used when using hardware accelerator such as KPU in K210 chip + +/* Backend selection */ +//#define NNOM_USING_CMSIS_NN // uncomment if use CMSIS-NN for optimation + + +#endif + + + diff --git a/components/ai/nnom/src/backends/nnom_local.c b/components/ai/nnom/src/backends/nnom_local.c new file mode 100644 index 000000000..5c514b21b --- /dev/null +++ b/components/ai/nnom/src/backends/nnom_local.c @@ -0,0 +1,1689 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Notice: + * Code in this file inlcudes derivative works from CMSIS + * Please check the LICENSE file for detial. + * + * Change Logs: + * Date Author Notes + * 2019-02-05 Jianjia Ma The first version + * 2019-03-19 Jianjia Ma Local C implementation partly from CMSIS-NN + * 2019-06-19 Jianjia Ma Implement CHW functions + */ + +#include "nnom.h" +#include "nnom_local.h" + +// modified from CMSIS-NN test_ref +void local_avepool_q7_HWC(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + const uint16_t output_shift, // output right shift + q7_t *bufferA, // a buffer for local storage, NULL by now + q7_t *Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out_y; i_y++) + { + for (i_x = 0; i_x < dim_im_out_x; i_x++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride_y - padding_y; k_y < i_y * stride_y - padding_y + dim_kernel_y; k_y++) + { + for (k_x = i_x * stride_x - padding_x; k_x < i_x * stride_x - padding_x + dim_kernel_x; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in_y && k_x < dim_im_in_x) + { + sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in_x)]; + count++; + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out_x)] = sum / (count>>output_shift); + } + } + } +} + +void local_avepool_q7_CHW(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + const uint16_t output_shift, // output right shift + q7_t *bufferA, // a buffer for local storage, NULL by now + q7_t *Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + int32_t ch_offset; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + ch_offset = i_ch_in*dim_im_in_x*dim_im_in_y; + for (i_y = 0; i_y < dim_im_out_y; i_y++) + { + for (i_x = 0; i_x < dim_im_out_x; i_x++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride_y - padding_y; k_y < i_y * stride_y - padding_y + dim_kernel_y; k_y++) + { + for (k_x = i_x * stride_x - padding_x; k_x < i_x * stride_x - padding_x + dim_kernel_x; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in_y && k_x < dim_im_in_x) + { + sum += Im_in[ch_offset + (k_x + k_y * dim_im_in_x)]; + count++; + } + } + } + Im_out[i_ch_in*dim_im_out_x*dim_im_out_y + (i_x + i_y * dim_im_out_x)] = sum / (count>>output_shift); + } + } + } +} + +// modified from CMSIS-NN test_ref +void local_maxpool_q7_HWC(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t *bufferA, // a buffer for local storage, NULL by now + q7_t *Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out_y; i_y++) + { + for (i_x = 0; i_x < dim_im_out_x; i_x++) + { + int max = -129; + for (k_y = i_y * stride_y - padding_y; k_y < i_y * stride_y - padding_y + dim_kernel_y; k_y++) + { + for (k_x = i_x * stride_x - padding_x; k_x < i_x * stride_x - padding_x + dim_kernel_x; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in_y && k_x < dim_im_in_x) + { + if (Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in_x)] > max) + { + max = Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in_x)]; + } + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out_x)] = max; + } + } + } +} + +void local_maxpool_q7_CHW(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t *bufferA, // a buffer for local storage, NULL by now + q7_t *Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + int32_t ch_offset; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + ch_offset = i_ch_in * dim_im_out_x * dim_im_out_y; + for (i_y = 0; i_y < dim_im_out_y; i_y++) + { + for (i_x = 0; i_x < dim_im_out_x; i_x++) + { + int max = -129; + for (k_y = i_y * stride_y - padding_y; k_y < i_y * stride_y - padding_y + dim_kernel_y; k_y++) + { + for (k_x = i_x * stride_x - padding_x; k_x < i_x * stride_x - padding_x + dim_kernel_x; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in_y && k_x < dim_im_in_x) + { + if (Im_in[i_ch_in * dim_im_in_x * dim_im_in_y + (k_x + k_y * dim_im_in_x)] > max) + { + max = Im_in[i_ch_in * dim_im_in_x * dim_im_in_y + (k_x + k_y * dim_im_in_x)]; + } + } + } + } + Im_out[ch_offset+(i_x + i_y * dim_im_out_x)] = max; + } + } + } +} + +// temporary for the thesis +// shift according to the maximum +void local_sumpool_q7_HWC(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t *bufferA, // a buffer for local storage, size = 4*output_size + q7_t *Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + int32_t *buf = (int32_t *)bufferA; + // stage2 + // int32_t max_abs = 0; + // int32_t output_shift; + // size_t output_size = dim_im_out_x * dim_im_out_x * ch_im_in; + + // save in 32bit + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out_y; i_y++) + { + for (i_x = 0; i_x < dim_im_out_x; i_x++) + { + int sum = 0; + for (k_y = i_y * stride_y - padding_y; k_y < i_y * stride_y - padding_y + dim_kernel_y; k_y++) + { + for (k_x = i_x * stride_x - padding_x; k_x < i_x * stride_x - padding_x + dim_kernel_x; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in_y && k_x < dim_im_in_x) + { + sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in_x)]; + } + } + } + // 32bit + buf[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out_x)] = sum; + } + } + } + + // // find max amount results + // for (int i = 0; i < output_size; i++) + // { + // int32_t val = buf[i]; + // if (val < 0) + // val = -val; + // if (val > max_abs) + // max_abs = val; + // } + // // find best shift to cover the max + // for (output_shift = 0;; output_shift++) + // { + // if (127 * (1 + output_shift) >= max_abs) + // break; + // } + + // // shift the results + // for (int i = 0; i < output_size; i++) + // { + // Im_out[i] = buf[i] >> output_shift; + // } + //return output_shift; +} + +// temporary for the thesis +// shift according to the maximum +void local_sumpool_q7_CHW(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t *bufferA, // a buffer for local storage, size = 4*output_size + q7_t *Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + int32_t *buf = (int32_t *)bufferA; + int32_t i_ch_offset, o_ch_offset; + // stage2 + // int32_t max_abs = 0; + // int32_t output_shift; + // size_t output_size = dim_im_out_x * dim_im_out_x * ch_im_in; + + // save in 32bit + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + i_ch_offset = i_ch_in*dim_im_in_x*dim_im_in_y; + o_ch_offset = i_ch_in*dim_im_out_x*dim_im_out_y; + + for (i_y = 0; i_y < dim_im_out_y; i_y++) + { + for (i_x = 0; i_x < dim_im_out_x; i_x++) + { + int sum = 0; + for (k_y = i_y * stride_y - padding_y; k_y < i_y * stride_y - padding_y + dim_kernel_y; k_y++) + { + for (k_x = i_x * stride_x - padding_x; k_x < i_x * stride_x - padding_x + dim_kernel_x; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in_y && k_x < dim_im_in_x) + { + sum += Im_in[i_ch_offset + (k_x + k_y * dim_im_in_x)]; + } + } + } + // 32bit + buf[o_ch_offset + (i_x + i_y * dim_im_out_x)] = sum; + } + } + } + + // // find max amount results + // for (int i = 0; i < output_size; i++) + // { + // int32_t val = buf[i]; + // if (val < 0) + // val = -val; + // if (val > max_abs) + // max_abs = val; + // } + // // find best shift to cover the max + // for (output_shift = 0;; output_shift++) + // { + // if (127 * (1 + output_shift) >= max_abs) + // break; + // } + + // // shift the results + // for (int i = 0; i < output_size; i++) + // { + // Im_out[i] = buf[i] >> output_shift; + // } + //return output_shift; +} + +// customised up sample pooling +void local_up_sampling_q7_HWC(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t *bufferA, // a buffer for local storage, NULL by now + q7_t *Im_out) +{ + int16_t i_x, i_y; + + // for loop for each pixel in input image. + for (i_y = 0; i_y < dim_im_in_y; i_y++) + { + for (i_x = 0; i_x < dim_im_in_x; i_x++) + { + // copy all the channels together. + const q7_t *p_in = Im_in + (i_y * dim_im_in_x + i_x ) * ch_im_in; + q7_t *pout = Im_out + (i_y * dim_im_in_x * dim_kernel_x * dim_kernel_y + i_x * dim_kernel_y) * ch_im_in; + + // copy along x axis + for(int i = 0; i> out_shift[shift_idx]), 8); + } + } + } +} + +void local_convolve_CHW_q7_nonsquare(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const nnom_qformat_param_t *bias_shift, // bias shifts + const nnom_qformat_param_t *out_shift, // output shift + const nnom_qtype_t q_type, // per channel or per tensor + q7_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +) +{ + int i, j, k, l, m, n; + long conv_out; + int in_row, in_col; + int shift_idx, shift_steps; + if(q_type == NNOM_QTYPE_PER_AXIS) + shift_steps = 1; + else + shift_steps = 0; + + for(i = 0, shift_idx = 0; i < ch_im_out; i++, shift_idx += shift_steps) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + if(bias) + conv_out = ((q31_t)(bias[i]) << bias_shift[shift_idx]) + NNOM_ROUND(out_shift[shift_idx]); + else + conv_out = (q31_t) NNOM_ROUND(out_shift[shift_idx]); + + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m * dilation_y - padding_y; + in_col = stride_x * k + n * dilation_x - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) + l * dim_im_in_x * dim_im_in_y] * + wt[(m * dim_kernel_x + n) * ch_im_in * ch_im_out + l * ch_im_out + i]; + } + } + } + } + Im_out[i * dim_im_out_x * dim_im_out_y + (j * dim_im_out_x + k)] = (q7_t)__NNOM_SSAT((conv_out >> out_shift[shift_idx]), 8); + } + } + } +} + +#define FALSE 0 +#define TRUE 1 + +static int alg_deconv2d_calculate_position( + int pos, + int stride, + int padding, + int dim_kernel, + int dim_in, + int* in_start, + int* kernel_start, + int* kernel_end) +{ + int is_zero = FALSE; + int of, adj; + is_zero = FALSE; + *in_start = pos/stride; + of = pos%stride; + *kernel_start = padding - of; + if(*kernel_start >= 0) { + adj = MIN(*in_start, *kernel_start/stride); + *kernel_start -= adj*stride; + *in_start -= adj; + } else { + adj = -*kernel_start + dim_kernel; + if(adj<=stride) { + is_zero = TRUE; + } else { + adj = MIN(dim_in-1-*in_start, adj/stride); + *kernel_start += adj*stride; + *in_start += adj; + } + } + of = dim_kernel - 1 - *kernel_start; + adj = MIN(dim_in-1-*in_start, of/stride); + *kernel_end = *kernel_start + adj*stride; + + return is_zero; +} + +void local_conv_trans_HWC_q7_nonsquare(const int8_t * Im_in, + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q7_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +) +// { +// int ox, oy, oc, ky, kx, kc, ix, iy; +// int conv_out; +// int in_pix_loc, wt_loc; + +// (void)dilation_y; +// (void)dilation_x; + +// // padding and stride are applied to output +// for (oc = 0; oc < ch_im_out; oc++) +// { +// for (oy = 0; oy < dim_im_out_y; oy++) +// { +// for (ox = 0; ox < dim_im_out_x; ox++) +// { +// conv_out = ((q31_t)(bias[oc]) << bias_shift) + NNOM_ROUND(out_shift); + +// for (ky = 0; ky < dim_kernel_y; ky++) +// { +// for (kx = 0; kx < dim_kernel_x; kx++) +// { +// // input y, input x location +// iy = oy / stride_y + ky - padding_y; +// ix = ox / stride_x + kx - padding_x; + +// if(ix >= 0 && iy >= 0 && ix < dim_im_in_y && iy< dim_im_in_y) +// { +// in_pix_loc = (iy * dim_im_in_x + ix) * ch_im_in; +// wt_loc = oc * ch_im_in * dim_kernel_y * dim_kernel_x + (ky * dim_kernel_x + kx) * ch_im_in; + +// for (kc = 0; kc < ch_im_in; kc++) +// { +// conv_out += Im_in[in_pix_loc + kc] * wt[wt_loc + kc]; +// } +// } +// } +// } + +// Im_out[oc + (oy * dim_im_out_x + ox) * ch_im_out] = (q7_t) __NNOM_SSAT((conv_out >> out_shift), 8); +// } +// } +// } +// } + +{ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + int kernel_start_x,kernel_end_x; + int kernel_start_y,kernel_end_y; + int in_row_start, in_col_start; + int is_zero; + + for (i = 0; i < ch_im_out; i++) { + for (j = 0; j < dim_im_out_y; j++) { + is_zero = alg_deconv2d_calculate_position(j, stride_y, padding_y, dim_kernel_y, + dim_im_in_y, &in_row_start, &kernel_start_y, &kernel_end_y); + + if(is_zero) { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NNOM_ROUND(out_shift); + conv_out = (q7_t) __NNOM_SSAT((conv_out >> out_shift), 8); + for (k = 0; k < dim_im_out_x; k++) { + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) conv_out; + } + continue; + } + + for (k = 0; k < dim_im_out_x; k++) { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NNOM_ROUND(out_shift); + + is_zero = alg_deconv2d_calculate_position(k, stride_x, padding_x, dim_kernel_x, + dim_im_in_x, &in_col_start, &kernel_start_x, &kernel_end_x); + + if(is_zero) { + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = conv_out; + continue; + } + + for (m = kernel_start_y, in_row = in_row_start; m <= kernel_end_y; m+=stride_y, in_row++) { + for (n = kernel_start_x, in_col = in_col_start; n <= kernel_end_x; n+=stride_x, in_col++) { + if ((in_row >= 0) && (in_col >= 0) && + (in_row < dim_im_in_y) && (in_col < dim_im_in_x)) { + for (l = 0; l < ch_im_in; l++) { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + l]; + } + } + } + } + + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __NNOM_SSAT((conv_out >> out_shift), 8); + } + } + } +} + +void local_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t *Im_in,// input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const nnom_qformat_param_t *bias_shift, // bias shifts + const nnom_qformat_param_t *out_shift, // output shift + const nnom_qtype_t q_type, // per channel or per tensor + q7_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +) +{ + int i_out_y, i_out_x, i_ch_out, i_ch_in, i_ch_mult; + int i_ker_y, i_ker_x; + int i_out = 0; + int shift_idx, shift_steps; + int ch_mult = ch_im_out / ch_im_in; + q31_t conv_out; + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + const int32_t base_idx_y = stride_y * i_out_y - padding_y; + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + const int32_t base_idx_x = stride_x * i_out_x - padding_x; + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for(i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + { + i_ch_out = i_ch_mult + i_ch_in * ch_mult; + int32_t ker_y_start = MAX(0, -(base_idx_y-(dilation_y-1))/dilation_y); + int32_t ker_x_start = MAX(0, -(base_idx_x-(dilation_x-1))/dilation_x); + int32_t ker_y_end = MIN(dim_kernel_y, (dim_im_in_y - base_idx_y + (dilation_y-1))/dilation_y); + int32_t ker_x_end = MIN(dim_kernel_x, (dim_im_in_x - base_idx_x + (dilation_x-1))/dilation_x); + + shift_idx = q_type == NNOM_QTYPE_PER_AXIS ? i_ch_out : 0; + if (bias) + conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift[shift_idx]) + NNOM_ROUND(out_shift[shift_idx]); + else + conv_out = (q31_t)NNOM_ROUND(out_shift[shift_idx]); + + for (i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + i_ker_y * dilation_y; + for (i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + i_ker_x * dilation_x; + int32_t in_pix_loc = (idx_y * dim_im_in_x + idx_x) * ch_im_in + i_ch_in; + int32_t wt_loc = (i_ker_y * dim_kernel_x + i_ker_x) * (ch_im_in * ch_mult) + i_ch_out; + conv_out += Im_in[in_pix_loc] * wt[wt_loc]; + } + } + Im_out[i_out++] = (q7_t)__NNOM_SSAT((conv_out >> out_shift[shift_idx]), 8); + } + } + } + } +} + +void local_depthwise_separable_conv_CHW_q7_nonsquare(const q7_t *Im_in,// input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const nnom_qformat_param_t *bias_shift, // bias shifts + const nnom_qformat_param_t *out_shift, // output shift + const nnom_qtype_t q_type, // per channel or per tensor + q7_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +) +{ + int i_out_y, i_out_x, i_ch_out, i_ch_in, i_ch_mult; + int i_ker_y, i_ker_x; + int i_out = 0; + int shift_idx, shift_steps; + int ch_mult = ch_im_out / ch_im_in; + q31_t conv_out; + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + const int32_t base_idx_y = stride_y * i_out_y - padding_y; + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + const int32_t base_idx_x = stride_x * i_out_x - padding_x; + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + { + i_ch_out = i_ch_mult + i_ch_in * ch_mult; + int32_t ker_y_start = MAX(0, -(base_idx_y-(dilation_y-1))/dilation_y); + int32_t ker_x_start = MAX(0, -(base_idx_x-(dilation_x-1))/dilation_x); + int32_t ker_y_end = MIN(dim_kernel_y, (dim_im_in_y - base_idx_y + (dilation_y-1))/dilation_y); + int32_t ker_x_end = MIN(dim_kernel_x, (dim_im_in_x - base_idx_x + (dilation_x-1))/dilation_x); + + shift_idx = q_type == NNOM_QTYPE_PER_AXIS ? i_ch_out : 0; + if (bias) + conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift[shift_idx]) + NNOM_ROUND(out_shift[shift_idx]); + else + conv_out = (q31_t)NNOM_ROUND(out_shift[shift_idx]); + + for (i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + i_ker_y * dilation_y; + for (i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + i_ker_x * dilation_x; + int32_t in_pix_loc = (idx_y * dim_im_in_x + idx_x) + i_ch_in * dim_im_in_x * dim_im_in_y; + int32_t wt_loc = (i_ker_y * dim_kernel_x + i_ker_x) * ch_im_out + i_ch_out; + conv_out += Im_in[in_pix_loc] * wt[wt_loc]; + } + } + Im_out[i_ch_out * dim_im_out_x * dim_im_out_y + (i_out_y * dim_im_out_x + i_out_x)] = (q7_t)__NNOM_SSAT((conv_out >> out_shift[shift_idx]), 8); + } + } + } + } + +} + + +void local_zero_padding_HWC_q7(const q7_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const uint16_t padding_top, // padding sizes y + const uint16_t padding_bottom, // padding sizes y + const uint16_t padding_left, // padding sizes x + const uint16_t padding_right, // padding sizes x + q7_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y) // output image dimension y +{ + int i, size; + q7_t * p_out = Im_out; + + // top rows + size = dim_im_out_x*ch_im_in*padding_top; + nnom_memset(p_out, 0, size); + p_out += size; + + // middle + for(i=0; i> 2; + const q7_t *pB = pM; + const q7_t *pA; + q7_t *pO = pOut; + + while (rowCnt) + { + pA = pV; + q31_t sum = (q31_t) NNOM_ROUND(out_shift); + q31_t sum2 = (q31_t) NNOM_ROUND(out_shift); + q31_t sum3 = (q31_t) NNOM_ROUND(out_shift); + q31_t sum4 = (q31_t) NNOM_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + while (colCnt) + { + q7_t inA1 = *pA++; + q7_t inA3 = *pA++; + q7_t inA2 = *pA++; + q7_t inA4 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum += inA3 * inB1 + inA4 * inB2; + sum2 += inA3 * inB3 + inA4 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA3 * inB1 + inA4 * inB2; + sum4 += inA3 * inB3 + inA4 * inB4; + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q7_t)__NNOM_SSAT((sum >> out_shift), 8); + *pO++ = (q7_t)__NNOM_SSAT((sum2 >> out_shift), 8); + *pO++ = (q7_t)__NNOM_SSAT((sum3 >> out_shift), 8); + *pO++ = (q7_t)__NNOM_SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = (q31_t) NNOM_ROUND (out_shift); + pA = pV; + for (int j = 0; j < dim_vec; j++) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q7_t)__NNOM_SSAT((ip_out >> out_shift), 8); + + rowCnt--; + } +} + +void local_dot_q7(const q7_t *pV, // pointer to vector + const q7_t *pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t out_shift, // amount of right-shift for output + q7_t *pOut) // output operand) +{ + for (int i = 0; i < num_of_rows; i++) + { + int ip_out = (q31_t) NNOM_ROUND(out_shift); + for (int j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q7_t)__NNOM_SSAT((ip_out >> out_shift), 8); + } +} + +void local_fully_connected_q7_opt(const q7_t *pV, // pointer to vector + const q7_t *pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t *bias, q7_t *pOut, // output operand + q15_t *vec_buffer) +{ + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q7_t *pA; + q7_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + pA = pV; + q31_t sum; + q31_t sum2; + q31_t sum3; + q31_t sum4; + uint16_t colCnt = dim_vec >> 2; + + if(bias) + { + sum = ((q31_t)(*pBias++) << bias_shift) + NNOM_ROUND(out_shift); + sum2 = ((q31_t)(*pBias++) << bias_shift) + NNOM_ROUND(out_shift); + sum3 = ((q31_t)(*pBias++) << bias_shift) + NNOM_ROUND(out_shift); + sum4 = ((q31_t)(*pBias++) << bias_shift) + NNOM_ROUND(out_shift); + } + else + { + sum = (q31_t) NNOM_ROUND(out_shift); + sum2 = (q31_t) NNOM_ROUND(out_shift); + sum3 = (q31_t) NNOM_ROUND(out_shift); + sum4 = (q31_t) NNOM_ROUND(out_shift); + } + + while (colCnt) + { + q7_t inA1 = *pA++; + q7_t inA3 = *pA++; + q7_t inA2 = *pA++; + q7_t inA4 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum += inA3 * inB1 + inA4 * inB2; + sum2 += inA3 * inB3 + inA4 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA3 * inB1 + inA4 * inB2; + sum4 += inA3 * inB3 + inA4 * inB4; + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q7_t)__NNOM_SSAT((sum >> out_shift), 8); + *pO++ = (q7_t)__NNOM_SSAT((sum2 >> out_shift), 8); + *pO++ = (q7_t)__NNOM_SSAT((sum3 >> out_shift), 8); + *pO++ = (q7_t)__NNOM_SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out; + if(bias) + ip_out=((q31_t)(*bias++) << bias_shift) + NNOM_ROUND(out_shift); + else + ip_out=(q31_t)NNOM_ROUND(out_shift); + + pA = pV; + for (int j = 0; j < dim_vec; j++) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q7_t)__NNOM_SSAT((ip_out >> out_shift), 8); + + rowCnt--; + } +} + +void local_fully_connected_q7(const q7_t *pV, // pointer to vector + const q7_t *pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t *bias, q7_t *pOut, // output operand + q15_t *vec_buffer) +{ + if(bias) + { + for (int i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(*bias++) << bias_shift) + NNOM_ROUND(out_shift); + for (int j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q7_t)__NNOM_SSAT((ip_out >> out_shift), 8); + } + } + else + { + for (int i = 0; i < num_of_rows; i++) + { + int ip_out = (q31_t)NNOM_ROUND(out_shift); + for (int j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q7_t)__NNOM_SSAT((ip_out >> out_shift), 8); + } + } +} + + +void local_softmax_q7(const q7_t *vec_in, const uint32_t dim_vec, q7_t *p_out) +{ + q31_t sum; + int32_t i; + uint8_t shift; + q15_t base; + base = -257; + + /* We first search for the maximum */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } + + /* + * So the base is set to max-8, meaning + * that we ignore really small values. + * anyway, they will be 0 after shrinking to q7_t. + */ + base = base - 8; + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + shift = (uint8_t)__NNOM_USAT(vec_in[i] - base, 5); + sum += 0x1 << shift; + } + } + + /* This is effectively (0x1 << 20) / sum */ + int output_base = 0x100000 / sum; + + /* + * Final confidence will be output_base >> ( 13 - (vec_in[i] - base) ) + * so 128 (0x1<<7) -> 100% confidence when sum = 0x1 << 8, output_base = 0x1 << 12 + * and vec_in[i]-base = 8 + */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + /* Here minimum value of 13+base-vec_in[i] will be 5 */ + shift = (uint8_t)__NNOM_USAT(13 + base - vec_in[i], 5); + p_out[i] = (q7_t)__NNOM_SSAT((output_base >> shift), 8); + } + else + { + p_out[i] = 0; + } + } +} + + +// hard sigmoid, +// y=-1 if x < -2.5 +// y=1 if x > 2.5 +// otherwise y = 0.2 * x + 0.5 (y=0.20315 * x + 0.5) +void local_hard_sigmoid_q7(q7_t *data, uint32_t size, int16_t dec_bit) +{ + int16_t limit = 2.5f * (1 << dec_bit)-1; + int16_t offset = 64; // 0.5 * 128 + int16_t mult = 26; // 0.2 * 128 + + // int bit >= 0 + for(int i=0; i= limit) + data[i] = 127; + else + { + data[i] = ((int16_t)(data[i] * mult) >> dec_bit) + offset; + } + } + } + +// hard tanh +// y=-1 if x < -1 +// y=1 if x > 1 +// otherwise y = x +void local_hard_tanh_q7(q7_t *data, uint32_t size, int16_t dec_bit) +{ + int16_t int_bit = 7 - dec_bit; + int16_t limit = 1 << dec_bit; + + if(dec_bit == 7) + return; + + // int bit < 0 + if(int_bit < 0) + for(int i=0; i= limit) + data[i] = 127; + else + { + data[i] = data[i] >> (-int_bit); + } + } + else + // int bit >= 0 + for(int i=0; i= limit) + data[i] = 127; + else + { + data[i] = data[i] << int_bit; + } + } +} + +void local_sigmoid_q7(q7_t *data, uint32_t size, int16_t int_width) +{ + uint32_t i = size; + q7_t *pIn = data; + q7_t *pOut = data; + q7_t in; + q7_t out; + uint16_t shift_size = 3 - int_width; + // saturation if int bit too large + if(int_width > 3) + { + while (i) + { + if(*pIn++ > 0) + *pOut++ = 127; + else + *pOut++ = 0; + i--; + } + } + // otherwise search table + else + { + while (i) + { + in = *pIn++; + out = nnom_sigmoid_table_q7[(uint8_t)(in >> shift_size)]; + *pOut++ = out; + i--; + } + } +} + +void local_tanh_q7(q7_t *data, uint32_t size, int16_t int_width) +{ + uint32_t i = size; + q7_t *pIn = data; + q7_t *pOut = data; + q7_t in; + q7_t out; + uint16_t shift_size = 3 - int_width; + + // saturation if int bit too large + if(int_width > 3) + { + while (i) + { + in = *pIn++; + if(in > 0) + *pOut++ = 127; + else if ( in == 0) + *pOut++ = 0; + else + *pOut++ = -128; + i--; + } + } + // otherwise search table + else + { + while (i) + { + in = *pIn++; + out = nnom_tanh_table_q7[(uint8_t)(in >> shift_size)]; + *pOut++ = out; + i--; + } + } +} + +void local_relu_q7(q7_t *data, uint32_t size) +{ + uint32_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } +} + +// alpha in q7 format with dec_bit=7 +void local_leaky_relu_q7(q7_t *data, q7_t alpha, uint32_t size) +{ + uint32_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + { + data[i] = data[i] * alpha / 128; + } + } +} + +// alpha in q7 format with dec_bit=7 +// max and threshold has the same Q format with the activation +void local_adv_relu_q7(q7_t *data, q7_t negative_slope, q7_t max, q7_t threshold, uint32_t size) +{ + uint32_t i; + for (i = 0; i < size; i++) + { + // `f(x) = max_value` for `x >= max_value`, + // `f(x) = x` for `threshold <= x < max_value`, + // `f(x) = alpha * (x - threshold)` otherwise. + + if(data[i] > max) + data[i] = max; + if (data[i] < threshold) + data[i] = (data[i] - threshold) * negative_slope / 128; + } +} + +// matrix ops +void local_mult_q7(q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + const uint16_t out_shift, + uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + q31_t product = pSrcA[i] * pSrcB[i]; + pDst[i] = (q7_t) __NNOM_SSAT(((product + NNOM_ROUND(out_shift)) >> out_shift), 8); + } +} + +void local_add_q7(q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + const uint16_t out_shift, + uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + q31_t sum = pSrcA[i] + pSrcB[i]; + pDst[i] = (q7_t) __NNOM_SSAT(((sum + NNOM_ROUND(out_shift)) >> out_shift), 8); + } +} + +void local_sub_q7(q7_t *pSrcA, + q7_t *pSrcB, + q7_t *pDst, + const uint16_t out_shift, + uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + q31_t sub = pSrcA[i] - pSrcB[i]; + pDst[i] = (q7_t) __NNOM_SSAT(((sub + NNOM_ROUND(out_shift)) >> out_shift), 8); + } +} + + + +void local_multiple_add_q7( q7_t *p_dst, + const int16_t out_shift, + uint32_t block_size, + uint32_t num_block, + q7_t **p_src) +{ + uint32_t i, blk; + q31_t sum; + + for (i = 0; i < block_size; i++) + { + sum = 0; + for(blk=0; blk < num_block; blk++) + sum += p_src[blk][i]; + p_dst[i] = (q7_t) __NNOM_SSAT(((sum + NNOM_ROUND(out_shift)) >> out_shift), 8); + } +} + +void local_multiple_mult_q7( q7_t *p_dst, + const int16_t out_shift, + uint32_t block_size, + uint32_t num_block, + q7_t **p_src) +{ + uint32_t i, blk; + q31_t product; + + for (i = 0; i < block_size; i++) + { + product = 1; + for(blk=0; blk < num_block; blk++) + product *= p_src[blk][i]; + p_dst[i] = (q7_t) __NNOM_SSAT(((product + NNOM_ROUND(out_shift)) >> out_shift), 8); + } +} + +void local_multiple_sub_q7( q7_t *p_dst, + const int16_t out_shift, + uint32_t block_size, + uint32_t num_block, + q7_t **p_src) +{ + uint32_t i, blk; + q31_t sub; + + for (i = 0; i < block_size; i++) + { + sub = p_src[0][i]; + for(blk=1; blk < num_block; blk++) + sub -= p_src[blk][i]; + p_dst[i] = (q7_t) __NNOM_SSAT(((sub + NNOM_ROUND(out_shift)) >> out_shift), 8); + } +} + + +void local_q7_to_q15_no_shift(const q7_t *src, q15_t *des, uint32_t size) +{ + // simple unloop + uint32_t count = size/8; + while (count-- > 0) + { + *des++ = (q15_t)*src++; + *des++ = (q15_t)*src++; + *des++ = (q15_t)*src++; + *des++ = (q15_t)*src++; + *des++ = (q15_t)*src++; + *des++ = (q15_t)*src++; + *des++ = (q15_t)*src++; + *des++ = (q15_t)*src++; + } + count = size%8; + while(count-- > 0) + *des++ = (q15_t)*src++; +} + +void local_q7_to_q15(const q7_t *src, q15_t *des, uint32_t size) +{ + // simple unloop + uint32_t count = size/8; + while (count-- > 0) + { + *des++ = (q15_t)*src++<<8; + *des++ = (q15_t)*src++<<8; + *des++ = (q15_t)*src++<<8; + *des++ = (q15_t)*src++<<8; + *des++ = (q15_t)*src++<<8; + *des++ = (q15_t)*src++<<8; + *des++ = (q15_t)*src++<<8; + *des++ = (q15_t)*src++<<8; + } + count = size%8; + while(count-- > 0) + *des++ = (q15_t)*src++<<8; +} + +// right shift q15 to q7 +void local_q15_to_q7(const q15_t *src, q7_t *des, uint32_t shift, uint32_t size) +{ + while(size-- >0) + { + *des = *src >> shift; + des++; + src++; + } +} + diff --git a/components/ai/nnom/src/backends/nnom_local_q15.c b/components/ai/nnom/src/backends/nnom_local_q15.c new file mode 100644 index 000000000..d78c3efc0 --- /dev/null +++ b/components/ai/nnom/src/backends/nnom_local_q15.c @@ -0,0 +1,1602 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Notice: + * Code in this file inlcudes derivative works from CMSIS + * Please check the LICENSE file for detial. + * + * Change Logs: + * Date Author Notes + * 2020-10-05 Jianjia Ma The first version + */ + +#include "nnom.h" +#include "nnom_local.h" + +// modified from CMSIS-NN test_ref +void local_avepool_q15_HWC(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + const uint16_t output_shift, // output right shift + q7_t *bufferA, // a buffer for local storage, NULL by now + q15_t *Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out_y; i_y++) + { + for (i_x = 0; i_x < dim_im_out_x; i_x++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride_y - padding_y; k_y < i_y * stride_y - padding_y + dim_kernel_y; k_y++) + { + for (k_x = i_x * stride_x - padding_x; k_x < i_x * stride_x - padding_x + dim_kernel_x; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in_y && k_x < dim_im_in_x) + { + sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in_x)]; + count++; + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out_x)] = sum / (count>>output_shift); + } + } + } +} + +void local_avepool_q15_CHW(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + const uint16_t output_shift, // output right shift + q7_t *bufferA, // a buffer for local storage, NULL by now + q15_t *Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + int32_t ch_offset; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + ch_offset = i_ch_in*dim_im_in_x*dim_im_in_y; + for (i_y = 0; i_y < dim_im_out_y; i_y++) + { + for (i_x = 0; i_x < dim_im_out_x; i_x++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride_y - padding_y; k_y < i_y * stride_y - padding_y + dim_kernel_y; k_y++) + { + for (k_x = i_x * stride_x - padding_x; k_x < i_x * stride_x - padding_x + dim_kernel_x; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in_y && k_x < dim_im_in_x) + { + sum += Im_in[ch_offset + (k_x + k_y * dim_im_in_x)]; + count++; + } + } + } + Im_out[i_ch_in*dim_im_out_x*dim_im_out_y + (i_x + i_y * dim_im_out_x)] = sum / (count>>output_shift); + } + } + } +} + +// modified from CMSIS-NN test_ref +void local_maxpool_q15_HWC(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t *bufferA, // a buffer for local storage, NULL by now + q15_t *Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out_y; i_y++) + { + for (i_x = 0; i_x < dim_im_out_x; i_x++) + { + int max = -32768; + for (k_y = i_y * stride_y - padding_y; k_y < i_y * stride_y - padding_y + dim_kernel_y; k_y++) + { + for (k_x = i_x * stride_x - padding_x; k_x < i_x * stride_x - padding_x + dim_kernel_x; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in_y && k_x < dim_im_in_x) + { + if (Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in_x)] > max) + { + max = Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in_x)]; + } + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out_x)] = max; + } + } + } +} + +void local_maxpool_q15_CHW(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t *bufferA, // a buffer for local storage, NULL by now + q15_t *Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + int32_t ch_offset; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + ch_offset = i_ch_in * dim_im_out_x * dim_im_out_y; + for (i_y = 0; i_y < dim_im_out_y; i_y++) + { + for (i_x = 0; i_x < dim_im_out_x; i_x++) + { + int max = -32768; + for (k_y = i_y * stride_y - padding_y; k_y < i_y * stride_y - padding_y + dim_kernel_y; k_y++) + { + for (k_x = i_x * stride_x - padding_x; k_x < i_x * stride_x - padding_x + dim_kernel_x; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in_y && k_x < dim_im_in_x) + { + if (Im_in[i_ch_in * dim_im_in_x * dim_im_in_y + (k_x + k_y * dim_im_in_x)] > max) + { + max = Im_in[i_ch_in * dim_im_in_x * dim_im_in_y + (k_x + k_y * dim_im_in_x)]; + } + } + } + } + Im_out[ch_offset+(i_x + i_y * dim_im_out_x)] = max; + } + } + } +} + +// shift according to the maximum +void local_sumpool_q15_HWC(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + const uint16_t output_shift, // output right shift + q7_t *bufferA, // a buffer for local storage, size = 4*output_size + q15_t *Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + int32_t *buf = (int32_t *)bufferA; + // stage2 + // int32_t max_abs = 0; + // int32_t output_shift; + // size_t output_size = dim_im_out_x * dim_im_out_x * ch_im_in; + + // save in 32bit + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out_y; i_y++) + { + for (i_x = 0; i_x < dim_im_out_x; i_x++) + { + int sum = 0; + for (k_y = i_y * stride_y - padding_y; k_y < i_y * stride_y - padding_y + dim_kernel_y; k_y++) + { + for (k_x = i_x * stride_x - padding_x; k_x < i_x * stride_x - padding_x + dim_kernel_x; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in_y && k_x < dim_im_in_x) + { + sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in_x)]; + } + } + } + // 32bit + buf[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out_x)] = (q15_t)__NNOM_SSAT((sum >> output_shift), 16); + } + } + } + + // // find max amount results + // for (int i = 0; i < output_size; i++) + // { + // int32_t val = buf[i]; + // if (val < 0) + // val = -val; + // if (val > max_abs) + // max_abs = val; + // } + // // find best shift to cover the max + // for (output_shift = 0;; output_shift++) + // { + // if (127 * (1 + output_shift) >= max_abs) + // break; + // } + + // // shift the results + // for (int i = 0; i < output_size; i++) + // { + // Im_out[i] = buf[i] >> output_shift; + // } + //return output_shift; +} + +// temporary for the thesis +// shift according to the maximum +void local_sumpool_q15_CHW(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t padding_x, // padding sizes + const uint16_t padding_y, // padding sizes + const uint16_t stride_x, // stride + const uint16_t stride_y, // stride + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + const uint16_t output_shift, // output right shift + q7_t *bufferA, // a buffer for local storage, size = 4*output_size + q15_t *Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + int32_t *buf = (int32_t *)bufferA; + int32_t i_ch_offset, o_ch_offset; + // // stage2 + // int32_t max_abs = 0; + // int32_t output_shift; + // size_t output_size = dim_im_out_x * dim_im_out_x * ch_im_in; + + // save in 32bit + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + i_ch_offset = i_ch_in*dim_im_in_x*dim_im_in_y; + o_ch_offset = i_ch_in*dim_im_out_x*dim_im_out_y; + + for (i_y = 0; i_y < dim_im_out_y; i_y++) + { + for (i_x = 0; i_x < dim_im_out_x; i_x++) + { + int sum = 0; + for (k_y = i_y * stride_y - padding_y; k_y < i_y * stride_y - padding_y + dim_kernel_y; k_y++) + { + for (k_x = i_x * stride_x - padding_x; k_x < i_x * stride_x - padding_x + dim_kernel_x; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in_y && k_x < dim_im_in_x) + { + sum += Im_in[i_ch_offset + (k_x + k_y * dim_im_in_x)]; + } + } + } + // 32bit + buf[o_ch_offset + (i_x + i_y * dim_im_out_x)] = (q15_t)__NNOM_SSAT((sum >> output_shift), 16); + } + } + } + + // // find max amount results + // for (int i = 0; i < output_size; i++) + // { + // int32_t val = buf[i]; + // if (val < 0) + // val = -val; + // if (val > max_abs) + // max_abs = val; + // } + // // find best shift to cover the max + // for (output_shift = 0;; output_shift++) + // { + // if (127 * (1 + output_shift) >= max_abs) + // break; + // } + + // // shift the results + // for (int i = 0; i < output_size; i++) + // { + // Im_out[i] = buf[i] >> output_shift; + // } + //return output_shift; +} + +// customised up sample pooling +void local_up_sampling_q15_HWC(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimension x or W + const uint16_t dim_im_in_y, // input image dimension y or H + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel_x, // window kernel size + const uint16_t dim_kernel_y, // window kernel size + const uint16_t dim_im_out_x, // output image dimension x or W + const uint16_t dim_im_out_y, // output image dimension y or H + q7_t *bufferA, // a buffer for local storage, NULL by now + q15_t *Im_out) +{ + int16_t i_x, i_y; + + // for loop for each pixel in input image. + for (i_y = 0; i_y < dim_im_in_y; i_y++) + { + for (i_x = 0; i_x < dim_im_in_x; i_x++) + { + // copy all the channels together. + const q15_t *p_in = Im_in + (i_y * dim_im_in_x + i_x ) * ch_im_in; + q15_t *pout = Im_out + (i_y * dim_im_in_x * dim_kernel_x * dim_kernel_y + i_x * dim_kernel_y) * ch_im_in; + + // copy along x axis + for(int i = 0; i> out_shift[shift_idx]), 16); + } + } + } +} + +void local_convolve_CHW_q15_nonsquare(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const nnom_qformat_param_t *bias_shift, // bias shifts + const nnom_qformat_param_t *out_shift, // output shift + const nnom_qtype_t q_type, // per channel or per tensor + q15_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +) +{ + int i, j, k, l, m, n; + int64_t conv_out; + int in_row, in_col; + int shift_idx, shift_steps; + if(q_type == NNOM_QTYPE_PER_AXIS) + shift_steps = 1; + else + shift_steps = 0; + + for(i = 0, shift_idx = 0; i < ch_im_out; i++, shift_idx += shift_steps) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + if(bias) + conv_out = ((q31_t)(bias[i]) << bias_shift[shift_idx]) + NNOM_ROUND(out_shift[shift_idx]); + else + conv_out = (q31_t)NNOM_ROUND(out_shift[shift_idx]); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m * dilation_y - padding_y; + in_col = stride_x * k + n * dilation_x - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) + l * dim_im_in_x * dim_im_in_y] * + wt[(m * dim_kernel_x + n) * ch_im_in * ch_im_out + l * ch_im_out + i]; + } + } + } + } + Im_out[i * dim_im_out_x * dim_im_out_y + (j * dim_im_out_x + k)] = (q15_t)__NNOM_SSAT((conv_out >> out_shift[shift_idx]), 16); + } + } + } +} + +#define FALSE 0 +#define TRUE 1 + +static int alg_deconv2d_calculate_position( + int pos, + int stride, + int padding, + int dim_kernel, + int dim_in, + int* in_start, + int* kernel_start, + int* kernel_end) +{ + int is_zero = FALSE; + int of, adj; + is_zero = FALSE; + *in_start = pos/stride; + of = pos%stride; + *kernel_start = padding - of; + if(*kernel_start >= 0) { + adj = MIN(*in_start, *kernel_start/stride); + *kernel_start -= adj*stride; + *in_start -= adj; + } else { + adj = -*kernel_start + dim_kernel; + if(adj<=stride) { + is_zero = TRUE; + } else { + adj = MIN(dim_in-1-*in_start, adj/stride); + *kernel_start += adj*stride; + *in_start += adj; + } + } + of = dim_kernel - 1 - *kernel_start; + adj = MIN(dim_in-1-*in_start, of/stride); + *kernel_end = *kernel_start + adj*stride; + + return is_zero; +} + +void local_conv_trans_HWC_q15_nonsquare(const int8_t * Im_in, + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q15_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +) +// { +// int ox, oy, oc, ky, kx, kc, ix, iy; +// int conv_out; +// int in_pix_loc, wt_loc; + +// (void)dilation_y; +// (void)dilation_x; + +// // padding and stride are applied to output +// for (oc = 0; oc < ch_im_out; oc++) +// { +// for (oy = 0; oy < dim_im_out_y; oy++) +// { +// for (ox = 0; ox < dim_im_out_x; ox++) +// { +// conv_out = ((q31_t)(bias[oc]) << bias_shift) + NNOM_ROUND(out_shift); + +// for (ky = 0; ky < dim_kernel_y; ky++) +// { +// for (kx = 0; kx < dim_kernel_x; kx++) +// { +// // input y, input x location +// iy = oy / stride_y + ky - padding_y; +// ix = ox / stride_x + kx - padding_x; + +// if(ix >= 0 && iy >= 0 && ix < dim_im_in_y && iy< dim_im_in_y) +// { +// in_pix_loc = (iy * dim_im_in_x + ix) * ch_im_in; +// wt_loc = oc * ch_im_in * dim_kernel_y * dim_kernel_x + (ky * dim_kernel_x + kx) * ch_im_in; + +// for (kc = 0; kc < ch_im_in; kc++) +// { +// conv_out += Im_in[in_pix_loc + kc] * wt[wt_loc + kc]; +// } +// } +// } +// } + +// Im_out[oc + (oy * dim_im_out_x + ox) * ch_im_out] = (q7_t) __NNOM_SSAT((conv_out >> out_shift), 8); +// } +// } +// } +// } + +{ + int i, j, k, l, m, n; + int64_t conv_out; + int in_row, in_col; + int kernel_start_x,kernel_end_x; + int kernel_start_y,kernel_end_y; + int in_row_start, in_col_start; + int is_zero; + + for (i = 0; i < ch_im_out; i++) { + for (j = 0; j < dim_im_out_y; j++) { + is_zero = alg_deconv2d_calculate_position(j, stride_y, padding_y, dim_kernel_y, + dim_im_in_y, &in_row_start, &kernel_start_y, &kernel_end_y); + + if(is_zero) { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NNOM_ROUND(out_shift); + conv_out = (q15_t) __NNOM_SSAT((conv_out >> out_shift), 16); + for (k = 0; k < dim_im_out_x; k++) { + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q15_t) conv_out; + } + continue; + } + + for (k = 0; k < dim_im_out_x; k++) { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NNOM_ROUND(out_shift); + + is_zero = alg_deconv2d_calculate_position(k, stride_x, padding_x, dim_kernel_x, + dim_im_in_x, &in_col_start, &kernel_start_x, &kernel_end_x); + + if(is_zero) { + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = conv_out; + continue; + } + + for (m = kernel_start_y, in_row = in_row_start; m <= kernel_end_y; m+=stride_y, in_row++) { + for (n = kernel_start_x, in_col = in_col_start; n <= kernel_end_x; n+=stride_x, in_col++) { + if ((in_row >= 0) && (in_col >= 0) && + (in_row < dim_im_in_y) && (in_col < dim_im_in_x)) { + for (l = 0; l < ch_im_in; l++) { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + l]; + } + } + } + } + + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q15_t) __NNOM_SSAT((conv_out >> out_shift), 16); + } + } + } +} + + + + +void local_depthwise_separable_conv_HWC_q15_nonsquare(const q15_t *Im_in,// input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const nnom_qformat_param_t *bias_shift, // bias shifts + const nnom_qformat_param_t *out_shift, // output shift + const nnom_qtype_t q_type, // per channel or per tensor + q15_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +) +{ + int i_out_y, i_out_x, i_ch_out, i_ch_in, i_ch_mult; + int i_ker_y, i_ker_x; + int i_out = 0; + int shift_idx; + int ch_mult = ch_im_out / ch_im_in; + int64_t conv_out; + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + const int32_t base_idx_y = stride_y * i_out_y - padding_y; + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + const int32_t base_idx_x = stride_x * i_out_x - padding_x; + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for(i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + { + i_ch_out = i_ch_mult + i_ch_in * ch_mult; + int32_t ker_y_start = MAX(0, -base_idx_y); + int32_t ker_x_start = MAX(0, -base_idx_x); + int32_t ker_y_end = MIN(dim_kernel_y, dim_im_in_y - base_idx_y); + int32_t ker_x_end = MIN(dim_kernel_x, dim_im_in_x - base_idx_x); + + shift_idx = q_type == NNOM_QTYPE_PER_AXIS ? i_ch_out : 0; + if (bias) + conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift[shift_idx]) + NNOM_ROUND(out_shift[shift_idx]); + else + conv_out = (q31_t)NNOM_ROUND(out_shift[shift_idx]); + + for (i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + i_ker_y * dilation_y; + for (i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + i_ker_x * dilation_x; + int32_t in_pix_loc = (idx_y * dim_im_in_x + idx_x) * ch_im_in + i_ch_in; + int32_t wt_loc = (i_ker_y * dim_kernel_x + i_ker_x) * (ch_im_in * ch_mult) + i_ch_out; + conv_out += Im_in[in_pix_loc] * wt[wt_loc]; + } + } + Im_out[i_out++] = (q15_t)__NNOM_SSAT((conv_out >> out_shift[shift_idx]), 16); + } + } + } + } +} + +void local_depthwise_separable_conv_CHW_q15_nonsquare(const q15_t *Im_in,// input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t *wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const uint16_t dilation_x, // dilation x + const uint16_t dilation_y, // dilation y + const q7_t *bias, // bias + const nnom_qformat_param_t *bias_shift, // bias shifts + const nnom_qformat_param_t *out_shift, // output shift + const nnom_qtype_t q_type, // per channel or per tensor + q15_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t *bufferA, //buffer space for input + q7_t *bufferB //buffer space for output +) +{ + int i_out_y, i_out_x, i_ch_out, i_ch_in, i_ch_mult; + int i_ker_y, i_ker_x; + int shift_idx; + int ch_mult = ch_im_out / ch_im_in; + int64_t conv_out; + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + const int32_t base_idx_y = stride_y * i_out_y - padding_y; + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + const int32_t base_idx_x = stride_x * i_out_x - padding_x; + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult++) + { + i_ch_out = i_ch_mult + i_ch_in * ch_mult; + int32_t ker_y_start = MAX(0, -base_idx_y); + int32_t ker_x_start = MAX(0, -base_idx_x); + int32_t ker_y_end = MIN(dim_kernel_y, dim_im_in_y - base_idx_y); + int32_t ker_x_end = MIN(dim_kernel_x, dim_im_in_x - base_idx_x); + + shift_idx = q_type == NNOM_QTYPE_PER_AXIS ? i_ch_out : 0; + if (bias) + conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift[shift_idx]) + NNOM_ROUND(out_shift[shift_idx]); + else + conv_out = (q31_t)NNOM_ROUND(out_shift[shift_idx]); + + for (i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++) + { + const int32_t idx_y = base_idx_y + i_ker_y * dilation_y; + for (i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++) + { + const int32_t idx_x = base_idx_x + i_ker_x * dilation_x; + int32_t in_pix_loc = (idx_y * dim_im_in_x + idx_x) + i_ch_in * dim_im_in_x * dim_im_in_y; + int32_t wt_loc = (i_ker_y * dim_kernel_x + i_ker_x) * ch_im_out + i_ch_out; + conv_out += Im_in[in_pix_loc] * wt[wt_loc]; + } + } + Im_out[i_ch_out * dim_im_out_x * dim_im_out_y + (i_out_y * dim_im_out_x + i_out_x)] = + (q15_t)__NNOM_SSAT((conv_out >> out_shift[shift_idx]), 16); + } + } + } + } + +} + +void local_zero_padding_HWC_q15(const q15_t *Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const uint16_t padding_top, // padding sizes y + const uint16_t padding_bottom, // padding sizes y + const uint16_t padding_left, // padding sizes x + const uint16_t padding_right, // padding sizes x + q15_t *Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y) // output image dimension y +{ + int i, size; + q15_t * p_out = Im_out; + + // top rows + size = dim_im_out_x*ch_im_in*padding_top; + nnom_memset(p_out, 0, size*sizeof(q15_t)); + p_out += size; + + // middle + for(i=0; i> out_shift), 16); + } +} + +void local_dot_q15_opt(const q15_t * pV, + const q15_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t out_shift, + q15_t * pOut) +{ + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t rowCnt = num_of_rows >> 2; + const q15_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + + while (rowCnt) + { + int64_t sum = (q31_t) NNOM_ROUND(out_shift); + int64_t sum2 = (q31_t) NNOM_ROUND(out_shift); + int64_t sum3 = (q31_t) NNOM_ROUND(out_shift); + int64_t sum4 = (q31_t) NNOM_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 1; + pA = pV; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + q15_t inB1 = *pB++; + q15_t inB2 = *pB++; + sum += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum2 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum3 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum4 += inA1 * inB1 + inA2 * inB2; + + colCnt--; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + colCnt--; + } + *pO++ = (q15_t) __NNOM_SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __NNOM_SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __NNOM_SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __NNOM_SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int64_t ip_out = (q31_t) + NNOM_ROUND(out_shift); + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __NNOM_SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } +} + +void local_fully_connected_mat_q7_vec_q15_opt(const q15_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q15_t * pOut, + q15_t * vec_buffer) +{ + + (void)vec_buffer; + + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + int64_t sum; + int64_t sum2; + int64_t sum3; + int64_t sum4; + uint16_t colCnt = dim_vec >> 1; + + // quick and dirty to support none bias fully connected + if(bias) + { + sum = ((q31_t)(*pBias++) << bias_shift) + NNOM_ROUND(out_shift); + sum2 = ((q31_t)(*pBias++) << bias_shift) + NNOM_ROUND(out_shift); + sum3 = ((q31_t)(*pBias++) << bias_shift) + NNOM_ROUND(out_shift); + sum4 = ((q31_t)(*pBias++) << bias_shift) + NNOM_ROUND(out_shift); + } + else + { + sum = (q31_t) NNOM_ROUND(out_shift); + sum2 = (q31_t) NNOM_ROUND(out_shift); + sum3 = (q31_t) NNOM_ROUND(out_shift); + sum4 = (q31_t) NNOM_ROUND(out_shift); + } + + pA = pV; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + colCnt--; + } + + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q15_t) __NNOM_SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __NNOM_SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __NNOM_SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __NNOM_SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int64_t ip_out; + int j; + + // quick and dirty to support none bias fully connected + if(bias) + ip_out = ((q31_t)(*pBias++) << bias_shift) + NNOM_ROUND(out_shift); + else + ip_out = (q31_t)NNOM_ROUND(out_shift); + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __NNOM_SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } +} + +void local_fully_connected_mat_q7_vec_q15(const q15_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q15_t * pOut, + q15_t * vec_buffer) +{ + int i, j; + + // a quick solution for none-bias dot. + if(bias == NULL) + { + for (i = 0; i < num_of_rows; i++) + { + int64_t ip_out = (q31_t) NNOM_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t) __NNOM_SSAT((ip_out >> out_shift), 16); + } + } + else + { + for (i = 0; i < num_of_rows; i++) + { + int64_t ip_out = ((q31_t)(bias[i]) << bias_shift) + NNOM_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t) __NNOM_SSAT((ip_out >> out_shift), 16); + } + } +} + +// This softmax is a copy from ARM CMSIS implimentation as it was efficient and written in pure-C. +// original implementation: https://github.com/ARM-software/CMSIS_5/blob/develop/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c +void local_softmax_q15(const q15_t * vec_in, const uint16_t dim_vec, q15_t * p_out) +{ + q31_t sum; + int16_t i; + uint8_t shift; + q31_t base; + base = -1 * 0x100000; + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } + + /* we ignore really small values + * anyway, they will be 0 after shrinking + * to q15_t + */ + base = base - 16; + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + shift = (uint8_t)__NNOM_USAT(vec_in[i] - base, 5); + sum += 0x1 << shift; + } + } + + /* This is effectively (0x1 << 32) / sum */ + int64_t div_base = 0x100000000LL; + int output_base = (int32_t)(div_base / sum); + + /* Final confidence will be output_base >> ( 17 - (vec_in[i] - base) ) + * so 32768 (0x1<<15) -> 100% confidence when sum = 0x1 << 16, output_base = 0x1 << 16 + * and vec_in[i]-base = 16 + */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + /* Here minimum value of 17+base-vec[i] will be 1 */ + shift = (uint8_t)__NNOM_USAT(17+base-vec_in[i], 5); + p_out[i] = (q15_t) __NNOM_SSAT((output_base >> shift), 16); + } else + { + p_out[i] = 0; + } + } + +} + + +// hard sigmoid, +// y=-1 if x < -2.5 +// y=1 if x > 2.5 +// otherwise y = 0.2 * x + 0.5 (y=0.20315 * x + 0.5) +void local_hard_sigmoid_q15(q15_t *data, uint32_t size, int16_t dec_bit) +{ + int16_t limit = 2.5f * (1 << dec_bit)-1; + int16_t offset = 16384; // 0.5 * 32768 + int16_t mult = 6554; // 0.2 * 32768 + + // int bit >= 0 + for(int i=0; i= limit) + data[i] = 32767; + else + { + data[i] = ((int32_t)(data[i] * mult) >> dec_bit) + offset; + } + } + } + +// hard tanh +// y=-1 if x < -1 +// y=1 if x > 1 +// otherwise y = x +void local_hard_tanh_q15(q15_t *data, uint32_t size, int16_t dec_bit) +{ + int16_t int_bit = 15 - dec_bit; + int16_t limit = 1 << dec_bit; + + if(dec_bit == 15) + return; + + // int bit < 0 + if(int_bit < 0) + for(int i=0; i= limit) + data[i] = 32767; + else + { + data[i] = data[i] >> (-int_bit); + } + } + else + // int bit >= 0 + for(int i=0; i= limit) + data[i] = 32767; + else + { + data[i] = data[i] << int_bit; + } + } +} + +void local_relu_q15(q15_t *data, uint32_t size) +{ + uint32_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } +} + +// alpha in q7 format with dec_bit=7 +void local_leaky_relu_q15(q15_t *data, q7_t alpha, uint32_t size) +{ + uint32_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + { + data[i] = data[i] * alpha / 128; + } + } +} + +// alpha in q7 format with dec_bit=7 +// max and threshold has the same Q format with the activation +void local_adv_relu_q15(q15_t *data, q7_t negative_slope, q15_t max, q15_t threshold, uint32_t size) +{ + uint32_t i; + for (i = 0; i < size; i++) + { + // `f(x) = max_value` for `x >= max_value`, + // `f(x) = x` for `threshold <= x < max_value`, + // `f(x) = alpha * (x - threshold)` otherwise. + + if(data[i] > max) + data[i] = max; + if (data[i] < threshold) + data[i] = (data[i] - threshold) * negative_slope / 128; + } +} + +// ARM's CMSIS implementation. +static void local_activation_q15(q15_t * data, uint32_t size, uint16_t int_width, const q15_t*lookup_table) +{ + uint32_t i = size; + q15_t *pIn = data; + q15_t *pOut = data; + uint16_t shift_size = 8 + 3 - int_width; + uint32_t bit_mask = 0x7FF >> int_width; + uint32_t full_frac = bit_mask + 1; + while (i) + { + q15_t out; + q15_t in = *pIn++; + q15_t frac = (uint32_t) in & bit_mask; + q15_t value = lookup_table[(uint8_t)(in >> shift_size)]; + if ((in >> shift_size) != 0x7f) + { + q15_t value2 = lookup_table[(uint8_t)(1 + ((uint8_t)(in >> shift_size)))]; + /* doing the interpolation here for better accuracy */ + out = ((q31_t) (full_frac - frac) * value + (q31_t) value2 * frac) >> shift_size; + } else + { + /* the largest positive value does not have a right side for linear interpolation */ + out = value; + } + *pOut++ = out; + i--; + } +} + +void local_sigmoid_q15(q15_t * data, uint32_t size, uint16_t int_width) +{ + local_activation_q15(data, size, int_width, nnom_sigmoid_table_q15); +} + +void local_tanh_q15(q15_t * data, uint32_t size, uint16_t int_width) +{ + local_activation_q15(data, size, int_width, nnom_tanh_table_q15); +} + +// matrix ops q15 +void local_mult_q15(q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + const uint16_t out_shift, + uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + q31_t product = pSrcA[i] * pSrcB[i]; + pDst[i] = (q15_t) __NNOM_SSAT(((product + NNOM_ROUND(out_shift)) >> out_shift), 16); + } +} + +void local_add_q15(q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + const uint16_t out_shift, + uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + q31_t sum = pSrcA[i] + pSrcB[i]; + pDst[i] = (q15_t) __NNOM_SSAT(((sum + NNOM_ROUND(out_shift)) >> out_shift), 16); + } +} + +void local_sub_q15(q15_t *pSrcA, + q15_t *pSrcB, + q15_t *pDst, + const uint16_t out_shift, + uint32_t blockSize) +{ + uint32_t i; + + for (i = 0; i < blockSize; i++) + { + q31_t sub = pSrcA[i] - pSrcB[i]; + pDst[i] = (q15_t) __NNOM_SSAT(((sub + NNOM_ROUND(out_shift)) >> out_shift), 16); + } +} + + +void local_multiple_add_q15( q15_t *p_dst, + const int16_t out_shift, + uint32_t block_size, + uint32_t num_block, + q15_t **p_src) +{ + uint32_t i, blk; + q31_t sum; + + for (i = 0; i < block_size; i++) + { + sum = 0; + for(blk=0; blk < num_block; blk++) + sum += p_src[blk][i]; + p_dst[i] = (q15_t) __NNOM_SSAT(((sum + NNOM_ROUND(out_shift)) >> out_shift), 16); + } +} + +void local_multiple_mult_q15( q15_t *p_dst, + const int16_t out_shift, + uint32_t block_size, + uint32_t num_block, + q15_t **p_src) +{ + uint32_t i, blk; + q63_t product; + + for (i = 0; i < block_size; i++) + { + product = 1; + for(blk=0; blk < num_block; blk++) + product *= p_src[blk][i]; + p_dst[i] = (q15_t) __NNOM_SSAT(((product + NNOM_ROUND(out_shift)) >> out_shift), 16); + } +} + +void local_multiple_sub_q15( q15_t *p_dst, + const int16_t out_shift, + uint32_t block_size, + uint32_t num_block, + q15_t **p_src) +{ + uint32_t i, blk; + q31_t sub; + + for (i = 0; i < block_size; i++) + { + sub = p_src[0][i]; + for(blk=1; blk < num_block; blk++) + sub -= p_src[blk][i]; + p_dst[i] = (q15_t) __NNOM_SSAT(((sub + NNOM_ROUND(out_shift)) >> out_shift), 16); + } +} + +// y = 1 - x +void local_1_minor_z_q15(q15_t* src, q15_t*des, uint16_t dec_bit, uint32_t size) +{ + int32_t one = (1 << dec_bit)-1; + for(int i=0; i +#include +#include +#include +#include "nnom.h" + +const char default_layer_names[][12] = DEFUALT_LAYER_NAMES; +const char default_activation_names[][8] = ACTIVATION_NAMES; +const char default_cell_names[][8] = DEFUALT_CELL_NAMES; +size_t nnom_memory_taken = 0; + +// local static functions (when libc/dynamic memory interfaces are not avaiable. ) +#ifdef NNOM_USING_STATIC_MEMORY +static uint8_t *nnom_static_buf = NULL; //pointer to static buffer +static size_t nnom_static_buf_size = 0; //static buf size +static size_t nnom_static_buf_curr = 0; +void nnom_set_static_buf(void* buf, size_t size) +{ + nnom_static_buf = buf; + nnom_static_buf_size = size; + nnom_static_buf_curr = 0; +} +void* nnom_malloc(size_t size) +{ + size = nnom_alignto(size, NNOM_ALIGN); + if(size + nnom_static_buf_curr < nnom_static_buf_size) + { + uint8_t* new_block = nnom_static_buf_curr + nnom_static_buf; + nnom_static_buf_curr += size; + return new_block; + } + else + { + if(nnom_static_buf_size == 0) + NNOM_LOG("Please set static memory using 'nnom_set_static_buf()' before calling model created."); + else + NNOM_LOG("No memory! Static buffer size(%d) not big enough, please increase buffer size!", + (uint32_t)nnom_static_buf_size); + return NULL; + } +} +void nnom_free(void* p){;} +#endif // NNOM_USING_STATIC_MEMORY + +void *nnom_mem(size_t size) +{ + size = nnom_alignto(size, NNOM_ALIGN); + void *p = (void*)nnom_malloc(size); + if (p) + { + nnom_memory_taken += size; //test + nnom_memset(p, 0, size); + } + return p; +} + +size_t nnom_mem_stat(void) +{ + return nnom_memory_taken; +} + +// get the size of an IO module +static size_t io_mem_size(nnom_layer_io_t *io) +{ + size_t size = 0; + if (io != NULL) + { + while (io) + { + size += tensor_size(io->tensor); + io = io->aux; + } + } + return size; +} + +size_t nnom_alignto(size_t value, uint32_t alignment) +{ + if (value % alignment == 0) + return value; + value += alignment - value % alignment; + return value; +} + +static nnom_layer_t *find_last(nnom_layer_t *layer) +{ + if (layer == NULL) + return NULL; + // iterate every layer until the last one on the list, then return the last instance + while (layer->out->hook.io != NULL) + layer = layer->out->hook.io->owner; + return layer; +} +// input start layer, return layer num +static uint32_t find_index(nnom_layer_t *start, nnom_layer_t *layer) +{ + uint32_t i = 1; + if (start == NULL) + return 0; + // iterate every layer until the last one on the list, then return the index number + while (start->out->hook.io != NULL) + { + i++; + if (layer == start) + return i; + start = start->out->hook.io->owner; + } + return 0; +} + +static nnom_status_t model_add(nnom_model_t *model, nnom_layer_t *layer) +{ + nnom_layer_t *last = NULL; + nnom_layer_t *curr = NULL; + + if (layer == NULL) + { + NNOM_LOG("Error: added a NULL layer, could be no memory while creating layer.\n"); + return NN_NO_MEMORY; + } + + last = find_last(model->head); + curr = layer; + + // when the layer list is empty, the find_last() return model->head. + if (last == NULL) + { + model->head = curr; + } + else + { + // hook the current layer with the last layer. + last->out->hook.io = curr->in; // hook IO + curr->in->hook.io = last->out; + } + return NN_SUCCESS; +} + +// find an available hook on the io module, normally used by output io module. +// input, the output io module that wants to hook on +// output, the new hook that added to the end of the hook list on the io +static nnom_layer_hook_t *allocate_hook(nnom_layer_io_t *io) +{ + nnom_layer_hook_t *hook; + if (io == NULL) + return NULL; + hook = &io->hook; + + // if the primary hook is empty, reture it directly. + if (hook->io == NULL) + { + return hook; + } + else + { + // find the empty place and allocate new hook for us + while (hook->next != NULL) + { + hook = hook->next; + } + hook->next = nnom_mem(sizeof(nnom_layer_hook_t)); + if (hook->next == NULL) + return NULL; + return hook->next; + } +} + +// to check if an io is hooked to other layer +// input the primary io of a layer's input or output +// return, the new io that added to the io list. +static nnom_layer_io_t *allocate_io(nnom_layer_io_t *io) +{ + if (io == NULL) + return NULL; + + // if the io is free to used + if (io->hook.io == NULL) + { + return io; + } + else + { + // find the empty place and allocate new hook for us + while (io->aux != NULL) + { + io = io->aux; + } + io->aux = nnom_mem(sizeof(nnom_layer_io_t)); + if (io->aux == NULL) + return NULL; + // the owner for new io is inherited + io->aux->owner = io->owner; + return io->aux; + } +} + +// hook the current layer to the input layer +// this function only to connect (single output layer) to (single input layer). +static nnom_layer_t *model_hook(nnom_layer_t *curr, nnom_layer_t *last) +{ + nnom_layer_io_t *curr_in_io; + nnom_layer_hook_t *last_io_hook; + + if (last == NULL || curr == NULL) + return NULL; + + // add a new hook to the output io of the last layer + last_io_hook = allocate_hook(last->out); + // add a new input io to the current layer's input list. + curr_in_io = allocate_io(curr->in); + + // manually hook them togeter. + last_io_hook->io = curr_in_io; + curr_in_io->hook.io = last->out; + + return curr; +} + +// merge a few layers using specified method +// num = the number of layer that will be merged +// method = functional layer such as (concat(), mult(), add(), sub()) +static nnom_layer_t *model_mergex(nnom_layer_t *method, int num, ...) +{ + nnom_layer_t *layer_in; + va_list valist; + + if (method == NULL) + return NULL; + + va_start(valist, num); + for (int i = 0; i < num; i++) + { + // get the input layer + layer_in = va_arg(valist, nnom_layer_t *); + model_hook(method, layer_in); + } + va_end(valist); + return method; +} + +// merge 2 input +// this is an older interface +// method = functional layer such as (concat(), mult(), add(), sub()) +static nnom_layer_t *model_merge(nnom_layer_t *method, nnom_layer_t *in1, nnom_layer_t *in2) +{ + return model_mergex(method, 2, in1, in2); +} + +// This api will merge activation to layer's actail to avoid the extra layer for activation +static nnom_layer_t *model_active(nnom_activation_t *act, nnom_layer_t *target) +{ + // simple and easy + target->actail = act; + return target; +} + +// when model=NULL, it create a new sequential model +nnom_model_t *new_model(nnom_model_t *model) +{ + nnom_model_t *m = model; + if (m == NULL) + { + m = nnom_mem(sizeof(nnom_model_t)); + m->is_allocated = true; + } + else + { + nnom_memset(m, 0, sizeof(nnom_model_t)); + m->is_allocated = false; + } + + // set methods + m->add = model_add; + m->hook = model_hook; + m->merge = model_merge; + m->mergex = model_mergex; + m->active = model_active; + + return m; +} + +static void io_tensor_delete(nnom_layer_io_t* io) +{ + while (io) + { + nnom_free(io->tensor); + io = io->aux; + } +} + +// delete all the aux hooks +// delete aux io only, keep the primary io. +static void io_list_delete(nnom_layer_io_t *io) +{ + nnom_layer_hook_t *hook, *next_hook; + nnom_layer_io_t *next_io; + while (io) + { + // store the next io + next_io = io->aux; + + // release hooks list first + hook = io->hook.next; + while (hook) + { + next_hook = hook->next; + nnom_free(hook); + hook = next_hook; + } + + // now we can release the aux io itself + // but if this io is the primary input/out of the layer, it will be freed with they layer's instance since they are allocated together. + if (io != io->owner->in && io != io->owner->out) + nnom_free(io); + + // next aux io + io = next_io; + } +} + +// there are 2 type of memory in a layer +// *primary memory* is allocated when a layer instance is created, they are created by layer API (Conv2D()...). +// it includes the layer instance, primary input, primary output, and an optional computational memory buffer instance +// each io module also has one primary hook. +// *secondary memory* are axiliary io modules, axiliary hooks and activations which created by model.xx() APIs (model.hook(), model.active()...) +// it includes the list of aux io modules, the list of aux hooks. +// +// Additionaly, layer's private free method must be called to free layer's private resources +// Such as activation instance passed to Activation() layer, and private memory allcated within Lambda layer. +// +// A layer is consist of a few io modules. primary io are allocated with layers instance. +// each of the io has a few hooks. primary hooks are included in the io module. +// so only "aux" hooks and ios need to be freed separately. +static void layer_delete(nnom_layer_t *layer) +{ + if (layer == NULL) + return; + + // call private free of the layer + if (layer->free) + layer->free(layer); + + // delete the tensors first. only input layer should delete input + if (layer->type == NNOM_INPUT) + io_tensor_delete(layer->in); + io_tensor_delete(layer->out); + + // release secondary memory on the layers. + // they are io lists and hooks list + io_list_delete(layer->in); + io_list_delete(layer->out); + + // release activations (it takes null too) + nnom_free(layer->actail); + + // release primary memory + nnom_free(layer); + return; +} + +void model_delete(nnom_model_t *m) +{ + nnom_layer_t *layer; + nnom_layer_t *next; + if (m == NULL) + return; + + // uses shortcut list to iterate the model, + // start from head + layer = m->head; + while (layer) + { + // get the next before releasing current + next = layer->shortcut; + // your term + layer_delete(layer); + // who's next! + layer = next; + } + + // free the memory blocks for the network's buffer + nnom_free(m->blocks->blk); + + // free model instance itself + if (m->is_allocated) + nnom_free(m); + else + nnom_memset(m, 0, sizeof(nnom_model_t)); + + nnom_memory_taken = 0; + return; +} + +// find an available memory block. +static nnom_mem_block_t *allocate_block(nnom_mem_block_t *list) +{ + nnom_mem_block_t *free = NULL; + uint32_t idx; + + for (idx = 0; idx < NNOM_BLOCK_NUM; idx++) + { + if (list[idx].owners == 0) + break; + } + if(idx == NNOM_BLOCK_NUM) + { + NNOM_LOG("\nERROR! No enough memory block for parallel buffers, please increase the 'NNOM_BLOCK_NUM' in 'nnom_port.h'\n"); + return NULL; + } + + free = &list[idx]; + return free; +} + +static void release_block(nnom_mem_block_t *block) +{ + if (block->owners > 0) + block->owners -= 1; + if (block->owners == 0) + block->state = NNOM_BUF_EMPTY; +} + +static void release_input_mem(nnom_layer_t *layer) +{ + nnom_layer_io_t *in; + // release all input of buf + in = layer->in; + while (in != NULL) + { + release_block(in->mem); + in = in->aux; + } +} +static void release_comp_mem(nnom_layer_t *layer) +{ + // release computational buf if exist + if (layer->comp != NULL) + { + release_block(layer->comp->mem); + } +} + +// return the length of the io lists +size_t nnom_io_length(nnom_layer_io_t *io) +{ + size_t num = 0; + if (io == NULL) + return 0; + while (io != NULL) + { + num++; + io = io->aux; + } + return num; +} + +// return the length of the hook lists +size_t nnom_hook_length(nnom_layer_hook_t *hook) +{ + size_t num = 0; + if (hook == NULL) + return 0; + while (hook != NULL) + { + num++; + hook = hook->next; + } + return num; +} + +// The shortcut version of find_last() method. +// must be used after compiling. +static nnom_layer_t *layer_shortcut_find_last(nnom_layer_t *start) +{ + nnom_layer_t *layer = start; + if (start == NULL) + return NULL; + while (layer->shortcut != NULL) + layer = layer->shortcut; + return layer; +} + +// call while compiling. +// the shorcut is for fast running and fast iliterating. +// simply link every layer as a list. ordered by its runing order +static nnom_status_t layer_shortcut_add(nnom_layer_t *start, nnom_layer_t *curr) +{ + nnom_layer_t *layer = start; + // first one, return + if (start == curr) + { + return NN_SUCCESS; + } + // find the end of the list, and add curr layer to the end of it. + while (layer->shortcut != NULL) + { + // if the layer is already in shortcut list, tell upper. + if (curr == layer) + return NN_ARGUMENT_ERROR; + layer = layer->shortcut; + } + layer->shortcut = curr; + + return NN_SUCCESS; +} + +// input the layer number, +static void print_layer_info(nnom_layer_t *layer, uint32_t layer_count) +{ + size_t in_size = io_mem_size(layer->in); + size_t out_size = io_mem_size(layer->out); + size_t compsize; + size_t mac = layer->stat.macc; + if (layer->comp != NULL) + compsize = layer->comp->size; + else + compsize = 0; + // names + if(layer->type != NNOM_RNN) + NNOM_LOG("#%-3d %-10s - ", layer_count, default_layer_names[layer->type]); + else + { + NNOM_LOG("#%-3d %-3s/", layer_count, default_layer_names[layer->type]); + NNOM_LOG("%-6s - ", default_cell_names[((nnom_rnn_layer_t*)layer)->cell->type]); + } + + // activations + if (layer->actail != NULL) + NNOM_LOG("%-8s - ", default_activation_names[layer->actail->type]); + else + NNOM_LOG(" - "); + + NNOM_LOG("("); + for (int i = 0; i < 3; i++) + { + if (layer->out->tensor->num_dim > i) + NNOM_LOG("%4d,", layer->out->tensor->dim[i]); + else + NNOM_LOG(" "); + } + NNOM_LOG(") "); + + // MAC operation + if(mac == 0) + NNOM_LOG(" "); + else if (mac < 10000) + NNOM_LOG("%7d ", (uint32_t)mac); + else if (mac < 1000*1000) + NNOM_LOG("%6dk ", (uint32_t)(mac/1000)); + else if (mac < 1000*1000*1000) + NNOM_LOG("%3d.%02dM ", (uint32_t)(mac/(1000*1000)), (uint32_t)(mac%(1000*1000)/(10*1000))); // xxx.xx M + else + NNOM_LOG("%3d.%02dG ", (uint32_t)(mac/(1000*1000*1000)), (uint32_t)(mac%(1000*1000*1000)/(10*1000*1000))); // xxx.xx G + + // memory + NNOM_LOG("(%6d,%6d,%6d)", (uint32_t)in_size, (uint32_t)out_size,(uint32_t) compsize); +} + +static void print_memory_block_info(nnom_mem_block_t *block_pool) +{ + // show the memory blocks's lifetime (number of owners) + NNOM_LOG(" "); + for (int i = 0; i < NNOM_BLOCK_NUM; i++) + { + if (i % 4 == 0) + NNOM_LOG(" "); + if (block_pool[i].owners) + NNOM_LOG("%d ", block_pool[i].owners); + else + NNOM_LOG("- "); + } + NNOM_LOG("\n"); +} + +// This is a nested called functions. +// to analyse the topology of the model, calculate the output_shape of each layer and create shortcut lists. +// Nest will happend when a layer have multiple output module or mutiple output hooks. +// This function will return when +// 1) if the layer has multiple input but not all of them are filled by last layers. returns NN_MORE_TODO +// 2) if all the output hooked are nested called. return NN_SUCCESS +// 3) if the layer is output layer. return NN_SUCCESS +nnom_status_t compile_layers(nnom_layer_t* first, nnom_layer_t *curr, nnom_mem_block_t *block_pool, uint32_t *layer_count) +{ + size_t mem_size = 0; + nnom_layer_t *layer = curr; + nnom_layer_io_t *in; + nnom_layer_io_t *out; + nnom_layer_hook_t *hook; + + nnom_mem_block_t *in_blk; + nnom_mem_block_t *out_blk; + + uint32_t local_layer_count = 1; + + if(layer_count == NULL) + layer_count = &local_layer_count; + + in = layer->in; + out = layer->out; + + while (layer) + { + // check input + in = layer->in; + + // check if this layer is the input layer + // the first layer has no input hooked, and the io is not initialized + if (in->hook.io == NULL) + { + // if the input is not initalized + if (in->mem == NULL) + { + in_blk = allocate_block(block_pool); + in_blk->owners += 1; // add 1 + mem_size = nnom_alignto(tensor_size(in->tensor), NNOM_ALIGN); + in_blk->size = mem_size > in_blk->size ? mem_size : in_blk->size; + // set the blk to the layer IO + in->mem = in_blk; + in->mem->state = NNOM_BUF_FILLED; //mark input buff filled + } + } + else + { + // get the mem for every input from its hooked output. + while (in != NULL) + { + in->mem = in->hook.io->mem; + in = in->aux; + } + } + + // if there are mutiple inputs, wait utill all blocks filled + in = layer->in; + if (in != NULL && in->aux != NULL) + { + while (in != NULL) + { + // if the mem (of its hooked output) is not allocated or is not filled. + // It not the time to run the layer yet, return and waits for next nested called. + if (in->mem == NULL || in->mem->state != NNOM_BUF_FILLED) + return NN_MORE_TODO; + in = in->aux; + } + } + + // if run to this point, then it is the right time to compile(run) this layer. + // compiling are seperated into the steps below. + // 1. to calculate the output shape. + // 2. to put the current layer to the end of shortcut list. + // 3. allocate computational buffer. + // 4. allocate output buffer for each output module. + // 5.1 if there is only one layer hooked to the output. we dont use nested call, but continue in this big while loop. + // 5.2 nested call the hooked output layers (if there are > 1 hooked to the output of this layer) + + // 1. calculate output shape while all inputs are filled + layer->build(layer); + + // 2. add to shortcut list. + layer_shortcut_add(first, layer); + + // 3. assign for computational buf + if (layer->comp != NULL) + { + layer->comp->mem = allocate_block(block_pool); + layer->comp->mem->owners += 1; // add us to buffer users + layer->comp->mem->state = NNOM_BUF_FILLED; + // record maximum mem size in this block + mem_size = nnom_alignto(layer->comp->size, NNOM_ALIGN); + layer->comp->mem->size = + mem_size > layer->comp->mem->size ? mem_size : layer->comp->mem->size; + } + + // print current layer's info. + // show names, activations, mem block size + print_layer_info(layer, (*layer_count)++); + + // 4. allocate output buffer for each output module. + // check output + if (layer->out == NULL) + return NN_SUCCESS; + + // 5.1 if there is only one layer hooked to the output. we dont use nested call, but continue in this big while loop. + // if the layer is Single Output, continue the loop directly. To reduce nested level + if (layer->out->aux == NULL && layer->out->hook.next == NULL) + { + // single buf layer. + if (layer->in->type == NNOM_TENSOR_BUF_NULL || layer->out->type == NNOM_TENSOR_BUF_NULL) + { + // pass to next layer directly, like we never touch the buffer(dont change life-time) + layer->out->mem = layer->in->mem; + + // print memory before release + print_memory_block_info(block_pool); + // computational buf + release_comp_mem(layer); + } + // not a single buf layer + else + { + // allocate mem block for the output + out_blk = allocate_block(block_pool); + if (out_blk == NULL) + return NN_NO_MEMORY; + // set the life time, only one hooked layer, so the life time is 1 + out_blk->owners = 1; + out_blk->state = NNOM_BUF_FILLED; // marked filled + // record maximum mem size in this block + mem_size = nnom_alignto(tensor_size(layer->out->tensor), NNOM_ALIGN); + out_blk->size = mem_size > out_blk->size ? mem_size : out_blk->size; + // set the blk to the layer IO + layer->out->mem = out_blk; + + // once we allocate for output, we can now release input and comput. + // print memory before release + print_memory_block_info(block_pool); + // release input mem and comp mem + release_input_mem(layer); + release_comp_mem(layer); + } + } + // Multiple output and/or mutiple hooks + else + { + // single buf layer will use the input buf for the first output + if (layer->in->type == NNOM_TENSOR_BUF_NULL || layer->out->type == NNOM_TENSOR_BUF_NULL) + { + // we dont allocate new buf, but use the input + // the ownership will be set to next layer later + layer->out->mem = layer->in->mem; + layer->out->mem->owners += nnom_hook_length(&layer->out->hook); // set the mem lifetime.// test + layer->out->mem->state = NNOM_BUF_FILLED; + + // print memory before release + print_memory_block_info(block_pool); + // release computational buff and input buffer + release_input_mem(layer); + release_comp_mem(layer); + } + // mutiple buf layer. (I/O use different memory blocks) + else + { + // allocate for every output + out = layer->out; + while (out != NULL && out->hook.io != NULL) // the output layer have no output IO + { + // assign new block + out->mem = allocate_block(block_pool); + if (out->mem == NULL) + return NN_NO_MEMORY; + // record maximum mem size in this block + mem_size = nnom_alignto(tensor_size(out->tensor), NNOM_ALIGN); + out->mem->size = mem_size > out->mem->size ? mem_size : out->mem->size; + // keep the block untill the last hooked layer is called. + out->mem->owners = nnom_hook_length(&out->hook); // set lifetime of the buffer = the num of hooked layers + out->mem->state = NNOM_BUF_FILLED; + + out = out->aux; + } + // once we allocate for output, we can now release input and comput (or reduce the lifetime). + // print memory before release + print_memory_block_info(block_pool); + // release input mem and comp mem + release_input_mem(layer); + release_comp_mem(layer); + } + + // 5.12 nested call the hooked output layers (if there are > 1 hooked to the output of this layer) + // while all the out module(s) receive a memory block, it is ready to be sent to other layers. + // iterate all hooked layers in each out module. + out = layer->out; + while (out != NULL) + { + // nested call hooked layer one by one. + hook = &out->hook; + while (hook != NULL && hook->io != NULL) + { + compile_layers(first, hook->io->owner, block_pool, layer_count); + hook = hook->next; + } + + // next io + out = out->aux; + } + + // when all the out is called. this should stop here. + // once enter mutiple output iterating, the function will always return. + // because at least one of the nested called by this function will run till the end of the model. + return NN_SUCCESS; + } + // Multiple output ended. + + // return if this is output layer. + // the output layer's output io is hooked to nothing. + if (layer->out->hook.io == NULL) + return NN_SUCCESS; + + // single output layer, this function continue to analyse next layer. + // switch to next layer. + layer = layer->out->hook.io->owner; + } + + // seems to be redundants + return NN_SUCCESS; +} + +size_t mem_analysis_result(nnom_model_t *m) +{ + uint32_t index; + uint32_t total_mem = 0; + NNOM_LOG("Memory cost by each block:\n "); + // print size of memory blocks + for (index = 0; index < NNOM_BLOCK_NUM; index++) + { + total_mem += m->blocks[index].size; + NNOM_LOG("blk_%d:%d ", index, (uint32_t)(m->blocks[index].size)); + } + // size of total memory cost by networks buffer + NNOM_LOG("\n Memory cost by network buffers: %d bytes\n", total_mem); + return total_mem; +} + +// allocate memory, and set them to each block according to the mem analysis results. +nnom_status_t block_mem_set(nnom_model_t *m, void *buf) +{ + uint32_t index; + uint32_t mem_offset = 0; + + for (index = 0; index < NNOM_BLOCK_NUM; index++) + { + if (m->blocks[index].size == 0) + break; + m->blocks[index].blk = (void *)((uint8_t*)buf + mem_offset); + mem_offset += m->blocks[index].size; + } + return NN_SUCCESS; +} + +// experimental: this function is temporary use to +// assign memory blk which has assigned to input and output to the corresponding tensor +nnom_status_t tensor_mem_set(nnom_model_t *m) +{ + nnom_layer_t *layer = m->head; + nnom_layer_io_t *io; + while (layer) + { + io = layer->in; + while (io) + { + io->tensor->p_data = io->mem->blk; + io = io->aux; + } + + io = layer->out; + while (io) + { + io->tensor->p_data = io->mem->blk; + io = io->aux; + } + + layer = layer->shortcut; + } + + return NN_SUCCESS; +} + +// this function has to be used after memory is assigned to the layers. +// it means it has to be call after compile_model() as well. +// it simply get the output buffer and set the buffer to tailed activation of each layer.. +nnom_status_t set_tailed_activation(nnom_model_t *m) +{ + NNOM_NULL_CHECK(m); + NNOM_NULL_CHECK(m->head); + nnom_layer_t *layer = m->head; + + // if tailed activation is exist, set it to the output. + while (layer) + { + if (layer->actail != NULL) + { + layer->actail->tensor = layer->out->tensor; + } + if (layer->shortcut == NULL) + break; + layer = layer->shortcut; + } + + return NN_SUCCESS; +} + +// get total ops +static uint64_t model_set_ops(nnom_model_t *m) +{ + nnom_layer_t *layer; + uint64_t total_ops = 0; + layer = m->head; + while (layer) + { + total_ops += layer->stat.macc; + if (layer->shortcut == NULL) + break; + layer = layer->shortcut; + } + m->total_ops = total_ops; + return total_ops; +} + +// a compiler can be use for both sequencial / functional model. +// the output layer is optional only when the model is single output model +// in this case, if output = NULL, the compile can find it by its own. +nnom_status_t model_compile(nnom_model_t *m, nnom_layer_t *input, nnom_layer_t *output) +{ + size_t buf_size; + uint8_t *buf; + uint32_t layer_num = 1; + uint32_t time = nnom_ms_get(); + + NNOM_NULL_CHECK(m); + NNOM_NULL_CHECK(input); + + m->head = input; + m->tail = output; + if (output == NULL) + m->tail = find_last(input); + + NNOM_LOG("NNoM version %d.%d.%d\n", NNOM_MAJORVERSION, NNOM_SUBVERSION, NNOM_REVISION); + NNOM_LOG("To disable logs, please void the marco 'NNOM_LOG(...)' in 'nnom_port.h'.\n"); + #ifdef NNOM_USING_CHW + NNOM_LOG("Data format: Channel first (CHW)\n"); + #else + NNOM_LOG("Data format: Channel last (HWC)\n"); + #endif + #ifdef NNOM_USING_CMSIS_NN + NNOM_LOG("Backend optimization: CMSIS-NN\n"); + #endif + #ifdef NNOM_USING_STATIC_MEMORY + NNOM_LOG("Static memory size set to: %d\n", (uint32_t)nnom_static_buf_size); + #endif + NNOM_LOG("Start compiling model...\n"); + NNOM_LOG("Layer(#) Activation output shape ops(MAC) mem(in, out, buf) mem blk lifetime\n"); + NNOM_LOG("-------------------------------------------------------------------------------------------------\n"); + + // compile layers, started from list head, nested run till the end of models + compile_layers(m->head, m->head, m->blocks, &layer_num); + + NNOM_LOG("-------------------------------------------------------------------------------------------------\n"); + + // if model's tail is not the last layer which built by user. + if (output->type != NNOM_OUTPUT) + NNOM_LOG("WARNING: the last layer '%s' is not the Output Layer, please check carefully.\n", + default_layer_names[output->type]); + + // get the total (aligned) memory requirement + buf_size = mem_analysis_result(m); + + // allocate one big memory block + buf = nnom_mem(buf_size); + if (buf == NULL) + { + NNOM_LOG("ERROR: No enough memory for network buffer, required %d bytes\n", (uint32_t)buf_size); + return NN_NO_MEMORY; + } + // all memory cost + NNOM_LOG(" Total memory occupied: %d bytes\n", (uint32_t)nnom_memory_taken); + + // split the memory for every memory block + block_mem_set(m, buf); + + // experimental: set memory from io to the io tensor + tensor_mem_set(m); + + // finally set the output buff to tailed activation on each layer + set_tailed_activation(m); + + // calculate the total operations and set it to the model + model_set_ops(m); + + // print the time. + if(nnom_ms_get()) + NNOM_LOG("Compling done in %d ms\n", nnom_ms_get() - time); + + return NN_SUCCESS; +} + +// This is a simplified API for compile models with sequencial model only +// this does not require specified Input / Output layers +nnom_status_t sequencial_compile(nnom_model_t *m) +{ + nnom_layer_t *input, *output; + input = m->head; + output = find_last(input); + return model_compile(m, input, output); +} + +// run that layer +nnom_status_t layer_run(nnom_layer_t *layer) +{ + nnom_status_t result; + uint32_t start; + NNOM_NULL_CHECK(layer); + + // start + start = nnom_us_get(); + // run main layer first + result = layer->run(layer); + // run tailed-activation if it is presented + if (layer->actail != NULL) + { + layer->actail->run(layer->actail); + } + // done + layer->stat.time = nnom_us_get() - start; + return result; +} + +// run the model, until the end_layer. If end_layer == NULL, run all layers. +nnom_status_t model_run_to(nnom_model_t *m, nnom_layer_t *end_layer) +{ + uint32_t layer_num = 1; + nnom_status_t result; + nnom_layer_t *layer; + NNOM_NULL_CHECK(m); + NNOM_NULL_CHECK(m->head); + + layer = m->head; + + // using shortcut run + while (layer) + { + // run layer + result = layer_run(layer); + if (result != NN_SUCCESS) + { + NNOM_LOG("Error: #%d %s layer return error code:%d\n", layer_num, default_layer_names[layer->type], result); + return result; + } + // run callback + if(m->layer_callback != NULL) + { + result = m->layer_callback(m, layer); + if (result != NN_SUCCESS) + { + NNOM_LOG("Error: Callback return error code %d at #%d %s layer\n", result, layer_num, default_layer_names[layer->type]); + return result; + } + } + // check if finished + if (layer == end_layer || layer->shortcut == NULL) + break; + layer = layer->shortcut; + layer_num++; + } + + return NN_SUCCESS; +} + +// run all layers. +nnom_status_t model_run(nnom_model_t *m) +{ + return model_run_to(m, NULL); +} + +// callback, called after each layer has finished the calculation. +nnom_status_t model_set_callback(nnom_model_t *m, nnom_status_t (*layer_callback)(nnom_model_t *m, nnom_layer_t *layer)) +{ + if(m->layer_callback != NULL && m->layer_callback != layer_callback) + return NN_LENGTH_ERROR; + + m->layer_callback = layer_callback; + return NN_SUCCESS; +} + +// delete callback. +void model_delete_callback(nnom_model_t *m) +{ + m->layer_callback = NULL; +} + +nnom_status_t check_model_version(unsigned long model_version) +{ + nnom_status_t result = NN_SUCCESS; + int32_t major, sub, rev; + major = model_version/10000; + sub = (model_version/100)%100; + rev = model_version % 100; + if(model_version != NNOM_VERSION) + { + NNOM_LOG("WARNING: model version %d.%d.%d dosen't match nnom version!\n", major, sub, rev); + result = -NN_ARGUMENT_ERROR; + } + else + { + NNOM_LOG("Model version: %d.%d.%d\n", major, sub, rev); + } + return result; +} + + diff --git a/components/ai/nnom/src/core/nnom_layers.c b/components/ai/nnom/src/core/nnom_layers.c new file mode 100644 index 000000000..dc059074a --- /dev/null +++ b/components/ai/nnom/src/core/nnom_layers.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-02-05 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" + +size_t shape_size(nnom_3d_shape_t *s) +{ + if (s == NULL) + return 0; + return s->h * s->w * s->c; +} + +nnom_3d_shape_t shape(size_t h, size_t w, size_t c) +{ + nnom_3d_shape_t s; + s.h = h; + s.w = w; + s.c = c; + return s; +} +nnom_3d_shape_t kernel(size_t h, size_t w) +{ + return shape(h, w, 1); +} +nnom_3d_shape_t stride(size_t h, size_t w) +{ + return shape(h, w, 1); +} +nnom_3d_shape_t dilation(size_t h, size_t w) +{ + return shape(h, w, 1); +} + +nnom_border_t border(size_t top, size_t bottom, size_t left, size_t right) +{ + nnom_border_t b; + b.top = top; + b.bottom = bottom; + b.left = left; + b.right = right; + return b; +} + +// this function has to be used while assign a io for a layer. +// because the io needs to know who is its owner. +nnom_layer_io_t *io_init(void *owner_layer, nnom_layer_io_t *io) +{ + io->owner = (nnom_layer_t *)owner_layer; + return io; +} + +// this function is to add a new IO to current inited IO +// input, the targeted IO that the new IO will be added to +// output , the new IO +nnom_layer_io_t *io_add_aux(nnom_layer_io_t *targeted_io) +{ + nnom_layer_io_t *new_io; + // check if the targeted io is inited, and its aux = NULL + if (targeted_io == NULL || targeted_io->owner == NULL || targeted_io->aux != NULL) + return NULL; + // create new io, init it + new_io = nnom_mem(sizeof(nnom_layer_io_t)); + if (new_io == NULL) + return NULL; + // add to aux + targeted_io->aux = new_io; + return io_init(targeted_io->owner, new_io); +} diff --git a/components/ai/nnom/src/core/nnom_tensor.c b/components/ai/nnom/src/core/nnom_tensor.c new file mode 100644 index 000000000..7d9026475 --- /dev/null +++ b/components/ai/nnom/src/core/nnom_tensor.c @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-02-05 Jianjia Ma The first version + * 2019-02-14 Jianjia Ma Add layer.free() method. + */ + +#include +#include +#include +#include +#include "nnom.h" +#include "nnom_tensor.h" + + // tensor size +size_t tensor_size(nnom_tensor_t* t) +{ + size_t size = 0; + if (t != NULL) + { + size = t->dim[0]; + for (int i = 1; i < t->num_dim; i++) + size *= t->dim[i]; + } + return size; +} +size_t tensor_size_byte(nnom_tensor_t* t) +{ + return tensor_size(t)*t->bitwidth/8; +} + + +size_t tensor_get_num_channel(nnom_tensor_t* t) +{ + // this will need to be changed to support batch. +#ifdef NNOM_USING_CHW + // channel first + //return t->dim[0]; + return t->dim[t->num_dim -1]; // we are always using hwc to describe even our data is in CHW +#else + // channel last + return t->dim[t->num_dim -1]; +#endif +} + +// initialise/create new tensor +nnom_tensor_t* new_tensor(nnom_qtype_t type, uint32_t num_dim, uint32_t num_channel) +{ + nnom_tensor_t* t = NULL; + uint32_t q_len; + if(type == NNOM_QTYPE_PER_AXIS) + { + q_len = num_channel; + } + else if (type == NNOM_QTYPE_PER_TENSOR) + { + q_len = 1; + } + else + { + NNOM_LOG("ERROR: tensor type not specified\n"); + return NULL; + } + + t = nnom_mem(nnom_alignto(sizeof(nnom_tensor_t), NNOM_ALIGN) + + num_dim*sizeof(nnom_shape_data_t) + + q_len*sizeof(nnom_qformat_param_t)*2); + if(t == NULL) + return t; + t->dim = (nnom_shape_data_t*)((uint8_t*)t + sizeof(nnom_tensor_t)); // should add alignment + t->q_dec = (nnom_qformat_param_t*)((uint8_t*)t->dim + num_dim*sizeof(nnom_shape_data_t)); + t->q_offset = (nnom_qformat_param_t*)((uint8_t*)t->q_dec + q_len*sizeof(nnom_qformat_param_t)); + t->num_dim = num_dim; + t->qtype = type; + + return t; +} + +void delete_tensor(nnom_tensor_t* t) +{ + if (t) + nnom_free(t); +} + +// set tensor by value +// for tensor with quantized type NNOM_QTYPE_PER_TENSOR +nnom_tensor_t* tensor_set_attr_v(nnom_tensor_t* t, + nnom_qformat_param_t dec_bit, nnom_qformat_param_t offset, nnom_shape_data_t* dim, uint32_t num_dim, uint8_t bitwidth) +{ + // copy dim + t->num_dim = num_dim; + nnom_memcpy(t->dim, dim, sizeof(nnom_shape_data_t) * num_dim); + + // bitwidth + t->bitwidth = bitwidth; + // copy the offset and q format + *(t->q_dec) = dec_bit; + *(t->q_offset) = offset; + return t; +} + + +// set tensor by pointer +// for tensor with quantized type NNOM_QTYPE_PER_AXIS +nnom_tensor_t* tensor_set_attr(nnom_tensor_t* t, + nnom_qformat_param_t*dec_bit, nnom_qformat_param_t *offset, nnom_shape_data_t* dim, uint32_t num_dim, uint8_t bitwidth) +{ + size_t size; + + // copy dim + t->num_dim = num_dim; + nnom_memcpy(t->dim, dim, sizeof(nnom_shape_data_t) * num_dim); + + // get the q format data size + if(t->qtype == NNOM_QTYPE_PER_AXIS) + size = sizeof(nnom_qformat_param_t) * tensor_get_num_channel(t); + else + size = sizeof(nnom_qformat_param_t); + + // bitwidth + t->bitwidth = bitwidth; + // copy the offset and q format + nnom_memcpy(t->q_dec, dec_bit, size); + nnom_memcpy(t->q_offset, offset, size); + return t; +} + +// this method copy the attributes of a tensor to a new tensor +// before that, src and des tensor must already have QTYPE and NUM_OF_DIM set. +// Note, the tensors must have the same lenght. this method wont cpy the memory pointer data (we will assign memory later after building) +nnom_tensor_t* tensor_cpy_attr(nnom_tensor_t* des, nnom_tensor_t* src) +{ + size_t size; + if(src->qtype != des->qtype || src->num_dim != des->num_dim) + return NULL; + + if(src->qtype == NNOM_QTYPE_PER_AXIS) + size = sizeof(nnom_qformat_param_t) * tensor_get_num_channel(src); + else + size = sizeof(nnom_qformat_param_t); + + // bit + des->bitwidth = src->bitwidth; + // copy quantisation parameters + nnom_memcpy(des->q_dec, src->q_dec, size); + nnom_memcpy(des->q_offset, src->q_offset, size); + + // copy number of dimension + des->num_dim = src->num_dim; + nnom_memcpy(des->dim, src->dim, src->num_dim * sizeof(nnom_shape_data_t)); + return des; +} + +// change format from CHW to HWC +// the shape of the data, input data, output data +void tensor_hwc2chw_q7(nnom_tensor_t* des, nnom_tensor_t* src) +{ + q7_t* p_out = des->p_data; + q7_t* p_in = src->p_data; + + for (int c = 0; c < src->dim[2]; c++) + { + for (int h = 0; h < src->dim[0]; h++) + { + for (int w = 0; w < src->dim[1]; w++) + { + *p_out = p_in[(h * src->dim[1] + w) * src->dim[2] + c]; + p_out++; + } + } + } +} + + +// only support 3d tensor +// change format from CHW to HWC +void tensor_chw2hwc_q7(nnom_tensor_t* des, nnom_tensor_t* src) +{ + q7_t* p_out = des->p_data; + q7_t* p_in = src->p_data; + int im_size; + int h_step; + + im_size = src->dim[0] * src->dim[1]; // H*W + + for (int h = 0; h < src->dim[0]; h++) + { + h_step = src->dim[1] * h; + for (int w = 0; w < src->dim[1]; w++) + { + for (int c = 0; c < src->dim[2]; c++) + { + *p_out = p_in[im_size * c + h_step + w]; + p_out++; + } + } + } + +} + +// (deprecated by tensor_hwc2chw version) +// change format from CHW to HWC +// the shape of the data, input data, output data +void hwc2chw_q7(nnom_3d_shape_t shape, q7_t* p_in, q7_t* p_out) +{ + for (int c = 0; c < shape.c; c++) + { + for (int h = 0; h < shape.h; h++) + { + for (int w = 0; w < shape.w; w++) + { + *p_out = p_in[(h * shape.w + w) * shape.c + c]; + p_out++; + } + } + } +} + +// (deprecated) +// change format from CHW to HWC +// the shape of the data, input data, output data +void chw2hwc_q7(nnom_3d_shape_t shape, q7_t* p_in, q7_t* p_out) +{ + int im_size = shape.w * shape.h; + int h_step; + + for (int h = 0; h < shape.h; h++) + { + h_step = shape.w * h; + for (int w = 0; w < shape.w; w++) + { + for (int c = 0; c < shape.c; c++) + { + *p_out = p_in[im_size * c + h_step + w]; + p_out++; + } + } + } +} diff --git a/components/ai/nnom/src/core/nnom_utils.c b/components/ai/nnom/src/core/nnom_utils.c new file mode 100644 index 000000000..3b13c3551 --- /dev/null +++ b/components/ai/nnom/src/core/nnom_utils.c @@ -0,0 +1,417 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-02-05 Jianjia Ma The first version + */ + +#include +#include +#include +#include +#include "nnom.h" +#include "nnom_utils.h" + +static nnom_predict_t *_predict_create_instance(nnom_model_t *m, size_t label_num, size_t top_k_size) +{ + nnom_predict_t *pre; + // allocate memory + pre = (nnom_predict_t *)nnom_malloc(sizeof(nnom_predict_t)); + if(pre == NULL) + return NULL; + pre->top_k = (uint32_t *)nnom_malloc(top_k_size * sizeof(uint32_t)); + pre->confusion_mat = (uint16_t *)nnom_malloc(label_num * label_num * sizeof(uint16_t)); + if(pre->top_k == NULL || pre->confusion_mat == NULL) + { + nnom_free(pre->top_k); nnom_free(pre->confusion_mat); nnom_free(pre); + return NULL; + } + nnom_memset(pre->top_k, 0, top_k_size * sizeof(uint32_t)); + nnom_memset(pre->confusion_mat, 0, label_num * label_num * sizeof(uint16_t)); + + // config + pre->label_num = label_num; + pre->top_k_size = top_k_size; + pre->predict_count = 0; + + // run + pre->model = m; + pre->t_run_total = 0; // model running time in total + pre->t_predict_start = 0; // when it is initial + pre->t_predict_total = 0; // total time of the whole test + + return pre; +} + +static void _predict_delete_instance(nnom_predict_t *pre) +{ + if(pre == NULL) + return; + nnom_free(pre->top_k); + nnom_free(pre->confusion_mat); + nnom_free(pre); +} + +// create a prediction +// input model, the buf pointer to the softwmax output (Temporary, this can be extract from model) +// the size of softmax output (the num of lable) +// the top k that wants to record. +nnom_predict_t *prediction_create(nnom_model_t *m, int8_t *buf_prediction, size_t label_num, size_t top_k_size) +{ + nnom_predict_t *pre = _predict_create_instance(m, label_num, top_k_size); + if (!pre) + return NULL; + if (!m) + { + _predict_delete_instance(pre); + return NULL; + } + + // set the output buffer of model to the prediction instance + pre->buf_prediction = buf_prediction; + + // mark start time. + pre->t_predict_start = nnom_ms_get(); + + return pre; +} + +// after a new data is set in input +// feed data to prediction +// input the current label, (range from 0 to total number of label -1) +// (the current input data should be set by user manully to the input buffer of the model.) +nnom_status_t prediction_run(nnom_predict_t *pre, uint32_t true_label, uint32_t*predict_label, float* prob) +{ + int max_val; + int max_index; + uint32_t true_ranking = 0; + uint32_t start; + uint32_t sum = 0; + + if (!pre) + return NN_ARGUMENT_ERROR; + + // now run model + start = nnom_ms_get(); + model_run(pre->model); + pre->t_run_total += nnom_ms_get() - start; + + // only draw matrix and top k when number of label > 1 + if (pre->label_num > 1) + { + // find how many prediction is bigger than the ground true. + // Raning rules, same as tensorflow. however, predictions in MCU is more frequencly to have equal probability since it is using fixed-point. + // if ranking is 1, 2, =2(true), 4, 5, 6. the result will be top 3. + // if ranking is 1, 2(true), =2, 4, 5, 6. the result will be top 2. + // find the ranking of the prediced label. + for (uint32_t j = 0; j < pre->label_num; j++) + { + if (j == true_label) + continue; + if (pre->buf_prediction[true_label] < pre->buf_prediction[j]) + true_ranking++; + // while value[label] = value[j]. only when label > j, label is the second of j + else if (pre->buf_prediction[true_label] == pre->buf_prediction[j] && j < true_label) + true_ranking++; + } + + if (true_ranking < pre->top_k_size) + pre->top_k[true_ranking]++; + + // Find top 1 and return the current prediction. + // If there are several maximum prediction, return the first one. + max_val = pre->buf_prediction[0]; + max_index = 0; + for (uint32_t j = 1; j < pre->label_num; j++) + { + if (pre->buf_prediction[j] > max_val) + { + max_val = pre->buf_prediction[j]; + max_index = j; + } + sum += pre->buf_prediction[j]; + } + // result + if (max_val != 0) + *prob = (float)max_val / 127.f; + else + *prob = 0; + *predict_label = max_index; + + // fill confusion matrix + pre->confusion_mat[true_label * pre->label_num + max_index] += 1; + } + // only one neural as output. + else + { + *prob = (float)pre->buf_prediction[0] / 127.f; + if (*prob >= 0.5f) + *predict_label = 1; + else + *predict_label = 0; + } + + // prediction count + pre->predict_count++; + + // return the prediction + return NN_SUCCESS; +} + +void prediction_end(nnom_predict_t *pre) +{ + if (!pre) + return; + pre->t_predict_total = nnom_ms_get() - pre->t_predict_start; +} + +void prediction_delete(nnom_predict_t *pre) +{ + _predict_delete_instance(pre); +} + +void prediction_matrix(nnom_predict_t *pre) +{ + if (!pre) + return; + // print titles + NNOM_LOG("\nConfusion matrix:\n"); + NNOM_LOG("predict"); + for (int i = 0; i < pre->label_num; i++) + { + NNOM_LOG("%6d", i); + } + NNOM_LOG("\n"); + NNOM_LOG("actual\n"); + // print the matrix + for (int i = 0; i < pre->label_num; i++) + { + uint32_t row_total = 0; + + NNOM_LOG(" %3d | ", i); + for (int j = 0; j < pre->label_num; j++) + { + row_total += pre->confusion_mat[i * pre->label_num + j]; + NNOM_LOG("%6d", pre->confusion_mat[i * pre->label_num + j]); + } + NNOM_LOG(" |%4d%%\n", pre->confusion_mat[i * pre->label_num + i] * 100 / row_total); + row_total = 0; + } + NNOM_LOG("\n"); +} + +// top-k +void prediction_top_k(nnom_predict_t *pre) +{ + uint32_t top = 0; + if (!pre) + return; + + for (int i = 0; i < pre->top_k_size; i++) + { + top += pre->top_k[i]; + if (top != pre->predict_count) + NNOM_LOG("Top %d Accuracy: %d.%02d%% \n", i + 1, (top * 100) / pre->predict_count, + ((top * 100 * 100) / pre->predict_count)%100); + else + NNOM_LOG("Top %d Accuracy: 100%% \n", i + 1); + } +} + +// this function is to print sumarry +void prediction_summary(nnom_predict_t *pre) +{ + if (!pre) + return; + // sumamry + NNOM_LOG("\nPrediction summary:\n"); + NNOM_LOG("Test frames: %d\n", pre->predict_count); + NNOM_LOG("Test running time: %d sec\n", pre->t_predict_total / 1000); + NNOM_LOG("Model running time: %d ms\n", pre->t_run_total); + if(pre->predict_count !=0) + NNOM_LOG("Average prediction time: %d us\n", (pre->t_run_total * 1000) / pre->predict_count); + if(pre->t_run_total != 0) + NNOM_LOG("Average effeciency: %d.%02d ops/us\n", (int)(((uint64_t)pre->model->total_ops * pre->predict_count) / (pre->t_run_total * 1000)), + (int)(((uint64_t)pre->model->total_ops * pre->predict_count)*100 / (pre->t_run_total * 1000))%100); + if(pre->t_run_total !=0 && pre->predict_count !=0) + NNOM_LOG("Average frame rate: %d.%d Hz\n", 1000 / (pre->t_run_total / pre->predict_count), + (1000*10 / (pre->t_run_total / pre->predict_count))%10); + + // only valid for multiple labels + if(pre->label_num > 1) + { + // print top-k + prediction_top_k(pre); + + // print confusion matrix + prediction_matrix(pre); + } +} + +// stand alone prediction API +// this api test one set of data, return the prediction +nnom_status_t nnom_predict(nnom_model_t *m, uint32_t *label, float *prob) +{ + int32_t max_val, max_index, sum; + int8_t *output; + + if (!m) + return NN_ARGUMENT_ERROR; + + model_run(m); + + // get the output memory + output = m->tail->out->tensor->p_data; + + // multiple neural output + if (tensor_size(m->tail->out->tensor) > 1) + { + // Top 1 + max_val = output[0]; + max_index = 0; + sum = max_val; + for (uint32_t i = 1; i < tensor_size(m->tail->out->tensor); i++) + { + if (output[i] > max_val) + { + max_val = output[i]; + max_index = i; + } + sum += output[i]; + } + // send results + *label = max_index; + if(max_val !=0) + *prob = (float)max_val/127.f; + else + *prob = 0; + } + // single neural output + else + { + *prob = (float)output[0] / 127.f; + if (*prob >= 0.5f) + *label = 1; + else + *label = 0; + } + + return NN_SUCCESS; +} + +static void layer_stat(nnom_layer_t *layer) +{ + // layer stat + if(layer->type != NNOM_RNN) + NNOM_LOG("%-10s - ", default_layer_names[layer->type]); + else + { + NNOM_LOG("%-3s/", default_layer_names[layer->type]); + NNOM_LOG("%-6s - ", default_cell_names[((nnom_rnn_layer_t*)layer)->cell->type]); + } + NNOM_LOG(" %8d ", layer->stat.time); + + // MAC operation + if(layer->stat.macc == 0) + NNOM_LOG(" "); + else if (layer->stat.macc < 10000) + NNOM_LOG("%7d ", (uint32_t)layer->stat.macc); + else if (layer->stat.macc < 1000*1000) + NNOM_LOG("%6dk ", (uint32_t)(layer->stat.macc/1000)); + else if (layer->stat.macc < 1000*1000*1000) + NNOM_LOG("%3d.%02dM ", (uint32_t)(layer->stat.macc/(1000*1000)), (uint32_t)(layer->stat.macc%(1000*1000)/(10*1000))); // xxx.xx M + else + NNOM_LOG("%3d.%02dG ", (uint32_t)(layer->stat.macc/(1000*1000*1000)), (uint32_t)(layer->stat.macc%(1000*1000*1000)/(10*1000*1000))); // xxx.xx G + + // layer efficiency + if (layer->stat.macc != 0 && layer->stat.time != 0) + NNOM_LOG("%d.%02d\n", (uint32_t)(layer->stat.macc / layer->stat.time), (uint32_t)((layer->stat.macc * 100) / (layer->stat.time) % 100)); + else + NNOM_LOG("\n"); +} + +void model_stat(nnom_model_t *m) +{ + size_t total_ops = 0; + size_t total_time = 0; + nnom_layer_t *layer; + uint32_t run_num = 0; + + if (!m) + return; + + layer = m->head; + + NNOM_LOG("\nPrint running stat..\n"); + NNOM_LOG("Layer(#) - Time(us) ops(MACs) ops/us \n"); + NNOM_LOG("--------------------------------------------------------\n"); + while (layer) + { + run_num++; + NNOM_LOG("#%-3d", run_num); + total_ops += layer->stat.macc; + total_time += layer->stat.time; + layer_stat(layer); + if (layer->shortcut == NULL) + break; + layer = layer->shortcut; + } + NNOM_LOG("\nSummary:\n"); + NNOM_LOG("Total ops (MAC): %d", (uint32_t)(total_ops)); + NNOM_LOG("(%d.%02dM)\n", (uint32_t) (total_ops/(1000*1000)), (uint32_t)(total_ops%(1000*1000)/(10000))); + NNOM_LOG("Prediction time :%dus\n", (uint32_t)total_time); + if(total_time != 0) + NNOM_LOG("Efficiency %d.%02d ops/us\n", + (uint32_t)(total_ops / total_time), + (uint32_t)((total_ops * 100) / (total_time) % 100)); + + NNOM_LOG("Total memory:%d\n", (uint32_t)nnom_mem_stat()); +} + +void model_io_format(nnom_model_t *m) +{ + nnom_layer_t *layer; + uint32_t run_num = 0; + + if (!m) + return; + + layer = m->head; + + NNOM_LOG("\nPrint layer input/output..\n"); + NNOM_LOG("Layer(#) - Input(Qnm) Output(Qnm) Oshape \n"); + NNOM_LOG("----------------------------------------------------------\n"); + while (layer) + { + run_num++; + NNOM_LOG("#%-3d", run_num); + if(layer->type != NNOM_RNN) + NNOM_LOG("%-10s - ", default_layer_names[layer->type]); + else + { + NNOM_LOG("%-3s/", default_layer_names[layer->type]); + NNOM_LOG("%-6s - ", default_cell_names[((nnom_rnn_layer_t*)layer)->cell->type]); + } + NNOM_LOG(" %2d.%2d", 7-layer->in->tensor->q_dec[0], layer->in->tensor->q_dec[0]); + NNOM_LOG(" %2d.%2d", 7-layer->out->tensor->q_dec[0], layer->out->tensor->q_dec[0]); + NNOM_LOG(" ("); + for (int i = 0; i < 3; i++) + { + if (layer->out->tensor->num_dim > i) + NNOM_LOG("%4d,", layer->out->tensor->dim[i]); + else + NNOM_LOG(" "); + } + NNOM_LOG(")\n"); + + if (layer->shortcut == NULL) + break; + layer = layer->shortcut; + } + +} diff --git a/components/ai/nnom/src/layers/nnom_activation.c b/components/ai/nnom/src/layers/nnom_activation.c new file mode 100644 index 000000000..c90171c77 --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_activation.c @@ -0,0 +1,369 @@ + + +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_activation.h" + +#ifdef NNOM_USING_CMSIS_NN +#include "arm_math.h" +#include "arm_nnfunctions.h" +#endif + +nnom_layer_t *Activation(nnom_activation_t *act) +{ + nnom_activation_layer_t *layer; + nnom_layer_io_t *in, *out; + + // apply a block memory for all the sub handles. + size_t mem_size = sizeof(nnom_activation_layer_t) + sizeof(nnom_layer_io_t) * 2; + layer = nnom_mem(mem_size); + if (layer == NULL) + return NULL; + + // distribut the memory to sub handles. + in = (void *)((uint8_t*)layer + sizeof(nnom_activation_layer_t)); + out = (void *)((uint8_t*)in + sizeof(nnom_layer_io_t)); + + // set type in layer parent + layer->super.type = NNOM_ACTIVATION; + layer->super.run = activation_run; + layer->super.build = default_build; + // set buf state + in->type = NNOM_TENSOR_BUF_TEMP; + out->type = NNOM_TENSOR_BUF_NULL; // when a layer's io is set to NULL, both will point to same mem. + // put in & out on the layer. + layer->super.in = io_init(layer, in); + layer->super.out = io_init(layer, out); + + // set activation to layer + layer->act = act; + + // set free method + layer->super.free = activation_free; + + return (nnom_layer_t *)layer; +} + +nnom_layer_t *ReLU(void) +{ + nnom_layer_t *layer = Activation(act_relu()); + if (layer == NULL) + return NULL; + + // set type in layer parent + layer->type = NNOM_RELU; + return layer; +} + +nnom_layer_t *LeakyReLU(float alpha) +{ + nnom_layer_t *layer = Activation(act_leaky_relu(alpha)); + if (layer == NULL) + return NULL; + + // set type in layer parent + layer->type = NNOM_LEAKY_RELU; + return layer; +} + +nnom_layer_t *AdvReLU(float alpha, float max, float threshold) +{ + nnom_layer_t *layer = Activation(act_adv_relu(alpha, max, threshold)); + if (layer == NULL) + return NULL; + + // set type in layer parent + layer->type = NNOM_ADV_RELU; + return layer; +} + +nnom_layer_t *Sigmoid(int32_t dec_bit) +{ + nnom_layer_t *layer = Activation(act_sigmoid(dec_bit)); + if (layer == NULL) + return NULL; + + // set type in layer parent + layer->type = NNOM_SIGMOID; + return layer; +} + +nnom_layer_t *TanH(int32_t dec_bit) +{ + nnom_layer_t *layer = Activation(act_tanh(dec_bit)); + if (layer == NULL) + return NULL; + // set type in layer parent + layer->type = NNOM_TANH; + return layer; +} + +void act_delete(nnom_activation_t* act){ + nnom_free(act); +} + +// activation takes act instance which is created. therefore, it must be free when activation is deleted. +// this is the callback in layer->free +nnom_status_t activation_free(nnom_layer_t *layer) +{ + if(layer) + act_delete(((nnom_activation_layer_t *)layer)->act); + return NN_SUCCESS; +} + +nnom_status_t activation_run(nnom_layer_t *layer) +{ + nnom_activation_layer_t *cl = (nnom_activation_layer_t *)layer; + return act_tensor_run(cl->act, layer->in->tensor); +} + +// porting +static nnom_status_t relu_run(nnom_activation_t* act) +{ + if(act->tensor->bitwidth == 16) + { + #ifdef NNOM_USING_CMSIS_NN + arm_relu_q15(act->tensor->p_data, tensor_size(act->tensor)); + #else + local_relu_q15(act->tensor->p_data, tensor_size(act->tensor)); + #endif + } + else + { + #ifdef NNOM_USING_CMSIS_NN + arm_relu_q7(act->tensor->p_data, tensor_size(act->tensor)); + #else + local_relu_q7(act->tensor->p_data, tensor_size(act->tensor)); + #endif + } + return NN_SUCCESS; +} + +// leaky relu +static nnom_status_t leaky_relu_run(nnom_activation_t* act) +{ + nnom_activation_leaky_relu_t* a = (nnom_activation_leaky_relu_t*) act; + if(act->tensor->bitwidth == 16) + local_leaky_relu_q15(act->tensor->p_data, a->alpha, tensor_size(act->tensor)); + else + local_leaky_relu_q7(act->tensor->p_data, a->alpha, tensor_size(act->tensor)); + return NN_SUCCESS; +} + +// advance relu +static nnom_status_t adv_relu_run(nnom_activation_t* act) +{ + nnom_activation_adv_relu_t* a = (nnom_activation_adv_relu_t*) act; + + // we need to convert float to fixpoint in runtime where we can know the tensor's q format + if(act->tensor->bitwidth == 16) + { + q15_t max = 32767; + q15_t threshold = MIN(a->threshold * (1 << (15 - act->tensor->q_dec[0])), 32767); + q7_t max_scale = (1 << (15 - act->tensor->q_dec[0])); + if(a->max != INFINITY && a->max != 0x7fc00000) + if(a->max * max_scale < max) + max = a->max * max_scale; + local_adv_relu_q15(act->tensor->p_data, a->negative_slope, max, threshold, tensor_size(act->tensor)); + } + // 8bit + else + { + q7_t max = 127; + q7_t threshold = MIN(a->threshold * (1 << (7 - act->tensor->q_dec[0])), 127); + q7_t max_scale = (1 << (7 - act->tensor->q_dec[0])); + if(a->max != INFINITY && a->max != 0x7fc00000) // QNAN 0x7fc00000 also represent infinity in script 0.4.1 + if(a->max * max_scale < max) + max = a->max * max_scale; + local_adv_relu_q7(act->tensor->p_data, a->negative_slope, max, threshold, tensor_size(act->tensor)); + } + + return NN_SUCCESS; +} + +static nnom_status_t tanh_run(nnom_activation_t* act) +{ + nnom_activation_fixed_q_t * a = (nnom_activation_fixed_q_t*)act; + // 16 bit + if(act->tensor->bitwidth == 16) + { + uint8_t int_bit = 15 - a->dec_bit; + #ifdef NNOM_USING_CMSIS_NN + arm_nn_activations_direct_q15(act->tensor->p_data, tensor_size(act->tensor), int_bit, ARM_TANH); + #else + local_tanh_q15(act->tensor->p_data, tensor_size(act->tensor), int_bit); + #endif + } + else // 8bit + { + uint8_t int_bit = 7 - a->dec_bit; + // arm version cannot handle int_bit > 3 + #ifdef NNOM_USING_CMSIS_NN + if(act->tensor->q_dec[0] <= 3) + arm_nn_activations_direct_q7(act->tensor->p_data, tensor_size(act->tensor), int_bit, ARM_TANH); + else + #endif + local_tanh_q7(act->tensor->p_data, tensor_size(act->tensor), int_bit); + } + return NN_SUCCESS; +} + +static nnom_status_t sigmoid_run( nnom_activation_t* act) +{ + nnom_activation_fixed_q_t * a = (nnom_activation_fixed_q_t*)act; + // 16 bit + if(act->tensor->bitwidth == 16) + { + uint8_t int_bit = 15 - a->dec_bit; + #ifdef NNOM_USING_CMSIS_NN + arm_nn_activations_direct_q15(act->tensor->p_data, tensor_size(act->tensor), int_bit, ARM_SIGMOID); + #else + local_sigmoid_q15(act->tensor->p_data, tensor_size(act->tensor), int_bit); + #endif + } + else // 8bit + { + uint8_t int_bit = 7 - a->dec_bit; + // arm version cannot handle int_bit > 3 + #ifdef NNOM_USING_CMSIS_NN + if(act->tensor->q_dec[0] <= 3) + arm_nn_activations_direct_q7(act->tensor->p_data, tensor_size(act->tensor), int_bit, ARM_TANH); + else + #endif + local_sigmoid_q7(act->tensor->p_data, tensor_size(act->tensor), int_bit); + } + + return NN_SUCCESS; +} + +static nnom_status_t hard_tanh_run( nnom_activation_t* act) +{ + nnom_activation_fixed_q_t * a = (nnom_activation_fixed_q_t*)act; + if(act->tensor->bitwidth == 16) + local_hard_tanh_q15(act->tensor->p_data, tensor_size(act->tensor), a->dec_bit + 8); // a->dec is based on 8 bit. + else + local_hard_tanh_q7(act->tensor->p_data, tensor_size(act->tensor), a->dec_bit); + return NN_SUCCESS; +} + +static nnom_status_t hard_sigmoid_run( nnom_activation_t* act) +{ + nnom_activation_fixed_q_t * a = (nnom_activation_fixed_q_t*)act; + if(act->tensor->bitwidth == 16) + local_hard_sigmoid_q15(act->tensor->p_data, tensor_size(act->tensor), a->dec_bit + 8); // a->dec is based on 8 bit. + else + local_hard_sigmoid_q7(act->tensor->p_data, tensor_size(act->tensor), a->dec_bit); + return NN_SUCCESS; +} + +// +nnom_activation_t* act_relu(void) +{ + nnom_activation_t* act = nnom_mem(sizeof(nnom_activation_t)); + act->run = relu_run; + act->type = ACT_RELU; + return act; +} + +nnom_activation_t* act_leaky_relu(float alpha) +{ + nnom_activation_leaky_relu_t* act = nnom_mem(sizeof(nnom_activation_leaky_relu_t)); + act->super.run = leaky_relu_run; + act->super.type = ACT_LEAKY_RELU; + act->alpha = (q7_t)(alpha*128); + return (nnom_activation_t* )act; +} + +nnom_activation_t* act_adv_relu(float negative_slope, float max, float threshold) +{ + nnom_activation_adv_relu_t* act = nnom_mem(sizeof(nnom_activation_adv_relu_t)); + act->super.run = adv_relu_run; + act->super.type = ACT_ADV_RELU; + act->negative_slope = (q7_t)(negative_slope*128); + act->max = max; + act->threshold = threshold; + return (nnom_activation_t* )act; +} + +nnom_activation_t* act_tanh(int32_t dec_bit) +{ + nnom_activation_fixed_q_t* act = nnom_mem(sizeof(nnom_activation_fixed_q_t)); + act->super.run = tanh_run; + act->super.type = ACT_TANH; + act->dec_bit = dec_bit; + return (nnom_activation_t*)act; +} + +nnom_activation_t* act_sigmoid(int32_t dec_bit) +{ + nnom_activation_fixed_q_t* act = nnom_mem(sizeof(nnom_activation_fixed_q_t)); + + act->super.run = sigmoid_run; + act->super.type = ACT_SIGMOID; + act->dec_bit = dec_bit; + return (nnom_activation_t*)act; +} + +nnom_activation_t* act_hard_tanh(int32_t dec_bit) +{ + nnom_activation_fixed_q_t* act = nnom_mem(sizeof(nnom_activation_fixed_q_t)); + + act->super.run = hard_tanh_run; + act->super.type = ACT_HARD_TANH; + act->dec_bit = dec_bit; + return (nnom_activation_t*)act; +} + +nnom_activation_t* act_hard_sigmoid(int32_t dec_bit) +{ + nnom_activation_fixed_q_t* act = nnom_mem(sizeof(nnom_activation_fixed_q_t)); + + act->super.run = hard_sigmoid_run; + act->super.type = ACT_HARD_SIGMOID; + act->dec_bit = dec_bit; + return (nnom_activation_t*)act; +} + +// return the decimal bit if the activation will change the q format of the layer. +int32_t act_get_dec_bit(nnom_activation_type_t type, int32_t dec_bit) +{ + switch(type) + { + case ACT_RELU: + case ACT_LEAKY_RELU: + case ACT_ADV_RELU: + break; + case ACT_TANH: + case ACT_HARD_TANH: + case ACT_SIGMOID: + case ACT_HARD_SIGMOID: + dec_bit = 7; + default:break; + } + return dec_bit; +} + +// a direct api to run activate a tensor +nnom_status_t act_tensor_run(nnom_activation_t* act, nnom_tensor_t* tensor) +{ + act->tensor = tensor; + return act->run(act); +} diff --git a/components/ai/nnom/src/layers/nnom_avgpool.c b/components/ai/nnom/src/layers/nnom_avgpool.c new file mode 100644 index 000000000..8ee220f4c --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_avgpool.c @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_avgpool.h" + +#ifdef NNOM_USING_CMSIS_NN +#include "arm_math.h" +#include "arm_nnfunctions.h" +#endif + +nnom_layer_t *avgpool_s(const nnom_pool_config_t * config) +{ + nnom_avgpool_layer_t *cl; + + if(config->num_dim == 1) + { + cl = (nnom_avgpool_layer_t *)AvgPool(kernel(1, config->kernel_size[0]), + stride(1, config->stride_size[0]), + config->padding_type); + } + else + { + cl = (nnom_avgpool_layer_t *)AvgPool(kernel(config->kernel_size[0], config->kernel_size[1]), + stride(config->stride_size[0], config->stride_size[1]), + config->padding_type); + } + + if(cl) + { + cl->super.config = (void*) config; + cl->output_shift = config->output_shift; // no idea if we need it + } + return (nnom_layer_t *)cl; +} + +nnom_layer_t *AvgPool(nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_padding_t pad_type) +{ + nnom_layer_t *layer = MaxPool(k, s, pad_type); + + if (layer != NULL) + { + layer->type = NNOM_AVGPOOL; + layer->run = avgpool_run; + layer->build = avgpool_build; + } + return (nnom_layer_t *)layer; +} + +nnom_status_t avgpool_build(nnom_layer_t *layer) +{ + uint32_t size; + // avg pooling share the same output shape, stride, padding setting. + maxpool_build(layer); + + #ifdef NNOM_USING_CMSIS_NN + // however, avg pooling require a computational buffer. + // bufferA size: 2*dim_im_out*ch_im_in + size = layer->out->tensor->dim[1] > layer->out->tensor->dim[0] ? + layer->out->tensor->dim[1] : layer->out->tensor->dim[0]; + layer->comp->size = 2 * size * layer->in->tensor->dim[2]; + #endif + + return NN_SUCCESS; +} + +nnom_status_t avgpool_run(nnom_layer_t *layer) +{ + nnom_avgpool_layer_t *cl = (nnom_avgpool_layer_t *)(layer); + uint16_t out_x, out_y; + // if global pooling + if(layer->out->tensor->num_dim == 1) + { + out_x = 1; out_y = 1; + } + else // normal pooling. + { + out_x = layer->out->tensor->dim[1]; //W + out_y = layer->out->tensor->dim[0]; //h + } + + // 16 bit + if(layer->in->tensor->bitwidth == 16) + { +#ifdef NNOM_USING_CHW + local_avepool_q15_CHW(layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->kernel.w, cl->kernel.h, + cl->pad.w, cl->pad.h, + cl->stride.w, cl->stride.h, + out_x, out_y, + cl->output_shift, + NULL, + layer->out->tensor->p_data); +#else + local_avepool_q15_HWC(layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->kernel.w, cl->kernel.h, + cl->pad.w, cl->pad.h, + cl->stride.w, cl->stride.h, + out_x, out_y, + cl->output_shift, + NULL, + layer->out->tensor->p_data); +#endif + } + // 8bit + else{ +#ifdef NNOM_USING_CHW + local_avepool_q7_CHW(layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->kernel.w, cl->kernel.h, + cl->pad.w, cl->pad.h, + cl->stride.w, cl->stride.h, + out_x, out_y, + cl->output_shift, + NULL, + layer->out->tensor->p_data); +#else //end of CHW + #ifdef NNOM_USING_CMSIS_NN + // 2D, square + if (layer->in->tensor->dim[1] == layer->in->tensor->dim[0] && + layer->out->tensor->dim[1] == layer->out->tensor->dim[0] && + cl->output_shift == 0) + { + arm_avepool_q7_HWC( + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[2], + cl->kernel.w, cl->pad.w, cl->stride.w, + layer->out->tensor->dim[1], + layer->comp->mem->blk, + layer->out->tensor->p_data); + } + // none square 2D, or 1D + else + #endif + { + // CMSIS-NN does not support none-square pooling, we have to use local implementation + local_avepool_q7_HWC(layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->kernel.w, cl->kernel.h, + cl->pad.w, cl->pad.h, + cl->stride.w, cl->stride.h, + out_x, out_y, + cl->output_shift, + NULL, + layer->out->tensor->p_data); + } +#endif + } + return NN_SUCCESS; +} diff --git a/components/ai/nnom/src/layers/nnom_baselayer.c b/components/ai/nnom/src/layers/nnom_baselayer.c new file mode 100644 index 000000000..0442fb2b0 --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_baselayer.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_baselayer.h" + +// this layer copys the input to the output + +nnom_layer_t *baselayer_s(const nnom_layer_config_t * config) +{ + nnom_layer_t *layer = BaseLayer(); + if(layer) + layer->config = (void*) config; + return layer; +} + +nnom_layer_t *BaseLayer() +{ + nnom_io_layer_t *layer; + nnom_layer_io_t *in, *out; + + // apply a block memory for all the sub handles. + size_t mem_size = sizeof(nnom_io_layer_t) + sizeof(nnom_layer_io_t) * 2; + layer = nnom_mem(mem_size); + if (layer == NULL) + return NULL; + + // distribut the memory to sub handles. + in = (void *)((uint8_t*)layer + sizeof(nnom_io_layer_t)); + out = (void *)((uint8_t*)in + sizeof(nnom_layer_io_t)); + + // set type in layer parent + layer->super.type = NNOM_BASE; + layer->super.run = default_run; + layer->super.build = default_build; + // set buf state + in->type = NNOM_TENSOR_BUF_TEMP; + out->type = NNOM_TENSOR_BUF_NULL; + // put in & out on the layer. + layer->super.in = io_init(layer, in); + layer->super.out = io_init(layer, out); + + return (nnom_layer_t *)layer; +} + +// this is call while output shape is not defined. +// this will set the output shape same as input shape, and it set only the primary IO +// this cannot be used as first layer, of course... +nnom_status_t default_build(nnom_layer_t *layer) +{ + // get the last layer's output as input shape + layer->in->tensor = layer->in->hook.io->tensor; + // output tensor + // 1. allocate a new tensor for output + // 2. set the same dim, qfmt to the new tensor. + layer->out->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR,layer->in->tensor->num_dim, tensor_get_num_channel(layer->in->tensor)); + tensor_cpy_attr(layer->out->tensor, layer->in->tensor); + + // see if the activation will change the q format + if(layer->actail) + layer->out->tensor->q_dec[0] = act_get_dec_bit(layer->actail->type, layer->out->tensor->q_dec[0]); + + // now this build has passed the input tensors (shapes, formats) to the new tensors. + return NN_SUCCESS; +} + +// simply copy input to output +nnom_status_t default_run(nnom_layer_t *layer) +{ + if(layer->out->type != NNOM_TENSOR_BUF_NULL) + { + nnom_memcpy(layer->out->tensor->p_data, layer->in->tensor->p_data, tensor_size_byte(layer->in->tensor)); + } + return NN_SUCCESS; +} diff --git a/components/ai/nnom/src/layers/nnom_concat.c b/components/ai/nnom/src/layers/nnom_concat.c new file mode 100644 index 000000000..0e1efa7a2 --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_concat.c @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_concat.h" + +nnom_layer_t *concat_s(const nnom_concat_config_t *config) +{ + nnom_layer_t* layer = Concat(config->axis); + if(layer) + layer->config = (void*) config; + return layer; +} + +// concate method +// concate requires more than one input module. aux input will be allocated in model.merge() +nnom_layer_t *Concat(int8_t axis) +{ + nnom_concat_layer_t *layer; + nnom_layer_io_t *in, *out; + size_t mem_size; + + // apply a block memory for all the sub handles. + mem_size = sizeof(nnom_concat_layer_t) + sizeof(nnom_layer_io_t) * 2; + layer = nnom_mem(mem_size); + if (layer == NULL) + return NULL; + + // distribut the memory to sub handles. + in = (void *)((uint8_t*)layer + sizeof(nnom_concat_layer_t)); + out = (void *)((uint8_t*)in + sizeof(nnom_layer_io_t)); + + // set type in layer parent + layer->super.type = NNOM_CONCAT; + layer->super.run = concat_run; + layer->super.build = concat_build; + // set buf state + in->type = NNOM_TENSOR_BUF_TEMP; + out->type = NNOM_TENSOR_BUF_TEMP; + // put in & out on the layer. + layer->super.in = io_init(layer, in); + layer->super.out = io_init(layer, out); + + // axis + layer->axis = axis; + + return (nnom_layer_t *)layer; +} + + +nnom_status_t concat_build(nnom_layer_t *layer) +{ + nnom_concat_layer_t *cl = (nnom_concat_layer_t *)layer; + nnom_layer_io_t *in; + uint32_t in_num = 0; + int32_t num_dim; + + // for each input module, copy the shape from the output of last layer + in = layer->in; + while (in != NULL) + { + //get the last layer's output as input shape + in->tensor = in->hook.io->tensor; + in = in->aux; + in_num++; + } + + // allocate new tensor for output, keep the same dimension lenght + layer->out->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, layer->in->tensor->num_dim, tensor_get_num_channel(layer->in->tensor)); + tensor_cpy_attr(layer->out->tensor, layer->in->tensor); + + // convert the axis. + if (cl->axis < 0) + cl->axis = (layer->in->tensor->num_dim + cl->axis); + else if (cl->axis >0) + cl->axis = cl->axis -1; // keras use axis start from 1. we are using 0, 1, 2 (check?) + + // find out the concated axis + num_dim = layer->in->tensor->num_dim; + for (uint32_t i = 0; i < num_dim; i ++) + { + // exclue the concat axies + if (i == cl->axis) + { + layer->out->tensor->dim[i] = 0; + + // add the same axis from all input up. + in = layer->in; + while (in != NULL) + { + layer->out->tensor->dim[i] += in->tensor->dim[i]; + in = in->aux; + } + continue; + } + + // check others, all other must be same shape + in = layer->in; + while (in != NULL && in->aux != NULL) + { + if (in->tensor->dim[i] != in->aux->tensor->dim[i]) + return NN_ARGUMENT_ERROR; + in = in->aux; + } + + // now set other axis + layer->out->tensor->dim[i] = layer->in->tensor->dim[i]; + } + + return NN_SUCCESS; +} + + +#ifdef NNOM_USING_CHW +// axis index converter between HWC and CHW +static inline int chw_i(int hwc, int num_dim) +{ + num_dim = num_dim -1; + hwc = hwc + 1; + if(hwc>num_dim) + hwc = 0; + return hwc; +} +static inline int hwc_i(int chw, int num_dim) +{ + num_dim = num_dim -1; + chw = chw - 1; + if(chw=2) input and 1 output. + nnom_concat_layer_t *cl = (nnom_concat_layer_t *)layer; + nnom_layer_io_t *in; + uint32_t dwidth = layer->in->tensor->bitwidth/8; // data width in byte + +#ifdef NNOM_USING_CHW + // Concatenate for HWC + uint8_t *pin; + uint8_t *pout = layer->out->tensor->p_data; + uint32_t block_size; + uint32_t n_block; + uint8_t num_dim = layer->in->tensor->num_dim; + + // calcualte number of block to concat. the other shapes before the concat axis + n_block = 1; + for(int i= 0; i< chw_i(cl->axis, num_dim); i++) + { + n_block *= layer->in->tensor->dim[hwc_i(i, num_dim)]; + } + + // concat all input layers + for(int i=0; iin; + while (in != NULL) + { + // the block size of concat data in this layer + block_size = dwidth; + for(int j= num_dim-1; j >= chw_i(cl->axis, num_dim); j--) + block_size *= in->tensor->dim[hwc_i(j, num_dim)]; + // concat + pin = (uint8_t *)in->tensor->p_data + i * block_size; + nnom_memcpy(pout, pin, block_size); + pout += block_size; + in = in->aux; + } + } + +#else // end of CHW concate + + // Concatenate for HWC + uint8_t* pin; + uint8_t* pout = layer->out->tensor->p_data; + uint32_t block_size; + uint32_t n_block; + uint8_t num_dim = layer->in->tensor->num_dim; + + // calcualte the number of block to concat. (the other shapes before the concat axis) + n_block = 1; + for (int i = 0; i < cl->axis; i++) + n_block *= layer->in->tensor->dim[i]; + + // concat all input layers + for (int i = 0; i < n_block; i++) + { + in = layer->in; + while (in != NULL) + { + // the block size of concat data in this layer + block_size = dwidth; + for (int j = cl->axis; j < num_dim; j++) + block_size *= in->tensor->dim[j]; + // concat + pin = (uint8_t*)in->tensor->p_data + i * block_size; + nnom_memcpy(pout, pin, block_size); + pout += block_size; + in = in->aux; + } + } +#endif + return NN_SUCCESS; +} + diff --git a/components/ai/nnom/src/layers/nnom_conv2d.c b/components/ai/nnom/src/layers/nnom_conv2d.c new file mode 100644 index 000000000..ea553aedf --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_conv2d.c @@ -0,0 +1,434 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_conv2d.h" + +#ifdef NNOM_USING_CMSIS_NN +#include "arm_math.h" +#include "arm_nnfunctions.h" +#endif + +// a machine friendly api, with suffix _s for structured configuration. +nnom_layer_t *conv2d_s(const nnom_conv2d_config_t *config) +{ + nnom_conv2d_layer_t *layer; + nnom_buf_t *comp; + nnom_layer_io_t *in, *out; + size_t mem_size; + + // allocate a block memory for all the sub handles and shifts. + mem_size = sizeof(nnom_conv2d_layer_t) + sizeof(nnom_layer_io_t) * 2 + sizeof(nnom_buf_t); + layer = nnom_mem(mem_size); + if (layer == NULL) + return NULL; + + // distribut the memory to sub handles. + in = (void *)((uint8_t*)layer + sizeof(nnom_conv2d_layer_t)); + out = (void *)((uint8_t*)in + sizeof(nnom_layer_io_t)); + comp = (void *)((uint8_t*)out + sizeof(nnom_layer_io_t)); + + // set type in layer parent + layer->super.type = NNOM_CONV_2D; + // set buf state + in->type = NNOM_TENSOR_BUF_TEMP; + out->type = NNOM_TENSOR_BUF_TEMP; + comp->type = NNOM_TENSOR_BUF_TEMP; + // put in & out on the layer. + layer->super.in = io_init(layer, in); + layer->super.out = io_init(layer, out); + #ifdef NNOM_USING_CMSIS_NN + layer->super.comp = comp; + #endif + // set run method & output shape + layer->super.run = conv2d_run; + layer->super.build = conv2d_build; + layer->super.free = conv2d_free; + + // save the config + layer->super.config = (void*) config; + + // get the private parameters + // test: for 1d input, expend h = 1 + if(config->weight->num_dim == 3) + { + layer->kernel = kernel(1, config->kernel_size[0]); + layer->stride = stride(1, config->stride_size[0]); + layer->dilation = dilation(1, config->dilation_size[0]); + } + else + { + layer->kernel = kernel(config->kernel_size[0], config->kernel_size[1]); + layer->stride = stride(config->stride_size[0], config->stride_size[1]); + layer->dilation = dilation(config->dilation_size[0], config->dilation_size[1]); + } + + layer->filter_mult = config->filter_size; // for convs, this means filter number + layer->padding_type = config->padding_type; + + // get bias and weight tensor, this should be created by script. + layer->weight = config->weight; + layer->bias = config->bias; + + // get shifts + layer->output_rshift = (nnom_qformat_param_t *)config->output_shift; + layer->bias_lshift = (nnom_qformat_param_t *)config->bias_shift; + + // padding + if (layer->padding_type == PADDING_SAME) + { + layer->pad.h = layer->dilation.h * (layer->kernel.h - 1) / 2; + layer->pad.w = layer->dilation.w * (layer->kernel.w - 1) / 2; + layer->pad.c = (1 - 1) / 2; + } + + return (nnom_layer_t *)layer; +} + + +// Conv2D +// multiplier of (output/input channel), +// shape of kernal, shape of strides, weight struct, bias struct +nnom_layer_t *Conv2D(uint32_t filters, nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_3d_shape_t d, nnom_padding_t pad_type, + const nnom_weight_t *w, const nnom_bias_t *b) +{ + nnom_conv2d_layer_t *layer; + nnom_buf_t *comp; + nnom_layer_io_t *in, *out; + // apply a block memory for all the sub handles. + size_t mem_size = sizeof(nnom_conv2d_layer_t) + sizeof(nnom_layer_io_t) * 2 + sizeof(nnom_buf_t); + layer = nnom_mem(mem_size); + if (layer == NULL) + return NULL; + + // distribut the memory to sub handles. + in = (void *)((uint8_t*)layer + sizeof(nnom_conv2d_layer_t)); + out = (void *)((uint8_t*)in + sizeof(nnom_layer_io_t)); + comp = (void *)((uint8_t*)out + sizeof(nnom_layer_io_t)); + + // set type in layer parent + layer->super.type = NNOM_CONV_2D; + // set buf state + in->type = NNOM_TENSOR_BUF_TEMP; + out->type = NNOM_TENSOR_BUF_TEMP; + comp->type = NNOM_TENSOR_BUF_TEMP; + // put in & out on the layer. + layer->super.in = io_init(layer, in); + layer->super.out = io_init(layer, out); + #ifdef NNOM_USING_CMSIS_NN + layer->super.comp = comp; + #endif + // set run method & output shape + layer->super.run = conv2d_run; + layer->super.build = conv2d_build; + + // get the private parameters + layer->kernel = k; + layer->stride = s; + layer->dilation = d; + layer->filter_mult = filters; // for convs, this means filter number + layer->padding_type = pad_type; + + // create weight and bias tensor + layer->weight = new_tensor(NNOM_QTYPE_PER_TENSOR, 4, filters); + layer->bias = new_tensor(NNOM_QTYPE_PER_TENSOR, 1, filters); + + // configure weight tensor manually to support new tensor based backends. + // needs to be very careful + { + // config weight + nnom_shape_data_t dim[4] = {k.h, k.w, k.c, filters}; + *(layer->weight->q_offset) = 0; // we have no support of offset here + *(layer->weight->q_dec) = 0; // not using it + layer->weight->p_data = (void*)w->p_value; + layer->weight->bitwidth = 8; + layer->weight->qtype = NNOM_QTYPE_PER_TENSOR; + nnom_memcpy(layer->weight->dim, dim, layer->weight->num_dim * sizeof(nnom_shape_data_t)); + + // config bias + dim[0] = filters; + *(layer->bias->q_offset) = 0; // we have no support of offset here + *(layer->bias->q_dec) = 0; // not using it + layer->bias->p_data = (void*) b->p_value; + layer->bias->bitwidth = 8; + layer->weight->qtype = NNOM_QTYPE_PER_TENSOR; + nnom_memcpy(layer->bias->dim, dim, layer->bias->num_dim * sizeof(nnom_shape_data_t)); + + // output shift and bias shift + layer->output_rshift = (nnom_qformat_param_t *)&w->shift; + layer->bias_lshift = (nnom_qformat_param_t *)&b->shift; + } + + return (nnom_layer_t *)layer; +} + +// keras's implementation. +// source: https://github.com/keras-team/keras/blob/7a39b6c62d43c25472b2c2476bd2a8983ae4f682/keras/utils/conv_utils.py#L85 +uint32_t conv_output_length(uint32_t input_length, uint32_t filter_size, nnom_padding_t padding, uint32_t stride, uint32_t dilation) +{ + if (input_length == 0) + return 0; + uint32_t dilated_filter_size = (filter_size - 1) * dilation + 1; + uint32_t output_length; + if(padding == PADDING_SAME) + output_length = input_length; + else + output_length = input_length - dilated_filter_size + 1; + return (output_length + stride - 1) / stride; +} + +nnom_status_t conv2d_build(nnom_layer_t *layer) +{ + nnom_conv2d_layer_t *cl = (nnom_conv2d_layer_t *)layer; + + // get the tensor from last layer's output + layer->in->tensor = layer->in->hook.io->tensor; + + // create new tensor for the output + layer->out->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, layer->in->tensor->num_dim, cl->filter_mult); + // copy then change later. + tensor_cpy_attr(layer->out->tensor, layer->in->tensor); + + // calculate the output tensor q format, only support per tensor quantise now + layer->out->tensor->q_dec[0] = layer->in->tensor->q_dec[0] + cl->weight->q_dec[0] - cl->output_rshift[0]; // need some modification for 16bit. + // see if the activation will change the q format + if(layer->actail) + layer->out->tensor->q_dec[0] = act_get_dec_bit(layer->actail->type, layer->out->tensor->q_dec[0]); + + // now we set up the tensor shape, always HWC format + layer->out->tensor->dim[0] = conv_output_length(layer->in->tensor->dim[0], cl->kernel.h, cl->padding_type, cl->stride.h, cl->dilation.h); + layer->out->tensor->dim[1] = conv_output_length(layer->in->tensor->dim[1], cl->kernel.w, cl->padding_type, cl->stride.w, cl->dilation.w); + layer->out->tensor->dim[2] = cl->filter_mult; // channel stays the same + + // fill padding + if (cl->padding_type == PADDING_SAME) + { + cl->pad.w = cl->dilation.w * (cl->kernel.w - 1) / 2; + cl->pad.h = cl->dilation.h * (cl->kernel.h - 1) / 2; + cl->pad.c = 0; + } + + #ifdef NNOM_USING_CMSIS_NN + // bufferA size: (1D shape) + // 2*ch_im_in*dim_kernel*dim_kernel + layer->comp->size = 2 * 2 * layer->in->tensor->dim[2] * cl->kernel.w * cl->kernel.h; + #endif + // computational cost: K x K x Cin x Hour x Wout x Cout + layer->stat.macc = cl->kernel.w * cl->kernel.h * layer->in->tensor->dim[2] * tensor_size(layer->out->tensor); + return NN_SUCCESS; +} + +nnom_status_t conv2d_free(nnom_layer_t *layer) +{ + // free weight and bias tensor when we are not initialised from structured configuration. + if(!layer->config) + { + nnom_conv2d_layer_t* cl = (nnom_conv2d_layer_t*)layer; + delete_tensor(cl->weight); + delete_tensor(cl->bias); + } + return NN_SUCCESS; +} + + +nnom_status_t conv2d_run(nnom_layer_t *layer) +{ + nnom_conv2d_layer_t *cl = (nnom_conv2d_layer_t *)layer; + +#ifdef NNOM_USING_CHW + // CHW format + if(layer->in->tensor->bitwidth == 16) + local_convolve_CHW_q15_nonsquare( + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->weight->p_data, layer->out->tensor->dim[2], + cl->kernel.w, cl->kernel.h, cl->pad.w, cl->pad.h, cl->stride.w, cl->stride.h, cl->dilation.w, cl->dilation.h, + cl->bias->p_data, cl->bias_lshift, cl->output_rshift, cl->weight->qtype, + layer->out->tensor->p_data, + layer->out->tensor->dim[1], layer->out->tensor->dim[0], NULL, NULL); + else + local_convolve_CHW_q7_nonsquare( + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->weight->p_data, layer->out->tensor->dim[2], + cl->kernel.w, cl->kernel.h, cl->pad.w, cl->pad.h, cl->stride.w, cl->stride.h, cl->dilation.w, cl->dilation.h, + cl->bias->p_data, cl->bias_lshift, cl->output_rshift, cl->weight->qtype, + layer->out->tensor->p_data, + layer->out->tensor->dim[1], layer->out->tensor->dim[0], NULL, NULL); + return NN_SUCCESS; +#else + // HWC format + #ifdef NNOM_USING_CMSIS_NN + // current cmsis nn does not support dilation + if(cl->dilation.w == 1 && cl->dilation.h == 1 && cl->weight->qtype == NNOM_QTYPE_PER_TENSOR) + { + // 8 bit cmsis nn + if(layer->in->tensor->bitwidth == 8) + { + //RGB + // ch_im_in = 3, w = h + if (layer->in->tensor->dim[2] == 3 && layer->in->tensor->dim[0] == layer->in->tensor->dim[1]) + // squared + if((cl->kernel.w == cl->kernel.h) && (cl->pad.w == cl->pad.h) && (cl->stride.w == cl->stride.h)) + return (nnom_status_t)arm_convolve_HWC_q7_RGB( + layer->in->tensor->p_data, layer->in->tensor->dim[1], layer->in->tensor->dim[2], + cl->weight->p_data, + layer->out->tensor->dim[2], + cl->kernel.w, cl->pad.w, cl->stride.w, + cl->bias->p_data, cl->bias_lshift[0], + cl->output_rshift[0], layer->out->tensor->p_data, layer->out->tensor->dim[1], + (q15_t *)(layer->comp->mem->blk), NULL); + + // check if can use optimized function + // ch_im_in is multiple of 4 + // ch_im_out is multiple of 2 + if ((layer->in->tensor->dim[2] % 4 == 0) && (layer->out->tensor->dim[2] % 2 == 0)) + { + // squared + if((layer->in->tensor->dim[0] == layer->in->tensor->dim[1]) + && (layer->out->tensor->dim[0] == layer->out->tensor->dim[1]) + && (cl->kernel.w == cl->kernel.h) && (cl->pad.w == cl->pad.h) && (cl->stride.w == cl->stride.h)) + { + // 1x1 fast + if (cl->kernel.w == 1 && cl->kernel.h == 1 && cl->stride.w == 1 && cl->stride.h == 1 && cl->pad.w == 0 && cl->pad.h == 0) + return (nnom_status_t)arm_convolve_1x1_HWC_q7_fast_nonsquare( + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->weight->p_data, + layer->out->tensor->dim[2], + cl->kernel.w, cl->kernel.h, cl->pad.w, cl->pad.h, cl->stride.w, cl->stride.h, + cl->bias->p_data, cl->bias_lshift[0], + cl->output_rshift[0], layer->out->tensor->p_data, layer->out->tensor->dim[1], layer->out->tensor->dim[0], + (q15_t *)(layer->comp->mem->blk), NULL); + // opt square shape + else + return (nnom_status_t)arm_convolve_HWC_q7_fast( + layer->in->tensor->p_data, layer->in->tensor->dim[1], layer->in->tensor->dim[2], + cl->weight->p_data, + layer->out->tensor->dim[2], cl->kernel.w, cl->pad.w, cl->stride.w, + cl->bias->p_data, cl->bias_lshift[0], + cl->output_rshift[0], layer->out->tensor->p_data, + layer->out->tensor->dim[1], (q15_t *)(layer->comp->mem->blk), NULL); + } + // opt none square shape + else + return (nnom_status_t)arm_convolve_HWC_q7_fast_nonsquare( + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->weight->p_data, layer->out->tensor->dim[2], + cl->kernel.w, cl->kernel.h, cl->pad.w, cl->pad.h, cl->stride.w, cl->stride.h, + cl->bias->p_data, cl->bias_lshift[0], cl->output_rshift[0], + layer->out->tensor->p_data, + layer->out->tensor->dim[1], layer->out->tensor->dim[0], (q15_t *)(layer->comp->mem->blk), NULL); + } + // none optimized + else + { + // none opt square shape + if ((layer->in->tensor->dim[0] == layer->in->tensor->dim[1] && + layer->out->tensor->dim[0] == layer->out->tensor->dim[1]) && + (cl->kernel.w == cl->kernel.h) && (cl->pad.w == cl->pad.h) && (cl->stride.w == cl->stride.h)) + return (nnom_status_t)arm_convolve_HWC_q7_basic( + layer->in->tensor->p_data, layer->in->tensor->dim[1], layer->in->tensor->dim[2], + cl->weight->p_data, + layer->out->tensor->dim[2], cl->kernel.w, cl->pad.w, cl->stride.w, + cl->bias->p_data, cl->bias_lshift[0], + cl->output_rshift[0], layer->out->tensor->p_data, + layer->out->tensor->dim[1], (q15_t *)(layer->comp->mem->blk), NULL); + // none opt none square shape + else + return (nnom_status_t)arm_convolve_HWC_q7_basic_nonsquare( + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->weight->p_data, layer->out->tensor->dim[2], + cl->kernel.w, cl->kernel.h, cl->pad.w, cl->pad.h, cl->stride.w, cl->stride.h, + cl->bias->p_data, cl->bias_lshift[0], cl->output_rshift[0], + layer->out->tensor->p_data, + layer->out->tensor->dim[1], layer->out->tensor->dim[0], (q15_t *)(layer->comp->mem->blk), NULL); + } //end of cmsis-nn none-opt + } //end of 8 bit cmsis-nn + else if (layer->in->tensor->bitwidth == 16) + { + // fast opt + if ((layer->in->tensor->dim[2] % 2 == 0) && (layer->out->tensor->dim[2] % 2 == 0)) + { + if((layer->in->tensor->dim[0] == layer->in->tensor->dim[1]) + && (layer->out->tensor->dim[0] == layer->out->tensor->dim[1]) + && (cl->kernel.w == cl->kernel.h) && (cl->pad.w == cl->pad.h) && (cl->stride.w == cl->stride.h)) + return (nnom_status_t)arm_convolve_HWC_q15_fast( + layer->in->tensor->p_data, layer->in->tensor->dim[1], layer->in->tensor->dim[2], + cl->weight->p_data, + layer->out->tensor->dim[2], cl->kernel.w, cl->pad.w, cl->stride.w, + cl->bias->p_data, cl->bias_lshift[0], + cl->output_rshift[0], layer->out->tensor->p_data, + layer->out->tensor->dim[1], (q15_t *)(layer->comp->mem->blk), NULL); + else + return (nnom_status_t)arm_convolve_HWC_q15_fast_nonsquare( + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->weight->p_data, layer->out->tensor->dim[2], + cl->kernel.w, cl->kernel.h, cl->pad.w, cl->pad.h, cl->stride.w, cl->stride.h, + cl->bias->p_data, cl->bias_lshift[0], cl->output_rshift[0], + layer->out->tensor->p_data, + layer->out->tensor->dim[1], layer->out->tensor->dim[0], (q15_t *)(layer->comp->mem->blk), NULL); + } + // none opt basic + else + { + local_convolve_HWC_q7_nonsquare( + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->weight->p_data, layer->out->tensor->dim[2], + cl->kernel.w, cl->kernel.h, cl->pad.w, cl->pad.h, cl->stride.w, cl->stride.h, cl->dilation.w, cl->dilation.h, + cl->bias->p_data, cl->bias_lshift, cl->output_rshift, cl->weight->qtype, + layer->out->tensor->p_data, + layer->out->tensor->dim[1], layer->out->tensor->dim[0], NULL, NULL); + return NN_SUCCESS; + } + + } // end of 16 bit cmsis-nn + } // end of dilation == 1 + else + #endif // NNOM_USING_CMSIS_NN + { + + if(layer->in->tensor->bitwidth == 16) + local_convolve_HWC_q15_nonsquare( + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->weight->p_data, layer->out->tensor->dim[2], + cl->kernel.w, cl->kernel.h, cl->pad.w, cl->pad.h, cl->stride.w, cl->stride.h, cl->dilation.w, cl->dilation.h, + cl->bias->p_data, cl->bias_lshift, cl->output_rshift, cl->weight->qtype, + layer->out->tensor->p_data, + layer->out->tensor->dim[1], layer->out->tensor->dim[0], NULL, NULL); + else + local_convolve_HWC_q7_nonsquare( + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->weight->p_data, layer->out->tensor->dim[2], + cl->kernel.w, cl->kernel.h, cl->pad.w, cl->pad.h, cl->stride.w, cl->stride.h, cl->dilation.w, cl->dilation.h, + cl->bias->p_data, cl->bias_lshift, cl->output_rshift, cl->weight->qtype, + layer->out->tensor->p_data, + layer->out->tensor->dim[1], layer->out->tensor->dim[0], NULL, NULL); + return NN_SUCCESS; + } +#endif // end of CHW/HWC + return NN_SUCCESS; +} + diff --git a/components/ai/nnom/src/layers/nnom_conv2d_trans.c b/components/ai/nnom/src/layers/nnom_conv2d_trans.c new file mode 100644 index 000000000..5a99380a2 --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_conv2d_trans.c @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-05-31 Jianjia Ma The first version + */ + + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_conv2d_trans.h" + +nnom_layer_t *conv2d_trans_s(const nnom_conv2d_config_t *config) +{ + nnom_layer_t *layer; + layer = conv2d_s(config); + if (layer) + { + layer->type = NNOM_CONV2D_TRANS; + layer->run = conv2d_trans_run; + layer->build = conv2d_trans_build; + } + return layer; +} + +nnom_layer_t *Conv2DTrans(uint32_t multiplier, nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_3d_shape_t d, nnom_padding_t pad_type, + const nnom_weight_t *w, const nnom_bias_t *b) +{ + nnom_layer_t *layer = Conv2D(multiplier, k, s, d, pad_type, w, b); + if (layer != NULL) + { + layer->type = NNOM_CONV2D_TRANS; + layer->run = conv2d_trans_run; + layer->build = conv2d_trans_build; + } + return layer; +} + +// utils, keras method +// https://github.com/keras-team/keras/blob/7a39b6c62d43c25472b2c2476bd2a8983ae4f682/keras/utils/conv_utils.py#L114 +// https://github.com/tensorflow/tensorflow/blob/2b96f3662bd776e277f86997659e61046b56c315/tensorflow/python/layers/utils.py#L156 +uint32_t conv_trans_output_length(uint32_t input_length, uint32_t kernel_size, nnom_padding_t padding, uint32_t stride_size, uint32_t dilation) +{ + input_length *= stride_size; + if (padding == PADDING_VALID) + input_length += MAX(kernel_size - stride_size, 0); + return input_length; +} + +nnom_status_t conv2d_trans_build(nnom_layer_t *layer) +{ + nnom_conv2d_trans_layer_t *cl = (nnom_conv2d_trans_layer_t *)layer; + + // get the tensor from last layer's output + layer->in->tensor = layer->in->hook.io->tensor; + + // create new tensor for the output + layer->out->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, layer->in->tensor->num_dim, cl->filter_mult); + // copy then change later. + tensor_cpy_attr(layer->out->tensor, layer->in->tensor); + + // calculate the output tensor q format, only support per tensor quantise now + layer->out->tensor->q_dec[0] = layer->in->tensor->q_dec[0] + cl->weight->q_dec[0] - cl->output_rshift[0]; + // see if the activation will change the q format + if(layer->actail) + layer->out->tensor->q_dec[0] = act_get_dec_bit(layer->actail->type, layer->out->tensor->q_dec[0]); + + // now we set up the tensor shape, always HWC format + layer->out->tensor->dim[0] = conv_trans_output_length(layer->in->tensor->dim[0], cl->kernel.h, cl->padding_type, cl->stride.h, cl->dilation.h); + layer->out->tensor->dim[1] = conv_trans_output_length(layer->in->tensor->dim[1], cl->kernel.w, cl->padding_type, cl->stride.w, cl->dilation.w); + layer->out->tensor->dim[2] = cl->filter_mult; // channel stays the same + + // fill the correct padding + if(cl->padding_type == PADDING_SAME) + { + cl->pad.h = (cl->kernel.h - cl->stride.h) / 2; // the padding to the output. + cl->pad.w = (cl->kernel.w - cl->stride.w) / 2; +// cl->pad.h = (cl->kernel.h - 1)/2; // the padding to the output. +// cl->pad.w = (cl->kernel.w - 1)/2; + cl->pad.c = 0; + } + else + { + cl->pad.h = 0; + cl->pad.w = 0; + cl->pad.c = 0; + } + + // bufferA size: (1D shape) + // 2*ch_im_in*dim_kernel*dim_kernel + //layer->comp->size = 2 * 2 * layer->in->tensor->dim[2] * cl->kernel.w * cl->kernel.h; + // computational cost: K x K x Cin x Hour x Wout x Cout + layer->stat.macc = cl->kernel.w * cl->kernel.h * layer->in->tensor->dim[2] * tensor_size(layer->out->tensor); + return NN_SUCCESS; +} + + +nnom_status_t conv2d_trans_run(nnom_layer_t *layer) +{ + nnom_conv2d_trans_layer_t *cl = (nnom_conv2d_trans_layer_t *)layer; + +#ifdef NNOM_USING_CHW + // no support for CHW yet + return NN_ARGUMENT_ERROR; +#else + + //return conv2d_run(layer); + + local_conv_trans_HWC_q7_nonsquare( + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->weight->p_data, layer->out->tensor->dim[2], + cl->kernel.w, cl->kernel.h, cl->pad.w, cl->pad.h, cl->stride.w, cl->stride.h, cl->dilation.w, cl->dilation.h, + cl->bias->p_data, cl->bias_lshift[0], cl->output_rshift[0], + layer->out->tensor->p_data, + layer->out->tensor->dim[1], layer->out->tensor->dim[0], NULL, NULL); + return NN_SUCCESS; +#endif +} + + diff --git a/components/ai/nnom/src/layers/nnom_cropping.c b/components/ai/nnom/src/layers/nnom_cropping.c new file mode 100644 index 000000000..01abe9265 --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_cropping.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_cropping.h" + +nnom_layer_t * cropping_s(const nnom_cropping_config_t *config) +{ + nnom_layer_t *layer = Cropping(config->pad); + if(layer) + layer->config = (void*) config; + return layer; +} + +// Cropping layer +nnom_layer_t *Cropping(nnom_border_t pad) +{ + nnom_layer_t *layer; + // most setting are the same as zero padding + layer = ZeroPadding(pad); + + // now change to cropping + layer->type = NNOM_CROPPING; + layer->run = cropping_run; + layer->build = cropping_build; + + return layer; +} + +nnom_status_t cropping_build(nnom_layer_t* layer) +{ + nnom_cropping_layer_t *cl = (nnom_cropping_layer_t *)layer; + + // get the tensor from last layer's output + layer->in->tensor = layer->in->hook.io->tensor; + + // create new tensor for output + layer->out->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, layer->in->tensor->num_dim, tensor_get_num_channel(layer->in->tensor)); + // copy then change later. + tensor_cpy_attr(layer->out->tensor, layer->in->tensor); + + // output shape + if(layer->in->tensor->dim[1] <= (cl->pad.left + cl->pad.right) || + layer->in->tensor->dim[0] <= (cl->pad.top + cl->pad.bottom)) + return NN_ARGUMENT_ERROR; + + layer->out->tensor->dim[0] = layer->in->tensor->dim[0] - (cl->pad.top + cl->pad.bottom); + layer->out->tensor->dim[1] = layer->in->tensor->dim[1] - (cl->pad.left + cl->pad.right); + layer->out->tensor->dim[2] = layer->in->tensor->dim[2]; + return NN_SUCCESS; +} + + +nnom_status_t cropping_run(nnom_layer_t * layer) +{ + nnom_cropping_layer_t *cl = (nnom_cropping_layer_t*)layer; + +#ifdef NNOM_USING_CHW + local_cropping_CHW_q7( +#else + local_cropping_HWC_q7( +#endif + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->pad.top, + cl->pad.bottom, + cl->pad.left, + cl->pad.right, + layer->out->tensor->p_data, + layer->out->tensor->dim[1], layer->out->tensor->dim[0]); + + return NN_SUCCESS; +} diff --git a/components/ai/nnom/src/layers/nnom_dense.c b/components/ai/nnom/src/layers/nnom_dense.c new file mode 100644 index 000000000..17c566c76 --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_dense.c @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_dense.h" + +#ifdef NNOM_USING_CMSIS_NN +#include "arm_math.h" +#include "arm_nnfunctions.h" +#endif + +nnom_layer_t *dense_s(const nnom_dense_config_t *config) +{ + nnom_dense_layer_t *layer; + nnom_buf_t *comp; + nnom_layer_io_t *in, *out; + + // apply a block memory for all the sub handles. + size_t mem_size = sizeof(nnom_dense_layer_t) + sizeof(nnom_layer_io_t) * 2 + sizeof(nnom_buf_t); + layer = nnom_mem(mem_size); + if (layer == NULL) + return NULL; + + // distribut the memory to sub handles. + in = (void *)((uint8_t*)layer + sizeof(nnom_dense_layer_t)); + out = (void *)((uint8_t*)in + sizeof(nnom_layer_io_t)); + comp = (void *)((uint8_t*)out + sizeof(nnom_layer_io_t)); + + // set type in layer parent + layer->super.type = NNOM_DENSE; + // set buf state + in->type = NNOM_TENSOR_BUF_TEMP; + out->type = NNOM_TENSOR_BUF_TEMP; + comp->type = NNOM_TENSOR_BUF_TEMP; + // put in & out on the layer. + layer->super.in = io_init(layer, in); + layer->super.out = io_init(layer, out); + layer->super.comp = comp; + // set run and outshape methods + layer->super.run = dense_run; + layer->super.build = dense_build; + layer->super.free = dense_free; + + // set parameters + layer->output_unit = tensor_get_num_channel(config->weight); + layer->bias = config->bias; + layer->weight = config->weight; + // set shifts + layer->output_rshift = (nnom_qformat_param_t *)config->output_shift; + layer->bias_lshift = (nnom_qformat_param_t *)config->bias_shift; + // set config + layer->super.config = (void*) config; + + return (nnom_layer_t *)layer; +} + +nnom_layer_t *Dense(size_t output_unit, const nnom_weight_t *w, const nnom_bias_t *b) +{ + nnom_dense_layer_t *layer; + nnom_buf_t *comp; + nnom_layer_io_t *in, *out; + + // apply a block memory for all the sub handles. + size_t mem_size = sizeof(nnom_dense_layer_t) + sizeof(nnom_layer_io_t) * 2 + sizeof(nnom_buf_t); + layer = nnom_mem(mem_size); + if (layer == NULL) + return NULL; + + // distribut the memory to sub handles. + in = (void *)((uint8_t*)layer + sizeof(nnom_dense_layer_t)); + out = (void *)((uint8_t*)in + sizeof(nnom_layer_io_t)); + comp = (void *)((uint8_t*)out + sizeof(nnom_layer_io_t)); + + // set type in layer parent + layer->super.type = NNOM_DENSE; + // set buf state + in->type = NNOM_TENSOR_BUF_TEMP; + out->type = NNOM_TENSOR_BUF_TEMP; + comp->type = NNOM_TENSOR_BUF_TEMP; + // put in & out on the layer. + layer->super.in = io_init(layer, in); + layer->super.out = io_init(layer, out); + layer->super.comp = comp; + // set run and outshape methods + layer->super.run = dense_run; + layer->super.build = dense_build; + + // set parameters + layer->output_unit = output_unit; // this is no longer needed. the information is contained in the weight tensor. + + layer->weight = new_tensor(NNOM_QTYPE_PER_TENSOR, 2, output_unit); + layer->bias = new_tensor(NNOM_QTYPE_PER_TENSOR, 1, output_unit); + + // configure weight tensor manually to support new tensor-based backends. + // needs to be very careful + { + // config weight + nnom_shape_data_t dim[2] = {0, output_unit}; // the first dim doesnt matter here. will be file in later. + *(layer->weight->q_offset) = 0; // we have no support of offset here + *(layer->weight->q_dec) = 0; // this is not even correct + layer->weight->p_data = (void*)w->p_value; + layer->weight->bitwidth = 8; + layer->weight->qtype = NNOM_QTYPE_PER_TENSOR; + nnom_memcpy(layer->weight->dim, dim, layer->weight->num_dim * sizeof(nnom_shape_data_t)); + + // config bias + dim[0] = output_unit; + *(layer->bias->q_offset) = 0; // we have no support of offset here + *(layer->bias->q_dec) = 0; // this is not even correct + layer->bias->p_data = (void*)b->p_value; + layer->bias->bitwidth = 8; + layer->weight->qtype = NNOM_QTYPE_PER_TENSOR; + nnom_memcpy(layer->bias->dim, dim, layer->bias->num_dim * sizeof(nnom_shape_data_t)); + } + + // set output shifts + layer->output_rshift = (nnom_qformat_param_t *)&w->shift; + layer->bias_lshift = (nnom_qformat_param_t *)&b->shift; + + return (nnom_layer_t *)layer; +} + +nnom_status_t dense_build(nnom_layer_t *layer) +{ + nnom_dense_layer_t *cl = (nnom_dense_layer_t *)layer; + + // get the tensor from last layer's output + layer->in->tensor = layer->in->hook.io->tensor; + + // create new tensor for output + layer->out->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, 1, tensor_get_num_channel(layer->in->tensor)); + // setup new tensor + nnom_shape_data_t dim[1] = {cl->output_unit}; + tensor_set_attr(layer->out->tensor, cl->weight->q_dec, cl->weight->q_offset, dim, 1, 8); // test, this is not correct + + // calculate the output tensor q format, only support per tensor quantise now + layer->out->tensor->q_dec[0] = layer->in->tensor->q_dec[0] + cl->weight->q_dec[0] - cl->output_rshift[0]; + // see if the activation will change the q format + if(layer->actail) + layer->out->tensor->q_dec[0] = act_get_dec_bit(layer->actail->type, layer->out->tensor->q_dec[0]); + + // vec_buffer size: dim_vec (*2, q7->q15) ? I am not sure this is right + layer->comp->size = tensor_size(layer->in->tensor)*2; + + // computational cost: In * out + layer->stat.macc = tensor_size(layer->in->tensor) * tensor_size(layer->out->tensor); + return NN_SUCCESS; +} + +nnom_status_t dense_free(nnom_layer_t *layer) +{ + // free weight and bias tensor when we are not initialised from structured configuration. + if(!layer->config) + { + nnom_dense_layer_t* cl = (nnom_dense_layer_t*)layer; + delete_tensor(cl->weight); + delete_tensor(cl->bias); + } + + return NN_SUCCESS; +} + +nnom_status_t dense_run(nnom_layer_t *layer) +{ + nnom_status_t result = NN_SUCCESS; + nnom_dense_layer_t *cl = (nnom_dense_layer_t *)(layer); + nnom_qformat_param_t bias_shift = cl->bias_lshift[0]; // this is not correct but a temporary fix solution for backward compatibility. + nnom_qformat_param_t output_shift = cl->output_rshift[0]; + + +#if !(DENSE_WEIGHT_OPT) + #ifdef NNOM_USING_CMSIS_NN + result = (nnom_status_t)arm_fully_connected_q7( + #else + local_fully_connected_q7( + #endif +#else + #ifdef NNOM_USING_CMSIS_NN + result = (nnom_status_t)arm_fully_connected_q7_opt( + #else + local_fully_connected_q7_opt( + #endif +#endif + layer->in->tensor->p_data, + cl->weight->p_data, + tensor_size(layer->in->tensor), layer->out->tensor->dim[0], + bias_shift, output_shift, + cl->bias->p_data, + layer->out->tensor->p_data, (q15_t *)(layer->comp->mem->blk)); + return result; +} + diff --git a/components/ai/nnom/src/layers/nnom_dw_conv2d.c b/components/ai/nnom/src/layers/nnom_dw_conv2d.c new file mode 100644 index 000000000..72ac7754e --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_dw_conv2d.c @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_dw_conv2d.h" + +#ifdef NNOM_USING_CMSIS_NN +#include "arm_math.h" +#include "arm_nnfunctions.h" +#endif + +nnom_layer_t *dw_conv2d_s(const nnom_conv2d_config_t *config) +{ + nnom_layer_t *layer; + layer = conv2d_s(config); + if (layer) + { + layer->type = NNOM_DW_CONV_2D; + layer->run = dw_conv2d_run; + layer->build = dw_conv2d_build; + } + return layer; +} + +nnom_layer_t *DW_Conv2D(uint32_t multiplier, nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_3d_shape_t d, nnom_padding_t pad_type, + const nnom_weight_t *w, const nnom_bias_t *b) +{ + nnom_layer_t *layer = Conv2D(multiplier, k, s, d, pad_type, w, b); // passing multiplier in . + if (layer != NULL) + { + layer->type = NNOM_DW_CONV_2D; + layer->run = dw_conv2d_run; + layer->build = dw_conv2d_build; + } + return layer; +} + +nnom_status_t dw_conv2d_build(nnom_layer_t *layer) +{ + nnom_conv2d_layer_t *cl = (nnom_conv2d_layer_t *)layer; + + // get the tensor from last layer's output + layer->in->tensor = layer->in->hook.io->tensor; + + // create new tensor for output + layer->out->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, layer->in->tensor->num_dim, tensor_get_num_channel(layer->in->tensor) * cl->filter_mult); + // copy then change later. + tensor_cpy_attr(layer->out->tensor, layer->in->tensor); + + // calculate the output tensor q format, only support per tensor quantise now + layer->out->tensor->q_dec[0] = layer->in->tensor->q_dec[0] + cl->weight->q_dec[0] - cl->output_rshift[0]; + // see if the activation will change the q format + if(layer->actail) + layer->out->tensor->q_dec[0] = act_get_dec_bit(layer->actail->type, layer->out->tensor->q_dec[0]); + + // now we set up the tensor shape, always HWC format + layer->out->tensor->dim[0] = conv_output_length(layer->in->tensor->dim[0], cl->kernel.h, cl->padding_type, cl->stride.h, cl->dilation.h); + layer->out->tensor->dim[1] = conv_output_length(layer->in->tensor->dim[1], cl->kernel.w, cl->padding_type, cl->stride.w, cl->dilation.w); + layer->out->tensor->dim[2] = layer->in->tensor->dim[2] * cl->filter_mult; // channel stays the same + + // fill padding + if (cl->padding_type == PADDING_SAME) + { + cl->pad.w = cl->dilation.w * (cl->kernel.w - 1) / 2; + cl->pad.h = cl->dilation.h * (cl->kernel.h - 1) / 2; + cl->pad.c = 0; + } + + // bufferA size: + #ifdef NNOM_USING_CMSIS_NN + layer->comp->size = 2 * 2 * (layer->in->tensor->dim[2] / cl->filter_mult) * cl->kernel.w * cl->kernel.h; + #endif + + // computational cost: K x K x Cin x Hout x Wout x Multiplier + // or : K x K x Cout x Hout x Wout + layer->stat.macc = cl->kernel.w * cl->kernel.h * tensor_size(layer->out->tensor); + return NN_SUCCESS; +} + +nnom_status_t dw_conv2d_run(nnom_layer_t *layer) +{ + nnom_status_t result = NN_SUCCESS; + nnom_conv2d_layer_t *cl = (nnom_conv2d_layer_t *)layer; + +#ifndef NNOM_USING_CHW + #ifdef NNOM_USING_CMSIS_NN + // Current CMSIS-NN does not support dilation + if(cl->dilation.w ==1 && cl->dilation.h == 1 && cl->weight->qtype == NNOM_QTYPE_PER_TENSOR && cl->filter_mult == 1) + { + // CMSIS-NN only support 1 mulplipier in depthwise conv + if (layer->in->tensor->dim[2] % 2 != 0 || layer->out->tensor->dim[2] % 2) + return NN_ARGUMENT_ERROR; + result = (nnom_status_t)arm_depthwise_separable_conv_HWC_q7_nonsquare( + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->weight->p_data, + layer->out->tensor->dim[2], + cl->kernel.w, cl->kernel.h, + cl->pad.w, cl->pad.h, + cl->stride.w, cl->stride.h, + cl->bias->p_data, + cl->bias_lshift[0], cl->output_rshift[0], + layer->out->tensor->p_data, + layer->out->tensor->dim[1], layer->out->tensor->dim[0], (q15_t *)(layer->comp->mem->blk), NULL); + } + else + #endif + local_depthwise_separable_conv_HWC_q7_nonsquare( +#else + local_depthwise_separable_conv_CHW_q7_nonsquare( +#endif + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->weight->p_data, + layer->out->tensor->dim[2], + cl->kernel.w, cl->kernel.h, + cl->pad.w, cl->pad.h, + cl->stride.w, cl->stride.h, + cl->dilation.w, cl->dilation.h, + cl->bias->p_data, + cl->bias_lshift, cl->output_rshift, cl->weight->qtype, + layer->out->tensor->p_data, + layer->out->tensor->dim[1], layer->out->tensor->dim[0], NULL, NULL); + return result; +} diff --git a/components/ai/nnom/src/layers/nnom_flatten.c b/components/ai/nnom/src/layers/nnom_flatten.c new file mode 100644 index 000000000..c976bca9a --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_flatten.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_flatten.h" + +nnom_layer_t *flatten_s(const nnom_flatten_config_t *config) +{ + nnom_layer_t *layer = Flatten(); + if(layer) + layer->config = (void*) config; + return layer; +} + +nnom_layer_t *Flatten(void) +{ + nnom_layer_t *layer; + nnom_layer_io_t *in, *out; + + // apply a block memory for all the sub handles. + size_t mem_size = sizeof(nnom_layer_t) + sizeof(nnom_layer_io_t) * 2; + layer = nnom_mem(mem_size); + if (layer == NULL) + return NULL; + + // distribut the memory to sub handles. + in = (void *)((uint8_t*)layer + sizeof(nnom_layer_t)); + out = (void *)((uint8_t*)in + sizeof(nnom_layer_io_t)); + + // set type in layer parent + layer->type = NNOM_FLATTEN; + layer->run = flatten_run; + layer->build = flatten_build; + // set buf state + in->type = NNOM_TENSOR_BUF_TEMP; + #ifdef NNOM_USING_CHW + out->type = NNOM_TENSOR_BUF_TEMP; // test for CHW format + #else + out->type = NNOM_TENSOR_BUF_NULL; + #endif + // put in & out on the layer. + layer->in = io_init(layer, in); + layer->out = io_init(layer, out); + + return layer; +} + +nnom_status_t flatten_build(nnom_layer_t *layer) +{ + // get the tensor from last layer's output + layer->in->tensor = layer->in->hook.io->tensor; + + // create new tensor for output + layer->out->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, layer->in->tensor->num_dim, tensor_get_num_channel(layer->in->tensor)); + // setup new tensor + nnom_shape_data_t dim[1] = {tensor_size(layer->in->tensor)}; + tensor_set_attr(layer->out->tensor, layer->in->tensor->q_dec, layer->in->tensor->q_offset, dim, 1, 8); + + return NN_SUCCESS; +} + +nnom_status_t flatten_run(nnom_layer_t *layer) +{ + #ifdef NNOM_USING_CHW + // CHW format must reorder to HWC for dense layer and all other 1D layer (?) + tensor_chw2hwc_q7(layer->out->tensor, layer->in->tensor); + #endif + return NN_SUCCESS; +} diff --git a/components/ai/nnom/src/layers/nnom_global_pool.c b/components/ai/nnom/src/layers/nnom_global_pool.c new file mode 100644 index 000000000..8e0d1ee64 --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_global_pool.c @@ -0,0 +1,145 @@ + +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_global_pool.h" + +nnom_layer_t * global_maxpool_s(const nnom_global_pool_config_t *config) +{ + nnom_maxpool_layer_t * cl = (nnom_maxpool_layer_t *)GlobalMaxPool(); + if(cl) + { + cl->super.config = (void*) config; + cl->output_shift = config->output_shift; + } + return (nnom_layer_t *)cl; +} +nnom_layer_t * global_avgpool_s(const nnom_global_pool_config_t *config) +{ + nnom_maxpool_layer_t * cl = (nnom_maxpool_layer_t *)GlobalAvgPool(); + if(cl) + { + cl->super.config = (void*) config; + cl->output_shift = config->output_shift; + } + return (nnom_layer_t *)cl; +} + +nnom_layer_t * global_sumpool_s(const nnom_global_pool_config_t *config) +{ + nnom_maxpool_layer_t * cl = (nnom_maxpool_layer_t *)GlobalSumPool(); + if(cl) + { + cl->super.config = (void*) config; + cl->output_shift = config->output_shift; + } + return (nnom_layer_t *)cl; +} + + +nnom_layer_t *GlobalMaxPool(void) +{ + // create the normal pooling layer, the parameters are left empty to fill in later. + // parameters will be filled in in global_pooling_build() + nnom_layer_t *layer = MaxPool(kernel(0, 0), stride(0, 0), PADDING_VALID); + + // change to global max pool + if (layer != NULL) + { + layer->type = NNOM_GLOBAL_MAXPOOL; + layer->build = global_pool_build; + } + + return (nnom_layer_t *)layer; +} + +nnom_layer_t *GlobalAvgPool(void) +{ + // create the normal pooling layer, the parameters are left empty to fill in later. + // parameters will be filled in global_pooling_build() remotely + nnom_layer_t *layer = MaxPool(kernel(0, 0), stride(0, 0), PADDING_VALID); + + // change some parameters to be recognised as avg pooling + if (layer != NULL) + { + layer->type = NNOM_GLOBAL_AVGPOOL; + layer->run = avgpool_run; // global and basic pooling share the same runner + layer->build = global_pool_build; + } + + return (nnom_layer_t *)layer; +} + +nnom_layer_t *GlobalSumPool(void) +{ + // create the normal pooling layer, the parameters are left empty to fill in later. + // parameters will be filled in global_pooling_build() remotely + nnom_layer_t *layer = MaxPool(kernel(0, 0), stride(0, 0), PADDING_VALID); + + // change some parameters to be recognised as avg pooling + if (layer != NULL) + { + layer->type = NNOM_GLOBAL_SUMPOOL; + layer->run = sumpool_run; // global and basic pooling share the same runner + layer->build = global_pool_build; + } + + return (nnom_layer_t *)layer; +} + +nnom_status_t global_pool_build(nnom_layer_t *layer) +{ + nnom_maxpool_layer_t *cl = (nnom_maxpool_layer_t *)layer; + + // get the tensor from last layer's output + layer->in->tensor = layer->in->hook.io->tensor; + + // create new tensor for output + layer->out->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, 1, tensor_get_num_channel(layer->in->tensor)); + + nnom_shape_data_t dim[1] = {tensor_get_num_channel(layer->in->tensor)}; // fill the first 2 dim later + tensor_set_attr_v(layer->out->tensor, layer->in->tensor->q_dec[0], 0, dim, sizeof(dim)/sizeof(nnom_shape_data_t), 8); + + // see if the activation will change the q format + if(layer->actail) + layer->out->tensor->q_dec[0] = act_get_dec_bit(layer->actail->type, layer->out->tensor->q_dec[0]); + + // different from other *_build(), the kernel..padding left by layer API needs to be set in here + // due to the *_run() methods of global pooling are using the normall pooling's. + // fill in the parameters left by layer APIs (GlobalAvgPool and MaxAvgPool) + cl->kernel = shape(layer->in->tensor->dim[0], layer->in->tensor->dim[1], 1); + cl->stride = shape(1, 1, 1); + cl->pad = shape(0, 0, 0); + cl->padding_type = PADDING_VALID; + + // additionally, avg pooling require computational buffer, which is 2*dim_im_out*ch_im_in + if (layer->type == NNOM_AVGPOOL || layer->type == NNOM_GLOBAL_AVGPOOL) + { + // bufferA size: 2*dim_im_out*ch_im_in + layer->comp->size = 2 * layer->out->tensor->dim[0] * layer->in->tensor->dim[2]; + } + + // additional for sumpool + if (layer->type == NNOM_SUMPOOL || layer->type == NNOM_GLOBAL_SUMPOOL) + layer->comp->size = 4 * tensor_size(layer->out->tensor); + + return NN_SUCCESS; +} + + diff --git a/components/ai/nnom/src/layers/nnom_gru_cell.c b/components/ai/nnom/src/layers/nnom_gru_cell.c new file mode 100644 index 000000000..7e01e9e2a --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_gru_cell.c @@ -0,0 +1,338 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-24 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_gru_cell.h" + +#ifdef NNOM_USING_CMSIS_NN +#include "arm_math.h" +#include "arm_nnfunctions.h" +#endif + +nnom_rnn_cell_t *gru_cell_s(const nnom_gru_cell_config_t* config) +{ + nnom_gru_cell_t *cell; + cell = nnom_mem(sizeof(nnom_gru_cell_t)); + if (cell == NULL) + return NULL; + // set methods + cell->super.run = gru_cell_run; + cell->super.build = gru_cell_build; + cell->super.free = gru_cell_free; + cell->super.config = (void*) config; + cell->super.units = config->units; + cell->super.type = NNOM_GRU_CELL; + + // set parameters + cell->bias = config->bias; + cell->weights = config->weights; + cell->recurrent_weights = config->recurrent_weights; + + // q format for intermediate calculation + cell->q_dec_h = config->q_dec_h; + cell->q_dec_z = config->q_dec_z; + + return (nnom_rnn_cell_t *)cell; +} + +nnom_status_t gru_cell_free(nnom_rnn_cell_t* cell) +{ + return NN_SUCCESS; +} + +// the state buffer and computational buffer shape of the cell +nnom_status_t gru_cell_build(nnom_rnn_cell_t* cell) +{ + nnom_layer_t *layer = cell->layer; + nnom_gru_cell_t *c = (nnom_gru_cell_t *)cell; + + // calculate output shift for the 2 calculation. + // hw = the product of hidden x weight, iw = the product of input x weight + // due to the addition of them, they must have same q format. + // that is -> c->q_dec_z; + + // for the dots in cell: output shift = input_dec + weight_dec - output_dec + c->oshift_hw = c->q_dec_h + c->recurrent_weights->q_dec[0] - c->q_dec_z; + c->oshift_iw = layer->in->tensor->q_dec[0] + c->weights->q_dec[0] - c->q_dec_z; + + // bias shift = bias_dec - out_dec + c->bias_shift = layer->in->tensor->q_dec[0] + c->weights->q_dec[0] - c->bias->q_dec[0]; + + // state size = one timestamp output size. + cell->state_size = cell->units * 2; // Q15 + + // comp buffer size: not required + cell->comp_buf_size = cell->units * (3*3) * 2 + cell->feature_size * 2; //q15 + input q7->q15 buffer. + + // finally, calculate the MAC for info for each timestamp + cell->macc = cell->feature_size * cell->units *3 // input: feature * state * 3 gates + + cell->units * cell->units *8 // recurrent, state * output_unit * (5 gate + 3 mult) + + cell->units * (3 + 3 + 5); // 3 gates, 3 mult, 5 addition + + return NN_SUCCESS; +} + + +// keras implementation as below. +/* + def step(cell_inputs, cell_states): + """Step function that will be used by Keras RNN backend.""" + h_tm1 = cell_states[0] + + # inputs projected by all gate matrices at once + matrix_x = K.dot(cell_inputs, kernel) + matrix_x = K.bias_add(matrix_x, input_bias) + + x_z, x_r, x_h = array_ops.split(matrix_x, 3, axis=1) + + # hidden state projected by all gate matrices at once + matrix_inner = K.dot(h_tm1, recurrent_kernel) + matrix_inner = K.bias_add(matrix_inner, recurrent_bias) + + recurrent_z, recurrent_r, recurrent_h = array_ops.split(matrix_inner, 3, + axis=1) + z = nn.sigmoid(x_z + recurrent_z) + r = nn.sigmoid(x_r + recurrent_r) + hh = nn.tanh(x_h + r * recurrent_h) + + # previous and candidate state mixed by update gate + h = z * h_tm1 + (1 - z) * hh + return h, [h] +*/ + +// +nnom_status_t gru_cell_run(nnom_rnn_cell_t* cell) +{ + nnom_layer_t *layer = cell->layer; + nnom_gru_cell_t* c = (nnom_gru_cell_t*) cell; + int act_int_bit = 7 - c->q_dec_z; + // gate data + q15_t* x_z, *x_r, *x_h; + q15_t* recurrent_z, *recurrent_r, *recurrent_h; + q15_t* temp[3]; + + // bias + q7_t* bias = (q7_t*)c->bias->p_data; + q7_t* recurrent_bias = (q7_t*)c->bias->p_data + cell->units*3; + + // state buffer + q15_t* h_tm1 = (q15_t*)cell->in_state; + q15_t* h_t = (q15_t*)cell->out_state; + + // computing buffer + // low |-- buf0 --|-- buf1 --|-- buf2 --|-- input_q15 --| + q15_t *buf[3]; + buf[0] = (q15_t*)layer->comp->mem->blk; + buf[1] = (q15_t*)layer->comp->mem->blk + cell->units*3; + buf[2] = (q15_t*)layer->comp->mem->blk + cell->units*6; + q15_t *in_q15_buf = (q15_t*)layer->comp->mem->blk + cell->units*9; + + // input q7 cast to q15 + local_q7_to_q15(cell->in_data, in_q15_buf, cell->feature_size); + + // matrix_x = K.dot(cell_inputs, kernel) + bias --> buf0 + #ifdef NNOM_USING_CMSIS_NN + arm_fully_connected_mat_q7_vec_q15_opt + #else + local_fully_connected_mat_q7_vec_q15_opt + #endif + (in_q15_buf, c->weights->p_data, cell->feature_size, + cell->units*3, c->bias_shift + 8, c->oshift_iw, bias, buf[0], NULL); + + // matrix_intter = K.dot(h_tm1, recurrent_kernel) + bias -> buf1 + #ifdef NNOM_USING_CMSIS_NN + arm_fully_connected_mat_q7_vec_q15_opt + #else + local_fully_connected_mat_q7_vec_q15_opt + #endif + (h_tm1, c->recurrent_weights->p_data, cell->units, + cell->units*3, c->bias_shift + 8, c->oshift_hw, recurrent_bias, buf[1], NULL); + + // split to each gate + x_z = buf[0]; + x_r = buf[0] + cell->units; + x_h = buf[0] + cell->units*2; + recurrent_z = buf[1]; + recurrent_r = buf[1] + cell->units; + recurrent_h = buf[1] + cell->units*2; + // buffers + temp[0] = buf[2]; + temp[1] = buf[2] + cell->units; + temp[2] = buf[2] + cell->units*2; + + /* z = nn.sigmoid(x_z + recurrent_z) */ + // 1. z1 = x_z + recurrent_z ---> temp[0] + local_add_q15(x_z, recurrent_z, temp[0], 0, cell->units); + // 2. z = sigmoid(z1) + local_sigmoid_q15(temp[0], cell->units, act_int_bit); + + /* r = nn.sigmoid(x_r + recurrent_r) */ + // 1. r1 = x_r + recurrent_r ---> temp[1] + local_add_q15(x_r, recurrent_r, temp[1], 0, cell->units); + // 2. r = sigmoid(r1) + local_sigmoid_q15(temp[1], cell->units, act_int_bit); + + /* hh = nn.tanh(x_h + r * recurrent_h) */ + // 1. hh1 = r * recurrent_h ---> temp[2] + local_mult_q15(temp[1], recurrent_h, temp[2], 15, cell->units); + // 2. hh2 = x_h + hh1 ---> temp[1] + local_add_q15(x_h, temp[2], temp[1], 0, cell->units); + // 3. hh = tanh(h2) ---> temp[1] + local_tanh_q15(temp[1], cell->units, act_int_bit); + + /* h = z * h_tm1 + (1 - z) * hh */ + // 1. h1 = z*h_tm1 ---> temp[2] + local_mult_q15(temp[0], h_tm1, temp[2], 15, cell->units); + // 2. h2 = 1 - z ---> h_t state buff + local_1_minor_z_q15(temp[0], h_t, 15, cell->units); + // 3. h3 = h2 * hh ---> temp[0] + local_mult_q15(h_t, temp[1], temp[0], 15, cell->units); + // h = h1 + h3 + local_add_q15(temp[2], temp[0], h_t, 0, cell->units); + + // finally, copy and convert state to output + local_q15_to_q7(h_t, cell->out_data, 8, cell->units); + return NN_SUCCESS; +} + + +// Researve for debugging, printing the intermediate variables/data. +#if 0 +// delete after testing completed +static void print_variable_q15(q15_t *data,char*name, int dec_bit, int size) +{ + printf("\n\n"); + printf("%s", name); + for(int i = 0; i < size; i++) + { + if(i%8==0) + printf("\n"); + printf("%f\t", (float) data[i] / (1 << dec_bit)); + } + printf("\n"); +} + +// +nnom_status_t gru_cell_run(nnom_rnn_cell_t* cell) +{ + nnom_layer_t *layer = cell->layer; + nnom_gru_cell_t* c = (nnom_gru_cell_t*) cell; + int act_int_bit = 7 - c->q_dec_z; + // gate data + q15_t* x_z, *x_r, *x_h; + q15_t* recurrent_z, *recurrent_r, *recurrent_h; + q15_t* temp[3]; + + // test + //nnom_memset(cell->in_data, 5 * (1<in->tensor->q_dec[0]), cell->feature_size); + + // bias + q7_t* bias = (q7_t*)c->bias->p_data; + q7_t* recurrent_bias = (q7_t*)c->bias->p_data + cell->units*3; + + // state buffer + q15_t* h_tm1 = (q15_t*)cell->in_state; + q15_t* h_t = (q15_t*)cell->out_state; + + // computing buffer + // low |-- buf0 --|-- buf1 --|-- buf2 --|-- input_q15 --| + q15_t *buf[3]; + buf[0] = (q15_t*)layer->comp->mem->blk; + buf[1] = (q15_t*)layer->comp->mem->blk + cell->units*3; + buf[2] = (q15_t*)layer->comp->mem->blk + cell->units*6; + q15_t *in_q15_buf = (q15_t*)layer->comp->mem->blk + cell->units*9; + + // input q7 cast to q15 + local_q7_to_q15(cell->in_data, in_q15_buf, cell->feature_size); + + // matrix_x = K.dot(cell_inputs, kernel) + bias --> buf0 + #ifdef NNOM_USING_CMSIS_NN + arm_fully_connected_mat_q7_vec_q15_opt + #else + local_fully_connected_mat_q7_vec_q15_opt + #endif + (in_q15_buf, c->weights->p_data, cell->feature_size, + cell->units*3, c->bias_shift + 8, c->oshift_iw, bias, buf[0], NULL); + + // matrix_intter = K.dot(h_tm1, recurrent_kernel) + bias -> buf1 + #ifdef NNOM_USING_CMSIS_NN + arm_fully_connected_mat_q7_vec_q15_opt + #else + local_fully_connected_mat_q7_vec_q15_opt + #endif + (h_tm1, c->recurrent_weights->p_data, cell->units, + cell->units*3, c->bias_shift + 8, c->oshift_hw, recurrent_bias, buf[1], NULL); + + print_variable_q15(in_q15_buf, "input", layer->in->tensor->q_dec[0]+8, cell->feature_size); + print_variable_q15(buf[0], "matrix_x", c->q_dec_z+8, cell->units*3); + print_variable_q15(buf[1], "matrix_recurrent", c->q_dec_z+8, cell->units*3); + + // split to each gate + x_z = buf[0]; + x_r = buf[0] + cell->units; + x_h = buf[0] + cell->units*2; + recurrent_z = buf[1]; + recurrent_r = buf[1] + cell->units; + recurrent_h = buf[1] + cell->units*2; + // buffers + temp[0] = buf[2]; + temp[1] = buf[2] + cell->units; + temp[2] = buf[2] + cell->units*2; + + // z = nn.sigmoid(x_z + recurrent_z) + // 1. z1 = x_z + recurrent_z ---> temp[0] + local_add_q15(x_z, recurrent_z, temp[0], 0, cell->units); + // 2. z = sigmoid(z1) + local_sigmoid_q15(temp[0], cell->units, act_int_bit); + print_variable_q15(temp[0], "z", 15, cell->units); + + // r = nn.sigmoid(x_r + recurrent_r) + // 1. r1 = x_r + recurrent_r ---> temp[1] + local_add_q15(x_r, recurrent_r, temp[1], 0, cell->units); + // 2. r = sigmoid(r1) + local_sigmoid_q15(temp[1], cell->units, act_int_bit); + print_variable_q15(temp[1], "r", 15, cell->units); + + // hh = nn.tanh(x_h + r * recurrent_h) + // 1. hh1 = r * recurrent_h ---> temp[2] + local_mult_q15(temp[1], recurrent_h, temp[2], 15, cell->units); + // 2. hh2 = x_h + h1 ---> temp[1] + local_add_q15(x_h, temp[2], temp[1], 0, cell->units); + // 3. hh = tanh(h2) ---> temp[1] + local_tanh_q15(temp[1], cell->units, act_int_bit); + print_variable_q15(temp[1], "hh", 15, cell->units); + + // h = z * h_tm1 + (1 - z) * hh + // 1. h1 = z*h_tm1 ---> temp[2] + local_mult_q15(temp[0], h_tm1, temp[2], 15, cell->units); + print_variable_q15( temp[2], "h1", 15, cell->units); + // 2. h2 = 1 - z ---> h_t state buff + local_1_minor_z_q15(temp[0], h_t, 15, cell->units); + print_variable_q15( h_t, "h2", 15, cell->units); + // 3. h3 = h2 * hh ---> temp[0] + local_mult_q15(h_t, temp[1], temp[0], 15, cell->units); + print_variable_q15( temp[0], "h3", 15, cell->units); + // h = h1 + h3 + local_add_q15(temp[2], temp[0], h_t, 0, cell->units); + print_variable_q15(h_t, "h", 15, cell->units); + + // finally, copy and convert state to output + local_q15_to_q7(h_t, cell->out_data, 8, cell->units); + return NN_SUCCESS; +} +#endif diff --git a/components/ai/nnom/src/layers/nnom_input.c b/components/ai/nnom/src/layers/nnom_input.c new file mode 100644 index 000000000..f1fc3b9c9 --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_input.c @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_input.h" + +nnom_layer_t *input_s(const nnom_io_config_t* config) +{ + nnom_io_layer_t *layer; + nnom_layer_io_t *in, *out; + // apply a block memory for all the sub handles. + layer = nnom_mem(sizeof(nnom_io_layer_t) + sizeof(nnom_layer_io_t) * 2); + if (layer == NULL) + return NULL; + + // distribut the memory to sub handles. + in = (void *)((uint8_t*)layer + sizeof(nnom_io_layer_t)); + out = (void *)((uint8_t*)in + sizeof(nnom_layer_io_t)); + + // set type in layer parent + layer->super.type = NNOM_INPUT; + layer->super.run = input_run; + layer->super.build = input_build; + // set buf state + in->type = NNOM_TENSOR_BUF_TEMP; + out->type = NNOM_TENSOR_BUF_NULL; + // put in & out on the layer. + layer->super.in = io_init(layer, in); + layer->super.out = io_init(layer, out); + + /* + // some other layers (Conv, pooling) are not supporting 12 d input, we still expand the 1,2 dimension to 3 + // test -> native support 1,2,3 D input. + layer->super.in->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, config->tensor->num_dim, tensor_get_num_channel(config->tensor)); + tensor_cpy_attr(layer->super.in->tensor, config->tensor); + layer->buf = config->tensor->p_data; + layer->dec_bit = config->tensor->q_dec[0]; + */ + + // set parameters + if(config->tensor->num_dim == 1) // test for 1d input, expend h = 1 + layer->shape = shape(1, 1, config->tensor->dim[0]); + else if (config->tensor->num_dim == 2) // test for 1d input, expend h = 1 + layer->shape = shape(1, config->tensor->dim[0], config->tensor->dim[1]); + else + layer->shape = shape(config->tensor->dim[0], config->tensor->dim[1], config->tensor->dim[2]); + layer->buf = config->tensor->p_data; + layer->dec_bit = config->tensor->q_dec[0]; + + // experimental: fixed input dim to 3 + // input normally dont have a tensor, so we create one to store the initial data. + nnom_shape_data_t dim[3] = {layer->shape.h, layer->shape.w, layer->shape.c}; + layer->super.in->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, 3, tensor_get_num_channel(config->tensor)); + tensor_set_attr_v(layer->super.in->tensor, layer->dec_bit, 0, dim, sizeof(dim)/sizeof(nnom_shape_data_t), 8); + return (nnom_layer_t *)layer; +} + +nnom_layer_t *Input(nnom_3d_shape_t input_shape, void *p_buf) +{ + nnom_io_layer_t *layer; + nnom_layer_io_t *in, *out; + + // apply a block memory for all the sub handles. + layer = nnom_mem(sizeof(nnom_io_layer_t) + sizeof(nnom_layer_io_t) * 2); + if (layer == NULL) + return NULL; + + // distribut the memory to sub handles. + in = (void *)((uint8_t*)layer + sizeof(nnom_io_layer_t)); + out = (void *)((uint8_t*)in + sizeof(nnom_layer_io_t)); + + // set type in layer parent + layer->super.type = NNOM_INPUT; + layer->super.run = input_run; + layer->super.build = input_build; + // set buf state + in->type = NNOM_TENSOR_BUF_TEMP; + out->type = NNOM_TENSOR_BUF_NULL; + // put in & out on the layer. + layer->super.in = io_init(layer, in); + layer->super.out = io_init(layer, out); + + // set parameters + layer->shape = input_shape; + layer->buf = p_buf; + layer->dec_bit = 7; + + // experimental: fixed input dim to 3 + // input normally dont have a tensor, so we create one to store the initial data. + nnom_shape_data_t dim[3] = { input_shape.h, input_shape.w, input_shape.c }; + layer->super.in->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, 3, input_shape.c); + tensor_set_attr_v(layer->super.in->tensor, layer->dec_bit, 0, dim, sizeof(dim)/sizeof(nnom_shape_data_t), 8); + return (nnom_layer_t *)layer; +} + +nnom_status_t input_build(nnom_layer_t* layer) +{ + // the input tensor of inputlayer has assigned previously + + // output tensor + // 1. allocate a new tensor for output + // 2. set the same dim, qfmt to the new tensor. + layer->out->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, layer->in->tensor->num_dim, tensor_get_num_channel(layer->in->tensor)); + tensor_cpy_attr(layer->out->tensor, layer->in->tensor); + + // now this build has passed the input tensors (shapes, formats) to the new tensors. + return NN_SUCCESS; +} + + +nnom_status_t input_run(nnom_layer_t *layer) +{ + nnom_io_layer_t *cl = (nnom_io_layer_t *)layer; +#ifdef NNOM_USING_CHW + if(layer->in->tensor->num_dim == 3) + { + nnom_3d_shape_t shape = {layer->in->tensor->dim[0], layer->in->tensor->dim[1], layer->in->tensor->dim[2]}; + hwc2chw_q7(shape, cl->buf, layer->in->tensor->p_data); + } + else if (layer->in->tensor->num_dim == 2) + { + nnom_3d_shape_t shape = {1, layer->in->tensor->dim[0], layer->in->tensor->dim[1]}; + hwc2chw_q7(shape, cl->buf, layer->in->tensor->p_data); + } + else +#endif + nnom_memcpy(layer->in->tensor->p_data, cl->buf, tensor_size(layer->in->tensor)); + + return NN_SUCCESS; +} diff --git a/components/ai/nnom/src/layers/nnom_lambda.c b/components/ai/nnom/src/layers/nnom_lambda.c new file mode 100644 index 000000000..31e9c7c5e --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_lambda.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_lambda.h" + +nnom_layer_t *lambda_s(const nnom_lambda_config_t * config) +{ + nnom_lambda_layer_t *cl = (nnom_lambda_layer_t *)Lambda( + config->run_func_name, + config->build_func_name, + config->free_func_name, + config->parameters); + if(cl) + cl->super.config = (void*) config; + return (nnom_layer_t *)cl; +} + +// TODO: extended to multiple IO layer +nnom_layer_t *Lambda(nnom_status_t (*run)(nnom_layer_t *), + nnom_status_t (*build)(nnom_layer_t *), + nnom_status_t (*free)(nnom_layer_t *), + void *parameters) +{ + nnom_lambda_layer_t *layer; + nnom_layer_io_t *in, *out; + + // apply a block memory for all the sub handles. + size_t mem_size = sizeof(nnom_io_layer_t) + sizeof(nnom_layer_io_t) * 2; + layer = nnom_mem(mem_size); + if (layer == NULL) + return NULL; + + // distribut the memory to sub handles. + in = (void *)((uint8_t*)layer + sizeof(nnom_lambda_layer_t)); + out = (void *)((uint8_t*)in + sizeof(nnom_layer_io_t)); + + // set buf type. + in->type = NNOM_TENSOR_BUF_TEMP; + out->type = NNOM_TENSOR_BUF_TEMP; + + // set io modules to the layer + layer->super.in = io_init(layer, in); + layer->super.out = io_init(layer, out); + // layer type + layer->super.type = NNOM_LAMBDA; + + // user parameters + layer->parameters = parameters; + + // free method + layer->super.free = free; + + // output shape method. pass NULL in will use the default outshape method, which set the output shape same as input shape. + if (build == NULL) + layer->super.build = default_build; + else + layer->super.build = build; + // run method. default_run() will simply copy data from input tensor to output tensor. + if(run == NULL) + layer->super.run = default_run; + else + layer->super.run = run; + + return (nnom_layer_t *)layer; +} diff --git a/components/ai/nnom/src/layers/nnom_lstm_cell.c b/components/ai/nnom/src/layers/nnom_lstm_cell.c new file mode 100644 index 000000000..ed4a120b4 --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_lstm_cell.c @@ -0,0 +1,334 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-24 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_lstm_cell.h" + +#ifdef NNOM_USING_CMSIS_NN +#include "arm_math.h" +#include "arm_nnfunctions.h" +#endif + +// LSTM RNN +// unit = output shape +// type of activation +nnom_rnn_cell_t *lstm_cell_s(const nnom_lstm_cell_config_t* config) +{ + nnom_lstm_cell_t *cell; + cell = nnom_mem(sizeof(nnom_lstm_cell_t)); + if (cell == NULL) + return NULL; + // set methods + cell->super.run = lstm_cell_q7_q15_run; + cell->super.build = lstm_cell_q7_q15_build; + cell->super.free = lstm_cell_free; + cell->super.config = (void*) config; + cell->super.units = config->units; + cell->super.type = NNOM_LSTM_CELL; + + // set parameters + cell->bias = config->bias; + cell->weights = config->weights; + cell->recurrent_weights = config->recurrent_weights; + + // q format for intermediate calculation + cell->q_dec_c = config->q_dec_c; + cell->q_dec_h = config->q_dec_h; + cell->q_dec_z = config->q_dec_z; + + return (nnom_rnn_cell_t *)cell; +} + +nnom_status_t lstm_cell_free(nnom_rnn_cell_t* cell) +{ + return NN_SUCCESS; +} + +// keras implementation as below. +/* + def step(cell_inputs, cell_states): + """Step function that will be used by Keras RNN backend.""" + h_tm1 = cell_states[0] # previous memory state + c_tm1 = cell_states[1] # previous carry state + + z = K.dot(cell_inputs, kernel) -> q_iw + z += K.dot(h_tm1, recurrent_kernel) -> q_hw + z = K.bias_add(z, bias) + + z0, z1, z2, z3 = array_ops.split(z, 4, axis=1) + + i = nn.sigmoid(z0) + f = nn.sigmoid(z1) + c = f * c_tm1 + i * nn.tanh(z2) + o = nn.sigmoid(z3) + + h = o * nn.tanh(c) + return h, [h, c] +*/ + + + +// the state buffer and computational buffer shape of the cell +nnom_status_t lstm_cell_q7_q15_build(nnom_rnn_cell_t* cell) +{ + nnom_layer_t *layer = cell->layer; + nnom_lstm_cell_t *c = (nnom_lstm_cell_t *)cell; + + // calculate output shift for the 2 calculation. + // hw = the product of hidden x weight, iw = the product of input x weight + // due to the addition of them, they must have same q format. + // that is -> c->q_dec_z; + + // for the dots in cell: output shift = input_dec + weight_dec - output_dec + c->oshift_hw = c->q_dec_h + c->recurrent_weights->q_dec[0] - c->q_dec_z; + c->oshift_iw = layer->in->tensor->q_dec[0] + c->weights->q_dec[0] - c->q_dec_z; + + // bias shift = bias_dec - out_dec + c->bias_shift = layer->in->tensor->q_dec[0] + c->weights->q_dec[0] - c->bias->q_dec[0]; + + // state size = one timestamp output size. + cell->state_size = cell->units * 2 * 2; // Q15 + + // // comp buffer size: not required + cell->comp_buf_size = cell->units * 12 * 2 + cell->feature_size * 2; //q15 + input q7->q15 buffer. + + // finally, calculate the MAC for info (for each timestamp) + cell->macc = cell->feature_size * cell->units *4 // input: feature * state * 4 gates + + cell->units * cell->units *4 // recurrent, state + + cell->units *10; // output_unit * (5 gate + 3 mult + 2 addition) + + return NN_SUCCESS; +} + +// Q7 input output +// Q7 weights +// Q15 states and intermediate buffer +nnom_status_t lstm_cell_q7_q15_run(nnom_rnn_cell_t* cell) +{ + nnom_layer_t *layer = cell->layer; + nnom_lstm_cell_t* c = (nnom_lstm_cell_t*) cell; + int act_int_bit = 7 - c->q_dec_z; + + // state buffer + // low |-- hidden --|-- carry --| high + q15_t* h_tm1 = (q15_t*)cell->in_state; + q15_t* c_tm1 = (q15_t*)cell->in_state + cell->units; + q15_t* o_state[2]; + o_state[0] = (q15_t*)cell->out_state; + o_state[1] = (q15_t*)cell->out_state + cell->units; + + // computing buffer + // low |-- buf0 --|-- buf1 --|-- buf2 --|-- input q15 --| + q15_t* z[4]; + q15_t *buf0, *buf1, *buf2, *in_q15_buf; + buf0 = (q15_t*)layer->comp->mem->blk; + buf1 = (q15_t*)layer->comp->mem->blk + cell->units*4; + buf2 = (q15_t*)layer->comp->mem->blk + cell->units*8; + in_q15_buf = (q15_t*)layer->comp->mem->blk + cell->units*12; + + // input q7 -> q15 + local_q7_to_q15(cell->in_data, in_q15_buf, cell->feature_size); + + // z1 = K.dot(cell_inputs, kernel) + bias -> buf1 + #ifdef NNOM_USING_CMSIS_NN + arm_fully_connected_mat_q7_vec_q15_opt + #else + local_fully_connected_mat_q7_vec_q15_opt + #endif + (in_q15_buf, c->weights->p_data, cell->feature_size, cell->units*4, c->bias_shift + 8, c->oshift_iw, c->bias->p_data, buf1, NULL); + + // z2 = K.dot(h_tm1, recurrent_kernel) -> buf2 + // --- arm version must use bias, so we have to use local implementation + local_fully_connected_mat_q7_vec_q15_opt(h_tm1, c->recurrent_weights->p_data, + cell->units, cell->units*4, 0, c->oshift_hw, NULL, buf2, NULL); + + // z = z1 + z2 -> buf0 + local_add_q15(buf1, buf2, buf0, 0, cell->units*4); + + // split the data to each gate + z[0] = buf0; + z[1] = buf0 + cell->units; + z[2] = buf0 + cell->units*2; + z[3] = buf0 + cell->units*3; + + // i = nn.sigmoid(z0) + local_sigmoid_q15(z[0], cell->units, act_int_bit); + // f = nn.sigmoid(z1) + local_sigmoid_q15(z[1], cell->units, act_int_bit); + // o = nn.sigmoid(z3) + local_sigmoid_q15(z[3], cell->units, act_int_bit); + + /* c = f * c_tm1 + i * nn.tanh(z2) for the step 1-3. */ + // 1. i * tanh(z2) -> buf1 + local_tanh_q15(z[2], cell->units, act_int_bit); + local_mult_q15(z[0], z[2], buf1, 30 - (c->q_dec_c+8), cell->units); + // 2. f * c_tm1 -> o_state[0] + local_mult_q15(z[1], c_tm1, o_state[0], 15, cell->units); + // 3. c = i*tanh + f*c_tm1 -> o_state[1] ** fill the upper state (carry) + local_add_q15(buf1, o_state[0], o_state[1], 0, cell->units); + + /* h = o * nn.tanh(c) -> o_state[0] for the step 1-2 */ + // 1. tanh(c) -> buf2 --- first copy then activate. + nnom_memcpy(buf2, o_state[1], cell->units*2); + local_tanh_q15(buf2, cell->units, 7 - c->q_dec_c); // this int bit is under 8bit + // 2. h = o*tanh(c) -> o_state[0] ** fill the lower state (memory, hidden) + local_mult_q15(z[3], buf2, o_state[0], 15, cell->units); + + // copy and shift q15 to q7 ** (copy hidden to output) + local_q15_to_q7(o_state[0], cell->out_data, 8, cell->units); + return NN_SUCCESS; +} + + +// researve for debugging, printing the intermediate products and variables +#if 0 +static void print_variable(q7_t* data,char*name, int dec_bit, int size) +{ + printf("\n"); + printf("%s\n", name); + for(int i = 0; i < size; i++) + { + if(i%8==0) + printf("\n"); + printf("%f\t", (float) data[i] / (1 << dec_bit)); + } + printf("\n"); +} + +static void print_variable_q15(q15_t *data,char*name, int dec_bit, int size) +{ + printf("\n\n"); + printf("%s", name); + for(int i = 0; i < size; i++) + { + if(i%8==0) + printf("\n"); + printf("%f\t", (float) data[i] / (1 << dec_bit)); + } + printf("\n"); +} + + +// Q7 input output +// Q7 weights +// Q15 states and intermediate buffer +nnom_status_t lstm_cell_q7_q15_run(nnom_rnn_cell_t* cell) +{ + nnom_layer_t *layer = cell->layer; + nnom_rnn_layer_t* cl = (nnom_rnn_layer_t *) layer; + nnom_lstm_cell_t* c = (nnom_lstm_cell_t*) cell; + int act_int_bit = 7 - c->q_dec_z; + + // test + //nnom_memset(cell->in_data, 32, cell->feature_size); + + // state buffer + // low |-- hidden --|-- carry --| high + q15_t* h_tm1 = (q15_t*)cell->in_state; + q15_t* c_tm1 = (q15_t*)cell->in_state + cell->units; + q15_t* o_state[2]; + o_state[0] = (q15_t*)cell->out_state; + o_state[1] = (q15_t*)cell->out_state + cell->units; + + // computing buffer + // low |-- buf0 --|-- buf1 --|-- buf2 --|-- input q15 --| + q15_t* z[4]; + q15_t *buf0, *buf1, *buf2, *in_q15_buf; + buf0 = (q15_t*)layer->comp->mem->blk; + buf1 = (q15_t*)layer->comp->mem->blk + cell->units*4; + buf2 = (q15_t*)layer->comp->mem->blk + cell->units*8; + in_q15_buf = (q15_t*)layer->comp->mem->blk + cell->units*12; + + // input q7 -> q15 + //local_q7_to_q15_no_shift(cell->in_data, in_q15_buf, cell->feature_size); + local_q7_to_q15(cell->in_data, in_q15_buf, cell->feature_size); + print_variable_q15(in_q15_buf, "input", layer->in->tensor->q_dec[0] + 8, cell->feature_size); + print_variable_q15(h_tm1, "h_tml", 15, cell->units); + print_variable_q15(c_tm1, "c_tml", c->q_dec_c + 8, cell->units); + + // z1 = K.dot(cell_inputs, kernel) + bias -> buf1 + #ifdef NNOM_USING_CMSIS_NN + arm_fully_connected_mat_q7_vec_q15_opt + #else + local_fully_connected_mat_q7_vec_q15_opt + #endif + (in_q15_buf, c->weights->p_data, cell->feature_size, cell->units*4, c->bias_shift + 8, c->oshift_iw, c->bias->p_data, buf1, NULL); + + // z2 = K.dot(h_tm1, recurrent_kernel) -> buf2 + // arm version must use bias, so we have to use local implementation + local_fully_connected_mat_q7_vec_q15_opt(h_tm1, c->recurrent_weights->p_data, + cell->units, cell->units*4, 0, c->oshift_hw, NULL, buf2, NULL); + + // z = z1 + z2 -> buf0 + local_add_q15(buf1, buf2, buf0, 0, cell->units*4); + + print_variable_q15(buf0, "z", c->q_dec_z + 8, cell->units*4); + print_variable_q15(buf1, "z1", c->q_dec_z + 8, cell->units*4); + print_variable_q15(buf2, "z2", c->q_dec_z + 8, cell->units*4); + + // split the data to each gate + z[0] = buf0; + z[1] = buf0 + cell->units; + z[2] = buf0 + cell->units*2; + z[3] = buf0 + cell->units*3; + + // i = nn.sigmoid(z0) + local_sigmoid_q15(z[0], cell->units, act_int_bit); + // f = nn.sigmoid(z1) + local_sigmoid_q15(z[1], cell->units, act_int_bit); + // o = nn.sigmoid(z3) + local_sigmoid_q15(z[3], cell->units, act_int_bit); + + print_variable_q15(z[0], "z[0] - i", 15, cell->units); + print_variable_q15(z[1], "z[1] - f", 15, cell->units); + print_variable_q15(z[3], "z[3] - o", 15, cell->units); + + /* c = f * c_tm1 + i * nn.tanh(z2) for the step 1-3. */ + // 1. i * tanh(z2) -> buf1 + local_tanh_q15(z[2], cell->units, act_int_bit); + print_variable_q15(z[2], "z[2] - ?", 15, cell->units); + + local_mult_q15(z[0], z[2], buf1, 30 - (c->q_dec_c+8), cell->units); //q0.15 * q0.15 >> (shift) = (q_c + 8) // i am not very sure + print_variable_q15(buf1, "c2: i * tanh(z2) ", c->q_dec_c+8, cell->units); + + // 2. f * c_tm1 -> o_state[0] + local_mult_q15(z[1], c_tm1, o_state[0], 15, cell->units); + print_variable_q15(o_state[0], "c1: f * c_tm1", c->q_dec_c+8, cell->units); + + // 3. c = i*tanh + f*c_tm1 -> o_state[1] ** fill the upper state (carry) + local_add_q15(buf1, o_state[0], o_state[1], 0, cell->units); + print_variable_q15(o_state[1], "c = c1+c2", c->q_dec_c+8, cell->units); + + /* h = o * nn.tanh(c) -> o_state[0] for the step 1-2 */ + // 1. tanh(c) -> buf2 --- first copy then activate. + nnom_memcpy(buf2, o_state[1], cell->units*2); + local_tanh_q15(buf2, cell->units, 7 - c->q_dec_c); // this int bit is under 8bit + print_variable_q15(buf2, "tanh(c)", 15, cell->units); + + // 2. h = o*tanh(c) -> o_state[0] ** fill the lower state (memory, hidden) + local_mult_q15(z[3], buf2, o_state[0], 15, cell->units); + print_variable_q15(o_state[0], "h = o*tanh(c)", 15, cell->units); + + // copy and shift q15 to q7 ** (copy hidden to output) + local_q15_to_q7(o_state[0], cell->out_data, 8, cell->units); + + print_variable(cell->out_data, "q7 output)", 7, cell->units); + + return NN_SUCCESS; +} +#endif diff --git a/components/ai/nnom/src/layers/nnom_matrix.c b/components/ai/nnom/src/layers/nnom_matrix.c new file mode 100644 index 000000000..e011ecc0f --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_matrix.c @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_matrix.h" + +// TODO, completely change this file to local version +#ifdef NNOM_USING_CMSIS_NN +#include "arm_math.h" +#include "arm_nnfunctions.h" +#endif + +nnom_status_t matrix_build(nnom_layer_t *layer); + +nnom_layer_t *add_s(const nnom_matrix_config_t * config) +{ + nnom_matrix_layer_t *cl = (nnom_matrix_layer_t *) Add(config->output_shift); + if(cl) + cl->super.config = (void*) config; + return (nnom_layer_t *)cl; +} + +nnom_layer_t *sub_s(const nnom_matrix_config_t * config) +{ + nnom_matrix_layer_t *cl = (nnom_matrix_layer_t *) Sub(config->output_shift); + if(cl) + cl->super.config = (void*) config; + return (nnom_layer_t *)cl; +} + +nnom_layer_t *mult_s(const nnom_matrix_config_t * config) +{ + nnom_matrix_layer_t *cl = (nnom_matrix_layer_t *) Mult(config->output_shift); + if(cl) + cl->super.config = (void*) config; + return (nnom_layer_t *)cl; +} + +nnom_layer_t *Add(int16_t oshift) +{ + nnom_matrix_layer_t *cl = (nnom_matrix_layer_t *)_same_shape_matrix_layer(); + if (cl == NULL) + return NULL; + // set type in layer parent + cl->super.type = NNOM_ADD; + cl->super.run = add_run; + cl->oshift = oshift; + return (nnom_layer_t *)cl; +} + +nnom_layer_t *Sub(int16_t oshift) +{ + nnom_matrix_layer_t *cl = (nnom_matrix_layer_t *)_same_shape_matrix_layer(); + if (cl == NULL) + return NULL; + // set type in layer parent + cl->super.type = NNOM_SUB; + cl->super.run = sub_run; + cl->oshift = oshift; + return (nnom_layer_t *)cl; +} + +nnom_layer_t *Mult(int16_t oshift) +{ + nnom_matrix_layer_t *cl = (nnom_matrix_layer_t *)_same_shape_matrix_layer(); + if (cl == NULL) + return NULL; + // set type in layer parent + cl->super.type = NNOM_MULT; + cl->super.run = mult_run; + cl->oshift = oshift; + return (nnom_layer_t *)cl; +} + +// init a base layer instance with same shape 1 in 1 out. More IO can be added later +// mainly used by matrix calculation (add, mult, sub) +nnom_layer_t *_same_shape_matrix_layer() +{ + nnom_matrix_layer_t *layer; + nnom_layer_io_t *in, *out; + //nnom_buf_t *comp; + size_t mem_size; + + // apply a block memory for all the sub handles. + mem_size = sizeof(nnom_matrix_layer_t) + sizeof(nnom_layer_io_t) * 2; + layer = nnom_mem(mem_size); + if (layer == NULL) + return NULL; + + // distribut the memory to sub handles. + in = (void *)((uint8_t*)layer + sizeof(nnom_matrix_layer_t)); + out = (void *)((uint8_t*)in + sizeof(nnom_layer_io_t)); + //comp = (void *)((uint8_t*)out + sizeof(nnom_layer_io_t)); + + // set type in layer parent + layer->super.build = matrix_build; + // set buf state + in->type = NNOM_TENSOR_BUF_TEMP; + out->type = NNOM_TENSOR_BUF_TEMP; + //comp->type = NNOM_TENSOR_BUF_TEMP; + // put in & out on the layer. + layer->super.in = io_init(layer, in); + layer->super.out = io_init(layer, out); + //layer->super.comp = comp; + return (nnom_layer_t*)layer; +} + +nnom_status_t matrix_build(nnom_layer_t *layer) +{ + // get the last layer's output as input shape (if more than one) + nnom_layer_io_t *in = layer->in; + while(in) + { + in->tensor = in->hook.io->tensor; + in = in->aux; + } + // output tensor + layer->out->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR,layer->in->tensor->num_dim, tensor_get_num_channel(layer->in->tensor)); + tensor_cpy_attr(layer->out->tensor, layer->in->tensor); + + // see if the activation will change the q format + if(layer->actail) + layer->out->tensor->q_dec[0] = act_get_dec_bit(layer->actail->type, layer->out->tensor->q_dec[0]); + + // now this build has passed the input tensors (shapes, formats) to the new tensors. + return NN_SUCCESS; +} + + +nnom_status_t add_run(nnom_layer_t *layer) +{ + nnom_matrix_layer_t* cl = (nnom_matrix_layer_t*)layer; + nnom_layer_io_t *in = layer->in;; + size_t t_size = tensor_size(layer->out->tensor); + int32_t oshift = cl->oshift; + size_t num_input = nnom_io_length(layer->in); + q7_t *input_mem_blk[MAX_INPUT_LAYER]; + + // if there is only 2 matrix + if(num_input == 2) + { + #ifdef NNOM_USING_CMSIS_NN + if(oshift == 0) + arm_add_q7(layer->in->tensor->p_data, layer->in->aux->tensor->p_data, layer->out->tensor->p_data, t_size); + else + #endif + local_add_q7(layer->in->tensor->p_data, layer->in->aux->tensor->p_data, layer->out->tensor->p_data, oshift, t_size); + } + else + { + for(int i = 0; i < num_input; i++) + { + input_mem_blk[i] = in->tensor->p_data; + in = in->aux; + } + local_multiple_add_q7(layer->out->tensor->p_data, oshift, t_size, num_input, input_mem_blk); + } + + return NN_SUCCESS; +} + +nnom_status_t sub_run(nnom_layer_t *layer) +{ + nnom_matrix_layer_t* cl = (nnom_matrix_layer_t*)layer; + nnom_layer_io_t *in = layer->in; + size_t t_size = tensor_size(layer->out->tensor); + int32_t oshift = cl->oshift; + size_t num_input = nnom_io_length(layer->in); + q7_t *input_mem_blk[MAX_INPUT_LAYER]; + + // if there is only 2 matrix + if(num_input == 2) + { + // the first 2 matrix + #ifdef NNOM_USING_CMSIS_NN + if(oshift == 0) + arm_sub_q7(layer->in->tensor->p_data, layer->in->aux->tensor->p_data, layer->out->tensor->p_data, t_size); + else + #endif + local_sub_q7(layer->in->tensor->p_data, layer->in->aux->tensor->p_data, layer->out->tensor->p_data, oshift, t_size); + } + else + { + for(int i = 0; i < num_input; i++) + { + input_mem_blk[i] = in->tensor->p_data; + in = in->aux; + } + local_multiple_sub_q7(layer->out->tensor->p_data, oshift, t_size, num_input, input_mem_blk); + } + return NN_SUCCESS; +} + +nnom_status_t mult_run(nnom_layer_t *layer) +{ + nnom_matrix_layer_t* cl = (nnom_matrix_layer_t*)layer; + nnom_layer_io_t *in = layer->in; + size_t t_size = tensor_size(layer->out->tensor); + int32_t oshift = cl->oshift; + size_t num_input = nnom_io_length(layer->in); + q7_t *input_mem_blk[MAX_INPUT_LAYER]; + + // if there is only 2 matrix + if(num_input == 2) + { + // the first 2 matrix + #ifdef NNOM_USING_CMSIS_NN + if(oshift == 0) + arm_mult_q7(layer->in->tensor->p_data, layer->in->aux->tensor->p_data, layer->out->tensor->p_data, t_size); + else + #endif + local_mult_q7(layer->in->tensor->p_data, layer->in->aux->tensor->p_data, layer->out->tensor->p_data, oshift, t_size); + } + else + { + for(int i = 0; i < num_input; i++) + { + input_mem_blk[i] = in->tensor->p_data; + in = in->aux; + } + local_multiple_mult_q7(layer->out->tensor->p_data, oshift, t_size, num_input, input_mem_blk); + } + return NN_SUCCESS; +} diff --git a/components/ai/nnom/src/layers/nnom_maxpool.c b/components/ai/nnom/src/layers/nnom_maxpool.c new file mode 100644 index 000000000..fe904bad8 --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_maxpool.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_maxpool.h" + +#ifdef NNOM_USING_CMSIS_NN +#include "arm_math.h" +#include "arm_nnfunctions.h" +#endif + +nnom_layer_t *maxpool_s(const nnom_pool_config_t * config) +{ + nnom_layer_t *layer; + + // test, to accomodate 1d and 2d input + if(config->num_dim == 1) + { + layer = MaxPool(kernel(1, config->kernel_size[0]), + stride(1, config->stride_size[0]), + config->padding_type); + } + else + { + layer = MaxPool(kernel(config->kernel_size[0], config->kernel_size[1]), + stride(config->stride_size[0], config->stride_size[1]), + config->padding_type); + } + + if(layer) + layer->config = (void*) config; + return layer; +} + +nnom_layer_t *MaxPool(nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_padding_t pad_type) +{ + nnom_maxpool_layer_t *layer; + nnom_buf_t *comp; + nnom_layer_io_t *in, *out; + + // apply a block memory for all the sub handles. + size_t mem_size = sizeof(nnom_maxpool_layer_t) + sizeof(nnom_layer_io_t) * 2 + sizeof(nnom_buf_t); + layer = nnom_mem(mem_size); + if (layer == NULL) + return NULL; + + // distribut the memory to sub handles. + in = (void *)((uint8_t*)layer + sizeof(nnom_maxpool_layer_t)); + out = (void *)((uint8_t*)in + sizeof(nnom_layer_io_t)); + comp = (void *)((uint8_t*)out + sizeof(nnom_layer_io_t)); + + // set type in layer parent + layer->super.type = NNOM_MAXPOOL; + layer->super.run = maxpool_run; + layer->super.build = maxpool_build; + // set buf state + in->type = NNOM_TENSOR_BUF_TEMP; + out->type = NNOM_TENSOR_BUF_TEMP; + comp->type = NNOM_TENSOR_BUF_TEMP; + // put in & out on the layer. + layer->super.in = io_init(layer, in); + layer->super.out = io_init(layer, out); + layer->super.comp = comp; + + // set parameters + layer->kernel = k; + layer->stride = s; + layer->padding_type = pad_type; + + // padding + if (layer->padding_type == PADDING_SAME) + { + layer->pad.h = (k.h - 1) / 2; + layer->pad.w = (k.w - 1) / 2; + layer->pad.c = 1; // no meaning + } + else + { + layer->pad.h = 0; + layer->pad.w = 0; + layer->pad.c = 0; + } + return (nnom_layer_t *)layer; +} + +nnom_status_t maxpool_build(nnom_layer_t *layer) +{ + nnom_maxpool_layer_t *cl = (nnom_maxpool_layer_t *)layer; + + // get the tensor from last layer's output + layer->in->tensor = layer->in->hook.io->tensor; + + // create new tensor for output + layer->out->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, layer->in->tensor->num_dim, tensor_get_num_channel(layer->in->tensor)); + // copy then change later. + tensor_cpy_attr(layer->out->tensor, layer->in->tensor); + + // see if the activation will change the q format + if(layer->actail) + layer->out->tensor->q_dec[0] = act_get_dec_bit(layer->actail->type, layer->out->tensor->q_dec[0]); + + // now we set up the tensor shape, always HWC format + if (cl->padding_type == PADDING_SAME) + { + layer->out->tensor->dim[0] = NN_CEILIF(layer->in->tensor->dim[0], cl->stride.h); + layer->out->tensor->dim[1] = NN_CEILIF(layer->in->tensor->dim[1], cl->stride.w); + layer->out->tensor->dim[2] = layer->in->tensor->dim[2]; // channel stays the same + } + else + { + layer->out->tensor->dim[0] = NN_CEILIF(layer->in->tensor->dim[0] - cl->kernel.h + 1, cl->stride.h); + layer->out->tensor->dim[1] = NN_CEILIF(layer->in->tensor->dim[1] - cl->kernel.w + 1, cl->stride.w); + layer->out->tensor->dim[2] = layer->in->tensor->dim[2]; + } + + return NN_SUCCESS; +} + +nnom_status_t maxpool_run(nnom_layer_t *layer) +{ + nnom_maxpool_layer_t *cl = (nnom_maxpool_layer_t *)(layer); + + uint16_t out_x, out_y; + + // if global pooling + if(layer->out->tensor->num_dim == 1) + { + out_x = 1; out_y = 1; + } + else // normal pooling. + { + out_x = layer->out->tensor->dim[1]; //W + out_y = layer->out->tensor->dim[0]; //h + } + +#ifdef NNOM_USING_CHW + local_maxpool_q7_CHW(layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->kernel.w, cl->kernel.h, + cl->pad.w, cl->pad.h, + cl->stride.w, cl->stride.h, + out_x, out_y, + NULL, + layer->out->tensor->p_data); +#else //end of CHW + // HWC + #ifdef NNOM_USING_CMSIS_NN + // 2D, square + if (layer->in->tensor->dim[1] == layer->in->tensor->dim[0] && + layer->out->tensor->dim[1] == layer->out->tensor->dim[0]) + { + arm_maxpool_q7_HWC( + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[2], + cl->kernel.w, cl->pad.w, cl->stride.w, + layer->out->tensor->dim[1], + NULL, + layer->out->tensor->p_data); + } + // none square 2D, or 1D + else + #endif + { + // CMSIS-NN does not support none-square pooling, we have to use local implementation + local_maxpool_q7_HWC(layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->kernel.w, cl->kernel.h, + cl->pad.w, cl->pad.h, + cl->stride.w, cl->stride.h, + out_x, out_y, + NULL, + layer->out->tensor->p_data); + } +#endif // CHW/HWC + return NN_SUCCESS; +} diff --git a/components/ai/nnom/src/layers/nnom_output.c b/components/ai/nnom/src/layers/nnom_output.c new file mode 100644 index 000000000..bed1c89cd --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_output.c @@ -0,0 +1,54 @@ + +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_output.h" + +nnom_layer_t *output_s(const nnom_io_config_t* config) +{ + nnom_layer_t *layer = input_s(config); + if(layer) + { + layer->config = (void*) config; + layer->type = NNOM_OUTPUT; + layer->run = output_run; + layer->build = default_build; + } + return layer; +} + +nnom_layer_t *Output(nnom_3d_shape_t output_shape, void *p_buf) +{ + // they are acturally the same.. expect the type defined + nnom_layer_t *layer = Input(output_shape, p_buf); + if (layer != NULL) + { + layer->type = NNOM_OUTPUT; + layer->run = output_run; + layer->build = default_build; + } + return layer; +} + +nnom_status_t output_run(nnom_layer_t *layer) +{ + nnom_io_layer_t *cl = (nnom_io_layer_t *)layer; + nnom_memcpy(cl->buf, layer->in->tensor->p_data, tensor_size(layer->out->tensor)); // in->memory -> user memory + return NN_SUCCESS; +} diff --git a/components/ai/nnom/src/layers/nnom_rnn.c b/components/ai/nnom/src/layers/nnom_rnn.c new file mode 100644 index 000000000..6fe9662e0 --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_rnn.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_rnn.h" + +nnom_status_t rnn_build(nnom_layer_t *layer); +nnom_status_t rnn_run(nnom_layer_t *layer); +nnom_status_t rnn_free(nnom_layer_t* layer); + +// RNN +nnom_layer_t *rnn_s(nnom_rnn_cell_t *cell, const nnom_rnn_config_t* config) +{ + nnom_rnn_layer_t *layer; + nnom_buf_t *comp; + nnom_layer_io_t *in, *out; + + // apply a block memory for all the sub handles. + size_t mem_size = sizeof(nnom_rnn_layer_t) + sizeof(nnom_layer_io_t) * 2 + sizeof(nnom_buf_t); + layer = nnom_mem(mem_size); + if (layer == NULL) + return NULL; + + // distribut the memory to sub handles. + in = (void *)((uint8_t*)layer + sizeof(nnom_rnn_layer_t)); + out = (void *)((uint8_t*)in + sizeof(nnom_layer_io_t)); + comp = (void *)((uint8_t*)out + sizeof(nnom_layer_io_t)); + + // set type in layer parent + layer->super.type = NNOM_RNN; + // set buf state + in->type = NNOM_TENSOR_BUF_TEMP; + out->type = NNOM_TENSOR_BUF_TEMP; + comp->type = NNOM_TENSOR_BUF_TEMP; + // put in & out on the layer. + layer->super.in = io_init(layer, in); + layer->super.out = io_init(layer, out); + layer->super.comp = comp; + // set run and outshape methods + layer->super.run = rnn_run; + layer->super.build = rnn_build; + layer->super.free = rnn_free; + + // rnn parameters. + layer->return_sequence = config->return_sequence; + layer->stateful = config->stateful; + layer->go_backwards = config->go_backwards; + layer->super.config = (void*)config; + layer->cell = cell; + + // set this layer to the cell + layer->cell->layer = (nnom_layer_t *)layer; + + return (nnom_layer_t *)layer; +} + +nnom_status_t rnn_free(nnom_layer_t* layer) +{ + nnom_rnn_layer_t* cl = (nnom_rnn_layer_t*)layer; + // free cell + if(cl->cell->free) + cl->cell->free(cl->cell); + + // free state buffer + nnom_free(cl->state_buf); + + return NN_SUCCESS; +} + +nnom_status_t rnn_build(nnom_layer_t* layer) +{ + nnom_rnn_layer_t *cl = (nnom_rnn_layer_t *)layer; + + // get the tensor from last layer's output + layer->in->tensor = layer->in->hook.io->tensor; + + // timestamp size + cl->timestamp_size = layer->in->tensor->num_dim > 2 ? layer->in->tensor->dim[1] : layer->in->tensor->dim[0]; + + if(cl->return_sequence) + { + // create new tensor for the output + layer->out->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, 2, 0); + // shape: timestamp, units + layer->out->tensor->dim[0] = cl->timestamp_size; + layer->out->tensor->dim[1] = cl->cell->units; + } + else + { + // create new tensor for the output + layer->out->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, 1, 0); + // shape: timestamp, units + layer->out->tensor->dim[0] = cl->cell->units; + } + + // output q format - the output of the available activations are both q0.7. + layer->out->tensor->q_dec[0] = layer->in->tensor->bitwidth==16? 15: 7; + layer->out->tensor->bitwidth = layer->in->tensor->bitwidth; + // see if the activation will change the q format + if(layer->actail) + layer->out->tensor->q_dec[0] = act_get_dec_bit(layer->actail->type, layer->out->tensor->q_dec[0]); + + // get feature size from input tensor + cl->cell->feature_size = tensor_get_num_channel(layer->in->tensor); // vector (feature) size + + // call cell builder to build the cell + cl->cell->build(cl->cell); + + // get the size of computation buffer? + cl->super.comp->size = cl->cell->comp_buf_size; // size of intermediate buffer required by the cell. + cl->state_buf = nnom_mem(cl->cell->state_size * 2); // allocate state buf for upper/lower state buffer. + if(!cl->state_buf) + return NN_NO_MEMORY; + + // get the computational cost provided by Cell + layer->stat.macc = cl->cell->macc * cl->timestamp_size; + return NN_SUCCESS; +} + +nnom_status_t rnn_run(nnom_layer_t* layer) +{ + nnom_status_t result; + nnom_rnn_layer_t* cl = (nnom_rnn_layer_t*)(layer); + size_t timestamps_size = layer->in->tensor->dim[layer->in->tensor->num_dim-2]; + size_t feature_size = tensor_get_num_channel(layer->in->tensor); // feature size = last dimension. + size_t state_size = cl->cell->state_size; + size_t output_growth; + void* upper_state = (q7_t*)cl->state_buf + state_size; + void* lower_state = (q7_t*)cl->state_buf; + + // reset state buffer if not in stateful + if (!cl->stateful) + nnom_memset(cl->state_buf, 0, state_size * 2); + + // set output data + output_growth = cl->return_sequence ? cl->cell->units : 0; + + // run timestamp by timestamp + for (uint32_t round = 0; round < timestamps_size; round++) + { + if(cl->go_backwards) + { + // set input data + cl->cell->in_data = (q7_t*)layer->in->tensor->p_data + feature_size*(timestamps_size - 1 - round); + // set output data + cl->cell->out_data = (q7_t*)layer->out->tensor->p_data + output_growth*(timestamps_size - 1 - round); + } + else + { + // set input data + cl->cell->in_data = (q7_t*)layer->in->tensor->p_data + feature_size*round; + // set output data + cl->cell->out_data = (q7_t*)layer->out->tensor->p_data + output_growth*round; + } + + // switch upper/lower state buffer + if(cl->cell->in_state != lower_state) + { + cl->cell->in_state = lower_state; + cl->cell->out_state = upper_state; + } + else + { + cl->cell->in_state = upper_state; + cl->cell->out_state = lower_state; + } + + // run it + result = cl->cell->run(cl->cell); + if(result != NN_SUCCESS) + return result; + } + + return NN_SUCCESS; +} + diff --git a/components/ai/nnom/src/layers/nnom_simple_cell.c b/components/ai/nnom/src/layers/nnom_simple_cell.c new file mode 100644 index 000000000..b61acbef3 --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_simple_cell.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-08-21 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_simple_cell.h" + +#ifdef NNOM_USING_CMSIS_NN +#include "arm_math.h" +#include "arm_nnfunctions.h" +#endif + +// Simple RNN +// unit = output shape +// type of activation +nnom_rnn_cell_t *simple_cell_s(const nnom_simple_cell_config_t* config) +{ + nnom_simple_cell_t *cell; + cell = nnom_mem(sizeof(nnom_simple_cell_t)); + if (cell == NULL) + return NULL; + // set methods + cell->super.run = simple_cell_run; + cell->super.build = simple_cell_build; + cell->super.free = simple_cell_free; + cell->super.config = (void*) config; + cell->super.units = config->units; + cell->super.type = NNOM_SIMPLE_CELL; + + // set parameters + cell->bias = config->bias; + cell->weights = config->weights; + cell->recurrent_weights = config->recurrent_weights; + cell->act_type = config->act_type; + // q format for intermediate products + cell->q_dec_iw = config->q_dec_iw; + cell->q_dec_hw = config->q_dec_hw; + cell->q_dec_h = config->q_dec_h; + + return (nnom_rnn_cell_t *)cell; +} + +nnom_status_t simple_cell_free(nnom_rnn_cell_t* cell) +{ + return NN_SUCCESS; +} + +// the state buffer and computational buffer shape of the cell +nnom_status_t simple_cell_build(nnom_rnn_cell_t* cell) +{ + nnom_layer_t *layer = cell->layer; + nnom_simple_cell_t *c = (nnom_simple_cell_t *)cell; + nnom_simple_cell_config_t *config = (nnom_simple_cell_config_t *)cell->config; + int q_hw_iw; + + // activation, check if activation is supported + if(config->act_type != ACT_SIGMOID && config->act_type != ACT_TANH) + return NN_ARGUMENT_ERROR; + + // calculate output shift for the 2 calculation. + // hw = the product of hidden x weight, iw = the product of input x weight + // due to the addition of them, they must have same q format. + q_hw_iw = MIN(c->q_dec_hw, c->q_dec_iw); + + // for the 2 dot in cell: output shift = input_dec + weight_dec - output_dec + c->oshift_hw = c->q_dec_h + c->recurrent_weights->q_dec[0] - q_hw_iw; + c->oshift_iw = layer->in->tensor->q_dec[0] + c->weights->q_dec[0] - q_hw_iw; + + // bias shift = bias_dec - out_dec + c->bias_shift = layer->in->tensor->q_dec[0] + c->weights->q_dec[0] - c->bias->q_dec[0]; + + // state size = one timestamp output size. + cell->state_size = cell->units; + + // comp buffer size: not required + cell->comp_buf_size = 0; + + // finally, calculate the MAC for info + cell->macc = cell->feature_size * cell->units // input: feature * state + + cell->units * cell->units; // recurrent, state * output_unit + + return NN_SUCCESS; +} + +// This Simple Cell replicate the Keras's SimpleCell as blow +/* + def call(self, inputs, states, training=None): + prev_output = states[0] if nest.is_sequence(states) else states + + h = K.dot(inputs, self.kernel) + h = K.bias_add(h, self.bias) + + h2 = K.dot(prev_output, self.recurrent_kernel) + output = h + H2 + output = self.activation(output) + + new_state = [output] if nest.is_sequence(states) else output + return output, new_state +*/ + +nnom_status_t simple_cell_run(nnom_rnn_cell_t* cell) +{ + nnom_simple_cell_t* c = (nnom_simple_cell_t*) cell; + int act_int_bit = 7 - MIN(c->q_dec_hw, c->q_dec_iw); + + // in_state x recurrent_weight -> h2 (output buf) + local_dot_q7_opt(cell->in_state, c->recurrent_weights->p_data, cell->units, cell->units, c->oshift_hw, cell->out_data); + // (input x weight) + bias -> h (in_state buf) + local_fully_connected_q7_opt(cell->in_data, c->weights->p_data, + cell->feature_size, cell->units, c->bias_shift, c->oshift_iw, c->bias->p_data, cell->in_state, NULL); + // h + h2 -> (out_state buf) + local_add_q7(cell->in_state, cell->out_data, cell->out_state, 0, cell->units); + + // active(out_state buf) + if(c->act_type == ACT_TANH) + local_tanh_q7(cell->out_state, cell->units, act_int_bit); + //local_hard_tanh_q7(cell->out_state, cell->units, act_int_bit); + else + local_sigmoid_q7(cell->out_state, cell->units, act_int_bit); + //local_hard_sigmoid_q7(cell->out_state, cell->units, act_int_bit); + + // (out_state buf) --copy--> (output buf) + nnom_memcpy(cell->out_data, cell->out_state, cell->units); + + return NN_SUCCESS; +} + + diff --git a/components/ai/nnom/src/layers/nnom_softmax.c b/components/ai/nnom/src/layers/nnom_softmax.c new file mode 100644 index 000000000..04b009b35 --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_softmax.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_softmax.h" + +#ifdef NNOM_USING_CMSIS_NN +#include "arm_math.h" +#include "arm_nnfunctions.h" +#endif + +nnom_layer_t *softmax_s(const nnom_softmax_config_t * config) +{ + nnom_layer_t * layer = Softmax(); + if(layer) + layer->config = (void*) config; + return layer; +} + +nnom_layer_t *Softmax(void) +{ + nnom_layer_t *layer; + nnom_layer_io_t *in, *out; + + // apply a block memory for all the sub handles. + size_t mem_size = sizeof(nnom_layer_t) + sizeof(nnom_layer_io_t) * 2; + layer = nnom_mem(mem_size); + if (layer == NULL) + return NULL; + + // distribut the memory to sub handles. + in = (void *)((uint8_t*)layer + sizeof(nnom_layer_t)); + out = (void *)((uint8_t*)in + sizeof(nnom_layer_io_t)); + + // set type in layer parent + layer->type = NNOM_SOFTMAX; + layer->run = softmax_run; + layer->build = softmax_build; + // set buf state + in->type = NNOM_TENSOR_BUF_TEMP; + out->type = NNOM_TENSOR_BUF_TEMP; + // put in & out on the layer. + layer->in = io_init(layer, in); + layer->out = io_init(layer, out); + + return layer; +} + +nnom_status_t softmax_build(nnom_layer_t *layer) +{ + // get the last layer's output as input shape + layer->in->tensor = layer->in->hook.io->tensor; + // output tensor + layer->out->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, layer->in->tensor->num_dim, tensor_get_num_channel(layer->in->tensor)); + tensor_cpy_attr(layer->out->tensor, layer->in->tensor); + // softmax has fixed output dec bit + layer->out->tensor->q_dec[0] = 7; + return NN_SUCCESS; +} + +nnom_status_t softmax_run(nnom_layer_t *layer) +{ + // looks like the new version cause accuracy drop quite a lot. +// #ifdef NNOM_USING_CMSIS_NN +// // temporary fixed for mutiple dimension input. +// arm_softmax_q7(layer->in->tensor->p_data, tensor_size(layer->out->tensor), layer->out->tensor->p_data); +// #else + local_softmax_q7(layer->in->tensor->p_data, tensor_size(layer->out->tensor), layer->out->tensor->p_data); + //#endif + return NN_SUCCESS; +} diff --git a/components/ai/nnom/src/layers/nnom_sumpool.c b/components/ai/nnom/src/layers/nnom_sumpool.c new file mode 100644 index 000000000..82de147c4 --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_sumpool.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_sumpool.h" + +nnom_layer_t *sumpool_s(const nnom_pool_config_t * config) +{ + nnom_sumpool_layer_t *cl; + if(config->num_dim == 1) + { + cl = (nnom_sumpool_layer_t *)SumPool(kernel(1, config->kernel_size[0]), + stride(1, config->stride_size[0]), + config->padding_type); + } + else + { + cl = (nnom_sumpool_layer_t *)SumPool(kernel(config->kernel_size[0], config->kernel_size[1]), + stride(config->stride_size[0], config->stride_size[1]), + config->padding_type); + } + if(cl) + { + cl->super.config = (void*) config; + cl->output_shift = config->output_shift; // no idea if we need it + } + return (nnom_layer_t *)cl; +} + + +nnom_layer_t *SumPool(nnom_3d_shape_t k, nnom_3d_shape_t s, nnom_padding_t pad_type) +{ + nnom_layer_t *layer = MaxPool(k, s, pad_type); + + if (layer != NULL) + { + layer->type = NNOM_SUMPOOL; + layer->run = sumpool_run; + layer->build = sumpool_build; + } + return (nnom_layer_t *)layer; +} + + +nnom_status_t sumpool_build(nnom_layer_t *layer) +{ + // avg pooling share the same output shape, stride, padding setting. + maxpool_build(layer); + + // however, avg pooling require a computational buffer. + layer->comp->size = 4 * tensor_size(layer->out->tensor); + + return NN_SUCCESS; +} + + +// sum pooling, dynamic change Q format, must be used in the last layer before softmax in current version +nnom_status_t sumpool_run(nnom_layer_t *layer) +{ + nnom_sumpool_layer_t *cl = (nnom_sumpool_layer_t *)(layer); + uint16_t out_x, out_y; + + // if global pooling + if(layer->out->tensor->num_dim == 1) + { + out_x = 1; out_y = 1; + } + else // normal pooling. + { + out_x = layer->out->tensor->dim[1]; //W + out_y = layer->out->tensor->dim[0]; //h + } + +#ifdef NNOM_USING_CHW + local_sumpool_q7_CHW( +#else + local_sumpool_q7_HWC( +#endif + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->kernel.w, cl->kernel.h, + cl->pad.w, cl->pad.h, + cl->stride.w, cl->stride.h, + out_x, out_y, + layer->comp->mem->blk, + layer->out->tensor->p_data); + + return NN_SUCCESS; +} diff --git a/components/ai/nnom/src/layers/nnom_upsample.c b/components/ai/nnom/src/layers/nnom_upsample.c new file mode 100644 index 000000000..96472a5ab --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_upsample.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_upsample.h" + +nnom_layer_t *upsample_s(const nnom_upsample_config_t *config) +{ + nnom_layer_t *layer = UpSample(kernel(config->kernel[0], config->kernel[1])); + if(layer) + layer->config = (void*) config; + return layer; +} + +// up sampling layer +nnom_layer_t *UpSample(nnom_3d_shape_t kernel) +{ + nnom_upsample_layer_t *layer; + nnom_layer_io_t *in, *out; + + // apply a block memory for all the sub handles. + size_t mem_size = sizeof(nnom_upsample_layer_t) + sizeof(nnom_layer_io_t) * 2; + layer = nnom_mem(mem_size); + if (layer == NULL) + return NULL; + + // distribut the memory to sub handles. + in = (void *)((uint8_t*)layer + sizeof(nnom_upsample_layer_t)); + out = (void *)((uint8_t*)in + sizeof(nnom_layer_io_t)); + + // set type in layer parent + layer->super.type = NNOM_UPSAMPLE; + // set buf state + in->type = NNOM_TENSOR_BUF_TEMP; + out->type = NNOM_TENSOR_BUF_TEMP; + // put in & out on the layer. + layer->super.in = io_init(layer, in); + layer->super.out = io_init(layer, out); + // set run and outshape methods + layer->super.run = upsample_run; + layer->super.build = upsample_build; + + // set parameters + layer->kernel = kernel; + + return (nnom_layer_t*)layer; +} + +nnom_status_t upsample_build(nnom_layer_t *layer) +{ + nnom_upsample_layer_t* cl = (nnom_upsample_layer_t*)layer; + + // get the last layer's output as input shape + layer->in->tensor = layer->in->hook.io->tensor; + // output tensor + // 1. allocate a new tensor for output + // 2. set the same dim, qfmt to the new tensor. + layer->out->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, layer->in->tensor->num_dim, tensor_get_num_channel(layer->in->tensor)); + tensor_cpy_attr(layer->out->tensor, layer->in->tensor); + + // see if the activation will change the q format + if(layer->actail) + layer->out->tensor->q_dec[0] = act_get_dec_bit(layer->actail->type, layer->out->tensor->q_dec[0]); + + // enlarge w and h, c stay the same. + layer->out->tensor->dim[0] = layer->in->tensor->dim[0] * cl->kernel.h; + layer->out->tensor->dim[1] = layer->in->tensor->dim[1] * cl->kernel.w; + + return NN_SUCCESS; +} + +// up sampling, or so called unpooling +nnom_status_t upsample_run(nnom_layer_t *layer) +{ + nnom_upsample_layer_t *cl = (nnom_upsample_layer_t *)(layer); + +#ifdef NNOM_USING_CHW + local_up_sampling_q7_CHW( +#else + local_up_sampling_q7_HWC( +#endif + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->kernel.w, cl->kernel.h, + layer->out->tensor->dim[1], layer->out->tensor->dim[0], + NULL, + layer->out->tensor->p_data); + return NN_SUCCESS; +} diff --git a/components/ai/nnom/src/layers/nnom_zero_padding.c b/components/ai/nnom/src/layers/nnom_zero_padding.c new file mode 100644 index 000000000..2352e614e --- /dev/null +++ b/components/ai/nnom/src/layers/nnom_zero_padding.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2018-2020 + * Jianjia Ma + * majianjia@live.com + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-07-23 Jianjia Ma The first version + */ + +#include +#include +#include + +#include "nnom.h" +#include "nnom_local.h" +#include "nnom_layers.h" +#include "layers/nnom_zero_padding.h" + +nnom_layer_t * zeropadding_s(const nnom_zero_padding_config_t* config) +{ + nnom_layer_t *layer = ZeroPadding(config->pad); + if(layer) + layer->config = (void*) config; + return (nnom_layer_t*)layer; +} + +// Zero padding layer +nnom_layer_t *ZeroPadding(nnom_border_t pad) +{ + nnom_zero_padding_layer_t *layer; + nnom_layer_io_t *in, *out; + + // apply a block memory for all the sub handles. + size_t mem_size = sizeof(nnom_zero_padding_layer_t) + sizeof(nnom_layer_io_t) * 2; + layer = nnom_mem(mem_size); + if (layer == NULL) + return NULL; + + // distribut the memory to sub handles. + in = (void *)((uint8_t*)layer + sizeof(nnom_zero_padding_layer_t)); + out = (void *)((uint8_t*)in + sizeof(nnom_layer_io_t)); + + // set type in layer parent + layer->super.type = NNOM_ZERO_PADDING; + // set buf state + in->type = NNOM_TENSOR_BUF_TEMP; + out->type = NNOM_TENSOR_BUF_TEMP; + // put in & out on the layer. + layer->super.in = io_init(layer, in); + layer->super.out = io_init(layer, out); + // set run and outshape methods + layer->super.run = zero_padding_run; + layer->super.build = zero_padding_build; + + // set parameters + layer->pad = pad; + + return (nnom_layer_t*)layer; +} + +nnom_status_t zero_padding_build(nnom_layer_t* layer) +{ + nnom_zero_padding_layer_t *cl = (nnom_zero_padding_layer_t *)layer; + + // get the tensor from last layer's output + layer->in->tensor = layer->in->hook.io->tensor; + + // create new tensor for output + layer->out->tensor = new_tensor(NNOM_QTYPE_PER_TENSOR, layer->in->tensor->num_dim, tensor_get_num_channel(layer->in->tensor)); + // copy then change later. + tensor_cpy_attr(layer->out->tensor, layer->in->tensor); + + // see if the activation will change the q format + if(layer->actail) + layer->out->tensor->q_dec[0] = act_get_dec_bit(layer->actail->type, layer->out->tensor->q_dec[0]); + + // output shape + layer->out->tensor->dim[1] = layer->in->tensor->dim[1] + cl->pad.left + cl->pad.right; + layer->out->tensor->dim[0] = layer->in->tensor->dim[0] + cl->pad.top + cl->pad.bottom; + layer->out->tensor->dim[2] = layer->in->tensor->dim[2]; + return NN_SUCCESS; +} + +nnom_status_t zero_padding_run(nnom_layer_t * layer) +{ + nnom_zero_padding_layer_t *cl = (nnom_zero_padding_layer_t*)layer; + +#ifdef NNOM_USING_CHW + local_zero_padding_CHW_q7( +#else + local_zero_padding_HWC_q7( +#endif + layer->in->tensor->p_data, + layer->in->tensor->dim[1], layer->in->tensor->dim[0], layer->in->tensor->dim[2], + cl->pad.top, + cl->pad.bottom, + cl->pad.left, + cl->pad.right, + layer->out->tensor->p_data, + layer->out->tensor->dim[1], layer->out->tensor->dim[0]); + + return NN_SUCCESS; +} + diff --git a/components/ai/tflite_micro/ARM_CortexM4_lib/tensorflow/lite/micro/examples/person_detection_experimental/main_functions.h b/components/ai/tflite_micro/ARM_CortexM4_lib/tensorflow/lite/micro/examples/person_detection_experimental/main_functions.h index 8361e318b..81f8e8f2b 100644 --- a/components/ai/tflite_micro/ARM_CortexM4_lib/tensorflow/lite/micro/examples/person_detection_experimental/main_functions.h +++ b/components/ai/tflite_micro/ARM_CortexM4_lib/tensorflow/lite/micro/examples/person_detection_experimental/main_functions.h @@ -20,11 +20,11 @@ limitations under the License. // Initializes all data needed for the example. The name is important, and needs // to be setup() for Arduino compatibility. -extern "C" void person_detect_init(); +//extern "C" void person_detect_init(); // Runs one iteration of data gathering and inference. This should be called // repeatedly from the application code. The name needs to be loop() for Arduino // compatibility. -extern "C" int person_detect(uint8_t * hardware_input); +//extern "C" int person_detect(uint8_t * hardware_input); #endif // TENSORFLOW_LITE_MICRO_EXAMPLES_PERSON_DETECTION_EXPERIMENTAL_MAIN_FUNCTIONS_H_ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/Changelog.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/Changelog.txt deleted file mode 100644 index 9ceae074a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/Changelog.txt +++ /dev/null @@ -1,330 +0,0 @@ -2018-09-13 (REL_1_6_0) Christian Walter - Notes: Changed licensing for mbfuncdisc.c. Updating licensing info - and contact details in core stack. - -2010-05-06 (REL_1_5_0) Christian Walter - Notes: Added support for Atmel AT91SAM3S (Cortex M3) for IAR. - - Detailed notes: - - FEATURES (ATSAM3S) : Added new port. - -2007-08-28 (REL_1_4_0) Christian Walter : - Notes: Added support for HCS08. Fixed some small bugs in the documentation - for the porting layer. - - Detailed notes: - - FEATURES (HCS08) : Added new port. - - BUGS (ALL) : Fixed some small bugs in the porting guide. - -2007-07-17 (REL_1_3_0) Christian Walter : - Notes: Added ARM7/AT91SAM7X port. Added Linux/TCP port from Steven Guo. - - Detailed notes: - - FEATURES (ARM7): Added ARM7/AT91SAM7x port. - - FEATURES (LINUX): Added Linux/TCP port from Steven Guo. - - BUGS (ALL): Fixed bug in where the high - byte of the register count was ignored. This does not have a - practical impact because the actual number of registers is always - lower. - -2007-07-17 (REL_1_3_0) Christian Walter : - Notes: Added Linux/TCP port. Fixed bug in MSP430 port. - Detailted notes: - - FEATURE (LINUX): Added Linux/TCP port. - - BUGS (MSP430): Fixed bug with calculating the timer value. - -2007-04-25 (REL_1_2_0) Christian Walter : - Notes: Added LPC214X ARM port with Keil compiler. Added Z8Encore port for - Z8F6422 microcontroller. - - Detailed notes: - - FEATURE (ARM): Added LPC214X ARM port for Keil ARM 2.41. - - FEATURE (Z8ENCORE): Added Z8F6422 for Z8Encore using the ZDS II - Z8 - Encore! development tools. - -2007-02-18 (REL_1_1_2) Christian Walter : - Notes: Fixed typo with the defined defining the supported Modbus - functions. Fixed bug when illegal slave address was passed to eMBInit - where the error was not detected. Fixed typo in the holding registers - where the frame for write multiple registers was parsed with the wrong - constants. The fix is not critical because the values matched. Fixed bug - in discrete input registers implementation where the frame was not parsed - correctly. Added new support for a CodeWarrior Coldfire port. - - Detailed notes: - - BUG (ALL): Modbus functions are compiled into the stack conditionally - by changing the MB_FUNC_XXX defines to either true(1) or false(0). - The defines for MB_FUNC_READ_HOLDING and MB_FUNC_WRITE_HOLDING - were wrong. - - BUG (ALL): eMBInit did not correctly check for addresses. Therefore - is was possible to start the Modbus stack with an address of 0 - or one > 247. - - BUG (ALL): eMBFuncWriteHoldingRegister should use - MB_PDU_FUNC_WRITE_MUL_ADDR_OFF and not MB_PDU_FUNC_READ_ADDR_OFF. - - BUG (ALL): eMBFuncReadDiscreteInputs calculated the number of discrete - registers to read wrong. - - FEATURE (ALL): Fixed some warnings in the code. - -2006-11-19 (REL_1_1_1) Christian Walter : - Notes: Fixed bug in Read/Write Multiple Registers function where - the registers addresses where calculated wrong. - Fixed bug in RTU and ASCII with the resource allocation in case of - an error. - Changed license to BSD style licsense. - - Detailed notes: - - OTHER (ALL): License is now BSD for protocol stack. - - BUG (ALL): The registers address received in a Modbus frame - must be converted to application addresses. The code for this - conversion was missing and therefore has lead to error when - this function was used (Registers of by one, Start at > 1). - - BUG (ALL): If the serial initialization within the porting fails - a timer is still allocated in eMBRTUInit and eMBASCIIInit. This - can lead to a memory leak depending upon the implementation of the - porting layer. - - FEATURE (MCF5235): Added sample shell scripts for testing. - - FEATURE (MSP430): Added sample shell script for testing and - changed default values to match the other ports. - -2006-10-30 (REL_1_1_0) Christian Walter : - Notes: Added support for Read/Write Multiple Registers function - (0x17). Added some tips to reduce memory requirements. - Added MSP430 Port for GCC and Rowley Crossworks. - - Detailed notes: - - FEATURE (MSP430): Added new MSP430 port. - - FEATURE (ALL): Added support for Read/Write Multiple Registers - function (0x17). The implementation simply makes two callbacks - to the eMBRegHoldingCB function where first the values are - written and then the other register values are read. - - FEATURE (ALL): Added some tips on reducing memory requirements - with the protocol stack. - -2006-10-30 (REL_1_0_5) Christian Walter : - Notes: eMBDisable and eMBClose can now be called multiple times - which makes shutdown of the protocol stack easier. - Fixed bug in RTU state machine where we switched from the - error state immediately to the idle state. Correct behaviour - would be to wait till the end of frame. - Added new STR71X GCC port which uses only freely available tools - like GNU ARM, OpenOCD (Wiggler) and GDB. - - Detailed notes: - - FEATURE (STR71X): Added GCC standalone port which does not - depend on the Rowley Crosswork tools. - - FEATURE (ALL): eMBDisable can now be called multiple times - and returns MB_ENOERR in case is was already disabled. - eMBClose also supports beeing called multiple times in - which pvMBFrameCloseCur( ) is called when the protocol stack - is in state STATE_DISABLED. - - BUG (RTU): Fixed bug in xMBRTUReceiveFSM where the error - state is immediately left because of a missing break. Instead - we should wait till the damaged frame is finished. - -2006-10-11 (REL_1_0_4) Christian Walter : - Notes: Fixed bug when more than 255 coils are requested. Fixed bug in - Linux/Cygwin port when not all bytes could be written by the first - call to write. Added support for removing previously registered - function handlers. - - Detailed notes: - - BUG (ALL): mbfunccoils contained a bug which limited the amount - of coils to read to 255. - - BUG (LINUX): prvbMBPortSerialWrite contained a bug in the loop - which writes the RTU/ASCII frame to the serial file descriptor. - If not all bytes where written in the first call or write was - interrupted the sent frame is corrupted. - - FEATURE (ALL): eMBRegisterCB now supports NULL as handler - argument in which case a previously registered function - handler is deregistered from the protocol stack. - -2006-09-27 (REL_1_0_3) Christian Walter : - Notes: Added new functions to support registering of custom callback - handlers. This makes it possible to implement new Modbus function - codes without touching the protocol stack. - New port for ATMega128 added. Thanks to Richard C Sandoz Jr. for - the patches. - - Detailed notes: - - FEATURE (ALL): Added support for registering new functions handlers - with eMBRegisterCB. - - FEATURE (AVR): Added patches from Richard C Sandoz Jr. for ATMega128 - -2006-09-06 (REL_1_0_2) Christian Walter : - Notes: Fixed bug in FreeRTOS porting layer for STR71X/lwIP target where - memory is not freed in the sys_arch_thread_remove function. - Synched MCF5235TCP port with the FreeRTOS/lwIP port for the STR71X. - - Detailed notes: - - BUG (STR71XTCP): Sys_arch_thread_remove did not free the memory from - the TCB. - - BUG (STR71XTCP): Unnecessary call to vTaskSuspendAll removed. - - BUG (STR71XTCP): Bug with counting variable. The first to lwIP tasks - got the same name (lwIP0). - - FEATURE (MCF5235TCP): Enhanced functions from the STR71X/lwIP port - merged into the Coldfire port. - -2006-09-04 (REL_1_0_1) Christian Walter : - Notes: Fixed bug in serial driver for STR71x target when the ring buffer - overflows. - - Detailed notes: - - BUG (STR71XTCP): Under high load the ring buffer in the serial driver - functions might overflow. There was an error with counting the number - of received characters which corrupted received frames. - Now receiver correctly recovers in case of dropped bytes. - -2006-09-04 (REL_1_0) Christian Walter : - Notes: Added support for ATmega8, ATmega16, ATmega32, ATmega169 and - RS485 drivers in the AVR support. Special thanks to Tran Minh Hoang - for his contribution. - Added a new lwIP port for the STR71X target which uses one serial - interface for a PPP connection. This can be used for remote Modbus/TCP - devices in combination with a Modem (E.g. GPRS or Analog). - - Detailed notes: - - FEATURES (AVR): Integrated patches from Tran Minh Hoang to support the - ATmega8, ATmega16, ATmega32, ATmega169 controllers. - - FEATURES (AVR): Added support for RS485 drivers in the AVR code. The - example supports the DS76176. - - FEATURES (STR71XTCP): implemented function in STR71X/lwIP porting layer - to remove running tasks. - - FEATURES (STR71XTCP): added new thread creation function in STR71X/lwIP - porting layer which allows specifing the stack size. - - BUGS (STR71XTCP): pppOpen defined in ppp.c does not check the return - value of sys_thread_new. If task creation fails the system crashes. - - BUGS (STR71XTCP): pppMain must not return - Instead it should remove - its task from the scheduler. - -2006-08-30 (REL_9) Christian Walter : - Notes: Added lwIP port for the MCF5235 target. The lwIP part is - generic and therefore FreeModbus now works on any target with - lwIP support. - - Detailed notes: - - FEATURES: Incoperated MCF5235 FreeRTOS/lwIP port done by the - author in this project. - - FEATURES: Added lwIP port for FreeModbus - - FEATURES: Added demo application for FreeModbus and lwIP. - -2006-08-22 (REL_0_82) Christian Walter - Notes: Fixed bug with Modbus ASCII support - - Detailed notes: - - BUG: During the last upgrade an error was introduced in the - initialization code of Modbus ASCII and therefore ASCII - support was broken. The bug is fixed now and was tested with - the Win32 port. - -2006-08-22 (REL_0_81) Christian Walter - Notes: Added porting guide - - Detailed notes: - - OTHER: Added a new porting guide to the documentation. - - OTHER: Added a empty example for new ports to the project as a - starting point. - -2006-08-01 (REL_0_8) Christian Walter - Notes: Added Linux RTU/ASCII port. - - Detailed notes: - - FEATURES: Added a new Linux RTU/ASCII port. The port should work - on any Linux distribution and it should be possible to run it - on uCLinux. - -2006-06-26 (REL_0_7) Christian Walter - Notes: Changed the WIN32 serial port to better fit into the design. - - Detailed notes: - - OTHER: Design of the WIN32 serial port changed. The polling function - for the serial device are now called from the event loop. - - OTHER: Debugging uses the same interface as the WIN32/TCP port. - -2006-06-25 Christian Walter - - Notes: Initial work on a Modbus/TCP port is available. The port includes - an example for a Win32 port which uses the Winsock API. - - Detailed notes: - - FEATURES: added required functions to core protocol stack to support - a Modbus/TCP implementation. - - FEATURES: added a Win32 port for the Modbus/TCP core. The port is - currently limited to one concurrent client. - - OTHER: The implementation of eMBClose to shutdown the protocol stack - was changed to unify it with the new Modbus/TCP code. - - - -2006-06-18 Christian Walter - - Detailed notes: - - OTHER: while working on the Win32 port some line feeds got - wrong. Also some source files used tabs instead of spaces. - - OTHER: prototypes for xMBUtilSetBits and xMBUtilGetBits fixed. - usNBits should be ucNBits by convention. - -2006-06-17 Christian Walter - - Notes: Fixed various bugs with the Win32 port - - Detailed notes: - - FEATURES: implement shutdown functionality for protocol stack. - - FEATURES: protocol stack can be enabled and disabled during runtime. - - FEATURES: interface functions now do more error checking. For - example if eMBPool is called in an uninitialized state. - - FEATURES: extended Win32 demo application to use the new features. - - BUG: fixed bug in Win32 demo for ASCII mode. - -2006-06-16 Christian Walter - Notes: The new version includes a new port for the - Win32 platform - - Detailed notes: - - FEATURES: added Win32 platform - -2006-05-14 Christian Walter - Notes: The new version includes a new port for the - Freescale MCF5235 processor. - - Detailed notes: - - FEATURES: added new MCF5235 port. - - OTHER: fixed some missing code headers. - -2006-05-01 Christian Walter - Notes: This version removes the t1.5 timers from the Modbus RTU - implementation because no one actually uses it and the CPU - load is very high. T - In addition some documentation cleanups has been done and the - ARM demo has been updated. - - Detailed notes: - - - FEATURES: the t1.5 timeout has been removed. Therefore only - one timer is required. - - BUG: the ARM demo project missed some files in the project - workspace and did not compile cleanly - -2006-02-28 Christian Walter - Notes: This version includes support for two new command - (write multiple coils, read discrete input) - - Detailed notes: - - BUG: some function used the wrong data types - - FEATURES: added support for write multiple coils function. - - FEATURES: added support for read discrete input. - - OTHER: some code cleanups with lint tool. - -2006-02-28 Christian Walter - - Notes: The new version 0.31 adds support for reading and writing the - coil registers and add some bug fixes. - - Detailed notes: - - BUG: fixed bug with to small modbus requests being ignored. - - FEATURES: added support for write single coil function. - - FEATURES: added support for working with byte packed bit fields - to support coils and discrete inputs better. - - API: API for set slave id functions changed. - -2006-02-26 Christian Walter - - Notes: First public release which includes an ARM and AVR port. diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/bsd.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/bsd.txt deleted file mode 100644 index 362d3e37c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/bsd.txt +++ /dev/null @@ -1,25 +0,0 @@ -Copyright (c) 2006 Christian Walter -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions -are met: -1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. -3. The name of the author may not be used to endorse or promote products - derived from this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/croutine.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/croutine.c deleted file mode 100644 index 4f2ba873c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/croutine.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/* Lists for ready and blocked co-routines. --------------------*/ -static xList pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ -static xList xDelayedCoRoutineList1; /*< Delayed co-routines. */ -static xList xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ -static xList * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */ -static xList * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ -static xList xPendingReadyList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ - -/* Other file private variables. --------------------------------*/ -corCRCB * pxCurrentCoRoutine = NULL; -static unsigned portBASE_TYPE uxTopCoRoutineReadyPriority = 0; -static portTickType xCoRoutineTickCount = 0; - -/* The initial state of the co-routine when it is created. */ -#define corINITIAL_STATE ( 0 ) - -/* - * Place the co-routine represented by pxCRCB into the appropriate ready queue - * for the priority. It is inserted at the end of the list. - * - * This macro accesses the co-routine ready lists and therefore must not be - * used from within an ISR. - */ -#define prvAddCoRoutineToReadyQueue( pxCRCB ) \ -{ \ - if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ - { \ - uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ - } \ - vListInsertEnd( ( xList * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ -} - -/* - * Utility to ready all the lists used by the scheduler. This is called - * automatically upon the creation of the first co-routine. - */ -static void prvInitialiseCoRoutineLists( void ); - -/* - * Co-routines that are readied by an interrupt cannot be placed directly into - * the ready lists (there is no mutual exclusion). Instead they are placed in - * in the pending ready list in order that they can later be moved to the ready - * list by the co-routine scheduler. - */ -static inline void prvCheckPendingReadyList( void ); - -/* - * Macro that looks at the list of co-routines that are currently delayed to - * see if any require waking. - * - * Co-routines are stored in the queue in the order of their wake time - - * meaning once one co-routine has been found whose timer has not expired - * we need not look any further down the list. - */ -static inline void prvCheckDelayedList( void ); - -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ) -{ -signed portBASE_TYPE xReturn; -corCRCB *pxCoRoutine; - - /* Allocate the memory that will store the co-routine control block. */ - pxCoRoutine = ( corCRCB * ) pvPortMalloc( sizeof( corCRCB ) ); - if( pxCoRoutine ) - { - /* If pxCurrentCoRoutine is NULL then this is the first co-routine to - be created and the co-routine data structures need initialising. */ - if( pxCurrentCoRoutine == NULL ) - { - pxCurrentCoRoutine = pxCoRoutine; - prvInitialiseCoRoutineLists(); - } - - /* Check the priority is within limits. */ - if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) - { - uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; - } - - /* Fill out the co-routine control block from the function parameters. */ - pxCoRoutine->uxState = corINITIAL_STATE; - pxCoRoutine->uxPriority = uxPriority; - pxCoRoutine->uxIndex = uxIndex; - pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; - - /* Initialise all the other co-routine control block parameters. */ - vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); - vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); - - /* Set the co-routine control block as a link back from the xListItem. - This is so we can get back to the containing CRCB from a generic item - in a list. */ - listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); - listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); - - /* Event lists are always in priority order. */ - listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); - - /* Now the co-routine has been initialised it can be added to the ready - list at the correct priority. */ - prvAddCoRoutineToReadyQueue( pxCoRoutine ); - - xReturn = pdPASS; - } - else - { - xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList ) -{ -portTickType xTimeToWake; - - /* Calculate the time to wake - this may overflow but this is - not a problem. */ - xTimeToWake = xCoRoutineTickCount + xTicksToDelay; - - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xCoRoutineTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - } - - if( pxEventList ) - { - /* Also add the co-routine to an event list. If this is done then the - function must be called with interrupts disabled. */ - vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); - } -} -/*-----------------------------------------------------------*/ - -static inline void prvCheckPendingReadyList( void ) -{ - /* Are there any co-routines waiting to get moved to the ready list? These - are co-routines that have been readied by an ISR. The ISR cannot access - the ready lists itself. */ - while( !listLIST_IS_EMPTY( &xPendingReadyList ) ) - { - corCRCB *pxUnblockedCRCB; - - /* The pending ready list can be accessed by an ISR. */ - portDISABLE_INTERRUPTS(); - { - pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyList) ); - vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); - } - portENABLE_INTERRUPTS(); - - vListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); - prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); - } -} -/*-----------------------------------------------------------*/ - -static inline void prvCheckDelayedList( void ) -{ -static portTickType xLastTickCount, xPassedTicks; -corCRCB *pxCRCB; - - xPassedTicks = xTaskGetTickCount() - xLastTickCount; - while( xPassedTicks ) - { - xCoRoutineTickCount++; - xPassedTicks--; - - /* If the tick count has overflowed we need to swap the ready lists. */ - if( xCoRoutineTickCount == 0 ) - { - xList * pxTemp; - - /* Tick count has overflowed so we need to swap the delay lists. If there are - any items in pxDelayedCoRoutineList here then there is an error! */ - pxTemp = pxDelayedCoRoutineList; - pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; - pxOverflowDelayedCoRoutineList = pxTemp; - } - - /* See if this tick has made a timeout expire. */ - while( ( pxCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ) ) != NULL ) - { - if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) - { - /* Timeout not yet expired. */ - break; - } - - portDISABLE_INTERRUPTS(); - { - /* The event could have occurred just before this critical - section. If this is the case then the generic list item will - have been moved to the pending ready list and the following - line is still valid. Also the pvContainer parameter will have - been set to NULL so the following lines are also valid. */ - vListRemove( &( pxCRCB->xGenericListItem ) ); - - /* Is the co-routine waiting on an event also? */ - if( pxCRCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxCRCB->xEventListItem ) ); - } - } - portENABLE_INTERRUPTS(); - - prvAddCoRoutineToReadyQueue( pxCRCB ); - } - } - - xLastTickCount = xCoRoutineTickCount; -} -/*-----------------------------------------------------------*/ - -void vCoRoutineSchedule( void ) -{ - /* See if any co-routines readied by events need moving to the ready lists. */ - prvCheckPendingReadyList(); - - /* See if any delayed co-routines have timed out. */ - prvCheckDelayedList(); - - /* Find the highest priority queue that contains ready co-routines. */ - while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) - { - if( uxTopCoRoutineReadyPriority == 0 ) - { - /* No more co-routines to check. */ - return; - } - --uxTopCoRoutineReadyPriority; - } - - /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines - of the same priority get an equal share of the processor time. */ - listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); - - /* Call the co-routine. */ - ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); - - return; -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseCoRoutineLists( void ) -{ -unsigned portBASE_TYPE uxPriority; - - for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) - { - vListInitialise( ( xList * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); - } - - vListInitialise( ( xList * ) &xDelayedCoRoutineList1 ); - vListInitialise( ( xList * ) &xDelayedCoRoutineList2 ); - vListInitialise( ( xList * ) &xPendingReadyList ); - - /* Start with pxDelayedCoRoutineList using list1 and the - pxOverflowDelayedCoRoutineList using list2. */ - pxDelayedCoRoutineList = &xDelayedCoRoutineList1; - pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList ) -{ -corCRCB *pxUnblockedCRCB; -signed portBASE_TYPE xReturn; - - /* This function is called from within an interrupt. It can only access - event lists and the pending ready list. */ - pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); - vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedCRCB->xEventListItem ) ); - - if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) - { - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/FreeRTOS.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/FreeRTOS.h deleted file mode 100644 index 676bda331..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/FreeRTOS.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -#ifndef INC_FREERTOS_H -#define INC_FREERTOS_H - - -/* - * Include the generic headers required for the FreeRTOS port being used. - */ -#include - -/* Basic FreeRTOS definitions. */ -#include "projdefs.h" - -/* Application specific configuration options. */ -#include "FreeRTOSConfig.h" - -/* Definitions specific to the port being used. */ -#include "portable.h" - - - - - - - -/* - * Check all the required application specific macros have been defined. - * These macros are application specific and (as downloaded) are defined - * within FreeRTOSConfig.h. - */ - -#ifndef configUSE_PREEMPTION - #error Missing definition: configUSE_PREEMPTION should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_IDLE_HOOK - #error Missing definition: configUSE_IDLE_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_TICK_HOOK - #error Missing definition: configUSE_TICK_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_CO_ROUTINES - #error Missing definition: configUSE_CO_ROUTINES should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskPrioritySet - #error Missing definition: INCLUDE_vTaskPrioritySet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_uxTaskPriorityGet - #error Missing definition: INCLUDE_uxTaskPriorityGet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelete - #error Missing definition: INCLUDE_vTaskDelete should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskCleanUpResources - #error Missing definition: INCLUDE_vTaskCleanUpResources should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskSuspend - #error Missing definition: INCLUDE_vTaskSuspend should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelayUntil - #error Missing definition: INCLUDE_vTaskDelayUntil should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelay - #error Missing definition: INCLUDE_vTaskDelay should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_16_BIT_TICKS - #error Missing definition: configUSE_16_BIT_TICKS should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/croutine.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/croutine.h deleted file mode 100644 index d3b52163d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/croutine.h +++ /dev/null @@ -1,716 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ -#ifndef CO_ROUTINE_H -#define CO_ROUTINE_H - -#include "list.h" - -/* Used to hide the implementation of the co-routine control block. The -control block structure however has to be included in the header due to -the macro implementation of the co-routine functionality. */ -typedef void * xCoRoutineHandle; - -/* Defines the prototype to which co-routine functions must conform. */ -typedef void (*crCOROUTINE_CODE)( xCoRoutineHandle, unsigned portBASE_TYPE ); - -typedef struct corCoRoutineControlBlock -{ - crCOROUTINE_CODE pxCoRoutineFunction; - xListItem xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ - xListItem xEventListItem; /*< List item used to place the CRCB in event lists. */ - unsigned portBASE_TYPE uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ - unsigned portBASE_TYPE uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ - unsigned portSHORT uxState; /*< Used internally by the co-routine implementation. */ -} corCRCB; /* Co-routine control block. Note must be identical in size down to uxPriority with tskTCB. */ - -/** - * croutine. h - *
- portBASE_TYPE xCoRoutineCreate(
-                                 crCOROUTINE_CODE pxCoRoutineCode,
-                                 unsigned portBASE_TYPE uxPriority,
-                                 unsigned portBASE_TYPE uxIndex
-                               );
- * - * Create a new co-routine and add it to the list of co-routines that are - * ready to run. - * - * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine - * functions require special syntax - see the co-routine section of the WEB - * documentation for more information. - * - * @param uxPriority The priority with respect to other co-routines at which - * the co-routine will run. - * - * @param uxIndex Used to distinguish between different co-routines that - * execute the same function. See the example below and the co-routine section - * of the WEB documentation for further information. - * - * @return pdPASS if the co-routine was successfully created and added to a ready - * list, otherwise an error code defined with ProjDefs.h. - * - * Example usage: -
- // Co-routine to be created.
- void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- // This may not be necessary for const variables.
- static const char cLedToFlash[ 2 ] = { 5, 6 };
- static const portTickType xTimeToDelay[ 2 ] = { 200, 400 };
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // This co-routine just delays for a fixed period, then toggles
-         // an LED.  Two co-routines are created using this function, so
-         // the uxIndex parameter is used to tell the co-routine which
-         // LED to flash and how long to delay.  This assumes xQueue has
-         // already been created.
-         vParTestToggleLED( cLedToFlash[ uxIndex ] );
-         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
-
- // Function that creates two co-routines.
- void vOtherFunction( void )
- {
- unsigned char ucParameterToPass;
- xTaskHandle xHandle;
-		
-     // Create two co-routines at priority 0.  The first is given index 0
-     // so (from the code above) toggles LED 5 every 200 ticks.  The second
-     // is given index 1 so toggles LED 6 every 400 ticks.
-     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
-     {
-         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
-     }
- }
-   
- * \defgroup xCoRoutineCreate xCoRoutineCreate - * \ingroup Tasks - */ -signed portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ); - - -/** - * croutine. h - *
- void vCoRoutineSchedule( void );
- * - * Run a co-routine. - * - * vCoRoutineSchedule() executes the highest priority co-routine that is able - * to run. The co-routine will execute until it either blocks, yields or is - * preempted by a task. Co-routines execute cooperatively so one - * co-routine cannot be preempted by another, but can be preempted by a task. - * - * If an application comprises of both tasks and co-routines then - * vCoRoutineSchedule should be called from the idle task (in an idle task - * hook). - * - * Example usage: -
- // This idle task hook will schedule a co-routine each time it is called.
- // The rest of the idle task will execute between co-routine calls.
- void vApplicationIdleHook( void )
- {
-	vCoRoutineSchedule();
- }
-
- // Alternatively, if you do not require any other part of the idle task to
- // execute, the idle task hook can call vCoRoutineScheduler() within an
- // infinite loop.
- void vApplicationIdleHook( void )
- {
-    for( ;; )
-    {
-        vCoRoutineSchedule();
-    }
- }
- 
- * \defgroup vCoRoutineSchedule vCoRoutineSchedule - * \ingroup Tasks - */ -void vCoRoutineSchedule( void ); - -/** - * croutine. h - *
- crSTART( xCoRoutineHandle xHandle );
- * - * This macro MUST always be called at the start of a co-routine function. - * - * Example usage: -
- // Co-routine to be created.
- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portLONG ulAVariable;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-          // Co-routine functionality goes here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
- * \defgroup crSTART crSTART - * \ingroup Tasks - */ -#define crSTART( pxCRCB ) switch( ( ( corCRCB * )pxCRCB )->uxState ) { case 0: - -/** - * croutine. h - *
- crEND();
- * - * This macro MUST always be called at the end of a co-routine function. - * - * Example usage: -
- // Co-routine to be created.
- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portLONG ulAVariable;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-          // Co-routine functionality goes here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
- * \defgroup crSTART crSTART - * \ingroup Tasks - */ -#define crEND() } - -/* - * These macros are intended for internal use by the co-routine implementation - * only. The macros should not be used directly by application writers. - */ -#define crSET_STATE0( xHandle ) ( ( corCRCB * )xHandle)->uxState = (__LINE__ * 2); return; case (__LINE__ * 2): -#define crSET_STATE1( xHandle ) ( ( corCRCB * )xHandle)->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1): - -/** - * croutine. h - *
- crDELAY( xCoRoutineHandle xHandle, portTickType xTicksToDelay );
- * - * Delay a co-routine for a fixed period of time. - * - * crDELAY can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * @param xHandle The handle of the co-routine to delay. This is the xHandle - * parameter of the co-routine function. - * - * @param xTickToDelay The number of ticks that the co-routine should delay - * for. The actual amount of time this equates to is defined by - * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_RATE_MS - * can be used to convert ticks to milliseconds. - * - * Example usage: -
- // Co-routine to be created.
- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- // This may not be necessary for const variables.
- // We are to delay for 200ms.
- static const xTickType xDelayTime = 200 / portTICK_RATE_MS;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-        // Delay for 200ms.
-        crDELAY( xHandle, xDelayTime );
-
-        // Do something here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
- * \defgroup crDELAY crDELAY - * \ingroup Tasks - */ -#define crDELAY( xHandle, xTicksToDelay ) \ - if( xTicksToDelay > 0 ) \ - { \ - vCoRoutineAddToDelayedList( xTicksToDelay, NULL ); \ - } \ - crSET_STATE0( xHandle ); - -/** - *
- crQUEUE_SEND(
-                  xCoRoutineHandle xHandle,
-                  xQueueHandle pxQueue,
-                  void *pvItemToQueue,
-                  portTickType xTicksToWait,
-                  portBASE_TYPE *pxResult
-             )
- * - * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine - * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. - * - * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas - * xQueueSend() and xQueueReceive() can only be used from tasks. - * - * crQUEUE_SEND can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xHandle The handle of the calling co-routine. This is the xHandle - * parameter of the co-routine function. - * - * @param pxQueue The handle of the queue on which the data will be posted. - * The handle is obtained as the return value when the queue is created using - * the xQueueCreate() API function. - * - * @param pvItemToQueue A pointer to the data being posted onto the queue. - * The number of bytes of each queued item is specified when the queue is - * created. This number of bytes is copied from pvItemToQueue into the queue - * itself. - * - * @param xTickToDelay The number of ticks that the co-routine should block - * to wait for space to become available on the queue, should space not be - * available immediately. The actual amount of time this equates to is defined - * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant - * portTICK_RATE_MS can be used to convert ticks to milliseconds (see example - * below). - * - * @param pxResult The variable pointed to by pxResult will be set to pdPASS if - * data was successfully posted onto the queue, otherwise it will be set to an - * error defined within ProjDefs.h. - * - * Example usage: -
- // Co-routine function that blocks for a fixed period then posts a number onto
- // a queue.
- static void prvCoRoutineFlashTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portBASE_TYPE xNumberToPost = 0;
- static portBASE_TYPE xResult;
-
-    // Co-routines must begin with a call to crSTART().
-    crSTART( xHandle );
-
-    for( ;; )
-    {
-        // This assumes the queue has already been created.
-        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
-
-        if( xResult != pdPASS )
-        {
-            // The message was not posted!
-        }
-
-        // Increment the number to be posted onto the queue.
-        xNumberToPost++;
-
-        // Delay for 100 ticks.
-        crDELAY( xHandle, 100 );
-    }
-
-    // Co-routines must end with a call to crEND().
-    crEND();
- }
- * \defgroup crQUEUE_SEND crQUEUE_SEND - * \ingroup Tasks - */ -#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ -{ \ - *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, xTicksToWait ); \ - if( *pxResult == errQUEUE_BLOCKED ) \ - { \ - crSET_STATE0( xHandle ); \ - *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, 0 ); \ - } \ - if( *pxResult == errQUEUE_YIELD ) \ - { \ - crSET_STATE1( xHandle ); \ - *pxResult = pdPASS; \ - } \ -} - -/** - * croutine. h - *
-  crQUEUE_RECEIVE(
-                     xCoRoutineHandle xHandle,
-                     xQueueHandle pxQueue,
-                     void *pvBuffer,
-                     portTickType xTicksToWait,
-                     portBASE_TYPE *pxResult
-                 )
- * - * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine - * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. - * - * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas - * xQueueSend() and xQueueReceive() can only be used from tasks. - * - * crQUEUE_RECEIVE can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xHandle The handle of the calling co-routine. This is the xHandle - * parameter of the co-routine function. - * - * @param pxQueue The handle of the queue from which the data will be received. - * The handle is obtained as the return value when the queue is created using - * the xQueueCreate() API function. - * - * @param pvBuffer The buffer into which the received item is to be copied. - * The number of bytes of each queued item is specified when the queue is - * created. This number of bytes is copied into pvBuffer. - * - * @param xTickToDelay The number of ticks that the co-routine should block - * to wait for data to become available from the queue, should data not be - * available immediately. The actual amount of time this equates to is defined - * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant - * portTICK_RATE_MS can be used to convert ticks to milliseconds (see the - * crQUEUE_SEND example). - * - * @param pxResult The variable pointed to by pxResult will be set to pdPASS if - * data was successfully retrieved from the queue, otherwise it will be set to - * an error code as defined within ProjDefs.h. - * - * Example usage: -
- // A co-routine receives the number of an LED to flash from a queue.  It
- // blocks on the queue until the number is received.
- static void prvCoRoutineFlashWorkTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portBASE_TYPE xResult;
- static unsigned portBASE_TYPE uxLEDToFlash;
-
-    // All co-routines must start with a call to crSTART().
-    crSTART( xHandle );
-
-    for( ;; )
-    {
-        // Wait for data to become available on the queue.
-        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
-
-        if( xResult == pdPASS )
-        {
-            // We received the LED to flash - flash it!
-            vParTestToggleLED( uxLEDToFlash );
-        }
-    }
-
-    crEND();
- }
- * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE - * \ingroup Tasks - */ -#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ -{ \ - *pxResult = xQueueCRReceive( pxQueue, pvBuffer, xTicksToWait ); \ - if( *pxResult == errQUEUE_BLOCKED ) \ - { \ - crSET_STATE0( xHandle ); \ - *pxResult = xQueueCRReceive( pxQueue, pvBuffer, 0 ); \ - } \ - if( *pxResult == errQUEUE_YIELD ) \ - { \ - crSET_STATE1( xHandle ); \ - *pxResult = pdPASS; \ - } \ -} - -/** - * croutine. h - *
-  crQUEUE_SEND_FROM_ISR(
-                            xQueueHandle pxQueue,
-                            void *pvItemToQueue,
-                            portBASE_TYPE xCoRoutinePreviouslyWoken
-                       )
- * - * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the - * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() - * functions used by tasks. - * - * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to - * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and - * xQueueReceiveFromISR() can only be used to pass data between a task and and - * ISR. - * - * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue - * that is being used from within a co-routine. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto - * the same queue multiple times from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. - * - * @return pdTRUE if a co-routine was woken by posting onto the queue. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage: -
- // A co-routine that blocks on a queue waiting for characters to be received.
- static void vReceivingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- portCHAR cRxedChar;
- portBASE_TYPE xResult;
-
-     // All co-routines must start with a call to crSTART().
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // Wait for data to become available on the queue.  This assumes the
-         // queue xCommsRxQueue has already been created!
-         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
-
-         // Was a character received?
-         if( xResult == pdPASS )
-         {
-             // Process the character here.
-         }
-     }
-
-     // All co-routines must end with a call to crEND().
-     crEND();
- }
-
- // An ISR that uses a queue to send characters received on a serial port to
- // a co-routine.
- void vUART_ISR( void )
- {
- portCHAR cRxedChar;
- portBASE_TYPE xCRWokenByPost = pdFALSE;
-
-     // We loop around reading characters until there are none left in the UART.
-     while( UART_RX_REG_NOT_EMPTY() )
-     {
-         // Obtain the character from the UART.
-         cRxedChar = UART_RX_REG;
-
-         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
-         // the first time around the loop.  If the post causes a co-routine
-         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
-         // In this manner we can ensure that if more than one co-routine is
-         // blocked on the queue only one is woken by this ISR no matter how
-         // many characters are posted to the queue.
-         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
-     }
- }
- * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR - * \ingroup Tasks - */ -#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) - - -/** - * croutine. h - *
-  crQUEUE_SEND_FROM_ISR(
-                            xQueueHandle pxQueue,
-                            void *pvBuffer,
-                            portBASE_TYPE * pxCoRoutineWoken
-                       )
- * - * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the - * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() - * functions used by tasks. - * - * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to - * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and - * xQueueReceiveFromISR() can only be used to pass data between a task and and - * ISR. - * - * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data - * from a queue that is being used from within a co-routine (a co-routine - * posted to the queue). - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvBuffer A pointer to a buffer into which the received item will be - * placed. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from the queue into - * pvBuffer. - * - * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become - * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a - * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise - * *pxCoRoutineWoken will remain unchanged. - * - * @return pdTRUE an item was successfully received from the queue, otherwise - * pdFALSE. - * - * Example usage: -
- // A co-routine that posts a character to a queue then blocks for a fixed
- // period.  The character is incremented each time.
- static void vSendingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // cChar holds its value while this co-routine is blocked and must therefore
- // be declared static.
- static portCHAR cCharToTx = 'a';
- portBASE_TYPE xResult;
-
-     // All co-routines must start with a call to crSTART().
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // Send the next character to the queue.
-         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
-
-         if( xResult == pdPASS )
-         {
-             // The character was successfully posted to the queue.
-         }
-		 else
-		 {
-			// Could not post the character to the queue.
-		 }
-
-         // Enable the UART Tx interrupt to cause an interrupt in this
-		 // hypothetical UART.  The interrupt will obtain the character
-		 // from the queue and send it.
-		 ENABLE_RX_INTERRUPT();
-
-		 // Increment to the next character then block for a fixed period.
-		 // cCharToTx will maintain its value across the delay as it is
-		 // declared static.
-		 cCharToTx++;
-		 if( cCharToTx > 'x' )
-		 {
-			cCharToTx = 'a';
-		 }
-		 crDELAY( 100 );
-     }
-
-     // All co-routines must end with a call to crEND().
-     crEND();
- }
-
- // An ISR that uses a queue to receive characters to send on a UART.
- void vUART_ISR( void )
- {
- portCHAR cCharToTx;
- portBASE_TYPE xCRWokenByPost = pdFALSE;
-
-     while( UART_TX_REG_EMPTY() )
-     {
-         // Are there any characters in the queue waiting to be sent?
-		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
-		 // is woken by the post - ensuring that only a single co-routine is
-		 // woken no matter how many times we go around this loop.
-         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
-		 {
-			 SEND_CHARACTER( cCharToTx );
-		 }
-     }
- }
- * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR - * \ingroup Tasks - */ -#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( pxQueue, pvBuffer, pxCoRoutineWoken ) - -/* - * This function is intended for internal use by the co-routine macros only. - * The macro nature of the co-routine implementation requires that the - * prototype appears here. The function should not be used by application - * writers. - * - * Removes the current co-routine from its ready list and places it in the - * appropriate delayed list. - */ -void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList ); - -/* - * This function is intended for internal use by the queue implementation only. - * The function should not be used by application writers. - * - * Removes the highest priority co-routine from the event list and places it in - * the pending ready list. - */ -signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList ); - - -#endif /* CO_ROUTINE_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/list.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/list.h deleted file mode 100644 index f3702c143..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/list.h +++ /dev/null @@ -1,282 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/* - * This is the list implementation used by the scheduler. While it is tailored - * heavily for the schedulers needs, it is also available for use by - * application code. - * - * xLists can only store pointers to xListItems. Each xListItem contains a - * numeric value (xItemValue). Most of the time the lists are sorted in - * descending item value order. - * - * Lists are created already containing one list item. The value of this - * item is the maximum possible that can be stored, it is therefore always at - * the end of the list and acts as a marker. The list member pxHead always - * points to this marker - even though it is at the tail of the list. This - * is because the tail contains a wrap back pointer to the true head of - * the list. - * - * In addition to it's value, each list item contains a pointer to the next - * item in the list (pxNext), a pointer to the list it is in (pxContainer) - * and a pointer to back to the object that contains it. These later two - * pointers are included for efficiency of list manipulation. There is - * effectively a two way link between the object containing the list item and - * the list item itself. - * - * - * \page ListIntroduction List Implementation - * \ingroup FreeRTOSIntro - */ - -/* - Changes from V4.3.1 - - + Included local const within listGET_OWNER_OF_NEXT_ENTRY() to assist - compiler with optimisation. Thanks B.R. -*/ - -#ifndef LIST_H -#define LIST_H - -/* - * Definition of the only type of object that a list can contain. - */ -struct xLIST_ITEM -{ - portTickType xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ - volatile struct xLIST_ITEM * pxNext; /*< Pointer to the next xListItem in the list. */ - volatile struct xLIST_ITEM * pxPrevious;/*< Pointer to the previous xListItem in the list. */ - void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ - void * pvContainer; /*< Pointer to the list in which this list item is placed (if any). */ -}; -typedef struct xLIST_ITEM xListItem; /* For some reason lint wants this as two separate definitions. */ - -struct xMINI_LIST_ITEM -{ - portTickType xItemValue; - volatile struct xLIST_ITEM *pxNext; - volatile struct xLIST_ITEM *pxPrevious; -}; -typedef struct xMINI_LIST_ITEM xMiniListItem; - -/* - * Definition of the type of queue used by the scheduler. - */ -typedef struct xLIST -{ - volatile unsigned portBASE_TYPE uxNumberOfItems; - volatile xListItem * pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to pvListGetOwnerOfNextEntry (). */ - volatile xMiniListItem xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ -} xList; - -/* - * Access macro to set the owner of a list item. The owner of a list item - * is the object (usually a TCB) that contains the list item. - * - * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( pxListItem )->pvOwner = ( void * ) pxOwner - -/* - * Access macro to set the value of the list item. In most cases the value is - * used to sort the list in descending order. - * - * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( pxListItem )->xItemValue = xValue - -/* - * Access macro the retrieve the value of the list item. The value can - * represent anything - for example a the priority of a task, or the time at - * which a task should be unblocked. - * - * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) - -/* - * Access macro to determine if a list contains any items. The macro will - * only have the value true if the list is empty. - * - * \page listLIST_IS_EMPTY listLIST_IS_EMPTY - * \ingroup LinkedList - */ -#define listLIST_IS_EMPTY( pxList ) ( ( pxList )->uxNumberOfItems == ( unsigned portBASE_TYPE ) 0 ) - -/* - * Access macro to return the number of items in the list. - */ -#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) - -/* - * Access function to obtain the owner of the next entry in a list. - * - * The list member pxIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list - * and returns that entries pxOwner parameter. Using multiple calls to this - * function it is therefore possible to move through every item contained in - * a list. - * - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the next item owner is to be returned. - * - * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ -{ \ -xList * const pxConstList = pxList; \ - /* Increment the index to the next item and return the item, ensuring */ \ - /* we don't return the marker used at the end of the list. */ \ - ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ - if( ( pxConstList )->pxIndex == ( xListItem * ) &( ( pxConstList )->xListEnd ) ) \ - { \ - ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ - } \ - pxTCB = ( pxConstList )->pxIndex->pvOwner; \ -} - - -/* - * Access function to obtain the owner of the first entry in a list. Lists - * are normally sorted in ascending item value order. - * - * This function returns the pxOwner member of the first item in the list. - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the owner of the head item is to be - * returned. - * - * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( pxList->uxNumberOfItems != ( unsigned portBASE_TYPE ) 0 ) ? ( (&( pxList->xListEnd ))->pxNext->pvOwner ) : ( NULL ) ) - -/* - * Check to see if a list item is within a list. The list item maintains a - * "container" pointer that points to the list it is in. All this macro does - * is check to see if the container and the list match. - * - * @param pxList The list we want to know if the list item is within. - * @param pxListItem The list item we want to know if is in the list. - * @return pdTRUE is the list item is in the list, otherwise pdFALSE. - * pointer against - */ -#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( pxListItem )->pvContainer == ( void * ) pxList ) - -/* - * Must be called before a list is used! This initialises all the members - * of the list structure and inserts the xListEnd item into the list as a - * marker to the back of the list. - * - * @param pxList Pointer to the list being initialised. - * - * \page vListInitialise vListInitialise - * \ingroup LinkedList - */ -void vListInitialise( xList *pxList ); - -/* - * Must be called before a list item is used. This sets the list container to - * null so the item does not think that it is already contained in a list. - * - * @param pxItem Pointer to the list item being initialised. - * - * \page vListInitialiseItem vListInitialiseItem - * \ingroup LinkedList - */ -void vListInitialiseItem( xListItem *pxItem ); - -/* - * Insert a list item into a list. The item will be inserted into the list in - * a position determined by its item value (descending item value order). - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The item to that is to be placed in the list. - * - * \page vListInsert vListInsert - * \ingroup LinkedList - */ -void vListInsert( xList *pxList, xListItem *pxNewListItem ); - -/* - * Insert a list item into a list. The item will be inserted in a position - * such that it will be the last item within the list returned by multiple - * calls to listGET_OWNER_OF_NEXT_ENTRY. - * - * The list member pvIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list. - * Placing an item in a list using vListInsertEnd effectively places the item - * in the list position pointed to by pvIndex. This means that every other - * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before - * the pvIndex parameter again points to the item being inserted. - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The list item to be inserted into the list. - * - * \page vListInsertEnd vListInsertEnd - * \ingroup LinkedList - */ -void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ); - -/* - * Remove an item from a list. The list item has a pointer to the list that - * it is in, so only the list item need be passed into the function. - * - * @param vListRemove The item to be removed. The item will remove itself from - * the list pointed to by it's pxContainer parameter. - * - * \page vListRemove vListRemove - * \ingroup LinkedList - */ -void vListRemove( xListItem *pxItemToRemove ); - - - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/portable.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/portable.h deleted file mode 100644 index 80bac44a0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/portable.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http:www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http:www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Portable layer API. Each function must be defined for each port. - *----------------------------------------------------------*/ - -#ifndef PORTABLE_H -#define PORTABLE_H - -/* Include the macro file relevant to the port being used. */ - -#ifdef SAM7_GCC - #include "FreeRTOS/portable/GCC/ARM7_AT91SAM7S/portmacro.h" -#endif - -/* - * Setup the stack of a new task so it is ready to be placed under the - * scheduler control. The registers have to be placed on the stack in - * the order that the port expects to find them. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ); - -/* - * Map to the memory management routines required for the port. - */ -void *pvPortMalloc( size_t xSize ); -void vPortFree( void *pv ); -void vPortInitialiseBlocks( void ); - -/* - * Setup the hardware ready for the scheduler to take control. This generally - * sets up a tick interrupt and sets timers for the correct tick frequency. - */ -portBASE_TYPE xPortStartScheduler( void ); - -/* - * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so - * the hardware is left in its original condition after the scheduler stops - * executing. - */ -void vPortEndScheduler( void ); - -#endif /* PORTABLE_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/projdefs.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/projdefs.h deleted file mode 100644 index 37a662229..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/projdefs.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -#ifndef PROJDEFS_H -#define PROJDEFS_H - -/* Defines to prototype to which task functions must conform. */ -typedef void (*pdTASK_CODE)( void * ); - -#define pdTRUE ( 1 ) -#define pdFALSE ( 0 ) - -#define pdPASS ( 1 ) -#define pdFAIL ( 0 ) -#define errQUEUE_EMPTY ( 0 ) -#define errQUEUE_FULL ( 0 ) - -/* Error definitions. */ -#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 ) -#define errNO_TASK_TO_RUN ( -2 ) -#define errQUEUE_BLOCKED ( -4 ) -#define errQUEUE_YIELD ( -5 ) - -#endif /* PROJDEFS_H */ - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/queue.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/queue.h deleted file mode 100644 index 4a6c9a660..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/queue.h +++ /dev/null @@ -1,474 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -#ifndef QUEUE_H -#define QUEUE_H - -typedef void * xQueueHandle; - -/** - * queue. h - *
- xQueueHandle xQueueCreate( 
-                              unsigned portBASE_TYPE uxQueueLength, 
-                              unsigned portBASE_TYPE uxItemSize 
-                          );
- * 
- * - * Creates a new queue instance. This allocates the storage required by the - * new queue and returns a handle for the queue. - * - * @param uxQueueLength The maximum number of items that the queue can contain. - * - * @param uxItemSize The number of bytes each item in the queue will require. - * Items are queued by copy, not by reference, so this is the number of bytes - * that will be copied for each posted item. Each item on the queue must be - * the same size. - * - * @return If the queue is successfully create then a handle to the newly - * created queue is returned. If the queue cannot be created then 0 is - * returned. - * - * Example usage: -
- struct AMessage
- {
-    portCHAR ucMessageID;
-    portCHAR ucData[ 20 ];
- };
-
- void vATask( void *pvParameters )
- {
- xQueueHandle xQueue1, xQueue2;
-
-    // Create a queue capable of containing 10 unsigned long values.
-    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );
-    if( xQueue1 == 0 )
-    {
-        // Queue was not created and must not be used.
-    }
-
-    // Create a queue capable of containing 10 pointers to AMessage structures.
-    // These should be passed by pointer as they contain a lot of data.
-    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-    if( xQueue2 == 0 )
-    {
-        // Queue was not created and must not be used.
-    }
-
-    // ... Rest of task code.
- }
- 
- * \defgroup xQueueCreate xQueueCreate - * \ingroup QueueManagement - */ -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); - -/** - * queue. h - *
- portBASE_TYPE xQueueSend( 
-                             xQueueHandle xQueue, 
-                             const void * pvItemToQueue, 
-                             portTickType xTicksToWait 
-                         );
- * 
- * - * Post an item on a queue. The item is queued by copy, not by reference. - * This function must not be called from an interrupt service routine. - * See xQueueSendFromISR () for an alternative which may be used in an ISR. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for space to become available on the queue, should it already - * be full. The call will return immediately if this is set to 0. The - * time is defined in tick periods so the constant portTICK_RATE_MS - * should be used to convert to real time if this is required. - * - * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. - * - * Example usage: -
- struct AMessage
- {
-    portCHAR ucMessageID;
-    portCHAR ucData[ 20 ];
- } xMessage;
-
- unsigned portLONG ulVar = 10UL;
-
- void vATask( void *pvParameters )
- {
- xQueueHandle xQueue1, xQueue2;
- struct AMessage *pxMessage;
-
-    // Create a queue capable of containing 10 unsigned long values.
-    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );
-
-    // Create a queue capable of containing 10 pointers to AMessage structures.
-    // These should be passed by pointer as they contain a lot of data.
-    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-
-    // ...
-
-    if( xQueue1 != 0 )
-    {
-        // Send an unsigned long.  Wait for 10 ticks for space to become 
-        // available if necessary.
-        if( xQueueSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )
-        {
-            // Failed to post the message, even after 10 ticks.
-        }
-    }
-
-    if( xQueue2 != 0 )
-    {
-        // Send a pointer to a struct AMessage object.  Don't block if the
-        // queue is already full.
-        pxMessage = & xMessage;
-        xQueueSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );
-    }
-
-	// ... Rest of task code.
- }
- 
- * \defgroup xQueueSend xQueueSend - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); - -/** - * queue. h - *
- portBASE_TYPE xQueueReceive( 
-                                xQueueHandle xQueue, 
-                                void *pvBuffer, 
-                                portTickType xTicksToWait 
-                            );
- * - * Receive an item from a queue. The item is received by copy so a buffer of - * adequate size must be provided. The number of bytes copied into the buffer - * was defined when the queue was created. - * - * This function must not be used in an interrupt service routine. See - * xQueueReceiveFromISR for an alternative that can. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pvBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for an item to receive should the queue be empty at the time - * of the call. The time is defined in tick periods so the constant - * portTICK_RATE_MS should be used to convert to real time if this is required. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: -
- struct AMessage
- {
-    portCHAR ucMessageID;
-    portCHAR ucData[ 20 ];
- } xMessage;
-
- xQueueHandle xQueue;
- 
- // Task to create a queue and post a value.
- void vATask( void *pvParameters )
- {
- struct AMessage *pxMessage;
-
-    // Create a queue capable of containing 10 pointers to AMessage structures.
-    // These should be passed by pointer as they contain a lot of data.
-    xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
-    if( xQueue == 0 )
-    {
-        // Failed to create the queue.
-    }
-
-    // ...
-
-    // Send a pointer to a struct AMessage object.  Don't block if the
-    // queue is already full.
-    pxMessage = & xMessage;
-    xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );
-
-	// ... Rest of task code.
- }
-
- // Task to receive from the queue.
- void vADifferentTask( void *pvParameters )
- {
- struct AMessage *pxRxedMessage;
-
-    if( xQueue != 0 )
-    {
-        // Receive a message on the created queue.  Block for 10 ticks if a
-        // message is not immediately available.
-        if( xQueueReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )
-        {
-            // pcRxedMessage now points to the struct AMessage variable posted
-            // by vATask.
-        }
-    }
-
-	// ... Rest of task code.
- }
- 
- * \defgroup xQueueReceive xQueueReceive - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueReceive( xQueueHandle xQueue, void *pvBuffer, portTickType xTicksToWait ); - -/** - * queue. h - *
unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue );
- * - * Return the number of messages stored in a queue. - * - * @param xQueue A handle to the queue being queried. - * - * @return The number of messages available in the queue. - * - * \page uxQueueMessagesWaiting uxQueueMessagesWaiting - * \ingroup QueueManagement - */ -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue ); - -/** - * queue. h - *
void vQueueDelete( xQueueHandle xQueue );
- * - * Delete a queue - freeing all the memory allocated for storing of items - * placed on the queue. - * - * @param xQueue A handle to the queue to be deleted. - * - * \page vQueueDelete vQueueDelete - * \ingroup QueueManagement - */ -void vQueueDelete( xQueueHandle xQueue ); - -/** - * queue. h - *
- portBASE_TYPE xQueueSendFromISR( 
-                                    xQueueHandle pxQueue, 
-                                    const void *pvItemToQueue, 
-                                    portBASE_TYPE xTaskPreviouslyWoken 
-                                );
- 
- * - * Post an item on a queue. It is safe to use this function from within an - * interrupt service routine. - * - * Items are queued by copy not reference so it is preferable to only - * queue small items, especially when called from an ISR. In most cases - * it would be preferable to store a pointer to the item being queued. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param cTaskPreviouslyWoken This is included so an ISR can post onto - * the same queue multiple times from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. See the file serial .c in the - * PC port for a good example of this mechanism. - * - * @return pdTRUE if a task was woken by posting onto the queue. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage for buffered IO (where the ISR can obtain more than one value - * per call): -
- void vBufferISR( void )
- {
- portCHAR cIn;
- portBASE_TYPE xTaskWokenByPost;
-
-    // We have not woken a task at the start of the ISR.
-    cTaskWokenByPost = pdFALSE;
-
-    // Loop until the buffer is empty.
-    do
-    {
-        // Obtain a byte from the buffer.
-        cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );						
-
-        // Post the byte.  The first time round the loop cTaskWokenByPost
-        // will be pdFALSE.  If the queue send causes a task to wake we do
-        // not want the task to run until we have finished the ISR, so
-        // xQueueSendFromISR does not cause a context switch.  Also we 
-        // don't want subsequent posts to wake any other tasks, so we store
-        // the return value back into cTaskWokenByPost so xQueueSendFromISR
-        // knows not to wake any task the next iteration of the loop.
-        xTaskWokenByPost = xQueueSendFromISR( xRxQueue, &cIn, cTaskWokenByPost );
-
-    } while( portINPUT_BYTE( BUFFER_COUNT ) );
-
-    // Now the buffer is empty we can switch context if necessary.
-    if( cTaskWokenByPost )
-    {
-        taskYIELD ();
-    }
- }
- 
- * - * \defgroup xQueueSendFromISR xQueueSendFromISR - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ); - -/** - * queue. h - *
- portBASE_TYPE xQueueReceiveFromISR( 
-                                       xQueueHandle pxQueue, 
-                                       void *pvBuffer, 
-                                       portBASE_TYPE *pxTaskWoken 
-                                   ); 
- * 
- * - * Receive an item from a queue. It is safe to use this function from within an - * interrupt service routine. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pvBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param pxTaskWoken A task may be blocked waiting for space to become - * available on the queue. If xQueueReceiveFromISR causes such a task to - * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will - * remain unchanged. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: -
- 
- xQueueHandle xQueue;
- 
- // Function to create a queue and post some values.
- void vAFunction( void *pvParameters )
- {
- portCHAR cValueToPost;
- const portTickType xBlockTime = ( portTickType )0xff;
-
-    // Create a queue capable of containing 10 characters.
-    xQueue = xQueueCreate( 10, sizeof( portCHAR ) );
-    if( xQueue == 0 )
-    {
-        // Failed to create the queue.
-    }
-
-    // ...
-
-    // Post some characters that will be used within an ISR.  If the queue
-    // is full then this task will block for xBlockTime ticks.
-    cValueToPost = 'a';
-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
-    cValueToPost = 'b';
-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
-
-    // ... keep posting characters ... this task may block when the queue
-    // becomes full.
-
-    cValueToPost = 'c';
-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
- }
-
- // ISR that outputs all the characters received on the queue. 
- void vISR_Routine( void )
- {
- portBASE_TYPE xTaskWokenByReceive = pdFALSE;
- portCHAR cRxedChar;
-
-    while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
-    {
-        // A character was received.  Output the character now.
-        vOutputCharacter( cRxedChar );
-
-        // If removing the character from the queue woke the task that was 
-        // posting onto the queue cTaskWokenByReceive will have been set to
-        // pdTRUE.  No matter how many times this loop iterates only one
-        // task will be woken.
-    }
-
-    if( cTaskWokenByPost != ( portCHAR ) pdFALSE;
-    {
-        taskYIELD ();
-    }
- }
- 
- * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - - -/* - * The functions defined above are for passing data to and from tasks. The - * functions below are the equivalents for passing data to and from - * co-rtoutines. - * - * These functions are called from the co-routine macro implementation and - * should not be called directly from application code. Instead use the macro - * wrappers defined within croutine.h. - */ -signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ); -signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); -signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ); -signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/semphr.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/semphr.h deleted file mode 100644 index bae09c746..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/semphr.h +++ /dev/null @@ -1,292 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -#include "queue.h" - -#ifndef SEMAPHORE_H -#define SEMAPHORE_H - -typedef xQueueHandle xSemaphoreHandle; - -#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( unsigned portCHAR ) 1 ) -#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( unsigned portCHAR ) 0 ) -#define semGIVE_BLOCK_TIME ( ( portTickType ) 0 ) - - -/** - * semphr. h - *
vSemaphoreCreateBinary( xSemaphoreHandle xSemaphore )
- * - * Macro that implements a semaphore by using the existing queue mechanism. - * The queue length is 1 as this is a binary semaphore. The data size is 0 - * as we don't want to actually store any data - we just want to know if the - * queue is empty or full. - * - * @param xSemaphore Handle to the created semaphore. Should be of type xSemaphoreHandle. - * - * Example usage: -
- xSemaphoreHandle xSemaphore;
-
- void vATask( void * pvParameters )
- {
-    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
-    // This is a macro so pass the variable in directly.
-    vSemaphoreCreateBinary( xSemaphore );
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.  
-    }
- }
- 
- * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary - * \ingroup Semaphores - */ -#define vSemaphoreCreateBinary( xSemaphore ) { \ - xSemaphore = xQueueCreate( ( unsigned portCHAR ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH ); \ - if( xSemaphore != NULL ) \ - { \ - xSemaphoreGive( xSemaphore ); \ - } \ - } - -/** - * semphr. h - * xSemaphoreTake( - * xSemaphoreHandle xSemaphore, - * portTickType xBlockTime - * ) - * - * Macro to obtain a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (). - * - * @param xSemaphore A handle to the semaphore being obtained. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @param xBlockTime The time in ticks to wait for the semaphore to become - * available. The macro portTICK_RATE_MS can be used to convert this to a - * real time. A block time of zero can be used to poll the semaphore. - * - * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime - * expired without the semaphore becoming available. - * - * Example usage: -
- xSemaphoreHandle xSemaphore = NULL;
-
- // A task that creates a semaphore.
- void vATask( void * pvParameters )
- {
-    // Create the semaphore to guard a shared resource.
-    vSemaphoreCreateBinary( xSemaphore );
- }
-
- // A task that uses the semaphore.
- void vAnotherTask( void * pvParameters )
- {
-    // ... Do other things.
-
-    if( xSemaphore != NULL )
-    {
-        // See if we can obtain the semaphore.  If the semaphore is not available
-        // wait 10 ticks to see if it becomes free.	
-        if( xSemaphoreTake( xSemaphore, ( portTickType ) 10 ) == pdTRUE )
-        {
-            // We were able to obtain the semaphore and can now access the
-            // shared resource.
-
-            // ...
-
-            // We have finished accessing the shared resource.  Release the 
-            // semaphore.
-            xSemaphoreGive( xSemaphore );
-        }
-        else
-        {
-            // We could not obtain the semaphore and can therefore not access
-            // the shared resource safely.
-        }
-    }
- }
- 
- * \defgroup xSemaphoreTake xSemaphoreTake - * \ingroup Semaphores - */ -#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueReceive( ( xQueueHandle ) xSemaphore, NULL, xBlockTime ) - -/** - * semphr. h - *
xSemaphoreGive( xSemaphoreHandle xSemaphore )
- * - * Macro to release a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (), and obtained using sSemaphoreTake (). - * - * This must not be used from an ISR. See xSemaphoreGiveFromISR () for - * an alternative which can be used from an ISR. - * - * @param xSemaphore A handle to the semaphore being released. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. - * Semaphores are implemented using queues. An error can occur if there is - * no space on the queue to post a message - indicating that the - * semaphore was not first obtained correctly. - * - * Example usage: -
- xSemaphoreHandle xSemaphore = NULL;
-
- void vATask( void * pvParameters )
- {
-    // Create the semaphore to guard a shared resource.
-    vSemaphoreCreateBinary( xSemaphore );
-
-    if( xSemaphore != NULL )
-    {
-        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
-        {
-            // We would expect this call to fail because we cannot give
-            // a semaphore without first "taking" it!
-        }
-
-        // Obtain the semaphore - don't block if the semaphore is not
-        // immediately available.
-        if( xSemaphoreTake( xSemaphore, ( portTickType ) 0 ) )
-        {
-            // We now have the semaphore and can access the shared resource.
-
-            // ...
-
-            // We have finished accessing the shared resource so can free the
-            // semaphore.
-            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
-            {
-                // We would not expect this call to fail because we must have
-                // obtained the semaphore to get here.
-            }
-        }
-    }
- }
- 
- * \defgroup xSemaphoreGive xSemaphoreGive - * \ingroup Semaphores - */ -#define xSemaphoreGive( xSemaphore ) xQueueSend( ( xQueueHandle ) xSemaphore, NULL, semGIVE_BLOCK_TIME ) - -/** - * semphr. h - *
- xSemaphoreGiveFromISR( 
-                          xSemaphoreHandle xSemaphore, 
-                          portSHORT sTaskPreviouslyWoken 
-                      )
- * - * Macro to release a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (), and obtained using xSemaphoreTake (). - * - * This macro can be used from an ISR. - * - * @param xSemaphore A handle to the semaphore being released. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @param sTaskPreviouslyWoken This is included so an ISR can make multiple calls - * to xSemaphoreGiveFromISR () from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. See the file serial .c in the - * PC port for a good example of using xSemaphoreGiveFromISR (). - * - * @return pdTRUE if a task was woken by releasing the semaphore. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage: -
- #define LONG_TIME 0xffff
- #define TICKS_TO_WAIT	10
- xSemaphoreHandle xSemaphore = NULL;
-
- // Repetitive task.
- void vATask( void * pvParameters )
- {
-    for( ;; )
-    {
-        // We want this task to run every 10 ticks or a timer.  The semaphore 
-        // was created before this task was started
-
-        // Block waiting for the semaphore to become available.
-        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
-        {
-            // It is time to execute.
-
-            // ...
-
-            // We have finished our task.  Return to the top of the loop where
-            // we will block on the semaphore until it is time to execute 
-            // again.
-        }
-    }
- }
-
- // Timer ISR
- void vTimerISR( void * pvParameters )
- {
- static unsigned portCHAR ucLocalTickCount = 0;
-
-    // A timer tick has occurred.
-
-    // ... Do other time functions.
-
-    // Is it time for vATask () to run?
-    ucLocalTickCount++;
-    if( ucLocalTickCount >= TICKS_TO_WAIT )
-    {
-        // Unblock the task by releasing the semaphore.
-        xSemaphoreGive( xSemaphore );
-
-        // Reset the count so we release the semaphore again in 10 ticks time.
-        ucLocalTickCount = 0;
-    }
- }
- 
- * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR - * \ingroup Semaphores - */ -#define xSemaphoreGiveFromISR( xSemaphore, xTaskPreviouslyWoken ) xQueueSendFromISR( ( xQueueHandle ) xSemaphore, NULL, xTaskPreviouslyWoken ) - - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/task.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/task.h deleted file mode 100644 index 5103f3c2b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/include/task.h +++ /dev/null @@ -1,970 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/* -Changes since V4.3.1: - - + Added xTaskGetSchedulerState() function. -*/ - -#ifndef TASK_H -#define TASK_H - -#include "portable.h" -#include "list.h" - -/*----------------------------------------------------------- - * MACROS AND DEFINITIONS - *----------------------------------------------------------*/ - -#define tskKERNEL_VERSION_NUMBER "V4.4.0" - -/** - * task. h - * - * Type by which tasks are referenced. For example, a call to xTaskCreate - * returns (via a pointer parameter) an xTaskHandle variable that can then - * be used as a parameter to vTaskDelete to delete the task. - * - * \page xTaskHandle xTaskHandle - * \ingroup Tasks - */ -typedef void * xTaskHandle; - -/* - * Used internally only. - */ -typedef struct xTIME_OUT -{ - portBASE_TYPE xOverflowCount; - portTickType xTimeOnEntering; -} xTimeOutType; - -/* - * Defines the priority used by the idle task. This must not be modified. - * - * \ingroup TaskUtils - */ -#define tskIDLE_PRIORITY ( ( unsigned portBASE_TYPE ) 0 ) - -/** - * task. h - * - * Macro for forcing a context switch. - * - * \page taskYIELD taskYIELD - * \ingroup SchedulerControl - */ -#define taskYIELD() portYIELD() - -/** - * task. h - * - * Macro to mark the start of a critical code region. Preemptive context - * switches cannot occur when in a critical region. - * - * NOTE: This may alter the stack (depending on the portable implementation) - * so must be used with care! - * - * \page taskENTER_CRITICAL taskENTER_CRITICAL - * \ingroup SchedulerControl - */ -#define taskENTER_CRITICAL() portENTER_CRITICAL() - -/** - * task. h - * - * Macro to mark the end of a critical code region. Preemptive context - * switches cannot occur when in a critical region. - * - * NOTE: This may alter the stack (depending on the portable implementation) - * so must be used with care! - * - * \page taskEXIT_CRITICAL taskEXIT_CRITICAL - * \ingroup SchedulerControl - */ -#define taskEXIT_CRITICAL() portEXIT_CRITICAL() - -/** - * task. h - * - * Macro to disable all maskable interrupts. - * - * \page taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS - * \ingroup SchedulerControl - */ -#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() - -/** - * task. h - * - * Macro to enable microcontroller interrupts. - * - * \page taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS - * \ingroup SchedulerControl - */ -#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() - -/* Definitions returned by xTaskGetSchedulerState(). */ -#define taskSCHEDULER_NOT_STARTED 0 -#define taskSCHEDULER_RUNNING 1 -#define taskSCHEDULER_SUSPENDED 2 - -/*----------------------------------------------------------- - * TASK CREATION API - *----------------------------------------------------------*/ - -/** - * task. h - *
- portBASE_TYPE xTaskCreate(
-                              pdTASK_CODE pvTaskCode,
-                              const portCHAR * const pcName,
-                              unsigned portSHORT usStackDepth,
-                              void *pvParameters,
-                              unsigned portBASE_TYPE uxPriority,
-                              xTaskHandle *pvCreatedTask
-                          );
- * - * Create a new task and add it to the list of tasks that are ready to run. - * - * @param pvTaskCode Pointer to the task entry function. Tasks - * must be implemented to never return (i.e. continuous loop). - * - * @param pcName A descriptive name for the task. This is mainly used to - * facilitate debugging. Max length defined by tskMAX_TASK_NAME_LEN - default - * is 16. - * - * @param usStackDepth The size of the task stack specified as the number of - * variables the stack can hold - not the number of bytes. For example, if - * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes - * will be allocated for stack storage. - * - * @param pvParameters Pointer that will be used as the parameter for the task - * being created. - * - * @param uxPriority The priority at which the task should run. - * - * @param pvCreatedTask Used to pass back a handle by which the created task - * can be referenced. - * - * @return pdPASS if the task was successfully created and added to a ready - * list, otherwise an error code defined in the file errors. h - * - * Example usage: -
- // Task to be created.
- void vTaskCode( void * pvParameters )
- {
-     for( ;; )
-     {
-         // Task code goes here.
-     }
- }
-
- // Function that creates a task.
- void vOtherFunction( void )
- {
- unsigned char ucParameterToPass;
- xTaskHandle xHandle;
-		
-     // Create the task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
-		
-     // Use the handle to delete the task.
-     vTaskDelete( xHandle );
- }
-   
- * \defgroup xTaskCreate xTaskCreate - * \ingroup Tasks - */ -signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pvCreatedTask ); - -/** - * task. h - *
void vTaskDelete( xTaskHandle pxTask );
- * - * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Remove a task from the RTOS real time kernels management. The task being - * deleted will be removed from all ready, blocked, suspended and event lists. - * - * NOTE: The idle task is responsible for freeing the kernel allocated - * memory from tasks that have been deleted. It is therefore important that - * the idle task is not starved of microcontroller processing time if your - * application makes any calls to vTaskDelete (). Memory allocated by the - * task code is not automatically freed, and should be freed before the task - * is deleted. - * - * See the demo application file death.c for sample code that utilises - * vTaskDelete (). - * - * @param pxTask The handle of the task to be deleted. Passing NULL will - * cause the calling task to be deleted. - * - * Example usage: -
- void vOtherFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create the task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-		
-     // Use the handle to delete the task.
-     vTaskDelete( xHandle );
- }
-   
- * \defgroup vTaskDelete vTaskDelete - * \ingroup Tasks - */ -void vTaskDelete( xTaskHandle pxTask ); - - -/*----------------------------------------------------------- - * TASK CONTROL API - *----------------------------------------------------------*/ - -/** - * task. h - *
void vTaskDelay( portTickType xTicksToDelay );
- * - * Delay a task for a given number of ticks. The actual time that the - * task remains blocked depends on the tick rate. The constant - * portTICK_RATE_MS can be used to calculate real time from the tick - * rate - with the resolution of one tick period. - * - * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * @param xTicksToDelay The amount of time, in tick periods, that - * the calling task should block. - * - * Example usage: -
- // Wait 10 ticks before performing an action.
- // NOTE:
- // This is for demonstration only and would be better achieved
- // using vTaskDelayUntil ().
- void vTaskFunction( void * pvParameters )
- {
- portTickType xDelay, xNextTime;
-
-     // Calc the time at which we want to perform the action
-     // next.
-     xNextTime = xTaskGetTickCount () + ( portTickType ) 10;
-
-     for( ;; )
-     {
-         xDelay = xNextTime - xTaskGetTickCount ();
-         xNextTime += ( portTickType ) 10;
-
-         // Guard against overflow
-         if( xDelay <= ( portTickType ) 10 )
-         {
-             vTaskDelay( xDelay );
-         }
-
-         // Perform action here.
-     }
- }
-   
- * \defgroup vTaskDelay vTaskDelay - * \ingroup TaskCtrl - */ -void vTaskDelay( portTickType xTicksToDelay ); - -/** - * task. h - *
void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement );
- * - * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Delay a task until a specified time. This function can be used by cyclical - * tasks to ensure a constant execution frequency. - * - * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will - * cause a task to block for the specified number of ticks from the time vTaskDelay () is - * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed - * execution frequency as the time between a task starting to execute and that task - * calling vTaskDelay () may not be fixed [the task may take a different path though the - * code between calls, or may get interrupted or preempted a different number of times - * each time it executes]. - * - * Whereas vTaskDelay () specifies a wake time relative to the time at which the function - * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to - * unblock. - * - * The constant portTICK_RATE_MS can be used to calculate real time from the tick - * rate - with the resolution of one tick period. - * - * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the - * task was last unblocked. The variable must be initialised with the current time - * prior to its first use (see the example below). Following this the variable is - * automatically updated within vTaskDelayUntil (). - * - * @param xTimeIncrement The cycle time period. The task will be unblocked at - * time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the - * same xTimeIncrement parameter value will cause the task to execute with - * a fixed interface period. - * - * Example usage: -
- // Perform an action every 10 ticks.
- void vTaskFunction( void * pvParameters )
- {
- portTickType xLastWakeTime;
- const portTickType xFrequency = 10;
-
-     // Initialise the xLastWakeTime variable with the current time.
-     xLastWakeTime = xTaskGetTickCount ();
-     for( ;; )
-     {
-         // Wait for the next cycle.
-         vTaskDelayUntil( &xLastWakeTime, xFrequency );
-
-         // Perform action here.
-     }
- }
-   
- * \defgroup vTaskDelayUntil vTaskDelayUntil - * \ingroup TaskCtrl - */ -void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement ); - -/** - * task. h - *
unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask );
- * - * INCLUDE_xTaskPriorityGet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Obtain the priority of any task. - * - * @param pxTask Handle of the task to be queried. Passing a NULL - * handle results in the priority of the calling task being returned. - * - * @return The priority of pxTask. - * - * Example usage: -
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create a task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-		
-     // ...
-
-     // Use the handle to obtain the priority of the created task.
-     // It was created with tskIDLE_PRIORITY, but may have changed
-     // it itself.
-     if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
-     {
-         // The task has changed it's priority.
-     }
-
-     // ...
-
-     // Is our priority higher than the created task?
-     if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
-     {
-         // Our priority (obtained using NULL handle) is higher.
-     }
- }
-   
- * \defgroup uxTaskPriorityGet uxTaskPriorityGet - * \ingroup TaskCtrl - */ -unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ); - -/** - * task. h - *
void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );
- * - * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Set the priority of any task. - * - * A context switch will occur before the function returns if the priority - * being set is higher than the currently executing task. - * - * @param pxTask Handle to the task for which the priority is being set. - * Passing a NULL handle results in the priority of the calling task being set. - * - * @param uxNewPriority The priority to which the task will be set. - * - * Example usage: -
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create a task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-     // ...
-
-     // Use the handle to raise the priority of the created task.
-     vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
-
-     // ...
-
-     // Use a NULL handle to raise our priority to the same value.
-     vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
- }
-   
- * \defgroup vTaskPrioritySet vTaskPrioritySet - * \ingroup TaskCtrl - */ -void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ); - -/** - * task. h - *
void vTaskSuspend( xTaskHandle pxTaskToSuspend );
- * - * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Suspend any task. When suspended a task will never get any microcontroller - * processing time, no matter what its priority. - * - * Calls to vTaskSuspend are not accumulative - - * i.e. calling vTaskSuspend () twice on the same task still only requires one - * call to vTaskResume () to ready the suspended task. - * - * @param pxTaskToSuspend Handle to the task being suspended. Passing a NULL - * handle will cause the calling task to be suspended. - * - * Example usage: -
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create a task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-		
-     // ...
-
-     // Use the handle to suspend the created task.
-     vTaskSuspend( xHandle );
-
-     // ...
-		
-     // The created task will not run during this period, unless
-     // another task calls vTaskResume( xHandle ).
-		
-     //...
-		
-
-     // Suspend ourselves.
-     vTaskSuspend( NULL );
-
-     // We cannot get here unless another task calls vTaskResume
-     // with our handle as the parameter.
- }
-   
- * \defgroup vTaskSuspend vTaskSuspend - * \ingroup TaskCtrl - */ -void vTaskSuspend( xTaskHandle pxTaskToSuspend ); - -/** - * task. h - *
void vTaskResume( xTaskHandle pxTaskToResume );
- * - * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Resumes a suspended task. - * - * A task that has been suspended by one of more calls to vTaskSuspend () - * will be made available for running again by a single call to - * vTaskResume (). - * - * @param pxTaskToResume Handle to the task being readied. - * - * Example usage: -
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create a task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-		
-     // ...
-
-     // Use the handle to suspend the created task.
-     vTaskSuspend( xHandle );
-
-     // ...
-	
-     // The created task will not run during this period, unless
-     // another task calls vTaskResume( xHandle ).
-		
-     //...
-		
-
-     // Resume the suspended task ourselves.
-     vTaskResume( xHandle );
-
-     // The created task will once again get microcontroller processing
-     // time in accordance with it priority within the system.
- }
-   
- * \defgroup vTaskResume vTaskResume - * \ingroup TaskCtrl - */ -void vTaskResume( xTaskHandle pxTaskToResume ); - -/** - * task. h - *
void xTaskResumeFromISR( xTaskHandle pxTaskToResume );
- * - * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be - * available. See the configuration section for more information. - * - * An implementation of vTaskResume() that can be called from within an ISR. - * - * A task that has been suspended by one of more calls to vTaskSuspend () - * will be made available for running again by a single call to - * xTaskResumeFromISR (). - * - * @param pxTaskToResume Handle to the task being readied. - * - * \defgroup vTaskResumeFromISR vTaskResumeFromISR - * \ingroup TaskCtrl - */ -portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ); - -/*----------------------------------------------------------- - * SCHEDULER CONTROL - *----------------------------------------------------------*/ - -/** - * task. h - *
void vTaskStartScheduler( void );
- * - * Starts the real time kernel tick processing. After calling the kernel - * has control over which tasks are executed and when. This function - * does not return until an executing task calls vTaskEndScheduler (). - * - * At least one task should be created via a call to xTaskCreate () - * before calling vTaskStartScheduler (). The idle task is created - * automatically when the first application task is created. - * - * See the demo application file main.c for an example of creating - * tasks and starting the kernel. - * - * Example usage: -
- void vAFunction( void )
- {
-     // Create at least one task before starting the kernel.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
-     // Start the real time kernel with preemption.
-     vTaskStartScheduler ();
-
-     // Will not get here unless a task calls vTaskEndScheduler ()
- }
-   
- * - * \defgroup vTaskStartScheduler vTaskStartScheduler - * \ingroup SchedulerControl - */ -void vTaskStartScheduler( void ); - -/** - * task. h - *
void vTaskEndScheduler( void );
- * - * Stops the real time kernel tick. All created tasks will be automatically - * deleted and multitasking (either preemptive or cooperative) will - * stop. Execution then resumes from the point where vTaskStartScheduler () - * was called, as if vTaskStartScheduler () had just returned. - * - * See the demo application file main. c in the demo/PC directory for an - * example that uses vTaskEndScheduler (). - * - * vTaskEndScheduler () requires an exit function to be defined within the - * portable layer (see vPortEndScheduler () in port. c for the PC port). This - * performs hardware specific operations such as stopping the kernel tick. - * - * vTaskEndScheduler () will cause all of the resources allocated by the - * kernel to be freed - but will not free resources allocated by application - * tasks. - * - * Example usage: -
- void vTaskCode( void * pvParameters )
- {
-     for( ;; )
-     {
-         // Task code goes here.
-
-         // At some point we want to end the real time kernel processing
-         // so call ...
-         vTaskEndScheduler ();
-     }
- }
-
- void vAFunction( void )
- {
-     // Create at least one task before starting the kernel.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
-     // Start the real time kernel with preemption.
-     vTaskStartScheduler ();
-
-     // Will only get here when the vTaskCode () task has called
-     // vTaskEndScheduler ().  When we get here we are back to single task
-     // execution.
- }
-   
- * - * \defgroup vTaskEndScheduler vTaskEndScheduler - * \ingroup SchedulerControl - */ -void vTaskEndScheduler( void ); - -/** - * task. h - *
void vTaskSuspendAll( void );
- * - * Suspends all real time kernel activity while keeping interrupts (including the - * kernel tick) enabled. - * - * After calling vTaskSuspendAll () the calling task will continue to execute - * without risk of being swapped out until a call to xTaskResumeAll () has been - * made. - * - * Example usage: -
- void vTask1( void * pvParameters )
- {
-     for( ;; )
-     {
-         // Task code goes here.
-
-         // ...
-
-         // At some point the task wants to perform a long operation during
-         // which it does not want to get swapped out.  It cannot use
-         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
-         // operation may cause interrupts to be missed - including the
-         // ticks.
-
-         // Prevent the real time kernel swapping out the task.
-         vTaskSuspendAll ();
-
-         // Perform the operation here.  There is no need to use critical
-         // sections as we have all the microcontroller processing time.
-         // During this time interrupts will still operate and the kernel
-         // tick count will be maintained.
-
-         // ...
-
-         // The operation is complete.  Restart the kernel.
-         xTaskResumeAll ();
-     }
- }
-   
- * \defgroup vTaskSuspendAll vTaskSuspendAll - * \ingroup SchedulerControl - */ -void vTaskSuspendAll( void ); - -/** - * task. h - *
portCHAR xTaskResumeAll( void );
- * - * Resumes real time kernel activity following a call to vTaskSuspendAll (). - * After a call to vTaskSuspendAll () the kernel will take control of which - * task is executing at any time. - * - * @return If resuming the scheduler caused a context switch then pdTRUE is - * returned, otherwise pdFALSE is returned. - * - * Example usage: -
- void vTask1( void * pvParameters )
- {
-     for( ;; )
-     {
-         // Task code goes here.
-
-         // ...
-
-         // At some point the task wants to perform a long operation during
-         // which it does not want to get swapped out.  It cannot use
-         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
-         // operation may cause interrupts to be missed - including the
-         // ticks.
-
-         // Prevent the real time kernel swapping out the task.
-         vTaskSuspendAll ();
-
-         // Perform the operation here.  There is no need to use critical
-         // sections as we have all the microcontroller processing time.
-         // During this time interrupts will still operate and the real
-         // time kernel tick count will be maintained.
-
-         // ...
-
-         // The operation is complete.  Restart the kernel.  We want to force
-         // a context switch - but there is no point if resuming the scheduler
-         // caused a context switch already.
-         if( !xTaskResumeAll () )
-         {
-              taskYIELD ();
-         }
-     }
- }
-   
- * \defgroup xTaskResumeAll xTaskResumeAll - * \ingroup SchedulerControl - */ -signed portBASE_TYPE xTaskResumeAll( void ); - - -/*----------------------------------------------------------- - * TASK UTILITIES - *----------------------------------------------------------*/ - -/** - * task. h - *
volatile portTickType xTaskGetTickCount( void );
- * - * @return The count of ticks since vTaskStartScheduler was called. - * - * \page xTaskGetTickCount xTaskGetTickCount - * \ingroup TaskUtils - */ -portTickType xTaskGetTickCount( void ); - -/** - * task. h - *
unsigned portSHORT uxTaskGetNumberOfTasks( void );
- * - * @return The number of tasks that the real time kernel is currently managing. - * This includes all ready, blocked and suspended tasks. A task that - * has been deleted but not yet freed by the idle task will also be - * included in the count. - * - * \page uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks - * \ingroup TaskUtils - */ -unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ); - -/** - * task. h - *
void vTaskList( portCHAR *pcWriteBuffer );
- * - * configUSE_TRACE_FACILITY, INCLUDE_vTaskDelete and INCLUDE_vTaskSuspend - * must all be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * NOTE: This function will disable interrupts for its duration. It is - * not intended for normal application runtime use but as a debug aid. - * - * Lists all the current tasks, along with their current state and stack - * usage high water mark. - * - * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or - * suspended ('S'). - * - * @param pcWriteBuffer A buffer into which the above mentioned details - * will be written, in ascii form. This buffer is assumed to be large - * enough to contain the generated report. Approximately 40 bytes per - * task should be sufficient. - * - * \page vTaskList vTaskList - * \ingroup TaskUtils - */ -void vTaskList( signed portCHAR *pcWriteBuffer ); - -/** - * task. h - *
void vTaskStartTrace( portCHAR * pcBuffer, unsigned portBASE_TYPE uxBufferSize );
- * - * Starts a real time kernel activity trace. The trace logs the identity of - * which task is running when. - * - * The trace file is stored in binary format. A separate DOS utility called - * convtrce.exe is used to convert this into a tab delimited text file which - * can be viewed and plotted in a spread sheet. - * - * @param pcBuffer The buffer into which the trace will be written. - * - * @param ulBufferSize The size of pcBuffer in bytes. The trace will continue - * until either the buffer in full, or ulTaskEndTrace () is called. - * - * \page vTaskStartTrace vTaskStartTrace - * \ingroup TaskUtils - */ -void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ); - -/** - * task. h - *
unsigned portLONG ulTaskEndTrace( void );
- * - * Stops a kernel activity trace. See vTaskStartTrace (). - * - * @return The number of bytes that have been written into the trace buffer. - * - * \page usTaskEndTrace usTaskEndTrace - * \ingroup TaskUtils - */ -unsigned portLONG ulTaskEndTrace( void ); - - -/*----------------------------------------------------------- - * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES - *----------------------------------------------------------*/ - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY - * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS - * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * Called from the real time kernel tick (either preemptive or cooperative), - * this increments the tick count and checks if any tasks that are blocked - * for a finite period required removing from a blocked list and placing on - * a ready list. - */ -inline void vTaskIncrementTick( void ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. - * - * Removes the calling task from the ready list and places it both - * on the list of tasks waiting for a particular event, and the - * list of delayed tasks. The task will be removed from both lists - * and replaced on the ready list should either the event occur (and - * there be no higher priority tasks waiting on the same event) or - * the delay period expires. - * - * @param pxEventList The list containing tasks that are blocked waiting - * for the event to occur. - * - * @param xTicksToWait The maximum amount of time that the task should wait - * for the event to occur. This is specified in kernel ticks,the constant - * portTICK_RATE_MS can be used to convert kernel ticks into a real time - * period. - */ -void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. - * - * Removes a task from both the specified event list and the list of blocked - * tasks, and places it on a ready queue. - * - * xTaskRemoveFromEventList () will be called if either an event occurs to - * unblock a task, or the block timeout period expires. - * - * @return pdTRUE if the task being removed has a higher priority than the task - * making the call, otherwise pdFALSE. - */ -signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * INCLUDE_vTaskCleanUpResources and INCLUDE_vTaskSuspend must be defined as 1 - * for this function to be available. - * See the configuration section for more information. - * - * Empties the ready and delayed queues of task control blocks, freeing the - * memory allocated for the task control block and task stacks as it goes. - */ -void vTaskCleanUpResources( void ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY - * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS - * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * Sets the pointer to the current TCB to the TCB of the highest priority task - * that is ready to run. - */ -inline void vTaskSwitchContext( void ); - -/* - * Return the handle of the calling task. - */ -xTaskHandle xTaskGetCurrentTaskHandle( void ); - -/* - * Capture the current time status for future reference. - */ -void vTaskSetTimeOutState( xTimeOutType *pxTimeOut ); - -/* - * Compare the time status now with that previously captured to see if the - * timeout has expired. - */ -portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType *pxTimeOut, portTickType * const pxTicksToWait ); - -/* - * Shortcut used by the queue implementation to prevent unnecessary call to - * taskYIELD(); - */ -void vTaskMissedYield( void ); - -/* - * Returns the scheduler state as taskSCHEDULER_RUNNING, - * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED. - */ -portBASE_TYPE xTaskGetSchedulerState( void ); - -#endif /* TASK_H */ - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/list.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/list.c deleted file mode 100644 index 3faa8b4e4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/list.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/* -Changes from V1.2.0 - - + Removed the volatile modifier from the function parameters. This was - only ever included to prevent compiler warnings. Now warnings are - removed by casting parameters where the calls are made. - - + prvListGetOwnerOfNextEntry() and prvListGetOwnerOfHeadEntry() have been - removed from the c file and added as macros to the h file. - - + uxNumberOfItems has been added to the list structure. This removes the - need for a pointer comparison when checking if a list is empty, and so - is slightly faster. - - + Removed the NULL check in vListRemove(). This makes the call faster but - necessitates any application code utilising the list implementation to - ensure NULL pointers are not passed. - -Changes from V2.0.0 - - + Double linked the lists to allow faster removal item removal. - -Changes from V2.6.1 - - + Make use of the new portBASE_TYPE definition where ever appropriate. - -Changes from V3.0.0 - - + API changes as described on the FreeRTOS.org WEB site. - -Changes from V3.2.4 - - + Removed the pxHead member of the xList structure. This always pointed - to the same place so has been removed to free a few bytes of RAM. - - + Introduced the xMiniListItem structure that does not include the - xListItem members that are not required by the xListEnd member of a list. - Again this was done to reduce RAM usage. - - + Changed the volatile definitions of some structure members to clean up - the code where the list structures are used. - -Changes from V4.0.4 - - + Optimised vListInsert() in the case when the wake time is the maximum - tick count value. -*/ - -#include -#include "FreeRTOS.h" -#include "list.h" - -/*----------------------------------------------------------- - * PUBLIC LIST API documented in list.h - *----------------------------------------------------------*/ - -void vListInitialise( xList *pxList ) -{ - /* The list structure contains a list item which is used to mark the - end of the list. To initialise the list the list end is inserted - as the only list entry. */ - pxList->pxIndex = ( xListItem * ) &( pxList->xListEnd ); - - /* The list end value is the highest possible value in the list to - ensure it remains at the end of the list. */ - pxList->xListEnd.xItemValue = portMAX_DELAY; - - /* The list end next and previous pointers point to itself so we know - when the list is empty. */ - pxList->xListEnd.pxNext = ( xListItem * ) &( pxList->xListEnd ); - pxList->xListEnd.pxPrevious = ( xListItem * ) &( pxList->xListEnd ); - - pxList->uxNumberOfItems = 0; -} -/*-----------------------------------------------------------*/ - -void vListInitialiseItem( xListItem *pxItem ) -{ - /* Make sure the list item is not recorded as being on a list. */ - pxItem->pvContainer = NULL; -} -/*-----------------------------------------------------------*/ - -void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ) -{ -volatile xListItem * pxIndex; - - /* Insert a new list item into pxList, but rather than sort the list, - makes the new list item the last item to be removed by a call to - pvListGetOwnerOfNextEntry. This means it has to be the item pointed to by - the pxIndex member. */ - pxIndex = pxList->pxIndex; - - pxNewListItem->pxNext = pxIndex->pxNext; - pxNewListItem->pxPrevious = pxList->pxIndex; - pxIndex->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; - pxIndex->pxNext = ( volatile xListItem * ) pxNewListItem; - pxList->pxIndex = ( volatile xListItem * ) pxNewListItem; - - /* Remember which list the item is in. */ - pxNewListItem->pvContainer = ( void * ) pxList; - - ( pxList->uxNumberOfItems )++; -} -/*-----------------------------------------------------------*/ - -void vListInsert( xList *pxList, xListItem *pxNewListItem ) -{ -volatile xListItem *pxIterator; -portTickType xValueOfInsertion; - - /* Insert the new list item into the list, sorted in ulListItem order. */ - xValueOfInsertion = pxNewListItem->xItemValue; - - /* If the list already contains a list item with the same item value then - the new list item should be placed after it. This ensures that TCB's which - are stored in ready lists (all of which have the same ulListItem value) - get an equal share of the CPU. However, if the xItemValue is the same as - the back marker the iteration loop below will not end. This means we need - to guard against this by checking the value first and modifying the - algorithm slightly if necessary. */ - if( xValueOfInsertion == portMAX_DELAY ) - { - pxIterator = pxList->xListEnd.pxPrevious; - } - else - { - for( pxIterator = ( xListItem * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) - { - /* There is nothing to do here, we are just iterating to the - wanted insertion position. */ - } - } - - pxNewListItem->pxNext = pxIterator->pxNext; - pxNewListItem->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; - pxNewListItem->pxPrevious = pxIterator; - pxIterator->pxNext = ( volatile xListItem * ) pxNewListItem; - - /* Remember which list the item is in. This allows fast removal of the - item later. */ - pxNewListItem->pvContainer = ( void * ) pxList; - - ( pxList->uxNumberOfItems )++; -} -/*-----------------------------------------------------------*/ - -void vListRemove( xListItem *pxItemToRemove ) -{ -xList * pxList; - - pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; - pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; - - /* The list item knows which list it is in. Obtain the list from the list - item. */ - pxList = ( xList * ) pxItemToRemove->pvContainer; - - /* Make sure the index is left pointing to a valid item. */ - if( pxList->pxIndex == pxItemToRemove ) - { - pxList->pxIndex = pxItemToRemove->pxPrevious; - } - - pxItemToRemove->pvContainer = NULL; - ( pxList->uxNumberOfItems )--; -} -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/port.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/port.c deleted file mode 100644 index 797cb5078..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/port.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * MODBUS Library: SAM7X Port - * Copyright (c) 2007 Christian Walter - * All rights reserved. - * - * $Id$ - */ -/* - * FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - * - * This file is part of the FreeRTOS.org distribution. - * - * FreeRTOS.org is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * FreeRTOS.org is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with FreeRTOS.org; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * A special exception to the GPL can be applied should you wish to distribute - * a combined work that includes FreeRTOS.org, without being obliged to provide - * the source code for any proprietary components. See the licensing section - * of http://www.FreeRTOS.org for full details of how and when the exception - * can be applied. - * - **************************************************************************** - * See http://www.FreeRTOS.org for documentation, latest information, license - * and contact details. Please ensure to read the configuration and relevant - * port sections of the online documentation. - * - * Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - * with commercial development and support options. - *************************************************************************** - */ - -/* ----------------------- System includes ----------------------------------*/ -#include - -/* ----------------------- FreeRTOS includes --------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "AT91SAM7X256.h" -#include "lib_AT91SAM7X256.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) -#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) -#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) - -/* -#define portPRESCALE_VALUE 0x00 -#define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 ) -#define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 ) - -#define portPIT_CLOCK_DIVISOR ( ( unsigned portLONG ) 16 ) -#define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS ) - -#define portINT_LEVEL_SENSITIVE 0 -#define portPIT_ENABLE ( ( unsigned portSHORT ) 0x1 << 24 ) -#define portPIT_INT_ENABLE ( ( unsigned portSHORT ) 0x1 << 25 ) -*/ - -/* ----------------------- Type definitions ---------------------------------*/ - -/* ----------------------- Static variables ---------------------------------*/ - -/* ----------------------- Function prototypes ------------------------------*/ -extern void vPortISRStartFirstTask( void ); -extern void vNonPreemptiveTick ( void ); -extern void vPreemptiveTick( void ); - -/* ----------------------- Static functions ---------------------------------*/ -static void prvSetupTimerInterrupt( void ); - -/* ----------------------- Start implementation -----------------------------*/ - -portSTACK_TYPE * -pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ - portSTACK_TYPE *pxOriginalTOS; - - pxOriginalTOS = pxTopOfStack; - /* Setup the initial stack of the task. The stack is set exactly as - * expected by the portRESTORE_CONTEXT() macro. - */ - - /* First on the stack is the return address - which in this case is the - * start of the task. The offset is added to make the return address appear - * as it would within an IRQ ISR. - */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - * R0. - */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack--; - - /* The last thing onto the stack is the status register, which is set for - * system mode, with interrupts enabled. - */ - *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; - -#ifdef THUMB_INTERWORK - { - /* We want the task to start in thumb mode. */ - *pxTopOfStack |= portTHUMB_MODE_BIT; - } -#endif - - pxTopOfStack--; - - /* Some optimisation levels use the stack differently to others. This - * means the interrupt flags cannot always be stored on the stack and will - * instead be stored in a variable, which is then saved as part of the - * tasks context. - */ - *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; - - return pxTopOfStack; -} - -portBASE_TYPE -xPortStartScheduler( void ) -{ - /* Start the timer that generates the tick ISR. Interrupts are disabled - * here already. - */ - prvSetupTimerInterrupt( ); - - /* Start the first task. */ - vPortISRStartFirstTask( ); - - /* Should not get here! */ - return 0; -} - -void -vPortEndScheduler( void ) -{ -} - -/* - * Setup the timer 0 to generate the tick interrupts at the required frequency. - */ -static void -prvSetupTimerInterrupt( void ) -{ - /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends - * on whether the preemptive or cooperative scheduler is being used. - */ -#if configUSE_PREEMPTION == 0 - AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, - AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, - ( void ( * )( void ) )vNonPreemptiveTick ); -#else - AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, - AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, - ( void ( * )( void ) )vPreemptiveTick ); - -#endif - - /* Configure the PIT period. */ - AT91F_PITInit( AT91C_BASE_PITC, portTICK_RATE_MS * 1000U, configCPU_CLOCK_HZ / 1000000U ); - AT91F_PITEnableInt( AT91C_BASE_PITC ); - AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/portISR.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/portISR.c deleted file mode 100644 index a9649127a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/portISR.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - * MODBUS Library: SAM7X Port - * Copyright (c) 2007 Christian Walter - * All rights reserved. - * - * $Id$ - */ -/* - * FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - * - * This file is part of the FreeRTOS.org distribution. - * - * FreeRTOS.org is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * FreeRTOS.org is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with FreeRTOS.org; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * A special exception to the GPL can be applied should you wish to distribute - * a combined work that includes FreeRTOS.org, without being obliged to provide - * the source code for any proprietary components. See the licensing section - * of http://www.FreeRTOS.org for full details of how and when the exception - * can be applied. - * - **************************************************************************** - * See http://www.FreeRTOS.org for documentation, latest information, license - * and contact details. Please ensure to read the configuration and relevant - * port sections of the online documentation. - * - * Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - * with commercial development and support options. - *************************************************************************** - */ - -/* ----------------------- System includes ----------------------------------*/ -#include - -/* ----------------------- FreeRTOS includes --------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "AT91SAM7X256.h" -#include "lib_AT91SAM7X256.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 ) -#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 ) -#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) -volatile unsigned portLONG ulCriticalNesting = 9999UL; - -/* ----------------------- Type definitions ---------------------------------*/ - -/* ----------------------- Static variables ---------------------------------*/ - -/* ----------------------- Function prototypes ------------------------------*/ -void vPortDisableInterruptsFromThumb( void ) __attribute__ ( ( naked ) ); -void vPortEnableInterruptsFromThumb( void ) __attribute__ ( ( naked ) ); -void vNonPreemptiveTick( void ) __attribute__ ( ( interrupt( "IRQ" ) ) ); -void vPreemptiveTick( void ) __attribute__ ( ( naked ) ); -void vPortYieldProcessor( void ) __attribute__ ( ( interrupt( "SWI" ), naked ) ); - -void vPortISRStartFirstTask( void ); - -/* ----------------------- Static functions ---------------------------------*/ - -/* ----------------------- Start implementation -----------------------------*/ - -void -vPortISRStartFirstTask( void ) -{ - /* Simply start the scheduler. This is included here as it can only be - * called from ARM mode. - */ - portRESTORE_CONTEXT( ); -} - -/* - * Called by portYIELD() or taskYIELD() to manually force a context switch. - * - * When a context switch is performed from the task level the saved task - * context is made to look as if it occurred from within the tick ISR. This - * way the same restore context function can be used when restoring the context - * saved from the ISR or that saved from a call to vPortYieldProcessor. - */ -void -vPortYieldProcessor( void ) -{ - /* Within an IRQ ISR the link register has an offset from the true return - * address, but an SWI ISR does not. Add the offset manually so the same - * ISR return code can be used in both cases. - */ - asm volatile ( "ADD LR, LR, #4" ); - - /* Perform the context switch. First save the context of the current task. */ - portSAVE_CONTEXT( ); - - /* Find the highest priority task that is ready to run. */ - vTaskSwitchContext( ); - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT( ); -} - -/* - * The ISR used for the scheduler tick depends on whether the cooperative or - * the preemptive scheduler is being used. - */ -#if configUSE_PREEMPTION == 0 - - - -void -vNonPreemptiveTick( void ) -{ - unsigned portLONG ulDummy; - - /* Increment the tick count - which may wake some tasks but as the - * preemptive scheduler is not being used any woken task is not given - * processor time no matter what its priority. - */ - vTaskIncrementTick( ); - - /* Clear the PIT interrupt. */ - AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR; -} -#else -void -vPreemptiveTick( void ) -{ - /* Save the context of the current task. */ - portSAVE_CONTEXT( ); - - /* Increment the tick count - this may wake a task. */ - vTaskIncrementTick( ); - - /* Find the highest priority task that is ready to run. */ - vTaskSwitchContext( ); - - /* End the interrupt in the AIC. */ - AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;; - - portRESTORE_CONTEXT( ); -} -#endif - -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions here to - * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then - * the utilities are defined as macros in portmacro.h - as per other ports. - */ -void -vPortDisableInterruptsFromThumb( void ) -{ - asm volatile ( "STMDB SP!, {R0}\n\t" /* Push R0. */ - "MRS R0, CPSR\n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0\n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}\n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ -} - -void -vPortEnableInterruptsFromThumb( void ) -{ - asm volatile ( "STMDB SP!, {R0}\n\t" /* Push R0. */ - "MRS R0, CPSR\n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0\n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0\n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}\n\t" /* Pop R0. */ - "BX R14" ); /* Return back to thumb. */ -} - -/* The code generated by the GCC compiler uses the stack in different ways at - * different optimisation levels. The interrupt flags can therefore not always - * be saved to the stack. Instead the critical section nesting level is stored - * in a variable, which is then saved as part of the stack context. - */ -void -vPortEnterCritical( void ) -{ - /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ - asm volatile ( "STMDB SP!, {R0}\n\t" /* Push R0. */ - "MRS R0, CPSR\n\t" /* Get CPSR. */ - "ORR R0, R0, #0xC0\n\t" /* Disable IRQ, FIQ. */ - "MSR CPSR, R0\n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - - /* Now interrupts are disabled ulCriticalNesting can be accessed - * directly. Increment ulCriticalNesting to keep a count of how many times - * portENTER_CRITICAL() has been called. - */ - ulCriticalNesting++; -} - -void -vPortExitCritical( void ) -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - /* Enable interrupts as per portEXIT_CRITICAL(). */ - asm volatile ( "STMDB SP!, {R0}\n\t" /* Push R0. */ - "MRS R0, CPSR\n\t" /* Get CPSR. */ - "BIC R0, R0, #0xC0\n\t" /* Enable IRQ, FIQ. */ - "MSR CPSR, R0\n\t" /* Write back modified value. */ - "LDMIA SP!, {R0}" ); /* Pop R0. */ - } - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/portmacro.h deleted file mode 100644 index 43593c56e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/GCC/ARM7_AT91SAM7S/portmacro.h +++ /dev/null @@ -1,230 +0,0 @@ -/* - * MODBUS Library: SAM7X Port - * Copyright (c) 2007 Christian Walter - * All rights reserved. - * - * $Id$ - */ -/* - * FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - * - * This file is part of the FreeRTOS.org distribution. - * - * FreeRTOS.org is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * FreeRTOS.org is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with FreeRTOS.org; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * A special exception to the GPL can be applied should you wish to distribute - * a combined work that includes FreeRTOS.org, without being obliged to provide - * the source code for any proprietary components. See the licensing section - * of http://www.FreeRTOS.org for full details of how and when the exception - * can be applied. - * - **************************************************************************** - * See http://www.FreeRTOS.org for documentation, latest information, license - * and contact details. Please ensure to read the configuration and relevant - * port sections of the online documentation. - * - * Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - * with commercial development and support options. - *************************************************************************** - */ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/* ----------------------- Defines (Type definitions) -----------------------*/ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE portLONG - -#if( configUSE_16_BIT_TICKS == 1 ) -typedef unsigned portSHORT portTickType; -#define portMAX_DELAY ( portTickType ) 0xffff -#else -typedef unsigned portLONG portTickType; -#define portMAX_DELAY ( portTickType ) 0xffffffff -#endif - -/* ----------------------- Defines (Architecture specific) ------------------*/ - -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -#define portNOP() asm volatile ( "NOP" ); - -/* - * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR - * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but - * are included here for efficiency. An attempt to call one from - * THUMB mode code will result in a compile time error. - */ -#define portRESTORE_CONTEXT() do { \ - extern volatile void * volatile pxCurrentTCB; \ - extern volatile unsigned portLONG ulCriticalNesting; \ - \ - /* Set the LR to the task stack. */ \ - asm volatile ( \ - "LDR R0, =pxCurrentTCB\n\t" \ - "LDR R0, [R0]\n\t" \ - "LDR LR, [R0]\n\t" \ - \ - /* The critical nesting depth is the first item on the stack. */ \ - /* Load it into the ulCriticalNesting variable. */ \ - "LDR R0, =ulCriticalNesting\n\t" \ - "LDMFD LR!, {R1}\n\t" \ - "STR R1, [R0]\n\t" \ - \ - /* Get the SPSR from the stack. */ \ - "LDMFD LR!, {R0}\n\t" \ - "MSR SPSR, R0\n\t" \ - \ - /* Restore all system mode registers for the task. */ \ - "LDMFD LR, {R0-R14}^\n\t" \ - "NOP\n\t" \ - \ - /* Restore the return address. */ \ - "LDR LR, [LR, #+60]\n\t" \ - \ - /* And return - correcting the offset in the LR to obtain the */ \ - /* correct address. */ \ - "SUBS PC, LR, #4\n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} while( 0 ) - -#define portSAVE_CONTEXT() do { \ - extern volatile void * volatile pxCurrentTCB; \ - extern volatile unsigned portLONG ulCriticalNesting; \ - \ - /* Push R0 as we are going to use the register. */ \ - asm volatile ( \ - "STMDB SP!, {R0}\n\t" \ - \ - /* Set R0 to point to the task stack pointer. */ \ - "STMDB SP,{SP}^\n\t" \ - "NOP\n\t" \ - "SUB SP, SP, #4\n\t" \ - "LDMIA SP!,{R0}\n\t" \ - \ - /* Push the return address onto the stack. */ \ - "STMDB R0!, {LR}\n\t" \ - \ - /* Now we have saved LR we can use it instead of R0. */ \ - "MOV LR, R0\n\t" \ - \ - /* Pop R0 so we can save it onto the system mode stack. */ \ - "LDMIA SP!, {R0}\n\t" \ - \ - /* Push all the system mode registers onto the task stack. */ \ - "STMDB LR,{R0-LR}^\n\t" \ - "NOP\n\t" \ - "SUB LR, LR, #60\n\t" \ - \ - /* Push the SPSR onto the task stack. */ \ - "MRS R0, SPSR\n\t" \ - "STMDB LR!, {R0}\n\t" \ - \ - "LDR R0, =ulCriticalNesting\n\t" \ - "LDR R0, [R0]\n\t" \ - "STMDB LR!, {R0}\n\t" \ - \ - /* Store the new top of stack for the task. */ \ - "LDR R0, =pxCurrentTCB\n\t" \ - "LDR R0, [R0]\n\t" \ - "STR LR, [R0]\n\t" \ - ); \ - ( void ) ulCriticalNesting; \ - ( void ) pxCurrentTCB; \ -} while( 0 ) - -#define portENTER_SWITCHING_ISR() do { \ - /* Save the context of the interrupted task. */ \ - portSAVE_CONTEXT(); \ - \ - /* We don't know the stack requirements for the ISR, so the frame */ \ - /* pointer will be set to the top of the task stack, and the stack*/ \ - /* pointer left where it is. The IRQ stack will get used for any */ \ - /* functions calls made by this ISR. */ \ - asm volatile ( "SUB R11, LR, #4" ); \ - { - -#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ - /* If a switch is required then we just need to call */ \ - /* vTaskSwitchContext() as the context has already been */ \ - /* saved. */ \ - if( SwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ - } \ - /* Restore the context of which ever task is now the highest */ \ - /* priority that is ready to run. */ \ - portRESTORE_CONTEXT(); \ -} while( 0 ) - -#define portYIELD() asm volatile ( "SWI" ); - -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions in - * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not - * defined then the utilities are defined as macros here - as per other ports. - */ -#ifdef THUMB_INTERWORK - -extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ( ( naked ) ); -extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ( ( naked ) ); - -#define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() -#define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() - -#else - -#define portDISABLE_INTERRUPTS() do { \ - asm volatile ( \ - "STMDB SP!, {R0}\n\t" /* Push R0. */ \ - "MRS R0, CPSR\n\t" /* Get CPSR. */ \ - "ORR R0, R0, #0xC0\n\t" /* Disable IRQ, FIQ. */ \ - "MSR CPSR, R0\n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0}" ); /* Pop R0. */ \ -} while( 0 ) - -#define portENABLE_INTERRUPTS() do { \ - asm volatile ( \ - "STMDB SP!, {R0}\n\t" /* Push R0. */ \ - "MRS R0, CPSR\n\t" /* Get CPSR. */ \ - "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \ - "MSR CPSR, R0\n\t" /* Write back modified value. */ \ - "LDMIA SP!, {R0}" ); /* Pop R0. */ \ -} while( 0 ) -#endif - -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); - -/* ----------------------- Defines (Other) ----------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_1.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_1.c deleted file mode 100644 index 57a7e4e0b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_1.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/* - -Changes between V2.5.1 and V2.5.1 - - + The memory pool has been defined within a struct to ensure correct memory - alignment on 32bit systems. - -Changes between V2.6.1 and V3.0.0 - - + An overflow check has been added to ensure the next free byte variable - does not wrap around. -*/ - - -/* - * The simplest possible implementation of pvPortMalloc(). Note that this - * implementation does NOT allow allocated memory to be freed again. - * - * See heap_2.c and heap_3.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ -#include -#include "FreeRTOS.h" -#include "task.h" - -/* Setup the correct byte alignment mask for the defined byte alignment. */ - -#if portBYTE_ALIGNMENT == 8 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0007 ) -#endif - -#if portBYTE_ALIGNMENT == 4 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) -#endif - -#if portBYTE_ALIGNMENT == 2 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) -#endif - -#if portBYTE_ALIGNMENT == 1 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) -#endif - -#ifndef heapBYTE_ALIGNMENT_MASK - #error "Invalid portBYTE_ALIGNMENT definition" -#endif - -/* Allocate the memory for the heap. The struct is used to force byte -alignment without using any non-portable code. */ -static struct xRTOS_HEAP -{ - unsigned portLONG ulDummy; - unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; -} xHeap; - -static size_t xNextFreeByte = ( size_t ) 0; -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -void *pvReturn = NULL; - - /* Ensure that blocks are always aligned to the required number of bytes. */ - #if portBYTE_ALIGNMENT != 1 - if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) - { - /* Byte alignment required. */ - xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); - } - #endif - - vTaskSuspendAll(); - { - /* Check there is enough room left for the allocation. */ - if( ( ( xNextFreeByte + xWantedSize ) < configTOTAL_HEAP_SIZE ) && - ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) )/* Check for overflow. */ - { - /* Return the next free byte then increment the index past this - block. */ - pvReturn = &( xHeap.ucHeap[ xNextFreeByte ] ); - xNextFreeByte += xWantedSize; - } - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ - /* Memory cannot be freed using this scheme. See heap_2.c and heap_3.c - for alternative implementations, and the memory management pages of - http://www.FreeRTOS.org for more information. */ - ( void ) pv; -} -/*-----------------------------------------------------------*/ - -void vPortInitialiseBlocks( void ) -{ - /* Only required when static memory is not cleared. */ - xNextFreeByte = ( size_t ) 0; -} - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_2.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_2.c deleted file mode 100644 index f733e7dd3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_2.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/* - * A sample implementation of pvPortMalloc() and vPortFree() that permits - * allocated blocks to be freed, but does not combine adjacent free blocks - * into a single larger block. - * - * See heap_1.c and heap_3.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ -#include - -#include "FreeRTOS.h" -#include "task.h" - -/* Setup the correct byte alignment mask for the defined byte alignment. */ - -#if portBYTE_ALIGNMENT == 8 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0007 ) -#endif - -#if portBYTE_ALIGNMENT == 4 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) -#endif - -#if portBYTE_ALIGNMENT == 2 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) -#endif - -#if portBYTE_ALIGNMENT == 1 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) -#endif - -#ifndef heapBYTE_ALIGNMENT_MASK - #error "Invalid portBYTE_ALIGNMENT definition" -#endif - -/* Allocate the memory for the heap. The struct is used to force byte -alignment without using any non-portable code. */ -static struct xRTOS_HEAP -{ - unsigned portLONG ulDummy; - unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; -} xHeap; - -/* Define the linked list structure. This is used to link free blocks in order -of their size. */ -typedef struct A_BLOCK_LINK -{ - struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */ - size_t xBlockSize; /*<< The size of the free block. */ -} xBlockLink; - - -static const unsigned portSHORT heapSTRUCT_SIZE = ( sizeof( xBlockLink ) + ( sizeof( xBlockLink ) % portBYTE_ALIGNMENT ) ); -#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) ) - -/* Create a couple of list links to mark the start and end of the list. */ -static xBlockLink xStart, xEnd; - -/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */ - -/* - * Insert a block into the list of free blocks - which is ordered by size of - * the block. Small blocks at the start of the list and large blocks at the end - * of the list. - */ -#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \ -{ \ -xBlockLink *pxIterator; \ -size_t xBlockSize; \ - \ - xBlockSize = pxBlockToInsert->xBlockSize; \ - \ - /* Iterate through the list until a block is found that has a larger size */ \ - /* than the block we are inserting. */ \ - for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \ - { \ - /* There is nothing to do here - just iterate to the correct position. */ \ - } \ - \ - /* Update the list to include the block being inserted in the correct */ \ - /* position. */ \ - pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \ - pxIterator->pxNextFreeBlock = pxBlockToInsert; \ -} -/*-----------------------------------------------------------*/ - -#define prvHeapInit() \ -{ \ -xBlockLink *pxFirstFreeBlock; \ - \ - /* xStart is used to hold a pointer to the first item in the list of free */ \ - /* blocks. The void cast is used to prevent compiler warnings. */ \ - xStart.pxNextFreeBlock = ( void * ) xHeap.ucHeap; \ - xStart.xBlockSize = ( size_t ) 0; \ - \ - /* xEnd is used to mark the end of the list of free blocks. */ \ - xEnd.xBlockSize = configTOTAL_HEAP_SIZE; \ - xEnd.pxNextFreeBlock = NULL; \ - \ - /* To start with there is a single free block that is sized to take up the \ - entire heap space. */ \ - pxFirstFreeBlock = ( void * ) xHeap.ucHeap; \ - pxFirstFreeBlock->xBlockSize = configTOTAL_HEAP_SIZE; \ - pxFirstFreeBlock->pxNextFreeBlock = &xEnd; \ -} -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -xBlockLink *pxBlock, *pxPreviousBlock, *pxNewBlockLink; -static portBASE_TYPE xHeapHasBeenInitialised = pdFALSE; -void *pvReturn = NULL; - - vTaskSuspendAll(); - { - /* If this is the first call to malloc then the heap will require - initialisation to setup the list of free blocks. */ - if( xHeapHasBeenInitialised == pdFALSE ) - { - prvHeapInit(); - xHeapHasBeenInitialised = pdTRUE; - } - - /* The wanted size is increased so it can contain a xBlockLink - structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) - { - xWantedSize += heapSTRUCT_SIZE; - - /* Ensure that blocks are always aligned to the required number of bytes. */ - if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) - { - /* Byte alignment required. */ - xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); - } - } - - if( ( xWantedSize > 0 ) && ( xWantedSize < configTOTAL_HEAP_SIZE ) ) - { - /* Blocks are stored in byte order - traverse the list from the start - (smallest) block until one of adequate size is found. */ - pxPreviousBlock = &xStart; - pxBlock = xStart.pxNextFreeBlock; - while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock ) ) - { - pxPreviousBlock = pxBlock; - pxBlock = pxBlock->pxNextFreeBlock; - } - - /* If we found the end marker then a block of adequate size was not found. */ - if( pxBlock != &xEnd ) - { - /* Return the memory space - jumping over the xBlockLink structure - at its start. */ - pvReturn = ( void * ) ( ( ( unsigned portCHAR * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE ); - - /* This block is being returned for use so must be taken our of the - list of free blocks. */ - pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; - - /* If the block is larger than required it can be split into two. */ - if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) - { - /* This block is to be split into two. Create a new block - following the number of bytes requested. The void cast is - used to prevent byte alignment warnings from the compiler. */ - pxNewBlockLink = ( void * ) ( ( ( unsigned portCHAR * ) pxBlock ) + xWantedSize ); - - /* Calculate the sizes of two blocks split from the single - block. */ - pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; - pxBlock->xBlockSize = xWantedSize; - - /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); - } - } - } - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ -unsigned portCHAR *puc = ( unsigned portCHAR * ) pv; -xBlockLink *pxLink; - - if( pv ) - { - /* The memory being freed will have an xBlockLink structure immediately - before it. */ - puc -= heapSTRUCT_SIZE; - - /* This casting is to keep the compiler from issuing warnings. */ - pxLink = ( void * ) puc; - - vTaskSuspendAll(); - { - /* Add this block to the list of free blocks. */ - prvInsertBlockIntoFreeList( ( ( xBlockLink * ) pxLink ) ); - } - xTaskResumeAll(); - } -} -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_3.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_3.c deleted file mode 100644 index c32f883bf..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/portable/MemMang/heap_3.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - - -/* - * Implementation of pvPortMalloc() and vPortFree() that relies on the - * compilers own malloc() and free() implementations. - * - * This file can only be used if the linker is configured to to generate - * a heap memory area. - * - * See heap_2.c and heap_1.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ - -#include - -#include "FreeRTOS.h" -#include "task.h" - -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -void *pvReturn; - - vTaskSuspendAll(); - { - pvReturn = malloc( xWantedSize ); - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ - if( pv ) - { - vTaskSuspendAll(); - { - free( pv ); - } - xTaskResumeAll(); - } -} - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/queue.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/queue.c deleted file mode 100644 index ab0c13ae2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/queue.c +++ /dev/null @@ -1,930 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along - with commercial development and support options. - *************************************************************************** -*/ - -/* -Changes from V1.01 - - + More use of 8bit data types. - + Function name prefixes changed where the data type returned has changed. - -Changed from V2.0.0 - - + Added the queue locking mechanism and make more use of the scheduler - suspension feature to minimise the time interrupts have to be disabled - when accessing a queue. - -Changed from V2.2.0 - - + Explicit use of 'signed' qualifier on portCHAR types added. - -Changes from V3.0.0 - - + API changes as described on the FreeRTOS.org WEB site. - -Changes from V3.2.3 - - + Added the queue functions that can be used from co-routines. - -Changes from V4.0.5 - - + Added a loop within xQueueSend() and xQueueReceive() to prevent the - functions exiting when a block time remains and the function has - not completed. - -Changes from V4.1.2: - - + BUG FIX: Removed the call to prvIsQueueEmpty from within xQueueCRReceive - as it exited with interrupts enabled. Thanks Paul Katz. - -Changes from V4.1.3: - - + Modified xQueueSend() and xQueueReceive() to handle the (very unlikely) - case whereby a task unblocking due to a temporal event can remove/send an - item from/to a queue when a higher priority task is still blocked on the - queue. This modification is a result of the SafeRTOS testing. -*/ - -#include -#include -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/*----------------------------------------------------------- - * PUBLIC LIST API documented in list.h - *----------------------------------------------------------*/ - -/* Constants used with the cRxLock and cTxLock structure members. */ -#define queueUNLOCKED ( ( signed portBASE_TYPE ) -1 ) -#define queueERRONEOUS_UNBLOCK ( -1 ) - -/* - * Definition of the queue used by the scheduler. - * Items are queued by copy, not reference. - */ -typedef struct QueueDefinition -{ - signed portCHAR *pcHead; /*< Points to the beginning of the queue storage area. */ - signed portCHAR *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */ - - signed portCHAR *pcWriteTo; /*< Points to the free next place in the storage area. */ - signed portCHAR *pcReadFrom; /*< Points to the last place that a queued item was read from. */ - - xList xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */ - xList xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */ - - unsigned portBASE_TYPE uxMessagesWaiting;/*< The number of items currently in the queue. */ - unsigned portBASE_TYPE uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */ - unsigned portBASE_TYPE uxItemSize; /*< The size of each items that the queue will hold. */ - - signed portBASE_TYPE xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ - signed portBASE_TYPE xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ -} xQUEUE; -/*-----------------------------------------------------------*/ - -/* - * Inside this file xQueueHandle is a pointer to a xQUEUE structure. - * To keep the definition private the API header file defines it as a - * pointer to void. - */ -typedef xQUEUE * xQueueHandle; - -/* - * Prototypes for public functions are included here so we don't have to - * include the API header file (as it defines xQueueHandle differently). These - * functions are documented in the API header file. - */ -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); -signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue ); -void vQueueDelete( xQueueHandle xQueue ); -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ); -signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - -#if configUSE_CO_ROUTINES == 1 - signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ); - signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ); - signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); -#endif - -/* - * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not - * prevent an ISR from adding or removing items to the queue, but does prevent - * an ISR from removing tasks from the queue event lists. If an ISR finds a - * queue is locked it will instead increment the appropriate queue lock count - * to indicate that a task may require unblocking. When the queue in unlocked - * these lock counts are inspected, and the appropriate action taken. - */ -static void prvUnlockQueue( xQueueHandle pxQueue ); - -/* - * Uses a critical section to determine if there is any data in a queue. - * - * @return pdTRUE if the queue contains no items, otherwise pdFALSE. - */ -static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ); - -/* - * Uses a critical section to determine if there is any space in a queue. - * - * @return pdTRUE if there is no space, otherwise pdFALSE; - */ -static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ); - -/* - * Macro that copies an item into the queue. This is done by copying the item - * byte for byte, not by reference. Updates the queue state to ensure it's - * integrity after the copy. - */ -#define prvCopyQueueData( pxQueue, pvItemToQueue ) \ -{ \ - memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize ); \ - ++( pxQueue->uxMessagesWaiting ); \ - pxQueue->pcWriteTo += pxQueue->uxItemSize; \ - if( pxQueue->pcWriteTo >= pxQueue->pcTail ) \ - { \ - pxQueue->pcWriteTo = pxQueue->pcHead; \ - } \ -} -/*-----------------------------------------------------------*/ - -/* - * Macro to mark a queue as locked. Locking a queue prevents an ISR from - * accessing the queue event lists. - */ -#define prvLockQueue( pxQueue ) \ -{ \ - taskENTER_CRITICAL(); \ - ++( pxQueue->xRxLock ); \ - ++( pxQueue->xTxLock ); \ - taskEXIT_CRITICAL(); \ -} -/*-----------------------------------------------------------*/ - - -/*----------------------------------------------------------- - * PUBLIC QUEUE MANAGEMENT API documented in queue.h - *----------------------------------------------------------*/ - -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ) -{ -xQUEUE *pxNewQueue; -size_t xQueueSizeInBytes; - - /* Allocate the new queue structure. */ - if( uxQueueLength > ( unsigned portBASE_TYPE ) 0 ) - { - pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) ); - if( pxNewQueue != NULL ) - { - /* Create the list of pointers to queue items. The queue is one byte - longer than asked for to make wrap checking easier/faster. */ - xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1; - - pxNewQueue->pcHead = ( signed portCHAR * ) pvPortMalloc( xQueueSizeInBytes ); - if( pxNewQueue->pcHead != NULL ) - { - /* Initialise the queue members as described above where the - queue type is defined. */ - pxNewQueue->pcTail = pxNewQueue->pcHead + ( uxQueueLength * uxItemSize ); - pxNewQueue->uxMessagesWaiting = 0; - pxNewQueue->pcWriteTo = pxNewQueue->pcHead; - pxNewQueue->pcReadFrom = pxNewQueue->pcHead + ( ( uxQueueLength - 1 ) * uxItemSize ); - pxNewQueue->uxLength = uxQueueLength; - pxNewQueue->uxItemSize = uxItemSize; - pxNewQueue->xRxLock = queueUNLOCKED; - pxNewQueue->xTxLock = queueUNLOCKED; - - /* Likewise ensure the event queues start with the correct state. */ - vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) ); - vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) ); - - return pxNewQueue; - } - else - { - vPortFree( pxNewQueue ); - } - } - } - - /* Will only reach here if we could not allocate enough memory or no memory - was required. */ - return NULL; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn = pdPASS; -xTimeOutType xTimeOut; - - /* Make sure other tasks do not access the queue. */ - vTaskSuspendAll(); - - /* Capture the current time status for future reference. */ - vTaskSetTimeOutState( &xTimeOut ); - - /* It is important that this is the only thread/ISR that modifies the - ready or delayed lists until xTaskResumeAll() is called. Places where - the ready/delayed lists are modified include: - - + vTaskDelay() - Nothing can call vTaskDelay as the scheduler is - suspended, vTaskDelay() cannot be called from an ISR. - + vTaskPrioritySet() - Has a critical section around the access. - + vTaskSwitchContext() - This will not get executed while the scheduler - is suspended. - + prvCheckDelayedTasks() - This will not get executed while the - scheduler is suspended. - + xTaskCreate() - Has a critical section around the access. - + vTaskResume() - Has a critical section around the access. - + xTaskResumeAll() - Has a critical section around the access. - + xTaskRemoveFromEventList - Checks to see if the scheduler is - suspended. If so then the TCB being removed from the event is - removed from the event and added to the xPendingReadyList. - */ - - /* Make sure interrupts do not access the queue event list. */ - prvLockQueue( pxQueue ); - - /* It is important that interrupts to not access the event list of the - queue being modified here. Places where the event list is modified - include: - - + xQueueSendFromISR(). This checks the lock on the queue to see if - it has access. If the queue is locked then the Tx lock count is - incremented to signify that a task waiting for data can be made ready - once the queue lock is removed. If the queue is not locked then - a task can be moved from the event list, but will not be removed - from the delayed list or placed in the ready list until the scheduler - is unlocked. - - + xQueueReceiveFromISR(). As per xQueueSendFromISR(). - */ - - /* If the queue is already full we may have to block. */ - do - { - if( prvIsQueueFull( pxQueue ) ) - { - /* The queue is full - do we want to block or just leave without - posting? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* We are going to place ourselves on the xTasksWaitingToSend event - list, and will get woken should the delay expire, or space become - available on the queue. - - As detailed above we do not require mutual exclusion on the event - list as nothing else can modify it or the ready lists while we - have the scheduler suspended and queue locked. - - It is possible that an ISR has removed data from the queue since we - checked if any was available. If this is the case then the data - will have been copied from the queue, and the queue variables - updated, but the event list will not yet have been checked to see if - anything is waiting as the queue is locked. */ - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); - - /* Force a context switch now as we are blocked. We can do - this from within a critical section as the task we are - switching to has its own context. When we return here (i.e. we - unblock) we will leave the critical section as normal. - - It is possible that an ISR has caused an event on an unrelated and - unlocked queue. If this was the case then the event list for that - queue will have been updated but the ready lists left unchanged - - instead the readied task will have been added to the pending ready - list. */ - taskENTER_CRITICAL(); - { - /* We can safely unlock the queue and scheduler here as - interrupts are disabled. We must not yield with anything - locked, but we can yield from within a critical section. - - Tasks that have been placed on the pending ready list cannot - be tasks that are waiting for events on this queue. See - in comment xTaskRemoveFromEventList(). */ - prvUnlockQueue( pxQueue ); - - /* Resuming the scheduler may cause a yield. If so then there - is no point yielding again here. */ - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - - /* We want to check to see if the queue is still full - before leaving the critical section. This is to prevent - this task placing an item into the queue due to an - interrupt making space on the queue between critical - sections (when there might be a higher priority task - blocked on the queue that cannot run yet because the - scheduler gets suspended). */ - if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) - { - /* We unblocked but there is no space in the queue, - we probably timed out. */ - xReturn = errQUEUE_FULL; - } - - /* Before leaving the critical section we have to ensure - exclusive access again. */ - vTaskSuspendAll(); - prvLockQueue( pxQueue ); - } - taskEXIT_CRITICAL(); - } - } - - /* If xReturn is errQUEUE_FULL then we unblocked when the queue - was still full. Don't check it again now as it is possible that - an interrupt has removed an item from the queue since we left the - critical section and we don't want to write to the queue in case - there is a task of higher priority blocked waiting for space to - be available on the queue. If this is the case the higher priority - task will execute when the scheduler is unsupended. */ - if( xReturn != errQUEUE_FULL ) - { - /* When we are here it is possible that we unblocked as space became - available on the queue. It is also possible that an ISR posted to the - queue since we left the critical section, so it may be that again there - is no space. This would only happen if a task and ISR post onto the - same queue. */ - taskENTER_CRITICAL(); - { - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - /* There is room in the queue, copy the data into the queue. */ - prvCopyQueueData( pxQueue, pvItemToQueue ); - xReturn = pdPASS; - - /* Update the TxLock count so prvUnlockQueue knows to check for - tasks waiting for data to become available in the queue. */ - ++( pxQueue->xTxLock ); - } - else - { - xReturn = errQUEUE_FULL; - } - } - taskEXIT_CRITICAL(); - } - - if( xReturn == errQUEUE_FULL ) - { - if( xTicksToWait > 0 ) - { - if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) - { - xReturn = queueERRONEOUS_UNBLOCK; - } - } - } - } - while( xReturn == queueERRONEOUS_UNBLOCK ); - - prvUnlockQueue( pxQueue ); - xTaskResumeAll(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ) -{ - /* Similar to xQueueSend, except we don't block if there is no room in the - queue. Also we don't directly wake a task that was blocked on a queue - read, instead we return a flag to say whether a context switch is required - or not (i.e. has a task with a higher priority than us been woken by this - post). */ - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - prvCopyQueueData( pxQueue, pvItemToQueue ); - - /* If the queue is locked we do not alter the event list. This will - be done when the queue is unlocked later. */ - if( pxQueue->xTxLock == queueUNLOCKED ) - { - /* We only want to wake one task per ISR, so check that a task has - not already been woken. */ - if( !xTaskPreviouslyWoken ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority so record that a - context switch is required. */ - return pdTRUE; - } - } - } - } - else - { - /* Increment the lock count so the task that unlocks the queue - knows that data was posted while it was locked. */ - ++( pxQueue->xTxLock ); - } - } - - return xTaskPreviouslyWoken; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn = pdTRUE; -xTimeOutType xTimeOut; - - /* This function is very similar to xQueueSend(). See comments within - xQueueSend() for a more detailed explanation. - - Make sure other tasks do not access the queue. */ - vTaskSuspendAll(); - - /* Capture the current time status for future reference. */ - vTaskSetTimeOutState( &xTimeOut ); - - /* Make sure interrupts do not access the queue. */ - prvLockQueue( pxQueue ); - - do - { - /* If there are no messages in the queue we may have to block. */ - if( prvIsQueueEmpty( pxQueue ) ) - { - /* There are no messages in the queue, do we want to block or just - leave with nothing? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); - taskENTER_CRITICAL(); - { - prvUnlockQueue( pxQueue ); - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - - if( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ) - { - /* We unblocked but the queue is empty. We probably - timed out. */ - xReturn = errQUEUE_EMPTY; - } - - vTaskSuspendAll(); - prvLockQueue( pxQueue ); - } - taskEXIT_CRITICAL(); - } - } - - if( xReturn != errQUEUE_EMPTY ) - { - taskENTER_CRITICAL(); - { - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - /* Increment the lock count so prvUnlockQueue knows to check for - tasks waiting for space to become available on the queue. */ - ++( pxQueue->xRxLock ); - xReturn = pdPASS; - } - else - { - xReturn = errQUEUE_EMPTY; - } - } - taskEXIT_CRITICAL(); - } - - if( xReturn == errQUEUE_EMPTY ) - { - if( xTicksToWait > 0 ) - { - if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) - { - xReturn = queueERRONEOUS_UNBLOCK; - } - } - } - } while( xReturn == queueERRONEOUS_UNBLOCK ); - - /* We no longer require exclusive access to the queue. */ - prvUnlockQueue( pxQueue ); - xTaskResumeAll(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ) -{ -signed portBASE_TYPE xReturn; - - /* We cannot block from an ISR, so check there is data available. */ - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Copy the data from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - /* If the queue is locked we will not modify the event list. Instead - we update the lock count so the task that unlocks the queue will know - that an ISR has removed data while the queue was locked. */ - if( pxQueue->xRxLock == queueUNLOCKED ) - { - /* We only want to wake one task per ISR, so check that a task has - not already been woken. */ - if( !( *pxTaskWoken ) ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - /* The task waiting has a higher priority than us so - force a context switch. */ - *pxTaskWoken = pdTRUE; - } - } - } - } - else - { - /* Increment the lock count so the task that unlocks the queue - knows that data was removed while it was locked. */ - ++( pxQueue->xRxLock ); - } - - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue ) -{ -unsigned portBASE_TYPE uxReturn; - - taskENTER_CRITICAL(); - uxReturn = pxQueue->uxMessagesWaiting; - taskEXIT_CRITICAL(); - - return uxReturn; -} -/*-----------------------------------------------------------*/ - -void vQueueDelete( xQueueHandle pxQueue ) -{ - vPortFree( pxQueue->pcHead ); - vPortFree( pxQueue ); -} -/*-----------------------------------------------------------*/ - -static void prvUnlockQueue( xQueueHandle pxQueue ) -{ - /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */ - - /* The lock counts contains the number of extra data items placed or - removed from the queue while the queue was locked. When a queue is - locked items can be added or removed, but the event lists cannot be - updated. */ - taskENTER_CRITICAL(); - { - --( pxQueue->xTxLock ); - - /* See if data was added to the queue while it was locked. */ - if( pxQueue->xTxLock > queueUNLOCKED ) - { - pxQueue->xTxLock = queueUNLOCKED; - - /* Data was posted while the queue was locked. Are any tasks - blocked waiting for data to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - /* Tasks that are removed from the event list will get added to - the pending ready list as the scheduler is still suspended. */ - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority so record that a - context switch is required. */ - vTaskMissedYield(); - } - } - } - } - taskEXIT_CRITICAL(); - - /* Do the same for the Rx lock. */ - taskENTER_CRITICAL(); - { - --( pxQueue->xRxLock ); - - if( pxQueue->xRxLock > queueUNLOCKED ) - { - pxQueue->xRxLock = queueUNLOCKED; - - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - vTaskMissedYield(); - } - } - } - } - taskEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - taskENTER_CRITICAL(); - xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ); - taskEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - taskENTER_CRITICAL(); - xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength ); - taskEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* If the queue is already full we may have to block. A critical section - is required to prevent an interrupt removing something from the queue - between the check to see if the queue is full and blocking on the queue. */ - portDISABLE_INTERRUPTS(); - { - if( prvIsQueueFull( pxQueue ) ) - { - /* The queue is full - do we want to block or just leave without - posting? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* As this is called from a coroutine we cannot block directly, but - return indicating that we need to block. */ - vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) ); - portENABLE_INTERRUPTS(); - return errQUEUE_BLOCKED; - } - else - { - portENABLE_INTERRUPTS(); - return errQUEUE_FULL; - } - } - } - portENABLE_INTERRUPTS(); - - portNOP(); - - portDISABLE_INTERRUPTS(); - { - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - /* There is room in the queue, copy the data into the queue. */ - prvCopyQueueData( pxQueue, pvItemToQueue ); - xReturn = pdPASS; - - /* Were any co-routines waiting for data to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - /* In this instance the co-routine could be placed directly - into the ready list as we are within a critical section. - Instead the same pending ready list mechansim is used as if - the event were caused from within an interrupt. */ - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The co-routine waiting has a higher priority so record - that a yield might be appropriate. */ - xReturn = errQUEUE_YIELD; - } - } - } - else - { - xReturn = errQUEUE_FULL; - } - } - portENABLE_INTERRUPTS(); - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* If the queue is already empty we may have to block. A critical section - is required to prevent an interrupt adding something to the queue - between the check to see if the queue is empty and blocking on the queue. */ - portDISABLE_INTERRUPTS(); - { - if( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ) - { - /* There are no messages in the queue, do we want to block or just - leave with nothing? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* As this is a co-routine we cannot block directly, but return - indicating that we need to block. */ - vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) ); - portENABLE_INTERRUPTS(); - return errQUEUE_BLOCKED; - } - else - { - portENABLE_INTERRUPTS(); - return errQUEUE_FULL; - } - } - } - portENABLE_INTERRUPTS(); - - portNOP(); - - portDISABLE_INTERRUPTS(); - { - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Data is available from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - xReturn = pdPASS; - - /* Were any co-routines waiting for space to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - /* In this instance the co-routine could be placed directly - into the ready list as we are within a critical section. - Instead the same pending ready list mechansim is used as if - the event were caused from within an interrupt. */ - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - xReturn = errQUEUE_YIELD; - } - } - } - else - { - xReturn = pdFAIL; - } - } - portENABLE_INTERRUPTS(); - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - - - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ) -{ - /* Cannot block within an ISR so if there is no space on the queue then - exit without doing anything. */ - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - prvCopyQueueData( pxQueue, pvItemToQueue ); - - /* We only want to wake one co-routine per ISR, so check that a - co-routine has not already been woken. */ - if( !xCoRoutinePreviouslyWoken ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - return pdTRUE; - } - } - } - } - - return xCoRoutinePreviouslyWoken; -} -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxCoRoutineWoken ) -{ -signed portBASE_TYPE xReturn; - - /* We cannot block from an ISR, so check there is data available. If - not then just leave without doing anything. */ - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Copy the data from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - if( !( *pxCoRoutineWoken ) ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - *pxCoRoutineWoken = pdTRUE; - } - } - } - - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/tasks.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/tasks.c deleted file mode 100644 index 3f2f0672a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOS/tasks.c +++ /dev/null @@ -1,1936 +0,0 @@ -/* - FreeRTOS.org V4.4.0 - Copyright (C) 2003-2007 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - - Also see http://www.SafeRTOS.com for an IEC 61508 compliant version, along - with development and support options. - *************************************************************************** -*/ - -/* -Changes from V1.00: - - + Call to portRESTORE_CONTEXT has been removed. The first context - switch is now performed within sPortStartScheduler(). - -Changes from V1.01: - - + More use of 8bit data types. - + Function name prefixes changed where the data type returned has changed. - + configUSE_TRACE_FACILITY is no longer defined by default. - -Changes from V1.2.0 - - + Introduced ucTopReadyPriority. This tracks the highest priority ready - queue that contains a valid TCB and thus makes the context switch - slightly faster. - - + prvAddTaskToReadyQueue() has been made a macro. - -Changes from V1.2.6 - - + Added conditional compilation directives. - + Extended API. - + Rearranged function order. - + Creating a task now causes a context switch if the task being created - has a higher priority than the calling task - assuming the kernel is - running. - + vTaskDelete() now only causes a context switch if the calling task is - the task being deleted. - -Changes from V2.0.0 - - + Allow the type of the tick count to be 16 or 32 bits. - + Introduce xPendingReadyList feature to allow the time interrupts have to - be disabled to be minimised. - + Remove the #if( INCLUDE_vTaskSuspendAll ) statements. vTaskSuspendAll() - is now always included as it is used by the scheduler itself. - -Changes from V2.1.0 - - + Bug fix - pxCurrentTCB is now initialised before the call to - prvInitializeTaskLists(). Previously pxCurrentTCB could be accessed - while null. - -Changed from V2.1.1 - - + Change to where lStackSize is declared within sTaskCreate() to prevent - compiler warnings with 8051 port. - -Changes from V2.2.0 - - + Explicit use of 'signed' qualifier on portCHAR types added. - + Changed odd calculation of initial pxTopOfStack value when - portSTACK_GROWTH < 0. - + Removed pcVersionNumber definition. - -Changes from V2.5.3 - - + cTaskResumeAll() modified to ensure it can be called prior to the task - lists being initialised. - -Changes from V2.5.5 - - + Added API function vTaskDelayUntil(). - + Added INCLUDE_vTaskDelay conditional compilation. - -Changes from V2.6.0 - - + Updated the vWriteTraceToBuffer macro to always be 4 byte aligned so it - can be used on ARM architectures. - + tskMAX_TASK_NAME_LEN definition replaced with the port specific - configMAX_TASK_NAME_LEN definition. - + Removed the call to strcpy when copying across the task name into the - TCB. - + Added ucTasksDeleted variable to prevent vTaskSuspendAll() being called - too often in the idle task. - -Changes between V3.0.0 and V2.6.1 - - + When resuming the scheduler a yield is performed if either a tick has - been missed, or a task is moved from the pending ready list into a ready - list. Previously a yield was not performed on this second condition. - + Introduced the type portBASE_TYPE. This necessitates several API - changes. - + Removed the sUsingPreemption variable. The constant defined in - portmacro.h is now used directly. - + The idle task can now include an optional hook function - and no longer - completes its time slice if other tasks with equal priority to it are - ready to run. - + See the FreeRTOS.org documentation for more information on V2.x.x to - V3.x.x modifications. - -Changes from V3.1.1 - - + Modified vTaskPrioritySet() and vTaskResume() to allow these functions to - be called while the scheduler is suspended. - + Corrected the task ordering within event lists. - -Changes from V3.2.0 - - + Added function xTaskGetCurrentTaskHandle(). - -Changes from V3.2.4 - - + Changed the volatile declarations on some variables to reflect the - changes to the list definitions. - + Changed the order of the TCB definition so there is commonality between - the task control block and a co-routine control block. - + Allow the scheduler to be started even if no tasks other than the idle - task has been created. This allows co-routines to run even when no tasks - have been created. - + The need for a context switch is now signalled if a task woken by an - event has a priority greater or equal to the currently running task. - Previously this was only greater than. - -Changes from V4.0.0 - - + Added the xMissedYield handling. - -Changes from V4.0.1 - - + The function vTaskList() now suspends the scheduler rather than disabling - interrupts during the creation of the task list. - + Allow a task to delete itself by passing in its own handle. Previously - this could only be done by passing in NULL. - + The tick hook function is now called only within a tick isr. Previously - it was also called when the tick function was called during the scheduler - unlocking process. - -Changes from V4.0.3 - - + Extra checks have been placed in vTaskPrioritySet() to avoid unnecessary - yields. - -Changed from V4.0.4 - - + Bug fix: The 'value' of the event list item is updated when the priority - of a task is changed. Previously only the priority of the TCB itself was - changed. - + When resuming a task a check is first made to see if the task is actually - suspended. - + vTaskPrioritySet() and vTaskResume() no longer use the event list item. - This has not been necessary since V4.0.1 when the xMissedYield handling - was added. - + Implement xTaskResumeFromISR(). - -Changes from V4.0.5 - - + Added utility functions and xOverflowCount variable to facilitate the - queue.c changes. - -Changes from V4.1.2 - - + Tasks that block on events with a timeout of portMAX_DELAY are now - blocked indefinitely if configINCLUDE_vTaskSuspend is defined. - Previously portMAX_DELAY was just the longest block time possible. - -Changes from V4.1.3 - - + Very small change made to xTaskCheckForTimeout() as a result of the - SafeRTOS testing. This corrects the case where the function can return an - invalid value - but only in an extremely unlikely scenario. - -Changes since V4.3.1: - - + Added xTaskGetSchedulerState() function. - + Added prvIsTaskSuspended() to take into account the Occurrence of - vTaskResume() or vTaskResumeFromISR() being called passing in the - handle of a task that appears in the Suspended list only because it - is blocked on an event without a timeout being specified. - + Updated xTaskCheckForTimeout() to take into account that tasks blocked - using the Suspended list should never time out. -*/ - -#include -#include -#include - -#include "FreeRTOS.h" -#include "task.h" - -/* - * Macro to define the amount of stack available to the idle task. - */ -#define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE - - -/* - * Default a definitions for backwards compatibility with old - * portmacro.h files. - */ -#ifndef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 16 -#endif - -#ifndef INCLUDE_xTaskGetCurrentTaskHandle - #define INCLUDE_xTaskGetCurrentTaskHandle 0 -#endif - -#ifndef configIDLE_SHOULD_YIELD - #define configIDLE_SHOULD_YIELD 1 -#endif - -#if configMAX_TASK_NAME_LEN < 1 - #undef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 1 -#endif - -#ifndef INCLUDE_xTaskResumeFromISR - #define INCLUDE_xTaskResumeFromISR 1 -#endif - -#ifndef INCLUDE_xTaskGetSchedulerState - #define INCLUDE_xTaskGetSchedulerState 0 -#endif - -/* - * Task control block. A task control block (TCB) is allocated to each task, - * and stores the context of the task. - */ -typedef struct tskTaskControlBlock -{ - volatile portSTACK_TYPE *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE STRUCT. */ - xListItem xGenericListItem; /*< List item used to place the TCB in ready and blocked queues. */ - xListItem xEventListItem; /*< List item used to place the TCB in event lists. */ - unsigned portBASE_TYPE uxPriority; /*< The priority of the task where 0 is the lowest priority. */ - portSTACK_TYPE *pxStack; /*< Points to the start of the stack. */ - unsigned portBASE_TYPE uxTCBNumber; /*< This is used for tracing the scheduler and making debugging easier only. */ - signed portCHAR pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */ - unsigned portSHORT usStackDepth; /*< Total depth of the stack (when empty). This is defined as the number of variables the stack can hold, not the number of bytes. */ -} tskTCB; - -/*lint -e956 */ - -tskTCB * volatile pxCurrentTCB = NULL; - -/* Lists for ready and blocked tasks. --------------------*/ - -static xList pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */ -static xList xDelayedTaskList1; /*< Delayed tasks. */ -static xList xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */ -static xList * volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */ -static xList * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */ -static xList xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready queue when the scheduler is resumed. */ - -#if ( INCLUDE_vTaskDelete == 1 ) - - static volatile xList xTasksWaitingTermination; /*< Tasks that have been deleted - but the their memory not yet freed. */ - static volatile unsigned portBASE_TYPE uxTasksDeleted = ( unsigned portBASE_TYPE ) 0; - -#endif - -#if ( INCLUDE_vTaskSuspend == 1 ) - - static xList xSuspendedTaskList; /*< Tasks that are currently suspended. */ - -#endif - -/* File private variables. --------------------------------*/ -static volatile unsigned portBASE_TYPE uxCurrentNumberOfTasks = ( unsigned portBASE_TYPE ) 0; -static volatile portTickType xTickCount = ( portTickType ) 0; -static unsigned portBASE_TYPE uxTopUsedPriority = tskIDLE_PRIORITY; -static volatile unsigned portBASE_TYPE uxTopReadyPriority = tskIDLE_PRIORITY; -static volatile signed portBASE_TYPE xSchedulerRunning = pdFALSE; -static volatile unsigned portBASE_TYPE uxSchedulerSuspended = ( unsigned portBASE_TYPE ) pdFALSE; -static volatile unsigned portBASE_TYPE uxMissedTicks = ( unsigned portBASE_TYPE ) 0; -static volatile portBASE_TYPE xMissedYield = ( portBASE_TYPE ) pdFALSE; -static volatile portBASE_TYPE xNumOfOverflows = ( portBASE_TYPE ) 0; -/* Debugging and trace facilities private variables and macros. ------------*/ - -/* - * The value used to fill the stack of a task when the task is created. This - * is used purely for checking the high water mark for tasks. - */ -#define tskSTACK_FILL_BYTE ( 0xa5 ) - -/* - * Macros used by vListTask to indicate which state a task is in. - */ -#define tskBLOCKED_CHAR ( ( signed portCHAR ) 'B' ) -#define tskREADY_CHAR ( ( signed portCHAR ) 'R' ) -#define tskDELETED_CHAR ( ( signed portCHAR ) 'D' ) -#define tskSUSPENDED_CHAR ( ( signed portCHAR ) 'S' ) - -/* - * Macros and private variables used by the trace facility. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - #define tskSIZE_OF_EACH_TRACE_LINE ( ( unsigned portLONG ) ( sizeof( unsigned portLONG ) + sizeof( unsigned portLONG ) ) ) - static volatile signed portCHAR * volatile pcTraceBuffer; - static signed portCHAR *pcTraceBufferStart; - static signed portCHAR *pcTraceBufferEnd; - static signed portBASE_TYPE xTracing = pdFALSE; - -#endif - -/* - * Macro that writes a trace of scheduler activity to a buffer. This trace - * shows which task is running when and is very useful as a debugging tool. - * As this macro is called each context switch it is a good idea to undefine - * it if not using the facility. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - #define vWriteTraceToBuffer() \ - { \ - if( xTracing ) \ - { \ - static unsigned portBASE_TYPE uxPreviousTask = 255; \ - \ - if( uxPreviousTask != pxCurrentTCB->uxTCBNumber ) \ - { \ - if( ( pcTraceBuffer + tskSIZE_OF_EACH_TRACE_LINE ) < pcTraceBufferEnd ) \ - { \ - uxPreviousTask = pxCurrentTCB->uxTCBNumber; \ - *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) xTickCount; \ - pcTraceBuffer += sizeof( unsigned portLONG ); \ - *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) uxPreviousTask; \ - pcTraceBuffer += sizeof( unsigned portLONG ); \ - } \ - else \ - { \ - xTracing = pdFALSE; \ - } \ - } \ - } \ - } - -#else - - #define vWriteTraceToBuffer() - -#endif - - -/* - * Place the task represented by pxTCB into the appropriate ready queue for - * the task. It is inserted at the end of the list. One quirk of this is - * that if the task being inserted is at the same priority as the currently - * executing task, then it will only be rescheduled after the currently - * executing task has been rescheduled. - */ -#define prvAddTaskToReadyQueue( pxTCB ) \ -{ \ - if( pxTCB->uxPriority > uxTopReadyPriority ) \ - { \ - uxTopReadyPriority = pxTCB->uxPriority; \ - } \ - vListInsertEnd( ( xList * ) &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ); \ -} - -/* - * Macro that looks at the list of tasks that are currently delayed to see if - * any require waking. - * - * Tasks are stored in the queue in the order of their wake time - meaning - * once one tasks has been found whose timer has not expired we need not look - * any further down the list. - */ -#define prvCheckDelayedTasks() \ -{ \ -register tskTCB *pxTCB; \ - \ - while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ) ) != NULL ) \ - { \ - if( xTickCount < listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) ) ) \ - { \ - break; \ - } \ - vListRemove( &( pxTCB->xGenericListItem ) ); \ - /* Is the task waiting on an event also? */ \ - if( pxTCB->xEventListItem.pvContainer ) \ - { \ - vListRemove( &( pxTCB->xEventListItem ) ); \ - } \ - prvAddTaskToReadyQueue( pxTCB ); \ - } \ -} - -/* - * Several functions take an xTaskHandle parameter that can optionally be NULL, - * where NULL is used to indicate that the handle of the currently executing - * task should be used in place of the parameter. This macro simply checks to - * see if the parameter is NULL and returns a pointer to the appropriate TCB. - */ -#define prvGetTCBFromHandle( pxHandle ) ( ( pxHandle == NULL ) ? ( tskTCB * ) pxCurrentTCB : ( tskTCB * ) pxHandle ) - - -/* File private functions. --------------------------------*/ - -/* - * Utility to ready a TCB for a given task. Mainly just copies the parameters - * into the TCB structure. - */ -static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ); - -/* - * Utility to ready all the lists used by the scheduler. This is called - * automatically upon the creation of the first task. - */ -static void prvInitialiseTaskLists( void ); - -/* - * The idle task, which as all tasks is implemented as a never ending loop. - * The idle task is automatically created and added to the ready lists upon - * creation of the first user task. - * - * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific - * language extensions. The equivalent prototype for this function is: - * - * void prvIdleTask( void *pvParameters ); - * - */ -static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ); - -/* - * Utility to free all memory allocated by the scheduler to hold a TCB, - * including the stack pointed to by the TCB. - * - * This does not free memory allocated by the task itself (i.e. memory - * allocated by calls to pvPortMalloc from within the tasks application code). - */ -#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) - static void prvDeleteTCB( tskTCB *pxTCB ); -#endif - -/* - * Used only by the idle task. This checks to see if anything has been placed - * in the list of tasks waiting to be deleted. If so the task is cleaned up - * and its TCB deleted. - */ -static void prvCheckTasksWaitingTermination( void ); - -/* - * Allocates memory from the heap for a TCB and associated stack. Checks the - * allocation was successful. - */ -static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ); - -/* - * Called from vTaskList. vListTasks details all the tasks currently under - * control of the scheduler. The tasks may be in one of a number of lists. - * prvListTaskWithinSingleList accepts a list and details the tasks from - * within just that list. - * - * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM - * NORMAL APPLICATION CODE. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ); - -#endif - -/* - * When a task is created, the stack of the task is filled with a known value. - * This function determines the 'high water mark' of the task stack by - * determining how much of the stack remains at the original preset value. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte ); - -#endif - -/* - * Checks that a task being resumed (unsuspended) is actually in the Suspended - * state. - */ -#if ( INCLUDE_vTaskSuspend == 1 ) - - static portBASE_TYPE prvIsTaskSuspended( const tskTCB * const pxTCB ); - -#endif - -/*lint +e956 */ - - - - - -/*----------------------------------------------------------- - * TASK CREATION API documented in task.h - *----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask ) -{ -signed portBASE_TYPE xReturn; -tskTCB * pxNewTCB; -static unsigned portBASE_TYPE uxTaskNumber = 0; /*lint !e956 Static is deliberate - this is guarded before use. */ - - /* Allocate the memory required by the TCB and stack for the new task. - checking that the allocation was successful. */ - pxNewTCB = prvAllocateTCBAndStack( usStackDepth ); - - if( pxNewTCB != NULL ) - { - portSTACK_TYPE *pxTopOfStack; - - /* Setup the newly allocated TCB with the initial state of the task. */ - prvInitialiseTCBVariables( pxNewTCB, usStackDepth, pcName, uxPriority ); - - /* Calculate the top of stack address. This depends on whether the - stack grows from high memory to low (as per the 80x86) or visa versa. - portSTACK_GROWTH is used to make the result positive or negative as - required by the port. */ - #if portSTACK_GROWTH < 0 - { - pxTopOfStack = pxNewTCB->pxStack + ( pxNewTCB->usStackDepth - 1 ); - } - #else - { - pxTopOfStack = pxNewTCB->pxStack; - } - #endif - - /* Initialize the TCB stack to look as if the task was already running, - but had been interrupted by the scheduler. The return address is set - to the start of the task function. Once the stack has been initialised - the top of stack variable is updated. */ - pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pvTaskCode, pvParameters ); - - /* We are going to manipulate the task queues to add this task to a - ready list, so must make sure no interrupts occur. */ - portENTER_CRITICAL(); - { - uxCurrentNumberOfTasks++; - if( uxCurrentNumberOfTasks == ( unsigned portBASE_TYPE ) 1 ) - { - /* As this is the first task it must also be the current task. */ - pxCurrentTCB = pxNewTCB; - - /* This is the first task to be created so do the preliminary - initialisation required. We will not recover if this call - fails, but we will report the failure. */ - prvInitialiseTaskLists(); - } - else - { - /* If the scheduler is not already running, make this task the - current task if it is the highest priority task to be created - so far. */ - if( xSchedulerRunning == pdFALSE ) - { - if( pxCurrentTCB->uxPriority <= uxPriority ) - { - pxCurrentTCB = pxNewTCB; - } - } - } - - /* Remember the top priority to make context switching faster. Use - the priority in pxNewTCB as this has been capped to a valid value. */ - if( pxNewTCB->uxPriority > uxTopUsedPriority ) - { - uxTopUsedPriority = pxNewTCB->uxPriority; - } - - /* Add a counter into the TCB for tracing only. */ - pxNewTCB->uxTCBNumber = uxTaskNumber; - uxTaskNumber++; - - prvAddTaskToReadyQueue( pxNewTCB ); - - xReturn = pdPASS; - } - portEXIT_CRITICAL(); - } - else - { - xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - } - - if( xReturn == pdPASS ) - { - if( ( void * ) pxCreatedTask != NULL ) - { - /* Pass the TCB out - in an anonymous way. The calling function/ - task can use this as a handle to delete the task later if - required.*/ - *pxCreatedTask = ( xTaskHandle ) pxNewTCB; - } - - if( xSchedulerRunning != pdFALSE ) - { - /* If the created task is of a higher priority than the current task - then it should run now. */ - if( pxCurrentTCB->uxPriority < uxPriority ) - { - taskYIELD(); - } - } - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelete == 1 ) - - void vTaskDelete( xTaskHandle pxTaskToDelete ) - { - tskTCB *pxTCB; - - taskENTER_CRITICAL(); - { - /* Ensure a yield is performed if the current task is being - deleted. */ - if( pxTaskToDelete == pxCurrentTCB ) - { - pxTaskToDelete = NULL; - } - - /* If null is passed in here then we are deleting ourselves. */ - pxTCB = prvGetTCBFromHandle( pxTaskToDelete ); - - /* Remove task from the ready list and place in the termination list. - This will stop the task from be scheduled. The idle task will check - the termination list and free up any memory allocated by the - scheduler for the TCB and stack. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Is the task waiting on an event also? */ - if( pxTCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - } - - vListInsertEnd( ( xList * ) &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) ); - - /* Increment the ucTasksDeleted variable so the idle task knows - there is a task that has been deleted and that it should therefore - check the xTasksWaitingTermination list. */ - ++uxTasksDeleted; - } - taskEXIT_CRITICAL(); - - /* Force a reschedule if we have just deleted the current task. */ - if( xSchedulerRunning != pdFALSE ) - { - if( ( void * ) pxTaskToDelete == NULL ) - { - taskYIELD(); - } - } - } - -#endif - - - - - - -/*----------------------------------------------------------- - * TASK CONTROL API documented in task.h - *----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelayUntil == 1 ) - - void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement ) - { - portTickType xTimeToWake; - portBASE_TYPE xAlreadyYielded, xShouldDelay = pdFALSE; - - vTaskSuspendAll(); - { - /* Generate the tick time at which the task wants to wake. */ - xTimeToWake = *pxPreviousWakeTime + xTimeIncrement; - - if( xTickCount < *pxPreviousWakeTime ) - { - /* The tick count has overflowed since this function was - lasted called. In this case the only time we should ever - actually delay is if the wake time has also overflowed, - and the wake time is greater than the tick time. When this - is the case it is as if neither time had overflowed. */ - if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xTickCount ) ) - { - xShouldDelay = pdTRUE; - } - } - else - { - /* The tick time has not overflowed. In this case we will - delay if either the wake time has overflowed, and/or the - tick time is less than the wake time. */ - if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xTickCount ) ) - { - xShouldDelay = pdTRUE; - } - } - - /* Update the wake time ready for the next call. */ - *pxPreviousWakeTime = xTimeToWake; - - if( xShouldDelay ) - { - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - } - xAlreadyYielded = xTaskResumeAll(); - - /* Force a reschedule if xTaskResumeAll has not already done so, we may - have put ourselves to sleep. */ - if( !xAlreadyYielded ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelay == 1 ) - - void vTaskDelay( portTickType xTicksToDelay ) - { - portTickType xTimeToWake; - signed portBASE_TYPE xAlreadyYielded = pdFALSE; - - /* A delay time of zero just forces a reschedule. */ - if( xTicksToDelay > ( portTickType ) 0 ) - { - vTaskSuspendAll(); - { - /* A task that is removed from the event list while the - scheduler is suspended will not get placed in the ready - list or removed from the blocked list until the scheduler - is resumed. - - This task cannot be in an event list as it is the currently - executing task. */ - - /* Calculate the time to wake - this may overflow but this is - not a problem. */ - xTimeToWake = xTickCount + xTicksToDelay; - - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - xAlreadyYielded = xTaskResumeAll(); - } - - /* Force a reschedule if xTaskResumeAll has not already done so, we may - have put ourselves to sleep. */ - if( !xAlreadyYielded ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_uxTaskPriorityGet == 1 ) - - unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ) - { - tskTCB *pxTCB; - unsigned portBASE_TYPE uxReturn; - - taskENTER_CRITICAL(); - { - /* If null is passed in here then we are changing the - priority of the calling function. */ - pxTCB = prvGetTCBFromHandle( pxTask ); - uxReturn = pxTCB->uxPriority; - } - taskEXIT_CRITICAL(); - - return uxReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskPrioritySet == 1 ) - - void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ) - { - tskTCB *pxTCB; - unsigned portBASE_TYPE uxCurrentPriority, xYieldRequired = pdFALSE; - - /* Ensure the new priority is valid. */ - if( uxNewPriority >= configMAX_PRIORITIES ) - { - uxNewPriority = configMAX_PRIORITIES - 1; - } - - taskENTER_CRITICAL(); - { - /* If null is passed in here then we are changing the - priority of the calling function. */ - pxTCB = prvGetTCBFromHandle( pxTask ); - uxCurrentPriority = pxTCB->uxPriority; - - if( uxCurrentPriority != uxNewPriority ) - { - /* The priority change may have readied a task of higher - priority than the calling task. */ - if( uxNewPriority > pxCurrentTCB->uxPriority ) - { - if( pxTask != NULL ) - { - /* The priority of another task is being raised. If we - were raising the priority of the currently running task - there would be no need to switch as it must have already - been the highest priority task. */ - xYieldRequired = pdTRUE; - } - } - else if( pxTask == NULL ) - { - /* Setting our own priority down means there may now be another - task of higher priority that is ready to execute. */ - xYieldRequired = pdTRUE; - } - - pxTCB->uxPriority = uxNewPriority; - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxNewPriority ); - - /* If the task is in the blocked or suspended list we need do - nothing more than change it's priority variable. However, if - the task is in a ready list it needs to be removed and placed - in the queue appropriate to its new priority. */ - if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxCurrentPriority ] ), &( pxTCB->xGenericListItem ) ) ) - { - /* The task is currently in its ready list - remove before adding - it to it's new ready list. As we are in a critical section we - can do this even if the scheduler is suspended. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - } - - if( xYieldRequired == pdTRUE ) - { - taskYIELD(); - } - } - } - taskEXIT_CRITICAL(); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - void vTaskSuspend( xTaskHandle pxTaskToSuspend ) - { - tskTCB *pxTCB; - - taskENTER_CRITICAL(); - { - /* Ensure a yield is performed if the current task is being - suspended. */ - if( pxTaskToSuspend == pxCurrentTCB ) - { - pxTaskToSuspend = NULL; - } - - /* If null is passed in here then we are suspending ourselves. */ - pxTCB = prvGetTCBFromHandle( pxTaskToSuspend ); - - /* Remove task from the ready/delayed list and place in the suspended list. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Is the task waiting on an event also? */ - if( pxTCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - } - - vListInsertEnd( ( xList * ) &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ); - } - taskEXIT_CRITICAL(); - - /* We may have just suspended the current task. */ - if( ( void * ) pxTaskToSuspend == NULL ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - static portBASE_TYPE prvIsTaskSuspended( const tskTCB * const pxTCB ) - { - portBASE_TYPE xReturn = pdFALSE; - - /* Is the task we are attempting to resume actually in the - suspended list? */ - if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE ) - { - /* Has the task already been resumed from within an ISR? */ - if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdTRUE ) - { - /* Is it in the suspended list because it is in the - Suspended state? It is possible to be in the suspended - list because it is blocked on a task with no timeout - specified. */ - if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) == pdTRUE ) - { - xReturn = pdTRUE; - } - } - } - - return xReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - void vTaskResume( xTaskHandle pxTaskToResume ) - { - tskTCB *pxTCB; - - /* Remove the task from whichever list it is currently in, and place - it in the ready list. */ - pxTCB = ( tskTCB * ) pxTaskToResume; - - /* The parameter cannot be NULL as it is impossible to resume the - currently executing task. */ - if( pxTCB != NULL ) - { - taskENTER_CRITICAL(); - { - if( prvIsTaskSuspended( pxTCB ) == pdTRUE ) - { - /* As we are in a critical section we can access the ready - lists even if the scheduler is suspended. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - - /* We may have just resumed a higher priority task. */ - if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - /* This yield may not cause the task just resumed to run, but - will leave the lists in the correct state for the next yield. */ - taskYIELD(); - } - } - } - taskEXIT_CRITICAL(); - } - } - -#endif - -/*-----------------------------------------------------------*/ - -#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ) - { - portBASE_TYPE xYieldRequired = pdFALSE; - tskTCB *pxTCB; - - pxTCB = ( tskTCB * ) pxTaskToResume; - - if( prvIsTaskSuspended( pxTCB ) == pdTRUE ) - { - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - xYieldRequired = ( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ); - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - } - else - { - /* We cannot access the delayed or ready lists, so will hold this - task pending until the scheduler is resumed, at which point a - yield will be preformed if necessary. */ - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); - } - } - - return xYieldRequired; - } - -#endif - - - - -/*----------------------------------------------------------- - * PUBLIC SCHEDULER CONTROL documented in task.h - *----------------------------------------------------------*/ - - -void vTaskStartScheduler( void ) -{ -portBASE_TYPE xReturn; - - /* Add the idle task at the lowest priority. */ - xReturn = xTaskCreate( prvIdleTask, ( signed portCHAR * ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); - - if( xReturn == pdPASS ) - { - /* Interrupts are turned off here, to ensure a tick does not occur - before or during the call to xPortStartScheduler(). The stacks of - the created tasks contain a status word with interrupts switched on - so interrupts will automatically get re-enabled when the first task - starts to run. - - STEPPING THROUGH HERE USING A DEBUGGER CAN CAUSE BIG PROBLEMS IF THE - DEBUGGER ALLOWS INTERRUPTS TO BE PROCESSED. */ - portDISABLE_INTERRUPTS(); - - xSchedulerRunning = pdTRUE; - xTickCount = ( portTickType ) 0; - - /* Setting up the timer tick is hardware specific and thus in the - portable interface. */ - if( xPortStartScheduler() ) - { - /* Should not reach here as if the scheduler is running the - function will not return. */ - } - else - { - /* Should only reach here if a task calls xTaskEndScheduler(). */ - } - } -} -/*-----------------------------------------------------------*/ - -void vTaskEndScheduler( void ) -{ - /* Stop the scheduler interrupts and call the portable scheduler end - routine so the original ISRs can be restored if necessary. The port - layer must ensure interrupts enable bit is left in the correct state. */ - portDISABLE_INTERRUPTS(); - xSchedulerRunning = pdFALSE; - vPortEndScheduler(); -} -/*----------------------------------------------------------*/ - -void vTaskSuspendAll( void ) -{ - portENTER_CRITICAL(); - ++uxSchedulerSuspended; - portEXIT_CRITICAL(); -} -/*----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskResumeAll( void ) -{ -register tskTCB *pxTCB; -signed portBASE_TYPE xAlreadyYielded = pdFALSE; - - /* It is possible that an ISR caused a task to be removed from an event - list while the scheduler was suspended. If this was the case then the - removed task will have been added to the xPendingReadyList. Once the - scheduler has been resumed it is safe to move all the pending ready - tasks from this list into their appropriate ready list. */ - portENTER_CRITICAL(); - { - --uxSchedulerSuspended; - - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - if( uxCurrentNumberOfTasks > ( unsigned portBASE_TYPE ) 0 ) - { - portBASE_TYPE xYieldRequired = pdFALSE; - - /* Move any readied tasks from the pending list into the - appropriate ready list. */ - while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xPendingReadyList ) ) ) != NULL ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - - /* If we have moved a task that has a priority higher than - the current task then we should yield. */ - if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - xYieldRequired = pdTRUE; - } - } - - /* If any ticks occurred while the scheduler was suspended then - they should be processed now. This ensures the tick count does not - slip, and that any delayed tasks are resumed at the correct time. */ - if( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) - { - while( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) - { - vTaskIncrementTick(); - --uxMissedTicks; - } - - /* As we have processed some ticks it is appropriate to yield - to ensure the highest priority task that is ready to run is - the task actually running. */ - xYieldRequired = pdTRUE; - } - - if( ( xYieldRequired == pdTRUE ) || ( xMissedYield == pdTRUE ) ) - { - xAlreadyYielded = pdTRUE; - xMissedYield = pdFALSE; - taskYIELD(); - } - } - } - } - portEXIT_CRITICAL(); - - return xAlreadyYielded; -} - - - - - - -/*----------------------------------------------------------- - * PUBLIC TASK UTILITIES documented in task.h - *----------------------------------------------------------*/ - - - -portTickType xTaskGetTickCount( void ) -{ -portTickType xTicks; - - /* Critical section required if running on a 16 bit processor. */ - taskENTER_CRITICAL(); - { - xTicks = xTickCount; - } - taskEXIT_CRITICAL(); - - return xTicks; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ) -{ -unsigned portBASE_TYPE uxNumberOfTasks; - - taskENTER_CRITICAL(); - uxNumberOfTasks = uxCurrentNumberOfTasks; - taskEXIT_CRITICAL(); - - return uxNumberOfTasks; -} -/*-----------------------------------------------------------*/ - -#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_vTaskDelete == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - void vTaskList( signed portCHAR *pcWriteBuffer ) - { - unsigned portBASE_TYPE uxQueue; - - /* This is a VERY costly function that should be used for debug only. - It leaves interrupts disabled for a LONG time. */ - - vTaskSuspendAll(); - { - /* Run through all the lists that could potentially contain a TCB and - report the task name, state and stack high water mark. */ - - pcWriteBuffer[ 0 ] = ( signed portCHAR ) 0x00; - strcat( ( portCHAR * ) pcWriteBuffer, ( const portCHAR * ) "\r\n" ); - - uxQueue = uxTopUsedPriority + 1; - - do - { - uxQueue--; - - if( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), tskREADY_CHAR ); - } - }while( uxQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); - - if( !listLIST_IS_EMPTY( pxDelayedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, tskBLOCKED_CHAR ); - } - - if( !listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, tskBLOCKED_CHAR ); - } - - if( !listLIST_IS_EMPTY( &xTasksWaitingTermination ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xTasksWaitingTermination, tskDELETED_CHAR ); - } - - if( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xSuspendedTaskList, tskSUSPENDED_CHAR ); - } - } - xTaskResumeAll(); - } - -#endif -/*----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ) - { - portENTER_CRITICAL(); - { - pcTraceBuffer = ( volatile signed portCHAR * volatile )pcBuffer; - pcTraceBufferStart = pcBuffer; - pcTraceBufferEnd = pcBuffer + ( ulBufferSize - tskSIZE_OF_EACH_TRACE_LINE ); - xTracing = pdTRUE; - } - portEXIT_CRITICAL(); - } - -#endif -/*----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - unsigned portLONG ulTaskEndTrace( void ) - { - unsigned portLONG ulBufferLength; - - portENTER_CRITICAL(); - xTracing = pdFALSE; - portEXIT_CRITICAL(); - - ulBufferLength = ( unsigned portLONG ) ( pcTraceBuffer - pcTraceBufferStart ); - - return ulBufferLength; - } - -#endif - - - -/*----------------------------------------------------------- - * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES - * documented in task.h - *----------------------------------------------------------*/ - - -inline void vTaskIncrementTick( void ) -{ - /* Called by the portable layer each time a tick interrupt occurs. - Increments the tick then checks to see if the new tick value will cause any - tasks to be unblocked. */ - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - ++xTickCount; - if( xTickCount == ( portTickType ) 0 ) - { - xList *pxTemp; - - /* Tick count has overflowed so we need to swap the delay lists. - If there are any items in pxDelayedTaskList here then there is - an error! */ - pxTemp = pxDelayedTaskList; - pxDelayedTaskList = pxOverflowDelayedTaskList; - pxOverflowDelayedTaskList = pxTemp; - xNumOfOverflows++; - } - - /* See if this tick has made a timeout expire. */ - prvCheckDelayedTasks(); - } - else - { - ++uxMissedTicks; - - /* The tick hook gets called at regular intervals, even if the - scheduler is locked. */ - #if ( configUSE_TICK_HOOK == 1 ) - { - extern void vApplicationTickHook( void ); - - vApplicationTickHook(); - } - #endif - } - - #if ( configUSE_TICK_HOOK == 1 ) - { - extern void vApplicationTickHook( void ); - - /* Guard against the tick hook being called when the missed tick - count is being unwound (when the scheduler is being unlocked. */ - if( uxMissedTicks == 0 ) - { - vApplicationTickHook(); - } - } - #endif -} -/*-----------------------------------------------------------*/ - -#if ( ( INCLUDE_vTaskCleanUpResources == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - void vTaskCleanUpResources( void ) - { - unsigned portSHORT usQueue; - volatile tskTCB *pxTCB; - - usQueue = ( unsigned portSHORT ) uxTopUsedPriority + ( unsigned portSHORT ) 1; - - /* Remove any TCB's from the ready queues. */ - do - { - usQueue--; - - while( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ usQueue ] ) ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &( pxReadyTasksLists[ usQueue ] ) ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - }while( usQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); - - /* Remove any TCB's from the delayed queue. */ - while( !listLIST_IS_EMPTY( &xDelayedTaskList1 ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList1 ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - /* Remove any TCB's from the overflow delayed queue. */ - while( !listLIST_IS_EMPTY( &xDelayedTaskList2 ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList2 ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - while( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xSuspendedTaskList ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - } - -#endif -/*-----------------------------------------------------------*/ - -void vTaskSwitchContext( void ) -{ - if( uxSchedulerSuspended != ( unsigned portBASE_TYPE ) pdFALSE ) - { - /* The scheduler is currently suspended - do not allow a context - switch. */ - xMissedYield = pdTRUE; - return; - } - - /* Find the highest priority queue that contains ready tasks. */ - while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) ) - { - --uxTopReadyPriority; - } - - /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the tasks of the - same priority get an equal share of the processor time. */ - listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) ); - vWriteTraceToBuffer(); -} -/*-----------------------------------------------------------*/ - -void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait ) -{ -portTickType xTimeToWake; - - /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE - SCHEDULER SUSPENDED. */ - - /* Place the event list item of the TCB in the appropriate event list. - This is placed in the list in priority order so the highest priority task - is the first to be woken by the event. */ - vListInsert( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) ); - - /* We must remove ourselves from the ready list before adding ourselves - to the blocked list as the same list item is used for both lists. We have - exclusive access to the ready lists as the scheduler is locked. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - - #if ( INCLUDE_vTaskSuspend == 1 ) - { - if( xTicksToWait == portMAX_DELAY ) - { - /* Add ourselves to the suspended task list instead of a delayed task - list to ensure we are not woken by a timing event. We will block - indefinitely. */ - vListInsertEnd( ( xList * ) &xSuspendedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* Calculate the time at which the task should be woken if the event does - not occur. This may overflow but this doesn't matter. */ - xTimeToWake = xTickCount + xTicksToWait; - - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - } - #else - { - /* Calculate the time at which the task should be woken if the event does - not occur. This may overflow but this doesn't matter. */ - xTimeToWake = xTickCount + xTicksToWait; - - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - #endif -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList ) -{ -tskTCB *pxUnblockedTCB; -portBASE_TYPE xReturn; - - /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE - SCHEDULER SUSPENDED. It can also be called from within an ISR. */ - - /* The event list is sorted in priority order, so we can remove the - first in the list, remove the TCB from the delayed list, and add - it to the ready list. - - If an event is for a queue that is locked then this function will never - get called - the lock count on the queue will get modified instead. This - means we can always expect exclusive access to the event list here. */ - pxUnblockedTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); - vListRemove( &( pxUnblockedTCB->xEventListItem ) ); - - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - vListRemove( &( pxUnblockedTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxUnblockedTCB ); - } - else - { - /* We cannot access the delayed or ready lists, so will hold this - task pending until the scheduler is resumed. */ - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); - } - - if( pxUnblockedTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - /* Return true if the task removed from the event list has - a higher priority than the calling task. This allows - the calling task to know if it should force a context - switch now. */ - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vTaskSetTimeOutState( xTimeOutType *pxTimeOut ) -{ - pxTimeOut->xOverflowCount = xNumOfOverflows; - pxTimeOut->xTimeOnEntering = xTickCount; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType *pxTimeOut, portTickType * const pxTicksToWait ) -{ -portBASE_TYPE xReturn; - - #if ( INCLUDE_vTaskSuspend == 1 ) - /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is - the maximum block time then the task should block indefinitely, and - therefore never time out. */ - if( *pxTicksToWait == portMAX_DELAY ) - { - xReturn = pdFALSE; - } - else /* We are not blocking indefinitely, perform the checks below. */ - #endif - - if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xTickCount >= pxTimeOut->xTimeOnEntering ) ) - { - /* The tick count is greater than the time at which vTaskSetTimeout() - was called, but has also overflowed since vTaskSetTimeOut() was called. - It must have wrapped all the way around and gone past us again. This - passed since vTaskSetTimeout() was called. */ - xReturn = pdTRUE; - } - else if( ( xTickCount - pxTimeOut->xTimeOnEntering ) < *pxTicksToWait ) - { - /* Not a genuine timeout. Adjust parameters for time remaining. */ - *pxTicksToWait -= ( xTickCount - pxTimeOut->xTimeOnEntering ); - vTaskSetTimeOutState( pxTimeOut ); - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vTaskMissedYield( void ) -{ - xMissedYield = pdTRUE; -} - -/* - * ----------------------------------------------------------- - * The Idle task. - * ---------------------------------------------------------- - * - * The portTASK_FUNCTION() macro is used to allow port/compiler specific - * language extensions. The equivalent prototype for this function is: - * - * void prvIdleTask( void *pvParameters ); - * - */ -static portTASK_FUNCTION( prvIdleTask, pvParameters ) -{ - /* Stop warnings. */ - ( void ) pvParameters; - - for( ;; ) - { - /* See if any tasks have been deleted. */ - prvCheckTasksWaitingTermination(); - - #if ( configUSE_PREEMPTION == 0 ) - { - /* If we are not using preemption we keep forcing a task switch to - see if any other task has become available. If we are using - preemption we don't need to do this as any task becoming available - will automatically get the processor anyway. */ - taskYIELD(); - } - #endif - - #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) - { - /* When using preemption tasks of equal priority will be - timesliced. If a task that is sharing the idle priority is ready - to run then the idle task should yield before the end of the - timeslice. - - A critical region is not required here as we are just reading from - the list, and an occasional incorrect value will not matter. If - the ready list at the idle priority contains more than one task - then a task other than the idle task is ready to execute. */ - if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( unsigned portBASE_TYPE ) 1 ) - { - taskYIELD(); - } - } - #endif - - #if ( configUSE_IDLE_HOOK == 1 ) - { - extern void vApplicationIdleHook( void ); - - /* Call the user defined function from within the idle task. This - allows the application designer to add background functionality - without the overhead of a separate task. - NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, - CALL A FUNCTION THAT MIGHT BLOCK. */ - vApplicationIdleHook(); - } - #endif - } -} /*lint !e715 pvParameters is not accessed but all task functions require the same prototype. */ - - - - - - - -/*----------------------------------------------------------- - * File private functions documented at the top of the file. - *----------------------------------------------------------*/ - - - -static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ) -{ - pxTCB->usStackDepth = usStackDepth; - - /* Store the function name in the TCB. */ - strncpy( ( char * ) pxTCB->pcTaskName, ( const char * ) pcName, ( unsigned portSHORT ) configMAX_TASK_NAME_LEN ); - pxTCB->pcTaskName[ ( unsigned portSHORT ) configMAX_TASK_NAME_LEN - ( unsigned portSHORT ) 1 ] = '\0'; - - /* This is used as an array index so must ensure it's not too large. */ - if( uxPriority >= configMAX_PRIORITIES ) - { - uxPriority = configMAX_PRIORITIES - 1; - } - - pxTCB->uxPriority = uxPriority; - - vListInitialiseItem( &( pxTCB->xGenericListItem ) ); - vListInitialiseItem( &( pxTCB->xEventListItem ) ); - - /* Set the pxTCB as a link back from the xListItem. This is so we can get - back to the containing TCB from a generic item in a list. */ - listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB ); - - /* Event lists are always in priority order. */ - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); - listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB ); -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseTaskLists( void ) -{ -unsigned portBASE_TYPE uxPriority; - - for( uxPriority = 0; uxPriority < configMAX_PRIORITIES; uxPriority++ ) - { - vListInitialise( ( xList * ) &( pxReadyTasksLists[ uxPriority ] ) ); - } - - vListInitialise( ( xList * ) &xDelayedTaskList1 ); - vListInitialise( ( xList * ) &xDelayedTaskList2 ); - vListInitialise( ( xList * ) &xPendingReadyList ); - - #if ( INCLUDE_vTaskDelete == 1 ) - { - vListInitialise( ( xList * ) &xTasksWaitingTermination ); - } - #endif - - #if ( INCLUDE_vTaskSuspend == 1 ) - { - vListInitialise( ( xList * ) &xSuspendedTaskList ); - } - #endif - - /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList - using list2. */ - pxDelayedTaskList = &xDelayedTaskList1; - pxOverflowDelayedTaskList = &xDelayedTaskList2; -} -/*-----------------------------------------------------------*/ - -static void prvCheckTasksWaitingTermination( void ) -{ - #if ( INCLUDE_vTaskDelete == 1 ) - { - portBASE_TYPE xListIsEmpty; - - /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called - too often in the idle task. */ - if( uxTasksDeleted > ( unsigned portBASE_TYPE ) 0 ) - { - vTaskSuspendAll(); - xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination ); - xTaskResumeAll(); - - if( !xListIsEmpty ) - { - tskTCB *pxTCB; - - portENTER_CRITICAL(); - { - pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xTasksWaitingTermination ) ); - vListRemove( &( pxTCB->xGenericListItem ) ); - --uxCurrentNumberOfTasks; - --uxTasksDeleted; - } - portEXIT_CRITICAL(); - - prvDeleteTCB( pxTCB ); - } - } - } - #endif -} -/*-----------------------------------------------------------*/ - -static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ) -{ -tskTCB *pxNewTCB; - - /* Allocate space for the TCB. Where the memory comes from depends on - the implementation of the port malloc function. */ - pxNewTCB = ( tskTCB * ) pvPortMalloc( sizeof( tskTCB ) ); - - if( pxNewTCB != NULL ) - { - /* Allocate space for the stack used by the task being created. - The base of the stack memory stored in the TCB so the task can - be deleted later if required. */ - pxNewTCB->pxStack = ( portSTACK_TYPE * ) pvPortMalloc( ( ( size_t )usStackDepth ) * sizeof( portSTACK_TYPE ) ); - - if( pxNewTCB->pxStack == NULL ) - { - /* Could not allocate the stack. Delete the allocated TCB. */ - vPortFree( pxNewTCB ); - pxNewTCB = NULL; - } - else - { - /* Just to help debugging. */ - memset( pxNewTCB->pxStack, tskSTACK_FILL_BYTE, usStackDepth * sizeof( portSTACK_TYPE ) ); - } - } - - return pxNewTCB; -} -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ) - { - volatile tskTCB *pxNextTCB, *pxFirstTCB; - static portCHAR pcStatusString[ 50 ]; - unsigned portSHORT usStackRemaining; - - /* Write the details of all the TCB's in pxList into the buffer. */ - listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); - do - { - listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); - usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned portCHAR * ) pxNextTCB->pxStack ); - sprintf( pcStatusString, ( portCHAR * ) "%s\t\t%c\t%u\t%u\t%u\r\n", pxNextTCB->pcTaskName, cStatus, ( unsigned int ) pxNextTCB->uxPriority, usStackRemaining, ( unsigned int ) pxNextTCB->uxTCBNumber ); - strcat( ( portCHAR * ) pcWriteBuffer, ( portCHAR * ) pcStatusString ); - - } while( pxNextTCB != pxFirstTCB ); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte ) - { - register unsigned portSHORT usCount = 0; - - while( *pucStackByte == tskSTACK_FILL_BYTE ) - { - pucStackByte -= portSTACK_GROWTH; - usCount++; - } - - usCount /= sizeof( portSTACK_TYPE ); - - return usCount; - } -#endif -/*-----------------------------------------------------------*/ - - - -#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) - - static void prvDeleteTCB( tskTCB *pxTCB ) - { - /* Free up the memory allocated by the scheduler for the task. It is up to - the task to free any memory allocated at the application level. */ - vPortFree( pxTCB->pxStack ); - vPortFree( pxTCB ); - } - -#endif - - -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) - - xTaskHandle xTaskGetCurrentTaskHandle( void ) - { - xTaskHandle xReturn; - - portENTER_CRITICAL(); - { - xReturn = ( xTaskHandle ) pxCurrentTCB; - } - portEXIT_CRITICAL(); - - return xReturn; - } - -#endif - -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_xTaskGetSchedulerState == 1 ) - - portBASE_TYPE xTaskGetSchedulerState( void ) - { - portBASE_TYPE xReturn; - - if( xSchedulerRunning == pdFALSE ) - { - xReturn = taskSCHEDULER_NOT_STARTED; - } - else - { - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - xReturn = taskSCHEDULER_RUNNING; - } - else - { - xReturn = taskSCHEDULER_SUSPENDED; - } - } - - return xReturn; - } - -#endif - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOSConfig.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOSConfig.h deleted file mode 100644 index fecd82413..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/FreeRTOSConfig.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * MODBUS Slave Library: A portable MODBUS slave for MODBUS ASCII/RTU/TCP. - * Copyright (c) 2007 Christian Walter - * All rights reserved. - * - * $Id$ - */ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/* ----------------------- Defines ------------------------------------------*/ - -#define vPortYieldProcessor swi_handler - -#define configUSE_PREEMPTION ( 1 ) -#define configUSE_IDLE_HOOK ( 0 ) -#define configUSE_TICK_HOOK ( 1 ) -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 48054857UL ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) 2048 ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY ( 1 ) -#define configUSE_16_BIT_TICKS ( 0 ) -#define configIDLE_SHOULD_YIELD ( 1 ) -#define configUSE_CO_ROUTINES ( 0 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -#define INCLUDE_vTaskPrioritySet ( 1 ) -#define INCLUDE_uxTaskPriorityGet ( 1 ) -#define INCLUDE_vTaskDelete ( 1 ) -#define INCLUDE_vTaskCleanUpResources ( 0 ) -#define INCLUDE_vTaskSuspend ( 1 ) -#define INCLUDE_vTaskDelayUntil ( 1 ) -#define INCLUDE_vTaskDelay ( 1 ) -#define INCLUDE_xTaskGetCurrentTaskHandle ( 1 ) - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.c deleted file mode 100644 index e2fd1e61e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * FreeModbus Libary: ARM7 Demo Application - * Copyright (C) 2006 Christian Walter - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "assert.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "support/AT91SAM7X256.h" -#include "support/lib_AT91SAM7X256.h" - -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define REG_HOLDING_START 0x1000 -#define REG_HOLDING_NREGS 130 -#define REG_INPUT_START 0x1000 -#define REG_INPUT_NREGS 4 - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegHoldingStart = REG_HOLDING_START; -static USHORT usRegHoldingBuf[REG_HOLDING_NREGS]; -static USHORT usRegInputStart = REG_INPUT_START; -static USHORT usRegInputBuf[REG_INPUT_NREGS]; - -/* ----------------------- Static functions ---------------------------------*/ -STATIC void vModbusTask( void *pvParameters ); -STATIC void vSetupHardware( void ); - -/* ----------------------- Start implementation -----------------------------*/ -int -main( void ) -{ - vSetupHardware( ); - - ( void )xTaskCreate( vModbusTask, NULL, configMINIMAL_STACK_SIZE, NULL, - tskIDLE_PRIORITY, NULL ); - - vTaskStartScheduler( ); - return 0; -} - -static void -vModbusTask( void *pvParameters ) -{ - int i; - - /* Select either ASCII or RTU Mode. */ - ( void )eMBInit( MB_RTU, 0x0A, 0, 38400, MB_PAR_EVEN ); - - /* Initialize the holding register values before starting the - * Modbus stack - */ - for( i = 0; i < REG_HOLDING_NREGS; i++ ) - { - usRegHoldingBuf[i] = ( unsigned short )i; - } - /* Initialize the input register values before starting the - * Modbus stack - */ - for( i = 0; i < REG_INPUT_NREGS; i++ ) - { - usRegInputBuf[i] = ( unsigned short )i; - } - - /* Enable the Modbus Protocol Stack. */ - ( void )eMBEnable( ); - for( ;; ) - { - /* Call the main polling loop of the Modbus protocol stack. */ - ( void )eMBPoll( ); - } -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_HOLDING_START ) && - ( usAddress + usNRegs <= REG_HOLDING_START + REG_HOLDING_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegHoldingStart ); - switch ( eMode ) - { - /* Pass current register values to the protocol stack. */ - case MB_REG_READ: - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegHoldingBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegHoldingBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - break; - - /* Update current register values with new values from the - * protocol stack. */ - case MB_REG_WRITE: - while( usNRegs > 0 ) - { - usRegHoldingBuf[iRegIndex] = *pucRegBuffer++ << 8; - usRegHoldingBuf[iRegIndex] |= *pucRegBuffer++; - iRegIndex++; - usNRegs--; - } - } - } - else - { - eStatus = MB_ENOREG; - } - return eStatus; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} - - -void -vSetupHardware( void ) -{ - vMBPInit( ); - - /* Enable the peripheral clock. */ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA; - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.hzp b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.hzp deleted file mode 100644 index 6711ff761..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.hzp +++ /dev/null @@ -1,115 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.hzs b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.hzs deleted file mode 100644 index b3e86b6ef..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/demo.hzs +++ /dev/null @@ -1,105 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/port.h deleted file mode 100644 index 636c923fa..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/port.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * FreeModbus Libary: ARM7/AT91SAM7X Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -#include -#include - -#include "FreeRTOS.h" - -#ifdef _cplusplus -extern "C" -{ -#endif - -/* ----------------------- Defines ------------------------------------------*/ - -#define INLINE inline -#define STATIC static - -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#define MB_PORT_HAS_CLOSE 1 -#define ENTER_CRITICAL_SECTION( ) vMBPPortEnterCritical( ) -#define EXIT_CRITICAL_SECTION( ) vMBPPortExitCritical( ) - -#ifndef TRUE -#define TRUE ( BOOL )1 -#endif - -#ifndef FALSE -#define FALSE ( BOOL )0 -#endif - -/* ----------------------- Type definitions ---------------------------------*/ - typedef char BOOL; - - typedef signed char BYTE; - typedef unsigned char UBYTE; - - typedef unsigned char UCHAR; - typedef char CHAR; - - typedef unsigned short USHORT; - typedef short SHORT; - - typedef unsigned long ULONG; - typedef long LONG; - -/* ----------------------- Function prototypes ------------------------------*/ - BOOL bMBPIsWithinException( void ); - void vMBPInit( void ); - void vMBPPortEnterCritical( void ); - void vMBPPortExitCritical( void ); - -#ifdef _cplusplus -} -#endif - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portevent.c deleted file mode 100644 index ebbde2eae..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portevent.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * FreeModbus Libary: ARM7/AT91SAM7X Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ -/* ----------------------- System includes ----------------------------------*/ -#include - -/* ----------------------- Platform includes --------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define HDL_RESET( x ) do { \ - ( x )->xQueueHdl = 0; \ -} while( 0 ); - -/* ----------------------- Type definitions ---------------------------------*/ -typedef struct -{ - xQueueHandle xQueueHdl; -} xEventInternalHandle; - -/* ----------------------- Static variables ---------------------------------*/ -STATIC BOOL bIsInitialized = FALSE; -STATIC xEventInternalHandle arxEventHdls[1]; - -/* ----------------------- Static functions ---------------------------------*/ - -/* ----------------------- Start implementation -----------------------------*/ - -BOOL -xMBPortEventInit( void ) -{ - BOOL bOkay = FALSE; - xQueueHandle xQueueHdl; - - ENTER_CRITICAL_SECTION( ); - xQueueHdl = xQueueCreate( 1, sizeof( eMBEventType ) ); - if( 0 != xQueueHdl ) - { - arxEventHdls[0].xQueueHdl = xQueueHdl; - bIsInitialized = TRUE; - bOkay = TRUE; - } - EXIT_CRITICAL_SECTION( ); - - return bOkay; -} - -void -vMBPortEventClose( ) -{ - ENTER_CRITICAL_SECTION( ); - if( bIsInitialized ) - { - if( 0 != arxEventHdls[0].xQueueHdl ) - { - vQueueDelete( arxEventHdls[0].xQueueHdl ); - } - HDL_RESET( &arxEventHdls[0] ); - } - EXIT_CRITICAL_SECTION( ); -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - portBASE_TYPE xEventSent = pdFALSE; - - ENTER_CRITICAL_SECTION( ); - if( bIsInitialized ) - { - if( bMBPIsWithinException( ) ) - { - xEventSent = - xQueueSendFromISR( arxEventHdls[0].xQueueHdl, ( const void * )&eEvent, pdFALSE ); - } - else - { - xEventSent = xQueueSend( arxEventHdls[0].xQueueHdl, ( const void * )&eEvent, pdFALSE ); - } - } - EXIT_CRITICAL_SECTION( ); - return xEventSent == pdTRUE ? TRUE : FALSE; -} - -BOOL -xMBPortEventGet( eMBEventType * peEvent ) -{ - BOOL bEventInQueue = FALSE; - - ENTER_CRITICAL_SECTION( ); - if( bIsInitialized ) - { - if( pdTRUE == xQueueReceive( arxEventHdls[0].xQueueHdl, peEvent, portTICK_RATE_MS * 50 ) ) - { - bEventInQueue = TRUE; - } - } - EXIT_CRITICAL_SECTION( ); - return bEventInQueue; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portother.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portother.c deleted file mode 100644 index f881374e4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portother.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * FreeModbus Libary: ARM7/AT91SAM7X Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include - -#include "FreeRTOS.h" -#include "task.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "AT91SAM7X256.h" -#include "lib_AT91SAM7X256.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "port.h" - -/* ----------------------- Defines ------------------------------------------*/ - -/* ----------------------- Type definitions ---------------------------------*/ - -/* ----------------------- Function prototypes ------------------------------*/ -void vMBPortSerialClose( void ); -void vMBPortEventClose( void ); -void vMBPortTimerClose( void ); - -/* ----------------------- Static variables ---------------------------------*/ - -/* ----------------------- Static functions ---------------------------------*/ -STATIC void vDefaultHandler( void ) __attribute__ ( ( interrupt( "IRQ" ) ) ); -STATIC void vDefaultSpuriousHandler( void ) __attribute__ ( ( interrupt( "IRQ" ) ) ); - -/* ----------------------- Start implementation -----------------------------*/ - -void -vMBPInit( void ) -{ - AT91F_AIC_Open( AT91C_BASE_AIC, AT91C_AIC_BRANCH_OPCODE, AT91C_AIC_BRANCH_OPCODE, - vDefaultHandler, vDefaultSpuriousHandler, AT91C_AIC_DCR_PROT ); -} - -void -__assert( const char *pcFile, const char *pcAssertion, int iLine ) -{ - volatile BOOL bBreakOut = FALSE; - - ( void )pcFile; - ( void )pcAssertion; - ( void )iLine; - ENTER_CRITICAL_SECTION( ); - while( !bBreakOut ); -} - -BOOL -bMBPIsWithinException( void ) -{ - BOOL bMBPIsWithinException = TRUE; - unsigned int uiCPSR; - asm volatile ( "MRS %0, CPSR":"=r" ( uiCPSR ): ); - - switch ( uiCPSR & 0x000000001F ) - { - case 0x00000010U: /* User Mode */ - case 0x0000001FU: /* System Mode */ - bMBPIsWithinException = FALSE; - break; - } - return bMBPIsWithinException; -} - -void -vMBPPortEnterCritical( void ) -{ - if( !bMBPIsWithinException( ) ) - { - portENTER_CRITICAL( ); - } -} - -void -vMBPPortExitCritical( void ) -{ - if( !bMBPIsWithinException( ) ) - { - portEXIT_CRITICAL( ); - } -} - -void -vMBPortClose( void ) -{ - vMBPortSerialClose( ); - vMBPortEventClose( ); - vMBPortTimerClose( ); -} - -void -vDefaultSpuriousHandler( void ) -{ -} - -void -vDefaultHandler( void ) -{ -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portserial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portserial.c deleted file mode 100644 index d68d9adde..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/portserial.c +++ /dev/null @@ -1,259 +0,0 @@ -/* - * FreeModbus Libary: ARM7/AT91SAM7X Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include -#include - -/* ----------------------- Platform includes --------------------------------*/ -#include "AT91SAM7X256.h" -#include "lib_AT91SAM7X256.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ - -#define USART_INTERRUPT_LEVEL ( 7 ) -#define USART_USART0_IDX ( 0 ) -#define USART_USART1_IDX ( 1 ) - -#define IDX_INVALID ( 255 ) -#define UART_BAUDRATE_MIN ( 300 ) -#define UART_BAUDRATE_MAX ( 115200 ) - -#define UART_INIT( ubIdx ) do { \ - if( AT91C_ID_US0 == ubIdx ) \ - { \ - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, AT91C_PA0_RXD0 | AT91C_PA1_TXD0 | AT91C_PA3_RTS0, 0 ); \ - } \ - else if( AT91C_ID_US1 == ubIdx ) \ - { \ - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, AT91C_PA5_RXD1 | AT91C_PA6_TXD1 | AT91C_PA8_RTS1, 0 ); \ - } \ - else \ - { \ - assert( 0 ); \ - } \ -} while( 0 ) - -#define HDL_RESET( x ) do { \ - ( x )->pxCOM = NULL; \ - ( x )->uiAT91C_ID_USX = 0; \ - ( x )->pvIRQHandlerFN = NULL; \ - ( x )->bIsRxEnabled = FALSE; \ - ( x )->bIsTxEnabled = FALSE; \ -} while( 0 ); - -/* ----------------------- Type definitions ---------------------------------*/ - -typedef struct -{ - AT91PS_USART pxCOM; - unsigned int uiAT91C_ID_USX; - volatile BOOL bIsRxEnabled; - volatile BOOL bIsTxEnabled; - void ( *pvIRQHandlerFN ) ( void ); -} xMBPSerialIntHandle; - -/* ----------------------- Static variables ---------------------------------*/ -STATIC xMBPSerialIntHandle xSerialHdls[1]; -STATIC BOOL bIsInitalized = FALSE; - -/* ----------------------- Static functions ---------------------------------*/ -STATIC void vUSART0ISR( void ) __attribute__ ( ( interrupt( "IRQ" ) ) ); -STATIC void vUSART1ISR( void ) __attribute__ ( ( interrupt( "IRQ" ) ) ); - -/* ----------------------- Start implementation -----------------------------*/ - -BOOL -xMBPortSerialInit( UCHAR ucPort, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity ) -{ - BOOL bOkay = TRUE; - unsigned int uiUARTMode = 0; - - ENTER_CRITICAL_SECTION( ); - if( !bIsInitalized ) - { - HDL_RESET( &xSerialHdls[0] ); - bIsInitalized = TRUE; - } - - uiUARTMode = AT91C_US_USMODE_RS485 | AT91C_US_CLKS_CLOCK; - switch ( eParity ) - { - case MB_PAR_NONE: - uiUARTMode |= AT91C_US_PAR_NONE; - uiUARTMode |= AT91C_US_NBSTOP_2_BIT; - break; - case MB_PAR_EVEN: - uiUARTMode |= AT91C_US_PAR_EVEN; - uiUARTMode |= AT91C_US_NBSTOP_1_BIT; - break; - case MB_PAR_ODD: - uiUARTMode |= AT91C_US_PAR_ODD; - uiUARTMode |= AT91C_US_NBSTOP_1_BIT; - break; - default: - break; - } - switch ( ucDataBits ) - { - case 8: - uiUARTMode |= AT91C_US_CHRL_8_BITS; - break; - case 7: - uiUARTMode |= AT91C_US_CHRL_7_BITS; - break; - default: - break; - } - if( bOkay ) - { - if( ( ucPort == USART_USART0_IDX ) && ( NULL == xSerialHdls[0].pxCOM ) ) - { - xSerialHdls[0].pxCOM = AT91C_BASE_US0; - xSerialHdls[0].uiAT91C_ID_USX = AT91C_ID_US0; - xSerialHdls[0].pvIRQHandlerFN = vUSART0ISR; - } - else if( ( ucPort == USART_USART1_IDX ) && ( NULL == xSerialHdls[0].pxCOM ) ) - { - xSerialHdls[0].pxCOM = AT91C_BASE_US1; - xSerialHdls[0].uiAT91C_ID_USX = AT91C_ID_US1; - xSerialHdls[0].pvIRQHandlerFN = vUSART1ISR; - } - else - { - bOkay = FALSE; - } - - if( bOkay ) - { - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << xSerialHdls[0].uiAT91C_ID_USX ); - AT91F_US_Configure( xSerialHdls[0].pxCOM, configCPU_CLOCK_HZ, uiUARTMode, ulBaudRate, - 0 ); - xSerialHdls[0].pxCOM->US_CR = AT91C_US_TXEN | AT91C_US_RXEN; - AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, xSerialHdls[0].uiAT91C_ID_USX, - USART_INTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, - xSerialHdls[0].pvIRQHandlerFN ); - AT91F_AIC_EnableIt( AT91C_BASE_AIC, xSerialHdls[0].uiAT91C_ID_USX ); - UART_INIT( xSerialHdls[0].uiAT91C_ID_USX ); - } - } - else - { - bOkay = FALSE; - } - - EXIT_CRITICAL_SECTION( ); - return bOkay; -} - -void -vMBPortSerialClose( void ) -{ - if( bIsInitalized ) - { - if( NULL != xSerialHdls[0].pxCOM ) - { - AT91F_AIC_DisableIt( AT91C_BASE_AIC, xSerialHdls[0].uiAT91C_ID_USX ); - AT91F_US_Close( xSerialHdls[0].pxCOM ); - HDL_RESET( &xSerialHdls[0] ); - } - } -} - -void -vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable ) -{ - ENTER_CRITICAL_SECTION( ); - assert( NULL != xSerialHdls[0].pxCOM ); - if( xRxEnable ) - { - AT91F_US_EnableIt( xSerialHdls[0].pxCOM, AT91C_US_RXRDY ); - xSerialHdls[0].bIsRxEnabled = TRUE; - } - else - { - AT91F_US_DisableIt( xSerialHdls[0].pxCOM, AT91C_US_RXRDY ); - xSerialHdls[0].bIsRxEnabled = FALSE; - } - - if( xTxEnable ) - { - AT91F_US_EnableIt( xSerialHdls[0].pxCOM, AT91C_US_TXRDY ); - xSerialHdls[0].bIsTxEnabled = TRUE; - } - else - { - AT91F_US_DisableIt( xSerialHdls[0].pxCOM, AT91C_US_TXRDY ); - xSerialHdls[0].bIsTxEnabled = FALSE; - } - EXIT_CRITICAL_SECTION( ); -} - -STATIC INLINE void -vUSARTIRQHandler( void ) -{ - unsigned int uiUSARTStatus = xSerialHdls[0].pxCOM->US_CSR; - - if( xSerialHdls[0].bIsRxEnabled && ( uiUSARTStatus & AT91C_US_RXRDY ) ) - { - pxMBFrameCBByteReceived( ); - } - if( xSerialHdls[0].bIsTxEnabled && ( uiUSARTStatus & AT91C_US_TXRDY ) ) - { - pxMBFrameCBTransmitterEmpty( ); - } -} - -BOOL -xMBPortSerialPutByte( CHAR ucByte ) -{ - assert( NULL != xSerialHdls[0].pxCOM ); - AT91F_US_PutChar( xSerialHdls[0].pxCOM, ucByte ); - return TRUE; -} - -BOOL -xMBPortSerialGetByte( CHAR * pucByte ) -{ - assert( NULL != xSerialHdls[0].pxCOM ); - *pucByte = ( CHAR ) AT91F_US_GetChar( xSerialHdls[0].pxCOM ); - return TRUE; -} - -void -vUSART0ISR( void ) -{ - assert( NULL != xSerialHdls[0].pxCOM ); - vUSARTIRQHandler( ); - AT91C_BASE_AIC->AIC_EOICR = 0; -} - -void -vUSART1ISR( void ) -{ - assert( NULL != xSerialHdls[0].pxCOM ); - vUSARTIRQHandler( ); - AT91C_BASE_AIC->AIC_EOICR = 0; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/porttimer.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/porttimer.c deleted file mode 100644 index 9f266043f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/port/porttimer.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * MODBUS Library: AT91SAM7X/FreeRTOS port - * Copyright (c) 2007 Christian Walter - * All rights reserved. - * - * $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include - -/* ----------------------- FreeRTOS includes --------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define TIMER_TIMEOUT_INVALID ( 65535U ) - -/* ----------------------- Type definitions ---------------------------------*/ -typedef struct -{ - volatile USHORT usNTimeOutMS; - volatile USHORT usNTimeLeft; -} xTimerInternalHandle; - -/* ----------------------- Static variables ---------------------------------*/ -STATIC xTimerInternalHandle arxTimerHdls[1]; -STATIC BOOL bIsInitalized = FALSE; - -/* ----------------------- Static functions ---------------------------------*/ - -/* ----------------------- Start implementation -----------------------------*/ - -BOOL -xMBPortTimersInit( USHORT usTim1Timerout50us ) -{ - USHORT usTimeoutMS; - - ENTER_CRITICAL_SECTION( ); - usTimeoutMS = ( usTim1Timerout50us + 10 ) / 20; - if( 0 == usTimeoutMS ) - { - usTimeoutMS = 1; - } - arxTimerHdls[0].usNTimeOutMS = usTimeoutMS; - arxTimerHdls[0].usNTimeLeft = TIMER_TIMEOUT_INVALID; - bIsInitalized = TRUE; - EXIT_CRITICAL_SECTION( ); - - return TRUE; -} - -void -vMBPortTimerClose( void ) -{ - ENTER_CRITICAL_SECTION( ); - if( bIsInitalized ) - { - arxTimerHdls[0].usNTimeLeft = TIMER_TIMEOUT_INVALID; - bIsInitalized = FALSE; - } - EXIT_CRITICAL_SECTION( ); -} - -void -vMBPortTimersEnable( ) -{ - assert( bIsInitalized ); - ENTER_CRITICAL_SECTION( ); - arxTimerHdls[0].usNTimeLeft = arxTimerHdls[0].usNTimeOutMS; - EXIT_CRITICAL_SECTION( ); -} - -void -vMBPortTimersDisable( ) -{ - assert( bIsInitalized ); - ENTER_CRITICAL_SECTION( ); - arxTimerHdls[0].usNTimeLeft = TIMER_TIMEOUT_INVALID; - EXIT_CRITICAL_SECTION( ); -} - -void -vApplicationTickHook( void ) -{ - if( bIsInitalized ) - { - if( TIMER_TIMEOUT_INVALID != arxTimerHdls[0].usNTimeLeft ) - { - arxTimerHdls[0].usNTimeLeft--; - if( 0 == arxTimerHdls[0].usNTimeLeft ) - { - arxTimerHdls[0].usNTimeLeft = TIMER_TIMEOUT_INVALID; - pxMBPortCBTimerExpired( ); - } - } - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/AT91SAM7X256.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/AT91SAM7X256.h deleted file mode 100644 index 032a97e5f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/AT91SAM7X256.h +++ /dev/null @@ -1,2551 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7X256.h -// Object : AT91SAM7X256 definitions -// Generated : AT91 SW Application Group 01/16/2006 (16:36:21) -// -// CVS Reference : /AT91SAM7X256.pl/1.15/Wed Nov 2 13:56:49 2005// -// CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// -// CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// -// CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// -// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 14:57:50 2005// -// CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// -// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:19:19 2005// -// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// -// CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:05:35 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7X256_H -#define AT91SAM7X256_H - -typedef volatile unsigned int AT91_REG; // Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS -{ - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[85]; // - AT91_REG PIOB_PER; // PIO Enable Register - AT91_REG PIOB_PDR; // PIO Disable Register - AT91_REG PIOB_PSR; // PIO Status Register - AT91_REG Reserved13[1]; // - AT91_REG PIOB_OER; // Output Enable Register - AT91_REG PIOB_ODR; // Output Disable Registerr - AT91_REG PIOB_OSR; // Output Status Register - AT91_REG Reserved14[1]; // - AT91_REG PIOB_IFER; // Input Filter Enable Register - AT91_REG PIOB_IFDR; // Input Filter Disable Register - AT91_REG PIOB_IFSR; // Input Filter Status Register - AT91_REG Reserved15[1]; // - AT91_REG PIOB_SODR; // Set Output Data Register - AT91_REG PIOB_CODR; // Clear Output Data Register - AT91_REG PIOB_ODSR; // Output Data Status Register - AT91_REG PIOB_PDSR; // Pin Data Status Register - AT91_REG PIOB_IER; // Interrupt Enable Register - AT91_REG PIOB_IDR; // Interrupt Disable Register - AT91_REG PIOB_IMR; // Interrupt Mask Register - AT91_REG PIOB_ISR; // Interrupt Status Register - AT91_REG PIOB_MDER; // Multi-driver Enable Register - AT91_REG PIOB_MDDR; // Multi-driver Disable Register - AT91_REG PIOB_MDSR; // Multi-driver Status Register - AT91_REG Reserved16[1]; // - AT91_REG PIOB_PPUDR; // Pull-up Disable Register - AT91_REG PIOB_PPUER; // Pull-up Enable Register - AT91_REG PIOB_PPUSR; // Pull-up Status Register - AT91_REG Reserved17[1]; // - AT91_REG PIOB_ASR; // Select A Register - AT91_REG PIOB_BSR; // Select B Register - AT91_REG PIOB_ABSR; // AB Select Status Register - AT91_REG Reserved18[9]; // - AT91_REG PIOB_OWER; // Output Write Enable Register - AT91_REG PIOB_OWDR; // Output Write Disable Register - AT91_REG PIOB_OWSR; // Output Write Status Register - AT91_REG Reserved19[341]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved20[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved21[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved22[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved23[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved24[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved25[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved26[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved27[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS , *AT91PS_SYS; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC -{ - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC , *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -typedef struct _AT91S_PDC -{ - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC , *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU -{ - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU , *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO -{ - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO , *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR -{ - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR , *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC -{ - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[4]; // Programmable Clock Register - AT91_REG Reserved4[4]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC , *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC -{ - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC , *AT91PS_RSTC; - -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Length -#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC -{ - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC , *AT91PS_RTTC; - -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC -{ - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC , *AT91PS_PITC; - -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC -{ - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC , *AT91PS_WDTC; - -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -typedef struct _AT91S_VREG -{ - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG , *AT91PS_VREG; - -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC -{ - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC , *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI -{ - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI , *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART -{ - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART , *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC -{ - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC , *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection -#define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock -#define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low -#define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0 -#define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1 -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI -{ - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI , *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH -{ - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; - -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC -{ - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC , *AT91PS_PWMC; - -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP -{ - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register - AT91_REG Reserved3[2]; // - AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register - AT91_REG Reserved4[3]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP , *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt -#define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -#define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 -#define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) -#define AT91C_UDP_PUON ((unsigned int) 0x1 << 9) // (UDP) Pull-up ON - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC -{ - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC , *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB -{ - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB , *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface -// ***************************************************************************** -typedef struct _AT91S_CAN_MB -{ - AT91_REG CAN_MB_MMR; // MailBox Mode Register - AT91_REG CAN_MB_MAM; // MailBox Acceptance Mask Register - AT91_REG CAN_MB_MID; // MailBox ID Register - AT91_REG CAN_MB_MFID; // MailBox Family ID Register - AT91_REG CAN_MB_MSR; // MailBox Status Register - AT91_REG CAN_MB_MDL; // MailBox Data Low Register - AT91_REG CAN_MB_MDH; // MailBox Data High Register - AT91_REG CAN_MB_MCR; // MailBox Control Register -} AT91S_CAN_MB , *AT91PS_CAN_MB; - -// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- -#define AT91C_CAN_MTIMEMARK ((unsigned int) 0xFFFF << 0) // (CAN_MB) Mailbox Timemark -#define AT91C_CAN_PRIOR ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority -#define AT91C_CAN_MOT ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type -#define AT91C_CAN_MOT_DIS ((unsigned int) 0x0 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RX ((unsigned int) 0x1 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_RXOVERWRITE ((unsigned int) 0x2 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_TX ((unsigned int) 0x3 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_CONSUMER ((unsigned int) 0x4 << 24) // (CAN_MB) -#define AT91C_CAN_MOT_PRODUCER ((unsigned int) 0x5 << 24) // (CAN_MB) -// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- -#define AT91C_CAN_MIDvB ((unsigned int) 0x3FFFF << 0) // (CAN_MB) Complementary bits for identifier in extended mode -#define AT91C_CAN_MIDvA ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode -#define AT91C_CAN_MIDE ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version -// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- -// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- -// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- -#define AT91C_CAN_MTIMESTAMP ((unsigned int) 0xFFFF << 0) // (CAN_MB) Timer Value -#define AT91C_CAN_MDLC ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code -#define AT91C_CAN_MRTR ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request -#define AT91C_CAN_MABT ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort -#define AT91C_CAN_MRDY ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready -#define AT91C_CAN_MMI ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored -// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- -// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- -// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- -#define AT91C_CAN_MACR ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox -#define AT91C_CAN_MTCR ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Control Area Network Interface -// ***************************************************************************** -typedef struct _AT91S_CAN -{ - AT91_REG CAN_MR; // Mode Register - AT91_REG CAN_IER; // Interrupt Enable Register - AT91_REG CAN_IDR; // Interrupt Disable Register - AT91_REG CAN_IMR; // Interrupt Mask Register - AT91_REG CAN_SR; // Status Register - AT91_REG CAN_BR; // Baudrate Register - AT91_REG CAN_TIM; // Timer Register - AT91_REG CAN_TIMESTP; // Time Stamp Register - AT91_REG CAN_ECR; // Error Counter Register - AT91_REG CAN_TCR; // Transfer Command Register - AT91_REG CAN_ACR; // Abort Command Register - AT91_REG Reserved0[52]; // - AT91_REG CAN_VR; // Version Register - AT91_REG Reserved1[64]; // - AT91S_CAN_MB CAN_MB0; // CAN Mailbox 0 - AT91S_CAN_MB CAN_MB1; // CAN Mailbox 1 - AT91S_CAN_MB CAN_MB2; // CAN Mailbox 2 - AT91S_CAN_MB CAN_MB3; // CAN Mailbox 3 - AT91S_CAN_MB CAN_MB4; // CAN Mailbox 4 - AT91S_CAN_MB CAN_MB5; // CAN Mailbox 5 - AT91S_CAN_MB CAN_MB6; // CAN Mailbox 6 - AT91S_CAN_MB CAN_MB7; // CAN Mailbox 7 - AT91S_CAN_MB CAN_MB8; // CAN Mailbox 8 - AT91S_CAN_MB CAN_MB9; // CAN Mailbox 9 - AT91S_CAN_MB CAN_MB10; // CAN Mailbox 10 - AT91S_CAN_MB CAN_MB11; // CAN Mailbox 11 - AT91S_CAN_MB CAN_MB12; // CAN Mailbox 12 - AT91S_CAN_MB CAN_MB13; // CAN Mailbox 13 - AT91S_CAN_MB CAN_MB14; // CAN Mailbox 14 - AT91S_CAN_MB CAN_MB15; // CAN Mailbox 15 -} AT91S_CAN , *AT91PS_CAN; - -// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- -#define AT91C_CAN_CANEN ((unsigned int) 0x1 << 0) // (CAN) CAN Controller Enable -#define AT91C_CAN_LPM ((unsigned int) 0x1 << 1) // (CAN) Disable/Enable Low Power Mode -#define AT91C_CAN_ABM ((unsigned int) 0x1 << 2) // (CAN) Disable/Enable Autobaud/Listen Mode -#define AT91C_CAN_OVL ((unsigned int) 0x1 << 3) // (CAN) Disable/Enable Overload Frame -#define AT91C_CAN_TEOF ((unsigned int) 0x1 << 4) // (CAN) Time Stamp messages at each end of Frame -#define AT91C_CAN_TTM ((unsigned int) 0x1 << 5) // (CAN) Disable/Enable Time Trigger Mode -#define AT91C_CAN_TIMFRZ ((unsigned int) 0x1 << 6) // (CAN) Enable Timer Freeze -#define AT91C_CAN_DRPT ((unsigned int) 0x1 << 7) // (CAN) Disable Repeat -// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- -#define AT91C_CAN_MB0 ((unsigned int) 0x1 << 0) // (CAN) Mailbox 0 Flag -#define AT91C_CAN_MB1 ((unsigned int) 0x1 << 1) // (CAN) Mailbox 1 Flag -#define AT91C_CAN_MB2 ((unsigned int) 0x1 << 2) // (CAN) Mailbox 2 Flag -#define AT91C_CAN_MB3 ((unsigned int) 0x1 << 3) // (CAN) Mailbox 3 Flag -#define AT91C_CAN_MB4 ((unsigned int) 0x1 << 4) // (CAN) Mailbox 4 Flag -#define AT91C_CAN_MB5 ((unsigned int) 0x1 << 5) // (CAN) Mailbox 5 Flag -#define AT91C_CAN_MB6 ((unsigned int) 0x1 << 6) // (CAN) Mailbox 6 Flag -#define AT91C_CAN_MB7 ((unsigned int) 0x1 << 7) // (CAN) Mailbox 7 Flag -#define AT91C_CAN_MB8 ((unsigned int) 0x1 << 8) // (CAN) Mailbox 8 Flag -#define AT91C_CAN_MB9 ((unsigned int) 0x1 << 9) // (CAN) Mailbox 9 Flag -#define AT91C_CAN_MB10 ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag -#define AT91C_CAN_MB11 ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag -#define AT91C_CAN_MB12 ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag -#define AT91C_CAN_MB13 ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag -#define AT91C_CAN_MB14 ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag -#define AT91C_CAN_MB15 ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag -#define AT91C_CAN_ERRA ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag -#define AT91C_CAN_WARN ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag -#define AT91C_CAN_ERRP ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag -#define AT91C_CAN_BOFF ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag -#define AT91C_CAN_SLEEP ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag -#define AT91C_CAN_WAKEUP ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag -#define AT91C_CAN_TOVF ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag -#define AT91C_CAN_TSTP ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag -#define AT91C_CAN_CERR ((unsigned int) 0x1 << 24) // (CAN) CRC Error -#define AT91C_CAN_SERR ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error -#define AT91C_CAN_AERR ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error -#define AT91C_CAN_FERR ((unsigned int) 0x1 << 27) // (CAN) Form Error -#define AT91C_CAN_BERR ((unsigned int) 0x1 << 28) // (CAN) Bit Error -// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- -// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- -// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- -#define AT91C_CAN_RBSY ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy -#define AT91C_CAN_TBSY ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy -#define AT91C_CAN_OVLY ((unsigned int) 0x1 << 31) // (CAN) Overload Busy -// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- -#define AT91C_CAN_PHASE2 ((unsigned int) 0x7 << 0) // (CAN) Phase 2 segment -#define AT91C_CAN_PHASE1 ((unsigned int) 0x7 << 4) // (CAN) Phase 1 segment -#define AT91C_CAN_PROPAG ((unsigned int) 0x7 << 8) // (CAN) Programmation time segment -#define AT91C_CAN_SYNC ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment -#define AT91C_CAN_BRP ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler -#define AT91C_CAN_SMP ((unsigned int) 0x1 << 24) // (CAN) Sampling mode -// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- -#define AT91C_CAN_TIMER ((unsigned int) 0xFFFF << 0) // (CAN) Timer field -// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- -// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- -#define AT91C_CAN_REC ((unsigned int) 0xFF << 0) // (CAN) Receive Error Counter -#define AT91C_CAN_TEC ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter -// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- -#define AT91C_CAN_TIMRST ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field -// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 -// ***************************************************************************** -typedef struct _AT91S_EMAC -{ - AT91_REG EMAC_NCR; // Network Control Register - AT91_REG EMAC_NCFGR; // Network Configuration Register - AT91_REG EMAC_NSR; // Network Status Register - AT91_REG Reserved0[2]; // - AT91_REG EMAC_TSR; // Transmit Status Register - AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer - AT91_REG EMAC_TBQP; // Transmit Buffer Queue Pointer - AT91_REG EMAC_RSR; // Receive Status Register - AT91_REG EMAC_ISR; // Interrupt Status Register - AT91_REG EMAC_IER; // Interrupt Enable Register - AT91_REG EMAC_IDR; // Interrupt Disable Register - AT91_REG EMAC_IMR; // Interrupt Mask Register - AT91_REG EMAC_MAN; // PHY Maintenance Register - AT91_REG EMAC_PTR; // Pause Time Register - AT91_REG EMAC_PFR; // Pause Frames received Register - AT91_REG EMAC_FTO; // Frames Transmitted OK Register - AT91_REG EMAC_SCF; // Single Collision Frame Register - AT91_REG EMAC_MCF; // Multiple Collision Frame Register - AT91_REG EMAC_FRO; // Frames Received OK Register - AT91_REG EMAC_FCSE; // Frame Check Sequence Error Register - AT91_REG EMAC_ALE; // Alignment Error Register - AT91_REG EMAC_DTF; // Deferred Transmission Frame Register - AT91_REG EMAC_LCOL; // Late Collision Register - AT91_REG EMAC_ECOL; // Excessive Collision Register - AT91_REG EMAC_TUND; // Transmit Underrun Error Register - AT91_REG EMAC_CSE; // Carrier Sense Error Register - AT91_REG EMAC_RRE; // Receive Ressource Error Register - AT91_REG EMAC_ROV; // Receive Overrun Errors Register - AT91_REG EMAC_RSE; // Receive Symbol Errors Register - AT91_REG EMAC_ELE; // Excessive Length Errors Register - AT91_REG EMAC_RJA; // Receive Jabbers Register - AT91_REG EMAC_USF; // Undersize Frames Register - AT91_REG EMAC_STE; // SQE Test Error Register - AT91_REG EMAC_RLE; // Receive Length Field Mismatch Register - AT91_REG EMAC_TPF; // Transmitted Pause Frames Register - AT91_REG EMAC_HRB; // Hash Address Bottom[31:0] - AT91_REG EMAC_HRT; // Hash Address Top[63:32] - AT91_REG EMAC_SA1L; // Specific Address 1 Bottom, First 4 bytes - AT91_REG EMAC_SA1H; // Specific Address 1 Top, Last 2 bytes - AT91_REG EMAC_SA2L; // Specific Address 2 Bottom, First 4 bytes - AT91_REG EMAC_SA2H; // Specific Address 2 Top, Last 2 bytes - AT91_REG EMAC_SA3L; // Specific Address 3 Bottom, First 4 bytes - AT91_REG EMAC_SA3H; // Specific Address 3 Top, Last 2 bytes - AT91_REG EMAC_SA4L; // Specific Address 4 Bottom, First 4 bytes - AT91_REG EMAC_SA4H; // Specific Address 4 Top, Last 2 bytes - AT91_REG EMAC_TID; // Type ID Checking Register - AT91_REG EMAC_TPQ; // Transmit Pause Quantum Register - AT91_REG EMAC_USRIO; // USER Input/Output Register - AT91_REG EMAC_WOL; // Wake On LAN Register - AT91_REG Reserved1[13]; // - AT91_REG EMAC_REV; // Revision Register -} AT91S_EMAC , *AT91PS_EMAC; - -// -------- EMAC_NCR : (EMAC Offset: 0x0) -------- -#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level. -#define AT91C_EMAC_LLB ((unsigned int) 0x1 << 1) // (EMAC) Loopback local. -#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) // (EMAC) Receive enable. -#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) // (EMAC) Transmit enable. -#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) // (EMAC) Management port enable. -#define AT91C_EMAC_CLRSTAT ((unsigned int) 0x1 << 5) // (EMAC) Clear statistics registers. -#define AT91C_EMAC_INCSTAT ((unsigned int) 0x1 << 6) // (EMAC) Increment statistics registers. -#define AT91C_EMAC_WESTAT ((unsigned int) 0x1 << 7) // (EMAC) Write enable for statistics registers. -#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) // (EMAC) Back pressure. -#define AT91C_EMAC_TSTART ((unsigned int) 0x1 << 9) // (EMAC) Start Transmission. -#define AT91C_EMAC_THALT ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. -#define AT91C_EMAC_TPFR ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame -#define AT91C_EMAC_TZQ ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame -// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- -#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) // (EMAC) Speed. -#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) // (EMAC) Full duplex. -#define AT91C_EMAC_JFRAME ((unsigned int) 0x1 << 3) // (EMAC) Jumbo Frames. -#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) // (EMAC) Copy all frames. -#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) // (EMAC) No broadcast. -#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) // (EMAC) Multicast hash event enable -#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) // (EMAC) Unicast hash enable. -#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) // (EMAC) Receive 1522 bytes. -#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) // (EMAC) External address match enable. -#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) // (EMAC) -#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8 -#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16 -#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32 -#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64 -#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PAE ((unsigned int) 0x1 << 13) // (EMAC) -#define AT91C_EMAC_RBOF ((unsigned int) 0x3 << 14) // (EMAC) -#define AT91C_EMAC_RBOF_OFFSET_0 ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_1 ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_2 ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer -#define AT91C_EMAC_RBOF_OFFSET_3 ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer -#define AT91C_EMAC_RLCE ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable -#define AT91C_EMAC_DRFCS ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS -#define AT91C_EMAC_EFRHD ((unsigned int) 0x1 << 18) // (EMAC) -#define AT91C_EMAC_IRXFCS ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS -// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- -#define AT91C_EMAC_LINKR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- -#define AT91C_EMAC_UBR ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RLES ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TGO ((unsigned int) 0x1 << 3) // (EMAC) Transmit Go -#define AT91C_EMAC_BEX ((unsigned int) 0x1 << 4) // (EMAC) Buffers exhausted mid frame -#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) // (EMAC) -// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- -#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 2) // (EMAC) -// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- -#define AT91C_EMAC_MFD ((unsigned int) 0x1 << 0) // (EMAC) -#define AT91C_EMAC_RCOMP ((unsigned int) 0x1 << 1) // (EMAC) -#define AT91C_EMAC_RXUBR ((unsigned int) 0x1 << 2) // (EMAC) -#define AT91C_EMAC_TXUBR ((unsigned int) 0x1 << 3) // (EMAC) -#define AT91C_EMAC_TUNDR ((unsigned int) 0x1 << 4) // (EMAC) -#define AT91C_EMAC_RLEX ((unsigned int) 0x1 << 5) // (EMAC) -#define AT91C_EMAC_TXERR ((unsigned int) 0x1 << 6) // (EMAC) -#define AT91C_EMAC_TCOMP ((unsigned int) 0x1 << 7) // (EMAC) -#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) // (EMAC) -#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) // (EMAC) -#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) // (EMAC) -#define AT91C_EMAC_PFRE ((unsigned int) 0x1 << 12) // (EMAC) -#define AT91C_EMAC_PTZ ((unsigned int) 0x1 << 13) // (EMAC) -// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- -// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- -// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- -// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- -#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) // (EMAC) -#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) // (EMAC) -#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) // (EMAC) -#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) // (EMAC) -#define AT91C_EMAC_SOF ((unsigned int) 0x3 << 30) // (EMAC) -// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- -#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 0) // (EMAC) Reduce MII -#define AT91C_EMAC_CLKEN ((unsigned int) 0x1 << 1) // (EMAC) Clock Enable -// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- -#define AT91C_EMAC_IP ((unsigned int) 0xFFFF << 0) // (EMAC) ARP request IP address -#define AT91C_EMAC_MAG ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable -#define AT91C_EMAC_ARP ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable -#define AT91C_EMAC_SA1 ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable -// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- -#define AT91C_EMAC_REVREF ((unsigned int) 0xFFFF << 0) // (EMAC) -#define AT91C_EMAC_PARTREF ((unsigned int) 0xFFFF << 16) // (EMAC) - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC -{ - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC , *AT91PS_ADC; - -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register -#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register -#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register -#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register -#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register -#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register -#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register -#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register -#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_RNPR ((AT91_REG *) 0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_TPR ((AT91_REG *) 0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_RPR ((AT91_REG *) 0xFFFE4100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_PTSR ((AT91_REG *) 0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register -#define AT91C_SPI1_RCR ((AT91_REG *) 0xFFFE4104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_TCR ((AT91_REG *) 0xFFFE410C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RNCR ((AT91_REG *) 0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_TNCR ((AT91_REG *) 0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TNPR ((AT91_REG *) 0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_PTCR ((AT91_REG *) 0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_CSR ((AT91_REG *) 0xFFFE4030) // (SPI1) Chip Select Register -#define AT91C_SPI1_IDR ((AT91_REG *) 0xFFFE4018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_SR ((AT91_REG *) 0xFFFE4010) // (SPI1) Status Register -#define AT91C_SPI1_RDR ((AT91_REG *) 0xFFFE4008) // (SPI1) Receive Data Register -#define AT91C_SPI1_CR ((AT91_REG *) 0xFFFE4000) // (SPI1) Control Register -#define AT91C_SPI1_IMR ((AT91_REG *) 0xFFFE401C) // (SPI1) Interrupt Mask Register -#define AT91C_SPI1_IER ((AT91_REG *) 0xFFFE4014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_TDR ((AT91_REG *) 0xFFFE400C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_MR ((AT91_REG *) 0xFFFE4004) // (SPI1) Mode Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register -#define AT91C_SPI0_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register -#define AT91C_SPI0_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI0) Receive Counter Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_CSR ((AT91_REG *) 0xFFFE0030) // (SPI0) Chip Select Register -#define AT91C_SPI0_IDR ((AT91_REG *) 0xFFFE0018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_SR ((AT91_REG *) 0xFFFE0010) // (SPI0) Status Register -#define AT91C_SPI0_RDR ((AT91_REG *) 0xFFFE0008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CR ((AT91_REG *) 0xFFFE0000) // (SPI0) Control Register -#define AT91C_SPI0_IMR ((AT91_REG *) 0xFFFE001C) // (SPI0) Interrupt Mask Register -#define AT91C_SPI0_IER ((AT91_REG *) 0xFFFE0014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_TDR ((AT91_REG *) 0xFFFE000C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_MR ((AT91_REG *) 0xFFFE0004) // (SPI0) Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for CAN_MB0 peripheral ========== -#define AT91C_CAN_MB0_MCR ((AT91_REG *) 0xFFFD021C) // (CAN_MB0) MailBox Control Register -#define AT91C_CAN_MB0_MDL ((AT91_REG *) 0xFFFD0214) // (CAN_MB0) MailBox Data Low Register -#define AT91C_CAN_MB0_MFID ((AT91_REG *) 0xFFFD020C) // (CAN_MB0) MailBox Family ID Register -#define AT91C_CAN_MB0_MAM ((AT91_REG *) 0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register -#define AT91C_CAN_MB0_MDH ((AT91_REG *) 0xFFFD0218) // (CAN_MB0) MailBox Data High Register -#define AT91C_CAN_MB0_MSR ((AT91_REG *) 0xFFFD0210) // (CAN_MB0) MailBox Status Register -#define AT91C_CAN_MB0_MID ((AT91_REG *) 0xFFFD0208) // (CAN_MB0) MailBox ID Register -#define AT91C_CAN_MB0_MMR ((AT91_REG *) 0xFFFD0200) // (CAN_MB0) MailBox Mode Register -// ========== Register definition for CAN_MB1 peripheral ========== -#define AT91C_CAN_MB1_MCR ((AT91_REG *) 0xFFFD023C) // (CAN_MB1) MailBox Control Register -#define AT91C_CAN_MB1_MDL ((AT91_REG *) 0xFFFD0234) // (CAN_MB1) MailBox Data Low Register -#define AT91C_CAN_MB1_MFID ((AT91_REG *) 0xFFFD022C) // (CAN_MB1) MailBox Family ID Register -#define AT91C_CAN_MB1_MAM ((AT91_REG *) 0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register -#define AT91C_CAN_MB1_MDH ((AT91_REG *) 0xFFFD0238) // (CAN_MB1) MailBox Data High Register -#define AT91C_CAN_MB1_MSR ((AT91_REG *) 0xFFFD0230) // (CAN_MB1) MailBox Status Register -#define AT91C_CAN_MB1_MID ((AT91_REG *) 0xFFFD0228) // (CAN_MB1) MailBox ID Register -#define AT91C_CAN_MB1_MMR ((AT91_REG *) 0xFFFD0220) // (CAN_MB1) MailBox Mode Register -// ========== Register definition for CAN_MB2 peripheral ========== -#define AT91C_CAN_MB2_MCR ((AT91_REG *) 0xFFFD025C) // (CAN_MB2) MailBox Control Register -#define AT91C_CAN_MB2_MDL ((AT91_REG *) 0xFFFD0254) // (CAN_MB2) MailBox Data Low Register -#define AT91C_CAN_MB2_MFID ((AT91_REG *) 0xFFFD024C) // (CAN_MB2) MailBox Family ID Register -#define AT91C_CAN_MB2_MAM ((AT91_REG *) 0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register -#define AT91C_CAN_MB2_MDH ((AT91_REG *) 0xFFFD0258) // (CAN_MB2) MailBox Data High Register -#define AT91C_CAN_MB2_MSR ((AT91_REG *) 0xFFFD0250) // (CAN_MB2) MailBox Status Register -#define AT91C_CAN_MB2_MID ((AT91_REG *) 0xFFFD0248) // (CAN_MB2) MailBox ID Register -#define AT91C_CAN_MB2_MMR ((AT91_REG *) 0xFFFD0240) // (CAN_MB2) MailBox Mode Register -// ========== Register definition for CAN_MB3 peripheral ========== -#define AT91C_CAN_MB3_MCR ((AT91_REG *) 0xFFFD027C) // (CAN_MB3) MailBox Control Register -#define AT91C_CAN_MB3_MDL ((AT91_REG *) 0xFFFD0274) // (CAN_MB3) MailBox Data Low Register -#define AT91C_CAN_MB3_MFID ((AT91_REG *) 0xFFFD026C) // (CAN_MB3) MailBox Family ID Register -#define AT91C_CAN_MB3_MAM ((AT91_REG *) 0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register -#define AT91C_CAN_MB3_MDH ((AT91_REG *) 0xFFFD0278) // (CAN_MB3) MailBox Data High Register -#define AT91C_CAN_MB3_MSR ((AT91_REG *) 0xFFFD0270) // (CAN_MB3) MailBox Status Register -#define AT91C_CAN_MB3_MID ((AT91_REG *) 0xFFFD0268) // (CAN_MB3) MailBox ID Register -#define AT91C_CAN_MB3_MMR ((AT91_REG *) 0xFFFD0260) // (CAN_MB3) MailBox Mode Register -// ========== Register definition for CAN_MB4 peripheral ========== -#define AT91C_CAN_MB4_MCR ((AT91_REG *) 0xFFFD029C) // (CAN_MB4) MailBox Control Register -#define AT91C_CAN_MB4_MDL ((AT91_REG *) 0xFFFD0294) // (CAN_MB4) MailBox Data Low Register -#define AT91C_CAN_MB4_MFID ((AT91_REG *) 0xFFFD028C) // (CAN_MB4) MailBox Family ID Register -#define AT91C_CAN_MB4_MAM ((AT91_REG *) 0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register -#define AT91C_CAN_MB4_MDH ((AT91_REG *) 0xFFFD0298) // (CAN_MB4) MailBox Data High Register -#define AT91C_CAN_MB4_MSR ((AT91_REG *) 0xFFFD0290) // (CAN_MB4) MailBox Status Register -#define AT91C_CAN_MB4_MID ((AT91_REG *) 0xFFFD0288) // (CAN_MB4) MailBox ID Register -#define AT91C_CAN_MB4_MMR ((AT91_REG *) 0xFFFD0280) // (CAN_MB4) MailBox Mode Register -// ========== Register definition for CAN_MB5 peripheral ========== -#define AT91C_CAN_MB5_MCR ((AT91_REG *) 0xFFFD02BC) // (CAN_MB5) MailBox Control Register -#define AT91C_CAN_MB5_MDL ((AT91_REG *) 0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register -#define AT91C_CAN_MB5_MFID ((AT91_REG *) 0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register -#define AT91C_CAN_MB5_MAM ((AT91_REG *) 0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register -#define AT91C_CAN_MB5_MDH ((AT91_REG *) 0xFFFD02B8) // (CAN_MB5) MailBox Data High Register -#define AT91C_CAN_MB5_MSR ((AT91_REG *) 0xFFFD02B0) // (CAN_MB5) MailBox Status Register -#define AT91C_CAN_MB5_MID ((AT91_REG *) 0xFFFD02A8) // (CAN_MB5) MailBox ID Register -#define AT91C_CAN_MB5_MMR ((AT91_REG *) 0xFFFD02A0) // (CAN_MB5) MailBox Mode Register -// ========== Register definition for CAN_MB6 peripheral ========== -#define AT91C_CAN_MB6_MAM ((AT91_REG *) 0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register -#define AT91C_CAN_MB6_MDH ((AT91_REG *) 0xFFFD02D8) // (CAN_MB6) MailBox Data High Register -#define AT91C_CAN_MB6_MSR ((AT91_REG *) 0xFFFD02D0) // (CAN_MB6) MailBox Status Register -#define AT91C_CAN_MB6_MID ((AT91_REG *) 0xFFFD02C8) // (CAN_MB6) MailBox ID Register -#define AT91C_CAN_MB6_MMR ((AT91_REG *) 0xFFFD02C0) // (CAN_MB6) MailBox Mode Register -#define AT91C_CAN_MB6_MCR ((AT91_REG *) 0xFFFD02DC) // (CAN_MB6) MailBox Control Register -#define AT91C_CAN_MB6_MDL ((AT91_REG *) 0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register -#define AT91C_CAN_MB6_MFID ((AT91_REG *) 0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register -// ========== Register definition for CAN_MB7 peripheral ========== -#define AT91C_CAN_MB7_MDH ((AT91_REG *) 0xFFFD02F8) // (CAN_MB7) MailBox Data High Register -#define AT91C_CAN_MB7_MSR ((AT91_REG *) 0xFFFD02F0) // (CAN_MB7) MailBox Status Register -#define AT91C_CAN_MB7_MID ((AT91_REG *) 0xFFFD02E8) // (CAN_MB7) MailBox ID Register -#define AT91C_CAN_MB7_MMR ((AT91_REG *) 0xFFFD02E0) // (CAN_MB7) MailBox Mode Register -#define AT91C_CAN_MB7_MCR ((AT91_REG *) 0xFFFD02FC) // (CAN_MB7) MailBox Control Register -#define AT91C_CAN_MB7_MDL ((AT91_REG *) 0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register -#define AT91C_CAN_MB7_MFID ((AT91_REG *) 0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register -#define AT91C_CAN_MB7_MAM ((AT91_REG *) 0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register -// ========== Register definition for CAN peripheral ========== -#define AT91C_CAN_IMR ((AT91_REG *) 0xFFFD000C) // (CAN) Interrupt Mask Register -#define AT91C_CAN_IER ((AT91_REG *) 0xFFFD0004) // (CAN) Interrupt Enable Register -#define AT91C_CAN_ECR ((AT91_REG *) 0xFFFD0020) // (CAN) Error Counter Register -#define AT91C_CAN_TIM ((AT91_REG *) 0xFFFD0018) // (CAN) Timer Register -#define AT91C_CAN_SR ((AT91_REG *) 0xFFFD0010) // (CAN) Status Register -#define AT91C_CAN_IDR ((AT91_REG *) 0xFFFD0008) // (CAN) Interrupt Disable Register -#define AT91C_CAN_MR ((AT91_REG *) 0xFFFD0000) // (CAN) Mode Register -#define AT91C_CAN_BR ((AT91_REG *) 0xFFFD0014) // (CAN) Baudrate Register -#define AT91C_CAN_TIMESTP ((AT91_REG *) 0xFFFD001C) // (CAN) Time Stamp Register -#define AT91C_CAN_TCR ((AT91_REG *) 0xFFFD0024) // (CAN) Transfer Command Register -#define AT91C_CAN_ACR ((AT91_REG *) 0xFFFD0028) // (CAN) Abort Command Register -#define AT91C_CAN_VR ((AT91_REG *) 0xFFFD00FC) // (CAN) Version Register -// ========== Register definition for EMAC peripheral ========== -#define AT91C_EMAC_TID ((AT91_REG *) 0xFFFDC0B8) // (EMAC) Type ID Checking Register -#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMAC_STE ((AT91_REG *) 0xFFFDC084) // (EMAC) SQE Test Error Register -#define AT91C_EMAC_RSE ((AT91_REG *) 0xFFFDC074) // (EMAC) Receive Symbol Errors Register -#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFDC02C) // (EMAC) Interrupt Disable Register -#define AT91C_EMAC_TBQP ((AT91_REG *) 0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer -#define AT91C_EMAC_TPQ ((AT91_REG *) 0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register -#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMAC_RLE ((AT91_REG *) 0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register -#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFDC030) // (EMAC) Interrupt Mask Register -#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMAC_PFR ((AT91_REG *) 0xFFFDC03C) // (EMAC) Pause Frames received Register -#define AT91C_EMAC_FCSE ((AT91_REG *) 0xFFFDC050) // (EMAC) Frame Check Sequence Error Register -#define AT91C_EMAC_FTO ((AT91_REG *) 0xFFFDC040) // (EMAC) Frames Transmitted OK Register -#define AT91C_EMAC_TUND ((AT91_REG *) 0xFFFDC064) // (EMAC) Transmit Underrun Error Register -#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFDC054) // (EMAC) Alignment Error Register -#define AT91C_EMAC_SCF ((AT91_REG *) 0xFFFDC044) // (EMAC) Single Collision Frame Register -#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMAC_ELE ((AT91_REG *) 0xFFFDC078) // (EMAC) Excessive Length Errors Register -#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFDC068) // (EMAC) Carrier Sense Error Register -#define AT91C_EMAC_DTF ((AT91_REG *) 0xFFFDC058) // (EMAC) Deferred Transmission Frame Register -#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFDC020) // (EMAC) Receive Status Register -#define AT91C_EMAC_USRIO ((AT91_REG *) 0xFFFDC0C0) // (EMAC) USER Input/Output Register -#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMAC_RRE ((AT91_REG *) 0xFFFDC06C) // (EMAC) Receive Ressource Error Register -#define AT91C_EMAC_RJA ((AT91_REG *) 0xFFFDC07C) // (EMAC) Receive Jabbers Register -#define AT91C_EMAC_TPF ((AT91_REG *) 0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register -#define AT91C_EMAC_ISR ((AT91_REG *) 0xFFFDC024) // (EMAC) Interrupt Status Register -#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFDC034) // (EMAC) PHY Maintenance Register -#define AT91C_EMAC_WOL ((AT91_REG *) 0xFFFDC0C4) // (EMAC) Wake On LAN Register -#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFDC080) // (EMAC) Undersize Frames Register -#define AT91C_EMAC_HRB ((AT91_REG *) 0xFFFDC090) // (EMAC) Hash Address Bottom[31:0] -#define AT91C_EMAC_PTR ((AT91_REG *) 0xFFFDC038) // (EMAC) Pause Time Register -#define AT91C_EMAC_HRT ((AT91_REG *) 0xFFFDC094) // (EMAC) Hash Address Top[63:32] -#define AT91C_EMAC_REV ((AT91_REG *) 0xFFFDC0FC) // (EMAC) Revision Register -#define AT91C_EMAC_MCF ((AT91_REG *) 0xFFFDC048) // (EMAC) Multiple Collision Frame Register -#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMAC_NCR ((AT91_REG *) 0xFFFDC000) // (EMAC) Network Control Register -#define AT91C_EMAC_FRO ((AT91_REG *) 0xFFFDC04C) // (EMAC) Frames Received OK Register -#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFDC05C) // (EMAC) Late Collision Register -#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMAC_NCFGR ((AT91_REG *) 0xFFFDC004) // (EMAC) Network Configuration Register -#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFDC014) // (EMAC) Transmit Status Register -#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFDC060) // (EMAC) Excessive Collision Register -#define AT91C_EMAC_ROV ((AT91_REG *) 0xFFFDC070) // (EMAC) Receive Overrun Errors Register -#define AT91C_EMAC_NSR ((AT91_REG *) 0xFFFDC008) // (EMAC) Network Status Register -#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer -#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFDC028) // (EMAC) Interrupt Enable Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_RXD0 ((unsigned int) AT91C_PIO_PA0) // USART 0 Receive Data -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_TXD0 ((unsigned int) AT91C_PIO_PA1) // USART 0 Transmit Data -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_TWD ((unsigned int) AT91C_PIO_PA10) // TWI Two-wire Serial Data -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_TWCK ((unsigned int) AT91C_PIO_PA11) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_SPI0_NPCS0 ((unsigned int) AT91C_PIO_PA12) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PA13_PCK1 ((unsigned int) AT91C_PIO_PA13) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PA14_IRQ1 ((unsigned int) AT91C_PIO_PA14) // External Interrupt 1 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA15) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PA15_TCLK2 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 2 external clock input -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_SPI0_MISO ((unsigned int) AT91C_PIO_PA16) // SPI 0 Master In Slave -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_SPI0_MOSI ((unsigned int) AT91C_PIO_PA17) // SPI 0 Master Out Slave -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_SPI0_SPCK ((unsigned int) AT91C_PIO_PA18) // SPI 0 Serial Clock -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_CANRX ((unsigned int) AT91C_PIO_PA19) // CAN Receive -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PA2_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA2) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_CANTX ((unsigned int) AT91C_PIO_PA20) // CAN Transmit -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TF ((unsigned int) AT91C_PIO_PA21) // SSC Transmit Frame Sync -#define AT91C_PA21_SPI1_NPCS0 ((unsigned int) AT91C_PIO_PA21) // SPI 1 Peripheral Chip Select 0 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TK ((unsigned int) AT91C_PIO_PA22) // SSC Transmit Clock -#define AT91C_PA22_SPI1_SPCK ((unsigned int) AT91C_PIO_PA22) // SPI 1 Serial Clock -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_TD ((unsigned int) AT91C_PIO_PA23) // SSC Transmit data -#define AT91C_PA23_SPI1_MOSI ((unsigned int) AT91C_PIO_PA23) // SPI 1 Master Out Slave -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RD ((unsigned int) AT91C_PIO_PA24) // SSC Receive Data -#define AT91C_PA24_SPI1_MISO ((unsigned int) AT91C_PIO_PA24) // SPI 1 Master In Slave -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_RK ((unsigned int) AT91C_PIO_PA25) // SSC Receive Clock -#define AT91C_PA25_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PA25) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_RF ((unsigned int) AT91C_PIO_PA26) // SSC Receive Frame Sync -#define AT91C_PA26_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA26) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DRXD ((unsigned int) AT91C_PIO_PA27) // DBGU Debug Receive Data -#define AT91C_PA27_PCK3 ((unsigned int) AT91C_PIO_PA27) // PMC Programmable Clock Output 3 -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DTXD ((unsigned int) AT91C_PIO_PA28) // DBGU Debug Transmit Data -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_FIQ ((unsigned int) AT91C_PIO_PA29) // AIC Fast Interrupt Input -#define AT91C_PA29_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA29) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_RTS0 ((unsigned int) AT91C_PIO_PA3) // USART 0 Ready To Send -#define AT91C_PA3_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PA3) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ0 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 0 -#define AT91C_PA30_PCK2 ((unsigned int) AT91C_PIO_PA30) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_CTS0 ((unsigned int) AT91C_PIO_PA4) // USART 0 Clear To Send -#define AT91C_PA4_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PA4) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD1 ((unsigned int) AT91C_PIO_PA5) // USART 1 Receive Data -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD1 ((unsigned int) AT91C_PIO_PA6) // USART 1 Transmit Data -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_SCK1 ((unsigned int) AT91C_PIO_PA7) // USART 1 Serial Clock -#define AT91C_PA7_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PA7) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_RTS1 ((unsigned int) AT91C_PIO_PA8) // USART 1 Ready To Send -#define AT91C_PA8_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PA8) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_CTS1 ((unsigned int) AT91C_PIO_PA9) // USART 1 Clear To Send -#define AT91C_PA9_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PA9) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB0 ((unsigned int) 1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PB0_PCK0 ((unsigned int) AT91C_PIO_PB0) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_ETXEN ((unsigned int) AT91C_PIO_PB1) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_ETX2 ((unsigned int) AT91C_PIO_PB10) // Ethernet MAC Transmit Data 2 -#define AT91C_PB10_SPI1_NPCS1 ((unsigned int) AT91C_PIO_PB10) // SPI 1 Peripheral Chip Select 1 -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_ETX3 ((unsigned int) AT91C_PIO_PB11) // Ethernet MAC Transmit Data 3 -#define AT91C_PB11_SPI1_NPCS2 ((unsigned int) AT91C_PIO_PB11) // SPI 1 Peripheral Chip Select 2 -#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_ETXER ((unsigned int) AT91C_PIO_PB12) // Ethernet MAC Transmikt Coding Error -#define AT91C_PB12_TCLK0 ((unsigned int) AT91C_PIO_PB12) // Timer Counter 0 external clock input -#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_ERX2 ((unsigned int) AT91C_PIO_PB13) // Ethernet MAC Receive Data 2 -#define AT91C_PB13_SPI0_NPCS1 ((unsigned int) AT91C_PIO_PB13) // SPI 0 Peripheral Chip Select 1 -#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_ERX3 ((unsigned int) AT91C_PIO_PB14) // Ethernet MAC Receive Data 3 -#define AT91C_PB14_SPI0_NPCS2 ((unsigned int) AT91C_PIO_PB14) // SPI 0 Peripheral Chip Select 2 -#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_ERXDV_ECRSDV ((unsigned int) AT91C_PIO_PB15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_ECOL ((unsigned int) AT91C_PIO_PB16) // Ethernet MAC Collision Detected -#define AT91C_PB16_SPI1_NPCS3 ((unsigned int) AT91C_PIO_PB16) // SPI 1 Peripheral Chip Select 3 -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_ERXCK ((unsigned int) AT91C_PIO_PB17) // Ethernet MAC Receive Clock -#define AT91C_PB17_SPI0_NPCS3 ((unsigned int) AT91C_PIO_PB17) // SPI 0 Peripheral Chip Select 3 -#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_EF100 ((unsigned int) AT91C_PIO_PB18) // Ethernet MAC Force 100 Mbits/sec -#define AT91C_PB18_ADTRG ((unsigned int) AT91C_PIO_PB18) // ADC External Trigger -#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_PWM0 ((unsigned int) AT91C_PIO_PB19) // PWM Channel 0 -#define AT91C_PB19_TCLK1 ((unsigned int) AT91C_PIO_PB19) // Timer Counter 1 external clock input -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_ETX0 ((unsigned int) AT91C_PIO_PB2) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_PWM1 ((unsigned int) AT91C_PIO_PB20) // PWM Channel 1 -#define AT91C_PB20_PCK0 ((unsigned int) AT91C_PIO_PB20) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_PWM2 ((unsigned int) AT91C_PIO_PB21) // PWM Channel 2 -#define AT91C_PB21_PCK1 ((unsigned int) AT91C_PIO_PB21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_PWM3 ((unsigned int) AT91C_PIO_PB22) // PWM Channel 3 -#define AT91C_PB22_PCK2 ((unsigned int) AT91C_PIO_PB22) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PB23 ((unsigned int) 1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_TIOA0 ((unsigned int) AT91C_PIO_PB23) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PB23_DCD1 ((unsigned int) AT91C_PIO_PB23) // USART 1 Data Carrier Detect -#define AT91C_PIO_PB24 ((unsigned int) 1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_TIOB0 ((unsigned int) AT91C_PIO_PB24) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PB24_DSR1 ((unsigned int) AT91C_PIO_PB24) // USART 1 Data Set ready -#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_TIOA1 ((unsigned int) AT91C_PIO_PB25) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PB25_DTR1 ((unsigned int) AT91C_PIO_PB25) // USART 1 Data Terminal ready -#define AT91C_PIO_PB26 ((unsigned int) 1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_TIOB1 ((unsigned int) AT91C_PIO_PB26) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PB26_RI1 ((unsigned int) AT91C_PIO_PB26) // USART 1 Ring Indicator -#define AT91C_PIO_PB27 ((unsigned int) 1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_TIOA2 ((unsigned int) AT91C_PIO_PB27) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PB27_PWM0 ((unsigned int) AT91C_PIO_PB27) // PWM Channel 0 -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_TIOB2 ((unsigned int) AT91C_PIO_PB28) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PB28_PWM1 ((unsigned int) AT91C_PIO_PB28) // PWM Channel 1 -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_PCK1 ((unsigned int) AT91C_PIO_PB29) // PMC Programmable Clock Output 1 -#define AT91C_PB29_PWM2 ((unsigned int) AT91C_PIO_PB29) // PWM Channel 2 -#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_ETX1 ((unsigned int) AT91C_PIO_PB3) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PB30 ((unsigned int) 1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_PCK2 ((unsigned int) AT91C_PIO_PB30) // PMC Programmable Clock Output 2 -#define AT91C_PB30_PWM3 ((unsigned int) AT91C_PIO_PB30) // PWM Channel 3 -#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_ECRS ((unsigned int) AT91C_PIO_PB4) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_ERX0 ((unsigned int) AT91C_PIO_PB5) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_ERX1 ((unsigned int) AT91C_PIO_PB6) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_ERXER ((unsigned int) AT91C_PIO_PB7) // Ethernet MAC Receive Error -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_EMDC ((unsigned int) AT91C_PIO_PB8) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_EMDIO ((unsigned int) AT91C_PIO_PB9) // Ethernet MAC Management Data Input/Output - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ((unsigned int) 3) // Parallel IO Controller B -#define AT91C_ID_SPI0 ((unsigned int) 4) // Serial Peripheral Interface 0 -#define AT91C_ID_SPI1 ((unsigned int) 5) // Serial Peripheral Interface 1 -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_CAN ((unsigned int) 15) // Control Area Network Controller -#define AT91C_ID_EMAC ((unsigned int) 16) // Ethernet MAC -#define AT91C_ID_ADC ((unsigned int) 17) // Analog-to-Digital Converter -#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved -#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ALL_INT ((unsigned int) 0xC003FFFF) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI1 ((AT91PS_PDC) 0xFFFE4100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI1 ((AT91PS_SPI) 0xFFFE4000) // (SPI1) Base Address -#define AT91C_BASE_PDC_SPI0 ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI0) Base Address -#define AT91C_BASE_SPI0 ((AT91PS_SPI) 0xFFFE0000) // (SPI0) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_CAN_MB0 ((AT91PS_CAN_MB) 0xFFFD0200) // (CAN_MB0) Base Address -#define AT91C_BASE_CAN_MB1 ((AT91PS_CAN_MB) 0xFFFD0220) // (CAN_MB1) Base Address -#define AT91C_BASE_CAN_MB2 ((AT91PS_CAN_MB) 0xFFFD0240) // (CAN_MB2) Base Address -#define AT91C_BASE_CAN_MB3 ((AT91PS_CAN_MB) 0xFFFD0260) // (CAN_MB3) Base Address -#define AT91C_BASE_CAN_MB4 ((AT91PS_CAN_MB) 0xFFFD0280) // (CAN_MB4) Base Address -#define AT91C_BASE_CAN_MB5 ((AT91PS_CAN_MB) 0xFFFD02A0) // (CAN_MB5) Base Address -#define AT91C_BASE_CAN_MB6 ((AT91PS_CAN_MB) 0xFFFD02C0) // (CAN_MB6) Base Address -#define AT91C_BASE_CAN_MB7 ((AT91PS_CAN_MB) 0xFFFD02E0) // (CAN_MB7) Base Address -#define AT91C_BASE_CAN ((AT91PS_CAN) 0xFFFD0000) // (CAN) Base Address -#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFDC000) // (EMAC) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbytes) -// IFLASH -#define AT91C_IFLASH ((char *) 0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal FLASH size in byte (256 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE ((unsigned int) 256) // Internal FLASH Page Size: 256 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE ((unsigned int) 16384) // Internal FLASH Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES ((unsigned int) 1024) // Internal FLASH Number of Pages: 1024 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS ((unsigned int) 16) // Internal FLASH Number of Lock Bits: 16 bytes - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/AT91SAM7_target.js b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/AT91SAM7_target.js deleted file mode 100644 index 3fc546e19..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/AT91SAM7_target.js +++ /dev/null @@ -1,64 +0,0 @@ -/****************************************************************************** - Target Script for Atmel AT91SAM7. - - Copyright (c) 2007 Rowley Associates Limited. - - This file may be distributed under the terms of the License Agreement - provided with this software. - - THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE - WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. - ******************************************************************************/ - -function Reset() -{ - /* Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF; */ - TargetInterface.pokeWord(0xffffffff,0xFFFFF124); - TargetInterface.pokeWord(0xffffffff,0xFFFFF128); - /* disable peripheral clock Peripheral Clock Disable Register */ - TargetInterface.pokeWord(0xffffffff,0xFFFFFC14); - - /* Reset and stop target */ - TargetInterface.stopAndReset(1); - - CKGR_MOR_VAL = 0x00004001; - CKGR_PLLR_VAL = 0x10483F0E; /* Set up the PLL (MCK, UDPCK = 18.432MHz * 73 / 14 / 2 = 48.05486MHz) */ - CKGR_MCKR_VAL1 = 0x00000004; - CKGR_MCKR_VAL2 = 0x00000007; - - if (TargetInterface.setMaximumJTAGFrequency) - { - /* Configure Clock (post 1.6 version) */ - TargetInterface.setMaximumJTAGFrequency(32768); - TargetInterface.pokeWord(0xFFFFFC20, CKGR_MOR_VAL); - TargetInterface.pokeWord(0xFFFFFC2C, CKGR_PLLR_VAL); - TargetInterface.pokeWord(0xFFFFFC30, CKGR_MCKR_VAL1); - TargetInterface.pokeWord(0xFFFFFC30, CKGR_MCKR_VAL2); - TargetInterface.setMaximumJTAGFrequency(10000000); - } - else - { - /* Configure Clock (1.6 version) */ - TargetInterface.pokeWord(0xFFFFFC20, CKGR_MOR_VAL); - TargetInterface.delay(10); - TargetInterface.pokeWord(0xFFFFFC2C, CKGR_PLLR_VAL); - TargetInterface.delay(10); - TargetInterface.pokeWord(0xFFFFFC30, CKGR_MCKR_VAL1); - TargetInterface.delay(10); - TargetInterface.pokeWord(0xFFFFFC30, CKGR_MCKR_VAL2); - TargetInterface.delay(10); - } -} - -function RAMReset() -{ - Reset(); - /* Remap SRAM to 0x00000000 */ - TargetInterface.pokeWord(0xFFFFFF00, 1); // MC_RCR -} - -function FLASHReset() -{ - Reset(); -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/lib_AT91SAM7X256.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/lib_AT91SAM7X256.h deleted file mode 100644 index 69c2a0b2e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/support/lib_AT91SAM7X256.h +++ /dev/null @@ -1,4119 +0,0 @@ -//* ---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//* ---------------------------------------------------------------------------- -//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//* ---------------------------------------------------------------------------- -//* File Name : lib_AT91SAM7X256.h -//* Object : AT91SAM7X256 inlined functions -//* Generated : AT91 SW Application Group 01/16/2006 (16:36:21) -//* -//* CVS Reference : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004// -//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// -//* CVS Reference : /lib_dbgu.h/1.1/Thu Aug 25 12:56:22 2005// -//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// -//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// -//* CVS Reference : /lib_spi2.h/1.2/Tue Aug 23 15:37:28 2005// -//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// -//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// -//* CVS Reference : /lib_pmc_SAM7X.h/1.5/Fri Nov 4 09:41:32 2005// -//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// -//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// -//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// -//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// -//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// -//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// -//* CVS Reference : /lib_udp.h/1.5/Tue Aug 30 12:13:47 2005// -//* CVS Reference : /lib_aic_6075b.h/1.2/Thu Jul 7 07:48:22 2005// -//* CVS Reference : /lib_can_AT91.h/1.5/Tue Aug 23 15:37:07 2005// -//* ---------------------------------------------------------------------------- - -#ifndef lib_AT91SAM7X256_H -#define lib_AT91SAM7X256_H - -#include "AT91SAM7X256.h" - -/* ***************************************************************************** - SOFTWARE API FOR AIC - ***************************************************************************** */ -#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ConfigureIt -//* \brief Interrupt Handler Initialization -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_AIC_ConfigureIt( AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id, // \arg interrupt number to initialize - unsigned int priority, // \arg priority to give to the interrupt - unsigned int src_type, // \arg activation and sense of activation - void ( *newHandler ) ( ) ) // \arg address of the interrupt handler -{ - unsigned int oldHandler; - unsigned int mask; - - oldHandler = pAic->AIC_SVR[irq_id]; - - mask = 0x1 << irq_id; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask; - //* Save the interrupt handler routine pointer and the interrupt priority - pAic->AIC_SVR[irq_id] = ( unsigned int )newHandler; - //* Store the Source Mode Register - pAic->AIC_SMR[irq_id] = src_type | priority; - //* Clear the interrupt on the interrupt controller - pAic->AIC_ICCR = mask; - - return oldHandler; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_EnableIt -//* \brief Enable corresponding IT number -//*---------------------------------------------------------------------------- -static __inline void -AT91F_AIC_EnableIt( AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - //* Enable the interrupt on the interrupt controller - pAic->AIC_IECR = 0x1 << irq_id; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_DisableIt -//* \brief Disable corresponding IT number -//*---------------------------------------------------------------------------- -static __inline void -AT91F_AIC_DisableIt( AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - unsigned int mask = 0x1 << irq_id; - - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask; - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = mask; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ClearIt -//* \brief Clear corresponding IT number -//*---------------------------------------------------------------------------- -static __inline void -AT91F_AIC_ClearIt( AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = ( 0x1 << irq_id ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_AcknowledgeIt -//* \brief Acknowledge corresponding IT number -//*---------------------------------------------------------------------------- -static __inline void -AT91F_AIC_AcknowledgeIt( AT91PS_AIC pAic ) // \arg pointer to the AIC registers -{ - pAic->AIC_EOICR = pAic->AIC_EOICR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_SetExceptionVector -//* \brief Configure vector handler -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_AIC_SetExceptionVector( unsigned int *pVector, // \arg pointer to the AIC registers - void ( *Handler ) ( ) ) // \arg Interrupt Handler -{ - unsigned int oldVector = *pVector; - - if( ( unsigned int )Handler == ( unsigned int )AT91C_AIC_BRANCH_OPCODE ) - *pVector = ( unsigned int )AT91C_AIC_BRANCH_OPCODE; - else - *pVector = - ( ( ( ( ( unsigned int )Handler ) - ( ( unsigned int )pVector ) - 0x8 ) >> 2 ) & 0x00FFFFFF ) | 0xEA000000; - - return oldVector; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Trig -//* \brief Trig an IT -//*---------------------------------------------------------------------------- -static __inline void -AT91F_AIC_Trig( AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number -{ - pAic->AIC_ISCR = ( 0x1 << irq_id ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsActive -//* \brief Test if an IT is active -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_AIC_IsActive( AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg Interrupt Number -{ - return ( pAic->AIC_ISR & ( 0x1 << irq_id ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsPending -//* \brief Test if an IT is pending -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_AIC_IsPending( AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg Interrupt Number -{ - return ( pAic->AIC_IPR & ( 0x1 << irq_id ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Open -//* \brief Set exception vectors and AIC registers to default values -//*---------------------------------------------------------------------------- -static __inline void -AT91F_AIC_Open( AT91PS_AIC pAic, // \arg pointer to the AIC registers - void ( *IrqHandler ) ( ), // \arg Default IRQ vector exception - void ( *FiqHandler ) ( ), // \arg Default FIQ vector exception - void ( *DefaultHandler ) ( ), // \arg Default Handler set in ISR - void ( *SpuriousHandler ) ( ), // \arg Default Spurious Handler - unsigned int protectMode ) // \arg Debug Control Register -{ - int i; - - // Disable all interrupts and set IVR to the default handler - for( i = 0; i < 32; ++i ) - { - AT91F_AIC_DisableIt( pAic, i ); - AT91F_AIC_ConfigureIt( pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler ); - } - - // Set the IRQ exception vector - AT91F_AIC_SetExceptionVector( ( unsigned int * )0x18, IrqHandler ); - // Set the Fast Interrupt exception vector - AT91F_AIC_SetExceptionVector( ( unsigned int * )0x1C, FiqHandler ); - - pAic->AIC_SPU = ( unsigned int )SpuriousHandler; - pAic->AIC_DCR = protectMode; -} - -/* ***************************************************************************** - SOFTWARE API FOR PDC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextRx -//* \brief Set the next receive transfer descriptor -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes ) // \arg number of bytes to be received -{ - pPDC->PDC_RNPR = ( unsigned int )address; - pPDC->PDC_RNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextTx -//* \brief Set the next transmit transfer descriptor -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes ) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TNPR = ( unsigned int )address; - pPDC->PDC_TNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetRx -//* \brief Set the receive transfer descriptor -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PDC_SetRx( AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes ) // \arg number of bytes to be received -{ - pPDC->PDC_RPR = ( unsigned int )address; - pPDC->PDC_RCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetTx -//* \brief Set the transmit transfer descriptor -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PDC_SetTx( AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes ) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TPR = ( unsigned int )address; - pPDC->PDC_TCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableTx -//* \brief Enable transmit -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PDC_EnableTx( AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableRx -//* \brief Enable receive -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PDC_EnableRx( AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableTx -//* \brief Disable transmit -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PDC_DisableTx( AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableRx -//* \brief Disable receive -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PDC_DisableRx( AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsTxEmpty -//* \brief Test if the current transfer descriptor has been sent -//*---------------------------------------------------------------------------- -static __inline int -AT91F_PDC_IsTxEmpty( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !( pPDC->PDC_TCR ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextTxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -static __inline int -AT91F_PDC_IsNextTxEmpty( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !( pPDC->PDC_TNCR ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsRxEmpty -//* \brief Test if the current transfer descriptor has been filled -//*---------------------------------------------------------------------------- -static __inline int -AT91F_PDC_IsRxEmpty( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !( pPDC->PDC_RCR ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextRxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -static __inline int -AT91F_PDC_IsNextRxEmpty( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !( pPDC->PDC_RNCR ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Open -//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PDC_Open( AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx( pPDC ); - AT91F_PDC_DisableTx( pPDC ); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx( pPDC, ( char * )0, 0 ); - AT91F_PDC_SetNextRx( pPDC, ( char * )0, 0 ); - AT91F_PDC_SetTx( pPDC, ( char * )0, 0 ); - AT91F_PDC_SetRx( pPDC, ( char * )0, 0 ); - - //* Enable the RX and TX PDC transfer requests - AT91F_PDC_EnableRx( pPDC ); - AT91F_PDC_EnableTx( pPDC ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Close -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PDC_Close( AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx( pPDC ); - AT91F_PDC_DisableTx( pPDC ); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx( pPDC, ( char * )0, 0 ); - AT91F_PDC_SetNextRx( pPDC, ( char * )0, 0 ); - AT91F_PDC_SetTx( pPDC, ( char * )0, 0 ); - AT91F_PDC_SetRx( pPDC, ( char * )0, 0 ); - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SendFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PDC_SendFrame( AT91PS_PDC pPDC, - char *pBuffer, unsigned int szBuffer, char *pNextBuffer, unsigned int szNextBuffer ) -{ - if( AT91F_PDC_IsTxEmpty( pPDC ) ) - { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetTx( pPDC, pBuffer, szBuffer ); - AT91F_PDC_SetNextTx( pPDC, pNextBuffer, szNextBuffer ); - return 2; - } - else if( AT91F_PDC_IsNextTxEmpty( pPDC ) ) - { - //* Only one buffer can be initialized - AT91F_PDC_SetNextTx( pPDC, pBuffer, szBuffer ); - return 1; - } - else - { - //* All buffer are in use... - return 0; - } -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_ReceiveFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PDC_ReceiveFrame( AT91PS_PDC pPDC, - char *pBuffer, unsigned int szBuffer, char *pNextBuffer, unsigned int szNextBuffer ) -{ - if( AT91F_PDC_IsRxEmpty( pPDC ) ) - { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetRx( pPDC, pBuffer, szBuffer ); - AT91F_PDC_SetNextRx( pPDC, pNextBuffer, szNextBuffer ); - return 2; - } - else if( AT91F_PDC_IsNextRxEmpty( pPDC ) ) - { - //* Only one buffer can be initialized - AT91F_PDC_SetNextRx( pPDC, pBuffer, szBuffer ); - return 1; - } - else - { - //* All buffer are in use... - return 0; - } -} - -/* ***************************************************************************** - SOFTWARE API FOR DBGU - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptEnable -//* \brief Enable DBGU Interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_DBGU_InterruptEnable( AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag ) // \arg dbgu interrupt to be enabled -{ - pDbgu->DBGU_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptDisable -//* \brief Disable DBGU Interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_DBGU_InterruptDisable( AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag ) // \arg dbgu interrupt to be disabled -{ - pDbgu->DBGU_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_GetInterruptMaskStatus -//* \brief Return DBGU Interrupt Mask Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status - AT91PS_DBGU pDbgu ) // \arg pointer to a DBGU controller -{ - return pDbgu->DBGU_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_IsInterruptMasked -//* \brief Test if DBGU Interrupt is Masked -//*---------------------------------------------------------------------------- -static __inline int -AT91F_DBGU_IsInterruptMasked( AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_DBGU_GetInterruptMaskStatus( pDbgu ) & flag ); -} - -/* ***************************************************************************** - SOFTWARE API FOR PIO - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPeriph -//* \brief Enable pins to be drived by peripheral -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_CfgPeriph( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int periphAEnable, // \arg PERIPH A to enable - unsigned int periphBEnable ) // \arg PERIPH B to enable -{ - pPio->PIO_ASR = periphAEnable; - pPio->PIO_BSR = periphBEnable; - pPio->PIO_PDR = ( periphAEnable | periphBEnable ); // Set in Periph mode -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOutput -//* \brief Enable PIO in output mode -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_CfgOutput( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pioEnable ) // \arg PIO to be enabled -{ - pPio->PIO_PER = pioEnable; // Set in PIO mode - pPio->PIO_OER = pioEnable; // Configure in Output -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInput -//* \brief Enable PIO in input mode -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_CfgInput( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputEnable ) // \arg PIO to be enabled -{ - // Disable output - pPio->PIO_ODR = inputEnable; - pPio->PIO_PER = inputEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOpendrain -//* \brief Configure PIO in open drain -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_CfgOpendrain( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int multiDrvEnable ) // \arg pio to be configured in open drain -{ - // Configure the multi-drive option - pPio->PIO_MDDR = ~multiDrvEnable; - pPio->PIO_MDER = multiDrvEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPullup -//* \brief Enable pullup on PIO -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_CfgPullup( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pullupEnable ) // \arg enable pullup on PIO -{ - // Connect or not Pullup - pPio->PIO_PPUDR = ~pullupEnable; - pPio->PIO_PPUER = pullupEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgDirectDrive -//* \brief Enable direct drive on PIO -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_CfgDirectDrive( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int directDrive ) // \arg PIO to be configured with direct drive -{ - // Configure the Direct Drive - pPio->PIO_OWDR = ~directDrive; - pPio->PIO_OWER = directDrive; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInputFilter -//* \brief Enable input filter on input PIO -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_CfgInputFilter( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputFilter ) // \arg PIO to be configured with input filter -{ - // Configure the Direct Drive - pPio->PIO_IFDR = ~inputFilter; - pPio->PIO_IFER = inputFilter; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInput -//* \brief Return PIO input value -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PIO_GetInput( // \return PIO input - AT91PS_PIO pPio ) // \arg pointer to a PIO controller -{ - return pPio->PIO_PDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputSet -//* \brief Test if PIO is input flag is active -//*---------------------------------------------------------------------------- -static __inline int -AT91F_PIO_IsInputSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_PIO_GetInput( pPio ) & flag ); -} - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_SetOutput -//* \brief Set to 1 output PIO -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_SetOutput( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg output to be set -{ - pPio->PIO_SODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ClearOutput -//* \brief Set to 0 output PIO -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_ClearOutput( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg output to be cleared -{ - pPio->PIO_CODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ForceOutput -//* \brief Force output when Direct drive option is enabled -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_ForceOutput( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg output to be forced -{ - pPio->PIO_ODSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Enable -//* \brief Enable PIO -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_Enable( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg pio to be enabled -{ - pPio->PIO_PER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Disable -//* \brief Disable PIO -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_Disable( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg pio to be disabled -{ - pPio->PIO_PDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetStatus -//* \brief Return PIO Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PIO_GetStatus( // \return PIO Status - AT91PS_PIO pPio ) // \arg pointer to a PIO controller -{ - return pPio->PIO_PSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsSet -//* \brief Test if PIO is Set -//*---------------------------------------------------------------------------- -static __inline int -AT91F_PIO_IsSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_PIO_GetStatus( pPio ) & flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputEnable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_OutputEnable( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg pio output to be enabled -{ - pPio->PIO_OER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputDisable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_OutputDisable( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg pio output to be disabled -{ - pPio->PIO_ODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputStatus -//* \brief Return PIO Output Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PIO_GetOutputStatus( // \return PIO Output Status - AT91PS_PIO pPio ) // \arg pointer to a PIO controller -{ - return pPio->PIO_OSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOuputSet -//* \brief Test if PIO Output is Set -//*---------------------------------------------------------------------------- -static __inline int -AT91F_PIO_IsOutputSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_PIO_GetOutputStatus( pPio ) & flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterEnable -//* \brief Input Filter Enable PIO -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_InputFilterEnable( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg pio input filter to be enabled -{ - pPio->PIO_IFER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterDisable -//* \brief Input Filter Disable PIO -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_InputFilterDisable( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg pio input filter to be disabled -{ - pPio->PIO_IFDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInputFilterStatus -//* \brief Return PIO Input Filter Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status - AT91PS_PIO pPio ) // \arg pointer to a PIO controller -{ - return pPio->PIO_IFSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputFilterSet -//* \brief Test if PIO Input filter is Set -//*---------------------------------------------------------------------------- -static __inline int -AT91F_PIO_IsInputFilterSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_PIO_GetInputFilterStatus( pPio ) & flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputDataStatus -//* \brief Return PIO Output Data Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status - AT91PS_PIO pPio ) // \arg pointer to a PIO controller -{ - return pPio->PIO_ODSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptEnable -//* \brief Enable PIO Interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_InterruptEnable( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg pio interrupt to be enabled -{ - pPio->PIO_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptDisable -//* \brief Disable PIO Interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_InterruptDisable( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg pio interrupt to be disabled -{ - pPio->PIO_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptMaskStatus -//* \brief Return PIO Interrupt Mask Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status - AT91PS_PIO pPio ) // \arg pointer to a PIO controller -{ - return pPio->PIO_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status - AT91PS_PIO pPio ) // \arg pointer to a PIO controller -{ - return pPio->PIO_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptMasked -//* \brief Test if PIO Interrupt is Masked -//*---------------------------------------------------------------------------- -static __inline int -AT91F_PIO_IsInterruptMasked( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_PIO_GetInterruptMaskStatus( pPio ) & flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptSet -//* \brief Test if PIO Interrupt is Set -//*---------------------------------------------------------------------------- -static __inline int -AT91F_PIO_IsInterruptSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_PIO_GetInterruptStatus( pPio ) & flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverEnable -//* \brief Multi Driver Enable PIO -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_MultiDriverEnable( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg pio to be enabled -{ - pPio->PIO_MDER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverDisable -//* \brief Multi Driver Disable PIO -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_MultiDriverDisable( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg pio to be disabled -{ - pPio->PIO_MDDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetMultiDriverStatus -//* \brief Return PIO Multi Driver Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status - AT91PS_PIO pPio ) // \arg pointer to a PIO controller -{ - return pPio->PIO_MDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsMultiDriverSet -//* \brief Test if PIO MultiDriver is Set -//*---------------------------------------------------------------------------- -static __inline int -AT91F_PIO_IsMultiDriverSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_PIO_GetMultiDriverStatus( pPio ) & flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_A_RegisterSelection -//* \brief PIO A Register Selection -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_A_RegisterSelection( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg pio A register selection -{ - pPio->PIO_ASR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_B_RegisterSelection -//* \brief PIO B Register Selection -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_B_RegisterSelection( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg pio B register selection -{ - pPio->PIO_BSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Get_AB_RegisterStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status - AT91PS_PIO pPio ) // \arg pointer to a PIO controller -{ - return pPio->PIO_ABSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsAB_RegisterSet -//* \brief Test if PIO AB Register is Set -//*---------------------------------------------------------------------------- -static __inline int -AT91F_PIO_IsAB_RegisterSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_PIO_Get_AB_RegisterStatus( pPio ) & flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteEnable -//* \brief Output Write Enable PIO -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_OutputWriteEnable( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg pio output write to be enabled -{ - pPio->PIO_OWER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteDisable -//* \brief Output Write Disable PIO -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIO_OutputWriteDisable( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg pio output write to be disabled -{ - pPio->PIO_OWDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputWriteStatus -//* \brief Return PIO Output Write Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status - AT91PS_PIO pPio ) // \arg pointer to a PIO controller -{ - return pPio->PIO_OWSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputWriteSet -//* \brief Test if PIO OutputWrite is Set -//*---------------------------------------------------------------------------- -static __inline int -AT91F_PIO_IsOutputWriteSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_PIO_GetOutputWriteStatus( pPio ) & flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetCfgPullup -//* \brief Return PIO Configuration Pullup -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup - AT91PS_PIO pPio ) // \arg pointer to a PIO controller -{ - return pPio->PIO_PPUSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputDataStatusSet -//* \brief Test if PIO Output Data Status is Set -//*---------------------------------------------------------------------------- -static __inline int -AT91F_PIO_IsOutputDataStatusSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_PIO_GetOutputDataStatus( pPio ) & flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsCfgPullupStatusSet -//* \brief Test if PIO Configuration Pullup Status is Set -//*---------------------------------------------------------------------------- -static __inline int -AT91F_PIO_IsCfgPullupStatusSet( AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag ) // \arg flag to be tested -{ - return ( ~AT91F_PIO_GetCfgPullup( pPio ) & flag ); -} - -/* ***************************************************************************** - SOFTWARE API FOR PMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkEnableReg -//* \brief Configure the System Clock Enable Register of the PMC controller -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PMC_CfgSysClkEnableReg( AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode ) -{ - //* Write to the SCER register - pPMC->PMC_SCER = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkDisableReg -//* \brief Configure the System Clock Disable Register of the PMC controller -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PMC_CfgSysClkDisableReg( AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode ) -{ - //* Write to the SCDR register - pPMC->PMC_SCDR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetSysClkStatusReg -//* \brief Return the System Clock Status Register of the PMC controller -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PMC_GetSysClkStatusReg( AT91PS_PMC pPMC // pointer to a CAN controller - ) -{ - return pPMC->PMC_SCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePeriphClock -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PMC_EnablePeriphClock( AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds ) // \arg IDs of peripherals -{ - pPMC->PMC_PCER = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePeriphClock -//* \brief Disable peripheral clock -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PMC_DisablePeriphClock( AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds ) // \arg IDs of peripherals -{ - pPMC->PMC_PCDR = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetPeriphClock -//* \brief Get peripheral clock status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PMC_GetPeriphClock( AT91PS_PMC pPMC ) // \arg pointer to PMC controller -{ - return pPMC->PMC_PCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CKGR_CfgMainOscillatorReg( AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int mode ) -{ - pCKGR->CKGR_MOR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CKGR_GetMainOscillatorReg( AT91PS_CKGR pCKGR ) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MOR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_EnableMainOscillator -//* \brief Enable the main oscillator -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CKGR_EnableMainOscillator( AT91PS_CKGR pCKGR ) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_DisableMainOscillator -//* \brief Disable the main oscillator -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CKGR_DisableMainOscillator( AT91PS_CKGR pCKGR ) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscStartUpTime -//* \brief Cfg MOR Register according to the main osc startup time -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int startup_time, // \arg main osc startup time in microsecond (us) - unsigned int slowClock ) // \arg slowClock in Hz -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; - pCKGR->CKGR_MOR |= ( ( slowClock * startup_time ) / ( 8 * 1000000 ) ) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClockFreqReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CKGR_GetMainClockFreqReg( AT91PS_CKGR pCKGR ) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MCFR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClock -//* \brief Return Main clock in Hz -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CKGR_GetMainClock( AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock ) // \arg slowClock in Hz -{ - return ( ( pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF ) * slowClock ) >> 4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgMCKReg -//* \brief Cfg Master Clock Register -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PMC_CfgMCKReg( AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode ) -{ - pPMC->PMC_MCKR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetMCKReg -//* \brief Return Master Clock Register -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PMC_GetMCKReg( AT91PS_PMC pPMC ) // \arg pointer to PMC controller -{ - return pPMC->PMC_MCKR; -} - -//*------------------------------------------------------------------------------ -//* \fn AT91F_PMC_GetMasterClock -//* \brief Return master clock in Hz which correponds to processor clock for ARM7 -//*------------------------------------------------------------------------------ -static __inline unsigned int -AT91F_PMC_GetMasterClock( AT91PS_PMC pPMC, // \arg pointer to PMC controller - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock ) // \arg slowClock in Hz -{ - unsigned int reg = pPMC->PMC_MCKR; - unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) ); - unsigned int pllDivider, pllMultiplier; - - switch ( reg & AT91C_PMC_CSS ) - { - case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected - return slowClock / prescaler; - case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected - return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / prescaler; - case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected - reg = pCKGR->CKGR_PLLR; - pllDivider = ( reg & AT91C_CKGR_DIV ); - pllMultiplier = ( ( reg & AT91C_CKGR_MUL ) >> 16 ) + 1; - return AT91F_CKGR_GetMainClock( pCKGR, slowClock ) / pllDivider * pllMultiplier / prescaler; - } - return 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePCK -//* \brief Enable Programmable Clock x Output -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PMC_EnablePCK( AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck, // \arg Programmable Clock x Output - unsigned int mode ) -{ - pPMC->PMC_PCKR[pck] = mode; - pPMC->PMC_SCER = ( 1 << pck ) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePCK -//* \brief Disable Programmable Clock x Output -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PMC_DisablePCK( AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck ) // \arg Programmable Clock x Output -{ - pPMC->PMC_SCDR = ( 1 << pck ) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnableIt -//* \brief Enable PMC interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PMC_EnableIt( AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag ) // IT to be enabled -{ - //* Write to the IER register - pPMC->PMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisableIt -//* \brief Disable PMC interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PMC_DisableIt( AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag ) // IT to be disabled -{ - //* Write to the IDR register - pPMC->PMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetStatus -//* \brief Return PMC Interrupt Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PMC_GetStatus( // \return PMC Interrupt Status - AT91PS_PMC pPMC ) // pointer to a PMC controller -{ - return pPMC->PMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetInterruptMaskStatus -//* \brief Return PMC Interrupt Mask Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status - AT91PS_PMC pPMC ) // pointer to a PMC controller -{ - return pPMC->PMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsInterruptMasked -//* \brief Test if PMC Interrupt is Masked -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PMC_IsInterruptMasked( AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_PMC_GetInterruptMaskStatus( pPMC ) & flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsStatusSet -//* \brief Test if PMC Status is Set -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PMC_IsStatusSet( AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_PMC_GetStatus( pPMC ) & flag ); -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_CKGR_CfgPLLReg -// \brief Cfg the PLL Register -// ---------------------------------------------------------------------------- -static __inline void -AT91F_CKGR_CfgPLLReg( AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int mode ) -{ - pCKGR->CKGR_PLLR = mode; -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_CKGR_GetPLLReg -// \brief Get the PLL Register -// ---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CKGR_GetPLLReg( AT91PS_CKGR pCKGR ) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_PLLR; -} - - -/* ***************************************************************************** - SOFTWARE API FOR RSTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSoftReset -//* \brief Start Software Reset -//*---------------------------------------------------------------------------- -static __inline void -AT91F_RSTSoftReset( AT91PS_RSTC pRSTC, unsigned int reset ) -{ - pRSTC->RSTC_RCR = ( 0xA5000000 | reset ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSetMode -//* \brief Set Reset Mode -//*---------------------------------------------------------------------------- -static __inline void -AT91F_RSTSetMode( AT91PS_RSTC pRSTC, unsigned int mode ) -{ - pRSTC->RSTC_RMR = ( 0xA5000000 | mode ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetMode -//* \brief Get Reset Mode -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_RSTGetMode( AT91PS_RSTC pRSTC ) -{ - return ( pRSTC->RSTC_RMR ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetStatus -//* \brief Get Reset Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_RSTGetStatus( AT91PS_RSTC pRSTC ) -{ - return ( pRSTC->RSTC_RSR ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTIsSoftRstActive -//* \brief Return !=0 if software reset is still not completed -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_RSTIsSoftRstActive( AT91PS_RSTC pRSTC ) -{ - return ( ( pRSTC->RSTC_RSR ) & AT91C_RSTC_SRCMP ); -} - -/* ***************************************************************************** - SOFTWARE API FOR RTTC - ***************************************************************************** */ -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_SetRTT_TimeBase() -//* \brief Set the RTT prescaler according to the TimeBase in ms -//*-------------------------------------------------------------------------------------- -static __inline unsigned int -AT91F_RTTSetTimeBase( AT91PS_RTTC pRTTC, unsigned int ms ) -{ - if( ms > 2000 ) - return 1; // AT91C_TIME_OUT_OF_RANGE - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= ( ( ( ms << 15 ) / 1000 ) & 0xFFFF ); - return 0; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTSetPrescaler() -//* \brief Set the new prescaler value -//*-------------------------------------------------------------------------------------- -static __inline unsigned int -AT91F_RTTSetPrescaler( AT91PS_RTTC pRTTC, unsigned int rtpres ) -{ - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= ( rtpres & 0xFFFF ); - return ( pRTTC->RTTC_RTMR ); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTRestart() -//* \brief Restart the RTT prescaler -//*-------------------------------------------------------------------------------------- -static __inline void -AT91F_RTTRestart( AT91PS_RTTC pRTTC ) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; -} - - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmINT() -//* \brief Enable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -static __inline void -AT91F_RTTSetAlarmINT( AT91PS_RTTC pRTTC ) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearAlarmINT() -//* \brief Disable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -static __inline void -AT91F_RTTClearAlarmINT( AT91PS_RTTC pRTTC ) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetRttIncINT() -//* \brief Enable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -static __inline void -AT91F_RTTSetRttIncINT( AT91PS_RTTC pRTTC ) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearRttIncINT() -//* \brief Disable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -static __inline void -AT91F_RTTClearRttIncINT( AT91PS_RTTC pRTTC ) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmValue() -//* \brief Set RTT Alarm Value -//*-------------------------------------------------------------------------------------- -static __inline void -AT91F_RTTSetAlarmValue( AT91PS_RTTC pRTTC, unsigned int alarm ) -{ - pRTTC->RTTC_RTAR = alarm; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_GetAlarmValue() -//* \brief Get RTT Alarm Value -//*-------------------------------------------------------------------------------------- -static __inline unsigned int -AT91F_RTTGetAlarmValue( AT91PS_RTTC pRTTC ) -{ - return ( pRTTC->RTTC_RTAR ); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTGetStatus() -//* \brief Read the RTT status -//*-------------------------------------------------------------------------------------- -static __inline unsigned int -AT91F_RTTGetStatus( AT91PS_RTTC pRTTC ) -{ - return ( pRTTC->RTTC_RTSR ); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ReadValue() -//* \brief Read the RTT value -//*-------------------------------------------------------------------------------------- -static __inline unsigned int -AT91F_RTTReadValue( AT91PS_RTTC pRTTC ) -{ - register volatile unsigned int val1, val2; - - do - { - val1 = pRTTC->RTTC_RTVR; - val2 = pRTTC->RTTC_RTVR; - } - while( val1 != val2 ); - return ( val1 ); -} - -/* ***************************************************************************** - SOFTWARE API FOR PITC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITInit -//* \brief System timer init : period in second, system clock freq in MHz -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PITInit( AT91PS_PITC pPITC, unsigned int period, unsigned int pit_frequency ) -{ - pPITC->PITC_PIMR = period ? ( period * pit_frequency + 8 ) >> 4 : 0; // +8 to avoid %10 and /10 - pPITC->PITC_PIMR |= AT91C_PITC_PITEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITSetPIV -//* \brief Set the PIT Periodic Interval Value -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PITSetPIV( AT91PS_PITC pPITC, unsigned int piv ) -{ - pPITC->PITC_PIMR = piv | ( pPITC->PITC_PIMR & ( AT91C_PITC_PITEN | AT91C_PITC_PITIEN ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITEnableInt -//* \brief Enable PIT periodic interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PITEnableInt( AT91PS_PITC pPITC ) -{ - pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITDisableInt -//* \brief Disable PIT periodic interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PITDisableInt( AT91PS_PITC pPITC ) -{ - pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetMode -//* \brief Read PIT mode register -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PITGetMode( AT91PS_PITC pPITC ) -{ - return ( pPITC->PITC_PIMR ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetStatus -//* \brief Read PIT status register -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PITGetStatus( AT91PS_PITC pPITC ) -{ - return ( pPITC->PITC_PISR ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetPIIR -//* \brief Read PIT CPIV and PICNT without ressetting the counters -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PITGetPIIR( AT91PS_PITC pPITC ) -{ - return ( pPITC->PITC_PIIR ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetPIVR -//* \brief Read System timer CPIV and PICNT without ressetting the counters -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PITGetPIVR( AT91PS_PITC pPITC ) -{ - return ( pPITC->PITC_PIVR ); -} - -/* ***************************************************************************** - SOFTWARE API FOR WDTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTSetMode -//* \brief Set Watchdog Mode Register -//*---------------------------------------------------------------------------- -static __inline void -AT91F_WDTSetMode( AT91PS_WDTC pWDTC, unsigned int Mode ) -{ - pWDTC->WDTC_WDMR = Mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTRestart -//* \brief Restart Watchdog -//*---------------------------------------------------------------------------- -static __inline void -AT91F_WDTRestart( AT91PS_WDTC pWDTC ) -{ - pWDTC->WDTC_WDCR = 0xA5000001; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTSGettatus -//* \brief Get Watchdog Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_WDTSGettatus( AT91PS_WDTC pWDTC ) -{ - return ( pWDTC->WDTC_WDSR & 0x3 ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTGetPeriod -//* \brief Translate ms into Watchdog Compatible value -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_WDTGetPeriod( unsigned int ms ) -{ - if( ( ms < 4 ) || ( ms > 16000 ) ) - return 0; - return ( ( ms << 8 ) / 1000 ); -} - -/* ***************************************************************************** - SOFTWARE API FOR VREG - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_Enable_LowPowerMode -//* \brief Enable VREG Low Power Mode -//*---------------------------------------------------------------------------- -static __inline void -AT91F_VREG_Enable_LowPowerMode( AT91PS_VREG pVREG ) -{ - pVREG->VREG_MR |= AT91C_VREG_PSTDBY; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_Disable_LowPowerMode -//* \brief Disable VREG Low Power Mode -//*---------------------------------------------------------------------------- -static __inline void -AT91F_VREG_Disable_LowPowerMode( AT91PS_VREG pVREG ) -{ - pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; -} /* ***************************************************************************** - SOFTWARE API FOR MC - ***************************************************************************** */ - -#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_Remap -//* \brief Make Remap -//*---------------------------------------------------------------------------- -static __inline void -AT91F_MC_Remap( void ) // -{ - AT91PS_MC pMC = ( AT91PS_MC ) AT91C_BASE_MC; - - pMC->MC_RCR = AT91C_MC_RCB; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_CfgModeReg -//* \brief Configure the EFC Mode Register of the MC controller -//*---------------------------------------------------------------------------- -static __inline void -AT91F_MC_EFC_CfgModeReg( AT91PS_MC pMC, // pointer to a MC controller - unsigned int mode ) // mode register -{ - // Write to the FMR register - pMC->MC_FMR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetModeReg -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_MC_EFC_GetModeReg( AT91PS_MC pMC ) // pointer to a MC controller -{ - return pMC->MC_FMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_ComputeFMCN -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_MC_EFC_ComputeFMCN( int master_clock ) // master clock in Hz -{ - return ( master_clock / 1000000 + 2 ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_PerformCmd -//* \brief Perform EFC Command -//*---------------------------------------------------------------------------- -static __inline void -AT91F_MC_EFC_PerformCmd( AT91PS_MC pMC, // pointer to a MC controller - unsigned int transfer_cmd ) -{ - pMC->MC_FCR = transfer_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetStatus -//* \brief Return MC EFC Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_MC_EFC_GetStatus( AT91PS_MC pMC ) // pointer to a MC controller -{ - return pMC->MC_FSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptMasked -//* \brief Test if EFC MC Interrupt is Masked -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_MC_EFC_IsInterruptMasked( AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_MC_EFC_GetModeReg( pMC ) & flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptSet -//* \brief Test if EFC MC Interrupt is Set -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_MC_EFC_IsInterruptSet( AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_MC_EFC_GetStatus( pMC ) & flag ); -} - -/* ***************************************************************************** - SOFTWARE API FOR SPI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgCs -//* \brief Configure SPI chip select register -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SPI_CfgCs( AT91PS_SPI pSPI, // pointer to a SPI controller - int cs, // SPI cs number (0 to 3) - int val ) // chip select register -{ - //* Write to the CSR register - *( pSPI->SPI_CSR + cs ) = val; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_EnableIt -//* \brief Enable SPI interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SPI_EnableIt( AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag ) // IT to be enabled -{ - //* Write to the IER register - pSPI->SPI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_DisableIt -//* \brief Disable SPI interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SPI_DisableIt( AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag ) // IT to be disabled -{ - //* Write to the IDR register - pSPI->SPI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Reset -//* \brief Reset the SPI controller -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SPI_Reset( AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Enable -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SPI_Enable( AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Disable -//* \brief Disable the SPI controller -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SPI_Disable( AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgMode -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SPI_CfgMode( AT91PS_SPI pSPI, // pointer to a SPI controller - int mode ) // mode register -{ - //* Write to the MR register - pSPI->SPI_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPCS -//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SPI_CfgPCS( AT91PS_SPI pSPI, // pointer to a SPI controller - char PCS_Device ) // PCS of the Device -{ - //* Write to the MR register - pSPI->SPI_MR &= 0xFFF0FFFF; - pSPI->SPI_MR |= ( ( PCS_Device << 16 ) & AT91C_SPI_PCS ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_SPI_ReceiveFrame( AT91PS_SPI pSPI, - char *pBuffer, unsigned int szBuffer, char *pNextBuffer, unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( ( AT91PS_PDC ) & ( pSPI->SPI_RPR ), pBuffer, szBuffer, pNextBuffer, szNextBuffer ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_SPI_SendFrame( AT91PS_SPI pSPI, - char *pBuffer, unsigned int szBuffer, char *pNextBuffer, unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( ( AT91PS_PDC ) & ( pSPI->SPI_RPR ), pBuffer, szBuffer, pNextBuffer, szNextBuffer ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Close -//* \brief Close SPI: disable IT disable transfert, close PDC -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SPI_Close( AT91PS_SPI pSPI ) // \arg pointer to a SPI controller -{ - //* Reset all the Chip Select register - pSPI->SPI_CSR[0] = 0; - pSPI->SPI_CSR[1] = 0; - pSPI->SPI_CSR[2] = 0; - pSPI->SPI_CSR[3] = 0; - - //* Reset the SPI mode - pSPI->SPI_MR = 0; - - //* Disable all interrupts - pSPI->SPI_IDR = 0xFFFFFFFF; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close( ( AT91PS_PDC ) & ( pSPI->SPI_RPR ) ); - - //* Disable receiver and transmitter and stop any activity immediately - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SPI_PutChar( AT91PS_SPI pSPI, unsigned int character, unsigned int cs_number ) -{ - unsigned int value_for_cs; - - value_for_cs = ( ~( 1 << cs_number ) ) & 0xF; //Place a zero among a 4 ONEs number - pSPI->SPI_TDR = ( character & 0xFFFF ) | ( value_for_cs << 16 ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -static __inline int -AT91F_SPI_GetChar( const AT91PS_SPI pSPI ) -{ - return ( ( pSPI->SPI_RDR ) & 0xFFFF ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetInterruptMaskStatus -//* \brief Return SPI Interrupt Mask Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status - AT91PS_SPI pSpi ) // \arg pointer to a SPI controller -{ - return pSpi->SPI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_IsInterruptMasked -//* \brief Test if SPI Interrupt is Masked -//*---------------------------------------------------------------------------- -static __inline int -AT91F_SPI_IsInterruptMasked( AT91PS_SPI pSpi, // \arg pointer to a SPI controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_SPI_GetInterruptMaskStatus( pSpi ) & flag ); -} - -/* ***************************************************************************** - SOFTWARE API FOR USART - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Calculate the baudrate -//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_EXT ) - -//* Standard Synchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ - AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* SCK used Label -#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) - -//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity -#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ - AT91C_US_CLKS_CLOCK +\ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_EVEN + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CKLO +\ - AT91C_US_OVER) - -//* Standard IRDA mode -#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Caluculate baud_value according to the main clock and the baud rate -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_US_Baudrate( const unsigned int main_clock, // \arg peripheral clock - const unsigned int baud_rate ) // \arg UART baudrate -{ - unsigned int baud_value = ( ( main_clock * 10 ) / ( baud_rate * 16 ) ); - - if( ( baud_value % 10 ) >= 5 ) - baud_value = ( baud_value / 10 ) + 1; - else - baud_value /= 10; - return baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US_SetBaudrate( AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed ) // \arg UART baudrate -{ - //* Define the baud rate divisor register - pUSART->US_BRGR = AT91F_US_Baudrate( mainClock, speed ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetTimeguard -//* \brief Set USART timeguard -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US_SetTimeguard( AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int timeguard ) // \arg timeguard value -{ - //* Write the Timeguard Register - pUSART->US_TTGR = timeguard; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableIt -//* \brief Enable USART IT -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US_EnableIt( AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag ) // \arg IT to be enabled -{ - //* Write to the IER register - pUSART->US_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableIt -//* \brief Disable USART IT -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US_DisableIt( AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag ) // \arg IT to be disabled -{ - //* Write to the IER register - pUSART->US_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Configure -//* \brief Configure USART -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US_Configure( AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int mode, // \arg mode Register to be programmed - unsigned int baudRate, // \arg baudrate to be programmed - unsigned int timeguard ) // \arg timeguard to be programmed -{ - //* Disable interrupts - pUSART->US_IDR = ( unsigned int )-1; - - //* Reset receiver and transmitter - pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS; - - //* Define the baud rate divisor register - AT91F_US_SetBaudrate( pUSART, mainClock, baudRate ); - - //* Write the Timeguard Register - AT91F_US_SetTimeguard( pUSART, timeguard ); - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open( ( AT91PS_PDC ) & ( pUSART->US_RPR ) ); - - //* Define the USART mode - pUSART->US_MR = mode; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableRx -//* \brief Enable receiving characters -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US_EnableRx( AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - //* Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableTx -//* \brief Enable sending characters -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US_EnableTx( AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetRx -//* \brief Reset Receiver and re-enable it -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US_ResetRx( AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - //* Reset receiver - pUSART->US_CR = AT91C_US_RSTRX; - //* Re-Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetTx -//* \brief Reset Transmitter and re-enable it -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US_ResetTx( AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - //* Reset transmitter - pUSART->US_CR = AT91C_US_RSTTX; - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableRx -//* \brief Disable Receiver -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US_DisableRx( AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - //* Disable receiver - pUSART->US_CR = AT91C_US_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableTx -//* \brief Disable Transmitter -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US_DisableTx( AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - //* Disable transmitter - pUSART->US_CR = AT91C_US_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Close -//* \brief Close USART: disable IT disable receiver and transmitter, close PDC -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US_Close( AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - //* Reset the baud rate divisor register - pUSART->US_BRGR = 0; - - //* Reset the USART mode - pUSART->US_MR = 0; - - //* Reset the Timeguard Register - pUSART->US_TTGR = 0; - - //* Disable all interrupts - pUSART->US_IDR = 0xFFFFFFFF; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close( ( AT91PS_PDC ) & ( pUSART->US_RPR ) ); - - //* Disable receiver and transmitter and stop any activity immediately - pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_TxReady -//* \brief Return 1 if a character can be written in US_THR -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_US_TxReady( AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return ( pUSART->US_CSR & AT91C_US_TXRDY ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_RxReady -//* \brief Return 1 if a character can be read in US_RHR -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_US_RxReady( AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return ( pUSART->US_CSR & AT91C_US_RXRDY ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Error -//* \brief Return the error flag -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_US_Error( AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return ( pUSART->US_CSR & ( AT91C_US_OVRE | // Overrun error - AT91C_US_FRAME | // Framing error - AT91C_US_PARE ) ); // Parity error -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US_PutChar( AT91PS_USART pUSART, int character ) -{ - pUSART->US_THR = ( character & 0x1FF ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -static __inline int -AT91F_US_GetChar( const AT91PS_USART pUSART ) -{ - return ( ( pUSART->US_RHR ) & 0x1FF ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_US_SendFrame( AT91PS_USART pUSART, - char *pBuffer, unsigned int szBuffer, char *pNextBuffer, unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( ( AT91PS_PDC ) & ( pUSART->US_RPR ), pBuffer, szBuffer, pNextBuffer, szNextBuffer ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_US_ReceiveFrame( AT91PS_USART pUSART, - char *pBuffer, unsigned int szBuffer, char *pNextBuffer, unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( ( AT91PS_PDC ) & ( pUSART->US_RPR ), pBuffer, szBuffer, pNextBuffer, szNextBuffer ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetIrdaFilter -//* \brief Set the value of IrDa filter tregister -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US_SetIrdaFilter( AT91PS_USART pUSART, unsigned char value ) -{ - pUSART->US_IF = value; -} - -/* ***************************************************************************** - SOFTWARE API FOR SSC - ***************************************************************************** */ -//* Define the standard I2S mode configuration - -//* Configuration to set in the SSC Transmit Clock Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - AT91C_SSC_CKS_DIV +\ - AT91C_SSC_CKO_CONTINOUS +\ - AT91C_SSC_CKG_NONE +\ - AT91C_SSC_START_FALL_RF +\ - AT91C_SSC_STTOUT +\ - ((1<<16) & AT91C_SSC_STTDLY) +\ - ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) - - -//* Configuration to set in the SSC Transmit Frame Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - (nb_bit_by_slot-1) +\ - AT91C_SSC_MSBF +\ - (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ - (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ - AT91C_SSC_FSOS_NEGATIVE) - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SSC_SetBaudrate( AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed ) // \arg SSC baudrate -{ - unsigned int baud_value; - - //* Define the baud rate divisor register - if( speed == 0 ) - baud_value = 0; - else - { - baud_value = ( unsigned int )( mainClock * 10 ) / ( 2 * speed ); - if( ( baud_value % 10 ) >= 5 ) - baud_value = ( baud_value / 10 ) + 1; - else - baud_value /= 10; - } - - pSSC->SSC_CMR = baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_Configure -//* \brief Configure SSC -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SSC_Configure( AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int syst_clock, // \arg System Clock Frequency - unsigned int baud_rate, // \arg Expected Baud Rate Frequency - unsigned int clock_rx, // \arg Receiver Clock Parameters - unsigned int mode_rx, // \arg mode Register to be programmed - unsigned int clock_tx, // \arg Transmitter Clock Parameters - unsigned int mode_tx ) // \arg mode Register to be programmed -{ - //* Disable interrupts - pSSC->SSC_IDR = ( unsigned int )-1; - - //* Reset receiver and transmitter - pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS; - - //* Define the Clock Mode Register - AT91F_SSC_SetBaudrate( pSSC, syst_clock, baud_rate ); - - //* Write the Receive Clock Mode Register - pSSC->SSC_RCMR = clock_rx; - - //* Write the Transmit Clock Mode Register - pSSC->SSC_TCMR = clock_tx; - - //* Write the Receive Frame Mode Register - pSSC->SSC_RFMR = mode_rx; - - //* Write the Transmit Frame Mode Register - pSSC->SSC_TFMR = mode_tx; - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open( ( AT91PS_PDC ) & ( pSSC->SSC_RPR ) ); - - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableRx -//* \brief Enable receiving datas -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SSC_EnableRx( AT91PS_SSC pSSC ) // \arg pointer to a SSC controller -{ - //* Enable receiver - pSSC->SSC_CR = AT91C_SSC_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableRx -//* \brief Disable receiving datas -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SSC_DisableRx( AT91PS_SSC pSSC ) // \arg pointer to a SSC controller -{ - //* Disable receiver - pSSC->SSC_CR = AT91C_SSC_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableTx -//* \brief Enable sending datas -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SSC_EnableTx( AT91PS_SSC pSSC ) // \arg pointer to a SSC controller -{ - //* Enable transmitter - pSSC->SSC_CR = AT91C_SSC_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableTx -//* \brief Disable sending datas -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SSC_DisableTx( AT91PS_SSC pSSC ) // \arg pointer to a SSC controller -{ - //* Disable transmitter - pSSC->SSC_CR = AT91C_SSC_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableIt -//* \brief Enable SSC IT -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SSC_EnableIt( AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag ) // \arg IT to be enabled -{ - //* Write to the IER register - pSSC->SSC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableIt -//* \brief Disable SSC IT -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SSC_DisableIt( AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag ) // \arg IT to be disabled -{ - //* Write to the IDR register - pSSC->SSC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_SSC_ReceiveFrame( AT91PS_SSC pSSC, - char *pBuffer, unsigned int szBuffer, char *pNextBuffer, unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( ( AT91PS_PDC ) & ( pSSC->SSC_RPR ), pBuffer, szBuffer, pNextBuffer, szNextBuffer ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_SSC_SendFrame( AT91PS_SSC pSSC, - char *pBuffer, unsigned int szBuffer, char *pNextBuffer, unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( ( AT91PS_PDC ) & ( pSSC->SSC_RPR ), pBuffer, szBuffer, pNextBuffer, szNextBuffer ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_GetInterruptMaskStatus -//* \brief Return SSC Interrupt Mask Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status - AT91PS_SSC pSsc ) // \arg pointer to a SSC controller -{ - return pSsc->SSC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_IsInterruptMasked -//* \brief Test if SSC Interrupt is Masked -//*---------------------------------------------------------------------------- -static __inline int -AT91F_SSC_IsInterruptMasked( AT91PS_SSC pSsc, // \arg pointer to a SSC controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_SSC_GetInterruptMaskStatus( pSsc ) & flag ); -} - -/* ***************************************************************************** - SOFTWARE API FOR TWI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_EnableIt -//* \brief Enable TWI IT -//*---------------------------------------------------------------------------- -static __inline void -AT91F_TWI_EnableIt( AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag ) // \arg IT to be enabled -{ - //* Write to the IER register - pTWI->TWI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_DisableIt -//* \brief Disable TWI IT -//*---------------------------------------------------------------------------- -static __inline void -AT91F_TWI_DisableIt( AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag ) // \arg IT to be disabled -{ - //* Write to the IDR register - pTWI->TWI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_Configure -//* \brief Configure TWI in master mode -//*---------------------------------------------------------------------------- -static __inline void -AT91F_TWI_Configure( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller -{ - //* Disable interrupts - pTWI->TWI_IDR = ( unsigned int )-1; - - //* Reset peripheral - pTWI->TWI_CR = AT91C_TWI_SWRST; - - //* Set Master mode - pTWI->TWI_CR = AT91C_TWI_MSEN; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_GetInterruptMaskStatus -//* \brief Return TWI Interrupt Mask Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status - AT91PS_TWI pTwi ) // \arg pointer to a TWI controller -{ - return pTwi->TWI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_IsInterruptMasked -//* \brief Test if TWI Interrupt is Masked -//*---------------------------------------------------------------------------- -static __inline int -AT91F_TWI_IsInterruptMasked( AT91PS_TWI pTwi, // \arg pointer to a TWI controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_TWI_GetInterruptMaskStatus( pTwi ) & flag ); -} - -/* ***************************************************************************** - SOFTWARE API FOR PWMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetStatus -//* \brief Return PWM Interrupt Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PWMC_GetStatus( // \return PWM Interrupt Status - AT91PS_PWMC pPWM ) // pointer to a PWM controller -{ - return pPWM->PWMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptEnable -//* \brief Enable PWM Interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PWMC_InterruptEnable( AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag ) // \arg PWM interrupt to be enabled -{ - pPwm->PWMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptDisable -//* \brief Disable PWM Interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PWMC_InterruptDisable( AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag ) // \arg PWM interrupt to be disabled -{ - pPwm->PWMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetInterruptMaskStatus -//* \brief Return PWM Interrupt Mask Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status - AT91PS_PWMC pPwm ) // \arg pointer to a PWM controller -{ - return pPwm->PWMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsInterruptMasked -//* \brief Test if PWM Interrupt is Masked -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PWMC_IsInterruptMasked( AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_PWMC_GetInterruptMaskStatus( pPWM ) & flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsStatusSet -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_PWMC_IsStatusSet( AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_PWMC_GetStatus( pPWM ) & flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_CfgChannel -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PWMC_CfgChannel( AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int mode, // \arg PWM mode - unsigned int period, // \arg PWM period - unsigned int duty ) // \arg PWM duty cycle -{ - pPWM->PWMC_CH[channelId].PWMC_CMR = mode; - pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; - pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StartChannel -//* \brief Enable channel -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PWMC_StartChannel( AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag ) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_ENA = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StopChannel -//* \brief Disable channel -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PWMC_StopChannel( AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag ) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_DIS = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_UpdateChannel -//* \brief Update Period or Duty Cycle -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PWMC_UpdateChannel( AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int update ) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; -} - -/* ***************************************************************************** - SOFTWARE API FOR UDP - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableIt -//* \brief Enable UDP IT -//*---------------------------------------------------------------------------- -static __inline void -AT91F_UDP_EnableIt( AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag ) // \arg IT to be enabled -{ - //* Write to the IER register - pUDP->UDP_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableIt -//* \brief Disable UDP IT -//*---------------------------------------------------------------------------- -static __inline void -AT91F_UDP_DisableIt( AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag ) // \arg IT to be disabled -{ - //* Write to the IDR register - pUDP->UDP_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetAddress -//* \brief Set UDP functional address -//*---------------------------------------------------------------------------- -static __inline void -AT91F_UDP_SetAddress( AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char address ) // \arg new UDP address -{ - pUDP->UDP_FADDR = ( AT91C_UDP_FEN | address ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -static __inline void -AT91F_UDP_EnableEp( AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint ) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -static __inline void -AT91F_UDP_DisableEp( AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint ) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetState -//* \brief Set UDP Device state -//*---------------------------------------------------------------------------- -static __inline void -AT91F_UDP_SetState( AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag ) // \arg new UDP address -{ - pUDP->UDP_GLBSTATE &= ~( AT91C_UDP_FADDEN | AT91C_UDP_CONFG ); - pUDP->UDP_GLBSTATE |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetState -//* \brief return UDP Device state -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_UDP_GetState( // \return the UDP device state - AT91PS_UDP pUDP ) // \arg pointer to a UDP controller -{ - return ( pUDP->UDP_GLBSTATE & ( AT91C_UDP_FADDEN | AT91C_UDP_CONFG ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_ResetEp -//* \brief Reset UDP endpoint -//*---------------------------------------------------------------------------- -static __inline void -AT91F_UDP_ResetEp( // \return the UDP device state - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag ) // \arg Endpoints to be reset -{ - pUDP->UDP_RSTEP = flag; - pUDP->UDP_RSTEP = 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStall -//* \brief Endpoint will STALL requests -//*---------------------------------------------------------------------------- -static __inline void -AT91F_UDP_EpStall( AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint ) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpWrite -//* \brief Write value in the DPR -//*---------------------------------------------------------------------------- -static __inline void -AT91F_UDP_EpWrite( AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned char value ) // \arg value to be written in the DPR -{ - pUDP->UDP_FDR[endpoint] = value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpRead -//* \brief Return value from the DPR -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_UDP_EpRead( AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint ) // \arg endpoint number -{ - return pUDP->UDP_FDR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpEndOfWr -//* \brief Notify the UDP that values in DPR are ready to be sent -//*---------------------------------------------------------------------------- -static __inline void -AT91F_UDP_EpEndOfWr( AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint ) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpClear -//* \brief Clear flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -static __inline void -AT91F_UDP_EpClear( AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag ) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] &= ~( flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpSet -//* \brief Set flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -static __inline void -AT91F_UDP_EpSet( AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag ) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStatus -//* \brief Return the endpoint CSR register -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_UDP_EpStatus( AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint ) // \arg endpoint number -{ - return pUDP->UDP_CSR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetInterruptMaskStatus -//* \brief Return UDP Interrupt Mask Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_UDP_GetInterruptMaskStatus( AT91PS_UDP pUdp ) // \arg pointer to a UDP controller -{ - return pUdp->UDP_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_IsInterruptMasked -//* \brief Test if UDP Interrupt is Masked -//*---------------------------------------------------------------------------- -static __inline int -AT91F_UDP_IsInterruptMasked( AT91PS_UDP pUdp, // \arg pointer to a UDP controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_UDP_GetInterruptMaskStatus( pUdp ) & flag ); -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_UDP_InterruptStatusRegister -// \brief Return the Interrupt Status Register -// ---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_UDP_InterruptStatusRegister( AT91PS_UDP pUDP ) // \arg pointer to a UDP controller -{ - return pUDP->UDP_ISR; -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_UDP_InterruptClearRegister -// \brief Clear Interrupt Register -// ---------------------------------------------------------------------------- -static __inline void -AT91F_UDP_InterruptClearRegister( AT91PS_UDP pUDP, // \arg pointer to UDP controller - unsigned int flag ) // \arg IT to be cleat -{ - pUDP->UDP_ICR = flag; -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_UDP_EnableTransceiver -// \brief Enable transceiver -// ---------------------------------------------------------------------------- -static __inline void -AT91F_UDP_EnableTransceiver( AT91PS_UDP pUDP ) // \arg pointer to a UDP controller -{ - pUDP->UDP_TXVC &= ~AT91C_UDP_TXVDIS; -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_UDP_DisableTransceiver -// \brief Disable transceiver -// ---------------------------------------------------------------------------- -static __inline void -AT91F_UDP_DisableTransceiver( AT91PS_UDP pUDP ) // \arg pointer to a UDP controller -{ - pUDP->UDP_TXVC = AT91C_UDP_TXVDIS; -} - -/* ***************************************************************************** - SOFTWARE API FOR TC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptEnable -//* \brief Enable TC Interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_TC_InterruptEnable( AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag ) // \arg TC interrupt to be enabled -{ - pTc->TC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptDisable -//* \brief Disable TC Interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_TC_InterruptDisable( AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag ) // \arg TC interrupt to be disabled -{ - pTc->TC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_GetInterruptMaskStatus -//* \brief Return TC Interrupt Mask Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status - AT91PS_TC pTc ) // \arg pointer to a TC controller -{ - return pTc->TC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_IsInterruptMasked -//* \brief Test if TC Interrupt is Masked -//*---------------------------------------------------------------------------- -static __inline int -AT91F_TC_IsInterruptMasked( AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_TC_GetInterruptMaskStatus( pTc ) & flag ); -} - -/* ***************************************************************************** - SOFTWARE API FOR CAN - ***************************************************************************** */ -#define STANDARD_FORMAT 0 -#define EXTENDED_FORMAT 1 - -//*---------------------------------------------------------------------------- -//* \fn AT91F_InitMailboxRegisters() -//* \brief Configure the corresponding mailbox -//*---------------------------------------------------------------------------- -static __inline void -AT91F_InitMailboxRegisters( AT91PS_CAN_MB CAN_Mailbox, - int mode_reg, - int acceptance_mask_reg, int id_reg, int data_low_reg, int data_high_reg, int control_reg ) -{ - CAN_Mailbox->CAN_MB_MCR = 0x0; - CAN_Mailbox->CAN_MB_MMR = mode_reg; - CAN_Mailbox->CAN_MB_MAM = acceptance_mask_reg; - CAN_Mailbox->CAN_MB_MID = id_reg; - CAN_Mailbox->CAN_MB_MDL = data_low_reg; - CAN_Mailbox->CAN_MB_MDH = data_high_reg; - CAN_Mailbox->CAN_MB_MCR = control_reg; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EnableCAN() -//* \brief -//*---------------------------------------------------------------------------- -static __inline void -AT91F_EnableCAN( AT91PS_CAN pCAN ) // pointer to a CAN controller -{ - pCAN->CAN_MR |= AT91C_CAN_CANEN; - - // Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver - while( ( pCAN->CAN_SR & AT91C_CAN_WAKEUP ) != AT91C_CAN_WAKEUP ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DisableCAN() -//* \brief -//*---------------------------------------------------------------------------- -static __inline void -AT91F_DisableCAN( AT91PS_CAN pCAN ) // pointer to a CAN controller -{ - pCAN->CAN_MR &= ~AT91C_CAN_CANEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_EnableIt -//* \brief Enable CAN interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CAN_EnableIt( AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int flag ) // IT to be enabled -{ - //* Write to the IER register - pCAN->CAN_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_DisableIt -//* \brief Disable CAN interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CAN_DisableIt( AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int flag ) // IT to be disabled -{ - //* Write to the IDR register - pCAN->CAN_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetStatus -//* \brief Return CAN Interrupt Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CAN_GetStatus( // \return CAN Interrupt Status - AT91PS_CAN pCAN ) // pointer to a CAN controller -{ - return pCAN->CAN_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetInterruptMaskStatus -//* \brief Return CAN Interrupt Mask Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status - AT91PS_CAN pCAN ) // pointer to a CAN controller -{ - return pCAN->CAN_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_IsInterruptMasked -//* \brief Test if CAN Interrupt is Masked -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CAN_IsInterruptMasked( AT91PS_CAN pCAN, // \arg pointer to a CAN controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_CAN_GetInterruptMaskStatus( pCAN ) & flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_IsStatusSet -//* \brief Test if CAN Interrupt is Set -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CAN_IsStatusSet( AT91PS_CAN pCAN, // \arg pointer to a CAN controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_CAN_GetStatus( pCAN ) & flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgModeReg -//* \brief Configure the Mode Register of the CAN controller -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CAN_CfgModeReg( AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int mode ) // mode register -{ - //* Write to the MR register - pCAN->CAN_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetModeReg -//* \brief Return the Mode Register of the CAN controller value -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CAN_GetModeReg( AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgBaudrateReg -//* \brief Configure the Baudrate of the CAN controller for the network -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CAN_CfgBaudrateReg( AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int baudrate_cfg ) -{ - //* Write to the BR register - pCAN->CAN_BR = baudrate_cfg; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetBaudrate -//* \brief Return the Baudrate of the CAN controller for the network value -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CAN_GetBaudrate( AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_BR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetInternalCounter -//* \brief Return CAN Timer Regsiter Value -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CAN_GetInternalCounter( AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_TIM; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetTimestamp -//* \brief Return CAN Timestamp Register Value -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CAN_GetTimestamp( AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_TIMESTP; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetErrorCounter -//* \brief Return CAN Error Counter Register Value -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CAN_GetErrorCounter( AT91PS_CAN pCAN // pointer to a CAN controller - ) -{ - return pCAN->CAN_ECR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_InitTransferRequest -//* \brief Request for a transfer on the corresponding mailboxes -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CAN_InitTransferRequest( AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int transfer_cmd ) -{ - pCAN->CAN_TCR = transfer_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_InitAbortRequest -//* \brief Abort the corresponding mailboxes -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CAN_InitAbortRequest( AT91PS_CAN pCAN, // pointer to a CAN controller - unsigned int abort_cmd ) -{ - pCAN->CAN_ACR = abort_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageModeReg -//* \brief Program the Message Mode Register -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CAN_CfgMessageModeReg( AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int mode ) -{ - CAN_Mailbox->CAN_MB_MMR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageModeReg -//* \brief Return the Message Mode Register -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CAN_GetMessageModeReg( AT91PS_CAN_MB CAN_Mailbox ) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageIDReg -//* \brief Program the Message ID Register -//* \brief Version == 0 for Standard messsage, Version == 1 for Extended -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CAN_CfgMessageIDReg( AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int id, unsigned char version ) -{ - if( version == 0 ) // IDvA Standard Format - CAN_Mailbox->CAN_MB_MID = id << 18; - else // IDvB Extended Format - CAN_Mailbox->CAN_MB_MID = id | ( 1 << 29 ); // set MIDE bit -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageIDReg -//* \brief Return the Message ID Register -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CAN_GetMessageIDReg( AT91PS_CAN_MB CAN_Mailbox ) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MID; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageAcceptanceMaskReg -//* \brief Program the Message Acceptance Mask Register -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CAN_CfgMessageAcceptanceMaskReg( AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int mask ) -{ - CAN_Mailbox->CAN_MB_MAM = mask; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageAcceptanceMaskReg -//* \brief Return the Message Acceptance Mask Register -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CAN_GetMessageAcceptanceMaskReg( AT91PS_CAN_MB CAN_Mailbox ) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MAM; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetFamilyID -//* \brief Return the Message ID Register -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CAN_GetFamilyID( AT91PS_CAN_MB CAN_Mailbox ) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MFID; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageCtrl -//* \brief Request and config for a transfer on the corresponding mailbox -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CAN_CfgMessageCtrlReg( AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int message_ctrl_cmd ) -{ - CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageStatus -//* \brief Return CAN Mailbox Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CAN_GetMessageStatus( AT91PS_CAN_MB CAN_Mailbox ) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageDataLow -//* \brief Program data low value -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CAN_CfgMessageDataLow( AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int data ) -{ - CAN_Mailbox->CAN_MB_MDL = data; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageDataLow -//* \brief Return data low value -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CAN_GetMessageDataLow( AT91PS_CAN_MB CAN_Mailbox ) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MDL; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgMessageDataHigh -//* \brief Program data high value -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CAN_CfgMessageDataHigh( AT91PS_CAN_MB CAN_Mailbox, // pointer to a CAN Mailbox - unsigned int data ) -{ - CAN_Mailbox->CAN_MB_MDH = data; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_GetMessageDataHigh -//* \brief Return data high value -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_CAN_GetMessageDataHigh( AT91PS_CAN_MB CAN_Mailbox ) // pointer to a CAN Mailbox -{ - return CAN_Mailbox->CAN_MB_MDH; -} - -/* ***************************************************************************** - SOFTWARE API FOR ADC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableIt -//* \brief Enable ADC interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_ADC_EnableIt( AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag ) // IT to be enabled -{ - //* Write to the IER register - pADC->ADC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableIt -//* \brief Disable ADC interrupt -//*---------------------------------------------------------------------------- -static __inline void -AT91F_ADC_DisableIt( AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag ) // IT to be disabled -{ - //* Write to the IDR register - pADC->ADC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetStatus -//* \brief Return ADC Interrupt Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_ADC_GetStatus( // \return ADC Interrupt Status - AT91PS_ADC pADC ) // pointer to a ADC controller -{ - return pADC->ADC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetInterruptMaskStatus -//* \brief Return ADC Interrupt Mask Status -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status - AT91PS_ADC pADC ) // pointer to a ADC controller -{ - return pADC->ADC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsInterruptMasked -//* \brief Test if ADC Interrupt is Masked -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_ADC_IsInterruptMasked( AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_ADC_GetInterruptMaskStatus( pADC ) & flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsStatusSet -//* \brief Test if ADC Status is Set -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_ADC_IsStatusSet( AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag ) // \arg flag to be tested -{ - return ( AT91F_ADC_GetStatus( pADC ) & flag ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgModeReg -//* \brief Configure the Mode Register of the ADC controller -//*---------------------------------------------------------------------------- -static __inline void -AT91F_ADC_CfgModeReg( AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mode ) // mode register -{ - //* Write to the MR register - pADC->ADC_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetModeReg -//* \brief Return the Mode Register of the ADC controller value -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_ADC_GetModeReg( AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgTimings -//* \brief Configure the different necessary timings of the ADC controller -//*---------------------------------------------------------------------------- -static __inline void -AT91F_ADC_CfgTimings( AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mck_clock, // in MHz - unsigned int adc_clock, // in MHz - unsigned int startup_time, // in us - unsigned int sample_and_hold_time ) // in ns -{ - unsigned int prescal, startup, shtim; - - prescal = mck_clock / ( 2 * adc_clock ) - 1; - startup = adc_clock * startup_time / 8 - 1; - shtim = adc_clock * sample_and_hold_time / 1000 - 1; - - //* Write to the MR register - pADC->ADC_MR = - ( ( prescal << 8 ) & AT91C_ADC_PRESCAL ) | ( ( startup << 16 ) & AT91C_ADC_STARTUP ) | ( ( shtim << 24 ) & - AT91C_ADC_SHTIM ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -static __inline void -AT91F_ADC_EnableChannel( AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel ) // mode register -{ - //* Write to the CHER register - pADC->ADC_CHER = channel; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -static __inline void -AT91F_ADC_DisableChannel( AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel ) // mode register -{ - //* Write to the CHDR register - pADC->ADC_CHDR = channel; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetChannelStatus -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_ADC_GetChannelStatus( AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CHSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_StartConversion -//* \brief Software request for a analog to digital conversion -//*---------------------------------------------------------------------------- -static __inline void -AT91F_ADC_StartConversion( AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - pADC->ADC_CR = AT91C_ADC_START; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_SoftReset -//* \brief Software reset -//*---------------------------------------------------------------------------- -static __inline void -AT91F_ADC_SoftReset( AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - pADC->ADC_CR = AT91C_ADC_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetLastConvertedData -//* \brief Return the Last Converted Data -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_ADC_GetLastConvertedData( AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_LCDR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH0 -//* \brief Return the Channel 0 Converted Data -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_ADC_GetConvertedDataCH0( AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH1 -//* \brief Return the Channel 1 Converted Data -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_ADC_GetConvertedDataCH1( AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR1; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH2 -//* \brief Return the Channel 2 Converted Data -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_ADC_GetConvertedDataCH2( AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR2; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH3 -//* \brief Return the Channel 3 Converted Data -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_ADC_GetConvertedDataCH3( AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR3; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH4 -//* \brief Return the Channel 4 Converted Data -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_ADC_GetConvertedDataCH4( AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH5 -//* \brief Return the Channel 5 Converted Data -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_ADC_GetConvertedDataCH5( AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR5; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH6 -//* \brief Return the Channel 6 Converted Data -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_ADC_GetConvertedDataCH6( AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR6; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH7 -//* \brief Return the Channel 7 Converted Data -//*---------------------------------------------------------------------------- -static __inline unsigned int -AT91F_ADC_GetConvertedDataCH7( AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR7; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_CfgPMC -//* \brief Enable Peripheral clock in PMC for MC -//*---------------------------------------------------------------------------- -static __inline void -AT91F_MC_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_SYS ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPMC -//* \brief Enable Peripheral clock in PMC for DBGU -//*---------------------------------------------------------------------------- -static __inline void -AT91F_DBGU_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_SYS ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPIO -//* \brief Configure PIO controllers to drive DBGU signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_DBGU_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address - ( ( unsigned int )AT91C_PA28_DTXD ) | ( ( unsigned int )AT91C_PA27_DRXD ), // Peripheral A - 0 ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH3_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH3 signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PWMC_CH3_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address - ( ( unsigned int )AT91C_PB22_PWM3 ), // Peripheral A - ( ( unsigned int )AT91C_PB30_PWM3 ) ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH2_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH2 signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PWMC_CH2_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address - ( ( unsigned int )AT91C_PB21_PWM2 ), // Peripheral A - ( ( unsigned int )AT91C_PB29_PWM2 ) ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH1_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH1 signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PWMC_CH1_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address - ( ( unsigned int )AT91C_PB20_PWM1 ), // Peripheral A - ( ( unsigned int )AT91C_PB28_PWM1 ) ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH0_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH0 signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PWMC_CH0_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address - ( ( unsigned int )AT91C_PB19_PWM0 ), // Peripheral A - ( ( unsigned int )AT91C_PB27_PWM0 ) ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EMAC_CfgPMC -//* \brief Enable Peripheral clock in PMC for EMAC -//*---------------------------------------------------------------------------- -static __inline void -AT91F_EMAC_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_EMAC ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_EMAC_CfgPIO -//* \brief Configure PIO controllers to drive EMAC signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_EMAC_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address - ( ( unsigned int )AT91C_PB9_EMDIO ) | ( ( unsigned int )AT91C_PB17_ERXCK ) | ( ( unsigned int )AT91C_PB15_ERXDV_ECRSDV ) | ( ( unsigned int )AT91C_PB8_EMDC ) | ( ( unsigned int )AT91C_PB16_ECOL ) | ( ( unsigned int )AT91C_PB7_ERXER ) | ( ( unsigned int )AT91C_PB5_ERX0 ) | ( ( unsigned int )AT91C_PB6_ERX1 ) | ( ( unsigned int )AT91C_PB13_ERX2 ) | ( ( unsigned int )AT91C_PB1_ETXEN ) | ( ( unsigned int )AT91C_PB14_ERX3 ) | ( ( unsigned int )AT91C_PB12_ETXER ) | ( ( unsigned int )AT91C_PB2_ETX0 ) | ( ( unsigned int )AT91C_PB3_ETX1 ) | ( ( unsigned int )AT91C_PB10_ETX2 ) | ( ( unsigned int )AT91C_PB18_EF100 ) | ( ( unsigned int )AT91C_PB11_ETX3 ) | ( ( unsigned int )AT91C_PB4_ECRS ) | ( ( unsigned int )AT91C_PB0_ETXCK_EREFCK ), // Peripheral A - 0 ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_CfgPMC -//* \brief Enable Peripheral clock in PMC for VREG -//*---------------------------------------------------------------------------- -static __inline void -AT91F_VREG_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_SYS ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_CfgPMC -//* \brief Enable Peripheral clock in PMC for SSC -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SSC_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_SSC ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_CfgPIO -//* \brief Configure PIO controllers to drive SSC signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SSC_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address - ( ( unsigned int )AT91C_PA23_TD ) | ( ( unsigned int )AT91C_PA21_TF ) | ( ( unsigned int )AT91C_PA25_RK ) | ( ( unsigned int )AT91C_PA24_RD ) | ( ( unsigned int )AT91C_PA26_RF ) | ( ( unsigned int )AT91C_PA22_TK ), // Peripheral A - 0 ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI1_CfgPMC -//* \brief Enable Peripheral clock in PMC for SPI1 -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SPI1_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_SPI1 ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI1_CfgPIO -//* \brief Configure PIO controllers to drive SPI1 signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SPI1_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ( ( unsigned int )AT91C_PA23_SPI1_MOSI ) | ( ( unsigned int )AT91C_PA21_SPI1_NPCS0 ) | ( ( unsigned int )AT91C_PA25_SPI1_NPCS1 ) | ( ( unsigned int )AT91C_PA2_SPI1_NPCS1 ) | ( ( unsigned int )AT91C_PA24_SPI1_MISO ) | ( ( unsigned int )AT91C_PA22_SPI1_SPCK ) | ( ( unsigned int )AT91C_PA26_SPI1_NPCS2 ) | ( ( unsigned int )AT91C_PA3_SPI1_NPCS2 ) | ( ( unsigned int )AT91C_PA29_SPI1_NPCS3 ) | ( ( unsigned int )AT91C_PA4_SPI1_NPCS3 ) ); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ( ( unsigned int )AT91C_PB10_SPI1_NPCS1 ) | ( ( unsigned int )AT91C_PB11_SPI1_NPCS2 ) | ( ( unsigned int )AT91C_PB16_SPI1_NPCS3 ) ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI0_CfgPMC -//* \brief Enable Peripheral clock in PMC for SPI0 -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SPI0_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_SPI0 ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI0_CfgPIO -//* \brief Configure PIO controllers to drive SPI0 signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_SPI0_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address - ( ( unsigned int )AT91C_PA17_SPI0_MOSI ) | ( ( unsigned int )AT91C_PA12_SPI0_NPCS0 ) | ( ( unsigned int )AT91C_PA13_SPI0_NPCS1 ) | ( ( unsigned int )AT91C_PA16_SPI0_MISO ) | ( ( unsigned int )AT91C_PA14_SPI0_NPCS2 ) | ( ( unsigned int )AT91C_PA18_SPI0_SPCK ) | ( ( unsigned int )AT91C_PA15_SPI0_NPCS3 ), // Peripheral A - ( ( unsigned int )AT91C_PA7_SPI0_NPCS1 ) | ( ( unsigned int )AT91C_PA8_SPI0_NPCS2 ) | ( ( unsigned int )AT91C_PA9_SPI0_NPCS3 ) ); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ( ( unsigned int )AT91C_PB13_SPI0_NPCS1 ) | ( ( unsigned int )AT91C_PB14_SPI0_NPCS2 ) | ( ( unsigned int )AT91C_PB17_SPI0_NPCS3 ) ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PWMC -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PWMC_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_PWMC ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC0 -//*---------------------------------------------------------------------------- -static __inline void -AT91F_TC0_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_TC0 ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPIO -//* \brief Configure PIO controllers to drive TC0 signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_TC0_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address - ( ( unsigned int )AT91C_PB23_TIOA0 ) | ( ( unsigned int )AT91C_PB24_TIOB0 ), // Peripheral A - ( ( unsigned int )AT91C_PB12_TCLK0 ) ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC1 -//*---------------------------------------------------------------------------- -static __inline void -AT91F_TC1_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_TC1 ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPIO -//* \brief Configure PIO controllers to drive TC1 signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_TC1_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address - ( ( unsigned int )AT91C_PB25_TIOA1 ) | ( ( unsigned int )AT91C_PB26_TIOB1 ), // Peripheral A - ( ( unsigned int )AT91C_PB19_TCLK1 ) ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC2 -//*---------------------------------------------------------------------------- -static __inline void -AT91F_TC2_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_TC2 ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPIO -//* \brief Configure PIO controllers to drive TC2 signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_TC2_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ( ( unsigned int )AT91C_PA15_TCLK2 ) ); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address - ( ( unsigned int )AT91C_PB27_TIOA2 ) | ( ( unsigned int )AT91C_PB28_TIOB2 ), // Peripheral A - 0 ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PITC -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PITC_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_SYS ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgPMC -//* \brief Enable Peripheral clock in PMC for ADC -//*---------------------------------------------------------------------------- -static __inline void -AT91F_ADC_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_ADC ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgPIO -//* \brief Configure PIO controllers to drive ADC signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_ADC_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ( ( unsigned int )AT91C_PB18_ADTRG ) ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PMC -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PMC_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_SYS ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPIO -//* \brief Configure PIO controllers to drive PMC signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PMC_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ( ( unsigned int )AT91C_PA13_PCK1 ) | ( ( unsigned int )AT91C_PA30_PCK2 ) | ( ( unsigned int )AT91C_PA27_PCK3 ) ); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address - ( ( unsigned int )AT91C_PB29_PCK1 ) | ( ( unsigned int )AT91C_PB30_PCK2 ), // Peripheral A - ( ( unsigned int )AT91C_PB21_PCK1 ) | ( ( unsigned int )AT91C_PB22_PCK2 ) | ( ( unsigned int )AT91C_PB20_PCK0 ) | ( ( unsigned int )AT91C_PB0_PCK0 ) ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for RSTC -//*---------------------------------------------------------------------------- -static __inline void -AT91F_RSTC_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_SYS ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RTTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for RTTC -//*---------------------------------------------------------------------------- -static __inline void -AT91F_RTTC_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_SYS ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOA_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOA -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIOA_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_PIOA ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOB_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOB -//*---------------------------------------------------------------------------- -static __inline void -AT91F_PIOB_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_PIOB ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPMC -//* \brief Enable Peripheral clock in PMC for TWI -//*---------------------------------------------------------------------------- -static __inline void -AT91F_TWI_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_TWI ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPIO -//* \brief Configure PIO controllers to drive TWI signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_TWI_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address - ( ( unsigned int )AT91C_PA10_TWD ) | ( ( unsigned int )AT91C_PA11_TWCK ), // Peripheral A - 0 ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for WDTC -//*---------------------------------------------------------------------------- -static __inline void -AT91F_WDTC_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_SYS ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPMC -//* \brief Enable Peripheral clock in PMC for US1 -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US1_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_US1 ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPIO -//* \brief Configure PIO controllers to drive US1 signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US1_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address - ( ( unsigned int )AT91C_PA5_RXD1 ) | ( ( unsigned int )AT91C_PA6_TXD1 ) | ( ( unsigned int )AT91C_PA8_RTS1 ) | ( ( unsigned int )AT91C_PA7_SCK1 ) | ( ( unsigned int )AT91C_PA9_CTS1 ), // Peripheral A - 0 ); // Peripheral B - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOB, // PIO controller base address - 0, // Peripheral A - ( ( unsigned int )AT91C_PB25_DTR1 ) | ( ( unsigned int )AT91C_PB23_DCD1 ) | ( ( unsigned int )AT91C_PB24_DSR1 ) | ( ( unsigned int )AT91C_PB26_RI1 ) ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPMC -//* \brief Enable Peripheral clock in PMC for US0 -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US0_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_US0 ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPIO -//* \brief Configure PIO controllers to drive US0 signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_US0_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address - ( ( unsigned int )AT91C_PA0_RXD0 ) | ( ( unsigned int )AT91C_PA1_TXD0 ) | ( ( unsigned int )AT91C_PA3_RTS0 ) | ( ( unsigned int )AT91C_PA2_SCK0 ) | ( ( unsigned int )AT91C_PA4_CTS0 ), // Peripheral A - 0 ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_CfgPMC -//* \brief Enable Peripheral clock in PMC for UDP -//*---------------------------------------------------------------------------- -static __inline void -AT91F_UDP_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_UDP ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPMC -//* \brief Enable Peripheral clock in PMC for AIC -//*---------------------------------------------------------------------------- -static __inline void -AT91F_AIC_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_IRQ0 ) | - ( ( unsigned int )1 << AT91C_ID_FIQ ) | ( ( unsigned int )1 << AT91C_ID_IRQ1 ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPIO -//* \brief Configure PIO controllers to drive AIC signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_AIC_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address - ( ( unsigned int )AT91C_PA30_IRQ0 ) | ( ( unsigned int )AT91C_PA29_FIQ ), // Peripheral A - ( ( unsigned int )AT91C_PA14_IRQ1 ) ); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgPMC -//* \brief Enable Peripheral clock in PMC for CAN -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CAN_CfgPMC( void ) -{ - AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, // PIO controller base address - ( ( unsigned int )1 << AT91C_ID_CAN ) ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CAN_CfgPIO -//* \brief Configure PIO controllers to drive CAN signals -//*---------------------------------------------------------------------------- -static __inline void -AT91F_CAN_CfgPIO( void ) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, // PIO controller base address - ( ( unsigned int )AT91C_PA20_CANTX ) | ( ( unsigned int )AT91C_PA19_CANRX ), // Peripheral A - 0 ); // Peripheral B -} - -#endif // lib_AT91SAM7X256_H diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/system/crt0.s b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/system/crt0.s deleted file mode 100644 index 3488c5a51..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/system/crt0.s +++ /dev/null @@ -1,232 +0,0 @@ -/***************************************************************************** - * Copyright (c) 2001, 2002 Rowley Associates Limited. * - * * - * This file may be distributed under the terms of the License Agreement * - * provided with this software. * - * * - * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * - * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - *****************************************************************************/ - -/***************************************************************************** - * Preprocessor Definitions - * ------------------------ - * APP_ENTRY_POINT - * - * Defines the application entry point function, if undefined this setting - * defaults to "main". - * - * INITIALIZE_STACKS - * - * If defined, the contents of the stacks will be initialized to a the - * value 0xCC. - * - * INITIALIZE_SECONDARY_SECTIONS - * - * If defined, the .text2, .data2 and .bss2 sections will be initialized. - * - * SUPERVISOR_START - * - * If defined, the application will start up in supervisor mode. If - * undefined the application will start up in system mode. - * - *****************************************************************************/ - - .section .init, "ax" - .code 32 - .align 4 - -#ifndef APP_ENTRY_POINT -#define APP_ENTRY_POINT main -#endif - - .weak _start - .global __start - .global __gccmain - .extern APP_ENTRY_POINT - .extern exit - -/***************************************************************************** - * Function : _start * - * Description : Main entry point and startup code for C system. * - *****************************************************************************/ -_start: -__start: - mrs r0, cpsr - bic r0, r0, #0x1F - - /* Setup stacks */ - orr r1, r0, #0x1B /* Undefined mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_und_end__ - - orr r1, r0, #0x17 /* Abort mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_abt_end__ - - orr r1, r0, #0x12 /* IRQ mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_irq_end__ - - orr r1, r0, #0x11 /* FIQ mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_fiq_end__ - - orr r1, r0, #0x13 /* Supervisor mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_svc_end__ -#ifdef SUPERVISOR_START - /* Start application in supervisor mode */ - ldr r1, =__stack_end__ /* Setup user/system mode stack */ - mov r2, sp - stmfd r2!, {r1} - ldmfd r2, {sp}^ -#else - /* Start application in system mode */ - orr r1, r0, #0x1F /* System mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_end__ -#endif - -#ifdef INITIALIZE_STACKS - mov r2, #0xCC - ldr r0, =__stack_und_start__ - ldr r1, =__stack_und_end__ - bl memory_set - ldr r0, =__stack_abt_start__ - ldr r1, =__stack_abt_end__ - bl memory_set - ldr r0, =__stack_irq_start__ - ldr r1, =__stack_irq_end__ - bl memory_set - ldr r0, =__stack_fiq_start__ - ldr r1, =__stack_fiq_end__ - bl memory_set - ldr r0, =__stack_svc_start__ - ldr r1, =__stack_svc_end__ - bl memory_set - ldr r0, =__stack_start__ - ldr r1, =__stack_end__ - bl memory_set -#endif - - /* Copy from initialised data section to data section (if necessary). */ - ldr r0, =__data_load_start__ - ldr r1, =__data_start__ - ldr r2, =__data_end__ - bl memory_copy - - /* Copy from initialised text section to text section (if necessary). */ - ldr r0, =__text_load_start__ - ldr r1, =__text_start__ - ldr r2, =__text_end__ - bl memory_copy - - /* Copy from initialised fast_text section to fast_text section (if necessary). */ - ldr r0, =__fast_load_start__ - ldr r1, =__fast_start__ - ldr r2, =__fast_end__ - bl memory_copy - - /* Zero the bss. */ - ldr r0, =__bss_start__ - ldr r1, =__bss_end__ - mov r2, #0 - bl memory_set - -#ifdef INITIALIZE_SECONDARY_SECTIONS - ldr r0, =__data2_load_start__ - ldr r1, =__data2_start__ - ldr r2, =__data2_end__ - bl memory_copy - - /* Copy from initialised text2 section to text2 section (if necessary). */ - ldr r0, =__text2_load_start__ - ldr r1, =__text2_start__ - ldr r2, =__text2_end__ - bl memory_copy - - /* Zero bss2. */ - ldr r0, =__bss2_start__ - ldr r1, =__bss2_end__ - mov r2, #0 - bl memory_set - -#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */ - - /* Initialise the heap */ - ldr r0, = __heap_start__ - ldr r1, = __heap_end__ - sub r1, r1, r0 /* r1 = r1-r0 */ - mov r2, #0 - str r2, [r0], #+4 /* *r0++ = 0 */ - str r1, [r0] /* *r0 = __heap_end__ - __heap_start__ */ - - /* Call constructors */ - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ -ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #+4 - stmfd sp!, {r0-r1} - mov lr, pc - mov pc, r2 - ldmfd sp!, {r0-r1} - b ctor_loop -ctor_end: - - /* Setup initial call frame */ - mov lr, #4 - mov r12, sp - stmfd sp!, {r11-r12, lr-pc} - sub r11, r12, #0x00000004 - -start: - /* Jump to application entry point */ - mov r0, #0 - mov r1, #0 - ldr r2, =APP_ENTRY_POINT - mov lr, pc -#ifdef __ARM_ARCH_3__ - mov pc, r2 -#else - bx r2 -#endif - - /* Call destructors */ - ldr r0, =__dtors_start__ - ldr r1, =__dtors_end__ -dtor_loop: - cmp r0, r1 - beq dtor_end - ldr r2, [r0], #+4 - stmfd sp!, {r0-r1} - mov lr, pc - mov pc, r2 - ldmfd sp!, {r0-r1} - b dtor_loop -dtor_end: - - /* Returned from application entry point, loop forever. */ -exit_loop: - b exit_loop - -memory_copy: - cmp r0, r1 - moveq pc, lr - subs r2, r2, r1 - moveq pc, lr -1: - ldrb r3, [r0], #+1 - strb r3, [r1], #+1 - subs r2, r2, #1 - bne 1b - mov pc, lr - -memory_set: - cmp r0, r1 - moveq pc, lr - strb r2, [r0], #1 - b memory_set - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/system/startup.s b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/system/startup.s deleted file mode 100644 index ce619a060..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AT91SAM7X_ROWLEY/system/startup.s +++ /dev/null @@ -1,236 +0,0 @@ -/***************************************************************************** - Exception handlers and startup code for Atmel AT91SAM7. - - Copyright (c) 2004 Rowley Associates Limited. - - This file may be distributed under the terms of the License Agreement - provided with this software. - - THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE - WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. - *****************************************************************************/ - -/***************************************************************************** - * Preprocessor Definitions - * ------------------------ - * - * VECTORED_IRQ_INTERRUPTS - * - * Enable vectored IRQ interrupts. If defined, the PC register will be loaded - * with the contents of the AIC_IVR register on an IRQ exception. - * - * STARTUP_FROM_RESET - * - * If defined, the program will startup from power-on/reset. If not defined - * the program will just loop endlessly from power-on/reset. - * - * This definition is not defined by default on this target because the - * debugger is unable to reset this target and maintain control of it over the - * JTAG interface. The advantage of doing this is that it allows the debugger - * to reset the CPU and run programs from a known reset CPU state on each run. - * It also acts as a safety net if you accidently download a program in FLASH - * that crashes and prevents the debugger from taking control over JTAG - * rendering the target unusable over JTAG. The obvious disadvantage of doing - * this is that your application will not startup without the debugger. - * - * We advise that on this target you keep STARTUP_FROM_RESET undefined whilst - * you are developing and only define STARTUP_FROM_RESET when development is - * complete. - * - * MC_FMR_FMCN_VAL - * - * Override the default Flash Mode Register FMCN value by defining - * MC_FMR_FMCN_VAL. - * - * MC_FMR_FWS_VAL - * - * Override the default Flash Mode Register FWS value by defining - * MC_FMR_FWS_VAL. - * - * CKGR_MOR_VAL - * - * Override the default Main Oscillator Register value by defining - * CKGR_MOR_VAL. - * - * CKGR_PLLR_VAL - * - * Override the default Clock Generator PLL Register value by defining - * CKGR_PLLR_VAL. - * - * NO_WATCHDOG_DISABLE - * - * If defined, the watchdog will not be disabled. - * - * NO_USER_RESET - * - * If defined, user reset will not be enabled. - * - * NO_PROTECTION_MODE - * - * If defined, AIC protection mode will not be enabled. AIC protection - * mode allows the AIC_IVR register to be accessed by the debugger (for - * example through the memory or register window). With protection mode - * disabled accesses of the AIC_IVR register by the debugger are likely - * to disrupt interrupt behaviour. - * - *****************************************************************************/ - -#include - -#ifndef MC_FMR_FMCN_VAL -#define MC_FMR_FMCN_VAL 72 -#endif - -#ifndef MC_FMR_FWS_VAL -#define MC_FMR_FWS_VAL 1 -#endif - -#ifndef CKGR_MOR_VAL -#define CKGR_MOR_VAL (0x40 << CKGR_MOR_OSCOUNT_BIT) | CKGR_MOR_MOSCEN -#endif - -#ifndef CKGR_PLLR_VAL -#if OSCILLATOR_CLOCK_FREQUENCY==18432000 -/* MCK, UDPCK = 18.432MHz * 73 / 14 / 2 = 48.05486MHz */ -#define CKGR_PLLR_VAL (1 << CKGR_PLLR_USBDIV_BIT) | (72 << CKGR_PLLR_MUL_BIT) | (0 << CKGR_PLLR_OUT_BIT) | (63 << CKGR_PLLR_PLLCOUNT_BIT) | (14 << CKGR_PLLR_DIV_BIT) -#else -#error OSCILLATOR_CLOCK_FREQUENCY not supported -#endif -#endif - - .section .vectors, "ax" - .code 32 - .align 0 - .global _vectors - .global reset_handler - -/***************************************************************************** - Exception Vectors - *****************************************************************************/ -_vectors: -#ifdef STARTUP_FROM_RESET - ldr pc, [pc, #reset_handler_address - . - 8] /* reset */ -#else - b . /* reset - infinite loop */ -#endif - ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */ - ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */ - ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */ - ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */ - nop - ldr pc, [pc, #-0xF20] /* irq */ - ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq */ - -reset_handler_address: - .word reset_handler -undef_handler_address: - .word undef_handler -swi_handler_address: - .word swi_handler -pabort_handler_address: - .word pabort_handler -dabort_handler_address: - .word dabort_handler -irq_handler_address: - .word irq_handler -fiq_handler_address: - .word fiq_handler - - .section .init, "ax" - .code 32 - .align 0 - -/****************************************************************************** - Reset handler - ******************************************************************************/ -reset_handler: - /* Set up FLASH wait state */ - ldr r1, =MC_BASE - ldr r0, =(MC_FMR_FMCN_VAL << MC_FMR_FMCN_BIT) | (MC_FMR_FWS_VAL << MC_FMR_FWS_BIT) - str r0, [r1, #MC_FMR_OFFSET] - - /* Disable Watchdog */ - ldr r1, =WDT_BASE - ldr r0, =WDT_MR_WDDIS - str r0, [r1, #WDT_MR_OFFSET] - -#ifndef NO_PROTECTION_MODE - /* Enable protect mode */ - ldr r1, =AIC_BASE - ldr r0, =0x00000001 - str r0, [r1, #AIC_DCR_OFFSET] -#endif - - /* Enable the main oscillator */ - ldr r1, =PMC_BASE - ldr r0, =CKGR_MOR_VAL - str r0, [r1, #CKGR_MOR_OFFSET] - -1:/* Wait for main oscillator to stabilize */ - ldr r0, [r1, #PMC_SR_OFFSET] - tst r0, #PMC_SR_MOSCS - beq 1b - - /* Set up the PLL */ - ldr r0, =CKGR_PLLR_VAL - str r0, [r1, #CKGR_PLLR_OFFSET] - -1:/* Wait for PLL to lock */ - ldr r0, [r1, #PMC_SR_OFFSET] - tst r0, #PMC_SR_LOCK - beq 1b - - /* Set the master clock prescaler */ - ldr r0, =(1 << PMC_MCKR_PRES_BIT) - str r0, [r1, #PMC_MCKR_OFFSET] - -1:/* Wait for MCKRDY */ - ldr r0, [r1, #PMC_SR_OFFSET] - tst r0, #PMC_SR_MCKRDY - beq 1b - - /* Select PLL as clock source */ - ldr r0, =((1 << PMC_MCKR_PRES_BIT) | 3 << PMC_MCKR_CSS_BIT) - str r0, [r1, #PMC_MCKR_OFFSET] - -#ifdef __FLASH_BUILD - /* Copy exception vectors into Internal SRAM */ - mov r8, #0x00200000 - ldr r9, =_vectors - ldmia r9!, {r0-r7} - stmia r8!, {r0-r7} - ldmia r9!, {r0-r6} - stmia r8!, {r0-r6} - - /* Remap Internal SRAM to 0x00000000 */ - ldr r1, =MC_BASE - ldr r0, =1 - strb r0, [r1, #MC_RCR_OFFSET] -#endif - - /* Jump to the default C runtime startup code. */ - b _start - -/****************************************************************************** - Default exception handlers - (These are declared weak symbols so they can be redefined in user code) - ******************************************************************************/ -undef_handler: - b . /* Endless loop */ - -swi_handler: - b . /* Endless loop */ - -pabort_handler: - b . /* Endless loop */ - -dabort_handler: - b . /* Endless loop */ - -irq_handler: - b . /* Endless loop */ - -fiq_handler: - b . /* Endless loop */ - - .weak undef_handler, swi_handler, pabort_handler, dabort_handler, irq_handler, fiq_handler diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/README.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/README.txt deleted file mode 100644 index 49e53ec6e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/README.txt +++ /dev/null @@ -1,68 +0,0 @@ - - FREEMODBUS 1.5 ATSAM3S EXAMPLE - ============================== - -REQUIREMENTS -============ - -This example contains a simple demo program for FreeMODBUS for the AT91SAM3S -Cortex M3 controllers on the SAM3S-EK [0] evaluation kit. It requires a wired -RS485 connection to a host processor and a MODBUS master software on the PC -side to be useful. Demo versions of MODBUS master stacks can be found in -[1], [2] and [3]. Commercial MODBUS stacks are available from [4]. - -INSTALLATION -============ -The SAM3S-EK evaluation board should be modified as following to enable RS485 -data transmission. - - - Place Jumpers JP11, JP10 and JP12 - - Place a solder drop accross R25 - -Warning: The RS485 shares data lines with USART1. It is therefore absolutely -necessary to set PA23 to a high level. - -SOURCE -====== - -TESTING -======= - -Start the MODBUS sample application and test if the input registers starting -at protocol address 1000 can be read. There are four registers values avai- -lable and the output should look like: - -Polling slave (Ctrl-C to stop) ... -[1000]: 6474 -[1001]: 0 -[1002]: 0 -[1003]: 0 -Polling slave (Ctrl-C to stop) ... -[1000]: -8831 -[1001]: 0 -[1002]: 0 -[1003]: 0 -Polling slave (Ctrl-C to stop) ... - -The simple testing utility used in the 'demo_rtu.bat' script can be found at -[3]. - -PROBLEMS -======== - -In case you can get no communication working make sure that the RS485 line is -biased correctly. The SAM3S-EK does not populate the RS485 bias resistors by -default and if you have a RS485 master which does not bias the lines either -you will get wrong characters. For this R24 and R30 on the bottom side of the -evaluation kit of the PCB should be populated. - -REFERENCES -========== - -[0] Atmel SAM3S-EK: http://www.atmel.com/dyn/products/tools_card_v2.asp?tool_id=4678 -[1] WinTech ModScan32: http://www.win-tech.com/html/modscan32.htm -[2] Modus Poll: http://www.modbustools.com/modbus_poll.asp -[3] FieldTalk Modpoll: http://www.focus-sw.com/fieldtalk/modpoll.html -[4] Embedded Solutions: http://www.embedded-solutions.at - -Version: $Id: README.txt,v 1.1 2010/06/05 09:57:46 wolti Exp $ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/AT91SAM3S4.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/AT91SAM3S4.h deleted file mode 100644 index a11e72a34..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/AT91SAM3S4.h +++ /dev/null @@ -1,7010 +0,0 @@ -/* ---------------------------------------------------------------------------- */ -/* Atmel Microcontroller Software Support */ -/* ---------------------------------------------------------------------------- */ -/* Copyright (c) 2009, Atmel Corporation */ -/* */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following condition is met: */ -/* */ -/* - Redistributions of source code must retain the above copyright notice, */ -/* this list of conditions and the disclaimer below. */ -/* */ -/* Atmel's name may not be used to endorse or promote products derived from */ -/* this software without specific prior written permission. */ -/* */ -/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ -/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ -/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ -/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ -/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ -/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ -/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ -/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ -/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* ---------------------------------------------------------------------------- */ -/* */ -/* File Name : AT91SAM3S.h */ -/* Object : AT91SAM3S definitions */ -/* Generated by : AT91 SW Application Group */ -/* Generated on : 2009-10-26 */ - -#ifndef AT91SAM3S_H -#define AT91SAM3S_H - -/** \addtogroup AT91SAM3S_definitions AT91SAM3S definitions - This file defines all structures and symbols for AT91SAM3S: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __ASSEMBLY__ -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *) value) -#define REG_ACCESS(type, address) (*(type*)address) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ***************************************************************************** */ -/* CMSIS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_cmsis CMSIS Definitions */ - -/*@{*/ - -/** - * \brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __MPU_PRESENT 0 /**< AT91SAM3S does not provide a MPU present or not */ -#define __NVIC_PRIO_BITS 4 /**< AT91SAM3S uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ -/****** AT91SAM3S specific Interrupt Numbers *****************************************/ - - SUPC_IRQn = 0, /**< 0 AT91SAM3S Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 AT91SAM3S Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 AT91SAM3S Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 AT91SAM3S Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 AT91SAM3S Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 AT91SAM3S Power Management Controller (PMC) */ - EFC_IRQn = 6, /**< 6 AT91SAM3S Enhanced Flash Controller (EFC) */ - UART0_IRQn = 8, /**< 8 AT91SAM3S UART 0 (UART0) */ - UART1_IRQn = 9, /**< 9 AT91SAM3S UART 1 (UART1) */ - SMC_IRQn = 10, /**< 10 AT91SAM3S Static Memory Controller (SMC) */ - PIOA_IRQn = 11, /**< 11 AT91SAM3S Parallel I/O Controller A (PIOA) */ - PIOB_IRQn = 12, /**< 12 AT91SAM3S Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 13, /**< 13 AT91SAM3S Parallel I/O Controller C (PIOC) */ - USART0_IRQn = 14, /**< 14 AT91SAM3S USART 0 (USART0) */ - USART1_IRQn = 15, /**< 15 AT91SAM3S USART 1 (USART1) */ - HSMCI_IRQn = 18, /**< 18 AT91SAM3S Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 19, /**< 19 AT91SAM3S Two Wire Interface 0 (TWI0) */ - TWI1_IRQn = 20, /**< 20 AT91SAM3S Two Wire Interface 1 (TWI1) */ - SPI_IRQn = 21, /**< 21 AT91SAM3S Serial Peripheral Interface (SPI) */ - SSC_IRQn = 22, /**< 22 AT91SAM3S Synchronous Serial Controler (SSC) */ - TC0_IRQn = 23, /**< 23 AT91SAM3S Timer/Counter 0 (TC0) */ - TC1_IRQn = 24, /**< 24 AT91SAM3S Timer/Counter 1 (TC1) */ - TC2_IRQn = 25, /**< 25 AT91SAM3S Timer/Counter 2 (TC2) */ - TC3_IRQn = 26, /**< 26 AT91SAM3S Timer/Counter 3 (TC3) */ - TC4_IRQn = 27, /**< 27 AT91SAM3S Timer/Counter 4 (TC4) */ - TC5_IRQn = 28, /**< 28 AT91SAM3S Timer/Counter 5 (TC5) */ - ADC_IRQn = 29, /**< 29 AT91SAM3S Analog To Digital Converter (ADC) */ - DACC_IRQn = 30, /**< 30 AT91SAM3S Digital To Analog Converter (DACC) */ - PWM_IRQn = 31, /**< 31 AT91SAM3S Pulse Width Modulation (PWM) */ - CRCCU_IRQn = 32, /**< 32 AT91SAM3S CRC Calculation Unit (CRCCU) */ - ACC_IRQn = 33, /**< 33 AT91SAM3S Analog Comparator (ACC) */ - UDP_IRQn = 34 /**< 34 AT91SAM3S USB Device Port (UDP) */ -} IRQn_Type; -/*@}*/ - -/* ***************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_api Peripheral Software API */ -/*@{*/ -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_ACC Analog Comparator Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Acc hardware registers */ -typedef struct { - WoReg ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ - RwReg ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ - RwReg Reserved1[7]; - WoReg ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ - WoReg ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ - RoReg ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ - RoReg ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved2[24]; - RwReg ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ - RwReg Reserved3[19]; - RwReg ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */ - RoReg ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */ -} Acc; -#endif /* __ASSEMBLY__ */ -/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ -#define ACC_CR_SWRST (0x1 << 0) /**< \brief (ACC_CR) SoftWare ReSeT */ -/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ -#define ACC_MR_SELPLUS (0x7 << 0) /**< \brief (ACC_MR) SELection for PLUS comparator input */ -#define ACC_MR_SELMINUS (0x7 << 4) /**< \brief (ACC_MR) SELection for MINUS comparator input */ -#define ACC_MR_ACEN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ -#define ACC_MR_ACEN_EN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ -#define ACC_MR_ACEN_DIS (0x0 << 8) /**< \brief (ACC_MR) Analog Comparator Disable */ -#define ACC_MR_EDGETYP (0x3 << 9) /**< \brief (ACC_MR) EDGE TYPe */ -#define ACC_MR_EDGETYP_RISING (0x0 << 9) /**< \brief (ACC_MR) EDGE TYPe ,RISING edge*/ -#define ACC_MR_EDGETYP_FALLING (0x1 << 9) /**< \brief (ACC_MR) EDGE TYPe,falling edge */ -#define ACC_MR_EDGETYP_ANY (0x2 << 9) /**< \brief (ACC_MR) EDGE TYPe,any edge */ -#define ACC_MR_INV (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ -#define ACC_MR_INV_EN (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ -#define ACC_MR_INV_DIS (0x0 << 12) /**< \brief (ACC_MR) DIRECTLY */ -#define ACC_MR_SELFS (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_SELFS_CF (0x0 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_SELFS_OUTPUT (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_FE (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ -#define ACC_MR_FE_EN (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ -#define ACC_MR_FE_DIS (0x0 << 14) /**< \brief (ACC_MR) Fault Enable */ -/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ -#define ACC_IER_CE (0x1 << 0) /**< \brief (ACC_IER) Comparison Edge */ -/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ -#define ACC_IDR_CE (0x1 << 0) /**< \brief (ACC_IDR) Comparison Edge */ -/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ -#define ACC_IMR_CE (0x1 << 0) /**< \brief (ACC_IMR) Comparison Edge */ -/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ -#define ACC_ISR_CE (0x1 << 0) /**< \brief (ACC_ISR) Comparison Edge */ -#define ACC_ISR_SCO (0x1 << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ -#define ACC_ISR_MASK (0x1 << 31) /**< \brief (ACC_ISR) */ -/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ -#define ACC_ACR_ISEL (0x1 << 0) /**< \brief (ACC_ACR) Current SELection */ -#define ACC_ACR_HYST (0x3 << 1) /**< \brief (ACC_ACR) HYSTeresis selection */ -/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */ -#define ACC_WPMR_WPEN (0x1 << 0) /**< \brief (ACC_WPMR) Write Protect Enable */ -#define ACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ACC_WPMR) Write Protect KEY */ -/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */ -#define ACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_ADC Analog-to-digital Converter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Adc hardware registers */ -typedef struct { - WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */ - RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */ - RwReg ADC_SEQ1R; /**< \brief (Adc Offset: 0x08) Channel Sequence 1Register */ - RwReg ADC_SEQ2R; /**< \brief (Adc Offset: 0x0C) Channel Sequence 2 Register */ - WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */ - WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */ - RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */ - RwReg Reserved1[1]; - RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */ - WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */ - WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */ - RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */ - RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved2[2]; - RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */ - RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */ - RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */ - RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */ - RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */ - RoReg ADC_CDR0; /**< \brief (Adc Offset: 0x50) Channel Data Register 0 */ - RoReg ADC_CDR1; /**< \brief (Adc Offset: 0x54) Channel Data Register 1 */ - RoReg ADC_CDR2; /**< \brief (Adc Offset: 0x58) Channel Data Register 2 */ - RoReg ADC_CDR3; /**< \brief (Adc Offset: 0x5C) Channel Data Register 3 */ - RoReg ADC_CDR4; /**< \brief (Adc Offset: 0x60) Channel Data Register 4 */ - RoReg ADC_CDR5; /**< \brief (Adc Offset: 0x64) Channel Data Register 5 */ - RoReg ADC_CDR6; /**< \brief (Adc Offset: 0x68) Channel Data Register 6 */ - RoReg ADC_CDR7; /**< \brief (Adc Offset: 0x6C) Channel Data Register 7 */ - RoReg ADC_CDR8; /**< \brief (Adc Offset: 0x70) Channel Data Register 8 */ - RoReg ADC_CDR9; /**< \brief (Adc Offset: 0x74) Channel Data Register 9 */ - RoReg ADC_CDR10; /**< \brief (Adc Offset: 0x78) Channel Data Register 10 */ - RoReg ADC_CDR11; /**< \brief (Adc Offset: 0x7C) Channel Data Register 11 */ - RoReg ADC_CDR12; /**< \brief (Adc Offset: 0x80) Channel Data Register 12 */ - RoReg ADC_CDR13; /**< \brief (Adc Offset: 0x84) Channel Data Register 13 */ - RoReg ADC_CDR14; /**< \brief (Adc Offset: 0x88) Channel Data Register 14 */ - RoReg ADC_CDR15; /**< \brief (Adc Offset: 0x8C) Channel Data Register 15 */ - RwReg Reserved3[1]; - RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */ - RwReg Reserved4[19]; - RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */ - RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved5[5]; - RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */ - RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */ - RwReg ADC_TPR; /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */ - RwReg ADC_TCR; /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */ - RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */ - RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */ - RwReg ADC_TNPR; /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */ - RwReg ADC_TNCR; /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */ - WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */ - RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */ -} Adc; -#endif /* __ASSEMBLY__ */ -/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ -#define ADC_CR_SWRST (0x1 << 0) /**< \brief (ADC_CR) Software Reset */ -#define ADC_CR_START (0x1 << 1) /**< \brief (ADC_CR) Start Conversion */ -/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ -#define ADC_MR_TRGEN (0x1 << 0) /**< \brief (ADC_MR) Trigger Enable */ -#define ADC_MR_TRGEN_DIS (0x0 << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software.*/ -#define ADC_MR_TRGEN_EN (0x1) /**< (ADC) Hardware trigger selected by TRGSEL field is enabled.*/ -#define ADC_MR_TRGSEL (0x7 << 1) /**< \brief (ADC_MR) Trigger Selection */ -#define ADC_MR_TRGSEL_EXT (0x0 << 1) /**< \brief (ADC_MR) Selected TRGSEL = External Trigger*/ -#define ADC_MR_TRGSEL_TIOA0 (0x1 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO0*/ -#define ADC_MR_TRGSEL_TIOA1 (0x2 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO1*/ -#define ADC_MR_TRGSEL_TIOA2 (0x3 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO2*/ -#define ADC_MR_TRGSEL_PWM0_TRIG (0x4 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM trigger*/ -#define ADC_MR_TRGSEL_PWM1_TRIG (0x5 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM Trigger*/ -#define ADC_MR_TRGSEL_RESERVED (0x6 << 1) /**< \brief (ADC_MR) Selected TRGSEL = Reserved*/ -#define ADC_MR_LOWRES (0x1 << 4) /**< \brief (ADC_MR) Resolution */ -#define ADC_MR_LOWRES_12_BIT (0x0 << 4) /**< \brief (ADC_MR) 12-bit resolution*/ -#define ADC_MR_LOWRES_10_BIT (0x1 << 4) /**< \brief (ADC_MR) 10-bit resolution*/ -#define ADC_MR_SLEEP (0x1 << 5) /**< \brief (ADC_MR) Sleep Mode */ -#define ADC_MR_SLEEP_NORMAL (0x0 << 5) /**< \brief (ADC12B) Normal Mode*/ -#define ADC_MR_FWUP (0x1 << 6) /**< \brief (ADC_MR) Fast Wake Up */ -#define ADC_MR_FREERUN (0x1 << 7) /**< \brief (ADC_MR) Free Run Mode */ -#define ADC_MR_PRESCAL (0xff << 8) /**< \brief (ADC_MR) Prescaler Rate Selection */ -#define ADC_MR_STARTUP (0xf << 16) /**< \brief (ADC_MR) Start Up Time */ -#define ADC_MR_SETTLING (0x3 << 20) /**< \brief (ADC_MR) Analog Settling Time */ -#define ADC_MR_ANACH (0x1 << 23) /**< \brief (ADC_MR) Analog Change */ -#define ADC_MR_TRACKTIM (0xf << 24) /**< \brief (ADC_MR) Tracking Time */ -#define ADC_MR_TRANSFER (0x3 << 28) /**< \brief (ADC_MR) */ -#define ADC_MR_USEQ (0x1 << 31) /**< \brief (ADC_MR) User Sequence Enable */ -/* -------- ADC_SEQ1R : (ADC Offset: 0x08) Channel Sequence 1Register -------- */ -#define ADC_SEQ1R_USCH1 (0x7 << 0) /**< \brief (ADC_SEQ1R) User Sequence Number 1 */ -#define ADC_SEQ1R_USCH2 (0x7 << 4) /**< \brief (ADC_SEQ1R) User Sequence Number 2 */ -#define ADC_SEQ1R_USCH3 (0x7 << 8) /**< \brief (ADC_SEQ1R) User Sequence Number 3 */ -#define ADC_SEQ1R_USCH4 (0x7 << 12) /**< \brief (ADC_SEQ1R) User Sequence Number 4 */ -#define ADC_SEQ1R_USCH5 (0x7 << 16) /**< \brief (ADC_SEQ1R) User Sequence Number 5 */ -#define ADC_SEQ1R_USCH6 (0x7 << 20) /**< \brief (ADC_SEQ1R) User Sequence Number 6 */ -#define ADC_SEQ1R_USCH7 (0x7 << 24) /**< \brief (ADC_SEQ1R) User Sequence Number 7 */ -#define ADC_SEQ1R_USCH8 (0x7 << 28) /**< \brief (ADC_SEQ1R) User Sequence Number 8 */ -/* -------- ADC_SEQ2R : (ADC Offset: 0x0C) Channel Sequence 2 Register -------- */ -#define ADC_SEQ2R_USCH9 (0x7 << 0) /**< \brief (ADC_SEQ2R) User Sequence Number 9 */ -#define ADC_SEQ2R_USCH10 (0x7 << 4) /**< \brief (ADC_SEQ2R) User Sequence Number 10 */ -#define ADC_SEQ2R_USCH11 (0x7 << 8) /**< \brief (ADC_SEQ2R) User Sequence Number 11 */ -#define ADC_SEQ2R_USCH12 (0x7 << 12) /**< \brief (ADC_SEQ2R) User Sequence Number 12 */ -#define ADC_SEQ2R_USCH13 (0x7 << 16) /**< \brief (ADC_SEQ2R) User Sequence Number 13 */ -#define ADC_SEQ2R_USCH14 (0x7 << 20) /**< \brief (ADC_SEQ2R) User Sequence Number 14 */ -#define ADC_SEQ2R_USCH15 (0x7 << 24) /**< \brief (ADC_SEQ2R) User Sequence Number 15 */ -#define ADC_SEQ2R_USCH16 (0x7 << 28) /**< \brief (ADC_SEQ2R) User Sequence Number 16 */ -/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ -#define ADC_CHER_CH0 (0x1 << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ -#define ADC_CHER_CH1 (0x1 << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ -#define ADC_CHER_CH2 (0x1 << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ -#define ADC_CHER_CH3 (0x1 << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ -#define ADC_CHER_CH4 (0x1 << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ -#define ADC_CHER_CH5 (0x1 << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ -#define ADC_CHER_CH6 (0x1 << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ -#define ADC_CHER_CH7 (0x1 << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ -#define ADC_CHER_CH8 (0x1 << 8) /**< \brief (ADC_CHER) Channel 8 Enable */ -#define ADC_CHER_CH9 (0x1 << 9) /**< \brief (ADC_CHER) Channel 9 Enable */ -#define ADC_CHER_CH10 (0x1 << 10) /**< \brief (ADC_CHER) Channel 10 Enable */ -#define ADC_CHER_CH11 (0x1 << 11) /**< \brief (ADC_CHER) Channel 11 Enable */ -#define ADC_CHER_CH12 (0x1 << 12) /**< \brief (ADC_CHER) Channel 12 Enable */ -#define ADC_CHER_CH13 (0x1 << 13) /**< \brief (ADC_CHER) Channel 13 Enable */ -#define ADC_CHER_CH14 (0x1 << 14) /**< \brief (ADC_CHER) Channel 14 Enable */ -#define ADC_CHER_CH15 (0x1 << 15) /**< \brief (ADC_CHER) Channel 15 Enable */ -/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ -#define ADC_CHDR_CH0 (0x1 << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */ -#define ADC_CHDR_CH1 (0x1 << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */ -#define ADC_CHDR_CH2 (0x1 << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */ -#define ADC_CHDR_CH3 (0x1 << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */ -#define ADC_CHDR_CH4 (0x1 << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */ -#define ADC_CHDR_CH5 (0x1 << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */ -#define ADC_CHDR_CH6 (0x1 << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */ -#define ADC_CHDR_CH7 (0x1 << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */ -#define ADC_CHDR_CH8 (0x1 << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */ -#define ADC_CHDR_CH9 (0x1 << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */ -#define ADC_CHDR_CH10 (0x1 << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */ -#define ADC_CHDR_CH11 (0x1 << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */ -#define ADC_CHDR_CH12 (0x1 << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */ -#define ADC_CHDR_CH13 (0x1 << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */ -#define ADC_CHDR_CH14 (0x1 << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */ -#define ADC_CHDR_CH15 (0x1 << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */ -/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ -#define ADC_CHSR_CH0 (0x1 << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ -#define ADC_CHSR_CH1 (0x1 << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ -#define ADC_CHSR_CH2 (0x1 << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ -#define ADC_CHSR_CH3 (0x1 << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ -#define ADC_CHSR_CH4 (0x1 << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ -#define ADC_CHSR_CH5 (0x1 << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ -#define ADC_CHSR_CH6 (0x1 << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ -#define ADC_CHSR_CH7 (0x1 << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ -#define ADC_CHSR_CH8 (0x1 << 8) /**< \brief (ADC_CHSR) Channel 8 Status */ -#define ADC_CHSR_CH9 (0x1 << 9) /**< \brief (ADC_CHSR) Channel 9 Status */ -#define ADC_CHSR_CH10 (0x1 << 10) /**< \brief (ADC_CHSR) Channel 10 Status */ -#define ADC_CHSR_CH11 (0x1 << 11) /**< \brief (ADC_CHSR) Channel 11 Status */ -#define ADC_CHSR_CH12 (0x1 << 12) /**< \brief (ADC_CHSR) Channel 12 Status */ -#define ADC_CHSR_CH13 (0x1 << 13) /**< \brief (ADC_CHSR) Channel 13 Status */ -#define ADC_CHSR_CH14 (0x1 << 14) /**< \brief (ADC_CHSR) Channel 14 Status */ -#define ADC_CHSR_CH15 (0x1 << 15) /**< \brief (ADC_CHSR) Channel 15 Status */ -/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ -#define ADC_LCDR_LDATA (0xfff << 0) /**< \brief (ADC_LCDR) Last Data Converted */ -#define ADC_LCDR_CHNB (0xf << 12) /**< \brief (ADC_LCDR) Channel Number */ -/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ -#define ADC_IER_EOC0 (0x1 << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ -#define ADC_IER_EOC1 (0x1 << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ -#define ADC_IER_EOC2 (0x1 << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ -#define ADC_IER_EOC3 (0x1 << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ -#define ADC_IER_EOC4 (0x1 << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ -#define ADC_IER_EOC5 (0x1 << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ -#define ADC_IER_EOC6 (0x1 << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ -#define ADC_IER_EOC7 (0x1 << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ -#define ADC_IER_EOC8 (0x1 << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */ -#define ADC_IER_EOC9 (0x1 << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */ -#define ADC_IER_EOC10 (0x1 << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */ -#define ADC_IER_EOC11 (0x1 << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */ -#define ADC_IER_EOC12 (0x1 << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */ -#define ADC_IER_EOC13 (0x1 << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */ -#define ADC_IER_EOC14 (0x1 << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */ -#define ADC_IER_EOC15 (0x1 << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */ -#define ADC_IER_DRDY (0x1 << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ -#define ADC_IER_GOVRE (0x1 << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ -#define ADC_IER_COMPE (0x1 << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */ -#define ADC_IER_ENDRX (0x1 << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ -#define ADC_IER_RXBUFF (0x1 << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ -/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ -#define ADC_IDR_EOC0 (0x1 << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ -#define ADC_IDR_EOC1 (0x1 << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ -#define ADC_IDR_EOC2 (0x1 << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ -#define ADC_IDR_EOC3 (0x1 << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ -#define ADC_IDR_EOC4 (0x1 << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ -#define ADC_IDR_EOC5 (0x1 << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ -#define ADC_IDR_EOC6 (0x1 << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ -#define ADC_IDR_EOC7 (0x1 << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ -#define ADC_IDR_EOC8 (0x1 << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */ -#define ADC_IDR_EOC9 (0x1 << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */ -#define ADC_IDR_EOC10 (0x1 << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */ -#define ADC_IDR_EOC11 (0x1 << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */ -#define ADC_IDR_EOC12 (0x1 << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */ -#define ADC_IDR_EOC13 (0x1 << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */ -#define ADC_IDR_EOC14 (0x1 << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */ -#define ADC_IDR_EOC15 (0x1 << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */ -#define ADC_IDR_DRDY (0x1 << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ -#define ADC_IDR_GOVRE (0x1 << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ -#define ADC_IDR_COMPE (0x1 << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */ -#define ADC_IDR_ENDRX (0x1 << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ -#define ADC_IDR_RXBUFF (0x1 << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ -/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ -#define ADC_IMR_EOC0 (0x1 << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ -#define ADC_IMR_EOC1 (0x1 << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ -#define ADC_IMR_EOC2 (0x1 << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ -#define ADC_IMR_EOC3 (0x1 << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ -#define ADC_IMR_EOC4 (0x1 << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ -#define ADC_IMR_EOC5 (0x1 << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ -#define ADC_IMR_EOC6 (0x1 << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ -#define ADC_IMR_EOC7 (0x1 << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ -#define ADC_IMR_EOC8 (0x1 << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */ -#define ADC_IMR_EOC9 (0x1 << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */ -#define ADC_IMR_EOC10 (0x1 << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */ -#define ADC_IMR_EOC11 (0x1 << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */ -#define ADC_IMR_EOC12 (0x1 << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */ -#define ADC_IMR_EOC13 (0x1 << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */ -#define ADC_IMR_EOC14 (0x1 << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */ -#define ADC_IMR_EOC15 (0x1 << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */ -#define ADC_IMR_DRDY (0x1 << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ -#define ADC_IMR_GOVRE (0x1 << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ -#define ADC_IMR_COMPE (0x1 << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */ -#define ADC_IMR_ENDRX (0x1 << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ -#define ADC_IMR_RXBUFF (0x1 << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ -/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */ -#define ADC_ISR_EOC0 (0x1 << 0) /**< \brief (ADC_ISR) End of Conversion 0 */ -#define ADC_ISR_EOC1 (0x1 << 1) /**< \brief (ADC_ISR) End of Conversion 1 */ -#define ADC_ISR_EOC2 (0x1 << 2) /**< \brief (ADC_ISR) End of Conversion 2 */ -#define ADC_ISR_EOC3 (0x1 << 3) /**< \brief (ADC_ISR) End of Conversion 3 */ -#define ADC_ISR_EOC4 (0x1 << 4) /**< \brief (ADC_ISR) End of Conversion 4 */ -#define ADC_ISR_EOC5 (0x1 << 5) /**< \brief (ADC_ISR) End of Conversion 5 */ -#define ADC_ISR_EOC6 (0x1 << 6) /**< \brief (ADC_ISR) End of Conversion 6 */ -#define ADC_ISR_EOC7 (0x1 << 7) /**< \brief (ADC_ISR) End of Conversion 7 */ -#define ADC_ISR_EOC8 (0x1 << 8) /**< \brief (ADC_ISR) End of Conversion 8 */ -#define ADC_ISR_EOC9 (0x1 << 9) /**< \brief (ADC_ISR) End of Conversion 9 */ -#define ADC_ISR_EOC10 (0x1 << 10) /**< \brief (ADC_ISR) End of Conversion 10 */ -#define ADC_ISR_EOC11 (0x1 << 11) /**< \brief (ADC_ISR) End of Conversion 11 */ -#define ADC_ISR_EOC12 (0x1 << 12) /**< \brief (ADC_ISR) End of Conversion 12 */ -#define ADC_ISR_EOC13 (0x1 << 13) /**< \brief (ADC_ISR) End of Conversion 13 */ -#define ADC_ISR_EOC14 (0x1 << 14) /**< \brief (ADC_ISR) End of Conversion 14 */ -#define ADC_ISR_EOC15 (0x1 << 15) /**< \brief (ADC_ISR) End of Conversion 15 */ -#define ADC_ISR_DRDY (0x1 << 24) /**< \brief (ADC_ISR) Data Ready */ -#define ADC_ISR_GOVRE (0x1 << 25) /**< \brief (ADC_ISR) General Overrun Error */ -#define ADC_ISR_COMPE (0x1 << 26) /**< \brief (ADC_ISR) Comparison Error */ -#define ADC_ISR_ENDRX (0x1 << 27) /**< \brief (ADC_ISR) End of RX Buffer */ -#define ADC_ISR_RXBUFF (0x1 << 28) /**< \brief (ADC_ISR) RX Buffer Full */ -/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */ -#define ADC_OVER_OVRE0 (0x1 << 0) /**< \brief (ADC_OVER) Overrun Error 0 */ -#define ADC_OVER_OVRE1 (0x1 << 1) /**< \brief (ADC_OVER) Overrun Error 1 */ -#define ADC_OVER_OVRE2 (0x1 << 2) /**< \brief (ADC_OVER) Overrun Error 2 */ -#define ADC_OVER_OVRE3 (0x1 << 3) /**< \brief (ADC_OVER) Overrun Error 3 */ -#define ADC_OVER_OVRE4 (0x1 << 4) /**< \brief (ADC_OVER) Overrun Error 4 */ -#define ADC_OVER_OVRE5 (0x1 << 5) /**< \brief (ADC_OVER) Overrun Error 5 */ -#define ADC_OVER_OVRE6 (0x1 << 6) /**< \brief (ADC_OVER) Overrun Error 6 */ -#define ADC_OVER_OVRE7 (0x1 << 7) /**< \brief (ADC_OVER) Overrun Error 7 */ -#define ADC_OVER_OVRE8 (0x1 << 8) /**< \brief (ADC_OVER) Overrun Error 8 */ -#define ADC_OVER_OVRE9 (0x1 << 9) /**< \brief (ADC_OVER) Overrun Error 9 */ -#define ADC_OVER_OVRE10 (0x1 << 10) /**< \brief (ADC_OVER) Overrun Error 10 */ -#define ADC_OVER_OVRE11 (0x1 << 11) /**< \brief (ADC_OVER) Overrun Error 11 */ -#define ADC_OVER_OVRE12 (0x1 << 12) /**< \brief (ADC_OVER) Overrun Error 12 */ -#define ADC_OVER_OVRE13 (0x1 << 13) /**< \brief (ADC_OVER) Overrun Error 13 */ -#define ADC_OVER_OVRE14 (0x1 << 14) /**< \brief (ADC_OVER) Overrun Error 14 */ -#define ADC_OVER_OVRE15 (0x1 << 15) /**< \brief (ADC_OVER) Overrun Error 15 */ -/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */ -#define ADC_EMR_CMPMODE (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode */ -#define ADC_EMR_CMPMODE_LOW (0x0 << 0) /**< \brief (ADC_EMR) Comparison Mode,lower than low threshold */ -#define ADC_EMR_CMPMODE_HIGH (0x1 << 0) /**< \brief (ADC_EMR) Comparison Mode,higher than high threshold */ -#define ADC_EMR_CMPMODE_IN (0x2 << 0) /**< \brief (ADC_EMR) Comparison Mode, in the comparison window */ -#define ADC_EMR_CMPMODE_OUT (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode, out of the comparison window */ -#define ADC_EMR_CMPSEL (0xf << 4) /**< \brief (ADC_EMR) Comparison Selected Channel */ -#define ADC_EMR_CMPALL (0x1 << 9) /**< \brief (ADC_EMR) Compare All Channels */ -#define ADC_EMR_TAG (0x1 << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */ -/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */ -#define ADC_CWR_LOWTHRES (0xfff << 0) /**< \brief (ADC_CWR) Low Threshold */ -#define ADC_CWR_HIGHTHRES (0xfff << 16) /**< \brief (ADC_CWR) High Threshold */ -/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */ -#define ADC_CGR_GAIN0 (0x3 << 0) /**< \brief (ADC_CGR) Gain for channel 0 */ -#define ADC_CGR_GAIN1 (0x3 << 2) /**< \brief (ADC_CGR) Gain for channel 1 */ -#define ADC_CGR_GAIN2 (0x3 << 4) /**< \brief (ADC_CGR) Gain for channel 2 */ -#define ADC_CGR_GAIN3 (0x3 << 6) /**< \brief (ADC_CGR) Gain for channel 3 */ -#define ADC_CGR_GAIN4 (0x3 << 8) /**< \brief (ADC_CGR) Gain for channel 4 */ -#define ADC_CGR_GAIN5 (0x3 << 10) /**< \brief (ADC_CGR) Gain for channel 5 */ -#define ADC_CGR_GAIN6 (0x3 << 12) /**< \brief (ADC_CGR) Gain for channel 6 */ -#define ADC_CGR_GAIN7 (0x3 << 14) /**< \brief (ADC_CGR) Gain for channel 7 */ -#define ADC_CGR_GAIN8 (0x3 << 16) /**< \brief (ADC_CGR) Gain for channel 8 */ -#define ADC_CGR_GAIN9 (0x3 << 18) /**< \brief (ADC_CGR) Gain for channel 9 */ -#define ADC_CGR_GAIN10 (0x3 << 20) /**< \brief (ADC_CGR) Gain for channel 10 */ -#define ADC_CGR_GAIN11 (0x3 << 22) /**< \brief (ADC_CGR) Gain for channel 11 */ -#define ADC_CGR_GAIN12 (0x3 << 24) /**< \brief (ADC_CGR) Gain for channel 12 */ -#define ADC_CGR_GAIN13 (0x3 << 26) /**< \brief (ADC_CGR) Gain for channel 13 */ -#define ADC_CGR_GAIN14 (0x3 << 28) /**< \brief (ADC_CGR) Gain for channel 14 */ -#define ADC_CGR_GAIN15 (0x3 << 30) /**< \brief (ADC_CGR) Gain for channel 15 */ -/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */ -#define ADC_COR_OFF0 (0x1 << 0) /**< \brief (ADC_COR) Offset for channel 0 */ -#define ADC_COR_OFF1 (0x1 << 1) /**< \brief (ADC_COR) Offset for channel 1 */ -#define ADC_COR_OFF2 (0x1 << 2) /**< \brief (ADC_COR) Offset for channel 2 */ -#define ADC_COR_OFF3 (0x1 << 3) /**< \brief (ADC_COR) Offset for channel 3 */ -#define ADC_COR_OFF4 (0x1 << 4) /**< \brief (ADC_COR) Offset for channel 4 */ -#define ADC_COR_OFF5 (0x1 << 5) /**< \brief (ADC_COR) Offset for channel 5 */ -#define ADC_COR_OFF6 (0x1 << 6) /**< \brief (ADC_COR) Offset for channel 6 */ -#define ADC_COR_OFF7 (0x1 << 7) /**< \brief (ADC_COR) Offset for channel 7 */ -#define ADC_COR_OFF8 (0x1 << 8) /**< \brief (ADC_COR) Offset for channel 8 */ -#define ADC_COR_OFF9 (0x1 << 9) /**< \brief (ADC_COR) Offset for channel 9 */ -#define ADC_COR_OFF10 (0x1 << 10) /**< \brief (ADC_COR) Offset for channel 10 */ -#define ADC_COR_OFF11 (0x1 << 11) /**< \brief (ADC_COR) Offset for channel 11 */ -#define ADC_COR_OFF12 (0x1 << 12) /**< \brief (ADC_COR) Offset for channel 12 */ -#define ADC_COR_OFF13 (0x1 << 13) /**< \brief (ADC_COR) Offset for channel 13 */ -#define ADC_COR_OFF14 (0x1 << 14) /**< \brief (ADC_COR) Offset for channel 14 */ -#define ADC_COR_OFF15 (0x1 << 15) /**< \brief (ADC_COR) Offset for channel 15 */ -#define ADC_COR_DIFF0 (0x1 << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */ -#define ADC_COR_DIFF1 (0x1 << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */ -#define ADC_COR_DIFF2 (0x1 << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */ -#define ADC_COR_DIFF3 (0x1 << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */ -#define ADC_COR_DIFF4 (0x1 << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */ -#define ADC_COR_DIFF5 (0x1 << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */ -#define ADC_COR_DIFF6 (0x1 << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */ -#define ADC_COR_DIFF7 (0x1 << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */ -#define ADC_COR_DIFF8 (0x1 << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */ -#define ADC_COR_DIFF9 (0x1 << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */ -#define ADC_COR_DIFF10 (0x1 << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */ -#define ADC_COR_DIFF11 (0x1 << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */ -#define ADC_COR_DIFF12 (0x1 << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */ -#define ADC_COR_DIFF13 (0x1 << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */ -#define ADC_COR_DIFF14 (0x1 << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */ -#define ADC_COR_DIFF15 (0x1 << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */ -/* -------- ADC_CDR0 : (ADC Offset: 0x50) Channel Data Register 0 -------- */ -#define ADC_CDR0_DATA (0x3ff << 0) /**< \brief (ADC_CDR0) Converted Data */ -/* -------- ADC_CDR1 : (ADC Offset: 0x54) Channel Data Register 1 -------- */ -#define ADC_CDR1_DATA (0x3ff << 0) /**< \brief (ADC_CDR1) Converted Data */ -/* -------- ADC_CDR2 : (ADC Offset: 0x58) Channel Data Register 2 -------- */ -#define ADC_CDR2_DATA (0x3ff << 0) /**< \brief (ADC_CDR2) Converted Data */ -/* -------- ADC_CDR3 : (ADC Offset: 0x5C) Channel Data Register 3 -------- */ -#define ADC_CDR3_DATA (0x3ff << 0) /**< \brief (ADC_CDR3) Converted Data */ -/* -------- ADC_CDR4 : (ADC Offset: 0x60) Channel Data Register 4 -------- */ -#define ADC_CDR4_DATA (0x3ff << 0) /**< \brief (ADC_CDR4) Converted Data */ -/* -------- ADC_CDR5 : (ADC Offset: 0x64) Channel Data Register 5 -------- */ -#define ADC_CDR5_DATA (0x3ff << 0) /**< \brief (ADC_CDR5) Converted Data */ -/* -------- ADC_CDR6 : (ADC Offset: 0x68) Channel Data Register 6 -------- */ -#define ADC_CDR6_DATA (0x3ff << 0) /**< \brief (ADC_CDR6) Converted Data */ -/* -------- ADC_CDR15 : (ADC Offset: 0x6C) Channel Data Register 15 -------- */ -#define ADC_CDR15_DATA (0x3ff << 0) /**< \brief (ADC_CDR15) Converted Data */ -/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */ -#define ADC_ACR_TSON (0x1 << 4) /**< \brief (ADC_ACR) Temperature Sensor On */ -#define ADC_ACR_IBCTL (0x3 << 8) /**< \brief (ADC_ACR) ADC Bias Current Control */ -/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */ -#define ADC_WPMR_WPEN (0x1 << 0) /**< \brief (ADC_WPMR) Write Protect Enable */ -#define ADC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ADC_WPMR) Write Protect KEY */ -/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */ -#define ADC_WPSR_WPVS (0x1 << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */ -#define ADC_WPSR_WPVSRC (0xffff << 8) /**< \brief (ADC_WPSR) Write Protect Violation Source */ -/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ -#define ADC_RPR_RXPTR (0xffffffff << 0) /**< \brief (ADC_RPR) Receive Pointer Register */ -/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */ -#define ADC_RCR_RXCTR (0xffff << 0) /**< \brief (ADC_RCR) Receive Counter Register */ -/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */ -#define ADC_TPR_TXPTR (0xffffffff << 0) /**< \brief (ADC_TPR) Transmit Counter Register */ -/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */ -#define ADC_TCR_TXCTR (0xffff << 0) /**< \brief (ADC_TCR) Transmit Counter Register */ -/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */ -#define ADC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (ADC_RNPR) Receive Next Pointer */ -/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */ -#define ADC_RNCR_RXNCTR (0xffff << 0) /**< \brief (ADC_RNCR) Receive Next Counter */ -/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define ADC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (ADC_TNPR) Transmit Next Pointer */ -/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define ADC_TNCR_TXNCTR (0xffff << 0) /**< \brief (ADC_TNCR) Transmit Counter Next */ -/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */ -#define ADC_PTCR_RXTEN (0x1 << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ -#define ADC_PTCR_RXTDIS (0x1 << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ -#define ADC_PTCR_TXTEN (0x1 << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ -#define ADC_PTCR_TXTDIS (0x1 << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ -/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */ -#define ADC_PTSR_RXTEN (0x1 << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ -#define ADC_PTSR_TXTEN (0x1 << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Chip Identifier */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_CHIPID Chip Identifier */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Chipid hardware registers */ -typedef struct { - RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ - RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ -} Chipid; -#endif /* __ASSEMBLY__ */ -/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ -#define CHIPID_CIDR_VERSION (0x1f << 0) /**< \brief (CHIPID_CIDR) Version of the Device */ -#define CHIPID_CIDR_EPROC (0x7 << 5) /**< \brief (CHIPID_CIDR) Embedded Processor */ -#define CHIPID_CIDR_NVPSIZ (0xf << 8) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ -#define CHIPID_CIDR_NVPSIZ2 (0xf << 12) /**< \brief (CHIPID_CIDR) */ -#define CHIPID_CIDR_SRAMSIZ (0xf << 16) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ -#define CHIPID_CIDR_ARCH (0xff << 20) /**< \brief (CHIPID_CIDR) Architecture Identifier */ -#define CHIPID_CIDR_NVPTYP (0x7 << 28) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ -#define CHIPID_CIDR_EXT (0x1 << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ -/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ -#define CHIPID_EXID_EXID (0xffffffff << 0) /**< \brief (CHIPID_EXID) Chip ID Extension */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_CRCCU Cyclic Redundancy Check Calculation Unit */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Crccu hardware registers */ -typedef struct { - RwReg CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */ - RwReg Reserved1[1]; - WoReg CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */ - WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */ - RoReg CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */ - WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */ - WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */ - RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */ - RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */ - RwReg Reserved2[4]; - WoReg CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */ - RwReg CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */ - RoReg CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */ - WoReg CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */ - WoReg CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */ - RoReg CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */ - RoReg CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */ -} Crccu; -#endif /* __ASSEMBLY__ */ -/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */ -#define CRCCU_DSCR_DSCR (0x7fffff << 9) /**< \brief (CRCCU_DSCR) Descriptor Base Address */ -/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */ -#define CRCCU_DMA_EN_DMAEN (0x1 << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */ -/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */ -#define CRCCU_DMA_DIS_DMADIS (0x1 << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */ -/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */ -#define CRCCU_DMA_SR_DMASR (0x1 << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */ -/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */ -#define CRCCU_DMA_IER_DMAIER (0x1 << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */ -/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */ -#define CRCCU_DMA_IDR_DMAIDR (0x1 << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */ -/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */ -#define CRCCU_DMA_IMR_DMAIMR (0x1 << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */ -/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */ -#define CRCCU_DMA_ISR_DMAISR (0x1 << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */ -/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */ -#define CRCCU_CR_RESET (0x1 << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */ -/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */ -#define CRCCU_MR_ENABLE (0x1 << 0) /**< \brief (CRCCU_MR) CRC Enable */ -#define CRCCU_MR_COMPARE (0x1 << 1) /**< \brief (CRCCU_MR) CRC Compare */ -#define CRCCU_MR_PTYPE (0x3 << 2) /**< \brief (CRCCU_MR) Primitive Polynomial */ -#define CRCCU_MR_PTYPE_CCIT8023 (0x0 << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */ -#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1 << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */ -#define CRCCU_MR_PTYPE_CCIT16 (0x2 << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */ -#define CRCCU_MR_DIVIDER (0xf << 4) /**< \brief (CRCCU_MR) Request Divider */ -/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */ -#define CRCCU_SR_CRC (0xffffffff << 0) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */ -/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */ -#define CRCCU_IER_ERRIER (0x1 << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */ -/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */ -#define CRCCU_IDR_ERRIDR (0x1 << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */ -/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */ -#define CRCCU_IMR_ERRIMR (0x1 << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */ -/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */ -#define CRCCU_ISR_ERRISR (0x1 << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_DACC Digital-to-Analog Converter Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Dacc hardware registers */ -typedef struct { - WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ - RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ - RwReg Reserved1[2]; - WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ - WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ - RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ - RwReg Reserved2[1]; - WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */ - WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ - WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ - RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ - RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved3[24]; - RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ - RwReg Reserved4[19]; - RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */ - RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */ - RwReg Reserved5[5]; - RwReg DACC_RPR; /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */ - RwReg DACC_RCR; /**< \brief (Dacc Offset: 0x104) Receive Counter Register */ - RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */ - RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */ - RwReg DACC_RNPR; /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */ - RwReg DACC_RNCR; /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */ - RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */ - RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */ - WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */ - RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */ -} Dacc; -#endif /* __ASSEMBLY__ */ -/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ -#define DACC_CR_SWRST (0x1 << 0) /**< \brief (DACC_CR) Software Reset */ -/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ -#define DACC_MR_TRGEN (0x1 << 0) /**< \brief (DACC_MR) Trigger Enable */ -#define DACC_MR_TRGEN_DIS (0x0 << 0) // (DACC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. -#define DACC_MR_TRGEN_EN (0x1 << 0) // (DACC_MR) Hardware trigger selected by TRGSEL field is enabled. - -#define DACC_MR_TRGSEL (0x7 << 1) /**< \brief (DACC_MR) Trigger Selection */ -#define DACC_MR_TRGSEL_EXT_TRIG (0x0 << 1) // (DACC_MR) External trigger -#define DACC_MR_TRGSEL_TIOA_0 (0x1 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 0 -#define DACC_MR_TRGSEL_TIOA_1 (0x2 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 1 -#define DACC_MR_TRGSEL_TIOA_2 (0x3 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 2 -#define DACC_MR_TRGSEL_PWM_0 (0x4 << 1) // (DACC_MR) PWM Event Line 0 -#define DACC_MR_TRGSEL_PWM_1 (0x5 << 1) // (DACC_MR) PWM Event Line 1 -#define DACC_MR_WORD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ -#define DACC_MR_WORD_HALF (0x0 << 4) /**< \brief (DACC_MR) Half-Word Transfer */ -#define DACC_MR_WORD_WORLD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ -#define DACC_MR_SLEEP (0x1 << 5) /**< \brief (DACC_MR) Sleep Mode */ -#define DACC_MR_SLEEP_NORMAL (0x0 << 5) // (DACC_MR) Normal Mode -#define DACC_MR_SLEEP_SLEEP (0x1 << 5) // (DACC_MR) Sleep Modes -#define DACC_MR_FASTWKUP (0x1 << 6) /**< \brief (DACC_MR) Fast Wake up Mode */ -#define DACC_MR_REFRESH (0xff << 8) /**< \brief (DACC_MR) Refresh Period */ -#define DACC_MR_USER_SEL (0x3 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_USER_SEL_0 (0x0 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_USER_SEL_1 (0x1 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_TAG (0x1 << 20) /**< \brief (DACC_MR) Tag Selection Mode */ -#define DACC_MR_MAXS (0x1 << 21) /**< \brief (DACC_MR) Max Speed Mode */ -#define DACC_MR_STARTUP (0x3f << 24) /**< \brief (DACC_MR) Startup Time Selection */ -/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ -#define DACC_CHER_CH0 (0x1 << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ -#define DACC_CHER_CH1 (0x1 << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ -#define DACC_CHER_CH2 (0x1 << 2) /**< \brief (DACC_CHER) Channel 2 Enable */ -/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ -#define DACC_CHDR_CH0 (0x1 << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ -#define DACC_CHDR_CH1 (0x1 << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ -#define DACC_CHDR_CH2 (0x1 << 2) /**< \brief (DACC_CHDR) Channel 2 Disable */ -/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ -#define DACC_CHSR_CH0 (0x1 << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ -#define DACC_CHSR_CH1 (0x1 << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ -#define DACC_CHSR_CH2 (0x1 << 2) /**< \brief (DACC_CHSR) Channel 2 Status */ -/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */ -#define DACC_CDR_DATA (0xffffffff << 0) /**< \brief (DACC_CDR) Data to Convert */ -/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ -#define DACC_IER_TXRDY (0x1 << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */ -#define DACC_IER_EOC (0x1 << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */ -#define DACC_IER_ENDTX (0x1 << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */ -#define DACC_IER_TXBUFE (0x1 << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ -#define DACC_IDR_TXRDY (0x1 << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */ -#define DACC_IDR_EOC (0x1 << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */ -#define DACC_IDR_ENDTX (0x1 << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */ -#define DACC_IDR_TXBUFE (0x1 << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ -#define DACC_IMR_TXRDY (0x1 << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */ -#define DACC_IMR_EOC (0x1 << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */ -#define DACC_IMR_ENDTX (0x1 << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */ -#define DACC_IMR_TXBUFE (0x1 << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ -#define DACC_ISR_TXRDY (0x1 << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */ -#define DACC_ISR_EOC (0x1 << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */ -#define DACC_ISR_ENDTX (0x1 << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */ -#define DACC_ISR_TXBUFE (0x1 << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */ -/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ -#define DACC_ACR_IBCTLCH0 (0x3 << 0) /**< \brief (DACC_ACR) Analog Output Current Control */ -#define DACC_ACR_IBCTLCH1 (0x3 << 2) /**< \brief (DACC_ACR) Analog Output Current Control */ -#define DACC_ACR_IBCTLDACCORE (0x3 << 8) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */ -/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */ -#define DACC_WPMR_WPEN (0x1 << 0) /**< \brief (DACC_WPMR) Write Protect Enable */ -#define DACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (DACC_WPMR) Write Protect KEY */ -/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */ -#define DACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (DACC_WPSR) Write protection error */ -#define DACC_WPSR_WPROTADDR (0xff << 8) /**< \brief (DACC_WPSR) Write protection error address */ -/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */ -#define DACC_RPR_RXPTR (0xffffffff << 0) /**< \brief (DACC_RPR) Receive Pointer Register */ -/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */ -#define DACC_RCR_RXCTR (0xffff << 0) /**< \brief (DACC_RCR) Receive Counter Register */ -/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */ -#define DACC_TPR_TXPTR (0xffffffff << 0) /**< \brief (DACC_TPR) Transmit Counter Register */ -/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */ -#define DACC_TCR_TXCTR (0xffff << 0) /**< \brief (DACC_TCR) Transmit Counter Register */ -/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */ -#define DACC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (DACC_RNPR) Receive Next Pointer */ -/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */ -#define DACC_RNCR_RXNCTR (0xffff << 0) /**< \brief (DACC_RNCR) Receive Next Counter */ -/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define DACC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (DACC_TNPR) Transmit Next Pointer */ -/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define DACC_TNCR_TXNCTR (0xffff << 0) /**< \brief (DACC_TNCR) Transmit Counter Next */ -/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */ -#define DACC_PTCR_RXTEN (0x1 << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */ -#define DACC_PTCR_RXTDIS (0x1 << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */ -#define DACC_PTCR_TXTEN (0x1 << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */ -#define DACC_PTCR_TXTDIS (0x1 << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */ -/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */ -#define DACC_PTSR_RXTEN (0x1 << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */ -#define DACC_PTSR_TXTEN (0x1 << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_EFC Embedded Flash Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Efc hardware registers */ -typedef struct { - RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ - WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ - RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ - RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ -} Efc; -#endif /* __ASSEMBLY__ */ -/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ -#define EEFC_FMR_FRDY (0x1 << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ -#define EEFC_FMR_FWS (0xf << 8) /**< \brief (EEFC_FMR) Flash Wait State */ -#define EEFC_FMR_FAM (0x1 << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ -/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ -#define EEFC_FCR_FCMD (0xff << 0) /**< \brief (EEFC_FCR) Flash Command */ -#define EEFC_FCR_FARG (0xffff << 8) /**< \brief (EEFC_FCR) Flash Command Argument */ -#define EEFC_FCR_FKEY (0xff << 24) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ -/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ -#define EEFC_FSR_FRDY (0x1 << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ -#define EEFC_FSR_FCMDE (0x1 << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ -#define EEFC_FSR_FLOCKE (0x1 << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ -/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ -#define EEFC_FRR_FVALUE (0xffffffff << 0) /**< \brief (EEFC_FRR) Flash Result Value */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_GPBR General Purpose Backup Register */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Gpbr hardware registers */ -typedef struct { - RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */ - RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */ - RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */ - RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */ -} Gpbr; -#endif /* __ASSEMBLY__ */ -/* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */ -#define SYS_GPBR0_GPBR_VALUE0 (0xffffffff << 0) /**< \brief (SYS_GPBR0) Value of GPBR x */ -/* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */ -#define SYS_GPBR1_GPBR_VALUE1 (0xffffffff << 0) /**< \brief (SYS_GPBR1) Value of GPBR x */ -/* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */ -#define SYS_GPBR2_GPBR_VALUE2 (0xffffffff << 0) /**< \brief (SYS_GPBR2) Value of GPBR x */ -/* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */ -#define SYS_GPBR3_GPBR_VALUE3 (0xffffffff << 0) /**< \brief (SYS_GPBR3) Value of GPBR x */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_HSMCI High Speed MultiMedia Card Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Hsmci hardware registers */ -typedef struct { - WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ - RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ - RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ - RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ - RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ - WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ - RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ - RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ - RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ - RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ - WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ - RwReg Reserved1[2]; - RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ - WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ - WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ - RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ - RwReg Reserved2[1]; - RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ - RwReg Reserved3[35]; - RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ - RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ - RwReg Reserved4[5]; - RwReg HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */ - RwReg HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */ - RwReg HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */ - RwReg HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */ - RwReg HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */ - RwReg HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */ - RwReg HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */ - RwReg HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */ - WoReg HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */ - RoReg HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */ -} Hsmci; -#endif /* __ASSEMBLY__ */ -/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ -#define HSMCI_CR_MCIEN (0x1 << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ -#define HSMCI_CR_MCIDIS (0x1 << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ -#define HSMCI_CR_PWSEN (0x1 << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ -#define HSMCI_CR_PWSDIS (0x1 << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ -#define HSMCI_CR_SWRST (0x1 << 7) /**< \brief (HSMCI_CR) Software Reset */ -/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ -#define HSMCI_MR_CLKDIV (0xff << 0) /**< \brief (HSMCI_MR) Clock Divider */ -#define HSMCI_MR_PWSDIV (0x7 << 8) /**< \brief (HSMCI_MR) Power Saving Divider */ -#define HSMCI_MR_RDPROOF (0x1 << 11) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_WRPROOF (0x1 << 12) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_FBYTE (0x1 << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ -#define HSMCI_MR_PADV (0x1 << 14) /**< \brief (HSMCI_MR) Padding Value */ -#define HSMCI_MR_PDCMODE (0x1 << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */ -#define HSMCI_MR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_MR) Data Block Length */ -/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ -#define HSMCI_DTOR_DTOCYC (0xf << 0) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ -#define HSMCI_DTOR_DTOMUL (0x7 << 4) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ -/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ -#define HSMCI_SDCR_SDCSEL (0x3 << 0) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ -#define HSMCI_SDCR_SDCBUS (0x3 << 6) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ -/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ -#define HSMCI_ARGR_ARG (0xffffffff << 0) /**< \brief (HSMCI_ARGR) Command Argument */ -/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ -#define HSMCI_CMDR_CMDNB (0x3f << 0) /**< \brief (HSMCI_CMDR) Command Number */ -#define HSMCI_CMDR_RSPTYP (0x3 << 6) /**< \brief (HSMCI_CMDR) Response Type */ -#define HSMCI_CMDR_SPCMD (0x7 << 8) /**< \brief (HSMCI_CMDR) Special Command */ -#define HSMCI_CMDR_OPDCMD (0x1 << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ -#define HSMCI_CMDR_MAXLAT (0x1 << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ -#define HSMCI_CMDR_TRCMD (0x3 << 16) /**< \brief (HSMCI_CMDR) Transfer Command */ -#define HSMCI_CMDR_TRDIR (0x1 << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ -#define HSMCI_CMDR_TRTYP (0x7 << 19) /**< \brief (HSMCI_CMDR) Transfer Type */ -#define HSMCI_CMDR_IOSPCMD (0x3 << 24) /**< \brief (HSMCI_CMDR) SDIO Special Command */ -#define HSMCI_CMDR_ATACS (0x1 << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ -#define HSMCI_CMDR_BOOT_ACK (0x1 << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ -/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ -#define HSMCI_BLKR_BCNT (0xffff << 0) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ -#define HSMCI_BLKR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_BLKR) Data Block Length */ -/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ -#define HSMCI_CSTOR_CSTOCYC (0xf << 0) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ -#define HSMCI_CSTOR_CSTOMUL (0x7 << 4) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ -/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ -#define HSMCI_RSPR_RSP (0xffffffff << 0) /**< \brief (HSMCI_RSPR[4]) Response */ -/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ -#define HSMCI_RDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_RDR) Data to Read */ -/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ -#define HSMCI_TDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_TDR) Data to Write */ -/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ -#define HSMCI_SR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_SR) Command Ready */ -#define HSMCI_SR_RXRDY (0x1 << 1) /**< \brief (HSMCI_SR) Receiver Ready */ -#define HSMCI_SR_TXRDY (0x1 << 2) /**< \brief (HSMCI_SR) Transmit Ready */ -#define HSMCI_SR_BLKE (0x1 << 3) /**< \brief (HSMCI_SR) Data Block Ended */ -#define HSMCI_SR_DTIP (0x1 << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ -#define HSMCI_SR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ -#define HSMCI_SR_ENDRX (0x1 << 6) /**< \brief (HSMCI_SR) End of RX Buffer */ -#define HSMCI_SR_ENDTX (0x1 << 7) /**< \brief (HSMCI_SR) End of TX Buffer */ -#define HSMCI_SR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */ -#define HSMCI_SR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ -#define HSMCI_SR_CSRCV (0x1 << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ -#define HSMCI_SR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_SR) RX Buffer Full */ -#define HSMCI_SR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */ -#define HSMCI_SR_RINDE (0x1 << 16) /**< \brief (HSMCI_SR) Response Index Error */ -#define HSMCI_SR_RDIRE (0x1 << 17) /**< \brief (HSMCI_SR) Response Direction Error */ -#define HSMCI_SR_RCRCE (0x1 << 18) /**< \brief (HSMCI_SR) Response CRC Error */ -#define HSMCI_SR_RENDE (0x1 << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ -#define HSMCI_SR_RTOE (0x1 << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ -#define HSMCI_SR_DCRCE (0x1 << 21) /**< \brief (HSMCI_SR) Data CRC Error */ -#define HSMCI_SR_DTOE (0x1 << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ -#define HSMCI_SR_CSTOE (0x1 << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ -#define HSMCI_SR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ -#define HSMCI_SR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ -#define HSMCI_SR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ -#define HSMCI_SR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ -#define HSMCI_SR_OVRE (0x1 << 30) /**< \brief (HSMCI_SR) Overrun */ -#define HSMCI_SR_UNRE (0x1 << 31) /**< \brief (HSMCI_SR) Underrun */ -/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ -#define HSMCI_IER_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ -#define HSMCI_IER_RXRDY (0x1 << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ -#define HSMCI_IER_TXRDY (0x1 << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ -#define HSMCI_IER_BLKE (0x1 << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ -#define HSMCI_IER_DTIP (0x1 << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ -#define HSMCI_IER_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ -#define HSMCI_IER_ENDRX (0x1 << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */ -#define HSMCI_IER_ENDTX (0x1 << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */ -#define HSMCI_IER_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ -#define HSMCI_IER_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ -#define HSMCI_IER_CSRCV (0x1 << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ -#define HSMCI_IER_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */ -#define HSMCI_IER_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */ -#define HSMCI_IER_RINDE (0x1 << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ -#define HSMCI_IER_RDIRE (0x1 << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ -#define HSMCI_IER_RCRCE (0x1 << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ -#define HSMCI_IER_RENDE (0x1 << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ -#define HSMCI_IER_RTOE (0x1 << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ -#define HSMCI_IER_DCRCE (0x1 << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ -#define HSMCI_IER_DTOE (0x1 << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ -#define HSMCI_IER_CSTOE (0x1 << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ -#define HSMCI_IER_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ -#define HSMCI_IER_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ -#define HSMCI_IER_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ -#define HSMCI_IER_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ -#define HSMCI_IER_OVRE (0x1 << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ -#define HSMCI_IER_UNRE (0x1 << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ -/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ -#define HSMCI_IDR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ -#define HSMCI_IDR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ -#define HSMCI_IDR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ -#define HSMCI_IDR_BLKE (0x1 << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ -#define HSMCI_IDR_DTIP (0x1 << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ -#define HSMCI_IDR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ -#define HSMCI_IDR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */ -#define HSMCI_IDR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */ -#define HSMCI_IDR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ -#define HSMCI_IDR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ -#define HSMCI_IDR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ -#define HSMCI_IDR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */ -#define HSMCI_IDR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define HSMCI_IDR_RINDE (0x1 << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ -#define HSMCI_IDR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ -#define HSMCI_IDR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ -#define HSMCI_IDR_RENDE (0x1 << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ -#define HSMCI_IDR_RTOE (0x1 << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ -#define HSMCI_IDR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ -#define HSMCI_IDR_DTOE (0x1 << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ -#define HSMCI_IDR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ -#define HSMCI_IDR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ -#define HSMCI_IDR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ -#define HSMCI_IDR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ -#define HSMCI_IDR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ -#define HSMCI_IDR_OVRE (0x1 << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ -#define HSMCI_IDR_UNRE (0x1 << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ -/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ -#define HSMCI_IMR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ -#define HSMCI_IMR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ -#define HSMCI_IMR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ -#define HSMCI_IMR_BLKE (0x1 << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ -#define HSMCI_IMR_DTIP (0x1 << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ -#define HSMCI_IMR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ -#define HSMCI_IMR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */ -#define HSMCI_IMR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */ -#define HSMCI_IMR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ -#define HSMCI_IMR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ -#define HSMCI_IMR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ -#define HSMCI_IMR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */ -#define HSMCI_IMR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define HSMCI_IMR_RINDE (0x1 << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ -#define HSMCI_IMR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ -#define HSMCI_IMR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ -#define HSMCI_IMR_RENDE (0x1 << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ -#define HSMCI_IMR_RTOE (0x1 << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ -#define HSMCI_IMR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ -#define HSMCI_IMR_DTOE (0x1 << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ -#define HSMCI_IMR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ -#define HSMCI_IMR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ -#define HSMCI_IMR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ -#define HSMCI_IMR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ -#define HSMCI_IMR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ -#define HSMCI_IMR_OVRE (0x1 << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ -#define HSMCI_IMR_UNRE (0x1 << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ -/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ -#define HSMCI_CFG_FIFOMODE (0x1 << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ -#define HSMCI_CFG_FERRCTRL (0x1 << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ -#define HSMCI_CFG_HSMODE (0x1 << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ -#define HSMCI_CFG_LSYNC (0x1 << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ -/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ -#define HSMCI_WPMR_WP_EN (0x1 << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ -#define HSMCI_WPMR_WP_KEY (0xffffff << 8) /**< \brief (HSMCI_WPMR) Write Protection Key password */ -/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ -#define HSMCI_WPSR_WP_VS (0xf << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ -#define HSMCI_WPSR_WP_VSRC (0xffff << 8) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */ -/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */ -#define HSMCI_RPR_RXPTR (0xffffffff << 0) /**< \brief (HSMCI_RPR) Receive Pointer Register */ -/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */ -#define HSMCI_RCR_RXCTR (0xffff << 0) /**< \brief (HSMCI_RCR) Receive Counter Register */ -/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */ -#define HSMCI_TPR_TXPTR (0xffffffff << 0) /**< \brief (HSMCI_TPR) Transmit Counter Register */ -/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */ -#define HSMCI_TCR_TXCTR (0xffff << 0) /**< \brief (HSMCI_TCR) Transmit Counter Register */ -/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */ -#define HSMCI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (HSMCI_RNPR) Receive Next Pointer */ -/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */ -#define HSMCI_RNCR_RXNCTR (0xffff << 0) /**< \brief (HSMCI_RNCR) Receive Next Counter */ -/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define HSMCI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */ -/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define HSMCI_TNCR_TXNCTR (0xffff << 0) /**< \brief (HSMCI_TNCR) Transmit Counter Next */ -/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */ -#define HSMCI_PTCR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */ -#define HSMCI_PTCR_RXTDIS (0x1 << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */ -#define HSMCI_PTCR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */ -#define HSMCI_PTCR_TXTDIS (0x1 << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */ -/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */ -#define HSMCI_PTSR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */ -#define HSMCI_PTSR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_MATRIX AHB Bus Matrix */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Matrix hardware registers */ -typedef struct { - RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ - RwReg Reserved1[12]; - RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ - RwReg Reserved2[11]; - RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ - RwReg Reserved3[1]; - RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ - RwReg Reserved4[1]; - RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ - RwReg Reserved5[1]; - RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ - RwReg Reserved6[1]; - RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ - RwReg Reserved7[28]; - RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System IO Configuration register */ - RwReg Reserved8[1]; - RwReg CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */ - RwReg Reserved9[49]; - RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */ - RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */ -} Matrix; -#endif /* __ASSEMBLY__ */ -/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ -#define MATRIX_MCFG_ULBT (0x7 << 0) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */ -/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ -#define MATRIX_SCFG_SLOT_CYCLE (0xff << 0) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */ -#define MATRIX_SCFG_DEFMSTR_TYPE (0x3 << 16) /**< \brief (MATRIX_SCFG[5]) Default Master Type */ -#define MATRIX_SCFG_FIXED_DEFMSTR (0x7 << 18) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */ -#define MATRIX_SCFG_ARBT (0x3 << 24) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */ -/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ -#define MATRIX_PRAS0_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ -#define MATRIX_PRAS0_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ -#define MATRIX_PRAS0_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ -#define MATRIX_PRAS0_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ -#define MATRIX_PRAS0_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ -/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ -#define MATRIX_PRAS1_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ -#define MATRIX_PRAS1_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ -#define MATRIX_PRAS1_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ -#define MATRIX_PRAS1_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ -#define MATRIX_PRAS1_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ -/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ -#define MATRIX_PRAS2_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ -#define MATRIX_PRAS2_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ -#define MATRIX_PRAS2_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ -#define MATRIX_PRAS2_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ -#define MATRIX_PRAS2_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ -/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ -#define MATRIX_PRAS3_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ -#define MATRIX_PRAS3_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ -#define MATRIX_PRAS3_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ -#define MATRIX_PRAS3_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ -#define MATRIX_PRAS3_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ -/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ -#define MATRIX_PRAS4_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ -#define MATRIX_PRAS4_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ -#define MATRIX_PRAS4_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ -#define MATRIX_PRAS4_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ -#define MATRIX_PRAS4_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ -/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System IO Configuration register -------- */ -#define CCFG_SYSIO_SYSIO4 (0x1 << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ -#define CCFG_SYSIO_SYSIO5 (0x1 << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ -#define CCFG_SYSIO_SYSIO6 (0x1 << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ -#define CCFG_SYSIO_SYSIO7 (0x1 << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ -#define CCFG_SYSIO_SYSIO10 (0x1 << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */ -#define CCFG_SYSIO_SYSIO11 (0x1 << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */ -#define CCFG_SYSIO_SYSIO12 (0x1 << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ -/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */ -#define CCFG_SMCNFCS_SMC_NFCS0 (0x1 << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS1 (0x1 << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS2 (0x1 << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS3 (0x1 << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ -/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */ -#define MATRIX_WPMR_WPEN (0x1 << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */ -#define MATRIX_WPMR_WPKEY (0xffffff << 8) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */ -/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */ -#define MATRIX_WPSR_WPVS (0x1 << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */ -#define MATRIX_WPSR_WPVSRC (0xffff << 8) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PDC Peripheral DMA Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pdc hardware registers */ -typedef struct { - RwReg Reserved1[64]; - RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x100) Receive Pointer Register */ - RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x104) Receive Counter Register */ - RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x108) Transmit Pointer Register */ - RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x10C) Transmit Counter Register */ - RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x110) Receive Next Pointer Register */ - RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x114) Receive Next Counter Register */ - RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x118) Transmit Next Pointer Register */ - RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x11C) Transmit Next Counter Register */ - WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x120) Transfer Control Register */ - RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x124) Transfer Status Register */ -} Pdc; -#endif /* __ASSEMBLY__ */ -/* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */ -#define PERIPH_RPR_RXPTR (0xffffffff << 0) /**< \brief (PERIPH_RPR) Receive Pointer Register */ -/* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */ -#define PERIPH_RCR_RXCTR (0xffff << 0) /**< \brief (PERIPH_RCR) Receive Counter Register */ -/* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */ -#define PERIPH_TPR_TXPTR (0xffffffff << 0) /**< \brief (PERIPH_TPR) Transmit Counter Register */ -/* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */ -#define PERIPH_TCR_TXCTR (0xffff << 0) /**< \brief (PERIPH_TCR) Transmit Counter Register */ -/* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */ -#define PERIPH_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ -/* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */ -#define PERIPH_RNCR_RXNCTR (0xffff << 0) /**< \brief (PERIPH_RNCR) Receive Next Counter */ -/* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PERIPH_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ -/* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PERIPH_TNCR_TXNCTR (0xffff << 0) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ -/* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */ -#define PERIPH_PTCR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ -#define PERIPH_PTCR_RXTDIS (0x1 << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ -#define PERIPH_PTCR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ -#define PERIPH_PTCR_TXTDIS (0x1 << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ -/* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */ -#define PERIPH_PTSR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ -#define PERIPH_PTSR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Parallel Input/Output */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PIO Parallel Input/Output */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pio hardware registers */ -typedef struct { - WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ - WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ - RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ - RwReg Reserved1[1]; - WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ - WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ - RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ - RwReg Reserved2[1]; - WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ - WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ - RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ - RwReg Reserved3[1]; - WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ - WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ - RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ - RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ - WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ - WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ - RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ - RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ - WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ - WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ - RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ - RwReg Reserved4[1]; - WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ - WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ - RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ - RwReg Reserved5[1]; - RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ - RwReg Reserved6[2]; - WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */ - WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */ - RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */ - RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ - WoReg PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ - WoReg PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ - RoReg PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ - RwReg Reserved7[1]; - WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ - WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ - RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ - RwReg Reserved8[1]; - WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ - WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ - RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ - RwReg Reserved9[1]; - WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ - WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ - RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ - RwReg Reserved10[1]; - WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ - WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ - RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ - RwReg Reserved11[1]; - RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ - RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ - RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ - RwReg Reserved12[5]; - RwReg PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ - RwReg Reserved13[19]; - RwReg PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */ - WoReg PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */ - WoReg PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */ - RoReg PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */ - RoReg PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */ - RoReg PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */ -} Pio; -#endif /* __ASSEMBLY__ */ -/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ -#define PIO_PER_P0 (0x1 << 0) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P1 (0x1 << 1) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P2 (0x1 << 2) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P3 (0x1 << 3) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P4 (0x1 << 4) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P5 (0x1 << 5) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P6 (0x1 << 6) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P7 (0x1 << 7) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P8 (0x1 << 8) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P9 (0x1 << 9) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P10 (0x1 << 10) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P11 (0x1 << 11) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P12 (0x1 << 12) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P13 (0x1 << 13) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P14 (0x1 << 14) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P15 (0x1 << 15) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P16 (0x1 << 16) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P17 (0x1 << 17) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P18 (0x1 << 18) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P19 (0x1 << 19) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P20 (0x1 << 20) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P21 (0x1 << 21) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P22 (0x1 << 22) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P23 (0x1 << 23) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P24 (0x1 << 24) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P25 (0x1 << 25) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P26 (0x1 << 26) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P27 (0x1 << 27) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P28 (0x1 << 28) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P29 (0x1 << 29) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P30 (0x1 << 30) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P31 (0x1 << 31) /**< \brief (PIO_PER) PIO Enable */ -/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ -#define PIO_PDR_P0 (0x1 << 0) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P1 (0x1 << 1) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P2 (0x1 << 2) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P3 (0x1 << 3) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P4 (0x1 << 4) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P5 (0x1 << 5) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P6 (0x1 << 6) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P7 (0x1 << 7) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P8 (0x1 << 8) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P9 (0x1 << 9) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P10 (0x1 << 10) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P11 (0x1 << 11) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P12 (0x1 << 12) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P13 (0x1 << 13) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P14 (0x1 << 14) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P15 (0x1 << 15) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P16 (0x1 << 16) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P17 (0x1 << 17) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P18 (0x1 << 18) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P19 (0x1 << 19) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P20 (0x1 << 20) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P21 (0x1 << 21) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P22 (0x1 << 22) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P23 (0x1 << 23) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P24 (0x1 << 24) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P25 (0x1 << 25) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P26 (0x1 << 26) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P27 (0x1 << 27) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P28 (0x1 << 28) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P29 (0x1 << 29) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P30 (0x1 << 30) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P31 (0x1 << 31) /**< \brief (PIO_PDR) PIO Disable */ -/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ -#define PIO_PSR_P0 (0x1 << 0) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P1 (0x1 << 1) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P2 (0x1 << 2) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P3 (0x1 << 3) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P4 (0x1 << 4) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P5 (0x1 << 5) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P6 (0x1 << 6) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P7 (0x1 << 7) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P8 (0x1 << 8) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P9 (0x1 << 9) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P10 (0x1 << 10) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P11 (0x1 << 11) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P12 (0x1 << 12) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P13 (0x1 << 13) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P14 (0x1 << 14) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P15 (0x1 << 15) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P16 (0x1 << 16) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P17 (0x1 << 17) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P18 (0x1 << 18) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P19 (0x1 << 19) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P20 (0x1 << 20) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P21 (0x1 << 21) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P22 (0x1 << 22) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P23 (0x1 << 23) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P24 (0x1 << 24) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P25 (0x1 << 25) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P26 (0x1 << 26) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P27 (0x1 << 27) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P28 (0x1 << 28) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P29 (0x1 << 29) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P30 (0x1 << 30) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P31 (0x1 << 31) /**< \brief (PIO_PSR) PIO Status */ -/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ -#define PIO_OER_P0 (0x1 << 0) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P1 (0x1 << 1) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P2 (0x1 << 2) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P3 (0x1 << 3) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P4 (0x1 << 4) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P5 (0x1 << 5) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P6 (0x1 << 6) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P7 (0x1 << 7) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P8 (0x1 << 8) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P9 (0x1 << 9) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P10 (0x1 << 10) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P11 (0x1 << 11) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P12 (0x1 << 12) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P13 (0x1 << 13) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P14 (0x1 << 14) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P15 (0x1 << 15) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P16 (0x1 << 16) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P17 (0x1 << 17) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P18 (0x1 << 18) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P19 (0x1 << 19) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P20 (0x1 << 20) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P21 (0x1 << 21) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P22 (0x1 << 22) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P23 (0x1 << 23) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P24 (0x1 << 24) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P25 (0x1 << 25) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P26 (0x1 << 26) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P27 (0x1 << 27) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P28 (0x1 << 28) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P29 (0x1 << 29) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P30 (0x1 << 30) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P31 (0x1 << 31) /**< \brief (PIO_OER) Output Enable */ -/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ -#define PIO_ODR_P0 (0x1 << 0) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P1 (0x1 << 1) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P2 (0x1 << 2) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P3 (0x1 << 3) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P4 (0x1 << 4) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P5 (0x1 << 5) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P6 (0x1 << 6) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P7 (0x1 << 7) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P8 (0x1 << 8) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P9 (0x1 << 9) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P10 (0x1 << 10) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P11 (0x1 << 11) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P12 (0x1 << 12) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P13 (0x1 << 13) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P14 (0x1 << 14) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P15 (0x1 << 15) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P16 (0x1 << 16) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P17 (0x1 << 17) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P18 (0x1 << 18) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P19 (0x1 << 19) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P20 (0x1 << 20) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P21 (0x1 << 21) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P22 (0x1 << 22) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P23 (0x1 << 23) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P24 (0x1 << 24) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P25 (0x1 << 25) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P26 (0x1 << 26) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P27 (0x1 << 27) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P28 (0x1 << 28) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P29 (0x1 << 29) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P30 (0x1 << 30) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P31 (0x1 << 31) /**< \brief (PIO_ODR) Output Disable */ -/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ -#define PIO_OSR_P0 (0x1 << 0) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P1 (0x1 << 1) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P2 (0x1 << 2) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P3 (0x1 << 3) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P4 (0x1 << 4) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P5 (0x1 << 5) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P6 (0x1 << 6) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P7 (0x1 << 7) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P8 (0x1 << 8) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P9 (0x1 << 9) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P10 (0x1 << 10) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P11 (0x1 << 11) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P12 (0x1 << 12) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P13 (0x1 << 13) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P14 (0x1 << 14) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P15 (0x1 << 15) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P16 (0x1 << 16) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P17 (0x1 << 17) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P18 (0x1 << 18) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P19 (0x1 << 19) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P20 (0x1 << 20) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P21 (0x1 << 21) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P22 (0x1 << 22) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P23 (0x1 << 23) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P24 (0x1 << 24) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P25 (0x1 << 25) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P26 (0x1 << 26) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P27 (0x1 << 27) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P28 (0x1 << 28) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P29 (0x1 << 29) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P30 (0x1 << 30) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P31 (0x1 << 31) /**< \brief (PIO_OSR) Output Status */ -/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ -#define PIO_IFER_P0 (0x1 << 0) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P1 (0x1 << 1) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P2 (0x1 << 2) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P3 (0x1 << 3) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P4 (0x1 << 4) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P5 (0x1 << 5) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P6 (0x1 << 6) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P7 (0x1 << 7) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P8 (0x1 << 8) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P9 (0x1 << 9) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P10 (0x1 << 10) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P11 (0x1 << 11) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P12 (0x1 << 12) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P13 (0x1 << 13) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P14 (0x1 << 14) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P15 (0x1 << 15) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P16 (0x1 << 16) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P17 (0x1 << 17) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P18 (0x1 << 18) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P19 (0x1 << 19) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P20 (0x1 << 20) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P21 (0x1 << 21) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P22 (0x1 << 22) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P23 (0x1 << 23) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P24 (0x1 << 24) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P25 (0x1 << 25) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P26 (0x1 << 26) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P27 (0x1 << 27) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P28 (0x1 << 28) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P29 (0x1 << 29) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P30 (0x1 << 30) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P31 (0x1 << 31) /**< \brief (PIO_IFER) Input Filter Enable */ -/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ -#define PIO_IFDR_P0 (0x1 << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P1 (0x1 << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P2 (0x1 << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P3 (0x1 << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P4 (0x1 << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P5 (0x1 << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P6 (0x1 << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P7 (0x1 << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P8 (0x1 << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P9 (0x1 << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P10 (0x1 << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P11 (0x1 << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P12 (0x1 << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P13 (0x1 << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P14 (0x1 << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P15 (0x1 << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P16 (0x1 << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P17 (0x1 << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P18 (0x1 << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P19 (0x1 << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P20 (0x1 << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P21 (0x1 << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P22 (0x1 << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P23 (0x1 << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P24 (0x1 << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P25 (0x1 << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P26 (0x1 << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P27 (0x1 << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P28 (0x1 << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P29 (0x1 << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P30 (0x1 << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P31 (0x1 << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ -/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ -#define PIO_IFSR_P0 (0x1 << 0) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P1 (0x1 << 1) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P2 (0x1 << 2) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P3 (0x1 << 3) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P4 (0x1 << 4) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P5 (0x1 << 5) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P6 (0x1 << 6) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P7 (0x1 << 7) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P8 (0x1 << 8) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P9 (0x1 << 9) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P10 (0x1 << 10) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P11 (0x1 << 11) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P12 (0x1 << 12) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P13 (0x1 << 13) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P14 (0x1 << 14) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P15 (0x1 << 15) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P16 (0x1 << 16) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P17 (0x1 << 17) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P18 (0x1 << 18) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P19 (0x1 << 19) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P20 (0x1 << 20) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P21 (0x1 << 21) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P22 (0x1 << 22) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P23 (0x1 << 23) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P24 (0x1 << 24) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P25 (0x1 << 25) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P26 (0x1 << 26) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P27 (0x1 << 27) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P28 (0x1 << 28) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P29 (0x1 << 29) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P30 (0x1 << 30) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P31 (0x1 << 31) /**< \brief (PIO_IFSR) Input Filer Status */ -/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ -#define PIO_SODR_P0 (0x1 << 0) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P1 (0x1 << 1) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P2 (0x1 << 2) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P3 (0x1 << 3) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P4 (0x1 << 4) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P5 (0x1 << 5) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P6 (0x1 << 6) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P7 (0x1 << 7) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P8 (0x1 << 8) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P9 (0x1 << 9) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P10 (0x1 << 10) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P11 (0x1 << 11) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P12 (0x1 << 12) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P13 (0x1 << 13) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P14 (0x1 << 14) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P15 (0x1 << 15) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P16 (0x1 << 16) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P17 (0x1 << 17) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P18 (0x1 << 18) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P19 (0x1 << 19) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P20 (0x1 << 20) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P21 (0x1 << 21) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P22 (0x1 << 22) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P23 (0x1 << 23) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P24 (0x1 << 24) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P25 (0x1 << 25) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P26 (0x1 << 26) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P27 (0x1 << 27) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P28 (0x1 << 28) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P29 (0x1 << 29) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P30 (0x1 << 30) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P31 (0x1 << 31) /**< \brief (PIO_SODR) Set Output Data */ -/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ -#define PIO_CODR_P0 (0x1 << 0) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P1 (0x1 << 1) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P2 (0x1 << 2) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P3 (0x1 << 3) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P4 (0x1 << 4) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P5 (0x1 << 5) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P6 (0x1 << 6) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P7 (0x1 << 7) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P8 (0x1 << 8) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P9 (0x1 << 9) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P10 (0x1 << 10) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P11 (0x1 << 11) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P12 (0x1 << 12) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P13 (0x1 << 13) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P14 (0x1 << 14) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P15 (0x1 << 15) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P16 (0x1 << 16) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P17 (0x1 << 17) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P18 (0x1 << 18) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P19 (0x1 << 19) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P20 (0x1 << 20) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P21 (0x1 << 21) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P22 (0x1 << 22) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P23 (0x1 << 23) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P24 (0x1 << 24) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P25 (0x1 << 25) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P26 (0x1 << 26) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P27 (0x1 << 27) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P28 (0x1 << 28) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P29 (0x1 << 29) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P30 (0x1 << 30) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P31 (0x1 << 31) /**< \brief (PIO_CODR) Clear Output Data */ -/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ -#define PIO_ODSR_P0 (0x1 << 0) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P1 (0x1 << 1) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P2 (0x1 << 2) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P3 (0x1 << 3) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P4 (0x1 << 4) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P5 (0x1 << 5) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P6 (0x1 << 6) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P7 (0x1 << 7) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P8 (0x1 << 8) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P9 (0x1 << 9) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P10 (0x1 << 10) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P11 (0x1 << 11) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P12 (0x1 << 12) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P13 (0x1 << 13) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P14 (0x1 << 14) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P15 (0x1 << 15) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P16 (0x1 << 16) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P17 (0x1 << 17) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P18 (0x1 << 18) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P19 (0x1 << 19) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P20 (0x1 << 20) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P21 (0x1 << 21) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P22 (0x1 << 22) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P23 (0x1 << 23) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P24 (0x1 << 24) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P25 (0x1 << 25) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P26 (0x1 << 26) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P27 (0x1 << 27) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P28 (0x1 << 28) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P29 (0x1 << 29) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P30 (0x1 << 30) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P31 (0x1 << 31) /**< \brief (PIO_ODSR) Output Data Status */ -/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ -#define PIO_PDSR_P0 (0x1 << 0) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P1 (0x1 << 1) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P2 (0x1 << 2) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P3 (0x1 << 3) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P4 (0x1 << 4) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P5 (0x1 << 5) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P6 (0x1 << 6) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P7 (0x1 << 7) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P8 (0x1 << 8) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P9 (0x1 << 9) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P10 (0x1 << 10) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P11 (0x1 << 11) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P12 (0x1 << 12) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P13 (0x1 << 13) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P14 (0x1 << 14) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P15 (0x1 << 15) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P16 (0x1 << 16) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P17 (0x1 << 17) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P18 (0x1 << 18) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P19 (0x1 << 19) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P20 (0x1 << 20) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P21 (0x1 << 21) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P22 (0x1 << 22) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P23 (0x1 << 23) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P24 (0x1 << 24) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P25 (0x1 << 25) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P26 (0x1 << 26) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P27 (0x1 << 27) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P28 (0x1 << 28) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P29 (0x1 << 29) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P30 (0x1 << 30) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P31 (0x1 << 31) /**< \brief (PIO_PDSR) Output Data Status */ -/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ -#define PIO_IER_P0 (0x1 << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P1 (0x1 << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P2 (0x1 << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P3 (0x1 << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P4 (0x1 << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P5 (0x1 << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P6 (0x1 << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P7 (0x1 << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P8 (0x1 << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P9 (0x1 << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P10 (0x1 << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P11 (0x1 << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P12 (0x1 << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P13 (0x1 << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P14 (0x1 << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P15 (0x1 << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P16 (0x1 << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P17 (0x1 << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P18 (0x1 << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P19 (0x1 << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P20 (0x1 << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P21 (0x1 << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P22 (0x1 << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P23 (0x1 << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P24 (0x1 << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P25 (0x1 << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P26 (0x1 << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P27 (0x1 << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P28 (0x1 << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P29 (0x1 << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P30 (0x1 << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P31 (0x1 << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ -#define PIO_IDR_P0 (0x1 << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P1 (0x1 << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P2 (0x1 << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P3 (0x1 << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P4 (0x1 << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P5 (0x1 << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P6 (0x1 << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P7 (0x1 << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P8 (0x1 << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P9 (0x1 << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P10 (0x1 << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P11 (0x1 << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P12 (0x1 << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P13 (0x1 << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P14 (0x1 << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P15 (0x1 << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P16 (0x1 << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P17 (0x1 << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P18 (0x1 << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P19 (0x1 << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P20 (0x1 << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P21 (0x1 << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P22 (0x1 << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P23 (0x1 << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P24 (0x1 << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P25 (0x1 << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P26 (0x1 << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P27 (0x1 << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P28 (0x1 << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P29 (0x1 << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P30 (0x1 << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P31 (0x1 << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ -#define PIO_IMR_P0 (0x1 << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P1 (0x1 << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P2 (0x1 << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P3 (0x1 << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P4 (0x1 << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P5 (0x1 << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P6 (0x1 << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P7 (0x1 << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P8 (0x1 << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P9 (0x1 << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P10 (0x1 << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P11 (0x1 << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P12 (0x1 << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P13 (0x1 << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P14 (0x1 << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P15 (0x1 << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P16 (0x1 << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P17 (0x1 << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P18 (0x1 << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P19 (0x1 << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P20 (0x1 << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P21 (0x1 << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P22 (0x1 << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P23 (0x1 << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P24 (0x1 << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P25 (0x1 << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P26 (0x1 << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P27 (0x1 << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P28 (0x1 << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P29 (0x1 << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P30 (0x1 << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P31 (0x1 << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ -#define PIO_ISR_P0 (0x1 << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P1 (0x1 << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P2 (0x1 << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P3 (0x1 << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P4 (0x1 << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P5 (0x1 << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P6 (0x1 << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P7 (0x1 << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P8 (0x1 << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P9 (0x1 << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P10 (0x1 << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P11 (0x1 << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P12 (0x1 << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P13 (0x1 << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P14 (0x1 << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P15 (0x1 << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P16 (0x1 << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P17 (0x1 << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P18 (0x1 << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P19 (0x1 << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P20 (0x1 << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P21 (0x1 << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P22 (0x1 << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P23 (0x1 << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P24 (0x1 << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P25 (0x1 << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P26 (0x1 << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P27 (0x1 << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P28 (0x1 << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P29 (0x1 << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P30 (0x1 << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P31 (0x1 << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ -#define PIO_MDER_P0 (0x1 << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P1 (0x1 << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P2 (0x1 << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P3 (0x1 << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P4 (0x1 << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P5 (0x1 << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P6 (0x1 << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P7 (0x1 << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P8 (0x1 << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P9 (0x1 << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P10 (0x1 << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P11 (0x1 << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P12 (0x1 << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P13 (0x1 << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P14 (0x1 << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P15 (0x1 << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P16 (0x1 << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P17 (0x1 << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P18 (0x1 << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P19 (0x1 << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P20 (0x1 << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P21 (0x1 << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P22 (0x1 << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P23 (0x1 << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P24 (0x1 << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P25 (0x1 << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P26 (0x1 << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P27 (0x1 << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P28 (0x1 << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P29 (0x1 << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P30 (0x1 << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P31 (0x1 << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ -/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ -#define PIO_MDDR_P0 (0x1 << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P1 (0x1 << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P2 (0x1 << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P3 (0x1 << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P4 (0x1 << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P5 (0x1 << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P6 (0x1 << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P7 (0x1 << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P8 (0x1 << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P9 (0x1 << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P10 (0x1 << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P11 (0x1 << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P12 (0x1 << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P13 (0x1 << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P14 (0x1 << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P15 (0x1 << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P16 (0x1 << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P17 (0x1 << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P18 (0x1 << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P19 (0x1 << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P20 (0x1 << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P21 (0x1 << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P22 (0x1 << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P23 (0x1 << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P24 (0x1 << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P25 (0x1 << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P26 (0x1 << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P27 (0x1 << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P28 (0x1 << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P29 (0x1 << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P30 (0x1 << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P31 (0x1 << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ -#define PIO_MDSR_P0 (0x1 << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P1 (0x1 << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P2 (0x1 << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P3 (0x1 << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P4 (0x1 << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P5 (0x1 << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P6 (0x1 << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P7 (0x1 << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P8 (0x1 << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P9 (0x1 << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P10 (0x1 << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P11 (0x1 << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P12 (0x1 << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P13 (0x1 << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P14 (0x1 << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P15 (0x1 << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P16 (0x1 << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P17 (0x1 << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P18 (0x1 << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P19 (0x1 << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P20 (0x1 << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P21 (0x1 << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P22 (0x1 << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P23 (0x1 << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P24 (0x1 << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P25 (0x1 << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P26 (0x1 << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P27 (0x1 << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P28 (0x1 << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P29 (0x1 << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P30 (0x1 << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P31 (0x1 << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ -/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ -#define PIO_PUDR_P0 (0x1 << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P1 (0x1 << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P2 (0x1 << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P3 (0x1 << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P4 (0x1 << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P5 (0x1 << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P6 (0x1 << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P7 (0x1 << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P8 (0x1 << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P9 (0x1 << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P10 (0x1 << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P11 (0x1 << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P12 (0x1 << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P13 (0x1 << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P14 (0x1 << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P15 (0x1 << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P16 (0x1 << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P17 (0x1 << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P18 (0x1 << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P19 (0x1 << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P20 (0x1 << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P21 (0x1 << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P22 (0x1 << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P23 (0x1 << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P24 (0x1 << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P25 (0x1 << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P26 (0x1 << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P27 (0x1 << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P28 (0x1 << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P29 (0x1 << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P30 (0x1 << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P31 (0x1 << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ -/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ -#define PIO_PUER_P0 (0x1 << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P1 (0x1 << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P2 (0x1 << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P3 (0x1 << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P4 (0x1 << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P5 (0x1 << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P6 (0x1 << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P7 (0x1 << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P8 (0x1 << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P9 (0x1 << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P10 (0x1 << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P11 (0x1 << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P12 (0x1 << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P13 (0x1 << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P14 (0x1 << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P15 (0x1 << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P16 (0x1 << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P17 (0x1 << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P18 (0x1 << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P19 (0x1 << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P20 (0x1 << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P21 (0x1 << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P22 (0x1 << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P23 (0x1 << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P24 (0x1 << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P25 (0x1 << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P26 (0x1 << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P27 (0x1 << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P28 (0x1 << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P29 (0x1 << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P30 (0x1 << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P31 (0x1 << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ -/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ -#define PIO_PUSR_P0 (0x1 << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P1 (0x1 << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P2 (0x1 << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P3 (0x1 << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P4 (0x1 << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P5 (0x1 << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P6 (0x1 << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P7 (0x1 << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P8 (0x1 << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P9 (0x1 << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P10 (0x1 << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P11 (0x1 << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P12 (0x1 << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P13 (0x1 << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P14 (0x1 << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P15 (0x1 << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P16 (0x1 << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P17 (0x1 << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P18 (0x1 << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P19 (0x1 << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P20 (0x1 << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P21 (0x1 << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P22 (0x1 << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P23 (0x1 << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P24 (0x1 << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P25 (0x1 << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P26 (0x1 << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P27 (0x1 << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P28 (0x1 << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P29 (0x1 << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P30 (0x1 << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P31 (0x1 << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ -/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ -#define PIO_ABCDSR_P0 (0x1 << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P1 (0x1 << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P2 (0x1 << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P3 (0x1 << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P4 (0x1 << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P5 (0x1 << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P6 (0x1 << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P7 (0x1 << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P8 (0x1 << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P9 (0x1 << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P10 (0x1 << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P11 (0x1 << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P12 (0x1 << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P13 (0x1 << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P14 (0x1 << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P15 (0x1 << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P16 (0x1 << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P17 (0x1 << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P18 (0x1 << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P19 (0x1 << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P20 (0x1 << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P21 (0x1 << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P22 (0x1 << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P23 (0x1 << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P24 (0x1 << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P25 (0x1 << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P26 (0x1 << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P27 (0x1 << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P28 (0x1 << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P29 (0x1 << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P30 (0x1 << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P31 (0x1 << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */ -#define PIO_SCIFSR_P0 (0x1 << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P1 (0x1 << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P2 (0x1 << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P3 (0x1 << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P4 (0x1 << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P5 (0x1 << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P6 (0x1 << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P7 (0x1 << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P8 (0x1 << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P9 (0x1 << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P10 (0x1 << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P11 (0x1 << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P12 (0x1 << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P13 (0x1 << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P14 (0x1 << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P15 (0x1 << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P16 (0x1 << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P17 (0x1 << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P18 (0x1 << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P19 (0x1 << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P20 (0x1 << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P21 (0x1 << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P22 (0x1 << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P23 (0x1 << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P24 (0x1 << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P25 (0x1 << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P26 (0x1 << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P27 (0x1 << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P28 (0x1 << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P29 (0x1 << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P30 (0x1 << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P31 (0x1 << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */ -#define PIO_DIFSR_P0 (0x1 << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P1 (0x1 << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P2 (0x1 << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P3 (0x1 << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P4 (0x1 << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P5 (0x1 << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P6 (0x1 << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P7 (0x1 << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P8 (0x1 << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P9 (0x1 << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P10 (0x1 << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P11 (0x1 << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P12 (0x1 << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P13 (0x1 << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P14 (0x1 << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P15 (0x1 << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P16 (0x1 << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P17 (0x1 << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P18 (0x1 << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P19 (0x1 << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P20 (0x1 << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P21 (0x1 << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P22 (0x1 << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P23 (0x1 << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P24 (0x1 << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P25 (0x1 << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P26 (0x1 << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P27 (0x1 << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P28 (0x1 << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P29 (0x1 << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P30 (0x1 << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P31 (0x1 << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */ -#define PIO_IFDGSR_P0 (0x1 << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P1 (0x1 << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P2 (0x1 << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P3 (0x1 << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P4 (0x1 << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P5 (0x1 << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P6 (0x1 << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P7 (0x1 << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P8 (0x1 << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P9 (0x1 << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P10 (0x1 << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P11 (0x1 << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P12 (0x1 << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P13 (0x1 << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P14 (0x1 << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P15 (0x1 << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P16 (0x1 << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P17 (0x1 << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P18 (0x1 << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P19 (0x1 << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P20 (0x1 << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P21 (0x1 << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P22 (0x1 << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P23 (0x1 << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P24 (0x1 << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P25 (0x1 << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P26 (0x1 << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P27 (0x1 << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P28 (0x1 << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P29 (0x1 << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P30 (0x1 << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P31 (0x1 << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ -#define PIO_SCDR_DIV0 (0x1 << 0) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV1 (0x1 << 1) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV2 (0x1 << 2) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV3 (0x1 << 3) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV4 (0x1 << 4) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV5 (0x1 << 5) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV6 (0x1 << 6) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV7 (0x1 << 7) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV8 (0x1 << 8) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV9 (0x1 << 9) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV10 (0x1 << 10) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV11 (0x1 << 11) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV12 (0x1 << 12) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV13 (0x1 << 13) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ -#define PIO_PPDDR_P0 (0x1 << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P1 (0x1 << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P2 (0x1 << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P3 (0x1 << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P4 (0x1 << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P5 (0x1 << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P6 (0x1 << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P7 (0x1 << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P8 (0x1 << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P9 (0x1 << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P10 (0x1 << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P11 (0x1 << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P12 (0x1 << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P13 (0x1 << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P14 (0x1 << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P15 (0x1 << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P16 (0x1 << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P17 (0x1 << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P18 (0x1 << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P19 (0x1 << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P20 (0x1 << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P21 (0x1 << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P22 (0x1 << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P23 (0x1 << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P24 (0x1 << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P25 (0x1 << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P26 (0x1 << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P27 (0x1 << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P28 (0x1 << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P29 (0x1 << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P30 (0x1 << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P31 (0x1 << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ -#define PIO_PPDER_P0 (0x1 << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P1 (0x1 << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P2 (0x1 << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P3 (0x1 << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P4 (0x1 << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P5 (0x1 << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P6 (0x1 << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P7 (0x1 << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P8 (0x1 << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P9 (0x1 << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P10 (0x1 << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P11 (0x1 << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P12 (0x1 << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P13 (0x1 << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P14 (0x1 << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P15 (0x1 << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P16 (0x1 << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P17 (0x1 << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P18 (0x1 << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P19 (0x1 << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P20 (0x1 << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P21 (0x1 << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P22 (0x1 << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P23 (0x1 << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P24 (0x1 << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P25 (0x1 << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P26 (0x1 << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P27 (0x1 << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P28 (0x1 << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P29 (0x1 << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P30 (0x1 << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P31 (0x1 << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */ -/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ -#define PIO_PPDSR_P0 (0x1 << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P1 (0x1 << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P2 (0x1 << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P3 (0x1 << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P4 (0x1 << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P5 (0x1 << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P6 (0x1 << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P7 (0x1 << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P8 (0x1 << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P9 (0x1 << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P10 (0x1 << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P11 (0x1 << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P12 (0x1 << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P13 (0x1 << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P14 (0x1 << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P15 (0x1 << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P16 (0x1 << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P17 (0x1 << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P18 (0x1 << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P19 (0x1 << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P20 (0x1 << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P21 (0x1 << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P22 (0x1 << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P23 (0x1 << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P24 (0x1 << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P25 (0x1 << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P26 (0x1 << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P27 (0x1 << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P28 (0x1 << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P29 (0x1 << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P30 (0x1 << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P31 (0x1 << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */ -/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ -#define PIO_OWER_P0 (0x1 << 0) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P1 (0x1 << 1) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P2 (0x1 << 2) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P3 (0x1 << 3) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P4 (0x1 << 4) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P5 (0x1 << 5) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P6 (0x1 << 6) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P7 (0x1 << 7) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P8 (0x1 << 8) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P9 (0x1 << 9) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P10 (0x1 << 10) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P11 (0x1 << 11) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P12 (0x1 << 12) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P13 (0x1 << 13) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P14 (0x1 << 14) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P15 (0x1 << 15) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P16 (0x1 << 16) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P17 (0x1 << 17) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P18 (0x1 << 18) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P19 (0x1 << 19) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P20 (0x1 << 20) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P21 (0x1 << 21) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P22 (0x1 << 22) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P23 (0x1 << 23) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P24 (0x1 << 24) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P25 (0x1 << 25) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P26 (0x1 << 26) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P27 (0x1 << 27) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P28 (0x1 << 28) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P29 (0x1 << 29) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P30 (0x1 << 30) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P31 (0x1 << 31) /**< \brief (PIO_OWER) Output Write Enable. */ -/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ -#define PIO_OWDR_P0 (0x1 << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P1 (0x1 << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P2 (0x1 << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P3 (0x1 << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P4 (0x1 << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P5 (0x1 << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P6 (0x1 << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P7 (0x1 << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P8 (0x1 << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P9 (0x1 << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P10 (0x1 << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P11 (0x1 << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P12 (0x1 << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P13 (0x1 << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P14 (0x1 << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P15 (0x1 << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P16 (0x1 << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P17 (0x1 << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P18 (0x1 << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P19 (0x1 << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P20 (0x1 << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P21 (0x1 << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P22 (0x1 << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P23 (0x1 << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P24 (0x1 << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P25 (0x1 << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P26 (0x1 << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P27 (0x1 << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P28 (0x1 << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P29 (0x1 << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P30 (0x1 << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P31 (0x1 << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ -/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ -#define PIO_OWSR_P0 (0x1 << 0) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P1 (0x1 << 1) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P2 (0x1 << 2) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P3 (0x1 << 3) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P4 (0x1 << 4) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P5 (0x1 << 5) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P6 (0x1 << 6) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P7 (0x1 << 7) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P8 (0x1 << 8) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P9 (0x1 << 9) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P10 (0x1 << 10) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P11 (0x1 << 11) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P12 (0x1 << 12) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P13 (0x1 << 13) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P14 (0x1 << 14) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P15 (0x1 << 15) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P16 (0x1 << 16) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P17 (0x1 << 17) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P18 (0x1 << 18) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P19 (0x1 << 19) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P20 (0x1 << 20) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P21 (0x1 << 21) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P22 (0x1 << 22) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P23 (0x1 << 23) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P24 (0x1 << 24) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P25 (0x1 << 25) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P26 (0x1 << 26) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P27 (0x1 << 27) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P28 (0x1 << 28) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P29 (0x1 << 29) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P30 (0x1 << 30) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P31 (0x1 << 31) /**< \brief (PIO_OWSR) Output Write Status. */ -/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ -#define PIO_AIMER_P0 (0x1 << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P1 (0x1 << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P2 (0x1 << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P3 (0x1 << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P4 (0x1 << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P5 (0x1 << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P6 (0x1 << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P7 (0x1 << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P8 (0x1 << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P9 (0x1 << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P10 (0x1 << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P11 (0x1 << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P12 (0x1 << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P13 (0x1 << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P14 (0x1 << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P15 (0x1 << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P16 (0x1 << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P17 (0x1 << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P18 (0x1 << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P19 (0x1 << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P20 (0x1 << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P21 (0x1 << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P22 (0x1 << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P23 (0x1 << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P24 (0x1 << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P25 (0x1 << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P26 (0x1 << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P27 (0x1 << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P28 (0x1 << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P29 (0x1 << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P30 (0x1 << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P31 (0x1 << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ -#define PIO_AIMDR_P0 (0x1 << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P1 (0x1 << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P2 (0x1 << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P3 (0x1 << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P4 (0x1 << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P5 (0x1 << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P6 (0x1 << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P7 (0x1 << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P8 (0x1 << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P9 (0x1 << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P10 (0x1 << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P11 (0x1 << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P12 (0x1 << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P13 (0x1 << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P14 (0x1 << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P15 (0x1 << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P16 (0x1 << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P17 (0x1 << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P18 (0x1 << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P19 (0x1 << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P20 (0x1 << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P21 (0x1 << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P22 (0x1 << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P23 (0x1 << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P24 (0x1 << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P25 (0x1 << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P26 (0x1 << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P27 (0x1 << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P28 (0x1 << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P29 (0x1 << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P30 (0x1 << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P31 (0x1 << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ -#define PIO_AIMMR_P0 (0x1 << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P1 (0x1 << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P2 (0x1 << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P3 (0x1 << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P4 (0x1 << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P5 (0x1 << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P6 (0x1 << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P7 (0x1 << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P8 (0x1 << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P9 (0x1 << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P10 (0x1 << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P11 (0x1 << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P12 (0x1 << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P13 (0x1 << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P14 (0x1 << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P15 (0x1 << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P16 (0x1 << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P17 (0x1 << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P18 (0x1 << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P19 (0x1 << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P20 (0x1 << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P21 (0x1 << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P22 (0x1 << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P23 (0x1 << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P24 (0x1 << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P25 (0x1 << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P26 (0x1 << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P27 (0x1 << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P28 (0x1 << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P29 (0x1 << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P30 (0x1 << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P31 (0x1 << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ -#define PIO_ESR_P0 (0x1 << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P1 (0x1 << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P2 (0x1 << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P3 (0x1 << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P4 (0x1 << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P5 (0x1 << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P6 (0x1 << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P7 (0x1 << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P8 (0x1 << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P9 (0x1 << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P10 (0x1 << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P11 (0x1 << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P12 (0x1 << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P13 (0x1 << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P14 (0x1 << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P15 (0x1 << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P16 (0x1 << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P17 (0x1 << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P18 (0x1 << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P19 (0x1 << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P20 (0x1 << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P21 (0x1 << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P22 (0x1 << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P23 (0x1 << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P24 (0x1 << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P25 (0x1 << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P26 (0x1 << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P27 (0x1 << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P28 (0x1 << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P29 (0x1 << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P30 (0x1 << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P31 (0x1 << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ -#define PIO_LSR_P0 (0x1 << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P1 (0x1 << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P2 (0x1 << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P3 (0x1 << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P4 (0x1 << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P5 (0x1 << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P6 (0x1 << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P7 (0x1 << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P8 (0x1 << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P9 (0x1 << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P10 (0x1 << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P11 (0x1 << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P12 (0x1 << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P13 (0x1 << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P14 (0x1 << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P15 (0x1 << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P16 (0x1 << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P17 (0x1 << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P18 (0x1 << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P19 (0x1 << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P20 (0x1 << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P21 (0x1 << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P22 (0x1 << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P23 (0x1 << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P24 (0x1 << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P25 (0x1 << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P26 (0x1 << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P27 (0x1 << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P28 (0x1 << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P29 (0x1 << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P30 (0x1 << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P31 (0x1 << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ -#define PIO_ELSR_P0 (0x1 << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P1 (0x1 << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P2 (0x1 << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P3 (0x1 << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P4 (0x1 << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P5 (0x1 << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P6 (0x1 << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P7 (0x1 << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P8 (0x1 << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P9 (0x1 << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P10 (0x1 << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P11 (0x1 << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P12 (0x1 << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P13 (0x1 << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P14 (0x1 << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P15 (0x1 << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P16 (0x1 << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P17 (0x1 << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P18 (0x1 << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P19 (0x1 << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P20 (0x1 << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P21 (0x1 << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P22 (0x1 << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P23 (0x1 << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P24 (0x1 << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P25 (0x1 << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P26 (0x1 << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P27 (0x1 << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P28 (0x1 << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P29 (0x1 << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P30 (0x1 << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P31 (0x1 << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ -#define PIO_FELLSR_P0 (0x1 << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P1 (0x1 << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P2 (0x1 << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P3 (0x1 << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P4 (0x1 << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P5 (0x1 << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P6 (0x1 << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P7 (0x1 << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P8 (0x1 << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P9 (0x1 << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P10 (0x1 << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P11 (0x1 << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P12 (0x1 << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P13 (0x1 << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P14 (0x1 << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P15 (0x1 << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P16 (0x1 << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P17 (0x1 << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P18 (0x1 << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P19 (0x1 << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P20 (0x1 << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P21 (0x1 << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P22 (0x1 << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P23 (0x1 << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P24 (0x1 << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P25 (0x1 << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P26 (0x1 << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P27 (0x1 << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P28 (0x1 << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P29 (0x1 << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P30 (0x1 << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P31 (0x1 << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ -#define PIO_REHLSR_P0 (0x1 << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P1 (0x1 << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P2 (0x1 << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P3 (0x1 << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P4 (0x1 << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P5 (0x1 << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P6 (0x1 << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P7 (0x1 << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P8 (0x1 << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P9 (0x1 << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P10 (0x1 << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P11 (0x1 << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P12 (0x1 << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P13 (0x1 << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P14 (0x1 << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P15 (0x1 << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P16 (0x1 << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P17 (0x1 << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P18 (0x1 << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P19 (0x1 << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P20 (0x1 << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P21 (0x1 << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P22 (0x1 << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P23 (0x1 << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P24 (0x1 << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P25 (0x1 << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P26 (0x1 << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P27 (0x1 << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P28 (0x1 << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P29 (0x1 << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P30 (0x1 << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P31 (0x1 << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ -#define PIO_FRLHSR_P0 (0x1 << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P1 (0x1 << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P2 (0x1 << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P3 (0x1 << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P4 (0x1 << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P5 (0x1 << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P6 (0x1 << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P7 (0x1 << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P8 (0x1 << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P9 (0x1 << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P10 (0x1 << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P11 (0x1 << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P12 (0x1 << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P13 (0x1 << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P14 (0x1 << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P15 (0x1 << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P16 (0x1 << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P17 (0x1 << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P18 (0x1 << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P19 (0x1 << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P20 (0x1 << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P21 (0x1 << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P22 (0x1 << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P23 (0x1 << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P24 (0x1 << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P25 (0x1 << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P26 (0x1 << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P27 (0x1 << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P28 (0x1 << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P29 (0x1 << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P30 (0x1 << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P31 (0x1 << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ -#define PIO_LOCKSR_P0 (0x1 << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P1 (0x1 << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P2 (0x1 << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P3 (0x1 << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P4 (0x1 << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P5 (0x1 << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P6 (0x1 << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P7 (0x1 << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P8 (0x1 << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P9 (0x1 << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P10 (0x1 << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P11 (0x1 << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P12 (0x1 << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P13 (0x1 << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P14 (0x1 << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P15 (0x1 << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P16 (0x1 << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P17 (0x1 << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P18 (0x1 << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P19 (0x1 << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P20 (0x1 << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P21 (0x1 << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P22 (0x1 << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P23 (0x1 << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P24 (0x1 << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P25 (0x1 << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P26 (0x1 << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P27 (0x1 << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P28 (0x1 << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P29 (0x1 << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P30 (0x1 << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P31 (0x1 << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ -/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PIO_WPMR_WPEN (0x1 << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ -#define PIO_WPMR_WPKEY (0xffffff << 8) /**< \brief (PIO_WPMR) Write Protect KEY */ -/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ -#define PIO_WPSR_WPVS (0x1 << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ -#define PIO_WPSR_WPVSRC (0xffff << 8) /**< \brief (PIO_WPSR) Write Protect Violation Source */ -/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ -#define PIO_SCHMITT_SCHMITT0 (0x1 << 0) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT1 (0x1 << 1) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT2 (0x1 << 2) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT3 (0x1 << 3) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT4 (0x1 << 4) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT5 (0x1 << 5) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT6 (0x1 << 6) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT7 (0x1 << 7) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT8 (0x1 << 8) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT9 (0x1 << 9) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT10 (0x1 << 10) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT11 (0x1 << 11) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT12 (0x1 << 12) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT13 (0x1 << 13) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT14 (0x1 << 14) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT15 (0x1 << 15) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT16 (0x1 << 16) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT17 (0x1 << 17) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT18 (0x1 << 18) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT19 (0x1 << 19) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT20 (0x1 << 20) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT21 (0x1 << 21) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT22 (0x1 << 22) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT23 (0x1 << 23) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT24 (0x1 << 24) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT25 (0x1 << 25) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT26 (0x1 << 26) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT27 (0x1 << 27) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT28 (0x1 << 28) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT29 (0x1 << 29) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT30 (0x1 << 30) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT31 (0x1 << 31) /**< \brief (PIO_SCHMITT) */ -/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */ -#define PIO_PCMR_PCEN (0x1 << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ -#define PIO_PCMR_DSIZE (0x3 << 4) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ -#define PIO_PCMR_ALWYS (0x1 << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ -#define PIO_PCMR_HALFS (0x1 << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ -#define PIO_PCMR_FRSTS (0x1 << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ -/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */ -#define PIO_PCIER_DRDY (0x1 << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ -#define PIO_PCIER_OVRE (0x1 << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ -#define PIO_PCIER_ENDRX (0x1 << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ -#define PIO_PCIER_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ -/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */ -#define PIO_PCIDR_DRDY (0x1 << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ -#define PIO_PCIDR_OVRE (0x1 << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ -#define PIO_PCIDR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ -#define PIO_PCIDR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ -/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */ -#define PIO_PCIMR_DRDY (0x1 << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ -#define PIO_PCIMR_OVRE (0x1 << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ -#define PIO_PCIMR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ -#define PIO_PCIMR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ -/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */ -#define PIO_PCISR_DRDY (0x1 << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ -#define PIO_PCISR_OVRE (0x1 << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */ -#define PIO_PCISR_ENDRX (0x1 << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */ -#define PIO_PCISR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */ -/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */ -#define PIO_PCRHR_RDATA (0xffffffff << 0) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Power Management Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PMC Power Management Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pmc hardware registers */ -typedef struct { - WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ - WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ - RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ - RwReg Reserved1[1]; - WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ - WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ - RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ - RwReg Reserved2[1]; - RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ - RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ - RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ - RwReg CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */ - RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ - RwReg Reserved3[1]; - RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ - RwReg Reserved4[1]; - RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ - RwReg Reserved5[5]; - WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ - WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ - RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ - RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ - RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ - RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ - WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ - RwReg Reserved6[26]; - RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ - RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ - RwReg Reserved7[5]; - WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ - WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ - RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ - RwReg Reserved8[1]; - RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ -} Pmc; -#endif /* __ASSEMBLY__ */ -/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ -#define PMC_SCER_UDP (0x1 << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */ -#define PMC_SCER_PCK0 (0x1 << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ -#define PMC_SCER_PCK1 (0x1 << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ -#define PMC_SCER_PCK2 (0x1 << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ -/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ -#define PMC_SCDR_UDP (0x1 << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */ -#define PMC_SCDR_PCK0 (0x1 << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ -#define PMC_SCDR_PCK1 (0x1 << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ -#define PMC_SCDR_PCK2 (0x1 << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ -/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ -#define PMC_SCSR_UDP (0x1 << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */ -#define PMC_SCSR_PCK0 (0x1 << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ -#define PMC_SCSR_PCK1 (0x1 << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ -#define PMC_SCSR_PCK2 (0x1 << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ -/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ -#define PMC_PCER0_PID2 (0x1 << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */ -#define PMC_PCER0_PID3 (0x1 << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */ -#define PMC_PCER0_PID4 (0x1 << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */ -#define PMC_PCER0_PID5 (0x1 << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */ -#define PMC_PCER0_PID6 (0x1 << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */ -#define PMC_PCER0_PID7 (0x1 << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ -#define PMC_PCER0_PID8 (0x1 << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ -#define PMC_PCER0_PID9 (0x1 << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ -#define PMC_PCER0_PID10 (0x1 << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ -#define PMC_PCER0_PID11 (0x1 << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ -#define PMC_PCER0_PID12 (0x1 << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ -#define PMC_PCER0_PID13 (0x1 << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ -#define PMC_PCER0_PID14 (0x1 << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ -#define PMC_PCER0_PID15 (0x1 << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ -#define PMC_PCER0_PID16 (0x1 << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ -#define PMC_PCER0_PID17 (0x1 << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ -#define PMC_PCER0_PID18 (0x1 << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ -#define PMC_PCER0_PID19 (0x1 << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ -#define PMC_PCER0_PID20 (0x1 << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ -#define PMC_PCER0_PID21 (0x1 << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ -#define PMC_PCER0_PID22 (0x1 << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ -#define PMC_PCER0_PID23 (0x1 << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ -#define PMC_PCER0_PID24 (0x1 << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ -#define PMC_PCER0_PID25 (0x1 << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ -#define PMC_PCER0_PID26 (0x1 << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ -#define PMC_PCER0_PID27 (0x1 << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ -#define PMC_PCER0_PID28 (0x1 << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ -#define PMC_PCER0_PID29 (0x1 << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ -#define PMC_PCER0_PID30 (0x1 << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ -#define PMC_PCER0_PID31 (0x1 << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ -/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ -#define PMC_PCDR0_PID2 (0x1 << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */ -#define PMC_PCDR0_PID3 (0x1 << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */ -#define PMC_PCDR0_PID4 (0x1 << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */ -#define PMC_PCDR0_PID5 (0x1 << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */ -#define PMC_PCDR0_PID6 (0x1 << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */ -#define PMC_PCDR0_PID7 (0x1 << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ -#define PMC_PCDR0_PID8 (0x1 << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ -#define PMC_PCDR0_PID9 (0x1 << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ -#define PMC_PCDR0_PID10 (0x1 << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ -#define PMC_PCDR0_PID11 (0x1 << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ -#define PMC_PCDR0_PID12 (0x1 << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ -#define PMC_PCDR0_PID13 (0x1 << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ -#define PMC_PCDR0_PID14 (0x1 << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ -#define PMC_PCDR0_PID15 (0x1 << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ -#define PMC_PCDR0_PID16 (0x1 << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ -#define PMC_PCDR0_PID17 (0x1 << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ -#define PMC_PCDR0_PID18 (0x1 << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ -#define PMC_PCDR0_PID19 (0x1 << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ -#define PMC_PCDR0_PID20 (0x1 << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ -#define PMC_PCDR0_PID21 (0x1 << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ -#define PMC_PCDR0_PID22 (0x1 << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ -#define PMC_PCDR0_PID23 (0x1 << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ -#define PMC_PCDR0_PID24 (0x1 << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ -#define PMC_PCDR0_PID25 (0x1 << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ -#define PMC_PCDR0_PID26 (0x1 << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ -#define PMC_PCDR0_PID27 (0x1 << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ -#define PMC_PCDR0_PID28 (0x1 << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ -#define PMC_PCDR0_PID29 (0x1 << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ -#define PMC_PCDR0_PID30 (0x1 << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ -#define PMC_PCDR0_PID31 (0x1 << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ -/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ -#define PMC_PCSR0_PID2 (0x1 << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */ -#define PMC_PCSR0_PID3 (0x1 << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */ -#define PMC_PCSR0_PID4 (0x1 << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */ -#define PMC_PCSR0_PID5 (0x1 << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */ -#define PMC_PCSR0_PID6 (0x1 << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */ -#define PMC_PCSR0_PID7 (0x1 << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ -#define PMC_PCSR0_PID8 (0x1 << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ -#define PMC_PCSR0_PID9 (0x1 << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ -#define PMC_PCSR0_PID10 (0x1 << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ -#define PMC_PCSR0_PID11 (0x1 << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ -#define PMC_PCSR0_PID12 (0x1 << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ -#define PMC_PCSR0_PID13 (0x1 << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ -#define PMC_PCSR0_PID14 (0x1 << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ -#define PMC_PCSR0_PID15 (0x1 << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ -#define PMC_PCSR0_PID16 (0x1 << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ -#define PMC_PCSR0_PID17 (0x1 << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ -#define PMC_PCSR0_PID18 (0x1 << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ -#define PMC_PCSR0_PID19 (0x1 << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ -#define PMC_PCSR0_PID20 (0x1 << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ -#define PMC_PCSR0_PID21 (0x1 << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ -#define PMC_PCSR0_PID22 (0x1 << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ -#define PMC_PCSR0_PID23 (0x1 << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ -#define PMC_PCSR0_PID24 (0x1 << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ -#define PMC_PCSR0_PID25 (0x1 << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ -#define PMC_PCSR0_PID26 (0x1 << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ -#define PMC_PCSR0_PID27 (0x1 << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ -#define PMC_PCSR0_PID28 (0x1 << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ -#define PMC_PCSR0_PID29 (0x1 << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ -#define PMC_PCSR0_PID30 (0x1 << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ -#define PMC_PCSR0_PID31 (0x1 << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ -/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ -#define CKGR_MOR_MOSCXTEN (0x1 << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ -#define CKGR_MOR_MOSCXTBY (0x1 << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ -#define CKGR_MOR_WAITMODE (0x1 << 2) /**< \brief (CKGR_MOR) Wait Mode Command */ -#define CKGR_MOR_MOSCRCEN (0x1 << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ -#define CKGR_MOR_MOSCRCF (0x7 << 4) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ -#define CKGR_MOR_MOSCXTST (0xff << 8) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ -#define CKGR_MOR_KEY (0xff << 16) /**< \brief (CKGR_MOR) Password */ -#define CKGR_MOR_MOSCSEL (0x1 << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ -#define CKGR_MOR_CFDEN (0x1 << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ -/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ -#define CKGR_MCFR_MAINF (0xffff << 0) /**< \brief (CKGR_MCFR) Main Clock Frequency */ -#define CKGR_MCFR_MAINFRDY (0x1 << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ -/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ -#define CKGR_PLLAR_DIVA (0xff << 0) /**< \brief (CKGR_PLLAR) Divider */ -#define CKGR_PLLAR_PLLACOUNT (0x3f << 8) /**< \brief (CKGR_PLLAR) PLLA Counter */ -#define CKGR_PLLAR_MULA (0x7ff << 16) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ -#define CKGR_PLLAR_STUCKTO1 (0x1 << 29) /**< \brief (CKGR_PLLAR) */ -/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */ -#define CKGR_PLLBR_DIVB (0xff << 0) /**< \brief (CKGR_PLLBR) Divider */ -#define CKGR_PLLBR_PLLBCOUNT (0x3f << 8) /**< \brief (CKGR_PLLBR) PLLB Counter */ -#define CKGR_PLLBR_MULB (0x7ff << 16) /**< \brief (CKGR_PLLBR) PLLB Multiplier */ -/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ -#define PMC_MCKR_CSS (0x3 << 0) /**< \brief (PMC_MCKR) Master Clock Source Selection */ -#define PMC_MCKR_CSS_SLOW_CLK (0x0 << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ -#define PMC_MCKR_CSS_MAIN_CLK (0x1 << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ -#define PMC_MCKR_CSS_PLLA_CLK (0x2 << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ -#define PMC_MCKR_CSS_PLLB_CLK (0x3 << 0) /**< \brief (PMC_MCKR) PLLB Clock is selected */ -#define PMC_MCKR_PRES (0x7 << 4) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ -#define PMC_MCKR_PRES_CLK (0x0 << 4) /**< \brief (PMC_MCKR) Selected clock */ -#define PMC_MCKR_PRES_CLK_2 (0x1 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ -#define PMC_MCKR_PRES_CLK_4 (0x2 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ -#define PMC_MCKR_PRES_CLK_8 (0x3 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ -#define PMC_MCKR_PRES_CLK_16 (0x4 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ -#define PMC_MCKR_PRES_CLK_32 (0x5 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ -#define PMC_MCKR_PRES_CLK_64 (0x6 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ -#define PMC_MCKR_PLLADIV2 (0x1 << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */ -#define PMC_MCKR_PLLBDIV2 (0x1 << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */ -/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ -#define PMC_USB_USBS (0x1 << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ -#define PMC_USB_USBDIV (0xf << 8) /**< \brief (PMC_USB) Divider for USB Clock. */ -/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ -#define PMC_PCK_CSS (0x7 << 0) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ -#define PMC_PCK_PRES (0x7 << 4) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ -/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ -#define PMC_IER_MOSCXTS (0x1 << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ -#define PMC_IER_LOCKA (0x1 << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ -#define PMC_IER_LOCKB (0x1 << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */ -#define PMC_IER_MCKRDY (0x1 << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ -#define PMC_IER_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ -#define PMC_IER_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ -#define PMC_IER_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ -#define PMC_IER_MOSCSELS (0x1 << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ -#define PMC_IER_MOSCRCS (0x1 << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ -#define PMC_IER_CFDEV (0x1 << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ -/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ -#define PMC_IDR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ -#define PMC_IDR_LOCKA (0x1 << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ -#define PMC_IDR_LOCKB (0x1 << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */ -#define PMC_IDR_MCKRDY (0x1 << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ -#define PMC_IDR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ -#define PMC_IDR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ -#define PMC_IDR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ -#define PMC_IDR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ -#define PMC_IDR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ -#define PMC_IDR_CFDEV (0x1 << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ -/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ -#define PMC_SR_MOSCXTS (0x1 << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ -#define PMC_SR_LOCKA (0x1 << 1) /**< \brief (PMC_SR) PLLA Lock Status */ -#define PMC_SR_LOCKB (0x1 << 2) /**< \brief (PMC_SR) PLLB Lock Status */ -#define PMC_SR_MCKRDY (0x1 << 3) /**< \brief (PMC_SR) Master Clock Status */ -#define PMC_SR_OSCSELS (0x1 << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ -#define PMC_SR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_MOSCSELS (0x1 << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ -#define PMC_SR_MOSCRCS (0x1 << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ -#define PMC_SR_CFDEV (0x1 << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ -#define PMC_SR_CFDS (0x1 << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ -#define PMC_SR_FOS (0x1 << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ -/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ -#define PMC_IMR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ -#define PMC_IMR_LOCKA (0x1 << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ -#define PMC_IMR_LOCKB (0x1 << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */ -#define PMC_IMR_MCKRDY (0x1 << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ -#define PMC_IMR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ -#define PMC_IMR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ -#define PMC_IMR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ -#define PMC_IMR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ -#define PMC_IMR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ -#define PMC_IMR_CFDEV (0x1 << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ -/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ -#define PMC_FSMR_FSTT0 (0x1 << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ -#define PMC_FSMR_FSTT1 (0x1 << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ -#define PMC_FSMR_FSTT2 (0x1 << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ -#define PMC_FSMR_FSTT3 (0x1 << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ -#define PMC_FSMR_FSTT4 (0x1 << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ -#define PMC_FSMR_FSTT5 (0x1 << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ -#define PMC_FSMR_FSTT6 (0x1 << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ -#define PMC_FSMR_FSTT7 (0x1 << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ -#define PMC_FSMR_FSTT8 (0x1 << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ -#define PMC_FSMR_FSTT9 (0x1 << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ -#define PMC_FSMR_FSTT10 (0x1 << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ -#define PMC_FSMR_FSTT11 (0x1 << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ -#define PMC_FSMR_FSTT12 (0x1 << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ -#define PMC_FSMR_FSTT13 (0x1 << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ -#define PMC_FSMR_FSTT14 (0x1 << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ -#define PMC_FSMR_FSTT15 (0x1 << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ -#define PMC_FSMR_RTTAL (0x1 << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ -#define PMC_FSMR_RTCAL (0x1 << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ -#define PMC_FSMR_USBAL (0x1 << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ -#define PMC_FSMR_LPM (0x1 << 20) /**< \brief (PMC_FSMR) Low Power Mode */ -/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ -#define PMC_FSPR_FSTP0 (0x1 << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP1 (0x1 << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP2 (0x1 << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP3 (0x1 << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP4 (0x1 << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP5 (0x1 << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP6 (0x1 << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP7 (0x1 << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP8 (0x1 << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP9 (0x1 << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP10 (0x1 << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP11 (0x1 << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP12 (0x1 << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP13 (0x1 << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP14 (0x1 << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP15 (0x1 << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ -#define PMC_FOCR_FOCLR (0x1 << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ -/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PMC_WPMR_WPEN (0x1 << 0) /**< \brief (PMC_WPMR) Write Protect Enable */ -#define PMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (PMC_WPMR) Write Protect KEY */ -/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */ -#define PMC_WPSR_WPVS (0x1 << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */ -#define PMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (PMC_WPSR) Write Protect Violation Source */ -/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ -#define PMC_PCER1_PID32 (0x1 << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ -#define PMC_PCER1_PID33 (0x1 << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ -#define PMC_PCER1_PID34 (0x1 << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ -#define PMC_PCER1_PID35 (0x1 << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ -#define PMC_PCER1_PID36 (0x1 << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */ -#define PMC_PCER1_PID37 (0x1 << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ -#define PMC_PCER1_PID38 (0x1 << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */ -#define PMC_PCER1_PID39 (0x1 << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ -#define PMC_PCER1_PID40 (0x1 << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ -#define PMC_PCER1_PID41 (0x1 << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ -#define PMC_PCER1_PID42 (0x1 << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ -#define PMC_PCER1_PID43 (0x1 << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ -#define PMC_PCER1_PID44 (0x1 << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ -#define PMC_PCER1_PID45 (0x1 << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ -#define PMC_PCER1_PID46 (0x1 << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ -#define PMC_PCER1_PID47 (0x1 << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ -#define PMC_PCER1_PID48 (0x1 << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ -#define PMC_PCER1_PID49 (0x1 << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ -#define PMC_PCER1_PID50 (0x1 << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ -#define PMC_PCER1_PID51 (0x1 << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ -#define PMC_PCER1_PID52 (0x1 << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ -#define PMC_PCER1_PID53 (0x1 << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ -#define PMC_PCER1_PID54 (0x1 << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */ -#define PMC_PCER1_PID55 (0x1 << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */ -#define PMC_PCER1_PID56 (0x1 << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ -#define PMC_PCER1_PID57 (0x1 << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ -#define PMC_PCER1_PID58 (0x1 << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ -#define PMC_PCER1_PID59 (0x1 << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ -#define PMC_PCER1_PID60 (0x1 << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ -#define PMC_PCER1_PID61 (0x1 << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */ -#define PMC_PCER1_PID62 (0x1 << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */ -#define PMC_PCER1_PID63 (0x1 << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */ -/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ -#define PMC_PCDR1_PID32 (0x1 << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ -#define PMC_PCDR1_PID33 (0x1 << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ -#define PMC_PCDR1_PID34 (0x1 << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ -#define PMC_PCDR1_PID35 (0x1 << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ -#define PMC_PCDR1_PID36 (0x1 << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */ -#define PMC_PCDR1_PID37 (0x1 << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ -#define PMC_PCDR1_PID38 (0x1 << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */ -#define PMC_PCDR1_PID39 (0x1 << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ -#define PMC_PCDR1_PID40 (0x1 << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ -#define PMC_PCDR1_PID41 (0x1 << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ -#define PMC_PCDR1_PID42 (0x1 << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ -#define PMC_PCDR1_PID43 (0x1 << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ -#define PMC_PCDR1_PID44 (0x1 << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ -#define PMC_PCDR1_PID45 (0x1 << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ -#define PMC_PCDR1_PID46 (0x1 << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ -#define PMC_PCDR1_PID47 (0x1 << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ -#define PMC_PCDR1_PID48 (0x1 << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ -#define PMC_PCDR1_PID49 (0x1 << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ -#define PMC_PCDR1_PID50 (0x1 << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ -#define PMC_PCDR1_PID51 (0x1 << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ -#define PMC_PCDR1_PID52 (0x1 << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ -#define PMC_PCDR1_PID53 (0x1 << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ -#define PMC_PCDR1_PID54 (0x1 << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */ -#define PMC_PCDR1_PID55 (0x1 << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */ -#define PMC_PCDR1_PID56 (0x1 << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ -#define PMC_PCDR1_PID57 (0x1 << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ -#define PMC_PCDR1_PID58 (0x1 << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ -#define PMC_PCDR1_PID59 (0x1 << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ -#define PMC_PCDR1_PID60 (0x1 << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ -#define PMC_PCDR1_PID61 (0x1 << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */ -#define PMC_PCDR1_PID62 (0x1 << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */ -#define PMC_PCDR1_PID63 (0x1 << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */ -/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ -#define PMC_PCSR1_PID32 (0x1 << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ -#define PMC_PCSR1_PID33 (0x1 << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ -#define PMC_PCSR1_PID34 (0x1 << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ -#define PMC_PCSR1_PID35 (0x1 << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ -#define PMC_PCSR1_PID36 (0x1 << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */ -#define PMC_PCSR1_PID37 (0x1 << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ -#define PMC_PCSR1_PID38 (0x1 << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */ -#define PMC_PCSR1_PID39 (0x1 << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ -#define PMC_PCSR1_PID40 (0x1 << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ -#define PMC_PCSR1_PID41 (0x1 << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ -#define PMC_PCSR1_PID42 (0x1 << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ -#define PMC_PCSR1_PID43 (0x1 << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ -#define PMC_PCSR1_PID44 (0x1 << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ -#define PMC_PCSR1_PID45 (0x1 << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ -#define PMC_PCSR1_PID46 (0x1 << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ -#define PMC_PCSR1_PID47 (0x1 << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ -#define PMC_PCSR1_PID48 (0x1 << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ -#define PMC_PCSR1_PID49 (0x1 << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ -#define PMC_PCSR1_PID50 (0x1 << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ -#define PMC_PCSR1_PID51 (0x1 << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ -#define PMC_PCSR1_PID52 (0x1 << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ -#define PMC_PCSR1_PID53 (0x1 << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ -#define PMC_PCSR1_PID54 (0x1 << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */ -#define PMC_PCSR1_PID55 (0x1 << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */ -#define PMC_PCSR1_PID56 (0x1 << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ -#define PMC_PCSR1_PID57 (0x1 << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ -#define PMC_PCSR1_PID58 (0x1 << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ -#define PMC_PCSR1_PID59 (0x1 << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ -#define PMC_PCSR1_PID60 (0x1 << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ -#define PMC_PCSR1_PID61 (0x1 << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */ -#define PMC_PCSR1_PID62 (0x1 << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */ -#define PMC_PCSR1_PID63 (0x1 << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */ -/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ -#define PMC_OCR_CAL4 (0x7f << 0) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_SEL4 (0x1 << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_CAL8 (0x7f << 8) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_SEL8 (0x1 << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_CAL12 (0x7f << 16) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */ -#define PMC_OCR_SEL12 (0x1 << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PWM Pulse Width Modulation Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief PwmCh_num hardware registers */ -typedef struct { - RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ - RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ - RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ - RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ - RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ - RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ - RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ - RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ -} PwmCh_num; -/** \brief Pwm hardware registers */ -typedef struct { - RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ - WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ - WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ - RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ - WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ - WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ - RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ - RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ - RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ - RwReg Reserved1[1]; - RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ - RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ - WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ - WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ - WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ - RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ - RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ - RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ - RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ - WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ - WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ - WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ - WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ - RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ - RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ - WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ - RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */ - RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ - RwReg Reserved2[3]; - RwReg PWM_ELxMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ - RwReg Reserved3[11]; - RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ - RwReg Reserved4[12]; - WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ - RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ - RwReg Reserved5[5]; - RwReg PWM_RPR; /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */ - RwReg PWM_RCR; /**< \brief (Pwm Offset: 0x104) Receive Counter Register */ - RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */ - RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */ - RwReg PWM_RNPR; /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */ - RwReg PWM_RNCR; /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */ - RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */ - RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */ - WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */ - RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */ - RwReg Reserved6[2]; - RwReg PWM_CMP0V; /**< \brief (Pwm Offset: 0x130) PWM Comparison 0 Value Register */ - WoReg PWM_CMP0VUPD; /**< \brief (Pwm Offset: 0x134) PWM Comparison 0 Value Update Register */ - RwReg PWM_CMP0M; /**< \brief (Pwm Offset: 0x138) PWM Comparison 0 Mode Register */ - WoReg PWM_CMP0MUPD; /**< \brief (Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register */ - RwReg PWM_CMP1V; /**< \brief (Pwm Offset: 0x140) PWM Comparison 1 Value Register */ - WoReg PWM_CMP1VUPD; /**< \brief (Pwm Offset: 0x144) PWM Comparison 1 Value Update Register */ - RwReg PWM_CMP1M; /**< \brief (Pwm Offset: 0x148) PWM Comparison 1 Mode Register */ - WoReg PWM_CMP1MUPD; /**< \brief (Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register */ - RwReg PWM_CMP2V; /**< \brief (Pwm Offset: 0x150) PWM Comparison 2 Value Register */ - WoReg PWM_CMP2VUPD; /**< \brief (Pwm Offset: 0x154) PWM Comparison 2 Value Update Register */ - RwReg PWM_CMP2M; /**< \brief (Pwm Offset: 0x158) PWM Comparison 2 Mode Register */ - WoReg PWM_CMP2MUPD; /**< \brief (Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register */ - RwReg PWM_CMP3V; /**< \brief (Pwm Offset: 0x160) PWM Comparison 3 Value Register */ - WoReg PWM_CMP3VUPD; /**< \brief (Pwm Offset: 0x164) PWM Comparison 3 Value Update Register */ - RwReg PWM_CMP3M; /**< \brief (Pwm Offset: 0x168) PWM Comparison 3 Mode Register */ - WoReg PWM_CMP3MUPD; /**< \brief (Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register */ - RwReg PWM_CMP4V; /**< \brief (Pwm Offset: 0x170) PWM Comparison 4 Value Register */ - WoReg PWM_CMP4VUPD; /**< \brief (Pwm Offset: 0x174) PWM Comparison 4 Value Update Register */ - RwReg PWM_CMP4M; /**< \brief (Pwm Offset: 0x178) PWM Comparison 4 Mode Register */ - WoReg PWM_CMP4MUPD; /**< \brief (Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register */ - RwReg PWM_CMP5V; /**< \brief (Pwm Offset: 0x180) PWM Comparison 5 Value Register */ - WoReg PWM_CMP5VUPD; /**< \brief (Pwm Offset: 0x184) PWM Comparison 5 Value Update Register */ - RwReg PWM_CMP5M; /**< \brief (Pwm Offset: 0x188) PWM Comparison 5 Mode Register */ - WoReg PWM_CMP5MUPD; /**< \brief (Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register */ - RwReg PWM_CMP6V; /**< \brief (Pwm Offset: 0x190) PWM Comparison 6 Value Register */ - WoReg PWM_CMP6VUPD; /**< \brief (Pwm Offset: 0x194) PWM Comparison 6 Value Update Register */ - RwReg PWM_CMP6M; /**< \brief (Pwm Offset: 0x198) PWM Comparison 6 Mode Register */ - WoReg PWM_CMP6MUPD; /**< \brief (Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register */ - RwReg PWM_CMP7V; /**< \brief (Pwm Offset: 0x1A0) PWM Comparison 7 Value Register */ - WoReg PWM_CMP7VUPD; /**< \brief (Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register */ - RwReg PWM_CMP7M; /**< \brief (Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register */ - WoReg PWM_CMP7MUPD; /**< \brief (Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register */ - RwReg Reserved7[20]; - PwmCh_num PWM_CH_NUM[4]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ -} Pwm; -#endif /* __ASSEMBLY__ */ -/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ -#define PWM_CLK_DIVA (0xff << 0) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREA (0xf << 8) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -#define PWM_CLK_DIVB (0xff << 16) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREB (0xf << 24) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ -#define PWM_ENA_CHID0 (0x1 << 0) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID1 (0x1 << 1) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID2 (0x1 << 2) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID3 (0x1 << 3) /**< \brief (PWM_ENA) Channel ID */ -/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ -#define PWM_DIS_CHID0 (0x1 << 0) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID1 (0x1 << 1) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID2 (0x1 << 2) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID3 (0x1 << 3) /**< \brief (PWM_DIS) Channel ID */ -/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ -#define PWM_SR_CHID0 (0x1 << 0) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID1 (0x1 << 1) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID2 (0x1 << 2) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID3 (0x1 << 3) /**< \brief (PWM_SR) Channel ID */ -/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ -#define PWM_IER1_CHID0 (0x1 << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ -#define PWM_IER1_CHID1 (0x1 << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ -#define PWM_IER1_CHID2 (0x1 << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ -#define PWM_IER1_CHID3 (0x1 << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ -#define PWM_IER1_FCHID0 (0x1 << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ -#define PWM_IER1_FCHID1 (0x1 << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ -#define PWM_IER1_FCHID2 (0x1 << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ -#define PWM_IER1_FCHID3 (0x1 << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ -/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ -#define PWM_IDR1_CHID0 (0x1 << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ -#define PWM_IDR1_CHID1 (0x1 << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ -#define PWM_IDR1_CHID2 (0x1 << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ -#define PWM_IDR1_CHID3 (0x1 << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ -#define PWM_IDR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ -#define PWM_IDR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ -#define PWM_IDR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ -#define PWM_IDR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ -/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ -#define PWM_IMR1_CHID0 (0x1 << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ -#define PWM_IMR1_CHID1 (0x1 << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ -#define PWM_IMR1_CHID2 (0x1 << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ -#define PWM_IMR1_CHID3 (0x1 << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ -#define PWM_IMR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ -#define PWM_IMR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ -#define PWM_IMR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ -#define PWM_IMR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ -/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ -#define PWM_ISR1_CHID0 (0x1 << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ -#define PWM_ISR1_CHID1 (0x1 << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ -#define PWM_ISR1_CHID2 (0x1 << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ -#define PWM_ISR1_CHID3 (0x1 << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ -#define PWM_ISR1_FCHID0 (0x1 << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ -#define PWM_ISR1_FCHID1 (0x1 << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ -#define PWM_ISR1_FCHID2 (0x1 << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ -#define PWM_ISR1_FCHID3 (0x1 << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ -/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ -#define PWM_SCM_SYNC0 (0x1 << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ -#define PWM_SCM_SYNC1 (0x1 << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ -#define PWM_SCM_SYNC2 (0x1 << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ -#define PWM_SCM_SYNC3 (0x1 << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ -#define PWM_SCM_UPDM (0x3 << 16) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ -#define PWM_SCM_PTRM (0x1 << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */ -#define PWM_SCM_PTRCS (0x7 << 21) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */ -/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ -#define PWM_SCUC_UPDULOCK (0x1 << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ -/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ -#define PWM_SCUP_UPR (0xf << 0) /**< \brief (PWM_SCUP) Update Period */ -#define PWM_SCUP_UPRCNT (0xf << 4) /**< \brief (PWM_SCUP) Update Period Counter */ -/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ -#define PWM_SCUPUPD_UPRUPD (0xf << 0) /**< \brief (PWM_SCUPUPD) Update Period Update */ -/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ -#define PWM_IER2_WRDY (0x1 << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ -#define PWM_IER2_ENDTX (0x1 << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */ -#define PWM_IER2_TXBUFE (0x1 << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */ -#define PWM_IER2_UNRE (0x1 << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ -#define PWM_IER2_CMPM0 (0x1 << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ -#define PWM_IER2_CMPM1 (0x1 << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ -#define PWM_IER2_CMPM2 (0x1 << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ -#define PWM_IER2_CMPM3 (0x1 << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ -#define PWM_IER2_CMPM4 (0x1 << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ -#define PWM_IER2_CMPM5 (0x1 << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ -#define PWM_IER2_CMPM6 (0x1 << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ -#define PWM_IER2_CMPM7 (0x1 << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ -#define PWM_IER2_CMPU0 (0x1 << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ -#define PWM_IER2_CMPU1 (0x1 << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ -#define PWM_IER2_CMPU2 (0x1 << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ -#define PWM_IER2_CMPU3 (0x1 << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ -#define PWM_IER2_CMPU4 (0x1 << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ -#define PWM_IER2_CMPU5 (0x1 << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ -#define PWM_IER2_CMPU6 (0x1 << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ -#define PWM_IER2_CMPU7 (0x1 << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ -/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ -#define PWM_IDR2_WRDY (0x1 << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ -#define PWM_IDR2_ENDTX (0x1 << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */ -#define PWM_IDR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */ -#define PWM_IDR2_UNRE (0x1 << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ -#define PWM_IDR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ -#define PWM_IDR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ -#define PWM_IDR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ -#define PWM_IDR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ -#define PWM_IDR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ -#define PWM_IDR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ -#define PWM_IDR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ -#define PWM_IDR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ -#define PWM_IDR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ -#define PWM_IDR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ -#define PWM_IDR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ -#define PWM_IDR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ -#define PWM_IDR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ -#define PWM_IDR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ -#define PWM_IDR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ -#define PWM_IDR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ -/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ -#define PWM_IMR2_WRDY (0x1 << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ -#define PWM_IMR2_ENDTX (0x1 << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */ -#define PWM_IMR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */ -#define PWM_IMR2_UNRE (0x1 << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ -#define PWM_IMR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ -#define PWM_IMR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ -#define PWM_IMR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ -#define PWM_IMR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ -#define PWM_IMR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ -#define PWM_IMR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ -#define PWM_IMR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ -#define PWM_IMR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ -#define PWM_IMR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ -#define PWM_IMR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ -#define PWM_IMR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ -#define PWM_IMR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ -#define PWM_IMR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ -#define PWM_IMR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ -#define PWM_IMR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ -#define PWM_IMR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ -/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ -#define PWM_ISR2_WRDY (0x1 << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ -#define PWM_ISR2_ENDTX (0x1 << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */ -#define PWM_ISR2_TXBUFE (0x1 << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */ -#define PWM_ISR2_UNRE (0x1 << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ -#define PWM_ISR2_CMPM0 (0x1 << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ -#define PWM_ISR2_CMPM1 (0x1 << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ -#define PWM_ISR2_CMPM2 (0x1 << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ -#define PWM_ISR2_CMPM3 (0x1 << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ -#define PWM_ISR2_CMPM4 (0x1 << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ -#define PWM_ISR2_CMPM5 (0x1 << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ -#define PWM_ISR2_CMPM6 (0x1 << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ -#define PWM_ISR2_CMPM7 (0x1 << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ -#define PWM_ISR2_CMPU0 (0x1 << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ -#define PWM_ISR2_CMPU1 (0x1 << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ -#define PWM_ISR2_CMPU2 (0x1 << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ -#define PWM_ISR2_CMPU3 (0x1 << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ -#define PWM_ISR2_CMPU4 (0x1 << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ -#define PWM_ISR2_CMPU5 (0x1 << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ -#define PWM_ISR2_CMPU6 (0x1 << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ -#define PWM_ISR2_CMPU7 (0x1 << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ -/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ -#define PWM_OOV_OOVH0 (0x1 << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ -#define PWM_OOV_OOVH1 (0x1 << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ -#define PWM_OOV_OOVH2 (0x1 << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ -#define PWM_OOV_OOVH3 (0x1 << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ -#define PWM_OOV_OOVL0 (0x1 << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ -#define PWM_OOV_OOVL1 (0x1 << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ -#define PWM_OOV_OOVL2 (0x1 << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ -#define PWM_OOV_OOVL3 (0x1 << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ -/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ -#define PWM_OS_OSH0 (0x1 << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ -#define PWM_OS_OSH1 (0x1 << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ -#define PWM_OS_OSH2 (0x1 << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ -#define PWM_OS_OSH3 (0x1 << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ -#define PWM_OS_OSL0 (0x1 << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ -#define PWM_OS_OSL1 (0x1 << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ -#define PWM_OS_OSL2 (0x1 << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ -#define PWM_OS_OSL3 (0x1 << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ -/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ -#define PWM_OSS_OSSH0 (0x1 << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSS_OSSH1 (0x1 << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSS_OSSH2 (0x1 << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSS_OSSH3 (0x1 << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSS_OSSL0 (0x1 << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSS_OSSL1 (0x1 << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSS_OSSL2 (0x1 << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSS_OSSL3 (0x1 << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ -#define PWM_OSC_OSCH0 (0x1 << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSC_OSCH1 (0x1 << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSC_OSCH2 (0x1 << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSC_OSCH3 (0x1 << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSC_OSCL0 (0x1 << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSC_OSCL1 (0x1 << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSC_OSCL2 (0x1 << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSC_OSCL3 (0x1 << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ -#define PWM_OSSUPD_OSSUPH0 (0x1 << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSSUPD_OSSUPH1 (0x1 << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSSUPD_OSSUPH2 (0x1 << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSSUPD_OSSUPH3 (0x1 << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSSUPD_OSSUPL0 (0x1 << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSSUPD_OSSUPL1 (0x1 << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSSUPD_OSSUPL2 (0x1 << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSSUPD_OSSUPL3 (0x1 << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ -#define PWM_OSCUPD_OSCUPH0 (0x1 << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSCUPD_OSCUPH1 (0x1 << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSCUPD_OSCUPH2 (0x1 << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSCUPD_OSCUPH3 (0x1 << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSCUPD_OSCUPL0 (0x1 << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSCUPD_OSCUPL1 (0x1 << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSCUPD_OSCUPL2 (0x1 << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSCUPD_OSCUPL3 (0x1 << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ -#define PWM_FMR_FPOL0 (0x1 << 0) /**< \brief (PWM_FMR) Fault 0 Polarity */ -#define PWM_FMR_FPOL1 (0x1 << 1) /**< \brief (PWM_FMR) Fault 1 Polarity */ -#define PWM_FMR_FPOL2 (0x1 << 2) /**< \brief (PWM_FMR) Fault 2 Polarity */ -#define PWM_FMR_FPOL3 (0x1 << 3) /**< \brief (PWM_FMR) Fault 3 Polarity */ -#define PWM_FMR_FMOD0 (0x1 << 8) /**< \brief (PWM_FMR) Fault 0 Activation Mode */ -#define PWM_FMR_FMOD1 (0x1 << 9) /**< \brief (PWM_FMR) Fault 1 Activation Mode */ -#define PWM_FMR_FMOD2 (0x1 << 10) /**< \brief (PWM_FMR) Fault 2 Activation Mode */ -#define PWM_FMR_FMOD3 (0x1 << 11) /**< \brief (PWM_FMR) Fault 3 Activation Mode */ -#define PWM_FMR_FFIL0 (0x1 << 16) /**< \brief (PWM_FMR) Fault 0 Filtering */ -#define PWM_FMR_FFIL1 (0x1 << 17) /**< \brief (PWM_FMR) Fault 1 Filtering */ -#define PWM_FMR_FFIL2 (0x1 << 18) /**< \brief (PWM_FMR) Fault 2 Filtering */ -#define PWM_FMR_FFIL3 (0x1 << 19) /**< \brief (PWM_FMR) Fault 3 Filtering */ -/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ -#define PWM_FSR_FIV0 (0x1 << 0) /**< \brief (PWM_FSR) Fault Input 0 Value */ -#define PWM_FSR_FIV1 (0x1 << 1) /**< \brief (PWM_FSR) Fault Input 1 Value */ -#define PWM_FSR_FIV2 (0x1 << 2) /**< \brief (PWM_FSR) Fault Input 2 Value */ -#define PWM_FSR_FIV3 (0x1 << 3) /**< \brief (PWM_FSR) Fault Input 3 Value */ -#define PWM_FSR_FS0 (0x1 << 8) /**< \brief (PWM_FSR) Fault 0 Status */ -#define PWM_FSR_FS1 (0x1 << 9) /**< \brief (PWM_FSR) Fault 1 Status */ -#define PWM_FSR_FS2 (0x1 << 10) /**< \brief (PWM_FSR) Fault 2 Status */ -#define PWM_FSR_FS3 (0x1 << 11) /**< \brief (PWM_FSR) Fault 3 Status */ -/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ -#define PWM_FCR_FCLR0 (0x1 << 0) /**< \brief (PWM_FCR) Fault 0 Clear */ -#define PWM_FCR_FCLR1 (0x1 << 1) /**< \brief (PWM_FCR) Fault 1 Clear */ -#define PWM_FCR_FCLR2 (0x1 << 2) /**< \brief (PWM_FCR) Fault 2 Clear */ -#define PWM_FCR_FCLR3 (0x1 << 3) /**< \brief (PWM_FCR) Fault 3 Clear */ -/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */ -#define PWM_FPV_FPVH0 (0x1 << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */ -#define PWM_FPV_FPVH1 (0x1 << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */ -#define PWM_FPV_FPVH2 (0x1 << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */ -#define PWM_FPV_FPVH3 (0x1 << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */ -#define PWM_FPV_FPVL0 (0x1 << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */ -#define PWM_FPV_FPVL1 (0x1 << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */ -#define PWM_FPV_FPVL2 (0x1 << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */ -#define PWM_FPV_FPVL3 (0x1 << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */ -/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ -#define PWM_FPE_FPE0 (0xff << 0) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 0 for channel x */ -#define PWM_FPE_FPE1 (0xff << 8) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 1 for channel x */ -#define PWM_FPE_FPE2 (0xff << 16) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 2 for channel x */ -#define PWM_FPE_FPE3 (0xff << 24) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 3 for channel x */ -/* -------- PWM_ELxMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ -#define PWM_ELxMR_CSEL0 (0x1 << 0) /**< \brief (PWM_ELxMR[2]) Comparison 0 Selection */ -#define PWM_ELxMR_CSEL1 (0x1 << 1) /**< \brief (PWM_ELxMR[2]) Comparison 1 Selection */ -#define PWM_ELxMR_CSEL2 (0x1 << 2) /**< \brief (PWM_ELxMR[2]) Comparison 2 Selection */ -#define PWM_ELxMR_CSEL3 (0x1 << 3) /**< \brief (PWM_ELxMR[2]) Comparison 3 Selection */ -#define PWM_ELxMR_CSEL4 (0x1 << 4) /**< \brief (PWM_ELxMR[2]) Comparison 4 Selection */ -#define PWM_ELxMR_CSEL5 (0x1 << 5) /**< \brief (PWM_ELxMR[2]) Comparison 5 Selection */ -#define PWM_ELxMR_CSEL6 (0x1 << 6) /**< \brief (PWM_ELxMR[2]) Comparison 6 Selection */ -#define PWM_ELxMR_CSEL7 (0x1 << 7) /**< \brief (PWM_ELxMR[2]) Comparison 7 Selection */ -/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ -#define PWM_SMMR_GCEN0 (0x1 << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ -#define PWM_SMMR_GCEN1 (0x1 << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ -#define PWM_SMMR_DOWN0 (0x1 << 16) /**< \brief (PWM_SMMR) DOWN Count */ -#define PWM_SMMR_DOWN1 (0x1 << 17) /**< \brief (PWM_SMMR) DOWN Count */ -/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ -#define PWM_WPCR_WPCMD (0x3 << 0) /**< \brief (PWM_WPCR) Write Protect Command */ -#define PWM_WPCR_WPRG0 (0x1 << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ -#define PWM_WPCR_WPRG1 (0x1 << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ -#define PWM_WPCR_WPRG2 (0x1 << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ -#define PWM_WPCR_WPRG3 (0x1 << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ -#define PWM_WPCR_WPRG4 (0x1 << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ -#define PWM_WPCR_WPRG5 (0x1 << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ -#define PWM_WPCR_WPKEY (0xffffff << 8) /**< \brief (PWM_WPCR) Write Protect Key */ -/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ -#define PWM_WPSR_WPSWS0 (0x1 << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS1 (0x1 << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS2 (0x1 << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS3 (0x1 << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS4 (0x1 << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS5 (0x1 << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPVS (0x1 << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ -#define PWM_WPSR_WPHWS0 (0x1 << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS1 (0x1 << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS2 (0x1 << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS3 (0x1 << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS4 (0x1 << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS5 (0x1 << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPVSRC (0xffff << 16) /**< \brief (PWM_WPSR) Write Protect Violation Source */ -/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */ -#define PWM_RPR_RXPTR (0xffffffff << 0) /**< \brief (PWM_RPR) Receive Pointer Register */ -/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */ -#define PWM_RCR_RXCTR (0xffff << 0) /**< \brief (PWM_RCR) Receive Counter Register */ -/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */ -#define PWM_TPR_TXPTR (0xffffffff << 0) /**< \brief (PWM_TPR) Transmit Counter Register */ -/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */ -#define PWM_TCR_TXCTR (0xffff << 0) /**< \brief (PWM_TCR) Transmit Counter Register */ -/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */ -#define PWM_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PWM_RNPR) Receive Next Pointer */ -/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */ -#define PWM_RNCR_RXNCTR (0xffff << 0) /**< \brief (PWM_RNCR) Receive Next Counter */ -/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PWM_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PWM_TNPR) Transmit Next Pointer */ -/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PWM_TNCR_TXNCTR (0xffff << 0) /**< \brief (PWM_TNCR) Transmit Counter Next */ -/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */ -#define PWM_PTCR_RXTEN (0x1 << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */ -#define PWM_PTCR_RXTDIS (0x1 << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */ -#define PWM_PTCR_TXTEN (0x1 << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */ -#define PWM_PTCR_TXTDIS (0x1 << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */ -/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */ -#define PWM_PTSR_RXTEN (0x1 << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */ -#define PWM_PTSR_TXTEN (0x1 << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */ -/* -------- PWM_CMP0V : (PWM Offset: 0x130) PWM Comparison 0 Value Register -------- */ -#define PWM_CMP0V_CV (0xffffff << 0) /**< \brief (PWM_CMP0V) Comparison x Value */ -#define PWM_CMP0V_CVM (0x1 << 24) /**< \brief (PWM_CMP0V) Comparison x Value Mode */ -/* -------- PWM_CMP0VUPD : (PWM Offset: 0x134) PWM Comparison 0 Value Update Register -------- */ -#define PWM_CMP0VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP0VUPD) Comparison x Value Update */ -#define PWM_CMP0VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP0VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP0M : (PWM Offset: 0x138) PWM Comparison 0 Mode Register -------- */ -#define PWM_CMP0M_CEN (0x1 << 0) /**< \brief (PWM_CMP0M) Comparison x Enable */ -#define PWM_CMP0M_CTR (0xf << 4) /**< \brief (PWM_CMP0M) Comparison x Trigger */ -#define PWM_CMP0M_CPR (0xf << 8) /**< \brief (PWM_CMP0M) Comparison x Period */ -#define PWM_CMP0M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP0M) Comparison x Period Counter */ -#define PWM_CMP0M_CUPR (0xf << 16) /**< \brief (PWM_CMP0M) Comparison x Update Period */ -#define PWM_CMP0M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP0M) Comparison x Update Period Counter */ -/* -------- PWM_CMP0MUPD : (PWM Offset: 0x13C) PWM Comparison 0 Mode Update Register -------- */ -#define PWM_CMP0MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP0MUPD) Comparison x Enable Update */ -#define PWM_CMP0MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP0MUPD) Comparison x Trigger Update */ -#define PWM_CMP0MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP0MUPD) Comparison x Period Update */ -#define PWM_CMP0MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP0MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP1V : (PWM Offset: 0x140) PWM Comparison 1 Value Register -------- */ -#define PWM_CMP1V_CV (0xffffff << 0) /**< \brief (PWM_CMP1V) Comparison x Value */ -#define PWM_CMP1V_CVM (0x1 << 24) /**< \brief (PWM_CMP1V) Comparison x Value Mode */ -/* -------- PWM_CMP1VUPD : (PWM Offset: 0x144) PWM Comparison 1 Value Update Register -------- */ -#define PWM_CMP1VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP1VUPD) Comparison x Value Update */ -#define PWM_CMP1VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP1VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP1M : (PWM Offset: 0x148) PWM Comparison 1 Mode Register -------- */ -#define PWM_CMP1M_CEN (0x1 << 0) /**< \brief (PWM_CMP1M) Comparison x Enable */ -#define PWM_CMP1M_CTR (0xf << 4) /**< \brief (PWM_CMP1M) Comparison x Trigger */ -#define PWM_CMP1M_CPR (0xf << 8) /**< \brief (PWM_CMP1M) Comparison x Period */ -#define PWM_CMP1M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP1M) Comparison x Period Counter */ -#define PWM_CMP1M_CUPR (0xf << 16) /**< \brief (PWM_CMP1M) Comparison x Update Period */ -#define PWM_CMP1M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP1M) Comparison x Update Period Counter */ -/* -------- PWM_CMP1MUPD : (PWM Offset: 0x14C) PWM Comparison 1 Mode Update Register -------- */ -#define PWM_CMP1MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP1MUPD) Comparison x Enable Update */ -#define PWM_CMP1MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP1MUPD) Comparison x Trigger Update */ -#define PWM_CMP1MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP1MUPD) Comparison x Period Update */ -#define PWM_CMP1MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP1MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP2V : (PWM Offset: 0x150) PWM Comparison 2 Value Register -------- */ -#define PWM_CMP2V_CV (0xffffff << 0) /**< \brief (PWM_CMP2V) Comparison x Value */ -#define PWM_CMP2V_CVM (0x1 << 24) /**< \brief (PWM_CMP2V) Comparison x Value Mode */ -/* -------- PWM_CMP2VUPD : (PWM Offset: 0x154) PWM Comparison 2 Value Update Register -------- */ -#define PWM_CMP2VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP2VUPD) Comparison x Value Update */ -#define PWM_CMP2VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP2VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP2M : (PWM Offset: 0x158) PWM Comparison 2 Mode Register -------- */ -#define PWM_CMP2M_CEN (0x1 << 0) /**< \brief (PWM_CMP2M) Comparison x Enable */ -#define PWM_CMP2M_CTR (0xf << 4) /**< \brief (PWM_CMP2M) Comparison x Trigger */ -#define PWM_CMP2M_CPR (0xf << 8) /**< \brief (PWM_CMP2M) Comparison x Period */ -#define PWM_CMP2M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP2M) Comparison x Period Counter */ -#define PWM_CMP2M_CUPR (0xf << 16) /**< \brief (PWM_CMP2M) Comparison x Update Period */ -#define PWM_CMP2M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP2M) Comparison x Update Period Counter */ -/* -------- PWM_CMP2MUPD : (PWM Offset: 0x15C) PWM Comparison 2 Mode Update Register -------- */ -#define PWM_CMP2MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP2MUPD) Comparison x Enable Update */ -#define PWM_CMP2MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP2MUPD) Comparison x Trigger Update */ -#define PWM_CMP2MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP2MUPD) Comparison x Period Update */ -#define PWM_CMP2MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP2MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP3V : (PWM Offset: 0x160) PWM Comparison 3 Value Register -------- */ -#define PWM_CMP3V_CV (0xffffff << 0) /**< \brief (PWM_CMP3V) Comparison x Value */ -#define PWM_CMP3V_CVM (0x1 << 24) /**< \brief (PWM_CMP3V) Comparison x Value Mode */ -/* -------- PWM_CMP3VUPD : (PWM Offset: 0x164) PWM Comparison 3 Value Update Register -------- */ -#define PWM_CMP3VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP3VUPD) Comparison x Value Update */ -#define PWM_CMP3VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP3VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP3M : (PWM Offset: 0x168) PWM Comparison 3 Mode Register -------- */ -#define PWM_CMP3M_CEN (0x1 << 0) /**< \brief (PWM_CMP3M) Comparison x Enable */ -#define PWM_CMP3M_CTR (0xf << 4) /**< \brief (PWM_CMP3M) Comparison x Trigger */ -#define PWM_CMP3M_CPR (0xf << 8) /**< \brief (PWM_CMP3M) Comparison x Period */ -#define PWM_CMP3M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP3M) Comparison x Period Counter */ -#define PWM_CMP3M_CUPR (0xf << 16) /**< \brief (PWM_CMP3M) Comparison x Update Period */ -#define PWM_CMP3M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP3M) Comparison x Update Period Counter */ -/* -------- PWM_CMP3MUPD : (PWM Offset: 0x16C) PWM Comparison 3 Mode Update Register -------- */ -#define PWM_CMP3MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP3MUPD) Comparison x Enable Update */ -#define PWM_CMP3MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP3MUPD) Comparison x Trigger Update */ -#define PWM_CMP3MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP3MUPD) Comparison x Period Update */ -#define PWM_CMP3MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP3MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP4V : (PWM Offset: 0x170) PWM Comparison 4 Value Register -------- */ -#define PWM_CMP4V_CV (0xffffff << 0) /**< \brief (PWM_CMP4V) Comparison x Value */ -#define PWM_CMP4V_CVM (0x1 << 24) /**< \brief (PWM_CMP4V) Comparison x Value Mode */ -/* -------- PWM_CMP4VUPD : (PWM Offset: 0x174) PWM Comparison 4 Value Update Register -------- */ -#define PWM_CMP4VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP4VUPD) Comparison x Value Update */ -#define PWM_CMP4VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP4VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP4M : (PWM Offset: 0x178) PWM Comparison 4 Mode Register -------- */ -#define PWM_CMP4M_CEN (0x1 << 0) /**< \brief (PWM_CMP4M) Comparison x Enable */ -#define PWM_CMP4M_CTR (0xf << 4) /**< \brief (PWM_CMP4M) Comparison x Trigger */ -#define PWM_CMP4M_CPR (0xf << 8) /**< \brief (PWM_CMP4M) Comparison x Period */ -#define PWM_CMP4M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP4M) Comparison x Period Counter */ -#define PWM_CMP4M_CUPR (0xf << 16) /**< \brief (PWM_CMP4M) Comparison x Update Period */ -#define PWM_CMP4M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP4M) Comparison x Update Period Counter */ -/* -------- PWM_CMP4MUPD : (PWM Offset: 0x17C) PWM Comparison 4 Mode Update Register -------- */ -#define PWM_CMP4MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP4MUPD) Comparison x Enable Update */ -#define PWM_CMP4MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP4MUPD) Comparison x Trigger Update */ -#define PWM_CMP4MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP4MUPD) Comparison x Period Update */ -#define PWM_CMP4MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP4MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP5V : (PWM Offset: 0x180) PWM Comparison 5 Value Register -------- */ -#define PWM_CMP5V_CV (0xffffff << 0) /**< \brief (PWM_CMP5V) Comparison x Value */ -#define PWM_CMP5V_CVM (0x1 << 24) /**< \brief (PWM_CMP5V) Comparison x Value Mode */ -/* -------- PWM_CMP5VUPD : (PWM Offset: 0x184) PWM Comparison 5 Value Update Register -------- */ -#define PWM_CMP5VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP5VUPD) Comparison x Value Update */ -#define PWM_CMP5VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP5VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP5M : (PWM Offset: 0x188) PWM Comparison 5 Mode Register -------- */ -#define PWM_CMP5M_CEN (0x1 << 0) /**< \brief (PWM_CMP5M) Comparison x Enable */ -#define PWM_CMP5M_CTR (0xf << 4) /**< \brief (PWM_CMP5M) Comparison x Trigger */ -#define PWM_CMP5M_CPR (0xf << 8) /**< \brief (PWM_CMP5M) Comparison x Period */ -#define PWM_CMP5M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP5M) Comparison x Period Counter */ -#define PWM_CMP5M_CUPR (0xf << 16) /**< \brief (PWM_CMP5M) Comparison x Update Period */ -#define PWM_CMP5M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP5M) Comparison x Update Period Counter */ -/* -------- PWM_CMP5MUPD : (PWM Offset: 0x18C) PWM Comparison 5 Mode Update Register -------- */ -#define PWM_CMP5MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP5MUPD) Comparison x Enable Update */ -#define PWM_CMP5MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP5MUPD) Comparison x Trigger Update */ -#define PWM_CMP5MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP5MUPD) Comparison x Period Update */ -#define PWM_CMP5MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP5MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP6V : (PWM Offset: 0x190) PWM Comparison 6 Value Register -------- */ -#define PWM_CMP6V_CV (0xffffff << 0) /**< \brief (PWM_CMP6V) Comparison x Value */ -#define PWM_CMP6V_CVM (0x1 << 24) /**< \brief (PWM_CMP6V) Comparison x Value Mode */ -/* -------- PWM_CMP6VUPD : (PWM Offset: 0x194) PWM Comparison 6 Value Update Register -------- */ -#define PWM_CMP6VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP6VUPD) Comparison x Value Update */ -#define PWM_CMP6VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP6VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP6M : (PWM Offset: 0x198) PWM Comparison 6 Mode Register -------- */ -#define PWM_CMP6M_CEN (0x1 << 0) /**< \brief (PWM_CMP6M) Comparison x Enable */ -#define PWM_CMP6M_CTR (0xf << 4) /**< \brief (PWM_CMP6M) Comparison x Trigger */ -#define PWM_CMP6M_CPR (0xf << 8) /**< \brief (PWM_CMP6M) Comparison x Period */ -#define PWM_CMP6M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP6M) Comparison x Period Counter */ -#define PWM_CMP6M_CUPR (0xf << 16) /**< \brief (PWM_CMP6M) Comparison x Update Period */ -#define PWM_CMP6M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP6M) Comparison x Update Period Counter */ -/* -------- PWM_CMP6MUPD : (PWM Offset: 0x19C) PWM Comparison 6 Mode Update Register -------- */ -#define PWM_CMP6MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP6MUPD) Comparison x Enable Update */ -#define PWM_CMP6MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP6MUPD) Comparison x Trigger Update */ -#define PWM_CMP6MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP6MUPD) Comparison x Period Update */ -#define PWM_CMP6MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP6MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP7V : (PWM Offset: 0x1A0) PWM Comparison 7 Value Register -------- */ -#define PWM_CMP7V_CV (0xffffff << 0) /**< \brief (PWM_CMP7V) Comparison x Value */ -#define PWM_CMP7V_CVM (0x1 << 24) /**< \brief (PWM_CMP7V) Comparison x Value Mode */ -/* -------- PWM_CMP7VUPD : (PWM Offset: 0x1A4) PWM Comparison 7 Value Update Register -------- */ -#define PWM_CMP7VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP7VUPD) Comparison x Value Update */ -#define PWM_CMP7VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP7VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP7M : (PWM Offset: 0x1A8) PWM Comparison 7 Mode Register -------- */ -#define PWM_CMP7M_CEN (0x1 << 0) /**< \brief (PWM_CMP7M) Comparison x Enable */ -#define PWM_CMP7M_CTR (0xf << 4) /**< \brief (PWM_CMP7M) Comparison x Trigger */ -#define PWM_CMP7M_CPR (0xf << 8) /**< \brief (PWM_CMP7M) Comparison x Period */ -#define PWM_CMP7M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP7M) Comparison x Period Counter */ -#define PWM_CMP7M_CUPR (0xf << 16) /**< \brief (PWM_CMP7M) Comparison x Update Period */ -#define PWM_CMP7M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP7M) Comparison x Update Period Counter */ -/* -------- PWM_CMP7MUPD : (PWM Offset: 0x1AC) PWM Comparison 7 Mode Update Register -------- */ -#define PWM_CMP7MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP7MUPD) Comparison x Enable Update */ -#define PWM_CMP7MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP7MUPD) Comparison x Trigger Update */ -#define PWM_CMP7MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP7MUPD) Comparison x Period Update */ -#define PWM_CMP7MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP7MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMR0 : (PWM Offset: 0x200) PWM Channel Mode Register (ch_num = 0) -------- */ -#define PWM_CMR0_CPRE (0xf << 0) /**< \brief (PWM_CMR0) Channel Pre-scaler */ -#define PWM_CMR0_CALG (0x1 << 8) /**< \brief (PWM_CMR0) Channel Alignment */ -#define PWM_CMR0_CPOL (0x1 << 9) /**< \brief (PWM_CMR0) Channel Polarity */ -#define PWM_CMR0_CES (0x1 << 10) /**< \brief (PWM_CMR0) Counter Event Selection */ -#define PWM_CMR0_DTE (0x1 << 16) /**< \brief (PWM_CMR0) Dead-Time Generator Enable */ -#define PWM_CMR0_DTHI (0x1 << 17) /**< \brief (PWM_CMR0) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR0_DTLI (0x1 << 18) /**< \brief (PWM_CMR0) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY0 : (PWM Offset: 0x204) PWM Channel Duty Cycle Register (ch_num = 0) -------- */ -#define PWM_CDTY0_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY0) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD0 : (PWM Offset: 0x208) PWM Channel Duty Cycle Update Register (ch_num = 0) -------- */ -#define PWM_CDTYUPD0_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD0) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD0 : (PWM Offset: 0x20C) PWM Channel Period Register (ch_num = 0) -------- */ -#define PWM_CPRD0_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD0) Channel Period */ -/* -------- PWM_CPRDUPD0 : (PWM Offset: 0x210) PWM Channel Period Update Register (ch_num = 0) -------- */ -#define PWM_CPRDUPD0_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD0) Channel Period Update */ -/* -------- PWM_CCNT0 : (PWM Offset: 0x214) PWM Channel Counter Register (ch_num = 0) -------- */ -#define PWM_CCNT0_CNT (0xffffff << 0) /**< \brief (PWM_CCNT0) Channel Counter Register */ -/* -------- PWM_DT0 : (PWM Offset: 0x218) PWM Channel Dead Time Register (ch_num = 0) -------- */ -#define PWM_DT0_DTH (0xffff << 0) /**< \brief (PWM_DT0) Dead-Time Value for PWMHx Output */ -#define PWM_DT0_DTL (0xffff << 16) /**< \brief (PWM_DT0) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD0 : (PWM Offset: 0x21C) PWM Channel Dead Time Update Register (ch_num = 0) -------- */ -#define PWM_DTUPD0_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD0_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR1 : (PWM Offset: 0x220) PWM Channel Mode Register (ch_num = 1) -------- */ -#define PWM_CMR1_CPRE (0xf << 0) /**< \brief (PWM_CMR1) Channel Pre-scaler */ -#define PWM_CMR1_CALG (0x1 << 8) /**< \brief (PWM_CMR1) Channel Alignment */ -#define PWM_CMR1_CPOL (0x1 << 9) /**< \brief (PWM_CMR1) Channel Polarity */ -#define PWM_CMR1_CES (0x1 << 10) /**< \brief (PWM_CMR1) Counter Event Selection */ -#define PWM_CMR1_DTE (0x1 << 16) /**< \brief (PWM_CMR1) Dead-Time Generator Enable */ -#define PWM_CMR1_DTHI (0x1 << 17) /**< \brief (PWM_CMR1) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR1_DTLI (0x1 << 18) /**< \brief (PWM_CMR1) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY1 : (PWM Offset: 0x224) PWM Channel Duty Cycle Register (ch_num = 1) -------- */ -#define PWM_CDTY1_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY1) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD1 : (PWM Offset: 0x228) PWM Channel Duty Cycle Update Register (ch_num = 1) -------- */ -#define PWM_CDTYUPD1_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD1) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD1 : (PWM Offset: 0x22C) PWM Channel Period Register (ch_num = 1) -------- */ -#define PWM_CPRD1_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD1) Channel Period */ -/* -------- PWM_CPRDUPD1 : (PWM Offset: 0x230) PWM Channel Period Update Register (ch_num = 1) -------- */ -#define PWM_CPRDUPD1_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD1) Channel Period Update */ -/* -------- PWM_CCNT1 : (PWM Offset: 0x234) PWM Channel Counter Register (ch_num = 1) -------- */ -#define PWM_CCNT1_CNT (0xffffff << 0) /**< \brief (PWM_CCNT1) Channel Counter Register */ -/* -------- PWM_DT1 : (PWM Offset: 0x238) PWM Channel Dead Time Register (ch_num = 1) -------- */ -#define PWM_DT1_DTH (0xffff << 0) /**< \brief (PWM_DT1) Dead-Time Value for PWMHx Output */ -#define PWM_DT1_DTL (0xffff << 16) /**< \brief (PWM_DT1) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD1 : (PWM Offset: 0x23C) PWM Channel Dead Time Update Register (ch_num = 1) -------- */ -#define PWM_DTUPD1_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD1_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR2 : (PWM Offset: 0x240) PWM Channel Mode Register (ch_num = 2) -------- */ -#define PWM_CMR2_CPRE (0xf << 0) /**< \brief (PWM_CMR2) Channel Pre-scaler */ -#define PWM_CMR2_CALG (0x1 << 8) /**< \brief (PWM_CMR2) Channel Alignment */ -#define PWM_CMR2_CPOL (0x1 << 9) /**< \brief (PWM_CMR2) Channel Polarity */ -#define PWM_CMR2_CES (0x1 << 10) /**< \brief (PWM_CMR2) Counter Event Selection */ -#define PWM_CMR2_DTE (0x1 << 16) /**< \brief (PWM_CMR2) Dead-Time Generator Enable */ -#define PWM_CMR2_DTHI (0x1 << 17) /**< \brief (PWM_CMR2) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR2_DTLI (0x1 << 18) /**< \brief (PWM_CMR2) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY2 : (PWM Offset: 0x244) PWM Channel Duty Cycle Register (ch_num = 2) -------- */ -#define PWM_CDTY2_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY2) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD2 : (PWM Offset: 0x248) PWM Channel Duty Cycle Update Register (ch_num = 2) -------- */ -#define PWM_CDTYUPD2_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD2) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD2 : (PWM Offset: 0x24C) PWM Channel Period Register (ch_num = 2) -------- */ -#define PWM_CPRD2_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD2) Channel Period */ -/* -------- PWM_CPRDUPD2 : (PWM Offset: 0x250) PWM Channel Period Update Register (ch_num = 2) -------- */ -#define PWM_CPRDUPD2_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD2) Channel Period Update */ -/* -------- PWM_CCNT2 : (PWM Offset: 0x254) PWM Channel Counter Register (ch_num = 2) -------- */ -#define PWM_CCNT2_CNT (0xffffff << 0) /**< \brief (PWM_CCNT2) Channel Counter Register */ -/* -------- PWM_DT2 : (PWM Offset: 0x258) PWM Channel Dead Time Register (ch_num = 2) -------- */ -#define PWM_DT2_DTH (0xffff << 0) /**< \brief (PWM_DT2) Dead-Time Value for PWMHx Output */ -#define PWM_DT2_DTL (0xffff << 16) /**< \brief (PWM_DT2) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD2 : (PWM Offset: 0x25C) PWM Channel Dead Time Update Register (ch_num = 2) -------- */ -#define PWM_DTUPD2_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD2_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR3 : (PWM Offset: 0x260) PWM Channel Mode Register (ch_num = 3) -------- */ -#define PWM_CMR3_CPRE (0xf << 0) /**< \brief (PWM_CMR3) Channel Pre-scaler */ -#define PWM_CMR3_CALG (0x1 << 8) /**< \brief (PWM_CMR3) Channel Alignment */ -#define PWM_CMR3_CPOL (0x1 << 9) /**< \brief (PWM_CMR3) Channel Polarity */ -#define PWM_CMR3_CES (0x1 << 10) /**< \brief (PWM_CMR3) Counter Event Selection */ -#define PWM_CMR3_DTE (0x1 << 16) /**< \brief (PWM_CMR3) Dead-Time Generator Enable */ -#define PWM_CMR3_DTHI (0x1 << 17) /**< \brief (PWM_CMR3) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR3_DTLI (0x1 << 18) /**< \brief (PWM_CMR3) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY3 : (PWM Offset: 0x264) PWM Channel Duty Cycle Register (ch_num = 3) -------- */ -#define PWM_CDTY3_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY3) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD3 : (PWM Offset: 0x268) PWM Channel Duty Cycle Update Register (ch_num = 3) -------- */ -#define PWM_CDTYUPD3_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD3) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD3 : (PWM Offset: 0x26C) PWM Channel Period Register (ch_num = 3) -------- */ -#define PWM_CPRD3_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD3) Channel Period */ -/* -------- PWM_CPRDUPD3 : (PWM Offset: 0x270) PWM Channel Period Update Register (ch_num = 3) -------- */ -#define PWM_CPRDUPD3_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD3) Channel Period Update */ -/* -------- PWM_CCNT3 : (PWM Offset: 0x274) PWM Channel Counter Register (ch_num = 3) -------- */ -#define PWM_CCNT3_CNT (0xffffff << 0) /**< \brief (PWM_CCNT3) Channel Counter Register */ -/* -------- PWM_DT3 : (PWM Offset: 0x278) PWM Channel Dead Time Register (ch_num = 3) -------- */ -#define PWM_DT3_DTH (0xffff << 0) /**< \brief (PWM_DT3) Dead-Time Value for PWMHx Output */ -#define PWM_DT3_DTL (0xffff << 16) /**< \brief (PWM_DT3) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD3 : (PWM Offset: 0x27C) PWM Channel Dead Time Update Register (ch_num = 3) -------- */ -#define PWM_DTUPD3_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD3_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMLx Output */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Reset Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RSTC Reset Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rstc hardware registers */ -typedef struct { - WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ - RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ - RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ -} Rstc; -#endif /* __ASSEMBLY__ */ -/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ -#define RSTC_CR_PROCRST (0x1 << 0) /**< \brief (RSTC_CR) Processor Reset */ -#define RSTC_CR_PERRST (0x1 << 2) /**< \brief (RSTC_CR) Peripheral Reset */ -#define RSTC_CR_EXTRST (0x1 << 3) /**< \brief (RSTC_CR) External Reset */ -#define RSTC_CR_KEY (0xff << 24) /**< \brief (RSTC_CR) Password */ -/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ -#define RSTC_SR_URSTS (0x1 << 0) /**< \brief (RSTC_SR) User Reset Status */ -#define RSTC_SR_RSTTYP (0x7 << 8) /**< \brief (RSTC_SR) Reset Type */ -#define RSTC_SR_NRSTL (0x1 << 16) /**< \brief (RSTC_SR) NRST Pin Level */ -#define RSTC_SR_SRCMP (0x1 << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ -/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ -#define RSTC_MR_URSTEN (0x1 << 0) /**< \brief (RSTC_MR) User Reset Enable */ -#define RSTC_MR_URSTIEN (0x1 << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ -#define RSTC_MR_ERSTL (0xf << 8) /**< \brief (RSTC_MR) External Reset Length */ -#define RSTC_MR_KEY (0xff << 24) /**< \brief (RSTC_MR) Password */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Clock */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RTC Real-time Clock */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtc hardware registers */ -typedef struct { - RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ - RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ - RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ - RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ - RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ - RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ - RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ - WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ - WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ - WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ - RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ - RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ -} Rtc; -#endif /* __ASSEMBLY__ */ -/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ -#define RTC_CR_UPDTIM (0x1 << 0) /**< \brief (RTC_CR) Update Request Time Register */ -#define RTC_CR_UPDCAL (0x1 << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ -#define RTC_CR_TIMEVSEL (0x3 << 8) /**< \brief (RTC_CR) Time Event Selection */ -#define RTC_CR_TIMEVSEL_MINUTE (0x0 << 8) /**< \brief (RTC_CR) Minute change. */ -#define RTC_CR_TIMEVSEL_HOUR (0x1 << 8) /**< \brief (RTC_CR) Hour change. */ -#define RTC_CR_TIMEVSEL_DAY24 (0x2 << 8) /**< \brief (RTC_CR) Every day at midnight. */ -#define RTC_CR_TIMEVSEL_DAY12 (0x3 << 8) /**< \brief (RTC_CR) Every day at noon. */ -#define RTC_CR_CALEVSEL (0x3 << 16) /**< \brief (RTC_CR) Calendar Event Selection */ -#define RTC_CR_CALEVSEL_WEEK (0x0 << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00). */ -#define RTC_CR_CALEVSEL_MONTH (0x1 << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00). */ -/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ -#define RTC_MR_HRMOD (0x1 << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ -/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ -#define RTC_TIMR_SEC (0x7f << 0) /**< \brief (RTC_TIMR) Current Second */ -#define RTC_TIMR_MIN (0x7f << 8) /**< \brief (RTC_TIMR) Current Minute */ -#define RTC_TIMR_HOUR (0x3f << 16) /**< \brief (RTC_TIMR) Current Hour */ -#define RTC_TIMR_AMPM (0x1 << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ -/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ -#define RTC_CALR_CENT (0x7f << 0) /**< \brief (RTC_CALR) Current Century */ -#define RTC_CALR_YEAR (0xff << 8) /**< \brief (RTC_CALR) Current Year */ -#define RTC_CALR_MONTH (0x1f << 16) /**< \brief (RTC_CALR) Current Month */ -#define RTC_CALR_DAY (0x7 << 21) /**< \brief (RTC_CALR) Current Day in Current Week */ -#define RTC_CALR_DATE (0x3f << 24) /**< \brief (RTC_CALR) Current Day in Current Month */ -/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ -#define RTC_TIMALR_SEC (0x7f << 0) /**< \brief (RTC_TIMALR) Second Alarm */ -#define RTC_TIMALR_SECEN (0x1 << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ -#define RTC_TIMALR_MIN (0x7f << 8) /**< \brief (RTC_TIMALR) Minute Alarm */ -#define RTC_TIMALR_MINEN (0x1 << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ -#define RTC_TIMALR_HOUR (0x3f << 16) /**< \brief (RTC_TIMALR) Hour Alarm */ -#define RTC_TIMALR_AMPM (0x1 << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ -#define RTC_TIMALR_HOUREN (0x1 << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ -/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ -#define RTC_CALALR_MONTH (0x1f << 16) /**< \brief (RTC_CALALR) Month Alarm */ -#define RTC_CALALR_MTHEN (0x1 << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ -#define RTC_CALALR_DATE (0x3f << 24) /**< \brief (RTC_CALALR) Date Alarm */ -#define RTC_CALALR_DATEEN (0x1 << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ -/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ -#define RTC_SR_ACKUPD (0x1 << 0) /**< \brief (RTC_SR) Acknowledge for Update */ -#define RTC_SR_ALARM (0x1 << 1) /**< \brief (RTC_SR) Alarm Flag */ -#define RTC_SR_SEC (0x1 << 2) /**< \brief (RTC_SR) Second Event */ -#define RTC_SR_TIMEV (0x1 << 3) /**< \brief (RTC_SR) Time Event */ -#define RTC_SR_CALEV (0x1 << 4) /**< \brief (RTC_SR) Calendar Event */ -/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ -#define RTC_SCCR_ACKCLR (0x1 << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ -#define RTC_SCCR_ALRCLR (0x1 << 1) /**< \brief (RTC_SCCR) Alarm Clear */ -#define RTC_SCCR_SECCLR (0x1 << 2) /**< \brief (RTC_SCCR) Second Clear */ -#define RTC_SCCR_TIMCLR (0x1 << 3) /**< \brief (RTC_SCCR) Time Clear */ -#define RTC_SCCR_CALCLR (0x1 << 4) /**< \brief (RTC_SCCR) Calendar Clear */ -/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ -#define RTC_IER_ACKEN (0x1 << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ -#define RTC_IER_ALREN (0x1 << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ -#define RTC_IER_SECEN (0x1 << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ -#define RTC_IER_TIMEN (0x1 << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ -#define RTC_IER_CALEN (0x1 << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ -/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ -#define RTC_IDR_ACKDIS (0x1 << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ -#define RTC_IDR_ALRDIS (0x1 << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ -#define RTC_IDR_SECDIS (0x1 << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ -#define RTC_IDR_TIMDIS (0x1 << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ -#define RTC_IDR_CALDIS (0x1 << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ -/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ -#define RTC_IMR_ACK (0x1 << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ -#define RTC_IMR_ALR (0x1 << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ -#define RTC_IMR_SEC (0x1 << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ -#define RTC_IMR_TIM (0x1 << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ -#define RTC_IMR_CAL (0x1 << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ -/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ -#define RTC_VER_NVTIM (0x1 << 0) /**< \brief (RTC_VER) Non-valid Time */ -#define RTC_VER_NVCAL (0x1 << 1) /**< \brief (RTC_VER) Non-valid Calendar */ -#define RTC_VER_NVTIMALR (0x1 << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ -#define RTC_VER_NVCALALR (0x1 << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RTT Real-time Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtt hardware registers */ -typedef struct { - RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ - RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ - RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ - RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ -} Rtt; -#endif /* __ASSEMBLY__ */ -/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ -#define RTT_MR_RTPRES (0xffff << 0) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ -#define RTT_MR_ALMIEN (0x1 << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ -#define RTT_MR_RTTINCIEN (0x1 << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ -#define RTT_MR_RTTRST (0x1 << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ -/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ -#define RTT_AR_ALMV (0xffffffff << 0) /**< \brief (RTT_AR) Alarm Value */ -/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ -#define RTT_VR_CRTV (0xffffffff << 0) /**< \brief (RTT_VR) Current Real-time Value */ -/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ -#define RTT_SR_ALMS (0x1 << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ -#define RTT_SR_RTTINC (0x1 << 1) /**< \brief (RTT_SR) Real-time Timer Increment */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Static Memory Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SMC Static Memory Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief SmcCs_number hardware registers */ -typedef struct { - RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ - RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ - RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ - RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */ -} SmcCs_number; -/** \brief Smc hardware registers */ -typedef struct { - SmcCs_number SMC_CS_NUMBER[5]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */ - RwReg Reserved1[12]; - RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ - WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ - WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ - RwReg Reserved2[22]; - RwReg SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */ - RoReg SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */ -} Smc; -#endif /* __ASSEMBLY__ */ -/* -------- SMC_SETUP0 : (SMC Offset: 0x0) SMC Setup Register (CS_number = 0) -------- */ -#define SMC_SETUP0_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP0) NWE Setup Length */ -#define SMC_SETUP0_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP0) NCS Setup Length in WRITE Access */ -#define SMC_SETUP0_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP0) NRD Setup Length */ -#define SMC_SETUP0_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP0) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE0 : (SMC Offset: 0x4) SMC Pulse Register (CS_number = 0) -------- */ -#define SMC_PULSE0_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE0) NWE Pulse Length */ -#define SMC_PULSE0_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE0) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE0_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE0) NRD Pulse Length */ -#define SMC_PULSE0_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE0) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE0 : (SMC Offset: 0x8) SMC Cycle Register (CS_number = 0) -------- */ -#define SMC_CYCLE0_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE0) Total Write Cycle Length */ -#define SMC_CYCLE0_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE0) Total Read Cycle Length */ -/* -------- SMC_MODE0 : (SMC Offset: 0xC) SMC Mode Register (CS_number = 0) -------- */ -#define SMC_MODE0_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE0) NWAIT Mode */ -#define SMC_MODE0_DBW (0x3 << 12) /**< \brief (SMC_MODE0) Data Bus Width */ -#define SMC_MODE0_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE0) Data Float Time */ -#define SMC_MODE0_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE0) TDF Optimization */ -#define SMC_MODE0_PMEN (0x1 << 24) /**< \brief (SMC_MODE0) Page Mode Enabled */ -#define SMC_MODE0_PS (0x3 << 28) /**< \brief (SMC_MODE0) Page Size */ -/* -------- SMC_SETUP1 : (SMC Offset: 0x10) SMC Setup Register (CS_number = 1) -------- */ -#define SMC_SETUP1_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP1) NWE Setup Length */ -#define SMC_SETUP1_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP1) NCS Setup Length in WRITE Access */ -#define SMC_SETUP1_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP1) NRD Setup Length */ -#define SMC_SETUP1_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP1) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE1 : (SMC Offset: 0x14) SMC Pulse Register (CS_number = 1) -------- */ -#define SMC_PULSE1_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE1) NWE Pulse Length */ -#define SMC_PULSE1_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE1) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE1_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE1) NRD Pulse Length */ -#define SMC_PULSE1_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE1) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE1 : (SMC Offset: 0x18) SMC Cycle Register (CS_number = 1) -------- */ -#define SMC_CYCLE1_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE1) Total Write Cycle Length */ -#define SMC_CYCLE1_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE1) Total Read Cycle Length */ -/* -------- SMC_MODE1 : (SMC Offset: 0x1C) SMC Mode Register (CS_number = 1) -------- */ -#define SMC_MODE1_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE1) NWAIT Mode */ -#define SMC_MODE1_DBW (0x3 << 12) /**< \brief (SMC_MODE1) Data Bus Width */ -#define SMC_MODE1_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE1) Data Float Time */ -#define SMC_MODE1_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE1) TDF Optimization */ -#define SMC_MODE1_PMEN (0x1 << 24) /**< \brief (SMC_MODE1) Page Mode Enabled */ -#define SMC_MODE1_PS (0x3 << 28) /**< \brief (SMC_MODE1) Page Size */ -/* -------- SMC_SETUP2 : (SMC Offset: 0x20) SMC Setup Register (CS_number = 2) -------- */ -#define SMC_SETUP2_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP2) NWE Setup Length */ -#define SMC_SETUP2_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP2) NCS Setup Length in WRITE Access */ -#define SMC_SETUP2_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP2) NRD Setup Length */ -#define SMC_SETUP2_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP2) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE2 : (SMC Offset: 0x24) SMC Pulse Register (CS_number = 2) -------- */ -#define SMC_PULSE2_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE2) NWE Pulse Length */ -#define SMC_PULSE2_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE2) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE2_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE2) NRD Pulse Length */ -#define SMC_PULSE2_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE2) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE2 : (SMC Offset: 0x28) SMC Cycle Register (CS_number = 2) -------- */ -#define SMC_CYCLE2_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE2) Total Write Cycle Length */ -#define SMC_CYCLE2_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE2) Total Read Cycle Length */ -/* -------- SMC_MODE2 : (SMC Offset: 0x2C) SMC Mode Register (CS_number = 2) -------- */ -#define SMC_MODE2_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE2) NWAIT Mode */ -#define SMC_MODE2_DBW (0x3 << 12) /**< \brief (SMC_MODE2) Data Bus Width */ -#define SMC_MODE2_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE2) Data Float Time */ -#define SMC_MODE2_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE2) TDF Optimization */ -#define SMC_MODE2_PMEN (0x1 << 24) /**< \brief (SMC_MODE2) Page Mode Enabled */ -#define SMC_MODE2_PS (0x3 << 28) /**< \brief (SMC_MODE2) Page Size */ -/* -------- SMC_SETUP3 : (SMC Offset: 0x30) SMC Setup Register (CS_number = 3) -------- */ -#define SMC_SETUP3_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP3) NWE Setup Length */ -#define SMC_SETUP3_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP3) NCS Setup Length in WRITE Access */ -#define SMC_SETUP3_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP3) NRD Setup Length */ -#define SMC_SETUP3_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP3) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE3 : (SMC Offset: 0x34) SMC Pulse Register (CS_number = 3) -------- */ -#define SMC_PULSE3_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE3) NWE Pulse Length */ -#define SMC_PULSE3_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE3) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE3_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE3) NRD Pulse Length */ -#define SMC_PULSE3_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE3) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE3 : (SMC Offset: 0x38) SMC Cycle Register (CS_number = 3) -------- */ -#define SMC_CYCLE3_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE3) Total Write Cycle Length */ -#define SMC_CYCLE3_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE3) Total Read Cycle Length */ -/* -------- SMC_MODE3 : (SMC Offset: 0x3C) SMC Mode Register (CS_number = 3) -------- */ -#define SMC_MODE3_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE3) NWAIT Mode */ -#define SMC_MODE3_DBW (0x3 << 12) /**< \brief (SMC_MODE3) Data Bus Width */ -#define SMC_MODE3_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE3) Data Float Time */ -#define SMC_MODE3_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE3) TDF Optimization */ -#define SMC_MODE3_PMEN (0x1 << 24) /**< \brief (SMC_MODE3) Page Mode Enabled */ -#define SMC_MODE3_PS (0x3 << 28) /**< \brief (SMC_MODE3) Page Size */ -/* -------- SMC_SETUP4 : (SMC Offset: 0x40) SMC Setup Register (CS_number = 4) -------- */ -#define SMC_SETUP4_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP4) NWE Setup Length */ -#define SMC_SETUP4_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP4) NCS Setup Length in WRITE Access */ -#define SMC_SETUP4_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP4) NRD Setup Length */ -#define SMC_SETUP4_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP4) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE4 : (SMC Offset: 0x44) SMC Pulse Register (CS_number = 4) -------- */ -#define SMC_PULSE4_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE4) NWE Pulse Length */ -#define SMC_PULSE4_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE4) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE4_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE4) NRD Pulse Length */ -#define SMC_PULSE4_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE4) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE4 : (SMC Offset: 0x48) SMC Cycle Register (CS_number = 4) -------- */ -#define SMC_CYCLE4_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE4) Total Write Cycle Length */ -#define SMC_CYCLE4_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE4) Total Read Cycle Length */ -/* -------- SMC_MODE4 : (SMC Offset: 0x4C) SMC Mode Register (CS_number = 4) -------- */ -#define SMC_MODE4_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE4) */ -#define SMC_MODE4_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE4) */ -#define SMC_MODE4_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE4) NWAIT Mode */ -#define SMC_MODE4_DBW (0x3 << 12) /**< \brief (SMC_MODE4) Data Bus Width */ -#define SMC_MODE4_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE4) Data Float Time */ -#define SMC_MODE4_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE4) TDF Optimization */ -#define SMC_MODE4_PMEN (0x1 << 24) /**< \brief (SMC_MODE4) Page Mode Enabled */ -#define SMC_MODE4_PS (0x3 << 28) /**< \brief (SMC_MODE4) Page Size */ -/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ -#define SMC_OCMS_SMSE (0x1 << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ -#define SMC_OCMS_CS0SE (0x1 << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS1SE (0x1 << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS2SE (0x1 << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS3SE (0x1 << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ -#define SMC_KEY1_KEY1 (0xffffffff << 0) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ -/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ -#define SMC_KEY2_KEY2 (0xffffffff << 0) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ -/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */ -#define SMC_WPMR_WPEN (0x1 << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ -#define SMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SMC_WPMR) Write Protect KEY */ -/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */ -#define SMC_WPSR_WPVS (0x1 << 0) /**< \brief (SMC_WPSR) Write Protect Enable */ -#define SMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SMC_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SPI Serial Peripheral Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Spi hardware registers */ -typedef struct { - WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ - RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ - RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ - WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ - RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ - WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ - WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ - RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ - RwReg Reserved1[4]; - RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ - RwReg Reserved2[41]; - RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ - RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ - RwReg Reserved3[5]; - RwReg SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */ - RwReg SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */ - RwReg SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */ - RwReg SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */ - RwReg SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */ - RwReg SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */ - RwReg SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */ - RwReg SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */ - WoReg SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */ - RoReg SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */ -} Spi; -#endif /* __ASSEMBLY__ */ -/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ -#define SPI_CR_SPIEN (0x1 << 0) /**< \brief (SPI_CR) SPI Enable */ -#define SPI_CR_SPIDIS (0x1 << 1) /**< \brief (SPI_CR) SPI Disable */ -#define SPI_CR_SWRST (0x1 << 7) /**< \brief (SPI_CR) SPI Software Reset */ -#define SPI_CR_LASTXFER (0x1 << 24) /**< \brief (SPI_CR) Last Transfer */ -/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ -#define SPI_MR_MSTR (0x1 << 0) /**< \brief (SPI_MR) Master/Slave Mode */ -#define SPI_MR_PS (0x1 << 1) /**< \brief (SPI_MR) Peripheral Select */ -#define SPI_MR_PS_FIXED (0x0 << 1) /**< \brief (SPI_MR) Fixed Peripheral Select. */ -#define SPI_MR_PS_VARIABLE (0x1 << 1) /**< \brief (SPI_MR) Variable Peripheral Select. */ -#define SPI_MR_PCSDEC (0x1 << 2) /**< \brief (SPI_MR) Chip Select Decode */ -#define SPI_MR_MODFDIS (0x1 << 4) /**< \brief (SPI_MR) Mode Fault Detection */ -#define SPI_MR_WDRBT (0x1 << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ -#define SPI_MR_LLB (0x1 << 7) /**< \brief (SPI_MR) Local Loopback Enable */ -#define SPI_MR_PCS (0xf << 16) /**< \brief (SPI_MR) Peripheral Chip Select */ -#define SPI_MR_DLYBCS (0xff << 24) /**< \brief (SPI_MR) Delay Between Chip Selects */ -/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ -#define SPI_RDR_RD (0xffff << 0) /**< \brief (SPI_RDR) Receive Data */ -#define SPI_RDR_PCS (0xf << 16) /**< \brief (SPI_RDR) Peripheral Chip Select */ -/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ -#define SPI_TDR_TD (0xffff << 0) /**< \brief (SPI_TDR) Transmit Data */ -#define SPI_TDR_PCS (0xf << 16) /**< \brief (SPI_TDR) Peripheral Chip Select */ -#define SPI_TDR_LASTXFER (0x1 << 24) /**< \brief (SPI_TDR) Last Transfer */ -/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ -#define SPI_SR_RDRF (0x1 << 0) /**< \brief (SPI_SR) Receive Data Register Full */ -#define SPI_SR_TDRE (0x1 << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ -#define SPI_SR_MODF (0x1 << 2) /**< \brief (SPI_SR) Mode Fault Error */ -#define SPI_SR_OVRES (0x1 << 3) /**< \brief (SPI_SR) Overrun Error Status */ -#define SPI_SR_ENDRX (0x1 << 4) /**< \brief (SPI_SR) End of RX buffer */ -#define SPI_SR_ENDTX (0x1 << 5) /**< \brief (SPI_SR) End of TX buffer */ -#define SPI_SR_RXBUFF (0x1 << 6) /**< \brief (SPI_SR) RX Buffer Full */ -#define SPI_SR_TXBUFE (0x1 << 7) /**< \brief (SPI_SR) TX Buffer Empty */ -#define SPI_SR_NSSR (0x1 << 8) /**< \brief (SPI_SR) NSS Rising */ -#define SPI_SR_TXEMPTY (0x1 << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ -#define SPI_SR_UNDES (0x1 << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ -#define SPI_SR_SPIENS (0x1 << 16) /**< \brief (SPI_SR) SPI Enable Status */ -/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ -#define SPI_IER_RDRF (0x1 << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ -#define SPI_IER_TDRE (0x1 << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ -#define SPI_IER_MODF (0x1 << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ -#define SPI_IER_OVRES (0x1 << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ -#define SPI_IER_ENDRX (0x1 << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */ -#define SPI_IER_ENDTX (0x1 << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */ -#define SPI_IER_RXBUFF (0x1 << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */ -#define SPI_IER_TXBUFE (0x1 << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */ -#define SPI_IER_NSSR (0x1 << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ -#define SPI_IER_TXEMPTY (0x1 << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ -#define SPI_IER_UNDES (0x1 << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ -/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ -#define SPI_IDR_RDRF (0x1 << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ -#define SPI_IDR_TDRE (0x1 << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ -#define SPI_IDR_MODF (0x1 << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ -#define SPI_IDR_OVRES (0x1 << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ -#define SPI_IDR_ENDRX (0x1 << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */ -#define SPI_IDR_ENDTX (0x1 << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */ -#define SPI_IDR_RXBUFF (0x1 << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */ -#define SPI_IDR_TXBUFE (0x1 << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SPI_IDR_NSSR (0x1 << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ -#define SPI_IDR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ -#define SPI_IDR_UNDES (0x1 << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ -/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ -#define SPI_IMR_RDRF (0x1 << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ -#define SPI_IMR_TDRE (0x1 << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ -#define SPI_IMR_MODF (0x1 << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ -#define SPI_IMR_OVRES (0x1 << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ -#define SPI_IMR_ENDRX (0x1 << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */ -#define SPI_IMR_ENDTX (0x1 << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */ -#define SPI_IMR_RXBUFF (0x1 << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */ -#define SPI_IMR_TXBUFE (0x1 << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SPI_IMR_NSSR (0x1 << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ -#define SPI_IMR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ -#define SPI_IMR_UNDES (0x1 << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ -/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ -#define SPI_CSR_CPOL (0x1 << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ -#define SPI_CSR_NCPHA (0x1 << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ -#define SPI_CSR_CSNAAT (0x1 << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_CSAAT (0x1 << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_BITS (0xf << 4) /**< \brief (SPI_CSR[4]) Bits Per Transfer (See the (Note:) below the register table; Section 9.9 "SPI Chip Select Register" on page 35.) */ -#define SPI_CSR_BITS_8 (0x0 << 4) /**< \brief (SPI_CSR[4]) 8 */ -#define SPI_CSR_BITS_9 (0x1 << 4) /**< \brief (SPI_CSR[4]) 9 */ -#define SPI_CSR_BITS_10 (0x2 << 4) /**< \brief (SPI_CSR[4]) 10 */ -#define SPI_CSR_BITS_11 (0x3 << 4) /**< \brief (SPI_CSR[4]) 11 */ -#define SPI_CSR_BITS_12 (0x4 << 4) /**< \brief (SPI_CSR[4]) 12 */ -#define SPI_CSR_BITS_13 (0x5 << 4) /**< \brief (SPI_CSR[4]) 13 */ -#define SPI_CSR_BITS_14 (0x6 << 4) /**< \brief (SPI_CSR[4]) 14 */ -#define SPI_CSR_BITS_15 (0x7 << 4) /**< \brief (SPI_CSR[4]) 15 */ -#define SPI_CSR_BITS_16 (0x8 << 4) /**< \brief (SPI_CSR[4]) 16 */ -#define SPI_CSR_SCBR (0xff << 8) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ -#define SPI_CSR_DLYBS (0xff << 16) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ -#define SPI_CSR_DLYBCT (0xff << 24) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ -/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ -#define SPI_WPMR_SPIWPEN (0x1 << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */ -#define SPI_WPMR_SPIWPKEY (0xffffff << 8) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */ -/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ -#define SPI_WPSR_SPIWPVS (0x7 << 0) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */ -#define SPI_WPSR_SPIWPVSRC (0xff << 8) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */ -/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */ -#define SPI_RPR_RXPTR (0xffffffff << 0) /**< \brief (SPI_RPR) Receive Pointer Register */ -/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */ -#define SPI_RCR_RXCTR (0xffff << 0) /**< \brief (SPI_RCR) Receive Counter Register */ -/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */ -#define SPI_TPR_TXPTR (0xffffffff << 0) /**< \brief (SPI_TPR) Transmit Counter Register */ -/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */ -#define SPI_TCR_TXCTR (0xffff << 0) /**< \brief (SPI_TCR) Transmit Counter Register */ -/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */ -#define SPI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SPI_RNPR) Receive Next Pointer */ -/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */ -#define SPI_RNCR_RXNCTR (0xffff << 0) /**< \brief (SPI_RNCR) Receive Next Counter */ -/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define SPI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SPI_TNPR) Transmit Next Pointer */ -/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define SPI_TNCR_TXNCTR (0xffff << 0) /**< \brief (SPI_TNCR) Transmit Counter Next */ -/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */ -#define SPI_PTCR_RXTEN (0x1 << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */ -#define SPI_PTCR_RXTDIS (0x1 << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */ -#define SPI_PTCR_TXTEN (0x1 << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */ -#define SPI_PTCR_TXTDIS (0x1 << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */ -/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */ -#define SPI_PTSR_RXTEN (0x1 << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */ -#define SPI_PTSR_TXTEN (0x1 << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SSC Synchronous Serial Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Ssc hardware registers */ -typedef struct { - WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ - RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ - RwReg Reserved1[2]; - RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ - RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ - RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ - RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ - RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ - WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ - RwReg Reserved2[2]; - RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ - RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ - RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ - RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ - RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ - WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ - WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ - RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ - RwReg Reserved3[37]; - RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */ - RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved4[5]; - RwReg SSC_RPR; /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */ - RwReg SSC_RCR; /**< \brief (Ssc Offset: 0x104) Receive Counter Register */ - RwReg SSC_TPR; /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */ - RwReg SSC_TCR; /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */ - RwReg SSC_RNPR; /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */ - RwReg SSC_RNCR; /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */ - RwReg SSC_TNPR; /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */ - RwReg SSC_TNCR; /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */ - WoReg SSC_PTCR; /**< \brief (Ssc Offset: 0x120) Transfer Control Register */ - RoReg SSC_PTSR; /**< \brief (Ssc Offset: 0x124) Transfer Status Register */ -} Ssc; -#endif /* __ASSEMBLY__ */ -/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ -#define SSC_CR_RXEN (0x1 << 0) /**< \brief (SSC_CR) Receive Enable */ -#define SSC_CR_RXDIS (0x1 << 1) /**< \brief (SSC_CR) Receive Disable */ -#define SSC_CR_TXEN (0x1 << 8) /**< \brief (SSC_CR) Transmit Enable */ -#define SSC_CR_TXDIS (0x1 << 9) /**< \brief (SSC_CR) Transmit Disable */ -#define SSC_CR_SWRST (0x1 << 15) /**< \brief (SSC_CR) Software Reset */ -/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ -#define SSC_CMR_DIV (0xfff << 0) /**< \brief (SSC_CMR) Clock Divider */ -/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ -#define SSC_RCMR_CKS (0x3 << 0) /**< \brief (SSC_RCMR) Receive Clock Selection */ -#define SSC_RCMR_CKS_DIV (0x0 << 0) /**< \brief (SSC_RCMR) Divided Clock */ -#define SSC_RCMR_CKS_TK (0x1 << 0) /**< \brief (SSC_RCMR) TK Clock signal */ -#define SSC_RCMR_CKS_RK (0x2 << 0) /**< \brief (SSC_RCMR) RK pin */ -#define SSC_RCMR_CKO (0x7 << 2) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ -#define SSC_RCMR_CKI (0x1 << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ -#define SSC_RCMR_CKG (0x3 << 6) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ -#define SSC_RCMR_CKG_NONE (0x0 << 6) /**< \brief (SSC_RCMR) None, continuous clock */ -#define SSC_RCMR_CKG_LOW (0x1 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ -#define SSC_RCMR_CKG_HIGH (0x2 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ -#define SSC_RCMR_START (0xf << 8) /**< \brief (SSC_RCMR) Receive Start Selection */ -#define SSC_RCMR_STOP (0x1 << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ -#define SSC_RCMR_STTDLY (0xff << 16) /**< \brief (SSC_RCMR) Receive Start Delay */ -#define SSC_RCMR_PERIOD (0xff << 24) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ -/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ -#define SSC_RFMR_DATLEN (0x1f << 0) /**< \brief (SSC_RFMR) Data Length */ -#define SSC_RFMR_LOOP (0x1 << 5) /**< \brief (SSC_RFMR) Loop Mode */ -#define SSC_RFMR_MSBF (0x1 << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ -#define SSC_RFMR_DATNB (0xf << 8) /**< \brief (SSC_RFMR) Data Number per Frame */ -#define SSC_RFMR_FSLEN (0xf << 16) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ -#define SSC_RFMR_FSOS (0x7 << 20) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ -#define SSC_RFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ -#define SSC_RFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_RFMR) FSLEN Field Extension */ -/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ -#define SSC_TCMR_CKS (0x3 << 0) /**< \brief (SSC_TCMR) Transmit Clock Selection */ -#define SSC_TCMR_CKO (0x7 << 2) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ -#define SSC_TCMR_CKI (0x1 << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ -#define SSC_TCMR_CKG (0x3 << 6) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ -#define SSC_TCMR_START (0xf << 8) /**< \brief (SSC_TCMR) Transmit Start Selection */ -#define SSC_TCMR_STTDLY (0xff << 16) /**< \brief (SSC_TCMR) Transmit Start Delay */ -#define SSC_TCMR_PERIOD (0xff << 24) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ -/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ -#define SSC_TFMR_DATLEN (0x1f << 0) /**< \brief (SSC_TFMR) Data Length */ -#define SSC_TFMR_DATDEF (0x1 << 5) /**< \brief (SSC_TFMR) Data Default Value */ -#define SSC_TFMR_MSBF (0x1 << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ -#define SSC_TFMR_DATNB (0xf << 8) /**< \brief (SSC_TFMR) Data Number per frame */ -#define SSC_TFMR_FSLEN (0xf << 16) /**< \brief (SSC_TFMR) Transmit Frame Syn Length */ -#define SSC_TFMR_FSOS (0x7 << 20) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ -#define SSC_TFMR_FSDEN (0x1 << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ -#define SSC_TFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ -#define SSC_TFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_TFMR) FSLEN Field Extension */ -/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ -#define SSC_RHR_RDAT (0xffffffff << 0) /**< \brief (SSC_RHR) Receive Data */ -/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ -#define SSC_THR_TDAT (0xffffffff << 0) /**< \brief (SSC_THR) Transmit Data */ -/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ -#define SSC_RSHR_RSDAT (0xffff << 0) /**< \brief (SSC_RSHR) Receive Synchronization Data */ -/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ -#define SSC_TSHR_TSDAT (0xffff << 0) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ -/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ -#define SSC_RC0R_CP0 (0xffff << 0) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ -/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ -#define SSC_RC1R_CP1 (0xffff << 0) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ -/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ -#define SSC_SR_TXRDY (0x1 << 0) /**< \brief (SSC_SR) Transmit Ready */ -#define SSC_SR_TXEMPTY (0x1 << 1) /**< \brief (SSC_SR) Transmit Empty */ -#define SSC_SR_ENDTX (0x1 << 2) /**< \brief (SSC_SR) End of Transmission */ -#define SSC_SR_TXBUFE (0x1 << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */ -#define SSC_SR_RXRDY (0x1 << 4) /**< \brief (SSC_SR) Receive Ready */ -#define SSC_SR_OVRUN (0x1 << 5) /**< \brief (SSC_SR) Receive Overrun */ -#define SSC_SR_ENDRX (0x1 << 6) /**< \brief (SSC_SR) End of Reception */ -#define SSC_SR_RXBUFF (0x1 << 7) /**< \brief (SSC_SR) Receive Buffer Full */ -#define SSC_SR_CP0 (0x1 << 8) /**< \brief (SSC_SR) Compare 0 */ -#define SSC_SR_CP1 (0x1 << 9) /**< \brief (SSC_SR) Compare 1 */ -#define SSC_SR_TXSYN (0x1 << 10) /**< \brief (SSC_SR) Transmit Sync */ -#define SSC_SR_RXSYN (0x1 << 11) /**< \brief (SSC_SR) Receive Sync */ -#define SSC_SR_TXEN (0x1 << 16) /**< \brief (SSC_SR) Transmit Enable */ -#define SSC_SR_RXEN (0x1 << 17) /**< \brief (SSC_SR) Receive Enable */ -/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ -#define SSC_IER_TXRDY (0x1 << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ -#define SSC_IER_TXEMPTY (0x1 << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ -#define SSC_IER_ENDTX (0x1 << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */ -#define SSC_IER_TXBUFE (0x1 << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */ -#define SSC_IER_RXRDY (0x1 << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ -#define SSC_IER_OVRUN (0x1 << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ -#define SSC_IER_ENDRX (0x1 << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */ -#define SSC_IER_RXBUFF (0x1 << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */ -#define SSC_IER_CP0 (0x1 << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ -#define SSC_IER_CP1 (0x1 << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ -#define SSC_IER_TXSYN (0x1 << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ -#define SSC_IER_RXSYN (0x1 << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ -/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ -#define SSC_IDR_TXRDY (0x1 << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ -#define SSC_IDR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ -#define SSC_IDR_ENDTX (0x1 << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */ -#define SSC_IDR_TXBUFE (0x1 << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SSC_IDR_RXRDY (0x1 << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ -#define SSC_IDR_OVRUN (0x1 << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ -#define SSC_IDR_ENDRX (0x1 << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */ -#define SSC_IDR_RXBUFF (0x1 << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */ -#define SSC_IDR_CP0 (0x1 << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ -#define SSC_IDR_CP1 (0x1 << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ -#define SSC_IDR_TXSYN (0x1 << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ -#define SSC_IDR_RXSYN (0x1 << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ -/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ -#define SSC_IMR_TXRDY (0x1 << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ -#define SSC_IMR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ -#define SSC_IMR_ENDTX (0x1 << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */ -#define SSC_IMR_TXBUFE (0x1 << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SSC_IMR_RXRDY (0x1 << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ -#define SSC_IMR_OVRUN (0x1 << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ -#define SSC_IMR_ENDRX (0x1 << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */ -#define SSC_IMR_RXBUFF (0x1 << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */ -#define SSC_IMR_CP0 (0x1 << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ -#define SSC_IMR_CP1 (0x1 << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ -#define SSC_IMR_TXSYN (0x1 << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ -#define SSC_IMR_RXSYN (0x1 << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ -/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */ -#define SSC_WPMR_WPEN (0x1 << 0) /**< \brief (SSC_WPMR) Write Protect Enable */ -#define SSC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SSC_WPMR) Write Protect KEY */ -/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */ -#define SSC_WPSR_WPVS (0x1 << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */ -#define SSC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SSC_WPSR) Write Protect Violation Source */ -/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */ -#define SSC_RPR_RXPTR (0xffffffff << 0) /**< \brief (SSC_RPR) Receive Pointer Register */ -/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */ -#define SSC_RCR_RXCTR (0xffff << 0) /**< \brief (SSC_RCR) Receive Counter Register */ -/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */ -#define SSC_TPR_TXPTR (0xffffffff << 0) /**< \brief (SSC_TPR) Transmit Counter Register */ -/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */ -#define SSC_TCR_TXCTR (0xffff << 0) /**< \brief (SSC_TCR) Transmit Counter Register */ -/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */ -#define SSC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SSC_RNPR) Receive Next Pointer */ -/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */ -#define SSC_RNCR_RXNCTR (0xffff << 0) /**< \brief (SSC_RNCR) Receive Next Counter */ -/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define SSC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SSC_TNPR) Transmit Next Pointer */ -/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define SSC_TNCR_TXNCTR (0xffff << 0) /**< \brief (SSC_TNCR) Transmit Counter Next */ -/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */ -#define SSC_PTCR_RXTEN (0x1 << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */ -#define SSC_PTCR_RXTDIS (0x1 << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */ -#define SSC_PTCR_TXTEN (0x1 << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */ -#define SSC_PTCR_TXTDIS (0x1 << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */ -/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */ -#define SSC_PTSR_RXTEN (0x1 << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */ -#define SSC_PTSR_TXTEN (0x1 << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Supply Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SUPC Supply Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Supc hardware registers */ -typedef struct { - WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ - RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ - RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ - RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */ - RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */ - RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ -} Supc; -#endif /* __ASSEMBLY__ */ -/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ -#define SUPC_CR_VROFF (0x1 << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ -#define SUPC_CR_VROFF_NO_EFFECT (0x0 << 2) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_VROFF_STOP_VREG (0x1 << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */ -#define SUPC_CR_XTALSEL (0x1 << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ -#define SUPC_CR_XTALSEL_NO_EFFECT (0x0 << 3) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1 << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ -#define SUPC_CR_KEY (0xff << 24) /**< \brief (SUPC_CR) Password */ -/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ -#define SUPC_SMMR_SMTH (0xf << 0) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ -#define SUPC_SMMR_SMTH_1_9V (0x0 << 0) /**< \brief (SUPC_SMMR) 1.9 V */ -#define SUPC_SMMR_SMTH_2_0V (0x1 << 0) /**< \brief (SUPC_SMMR) 2.0 V */ -#define SUPC_SMMR_SMTH_2_1V (0x2 << 0) /**< \brief (SUPC_SMMR) 2.1 V */ -#define SUPC_SMMR_SMTH_2_2V (0x3 << 0) /**< \brief (SUPC_SMMR) 2.2 V */ -#define SUPC_SMMR_SMTH_2_3V (0x4 << 0) /**< \brief (SUPC_SMMR) 2.3 V */ -#define SUPC_SMMR_SMTH_2_4V (0x5 << 0) /**< \brief (SUPC_SMMR) 2.4 V */ -#define SUPC_SMMR_SMTH_2_5V (0x6 << 0) /**< \brief (SUPC_SMMR) 2.5 V */ -#define SUPC_SMMR_SMTH_2_6V (0x7 << 0) /**< \brief (SUPC_SMMR) 2.6 V */ -#define SUPC_SMMR_SMTH_2_7V (0x8 << 0) /**< \brief (SUPC_SMMR) 2.7 V */ -#define SUPC_SMMR_SMTH_2_8V (0x9 << 0) /**< \brief (SUPC_SMMR) 2.8 V */ -#define SUPC_SMMR_SMTH_2_9V (0xA << 0) /**< \brief (SUPC_SMMR) 2.9 V */ -#define SUPC_SMMR_SMTH_3_0V (0xB << 0) /**< \brief (SUPC_SMMR) 3.0 V */ -#define SUPC_SMMR_SMTH_3_1V (0xC << 0) /**< \brief (SUPC_SMMR) 3.1 V */ -#define SUPC_SMMR_SMTH_3_2V (0xD << 0) /**< \brief (SUPC_SMMR) 3.2 V */ -#define SUPC_SMMR_SMTH_3_3V (0xE << 0) /**< \brief (SUPC_SMMR) 3.3 V */ -#define SUPC_SMMR_SMTH_3_4V (0xF << 0) /**< \brief (SUPC_SMMR) 3.4 V */ -#define SUPC_SMMR_SMSMPL (0x7 << 8) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ -#define SUPC_SMMR_SMSMPL_SMD (0x0 << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ -#define SUPC_SMMR_SMSMPL_CSM (0x1 << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ -#define SUPC_SMMR_SMSMPL_32SLCK (0x2 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ -#define SUPC_SMMR_SMSMPL_256SLCK (0x3 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ -#define SUPC_SMMR_SMSMPL_2048SLCK (0x4 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ -#define SUPC_SMMR_SMRSTEN (0x1 << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ -#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN (0x1 << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ -#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN_ENABLE (0x1 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ -/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ -#define SUPC_MR_BODRSTEN (0x1 << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ -#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ -#define SUPC_MR_BODRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ -#define SUPC_MR_BODDIS (0x1 << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ -#define SUPC_MR_BODDIS_ENABLE (0x0 << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ -#define SUPC_MR_BODDIS_DISABLE (0x1 << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ -#define SUPC_MR_ONREG (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */ -#define SUPC_MR_ONREG_ONREG_UNUSED (0x0 << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */ -#define SUPC_MR_ONREG_ONREG_USED (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */ -#define SUPC_MR_OSCBYPASS (0x1 << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ -#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0 << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ -#define SUPC_MR_OSCBYPASS_BYPASS (0x1 << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ -#define SUPC_MR_KEY (0xff << 24) /**< \brief (SUPC_MR) Password Key */ -/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */ -#define SUPC_WUMR_SMEN (0x1 << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */ -#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */ -#define SUPC_WUMR_SMEN_ENABLE (0x1 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTTEN (0x1 << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */ -#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTTEN_ENABLE (0x1 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTCEN (0x1 << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */ -#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTCEN_ENABLE (0x1 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_WKUPDBC (0x7 << 12) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer */ -#define SUPC_WUMR_WKUPDBC_1SCLK (0x0 << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ -#define SUPC_WUMR_WKUPDBC_3SCLK (0x1 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 3 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32SCLK (0x2 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_512SCLK (0x3 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 512 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_4096SCLK (0x4 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 4,096 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32768SCLK (0x5 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32,768 SLCK periods */ -/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */ -#define SUPC_WUIR_WKUPEN0 (0x1 << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */ -#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN0_ENABLE (0x1 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN1 (0x1 << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */ -#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN1_ENABLE (0x1 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN2 (0x1 << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */ -#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN2_ENABLE (0x1 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN3 (0x1 << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */ -#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN3_ENABLE (0x1 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN4 (0x1 << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */ -#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN4_ENABLE (0x1 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN5 (0x1 << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */ -#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN5_ENABLE (0x1 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN6 (0x1 << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */ -#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN6_ENABLE (0x1 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN7 (0x1 << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */ -#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN7_ENABLE (0x1 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN8 (0x1 << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */ -#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN8_ENABLE (0x1 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN9 (0x1 << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */ -#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN9_ENABLE (0x1 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN10 (0x1 << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */ -#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN10_ENABLE (0x1 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN11 (0x1 << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */ -#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN11_ENABLE (0x1 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN12 (0x1 << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */ -#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN12_ENABLE (0x1 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN13 (0x1 << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */ -#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN13_ENABLE (0x1 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN14 (0x1 << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */ -#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN14_ENABLE (0x1 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN15 (0x1 << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */ -#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN15_ENABLE (0x1 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0 (0x1 << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */ -#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0 << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1 << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1 (0x1 << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */ -#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0 << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1 << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2 (0x1 << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */ -#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0 << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1 << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3 (0x1 << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */ -#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0 << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1 << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4 (0x1 << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */ -#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0 << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1 << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5 (0x1 << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */ -#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0 << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1 << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6 (0x1 << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */ -#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0 << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1 << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7 (0x1 << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */ -#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0 << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1 << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8 (0x1 << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */ -#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0 << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1 << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9 (0x1 << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */ -#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0 << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1 << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10 (0x1 << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */ -#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0 << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1 << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11 (0x1 << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */ -#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0 << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1 << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12 (0x1 << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */ -#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0 << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1 << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13 (0x1 << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */ -#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0 << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1 << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14 (0x1 << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */ -#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0 << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1 << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15 (0x1 << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */ -#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0 << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1 << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ -#define SUPC_SR_WKUPS (0x1 << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */ -#define SUPC_SR_WKUPS_NO (0x0 << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_WKUPS_PRESENT (0x1 << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS (0x1 << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */ -#define SUPC_SR_SMWS_NO (0x0 << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS_PRESENT (0x1 << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_BODRSTS (0x1 << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ -#define SUPC_SR_BODRSTS_NO (0x0 << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_BODRSTS_PRESENT (0x1 << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS (0x1 << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ -#define SUPC_SR_SMRSTS_NO (0x0 << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS_PRESENT (0x1 << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMS (0x1 << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ -#define SUPC_SR_SMS_NO (0x0 << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMS_PRESENT (0x1 << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMOS (0x1 << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ -#define SUPC_SR_SMOS_HIGH (0x0 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */ -#define SUPC_SR_SMOS_LOW (0x1 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */ -#define SUPC_SR_OSCSEL (0x1 << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ -#define SUPC_SR_OSCSEL_RC (0x0 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ -#define SUPC_SR_OSCSEL_CRYST (0x1 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ -#define SUPC_SR_WKUPIS0 (0x1 << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ -#define SUPC_SR_WKUPIS0_DIS (0x0 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS0_EN (0x1 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1 (0x1 << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ -#define SUPC_SR_WKUPIS1_DIS (0x0 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1_EN (0x1 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2 (0x1 << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ -#define SUPC_SR_WKUPIS2_DIS (0x0 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2_EN (0x1 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3 (0x1 << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ -#define SUPC_SR_WKUPIS3_DIS (0x0 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3_EN (0x1 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4 (0x1 << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ -#define SUPC_SR_WKUPIS4_DIS (0x0 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4_EN (0x1 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5 (0x1 << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ -#define SUPC_SR_WKUPIS5_DIS (0x0 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5_EN (0x1 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6 (0x1 << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ -#define SUPC_SR_WKUPIS6_DIS (0x0 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6_EN (0x1 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7 (0x1 << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ -#define SUPC_SR_WKUPIS7_DIS (0x0 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7_EN (0x1 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8 (0x1 << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ -#define SUPC_SR_WKUPIS8_DIS (0x0 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8_EN (0x1 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9 (0x1 << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ -#define SUPC_SR_WKUPIS9_DIS (0x0 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9_EN (0x1 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10 (0x1 << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ -#define SUPC_SR_WKUPIS10_DIS (0x0 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10_EN (0x1 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11 (0x1 << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ -#define SUPC_SR_WKUPIS11_DIS (0x0 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11_EN (0x1 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12 (0x1 << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ -#define SUPC_SR_WKUPIS12_DIS (0x0 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12_EN (0x1 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13 (0x1 << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ -#define SUPC_SR_WKUPIS13_DIS (0x0 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13_EN (0x1 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14 (0x1 << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ -#define SUPC_SR_WKUPIS14_DIS (0x0 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14_EN (0x1 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15 (0x1 << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ -#define SUPC_SR_WKUPIS15_DIS (0x0 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15_EN (0x1 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Timer Counter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_TC Timer Counter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief TcChannel hardware registers */ -typedef struct { - RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ - RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ - RwReg Reserved1[2]; - RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ - RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ - RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ - RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ - RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ - RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ - RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ - RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ - RwReg Reserved2[4]; -} TcChannel; -/** \brief Tc hardware registers */ -typedef struct { - TcChannel TC_CHANNEL[3]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ - WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ - RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ - WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ - WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ - RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ - RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ - RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ - RwReg Reserved1[2]; - RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */ - RwReg Reserved2[5]; - RoReg TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ -} Tc; -#endif /* __ASSEMBLY__ */ -/* -------- TC_CCR0 : (TC Offset: 0x0) Channel Control Register (channel = 0) -------- */ -#define TC_CCR0_CLKEN (0x1 << 0) /**< \brief (TC_CCR0) Counter Clock Enable Command */ -#define TC_CCR0_CLKDIS (0x1 << 1) /**< \brief (TC_CCR0) Counter Clock Disable Command */ -#define TC_CCR0_SWTRG (0x1 << 2) /**< \brief (TC_CCR0) Software Trigger Command */ -/* -------- TC_CMR0 : (TC Offset: 0x4) Channel Mode Register (channel = 0) -------- */ -#define TC_CMR0_TCCLKS (0x7 << 0) /**< \brief (TC_CMR0) Clock Selection */ -#define TC_CM0_TCCLKS_TIMER_DIV1_CLOCK (0x0 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV1_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV2_CLOCK (0x1 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV2_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV3_CLOCK (0x2 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV3_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV4_CLOCK (0x3 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV4_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV5_CLOCK (0x4 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV5_CLOCK*/ -#define TC_CM0_TCCLKS_XC0 (0x5 << 0) /**< (TC_CMR0) Clock selected: XC0*/ -#define TC_CM0_TCCLKS_XC1 (0x6 << 0) /**< (TC_CMR0) Clock selected: XC1*/ -#define TC_CM0_TCCLKS_XC2 (0x7 << 0) /**< (TC_CMR0) Clock selected: XC2*/ -#define TC_CMR0_CLKI (0x1 << 3) /**< \brief (TC_CMR0) Clock Invert */ -#define TC_CMR0_BURST (0x3 << 4) /**< \brief (TC_CMR0) Burst Signal Selection */ -#define TC_CMR0_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR0) The clock is not gated by an external signal. */ -#define TC_CMR0_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR0) XC0 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR0) XC1 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR0) XC2 is ANDed with the selected clock. */ -#define TC_CMR0_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR0) Counter Clock Stopped with RB Loading */ -#define TC_CMR0_LDBDIS (0x1 << 7) /**< \brief (TC_CMR0) Counter Clock Disable with RB Loading */ -#define TC_CMR0_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR0) External Trigger Edge Selection */ -#define TC_CMR0_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR0) rising edge */ -#define TC_CMR0_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR0) falling edge */ -#define TC_CMR0_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR0) each edge */ -#define TC_CMR0_ABETRG (0x1 << 10) /**< \brief (TC_CMR0) TIOA or TIOB External Trigger Selection */ -#define TC_CMR0_CPCTRG (0x1 << 14) /**< \brief (TC_CMR0) RC Compare Trigger Enable */ -#define TC_CMR0_WAVE (0x1 << 15) /**< \brief (TC_CMR0) */ -#define TC_CMR0_LDRA (0x3 << 16) /**< \brief (TC_CMR0) RA Loading Selection */ -#define TC_CMR0_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR0) each edge of TIOA */ -#define TC_CMR0_LDRB (0x3 << 18) /**< \brief (TC_CMR0) RB Loading Selection */ -#define TC_CMR0_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR0) each edge of TIOA */ - -#define TC_CMR0_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define TC_CMR0_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define TC_CMR0_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define TC_CMR0_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle - -#define TC_CMR0_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define TC_CMR0_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define TC_CMR0_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define TC_CMR0_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -/* -------- TC_CV0 : (TC Offset: 0x10) Counter Value (channel = 0) -------- */ -#define TC_CV0_CV (0xffff << 0) /**< \brief (TC_CV0) Counter Value */ -/* -------- TC_RA0 : (TC Offset: 0x14) Register A (channel = 0) -------- */ -#define TC_RA0_RA (0xffff << 0) /**< \brief (TC_RA0) Register A */ -/* -------- TC_RB0 : (TC Offset: 0x18) Register B (channel = 0) -------- */ -#define TC_RB0_RB (0xffff << 0) /**< \brief (TC_RB0) Register B */ -/* -------- TC_RC0 : (TC Offset: 0x1C) Register C (channel = 0) -------- */ -#define TC_RC0_RC (0xffff << 0) /**< \brief (TC_RC0) Register C */ -/* -------- TC_SR0 : (TC Offset: 0x20) Status Register (channel = 0) -------- */ -#define TC_SR0_COVFS (0x1 << 0) /**< \brief (TC_SR0) Counter Overflow Status */ -#define TC_SR0_LOVRS (0x1 << 1) /**< \brief (TC_SR0) Load Overrun Status */ -#define TC_SR0_CPAS (0x1 << 2) /**< \brief (TC_SR0) RA Compare Status */ -#define TC_SR0_CPBS (0x1 << 3) /**< \brief (TC_SR0) RB Compare Status */ -#define TC_SR0_CPCS (0x1 << 4) /**< \brief (TC_SR0) RC Compare Status */ -#define TC_SR0_LDRAS (0x1 << 5) /**< \brief (TC_SR0) RA Loading Status */ -#define TC_SR0_LDRBS (0x1 << 6) /**< \brief (TC_SR0) RB Loading Status */ -#define TC_SR0_ETRGS (0x1 << 7) /**< \brief (TC_SR0) External Trigger Status */ -#define TC_SR0_CLKSTA (0x1 << 16) /**< \brief (TC_SR0) Clock Enabling Status */ -#define TC_SR0_MTIOA (0x1 << 17) /**< \brief (TC_SR0) TIOA Mirror */ -#define TC_SR0_MTIOB (0x1 << 18) /**< \brief (TC_SR0) TIOB Mirror */ -/* -------- TC_IER0 : (TC Offset: 0x24) Interrupt Enable Register (channel = 0) -------- */ -#define TC_IER0_COVFS (0x1 << 0) /**< \brief (TC_IER0) Counter Overflow */ -#define TC_IER0_LOVRS (0x1 << 1) /**< \brief (TC_IER0) Load Overrun */ -#define TC_IER0_CPAS (0x1 << 2) /**< \brief (TC_IER0) RA Compare */ -#define TC_IER0_CPBS (0x1 << 3) /**< \brief (TC_IER0) RB Compare */ -#define TC_IER0_CPCS (0x1 << 4) /**< \brief (TC_IER0) RC Compare */ -#define TC_IER0_LDRAS (0x1 << 5) /**< \brief (TC_IER0) RA Loading */ -#define TC_IER0_LDRBS (0x1 << 6) /**< \brief (TC_IER0) RB Loading */ -#define TC_IER0_ETRGS (0x1 << 7) /**< \brief (TC_IER0) External Trigger */ -/* -------- TC_IDR0 : (TC Offset: 0x28) Interrupt Disable Register (channel = 0) -------- */ -#define TC_IDR0_COVFS (0x1 << 0) /**< \brief (TC_IDR0) Counter Overflow */ -#define TC_IDR0_LOVRS (0x1 << 1) /**< \brief (TC_IDR0) Load Overrun */ -#define TC_IDR0_CPAS (0x1 << 2) /**< \brief (TC_IDR0) RA Compare */ -#define TC_IDR0_CPBS (0x1 << 3) /**< \brief (TC_IDR0) RB Compare */ -#define TC_IDR0_CPCS (0x1 << 4) /**< \brief (TC_IDR0) RC Compare */ -#define TC_IDR0_LDRAS (0x1 << 5) /**< \brief (TC_IDR0) RA Loading */ -#define TC_IDR0_LDRBS (0x1 << 6) /**< \brief (TC_IDR0) RB Loading */ -#define TC_IDR0_ETRGS (0x1 << 7) /**< \brief (TC_IDR0) External Trigger */ -/* -------- TC_IMR0 : (TC Offset: 0x2C) Interrupt Mask Register (channel = 0) -------- */ -#define TC_IMR0_COVFS (0x1 << 0) /**< \brief (TC_IMR0) Counter Overflow */ -#define TC_IMR0_LOVRS (0x1 << 1) /**< \brief (TC_IMR0) Load Overrun */ -#define TC_IMR0_CPAS (0x1 << 2) /**< \brief (TC_IMR0) RA Compare */ -#define TC_IMR0_CPBS (0x1 << 3) /**< \brief (TC_IMR0) RB Compare */ -#define TC_IMR0_CPCS (0x1 << 4) /**< \brief (TC_IMR0) RC Compare */ -#define TC_IMR0_LDRAS (0x1 << 5) /**< \brief (TC_IMR0) RA Loading */ -#define TC_IMR0_LDRBS (0x1 << 6) /**< \brief (TC_IMR0) RB Loading */ -#define TC_IMR0_ETRGS (0x1 << 7) /**< \brief (TC_IMR0) External Trigger */ -/* -------- TC_CCR1 : (TC Offset: 0x40) Channel Control Register (channel = 1) -------- */ -#define TC_CCR1_CLKEN (0x1 << 0) /**< \brief (TC_CCR1) Counter Clock Enable Command */ -#define TC_CCR1_CLKDIS (0x1 << 1) /**< \brief (TC_CCR1) Counter Clock Disable Command */ -#define TC_CCR1_SWTRG (0x1 << 2) /**< \brief (TC_CCR1) Software Trigger Command */ -/* -------- TC_CMR1 : (TC Offset: 0x44) Channel Mode Register (channel = 1) -------- */ -#define TC_CMR1_TCCLKS (0x7 << 0) /**< \brief (TC_CMR1) Clock Selection */ -#define TC_CMR1_CLKI (0x1 << 3) /**< \brief (TC_CMR1) Clock Invert */ -#define TC_CMR1_BURST (0x3 << 4) /**< \brief (TC_CMR1) Burst Signal Selection */ -#define TC_CMR1_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR1) The clock is not gated by an external signal. */ -#define TC_CMR1_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR1) XC0 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR1) XC1 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR1) XC2 is ANDed with the selected clock. */ -#define TC_CMR1_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR1) Counter Clock Stopped with RB Loading */ -#define TC_CMR1_LDBDIS (0x1 << 7) /**< \brief (TC_CMR1) Counter Clock Disable with RB Loading */ -#define TC_CMR1_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR1) External Trigger Edge Selection */ -#define TC_CMR1_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR1) rising edge */ -#define TC_CMR1_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR1) falling edge */ -#define TC_CMR1_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR1) each edge */ -#define TC_CMR1_ABETRG (0x1 << 10) /**< \brief (TC_CMR1) TIOA or TIOB External Trigger Selection */ -#define TC_CMR1_CPCTRG (0x1 << 14) /**< \brief (TC_CMR1) RC Compare Trigger Enable */ -#define TC_CMR1_WAVE (0x1 << 15) /**< \brief (TC_CMR1) */ -#define TC_CMR1_LDRA (0x3 << 16) /**< \brief (TC_CMR1) RA Loading Selection */ -#define TC_CMR1_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR1) each edge of TIOA */ -#define TC_CMR1_LDRB (0x3 << 18) /**< \brief (TC_CMR1) RB Loading Selection */ -#define TC_CMR1_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR1) each edge of TIOA */ -/* -------- TC_CV1 : (TC Offset: 0x50) Counter Value (channel = 1) -------- */ -#define TC_CV1_CV (0xffff << 0) /**< \brief (TC_CV1) Counter Value */ -/* -------- TC_RA1 : (TC Offset: 0x54) Register A (channel = 1) -------- */ -#define TC_RA1_RA (0xffff << 0) /**< \brief (TC_RA1) Register A */ -/* -------- TC_RB1 : (TC Offset: 0x58) Register B (channel = 1) -------- */ -#define TC_RB1_RB (0xffff << 0) /**< \brief (TC_RB1) Register B */ -/* -------- TC_RC1 : (TC Offset: 0x5C) Register C (channel = 1) -------- */ -#define TC_RC1_RC (0xffff << 0) /**< \brief (TC_RC1) Register C */ -/* -------- TC_SR1 : (TC Offset: 0x60) Status Register (channel = 1) -------- */ -#define TC_SR1_COVFS (0x1 << 0) /**< \brief (TC_SR1) Counter Overflow Status */ -#define TC_SR1_LOVRS (0x1 << 1) /**< \brief (TC_SR1) Load Overrun Status */ -#define TC_SR1_CPAS (0x1 << 2) /**< \brief (TC_SR1) RA Compare Status */ -#define TC_SR1_CPBS (0x1 << 3) /**< \brief (TC_SR1) RB Compare Status */ -#define TC_SR1_CPCS (0x1 << 4) /**< \brief (TC_SR1) RC Compare Status */ -#define TC_SR1_LDRAS (0x1 << 5) /**< \brief (TC_SR1) RA Loading Status */ -#define TC_SR1_LDRBS (0x1 << 6) /**< \brief (TC_SR1) RB Loading Status */ -#define TC_SR1_ETRGS (0x1 << 7) /**< \brief (TC_SR1) External Trigger Status */ -#define TC_SR1_CLKSTA (0x1 << 16) /**< \brief (TC_SR1) Clock Enabling Status */ -#define TC_SR1_MTIOA (0x1 << 17) /**< \brief (TC_SR1) TIOA Mirror */ -#define TC_SR1_MTIOB (0x1 << 18) /**< \brief (TC_SR1) TIOB Mirror */ -/* -------- TC_IER1 : (TC Offset: 0x64) Interrupt Enable Register (channel = 1) -------- */ -#define TC_IER1_COVFS (0x1 << 0) /**< \brief (TC_IER1) Counter Overflow */ -#define TC_IER1_LOVRS (0x1 << 1) /**< \brief (TC_IER1) Load Overrun */ -#define TC_IER1_CPAS (0x1 << 2) /**< \brief (TC_IER1) RA Compare */ -#define TC_IER1_CPBS (0x1 << 3) /**< \brief (TC_IER1) RB Compare */ -#define TC_IER1_CPCS (0x1 << 4) /**< \brief (TC_IER1) RC Compare */ -#define TC_IER1_LDRAS (0x1 << 5) /**< \brief (TC_IER1) RA Loading */ -#define TC_IER1_LDRBS (0x1 << 6) /**< \brief (TC_IER1) RB Loading */ -#define TC_IER1_ETRGS (0x1 << 7) /**< \brief (TC_IER1) External Trigger */ -/* -------- TC_IDR1 : (TC Offset: 0x68) Interrupt Disable Register (channel = 1) -------- */ -#define TC_IDR1_COVFS (0x1 << 0) /**< \brief (TC_IDR1) Counter Overflow */ -#define TC_IDR1_LOVRS (0x1 << 1) /**< \brief (TC_IDR1) Load Overrun */ -#define TC_IDR1_CPAS (0x1 << 2) /**< \brief (TC_IDR1) RA Compare */ -#define TC_IDR1_CPBS (0x1 << 3) /**< \brief (TC_IDR1) RB Compare */ -#define TC_IDR1_CPCS (0x1 << 4) /**< \brief (TC_IDR1) RC Compare */ -#define TC_IDR1_LDRAS (0x1 << 5) /**< \brief (TC_IDR1) RA Loading */ -#define TC_IDR1_LDRBS (0x1 << 6) /**< \brief (TC_IDR1) RB Loading */ -#define TC_IDR1_ETRGS (0x1 << 7) /**< \brief (TC_IDR1) External Trigger */ -/* -------- TC_IMR1 : (TC Offset: 0x6C) Interrupt Mask Register (channel = 1) -------- */ -#define TC_IMR1_COVFS (0x1 << 0) /**< \brief (TC_IMR1) Counter Overflow */ -#define TC_IMR1_LOVRS (0x1 << 1) /**< \brief (TC_IMR1) Load Overrun */ -#define TC_IMR1_CPAS (0x1 << 2) /**< \brief (TC_IMR1) RA Compare */ -#define TC_IMR1_CPBS (0x1 << 3) /**< \brief (TC_IMR1) RB Compare */ -#define TC_IMR1_CPCS (0x1 << 4) /**< \brief (TC_IMR1) RC Compare */ -#define TC_IMR1_LDRAS (0x1 << 5) /**< \brief (TC_IMR1) RA Loading */ -#define TC_IMR1_LDRBS (0x1 << 6) /**< \brief (TC_IMR1) RB Loading */ -#define TC_IMR1_ETRGS (0x1 << 7) /**< \brief (TC_IMR1) External Trigger */ -/* -------- TC_CCR2 : (TC Offset: 0x80) Channel Control Register (channel = 2) -------- */ -#define TC_CCR2_CLKEN (0x1 << 0) /**< \brief (TC_CCR2) Counter Clock Enable Command */ -#define TC_CCR2_CLKDIS (0x1 << 1) /**< \brief (TC_CCR2) Counter Clock Disable Command */ -#define TC_CCR2_SWTRG (0x1 << 2) /**< \brief (TC_CCR2) Software Trigger Command */ -/* -------- TC_CMR2 : (TC Offset: 0x84) Channel Mode Register (channel = 2) -------- */ -#define TC_CMR2_TCCLKS (0x7 << 0) /**< \brief (TC_CMR2) Clock Selection */ -#define TC_CMR2_CLKI (0x1 << 3) /**< \brief (TC_CMR2) Clock Invert */ -#define TC_CMR2_BURST (0x3 << 4) /**< \brief (TC_CMR2) Burst Signal Selection */ -#define TC_CMR2_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR2) The clock is not gated by an external signal. */ -#define TC_CMR2_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR2) XC0 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR2) XC1 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR2) XC2 is ANDed with the selected clock. */ -#define TC_CMR2_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR2) Counter Clock Stopped with RB Loading */ -#define TC_CMR2_LDBDIS (0x1 << 7) /**< \brief (TC_CMR2) Counter Clock Disable with RB Loading */ -#define TC_CMR2_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR2) External Trigger Edge Selection */ -#define TC_CMR2_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR2) rising edge */ -#define TC_CMR2_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR2) falling edge */ -#define TC_CMR2_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR2) each edge */ -#define TC_CMR2_ABETRG (0x1 << 10) /**< \brief (TC_CMR2) TIOA or TIOB External Trigger Selection */ -#define TC_CMR2_CPCTRG (0x1 << 14) /**< \brief (TC_CMR2) RC Compare Trigger Enable */ -#define TC_CMR2_WAVE (0x1 << 15) /**< \brief (TC_CMR2) */ -#define TC_CMR2_LDRA (0x3 << 16) /**< \brief (TC_CMR2) RA Loading Selection */ -#define TC_CMR2_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR2) each edge of TIOA */ -#define TC_CMR2_LDRB (0x3 << 18) /**< \brief (TC_CMR2) RB Loading Selection */ -#define TC_CMR2_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR2) each edge of TIOA */ -/* -------- TC_CV2 : (TC Offset: 0x90) Counter Value (channel = 2) -------- */ -#define TC_CV2_CV (0xffff << 0) /**< \brief (TC_CV2) Counter Value */ -/* -------- TC_RA2 : (TC Offset: 0x94) Register A (channel = 2) -------- */ -#define TC_RA2_RA (0xffff << 0) /**< \brief (TC_RA2) Register A */ -/* -------- TC_RB2 : (TC Offset: 0x98) Register B (channel = 2) -------- */ -#define TC_RB2_RB (0xffff << 0) /**< \brief (TC_RB2) Register B */ -/* -------- TC_RC2 : (TC Offset: 0x9C) Register C (channel = 2) -------- */ -#define TC_RC2_RC (0xffff << 0) /**< \brief (TC_RC2) Register C */ -/* -------- TC_SR2 : (TC Offset: 0xA0) Status Register (channel = 2) -------- */ -#define TC_SR2_COVFS (0x1 << 0) /**< \brief (TC_SR2) Counter Overflow Status */ -#define TC_SR2_LOVRS (0x1 << 1) /**< \brief (TC_SR2) Load Overrun Status */ -#define TC_SR2_CPAS (0x1 << 2) /**< \brief (TC_SR2) RA Compare Status */ -#define TC_SR2_CPBS (0x1 << 3) /**< \brief (TC_SR2) RB Compare Status */ -#define TC_SR2_CPCS (0x1 << 4) /**< \brief (TC_SR2) RC Compare Status */ -#define TC_SR2_LDRAS (0x1 << 5) /**< \brief (TC_SR2) RA Loading Status */ -#define TC_SR2_LDRBS (0x1 << 6) /**< \brief (TC_SR2) RB Loading Status */ -#define TC_SR2_ETRGS (0x1 << 7) /**< \brief (TC_SR2) External Trigger Status */ -#define TC_SR2_CLKSTA (0x1 << 16) /**< \brief (TC_SR2) Clock Enabling Status */ -#define TC_SR2_MTIOA (0x1 << 17) /**< \brief (TC_SR2) TIOA Mirror */ -#define TC_SR2_MTIOB (0x1 << 18) /**< \brief (TC_SR2) TIOB Mirror */ -/* -------- TC_IER2 : (TC Offset: 0xA4) Interrupt Enable Register (channel = 2) -------- */ -#define TC_IER2_COVFS (0x1 << 0) /**< \brief (TC_IER2) Counter Overflow */ -#define TC_IER2_LOVRS (0x1 << 1) /**< \brief (TC_IER2) Load Overrun */ -#define TC_IER2_CPAS (0x1 << 2) /**< \brief (TC_IER2) RA Compare */ -#define TC_IER2_CPBS (0x1 << 3) /**< \brief (TC_IER2) RB Compare */ -#define TC_IER2_CPCS (0x1 << 4) /**< \brief (TC_IER2) RC Compare */ -#define TC_IER2_LDRAS (0x1 << 5) /**< \brief (TC_IER2) RA Loading */ -#define TC_IER2_LDRBS (0x1 << 6) /**< \brief (TC_IER2) RB Loading */ -#define TC_IER2_ETRGS (0x1 << 7) /**< \brief (TC_IER2) External Trigger */ -/* -------- TC_IDR2 : (TC Offset: 0xA8) Interrupt Disable Register (channel = 2) -------- */ -#define TC_IDR2_COVFS (0x1 << 0) /**< \brief (TC_IDR2) Counter Overflow */ -#define TC_IDR2_LOVRS (0x1 << 1) /**< \brief (TC_IDR2) Load Overrun */ -#define TC_IDR2_CPAS (0x1 << 2) /**< \brief (TC_IDR2) RA Compare */ -#define TC_IDR2_CPBS (0x1 << 3) /**< \brief (TC_IDR2) RB Compare */ -#define TC_IDR2_CPCS (0x1 << 4) /**< \brief (TC_IDR2) RC Compare */ -#define TC_IDR2_LDRAS (0x1 << 5) /**< \brief (TC_IDR2) RA Loading */ -#define TC_IDR2_LDRBS (0x1 << 6) /**< \brief (TC_IDR2) RB Loading */ -#define TC_IDR2_ETRGS (0x1 << 7) /**< \brief (TC_IDR2) External Trigger */ -/* -------- TC_IMR2 : (TC Offset: 0xAC) Interrupt Mask Register (channel = 2) -------- */ -#define TC_IMR2_COVFS (0x1 << 0) /**< \brief (TC_IMR2) Counter Overflow */ -#define TC_IMR2_LOVRS (0x1 << 1) /**< \brief (TC_IMR2) Load Overrun */ -#define TC_IMR2_CPAS (0x1 << 2) /**< \brief (TC_IMR2) RA Compare */ -#define TC_IMR2_CPBS (0x1 << 3) /**< \brief (TC_IMR2) RB Compare */ -#define TC_IMR2_CPCS (0x1 << 4) /**< \brief (TC_IMR2) RC Compare */ -#define TC_IMR2_LDRAS (0x1 << 5) /**< \brief (TC_IMR2) RA Loading */ -#define TC_IMR2_LDRBS (0x1 << 6) /**< \brief (TC_IMR2) RB Loading */ -#define TC_IMR2_ETRGS (0x1 << 7) /**< \brief (TC_IMR2) External Trigger */ -/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ -#define TC_BCR_SYNC (0x1 << 0) /**< \brief (TC_BCR) Synchro Command */ -/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ -#define TC_BMR_TC0XC0S (0x3 << 0) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ -#define TC_BMR_TC0XC0S_TCLK0 (0x0 << 0) /**< \brief (TC_BMR) TCLK0 */ -#define TC_BMR_TC0XC0S_NONE (0x1 << 0) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC0XC0S_TIOA1 (0x2 << 0) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_TC0XC0S_TIOA2 (0x3 << 0) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC1XC1S (0x3 << 2) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ -#define TC_BMR_TC1XC1S_TCLK1 (0x0 << 2) /**< \brief (TC_BMR) TCLK1 */ -#define TC_BMR_TC1XC1S_NONE (0x1 << 2) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC1XC1S_TIOA0 (0x2 << 2) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC1XC1S_TIOA2 (0x3 << 2) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC2XC2S (0x3 << 4) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ -#define TC_BMR_TC2XC2S_TCLK2 (0x0 << 4) /**< \brief (TC_BMR) TCLK2 */ -#define TC_BMR_TC2XC2S_NONE (0x1 << 4) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC2XC2S_TIOA0 (0x2 << 4) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC2XC2S_TIOA1 (0x3 << 4) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_QDEN (0x1 << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ -#define TC_BMR_POSEN (0x1 << 9) /**< \brief (TC_BMR) POSition ENabled */ -#define TC_BMR_SPEEDEN (0x1 << 10) /**< \brief (TC_BMR) SPEED ENabled */ -#define TC_BMR_QDTRANS (0x1 << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ -#define TC_BMR_EDGPHA (0x1 << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ -#define TC_BMR_INVA (0x1 << 13) /**< \brief (TC_BMR) INVerted phA */ -#define TC_BMR_INVB (0x1 << 14) /**< \brief (TC_BMR) INVerted phB */ -#define TC_BMR_INVIDX (0x1 << 15) /**< \brief (TC_BMR) INVerted InDeX */ -#define TC_BMR_SWAP (0x1 << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ -#define TC_BMR_IDXPHB (0x1 << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ -#define TC_BMR_FILTER (0x1 << 19) /**< \brief (TC_BMR) */ -#define TC_BMR_MAXFILT (0x3f << 20) /**< \brief (TC_BMR) MAXimum FILTer */ -/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ -#define TC_QIER_IDX (0x1 << 0) /**< \brief (TC_QIER) InDeX */ -#define TC_QIER_DIRCHG (0x1 << 1) /**< \brief (TC_QIER) DIRection CHanGe */ -#define TC_QIER_QERR (0x1 << 2) /**< \brief (TC_QIER) Quadrature ERRor */ -/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ -#define TC_QIDR_IDX (0x1 << 0) /**< \brief (TC_QIDR) InDeX */ -#define TC_QIDR_DIRCHG (0x1 << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ -#define TC_QIDR_QERR (0x1 << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ -/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ -#define TC_QIMR_IDX (0x1 << 0) /**< \brief (TC_QIMR) InDeX */ -#define TC_QIMR_DIRCHG (0x1 << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ -#define TC_QIMR_QERR (0x1 << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ -/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ -#define TC_QISR_IDX (0x1 << 0) /**< \brief (TC_QISR) InDeX */ -#define TC_QISR_DIRCHG (0x1 << 1) /**< \brief (TC_QISR) DIRection CHanGe */ -#define TC_QISR_QERR (0x1 << 2) /**< \brief (TC_QISR) Quadrature ERRor */ -#define TC_QISR_DIR (0x1 << 8) /**< \brief (TC_QISR) Direction */ -/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ -#define TC_FMR_ENCF0 (0x1 << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */ -#define TC_FMR_ENCF1 (0x1 << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */ -/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */ -#define TC_WPMR_WPEN (0x1 << 0) /**< \brief (TC_WPMR) Write Protect Enable */ -#define TC_WPMR_WPKEY (0xffffff << 8) /**< \brief (TC_WPMR) Write Protect KEY */ -/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ -#define TC_VER_VERSION (0xfff << 0) /**< \brief (TC_VER) */ -#define TC_VER_MFN (0x7 << 16) /**< \brief (TC_VER) */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Two-wire Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_TWI Two-wire Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Twi hardware registers */ -typedef struct { - WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ - RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ - RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ - RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ - RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ - RwReg Reserved1[3]; - RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ - WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ - WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ - RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ - RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ - WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ - RwReg Reserved2[50]; - RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ - RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ - RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ - RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ - RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ - RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ - RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ - RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ - WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ - RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ -} Twi; -#endif /* __ASSEMBLY__ */ -/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ -#define TWI_CR_START (0x1 << 0) /**< \brief (TWI_CR) Send a START Condition */ -#define TWI_CR_STOP (0x1 << 1) /**< \brief (TWI_CR) Send a STOP Condition */ -#define TWI_CR_MSEN (0x1 << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ -#define TWI_CR_MSDIS (0x1 << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ -#define TWI_CR_SVEN (0x1 << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ -#define TWI_CR_SVDIS (0x1 << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ -#define TWI_CR_QUICK (0x1 << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ -#define TWI_CR_SWRST (0x1 << 7) /**< \brief (TWI_CR) Software Reset */ -/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ -#define TWI_MMR_IADRSZ (0x3 << 8) /**< \brief (TWI_MMR) Internal Device Address Size */ -#define TWI_MMR_IADRSZ_NO (0x0 << 8) /**< \brief (TWI_MMR) No internal device address */ -#define TWI_MMR_IADRSZ_1_BYTE (0x1 << 8) /**< \brief (TWI_MMR) One-byte internal device address */ -#define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ -#define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ -#define TWI_MMR_MREAD (0x1 << 12) /**< \brief (TWI_MMR) Master Read Direction */ -#define TWI_MMR_DADR (0x7f << 16) /**< \brief (TWI_MMR) Device Address */ -/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ -#define TWI_SMR_SADR (0x7f << 16) /**< \brief (TWI_SMR) Slave Address */ -/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ -#define TWI_IADR_IADR (0xffffff << 0) /**< \brief (TWI_IADR) Internal Address */ -/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ -#define TWI_CWGR_CLDIV (0xff << 0) /**< \brief (TWI_CWGR) Clock Low Divider */ -#define TWI_CWGR_CHDIV (0xff << 8) /**< \brief (TWI_CWGR) Clock High Divider */ -#define TWI_CWGR_CKDIV (0x7 << 16) /**< \brief (TWI_CWGR) Clock Divider */ -/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ -#define TWI_SR_TXCOMP (0x1 << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ -#define TWI_SR_RXRDY (0x1 << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ -#define TWI_SR_TXRDY (0x1 << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ -#define TWI_SR_SVREAD (0x1 << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ -#define TWI_SR_SVACC (0x1 << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ -#define TWI_SR_GACC (0x1 << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ -#define TWI_SR_OVRE (0x1 << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ -#define TWI_SR_NACK (0x1 << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ -#define TWI_SR_ARBLST (0x1 << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ -#define TWI_SR_SCLWS (0x1 << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ -#define TWI_SR_EOSACC (0x1 << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ -#define TWI_SR_ENDRX (0x1 << 12) /**< \brief (TWI_SR) End of RX buffer */ -#define TWI_SR_ENDTX (0x1 << 13) /**< \brief (TWI_SR) End of TX buffer */ -#define TWI_SR_RXBUFF (0x1 << 14) /**< \brief (TWI_SR) RX Buffer Full */ -#define TWI_SR_TXBUFE (0x1 << 15) /**< \brief (TWI_SR) TX Buffer Empty */ -/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ -#define TWI_IER_TXCOMP (0x1 << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ -#define TWI_IER_RXRDY (0x1 << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ -#define TWI_IER_TXRDY (0x1 << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ -#define TWI_IER_SVACC (0x1 << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ -#define TWI_IER_GACC (0x1 << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ -#define TWI_IER_OVRE (0x1 << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ -#define TWI_IER_NACK (0x1 << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ -#define TWI_IER_ARBLST (0x1 << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ -#define TWI_IER_SCL_WS (0x1 << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ -#define TWI_IER_EOSACC (0x1 << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ -#define TWI_IER_ENDRX (0x1 << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ -#define TWI_IER_ENDTX (0x1 << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ -#define TWI_IER_RXBUFF (0x1 << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ -#define TWI_IER_TXBUFE (0x1 << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ -#define TWI_IDR_TXCOMP (0x1 << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ -#define TWI_IDR_RXRDY (0x1 << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ -#define TWI_IDR_TXRDY (0x1 << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ -#define TWI_IDR_SVACC (0x1 << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ -#define TWI_IDR_GACC (0x1 << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ -#define TWI_IDR_OVRE (0x1 << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ -#define TWI_IDR_NACK (0x1 << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ -#define TWI_IDR_ARBLST (0x1 << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ -#define TWI_IDR_SCL_WS (0x1 << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ -#define TWI_IDR_EOSACC (0x1 << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ -#define TWI_IDR_ENDRX (0x1 << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ -#define TWI_IDR_ENDTX (0x1 << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ -#define TWI_IDR_RXBUFF (0x1 << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ -#define TWI_IDR_TXBUFE (0x1 << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ -#define TWI_IMR_TXCOMP (0x1 << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ -#define TWI_IMR_RXRDY (0x1 << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ -#define TWI_IMR_TXRDY (0x1 << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ -#define TWI_IMR_SVACC (0x1 << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ -#define TWI_IMR_GACC (0x1 << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ -#define TWI_IMR_OVRE (0x1 << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ -#define TWI_IMR_NACK (0x1 << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ -#define TWI_IMR_ARBLST (0x1 << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ -#define TWI_IMR_SCL_WS (0x1 << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ -#define TWI_IMR_EOSACC (0x1 << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ -#define TWI_IMR_ENDRX (0x1 << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ -#define TWI_IMR_ENDTX (0x1 << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ -#define TWI_IMR_RXBUFF (0x1 << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ -#define TWI_IMR_TXBUFE (0x1 << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ -#define TWI_RHR_RXDATA (0xff << 0) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ -/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ -#define TWI_THR_TXDATA (0xff << 0) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ -/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ -#define TWI_RPR_RXPTR (0xffffffff << 0) /**< \brief (TWI_RPR) Receive Pointer Register */ -/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ -#define TWI_RCR_RXCTR (0xffff << 0) /**< \brief (TWI_RCR) Receive Counter Register */ -/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ -#define TWI_TPR_TXPTR (0xffffffff << 0) /**< \brief (TWI_TPR) Transmit Counter Register */ -/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ -#define TWI_TCR_TXCTR (0xffff << 0) /**< \brief (TWI_TCR) Transmit Counter Register */ -/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ -#define TWI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (TWI_RNPR) Receive Next Pointer */ -/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ -#define TWI_RNCR_RXNCTR (0xffff << 0) /**< \brief (TWI_RNCR) Receive Next Counter */ -/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define TWI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (TWI_TNPR) Transmit Next Pointer */ -/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define TWI_TNCR_TXNCTR (0xffff << 0) /**< \brief (TWI_TNCR) Transmit Counter Next */ -/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ -#define TWI_PTCR_RXTEN (0x1 << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ -#define TWI_PTCR_RXTDIS (0x1 << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ -#define TWI_PTCR_TXTEN (0x1 << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ -#define TWI_PTCR_TXTDIS (0x1 << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ -/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ -#define TWI_PTSR_RXTEN (0x1 << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ -#define TWI_PTSR_TXTEN (0x1 << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_UART Universal Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Uart hardware registers */ -typedef struct { - WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ - RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ - WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ - WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ - RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ - RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ - RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ - WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ - RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ - RwReg Reserved1[55]; - RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ - RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ - RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ - RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ - RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ - RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ - RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ - RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ - WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ - RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ -} Uart; -#endif /* __ASSEMBLY__ */ -/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ -#define UART_CR_RSTRX (0x1 << 2) /**< \brief (UART_CR) Reset Receiver */ -#define UART_CR_RSTTX (0x1 << 3) /**< \brief (UART_CR) Reset Transmitter */ -#define UART_CR_RXEN (0x1 << 4) /**< \brief (UART_CR) Receiver Enable */ -#define UART_CR_RXDIS (0x1 << 5) /**< \brief (UART_CR) Receiver Disable */ -#define UART_CR_TXEN (0x1 << 6) /**< \brief (UART_CR) Transmitter Enable */ -#define UART_CR_TXDIS (0x1 << 7) /**< \brief (UART_CR) Transmitter Disable */ -#define UART_CR_RSTSTA (0x1 << 8) /**< \brief (UART_CR) Reset Status Bits */ -/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ -#define UART_MR_PAR (0x7 << 9) /**< \brief (UART_MR) Parity Type */ -#define UART_MR_CHMODE (0x3 << 14) /**< \brief (UART_MR) Channel Mode */ -/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ -#define UART_IER_RXRDY (0x1 << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ -#define UART_IER_TXRDY (0x1 << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ -#define UART_IER_ENDRX (0x1 << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ -#define UART_IER_ENDTX (0x1 << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ -#define UART_IER_OVRE (0x1 << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ -#define UART_IER_FRAME (0x1 << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ -#define UART_IER_PARE (0x1 << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ -#define UART_IER_TXEMPTY (0x1 << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ -#define UART_IER_TXBUFE (0x1 << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ -#define UART_IER_RXBUFF (0x1 << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ -/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ -#define UART_IDR_RXRDY (0x1 << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ -#define UART_IDR_TXRDY (0x1 << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ -#define UART_IDR_ENDRX (0x1 << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ -#define UART_IDR_ENDTX (0x1 << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ -#define UART_IDR_OVRE (0x1 << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ -#define UART_IDR_FRAME (0x1 << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ -#define UART_IDR_PARE (0x1 << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ -#define UART_IDR_TXEMPTY (0x1 << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ -#define UART_IDR_TXBUFE (0x1 << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ -#define UART_IDR_RXBUFF (0x1 << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ -/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ -#define UART_IMR_RXRDY (0x1 << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ -#define UART_IMR_TXRDY (0x1 << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ -#define UART_IMR_ENDRX (0x1 << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ -#define UART_IMR_ENDTX (0x1 << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ -#define UART_IMR_OVRE (0x1 << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ -#define UART_IMR_FRAME (0x1 << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ -#define UART_IMR_PARE (0x1 << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ -#define UART_IMR_TXEMPTY (0x1 << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ -#define UART_IMR_TXBUFE (0x1 << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ -#define UART_IMR_RXBUFF (0x1 << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ -/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ -#define UART_SR_RXRDY (0x1 << 0) /**< \brief (UART_SR) Receiver Ready */ -#define UART_SR_TXRDY (0x1 << 1) /**< \brief (UART_SR) Transmitter Ready */ -#define UART_SR_ENDRX (0x1 << 3) /**< \brief (UART_SR) End of Receiver Transfer */ -#define UART_SR_ENDTX (0x1 << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ -#define UART_SR_OVRE (0x1 << 5) /**< \brief (UART_SR) Overrun Error */ -#define UART_SR_FRAME (0x1 << 6) /**< \brief (UART_SR) Framing Error */ -#define UART_SR_PARE (0x1 << 7) /**< \brief (UART_SR) Parity Error */ -#define UART_SR_TXEMPTY (0x1 << 9) /**< \brief (UART_SR) Transmitter Empty */ -#define UART_SR_TXBUFE (0x1 << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ -#define UART_SR_RXBUFF (0x1 << 12) /**< \brief (UART_SR) Receive Buffer Full */ -/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ -#define UART_RHR_RXCHR (0xff << 0) /**< \brief (UART_RHR) Received Character */ -/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ -#define UART_THR_TXCHR (0xff << 0) /**< \brief (UART_THR) Character to be Transmitted */ -/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define UART_BRGR_CD (0xffff << 0) /**< \brief (UART_BRGR) Clock Divisor */ -/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ -#define UART_RPR_RXPTR (0xffffffff << 0) /**< \brief (UART_RPR) Receive Pointer Register */ -/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ -#define UART_RCR_RXCTR (0xffff << 0) /**< \brief (UART_RCR) Receive Counter Register */ -/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ -#define UART_TPR_TXPTR (0xffffffff << 0) /**< \brief (UART_TPR) Transmit Counter Register */ -/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ -#define UART_TCR_TXCTR (0xffff << 0) /**< \brief (UART_TCR) Transmit Counter Register */ -/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ -#define UART_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (UART_RNPR) Receive Next Pointer */ -/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ -#define UART_RNCR_RXNCTR (0xffff << 0) /**< \brief (UART_RNCR) Receive Next Counter */ -/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define UART_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (UART_TNPR) Transmit Next Pointer */ -/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define UART_TNCR_TXNCTR (0xffff << 0) /**< \brief (UART_TNCR) Transmit Counter Next */ -/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ -#define UART_PTCR_RXTEN (0x1 << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ -#define UART_PTCR_RXTDIS (0x1 << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ -#define UART_PTCR_TXTEN (0x1 << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ -#define UART_PTCR_TXTDIS (0x1 << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ -/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ -#define UART_PTSR_RXTEN (0x1 << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ -#define UART_PTSR_TXTEN (0x1 << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR USB Device Port */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_UDP USB Device Port */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Udp hardware registers */ -typedef struct { - RoReg UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */ - RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */ - RwReg UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */ - RwReg Reserved1[1]; - WoReg UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */ - WoReg UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */ - RoReg UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */ - RoReg UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */ - WoReg UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */ - RwReg Reserved2[1]; - RwReg UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */ - RwReg Reserved3[1]; - RwReg UDP_CSR[8]; /**< \brief (Udp Offset: 0x30) Endpoint Control and Status Register (ept_num = 0) */ - RwReg UDP_FDR[8]; /**< \brief (Udp Offset: 0x50) Endpoint FIFO Data Register (ept_num = 0) */ - RwReg Reserved4[1]; - RwReg UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */ -} Udp; -#endif /* __ASSEMBLY__ */ -/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */ -#define UDP_FRM_NUM_FRM_NUM (0x7ff << 0) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */ -#define UDP_FRM_NUM_FRM_ERR (0x1 << 16) /**< \brief (UDP_FRM_NUM) Frame Error */ -#define UDP_FRM_NUM_FRM_OK (0x1 << 17) /**< \brief (UDP_FRM_NUM) Frame OK */ -/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */ -#define UDP_GLB_STAT_FADDEN (0x1 << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */ -#define UDP_GLB_STAT_CONFG (0x1 << 1) /**< \brief (UDP_GLB_STAT) Configured */ -#define UDP_GLB_STAT_ESR (0x1 << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */ -#define UDP_GLB_STAT_RSMINPR (0x1 << 3) /**< \brief (UDP_GLB_STAT) */ -#define UDP_GLB_STAT_RMWUPE (0x1 << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */ -/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */ -#define UDP_FADDR_FADD (0x7f << 0) /**< \brief (UDP_FADDR) Function Address Value */ -#define UDP_FADDR_FEN (0x1 << 8) /**< \brief (UDP_FADDR) Function Enable */ -/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */ -#define UDP_IER_EP0INT (0x1 << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */ -#define UDP_IER_EP1INT (0x1 << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */ -#define UDP_IER_EP2INT (0x1 << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */ -#define UDP_IER_EP3INT (0x1 << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */ -#define UDP_IER_EP4INT (0x1 << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */ -#define UDP_IER_EP5INT (0x1 << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */ -#define UDP_IER_EP6INT (0x1 << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */ -#define UDP_IER_EP7INT (0x1 << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */ -#define UDP_IER_RXSUSP (0x1 << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */ -#define UDP_IER_RXRSM (0x1 << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */ -#define UDP_IER_EXTRSM (0x1 << 10) /**< \brief (UDP_IER) */ -#define UDP_IER_SOFINT (0x1 << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */ -#define UDP_IER_WAKEUP (0x1 << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */ -/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */ -#define UDP_IDR_EP0INT (0x1 << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */ -#define UDP_IDR_EP1INT (0x1 << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */ -#define UDP_IDR_EP2INT (0x1 << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */ -#define UDP_IDR_EP3INT (0x1 << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */ -#define UDP_IDR_EP4INT (0x1 << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */ -#define UDP_IDR_EP5INT (0x1 << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */ -#define UDP_IDR_EP6INT (0x1 << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */ -#define UDP_IDR_EP7INT (0x1 << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */ -#define UDP_IDR_RXSUSP (0x1 << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */ -#define UDP_IDR_RXRSM (0x1 << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */ -#define UDP_IDR_EXTRSM (0x1 << 10) /**< \brief (UDP_IDR) */ -#define UDP_IDR_SOFINT (0x1 << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */ -#define UDP_IDR_WAKEUP (0x1 << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */ -/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */ -#define UDP_IMR_EP0INT (0x1 << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */ -#define UDP_IMR_EP1INT (0x1 << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */ -#define UDP_IMR_EP2INT (0x1 << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */ -#define UDP_IMR_EP3INT (0x1 << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */ -#define UDP_IMR_EP4INT (0x1 << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */ -#define UDP_IMR_EP5INT (0x1 << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */ -#define UDP_IMR_EP6INT (0x1 << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */ -#define UDP_IMR_EP7INT (0x1 << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */ -#define UDP_IMR_RXSUSP (0x1 << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */ -#define UDP_IMR_RXRSM (0x1 << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */ -#define UDP_IMR_EXTRSM (0x1 << 10) /**< \brief (UDP_IMR) */ -#define UDP_IMR_SOFINT (0x1 << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */ -#define UDP_IMR_BIT12 (0x1 << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */ -#define UDP_IMR_WAKEUP (0x1 << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */ -/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */ -#define UDP_ISR_EP0INT (0x1 << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */ -#define UDP_ISR_EP1INT (0x1 << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */ -#define UDP_ISR_EP2INT (0x1 << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */ -#define UDP_ISR_EP3INT (0x1 << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */ -#define UDP_ISR_EP4INT (0x1 << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */ -#define UDP_ISR_EP5INT (0x1 << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */ -#define UDP_ISR_EP6INT (0x1 << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */ -#define UDP_ISR_EP7INT (0x1 << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */ -#define UDP_ISR_RXSUSP (0x1 << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */ -#define UDP_ISR_RXRSM (0x1 << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -#define UDP_ISR_EXTRSM (0x1 << 10) /**< \brief (UDP_ISR) */ -#define UDP_ISR_SOFINT (0x1 << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */ -#define UDP_ISR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */ -#define UDP_ISR_WAKEUP (0x1 << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */ -#define UDP_ICR_RXSUSP (0x1 << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */ -#define UDP_ICR_RXRSM (0x1 << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */ -#define UDP_ICR_EXTRSM (0x1 << 10) /**< \brief (UDP_ICR) */ -#define UDP_ICR_SOFINT (0x1 << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */ -#define UDP_ICR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */ -#define UDP_ICR_WAKEUP (0x1 << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */ -/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */ -#define UDP_RST_EP_EP0 (0x1 << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */ -#define UDP_RST_EP_EP1 (0x1 << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */ -#define UDP_RST_EP_EP2 (0x1 << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */ -#define UDP_RST_EP_EP3 (0x1 << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */ -#define UDP_RST_EP_EP4 (0x1 << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */ -#define UDP_RST_EP_EP5 (0x1 << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */ -#define UDP_RST_EP_EP6 (0x1 << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */ -#define UDP_RST_EP_EP7 (0x1 << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */ -/* -------- UDP_CSR[8] : (UDP Offset: 0x2C) Endpoint Control and Status Register (ept_num = 0) -------- */ -#define UDP_CSR_TXCOMP (0x1 << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */ -#define UDP_CSR_RX_DATA_BK0 (0x1 << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */ -#define UDP_CSR_RXSETUP (0x1 << 2) /**< \brief (UDP_CSR[8]) Received Setup */ -#define UDP_CSR_STALLSENTISOERROR (0x1 << 3) /**< \brief (UDP_CSR[8]) */ -#define UDP_CSR_TXPKTRDY (0x1 << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */ -#define UDP_CSR_FORCESTALL (0x1 << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */ -#define UDP_CSR_RX_DATA_BK1 (0x1 << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */ -#define UDP_CSR_DIR (0x1 << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */ -#define UDP_CSR_EPTYPE (0x7 << 8) /**< \brief (UDP_CSR[8]) Endpoint Type */ -#define UDP_CSR_EPTYPE_CTRL (0x0 << 8) /**< \brief (UDP_CSR[8]) Control */ -#define UDP_CSR_EPTYPE_ISO_OUT (0x1 << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */ -#define UDP_CSR_EPTYPE_BULK_OUT (0x2 << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */ -#define UDP_CSR_EPTYPE_INT_OUT (0x3 << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */ -#define UDP_CSR_EPTYPE_ISO_IN (0x5 << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */ -#define UDP_CSR_EPTYPE_BULK_IN (0x6 << 8) /**< \brief (UDP_CSR[8]) Bulk IN */ -#define UDP_CSR_EPTYPE_INT_IN (0x7 << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */ -#define UDP_CSR_DTGLE (0x1 << 11) /**< \brief (UDP_CSR[8]) Data Toggle */ -#define UDP_CSR_EPEDS (0x1 << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */ -#define UDP_CSR_RXBYTECNT (0x7ff << 16) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */ -/* -------- UDP_FDR[8] : (UDP Offset: 0x4C) Endpoint FIFO Data Register (ept_num = 0) -------- */ -#define UDP_FDR_FIFO_DATA (0xff << 0) /**< \brief (UDP_FDR[8]) FIFO Data Value */ -/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */ -#define UDP_TXVC_TXVDIS (0x1 << 8) /**< \brief (UDP_TXVC) Transceiver Disable */ -#define UDP_TXVC_PUON (0x1 << 9) /**< \brief (UDP_TXVC) Pullup On */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_USART Universal Synchronous Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Usart hardware registers */ -typedef struct { - WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ - RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ - WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ - WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ - RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ - RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ - RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ - WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ - RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ - RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ - RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ - RwReg Reserved1[5]; - RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ - RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ - RwReg Reserved2[1]; - RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ - RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ - RwReg Reserved3[36]; - RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */ - RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved4[4]; - RoReg US_VERSION; /**< \brief (Usart Offset: 0xFC) Version Register */ - RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ - RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ - RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ - RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ - RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ - RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ - RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ - RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ - WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ - RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ -} Usart; -#endif /* __ASSEMBLY__ */ -/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ -#define US_CR_RSTRX (0x1 << 2) /**< \brief (US_CR) Reset Receiver */ -#define US_CR_RSTTX (0x1 << 3) /**< \brief (US_CR) Reset Transmitter */ -#define US_CR_RXEN (0x1 << 4) /**< \brief (US_CR) Receiver Enable */ -#define US_CR_RXDIS (0x1 << 5) /**< \brief (US_CR) Receiver Disable */ -#define US_CR_TXEN (0x1 << 6) /**< \brief (US_CR) Transmitter Enable */ -#define US_CR_TXDIS (0x1 << 7) /**< \brief (US_CR) Transmitter Disable */ -#define US_CR_RSTSTA (0x1 << 8) /**< \brief (US_CR) Reset Status Bits */ -#define US_CR_STTBRK (0x1 << 9) /**< \brief (US_CR) Start Break */ -#define US_CR_STPBRK (0x1 << 10) /**< \brief (US_CR) Stop Break */ -#define US_CR_STTTO (0x1 << 11) /**< \brief (US_CR) Start Time-out */ -#define US_CR_SENDA (0x1 << 12) /**< \brief (US_CR) Send Address */ -#define US_CR_RSTIT (0x1 << 13) /**< \brief (US_CR) Reset Iterations */ -#define US_CR_RSTNACK (0x1 << 14) /**< \brief (US_CR) Reset Non Acknowledge */ -#define US_CR_RETTO (0x1 << 15) /**< \brief (US_CR) Rearm Time-out */ -#define US_CR_DTREN (0x1 << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ -#define US_CR_DTRDIS (0x1 << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ -#define US_CR_RTSEN__FCS (0x1 << 18) /**< \brief (US_CR) Request to Send Enable/Force SPI Chip Select */ -#define US_CR_RTSDIS__RCS (0x1 << 19) /**< \brief (US_CR) Request to Send Disable/Release SPI Chip Select */ -/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ -#define US_MR_USART_MODE (0xf << 0) /**< \brief (US_MR) */ -#define US_MR_USART_MODE_NORMAL (0x0) /**< (USART) Normal*/ -#define US_MR_USART_MODE_RS485 (0x1) /**< (USART) RS485*/ -#define US_MR_USART_MODE_HWHSH (0x2) /**< (USART) Hardware Handshaking*/ -#define US_MR_USART_MODE_ISO7816_0 (0x4) /**< (USART) ISO7816 protocol: T = 0*/ -#define US_MR_USART_MODE_ISO7816_1 (0x6) /**< (USART) ISO7816 protocol: T = 1*/ -#define US_MR_USART_MODE_IRDA (0x8) /**< (USART) IrDA*/ -#define US_MR_USART_MODE_SPIM (0xE) /**< (USART) SPI Master*/ -#define US_MR_USART_MODE_SPIS (0xF) /**< (USART) SPI Slave*/ -#define US_MR_USCLKS (0x3 << 4) /**< \brief (US_MR) Clock Selection */ -#define US_MR_USCLKS_CLOCK (0x0 << 4) /**< (USART) MCK*/ -#define US_MR_USCLKS_FDIV1 (0x1 << 4) /**< (USART) MCK/DIV(DIV=8)*/ -#define US_MR_USCLKS_SLOW (0x2 << 4) /**< (USART) Reserved*/ -#define US_MR_USCLKS_EXT (0x3 << 4) /**< (USART) SCK*/ -#define US_MR_CHRL (0x3 << 6) /**< \brief (US_MR) Character Length. */ -#define US_MR_CHRL_5_BITS (0x0 << 6) /**< (USART) Character Length: 5 bits*/ -#define US_MR_CHRL_6_BITS (0x1 << 6) /**< (USART) Character Length: 6 bits*/ -#define US_MR_CHRL_7_BITS (0x2 << 6) /**< (USART) Character Length: 7 bits*/ -#define US_MR_CHRL_8_BITS (0x3 << 6) /**< (USART) Character Length: 8 bits*/ -#define US_MR_SYNC__CPHA (0x1 << 8) /**< \brief (US_MR) Synchronous Mode Select or SPI Clock Phase */ -#define US_MR_PAR (0x7 << 9) /**< \brief (US_MR) Parity Type */ -#define US_MR_PAR_EVEN (0x0 << 9) /**< (USART) Even Parity*/ -#define US_MR_PAR_ODD (0x1 << 9) /**< (USART) Odd Parity*/ -#define US_MR_PAR_SPACE (0x2 << 9) /**< (USART) Parity forced to 0 (Space)*/ -#define US_MR_PAR_MARK (0x3 << 9) /**< (USART) Parity forced to 1 (Mark)*/ -#define US_MR_PAR_NONE (0x4 << 9) /**< (USART) No Parity*/ -#define US_MR_PAR_MULTI_DROP (0x6 << 9) /**< (USART) Multi-drop mode*/ -#define US_MR_NBSTOP (0x3 << 12) /**< \brief (US_MR) Number of Stop Bits */ -#define US_MR_NBSTOP_1_BIT (0x0 << 12) /**< (USART) 1 stop bit*/ -#define US_MR_NBSTOP_15_BIT (0x1 << 12) /**< (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits*/ -#define US_MR_NBSTOP_2_BIT (0x2 << 12) /**< (USART) 2 stop bits*/ -#define US_MR_CHMODE (0x3 << 14) /**< \brief (US_MR) Channel Mode */ -#define US_MR_CHMODE_NORMAL (0x0 << 14) /**< (USART) Normal Mode: The USART channel operates as an RX/TX USART.*/ -#define US_MR_CHMODE_AUTO (0x1 << 14) /**< (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.*/ -#define US_MR_CHMODE_LOCAL (0x2 << 14) /**< (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.*/ -#define US_MR_CHMODE_REMOTE (0x3 << 14) /**< (USART) Remote Loopback: RXD pin is internally connected to TXD pin.*/ -#define US_MR_MSBF__CPOL (0x1 << 16) /**< \brief (US_MR) Bit Order or SPI Clock Polarity */ -#define US_MR_MODE9 (0x1 << 17) /**< \brief (US_MR) 9-bit Character Length */ -#define US_MR_CLKO (0x1 << 18) /**< \brief (US_MR) Clock Output Select */ -#define US_MR_OVER (0x1 << 19) /**< \brief (US_MR) Oversampling Mode */ -#define US_MR_INACK (0x1 << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ -#define US_MR_DSNACK (0x1 << 21) /**< \brief (US_MR) Disable Successive NACK */ -#define US_MR_VAR_SYNC (0x1 << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ -#define US_MR_INVDATA (0x1 << 23) /**< \brief (US_MR) INverted Data */ -#define US_MR_MAX_ITERATION (0x7 << 24) /**< \brief (US_MR) */ -#define US_MR_FILTER (0x1 << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ -#define US_MR_MAN (0x1 << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ -#define US_MR_MODSYNC_ (0x1 << 30) /**< \brief (US_MR) */ -#define US_MR_ONEBIT (0x1 << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ -/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ -#define US_IER_RXRDY (0x1 << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ -#define US_IER_TXRDY (0x1 << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ -#define US_IER_RXBRK (0x1 << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ -#define US_IER_ENDRX (0x1 << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */ -#define US_IER_ENDTX (0x1 << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */ -#define US_IER_OVRE (0x1 << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ -#define US_IER_FRAME (0x1 << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ -#define US_IER_PARE (0x1 << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ -#define US_IER_TIMEOUT (0x1 << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ -#define US_IER_TXEMPTY (0x1 << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ -#define US_IER_ITER__UNRE (0x1 << 10) /**< \brief (US_IER) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IER_TXBUFE (0x1 << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */ -#define US_IER_RXBUFF (0x1 << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */ -#define US_IER_NACK (0x1 << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ -#define US_IER_RIIC (0x1 << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ -#define US_IER_DSRIC (0x1 << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ -#define US_IER_DCDIC (0x1 << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ -#define US_IER_CTSIC (0x1 << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ -#define US_IER_MANE (0x1 << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ -/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ -#define US_IDR_RXRDY (0x1 << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ -#define US_IDR_TXRDY (0x1 << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ -#define US_IDR_RXBRK (0x1 << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ -#define US_IDR_ENDRX (0x1 << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */ -#define US_IDR_ENDTX (0x1 << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */ -#define US_IDR_OVRE (0x1 << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */ -#define US_IDR_FRAME (0x1 << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ -#define US_IDR_PARE (0x1 << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ -#define US_IDR_TIMEOUT (0x1 << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ -#define US_IDR_TXEMPTY (0x1 << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ -#define US_IDR_ITER__UNRE (0x1 << 10) /**< \brief (US_IDR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IDR_TXBUFE (0x1 << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */ -#define US_IDR_RXBUFF (0x1 << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */ -#define US_IDR_NACK (0x1 << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ -#define US_IDR_RIIC (0x1 << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ -#define US_IDR_DSRIC (0x1 << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ -#define US_IDR_DCDIC (0x1 << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ -#define US_IDR_CTSIC (0x1 << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ -#define US_IDR_MANE (0x1 << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ -/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ -#define US_IMR_RXRDY (0x1 << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ -#define US_IMR_TXRDY (0x1 << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ -#define US_IMR_RXBRK (0x1 << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ -#define US_IMR_ENDRX (0x1 << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */ -#define US_IMR_ENDTX (0x1 << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */ -#define US_IMR_OVRE (0x1 << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ -#define US_IMR_FRAME (0x1 << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ -#define US_IMR_PARE (0x1 << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ -#define US_IMR_TIMEOUT (0x1 << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ -#define US_IMR_TXEMPTY (0x1 << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ -#define US_IMR_ITER__UNRE (0x1 << 10) /**< \brief (US_IMR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IMR_TXBUFE (0x1 << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */ -#define US_IMR_RXBUFF (0x1 << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */ -#define US_IMR_NACK (0x1 << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ -#define US_IMR_RIIC (0x1 << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ -#define US_IMR_DSRIC (0x1 << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ -#define US_IMR_DCDIC (0x1 << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ -#define US_IMR_CTSIC (0x1 << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ -#define US_IMR_MANE (0x1 << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ -/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ -#define US_CSR_RXRDY (0x1 << 0) /**< \brief (US_CSR) Receiver Ready */ -#define US_CSR_TXRDY (0x1 << 1) /**< \brief (US_CSR) Transmitter Ready */ -#define US_CSR_RXBRK (0x1 << 2) /**< \brief (US_CSR) Break Received/End of Break */ -#define US_CSR_ENDRX (0x1 << 3) /**< \brief (US_CSR) End of Receiver Transfer */ -#define US_CSR_ENDTX (0x1 << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ -#define US_CSR_OVRE (0x1 << 5) /**< \brief (US_CSR) Overrun Error */ -#define US_CSR_FRAME (0x1 << 6) /**< \brief (US_CSR) Framing Error */ -#define US_CSR_PARE (0x1 << 7) /**< \brief (US_CSR) Parity Error */ -#define US_CSR_TIMEOUT (0x1 << 8) /**< \brief (US_CSR) Receiver Time-out */ -#define US_CSR_TXEMPTY (0x1 << 9) /**< \brief (US_CSR) Transmitter Empty */ -#define US_CSR_ITER__UNRE (0x1 << 10) /**< \brief (US_CSR) Max number of Repetitions Reached or SPI Underrun Error */ -#define US_CSR_TXBUFE (0x1 << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ -#define US_CSR_RXBUFF (0x1 << 12) /**< \brief (US_CSR) Reception Buffer Full */ -#define US_CSR_NACK (0x1 << 13) /**< \brief (US_CSR) */ -#define US_CSR_RIIC (0x1 << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */ -#define US_CSR_DSRIC (0x1 << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */ -#define US_CSR_DCDIC (0x1 << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */ -#define US_CSR_CTSIC (0x1 << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ -#define US_CSR_RI (0x1 << 20) /**< \brief (US_CSR) Image of RI Input */ -#define US_CSR_DSR (0x1 << 21) /**< \brief (US_CSR) Image of DSR Input */ -#define US_CSR_DCD (0x1 << 22) /**< \brief (US_CSR) Image of DCD Input */ -#define US_CSR_CTS (0x1 << 23) /**< \brief (US_CSR) Image of CTS Input */ -#define US_CSR_MANERR (0x1 << 24) /**< \brief (US_CSR) Manchester Error */ -/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ -#define US_RHR_RXCHR (0x1ff << 0) /**< \brief (US_RHR) Received Character */ -#define US_RHR_RXSYNH (0x1 << 15) /**< \brief (US_RHR) Received Sync */ -/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ -#define US_THR_TXCHR (0x1ff << 0) /**< \brief (US_THR) Character to be Transmitted */ -#define US_THR_TXSYNH (0x1 << 15) /**< \brief (US_THR) Sync Field to be transmitted */ -/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define US_BRGR_CD (0xffff << 0) /**< \brief (US_BRGR) Clock Divider */ -#define US_BRGR_FP (0x7 << 16) /**< \brief (US_BRGR) Fractional Part */ -/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ -#define US_RTOR_TO (0xffff << 0) /**< \brief (US_RTOR) Time-out Value */ -/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ -#define US_TTGR_TG (0xff << 0) /**< \brief (US_TTGR) Timeguard Value */ -/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ -#define US_FIDI_FI_DI_RATIO (0x7ff << 0) /**< \brief (US_FIDI) FI Over DI Ratio Value */ -/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ -#define US_NER_NB_ERRORS (0xff << 0) /**< \brief (US_NER) Number of Errors */ -/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ -#define US_IF_IRDA_FILTER (0xff << 0) /**< \brief (US_IF) IrDA Filter */ -/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ -#define US_MAN_TX_PL (0xf << 0) /**< \brief (US_MAN) Transmitter Preamble Length */ -#define US_MAN_TX_PP (0x3 << 8) /**< \brief (US_MAN) Transmitter Preamble Pattern */ -#define US_MAN_TX_MPOL (0x1 << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ -#define US_MAN_RX_PL (0xf << 16) /**< \brief (US_MAN) Receiver Preamble Length */ -#define US_MAN_RX_PP (0x3 << 24) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ -#define US_MAN_RX_MPOL (0x1 << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ -#define US_MAN_STUCKTO1 (0x1 << 29) /**< \brief (US_MAN) */ -#define US_MAN_DRIFT (0x1 << 30) /**< \brief (US_MAN) Drift compensation */ -/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */ -#define US_WPMR_WPEN (0x1 << 0) /**< \brief (US_WPMR) Write Protect Enable */ -#define US_WPMR_WPKEY (0xffffff << 8) /**< \brief (US_WPMR) Write Protect KEY */ -/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */ -#define US_WPSR_WPVS (0x1 << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ -#define US_WPSR_WPVSRC (0xffff << 8) /**< \brief (US_WPSR) Write Protect Violation Source */ -/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */ -#define US_VERSION_VERSION (0xfff << 0) /**< \brief (US_VERSION) */ -#define US_VERSION_MFN (0x7 << 16) /**< \brief (US_VERSION) */ -/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ -#define US_RPR_RXPTR (0xffffffff << 0) /**< \brief (US_RPR) Receive Pointer Register */ -/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ -#define US_RCR_RXCTR (0xffff << 0) /**< \brief (US_RCR) Receive Counter Register */ -/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ -#define US_TPR_TXPTR (0xffffffff << 0) /**< \brief (US_TPR) Transmit Counter Register */ -/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ -#define US_TCR_TXCTR (0xffff << 0) /**< \brief (US_TCR) Transmit Counter Register */ -/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ -#define US_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (US_RNPR) Receive Next Pointer */ -/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ -#define US_RNCR_RXNCTR (0xffff << 0) /**< \brief (US_RNCR) Receive Next Counter */ -/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define US_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (US_TNPR) Transmit Next Pointer */ -/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define US_TNCR_TXNCTR (0xffff << 0) /**< \brief (US_TNCR) Transmit Counter Next */ -/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ -#define US_PTCR_RXTEN (0x1 << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ -#define US_PTCR_RXTDIS (0x1 << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ -#define US_PTCR_TXTEN (0x1 << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ -#define US_PTCR_TXTDIS (0x1 << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ -/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ -#define US_PTSR_RXTEN (0x1 << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ -#define US_PTSR_TXTEN (0x1 << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Watchdog Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_WDT Watchdog Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Wdt hardware registers */ -typedef struct { - WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ - RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ - RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ -} Wdt; -#endif /* __ASSEMBLY__ */ -/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ -#define WDT_CR_WDRSTT (0x1 << 0) /**< \brief (WDT_CR) Watchdog Restart */ -#define WDT_CR_KEY (0xff << 24) /**< \brief (WDT_CR) Password */ -/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ -#define WDT_MR_WDV (0xfff << 0) /**< \brief (WDT_MR) Watchdog Counter Value */ -#define WDT_MR_WDFIEN (0x1 << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ -#define WDT_MR_WDRSTEN (0x1 << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ -#define WDT_MR_WDRPROC (0x1 << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ -#define WDT_MR_WDDIS (0x1 << 15) /**< \brief (WDT_MR) Watchdog Disable */ -#define WDT_MR_WDD (0xfff << 16) /**< \brief (WDT_MR) Watchdog Delta Value */ -#define WDT_MR_WDDBGHLT (0x1 << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ -#define WDT_MR_WDIDLEHLT (0x1 << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ -/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ -#define WDT_SR_WDUNF (0x1 << 0) /**< \brief (WDT_SR) Watchdog Underflow */ -#define WDT_SR_WDERR (0x1 << 1) /**< \brief (WDT_SR) Watchdog Error */ - -/*@}*/ - -/*@}*/ - -/* ***************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_reg Registers Access Definitions */ -/*@{*/ - -/* ========== Register definition for HSMCI peripheral ========== */ -#define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */ -#define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */ -#define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ -#define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ -#define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */ -#define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */ -#define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */ -#define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ -#define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */ -#define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */ -#define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ -#define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */ -#define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ -#define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ -#define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ -#define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */ -#define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ -#define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ -#define REG_HSMCI_RPR REG_ACCESS(RwReg, 0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */ -#define REG_HSMCI_RCR REG_ACCESS(RwReg, 0x40000104U) /**< \brief (HSMCI) Receive Counter Register */ -#define REG_HSMCI_TPR REG_ACCESS(RwReg, 0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */ -#define REG_HSMCI_TCR REG_ACCESS(RwReg, 0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */ -#define REG_HSMCI_RNPR REG_ACCESS(RwReg, 0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */ -#define REG_HSMCI_RNCR REG_ACCESS(RwReg, 0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */ -#define REG_HSMCI_TNPR REG_ACCESS(RwReg, 0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */ -#define REG_HSMCI_TNCR REG_ACCESS(RwReg, 0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */ -#define REG_HSMCI_PTCR REG_ACCESS(WoReg, 0x40000120U) /**< \brief (HSMCI) Transfer Control Register */ -#define REG_HSMCI_PTSR REG_ACCESS(RoReg, 0x40000124U) /**< \brief (HSMCI) Transfer Status Register */ -/* ========== Register definition for SSC peripheral ========== */ -#define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */ -#define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */ -#define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ -#define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ -#define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ -#define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ -#define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */ -#define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */ -#define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ -#define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ -#define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ -#define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ -#define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */ -#define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ -#define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ -#define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ -#define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ -#define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ -#define REG_SSC_RPR REG_ACCESS(RwReg, 0x40004100U) /**< \brief (SSC) Receive Pointer Register */ -#define REG_SSC_RCR REG_ACCESS(RwReg, 0x40004104U) /**< \brief (SSC) Receive Counter Register */ -#define REG_SSC_TPR REG_ACCESS(RwReg, 0x40004108U) /**< \brief (SSC) Transmit Pointer Register */ -#define REG_SSC_TCR REG_ACCESS(RwReg, 0x4000410CU) /**< \brief (SSC) Transmit Counter Register */ -#define REG_SSC_RNPR REG_ACCESS(RwReg, 0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */ -#define REG_SSC_RNCR REG_ACCESS(RwReg, 0x40004114U) /**< \brief (SSC) Receive Next Counter Register */ -#define REG_SSC_TNPR REG_ACCESS(RwReg, 0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */ -#define REG_SSC_TNCR REG_ACCESS(RwReg, 0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */ -#define REG_SSC_PTCR REG_ACCESS(WoReg, 0x40004120U) /**< \brief (SSC) Transfer Control Register */ -#define REG_SSC_PTSR REG_ACCESS(RoReg, 0x40004124U) /**< \brief (SSC) Transfer Status Register */ -/* ========== Register definition for SPI peripheral ========== */ -#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */ -#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */ -#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */ -#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */ -#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */ -#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ -#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ -#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ -#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */ -#define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ -#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ -#define REG_SPI_RPR REG_ACCESS(RwReg, 0x40008100U) /**< \brief (SPI) Receive Pointer Register */ -#define REG_SPI_RCR REG_ACCESS(RwReg, 0x40008104U) /**< \brief (SPI) Receive Counter Register */ -#define REG_SPI_TPR REG_ACCESS(RwReg, 0x40008108U) /**< \brief (SPI) Transmit Pointer Register */ -#define REG_SPI_TCR REG_ACCESS(RwReg, 0x4000810CU) /**< \brief (SPI) Transmit Counter Register */ -#define REG_SPI_RNPR REG_ACCESS(RwReg, 0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */ -#define REG_SPI_RNCR REG_ACCESS(RwReg, 0x40008114U) /**< \brief (SPI) Receive Next Counter Register */ -#define REG_SPI_TNPR REG_ACCESS(RwReg, 0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */ -#define REG_SPI_TNCR REG_ACCESS(RwReg, 0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */ -#define REG_SPI_PTCR REG_ACCESS(WoReg, 0x40008120U) /**< \brief (SPI) Transfer Control Register */ -#define REG_SPI_PTSR REG_ACCESS(RoReg, 0x40008124U) /**< \brief (SPI) Transfer Status Register */ -/* ========== Register definition for TC0 peripheral ========== */ -#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ -#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ -#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ -#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ -#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ -#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ -#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ -#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ -#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ -#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ -#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ -#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ -#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ -#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ -#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ -#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ -#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ -#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ -#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ -#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ -#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ -#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ -#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ -#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ -#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ -#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ -#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ -#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ -#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ -#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ -#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400100C0U) /**< \brief (TC0) Block Control Register */ -#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400100C4U) /**< \brief (TC0) Block Mode Register */ -#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ -#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ -#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ -#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ -#define REG_TC0_FMR REG_ACCESS(RwReg, 0x400100D8U) /**< \brief (TC0) Fault Mode Register */ -#define REG_TC0_WPMR REG_ACCESS(RwReg, 0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */ -#define REG_TC0_VER REG_ACCESS(RoReg, 0x400100FCU) /**< \brief (TC0) Version Register */ -/* ========== Register definition for TC1 peripheral ========== */ -#define REG_TC1_CCR0 REG_ACCESS(WoReg, 0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ -#define REG_TC1_CMR0 REG_ACCESS(RwReg, 0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ -#define REG_TC1_CV0 REG_ACCESS(RoReg, 0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ -#define REG_TC1_RA0 REG_ACCESS(RwReg, 0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ -#define REG_TC1_RB0 REG_ACCESS(RwReg, 0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ -#define REG_TC1_RC0 REG_ACCESS(RwReg, 0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ -#define REG_TC1_SR0 REG_ACCESS(RoReg, 0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ -#define REG_TC1_IER0 REG_ACCESS(WoReg, 0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ -#define REG_TC1_IDR0 REG_ACCESS(WoReg, 0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ -#define REG_TC1_IMR0 REG_ACCESS(RoReg, 0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ -#define REG_TC1_CCR1 REG_ACCESS(WoReg, 0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ -#define REG_TC1_CMR1 REG_ACCESS(RwReg, 0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ -#define REG_TC1_CV1 REG_ACCESS(RoReg, 0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ -#define REG_TC1_RA1 REG_ACCESS(RwReg, 0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ -#define REG_TC1_RB1 REG_ACCESS(RwReg, 0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ -#define REG_TC1_RC1 REG_ACCESS(RwReg, 0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ -#define REG_TC1_SR1 REG_ACCESS(RoReg, 0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ -#define REG_TC1_IER1 REG_ACCESS(WoReg, 0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ -#define REG_TC1_IDR1 REG_ACCESS(WoReg, 0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ -#define REG_TC1_IMR1 REG_ACCESS(RoReg, 0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ -#define REG_TC1_CCR2 REG_ACCESS(WoReg, 0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ -#define REG_TC1_CMR2 REG_ACCESS(RwReg, 0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ -#define REG_TC1_CV2 REG_ACCESS(RoReg, 0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ -#define REG_TC1_RA2 REG_ACCESS(RwReg, 0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ -#define REG_TC1_RB2 REG_ACCESS(RwReg, 0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ -#define REG_TC1_RC2 REG_ACCESS(RwReg, 0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ -#define REG_TC1_SR2 REG_ACCESS(RoReg, 0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ -#define REG_TC1_IER2 REG_ACCESS(WoReg, 0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ -#define REG_TC1_IDR2 REG_ACCESS(WoReg, 0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ -#define REG_TC1_IMR2 REG_ACCESS(RoReg, 0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ -#define REG_TC1_BCR REG_ACCESS(WoReg, 0x400140C0U) /**< \brief (TC1) Block Control Register */ -#define REG_TC1_BMR REG_ACCESS(RwReg, 0x400140C4U) /**< \brief (TC1) Block Mode Register */ -#define REG_TC1_QIER REG_ACCESS(WoReg, 0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ -#define REG_TC1_QIDR REG_ACCESS(WoReg, 0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ -#define REG_TC1_QIMR REG_ACCESS(RoReg, 0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ -#define REG_TC1_QISR REG_ACCESS(RoReg, 0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ -#define REG_TC1_FMR REG_ACCESS(RwReg, 0x400140D8U) /**< \brief (TC1) Fault Mode Register */ -#define REG_TC1_WPMR REG_ACCESS(RwReg, 0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */ -#define REG_TC1_VER REG_ACCESS(RoReg, 0x400140FCU) /**< \brief (TC1) Version Register */ -/* ========== Register definition for TWI0 peripheral ========== */ -#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40018000U) /**< \brief (TWI0) Control Register */ -#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40018004U) /**< \brief (TWI0) Master Mode Register */ -#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40018008U) /**< \brief (TWI0) Slave Mode Register */ -#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4001800CU) /**< \brief (TWI0) Internal Address Register */ -#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */ -#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40018020U) /**< \brief (TWI0) Status Register */ -#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */ -#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */ -#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */ -#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40018030U) /**< \brief (TWI0) Receive Holding Register */ -#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40018034U) /**< \brief (TWI0) Transmit Holding Register */ -#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40018100U) /**< \brief (TWI0) Receive Pointer Register */ -#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40018104U) /**< \brief (TWI0) Receive Counter Register */ -#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */ -#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */ -#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */ -#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */ -#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */ -#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */ -#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40018120U) /**< \brief (TWI0) Transfer Control Register */ -#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40018124U) /**< \brief (TWI0) Transfer Status Register */ -/* ========== Register definition for TWI1 peripheral ========== */ -#define REG_TWI1_CR REG_ACCESS(WoReg, 0x4001C000U) /**< \brief (TWI1) Control Register */ -#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x4001C004U) /**< \brief (TWI1) Master Mode Register */ -#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x4001C008U) /**< \brief (TWI1) Slave Mode Register */ -#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4001C00CU) /**< \brief (TWI1) Internal Address Register */ -#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */ -#define REG_TWI1_SR REG_ACCESS(RoReg, 0x4001C020U) /**< \brief (TWI1) Status Register */ -#define REG_TWI1_IER REG_ACCESS(WoReg, 0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */ -#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */ -#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */ -#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x4001C030U) /**< \brief (TWI1) Receive Holding Register */ -#define REG_TWI1_THR REG_ACCESS(WoReg, 0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */ -#define REG_TWI1_RPR REG_ACCESS(RwReg, 0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */ -#define REG_TWI1_RCR REG_ACCESS(RwReg, 0x4001C104U) /**< \brief (TWI1) Receive Counter Register */ -#define REG_TWI1_TPR REG_ACCESS(RwReg, 0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */ -#define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */ -#define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */ -#define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */ -#define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */ -#define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */ -#define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x4001C120U) /**< \brief (TWI1) Transfer Control Register */ -#define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x4001C124U) /**< \brief (TWI1) Transfer Status Register */ -/* ========== Register definition for PWM peripheral ========== */ -#define REG_PWM_CLK REG_ACCESS(RwReg, 0x40020000U) /**< \brief (PWM) PWM Clock Register */ -#define REG_PWM_ENA REG_ACCESS(WoReg, 0x40020004U) /**< \brief (PWM) PWM Enable Register */ -#define REG_PWM_DIS REG_ACCESS(WoReg, 0x40020008U) /**< \brief (PWM) PWM Disable Register */ -#define REG_PWM_SR REG_ACCESS(RoReg, 0x4002000CU) /**< \brief (PWM) PWM Status Register */ -#define REG_PWM_IER1 REG_ACCESS(WoReg, 0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ -#define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ -#define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ -#define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ -#define REG_PWM_SCM REG_ACCESS(RwReg, 0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ -#define REG_PWM_SCUC REG_ACCESS(RwReg, 0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ -#define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ -#define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ -#define REG_PWM_IER2 REG_ACCESS(WoReg, 0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ -#define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ -#define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ -#define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ -#define REG_PWM_OOV REG_ACCESS(RwReg, 0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */ -#define REG_PWM_OS REG_ACCESS(RwReg, 0x40020048U) /**< \brief (PWM) PWM Output Selection Register */ -#define REG_PWM_OSS REG_ACCESS(WoReg, 0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */ -#define REG_PWM_OSC REG_ACCESS(WoReg, 0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */ -#define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ -#define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ -#define REG_PWM_FMR REG_ACCESS(RwReg, 0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */ -#define REG_PWM_FSR REG_ACCESS(RoReg, 0x40020060U) /**< \brief (PWM) PWM Fault Status Register */ -#define REG_PWM_FCR REG_ACCESS(WoReg, 0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */ -#define REG_PWM_FPV REG_ACCESS(RwReg, 0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */ -#define REG_PWM_FPE REG_ACCESS(RwReg, 0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ -#define REG_PWM_ELxMR REG_ACCESS(RwReg, 0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ -#define REG_PWM_SMMR REG_ACCESS(RwReg, 0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ -#define REG_PWM_WPCR REG_ACCESS(WoReg, 0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */ -#define REG_PWM_WPSR REG_ACCESS(RoReg, 0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */ -#define REG_PWM_RPR REG_ACCESS(RwReg, 0x40020100U) /**< \brief (PWM) Receive Pointer Register */ -#define REG_PWM_RCR REG_ACCESS(RwReg, 0x40020104U) /**< \brief (PWM) Receive Counter Register */ -#define REG_PWM_TPR REG_ACCESS(RwReg, 0x40020108U) /**< \brief (PWM) Transmit Pointer Register */ -#define REG_PWM_TCR REG_ACCESS(RwReg, 0x4002010CU) /**< \brief (PWM) Transmit Counter Register */ -#define REG_PWM_RNPR REG_ACCESS(RwReg, 0x40020110U) /**< \brief (PWM) Receive Next Pointer Register */ -#define REG_PWM_RNCR REG_ACCESS(RwReg, 0x40020114U) /**< \brief (PWM) Receive Next Counter Register */ -#define REG_PWM_TNPR REG_ACCESS(RwReg, 0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */ -#define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */ -#define REG_PWM_PTCR REG_ACCESS(WoReg, 0x40020120U) /**< \brief (PWM) Transfer Control Register */ -#define REG_PWM_PTSR REG_ACCESS(RoReg, 0x40020124U) /**< \brief (PWM) Transfer Status Register */ -#define REG_PWM_CMP0V REG_ACCESS(RwReg, 0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ -#define REG_PWM_CMP0VUPD REG_ACCESS(WoReg, 0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ -#define REG_PWM_CMP0M REG_ACCESS(RwReg, 0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ -#define REG_PWM_CMP0MUPD REG_ACCESS(WoReg, 0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ -#define REG_PWM_CMP1V REG_ACCESS(RwReg, 0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ -#define REG_PWM_CMP1VUPD REG_ACCESS(WoReg, 0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ -#define REG_PWM_CMP1M REG_ACCESS(RwReg, 0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ -#define REG_PWM_CMP1MUPD REG_ACCESS(WoReg, 0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ -#define REG_PWM_CMP2V REG_ACCESS(RwReg, 0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ -#define REG_PWM_CMP2VUPD REG_ACCESS(WoReg, 0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ -#define REG_PWM_CMP2M REG_ACCESS(RwReg, 0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ -#define REG_PWM_CMP2MUPD REG_ACCESS(WoReg, 0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ -#define REG_PWM_CMP3V REG_ACCESS(RwReg, 0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ -#define REG_PWM_CMP3VUPD REG_ACCESS(WoReg, 0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ -#define REG_PWM_CMP3M REG_ACCESS(RwReg, 0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ -#define REG_PWM_CMP3MUPD REG_ACCESS(WoReg, 0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ -#define REG_PWM_CMP4V REG_ACCESS(RwReg, 0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ -#define REG_PWM_CMP4VUPD REG_ACCESS(WoReg, 0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ -#define REG_PWM_CMP4M REG_ACCESS(RwReg, 0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ -#define REG_PWM_CMP4MUPD REG_ACCESS(WoReg, 0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ -#define REG_PWM_CMP5V REG_ACCESS(RwReg, 0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ -#define REG_PWM_CMP5VUPD REG_ACCESS(WoReg, 0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ -#define REG_PWM_CMP5M REG_ACCESS(RwReg, 0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ -#define REG_PWM_CMP5MUPD REG_ACCESS(WoReg, 0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ -#define REG_PWM_CMP6V REG_ACCESS(RwReg, 0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ -#define REG_PWM_CMP6VUPD REG_ACCESS(WoReg, 0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ -#define REG_PWM_CMP6M REG_ACCESS(RwReg, 0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ -#define REG_PWM_CMP6MUPD REG_ACCESS(WoReg, 0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ -#define REG_PWM_CMP7V REG_ACCESS(RwReg, 0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ -#define REG_PWM_CMP7VUPD REG_ACCESS(WoReg, 0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ -#define REG_PWM_CMP7M REG_ACCESS(RwReg, 0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ -#define REG_PWM_CMP7MUPD REG_ACCESS(WoReg, 0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ -#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ -#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ -#define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ -#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ -#define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ -#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ -#define REG_PWM_DT0 REG_ACCESS(RwReg, 0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ -#define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ -#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ -#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ -#define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ -#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ -#define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ -#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ -#define REG_PWM_DT1 REG_ACCESS(RwReg, 0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ -#define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ -#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ -#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ -#define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ -#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ -#define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ -#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ -#define REG_PWM_DT2 REG_ACCESS(RwReg, 0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ -#define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ -#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ -#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ -#define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ -#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ -#define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ -#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ -#define REG_PWM_DT3 REG_ACCESS(RwReg, 0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ -#define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ -/* ========== Register definition for USART0 peripheral ========== */ -#define REG_USART0_CR REG_ACCESS(WoReg, 0x40024000U) /**< \brief (USART0) Control Register */ -#define REG_USART0_MR REG_ACCESS(RwReg, 0x40024004U) /**< \brief (USART0) Mode Register */ -#define REG_USART0_IER REG_ACCESS(WoReg, 0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ -#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ -#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ -#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40024014U) /**< \brief (USART0) Channel Status Register */ -#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40024018U) /**< \brief (USART0) Receiver Holding Register */ -#define REG_USART0_THR REG_ACCESS(WoReg, 0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */ -#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ -#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ -#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ -#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ -#define REG_USART0_NER REG_ACCESS(RoReg, 0x40024044U) /**< \brief (USART0) Number of Errors Register */ -#define REG_USART0_IF REG_ACCESS(RwReg, 0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ -#define REG_USART0_MAN REG_ACCESS(RwReg, 0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ -#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */ -#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400240E8U) /**< \brief (USART0) Write Protect Status Register */ -#define REG_USART0_VERSION REG_ACCESS(RoReg, 0x400240FCU) /**< \brief (USART0) Version Register */ -#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40024100U) /**< \brief (USART0) Receive Pointer Register */ -#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40024104U) /**< \brief (USART0) Receive Counter Register */ -#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40024108U) /**< \brief (USART0) Transmit Pointer Register */ -#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4002410CU) /**< \brief (USART0) Transmit Counter Register */ -#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */ -#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40024114U) /**< \brief (USART0) Receive Next Counter Register */ -#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */ -#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */ -#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40024120U) /**< \brief (USART0) Transfer Control Register */ -#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40024124U) /**< \brief (USART0) Transfer Status Register */ -/* ========== Register definition for USART1 peripheral ========== */ -#define REG_USART1_CR REG_ACCESS(WoReg, 0x40028000U) /**< \brief (USART1) Control Register */ -#define REG_USART1_MR REG_ACCESS(RwReg, 0x40028004U) /**< \brief (USART1) Mode Register */ -#define REG_USART1_IER REG_ACCESS(WoReg, 0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ -#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ -#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ -#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40028014U) /**< \brief (USART1) Channel Status Register */ -#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40028018U) /**< \brief (USART1) Receiver Holding Register */ -#define REG_USART1_THR REG_ACCESS(WoReg, 0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */ -#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ -#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ -#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ -#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ -#define REG_USART1_NER REG_ACCESS(RoReg, 0x40028044U) /**< \brief (USART1) Number of Errors Register */ -#define REG_USART1_IF REG_ACCESS(RwReg, 0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ -#define REG_USART1_MAN REG_ACCESS(RwReg, 0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ -#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */ -#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400280E8U) /**< \brief (USART1) Write Protect Status Register */ -#define REG_USART1_VERSION REG_ACCESS(RoReg, 0x400280FCU) /**< \brief (USART1) Version Register */ -#define REG_USART1_RPR REG_ACCESS(RwReg, 0x40028100U) /**< \brief (USART1) Receive Pointer Register */ -#define REG_USART1_RCR REG_ACCESS(RwReg, 0x40028104U) /**< \brief (USART1) Receive Counter Register */ -#define REG_USART1_TPR REG_ACCESS(RwReg, 0x40028108U) /**< \brief (USART1) Transmit Pointer Register */ -#define REG_USART1_TCR REG_ACCESS(RwReg, 0x4002810CU) /**< \brief (USART1) Transmit Counter Register */ -#define REG_USART1_RNPR REG_ACCESS(RwReg, 0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */ -#define REG_USART1_RNCR REG_ACCESS(RwReg, 0x40028114U) /**< \brief (USART1) Receive Next Counter Register */ -#define REG_USART1_TNPR REG_ACCESS(RwReg, 0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */ -#define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */ -#define REG_USART1_PTCR REG_ACCESS(WoReg, 0x40028120U) /**< \brief (USART1) Transfer Control Register */ -#define REG_USART1_PTSR REG_ACCESS(RoReg, 0x40028124U) /**< \brief (USART1) Transfer Status Register */ -/* ========== Register definition for UDP peripheral ========== */ -#define REG_UDP_FRM_NUM REG_ACCESS(RoReg, 0x40034000U) /**< \brief (UDP) Frame Number Register */ -#define REG_UDP_GLB_STAT REG_ACCESS(RwReg, 0x40034004U) /**< \brief (UDP) Global State Register */ -#define REG_UDP_FADDR REG_ACCESS(RwReg, 0x40034008U) /**< \brief (UDP) Function Address Register */ -#define REG_UDP_IER REG_ACCESS(WoReg, 0x40034010U) /**< \brief (UDP) Interrupt Enable Register */ -#define REG_UDP_IDR REG_ACCESS(WoReg, 0x40034014U) /**< \brief (UDP) Interrupt Disable Register */ -#define REG_UDP_IMR REG_ACCESS(RoReg, 0x40034018U) /**< \brief (UDP) Interrupt Mask Register */ -#define REG_UDP_ISR REG_ACCESS(RoReg, 0x4003401CU) /**< \brief (UDP) Interrupt Status Register */ -#define REG_UDP_ICR REG_ACCESS(WoReg, 0x40034020U) /**< \brief (UDP) Interrupt Clear Register */ -#define REG_UDP_RST_EP REG_ACCESS(RwReg, 0x40034028U) /**< \brief (UDP) Reset Endpoint Register */ -#define REG_UDP_CSR REG_ACCESS(RwReg, 0x4003402CU) /**< \brief (UDP) Endpoint Control and Status Register (ept_num = 0) */ -#define REG_UDP_FDR REG_ACCESS(RwReg, 0x4003404CU) /**< \brief (UDP) Endpoint FIFO Data Register (ept_num = 0) */ -#define REG_UDP_TXVC REG_ACCESS(RwReg, 0x40034074U) /**< \brief (UDP) Transceiver Control Register */ -/* ========== Register definition for ADC peripheral ========== */ -#define REG_ADC_CR REG_ACCESS(WoReg, 0x40038000U) /**< \brief (ADC) Control Register */ -#define REG_ADC_MR REG_ACCESS(RwReg, 0x40038004U) /**< \brief (ADC) Mode Register */ -#define REG_ADC_SEQ1R REG_ACCESS(RwReg, 0x40038008U) /**< \brief (ADC) Channel Sequence 1Register */ -#define REG_ADC_SEQ2R REG_ACCESS(RwReg, 0x4003800CU) /**< \brief (ADC) Channel Sequence 2 Register */ -#define REG_ADC_CHER REG_ACCESS(WoReg, 0x40038010U) /**< \brief (ADC) Channel Enable Register */ -#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x40038014U) /**< \brief (ADC) Channel Disable Register */ -#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x40038018U) /**< \brief (ADC) Channel Status Register */ -#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x40038020U) /**< \brief (ADC) Last Converted Data Register */ -#define REG_ADC_IER REG_ACCESS(WoReg, 0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ -#define REG_ADC_IDR REG_ACCESS(WoReg, 0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ -#define REG_ADC_IMR REG_ACCESS(RoReg, 0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ -#define REG_ADC_ISR REG_ACCESS(RoReg, 0x40038030U) /**< \brief (ADC) Interrupt Status Register */ -#define REG_ADC_OVER REG_ACCESS(RoReg, 0x4003803CU) /**< \brief (ADC) Overrun Status Register */ -#define REG_ADC_EMR REG_ACCESS(RwReg, 0x40038040U) /**< \brief (ADC) Extended Mode Register */ -#define REG_ADC_CWR REG_ACCESS(RwReg, 0x40038044U) /**< \brief (ADC) Compare Window Register */ -#define REG_ADC_CGR REG_ACCESS(RwReg, 0x40038048U) /**< \brief (ADC) Channel Gain Register */ -#define REG_ADC_COR REG_ACCESS(RwReg, 0x4003804CU) /**< \brief (ADC) Channel Offset Register */ -#define REG_ADC_CDR0 REG_ACCESS(RoReg, 0x40038050U) /**< \brief (ADC) Channel Data Register 0 */ -#define REG_ADC_CDR1 REG_ACCESS(RoReg, 0x40038054U) /**< \brief (ADC) Channel Data Register 1 */ -#define REG_ADC_CDR2 REG_ACCESS(RoReg, 0x40038058U) /**< \brief (ADC) Channel Data Register 2 */ -#define REG_ADC_CDR3 REG_ACCESS(RoReg, 0x4003805CU) /**< \brief (ADC) Channel Data Register 3 */ -#define REG_ADC_CDR4 REG_ACCESS(RoReg, 0x40038060U) /**< \brief (ADC) Channel Data Register 4 */ -#define REG_ADC_CDR5 REG_ACCESS(RoReg, 0x40038064U) /**< \brief (ADC) Channel Data Register 5 */ -#define REG_ADC_CDR6 REG_ACCESS(RoReg, 0x40038068U) /**< \brief (ADC) Channel Data Register 6 */ -#define REG_ADC_CDR15 REG_ACCESS(RoReg, 0x4003806CU) /**< \brief (ADC) Channel Data Register 15 */ -#define REG_ADC_ACR REG_ACCESS(RwReg, 0x40038094U) /**< \brief (ADC) Analog Control Register */ -#define REG_ADC_WPMR REG_ACCESS(RwReg, 0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */ -#define REG_ADC_WPSR REG_ACCESS(RoReg, 0x400380E8U) /**< \brief (ADC) Write Protect Status Register */ -#define REG_ADC_RPR REG_ACCESS(RwReg, 0x40038100U) /**< \brief (ADC) Receive Pointer Register */ -#define REG_ADC_RCR REG_ACCESS(RwReg, 0x40038104U) /**< \brief (ADC) Receive Counter Register */ -#define REG_ADC_TPR REG_ACCESS(RwReg, 0x40038108U) /**< \brief (ADC) Transmit Pointer Register */ -#define REG_ADC_TCR REG_ACCESS(RwReg, 0x4003810CU) /**< \brief (ADC) Transmit Counter Register */ -#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ -#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ -#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */ -#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */ -#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x40038120U) /**< \brief (ADC) Transfer Control Register */ -#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x40038124U) /**< \brief (ADC) Transfer Status Register */ -/* ========== Register definition for DACC peripheral ========== */ -#define REG_DACC_CR REG_ACCESS(WoReg, 0x4003C000U) /**< \brief (DACC) Control Register */ -#define REG_DACC_MR REG_ACCESS(RwReg, 0x4003C004U) /**< \brief (DACC) Mode Register */ -#define REG_DACC_CHER REG_ACCESS(WoReg, 0x4003C010U) /**< \brief (DACC) Channel Enable Register */ -#define REG_DACC_CHDR REG_ACCESS(WoReg, 0x4003C014U) /**< \brief (DACC) Channel Disable Register */ -#define REG_DACC_CHSR REG_ACCESS(RoReg, 0x4003C018U) /**< \brief (DACC) Channel Status Register */ -#define REG_DACC_CDR REG_ACCESS(WoReg, 0x4003C020U) /**< \brief (DACC) Conversion Data Register */ -#define REG_DACC_IER REG_ACCESS(WoReg, 0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */ -#define REG_DACC_IDR REG_ACCESS(WoReg, 0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */ -#define REG_DACC_IMR REG_ACCESS(RoReg, 0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */ -#define REG_DACC_ISR REG_ACCESS(RoReg, 0x4003C030U) /**< \brief (DACC) Interrupt Status Register */ -#define REG_DACC_ACR REG_ACCESS(RwReg, 0x4003C094U) /**< \brief (DACC) Analog Current Register */ -#define REG_DACC_WPMR REG_ACCESS(RwReg, 0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */ -#define REG_DACC_WPSR REG_ACCESS(RoReg, 0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */ -#define REG_DACC_RPR REG_ACCESS(RwReg, 0x4003C100U) /**< \brief (DACC) Receive Pointer Register */ -#define REG_DACC_RCR REG_ACCESS(RwReg, 0x4003C104U) /**< \brief (DACC) Receive Counter Register */ -#define REG_DACC_TPR REG_ACCESS(RwReg, 0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */ -#define REG_DACC_TCR REG_ACCESS(RwReg, 0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */ -#define REG_DACC_RNPR REG_ACCESS(RwReg, 0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */ -#define REG_DACC_RNCR REG_ACCESS(RwReg, 0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */ -#define REG_DACC_TNPR REG_ACCESS(RwReg, 0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */ -#define REG_DACC_TNCR REG_ACCESS(RwReg, 0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */ -#define REG_DACC_PTCR REG_ACCESS(WoReg, 0x4003C120U) /**< \brief (DACC) Transfer Control Register */ -#define REG_DACC_PTSR REG_ACCESS(RoReg, 0x4003C124U) /**< \brief (DACC) Transfer Status Register */ -/* ========== Register definition for ACC peripheral ========== */ -#define REG_ACC_CR REG_ACCESS(WoReg, 0x40040000U) /**< \brief (ACC) Control Register */ -#define REG_ACC_MR REG_ACCESS(RwReg, 0x40040004U) /**< \brief (ACC) Mode Register */ -#define REG_ACC_IER REG_ACCESS(WoReg, 0x40040024U) /**< \brief (ACC) Interrupt Enable Register */ -#define REG_ACC_IDR REG_ACCESS(WoReg, 0x40040028U) /**< \brief (ACC) Interrupt Disable Register */ -#define REG_ACC_IMR REG_ACCESS(RoReg, 0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */ -#define REG_ACC_ISR REG_ACCESS(RoReg, 0x40040030U) /**< \brief (ACC) Interrupt Status Register */ -#define REG_ACC_ACR REG_ACCESS(RwReg, 0x40040094U) /**< \brief (ACC) Analog Control Register */ -#define REG_ACC_WPMR REG_ACCESS(RwReg, 0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */ -#define REG_ACC_WPSR REG_ACCESS(RoReg, 0x400400E8U) /**< \brief (ACC) Write Protect Status Register */ -/* ========== Register definition for CRCCU peripheral ========== */ -#define REG_CRCCU_DSCR REG_ACCESS(RwReg, 0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ -#define REG_CRCCU_DMA_EN REG_ACCESS(WoReg, 0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ -#define REG_CRCCU_DMA_DIS REG_ACCESS(WoReg, 0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ -#define REG_CRCCU_DMA_SR REG_ACCESS(RoReg, 0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ -#define REG_CRCCU_DMA_IER REG_ACCESS(WoReg, 0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ -#define REG_CRCCU_DMA_IDR REG_ACCESS(WoReg, 0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ -#define REG_CRCCU_DMA_IMR REG_ACCESS(RoReg, 0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ -#define REG_CRCCU_DMA_ISR REG_ACCESS(RoReg, 0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ -#define REG_CRCCU_CR REG_ACCESS(WoReg, 0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */ -#define REG_CRCCU_MR REG_ACCESS(RwReg, 0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */ -#define REG_CRCCU_SR REG_ACCESS(RoReg, 0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */ -#define REG_CRCCU_IER REG_ACCESS(WoReg, 0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ -#define REG_CRCCU_IDR REG_ACCESS(WoReg, 0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ -#define REG_CRCCU_IMR REG_ACCESS(RoReg, 0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ -#define REG_CRCCU_ISR REG_ACCESS(RoReg, 0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ -/* ========== Register definition for SMC peripheral ========== */ -#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ -#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ -#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ -#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ -#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ -#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ -#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ -#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ -#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ -#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ -#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ -#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ -#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ -#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ -#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ -#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ -#define REG_SMC_SETUP4 REG_ACCESS(RwReg, 0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */ -#define REG_SMC_PULSE4 REG_ACCESS(RwReg, 0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */ -#define REG_SMC_CYCLE4 REG_ACCESS(RwReg, 0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */ -#define REG_SMC_MODE4 REG_ACCESS(RwReg, 0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */ -#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */ -#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ -#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ -#define REG_SMC_WPMR REG_ACCESS(RwReg, 0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ -#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */ -/* ========== Register definition for MATRIX peripheral ========== */ -#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ -#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ -#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ -#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ -#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ -#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ -#define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ -#define REG_MATRIX_SYSIO REG_ACCESS(RwReg, 0x400E0314U) /**< \brief (MATRIX) System IO Configuration register */ -#define REG_MATRIX_SMCNFCS REG_ACCESS(RwReg, 0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */ -#define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ -#define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ -/* ========== Register definition for PMC peripheral ========== */ -#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ -#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ -#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */ -#define REG_PMC_PCER0 REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ -#define REG_PMC_PCDR0 REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ -#define REG_PMC_PCSR0 REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ -#define REG_PMC_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ -#define REG_PMC_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ -#define REG_PMC_PLLAR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */ -#define REG_PMC_PLLBR REG_ACCESS(RwReg, 0x400E042CU) /**< \brief (PMC) PLLB Register */ -#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */ -#define REG_PMC_USB REG_ACCESS(RwReg, 0x400E0438U) /**< \brief (PMC) USB Clock Register */ -#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ -#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ -#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ -#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */ -#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ -#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ -#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ -#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ -#define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ -#define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ -#define REG_PMC_PCER1 REG_ACCESS(WoReg, 0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ -#define REG_PMC_PCDR1 REG_ACCESS(WoReg, 0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ -#define REG_PMC_PCSR1 REG_ACCESS(RoReg, 0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ -#define REG_PMC_OCR REG_ACCESS(RwReg, 0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ -/* ========== Register definition for UART0 peripheral ========== */ -#define REG_UART0_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART0) Control Register */ -#define REG_UART0_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART0) Mode Register */ -#define REG_UART0_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */ -#define REG_UART0_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */ -#define REG_UART0_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */ -#define REG_UART0_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART0) Status Register */ -#define REG_UART0_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART0) Receive Holding Register */ -#define REG_UART0_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART0) Transmit Holding Register */ -#define REG_UART0_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */ -#define REG_UART0_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART0) Receive Pointer Register */ -#define REG_UART0_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART0) Receive Counter Register */ -#define REG_UART0_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */ -#define REG_UART0_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART0) Transmit Counter Register */ -#define REG_UART0_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */ -#define REG_UART0_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */ -#define REG_UART0_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */ -#define REG_UART0_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */ -#define REG_UART0_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART0) Transfer Control Register */ -#define REG_UART0_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART0) Transfer Status Register */ -/* ========== Register definition for CHIPID peripheral ========== */ -#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ -#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ -/* ========== Register definition for UART1 peripheral ========== */ -#define REG_UART1_CR REG_ACCESS(WoReg, 0x400E0800U) /**< \brief (UART1) Control Register */ -#define REG_UART1_MR REG_ACCESS(RwReg, 0x400E0804U) /**< \brief (UART1) Mode Register */ -#define REG_UART1_IER REG_ACCESS(WoReg, 0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */ -#define REG_UART1_IDR REG_ACCESS(WoReg, 0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */ -#define REG_UART1_IMR REG_ACCESS(RoReg, 0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */ -#define REG_UART1_SR REG_ACCESS(RoReg, 0x400E0814U) /**< \brief (UART1) Status Register */ -#define REG_UART1_RHR REG_ACCESS(RoReg, 0x400E0818U) /**< \brief (UART1) Receive Holding Register */ -#define REG_UART1_THR REG_ACCESS(WoReg, 0x400E081CU) /**< \brief (UART1) Transmit Holding Register */ -#define REG_UART1_BRGR REG_ACCESS(RwReg, 0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */ -#define REG_UART1_RPR REG_ACCESS(RwReg, 0x400E0900U) /**< \brief (UART1) Receive Pointer Register */ -#define REG_UART1_RCR REG_ACCESS(RwReg, 0x400E0904U) /**< \brief (UART1) Receive Counter Register */ -#define REG_UART1_TPR REG_ACCESS(RwReg, 0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */ -#define REG_UART1_TCR REG_ACCESS(RwReg, 0x400E090CU) /**< \brief (UART1) Transmit Counter Register */ -#define REG_UART1_RNPR REG_ACCESS(RwReg, 0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */ -#define REG_UART1_RNCR REG_ACCESS(RwReg, 0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */ -#define REG_UART1_TNPR REG_ACCESS(RwReg, 0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */ -#define REG_UART1_TNCR REG_ACCESS(RwReg, 0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */ -#define REG_UART1_PTCR REG_ACCESS(WoReg, 0x400E0920U) /**< \brief (UART1) Transfer Control Register */ -#define REG_UART1_PTSR REG_ACCESS(RoReg, 0x400E0924U) /**< \brief (UART1) Transfer Status Register */ -/* ========== Register definition for EFC peripheral ========== */ -#define REG_EFC_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ -#define REG_EFC_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ -#define REG_EFC_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ -#define REG_EFC_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ -/* ========== Register definition for PIOA peripheral ========== */ -#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ -#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ -#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ -#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ -#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ -#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOA) Output Status Register */ -#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ -#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ -#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ -#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ -#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ -#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ -#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ -#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ -#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ -#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ -#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ -#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ -#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ -#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ -#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ -#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ -#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ -#define REG_PIOA_ABCDSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ -#define REG_PIOA_SCIFSR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ -#define REG_PIOA_DIFSR REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ -#define REG_PIOA_IFDGSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ -#define REG_PIOA_PPDDR REG_ACCESS(WoReg, 0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ -#define REG_PIOA_PPDER REG_ACCESS(WoReg, 0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ -#define REG_PIOA_PPDSR REG_ACCESS(RoReg, 0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ -#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ -#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ -#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ -#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ -#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ -#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ -#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ -#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ -#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ -#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ -#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ -#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ -#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOA) Lock Status */ -#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ -#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ -#define REG_PIOA_SCHMITT REG_ACCESS(RwReg, 0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ -#define REG_PIOA_PCMR REG_ACCESS(RwReg, 0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ -#define REG_PIOA_PCIER REG_ACCESS(WoReg, 0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ -#define REG_PIOA_PCIDR REG_ACCESS(WoReg, 0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ -#define REG_PIOA_PCIMR REG_ACCESS(RoReg, 0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ -#define REG_PIOA_PCISR REG_ACCESS(RoReg, 0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ -#define REG_PIOA_PCRHR REG_ACCESS(RoReg, 0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ -/* ========== Register definition for PIOB peripheral ========== */ -#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ -#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ -#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOB) PIO Status Register */ -#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOB) Output Enable Register */ -#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOB) Output Disable Register */ -#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOB) Output Status Register */ -#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ -#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ -#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ -#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ -#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ -#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ -#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ -#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ -#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ -#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ -#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ -#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ -#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ -#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ -#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ -#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ -#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ -#define REG_PIOB_ABCDSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ -#define REG_PIOB_SCIFSR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ -#define REG_PIOB_DIFSR REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ -#define REG_PIOB_IFDGSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ -#define REG_PIOB_PPDDR REG_ACCESS(WoReg, 0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ -#define REG_PIOB_PPDER REG_ACCESS(WoReg, 0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ -#define REG_PIOB_PPDSR REG_ACCESS(RoReg, 0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ -#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ -#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ -#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ -#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ -#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ -#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ -#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ -#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOB) Level Select Register */ -#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ -#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ -#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ -#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ -#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOB) Lock Status */ -#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ -#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ -#define REG_PIOB_SCHMITT REG_ACCESS(RwReg, 0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ -#define REG_PIOB_PCMR REG_ACCESS(RwReg, 0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ -#define REG_PIOB_PCIER REG_ACCESS(WoReg, 0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ -#define REG_PIOB_PCIDR REG_ACCESS(WoReg, 0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ -#define REG_PIOB_PCIMR REG_ACCESS(RoReg, 0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ -#define REG_PIOB_PCISR REG_ACCESS(RoReg, 0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ -#define REG_PIOB_PCRHR REG_ACCESS(RoReg, 0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ -/* ========== Register definition for PIOC peripheral ========== */ -#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ -#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ -#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1208U) /**< \brief (PIOC) PIO Status Register */ -#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (PIOC) Output Enable Register */ -#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1214U) /**< \brief (PIOC) Output Disable Register */ -#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1218U) /**< \brief (PIOC) Output Status Register */ -#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ -#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ -#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ -#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ -#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ -#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ -#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ -#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ -#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ -#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ -#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ -#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ -#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ -#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ -#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ -#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ -#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ -#define REG_PIOC_ABCDSR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ -#define REG_PIOC_SCIFSR REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ -#define REG_PIOC_DIFSR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ -#define REG_PIOC_IFDGSR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ -#define REG_PIOC_PPDDR REG_ACCESS(WoReg, 0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ -#define REG_PIOC_PPDER REG_ACCESS(WoReg, 0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ -#define REG_PIOC_PPDSR REG_ACCESS(RoReg, 0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ -#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ -#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ -#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ -#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ -#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ -#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ -#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ -#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E12C4U) /**< \brief (PIOC) Level Select Register */ -#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ -#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ -#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ -#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ -#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E12E0U) /**< \brief (PIOC) Lock Status */ -#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ -#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ -#define REG_PIOC_SCHMITT REG_ACCESS(RwReg, 0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ -#define REG_PIOC_PCMR REG_ACCESS(RwReg, 0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ -#define REG_PIOC_PCIER REG_ACCESS(WoReg, 0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ -#define REG_PIOC_PCIDR REG_ACCESS(WoReg, 0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ -#define REG_PIOC_PCIMR REG_ACCESS(RoReg, 0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ -#define REG_PIOC_PCISR REG_ACCESS(RoReg, 0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ -#define REG_PIOC_PCRHR REG_ACCESS(RoReg, 0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ -/* ========== Register definition for RSTC peripheral ========== */ -#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1400U) /**< \brief (RSTC) Control Register */ -#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1404U) /**< \brief (RSTC) Status Register */ -#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1408U) /**< \brief (RSTC) Mode Register */ -/* ========== Register definition for SUPC peripheral ========== */ -#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ -#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ -#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ -#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ -#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ -#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ -/* ========== Register definition for RTT peripheral ========== */ -#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1430U) /**< \brief (RTT) Mode Register */ -#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1434U) /**< \brief (RTT) Alarm Register */ -#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1438U) /**< \brief (RTT) Value Register */ -#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E143CU) /**< \brief (RTT) Status Register */ -/* ========== Register definition for WDT peripheral ========== */ -#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1450U) /**< \brief (WDT) Control Register */ -#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1454U) /**< \brief (WDT) Mode Register */ -#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1458U) /**< \brief (WDT) Status Register */ -/* ========== Register definition for RTC peripheral ========== */ -#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1460U) /**< \brief (RTC) Control Register */ -#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1464U) /**< \brief (RTC) Mode Register */ -#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1468U) /**< \brief (RTC) Time Register */ -#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E146CU) /**< \brief (RTC) Calendar Register */ -#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1470U) /**< \brief (RTC) Time Alarm Register */ -#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ -#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1478U) /**< \brief (RTC) Status Register */ -#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ -#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ -#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ -#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ -#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E148CU) /**< \brief (RTC) Valid Entry Register */ -/* ========== Register definition for GPBR peripheral ========== */ -#define REG_GPBR_GPBR0 REG_ACCESS(RwReg, 0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register 0 */ -#define REG_GPBR_GPBR1 REG_ACCESS(RwReg, 0x400E1494U) /**< \brief (GPBR) General Purpose Backup Register 1 */ -#define REG_GPBR_GPBR2 REG_ACCESS(RwReg, 0x400E1498U) /**< \brief (GPBR) General Purpose Backup Register 2 */ -#define REG_GPBR_GPBR3 REG_ACCESS(RwReg, 0x400E149CU) /**< \brief (GPBR) General Purpose Backup Register 3 */ -/*@}*/ - -/* ***************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */ -#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ -#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ -#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ -#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ -#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ -#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ -#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ -#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ -#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ -#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ -#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ -#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ -#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ -#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ -#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ -#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ -#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ -#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ -#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ -/*@}*/ - -/* ***************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_base Peripheral Base Address Definitions */ -/*@{*/ - -#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define PDC_HSMCI CAST(Pdc , 0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ -#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */ -#define PDC_SSC CAST(Pdc , 0x40004100U) /**< \brief (PDC_SSC ) Base Address */ -#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */ -#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */ -#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */ -#define TC1 CAST(Tc , 0x40014000U) /**< \brief (TC1 ) Base Address */ -#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 CAST(Pdc , 0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM CAST(Pdc , 0x40020100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 CAST(Usart , 0x40028000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 CAST(Pdc , 0x40028100U) /**< \brief (PDC_USART1) Base Address */ -#define UDP CAST(Udp , 0x40034000U) /**< \brief (UDP ) Base Address */ -#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */ -#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ -#define ACC CAST(Acc , 0x40040000U) /**< \brief (ACC ) Base Address */ -#define CRCCU CAST(Crccu , 0x40044000U) /**< \brief (CRCCU ) Base Address */ -#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */ -#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */ -#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */ -#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ -#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */ -#define PDC_UART1 CAST(Pdc , 0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ -#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC CAST(Pio , 0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */ -#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */ -#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */ -#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */ -#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */ -#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */ -/*@}*/ - -/* ***************************************************************************** */ -/* PIO DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_pio Peripheral Pio Definitions */ -/*@{*/ - -#define PIO_PA0 (1 << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1 << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1 << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1 << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1 << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1 << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1 << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1 << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1 << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1 << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1 << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1 << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1 << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1 << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1 << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1 << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1 << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1 << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1 << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1 << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1 << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1 << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1 << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1 << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1 << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1 << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1 << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1 << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1 << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1 << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1 << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1 << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1 << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1 << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1 << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1 << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1 << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1 << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1 << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1 << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1 << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1 << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1 << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1 << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1 << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1 << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1 << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PC0 (1 << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1 << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1 << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1 << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1 << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1 << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1 << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1 << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1 << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1 << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1 << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1 << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1 << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1 << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1 << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1 << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1 << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1 << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1 << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1 << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1 << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1 << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1 << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1 << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1 << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1 << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1 << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1 << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1 << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1 << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1 << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PC31 (1 << 31) /**< \brief Pin Controlled by PC31 */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA28C_MCCDA (1 << 28) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PA29C_MCCK (1 << 29) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA30C_MCDA0 (1 << 30) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA31C_MCDA1 (1 << 31) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA26C_MCDA2 (1 << 26) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA27C_MCDA3 (1 << 27) /**< \brief Hsmci signal: MCDA3 */ -/* ========== Pio definition for SSC peripheral ========== */ -#define PIO_PA18A_RD (1 << 18) /**< \brief Ssc signal: RD */ -#define PIO_PA20A_RF (1 << 20) /**< \brief Ssc signal: RF */ -#define PIO_PA19A_RK (1 << 19) /**< \brief Ssc signal: RK */ -#define PIO_PA17A_TD (1 << 17) /**< \brief Ssc signal: TD */ -#define PIO_PA15A_TF (1 << 15) /**< \brief Ssc signal: TF */ -#define PIO_PA16A_TK (1 << 16) /**< \brief Ssc signal: TK */ -/* ========== Pio definition for SPI peripheral ========== */ -#define PIO_PA12A_MISO (1 << 12) /**< \brief Spi signal: MISO */ -#define PIO_PA13A_MOSI (1 << 13) /**< \brief Spi signal: MOSI */ -#define PIO_PA11A_NPCS0 (1 << 11) /**< \brief Spi signal: NPCS0 */ -#define PIO_PA31A_NPCS1 (1 << 31) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA9B_NPCS1 (1 << 9) /**< \brief Spi signal: NPCS1 */ -#define PIO_PB14A_NPCS1 (1 << 14) /**< \brief Spi signal: NPCS1 */ -#define PIO_PC4B_NPCS1 (1 << 4) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA10B_NPCS2 (1 << 10) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA30B_NPCS2 (1 << 30) /**< \brief Spi signal: NPCS2 */ -#define PIO_PB2B_NPCS2 (1 << 2) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA22B_NPCS3 (1 << 22) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA3B_NPCS3 (1 << 3) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA5B_NPCS3 (1 << 5) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA14A_SPCK (1 << 14) /**< \brief Spi signal: SPCK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA4B_TCLK0 (1 << 4) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA28B_TCLK1 (1 << 28) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA29B_TCLK2 (1 << 29) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA0B_TIOA0 (1 << 0) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA15B_TIOA1 (1 << 15) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA26B_TIOA2 (1 << 26) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA1B_TIOB0 (1 << 1) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA16B_TIOB1 (1 << 16) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA27B_TIOB2 (1 << 27) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PC25B_TCLK3 (1 << 25) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PC28B_TCLK4 (1 << 28) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PC31B_TCLK5 (1 << 31) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PC23B_TIOA3 (1 << 23) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PC26B_TIOA4 (1 << 26) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PC29B_TIOA5 (1 << 29) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PC24B_TIOB3 (1 << 24) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PC27B_TIOB4 (1 << 27) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PC30B_TIOB5 (1 << 30) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA4A_TWCK0 (1 << 4) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA3A_TWD0 (1 << 3) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB5A_TWCK1 (1 << 5) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB4A_TWD1 (1 << 4) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA9C_PWMFI0 (1 << 9) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA11B_PWMH0 (1 << 11) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA23B_PWMH0 (1 << 23) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC18B_PWMH0 (1 << 18) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA12B_PWMH1 (1 << 12) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA24B_PWMH1 (1 << 24) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC19B_PWMH1 (1 << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA13B_PWMH2 (1 << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA2A_PWMH2 (1 << 2) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA25B_PWMH2 (1 << 25) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB4B_PWMH2 (1 << 4) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC20B_PWMH2 (1 << 20) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA17C_PWMH3 (1 << 17) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA7B_PWMH3 (1 << 7) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC21B_PWMH3 (1 << 21) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA19B_PWML0 (1 << 19) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB5B_PWML0 (1 << 5) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC0B_PWML0 (1 << 0) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC13B_PWML0 (1 << 13) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA20B_PWML1 (1 << 20) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB12A_PWML1 (1 << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC1B_PWML1 (1 << 1) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC15B_PWML1 (1 << 15) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA16C_PWML2 (1 << 16) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA30A_PWML2 (1 << 30) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB13A_PWML2 (1 << 13) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC2B_PWML2 (1 << 2) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA15C_PWML3 (1 << 15) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC22B_PWML3 (1 << 22) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC3B_PWML3 (1 << 3) /**< \brief Pwm signal: PWML3 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PA8A_CTS0 (1 << 8) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PA7A_RTS0 (1 << 7) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PA5A_RXD0 (1 << 5) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PA2B_SCK0 (1 << 2) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PA6A_TXD0 (1 << 6) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA25A_CTS1 (1 << 25) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA26A_DCD1 (1 << 26) /**< \brief Usart1 signal: DCD1 */ -#define PIO_PA28A_DSR1 (1 << 28) /**< \brief Usart1 signal: DSR1 */ -#define PIO_PA27A_DTR1 (1 << 27) /**< \brief Usart1 signal: DTR1 */ -#define PIO_PA29A_RI1 (1 << 29) /**< \brief Usart1 signal: RI1 */ -#define PIO_PA24A_RTS1 (1 << 24) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA21A_RXD1 (1 << 21) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA23A_SCK1 (1 << 23) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA22A_TXD1 (1 << 22) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA17X1_AD0 (1 << 17) /**< \brief Adc signal: AD0 */ -#define PIO_PA18X1_AD1 (1 << 18) /**< \brief Adc signal: AD1 */ -#define PIO_PC13X1_AD10 (1 << 13) /**< \brief Adc signal: AD10 */ -#define PIO_PC15X1_AD11 (1 << 15) /**< \brief Adc signal: AD11 */ -#define PIO_PC12X1_AD12 (1 << 12) /**< \brief Adc signal: AD12 */ -#define PIO_PC29X1_AD13 (1 << 29) /**< \brief Adc signal: AD13 */ -#define PIO_PC30X1_AD14 (1 << 30) /**< \brief Adc signal: AD14 */ -#define PIO_PA19X1_AD2 (1 << 19) /**< \brief Adc signal: AD2 */ -#define PIO_PA20X1_AD3 (1 << 20) /**< \brief Adc signal: AD3 */ -#define PIO_PB0X1_AD4 (1 << 0) /**< \brief Adc signal: AD4 */ -#define PIO_PB1X1_AD5 (1 << 1) /**< \brief Adc signal: AD5 */ -#define PIO_PB2X1_AD6 (1 << 2) /**< \brief Adc signal: AD6 */ -#define PIO_PB3X1_AD7 (1 << 3) /**< \brief Adc signal: AD7 */ -#define PIO_PA21X1_AD8 (1 << 21) /**< \brief Adc signal: AD8 */ -#define PIO_PA22X1_AD9 (1 << 22) /**< \brief Adc signal: AD9 */ -#define PIO_PA8B_ADTRG (1 << 8) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB13X1_DAC0 (1 << 13) /**< \brief Dacc signal: DAC0 */ -#define PIO_PB14X1_DAC1 (1 << 14) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA2C_DATRG (1 << 2) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA6B_PCK0 (1 << 6) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB13B_PCK0 (1 << 13) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA17B_PCK1 (1 << 17) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA21B_PCK1 (1 << 21) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA18B_PCK2 (1 << 18) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1 << 31) /**< \brief Pmc signal: PCK2 */ -#define PIO_PB3B_PCK2 (1 << 3) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for UART0 peripheral ========== */ -#define PIO_PA9A_URXD0 (1 << 9) /**< \brief Uart0 signal: URXD0 */ -#define PIO_PA10A_UTXD0 (1 << 10) /**< \brief Uart0 signal: UTXD0 */ -/* ========== Pio definition for UART1 peripheral ========== */ -#define PIO_PB2A_URXD1 (1 << 2) /**< \brief Uart1 signal: URXD1 */ -#define PIO_PB3A_UTXD1 (1 << 3) /**< \brief Uart1 signal: UTXD1 */ -/* ========== Pio definition for PIOA peripheral ========== */ -#define PIO_PA24X1_PIODC0 (1 << 24) /**< \brief Pioa signal: PIODC0 */ -#define PIO_PA25X1_PIODC1 (1 << 25) /**< \brief Pioa signal: PIODC1 */ -#define PIO_PA26X1_PIODC2 (1 << 26) /**< \brief Pioa signal: PIODC2 */ -#define PIO_PA27X1_PIODC3 (1 << 27) /**< \brief Pioa signal: PIODC3 */ -#define PIO_PA28X1_PIODC4 (1 << 28) /**< \brief Pioa signal: PIODC4 */ -#define PIO_PA29X1_PIODC5 (1 << 29) /**< \brief Pioa signal: PIODC5 */ -#define PIO_PA30X1_PIODC6 (1 << 30) /**< \brief Pioa signal: PIODC6 */ -#define PIO_PA31X1_PIODC7 (1 << 31) /**< \brief Pioa signal: PIODC7 */ -#define PIO_PA23X1_PIODCCLK (1 << 23) /**< \brief Pioa signal: PIODCCLK */ -#define PIO_PA15X1_PIODCEN1 (1 << 15) /**< \brief Pioa signal: PIODCEN1 */ -#define PIO_PA16X1_PIODCEN2 (1 << 16) /**< \brief Pioa signal: PIODCEN2 */ -/*@}*/ - -/* ***************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ - -#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -#define AT91C_IFLASH (0x00400000) /**< Internal Flash base address */ -#define AT91C_IROM (0x00800000) /**< Internal ROM base address */ -#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -#define AT91C_EBI_CS0 (0x60000000) /**< EBI Chip Select 0 base address */ -#define AT91C_EBI_CS1 (0x61000000) /**< EBI Chip Select 1 base address */ -#define AT91C_EBI_CS2 (0x62000000) /**< EBI Chip Select 2 base address */ -#define AT91C_EBI_CS3 (0x63000000) /**< EBI Chip Select 3 base address */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* AT91SAM3S_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/chip.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/chip.h deleted file mode 100644 index 8b6984086..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/chip.h +++ /dev/null @@ -1,130 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Definition of AT91SAM3S4 characteristics and features -/// -/// !Usage -/// -# For ARM core feature, see "AT91SAM3S4 - ARM core features". -/// -# For IP features, see "AT91SAM3S4 - IP features". -/// -# For misc, see "AT91SAM3S4 - Misc". -//------------------------------------------------------------------------------ - -#ifndef CHIP_H -#define CHIP_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "AT91SAM3S4 - ARM core features" -/// This page lists several characteristics related to the ARM core -/// - -//ARM core features - -/// ARM core definition. -#define cortexm3 - -/// family definition. -#define at91sam3s - -//------------------------------------------------------------------------------ -/// \page "AT91SAM3S4 - IP features" -/// This page lists several characteristics related to the embedded IP -/// - -//IP FEATURES - -// EFC GPNVM number -#define CHIP_EFC_NUM_GPNVMS 3 - -/// Indicates chip has an Enhanced EFC. -#define CHIP_FLASH_EEFC - -// DMA channels number -#define CHIP_DMA_CHANNEL_NUM 4 - -// Indicate chip's MCI interface. -#define MCI2_INTERFACE - -// Indicate chip SSC has DMA interface. -#define CHIP_SSC_DMA - -// Indicate chip SPI has DMA interface. -#define CHIP_SPI_DMA - -/// Indicates chip has an UDP Full Speed. -#define CHIP_USB_UDP - -/// Indicates chip has an internal pull-up. -#define CHIP_USB_PULLUP_INTERNAL - -/// Number of USB endpoints -#define CHIP_USB_NUMENDPOINTS 8 - -/// Endpoints max paxcket size -#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) \ - ((i == 0) ? 64 : \ - ((i == 1) ? 64 : \ - ((i == 2) ? 64 : \ - ((i == 3) ? 64 : \ - ((i == 4) ? 512 : \ - ((i == 5) ? 512 : \ - ((i == 6) ? 64 : \ - ((i == 7) ? 64 : 0 )))))))) - -/// Endpoints Number of Bank -#define CHIP_USB_ENDPOINTS_BANKS(i) \ - ((i == 0) ? 1 : \ - ((i == 1) ? 2 : \ - ((i == 2) ? 2 : \ - ((i == 3) ? 1 : \ - ((i == 4) ? 2 : \ - ((i == 5) ? 2 : \ - ((i == 6) ? 2 : \ - ((i == 7) ? 2 : 0 )))))))) - -//------------------------------------------------------------------------------ -/// \page "AT91SAM3S4 - Misc " -/// This page lists misc features -/// - -//Misc - -#endif //#ifndef CHIP_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/flash.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/flash.icf deleted file mode 100644 index 65ac33120..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/flash.icf +++ /dev/null @@ -1,30 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Vector table start*/ -define symbol __ICFEDIT_vector_start__ = 0x000400000; /*Add for CMSIS*/ -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2000BFFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00400000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0043FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; -define symbol __ICFEDIT_size_heap__ = 0x200; - -export symbol __ICFEDIT_vector_start__; /*Add for CMSIS*/ -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors }; /*Add for CMSIS*/ -place in ROM_region { readonly }; -place in RAM_region { readwrite,,block CSTACK, block HEAP }; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/flash.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/flash.lds deleted file mode 100644 index 9d01841e2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/flash.lds +++ /dev/null @@ -1,81 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Linker script for running in internal FLASH on the AT91SAM3S4 - *----------------------------------------------------------------------------*/ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(ResetException) - -/* Memory Spaces Definitions */ -MEMORY -{ - sram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x0000C000 /* sram, 48K */ - flash (W!RX) : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* Flash, 256K */ -} - -SECTIONS -{ - .fixed : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors)) - *(.text*) - *(.rodata*) - *(.glue_7) - *(.glue_7t) - . = ALIGN(4); - _efixed = .; /* End of text section */ - } >flash - - .relocate : AT (_efixed) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc); - *(.data); - . = ALIGN(4); - _erelocate = .; - } >sram - - .bss (NOLOAD) : { - . = ALIGN(4); - _szero = .; - *(.bss) - . = ALIGN(4); - _ezero = .; - } >sram - - /* Stack in the end of SRAM */ - _estack = 0x2000BFFC; -} -end = .; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram.icf deleted file mode 100644 index 22eb374b1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram.icf +++ /dev/null @@ -1,27 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Vector table start*/ -define symbol __ICFEDIT_vector_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2000BFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x900; -define symbol __ICFEDIT_size_heap__ = 0x200; -/*-Exports-*/ -export symbol __ICFEDIT_vector_start__; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -/* define block RamVect with alignment = 8, size = __ICFEDIT_size_vectors__ { }; */ -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors }; -place in RAM_region { readonly, readwrite, block CSTACK, block HEAP }; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram.lds deleted file mode 100644 index 2d38cfcc9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram.lds +++ /dev/null @@ -1,81 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Linker script for running in internal SRAM on the AT91SAM3S4 - *----------------------------------------------------------------------------*/ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(ResetException) - -/* Memory Spaces Definitions */ -MEMORY -{ - sram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x0000C000 /* sram, 48K */ -} - -SECTIONS -{ - .fixed : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors)) - *(.text*) - *(.ramfunc) - *(.rodata*) - *(.glue_7) - *(.glue_7t) - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > sram - - .relocate : AT (_efixed) - { - . = ALIGN(4); - _srelocate = .; - *(.data) - . = ALIGN(4); - _erelocate = .; - } >sram - - .bss (NOLOAD) : { - . = ALIGN(4); - _szero = .; - *(.bss) - . = ALIGN(4); - _ezero = .; - } >sram - - /* Stack in the end of SRAM */ - _estack = 0x2000BFFC; - -} -end = .; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram_flashloader.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram_flashloader.icf deleted file mode 100644 index a954d2cba..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram_flashloader.icf +++ /dev/null @@ -1,33 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x0; -define symbol __ICFEDIT_region_ROM_end__ = 0x0; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000040; -define symbol __ICFEDIT_region_RAM_end__ = 0x2000BFFF; - -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x0200; -define symbol __ICFEDIT_size_heap__ = 0x000; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -//initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { section .intvec }; - -place at start of RAM_region { block RamTop with fixed order {readonly, section LOWEND}}; -place at end of RAM_region { block RamBottom with fixed order {section HIGHSTART, readwrite, section .init, - block CSTACK, block HEAP}}; - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram_samba.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram_samba.lds deleted file mode 100644 index 16b1dc962..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3s4/sram_samba.lds +++ /dev/null @@ -1,91 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Linker script for running in internal SRAM on the AT91SAM3S4 - *----------------------------------------------------------------------------*/ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(entry) - -/* Memory Spaces Definitions */ -MEMORY -{ - romcodesram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x01000 - sram (W!RX) : ORIGIN = 0x20001000, LENGTH = 0x0000B000 /* sram, 48K - sizeof(romcodesram) */ -} - -/* Entry point */ -/*ENTRY (ResetException)*/ - -SECTIONS -{ - /* startup code in the .isr_vector */ - .text : - { - . = ALIGN(4); - _stext = .; - KEEP(*(.isr_vector .isr_vector.*)) - *(.mailbox) - *(.text .text.*) - *(.rodata .rodata.*) - *(.glue_7) - *(.glue_7t) - *(.gcc_except_table) - *(.rodata .rodata*) - *(.gnu.linkonce.r.*) - . = ALIGN(4); - _etext = .; - } > sram - - /* data */ - .data : - { - . = ALIGN(4); - _sidata = .; - _sdata = .; - - *(.data) - *(.data.*) - . = ALIGN(4); - _edata = .; - } > sram - - .bss (NOLOAD) : { - _szero = .; - *(.bss) - . = ALIGN(4); - _ezero = .; - } >sram - - /* Stack in SRAM */ - _sstack = 0x2000BFFC; -} -end = .; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/AT91SAM3U4.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/AT91SAM3U4.h deleted file mode 100644 index 64101aa0c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/AT91SAM3U4.h +++ /dev/null @@ -1,7439 +0,0 @@ -/* ---------------------------------------------------------------------------- */ -/* Atmel Microcontroller Software Support */ -/* ---------------------------------------------------------------------------- */ -/* Copyright (c) 2009, Atmel Corporation */ -/* */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following condition is met: */ -/* */ -/* - Redistributions of source code must retain the above copyright notice, */ -/* this list of conditions and the disclaimer below. */ -/* */ -/* Atmel's name may not be used to endorse or promote products derived from */ -/* this software without specific prior written permission. */ -/* */ -/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ -/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ -/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ -/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ -/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ -/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ -/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ -/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ -/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* ---------------------------------------------------------------------------- */ -/* */ -/* File Name : AT91SAM3U.h */ -/* Object : AT91SAM3U definitions */ -/* Generated by : AT91 SW Application Group */ -/* Generated on : 2009-09-10 */ - -#ifndef AT91SAM3U_H -#define AT91SAM3U_H - -/** \addtogroup AT91SAM3U_definitions AT91SAM3U definitions - This file defines all structures and symbols for AT91SAM3U: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __ASSEMBLY__ -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *) value) -#define REG_ACCESS(type, address) (*(type*)address) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ***************************************************************************** */ -/* CMSIS DEFINITIONS FOR AT91SAM3U */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3U_cmsis CMSIS Definitions */ - -/*@{*/ - -/** - * \brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __MPU_PRESENT 0 /**< AT91SAM3U does not provide a MPU present or not */ -#define __NVIC_PRIO_BITS 4 /**< AT91SAM3U uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ -/****** AT91SAM3U specific Interrupt Numbers *****************************************/ - - SUPC_IRQn = 0, /**< 0 AT91SAM3U Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 AT91SAM3U Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 AT91SAM3U Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 AT91SAM3U Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 AT91SAM3U Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 AT91SAM3U Power Management Controller (PMC) */ - EFC0_IRQn = 6, /**< 6 AT91SAM3U Enhanced Embedded Flash Controller 0 (EFC0) */ - EFC1_IRQn = 7, /**< 7 AT91SAM3U Enhanced Embedded Flash Controller 1 (EFC1) */ - UART_IRQn = 8, /**< 8 AT91SAM3U Universal Asynchronous Receiver Transmitter (UART) */ - SMC_IRQn = 9, /**< 9 AT91SAM3U Static Memory Controller (SMC) */ - PIOA_IRQn = 10, /**< 10 AT91SAM3U Parallel I/O Controller A, (PIOA) */ - PIOB_IRQn = 11, /**< 11 AT91SAM3U Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 12, /**< 12 AT91SAM3U Parallel I/O Controller C (PIOC) */ - USART0_IRQn = 13, /**< 13 AT91SAM3U USART 0 (USART0) */ - USART1_IRQn = 14, /**< 14 AT91SAM3U USART 1 (USART1) */ - USART2_IRQn = 15, /**< 15 AT91SAM3U USART 2 (USART2) */ - USART3_IRQn = 16, /**< 16 AT91SAM3U USART 3 (USART3) */ - HSMCI_IRQn = 17, /**< 17 AT91SAM3U High Speed Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 18, /**< 18 AT91SAM3U Two-Wire Interface 0 (TWI0) */ - TWI1_IRQn = 19, /**< 19 AT91SAM3U Two-Wire Interface 1 (TWI1) */ - SPI_IRQn = 20, /**< 20 AT91SAM3U Serial Peripheral Interface (SPI) */ - SSC_IRQn = 21, /**< 21 AT91SAM3U Synchronous Serial Controller (SSC) */ - TC0_IRQn = 22, /**< 22 AT91SAM3U Timer Counter 0 (TC0) */ - TC1_IRQn = 23, /**< 23 AT91SAM3U Timer Counter 1 (TC1) */ - TC2_IRQn = 24, /**< 24 AT91SAM3U Timer Counter 2 (TC2) */ - PWM_IRQn = 25, /**< 25 AT91SAM3U Pulse Width Modulation Controller (PWM) */ - ADC12B_IRQn = 26, /**< 26 AT91SAM3U 12-bit ADC Controller (ADC12B) */ - ADC_IRQn = 27, /**< 27 AT91SAM3U 10-bit ADC Controller (ADC) */ - DMAC_IRQn = 28, /**< 28 AT91SAM3U DMA Controller (DMAC) */ - UDPHS_IRQn = 29, /**< 29 AT91SAM3U USB Device High Speed (UDPHS) */ -} IRQn_Type; -/*@}*/ - -/* ***************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR AT91SAM3U */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3U_api Peripheral Software API */ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_ADC12B Analog-to-digital Converter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Adc12b hardware registers */ -typedef struct { - WoReg ADC_CR; /**< \brief (Adc12b Offset: 0x00) Control Register */ - RwReg ADC_MR; /**< \brief (Adc12b Offset: 0x04) Mode Register */ - RwReg Reserved1[2]; - WoReg ADC_CHER; /**< \brief (Adc12b Offset: 0x10) Channel Enable Register */ - WoReg ADC_CHDR; /**< \brief (Adc12b Offset: 0x14) Channel Disable Register */ - RoReg ADC_CHSR; /**< \brief (Adc12b Offset: 0x18) Channel Status Register */ - RoReg ADC_SR; /**< \brief (Adc12b Offset: 0x1C) Status Register */ - RoReg ADC_LCDR; /**< \brief (Adc12b Offset: 0x20) Last Converted Data Register */ - WoReg ADC_IER; /**< \brief (Adc12b Offset: 0x24) Interrupt Enable Register */ - WoReg ADC_IDR; /**< \brief (Adc12b Offset: 0x28) Interrupt Disable Register */ - RoReg ADC_IMR; /**< \brief (Adc12b Offset: 0x2C) Interrupt Mask Register */ - RoReg ADC_CDR[8]; /**< \brief (Adc12b Offset: 0x30) Channel Data Register */ - RwReg Reserved2[5]; - RwReg ADC_ACR; /**< \brief (Adc12b Offset: 0x64) Analog Control Register */ - RwReg ADC_EMR; /**< \brief (Adc12b Offset: 0x68) Extended Mode Register */ - RwReg Reserved3[37]; - RwReg ADC_RPR; /**< \brief (Adc12b Offset: 0x100) Receive Pointer Register */ - RwReg ADC_RCR; /**< \brief (Adc12b Offset: 0x104) Receive Counter Register */ - RwReg ADC_TPR; /**< \brief (Adc12b Offset: 0x108) Transmit Pointer Register */ - RwReg ADC_TCR; /**< \brief (Adc12b Offset: 0x10C) Transmit Counter Register */ - RwReg ADC_RNPR; /**< \brief (Adc12b Offset: 0x110) Receive Next Pointer Register */ - RwReg ADC_RNCR; /**< \brief (Adc12b Offset: 0x114) Receive Next Counter Register */ - RwReg ADC_TNPR; /**< \brief (Adc12b Offset: 0x118) Transmit Next Pointer Register */ - RwReg ADC_TNCR; /**< \brief (Adc12b Offset: 0x11C) Transmit Next Counter Register */ - WoReg ADC_PTCR; /**< \brief (Adc12b Offset: 0x120) Transfer Control Register */ - RoReg ADC_PTSR; /**< \brief (Adc12b Offset: 0x124) Transfer Status Register */ -} Adc12b; -#endif /* __ASSEMBLY__ */ -/* -------- ADC_CR : (ADC12B Offset: 0x00) Control Register -------- */ -#define ADC_CR_SWRST (0x1 << 0) /**< \brief (ADC_CR) Software Reset */ -#define ADC_CR_START (0x1 << 1) /**< \brief (ADC_CR) Start Conversion */ -/* -------- ADC_MR : (ADC12B Offset: 0x04) Mode Register -------- */ -#define ADC_MR_TRGEN (0x1 << 0) /**< \brief (ADC_MR) Trigger Enable */ -#define ADC_MR_TRGSEL (0x7 << 1) /**< \brief (ADC_MR) Trigger Selection */ -#define ADC_MR_LOWRES (0x1 << 4) /**< \brief (ADC_MR) Resolution */ -#define ADC_MR_SLEEP (0x1 << 5) /**< \brief (ADC_MR) Sleep Mode */ -#define ADC_MR_PRESCAL (0xff << 8) /**< \brief (ADC_MR) Prescaler Rate Selection */ -#define ADC_MR_STARTUP (0xff << 16) /**< \brief (ADC_MR) Start Up Time */ -#define ADC_MR_SHTIM (0xf << 24) /**< \brief (ADC_MR) Sample & Hold Time */ -/* -------- ADC_CHER : (ADC12B Offset: 0x10) Channel Enable Register -------- */ -#define ADC_CHER_CH0 (0x1 << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ -#define ADC_CHER_CH1 (0x1 << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ -#define ADC_CHER_CH2 (0x1 << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ -#define ADC_CHER_CH3 (0x1 << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ -#define ADC_CHER_CH4 (0x1 << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ -#define ADC_CHER_CH5 (0x1 << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ -#define ADC_CHER_CH6 (0x1 << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ -#define ADC_CHER_CH7 (0x1 << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ -/* -------- ADC_CHDR : (ADC12B Offset: 0x14) Channel Disable Register -------- */ -#define ADC_CHDR_CH0 (0x1 << 0) /**< \brief (ADC_CHDR) */ -#define ADC_CHDR_CH1 (0x1 << 1) /**< \brief (ADC_CHDR) */ -#define ADC_CHDR_CH2 (0x1 << 2) /**< \brief (ADC_CHDR) */ -#define ADC_CHDR_CH3 (0x1 << 3) /**< \brief (ADC_CHDR) */ -#define ADC_CHDR_CH4 (0x1 << 4) /**< \brief (ADC_CHDR) */ -#define ADC_CHDR_CH5 (0x1 << 5) /**< \brief (ADC_CHDR) */ -#define ADC_CHDR_CH6 (0x1 << 6) /**< \brief (ADC_CHDR) */ -#define ADC_CHDR_CH7 (0x1 << 7) /**< \brief (ADC_CHDR) */ -/* -------- ADC_CHSR : (ADC12B Offset: 0x18) Channel Status Register -------- */ -#define ADC_CHSR_CH0 (0x1 << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ -#define ADC_CHSR_CH1 (0x1 << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ -#define ADC_CHSR_CH2 (0x1 << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ -#define ADC_CHSR_CH3 (0x1 << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ -#define ADC_CHSR_CH4 (0x1 << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ -#define ADC_CHSR_CH5 (0x1 << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ -#define ADC_CHSR_CH6 (0x1 << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ -#define ADC_CHSR_CH7 (0x1 << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ -/* -------- ADC_SR : (ADC12B Offset: 0x1C) Status Register -------- */ -#define ADC_SR_EOC0 (0x1 << 0) /**< \brief (ADC_SR) End of Conversion 0 */ -#define ADC_SR_EOC1 (0x1 << 1) /**< \brief (ADC_SR) End of Conversion 1 */ -#define ADC_SR_EOC2 (0x1 << 2) /**< \brief (ADC_SR) End of Conversion 2 */ -#define ADC_SR_EOC3 (0x1 << 3) /**< \brief (ADC_SR) End of Conversion 3 */ -#define ADC_SR_EOC4 (0x1 << 4) /**< \brief (ADC_SR) End of Conversion 4 */ -#define ADC_SR_EOC5 (0x1 << 5) /**< \brief (ADC_SR) End of Conversion 5 */ -#define ADC_SR_EOC6 (0x1 << 6) /**< \brief (ADC_SR) End of Conversion 6 */ -#define ADC_SR_EOC7 (0x1 << 7) /**< \brief (ADC_SR) End of Conversion 7 */ -#define ADC_SR_OVRE0 (0x1 << 8) /**< \brief (ADC_SR) Overrun Error 0 */ -#define ADC_SR_OVRE1 (0x1 << 9) /**< \brief (ADC_SR) Overrun Error 1 */ -#define ADC_SR_OVRE2 (0x1 << 10) /**< \brief (ADC_SR) Overrun Error 2 */ -#define ADC_SR_OVRE3 (0x1 << 11) /**< \brief (ADC_SR) Overrun Error 3 */ -#define ADC_SR_OVRE4 (0x1 << 12) /**< \brief (ADC_SR) Overrun Error 4 */ -#define ADC_SR_OVRE5 (0x1 << 13) /**< \brief (ADC_SR) Overrun Error 5 */ -#define ADC_SR_OVRE6 (0x1 << 14) /**< \brief (ADC_SR) Overrun Error 6 */ -#define ADC_SR_OVRE7 (0x1 << 15) /**< \brief (ADC_SR) Overrun Error 7 */ -#define ADC_SR_DRDY (0x1 << 16) /**< \brief (ADC_SR) Data Ready */ -#define ADC_SR_GOVRE (0x1 << 17) /**< \brief (ADC_SR) General Overrun Error */ -#define ADC_SR_ENDRX (0x1 << 18) /**< \brief (ADC_SR) End of RX Buffer */ -#define ADC_SR_RXBUFF (0x1 << 19) /**< \brief (ADC_SR) RX Buffer Full */ -/* -------- ADC_LCDR : (ADC12B Offset: 0x20) Last Converted Data Register -------- */ -#define ADC_LCDR_LDATA (0xfff << 0) /**< \brief (ADC_LCDR) Last Data Converted */ -/* -------- ADC_IER : (ADC12B Offset: 0x24) Interrupt Enable Register -------- */ -#define ADC_IER_EOC0 (0x1 << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ -#define ADC_IER_EOC1 (0x1 << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ -#define ADC_IER_EOC2 (0x1 << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ -#define ADC_IER_EOC3 (0x1 << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ -#define ADC_IER_EOC4 (0x1 << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ -#define ADC_IER_EOC5 (0x1 << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ -#define ADC_IER_EOC6 (0x1 << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ -#define ADC_IER_EOC7 (0x1 << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ -#define ADC_IER_OVRE0 (0x1 << 8) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 0 */ -#define ADC_IER_OVRE1 (0x1 << 9) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 1 */ -#define ADC_IER_OVRE2 (0x1 << 10) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 2 */ -#define ADC_IER_OVRE3 (0x1 << 11) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 3 */ -#define ADC_IER_OVRE4 (0x1 << 12) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 4 */ -#define ADC_IER_OVRE5 (0x1 << 13) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 5 */ -#define ADC_IER_OVRE6 (0x1 << 14) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 6 */ -#define ADC_IER_OVRE7 (0x1 << 15) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 7 */ -#define ADC_IER_DRDY (0x1 << 16) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ -#define ADC_IER_GOVRE (0x1 << 17) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ -#define ADC_IER_ENDRX (0x1 << 18) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ -#define ADC_IER_RXBUFF (0x1 << 19) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ -/* -------- ADC_IDR : (ADC12B Offset: 0x28) Interrupt Disable Register -------- */ -#define ADC_IDR_EOC0 (0x1 << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ -#define ADC_IDR_EOC1 (0x1 << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ -#define ADC_IDR_EOC2 (0x1 << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ -#define ADC_IDR_EOC3 (0x1 << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ -#define ADC_IDR_EOC4 (0x1 << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ -#define ADC_IDR_EOC5 (0x1 << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ -#define ADC_IDR_EOC6 (0x1 << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ -#define ADC_IDR_EOC7 (0x1 << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ -#define ADC_IDR_OVRE0 (0x1 << 8) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 0 */ -#define ADC_IDR_OVRE1 (0x1 << 9) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 1 */ -#define ADC_IDR_OVRE2 (0x1 << 10) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 2 */ -#define ADC_IDR_OVRE3 (0x1 << 11) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 3 */ -#define ADC_IDR_OVRE4 (0x1 << 12) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 4 */ -#define ADC_IDR_OVRE5 (0x1 << 13) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 5 */ -#define ADC_IDR_OVRE6 (0x1 << 14) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 6 */ -#define ADC_IDR_OVRE7 (0x1 << 15) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 7 */ -#define ADC_IDR_DRDY (0x1 << 16) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ -#define ADC_IDR_GOVRE (0x1 << 17) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ -#define ADC_IDR_ENDRX (0x1 << 18) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ -#define ADC_IDR_RXBUFF (0x1 << 19) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ -/* -------- ADC_IMR : (ADC12B Offset: 0x2C) Interrupt Mask Register -------- */ -#define ADC_IMR_EOC0 (0x1 << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ -#define ADC_IMR_EOC1 (0x1 << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ -#define ADC_IMR_EOC2 (0x1 << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ -#define ADC_IMR_EOC3 (0x1 << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ -#define ADC_IMR_EOC4 (0x1 << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ -#define ADC_IMR_EOC5 (0x1 << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ -#define ADC_IMR_EOC6 (0x1 << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ -#define ADC_IMR_EOC7 (0x1 << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ -#define ADC_IMR_OVRE0 (0x1 << 8) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 0 */ -#define ADC_IMR_OVRE1 (0x1 << 9) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 1 */ -#define ADC_IMR_OVRE2 (0x1 << 10) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 2 */ -#define ADC_IMR_OVRE3 (0x1 << 11) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 3 */ -#define ADC_IMR_OVRE4 (0x1 << 12) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 4 */ -#define ADC_IMR_OVRE5 (0x1 << 13) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 5 */ -#define ADC_IMR_OVRE6 (0x1 << 14) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 6 */ -#define ADC_IMR_OVRE7 (0x1 << 15) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 7 */ -#define ADC_IMR_DRDY (0x1 << 16) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ -#define ADC_IMR_GOVRE (0x1 << 17) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ -#define ADC_IMR_ENDRX (0x1 << 18) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ -#define ADC_IMR_RXBUFF (0x1 << 19) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ -/* -------- ADC_CDR[8] : (ADC12B Offset: 0x30) Channel Data Register -------- */ -#define ADC_CDR_DATA (0xfff << 0) /**< \brief (ADC_CDR[8]) Converted Data */ -/* -------- ADC_ACR : (ADC12B Offset: 0x64) Analog Control Register -------- */ -#define ADC_ACR_GAIN (0x3 << 0) /**< \brief (ADC_ACR) Input Gain */ -#define ADC_ACR_IBCTL (0x3 << 6) /**< \brief (ADC_ACR) Bias Current Control */ -#define ADC_ACR_DIFF (0x1 << 16) /**< \brief (ADC_ACR) Differential Mode */ -#define ADC_ACR_OFFSET (0x1 << 17) /**< \brief (ADC_ACR) Input OFFSET */ -/* -------- ADC_EMR : (ADC12B Offset: 0x68) Extended Mode Register -------- */ -#define ADC_EMR_OFFMODES (0x1 << 0) /**< \brief (ADC_EMR) Off Mode if Sleep Bit (ADC_MR) = 1 */ -#define ADC_EMR_OFF_MODE_STARTUP_TIME (0xff << 16) /**< \brief (ADC_EMR) Startup Time */ -/* -------- ADC_RPR : (ADC12B Offset: 0x100) Receive Pointer Register -------- */ -#define ADC_RPR_RXPTR (0xffffffff << 0) /**< \brief (ADC_RPR) Receive Pointer Register */ -/* -------- ADC_RCR : (ADC12B Offset: 0x104) Receive Counter Register -------- */ -#define ADC_RCR_RXCTR (0xffff << 0) /**< \brief (ADC_RCR) Receive Counter Register */ -/* -------- ADC_TPR : (ADC12B Offset: 0x108) Transmit Pointer Register -------- */ -#define ADC_TPR_TXPTR (0xffffffff << 0) /**< \brief (ADC_TPR) Transmit Counter Register */ -/* -------- ADC_TCR : (ADC12B Offset: 0x10C) Transmit Counter Register -------- */ -#define ADC_TCR_TXCTR (0xffff << 0) /**< \brief (ADC_TCR) Transmit Counter Register */ -/* -------- ADC_RNPR : (ADC12B Offset: 0x110) Receive Next Pointer Register -------- */ -#define ADC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (ADC_RNPR) Receive Next Pointer */ -/* -------- ADC_RNCR : (ADC12B Offset: 0x114) Receive Next Counter Register -------- */ -#define ADC_RNCR_RXNCTR (0xffff << 0) /**< \brief (ADC_RNCR) Receive Next Counter */ -/* -------- ADC_TNPR : (ADC12B Offset: 0x118) Transmit Next Pointer Register -------- */ -#define ADC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (ADC_TNPR) Transmit Next Pointer */ -/* -------- ADC_TNCR : (ADC12B Offset: 0x11C) Transmit Next Counter Register -------- */ -#define ADC_TNCR_TXNCTR (0xffff << 0) /**< \brief (ADC_TNCR) Transmit Counter Next */ -/* -------- ADC_PTCR : (ADC12B Offset: 0x120) Transfer Control Register -------- */ -#define ADC_PTCR_RXTEN (0x1 << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ -#define ADC_PTCR_RXTDIS (0x1 << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ -#define ADC_PTCR_TXTEN (0x1 << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ -#define ADC_PTCR_TXTDIS (0x1 << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ -/* -------- ADC_PTSR : (ADC12B Offset: 0x124) Transfer Status Register -------- */ -#define ADC_PTSR_RXTEN (0x1 << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ -#define ADC_PTSR_TXTEN (0x1 << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Chip Identifier */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_CHIPID Chip Identifier */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Chipid hardware registers */ -typedef struct { - RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ - RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ -} Chipid; -#endif /* __ASSEMBLY__ */ -/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ -#define CHIPID_CIDR_VERSION (0x1f << 0) /**< \brief (CHIPID_CIDR) Version of the Device */ -#define CHIPID_CIDR_EPROC (0x7 << 5) /**< \brief (CHIPID_CIDR) Embedded Processor */ -#define CHIPID_CIDR_NVPSIZ (0xf << 8) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ -#define CHIPID_CIDR_NVPSIZ2 (0xf << 12) /**< \brief (CHIPID_CIDR) */ -#define CHIPID_CIDR_SRAMSIZ (0xf << 16) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ -#define CHIPID_CIDR_ARCH (0xff << 20) /**< \brief (CHIPID_CIDR) Architecture Identifier */ -#define CHIPID_CIDR_NVPTYP (0x7 << 28) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ -#define CHIPID_CIDR_EXT (0x1 << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ -/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ -#define CHIPID_EXID_EXID (0xffffffff << 0) /**< \brief (CHIPID_EXID) Chip ID Extension */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR DMA Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_DMAC DMA Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief DmacCh_num hardware registers */ -typedef struct { - RwReg DMAC_SADDR; /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */ - RwReg DMAC_DADDR; /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */ - RwReg DMAC_DSCR; /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */ - RwReg DMAC_CTRLA; /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */ - RwReg DMAC_CTRLB; /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */ - RwReg DMAC_CFG; /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */ - RwReg Reserved1[4]; -} DmacCh_num; -/** \brief Dmac hardware registers */ -typedef struct { - RwReg DMAC_GCFG; /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */ - RwReg DMAC_EN; /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */ - RwReg DMAC_SREQ; /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */ - RwReg DMAC_CREQ; /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */ - RwReg DMAC_LAST; /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */ - RwReg Reserved1[1]; - WoReg DMAC_EBCIER; /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. */ - WoReg DMAC_EBCIDR; /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. */ - RoReg DMAC_EBCIMR; /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. */ - RoReg DMAC_EBCISR; /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. */ - WoReg DMAC_CHER; /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */ - WoReg DMAC_CHDR; /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */ - RoReg DMAC_CHSR; /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */ - RwReg Reserved2[2]; - DmacCh_num DMAC_CH_NUM[4]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 3 */ -} Dmac; -#endif /* __ASSEMBLY__ */ -/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */ -#define DMAC_GCFG_ARB_CFG (0x1 << 4) /**< \brief (DMAC_GCFG) */ -/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */ -#define DMAC_EN_ENABLE (0x1 << 0) /**< \brief (DMAC_EN) */ -/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */ -#define DMAC_SREQ_SSREQ0 (0x1 << 0) /**< \brief (DMAC_SREQ) */ -#define DMAC_SREQ_DSREQ0 (0x1 << 1) /**< \brief (DMAC_SREQ) */ -#define DMAC_SREQ_SSREQ1 (0x1 << 2) /**< \brief (DMAC_SREQ) */ -#define DMAC_SREQ_DSREQ1 (0x1 << 3) /**< \brief (DMAC_SREQ) */ -#define DMAC_SREQ_SSREQ2_ (0x1 << 4) /**< \brief (DMAC_SREQ) */ -#define DMAC_SREQ_DSREQ2_ (0x1 << 5) /**< \brief (DMAC_SREQ) */ -#define DMAC_SREQ_SSREQ3 (0x1 << 6) /**< \brief (DMAC_SREQ) */ -#define DMAC_SREQ_DSREQ3 (0x1 << 7) /**< \brief (DMAC_SREQ) */ -/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */ -#define DMAC_CREQ_SCREQ0 (0x1 << 0) /**< \brief (DMAC_CREQ) */ -#define DMAC_CREQ_DCREQ0 (0x1 << 1) /**< \brief (DMAC_CREQ) */ -#define DMAC_CREQ_SCREQ1 (0x1 << 2) /**< \brief (DMAC_CREQ) */ -#define DMAC_CREQ_DCREQ1 (0x1 << 3) /**< \brief (DMAC_CREQ) */ -#define DMAC_CREQ_SCREQ2_ (0x1 << 4) /**< \brief (DMAC_CREQ) */ -#define DMAC_CREQ_DCREQ2_ (0x1 << 5) /**< \brief (DMAC_CREQ) */ -#define DMAC_CREQ_SCREQ3 (0x1 << 6) /**< \brief (DMAC_CREQ) */ -#define DMAC_CREQ_DCREQ3 (0x1 << 7) /**< \brief (DMAC_CREQ) */ -/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */ -#define DMAC_LAST_SLAST0 (0x1 << 0) /**< \brief (DMAC_LAST) */ -#define DMAC_LAST_DLAST0 (0x1 << 1) /**< \brief (DMAC_LAST) */ -#define DMAC_LAST_SLAST1 (0x1 << 2) /**< \brief (DMAC_LAST) */ -#define DMAC_LAST_DLAST1 (0x1 << 3) /**< \brief (DMAC_LAST) */ -#define DMAC_LAST_SLAST2 (0x1 << 4) /**< \brief (DMAC_LAST) */ -#define DMAC_LAST_DLAST2 (0x1 << 5) /**< \brief (DMAC_LAST) */ -#define DMAC_LAST_SLAST3 (0x1 << 6) /**< \brief (DMAC_LAST) */ -#define DMAC_LAST_DLAST3 (0x1 << 7) /**< \brief (DMAC_LAST) */ -/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. -------- */ -#define DMAC_EBCIER_BTC0 (0x1 << 0) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_BTC1 (0x1 << 1) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_BTC2 (0x1 << 2) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_BTC3 (0x1 << 3) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_CBTC0 (0x1 << 8) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_CBTC1 (0x1 << 9) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_CBTC2 (0x1 << 10) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_CBTC3 (0x1 << 11) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_ERR0 (0x1 << 16) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_ERR1 (0x1 << 17) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_ERR2 (0x1 << 18) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_ERR3 (0x1 << 19) /**< \brief (DMAC_EBCIER) */ -/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. -------- */ -#define DMAC_EBCIDR_BTC0 (0x1 << 0) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_BTC1 (0x1 << 1) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_BTC2 (0x1 << 2) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_BTC3 (0x1 << 3) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_CBTC0 (0x1 << 8) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_CBTC1 (0x1 << 9) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_CBTC2 (0x1 << 10) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_CBTC3 (0x1 << 11) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_ERR0 (0x1 << 16) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_ERR1 (0x1 << 17) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_ERR2 (0x1 << 18) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_ERR3 (0x1 << 19) /**< \brief (DMAC_EBCIDR) */ -/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. -------- */ -#define DMAC_EBCIMR_BTC0 (0x1 << 0) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_BTC1 (0x1 << 1) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_BTC2 (0x1 << 2) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_BTC3 (0x1 << 3) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_CBTC0 (0x1 << 8) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_CBTC1 (0x1 << 9) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_CBTC2 (0x1 << 10) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_CBTC3 (0x1 << 11) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_ERR0 (0x1 << 16) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_ERR1 (0x1 << 17) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_ERR2 (0x1 << 18) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_ERR3 (0x1 << 19) /**< \brief (DMAC_EBCIMR) */ -/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. -------- */ -#define DMAC_EBCISR_BTC0 (0x1 << 0) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_BTC1 (0x1 << 1) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_BTC2 (0x1 << 2) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_BTC3 (0x1 << 3) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_CBTC0 (0x1 << 8) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_CBTC1 (0x1 << 9) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_CBTC2 (0x1 << 10) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_CBTC3 (0x1 << 11) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_ERR0 (0x1 << 16) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_ERR1 (0x1 << 17) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_ERR2 (0x1 << 18) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_ERR3 (0x1 << 19) /**< \brief (DMAC_EBCISR) */ -/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */ -#define DMAC_CHER_ENA0 (0x1 << 0) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_ENA1 (0x1 << 1) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_ENA2 (0x1 << 2) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_ENA3 (0x1 << 3) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_SUSP0 (0x1 << 8) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_SUSP1 (0x1 << 9) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_SUSP2 (0x1 << 10) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_SUSP3 (0x1 << 11) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_KEEP0 (0x1 << 24) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_KEEP1 (0x1 << 25) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_KEEP2 (0x1 << 26) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_KEEP3 (0x1 << 27) /**< \brief (DMAC_CHER) */ -/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */ -#define DMAC_CHDR_DIS0 (0x1 << 0) /**< \brief (DMAC_CHDR) */ -#define DMAC_CHDR_DIS1 (0x1 << 1) /**< \brief (DMAC_CHDR) */ -#define DMAC_CHDR_DIS2 (0x1 << 2) /**< \brief (DMAC_CHDR) */ -#define DMAC_CHDR_DIS3 (0x1 << 3) /**< \brief (DMAC_CHDR) */ -#define DMAC_CHDR_RES0 (0x1 << 8) /**< \brief (DMAC_CHDR) */ -#define DMAC_CHDR_RES1 (0x1 << 9) /**< \brief (DMAC_CHDR) */ -#define DMAC_CHDR_RES2 (0x1 << 10) /**< \brief (DMAC_CHDR) */ -#define DMAC_CHDR_RES3 (0x1 << 11) /**< \brief (DMAC_CHDR) */ -/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */ -#define DMAC_CHSR_ENA0 (0x1 << 0) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_ENA1 (0x1 << 1) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_ENA2 (0x1 << 2) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_ENA3 (0x1 << 3) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_SUSP0 (0x1 << 8) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_SUSP1 (0x1 << 9) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_SUSP2 (0x1 << 10) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_SUSP3 (0x1 << 11) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_EMPT0 (0x1 << 16) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_EMPT1 (0x1 << 17) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_EMPT2 (0x1 << 18) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_EMPT3 (0x1 << 19) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_STAL0 (0x1 << 24) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_STAL1 (0x1 << 25) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_STAL2 (0x1 << 26) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_STAL3 (0x1 << 27) /**< \brief (DMAC_CHSR) */ -/* -------- DMAC_SADDR0 : (DMAC Offset: 0x3C) DMAC Channel Source Address Register (ch_num = 0) -------- */ -#define DMAC_SADDR0_SADDRx (0xffffffff << 0) /**< \brief (DMAC_SADDR0) */ -/* -------- DMAC_DADDR0 : (DMAC Offset: 0x40) DMAC Channel Destination Address Register (ch_num = 0) -------- */ -#define DMAC_DADDR0_DADDRx (0xffffffff << 0) /**< \brief (DMAC_DADDR0) */ -/* -------- DMAC_DSCR0 : (DMAC Offset: 0x44) DMAC Channel Descriptor Address Register (ch_num = 0) -------- */ -#define DMAC_DSCR0_DSCRx (0x3fffffff << 2) /**< \brief (DMAC_DSCR0) */ -/* -------- DMAC_CTRLA0 : (DMAC Offset: 0x48) DMAC Channel Control A Register (ch_num = 0) -------- */ -#define DMAC_CTRLA0_BTSIZE (0xfff << 0) /**< \brief (DMAC_CTRLA0) */ -#define DMAC_CTRLA0_SCSIZE (0x1 << 16) /**< \brief (DMAC_CTRLA0) */ -#define DMAC_CTRLA0_DCSIZE (0x1 << 20) /**< \brief (DMAC_CTRLA0) */ -#define DMAC_CTRLA0_SRC_WIDTH (0x3 << 24) /**< \brief (DMAC_CTRLA0) */ -#define DMAC_CTRLA0_DST_WIDTH (0x3 << 28) /**< \brief (DMAC_CTRLA0) */ -#define DMAC_CTRLA0_DONE (0x1 << 31) /**< \brief (DMAC_CTRLA0) */ -/* -------- DMAC_CTRLB0 : (DMAC Offset: 0x4C) DMAC Channel Control B Register (ch_num = 0) -------- */ -#define DMAC_CTRLB0_SRC_DSCR (0x1 << 16) /**< \brief (DMAC_CTRLB0) */ -#define DMAC_CTRLB0_DST_DSCR (0x1 << 20) /**< \brief (DMAC_CTRLB0) */ -#define DMAC_CTRLB0_FC (0x3 << 21) /**< \brief (DMAC_CTRLB0) */ -#define DMAC_CTRLB0_SRC_INCR (0x3 << 24) /**< \brief (DMAC_CTRLB0) */ -#define DMAC_CTRLB0_DST_INCR (0x3 << 28) /**< \brief (DMAC_CTRLB0) */ -#define DMAC_CTRLB0_IEN (0x1 << 30) /**< \brief (DMAC_CTRLB0) */ -/* -------- DMAC_CFG0 : (DMAC Offset: 0x50) DMAC Channel Configuration Register (ch_num = 0) -------- */ -#define DMAC_CFG0_SRC_PER (0xf << 0) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_DST_PER (0xf << 4) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_SRC_H2SEL (0x1 << 9) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_DST_H2SEL (0x1 << 13) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_SOD (0x1 << 16) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_LOCK_IF (0x1 << 20) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_LOCK_B (0x1 << 21) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_LOCK_IF_L (0x1 << 22) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_AHB_PROT (0x7 << 24) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_FIFOCFG (0x3 << 28) /**< \brief (DMAC_CFG0) */ -/* -------- DMAC_SADDR1 : (DMAC Offset: 0x64) DMAC Channel Source Address Register (ch_num = 1) -------- */ -#define DMAC_SADDR1_SADDRx (0xffffffff << 0) /**< \brief (DMAC_SADDR1) */ -/* -------- DMAC_DADDR1 : (DMAC Offset: 0x68) DMAC Channel Destination Address Register (ch_num = 1) -------- */ -#define DMAC_DADDR1_DADDRx (0xffffffff << 0) /**< \brief (DMAC_DADDR1) */ -/* -------- DMAC_DSCR1 : (DMAC Offset: 0x6C) DMAC Channel Descriptor Address Register (ch_num = 1) -------- */ -#define DMAC_DSCR1_DSCRx (0x3fffffff << 2) /**< \brief (DMAC_DSCR1) */ -/* -------- DMAC_CTRLA1 : (DMAC Offset: 0x70) DMAC Channel Control A Register (ch_num = 1) -------- */ -#define DMAC_CTRLA1_BTSIZE (0xfff << 0) /**< \brief (DMAC_CTRLA1) */ -#define DMAC_CTRLA1_SCSIZE (0x1 << 16) /**< \brief (DMAC_CTRLA1) */ -#define DMAC_CTRLA1_DCSIZE (0x1 << 20) /**< \brief (DMAC_CTRLA1) */ -#define DMAC_CTRLA1_SRC_WIDTH (0x3 << 24) /**< \brief (DMAC_CTRLA1) */ -#define DMAC_CTRLA1_DST_WIDTH (0x3 << 28) /**< \brief (DMAC_CTRLA1) */ -#define DMAC_CTRLA1_DONE (0x1 << 31) /**< \brief (DMAC_CTRLA1) */ -/* -------- DMAC_CTRLB1 : (DMAC Offset: 0x74) DMAC Channel Control B Register (ch_num = 1) -------- */ -#define DMAC_CTRLB1_SRC_DSCR (0x1 << 16) /**< \brief (DMAC_CTRLB1) */ -#define DMAC_CTRLB1_DST_DSCR (0x1 << 20) /**< \brief (DMAC_CTRLB1) */ -#define DMAC_CTRLB1_FC (0x3 << 21) /**< \brief (DMAC_CTRLB1) */ -#define DMAC_CTRLB1_SRC_INCR (0x3 << 24) /**< \brief (DMAC_CTRLB1) */ -#define DMAC_CTRLB1_DST_INCR (0x3 << 28) /**< \brief (DMAC_CTRLB1) */ -#define DMAC_CTRLB1_IEN (0x1 << 30) /**< \brief (DMAC_CTRLB1) */ -/* -------- DMAC_CFG1 : (DMAC Offset: 0x78) DMAC Channel Configuration Register (ch_num = 1) -------- */ -#define DMAC_CFG1_SRC_PER (0xf << 0) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_DST_PER (0xf << 4) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_SRC_H2SEL (0x1 << 9) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_DST_H2SEL (0x1 << 13) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_SOD (0x1 << 16) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_LOCK_IF (0x1 << 20) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_LOCK_B (0x1 << 21) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_LOCK_IF_L (0x1 << 22) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_AHB_PROT (0x7 << 24) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_FIFOCFG (0x3 << 28) /**< \brief (DMAC_CFG1) */ -/* -------- DMAC_SADDR2 : (DMAC Offset: 0x8C) DMAC Channel Source Address Register (ch_num = 2) -------- */ -#define DMAC_SADDR2_SADDRx (0xffffffff << 0) /**< \brief (DMAC_SADDR2) */ -/* -------- DMAC_DADDR2 : (DMAC Offset: 0x90) DMAC Channel Destination Address Register (ch_num = 2) -------- */ -#define DMAC_DADDR2_DADDRx (0xffffffff << 0) /**< \brief (DMAC_DADDR2) */ -/* -------- DMAC_DSCR2 : (DMAC Offset: 0x94) DMAC Channel Descriptor Address Register (ch_num = 2) -------- */ -#define DMAC_DSCR2_DSCRx (0x3fffffff << 2) /**< \brief (DMAC_DSCR2) */ -/* -------- DMAC_CTRLA2 : (DMAC Offset: 0x98) DMAC Channel Control A Register (ch_num = 2) -------- */ -#define DMAC_CTRLA2_BTSIZE (0xfff << 0) /**< \brief (DMAC_CTRLA2) */ -#define DMAC_CTRLA2_SCSIZE (0x1 << 16) /**< \brief (DMAC_CTRLA2) */ -#define DMAC_CTRLA2_DCSIZE (0x1 << 20) /**< \brief (DMAC_CTRLA2) */ -#define DMAC_CTRLA2_SRC_WIDTH (0x3 << 24) /**< \brief (DMAC_CTRLA2) */ -#define DMAC_CTRLA2_DST_WIDTH (0x3 << 28) /**< \brief (DMAC_CTRLA2) */ -#define DMAC_CTRLA2_DONE (0x1 << 31) /**< \brief (DMAC_CTRLA2) */ -/* -------- DMAC_CTRLB2 : (DMAC Offset: 0x9C) DMAC Channel Control B Register (ch_num = 2) -------- */ -#define DMAC_CTRLB2_SRC_DSCR (0x1 << 16) /**< \brief (DMAC_CTRLB2) */ -#define DMAC_CTRLB2_DST_DSCR (0x1 << 20) /**< \brief (DMAC_CTRLB2) */ -#define DMAC_CTRLB2_FC (0x3 << 21) /**< \brief (DMAC_CTRLB2) */ -#define DMAC_CTRLB2_SRC_INCR (0x3 << 24) /**< \brief (DMAC_CTRLB2) */ -#define DMAC_CTRLB2_DST_INCR (0x3 << 28) /**< \brief (DMAC_CTRLB2) */ -#define DMAC_CTRLB2_IEN (0x1 << 30) /**< \brief (DMAC_CTRLB2) */ -/* -------- DMAC_CFG2 : (DMAC Offset: 0xA0) DMAC Channel Configuration Register (ch_num = 2) -------- */ -#define DMAC_CFG2_SRC_PER (0xf << 0) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_DST_PER (0xf << 4) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_SRC_H2SEL (0x1 << 9) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_DST_H2SEL (0x1 << 13) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_SOD (0x1 << 16) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_LOCK_IF (0x1 << 20) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_LOCK_B (0x1 << 21) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_LOCK_IF_L (0x1 << 22) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_AHB_PROT (0x7 << 24) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_FIFOCFG (0x3 << 28) /**< \brief (DMAC_CFG2) */ -/* -------- DMAC_SADDR3 : (DMAC Offset: 0xB4) DMAC Channel Source Address Register (ch_num = 3) -------- */ -#define DMAC_SADDR3_SADDRx (0xffffffff << 0) /**< \brief (DMAC_SADDR3) */ -/* -------- DMAC_DADDR3 : (DMAC Offset: 0xB8) DMAC Channel Destination Address Register (ch_num = 3) -------- */ -#define DMAC_DADDR3_DADDRx (0xffffffff << 0) /**< \brief (DMAC_DADDR3) */ -/* -------- DMAC_DSCR3 : (DMAC Offset: 0xBC) DMAC Channel Descriptor Address Register (ch_num = 3) -------- */ -#define DMAC_DSCR3_DSCRx (0x3fffffff << 2) /**< \brief (DMAC_DSCR3) */ -/* -------- DMAC_CTRLA3 : (DMAC Offset: 0xC0) DMAC Channel Control A Register (ch_num = 3) -------- */ -#define DMAC_CTRLA3_BTSIZE (0xfff << 0) /**< \brief (DMAC_CTRLA3) */ -#define DMAC_CTRLA3_SCSIZE (0x1 << 16) /**< \brief (DMAC_CTRLA3) */ -#define DMAC_CTRLA3_DCSIZE (0x1 << 20) /**< \brief (DMAC_CTRLA3) */ -#define DMAC_CTRLA3_SRC_WIDTH (0x3 << 24) /**< \brief (DMAC_CTRLA3) */ -#define DMAC_CTRLA3_DST_WIDTH (0x3 << 28) /**< \brief (DMAC_CTRLA3) */ -#define DMAC_CTRLA3_DONE (0x1 << 31) /**< \brief (DMAC_CTRLA3) */ -/* -------- DMAC_CTRLB3 : (DMAC Offset: 0xC4) DMAC Channel Control B Register (ch_num = 3) -------- */ -#define DMAC_CTRLB3_SRC_DSCR (0x1 << 16) /**< \brief (DMAC_CTRLB3) */ -#define DMAC_CTRLB3_DST_DSCR (0x1 << 20) /**< \brief (DMAC_CTRLB3) */ -#define DMAC_CTRLB3_FC (0x3 << 21) /**< \brief (DMAC_CTRLB3) */ -#define DMAC_CTRLB3_SRC_INCR (0x3 << 24) /**< \brief (DMAC_CTRLB3) */ -#define DMAC_CTRLB3_DST_INCR (0x3 << 28) /**< \brief (DMAC_CTRLB3) */ -#define DMAC_CTRLB3_IEN (0x1 << 30) /**< \brief (DMAC_CTRLB3) */ -/* -------- DMAC_CFG3 : (DMAC Offset: 0xC8) DMAC Channel Configuration Register (ch_num = 3) -------- */ -#define DMAC_CFG3_SRC_PER (0xf << 0) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_DST_PER (0xf << 4) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_SRC_H2SEL (0x1 << 9) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_DST_H2SEL (0x1 << 13) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_SOD (0x1 << 16) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_LOCK_IF (0x1 << 20) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_LOCK_B (0x1 << 21) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_LOCK_IF_L (0x1 << 22) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_AHB_PROT (0x7 << 24) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_FIFOCFG (0x3 << 28) /**< \brief (DMAC_CFG3) */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_EFC Embedded Flash Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Efc hardware registers */ -typedef struct { - RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ - WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ - RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ - RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ -} Efc; -#endif /* __ASSEMBLY__ */ -/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ -#define EEFC_FMR_FRDY (0x1 << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ -#define EEFC_FMR_FWS (0xf << 8) /**< \brief (EEFC_FMR) Flash Wait State */ -#define EEFC_FMR_FAM (0x1 << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ -/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ -#define EEFC_FCR_FCMD (0xff << 0) /**< \brief (EEFC_FCR) Flash Command */ -#define EEFC_FCR_FARG (0xffff << 8) /**< \brief (EEFC_FCR) Flash Command Argument */ -#define EEFC_FCR_FKEY (0xff << 24) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ -/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ -#define EEFC_FSR_FRDY (0x1 << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ -#define EEFC_FSR_FCMDE (0x1 << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ -#define EEFC_FSR_FLOCKE (0x1 << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ -/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ -#define EEFC_FRR_FVALUE (0xffffffff << 0) /**< \brief (EEFC_FRR) Flash Result Value */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_GPBR General Purpose Backup Register */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Gpbr hardware registers */ -typedef struct { - RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */ - RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */ - RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */ - RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */ -} Gpbr; -#endif /* __ASSEMBLY__ */ -/* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */ -#define SYS_GPBR0_GPBR_VALUE0 (0xffffffff << 0) /**< \brief (SYS_GPBR0) Value of GPBR x */ -/* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */ -#define SYS_GPBR1_GPBR_VALUE1 (0xffffffff << 0) /**< \brief (SYS_GPBR1) Value of GPBR x */ -/* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */ -#define SYS_GPBR2_GPBR_VALUE2 (0xffffffff << 0) /**< \brief (SYS_GPBR2) Value of GPBR x */ -/* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */ -#define SYS_GPBR3_GPBR_VALUE3 (0xffffffff << 0) /**< \brief (SYS_GPBR3) Value of GPBR x */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR MultiMedia Card Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_HSMCI MultiMedia Card Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Hsmci hardware registers */ -typedef struct { - WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ - RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ - RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ - RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ - RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ - WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ - RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ - RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ - RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ - RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ - WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ - RwReg Reserved1[2]; - RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ - WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ - WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ - RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ - RwReg HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */ - RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ - RwReg Reserved2[35]; - RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ - RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ -} Hsmci; -#endif /* __ASSEMBLY__ */ -/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ -#define HSMCI_CR_MCIEN (0x1 << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ -#define HSMCI_CR_HSMCIDIS (0x1 << 1) /**< \brief (HSMCI_CR) */ -#define HSMCI_CR_PWSEN (0x1 << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ -#define HSMCI_CR_PWSDIS (0x1 << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ -#define HSMCI_CR_SWRST (0x1 << 7) /**< \brief (HSMCI_CR) Software Reset */ -/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ -#define HSMCI_MR_CLKDIV (0xff << 0) /**< \brief (HSMCI_MR) Clock Divider */ -#define HSMCI_MR_PWSDIV (0x7 << 8) /**< \brief (HSMCI_MR) Power Saving Divider */ -#define HSMCI_MR_RDPROOF (0x1 << 11) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_WRPROOF (0x1 << 12) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_FBYTE (0x1 << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ -#define HSMCI_MR_PADV (0x1 << 14) /**< \brief (HSMCI_MR) Padding Value */ -#define HSMCI_MR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_MR) Data Block Length */ -/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ -#define HSMCI_DTOR_DTOCYC (0xf << 0) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ -#define HSMCI_DTOR_DTOMUL (0x7 << 4) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ -/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ -#define HSMCI_SDCR_SDCSEL (0x3 << 0) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ -#define HSMCI_SDCR_SDCBUS (0x3 << 6) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ -/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ -#define HSMCI_ARGR_ARG (0xffffffff << 0) /**< \brief (HSMCI_ARGR) Command Argument */ -/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ -#define HSMCI_CMDR_CMDNB (0x3f << 0) /**< \brief (HSMCI_CMDR) Command Number */ -#define HSMCI_CMDR_RSPTYP (0x3 << 6) /**< \brief (HSMCI_CMDR) Response Type */ -#define HSMCI_CMDR_SPCMD (0x7 << 8) /**< \brief (HSMCI_CMDR) Special Command */ -#define HSMCI_CMDR_OPDCMD (0x1 << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ -#define HSMCI_CMDR_MAXLAT (0x1 << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ -#define HSMCI_CMDR_TRCMD (0x3 << 16) /**< \brief (HSMCI_CMDR) Transfer Command */ -#define HSMCI_CMDR_TRDIR (0x1 << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ -#define HSMCI_CMDR_TRTYP (0x7 << 19) /**< \brief (HSMCI_CMDR) Transfer Type */ -#define HSMCI_CMDR_IOSPCMD (0x3 << 24) /**< \brief (HSMCI_CMDR) SDIO Special Command */ -#define HSMCI_CMDR_ATACS (0x1 << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ -#define HSMCI_CMDR_BOOT_ACK (0x1 << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ -/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ -#define HSMCI_BLKR_BCNT (0xffff << 0) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ -#define HSMCI_BLKR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_BLKR) Data Block Length */ -/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ -#define HSMCI_CSTOR_CSTOCYC (0xf << 0) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ -#define HSMCI_CSTOR_CSTOMUL (0x7 << 4) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ -/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ -#define HSMCI_RSPR_RSP (0xffffffff << 0) /**< \brief (HSMCI_RSPR[4]) Response */ -/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ -#define HSMCI_RDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_RDR) Data to Read */ -/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ -#define HSMCI_TDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_TDR) Data to Write */ -/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ -#define HSMCI_SR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_SR) Command Ready */ -#define HSMCI_SR_RXRDY (0x1 << 1) /**< \brief (HSMCI_SR) Receiver Ready */ -#define HSMCI_SR_TXRDY (0x1 << 2) /**< \brief (HSMCI_SR) Transmit Ready */ -#define HSMCI_SR_BLKE (0x1 << 3) /**< \brief (HSMCI_SR) Data Block Ended */ -#define HSMCI_SR_DTIP (0x1 << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ -#define HSMCI_SR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ -#define HSMCI_SR_MCI_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_SR) */ -#define HSMCI_SR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ -#define HSMCI_SR_CSRCV (0x1 << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ -#define HSMCI_SR_RINDE (0x1 << 16) /**< \brief (HSMCI_SR) Response Index Error */ -#define HSMCI_SR_RDIRE (0x1 << 17) /**< \brief (HSMCI_SR) Response Direction Error */ -#define HSMCI_SR_RCRCE (0x1 << 18) /**< \brief (HSMCI_SR) Response CRC Error */ -#define HSMCI_SR_RENDE (0x1 << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ -#define HSMCI_SR_RTOE (0x1 << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ -#define HSMCI_SR_DCRCE (0x1 << 21) /**< \brief (HSMCI_SR) Data CRC Error */ -#define HSMCI_SR_DTOE (0x1 << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ -#define HSMCI_SR_CSTOE (0x1 << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ -#define HSMCI_SR_BLKOVRE (0x1 << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error */ -#define HSMCI_SR_DMADONE (0x1 << 25) /**< \brief (HSMCI_SR) DMA Transfer done */ -#define HSMCI_SR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ -#define HSMCI_SR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ -#define HSMCI_SR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ -#define HSMCI_SR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ -#define HSMCI_SR_OVRE (0x1 << 30) /**< \brief (HSMCI_SR) Overrun */ -#define HSMCI_SR_UNRE (0x1 << 31) /**< \brief (HSMCI_SR) Underrun */ -/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ -#define HSMCI_IER_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ -#define HSMCI_IER_RXRDY (0x1 << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ -#define HSMCI_IER_TXRDY (0x1 << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ -#define HSMCI_IER_BLKE (0x1 << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ -#define HSMCI_IER_DTIP (0x1 << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ -#define HSMCI_IER_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ -#define HSMCI_IER_MCI_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IER) */ -#define HSMCI_IER_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ -#define HSMCI_IER_CSRCV (0x1 << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ -#define HSMCI_IER_RINDE (0x1 << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ -#define HSMCI_IER_RDIRE (0x1 << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ -#define HSMCI_IER_RCRCE (0x1 << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ -#define HSMCI_IER_RENDE (0x1 << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ -#define HSMCI_IER_RTOE (0x1 << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ -#define HSMCI_IER_DCRCE (0x1 << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ -#define HSMCI_IER_DTOE (0x1 << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ -#define HSMCI_IER_CSTOE (0x1 << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ -#define HSMCI_IER_BLKOVRE (0x1 << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */ -#define HSMCI_IER_DMADONE (0x1 << 25) /**< \brief (HSMCI_IER) DMA Transfer completed Interrupt Enable */ -#define HSMCI_IER_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ -#define HSMCI_IER_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ -#define HSMCI_IER_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ -#define HSMCI_IER_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ -#define HSMCI_IER_OVRE (0x1 << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ -#define HSMCI_IER_UNRE (0x1 << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ -/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ -#define HSMCI_IDR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ -#define HSMCI_IDR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ -#define HSMCI_IDR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ -#define HSMCI_IDR_BLKE (0x1 << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ -#define HSMCI_IDR_DTIP (0x1 << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ -#define HSMCI_IDR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ -#define HSMCI_IDR_MCI_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IDR) */ -#define HSMCI_IDR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ -#define HSMCI_IDR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt disable */ -#define HSMCI_IDR_RINDE (0x1 << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ -#define HSMCI_IDR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ -#define HSMCI_IDR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ -#define HSMCI_IDR_RENDE (0x1 << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ -#define HSMCI_IDR_RTOE (0x1 << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ -#define HSMCI_IDR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ -#define HSMCI_IDR_DTOE (0x1 << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ -#define HSMCI_IDR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ -#define HSMCI_IDR_BLKOVRE (0x1 << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */ -#define HSMCI_IDR_DMADONE (0x1 << 25) /**< \brief (HSMCI_IDR) DMA Transfer completed Interrupt Disable */ -#define HSMCI_IDR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ -#define HSMCI_IDR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ -#define HSMCI_IDR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ -#define HSMCI_IDR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ -#define HSMCI_IDR_OVRE (0x1 << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ -#define HSMCI_IDR_UNRE (0x1 << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ -/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ -#define HSMCI_IMR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ -#define HSMCI_IMR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ -#define HSMCI_IMR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ -#define HSMCI_IMR_BLKE (0x1 << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ -#define HSMCI_IMR_DTIP (0x1 << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ -#define HSMCI_IMR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ -#define HSMCI_IMR_MCI_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IMR) */ -#define HSMCI_IMR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ -#define HSMCI_IMR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ -#define HSMCI_IMR_RINDE (0x1 << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ -#define HSMCI_IMR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ -#define HSMCI_IMR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ -#define HSMCI_IMR_RENDE (0x1 << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ -#define HSMCI_IMR_RTOE (0x1 << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ -#define HSMCI_IMR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ -#define HSMCI_IMR_DTOE (0x1 << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ -#define HSMCI_IMR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ -#define HSMCI_IMR_BLKOVRE (0x1 << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */ -#define HSMCI_IMR_DMADONE (0x1 << 25) /**< \brief (HSMCI_IMR) DMA Transfer Completed Interrupt Mask */ -#define HSMCI_IMR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ -#define HSMCI_IMR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ -#define HSMCI_IMR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ -#define HSMCI_IMR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ -#define HSMCI_IMR_OVRE (0x1 << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ -#define HSMCI_IMR_UNRE (0x1 << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ -/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */ -#define HSMCI_DMA_OFFSET (0x3 << 0) /**< \brief (HSMCI_DMA) DMA Write Buffer Offset */ -#define HSMCI_DMA_CHKSIZE (0x1 << 4) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */ -#define HSMCI_DMA_DMAEN (0x1 << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */ -#define HSMCI_DMA_ROPT (0x1 << 12) /**< \brief (HSMCI_DMA) Read Optimization with padding */ -/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ -#define HSMCI_CFG_FIFOMODE (0x1 << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ -#define HSMCI_CFG_FERRCTRL (0x1 << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ -#define HSMCI_CFG_HSMODE (0x1 << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ -#define HSMCI_CFG_LSYNC (0x1 << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ -/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ -#define HSMCI_WPMR_WP_EN (0x1 << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ -#define HSMCI_WPMR_WP_KEY (0xffffff << 8) /**< \brief (HSMCI_WPMR) Write Protection Key password */ -/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ -#define HSMCI_WPSR_WP_VS (0xf << 0) /**< \brief (HSMCI_WPSR) */ -#define HSMCI_WPSR_WP_VSRC (0xffff << 8) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_MATRIX AHB Bus Matrix */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Matrix hardware registers */ -typedef struct { - RwReg MATRIX_MCFG[5]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ - RwReg Reserved1[11]; - RwReg MATRIX_SCFG[10]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ - RwReg Reserved2[6]; - RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ - RwReg Reserved3[1]; - RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ - RwReg Reserved4[1]; - RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ - RwReg Reserved5[1]; - RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ - RwReg Reserved6[1]; - RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ - RwReg Reserved7[1]; - RwReg MATRIX_PRAS5; /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */ - RwReg Reserved8[1]; - RwReg MATRIX_PRAS6; /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */ - RwReg Reserved9[1]; - RwReg MATRIX_PRAS7; /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */ - RwReg Reserved10[1]; - RwReg MATRIX_PRAS8; /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */ - RwReg Reserved11[1]; - RwReg MATRIX_PRAS9; /**< \brief (Matrix Offset: 0x00C8) Priority Register A for Slave 9 */ - RwReg Reserved12[13]; - RwReg MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */ -} Matrix; -#endif /* __ASSEMBLY__ */ -/* -------- MATRIX_MCFG[5] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ -#define MATRIX_MCFG_ULBT (0x7 << 0) /**< \brief (MATRIX_MCFG[5]) Undefined Length Burst Type */ -/* -------- MATRIX_SCFG[10] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ -#define MATRIX_SCFG_SLOT_CYCLE (0xff << 0) /**< \brief (MATRIX_SCFG[10]) Maximum Number of Allowed Cycles for a Burst */ -#define MATRIX_SCFG_DEFMSTR_TYPE (0x3 << 16) /**< \brief (MATRIX_SCFG[10]) Default Master Type */ -#define MATRIX_SCFG_FIXED_DEFMSTR (0x7 << 18) /**< \brief (MATRIX_SCFG[10]) Fixed Default Master */ -#define MATRIX_SCFG_ARBT (0x3 << 24) /**< \brief (MATRIX_SCFG[10]) Arbitration Type */ -/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ -#define MATRIX_PRAS0_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ -#define MATRIX_PRAS0_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ -#define MATRIX_PRAS0_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ -#define MATRIX_PRAS0_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ -#define MATRIX_PRAS0_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ -/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ -#define MATRIX_PRAS1_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ -#define MATRIX_PRAS1_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ -#define MATRIX_PRAS1_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ -#define MATRIX_PRAS1_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ -#define MATRIX_PRAS1_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ -/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ -#define MATRIX_PRAS2_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ -#define MATRIX_PRAS2_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ -#define MATRIX_PRAS2_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ -#define MATRIX_PRAS2_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ -#define MATRIX_PRAS2_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ -/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ -#define MATRIX_PRAS3_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ -#define MATRIX_PRAS3_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ -#define MATRIX_PRAS3_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ -#define MATRIX_PRAS3_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ -#define MATRIX_PRAS3_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ -/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ -#define MATRIX_PRAS4_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ -#define MATRIX_PRAS4_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ -#define MATRIX_PRAS4_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ -#define MATRIX_PRAS4_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ -#define MATRIX_PRAS4_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ -/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */ -#define MATRIX_PRAS5_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS5) Master 0 Priority */ -#define MATRIX_PRAS5_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS5) Master 1 Priority */ -#define MATRIX_PRAS5_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS5) Master 2 Priority */ -#define MATRIX_PRAS5_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS5) Master 3 Priority */ -#define MATRIX_PRAS5_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS5) Master 4 Priority */ -/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */ -#define MATRIX_PRAS6_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS6) Master 0 Priority */ -#define MATRIX_PRAS6_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS6) Master 1 Priority */ -#define MATRIX_PRAS6_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS6) Master 2 Priority */ -#define MATRIX_PRAS6_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS6) Master 3 Priority */ -#define MATRIX_PRAS6_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS6) Master 4 Priority */ -/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */ -#define MATRIX_PRAS7_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS7) Master 0 Priority */ -#define MATRIX_PRAS7_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS7) Master 1 Priority */ -#define MATRIX_PRAS7_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS7) Master 2 Priority */ -#define MATRIX_PRAS7_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS7) Master 3 Priority */ -#define MATRIX_PRAS7_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS7) Master 4 Priority */ -/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */ -#define MATRIX_PRAS8_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS8) Master 0 Priority */ -#define MATRIX_PRAS8_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS8) Master 1 Priority */ -#define MATRIX_PRAS8_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS8) Master 2 Priority */ -#define MATRIX_PRAS8_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS8) Master 3 Priority */ -#define MATRIX_PRAS8_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS8) Master 4 Priority */ -/* -------- MATRIX_PRAS9 : (MATRIX Offset: 0x00C8) Priority Register A for Slave 9 -------- */ -#define MATRIX_PRAS9_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS9) Master 0 Priority */ -#define MATRIX_PRAS9_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS9) Master 1 Priority */ -#define MATRIX_PRAS9_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS9) Master 2 Priority */ -#define MATRIX_PRAS9_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS9) Master 3 Priority */ -#define MATRIX_PRAS9_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS9) Master 4 Priority */ -/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */ -#define MATRIX_MRCR_RCB0 (0x1 << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 0 */ -#define MATRIX_MRCR_RCB1 (0x1 << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 1 */ -#define MATRIX_MRCR_RCB2 (0x1 << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 2 */ -#define MATRIX_MRCR_RCB3 (0x1 << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 3 */ -#define MATRIX_MRCR_RCB4 (0x1 << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 4 */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_PDC Peripheral DMA Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pdc hardware registers */ -typedef struct { - RwReg Reserved1[64]; - RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x100) Receive Pointer Register */ - RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x104) Receive Counter Register */ - RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x108) Transmit Pointer Register */ - RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x10C) Transmit Counter Register */ - RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x110) Receive Next Pointer Register */ - RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x114) Receive Next Counter Register */ - RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x118) Transmit Next Pointer Register */ - RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x11C) Transmit Next Counter Register */ - WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x120) Transfer Control Register */ - RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x124) Transfer Status Register */ -} Pdc; -#endif /* __ASSEMBLY__ */ -/* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */ -#define PERIPH_RPR_RXPTR (0xffffffff << 0) /**< \brief (PERIPH_RPR) Receive Pointer Register */ -/* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */ -#define PERIPH_RCR_RXCTR (0xffff << 0) /**< \brief (PERIPH_RCR) Receive Counter Register */ -/* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */ -#define PERIPH_TPR_TXPTR (0xffffffff << 0) /**< \brief (PERIPH_TPR) Transmit Counter Register */ -/* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */ -#define PERIPH_TCR_TXCTR (0xffff << 0) /**< \brief (PERIPH_TCR) Transmit Counter Register */ -/* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */ -#define PERIPH_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ -/* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */ -#define PERIPH_RNCR_RXNCTR (0xffff << 0) /**< \brief (PERIPH_RNCR) Receive Next Counter */ -/* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PERIPH_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ -/* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PERIPH_TNCR_TXNCTR (0xffff << 0) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ -/* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */ -#define PERIPH_PTCR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ -#define PERIPH_PTCR_RXTDIS (0x1 << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ -#define PERIPH_PTCR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ -#define PERIPH_PTCR_TXTDIS (0x1 << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ -/* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */ -#define PERIPH_PTSR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ -#define PERIPH_PTSR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Parallel Input/Output */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_PIO Parallel Input/Output */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pio hardware registers */ -typedef struct { - WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ - WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ - RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ - RwReg Reserved1[1]; - WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ - WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ - RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ - RwReg Reserved2[1]; - WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ - WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ - RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ - RwReg Reserved3[1]; - WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ - WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ - RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ - RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ - WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ - WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ - RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ - RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ - WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ - WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ - RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ - RwReg Reserved4[1]; - WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ - WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ - RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ - RwReg Reserved5[1]; - RwReg PIO_ABSR; /**< \brief (Pio Offset: 0x0070) Peripheral AB Select Register */ - RwReg Reserved6[3]; - WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */ - WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */ - RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */ - RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ - RwReg Reserved7[4]; - WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ - WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ - RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ - RwReg Reserved8[1]; - WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ - WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ - RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ - RwReg Reserved9[1]; - WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ - WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ - RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ - RwReg Reserved10[1]; - WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ - WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ - RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ - RwReg Reserved11[1]; - RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ - RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ - RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ -} Pio; -#endif /* __ASSEMBLY__ */ -/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ -#define PIO_PER_P0 (0x1 << 0) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P1 (0x1 << 1) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P2 (0x1 << 2) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P3 (0x1 << 3) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P4 (0x1 << 4) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P5 (0x1 << 5) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P6 (0x1 << 6) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P7 (0x1 << 7) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P8 (0x1 << 8) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P9 (0x1 << 9) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P10 (0x1 << 10) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P11 (0x1 << 11) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P12 (0x1 << 12) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P13 (0x1 << 13) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P14 (0x1 << 14) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P15 (0x1 << 15) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P16 (0x1 << 16) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P17 (0x1 << 17) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P18 (0x1 << 18) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P19 (0x1 << 19) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P20 (0x1 << 20) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P21 (0x1 << 21) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P22 (0x1 << 22) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P23 (0x1 << 23) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P24 (0x1 << 24) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P25 (0x1 << 25) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P26 (0x1 << 26) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P27 (0x1 << 27) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P28 (0x1 << 28) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P29 (0x1 << 29) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P30 (0x1 << 30) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P31 (0x1 << 31) /**< \brief (PIO_PER) PIO Enable */ -/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ -#define PIO_PDR_P0 (0x1 << 0) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P1 (0x1 << 1) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P2 (0x1 << 2) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P3 (0x1 << 3) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P4 (0x1 << 4) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P5 (0x1 << 5) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P6 (0x1 << 6) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P7 (0x1 << 7) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P8 (0x1 << 8) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P9 (0x1 << 9) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P10 (0x1 << 10) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P11 (0x1 << 11) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P12 (0x1 << 12) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P13 (0x1 << 13) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P14 (0x1 << 14) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P15 (0x1 << 15) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P16 (0x1 << 16) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P17 (0x1 << 17) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P18 (0x1 << 18) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P19 (0x1 << 19) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P20 (0x1 << 20) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P21 (0x1 << 21) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P22 (0x1 << 22) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P23 (0x1 << 23) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P24 (0x1 << 24) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P25 (0x1 << 25) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P26 (0x1 << 26) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P27 (0x1 << 27) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P28 (0x1 << 28) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P29 (0x1 << 29) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P30 (0x1 << 30) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P31 (0x1 << 31) /**< \brief (PIO_PDR) PIO Disable */ -/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ -#define PIO_PSR_P0 (0x1 << 0) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P1 (0x1 << 1) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P2 (0x1 << 2) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P3 (0x1 << 3) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P4 (0x1 << 4) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P5 (0x1 << 5) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P6 (0x1 << 6) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P7 (0x1 << 7) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P8 (0x1 << 8) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P9 (0x1 << 9) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P10 (0x1 << 10) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P11 (0x1 << 11) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P12 (0x1 << 12) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P13 (0x1 << 13) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P14 (0x1 << 14) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P15 (0x1 << 15) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P16 (0x1 << 16) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P17 (0x1 << 17) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P18 (0x1 << 18) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P19 (0x1 << 19) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P20 (0x1 << 20) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P21 (0x1 << 21) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P22 (0x1 << 22) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P23 (0x1 << 23) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P24 (0x1 << 24) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P25 (0x1 << 25) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P26 (0x1 << 26) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P27 (0x1 << 27) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P28 (0x1 << 28) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P29 (0x1 << 29) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P30 (0x1 << 30) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P31 (0x1 << 31) /**< \brief (PIO_PSR) PIO Status */ -/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ -#define PIO_OER_P0 (0x1 << 0) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P1 (0x1 << 1) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P2 (0x1 << 2) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P3 (0x1 << 3) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P4 (0x1 << 4) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P5 (0x1 << 5) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P6 (0x1 << 6) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P7 (0x1 << 7) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P8 (0x1 << 8) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P9 (0x1 << 9) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P10 (0x1 << 10) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P11 (0x1 << 11) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P12 (0x1 << 12) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P13 (0x1 << 13) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P14 (0x1 << 14) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P15 (0x1 << 15) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P16 (0x1 << 16) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P17 (0x1 << 17) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P18 (0x1 << 18) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P19 (0x1 << 19) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P20 (0x1 << 20) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P21 (0x1 << 21) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P22 (0x1 << 22) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P23 (0x1 << 23) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P24 (0x1 << 24) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P25 (0x1 << 25) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P26 (0x1 << 26) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P27 (0x1 << 27) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P28 (0x1 << 28) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P29 (0x1 << 29) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P30 (0x1 << 30) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P31 (0x1 << 31) /**< \brief (PIO_OER) Output Enable */ -/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ -#define PIO_ODR_P0 (0x1 << 0) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P1 (0x1 << 1) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P2 (0x1 << 2) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P3 (0x1 << 3) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P4 (0x1 << 4) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P5 (0x1 << 5) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P6 (0x1 << 6) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P7 (0x1 << 7) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P8 (0x1 << 8) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P9 (0x1 << 9) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P10 (0x1 << 10) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P11 (0x1 << 11) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P12 (0x1 << 12) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P13 (0x1 << 13) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P14 (0x1 << 14) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P15 (0x1 << 15) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P16 (0x1 << 16) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P17 (0x1 << 17) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P18 (0x1 << 18) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P19 (0x1 << 19) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P20 (0x1 << 20) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P21 (0x1 << 21) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P22 (0x1 << 22) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P23 (0x1 << 23) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P24 (0x1 << 24) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P25 (0x1 << 25) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P26 (0x1 << 26) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P27 (0x1 << 27) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P28 (0x1 << 28) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P29 (0x1 << 29) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P30 (0x1 << 30) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P31 (0x1 << 31) /**< \brief (PIO_ODR) Output Disable */ -/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ -#define PIO_OSR_P0 (0x1 << 0) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P1 (0x1 << 1) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P2 (0x1 << 2) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P3 (0x1 << 3) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P4 (0x1 << 4) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P5 (0x1 << 5) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P6 (0x1 << 6) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P7 (0x1 << 7) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P8 (0x1 << 8) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P9 (0x1 << 9) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P10 (0x1 << 10) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P11 (0x1 << 11) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P12 (0x1 << 12) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P13 (0x1 << 13) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P14 (0x1 << 14) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P15 (0x1 << 15) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P16 (0x1 << 16) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P17 (0x1 << 17) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P18 (0x1 << 18) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P19 (0x1 << 19) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P20 (0x1 << 20) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P21 (0x1 << 21) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P22 (0x1 << 22) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P23 (0x1 << 23) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P24 (0x1 << 24) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P25 (0x1 << 25) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P26 (0x1 << 26) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P27 (0x1 << 27) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P28 (0x1 << 28) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P29 (0x1 << 29) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P30 (0x1 << 30) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P31 (0x1 << 31) /**< \brief (PIO_OSR) Output Status */ -/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ -#define PIO_IFER_P0 (0x1 << 0) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P1 (0x1 << 1) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P2 (0x1 << 2) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P3 (0x1 << 3) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P4 (0x1 << 4) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P5 (0x1 << 5) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P6 (0x1 << 6) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P7 (0x1 << 7) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P8 (0x1 << 8) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P9 (0x1 << 9) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P10 (0x1 << 10) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P11 (0x1 << 11) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P12 (0x1 << 12) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P13 (0x1 << 13) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P14 (0x1 << 14) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P15 (0x1 << 15) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P16 (0x1 << 16) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P17 (0x1 << 17) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P18 (0x1 << 18) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P19 (0x1 << 19) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P20 (0x1 << 20) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P21 (0x1 << 21) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P22 (0x1 << 22) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P23 (0x1 << 23) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P24 (0x1 << 24) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P25 (0x1 << 25) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P26 (0x1 << 26) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P27 (0x1 << 27) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P28 (0x1 << 28) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P29 (0x1 << 29) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P30 (0x1 << 30) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P31 (0x1 << 31) /**< \brief (PIO_IFER) Input Filter Enable */ -/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ -#define PIO_IFDR_P0 (0x1 << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P1 (0x1 << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P2 (0x1 << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P3 (0x1 << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P4 (0x1 << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P5 (0x1 << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P6 (0x1 << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P7 (0x1 << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P8 (0x1 << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P9 (0x1 << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P10 (0x1 << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P11 (0x1 << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P12 (0x1 << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P13 (0x1 << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P14 (0x1 << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P15 (0x1 << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P16 (0x1 << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P17 (0x1 << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P18 (0x1 << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P19 (0x1 << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P20 (0x1 << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P21 (0x1 << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P22 (0x1 << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P23 (0x1 << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P24 (0x1 << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P25 (0x1 << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P26 (0x1 << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P27 (0x1 << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P28 (0x1 << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P29 (0x1 << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P30 (0x1 << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P31 (0x1 << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ -/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ -#define PIO_IFSR_P0 (0x1 << 0) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P1 (0x1 << 1) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P2 (0x1 << 2) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P3 (0x1 << 3) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P4 (0x1 << 4) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P5 (0x1 << 5) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P6 (0x1 << 6) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P7 (0x1 << 7) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P8 (0x1 << 8) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P9 (0x1 << 9) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P10 (0x1 << 10) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P11 (0x1 << 11) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P12 (0x1 << 12) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P13 (0x1 << 13) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P14 (0x1 << 14) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P15 (0x1 << 15) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P16 (0x1 << 16) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P17 (0x1 << 17) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P18 (0x1 << 18) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P19 (0x1 << 19) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P20 (0x1 << 20) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P21 (0x1 << 21) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P22 (0x1 << 22) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P23 (0x1 << 23) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P24 (0x1 << 24) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P25 (0x1 << 25) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P26 (0x1 << 26) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P27 (0x1 << 27) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P28 (0x1 << 28) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P29 (0x1 << 29) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P30 (0x1 << 30) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P31 (0x1 << 31) /**< \brief (PIO_IFSR) Input Filer Status */ -/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ -#define PIO_SODR_P0 (0x1 << 0) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P1 (0x1 << 1) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P2 (0x1 << 2) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P3 (0x1 << 3) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P4 (0x1 << 4) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P5 (0x1 << 5) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P6 (0x1 << 6) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P7 (0x1 << 7) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P8 (0x1 << 8) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P9 (0x1 << 9) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P10 (0x1 << 10) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P11 (0x1 << 11) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P12 (0x1 << 12) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P13 (0x1 << 13) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P14 (0x1 << 14) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P15 (0x1 << 15) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P16 (0x1 << 16) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P17 (0x1 << 17) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P18 (0x1 << 18) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P19 (0x1 << 19) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P20 (0x1 << 20) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P21 (0x1 << 21) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P22 (0x1 << 22) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P23 (0x1 << 23) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P24 (0x1 << 24) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P25 (0x1 << 25) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P26 (0x1 << 26) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P27 (0x1 << 27) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P28 (0x1 << 28) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P29 (0x1 << 29) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P30 (0x1 << 30) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P31 (0x1 << 31) /**< \brief (PIO_SODR) Set Output Data */ -/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ -#define PIO_CODR_P0 (0x1 << 0) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P1 (0x1 << 1) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P2 (0x1 << 2) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P3 (0x1 << 3) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P4 (0x1 << 4) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P5 (0x1 << 5) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P6 (0x1 << 6) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P7 (0x1 << 7) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P8 (0x1 << 8) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P9 (0x1 << 9) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P10 (0x1 << 10) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P11 (0x1 << 11) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P12 (0x1 << 12) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P13 (0x1 << 13) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P14 (0x1 << 14) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P15 (0x1 << 15) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P16 (0x1 << 16) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P17 (0x1 << 17) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P18 (0x1 << 18) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P19 (0x1 << 19) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P20 (0x1 << 20) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P21 (0x1 << 21) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P22 (0x1 << 22) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P23 (0x1 << 23) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P24 (0x1 << 24) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P25 (0x1 << 25) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P26 (0x1 << 26) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P27 (0x1 << 27) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P28 (0x1 << 28) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P29 (0x1 << 29) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P30 (0x1 << 30) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P31 (0x1 << 31) /**< \brief (PIO_CODR) Clear Output Data */ -/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ -#define PIO_ODSR_P0 (0x1 << 0) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P1 (0x1 << 1) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P2 (0x1 << 2) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P3 (0x1 << 3) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P4 (0x1 << 4) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P5 (0x1 << 5) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P6 (0x1 << 6) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P7 (0x1 << 7) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P8 (0x1 << 8) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P9 (0x1 << 9) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P10 (0x1 << 10) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P11 (0x1 << 11) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P12 (0x1 << 12) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P13 (0x1 << 13) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P14 (0x1 << 14) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P15 (0x1 << 15) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P16 (0x1 << 16) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P17 (0x1 << 17) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P18 (0x1 << 18) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P19 (0x1 << 19) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P20 (0x1 << 20) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P21 (0x1 << 21) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P22 (0x1 << 22) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P23 (0x1 << 23) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P24 (0x1 << 24) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P25 (0x1 << 25) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P26 (0x1 << 26) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P27 (0x1 << 27) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P28 (0x1 << 28) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P29 (0x1 << 29) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P30 (0x1 << 30) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P31 (0x1 << 31) /**< \brief (PIO_ODSR) Output Data Status */ -/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ -#define PIO_PDSR_P0 (0x1 << 0) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P1 (0x1 << 1) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P2 (0x1 << 2) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P3 (0x1 << 3) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P4 (0x1 << 4) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P5 (0x1 << 5) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P6 (0x1 << 6) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P7 (0x1 << 7) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P8 (0x1 << 8) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P9 (0x1 << 9) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P10 (0x1 << 10) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P11 (0x1 << 11) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P12 (0x1 << 12) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P13 (0x1 << 13) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P14 (0x1 << 14) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P15 (0x1 << 15) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P16 (0x1 << 16) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P17 (0x1 << 17) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P18 (0x1 << 18) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P19 (0x1 << 19) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P20 (0x1 << 20) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P21 (0x1 << 21) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P22 (0x1 << 22) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P23 (0x1 << 23) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P24 (0x1 << 24) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P25 (0x1 << 25) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P26 (0x1 << 26) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P27 (0x1 << 27) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P28 (0x1 << 28) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P29 (0x1 << 29) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P30 (0x1 << 30) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P31 (0x1 << 31) /**< \brief (PIO_PDSR) Output Data Status */ -/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ -#define PIO_IER_P0 (0x1 << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P1 (0x1 << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P2 (0x1 << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P3 (0x1 << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P4 (0x1 << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P5 (0x1 << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P6 (0x1 << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P7 (0x1 << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P8 (0x1 << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P9 (0x1 << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P10 (0x1 << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P11 (0x1 << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P12 (0x1 << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P13 (0x1 << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P14 (0x1 << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P15 (0x1 << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P16 (0x1 << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P17 (0x1 << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P18 (0x1 << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P19 (0x1 << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P20 (0x1 << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P21 (0x1 << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P22 (0x1 << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P23 (0x1 << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P24 (0x1 << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P25 (0x1 << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P26 (0x1 << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P27 (0x1 << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P28 (0x1 << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P29 (0x1 << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P30 (0x1 << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P31 (0x1 << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ -#define PIO_IDR_P0 (0x1 << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P1 (0x1 << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P2 (0x1 << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P3 (0x1 << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P4 (0x1 << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P5 (0x1 << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P6 (0x1 << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P7 (0x1 << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P8 (0x1 << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P9 (0x1 << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P10 (0x1 << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P11 (0x1 << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P12 (0x1 << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P13 (0x1 << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P14 (0x1 << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P15 (0x1 << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P16 (0x1 << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P17 (0x1 << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P18 (0x1 << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P19 (0x1 << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P20 (0x1 << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P21 (0x1 << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P22 (0x1 << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P23 (0x1 << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P24 (0x1 << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P25 (0x1 << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P26 (0x1 << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P27 (0x1 << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P28 (0x1 << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P29 (0x1 << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P30 (0x1 << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P31 (0x1 << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ -#define PIO_IMR_P0 (0x1 << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P1 (0x1 << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P2 (0x1 << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P3 (0x1 << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P4 (0x1 << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P5 (0x1 << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P6 (0x1 << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P7 (0x1 << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P8 (0x1 << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P9 (0x1 << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P10 (0x1 << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P11 (0x1 << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P12 (0x1 << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P13 (0x1 << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P14 (0x1 << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P15 (0x1 << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P16 (0x1 << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P17 (0x1 << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P18 (0x1 << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P19 (0x1 << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P20 (0x1 << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P21 (0x1 << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P22 (0x1 << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P23 (0x1 << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P24 (0x1 << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P25 (0x1 << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P26 (0x1 << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P27 (0x1 << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P28 (0x1 << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P29 (0x1 << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P30 (0x1 << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P31 (0x1 << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ -#define PIO_ISR_P0 (0x1 << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P1 (0x1 << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P2 (0x1 << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P3 (0x1 << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P4 (0x1 << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P5 (0x1 << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P6 (0x1 << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P7 (0x1 << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P8 (0x1 << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P9 (0x1 << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P10 (0x1 << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P11 (0x1 << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P12 (0x1 << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P13 (0x1 << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P14 (0x1 << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P15 (0x1 << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P16 (0x1 << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P17 (0x1 << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P18 (0x1 << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P19 (0x1 << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P20 (0x1 << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P21 (0x1 << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P22 (0x1 << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P23 (0x1 << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P24 (0x1 << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P25 (0x1 << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P26 (0x1 << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P27 (0x1 << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P28 (0x1 << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P29 (0x1 << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P30 (0x1 << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P31 (0x1 << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ -#define PIO_MDER_P0 (0x1 << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P1 (0x1 << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P2 (0x1 << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P3 (0x1 << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P4 (0x1 << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P5 (0x1 << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P6 (0x1 << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P7 (0x1 << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P8 (0x1 << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P9 (0x1 << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P10 (0x1 << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P11 (0x1 << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P12 (0x1 << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P13 (0x1 << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P14 (0x1 << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P15 (0x1 << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P16 (0x1 << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P17 (0x1 << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P18 (0x1 << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P19 (0x1 << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P20 (0x1 << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P21 (0x1 << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P22 (0x1 << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P23 (0x1 << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P24 (0x1 << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P25 (0x1 << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P26 (0x1 << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P27 (0x1 << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P28 (0x1 << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P29 (0x1 << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P30 (0x1 << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P31 (0x1 << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ -/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ -#define PIO_MDDR_P0 (0x1 << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P1 (0x1 << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P2 (0x1 << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P3 (0x1 << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P4 (0x1 << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P5 (0x1 << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P6 (0x1 << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P7 (0x1 << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P8 (0x1 << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P9 (0x1 << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P10 (0x1 << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P11 (0x1 << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P12 (0x1 << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P13 (0x1 << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P14 (0x1 << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P15 (0x1 << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P16 (0x1 << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P17 (0x1 << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P18 (0x1 << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P19 (0x1 << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P20 (0x1 << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P21 (0x1 << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P22 (0x1 << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P23 (0x1 << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P24 (0x1 << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P25 (0x1 << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P26 (0x1 << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P27 (0x1 << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P28 (0x1 << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P29 (0x1 << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P30 (0x1 << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P31 (0x1 << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ -#define PIO_MDSR_P0 (0x1 << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P1 (0x1 << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P2 (0x1 << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P3 (0x1 << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P4 (0x1 << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P5 (0x1 << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P6 (0x1 << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P7 (0x1 << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P8 (0x1 << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P9 (0x1 << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P10 (0x1 << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P11 (0x1 << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P12 (0x1 << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P13 (0x1 << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P14 (0x1 << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P15 (0x1 << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P16 (0x1 << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P17 (0x1 << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P18 (0x1 << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P19 (0x1 << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P20 (0x1 << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P21 (0x1 << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P22 (0x1 << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P23 (0x1 << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P24 (0x1 << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P25 (0x1 << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P26 (0x1 << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P27 (0x1 << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P28 (0x1 << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P29 (0x1 << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P30 (0x1 << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P31 (0x1 << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ -/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ -#define PIO_PUDR_P0 (0x1 << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P1 (0x1 << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P2 (0x1 << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P3 (0x1 << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P4 (0x1 << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P5 (0x1 << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P6 (0x1 << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P7 (0x1 << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P8 (0x1 << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P9 (0x1 << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P10 (0x1 << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P11 (0x1 << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P12 (0x1 << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P13 (0x1 << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P14 (0x1 << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P15 (0x1 << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P16 (0x1 << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P17 (0x1 << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P18 (0x1 << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P19 (0x1 << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P20 (0x1 << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P21 (0x1 << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P22 (0x1 << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P23 (0x1 << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P24 (0x1 << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P25 (0x1 << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P26 (0x1 << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P27 (0x1 << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P28 (0x1 << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P29 (0x1 << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P30 (0x1 << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P31 (0x1 << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ -/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ -#define PIO_PUER_P0 (0x1 << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P1 (0x1 << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P2 (0x1 << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P3 (0x1 << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P4 (0x1 << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P5 (0x1 << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P6 (0x1 << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P7 (0x1 << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P8 (0x1 << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P9 (0x1 << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P10 (0x1 << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P11 (0x1 << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P12 (0x1 << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P13 (0x1 << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P14 (0x1 << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P15 (0x1 << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P16 (0x1 << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P17 (0x1 << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P18 (0x1 << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P19 (0x1 << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P20 (0x1 << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P21 (0x1 << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P22 (0x1 << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P23 (0x1 << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P24 (0x1 << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P25 (0x1 << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P26 (0x1 << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P27 (0x1 << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P28 (0x1 << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P29 (0x1 << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P30 (0x1 << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P31 (0x1 << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ -/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ -#define PIO_PUSR_P0 (0x1 << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P1 (0x1 << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P2 (0x1 << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P3 (0x1 << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P4 (0x1 << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P5 (0x1 << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P6 (0x1 << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P7 (0x1 << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P8 (0x1 << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P9 (0x1 << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P10 (0x1 << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P11 (0x1 << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P12 (0x1 << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P13 (0x1 << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P14 (0x1 << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P15 (0x1 << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P16 (0x1 << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P17 (0x1 << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P18 (0x1 << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P19 (0x1 << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P20 (0x1 << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P21 (0x1 << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P22 (0x1 << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P23 (0x1 << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P24 (0x1 << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P25 (0x1 << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P26 (0x1 << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P27 (0x1 << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P28 (0x1 << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P29 (0x1 << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P30 (0x1 << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P31 (0x1 << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ -/* -------- PIO_ABSR : (PIO Offset: 0x0070) Peripheral AB Select Register -------- */ -#define PIO_ABSR_P0 (0x1 << 0) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P1 (0x1 << 1) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P2 (0x1 << 2) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P3 (0x1 << 3) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P4 (0x1 << 4) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P5 (0x1 << 5) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P6 (0x1 << 6) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P7 (0x1 << 7) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P8 (0x1 << 8) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P9 (0x1 << 9) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P10 (0x1 << 10) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P11 (0x1 << 11) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P12 (0x1 << 12) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P13 (0x1 << 13) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P14 (0x1 << 14) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P15 (0x1 << 15) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P16 (0x1 << 16) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P17 (0x1 << 17) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P18 (0x1 << 18) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P19 (0x1 << 19) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P20 (0x1 << 20) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P21 (0x1 << 21) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P22 (0x1 << 22) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P23 (0x1 << 23) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P24 (0x1 << 24) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P25 (0x1 << 25) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P26 (0x1 << 26) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P27 (0x1 << 27) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P28 (0x1 << 28) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P29 (0x1 << 29) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P30 (0x1 << 30) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P31 (0x1 << 31) /**< \brief (PIO_ABSR) Peripheral A Select. */ -/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */ -#define PIO_SCIFSR_P0 (0x1 << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P1 (0x1 << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P2 (0x1 << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P3 (0x1 << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P4 (0x1 << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P5 (0x1 << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P6 (0x1 << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P7 (0x1 << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P8 (0x1 << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P9 (0x1 << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P10 (0x1 << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P11 (0x1 << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P12 (0x1 << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P13 (0x1 << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P14 (0x1 << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P15 (0x1 << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P16 (0x1 << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P17 (0x1 << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P18 (0x1 << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P19 (0x1 << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P20 (0x1 << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P21 (0x1 << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P22 (0x1 << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P23 (0x1 << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P24 (0x1 << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P25 (0x1 << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P26 (0x1 << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P27 (0x1 << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P28 (0x1 << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P29 (0x1 << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P30 (0x1 << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P31 (0x1 << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */ -#define PIO_DIFSR_P0 (0x1 << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P1 (0x1 << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P2 (0x1 << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P3 (0x1 << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P4 (0x1 << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P5 (0x1 << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P6 (0x1 << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P7 (0x1 << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P8 (0x1 << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P9 (0x1 << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P10 (0x1 << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P11 (0x1 << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P12 (0x1 << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P13 (0x1 << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P14 (0x1 << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P15 (0x1 << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P16 (0x1 << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P17 (0x1 << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P18 (0x1 << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P19 (0x1 << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P20 (0x1 << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P21 (0x1 << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P22 (0x1 << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P23 (0x1 << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P24 (0x1 << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P25 (0x1 << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P26 (0x1 << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P27 (0x1 << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P28 (0x1 << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P29 (0x1 << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P30 (0x1 << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P31 (0x1 << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */ -#define PIO_IFDGSR_P0 (0x1 << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P1 (0x1 << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P2 (0x1 << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P3 (0x1 << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P4 (0x1 << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P5 (0x1 << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P6 (0x1 << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P7 (0x1 << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P8 (0x1 << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P9 (0x1 << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P10 (0x1 << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P11 (0x1 << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P12 (0x1 << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P13 (0x1 << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P14 (0x1 << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P15 (0x1 << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P16 (0x1 << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P17 (0x1 << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P18 (0x1 << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P19 (0x1 << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P20 (0x1 << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P21 (0x1 << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P22 (0x1 << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P23 (0x1 << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P24 (0x1 << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P25 (0x1 << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P26 (0x1 << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P27 (0x1 << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P28 (0x1 << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P29 (0x1 << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P30 (0x1 << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P31 (0x1 << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ -#define PIO_SCDR_DIV0 (0x1 << 0) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV1 (0x1 << 1) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV2 (0x1 << 2) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV3 (0x1 << 3) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV4 (0x1 << 4) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV5 (0x1 << 5) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV6 (0x1 << 6) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV7 (0x1 << 7) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV8 (0x1 << 8) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV9 (0x1 << 9) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV10 (0x1 << 10) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV11 (0x1 << 11) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV12 (0x1 << 12) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV13 (0x1 << 13) /**< \brief (PIO_SCDR) */ -/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ -#define PIO_OWER_P0 (0x1 << 0) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P1 (0x1 << 1) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P2 (0x1 << 2) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P3 (0x1 << 3) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P4 (0x1 << 4) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P5 (0x1 << 5) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P6 (0x1 << 6) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P7 (0x1 << 7) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P8 (0x1 << 8) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P9 (0x1 << 9) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P10 (0x1 << 10) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P11 (0x1 << 11) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P12 (0x1 << 12) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P13 (0x1 << 13) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P14 (0x1 << 14) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P15 (0x1 << 15) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P16 (0x1 << 16) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P17 (0x1 << 17) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P18 (0x1 << 18) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P19 (0x1 << 19) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P20 (0x1 << 20) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P21 (0x1 << 21) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P22 (0x1 << 22) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P23 (0x1 << 23) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P24 (0x1 << 24) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P25 (0x1 << 25) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P26 (0x1 << 26) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P27 (0x1 << 27) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P28 (0x1 << 28) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P29 (0x1 << 29) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P30 (0x1 << 30) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P31 (0x1 << 31) /**< \brief (PIO_OWER) Output Write Enable. */ -/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ -#define PIO_OWDR_P0 (0x1 << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P1 (0x1 << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P2 (0x1 << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P3 (0x1 << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P4 (0x1 << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P5 (0x1 << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P6 (0x1 << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P7 (0x1 << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P8 (0x1 << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P9 (0x1 << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P10 (0x1 << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P11 (0x1 << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P12 (0x1 << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P13 (0x1 << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P14 (0x1 << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P15 (0x1 << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P16 (0x1 << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P17 (0x1 << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P18 (0x1 << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P19 (0x1 << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P20 (0x1 << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P21 (0x1 << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P22 (0x1 << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P23 (0x1 << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P24 (0x1 << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P25 (0x1 << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P26 (0x1 << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P27 (0x1 << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P28 (0x1 << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P29 (0x1 << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P30 (0x1 << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P31 (0x1 << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ -/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ -#define PIO_OWSR_P0 (0x1 << 0) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P1 (0x1 << 1) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P2 (0x1 << 2) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P3 (0x1 << 3) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P4 (0x1 << 4) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P5 (0x1 << 5) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P6 (0x1 << 6) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P7 (0x1 << 7) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P8 (0x1 << 8) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P9 (0x1 << 9) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P10 (0x1 << 10) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P11 (0x1 << 11) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P12 (0x1 << 12) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P13 (0x1 << 13) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P14 (0x1 << 14) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P15 (0x1 << 15) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P16 (0x1 << 16) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P17 (0x1 << 17) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P18 (0x1 << 18) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P19 (0x1 << 19) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P20 (0x1 << 20) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P21 (0x1 << 21) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P22 (0x1 << 22) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P23 (0x1 << 23) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P24 (0x1 << 24) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P25 (0x1 << 25) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P26 (0x1 << 26) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P27 (0x1 << 27) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P28 (0x1 << 28) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P29 (0x1 << 29) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P30 (0x1 << 30) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P31 (0x1 << 31) /**< \brief (PIO_OWSR) Output Write Status. */ -/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ -#define PIO_AIMER_P0 (0x1 << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P1 (0x1 << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P2 (0x1 << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P3 (0x1 << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P4 (0x1 << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P5 (0x1 << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P6 (0x1 << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P7 (0x1 << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P8 (0x1 << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P9 (0x1 << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P10 (0x1 << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P11 (0x1 << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P12 (0x1 << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P13 (0x1 << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P14 (0x1 << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P15 (0x1 << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P16 (0x1 << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P17 (0x1 << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P18 (0x1 << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P19 (0x1 << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P20 (0x1 << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P21 (0x1 << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P22 (0x1 << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P23 (0x1 << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P24 (0x1 << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P25 (0x1 << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P26 (0x1 << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P27 (0x1 << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P28 (0x1 << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P29 (0x1 << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P30 (0x1 << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P31 (0x1 << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ -#define PIO_AIMDR_P0 (0x1 << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P1 (0x1 << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P2 (0x1 << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P3 (0x1 << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P4 (0x1 << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P5 (0x1 << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P6 (0x1 << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P7 (0x1 << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P8 (0x1 << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P9 (0x1 << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P10 (0x1 << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P11 (0x1 << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P12 (0x1 << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P13 (0x1 << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P14 (0x1 << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P15 (0x1 << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P16 (0x1 << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P17 (0x1 << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P18 (0x1 << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P19 (0x1 << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P20 (0x1 << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P21 (0x1 << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P22 (0x1 << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P23 (0x1 << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P24 (0x1 << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P25 (0x1 << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P26 (0x1 << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P27 (0x1 << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P28 (0x1 << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P29 (0x1 << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P30 (0x1 << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P31 (0x1 << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ -#define PIO_AIMMR_P0 (0x1 << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P1 (0x1 << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P2 (0x1 << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P3 (0x1 << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P4 (0x1 << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P5 (0x1 << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P6 (0x1 << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P7 (0x1 << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P8 (0x1 << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P9 (0x1 << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P10 (0x1 << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P11 (0x1 << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P12 (0x1 << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P13 (0x1 << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P14 (0x1 << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P15 (0x1 << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P16 (0x1 << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P17 (0x1 << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P18 (0x1 << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P19 (0x1 << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P20 (0x1 << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P21 (0x1 << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P22 (0x1 << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P23 (0x1 << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P24 (0x1 << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P25 (0x1 << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P26 (0x1 << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P27 (0x1 << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P28 (0x1 << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P29 (0x1 << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P30 (0x1 << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P31 (0x1 << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ -#define PIO_ESR_P0 (0x1 << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P1 (0x1 << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P2 (0x1 << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P3 (0x1 << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P4 (0x1 << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P5 (0x1 << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P6 (0x1 << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P7 (0x1 << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P8 (0x1 << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P9 (0x1 << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P10 (0x1 << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P11 (0x1 << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P12 (0x1 << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P13 (0x1 << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P14 (0x1 << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P15 (0x1 << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P16 (0x1 << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P17 (0x1 << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P18 (0x1 << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P19 (0x1 << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P20 (0x1 << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P21 (0x1 << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P22 (0x1 << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P23 (0x1 << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P24 (0x1 << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P25 (0x1 << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P26 (0x1 << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P27 (0x1 << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P28 (0x1 << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P29 (0x1 << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P30 (0x1 << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P31 (0x1 << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ -#define PIO_LSR_P0 (0x1 << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P1 (0x1 << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P2 (0x1 << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P3 (0x1 << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P4 (0x1 << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P5 (0x1 << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P6 (0x1 << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P7 (0x1 << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P8 (0x1 << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P9 (0x1 << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P10 (0x1 << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P11 (0x1 << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P12 (0x1 << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P13 (0x1 << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P14 (0x1 << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P15 (0x1 << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P16 (0x1 << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P17 (0x1 << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P18 (0x1 << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P19 (0x1 << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P20 (0x1 << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P21 (0x1 << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P22 (0x1 << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P23 (0x1 << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P24 (0x1 << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P25 (0x1 << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P26 (0x1 << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P27 (0x1 << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P28 (0x1 << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P29 (0x1 << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P30 (0x1 << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P31 (0x1 << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ -#define PIO_ELSR_P0 (0x1 << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P1 (0x1 << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P2 (0x1 << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P3 (0x1 << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P4 (0x1 << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P5 (0x1 << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P6 (0x1 << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P7 (0x1 << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P8 (0x1 << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P9 (0x1 << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P10 (0x1 << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P11 (0x1 << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P12 (0x1 << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P13 (0x1 << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P14 (0x1 << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P15 (0x1 << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P16 (0x1 << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P17 (0x1 << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P18 (0x1 << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P19 (0x1 << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P20 (0x1 << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P21 (0x1 << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P22 (0x1 << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P23 (0x1 << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P24 (0x1 << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P25 (0x1 << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P26 (0x1 << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P27 (0x1 << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P28 (0x1 << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P29 (0x1 << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P30 (0x1 << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P31 (0x1 << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ -#define PIO_FELLSR_P0 (0x1 << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P1 (0x1 << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P2 (0x1 << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P3 (0x1 << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P4 (0x1 << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P5 (0x1 << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P6 (0x1 << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P7 (0x1 << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P8 (0x1 << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P9 (0x1 << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P10 (0x1 << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P11 (0x1 << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P12 (0x1 << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P13 (0x1 << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P14 (0x1 << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P15 (0x1 << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P16 (0x1 << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P17 (0x1 << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P18 (0x1 << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P19 (0x1 << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P20 (0x1 << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P21 (0x1 << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P22 (0x1 << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P23 (0x1 << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P24 (0x1 << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P25 (0x1 << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P26 (0x1 << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P27 (0x1 << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P28 (0x1 << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P29 (0x1 << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P30 (0x1 << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P31 (0x1 << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ -#define PIO_REHLSR_P0 (0x1 << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P1 (0x1 << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P2 (0x1 << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P3 (0x1 << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P4 (0x1 << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P5 (0x1 << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P6 (0x1 << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P7 (0x1 << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P8 (0x1 << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P9 (0x1 << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P10 (0x1 << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P11 (0x1 << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P12 (0x1 << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P13 (0x1 << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P14 (0x1 << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P15 (0x1 << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P16 (0x1 << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P17 (0x1 << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P18 (0x1 << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P19 (0x1 << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P20 (0x1 << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P21 (0x1 << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P22 (0x1 << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P23 (0x1 << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P24 (0x1 << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P25 (0x1 << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P26 (0x1 << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P27 (0x1 << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P28 (0x1 << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P29 (0x1 << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P30 (0x1 << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P31 (0x1 << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ -#define PIO_FRLHSR_P0 (0x1 << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P1 (0x1 << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P2 (0x1 << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P3 (0x1 << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P4 (0x1 << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P5 (0x1 << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P6 (0x1 << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P7 (0x1 << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P8 (0x1 << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P9 (0x1 << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P10 (0x1 << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P11 (0x1 << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P12 (0x1 << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P13 (0x1 << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P14 (0x1 << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P15 (0x1 << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P16 (0x1 << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P17 (0x1 << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P18 (0x1 << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P19 (0x1 << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P20 (0x1 << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P21 (0x1 << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P22 (0x1 << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P23 (0x1 << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P24 (0x1 << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P25 (0x1 << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P26 (0x1 << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P27 (0x1 << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P28 (0x1 << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P29 (0x1 << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P30 (0x1 << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P31 (0x1 << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ -#define PIO_LOCKSR_P0 (0x1 << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P1 (0x1 << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P2 (0x1 << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P3 (0x1 << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P4 (0x1 << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P5 (0x1 << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P6 (0x1 << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P7 (0x1 << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P8 (0x1 << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P9 (0x1 << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P10 (0x1 << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P11 (0x1 << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P12 (0x1 << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P13 (0x1 << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P14 (0x1 << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P15 (0x1 << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P16 (0x1 << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P17 (0x1 << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P18 (0x1 << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P19 (0x1 << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P20 (0x1 << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P21 (0x1 << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P22 (0x1 << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P23 (0x1 << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P24 (0x1 << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P25 (0x1 << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P26 (0x1 << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P27 (0x1 << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P28 (0x1 << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P29 (0x1 << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P30 (0x1 << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P31 (0x1 << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ -/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PIO_WPMR_WPEN (0x1 << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ -#define PIO_WPMR_WPKEY (0xffffff << 8) /**< \brief (PIO_WPMR) Write Protect KEY */ -/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ -#define PIO_WPSR_WPVS (0x1 << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ -#define PIO_WPSR_WPVSRC (0xffff << 8) /**< \brief (PIO_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Power Management Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_PMC Power Management Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pmc hardware registers */ -typedef struct { - WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ - WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ - RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ - RwReg Reserved1[1]; - WoReg PMC_PCER; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register */ - WoReg PMC_PCDR; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register */ - RoReg PMC_PCSR; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register */ - RwReg CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */ - RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ - RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ - RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ - RwReg Reserved2[1]; - RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ - RwReg Reserved3[3]; - RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ - RwReg Reserved4[5]; - WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ - WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ - RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ - RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ - RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ - RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ - WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ -} Pmc; -#endif /* __ASSEMBLY__ */ -/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ -#define PMC_SCER_PCK0 (0x1 << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ -#define PMC_SCER_PCK1 (0x1 << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ -#define PMC_SCER_PCK2 (0x1 << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ -/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ -#define PMC_SCDR_PCK0 (0x1 << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ -#define PMC_SCDR_PCK1 (0x1 << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ -#define PMC_SCDR_PCK2 (0x1 << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ -/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ -#define PMC_SCSR_PCK0 (0x1 << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ -#define PMC_SCSR_PCK1 (0x1 << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ -#define PMC_SCSR_PCK2 (0x1 << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ -/* -------- PMC_PCER : (PMC Offset: 0x0010) Peripheral Clock Enable Register -------- */ -#define PMC_PCER_PID2 (0x1 << 2) /**< \brief (PMC_PCER) Peripheral Clock 2 Enable */ -#define PMC_PCER_PID3 (0x1 << 3) /**< \brief (PMC_PCER) Peripheral Clock 3 Enable */ -#define PMC_PCER_PID4 (0x1 << 4) /**< \brief (PMC_PCER) Peripheral Clock 4 Enable */ -#define PMC_PCER_PID5 (0x1 << 5) /**< \brief (PMC_PCER) Peripheral Clock 5 Enable */ -#define PMC_PCER_PID6 (0x1 << 6) /**< \brief (PMC_PCER) Peripheral Clock 6 Enable */ -#define PMC_PCER_PID7 (0x1 << 7) /**< \brief (PMC_PCER) Peripheral Clock 7 Enable */ -#define PMC_PCER_PID8 (0x1 << 8) /**< \brief (PMC_PCER) Peripheral Clock 8 Enable */ -#define PMC_PCER_PID9 (0x1 << 9) /**< \brief (PMC_PCER) Peripheral Clock 9 Enable */ -#define PMC_PCER_PID10 (0x1 << 10) /**< \brief (PMC_PCER) Peripheral Clock 10 Enable */ -#define PMC_PCER_PID11 (0x1 << 11) /**< \brief (PMC_PCER) Peripheral Clock 11 Enable */ -#define PMC_PCER_PID12 (0x1 << 12) /**< \brief (PMC_PCER) Peripheral Clock 12 Enable */ -#define PMC_PCER_PID13 (0x1 << 13) /**< \brief (PMC_PCER) Peripheral Clock 13 Enable */ -#define PMC_PCER_PID14 (0x1 << 14) /**< \brief (PMC_PCER) Peripheral Clock 14 Enable */ -#define PMC_PCER_PID15 (0x1 << 15) /**< \brief (PMC_PCER) Peripheral Clock 15 Enable */ -#define PMC_PCER_PID16 (0x1 << 16) /**< \brief (PMC_PCER) Peripheral Clock 16 Enable */ -#define PMC_PCER_PID17 (0x1 << 17) /**< \brief (PMC_PCER) Peripheral Clock 17 Enable */ -#define PMC_PCER_PID18 (0x1 << 18) /**< \brief (PMC_PCER) Peripheral Clock 18 Enable */ -#define PMC_PCER_PID19 (0x1 << 19) /**< \brief (PMC_PCER) Peripheral Clock 19 Enable */ -#define PMC_PCER_PID20 (0x1 << 20) /**< \brief (PMC_PCER) Peripheral Clock 20 Enable */ -#define PMC_PCER_PID21 (0x1 << 21) /**< \brief (PMC_PCER) Peripheral Clock 21 Enable */ -#define PMC_PCER_PID22 (0x1 << 22) /**< \brief (PMC_PCER) Peripheral Clock 22 Enable */ -#define PMC_PCER_PID23 (0x1 << 23) /**< \brief (PMC_PCER) Peripheral Clock 23 Enable */ -#define PMC_PCER_PID24 (0x1 << 24) /**< \brief (PMC_PCER) Peripheral Clock 24 Enable */ -#define PMC_PCER_PID25 (0x1 << 25) /**< \brief (PMC_PCER) Peripheral Clock 25 Enable */ -#define PMC_PCER_PID26 (0x1 << 26) /**< \brief (PMC_PCER) Peripheral Clock 26 Enable */ -#define PMC_PCER_PID27 (0x1 << 27) /**< \brief (PMC_PCER) Peripheral Clock 27 Enable */ -#define PMC_PCER_PID28 (0x1 << 28) /**< \brief (PMC_PCER) Peripheral Clock 28 Enable */ -#define PMC_PCER_PID29 (0x1 << 29) /**< \brief (PMC_PCER) Peripheral Clock 29 Enable */ -#define PMC_PCER_PID30 (0x1 << 30) /**< \brief (PMC_PCER) Peripheral Clock 30 Enable */ -#define PMC_PCER_PID31 (0x1 << 31) /**< \brief (PMC_PCER) Peripheral Clock 31 Enable */ -/* -------- PMC_PCDR : (PMC Offset: 0x0014) Peripheral Clock Disable Register -------- */ -#define PMC_PCDR_PID2 (0x1 << 2) /**< \brief (PMC_PCDR) Peripheral Clock 2 Disable */ -#define PMC_PCDR_PID3 (0x1 << 3) /**< \brief (PMC_PCDR) Peripheral Clock 3 Disable */ -#define PMC_PCDR_PID4 (0x1 << 4) /**< \brief (PMC_PCDR) Peripheral Clock 4 Disable */ -#define PMC_PCDR_PID5 (0x1 << 5) /**< \brief (PMC_PCDR) Peripheral Clock 5 Disable */ -#define PMC_PCDR_PID6 (0x1 << 6) /**< \brief (PMC_PCDR) Peripheral Clock 6 Disable */ -#define PMC_PCDR_PID7 (0x1 << 7) /**< \brief (PMC_PCDR) Peripheral Clock 7 Disable */ -#define PMC_PCDR_PID8 (0x1 << 8) /**< \brief (PMC_PCDR) Peripheral Clock 8 Disable */ -#define PMC_PCDR_PID9 (0x1 << 9) /**< \brief (PMC_PCDR) Peripheral Clock 9 Disable */ -#define PMC_PCDR_PID10 (0x1 << 10) /**< \brief (PMC_PCDR) Peripheral Clock 10 Disable */ -#define PMC_PCDR_PID11 (0x1 << 11) /**< \brief (PMC_PCDR) Peripheral Clock 11 Disable */ -#define PMC_PCDR_PID12 (0x1 << 12) /**< \brief (PMC_PCDR) Peripheral Clock 12 Disable */ -#define PMC_PCDR_PID13 (0x1 << 13) /**< \brief (PMC_PCDR) Peripheral Clock 13 Disable */ -#define PMC_PCDR_PID14 (0x1 << 14) /**< \brief (PMC_PCDR) Peripheral Clock 14 Disable */ -#define PMC_PCDR_PID15 (0x1 << 15) /**< \brief (PMC_PCDR) Peripheral Clock 15 Disable */ -#define PMC_PCDR_PID16 (0x1 << 16) /**< \brief (PMC_PCDR) Peripheral Clock 16 Disable */ -#define PMC_PCDR_PID17 (0x1 << 17) /**< \brief (PMC_PCDR) Peripheral Clock 17 Disable */ -#define PMC_PCDR_PID18 (0x1 << 18) /**< \brief (PMC_PCDR) Peripheral Clock 18 Disable */ -#define PMC_PCDR_PID19 (0x1 << 19) /**< \brief (PMC_PCDR) Peripheral Clock 19 Disable */ -#define PMC_PCDR_PID20 (0x1 << 20) /**< \brief (PMC_PCDR) Peripheral Clock 20 Disable */ -#define PMC_PCDR_PID21 (0x1 << 21) /**< \brief (PMC_PCDR) Peripheral Clock 21 Disable */ -#define PMC_PCDR_PID22 (0x1 << 22) /**< \brief (PMC_PCDR) Peripheral Clock 22 Disable */ -#define PMC_PCDR_PID23 (0x1 << 23) /**< \brief (PMC_PCDR) Peripheral Clock 23 Disable */ -#define PMC_PCDR_PID24 (0x1 << 24) /**< \brief (PMC_PCDR) Peripheral Clock 24 Disable */ -#define PMC_PCDR_PID25 (0x1 << 25) /**< \brief (PMC_PCDR) Peripheral Clock 25 Disable */ -#define PMC_PCDR_PID26 (0x1 << 26) /**< \brief (PMC_PCDR) Peripheral Clock 26 Disable */ -#define PMC_PCDR_PID27 (0x1 << 27) /**< \brief (PMC_PCDR) Peripheral Clock 27 Disable */ -#define PMC_PCDR_PID28 (0x1 << 28) /**< \brief (PMC_PCDR) Peripheral Clock 28 Disable */ -#define PMC_PCDR_PID29 (0x1 << 29) /**< \brief (PMC_PCDR) Peripheral Clock 29 Disable */ -#define PMC_PCDR_PID30 (0x1 << 30) /**< \brief (PMC_PCDR) Peripheral Clock 30 Disable */ -#define PMC_PCDR_PID31 (0x1 << 31) /**< \brief (PMC_PCDR) Peripheral Clock 31 Disable */ -/* -------- PMC_PCSR : (PMC Offset: 0x0018) Peripheral Clock Status Register -------- */ -#define PMC_PCSR_PID2 (0x1 << 2) /**< \brief (PMC_PCSR) Peripheral Clock 2 Status */ -#define PMC_PCSR_PID3 (0x1 << 3) /**< \brief (PMC_PCSR) Peripheral Clock 3 Status */ -#define PMC_PCSR_PID4 (0x1 << 4) /**< \brief (PMC_PCSR) Peripheral Clock 4 Status */ -#define PMC_PCSR_PID5 (0x1 << 5) /**< \brief (PMC_PCSR) Peripheral Clock 5 Status */ -#define PMC_PCSR_PID6 (0x1 << 6) /**< \brief (PMC_PCSR) Peripheral Clock 6 Status */ -#define PMC_PCSR_PID7 (0x1 << 7) /**< \brief (PMC_PCSR) Peripheral Clock 7 Status */ -#define PMC_PCSR_PID8 (0x1 << 8) /**< \brief (PMC_PCSR) Peripheral Clock 8 Status */ -#define PMC_PCSR_PID9 (0x1 << 9) /**< \brief (PMC_PCSR) Peripheral Clock 9 Status */ -#define PMC_PCSR_PID10 (0x1 << 10) /**< \brief (PMC_PCSR) Peripheral Clock 10 Status */ -#define PMC_PCSR_PID11 (0x1 << 11) /**< \brief (PMC_PCSR) Peripheral Clock 11 Status */ -#define PMC_PCSR_PID12 (0x1 << 12) /**< \brief (PMC_PCSR) Peripheral Clock 12 Status */ -#define PMC_PCSR_PID13 (0x1 << 13) /**< \brief (PMC_PCSR) Peripheral Clock 13 Status */ -#define PMC_PCSR_PID14 (0x1 << 14) /**< \brief (PMC_PCSR) Peripheral Clock 14 Status */ -#define PMC_PCSR_PID15 (0x1 << 15) /**< \brief (PMC_PCSR) Peripheral Clock 15 Status */ -#define PMC_PCSR_PID16 (0x1 << 16) /**< \brief (PMC_PCSR) Peripheral Clock 16 Status */ -#define PMC_PCSR_PID17 (0x1 << 17) /**< \brief (PMC_PCSR) Peripheral Clock 17 Status */ -#define PMC_PCSR_PID18 (0x1 << 18) /**< \brief (PMC_PCSR) Peripheral Clock 18 Status */ -#define PMC_PCSR_PID19 (0x1 << 19) /**< \brief (PMC_PCSR) Peripheral Clock 19 Status */ -#define PMC_PCSR_PID20 (0x1 << 20) /**< \brief (PMC_PCSR) Peripheral Clock 20 Status */ -#define PMC_PCSR_PID21 (0x1 << 21) /**< \brief (PMC_PCSR) Peripheral Clock 21 Status */ -#define PMC_PCSR_PID22 (0x1 << 22) /**< \brief (PMC_PCSR) Peripheral Clock 22 Status */ -#define PMC_PCSR_PID23 (0x1 << 23) /**< \brief (PMC_PCSR) Peripheral Clock 23 Status */ -#define PMC_PCSR_PID24 (0x1 << 24) /**< \brief (PMC_PCSR) Peripheral Clock 24 Status */ -#define PMC_PCSR_PID25 (0x1 << 25) /**< \brief (PMC_PCSR) Peripheral Clock 25 Status */ -#define PMC_PCSR_PID26 (0x1 << 26) /**< \brief (PMC_PCSR) Peripheral Clock 26 Status */ -#define PMC_PCSR_PID27 (0x1 << 27) /**< \brief (PMC_PCSR) Peripheral Clock 27 Status */ -#define PMC_PCSR_PID28 (0x1 << 28) /**< \brief (PMC_PCSR) Peripheral Clock 28 Status */ -#define PMC_PCSR_PID29 (0x1 << 29) /**< \brief (PMC_PCSR) Peripheral Clock 29 Status */ -#define PMC_PCSR_PID30 (0x1 << 30) /**< \brief (PMC_PCSR) Peripheral Clock 30 Status */ -#define PMC_PCSR_PID31 (0x1 << 31) /**< \brief (PMC_PCSR) Peripheral Clock 31 Status */ -/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */ -#define CKGR_UCKR_UPLLEN (0x1 << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */ -#define CKGR_UCKR_UPLLCOUNT (0xf << 20) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */ -/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ -#define CKGR_MOR_MOSCXTEN (0x1 << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ -#define CKGR_MOR_MOSCXTBY (0x1 << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ -#define CKGR_MOR_WAITMODE (0x1 << 2) /**< \brief (CKGR_MOR) Wait Mode Command */ -#define CKGR_MOR_MOSCRCEN (0x1 << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ -#define CKGR_MOR_MOSCRCF (0x7 << 4) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ -#define CKGR_MOR_MOSCXTST (0xff << 8) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ -#define CKGR_MOR_KEY (0xff << 16) /**< \brief (CKGR_MOR) Password */ -#define CKGR_MOR_MOSCSEL (0x1 << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ -#define CKGR_MOR_CFDEN (0x1 << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ -/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ -#define CKGR_MCFR_MAINF (0xffff << 0) /**< \brief (CKGR_MCFR) Main Clock Frequency */ -#define CKGR_MCFR_MAINFRDY (0x1 << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ -/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ -#define CKGR_PLLAR_DIVA (0xff << 0) /**< \brief (CKGR_PLLAR) Divider */ -#define CKGR_PLLAR_PLLACOUNT (0x3f << 8) /**< \brief (CKGR_PLLAR) PLLA Counter */ -#define CKGR_PLLAR_STMODE (0x3 << 14) /**< \brief (CKGR_PLLAR) Start Mode */ -#define CKGR_PLLAR_MULA (0x7ff << 16) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ -#define CKGR_PLLAR_STUCKTO1 (0x1 << 29) /**< \brief (CKGR_PLLAR) */ -/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ -#define PMC_MCKR_CSS (0x3 << 0) /**< \brief (PMC_MCKR) Master Clock Source Selection */ -#define PMC_MCKR_CSS_SLOW_CLK (0x0 << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ -#define PMC_MCKR_CSS_MAIN_CLK (0x1 << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ -#define PMC_MCKR_CSS_PLLA_CLK (0x2 << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ -#define PMC_MCKR_CSS_PLLB_CLK (0x3 << 0) /**< \brief (PMC_MCKR) UPLL Clock is selected */ -#define PMC_MCKR_PRES (0x7 << 4) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ -#define PMC_MCKR_PRES_CLK (0x0 << 4) /**< \brief (PMC_MCKR) Selected clock */ -#define PMC_MCKR_PRES_CLK_2 (0x1 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ -#define PMC_MCKR_PRES_CLK_4 (0x2 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ -#define PMC_MCKR_PRES_CLK_8 (0x3 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ -#define PMC_MCKR_PRES_CLK_16 (0x4 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ -#define PMC_MCKR_PRES_CLK_32 (0x5 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ -#define PMC_MCKR_PRES_CLK_64 (0x6 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ -/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ -#define PMC_PCK_CSS (0x7 << 0) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ -#define PMC_PCK_PRES (0x7 << 4) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ -/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ -#define PMC_IER_MOSCXTS (0x1 << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ -#define PMC_IER_LOCKA (0x1 << 1) /**< \brief (PMC_IER) PLL A Lock Interrupt Enable */ -#define PMC_IER_MCKRDY (0x1 << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ -#define PMC_IER_LOCKU (0x1 << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */ -#define PMC_IER_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ -#define PMC_IER_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ -#define PMC_IER_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ -#define PMC_IER_MOSCSELS (0x1 << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ -#define PMC_IER_MOSCRCS (0x1 << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ -#define PMC_IER_CFDEV (0x1 << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ -/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ -#define PMC_IDR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ -#define PMC_IDR_LOCKA (0x1 << 1) /**< \brief (PMC_IDR) PLL A Lock Interrupt Disable */ -#define PMC_IDR_MCKRDY (0x1 << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ -#define PMC_IDR_LOCKU (0x1 << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */ -#define PMC_IDR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ -#define PMC_IDR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ -#define PMC_IDR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ -#define PMC_IDR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ -#define PMC_IDR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ -#define PMC_IDR_CFDEV (0x1 << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ -/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ -#define PMC_SR_MOSCXTS (0x1 << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ -#define PMC_SR_LOCKA (0x1 << 1) /**< \brief (PMC_SR) PLL A Lock Status */ -#define PMC_SR_MCKRDY (0x1 << 3) /**< \brief (PMC_SR) Master Clock Status */ -#define PMC_SR_LOCKU (0x1 << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */ -#define PMC_SR_OSCSELS (0x1 << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ -#define PMC_SR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_MOSCSELS (0x1 << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ -#define PMC_SR_MOSCRCS (0x1 << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ -#define PMC_SR_CFDEV (0x1 << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ -#define PMC_SR_CFDS (0x1 << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ -#define PMC_SR_FOS (0x1 << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ -/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ -#define PMC_IMR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ -#define PMC_IMR_LOCKA (0x1 << 1) /**< \brief (PMC_IMR) PLL A Lock Interrupt Mask */ -#define PMC_IMR_MCKRDY (0x1 << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ -#define PMC_IMR_LOCKU (0x1 << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */ -#define PMC_IMR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ -#define PMC_IMR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ -#define PMC_IMR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ -#define PMC_IMR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ -#define PMC_IMR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ -#define PMC_IMR_CFDEV (0x1 << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ -/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ -#define PMC_FSMR_FSTT0 (0x1 << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ -#define PMC_FSMR_FSTT1 (0x1 << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ -#define PMC_FSMR_FSTT2 (0x1 << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ -#define PMC_FSMR_FSTT3 (0x1 << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ -#define PMC_FSMR_FSTT4 (0x1 << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ -#define PMC_FSMR_FSTT5 (0x1 << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ -#define PMC_FSMR_FSTT6 (0x1 << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ -#define PMC_FSMR_FSTT7 (0x1 << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ -#define PMC_FSMR_FSTT8 (0x1 << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ -#define PMC_FSMR_FSTT9 (0x1 << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ -#define PMC_FSMR_FSTT10 (0x1 << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ -#define PMC_FSMR_FSTT11 (0x1 << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ -#define PMC_FSMR_FSTT12 (0x1 << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ -#define PMC_FSMR_FSTT13 (0x1 << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ -#define PMC_FSMR_FSTT14 (0x1 << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ -#define PMC_FSMR_FSTT15 (0x1 << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ -#define PMC_FSMR_RTTAL (0x1 << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ -#define PMC_FSMR_RTCAL (0x1 << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ -#define PMC_FSMR_USBAL (0x1 << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ -#define PMC_FSMR_LPM (0x1 << 20) /**< \brief (PMC_FSMR) Low Power Mode */ -/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ -#define PMC_FSPR_FSTP0 (0x1 << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 0 */ -#define PMC_FSPR_FSTP1 (0x1 << 1) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP2 (0x1 << 2) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP3 (0x1 << 3) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP4 (0x1 << 4) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP5 (0x1 << 5) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP6 (0x1 << 6) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP7 (0x1 << 7) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP8 (0x1 << 8) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP9 (0x1 << 9) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP10 (0x1 << 10) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP11 (0x1 << 11) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP12 (0x1 << 12) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP13 (0x1 << 13) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP14 (0x1 << 14) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP15 (0x1 << 15) /**< \brief (PMC_FSPR) */ -/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ -#define PMC_FOCR_FOCLR (0x1 << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_PWM Pulse Width Modulation Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief PwmCh_num hardware registers */ -typedef struct { - RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ - RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ - RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ - RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ - RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ - RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ - RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ - RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ -} PwmCh_num; -/** \brief Pwm hardware registers */ -typedef struct { - RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ - WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ - WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ - RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ - WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ - WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ - RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ - RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ - RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ - RwReg Reserved1[1]; - RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ - RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ - WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ - WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ - WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ - RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ - RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ - RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ - RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ - WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ - WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ - WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ - WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ - RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ - RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ - WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ - RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */ - RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ - RwReg Reserved2[3]; - RwReg PWM_ELxMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ - RwReg Reserved3[24]; - WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ - RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ - RwReg Reserved4[5]; - RwReg PWM_RPR; /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */ - RwReg PWM_RCR; /**< \brief (Pwm Offset: 0x104) Receive Counter Register */ - RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */ - RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */ - RwReg PWM_RNPR; /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */ - RwReg PWM_RNCR; /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */ - RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */ - RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */ - WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */ - RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */ - RwReg Reserved5[2]; - RwReg PWM_CMP0V; /**< \brief (Pwm Offset: 0x130) PWM Comparison 0 Value Register */ - WoReg PWM_CMP0VUPD; /**< \brief (Pwm Offset: 0x134) PWM Comparison 0 Value Update Register */ - RwReg PWM_CMP0M; /**< \brief (Pwm Offset: 0x138) PWM Comparison 0 Mode Register */ - WoReg PWM_CMP0MUPD; /**< \brief (Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register */ - RwReg PWM_CMP1V; /**< \brief (Pwm Offset: 0x140) PWM Comparison 1 Value Register */ - WoReg PWM_CMP1VUPD; /**< \brief (Pwm Offset: 0x144) PWM Comparison 1 Value Update Register */ - RwReg PWM_CMP1M; /**< \brief (Pwm Offset: 0x148) PWM Comparison 1 Mode Register */ - WoReg PWM_CMP1MUPD; /**< \brief (Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register */ - RwReg PWM_CMP2V; /**< \brief (Pwm Offset: 0x150) PWM Comparison 2 Value Register */ - WoReg PWM_CMP2VUPD; /**< \brief (Pwm Offset: 0x154) PWM Comparison 2 Value Update Register */ - RwReg PWM_CMP2M; /**< \brief (Pwm Offset: 0x158) PWM Comparison 2 Mode Register */ - WoReg PWM_CMP2MUPD; /**< \brief (Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register */ - RwReg PWM_CMP3V; /**< \brief (Pwm Offset: 0x160) PWM Comparison 3 Value Register */ - WoReg PWM_CMP3VUPD; /**< \brief (Pwm Offset: 0x164) PWM Comparison 3 Value Update Register */ - RwReg PWM_CMP3M; /**< \brief (Pwm Offset: 0x168) PWM Comparison 3 Mode Register */ - WoReg PWM_CMP3MUPD; /**< \brief (Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register */ - RwReg PWM_CMP4V; /**< \brief (Pwm Offset: 0x170) PWM Comparison 4 Value Register */ - WoReg PWM_CMP4VUPD; /**< \brief (Pwm Offset: 0x174) PWM Comparison 4 Value Update Register */ - RwReg PWM_CMP4M; /**< \brief (Pwm Offset: 0x178) PWM Comparison 4 Mode Register */ - WoReg PWM_CMP4MUPD; /**< \brief (Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register */ - RwReg PWM_CMP5V; /**< \brief (Pwm Offset: 0x180) PWM Comparison 5 Value Register */ - WoReg PWM_CMP5VUPD; /**< \brief (Pwm Offset: 0x184) PWM Comparison 5 Value Update Register */ - RwReg PWM_CMP5M; /**< \brief (Pwm Offset: 0x188) PWM Comparison 5 Mode Register */ - WoReg PWM_CMP5MUPD; /**< \brief (Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register */ - RwReg PWM_CMP6V; /**< \brief (Pwm Offset: 0x190) PWM Comparison 6 Value Register */ - WoReg PWM_CMP6VUPD; /**< \brief (Pwm Offset: 0x194) PWM Comparison 6 Value Update Register */ - RwReg PWM_CMP6M; /**< \brief (Pwm Offset: 0x198) PWM Comparison 6 Mode Register */ - WoReg PWM_CMP6MUPD; /**< \brief (Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register */ - RwReg PWM_CMP7V; /**< \brief (Pwm Offset: 0x1A0) PWM Comparison 7 Value Register */ - WoReg PWM_CMP7VUPD; /**< \brief (Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register */ - RwReg PWM_CMP7M; /**< \brief (Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register */ - WoReg PWM_CMP7MUPD; /**< \brief (Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register */ - RwReg Reserved6[20]; - PwmCh_num PWM_CH_NUM[4]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ -} Pwm; -#endif /* __ASSEMBLY__ */ -/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ -#define PWM_CLK_DIVA (0xff << 0) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREA (0xf << 8) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -#define PWM_CLK_DIVB (0xff << 16) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREB (0xf << 24) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ -#define PWM_ENA_CHID0 (0x1 << 0) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID1 (0x1 << 1) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID2 (0x1 << 2) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID3 (0x1 << 3) /**< \brief (PWM_ENA) Channel ID */ -/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ -#define PWM_DIS_CHID0 (0x1 << 0) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID1 (0x1 << 1) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID2 (0x1 << 2) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID3 (0x1 << 3) /**< \brief (PWM_DIS) Channel ID */ -/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ -#define PWM_SR_CHID0 (0x1 << 0) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID1 (0x1 << 1) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID2 (0x1 << 2) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID3 (0x1 << 3) /**< \brief (PWM_SR) Channel ID */ -/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ -#define PWM_IER1_CHID0 (0x1 << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ -#define PWM_IER1_CHID1 (0x1 << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ -#define PWM_IER1_CHID2 (0x1 << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ -#define PWM_IER1_CHID3 (0x1 << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ -#define PWM_IER1_FCHID0 (0x1 << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ -#define PWM_IER1_FCHID1 (0x1 << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ -#define PWM_IER1_FCHID2 (0x1 << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ -#define PWM_IER1_FCHID3 (0x1 << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ -/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ -#define PWM_IDR1_CHID0 (0x1 << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ -#define PWM_IDR1_CHID1 (0x1 << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ -#define PWM_IDR1_CHID2 (0x1 << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ -#define PWM_IDR1_CHID3 (0x1 << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ -#define PWM_IDR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ -#define PWM_IDR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ -#define PWM_IDR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ -#define PWM_IDR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ -/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ -#define PWM_IMR1_CHID0 (0x1 << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ -#define PWM_IMR1_CHID1 (0x1 << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ -#define PWM_IMR1_CHID2 (0x1 << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ -#define PWM_IMR1_CHID3 (0x1 << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ -#define PWM_IMR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ -#define PWM_IMR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ -#define PWM_IMR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ -#define PWM_IMR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ -/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ -#define PWM_ISR1_CHID0 (0x1 << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ -#define PWM_ISR1_CHID1 (0x1 << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ -#define PWM_ISR1_CHID2 (0x1 << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ -#define PWM_ISR1_CHID3 (0x1 << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ -#define PWM_ISR1_FCHID0 (0x1 << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ -#define PWM_ISR1_FCHID1 (0x1 << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ -#define PWM_ISR1_FCHID2 (0x1 << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ -#define PWM_ISR1_FCHID3 (0x1 << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ -/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ -#define PWM_SCM_SYNC0 (0x1 << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ -#define PWM_SCM_SYNC1 (0x1 << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ -#define PWM_SCM_SYNC2 (0x1 << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ -#define PWM_SCM_SYNC3 (0x1 << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ -#define PWM_SCM_UPDM (0x3 << 16) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ -#define PWM_SCM_UPDM_MODE0 (0x0 << 16) // (PWMC) Manual write of data and manual trigger of the update -#define PWM_SCM_UPDM_MODE1 (0x1 << 16) // (PWMC) Manual write of data and automatic trigger of the update -#define PWM_SCM_UPDM_MODE2 (0x2 << 16) // (PWMC) Automatic write of data and automatic trigger of the update -#define PWM_SCM_PTRM (0x1 << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */ -#define PWM_SCM_PTRCS (0x7 << 21) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */ -/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ -#define PWM_SCUC_UPDULOCK (0x1 << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ -/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ -#define PWM_SCUP_UPR (0xf << 0) /**< \brief (PWM_SCUP) Update Period */ -#define PWM_SCUP_UPRCNT (0xf << 4) /**< \brief (PWM_SCUP) Update Period Counter */ -/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ -#define PWM_SCUPUPD_UPRUPD (0xf << 0) /**< \brief (PWM_SCUPUPD) Update Period Update */ -/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ -#define PWM_IER2_WRDY (0x1 << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ -#define PWM_IER2_ENDTX (0x1 << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */ -#define PWM_IER2_TXBUFE (0x1 << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */ -#define PWM_IER2_UNRE (0x1 << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ -#define PWM_IER2_CMPM0 (0x1 << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ -#define PWM_IER2_CMPM1 (0x1 << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ -#define PWM_IER2_CMPM2 (0x1 << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ -#define PWM_IER2_CMPM3 (0x1 << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ -#define PWM_IER2_CMPM4 (0x1 << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ -#define PWM_IER2_CMPM5 (0x1 << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ -#define PWM_IER2_CMPM6 (0x1 << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ -#define PWM_IER2_CMPM7 (0x1 << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ -#define PWM_IER2_CMPU0 (0x1 << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ -#define PWM_IER2_CMPU1 (0x1 << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ -#define PWM_IER2_CMPU2 (0x1 << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ -#define PWM_IER2_CMPU3 (0x1 << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ -#define PWM_IER2_CMPU4 (0x1 << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ -#define PWM_IER2_CMPU5 (0x1 << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ -#define PWM_IER2_CMPU6 (0x1 << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ -#define PWM_IER2_CMPU7 (0x1 << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ -/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ -#define PWM_IDR2_WRDY (0x1 << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ -#define PWM_IDR2_ENDTX (0x1 << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */ -#define PWM_IDR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */ -#define PWM_IDR2_UNRE (0x1 << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ -#define PWM_IDR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ -#define PWM_IDR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ -#define PWM_IDR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ -#define PWM_IDR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ -#define PWM_IDR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ -#define PWM_IDR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ -#define PWM_IDR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ -#define PWM_IDR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ -#define PWM_IDR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ -#define PWM_IDR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ -#define PWM_IDR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ -#define PWM_IDR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ -#define PWM_IDR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ -#define PWM_IDR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ -#define PWM_IDR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ -#define PWM_IDR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ -/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ -#define PWM_IMR2_WRDY (0x1 << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ -#define PWM_IMR2_ENDTX (0x1 << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */ -#define PWM_IMR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */ -#define PWM_IMR2_UNRE (0x1 << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ -#define PWM_IMR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ -#define PWM_IMR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ -#define PWM_IMR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ -#define PWM_IMR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ -#define PWM_IMR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ -#define PWM_IMR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ -#define PWM_IMR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ -#define PWM_IMR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ -#define PWM_IMR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ -#define PWM_IMR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ -#define PWM_IMR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ -#define PWM_IMR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ -#define PWM_IMR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ -#define PWM_IMR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ -#define PWM_IMR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ -#define PWM_IMR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ -/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ -#define PWM_ISR2_WRDY (0x1 << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ -#define PWM_ISR2_ENDTX (0x1 << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */ -#define PWM_ISR2_TXBUFE (0x1 << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */ -#define PWM_ISR2_UNRE (0x1 << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ -#define PWM_ISR2_CMPM0 (0x1 << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ -#define PWM_ISR2_CMPM1 (0x1 << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ -#define PWM_ISR2_CMPM2 (0x1 << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ -#define PWM_ISR2_CMPM3 (0x1 << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ -#define PWM_ISR2_CMPM4 (0x1 << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ -#define PWM_ISR2_CMPM5 (0x1 << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ -#define PWM_ISR2_CMPM6 (0x1 << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ -#define PWM_ISR2_CMPM7 (0x1 << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ -#define PWM_ISR2_CMPU0 (0x1 << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ -#define PWM_ISR2_CMPU1 (0x1 << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ -#define PWM_ISR2_CMPU2 (0x1 << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ -#define PWM_ISR2_CMPU3 (0x1 << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ -#define PWM_ISR2_CMPU4 (0x1 << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ -#define PWM_ISR2_CMPU5 (0x1 << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ -#define PWM_ISR2_CMPU6 (0x1 << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ -#define PWM_ISR2_CMPU7 (0x1 << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ -/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ -#define PWM_OOV_OOVH0 (0x1 << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ -#define PWM_OOV_OOVH1 (0x1 << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ -#define PWM_OOV_OOVH2 (0x1 << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ -#define PWM_OOV_OOVH3 (0x1 << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ -#define PWM_OOV_OOVL0 (0x1 << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ -#define PWM_OOV_OOVL1 (0x1 << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ -#define PWM_OOV_OOVL2 (0x1 << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ -#define PWM_OOV_OOVL3 (0x1 << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ -/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ -#define PWM_OS_OSH0 (0x1 << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ -#define PWM_OS_OSH1 (0x1 << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ -#define PWM_OS_OSH2 (0x1 << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ -#define PWM_OS_OSH3 (0x1 << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ -#define PWM_OS_OSL0 (0x1 << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ -#define PWM_OS_OSL1 (0x1 << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ -#define PWM_OS_OSL2 (0x1 << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ -#define PWM_OS_OSL3 (0x1 << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ -/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ -#define PWM_OSS_OSSH0 (0x1 << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSS_OSSH1 (0x1 << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSS_OSSH2 (0x1 << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSS_OSSH3 (0x1 << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSS_OSSL0 (0x1 << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSS_OSSL1 (0x1 << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSS_OSSL2 (0x1 << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSS_OSSL3 (0x1 << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ -#define PWM_OSC_OSCH0 (0x1 << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSC_OSCH1 (0x1 << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSC_OSCH2 (0x1 << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSC_OSCH3 (0x1 << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSC_OSCL0 (0x1 << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSC_OSCL1 (0x1 << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSC_OSCL2 (0x1 << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSC_OSCL3 (0x1 << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ -#define PWM_OSSUPD_OSSUPH0 (0x1 << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSSUPD_OSSUPH1 (0x1 << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSSUPD_OSSUPH2 (0x1 << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSSUPD_OSSUPH3 (0x1 << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSSUPD_OSSUPL0 (0x1 << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSSUPD_OSSUPL1 (0x1 << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSSUPD_OSSUPL2 (0x1 << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSSUPD_OSSUPL3 (0x1 << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ -#define PWM_OSCUPD_OSCUPH0 (0x1 << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSCUPD_OSCUPH1 (0x1 << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSCUPD_OSCUPH2 (0x1 << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSCUPD_OSCUPH3 (0x1 << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSCUPD_OSCUPL0 (0x1 << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSCUPD_OSCUPL1 (0x1 << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSCUPD_OSCUPL2 (0x1 << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSCUPD_OSCUPL3 (0x1 << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ -#define PWM_FMR_FPOL0 (0x1 << 0) /**< \brief (PWM_FMR) Fault 0 Polarity */ -#define PWM_FMR_FPOL1 (0x1 << 1) /**< \brief (PWM_FMR) Fault 1 Polarity */ -#define PWM_FMR_FPOL2 (0x1 << 2) /**< \brief (PWM_FMR) Fault 2 Polarity */ -#define PWM_FMR_FPOL3 (0x1 << 3) /**< \brief (PWM_FMR) Fault 3 Polarity */ -#define PWM_FMR_FMOD0 (0x1 << 8) /**< \brief (PWM_FMR) Fault 0 Activation Mode */ -#define PWM_FMR_FMOD1 (0x1 << 9) /**< \brief (PWM_FMR) Fault 1 Activation Mode */ -#define PWM_FMR_FMOD2 (0x1 << 10) /**< \brief (PWM_FMR) Fault 2 Activation Mode */ -#define PWM_FMR_FMOD3 (0x1 << 11) /**< \brief (PWM_FMR) Fault 3 Activation Mode */ -#define PWM_FMR_FFIL0 (0x1 << 16) /**< \brief (PWM_FMR) Fault 0 Filtering */ -#define PWM_FMR_FFIL1 (0x1 << 17) /**< \brief (PWM_FMR) Fault 1 Filtering */ -#define PWM_FMR_FFIL2 (0x1 << 18) /**< \brief (PWM_FMR) Fault 2 Filtering */ -#define PWM_FMR_FFIL3 (0x1 << 19) /**< \brief (PWM_FMR) Fault 3 Filtering */ -/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ -#define PWM_FSR_FIV0 (0x1 << 0) /**< \brief (PWM_FSR) Fault Input 0 Value */ -#define PWM_FSR_FIV1 (0x1 << 1) /**< \brief (PWM_FSR) Fault Input 1 Value */ -#define PWM_FSR_FIV2 (0x1 << 2) /**< \brief (PWM_FSR) Fault Input 2 Value */ -#define PWM_FSR_FIV3 (0x1 << 3) /**< \brief (PWM_FSR) Fault Input 3 Value */ -#define PWM_FSR_FS0 (0x1 << 8) /**< \brief (PWM_FSR) Fault 0 Status */ -#define PWM_FSR_FS1 (0x1 << 9) /**< \brief (PWM_FSR) Fault 1 Status */ -#define PWM_FSR_FS2 (0x1 << 10) /**< \brief (PWM_FSR) Fault 2 Status */ -#define PWM_FSR_FS3 (0x1 << 11) /**< \brief (PWM_FSR) Fault 3 Status */ -/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ -#define PWM_FCR_FCLR0 (0x1 << 0) /**< \brief (PWM_FCR) Fault 0 Clear */ -#define PWM_FCR_FCLR1 (0x1 << 1) /**< \brief (PWM_FCR) Fault 1 Clear */ -#define PWM_FCR_FCLR2 (0x1 << 2) /**< \brief (PWM_FCR) Fault 2 Clear */ -#define PWM_FCR_FCLR3 (0x1 << 3) /**< \brief (PWM_FCR) Fault 3 Clear */ -/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */ -#define PWM_FPV_FPVH0 (0x1 << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */ -#define PWM_FPV_FPVH1 (0x1 << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */ -#define PWM_FPV_FPVH2 (0x1 << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */ -#define PWM_FPV_FPVH3 (0x1 << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */ -#define PWM_FPV_FPVL0 (0x1 << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */ -#define PWM_FPV_FPVL1 (0x1 << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */ -#define PWM_FPV_FPVL2 (0x1 << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */ -#define PWM_FPV_FPVL3 (0x1 << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */ -/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ -#define PWM_FPE_FPE0 (0xff << 0) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 0 for channel x */ -#define PWM_FPE_FPE1 (0xff << 8) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 1 for channel x */ -#define PWM_FPE_FPE2 (0xff << 16) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 2 for channel x */ -#define PWM_FPE_FPE3 (0xff << 24) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 3 for channel x */ -/* -------- PWM_ELxMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ -#define PWM_ELxMR_CSEL0 (0x1 << 0) /**< \brief (PWM_ELxMR[2]) Comparison 0 Selection */ -#define PWM_ELxMR_CSEL1 (0x1 << 1) /**< \brief (PWM_ELxMR[2]) Comparison 1 Selection */ -#define PWM_ELxMR_CSEL2 (0x1 << 2) /**< \brief (PWM_ELxMR[2]) Comparison 2 Selection */ -#define PWM_ELxMR_CSEL3 (0x1 << 3) /**< \brief (PWM_ELxMR[2]) Comparison 3 Selection */ -#define PWM_ELxMR_CSEL4 (0x1 << 4) /**< \brief (PWM_ELxMR[2]) Comparison 4 Selection */ -#define PWM_ELxMR_CSEL5 (0x1 << 5) /**< \brief (PWM_ELxMR[2]) Comparison 5 Selection */ -#define PWM_ELxMR_CSEL6 (0x1 << 6) /**< \brief (PWM_ELxMR[2]) Comparison 6 Selection */ -#define PWM_ELxMR_CSEL7 (0x1 << 7) /**< \brief (PWM_ELxMR[2]) Comparison 7 Selection */ -/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ -#define PWM_WPCR_WPCMD (0x3 << 0) /**< \brief (PWM_WPCR) Write Protect Command */ -#define PWM_WPCR_WPRG0 (0x1 << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ -#define PWM_WPCR_WPRG1 (0x1 << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ -#define PWM_WPCR_WPRG2 (0x1 << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ -#define PWM_WPCR_WPRG3 (0x1 << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ -#define PWM_WPCR_WPRG4 (0x1 << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ -#define PWM_WPCR_WPRG5 (0x1 << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ -#define PWM_WPCR_WPKEY (0xffffff << 8) /**< \brief (PWM_WPCR) Write Protect Key */ -/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ -#define PWM_WPSR_WPSWS0 (0x1 << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS1 (0x1 << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS2 (0x1 << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS3 (0x1 << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS4 (0x1 << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS5 (0x1 << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPVS (0x1 << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ -#define PWM_WPSR_WPHWS0 (0x1 << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS1 (0x1 << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS2 (0x1 << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS3 (0x1 << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS4 (0x1 << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS5 (0x1 << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPVSRC (0xffff << 16) /**< \brief (PWM_WPSR) Write Protect Violation Source */ -/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */ -#define PWM_RPR_RXPTR (0xffffffff << 0) /**< \brief (PWM_RPR) Receive Pointer Register */ -/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */ -#define PWM_RCR_RXCTR (0xffff << 0) /**< \brief (PWM_RCR) Receive Counter Register */ -/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */ -#define PWM_TPR_TXPTR (0xffffffff << 0) /**< \brief (PWM_TPR) Transmit Counter Register */ -/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */ -#define PWM_TCR_TXCTR (0xffff << 0) /**< \brief (PWM_TCR) Transmit Counter Register */ -/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */ -#define PWM_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PWM_RNPR) Receive Next Pointer */ -/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */ -#define PWM_RNCR_RXNCTR (0xffff << 0) /**< \brief (PWM_RNCR) Receive Next Counter */ -/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PWM_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PWM_TNPR) Transmit Next Pointer */ -/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PWM_TNCR_TXNCTR (0xffff << 0) /**< \brief (PWM_TNCR) Transmit Counter Next */ -/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */ -#define PWM_PTCR_RXTEN (0x1 << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */ -#define PWM_PTCR_RXTDIS (0x1 << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */ -#define PWM_PTCR_TXTEN (0x1 << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */ -#define PWM_PTCR_TXTDIS (0x1 << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */ -/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */ -#define PWM_PTSR_RXTEN (0x1 << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */ -#define PWM_PTSR_TXTEN (0x1 << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */ -/* -------- PWM_CMP0V : (PWM Offset: 0x130) PWM Comparison 0 Value Register -------- */ -#define PWM_CMP0V_CV (0xffffff << 0) /**< \brief (PWM_CMP0V) Comparison x Value */ -#define PWM_CMP0V_CVM (0x1 << 24) /**< \brief (PWM_CMP0V) Comparison x Value Mode */ -/* -------- PWM_CMP0VUPD : (PWM Offset: 0x134) PWM Comparison 0 Value Update Register -------- */ -#define PWM_CMP0VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP0VUPD) Comparison x Value Update */ -#define PWM_CMP0VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP0VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP0M : (PWM Offset: 0x138) PWM Comparison 0 Mode Register -------- */ -#define PWM_CMP0M_CEN (0x1 << 0) /**< \brief (PWM_CMP0M) Comparison x Enable */ -#define PWM_CMP0M_CTR (0xf << 4) /**< \brief (PWM_CMP0M) Comparison x Trigger */ -#define PWM_CMP0M_CPR (0xf << 8) /**< \brief (PWM_CMP0M) Comparison x Period */ -#define PWM_CMP0M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP0M) Comparison x Period Counter */ -#define PWM_CMP0M_CUPR (0xf << 16) /**< \brief (PWM_CMP0M) Comparison x Update Period */ -#define PWM_CMP0M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP0M) Comparison x Update Period Counter */ -/* -------- PWM_CMP0MUPD : (PWM Offset: 0x13C) PWM Comparison 0 Mode Update Register -------- */ -#define PWM_CMP0MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP0MUPD) Comparison x Enable Update */ -#define PWM_CMP0MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP0MUPD) Comparison x Trigger Update */ -#define PWM_CMP0MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP0MUPD) Comparison x Period Update */ -#define PWM_CMP0MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP0MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP1V : (PWM Offset: 0x140) PWM Comparison 1 Value Register -------- */ -#define PWM_CMP1V_CV (0xffffff << 0) /**< \brief (PWM_CMP1V) Comparison x Value */ -#define PWM_CMP1V_CVM (0x1 << 24) /**< \brief (PWM_CMP1V) Comparison x Value Mode */ -/* -------- PWM_CMP1VUPD : (PWM Offset: 0x144) PWM Comparison 1 Value Update Register -------- */ -#define PWM_CMP1VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP1VUPD) Comparison x Value Update */ -#define PWM_CMP1VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP1VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP1M : (PWM Offset: 0x148) PWM Comparison 1 Mode Register -------- */ -#define PWM_CMP1M_CEN (0x1 << 0) /**< \brief (PWM_CMP1M) Comparison x Enable */ -#define PWM_CMP1M_CTR (0xf << 4) /**< \brief (PWM_CMP1M) Comparison x Trigger */ -#define PWM_CMP1M_CPR (0xf << 8) /**< \brief (PWM_CMP1M) Comparison x Period */ -#define PWM_CMP1M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP1M) Comparison x Period Counter */ -#define PWM_CMP1M_CUPR (0xf << 16) /**< \brief (PWM_CMP1M) Comparison x Update Period */ -#define PWM_CMP1M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP1M) Comparison x Update Period Counter */ -/* -------- PWM_CMP1MUPD : (PWM Offset: 0x14C) PWM Comparison 1 Mode Update Register -------- */ -#define PWM_CMP1MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP1MUPD) Comparison x Enable Update */ -#define PWM_CMP1MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP1MUPD) Comparison x Trigger Update */ -#define PWM_CMP1MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP1MUPD) Comparison x Period Update */ -#define PWM_CMP1MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP1MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP2V : (PWM Offset: 0x150) PWM Comparison 2 Value Register -------- */ -#define PWM_CMP2V_CV (0xffffff << 0) /**< \brief (PWM_CMP2V) Comparison x Value */ -#define PWM_CMP2V_CVM (0x1 << 24) /**< \brief (PWM_CMP2V) Comparison x Value Mode */ -/* -------- PWM_CMP2VUPD : (PWM Offset: 0x154) PWM Comparison 2 Value Update Register -------- */ -#define PWM_CMP2VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP2VUPD) Comparison x Value Update */ -#define PWM_CMP2VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP2VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP2M : (PWM Offset: 0x158) PWM Comparison 2 Mode Register -------- */ -#define PWM_CMP2M_CEN (0x1 << 0) /**< \brief (PWM_CMP2M) Comparison x Enable */ -#define PWM_CMP2M_CTR (0xf << 4) /**< \brief (PWM_CMP2M) Comparison x Trigger */ -#define PWM_CMP2M_CPR (0xf << 8) /**< \brief (PWM_CMP2M) Comparison x Period */ -#define PWM_CMP2M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP2M) Comparison x Period Counter */ -#define PWM_CMP2M_CUPR (0xf << 16) /**< \brief (PWM_CMP2M) Comparison x Update Period */ -#define PWM_CMP2M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP2M) Comparison x Update Period Counter */ -/* -------- PWM_CMP2MUPD : (PWM Offset: 0x15C) PWM Comparison 2 Mode Update Register -------- */ -#define PWM_CMP2MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP2MUPD) Comparison x Enable Update */ -#define PWM_CMP2MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP2MUPD) Comparison x Trigger Update */ -#define PWM_CMP2MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP2MUPD) Comparison x Period Update */ -#define PWM_CMP2MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP2MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP3V : (PWM Offset: 0x160) PWM Comparison 3 Value Register -------- */ -#define PWM_CMP3V_CV (0xffffff << 0) /**< \brief (PWM_CMP3V) Comparison x Value */ -#define PWM_CMP3V_CVM (0x1 << 24) /**< \brief (PWM_CMP3V) Comparison x Value Mode */ -/* -------- PWM_CMP3VUPD : (PWM Offset: 0x164) PWM Comparison 3 Value Update Register -------- */ -#define PWM_CMP3VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP3VUPD) Comparison x Value Update */ -#define PWM_CMP3VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP3VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP3M : (PWM Offset: 0x168) PWM Comparison 3 Mode Register -------- */ -#define PWM_CMP3M_CEN (0x1 << 0) /**< \brief (PWM_CMP3M) Comparison x Enable */ -#define PWM_CMP3M_CTR (0xf << 4) /**< \brief (PWM_CMP3M) Comparison x Trigger */ -#define PWM_CMP3M_CPR (0xf << 8) /**< \brief (PWM_CMP3M) Comparison x Period */ -#define PWM_CMP3M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP3M) Comparison x Period Counter */ -#define PWM_CMP3M_CUPR (0xf << 16) /**< \brief (PWM_CMP3M) Comparison x Update Period */ -#define PWM_CMP3M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP3M) Comparison x Update Period Counter */ -/* -------- PWM_CMP3MUPD : (PWM Offset: 0x16C) PWM Comparison 3 Mode Update Register -------- */ -#define PWM_CMP3MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP3MUPD) Comparison x Enable Update */ -#define PWM_CMP3MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP3MUPD) Comparison x Trigger Update */ -#define PWM_CMP3MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP3MUPD) Comparison x Period Update */ -#define PWM_CMP3MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP3MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP4V : (PWM Offset: 0x170) PWM Comparison 4 Value Register -------- */ -#define PWM_CMP4V_CV (0xffffff << 0) /**< \brief (PWM_CMP4V) Comparison x Value */ -#define PWM_CMP4V_CVM (0x1 << 24) /**< \brief (PWM_CMP4V) Comparison x Value Mode */ -/* -------- PWM_CMP4VUPD : (PWM Offset: 0x174) PWM Comparison 4 Value Update Register -------- */ -#define PWM_CMP4VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP4VUPD) Comparison x Value Update */ -#define PWM_CMP4VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP4VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP4M : (PWM Offset: 0x178) PWM Comparison 4 Mode Register -------- */ -#define PWM_CMP4M_CEN (0x1 << 0) /**< \brief (PWM_CMP4M) Comparison x Enable */ -#define PWM_CMP4M_CTR (0xf << 4) /**< \brief (PWM_CMP4M) Comparison x Trigger */ -#define PWM_CMP4M_CPR (0xf << 8) /**< \brief (PWM_CMP4M) Comparison x Period */ -#define PWM_CMP4M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP4M) Comparison x Period Counter */ -#define PWM_CMP4M_CUPR (0xf << 16) /**< \brief (PWM_CMP4M) Comparison x Update Period */ -#define PWM_CMP4M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP4M) Comparison x Update Period Counter */ -/* -------- PWM_CMP4MUPD : (PWM Offset: 0x17C) PWM Comparison 4 Mode Update Register -------- */ -#define PWM_CMP4MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP4MUPD) Comparison x Enable Update */ -#define PWM_CMP4MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP4MUPD) Comparison x Trigger Update */ -#define PWM_CMP4MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP4MUPD) Comparison x Period Update */ -#define PWM_CMP4MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP4MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP5V : (PWM Offset: 0x180) PWM Comparison 5 Value Register -------- */ -#define PWM_CMP5V_CV (0xffffff << 0) /**< \brief (PWM_CMP5V) Comparison x Value */ -#define PWM_CMP5V_CVM (0x1 << 24) /**< \brief (PWM_CMP5V) Comparison x Value Mode */ -/* -------- PWM_CMP5VUPD : (PWM Offset: 0x184) PWM Comparison 5 Value Update Register -------- */ -#define PWM_CMP5VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP5VUPD) Comparison x Value Update */ -#define PWM_CMP5VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP5VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP5M : (PWM Offset: 0x188) PWM Comparison 5 Mode Register -------- */ -#define PWM_CMP5M_CEN (0x1 << 0) /**< \brief (PWM_CMP5M) Comparison x Enable */ -#define PWM_CMP5M_CTR (0xf << 4) /**< \brief (PWM_CMP5M) Comparison x Trigger */ -#define PWM_CMP5M_CPR (0xf << 8) /**< \brief (PWM_CMP5M) Comparison x Period */ -#define PWM_CMP5M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP5M) Comparison x Period Counter */ -#define PWM_CMP5M_CUPR (0xf << 16) /**< \brief (PWM_CMP5M) Comparison x Update Period */ -#define PWM_CMP5M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP5M) Comparison x Update Period Counter */ -/* -------- PWM_CMP5MUPD : (PWM Offset: 0x18C) PWM Comparison 5 Mode Update Register -------- */ -#define PWM_CMP5MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP5MUPD) Comparison x Enable Update */ -#define PWM_CMP5MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP5MUPD) Comparison x Trigger Update */ -#define PWM_CMP5MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP5MUPD) Comparison x Period Update */ -#define PWM_CMP5MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP5MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP6V : (PWM Offset: 0x190) PWM Comparison 6 Value Register -------- */ -#define PWM_CMP6V_CV (0xffffff << 0) /**< \brief (PWM_CMP6V) Comparison x Value */ -#define PWM_CMP6V_CVM (0x1 << 24) /**< \brief (PWM_CMP6V) Comparison x Value Mode */ -/* -------- PWM_CMP6VUPD : (PWM Offset: 0x194) PWM Comparison 6 Value Update Register -------- */ -#define PWM_CMP6VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP6VUPD) Comparison x Value Update */ -#define PWM_CMP6VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP6VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP6M : (PWM Offset: 0x198) PWM Comparison 6 Mode Register -------- */ -#define PWM_CMP6M_CEN (0x1 << 0) /**< \brief (PWM_CMP6M) Comparison x Enable */ -#define PWM_CMP6M_CTR (0xf << 4) /**< \brief (PWM_CMP6M) Comparison x Trigger */ -#define PWM_CMP6M_CPR (0xf << 8) /**< \brief (PWM_CMP6M) Comparison x Period */ -#define PWM_CMP6M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP6M) Comparison x Period Counter */ -#define PWM_CMP6M_CUPR (0xf << 16) /**< \brief (PWM_CMP6M) Comparison x Update Period */ -#define PWM_CMP6M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP6M) Comparison x Update Period Counter */ -/* -------- PWM_CMP6MUPD : (PWM Offset: 0x19C) PWM Comparison 6 Mode Update Register -------- */ -#define PWM_CMP6MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP6MUPD) Comparison x Enable Update */ -#define PWM_CMP6MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP6MUPD) Comparison x Trigger Update */ -#define PWM_CMP6MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP6MUPD) Comparison x Period Update */ -#define PWM_CMP6MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP6MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP7V : (PWM Offset: 0x1A0) PWM Comparison 7 Value Register -------- */ -#define PWM_CMP7V_CV (0xffffff << 0) /**< \brief (PWM_CMP7V) Comparison x Value */ -#define PWM_CMP7V_CVM (0x1 << 24) /**< \brief (PWM_CMP7V) Comparison x Value Mode */ -/* -------- PWM_CMP7VUPD : (PWM Offset: 0x1A4) PWM Comparison 7 Value Update Register -------- */ -#define PWM_CMP7VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP7VUPD) Comparison x Value Update */ -#define PWM_CMP7VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP7VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP7M : (PWM Offset: 0x1A8) PWM Comparison 7 Mode Register -------- */ -#define PWM_CMP7M_CEN (0x1 << 0) /**< \brief (PWM_CMP7M) Comparison x Enable */ -#define PWM_CMP7M_CTR (0xf << 4) /**< \brief (PWM_CMP7M) Comparison x Trigger */ -#define PWM_CMP7M_CPR (0xf << 8) /**< \brief (PWM_CMP7M) Comparison x Period */ -#define PWM_CMP7M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP7M) Comparison x Period Counter */ -#define PWM_CMP7M_CUPR (0xf << 16) /**< \brief (PWM_CMP7M) Comparison x Update Period */ -#define PWM_CMP7M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP7M) Comparison x Update Period Counter */ -/* -------- PWM_CMP7MUPD : (PWM Offset: 0x1AC) PWM Comparison 7 Mode Update Register -------- */ -#define PWM_CMP7MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP7MUPD) Comparison x Enable Update */ -#define PWM_CMP7MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP7MUPD) Comparison x Trigger Update */ -#define PWM_CMP7MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP7MUPD) Comparison x Period Update */ -#define PWM_CMP7MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP7MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMR0 : (PWM Offset: 0x200) PWM Channel Mode Register (ch_num = 0) -------- */ -#define PWM_CMR0_CPRE (0xf << 0) /**< \brief (PWM_CMR0) Channel Pre-scaler */ -#define PWM_CMR0_CPRE_MCK_DIV_2 (0x1) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_4 (0x2) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_8 (0x3) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_16 (0x4) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_32 (0x5) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_64 (0x6) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_128 (0x7) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_256 (0x8) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_512 (0x9) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_1024 (0xA) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCKA (0xB) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCKB (0xC) // (PWMC_CH) -#define PWM_CMR0_CALG (0x1 << 8) /**< \brief (PWM_CMR0) Channel Alignment */ -#define PWM_CMR0_CPOL (0x1 << 9) /**< \brief (PWM_CMR0) Channel Polarity */ -#define PWM_CMR0_CES (0x1 << 10) /**< \brief (PWM_CMR0) Counter Event Selection */ -#define PWM_CMR0_DTE (0x1 << 16) /**< \brief (PWM_CMR0) Dead-Time Generator Enable */ -#define PWM_CMR0_DTHI (0x1 << 17) /**< \brief (PWM_CMR0) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR0_DTLI (0x1 << 18) /**< \brief (PWM_CMR0) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY0 : (PWM Offset: 0x204) PWM Channel Duty Cycle Register (ch_num = 0) -------- */ -#define PWM_CDTY0_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY0) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD0 : (PWM Offset: 0x208) PWM Channel Duty Cycle Update Register (ch_num = 0) -------- */ -#define PWM_CDTYUPD0_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD0) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD0 : (PWM Offset: 0x20C) PWM Channel Period Register (ch_num = 0) -------- */ -#define PWM_CPRD0_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD0) Channel Period */ -/* -------- PWM_CPRDUPD0 : (PWM Offset: 0x210) PWM Channel Period Update Register (ch_num = 0) -------- */ -#define PWM_CPRDUPD0_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD0) Channel Period Update */ -/* -------- PWM_CCNT0 : (PWM Offset: 0x214) PWM Channel Counter Register (ch_num = 0) -------- */ -#define PWM_CCNT0_CNT (0xffffff << 0) /**< \brief (PWM_CCNT0) Channel Counter Register */ -/* -------- PWM_DT0 : (PWM Offset: 0x218) PWM Channel Dead Time Register (ch_num = 0) -------- */ -#define PWM_DT0_DTH (0xffff << 0) /**< \brief (PWM_DT0) Dead-Time Value for PWMHx Output */ -#define PWM_DT0_DTL (0xffff << 16) /**< \brief (PWM_DT0) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD0 : (PWM Offset: 0x21C) PWM Channel Dead Time Update Register (ch_num = 0) -------- */ -#define PWM_DTUPD0_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD0_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR1 : (PWM Offset: 0x220) PWM Channel Mode Register (ch_num = 1) -------- */ -#define PWM_CMR1_CPRE (0xf << 0) /**< \brief (PWM_CMR1) Channel Pre-scaler */ -#define PWM_CMR1_CPRE_MCK_DIV_2 (0x1) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_4 (0x2) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_8 (0x3) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_16 (0x4) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_32 (0x5) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_64 (0x6) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_128 (0x7) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_256 (0x8) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_512 (0x9) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_1024 (0xA) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCKA (0xB) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCKB (0xC) // (PWMC_CH) -#define PWM_CMR1_CALG (0x1 << 8) /**< \brief (PWM_CMR1) Channel Alignment */ -#define PWM_CMR1_CPOL (0x1 << 9) /**< \brief (PWM_CMR1) Channel Polarity */ -#define PWM_CMR1_CES (0x1 << 10) /**< \brief (PWM_CMR1) Counter Event Selection */ -#define PWM_CMR1_DTE (0x1 << 16) /**< \brief (PWM_CMR1) Dead-Time Generator Enable */ -#define PWM_CMR1_DTHI (0x1 << 17) /**< \brief (PWM_CMR1) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR1_DTLI (0x1 << 18) /**< \brief (PWM_CMR1) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY1 : (PWM Offset: 0x224) PWM Channel Duty Cycle Register (ch_num = 1) -------- */ -#define PWM_CDTY1_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY1) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD1 : (PWM Offset: 0x228) PWM Channel Duty Cycle Update Register (ch_num = 1) -------- */ -#define PWM_CDTYUPD1_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD1) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD1 : (PWM Offset: 0x22C) PWM Channel Period Register (ch_num = 1) -------- */ -#define PWM_CPRD1_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD1) Channel Period */ -/* -------- PWM_CPRDUPD1 : (PWM Offset: 0x230) PWM Channel Period Update Register (ch_num = 1) -------- */ -#define PWM_CPRDUPD1_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD1) Channel Period Update */ -/* -------- PWM_CCNT1 : (PWM Offset: 0x234) PWM Channel Counter Register (ch_num = 1) -------- */ -#define PWM_CCNT1_CNT (0xffffff << 0) /**< \brief (PWM_CCNT1) Channel Counter Register */ -/* -------- PWM_DT1 : (PWM Offset: 0x238) PWM Channel Dead Time Register (ch_num = 1) -------- */ -#define PWM_DT1_DTH (0xffff << 0) /**< \brief (PWM_DT1) Dead-Time Value for PWMHx Output */ -#define PWM_DT1_DTL (0xffff << 16) /**< \brief (PWM_DT1) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD1 : (PWM Offset: 0x23C) PWM Channel Dead Time Update Register (ch_num = 1) -------- */ -#define PWM_DTUPD1_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD1_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR2 : (PWM Offset: 0x240) PWM Channel Mode Register (ch_num = 2) -------- */ -#define PWM_CMR2_CPRE (0xf << 0) /**< \brief (PWM_CMR2) Channel Pre-scaler */ -#define PWM_CMR2_CPRE_MCK_DIV_2 (0x1) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_4 (0x2) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_8 (0x3) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_16 (0x4) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_32 (0x5) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_64 (0x6) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_128 (0x7) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_256 (0x8) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_512 (0x9) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_1024 (0xA) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCKA (0xB) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCKB (0xC) // (PWMC_CH) -#define PWM_CMR2_CALG (0x1 << 8) /**< \brief (PWM_CMR2) Channel Alignment */ -#define PWM_CMR2_CPOL (0x1 << 9) /**< \brief (PWM_CMR2) Channel Polarity */ -#define PWM_CMR2_CES (0x1 << 10) /**< \brief (PWM_CMR2) Counter Event Selection */ -#define PWM_CMR2_DTE (0x1 << 16) /**< \brief (PWM_CMR2) Dead-Time Generator Enable */ -#define PWM_CMR2_DTHI (0x1 << 17) /**< \brief (PWM_CMR2) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR2_DTLI (0x1 << 18) /**< \brief (PWM_CMR2) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY2 : (PWM Offset: 0x244) PWM Channel Duty Cycle Register (ch_num = 2) -------- */ -#define PWM_CDTY2_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY2) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD2 : (PWM Offset: 0x248) PWM Channel Duty Cycle Update Register (ch_num = 2) -------- */ -#define PWM_CDTYUPD2_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD2) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD2 : (PWM Offset: 0x24C) PWM Channel Period Register (ch_num = 2) -------- */ -#define PWM_CPRD2_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD2) Channel Period */ -/* -------- PWM_CPRDUPD2 : (PWM Offset: 0x250) PWM Channel Period Update Register (ch_num = 2) -------- */ -#define PWM_CPRDUPD2_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD2) Channel Period Update */ -/* -------- PWM_CCNT2 : (PWM Offset: 0x254) PWM Channel Counter Register (ch_num = 2) -------- */ -#define PWM_CCNT2_CNT (0xffffff << 0) /**< \brief (PWM_CCNT2) Channel Counter Register */ -/* -------- PWM_DT2 : (PWM Offset: 0x258) PWM Channel Dead Time Register (ch_num = 2) -------- */ -#define PWM_DT2_DTH (0xffff << 0) /**< \brief (PWM_DT2) Dead-Time Value for PWMHx Output */ -#define PWM_DT2_DTL (0xffff << 16) /**< \brief (PWM_DT2) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD2 : (PWM Offset: 0x25C) PWM Channel Dead Time Update Register (ch_num = 2) -------- */ -#define PWM_DTUPD2_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD2_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR3 : (PWM Offset: 0x260) PWM Channel Mode Register (ch_num = 3) -------- */ -#define PWM_CMR3_CPRE (0xf << 0) /**< \brief (PWM_CMR3) Channel Pre-scaler */ -#define PWM_CMR3_CPRE_MCK_DIV_2 (0x1) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_4 (0x2) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_8 (0x3) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_16 (0x4) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_32 (0x5) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_64 (0x6) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_128 (0x7) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_256 (0x8) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_512 (0x9) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_1024 (0xA) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCKA (0xB) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCKB (0xC) // (PWMC_CH) -#define PWM_CMR3_CALG (0x1 << 8) /**< \brief (PWM_CMR3) Channel Alignment */ -#define PWM_CMR3_CPOL (0x1 << 9) /**< \brief (PWM_CMR3) Channel Polarity */ -#define PWM_CMR3_CES (0x1 << 10) /**< \brief (PWM_CMR3) Counter Event Selection */ -#define PWM_CMR3_DTE (0x1 << 16) /**< \brief (PWM_CMR3) Dead-Time Generator Enable */ -#define PWM_CMR3_DTHI (0x1 << 17) /**< \brief (PWM_CMR3) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR3_DTLI (0x1 << 18) /**< \brief (PWM_CMR3) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY3 : (PWM Offset: 0x264) PWM Channel Duty Cycle Register (ch_num = 3) -------- */ -#define PWM_CDTY3_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY3) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD3 : (PWM Offset: 0x268) PWM Channel Duty Cycle Update Register (ch_num = 3) -------- */ -#define PWM_CDTYUPD3_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD3) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD3 : (PWM Offset: 0x26C) PWM Channel Period Register (ch_num = 3) -------- */ -#define PWM_CPRD3_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD3) Channel Period */ -/* -------- PWM_CPRDUPD3 : (PWM Offset: 0x270) PWM Channel Period Update Register (ch_num = 3) -------- */ -#define PWM_CPRDUPD3_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD3) Channel Period Update */ -/* -------- PWM_CCNT3 : (PWM Offset: 0x274) PWM Channel Counter Register (ch_num = 3) -------- */ -#define PWM_CCNT3_CNT (0xffffff << 0) /**< \brief (PWM_CCNT3) Channel Counter Register */ -/* -------- PWM_DT3 : (PWM Offset: 0x278) PWM Channel Dead Time Register (ch_num = 3) -------- */ -#define PWM_DT3_DTH (0xffff << 0) /**< \brief (PWM_DT3) Dead-Time Value for PWMHx Output */ -#define PWM_DT3_DTL (0xffff << 16) /**< \brief (PWM_DT3) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD3 : (PWM Offset: 0x27C) PWM Channel Dead Time Update Register (ch_num = 3) -------- */ -#define PWM_DTUPD3_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD3_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMLx Output */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Reset Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_RSTC Reset Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rstc hardware registers */ -typedef struct { - WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ - RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ - RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ -} Rstc; -#endif /* __ASSEMBLY__ */ -/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ -#define RSTC_CR_PROCRST (0x1 << 0) /**< \brief (RSTC_CR) Processor Reset */ -#define RSTC_CR_PERRST (0x1 << 2) /**< \brief (RSTC_CR) Peripheral Reset */ -#define RSTC_CR_EXTRST (0x1 << 3) /**< \brief (RSTC_CR) External Reset */ -#define RSTC_CR_KEY (0xff << 24) /**< \brief (RSTC_CR) Password */ -/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ -#define RSTC_SR_URSTS (0x1 << 0) /**< \brief (RSTC_SR) User Reset Status */ -#define RSTC_SR_RSTTYP (0x7 << 8) /**< \brief (RSTC_SR) Reset Type */ -#define RSTC_SR_NRSTL (0x1 << 16) /**< \brief (RSTC_SR) NRST Pin Level */ -#define RSTC_SR_SRCMP (0x1 << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ -/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ -#define RSTC_MR_URSTEN (0x1 << 0) /**< \brief (RSTC_MR) User Reset Enable */ -#define RSTC_MR_URSTIEN (0x1 << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ -#define RSTC_MR_ERSTL (0xf << 8) /**< \brief (RSTC_MR) External Reset Length */ -#define RSTC_MR_KEY (0xff << 24) /**< \brief (RSTC_MR) Password */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Clock */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_RTC Real-time Clock */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtc hardware registers */ -typedef struct { - RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ - RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ - RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ - RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ - RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ - RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ - RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ - WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ - WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ - WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ - RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ - RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ -} Rtc; -#endif /* __ASSEMBLY__ */ -/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ -#define RTC_CR_UPDTIM (0x1 << 0) /**< \brief (RTC_CR) Update Request Time Register */ -#define RTC_CR_UPDCAL (0x1 << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ -#define RTC_CR_TIMEVSEL (0x3 << 8) /**< \brief (RTC_CR) Time Event Selection */ -#define RTC_CR_TIMEVSEL_MINUTE (0x0 << 8) /**< \brief (RTC_CR) Minute change. */ -#define RTC_CR_TIMEVSEL_HOUR (0x1 << 8) /**< \brief (RTC_CR) Hour change. */ -#define RTC_CR_TIMEVSEL_DAY24 (0x2 << 8) /**< \brief (RTC_CR) Every day at midnight. */ -#define RTC_CR_TIMEVSEL_DAY12 (0x3 << 8) /**< \brief (RTC_CR) Every day at noon. */ -#define RTC_CR_CALEVSEL (0x3 << 16) /**< \brief (RTC_CR) Calendar Event Selection */ -#define RTC_CR_CALEVSEL_WEEK (0x0 << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00). */ -#define RTC_CR_CALEVSEL_MONTH (0x1 << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00). */ -/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ -#define RTC_MR_HRMOD (0x1 << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ -/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ -#define RTC_TIMR_SEC (0x7f << 0) /**< \brief (RTC_TIMR) Current Second */ -#define RTC_TIMR_MIN (0x7f << 8) /**< \brief (RTC_TIMR) Current Minute */ -#define RTC_TIMR_HOUR (0x3f << 16) /**< \brief (RTC_TIMR) Current Hour */ -#define RTC_TIMR_AMPM (0x1 << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ -/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ -#define RTC_CALR_CENT (0x7f << 0) /**< \brief (RTC_CALR) Current Century */ -#define RTC_CALR_YEAR (0xff << 8) /**< \brief (RTC_CALR) Current Year */ -#define RTC_CALR_MONTH (0x1f << 16) /**< \brief (RTC_CALR) Current Month */ -#define RTC_CALR_DAY (0x7 << 21) /**< \brief (RTC_CALR) Current Day in Current Week */ -#define RTC_CALR_DATE (0x3f << 24) /**< \brief (RTC_CALR) Current Day in Current Month */ -/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ -#define RTC_TIMALR_SEC (0x7f << 0) /**< \brief (RTC_TIMALR) Second Alarm */ -#define RTC_TIMALR_SECEN (0x1 << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ -#define RTC_TIMALR_MIN (0x7f << 8) /**< \brief (RTC_TIMALR) Minute Alarm */ -#define RTC_TIMALR_MINEN (0x1 << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ -#define RTC_TIMALR_HOUR (0x3f << 16) /**< \brief (RTC_TIMALR) Hour Alarm */ -#define RTC_TIMALR_AMPM (0x1 << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ -#define RTC_TIMALR_HOUREN (0x1 << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ -/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ -#define RTC_CALALR_MONTH (0x1f << 16) /**< \brief (RTC_CALALR) Month Alarm */ -#define RTC_CALALR_MTHEN (0x1 << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ -#define RTC_CALALR_DATE (0x3f << 24) /**< \brief (RTC_CALALR) Date Alarm */ -#define RTC_CALALR_DATEEN (0x1 << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ -/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ -#define RTC_SR_ACKUPD (0x1 << 0) /**< \brief (RTC_SR) Acknowledge for Update */ -#define RTC_SR_ALARM (0x1 << 1) /**< \brief (RTC_SR) Alarm Flag */ -#define RTC_SR_SEC (0x1 << 2) /**< \brief (RTC_SR) Second Event */ -#define RTC_SR_TIMEV (0x1 << 3) /**< \brief (RTC_SR) Time Event */ -#define RTC_SR_CALEV (0x1 << 4) /**< \brief (RTC_SR) Calendar Event */ -/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ -#define RTC_SCCR_ACKCLR (0x1 << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ -#define RTC_SCCR_ALRCLR (0x1 << 1) /**< \brief (RTC_SCCR) Alarm Clear */ -#define RTC_SCCR_SECCLR (0x1 << 2) /**< \brief (RTC_SCCR) Second Clear */ -#define RTC_SCCR_TIMCLR (0x1 << 3) /**< \brief (RTC_SCCR) Time Clear */ -#define RTC_SCCR_CALCLR (0x1 << 4) /**< \brief (RTC_SCCR) Calendar Clear */ -/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ -#define RTC_IER_ACKEN (0x1 << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ -#define RTC_IER_ALREN (0x1 << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ -#define RTC_IER_SECEN (0x1 << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ -#define RTC_IER_TIMEN (0x1 << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ -#define RTC_IER_CALEN (0x1 << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ -/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ -#define RTC_IDR_ACKDIS (0x1 << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ -#define RTC_IDR_ALRDIS (0x1 << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ -#define RTC_IDR_SECDIS (0x1 << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ -#define RTC_IDR_TIMDIS (0x1 << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ -#define RTC_IDR_CALDIS (0x1 << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ -/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ -#define RTC_IMR_ACK (0x1 << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ -#define RTC_IMR_ALR (0x1 << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ -#define RTC_IMR_SEC (0x1 << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ -#define RTC_IMR_TIM (0x1 << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ -#define RTC_IMR_CAL (0x1 << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ -/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ -#define RTC_VER_NVTIM (0x1 << 0) /**< \brief (RTC_VER) Non-valid Time */ -#define RTC_VER_NVCAL (0x1 << 1) /**< \brief (RTC_VER) Non-valid Calendar */ -#define RTC_VER_NVTIMALR (0x1 << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ -#define RTC_VER_NVCALALR (0x1 << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_RTT Real-time Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtt hardware registers */ -typedef struct { - RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ - RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ - RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ - RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ -} Rtt; -#endif /* __ASSEMBLY__ */ -/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ -#define RTT_MR_RTPRES (0xffff << 0) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ -#define RTT_MR_ALMIEN (0x1 << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ -#define RTT_MR_RTTINCIEN (0x1 << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ -#define RTT_MR_RTTRST (0x1 << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ -/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ -#define RTT_AR_ALMV (0xffffffff << 0) /**< \brief (RTT_AR) Alarm Value */ -/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ -#define RTT_VR_CRTV (0xffffffff << 0) /**< \brief (RTT_VR) Current Real-time Value */ -/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ -#define RTT_SR_ALMS (0x1 << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ -#define RTT_SR_RTTINC (0x1 << 1) /**< \brief (RTT_SR) Real-time Timer Increment */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Static Memory Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_SMC Static Memory Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief SmcCs_number hardware registers */ -typedef struct { - RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC SETUP Register */ - RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC PULSE Register */ - RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC CYCLE Register */ - RwReg SMC_TIMINGS; /**< \brief (SmcCs_number Offset: 0xC) SMC TIMINGS Register */ - RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0x10) SMC MODE Register */ -} SmcCs_number; -/** \brief Smc hardware registers */ -typedef struct { - RwReg SMC_CFG; /**< \brief (Smc Offset: 0x000) SMC NFC Configuration Register */ - WoReg SMC_CTRL; /**< \brief (Smc Offset: 0x004) SMC NFC Control Register */ - RoReg SMC_SR; /**< \brief (Smc Offset: 0x008) SMC NFC Status Register */ - WoReg SMC_IER; /**< \brief (Smc Offset: 0x00C) SMC NFC Interrupt Enable Register */ - WoReg SMC_IDR; /**< \brief (Smc Offset: 0x010) SMC NFC Interrupt Disable Register */ - RoReg SMC_IMR; /**< \brief (Smc Offset: 0x014) SMC NFC Interrupt Mask Register */ - RwReg SMC_ADDR; /**< \brief (Smc Offset: 0x018) SMC NFC Address Cycle Zero Register */ - RwReg SMC_BANK; /**< \brief (Smc Offset: 0x01C) SMC Bank Address Register */ - WoReg SMC_ECC_CTRL; /**< \brief (Smc Offset: 0x020) SMC ECC Control Register */ - RwReg SMC_ECC_MD; /**< \brief (Smc Offset: 0x024) SMC ECC Mode Register */ - RoReg SMC_ECC_SR1; /**< \brief (Smc Offset: 0x028) SMC ECC Status 1 Register */ - RoReg SMC_ECC_PR0; /**< \brief (Smc Offset: 0x02C) SMC ECC Parity 0 Register */ - RoReg SMC_ECC_PR1; /**< \brief (Smc Offset: 0x030) SMC ECC parity 1 Register */ - RoReg SMC_ECC_SR2; /**< \brief (Smc Offset: 0x034) SMC ECC status 2 Register */ - RoReg SMC_ECC_PR2; /**< \brief (Smc Offset: 0x038) SMC ECC parity 2 Register */ - RoReg SMC_ECC_PR3; /**< \brief (Smc Offset: 0x03C) SMC ECC parity 3 Register */ - RoReg SMC_ECC_PR4; /**< \brief (Smc Offset: 0x040) SMC ECC parity 4 Register */ - RoReg SMC_ECC_PR5; /**< \brief (Smc Offset: 0x044) SMC ECC parity 5 Register */ - RoReg SMC_ECC_PR6; /**< \brief (Smc Offset: 0x048) SMC ECC parity 6 Register */ - RoReg SMC_ECC_PR7; /**< \brief (Smc Offset: 0x04C) SMC ECC parity 7 Register */ - RoReg SMC_ECC_PR8; /**< \brief (Smc Offset: 0x050) SMC ECC parity 8 Register */ - RoReg SMC_ECC_PR9; /**< \brief (Smc Offset: 0x054) SMC ECC parity 9 Register */ - RoReg SMC_ECC_PR10; /**< \brief (Smc Offset: 0x058) SMC ECC parity 10 Register */ - RoReg SMC_ECC_PR11; /**< \brief (Smc Offset: 0x05C) SMC ECC parity 11 Register */ - RoReg SMC_ECC_PR12; /**< \brief (Smc Offset: 0x060) SMC ECC parity 12 Register */ - RoReg SMC_ECC_PR13; /**< \brief (Smc Offset: 0x064) SMC ECC parity 13 Register */ - RoReg SMC_ECC_PR14; /**< \brief (Smc Offset: 0x068) SMC ECC parity 14 Register */ - RoReg SMC_ECC_PR15; /**< \brief (Smc Offset: 0x06C) SMC ECC parity 15 Register */ - SmcCs_number SMC_CS_NUMBER[4]; /**< \brief (Smc Offset: 0x70) CS_number = 0 .. 3 */ - RwReg Reserved1[20]; - RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x110) SMC OCMS MODE Register */ - WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x114) SMC KEY1 Register */ - WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x118) SMC KEY2 Register */ - RwReg Reserved2[50]; - WoReg SMC_WPCR; /**< \brief (Smc Offset: 0x1E4) Write Protection Control Register */ - RoReg SMC_WPSR; /**< \brief (Smc Offset: 0x1E8) Write Protection Status Register */ -} Smc; -#endif /* __ASSEMBLY__ */ -/* -------- SMC_CFG : (SMC Offset: 0x000) SMC NFC Configuration Register -------- */ -#define SMC_CFG_PAGESIZE (0x3 << 0) /**< \brief (SMC_CFG) */ -#define SMC_CFG_WSPARE (0x1 << 8) /**< \brief (SMC_CFG) Write Spare Area */ -#define SMC_CFG_RSPARE (0x1 << 9) /**< \brief (SMC_CFG) Read Spare Area */ -#define SMC_CFG_EDGECTRL (0x1 << 12) /**< \brief (SMC_CFG) Rising/Falling Edge Detection Control */ -#define SMC_CFG_RBEDGE (0x1 << 13) /**< \brief (SMC_CFG) Ready/Busy Signal Edge Detection */ -#define SMC_CFG_DTOCYC (0xf << 16) /**< \brief (SMC_CFG) Data Timeout Cycle Number */ -#define SMC_CFG_DTOMUL (0x7 << 20) /**< \brief (SMC_CFG) Data Timeout Multiplier */ -/* -------- SMC_CTRL : (SMC Offset: 0x004) SMC NFC Control Register -------- */ -#define SMC_CTRL_NFCEN (0x1 << 0) /**< \brief (SMC_CTRL) NAND Flash Controller Enable */ -#define SMC_CTRL_NFCDIS (0x1 << 1) /**< \brief (SMC_CTRL) NAND Flash Controller Disable */ -/* -------- SMC_SR : (SMC Offset: 0x008) SMC NFC Status Register -------- */ -#define SMC_SR_SMCSTS (0x1 << 0) /**< \brief (SMC_SR) NAND Flash Controller status (this field cannot be reset) */ -#define SMC_SR_RB_RISE (0x1 << 4) /**< \brief (SMC_SR) Selected Ready Busy Rising Edge Detected */ -#define SMC_SR_RB_FALL (0x1 << 5) /**< \brief (SMC_SR) Selected Ready Busy Falling Edge Detected */ -#define SMC_SR_NFCBUSY (0x1 << 8) /**< \brief (SMC_SR) NFC Busy (this field cannot be reset) */ -#define SMC_SR_NFCWR (0x1 << 11) /**< \brief (SMC_SR) NFC Write/Read Operation (this field cannot be reset) */ -#define SMC_SR_NFCSID (0x7 << 12) /**< \brief (SMC_SR) NFC Chip Select ID (this field cannot be reset) */ -#define SMC_SR_XFRDONE (0x1 << 16) /**< \brief (SMC_SR) NFC Data Transfer Terminated */ -#define SMC_SR_CMDDONE (0x1 << 17) /**< \brief (SMC_SR) Command Done */ -#define SMC_SR_DTOE (0x1 << 20) /**< \brief (SMC_SR) Data Timeout Error */ -#define SMC_SR_UNDEF (0x1 << 21) /**< \brief (SMC_SR) Undefined Area Error */ -#define SMC_SR_AWB (0x1 << 22) /**< \brief (SMC_SR) Accessing While Busy */ -#define SMC_SR_NFCASE (0x1 << 23) /**< \brief (SMC_SR) NFC Access Size Error */ -#define SMC_SR_RB_EDGE0 (0x1 << 24) /**< \brief (SMC_SR) Ready/Busy Line 0 Edge Detected */ -/* -------- SMC_IER : (SMC Offset: 0x00C) SMC NFC Interrupt Enable Register -------- */ -#define SMC_IER_RB_RISE (0x1 << 4) /**< \brief (SMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */ -#define SMC_IER_RB_FALL (0x1 << 5) /**< \brief (SMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */ -#define SMC_IER_XFRDONE (0x1 << 16) /**< \brief (SMC_IER) Transfer Done Interrupt Enable */ -#define SMC_IER_CMDDONE (0x1 << 17) /**< \brief (SMC_IER) Command Done Interrupt Enable */ -#define SMC_IER_DTOE (0x1 << 20) /**< \brief (SMC_IER) Data Timeout Error Interrupt Enable */ -#define SMC_IER_UNDEF (0x1 << 21) /**< \brief (SMC_IER) Undefined Area Access Interrupt Enable */ -#define SMC_IER_AWB (0x1 << 22) /**< \brief (SMC_IER) Accessing While Busy Interrupt Enable */ -#define SMC_IER_NFCASE (0x1 << 23) /**< \brief (SMC_IER) NFC Access Size Error Interrupt Enable */ -#define SMC_IER_RB_EDGE0 (0x1 << 24) /**< \brief (SMC_IER) Ready/Busy Line 0 Interrupt Enable */ -/* -------- SMC_IDR : (SMC Offset: 0x010) SMC NFC Interrupt Disable Register -------- */ -#define SMC_IDR_RB_RISE (0x1 << 4) /**< \brief (SMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */ -#define SMC_IDR_RB_FALL (0x1 << 5) /**< \brief (SMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */ -#define SMC_IDR_XFRDONE (0x1 << 16) /**< \brief (SMC_IDR) Transfer Done Interrupt Disable */ -#define SMC_IDR_CMDDONE (0x1 << 17) /**< \brief (SMC_IDR) Command Done Interrupt Disable */ -#define SMC_IDR_DTOE (0x1 << 20) /**< \brief (SMC_IDR) Data Timeout Error Interrupt Disable */ -#define SMC_IDR_UNDEF (0x1 << 21) /**< \brief (SMC_IDR) Undefined Area Access Interrupt Disable */ -#define SMC_IDR_AWB (0x1 << 22) /**< \brief (SMC_IDR) Accessing While Busy Interrupt Disable */ -#define SMC_IDR_NFCASE (0x1 << 23) /**< \brief (SMC_IDR) NFC Access Size Error Interrupt Disable */ -#define SMC_IDR_RB_EDGE0 (0x1 << 24) /**< \brief (SMC_IDR) Ready/Busy Line 0 Interrupt Disable */ -/* -------- SMC_IMR : (SMC Offset: 0x014) SMC NFC Interrupt Mask Register -------- */ -#define SMC_IMR_RB_RISE (0x1 << 4) /**< \brief (SMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */ -#define SMC_IMR_RB_FALL (0x1 << 5) /**< \brief (SMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */ -#define SMC_IMR_XFRDONE (0x1 << 16) /**< \brief (SMC_IMR) Transfer Done Interrupt Mask */ -#define SMC_IMR_CMDDONE (0x1 << 17) /**< \brief (SMC_IMR) Command Done Interrupt Mask */ -#define SMC_IMR_DTOE (0x1 << 20) /**< \brief (SMC_IMR) Data Timeout Error Interrupt Mask */ -#define SMC_IMR_UNDEF (0x1 << 21) /**< \brief (SMC_IMR) Undefined Area Access Interrupt Mask5 */ -#define SMC_IMR_AWB (0x1 << 22) /**< \brief (SMC_IMR) Accessing While Busy Interrupt Mask */ -#define SMC_IMR_NFCASE (0x1 << 23) /**< \brief (SMC_IMR) NFC Access Size Error Interrupt Mask */ -#define SMC_IMR_RB_EDGE0 (0x1 << 24) /**< \brief (SMC_IMR) Ready/Busy Line 0 Interrupt Mask */ -/* -------- SMC_ADDR : (SMC Offset: 0x018) SMC NFC Address Cycle Zero Register -------- */ -#define SMC_ADDR_ADDR_CYCLE0 (0xff << 0) /**< \brief (SMC_ADDR) NAND Flash Array Address cycle 0 */ -/* -------- SMC_BANK : (SMC Offset: 0x01C) SMC Bank Address Register -------- */ -#define SMC_BANK_BANK (0x7 << 0) /**< \brief (SMC_BANK) Bank Identifier */ -/* -------- SMC_ECC_CTRL : (SMC Offset: 0x020) SMC ECC Control Register -------- */ -#define SMC_ECC_CTRL_RST (0x1 << 0) /**< \brief (SMC_ECC_CTRL) Reset ECC */ -#define SMC_ECC_CTRL_SWRST (0x1 << 1) /**< \brief (SMC_ECC_CTRL) Software Reset */ -/* -------- SMC_ECC_MD : (SMC Offset: 0x024) SMC ECC Mode Register -------- */ -#define SMC_ECC_MD_ECC_PAGESIZE (0x3 << 0) /**< \brief (SMC_ECC_MD) */ -#define SMC_ECC_MD_TYPCORREC (0x3 << 4) /**< \brief (SMC_ECC_MD) type of correction */ -/* -------- SMC_ECC_SR1 : (SMC Offset: 0x028) SMC ECC Status 1 Register -------- */ -#define SMC_ECC_SR1_RECERR0 (0x1 << 0) /**< \brief (SMC_ECC_SR1) Recoverable Error */ -#define SMC_ECC_SR1_ECCERR0 (0x3 << 1) /**< \brief (SMC_ECC_SR1) ECC Error */ -#define SMC_ECC_SR1_RECERR1 (0x1 << 4) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes */ -#define SMC_ECC_SR1_ECCERR1 (0x1 << 5) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */ -#define SMC_ECC_SR1_MULERR1 (0x1 << 6) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */ -#define SMC_ECC_SR1_RECERR2 (0x1 << 8) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */ -#define SMC_ECC_SR1_ECCERR2 (0x1 << 9) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */ -#define SMC_ECC_SR1_MULERR2 (0x1 << 10) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */ -#define SMC_ECC_SR1_RECERR3 (0x1 << 12) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */ -#define SMC_ECC_SR1_ECCERR3 (0x1 << 13) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */ -#define SMC_ECC_SR1_MULERR3 (0x1 << 14) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */ -#define SMC_ECC_SR1_RECERR4 (0x1 << 16) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */ -#define SMC_ECC_SR1_ECCERR4 (0x3 << 17) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */ -#define SMC_ECC_SR1_RECERR5 (0x1 << 20) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */ -#define SMC_ECC_SR1_ECCERR5 (0x3 << 21) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */ -#define SMC_ECC_SR1_RECERR6 (0x1 << 24) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */ -#define SMC_ECC_SR1_ECCERR6 (0x3 << 25) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */ -#define SMC_ECC_SR1_RECERR7 (0x1 << 28) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */ -#define SMC_ECC_SR1_ECCERR7 (0x3 << 29) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */ -/* -------- SMC_ECC_PR0 : (SMC Offset: 0x02C) SMC ECC Parity 0 Register -------- */ -#define SMC_ECC_PR0_BITADDR (0xf << 0) /**< \brief (SMC_ECC_PR0) Bit Address */ -#define SMC_ECC_PR0_WORDADDR (0xfff << 4) /**< \brief (SMC_ECC_PR0) Word Address */ -/* -------- SMC_ECC_PR1 : (SMC Offset: 0x030) SMC ECC parity 1 Register -------- */ -#define SMC_ECC_PR1_NPARITY (0xffff << 0) /**< \brief (SMC_ECC_PR1) */ -/* -------- SMC_ECC_SR2 : (SMC Offset: 0x034) SMC ECC status 2 Register -------- */ -#define SMC_ECC_SR2_RECERR8 (0x1 << 0) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2048th and the 2303rd bytes */ -#define SMC_ECC_SR2_ECCERR8 (0x3 << 1) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2048th and the 2303rd bytes */ -#define SMC_ECC_SR2_RECERR9 (0x1 << 4) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2304th and the 2559th bytes */ -#define SMC_ECC_SR2_ECCERR9 (0x1 << 5) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2304th and the 2559th bytes */ -#define SMC_ECC_SR2_MULERR9 (0x1 << 6) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2304th and the 2559th bytes */ -#define SMC_ECC_SR2_RECERR10 (0x1 << 8) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2560th and the 2815th bytes */ -#define SMC_ECC_SR2_ECCERR10 (0x1 << 9) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2560th and the 2815th bytes */ -#define SMC_ECC_SR2_MULERR10 (0x1 << 10) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2560th and the 2815th bytes */ -#define SMC_ECC_SR2_RECERR11 (0x1 << 12) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2816th and the 3071st bytes */ -#define SMC_ECC_SR2_ECCERR11 (0x1 << 13) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2816th and the 3071st bytes */ -#define SMC_ECC_SR2_MULERR11 (0x1 << 14) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2816th and the 3071st bytes */ -#define SMC_ECC_SR2_RECERR12 (0x1 << 16) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3072nd and the 3327th bytes */ -#define SMC_ECC_SR2_ECCERR12 (0x3 << 17) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3072nd and the 3327th bytes */ -#define SMC_ECC_SR2_RECERR13 (0x1 << 20) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3328th and the 3583rd bytes */ -#define SMC_ECC_SR2_ECCERR13 (0x3 << 21) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3328th and the 3583rd bytes */ -#define SMC_ECC_SR2_RECERR14 (0x1 << 24) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3584th and the 3839th bytes */ -#define SMC_ECC_SR2_ECCERR14 (0x3 << 25) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3584th and the 3839th bytes */ -#define SMC_ECC_SR2_RECERR15 (0x1 << 28) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3840th and the 4095th bytes */ -#define SMC_ECC_SR2_ECCERR15 (0x3 << 29) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3840th and the 4095th bytes */ -/* -------- SMC_ECC_PR2 : (SMC Offset: 0x038) SMC ECC parity 2 Register -------- */ -/* -------- SMC_ECC_PR3 : (SMC Offset: 0x03C) SMC ECC parity 3 Register -------- */ -/* -------- SMC_ECC_PR4 : (SMC Offset: 0x040) SMC ECC parity 4 Register -------- */ -/* -------- SMC_ECC_PR5 : (SMC Offset: 0x044) SMC ECC parity 5 Register -------- */ -/* -------- SMC_ECC_PR6 : (SMC Offset: 0x048) SMC ECC parity 6 Register -------- */ -/* -------- SMC_ECC_PR7 : (SMC Offset: 0x04C) SMC ECC parity 7 Register -------- */ -/* -------- SMC_ECC_PR8 : (SMC Offset: 0x050) SMC ECC parity 8 Register -------- */ -/* -------- SMC_ECC_PR9 : (SMC Offset: 0x054) SMC ECC parity 9 Register -------- */ -/* -------- SMC_ECC_PR10 : (SMC Offset: 0x058) SMC ECC parity 10 Register -------- */ -/* -------- SMC_ECC_PR11 : (SMC Offset: 0x05C) SMC ECC parity 11 Register -------- */ -/* -------- SMC_ECC_PR12 : (SMC Offset: 0x060) SMC ECC parity 12 Register -------- */ -/* -------- SMC_ECC_PR13 : (SMC Offset: 0x064) SMC ECC parity 13 Register -------- */ -/* -------- SMC_ECC_PR14 : (SMC Offset: 0x068) SMC ECC parity 14 Register -------- */ -/* -------- SMC_ECC_PR15 : (SMC Offset: 0x06C) SMC ECC parity 15 Register -------- */ -/* -------- SMC_SETUP0 : (SMC Offset: 0x70) SMC SETUP Register (CS_number = 0) -------- */ -#define SMC_SETUP0_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP0) NWE Setup length */ -#define SMC_SETUP0_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP0) NCS Setup length in Write access */ -#define SMC_SETUP0_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP0) NRD Setup length */ -#define SMC_SETUP0_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP0) NCS Setup length in Read access */ -/* -------- SMC_PULSE0 : (SMC Offset: 0x74) SMC PULSE Register (CS_number = 0) -------- */ -#define SMC_PULSE0_NWE_PULSE (0x3f << 0) /**< \brief (SMC_PULSE0) NWE Pulse Length */ -#define SMC_PULSE0_NCS_WR_PULSE (0x3f << 8) /**< \brief (SMC_PULSE0) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE0_NRD_PULSE (0x3f << 16) /**< \brief (SMC_PULSE0) NRD Pulse Length */ -#define SMC_PULSE0_NCS_RD_PULSE (0x3f << 24) /**< \brief (SMC_PULSE0) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE0 : (SMC Offset: 0x78) SMC CYCLE Register (CS_number = 0) -------- */ -#define SMC_CYCLE0_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE0) Total Write Cycle Length */ -#define SMC_CYCLE0_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE0) Total Read Cycle Length */ -/* -------- SMC_TIMINGS0 : (SMC Offset: 0x7C) SMC TIMINGS Register (CS_number = 0) -------- */ -#define SMC_TIMINGS0_TCLR (0xf << 0) /**< \brief (SMC_TIMINGS0) CLE to REN Low Delay */ -#define SMC_TIMINGS0_TADL (0xf << 4) /**< \brief (SMC_TIMINGS0) ALE to Data Start */ -#define SMC_TIMINGS0_TAR (0xf << 8) /**< \brief (SMC_TIMINGS0) ALE to REN Low Delay */ -#define SMC_TIMINGS0_OCMS (0x1 << 12) /**< \brief (SMC_TIMINGS0) Off Chip Memory Scrambling Enable */ -#define SMC_TIMINGS0_TRR (0xf << 16) /**< \brief (SMC_TIMINGS0) Ready to REN Low Delay */ -#define SMC_TIMINGS0_TWB (0xf << 24) /**< \brief (SMC_TIMINGS0) WEN High to REN to Busy */ -#define SMC_TIMINGS0_RBNSEL (0x7 << 28) /**< \brief (SMC_TIMINGS0) Ready/Busy Line Selection */ -#define SMC_TIMINGS0_NFSEL (0x1 << 31) /**< \brief (SMC_TIMINGS0) NAND Flash Selection */ -/* -------- SMC_MODE0 : (SMC Offset: 0x80) SMC MODE Register (CS_number = 0) -------- */ -#define SMC_MODE0_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE0) NWAIT Mode */ -#define SMC_MODE0_BAT (0x1 << 8) /**< \brief (SMC_MODE0) Byte Access Type */ -#define SMC_MODE0_DBW (0x1 << 12) /**< \brief (SMC_MODE0) Data Bus Width */ -#define SMC_MODE0_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE0) Data Float Time */ -#define SMC_MODE0_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE0) TDF Optimization */ -/* -------- SMC_SETUP1 : (SMC Offset: 0x84) SMC SETUP Register (CS_number = 1) -------- */ -#define SMC_SETUP1_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP1) NWE Setup length */ -#define SMC_SETUP1_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP1) NCS Setup length in Write access */ -#define SMC_SETUP1_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP1) NRD Setup length */ -#define SMC_SETUP1_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP1) NCS Setup length in Read access */ -/* -------- SMC_PULSE1 : (SMC Offset: 0x88) SMC PULSE Register (CS_number = 1) -------- */ -#define SMC_PULSE1_NWE_PULSE (0x3f << 0) /**< \brief (SMC_PULSE1) NWE Pulse Length */ -#define SMC_PULSE1_NCS_WR_PULSE (0x3f << 8) /**< \brief (SMC_PULSE1) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE1_NRD_PULSE (0x3f << 16) /**< \brief (SMC_PULSE1) NRD Pulse Length */ -#define SMC_PULSE1_NCS_RD_PULSE (0x3f << 24) /**< \brief (SMC_PULSE1) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE1 : (SMC Offset: 0x8C) SMC CYCLE Register (CS_number = 1) -------- */ -#define SMC_CYCLE1_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE1) Total Write Cycle Length */ -#define SMC_CYCLE1_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE1) Total Read Cycle Length */ -/* -------- SMC_TIMINGS1 : (SMC Offset: 0x90) SMC TIMINGS Register (CS_number = 1) -------- */ -#define SMC_TIMINGS1_TCLR (0xf << 0) /**< \brief (SMC_TIMINGS1) CLE to REN Low Delay */ -#define SMC_TIMINGS1_TADL (0xf << 4) /**< \brief (SMC_TIMINGS1) ALE to Data Start */ -#define SMC_TIMINGS1_TAR (0xf << 8) /**< \brief (SMC_TIMINGS1) ALE to REN Low Delay */ -#define SMC_TIMINGS1_OCMS (0x1 << 12) /**< \brief (SMC_TIMINGS1) Off Chip Memory Scrambling Enable */ -#define SMC_TIMINGS1_TRR (0xf << 16) /**< \brief (SMC_TIMINGS1) Ready to REN Low Delay */ -#define SMC_TIMINGS1_TWB (0xf << 24) /**< \brief (SMC_TIMINGS1) WEN High to REN to Busy */ -#define SMC_TIMINGS1_RBNSEL (0x7 << 28) /**< \brief (SMC_TIMINGS1) Ready/Busy Line Selection */ -#define SMC_TIMINGS1_NFSEL (0x1 << 31) /**< \brief (SMC_TIMINGS1) NAND Flash Selection */ -/* -------- SMC_MODE1 : (SMC Offset: 0x94) SMC MODE Register (CS_number = 1) -------- */ -#define SMC_MODE1_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE1) NWAIT Mode */ -#define SMC_MODE1_BAT (0x1 << 8) /**< \brief (SMC_MODE1) Byte Access Type */ -#define SMC_MODE1_DBW (0x1 << 12) /**< \brief (SMC_MODE1) Data Bus Width */ -#define SMC_MODE1_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE1) Data Float Time */ -#define SMC_MODE1_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE1) TDF Optimization */ -/* -------- SMC_SETUP2 : (SMC Offset: 0x98) SMC SETUP Register (CS_number = 2) -------- */ -#define SMC_SETUP2_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP2) NWE Setup length */ -#define SMC_SETUP2_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP2) NCS Setup length in Write access */ -#define SMC_SETUP2_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP2) NRD Setup length */ -#define SMC_SETUP2_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP2) NCS Setup length in Read access */ -/* -------- SMC_PULSE2 : (SMC Offset: 0x9C) SMC PULSE Register (CS_number = 2) -------- */ -#define SMC_PULSE2_NWE_PULSE (0x3f << 0) /**< \brief (SMC_PULSE2) NWE Pulse Length */ -#define SMC_PULSE2_NCS_WR_PULSE (0x3f << 8) /**< \brief (SMC_PULSE2) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE2_NRD_PULSE (0x3f << 16) /**< \brief (SMC_PULSE2) NRD Pulse Length */ -#define SMC_PULSE2_NCS_RD_PULSE (0x3f << 24) /**< \brief (SMC_PULSE2) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE2 : (SMC Offset: 0xA0) SMC CYCLE Register (CS_number = 2) -------- */ -#define SMC_CYCLE2_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE2) Total Write Cycle Length */ -#define SMC_CYCLE2_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE2) Total Read Cycle Length */ -/* -------- SMC_TIMINGS2 : (SMC Offset: 0xA4) SMC TIMINGS Register (CS_number = 2) -------- */ -#define SMC_TIMINGS2_TCLR (0xf << 0) /**< \brief (SMC_TIMINGS2) CLE to REN Low Delay */ -#define SMC_TIMINGS2_TADL (0xf << 4) /**< \brief (SMC_TIMINGS2) ALE to Data Start */ -#define SMC_TIMINGS2_TAR (0xf << 8) /**< \brief (SMC_TIMINGS2) ALE to REN Low Delay */ -#define SMC_TIMINGS2_OCMS (0x1 << 12) /**< \brief (SMC_TIMINGS2) Off Chip Memory Scrambling Enable */ -#define SMC_TIMINGS2_TRR (0xf << 16) /**< \brief (SMC_TIMINGS2) Ready to REN Low Delay */ -#define SMC_TIMINGS2_TWB (0xf << 24) /**< \brief (SMC_TIMINGS2) WEN High to REN to Busy */ -#define SMC_TIMINGS2_RBNSEL (0x7 << 28) /**< \brief (SMC_TIMINGS2) Ready/Busy Line Selection */ -#define SMC_TIMINGS2_NFSEL (0x1 << 31) /**< \brief (SMC_TIMINGS2) NAND Flash Selection */ -/* -------- SMC_MODE2 : (SMC Offset: 0xA8) SMC MODE Register (CS_number = 2) -------- */ -#define SMC_MODE2_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE2) NWAIT Mode */ -#define SMC_MODE2_BAT (0x1 << 8) /**< \brief (SMC_MODE2) Byte Access Type */ -#define SMC_MODE2_DBW (0x1 << 12) /**< \brief (SMC_MODE2) Data Bus Width */ -#define SMC_MODE2_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE2) Data Float Time */ -#define SMC_MODE2_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE2) TDF Optimization */ -/* -------- SMC_SETUP3 : (SMC Offset: 0xAC) SMC SETUP Register (CS_number = 3) -------- */ -#define SMC_SETUP3_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP3) NWE Setup length */ -#define SMC_SETUP3_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP3) NCS Setup length in Write access */ -#define SMC_SETUP3_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP3) NRD Setup length */ -#define SMC_SETUP3_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP3) NCS Setup length in Read access */ -/* -------- SMC_PULSE3 : (SMC Offset: 0xB0) SMC PULSE Register (CS_number = 3) -------- */ -#define SMC_PULSE3_NWE_PULSE (0x3f << 0) /**< \brief (SMC_PULSE3) NWE Pulse Length */ -#define SMC_PULSE3_NCS_WR_PULSE (0x3f << 8) /**< \brief (SMC_PULSE3) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE3_NRD_PULSE (0x3f << 16) /**< \brief (SMC_PULSE3) NRD Pulse Length */ -#define SMC_PULSE3_NCS_RD_PULSE (0x3f << 24) /**< \brief (SMC_PULSE3) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE3 : (SMC Offset: 0xB4) SMC CYCLE Register (CS_number = 3) -------- */ -#define SMC_CYCLE3_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE3) Total Write Cycle Length */ -#define SMC_CYCLE3_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE3) Total Read Cycle Length */ -/* -------- SMC_TIMINGS3 : (SMC Offset: 0xB8) SMC TIMINGS Register (CS_number = 3) -------- */ -#define SMC_TIMINGS3_TCLR (0xf << 0) /**< \brief (SMC_TIMINGS3) CLE to REN Low Delay */ -#define SMC_TIMINGS3_TADL (0xf << 4) /**< \brief (SMC_TIMINGS3) ALE to Data Start */ -#define SMC_TIMINGS3_TAR (0xf << 8) /**< \brief (SMC_TIMINGS3) ALE to REN Low Delay */ -#define SMC_TIMINGS3_OCMS (0x1 << 12) /**< \brief (SMC_TIMINGS3) Off Chip Memory Scrambling Enable */ -#define SMC_TIMINGS3_TRR (0xf << 16) /**< \brief (SMC_TIMINGS3) Ready to REN Low Delay */ -#define SMC_TIMINGS3_TWB (0xf << 24) /**< \brief (SMC_TIMINGS3) WEN High to REN to Busy */ -#define SMC_TIMINGS3_RBNSEL (0x7 << 28) /**< \brief (SMC_TIMINGS3) Ready/Busy Line Selection */ -#define SMC_TIMINGS3_NFSEL (0x1 << 31) /**< \brief (SMC_TIMINGS3) NAND Flash Selection */ -/* -------- SMC_MODE3 : (SMC Offset: 0xBC) SMC MODE Register (CS_number = 3) -------- */ -#define SMC_MODE3_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE3) NWAIT Mode */ -#define SMC_MODE3_BAT (0x1 << 8) /**< \brief (SMC_MODE3) Byte Access Type */ -#define SMC_MODE3_DBW (0x1 << 12) /**< \brief (SMC_MODE3) Data Bus Width */ -#define SMC_MODE3_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE3) Data Float Time */ -#define SMC_MODE3_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE3) TDF Optimization */ -/* -------- SMC_OCMS : (SMC Offset: 0x110) SMC OCMS MODE Register -------- */ -#define SMC_OCMS_SMSE (0x1 << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ -#define SMC_OCMS_SRSE (0x1 << 1) /**< \brief (SMC_OCMS) SRAM Scrambling Enable */ -/* -------- SMC_KEY1 : (SMC Offset: 0x114) SMC KEY1 Register -------- */ -#define SMC_KEY1_KEY1 (0xffffffff << 0) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ -/* -------- SMC_KEY2 : (SMC Offset: 0x118) SMC KEY2 Register -------- */ -#define SMC_KEY2_KEY2 (0xffffffff << 0) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ -/* -------- SMC_WPCR : (SMC Offset: 0x1E4) Write Protection Control Register -------- */ -#define SMC_WPCR_WP_EN (0x1 << 0) /**< \brief (SMC_WPCR) */ -#define SMC_WPCR_WP_KEY (0xffffff << 8) /**< \brief (SMC_WPCR) Write Protection KEY password */ -/* -------- SMC_WPSR : (SMC Offset: 0x1E8) Write Protection Status Register -------- */ -#define SMC_WPSR_WP_VS (0xf << 0) /**< \brief (SMC_WPSR) Write Protection Violation Status */ -#define SMC_WPSR_WP_VSRC (0xffff << 8) /**< \brief (SMC_WPSR) Write Protection Violation SouRCe */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_SPI Serial Peripheral Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Spi hardware registers */ -typedef struct { - WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ - RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ - RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ - WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ - RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ - WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ - WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ - RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ - RwReg Reserved1[4]; - RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ - RwReg Reserved2[41]; - RwReg SPI_WPCR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ - RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ -} Spi; -#endif /* __ASSEMBLY__ */ -/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ -#define SPI_CR_SPIEN (0x1 << 0) /**< \brief (SPI_CR) SPI Enable */ -#define SPI_CR_SPIDIS (0x1 << 1) /**< \brief (SPI_CR) SPI Disable */ -#define SPI_CR_SWRST (0x1 << 7) /**< \brief (SPI_CR) SPI Software Reset */ -#define SPI_CR_LASTXFER (0x1 << 24) /**< \brief (SPI_CR) Last Transfer */ -/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ -#define SPI_MR_MSTR (0x1 << 0) /**< \brief (SPI_MR) Master/Slave Mode */ -#define SPI_MR_PS (0x1 << 1) /**< \brief (SPI_MR) Peripheral Select */ -#define SPI_MR_PS_FIXED (0x0 << 1) /**< \brief (SPI_MR) Fixed Peripheral Select. */ -#define SPI_MR_PS_VARIABLE (0x1 << 1) /**< \brief (SPI_MR) Variable Peripheral Select. */ -#define SPI_MR_PCSDEC (0x1 << 2) /**< \brief (SPI_MR) Chip Select Decode */ -#define SPI_MR_MODFDIS (0x1 << 4) /**< \brief (SPI_MR) Mode Fault Detection */ -#define SPI_MR_WDRBT (0x1 << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ -#define SPI_MR_LLB (0x1 << 7) /**< \brief (SPI_MR) Local Loopback Enable */ -#define SPI_MR_PCS (0xf << 16) /**< \brief (SPI_MR) Peripheral Chip Select */ -#define SPI_MR_DLYBCS (0xff << 24) /**< \brief (SPI_MR) Delay Between Chip Selects */ -/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ -#define SPI_RDR_RD (0xffff << 0) /**< \brief (SPI_RDR) Receive Data */ -#define SPI_RDR_PCS (0xf << 16) /**< \brief (SPI_RDR) Peripheral Chip Select */ -/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ -#define SPI_TDR_TD (0xffff << 0) /**< \brief (SPI_TDR) Transmit Data */ -#define SPI_TDR_PCS (0xf << 16) /**< \brief (SPI_TDR) Peripheral Chip Select */ -#define SPI_TDR_LASTXFER (0x1 << 24) /**< \brief (SPI_TDR) Last Transfer */ -/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ -#define SPI_SR_RDRF (0x1 << 0) /**< \brief (SPI_SR) Receive Data Register Full */ -#define SPI_SR_TDRE (0x1 << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ -#define SPI_SR_MODF (0x1 << 2) /**< \brief (SPI_SR) Mode Fault Error */ -#define SPI_SR_OVRES (0x1 << 3) /**< \brief (SPI_SR) Overrun Error Status */ -#define SPI_SR_RXBUFF (0x1 << 6) /**< \brief (SPI_SR) */ -#define SPI_SR_NSSR (0x1 << 8) /**< \brief (SPI_SR) NSS Rising */ -#define SPI_SR_TXEMPTY (0x1 << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ -#define SPI_SR_UNDES (0x1 << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ -#define SPI_SR_SPIENS (0x1 << 16) /**< \brief (SPI_SR) SPI Enable Status */ -/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ -#define SPI_IER_RDRF (0x1 << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ -#define SPI_IER_TDRE (0x1 << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ -#define SPI_IER_MODF (0x1 << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ -#define SPI_IER_OVRES (0x1 << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ -#define SPI_IER_RXBUFF (0x1 << 6) /**< \brief (SPI_IER) */ -#define SPI_IER_NSSR (0x1 << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ -#define SPI_IER_TXEMPTY (0x1 << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ -#define SPI_IER_UNDES (0x1 << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ -/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ -#define SPI_IDR_RDRF (0x1 << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ -#define SPI_IDR_TDRE (0x1 << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ -#define SPI_IDR_MODF (0x1 << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ -#define SPI_IDR_OVRES (0x1 << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ -#define SPI_IDR_RXBUFF (0x1 << 6) /**< \brief (SPI_IDR) */ -#define SPI_IDR_NSSR (0x1 << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ -#define SPI_IDR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ -#define SPI_IDR_UNDES (0x1 << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ -/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ -#define SPI_IMR_RDRF (0x1 << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ -#define SPI_IMR_TDRE (0x1 << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ -#define SPI_IMR_MODF (0x1 << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ -#define SPI_IMR_OVRES (0x1 << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ -#define SPI_IMR_RXBUFF (0x1 << 6) /**< \brief (SPI_IMR) */ -#define SPI_IMR_NSSR (0x1 << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ -#define SPI_IMR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ -#define SPI_IMR_UNDES (0x1 << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ -/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ -#define SPI_CSR_CPOL (0x1 << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ -#define SPI_CSR_NCPHA (0x1 << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ -#define SPI_CSR_CSNAAT (0x1 << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_CSAAT (0x1 << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_BITS (0xf << 4) /**< \brief (SPI_CSR[4]) Bits Per Transfer (See the (Note:) below the register table; Section 9.9 "SPI Chip Select Register" on page 37.) */ -#define SPI_CSR_BITS_8 (0x0 << 4) /**< \brief (SPI_CSR[4]) 8 */ -#define SPI_CSR_BITS_9 (0x1 << 4) /**< \brief (SPI_CSR[4]) 9 */ -#define SPI_CSR_BITS_10 (0x2 << 4) /**< \brief (SPI_CSR[4]) 10 */ -#define SPI_CSR_BITS_11 (0x3 << 4) /**< \brief (SPI_CSR[4]) 11 */ -#define SPI_CSR_BITS_12 (0x4 << 4) /**< \brief (SPI_CSR[4]) 12 */ -#define SPI_CSR_BITS_13 (0x5 << 4) /**< \brief (SPI_CSR[4]) 13 */ -#define SPI_CSR_BITS_14 (0x6 << 4) /**< \brief (SPI_CSR[4]) 14 */ -#define SPI_CSR_BITS_15 (0x7 << 4) /**< \brief (SPI_CSR[4]) 15 */ -#define SPI_CSR_BITS_16 (0x8 << 4) /**< \brief (SPI_CSR[4]) 16 */ -#define SPI_CSR_SCBR (0xff << 8) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ -#define SPI_CSR_DLYBS (0xff << 16) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ -#define SPI_CSR_DLYBCT (0xff << 24) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ -/* -------- SPI_WPCR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ -#define SPI_WPCR_SPIWPEN (0x1 << 0) /**< \brief (SPI_WPCR) SPI Write Protection Enable */ -#define SPI_WPCR_SPIWPKEY (0xffffff << 8) /**< \brief (SPI_WPCR) SPI Write Protection Key Password */ -/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ -#define SPI_WPSR_SPIWPVS (0x7 << 0) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */ -#define SPI_WPSR_SPIWPVSRC (0xff << 8) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_SSC Synchronous Serial Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Ssc hardware registers */ -typedef struct { - WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ - RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ - RwReg Reserved1[2]; - RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ - RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ - RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ - RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ - RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ - WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ - RwReg Reserved2[2]; - RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ - RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ - RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ - RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ - RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ - WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ - WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ - RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ - RwReg Reserved3[37]; - RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */ - RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */ -} Ssc; -#endif /* __ASSEMBLY__ */ -/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ -#define SSC_CR_RXEN (0x1 << 0) /**< \brief (SSC_CR) Receive Enable */ -#define SSC_CR_RXDIS (0x1 << 1) /**< \brief (SSC_CR) Receive Disable */ -#define SSC_CR_TXEN (0x1 << 8) /**< \brief (SSC_CR) Transmit Enable */ -#define SSC_CR_TXDIS (0x1 << 9) /**< \brief (SSC_CR) Transmit Disable */ -#define SSC_CR_SWRST (0x1 << 15) /**< \brief (SSC_CR) Software Reset */ -/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ -#define SSC_CMR_DIV (0xfff << 0) /**< \brief (SSC_CMR) Clock Divider */ -/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ -#define SSC_RCMR_CKS (0x3 << 0) /**< \brief (SSC_RCMR) Receive Clock Selection */ -#define SSC_RCMR_CKS_DIV (0x0 << 0) /**< \brief (SSC_RCMR) Divided Clock */ -#define SSC_RCMR_CKS_TK (0x1 << 0) /**< \brief (SSC_RCMR) TK Clock signal */ -#define SSC_RCMR_CKS_RK (0x2 << 0) /**< \brief (SSC_RCMR) RK pin */ -#define SSC_RCMR_CKO (0x7 << 2) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ -#define SSC_RCMR_CKI (0x1 << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ -#define SSC_RCMR_CKG (0x3 << 6) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ -#define SSC_RCMR_CKG_NONE (0x0 << 6) /**< \brief (SSC_RCMR) None, continuous clock */ -#define SSC_RCMR_CKG_LOW (0x1 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ -#define SSC_RCMR_CKG_HIGH (0x2 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ -#define SSC_RCMR_START (0xf << 8) /**< \brief (SSC_RCMR) Receive Start Selection */ -#define SSC_RCMR_STOP (0x1 << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ -#define SSC_RCMR_STTDLY (0xff << 16) /**< \brief (SSC_RCMR) Receive Start Delay */ -#define SSC_RCMR_PERIOD (0xff << 24) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ -/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ -#define SSC_RFMR_DATLEN (0x1f << 0) /**< \brief (SSC_RFMR) Data Length */ -#define SSC_RFMR_LOOP (0x1 << 5) /**< \brief (SSC_RFMR) Loop Mode */ -#define SSC_RFMR_MSBF (0x1 << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ -#define SSC_RFMR_DATNB (0xf << 8) /**< \brief (SSC_RFMR) Data Number per Frame */ -#define SSC_RFMR_FSLEN (0xf << 16) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ -#define SSC_RFMR_FSOS (0x7 << 20) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ -#define SSC_RFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ -#define SSC_RFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_RFMR) FSLEN Field Extension */ -/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ -#define SSC_TCMR_CKS (0x3 << 0) /**< \brief (SSC_TCMR) Transmit Clock Selection */ -#define SSC_TCMR_CKO (0x7 << 2) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ -#define SSC_TCMR_CKI (0x1 << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ -#define SSC_TCMR_CKG (0x3 << 6) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ -#define SSC_TCMR_START (0xf << 8) /**< \brief (SSC_TCMR) Transmit Start Selection */ -#define SSC_TCMR_STTDLY (0xff << 16) /**< \brief (SSC_TCMR) Transmit Start Delay */ -#define SSC_TCMR_PERIOD (0xff << 24) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ -/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ -#define SSC_TFMR_DATLEN (0x1f << 0) /**< \brief (SSC_TFMR) Data Length */ -#define SSC_TFMR_DATDEF (0x1 << 5) /**< \brief (SSC_TFMR) Data Default Value */ -#define SSC_TFMR_MSBF (0x1 << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ -#define SSC_TFMR_DATNB (0xf << 8) /**< \brief (SSC_TFMR) Data Number per frame */ -#define SSC_TFMR_FSLEN (0xf << 16) /**< \brief (SSC_TFMR) Transmit Frame Syn Length */ -#define SSC_TFMR_FSOS (0x7 << 20) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ -#define SSC_TFMR_FSDEN (0x1 << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ -#define SSC_TFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ -#define SSC_TFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_TFMR) FSLEN Field Extension */ -/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ -#define SSC_RHR_RDAT (0xffffffff << 0) /**< \brief (SSC_RHR) Receive Data */ -/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ -#define SSC_THR_TDAT (0xffffffff << 0) /**< \brief (SSC_THR) Transmit Data */ -/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ -#define SSC_RSHR_RSDAT (0xffff << 0) /**< \brief (SSC_RSHR) Receive Synchronization Data */ -/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ -#define SSC_TSHR_TSDAT (0xffff << 0) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ -/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ -#define SSC_RC0R_CP0 (0xffff << 0) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ -/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ -#define SSC_RC1R_CP1 (0xffff << 0) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ -/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ -#define SSC_SR_TXRDY (0x1 << 0) /**< \brief (SSC_SR) Transmit Ready */ -#define SSC_SR_TXEMPTY (0x1 << 1) /**< \brief (SSC_SR) Transmit Empty */ -#define SSC_SR_ENDTX (0x1 << 2) /**< \brief (SSC_SR) End of Transmission */ -#define SSC_SR_TXBUFE (0x1 << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */ -#define SSC_SR_RXRDY (0x1 << 4) /**< \brief (SSC_SR) Receive Ready */ -#define SSC_SR_OVRUN (0x1 << 5) /**< \brief (SSC_SR) Receive Overrun */ -#define SSC_SR_ENDRX (0x1 << 6) /**< \brief (SSC_SR) End of Reception */ -#define SSC_SR_RXBUFF (0x1 << 7) /**< \brief (SSC_SR) Receive Buffer Full */ -#define SSC_SR_CP0 (0x1 << 8) /**< \brief (SSC_SR) Compare 0 */ -#define SSC_SR_CP1 (0x1 << 9) /**< \brief (SSC_SR) Compare 1 */ -#define SSC_SR_TXSYN (0x1 << 10) /**< \brief (SSC_SR) Transmit Sync */ -#define SSC_SR_RXSYN (0x1 << 11) /**< \brief (SSC_SR) Receive Sync */ -#define SSC_SR_TXEN (0x1 << 16) /**< \brief (SSC_SR) Transmit Enable */ -#define SSC_SR_RXEN (0x1 << 17) /**< \brief (SSC_SR) Receive Enable */ -/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ -#define SSC_IER_TXRDY (0x1 << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ -#define SSC_IER_TXEMPTY (0x1 << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ -#define SSC_IER_ENDTX (0x1 << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */ -#define SSC_IER_TXBUFE (0x1 << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */ -#define SSC_IER_RXRDY (0x1 << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ -#define SSC_IER_OVRUN (0x1 << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ -#define SSC_IER_ENDRX (0x1 << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */ -#define SSC_IER_RXBUFF (0x1 << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */ -#define SSC_IER_CP0 (0x1 << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ -#define SSC_IER_CP1 (0x1 << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ -#define SSC_IER_TXSYN (0x1 << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ -#define SSC_IER_RXSYN (0x1 << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ -/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ -#define SSC_IDR_TXRDY (0x1 << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ -#define SSC_IDR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ -#define SSC_IDR_ENDTX (0x1 << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */ -#define SSC_IDR_TXBUFE (0x1 << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SSC_IDR_RXRDY (0x1 << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ -#define SSC_IDR_OVRUN (0x1 << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ -#define SSC_IDR_ENDRX (0x1 << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */ -#define SSC_IDR_RXBUFF (0x1 << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */ -#define SSC_IDR_CP0 (0x1 << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ -#define SSC_IDR_CP1 (0x1 << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ -#define SSC_IDR_TXSYN (0x1 << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ -#define SSC_IDR_RXSYN (0x1 << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ -/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ -#define SSC_IMR_TXRDY (0x1 << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ -#define SSC_IMR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ -#define SSC_IMR_ENDTX (0x1 << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */ -#define SSC_IMR_TXBUFE (0x1 << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SSC_IMR_RXRDY (0x1 << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ -#define SSC_IMR_OVRUN (0x1 << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ -#define SSC_IMR_ENDRX (0x1 << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */ -#define SSC_IMR_RXBUFF (0x1 << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */ -#define SSC_IMR_CP0 (0x1 << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ -#define SSC_IMR_CP1 (0x1 << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ -#define SSC_IMR_TXSYN (0x1 << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ -#define SSC_IMR_RXSYN (0x1 << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ -/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */ -#define SSC_WPMR_WPEN (0x1 << 0) /**< \brief (SSC_WPMR) Write Protect Enable */ -#define SSC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SSC_WPMR) Write Protect KEY */ -/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */ -#define SSC_WPSR_WPVS (0x1 << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */ -#define SSC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SSC_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Supply Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_SUPC Supply Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Supc hardware registers */ -typedef struct { - WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ - RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ - RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ - RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */ - RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */ - RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ -} Supc; -#endif /* __ASSEMBLY__ */ -/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ -#define SUPC_CR_VROFF (0x1 << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ -#define SUPC_CR_VROFF_NO_EFFECT (0x0 << 2) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_VROFF_STOP_VREG (0x1 << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */ -#define SUPC_CR_XTALSEL (0x1 << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ -#define SUPC_CR_XTALSEL_NO_EFFECT (0x0 << 3) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1 << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ -#define SUPC_CR_KEY (0xff << 24) /**< \brief (SUPC_CR) Password */ -/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ -#define SUPC_SMMR_SMTH (0xf << 0) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ -#define SUPC_SMMR_SMTH_1_9V (0x0 << 0) /**< \brief (SUPC_SMMR) 1.9 V */ -#define SUPC_SMMR_SMTH_2_0V (0x1 << 0) /**< \brief (SUPC_SMMR) 2.0 V */ -#define SUPC_SMMR_SMTH_2_1V (0x2 << 0) /**< \brief (SUPC_SMMR) 2.1 V */ -#define SUPC_SMMR_SMTH_2_2V (0x3 << 0) /**< \brief (SUPC_SMMR) 2.2 V */ -#define SUPC_SMMR_SMTH_2_3V (0x4 << 0) /**< \brief (SUPC_SMMR) 2.3 V */ -#define SUPC_SMMR_SMTH_2_4V (0x5 << 0) /**< \brief (SUPC_SMMR) 2.4 V */ -#define SUPC_SMMR_SMTH_2_5V (0x6 << 0) /**< \brief (SUPC_SMMR) 2.5 V */ -#define SUPC_SMMR_SMTH_2_6V (0x7 << 0) /**< \brief (SUPC_SMMR) 2.6 V */ -#define SUPC_SMMR_SMTH_2_7V (0x8 << 0) /**< \brief (SUPC_SMMR) 2.7 V */ -#define SUPC_SMMR_SMTH_2_8V (0x9 << 0) /**< \brief (SUPC_SMMR) 2.8 V */ -#define SUPC_SMMR_SMTH_2_9V (0xA << 0) /**< \brief (SUPC_SMMR) 2.9 V */ -#define SUPC_SMMR_SMTH_3_0V (0xB << 0) /**< \brief (SUPC_SMMR) 3.0 V */ -#define SUPC_SMMR_SMTH_3_1V (0xC << 0) /**< \brief (SUPC_SMMR) 3.1 V */ -#define SUPC_SMMR_SMTH_3_2V (0xD << 0) /**< \brief (SUPC_SMMR) 3.2 V */ -#define SUPC_SMMR_SMTH_3_3V (0xE << 0) /**< \brief (SUPC_SMMR) 3.3 V */ -#define SUPC_SMMR_SMTH_3_4V (0xF << 0) /**< \brief (SUPC_SMMR) 3.4 V */ -#define SUPC_SMMR_SMSMPL (0x7 << 8) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ -#define SUPC_SMMR_SMSMPL_SMD (0x0 << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ -#define SUPC_SMMR_SMSMPL_CSM (0x1 << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ -#define SUPC_SMMR_SMSMPL_32SLCK (0x2 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ -#define SUPC_SMMR_SMSMPL_256SLCK (0x3 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ -#define SUPC_SMMR_SMSMPL_2048SLCK (0x4 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ -#define SUPC_SMMR_SMRSTEN (0x1 << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ -#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN (0x1 << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ -#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN_ENABLE (0x1 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ -/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ -#define SUPC_MR_BODRSTEN (0x1 << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ -#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ -#define SUPC_MR_BODRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ -#define SUPC_MR_BODDIS (0x1 << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ -#define SUPC_MR_BODDIS_ENABLE (0x0 << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ -#define SUPC_MR_BODDIS_DISABLE (0x1 << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ -#define SUPC_MR_VDDIORDY (0x1 << 14) /**< \brief (SUPC_MR) VDDIO Ready */ -#define SUPC_MR_VDDIORDY_VDDIO_REMOVED (0x0 << 14) /**< \brief (SUPC_MR) VDDIO is removed (used before going to backup mode when backup batteries are used) */ -#define SUPC_MR_VDDIORDY_VDDIO_PRESENT (0x1 << 14) /**< \brief (SUPC_MR) VDDIO is present (used before going to backup mode when backup batteries are used) */ -#define SUPC_MR_OSCBYPASS (0x1 << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ -#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0 << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ -#define SUPC_MR_OSCBYPASS_BYPASS (0x1 << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ -#define SUPC_MR_KEY (0xff << 24) /**< \brief (SUPC_MR) Password Key */ -/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */ -#define SUPC_WUMR_FWUPEN (0x1 << 0) /**< \brief (SUPC_WUMR) Force Wake Up Enable */ -#define SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0 << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin has no wake up effect. */ -#define SUPC_WUMR_FWUPEN_ENABLE (0x1 << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin low forces the wake up of the core power supply. */ -#define SUPC_WUMR_SMEN (0x1 << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */ -#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */ -#define SUPC_WUMR_SMEN_ENABLE (0x1 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTTEN (0x1 << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */ -#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTTEN_ENABLE (0x1 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTCEN (0x1 << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */ -#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTCEN_ENABLE (0x1 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_FWUPDBC (0x7 << 8) /**< \brief (SUPC_WUMR) Force Wake Up Debouncer */ -#define SUPC_WUMR_FWUPDBC_1SCLK (0x0 << 8) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ -#define SUPC_WUMR_FWUPDBC_3SCLK (0x1 << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 3 SLCK periods */ -#define SUPC_WUMR_FWUPDBC_32SCLK (0x2 << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32 SLCK periods */ -#define SUPC_WUMR_FWUPDBC_512SCLK (0x3 << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 512 SLCK periods */ -#define SUPC_WUMR_FWUPDBC_4096SCLK (0x4 << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 4,096 SLCK periods */ -#define SUPC_WUMR_FWUPDBC_32768SCLK (0x5 << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32,768 SLCK periods */ -#define SUPC_WUMR_WKUPDBC (0x7 << 12) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer */ -#define SUPC_WUMR_WKUPDBC_1SCLK (0x0 << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ -#define SUPC_WUMR_WKUPDBC_3SCLK (0x1 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 3 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32SCLK (0x2 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_512SCLK (0x3 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 512 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_4096SCLK (0x4 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 4,096 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32768SCLK (0x5 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32,768 SLCK periods */ -/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */ -#define SUPC_WUIR_WKUPEN0 (0x1 << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */ -#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN0_ENABLE (0x1 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN1 (0x1 << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */ -#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN1_ENABLE (0x1 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN2 (0x1 << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */ -#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN2_ENABLE (0x1 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN3 (0x1 << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */ -#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN3_ENABLE (0x1 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN4 (0x1 << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */ -#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN4_ENABLE (0x1 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN5 (0x1 << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */ -#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN5_ENABLE (0x1 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN6 (0x1 << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */ -#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN6_ENABLE (0x1 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN7 (0x1 << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */ -#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN7_ENABLE (0x1 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN8 (0x1 << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */ -#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN8_ENABLE (0x1 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN9 (0x1 << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */ -#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN9_ENABLE (0x1 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN10 (0x1 << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */ -#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN10_ENABLE (0x1 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN11 (0x1 << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */ -#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN11_ENABLE (0x1 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN12 (0x1 << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */ -#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN12_ENABLE (0x1 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN13 (0x1 << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */ -#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN13_ENABLE (0x1 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN14 (0x1 << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */ -#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN14_ENABLE (0x1 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN15 (0x1 << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */ -#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN15_ENABLE (0x1 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0 (0x1 << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */ -#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0 << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1 << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1 (0x1 << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */ -#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0 << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1 << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2 (0x1 << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */ -#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0 << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1 << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3 (0x1 << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */ -#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0 << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1 << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4 (0x1 << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */ -#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0 << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1 << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5 (0x1 << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */ -#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0 << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1 << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6 (0x1 << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */ -#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0 << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1 << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7 (0x1 << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */ -#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0 << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1 << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8 (0x1 << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */ -#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0 << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1 << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9 (0x1 << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */ -#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0 << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1 << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10 (0x1 << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */ -#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0 << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1 << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11 (0x1 << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */ -#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0 << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1 << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12 (0x1 << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */ -#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0 << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1 << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13 (0x1 << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */ -#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0 << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1 << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14 (0x1 << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */ -#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0 << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1 << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15 (0x1 << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */ -#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0 << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1 << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ -#define SUPC_SR_FWUPS (0x1 << 0) /**< \brief (SUPC_SR) FWUP Wake Up Status */ -#define SUPC_SR_FWUPS_NO (0x0 << 0) /**< \brief (SUPC_SR) no wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_FWUPS_PRESENT (0x1 << 0) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_WKUPS (0x1 << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */ -#define SUPC_SR_WKUPS_NO (0x0 << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_WKUPS_PRESENT (0x1 << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS (0x1 << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */ -#define SUPC_SR_SMWS_NO (0x0 << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS_PRESENT (0x1 << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_BODRSTS (0x1 << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ -#define SUPC_SR_BODRSTS_NO (0x0 << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_BODRSTS_PRESENT (0x1 << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS (0x1 << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ -#define SUPC_SR_SMRSTS_NO (0x0 << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS_PRESENT (0x1 << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMS (0x1 << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ -#define SUPC_SR_SMS_NO (0x0 << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMS_PRESENT (0x1 << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMOS (0x1 << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ -#define SUPC_SR_SMOS_HIGH (0x0 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI higher than its threshold at its last measurement. */ -#define SUPC_SR_SMOS_LOW (0x1 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI lower than its threshold at its last measurement. */ -#define SUPC_SR_OSCSEL (0x1 << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ -#define SUPC_SR_OSCSEL_RC (0x0 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ -#define SUPC_SR_OSCSEL_CRYST (0x1 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ -#define SUPC_SR_FWUPIS (0x1 << 12) /**< \brief (SUPC_SR) FWUP Input Status */ -#define SUPC_SR_FWUPIS_LOW (0x0 << 12) /**< \brief (SUPC_SR) FWUP input is tied low. */ -#define SUPC_SR_FWUPIS_HIGH (0x1 << 12) /**< \brief (SUPC_SR) FWUP input is tied high. */ -#define SUPC_SR_WKUPIS0 (0x1 << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ -#define SUPC_SR_WKUPIS0_DIS (0x0 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS0_EN (0x1 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1 (0x1 << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ -#define SUPC_SR_WKUPIS1_DIS (0x0 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1_EN (0x1 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2 (0x1 << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ -#define SUPC_SR_WKUPIS2_DIS (0x0 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2_EN (0x1 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3 (0x1 << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ -#define SUPC_SR_WKUPIS3_DIS (0x0 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3_EN (0x1 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4 (0x1 << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ -#define SUPC_SR_WKUPIS4_DIS (0x0 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4_EN (0x1 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5 (0x1 << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ -#define SUPC_SR_WKUPIS5_DIS (0x0 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5_EN (0x1 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6 (0x1 << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ -#define SUPC_SR_WKUPIS6_DIS (0x0 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6_EN (0x1 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7 (0x1 << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ -#define SUPC_SR_WKUPIS7_DIS (0x0 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7_EN (0x1 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8 (0x1 << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ -#define SUPC_SR_WKUPIS8_DIS (0x0 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8_EN (0x1 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9 (0x1 << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ -#define SUPC_SR_WKUPIS9_DIS (0x0 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9_EN (0x1 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10 (0x1 << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ -#define SUPC_SR_WKUPIS10_DIS (0x0 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10_EN (0x1 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11 (0x1 << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ -#define SUPC_SR_WKUPIS11_DIS (0x0 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11_EN (0x1 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12 (0x1 << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ -#define SUPC_SR_WKUPIS12_DIS (0x0 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12_EN (0x1 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13 (0x1 << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ -#define SUPC_SR_WKUPIS13_DIS (0x0 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13_EN (0x1 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14 (0x1 << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ -#define SUPC_SR_WKUPIS14_DIS (0x0 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14_EN (0x1 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15 (0x1 << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ -#define SUPC_SR_WKUPIS15_DIS (0x0 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15_EN (0x1 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Timer Counter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_TC Timer Counter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief TcChannel hardware registers */ -typedef struct { - RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ - RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ - RwReg Reserved1[2]; - RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ - RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ - RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ - RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ - RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ - RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ - RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ - RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ - RwReg Reserved2[4]; -} TcChannel; -/** \brief Tc hardware registers */ -typedef struct { - TcChannel TC_CHANNEL[3]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ - WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ - RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ - WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ - WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ - RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ - RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ - RwReg Reserved1[9]; - RoReg TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ -} Tc; -#endif /* __ASSEMBLY__ */ -/* -------- TC_CCR0 : (TC Offset: 0x0) Channel Control Register (channel = 0) -------- */ -#define TC_CCR0_CLKEN (0x1 << 0) /**< \brief (TC_CCR0) Counter Clock Enable Command */ -#define TC_CCR0_CLKDIS (0x1 << 1) /**< \brief (TC_CCR0) Counter Clock Disable Command */ -#define TC_CCR0_SWTRG (0x1 << 2) /**< \brief (TC_CCR0) Software Trigger Command */ -/* -------- TC_CMR0 : (TC Offset: 0x4) Channel Mode Register (channel = 0) -------- */ -#define TC_CMR0_TCCLKS (0x7 << 0) /**< \brief (TC_CMR0) Clock Selection */ -#define TC_CMR0_CLKI (0x1 << 3) /**< \brief (TC_CMR0) Clock Invert */ -#define TC_CMR0_BURST (0x3 << 4) /**< \brief (TC_CMR0) Burst Signal Selection */ -#define TC_CMR0_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR0) The clock is not gated by an external signal. */ -#define TC_CMR0_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR0) XC0 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR0) XC1 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR0) XC2 is ANDed with the selected clock. */ -#define TC_CMR0_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR0) Counter Clock Stopped with RB Loading */ -#define TC_CMR0_LDBDIS (0x1 << 7) /**< \brief (TC_CMR0) Counter Clock Disable with RB Loading */ -#define TC_CMR0_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR0) External Trigger Edge Selection */ -#define TC_CMR0_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR0) rising edge */ -#define TC_CMR0_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR0) falling edge */ -#define TC_CMR0_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR0) each edge */ -#define TC_CMR0_ABETRG (0x1 << 10) /**< \brief (TC_CMR0) TIOA or TIOB External Trigger Selection */ -#define TC_CMR0_CPCTRG (0x1 << 14) /**< \brief (TC_CMR0) RC Compare Trigger Enable */ -#define TC_CMR0_WAVE (0x1 << 15) /**< \brief (TC_CMR0) */ -#define TC_CMR0_LDRA (0x3 << 16) /**< \brief (TC_CMR0) RA Loading Selection */ -#define TC_CMR0_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR0) each edge of TIOA */ -#define TC_CMR0_LDRB (0x3 << 18) /**< \brief (TC_CMR0) RB Loading Selection */ -#define TC_CMR0_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR0) each edge of TIOA */ -/* -------- TC_CV0 : (TC Offset: 0x10) Counter Value (channel = 0) -------- */ -#define TC_CV0_CV (0xffff << 0) /**< \brief (TC_CV0) Counter Value */ -/* -------- TC_RA0 : (TC Offset: 0x14) Register A (channel = 0) -------- */ -#define TC_RA0_RA (0xffff << 0) /**< \brief (TC_RA0) Register A */ -/* -------- TC_RB0 : (TC Offset: 0x18) Register B (channel = 0) -------- */ -#define TC_RB0_RB (0xffff << 0) /**< \brief (TC_RB0) Register B */ -/* -------- TC_RC0 : (TC Offset: 0x1C) Register C (channel = 0) -------- */ -#define TC_RC0_RC (0xffff << 0) /**< \brief (TC_RC0) Register C */ -/* -------- TC_SR0 : (TC Offset: 0x20) Status Register (channel = 0) -------- */ -#define TC_SR0_COVFS (0x1 << 0) /**< \brief (TC_SR0) Counter Overflow Status */ -#define TC_SR0_LOVRS (0x1 << 1) /**< \brief (TC_SR0) Load Overrun Status */ -#define TC_SR0_CPAS (0x1 << 2) /**< \brief (TC_SR0) RA Compare Status */ -#define TC_SR0_CPBS (0x1 << 3) /**< \brief (TC_SR0) RB Compare Status */ -#define TC_SR0_CPCS (0x1 << 4) /**< \brief (TC_SR0) RC Compare Status */ -#define TC_SR0_LDRAS (0x1 << 5) /**< \brief (TC_SR0) RA Loading Status */ -#define TC_SR0_LDRBS (0x1 << 6) /**< \brief (TC_SR0) RB Loading Status */ -#define TC_SR0_ETRGS (0x1 << 7) /**< \brief (TC_SR0) External Trigger Status */ -#define TC_SR0_CLKSTA (0x1 << 16) /**< \brief (TC_SR0) Clock Enabling Status */ -#define TC_SR0_MTIOA (0x1 << 17) /**< \brief (TC_SR0) TIOA Mirror */ -#define TC_SR0_MTIOB (0x1 << 18) /**< \brief (TC_SR0) TIOB Mirror */ -/* -------- TC_IER0 : (TC Offset: 0x24) Interrupt Enable Register (channel = 0) -------- */ -#define TC_IER0_COVFS (0x1 << 0) /**< \brief (TC_IER0) Counter Overflow */ -#define TC_IER0_LOVRS (0x1 << 1) /**< \brief (TC_IER0) Load Overrun */ -#define TC_IER0_CPAS (0x1 << 2) /**< \brief (TC_IER0) RA Compare */ -#define TC_IER0_CPBS (0x1 << 3) /**< \brief (TC_IER0) RB Compare */ -#define TC_IER0_CPCS (0x1 << 4) /**< \brief (TC_IER0) RC Compare */ -#define TC_IER0_LDRAS (0x1 << 5) /**< \brief (TC_IER0) RA Loading */ -#define TC_IER0_LDRBS (0x1 << 6) /**< \brief (TC_IER0) RB Loading */ -#define TC_IER0_ETRGS (0x1 << 7) /**< \brief (TC_IER0) External Trigger */ -/* -------- TC_IDR0 : (TC Offset: 0x28) Interrupt Disable Register (channel = 0) -------- */ -#define TC_IDR0_COVFS (0x1 << 0) /**< \brief (TC_IDR0) Counter Overflow */ -#define TC_IDR0_LOVRS (0x1 << 1) /**< \brief (TC_IDR0) Load Overrun */ -#define TC_IDR0_CPAS (0x1 << 2) /**< \brief (TC_IDR0) RA Compare */ -#define TC_IDR0_CPBS (0x1 << 3) /**< \brief (TC_IDR0) RB Compare */ -#define TC_IDR0_CPCS (0x1 << 4) /**< \brief (TC_IDR0) RC Compare */ -#define TC_IDR0_LDRAS (0x1 << 5) /**< \brief (TC_IDR0) RA Loading */ -#define TC_IDR0_LDRBS (0x1 << 6) /**< \brief (TC_IDR0) RB Loading */ -#define TC_IDR0_ETRGS (0x1 << 7) /**< \brief (TC_IDR0) External Trigger */ -/* -------- TC_IMR0 : (TC Offset: 0x2C) Interrupt Mask Register (channel = 0) -------- */ -#define TC_IMR0_COVFS (0x1 << 0) /**< \brief (TC_IMR0) Counter Overflow */ -#define TC_IMR0_LOVRS (0x1 << 1) /**< \brief (TC_IMR0) Load Overrun */ -#define TC_IMR0_CPAS (0x1 << 2) /**< \brief (TC_IMR0) RA Compare */ -#define TC_IMR0_CPBS (0x1 << 3) /**< \brief (TC_IMR0) RB Compare */ -#define TC_IMR0_CPCS (0x1 << 4) /**< \brief (TC_IMR0) RC Compare */ -#define TC_IMR0_LDRAS (0x1 << 5) /**< \brief (TC_IMR0) RA Loading */ -#define TC_IMR0_LDRBS (0x1 << 6) /**< \brief (TC_IMR0) RB Loading */ -#define TC_IMR0_ETRGS (0x1 << 7) /**< \brief (TC_IMR0) External Trigger */ -/* -------- TC_CCR1 : (TC Offset: 0x40) Channel Control Register (channel = 1) -------- */ -#define TC_CCR1_CLKEN (0x1 << 0) /**< \brief (TC_CCR1) Counter Clock Enable Command */ -#define TC_CCR1_CLKDIS (0x1 << 1) /**< \brief (TC_CCR1) Counter Clock Disable Command */ -#define TC_CCR1_SWTRG (0x1 << 2) /**< \brief (TC_CCR1) Software Trigger Command */ -/* -------- TC_CMR1 : (TC Offset: 0x44) Channel Mode Register (channel = 1) -------- */ -#define TC_CMR1_TCCLKS (0x7 << 0) /**< \brief (TC_CMR1) Clock Selection */ -#define TC_CMR1_CLKI (0x1 << 3) /**< \brief (TC_CMR1) Clock Invert */ -#define TC_CMR1_BURST (0x3 << 4) /**< \brief (TC_CMR1) Burst Signal Selection */ -#define TC_CMR1_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR1) The clock is not gated by an external signal. */ -#define TC_CMR1_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR1) XC0 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR1) XC1 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR1) XC2 is ANDed with the selected clock. */ -#define TC_CMR1_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR1) Counter Clock Stopped with RB Loading */ -#define TC_CMR1_LDBDIS (0x1 << 7) /**< \brief (TC_CMR1) Counter Clock Disable with RB Loading */ -#define TC_CMR1_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR1) External Trigger Edge Selection */ -#define TC_CMR1_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR1) rising edge */ -#define TC_CMR1_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR1) falling edge */ -#define TC_CMR1_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR1) each edge */ -#define TC_CMR1_ABETRG (0x1 << 10) /**< \brief (TC_CMR1) TIOA or TIOB External Trigger Selection */ -#define TC_CMR1_CPCTRG (0x1 << 14) /**< \brief (TC_CMR1) RC Compare Trigger Enable */ -#define TC_CMR1_WAVE (0x1 << 15) /**< \brief (TC_CMR1) */ -#define TC_CMR1_LDRA (0x3 << 16) /**< \brief (TC_CMR1) RA Loading Selection */ -#define TC_CMR1_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR1) each edge of TIOA */ -#define TC_CMR1_LDRB (0x3 << 18) /**< \brief (TC_CMR1) RB Loading Selection */ -#define TC_CMR1_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR1) each edge of TIOA */ -/* -------- TC_CV1 : (TC Offset: 0x50) Counter Value (channel = 1) -------- */ -#define TC_CV1_CV (0xffff << 0) /**< \brief (TC_CV1) Counter Value */ -/* -------- TC_RA1 : (TC Offset: 0x54) Register A (channel = 1) -------- */ -#define TC_RA1_RA (0xffff << 0) /**< \brief (TC_RA1) Register A */ -/* -------- TC_RB1 : (TC Offset: 0x58) Register B (channel = 1) -------- */ -#define TC_RB1_RB (0xffff << 0) /**< \brief (TC_RB1) Register B */ -/* -------- TC_RC1 : (TC Offset: 0x5C) Register C (channel = 1) -------- */ -#define TC_RC1_RC (0xffff << 0) /**< \brief (TC_RC1) Register C */ -/* -------- TC_SR1 : (TC Offset: 0x60) Status Register (channel = 1) -------- */ -#define TC_SR1_COVFS (0x1 << 0) /**< \brief (TC_SR1) Counter Overflow Status */ -#define TC_SR1_LOVRS (0x1 << 1) /**< \brief (TC_SR1) Load Overrun Status */ -#define TC_SR1_CPAS (0x1 << 2) /**< \brief (TC_SR1) RA Compare Status */ -#define TC_SR1_CPBS (0x1 << 3) /**< \brief (TC_SR1) RB Compare Status */ -#define TC_SR1_CPCS (0x1 << 4) /**< \brief (TC_SR1) RC Compare Status */ -#define TC_SR1_LDRAS (0x1 << 5) /**< \brief (TC_SR1) RA Loading Status */ -#define TC_SR1_LDRBS (0x1 << 6) /**< \brief (TC_SR1) RB Loading Status */ -#define TC_SR1_ETRGS (0x1 << 7) /**< \brief (TC_SR1) External Trigger Status */ -#define TC_SR1_CLKSTA (0x1 << 16) /**< \brief (TC_SR1) Clock Enabling Status */ -#define TC_SR1_MTIOA (0x1 << 17) /**< \brief (TC_SR1) TIOA Mirror */ -#define TC_SR1_MTIOB (0x1 << 18) /**< \brief (TC_SR1) TIOB Mirror */ -/* -------- TC_IER1 : (TC Offset: 0x64) Interrupt Enable Register (channel = 1) -------- */ -#define TC_IER1_COVFS (0x1 << 0) /**< \brief (TC_IER1) Counter Overflow */ -#define TC_IER1_LOVRS (0x1 << 1) /**< \brief (TC_IER1) Load Overrun */ -#define TC_IER1_CPAS (0x1 << 2) /**< \brief (TC_IER1) RA Compare */ -#define TC_IER1_CPBS (0x1 << 3) /**< \brief (TC_IER1) RB Compare */ -#define TC_IER1_CPCS (0x1 << 4) /**< \brief (TC_IER1) RC Compare */ -#define TC_IER1_LDRAS (0x1 << 5) /**< \brief (TC_IER1) RA Loading */ -#define TC_IER1_LDRBS (0x1 << 6) /**< \brief (TC_IER1) RB Loading */ -#define TC_IER1_ETRGS (0x1 << 7) /**< \brief (TC_IER1) External Trigger */ -/* -------- TC_IDR1 : (TC Offset: 0x68) Interrupt Disable Register (channel = 1) -------- */ -#define TC_IDR1_COVFS (0x1 << 0) /**< \brief (TC_IDR1) Counter Overflow */ -#define TC_IDR1_LOVRS (0x1 << 1) /**< \brief (TC_IDR1) Load Overrun */ -#define TC_IDR1_CPAS (0x1 << 2) /**< \brief (TC_IDR1) RA Compare */ -#define TC_IDR1_CPBS (0x1 << 3) /**< \brief (TC_IDR1) RB Compare */ -#define TC_IDR1_CPCS (0x1 << 4) /**< \brief (TC_IDR1) RC Compare */ -#define TC_IDR1_LDRAS (0x1 << 5) /**< \brief (TC_IDR1) RA Loading */ -#define TC_IDR1_LDRBS (0x1 << 6) /**< \brief (TC_IDR1) RB Loading */ -#define TC_IDR1_ETRGS (0x1 << 7) /**< \brief (TC_IDR1) External Trigger */ -/* -------- TC_IMR1 : (TC Offset: 0x6C) Interrupt Mask Register (channel = 1) -------- */ -#define TC_IMR1_COVFS (0x1 << 0) /**< \brief (TC_IMR1) Counter Overflow */ -#define TC_IMR1_LOVRS (0x1 << 1) /**< \brief (TC_IMR1) Load Overrun */ -#define TC_IMR1_CPAS (0x1 << 2) /**< \brief (TC_IMR1) RA Compare */ -#define TC_IMR1_CPBS (0x1 << 3) /**< \brief (TC_IMR1) RB Compare */ -#define TC_IMR1_CPCS (0x1 << 4) /**< \brief (TC_IMR1) RC Compare */ -#define TC_IMR1_LDRAS (0x1 << 5) /**< \brief (TC_IMR1) RA Loading */ -#define TC_IMR1_LDRBS (0x1 << 6) /**< \brief (TC_IMR1) RB Loading */ -#define TC_IMR1_ETRGS (0x1 << 7) /**< \brief (TC_IMR1) External Trigger */ -/* -------- TC_CCR2 : (TC Offset: 0x80) Channel Control Register (channel = 2) -------- */ -#define TC_CCR2_CLKEN (0x1 << 0) /**< \brief (TC_CCR2) Counter Clock Enable Command */ -#define TC_CCR2_CLKDIS (0x1 << 1) /**< \brief (TC_CCR2) Counter Clock Disable Command */ -#define TC_CCR2_SWTRG (0x1 << 2) /**< \brief (TC_CCR2) Software Trigger Command */ -/* -------- TC_CMR2 : (TC Offset: 0x84) Channel Mode Register (channel = 2) -------- */ -#define TC_CMR2_TCCLKS (0x7 << 0) /**< \brief (TC_CMR2) Clock Selection */ -#define TC_CMR2_CLKI (0x1 << 3) /**< \brief (TC_CMR2) Clock Invert */ -#define TC_CMR2_BURST (0x3 << 4) /**< \brief (TC_CMR2) Burst Signal Selection */ -#define TC_CMR2_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR2) The clock is not gated by an external signal. */ -#define TC_CMR2_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR2) XC0 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR2) XC1 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR2) XC2 is ANDed with the selected clock. */ -#define TC_CMR2_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR2) Counter Clock Stopped with RB Loading */ -#define TC_CMR2_LDBDIS (0x1 << 7) /**< \brief (TC_CMR2) Counter Clock Disable with RB Loading */ -#define TC_CMR2_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR2) External Trigger Edge Selection */ -#define TC_CMR2_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR2) rising edge */ -#define TC_CMR2_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR2) falling edge */ -#define TC_CMR2_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR2) each edge */ -#define TC_CMR2_ABETRG (0x1 << 10) /**< \brief (TC_CMR2) TIOA or TIOB External Trigger Selection */ -#define TC_CMR2_CPCTRG (0x1 << 14) /**< \brief (TC_CMR2) RC Compare Trigger Enable */ -#define TC_CMR2_WAVE (0x1 << 15) /**< \brief (TC_CMR2) */ -#define TC_CMR2_LDRA (0x3 << 16) /**< \brief (TC_CMR2) RA Loading Selection */ -#define TC_CMR2_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR2) each edge of TIOA */ -#define TC_CMR2_LDRB (0x3 << 18) /**< \brief (TC_CMR2) RB Loading Selection */ -#define TC_CMR2_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR2) each edge of TIOA */ -/* -------- TC_CV2 : (TC Offset: 0x90) Counter Value (channel = 2) -------- */ -#define TC_CV2_CV (0xffff << 0) /**< \brief (TC_CV2) Counter Value */ -/* -------- TC_RA2 : (TC Offset: 0x94) Register A (channel = 2) -------- */ -#define TC_RA2_RA (0xffff << 0) /**< \brief (TC_RA2) Register A */ -/* -------- TC_RB2 : (TC Offset: 0x98) Register B (channel = 2) -------- */ -#define TC_RB2_RB (0xffff << 0) /**< \brief (TC_RB2) Register B */ -/* -------- TC_RC2 : (TC Offset: 0x9C) Register C (channel = 2) -------- */ -#define TC_RC2_RC (0xffff << 0) /**< \brief (TC_RC2) Register C */ -/* -------- TC_SR2 : (TC Offset: 0xA0) Status Register (channel = 2) -------- */ -#define TC_SR2_COVFS (0x1 << 0) /**< \brief (TC_SR2) Counter Overflow Status */ -#define TC_SR2_LOVRS (0x1 << 1) /**< \brief (TC_SR2) Load Overrun Status */ -#define TC_SR2_CPAS (0x1 << 2) /**< \brief (TC_SR2) RA Compare Status */ -#define TC_SR2_CPBS (0x1 << 3) /**< \brief (TC_SR2) RB Compare Status */ -#define TC_SR2_CPCS (0x1 << 4) /**< \brief (TC_SR2) RC Compare Status */ -#define TC_SR2_LDRAS (0x1 << 5) /**< \brief (TC_SR2) RA Loading Status */ -#define TC_SR2_LDRBS (0x1 << 6) /**< \brief (TC_SR2) RB Loading Status */ -#define TC_SR2_ETRGS (0x1 << 7) /**< \brief (TC_SR2) External Trigger Status */ -#define TC_SR2_CLKSTA (0x1 << 16) /**< \brief (TC_SR2) Clock Enabling Status */ -#define TC_SR2_MTIOA (0x1 << 17) /**< \brief (TC_SR2) TIOA Mirror */ -#define TC_SR2_MTIOB (0x1 << 18) /**< \brief (TC_SR2) TIOB Mirror */ -/* -------- TC_IER2 : (TC Offset: 0xA4) Interrupt Enable Register (channel = 2) -------- */ -#define TC_IER2_COVFS (0x1 << 0) /**< \brief (TC_IER2) Counter Overflow */ -#define TC_IER2_LOVRS (0x1 << 1) /**< \brief (TC_IER2) Load Overrun */ -#define TC_IER2_CPAS (0x1 << 2) /**< \brief (TC_IER2) RA Compare */ -#define TC_IER2_CPBS (0x1 << 3) /**< \brief (TC_IER2) RB Compare */ -#define TC_IER2_CPCS (0x1 << 4) /**< \brief (TC_IER2) RC Compare */ -#define TC_IER2_LDRAS (0x1 << 5) /**< \brief (TC_IER2) RA Loading */ -#define TC_IER2_LDRBS (0x1 << 6) /**< \brief (TC_IER2) RB Loading */ -#define TC_IER2_ETRGS (0x1 << 7) /**< \brief (TC_IER2) External Trigger */ -/* -------- TC_IDR2 : (TC Offset: 0xA8) Interrupt Disable Register (channel = 2) -------- */ -#define TC_IDR2_COVFS (0x1 << 0) /**< \brief (TC_IDR2) Counter Overflow */ -#define TC_IDR2_LOVRS (0x1 << 1) /**< \brief (TC_IDR2) Load Overrun */ -#define TC_IDR2_CPAS (0x1 << 2) /**< \brief (TC_IDR2) RA Compare */ -#define TC_IDR2_CPBS (0x1 << 3) /**< \brief (TC_IDR2) RB Compare */ -#define TC_IDR2_CPCS (0x1 << 4) /**< \brief (TC_IDR2) RC Compare */ -#define TC_IDR2_LDRAS (0x1 << 5) /**< \brief (TC_IDR2) RA Loading */ -#define TC_IDR2_LDRBS (0x1 << 6) /**< \brief (TC_IDR2) RB Loading */ -#define TC_IDR2_ETRGS (0x1 << 7) /**< \brief (TC_IDR2) External Trigger */ -/* -------- TC_IMR2 : (TC Offset: 0xAC) Interrupt Mask Register (channel = 2) -------- */ -#define TC_IMR2_COVFS (0x1 << 0) /**< \brief (TC_IMR2) Counter Overflow */ -#define TC_IMR2_LOVRS (0x1 << 1) /**< \brief (TC_IMR2) Load Overrun */ -#define TC_IMR2_CPAS (0x1 << 2) /**< \brief (TC_IMR2) RA Compare */ -#define TC_IMR2_CPBS (0x1 << 3) /**< \brief (TC_IMR2) RB Compare */ -#define TC_IMR2_CPCS (0x1 << 4) /**< \brief (TC_IMR2) RC Compare */ -#define TC_IMR2_LDRAS (0x1 << 5) /**< \brief (TC_IMR2) RA Loading */ -#define TC_IMR2_LDRBS (0x1 << 6) /**< \brief (TC_IMR2) RB Loading */ -#define TC_IMR2_ETRGS (0x1 << 7) /**< \brief (TC_IMR2) External Trigger */ -/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ -#define TC_BCR_SYNC (0x1 << 0) /**< \brief (TC_BCR) Synchro Command */ -/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ -#define TC_BMR_TC0XC0S (0x3 << 0) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ -#define TC_BMR_TC0XC0S_TCLK0 (0x0 << 0) /**< \brief (TC_BMR) TCLK0 */ -#define TC_BMR_TC0XC0S_NONE (0x1 << 0) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC0XC0S_TIOA1 (0x2 << 0) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_TC0XC0S_TIOA2 (0x3 << 0) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC1XC1S (0x3 << 2) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ -#define TC_BMR_TC1XC1S_TCLK1 (0x0 << 2) /**< \brief (TC_BMR) TCLK1 */ -#define TC_BMR_TC1XC1S_NONE (0x1 << 2) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC1XC1S_TIOA0 (0x2 << 2) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC1XC1S_TIOA2 (0x3 << 2) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC2XC2S (0x3 << 4) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ -#define TC_BMR_TC2XC2S_TCLK2 (0x0 << 4) /**< \brief (TC_BMR) TCLK2 */ -#define TC_BMR_TC2XC2S_NONE (0x1 << 4) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC2XC2S_TIOA0 (0x2 << 4) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC2XC2S_TIOA1 (0x3 << 4) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_QDEN (0x1 << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ -#define TC_BMR_POSEN (0x1 << 9) /**< \brief (TC_BMR) POSition ENabled */ -#define TC_BMR_SPEEDEN (0x1 << 10) /**< \brief (TC_BMR) SPEED ENabled */ -#define TC_BMR_QDTRANS (0x1 << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ -#define TC_BMR_EDGPHA (0x1 << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ -#define TC_BMR_INVA (0x1 << 13) /**< \brief (TC_BMR) INVerted phA */ -#define TC_BMR_INVB (0x1 << 14) /**< \brief (TC_BMR) INVerted phB */ -#define TC_BMR_INVIDX (0x1 << 15) /**< \brief (TC_BMR) INVerted InDeX */ -#define TC_BMR_SWAP (0x1 << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ -#define TC_BMR_IDXPHB (0x1 << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ -#define TC_BMR_FILTER (0x1 << 19) /**< \brief (TC_BMR) */ -#define TC_BMR_MAXFILT (0x3f << 20) /**< \brief (TC_BMR) MAXimum FILTer */ -/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ -#define TC_QIER_IDX (0x1 << 0) /**< \brief (TC_QIER) InDeX */ -#define TC_QIER_DIRCHG (0x1 << 1) /**< \brief (TC_QIER) DIRection CHanGe */ -#define TC_QIER_QERR (0x1 << 2) /**< \brief (TC_QIER) Quadrature ERRor */ -/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ -#define TC_QIDR_IDX (0x1 << 0) /**< \brief (TC_QIDR) InDeX */ -#define TC_QIDR_DIRCHG (0x1 << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ -#define TC_QIDR_QERR (0x1 << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ -/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ -#define TC_QIMR_IDX (0x1 << 0) /**< \brief (TC_QIMR) InDeX */ -#define TC_QIMR_DIRCHG (0x1 << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ -#define TC_QIMR_QERR (0x1 << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ -/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ -#define TC_QISR_IDX (0x1 << 0) /**< \brief (TC_QISR) InDeX */ -#define TC_QISR_DIRCHG (0x1 << 1) /**< \brief (TC_QISR) DIRection CHanGe */ -#define TC_QISR_QERR (0x1 << 2) /**< \brief (TC_QISR) Quadrature ERRor */ -#define TC_QISR_DIR (0x1 << 8) /**< \brief (TC_QISR) Direction */ -/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ -#define TC_VER_VERSION (0xfff << 0) /**< \brief (TC_VER) */ -#define TC_VER_MFN (0x7 << 16) /**< \brief (TC_VER) */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Two-wire Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_TWI Two-wire Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Twi hardware registers */ -typedef struct { - WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ - RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ - RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ - RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ - RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ - RwReg Reserved1[3]; - RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ - WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ - WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ - RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ - RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ - WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ - RwReg Reserved2[50]; - RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ - RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ - RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ - RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ - RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ - RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ - RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ - RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ - WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ - RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ -} Twi; -#endif /* __ASSEMBLY__ */ -/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ -#define TWI_CR_START (0x1 << 0) /**< \brief (TWI_CR) Send a START Condition */ -#define TWI_CR_STOP (0x1 << 1) /**< \brief (TWI_CR) Send a STOP Condition */ -#define TWI_CR_MSEN (0x1 << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ -#define TWI_CR_MSDIS (0x1 << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ -#define TWI_CR_SVEN (0x1 << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ -#define TWI_CR_SVDIS (0x1 << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ -#define TWI_CR_QUICK (0x1 << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ -#define TWI_CR_SWRST (0x1 << 7) /**< \brief (TWI_CR) Software Reset */ -/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ -#define TWI_MMR_IADRSZ (0x3 << 8) /**< \brief (TWI_MMR) Internal Device Address Size */ -#define TWI_MMR_IADRSZ_NO (0x0 << 8) /**< \brief (TWI_MMR) No internal device address */ -#define TWI_MMR_IADRSZ_1_BYTE (0x1 << 8) /**< \brief (TWI_MMR) One-byte internal device address */ -#define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ -#define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ -#define TWI_MMR_MREAD (0x1 << 12) /**< \brief (TWI_MMR) Master Read Direction */ -#define TWI_MMR_DADR (0x7f << 16) /**< \brief (TWI_MMR) Device Address */ -/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ -#define TWI_SMR_SADR (0x7f << 16) /**< \brief (TWI_SMR) Slave Address */ -/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ -#define TWI_IADR_IADR (0xffffff << 0) /**< \brief (TWI_IADR) Internal Address */ -/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ -#define TWI_CWGR_CLDIV (0xff << 0) /**< \brief (TWI_CWGR) Clock Low Divider */ -#define TWI_CWGR_CHDIV (0xff << 8) /**< \brief (TWI_CWGR) Clock High Divider */ -#define TWI_CWGR_CKDIV (0x7 << 16) /**< \brief (TWI_CWGR) Clock Divider */ -/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ -#define TWI_SR_TXCOMP (0x1 << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ -#define TWI_SR_RXRDY (0x1 << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ -#define TWI_SR_TXRDY (0x1 << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ -#define TWI_SR_SVREAD (0x1 << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ -#define TWI_SR_SVACC (0x1 << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ -#define TWI_SR_GACC (0x1 << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ -#define TWI_SR_OVRE (0x1 << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ -#define TWI_SR_NACK (0x1 << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ -#define TWI_SR_ARBLST (0x1 << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ -#define TWI_SR_SCLWS (0x1 << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ -#define TWI_SR_EOSACC (0x1 << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ -#define TWI_SR_ENDRX (0x1 << 12) /**< \brief (TWI_SR) End of RX buffer */ -#define TWI_SR_ENDTX (0x1 << 13) /**< \brief (TWI_SR) End of TX buffer */ -#define TWI_SR_RXBUFF (0x1 << 14) /**< \brief (TWI_SR) RX Buffer Full */ -#define TWI_SR_TXBUFE (0x1 << 15) /**< \brief (TWI_SR) TX Buffer Empty */ -/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ -#define TWI_IER_TXCOMP (0x1 << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ -#define TWI_IER_RXRDY (0x1 << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ -#define TWI_IER_TXRDY (0x1 << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ -#define TWI_IER_SVACC (0x1 << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ -#define TWI_IER_GACC (0x1 << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ -#define TWI_IER_OVRE (0x1 << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ -#define TWI_IER_NACK (0x1 << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ -#define TWI_IER_ARBLST (0x1 << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ -#define TWI_IER_SCL_WS (0x1 << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ -#define TWI_IER_EOSACC (0x1 << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ -#define TWI_IER_ENDRX (0x1 << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ -#define TWI_IER_ENDTX (0x1 << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ -#define TWI_IER_RXBUFF (0x1 << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ -#define TWI_IER_TXBUFE (0x1 << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ -#define TWI_IDR_TXCOMP (0x1 << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ -#define TWI_IDR_RXRDY (0x1 << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ -#define TWI_IDR_TXRDY (0x1 << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ -#define TWI_IDR_SVACC (0x1 << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ -#define TWI_IDR_GACC (0x1 << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ -#define TWI_IDR_OVRE (0x1 << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ -#define TWI_IDR_NACK (0x1 << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ -#define TWI_IDR_ARBLST (0x1 << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ -#define TWI_IDR_SCL_WS (0x1 << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ -#define TWI_IDR_EOSACC (0x1 << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ -#define TWI_IDR_ENDRX (0x1 << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ -#define TWI_IDR_ENDTX (0x1 << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ -#define TWI_IDR_RXBUFF (0x1 << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ -#define TWI_IDR_TXBUFE (0x1 << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ -#define TWI_IMR_TXCOMP (0x1 << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ -#define TWI_IMR_RXRDY (0x1 << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ -#define TWI_IMR_TXRDY (0x1 << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ -#define TWI_IMR_SVACC (0x1 << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ -#define TWI_IMR_GACC (0x1 << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ -#define TWI_IMR_OVRE (0x1 << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ -#define TWI_IMR_NACK (0x1 << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ -#define TWI_IMR_ARBLST (0x1 << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ -#define TWI_IMR_SCL_WS (0x1 << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ -#define TWI_IMR_EOSACC (0x1 << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ -#define TWI_IMR_ENDRX (0x1 << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ -#define TWI_IMR_ENDTX (0x1 << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ -#define TWI_IMR_RXBUFF (0x1 << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ -#define TWI_IMR_TXBUFE (0x1 << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ -#define TWI_RHR_RXDATA (0xff << 0) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ -/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ -#define TWI_THR_TXDATA (0xff << 0) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ -/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ -#define TWI_RPR_RXPTR (0xffffffff << 0) /**< \brief (TWI_RPR) Receive Pointer Register */ -/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ -#define TWI_RCR_RXCTR (0xffff << 0) /**< \brief (TWI_RCR) Receive Counter Register */ -/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ -#define TWI_TPR_TXPTR (0xffffffff << 0) /**< \brief (TWI_TPR) Transmit Counter Register */ -/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ -#define TWI_TCR_TXCTR (0xffff << 0) /**< \brief (TWI_TCR) Transmit Counter Register */ -/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ -#define TWI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (TWI_RNPR) Receive Next Pointer */ -/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ -#define TWI_RNCR_RXNCTR (0xffff << 0) /**< \brief (TWI_RNCR) Receive Next Counter */ -/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define TWI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (TWI_TNPR) Transmit Next Pointer */ -/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define TWI_TNCR_TXNCTR (0xffff << 0) /**< \brief (TWI_TNCR) Transmit Counter Next */ -/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ -#define TWI_PTCR_RXTEN (0x1 << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ -#define TWI_PTCR_RXTDIS (0x1 << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ -#define TWI_PTCR_TXTEN (0x1 << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ -#define TWI_PTCR_TXTDIS (0x1 << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ -/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ -#define TWI_PTSR_RXTEN (0x1 << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ -#define TWI_PTSR_TXTEN (0x1 << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_UART Universal Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Uart hardware registers */ -typedef struct { - WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ - RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ - WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ - WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ - RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ - RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ - RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ - WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ - RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ - RwReg Reserved1[55]; - RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ - RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ - RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ - RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ - RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ - RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ - RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ - RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ - WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ - RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ -} Uart; -#endif /* __ASSEMBLY__ */ -/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ -#define UART_CR_RSTRX (0x1 << 2) /**< \brief (UART_CR) Reset Receiver */ -#define UART_CR_RSTTX (0x1 << 3) /**< \brief (UART_CR) Reset Transmitter */ -#define UART_CR_RXEN (0x1 << 4) /**< \brief (UART_CR) Receiver Enable */ -#define UART_CR_RXDIS (0x1 << 5) /**< \brief (UART_CR) Receiver Disable */ -#define UART_CR_TXEN (0x1 << 6) /**< \brief (UART_CR) Transmitter Enable */ -#define UART_CR_TXDIS (0x1 << 7) /**< \brief (UART_CR) Transmitter Disable */ -#define UART_CR_RSTSTA (0x1 << 8) /**< \brief (UART_CR) Reset Status Bits */ -/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ -#define UART_MR_PAR (0x7 << 9) /**< \brief (UART_MR) Parity Type */ -#define UART_MR_CHMODE (0x3 << 14) /**< \brief (UART_MR) Channel Mode */ -/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ -#define UART_IER_RXRDY (0x1 << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ -#define UART_IER_TXRDY (0x1 << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ -#define UART_IER_ENDRX (0x1 << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ -#define UART_IER_ENDTX (0x1 << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ -#define UART_IER_OVRE (0x1 << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ -#define UART_IER_FRAME (0x1 << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ -#define UART_IER_PARE (0x1 << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ -#define UART_IER_TXEMPTY (0x1 << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ -#define UART_IER_TXBUFE (0x1 << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ -#define UART_IER_RXBUFF (0x1 << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ -/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ -#define UART_IDR_RXRDY (0x1 << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ -#define UART_IDR_TXRDY (0x1 << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ -#define UART_IDR_ENDRX (0x1 << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ -#define UART_IDR_ENDTX (0x1 << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ -#define UART_IDR_OVRE (0x1 << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ -#define UART_IDR_FRAME (0x1 << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ -#define UART_IDR_PARE (0x1 << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ -#define UART_IDR_TXEMPTY (0x1 << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ -#define UART_IDR_TXBUFE (0x1 << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ -#define UART_IDR_RXBUFF (0x1 << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ -/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ -#define UART_IMR_RXRDY (0x1 << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ -#define UART_IMR_TXRDY (0x1 << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ -#define UART_IMR_ENDRX (0x1 << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ -#define UART_IMR_ENDTX (0x1 << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ -#define UART_IMR_OVRE (0x1 << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ -#define UART_IMR_FRAME (0x1 << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ -#define UART_IMR_PARE (0x1 << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ -#define UART_IMR_TXEMPTY (0x1 << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ -#define UART_IMR_TXBUFE (0x1 << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ -#define UART_IMR_RXBUFF (0x1 << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ -/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ -#define UART_SR_RXRDY (0x1 << 0) /**< \brief (UART_SR) Receiver Ready */ -#define UART_SR_TXRDY (0x1 << 1) /**< \brief (UART_SR) Transmitter Ready */ -#define UART_SR_ENDRX (0x1 << 3) /**< \brief (UART_SR) End of Receiver Transfer */ -#define UART_SR_ENDTX (0x1 << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ -#define UART_SR_OVRE (0x1 << 5) /**< \brief (UART_SR) Overrun Error */ -#define UART_SR_FRAME (0x1 << 6) /**< \brief (UART_SR) Framing Error */ -#define UART_SR_PARE (0x1 << 7) /**< \brief (UART_SR) Parity Error */ -#define UART_SR_TXEMPTY (0x1 << 9) /**< \brief (UART_SR) Transmitter Empty */ -#define UART_SR_TXBUFE (0x1 << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ -#define UART_SR_RXBUFF (0x1 << 12) /**< \brief (UART_SR) Receive Buffer Full */ -/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ -#define UART_RHR_RXCHR (0xff << 0) /**< \brief (UART_RHR) Received Character */ -/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ -#define UART_THR_TXCHR (0xff << 0) /**< \brief (UART_THR) Character to be Transmitted */ -/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define UART_BRGR_CD (0xffff << 0) /**< \brief (UART_BRGR) Clock Divisor */ -/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ -#define UART_RPR_RXPTR (0xffffffff << 0) /**< \brief (UART_RPR) Receive Pointer Register */ -/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ -#define UART_RCR_RXCTR (0xffff << 0) /**< \brief (UART_RCR) Receive Counter Register */ -/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ -#define UART_TPR_TXPTR (0xffffffff << 0) /**< \brief (UART_TPR) Transmit Counter Register */ -/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ -#define UART_TCR_TXCTR (0xffff << 0) /**< \brief (UART_TCR) Transmit Counter Register */ -/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ -#define UART_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (UART_RNPR) Receive Next Pointer */ -/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ -#define UART_RNCR_RXNCTR (0xffff << 0) /**< \brief (UART_RNCR) Receive Next Counter */ -/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define UART_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (UART_TNPR) Transmit Next Pointer */ -/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define UART_TNCR_TXNCTR (0xffff << 0) /**< \brief (UART_TNCR) Transmit Counter Next */ -/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ -#define UART_PTCR_RXTEN (0x1 << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ -#define UART_PTCR_RXTDIS (0x1 << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ -#define UART_PTCR_TXTEN (0x1 << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ -#define UART_PTCR_TXTDIS (0x1 << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ -/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ -#define UART_PTSR_RXTEN (0x1 << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ -#define UART_PTSR_TXTEN (0x1 << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR USB High Speed Device Port */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_UDPHS USB High Speed Device Port */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief UdphsDma hardware registers */ -typedef struct { - RwReg UDPHS_DMANXTDSC; /**< \brief (UdphsDma Offset: 0x0) UDPHS DMA Next Descriptor Address Register */ - RwReg UDPHS_DMAADDRESS; /**< \brief (UdphsDma Offset: 0x4) UDPHS DMA Channel Address Register */ - RwReg UDPHS_DMACONTROL; /**< \brief (UdphsDma Offset: 0x8) UDPHS DMA Channel Control Register */ - RwReg UDPHS_DMASTATUS; /**< \brief (UdphsDma Offset: 0xC) UDPHS DMA Channel Status Register */ -} UdphsDma; -/** \brief UdphsEpt hardware registers */ -typedef struct { - RwReg UDPHS_EPTCFG; /**< \brief (UdphsEpt Offset: 0x0) UDPHS Endpoint Configuration Register */ - RwReg UDPHS_EPTCTLENB; /**< \brief (UdphsEpt Offset: 0x4) UDPHS Endpoint Control Enable Register */ - RwReg UDPHS_EPTCTLDIS; /**< \brief (UdphsEpt Offset: 0x8) UDPHS Endpoint Control Disable Register */ - RwReg UDPHS_EPTCTL; /**< \brief (UdphsEpt Offset: 0xC) UDPHS Endpoint Control Register */ - RwReg Reserved1[1]; - RwReg UDPHS_EPTSETSTA; /**< \brief (UdphsEpt Offset: 0x14) UDPHS Endpoint Set Status Register */ - RwReg UDPHS_EPTCLRSTA; /**< \brief (UdphsEpt Offset: 0x18) UDPHS Endpoint Clear Status Register */ - RwReg UDPHS_EPTSTA; /**< \brief (UdphsEpt Offset: 0x1C) UDPHS Endpoint Status Register */ -} UdphsEpt; -/** \brief Udphs hardware registers */ -typedef struct { - RwReg UDPHS_CTRL; /**< \brief (Udphs Offset: 0x00) UDPHS Control Register */ - RoReg UDPHS_FNUM; /**< \brief (Udphs Offset: 0x04) UDPHS Frame Number Register */ - RwReg Reserved1[2]; - RwReg UDPHS_IEN; /**< \brief (Udphs Offset: 0x10) UDPHS Interrupt Enable Register */ - RoReg UDPHS_INTSTA; /**< \brief (Udphs Offset: 0x14) UDPHS Interrupt Status Register */ - WoReg UDPHS_CLRINT; /**< \brief (Udphs Offset: 0x18) UDPHS Clear Interrupt Register */ - WoReg UDPHS_EPTRST; /**< \brief (Udphs Offset: 0x1C) UDPHS Endpoints Reset Register */ - RwReg Reserved2[48]; - RwReg UDPHS_TST; /**< \brief (Udphs Offset: 0xE0) UDPHS Test Register */ - RwReg Reserved3[3]; - RoReg UDPHS_IPNAME1; /**< \brief (Udphs Offset: 0xF0) UDPHS Name1 Register */ - RoReg UDPHS_IPNAME2; /**< \brief (Udphs Offset: 0xF4) UDPHS Name2 Register */ - RoReg UDPHS_IPFEATURES; /**< \brief (Udphs Offset: 0xF8) UDPHS Features Register */ - RwReg Reserved4[1]; - UdphsEpt UDPHS_EPT[7]; /**< \brief (Udphs Offset: 0x100) endpoint = 0 .. 6 */ - RwReg Reserved5[80]; - UdphsDma UDPHS_DMA[5]; /**< \brief (Udphs Offset: 0x320) channel = 1 .. 5 */ -} Udphs; -#endif /* __ASSEMBLY__ */ -/* -------- UDPHS_CTRL : (UDPHS Offset: 0x00) UDPHS Control Register -------- */ -#define UDPHS_CTRL_DEV_ADDR (0x7f << 0) /**< \brief (UDPHS_CTRL) UDPHS Address */ -#define UDPHS_CTRL_FADDR_EN (0x1 << 7) /**< \brief (UDPHS_CTRL) Function Address Enable */ -#define UDPHS_CTRL_EN_UDPHS (0x1 << 8) /**< \brief (UDPHS_CTRL) UDPHS Enable */ -#define UDPHS_CTRL_DETACH (0x1 << 9) /**< \brief (UDPHS_CTRL) Detach Command */ -#define UDPHS_CTRL_REWAKEUP (0x1 << 10) /**< \brief (UDPHS_CTRL) Send Remote Wake Up */ -#define UDPHS_CTRL_PULLD_DIS (0x1 << 11) /**< \brief (UDPHS_CTRL) Pull-Down Disable */ -/* -------- UDPHS_FNUM : (UDPHS Offset: 0x04) UDPHS Frame Number Register -------- */ -#define UDPHS_FNUM_MICRO_FRAME_NUM (0x7 << 0) /**< \brief (UDPHS_FNUM) Microframe Number */ -#define UDPHS_FNUM_FRAME_NUMBER (0x7ff << 3) /**< \brief (UDPHS_FNUM) Frame Number as defined in the Packet Field Formats */ -#define UDPHS_FNUM_FNUM_ERR (0x1 << 31) /**< \brief (UDPHS_FNUM) Frame Number CRC Error */ -/* -------- UDPHS_IEN : (UDPHS Offset: 0x10) UDPHS Interrupt Enable Register -------- */ -#define UDPHS_IEN_DET_SUSPD (0x1 << 1) /**< \brief (UDPHS_IEN) Suspend Interrupt Enable */ -#define UDPHS_IEN_MICRO_SOF (0x1 << 2) /**< \brief (UDPHS_IEN) Micro-SOF Interrupt Enable */ -#define UDPHS_IEN_INT_SOF (0x1 << 3) /**< \brief (UDPHS_IEN) SOF Interrupt Enable */ -#define UDPHS_IEN_ENDRESET (0x1 << 4) /**< \brief (UDPHS_IEN) End Of Reset Interrupt Enable */ -#define UDPHS_IEN_WAKE_UP (0x1 << 5) /**< \brief (UDPHS_IEN) Wake Up CPU Interrupt Enable */ -#define UDPHS_IEN_ENDOFRSM (0x1 << 6) /**< \brief (UDPHS_IEN) End Of Resume Interrupt Enable */ -#define UDPHS_IEN_UPSTR_RES (0x1 << 7) /**< \brief (UDPHS_IEN) Upstream Resume Interrupt Enable */ -#define UDPHS_IEN_EPT_0 (0x1 << 8) /**< \brief (UDPHS_IEN) Endpoint 0 Interrupt Enable */ -#define UDPHS_IEN_EPT_1 (0x1 << 9) /**< \brief (UDPHS_IEN) Endpoint 1 Interrupt Enable */ -#define UDPHS_IEN_EPT_2 (0x1 << 10) /**< \brief (UDPHS_IEN) Endpoint 2 Interrupt Enable */ -#define UDPHS_IEN_EPT_3 (0x1 << 11) /**< \brief (UDPHS_IEN) Endpoint 3 Interrupt Enable */ -#define UDPHS_IEN_EPT_4 (0x1 << 12) /**< \brief (UDPHS_IEN) Endpoint 4 Interrupt Enable */ -#define UDPHS_IEN_EPT_5 (0x1 << 13) /**< \brief (UDPHS_IEN) Endpoint 5 Interrupt Enable */ -#define UDPHS_IEN_EPT_6 (0x1 << 14) /**< \brief (UDPHS_IEN) Endpoint 6 Interrupt Enable */ -#define UDPHS_IEN_DMA_1 (0x1 << 25) /**< \brief (UDPHS_IEN) DMA Channel 1 Interrupt Enable */ -#define UDPHS_IEN_DMA_2 (0x1 << 26) /**< \brief (UDPHS_IEN) DMA Channel 2 Interrupt Enable */ -#define UDPHS_IEN_DMA_3 (0x1 << 27) /**< \brief (UDPHS_IEN) DMA Channel 3 Interrupt Enable */ -#define UDPHS_IEN_DMA_4 (0x1 << 28) /**< \brief (UDPHS_IEN) DMA Channel 4 Interrupt Enable */ -#define UDPHS_IEN_DMA_5 (0x1 << 29) /**< \brief (UDPHS_IEN) DMA Channel 5 Interrupt Enable */ -#define UDPHS_IEN_DMA_6 (0x1 << 30) /**< \brief (UDPHS_IEN) DMA Channel 6 Interrupt Enable */ -/* -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) UDPHS Interrupt Status Register -------- */ -#define UDPHS_INTSTA_SPEED (0x1 << 0) /**< \brief (UDPHS_INTSTA) Speed Status */ -#define UDPHS_INTSTA_DET_SUSPD (0x1 << 1) /**< \brief (UDPHS_INTSTA) Suspend Interrupt */ -#define UDPHS_INTSTA_MICRO_SOF (0x1 << 2) /**< \brief (UDPHS_INTSTA) Micro Start Of Frame Interrupt */ -#define UDPHS_INTSTA_INT_SOF (0x1 << 3) /**< \brief (UDPHS_INTSTA) Start Of Frame Interrupt */ -#define UDPHS_INTSTA_ENDRESET (0x1 << 4) /**< \brief (UDPHS_INTSTA) End Of Reset Interrupt */ -#define UDPHS_INTSTA_WAKE_UP (0x1 << 5) /**< \brief (UDPHS_INTSTA) Wake Up CPU Interrupt */ -#define UDPHS_INTSTA_ENDOFRSM (0x1 << 6) /**< \brief (UDPHS_INTSTA) End Of Resume Interrupt */ -#define UDPHS_INTSTA_UPSTR_RES (0x1 << 7) /**< \brief (UDPHS_INTSTA) Upstream Resume Interrupt */ -#define UDPHS_INTSTA_EPT_0 (0x1 << 8) /**< \brief (UDPHS_INTSTA) Endpoint 0 Interrupt */ -#define UDPHS_INTSTA_EPT_1 (0x1 << 9) /**< \brief (UDPHS_INTSTA) Endpoint 1 Interrupt */ -#define UDPHS_INTSTA_EPT_2 (0x1 << 10) /**< \brief (UDPHS_INTSTA) Endpoint 2 Interrupt */ -#define UDPHS_INTSTA_EPT_3 (0x1 << 11) /**< \brief (UDPHS_INTSTA) Endpoint 3 Interrupt */ -#define UDPHS_INTSTA_EPT_4 (0x1 << 12) /**< \brief (UDPHS_INTSTA) Endpoint 4 Interrupt */ -#define UDPHS_INTSTA_EPT_5 (0x1 << 13) /**< \brief (UDPHS_INTSTA) Endpoint 5 Interrupt */ -#define UDPHS_INTSTA_EPT_6 (0x1 << 14) /**< \brief (UDPHS_INTSTA) Endpoint 6 Interrupt */ -#define UDPHS_INTSTA_DMA_1 (0x1 << 25) /**< \brief (UDPHS_INTSTA) DMA Channel 1 Interrupt */ -#define UDPHS_INTSTA_DMA_2 (0x1 << 26) /**< \brief (UDPHS_INTSTA) DMA Channel 2 Interrupt */ -#define UDPHS_INTSTA_DMA_3 (0x1 << 27) /**< \brief (UDPHS_INTSTA) DMA Channel 3 Interrupt */ -#define UDPHS_INTSTA_DMA_4 (0x1 << 28) /**< \brief (UDPHS_INTSTA) DMA Channel 4 Interrupt */ -#define UDPHS_INTSTA_DMA_5 (0x1 << 29) /**< \brief (UDPHS_INTSTA) DMA Channel 5 Interrupt */ -#define UDPHS_INTSTA_DMA_6 (0x1 << 30) /**< \brief (UDPHS_INTSTA) DMA Channel 6 Interrupt */ -/* -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) UDPHS Clear Interrupt Register -------- */ -#define UDPHS_CLRINT_DET_SUSPD (0x1 << 1) /**< \brief (UDPHS_CLRINT) Suspend Interrupt Clear */ -#define UDPHS_CLRINT_MICRO_SOF (0x1 << 2) /**< \brief (UDPHS_CLRINT) Micro Start Of Frame Interrupt Clear */ -#define UDPHS_CLRINT_INT_SOF (0x1 << 3) /**< \brief (UDPHS_CLRINT) Start Of Frame Interrupt Clear */ -#define UDPHS_CLRINT_ENDRESET (0x1 << 4) /**< \brief (UDPHS_CLRINT) End Of Reset Interrupt Clear */ -#define UDPHS_CLRINT_WAKE_UP (0x1 << 5) /**< \brief (UDPHS_CLRINT) Wake Up CPU Interrupt Clear */ -#define UDPHS_CLRINT_ENDOFRSM (0x1 << 6) /**< \brief (UDPHS_CLRINT) End Of Resume Interrupt Clear */ -#define UDPHS_CLRINT_UPSTR_RES (0x1 << 7) /**< \brief (UDPHS_CLRINT) Upstream Resume Interrupt Clear */ -/* -------- UDPHS_EPTRST : (UDPHS Offset: 0x1C) UDPHS Endpoints Reset Register -------- */ -#define UDPHS_EPTRST_EPT_0 (0x1 << 0) /**< \brief (UDPHS_EPTRST) Endpoint 0 Reset */ -#define UDPHS_EPTRST_EPT_1 (0x1 << 1) /**< \brief (UDPHS_EPTRST) Endpoint 1 Reset */ -#define UDPHS_EPTRST_EPT_2 (0x1 << 2) /**< \brief (UDPHS_EPTRST) Endpoint 2 Reset */ -#define UDPHS_EPTRST_EPT_3 (0x1 << 3) /**< \brief (UDPHS_EPTRST) Endpoint 3 Reset */ -#define UDPHS_EPTRST_EPT_4 (0x1 << 4) /**< \brief (UDPHS_EPTRST) Endpoint 4 Reset */ -#define UDPHS_EPTRST_EPT_5 (0x1 << 5) /**< \brief (UDPHS_EPTRST) Endpoint 5 Reset */ -#define UDPHS_EPTRST_EPT_6 (0x1 << 6) /**< \brief (UDPHS_EPTRST) Endpoint 6 Reset */ -/* -------- UDPHS_TST : (UDPHS Offset: 0xE0) UDPHS Test Register -------- */ -#define UDPHS_TST_SPEED_CFG (0x3 << 0) /**< \brief (UDPHS_TST) Speed Configuration */ -#define UDPHS_TST_TST_J (0x1 << 2) /**< \brief (UDPHS_TST) Test J Mode */ -#define UDPHS_TST_TST_K (0x1 << 3) /**< \brief (UDPHS_TST) Test K Mode */ -#define UDPHS_TST_TST_PKT (0x1 << 4) /**< \brief (UDPHS_TST) Test Packet Mode */ -#define UDPHS_TST_OPMODE2 (0x1 << 5) /**< \brief (UDPHS_TST) OpMode2 */ -/* -------- UDPHS_IPNAME1 : (UDPHS Offset: 0xF0) UDPHS Name1 Register -------- */ -#define UDPHS_IPNAME1_IP_NAME1 (0xffffffff << 0) /**< \brief (UDPHS_IPNAME1) */ -/* -------- UDPHS_IPNAME2 : (UDPHS Offset: 0xF4) UDPHS Name2 Register -------- */ -#define UDPHS_IPNAME2_IP_NAME2 (0xffffffff << 0) /**< \brief (UDPHS_IPNAME2) */ -/* -------- UDPHS_IPFEATURES : (UDPHS Offset: 0xF8) UDPHS Features Register -------- */ -#define UDPHS_IPFEATURES_EPT_NBR_MAX (0xf << 0) /**< \brief (UDPHS_IPFEATURES) Max Number of Endpoints */ -#define UDPHS_IPFEATURES_DMA_CHANNEL_NBR (0x7 << 4) /**< \brief (UDPHS_IPFEATURES) Number of DMA Channels */ -#define UDPHS_IPFEATURES_DMA_B_SIZ (0x1 << 7) /**< \brief (UDPHS_IPFEATURES) DMA Buffer Size */ -#define UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH (0xf << 8) /**< \brief (UDPHS_IPFEATURES) DMA FIFO Depth in Words */ -#define UDPHS_IPFEATURES_FIFO_MAX_SIZE (0x7 << 12) /**< \brief (UDPHS_IPFEATURES) DPRAM Size */ -#define UDPHS_IPFEATURES_BW_DPRAM (0x1 << 15) /**< \brief (UDPHS_IPFEATURES) DPRAM Byte Write Capability */ -#define UDPHS_IPFEATURES_DATAB16_8 (0x1 << 16) /**< \brief (UDPHS_IPFEATURES) UTMI DataBus16_8 */ -#define UDPHS_IPFEATURES_ISO_EPT_1 (0x1 << 17) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_2 (0x1 << 18) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_3 (0x1 << 19) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_4 (0x1 << 20) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_5 (0x1 << 21) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_6 (0x1 << 22) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_7 (0x1 << 23) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_8 (0x1 << 24) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_9 (0x1 << 25) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_10 (0x1 << 26) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_11 (0x1 << 27) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_12 (0x1 << 28) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_13 (0x1 << 29) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_14 (0x1 << 30) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_15 (0x1 << 31) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -/* -------- UDPHS_EPTCFG0 : (UDPHS Offset: 0x100) UDPHS Endpoint Configuration Register (endpoint = 0) -------- */ -#define UDPHS_EPTCFG0_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG0) Endpoint Size */ -#define UDPHS_EPTCFG0_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG0) 8 bytes */ -#define UDPHS_EPTCFG0_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG0) 16 bytes */ -#define UDPHS_EPTCFG0_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG0) 32 bytes */ -#define UDPHS_EPTCFG0_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG0) 64 bytes */ -#define UDPHS_EPTCFG0_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG0) 128 bytes */ -#define UDPHS_EPTCFG0_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG0) 256 bytes */ -#define UDPHS_EPTCFG0_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG0) 512 bytes */ -#define UDPHS_EPTCFG0_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG0) 1024 bytes */ -#define UDPHS_EPTCFG0_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG0) Endpoint Direction */ -#define UDPHS_EPTCFG0_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG0) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG0_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG0) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG0_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG0) Endpoint Type */ -#define UDPHS_EPTCFG0_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG0) Control endpoint */ -#define UDPHS_EPTCFG0_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG0) Isochronous endpoint */ -#define UDPHS_EPTCFG0_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG0) Bulk endpoint */ -#define UDPHS_EPTCFG0_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG0) Interrupt endpoint */ -#define UDPHS_EPTCFG0_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG0) Number of Banks */ -#define UDPHS_EPTCFG0_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG0) Zero bank, the endpoint is not mapped in memory */ -#define UDPHS_EPTCFG0_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG0) One bank (bank 0) */ -#define UDPHS_EPTCFG0_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG0) Double bank (Ping-Pong: bank 0/bank 1) */ -#define UDPHS_EPTCFG0_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG0) Triple bank (bank 0/bank 1/bank 2) */ -#define UDPHS_EPTCFG0_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG0) Number Of Transaction per Microframe */ -#define UDPHS_EPTCFG0_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG0) Endpoint Mapped */ -/* -------- UDPHS_EPTCTLENB0 : (UDPHS Offset: 0x104) UDPHS Endpoint Control Enable Register (endpoint = 0) -------- */ -#define UDPHS_EPTCTLENB0_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB0) Endpoint Enable */ -#define UDPHS_EPTCTLENB0_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB0) Packet Auto-Valid Enable */ -#define UDPHS_EPTCTLENB0_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB0) Interrupts Disable DMA */ -#define UDPHS_EPTCTLENB0_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB0) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLENB0_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB0) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB0_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB0) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB0_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB0) Overflow Error Interrupt Enable */ -#define UDPHS_EPTCTLENB0_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB0) Received OUT Data Interrupt Enable */ -#define UDPHS_EPTCTLENB0_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB0) Transmitted IN Data Complete Interrupt Enable */ -#define UDPHS_EPTCTLENB0_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB0) TX Packet Ready/Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB0_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB0) Received SETUP/Error Flow Interrupt Enable */ -#define UDPHS_EPTCTLENB0_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB0) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB0_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB0) NAKIN/Bank Flush Error Interrupt Enable */ -#define UDPHS_EPTCTLENB0_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB0) NAKOUT Interrupt Enable */ -#define UDPHS_EPTCTLENB0_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB0) Busy Bank Interrupt Enable */ -#define UDPHS_EPTCTLENB0_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB0) Short Packet Send/Short Packet Interrupt Enable */ -/* -------- UDPHS_EPTCTLDIS0 : (UDPHS Offset: 0x108) UDPHS Endpoint Control Disable Register (endpoint = 0) -------- */ -#define UDPHS_EPTCTLDIS0_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS0) Endpoint Disable */ -#define UDPHS_EPTCTLDIS0_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS0) Packet Auto-Valid Disable */ -#define UDPHS_EPTCTLDIS0_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS0) Interrupts Disable DMA */ -#define UDPHS_EPTCTLDIS0_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS0) NYET Enable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLDIS0_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS0) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS0_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS0) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS0_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS0) Overflow Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS0) Received OUT Data Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS0) Transmitted IN Data Complete Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS0) TX Packet Ready/Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS0) Received SETUP/Error Flow Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS0) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS0) NAKIN/bank flush error Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS0) NAKOUT Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS0) Busy Bank Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS0) Short Packet Interrupt Disable */ -/* -------- UDPHS_EPTCTL0 : (UDPHS Offset: 0x10C) UDPHS Endpoint Control Register (endpoint = 0) -------- */ -#define UDPHS_EPTCTL0_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL0) Endpoint Enable */ -#define UDPHS_EPTCTL0_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL0) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */ -#define UDPHS_EPTCTL0_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL0) Interrupt Disables DMA */ -#define UDPHS_EPTCTL0_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL0) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTL0_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL0) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL0_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL0) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL0_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL0) Overflow Error Interrupt Enabled */ -#define UDPHS_EPTCTL0_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL0) Received OUT Data Interrupt Enabled */ -#define UDPHS_EPTCTL0_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL0) Transmitted IN Data Complete Interrupt Enabled */ -#define UDPHS_EPTCTL0_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL0) TX Packet Ready/Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL0_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL0) Received SETUP/Error Flow Interrupt Enabled */ -#define UDPHS_EPTCTL0_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL0) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL0_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL0) NAKIN/Bank Flush Error Interrupt Enabled */ -#define UDPHS_EPTCTL0_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL0) NAKOUT Interrupt Enabled */ -#define UDPHS_EPTCTL0_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL0) Busy Bank Interrupt Enabled */ -#define UDPHS_EPTCTL0_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL0) Short Packet Interrupt Enabled */ -/* -------- UDPHS_EPTSETSTA0 : (UDPHS Offset: 0x114) UDPHS Endpoint Set Status Register (endpoint = 0) -------- */ -#define UDPHS_EPTSETSTA0_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA0) Stall Handshake Request Set */ -#define UDPHS_EPTSETSTA0_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA0) KILL Bank Set (for IN Endpoint) */ -#define UDPHS_EPTSETSTA0_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA0) TX Packet Ready Set */ -/* -------- UDPHS_EPTCLRSTA0 : (UDPHS Offset: 0x118) UDPHS Endpoint Clear Status Register (endpoint = 0) -------- */ -#define UDPHS_EPTCLRSTA0_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA0) Stall Handshake Request Clear */ -#define UDPHS_EPTCLRSTA0_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA0) Data Toggle Clear */ -#define UDPHS_EPTCLRSTA0_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA0) Received OUT Data Clear */ -#define UDPHS_EPTCLRSTA0_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA0) Transmitted IN Data Complete Clear */ -#define UDPHS_EPTCLRSTA0_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA0) Received SETUP/Error Flow Clear */ -#define UDPHS_EPTCLRSTA0_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA0) Stall Sent/Number of Transaction Error Clear */ -#define UDPHS_EPTCLRSTA0_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA0) NAKIN/Bank Flush Error Clear */ -#define UDPHS_EPTCLRSTA0_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA0) NAKOUT Clear */ -/* -------- UDPHS_EPTSTA0 : (UDPHS Offset: 0x11C) UDPHS Endpoint Status Register (endpoint = 0) -------- */ -#define UDPHS_EPTSTA0_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA0) Stall Handshake Request */ -#define UDPHS_EPTSTA0_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA0) Toggle Sequencing */ -#define UDPHS_EPTSTA0_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA0) Overflow Error */ -#define UDPHS_EPTSTA0_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA0) Received OUT Data/KILL Bank */ -#define UDPHS_EPTSTA0_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA0) Transmitted IN Data Complete */ -#define UDPHS_EPTSTA0_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA0) TX Packet Ready/Transaction Error */ -#define UDPHS_EPTSTA0_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA0) Received SETUP/Error Flow */ -#define UDPHS_EPTSTA0_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA0) Stall Sent/CRC ISO Error/Number of Transaction Error */ -#define UDPHS_EPTSTA0_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA0) NAK IN/Bank Flush Error */ -#define UDPHS_EPTSTA0_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA0) NAK OUT */ -#define UDPHS_EPTSTA0_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA0) Current Bank/Control Direction */ -#define UDPHS_EPTSTA0_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA0) Busy Bank Number */ -#define UDPHS_EPTSTA0_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA0) UDPHS Byte Count */ -#define UDPHS_EPTSTA0_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA0) Short Packet */ -/* -------- UDPHS_EPTCFG1 : (UDPHS Offset: 0x120) UDPHS Endpoint Configuration Register (endpoint = 1) -------- */ -#define UDPHS_EPTCFG1_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG1) Endpoint Size */ -#define UDPHS_EPTCFG1_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG1) 8 bytes */ -#define UDPHS_EPTCFG1_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG1) 16 bytes */ -#define UDPHS_EPTCFG1_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG1) 32 bytes */ -#define UDPHS_EPTCFG1_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG1) 64 bytes */ -#define UDPHS_EPTCFG1_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG1) 128 bytes */ -#define UDPHS_EPTCFG1_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG1) 256 bytes */ -#define UDPHS_EPTCFG1_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG1) 512 bytes */ -#define UDPHS_EPTCFG1_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG1) 1024 bytes */ -#define UDPHS_EPTCFG1_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG1) Endpoint Direction */ -#define UDPHS_EPTCFG1_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG1) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG1_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG1) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG1_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG1) Endpoint Type */ -#define UDPHS_EPTCFG1_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG1) Control endpoint */ -#define UDPHS_EPTCFG1_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG1) Isochronous endpoint */ -#define UDPHS_EPTCFG1_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG1) Bulk endpoint */ -#define UDPHS_EPTCFG1_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG1) Interrupt endpoint */ -#define UDPHS_EPTCFG1_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG1) Number of Banks */ -#define UDPHS_EPTCFG1_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG1) Zero bank, the endpoint is not mapped in memory */ -#define UDPHS_EPTCFG1_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG1) One bank (bank 0) */ -#define UDPHS_EPTCFG1_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG1) Double bank (Ping-Pong: bank 0/bank 1) */ -#define UDPHS_EPTCFG1_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG1) Triple bank (bank 0/bank 1/bank 2) */ -#define UDPHS_EPTCFG1_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG1) Number Of Transaction per Microframe */ -#define UDPHS_EPTCFG1_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG1) Endpoint Mapped */ -/* -------- UDPHS_EPTCTLENB1 : (UDPHS Offset: 0x124) UDPHS Endpoint Control Enable Register (endpoint = 1) -------- */ -#define UDPHS_EPTCTLENB1_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB1) Endpoint Enable */ -#define UDPHS_EPTCTLENB1_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB1) Packet Auto-Valid Enable */ -#define UDPHS_EPTCTLENB1_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB1) Interrupts Disable DMA */ -#define UDPHS_EPTCTLENB1_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB1) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLENB1_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB1) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB1_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB1) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB1_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB1) Overflow Error Interrupt Enable */ -#define UDPHS_EPTCTLENB1_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB1) Received OUT Data Interrupt Enable */ -#define UDPHS_EPTCTLENB1_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB1) Transmitted IN Data Complete Interrupt Enable */ -#define UDPHS_EPTCTLENB1_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB1) TX Packet Ready/Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB1_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB1) Received SETUP/Error Flow Interrupt Enable */ -#define UDPHS_EPTCTLENB1_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB1) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB1_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB1) NAKIN/Bank Flush Error Interrupt Enable */ -#define UDPHS_EPTCTLENB1_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB1) NAKOUT Interrupt Enable */ -#define UDPHS_EPTCTLENB1_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB1) Busy Bank Interrupt Enable */ -#define UDPHS_EPTCTLENB1_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB1) Short Packet Send/Short Packet Interrupt Enable */ -/* -------- UDPHS_EPTCTLDIS1 : (UDPHS Offset: 0x128) UDPHS Endpoint Control Disable Register (endpoint = 1) -------- */ -#define UDPHS_EPTCTLDIS1_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS1) Endpoint Disable */ -#define UDPHS_EPTCTLDIS1_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS1) Packet Auto-Valid Disable */ -#define UDPHS_EPTCTLDIS1_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS1) Interrupts Disable DMA */ -#define UDPHS_EPTCTLDIS1_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS1) NYET Enable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLDIS1_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS1) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS1_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS1) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS1_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS1) Overflow Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS1) Received OUT Data Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS1) Transmitted IN Data Complete Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS1) TX Packet Ready/Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS1) Received SETUP/Error Flow Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS1) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS1) NAKIN/bank flush error Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS1) NAKOUT Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS1) Busy Bank Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS1) Short Packet Interrupt Disable */ -/* -------- UDPHS_EPTCTL1 : (UDPHS Offset: 0x12C) UDPHS Endpoint Control Register (endpoint = 1) -------- */ -#define UDPHS_EPTCTL1_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL1) Endpoint Enable */ -#define UDPHS_EPTCTL1_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL1) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */ -#define UDPHS_EPTCTL1_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL1) Interrupt Disables DMA */ -#define UDPHS_EPTCTL1_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL1) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTL1_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL1) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL1_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL1) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL1_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL1) Overflow Error Interrupt Enabled */ -#define UDPHS_EPTCTL1_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL1) Received OUT Data Interrupt Enabled */ -#define UDPHS_EPTCTL1_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL1) Transmitted IN Data Complete Interrupt Enabled */ -#define UDPHS_EPTCTL1_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL1) TX Packet Ready/Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL1_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL1) Received SETUP/Error Flow Interrupt Enabled */ -#define UDPHS_EPTCTL1_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL1) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL1_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL1) NAKIN/Bank Flush Error Interrupt Enabled */ -#define UDPHS_EPTCTL1_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL1) NAKOUT Interrupt Enabled */ -#define UDPHS_EPTCTL1_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL1) Busy Bank Interrupt Enabled */ -#define UDPHS_EPTCTL1_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL1) Short Packet Interrupt Enabled */ -/* -------- UDPHS_EPTSETSTA1 : (UDPHS Offset: 0x134) UDPHS Endpoint Set Status Register (endpoint = 1) -------- */ -#define UDPHS_EPTSETSTA1_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA1) Stall Handshake Request Set */ -#define UDPHS_EPTSETSTA1_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA1) KILL Bank Set (for IN Endpoint) */ -#define UDPHS_EPTSETSTA1_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA1) TX Packet Ready Set */ -/* -------- UDPHS_EPTCLRSTA1 : (UDPHS Offset: 0x138) UDPHS Endpoint Clear Status Register (endpoint = 1) -------- */ -#define UDPHS_EPTCLRSTA1_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA1) Stall Handshake Request Clear */ -#define UDPHS_EPTCLRSTA1_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA1) Data Toggle Clear */ -#define UDPHS_EPTCLRSTA1_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA1) Received OUT Data Clear */ -#define UDPHS_EPTCLRSTA1_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA1) Transmitted IN Data Complete Clear */ -#define UDPHS_EPTCLRSTA1_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA1) Received SETUP/Error Flow Clear */ -#define UDPHS_EPTCLRSTA1_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA1) Stall Sent/Number of Transaction Error Clear */ -#define UDPHS_EPTCLRSTA1_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA1) NAKIN/Bank Flush Error Clear */ -#define UDPHS_EPTCLRSTA1_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA1) NAKOUT Clear */ -/* -------- UDPHS_EPTSTA1 : (UDPHS Offset: 0x13C) UDPHS Endpoint Status Register (endpoint = 1) -------- */ -#define UDPHS_EPTSTA1_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA1) Stall Handshake Request */ -#define UDPHS_EPTSTA1_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA1) Toggle Sequencing */ -#define UDPHS_EPTSTA1_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA1) Overflow Error */ -#define UDPHS_EPTSTA1_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA1) Received OUT Data/KILL Bank */ -#define UDPHS_EPTSTA1_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA1) Transmitted IN Data Complete */ -#define UDPHS_EPTSTA1_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA1) TX Packet Ready/Transaction Error */ -#define UDPHS_EPTSTA1_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA1) Received SETUP/Error Flow */ -#define UDPHS_EPTSTA1_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA1) Stall Sent/CRC ISO Error/Number of Transaction Error */ -#define UDPHS_EPTSTA1_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA1) NAK IN/Bank Flush Error */ -#define UDPHS_EPTSTA1_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA1) NAK OUT */ -#define UDPHS_EPTSTA1_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA1) Current Bank/Control Direction */ -#define UDPHS_EPTSTA1_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA1) Busy Bank Number */ -#define UDPHS_EPTSTA1_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA1) UDPHS Byte Count */ -#define UDPHS_EPTSTA1_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA1) Short Packet */ -/* -------- UDPHS_EPTCFG2 : (UDPHS Offset: 0x140) UDPHS Endpoint Configuration Register (endpoint = 2) -------- */ -#define UDPHS_EPTCFG2_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG2) Endpoint Size */ -#define UDPHS_EPTCFG2_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG2) 8 bytes */ -#define UDPHS_EPTCFG2_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG2) 16 bytes */ -#define UDPHS_EPTCFG2_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG2) 32 bytes */ -#define UDPHS_EPTCFG2_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG2) 64 bytes */ -#define UDPHS_EPTCFG2_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG2) 128 bytes */ -#define UDPHS_EPTCFG2_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG2) 256 bytes */ -#define UDPHS_EPTCFG2_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG2) 512 bytes */ -#define UDPHS_EPTCFG2_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG2) 1024 bytes */ -#define UDPHS_EPTCFG2_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG2) Endpoint Direction */ -#define UDPHS_EPTCFG2_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG2) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG2_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG2) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG2_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG2) Endpoint Type */ -#define UDPHS_EPTCFG2_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG2) Control endpoint */ -#define UDPHS_EPTCFG2_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG2) Isochronous endpoint */ -#define UDPHS_EPTCFG2_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG2) Bulk endpoint */ -#define UDPHS_EPTCFG2_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG2) Interrupt endpoint */ -#define UDPHS_EPTCFG2_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG2) Number of Banks */ -#define UDPHS_EPTCFG2_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG2) Zero bank, the endpoint is not mapped in memory */ -#define UDPHS_EPTCFG2_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG2) One bank (bank 0) */ -#define UDPHS_EPTCFG2_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG2) Double bank (Ping-Pong: bank 0/bank 1) */ -#define UDPHS_EPTCFG2_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG2) Triple bank (bank 0/bank 1/bank 2) */ -#define UDPHS_EPTCFG2_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG2) Number Of Transaction per Microframe */ -#define UDPHS_EPTCFG2_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG2) Endpoint Mapped */ -/* -------- UDPHS_EPTCTLENB2 : (UDPHS Offset: 0x144) UDPHS Endpoint Control Enable Register (endpoint = 2) -------- */ -#define UDPHS_EPTCTLENB2_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB2) Endpoint Enable */ -#define UDPHS_EPTCTLENB2_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB2) Packet Auto-Valid Enable */ -#define UDPHS_EPTCTLENB2_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB2) Interrupts Disable DMA */ -#define UDPHS_EPTCTLENB2_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB2) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLENB2_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB2) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB2_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB2) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB2_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB2) Overflow Error Interrupt Enable */ -#define UDPHS_EPTCTLENB2_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB2) Received OUT Data Interrupt Enable */ -#define UDPHS_EPTCTLENB2_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB2) Transmitted IN Data Complete Interrupt Enable */ -#define UDPHS_EPTCTLENB2_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB2) TX Packet Ready/Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB2_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB2) Received SETUP/Error Flow Interrupt Enable */ -#define UDPHS_EPTCTLENB2_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB2) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB2_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB2) NAKIN/Bank Flush Error Interrupt Enable */ -#define UDPHS_EPTCTLENB2_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB2) NAKOUT Interrupt Enable */ -#define UDPHS_EPTCTLENB2_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB2) Busy Bank Interrupt Enable */ -#define UDPHS_EPTCTLENB2_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB2) Short Packet Send/Short Packet Interrupt Enable */ -/* -------- UDPHS_EPTCTLDIS2 : (UDPHS Offset: 0x148) UDPHS Endpoint Control Disable Register (endpoint = 2) -------- */ -#define UDPHS_EPTCTLDIS2_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS2) Endpoint Disable */ -#define UDPHS_EPTCTLDIS2_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS2) Packet Auto-Valid Disable */ -#define UDPHS_EPTCTLDIS2_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS2) Interrupts Disable DMA */ -#define UDPHS_EPTCTLDIS2_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS2) NYET Enable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLDIS2_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS2) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS2_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS2) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS2_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS2) Overflow Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS2) Received OUT Data Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS2) Transmitted IN Data Complete Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS2) TX Packet Ready/Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS2) Received SETUP/Error Flow Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS2) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS2) NAKIN/bank flush error Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS2) NAKOUT Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS2) Busy Bank Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS2) Short Packet Interrupt Disable */ -/* -------- UDPHS_EPTCTL2 : (UDPHS Offset: 0x14C) UDPHS Endpoint Control Register (endpoint = 2) -------- */ -#define UDPHS_EPTCTL2_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL2) Endpoint Enable */ -#define UDPHS_EPTCTL2_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL2) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */ -#define UDPHS_EPTCTL2_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL2) Interrupt Disables DMA */ -#define UDPHS_EPTCTL2_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL2) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTL2_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL2) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL2_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL2) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL2_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL2) Overflow Error Interrupt Enabled */ -#define UDPHS_EPTCTL2_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL2) Received OUT Data Interrupt Enabled */ -#define UDPHS_EPTCTL2_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL2) Transmitted IN Data Complete Interrupt Enabled */ -#define UDPHS_EPTCTL2_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL2) TX Packet Ready/Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL2_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL2) Received SETUP/Error Flow Interrupt Enabled */ -#define UDPHS_EPTCTL2_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL2) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL2_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL2) NAKIN/Bank Flush Error Interrupt Enabled */ -#define UDPHS_EPTCTL2_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL2) NAKOUT Interrupt Enabled */ -#define UDPHS_EPTCTL2_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL2) Busy Bank Interrupt Enabled */ -#define UDPHS_EPTCTL2_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL2) Short Packet Interrupt Enabled */ -/* -------- UDPHS_EPTSETSTA2 : (UDPHS Offset: 0x154) UDPHS Endpoint Set Status Register (endpoint = 2) -------- */ -#define UDPHS_EPTSETSTA2_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA2) Stall Handshake Request Set */ -#define UDPHS_EPTSETSTA2_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA2) KILL Bank Set (for IN Endpoint) */ -#define UDPHS_EPTSETSTA2_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA2) TX Packet Ready Set */ -/* -------- UDPHS_EPTCLRSTA2 : (UDPHS Offset: 0x158) UDPHS Endpoint Clear Status Register (endpoint = 2) -------- */ -#define UDPHS_EPTCLRSTA2_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA2) Stall Handshake Request Clear */ -#define UDPHS_EPTCLRSTA2_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA2) Data Toggle Clear */ -#define UDPHS_EPTCLRSTA2_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA2) Received OUT Data Clear */ -#define UDPHS_EPTCLRSTA2_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA2) Transmitted IN Data Complete Clear */ -#define UDPHS_EPTCLRSTA2_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA2) Received SETUP/Error Flow Clear */ -#define UDPHS_EPTCLRSTA2_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA2) Stall Sent/Number of Transaction Error Clear */ -#define UDPHS_EPTCLRSTA2_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA2) NAKIN/Bank Flush Error Clear */ -#define UDPHS_EPTCLRSTA2_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA2) NAKOUT Clear */ -/* -------- UDPHS_EPTSTA2 : (UDPHS Offset: 0x15C) UDPHS Endpoint Status Register (endpoint = 2) -------- */ -#define UDPHS_EPTSTA2_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA2) Stall Handshake Request */ -#define UDPHS_EPTSTA2_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA2) Toggle Sequencing */ -#define UDPHS_EPTSTA2_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA2) Overflow Error */ -#define UDPHS_EPTSTA2_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA2) Received OUT Data/KILL Bank */ -#define UDPHS_EPTSTA2_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA2) Transmitted IN Data Complete */ -#define UDPHS_EPTSTA2_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA2) TX Packet Ready/Transaction Error */ -#define UDPHS_EPTSTA2_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA2) Received SETUP/Error Flow */ -#define UDPHS_EPTSTA2_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA2) Stall Sent/CRC ISO Error/Number of Transaction Error */ -#define UDPHS_EPTSTA2_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA2) NAK IN/Bank Flush Error */ -#define UDPHS_EPTSTA2_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA2) NAK OUT */ -#define UDPHS_EPTSTA2_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA2) Current Bank/Control Direction */ -#define UDPHS_EPTSTA2_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA2) Busy Bank Number */ -#define UDPHS_EPTSTA2_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA2) UDPHS Byte Count */ -#define UDPHS_EPTSTA2_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA2) Short Packet */ -/* -------- UDPHS_EPTCFG3 : (UDPHS Offset: 0x160) UDPHS Endpoint Configuration Register (endpoint = 3) -------- */ -#define UDPHS_EPTCFG3_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG3) Endpoint Size */ -#define UDPHS_EPTCFG3_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG3) 8 bytes */ -#define UDPHS_EPTCFG3_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG3) 16 bytes */ -#define UDPHS_EPTCFG3_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG3) 32 bytes */ -#define UDPHS_EPTCFG3_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG3) 64 bytes */ -#define UDPHS_EPTCFG3_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG3) 128 bytes */ -#define UDPHS_EPTCFG3_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG3) 256 bytes */ -#define UDPHS_EPTCFG3_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG3) 512 bytes */ -#define UDPHS_EPTCFG3_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG3) 1024 bytes */ -#define UDPHS_EPTCFG3_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG3) Endpoint Direction */ -#define UDPHS_EPTCFG3_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG3) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG3_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG3) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG3_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG3) Endpoint Type */ -#define UDPHS_EPTCFG3_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG3) Control endpoint */ -#define UDPHS_EPTCFG3_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG3) Isochronous endpoint */ -#define UDPHS_EPTCFG3_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG3) Bulk endpoint */ -#define UDPHS_EPTCFG3_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG3) Interrupt endpoint */ -#define UDPHS_EPTCFG3_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG3) Number of Banks */ -#define UDPHS_EPTCFG3_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG3) Zero bank, the endpoint is not mapped in memory */ -#define UDPHS_EPTCFG3_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG3) One bank (bank 0) */ -#define UDPHS_EPTCFG3_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG3) Double bank (Ping-Pong: bank 0/bank 1) */ -#define UDPHS_EPTCFG3_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG3) Triple bank (bank 0/bank 1/bank 2) */ -#define UDPHS_EPTCFG3_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG3) Number Of Transaction per Microframe */ -#define UDPHS_EPTCFG3_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG3) Endpoint Mapped */ -/* -------- UDPHS_EPTCTLENB3 : (UDPHS Offset: 0x164) UDPHS Endpoint Control Enable Register (endpoint = 3) -------- */ -#define UDPHS_EPTCTLENB3_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB3) Endpoint Enable */ -#define UDPHS_EPTCTLENB3_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB3) Packet Auto-Valid Enable */ -#define UDPHS_EPTCTLENB3_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB3) Interrupts Disable DMA */ -#define UDPHS_EPTCTLENB3_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB3) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLENB3_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB3) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB3_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB3) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB3_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB3) Overflow Error Interrupt Enable */ -#define UDPHS_EPTCTLENB3_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB3) Received OUT Data Interrupt Enable */ -#define UDPHS_EPTCTLENB3_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB3) Transmitted IN Data Complete Interrupt Enable */ -#define UDPHS_EPTCTLENB3_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB3) TX Packet Ready/Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB3_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB3) Received SETUP/Error Flow Interrupt Enable */ -#define UDPHS_EPTCTLENB3_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB3) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB3_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB3) NAKIN/Bank Flush Error Interrupt Enable */ -#define UDPHS_EPTCTLENB3_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB3) NAKOUT Interrupt Enable */ -#define UDPHS_EPTCTLENB3_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB3) Busy Bank Interrupt Enable */ -#define UDPHS_EPTCTLENB3_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB3) Short Packet Send/Short Packet Interrupt Enable */ -/* -------- UDPHS_EPTCTLDIS3 : (UDPHS Offset: 0x168) UDPHS Endpoint Control Disable Register (endpoint = 3) -------- */ -#define UDPHS_EPTCTLDIS3_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS3) Endpoint Disable */ -#define UDPHS_EPTCTLDIS3_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS3) Packet Auto-Valid Disable */ -#define UDPHS_EPTCTLDIS3_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS3) Interrupts Disable DMA */ -#define UDPHS_EPTCTLDIS3_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS3) NYET Enable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLDIS3_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS3) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS3_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS3) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS3_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS3) Overflow Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS3) Received OUT Data Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS3) Transmitted IN Data Complete Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS3) TX Packet Ready/Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS3) Received SETUP/Error Flow Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS3) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS3) NAKIN/bank flush error Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS3) NAKOUT Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS3) Busy Bank Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS3) Short Packet Interrupt Disable */ -/* -------- UDPHS_EPTCTL3 : (UDPHS Offset: 0x16C) UDPHS Endpoint Control Register (endpoint = 3) -------- */ -#define UDPHS_EPTCTL3_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL3) Endpoint Enable */ -#define UDPHS_EPTCTL3_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL3) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */ -#define UDPHS_EPTCTL3_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL3) Interrupt Disables DMA */ -#define UDPHS_EPTCTL3_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL3) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTL3_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL3) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL3_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL3) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL3_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL3) Overflow Error Interrupt Enabled */ -#define UDPHS_EPTCTL3_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL3) Received OUT Data Interrupt Enabled */ -#define UDPHS_EPTCTL3_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL3) Transmitted IN Data Complete Interrupt Enabled */ -#define UDPHS_EPTCTL3_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL3) TX Packet Ready/Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL3_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL3) Received SETUP/Error Flow Interrupt Enabled */ -#define UDPHS_EPTCTL3_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL3) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL3_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL3) NAKIN/Bank Flush Error Interrupt Enabled */ -#define UDPHS_EPTCTL3_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL3) NAKOUT Interrupt Enabled */ -#define UDPHS_EPTCTL3_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL3) Busy Bank Interrupt Enabled */ -#define UDPHS_EPTCTL3_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL3) Short Packet Interrupt Enabled */ -/* -------- UDPHS_EPTSETSTA3 : (UDPHS Offset: 0x174) UDPHS Endpoint Set Status Register (endpoint = 3) -------- */ -#define UDPHS_EPTSETSTA3_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA3) Stall Handshake Request Set */ -#define UDPHS_EPTSETSTA3_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA3) KILL Bank Set (for IN Endpoint) */ -#define UDPHS_EPTSETSTA3_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA3) TX Packet Ready Set */ -/* -------- UDPHS_EPTCLRSTA3 : (UDPHS Offset: 0x178) UDPHS Endpoint Clear Status Register (endpoint = 3) -------- */ -#define UDPHS_EPTCLRSTA3_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA3) Stall Handshake Request Clear */ -#define UDPHS_EPTCLRSTA3_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA3) Data Toggle Clear */ -#define UDPHS_EPTCLRSTA3_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA3) Received OUT Data Clear */ -#define UDPHS_EPTCLRSTA3_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA3) Transmitted IN Data Complete Clear */ -#define UDPHS_EPTCLRSTA3_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA3) Received SETUP/Error Flow Clear */ -#define UDPHS_EPTCLRSTA3_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA3) Stall Sent/Number of Transaction Error Clear */ -#define UDPHS_EPTCLRSTA3_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA3) NAKIN/Bank Flush Error Clear */ -#define UDPHS_EPTCLRSTA3_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA3) NAKOUT Clear */ -/* -------- UDPHS_EPTSTA3 : (UDPHS Offset: 0x17C) UDPHS Endpoint Status Register (endpoint = 3) -------- */ -#define UDPHS_EPTSTA3_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA3) Stall Handshake Request */ -#define UDPHS_EPTSTA3_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA3) Toggle Sequencing */ -#define UDPHS_EPTSTA3_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA3) Overflow Error */ -#define UDPHS_EPTSTA3_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA3) Received OUT Data/KILL Bank */ -#define UDPHS_EPTSTA3_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA3) Transmitted IN Data Complete */ -#define UDPHS_EPTSTA3_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA3) TX Packet Ready/Transaction Error */ -#define UDPHS_EPTSTA3_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA3) Received SETUP/Error Flow */ -#define UDPHS_EPTSTA3_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA3) Stall Sent/CRC ISO Error/Number of Transaction Error */ -#define UDPHS_EPTSTA3_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA3) NAK IN/Bank Flush Error */ -#define UDPHS_EPTSTA3_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA3) NAK OUT */ -#define UDPHS_EPTSTA3_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA3) Current Bank/Control Direction */ -#define UDPHS_EPTSTA3_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA3) Busy Bank Number */ -#define UDPHS_EPTSTA3_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA3) UDPHS Byte Count */ -#define UDPHS_EPTSTA3_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA3) Short Packet */ -/* -------- UDPHS_EPTCFG4 : (UDPHS Offset: 0x180) UDPHS Endpoint Configuration Register (endpoint = 4) -------- */ -#define UDPHS_EPTCFG4_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG4) Endpoint Size */ -#define UDPHS_EPTCFG4_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG4) 8 bytes */ -#define UDPHS_EPTCFG4_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG4) 16 bytes */ -#define UDPHS_EPTCFG4_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG4) 32 bytes */ -#define UDPHS_EPTCFG4_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG4) 64 bytes */ -#define UDPHS_EPTCFG4_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG4) 128 bytes */ -#define UDPHS_EPTCFG4_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG4) 256 bytes */ -#define UDPHS_EPTCFG4_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG4) 512 bytes */ -#define UDPHS_EPTCFG4_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG4) 1024 bytes */ -#define UDPHS_EPTCFG4_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG4) Endpoint Direction */ -#define UDPHS_EPTCFG4_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG4) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG4_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG4) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG4_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG4) Endpoint Type */ -#define UDPHS_EPTCFG4_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG4) Control endpoint */ -#define UDPHS_EPTCFG4_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG4) Isochronous endpoint */ -#define UDPHS_EPTCFG4_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG4) Bulk endpoint */ -#define UDPHS_EPTCFG4_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG4) Interrupt endpoint */ -#define UDPHS_EPTCFG4_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG4) Number of Banks */ -#define UDPHS_EPTCFG4_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG4) Zero bank, the endpoint is not mapped in memory */ -#define UDPHS_EPTCFG4_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG4) One bank (bank 0) */ -#define UDPHS_EPTCFG4_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG4) Double bank (Ping-Pong: bank 0/bank 1) */ -#define UDPHS_EPTCFG4_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG4) Triple bank (bank 0/bank 1/bank 2) */ -#define UDPHS_EPTCFG4_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG4) Number Of Transaction per Microframe */ -#define UDPHS_EPTCFG4_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG4) Endpoint Mapped */ -/* -------- UDPHS_EPTCTLENB4 : (UDPHS Offset: 0x184) UDPHS Endpoint Control Enable Register (endpoint = 4) -------- */ -#define UDPHS_EPTCTLENB4_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB4) Endpoint Enable */ -#define UDPHS_EPTCTLENB4_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB4) Packet Auto-Valid Enable */ -#define UDPHS_EPTCTLENB4_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB4) Interrupts Disable DMA */ -#define UDPHS_EPTCTLENB4_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB4) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLENB4_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB4) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB4_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB4) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB4_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB4) Overflow Error Interrupt Enable */ -#define UDPHS_EPTCTLENB4_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB4) Received OUT Data Interrupt Enable */ -#define UDPHS_EPTCTLENB4_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB4) Transmitted IN Data Complete Interrupt Enable */ -#define UDPHS_EPTCTLENB4_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB4) TX Packet Ready/Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB4_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB4) Received SETUP/Error Flow Interrupt Enable */ -#define UDPHS_EPTCTLENB4_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB4) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB4_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB4) NAKIN/Bank Flush Error Interrupt Enable */ -#define UDPHS_EPTCTLENB4_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB4) NAKOUT Interrupt Enable */ -#define UDPHS_EPTCTLENB4_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB4) Busy Bank Interrupt Enable */ -#define UDPHS_EPTCTLENB4_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB4) Short Packet Send/Short Packet Interrupt Enable */ -/* -------- UDPHS_EPTCTLDIS4 : (UDPHS Offset: 0x188) UDPHS Endpoint Control Disable Register (endpoint = 4) -------- */ -#define UDPHS_EPTCTLDIS4_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS4) Endpoint Disable */ -#define UDPHS_EPTCTLDIS4_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS4) Packet Auto-Valid Disable */ -#define UDPHS_EPTCTLDIS4_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS4) Interrupts Disable DMA */ -#define UDPHS_EPTCTLDIS4_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS4) NYET Enable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLDIS4_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS4) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS4_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS4) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS4_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS4) Overflow Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS4) Received OUT Data Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS4) Transmitted IN Data Complete Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS4) TX Packet Ready/Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS4) Received SETUP/Error Flow Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS4) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS4) NAKIN/bank flush error Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS4) NAKOUT Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS4) Busy Bank Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS4) Short Packet Interrupt Disable */ -/* -------- UDPHS_EPTCTL4 : (UDPHS Offset: 0x18C) UDPHS Endpoint Control Register (endpoint = 4) -------- */ -#define UDPHS_EPTCTL4_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL4) Endpoint Enable */ -#define UDPHS_EPTCTL4_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL4) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */ -#define UDPHS_EPTCTL4_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL4) Interrupt Disables DMA */ -#define UDPHS_EPTCTL4_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL4) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTL4_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL4) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL4_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL4) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL4_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL4) Overflow Error Interrupt Enabled */ -#define UDPHS_EPTCTL4_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL4) Received OUT Data Interrupt Enabled */ -#define UDPHS_EPTCTL4_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL4) Transmitted IN Data Complete Interrupt Enabled */ -#define UDPHS_EPTCTL4_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL4) TX Packet Ready/Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL4_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL4) Received SETUP/Error Flow Interrupt Enabled */ -#define UDPHS_EPTCTL4_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL4) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL4_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL4) NAKIN/Bank Flush Error Interrupt Enabled */ -#define UDPHS_EPTCTL4_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL4) NAKOUT Interrupt Enabled */ -#define UDPHS_EPTCTL4_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL4) Busy Bank Interrupt Enabled */ -#define UDPHS_EPTCTL4_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL4) Short Packet Interrupt Enabled */ -/* -------- UDPHS_EPTSETSTA4 : (UDPHS Offset: 0x194) UDPHS Endpoint Set Status Register (endpoint = 4) -------- */ -#define UDPHS_EPTSETSTA4_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA4) Stall Handshake Request Set */ -#define UDPHS_EPTSETSTA4_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA4) KILL Bank Set (for IN Endpoint) */ -#define UDPHS_EPTSETSTA4_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA4) TX Packet Ready Set */ -/* -------- UDPHS_EPTCLRSTA4 : (UDPHS Offset: 0x198) UDPHS Endpoint Clear Status Register (endpoint = 4) -------- */ -#define UDPHS_EPTCLRSTA4_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA4) Stall Handshake Request Clear */ -#define UDPHS_EPTCLRSTA4_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA4) Data Toggle Clear */ -#define UDPHS_EPTCLRSTA4_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA4) Received OUT Data Clear */ -#define UDPHS_EPTCLRSTA4_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA4) Transmitted IN Data Complete Clear */ -#define UDPHS_EPTCLRSTA4_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA4) Received SETUP/Error Flow Clear */ -#define UDPHS_EPTCLRSTA4_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA4) Stall Sent/Number of Transaction Error Clear */ -#define UDPHS_EPTCLRSTA4_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA4) NAKIN/Bank Flush Error Clear */ -#define UDPHS_EPTCLRSTA4_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA4) NAKOUT Clear */ -/* -------- UDPHS_EPTSTA4 : (UDPHS Offset: 0x19C) UDPHS Endpoint Status Register (endpoint = 4) -------- */ -#define UDPHS_EPTSTA4_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA4) Stall Handshake Request */ -#define UDPHS_EPTSTA4_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA4) Toggle Sequencing */ -#define UDPHS_EPTSTA4_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA4) Overflow Error */ -#define UDPHS_EPTSTA4_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA4) Received OUT Data/KILL Bank */ -#define UDPHS_EPTSTA4_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA4) Transmitted IN Data Complete */ -#define UDPHS_EPTSTA4_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA4) TX Packet Ready/Transaction Error */ -#define UDPHS_EPTSTA4_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA4) Received SETUP/Error Flow */ -#define UDPHS_EPTSTA4_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA4) Stall Sent/CRC ISO Error/Number of Transaction Error */ -#define UDPHS_EPTSTA4_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA4) NAK IN/Bank Flush Error */ -#define UDPHS_EPTSTA4_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA4) NAK OUT */ -#define UDPHS_EPTSTA4_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA4) Current Bank/Control Direction */ -#define UDPHS_EPTSTA4_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA4) Busy Bank Number */ -#define UDPHS_EPTSTA4_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA4) UDPHS Byte Count */ -#define UDPHS_EPTSTA4_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA4) Short Packet */ -/* -------- UDPHS_EPTCFG5 : (UDPHS Offset: 0x1A0) UDPHS Endpoint Configuration Register (endpoint = 5) -------- */ -#define UDPHS_EPTCFG5_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG5) Endpoint Size */ -#define UDPHS_EPTCFG5_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG5) 8 bytes */ -#define UDPHS_EPTCFG5_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG5) 16 bytes */ -#define UDPHS_EPTCFG5_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG5) 32 bytes */ -#define UDPHS_EPTCFG5_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG5) 64 bytes */ -#define UDPHS_EPTCFG5_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG5) 128 bytes */ -#define UDPHS_EPTCFG5_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG5) 256 bytes */ -#define UDPHS_EPTCFG5_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG5) 512 bytes */ -#define UDPHS_EPTCFG5_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG5) 1024 bytes */ -#define UDPHS_EPTCFG5_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG5) Endpoint Direction */ -#define UDPHS_EPTCFG5_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG5) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG5_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG5) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG5_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG5) Endpoint Type */ -#define UDPHS_EPTCFG5_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG5) Control endpoint */ -#define UDPHS_EPTCFG5_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG5) Isochronous endpoint */ -#define UDPHS_EPTCFG5_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG5) Bulk endpoint */ -#define UDPHS_EPTCFG5_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG5) Interrupt endpoint */ -#define UDPHS_EPTCFG5_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG5) Number of Banks */ -#define UDPHS_EPTCFG5_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG5) Zero bank, the endpoint is not mapped in memory */ -#define UDPHS_EPTCFG5_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG5) One bank (bank 0) */ -#define UDPHS_EPTCFG5_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG5) Double bank (Ping-Pong: bank 0/bank 1) */ -#define UDPHS_EPTCFG5_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG5) Triple bank (bank 0/bank 1/bank 2) */ -#define UDPHS_EPTCFG5_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG5) Number Of Transaction per Microframe */ -#define UDPHS_EPTCFG5_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG5) Endpoint Mapped */ -/* -------- UDPHS_EPTCTLENB5 : (UDPHS Offset: 0x1A4) UDPHS Endpoint Control Enable Register (endpoint = 5) -------- */ -#define UDPHS_EPTCTLENB5_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB5) Endpoint Enable */ -#define UDPHS_EPTCTLENB5_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB5) Packet Auto-Valid Enable */ -#define UDPHS_EPTCTLENB5_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB5) Interrupts Disable DMA */ -#define UDPHS_EPTCTLENB5_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB5) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLENB5_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB5) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB5_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB5) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB5_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB5) Overflow Error Interrupt Enable */ -#define UDPHS_EPTCTLENB5_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB5) Received OUT Data Interrupt Enable */ -#define UDPHS_EPTCTLENB5_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB5) Transmitted IN Data Complete Interrupt Enable */ -#define UDPHS_EPTCTLENB5_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB5) TX Packet Ready/Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB5_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB5) Received SETUP/Error Flow Interrupt Enable */ -#define UDPHS_EPTCTLENB5_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB5) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB5_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB5) NAKIN/Bank Flush Error Interrupt Enable */ -#define UDPHS_EPTCTLENB5_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB5) NAKOUT Interrupt Enable */ -#define UDPHS_EPTCTLENB5_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB5) Busy Bank Interrupt Enable */ -#define UDPHS_EPTCTLENB5_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB5) Short Packet Send/Short Packet Interrupt Enable */ -/* -------- UDPHS_EPTCTLDIS5 : (UDPHS Offset: 0x1A8) UDPHS Endpoint Control Disable Register (endpoint = 5) -------- */ -#define UDPHS_EPTCTLDIS5_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS5) Endpoint Disable */ -#define UDPHS_EPTCTLDIS5_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS5) Packet Auto-Valid Disable */ -#define UDPHS_EPTCTLDIS5_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS5) Interrupts Disable DMA */ -#define UDPHS_EPTCTLDIS5_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS5) NYET Enable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLDIS5_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS5) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS5_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS5) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS5_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS5) Overflow Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS5) Received OUT Data Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS5) Transmitted IN Data Complete Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS5) TX Packet Ready/Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS5) Received SETUP/Error Flow Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS5) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS5) NAKIN/bank flush error Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS5) NAKOUT Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS5) Busy Bank Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS5) Short Packet Interrupt Disable */ -/* -------- UDPHS_EPTCTL5 : (UDPHS Offset: 0x1AC) UDPHS Endpoint Control Register (endpoint = 5) -------- */ -#define UDPHS_EPTCTL5_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL5) Endpoint Enable */ -#define UDPHS_EPTCTL5_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL5) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */ -#define UDPHS_EPTCTL5_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL5) Interrupt Disables DMA */ -#define UDPHS_EPTCTL5_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL5) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTL5_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL5) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL5_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL5) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL5_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL5) Overflow Error Interrupt Enabled */ -#define UDPHS_EPTCTL5_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL5) Received OUT Data Interrupt Enabled */ -#define UDPHS_EPTCTL5_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL5) Transmitted IN Data Complete Interrupt Enabled */ -#define UDPHS_EPTCTL5_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL5) TX Packet Ready/Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL5_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL5) Received SETUP/Error Flow Interrupt Enabled */ -#define UDPHS_EPTCTL5_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL5) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL5_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL5) NAKIN/Bank Flush Error Interrupt Enabled */ -#define UDPHS_EPTCTL5_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL5) NAKOUT Interrupt Enabled */ -#define UDPHS_EPTCTL5_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL5) Busy Bank Interrupt Enabled */ -#define UDPHS_EPTCTL5_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL5) Short Packet Interrupt Enabled */ -/* -------- UDPHS_EPTSETSTA5 : (UDPHS Offset: 0x1B4) UDPHS Endpoint Set Status Register (endpoint = 5) -------- */ -#define UDPHS_EPTSETSTA5_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA5) Stall Handshake Request Set */ -#define UDPHS_EPTSETSTA5_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA5) KILL Bank Set (for IN Endpoint) */ -#define UDPHS_EPTSETSTA5_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA5) TX Packet Ready Set */ -/* -------- UDPHS_EPTCLRSTA5 : (UDPHS Offset: 0x1B8) UDPHS Endpoint Clear Status Register (endpoint = 5) -------- */ -#define UDPHS_EPTCLRSTA5_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA5) Stall Handshake Request Clear */ -#define UDPHS_EPTCLRSTA5_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA5) Data Toggle Clear */ -#define UDPHS_EPTCLRSTA5_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA5) Received OUT Data Clear */ -#define UDPHS_EPTCLRSTA5_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA5) Transmitted IN Data Complete Clear */ -#define UDPHS_EPTCLRSTA5_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA5) Received SETUP/Error Flow Clear */ -#define UDPHS_EPTCLRSTA5_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA5) Stall Sent/Number of Transaction Error Clear */ -#define UDPHS_EPTCLRSTA5_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA5) NAKIN/Bank Flush Error Clear */ -#define UDPHS_EPTCLRSTA5_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA5) NAKOUT Clear */ -/* -------- UDPHS_EPTSTA5 : (UDPHS Offset: 0x1BC) UDPHS Endpoint Status Register (endpoint = 5) -------- */ -#define UDPHS_EPTSTA5_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA5) Stall Handshake Request */ -#define UDPHS_EPTSTA5_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA5) Toggle Sequencing */ -#define UDPHS_EPTSTA5_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA5) Overflow Error */ -#define UDPHS_EPTSTA5_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA5) Received OUT Data/KILL Bank */ -#define UDPHS_EPTSTA5_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA5) Transmitted IN Data Complete */ -#define UDPHS_EPTSTA5_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA5) TX Packet Ready/Transaction Error */ -#define UDPHS_EPTSTA5_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA5) Received SETUP/Error Flow */ -#define UDPHS_EPTSTA5_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA5) Stall Sent/CRC ISO Error/Number of Transaction Error */ -#define UDPHS_EPTSTA5_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA5) NAK IN/Bank Flush Error */ -#define UDPHS_EPTSTA5_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA5) NAK OUT */ -#define UDPHS_EPTSTA5_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA5) Current Bank/Control Direction */ -#define UDPHS_EPTSTA5_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA5) Busy Bank Number */ -#define UDPHS_EPTSTA5_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA5) UDPHS Byte Count */ -#define UDPHS_EPTSTA5_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA5) Short Packet */ -/* -------- UDPHS_EPTCFG6 : (UDPHS Offset: 0x1C0) UDPHS Endpoint Configuration Register (endpoint = 6) -------- */ -#define UDPHS_EPTCFG6_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG6) Endpoint Size */ -#define UDPHS_EPTCFG6_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG6) 8 bytes */ -#define UDPHS_EPTCFG6_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG6) 16 bytes */ -#define UDPHS_EPTCFG6_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG6) 32 bytes */ -#define UDPHS_EPTCFG6_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG6) 64 bytes */ -#define UDPHS_EPTCFG6_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG6) 128 bytes */ -#define UDPHS_EPTCFG6_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG6) 256 bytes */ -#define UDPHS_EPTCFG6_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG6) 512 bytes */ -#define UDPHS_EPTCFG6_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG6) 1024 bytes */ -#define UDPHS_EPTCFG6_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG6) Endpoint Direction */ -#define UDPHS_EPTCFG6_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG6) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG6_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG6) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG6_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG6) Endpoint Type */ -#define UDPHS_EPTCFG6_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG6) Control endpoint */ -#define UDPHS_EPTCFG6_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG6) Isochronous endpoint */ -#define UDPHS_EPTCFG6_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG6) Bulk endpoint */ -#define UDPHS_EPTCFG6_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG6) Interrupt endpoint */ -#define UDPHS_EPTCFG6_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG6) Number of Banks */ -#define UDPHS_EPTCFG6_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG6) Zero bank, the endpoint is not mapped in memory */ -#define UDPHS_EPTCFG6_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG6) One bank (bank 0) */ -#define UDPHS_EPTCFG6_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG6) Double bank (Ping-Pong: bank 0/bank 1) */ -#define UDPHS_EPTCFG6_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG6) Triple bank (bank 0/bank 1/bank 2) */ -#define UDPHS_EPTCFG6_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG6) Number Of Transaction per Microframe */ -#define UDPHS_EPTCFG6_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG6) Endpoint Mapped */ -/* -------- UDPHS_EPTCTLENB6 : (UDPHS Offset: 0x1C4) UDPHS Endpoint Control Enable Register (endpoint = 6) -------- */ -#define UDPHS_EPTCTLENB6_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB6) Endpoint Enable */ -#define UDPHS_EPTCTLENB6_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB6) Packet Auto-Valid Enable */ -#define UDPHS_EPTCTLENB6_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB6) Interrupts Disable DMA */ -#define UDPHS_EPTCTLENB6_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB6) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLENB6_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB6) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB6_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB6) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB6_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB6) Overflow Error Interrupt Enable */ -#define UDPHS_EPTCTLENB6_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB6) Received OUT Data Interrupt Enable */ -#define UDPHS_EPTCTLENB6_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB6) Transmitted IN Data Complete Interrupt Enable */ -#define UDPHS_EPTCTLENB6_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB6) TX Packet Ready/Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB6_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB6) Received SETUP/Error Flow Interrupt Enable */ -#define UDPHS_EPTCTLENB6_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB6) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB6_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB6) NAKIN/Bank Flush Error Interrupt Enable */ -#define UDPHS_EPTCTLENB6_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB6) NAKOUT Interrupt Enable */ -#define UDPHS_EPTCTLENB6_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB6) Busy Bank Interrupt Enable */ -#define UDPHS_EPTCTLENB6_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB6) Short Packet Send/Short Packet Interrupt Enable */ -/* -------- UDPHS_EPTCTLDIS6 : (UDPHS Offset: 0x1C8) UDPHS Endpoint Control Disable Register (endpoint = 6) -------- */ -#define UDPHS_EPTCTLDIS6_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS6) Endpoint Disable */ -#define UDPHS_EPTCTLDIS6_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS6) Packet Auto-Valid Disable */ -#define UDPHS_EPTCTLDIS6_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS6) Interrupts Disable DMA */ -#define UDPHS_EPTCTLDIS6_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS6) NYET Enable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLDIS6_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS6) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS6_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS6) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS6_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS6) Overflow Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS6) Received OUT Data Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS6) Transmitted IN Data Complete Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS6) TX Packet Ready/Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS6) Received SETUP/Error Flow Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS6) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS6) NAKIN/bank flush error Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS6) NAKOUT Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS6) Busy Bank Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS6) Short Packet Interrupt Disable */ -/* -------- UDPHS_EPTCTL6 : (UDPHS Offset: 0x1CC) UDPHS Endpoint Control Register (endpoint = 6) -------- */ -#define UDPHS_EPTCTL6_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL6) Endpoint Enable */ -#define UDPHS_EPTCTL6_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL6) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */ -#define UDPHS_EPTCTL6_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL6) Interrupt Disables DMA */ -#define UDPHS_EPTCTL6_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL6) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTL6_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL6) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL6_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL6) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL6_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL6) Overflow Error Interrupt Enabled */ -#define UDPHS_EPTCTL6_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL6) Received OUT Data Interrupt Enabled */ -#define UDPHS_EPTCTL6_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL6) Transmitted IN Data Complete Interrupt Enabled */ -#define UDPHS_EPTCTL6_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL6) TX Packet Ready/Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL6_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL6) Received SETUP/Error Flow Interrupt Enabled */ -#define UDPHS_EPTCTL6_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL6) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL6_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL6) NAKIN/Bank Flush Error Interrupt Enabled */ -#define UDPHS_EPTCTL6_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL6) NAKOUT Interrupt Enabled */ -#define UDPHS_EPTCTL6_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL6) Busy Bank Interrupt Enabled */ -#define UDPHS_EPTCTL6_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL6) Short Packet Interrupt Enabled */ -/* -------- UDPHS_EPTSETSTA6 : (UDPHS Offset: 0x1D4) UDPHS Endpoint Set Status Register (endpoint = 6) -------- */ -#define UDPHS_EPTSETSTA6_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA6) Stall Handshake Request Set */ -#define UDPHS_EPTSETSTA6_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA6) KILL Bank Set (for IN Endpoint) */ -#define UDPHS_EPTSETSTA6_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA6) TX Packet Ready Set */ -/* -------- UDPHS_EPTCLRSTA6 : (UDPHS Offset: 0x1D8) UDPHS Endpoint Clear Status Register (endpoint = 6) -------- */ -#define UDPHS_EPTCLRSTA6_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA6) Stall Handshake Request Clear */ -#define UDPHS_EPTCLRSTA6_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA6) Data Toggle Clear */ -#define UDPHS_EPTCLRSTA6_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA6) Received OUT Data Clear */ -#define UDPHS_EPTCLRSTA6_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA6) Transmitted IN Data Complete Clear */ -#define UDPHS_EPTCLRSTA6_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA6) Received SETUP/Error Flow Clear */ -#define UDPHS_EPTCLRSTA6_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA6) Stall Sent/Number of Transaction Error Clear */ -#define UDPHS_EPTCLRSTA6_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA6) NAKIN/Bank Flush Error Clear */ -#define UDPHS_EPTCLRSTA6_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA6) NAKOUT Clear */ -/* -------- UDPHS_EPTSTA6 : (UDPHS Offset: 0x1DC) UDPHS Endpoint Status Register (endpoint = 6) -------- */ -#define UDPHS_EPTSTA6_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA6) Stall Handshake Request */ -#define UDPHS_EPTSTA6_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA6) Toggle Sequencing */ -#define UDPHS_EPTSTA6_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA6) Overflow Error */ -#define UDPHS_EPTSTA6_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA6) Received OUT Data/KILL Bank */ -#define UDPHS_EPTSTA6_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA6) Transmitted IN Data Complete */ -#define UDPHS_EPTSTA6_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA6) TX Packet Ready/Transaction Error */ -#define UDPHS_EPTSTA6_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA6) Received SETUP/Error Flow */ -#define UDPHS_EPTSTA6_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA6) Stall Sent/CRC ISO Error/Number of Transaction Error */ -#define UDPHS_EPTSTA6_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA6) NAK IN/Bank Flush Error */ -#define UDPHS_EPTSTA6_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA6) NAK OUT */ -#define UDPHS_EPTSTA6_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA6) Current Bank/Control Direction */ -#define UDPHS_EPTSTA6_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA6) Busy Bank Number */ -#define UDPHS_EPTSTA6_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA6) UDPHS Byte Count */ -#define UDPHS_EPTSTA6_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA6) Short Packet */ -/* -------- UDPHS_DMANXTDSC1 : (UDPHS Offset: 0x320) UDPHS DMA Next Descriptor Address Register (channel = 1) -------- */ -#define UDPHS_DMANXTDSC1_NXT_DSC_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMANXTDSC1) */ -/* -------- UDPHS_DMAADDRESS1 : (UDPHS Offset: 0x324) UDPHS DMA Channel Address Register (channel = 1) -------- */ -#define UDPHS_DMAADDRESS1_BUFF_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMAADDRESS1) */ -/* -------- UDPHS_DMACONTROL1 : (UDPHS Offset: 0x328) UDPHS DMA Channel Control Register (channel = 1) -------- */ -#define UDPHS_DMACONTROL1_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMACONTROL1) */ -#define UDPHS_DMACONTROL1_LDNXT_DSC (0x1 << 1) /**< \brief (UDPHS_DMACONTROL1) Load Next Channel Transfer Descriptor Enable (Command) */ -#define UDPHS_DMACONTROL1_END_TR_EN (0x1 << 2) /**< \brief (UDPHS_DMACONTROL1) End of Transfer Enable (Control) */ -#define UDPHS_DMACONTROL1_END_B_EN (0x1 << 3) /**< \brief (UDPHS_DMACONTROL1) End of Buffer Enable (Control) */ -#define UDPHS_DMACONTROL1_END_TR_IT (0x1 << 4) /**< \brief (UDPHS_DMACONTROL1) End of Transfer Interrupt Enable */ -#define UDPHS_DMACONTROL1_END_BUFFIT (0x1 << 5) /**< \brief (UDPHS_DMACONTROL1) End of Buffer Interrupt Enable */ -#define UDPHS_DMACONTROL1_DESC_LD_IT (0x1 << 6) /**< \brief (UDPHS_DMACONTROL1) Descriptor Loaded Interrupt Enable */ -#define UDPHS_DMACONTROL1_BURST_LCK (0x1 << 7) /**< \brief (UDPHS_DMACONTROL1) Burst Lock Enable */ -#define UDPHS_DMACONTROL1_BUFF_LENGTH (0xffff << 16) /**< \brief (UDPHS_DMACONTROL1) Buffer Byte Length (Write-only) */ -/* -------- UDPHS_DMASTATUS1 : (UDPHS Offset: 0x32C) UDPHS DMA Channel Status Register (channel = 1) -------- */ -#define UDPHS_DMASTATUS1_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMASTATUS1) Channel Enable Status */ -#define UDPHS_DMASTATUS1_CHANN_ACT (0x1 << 1) /**< \brief (UDPHS_DMASTATUS1) Channel Active Status */ -#define UDPHS_DMASTATUS1_END_TR_ST (0x1 << 4) /**< \brief (UDPHS_DMASTATUS1) End of Channel Transfer Status */ -#define UDPHS_DMASTATUS1_END_BF_ST (0x1 << 5) /**< \brief (UDPHS_DMASTATUS1) End of Channel Buffer Status */ -#define UDPHS_DMASTATUS1_DESC_LDST (0x1 << 6) /**< \brief (UDPHS_DMASTATUS1) Descriptor Loaded Status */ -#define UDPHS_DMASTATUS1_BUFF_COUNT (0xffff << 16) /**< \brief (UDPHS_DMASTATUS1) Buffer Byte Count */ -/* -------- UDPHS_DMANXTDSC2 : (UDPHS Offset: 0x330) UDPHS DMA Next Descriptor Address Register (channel = 2) -------- */ -#define UDPHS_DMANXTDSC2_NXT_DSC_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMANXTDSC2) */ -/* -------- UDPHS_DMAADDRESS2 : (UDPHS Offset: 0x334) UDPHS DMA Channel Address Register (channel = 2) -------- */ -#define UDPHS_DMAADDRESS2_BUFF_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMAADDRESS2) */ -/* -------- UDPHS_DMACONTROL2 : (UDPHS Offset: 0x338) UDPHS DMA Channel Control Register (channel = 2) -------- */ -#define UDPHS_DMACONTROL2_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMACONTROL2) */ -#define UDPHS_DMACONTROL2_LDNXT_DSC (0x1 << 1) /**< \brief (UDPHS_DMACONTROL2) Load Next Channel Transfer Descriptor Enable (Command) */ -#define UDPHS_DMACONTROL2_END_TR_EN (0x1 << 2) /**< \brief (UDPHS_DMACONTROL2) End of Transfer Enable (Control) */ -#define UDPHS_DMACONTROL2_END_B_EN (0x1 << 3) /**< \brief (UDPHS_DMACONTROL2) End of Buffer Enable (Control) */ -#define UDPHS_DMACONTROL2_END_TR_IT (0x1 << 4) /**< \brief (UDPHS_DMACONTROL2) End of Transfer Interrupt Enable */ -#define UDPHS_DMACONTROL2_END_BUFFIT (0x1 << 5) /**< \brief (UDPHS_DMACONTROL2) End of Buffer Interrupt Enable */ -#define UDPHS_DMACONTROL2_DESC_LD_IT (0x1 << 6) /**< \brief (UDPHS_DMACONTROL2) Descriptor Loaded Interrupt Enable */ -#define UDPHS_DMACONTROL2_BURST_LCK (0x1 << 7) /**< \brief (UDPHS_DMACONTROL2) Burst Lock Enable */ -#define UDPHS_DMACONTROL2_BUFF_LENGTH (0xffff << 16) /**< \brief (UDPHS_DMACONTROL2) Buffer Byte Length (Write-only) */ -/* -------- UDPHS_DMASTATUS2 : (UDPHS Offset: 0x33C) UDPHS DMA Channel Status Register (channel = 2) -------- */ -#define UDPHS_DMASTATUS2_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMASTATUS2) Channel Enable Status */ -#define UDPHS_DMASTATUS2_CHANN_ACT (0x1 << 1) /**< \brief (UDPHS_DMASTATUS2) Channel Active Status */ -#define UDPHS_DMASTATUS2_END_TR_ST (0x1 << 4) /**< \brief (UDPHS_DMASTATUS2) End of Channel Transfer Status */ -#define UDPHS_DMASTATUS2_END_BF_ST (0x1 << 5) /**< \brief (UDPHS_DMASTATUS2) End of Channel Buffer Status */ -#define UDPHS_DMASTATUS2_DESC_LDST (0x1 << 6) /**< \brief (UDPHS_DMASTATUS2) Descriptor Loaded Status */ -#define UDPHS_DMASTATUS2_BUFF_COUNT (0xffff << 16) /**< \brief (UDPHS_DMASTATUS2) Buffer Byte Count */ -/* -------- UDPHS_DMANXTDSC3 : (UDPHS Offset: 0x340) UDPHS DMA Next Descriptor Address Register (channel = 3) -------- */ -#define UDPHS_DMANXTDSC3_NXT_DSC_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMANXTDSC3) */ -/* -------- UDPHS_DMAADDRESS3 : (UDPHS Offset: 0x344) UDPHS DMA Channel Address Register (channel = 3) -------- */ -#define UDPHS_DMAADDRESS3_BUFF_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMAADDRESS3) */ -/* -------- UDPHS_DMACONTROL3 : (UDPHS Offset: 0x348) UDPHS DMA Channel Control Register (channel = 3) -------- */ -#define UDPHS_DMACONTROL3_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMACONTROL3) */ -#define UDPHS_DMACONTROL3_LDNXT_DSC (0x1 << 1) /**< \brief (UDPHS_DMACONTROL3) Load Next Channel Transfer Descriptor Enable (Command) */ -#define UDPHS_DMACONTROL3_END_TR_EN (0x1 << 2) /**< \brief (UDPHS_DMACONTROL3) End of Transfer Enable (Control) */ -#define UDPHS_DMACONTROL3_END_B_EN (0x1 << 3) /**< \brief (UDPHS_DMACONTROL3) End of Buffer Enable (Control) */ -#define UDPHS_DMACONTROL3_END_TR_IT (0x1 << 4) /**< \brief (UDPHS_DMACONTROL3) End of Transfer Interrupt Enable */ -#define UDPHS_DMACONTROL3_END_BUFFIT (0x1 << 5) /**< \brief (UDPHS_DMACONTROL3) End of Buffer Interrupt Enable */ -#define UDPHS_DMACONTROL3_DESC_LD_IT (0x1 << 6) /**< \brief (UDPHS_DMACONTROL3) Descriptor Loaded Interrupt Enable */ -#define UDPHS_DMACONTROL3_BURST_LCK (0x1 << 7) /**< \brief (UDPHS_DMACONTROL3) Burst Lock Enable */ -#define UDPHS_DMACONTROL3_BUFF_LENGTH (0xffff << 16) /**< \brief (UDPHS_DMACONTROL3) Buffer Byte Length (Write-only) */ -/* -------- UDPHS_DMASTATUS3 : (UDPHS Offset: 0x34C) UDPHS DMA Channel Status Register (channel = 3) -------- */ -#define UDPHS_DMASTATUS3_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMASTATUS3) Channel Enable Status */ -#define UDPHS_DMASTATUS3_CHANN_ACT (0x1 << 1) /**< \brief (UDPHS_DMASTATUS3) Channel Active Status */ -#define UDPHS_DMASTATUS3_END_TR_ST (0x1 << 4) /**< \brief (UDPHS_DMASTATUS3) End of Channel Transfer Status */ -#define UDPHS_DMASTATUS3_END_BF_ST (0x1 << 5) /**< \brief (UDPHS_DMASTATUS3) End of Channel Buffer Status */ -#define UDPHS_DMASTATUS3_DESC_LDST (0x1 << 6) /**< \brief (UDPHS_DMASTATUS3) Descriptor Loaded Status */ -#define UDPHS_DMASTATUS3_BUFF_COUNT (0xffff << 16) /**< \brief (UDPHS_DMASTATUS3) Buffer Byte Count */ -/* -------- UDPHS_DMANXTDSC4 : (UDPHS Offset: 0x350) UDPHS DMA Next Descriptor Address Register (channel = 4) -------- */ -#define UDPHS_DMANXTDSC4_NXT_DSC_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMANXTDSC4) */ -/* -------- UDPHS_DMAADDRESS4 : (UDPHS Offset: 0x354) UDPHS DMA Channel Address Register (channel = 4) -------- */ -#define UDPHS_DMAADDRESS4_BUFF_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMAADDRESS4) */ -/* -------- UDPHS_DMACONTROL4 : (UDPHS Offset: 0x358) UDPHS DMA Channel Control Register (channel = 4) -------- */ -#define UDPHS_DMACONTROL4_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMACONTROL4) */ -#define UDPHS_DMACONTROL4_LDNXT_DSC (0x1 << 1) /**< \brief (UDPHS_DMACONTROL4) Load Next Channel Transfer Descriptor Enable (Command) */ -#define UDPHS_DMACONTROL4_END_TR_EN (0x1 << 2) /**< \brief (UDPHS_DMACONTROL4) End of Transfer Enable (Control) */ -#define UDPHS_DMACONTROL4_END_B_EN (0x1 << 3) /**< \brief (UDPHS_DMACONTROL4) End of Buffer Enable (Control) */ -#define UDPHS_DMACONTROL4_END_TR_IT (0x1 << 4) /**< \brief (UDPHS_DMACONTROL4) End of Transfer Interrupt Enable */ -#define UDPHS_DMACONTROL4_END_BUFFIT (0x1 << 5) /**< \brief (UDPHS_DMACONTROL4) End of Buffer Interrupt Enable */ -#define UDPHS_DMACONTROL4_DESC_LD_IT (0x1 << 6) /**< \brief (UDPHS_DMACONTROL4) Descriptor Loaded Interrupt Enable */ -#define UDPHS_DMACONTROL4_BURST_LCK (0x1 << 7) /**< \brief (UDPHS_DMACONTROL4) Burst Lock Enable */ -#define UDPHS_DMACONTROL4_BUFF_LENGTH (0xffff << 16) /**< \brief (UDPHS_DMACONTROL4) Buffer Byte Length (Write-only) */ -/* -------- UDPHS_DMASTATUS4 : (UDPHS Offset: 0x35C) UDPHS DMA Channel Status Register (channel = 4) -------- */ -#define UDPHS_DMASTATUS4_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMASTATUS4) Channel Enable Status */ -#define UDPHS_DMASTATUS4_CHANN_ACT (0x1 << 1) /**< \brief (UDPHS_DMASTATUS4) Channel Active Status */ -#define UDPHS_DMASTATUS4_END_TR_ST (0x1 << 4) /**< \brief (UDPHS_DMASTATUS4) End of Channel Transfer Status */ -#define UDPHS_DMASTATUS4_END_BF_ST (0x1 << 5) /**< \brief (UDPHS_DMASTATUS4) End of Channel Buffer Status */ -#define UDPHS_DMASTATUS4_DESC_LDST (0x1 << 6) /**< \brief (UDPHS_DMASTATUS4) Descriptor Loaded Status */ -#define UDPHS_DMASTATUS4_BUFF_COUNT (0xffff << 16) /**< \brief (UDPHS_DMASTATUS4) Buffer Byte Count */ -/* -------- UDPHS_DMANXTDSC5 : (UDPHS Offset: 0x360) UDPHS DMA Next Descriptor Address Register (channel = 5) -------- */ -#define UDPHS_DMANXTDSC5_NXT_DSC_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMANXTDSC5) */ -/* -------- UDPHS_DMAADDRESS5 : (UDPHS Offset: 0x364) UDPHS DMA Channel Address Register (channel = 5) -------- */ -#define UDPHS_DMAADDRESS5_BUFF_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMAADDRESS5) */ -/* -------- UDPHS_DMACONTROL5 : (UDPHS Offset: 0x368) UDPHS DMA Channel Control Register (channel = 5) -------- */ -#define UDPHS_DMACONTROL5_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMACONTROL5) */ -#define UDPHS_DMACONTROL5_LDNXT_DSC (0x1 << 1) /**< \brief (UDPHS_DMACONTROL5) Load Next Channel Transfer Descriptor Enable (Command) */ -#define UDPHS_DMACONTROL5_END_TR_EN (0x1 << 2) /**< \brief (UDPHS_DMACONTROL5) End of Transfer Enable (Control) */ -#define UDPHS_DMACONTROL5_END_B_EN (0x1 << 3) /**< \brief (UDPHS_DMACONTROL5) End of Buffer Enable (Control) */ -#define UDPHS_DMACONTROL5_END_TR_IT (0x1 << 4) /**< \brief (UDPHS_DMACONTROL5) End of Transfer Interrupt Enable */ -#define UDPHS_DMACONTROL5_END_BUFFIT (0x1 << 5) /**< \brief (UDPHS_DMACONTROL5) End of Buffer Interrupt Enable */ -#define UDPHS_DMACONTROL5_DESC_LD_IT (0x1 << 6) /**< \brief (UDPHS_DMACONTROL5) Descriptor Loaded Interrupt Enable */ -#define UDPHS_DMACONTROL5_BURST_LCK (0x1 << 7) /**< \brief (UDPHS_DMACONTROL5) Burst Lock Enable */ -#define UDPHS_DMACONTROL5_BUFF_LENGTH (0xffff << 16) /**< \brief (UDPHS_DMACONTROL5) Buffer Byte Length (Write-only) */ -/* -------- UDPHS_DMASTATUS5 : (UDPHS Offset: 0x36C) UDPHS DMA Channel Status Register (channel = 5) -------- */ -#define UDPHS_DMASTATUS5_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMASTATUS5) Channel Enable Status */ -#define UDPHS_DMASTATUS5_CHANN_ACT (0x1 << 1) /**< \brief (UDPHS_DMASTATUS5) Channel Active Status */ -#define UDPHS_DMASTATUS5_END_TR_ST (0x1 << 4) /**< \brief (UDPHS_DMASTATUS5) End of Channel Transfer Status */ -#define UDPHS_DMASTATUS5_END_BF_ST (0x1 << 5) /**< \brief (UDPHS_DMASTATUS5) End of Channel Buffer Status */ -#define UDPHS_DMASTATUS5_DESC_LDST (0x1 << 6) /**< \brief (UDPHS_DMASTATUS5) Descriptor Loaded Status */ -#define UDPHS_DMASTATUS5_BUFF_COUNT (0xffff << 16) /**< \brief (UDPHS_DMASTATUS5) Buffer Byte Count */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_USART Universal Synchronous Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Usart hardware registers */ -typedef struct { - WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ - RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ - WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ - WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ - RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ - RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ - RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ - WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ - RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ - RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ - RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ - RwReg Reserved1[5]; - RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ - RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ - RwReg Reserved2[1]; - RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ - RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ - RwReg Reserved3[36]; - RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */ - RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved4[4]; - RoReg US_VERSION; /**< \brief (Usart Offset: 0xFC) Version Register */ - RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ - RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ - RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ - RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ - RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ - RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ - RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ - RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ - WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ - RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ -} Usart; -#endif /* __ASSEMBLY__ */ -/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ -#define US_CR_RSTRX (0x1 << 2) /**< \brief (US_CR) Reset Receiver */ -#define US_CR_RSTTX (0x1 << 3) /**< \brief (US_CR) Reset Transmitter */ -#define US_CR_RXEN (0x1 << 4) /**< \brief (US_CR) Receiver Enable */ -#define US_CR_RXDIS (0x1 << 5) /**< \brief (US_CR) Receiver Disable */ -#define US_CR_TXEN (0x1 << 6) /**< \brief (US_CR) Transmitter Enable */ -#define US_CR_TXDIS (0x1 << 7) /**< \brief (US_CR) Transmitter Disable */ -#define US_CR_RSTSTA (0x1 << 8) /**< \brief (US_CR) Reset Status Bits */ -#define US_CR_STTBRK (0x1 << 9) /**< \brief (US_CR) Start Break */ -#define US_CR_STPBRK (0x1 << 10) /**< \brief (US_CR) Stop Break */ -#define US_CR_STTTO (0x1 << 11) /**< \brief (US_CR) Start Time-out */ -#define US_CR_SENDA (0x1 << 12) /**< \brief (US_CR) Send Address */ -#define US_CR_RSTIT (0x1 << 13) /**< \brief (US_CR) Reset Iterations */ -#define US_CR_RSTNACK (0x1 << 14) /**< \brief (US_CR) Reset Non Acknowledge */ -#define US_CR_RETTO (0x1 << 15) /**< \brief (US_CR) Rearm Time-out */ -#define US_CR_RTSEN__FCS (0x1 << 18) /**< \brief (US_CR) Request to Send Enable/Force SPI Chip Select */ -#define US_CR_RTSDIS__RCS (0x1 << 19) /**< \brief (US_CR) Request to Send Disable/Release SPI Chip Select */ -/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ -#define US_MR_USART_MODE (0xf << 0) /**< \brief (US_MR) */ -#define US_MR_USCLKS (0x3 << 4) /**< \brief (US_MR) Clock Selection */ -#define US_MR_CHRL (0x3 << 6) /**< \brief (US_MR) Character Length. */ -#define US_MR_SYNC__CPHA (0x1 << 8) /**< \brief (US_MR) Synchronous Mode Select or SPI Clock Phase */ -#define US_MR_PAR (0x7 << 9) /**< \brief (US_MR) Parity Type */ -#define US_MR_NBSTOP (0x3 << 12) /**< \brief (US_MR) Number of Stop Bits */ -#define US_MR_CHMODE (0x3 << 14) /**< \brief (US_MR) Channel Mode */ -#define US_MR_MSBF__CPOL (0x1 << 16) /**< \brief (US_MR) Bit Order or SPI Clock Polarity */ -#define US_MR_MODE9 (0x1 << 17) /**< \brief (US_MR) 9-bit Character Length */ -#define US_MR_CLKO (0x1 << 18) /**< \brief (US_MR) Clock Output Select */ -#define US_MR_OVER (0x1 << 19) /**< \brief (US_MR) Oversampling Mode */ -#define US_MR_INACK (0x1 << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ -#define US_MR_DSNACK (0x1 << 21) /**< \brief (US_MR) Disable Successive NACK */ -#define US_MR_VAR_SYNC (0x1 << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ -#define US_MR_INVDATA (0x1 << 23) /**< \brief (US_MR) INverted Data */ -#define US_MR_MAX_ITERATION (0x7 << 24) /**< \brief (US_MR) */ -#define US_MR_FILTER (0x1 << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ -#define US_MR_MAN (0x1 << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ -#define US_MR_MODSYNC_ (0x1 << 30) /**< \brief (US_MR) */ -#define US_MR_ONEBIT (0x1 << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ -/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ -#define US_IER_RXRDY (0x1 << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ -#define US_IER_TXRDY (0x1 << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ -#define US_IER_RXBRK (0x1 << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ -#define US_IER_ENDRX (0x1 << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */ -#define US_IER_ENDTX (0x1 << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */ -#define US_IER_OVRE (0x1 << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ -#define US_IER_FRAME (0x1 << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ -#define US_IER_PARE (0x1 << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ -#define US_IER_TIMEOUT (0x1 << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ -#define US_IER_TXEMPTY (0x1 << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ -#define US_IER_ITER__UNRE (0x1 << 10) /**< \brief (US_IER) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IER_TXBUFE (0x1 << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */ -#define US_IER_RXBUFF (0x1 << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */ -#define US_IER_NACK (0x1 << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ -#define US_IER_CTSIC (0x1 << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ -#define US_IER_MANE (0x1 << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ -/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ -#define US_IDR_RXRDY (0x1 << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ -#define US_IDR_TXRDY (0x1 << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ -#define US_IDR_RXBRK (0x1 << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ -#define US_IDR_ENDRX (0x1 << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */ -#define US_IDR_ENDTX (0x1 << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */ -#define US_IDR_OVRE (0x1 << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */ -#define US_IDR_FRAME (0x1 << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ -#define US_IDR_PARE (0x1 << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ -#define US_IDR_TIMEOUT (0x1 << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ -#define US_IDR_TXEMPTY (0x1 << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ -#define US_IDR_ITER__UNRE (0x1 << 10) /**< \brief (US_IDR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IDR_TXBUFE (0x1 << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */ -#define US_IDR_RXBUFF (0x1 << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */ -#define US_IDR_NACK (0x1 << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ -#define US_IDR_CTSIC (0x1 << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ -#define US_IDR_MANE (0x1 << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ -/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ -#define US_IMR_RXRDY (0x1 << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ -#define US_IMR_TXRDY (0x1 << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ -#define US_IMR_RXBRK (0x1 << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ -#define US_IMR_ENDRX (0x1 << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */ -#define US_IMR_ENDTX (0x1 << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */ -#define US_IMR_OVRE (0x1 << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ -#define US_IMR_FRAME (0x1 << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ -#define US_IMR_PARE (0x1 << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ -#define US_IMR_TIMEOUT (0x1 << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ -#define US_IMR_TXEMPTY (0x1 << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ -#define US_IMR_ITER__UNRE (0x1 << 10) /**< \brief (US_IMR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IMR_TXBUFE (0x1 << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */ -#define US_IMR_RXBUFF (0x1 << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */ -#define US_IMR_NACK (0x1 << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ -#define US_IMR_CTSIC (0x1 << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ -#define US_IMR_MANE (0x1 << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ -/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ -#define US_CSR_RXRDY (0x1 << 0) /**< \brief (US_CSR) Receiver Ready */ -#define US_CSR_TXRDY (0x1 << 1) /**< \brief (US_CSR) Transmitter Ready */ -#define US_CSR_RXBRK (0x1 << 2) /**< \brief (US_CSR) Break Received/End of Break */ -#define US_CSR_ENDRX (0x1 << 3) /**< \brief (US_CSR) End of Receiver Transfer */ -#define US_CSR_ENDTX (0x1 << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ -#define US_CSR_OVRE (0x1 << 5) /**< \brief (US_CSR) Overrun Error */ -#define US_CSR_FRAME (0x1 << 6) /**< \brief (US_CSR) Framing Error */ -#define US_CSR_PARE (0x1 << 7) /**< \brief (US_CSR) Parity Error */ -#define US_CSR_TIMEOUT (0x1 << 8) /**< \brief (US_CSR) Receiver Time-out */ -#define US_CSR_TXEMPTY (0x1 << 9) /**< \brief (US_CSR) Transmitter Empty */ -#define US_CSR_ITER__UNRE (0x1 << 10) /**< \brief (US_CSR) Max number of Repetitions Reached or SPI Underrun Error */ -#define US_CSR_TXBUFE (0x1 << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ -#define US_CSR_RXBUFF (0x1 << 12) /**< \brief (US_CSR) Reception Buffer Full */ -#define US_CSR_NACK (0x1 << 13) /**< \brief (US_CSR) */ -#define US_CSR_CTSIC (0x1 << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ -#define US_CSR_CTS (0x1 << 23) /**< \brief (US_CSR) Image of CTS Input */ -#define US_CSR_MANERR (0x1 << 24) /**< \brief (US_CSR) Manchester Error */ -/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ -#define US_RHR_RXCHR (0x1ff << 0) /**< \brief (US_RHR) Received Character */ -#define US_RHR_RXSYNH (0x1 << 15) /**< \brief (US_RHR) Received Sync */ -/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ -#define US_THR_TXCHR (0x1ff << 0) /**< \brief (US_THR) Character to be Transmitted */ -#define US_THR_TXSYNH (0x1 << 15) /**< \brief (US_THR) Sync Field to be transmitted */ -/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define US_BRGR_CD (0xffff << 0) /**< \brief (US_BRGR) Clock Divider */ -#define US_BRGR_FP (0x7 << 16) /**< \brief (US_BRGR) Fractional Part */ -/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ -#define US_RTOR_TO (0xffff << 0) /**< \brief (US_RTOR) Time-out Value */ -/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ -#define US_TTGR_TG (0xff << 0) /**< \brief (US_TTGR) Timeguard Value */ -/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ -#define US_FIDI_FI_DI_RATIO (0x7ff << 0) /**< \brief (US_FIDI) FI Over DI Ratio Value */ -/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ -#define US_NER_NB_ERRORS (0xff << 0) /**< \brief (US_NER) Number of Errors */ -/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ -#define US_IF_IRDA_FILTER (0xff << 0) /**< \brief (US_IF) IrDA Filter */ -/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ -#define US_MAN_TX_PL (0xf << 0) /**< \brief (US_MAN) Transmitter Preamble Length */ -#define US_MAN_TX_PP (0x3 << 8) /**< \brief (US_MAN) Transmitter Preamble Pattern */ -#define US_MAN_TX_MPOL (0x1 << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ -#define US_MAN_RX_PL (0xf << 16) /**< \brief (US_MAN) Receiver Preamble Length */ -#define US_MAN_RX_PP (0x3 << 24) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ -#define US_MAN_RX_MPOL (0x1 << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ -#define US_MAN_STUCKTO1 (0x1 << 29) /**< \brief (US_MAN) */ -#define US_MAN_DRIFT (0x1 << 30) /**< \brief (US_MAN) Drift compensation */ -/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */ -#define US_WPMR_WPEN (0x1 << 0) /**< \brief (US_WPMR) Write Protect Enable */ -#define US_WPMR_WPKEY (0xffffff << 8) /**< \brief (US_WPMR) Write Protect KEY */ -/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */ -#define US_WPSR_WPVS (0x1 << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ -#define US_WPSR_WPVSRC (0xffff << 8) /**< \brief (US_WPSR) Write Protect Violation Source */ -/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */ -#define US_VERSION_VERSION (0xfff << 0) /**< \brief (US_VERSION) */ -#define US_VERSION_MFN (0x7 << 16) /**< \brief (US_VERSION) */ -/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ -#define US_RPR_RXPTR (0xffffffff << 0) /**< \brief (US_RPR) Receive Pointer Register */ -/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ -#define US_RCR_RXCTR (0xffff << 0) /**< \brief (US_RCR) Receive Counter Register */ -/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ -#define US_TPR_TXPTR (0xffffffff << 0) /**< \brief (US_TPR) Transmit Counter Register */ -/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ -#define US_TCR_TXCTR (0xffff << 0) /**< \brief (US_TCR) Transmit Counter Register */ -/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ -#define US_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (US_RNPR) Receive Next Pointer */ -/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ -#define US_RNCR_RXNCTR (0xffff << 0) /**< \brief (US_RNCR) Receive Next Counter */ -/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define US_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (US_TNPR) Transmit Next Pointer */ -/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define US_TNCR_TXNCTR (0xffff << 0) /**< \brief (US_TNCR) Transmit Counter Next */ -/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ -#define US_PTCR_RXTEN (0x1 << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ -#define US_PTCR_RXTDIS (0x1 << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ -#define US_PTCR_TXTEN (0x1 << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ -#define US_PTCR_TXTDIS (0x1 << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ -/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ -#define US_PTSR_RXTEN (0x1 << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ -#define US_PTSR_TXTEN (0x1 << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Watchdog Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_WDT Watchdog Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Wdt hardware registers */ -typedef struct { - WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ - RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ - RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ -} Wdt; -#endif /* __ASSEMBLY__ */ -/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ -#define WDT_CR_WDRSTT (0x1 << 0) /**< \brief (WDT_CR) Watchdog Restart */ -#define WDT_CR_KEY (0xff << 24) /**< \brief (WDT_CR) Password */ -/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ -#define WDT_MR_WDV (0xfff << 0) /**< \brief (WDT_MR) Watchdog Counter Value */ -#define WDT_MR_WDFIEN (0x1 << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ -#define WDT_MR_WDRSTEN (0x1 << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ -#define WDT_MR_WDRPROC (0x1 << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ -#define WDT_MR_WDDIS (0x1 << 15) /**< \brief (WDT_MR) Watchdog Disable */ -#define WDT_MR_WDD (0xfff << 16) /**< \brief (WDT_MR) Watchdog Delta Value */ -#define WDT_MR_WDDBGHLT (0x1 << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ -#define WDT_MR_WDIDLEHLT (0x1 << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ -/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ -#define WDT_SR_WDUNF (0x1 << 0) /**< \brief (WDT_SR) Watchdog Underflow */ -#define WDT_SR_WDERR (0x1 << 1) /**< \brief (WDT_SR) Watchdog Error */ - -/*@}*/ - -/*@}*/ - -/* ***************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR AT91SAM3U */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3U_reg Registers Access Definitions */ -/*@{*/ - -/* ========== Register definition for HSMCI peripheral ========== */ -#define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */ -#define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */ -#define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ -#define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ -#define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */ -#define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */ -#define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */ -#define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ -#define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */ -#define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */ -#define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ -#define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */ -#define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ -#define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ -#define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ -#define REG_HSMCI_DMA REG_ACCESS(RwReg, 0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ -#define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */ -#define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ -#define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ -/* ========== Register definition for SSC peripheral ========== */ -#define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */ -#define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */ -#define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ -#define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ -#define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ -#define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ -#define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */ -#define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */ -#define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ -#define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ -#define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ -#define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ -#define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */ -#define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ -#define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ -#define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ -#define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ -#define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ -/* ========== Register definition for SPI peripheral ========== */ -#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */ -#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */ -#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */ -#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */ -#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */ -#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ -#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ -#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ -#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */ -#define REG_SPI_WPCR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ -#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ -/* ========== Register definition for TC0 peripheral ========== */ -#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ -#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ -#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */ -#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40080014U) /**< \brief (TC0) Register A (channel = 0) */ -#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40080018U) /**< \brief (TC0) Register B (channel = 0) */ -#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */ -#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */ -#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ -#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ -#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ -#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ -#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ -#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */ -#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40080054U) /**< \brief (TC0) Register A (channel = 1) */ -#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40080058U) /**< \brief (TC0) Register B (channel = 1) */ -#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */ -#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */ -#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ -#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ -#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ -#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ -#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ -#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */ -#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40080094U) /**< \brief (TC0) Register A (channel = 2) */ -#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40080098U) /**< \brief (TC0) Register B (channel = 2) */ -#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */ -#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */ -#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ -#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ -#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ -#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400800C0U) /**< \brief (TC0) Block Control Register */ -#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400800C4U) /**< \brief (TC0) Block Mode Register */ -#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ -#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ -#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ -#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ -#define REG_TC0_VER REG_ACCESS(RoReg, 0x400800FCU) /**< \brief (TC0) Version Register */ -/* ========== Register definition for TWI0 peripheral ========== */ -#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40084000U) /**< \brief (TWI0) Control Register */ -#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40084004U) /**< \brief (TWI0) Master Mode Register */ -#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40084008U) /**< \brief (TWI0) Slave Mode Register */ -#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4008400CU) /**< \brief (TWI0) Internal Address Register */ -#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40084010U) /**< \brief (TWI0) Clock Waveform Generator Register */ -#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40084020U) /**< \brief (TWI0) Status Register */ -#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40084024U) /**< \brief (TWI0) Interrupt Enable Register */ -#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40084028U) /**< \brief (TWI0) Interrupt Disable Register */ -#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4008402CU) /**< \brief (TWI0) Interrupt Mask Register */ -#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40084030U) /**< \brief (TWI0) Receive Holding Register */ -#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40084034U) /**< \brief (TWI0) Transmit Holding Register */ -#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40084100U) /**< \brief (TWI0) Receive Pointer Register */ -#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40084104U) /**< \brief (TWI0) Receive Counter Register */ -#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40084108U) /**< \brief (TWI0) Transmit Pointer Register */ -#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4008410CU) /**< \brief (TWI0) Transmit Counter Register */ -#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40084110U) /**< \brief (TWI0) Receive Next Pointer Register */ -#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40084114U) /**< \brief (TWI0) Receive Next Counter Register */ -#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40084118U) /**< \brief (TWI0) Transmit Next Pointer Register */ -#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4008411CU) /**< \brief (TWI0) Transmit Next Counter Register */ -#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40084120U) /**< \brief (TWI0) Transfer Control Register */ -#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40084124U) /**< \brief (TWI0) Transfer Status Register */ -/* ========== Register definition for TWI1 peripheral ========== */ -#define REG_TWI1_CR REG_ACCESS(WoReg, 0x40088000U) /**< \brief (TWI1) Control Register */ -#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x40088004U) /**< \brief (TWI1) Master Mode Register */ -#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x40088008U) /**< \brief (TWI1) Slave Mode Register */ -#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4008800CU) /**< \brief (TWI1) Internal Address Register */ -#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x40088010U) /**< \brief (TWI1) Clock Waveform Generator Register */ -#define REG_TWI1_SR REG_ACCESS(RoReg, 0x40088020U) /**< \brief (TWI1) Status Register */ -#define REG_TWI1_IER REG_ACCESS(WoReg, 0x40088024U) /**< \brief (TWI1) Interrupt Enable Register */ -#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x40088028U) /**< \brief (TWI1) Interrupt Disable Register */ -#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4008802CU) /**< \brief (TWI1) Interrupt Mask Register */ -#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x40088030U) /**< \brief (TWI1) Receive Holding Register */ -#define REG_TWI1_THR REG_ACCESS(WoReg, 0x40088034U) /**< \brief (TWI1) Transmit Holding Register */ -#define REG_TWI1_RPR REG_ACCESS(RwReg, 0x40088100U) /**< \brief (TWI1) Receive Pointer Register */ -#define REG_TWI1_RCR REG_ACCESS(RwReg, 0x40088104U) /**< \brief (TWI1) Receive Counter Register */ -#define REG_TWI1_TPR REG_ACCESS(RwReg, 0x40088108U) /**< \brief (TWI1) Transmit Pointer Register */ -#define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4008810CU) /**< \brief (TWI1) Transmit Counter Register */ -#define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x40088110U) /**< \brief (TWI1) Receive Next Pointer Register */ -#define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x40088114U) /**< \brief (TWI1) Receive Next Counter Register */ -#define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x40088118U) /**< \brief (TWI1) Transmit Next Pointer Register */ -#define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4008811CU) /**< \brief (TWI1) Transmit Next Counter Register */ -#define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x40088120U) /**< \brief (TWI1) Transfer Control Register */ -#define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x40088124U) /**< \brief (TWI1) Transfer Status Register */ -/* ========== Register definition for PWM peripheral ========== */ -#define REG_PWM_CLK REG_ACCESS(RwReg, 0x4008C000U) /**< \brief (PWM) PWM Clock Register */ -#define REG_PWM_ENA REG_ACCESS(WoReg, 0x4008C004U) /**< \brief (PWM) PWM Enable Register */ -#define REG_PWM_DIS REG_ACCESS(WoReg, 0x4008C008U) /**< \brief (PWM) PWM Disable Register */ -#define REG_PWM_SR REG_ACCESS(RoReg, 0x4008C00CU) /**< \brief (PWM) PWM Status Register */ -#define REG_PWM_IER1 REG_ACCESS(WoReg, 0x4008C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ -#define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x4008C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ -#define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x4008C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ -#define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4008C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ -#define REG_PWM_SCM REG_ACCESS(RwReg, 0x4008C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ -#define REG_PWM_SCUC REG_ACCESS(RwReg, 0x4008C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ -#define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4008C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ -#define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x4008C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ -#define REG_PWM_IER2 REG_ACCESS(WoReg, 0x4008C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ -#define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x4008C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ -#define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4008C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ -#define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x4008C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ -#define REG_PWM_OOV REG_ACCESS(RwReg, 0x4008C044U) /**< \brief (PWM) PWM Output Override Value Register */ -#define REG_PWM_OS REG_ACCESS(RwReg, 0x4008C048U) /**< \brief (PWM) PWM Output Selection Register */ -#define REG_PWM_OSS REG_ACCESS(WoReg, 0x4008C04CU) /**< \brief (PWM) PWM Output Selection Set Register */ -#define REG_PWM_OSC REG_ACCESS(WoReg, 0x4008C050U) /**< \brief (PWM) PWM Output Selection Clear Register */ -#define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x4008C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ -#define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x4008C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ -#define REG_PWM_FMR REG_ACCESS(RwReg, 0x4008C05CU) /**< \brief (PWM) PWM Fault Mode Register */ -#define REG_PWM_FSR REG_ACCESS(RoReg, 0x4008C060U) /**< \brief (PWM) PWM Fault Status Register */ -#define REG_PWM_FCR REG_ACCESS(WoReg, 0x4008C064U) /**< \brief (PWM) PWM Fault Clear Register */ -#define REG_PWM_FPV REG_ACCESS(RwReg, 0x4008C068U) /**< \brief (PWM) PWM Fault Protection Value Register */ -#define REG_PWM_FPE REG_ACCESS(RwReg, 0x4008C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ -#define REG_PWM_ELxMR REG_ACCESS(RwReg, 0x4008C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ -#define REG_PWM_WPCR REG_ACCESS(WoReg, 0x4008C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */ -#define REG_PWM_WPSR REG_ACCESS(RoReg, 0x4008C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */ -#define REG_PWM_RPR REG_ACCESS(RwReg, 0x4008C100U) /**< \brief (PWM) Receive Pointer Register */ -#define REG_PWM_RCR REG_ACCESS(RwReg, 0x4008C104U) /**< \brief (PWM) Receive Counter Register */ -#define REG_PWM_TPR REG_ACCESS(RwReg, 0x4008C108U) /**< \brief (PWM) Transmit Pointer Register */ -#define REG_PWM_TCR REG_ACCESS(RwReg, 0x4008C10CU) /**< \brief (PWM) Transmit Counter Register */ -#define REG_PWM_RNPR REG_ACCESS(RwReg, 0x4008C110U) /**< \brief (PWM) Receive Next Pointer Register */ -#define REG_PWM_RNCR REG_ACCESS(RwReg, 0x4008C114U) /**< \brief (PWM) Receive Next Counter Register */ -#define REG_PWM_TNPR REG_ACCESS(RwReg, 0x4008C118U) /**< \brief (PWM) Transmit Next Pointer Register */ -#define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4008C11CU) /**< \brief (PWM) Transmit Next Counter Register */ -#define REG_PWM_PTCR REG_ACCESS(WoReg, 0x4008C120U) /**< \brief (PWM) Transfer Control Register */ -#define REG_PWM_PTSR REG_ACCESS(RoReg, 0x4008C124U) /**< \brief (PWM) Transfer Status Register */ -#define REG_PWM_CMP0V REG_ACCESS(RwReg, 0x4008C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ -#define REG_PWM_CMP0VUPD REG_ACCESS(WoReg, 0x4008C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ -#define REG_PWM_CMP0M REG_ACCESS(RwReg, 0x4008C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ -#define REG_PWM_CMP0MUPD REG_ACCESS(WoReg, 0x4008C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ -#define REG_PWM_CMP1V REG_ACCESS(RwReg, 0x4008C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ -#define REG_PWM_CMP1VUPD REG_ACCESS(WoReg, 0x4008C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ -#define REG_PWM_CMP1M REG_ACCESS(RwReg, 0x4008C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ -#define REG_PWM_CMP1MUPD REG_ACCESS(WoReg, 0x4008C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ -#define REG_PWM_CMP2V REG_ACCESS(RwReg, 0x4008C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ -#define REG_PWM_CMP2VUPD REG_ACCESS(WoReg, 0x4008C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ -#define REG_PWM_CMP2M REG_ACCESS(RwReg, 0x4008C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ -#define REG_PWM_CMP2MUPD REG_ACCESS(WoReg, 0x4008C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ -#define REG_PWM_CMP3V REG_ACCESS(RwReg, 0x4008C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ -#define REG_PWM_CMP3VUPD REG_ACCESS(WoReg, 0x4008C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ -#define REG_PWM_CMP3M REG_ACCESS(RwReg, 0x4008C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ -#define REG_PWM_CMP3MUPD REG_ACCESS(WoReg, 0x4008C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ -#define REG_PWM_CMP4V REG_ACCESS(RwReg, 0x4008C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ -#define REG_PWM_CMP4VUPD REG_ACCESS(WoReg, 0x4008C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ -#define REG_PWM_CMP4M REG_ACCESS(RwReg, 0x4008C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ -#define REG_PWM_CMP4MUPD REG_ACCESS(WoReg, 0x4008C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ -#define REG_PWM_CMP5V REG_ACCESS(RwReg, 0x4008C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ -#define REG_PWM_CMP5VUPD REG_ACCESS(WoReg, 0x4008C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ -#define REG_PWM_CMP5M REG_ACCESS(RwReg, 0x4008C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ -#define REG_PWM_CMP5MUPD REG_ACCESS(WoReg, 0x4008C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ -#define REG_PWM_CMP6V REG_ACCESS(RwReg, 0x4008C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ -#define REG_PWM_CMP6VUPD REG_ACCESS(WoReg, 0x4008C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ -#define REG_PWM_CMP6M REG_ACCESS(RwReg, 0x4008C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ -#define REG_PWM_CMP6MUPD REG_ACCESS(WoReg, 0x4008C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ -#define REG_PWM_CMP7V REG_ACCESS(RwReg, 0x4008C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ -#define REG_PWM_CMP7VUPD REG_ACCESS(WoReg, 0x4008C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ -#define REG_PWM_CMP7M REG_ACCESS(RwReg, 0x4008C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ -#define REG_PWM_CMP7MUPD REG_ACCESS(WoReg, 0x4008C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ -#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x4008C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ -#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x4008C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ -#define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x4008C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ -#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4008C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ -#define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x4008C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ -#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x4008C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ -#define REG_PWM_DT0 REG_ACCESS(RwReg, 0x4008C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ -#define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4008C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ -#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x4008C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ -#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x4008C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ -#define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x4008C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ -#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4008C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ -#define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x4008C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ -#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x4008C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ -#define REG_PWM_DT1 REG_ACCESS(RwReg, 0x4008C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ -#define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4008C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ -#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x4008C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ -#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x4008C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ -#define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x4008C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ -#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4008C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ -#define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x4008C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ -#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x4008C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ -#define REG_PWM_DT2 REG_ACCESS(RwReg, 0x4008C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ -#define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4008C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ -#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x4008C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ -#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x4008C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ -#define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x4008C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ -#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4008C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ -#define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x4008C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ -#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x4008C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ -#define REG_PWM_DT3 REG_ACCESS(RwReg, 0x4008C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ -#define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4008C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ -/* ========== Register definition for USART0 peripheral ========== */ -#define REG_USART0_CR REG_ACCESS(WoReg, 0x40090000U) /**< \brief (USART0) Control Register */ -#define REG_USART0_MR REG_ACCESS(RwReg, 0x40090004U) /**< \brief (USART0) Mode Register */ -#define REG_USART0_IER REG_ACCESS(WoReg, 0x40090008U) /**< \brief (USART0) Interrupt Enable Register */ -#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4009000CU) /**< \brief (USART0) Interrupt Disable Register */ -#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40090010U) /**< \brief (USART0) Interrupt Mask Register */ -#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40090014U) /**< \brief (USART0) Channel Status Register */ -#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40090018U) /**< \brief (USART0) Receiver Holding Register */ -#define REG_USART0_THR REG_ACCESS(WoReg, 0x4009001CU) /**< \brief (USART0) Transmitter Holding Register */ -#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40090020U) /**< \brief (USART0) Baud Rate Generator Register */ -#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40090024U) /**< \brief (USART0) Receiver Time-out Register */ -#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40090028U) /**< \brief (USART0) Transmitter Timeguard Register */ -#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40090040U) /**< \brief (USART0) FI DI Ratio Register */ -#define REG_USART0_NER REG_ACCESS(RoReg, 0x40090044U) /**< \brief (USART0) Number of Errors Register */ -#define REG_USART0_IF REG_ACCESS(RwReg, 0x4009004CU) /**< \brief (USART0) IrDA Filter Register */ -#define REG_USART0_MAN REG_ACCESS(RwReg, 0x40090050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ -#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400900E4U) /**< \brief (USART0) Write Protect Mode Register */ -#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400900E8U) /**< \brief (USART0) Write Protect Status Register */ -#define REG_USART0_VERSION REG_ACCESS(RoReg, 0x400900FCU) /**< \brief (USART0) Version Register */ -#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40090100U) /**< \brief (USART0) Receive Pointer Register */ -#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40090104U) /**< \brief (USART0) Receive Counter Register */ -#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40090108U) /**< \brief (USART0) Transmit Pointer Register */ -#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4009010CU) /**< \brief (USART0) Transmit Counter Register */ -#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40090110U) /**< \brief (USART0) Receive Next Pointer Register */ -#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40090114U) /**< \brief (USART0) Receive Next Counter Register */ -#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40090118U) /**< \brief (USART0) Transmit Next Pointer Register */ -#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4009011CU) /**< \brief (USART0) Transmit Next Counter Register */ -#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40090120U) /**< \brief (USART0) Transfer Control Register */ -#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40090124U) /**< \brief (USART0) Transfer Status Register */ -/* ========== Register definition for USART1 peripheral ========== */ -#define REG_USART1_CR REG_ACCESS(WoReg, 0x40094000U) /**< \brief (USART1) Control Register */ -#define REG_USART1_MR REG_ACCESS(RwReg, 0x40094004U) /**< \brief (USART1) Mode Register */ -#define REG_USART1_IER REG_ACCESS(WoReg, 0x40094008U) /**< \brief (USART1) Interrupt Enable Register */ -#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4009400CU) /**< \brief (USART1) Interrupt Disable Register */ -#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40094010U) /**< \brief (USART1) Interrupt Mask Register */ -#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40094014U) /**< \brief (USART1) Channel Status Register */ -#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40094018U) /**< \brief (USART1) Receiver Holding Register */ -#define REG_USART1_THR REG_ACCESS(WoReg, 0x4009401CU) /**< \brief (USART1) Transmitter Holding Register */ -#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40094020U) /**< \brief (USART1) Baud Rate Generator Register */ -#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40094024U) /**< \brief (USART1) Receiver Time-out Register */ -#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40094028U) /**< \brief (USART1) Transmitter Timeguard Register */ -#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40094040U) /**< \brief (USART1) FI DI Ratio Register */ -#define REG_USART1_NER REG_ACCESS(RoReg, 0x40094044U) /**< \brief (USART1) Number of Errors Register */ -#define REG_USART1_IF REG_ACCESS(RwReg, 0x4009404CU) /**< \brief (USART1) IrDA Filter Register */ -#define REG_USART1_MAN REG_ACCESS(RwReg, 0x40094050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ -#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400940E4U) /**< \brief (USART1) Write Protect Mode Register */ -#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400940E8U) /**< \brief (USART1) Write Protect Status Register */ -#define REG_USART1_VERSION REG_ACCESS(RoReg, 0x400940FCU) /**< \brief (USART1) Version Register */ -#define REG_USART1_RPR REG_ACCESS(RwReg, 0x40094100U) /**< \brief (USART1) Receive Pointer Register */ -#define REG_USART1_RCR REG_ACCESS(RwReg, 0x40094104U) /**< \brief (USART1) Receive Counter Register */ -#define REG_USART1_TPR REG_ACCESS(RwReg, 0x40094108U) /**< \brief (USART1) Transmit Pointer Register */ -#define REG_USART1_TCR REG_ACCESS(RwReg, 0x4009410CU) /**< \brief (USART1) Transmit Counter Register */ -#define REG_USART1_RNPR REG_ACCESS(RwReg, 0x40094110U) /**< \brief (USART1) Receive Next Pointer Register */ -#define REG_USART1_RNCR REG_ACCESS(RwReg, 0x40094114U) /**< \brief (USART1) Receive Next Counter Register */ -#define REG_USART1_TNPR REG_ACCESS(RwReg, 0x40094118U) /**< \brief (USART1) Transmit Next Pointer Register */ -#define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4009411CU) /**< \brief (USART1) Transmit Next Counter Register */ -#define REG_USART1_PTCR REG_ACCESS(WoReg, 0x40094120U) /**< \brief (USART1) Transfer Control Register */ -#define REG_USART1_PTSR REG_ACCESS(RoReg, 0x40094124U) /**< \brief (USART1) Transfer Status Register */ -/* ========== Register definition for USART2 peripheral ========== */ -#define REG_USART2_CR REG_ACCESS(WoReg, 0x40098000U) /**< \brief (USART2) Control Register */ -#define REG_USART2_MR REG_ACCESS(RwReg, 0x40098004U) /**< \brief (USART2) Mode Register */ -#define REG_USART2_IER REG_ACCESS(WoReg, 0x40098008U) /**< \brief (USART2) Interrupt Enable Register */ -#define REG_USART2_IDR REG_ACCESS(WoReg, 0x4009800CU) /**< \brief (USART2) Interrupt Disable Register */ -#define REG_USART2_IMR REG_ACCESS(RoReg, 0x40098010U) /**< \brief (USART2) Interrupt Mask Register */ -#define REG_USART2_CSR REG_ACCESS(RoReg, 0x40098014U) /**< \brief (USART2) Channel Status Register */ -#define REG_USART2_RHR REG_ACCESS(RoReg, 0x40098018U) /**< \brief (USART2) Receiver Holding Register */ -#define REG_USART2_THR REG_ACCESS(WoReg, 0x4009801CU) /**< \brief (USART2) Transmitter Holding Register */ -#define REG_USART2_BRGR REG_ACCESS(RwReg, 0x40098020U) /**< \brief (USART2) Baud Rate Generator Register */ -#define REG_USART2_RTOR REG_ACCESS(RwReg, 0x40098024U) /**< \brief (USART2) Receiver Time-out Register */ -#define REG_USART2_TTGR REG_ACCESS(RwReg, 0x40098028U) /**< \brief (USART2) Transmitter Timeguard Register */ -#define REG_USART2_FIDI REG_ACCESS(RwReg, 0x40098040U) /**< \brief (USART2) FI DI Ratio Register */ -#define REG_USART2_NER REG_ACCESS(RoReg, 0x40098044U) /**< \brief (USART2) Number of Errors Register */ -#define REG_USART2_IF REG_ACCESS(RwReg, 0x4009804CU) /**< \brief (USART2) IrDA Filter Register */ -#define REG_USART2_MAN REG_ACCESS(RwReg, 0x40098050U) /**< \brief (USART2) Manchester Encoder Decoder Register */ -#define REG_USART2_WPMR REG_ACCESS(RwReg, 0x400980E4U) /**< \brief (USART2) Write Protect Mode Register */ -#define REG_USART2_WPSR REG_ACCESS(RoReg, 0x400980E8U) /**< \brief (USART2) Write Protect Status Register */ -#define REG_USART2_VERSION REG_ACCESS(RoReg, 0x400980FCU) /**< \brief (USART2) Version Register */ -#define REG_USART2_RPR REG_ACCESS(RwReg, 0x40098100U) /**< \brief (USART2) Receive Pointer Register */ -#define REG_USART2_RCR REG_ACCESS(RwReg, 0x40098104U) /**< \brief (USART2) Receive Counter Register */ -#define REG_USART2_TPR REG_ACCESS(RwReg, 0x40098108U) /**< \brief (USART2) Transmit Pointer Register */ -#define REG_USART2_TCR REG_ACCESS(RwReg, 0x4009810CU) /**< \brief (USART2) Transmit Counter Register */ -#define REG_USART2_RNPR REG_ACCESS(RwReg, 0x40098110U) /**< \brief (USART2) Receive Next Pointer Register */ -#define REG_USART2_RNCR REG_ACCESS(RwReg, 0x40098114U) /**< \brief (USART2) Receive Next Counter Register */ -#define REG_USART2_TNPR REG_ACCESS(RwReg, 0x40098118U) /**< \brief (USART2) Transmit Next Pointer Register */ -#define REG_USART2_TNCR REG_ACCESS(RwReg, 0x4009811CU) /**< \brief (USART2) Transmit Next Counter Register */ -#define REG_USART2_PTCR REG_ACCESS(WoReg, 0x40098120U) /**< \brief (USART2) Transfer Control Register */ -#define REG_USART2_PTSR REG_ACCESS(RoReg, 0x40098124U) /**< \brief (USART2) Transfer Status Register */ -/* ========== Register definition for USART3 peripheral ========== */ -#define REG_USART3_CR REG_ACCESS(WoReg, 0x4009C000U) /**< \brief (USART3) Control Register */ -#define REG_USART3_MR REG_ACCESS(RwReg, 0x4009C004U) /**< \brief (USART3) Mode Register */ -#define REG_USART3_IER REG_ACCESS(WoReg, 0x4009C008U) /**< \brief (USART3) Interrupt Enable Register */ -#define REG_USART3_IDR REG_ACCESS(WoReg, 0x4009C00CU) /**< \brief (USART3) Interrupt Disable Register */ -#define REG_USART3_IMR REG_ACCESS(RoReg, 0x4009C010U) /**< \brief (USART3) Interrupt Mask Register */ -#define REG_USART3_CSR REG_ACCESS(RoReg, 0x4009C014U) /**< \brief (USART3) Channel Status Register */ -#define REG_USART3_RHR REG_ACCESS(RoReg, 0x4009C018U) /**< \brief (USART3) Receiver Holding Register */ -#define REG_USART3_THR REG_ACCESS(WoReg, 0x4009C01CU) /**< \brief (USART3) Transmitter Holding Register */ -#define REG_USART3_BRGR REG_ACCESS(RwReg, 0x4009C020U) /**< \brief (USART3) Baud Rate Generator Register */ -#define REG_USART3_RTOR REG_ACCESS(RwReg, 0x4009C024U) /**< \brief (USART3) Receiver Time-out Register */ -#define REG_USART3_TTGR REG_ACCESS(RwReg, 0x4009C028U) /**< \brief (USART3) Transmitter Timeguard Register */ -#define REG_USART3_FIDI REG_ACCESS(RwReg, 0x4009C040U) /**< \brief (USART3) FI DI Ratio Register */ -#define REG_USART3_NER REG_ACCESS(RoReg, 0x4009C044U) /**< \brief (USART3) Number of Errors Register */ -#define REG_USART3_IF REG_ACCESS(RwReg, 0x4009C04CU) /**< \brief (USART3) IrDA Filter Register */ -#define REG_USART3_MAN REG_ACCESS(RwReg, 0x4009C050U) /**< \brief (USART3) Manchester Encoder Decoder Register */ -#define REG_USART3_WPMR REG_ACCESS(RwReg, 0x4009C0E4U) /**< \brief (USART3) Write Protect Mode Register */ -#define REG_USART3_WPSR REG_ACCESS(RoReg, 0x4009C0E8U) /**< \brief (USART3) Write Protect Status Register */ -#define REG_USART3_VERSION REG_ACCESS(RoReg, 0x4009C0FCU) /**< \brief (USART3) Version Register */ -#define REG_USART3_RPR REG_ACCESS(RwReg, 0x4009C100U) /**< \brief (USART3) Receive Pointer Register */ -#define REG_USART3_RCR REG_ACCESS(RwReg, 0x4009C104U) /**< \brief (USART3) Receive Counter Register */ -#define REG_USART3_TPR REG_ACCESS(RwReg, 0x4009C108U) /**< \brief (USART3) Transmit Pointer Register */ -#define REG_USART3_TCR REG_ACCESS(RwReg, 0x4009C10CU) /**< \brief (USART3) Transmit Counter Register */ -#define REG_USART3_RNPR REG_ACCESS(RwReg, 0x4009C110U) /**< \brief (USART3) Receive Next Pointer Register */ -#define REG_USART3_RNCR REG_ACCESS(RwReg, 0x4009C114U) /**< \brief (USART3) Receive Next Counter Register */ -#define REG_USART3_TNPR REG_ACCESS(RwReg, 0x4009C118U) /**< \brief (USART3) Transmit Next Pointer Register */ -#define REG_USART3_TNCR REG_ACCESS(RwReg, 0x4009C11CU) /**< \brief (USART3) Transmit Next Counter Register */ -#define REG_USART3_PTCR REG_ACCESS(WoReg, 0x4009C120U) /**< \brief (USART3) Transfer Control Register */ -#define REG_USART3_PTSR REG_ACCESS(RoReg, 0x4009C124U) /**< \brief (USART3) Transfer Status Register */ -/* ========== Register definition for UDPHS peripheral ========== */ -#define REG_UDPHS_CTRL REG_ACCESS(RwReg, 0x400A4000U) /**< \brief (UDPHS) UDPHS Control Register */ -#define REG_UDPHS_FNUM REG_ACCESS(RoReg, 0x400A4004U) /**< \brief (UDPHS) UDPHS Frame Number Register */ -#define REG_UDPHS_IEN REG_ACCESS(RwReg, 0x400A4010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */ -#define REG_UDPHS_INTSTA REG_ACCESS(RoReg, 0x400A4014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */ -#define REG_UDPHS_CLRINT REG_ACCESS(WoReg, 0x400A4018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */ -#define REG_UDPHS_EPTRST REG_ACCESS(WoReg, 0x400A401CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */ -#define REG_UDPHS_TST REG_ACCESS(RwReg, 0x400A40E0U) /**< \brief (UDPHS) UDPHS Test Register */ -#define REG_UDPHS_IPNAME1 REG_ACCESS(RoReg, 0x400A40F0U) /**< \brief (UDPHS) UDPHS Name1 Register */ -#define REG_UDPHS_IPNAME2 REG_ACCESS(RoReg, 0x400A40F4U) /**< \brief (UDPHS) UDPHS Name2 Register */ -#define REG_UDPHS_IPFEATURES REG_ACCESS(RoReg, 0x400A40F8U) /**< \brief (UDPHS) UDPHS Features Register */ -#define REG_UDPHS_EPTCFG0 REG_ACCESS(RwReg, 0x400A4100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */ -#define REG_UDPHS_EPTCTLENB0 REG_ACCESS(WoReg, 0x400A4104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */ -#define REG_UDPHS_EPTCTLDIS0 REG_ACCESS(WoReg, 0x400A4108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */ -#define REG_UDPHS_EPTCTL0 REG_ACCESS(RoReg, 0x400A410CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */ -#define REG_UDPHS_EPTSETSTA0 REG_ACCESS(WoReg, 0x400A4114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */ -#define REG_UDPHS_EPTCLRSTA0 REG_ACCESS(WoReg, 0x400A4118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */ -#define REG_UDPHS_EPTSTA0 REG_ACCESS(RoReg, 0x400A411CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */ -#define REG_UDPHS_EPTCFG1 REG_ACCESS(RwReg, 0x400A4120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */ -#define REG_UDPHS_EPTCTLENB1 REG_ACCESS(WoReg, 0x400A4124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */ -#define REG_UDPHS_EPTCTLDIS1 REG_ACCESS(WoReg, 0x400A4128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */ -#define REG_UDPHS_EPTCTL1 REG_ACCESS(RoReg, 0x400A412CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */ -#define REG_UDPHS_EPTSETSTA1 REG_ACCESS(WoReg, 0x400A4134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */ -#define REG_UDPHS_EPTCLRSTA1 REG_ACCESS(WoReg, 0x400A4138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */ -#define REG_UDPHS_EPTSTA1 REG_ACCESS(RoReg, 0x400A413CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */ -#define REG_UDPHS_EPTCFG2 REG_ACCESS(RwReg, 0x400A4140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */ -#define REG_UDPHS_EPTCTLENB2 REG_ACCESS(WoReg, 0x400A4144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */ -#define REG_UDPHS_EPTCTLDIS2 REG_ACCESS(WoReg, 0x400A4148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */ -#define REG_UDPHS_EPTCTL2 REG_ACCESS(RoReg, 0x400A414CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */ -#define REG_UDPHS_EPTSETSTA2 REG_ACCESS(WoReg, 0x400A4154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */ -#define REG_UDPHS_EPTCLRSTA2 REG_ACCESS(WoReg, 0x400A4158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */ -#define REG_UDPHS_EPTSTA2 REG_ACCESS(RoReg, 0x400A415CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */ -#define REG_UDPHS_EPTCFG3 REG_ACCESS(RwReg, 0x400A4160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */ -#define REG_UDPHS_EPTCTLENB3 REG_ACCESS(WoReg, 0x400A4164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */ -#define REG_UDPHS_EPTCTLDIS3 REG_ACCESS(WoReg, 0x400A4168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */ -#define REG_UDPHS_EPTCTL3 REG_ACCESS(RoReg, 0x400A416CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */ -#define REG_UDPHS_EPTSETSTA3 REG_ACCESS(WoReg, 0x400A4174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */ -#define REG_UDPHS_EPTCLRSTA3 REG_ACCESS(WoReg, 0x400A4178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */ -#define REG_UDPHS_EPTSTA3 REG_ACCESS(RoReg, 0x400A417CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */ -#define REG_UDPHS_EPTCFG4 REG_ACCESS(RwReg, 0x400A4180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */ -#define REG_UDPHS_EPTCTLENB4 REG_ACCESS(WoReg, 0x400A4184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */ -#define REG_UDPHS_EPTCTLDIS4 REG_ACCESS(WoReg, 0x400A4188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */ -#define REG_UDPHS_EPTCTL4 REG_ACCESS(RoReg, 0x400A418CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */ -#define REG_UDPHS_EPTSETSTA4 REG_ACCESS(WoReg, 0x400A4194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */ -#define REG_UDPHS_EPTCLRSTA4 REG_ACCESS(WoReg, 0x400A4198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */ -#define REG_UDPHS_EPTSTA4 REG_ACCESS(RoReg, 0x400A419CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */ -#define REG_UDPHS_EPTCFG5 REG_ACCESS(RwReg, 0x400A41A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */ -#define REG_UDPHS_EPTCTLENB5 REG_ACCESS(WoReg, 0x400A41A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */ -#define REG_UDPHS_EPTCTLDIS5 REG_ACCESS(WoReg, 0x400A41A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */ -#define REG_UDPHS_EPTCTL5 REG_ACCESS(RoReg, 0x400A41ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */ -#define REG_UDPHS_EPTSETSTA5 REG_ACCESS(WoReg, 0x400A41B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */ -#define REG_UDPHS_EPTCLRSTA5 REG_ACCESS(WoReg, 0x400A41B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */ -#define REG_UDPHS_EPTSTA5 REG_ACCESS(RoReg, 0x400A41BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */ -#define REG_UDPHS_EPTCFG6 REG_ACCESS(RwReg, 0x400A41C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */ -#define REG_UDPHS_EPTCTLENB6 REG_ACCESS(WoReg, 0x400A41C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */ -#define REG_UDPHS_EPTCTLDIS6 REG_ACCESS(WoReg, 0x400A41C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */ -#define REG_UDPHS_EPTCTL6 REG_ACCESS(RoReg, 0x400A41CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */ -#define REG_UDPHS_EPTSETSTA6 REG_ACCESS(WoReg, 0x400A41D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */ -#define REG_UDPHS_EPTCLRSTA6 REG_ACCESS(WoReg, 0x400A41D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */ -#define REG_UDPHS_EPTSTA6 REG_ACCESS(RoReg, 0x400A41DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */ -#define REG_UDPHS_DMANXTDSC1 REG_ACCESS(RwReg, 0x400A4320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */ -#define REG_UDPHS_DMAADDRESS1 REG_ACCESS(RwReg, 0x400A4324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */ -#define REG_UDPHS_DMACONTROL1 REG_ACCESS(RwReg, 0x400A4328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */ -#define REG_UDPHS_DMASTATUS1 REG_ACCESS(RwReg, 0x400A432CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */ -#define REG_UDPHS_DMANXTDSC2 REG_ACCESS(RwReg, 0x400A4330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */ -#define REG_UDPHS_DMAADDRESS2 REG_ACCESS(RwReg, 0x400A4334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */ -#define REG_UDPHS_DMACONTROL2 REG_ACCESS(RwReg, 0x400A4338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */ -#define REG_UDPHS_DMASTATUS2 REG_ACCESS(RwReg, 0x400A433CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */ -#define REG_UDPHS_DMANXTDSC3 REG_ACCESS(RwReg, 0x400A4340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */ -#define REG_UDPHS_DMAADDRESS3 REG_ACCESS(RwReg, 0x400A4344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */ -#define REG_UDPHS_DMACONTROL3 REG_ACCESS(RwReg, 0x400A4348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */ -#define REG_UDPHS_DMASTATUS3 REG_ACCESS(RwReg, 0x400A434CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */ -#define REG_UDPHS_DMANXTDSC4 REG_ACCESS(RwReg, 0x400A4350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */ -#define REG_UDPHS_DMAADDRESS4 REG_ACCESS(RwReg, 0x400A4354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */ -#define REG_UDPHS_DMACONTROL4 REG_ACCESS(RwReg, 0x400A4358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */ -#define REG_UDPHS_DMASTATUS4 REG_ACCESS(RwReg, 0x400A435CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */ -#define REG_UDPHS_DMANXTDSC5 REG_ACCESS(RwReg, 0x400A4360U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */ -#define REG_UDPHS_DMAADDRESS5 REG_ACCESS(RwReg, 0x400A4364U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */ -#define REG_UDPHS_DMACONTROL5 REG_ACCESS(RwReg, 0x400A4368U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */ -#define REG_UDPHS_DMASTATUS5 REG_ACCESS(RwReg, 0x400A436CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */ -/* ========== Register definition for ADC12B peripheral ========== */ -#define REG_ADC12B_CR REG_ACCESS(WoReg, 0x400A8000U) /**< \brief (ADC12B) Control Register */ -#define REG_ADC12B_MR REG_ACCESS(RwReg, 0x400A8004U) /**< \brief (ADC12B) Mode Register */ -#define REG_ADC12B_CHER REG_ACCESS(WoReg, 0x400A8010U) /**< \brief (ADC12B) Channel Enable Register */ -#define REG_ADC12B_CHDR REG_ACCESS(WoReg, 0x400A8014U) /**< \brief (ADC12B) Channel Disable Register */ -#define REG_ADC12B_CHSR REG_ACCESS(RoReg, 0x400A8018U) /**< \brief (ADC12B) Channel Status Register */ -#define REG_ADC12B_SR REG_ACCESS(RoReg, 0x400A801CU) /**< \brief (ADC12B) Status Register */ -#define REG_ADC12B_LCDR REG_ACCESS(RoReg, 0x400A8020U) /**< \brief (ADC12B) Last Converted Data Register */ -#define REG_ADC12B_IER REG_ACCESS(WoReg, 0x400A8024U) /**< \brief (ADC12B) Interrupt Enable Register */ -#define REG_ADC12B_IDR REG_ACCESS(WoReg, 0x400A8028U) /**< \brief (ADC12B) Interrupt Disable Register */ -#define REG_ADC12B_IMR REG_ACCESS(RoReg, 0x400A802CU) /**< \brief (ADC12B) Interrupt Mask Register */ -#define REG_ADC12B_CDR REG_ACCESS(RoReg, 0x400A8030U) /**< \brief (ADC12B) Channel Data Register */ -#define REG_ADC12B_ACR REG_ACCESS(RwReg, 0x400A8064U) /**< \brief (ADC12B) Analog Control Register */ -#define REG_ADC12B_EMR REG_ACCESS(RwReg, 0x400A8068U) /**< \brief (ADC12B) Extended Mode Register */ -#define REG_ADC12B_RPR REG_ACCESS(RwReg, 0x400A8100U) /**< \brief (ADC12B) Receive Pointer Register */ -#define REG_ADC12B_RCR REG_ACCESS(RwReg, 0x400A8104U) /**< \brief (ADC12B) Receive Counter Register */ -#define REG_ADC12B_TPR REG_ACCESS(RwReg, 0x400A8108U) /**< \brief (ADC12B) Transmit Pointer Register */ -#define REG_ADC12B_TCR REG_ACCESS(RwReg, 0x400A810CU) /**< \brief (ADC12B) Transmit Counter Register */ -#define REG_ADC12B_RNPR REG_ACCESS(RwReg, 0x400A8110U) /**< \brief (ADC12B) Receive Next Pointer Register */ -#define REG_ADC12B_RNCR REG_ACCESS(RwReg, 0x400A8114U) /**< \brief (ADC12B) Receive Next Counter Register */ -#define REG_ADC12B_TNPR REG_ACCESS(RwReg, 0x400A8118U) /**< \brief (ADC12B) Transmit Next Pointer Register */ -#define REG_ADC12B_TNCR REG_ACCESS(RwReg, 0x400A811CU) /**< \brief (ADC12B) Transmit Next Counter Register */ -#define REG_ADC12B_PTCR REG_ACCESS(WoReg, 0x400A8120U) /**< \brief (ADC12B) Transfer Control Register */ -#define REG_ADC12B_PTSR REG_ACCESS(RoReg, 0x400A8124U) /**< \brief (ADC12B) Transfer Status Register */ -/* ========== Register definition for ADC peripheral ========== */ -#define REG_ADC_CR REG_ACCESS(WoReg, 0x400AC000U) /**< \brief (ADC) Control Register */ -#define REG_ADC_MR REG_ACCESS(RwReg, 0x400AC004U) /**< \brief (ADC) Mode Register */ -#define REG_ADC_CHER REG_ACCESS(WoReg, 0x400AC010U) /**< \brief (ADC) Channel Enable Register */ -#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x400AC014U) /**< \brief (ADC) Channel Disable Register */ -#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x400AC018U) /**< \brief (ADC) Channel Status Register */ -#define REG_ADC_SR REG_ACCESS(RoReg, 0x400AC01CU) /**< \brief (ADC) Status Register */ -#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x400AC020U) /**< \brief (ADC) Last Converted Data Register */ -#define REG_ADC_IER REG_ACCESS(WoReg, 0x400AC024U) /**< \brief (ADC) Interrupt Enable Register */ -#define REG_ADC_IDR REG_ACCESS(WoReg, 0x400AC028U) /**< \brief (ADC) Interrupt Disable Register */ -#define REG_ADC_IMR REG_ACCESS(RoReg, 0x400AC02CU) /**< \brief (ADC) Interrupt Mask Register */ -#define REG_ADC_CDR REG_ACCESS(RoReg, 0x400AC030U) /**< \brief (ADC) Channel Data Register */ -#define REG_ADC_RPR REG_ACCESS(RwReg, 0x400AC100U) /**< \brief (ADC) Receive Pointer Register */ -#define REG_ADC_RCR REG_ACCESS(RwReg, 0x400AC104U) /**< \brief (ADC) Receive Counter Register */ -#define REG_ADC_TPR REG_ACCESS(RwReg, 0x400AC108U) /**< \brief (ADC) Transmit Pointer Register */ -#define REG_ADC_TCR REG_ACCESS(RwReg, 0x400AC10CU) /**< \brief (ADC) Transmit Counter Register */ -#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x400AC110U) /**< \brief (ADC) Receive Next Pointer Register */ -#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x400AC114U) /**< \brief (ADC) Receive Next Counter Register */ -#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x400AC118U) /**< \brief (ADC) Transmit Next Pointer Register */ -#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x400AC11CU) /**< \brief (ADC) Transmit Next Counter Register */ -#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x400AC120U) /**< \brief (ADC) Transfer Control Register */ -#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x400AC124U) /**< \brief (ADC) Transfer Status Register */ -/* ========== Register definition for DMAC peripheral ========== */ -#define REG_DMAC_GCFG REG_ACCESS(RwReg, 0x400B0000U) /**< \brief (DMAC) DMAC Global Configuration Register */ -#define REG_DMAC_EN REG_ACCESS(RwReg, 0x400B0004U) /**< \brief (DMAC) DMAC Enable Register */ -#define REG_DMAC_SREQ REG_ACCESS(RwReg, 0x400B0008U) /**< \brief (DMAC) DMAC Software Single Request Register */ -#define REG_DMAC_CREQ REG_ACCESS(RwReg, 0x400B000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */ -#define REG_DMAC_LAST REG_ACCESS(RwReg, 0x400B0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */ -#define REG_DMAC_EBCIER REG_ACCESS(WoReg, 0x400B0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. */ -#define REG_DMAC_EBCIDR REG_ACCESS(WoReg, 0x400B001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. */ -#define REG_DMAC_EBCIMR REG_ACCESS(RoReg, 0x400B0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. */ -#define REG_DMAC_EBCISR REG_ACCESS(RoReg, 0x400B0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. */ -#define REG_DMAC_CHER REG_ACCESS(WoReg, 0x400B0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */ -#define REG_DMAC_CHDR REG_ACCESS(WoReg, 0x400B002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */ -#define REG_DMAC_CHSR REG_ACCESS(RoReg, 0x400B0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */ -#define REG_DMAC_SADDR0 REG_ACCESS(RwReg, 0x400B003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */ -#define REG_DMAC_DADDR0 REG_ACCESS(RwReg, 0x400B0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */ -#define REG_DMAC_DSCR0 REG_ACCESS(RwReg, 0x400B0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */ -#define REG_DMAC_CTRLA0 REG_ACCESS(RwReg, 0x400B0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */ -#define REG_DMAC_CTRLB0 REG_ACCESS(RwReg, 0x400B004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */ -#define REG_DMAC_CFG0 REG_ACCESS(RwReg, 0x400B0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */ -#define REG_DMAC_SADDR1 REG_ACCESS(RwReg, 0x400B0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */ -#define REG_DMAC_DADDR1 REG_ACCESS(RwReg, 0x400B0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */ -#define REG_DMAC_DSCR1 REG_ACCESS(RwReg, 0x400B006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */ -#define REG_DMAC_CTRLA1 REG_ACCESS(RwReg, 0x400B0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */ -#define REG_DMAC_CTRLB1 REG_ACCESS(RwReg, 0x400B0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */ -#define REG_DMAC_CFG1 REG_ACCESS(RwReg, 0x400B0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */ -#define REG_DMAC_SADDR2 REG_ACCESS(RwReg, 0x400B008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */ -#define REG_DMAC_DADDR2 REG_ACCESS(RwReg, 0x400B0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */ -#define REG_DMAC_DSCR2 REG_ACCESS(RwReg, 0x400B0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */ -#define REG_DMAC_CTRLA2 REG_ACCESS(RwReg, 0x400B0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */ -#define REG_DMAC_CTRLB2 REG_ACCESS(RwReg, 0x400B009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */ -#define REG_DMAC_CFG2 REG_ACCESS(RwReg, 0x400B00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */ -#define REG_DMAC_SADDR3 REG_ACCESS(RwReg, 0x400B00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */ -#define REG_DMAC_DADDR3 REG_ACCESS(RwReg, 0x400B00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */ -#define REG_DMAC_DSCR3 REG_ACCESS(RwReg, 0x400B00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */ -#define REG_DMAC_CTRLA3 REG_ACCESS(RwReg, 0x400B00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */ -#define REG_DMAC_CTRLB3 REG_ACCESS(RwReg, 0x400B00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */ -#define REG_DMAC_CFG3 REG_ACCESS(RwReg, 0x400B00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */ -/* ========== Register definition for SMC peripheral ========== */ -#define REG_SMC_CFG REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */ -#define REG_SMC_CTRL REG_ACCESS(WoReg, 0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */ -#define REG_SMC_SR REG_ACCESS(RoReg, 0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */ -#define REG_SMC_IER REG_ACCESS(WoReg, 0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */ -#define REG_SMC_IDR REG_ACCESS(WoReg, 0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */ -#define REG_SMC_IMR REG_ACCESS(RoReg, 0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */ -#define REG_SMC_ADDR REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */ -#define REG_SMC_BANK REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */ -#define REG_SMC_ECC_CTRL REG_ACCESS(WoReg, 0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */ -#define REG_SMC_ECC_MD REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */ -#define REG_SMC_ECC_SR1 REG_ACCESS(RoReg, 0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */ -#define REG_SMC_ECC_PR0 REG_ACCESS(RoReg, 0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */ -#define REG_SMC_ECC_PR1 REG_ACCESS(RoReg, 0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */ -#define REG_SMC_ECC_SR2 REG_ACCESS(RoReg, 0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */ -#define REG_SMC_ECC_PR2 REG_ACCESS(RoReg, 0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */ -#define REG_SMC_ECC_PR3 REG_ACCESS(RoReg, 0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */ -#define REG_SMC_ECC_PR4 REG_ACCESS(RoReg, 0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */ -#define REG_SMC_ECC_PR5 REG_ACCESS(RoReg, 0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */ -#define REG_SMC_ECC_PR6 REG_ACCESS(RoReg, 0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */ -#define REG_SMC_ECC_PR7 REG_ACCESS(RoReg, 0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */ -#define REG_SMC_ECC_PR8 REG_ACCESS(RoReg, 0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */ -#define REG_SMC_ECC_PR9 REG_ACCESS(RoReg, 0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */ -#define REG_SMC_ECC_PR10 REG_ACCESS(RoReg, 0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */ -#define REG_SMC_ECC_PR11 REG_ACCESS(RoReg, 0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */ -#define REG_SMC_ECC_PR12 REG_ACCESS(RoReg, 0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */ -#define REG_SMC_ECC_PR13 REG_ACCESS(RoReg, 0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */ -#define REG_SMC_ECC_PR14 REG_ACCESS(RoReg, 0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */ -#define REG_SMC_ECC_PR15 REG_ACCESS(RoReg, 0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */ -#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0070U) /**< \brief (SMC) SMC SETUP Register (CS_number = 0) */ -#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0074U) /**< \brief (SMC) SMC PULSE Register (CS_number = 0) */ -#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0078U) /**< \brief (SMC) SMC CYCLE Register (CS_number = 0) */ -#define REG_SMC_TIMINGS0 REG_ACCESS(RwReg, 0x400E007CU) /**< \brief (SMC) SMC TIMINGS Register (CS_number = 0) */ -#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC MODE Register (CS_number = 0) */ -#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0084U) /**< \brief (SMC) SMC SETUP Register (CS_number = 1) */ -#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0088U) /**< \brief (SMC) SMC PULSE Register (CS_number = 1) */ -#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E008CU) /**< \brief (SMC) SMC CYCLE Register (CS_number = 1) */ -#define REG_SMC_TIMINGS1 REG_ACCESS(RwReg, 0x400E0090U) /**< \brief (SMC) SMC TIMINGS Register (CS_number = 1) */ -#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E0094U) /**< \brief (SMC) SMC MODE Register (CS_number = 1) */ -#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0098U) /**< \brief (SMC) SMC SETUP Register (CS_number = 2) */ -#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E009CU) /**< \brief (SMC) SMC PULSE Register (CS_number = 2) */ -#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E00A0U) /**< \brief (SMC) SMC CYCLE Register (CS_number = 2) */ -#define REG_SMC_TIMINGS2 REG_ACCESS(RwReg, 0x400E00A4U) /**< \brief (SMC) SMC TIMINGS Register (CS_number = 2) */ -#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E00A8U) /**< \brief (SMC) SMC MODE Register (CS_number = 2) */ -#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E00ACU) /**< \brief (SMC) SMC SETUP Register (CS_number = 3) */ -#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E00B0U) /**< \brief (SMC) SMC PULSE Register (CS_number = 3) */ -#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E00B4U) /**< \brief (SMC) SMC CYCLE Register (CS_number = 3) */ -#define REG_SMC_TIMINGS3 REG_ACCESS(RwReg, 0x400E00B8U) /**< \brief (SMC) SMC TIMINGS Register (CS_number = 3) */ -#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E00BCU) /**< \brief (SMC) SMC MODE Register (CS_number = 3) */ -#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0110U) /**< \brief (SMC) SMC OCMS MODE Register */ -#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0114U) /**< \brief (SMC) SMC KEY1 Register */ -#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0118U) /**< \brief (SMC) SMC KEY2 Register */ -#define REG_SMC_WPCR REG_ACCESS(WoReg, 0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */ -#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */ -/* ========== Register definition for MATRIX peripheral ========== */ -#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ -#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ -#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ -#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ -#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ -#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ -#define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ -#define REG_MATRIX_PRAS5 REG_ACCESS(RwReg, 0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ -#define REG_MATRIX_PRAS6 REG_ACCESS(RwReg, 0x400E02B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ -#define REG_MATRIX_PRAS7 REG_ACCESS(RwReg, 0x400E02B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ -#define REG_MATRIX_PRAS8 REG_ACCESS(RwReg, 0x400E02C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ -#define REG_MATRIX_PRAS9 REG_ACCESS(RwReg, 0x400E02C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */ -#define REG_MATRIX_MRCR REG_ACCESS(RwReg, 0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */ -/* ========== Register definition for PMC peripheral ========== */ -#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ -#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ -#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */ -#define REG_PMC_PCER REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register */ -#define REG_PMC_PCDR REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register */ -//#define REG_PMC_PCSR REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register */ -#define REG_PMC_UCKR REG_ACCESS(RwReg, 0x400E041CU) /**< \brief (PMC) UTMI Clock Register */ -#define REG_PMC_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ -#define REG_PMC_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ -#define REG_PMC_PLLAR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */ -#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */ -#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ -#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ -#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ -#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */ -#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ -#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ -#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ -#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ -/* ========== Register definition for UART peripheral ========== */ -#define REG_UART_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART) Control Register */ -#define REG_UART_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART) Mode Register */ -#define REG_UART_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART) Interrupt Enable Register */ -#define REG_UART_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART) Interrupt Disable Register */ -#define REG_UART_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART) Interrupt Mask Register */ -#define REG_UART_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART) Status Register */ -#define REG_UART_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART) Receive Holding Register */ -#define REG_UART_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART) Transmit Holding Register */ -#define REG_UART_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART) Baud Rate Generator Register */ -#define REG_UART_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART) Receive Pointer Register */ -#define REG_UART_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART) Receive Counter Register */ -#define REG_UART_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART) Transmit Pointer Register */ -#define REG_UART_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART) Transmit Counter Register */ -#define REG_UART_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART) Receive Next Pointer Register */ -#define REG_UART_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART) Receive Next Counter Register */ -#define REG_UART_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART) Transmit Next Pointer Register */ -#define REG_UART_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART) Transmit Next Counter Register */ -#define REG_UART_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART) Transfer Control Register */ -#define REG_UART_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART) Transfer Status Register */ -/* ========== Register definition for CHIPID peripheral ========== */ -#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ -#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ -/* ========== Register definition for EFC0 peripheral ========== */ -#define REG_EFC0_FMR REG_ACCESS(RwReg, 0x400E0800U) /**< \brief (EFC0) EEFC Flash Mode Register */ -#define REG_EFC0_FCR REG_ACCESS(WoReg, 0x400E0804U) /**< \brief (EFC0) EEFC Flash Command Register */ -#define REG_EFC0_FSR REG_ACCESS(RoReg, 0x400E0808U) /**< \brief (EFC0) EEFC Flash Status Register */ -#define REG_EFC0_FRR REG_ACCESS(RoReg, 0x400E080CU) /**< \brief (EFC0) EEFC Flash Result Register */ -/* ========== Register definition for EFC1 peripheral ========== */ -#define REG_EFC1_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC1) EEFC Flash Mode Register */ -#define REG_EFC1_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC1) EEFC Flash Command Register */ -#define REG_EFC1_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC1) EEFC Flash Status Register */ -#define REG_EFC1_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC1) EEFC Flash Result Register */ -/* ========== Register definition for PIOA peripheral ========== */ -#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0C00U) /**< \brief (PIOA) PIO Enable Register */ -#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0C04U) /**< \brief (PIOA) PIO Disable Register */ -#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0C08U) /**< \brief (PIOA) PIO Status Register */ -#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0C10U) /**< \brief (PIOA) Output Enable Register */ -#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0C14U) /**< \brief (PIOA) Output Disable Register */ -#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0C18U) /**< \brief (PIOA) Output Status Register */ -#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0C20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ -#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0C24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ -#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0C28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ -#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0C30U) /**< \brief (PIOA) Set Output Data Register */ -#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0C34U) /**< \brief (PIOA) Clear Output Data Register */ -#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0C38U) /**< \brief (PIOA) Output Data Status Register */ -#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0C3CU) /**< \brief (PIOA) Pin Data Status Register */ -#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0C40U) /**< \brief (PIOA) Interrupt Enable Register */ -#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0C44U) /**< \brief (PIOA) Interrupt Disable Register */ -#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0C48U) /**< \brief (PIOA) Interrupt Mask Register */ -#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0C4CU) /**< \brief (PIOA) Interrupt Status Register */ -#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0C50U) /**< \brief (PIOA) Multi-driver Enable Register */ -#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0C54U) /**< \brief (PIOA) Multi-driver Disable Register */ -#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0C58U) /**< \brief (PIOA) Multi-driver Status Register */ -#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0C60U) /**< \brief (PIOA) Pull-up Disable Register */ -#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0C64U) /**< \brief (PIOA) Pull-up Enable Register */ -#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0C68U) /**< \brief (PIOA) Pad Pull-up Status Register */ -#define REG_PIOA_ABSR REG_ACCESS(RwReg, 0x400E0C70U) /**< \brief (PIOA) Peripheral AB Select Register */ -#define REG_PIOA_SCIFSR REG_ACCESS(WoReg, 0x400E0C80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ -#define REG_PIOA_DIFSR REG_ACCESS(WoReg, 0x400E0C84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ -#define REG_PIOA_IFDGSR REG_ACCESS(RoReg, 0x400E0C88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0C8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ -#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0CA0U) /**< \brief (PIOA) Output Write Enable */ -#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0CA4U) /**< \brief (PIOA) Output Write Disable */ -#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0CA8U) /**< \brief (PIOA) Output Write Status Register */ -#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0CB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ -#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0CB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ -#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0CB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ -#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0CC0U) /**< \brief (PIOA) Edge Select Register */ -#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0CC4U) /**< \brief (PIOA) Level Select Register */ -#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0CC8U) /**< \brief (PIOA) Edge/Level Status Register */ -#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0CD0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ -#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0CD4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ -#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0CD8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ -#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0CE0U) /**< \brief (PIOA) Lock Status */ -#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0CE4U) /**< \brief (PIOA) Write Protect Mode Register */ -#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0CE8U) /**< \brief (PIOA) Write Protect Status Register */ -/* ========== Register definition for PIOB peripheral ========== */ -#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOB) PIO Enable Register */ -#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOB) PIO Disable Register */ -#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOB) PIO Status Register */ -#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOB) Output Enable Register */ -#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOB) Output Disable Register */ -#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOB) Output Status Register */ -#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ -#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ -#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOB) Glitch Input Filter Status Register */ -#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOB) Set Output Data Register */ -#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOB) Clear Output Data Register */ -#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOB) Output Data Status Register */ -#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOB) Pin Data Status Register */ -#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOB) Interrupt Enable Register */ -#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOB) Interrupt Disable Register */ -#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOB) Interrupt Mask Register */ -#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOB) Interrupt Status Register */ -#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOB) Multi-driver Enable Register */ -#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOB) Multi-driver Disable Register */ -#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOB) Multi-driver Status Register */ -#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOB) Pull-up Disable Register */ -#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOB) Pull-up Enable Register */ -#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOB) Pad Pull-up Status Register */ -#define REG_PIOB_ABSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOB) Peripheral AB Select Register */ -#define REG_PIOB_SCIFSR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ -#define REG_PIOB_DIFSR REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ -#define REG_PIOB_IFDGSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ -#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOB) Output Write Enable */ -#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOB) Output Write Disable */ -#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOB) Output Write Status Register */ -#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ -#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ -#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ -#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOB) Edge Select Register */ -#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOB) Level Select Register */ -#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOB) Edge/Level Status Register */ -#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ -#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ -#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ -#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOB) Lock Status */ -#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOB) Write Protect Mode Register */ -#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOB) Write Protect Status Register */ -/* ========== Register definition for PIOC peripheral ========== */ -#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOC) PIO Enable Register */ -#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOC) PIO Disable Register */ -#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOC) PIO Status Register */ -#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOC) Output Enable Register */ -#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOC) Output Disable Register */ -#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOC) Output Status Register */ -#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ -#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ -#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOC) Glitch Input Filter Status Register */ -#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOC) Set Output Data Register */ -#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOC) Clear Output Data Register */ -#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOC) Output Data Status Register */ -#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOC) Pin Data Status Register */ -#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOC) Interrupt Enable Register */ -#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOC) Interrupt Disable Register */ -#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOC) Interrupt Mask Register */ -#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOC) Interrupt Status Register */ -#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOC) Multi-driver Enable Register */ -#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOC) Multi-driver Disable Register */ -#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOC) Multi-driver Status Register */ -#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOC) Pull-up Disable Register */ -#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOC) Pull-up Enable Register */ -#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOC) Pad Pull-up Status Register */ -#define REG_PIOC_ABSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOC) Peripheral AB Select Register */ -#define REG_PIOC_SCIFSR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ -#define REG_PIOC_DIFSR REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ -#define REG_PIOC_IFDGSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ -#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOC) Output Write Enable */ -#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOC) Output Write Disable */ -#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOC) Output Write Status Register */ -#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ -#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ -#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ -#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOC) Edge Select Register */ -#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOC) Level Select Register */ -#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOC) Edge/Level Status Register */ -#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ -#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ -#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ -#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOC) Lock Status */ -#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOC) Write Protect Mode Register */ -#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOC) Write Protect Status Register */ -/* ========== Register definition for RSTC peripheral ========== */ -#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (RSTC) Control Register */ -#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1204U) /**< \brief (RSTC) Status Register */ -#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1208U) /**< \brief (RSTC) Mode Register */ -/* ========== Register definition for SUPC peripheral ========== */ -#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (SUPC) Supply Controller Control Register */ -#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1214U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ -#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1218U) /**< \brief (SUPC) Supply Controller Mode Register */ -#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E121CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ -#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1220U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ -#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1224U) /**< \brief (SUPC) Supply Controller Status Register */ -/* ========== Register definition for RTT peripheral ========== */ -#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1230U) /**< \brief (RTT) Mode Register */ -#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1234U) /**< \brief (RTT) Alarm Register */ -#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1238U) /**< \brief (RTT) Value Register */ -#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (RTT) Status Register */ -/* ========== Register definition for WDT peripheral ========== */ -#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (WDT) Control Register */ -#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1254U) /**< \brief (WDT) Mode Register */ -#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (WDT) Status Register */ -/* ========== Register definition for RTC peripheral ========== */ -#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1260U) /**< \brief (RTC) Control Register */ -#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1264U) /**< \brief (RTC) Mode Register */ -#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1268U) /**< \brief (RTC) Time Register */ -#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E126CU) /**< \brief (RTC) Calendar Register */ -#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (RTC) Time Alarm Register */ -#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1274U) /**< \brief (RTC) Calendar Alarm Register */ -#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1278U) /**< \brief (RTC) Status Register */ -#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E127CU) /**< \brief (RTC) Status Clear Command Register */ -#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (RTC) Interrupt Enable Register */ -#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (RTC) Interrupt Disable Register */ -#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (RTC) Interrupt Mask Register */ -#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E128CU) /**< \brief (RTC) Valid Entry Register */ -/* ========== Register definition for GPBR peripheral ========== */ -#define REG_GPBR_GPBR0 REG_ACCESS(RwReg, 0x400E1290U) /**< \brief (GPBR) General Purpose Backup Register 0 */ -#define REG_GPBR_GPBR1 REG_ACCESS(RwReg, 0x400E1294U) /**< \brief (GPBR) General Purpose Backup Register 1 */ -#define REG_GPBR_GPBR2 REG_ACCESS(RwReg, 0x400E1298U) /**< \brief (GPBR) General Purpose Backup Register 2 */ -#define REG_GPBR_GPBR3 REG_ACCESS(RwReg, 0x400E129CU) /**< \brief (GPBR) General Purpose Backup Register 3 */ -/*@}*/ - -/* ***************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR AT91SAM3U */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3U_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC0 ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */ -#define ID_EFC1 ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */ -#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */ -#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ -#define ID_PIOA (10) /**< \brief Parallel I/O Controller A, (PIOA) */ -#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ -#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ -#define ID_USART3 (16) /**< \brief USART 3 (USART3) */ -#define ID_HSMCI (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (18) /**< \brief Two-Wire Interface 0 (TWI0) */ -#define ID_TWI1 (19) /**< \brief Two-Wire Interface 1 (TWI1) */ -#define ID_SPI (20) /**< \brief Serial Peripheral Interface (SPI) */ -#define ID_SSC (21) /**< \brief Synchronous Serial Controller (SSC) */ -#define ID_TC0 (22) /**< \brief Timer Counter 0 (TC0) */ -#define ID_TC1 (23) /**< \brief Timer Counter 1 (TC1) */ -#define ID_TC2 (24) /**< \brief Timer Counter 2 (TC2) */ -#define ID_PWM (25) /**< \brief Pulse Width Modulation Controller (PWM) */ -#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */ -#define ID_ADC (27) /**< \brief 10-bit ADC Controller (ADC) */ -#define ID_DMAC (28) /**< \brief DMA Controller (DMAC) */ -#define ID_UDPHS (29) /**< \brief USB Device High Speed (UDPHS) */ -/*@}*/ - -/* ***************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR AT91SAM3U */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3U_base Peripheral Base Address Definitions */ -/*@{*/ - -#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */ -#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */ -#define TC0 CAST(Tc , 0x40080000U) /**< \brief (TC0 ) Base Address */ -#define TWI0 CAST(Twi , 0x40084000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 CAST(Pdc , 0x40084100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 CAST(Twi , 0x40088000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 CAST(Pdc , 0x40088100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM CAST(Pwm , 0x4008C000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM CAST(Pdc , 0x4008C100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 CAST(Usart , 0x40090000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 CAST(Pdc , 0x40090100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 CAST(Usart , 0x40094000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 CAST(Pdc , 0x40094100U) /**< \brief (PDC_USART1) Base Address */ -#define USART2 CAST(Usart , 0x40098000U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 CAST(Pdc , 0x40098100U) /**< \brief (PDC_USART2) Base Address */ -#define USART3 CAST(Usart , 0x4009C000U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 CAST(Pdc , 0x4009C100U) /**< \brief (PDC_USART3) Base Address */ -#define UDPHS CAST(Udphs , 0x400A4000U) /**< \brief (UDPHS ) Base Address */ -#define ADC12B CAST(Adc12b , 0x400A8000U) /**< \brief (ADC12B ) Base Address */ -#define PDC_ADC12B CAST(Pdc , 0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */ -#define ADC CAST(Adc , 0x400AC000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC CAST(Pdc , 0x400AC100U) /**< \brief (PDC_ADC ) Base Address */ -#define DMAC CAST(Dmac , 0x400B0000U) /**< \brief (DMAC ) Base Address */ -#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */ -#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */ -#define UART CAST(Uart , 0x400E0600U) /**< \brief (UART ) Base Address */ -#define PDC_UART CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART ) Base Address */ -#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC0 CAST(Efc , 0x400E0800U) /**< \brief (EFC0 ) Base Address */ -#define EFC1 CAST(Efc , 0x400E0A00U) /**< \brief (EFC1 ) Base Address */ -#define PIOA CAST(Pio , 0x400E0C00U) /**< \brief (PIOA ) Base Address */ -#define PIOB CAST(Pio , 0x400E0E00U) /**< \brief (PIOB ) Base Address */ -#define PIOC CAST(Pio , 0x400E1000U) /**< \brief (PIOC ) Base Address */ -#define RSTC CAST(Rstc , 0x400E1200U) /**< \brief (RSTC ) Base Address */ -#define SUPC CAST(Supc , 0x400E1210U) /**< \brief (SUPC ) Base Address */ -#define RTT CAST(Rtt , 0x400E1230U) /**< \brief (RTT ) Base Address */ -#define WDT CAST(Wdt , 0x400E1250U) /**< \brief (WDT ) Base Address */ -#define RTC CAST(Rtc , 0x400E1260U) /**< \brief (RTC ) Base Address */ -#define GPBR CAST(Gpbr , 0x400E1290U) /**< \brief (GPBR ) Base Address */ -/*@}*/ - -/* ***************************************************************************** */ -/* PIO DEFINITIONS FOR AT91SAM3U */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3U_pio Peripheral Pio Definitions */ -/*@{*/ - -#define PIO_PA0 (1 << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1 << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1 << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1 << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1 << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1 << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1 << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1 << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1 << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1 << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1 << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1 << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1 << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1 << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1 << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1 << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1 << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1 << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1 << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1 << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1 << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1 << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1 << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1 << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1 << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1 << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1 << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1 << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1 << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1 << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1 << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1 << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1 << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1 << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1 << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1 << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1 << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1 << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1 << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1 << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1 << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1 << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1 << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1 << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1 << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1 << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1 << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PB15 (1 << 15) /**< \brief Pin Controlled by PB15 */ -#define PIO_PB16 (1 << 16) /**< \brief Pin Controlled by PB16 */ -#define PIO_PB17 (1 << 17) /**< \brief Pin Controlled by PB17 */ -#define PIO_PB18 (1 << 18) /**< \brief Pin Controlled by PB18 */ -#define PIO_PB19 (1 << 19) /**< \brief Pin Controlled by PB19 */ -#define PIO_PB20 (1 << 20) /**< \brief Pin Controlled by PB20 */ -#define PIO_PB21 (1 << 21) /**< \brief Pin Controlled by PB21 */ -#define PIO_PB22 (1 << 22) /**< \brief Pin Controlled by PB22 */ -#define PIO_PB23 (1 << 23) /**< \brief Pin Controlled by PB23 */ -#define PIO_PB24 (1 << 24) /**< \brief Pin Controlled by PB24 */ -#define PIO_PB25 (1 << 25) /**< \brief Pin Controlled by PB25 */ -#define PIO_PB26 (1 << 26) /**< \brief Pin Controlled by PB26 */ -#define PIO_PB27 (1 << 27) /**< \brief Pin Controlled by PB27 */ -#define PIO_PB28 (1 << 28) /**< \brief Pin Controlled by PB28 */ -#define PIO_PB29 (1 << 29) /**< \brief Pin Controlled by PB29 */ -#define PIO_PB30 (1 << 30) /**< \brief Pin Controlled by PB30 */ -#define PIO_PB31 (1 << 31) /**< \brief Pin Controlled by PB31 */ -#define PIO_PC0 (1 << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1 << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1 << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1 << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1 << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1 << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1 << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1 << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1 << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1 << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1 << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1 << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1 << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1 << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1 << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1 << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1 << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1 << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1 << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1 << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1 << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1 << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1 << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1 << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1 << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1 << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1 << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1 << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1 << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1 << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1 << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PC31 (1 << 31) /**< \brief Pin Controlled by PC31 */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA4A_MCCDA (1 << 4) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PA3A_MCCK (1 << 3) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA5A_MCDA0 (1 << 5) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA6A_MCDA1 (1 << 6) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA7A_MCDA2 (1 << 7) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA8A_MCDA3 (1 << 8) /**< \brief Hsmci signal: MCDA3 */ -#define PIO_PC28B_MCDA4 (1 << 28) /**< \brief Hsmci signal: MCDA4 */ -#define PIO_PC29B_MCDA5 (1 << 29) /**< \brief Hsmci signal: MCDA5 */ -#define PIO_PC30B_MCDA6 (1 << 30) /**< \brief Hsmci signal: MCDA6 */ -#define PIO_PC31B_MCDA7 (1 << 31) /**< \brief Hsmci signal: MCDA7 */ -/* ========== Pio definition for SSC peripheral ========== */ -#define PIO_PA27A_RD (1 << 27) /**< \brief Ssc signal: RD */ -#define PIO_PA31A_RF (1 << 31) /**< \brief Ssc signal: RF */ -#define PIO_PA29A_RK (1 << 29) /**< \brief Ssc signal: RK */ -#define PIO_PA26A_TD (1 << 26) /**< \brief Ssc signal: TD */ -#define PIO_PA30A_TF (1 << 30) /**< \brief Ssc signal: TF */ -#define PIO_PA28A_TK (1 << 28) /**< \brief Ssc signal: TK */ -/* ========== Pio definition for SPI peripheral ========== */ -#define PIO_PA13A_MISO (1 << 13) /**< \brief Spi signal: MISO */ -#define PIO_PA14A_MOSI (1 << 14) /**< \brief Spi signal: MOSI */ -#define PIO_PA16A_NPCS0 (1 << 16) /**< \brief Spi signal: NPCS0 */ -#define PIO_PA0B_NPCS1 (1 << 0) /**< \brief Spi signal: NPCS1 */ -#define PIO_PC19B_NPCS1 (1 << 19) /**< \brief Spi signal: NPCS1 */ -#define PIO_PC3B_NPCS1 (1 << 3) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA1B_NPCS2 (1 << 1) /**< \brief Spi signal: NPCS2 */ -#define PIO_PC14B_NPCS2 (1 << 14) /**< \brief Spi signal: NPCS2 */ -#define PIO_PC4B_NPCS2 (1 << 4) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA19B_NPCS3 (1 << 19) /**< \brief Spi signal: NPCS3 */ -#define PIO_PC5B_NPCS3 (1 << 5) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA15A_SPCK (1 << 15) /**< \brief Spi signal: SPCK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA2A_TCLK0 (1 << 2) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PB4A_TCLK1 (1 << 4) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA26B_TCLK2 (1 << 26) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA1A_TIOA0 (1 << 1) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PB5A_TIOA1 (1 << 5) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA30B_TIOA2 (1 << 30) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA0A_TIOB0 (1 << 0) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PB6A_TIOB1 (1 << 6) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA31B_TIOB2 (1 << 31) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA10A_TWCK0 (1 << 10) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA9A_TWD0 (1 << 9) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PA25A_TWCK1 (1 << 25) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PA24A_TWD1 (1 << 24) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA11B_PWMFI0 (1 << 11) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA12B_PWMFI1 (1 << 12) /**< \brief Pwm signal: PWMFI1 */ -#define PIO_PA18B_PWMFI2 (1 << 18) /**< \brief Pwm signal: PWMFI2 */ -#define PIO_PA28B_PWMH0 (1 << 28) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA4B_PWMH0 (1 << 4) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB13B_PWMH0 (1 << 13) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC24B_PWMH0 (1 << 24) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA29B_PWMH1 (1 << 29) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA5B_PWMH1 (1 << 5) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB14B_PWMH1 (1 << 14) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC25B_PWMH1 (1 << 25) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA15B_PWMH2 (1 << 15) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA6B_PWMH2 (1 << 6) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB15B_PWMH2 (1 << 15) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB2A_PWMH2 (1 << 2) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC26B_PWMH2 (1 << 26) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA20B_PWMH3 (1 << 20) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB16B_PWMH3 (1 << 16) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB3A_PWMH3 (1 << 3) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC27B_PWMH3 (1 << 27) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA7B_PWML0 (1 << 7) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB17B_PWML0 (1 << 17) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB25B_PWML0 (1 << 25) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC29A_PWML0 (1 << 29) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC6B_PWML0 (1 << 6) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA8B_PWML1 (1 << 8) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB18B_PWML1 (1 << 18) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB26B_PWML1 (1 << 26) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC30A_PWML1 (1 << 30) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC7B_PWML1 (1 << 7) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA9B_PWML2 (1 << 9) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB19B_PWML2 (1 << 19) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB27B_PWML2 (1 << 27) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC31A_PWML2 (1 << 31) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC8B_PWML2 (1 << 8) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA10B_PWML3 (1 << 10) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB20B_PWML3 (1 << 20) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB28B_PWML3 (1 << 28) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC16B_PWML3 (1 << 16) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC9B_PWML3 (1 << 9) /**< \brief Pwm signal: PWML3 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PB8A_CTS0 (1 << 8) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PB11B_DCD0 (1 << 11) /**< \brief Usart0 signal: DCD0 */ -#define PIO_PB10B_DSR0 (1 << 10) /**< \brief Usart0 signal: DSR0 */ -#define PIO_PB9B_DTR0 (1 << 9) /**< \brief Usart0 signal: DTR0 */ -#define PIO_PB12B_RI0 (1 << 12) /**< \brief Usart0 signal: RI0 */ -#define PIO_PB7A_RTS0 (1 << 7) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PA19A_RXD0 (1 << 19) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PA17A_SCK0 (1 << 17) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PA18A_TXD0 (1 << 18) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA23B_CTS1 (1 << 23) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA22B_RTS1 (1 << 22) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA21A_RXD1 (1 << 21) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA24B_SCK1 (1 << 24) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA20A_TXD1 (1 << 20) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio definition for USART2 peripheral ========== */ -#define PIO_PB22B_CTS2 (1 << 22) /**< \brief Usart2 signal: CTS2 */ -#define PIO_PB21B_RTS2 (1 << 21) /**< \brief Usart2 signal: RTS2 */ -#define PIO_PA23A_RXD2 (1 << 23) /**< \brief Usart2 signal: RXD2 */ -#define PIO_PA25B_SCK2 (1 << 25) /**< \brief Usart2 signal: SCK2 */ -#define PIO_PA22A_TXD2 (1 << 22) /**< \brief Usart2 signal: TXD2 */ -/* ========== Pio definition for USART3 peripheral ========== */ -#define PIO_PC10B_CTS3 (1 << 10) /**< \brief Usart3 signal: CTS3 */ -#define PIO_PC11B_RTS3 (1 << 11) /**< \brief Usart3 signal: RTS3 */ -#define PIO_PC13B_RXD3 (1 << 13) /**< \brief Usart3 signal: RXD3 */ -#define PIO_PC19A_SCK3 (1 << 19) /**< \brief Usart3 signal: SCK3 */ -#define PIO_PC12B_TXD3 (1 << 12) /**< \brief Usart3 signal: TXD3 */ -/* ========== Pio definition for ADC12B peripheral ========== */ -#define PIO_PA2B_AD12BTRG (1 << 2) /**< \brief Adc12b signal: AD12BTRG */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA17B_ADTRG (1 << 17) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA21B_PCK0 (1 << 21) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA27B_PCK0 (1 << 27) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA3B_PCK1 (1 << 3) /**< \brief Pmc signal: PCK1 */ -#define PIO_PB24B_PCK1 (1 << 24) /**< \brief Pmc signal: PCK1 */ -#define PIO_PB23B_PCK2 (1 << 23) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for UART peripheral ========== */ -#define PIO_PA11A_URXD (1 << 11) /**< \brief Uart signal: URXD */ -#define PIO_PA12A_UTXD (1 << 12) /**< \brief Uart signal: UTXD */ -/*@}*/ - -/* ***************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR AT91SAM3U */ -/* ***************************************************************************** */ - -#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -#define AT91C_IFLASH (0x00080000) /**< Internal Flash base address */ -//#define AT91C_IFLASH (0x00100000) /**< Internal Flash base address */ -#define AT91C_IROM (0x00180000) /**< Internal ROM base address */ -//#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -//#define AT91C_IRAM (0x20080000) /**< Internal RAM base address */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* AT91SAM3U_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/chip.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/chip.h deleted file mode 100644 index 03133de4e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/chip.h +++ /dev/null @@ -1,77 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - - -#ifndef CHIP_H -#define CHIP_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - - -//ARM core features - -// ARM core definition. -#define cortexm3 - -// family definition. -#define at91sam3u - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ - -//IP FEATURES - -// EFC GPNVM number -#define CHIP_EFC_NUM_GPNVMS 3 - -// Indicates chip has an Enhanced EFC. -#define CHIP_FLASH_EEFC - -// DMA channels number -#define CHIP_DMA_CHANNEL_NUM 4 - -// Indicate chip has a nandflash controller. -#define CHIP_NAND_CTRL - -//------------------------------------------------------------------------------ - - -//Misc - -//------------------------------------------------------------------------------ - -#endif //#ifndef CHIP_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.icf deleted file mode 100644 index a8911758c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.icf +++ /dev/null @@ -1,47 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Vector table start*/ -define symbol __ICFEDIT_vector_start__ = 0x00080000; /*Add for CMSIS*/ -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM0_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM0_end__ = 0x20007FFF; -define symbol __ICFEDIT_region_RAM1_start__ = 0x20080000; -define symbol __ICFEDIT_region_RAM1_end__ = 0x20083FFF; -define symbol __ICFEDIT_region_ROM0_start__ = 0x00080000; -define symbol __ICFEDIT_region_ROM0_end__ = 0x0009FFFF; -define symbol __ICFEDIT_region_ROM1_start__ = 0x00100000; -define symbol __ICFEDIT_region_ROM1_end__ = 0x0011FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; -define symbol __ICFEDIT_size_heap__ = 0x200; -/*-Specials-*/ -/*define symbol __ICFEDIT_region_RAM_VECT_start__ = __ICFEDIT_region_RAM0_start__;*/ /*Referenced for CMSIS*/ -/*define symbol __ICFEDIT_size_vectors__ = 0x100;*/ /*Referenced for CMSIS*/ -/*-Exports-*/ -/*export symbol __ICFEDIT_region_RAM_VECT_start__;*/ -export symbol __ICFEDIT_vector_start__; /*Add for CMSIS*/ -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -/*define region RAM_VECT_region = mem:[from __ICFEDIT_region_RAM_VECT_start__ size __ICFEDIT_size_vectors__];*/ /*Referenced for CMSIS*/ -/*define region RAM0_region = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__];*/ /*Referenced for CMSIS*/ -define region RAM0_region = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__]; -define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__]; -/*define region RAM_region = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] | - mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/ /*Referenced for CMSIS*/ -define region ROM0_region = mem:[from __ICFEDIT_region_ROM0_start__ to __ICFEDIT_region_ROM0_end__]; -define region ROM1_region = mem:[from __ICFEDIT_region_ROM1_start__ to __ICFEDIT_region_ROM1_end__]; - -/*define block RamVect with alignment = 8, size = __ICFEDIT_size_vectors__ { };*/ -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -/*place at start of ROM0_region { readonly section .vectors };*/ /*Referenced for CMSIS*/ -place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors }; /*Add for CMSIS*/ -place in ROM0_region { readonly }; -place in RAM0_region { readwrite, block CSTACK, block HEAP }; -/*place in RAM_VECT_region { block RamVect };*/ /*Referenced for CMSIS*/ \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.lds deleted file mode 100644 index 0355f9223..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.lds +++ /dev/null @@ -1,87 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Linker script for running in internal FLASH on the AT91SAM3U4 - *----------------------------------------------------------------------------*/ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(ResetException) - -/* Vector Definition */ -/* vector is put at very begin adress of SRAM0, the preserved size is 0x100 */ -_vect_start = 0x20000000; - -/* Memory Spaces Definitions */ -MEMORY -{ - sram0 (W!RX) : ORIGIN = 0x20000100, LENGTH = 0x00007F00 /* Sram0, 32K */ - sram1 (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */ - flash0 (W!RX) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */ - flash1 (W!RX) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* Flash1, 128K */ -} - -SECTIONS -{ - .fixed : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors)) - *(.text*) - *(.rodata*) - *(.glue_7) - *(.glue_7t) - . = ALIGN(4); - _efixed = .; /* End of text section */ - } >flash0 - - .relocate : AT (_efixed) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc); - *(.data); - . = ALIGN(4); - _erelocate = .; - } >sram0 - - .bss (NOLOAD) : { - . = ALIGN(4); - _szero = .; - *(.bss) - . = ALIGN(4); - _ezero = .; - } >sram0 - - /* Stack in the end of SRAM0 */ - _estack = 0x20007FFC; -} -end = .; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.sct b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.sct deleted file mode 100644 index 3ec4fac7b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/flash.sct +++ /dev/null @@ -1,58 +0,0 @@ -; * ---------------------------------------------------------------------------- -; * ATMEL Microcontroller Software Support -; * ---------------------------------------------------------------------------- -; * Copyright (c) 2008, Atmel Corporation -; * -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without -; * modification, are permitted provided that the following conditions are met: -; * -; * - Redistributions of source code must retain the above copyright notice, -; * this list of conditions and the disclaimer below. -; * -; * Atmel's name may not be used to endorse or promote products derived from -; * this software without specific prior written permission. -; * -; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * ---------------------------------------------------------------------------- - -; *------------------------------------------------------------------------------ -; * Linker scatter for running in internal SRAM on the AT91SAM3U4 -; *----------------------------------------------------------------------------*/ - -; /* vector is put at very begin adress of SRAM0, the preserved size is 0x100 */ -Load_region 0x80000 0x20000 -{ - ; Flash 128K - Vector_region 0x80000 - { - board_cstartup_keil.o (vectors, +FIRST) - } - Fixed_region +0 - { - .ANY (+RO) - } - ; SRAM0 32K - Relocate_region 0x20000100 (0x8000-0x100) - { - .ANY (+RW +ZI) - } - ; Configure Stack and Heap - ARM_LIB_HEAP 0x20007000 EMPTY 0x400 - { - } - - ARM_LIB_STACK 0x20007FFC EMPTY -0x400 - { - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.icf deleted file mode 100644 index bdd5f4d10..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.icf +++ /dev/null @@ -1,43 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Vector table start*/ -define symbol __ICFEDIT_vector_start__ = 0x60000000; /*Add for CMSIS*/ -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM0_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM0_end__ = 0x20007FFF; -define symbol __ICFEDIT_region_RAM1_start__ = 0x20080000; -define symbol __ICFEDIT_region_RAM1_end__ = 0x20083FFF; -define symbol __ICFEDIT_region_PSRAM_start__ = 0x60000000; -define symbol __ICFEDIT_region_RSRAM_end__ = 0x600FFFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/*-Specials-*/ -/*define symbol __ICFEDIT_region_RAM_VECT_start__ = __ICFEDIT_region_RAM0_start__;*/ /*Referenced for CMSIS*/ -/*define symbol __ICFEDIT_size_vectors__ = 0x100;*/ /*Referenced for CMSIS*/ -/*-Exports-*/ -export symbol __ICFEDIT_region_RAM_VECT_start__; /*Add for CMSIS*/ -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -/*define region RAM_VECT_region = mem:[from __ICFEDIT_region_RAM_VECT_start__ size __ICFEDIT_size_vectors__];*/ -/*define region RAM0_region = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__];*/ /*Referenced for CMSIS*/ -define region RAM0_region = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__]; -define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__]; -/*define region RAM_region = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] | - mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/ /*Referenced for CMSIS*/ -define region PSRAM_region = mem:[from __ICFEDIT_region_PSRAM_start__ to __ICFEDIT_region_RSRAM_end__]; - -/*define block RamVect with alignment = 8, size = __ICFEDIT_size_vectors__ { };*/ /*Referenced for CMSIS*/ -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -/*place at start of PSRAM_region { readonly section .vectors };*/ /*Referenced for CMSIS*/ -place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors }; /*Add for CMSIS*/ -place in PSRAM_region { readonly }; -place in PSRAM_region { readwrite, block CSTACK, block HEAP }; -/*place in RAM_VECT_region { block RamVect };*/ /*Referenced for CMSIS*/ \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.lds deleted file mode 100644 index b5b8c8d57..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.lds +++ /dev/null @@ -1,86 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Linker script for running in internal PSRAM on the AT91SAM3U4 - *----------------------------------------------------------------------------*/ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(ResetException) - -/* Vector Definition */ -/* vector is put at very begin adress of SRAM0, the preserved size is 0x100 */ -_vect_start = 0x20000000; - -/* Memory Spaces Definitions */ -MEMORY -{ - sram0 (W!RX) : ORIGIN = 0x20000100, LENGTH = 0x00007F00 /* Sram0, 32K */ - sram1 (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */ - psram (W!RX) : ORIGIN = 0x60000000, LENGTH = 0x00100000 /* PSRAM, 1M */ -} - -SECTIONS -{ - .fixed : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors)) - *(.text*) - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.data) - . = ALIGN(4); - _efixed = .; /* End of text section */ - } >psram - - .relocate : AT (_efixed) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc); - . = ALIGN(4); - _erelocate = .; - } >sram0 - - .bss (NOLOAD) : { - . = ALIGN(4); - _szero = .; - *(.bss) - . = ALIGN(4); - _ezero = .; - } >psram - - /* Stack in the end of SRAM0 */ - _estack = 0x20007FFC; -} -end = .; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.sct b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.sct deleted file mode 100644 index 162f57b6b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/psram.sct +++ /dev/null @@ -1,59 +0,0 @@ -; * ---------------------------------------------------------------------------- -; * ATMEL Microcontroller Software Support -; * ---------------------------------------------------------------------------- -; * Copyright (c) 2008, Atmel Corporation -; * -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without -; * modification, are permitted provided that the following conditions are met: -; * -; * - Redistributions of source code must retain the above copyright notice, -; * this list of conditions and the disclaimer below. -; * -; * Atmel's name may not be used to endorse or promote products derived from -; * this software without specific prior written permission. -; * -; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * ---------------------------------------------------------------------------- - -; *------------------------------------------------------------------------------ -; * Linker scatter for running in internal SRAM on the AT91SAM3U4 -; *----------------------------------------------------------------------------*/ - -; /* vector is put at very begin adress of SRAM0, the preserved size is 0x100 */ -Load_region 0x60000000 0x100000 -{ - ; PSRAM 1M - Vector_region 0x60000000 - { - board_cstartup_keil.o (vectors, +FIRST) - } - - Fixed_region +0 - { - .ANY (+RO) - .ANY (+RW +ZI) - } - - ; SRAM0 32K - IVector_region 0x20000000 0x100 {} - - ; Configure Stack and Heap - ARM_LIB_HEAP 0x20007000 EMPTY 0x400 - { - } - - ARM_LIB_STACK 0x20007FFC EMPTY -0x400 - { - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.icf deleted file mode 100644 index 242942af3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.icf +++ /dev/null @@ -1,33 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Vector table start*/ -define symbol __ICFEDIT_vector_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM0_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM0_end__ = 0x20007FFF; -define symbol __ICFEDIT_region_RAM1_start__ = 0x20080000; -define symbol __ICFEDIT_region_RAM1_end__ = 0x20083FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/*-Exports-*/ -export symbol __ICFEDIT_vector_start__; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM0_region = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__]; -define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__]; -/*define region RAM_region = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] | - mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/ - -/* define block RamVect with alignment = 8, size = __ICFEDIT_size_vectors__ { }; */ -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors }; -place in RAM0_region { readonly }; -place in RAM1_region { readwrite, block CSTACK, block HEAP }; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.lds deleted file mode 100644 index 12029473e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.lds +++ /dev/null @@ -1,84 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Linker script for running in internal SRAM on the AT91SAM3U4 - *----------------------------------------------------------------------------*/ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(ResetException) - -/* Vector Definition */ -_vect_start = 0x20000000; - -/* Memory Spaces Definitions */ -MEMORY -{ - sram0 (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */ - sram1 (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */ -} - -SECTIONS -{ - .fixed : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors)) - *(.text*) - *(.ramfunc) - *(.rodata*) - *(.glue_7) - *(.glue_7t) - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > sram0 - - .relocate : AT (_efixed) - { - . = ALIGN(4); - _srelocate = .; - *(.data) - . = ALIGN(4); - _erelocate = .; - } >sram1 - - .bss (NOLOAD) : { - . = ALIGN(4); - _szero = .; - *(.bss) - . = ALIGN(4); - _ezero = .; - } >sram1 - - /* Stack in the end of SRAM1 */ - _estack = 0x20083FFC; -} -end = .; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.sct b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.sct deleted file mode 100644 index f279cf79c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram.sct +++ /dev/null @@ -1,60 +0,0 @@ -; * ---------------------------------------------------------------------------- -; * ATMEL Microcontroller Software Support -; * ---------------------------------------------------------------------------- -; * Copyright (c) 2008, Atmel Corporation -; * -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without -; * modification, are permitted provided that the following conditions are met: -; * -; * - Redistributions of source code must retain the above copyright notice, -; * this list of conditions and the disclaimer below. -; * -; * Atmel's name may not be used to endorse or promote products derived from -; * this software without specific prior written permission. -; * -; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * ---------------------------------------------------------------------------- - -; *------------------------------------------------------------------------------ -; * Linker scatter for running in internal SRAM on the AT91SAM3U4 -; *----------------------------------------------------------------------------*/ - -Load_region 0x20000000 0x8000 -{ - ; RAM0 32K - Vector_region 0x20000000 0x100 - { - board_cstartup_keil.o (vectors, +FIRST) - } - - Fixed_region +0 - { - .ANY (+RO) - } - - ; RAM1 16K - Relocate_region 0x20080000 0x4000 - { - .ANY (+RW +ZI) - } - - ; Configure Stack and Heap - ARM_LIB_HEAP 0x20083000 EMPTY 0x400 - { - } - - ARM_LIB_STACK 0x20083FFC EMPTY -0x400 - { - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram_samba.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram_samba.lds deleted file mode 100644 index 226b4595b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/at91sam3u4/sram_samba.lds +++ /dev/null @@ -1,92 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Linker script for running in internal SRAM on the AT91SAM3U4 - *----------------------------------------------------------------------------*/ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(entry) - -/* Memory Spaces Definitions */ -MEMORY -{ - romcodesram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x01000 - sram0 (W!RX) : ORIGIN = 0x20001000, LENGTH = 0x00007000 /* Sram0, 32K */ -} - -/* Entry point */ -/*ENTRY (ResetException)*/ - -SECTIONS -{ - /* startup code in the .isr_vector */ - .text : - { - . = ALIGN(4); - _stext = .; - KEEP(*(.isr_vector .isr_vector.*)) - *(.mailbox) - *(.text .text.*) - *(.rodata .rodata.*) - *(.glue_7) - *(.glue_7t) - *(.gcc_except_table) - *(.rodata .rodata*) - *(.gnu.linkonce.r.*) - . = ALIGN(4); - _etext = .; - } > sram0 - - /* data */ - .data : - { - . = ALIGN(4); - _sidata = .; - _sdata = .; - - *(.data) - *(.data.*) - . = ALIGN(4); - _edata = .; - } > sram0 - - .bss (NOLOAD) : { - _szero = .; - *(.bss) - . = ALIGN(4); - _ezero = .; - } >sram0 - - /* Stack in SRAM0 */ - _sstack = 0x20008000; -} -end = .; - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board.h deleted file mode 100644 index 766ae4746..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board.h +++ /dev/null @@ -1,665 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/** - * \page sam3s_ek_board_desc "SAM3S-EK - Board Description" - * - * \section - * A file is dedicated to descibe the AT91SAM3S-EK board. - * - * \section Contents - * - The code for booting the board is provided by board_cstartup.S and - * board_lowlevel.c. - * - For using board PIOs, board characteristics (clock, etc.) and external - * components, see board.h. - * - For manipulating memories (remapping, SDRAM, etc.), see board_memories.h. - * - * To get more software details and the full list of parameters related to the - * SAM3S-EK board configuration, please have a look at the source file: \n - * \ref board.h\n - * - * This file can be used as a template and modified to fit a custom board, with - * specific PIOs usage or memory connections. - **/ -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// \file board.h -/// -/// \par Purpose -/// -/// Definition of AT91SAM3S-EK characteristics, AT91SAM3S-dependant PIOs and -/// external components interfacing. -/// -/// \par Usage -/// -# For operating frequency information, see "SAM3S-EK - Operating frequencies". -/// -# For using portable PIO definitions, see "SAM3S-EK - PIO definitions". -/// -# Several USB definitions are included here (see "SAM3S-EK - USB device"). -//------------------------------------------------------------------------------ - -#ifndef BOARD_H -#define BOARD_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -/* These headers were introduced in C99 by working group ISO/IEC JTC1/SC22/WG14. */ -#include -#include - -#if defined(at91sam3s4) - #include "at91sam3s4/chip.h" - #include "at91sam3s4/AT91SAM3S4.h" -#else - #error Board does not support the specified chip. -#endif - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par -/// This page lists several definition related to the board description. -/// -/// Definitions -/// - BOARD_NAME - -/// Name of the board. -#define BOARD_NAME "AT91SAM3S-EK" -/// Board definition. -#define at91sam3sek -/// Family definition (already defined). -#define at91sam3s -/// Core definition -#define cortexm3 - -//#define BOARD_REV_A -#define BOARD_REV_B - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_opfreq "SAM3S-EK - Operating frequencies" -/// This page lists several definition related to the board operating frequency -/// (when using the initialization done by board_lowlevel.c). -/// -/// !Definitions -/// - BOARD_MAINOSC -/// - BOARD_MCK - -/// Frequency of the board main oscillator. -#define BOARD_MAINOSC 12000000 - -/// Master clock frequency (when using board_lowlevel.c). -//#define BOARD_MCK 48000000 -#define BOARD_MCK 64000000 - -//------------------------------------------------------------------------------ -// ADC -//------------------------------------------------------------------------------ - -/// Startup time max, return from Idle mode (in s) -#define ADC_STARTUP_TIME_MAX 15 -/// Track and hold Acquisition Time min (in ns) -#define ADC_TRACK_HOLD_TIME_MIN 1200 - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// USB attributes configuration descriptor (bus or self powered, remote wakeup) -//#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_RWAKEUP -#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_piodef "SAM3S-EK - PIO definitions" -/// This pages lists all the pio definitions contained in board.h. The constants -/// are named using the following convention: PIN_* for a constant which defines -/// a single Pin instance (but may include several PIOs sharing the same -/// controller), and PINS_* for a list of Pin instances. -/// -/// !ADC -/// - PIN_ADC0_AD0 -/// - PIN_ADC0_AD1 -/// - PIN_ADC0_AD2 -/// - PIN_ADC0_AD3 -/// - PIN_ADC0_AD4 -/// - PIN_ADC0_AD5 -/// - PIN_ADC0_AD6 -/// - PIN_ADC0_AD7 -/// - PINS_ADC0 -/// -/// !UART -/// - PINS_UART -/// -/// !EBI -/// - PIN_EBI_DATA_BUS -/// - PIN_EBI_NCS0 -/// - PIN_EBI_NRD -/// - PIN_EBI_NWE -/// - PIN_EBI_ADDR_BUS -/// - PIN_EBI_PSRAM_NBS -/// - PIN_EBI_A1 -/// - PIN_EBI_LCD_RS -/// -/// !LEDs -/// - PIN_LED_0 -/// - PIN_LED_1 -/// - PIN_LED_2 -/// - PINS_LEDS -/// -/// !MCI -/// - PINS_MCI -/// -/// !Push buttons -/// - PIN_PUSHBUTTON_1 -/// - PIN_PUSHBUTTON_2 -/// - PINS_PUSHBUTTONS -/// - PUSHBUTTON_BP1 -/// - PUSHBUTTON_BP2 -/// -/// !PWMC -/// - PIN_PWMC_PWMH0 -/// - PIN_PWMC_PWML0 -/// - PIN_PWMC_PWMH1 -/// - PIN_PWMC_PWML1 -/// - PIN_PWMC_PWMH2 -/// - PIN_PWMC_PWML2 -/// - PIN_PWMC_PWMH3 -/// - PIN_PWMC_PWML3 -/// - PIN_PWM_LED0 -/// - PIN_PWM_LED1 -/// - PIN_PWM_LED2 -/// - CHANNEL_PWM_LED0 -/// - CHANNEL_PWM_LED1 -/// - CHANNEL_PWM_LED2 -/// -/// !SPI -/// - PIN_SPI_MISO -/// - PIN_SPI_MOSI -/// - PIN_SPI_SPCK -/// - PINS_SPI -/// - PIN_SPI_NPCS0_PA11 -/// -/// ! SSC -/// - PIN_SSC_TD -/// - PIN_SSC_TK -/// - PIN_SSC_TF -/// - PINS_SSC_CODEC -/// -/// ! PCK0 -/// - PIN_PCK0 -/// -/// !TWI -/// - PIN_TWI_TWD0 -/// - PIN_TWI_TWCK0 -/// - PINS_TWI -/// -/// !USART0 -/// - PIN_USART0_RXD -/// - PIN_USART0_TXD -/// - PIN_USART0_CTS -/// - PIN_USART0_RTS -/// - PIN_USART0_SCK -/// -/// !USB -/// - PIN_USB_PULLUP -/// - -/// ADC_AD0 pin definition. -#define PIN_ADC0_AD0 {1 << 21, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD1 pin definition. -#define PIN_ADC0_AD1 {1 << 30, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD2 pin definition. -#define PIN_ADC0_AD2 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD3 pin definition. -#define PIN_ADC0_AD3 {1 << 4, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD4 pin definition. -#define PIN_ADC0_AD4 {1 << 15, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD5 pin definition. -#define PIN_ADC0_AD5 {1 << 16, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD6 pin definition. -#define PIN_ADC0_AD6 {1 << 17, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD7 pin definition. -#define PIN_ADC0_AD7 {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} - -/// Pins ADC -#define PINS_ADC PIN_ADC0_AD0, PIN_ADC0_AD1, PIN_ADC0_AD2, PIN_ADC0_AD3, PIN_ADC0_AD4, PIN_ADC0_AD5, PIN_ADC0_AD6, PIN_ADC0_AD7 - -/** UART pins (UTXD0 and URXD0) definitions, PA9,10. */ -#define PINS_UART {0x00000600, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} - -/// EBI -#define PIN_EBI_DATA_BUS {0xFF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NRD {1 << 11, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NWE {1 << 8, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} - -#define PIN_EBI_NCS0 {1 << 20, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_PSRAM_ADDR_BUS {0x3f00fff, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_PSRAM_NBS {1 << 7, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_PULLUP}, \ - {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_A1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} - -#define PIN_EBI_NCS1 {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD CS pin */ -#define PIN_EBI_LCD_RS {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD RS pin */ - -#ifdef BOARD_REV_A -/** LED #0 pin definition. */ -#define PIN_LED_0 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #1 pin definition. */ -#define PIN_LED_1 {1 << 21, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #2 pin definition. */ -#define PIN_LED_2 {1 << 22, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -#endif -#ifdef BOARD_REV_B -/** LED #0 pin definition. */ -#define PIN_LED_0 {1 << 19, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #1 pin definition. */ -#define PIN_LED_1 {1 << 20, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #2 pin definition. */ -#define PIN_LED_2 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -#endif - -/** List of all LEDs definitions. */ -#define PINS_LEDS PIN_LED_0, PIN_LED_1, PIN_LED_2 - -/// MCI pins definition. -#define PINS_MCI {0x1f8, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_PULLUP}, \ - {1 << 3, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} - -/// MCI pin Card Detect -#define PIN_MCI_CD \ - {AT91C_PIO_PA25, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} - -/** Push button #0 definition. Attributes = pull-up + debounce + interrupt on rising edge. */ -#define PIN_PUSHBUTTON_1 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE} -/** Push button #1 definition. Attributes = pull-up + debounce + interrupt on falling edge. */ -#define PIN_PUSHBUTTON_2 {1 << 12, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE} -/** List of all push button definitions. */ -#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2 - -/** Push button #1 index. */ -#define PUSHBUTTON_BP1 0 -/** Push button #2 index. */ -#define PUSHBUTTON_BP2 1 - -/// Simulated joystick LEFT index. -#define JOYSTICK_LEFT 0 -/// Simulated joystick RIGHT index. -#define JOYSTICK_RIGHT 1 - -/** PWMC PWM0 pin definition. */ -#define PIN_PWMC_PWMH0 {1 << 18, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML0 {1 << 19, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} -/** PWMC PWM1 pin definition. */ -#define PIN_PWMC_PWMH1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML1 {1 << 20, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} -/** PWMC PWM2 pin definition. */ -#define PIN_PWMC_PWMH2 {1 << 20, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML2 {1 << 16, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} -/** PWMC PWM3 pin definition. */ -#define PIN_PWMC_PWMH3 {1 << 21, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML3 {1 << 15, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} -/** PWM pin definition for LED0 */ -#define PIN_PWM_LED0 PIN_PWMC_PWMH0, PIN_PWMC_PWML0 -/** PWM pin definition for LED1 */ -#define PIN_PWM_LED1 PIN_PWMC_PWMH2, PIN_PWMC_PWML2 -/** PWM pin definition for LED2 */ -#define PIN_PWM_LED2 PIN_PWMC_PWMH3, PIN_PWMC_PWML3 -/** PWM channel for LED0 */ -#define CHANNEL_PWM_LED0 0 -/** PWM channel for LED1 */ -#define CHANNEL_PWM_LED1 2 -/** PWM channel for LED2 */ -#define CHANNEL_PWM_LED2 3 - -/** SPI MISO pin definition. */ -#define PIN_SPI_MISO {1 << 12, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** SPI MOSI pin definition. */ -#define PIN_SPI_MOSI {1 << 13, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** SPI SPCK pin definition. */ -#define PIN_SPI_SPCK {1 << 14, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** SPI chip select pin definition. */ -#define PIN_SPI_NPCS0_PA11 {1 << 11, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** List of SPI pin definitions (MISO, MOSI & SPCK). */ -#define PINS_SPI PIN_SPI_MISO, PIN_SPI_MOSI, PIN_SPI_SPCK - -/// SSC pins definition. -#define PIN_SSC_TD {0x1 << 26, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_SSC_TK {0x1 << 28, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_SSC_TF {0x1 << 30, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PINS_SSC_CODEC PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF - -/// PCK0 -#define PIN_PCK0 {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} - -/// TWI pins definition. -#define TWI_V3XX -#define PIN_TWI_TWD0 {0x1 << 9, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_TWI_TWCK0 {0x1 << 10, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PINS_TWI0 PIN_TWI_TWD0, PIN_TWI_TWCK0 -#define PIN_TWI_TWD1 {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_TWI_TWCK1 {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PINS_TWI1 PIN_TWI_TWD1, PIN_TWI_TWCK1 - -/// USART0 -#define PIN_USART0_RXD {0x1 << 19, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_TXD {0x1 << 18, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_CTS {0x1 << 8, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_RTS {0x1 << 7, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_SCK {0x1 << 17, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} - -/// USART1 -#define PIN_USART1_RXD {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_TXD {0x1 << 22, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_CTS {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_RTS {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_EN {0x1 << 23, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} - - - -/// USB VBus monitoring pin definition. -#ifdef BOARD_REV_A -#define PIN_USB_VBUS {1 << 23, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -#endif -#ifdef BOARD_REV_B -#define PIN_USB_VBUS {1 << 21, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -#endif - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_extcomp "SAM3S-EK - External components" -/// This page lists the definitions related to external on-board components -/// located in the board.h file for the AT91SAM3S-EK. -/// -/// !AT45 Dataflash Card -/// - BOARD_AT45_A_SPI_BASE -/// - BOARD_AT45_A_SPI_ID -/// - BOARD_AT45_A_SPI_PINS -/// - BOARD_AT45_A_SPI -/// - BOARD_AT45_A_NPCS -/// - BOARD_AT45_A_NPCS_PIN -/// -/// !AT45 Dataflash (serial onboard DataFlash) -/// - BOARD_AT45_B_SPI_BASE -/// - BOARD_AT45_B_SPI_ID -/// - BOARD_AT45_B_SPI_PINS -/// - BOARD_AT45_B_SPI -/// - BOARD_AT45_B_NPCS -/// - BOARD_AT45_B_NPCS_PIN -/// -/// !AT26 Serial Flash -/// - BOARD_AT26_A_SPI_BASE -/// - BOARD_AT26_A_SPI_ID -/// - BOARD_AT26_A_SPI_PINS -/// - BOARD_AT26_A_SPI -/// - BOARD_AT26_A_NPCS -/// - BOARD_AT26_A_NPCS_PIN -/// -/// !SD Card -/// - MCI2_INTERFACE -/// - BOARD_SD_MCI_BASE -/// - BOARD_SD_MCI_ID -/// - BOARD_SD_PINS -/// - BOARD_SD_SLOT -/// -/// !PSRAM -/// - BOARD_PSRAM_PINS -/// -/// !LCD -/// - BOARD_LCD_ILI9325 -/// - BOARD_LCD_PINS -/// - BOARD_BACKLIGHT_PIN -/// - BOARD_LCD_BASE -/// - BOARD_LCD_RS -/// - BOARD_LCD_WIDTH -/// - BOARD_LCD_HEIGHT -/// -/// !TouchScreen -/// - BOARD_TSC_ADS7843 -/// - PIN_TCS_IRQ -/// - PIN_TCS_BUSY -/// - BOARD_TSC_SPI_BASE -/// - BOARD_TSC_SPI_ID -/// - BOARD_TSC_SPI_PINS -/// - BOARD_TSC_NPCS -/// - BOARD_TSC_NPCS_PIN -/// -/// Base address of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_A_SPI_BASE SPI0 -///// Identifier of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_A_SPI_ID ID_SPI0 -///// Pins of the SPI peripheral connected to the dataflash. -//#define BOARD_AT45_A_SPI_PINS PINS_SPI0 -///// Dataflahs SPI number. -//#define BOARD_AT45_A_SPI 0 -///// Chip select connected to the dataflash. -//#define BOARD_AT45_A_NPCS 3 -///// Chip select pin connected to the dataflash. -//#define BOARD_AT45_A_NPCS_PIN PIN_SPI0_NPCS3 - -/// Base address of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_B_SPI_BASE SPI1 -///// Identifier of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_B_SPI_ID ID_SPI1 -///// Pins of the SPI peripheral connected to the dataflash. -//#define BOARD_AT45_B_SPI_PINS PINS_SPI1 -///// Dataflahs SPI number. -//#define BOARD_AT45_B_SPI 1 -///// Chip select connected to the dataflash. -//#define BOARD_AT45_B_NPCS 3 -///// Chip select pin connected to the dataflash. -//#define BOARD_AT45_B_NPCS_PIN PIN_SPI1_NPCS3 - -/// Base address of SPI peripheral connected to the serialflash. -//#define BOARD_AT26_A_SPI_BASE SPI0 -///// Identifier of SPI peripheral connected to the serialflash. -//#define BOARD_AT26_A_SPI_ID ID_SPI0 -///// Pins of the SPI peripheral connected to the serialflash. -//#define BOARD_AT26_A_SPI_PINS PINS_SPI0 -///// Serialflash SPI number. -//#define BOARD_AT26_A_SPI 0 -///// Chip select connected to the serialflash. -//#define BOARD_AT26_A_NPCS 3 -///// Chip select pin connected to the serialflash. -//#define BOARD_AT26_A_NPCS_PIN PIN_SPI0_NPCS3 - -/// ISO7816 -/// - PIN_SMARTCARD_CONNECT -/// - PIN_ISO7816_RSTMC -/// - PINS_ISO7816 - -/// Smartcard detection pin -//#define PIN_SMARTCARD_CONNECT {1 << 5, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} -/// PIN used for reset the smartcard -//#define PIN_ISO7816_RSTMC {1 << 7, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} -/// Pins used for connect the smartcard -//#define PINS_ISO7816 PIN_USART0_TXD, PIN_USART0_SCK, PIN_ISO7816_RSTMC - -/// Dma channel number -#define BOARD_MCI_DMA_CHANNEL 0 -/// MCI0 DMA hardware handshaking ID -#define DMA_HW_SRC_REQ_ID_MCI0 AT91C_HDMA_SRC_PER_0 -#define DMA_HW_DEST_REQ_ID_MCI0 AT91C_HDMA_DST_PER_0 -/// MCI1 DMA hardware handshaking ID -#define DMA_HW_SRC_REQ_ID_MCI1 AT91C_HDMA_SRC_PER_13 -#define DMA_HW_DEST_REQ_ID_MCI1 AT91C_HDMA_DST_PER_13 -/// SD DMA hardware handshaking ID -#define BOARD_SD_DMA_HW_SRC_REQ_ID DMA_HW_SRC_REQ_ID_MCI0 -#define BOARD_SD_DMA_HW_DEST_REQ_ID DMA_HW_DEST_REQ_ID_MCI0 - - -/// HS MCI interface -#define MCI2_INTERFACE -/// Base address of the MCI peripheral connected to the SD card. -#define BOARD_SD_MCI_BASE MCI0//MCI -///// Peripheral identifier of the MCI connected to the SD card. -#define BOARD_SD_MCI_ID ID_MCI0 //ID_MCI -///// MCI pins that shall be configured to access the SD card. -#define BOARD_SD_PINS PINS_MCI -///// MCI slot to which the SD card is connected to. -#define BOARD_SD_SLOT MCI_SD_SLOTA -///// MCI Card Detect pin. -#define BOARD_SD_PIN_CD PIN_MCI_CD - -//#define BOARD_PSRAM_PINS PIN_EBI_DATA_BUS, PIN_EBI_NCS0, PIN_EBI_NRD, PIN_EBI_NWE, \ - PIN_EBI_PSRAM_ADDR_BUS, PIN_EBI_PSRAM_NBS, PIN_EBI_A1 - -/** Indicates board has an ILI9325 external component to manage LCD. */ -#define BOARD_LCD_ILI9325 - -/** LCD pins definition. */ -#define BOARD_LCD_PINS PIN_EBI_DATA_BUS, PIN_EBI_NRD, PIN_EBI_NWE, \ - PIN_EBI_NCS1, PIN_EBI_LCD_RS -/** Backlight pin definition. */ -#define BOARD_BACKLIGHT_PIN {1 << 13, PIOC, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT} -/** Define ILI9325 base address. */ -#define BOARD_LCD_BASE 0x61000000 -/** Define ILI9325 register select signal. */ -#define BOARD_LCD_RS (1 << 1) -/** Display width in pixels. */ -#define BOARD_LCD_WIDTH 240 -/** Display height in pixels. */ -#define BOARD_LCD_HEIGHT 320 - -/** Indicates board has an ADS7843 external component to manage Touch Screen */ -#define BOARD_TSC_ADS7843 - -#ifdef BOARD_REV_A -/** Touchscreen controller IRQ pin definition. */ -#define PIN_TCS_IRQ {PIO_PA4, PIOA, ID_PIOA, PIO_INPUT, PIO_DEBOUNCE | PIO_IT_AIME | PIO_IT_EDGE} -#define PIN_TCS_IRQ_WUP_ID (1 << 3) -/** Touchscreen controller Busy pin definition. */ -#define PIN_TCS_BUSY {PIO_PA5, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} -#endif -#ifdef BOARD_REV_B -/** Touchscreen controller IRQ pin definition. */ -#define PIN_TCS_IRQ {PIO_PA16, PIOA, ID_PIOA, PIO_INPUT, PIO_DEBOUNCE | PIO_IT_AIME | PIO_IT_EDGE} -#define PIN_TCS_IRQ_WUP_ID (1 << 15) -/** Touchscreen controller Busy pin definition. */ -#define PIN_TCS_BUSY {PIO_PA17, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} -#endif - -/** Base address of SPI peripheral connected to the touchscreen controller. */ -#define BOARD_TSC_SPI_BASE SPI -/** Identifier of SPI peripheral connected to the touchscreen controller. */ -#define BOARD_TSC_SPI_ID ID_SPI -/** Pins of the SPI peripheral connected to the touchscreen controller. */ -#define BOARD_TSC_SPI_PINS PINS_SPI -/** Chip select connected to the touchscreen controller. */ -#define BOARD_TSC_NPCS 0 -/** Chip select pin connected to the touchscreen controller. */ -#define BOARD_TSC_NPCS_PIN PIN_SPI_NPCS0_PA11 - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_mem "SAM3S-EK - Memories" -/// This page lists definitions related to internal & external on-board memories. -/// -/// !Embedded Flash -/// - BOARD_FLASH_EFC - -/// Internal SRAM address -#define AT91C_ISRAM AT91C_IRAM -#define AT91C_ISRAM_SIZE 0x00008000 - -#define AT91C_IFLASH_SIZE (0x40000) -#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH 0 Page Size: 256 bytes -#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH 0 Number of Pages: 512 -#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH 0 Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH 0 Number of Lock Bits: 16 - -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// \section sam3s_ek_extcomp "SAM3S-EK - External components" -/// This page lists the definitions related to external on-board components -/// located in the board.h file for the SAM3S-EK. -/// -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_chipdef "SAM3S-EK - Individual chip definition" -/// This page lists the definitions related to different chip's definition -/// located in the board.h file for the SAM3S-EK. - -/// DBGU -#define BOARD_DBGU_ID ID_DBGU - -/// Rtc -#define BOARD_RTC_ID ID_RTC - -/// Twi eeprom -#define BOARD_ID_TWI_EEPROM ID_TWI1 -#define BOARD_BASE_TWI_EEPROM TWI1 -#define BOARD_PINS_TWI_EEPROM PINS_TWI1 - -/// USART -#define BOARD_PIN_USART_RXD PIN_USART1_RXD -#define BOARD_PIN_USART_TXD PIN_USART1_TXD -#define BOARD_PIN_USART_CTS PIN_USART1_CTS -#define BOARD_PIN_USART_RTS PIN_USART1_RTS -#define BOARD_PIN_USART_EN PIN_USART1_EN -#define BOARD_USART_BASE USART1 -#define BOARD_ID_USART ID_USART1 - -//------------------------------------------------------------------------------ - - -#define PIN_EBI_NANDOE {1 << 9, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDWE {1 << 10, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDCLE {1 << 17, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDALE {1 << 16, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDIO {0x000000FF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} - -/// Nandflash chip enable pin definition. -#define BOARD_NF_CE_PIN {1 << 14, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -/// Nandflash ready/busy pin definition. -#define BOARD_NF_RB_PIN {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP} - -/// Nandflash controller peripheral pins definition. -#define PINS_NANDFLASH PIN_EBI_NANDIO, BOARD_NF_CE_PIN, BOARD_NF_RB_PIN, PIN_EBI_NANDOE, \ - PIN_EBI_NANDWE, PIN_EBI_NANDCLE, PIN_EBI_NANDALE - -/// Address for transferring command bytes to the nandflash. -#define BOARD_NF_COMMAND_ADDR 0x60400000 -/// Address for transferring address bytes to the nandflash. -#define BOARD_NF_ADDRESS_ADDR 0x60200000 -/// Address for transferring data bytes to the nandflash. -#define BOARD_NF_DATA_ADDR 0x60000000 - -#endif //#ifndef BOARD_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_gnu.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_gnu.c deleted file mode 100644 index 632cdaca3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_gnu.c +++ /dev/null @@ -1,172 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "board.h" -#include "exceptions.h" -#include "board_lowlevel.h" - -#include - -/*---------------------------------------------------------------------------- - * Exported variables - *----------------------------------------------------------------------------*/ - -/* Stack top */ -extern uint32_t _estack; - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -/* The mask of VTOR register */ -#define SCB_VTOR_MASK 0x3FFFFFF8 - -/*---------------------------------------------------------------------------- - * ProtoTypes - *----------------------------------------------------------------------------*/ - -extern int main(void); -void ResetException(void); - -/*---------------------------------------------------------------------------- - * Local variables - *----------------------------------------------------------------------------*/ - -/* Exception Table */ -__attribute__((section(".vectors"))) -IntFunc exception_table[] = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - (IntFunc)&_estack, - ResetException, - - NMI_Handler, - HardFault_Handler, - MemManage_Handler, - BusFault_Handler, - UsageFault_Handler, - 0, 0, 0, 0, /* Reserved */ - SVC_Handler, - DebugMon_Handler, - 0, /* Reserved */ - PendSV_Handler, - SysTick_Handler, - - /* Configurable interrupts */ - SUPC_IrqHandler, /* 0 Supply Controller */ - RSTC_IrqHandler, /* 1 Reset Controller */ - RTC_IrqHandler, /* 2 Real Time Clock */ - RTT_IrqHandler, /* 3 Real Time Timer */ - WDT_IrqHandler, /* 4 Watchdog Timer */ - PMC_IrqHandler, /* 5 PMC */ - EEFC_IrqHandler, /* 6 EEFC */ - IrqHandlerNotUsed, /* 7 Reserved */ - UART0_IrqHandler, /* 8 UART0 */ - UART1_IrqHandler, /* 9 UART1 */ - SMC_IrqHandler, /* 10 SMC */ - PIOA_IrqHandler, /* 11 Parallel IO Controller A */ - PIOB_IrqHandler, /* 12 Parallel IO Controller B */ - PIOC_IrqHandler, /* 13 Parallel IO Controller C */ - USART0_IrqHandler, /* 14 USART 0 */ - USART1_IrqHandler, /* 15 USART 1 */ - IrqHandlerNotUsed, /* 16 Reserved */ - IrqHandlerNotUsed, /* 17 Reserved */ - MCI_IrqHandler, /* 18 MCI */ - TWI0_IrqHandler, /* 19 TWI 0 */ - TWI1_IrqHandler, /* 20 TWI 1 */ - SPI_IrqHandler, /* 21 SPI */ - SSC_IrqHandler, /* 22 SSC */ - TC0_IrqHandler, /* 23 Timer Counter 0 */ - TC1_IrqHandler, /* 24 Timer Counter 1 */ - TC2_IrqHandler, /* 25 Timer Counter 2 */ - TC3_IrqHandler, /* 26 Timer Counter 3 */ - TC4_IrqHandler, /* 27 Timer Counter 4 */ - TC5_IrqHandler, /* 28 Timer Counter 5 */ - ADC_IrqHandler, /* 29 ADC controller */ - DAC_IrqHandler, /* 30 DAC controller */ - PWM_IrqHandler, /* 31 PWM */ - CRCCU_IrqHandler, /* 32 CRC Calculation Unit */ - ACC_IrqHandler, /* 33 Analog Comparator */ - USBD_IrqHandler, /* 34 USB Device Port */ - IrqHandlerNotUsed /* 35 not used */ -}; - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void ResetException(void) -{ - uint32_t *pSrc, *pDest; - - LowLevelInit(); - - /* Initialize the relocate segment */ - pSrc = &_efixed; - pDest = &_srelocate; - if (pSrc != pDest) { - for(; pDest < &_erelocate;) { - - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for(pDest = &_szero; pDest < &_ezero;) { - - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *)&_sfixed; - SCB->VTOR = ((uint32_t)(pSrc)) & 0x2FFFFFF8; - - /* Branch to main function */ - main(); - - /* Infinite loop */ - while(1); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_iar.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_iar.c deleted file mode 100644 index fbfcca218..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_iar.c +++ /dev/null @@ -1,143 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Headers - *------------------------------------------------------------------------------*/ - -#include "board.h" -#include - -#include "exceptions.h" -#include "board_lowlevel.h" - -/*------------------------------------------------------------------------------ - * Types - *------------------------------------------------------------------------------*/ -typedef union { IntFunc __fun; void * __ptr; } IntVector; - -/*------------------------------------------------------------------------------ - * ProtoTypes - *------------------------------------------------------------------------------*/ -extern void __iar_program_start( void ); - -int __low_level_init( void ); - -/*------------------------------------------------------------------------------ - * Variables - *------------------------------------------------------------------------------*/ -extern unsigned int __ICFEDIT_vector_start__; - - -/*------------------------------------------------------------------------------ - * Exception Table - *------------------------------------------------------------------------------*/ -#pragma language=extended -#pragma segment="CSTACK" - -/* The name "__vector_table" has special meaning for C-SPY: */ -/* it is where the SP start value is found, and the NVIC vector */ -/* table register (VTOR) is initialized to this address if != 0. */ - -#pragma section = ".vectors" -#pragma location = ".vectors" -const IntVector __vector_table[] = -{ - { .__ptr = __sfe( "CSTACK" ) }, - __iar_program_start, - - NMI_Handler, - HardFault_Handler, - MemManage_Handler, - BusFault_Handler, - UsageFault_Handler, - 0, 0, 0, 0, /* Reserved */ - SVC_Handler, - DebugMon_Handler, - 0, /* Reserved */ - PendSV_Handler, - SysTick_Handler, - - /* Configurable interrupts */ - SUPC_IrqHandler, /* 0 SUPPLY CONTROLLER */ - RSTC_IrqHandler, /* 1 RESET CONTROLLER */ - RTC_IrqHandler, /* 2 REAL TIME CLOCK */ - RTT_IrqHandler, /* 3 REAL TIME TIMER */ - WDT_IrqHandler, /* 4 WATCHDOG TIMER */ - PMC_IrqHandler, /* 5 PMC */ - EEFC_IrqHandler, /* 6 EEFC */ - IrqHandlerNotUsed, /* 7 Reserved */ - UART0_IrqHandler, /* 8 UART0 */ - UART1_IrqHandler, /* 9 UART1 */ - SMC_IrqHandler, /* 10 SMC */ - PIOA_IrqHandler, /* 11 Parallel IO Controller A */ - PIOB_IrqHandler, /* 12 Parallel IO Controller B */ - PIOC_IrqHandler, /* 13 Parallel IO Controller C */ - USART0_IrqHandler, /* 14 USART 0 */ - USART1_IrqHandler, /* 15 USART 1 */ - IrqHandlerNotUsed, /* 16 Reserved */ - IrqHandlerNotUsed, /* 17 Reserved */ - MCI_IrqHandler, /* 18 MCI */ - TWI0_IrqHandler, /* 19 TWI 0 */ - TWI1_IrqHandler, /* 20 TWI 1 */ - SPI_IrqHandler, /* 21 SPI */ - SSC_IrqHandler, /* 22 SSC */ - TC0_IrqHandler, /* 23 Timer Counter 0 */ - TC1_IrqHandler, /* 24 Timer Counter 1 */ - TC2_IrqHandler, /* 25 Timer Counter 2 */ - TC3_IrqHandler, /* 26 Timer Counter 3 */ - TC4_IrqHandler, /* 27 Timer Counter 4 */ - TC5_IrqHandler, /* 28 Timer Counter 5 */ - ADC_IrqHandler, /* 29 ADC controller */ - DAC_IrqHandler, /* 30 DAC controller */ - PWM_IrqHandler, /* 31 PWM */ - CRCCU_IrqHandler, /* 32 CRC Calculation Unit */ - ACC_IrqHandler, /* 33 Analog Comparator */ - USBD_IrqHandler, /* 34 USB Device Port */ - IrqHandlerNotUsed /* 35 not used */ -}; - -/*------------------------------------------------------------------------------ - * Exception Table - *------------------------------------------------------------------------------*/ - -/**------------------------------------------------------------------------------ - * This is the code that gets called on processor reset. To initialize the - * device. - *------------------------------------------------------------------------------*/ -int __low_level_init( void ) -{ - unsigned int * src = __section_begin(".vectors"); - - LowLevelInit(); - - SCB->VTOR = ((unsigned int)(src)) | (0x0 << 7); - - return 1; /* if return 0, the data sections will not be initialized. */ -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_keil.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_keil.c deleted file mode 100644 index aeb935866..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_cstartup_keil.c +++ /dev/null @@ -1,131 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ -#include "board.h" -#include "exceptions.h" -#include "board_lowlevel.h" - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ -typedef union { IntFunc __fun; void * __ptr; } IrqVector; - -//------------------------------------------------------------------------------ -// ProtoTypes -//------------------------------------------------------------------------------ -extern int Image$$ARM_LIB_STACK$$ZI$$Limit; -extern int Image$$Vector_region$$Base; -extern int Image$$Vector_region$$Limit; - -extern void __main(void); -void resetHandler( void ); - -//------------------------------------------------------------------------------ -// Variables -//------------------------------------------------------------------------------ - -#pragma arm section rodata="vectors" -const IrqVector __vector_table[] = -{ - (IntFunc)&Image$$ARM_LIB_STACK$$ZI$$Limit, - resetHandler, - - NMI_Handler, - HardFault_Handler, - MemManage_Handler, - BusFault_Handler, - UsageFault_Handler, - 0, 0, 0, 0, // Reserved - SVC_Handler, - DebugMon_Handler, - 0, // Reserved - PendSV_Handler, - SysTick_Handler, - - // Configurable interrupts - SUPC_IrqHandler, // 0 SUPPLY CONTROLLER - RSTC_IrqHandler, // 1 RESET CONTROLLER - RTC_IrqHandler, // 2 REAL TIME CLOCK - RTT_IrqHandler, // 3 REAL TIME TIMER - WDT_IrqHandler, // 4 WATCHDOG TIMER - PMC_IrqHandler, // 5 PMC - EFC0_IrqHandler, // 6 EFC0 - EFC1_IrqHandler, // 7 EFC1 - DBGU_IrqHandler, // 8 DBGU - HSMC4_IrqHandler, // 9 HSMC4 - PIOA_IrqHandler, // 10 Parallel IO Controller A - PIOB_IrqHandler, // 11 Parallel IO Controller B - PIOC_IrqHandler, // 12 Parallel IO Controller C - USART0_IrqHandler, // 13 USART 0 - USART1_IrqHandler, // 14 USART 1 - USART2_IrqHandler, // 15 USART 2 - USART3_IrqHandler, // 16 USART 3 - MCI0_IrqHandler, // 17 Multimedia Card Interface - TWI0_IrqHandler, // 18 TWI 0 - TWI1_IrqHandler, // 19 TWI 1 - SPI0_IrqHandler, // 20 Serial Peripheral Interface - SSC0_IrqHandler, // 21 Serial Synchronous Controller 0 - TC0_IrqHandler, // 22 Timer Counter 0 - TC1_IrqHandler, // 23 Timer Counter 1 - TC2_IrqHandler, // 24 Timer Counter 2 - PWM_IrqHandler, // 25 Pulse Width Modulation Controller - ADCC0_IrqHandler, // 26 ADC controller0 - ADCC1_IrqHandler, // 27 ADC controller1 - HDMA_IrqHandler, // 28 HDMA - UDPD_IrqHandler, // 29 USB Device High Speed UDP_HS - IrqHandlerNotUsed // 30 not used -}; -#pragma arm section - -//------------------------------------------------------------------------------ -/// This is the code that gets called on processor reset. To initialize the -/// device. -//------------------------------------------------------------------------------ -void resetHandler( void ) -{ - unsigned int *pSrc = (unsigned int *)&Image$$Vector_region$$Base; - - // Low level Initialize - LowLevelInit(); - - AT91C_BASE_NVIC->NVIC_VTOFFR = ((unsigned int)(pSrc)) | (0x0 << 7); - - // Enter C library entry point - __main(); - - /* Infinite loop */ - while(1); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_lowlevel.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_lowlevel.c deleted file mode 100644 index 63ce7117d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_lowlevel.c +++ /dev/null @@ -1,141 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "board.h" -#include "board_memories.h" -#include "board_lowlevel.h" -#include - -/*---------------------------------------------------------------------------- - * Local definitions - *----------------------------------------------------------------------------*/ -/** Define clock timeout */ -#define CLOCK_TIMEOUT 5000 - -/*---------------------------------------------------------------------------- - * Local functions - *----------------------------------------------------------------------------*/ -static void BOARD_ConfigurePmc(void) -{ - -#define AT91C_CKGR_MUL_SHIFT 16 -#define AT91C_CKGR_PLLCOUNT_SHIFT 8 -#define AT91C_CKGR_DIV_SHIFT 0 - -// Settings at 64 MHz for MCK - -#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST & (0x8 << 8)) - -// PLLA Settings 64 MHz : 12 / 3 * 32 -#define BOARD_PLLAR ((1 << 29) | (0x1F << AT91C_CKGR_MUL_SHIFT) \ - | (0x1 << AT91C_CKGR_PLLCOUNT_SHIFT) | (0x3 << AT91C_CKGR_DIV_SHIFT)) - -// PLLB Settings 96 MHz -#define BOARD_PLLBR ((1 << 29) | (0x7 << AT91C_CKGR_MUL_SHIFT) \ - | (0x1 << AT91C_CKGR_PLLCOUNT_SHIFT) | (0x1 << AT91C_CKGR_DIV_SHIFT)) - -// USB on PLLB, MCK/PCK on PLLA -#define BOARD_MCKR ( PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK) - -// Define clock timeout -#undef CLOCK_TIMEOUT -#define CLOCK_TIMEOUT 0xFFFFFFFF - - uint32_t timeout = 0; - - /* Enable NRST reset - ************************************/ - //AT91C_BASE_RSTC->RSTC_RMR |= AT91C_RSTC_URSTEN; - - /* Initialize main oscillator - ****************************/ - if(!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) - { - - PMC->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; - timeout = 0; - while (!(PMC->PMC_SR & PMC_SR_MOSCXTS) && (timeout++ < CLOCK_TIMEOUT)); - - } - - /* Switch to 3-20MHz Xtal oscillator */ - PMC->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; - timeout = 0; - while (!(PMC->PMC_SR & PMC_SR_MOSCSELS) && (timeout++ < CLOCK_TIMEOUT)); - PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; - timeout = 0; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - - /** Set 3 WS for Embedded Flash Access */ - EFC->EEFC_FMR = (3 << 8); - - /* Initialize PLLA */ - PMC->CKGR_PLLAR = BOARD_PLLAR; - timeout = 0; - while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (timeout++ < CLOCK_TIMEOUT)); - - /* Initialize PLLB */ - PMC->CKGR_PLLBR = BOARD_PLLBR; - timeout = 0; - while (!(PMC->PMC_SR & PMC_SR_LOCKB) && (timeout++ < CLOCK_TIMEOUT)); - - // Set USB clock on PLLB - REG_PMC_USB = PMC_USB_USBS | (PMC_USB_USBDIV & (1 << 8)); - - /* Switch to fast clock - **********************/ - PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; - timeout = 0; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - - PMC->PMC_MCKR = BOARD_MCKR; - timeout = 0; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - -} - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------*/ -/** - * \brief Performs the low-level initialization of the chip. This includes EFC, - * master clock and watchdog configuration. - */ -/*----------------------------------------------------------------------------*/ -void LowLevelInit (void) -{ - /** Configure PMC */ - BOARD_ConfigurePmc(); -} \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_lowlevel.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_lowlevel.h deleted file mode 100644 index c7effdf1f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_lowlevel.h +++ /dev/null @@ -1,49 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Collection of methods for lowlevel. -/// -//------------------------------------------------------------------------------ - -#ifndef BOARD_LOWLEVEL_H -#define BOARD_LOWLEVEL_H - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -extern void LowLevelInit(void); -extern void OptimizeCpuSpeed(void); - -#endif // BOARD_LOWLEVEL_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_memories.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_memories.c deleted file mode 100644 index 6c2242635..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_memories.c +++ /dev/null @@ -1,96 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: Memories implementation -*/ -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include -#include "board_memories.h" - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - - -/** - * \brief Configures the EBI for NandFlash access. - * - */ -extern void BOARD_ConfigureNandFlash( void ) -{ - // Open EBI clock - PMC->PMC_PCER0 = (1<< ID_SMC); - // NCS0 is assigned to a NAND Flash (NANDOE and NANWE used for NCS0) - MATRIX->CCFG_SMCNFCS = CCFG_SMCNFCS_SMC_NFCS0; - -#if 0 - SMC->SMC_CS_NUMBER[0].SMC_SETUP = 0 - | ((0 << 0) & SMC_SETUP0_NWE_SETUP) - | ((1 << 8) & SMC_SETUP0_NCS_WR_SETUP) - | ((0 << 16) & SMC_SETUP0_NRD_SETUP) - | ((1 << 24) & SMC_SETUP0_NCS_RD_SETUP); - - SMC->SMC_CS_NUMBER[0].SMC_PULSE = 0 - | ((2 << 0) & SMC_PULSE0_NWE_PULSE) - | ((3 << 8) & SMC_PULSE0_NCS_WR_PULSE) - | ((4 << 16) & SMC_PULSE0_NRD_PULSE) - | ((4 << 24) & SMC_PULSE0_NCS_RD_PULSE); - - SMC->SMC_CS_NUMBER[0].SMC_CYCLE = 0 - | ((4 << 0) & SMC_CYCLE0_NWE_CYCLE) - | ((7 << 16) & SMC_CYCLE0_NRD_CYCLE); - - SMC->SMC_CS_NUMBER[0].SMC_MODE = SMC_MODE0_READ_MODE | SMC_MODE0_WRITE_MODE; -#else - SMC->SMC_CS_NUMBER[0].SMC_SETUP = 0 - | ((0 << 0) & SMC_SETUP0_NWE_SETUP) - | ((0 << 8) & SMC_SETUP0_NCS_WR_SETUP) - | ((0 << 16) & SMC_SETUP0_NRD_SETUP) - | ((0 << 24) & SMC_SETUP0_NCS_RD_SETUP); - - SMC->SMC_CS_NUMBER[0].SMC_PULSE = 0 - | ((2 << 0) & SMC_PULSE0_NWE_PULSE) - | ((2 << 8) & SMC_PULSE0_NCS_WR_PULSE) - | ((2 << 16) & SMC_PULSE0_NRD_PULSE) - | ((2 << 24) & SMC_PULSE0_NCS_RD_PULSE); - - SMC->SMC_CS_NUMBER[0].SMC_CYCLE = 0 - | ((3 << 0) & SMC_CYCLE0_NWE_CYCLE) - | ((3 << 16) & SMC_CYCLE0_NRD_CYCLE); - - SMC->SMC_CS_NUMBER[0].SMC_MODE = SMC_MODE1_READ_MODE | SMC_MODE1_WRITE_MODE; -#endif - - - -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_memories.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_memories.h deleted file mode 100644 index b9f472ff8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/board_memories.h +++ /dev/null @@ -1,49 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// -/// !Usage -/// -//------------------------------------------------------------------------------ - -#ifndef BOARD_MEMORIES_H -#define BOARD_MEMORIES_H - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void BOARD_ConfigureNandFlash( void ) ; - -#endif //#ifndef BOARD_MEMORIES_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/exceptions.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/exceptions.c deleted file mode 100644 index b9b329bf5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/exceptions.c +++ /dev/null @@ -1,385 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * This file contains the default exception handlers. - * - * \note - * The exception handler has weak aliases. - * As they are weak aliases, any function with the same name will override - * this definition. - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "exceptions.h" -#include - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Default interrupt handler for not used irq. - */ -void IrqHandlerNotUsed(void) -{ - while(1); -} - -/** - * \brief Default NMI interrupt handler. - */ -WEAK void NMI_Handler(void) -{ - while(1); -} - -/** - * \brief Default HardFault interrupt handler. - */ -WEAK void HardFault_Handler(void) -{ - while(1); -} - -/** - * \brief Default MemManage interrupt handler. - */ -WEAK void MemManage_Handler(void) -{ - while(1); -} - -/** - * \brief Default BusFault interrupt handler. - */ -WEAK void BusFault_Handler(void) -{ - while(1); -} - -/** - * \brief Default UsageFault interrupt handler. - */ -WEAK void UsageFault_Handler(void) -{ - while(1); -} - -/** - * \brief Default SVC interrupt handler. - */ -WEAK void SVC_Handler(void) -{ - while(1); -} - -/** - * \brief Default DebugMon interrupt handler. - */ -WEAK void DebugMon_Handler(void) -{ - while(1); -} - -/** - * \brief Default PendSV interrupt handler. - */ -WEAK void PendSV_Handler(void) -{ - while(1); -} - -/** - * \brief Default SysTick interrupt handler. - */ -WEAK void SysTick_Handler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for Supply Controller. - */ -WEAK void SUPC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for Reset Controller. - */ -WEAK void RSTC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for Real Time Clock. - */ -WEAK void RTC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for Real Time Timer. - */ -WEAK void RTT_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for Watchdog Timer. - */ -WEAK void WDT_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for PMC. - */ -WEAK void PMC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for EEFC. - */ -WEAK void EEFC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for UART0. - */ -WEAK void UART0_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for UART1. - */ -WEAK void UART1_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for SMC. - */ -WEAK void SMC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for PIOA Controller. - */ -WEAK void PIOA_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for PIOB Controller. - */ -WEAK void PIOB_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for PIOC Controller. - */ -WEAK void PIOC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for USART0. - */ -WEAK void USART0_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for USART1. - */ -WEAK void USART1_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for MCI. - */ -WEAK void MCI_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for TWI0. - */ -WEAK void TWI0_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for TWI1. - */ -WEAK void TWI1_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for SPI. - */ -WEAK void SPI_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for SSC. - */ -WEAK void SSC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for TC0. - */ -WEAK void TC0_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for TC1. - */ -WEAK void TC1_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for TC2. - */ -WEAK void TC2_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for TC3. - */ -WEAK void TC3_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for TC4. - */ -WEAK void TC4_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for TC5. - */ -WEAK void TC5_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for ADC. - */ -WEAK void ADC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for DAC. - */ -WEAK void DAC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for PWM. - */ -WEAK void PWM_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for CRCCU. - */ -WEAK void CRCCU_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for ACC. - */ -WEAK void ACC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for USBD. - */ -WEAK void USBD_IrqHandler(void) -{ - while(1); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/exceptions.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/exceptions.h deleted file mode 100644 index b6b366c65..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/board/exceptions.h +++ /dev/null @@ -1,103 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * Interface for default exception handlers. - */ - -#ifndef EXCEPTIONS_H -#define EXCEPTIONS_H - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - -/* Function prototype for exception table items (interrupt handler). */ -typedef void( *IntFunc )( void ); - -/* Define WEAK attribute */ -#if defined ( __CC_ARM ) - #define WEAK __attribute__ ((weak)) -#elif defined ( __ICCARM__ ) - #define WEAK __weak -#elif defined ( __GNUC__ ) - #define WEAK __attribute__ ((weak)) -#endif - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void IrqHandlerNotUsed(void); - -extern WEAK void NMI_Handler( void ); -extern WEAK void HardFault_Handler( void ); -extern WEAK void MemManage_Handler( void ); -extern WEAK void BusFault_Handler( void ); -extern WEAK void UsageFault_Handler( void ); -extern WEAK void SVC_Handler( void ); -extern WEAK void DebugMon_Handler( void ); -extern WEAK void PendSV_Handler( void ); -extern WEAK void SysTick_Handler( void ); - -extern WEAK void SUPC_IrqHandler(void); -extern WEAK void RSTC_IrqHandler(void); -extern WEAK void RTC_IrqHandler(void); -extern WEAK void RTT_IrqHandler(void); -extern WEAK void WDT_IrqHandler(void); -extern WEAK void PMC_IrqHandler(void); -extern WEAK void EEFC_IrqHandler(void); -extern WEAK void UART0_IrqHandler(void); -extern WEAK void UART1_IrqHandler(void); -extern WEAK void SMC_IrqHandler(void); -extern WEAK void PIOA_IrqHandler(void); -extern WEAK void PIOB_IrqHandler(void); -extern WEAK void PIOC_IrqHandler(void); -extern WEAK void USART0_IrqHandler(void); -extern WEAK void USART1_IrqHandler(void); -extern WEAK void MCI_IrqHandler(void); -extern WEAK void TWI0_IrqHandler(void); -extern WEAK void TWI1_IrqHandler(void); -extern WEAK void SPI_IrqHandler(void); -extern WEAK void SSC_IrqHandler(void); -extern WEAK void TC0_IrqHandler(void); -extern WEAK void TC1_IrqHandler(void); -extern WEAK void TC2_IrqHandler(void); -extern WEAK void TC3_IrqHandler(void); -extern WEAK void TC4_IrqHandler(void); -extern WEAK void TC5_IrqHandler(void); -extern WEAK void ADC_IrqHandler(void); -extern WEAK void DAC_IrqHandler(void); -extern WEAK void PWM_IrqHandler(void); -extern WEAK void CRCCU_IrqHandler(void); -extern WEAK void ACC_IrqHandler(void); -extern WEAK void USBD_IrqHandler(void); - -#endif /* #ifndef EXCEPTIONS_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.c deleted file mode 100644 index 0d4ea8433..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * FreeModbus Libary: Atmel AT91SAM3S Demo Application - * Copyright (C) 2010 Christian Walter - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * IF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * File: $Id$ - */ - -/* ----------------------- AT91SAM3S includes -------------------------------*/ -#include -#include - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define REG_INPUT_START ( 1000 ) -#define REG_INPUT_NREGS ( 64 ) - -#define REG_HOLDING_START ( 1 ) -#define REG_HOLDING_NREGS ( 32 ) - -/* ----------------------- Static functions ---------------------------------*/ -static void _SetupHardware( void ); - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegInputStart = REG_INPUT_START; -static USHORT usRegInputBuf[REG_INPUT_NREGS]; -static USHORT usRegHoldingStart = REG_HOLDING_START; -static USHORT usRegHoldingBuf[REG_HOLDING_NREGS]; - -/* ----------------------- Start implementation -----------------------------*/ -int -main( void ) -{ - _SetupHardware( ); - - const UCHAR ucSlaveID[] = { 0xAA, 0xBB, 0xCC }; - eMBErrorCode eStatus; - - for( ;; ) - { - if( MB_ENOERR != ( eStatus = eMBInit( MB_RTU, 0x0A, 1, 38400, MB_PAR_EVEN ) ) ) - { - /* Can not initialize. Add error handling code here. */ - } - else - { - if( MB_ENOERR != ( eStatus = eMBSetSlaveID( 0x34, TRUE, ucSlaveID, 3 ) ) ) - { - /* Can not set slave id. Check arguments */ - } - else if( MB_ENOERR != ( eStatus = eMBEnable( ) ) ) - { - /* Enable failed. */ - } - else - { - usRegHoldingBuf[0] = 1; - do - { - ( void )eMBPoll( ); - - /* Here we simply count the number of poll cycles. */ - usRegInputBuf[0]++; - } - while( usRegHoldingBuf[0] ); - ( void )eMBDisable( ); - ( void )eMBClose( ); - } - } - } - return 1; -} - -void _SetupHardware( void ) -{ - WDT_Disable( ); - - uint32_t i = 0; - for( i = 0; i < 35; i++ ) - { - NVIC_SetPriority( (IRQn_Type)i, 0xF << 4 ) ; - } -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = - ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = - ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_HOLDING_START ) && ( usAddress + usNRegs <= REG_HOLDING_START + REG_HOLDING_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegHoldingStart ); - switch ( eMode ) - { - case MB_REG_READ: - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegHoldingBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegHoldingBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - break; - - case MB_REG_WRITE: - while( usNRegs > 0 ) - { - usRegHoldingBuf[iRegIndex] = *pucRegBuffer++ << 8; - usRegHoldingBuf[iRegIndex] |= *pucRegBuffer++; - iRegIndex++; - usNRegs--; - } - } - } - else - { - eStatus = MB_ENOREG; - } - return eStatus; -} - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, - eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.ewp b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.ewp deleted file mode 100644 index 861dd43ab..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.ewp +++ /dev/null @@ -1,1758 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 17 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 22 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 7 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 17 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 22 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 7 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 9 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - board - - $PROJ_DIR$\board\board_cstartup_iar.c - - - $PROJ_DIR$\board\board_lowlevel.c - - - $PROJ_DIR$\board\board_memories.c - - - $PROJ_DIR$\board\exceptions.c - - - - drivers - - $PROJ_DIR$\libraries\drivers\pio\pio.c - - - $PROJ_DIR$\libraries\drivers\pmc\pmc.c - - - $PROJ_DIR$\libraries\drivers\tc\tc.c - - - $PROJ_DIR$\libraries\drivers\usart\usart.c - - - $PROJ_DIR$\libraries\drivers\wdt\wdt.c - - - - modbus - - $PROJ_DIR$\..\..\modbus\mb.c - - - $PROJ_DIR$\..\..\modbus\include\mb.h - - - $PROJ_DIR$\..\..\modbus\ascii\mbascii.c - - - $PROJ_DIR$\..\..\modbus\ascii\mbascii.h - - - $PROJ_DIR$\..\..\modbus\include\mbconfig.h - - - $PROJ_DIR$\..\..\modbus\rtu\mbcrc.c - - - $PROJ_DIR$\..\..\modbus\rtu\mbcrc.h - - - $PROJ_DIR$\..\..\modbus\include\mbframe.h - - - $PROJ_DIR$\..\..\modbus\include\mbfunc.h - - - $PROJ_DIR$\..\..\modbus\functions\mbfunccoils.c - - - $PROJ_DIR$\..\..\modbus\functions\mbfuncdiag.c - - - $PROJ_DIR$\..\..\modbus\functions\mbfuncdisc.c - - - $PROJ_DIR$\..\..\modbus\functions\mbfuncholding.c - - - $PROJ_DIR$\..\..\modbus\functions\mbfuncinput.c - - - $PROJ_DIR$\..\..\modbus\functions\mbfuncother.c - - - $PROJ_DIR$\..\..\modbus\include\mbport.h - - - $PROJ_DIR$\..\..\modbus\include\mbproto.h - - - $PROJ_DIR$\..\..\modbus\rtu\mbrtu.c - - - $PROJ_DIR$\..\..\modbus\rtu\mbrtu.h - - - $PROJ_DIR$\..\..\modbus\functions\mbutils.c - - - $PROJ_DIR$\..\..\modbus\include\mbutils.h - - - - port - - $PROJ_DIR$\port\port.h - - - $PROJ_DIR$\port\portevent.c - - - $PROJ_DIR$\port\portother.c - - - $PROJ_DIR$\port\portserial.c - - - $PROJ_DIR$\port\porttimer.c - - - - $PROJ_DIR$\demo.c - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.eww b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.eww deleted file mode 100644 index 2b25c1341..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\demo.ewp - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo_rtu.bat b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo_rtu.bat deleted file mode 100644 index 402b47572..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/demo_rtu.bat +++ /dev/null @@ -1 +0,0 @@ -..\..\tools\modpoll.exe -m rtu -a 10 -r 1000 -c 4 -t 3 -b 38400 -d 8 -p even COM1 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/cmsis/core_cm3.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/cmsis/core_cm3.c deleted file mode 100644 index b3a9a886d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/cmsis/core_cm3.c +++ /dev/null @@ -1,804 +0,0 @@ -/****************************************************************************** - * @file: core_cm3.c - * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version: V1.10 - * @date: 24. Feb. 2009 - *---------------------------------------------------------------------------- - * - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-Mx - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - - -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for armcc */ - #define __INLINE __inline /*!< inline keyword for armcc */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for iarcc */ - #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */ - #define __nop __no_operation /*!< no operation intrinsic in iarcc */ - -#elif defined ( __GNUC__ ) - #define __ASM asm /*!< asm keyword for gcc */ - #define __INLINE inline /*!< inline keyword for gcc */ -#endif - - - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param int16_t value to reverse - * @return int32_t reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * @param none - * @return none - * - * Removes the exclusive lock which is created by ldrex. - */ -__ASM void __CLREX(void) -{ - clrex -} - -/** - * @brief Return the Base Priority value - * - * @param none - * @return uint32_t BasePriority - * - * Return the content of the base priority register - */ -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} - -/** - * @brief Set the Base Priority value - * - * @param uint32_t BasePriority - * @return none - * - * Set the base priority register - */ -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} - -/** - * @brief Return the Priority Mask value - * - * @param none - * @return uint32_t PriMask - * - * Return the state of the priority mask bit from the priority mask - * register - */ -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} - -/** - * @brief Set the Priority Mask value - * - * @param uint32_t PriMask - * @return none - * - * Set the priority mask bit in the priority mask register - */ -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} - -/** - * @brief Return the Fault Mask value - * - * @param none - * @return uint32_t FaultMask - * - * Return the content of the fault mask register - */ -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} - -/** - * @brief Set the Fault Mask value - * - * @param uint32_t faultMask value - * @return none - * - * Set the fault mask register - */ -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} - -/** - * @brief Return the Control Register value - * - * @param none - * @return uint32_t Control value - * - * Return the content of the control register - */ -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} - -/** - * @brief Set the Control Register value - * - * @param uint32_t Control value - * @return none - * - * Set the control register - */ -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} - -#endif /* __ARMCC_VERSION */ - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -#pragma diag_suppress=Pe940 - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse bit order of value - * - * @param uint32_t value to reverse - * @return uint32_t reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive - * - * @param uint8_t* address - * @return uint8_t value of (*address) - * - * Exclusive LDR command - */ -uint8_t __LDREXB(uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive - * - * @param uint16_t* address - * @return uint16_t value of (*address) - * - * Exclusive LDR command - */ -uint16_t __LDREXH(uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive - * - * @param uint32_t* address - * @return uint32_t value of (*address) - * - * Exclusive LDR command - */ -uint32_t __LDREXW(uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive - * - * @param uint8_t *address - * @param uint8_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive - * - * @param uint16_t *address - * @param uint16_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive - * - * @param uint32_t *address - * @param uint32_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); - __ASM("bx lr"); -} - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) ); -} - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) ); -} - -/** - * @brief Return the Base Priority value - * - * @param none - * @return uint32_t BasePriority - * - * Return the content of the base priority register - */ -uint32_t __get_BASEPRI(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Base Priority value - * - * @param uint32_t BasePriority - * @return none - * - * Set the base priority register - */ -void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - -/** - * @brief Return the Priority Mask value - * - * @param none - * @return uint32_t PriMask - * - * Return the state of the priority mask bit from the priority mask - * register - */ -uint32_t __get_PRIMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Priority Mask value - * - * @param uint32_t PriMask - * @return none - * - * Set the priority mask bit in the priority mask register - */ -void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - -/** - * @brief Return the Fault Mask value - * - * @param none - * @return uint32_t FaultMask - * - * Return the content of the fault mask register - */ -uint32_t __get_FAULTMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Fault Mask value - * - * @param uint32_t faultMask value - * @return none - * - * Set the fault mask register - */ -void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -/** - * @brief Reverse byte order in integer value - * - * @param uint32_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in integer value - */ -uint32_t __REV(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param int32_t value to reverse - * @return int32_t reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -int32_t __REVSH(int16_t value) -{ - uint32_t result=0; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse bit order of value - * - * @param uint32_t value to reverse - * @return uint32_t reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief LDR Exclusive - * - * @param uint8_t* address - * @return uint8_t value of (*address) - * - * Exclusive LDR command - */ -uint8_t __LDREXB(uint8_t *addr) -{ - uint8_t result=0; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive - * - * @param uint16_t* address - * @return uint16_t value of (*address) - * - * Exclusive LDR command - */ -uint16_t __LDREXH(uint16_t *addr) -{ - uint16_t result=0; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive - * - * @param uint32_t* address - * @return uint32_t value of (*address) - * - * Exclusive LDR command - */ -uint32_t __LDREXW(uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief STR Exclusive - * - * @param uint8_t *address - * @param uint8_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive - * - * @param uint16_t *address - * @param uint16_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive - * - * @param uint32_t *address - * @param uint32_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief Return the Control Register value - * - * @param none - * @return uint32_t Control value - * - * Return the content of the control register - */ -uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param uint32_t Control value - * @return none - * - * Set the control register - */ -void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - -#endif - - - - - - - - - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/cmsis/core_cm3.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/cmsis/core_cm3.h deleted file mode 100644 index 59b054ded..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/cmsis/core_cm3.h +++ /dev/null @@ -1,1265 +0,0 @@ -/****************************************************************************** - * @file: core_cm3.h - * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version: V1.10 - * @date: 24. Feb. 2009 - *---------------------------------------------------------------------------- - * - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-Mx - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - - - -#ifndef __CM3_CORE_H__ -#define __CM3_CORE_H__ - - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -/** - * Lint configuration \n - * ----------------------- \n - * - * The following Lint messages will be suppressed and not shown: \n - * \n - * --- Error 10: --- \n - * register uint32_t __regBasePri __asm("basepri"); \n - * Error 10: Expecting ';' \n - * \n - * --- Error 530: --- \n - * return(__regBasePri); \n - * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n - * \n - * --- Error 550: --- \n - * __regBasePri = (basePri & 0x1ff); \n - * } \n - * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n - * \n - * --- Error 754: --- \n - * uint32_t RESERVED0[24]; \n - * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced \n - * \n - * --- Error 750: --- \n - * #define __CM3_CORE_H__ \n - * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n - * \n - * --- Error 528: --- \n - * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n - * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n - * \n - * --- Error 751: --- \n - * } InterruptType_Type; \n - * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n - * \n - * \n - * Note: To re-enable a Message, insert a space before 'lint' * \n - * - */ - -/*lint -save */ -/*lint -e10 */ -/*lint -e530 */ -/*lint -e550 */ -/*lint -e754 */ -/*lint -e750 */ -/*lint -e528 */ -/*lint -e751 */ - - -#include /* Include standard types */ - -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ -#endif - - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#define __I volatile const /*!< defines 'read only' permissions */ -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ - - -/* System Reset */ -#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */ -#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */ -#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */ -#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */ - -/* Core Debug */ -#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */ -#define ITM_TCR_ITMENA 1 /*!< ITM enable */ - - - - -/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Software Trigger Interrupt Register */ -} NVIC_Type; - - -/* memory mapping struct for System Control Block */ -typedef struct -{ - __I uint32_t CPUID; /*!< CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< System Control Register */ - __IO uint32_t CCR; /*!< Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Processor Feature Register */ - __I uint32_t DFR; /*!< Debug Feature Register */ - __I uint32_t ADR; /*!< Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< ISA Feature Register */ -} SCB_Type; - - -/* memory mapping struct for SysTick */ -typedef struct -{ - __IO uint32_t CTRL; /*!< SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< SysTick Current Value Register */ - __I uint32_t CALIB; /*!< SysTick Calibration Register */ -} SysTick_Type; - - -/* memory mapping structur for ITM */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< ITM Integration Write Register */ - __IO uint32_t IRR; /*!< ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< ITM Lock Access Register */ - __IO uint32_t LSR; /*!< ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< ITM Product ID Registers */ - __I uint32_t PID5; - __I uint32_t PID6; - __I uint32_t PID7; - __I uint32_t PID0; - __I uint32_t PID1; - __I uint32_t PID2; - __I uint32_t PID3; - __I uint32_t CID0; - __I uint32_t CID1; - __I uint32_t CID2; - __I uint32_t CID3; -} ITM_Type; - - -/* memory mapped struct for Interrupt Type */ -typedef struct -{ - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Interrupt Control Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Auxiliary Control Register */ -#else - uint32_t RESERVED1; -#endif -} InterruptType_Type; - - -/* Memory Protection Unit */ -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) -typedef struct -{ - __I uint32_t TYPE; /*!< MPU Type Register */ - __IO uint32_t CTRL; /*!< MPU Control Register */ - __IO uint32_t RNR; /*!< MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; -#endif - - -/* Core Debug Register */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ -#endif - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - #define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ - -#elif defined ( __GNUC__ ) - #define __ASM asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#define __enable_fault_irq __enable_fiq -#define __disable_fault_irq __disable_fiq - -#define __NOP __nop -#define __WFI __wfi -#define __WFE __wfe -#define __SEV __sev -#define __ISB() __isb(0) -#define __DSB() __dsb(0) -#define __DMB() __dmb(0) -#define __REV __rev -#define __RBIT __rbit -#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) -#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) -#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) -#define __STREXB(value, ptr) __strex(value, ptr) -#define __STREXH(value, ptr) __strex(value, ptr) -#define __STREXW(value, ptr) __strex(value, ptr) - - - /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ - /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ - /* intrinsic void __enable_irq(); */ - /* intrinsic void __disable_irq(); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/* - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param int16_t value to reverse - * @return int32_t reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * @param none - * @return none - * - * Removes the exclusive lock which is created by ldrex. - */ -extern void __CLREX(void); - -/** - * @brief Return the Base Priority value - * - * @param none - * @return uint32_t BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param uint32_t BasePriority - * @return none - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @param none - * @return uint32_t PriMask - * - * Return the state of the priority mask bit from the priority mask - * register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param uint32_t PriMask - * @return none - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @param none - * @return uint32_t FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param uint32_t faultMask value - * @return none - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value - * - * @param none - * @return uint32_t Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param uint32_t Control value - * @return none - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -#else /* (__ARMCC_VERSION >= 400000) */ - - -/** - * @brief Remove the exclusive lock created by ldrex - * - * @param none - * @return none - * - * Removes the exclusive lock which is created by ldrex. - */ -#define __CLREX __clrex - -/** - * @brief Return the Base Priority value - * - * @param none - * @return uint32_t BasePriority - * - * Return the content of the base priority register - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - -/** - * @brief Set the Base Priority value - * - * @param uint32_t BasePriority - * @return none - * - * Set the base priority register - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0x1ff); -} - -/** - * @brief Return the Priority Mask value - * - * @param none - * @return uint32_t PriMask - * - * Return the state of the priority mask bit from the priority mask - * register - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - -/** - * @brief Set the Priority Mask value - * - * @param uint32_t PriMask - * @return none - * - * Set the priority mask bit in the priority mask register - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - -/** - * @brief Return the Fault Mask value - * - * @param none - * @return uint32_t FaultMask - * - * Return the content of the fault mask register - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - -/** - * @brief Set the Fault Mask value - * - * @param uint32_t faultMask value - * @return none - * - * Set the fault mask register - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); -} - -/** - * @brief Return the Control Register value - * - * @param none - * @return uint32_t Control value - * - * Return the content of the control register - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - -/** - * @brief Set the Control Register value - * - * @param uint32_t Control value - * @return none - * - * Set the control register - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ -#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ - -static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } - -static __INLINE void __WFI() { __ASM ("wfi"); } -static __INLINE void __WFE() { __ASM ("wfe"); } -static __INLINE void __SEV() { __ASM ("sev"); } -static __INLINE void __CLREX() { __ASM ("clrex"); } - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse bit order of value - * - * @param uint32_t value to reverse - * @return uint32_t reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive - * - * @param uint8_t* address - * @return uint8_t value of (*address) - * - * Exclusive LDR command - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive - * - * @param uint16_t* address - * @return uint16_t value of (*address) - * - * Exclusive LDR command - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive - * - * @param uint32_t* address - * @return uint32_t value of (*address) - * - * Exclusive LDR command - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint8_t *address - * @param uint8_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint16_t *address - * @param uint16_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint32_t *address - * @param uint32_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - -/* intrinsic void __set_PRIMASK(); */ -/* intrinsic void __get_PRIMASK(); */ -/* intrinsic void __set_FAULTMASK(); */ -/* intrinsic void __get_FAULTMASK(); */ -/* intrinsic uint32_t __REV(uint32_t value); */ -/* intrinsic uint32_t __REVSH(uint32_t value); */ -/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ -/* intrinsic unsigned long __LDREX(unsigned long *); */ - - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -static __INLINE void __NOP() { __ASM volatile ("nop"); } -static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } -static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } - -static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } - -static __INLINE void __WFI() { __ASM volatile ("wfi"); } -static __INLINE void __WFE() { __ASM volatile ("wfe"); } -static __INLINE void __SEV() { __ASM volatile ("sev"); } -static __INLINE void __ISB(arg) { __ASM volatile ("isb"); } -static __INLINE void __DSB(arg) { __ASM volatile ("dsb"); } -static __INLINE void __DMB(arg) { __ASM volatile ("dmb"); } -static __INLINE void __CLREX() { __ASM volatile ("clrex"); } - - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Return the Base Priority value - * - * @param none - * @return uint32_t BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param uint32_t BasePriority - * @return none - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @param none - * @return uint32_t PriMask - * - * Return the state of the priority mask bit from the priority mask - * register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param uint32_t PriMask - * @return none - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @param none - * @return uint32_t FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param uint32_t faultMask value - * @return none - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value -* -* @param none -* @return uint32_t Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param uint32_t Control value - * @return none - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -/** - * @brief Reverse byte order in integer value - * - * @param uint32_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in integer value - */ -extern uint32_t __REV(uint32_t value); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/* - * Reverse byte order in signed short value with sign extension to integer - * - * @param int16_t value to reverse - * @return int32_t reversed value - * - * @brief Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - -/** - * @brief Reverse bit order of value - * - * @param uint32_t value to reverse - * @return uint32_t reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive - * - * @param uint8_t* address - * @return uint8_t value of (*address) - * - * Exclusive LDR command - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive - * - * @param uint16_t* address - * @return uint16_t value of (*address) - * - * Exclusive LDR command - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive - * - * @param uint32_t* address - * @return uint32_t value of (*address) - * - * Exclusive LDR command - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint8_t *address - * @param uint8_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint16_t *address - * @param uint16_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint32_t *address - * @param uint32_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - -#endif - - - -/* ########################## NVIC functions #################################### */ - -/** - * @brief Set the Priority Grouping in NVIC Interrupt Controller - * - * @param uint32_t priority_grouping is priority grouping field - * @return - * - * Set the priority grouping field using the required unlock sequence. - * The parameter priority_grouping is assigned to the field - * SCB->AIRCR [10:8] PRIGROUP field. - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t priority_grouping) -{ - uint32_t reg_value=0; - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */ - reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (priority_grouping << 8))); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn_Type IRQn specifies the interrupt number - * @return none - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn_Type IRQn is the positive number of the external interrupt - * @return none - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - -/** - * @brief Read the interrupt pending bit for a device specific interrupt source - * - * @param IRQn_Type IRQn is the number of the device specifc interrupt - * @return IRQn_Type Number of pending interrupt or zero - * - * Read the pending register in NVIC and return the number of the - * specified interrupt if its status is pending, otherwise it returns - * zero. The interrupt number cannot be a negative value. - */ -static __INLINE IRQn_Type NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((IRQn_Type) (NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))); /* Return Interrupt bit or 'zero' */ -} - -/** - * @brief Set the pending bit for an external interrupt - * - * @param IRQn_Type IRQn is the Number of the interrupt - * @return none - * - * Set the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - -/** - * @brief Clear the pending bit for an external interrupt - * - * @param IRQn_Type IRQn is the Number of the interrupt - * @return none - * - * Clear the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - -/** - * @brief Read the active bit for an external interrupt - * - * @param IRQn_Type IRQn is the Number of the interrupt - * @return IRQn_Type Number of pending interrupt or zero - * - * Read the active register in NVIC and returns the number of the - * specified interrupt if its status is active, otherwise it - * returns zero. The interrupt number cannot be a negative value. - */ -static __INLINE IRQn_Type NVIC_GetActive(IRQn_Type IRQn) -{ - return((IRQn_Type)(NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))); /* Return Interruptnumber or 'zero' */ -} - -/** - * @brief Set the priority for an interrupt - * - * @param IRQn_Type IRQn is the Number of the interrupt - * @param priority is the priority for the interrupt - * @return none - * - * Set the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. \n - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, int32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ - else { - //NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ - NVIC->IP[(uint32_t)(IRQn)] = (priority & 0xff); } /* set Priority for device specific Interrupts */ -} - -/** - * @brief Read the priority for an interrupt - * - * @param IRQn_Type IRQn is the Number of the interrupt - * @return priority is the priority for the interrupt - * - * Read the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * The returned priority value is automatically aligned to the implemented - * priority bits of the microcontroller. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - - -/* ################################## SysTick function ############################################ */ - -#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) - -/* SysTick constants */ -#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */ -#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */ -#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */ -#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */ - -/** - * @brief Initialize and start the SysTick counter and its interrupt. - * - * @param uint32_t ticks is the number of ticks between two interrupts - * @return none - * - * Initialise the system tick timer and its interrupt and start the - * system tick timer / counter in free running mode to generate - * periodical interrupts. - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = (0x00); /* Load the SysTick Counter Value */ - SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<DEMCR & CoreDebug_DEMCR_TRCENA) && - (ITM->TCR & ITM_TCR_ITMENA) && - (ITM->TER & (1UL << 0)) ) - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - -#endif - -/*lint -restore */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/acc/acc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/acc/acc.c deleted file mode 100644 index 2c3e00809..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/acc/acc.c +++ /dev/null @@ -1,164 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup adc_module Working with ACC - * The ACC driver provides the interface to configure and use the ACC peripheral.\n - * - * It converts the analog input to digital format. The converted result could be 12bit - * or 10bit. The ACC supports up to 16 analog lines. - * - * To Enable a ACC conversion,the user has to follow these few steps: - *
    - *
  • Select an appropriate reference voltage on ADVREF
  • - *
  • Configure the ACC according to its requirements and special needs,which could be - broken down into several parts: - * -# Select the resolution by setting or clearing ACC_MR_LOWRES bit in ACC_MR (Mode Register) - * -# Set ACC clock by setting ACC_MR_PRESCAL bits in ACC_MR, the clock is caculated with - ACCClock = MCK / ( (PRESCAL+1) * 2 ) - * -# Set Startup Time,Tracking Clock cycles and Transfer Clock respeticively in ACC_MR. -
  • - *
  • Start conversion by setting ACC_CR_START in ACC_CR.
  • - *
- * - * For more accurate information, please look at the ACC section of the - * Datasheet. - * - * Related files :\n - * \ref adc.c\n - * \ref adc.h\n -*/ -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include -#include - - - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Initialize the ACC controller - * \param pAcc Pointer to an Acc instance. - * \param idAcc ACC identifier - * \param selplus input connected to inp, 0~7 - * \param selminus input connected to inm,0~7 - * \param ac_en Analog comprator enabled/disabled,use pattern - * \param edge CF flag triggering mode,use pattern - * \param invert INVert comparator output,use pattern defined in the device header - file -*/ -void ACC_Configure(Acc *pAcc, - uint8_t idAcc, - uint8_t selplus, - uint8_t selminus, - uint16_t ac_en, - uint16_t edge, - uint16_t invert) -{ - - /* Enable peripheral clock*/ - PMC->PMC_PCER1 = 1 << (idAcc-32); - - /* Reset the controller */ - pAcc->ACC_CR |= ACC_CR_SWRST; - - /* Write to the MR register */ - ACC_CfgModeReg( pAcc, - ( selplus & ACC_MR_SELPLUS) - | (( selminus<<4) & ACC_MR_SELMINUS) - | ( ac_en & ACC_MR_ACEN) - | ( edge & ACC_MR_EDGETYP) - | ( invert & ACC_MR_INV) ); - //pAcc->ACC_MR |= (ACC_MR_SELFS_OUTPUT|ACC_MR_FE_EN); - - pAcc->ACC_ACR = 0x7; - - while(pAcc->ACC_ISR & (uint32_t)ACC_ISR_MASK); -} - - -/** - * Return the Channel Converted Data - * \param pAdc Pointer to an Adc instance. - * \param channel channel to get converted value - * \return Channel converted data of the specified channel - */ -void ACC_SetComparisionPair(Acc *pAcc, uint8_t selplus,uint8_t selminus) -{ - - uint32_t temp; - - ASSERT(selplus < 8 && selminus < 8,"The assigned channel number is invalid!"); - - temp = pAcc->ACC_MR; - - pAcc->ACC_MR = temp & (~ACC_MR_SELMINUS)&(~ACC_MR_SELPLUS); - - pAcc->ACC_MR |= ((selplus & ACC_MR_SELPLUS)|((selminus<<4) & ACC_MR_SELMINUS)); - -} -/** - * Return Comparison Result - * \param pAcc Pointer to an Acc instance. - * \param status value of ACC_ISR - */ -uint8_t ACC_GetComparisionResult(Acc *pAcc,uint32_t status) -{ - uint32_t temp = pAcc->ACC_MR; - if( (temp & ACC_MR_INV)== ACC_MR_INV) - { - - if( status & ACC_ISR_SCO) - { - return 0; /* inn>inp*/ - } - else return 1;/* inp>inn*/ - - } - else - { - - if( status & ACC_ISR_SCO) - { - return 1; /* inp>inn*/ - } - else return 0;/* inn>inp*/ - } - -} - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/acc/acc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/acc/acc.h deleted file mode 100644 index 284d8d44a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/acc/acc.h +++ /dev/null @@ -1,144 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \unit - * - * !Purpose - * - * Interface for configuration the Analog-to-Digital Converter (ACC) peripheral. - * - * !Usage - * - * -# Configurate the pins for ACC - * -# Initialize the ACC with ACC_Initialize(). - * -# Select the active channel using ACC_EnableChannel() - * -# Start the conversion with ACC_StartConversion() - * -# Wait the end of the conversion by polling status with ACC_GetStatus() - * -# Finally, get the converted data using ACC_GetConvertedData() - * -*/ -#ifndef ACC_H -#define ACC_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include - -/*------------------------------------------------------------------------------ - * Definitions - *------------------------------------------------------------------------------*/ -#define ACC_SELPLUS_AD12B0 0 -#define ACC_SELPLUS_AD12B1 1 -#define ACC_SELPLUS_AD12B2 2 -#define ACC_SELPLUS_AD12B3 3 -#define ACC_SELPLUS_AD12B4 4 -#define ACC_SELPLUS_AD12B5 5 -#define ACC_SELPLUS_AD12B6 6 -#define ACC_SELPLUS_AD12B7 7 -#define ACC_SELMINUS_TS 0 -#define ACC_SELMINUS_ADVREF 1 -#define ACC_SELMINUS_DAC0 2 -#define ACC_SELMINUS_DAC1 3 -#define ACC_SELMINUS_AD12B0 4 -#define ACC_SELMINUS_AD12B1 5 -#define ACC_SELMINUS_AD12B2 6 -#define ACC_SELMINUS_AD12B3 7 - - -/*------------------------------------------------------------------------------ - * Macros function of register access - *------------------------------------------------------------------------------*/ -#define ACC_CfgModeReg(pAcc, mode) { \ - (pAcc)->ACC_MR = (mode);\ - } - -#define ACC_GetModeReg(pAcc) ((pAcc)->ACC_MR) - -#define ACC_StartConversion(pAcc) ((pAcc)->ACC_CR = ACC_CR_START) - -#define ACC_SoftReset(pAcc) ((pAcc)->ACC_CR = ACC_CR_SWRST) - -#define ACC_EnableChannel(pAcc, channel) {\ - ASSERT(channel < 16, "ACC Channel not exist");\ - (pAcc)->ACC_CHER = (1 << (channel));\ - } - -#define ACC_DisableChannel (pAcc, channel) {\ - ASSERT((channel) < 16, "ACC Channel not exist");\ - (pAcc)->ACC_CHDR = (1 << (channel));\ - } - -#define ACC_EnableIt(pAcc, mode) {\ - ASSERT(((mode)&0xFFF00000)== 0, "ACC bad interrupt IER");\ - (pAcc)->ACC_IER = (mode);\ - } - -#define ACC_DisableIt(pAcc, mode) {\ - ASSERT(((mode)&0xFFF00000)== 0, "ACC bad interrupt IDR");\ - (pAcc)->ACC_IDR = (mode);\ - } - -#define ACC_EnableDataReadyIt(pAcc) ((pAcc)->ACC_IER = AT91C_ACC_DRDY) - -#define ACC_GetStatus(pAcc) ((pAcc)->ACC_ISR) - -#define ACC_GetChannelStatus(pAcc) ((pAcc)->ACC_CHSR) - -#define ACC_GetInterruptMaskStatus(pAcc) ((pAcc)->ACC_IMR) - -#define ACC_GetLastConvertedData(pAcc) ((pAcc)->ACC_LCDR) - -#define ACC_CfgAnalogCtrlReg(pAcc,mode) {\ - ASSERT(((mode) & 0xFFFCFF3C)==0, "ACC bad analog control config");\ - (pAcc)->ACC_ACR = (mode);\ - } - -#define ACC_CfgExtModeReg(pAcc, extmode) {\ - ASSERT(((extmode) & 0xFF00FFFE)==0, "ACC bad extended mode config");\ - (pAcc)->ACC_EMR = (extmode);\ - } - -#define ACC_GetAnalogCtrlReg(pAcc) ((pAcc)->ACC_ACR) - -/*------------------------------------------------------------------------------ - * Exported functions - *------------------------------------------------------------------------------*/ -void ACC_Configure(Acc *pAcc, - uint8_t idAcc, - uint8_t selplus, - uint8_t selminus, - uint16_t ac_en, - uint16_t edge, - uint16_t invert); - -extern uint8_t ACC_GetComparisionResult(Acc *pAcc,uint32_t status); - -#endif //#ifndef ACC_H diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/adc/adc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/adc/adc.c deleted file mode 100644 index 241a8d935..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/adc/adc.c +++ /dev/null @@ -1,231 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup adc_module Working with ADC - * The ADC driver provides the interface to configure and use the ADC peripheral. - * \n - * - * It converts the analog input to digital format. The converted result could be - * 12bit or 10bit. The ADC supports up to 16 analog lines. - * - * To Enable a ADC conversion,the user has to follow these few steps: - *
    - *
  • Select an appropriate reference voltage on ADVREF
  • - *
  • Configure the ADC according to its requirements and special needs,which - * could be broken down into several parts: - * -# Select the resolution by setting or clearing ADC_MR_LOWRES bit in - * ADC_MR (Mode Register) - * -# Set ADC clock by setting ADC_MR_PRESCAL bits in ADC_MR, the clock is - * calculated with ADCClock = MCK / ( (PRESCAL+1) * 2 ) - * -# Set Startup Time,Tracking Clock cycles and Transfer Clock respectively - * in ADC_MR. -
  • - *
  • Start conversion by setting ADC_CR_START in ADC_CR.
  • - *
- * - * For more accurate information, please look at the ADC section of the - * Datasheet. - * - * Related files :\n - * \ref adc.c\n - * \ref adc.h\n -*/ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include -#include - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Initialize the ADC controller - * \param pAdc Pointer to an Adc instance. - * \param trgEn trigger mode, software or Hardware - * \param trgSel hardware trigger selection - * \param sleepMode sleep mode selection - * \param resolution resolution selection 10 bits or 12 bits - * \param mckClock value of MCK in Hz - * \param adcClock value of the ADC clock in Hz - * \param startupTime value of the start up time (in ADCClock) (see datasheet) - * \param trackingt Tracking Time (in ADCClock cycle) -*/ -void ADC_Initialize(Adc *pAdc, uint8_t idAdc, uint8_t trgEn, uint8_t trgSel, - uint8_t sleepMode, uint8_t resolution, uint32_t mckClock, - uint32_t adcClock, uint32_t startup, uint32_t tracking) { - uint32_t prescal; - prescal = (mckClock / (2*adcClock)) - 1; - - ASSERT( (prescal<0x3F), "ADC Bad PRESCAL\n\r"); - - TRACE_DEBUG("adcClock:%lu MasterClock:%lu\n\r", (mckClock/((prescal+1)*2)), - mckClock); - - if( adcClock != (mckClock/((prescal+1)*2)) ) { - TRACE_WARNING("User and calculated adcClocks are different : " - "user=%lu calc=%lu\n\r", - adcClock, (mckClock/((prescal+1)*2))); - } - - /* Enable peripheral clock*/ - PMC->PMC_PCER0 = 1 << idAdc; - - /* Reset the controller */ - ADC_SoftReset(pAdc); - - /* Write to the MR register */ - ADC_CfgModeReg( pAdc, - ( trgEn & ADC_MR_TRGEN) - | ( trgSel & ADC_MR_TRGSEL) - | ( resolution & ADC_MR_LOWRES) - | ( sleepMode & ADC_MR_SLEEP) - | ( (prescal<<8) & ADC_MR_PRESCAL) - | ( (startup<<16) & ADC_MR_STARTUP) - | ( (tracking<<24) & ADC_MR_TRACKTIM) ); -} - -/** - * Return the Channel Converted Data - * \param pAdc Pointer to an Adc instance. - * \param channel channel to get converted value - */ -uint32_t ADC_GetConvertedData(Adc *pAdc, uint32_t channel) { - uint32_t data=0; - - if (15 >= channel) { - data = *((RoReg *)((uint32_t)&(pAdc->ADC_CDR0)+ channel*4)); - } - return data; -} -/** - * Set compare channel - * \param pAdc Pointer to an Adc instance. - * \param channel channel number to be set,16 for all channels - */ -void ADC_SetCompareChannel(Adc *pAdc, uint8_t channel) { - ASSERT(channel<=16, "Invalid channel number"); - if (channel < 16) { - pAdc->ADC_EMR &= ~(ADC_EMR_CMPALL); - pAdc->ADC_EMR &= ~(ADC_EMR_CMPSEL); - pAdc->ADC_EMR |= (channel << 4); - } else { - pAdc->ADC_EMR |= ADC_EMR_CMPALL; - } -} -/** - * Set compare mode - * \param pAdc Pointer to an Adc instance. - * \param mode compare mode - */ -void ADC_SetCompareMode(Adc *pAdc, uint8_t mode) { - pAdc->ADC_EMR &= ~(ADC_EMR_CMPMODE); - pAdc->ADC_EMR |= mode; -} -/** - * Set comparsion window,one thereshold each time - * \param pAdc Pointer to an Adc instance. - * \param hi_lo Comparison Window - */ -void ADC_SetComparisonWindow(Adc *pAdc, uint32_t hi_lo) { - pAdc->ADC_CWR = hi_lo; -} - -/**---------------------------------------------------------------------------- -* Test if ADC Interrupt is Masked -* \param pAdc Pointer to an Adc instance. -* \param flag flag to be tested -* \return 1 if interrupt is masked, otherwise 0 -*/ -uint32_t ADC_IsInterruptMasked(Adc *pAdc, uint32_t flag) { - return (ADC_GetInterruptMaskStatus(pAdc) & flag); -} - -/**---------------------------------------------------------------------------- -* Test if ADC Status is Set -* \param pAdc Pointer to an Adc instance. -* \param flag flag to be tested -* \return 1 if the staus is set; 0 otherwise -*/ -uint32_t ADC_IsStatusSet(Adc *pAdc, uint32_t flag) { - return (ADC_GetStatus(pAdc) & flag); -} - -/**---------------------------------------------------------------------------- -* Test if ADC channel interrupt Status is Set -* \param adc_sr Value of SR register -* \param channel Channel to be tested -* \return 1 if interrupt status is set, otherwise 0 -*/ -uint8_t ADC_IsChannelInterruptStatusSet(uint32_t adc_sr, uint32_t channel) { - uint8_t status; - - if((adc_sr & (1<ADC_RCR == 0) && (pADC->ADC_RNCR == 0)) { - - pADC->ADC_RPR = (uint32_t) pBuffer; - pADC->ADC_RCR = size; - pADC->ADC_PTCR = ADC_PTCR_RXTEN; - - return 1; - } - /* Check if the second PDC bank is free*/ - else if (pADC->ADC_RNCR == 0) { - - pADC->ADC_RNPR = (uint32_t) pBuffer; - pADC->ADC_RNCR = size; - - return 1; - } else { - - return 0; - } - -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/adc/adc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/adc/adc.h deleted file mode 100644 index 702143f0e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/adc/adc.h +++ /dev/null @@ -1,158 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \unit - * - * !Purpose - * - * Interface for configuration the Analog-to-Digital Converter (ADC) peripheral. - * - * !Usage - * - * -# Configurate the pins for ADC - * -# Initialize the ADC with ADC_Initialize(). - * -# Select the active channel using ADC_EnableChannel() - * -# Start the conversion with ADC_StartConversion() - * -# Wait the end of the conversion by polling status with ADC_GetStatus() - * -# Finally, get the converted data using ADC_GetConvertedData() - * -*/ -#ifndef ADC_H -#define ADC_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include - -/*------------------------------------------------------------------------------ - * Definitions - *------------------------------------------------------------------------------*/ -#define ADC_CHANNEL_0 0 -#define ADC_CHANNEL_1 1 -#define ADC_CHANNEL_2 2 -#define ADC_CHANNEL_3 3 -#define ADC_CHANNEL_4 4 -#define ADC_CHANNEL_5 5 -#define ADC_CHANNEL_6 6 -#define ADC_CHANNEL_7 7 -#define ADC_CHANNEL_8 8 -#define ADC_CHANNEL_9 9 -#define ADC_CHANNEL_10 10 -#define ADC_CHANNEL_11 11 -#define ADC_CHANNEL_12 12 -#define ADC_CHANNEL_13 13 -#define ADC_CHANNEL_14 14 -#define ADC_CHANNEL_15 15 - -/*------------------------------------------------------------------------------ - * Macros function of register access - *------------------------------------------------------------------------------*/ -#define ADC_CfgModeReg(pAdc, mode) { \ - ASSERT(((mode)&0xF00000C0)== 0, "ADC Bad configuration ADC MR");\ - (pAdc)->ADC_MR = (mode);\ - } - -#define ADC_GetModeReg(pAdc) ((pAdc)->ADC_MR) - -#define ADC_StartConversion(pAdc) ((pAdc)->ADC_CR = ADC_CR_START) - -#define ADC_SoftReset(pAdc) ((pAdc)->ADC_CR = ADC_CR_SWRST) - -#define ADC_EnableChannel(pAdc, channel) {\ - ASSERT(channel < 16, "ADC Channel not exist");\ - (pAdc)->ADC_CHER = (1 << (channel));\ - } - -#define ADC_DisableChannel (pAdc, channel) {\ - ASSERT((channel) < 16, "ADC Channel not exist");\ - (pAdc)->ADC_CHDR = (1 << (channel));\ - } - -#define ADC_EnableIt(pAdc, mode) {\ - (pAdc)->ADC_IER = (mode);\ - } - -#define ADC_DisableIt(pAdc, mode) {\ - (pAdc)->ADC_IDR = (mode);\ - } - -#define ADC_EnbaleTS(pAdc,mode) {\ - (pAdc)->ADC_ACR |= mode;\ - } - -#define ADC_EnableDataReadyIt(pAdc) ((pAdc)->ADC_IER = AT91C_ADC_DRDY) - -#define ADC_GetStatus(pAdc) ((pAdc)->ADC_ISR) - -#define ADC_GetCompareMode(pAdc) (((pAdc)->ADC_EMR)& (ADC_EMR_CMPMODE)) - -#define ADC_GetChannelStatus(pAdc) ((pAdc)->ADC_CHSR) - -#define ADC_GetInterruptMaskStatus(pAdc) ((pAdc)->ADC_IMR) - -#define ADC_GetLastConvertedData(pAdc) ((pAdc)->ADC_LCDR) - -#define ADC_CfgAnalogCtrlReg(pAdc,mode) {\ - ASSERT(((mode) & 0xFFFCFF3C)==0, "ADC bad analog control config");\ - (pAdc)->ADC_ACR = (mode);\ - } - -#define ADC_CfgExtModeReg(pAdc, extmode) {\ - ASSERT(((extmode) & 0xFF00FFFE)==0, "ADC bad extended mode config");\ - (pAdc)->ADC_EMR = (extmode);\ - } - -#define ADC_GetAnalogCtrlReg(pAdc) ((pAdc)->ADC_ACR) - -/*------------------------------------------------------------------------------ - * Exported functions - *------------------------------------------------------------------------------*/ -extern void ADC_Initialize (Adc *pAdc, - uint8_t idAdc, - uint8_t trgEn, - uint8_t trgSel, - uint8_t sleepMode, - uint8_t resolution, - uint32_t mckClock, - uint32_t adcClock, - uint32_t startupTime, - uint32_t sampleAndHoldTime); -extern uint32_t ADC_GetConvertedData(Adc *pAdc, uint32_t channel); -extern void ADC_SetCompareChannel(Adc *pAdc, uint8_t channel); -extern void ADC_SetCompareMode(Adc *pAdc, uint8_t mode); -extern void ADC_SetComparisonWindow(Adc *pAdc, uint32_t hi_lo); -extern uint32_t ADC_IsInterruptMasked(Adc *pAdc, uint32_t flag); -extern uint32_t ADC_IsStatusSet(Adc *pAdc, uint32_t flag); -extern uint8_t ADC_IsChannelInterruptStatusSet(uint32_t adc_sr, - uint32_t channel); -extern int8_t ADC_ReadBuffer(Adc *pADC,int16_t *pBuffer,int32_t size); - -#endif //#ifndef ADC_H diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/async/async.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/async/async.c deleted file mode 100644 index 65ba73a6e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/async/async.c +++ /dev/null @@ -1,54 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Provide a routine for asynchronos transfer. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include -#include "async.h" - -/*---------------------------------------------------------------------------- - * Global functions - *----------------------------------------------------------------------------*/ - /** - * \brief Returns 1 if the given transfer has ended; otherwise returns 0. - * \param pAsync Pointer to an Async instance. - */ -uint8_t ASYNC_IsFinished(Async *pAsync) -{ - return (pAsync->status != ASYNC_STATUS_PENDING); -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/async/async.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/async/async.h deleted file mode 100644 index af03d0e22..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/async/async.h +++ /dev/null @@ -1,67 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - - /** - * \file - * - * Provide a routine for asynchronos transfer. - * - */ - -#ifndef ASYNC_H -#define ASYNC_H - - -/*---------------------------------------------------------------------------- - * Definition - *----------------------------------------------------------------------------*/ -/** Transfer is still pending.*/ -#define ASYNC_STATUS_PENDING 0xFF - -/*---------------------------------------------------------------------------- - * Type - *----------------------------------------------------------------------------*/ -/** Asynchronous transfer descriptor. */ -typedef struct _Async { - - /** Asynchronous transfer status.*/ - volatile uint8_t status; - /** Callback function to invoke when transfer completes or fails.*/ - void *callback; - /** Driver storage area; do not use.*/ - uint32_t pStorage[4]; -} Async; - -/*---------------------------------------------------------------------------- - * Global functions - *----------------------------------------------------------------------------*/ -extern uint8_t ASYNC_IsFinished(Async *pAsync); - -#endif //#ifndef ASYNC_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/crccu/crccu.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/crccu/crccu.c deleted file mode 100644 index 0e4acec88..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/crccu/crccu.c +++ /dev/null @@ -1,134 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup crccu_module Working with CRCCU - * The CRCCU driver provides the interface to configure and use the CRCCU - * peripheral. - * - * It performs a CRC computation on a Memory Area. CRC computation is performed - * from the LSB to MSB bit. Three different polynomials are available: - * CCIT802.3, CASTAGNOLI and CCIT16. - * - * To computes CRC of a buffer, the user has to follow these few steps: - *
    - *
  • Reset initial CRC by setting RESET bit in CRCCU_CRC_CR,
  • - *
  • Configure CRC descriptor and working mode,
  • - *
  • Start to compute CRC by setting DMAEN in CRCCU_DMA_EN,
  • - *
  • Get CRC value in CRCCU_CRC_SR.
  • - *
- * - * For more accurate information, please look at the CRCCU section of the - * Datasheet. - * - * Related files :\n - * \ref crccu.c\n - * \ref crccu.h.\n -*/ -/*@{*/ -/*@}*/ - -/** - * \file - * - * Implementation of Cyclic Redundancy Check Calculation Unit (CRCCU). - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include "crccu.h" -#include - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ -#define CRCCU_TIMEOUT 0xFFFFFFFF - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ -/** - * \brief Reset initial CRC to 0xFFFFFFFF. - */ -void CRCCU_ResetCrcValue(void) -{ - Crccu *pCrccu = CRCCU; - - pCrccu->CRCCU_CR = CRCCU_CR_RESET; -} - -/** - * \brief Configure the CRCCU. - * - * \param dscrAddr CRC decscriptor address. - * \param mode CRC work mode - */ -void CRCCU_Configure(uint32_t dscrAddr, uint32_t mode) -{ - Crccu *pCrccu = CRCCU; - - pCrccu->CRCCU_DSCR = dscrAddr; - pCrccu->CRCCU_MR = mode; -} - -/** - * \brief Start to compute the CRC of a buffer. - * - * \return The CRC of the buffer. - */ -uint32_t CRCCU_ComputeCrc(void) -{ - Crccu *pCrccu = CRCCU; - uint32_t timeout = 0; - - pCrccu->CRCCU_DMA_EN = CRCCU_DMA_EN_DMAEN; - while (((pCrccu->CRCCU_DMA_SR & CRCCU_DMA_SR_DMASR) == CRCCU_DMA_SR_DMASR) - && (timeout++ < CRCCU_TIMEOUT)); - - return (pCrccu->CRCCU_SR); -} - -/** - * \brief Compare the CRC of a buffer is match to reference CRC. - * - * \return if 0 CRC is match, else dismatch. - */ -uint32_t CRCCU_CompareCrc(void) -{ - Crccu *pCrccu = CRCCU; - - if ((pCrccu->CRCCU_ISR & CRCCU_ISR_ERRISR) == CRCCU_ISR_ERRISR) { - return 1; - } else { - return 0; - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/crccu/crccu.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/crccu/crccu.h deleted file mode 100644 index 7298f6109..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/crccu/crccu.h +++ /dev/null @@ -1,66 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for Cyclic Redundancy Check Calculation Unit (CRCCU). - */ - -#ifndef CRCCU_H -#define CRCCU_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - -typedef struct { - unsigned int TR_ADDR; - unsigned int TR_CTRL; - unsigned int reserved[2]; - unsigned int TR_CRC; -} CrcDscr; - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ -void CRCCU_ResetCrcValue(void); -void CRCCU_Configure(uint32_t dscrAddr, uint32_t mode); -uint32_t CRCCU_ComputeCrc(void); -uint32_t CRCCU_CompareCrc(void); - -#endif /* #ifndef CRCCU_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/dacc/dacc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/dacc/dacc.c deleted file mode 100644 index f576aa497..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/dacc/dacc.c +++ /dev/null @@ -1,172 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup dacc_module Working with DACC - * The DACC driver provides the interface to configure and use the DACC peripheral.\n - * - * The DACC(Digital-to-Analog Converter Controller) converts digital code to analog output. - * The data to be converted are sent in a common register for all channels. It offers up to 2 - * analog outputs.The output voltage ranges from (1/6)ADVREF to (5/6)ADVREF. - * - * To Enable a DACC conversion,the user has to follow these few steps: - *
    - *
  • Select an appropriate reference voltage on ADVREF
  • - *
  • Configure the DACC according to its requirements and special needs,which could be - broken down into several parts: - * -# Enable DACC in free running mode by clearing TRGEN in DACC_MR; - * -# Configure Startup Time and Refresh Period through setting STARTUP and REFRESH fields - * in DACC_MR; The refresh mechanism is used to protect the output analog value from - * decreasing. - * -# Enable channels and write digital code to DACC_CDR,in free running mode, the conversion - * is started right after at least one channel is enabled and data is written . -
  • - *
- * - * For more accurate information, please look at the DACC section of the - * Datasheet. - * - * Related files :\n - * \ref DACC.c\n - * \ref DACC.h\n -*/ -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include -#include - - - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Initialize the DACC controller - * \param pDACC Pointer to an DACC instance. - * \param idDACC identifier of DAC peripheral - * \param trgEn trigger mode, free running mode or external Hardware trigger - * \param word transfer size,word or half word - * \param trgSel hardware trigger selection - * \param sleepMode sleep mode selection - * \param mck value of MCK in Hz - * \param refresh refresh period - * \param user_sel user channel selection ,0 or 1 - * \param startup value of the start up time (in DACCClock) (see datasheet) -*/ -void DACC_Initialize (Dacc *pDACC, - uint8_t idDACC, - uint8_t trgEn, - uint8_t trgSel, - uint8_t word, - uint8_t sleepMode, - uint32_t mck, - uint8_t refresh,/*refresh period*/ - uint8_t user_sel,/*user channel selection*/ - uint32_t startup - ) -{ - ASSERT(1024*refresh*1000/(mck/2)<20,"Refresh preriod is too big!"); - - - /* Enable peripheral clock*/ - PMC->PMC_PCER0 = 1 << idDACC; - - /* Reset the controller */ - DACC_SoftReset(pDACC); - - /* Write to the MR register */ - DACC_CfgModeReg( pDACC, - ( trgEn & DACC_MR_TRGEN) - | ( trgSel & DACC_MR_TRGSEL) - | ( word & DACC_MR_WORD) - | ( sleepMode & DACC_MR_SLEEP) - | ( (refresh<<8) & DACC_MR_REFRESH) - | ( (user_sel<<16)& DACC_MR_USER_SEL) - | ( (startup<<24) & DACC_MR_STARTUP)); -} - - -/** - * Set the Conversion Data - * \param pDACC Pointer to an Dacc instance. - * \param channel channel to get converted value - * \return Channel converted data of the specified channel - */ -void DACC_SetConversionData(Dacc *pDACC, uint32_t data) -{ - uint32_t mr = pDACC->DACC_MR; - - if(mr & DACC_MR_WORD) - { - pDACC->DACC_CDR = data; - } - else - { - pDACC->DACC_CDR = (data&0xFFFF); - } -} - - -/** - * \brief Write converted data through PDC channel - * \param pDACC the pointer of DACC peripheral - * \param pBuffer the destination buffer - * \param size the size of the buffer -*/ -int8_t DACC_WriteBuffer(Dacc *pDACC,int16_t *pBuffer,int32_t size) -{ - - /* Check if the first PDC bank is free*/ - if ((pDACC->DACC_TCR == 0) && (pDACC->DACC_TNCR == 0)) { - - pDACC->DACC_TPR = (uint32_t) pBuffer; - pDACC->DACC_TCR = size; - pDACC->DACC_PTCR = DACC_PTCR_RXTEN; - - return 1; - } - /* Check if the second PDC bank is free*/ - else if (pDACC->DACC_TNCR == 0) { - - pDACC->DACC_TNPR = (uint32_t) pBuffer; - pDACC->DACC_TNCR = size; - - return 1; - } - else { - - return 0; - } - -} - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/dacc/dacc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/dacc/dacc.h deleted file mode 100644 index c2aebada3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/dacc/dacc.h +++ /dev/null @@ -1,133 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \unit - * - * !Purpose - * - * Interface for configuration the Analog-to-Digital Converter (DACC) peripheral. - * - * !Usage - * - * -# Configurate the pins for DACC - * -# Initialize the DACC with DACC_Initialize(). - * -# Select the active channel using DACC_EnableChannel() - * -# Start the conversion with DACC_StartConversion() - * -# Wait the end of the conversion by polling status with DACC_GetStatus() - * -# Finally, get the converted data using DACC_GetConvertedData() - * -*/ -#ifndef DACC_H -#define DACC_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include - -/*------------------------------------------------------------------------------ - * Definitions - *------------------------------------------------------------------------------*/ -#define DACC_CHANNEL_0 0 -#define DACC_CHANNEL_1 1 - - -/*------------------------------------------------------------------------------ - * Macros function of register access - *------------------------------------------------------------------------------*/ -#define DACC_CfgModeReg(pDACC, mode) { \ - (pDACC)->DACC_MR = (mode);\ - } - -#define DACC_GetModeReg(pDACC) ((pDACC)->DACC_MR) - -#define DACC_StartConversion(pDACC) ((pDACC)->DACC_CR = DACC_CR_START) - -#define DACC_SoftReset(pDACC) ((pDACC)->DACC_CR = DACC_CR_SWRST) - -#define DACC_EnableChannel(pDACC, channel) {\ - (pDACC)->DACC_CHER = (1 << (channel));\ - } - -#define DACC_DisableChannel (pDACC, channel) {\ - (pDACC)->DACC_CHDR = (1 << (channel));\ - } - -#define DACC_EnableIt(pDACC, mode) {\ - ASSERT(((mode)&0xFFF00000)== 0, "DACC bad interrupt IER");\ - (pDACC)->DACC_IER = (mode);\ - } - -#define DACC_DisableIt(pDACC, mode) {\ - ASSERT(((mode)&0xFFF00000)== 0, "DACC bad interrupt IDR");\ - (pDACC)->DACC_IDR = (mode);\ - } - -#define DACC_EnableDataReadyIt(pDACC) ((pDACC)->DACC_IER = AT91C_DACC_DRDY) - -#define DACC_GetStatus(pDACC) ((pDACC)->DACC_ISR) - -#define DACC_GetChannelStatus(pDACC) ((pDACC)->DACC_CHSR) - -#define DACC_GetInterruptMaskStatus(pDACC) ((pDACC)->DACC_IMR) - -#define DACC_GetLastConvertedData(pDACC) ((pDACC)->DACC_LCDR) - -#define DACC_CfgAnalogCtrlReg(pDACC,mode) {\ - ASSERT(((mode) & 0xFFFCFF3C)==0, "DACC bad analog control config");\ - (pDACC)->DACC_ACR = (mode);\ - } - -#define DACC_CfgExtModeReg(pDACC, extmode) {\ - ASSERT(((extmode) & 0xFF00FFFE)==0, "DACC bad extended mode config");\ - (pDACC)->DACC_EMR = (extmode);\ - } - -#define DACC_GetAnalogCtrlReg(pDACC) ((pDACC)->DACC_ACR) - -/*------------------------------------------------------------------------------ - * Exported functions - *------------------------------------------------------------------------------*/ -extern void DACC_Initialize (Dacc *pDACC, - uint8_t idDACC, - uint8_t trgEn, - uint8_t trgSel, - uint8_t word, - uint8_t sleepMode, - uint32_t mck, - uint8_t refresh,/*refresh period*/ - uint8_t user_sel,/*user channel selection*/ - uint32_t startup - ); - - -extern void DACC_SetConversionData(Dacc *pDACC, uint32_t data); - -#endif //#ifndef DACC_H diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/efc/efc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/efc/efc.c deleted file mode 100644 index 56ace4b0f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/efc/efc.c +++ /dev/null @@ -1,286 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup efc_module Working with Enhanced Embedded Flash - * The EEFC driver provides the interface to configure and use the EEFC - * peripheral. - * - * The user needs to set the number of wait states depending on the frequency used.\n - * Configure number of cycles for flash read/write operations in the FWS field of EEFC_FMR. - * - * It offers a function to send flash command to EEFC and waits for the - * flash to be ready. - * - * To send flash command, the user could do in either of following way: - *
    - *
  • Write a correct key, command and argument in EEFC_FCR.
  • - *
  • Or, Use IAP (In Application Programming) function which is executed from - * ROM directly, this allows flash programming to be done by code running in flash.
  • - *
  • Once the command is achieved, it can be detected even by polling EEFC_FSR or interrupt. - *
- * - * The command argument could be a page number,GPNVM number or nothing, it depends on - * the command itself. Some useful functions in this driver could help user tranlate physical - * flash address into a page number and vice verse. - * - * For more accurate information, please look at the EEFC section of the - * Datasheet. - * - * Related files :\n - * \ref efc.c\n - * \ref efc.h.\n -*/ -/*@{*/ -/*@}*/ - - -/** - * \file - * - * Implementation of Emhance embedded Flash (EEFC) controller. - * - */ - - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include -#include "efc.h" -#include -#include - - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Enables the flash ready interrupt source on the EEFC peripheral. - * - * \param efc Pointer to a Efc instance - */ -void EFC_EnableFrdyIt(Efc *efc) -{ - efc->EEFC_FMR |= EEFC_FMR_FRDY; -} - -/** - * \brief Disables the flash ready interrupt source on the EEFC peripheral. - * - * \param efc Pointer to a Efc instance - */ - -void EFC_DisableFrdyIt(Efc *efc) -{ - efc->EEFC_FMR &= ~EEFC_FMR_FRDY; -} - - -/** - * \brief Set read/write wait state on the EEFC perpherial. - * - * \param efc Pointer to a Efc instance - * \param cycles the number of wait states in cycle. - */ - -void EFC_SetWaitState(Efc *efc, uint8_t cycles) -{ - uint32_t value; - value = efc->EEFC_FMR; - value &= ~EEFC_FMR_FWS; - value |= cycles << 8; - efc->EEFC_FMR = value; -} - -/** - * \brief Returns the current status of the EEFC. - * - * \note Keep in mind that this function clears the value of some status bits (LOCKE, PROGE). - * - * \param efc Pointer to a Efc instance - */ -uint32_t EFC_GetStatus(Efc *efc) -{ - return efc->EEFC_FSR; -} - -/** - * \brief Returns the result of the last executed command. - * - * \param efc Pointer to a Efc instance - */ -uint32_t EFC_GetResult(Efc *efc) { - - return efc->EEFC_FRR; -} - -/** - * \brief Translates the given address page and offset values. - * \note The resulting values are stored in the provided variables if they are not null. - * - * \param efc Pointer to a Efc instance - * \param address Address to translate. - * \param pPage First page accessed. - * \param pOffset Byte offset in first page. - */ -void EFC_TranslateAddress( - Efc **efc, - uint32_t address, - unsigned short *pPage, - unsigned short *pOffset) -{ - Efc *pEfc; - unsigned short page; - unsigned short offset; - - SANITY_CHECK(address >= AT91C_IFLASH); - SANITY_CHECK(address <= (AT91C_IFLASH + AT91C_IFLASH_SIZE)); - - pEfc = EFC; - page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE; - offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE; - - TRACE_DEBUG("Translated 0x%08X to page=%d and offset=%d\n\r", address, page, offset); - // Store values - if (pEfc) { - *efc = pEfc; - } - if (pPage) { - *pPage = page; - } - if (pOffset) { - *pOffset = offset; - } -} - -/** - * \brief Computes the address of a flash access given the page and offset. - * - * \param efc Pointer to a Efc instance - * \param page Page number. - * \param offset Byte offset inside page. - * \param pAddress Computed address (optional). - */ -void EFC_ComputeAddress( - Efc *efc, - unsigned short page, - unsigned short offset, - uint32_t *pAddress) -{ - uint32_t address; - SANITY_CHECK(efc); - SANITY_CHECK(page <= AT91C_IFLASH_NB_OF_PAGES); - SANITY_CHECK(offset < AT91C_IFLASH_PAGE_SIZE); - // Compute address - address = AT91C_IFLASH + page * AT91C_IFLASH_PAGE_SIZE + offset; - // Store result - if (pAddress) { - *pAddress = address; - } -} - -/** - * \brief Starts the executing the given command on the EEFC and returns as soon as the command is started. - * - * \note It does NOT set the FMCN field automatically. - * \param efc Pointer to a Efc instance - * \param command Command to execute. - * \param argument Command argument (should be 0 if not used). - */ -void EFC_StartCommand(Efc *efc, uint8_t command, unsigned short argument) -{ - // Check command & argument - switch (command) { - - case EFC_FCMD_WP: - case EFC_FCMD_WPL: - case EFC_FCMD_EWP: - case EFC_FCMD_EWPL: - case EFC_FCMD_SLB: - case EFC_FCMD_CLB: - ASSERT(argument < AT91C_IFLASH_NB_OF_PAGES, - "-F- Embedded flash has only %d pages\n\r", - AT91C_IFLASH_NB_OF_PAGES); - break; - - case EFC_FCMD_SFB: - case EFC_FCMD_CFB: - ASSERT(argument < 2, "-F- Embedded flash has only %d GPNVMs\n\r", 2); - break; - - case EFC_FCMD_GETD: - case EFC_FCMD_EA: - case EFC_FCMD_GLB: - case EFC_FCMD_GFB: - case EFC_FCMD_STUI: - ASSERT(argument == 0, "-F- Argument is meaningless for the given command.\n\r"); - break; - - default: ASSERT(0, "-F- Unknown command %d\n\r", command); - } - - // Start command Embedded flash - ASSERT((efc->EEFC_FSR & EEFC_FMR_FRDY) == EEFC_FMR_FRDY, "-F- EEFC is not ready\n\r"); - efc->EEFC_FCR = (0x5A << 24) | (argument << 8) | command; -} - -/** - * \brief Performs the given command and wait until its completion (or an error). - * - * \param efc Pointer to a Efc instance - * \param command Command to perform. - * \param argument Optional command argument. - * \return 0 if successful, otherwise returns an error code. - */ - -uint8_t EFC_PerformCommand(Efc *efc, uint8_t command, unsigned short argument) -{ - -#if defined(flash) || defined(USE_IAP_FEATURE) - // Pointer on IAP function in ROM - static uint32_t (*IAP_PerformCommand)(uint32_t, uint32_t); - IAP_PerformCommand = (uint32_t (*)(uint32_t, uint32_t)) *((uint32_t *) CHIP_FLASH_IAP_ADDRESS); - IAP_PerformCommand(0, (0x5A << 24) | (argument << 8) | command); - return (efc->EEFC_FSR & (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE)); - -#else - uint32_t status; - efc->EEFC_FCR = (0x5A << 24) | (argument << 8) | command; - do { - - status = efc->EEFC_FSR; - } - while ((status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY); - - return (status & (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE)); -#endif -} - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/efc/efc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/efc/efc.h deleted file mode 100644 index 84fabc38f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/efc/efc.h +++ /dev/null @@ -1,112 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * \par Purpose - * - * Interface for configuration the Enhanced Embedded Flash Controller (EEFC) peripheral. - * - * \par Usage - * - * -# Enable/disable %flash ready interrupt sources using EFC_EnableFrdyIt() - * and EFC_DisableFrdyIt(). - * -# Translates the given address into which EEFC, page and offset values - * for difference density %flash memory using EFC_TranslateAddress(). - * -# Computes the address of a %flash access given the EFC, page and offset - * for difference density %flash memory using EFC_ComputeAddress(). - * -# Start the executing command with EFC_StartCommand() - * -# Retrieve the current status of the EFC using EFC_GetStatus(). - * -# Retrieve the result of the last executed command with EFC_GetResult(). - */ - -#ifndef EFC_H -#define EFC_H - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ -/* EFC command */ -#define EFC_FCMD_GETD 0x00 -#define EFC_FCMD_WP 0x01 -#define EFC_FCMD_WPL 0x02 -#define EFC_FCMD_EWP 0x03 -#define EFC_FCMD_EWPL 0x04 -#define EFC_FCMD_EA 0x05 -#define EFC_FCMD_SLB 0x08 -#define EFC_FCMD_CLB 0x09 -#define EFC_FCMD_GLB 0x0A -#define EFC_FCMD_SFB 0x0B -#define EFC_FCMD_CFB 0x0C -#define EFC_FCMD_GFB 0x0D -#define EFC_FCMD_STUI 0x0E -#define EFC_FCMD_SPUI 0x0F - -/* The IAP function entry addreass */ -#define CHIP_FLASH_IAP_ADDRESS (0x00800008) - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void EFC_EnableFrdyIt(Efc *efc); - -extern void EFC_DisableFrdyIt(Efc *efc); - -extern void EFC_SetWaitState(Efc *efc, uint8_t cycles); - -extern void EFC_TranslateAddress( - Efc **pEfc, - uint32_t address, - unsigned short *pPage, - unsigned short *pOffset); - -extern void EFC_ComputeAddress( - Efc *efc, - unsigned short page, - unsigned short offset, - uint32_t *pAddress); - -extern void EFC_StartCommand( - Efc *efc, - uint8_t command, - unsigned short argument); - -extern uint8_t EFC_PerformCommand( - Efc *efc, - uint8_t command, - unsigned short argument); - -extern uint32_t EFC_GetStatus(Efc *efc); - -extern uint32_t EFC_GetResult(Efc *efc); - -#endif //#ifndef EFC_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/flash/flashd.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/flash/flashd.c deleted file mode 100644 index c0e669132..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/flash/flashd.c +++ /dev/null @@ -1,494 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup flashd_module Flash Memory Interface - * The flash driver manages the programming, erasing, locking and unlocking sequences - * with dedicated commands. - * - * To implement flash programing operation, the user has to follow these few steps : - *
    - *
  • Configue flash wait states to initializes the flash.
  • - *
  • Checks whether a region to be programmed is locked.
  • - *
  • Unlocks the user region to be programmed if the region have locked before.
  • - *
  • Erases the user page before program (optional).
  • - *
  • Writes the user page from the page buffer.
  • - *
  • Locks the region of programmed area if any.
  • - *
- * - * Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption. - * A check of this validity and padding for 32-bit alignment should be done in write algorithm. - - * Lock/unlock range associated with the user address range is automatically translated. - * - * This security bit can be enabled through the command "Set General Purpose NVM Bit 0". - * - * A 128-bit factory programmed unique ID could be read to serve several purposes. - * - * The driver accesses the flash memory by calling the lowlevel module provided in \ref efc_module. - * For more accurate information, please look at the EEFC section of the Datasheet. - * - * Related files :\n - * \ref flashd.c\n - * \ref flashd.h.\n - * \ref efc.c\n - * \ref efc.h.\n -*/ -/*@{*/ -/*@}*/ - - -/** - * \file - * - * The flash driver provides the unified interface for flash program operations. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include "flashd.h" -#include - -#include -#include -#include -#include - -#include - - -/*---------------------------------------------------------------------------- - * Local functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Computes the lock range associated with the given address range. - * - * \param start Start address of lock range. - * \param end End address of lock range. - * \param pActualStart Actual start address of lock range. - * \param pActualEnd Actual end address of lock range. - */ -static void ComputeLockRange( - uint32_t start, - uint32_t end, - uint32_t *pActualStart, - uint32_t *pActualEnd) -{ - Efc *pStartEfc, *pEndEfc; - uint16_t startPage, endPage; - uint16_t numPagesInRegion; - uint16_t actualStartPage, actualEndPage; - - // Convert start and end address in page numbers - EFC_TranslateAddress(&pStartEfc, start, &startPage, 0); - EFC_TranslateAddress(&pEndEfc, end, &endPage, 0); - - // Find out the first page of the first region to lock - numPagesInRegion = AT91C_IFLASH_LOCK_REGION_SIZE / AT91C_IFLASH_PAGE_SIZE; - actualStartPage = startPage - (startPage % numPagesInRegion); - actualEndPage = endPage; - if ((endPage % numPagesInRegion) != 0) { - - actualEndPage += numPagesInRegion - (endPage % numPagesInRegion); - } - // Store actual page numbers - EFC_ComputeAddress(pStartEfc, actualStartPage, 0, pActualStart); - EFC_ComputeAddress(pEndEfc, actualEndPage, 0, pActualEnd); - TRACE_DEBUG("Actual lock range is 0x%06X - 0x%06X\n\r", *pActualStart, *pActualEnd); -} - - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Initializes the flash driver. - * - * \param mck Master clock frequency in Hz. - */ - -void FLASHD_Initialize(uint32_t mck) -{ - EFC_DisableFrdyIt(EFC); - if ((mck/1000000) >= 64) { - EFC_SetWaitState(EFC, 2); - } - else if ((mck/1000000) >= 50) { - EFC_SetWaitState(EFC, 1); - } - else { - EFC_SetWaitState(EFC, 0); - } -} - -/** - * \brief Erases the entire flash. - * - * \param address Flash start address. - * \return 0 if successful; otherwise returns an error code. - */ -uint8_t FLASHD_Erase(uint32_t address) -{ - Efc *pEfc; - uint16_t page; - uint16_t offset; - uint8_t error; - SANITY_CHECK((address >=AT91C_IFLASH) || (address <= (AT91C_IFLASH + AT91C_IFLASH_SIZE))); - // Translate write address - EFC_TranslateAddress(&pEfc, address, &page, &offset); - error = EFC_PerformCommand(pEfc, EFC_FCMD_EA, 0); - return error; -} - - -static uint8_t pPageBuffer[AT91C_IFLASH_PAGE_SIZE]; -/** - * \brief Writes a data buffer in the internal flash - * - * \note This function works in polling mode, and thus only returns when the - * data has been effectively written. - * \param address Write address. - * \param pBuffer Data buffer. - * \param size Size of data buffer in bytes. - * \return 0 if successful, otherwise returns an error code. - */ -uint8_t FLASHD_Write( - uint32_t address, - const void *pBuffer, - uint32_t size) -{ - Efc *pEfc; - uint16_t page; - uint16_t offset; - uint32_t writeSize; - uint32_t pageAddress; - uint16_t padding; - uint8_t error; - - uint32_t sizeTmp; - uint32_t *pAlignedDestination; - uint32_t *pAlignedSource; - - SANITY_CHECK(pBuffer); - SANITY_CHECK(address >=AT91C_IFLASH); - SANITY_CHECK((address + size) <= (AT91C_IFLASH + AT91C_IFLASH_SIZE)); - // Translate write address - EFC_TranslateAddress(&pEfc, address, &page, &offset); - - // Write all pages - while (size > 0) { - - // Copy data in temporary buffer to avoid alignment problems - writeSize = min(AT91C_IFLASH_PAGE_SIZE - offset, size); - EFC_ComputeAddress(pEfc, page, 0, &pageAddress); - padding = AT91C_IFLASH_PAGE_SIZE - offset - writeSize; - - // Pre-buffer data - memcpy(pPageBuffer, (void *) pageAddress, offset); - - // Buffer data - memcpy(pPageBuffer + offset, pBuffer, writeSize); - - // Post-buffer data - memcpy(pPageBuffer + offset + writeSize, (void *) (pageAddress + offset + writeSize), padding); - - // Write page - // Writing 8-bit and 16-bit data is not allowed - // and may lead to unpredictable data corruption - pAlignedDestination = (uint32_t*)pageAddress; - pAlignedSource = (uint32_t*)pPageBuffer; - sizeTmp = AT91C_IFLASH_PAGE_SIZE; - while (sizeTmp >= 4) { - - *pAlignedDestination++ = *pAlignedSource++; - sizeTmp -= 4; - } - - // Send writing command - error = EFC_PerformCommand(pEfc, EFC_FCMD_EWP, page); - if (error) { - - return error; - } - - // Progression - address += AT91C_IFLASH_PAGE_SIZE; - pBuffer = (void *) ((uint32_t) pBuffer + writeSize); - size -= writeSize; - page++; - offset = 0; - } - - return 0; -} -/** - * \brief Locks all the regions in the given address range. The actual lock range is - * reported through two output parameters. - * \param address Start address of lock range. - * \param end End address of lock range. - * \param pActualStart Start address of the actual lock range (optional). - * \param pActualEnd End address of the actual lock range (optional). - * \return 0 if successful, otherwise returns an error code. - */ -uint8_t FLASHD_Lock( - uint32_t start, - uint32_t end, - uint32_t *pActualStart, - uint32_t *pActualEnd) -{ - Efc *pEfc; - uint32_t actualStart, actualEnd; - uint16_t startPage, endPage; - uint8_t error; - uint16_t numPagesInRegion = AT91C_IFLASH_LOCK_REGION_SIZE / AT91C_IFLASH_PAGE_SIZE; - - // Compute actual lock range and store it - ComputeLockRange(start, end, &actualStart, &actualEnd); - if (pActualStart) { - - *pActualStart = actualStart; - } - if (pActualEnd) { - - *pActualEnd = actualEnd; - } - - // Compute page numbers - EFC_TranslateAddress(&pEfc, actualStart, &startPage, 0); - EFC_TranslateAddress(0, actualEnd, &endPage, 0); - - // Lock all pages - while (startPage < endPage) { - - error = EFC_PerformCommand(pEfc, EFC_FCMD_SLB, startPage); - if (error) { - - return error; - } - startPage += numPagesInRegion; - } - - return 0; -} - -/** - * \brief Unlocks all the regions in the given address range. The actual unlock range is - * reported through two output parameters. - * \param address Start address of unlock range. - * \param end End address of unlock range. - * \param pActualStart Start address of the actual unlock range (optional). - * \param pActualEnd End address of the actual unlock range (optional). - * \return 0 if successful, otherwise returns an error code. - */ -uint8_t FLASHD_Unlock( - uint32_t start, - uint32_t end, - uint32_t *pActualStart, - uint32_t *pActualEnd) -{ - Efc *pEfc; - uint32_t actualStart, actualEnd; - uint16_t startPage, endPage; - uint8_t error; - uint16_t numPagesInRegion = AT91C_IFLASH_LOCK_REGION_SIZE / AT91C_IFLASH_PAGE_SIZE; - - // Compute actual unlock range and store it - ComputeLockRange(start, end, &actualStart, &actualEnd); - if (pActualStart) { - - *pActualStart = actualStart; - } - if (pActualEnd) { - - *pActualEnd = actualEnd; - } - - // Compute page numbers - EFC_TranslateAddress(&pEfc, actualStart, &startPage, 0); - EFC_TranslateAddress(0, actualEnd, &endPage, 0); - - // Unlock all pages - while (startPage < endPage) { - - error = EFC_PerformCommand(pEfc, EFC_FCMD_CLB, startPage); - if (error) { - - return error; - } - startPage += numPagesInRegion; - } - return 0; -} - -/** - * \brief Returns the number of locked regions inside the given address range. - * - * \param address Start address of range - * \param end End address of range. - */ -uint8_t FLASHD_IsLocked(uint32_t start, uint32_t end) -{ - Efc *pEfc; - uint16_t startPage, endPage; - uint8_t startRegion, endRegion; - uint32_t numPagesInRegion; - uint32_t status; - uint8_t error; - uint32_t numLockedRegions = 0; - - SANITY_CHECK(end >= start); - SANITY_CHECK((start >=AT91C_IFLASH) && (end <= AT91C_IFLASH + AT91C_IFLASH_SIZE)); - - // Compute page numbers - EFC_TranslateAddress(&pEfc, start, &startPage, 0); - EFC_TranslateAddress(0, end, &endPage, 0); - - // Compute region numbers - numPagesInRegion = AT91C_IFLASH_LOCK_REGION_SIZE / AT91C_IFLASH_PAGE_SIZE; - startRegion = startPage / numPagesInRegion; - endRegion = endPage / numPagesInRegion; - if ((endPage % numPagesInRegion) != 0) { - - endRegion++; - } - - // Retrieve lock status - error = EFC_PerformCommand(pEfc, EFC_FCMD_GLB, 0); - ASSERT(!error, "-F- Error while trying to fetch lock bits status (0x%02X)\n\r", error); - status = EFC_GetResult(pEfc); - - // Check status of each involved region - while (startRegion < endRegion) { - - if ((status & (1 << startRegion)) != 0) { - - numLockedRegions++; - } - startRegion++; - } - - return numLockedRegions; -} - -/** - * \brief Check if the given GPNVM bit is set or not. - * - * \param gpnvm GPNVM bit index. - * \returns 1 if the given GPNVM bit is currently set; otherwise returns 0. - */ -uint8_t FLASHD_IsGPNVMSet(uint8_t gpnvm) -{ - uint8_t error; - uint32_t status; - - SANITY_CHECK(gpnvm < 2); - - // Get GPNVMs status - error = EFC_PerformCommand(EFC, EFC_FCMD_GFB, 0); - ASSERT(!error, "-F- Error while trying to fetch GPNVMs status (0x%02X)\n\r", error); - status = EFC_GetResult(EFC); - - // Check if GPNVM is set - if ((status & (1 << gpnvm)) != 0) { - return 1; - } - else { - return 0; - } -} -/** - * \brief Sets the selected GPNVM bit. - * - * \param gpnvm GPNVM bit index. - * \returns 0 if successful; otherwise returns an error code. - */ -uint8_t FLASHD_SetGPNVM(uint8_t gpnvm) -{ - SANITY_CHECK(gpnvm < 2); - - if (!FLASHD_IsGPNVMSet(gpnvm)) { - - return EFC_PerformCommand(EFC, EFC_FCMD_SFB, gpnvm); - } - else { - - return 0; - } -} - -/** - * \brief Clears the selected GPNVM bit. - * - * \param gpnvm GPNVM bit index. - * \returns 0 if successful; otherwise returns an error code. - */ -uint8_t FLASHD_ClearGPNVM(uint8_t gpnvm) -{ - SANITY_CHECK(gpnvm < 2); - - if (FLASHD_IsGPNVMSet(gpnvm)) { - - return EFC_PerformCommand(EFC, EFC_FCMD_CFB, gpnvm); - } - else { - - return 0; - } -} -/** - * \brief Read the unique ID. - * - * \param uniqueID pointer on a 4bytes char containing the unique ID value. - * \returns 0 if successful; otherwise returns an error code. - */ -uint8_t FLASHD_ReadUniqueID (uint32_t * uniqueID) -{ - uint8_t error; - SANITY_CHECK(uniqueID != NULL); - - uniqueID[0] = 0; - uniqueID[1] = 0; - uniqueID[2] = 0; - uniqueID[3] = 0; - - EFC_StartCommand(EFC, EFC_FCMD_STUI, 0); - - uniqueID[0] = *(uint32_t *)AT91C_IFLASH; - uniqueID[1] = *(uint32_t *)(AT91C_IFLASH + 4); - uniqueID[2] = *(uint32_t *)(AT91C_IFLASH + 8); - uniqueID[3] = *(uint32_t *)(AT91C_IFLASH + 12); - - error = EFC_PerformCommand(EFC, EFC_FCMD_SPUI, 0); - if (error) return error; - - return 0; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/flash/flashd.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/flash/flashd.h deleted file mode 100644 index 14b765b2f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/flash/flashd.h +++ /dev/null @@ -1,84 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- -*/ - -/** - * \file - * - * The flash driver provides the unified interface for flash program operations. - * - */ - -#ifndef FLASHD_H -#define FLASHD_H - -#include - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void FLASHD_Initialize(uint32_t mck); - -extern uint8_t FLASHD_Erase(uint32_t address); - -extern uint8_t FLASHD_Write( - uint32_t address, - const void *pBuffer, - uint32_t size); - -extern uint8_t FLASHD_Lock( - uint32_t start, - uint32_t end, - uint32_t *pActualStart, - uint32_t *pActualEnd); - -extern uint8_t FLASHD_Unlock( - uint32_t start, - uint32_t end, - uint32_t *pActualStart, - uint32_t *pActualEnd); - -extern uint8_t FLASHD_IsLocked( - uint32_t start, - uint32_t end); - -extern uint8_t FLASHD_SetGPNVM(uint8_t gpnvm); - -extern uint8_t FLASHD_ClearGPNVM(uint8_t gpnvm); - -extern uint8_t FLASHD_IsGPNVMSet(uint8_t gpnvm); - -#define FLASHD_IsSecurityBitSet() FLASHD_IsGPNVMSet(0) - -#define FLASHD_SetSecurityBit() FLASHD_SetGPNVM(0) - -extern uint8_t FLASHD_ReadUniqueID(uint32_t * uniqueID); - -#endif //#ifndef FLASHD_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/color.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/color.h deleted file mode 100644 index 3258b82cc..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/color.h +++ /dev/null @@ -1,85 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef COLOR_H -#define COLOR_H - -/** - * \file - * - * RGB 24-bits color table definition. - * - */ - -/* - * RGB 24 Bpp - * RGB 888 - * R7R6R5R4 R3R2R1R0 G7G6G5G4 G3G2G1G0 B7B6B5B4 B3B2B1B0 - */ -#define COLOR_BLACK 0x000000 -#define COLOR_WHITE 0xFFFFFF - -#define COLOR_BLUE 0x0000FF -#define COLOR_GREEN 0x00FF00 -#define COLOR_RED 0xFF0000 - -#define COLOR_NAVY 0x000080 -#define COLOR_DARKBLUE 0x00008B -#define COLOR_DARKGREEN 0x006400 -#define COLOR_DARKCYAN 0x008B8B -#define COLOR_CYAN 0x00FFFF -#define COLOR_TURQUOISE 0x40E0D0 -#define COLOR_INDIGO 0x4B0082 -#define COLOR_DARKRED 0x800000 -#define COLOR_OLIVE 0x808000 -#define COLOR_GRAY 0x808080 -#define COLOR_SKYBLUE 0x87CEEB -#define COLOR_BLUEVIOLET 0x8A2BE2 -#define COLOR_LIGHTGREEN 0x90EE90 -#define COLOR_DARKVIOLET 0x9400D3 -#define COLOR_YELLOWGREEN 0x9ACD32 -#define COLOR_BROWN 0xA52A2A -#define COLOR_DARKGRAY 0xA9A9A9 -#define COLOR_SIENNA 0xA0522D -#define COLOR_LIGHTBLUE 0xADD8E6 -#define COLOR_GREENYELLOW 0xADFF2F -#define COLOR_SILVER 0xC0C0C0 -#define COLOR_LIGHTGREY 0xD3D3D3 -#define COLOR_LIGHTCYAN 0xE0FFFF -#define COLOR_VIOLET 0xEE82EE -#define COLOR_AZUR 0xF0FFFF -#define COLOR_BEIGE 0xF5F5DC -#define COLOR_MAGENTA 0xFF00FF -#define COLOR_TOMATO 0xFF6347 -#define COLOR_GOLD 0xFFD700 -#define COLOR_ORANGE 0xFFA500 -#define COLOR_SNOW 0xFFFAFA -#define COLOR_YELLOW 0xFFFF00 - -#endif /* #define COLOR_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/draw.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/draw.c deleted file mode 100644 index 4e1975be0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/draw.c +++ /dev/null @@ -1,333 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of draw function on LCD, Include draw text, image - * and basic shapes (line, rectangle, circle). - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include - -#include "draw.h" -#include "font.h" -#include -#include -#include - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Fills the given LCD buffer with a particular color. - * - * \param color Fill color. - */ -void LCDD_Fill(uint32_t color) -{ - uint32_t i; - - LCD_SetCursor(0, 0); - LCD_WriteRAM_Prepare(); - for (i = 0; i < (BOARD_LCD_WIDTH * BOARD_LCD_HEIGHT); i++) { - - LCD_WriteRAM(color); - } -} - -/** - * \brief Draw a pixel on LCD of given color. - * - * \param x X-coordinate of pixel. - * \param y Y-coordinate of pixel. - * \param color Pixel color. - */ -void LCDD_DrawPixel( - uint32_t x, - uint32_t y, - uint32_t color) -{ - LCD_SetCursor(x, y); - LCD_WriteRAM_Prepare(); - LCD_WriteRAM(color); -} - -/** - * \brief Read a pixel from LCD. - * - * \param x X-coordinate of pixel. - * \param y Y-coordinate of pixel. - * - * \return color Readed pixel color. - */ -uint32_t LCDD_ReadPixel( - uint32_t x, - uint32_t y) -{ - uint32_t color; - - LCD_SetCursor(x, y); - LCD_ReadRAM_Prepare(); - color = LCD_ReadRAM(); - - return color; -} - -/* - * \brief Draw a line on LCD, horizontal and vertical line are supported. - * - * \param x X-coordinate of line start. - * \param y Y-coordinate of line start. - * \param length line length. - * \param direction line direction: 0 - horizontal, 1 - vertical. - * \param color Pixel color. - */ -void LCDD_DrawLine( - uint32_t x, - uint32_t y, - uint32_t length, - uint32_t direction, - uint32_t color) -{ - uint32_t i = 0; - - LCD_SetCursor(x, y); - - if(direction == DIRECTION_HLINE) { - LCD_WriteRAM_Prepare(); - for(i = 0; i < length; i++) { - LCD_WriteRAM(color); - } - } - else { - for(i = 0; i < length; i++) { - LCD_WriteRAM_Prepare(); - LCD_WriteRAM(color); - y++; - LCD_SetCursor(x, y); - } - } -} - -/* - * \brief Draws a rectangle on LCD, at the given coordinates. - * - * \param x X-coordinate of upper-left rectangle corner. - * \param y Y-coordinate of upper-left rectangle corner. - * \param width Rectangle width in pixels. - * \param height Rectangle height in pixels. - * \param color Rectangle color. - */ -void LCDD_DrawRectangle( - uint32_t x, - uint32_t y, - uint32_t width, - uint32_t height, - uint32_t color) -{ - LCDD_DrawLine(x, y, width, DIRECTION_HLINE, color); - LCDD_DrawLine(x, (y + height), width, DIRECTION_HLINE, color); - - LCDD_DrawLine(x, y, height, DIRECTION_VLINE, color); - LCDD_DrawLine((x + width), y, height, DIRECTION_VLINE, color); -} - -/* - * \brief Draws a rectangle with fill inside on LCD, at the given coordinates. - * - * \param x X-coordinate of upper-left rectangle corner. - * \param y Y-coordinate of upper-left rectangle corner. - * \param width Rectangle width in pixels. - * \param height Rectangle height in pixels. - * \param color Rectangle color. - */ -void LCDD_DrawRectangleWithFill( - uint32_t x, - uint32_t y, - uint32_t width, - uint32_t height, - uint32_t color) -{ - uint32_t i; - - for (i = 0; i < height; i++) { - LCDD_DrawLine(x, y+i, width, DIRECTION_HLINE, color); - } -} - -/** - * \brief Draws a circle on LCD, at the given coordinates. - * - * \param x X-coordinate of circle center. - * \param y Y-coordinate of circle center. - * \param r circle radius. - * \param color circle color. - */ -void LCDD_DrawCircle( - uint32_t x, - uint32_t y, - uint32_t r, - uint32_t color) -{ - signed int d; /* Decision Variable */ - uint32_t curX; /* Current X Value */ - uint32_t curY; /* Current Y Value */ - - d = 3 - (r << 1); - curX = 0; - curY = r; - - while (curX <= curY) - { - LCDD_DrawPixel(x + curX, y + curY, color); - LCDD_DrawPixel(x + curX, y - curY, color); - LCDD_DrawPixel(x - curX, y + curY, color); - LCDD_DrawPixel(x - curX, y - curY, color); - LCDD_DrawPixel(x + curY, y + curX, color); - LCDD_DrawPixel(x + curY, y - curX, color); - LCDD_DrawPixel(x - curY, y + curX, color); - LCDD_DrawPixel(x - curY, y - curX, color); - - if (d < 0) { - d += (curX << 2) + 6; - } - else { - d += ((curX - curY) << 2) + 10; - curY--; - } - curX++; - } -} - -/** - * \brief Draws a string inside a LCD buffer, at the given coordinates. Line breaks - * will be honored. - * - * \param x X-coordinate of string top-left corner. - * \param y Y-coordinate of string top-left corner. - * \param pString String to display. - * \param color String color. - */ -void LCDD_DrawString( - uint32_t x, - uint32_t y, - const uint8_t *pString, - uint32_t color) -{ - unsigned xorg = x; - - while (*pString != 0) { - if (*pString == '\n') { - - y += gFont.height + 2; - x = xorg; - } - else { - - LCDD_DrawChar(x, y, *pString, color); - x += gFont.width + 2; - } - pString++; - } -} - -/** - * \brief Returns the width & height in pixels that a string will occupy on the screen - * if drawn using LCDD_DrawString. - * - * \param pString String. - * \param pWidth Pointer for storing the string width (optional). - * \param pHeight Pointer for storing the string height (optional). - * - * \return String width in pixels. - */ -void LCDD_GetStringSize( - const uint8_t *pString, - uint32_t *pWidth, - uint32_t *pHeight) -{ - uint32_t width = 0; - uint32_t height = gFont.height; - - while (*pString != 0) { - - if (*pString == '\n') { - - height += gFont.height + 2; - } - else { - - width += gFont.width + 2; - } - pString++; - } - - if (width > 0) width -= 2; - - if (pWidth) *pWidth = width; - if (pHeight) *pHeight = height; -} - -/* - * \brief Draw a raw image at given position on LCD. - * - * \param x X-coordinate of image start. - * \param y Y-coordinate of image start. - * \param pImage Image buffer. - * \param width Image width. - * \param height Image height. - */ -void LCDD_DrawImage( - uint32_t x, - uint32_t y, - const uint8_t *pImage, - uint32_t width, - uint32_t height) -{ - uint32_t row, col; - - for(row = y; row < (y + height); row++) { - LCD_SetCursor(x, row); - LCD_WriteRAM_Prepare(); - for(col = x; col < (x + width); col++) { - LCD_D() = *pImage++; - LCD_D() = *pImage++; - LCD_D() = *pImage++; - } - } -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/draw.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/draw.h deleted file mode 100644 index e7fb7a57f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/draw.h +++ /dev/null @@ -1,114 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - - /** - * \file - * - * Interface for draw function on LCD. - * - */ - -#ifndef DRAW_H -#define DRAW_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -/** Horizontal direction line definition */ -#define DIRECTION_HLINE 0 -/** Vertical direction line definition */ -#define DIRECTION_VLINE 1 - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ -extern void LCDD_Fill(uint32_t color); - -extern void LCDD_DrawPixel( - uint32_t x, - uint32_t y, - uint32_t c); - -extern uint32_t LCDD_ReadPixel( - uint32_t x, - uint32_t y); - -extern void LCDD_DrawLine( - uint32_t x, - uint32_t y, - uint32_t length, - uint32_t direction, - uint32_t color); - -extern void LCDD_DrawRectangle( - uint32_t x, - uint32_t y, - uint32_t width, - uint32_t height, - uint32_t color); - -extern void LCDD_DrawRectangleWithFill( - uint32_t x, - uint32_t y, - uint32_t width, - uint32_t height, - uint32_t color); - -extern void LCDD_DrawCircle( - uint32_t x, - uint32_t y, - uint32_t r, - uint32_t color); - -extern void LCDD_DrawString( - uint32_t x, - uint32_t y, - const uint8_t *pString, - uint32_t color); - -extern void LCDD_GetStringSize( - const uint8_t *pString, - uint32_t *pWidth, - uint32_t *pHeight); - -extern void LCDD_DrawImage( - uint32_t x, - uint32_t y, - const uint8_t *pImage, - uint32_t width, - uint32_t height); - -#endif /* #ifndef DRAW_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font.c deleted file mode 100644 index 4a1612980..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font.c +++ /dev/null @@ -1,95 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of draw font on LCD. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include "color.h" -#include "font.h" -#include "draw.h" -#include "font10x14.h" -#include - -/*---------------------------------------------------------------------------- - * Local variables - *----------------------------------------------------------------------------*/ - -/** Global variable describing the font being instancied. */ -const Font gFont = {10, 14}; - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Draws an ASCII character on LCD. - * - * \param x X-coordinate of character upper-left corner. - * \param y Y-coordinate of character upper-left corner. - * \param c Character to output. - * \param color Character color. -*/ -void LCDD_DrawChar( - uint32_t x, - uint32_t y, - uint8_t c, - uint32_t color) -{ - uint32_t row, col; - - SANITY_CHECK((c >= 0x20) && (c <= 0x7F)); - - for (col = 0; col < 10; col++) { - - for (row = 0; row < 8; row++) { - - if ((pCharset10x14[((c - 0x20) * 20) + col * 2] >> (7 - row)) & 0x1) { - - LCDD_DrawPixel(x+col, y+row, color); - } - } - for (row = 0; row < 6; row++) { - - if ((pCharset10x14[((c - 0x20) * 20) + col * 2 + 1] >> (7 - row)) & 0x1) { - - LCDD_DrawPixel(x+col, y+row+8, color); - } - } - } -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font.h deleted file mode 100644 index d46cf6c45..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font.h +++ /dev/null @@ -1,92 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for draw font on LCD. - * - */ - -/** - * - * \section Purpose - * - * The font.h files declares a font structure and a LCDD_DrawChar function - * that must be implemented by a font definition file to be used with the - * LCDD_DrawString method of draw.h. - * - * The font10x14.c implements the necessary variable and function for a 10x14 - * font. - * - * \section Usage - * - * -# Declare a gFont global variable with the necessary Font information. - * -# Implement an LCDD_DrawChar function which displays the specified - * character on the LCD. - * -# Use the LCDD_DrawString method defined in draw.h to display a complete - * string. - */ - -#ifndef FONT_H -#define FONT_H - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - - -/** Describes the font (width, height, supported characters, etc.) used by - * the LCD driver draw API. - */ -typedef struct _Font { - /* Font width in pixels. */ - uint8_t width; - /* Font height in pixels. */ - uint8_t height; -} Font; - -/*---------------------------------------------------------------------------- - * Variables - *----------------------------------------------------------------------------*/ - -/** Global variable describing the font being instancied. */ -extern const Font gFont; - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void LCDD_DrawChar( - uint32_t x, - uint32_t y, - uint8_t c, - uint32_t color); - -#endif /* #ifndef FONT_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font10x14.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font10x14.h deleted file mode 100644 index 2ce2589ea..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/font10x14.h +++ /dev/null @@ -1,236 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - - /** - * \file - * - * Font 10x14 table definition. - * - */ - -#ifndef LCD_FONT_10x14_H -#define LCD_FONT_10x14_H - -/** Char set of font 10x14 */ -const uint8_t pCharset10x14[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xCC, - 0xFF, 0xCC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00, - 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x0C, 0xC0, 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0, - 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0, - 0x0C, 0x60, 0x1E, 0x70, 0x3F, 0x30, 0x33, 0x30, 0xFF, 0xFC, - 0xFF, 0xFC, 0x33, 0x30, 0x33, 0xF0, 0x39, 0xE0, 0x18, 0xC0, - 0x60, 0x00, 0xF0, 0x0C, 0xF0, 0x3C, 0x60, 0xF0, 0x03, 0xC0, - 0x0F, 0x00, 0x3C, 0x18, 0xF0, 0x3C, 0xC0, 0x3C, 0x00, 0x18, - 0x3C, 0xF0, 0x7F, 0xF8, 0xC3, 0x1C, 0xC7, 0x8C, 0xCF, 0xCC, - 0xDC, 0xEC, 0x78, 0x78, 0x30, 0x30, 0x00, 0xFC, 0x00, 0xCC, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0xEC, 0x00, - 0xF8, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x0F, 0xC0, 0x3F, 0xF0, 0x78, 0x78, - 0x60, 0x18, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0x60, 0x18, - 0x78, 0x78, 0x3F, 0xF0, 0x0F, 0xC0, 0x00, 0x00, 0x00, 0x00, - 0x0C, 0x60, 0x0E, 0xE0, 0x07, 0xC0, 0x03, 0x80, 0x3F, 0xF8, - 0x3F, 0xF8, 0x03, 0x80, 0x07, 0xC0, 0x0E, 0xE0, 0x0C, 0x60, - 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x3F, 0xF0, - 0x3F, 0xF0, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, - 0x00, 0x44, 0x00, 0xEC, 0x00, 0xF8, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, - 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, - 0x00, 0x18, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x18, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x0C, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0, - 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x00, 0xC0, 0x00, 0x00, 0x00, - 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0xFC, 0xC1, 0xCC, 0xC3, 0x8C, - 0xC7, 0x0C, 0xCE, 0x0C, 0xFC, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0, - 0x00, 0x00, 0x00, 0x00, 0x30, 0x0C, 0x70, 0x0C, 0xFF, 0xFC, - 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, - 0x30, 0x0C, 0x70, 0x1C, 0xE0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC, - 0xC1, 0xCC, 0xC3, 0x8C, 0xE7, 0x0C, 0x7E, 0x0C, 0x3C, 0x0C, - 0x30, 0x30, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, - 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x7F, 0xF8, 0x3C, 0xF0, - 0x03, 0xC0, 0x07, 0xC0, 0x0E, 0xC0, 0x1C, 0xC0, 0x38, 0xC0, - 0x70, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xC0, 0x00, 0xC0, - 0xFC, 0x30, 0xFC, 0x38, 0xCC, 0x1C, 0xCC, 0x0C, 0xCC, 0x0C, - 0xCC, 0x0C, 0xCC, 0x0C, 0xCE, 0x1C, 0xC7, 0xF8, 0xC3, 0xF0, - 0x3F, 0xF0, 0x7F, 0xF8, 0xE3, 0x1C, 0xC3, 0x0C, 0xC3, 0x0C, - 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x9C, 0x71, 0xF8, 0x30, 0xF0, - 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC3, 0xFC, - 0xC7, 0xFC, 0xCE, 0x00, 0xDC, 0x00, 0xF8, 0x00, 0xF0, 0x00, - 0x3C, 0xF0, 0x7F, 0xF8, 0xE7, 0x9C, 0xC3, 0x0C, 0xC3, 0x0C, - 0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0, - 0x3C, 0x00, 0x7E, 0x00, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x1C, - 0xC3, 0x38, 0xC3, 0x70, 0xE7, 0xE0, 0x7F, 0xC0, 0x3F, 0x80, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x60, 0x3C, 0xF0, - 0x3C, 0xF0, 0x18, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x44, 0x3C, 0xEC, - 0x3C, 0xF8, 0x18, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0, - 0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0x00, 0x00, - 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, - 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, - 0x00, 0x00, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x38, 0x70, - 0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00, - 0x30, 0x00, 0x70, 0x00, 0xE0, 0x00, 0xC0, 0x00, 0xC1, 0xEC, - 0xC3, 0xEC, 0xC3, 0x00, 0xE6, 0x00, 0x7E, 0x00, 0x3C, 0x00, - 0x30, 0xF0, 0x71, 0xF8, 0xE3, 0x9C, 0xC3, 0x0C, 0xC3, 0xFC, - 0xC3, 0xFC, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0, - 0x3F, 0xFC, 0x7F, 0xFC, 0xE0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, - 0xC0, 0xC0, 0xC0, 0xC0, 0xE0, 0xC0, 0x7F, 0xFC, 0x3F, 0xFC, - 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, - 0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0, - 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, - 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x30, 0x30, - 0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, - 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0, - 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, - 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, - 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00, - 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00, 0xC0, 0x00, 0xC0, 0x00, - 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, - 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x73, 0xF8, 0x33, 0xF0, - 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, - 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, - 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC, - 0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x30, 0x00, 0x38, 0xC0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, - 0xC0, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0, 0xC0, 0x00, 0xC0, 0x00, - 0xFF, 0xFC, 0xFF, 0xFC, 0x07, 0x80, 0x07, 0x80, 0x0F, 0xC0, - 0x1C, 0xE0, 0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, - 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, - 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, - 0xFF, 0xFC, 0xFF, 0xFC, 0x70, 0x00, 0x38, 0x00, 0x1F, 0x00, - 0x1F, 0x00, 0x38, 0x00, 0x70, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, - 0xFF, 0xFC, 0xFF, 0xFC, 0x1C, 0x00, 0x0E, 0x00, 0x07, 0x00, - 0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0xFF, 0xFC, 0xFF, 0xFC, - 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, - 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0, - 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00, - 0xC3, 0x00, 0xC3, 0x00, 0xE7, 0x00, 0x7E, 0x00, 0x3C, 0x00, - 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0xCC, - 0xC0, 0xEC, 0xC0, 0x7C, 0xE0, 0x38, 0x7F, 0xFC, 0x3F, 0xEC, - 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x80, 0xC3, 0x80, - 0xC3, 0xC0, 0xC3, 0xC0, 0xE7, 0x70, 0x7E, 0x3C, 0x3C, 0x1C, - 0x3C, 0x18, 0x7E, 0x1C, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, - 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x9C, 0xE1, 0xF8, 0x60, 0xF0, - 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xFF, 0xFC, - 0xFF, 0xFC, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, - 0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C, - 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0, - 0xFF, 0xC0, 0xFF, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, - 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0xFF, 0xE0, 0xFF, 0xC0, - 0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x3C, 0x00, 0xF8, - 0x00, 0xF8, 0x00, 0x3C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0, - 0xF0, 0x3C, 0xF8, 0x7C, 0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80, - 0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0, 0xF8, 0x7C, 0xF0, 0x3C, - 0xFC, 0x00, 0xFE, 0x00, 0x07, 0x00, 0x03, 0x80, 0x01, 0xFC, - 0x01, 0xFC, 0x03, 0x80, 0x07, 0x00, 0xFE, 0x00, 0xFC, 0x00, - 0xC0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC, 0xC1, 0xCC, 0xC3, 0x8C, - 0xC7, 0x0C, 0xCE, 0x0C, 0xDC, 0x0C, 0xF8, 0x0C, 0xF0, 0x0C, - 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C, - 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x30, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x03, 0x00, - 0x03, 0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x30, - 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, - 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x0C, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x00, 0xE0, 0x00, - 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C, 0x00, - 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, - 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, - 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00, - 0x38, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x30, 0x06, 0x78, 0x0E, 0xFC, 0x0C, 0xCC, 0x0C, 0xCC, - 0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xCC, 0x07, 0xFC, 0x03, 0xF8, - 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C, - 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x9C, 0x01, 0xF8, 0x00, 0xF0, - 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C, - 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0x30, - 0x00, 0xF0, 0x01, 0xF8, 0x03, 0x9C, 0x03, 0x0C, 0x03, 0x0C, - 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C, 0xFF, 0xFC, 0xFF, 0xFC, - 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0xDC, 0x0C, 0xCC, 0x0C, 0xCC, - 0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xDC, 0x07, 0xD8, 0x03, 0x90, - 0x00, 0x00, 0x03, 0x00, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x00, - 0xE3, 0x00, 0x70, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC, - 0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xDC, 0x0F, 0xF8, 0x07, 0xF0, - 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, - 0x03, 0x00, 0x03, 0x80, 0x01, 0xFC, 0x00, 0xFC, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0xFC, - 0x1B, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x30, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C, - 0x00, 0x0C, 0x00, 0x1C, 0xCF, 0xF8, 0xCF, 0xF0, 0x00, 0x00, - 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xE0, 0x01, 0xE0, - 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC, - 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, - 0x0F, 0xFC, 0x0F, 0xFC, 0x0E, 0x00, 0x07, 0x00, 0x03, 0xC0, - 0x03, 0xC0, 0x07, 0x00, 0x0E, 0x00, 0x0F, 0xFC, 0x0F, 0xFC, - 0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x00, 0x07, 0x00, 0x0E, 0x00, - 0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0xFC, 0x03, 0xFC, - 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C, - 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0xF8, 0x03, 0xF0, - 0x0F, 0xFC, 0x0F, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, - 0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00, - 0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, - 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xFC, 0x0F, 0xFC, - 0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, - 0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x03, 0x00, - 0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC, - 0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xFC, 0x0E, 0x78, 0x06, 0x30, - 0x00, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0xFF, 0xF0, 0xFF, 0xF8, - 0x0C, 0x1C, 0x0C, 0x1C, 0x0C, 0x38, 0x0C, 0x30, 0x00, 0x00, - 0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C, - 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0, - 0x0F, 0xC0, 0x0F, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, - 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x0F, 0xE0, 0x0F, 0xC0, - 0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0xF8, - 0x00, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0, - 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0xF0, 0x01, 0xE0, - 0x01, 0xE0, 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C, - 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x0C, 0x03, 0x9C, 0x01, 0xF8, - 0x01, 0xF0, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, 0x0C, 0x00, - 0x0C, 0x0C, 0x0C, 0x1C, 0x0C, 0x3C, 0x0C, 0x7C, 0x0C, 0xEC, - 0x0D, 0xCC, 0x0F, 0x8C, 0x0F, 0x0C, 0x0E, 0x0C, 0x0C, 0x0C, - 0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x3F, 0xF0, 0x7C, 0xF8, - 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, - 0x03, 0x0C, 0x03, 0x0C, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x0C, - 0xC3, 0x0C, 0xC0, 0x0C, 0xE0, 0x0C, 0x70, 0x0C, 0x30, 0x0C, - 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, - 0x7C, 0xF8, 0x3F, 0xF0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00, - 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, - 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, - 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, - 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC -}; - -#endif /* #ifdef _LCD_FONT_10x14_h */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/lcdd.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/lcdd.c deleted file mode 100644 index 1d7b158a8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/lcdd.c +++ /dev/null @@ -1,149 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of LCD driver, Include LCD initialization, - * LCD on/off and LCD backlight control. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include "lcdd.h" -#include -#include -#include -#include - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Initializes the LCD controller. - * Configure SMC to access LCD controller at 64MHz MCK. - */ -void LCDD_Initialize(void) -{ - const Pin pPins[] = {BOARD_LCD_PINS}; - Smc *pSmc = SMC; - - /* Enable pins */ - PIO_Configure(pPins, PIO_LISTSIZE(pPins)); - - /* Enable peripheral clock */ - PMC_EnablePeripheral(ID_SMC); - - /* EBI SMC Configuration */ - pSmc->SMC_CS_NUMBER[1].SMC_SETUP = 0 - | ((2 << 0) & SMC_SETUP1_NWE_SETUP) - | ((2 << 8) & SMC_SETUP1_NCS_WR_SETUP) - | ((2 << 16) & SMC_SETUP1_NRD_SETUP) - | ((2 << 24) & SMC_SETUP1_NCS_RD_SETUP) - ; - - pSmc->SMC_CS_NUMBER[1].SMC_PULSE = 0 - | ((4 << 0) & SMC_PULSE1_NWE_PULSE) - | ((4 << 8) & SMC_PULSE1_NCS_WR_PULSE) - | ((10 << 16) & SMC_PULSE1_NRD_PULSE) - | ((10 << 24) & SMC_PULSE1_NCS_RD_PULSE) - ; - - pSmc->SMC_CS_NUMBER[1].SMC_CYCLE = 0 - | ((10 << 0) & SMC_CYCLE1_NWE_CYCLE) - | ((22 << 16) & SMC_CYCLE1_NRD_CYCLE) - ; - - pSmc->SMC_CS_NUMBER[1].SMC_MODE = 0 - | (SMC_MODE1_READ_MODE) - | (SMC_MODE1_WRITE_MODE) - | (0) /* Set 8 bit width. TODO: replace with definition in device header file */ - ; - - /* Initialize LCD controller */ - LCD_Initialize(); - - /* Set LCD backlight */ - LCDD_SetBacklight(2); -} - -/** - * \brief Turn on the LCD. - */ -void LCDD_On(void) -{ - LCD_On(); -} - -/** - * \brief Turn off the LCD. - */ -void LCDD_Off(void) -{ - LCD_Off(); -} - -/** - * \brief Set the backlight of the LCD. - * - * \param level Backlight brightness level [1..16], 1 means maximum brightness. - */ -void LCDD_SetBacklight (uint32_t level) -{ - uint32_t i; - const Pin pPins[] = {BOARD_BACKLIGHT_PIN}; - - /* Ensure valid level */ - level = (level < 1) ? 1 : level; - level = (level > 16) ? 16 : level; - - /* Enable pins */ - PIO_Configure(pPins, PIO_LISTSIZE(pPins)); - - /* Switch off backlight */ - PIO_Clear(pPins); - i = 600 * (BOARD_MCK / 1000000); /* wait for at least 500us */ - while(i--); - - /* Set new backlight level */ - for (i = 0; i < level; i++) { - PIO_Clear(pPins); - PIO_Clear(pPins); - PIO_Clear(pPins); - - PIO_Set(pPins); - PIO_Set(pPins); - PIO_Set(pPins); - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/lcdd.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/lcdd.h deleted file mode 100644 index 8ba19f05b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/lcd/lcdd.h +++ /dev/null @@ -1,52 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for LCD driver. - * - */ - -#ifndef LCDD_H -#define LCDD_H - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void LCDD_Initialize(void); - -extern void LCDD_On(void); - -extern void LCDD_Off(void); - -extern void LCDD_SetBacklight (uint32_t step); - -#endif /* #ifndef LCDD_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio.c deleted file mode 100644 index db13b2b40..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio.c +++ /dev/null @@ -1,464 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/// \file - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "pio.h" -#include -#include - -//------------------------------------------------------------------------------ -// Local Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Configures one or more pin(s) of a PIO controller as being controlled by -/// peripheral A. Optionally, the corresponding internal pull-up(s) can be -/// enabled. -/// \param pio Pointer to a PIO controller. -/// \param mask Bitmask of one or more pin(s) to configure. -/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be -/// configured. -//------------------------------------------------------------------------------ -static void PIO_SetPeripheralA( - Pio *pio, - unsigned int mask, - unsigned char enablePullUp) -{ - unsigned int abcdsr; - // Disable interrupts on the pin(s) - pio->PIO_IDR = mask; - - // Enable the pull-up(s) if necessary - if (enablePullUp) { - pio->PIO_PUER = mask; - } - else { - - pio->PIO_PUDR = mask; - } - - abcdsr = pio->PIO_ABCDSR[0]; - pio->PIO_ABCDSR[0] &= (~mask & abcdsr); - abcdsr = pio->PIO_ABCDSR[1]; - pio->PIO_ABCDSR[1] &= (~mask & abcdsr); - pio->PIO_PDR = mask; -} - -//------------------------------------------------------------------------------ -/// Configures one or more pin(s) of a PIO controller as being controlled by -/// peripheral B. Optionally, the corresponding internal pull-up(s) can be -/// enabled. -/// \param pio Pointer to a PIO controller. -/// \param mask Bitmask of one or more pin(s) to configure. -/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be -/// configured. -//------------------------------------------------------------------------------ -static void PIO_SetPeripheralB( - Pio *pio, - unsigned int mask, - unsigned char enablePullUp) -{ - unsigned int abcdsr; - // Disable interrupts on the pin(s) - pio->PIO_IDR = mask; - - // Enable the pull-up(s) if necessary - if (enablePullUp) { - - pio->PIO_PUER = mask; - } - else { - - pio->PIO_PUDR = mask; - } - - abcdsr = pio->PIO_ABCDSR[0]; - pio->PIO_ABCDSR[0] = (mask | abcdsr); - abcdsr = pio->PIO_ABCDSR[1]; - pio->PIO_ABCDSR[1] &= (~mask & abcdsr); - - pio->PIO_PDR = mask; -} - -//------------------------------------------------------------------------------ -/// Configures one or more pin(s) of a PIO controller as being controlled by -/// peripheral C. Optionally, the corresponding internal pull-up(s) can be -/// enabled. -/// \param pio Pointer to a PIO controller. -/// \param mask Bitmask of one or more pin(s) to configure. -/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be -/// configured. -//------------------------------------------------------------------------------ -static void PIO_SetPeripheralC( - Pio *pio, - unsigned int mask, - unsigned char enablePullUp) -{ - unsigned int abcdsr; - // Disable interrupts on the pin(s) - pio->PIO_IDR = mask; - - // Enable the pull-up(s) if necessary - if (enablePullUp) { - - pio->PIO_PUER = mask; - } - else { - - pio->PIO_PUDR = mask; - } - - abcdsr = pio->PIO_ABCDSR[0]; - pio->PIO_ABCDSR[0] &= (~mask & abcdsr); - abcdsr = pio->PIO_ABCDSR[1]; - pio->PIO_ABCDSR[1] = (mask | abcdsr); - - pio->PIO_PDR = mask; -} - -//------------------------------------------------------------------------------ -/// Configures one or more pin(s) of a PIO controller as being controlled by -/// peripheral D. Optionally, the corresponding internal pull-up(s) can be -/// enabled. -/// \param pio Pointer to a PIO controller. -/// \param mask Bitmask of one or more pin(s) to configure. -/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be -/// configured. -//------------------------------------------------------------------------------ -static void PIO_SetPeripheralD( - Pio *pio, - unsigned int mask, - unsigned char enablePullUp) -{ - unsigned int abcdsr; - // Disable interrupts on the pin(s) - pio->PIO_IDR = mask; - - // Enable the pull-up(s) if necessary - if (enablePullUp) { - - pio->PIO_PUER = mask; - } - else { - - pio->PIO_PUDR = mask; - } - - abcdsr = pio->PIO_ABCDSR[0]; - pio->PIO_ABCDSR[0] = (mask | abcdsr); - abcdsr = pio->PIO_ABCDSR[1]; - pio->PIO_ABCDSR[1] = (mask | abcdsr); - - pio->PIO_PDR = mask; -} - -//------------------------------------------------------------------------------ -/// Configures one or more pin(s) or a PIO controller as inputs. Optionally, -/// the corresponding internal pull-up(s) and glitch filter(s) can be -/// enabled. -/// \param pio Pointer to a PIO controller. -/// \param mask Bitmask indicating which pin(s) to configure as input(s). -/// \param enablePullUp Indicates if the internal pull-up(s) must be enabled. -/// \param enableFilter Indicates if the glitch filter(s) must be enabled. -//------------------------------------------------------------------------------ -static void PIO_SetInput( - Pio *pio, - unsigned int mask, - unsigned char attribute) -{ - // Disable interrupts - pio->PIO_IDR = mask; - - // Enable pull-up(s) if necessary - if (attribute & PIO_PULLUP) - pio->PIO_PUER = mask; - else - pio->PIO_PUDR = mask; - - // Enable de-glitch(s) if necessary - if (attribute & PIO_DEGLITCH) - pio->PIO_IFER = mask; - else - pio->PIO_IFDR = mask; - - // Enable de-bounce if necessary - if (attribute & PIO_DEBOUNCE) { - pio->PIO_DIFSR = mask; - } - - // Configure pin as input - pio->PIO_ODR = mask; - pio->PIO_PER = mask; -} - -//------------------------------------------------------------------------------ -/// Configures one or more pin(s) of a PIO controller as outputs, with the -/// given default value. Optionally, the multi-drive feature can be enabled -/// on the pin(s). -/// \param pio Pointer to a PIO controller. -/// \param mask Bitmask indicating which pin(s) to configure. -/// \param defaultValue Default level on the pin(s). -/// \param enableMultiDrive Indicates if the pin(s) shall be configured as -/// open-drain. -/// \param enablePullUp Indicates if the pin shall have its pull-up activated. -//------------------------------------------------------------------------------ -static void PIO_SetOutput( - Pio *pio, - unsigned int mask, - unsigned char defaultValue, - unsigned char enableMultiDrive, - unsigned char enablePullUp) -{ - // Disable interrupts - pio->PIO_IDR = mask; - - // Enable pull-up(s) if necessary - if (enablePullUp) { - - pio->PIO_PUER = mask; - } - else { - - pio->PIO_PUDR = mask; - } - - // Enable multi-drive if necessary - if (enableMultiDrive) { - - pio->PIO_MDER = mask; - } - else { - - pio->PIO_MDDR = mask; - } - - // Set default value - if (defaultValue) { - - pio->PIO_SODR = mask; - } - else { - - pio->PIO_CODR = mask; - } - - // Configure pin(s) as output(s) - pio->PIO_OER = mask; - pio->PIO_PER = mask; -} - -//------------------------------------------------------------------------------ -/// Configures interrupt mode for input Pins -/// \param pio Pointer to a PIO controller. -/// \param mask Bitmask indicating which pin(s) to configure. -/// \param additionnalItMode Enable Pio Additionnal It Mode. -/// \param edgeMode Enable the edge mode. -/// \param risingEdgeOrHighLevel Enable IT on rising edge or high level. -//------------------------------------------------------------------------------ -static void PIO_SetInterrupt( - Pio *pio, - unsigned int mask, - unsigned char additionnalItMode, - unsigned char edgeMode, - unsigned char risingEdgeOrHighLevel) -{ - /* Configure the Interrupt mode in the PIO controller */ - if (additionnalItMode) { - /* enable additional interrupt mode */ - pio->PIO_AIMER = mask; - - /* if bit field of selected pin is 1, set as Rising Edge/High level detection event */ - if (risingEdgeOrHighLevel) - pio->PIO_REHLSR = mask; - else - pio->PIO_FELLSR = mask; - - /* if bit field of selected pin is 1, set as edge detection source */ - if (edgeMode) - pio->PIO_ESR = mask; - else - pio->PIO_LSR = mask; - } else { - /* disable additional interrupt mode */ - pio->PIO_AIMDR = mask; - } -} - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Configures a list of Pin instances, each of which can either hold a single -/// pin or a group of pins, depending on the mask value; all pins are configured -/// by this function. The size of the array must also be provided and is easily -/// computed using PIO_LISTSIZE whenever its length is not known in advance. -/// \param list Pointer to a list of Pin instances. -/// \param size Size of the Pin list (calculated using PIO_LISTSIZE). -/// \return 1 if the pins have been configured properly; otherwise 0. -//------------------------------------------------------------------------------ -unsigned char PIO_Configure(const Pin *list, unsigned int size) -{ - // Configure pins - while (size > 0) { - - switch (list->type) { - - case PIO_PERIPH_A: - PIO_SetPeripheralA(list->pio, - list->mask, - (list->attribute & PIO_PULLUP) ? 1 : 0); - break; - - case PIO_PERIPH_B: - PIO_SetPeripheralB(list->pio, - list->mask, - (list->attribute & PIO_PULLUP) ? 1 : 0); - break; - - case PIO_PERIPH_C: - PIO_SetPeripheralC(list->pio, - list->mask, - (list->attribute & PIO_PULLUP) ? 1 : 0); - break; - - case PIO_PERIPH_D: - PIO_SetPeripheralD(list->pio, - list->mask, - (list->attribute & PIO_PULLUP) ? 1 : 0); - break; - case PIO_INPUT: - PMC_EnablePeripheral(list->id); - PIO_SetInput(list->pio, - list->mask, - list->attribute); - PIO_SetInterrupt(list->pio, - list->mask, - (list->attribute & PIO_IT_AIME) ? 1 : 0, - (list->attribute & PIO_IT_EDGE) ? 1 : 0, - (list->attribute & PIO_IT_RE_OR_HL) ? 1 : 0); - break; - - case PIO_OUTPUT_0: - case PIO_OUTPUT_1: - PIO_SetOutput(list->pio, - list->mask, - (list->type == PIO_OUTPUT_1), - (list->attribute & PIO_OPENDRAIN) ? 1 : 0, - (list->attribute & PIO_PULLUP) ? 1 : 0); - break; - - default: return 0; - } - - list++; - size--; - } - - return 1; -} - -//------------------------------------------------------------------------------ -/// Sets a high output level on all the PIOs defined in the given Pin instance. -/// This has no immediate effects on PIOs that are not output, but the PIO -/// controller will memorize the value they are changed to outputs. -/// \param pin Pointer to a Pin instance describing one or more pins. -//------------------------------------------------------------------------------ -void PIO_Set(const Pin *pin) -{ - pin->pio->PIO_SODR = pin->mask; -} - -//------------------------------------------------------------------------------ -/// Sets a low output level on all the PIOs defined in the given Pin instance. -/// This has no immediate effects on PIOs that are not output, but the PIO -/// controller will memorize the value they are changed to outputs. -/// \param pin Pointer to a Pin instance describing one or more pins. -//------------------------------------------------------------------------------ -void PIO_Clear(const Pin *pin) -{ - pin->pio->PIO_CODR = pin->mask; -} - -//------------------------------------------------------------------------------ -/// Returns 1 if one or more PIO of the given Pin instance currently have a high -/// level; otherwise returns 0. This method returns the actual value that is -/// being read on the pin. To return the supposed output value of a pin, use -/// PIO_GetOutputDataStatus() instead. -/// \param pin Pointer to a Pin instance describing one or more pins. -/// \return 1 if the Pin instance contains at least one PIO that currently has -/// a high level; otherwise 0. -//------------------------------------------------------------------------------ -unsigned char PIO_Get(const Pin *pin) -{ - unsigned int reg; - if ((pin->type == PIO_OUTPUT_0) || (pin->type == PIO_OUTPUT_1)) { - - reg = pin->pio->PIO_ODSR; - } - else { - - reg = pin->pio->PIO_PDSR; - } - - if ((reg & pin->mask) == 0) { - - return 0; - } - else { - - return 1; - } -} - - -//------------------------------------------------------------------------------ -/// Returns 1 if one or more PIO of the given Pin are configured to output a -/// high level (even if they are not output). -/// To get the actual value of the pin, use PIO_Get() instead. -/// \param pin Pointer to a Pin instance describing one or more pins. -/// \return 1 if the Pin instance contains at least one PIO that is configured -/// to output a high level; otherwise 0. -//------------------------------------------------------------------------------ -unsigned char PIO_GetOutputDataStatus(const Pin *pin) -{ - if ((pin->pio->PIO_ODSR & pin->mask) == 0) { - - return 0; - } - else { - - return 1; - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio.h deleted file mode 100644 index 52fd593bd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio.h +++ /dev/null @@ -1,215 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \file -/// -/// \par Purpose -/// -/// This file provides a basic API for PIO configuration and usage of -/// user-controlled pins. Please refer to the board.h file for a list of -/// available pin definitions. -/// -/// \par Usage -/// -/// -# Define a constant pin description array such as the following one, using -/// the existing definitions provided by the board.h file if possible: -/// \code -/// const Pin pPins[] = {PIN_USART0_TXD, PIN_USART0_RXD}; -/// \endcode -/// Alternatively, it is possible to add new pins by provided the full Pin -/// structure: -/// \code -/// // Pin instance to configure PA10 & PA11 as inputs with the internal -/// // pull-up enabled. -/// const Pin pPins = { -/// (1 << 10) | (1 << 11), -/// REG_PIOA, -/// ID_PIOA, -/// PIO_INPUT, -/// PIO_PULLUP -/// }; -/// \endcode -/// -# Configure a pin array by calling PIO_Configure() with a pointer to the -/// array and its size (which is computed using the PIO_LISTSIZE macro). -/// -# Change and get the value of a user-controlled pin using the PIO_Set, -/// PIO_Clear and PIO_Get methods. -/// -# Get the level being currently output by a user-controlled pin configured -/// as an output using PIO_GetOutputDataStatus(). -//------------------------------------------------------------------------------ - -#ifndef PIO_H -#define PIO_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Global Definitions -//------------------------------------------------------------------------------ - -/// The pin is controlled by the associated signal of peripheral A. -#define PIO_PERIPH_A 0 -/// The pin is controlled by the associated signal of peripheral B. -#define PIO_PERIPH_B 1 -/// The pin is controlled by the associated signal of peripheral C. -#define PIO_PERIPH_C 2 -/// The pin is controlled by the associated signal of peripheral D. -#define PIO_PERIPH_D 3 -/// The pin is an input. -#define PIO_INPUT 4 -/// The pin is an output and has a default level of 0. -#define PIO_OUTPUT_0 5 -/// The pin is an output and has a default level of 1. -#define PIO_OUTPUT_1 6 - -/// Default pin configuration (no attribute). -#define PIO_DEFAULT (0 << 0) -/// The internal pin pull-up is active. -#define PIO_PULLUP (1 << 0) -/// The internal glitch filter is active. -#define PIO_DEGLITCH (1 << 1) -/// The pin is open-drain. -#define PIO_OPENDRAIN (1 << 2) - -/// The internal debouncing filter is active. -#define PIO_DEBOUNCE (1 << 3) - -/// Enable additional interrupt modes. -#define PIO_IT_AIME (1 << 4) - -/// Interrupt High Level/Rising Edge detection is active. -#define PIO_IT_RE_OR_HL (1 << 5) -/// Interrupt Edge detection is active. -#define PIO_IT_EDGE (1 << 6) - -/// Low level interrupt is active -#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME) -/// High level interrupt is active -#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME) -/// Falling edge interrupt is active -#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME) -/// Rising edge interrupt is active -#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME) - -//------------------------------------------------------------------------------ -// Global Macros -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Calculates the size of an array of Pin instances. The array must be defined -/// locally (i.e. not a pointer), otherwise the computation will not be correct. -/// \param pPins Local array of Pin instances. -/// \return Number of elements in array. -//------------------------------------------------------------------------------ -#define PIO_LISTSIZE(pPins) (sizeof(pPins) / sizeof(Pin)) - -//------------------------------------------------------------------------------ -// Global Types -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// Describes the type and attribute of one PIO pin or a group of similar pins. -/// The #type# field can have the following values: -/// - PIO_PERIPH_A -/// - PIO_PERIPH_B -/// - PIO_OUTPUT_0 -/// - PIO_OUTPUT_1 -/// - PIO_INPUT -/// -/// The #attribute# field is a bitmask that can either be set to PIO_DEFAULt, -/// or combine (using bitwise OR '|') any number of the following constants: -/// - PIO_PULLUP -/// - PIO_DEGLITCH -/// - PIO_DEBOUNCE -/// - PIO_OPENDRAIN -/// - PIO_IT_LOW_LEVEL -/// - PIO_IT_HIGH_LEVEL -/// - PIO_IT_FALL_EDGE -/// - PIO_IT_RISE_EDGE -//------------------------------------------------------------------------------ -typedef struct { - - /// Bitmask indicating which pin(s) to configure. - unsigned int mask; - /// Pointer to the PIO controller which has the pin(s). - Pio *pio; - /// Peripheral ID of the PIO controller which has the pin(s). - unsigned char id; - /// Pin type. - unsigned char type; - /// Pin attribute. - unsigned char attribute; -} Pin; - -//------------------------------------------------------------------------------ -// Global Access Macros -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// Configures Glitch or Debouncing filter for input -/// \param pin Pointer to a Pin instance describing one or more pins. -/// \param cuttoff Cutt off frequency for debounce filter -//------------------------------------------------------------------------------ -static inline void PIO_SetDebounceFilter( - const Pin *pin, - unsigned int cuttoff) - { - Pio *pio = pin->pio; - - pio->PIO_DIFSR = pin->mask;//set Debouncing, 0 bit field no effect - pio->PIO_SCDR = ((32678/(2*(cuttoff))) - 1) & 0x3FFF;//the lowest 14 bits work -} - - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -extern unsigned char PIO_Configure(const Pin *list, unsigned int size); - -extern void PIO_Set(const Pin *pin); - -extern void PIO_Clear(const Pin *pin); - -extern unsigned char PIO_Get(const Pin *pin); - -//extern unsigned int PIO_GetISR(const Pin *pin); - -extern unsigned char PIO_GetOutputDataStatus(const Pin *pin); - -extern void PIO_EnableDebounce(const Pin *pin, unsigned int clkDiv); - -#endif //#ifndef PIO_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_it.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_it.c deleted file mode 100644 index e04a07c5b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_it.c +++ /dev/null @@ -1,411 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/// \file - -/// Disable traces for this file -#undef TRACE_LEVEL -#define TRACE_LEVEL 0 - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "pio_it.h" -#include "pio.h" -#include -#include -#include -#include -#include - -//------------------------------------------------------------------------------ -// Local definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Local types -//------------------------------------------------------------------------------ -/* Define WEAK attribute */ -#if defined ( __CC_ARM ) - #define WEAK __attribute__ ((weak)) -#elif defined ( __ICCARM__ ) - #define WEAK __weak -#elif defined ( __GNUC__ ) - #define WEAK __attribute__ ((weak)) -#endif - - -//------------------------------------------------------------------------------ -// Local variables -//------------------------------------------------------------------------------ -typedef void (*PioHandler) (unsigned char id); - -/* Default PIO handlers defined as weak functions which have to be redefined by - * the application */ -WEAK void PIOA_Irq0Handler(unsigned char id) {} -WEAK void PIOA_Irq1Handler(unsigned char id) {} -WEAK void PIOA_Irq2Handler(unsigned char id) {} -WEAK void PIOA_Irq3Handler(unsigned char id) {} -WEAK void PIOA_Irq4Handler(unsigned char id) {} -WEAK void PIOA_Irq5Handler(unsigned char id) {} -WEAK void PIOA_Irq6Handler(unsigned char id) {} -WEAK void PIOA_Irq7Handler(unsigned char id) {} -WEAK void PIOA_Irq8Handler(unsigned char id) {} -WEAK void PIOA_Irq9Handler(unsigned char id) {} -WEAK void PIOA_Irq10Handler(unsigned char id) {} -WEAK void PIOA_Irq11Handler(unsigned char id) {} -WEAK void PIOA_Irq12Handler(unsigned char id) {} -WEAK void PIOA_Irq13Handler(unsigned char id) {} -WEAK void PIOA_Irq14Handler(unsigned char id) {} -WEAK void PIOA_Irq15Handler(unsigned char id) {} -WEAK void PIOA_Irq16Handler(unsigned char id) {} -WEAK void PIOA_Irq17Handler(unsigned char id) {} -WEAK void PIOA_Irq18Handler(unsigned char id) {} -WEAK void PIOA_Irq19Handler(unsigned char id) {} -WEAK void PIOA_Irq20Handler(unsigned char id) {} -WEAK void PIOA_Irq21Handler(unsigned char id) {} -WEAK void PIOA_Irq22Handler(unsigned char id) {} -WEAK void PIOA_Irq23Handler(unsigned char id) {} -WEAK void PIOA_Irq24Handler(unsigned char id) {} -WEAK void PIOA_Irq25Handler(unsigned char id) {} -WEAK void PIOA_Irq26Handler(unsigned char id) {} -WEAK void PIOA_Irq27Handler(unsigned char id) {} -WEAK void PIOA_Irq28Handler(unsigned char id) {} -WEAK void PIOA_Irq29Handler(unsigned char id) {} -WEAK void PIOA_Irq30Handler(unsigned char id) {} -WEAK void PIOA_Irq31Handler(unsigned char id) {} - - -/** pioAHandlers records ISR routines for each PIO Id for PIO controller A */ -static const PioHandler pioAHandlers[32] = { - (PioHandler) PIOA_Irq0Handler, /**< PA0 IT Handler */ - (PioHandler) PIOA_Irq1Handler, /**< PA1 IT Handler */ - (PioHandler) PIOA_Irq2Handler, /**< PA2 IT Handler */ - (PioHandler) PIOA_Irq3Handler, /**< PA3 IT Handler */ - (PioHandler) PIOA_Irq4Handler, /**< PA4 IT Handler */ - (PioHandler) PIOA_Irq5Handler, /**< PA5 IT Handler */ - (PioHandler) PIOA_Irq6Handler, /**< PA6 IT Handler */ - (PioHandler) PIOA_Irq7Handler, /**< PA7 IT Handler */ - (PioHandler) PIOA_Irq8Handler, /**< PA8 IT Handler */ - (PioHandler) PIOA_Irq9Handler, /**< PA9 IT Handler */ - (PioHandler) PIOA_Irq10Handler, /**< PA10 IT Handler */ - (PioHandler) PIOA_Irq11Handler, /**< PA11 IT Handler */ - (PioHandler) PIOA_Irq12Handler, /**< PA12 IT Handler */ - (PioHandler) PIOA_Irq13Handler, /**< PA13 IT Handler */ - (PioHandler) PIOA_Irq14Handler, /**< PA14 IT Handler */ - (PioHandler) PIOA_Irq15Handler, /**< PA15 IT Handler */ - (PioHandler) PIOA_Irq16Handler, /**< PA16 IT Handler */ - (PioHandler) PIOA_Irq17Handler, /**< PA17 IT Handler */ - (PioHandler) PIOA_Irq18Handler, /**< PA18 IT Handler */ - (PioHandler) PIOA_Irq19Handler, /**< PA19 IT Handler */ - (PioHandler) PIOA_Irq20Handler, /**< PA20 IT Handler */ - (PioHandler) PIOA_Irq21Handler, /**< PA21 IT Handler */ - (PioHandler) PIOA_Irq22Handler, /**< PA22 IT Handler */ - (PioHandler) PIOA_Irq23Handler, /**< PA23 IT Handler */ - (PioHandler) PIOA_Irq24Handler, /**< PA24 IT Handler */ - (PioHandler) PIOA_Irq25Handler, /**< PA25 IT Handler */ - (PioHandler) PIOA_Irq26Handler, /**< PA26 IT Handler */ - (PioHandler) PIOA_Irq27Handler, /**< PA27 IT Handler */ - (PioHandler) PIOA_Irq28Handler, /**< PA28 IT Handler */ - (PioHandler) PIOA_Irq29Handler, /**< PA29 IT Handler */ - (PioHandler) PIOA_Irq30Handler, /**< PA30 IT Handler */ - (PioHandler) PIOA_Irq31Handler /**< PA31 IT Handler */ -}; - -/* Default PIO handlers defined as weak functions which have to be redefined by - * the application */ -WEAK void PIOB_Irq0Handler(unsigned char id) {} -WEAK void PIOB_Irq1Handler(unsigned char id) {} -WEAK void PIOB_Irq2Handler(unsigned char id) {} -WEAK void PIOB_Irq3Handler(unsigned char id) {} -WEAK void PIOB_Irq4Handler(unsigned char id) {} -WEAK void PIOB_Irq5Handler(unsigned char id) {} -WEAK void PIOB_Irq6Handler(unsigned char id) {} -WEAK void PIOB_Irq7Handler(unsigned char id) {} -WEAK void PIOB_Irq8Handler(unsigned char id) {} -WEAK void PIOB_Irq9Handler(unsigned char id) {} -WEAK void PIOB_Irq10Handler(unsigned char id) {} -WEAK void PIOB_Irq11Handler(unsigned char id) {} -WEAK void PIOB_Irq12Handler(unsigned char id) {} -WEAK void PIOB_Irq13Handler(unsigned char id) {} -WEAK void PIOB_Irq14Handler(unsigned char id) {} -WEAK void PIOB_Irq15Handler(unsigned char id) {} -WEAK void PIOB_Irq16Handler(unsigned char id) {} -WEAK void PIOB_Irq17Handler(unsigned char id) {} -WEAK void PIOB_Irq18Handler(unsigned char id) {} -WEAK void PIOB_Irq19Handler(unsigned char id) {} -WEAK void PIOB_Irq20Handler(unsigned char id) {} -WEAK void PIOB_Irq21Handler(unsigned char id) {} -WEAK void PIOB_Irq22Handler(unsigned char id) {} -WEAK void PIOB_Irq23Handler(unsigned char id) {} -WEAK void PIOB_Irq24Handler(unsigned char id) {} -WEAK void PIOB_Irq25Handler(unsigned char id) {} -WEAK void PIOB_Irq26Handler(unsigned char id) {} -WEAK void PIOB_Irq27Handler(unsigned char id) {} -WEAK void PIOB_Irq28Handler(unsigned char id) {} -WEAK void PIOB_Irq29Handler(unsigned char id) {} -WEAK void PIOB_Irq30Handler(unsigned char id) {} -WEAK void PIOB_Irq31Handler(unsigned char id) {} - - -/** PIOBHandlers records ISR routines for each PIO Id for PIO controller A */ -static const PioHandler pioBHandlers[32] = { - (PioHandler) PIOB_Irq0Handler, /**< PB0 IT Handler */ - (PioHandler) PIOB_Irq1Handler, /**< PB1 IT Handler */ - (PioHandler) PIOB_Irq2Handler, /**< PB2 IT Handler */ - (PioHandler) PIOB_Irq3Handler, /**< PB3 IT Handler */ - (PioHandler) PIOB_Irq4Handler, /**< PB4 IT Handler */ - (PioHandler) PIOB_Irq5Handler, /**< PB5 IT Handler */ - (PioHandler) PIOB_Irq6Handler, /**< PB6 IT Handler */ - (PioHandler) PIOB_Irq7Handler, /**< PB7 IT Handler */ - (PioHandler) PIOB_Irq8Handler, /**< PB8 IT Handler */ - (PioHandler) PIOB_Irq9Handler, /**< PB9 IT Handler */ - (PioHandler) PIOB_Irq10Handler, /**< PB10 IT Handler */ - (PioHandler) PIOB_Irq11Handler, /**< PB11 IT Handler */ - (PioHandler) PIOB_Irq12Handler, /**< PB12 IT Handler */ - (PioHandler) PIOB_Irq13Handler, /**< PB13 IT Handler */ - (PioHandler) PIOB_Irq14Handler, /**< PB14 IT Handler */ - (PioHandler) PIOB_Irq15Handler, /**< PB15 IT Handler */ - (PioHandler) PIOB_Irq16Handler, /**< PB16 IT Handler */ - (PioHandler) PIOB_Irq17Handler, /**< PB17 IT Handler */ - (PioHandler) PIOB_Irq18Handler, /**< PB18 IT Handler */ - (PioHandler) PIOB_Irq19Handler, /**< PB19 IT Handler */ - (PioHandler) PIOB_Irq20Handler, /**< PB20 IT Handler */ - (PioHandler) PIOB_Irq21Handler, /**< PB21 IT Handler */ - (PioHandler) PIOB_Irq22Handler, /**< PB22 IT Handler */ - (PioHandler) PIOB_Irq23Handler, /**< PB23 IT Handler */ - (PioHandler) PIOB_Irq24Handler, /**< PB24 IT Handler */ - (PioHandler) PIOB_Irq25Handler, /**< PB25 IT Handler */ - (PioHandler) PIOB_Irq26Handler, /**< PB26 IT Handler */ - (PioHandler) PIOB_Irq27Handler, /**< PB27 IT Handler */ - (PioHandler) PIOB_Irq28Handler, /**< PB28 IT Handler */ - (PioHandler) PIOB_Irq29Handler, /**< PB29 IT Handler */ - (PioHandler) PIOB_Irq30Handler, /**< PB30 IT Handler */ - (PioHandler) PIOB_Irq31Handler /**< PB31 IT Handler */ -}; - -/* Default PIO handlers defined as weak functions which have to be redefined by - * the application */ -WEAK void PIOC_Irq0Handler(unsigned char id) {} -WEAK void PIOC_Irq1Handler(unsigned char id) {} -WEAK void PIOC_Irq2Handler(unsigned char id) {} -WEAK void PIOC_Irq3Handler(unsigned char id) {} -WEAK void PIOC_Irq4Handler(unsigned char id) {} -WEAK void PIOC_Irq5Handler(unsigned char id) {} -WEAK void PIOC_Irq6Handler(unsigned char id) {} -WEAK void PIOC_Irq7Handler(unsigned char id) {} -WEAK void PIOC_Irq8Handler(unsigned char id) {} -WEAK void PIOC_Irq9Handler(unsigned char id) {} -WEAK void PIOC_Irq10Handler(unsigned char id) {} -WEAK void PIOC_Irq11Handler(unsigned char id) {} -WEAK void PIOC_Irq12Handler(unsigned char id) {} -WEAK void PIOC_Irq13Handler(unsigned char id) {} -WEAK void PIOC_Irq14Handler(unsigned char id) {} -WEAK void PIOC_Irq15Handler(unsigned char id) {} -WEAK void PIOC_Irq16Handler(unsigned char id) {} -WEAK void PIOC_Irq17Handler(unsigned char id) {} -WEAK void PIOC_Irq18Handler(unsigned char id) {} -WEAK void PIOC_Irq19Handler(unsigned char id) {} -WEAK void PIOC_Irq20Handler(unsigned char id) {} -WEAK void PIOC_Irq21Handler(unsigned char id) {} -WEAK void PIOC_Irq22Handler(unsigned char id) {} -WEAK void PIOC_Irq23Handler(unsigned char id) {} -WEAK void PIOC_Irq24Handler(unsigned char id) {} -WEAK void PIOC_Irq25Handler(unsigned char id) {} -WEAK void PIOC_Irq26Handler(unsigned char id) {} -WEAK void PIOC_Irq27Handler(unsigned char id) {} -WEAK void PIOC_Irq28Handler(unsigned char id) {} -WEAK void PIOC_Irq29Handler(unsigned char id) {} -WEAK void PIOC_Irq30Handler(unsigned char id) {} -WEAK void PIOC_Irq31Handler(unsigned char id) {} - - -/** PIOCHandlers records ISR routines for each PIO Id for PIO controller A */ -static const PioHandler pioCHandlers[32] = { - (PioHandler) PIOC_Irq0Handler, /**< PC0 IT Handler */ - (PioHandler) PIOC_Irq1Handler, /**< PC1 IT Handler */ - (PioHandler) PIOC_Irq2Handler, /**< PC2 IT Handler */ - (PioHandler) PIOC_Irq3Handler, /**< PC3 IT Handler */ - (PioHandler) PIOC_Irq4Handler, /**< PC4 IT Handler */ - (PioHandler) PIOC_Irq5Handler, /**< PC5 IT Handler */ - (PioHandler) PIOC_Irq6Handler, /**< PC6 IT Handler */ - (PioHandler) PIOC_Irq7Handler, /**< PC7 IT Handler */ - (PioHandler) PIOC_Irq8Handler, /**< PC8 IT Handler */ - (PioHandler) PIOC_Irq9Handler, /**< PC9 IT Handler */ - (PioHandler) PIOC_Irq10Handler, /**< PC10 IT Handler */ - (PioHandler) PIOC_Irq11Handler, /**< PC11 IT Handler */ - (PioHandler) PIOC_Irq12Handler, /**< PC12 IT Handler */ - (PioHandler) PIOC_Irq13Handler, /**< PC13 IT Handler */ - (PioHandler) PIOC_Irq14Handler, /**< PC14 IT Handler */ - (PioHandler) PIOC_Irq15Handler, /**< PC15 IT Handler */ - (PioHandler) PIOC_Irq16Handler, /**< PC16 IT Handler */ - (PioHandler) PIOC_Irq17Handler, /**< PC17 IT Handler */ - (PioHandler) PIOC_Irq18Handler, /**< PC18 IT Handler */ - (PioHandler) PIOC_Irq19Handler, /**< PC19 IT Handler */ - (PioHandler) PIOC_Irq20Handler, /**< PC20 IT Handler */ - (PioHandler) PIOC_Irq21Handler, /**< PC21 IT Handler */ - (PioHandler) PIOC_Irq22Handler, /**< PC22 IT Handler */ - (PioHandler) PIOC_Irq23Handler, /**< PC23 IT Handler */ - (PioHandler) PIOC_Irq24Handler, /**< PC24 IT Handler */ - (PioHandler) PIOC_Irq25Handler, /**< PC25 IT Handler */ - (PioHandler) PIOC_Irq26Handler, /**< PC26 IT Handler */ - (PioHandler) PIOC_Irq27Handler, /**< PC27 IT Handler */ - (PioHandler) PIOC_Irq28Handler, /**< PC28 IT Handler */ - (PioHandler) PIOC_Irq29Handler, /**< PC29 IT Handler */ - (PioHandler) PIOC_Irq30Handler, /**< PC30 IT Handler */ - (PioHandler) PIOC_Irq31Handler /**< PC31 IT Handler */ -}; - -//------------------------------------------------------------------------------ -/// \brief Generic PIO Handler. -/// The NVIC branches to the PIOx_IrqHandler() registered in exeption.c -/// PIOx_IrqHandler() invokes PIO_IrqHandler which scans which id has triggered -/// an interrupt and call the corresponding routine for the Id (<=> for the pin) -/// \param pPio PIO controller base address. -/// \param pPioHandlers Constant table which contains IT routines for each PIO Id -//------------------------------------------------------------------------------ -static void PIO_IrqHandler(Pio *pPio, const PioHandler *pPioHandlers) -{ - unsigned int status, id; - - status = pPio->PIO_ISR; - status &= pPio->PIO_IMR; - - for (id = 0; id < 32; ++id) { - if (status & (1 << id)) { - pPioHandlers[id](id); - } - } - -} - -//------------------------------------------------------------------------------ -// Global functions -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// \brief Parallel IO Controller A interrupt handler -/// Redefined PIOA interrupt handler for NVIC interrupt table. -//------------------------------------------------------------------------------ -void PIOA_IrqHandler(void) -{ - PIO_IrqHandler(PIOA, pioAHandlers); -} - -//------------------------------------------------------------------------------ -/// \brief Parallel IO Controller B interrupt handler -/// Redefined PIOB interrupt handler for NVIC interrupt table. -//------------------------------------------------------------------------------ -void PIOB_IrqHandler(void) -{ - PIO_IrqHandler(PIOB, pioBHandlers); -} - -//------------------------------------------------------------------------------ -/// \brief Parallel IO Controller C interrupt handler -/// Redefined PIOC interrupt handler for NVIC interrupt table. -//------------------------------------------------------------------------------ -void PIOC_IrqHandler(void) -{ - PIO_IrqHandler(PIOC, pioCHandlers); -} - -//------------------------------------------------------------------------------ -/// Enables the given interrupt source. The status -/// register of the corresponding PIO controller is cleared prior to enabling -/// the interrupt. -/// \param pPin Interrupt source to enable. -//------------------------------------------------------------------------------ -void PIO_EnableIt(const Pin *pPin) -{ - Pio* pio = pPin->pio; - TRACE_DEBUG("PIO_EnableIt()\n\r"); - -// SANITY_CHECK(pPin); - - /* Enable the interrupt in the PIO controller */ - pio->PIO_ISR; - pio->PIO_IER = pPin->mask; - - -} - -//------------------------------------------------------------------------------ -/// Disables a given interrupt source, with no added side effects. -/// \param pPin Interrupt source to disable. -//------------------------------------------------------------------------------ -void PIO_DisableIt(const Pin *pPin) -{ - Pio* pio = pPin->pio; - SANITY_CHECK(pPin); - - TRACE_DEBUG("PIO_DisableIt()\n\r"); - - /* Disable the interrupt in the PIO controller */ - pio->PIO_IDR = pPin->mask; -} - -//------------------------------------------------------------------------------ -/// \brief Initializes the PIO interrupt management logic -/// The desired priority of PIO interrupts must be provided. -/// Calling this function multiple times result in the reset of currently -/// configured interrupts. -/// \param priority PIO controller interrupts priority. -//------------------------------------------------------------------------------ -void PIO_InitializeInterrupts(unsigned int priority) -{ - TRACE_DEBUG("PIO_Initialize()\n\r"); - - // Configure PIO interrupt sources - TRACE_DEBUG("PIO_Initialize: Configuring PIOA\n\r"); - PIOA->PIO_ISR; - PIOA->PIO_IDR = 0xFFFFFFFF; - NVIC_DisableIRQ(PIOA_IRQn); - NVIC_ClearPendingIRQ(PIOA_IRQn); - NVIC_SetPriority(PIOA_IRQn, priority); - NVIC_EnableIRQ(PIOA_IRQn); - - TRACE_DEBUG("PIO_Initialize: Configuring PIOB\n\r"); - PIOB->PIO_ISR; - PIOB->PIO_IDR = 0xFFFFFFFF; - NVIC_DisableIRQ(PIOB_IRQn); - NVIC_ClearPendingIRQ(PIOB_IRQn); - NVIC_SetPriority(PIOB_IRQn, priority); - NVIC_EnableIRQ(PIOB_IRQn); - - TRACE_DEBUG("PIO_Initialize: Configuring PIOC\n\r"); - PIOC->PIO_ISR; - PIOC->PIO_IDR = 0xFFFFFFFF; - NVIC_DisableIRQ(PIOC_IRQn); - NVIC_ClearPendingIRQ(PIOC_IRQn); - NVIC_SetPriority(PIOC_IRQn, priority); - NVIC_EnableIRQ(PIOC_IRQn); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_it.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_it.h deleted file mode 100644 index cc44903ae..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_it.h +++ /dev/null @@ -1,153 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \file -/// -/// \par Purpose -/// -/// Configuration and handling of interrupts on PIO status changes. The API -/// provided here have several advantages over the traditional PIO interrupt -/// configuration approach: -/// - It is highly portable -/// - It automatically demultiplexes interrupts when multiples pins have been -/// configured on a single PIO controller -/// - It allows a group of pins to share the same interrupt -/// -/// However, it also has several minor drawbacks that may prevent from using it -/// in particular applications: -/// - It enables the clocks of all PIO controllers -/// - PIO controllers all share the same interrupt handler, which does the -/// demultiplexing and can be slower than direct configuration -/// - It reserves space for a fixed number of interrupts, which can be -/// increased by modifying the appropriate constant in pio_it.c. -/// -/// \par Usage -/// -/// -# Initialize the PIO interrupt mechanism using PIO_InitializeInterrupts() -/// with the desired priority (0 ... 7). -/// -# Configure a status change interrupt on one or more pin(s) with -/// PIO_ConfigureIt(). -/// -# Enable & disable interrupts on pins using PIO_EnableIt() and -/// PIO_DisableIt(). -//------------------------------------------------------------------------------ - -#ifndef PIO_IT_H -#define PIO_IT_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "pio.h" - -//------------------------------------------------------------------------------ -// Global functions -//------------------------------------------------------------------------------ - -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/// \file - -/// Disable traces for this file -#undef TRACE_LEVEL -#define TRACE_LEVEL 0 - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "pio_it.h" -#include "pio.h" - -//------------------------------------------------------------------------------ -/// \brief Parallel IO Controller A interrupt handler -/// Redefined PIOA interrupt handler for NVIC interrupt table. -//------------------------------------------------------------------------------ -extern void PIOA_IrqHandler(void); -//------------------------------------------------------------------------------ -/// \brief Parallel IO Controller B interrupt handler -/// Redefined PIOB interrupt handler for NVIC interrupt table. -//------------------------------------------------------------------------------ -extern void PIOB_IrqHandler(void); -//------------------------------------------------------------------------------ -/// \brief Parallel IO Controller C interrupt handler -/// Redefined PIOC interrupt handler for NVIC interrupt table. -//------------------------------------------------------------------------------ -extern void PIOC_IrqHandler(void); -//------------------------------------------------------------------------------ -/// Configures and enables the given interrupt source. The status -/// register of the corresponding PIO controller is cleared prior to enabling -/// the interrupt. -/// \param pPin Interrupt source to enable. -//------------------------------------------------------------------------------ -extern void PIO_EnableIt(const Pin *pPin); -//------------------------------------------------------------------------------ -/// Disables a given interrupt source, with no added side effects. -/// \param pPin Interrupt source to disable. -//------------------------------------------------------------------------------ -extern void PIO_DisableIt(const Pin *pPin); -//------------------------------------------------------------------------------ -/// \brief Initializes the PIO interrupt management logic -/// The desired priority of PIO interrupts must be provided. -/// Calling this function multiple times result in the reset of currently -/// configured interrupts. -/// \param priority PIO controller interrupts priority. -//------------------------------------------------------------------------------ -extern void PIO_InitializeInterrupts(unsigned int priority); - -#endif //#ifndef PIO_IT_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_keypad.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_keypad.c deleted file mode 100644 index e0fad2675..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_keypad.c +++ /dev/null @@ -1,147 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include -#include "pio.h" -#include "pio_keypad.h" - - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Configures keypad controller -/// \param pPIO Pointer to a PIO instance -/// \param config Configuration data for given pin,see head file for detail -//------------------------------------------------------------------------------ -void PIO_KeyPadConfig(AT91S_PIO *pPIO, KeyPadConfig *config) -{ - //enable/disable keypad controller - pPIO->PIO_KER = config->enable; - - //if enable, set keypad matrix and debouncing - if(config->enable == TRUE) { - //set key matrix - pPIO->PIO_KRCR = (config->row | config->col<<8) ; - - //set debouncing - pPIO->PIO_KDR = config->debouncing; - - } -} - - -//------------------------------------------------------------------------------ -/// Get Key Press/Release status -/// \param pPIO Pointer to a PIO instance -/// \param event Pointer to a instance of KeyEvent for storing keypad status -//------------------------------------------------------------------------------ -void PIO_GetKeyStatus(AT91S_PIO *pPIO, KeyEvent *event) -{ - int i,j; - - //get key press event - event->kdEvent.press = (pPIO->KSR&0x1)?TRUE:FALSE; - event->kdEvent.keyPressNum = (pPIO->KSR>>8)&0x3; - j=event->kdEvent.keyPressNum+1; - for(i=0; ikdEvent.preKeyMatrix[i].row = ((pPIO->KKPR) >> (8*i)) & 0x7; - event->kdEvent.preKeyMatrix[i].col = ((pPIO->KKPR) >> (8*i+4)) & 0x7; - } - - //get key release event - event->kuEvent.release = ((pPIO->KSR>>1) & 0x1)?TRUE:FALSE; - event->kuEvent.keyRelNum = (pPIO->KSR>>16)&0x3; - j=event->kdEvent.keyPressNum+1; - for(i=0;ikuEvent.relKeyMatrix[i].row = ((pPIO->KKRR) >> (8*i)) & 0x7; - event->kuEvent.relKeyMatrix[i].col = ((pPIO->KKRR) >> (8*i+4)) & 0x7; - } - -} - - -//------------------------------------------------------------------------------ -/// Enable keypad interrupt as Key Press Interrupt or Key Release Interrupt or both -/// \param pPIO Pointer to a PIO instance -/// \param mode Select key interrupt mode to enable, -/// 0x1 Key Press Interrupt -/// 0x2 Key Release Interrupt -/// 0x3 both of two type -//------------------------------------------------------------------------------ -void PIO_KeypadEnableIt(AT91S_PIO *pPIO, unsigned int mode) -{ - switch(mode){ - case 1:PIO_KeyPadEnableKPIt(pPIO); - break; - - case 2:PIO_KeyPadEnableKRIt(pPIO); - break; - - case 3:PIO_KeyPadEnableKPIt(pPIO); - PIO_KeyPadEnableKRIt(pPIO); - break; - - default:break; - } - -} - -//------------------------------------------------------------------------------ -/// Disable Key Press Interrupt or Key Release Interrupt or both of them -/// \param pPIO Pointer to a PIO instance -/// \param mode Select key interrupt mode to disable, -/// 0x1 Key Press Interrupt -/// 0x2 Key Release Interrupt -/// 0x3 both of two type -//------------------------------------------------------------------------------ -void PIO_KeypadDisableIt(AT91S_PIO *pPIO, unsigned int mode) -{ - switch(mode){ - case 1:PIO_KeyPadDisableKPIt(pPIO); - break; - - case 2:PIO_KeyPadDisableKRIt(pPIO); - break; - - case 3:PIO_KeyPadDisableKPIt(pPIO); - PIO_KeyPadDisableKRIt(pPIO); - break; - - default:break; - } - -} - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_keypad.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_keypad.h deleted file mode 100644 index 54021f6bd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pio/pio_keypad.h +++ /dev/null @@ -1,153 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef PIO_KEYPAD_H -#define PIO_KEYPAD_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Global Definitions -//------------------------------------------------------------------------------ - - - - -//------------------------------------------------------------------------------ -// Global Macros -//------------------------------------------------------------------------------ -//enable keypad press interrupt -#define PIO_KeyPadEnableKPIt(pPIO) ((pPIO)->KIER = 1<<0) - -//enable keypad release interrupt -#define PIO_KeyPadEnableKRIt(pPIO) ((pPIO)->KIER = 1<<1) - -//disable keypad press interrupt -#define PIO_KeyPadDisableKPIt(pPIO) ((pPIO)->KIDR = 1<<0) - -//disable keypad release interrupt -#define PIO_KeyPadDisableKRIt(pPIO) ((pPIO)->KIDR = 1<<1) - -//enable keypad controller interrupt -#define PIO_KeyPadEnableIt(pPIO, mode) {switch(mode):\ - case 1:PIO_KeyPadEnableKPIt(pPIO);break;\ - case 2:PIO_KeyPadEnableKRIt(pPIO);break;\ - case 3:PIO_KeyPadEnableKPIt(pPIO);\ - PIO_KeyPadEnableKRIt(pPIO);break;\ - default:break;\ - } - -//disable keypad controller interrupt -#define PIO_KeyPadDisableIt(pPIO, mode) {switch(mode):\ - case 1:PIO_KeyPadDisableKPIt(pPIO);break;\ - case 2:PIO_KeyPadDisableKRIt(pPIO);break;\ - case 3:PIO_KeyPadDisableKPIt(pPIO);\ - PIO_KeyPadDisableKRIt(pPIO);break;\ - default:break;\ - } - -//get keypad controller interrupt mask -#define PIO_KeyPadGetItMask(pPIO) ((pPIO)->PIO_KIMR) - - -//------------------------------------------------------------------------------ -/// Calculates the size of an array of Pin instances. The array must be defined -/// locally (i.e. not a pointer), otherwise the computation will not be correct. -/// \param pPins Local array of Pin instances. -/// \return Number of elements in array. -//------------------------------------------------------------------------------ -#define PIO_LISTSIZE(pPins) (sizeof(pPins) / sizeof(Pin)) - -//------------------------------------------------------------------------------ -// Global Types -//------------------------------------------------------------------------------ -typedef enum { - FALSE, - TRUE -} bool; - -typedef struct _KeyPadConfig { - bool enable;//keypad controller enable or disable - unsigned char col:3;//config column size - unsigned char row:3;//config row size - unsigned int debouncing;//config debouncing -} KeyPadConfig; - - -typedef struct _KeyColRow { - unsigned char row:3; - unsigned char col:3; -} KeyColRow; - - -typedef struct _KeyDownEvent { - bool press;//at least 1 pressed key detected, or 0 - unsigned char keyPressNum;//simultaneously pressed key number - KeyColRow preKeyMatrix[4];//pressed key matrix -} KeyDownEvent; - - - -typedef struct _KeyUpEvent { - bool release;//at least 1 released key detected, or 0 - unsigned char keyRelNum;//simultaneously released key number - KeyColRow relKeyMatrix[4];//released key matrix -} KeyUpEvent; - - - -typedef struct _KeyEvent { - KeyDownEvent kdEvent; - KeyUpEvent kuEvent; -} KeyEvent; - -//------------------------------------------------------------------------------ -// Global Access Macros -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -void PIO_KeyPadConfig(AT91S_PIO *pPIO, KeyPadConfig *config); - -void PIO_GetKeyStatus(AT91S_PIO *pPIO, KeyEvent *event); - -void PIO_KeypadEnableIt(AT91S_PIO *pio, unsigned int mode); - -void PIO_KeypadDisableIt(AT91S_PIO *pio, unsigned int mode); - - -#endif //#ifndef PIO_KEYPAD_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pmc/pmc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pmc/pmc.c deleted file mode 100644 index 2c72eff31..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pmc/pmc.c +++ /dev/null @@ -1,143 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "pmc.h" -#include -#include - -//------------------------------------------------------------------------------ -// Local definitions -//------------------------------------------------------------------------------ -#define MASK_STATUS0 0xFFFFFFFC -#define MASK_STATUS1 0xFFFFFFFF - - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Enables the clock of a peripheral. The peripheral ID is used - * to identify which peripheral is targetted. - * \note The ID must NOT be shifted (i.e. 1 << ID_xxx). - * \param id Peripheral ID (ID_xxx). - */ -void PMC_EnablePeripheral(unsigned int id) -{ - SANITY_CHECK(id < 35); - if (id < 32) { - if ((PMC->PMC_PCSR0 & (1 << id)) == (1 << id)) { - - TRACE_DEBUG("PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", id); - } - else { - PMC->PMC_PCER0 = 1 << id; - } - } - else { - id -= 32; - if ((PMC->PMC_PCSR1 & (1 << id)) == (1 << id)) { - - TRACE_DEBUG("PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", id + 32); - } - else { - PMC->PMC_PCER1 = 1 << id; - } - } -} - -/** - * \brief Disables the clock of a peripheral. The peripheral ID is used - * to identify which peripheral is targetted. - * \note The ID must NOT be shifted (i.e. 1 << ID_xxx). - * \param id Peripheral ID (ID_xxx). - */ -void PMC_DisablePeripheral(unsigned int id) -{ - SANITY_CHECK(id < 35); - if (id < 32) { - if ((PMC->PMC_PCSR0 & (1 << id)) != (1 << id)) { - TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", id); - } - else { - PMC->PMC_PCDR0 = 1 << id; - } - } - else { - id -= 32; - if ((PMC->PMC_PCSR1 & (1 << id)) != (1 << id)) { - TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", id + 32); - } - else { - PMC->PMC_PCDR1 = 1 << id; - } - } -} - -/** - * \brief Enable all the periph clock via PMC - */ -void PMC_EnableAllPeripherals(void) -{ - PMC->PMC_PCER0 = MASK_STATUS0; - while( (PMC->PMC_PCSR0 & MASK_STATUS0) != MASK_STATUS0); - PMC->PMC_PCER1 = MASK_STATUS1; - while( (PMC->PMC_PCSR1 & MASK_STATUS1) != MASK_STATUS1); - TRACE_DEBUG("Enable all periph clocks\n\r"); -} -/** - * \brief Disable all the periph clock via PMC - */ -void PMC_DisableAllPeripherals(void) -{ - PMC->PMC_PCDR0 = MASK_STATUS0; - while((PMC->PMC_PCSR0 & MASK_STATUS0) != 0); - PMC->PMC_PCDR1 = MASK_STATUS1; - while((PMC->PMC_PCSR1 & MASK_STATUS1) != 0); - TRACE_DEBUG("Disable all periph clocks\n\r"); -} - -/** - * \brief Get Periph Status for the given peripheral ID. - * \param id Peripheral ID (ID_xxx). - */ -unsigned int PMC_IsPeriphEnabled(unsigned int id) -{ - SANITY_CHECK(id < 35); - if (id < 32) { - return (PMC->PMC_PCSR0 & (1 << id)); - } - else { - return (PMC->PMC_PCSR1 & (1 << (id - 32))); - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pmc/pmc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pmc/pmc.h deleted file mode 100644 index 0e5bd33e8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pmc/pmc.h +++ /dev/null @@ -1,62 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef PMC_H -#define PMC_H - -//------------------------------------------------------------------------------ -// Global functions -//------------------------------------------------------------------------------ - -#if defined(at91sam7l64) || defined(at91sam7l128) -extern void PMC_SetFastWakeUpInputs(unsigned int inputs); -extern void PMC_DisableMainOscillator(void); -extern -#ifdef __ICCARM__ -__ramfunc -#endif //__ICCARM__ -void PMC_DisableMainOscillatorForWaitMode(void); -#endif // at91sam7l64 at91sam7l128 - -extern void PMC_DisableProcessorClock(void); -extern void PMC_EnablePeripheral(unsigned int id); -extern void PMC_DisablePeripheral(unsigned int id); -extern void PMC_CPUInIdleMode(void); - - -extern void PMC_EnableAllPeripherals(void); - -extern void PMC_DisableAllPeripherals(void); - -extern unsigned int PMC_IsAllPeriphEnabled(void); - -extern unsigned int PMC_IsPeriphEnabled(unsigned int id); - -#endif //#ifndef PMC_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pwmc/pwmc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pwmc/pwmc.c deleted file mode 100644 index 406a5c8ad..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pwmc/pwmc.c +++ /dev/null @@ -1,648 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup pwm_module Working with PWM - * The PWM driver provides the interface to configure and use the PWM - * peripheral. - * - * The PWM macrocell controls square output waveforms of 4 channels. - * Characteristics of output waveforms such as period, duty-cycle, - * dead-time can be configured.\n - * Some of PWM channels can be linked together as synchronous channel and - * duty-cycle of synchronous channels can be updated by PDC automaticly. - * - * Before enabling the channels, they must have been configured first. - * The main settings include: - *
    - *
  • Configuration of the clock generator.
  • - *
  • Selection of the clock for each channel.
  • - *
  • Configuration of output waveform characteristics, such as period, duty-cycle etc.
  • - *
  • Configuration for synchronous channels if needed.
  • - * - Selection of the synchronous channels. - * - Selection of the moment when the WRDY flag and the corresponding PDC - * transfer request are set (PTRM and PTRCS in the PWM_SCM register). - * - Configuration of the update mode (UPDM in the PWM_SCM register). - * - Configuration of the update period (UPR in the PWM_SCUP register). - *
- * - * After the channels is enabled, the user must use respective update registers - * to change the wave characteristics to prevent unexpected output waveform. - * i.e. PWM_CDTYUPDx register should be used if user want to change duty-cycle - * when the channel is enabled. - * - * For more accurate information, please look at the PWM section of the - * Datasheet. - * - * Related files :\n - * \ref pwmc.c\n - * \ref pwmc.h.\n - */ -/*@{*/ -/*@}*/ - -/** - * \file - * - * Implementation of the Pulse Width Modulation Controller (PWM) peripheral. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -/* These headers were introduced in C99 by working group ISO/IEC JTC1/SC22/WG14. */ -#include - -#include "pwmc.h" -#include -#include -#include - -/*---------------------------------------------------------------------------- - * Local functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Finds a prescaler/divisor couple to generate the desired frequency - * from MCK. - * - * Returns the value to enter in PWM_CLK or 0 if the configuration cannot be - * met. - * - * \param frequency Desired frequency in Hz. - * \param mck Master clock frequency in Hz. - */ -static uint16_t FindClockConfiguration( - uint32_t frequency, - uint32_t mck) -{ - uint32_t divisors[11] = {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024}; - uint8_t divisor = 0; - uint32_t prescaler; - - SANITY_CHECK(frequency < mck); - - /* Find prescaler and divisor values */ - prescaler = (mck / divisors[divisor]) / frequency; - while ((prescaler > 255) && (divisor < 11)) { - - divisor++; - prescaler = (mck / divisors[divisor]) / frequency; - } - - /* Return result */ - if (divisor < 11) { - - TRACE_DEBUG("Found divisor=%u and prescaler=%u for freq=%uHz\n\r", - divisors[divisor], prescaler, frequency); - return prescaler | (divisor << 8); - } - else { - - return 0; - } -} - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Configures PWM a channel with the given parameters, basic configure function. - * - * The PWM controller must have been clocked in the PMC prior to calling this - * function. - * Beware: this function disables the channel. It waits until disable is effective. - * - * \param channel Channel number. - * \param prescaler Channel prescaler. - * \param alignment Channel alignment. - * \param polarity Channel polarity. - */ -void PWMC_ConfigureChannel( - uint8_t channel, - uint32_t prescaler, - uint32_t alignment, - uint32_t polarity) -{ - SANITY_CHECK(prescaler < PWM_CMR0_CPRE_MCKB); - SANITY_CHECK((alignment & ~PWM_CMR0_CALG) == 0); - SANITY_CHECK((polarity & ~PWM_CMR0_CPOL) == 0); - - /* Disable channel (effective at the end of the current period) */ - if ((PWM->PWM_SR & (1 << channel)) != 0) { - PWM->PWM_DIS = 1 << channel; - while ((PWM->PWM_SR & (1 << channel)) != 0); - } - - /* Configure channel */ - PWM->PWM_CH_NUM[channel].PWM_CMR = prescaler | alignment | polarity; -} - -/** - * \brief Configures PWM a channel with the given parameters, extend configure function. - * - * The PWM controller must have been clocked in the PMC prior to calling this - * function. - * Beware: this function disables the channel. It waits until disable is effective. - * - * \param channel Channel number. - * \param prescaler Channel prescaler. - * \param alignment Channel alignment. - * \param polarity Channel polarity. - * \param countEventSelect Channel counter event selection. - * \param DTEnable Channel dead time generator enable. - * \param DTHInverte Channel Dead-Time PWMHx output Inverted. - * \param DTLInverte Channel Dead-Time PWMHx output Inverted. - */ -void PWMC_ConfigureChannelExt( - uint8_t channel, - uint32_t prescaler, - uint32_t alignment, - uint32_t polarity, - uint32_t countEventSelect, - uint32_t DTEnable, - uint32_t DTHInverte, - uint32_t DTLInverte) -{ - SANITY_CHECK(prescaler < PWM_CMR0_CPRE_MCKB); - SANITY_CHECK((alignment & ~PWM_CMR0_CALG) == 0); - SANITY_CHECK((polarity & ~PWM_CMR0_CPOL) == 0); - SANITY_CHECK((countEventSelect & ~PWM_CMR0_CES) == 0); - SANITY_CHECK((DTEnable & ~PWM_CMR0_DTE) == 0); - SANITY_CHECK((DTHInverte & ~PWM_CMR0_DTHI) == 0); - SANITY_CHECK((DTLInverte & ~PWM_CMR0_DTLI) == 0); - - /* Disable channel (effective at the end of the current period) */ - if ((PWM->PWM_SR & (1 << channel)) != 0) { - PWM->PWM_DIS = 1 << channel; - while ((PWM->PWM_SR & (1 << channel)) != 0); - } - - /* Configure channel */ - PWM->PWM_CH_NUM[channel].PWM_CMR = prescaler | alignment | polarity | - countEventSelect | DTEnable | DTHInverte | DTLInverte; -} - -/** - * \brief Configures PWM clocks A & B to run at the given frequencies. - * - * This function finds the best MCK divisor and prescaler values automatically. - * - * \param clka Desired clock A frequency (0 if not used). - * \param clkb Desired clock B frequency (0 if not used). - * \param mck Master clock frequency. - */ -void PWMC_ConfigureClocks(uint32_t clka, uint32_t clkb, uint32_t mck) -{ - uint32_t mode = 0; - uint32_t result; - - /* Clock A */ - if (clka != 0) { - - result = FindClockConfiguration(clka, mck); - ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", (unsigned int)clka); - mode |= result; - } - - /* Clock B */ - if (clkb != 0) { - - result = FindClockConfiguration(clkb, mck); - ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", (unsigned int)clkb); - mode |= (result << 16); - } - - /* Configure clocks */ - TRACE_DEBUG("Setting PWM_CLK = 0x%08X\n\r", mode); - PWM->PWM_CLK = mode; -} - -/** - * \brief Sets the period value used by a PWM channel. - * - * This function writes directly to the CPRD register if the channel is disabled; - * otherwise, it uses the update register CPRDUPD. - * - * \param channel Channel number. - * \param period Period value. - */ -void PWMC_SetPeriod(uint8_t channel, uint16_t period) -{ - /* If channel is disabled, write to CPRD */ - if ((PWM->PWM_SR & (1 << channel)) == 0) { - - PWM->PWM_CH_NUM[channel].PWM_CPRD = period; - } - /* Otherwise use update register */ - else { - - PWM->PWM_CH_NUM[channel].PWM_CPRDUPD = period; - } -} - -/** - * \brief Sets the duty cycle used by a PWM channel. - * This function writes directly to the CDTY register if the channel is disabled; - * otherwise it uses the update register CDTYUPD. - * Note that the duty cycle must always be inferior or equal to the channel - * period. - * - * \param channel Channel number. - * \param duty Duty cycle value. - */ -void PWMC_SetDutyCycle(uint8_t channel, uint16_t duty) -{ - SANITY_CHECK(duty <= PWM->PWM_CH_NUM[channel].PWM_CPRD); - - /* If channel is disabled, write to CDTY */ - if ((PWM->PWM_SR & (1 << channel)) == 0) { - - PWM->PWM_CH_NUM[channel].PWM_CDTY = duty; - } - /* Otherwise use update register */ - else { - - PWM->PWM_CH_NUM[channel].PWM_CDTYUPD = duty; - } -} - -/** - * \brief Sets the dead time used by a PWM channel. - * This function writes directly to the DT register if the channel is disabled; - * otherwise it uses the update register DTUPD. - * Note that the dead time must always be inferior or equal to the channel - * period. - * - * \param channel Channel number. - * \param timeH Dead time value for PWMHx output. - * \param timeL Dead time value for PWMLx output. - */ -void PWMC_SetDeadTime(uint8_t channel, uint16_t timeH, uint16_t timeL) -{ - SANITY_CHECK(timeH <= PWM->PWM_CH_NUM[channel].PWM_CPRD); - SANITY_CHECK(timeL <= PWM->PWM_CH_NUM[channel].PWM_CPRD); - - /* If channel is disabled, write to DT */ - if ((PWM->PWM_SR & (1 << channel)) == 0) { - - PWM->PWM_CH_NUM[channel].PWM_DT = timeH | (timeL << 16); - } - /* Otherwise use update register */ - else { - PWM->PWM_CH_NUM[channel].PWM_DTUPD = timeH | (timeL << 16); - } -} - -/** - * \brief Configures Syncronous channel with the given parameters. - * Beware: At this time, the channels should be disabled. - * - * \param channels Bitwise OR of Syncronous channels. - * \param updateMode Syncronous channel update mode. - * \param requestMode PDC transfer request mode. - * \param requestComparisonSelect PDC transfer request comparison selection. - */ -void PWMC_ConfigureSyncChannel( - uint32_t channels, - uint32_t updateMode, - uint32_t requestMode, - uint32_t requestComparisonSelect) -{ - PWM->PWM_SCM = channels | updateMode | requestMode - | requestComparisonSelect; -} - -/** - * \brief Sets the update period of the synchronous channels. - * This function writes directly to the SCUP register if the channel #0 is disabled; - * otherwise it uses the update register SCUPUPD. - * - * \param period update period. - */ -void PWMC_SetSyncChannelUpdatePeriod(uint8_t period) -{ - /* If channel is disabled, write to SCUP */ - if ((PWM->PWM_SR & (1 << 0)) == 0) { - - PWM->PWM_SCUP = period; - } - /* Otherwise use update register */ - else { - - PWM->PWM_SCUPUPD = period; - } -} - -/** - * \brief Sets synchronous channels update unlock. - * - * Note: If the UPDM field is set to 0, writing the UPDULOCK bit to 1 - * triggers the update of the period value, the duty-cycle and - * the dead-time values of synchronous channels at the beginning - * of the next PWM period. If the field UPDM is set to 1 or 2, - * writing the UPDULOCK bit to 1 triggers only the update of - * the period value and of the dead-time values of synchronous channels. - * This bit is automatically reset when the update is done. - */ -void PWMC_SetSyncChannelUpdateUnlock(void) -{ - PWM->PWM_SCUC = PWM_SCUC_UPDULOCK; -} - -/** - * \brief Enables the given PWM channel. - * - * This does NOT enable the corresponding pin;this must be done in the user code. - * - * \param channel Channel number. - */ -void PWMC_EnableChannel(uint8_t channel) -{ - PWM->PWM_ENA = 1 << channel; -} - -/** - * \brief Disables the given PWM channel. - * - * Beware, channel will be effectively disabled at the end of the current period. - * Application can check channel is disabled using the following wait loop: - * while ((PWM->PWM_SR & (1 << channel)) != 0); - * - * \param channel Channel number. - */ -void PWMC_DisableChannel(uint8_t channel) -{ - PWM->PWM_DIS = 1 << channel; -} - -/** - * \brief Enables the period interrupt for the given PWM channel. - * - * \param channel Channel number. - */ -void PWMC_EnableChannelIt(uint8_t channel) -{ - PWM->PWM_IER1 = 1 << channel; -} - -/** - * \brief Disables the period interrupt for the given PWM channel. - * - * \param channel Channel number. - */ -void PWMC_DisableChannelIt(uint8_t channel) -{ - PWM->PWM_IDR1 = 1 << channel; -} - -/** - * \brief Enables the selected interrupts sources on a PWMC peripheral. - * - * \param sources1 Bitwise OR of selected interrupt sources of PWM_IER1. - * \param sources2 Bitwise OR of selected interrupt sources of PWM_IER2. - */ -void PWMC_EnableIt(uint32_t sources1, uint32_t sources2) -{ - PWM->PWM_IER1 = sources1; - PWM->PWM_IER2 = sources2; -} - -/** - * \brief Disables the selected interrupts sources on a PWMC peripheral. - * - * \param sources1 Bitwise OR of selected interrupt sources of PWM_IDR1. - * \param sources2 Bitwise OR of selected interrupt sources of PWM_IDR2. - */ -void PWMC_DisableIt(uint32_t sources1, uint32_t sources2) -{ - PWM->PWM_IDR1 = sources1; - PWM->PWM_IDR2 = sources2; -} - -/** - * \brief Sends the contents of buffer through a PWMC peripheral, using the PDC to - * take care of the transfer. - * - * Note: Duty cycle of syncronous channels can update by PDC - * when the field UPDM (Update Mode) in the PWM_SCM register is set to 2. - * - * \param pwmc Pointer to an Pwm instance. - * \param buffer Data buffer to send. - * \param length Length of the data buffer. - */ -uint8_t PWMC_WriteBuffer(Pwm *pwmc, - void *buffer, - uint32_t length) -{ - /* Check if first bank is free */ - if (pwmc->PWM_TCR == 0) { - - pwmc->PWM_TPR = (uint32_t) buffer; - pwmc->PWM_TCR = length; - pwmc->PWM_PTCR = PERIPH_PTCR_TXTEN; - return 1; - } - /* Check if second bank is free */ - else if (pwmc->PWM_TNCR == 0) { - - pwmc->PWM_TNPR = (uint32_t) buffer; - pwmc->PWM_TNCR = length; - return 1; - } - - /* No free banks */ - return 0; -} - -/** - * \brief Set PWM output override value. - * - * \param value Bitwise OR of output override value. - */ -void PWMC_SetOverrideValue(uint32_t value) -{ - PWM->PWM_OOV = value; -} - -/** - * \brief Enalbe override output. - * - * \param value Bitwise OR of output selection. - * \param sync 0: enable the output asyncronously, 1: enable it syncronously - */ -void PWMC_EnableOverrideOutput(uint32_t value, uint32_t sync) -{ - if (sync) { - - PWM->PWM_OSSUPD = value; - } else { - - PWM->PWM_OSS = value; - } -} - -/** - * \brief Disalbe override output. - * - * \param value Bitwise OR of output selection. - * \param sync 0: enable the output asyncronously, 1: enable it syncronously - */ -void PWMC_DisableOverrideOutput(uint32_t value, uint32_t sync) -{ - if (sync) { - - PWM->PWM_OSCUPD = value; - } else { - - PWM->PWM_OSC = value; - } -} - -/** - * \brief Set PWM fault mode. - * - * \param mode Bitwise OR of fault mode. - */ -void PWMC_SetFaultMode(uint32_t mode) -{ - PWM->PWM_FMR = mode; -} - -/** - * \brief PWM fault clear. - * - * \param fault Bitwise OR of fault to clear. - */ -void PWMC_FaultClear(uint32_t fault) -{ - PWM->PWM_FCR = fault; -} - -/** - * \brief Set PWM fault protection value. - * - * \param value Bitwise OR of fault protection value. - */ -void PWMC_SetFaultProtectionValue(uint32_t value) -{ - PWM->PWM_FPV = value; -} - -/** - * \brief Enable PWM fault protection. - * - * \param value Bitwise OR of FPEx[y]. - */ -void PWMC_EnableFaultProtection(uint32_t value) -{ - PWM->PWM_FPE = value; -} - -/** - * \brief Configure comparison unit. - * - * \param x comparison x index - * \param value comparison x value. - * \param mode comparison x mode - */ -void PWMC_ConfigureComparisonUnit(uint32_t x, uint32_t value, uint32_t mode) -{ - /* If channel is disabled, write to CMPxM & CMPxV */ - if ((PWM->PWM_SR & (1 << 0)) == 0) { - if (x == 0) { - PWM->PWM_CMP0M = mode; - PWM->PWM_CMP0V = value; - } else if (x == 1) { - PWM->PWM_CMP1M = mode; - PWM->PWM_CMP1V = value; - } else if (x == 2) { - PWM->PWM_CMP2M = mode; - PWM->PWM_CMP2V = value; - } else if (x == 3) { - PWM->PWM_CMP3M = mode; - PWM->PWM_CMP3V = value; - } else if (x == 4) { - PWM->PWM_CMP4M = mode; - PWM->PWM_CMP4V = value; - } else if (x == 5) { - PWM->PWM_CMP5M = mode; - PWM->PWM_CMP5V = value; - } else if (x == 6) { - PWM->PWM_CMP6M = mode; - PWM->PWM_CMP6V = value; - } else if (x == 7) { - PWM->PWM_CMP7M = mode; - PWM->PWM_CMP7V = value; - } - } - /* Otherwise use update register */ - else { - if (x == 0) { - PWM->PWM_CMP0MUPD = mode; - PWM->PWM_CMP0VUPD = value; - } else if (x == 1) { - PWM->PWM_CMP1MUPD = mode; - PWM->PWM_CMP1VUPD = value; - } else if (x == 2) { - PWM->PWM_CMP2MUPD = mode; - PWM->PWM_CMP2VUPD = value; - } else if (x == 3) { - PWM->PWM_CMP3MUPD = mode; - PWM->PWM_CMP3VUPD = value; - } else if (x == 4) { - PWM->PWM_CMP4MUPD = mode; - PWM->PWM_CMP4VUPD = value; - } else if (x == 5) { - PWM->PWM_CMP5MUPD = mode; - PWM->PWM_CMP5VUPD = value; - } else if (x == 6) { - PWM->PWM_CMP6MUPD = mode; - PWM->PWM_CMP6VUPD = value; - } else if (x == 7) { - PWM->PWM_CMP7MUPD = mode; - PWM->PWM_CMP7VUPD = value; - } - } -} - -/** - * \brief Configure event line mode. - * - * \param x Line x - * \param mode Bitwise OR of line mode selection - */ -void PWMC_ConfigureEventLineMode(uint32_t x, uint32_t mode) -{ - SANITY_CHECK(x < 2); - - PWM->PWM_ELxMR[x] = mode; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pwmc/pwmc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pwmc/pwmc.h deleted file mode 100644 index 1c0a5b29d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/pwmc/pwmc.h +++ /dev/null @@ -1,159 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * \par Purpose - * - * Interface for configuration the Pulse Width Modulation Controller (PWM) peripheral. - * - * \par Usage - * - * -# Configures PWM clocks A & B to run at the given frequencies using - * \ref PWMC_ConfigureClocks(). - * -# Configure PWMC channel using \ref PWMC_ConfigureChannel(), \ref PWMC_ConfigureChannelExt() - * \ref PWMC_SetPeriod(), \ref PWMC_SetDutyCycle() and \ref PWMC_SetDeadTime(). - * -# Enable & disable channel using \ref PWMC_EnableChannel() and - * \ref PWMC_DisableChannel(). - * -# Enable & disable the period interrupt for the given PWM channel using - * \ref PWMC_EnableChannelIt() and \ref PWMC_DisableChannelIt(). - * -# Enable & disable the selected interrupts sources on a PWMC peripheral - * using \ref PWMC_EnableIt() and \ref PWMC_DisableIt(). - * -# Control syncronous channel using \ref PWMC_ConfigureSyncChannel(), - * \ref PWMC_SetSyncChannelUpdatePeriod() and \ref PWMC_SetSyncChannelUpdateUnlock(). - * -# Control PWM override output using \ref PWMC_SetOverrideValue(), - * \ref PWMC_EnableOverrideOutput() and \ref PWMC_DisableOverrideOutput(). - * -# \ref Send data through the transmitter using \ref PWMC_WriteBuffer(). - * - */ - -#ifndef PWMC_H -#define PWMC_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -/* PWM sub-bit field definition. begin */ -/* TODO: remove them when AT91SAM3S4.h have the definitions. */ -// PWM_CMRx -#define PWM_CMR0_CPRE_MCKA (0xB) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCKB (0xC) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCKA (0xB) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCKA (0xB) // (PWMC_CH) -// PWM_SCM -#define PWM_SCM_UPDM_MODE0 (0x0 << 16) // (PWMC) Manual write of data and manual trigger of the update -#define PWM_SCM_UPDM_MODE1 (0x1 << 16) // (PWMC) Manual write of data and automatic trigger of the update -#define PWM_SCM_UPDM_MODE2 (0x2 << 16) // (PWMC) Automatic write of data and automatic trigger of the update -/* end */ - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void PWMC_ConfigureChannel( - uint8_t channel, - uint32_t prescaler, - uint32_t alignment, - uint32_t polarity); - -extern void PWMC_ConfigureChannelExt( - uint8_t channel, - uint32_t prescaler, - uint32_t alignment, - uint32_t polarity, - uint32_t countEventSelect, - uint32_t DTEnable, - uint32_t DTHInverte, - uint32_t DTLInverte); - -extern void PWMC_ConfigureClocks - (uint32_t clka, - uint32_t clkb, - uint32_t mck); - -extern void PWMC_SetPeriod(uint8_t channel, uint16_t period); - -extern void PWMC_SetDutyCycle(uint8_t channel, uint16_t duty); - -extern void PWMC_SetDeadTime(uint8_t channel, uint16_t timeH, uint16_t timeL); - -extern void PWMC_ConfigureSyncChannel( - uint32_t channels, - uint32_t updateMode, - uint32_t requestMode, - uint32_t requestComparisonSelect); - -extern void PWMC_SetSyncChannelUpdatePeriod(uint8_t period); - -extern void PWMC_SetSyncChannelUpdateUnlock(void); - -extern void PWMC_EnableChannel(uint8_t channel); - -extern void PWMC_DisableChannel(uint8_t channel); - -extern void PWMC_EnableChannelIt(uint8_t channel); - -extern void PWMC_DisableChannelIt(uint8_t channel); - -extern void PWMC_EnableIt(uint32_t sources1, uint32_t sources2); - -extern void PWMC_DisableIt(uint32_t sources1, uint32_t sources2); - -extern uint8_t PWMC_WriteBuffer(Pwm *pwmc, - void *buffer, - uint32_t length); - -extern void PWMC_SetOverrideValue(uint32_t value); - -extern void PWMC_EnableOverrideOutput(uint32_t value, uint32_t sync); - -extern void PWMC_DisableOverrideOutput(uint32_t value, uint32_t sync); - -extern void PWMC_SetFaultMode(uint32_t mode); - -extern void PWMC_FaultClear(uint32_t fault); - -extern void PWMC_SetFaultProtectionValue(uint32_t value); - -extern void PWMC_EnableFaultProtection(uint32_t value); - -extern void PWMC_ConfigureComparisonUnit(uint32_t x, uint32_t value, uint32_t mode); - -extern void PWMC_ConfigureEventLineMode(uint32_t x, uint32_t mode); - -#endif /* #ifndef PWMC_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta1.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta1.txt deleted file mode 100644 index a0aa300d0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta1.txt +++ /dev/null @@ -1,6 +0,0 @@ -QTouch library for AT91SAM3S-EK board version A. -Modified board. - -Burst pulses 5 CPU cycles wide. - -Slider on pins PA0, PA1, PA2, PA3, PA4, PA5 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta2.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta2.txt deleted file mode 100644 index 3ae67b9dd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta2.txt +++ /dev/null @@ -1,10 +0,0 @@ -QTouch library for AT91SAM3S-EK board version A. -Modified board. - -Burst pulses 5 CPU cycles wide. - -A Valid key on pins PC22 and PC23 -A UP key on pins PC24 and PC25 -A Down key on pins PC26 and PC27 -A Left key on pins PC28 and PC29 -A right key on pins PC30 and PC31 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevB.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevB.txt deleted file mode 100644 index b05f3865e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/qtouch/libQTouchIarCfg3SRevB.txt +++ /dev/null @@ -1,11 +0,0 @@ -QTouch library for AT91SAM3S-EK board version B. - -Burst pulses 5 CPU cycles wide. - -Slider on pins PA0, PA1, PA2, PA3, PA4, PA5 - -A Valid key on pins PC22 and PC23 -A UP key on pins PC24 and PC25 -A Down key on pins PC26 and PC27 -A Left key on pins PC28 and PC29 -A right key on pins PC30 and PC31 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtc/rtc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtc/rtc.c deleted file mode 100644 index 8ed4d4305..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtc/rtc.c +++ /dev/null @@ -1,467 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup rtc_module Working with RTC - * The RTC driver provides the interface to configure and use the RTC - * peripheral. - * - * It manages date, time, and alarms.\n - * This timer is clocked by the 32kHz system clock, and is not impacted by - * power management settings (PMC). To be accurate, it is better to use an - * external 32kHz crystal instead of the internal 32kHz RC.\n - * - * It uses BCD format, and time can be set in AM/PM or 24h mode through a - * configuration bit in the mode register.\n - * - * To update date or time, the user has to follow these few steps : - *
    - *
  • Set UPDTIM and/or UPDCAL bit(s) in RTC_CR,
  • - *
  • Polling or IRQ on the ACKUPD bit of RTC_CR,
  • - *
  • Clear ACKUPD bit in RTC_SCCR,
  • - *
  • Update Time and/or Calendar values in RTC_TIMR/RTC_CALR (BCD format),
  • - *
  • Clear UPDTIM and/or UPDCAL bit in RTC_CR.
  • - *
- * An alarm can be set to happen on month, date, hours, minutes or seconds, - * by setting the proper "Enable" bit of each of these fields in the Time and - * Calendar registers. - * This allows a large number of configurations to be available for the user. - * Alarm occurence can be detected even by polling or interrupt. - * - * A check of the validity of the date and time format and values written by the user is automatically done. - * Errors are reported through the Valid Entry Register. - * - * For more accurate information, please look at the RTC section of the - * Datasheet. - * - * Related files :\n - * \ref rtc.c\n - * \ref rtc.h.\n -*/ -/*@{*/ -/*@}*/ - - -/** - * \file - * - * Implementation of Real Time Clock (RTC) controller. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -/* These headers were introduced in C99 by working group ISO/IEC JTC1/SC22/WG14. */ -#include - -#include "rtc.h" -#include -#include -#include - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Sets the RTC in either 12 or 24 hour mode. - * - * \param mode Hour mode. - */ -void RTC_SetHourMode(uint32_t mode) -{ - SANITY_CHECK((mode & 0xFFFFFFFE) == 0); - - TRACE_DEBUG("RTC_SetHourMode()\n\r"); - - RTC->RTC_MR = mode; -} - -/** - * \brief Gets the RTC mode. - * - * \return Hour mode. - */ -uint32_t RTC_GetHourMode( void ) -{ - uint32_t hmode; - - TRACE_DEBUG("RTC_SetHourMode()\n\r"); - - hmode = RTC->RTC_MR; - hmode &= 0xFFFFFFFE; - - return hmode; -} - -/** - * \brief Enables the selected interrupt sources of the RTC. - * - * \param sources Interrupt sources to enable. - */ -void RTC_EnableIt(uint32_t sources) -{ - SANITY_CHECK((sources & ~0x1F) == 0); - - TRACE_DEBUG("RTC_EnableIt()\n\r"); - - RTC->RTC_IER = sources; -} - -/** -* \brief Disables the selected interrupt sources of the RTC. -* -* \param sources Interrupt sources to disable. -*/ -void RTC_DisableIt(uint32_t sources) -{ - SANITY_CHECK((sources & ~0x1F) == 0); - - TRACE_DEBUG("RTC_DisableIt()\n\r"); - - RTC->RTC_IDR = sources; -} - -/** - * \brief Sets the current time in the RTC. - * - * \param hour Current hour in 12 or 24 hour mode. - * \param minute Current minute. - * \param second Current second. - * \return 0 sucess, 1 fail to set - */ -int RTC_SetTime(uint8_t hour, uint8_t minute, uint8_t second) -{ - uint32_t time=0; - uint8_t hour_bcd; - uint8_t min_bcd; - uint8_t sec_bcd; - - TRACE_DEBUG("RTC_SetTime(%02d:%02d:%02d)\n\r", hour, minute, second); - - /* if 12-hour mode, set AMPM bit */ - if ((RTC->RTC_MR & RTC_MR_HRMOD) == RTC_MR_HRMOD) { - - if (hour > 12) { - - hour -= 12; - time |= RTC_TIMR_AMPM; - } - } - hour_bcd = (hour%10) | ((hour/10)<<4); - min_bcd = (minute%10) | ((minute/10)<<4); - sec_bcd = (second%10) | ((second/10)<<4); - - /* value overflow */ - if((hour_bcd & (uint8_t)(~RTC_HOUR_BIT_LEN_MASK)) | - (min_bcd & (uint8_t)(~RTC_MIN_BIT_LEN_MASK)) | - (sec_bcd & (uint8_t)(~RTC_SEC_BIT_LEN_MASK))) - return 1; - - time = sec_bcd | (min_bcd << 8) | (hour_bcd<<16); - - /* Set time */ - while ((RTC->RTC_SR & RTC_SR_SEC) != RTC_SR_SEC); /* wait from previous set */ - RTC->RTC_CR |= RTC_CR_UPDTIM; - while ((RTC->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD); - RTC->RTC_SCCR = RTC_SCCR_ACKCLR; - RTC->RTC_TIMR = time; - RTC->RTC_CR &= ~RTC_CR_UPDTIM; - RTC->RTC_SCCR |= RTC_SCCR_SECCLR; /* clear SECENV in SCCR */ - - return (int)(RTC->RTC_VER & RTC_VER_NVTIM); -} - -/** - * \brief Retrieves the current time as stored in the RTC in several variables. - * - * \param pHour If not null, current hour is stored in this variable. - * \param pMinute If not null, current minute is stored in this variable. - * \param pSecond If not null, current second is stored in this variable. - */ -void RTC_GetTime( - uint8_t *pHour, - uint8_t *pMinute, - uint8_t *pSecond) -{ - uint32_t time; - - TRACE_DEBUG("RTC_GetTime()\n\r"); - - /* Get current RTC time */ - time = RTC->RTC_TIMR; - while (time != RTC->RTC_TIMR) { - - time = RTC->RTC_TIMR; - } - - /* Hour */ - if (pHour) { - - *pHour = ((time & 0x00300000) >> 20) * 10 - + ((time & 0x000F0000) >> 16); - if ((time & RTC_TIMR_AMPM) == RTC_TIMR_AMPM) { - - *pHour += 12; - } - } - - /* Minute */ - if (pMinute) { - - *pMinute = ((time & 0x00007000) >> 12) * 10 - + ((time & 0x00000F00) >> 8); - } - - /* Second */ - if (pSecond) { - - *pSecond = ((time & 0x00000070) >> 4) * 10 - + (time & 0x0000000F); - } -} - -/** - * \brief Sets a time alarm on the RTC. - * The match is performed only on the provided variables; - * Setting all pointers to 0 disables the time alarm. - * - * \note In AM/PM mode, the hour value must have bit #7 set for PM, cleared for - * AM (as expected in the time registers). - * - * \param pHour If not null, the time alarm will hour-match this value. - * \param pMinute If not null, the time alarm will minute-match this value. - * \param pSecond If not null, the time alarm will second-match this value. - * \return 0 success, 1 fail to set - */ -int RTC_SetTimeAlarm( - uint8_t *pHour, - uint8_t *pMinute, - uint8_t *pSecond) -{ - uint32_t alarm = 0; - - TRACE_DEBUG("RTC_SetTimeAlarm()\n\r"); - - /* Hour */ - if (pHour) { - - alarm |= RTC_TIMALR_HOUREN | ((*pHour / 10) << 20) | ((*pHour % 10) << 16); - } - - /* Minute */ - if (pMinute) { - - alarm |= RTC_TIMALR_MINEN | ((*pMinute / 10) << 12) | ((*pMinute % 10) << 8); - } - - /* Second */ - if (pSecond) { - - alarm |= RTC_TIMALR_SECEN | ((*pSecond / 10) << 4) | (*pSecond % 10); - } - - RTC->RTC_TIMALR = alarm; - - return (int)(RTC->RTC_VER & RTC_VER_NVTIMALR); -} - -/** - * \brief Retrieves the current year, month and day from the RTC. - * Month, day and week values are numbered starting at 1. - * - * \param pYear Current year (optional). - * \param pMonth Current month (optional). - * \param pDay Current day (optional). - * \param pWeek Current day in current week (optional). - */ -void RTC_GetDate( - unsigned short *pYear, - uint8_t *pMonth, - uint8_t *pDay, - uint8_t *pWeek) -{ - uint32_t date; - - /* Get current date (multiple reads are necessary to insure a stable value) */ - do { - - date = RTC->RTC_CALR; - } - while (date != RTC->RTC_CALR); - - /* Retrieve year */ - if (pYear) { - - *pYear = (((date >> 4) & 0x7) * 1000) - + ((date & 0xF) * 100) - + (((date >> 12) & 0xF) * 10) - + ((date >> 8) & 0xF); - } - - /* Retrieve month */ - if (pMonth) { - - *pMonth = (((date >> 20) & 1) * 10) + ((date >> 16) & 0xF); - } - - /* Retrieve day */ - if (pDay) { - - *pDay = (((date >> 28) & 0x3) * 10) + ((date >> 24) & 0xF); - } - - /* Retrieve week */ - if (pWeek) { - - *pWeek = ((date >> 21) & 0x7); - } -} - -/** - * \brief Sets the current year, month and day in the RTC. - * Month, day and week values must be numbered starting from 1. - * - * \param year Current year. - * \param month Current month. - * \param day Current day. - * \param week Day number in current week. - * \return 0 success, 1 fail to set - */ -int RTC_SetDate( - unsigned short year, - uint8_t month, - uint8_t day, - uint8_t week) -{ - uint32_t date; - uint8_t cent_bcd; - uint8_t year_bcd; - uint8_t month_bcd; - uint8_t day_bcd; - uint8_t week_bcd; - - cent_bcd = ((year/100)%10) | ((year/1000)<<4); - year_bcd = (year%10) | (((year/10)%10)<<4); - month_bcd = ((month%10) | (month/10)<<4); - day_bcd = ((day%10) | (day/10)<<4); - week_bcd = ((week%10) | (week/10)<<4); - - /* value over flow */ - if((cent_bcd & (uint8_t)(~RTC_CENT_BIT_LEN_MASK)) | - (year_bcd & (uint8_t)(~RTC_YEAR_BIT_LEN_MASK)) | - (month_bcd & (uint8_t)(~RTC_MONTH_BIT_LEN_MASK)) | - (week_bcd & (uint8_t)(~RTC_WEEK_BIT_LEN_MASK)) | - (day_bcd & (uint8_t)(~RTC_DATE_BIT_LEN_MASK))) - return 1; - - - /* Convert values to date register value */ - date = cent_bcd | - (year_bcd << 8) | - (month_bcd << 16) | - (week_bcd << 21) | - (day_bcd << 24); - - - /* Update calendar register */ - while ((RTC->RTC_SR & RTC_SR_SEC) != RTC_SR_SEC); /* wait from previous set */ - RTC->RTC_CR |= RTC_CR_UPDCAL; - while ((RTC->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD); - RTC->RTC_SCCR = RTC_SCCR_ACKCLR; - RTC->RTC_CALR = date; - RTC->RTC_CR &= ~RTC_CR_UPDCAL; - RTC->RTC_SCCR |= RTC_SCCR_SECCLR; /* clear SECENV in SCCR */ - - return (int)(RTC->RTC_VER & RTC_VER_NVCAL); -} - -/** - * \brief Sets a date alarm in the RTC. - * The alarm will match only the provided values; - * Passing a null-pointer disables the corresponding field match. - * - * \param pMonth If not null, the RTC alarm will month-match this value. - * \param pDay If not null, the RTC alarm will day-match this value. - * \return 0 success, 1 fail to set - */ -int RTC_SetDateAlarm(uint8_t *pMonth, uint8_t *pDay) -{ - uint32_t alarm; - - alarm = ((pMonth) || (pDay)) ? (0) : (0x01010000); - - TRACE_DEBUG("RTC_SetDateAlarm()\n\r"); - - /* Compute alarm field value */ - if (pMonth) { - - alarm |= RTC_CALALR_MTHEN | ((*pMonth / 10) << 20) | ((*pMonth % 10) << 16); - } - if (pDay) { - - alarm |= RTC_CALALR_DATEEN | ((*pDay / 10) << 28) | ((*pDay % 10) << 24); - } - - /* Set alarm */ - RTC->RTC_CALALR = alarm; - - return (int)(RTC->RTC_VER & RTC_VER_NVCALALR); -} - -/** - * \brief Clear flag bits of status clear command register in the RTC. - * - * \param mask Bits mask of cleared events - */ -void RTC_ClearSCCR(uint32_t mask) -{ - /* Clear all flag bits in status clear command register */ - mask &= RTC_SCCR_ACKCLR | RTC_SCCR_ALRCLR | RTC_SCCR_SECCLR | \ - RTC_SCCR_TIMCLR | RTC_SCCR_CALCLR; - - RTC->RTC_SCCR = mask; -} - -/** - * \brief Get flag bits of status register in the RTC. - * - * \param mask Bits mask of Status Register - * \return Status register & mask - */ -uint32_t RTC_GetSR(uint32_t mask) -{ - uint32_t event; - - event = RTC->RTC_SR; - - return (event & mask); -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtc/rtc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtc/rtc.h deleted file mode 100644 index 5f821d3d9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtc/rtc.h +++ /dev/null @@ -1,99 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for Real Time Clock (RTC) controller. - * - */ - -#ifndef RTC_H -#define RTC_H - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -#define RTC_HOUR_BIT_LEN_MASK 0x3F -#define RTC_MIN_BIT_LEN_MASK 0x7F -#define RTC_SEC_BIT_LEN_MASK 0x7F -#define RTC_CENT_BIT_LEN_MASK 0x7F -#define RTC_YEAR_BIT_LEN_MASK 0xFF -#define RTC_MONTH_BIT_LEN_MASK 0x1F -#define RTC_DATE_BIT_LEN_MASK 0x3F -#define RTC_WEEK_BIT_LEN_MASK 0x07 - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void RTC_SetHourMode(uint32_t mode); - -extern uint32_t RTC_GetHourMode( void ) ; - -extern void RTC_EnableIt(uint32_t sources); - -extern void RTC_DisableIt(uint32_t sources); - -extern int RTC_SetTime( - uint8_t hour, - uint8_t minute, - uint8_t second); - -extern void RTC_GetTime( - uint8_t *pHour, - uint8_t *pMinute, - uint8_t *pSecond); - -extern int RTC_SetTimeAlarm( - uint8_t *pHour, - uint8_t *pMinute, - uint8_t *pSecond); - -extern void RTC_GetDate( - unsigned short *pYear, - uint8_t *pMonth, - uint8_t *pDay, - uint8_t *pWeek); - -extern int RTC_SetDate( - unsigned short year, - uint8_t month, - uint8_t day, - uint8_t week); - -extern int RTC_SetDateAlarm(uint8_t *pMonth, uint8_t *pDay); - -extern void RTC_ClearSCCR(uint32_t mask); - -extern uint32_t RTC_GetSR(uint32_t mask); - -#endif /* #ifndef RTC_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtt/rtt.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtt/rtt.c deleted file mode 100644 index f225ad355..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtt/rtt.c +++ /dev/null @@ -1,136 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup rtt_module Working with RTT - * The RTT driver provides the interface to configure and use the RTT - * peripheral. - * - * The Real-time Timer is used to count elapsed seconds.\n - * This timer is clocked by the 32kHz system clock divided by a programmable - * 16-bit balue. To be accurate, it is better to use an - * external 32kHz crystal instead of the internal 32kHz RC.\n - * - * To count elapsed seconds, the user could follow these few steps: - *
    - *
  • Programming PTPRES in RTT_MR to feeding the timer with a 1Hz signal.
  • - *
  • Writing the bit RTTRST in RTT_MR to restart the timer with new settings.
  • - *
- * - * An alarm can be set to happen on second by setting alarm value in RTT_AR. - * Alarm occurence can be detected by polling or interrupt. - * - * For more accurate information, please look at the RTT section of the - * Datasheet. - * - * Related files :\n - * \ref rtt.c\n - * \ref rtt.h.\n - */ -/*@{*/ -/*@}*/ - -/** - * \file - * - * Implementation of Real Time Timer (RTT) controller. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -/* These headers were introduced in C99 by working group ISO/IEC JTC1/SC22/WG14. */ -#include - -#include "rtt.h" -#include - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Changes the prescaler value of the given RTT and restarts it. - * - * \note This function disables RTT interrupt sources. - * - * \param rtt Pointer to a Rtt instance. - * \param prescaler Prescaler value for the RTT. - */ -void RTT_SetPrescaler(Rtt *rtt, uint16_t prescaler) -{ - rtt->RTT_MR = (prescaler | RTT_MR_RTTRST); -} - -/** - * \brief Returns the current value of the RTT timer value. - * - * \param rtt Pointer to a Rtt instance. - */ -uint32_t RTT_GetTime(Rtt *rtt) -{ - return rtt->RTT_VR; -} - -/** - * \brief Enables the specified RTT interrupt sources. - * - * \param rtt Pointer to a Rtt instance. - * \param sources Bitmask of interrupts to enable. - */ -void RTT_EnableIT(Rtt *rtt, uint32_t sources) -{ - ASSERT((sources & 0x0004FFFF) == 0, - "RTT_EnableIT: Wrong sources value.\n\r"); - rtt->RTT_MR |= sources; -} - -/** - * \brief Returns the status register value of the given RTT. - * - * \param rtt Pointer to an Rtt instance. - */ -uint32_t RTT_GetStatus(Rtt *rtt) -{ - return rtt->RTT_SR; -} - -/** - * \brief Configures the RTT to generate an alarm at the given time. - * - * \param pRtt Pointer to an Rtt instance. - * \param time Alarm time. - */ -void RTT_SetAlarm(Rtt *pRtt, uint32_t time) -{ - SANITY_CHECK(time > 0); - - pRtt->RTT_AR = time - 1; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtt/rtt.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtt/rtt.h deleted file mode 100644 index 13d4b716d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/rtt/rtt.h +++ /dev/null @@ -1,80 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * \par Purpose - * - * Interface for Real Time Timer (RTT) controller. - * - * \par Usage - * - * -# Changes the prescaler value of the given RTT and restarts it - * using \ref RTT_SetPrescaler(). - * -# Get current value of the RTT using \ref RTT_GetTime(). - * -# Enables the specified RTT interrupt using \ref RTT_EnableIT(). - * -# Get the status register value of the given RTT using \ref RTT_GetStatus(). - * -# Configures the RTT to generate an alarm at the given time - * using \ref RTT_SetAlarm(). - */ - -#ifndef RTT_H -#define RTT_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -#ifndef AT91C_BASE_RTTC - #define AT91C_BASE_RTTC RTT -#endif - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void RTT_SetPrescaler(Rtt *rtt, uint16_t prescaler); - -extern uint32_t RTT_GetTime(Rtt *rtt); - -extern void RTT_EnableIT(Rtt *rtt, uint32_t sources); - -extern uint32_t RTT_GetStatus(Rtt *rtt); - -extern void RTT_SetAlarm(Rtt *pRtt, uint32_t time); - -#endif /* #ifndef RTT_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/at45d.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/at45d.c deleted file mode 100644 index 4a6088373..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/at45d.c +++ /dev/null @@ -1,253 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup at45d_module AT45 driver. - * The AT45 Dataflash driver is based on the corresponding AT45 driver. - * A AT45 instance has to be initialized using the Dataflash levle function - * AT45_Configure(). AT45 Dataflash can be automatically detected using - * the AT45_FindDevice() function. Then AT45 dataflash operations such as - * read, write and erase DF can be launched using AT45_SendCommand function - * with corresponding AT45 command set. - * - * \usage - *
    - *
  • Reads data from the At45 at the specified address using AT45D_Read().
  • - *
  • Writes data on the At45 at the specified address using AT45D_Write().
  • - *
  • Erases a page of data at the given address using AT45D_Erase().
  • - *
  • Poll until the At45 has completed of corresponding operations using - * AT45D_WaitReady().
  • - *
  • Retrieves and returns the At45 current using AT45D_GetStatus().
  • - *
- * Related files :\n - * \ref at45d.c\n - * \ref at45d.h.\n - */ - /*@{*/ - /*@}*/ - - -/** - * \file - * - * Implementation of At45 driver. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "spi_at45.h" -#include "at45d.h" -#include -#include - -/*---------------------------------------------------------------------------- - * Local functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Wait for transfer to finish calling the SPI driver ISR (interrupts are - * disabled). - * - * \param pAt45 Pointer to an AT45 driver instance. - */ -static void AT45D_Wait(At45 *pAt45) -{ - SANITY_CHECK(pAt45); - - /* Wait for transfer to finish*/ - while (AT45_IsBusy(pAt45)) { - - SPID_Handler(pAt45->pSpid); - } -} - -/*---------------------------------------------------------------------------- - * Global functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Waits for the At45 to be ready to accept new commands. - * - * \param pAt45 Pointer to an AT45 driver instance. - */ -void AT45D_WaitReady(At45 *pAt45) -{ - uint8_t ready = 0; - - SANITY_CHECK(pAt45); - /* Poll device until it is ready.*/ - while (!ready) { - ready = AT45_STATUS_READY(AT45D_GetStatus(pAt45)); - } -} - -/** - * \brief Retrieves and returns the At45 current status, or 0 if an error happened. - * - * \param pAt45 Pointer to an AT45 driver instance. - */ -uint8_t AT45D_GetStatus(At45 *pAt45) -{ - uint8_t error; - uint8_t status; - - SANITY_CHECK(pAt45); - - /* Issue a status register read command*/ - error = AT45_SendCommand(pAt45, AT45_STATUS_READ, 1, &status, 1, 0, 0, 0); - ASSERT(!error, "-F- AT45_GetStatus: Failed to issue command.\n\r"); - - /* Wait for command to terminate*/ - while (AT45_IsBusy(pAt45)) { - AT45D_Wait(pAt45); - } - return status; -} - -/** - * \brief Reads data from the At45 inside the provided buffer. Since a continuous - * read command is used, there is no restriction on the buffer size and read address. - * - * \param pAt45 Pointer to an AT45 driver instance. - * \param pBuffer Data buffer. - * \param size Number of bytes to read. - * \param address Address at which data shall be read. - */ -void AT45D_Read( - At45 *pAt45, - uint8_t *pBuffer, - uint32_t size, - uint32_t address) -{ - uint8_t error; - - SANITY_CHECK(pAt45); - SANITY_CHECK(pBuffer); - - /* Issue a continuous read array command.*/ - error = AT45_SendCommand(pAt45, AT45_CONTINUOUS_READ_LEG, 8, pBuffer, size, address, 0, 0); - ASSERT(!error, "-F- AT45_Read: Failed to issue command\n\r"); - - /* Wait for the read command to execute.*/ - while (AT45_IsBusy(pAt45)) { - - AT45D_Wait(pAt45); - } -} - -/** - * \brief Writes data on the At45 at the specified address. Only one page of - * data is written that way; if the address is not at the beginning of the - * page, the data is written starting from this address and wraps around to - * the beginning of the page. - * \param pAt45 Pointer to an AT45 driver instance. - * \param pBuffer Data buffer. - * \param size Number of bytes to write. - * \param address Destination address on the At45. - */ -void AT45D_Write( - At45 *pAt45, - uint8_t *pBuffer, - uint32_t size, - uint32_t address) -{ - uint8_t error; - - SANITY_CHECK(pAt45); - SANITY_CHECK(pBuffer); - SANITY_CHECK(size <= pAt45->pDesc->pageSize); - - /* Issue a page write through buffer 1 command. */ - error = AT45_SendCommand(pAt45, AT45_PAGE_WRITE_BUF1, 4, pBuffer, size, address, 0, 0); - ASSERT(!error, "-F- AT45_Write: Could not issue command.\n\r"); - - /* Wait until the command is sent. */ - while (AT45_IsBusy(pAt45)) { - - AT45D_Wait(pAt45); - } - - /* Wait until the At45 becomes ready again.*/ - AT45D_WaitReady(pAt45); -} - -/** - * \brief Erases a page of data at the given address in the At45. - * - * \param pAt45 Pointer to an AT45 driver instance. - * \param address Address of page to erase. - */ -void AT45D_Erase(At45 *pAt45, uint32_t address) -{ - uint8_t error; - - SANITY_CHECK(pAt45); - - /* Issue a page erase command. */ - error = AT45_SendCommand(pAt45, AT45_PAGE_ERASE, 4, 0, 0, address, 0, 0); - ASSERT(!error, "-F- AT45_Erase: Could not issue command.\n\r"); - - /* Wait for end of transfer. */ - while (AT45_IsBusy(pAt45)) { - - AT45D_Wait(pAt45); - } - - /* Poll until the At45 has completed the erase operation.*/ - AT45D_WaitReady(pAt45); -} - -/** - * \brief Configure power-of-2 binary page size in the At45. - * - * \param pAt45 Pointer to an AT45 driver instance. - */ -void AT45D_BinaryPage(At45 *pAt45) -{ - uint8_t error; - uint8_t opcode[3]= {AT45_BINARY_PAGE}; - SANITY_CHECK(pAt45); - - /* Issue a binary page command. */ - - error = AT45_SendCommand(pAt45, AT45_BINARY_PAGE_FIRST_OPCODE, 1, opcode, 3, 0, 0, 0); - - ASSERT(!error, "-F- AT45_Erase: Could not issue command.\n\r"); - - /* Wait for end of transfer.*/ - while (AT45_IsBusy(pAt45)) { - - AT45D_Wait(pAt45); - } - - /* Wait until the At45 becomes ready again.*/ - AT45D_WaitReady(pAt45); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/at45d.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/at45d.h deleted file mode 100644 index 31a06ab66..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/at45d.h +++ /dev/null @@ -1,72 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of At45 driver. - * - */ - - -#ifndef AT45D_H -#define AT45D_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "spi_at45.h" - -/*---------------------------------------------------------------------------- - * Global functions - *----------------------------------------------------------------------------*/ - -extern void AT45D_WaitReady(At45 *pAt45); - -extern uint8_t AT45D_GetStatus(At45 *pAt45); - -extern void AT45D_Read( - At45 *pAt45, - uint8_t *pBuffer, - uint32_t size, - uint32_t address); - -extern void AT45D_Write( - At45 *pAt45, - uint8_t *pBuffer, - uint32_t size, - uint32_t address); - -extern void AT45D_Erase(At45 *pAt45, uint32_t address); - -extern void AT45D_BinaryPage(At45 *pAt45); - -#endif //#ifndef AT45D_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_at45.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_at45.c deleted file mode 100644 index 679a7d787..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_at45.c +++ /dev/null @@ -1,311 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup spi_at45_module SPI AT45 driver. - * The Dataflash driver is based on top of the corresponding Spi driver. - * A Dataflash structure instance has to be initialized using the DF_Init - * function. Then basic dataflash operations can be launched using macros such - * as DF_continuous_read. These macros invoke the DF_Command() function which - * invokes the DPI low driver using the SPI_SendCommand() function. - * Beware to compute the dataflash internal address, the dataflash sector - * description must be known (DataflashDesc). Dataflash can be automatically - * detected using the DF_Scan() function. - * - * \usage - *
    - *
  • Initializes an AT45 instance and configures SPI chip select pin - * using AT45_Configure().
  • - *
  • Detect DF and returns DF description corresponding to the device - * connected using AT45_FindDevice().This function shall be called by - * the application before AT45_SendCommand.
  • - *
  • Sends a command to the DF through the SPI using AT45_SendCommand(). - * The command is identified by its command code and the number of - * bytes to transfer.
  • - *
  • Example code for sending command to write a page to DF.
  • - * \code - * // Issue a page write through buffer 1 command - * error = AT45_SendCommand(pAt45, AT45_PAGE_WRITE_BUF1, 4, - * pBuffer, size, address, 0, 0); - * \endcode - *
  • Example code for sending command to read a page from DF. - * If data needs to be received, then a data buffer must be - * provided.
  • - * \code - * // Issue a continuous read array command - * error = AT45_SendCommand(pAt45, AT45_CONTINUOUS_READ_LEG, 8, - * pBuffer, size, address, 0, 0); - * \endcode - *
  • This function does not block; its optional callback will - * be invoked when the transfer completes.
  • - *
  • Check the AT45 driver is ready or not by polling AT45_IsBusy(). - *
- * Related files :\n - * \ref spi_at45.c\n - * \ref spi_at45.h.\n -*/ -/*@{*/ -/*@}*/ - - -/** - * \file - * - * Implementation of SPI At45 driver. - * - */ - - - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "spi_at45.h" -#include -#include -#include - -/*---------------------------------------------------------------------------- - * Internal definitions - *----------------------------------------------------------------------------*/ - -/** Number of dataflash which can be recognized.*/ -#define NUMDATAFLASH (sizeof(at45Devices) / sizeof(At45Desc)) - -/*---------------------------------------------------------------------------- - * Local variables - *----------------------------------------------------------------------------*/ - -/** indicate if the device is configured as binary page or not.*/ -static uint8_t configuredBinaryPage; - -/** At45 device descriptor structure. */ -static const At45Desc at45Devices[] = { - { 512, 1, 264, 9, 0x0C, "AT45DB011D"}, - { 1024, 1, 264, 9, 0x14, "AT45DB021D"}, - { 2048, 1, 264, 9, 0x1C, "AT45DB041D"}, - { 4096, 1, 264, 9, 0x24, "AT45DB081D"}, - { 4096, 1, 528, 10, 0x2C, "AT45DB161D"}, - { 8192, 1, 528, 10, 0x34, "AT45DB321D"}, - { 8192, 1, 1056, 11, 0x3C, "AT45DB642D"}, - {16384, 1, 1056, 11, 0x10, "AT45DB1282"}, - {16384, 1, 2112, 12, 0x18, "AT45DB2562"}, - {32768, 1, 2112, 12, 0x20, "AT45DB5122"} -}; - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Initializes an AT45 instance and configures SPI chip select register. - * - * \param pAt45 Pointer to the At45 instance to initialize. - * \param pSpid Pointer to the underlying SPI driver. - * \param spiCs Chip select value to connect to the At45. - * \return 0. - */ -uint8_t AT45_Configure(At45 *pAt45, Spid *pSpid, uint8_t spiCs) -{ - SpidCmd *pCommand; - - /* Sanity checks */ - ASSERT(pSpid, "AT45_Configure: pSpid is 0.\n\r"); - ASSERT(pAt45, "AT45_Configure: pAt45 is 0.\n\r"); - - /* Initialize the At45 instance */ - pAt45->pSpid = pSpid; - pAt45->pDesc = 0; - memset(pAt45->pCmdBuffer, 0, 8); - - /* Initialize the spidCmd structure*/ - pCommand = &(pAt45->command); - pCommand->pCmd = pAt45->pCmdBuffer; - pCommand->callback = 0; - pCommand->pArgument = 0; - pCommand->spiCs = spiCs; - - return 0; -} - -/** - * \brief Check if the At45 driver is in busy. - * - * \param pAt45 Pointer to the At45 instance to initialize. - * \return 1 if the At45 driver is not executing any command,otherwise it returns 0. - */ -uint8_t AT45_IsBusy(At45 *pAt45) -{ - return SPID_IsBusy(pAt45->pSpid); -} - -/** - * \brief Sends a command to the dataflash through the SPI. - * The command is identified by its command code and the number of bytes to transfer - * (1 + number of address bytes + number of dummy bytes).If data needs to be received, - * then a data buffer must be provided. - * \note This function does not block; its optional callback will be invoked when - * the transfer completes. - * \param pAt45 Pointer to the At45 instance to initialize. - * \param cmd Command code. - * \param cmdSize Size of command code + address bytes + dummy bytes. - * \param pData Data buffer. - * \param dataSize Number of data bytes to send/receive. - * \param address Address at which the command is performed if meaningful. - * \param callback Optional callback to invoke at end of transfer. - * \param pArgument Optional parameter to the callback function. - * \return 0. - */ -uint8_t AT45_SendCommand( - At45 *pAt45, - uint8_t cmd, - uint8_t cmdSize, - uint8_t *pData, - uint32_t dataSize, - uint32_t address, - SpidCallback callback, - void *pArgument) -{ - SpidCmd *pCommand; - const At45Desc *pDesc = pAt45->pDesc; - uint32_t dfAddress = 0; - - /* Sanity checks*/ - ASSERT(pAt45, "AT45_Command: pAt45 is 0.\n\r"); - ASSERT(pDesc || (cmd == AT45_STATUS_READ), - "AT45_Command: Device has no descriptor, only STATUS_READ command allowed\n\r"); - - /* Check if the SPI driver is available*/ - if (AT45_IsBusy(pAt45)) { - - return AT45_ERROR_LOCK; - } - - /* Compute command pattern*/ - pAt45->pCmdBuffer[0] = cmd; - - /* Add address bytes if necessary*/ - if (cmdSize > 1) { - - ASSERT(pDesc, "AT45_Command: No descriptor for dataflash.\n\r"); - if (!configuredBinaryPage) { - dfAddress = - ((address / (pDesc->pageSize)) << pDesc->pageOffset) - + (address % (pDesc->pageSize)); - } - else { - dfAddress = address; - } - /* Write address bytes*/ - if (pDesc->pageNumber >= 16384) { - - pAt45->pCmdBuffer[1] = ((dfAddress & 0x0F000000) >> 24); - pAt45->pCmdBuffer[2] = ((dfAddress & 0x00FF0000) >> 16); - pAt45->pCmdBuffer[3] = ((dfAddress & 0x0000FF00) >> 8); - pAt45->pCmdBuffer[4] = ((dfAddress & 0x000000FF) >> 0); - - if ((cmd != AT45_CONTINUOUS_READ) && (cmd != AT45_PAGE_READ)) { - - cmdSize++; - } - } - else { - - pAt45->pCmdBuffer[1] = ((dfAddress & 0x00FF0000) >> 16); - pAt45->pCmdBuffer[2] = ((dfAddress & 0x0000FF00) >> 8); - pAt45->pCmdBuffer[3] = ((dfAddress & 0x000000FF) >> 0); - } - } - - /* Update the SPI Transfer descriptors*/ - pCommand = &(pAt45->command); - pCommand->cmdSize = cmdSize; - pCommand->pData = pData; - pCommand->dataSize = dataSize; - pCommand->callback = callback; - pCommand->pArgument = pArgument; - - /* Send Command and data through the SPI*/ - if (SPID_SendCommand(pAt45->pSpid, pCommand)) { - - return AT45_ERROR_SPI; - } - - return 0; -} - -/** - * \brief returns the At45Desc structure corresponding to the device connected. - * It automatically initializes pAt45->pDesc field structure. - * \note This function shall be called by the application before AT45_SendCommand. - * \param pAt45 Pointer to the At45 instance to initialize. - * \param status Device status register value. - * \return 0 if successful; Otherwise, returns AT45_ERROR_LOCK if the At45 - * driver is in use or AT45_ERROR_SPI if there was an error with the SPI driver. - */ -const At45Desc * AT45_FindDevice(At45 *pAt45, uint8_t status) -{ - uint32_t i; - uint8_t id = AT45_STATUS_ID(status); - - /* Check if status is all one; in which case, it is assumed that no device is connected*/ - if (status == 0xFF) { - - return 0; - } - - /* Look in device array */ - i = 0; - pAt45->pDesc = 0; - while ((i < NUMDATAFLASH) && !(pAt45->pDesc)) { - - if (at45Devices[i].id == id) { - - pAt45->pDesc = &(at45Devices[i]); - } - i++; - } - configuredBinaryPage = AT45_STATUS_BINARY(status); - return pAt45->pDesc; -} - -/** - * \brief returns the pagesize corresponding to the device connected. - * \param pAt45 Pointer to the At45 instance to initialize. - * \param status Device status register value. - * \return page size. - */ -uint32_t AT45_PageSize(At45 *pAt45) -{ - uint32_t pagesize = pAt45->pDesc->pageSize; - if(((pAt45->pDesc->hasBinaryPage) == 0) || !configuredBinaryPage){ - return pagesize; - } - return ((pagesize >> 8) << 8); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_at45.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_at45.h deleted file mode 100644 index fc1fca4e7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_at45.h +++ /dev/null @@ -1,202 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of SPI At45 driver. - * - */ - -#ifndef SPI_AT45_H -#define SPI_AT45_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include "spi_pdc.h" - -/*---------------------------------------------------------------------------- - * Macros - *----------------------------------------------------------------------------*/ -/** Returns 1 if the device is ready; otherwise 0.*/ -#define AT45_STATUS_READY(status) (status & 0x80) -/** Returns the device ID code.*/ -#define AT45_STATUS_ID(status) (status & 0x3c) -/** Returns 1 if the device is configured in binary page mode; otherwise 0.*/ -#define AT45_STATUS_BINARY(status) (status & 0x01) - -#define AT45_PageOffset(pAt45) ((pAt45)->pDesc->pageOffset) -#define AT45_PageNumber(pAt45) ((pAt45)->pDesc->pageNumber) - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -/** The dataflash driver is currently in use.*/ -#define AT45_ERROR_LOCK 1 -/** There was an error with the SPI driver.*/ -#define AT45_ERROR_SPI 2 - -/** AT45 dataflash SPI CSR settings given MCK and SPCK.*/ -#define AT45_CSR(mck, spck) (SPI_CSR_NCPHA | SPID_CSR_DLYBCT(mck, 250) | SPID_CSR_DLYBS(mck, 250) | SPID_CSR_SCBR(mck, spck)) - -/** Main memory page read command code. */ -#define AT45_PAGE_READ 0xD2 -/** Continous array read (legacy) command code.*/ -#define AT45_CONTINUOUS_READ_LEG 0xE8 -/** Continous array read (low frequency) command code.*/ -#define AT45_CONTINUOUS_READ_LF 0x03 -/** Continous array read command code.*/ -#define AT45_CONTINUOUS_READ 0x0B -/** Buffer 1 read (low frequency) command code.*/ -#define AT45_BUF1_READ_LF 0xD1 -/** Buffer 2 read (low frequency) command code.*/ -#define AT45_BUF2_READ_LF 0xD3 -/** Buffer 1 read (serial) command code.*/ -#define AT45_BUF1_READ_SER 0xD4 -/** Buffer 2 read (serial) command code.*/ -#define AT45_BUF2_READ_SER 0xD6 -/** Buffer 1 read (8-bit) command code.*/ -#define AT45_BUF1_READ_8B 0x54 -/** Buffer 2 read (8-bit) command code.*/ -#define AT45_BUF2_READ_8B 0x56 - -/** Buffer 1 write command code.*/ -#define AT45_BUF1_WRITE 0x84 -/** Buffer 2 write command code.*/ -#define AT45_BUF2_WRITE 0x87 -/** Buffer 1 to main memory page program with erase command code.*/ -#define AT45_BUF1_MEM_ERASE 0x83 -/** Buffer 2 to main memory page program with erase command code.*/ -#define AT45_BUF2_MEM_ERASE 0x86 -/** Buffer 1 to main memory page program without erase command code.*/ -#define AT45_BUF1_MEM_NOERASE 0x88 -/** Buffer 2 to main memory page program without erase command code.*/ -#define AT45_BUF2_MEM_NOERASE 0x89 -/** Page erase command code.*/ -#define AT45_PAGE_ERASE 0x81 -/** Block erase command code.*/ -#define AT45_BLOCK_ERASE 0x50 -/** Sector erase command code.*/ -#define AT45_SECTOR_ERASE 0x7C -/** Chip erase command code.*/ -#define AT45_CHIP_ERASE 0xC7, 0x94, 0x80, 0x9A -/** Main memory page program through buffer 1 command code.*/ -#define AT45_PAGE_WRITE_BUF1 0x82 -/** Main memory page program through buffer 2 command code.*/ -#define AT45_PAGE_WRITE_BUF2 0x85 - -/** Main memory page to buffer 1 transfer command code.*/ -#define AT45_PAGE_BUF1_TX 0x53 -/** Main memory page to buffer 2 transfer command code.*/ -#define AT45_PAGE_BUF2_TX 0x55 -/** Main memory page to buffer 1 compare command code.*/ -#define AT45_PAGE_BUF1_CMP 0x60 -/** Main memory page to buffer 2 compare command code.*/ -#define AT45_PAGE_BUF2_CMP 0x61 -/** Auto page rewrite through buffer 1 command code.*/ -#define AT45_AUTO_REWRITE_BUF1 0x58 -/** Auto page rewrite through buffer 2 command code.*/ -#define AT45_AUTO_REWRITE_BUF2 0x59 -/** Deep power-down command code.*/ -#define AT45_DEEP_PDOWN 0xB9 -/** Resume from deep power-down command code.*/ -#define AT45_RES_DEEP_PDOWN 0xAB -/** Status register read command code.*/ -#define AT45_STATUS_READ 0xD7 -/** Manufacturer and device ID read command code.*/ -#define AT45_ID_READ 0x9F - -/** Power-of-2 binary page size configuration command code.*/ -#define AT45_BINARY_PAGE_FIRST_OPCODE 0x3D -#define AT45_BINARY_PAGE 0x2A, 0x80, 0xA6 - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - -/** Dataflash description. A constant array of DataflashDesc instance is defined - in at45.c. The DF_Scan() function returns the corresponding descriptor according - to the dataflash ID detected. This description (page_size, page_offset) is used - to compute the internal dataflash address by the DF_Command() function. */ -typedef struct { - /** dataflash page number. */ - uint32_t pageNumber; - // indicate if power-of-2 binary page supported.*/ - uint32_t hasBinaryPage; - /** dataflash page size.*/ - uint32_t pageSize; - /** page offset in command.*/ - uint32_t pageOffset; - /** Dataflash ID.*/ - uint8_t id; - /** Identifier.*/ - const char *name; -} At45Desc; - -/** Dataflash driver structure. It holds the current command being processed. - This structure is initialized by the DF_Init() command. - pDfDesc field can be initialized by the DF_Scan() function. - cmdBuffer is a private driver area used to compute the dataflash address to - be sent to the dataflash. Beware the PDC master must have access to this area.*/ -typedef struct _Dataflash { - /** Pointer to Spi Structure (SPI low level driver).*/ - Spid *pSpid; - /** Current SPI command sent to the SPI low level driver.*/ - SpidCmd command; - /** Pointer to the dataflash description.*/ - const At45Desc *pDesc; - /** Buffer to store the current command (opcode + dataflash address.*/ - uint8_t pCmdBuffer[8]; -} At45; - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern uint8_t AT45_Configure(At45 *pAt45, Spid *pSpid, uint8_t spiCs); - -extern uint8_t AT45_IsBusy(At45 *pAt45); - -extern uint8_t AT45_SendCommand( - At45 *pAt45, - uint8_t cmd, - uint8_t cmdSize, - uint8_t *pData, - uint32_t dataSize, - uint32_t address, - SpidCallback callback, - void *pArgument); - -extern const At45Desc * AT45_FindDevice(At45 *pAt45, uint8_t status); - -extern uint32_t AT45_PageSize(At45 *pAt45); -#endif // #ifndef SPI_AT45_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_pdc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_pdc.c deleted file mode 100644 index d0998b041..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_pdc.c +++ /dev/null @@ -1,275 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup spi_pdc_module SPI PDC driver - * The Spi driver is a low level spi driver which performs SPI device Initializes, - * spi transfer and receive. It can be used by upper SPI driver such as AT45 - * driver and AT26 driver. - * - * \usage - *
    - *
  • Initializes a SPI instance and the corresponding SPI hardware, - * Configure SPI in Master Mode using SPID_Configure().
  • - *
  • Configures the SPI characteristics (such as Clock Polarity, Phase, - * transfers delay and Baud Rate) for the device corresponding to the - * chip select using SPID_ConfigureCS().
  • - *
  • Starts a SPI master transfer using SPID_SendCommand(). - * The transfer is performed using the PDC channels.
  • - *
  • It enable the SPI clock.
  • - *
  • Set the corresponding peripheral chip select.
  • - *
  • Initialize the two SPI PDC buffers.
  • - *
  • Initialize SPI_TPR and SPI_TCR with SPI command data and size - * to send command data first.
  • - *
  • Initialize SPI_RPR and SPI_RCR with SPI command data and size - * as dummy value.
  • - *
  • Initialize SPI_TNPR and SPI_TNCR with rest of the data to be - * transfered.(if the data specified in cmd structure)
  • - *
  • Initialize SPI_RNPR and SPI_RNCR with rest of the data to be - * received.(if the data specified in cmd structure)
  • - *
  • Initialize the callback function if specified.
  • - *
  • Enable transmitter and receiver.
  • - *
  • Example for sending a command to the dataflash through the SPI.
  • - * \code - * /// Build command to be sent. - * ... - * // Send Command and data through the SPI - * if (SPID_SendCommand(pAt45->pSpid, pCommand)) { - * return AT45_ERROR_SPI; - * } - * \endcode - *
  • The SPI_Handler() must be called by the SPI Interrupt Service Routine - * with the corresponding Spi instance. It is invokes to check for pending - * interrupts.
  • - *
  • Example for initializing SPI interrupt handler in upper application.
  • - * \code - * AIC_ConfigureIT(AT91C_ID_SPI, 0, SPI_Handler); - * \endcode - *
- * Related files :\n - * \ref spi_pdc.c\n - * \ref spi_pdc.h.\n -*/ -/*@{*/ -/*@}*/ - - -/** - * \file - * - * Implementation of SPI PDC driver. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "spi_pdc.h" -#include - -/*---------------------------------------------------------------------------- - * Macros - *----------------------------------------------------------------------------*/ - -/** Write PMC register*/ -#define WRITE_PMC(pPmc, regName, value) pPmc->regName = (value) - -/** Write SPI register*/ -#define WRITE_SPI(pSpi, regName, value) pSpi->regName = (value) - -/** Read SPI registers */ -#define READ_SPI(pSpi, regName) (pSpi->regName) - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Initializes the Spid structure and the corresponding SPI hardware. - * - * \param pSpid Pointer to a Spid instance. - * \param pSpiHw Associated SPI peripheral. - * \param spiId SPI peripheral identifier. - * \return 0. - */ -uint8_t SPID_Configure(Spid *pSpid, Spi *pSpiHw, uint8_t spiId) -{ - /* Initialize the SPI structure*/ - pSpid->pSpiHw = pSpiHw; - pSpid->spiId = spiId; - pSpid->semaphore = 1; - pSpid->pCurrentCommand = 0; - - /* Enable the SPI clock*/ - WRITE_PMC(PMC, PMC_PCER0, (1 << pSpid->spiId)); - - /* Execute a software reset of the SPI twice */ - WRITE_SPI(pSpiHw, SPI_CR, SPI_CR_SWRST); - WRITE_SPI(pSpiHw, SPI_CR, SPI_CR_SWRST); - - /* Configure SPI in Master Mode with No CS selected !!! */ - WRITE_SPI(pSpiHw, SPI_MR, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PCS); - - /* Enable the SPI*/ - WRITE_SPI(pSpiHw, SPI_CR, SPI_CR_SPIEN); - - /* Enable the SPI clock*/ - WRITE_PMC(PMC, PMC_PCDR0, (1 << pSpid->spiId)); - - return 0; -} - -/** - * \brief Configures the parameters for the device corresponding to the cs. - * - * \param pSpid Pointer to a Spid instance. - * \param cs number corresponding to the SPI chip select. - * \param csr SPI_CSR value to setup. - */ -void SPID_ConfigureCS(Spid *pSpid, uint8_t cs, uint32_t csr) -{ - Spi *pSpiHw = pSpid->pSpiHw; - WRITE_SPI(pSpiHw, SPI_CSR[cs], csr); -} - -/** - * \brief Starts a SPI master transfer. This is a non blocking function. It will - * return as soon as the transfer is started. - * - * \param pSpid Pointer to a Spid instance. - * \param pCommand Pointer to the SPI command to execute. - * \return 0 if the transfer has been started successfully; otherwise returns - * SPID_ERROR_LOCK is the driver is in use, or SPID_ERROR if the command is not - * valid. - */ -uint8_t SPID_SendCommand(Spid *pSpid, SpidCmd *pCommand) -{ - Spi *pSpiHw = pSpid->pSpiHw; - uint32_t spiMr; - - /* Try to get the dataflash semaphore */ - if (pSpid->semaphore == 0) { - - return SPID_ERROR_LOCK; - } - pSpid->semaphore--; - - /* Enable the SPI clock */ - WRITE_PMC(PMC, PMC_PCER0, (1 << pSpid->spiId)); - - /* Disable transmitter and receiver*/ - WRITE_SPI(pSpiHw, SPI_PTCR, SPI_PTCR_RXTDIS | SPI_PTCR_TXTDIS); - - /* Write to the MR register*/ - spiMr = READ_SPI(pSpiHw, SPI_MR); - spiMr |= SPI_MR_PCS; - spiMr &= ~((1 << pCommand->spiCs) << 16); - WRITE_SPI(pSpiHw, SPI_MR, spiMr); - - /* Initialize the two SPI PDC buffer*/ - WRITE_SPI(pSpiHw, SPI_RPR, (int) pCommand->pCmd); - WRITE_SPI(pSpiHw, SPI_RCR, pCommand->cmdSize); - WRITE_SPI(pSpiHw, SPI_TPR, (int) pCommand->pCmd); - WRITE_SPI(pSpiHw, SPI_TCR, pCommand->cmdSize); - - WRITE_SPI(pSpiHw, SPI_RNPR, (int) pCommand->pData); - WRITE_SPI(pSpiHw, SPI_RNCR, pCommand->dataSize); - WRITE_SPI(pSpiHw, SPI_TNPR, (int) pCommand->pData); - WRITE_SPI(pSpiHw, SPI_TNCR, pCommand->dataSize); - - /* Initialize the callback*/ - pSpid->pCurrentCommand = pCommand; - - /* Enable transmitter and receiver*/ - WRITE_SPI(pSpiHw, SPI_PTCR, SPI_PTCR_RXTEN | SPI_PTCR_TXTEN); - - /* Enable buffer complete interrupt*/ - WRITE_SPI(pSpiHw, SPI_IER, SPI_IER_RXBUFF); - - return 0; -} - - -/** - * \brief The SPI_Handler must be called by the SPI Interrupt Service Routine with the - * corresponding Spi instance. - * - * \note The SPI_Handler will unlock the Spi semaphore and invoke the upper application - * callback. - * \param pSpid Pointer to a Spid instance. - */ -void SPID_Handler(Spid *pSpid) -{ - SpidCmd *pSpidCmd = pSpid->pCurrentCommand; - Spi *pSpiHw = pSpid->pSpiHw; - volatile uint32_t spiSr; - - /* Read the status register*/ - spiSr = READ_SPI(pSpiHw, SPI_SR); - if (spiSr & SPI_SR_RXBUFF) { - - /* Disable transmitter and receiver */ - WRITE_SPI(pSpiHw, SPI_PTCR, SPI_PTCR_RXTDIS | SPI_PTCR_TXTDIS); - - /* Disable the SPI clock*/ - WRITE_PMC(PMC, PMC_PCDR0, (1 << pSpid->spiId)); - - /* Disable buffer complete interrupt */ - WRITE_SPI(pSpiHw, SPI_IDR, SPI_IDR_RXBUFF); - - /* Release the dataflash semaphore*/ - pSpid->semaphore++; - - /* Invoke the callback associated with the current command*/ - if (pSpidCmd && pSpidCmd->callback) { - - pSpidCmd->callback(0, pSpidCmd->pArgument); - } - - /* Nothing must be done after. A new DF operation may have been started - in the callback function.*/ - } -} - -/** - * \brief Returns 1 if the SPI driver is currently busy executing a command; otherwise - * returns 0. - * \param pSpid Pointer to a Spid instance. - */ -uint8_t SPID_IsBusy(const Spid *pSpid) -{ - if (pSpid->semaphore == 0) { - - return 1; - } - else { - - return 0; - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_pdc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_pdc.h deleted file mode 100644 index bace9efca..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi-flash/spi_pdc.h +++ /dev/null @@ -1,133 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of SPI PDC driver. - * - */ - -#ifndef SPI_PDC_H -#define SPI_PDC_H - - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -/** An unspecified error has occured.*/ -#define SPID_ERROR 1 - -/** SPI driver is currently in use.*/ -#define SPID_ERROR_LOCK 2 - -/*---------------------------------------------------------------------------- - * Macros - *----------------------------------------------------------------------------*/ - -/** Calculates the value of the SCBR field of the Chip Select Register given MCK and SPCK.*/ -#define SPID_CSR_SCBR(mck, spck) ((((mck) / (spck)) << 8) & SPI_CSR_SCBR) - -/** Calculates the value of the DLYBS field of the Chip Select Register given delay in ns and MCK.*/ -#define SPID_CSR_DLYBS(mck, delay) ((((((delay) * ((mck) / 1000000)) / 1000) + 1) << 16) & SPI_CSR_DLYBS) - -/** Calculates the value of the DLYBCT field of the Chip Select Register given delay in ns and MCK.*/ -#define SPID_CSR_DLYBCT(mck, delay) ((((((delay) / 32 * ((mck) / 1000000)) / 1000) + 1) << 24) & SPI_CSR_DLYBCT) - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - -/** SPI transfer complete callback.*/ -typedef void (*SpidCallback )(uint8_t, void *); - -/** Spi Transfer Request prepared by the application upper layer. This structure - is sent to the SPI_SendCommand function to start the transfer. At the end of - the transfer, the callback is invoked by the interrupt handler.*/ -typedef struct _SpidCmd { - - /** Pointer to the command data.*/ - uint8_t *pCmd; - /** Command size in bytes.*/ - uint8_t cmdSize; - /** Pointer to the data to be sent.*/ - uint8_t *pData; - /** Data size in bytes.*/ - unsigned short dataSize; - /** SPI chip select.*/ - uint8_t spiCs; - /** Callback function invoked at the end of transfer.*/ - SpidCallback callback; - /** Callback arguments.*/ - void *pArgument; - -} SpidCmd; - -/** Constant structure associated with SPI port. This structure prevents - client applications to have access in the same time.*/ -typedef struct { - - /** Pointer to SPI Hardware registers*/ - Spi *pSpiHw; - /** SPI Id as defined in the product datasheet*/ - char spiId; - /** Current SpiCommand being processed*/ - SpidCmd *pCurrentCommand; - /** Mutual exclusion semaphore.*/ - volatile char semaphore; - -} Spid; - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern uint8_t SPID_Configure( - Spid *pSpid, - Spi *pSpiHw, - uint8_t spiId); - -extern void SPID_ConfigureCS(Spid *pSpid, uint8_t cs, uint32_t csr); - -extern uint8_t SPID_SendCommand( - Spid *pSpid, - SpidCmd *pCommand); - -extern void SPID_Handler(Spid *pSpid); - -extern uint8_t SPID_IsBusy(const Spid *pSpid); - -#endif // #ifndef SPI_PDC_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi/spi.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi/spi.c deleted file mode 100644 index 4e6ba29a7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi/spi.c +++ /dev/null @@ -1,241 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup spi_module Working with SPI - * The SPI driver provides the interface to configure and use the SPI - * peripheral. - * - * The Serial Peripheral Interface (SPI) circuit is a synchronous serial - * data link that provides communication with external devices in Master - * or Slave Mode. - * - * To use the SPI, the user has to follow these few steps: - * -# Enable the SPI pins required by the application (see pio.h). - * -# Configure the SPI using the \ref SPI_Configure(). This enables the - * peripheral clock. The mode register is loaded with the given value. - * -# Configure all the necessary chip selects with \ref SPI_ConfigureNPCS(). - * -# Enable the SPI by calling \ref SPI_Enable(). - * -# Send/receive data using \ref SPI_Write() and \ref SPI_Read(). Note that \ref SPI_Read() - * must be called after \ref SPI_Write() to retrieve the last value read. - * -# Send/receive data using the PDC with the \ref SPI_WriteBuffer() and - * \ref SPI_ReadBuffer() functions. - * -# Disable the SPI by calling \ref SPI_Disable(). - * - * For more accurate information, please look at the SPI section of the - * Datasheet. - * - * Related files :\n - * \ref spi.c\n - * \ref spi.h.\n -*/ -/*@{*/ -/*@}*/ - -/** - * \file - * - * Implementation of Serial Peripheral Interface (SPI) controller. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include "spi.h" -#include "pmc/pmc.h" - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Enables a SPI peripheral. - * - * \param spi Pointer to an Spi instance. - */ -void SPI_Enable(Spi *spi) -{ - spi->SPI_CR = SPI_CR_SPIEN; -} - -/** - * \brief Disables a SPI peripheral. - * - * \param spi Pointer to an Spi instance. - */ -void SPI_Disable(Spi *spi) -{ - spi->SPI_CR = SPI_CR_SPIDIS; -} - -/** - * \brief Configures a SPI peripheral as specified. The configuration can be computed - * using several macros (see \ref spi_configuration_macros). - * - * \param spi Pointer to an Spi instance. - * \param id Peripheral ID of the SPI. - * \param configuration Value of the SPI configuration register. - */ -void SPI_Configure(Spi *spi, - uint32_t id, - uint32_t configuration) -{ - PMC_EnablePeripheral(ID_SPI); - spi->SPI_CR = SPI_CR_SPIDIS; - - /* Execute a software reset of the SPI twice */ - spi->SPI_CR = SPI_CR_SWRST; - spi->SPI_CR = SPI_CR_SWRST; - spi->SPI_MR = configuration; -} - -/** - * \brief Configures a chip select of a SPI peripheral. The chip select configuration - * is computed using several macros (see \ref spi_configuration_macros). - * - * \param spi Pointer to an Spi instance. - * \param npcs Chip select to configure (0, 1, 2 or 3). - * \param configuration Desired chip select configuration. - */ -void SPI_ConfigureNPCS(Spi *spi, - uint32_t npcs, - uint32_t configuration) -{ - spi->SPI_CSR[npcs] = configuration; -} - -/** - * \brief Sends data through a SPI peripheral. If the SPI is configured to use a fixed - * peripheral select, the npcs value is meaningless. Otherwise, it identifies - * the component which shall be addressed. - * - * \param spi Pointer to an Spi instance. - * \param npcs Chip select of the component to address (0, 1, 2 or 3). - * \param data Word of data to send. - */ -void SPI_Write(Spi *spi, uint32_t npcs, uint16_t data) -{ - /* Send data */ - while ((spi->SPI_SR & SPI_SR_TXEMPTY) == 0); - spi->SPI_TDR = data | SPI_PCS(npcs); - while ((spi->SPI_SR & SPI_SR_TDRE) == 0); -} - -/** - * \brief Sends the contents of buffer through a SPI peripheral, using the PDC to - * take care of the transfer. - * - * \param spi Pointer to an Spi instance. - * \param buffer Data buffer to send. - * \param length Length of the data buffer. - */ -uint8_t SPI_WriteBuffer(Spi *spi, - void *buffer, - uint32_t length) -{ - /* Check if first bank is free */ - if (spi->SPI_TCR == 0) { - - spi->SPI_TPR = (uint32_t) buffer; - spi->SPI_TCR = length; - spi->SPI_PTCR = PERIPH_PTCR_TXTEN; - return 1; - } - /* Check if second bank is free */ - else if (spi->SPI_TNCR == 0) { - - spi->SPI_TNPR = (uint32_t) buffer; - spi->SPI_TNCR = length; - return 1; - } - - /* No free banks */ - return 0; -} - -/** - * \brief Check if SPI transfer finish. - * - * \param spi Pointer to an Spi instance. - * - * \return Returns 1 if there is no pending write operation on the SPI; otherwise - * returns 0. - */ -uint8_t SPI_IsFinished(Spi *spi) -{ - return ((spi->SPI_SR & SPI_SR_TXEMPTY) != 0); -} - -/** - * \brief Reads and returns the last word of data received by a SPI peripheral. This - * method must be called after a successful SPI_Write call. - * - * \param spi Pointer to an Spi instance. - * - * \return readed data. - */ -uint16_t SPI_Read(Spi *spi) -{ - while ((spi->SPI_SR & SPI_SR_RDRF) == 0); - return spi->SPI_RDR & 0xFFFF; -} - -/** - * \brief Reads data from a SPI peripheral until the provided buffer is filled. This - * method does NOT need to be called after SPI_Write or SPI_WriteBuffer. - * - * \param spi Pointer to an Spi instance. - * \param buffer Data buffer to store incoming bytes. - * \param length Length in bytes of the data buffer. - */ -uint8_t SPI_ReadBuffer(Spi *spi, - void *buffer, - uint32_t length) -{ - /* Check if the first bank is free */ - if (spi->SPI_RCR == 0) { - - spi->SPI_RPR = (uint32_t) buffer; - spi->SPI_RCR = length; - spi->SPI_PTCR = PERIPH_PTCR_RXTEN; - return 1; - } - /* Check if second bank is free */ - else if (spi->SPI_RNCR == 0) { - - spi->SPI_RNPR = (uint32_t) buffer; - spi->SPI_RNCR = length; - return 1; - } - - /* No free bank */ - return 0; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi/spi.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi/spi.h deleted file mode 100644 index f78a34baf..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/spi/spi.h +++ /dev/null @@ -1,104 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for Serial Peripheral Interface (SPI) controller. - * - */ - -#ifndef SPI_H -#define SPI_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include - -/*---------------------------------------------------------------------------- - * Macros - *----------------------------------------------------------------------------*/ - -/** - * \page spi_configuration_macros SPI configuration macros - * - * This page lists several macros which should be used when configuring a SPI - * peripheral. - * - * \par Macros: - * - \ref SPI_PCS - * - \ref SPI_SCBR - * - \ref SPI_DLYBS - * - \ref SPI_DLYBCT - */ - -/** Calculate the PCS field value given the chip select NPCS value */ -#define SPI_PCS(npcs) ((~(1 << npcs) & 0xF) << 16) - -/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */ -#define SPI_SCBR(baudrate, masterClock) \ - ((uint32_t) (masterClock / baudrate) << 8) - -/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */ -#define SPI_DLYBS(delay, masterClock) \ - ((uint32_t) (((masterClock / 1000000) * delay) / 1000) << 16) - -/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */ -#define SPI_DLYBCT(delay, masterClock) \ - ((uint32_t) (((masterClock / 1000000) * delay) / 32000) << 24) -/*------------------------------------------------------------------------------ */ - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void SPI_Enable(Spi *spi); -extern void SPI_Disable(Spi *spi); -extern void SPI_Configure(Spi *spi, - uint32_t id, - uint32_t configuration); -extern void SPI_ConfigureNPCS(Spi *spi, - uint32_t npcs, - uint32_t configuration); -extern void SPI_Write(Spi *spi, uint32_t npcs, uint16_t data); -extern uint8_t SPI_WriteBuffer(Spi *spi, - void *buffer, - uint32_t length); - -extern uint8_t SPI_IsFinished(Spi *pSpi); - -extern uint16_t SPI_Read(Spi *spi); -extern uint8_t SPI_ReadBuffer(Spi *spi, - void *buffer, - uint32_t length); - -#endif /* #ifndef SPI_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/ssc/ssc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/ssc/ssc.c deleted file mode 100644 index 3fb0cc045..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/ssc/ssc.c +++ /dev/null @@ -1,248 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup ssc module Working with SSC - * The SSC driver provides the interface to configure and use the SSC - * peripheral. - * - * !Usage - * - * -# Enable the SSC interface pins. - * -# Configure the SSC to operate at a specific frequency by calling - * SSC_Configure(). This function enables the peripheral clock of the SSC, - * but not its PIOs. - * -# Configure the transmitter and/or the receiver using the - * SSC_ConfigureTransmitter() and SSC_ConfigureEmitter() functions. - * -# Enable the PIOs or the transmitter and/or the received. - * -# Enable the transmitter and/or the receiver using SSC_EnableTransmitter() - * and SSC_EnableReceiver() - * -# Send data through the transmitter using SSC_Write() and SSC_WriteBuffer() - * -# Receive data from the receiver using SSC_Read() and SSC_ReadBuffer() - * -# Disable the transmitter and/or the receiver using SSC_DisableTransmitter() - * and SSC_DisableReceiver() - * - * For more accurate information, please look at the RTC section of the - * Datasheet. - * - * Related files :\n - * \ref ssc.c\n - * \ref ssc.h.\n -*/ -/*@{*/ -/*@}*/ - - -/** - * \file - * - * Implementation of Synchronous Serial (SSC) controller. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include "ssc.h" - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Configures a SSC peripheral.If the divided clock is not used, the master - * clock frequency can be set to 0. - * \note The emitter and transmitter are disabled by this function. - * \param bitRate bit rate. - * \param masterClock master clock. - */ -void SSC_Configure(uint32_t bitRate, uint32_t masterClock) -{ - /* Enable SSC peripheral clock */ - PMC->PMC_PCER0 = 1 << ID_SSC; - - /* Reset, disable receiver & transmitter */ - SSC->SSC_CR = SSC_CR_RXDIS | SSC_CR_TXDIS | SSC_CR_SWRST; - - SSC->SSC_PTCR = SSC_PTCR_RXTDIS | SSC_PTCR_TXTDIS; - /* Configure clock frequency */ - if (bitRate != 0) { - - SSC->SSC_CMR = masterClock / (2 * bitRate); - } - else { - - SSC->SSC_CMR = 0; - } -} - -/** - * \brief Configures the transmitter of a SSC peripheral. - * \param tcmr Transmit Clock Mode Register value. - * \param tfmr Transmit Frame Mode Register value. - */ -void SSC_ConfigureTransmitter(uint32_t tcmr, uint32_t tfmr) -{ - SSC->SSC_TCMR = tcmr; - SSC->SSC_TFMR = tfmr; -} - -/** - * \brief Configures the receiver of a SSC peripheral. - * \param rcmr Receive Clock Mode Register value. - * \param rfmr Receive Frame Mode Register value. - */ -void SSC_ConfigureReceiver(uint32_t rcmr, uint32_t rfmr) -{ - SSC->SSC_RCMR = rcmr; - SSC->SSC_RFMR = rfmr; -} - -/** - * \brief Enables the transmitter of a SSC peripheral. - */ -void SSC_EnableTransmitter(void) -{ - SSC->SSC_CR = SSC_CR_TXEN; -} - -/** - * \brief Disables the transmitter of a SSC peripheral. - */ -void SSC_DisableTransmitter(void) -{ - SSC->SSC_CR = SSC_CR_TXDIS; -} - -/** - * \brief Enables the receiver of a SSC peripheral. - */ -void SSC_EnableReceiver(void) -{ - SSC->SSC_CR = SSC_CR_RXEN; -} - -/** - * \brief Disables the receiver of a SSC peripheral. - */ -void SSC_DisableReceiver(void) -{ - SSC->SSC_CR = SSC_CR_RXDIS; -} - -/** - * \brief Enables one or more interrupt sources of a SSC peripheral. - * \param Bitwise OR of selected interrupt sources. - */ -void SSC_EnableInterrupts(uint32_t sources) -{ - SSC->SSC_IER = sources; -} - -/** - * \brief Disables one or more interrupt sources of a SSC peripheral. - * \param Bitwise OR of selected interrupt sources. - */ -void SSC_DisableInterrupts(uint32_t sources) -{ - SSC->SSC_IDR = sources; -} - -/** - * \brief Sends one data frame through a SSC peripheral. If another frame is currently - * being sent, this function waits for the previous transfer to complete. - * \param frame Data frame to send. - */ -void SSC_Write(uint32_t frame) -{ - while ((SSC->SSC_SR & SSC_SR_TXRDY) == 0); - SSC->SSC_THR = frame; -} - -/** - * \brief Waits until one frame is received on a SSC peripheral, and returns it. - */ -uint32_t SSC_Read(void) -{ - while ((SSC->SSC_SR & SSC_SR_RXRDY) == 0); - return SSC->SSC_RHR; -} - -/** - * \brief Sends the contents of a data buffer a SSC peripheral, using the PDC. - * \param buffer Data buffer to send. - * \param length Size of the data buffer. - * \return 1 if the buffer has been queued for transmission; otherwise returns 0. - */ -uint8_t SSC_WriteBuffer(void *buffer, uint32_t length) -{ - /* Check if first bank is free*/ - if (SSC->SSC_TCR == 0) { - - SSC->SSC_TPR = (uint32_t) buffer; - SSC->SSC_TCR = length; - SSC->SSC_PTCR = SSC_PTCR_TXTEN; - return 1; - } - /* Check if second bank is free*/ - else if (SSC->SSC_TNCR == 0) { - - SSC->SSC_TNPR = (uint32_t) buffer; - SSC->SSC_TNCR = length; - return 1; - } - return 0; -} - -/** - * \brief Reads data coming from a SSC peripheral receiver and stores it into the - * giving buffer with PDC. - * \param buffer ata buffer used for reception. - * \param length Size of the data buffer. - * \return 1 if the buffer has been queued for reception; otherwise returns 0. - */ -uint8_t SSC_ReadBuffer(void *buffer, uint32_t length) -{ - /* Check if the first bank is free*/ - if (SSC->SSC_RCR == 0) { - - SSC->SSC_RPR = (uint32_t) buffer; - SSC->SSC_RCR = length; - SSC->SSC_PTCR = SSC_PTCR_RXTEN; - return 1; - } - /* Check if second bank is free*/ - else if (SSC->SSC_RNCR == 0) { - SSC->SSC_RNPR = (uint32_t) buffer; - SSC->SSC_RNCR = length; - return 1; - } - return 0; -} \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/ssc/ssc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/ssc/ssc.h deleted file mode 100644 index 1dd5185c6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/ssc/ssc.h +++ /dev/null @@ -1,58 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for Synchronous Serial (SSC) controller. - * - */ - -#ifndef SSC_H -#define SSC_H - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ -extern void SSC_Configure(uint32_t bitRate, uint32_t masterClock); -extern void SSC_ConfigureTransmitter(uint32_t tcmr, uint32_t tfmr); -extern void SSC_ConfigureReceiver(uint32_t rcmr, uint32_t rfmr); -extern void SSC_EnableTransmitter(void); -extern void SSC_DisableTransmitter(void); -extern void SSC_EnableReceiver(void); -extern void SSC_DisableReceiver(void); -extern void SSC_EnableInterrupts(uint32_t sources); -extern void SSC_DisableInterrupts(uint32_t sources); -extern void SSC_Write(uint32_t frame); -extern uint32_t SSC_Read(void); -extern uint8_t SSC_WriteBuffer(void *buffer, uint32_t length); -extern uint8_t SSC_ReadBuffer(void *buffer, uint32_t length); - -#endif //#ifndef SSC_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tc/tc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tc/tc.c deleted file mode 100644 index 70ed8fa34..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tc/tc.c +++ /dev/null @@ -1,148 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Headers - *------------------------------------------------------------------------------*/ - -#include "tc.h" - -/*------------------------------------------------------------------------------ - * Global functions - *------------------------------------------------------------------------------*/ - -/**------------------------------------------------------------------------------ - * \brief Configures a Timer Counter Channel - * Configures a Timer Counter to operate in the given mode. Timer is stopped - * after configuration and must be restarted with TC_Start(). All the - * interrupts of the timer are also disabled. - * \param pTc Pointer to an AT91S_TC instance. - * \param channel Channel number. - * \param mode Operating mode (TC_CMR value). - *------------------------------------------------------------------------------*/ -void TC_Configure(Tc *pTc, unsigned char channel, unsigned int mode) -{ - TcChannel *pTcCh = &pTc->TC_CHANNEL[channel]; - - /* Disable TC clock */ - pTcCh->TC_CCR = TC_CCR0_CLKDIS; - - /* Disable interrupts */ - pTcCh->TC_IDR = 0xFFFFFFFF; - - /* Clear status register */ - pTcCh->TC_SR; - - /* Set mode */ - pTcCh->TC_CMR = mode; -} - -/**------------------------------------------------------------------------------ - * \brief Reset and Start the TC Channel - * Enables the timer clock and performs a software reset to start the counting. - * \param pTc Pointer to an AT91S_TC instance. - * \param channel Channel number. - *------------------------------------------------------------------------------*/ -void TC_Start(Tc *pTc, unsigned char channel) -{ - TcChannel *pTcCh = &pTc->TC_CHANNEL[channel]; - pTcCh->TC_CCR = TC_CCR0_CLKEN | TC_CCR0_SWTRG; -} - -/**------------------------------------------------------------------------------ - * \brief Stop TC Channel - * Disables the timer clock, stopping the counting. - * \param pTc Pointer to an AT91S_TC instance. - * \param channel Channel number. - *------------------------------------------------------------------------------*/ -void TC_Stop(Tc *pTc, unsigned char channel) -{ - TcChannel *pTcCh = &pTc->TC_CHANNEL[channel]; - pTcCh->TC_CCR = TC_CCR0_CLKDIS; -} - -/**------------------------------------------------------------------------------ - * \brief Find best MCK divisor - * Finds the best MCK divisor given the timer frequency and MCK. The result - * is guaranteed to satisfy the following equation: - * \pre - * (MCK / (DIV * 65536)) <= freq <= (MCK / DIV) - * \endpre - * with DIV being the highest possible value. - * \param freq Desired timer frequency. - * \param mck Master clock frequency. - * \param div Divisor value. - * \param tcclks TCCLKS field value for divisor. - * \return 1 if a proper divisor has been found; otherwise 0. - *------------------------------------------------------------------------------*/ -unsigned char TC_FindMckDivisor( - unsigned int freq, - unsigned int mck, - unsigned int *div, - unsigned int *tcclks) -{ - const unsigned int divisors[5] = {2, 8, 32, 128,BOARD_MCK / 32768}; - - unsigned int index = 0; - - /* Satisfy lower bound */ - while (freq < ((mck / divisors[index]) / 65536)) { - - index++; - - /* If no divisor can be found, return 0 */ - if (index == 5) { - - return 0; - } - } - - /* Try to maximize DIV while satisfying upper bound */ - while (index < 4) { - - if (freq > (mck / divisors[index + 1])) { - - break; - } - index++; - } - - /* Store results */ - if (div) { - - *div = divisors[index]; - } - if (tcclks) { - - *tcclks = index; - } - - return 1; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tc/tc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tc/tc.h deleted file mode 100644 index 43cb83df8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tc/tc.h +++ /dev/null @@ -1,70 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/**------------------------------------------------------------------------------ - * \unit - * - * Purpose - * - * API for configuring and using Timer Counter (TC) peripherals. - * - * Usage - * -# Optionally, use TC_FindMckDivisor() to let the program find the best - * TCCLKS field value automatically. - * -# Configure a Timer Counter in the desired mode using TC_Configure(). - * -# Start or stop the timer clock using TC_Start() and TC_Stop(). - *------------------------------------------------------------------------------*/ - -#ifndef TC_H -#define TC_H - -/*------------------------------------------------------------------------------ - * Headers - *------------------------------------------------------------------------------*/ - -#include - -/*------------------------------------------------------------------------------ - * Global functions - *------------------------------------------------------------------------------*/ - -extern void TC_Configure(Tc *pTc, unsigned char ch, unsigned int mode); - -extern void TC_Start(Tc *pTc, unsigned char ch); - -extern void TC_Stop(Tc *pTc, unsigned char ch); - -extern unsigned char TC_FindMckDivisor( - unsigned int freq, - unsigned int mck, - unsigned int *div, - unsigned int *tcclks); - -#endif /* #ifndef TC_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd.h deleted file mode 100644 index 38f0d8df4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd.h +++ /dev/null @@ -1,69 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for touchscreen driver which includes touchscreen calibration, - * retrieving measurements etc. - * - * \par Usage - * - * -# Call TSD_Initialize() whenever the touchscreen should start the - * calibration process (as it is done in the function). - * -# Declare a global TSD_PenPressed function anywhere in your code. This - * function will get called every time the pen is pressed on the screen. - * -# Declare a global TSD_PenMoved function, which will get called whenever - * the pen stays in contact with the screen but changes position. - * -# Declare a global TSD_PenReleased function, which will be invoked as the - * pen is lifted from the screen. - */ - -#ifndef TSD_H -#define TSD_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "tsd_com.h" - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void TSD_Initialize(int8_t calEn); - -extern uint8_t TSD_Calibrate(void); - -extern void TSD_Reset(void); - -extern void TSD_TimerHandler(void); - -#endif /* #ifndef TSD_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_ads7843.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_ads7843.c deleted file mode 100644 index ee0fc869d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_ads7843.c +++ /dev/null @@ -1,302 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of ADS7843 driver. - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include -#include - -#ifdef BOARD_TSC_ADS7843 - -#include "tsd.h" -#include "tsd_com.h" -#include -#include -#include -#include -#include -#include -#include "tsd/tsd_ads7843.h" - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -/** Delay for pushbutton debouncing (the time-base is 10 ms). */ -#define DEBOUNCE_TIME 6 /* 10 * 6 = 60 ms */ - -/** Color of calibration points. */ -#define POINTS_COLOR 0x0000FF - -/** Size in pixels of calibration points. */ -#define POINTS_SIZE 4 - -/** Maximum difference in pixels between the test point and the measured point. */ -#define POINTS_MAX_ERROR 5 - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - -/** pen state */ -typedef enum { - STATE_PEN_RELEASED = 0, - STATE_PEN_PRESSED = 1, - STATE_PEN_DEBOUNCE = 2 -} e_pen_state; - -/*---------------------------------------------------------------------------- - * Local variables - *----------------------------------------------------------------------------*/ - -/** Pins used by Interrupt Signal for Touch Screen Controller */ -static const Pin pinPenIRQ = PIN_TCS_IRQ; - -/** Global timestamp in milliseconds since start of application. */ -static volatile uint32_t timestamp = 0; - -/** last time when the pen is pressed on the touchscreen */ -static volatile uint32_t timePress = 0; - -/** last time when the pen is released */ -static volatile uint32_t timeRelease = 0; - -/** pen state */ -static volatile e_pen_state penState = STATE_PEN_RELEASED; - -/** Touch screen initiallized flag */ -static uint32_t tsInitFlag = 0; - -/*---------------------------------------------------------------------------- - * Local functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Timer handler for touch screen. Increments the timestamp counter. - * Determine the state "Pen Pressed" or "Pen Released". To change state, - * the penIRQ has to keep the same value during DEBOUNCE_TIME. - * - * \note External timer interrupt should call it per 10ms. - */ -extern void TSD_TimerHandler( void ) -{ - uint32_t data[2]; - static uint32_t point[2]; - - if (!tsInitFlag) return; - - timestamp++; - /* Get the current position of the pen if penIRQ has low value (pen pressed) */ - if (PIO_Get(&pinPenIRQ) == 0) { - /* Get the current position of the pressed pen */ - if(TSDCom_IsCalibrationOk()) { - TSD_GetRawMeasurement(data); - TSDCom_InterpolateMeasurement(data, point); - } - - /* call the callback function */ - if(penState == STATE_PEN_PRESSED) { - if(TSDCom_IsCalibrationOk()) { - TSD_PenMoved(point[0], point[1]); - } - } - } - - /* Determine the pen state */ - if (PIO_Get(&pinPenIRQ) == 0) { - - /* reinit the last time when release */ - timeRelease = timestamp; - if(penState == STATE_PEN_DEBOUNCE) { - if( (timestamp - timePress) > DEBOUNCE_TIME) { - /* pen is pressed during an enough time : the state change */ - penState = STATE_PEN_PRESSED; - /* call the callback function */ - if(TSDCom_IsCalibrationOk()) { - TSD_PenPressed(point[0], point[1]); - } - } - } - } - else { - /* reinit the last time when release */ - timePress = timestamp; - - if(penState == STATE_PEN_DEBOUNCE) { - if( (timestamp - timeRelease) > DEBOUNCE_TIME) { - /* pen is released during an enough time : the state change */ - penState = STATE_PEN_RELEASED; - /* call the callback function */ - if(TSDCom_IsCalibrationOk()) { - TSD_PenReleased(point[0], point[1]); - } - } - } - } -} - -/** - * \breif Interrupt handler for Touchscreen. - */ -static void ISR_PenIRQ(void) -{ - /* Check if the pen has been pressed */ - if (!PIO_Get(&pinPenIRQ)) { - if(penState == STATE_PEN_RELEASED) { - - timePress = timestamp; - penState = STATE_PEN_DEBOUNCE; - } - } - else { - if(penState == STATE_PEN_PRESSED) { - - timeRelease = timestamp; - penState = STATE_PEN_DEBOUNCE; - } - } -} - -/** - * \brief Configure PENIRQ for interrupt. - */ -static void ConfigurePenIRQ(void) -{ - /* Configure pios */ - PIO_Configure(&pinPenIRQ, PIO_LISTSIZE(pinPenIRQ)); - - /* Initialize interrupts */ - PIO_InitializeInterrupts(0); - PIO_ConfigureIt(&pinPenIRQ, (void (*)(const Pin *)) ISR_PenIRQ); - - /* Enable the interrupt */ - PIO_EnableIt(&pinPenIRQ); -} - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Reads and store a touchscreen measurement in the provided array. - * - * \param pData Array where the measurements will be stored - */ -extern void TSD_GetRawMeasurement(uint32_t *pData) -{ - /* Get the current position of the pressed pen */ - PIO_DisableIt(&pinPenIRQ); - ADS7843_GetPosition(&pData[0], &pData[1]); - PIO_EnableIt(&pinPenIRQ); -} - -/** - * \brief Wait pen pressed. - */ -extern void TSD_WaitPenPressed( void ) -{ - /* Wait for touch & end of conversion */ - while (penState != STATE_PEN_RELEASED); - /*while (penState != STATE_PEN_PRESSED); */ - while (penState != STATE_PEN_PRESSED) { - } -} - -/** - * \brief Wait pen released. - */ -extern void TSD_WaitPenReleased( void ) -{ - /* Wait for contact loss */ - while (penState != STATE_PEN_PRESSED); - while (penState != STATE_PEN_RELEASED); -} - -/** - * \brief Do calibration. - * - * \return 1 if calibration is Ok, 0 else. - */ -uint8_t TSD_Calibrate(void) -{ - uint8_t ret = 0; - - /* Calibration is done only once */ - if(TSDCom_IsCalibrationOk()) { - return 1; - } - - /* Do calibration */ - ret = TSDCom_Calibrate(); - - return ret; -} - -/** - * \brief Initializes the touchscreen driver and starts the calibration process. When - * finished, the touchscreen is operational. - * - * \note Important: the LCD driver must have been initialized prior to calling this - * function. - */ -extern void TSD_Initialize( int8_t calEn ) -{ - ADS7843_Initialize(); - ConfigurePenIRQ(); - - tsInitFlag = 1; - - /* Calibration */ - if(calEn) { - while (!TSD_Calibrate()); - } -} - -/** - * \brief Stop the Touchscreen, disable interrupt. - */ -void TSD_Reset(void) -{ - /* Disable SPI 0 */ - ADS7843_Reset(); - - /* Disable the interrupt */ - PIO_DisableIt(&pinPenIRQ); -} - -#endif /* #ifdef BOARD_TSC_ADS7843 */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_ads7843.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_ads7843.h deleted file mode 100644 index 3f4bf2eff..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_ads7843.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef _TSD_ADS7843_ -#define _TSD_ADS7843_ - -/*---------------------------------------------------------------------------- - * External functions - *----------------------------------------------------------------------------*/ -extern void TSD_PenPressed( uint32_t dwX, uint32_t dwY ) ; -extern void TSD_PenMoved( uint32_t dwX, uint32_t dwY ) ; -extern void TSD_PenReleased( uint32_t dwX, uint32_t dwY ) ; - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ -extern void TSD_WaitPenPressed( void ) ; -extern void TSD_WaitPenReleased( void ) ; -extern void TSD_GetRawMeasurement( uint32_t *pData ) ; -extern void TSD_Initialize( int8_t calEn ) ; - - -#endif // _TSD_ADS7843_ \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_com.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_com.c deleted file mode 100644 index 2e0360fe9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_com.c +++ /dev/null @@ -1,380 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of touchscreen driver device irrelevance code. - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include - -#include "tsd.h" -#include -#include -#include -#include -#include -#include -#include -#include "tsd/tsd_ads7843.h" - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -/** Size in pixels of calibration points. */ -#define POINTS_SIZE 4 -/** Maximum difference in pixels between the test point and the measured point. */ -#define POINTS_MAX_ERROR 8 - -/** Delay at the end of calibartion for result display */ -#define DELAY_RESULT_DISPLAY 4000000 - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - -/** Point used during the touchscreen calibration process. */ -typedef struct _CalibrationPoint { - - /** Coordinate of point along the X-axis of the screen. */ - uint32_t x; - /** Coordinate of point along the Y-axis of the screen. */ - uint32_t y; - /** Calibration data of point. */ - uint32_t data[2]; - -} CalibrationPoint; - -/*---------------------------------------------------------------------------- - * Variables - *----------------------------------------------------------------------------*/ - -/** indicates if the touch screen has been calibrated. */ -/** If not, Callback functions are not called. */ -static volatile uint8_t bCalibrationOk = 1 ; //0; -/** Slope for interpoling touchscreen measurements along the X-axis. */ -static int32_t xSlope; -/** Slope for interpoling touchscreen measurements along the Y-axis. */ -static int32_t ySlope; - -/** Calibration points. */ -static CalibrationPoint calibrationPoints[] = { - - /* Top-left corner calibration point */ - { - BOARD_LCD_WIDTH / 10, - BOARD_LCD_HEIGHT / 10, - {0, 0} - }, - /* Top-right corner calibration point */ - { - BOARD_LCD_WIDTH - BOARD_LCD_WIDTH / 10, - BOARD_LCD_HEIGHT / 10, - {0, 0} - }, - /* Bottom-right corner calibration point */ - { - BOARD_LCD_WIDTH - BOARD_LCD_WIDTH / 10, - BOARD_LCD_HEIGHT - BOARD_LCD_HEIGHT / 10, - {0, 0} - }, - /* Bottom-left corner calibration point */ - { - BOARD_LCD_WIDTH / 10, - BOARD_LCD_HEIGHT - BOARD_LCD_HEIGHT / 10, - {0, 0} - } -}; - -/** Test point */ -static const CalibrationPoint testPoint = { - BOARD_LCD_WIDTH / 2, - BOARD_LCD_HEIGHT / 2, - {0, 0} -}; - -/*---------------------------------------------------------------------------- - * External functions - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - * Local functions - *----------------------------------------------------------------------------*/ - -/* - * \brief Display a calibration point on the given buffer. - * - * \param pPoint Calibration point to display. - */ -static void DrawCalibrationPoint(const CalibrationPoint *pPoint) -{ - LCDD_DrawRectangleWithFill(pPoint->x - POINTS_SIZE / 2, - pPoint->y - POINTS_SIZE / 2, - POINTS_SIZE, - POINTS_SIZE, - COLOR_RED); -} - -/** - * \brief Clears a calibration point from the given buffer. - * - * \param pPoint Calibration point to clear. - */ -static void ClearCalibrationPoint(const CalibrationPoint *pPoint) -{ - LCDD_DrawRectangleWithFill(pPoint->x - POINTS_SIZE / 2, - pPoint->y - POINTS_SIZE / 2, - POINTS_SIZE, - POINTS_SIZE, - COLOR_WHITE); -} - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \breif Indicates if the calibration of the touch screen is Ok. - * - * \return 1 calibration Ok, 0 if not. - */ -uint8_t TSDCom_IsCalibrationOk(void) -{ - if (bCalibrationOk == 1) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Interpolates the provided raw measurements using the previously calculated - * slope. The resulting x and y coordinates are stored in an array. - * - * \param pData Raw measurement data, as returned by TSD_GetRawMeasurement(). - * \param pPoint Array in which x and y will be stored. - */ -void TSDCom_InterpolateMeasurement(const uint32_t *pData, uint32_t *pPoint) -{ - pPoint[0] = calibrationPoints[0].x - - (((int32_t) calibrationPoints[0].data[0] - (int32_t) pData[0]) * 1024) - / xSlope; - - pPoint[1] = calibrationPoints[0].y - - (((int32_t) calibrationPoints[0].data[1] - (int32_t) pData[1]) * 1024) - / ySlope; - - if(pPoint[0] & 0x80000000) /* Is pPoint[0] negative ? */ - { - pPoint[0] = 0; - } - - if(pPoint[0] > BOARD_LCD_WIDTH) /* Is pPoint[0] bigger than the LCD width ? */ - { - pPoint[0] = BOARD_LCD_WIDTH; - } - - if(pPoint[1] & 0x80000000) /* Is pPoint[1] negative ? */ - { - pPoint[1] = 0; - } - - if(pPoint[1] > BOARD_LCD_HEIGHT) /* Is pPoint[1] bigger than the LCD width ? */ - { - pPoint[1] = BOARD_LCD_HEIGHT; - } -} - -/** - * \brief Performs the calibration process using the provided buffer to display - * information. - * - * \return True if calibration was successful; otherwise false. - */ -uint8_t TSDCom_Calibrate(void) -{ - volatile uint32_t i; /* to keep the tempo with gcc code optimisation */ - int32_t slope1, slope2; - CalibrationPoint measuredPoint; - uint8_t xOk, yOk; - int32_t xDiff, yDiff; - - /* Calibration setup */ - LCDD_Fill(COLOR_WHITE); - LCDD_DrawString(30, 50, (uint8_t *)"LCD calibration", COLOR_BLACK); - LCDD_DrawString(1, 140, (uint8_t *)"Touch the dots to\ncalibrate the screen", COLOR_DARKBLUE); - - /* Calibration points */ - for (i=0; i < 4; i++) { - - DrawCalibrationPoint(&calibrationPoints[i]); - - /* Wait for touch & end of conversion */ - TSD_WaitPenPressed(); - TSD_GetRawMeasurement(calibrationPoints[i].data); - ClearCalibrationPoint(&calibrationPoints[i]); - - /* Wait for contact loss */ - TSD_WaitPenReleased(); - } - - /** - * Calculate slopes using the calibration data - * Theory behind those calculations: - * - We suppose the touchscreen measurements are linear, so the following equations are true (simple - * linear regression) for any two 'a' and 'b' points of the screen: - * dx = (a.data[0] - b.data[0]) / (a.x - b.x) - * dy = (a.data[1] - b.data[1]) / (a.y - b.y) - * - * - We calculate dx and dy (called xslope and yslope here) using the calibration points. - * - * - We can then use dx and dy to infer the position of a point 'p' given the measurements performed - * by the touchscreen ('c' is any of the calibration points): - * dx = (p.data[0] - c.data[0]) / (p.x - c.x) - * dy = (p.data[1] - c.data[1]) / (p.y - c.y) - * Thus: - * p.x = c.x - (p.data[0] - c.data[0]) / dx - * p.y = c.y - (p.data[1] - c.data[1]) / dy - * - * - Since there are four calibration points, dx and dy can be calculated twice, so we average - * the two values. - */ - slope1 = ((int32_t) calibrationPoints[0].data[0]) - ((int32_t) calibrationPoints[1].data[0]); - slope1 *= 1024; - slope1 /= ((int32_t) calibrationPoints[0].x) - ((int32_t) calibrationPoints[1].x); - slope2 = ((int32_t) calibrationPoints[2].data[0]) - ((int32_t) calibrationPoints[3].data[0]); - slope2 *= 1024; - slope2 /= ((int32_t) calibrationPoints[2].x) - ((int32_t) calibrationPoints[3].x); - xSlope = (slope1 + slope2) / 2; - - slope1 = ((int32_t) calibrationPoints[0].data[1]) - ((int32_t) calibrationPoints[2].data[1]); - slope1 *= 1024; - slope1 /= ((int32_t) calibrationPoints[0].y) - ((int32_t) calibrationPoints[2].y); - slope2 = ((int32_t) calibrationPoints[1].data[1]) - ((int32_t) calibrationPoints[3].data[1]); - slope2 *= 1024; - slope2 /= ((int32_t) calibrationPoints[1].y) - ((int32_t) calibrationPoints[3].y); - ySlope = (slope1 + slope2) / 2; - - /* Test point */ - LCDD_Fill(0xFFFFFF); - LCDD_DrawString(30, 50, (uint8_t *)"LCD calibration", COLOR_BLACK); - LCDD_DrawString(1, 100, (uint8_t *)" Touch the point to\nvalidate calibration", COLOR_DARKBLUE); - DrawCalibrationPoint(&testPoint); - - /* Wait for touch & end of conversion */ - TSD_WaitPenPressed(); - - TSD_GetRawMeasurement(measuredPoint.data); - TSDCom_InterpolateMeasurement(measuredPoint.data, (uint32_t *) &measuredPoint); - DrawCalibrationPoint(&measuredPoint); - - /* Check resulting x and y */ - xDiff = (int32_t) measuredPoint.x - (int32_t) testPoint.x; - yDiff = (int32_t) measuredPoint.y - (int32_t) testPoint.y; - xOk = (xDiff >= -POINTS_MAX_ERROR) && (xDiff <= POINTS_MAX_ERROR); - yOk = (yDiff >= -POINTS_MAX_ERROR) && (yDiff <= POINTS_MAX_ERROR); - - /* Wait for contact loss */ - TSD_WaitPenReleased(); - - /* Check calibration result */ - if (xOk && yOk) { - - bCalibrationOk = 1; - LCDD_Fill(COLOR_WHITE); - LCDD_DrawString(30, 50, (uint8_t *)"LCD calibration", COLOR_BLACK); - LCDD_DrawString(80, 140, (uint8_t *)"Success !", COLOR_GREEN); - - } - else { - - bCalibrationOk = 0; - LCDD_Fill(COLOR_WHITE); - LCDD_DrawString(30, 50, (uint8_t *)"LCD calibration", COLOR_BLACK); - LCDD_DrawString(40, 140, (uint8_t *)"Error too big", COLOR_RED); - } - - /* Slight delay */ - for (i = 0; i < DELAY_RESULT_DISPLAY; i++); - - return (xOk && yOk); -} - -/** - * \brief Read calibrate data to buffer. - * - * \param pBuffer Data buffer. - * \param size Size of data buffer in bytes. - */ -void TSDCom_ReadCalibrateData(void *pBuffer, uint32_t size) -{ - uint8_t *pDest = (uint8_t *)pBuffer; - - SANITY_CHECK((sizeof(bCalibrationOk) + sizeof(xSlope) + - sizeof(ySlope) + sizeof(calibrationPoints[0].data)) < size); - - memcpy(pDest, (void const *)&bCalibrationOk, sizeof(bCalibrationOk)); - pDest += sizeof(bCalibrationOk); - memcpy(pDest, &xSlope, sizeof(xSlope)); - pDest += sizeof(xSlope); - memcpy(pDest, &ySlope, sizeof(ySlope)); - pDest += sizeof(ySlope); - memcpy(pDest, &calibrationPoints[0].data, sizeof(calibrationPoints[0].data)); - pDest += sizeof(calibrationPoints[0].data); -} - -/** - * \brief Restore calibrate data with buffer data. - * - * \param pBuffer Data buffer. - * \param size Size of data buffer in bytes. - */ -void TSDCom_RestoreCalibrateData(void *pBuffer, uint32_t size) -{ - uint8_t *pSrc = (uint8_t *)pBuffer; - - SANITY_CHECK((sizeof(bCalibrationOk) + sizeof(xSlope) + - sizeof(ySlope) + sizeof(calibrationPoints[0].data)) < size); - - memcpy((void *)&bCalibrationOk, pSrc, sizeof(bCalibrationOk)); - pSrc += sizeof(bCalibrationOk); - memcpy(&xSlope, pSrc, sizeof(xSlope)); - pSrc += sizeof(xSlope); - memcpy(&ySlope, pSrc, sizeof(ySlope)); - pSrc += sizeof(ySlope); - memcpy(&calibrationPoints[0].data, pSrc, sizeof(calibrationPoints[0].data)); - pSrc += sizeof(calibrationPoints[0].data); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_com.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_com.h deleted file mode 100644 index ca6f285d6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/tsd/tsd_com.h +++ /dev/null @@ -1,54 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for touchscreen driver device irrelevance code. - */ - -#ifndef TSD_COM_H -#define TSD_COM_H - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void TSDCom_InterpolateMeasurement( - const uint32_t *pData, - uint32_t *pPoint); - -uint8_t TSDCom_Calibrate(void); - -uint8_t TSDCom_IsCalibrationOk(void); - -void TSDCom_ReadCalibrateData(void *pBuffer, uint32_t size); -void TSDCom_RestoreCalibrateData(void *pBuffer, uint32_t size); - -#endif /* #ifndef TSD_COM_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twi.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twi.c deleted file mode 100644 index 5de7b2ee5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twi.c +++ /dev/null @@ -1,377 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup twi_module Working with TWI - * The TWI driver provides the interface to configure and use the TWI - * peripheral. - * - * \usage - *
    - *
  • Configures a TWI peripheral to operate in master mode, at the given - * frequency (in Hz) using TWI_Configure().
  • - *
  • Sends a STOP condition on the TWI using TWI_Stop().
  • - *
  • Starts a read operation on the TWI bus with the specified slave using - * TWI_StartRead(). Data must then be read using TWI_ReadByte() whenever - * a byte is available (poll using TWI_ByteReceived()).
  • - *
  • Starts a write operation on the TWI to access the selected slave using - * TWI_StartWrite(). A byte of data must be provided to start the write; - * other bytes are written next.
  • - *
  • Sends a byte of data to one of the TWI slaves on the bus using TWI_WriteByte(). - * This function must be called once before TWI_StartWrite() with the first byte of data - * to send, then it shall be called repeatedly after that to send the remaining bytes.
  • - *
  • Check if a byte has been received and can be read on the given TWI - * peripheral using TWI_ByteReceived().< - * Check if a byte has been sent using TWI_ByteSent().
  • - *
  • Check if the current transmission is complete (the STOP has been sent) - * using TWI_TransferComplete().
  • - *
  • Enables & disable the selected interrupts sources on a TWI peripheral - * using TWI_EnableIt() and TWI_DisableIt().
  • - *
  • Get current status register of the given TWI peripheral using - * TWI_GetStatus(). Get current status register of the given TWI peripheral, but - * masking interrupt sources which are not currently enabled using - * TWI_GetMaskedStatus().
  • - *
- * For more accurate information, please look at the TWI section of the - * Datasheet. - * - * Related files :\n - * \ref twi.c\n - * \ref twi.h.\n -*/ -/*@{*/ -/*@}*/ - - -/** - * \file - * - * Implementation of Two Wire Interface (TWI). - * - */ - - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include "twi.h" -#include -#include -#include - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Configures a TWI peripheral to operate in master mode, at the given - * frequency (in Hz). The duty cycle of the TWI clock is set to 50%. - * \param pTwi Pointer to an Twi instance. - * \param twck Desired TWI clock frequency. - * \param mck Master clock frequency. - */ -void TWI_ConfigureMaster(Twi *pTwi, uint32_t twck, uint32_t mck) -{ - uint32_t ckdiv = 0; - uint32_t cldiv; - uint8_t ok = 0; - - TRACE_DEBUG("TWI_ConfigureMaster()\n\r"); - SANITY_CHECK(pTwi); - - /* SVEN: TWI Slave Mode Enabled */ - pTwi->TWI_CR = TWI_CR_SVEN; - /* Reset the TWI*/ - pTwi->TWI_CR = TWI_CR_SWRST; - pTwi->TWI_RHR; - - /* TWI Slave Mode Disabled, TWI Master Mode Disabled. */ - pTwi->TWI_CR = TWI_CR_SVDIS; - pTwi->TWI_CR = TWI_CR_MSDIS; - - /* Set master mode */ - pTwi->TWI_CR = TWI_CR_MSEN; - - /* Configure clock */ - while (!ok) { - cldiv = ((mck / (2 * twck)) - 3) / power(2, ckdiv); - if (cldiv <= 255) { - ok = 1; - } - else { - ckdiv++; - } - } - ASSERT(ckdiv < 8, "-F- Cannot find valid TWI clock parameters\n\r"); - TRACE_DEBUG("Using CKDIV = %u and CLDIV/CHDIV = %u\n\r", ckdiv, cldiv); - pTwi->TWI_CWGR = 0; - pTwi->TWI_CWGR = (ckdiv << 16) | (cldiv << 8) | cldiv; -} - -/** - * \brief Configures a TWI peripheral to operate in slave mode. - * \param pTwi Pointer to an Twi instance. - * \param slaveAddress Slave address. - */ -void TWI_ConfigureSlave(Twi *pTwi, uint8_t slaveAddress) -{ - uint32_t i; - - /* TWI software reset */ - pTwi->TWI_CR = TWI_CR_SWRST; - pTwi->TWI_RHR; - - /* Wait at least 10 ms */ - for (i=0; i < 1000000; i++); - - /* TWI Slave Mode Disabled, TWI Master Mode Disabled*/ - pTwi->TWI_CR = TWI_CR_SVDIS | TWI_CR_MSDIS; - - /* Configure slave address. */ - pTwi->TWI_SMR = 0; - pTwi->TWI_SMR = (slaveAddress << 16) & TWI_SMR_SADR; - - /* SVEN: TWI Slave Mode Enabled */ - pTwi->TWI_CR = TWI_CR_SVEN; - - /* Wait at least 10 ms */ - for (i=0; i < 1000000; i++); - ASSERT( (pTwi->TWI_CR & TWI_CR_SVDIS)!= TWI_CR_SVDIS, "Can't configure TWI slave mode"); -} - -/** - * \brief Sends a STOP condition on the TWI. - * \param pTwi Pointer to an Twi instance. - */ -void TWI_Stop(Twi *pTwi) -{ - SANITY_CHECK(pTwi); - pTwi->TWI_CR = TWI_CR_STOP; -} - -/** - * \brief Starts a read operation on the TWI bus with the specified slave, it returns - * immediately. Data must then be read using TWI_ReadByte() whenever a byte is - * available (poll using TWI_ByteReceived()). - * \param pTwi Pointer to an Twi instance. - * \param address Slave address on the bus. - * \param iaddress Optional internal address bytes. - * \param isize Number of internal address bytes. - */ -void TWI_StartRead( - Twi *pTwi, - uint8_t address, - uint32_t iaddress, - uint8_t isize) -{ - SANITY_CHECK(pTwi); - SANITY_CHECK((address & 0x80) == 0); - SANITY_CHECK((iaddress & 0xFF000000) == 0); - SANITY_CHECK(isize < 4); - - /* Set slave address and number of internal address bytes. */ - pTwi->TWI_MMR = 0; - pTwi->TWI_MMR = (isize << 8) | TWI_MMR_MREAD | (address << 16); - - /* Set internal address bytes */ - pTwi->TWI_IADR = 0; - pTwi->TWI_IADR = iaddress; - - /* Send START condition */ - pTwi->TWI_CR = TWI_CR_START; -} - -/** - * \brief Reads a byte from the TWI bus. The read operation must have been started - * using TWI_StartRead() and a byte must be available (check with TWI_ByteReceived()). - * \param pTwi Pointer to an Twi instance. - * \return byte read. - */ -uint8_t TWI_ReadByte(Twi *pTwi) -{ - SANITY_CHECK(pTwi); - - return pTwi->TWI_RHR; -} - -/** - * \brief Sends a byte of data to one of the TWI slaves on the bus. - * \note This function must be called once before TWI_StartWrite() with - * the first byte of data to send, then it shall be called repeatedly - * after that to send the remaining bytes. - * \param pTwi Pointer to an Twi instance. - * \param byte Byte to send. - */ -void TWI_WriteByte(Twi *pTwi, uint8_t byte) -{ - SANITY_CHECK(pTwi); - - pTwi->TWI_THR = byte; -} - -/** - * \brief Starts a write operation on the TWI to access the selected slave, then - * returns immediately. A byte of data must be provided to start the write; - * other bytes are written next. - * after that to send the remaining bytes. - * \param pTwi Pointer to an Twi instance. - * \param address Address of slave to acccess on the bus. - * \param iaddress Optional slave internal address. - * \param isize Number of internal address bytes. - * \param byte First byte to send. - */ -void TWI_StartWrite( - Twi *pTwi, - uint8_t address, - uint32_t iaddress, - uint8_t isize, - uint8_t byte) -{ - SANITY_CHECK(pTwi); - SANITY_CHECK((address & 0x80) == 0); - SANITY_CHECK((iaddress & 0xFF000000) == 0); - SANITY_CHECK(isize < 4); - - /* Set slave address and number of internal address bytes. */ - pTwi->TWI_MMR = 0; - pTwi->TWI_MMR = (isize << 8) | (address << 16); - - /* Set internal address bytes. */ - pTwi->TWI_IADR = 0; - pTwi->TWI_IADR = iaddress; - - /* Write first byte to send.*/ - TWI_WriteByte(pTwi, byte); -} - -/** - * \brief Check if a byte have been receiced from TWI. - * \param pTwi Pointer to an Twi instance. - * \return 1 if a byte has been received and can be read on the given TWI - * peripheral; otherwise, returns 0. This function resets the status register. - */ -uint8_t TWI_ByteReceived(Twi *pTwi) -{ - return ((pTwi->TWI_SR & TWI_SR_RXRDY) == TWI_SR_RXRDY); -} - -/** - * \brief Check if a byte have been sent to TWI. - * \param pTwi Pointer to an Twi instance. - * \return 1 if a byte has been sent so another one can be stored for - * transmission; otherwise returns 0. This function clears the status register. - */ -uint8_t TWI_ByteSent(Twi *pTwi) -{ - return ((pTwi->TWI_SR & TWI_SR_TXRDY) == TWI_SR_TXRDY); -} - -/** - * \brief Check if current transmission is complet. - * \param pTwi Pointer to an Twi instance. - * \return 1 if the current transmission is complete (the STOP has been sent); - * otherwise returns 0. - */ -uint8_t TWI_TransferComplete(Twi *pTwi) -{ - return ((pTwi->TWI_SR & TWI_SR_TXCOMP) == TWI_SR_TXCOMP); -} - -/** - * \brief Enables the selected interrupts sources on a TWI peripheral. - * \param pTwi Pointer to an Twi instance. - * \param sources Bitwise OR of selected interrupt sources. - */ -void TWI_EnableIt(Twi *pTwi, uint32_t sources) -{ - SANITY_CHECK(pTwi); - SANITY_CHECK((sources & 0xFFFFF088) == 0); - - pTwi->TWI_IER = sources; -} - -/** - * \brief Disables the selected interrupts sources on a TWI peripheral. - * \param pTwi Pointer to an Twi instance. - * \param sources Bitwise OR of selected interrupt sources. - */ -void TWI_DisableIt(Twi *pTwi, uint32_t sources) -{ - SANITY_CHECK(pTwi); - SANITY_CHECK((sources & 0xFFFFF088) == 0); - - pTwi->TWI_IDR = sources; -} - -/** - * \brief Get the current status register of the given TWI peripheral. - * \note This resets the internal value of the status register, so further - * read may yield different values. - * \param pTwi Pointer to an Twi instance. - * \return TWI status register. - */ -uint32_t TWI_GetStatus(Twi *pTwi) -{ - SANITY_CHECK(pTwi); - - return pTwi->TWI_SR; -} - -/** - * \brief Returns the current status register of the given TWI peripheral, but - * masking interrupt sources which are not currently enabled. - * \note This resets the internal value of the status register, so further - * read may yield different values. - * \param pTwi Pointer to an Twi instance. - */ -uint32_t TWI_GetMaskedStatus(Twi *pTwi) -{ - uint32_t status; - - SANITY_CHECK(pTwi); - - status = pTwi->TWI_SR; - status &= pTwi->TWI_IMR; - - return status; -} - -/** - * \brief Sends a STOP condition. STOP Condition is sent just after completing - * the current byte transmission in master read mode. - * \param pTwi Pointer to an Twi instance. - */ -void TWI_SendSTOPCondition(Twi *pTwi) -{ - SANITY_CHECK(pTwi); - - pTwi->TWI_CR |= TWI_CR_STOP; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twi.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twi.h deleted file mode 100644 index a23740486..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twi.h +++ /dev/null @@ -1,95 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for configuration the Two Wire Interface (TWI) peripheral. - * - */ - -#ifndef TWI_H -#define TWI_H - -/*---------------------------------------------------------------------------- - * Macros - *----------------------------------------------------------------------------*/ -/* Returns 1 if the TXRDY bit (ready to transmit data) is set in the given status register value.*/ -#define TWI_STATUS_TXRDY(status) ((status & TWI_SR_TXRDY) == TWI_SR_TXRDY) - -/* Returns 1 if the RXRDY bit (ready to receive data) is set in the given status register value.*/ -#define TWI_STATUS_RXRDY(status) ((status & TWI_SR_RXRDY) == TWI_SR_RXRDY) - -/* Returns 1 if the TXCOMP bit (transfer complete) is set in the given status register value.*/ -#define TWI_STATUS_TXCOMP(status) ((status & TWI_SR_TXCOMP) == TWI_SR_TXCOMP) - -/*---------------------------------------------------------------------------- - * External function - *----------------------------------------------------------------------------*/ - -extern void TWI_ConfigureMaster(Twi *pTwi, uint32_t twck, uint32_t mck); - -extern void TWI_ConfigureSlave(Twi *pTwi, uint8_t slaveAddress); - -extern void TWI_Stop(Twi *pTwi); - -extern void TWI_StartRead( - Twi *pTwi, - uint8_t address, - uint32_t iaddress, - uint8_t isize); - -extern uint8_t TWI_ReadByte(Twi *pTwi); - -extern void TWI_WriteByte(Twi *pTwi, uint8_t byte); - -extern void TWI_StartWrite( - Twi *pTwi, - uint8_t address, - uint32_t iaddress, - uint8_t isize, - uint8_t byte); - -extern uint8_t TWI_ByteReceived(Twi *pTwi); - -extern uint8_t TWI_ByteSent(Twi *pTwi); - -extern uint8_t TWI_TransferComplete(Twi *pTwi); - -extern void TWI_EnableIt(Twi *pTwi, uint32_t sources); - -extern void TWI_DisableIt(Twi *pTwi, uint32_t sources); - -extern uint32_t TWI_GetStatus(Twi *pTwi); - -extern uint32_t TWI_GetMaskedStatus(Twi *pTwi); - -extern void TWI_SendSTOPCondition(Twi *pTwi); - -#endif //#ifndef TWI_H diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twid.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twid.c deleted file mode 100644 index 6d1774de3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/twi/twid.c +++ /dev/null @@ -1,342 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - - - - - - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "twid.h" -#include -#include -#include - -/*---------------------------------------------------------------------------- - * Definition - *----------------------------------------------------------------------------*/ -#define TWITIMEOUTMAX 50000 - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - -/** TWI driver callback function.*/ -typedef void (*TwiCallback)(Async *); - -/** TWI asynchronous transfer descriptor.*/ -typedef struct _AsyncTwi { - - /** Asynchronous transfer status. */ - volatile uint8_t status; - // Callback function to invoke when transfer completes or fails.*/ - TwiCallback callback; - /** Pointer to the data buffer.*/ - uint8_t *pData; - /** Total number of bytes to transfer.*/ - uint32_t num; - /** Number of already transferred bytes.*/ - uint32_t transferred; - -} AsyncTwi; - -/*---------------------------------------------------------------------------- - * Global functions - *----------------------------------------------------------------------------*/ -/** - * \brief Initializes a TWI driver instance, using the given TWI peripheral. - * \note The peripheral must have been initialized properly before calling this function. - * \param pTwid Pointer to the Twid instance to initialize. - * \param pTwi Pointer to the TWI peripheral to use. - */ -void TWID_Initialize(Twid *pTwid, Twi *pTwi) -{ - TRACE_DEBUG("TWID_Initialize()\n\r"); - SANITY_CHECK(pTwid); - SANITY_CHECK(pTwi); - - /* Initialize driver. */ - pTwid->pTwi = pTwi; - pTwid->pTransfer = 0; -} - - -/** - * \brief Interrupt handler for a TWI peripheral. Manages asynchronous transfer - * occuring on the bus. This function MUST be called by the interrupt service - * routine of the TWI peripheral if asynchronous read/write are needed. - * \param pTwid Pointer to a Twid instance. - */ -void TWID_Handler(Twid *pTwid) -{ - uint8_t status; - AsyncTwi *pTransfer = (AsyncTwi *) pTwid->pTransfer; - Twi *pTwi = pTwid->pTwi; - - SANITY_CHECK(pTwid); - - /* Retrieve interrupt status */ - status = TWI_GetMaskedStatus(pTwi); - - /* Byte received */ - if (TWI_STATUS_RXRDY(status)) { - - pTransfer->pData[pTransfer->transferred] = TWI_ReadByte(pTwi); - pTransfer->transferred++; - - /* check for transfer finish */ - if (pTransfer->transferred == pTransfer->num) { - - TWI_DisableIt(pTwi, TWI_IDR_RXRDY); - TWI_EnableIt(pTwi, TWI_IER_TXCOMP); - } - /* Last byte? */ - else if (pTransfer->transferred == (pTransfer->num - 1)) { - - TWI_Stop(pTwi); - } - } - /* Byte sent*/ - else if (TWI_STATUS_TXRDY(status)) { - - /* Transfer finished ? */ - if (pTransfer->transferred == pTransfer->num) { - - TWI_DisableIt(pTwi, TWI_IDR_TXRDY); - TWI_EnableIt(pTwi, TWI_IER_TXCOMP); - TWI_SendSTOPCondition(pTwi); - } - /* Bytes remaining */ - else { - - TWI_WriteByte(pTwi, pTransfer->pData[pTransfer->transferred]); - pTransfer->transferred++; - } - } - /* Transfer complete*/ - else if (TWI_STATUS_TXCOMP(status)) { - - TWI_DisableIt(pTwi, TWI_IDR_TXCOMP); - pTransfer->status = 0; - if (pTransfer->callback) { - - pTransfer->callback((Async *) pTransfer); - } - pTwid->pTransfer = 0; - } -} - -/** - * \brief Asynchronously reads data from a slave on the TWI bus. An optional - * callback function is triggered when the transfer is complete. - * \param pTwid Pointer to a Twid instance. - * \param address TWI slave address. - * \param iaddress Optional slave internal address. - * \param isize Internal address size in bytes. - * \param pData Data buffer for storing received bytes. - * \param num Number of bytes to read. - * \param pAsync Asynchronous transfer descriptor. - * \return 0 if the transfer has been started; otherwise returns a TWI error code. - */ -uint8_t TWID_Read( - Twid *pTwid, - uint8_t address, - uint32_t iaddress, - uint8_t isize, - uint8_t *pData, - uint32_t num, - Async *pAsync) -{ - Twi *pTwi = pTwid->pTwi; - AsyncTwi *pTransfer = (AsyncTwi *) pTwid->pTransfer; - uint32_t timeout; - - SANITY_CHECK(pTwid); - SANITY_CHECK((address & 0x80) == 0); - SANITY_CHECK((iaddress & 0xFF000000) == 0); - SANITY_CHECK(isize < 4); - - /* Check that no transfer is already pending*/ - if (pTransfer) { - - TRACE_ERROR("TWID_Read: A transfer is already pending\n\r"); - return TWID_ERROR_BUSY; - } - - /* Set STOP signal if only one byte is sent*/ - if (num == 1) { - - TWI_Stop(pTwi); - } - - /* Asynchronous transfer*/ - if (pAsync) { - - /* Update the transfer descriptor */ - pTwid->pTransfer = pAsync; - pTransfer = (AsyncTwi *) pAsync; - pTransfer->status = ASYNC_STATUS_PENDING; - pTransfer->pData = pData; - pTransfer->num = num; - pTransfer->transferred = 0; - - /* Enable read interrupt and start the transfer */ - TWI_EnableIt(pTwi, TWI_IER_RXRDY); - TWI_StartRead(pTwi, address, iaddress, isize); - } - /* Synchronous transfer*/ - else { - - /* Start read*/ - TWI_StartRead(pTwi, address, iaddress, isize); - - /* Read all bytes, setting STOP before the last byte*/ - while (num > 0) { - - /* Last byte ?*/ - if (num == 1) { - - TWI_Stop(pTwi); - } - - /* Wait for byte then read and store it*/ - timeout = 0; - while( !TWI_ByteReceived(pTwi) && (++timeoutpTwi; - AsyncTwi *pTransfer = (AsyncTwi *) pTwid->pTransfer; - uint32_t timeout; - - SANITY_CHECK(pTwi); - SANITY_CHECK((address & 0x80) == 0); - SANITY_CHECK((iaddress & 0xFF000000) == 0); - SANITY_CHECK(isize < 4); - - /* Check that no transfer is already pending */ - if (pTransfer) { - - TRACE_ERROR("TWI_Write: A transfer is already pending\n\r"); - return TWID_ERROR_BUSY; - } - - /* Asynchronous transfer */ - if (pAsync) { - - /* Update the transfer descriptor */ - pTwid->pTransfer = pAsync; - pTransfer = (AsyncTwi *) pAsync; - pTransfer->status = ASYNC_STATUS_PENDING; - pTransfer->pData = pData; - pTransfer->num = num; - pTransfer->transferred = 1; - - /* Enable write interrupt and start the transfer */ - TWI_StartWrite(pTwi, address, iaddress, isize, *pData); - TWI_EnableIt(pTwi, TWI_IER_TXRDY); - } - /* Synchronous transfer*/ - else { - - // Start write - TWI_StartWrite(pTwi, address, iaddress, isize, *pData++); - num--; - - /* Send all bytes */ - while (num > 0) { - - /* Wait before sending the next byte */ - timeout = 0; - while( !TWI_ByteSent(pTwi) && (++timeout -#include - -/*---------------------------------------------------------------------------- - * Definition - *----------------------------------------------------------------------------*/ - -/** TWI driver is currently busy. */ -#define TWID_ERROR_BUSY 1 - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - -/** TWI driver structure. Holds the internal state of the driver.*/ -typedef struct _Twid { - /** Pointer to the underlying TWI peripheral.*/ - Twi *pTwi; - /** Current asynchronous transfer being processed.*/ - Async *pTransfer; - -} Twid; - -/*---------------------------------------------------------------------------- - * Export functions - *----------------------------------------------------------------------------*/ -extern void TWID_Initialize(Twid *pTwid, Twi *pTwi); - -extern void TWID_Handler(Twid *pTwid); - -extern uint8_t TWID_Read( - Twid *pTwid, - uint8_t address, - uint32_t iaddress, - uint8_t isize, - uint8_t *pData, - uint32_t num, - Async *pAsync); - -extern uint8_t TWID_Write( - Twid *pTwid, - uint8_t address, - uint32_t iaddress, - uint8_t isize, - uint8_t *pData, - uint32_t num, - Async *pAsync); - -#endif //#ifndef TWID_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/uart_console.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/uart_console.c deleted file mode 100644 index 07eaeec38..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/uart_console.c +++ /dev/null @@ -1,288 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implements UART console. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include -#include -#include -#include -#include - -#include "usart/uart_console.h" - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -/** Console baudrate always using 115200. */ -#define CONSOLE_BAUDRATE 115200 -/** Usart Hw interface used by the console (UART0). */ -#define CONSOLE_USART UART0 -/** Usart Hw ID used by the console (UART0). */ -#define CONSOLE_ID ID_UART0 -/** Pins description corresponding to Rxd,Txd, (UART pins) */ -#define CONSOLE_PINS {PINS_UART} - -/*---------------------------------------------------------------------------- - * Variables - *----------------------------------------------------------------------------*/ - -/** Is Console Initialized. */ -static uint8_t isConsolInitialized = 0; - -/** - * \brief Configures an USART peripheral with the specified parameters. - * - * \param baudrate Baudrate at which the USART should operate (in Hz). - * \param masterClock Frequency of the system master clock (in Hz). - */ -static void UART_Configure( uint32_t baudrate, - uint32_t masterClock) -{ - const Pin pPins[] = CONSOLE_PINS; - Uart *pUart = CONSOLE_USART; - - /* Configure PIO */ - PIO_Configure(pPins, PIO_LISTSIZE(pPins)); - - /* Configure PMC */ - PMC->PMC_PCER0 = 1 << CONSOLE_ID; - - /* Reset and disable receiver & transmitter */ - pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX - | UART_CR_RXDIS | UART_CR_TXDIS; - - /* Configure mode */ - pUart->UART_MR = (0x4 << 9); /* TODO: Change with new symbols: AT91C_UART_CHRL_8_BITS | AT91C_UART_PAR_NONE */ - - /* Configure baudrate */ - /* Asynchronous, no oversampling */ - pUart->UART_BRGR = (masterClock / baudrate) / 16; - - /* Disable PDC channel */ - pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS; - - /* Enable receiver and transmitter */ - pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; - - isConsolInitialized = 1; -} - -/** - * \brief Outputs a character on the UART line. - * - * \note This function is synchronous (i.e. uses polling). - * \param c Character to send. - */ -void UART_PutChar(uint8_t c) -{ - Uart *pUart = CONSOLE_USART; - - if (!isConsolInitialized) - UART_Configure(CONSOLE_BAUDRATE, BOARD_MCK); - - /* Wait for the transmitter to be ready */ - while ((pUart->UART_SR & UART_SR_TXEMPTY) == 0); - - /* Send character */ - pUart->UART_THR = c; - -} - -/** - * \brief Input a character from the UART line. - * - * \note This function is synchronous - * \return character received. - */ -uint8_t UART_GetChar(void) -{ - Uart *pUart = CONSOLE_USART; - - if (!isConsolInitialized) - UART_Configure(CONSOLE_BAUDRATE, BOARD_MCK); - - while((pUart->UART_SR & UART_SR_RXRDY) == 0); - return pUart->UART_RHR; -} - -/** - * \brief Check if there is Input from UART line. - * - * \return true if there is Input. - */ -bool UART_IsRxReady(void) -{ - Uart *pUart = CONSOLE_USART; - - if (!isConsolInitialized) - UART_Configure(CONSOLE_BAUDRATE, BOARD_MCK); - - return (pUart->UART_SR & UART_SR_RXRDY) > 0; -} - -/* \cond NOFPUT */ -#ifndef NOFPUT -#include -#include -/** - * \brief Implementation of fputc using the UART as the standard output. Required - * for printf(). - * - * \param c Character to write. - * \param pStream Output stream. - * - * \return The character written if successful, or -1 if the output stream is - * not stdout or stderr. - */ -int fputc ( int c, FILE * pStream ) -{ - if ((pStream == stdout) || (pStream == stderr)) { - UART_PutChar(c); - return c; - } - else { - - return EOF; - } -} - -/** - * \brief Implementation of fputs using the UART as the standard output. Required - * for printf(). Does NOT currently use the PDC. - * - * \param pStr String to write. - * \param pStream Output stream. - * - * \return Number of characters written if successful, or -1 if the output - * stream is not stdout or stderr. - */ -signed int fputs(const char *pStr, FILE *pStream) -{ - signed int num = 0; - - while (*pStr != 0) { - - if (fputc(*pStr, pStream) == -1) { - - return -1; - } - num++; - pStr++; - } - - return num; -} - -#undef putchar - -/** - * \brief Outputs a character on the UART. - * - * \param c Character to output. - * - * \return The character that was output. - */ -signed int putchar(signed int c) -{ - return fputc(c, stdout); -} - -/* The char which has been ungotten, or EOF. */ -static int _UngetChar = EOF; - -/** - * \brief Implementation of fputc using the UART as the standard output. Required - * for printf(). - * - * \param c Character to write. - * \param pStream Output stream. - * - * \return The character written if successful, or -1 if the output stream is - * not stdout or stderr. - */ -int fgetc (FILE * pStream ) -{ - int c; - - if (pStream == stdin) { - c = UART_GetChar(); - return c; - } - else { - - return EOF; - } -} - -#undef getchar -/** - * \brief Get a character from UART. - * - * \return The character received. - */ -signed int getchar(void) -{ - if (_UngetChar != EOF) - { - int res = _UngetChar; - _UngetChar = EOF; - return res; - } - else - { - return fgetc(stdin); - } -} - -#undef __ungetchar -/** - * \brief Unget a character from stdin. - * - * \return The unget character. - */ -signed int __ungetchar(int c) -{ - _UngetChar = c; - return c; -} - -#endif /* #ifndef NOFPUT */ -/* \endcond */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/uart_console.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/uart_console.h deleted file mode 100644 index dfa192178..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/uart_console.h +++ /dev/null @@ -1,38 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - - -#ifndef UART_CONSOLE_H_ -#define UART_CONSOLE_H_ - -extern void UART_PutChar(uint8_t c); -extern uint8_t UART_GetChar(void); -extern bool UART_IsRxReady(void); - -#endif /* UART_CONSOLE_H_ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/usart.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/usart.c deleted file mode 100644 index 5aa10e5dd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/usart.c +++ /dev/null @@ -1,395 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup usart_module Working with USART - * The USART driver provides the interface to configure and use the USART peripheral.\n - * - * The USART supports several kinds of comminication modes such as full-duplex asynchronous/ - * synchronous serial commnunication,RS485 with driver control signal,ISO7816,SPI and Test modes. - * - * To start a USART transfer with \ref AT91SAM3S_PDC "PDC" support, the user could follow these steps: - *
    - *
  • Configure USART with expected mode and baudrate(see \ref USART_Configure), which could be done by: - * -# Resetting and disabling transmitter and receiver by setting US_CR(Control Register).
  • - * -# Conifguring the USART in a specific mode by setting USART_MODE bits in US_MR(Mode Register) - * -# Setting baudrate which is different from mode to mode. - - *
  • Enable transmitter or receiver respectively by set US_CR_TXEN or US_CR_RXEN in US_CR.
  • - *
  • Read from or write to the peripheral with \ref USART_ReadBuffer or \ref USART_WriteBuffer. - These operations could be done by polling or interruption.
  • - *
  • For polling, check the status bit US_CSR_ENDRX/US_CSR_RXBUFF (READ) or US_CSR_ENDTX/ - US_CSR_TXBUFE (WRITE).
  • - *
  • For interruption,"enable" the status bit through US_IER and - realize the hanler with USARTx_IrqHandler according to IRQ vector - table which is defined in board_cstartup_.c - To enable the interruption of USART,it should be configured with priority and enabled first through - NVIC .
  • - *
- * - * For more accurate information, please look at the USART section of the - * Datasheet. - * - * Related files :\n - * \ref usart.c\n - * \ref usart.h\n -*/ - - - -/** - * \file - * - * Implementation of USART (Universal Synchronous Asynchronous Receiver Transmitter) - * controller. - * - */ -/*------------------------------------------------------------------------------ - * Headers - *------------------------------------------------------------------------------*/ -#include - -#include "usart.h" -#include -#include - -/*---------------------------------------------------------------------------- - * Local definitions - *----------------------------------------------------------------------------*/ - - -/*------------------------------------------------------------------------------ - * Exported functions - *------------------------------------------------------------------------------*/ - -/** - * \brief Configures an USART peripheral with the specified parameters. - * - * - * \param usart Pointer to the USART peripheral to configure. - * \param mode Desired value for the USART mode register (see the datasheet). - * \param baudrate Baudrate at which the USART should operate (in Hz). - * \param masterClock Frequency of the system master clock (in Hz). - */ -void USART_Configure(Usart *usart, - uint32_t mode, - uint32_t baudrate, - uint32_t masterClock) -{ - /* Reset and disable receiver & transmitter*/ - usart->US_CR = US_CR_RSTRX | US_CR_RSTTX - | US_CR_RXDIS | US_CR_TXDIS; - - /* Configure mode*/ - usart->US_MR = mode; - - /* Configure baudrate*/ - /* Asynchronous, no oversampling*/ - if (((mode & US_MR_SYNC__CPHA) == 0) - && ((mode & US_MR_OVER) == 0)) { - - usart->US_BRGR = (masterClock / baudrate) / 16; - } - /* TODO other modes*/ -} -/** - * \brief Enables or disables the transmitter of an USART peripheral. - * - * - * \param usart Pointer to an USART peripheral - * \param enabled If true, the transmitter is enabled; otherwise it is - * disabled. - */ -void USART_SetTransmitterEnabled(Usart *usart, uint8_t enabled) -{ - if (enabled) { - - usart->US_CR = US_CR_TXEN; - } - else { - - usart->US_CR = US_CR_TXDIS; - } -} - -/** - * \brief Enables or disables the receiver of an USART peripheral - * - * - * \param usart Pointer to an USART peripheral - * \param enabled If true, the receiver is enabled; otherwise it is disabled. - */ -void USART_SetReceiverEnabled(Usart *usart, - uint8_t enabled) -{ - if (enabled) { - - usart->US_CR = US_CR_RXEN; - } - else { - - usart->US_CR = US_CR_RXDIS; - } -} - -/** - * \brief Sends one packet of data through the specified USART peripheral. This - * function operates synchronously, so it only returns when the data has been - * actually sent. - * - * - * \param usart Pointer to an USART peripheral. - * \param data Data to send including 9nth bit and sync field if necessary (in - * the same format as the US_THR register in the datasheet). - * \param timeOut Time out value (0 = no timeout). - */ -void USART_Write( - Usart *usart, - uint16_t data, - volatile uint32_t timeOut) -{ - if (timeOut == 0) { - - while ((usart->US_CSR & US_CSR_TXEMPTY) == 0); - } - else { - - while ((usart->US_CSR & US_CSR_TXEMPTY) == 0) { - - if (timeOut == 0) { - - TRACE_ERROR("USART_Write: Timed out.\n\r"); - return; - } - timeOut--; - } - } - - usart->US_THR = data; -} - -/** - * \brief Sends the contents of a data buffer through the specified USART peripheral. - * This function returns immediately (1 if the buffer has been queued, 0 - * otherwise); poll the ENDTX and TXBUFE bits of the USART status register - * to check for the transfer completion. - * - * \param usart Pointer to an USART peripheral. - * \param buffer Pointer to the data buffer to send. - * \param size Size of the data buffer (in bytes). - */ -uint8_t USART_WriteBuffer( - Usart *usart, - void *buffer, - uint32_t size) -{ - /* Check if the first PDC bank is free*/ - if ((usart->US_TCR == 0) && (usart->US_TNCR == 0)) { - - usart->US_TPR = (uint32_t) buffer; - usart->US_TCR = size; - usart->US_PTCR = US_PTCR_TXTEN; - - return 1; - } - /* Check if the second PDC bank is free*/ - else if (usart->US_TNCR == 0) { - - usart->US_TNPR = (uint32_t) buffer; - usart->US_TNCR = size; - - return 1; - } - else { - - return 0; - } -} - - -/** - * \brief Reads and return a packet of data on the specified USART peripheral. This - * function operates asynchronously, so it waits until some data has been - * received. - * - * \param usart Pointer to an USART peripheral. - * \param timeOut Time out value (0 -> no timeout). - */ -uint16_t USART_Read( - Usart *usart, - volatile uint32_t timeOut) -{ - if (timeOut == 0) { - - while ((usart->US_CSR & US_CSR_RXRDY) == 0); - } - else { - - while ((usart->US_CSR & US_CSR_RXRDY) == 0) { - - if (timeOut == 0) { - - TRACE_ERROR("USART_Read: Timed out.\n\r"); - return 0; - } - timeOut--; - } - } - - return usart->US_RHR; -} - -/** - * \brief Reads data from an USART peripheral, filling the provided buffer until it - * becomes full. This function returns immediately with 1 if the buffer has - * been queued for transmission; otherwise 0. - * - * \param usart Pointer to an USART peripheral. - * \param buffer Pointer to the buffer where the received data will be stored. - * \param size Size of the data buffer (in bytes). - */ -uint8_t USART_ReadBuffer(Usart *usart, - void *buffer, - uint32_t size) -{ - /* Check if the first PDC bank is free*/ - if ((usart->US_RCR == 0) && (usart->US_RNCR == 0)) { - - usart->US_RPR = (uint32_t) buffer; - usart->US_RCR = size; - usart->US_PTCR = US_PTCR_RXTEN; - - return 1; - } - /* Check if the second PDC bank is free*/ - else if (usart->US_RNCR == 0) { - - usart->US_RNPR = (uint32_t) buffer; - usart->US_RNCR = size; - - return 1; - } - else { - - return 0; - } -} - -/** - * \brief Returns 1 if some data has been received and can be read from an USART; - * otherwise returns 0. - * - * \param usart Pointer to an Usart instance. - */ -uint8_t USART_IsDataAvailable(Usart *usart) -{ - if ((usart->US_CSR & US_CSR_RXRDY) != 0) { - - return 1; - } - else { - - return 0; - } -} - -/** - * \brief Sets the filter value for the IRDA demodulator. - * - * \param pUsart Pointer to an Usart instance. - * \param filter Filter value. - */ -void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter) -{ - SANITY_CHECK(pUsart); - - pUsart->US_IF = filter; -} - -/** - * \brief Sends one packet of data through the specified USART peripheral. This - * function operates synchronously, so it only returns when the data has been - * actually sent. - * - * \param usart Pointer to an USART peripheral. - * \param c Character to send - */ -void USART_PutChar( - Usart *usart, - uint8_t c) -{ - /* Wait for the transmitter to be ready*/ - while ((usart->US_CSR & US_CSR_TXEMPTY) == 0); - - /* Send character*/ - usart->US_THR = c; - - /* Wait for the transfer to complete*/ - while ((usart->US_CSR & US_CSR_TXEMPTY) == 0); -} - -/** - * \brief Return 1 if a character can be read in USART - */ -uint32_t USART_IsRxReady(Usart *usart) -{ - return (usart->US_CSR & US_CSR_RXRDY); -} -/** - * \brief Get present status - */ -uint32_t USART_GetStatus(Usart *usart) -{ - return usart->US_CSR; -} -/** - * \brief Enable interrupt - */ -void USART_EnableIt(Usart *usart,uint32_t mode) -{ - usart->US_IER = mode; -} -/** - * \brief Disable interrupt - */ -void USART_DisableIt(Usart *usart,uint32_t mode) -{ - usart->US_IDR = mode; -} -/** - * \brief Reads and returns a character from the USART. - * - * \note This function is synchronous (i.e. uses polling). - * \param usart Pointer to an USART peripheral. - * \return Character received. - */ -uint8_t USART_GetChar(Usart *usart) -{ - while ((usart->US_CSR & US_CSR_RXRDY) == 0); - return usart->US_RHR; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/usart.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/usart.h deleted file mode 100644 index 8c50f87eb..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/usart/usart.h +++ /dev/null @@ -1,129 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * \par Purpose - * - * This module provides several definitions and methods for using an USART - * peripheral. - * - * \par Usage - * - * -# Enable the USART peripheral clock in the PMC. - * -# Enable the required USART PIOs (see pio.h). - * -# Configure the UART by calling USART_Configure. - * -# Enable the transmitter and/or the receiver of the USART using - * USART_SetTransmitterEnabled and USART_SetReceiverEnabled. - * -# Send data through the USART using the USART_Write and - * USART_WriteBuffer methods. - * -# Receive data from the USART using the USART_Read and - * USART_ReadBuffer functions; the availability of data can be polled - * with USART_IsDataAvailable. - * -# Disable the transmitter and/or the receiver of the USART with - * USART_SetTransmitterEnabled and USART_SetReceiverEnabled. - */ - -#ifndef USART_H -#define USART_H - -/*------------------------------------------------------------------------------ - * Headers - *------------------------------------------------------------------------------*/ - -#include - -/*------------------------------------------------------------------------------ - * Definitions - *------------------------------------------------------------------------------*/ - -/** \section USART_mode USART modes - * This section lists several common operating modes for an USART peripheral. - * - * \b Modes - * - USART_MODE_ASYNCHRONOUS - * - USART_MODE_IRDA - */ - -/** Basic asynchronous mode, i.e. 8 bits no parity.*/ -#define USART_MODE_ASYNCHRONOUS (AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE) - -/** IRDA mode*/ -#define USART_MODE_IRDA (AT91C_US_USMODE_IRDA | AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_FILTER) - - -/*------------------------------------------------------------------------------*/ -/* Exported functions*/ -/*------------------------------------------------------------------------------*/ - -extern void USART_Configure( - Usart *usart, - uint32_t mode, - uint32_t baudrate, - uint32_t masterClock); -extern uint32_t USART_GetStatus(Usart *usart); -extern void USART_EnableIt(Usart *usart,uint32_t mode); -extern void USART_DisableIt(Usart *usart,uint32_t mode); -extern void USART_SetTransmitterEnabled(Usart *usart, uint8_t enabled); - -extern void USART_SetReceiverEnabled(Usart *usart, uint8_t enabled); - -extern void USART_Write( - Usart *usart, - uint16_t data, - volatile uint32_t timeOut); - -extern uint8_t USART_WriteBuffer( - Usart *usart, - void *buffer, - uint32_t size); - -extern uint16_t USART_Read( - Usart *usart, - volatile uint32_t timeOut); - -extern uint8_t USART_ReadBuffer( - Usart *usart, - void *buffer, - uint32_t size); - -extern uint8_t USART_IsDataAvailable(Usart *usart); - -extern void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter); - -extern void USART_PutChar(Usart *usart, uint8_t c); - -extern uint32_t USART_IsRxReady(Usart *usart); - -extern uint8_t USART_GetChar(Usart *usart); - - -#endif /*#ifndef USART_H*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/assert.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/assert.h deleted file mode 100644 index 5c21781de..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/assert.h +++ /dev/null @@ -1,114 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// Definition of the ASSERT() and SANITY_CHECK() macros, which are used for -/// runtime condition & parameter verifying. -/// -/// !Usage -/// -/// -# Use ASSERT() in your code to check the value of function parameters, -/// return values, etc. *Warning:* the ASSERT() condition must not have -/// any side-effect; otherwise, the program may not work properly -/// anymore when assertions are disabled. -/// -# Use SANITY_CHECK() to perform checks with a default error message -/// (outputs the file and line number where the error occured). This -/// reduces memory overhead caused by assertion error strings. -/// -# Initialize the dbgu to see failed assertions at run-time. -/// -# Assertions can be entirely disabled by defining the NOASSERT symbol -/// at compilation time. -//------------------------------------------------------------------------------ - -#ifndef ASSERT_H -#define ASSERT_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include -#include "trace.h" - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ -#if defined(NOASSERT) - #define ASSERT(...) - #define SANITY_CHECK(...) -#else - - #if (TRACE_LEVEL == 0) - /// Checks that the given condition is true, - /// otherwise stops the program execution. - /// \param condition Condition to verify. - #define ASSERT(condition, ...) { \ - if (!(condition)) { \ - while (1); \ - } \ - } - - /// Performs the same duty as the ASSERT() macro - /// \param condition Condition to verify. - #define SANITY_CHECK(condition) ASSERT(condition, ...) - - #else - /// Checks that the given condition is true, otherwise displays an error - /// message and stops the program execution. - /// \param condition Condition to verify. - #define ASSERT(condition, ...) { \ - if (!(condition)) { \ - printf("-F- ASSERT: "); \ - printf(__VA_ARGS__); \ - while (1); \ - } \ - } - #define SANITY_ERROR "Sanity check failed at %s:%d\n\r" - - /// Performs the same duty as the ASSERT() macro, except a default error - /// message is output if the condition is false. - /// \param condition Condition to verify. - #define SANITY_CHECK(condition) ASSERT(condition, SANITY_ERROR, __FILE__, __LINE__) - #endif -#endif - - - - - - - - - - -#endif //#ifndef ASSERT_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bitbanding.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bitbanding.h deleted file mode 100644 index 8ef5976cf..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bitbanding.h +++ /dev/null @@ -1,108 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef BITBANDING_H -#define BITBANDING_H - -//------------------------------------------------------------------------------ -/// \file bitbanding.h -/// Include Defines & macros for bit-banding. -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Header files -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Global Macros -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \def IS_BITBAND_SRAM_ADDR(x) -/// \brief Check if the address is in bit banding sram region. -/// \note The address should be in area of 0x2000000 ~ 0x200FFFFF -/// \param x The address to check. -//------------------------------------------------------------------------------ -#define IS_BITBAND_SRAM_ADDR(x) \ - ( ((uint32_t)(x)) >= 0x20000000 && \ - ((uint32_t)(x)) < (0x20000000+0x100000) ) - -//------------------------------------------------------------------------------ -/// \def IS_BITBAND_PERIPH_ADDR(x) -/// \brief Check if the address is in bit banding peripheral region -/// \note The address should be in area of 0x4000000 ~ 0x400FFFFF -/// \param x The address to check -//------------------------------------------------------------------------------ -#define IS_BITBAND_PERIPH_ADDR(x) \ - ( ((uint32_t)(x)) >= 0x40000000 && \ - ((uint32_t)(x)) < (0x40000000+0x100000) ) - -//------------------------------------------------------------------------------ -/// \def BITBAND_ALIAS_ADDRESS(addr, bit) -/// \brief Calculate bit band alias address. -/// -/// Calculate the bit band alias address and return a pointer address to word. -/// \param addr The byte address of bitbanding bit. -/// \param bit The bit position of bitbanding bit. -/// \callergraph -//------------------------------------------------------------------------------ -#define BITBAND_ALIAS_ADDRESS(addr, bit) \ - ((volatile uint32_t*)((((uint32_t)(addr) & 0xF0000000) + 0x02000000) \ - +((((uint32_t)(addr)&0xFFFFF)*32)\ - +( (uint32_t)(bit)*4)))) - -//------------------------------------------------------------------------------ -/// \def WRITE_BITBANDING(addr32, bit, val) -/// \brief Bit write through bit banding. -/// \param addr32 32-bit aligned byte address where the bit exists. -/// \param bit Bit position. -/// \param val The value that the bit is set to. -/// \callergraph -//------------------------------------------------------------------------------ -#define WRITE_BITBANDING(addr32, bit, val) do {\ - *BITBAND_ALIAS_ADDRESS(addr32,bit) = (val); \ - } while (0); - -//------------------------------------------------------------------------------ -/// \def TOGGLE_BITBANDING(addr32, bit) -/// \brief Toggle bit through bit banding -/// \param addr32 32-bit aligned byte address where the bit exists. -/// \param bit Bit position. -//------------------------------------------------------------------------------ -#define TOGGLE_BITBANDING(addr32, bit) do {\ - volatile uint32_t * p = \ - BITBAND_ALIAS_ADDRESS(addr32,bit); \ - if (*p) *p = 0; \ - else *p = 1; \ - }while(0); - -#endif //#ifndef BITBANDING_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bmp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bmp.c deleted file mode 100644 index fe3058757..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bmp.c +++ /dev/null @@ -1,322 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "bmp.h" -#include -#include - -#include - -//----------------------------------------------------------------------------- -// Define -//----------------------------------------------------------------------------- -/// BMP offset for header -#define IMAGE_OFFSET 0x100 - - -//------------------------------------------------------------------------------ -// Internal constants -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Internal types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Describe the BMP palette -//------------------------------------------------------------------------------ -struct BMPPaletteEntry { - - /// Blue value - unsigned char b; - /// Green value - unsigned char g; - /// Red value - unsigned char r; - /// Filler character value - unsigned char filler; -}; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Test if BMP is valid -/// \param file Buffer holding the file to examinate. -/// \return 1 if the header of a BMP file is valid; otherwise returns 0. -//------------------------------------------------------------------------------ -unsigned char BMP_IsValid(void *file) -{ - return ((struct BMPHeader *) file)->type == BMP_TYPE; -} - -//------------------------------------------------------------------------------ -/// Returns the size of a BMP image given at least its header (the file does -/// not have to be complete). -/// \param file Pointer to the buffer which holds the BMP file. -/// \return size of BMP image -//------------------------------------------------------------------------------ -unsigned int BMP_GetFileSize(void *file) -{ - return ((struct BMPHeader *) file)->fileSize; -} - -//----------------------------------------------------------------------------- -/// Write a BMP header -/// \param pAddressHeader Begin address of the BMP -/// \param bmpHSize BMP heigth size -/// \param bmpVSize BMP width size -/// \param bmpRgb Type of BMP (YUV or RGB) -/// \param nbByte_Pixels Number of byte per pixels -//----------------------------------------------------------------------------- -void WriteBMPheader(unsigned int* pAddressHeader, - unsigned int bmpHSize, - unsigned int bmpVSize, - unsigned char bmpRgb, - unsigned char nbByte_Pixels) -{ - unsigned int i; - unsigned int* fill; - struct BMPHeader *Header; - - fill = pAddressHeader; - for (i=0; itype = BMP_TYPE; - Header->fileSize = (bmpHSize * bmpVSize * nbByte_Pixels) + IMAGE_OFFSET; - Header->reserved1 = 0; - Header->reserved2 = 0; - Header->offset = IMAGE_OFFSET; - Header->headerSize = BITMAPINFOHEADER; - Header->width = bmpHSize; - Header->height = bmpVSize; - Header->planes = 1; - Header->bits = nbByte_Pixels * 8; - Header->compression = 0; - Header->imageSize = bmpHSize * bmpVSize * nbByte_Pixels; - Header->xresolution = 0; - Header->yresolution = 0; - Header->ncolours = 0; - Header->importantcolours = 0; -} - - -//------------------------------------------------------------------------------ -/// debug function, dislay BMP header -/// \param pAddressHeader Address of the BMP -//------------------------------------------------------------------------------ -void BMP_displayHeader(unsigned int* pAddressHeader) -{ - struct BMPHeader *header; - - header = (struct BMPHeader*) pAddressHeader; - - TRACE_INFO("BMP\n\r"); - TRACE_INFO("type 0x%X \n\r", header->type); - TRACE_INFO("fileSize %d \n\r", header->fileSize); - TRACE_INFO("reserved1 %d \n\r", header->reserved1); - TRACE_INFO("reserved2 %d \n\r", header->reserved2); - TRACE_INFO("offset %d \n\r", header->offset); - TRACE_INFO("headerSize %d \n\r", header->headerSize); - TRACE_INFO("width %d \n\r", header->width); - TRACE_INFO("height %d \n\r", header->height); - TRACE_INFO("planes %d \n\r", header->planes); - TRACE_INFO("bits %d \n\r", header->bits); - TRACE_INFO("compression %d \n\r", header->compression); - TRACE_INFO("imageSize %d \n\r", header->imageSize); - TRACE_INFO("xresolution %d \n\r", header->xresolution); - TRACE_INFO("yresolution %d \n\r", header->yresolution); - TRACE_INFO("ncolours %d \n\r", header->ncolours); - TRACE_INFO("importantcolours %d\n\r", header->importantcolours); -} - - -//------------------------------------------------------------------------------ -/// Loads a BMP image located at the given address, decodes it and stores the -/// resulting image inside the provided buffer. Image must have the specified -/// width & height. -/// If no buffer is provided, this function simply checks if it is able to -/// decode the image. -/// \param file Buffer which holds the BMP file. -/// \param buffer Buffer in which to store the decoded image. -/// \param width Buffer width in pixels. -/// \param height Buffer height in pixels. -/// \param bpp Number of bits per pixels that the buffer stores. -/// \return 0 if the image has been loaded; otherwise returns an error code. -//------------------------------------------------------------------------------ -unsigned char BMP_Decode( - void *file, - unsigned char *buffer, - unsigned int width, - unsigned int height, - unsigned char bpp) -{ - struct BMPHeader *header; - unsigned int i, j; - unsigned char r, g, b; - unsigned char *image; - - // Read header information - header = (struct BMPHeader *) file; - - // Verify that the file is valid - if (!BMP_IsValid(file)) { - - TRACE_ERROR("BMP_Decode: File type is not 'BM' (0x%04X).\n\r",header->type); - return 1; - } - - // Check that parameters match - if ((header->compression != 0) - || (header->width != width) - || (header->height != height)) { - - TRACE_ERROR("BMP_Decode: File format not supported\n\r"); - TRACE_ERROR(" -> .compression = %u\n\r", header->compression); - TRACE_ERROR(" -> .width = %u\n\r", header->width); - TRACE_ERROR(" -> .height = %u\n\r", header->height); - TRACE_ERROR(" -> .bits = %d\n\r", header->bits); - return 2; - } - - // Get image data - image = (unsigned char *) ((unsigned int) file + header->offset); - - // Check that the bpp resolution is supported - // Only a 24-bit output & 24- or 8-bit input are supported - if (bpp != 24) { - - TRACE_ERROR("BMP_Decode: Output resolution not supported\n\r"); - return 3; - } - else if (header->bits == 24) { - - // Decoding is ok - if (!buffer) return 0; - - // Get image data (swapping red & blue) - for (i=0; i < height; i++) { - for (j=0; j < width; j++) { - - r = image[((height - i - 1) * width + j) * 3 + 2]; - g = image[((height - i - 1) * width + j) * 3 + 1]; - b = image[((height - i - 1) * width + j) * 3]; - -#if defined(BOARD_LCD_RGB565) - // Interlacing - r = ((r << 1) & 0xF0) | ((g & 0x80) >> 4) | ((r & 0x80) >> 5); - g = (g << 1) & 0xF8; - b = b & 0xF8; - - buffer[(i * width + j) * 3] = b; - buffer[(i * width + j) * 3 + 1] = g; - buffer[(i * width + j) * 3 + 2] = r; - -#else - buffer[(i * width + j) * 3] = r; - buffer[(i * width + j) * 3 + 1] = g; - buffer[(i * width + j) * 3 + 2] = b; -#endif //#if defined(BOARD_LCD_RGB565) - } - } - } - else if (header->bits == 8) { - - // Decoding is ok - if (!buffer) return 0; - - // Retrieve palette - struct BMPPaletteEntry palette[256]; - memcpy(palette, - (unsigned char *) ((unsigned int) file + sizeof(struct BMPHeader)), - header->offset - sizeof(struct BMPHeader)); - - // Decode image (reversing row order) - for (i=0; i < height; i++) { - for (j=0; j < width; j++) { - - r = palette[image[(height - i - 1) * width + j]].r; - g = palette[image[(height - i - 1) * width + j]].g; - b = palette[image[(height - i - 1) * width + j]].b; - - buffer[(i * width + j) * 3] = r; - buffer[(i * width + j) * 3 + 1] = g; - buffer[(i * width + j) * 3 + 2] = b; - } - } - } - else { - - TRACE_ERROR("BMP_Decode: Input resolution not supported\n\r"); - TRACE_INFO("header->bits 0x%X \n\r", header->bits); - return 4; - } - - return 0; -} - -//------------------------------------------------------------------------------ -/// Convert RGB 565 to RGB 555 (RGB 555 is adapted to LCD) -/// \param fileSource Buffer which holds the RGB file -/// \param fileDestination Buffer in which to store the decoded image -/// \param width Buffer width in pixels. -/// \param height Buffer height in pixels. -/// \param bpp Number of bits per pixels that the buffer stores. -//------------------------------------------------------------------------------ -void RGB565toBGR555( - unsigned char *fileSource, - unsigned char *fileDestination, - unsigned int width, - unsigned int height, - unsigned char bpp) -{ - unsigned int i; - unsigned int j; - unsigned int row; - - for (i=0; i < height*(bpp/8); i++) { - row = (i*width*(bpp/8)); - for (j=0; j <= width*(bpp/8); j+=2) { - fileDestination[row+j] = ((fileSource[row+j+1]>>3)&0x1F) - | (fileSource[row+j]&0xE0); - fileDestination[row+j+1] = (fileSource[row+j+1]&0x03) - | ((fileSource[row+j]&0x1F)<<2); - } - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bmp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bmp.h deleted file mode 100644 index 81280b226..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/bmp.h +++ /dev/null @@ -1,130 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Utility for BMP -/// -//------------------------------------------------------------------------------ - -#ifndef BMP_H -#define BMP_H - -/// BMP magic number ('BM'). -#define BMP_TYPE 0x4D42 - -/// headerSize must be set to 40 -#define BITMAPINFOHEADER 40 - -//------------------------------------------------------------------------------ -// Exported types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -// BMP (Windows) Header Format -struct BMPHeader { - /// signature, must be 4D42 hex - unsigned short type; - /// size of BMP file in bytes (unreliable) - unsigned int fileSize; - /// reserved, must be zero - unsigned short reserved1; - /// reserved, must be zero - unsigned short reserved2; - /// offset to start of image data in bytes - unsigned int offset; - /// size of BITMAPINFOHEADER structure, must be 40 - unsigned int headerSize; - /// image width in pixels - unsigned int width; - /// image height in pixels - unsigned int height; - /// number of planes in the image, must be 1 - unsigned short planes; - /// number of bits per pixel (1, 4, 8, 16, 24, 32) - unsigned short bits; - /// compression type (0=none, 1=RLE-8, 2=RLE-4) - unsigned int compression; - /// size of image data in bytes (including padding) - unsigned int imageSize; - /// horizontal resolution in pixels per meter (unreliable) - unsigned int xresolution; - /// vertical resolution in pixels per meter (unreliable) - unsigned int yresolution; - /// number of colors in image, or zero - unsigned int ncolours; - /// number of important colors, or zero - unsigned int importantcolours; - -} __attribute__ ((packed)); // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char BMP_IsValid(void *file); - -extern unsigned int BMP_GetFileSize(void *file); - -extern unsigned char BMP_Decode( - void *file, - unsigned char *buffer, - unsigned int width, - unsigned int height, - unsigned char bpp); - -extern void WriteBMPheader(unsigned int* pAddressHeader, - unsigned int bmpHSize, - unsigned int bmpVSize, - unsigned char bmpRgb, - unsigned char nbByte_Pixels); - -extern void BMP_displayHeader(unsigned int* pAddressHeader); - -extern void RGB565toBGR555( - unsigned char *fileSource, - unsigned char *fileDestination, - unsigned int width, - unsigned int height, - unsigned char bpp); - - -#endif //#ifndef BMP_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/clock.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/clock.c deleted file mode 100644 index c298fb799..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/clock.c +++ /dev/null @@ -1,259 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "clock.h" -#include -#include - -//------------------------------------------------------------------------------ -// Internal types -//------------------------------------------------------------------------------ -int currentConfig = 0; // 0 have to be the default configuration - -//------------------------------------------------------------------------------ -/// Describes a possible clock configuration (processor clock & master clock), -/// including the necessary register values. -//------------------------------------------------------------------------------ -struct ClockConfiguration { - - /// Processor clock frequency (in MHz). - unsigned short pck; - /// Master clock frequency (in MHz). - unsigned short mck; - /// CKGR_PLL reqister value. - unsigned int pllr; - /// PMC_MCKR register value. - unsigned int mckr; -}; - -//------------------------------------------------------------------------------ -// Internal variables -//------------------------------------------------------------------------------ - -// Clock configurations for the AT91SAM9263-EK -#if defined(at91sam9263) - -#define AT91C_CKGR_PLLR AT91C_CKGR_PLLAR -#define AT91C_PMC_LOCK AT91C_PMC_LOCKA - -static const struct ClockConfiguration clockConfigurations[] = { - // PCK = 200 MHz, MCK = 100 MHz - {200, 100, 0x206DBF09, 0x00000102}, - // PCK = 240 MHz, MCK = 120 MHz - {240, 120, 0x202BC003, 0x00000102}, - // PCK = 120 MHz, MCK = 120 MHz - {120, 120, 0x20156003, 0x00000002}, - // PCK = 96 MHz, MCK = 48 MHz - {96, 48, 0x2057400F, 0x00000102}, - // PCK = 48 MHz, MCK = 48 MHz - {48, 48, 0x2057400F, 0x00000006} -}; - -// Clock configurations for the AT91SAM9G20-EK -#elif defined(at91sam9g20) - -#define AT91C_CKGR_PLLR AT91C_CKGR_PLLAR -#define AT91C_PMC_LOCK AT91C_PMC_LOCKA - -static const struct ClockConfiguration clockConfigurations[] = { - - // PCK = 400 MHz, MCK = 133 MHz - {400, 133, 0x202A0101, 0x00001302}, - // PCK = 200 MHz, MCK = 100 MHz - {200, 100, 0x202A3F01, 0x0000010A}, - // PCK = 96 MHz, MCK = 48 MHz - {96, 48, 0x207C3F03, 0x0000010E}, - // PCK = 48 MHz, MCK = 48 MHz - {48, 48, 0x207C3F03, 0x00000012} -}; - -// Clock configurations for the AT91SAM9XE-EK, AT91SAM9261-EK -#elif defined(at91sam9xe128) || \ - defined(at91sam9xe256) || \ - defined(at91sam9xe512) || \ - defined(at91sam9261) - -#define AT91C_CKGR_PLLR AT91C_CKGR_PLLAR -#define AT91C_PMC_LOCK AT91C_PMC_LOCKA - -static const struct ClockConfiguration clockConfigurations[] = { - - // PCK = 200 MHz, MCK = 100 MHz - {200, 100, 0x208CBF0D, 0x00000102}, - // PCK = 100 MHz, MCK = 100 MHz - {100, 100, 0x20273F07, 0x00000002}, - // PCK = 96 MHz, MCK = 48 MHz - {96, 48, 0x20483F0E, 0x00000102}, - // PCK = 48 MHz, MCK = 48 MHz - {48, 48, 0x20483F0E, 0x00000006} -}; - -// Clock configurations for the AT91SAM9RL64-EK, AT91CAP9-DK, AT91CAP9-STK -#elif defined(at91sam9rl64) || \ - defined(at91cap9) - -#define AT91C_CKGR_PLLR AT91C_CKGR_PLLAR -#define AT91C_PMC_LOCK AT91C_PMC_LOCKA - -static const struct ClockConfiguration clockConfigurations[] = { - - // PCK = 200 MHz, MCK = 100 MHz - {200, 100, 0x2031BF03, 0x00000102}, - // PCK = 100 MHz, MCK = 100 MHz - {100, 100, 0x20183F03, 0x00000002}, - // PCK = 96 MHz, MCK = 48 MHz - {96, 48, 0x20073F01, 0x00000102}, - // PCK = 48 MHz, MCK = 48 MHz - {48, 48, 0x20073F01, 0x00000006} -}; - -// Clock configuration for the AT91SAM7X-EK, AT91SAM7S-EK, AT91SAM7SE-EK -#elif defined(at91sam7x128) || defined(at91sam7x256) || defined(at91sam7x512) \ - || defined(at91sam7xc128) || defined(at91sam7xc256) || defined(at91sam7xc512) \ - || defined(at91sam7s16) || defined(at91sam7s161) || defined(at91sam7s32) \ - || defined(at91sam7s321) || defined(at91sam7s64) || defined(at91sam7s128) \ - || defined(at91sam7s256) || defined(at91sam7s512) || defined(at91sam7se32) \ - || defined(at91sam7se256) || defined(at91sam7se512) - -static const struct ClockConfiguration clockConfigurations[] = { - - // PCK = 55 MHz, MCK = 55 MHz - {55, 55, 0x006A3F12, 0x00000007}, - // PCK = 48 MHz, MCK = 48 MHz - {48, 48, 0x00483F0E, 0x00000007}, -}; - -// Clock configuration for the AT91SAM7A3 -#elif defined(at91sam7a3) - -static const struct ClockConfiguration clockConfigurations[] = { - - // PCK = 60 MHz, MCK = 60 MHz - {60, 60, 0x000C3F02, 0x00000007}, - // PCK = 48 MHz, MCK = 48 MHz - {48, 48, 0x00483F0E, 0x00000007} -}; - -// No clock configuration -#else - #error No clock configuration for this board. -#endif - -/// Number of available clock configurations -#define NB_CLOCK_CONFIGURATION (sizeof(clockConfigurations)/sizeof(clockConfigurations[0])) - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Sets the specified clock configuration. -/// \param configuration Index of the configuration to set. -//------------------------------------------------------------------------------ -void CLOCK_SetConfig(unsigned char configuration) -{ - printf("Setting clock configuration #%d ... ", configuration); - currentConfig = configuration; - - // Switch to main oscillator in two operations - PMC->PMC_MCKR = (PMC->PMC_MCKR & ~AT91C_PMC_CSS) | AT91C_PMC_CSS_MAIN_CLK; - while ((PMC->PMC_SR & AT91C_PMC_MCKRDY) == 0); - - // Configure PLL - *AT91C_CKGR_PLLAR = clockConfigurations[configuration].pllr; - while ((PMC->PMC_SR & AT91C_PMC_LOCKA) == 0); - - // Configure master clock in two operations - PMC->PMC_MCKR = (clockConfigurations[configuration].mckr & ~AT91C_PMC_CSS) | AT91C_PMC_CSS_MAIN_CLK; - while ((PMC->PMC_SR & AT91C_PMC_MCKRDY) == 0); - PMC->PMC_MCKR = clockConfigurations[configuration].mckr; - while ((PMC->PMC_SR & AT91C_PMC_MCKRDY) == 0); - - // DBGU reconfiguration - DBGU_Configure(DBGU_STANDARD, 115200, clockConfigurations[configuration].mck*1000000); - printf("done.\n\r"); -} - -//------------------------------------------------------------------------------ -/// Display the user menu on the DBGU. -//------------------------------------------------------------------------------ -void CLOCK_DisplayMenu(void) -{ - unsigned int i; - - printf("\n\rMenu Clock configuration:\n\r"); - for (i = 0; i < NB_CLOCK_CONFIGURATION; i++) { - - printf(" %d: Set PCK = %3d MHz, MCK = %3d MHz %s\n\r", - i, - clockConfigurations[i].pck, - clockConfigurations[i].mck, - (currentConfig==i)?"(curr)":""); - } -} - -//------------------------------------------------------------------------------ -/// Get the current MCK -//------------------------------------------------------------------------------ -unsigned short CLOCK_GetCurrMCK(void) -{ - return clockConfigurations[currentConfig].mck; -} - -//------------------------------------------------------------------------------ -/// Get the current PCK -//------------------------------------------------------------------------------ -unsigned short CLOCK_GetCurrPCK(void) -{ - return clockConfigurations[currentConfig].pck; -} - -//------------------------------------------------------------------------------ -/// Change clock configuration. -//------------------------------------------------------------------------------ -void CLOCK_UserChangeConfig(void) -{ - unsigned char key = 0; - - while (1) - { - CLOCK_DisplayMenu(); - key = DBGU_GetChar(); - - if ((key >= '0') && (key <= ('0' + NB_CLOCK_CONFIGURATION - 1))) - { - CLOCK_SetConfig(key - '0'); - break; - } - } -} \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/clock.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/clock.h deleted file mode 100644 index 54083008d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/clock.h +++ /dev/null @@ -1,47 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef CLOCK_H -#define CLOCK_H - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -extern void CLOCK_SetConfig(unsigned char configuration); - -extern void CLOCK_DisplayMenu(void); - -extern void CLOCK_UserChangeConfig(void); - -extern unsigned short CLOCK_GetCurrMCK(void); - -extern unsigned short CLOCK_GetCurrPCK(void); - -#endif //#ifndef FREQCONF_H diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_hardware.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_hardware.c deleted file mode 100644 index 1501afef0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_hardware.c +++ /dev/null @@ -1,316 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Function: Firmware encryption using hardware acceleration -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include "aes_hardware.h" - -#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_HARD) -#include -#include -#include -#include -#include -#include -#include - -//------------------------------------------------------------------------------ -// Inline functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Converts an ASCII value to an hexadecimal one -/// \param ASCII string -/// \param Buffer to store integer value -/// \param Length of string -//------------------------------------------------------------------------------ -static inline void ASCII2Hex(const unsigned char * ascii, - unsigned char * binary, - unsigned int length) -{ - unsigned int i; - - for (i=0; i < length; i++) { - if (ascii[i*2] >= 'A') { - binary[i] = ascii[i*2] - 'A' + 10; - } - else { - binary[i] = ascii[i*2] - '0'; - } - binary[i] <<= 4; - if (ascii[i*2+1] >= 'A') { - binary[i] += ascii[i*2+1] - 'A' + 10; - } - else { - binary[i] += ascii[i*2+1] - '0'; - } - } -} - -//------------------------------------------------------------------------------ -// Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Initializes the AES peripheral -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -void aes_hard_init(void) -{ - unsigned char key[16]; - -#if defined(ENCRYPTION_CTR) || defined(ENCRYPTION_CBC) - unsigned char IV[16]; -#endif - - TRACE_DEBUG("AES/HARD: Initializing ...\n\r"); - - // Activate peripheral clock -#ifdef AT91C_ID_AES - PMC_EnablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_EnablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_EnablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - - // Load mode -#if defined(ENCRYPTION_ECB) - //AES_Configure(AT91C_AES_CIPHER, AT91C_AES_SMOD_PDC, AT91C_AES_OPMOD_ECB); - - AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_ECB; -#elif defined(ENCRYPTION_CBC) - AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_CBC; -#elif defined(ENCRYPTION_CTR) - AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_CTR; -#endif - - // Convert and load key - ASCII2Hex((unsigned char*)ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - AES_SetKey((unsigned int*)key); - - // Convert and load IV -#if defined(ENCRYPTION_CTR) || defined(ENCRYPTION_CBC) - ASCII2Hex((unsigned char*)ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - AES_SetVector((unsigned int*)IV); -#endif - - TRACE_DEBUG("AES/HARD: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the AES peripheral for CBC mode -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -#if defined(ENCRYPTION_CBC) -void aes_hard_init_CBC(void) -{ - unsigned char key[16]; - unsigned char IV[16]; - - TRACE_DEBUG("aes_hard_init_CBC\n\r"); - - // Activate peripheral clock -#ifdef AT91C_ID_AES - PMC_EnablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_EnablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_EnablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - - // Load mode - AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_CBC; - - // Convert and load key - ASCII2Hex((unsigned char*)ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - AES_SetKey((unsigned int*)key); - - // Convert and load IV - ASCII2Hex((unsigned char*)ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - AES_SetVector((unsigned int*)IV); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the AES peripheral for CTR mode -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -void aes_hard_init_CTR(void) -{ - unsigned char key[16]; - unsigned char IV[16]; - - TRACE_DEBUG("aes_hard_init_CTR\n\r"); - - // Activate peripheral clock -#ifdef AT91C_ID_AES - PMC_EnablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_EnablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_EnablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - - // Load mode - AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_CTR; - - // Convert and load key - ASCII2Hex((unsigned char*)ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - AES_SetKey((unsigned int*)key); - - // Convert and load IV - ASCII2Hex((unsigned char*)ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - AES_SetVector((unsigned int*)IV); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the AES peripheral for ECB mode -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) -void aes_hard_init_ECB(void) -{ - unsigned char key[16]; - - TRACE_DEBUG("aes_hard_init_ECB\n\r"); - - // Activate peripheral clock -#ifdef AT91C_ID_AES - PMC_EnablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_EnablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_EnablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - - // Load mode - //AES_Configure(AT91C_AES_CIPHER, AT91C_AES_SMOD_MANUAL, AT91C_AES_OPMOD_ECB); - AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_ECB; - - // Convert and load key - ASCII2Hex((unsigned char*)ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - AES_SetKey((unsigned int*)key); -} -#endif -#endif // ONLY_ONE_ENCRYPTION - -//------------------------------------------------------------------------------ -/// Cleans up the AES peripheral -//------------------------------------------------------------------------------ -void aes_hard_cleanup(void) -{ - TRACE_DEBUG("AES/HARD: Cleaning up ...\n\r"); - - AT91C_BASE_AES->AES_MR = 0; - -#ifdef AT91C_ID_AES - PMC_DisablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_DisablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_DisablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - - // Close PDC - AT91C_BASE_PDC_AES->PDC_PTCR = AT91C_PDC_RXTDIS; - AT91C_BASE_PDC_AES->PDC_PTCR = AT91C_PDC_TXTDIS; - - // Reset all Counter register Next buffer first - AT91C_BASE_PDC_AES->PDC_TNPR = 0; - AT91C_BASE_PDC_AES->PDC_TNCR = 0; - AT91C_BASE_PDC_AES->PDC_RPR = 0; - AT91C_BASE_PDC_AES->PDC_RCR = 0; - AT91C_BASE_PDC_AES->PDC_TPR = 0; - AT91C_BASE_PDC_AES->PDC_TCR = 0; - AT91C_BASE_PDC_AES->PDC_RPR = 0; - AT91C_BASE_PDC_AES->PDC_RCR = 0; - - TRACE_DEBUG("AES/HARD: Cleanup done.\n\r"); -} - -//------------------------------------------------------------------------------ -/// Decrypts a variable-length cipher text -/// \param pCipherText text to decrypt -/// \param pPlainText to store plain text -/// \param length of cipher text (in bytes) -/// \return: 1 if ok, 0 if error -//------------------------------------------------------------------------------ -int aes_hard_decrypt(const unsigned char *pCipherText, - unsigned char *pPlainText, - unsigned int length) -{ - TRACE_DEBUG("aes_hard_decrypt\n\r"); - - // Check parameters - if ((pCipherText == NULL) || (pPlainText == NULL)) { - return 0; - } - - // Set source and destination buffers in PDC - AT91C_BASE_PDC_AES->PDC_TPR = (unsigned int) pCipherText; - AT91C_BASE_PDC_AES->PDC_RPR = (unsigned int) pPlainText; - - AT91C_BASE_PDC_AES->PDC_TCR = length >> 2; - AT91C_BASE_PDC_AES->PDC_RCR = length >> 2; - - // Start decryption and wait - AT91C_BASE_PDC_AES->PDC_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN; - while (((AES_GetStatus()) & AT91C_AES_ENDRX) == 0); - - return 1; -} - -#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_HARD) - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_hardware.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_hardware.h deleted file mode 100644 index 62f38a7fe..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_hardware.h +++ /dev/null @@ -1,100 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// Firmware encryption using AES hardware acceleration -/// This code is based on the AES reference implementation published by Paulo -/// Barreto and Vincent Rijmen. -/// -/// !Usage -/// -/// -# aes_hard_init: Initialize AES hardware -/// -# aes_hard_init_CBC: for the CBC mode -/// -# aes_hard_init_CTR: for the CTR mode -/// -# aes_hard_init_ECB: for the ECB mode -/// -# aes_hard_cleanup: Cleans up AES -/// -# aes_hard_decrypt: Decrypts a variable-length cipher text -//------------------------------------------------------------------------------ - -#ifndef BOOTLOADER_AES_HARDWARE_H -#define BOOTLOADER_AES_HARDWARE_H - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "config.h" - -#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_HARD) - -//------------------------------------------------------------------------------ -// Check configuration -//------------------------------------------------------------------------------ -#if (ENCRYPTION_KEY_LENGTH != 16) - #error Hardware AES acceleration only supports 128 bits keys. -#endif - -#if (ENCRYPTION_BLOCK_LENGTH != 16) - #error Hardware AES acceleration only supports 128 bits blocks. -#endif - -#if !defined(ENCRYPTION_ECB) && \ - !defined(ENCRYPTION_CBC) && \ - !defined(ENCRYPTION_CTR) - #error Only ECB, CBC & CTR modes are supported. -#endif - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -#define ENCRYPTION_INIT aes_hard_init -#define ENCRYPTION_CLEANUP aes_hard_cleanup -#define ENCRYPTION_DECRYPT aes_hard_decrypt -#endif - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -extern void aes_hard_init(void); -#ifndef ONLY_ONE_ENCRYPTION -extern void aes_hard_init_CBC(void); -extern void aes_hard_init_CTR(void); -extern void aes_hard_init_ECB(void); -#endif -extern void aes_hard_cleanup(void); -extern int aes_hard_decrypt(const unsigned char *, unsigned char *, unsigned int); - -#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_HARD) -#endif // BOOTLOADER_AES_HARDWARE_H - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_reference.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_reference.c deleted file mode 100644 index a94844ab3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_reference.c +++ /dev/null @@ -1,801 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Firmware encryption using AES reference implementation -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "aes_reference.h" - -#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_REF) -#include -#include -#include -#include -#include -#include - -//------------------------------------------------------------------------------ -// Global variables -//------------------------------------------------------------------------------ -#define word8 static unsigned char -#define word32 static unsigned int - -#include "boxes-ref.dat" - -static unsigned char shifts[3][2][4] = { - {{0,1,2,3}, {0,3,2,1}}, - {{0,1,2,3}, {0,5,4,3}}, - {{0,7,5,5}, {0,1,3,4}} -}; - -static unsigned char key[KC][4]; -static unsigned char expandedKey[ROUNDS+1][BC][4]; -static unsigned int T0[256], T1[256], T2[256], T3[256], TF[256]; - -#if defined(ENCRYPTION_CBC) || defined(ENCRYPTION_CTR) -static unsigned char IV[BC][4]; -#endif - -//------------------------------------------------------------------------------ -// Inline functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Multiply two elements of GF(2^m) needed for MixColumn and InvMixColumn -/// \param a first element -/// \param b second element -/// \return result of operation -//------------------------------------------------------------------------------ -static unsigned char mul(unsigned char a, unsigned char b) -{ - if (a && b) { - return Alogtable[(Logtable[a] + Logtable[b])%255]; - } - else { - return 0; - } -} - -//------------------------------------------------------------------------------ -/// Returns the minimum between two numbers -/// \param First number -/// \param Second number -/// \return Minimum between the two operands -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -static unsigned int min(unsigned int number1, unsigned int number2) -{ - if (number1 > number2) { - return number2; - } - else { - return number1; - } -} -#endif - -//------------------------------------------------------------------------------ -/// XOR text and round key together -/// \param Plain text -/// \param Round key -//------------------------------------------------------------------------------ -static inline void addRoundKey(unsigned char a[BC][4], const unsigned char rk[BC][4]) -{ - unsigned int i; - - for (i=0; i < BC; i++) { - ((int *) a)[i] ^= ((int *) rk)[i]; - } -} - -//------------------------------------------------------------------------------ -/// Performs the AES key schedule -/// \param Key to use -/// \param Buffer to store expanded key schedule -//------------------------------------------------------------------------------ -static inline void keySchedule(unsigned char k[KC][4], unsigned char W[ROUNDS+1][BC][4]) -{ - int t; - int rconpointer = 0; - unsigned int j; - unsigned char tk[KC][4]; - - for(j=0; j < KC; j++) { - ((int *) tk)[j] = ((int *) k)[j]; - } - - t = 0; - /* copy values into round key array */ - for(j=0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) { - ((int *) W[t / BC])[t%BC] = ((int *) tk)[j]; - } - - while (t < (ROUNDS+1)*BC) { - - tk[0][0] ^= S[tk[KC-1][1]] ^ rcon[rconpointer++]; - tk[0][1] ^= S[tk[KC-1][2]]; - tk[0][2] ^= S[tk[KC-1][3]]; - tk[0][3] ^= S[tk[KC-1][0]]; - - if (KC != 8) { - for(j=1; j < KC; j++) { - ((int *) tk)[j] ^= ((int *) tk)[j-1]; - } - } - else { - for(j=1; j < KC/2; j++) { - ((int *) tk)[j] ^= ((int *) tk)[j-1]; - } - tk[KC/2][0] ^= S[tk[KC/2 - 1][0]]; - tk[KC/2][1] ^= S[tk[KC/2 - 1][1]]; - tk[KC/2][2] ^= S[tk[KC/2 - 1][2]]; - tk[KC/2][3] ^= S[tk[KC/2 - 1][3]]; - - for(j=KC/2+1; j < KC; j++) { - ((int *) tk)[j] ^= ((int *) tk)[j-1]; - } - } - - // copy values into round key array - for(j=0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) { - ((int *) W[t/BC])[t%BC] = ((int *) tk)[j]; - } - } -} - -//------------------------------------------------------------------------------ -/// Performs the AES inverse key schedule -/// \param Key to use -/// \param Buffer to store expanded key schedule -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) || defined(ENCRYPTION_CBC) -static inline void invKeySchedule(unsigned char k[KC][4], - unsigned char W[ROUNDS+1][BC][4]) -{ - unsigned int r; - unsigned int j; - unsigned char tmp[4]; - - // Expand key normally - keySchedule(k, W); - - // Apply invMixColumns to all rounds except first and last one - for (r=1; r < ROUNDS; r++) { - for (j=0; j < BC; j++) { - tmp[0] = mul(0x0E, W[r][j][0]) ^ mul(0x0B, W[r][j][1]) ^ - mul(0x0D, W[r][j][2]) ^ mul(0x09, W[r][j][3]); - tmp[1] = mul(0x0E, W[r][j][1]) ^ mul(0x0B, W[r][j][2]) ^ - mul(0x0D, W[r][j][3]) ^ mul(0x09, W[r][j][0]); - tmp[2] = mul(0x0E, W[r][j][2]) ^ mul(0x0B, W[r][j][3]) ^ - mul(0x0D, W[r][j][0]) ^ mul(0x09, W[r][j][1]); - tmp[3] = mul(0x0E, W[r][j][3]) ^ mul(0x0B, W[r][j][0]) ^ - mul(0x0D, W[r][j][1]) ^ mul(0x09, W[r][j][2]); - W[r][j][0] = tmp[0]; - W[r][j][1] = tmp[1]; - W[r][j][2] = tmp[2]; - W[r][j][3] = tmp[3]; - } - } -} -#endif - -//------------------------------------------------------------------------------ -/// Perform the RotBytes operation needed by the AES cipher -/// \param input to rotate -/// \return Rotated word -//------------------------------------------------------------------------------ -static inline unsigned int rotBytes(unsigned int input) -{ - return ((input << 8) | (input >> 24)); -} - -//------------------------------------------------------------------------------ -/// Generates the lookup tables needed for encryption -/// \param Pointer to t0 -/// \param Pointer to t1 -/// \param Pointer to t2 -/// \param Pointer to t3 -/// \param Pointer to tf -/// \param Box -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -static inline void generateEncryptionLUTs(unsigned int * t0, - unsigned int * t1, - unsigned int * t2, - unsigned int * t3, - unsigned int * tf, - unsigned char box[256]) -{ - unsigned int a; - - for (a=0; a <= 255; a++) { - // Calc t0 - t0[a] = (mul(2, box[a])) | - (box[a] << 8) | - (box[a] << 16) | - (mul(3, box[a]) << 24); - - // Calc t1, t2, t3 - t1[a] = rotBytes(t0[a]); - t2[a] = rotBytes(t1[a]); - t3[a] = rotBytes(t2[a]); - - // Calc tf - tf[a] = box[a] | (box[a] << 8) | (box[a] << 16) | (box[a] << 24); - } -} -#endif - -//------------------------------------------------------------------------------ -/// Generates the lookup tables needed for decryption -/// \param Pointer to t0 -/// \param Pointer to t1 -/// \param Pointer to t2 -/// \param Pointer to t3 -/// \param Pointer to tf -/// \param Box -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) || defined(ENCRYPTION_CBC) -static inline void generateDecryptionLUTs(unsigned int * t0, - unsigned int * t1, - unsigned int * t2, - unsigned int * t3, - unsigned int * tf, - unsigned char box[256]) -{ - unsigned int a; - - for (a=0; a <= 255; a++) { - - // Calc t0 - t0[a] = (mul(0x0E, box[a])) | - (mul(0x09, box[a]) << 8) | - (mul(0x0D, box[a]) << 16) | - (mul(0x0B, box[a]) << 24); - - // Calc t1, t2, t3 - t1[a] = rotBytes(t0[a]); - t2[a] = rotBytes(t1[a]); - t3[a] = rotBytes(t2[a]); - - // Calc tf - tf[a] = box[a] | (box[a] << 8) | (box[a] << 16) | (box[a] << 24); - } -} -#endif - -//------------------------------------------------------------------------------ -/// Copies a block to a buffer -/// \param Block to copy -/// \param Buffer to store copy -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -static void copyBlock(unsigned char input[BC][4], unsigned char output[BC][4]) -{ - unsigned int j; - - for (j=0; j < BC; j++) { - ((int *) output)[j] = ((int *) input)[j]; - } -} -#endif - -//------------------------------------------------------------------------------ -/// Encrypts a block of plain text using precalculated LUTs -/// \param Block of plain text to encrypt -/// \param Expanded key -/// \param Pointer to t0 -/// \param Pointer to t1 -/// \param Pointer to t2 -/// \param Pointer to t3 -/// \param Pointer to tf -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -static inline void encrypt(unsigned char a[BC][4], - const unsigned char rk[ROUNDS+1][BC][4], - unsigned int * t0, - unsigned int * t1, - unsigned int * t2, - unsigned int * t3, - unsigned int * tf) -{ - unsigned char b[BC][4]; - unsigned int r; - unsigned int j; - - // First key addition - addRoundKey(a, rk[0]); - - // ROUNDS-1 ordinary rounds - for(r=1; r < ROUNDS; r++) { - for (j=0; j < BC; j++) { - - ((int *) b)[j] = t0[a[j][0]] ^ - t1[a[(j+shifts[SC][0][1])%BC][1]] ^ - t2[a[(j+shifts[SC][0][2])%BC][2]] ^ - t3[a[(j+shifts[SC][0][3])%BC][3]] ^ - ((int *) rk[r])[j]; - } - if ((++r) == ROUNDS) { - break; - } - for (j=0; j < BC; j++) { - ((int *) a)[j] = t0[b[j][0]] ^ - t1[b[(j+shifts[SC][0][1])%BC][1]] ^ - t2[b[(j+shifts[SC][0][2])%BC][2]] ^ - t3[b[(j+shifts[SC][0][3])%BC][3]] ^ - ((int *) rk[r])[j]; - } - } - - // Last round (no MixColumns) - for (j=0; j < BC; j++) { - ((int *) a)[j] = (t0f[b[j][0]]) ^ - (t1f[b[(j+shifts[SC][0][1])%BC][1]]) ^ - (t2f[b[(j+shifts[SC][0][2])%BC][2]]) ^ - (t3f[b[(j+shifts[SC][0][3])%BC][3]]) ^ - ((int *) rk[ROUNDS])[j]; - } -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypts a block of plain text using precalculated LUTs -/// \param Block of cipher text to decrypt -/// \param Expanded key -/// \param Pointer to t0 -/// \param Pointer to t1 -/// \param Pointer to t2 -/// \param Pointer to t3 -/// \param Pointer to tf -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) || defined(ENCRYPTION_CBC) -static inline void decrypt(unsigned char a[BC][4], - const unsigned char rk[ROUNDS+1][BC][4], - unsigned int * t0, - unsigned int * t1, - unsigned int * t2, - unsigned int * t3, - unsigned int * tf) -{ - unsigned char b[BC][4]; - unsigned int r; - unsigned int j; - - // First key addition - addRoundKey(a, rk[ROUNDS]); - - // ROUNDS-1 ordinary rounds - for(r=ROUNDS-1; r > 0; r--) { - for (j=0; j < BC; j++) { - ((int *) b)[j] = t0[a[j][0]] ^ - t1[a[(j+shifts[SC][1][1])%BC][1]] ^ - t2[a[(j+shifts[SC][1][2])%BC][2]] ^ - t3[a[(j+shifts[SC][1][3])%BC][3]] ^ - ((int *) rk[r])[j]; - } - if ((--r) == 0) { - break; - } - for (j=0; j < BC; j++) { - ((int *) a)[j] = t0[b[j][0]] ^ - t1[b[(j+shifts[SC][1][1])%BC][1]] ^ - t2[b[(j+shifts[SC][1][2])%BC][2]] ^ - t3[b[(j+shifts[SC][1][3])%BC][3]] ^ - ((int *) rk[r])[j]; - } - } - // Last round (no MixColumns) - for (j=0; j < BC; j++) { - ((int *) a)[j] = (t0f[b[j][0]]) ^ - (t1f[b[(j+shifts[SC][1][1])%BC][1]]) ^ - (t2f[b[(j+shifts[SC][1][2])%BC][2]]) ^ - (t3f[b[(j+shifts[SC][1][3])%BC][3]]) ^ - ((int *) rk[0])[j]; - } -} -#endif - -//------------------------------------------------------------------------------ -/// Converts an ASCII hexadecimal representation to a raw binary one -/// \param ASCII value -/// \param Buffer to store binary value -/// \param Size of value -//------------------------------------------------------------------------------ -static void ASCII2RawHex(const unsigned char * ascii, - unsigned char * binary, - unsigned int length) -{ - unsigned char * ptr; - unsigned int i; - - ptr = (unsigned char *) binary; - for (i=0; i < length; i++, ptr++, ascii++) { - if (*ascii >= 'A') { - *ptr = *ascii - 'A' + 10; - } - else { - *ptr = *ascii - '0'; - } - *ptr <<= 4; - ascii++; - if (*ascii >= 'A') { - *ptr += *ascii - 'A' + 10; - } - else { - *ptr += *ascii - '0'; - } - } -} - -//------------------------------------------------------------------------------ -/// Decrypts a cipher text using ECB mode -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text -/// \param Expanded key to use -/// \return 0 if successful, 0 otherwise -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) -static unsigned int ecb_decrypt(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length, - unsigned char expandedKey[ROUNDS+1][BC][4]) -{ - unsigned char block[BC][4]; - unsigned int i; - unsigned int l; - - // Check input parameters - if ((cipherText == NULL) || (plainText == NULL) || (expandedKey == NULL)) { - TRACE_DEBUG("AES/REF: NULL parameter(s).\n\r"); - return 0; - } - if (length%ENCRYPTION_BLOCK_LENGTH != 0) { - TRACE_DEBUG("AES/REF: Data length must be a multiple of the cipher block size.\n\r"); - return 0; - } - // ECB decryption - for (l=0; l < length;) { - // Copy cipher text block, decrypt it and copy result - for (i=0; i < ENCRYPTION_BLOCK_LENGTH; i++) { - ((char *) block)[i] = cipherText[l+i]; - } - decrypt(block, expandedKey, T0, T1, T2, T3, TF); - for (i=0; i < ENCRYPTION_BLOCK_LENGTH; i++) { - plainText[l+i] = ((char *) block)[i]; - } - l += ENCRYPTION_BLOCK_LENGTH; - } - - return 1; -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypts a cipher text using CBC mode -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -/// \param Expanded key to use -/// \param Initialization vector to use -/// \return 1 if successful, 0 otherwise */ -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CBC) -static unsigned int cbc_decrypt(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length, - const unsigned char expandedKey[ROUNDS+1][BC][4], - unsigned char IV[BC][4]) -{ - unsigned char block[BC][4]; - unsigned int i; - unsigned int l; - - // Check input parameters - if ((cipherText == NULL) || (plainText == NULL)) { - TRACE_DEBUG("AES/REF: NULL parameter(s).\n\r"); - return 0; - } - if (length%ENCRYPTION_BLOCK_LENGTH != 0) { - TRACE_DEBUG("AES/REF: Cipher text length must be a multiple of the cipher block length.\n\r"); - return 0; - } - // Decrypt data - for (l=0; l < length;) { - // Copy and decrypt a block of cipher text - for (i=0; i < BC; i++) { - ((int *) block)[i] = ((int *) &cipherText[l])[i]; - } - decrypt(block, expandedKey, T0, T1, T2, T3, TF); - // Xor decrypted text & IV, copy new IV - for (i=0; i < BC; i++) { - unsigned int tmp = ((int *) block)[i] ^ ((int *) IV)[i]; - ((int *) IV)[i] = ((int *) &cipherText[l])[i]; - ((int *) &plainText[l])[i] = tmp; - } - - // Loop progression - l += ENCRYPTION_BLOCK_LENGTH; - } - return 1; -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypts a cipher text using CTR mode -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text -/// \param Expanded key to use -/// \param Initialization vector to use -/// \return 1 if successful, 0 otherwise -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -static unsigned int ctr_decrypt(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length, - const unsigned char expandedKey[ROUNDS+1][BC][4], - unsigned char IV[BC][4]) -{ - unsigned char block[BC][4]; - unsigned int bytes; - unsigned int i; - unsigned int l; - int k; - - // Check input parameters - if ((cipherText == NULL) || (plainText == NULL)) { - return 0; - } - for (l=0; l < length;) { - // Copy counter and encrypt it - copyBlock(IV, block); - encrypt(block, expandedKey, T0, T1, T2, T3, TF); - - // XOR current plain text block with encrypted counter - bytes = min(length - l, ENCRYPTION_BLOCK_LENGTH); - - for (i=0; i < bytes; i++) { - plainText[l+i] = cipherText[l+i] ^ ((char *) block)[i]; - } - // Increment counter (big-endian) and number of encrypted bytes - for (k=ENCRYPTION_BLOCK_LENGTH-1; k >= 0; k--) { - if (++((char *) IV)[k] != 0) { - break; - } - } - l += bytes; - } - return 1; -} -#endif - -//------------------------------------------------------------------------------ -// Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Initializes the AES algorithm -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -void aes_ref_init(void) -{ - TRACE_DEBUG("AES/REF: Initializing ...\n\r"); - - ASCII2RawHex((unsigned char*)ENCRYPTION_KEY, (unsigned char*)key, ENCRYPTION_KEY_LENGTH); - -#if defined(ENCRYPTION_ECB) || defined(ENCRYPTION_CBC) - - // Initialize key schedule - invKeySchedule(key, expandedKey); - - // Generate lookup tables - generateDecryptionLUTs(T0, T1, T2, T3, TF, Si); - -#elif defined(ENCRYPTION_CTR) - - // Initialize key schedule - keySchedule(key, expandedKey); - - // Generate lookup tables - generateEncryptionLUTs(T0, T1, T2, T3, TF, S); -#endif - -#if defined(ENCRYPTION_CBC) || defined(ENCRYPTION_CTR) - // Initialize counter - ASCII2RawHex((unsigned char*)ENCRYPTION_IV, (unsigned char*)IV, ENCRYPTION_BLOCK_LENGTH); -#endif - - TRACE_DEBUG("AES/REF: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the AES algorithm mode CBC -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -#if defined(ENCRYPTION_CBC) -void aes_ref_init_CBC(void) -{ - TRACE_DEBUG("aes_ref_init_CBC\n\r"); - - ASCII2RawHex((unsigned char*)ENCRYPTION_KEY, (unsigned char*)key, ENCRYPTION_KEY_LENGTH); - - // Initialize key schedule - invKeySchedule(key, expandedKey); - - // Generate lookup tables - generateDecryptionLUTs(T0, T1, T2, T3, TF, Si); - - // Initialize counter - ASCII2RawHex((unsigned char*)ENCRYPTION_IV, (unsigned char*)IV, ENCRYPTION_BLOCK_LENGTH); - - TRACE_DEBUG("AES/REF: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the AES algorithm mode ECB -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) -void aes_ref_init_ECB(void) -{ - TRACE_DEBUG("aes_ref_init_ECB\n\r"); - - ASCII2RawHex((unsigned char*)ENCRYPTION_KEY, (unsigned char*)key, ENCRYPTION_KEY_LENGTH); - - // Initialize key schedule - invKeySchedule(key, expandedKey); - - // Generate lookup tables - generateDecryptionLUTs(T0, T1, T2, T3, TF, Si); - - TRACE_DEBUG("AES/REF: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the AES algorithm mode CTR -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -void aes_ref_init_CTR(void) -{ - TRACE_DEBUG("aes_ref_init_CTR\n\r"); - - ASCII2RawHex((unsigned char*)ENCRYPTION_KEY, (unsigned char*)key, ENCRYPTION_KEY_LENGTH); - - // Initialize key schedule - keySchedule(key, expandedKey); - - // Generate lookup tables - generateEncryptionLUTs(T0, T1, T2, T3, TF, S); - - // Initialize counter - ASCII2RawHex((unsigned char*)ENCRYPTION_IV, (unsigned char*)IV, ENCRYPTION_BLOCK_LENGTH); - - TRACE_DEBUG("AES/REF: Initialization done.\n\r"); -} -#endif -#endif // ONLY_ONE_ENCRYPTION - -//------------------------------------------------------------------------------ -/// Cleanup the AES algorithm -//------------------------------------------------------------------------------ -void aes_ref_cleanup(void) -{ - TRACE_DEBUG("AES/REF: Cleaning up ...\n\r"); - TRACE_DEBUG("AES/REF: Cleanup done.\n\r"); -} - -//------------------------------------------------------------------------------ -/// Decrypt a cipher text of variable length -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -/// \return 1 if decryption was successful, 0 otherwise. -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -int aes_ref_decrypt(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length) -{ - TRACE_DEBUG("aes_ref_decrypt\n\r"); -#if defined(ENCRYPTION_ECB) - return ecb_decrypt(cipherText, plainText, length, expandedKey); -#elif defined(ENCRYPTION_CBC) - return cbc_decrypt(cipherText, plainText, length, expandedKey, IV);; -#elif defined(ENCRYPTION_CTR) - return ctr_decrypt(cipherText, plainText, length, expandedKey, IV); -#endif -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypt a cipher text of variable length, mode CBC -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -/// \return 1 if decryption was successful, 0 otherwise. -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -#if defined(ENCRYPTION_CBC) -int aes_ref_decrypt_CBC(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length) -{ - TRACE_DEBUG("aes_ref_decrypt_CBC\n\r"); - return cbc_decrypt(cipherText, plainText, length, expandedKey, IV);; -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypt a cipher text of variable length, mode ECB -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -/// \return 1 if decryption was successful, 0 otherwise. -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) -int aes_ref_decrypt_ECB(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length) -{ - TRACE_DEBUG("aes_ref_decrypt_ECB\n\r"); - return ecb_decrypt(cipherText, plainText, length, expandedKey); -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypt a cipher text of variable length, mode CTR -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -/// \return 1 if decryption was successful, 0 otherwise. -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -int aes_ref_decrypt_CTR(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length) -{ - TRACE_DEBUG("aes_ref_decrypt_CTR\n\r"); - return ctr_decrypt(cipherText, plainText, length, expandedKey, IV); -} -#endif - -#endif // ONLY_ONE_ENCRYPTION - -#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_REF) - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_reference.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_reference.h deleted file mode 100644 index a47907bd9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/aes_reference.h +++ /dev/null @@ -1,132 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// Firmware encryption using AES reference implementation -/// -/// !Usage -/// -/// -# aes_ref_init: Initialize AES hardware -/// -# aes_ref_init_CBC: for the CBC mode -/// -# aes_ref_init_ECB: for the CTR mode -/// -# aes_ref_init_CTR: for the ECB mode -/// -# aes_ref_cleanup: Cleans up AES -/// -# aes_ref_decrypt: Decrypts a variable-length cipher text -/// -# aes_ref_decrypt_CBC: for CBC mode -/// -# aes_ref_decrypt_ECB: for ECB mode -/// -# aes_ref_decrypt_CTR: for CTR mode -//------------------------------------------------------------------------------ - -#ifndef BOOTLOADER_AES_REFERENCE_H -#define BOOTLOADER_AES_REFERENCE_H - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "config.h" - - -#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_REF) - -//------------------------------------------------------------------------------ -// Check configuration -//------------------------------------------------------------------------------ - -// Supported modes -#if !defined(ENCRYPTION_ECB) && \ - !defined(ENCRYPTION_CBC) && \ - !defined(ENCRYPTION_CTR) - #error No other mode than ECB, CBC & CTR are supported. -#endif - -// Supported key length -#if (ENCRYPTION_KEY_LENGTH != 16) && \ - (ENCRYPTION_KEY_LENGTH != 24) && \ - (ENCRYPTION_KEY_LENGTH != 32) - #error Only key lengths of 128, 192 or 256 bits are supported. -#endif - -// Supported block length -#if (ENCRYPTION_BLOCK_LENGTH != 16) - #error Only block length of 128 bits is supported. -#endif - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ -#define BC (ENCRYPTION_BLOCK_LENGTH / 4) -#define SC ((BC - 4) >> 1) -#define KC (ENCRYPTION_KEY_LENGTH / 4) -#define t0f 0x000000FF & tf -#define t1f 0x0000FF00 & tf -#define t2f 0x00FF0000 & tf -#define t3f 0xFF000000 & tf - -#if (KC >= BC) - #define ROUNDS (KC + 6) -#else - #define ROUNDS (BC + 6) -#endif - -#ifdef ONLY_ONE_ENCRYPTION -#define ENCRYPTION_INIT aes_ref_init -#define ENCRYPTION_CLEANUP aes_ref_cleanup -#define ENCRYPTION_DECRYPT aes_ref_decrypt -#endif - -//------------------------------------------------------------------------------ -// Prototypes -//------------------------------------------------------------------------------ -extern void aes_ref_init(void); -extern void aes_ref_init_CBC(void); -extern void aes_ref_init_ECB(void); -extern void aes_ref_init_CTR(void); -extern void aes_ref_cleanup(void); -extern int aes_ref_decrypt(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length); -extern int aes_ref_decrypt_CBC(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length); -extern int aes_ref_decrypt_ECB(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length); -extern int aes_ref_decrypt_CTR(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length); - -#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_REF) - -#endif // BOOTLOADER_AES_REFERENCE_H - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/encryption.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/encryption.h deleted file mode 100644 index 8b2850091..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/encryption.h +++ /dev/null @@ -1,98 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// Firmware encryption -/// -/// !Usage -/// -/// This file must include the header of every encryption module implemented for -/// the bootloader. It is also responsible for defining mock functions if no -/// encryption module is selected, as well as checking that parameters are -/// correctly set. -// -/// An encryption module must define the following functions: -/// -# void encryption_init(void); -/// -# void encryption_cleanup(void); -/// -# int encryption_decrypt(const unsigned char *, unsigned char *, unsigned int) -//------------------------------------------------------------------------------ - -#ifndef BOOTLOADER_ENCRYPTION_H -#define BOOTLOADER_ENCRYPTION_H - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "config.h" - - -//------------------------------------------------------------------------------ -// Check configuration -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -#if !defined(ENCRYPTION_INIT) && !defined(USE_ENCRYPTION) - #define ENCRYPTION_INIT(); - #define ENCRYPTION_CLEANUP(); - #define ENCRYPTION_DECRYPT(...) 1 - -#elif !defined(ENCRYPTION_INIT) && defined(USE_ENCRYPTION) - #error USE_ENCRYPTION defined but no encryption method selected. - -#elif !defined(ENCRYPTION_AES_LTC) && \ - !defined(ENCRYPTION_AES_REF) && \ - !defined(ENCRYPTION_AES_HARD) && \ - !defined(ENCRYPTION_3DES_LTC) && \ - !defined(ENCRYPTION_3DES_HARD) - #error No algorithm selected. - -#elif !defined(ENCRYPTION_ECB) && \ - !defined(ENCRYPTION_CBC) && \ - !defined(ENCRYPTION_CTR) - #error No encryption mode selected. - -#elif !defined(ENCRYPTION_KEY) - #error No key defined. - -#elif !defined(ENCRYPTION_KEY_LENGTH) - #error No key length selected. - -#elif !defined(ENCRYPTION_IV) - #error No initialization vector defined. - -#elif !defined(ENCRYPTION_BLOCK_LENGTH) - #error No block length selected. - -#endif -#endif // ONLY_ONE_ENCRYPTION -#endif // BOOTLOADER_ENCRYPTION_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/libtomcrypt.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/libtomcrypt.c deleted file mode 100644 index c21b20c91..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/libtomcrypt.c +++ /dev/null @@ -1,445 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Function: Firmware encryption using libTomCrypt -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include "libtomcrypt.h" -#include -#include -#include "config.h" - -#if defined(USE_ENCRYPTION) && (defined(ENCRYPTION_AES_LTC) || defined(ENCRYPTION_3DES_LTC)) -#include -#include -#include -#include -#include - -//------------------------------------------------------------------------------ -// Global variables -//------------------------------------------------------------------------------ - -#if defined(ENCRYPTION_ECB) - symmetric_ECB sECB; -#endif -#if defined(ENCRYPTION_CBC) - symmetric_CBC sCBC; -#endif -#if defined(ENCRYPTION_CTR) - symmetric_CTR sCTR; -#endif - -//------------------------------------------------------------------------------ -// Inline functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Converts an ASCII string to an hexadecimal value -/// \param ASCII string to convert -/// \param Buffer to store converted value -/// \param Length of buffer -//------------------------------------------------------------------------------ -static inline void ASCII2Hex(const char * ascii, unsigned char * binary, unsigned int length) -{ - unsigned int i; - - for (i=0; i < length; i++) { - if (ascii[i*2] >= 'A') { - binary[i] = ascii[i*2] - 'A' + 10; - } - else { - binary[i] = ascii[i*2] - '0'; - } - binary[i] <<= 4; - if (ascii[i*2+1] >= 'A') { - binary[i] += ascii[i*2+1] - 'A' + 10; - } - else { - binary[i] += ascii[i*2+1] - '0'; - } - } -} - -//------------------------------------------------------------------------------ -// Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Initializes the decryption process -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -void ltc_init(void) -{ - int cipherID; - unsigned char key[ENCRYPTION_KEY_LENGTH]; - -#if defined(ENCRYPTION_CTR) || defined(ENCRYPTION_CBC) - unsigned char IV[ENCRYPTION_BLOCK_LENGTH]; -#endif - - TRACE_DEBUG("LTC: Initializing ...\n\r"); - - // Register cipher - register_cipher(&CIPHER_DESC); - cipherID = find_cipher(CIPHER_NAME); - - // Load key - ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - -#if defined(ENCRYPTION_CTR) || defined(ENCRYPTION_CBC) - // Load IV - ASCII2Hex(ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); -#endif - - // Start decryption mode -#if defined(ENCRYPTION_ECB) - ecb_start(cipherID, key, ENCRYPTION_KEY_LENGTH, 0, &sECB); -#elif defined(ENCRYPTION_CBC) - cbc_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, &sCBC); -#elif defined(ENCRYPTION_CTR) - ctr_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, CTR_COUNTER_BIG_ENDIAN, &sCTR); -#endif - - TRACE_DEBUG("LTC: Initialization done.\n\r"); -} -#endif // ONLY_ONE_ENCRYPTION - -//------------------------------------------------------------------------------ -/// Initializes the decryption process for AES, mode CBC -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -#if defined(ENCRYPTION_CBC) -void ltc_init_AES_CBC(void) -{ - int cipherID; - unsigned char key[ENCRYPTION_KEY_LENGTH]; - unsigned char IV[ENCRYPTION_BLOCK_LENGTH]; - - TRACE_DEBUG("LTC: Initializing CBC...\n\r"); - - // Register cipher - register_cipher(&rijndael_desc); - cipherID = find_cipher("rijndael"); - - // Load key - ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - // Load IV - ASCII2Hex(ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - // Start decryption mode - cbc_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, &sCBC); - - TRACE_DEBUG("LTC: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the decryption process for AES, mode CTR -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -void ltc_init_AES_CTR(void) -{ - int cipherID; - unsigned char key[ENCRYPTION_KEY_LENGTH]; - unsigned char IV[ENCRYPTION_BLOCK_LENGTH]; - - TRACE_DEBUG("LTC: Initializing CTR...\n\r"); - - // Register cipher - register_cipher(&rijndael_desc); - cipherID = find_cipher("rijndael"); - - // Load key - ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - // Load IV - ASCII2Hex(ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - // Start decryption mode - ctr_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, CTR_COUNTER_BIG_ENDIAN, &sCTR); - - TRACE_DEBUG("LTC: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the decryption process for AES, mode ECB -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) -void ltc_init_AES_ECB(void) -{ - int cipherID; - unsigned char key[ENCRYPTION_KEY_LENGTH]; - - TRACE_DEBUG("LTC: Initializing ECB...\n\r"); - - // Register cipher - register_cipher(&rijndael_desc); - cipherID = find_cipher("rijndael"); - - // Load key - ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - // Start decryption mode - ecb_start(cipherID, key, ENCRYPTION_KEY_LENGTH, 0, &sECB); - - TRACE_DEBUG("LTC: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the decryption process for 3DES, mode CBC -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CBC) -void ltc_init_3DES_CBC(void) -{ - int cipherID; - unsigned char key[ENCRYPTION_KEY_LENGTH]; - unsigned char IV[ENCRYPTION_BLOCK_LENGTH]; - - TRACE_DEBUG("LTC: Initializing CBC...\n\r"); - - // Register cipher - register_cipher(&des3_desc); - cipherID = find_cipher("3des"); - - // Load key - ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - // Load IV - ASCII2Hex(ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - // Start decryption mode - cbc_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, &sCBC); - - TRACE_DEBUG("LTC: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the decryption process for 3DES, mode CTR -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -void ltc_init_3DES_CTR(void) -{ - int cipherID; - unsigned char key[ENCRYPTION_KEY_LENGTH]; - unsigned char IV[ENCRYPTION_BLOCK_LENGTH]; - - TRACE_DEBUG("LTC: Initializing CTR...\n\r"); - - // Register cipher - register_cipher(&des3_desc); - cipherID = find_cipher("3des"); - - // Load key - ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - // Load IV - ASCII2Hex(ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - // Start decryption mode - ctr_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, CTR_COUNTER_BIG_ENDIAN, &sCTR); - - TRACE_DEBUG("LTC: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the decryption process for 3DES, mode ECB -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) -void ltc_init_3DES_ECB(void) -{ - int cipherID; - unsigned char key[ENCRYPTION_KEY_LENGTH]; - - TRACE_DEBUG("LTC: Initializing ECB...\n\r"); - - // Register cipher - register_cipher(&des3_desc); - cipherID = find_cipher("3des"); - - // Load key - ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - // Start decryption mode - ecb_start(cipherID, key, ENCRYPTION_KEY_LENGTH, 0, &sECB); - - TRACE_DEBUG("LTC: Initialization done.\n\r"); -} -#endif -#endif // ONLY_ONE_ENCRYPTION - - -//------------------------------------------------------------------------------ -/// Terminates the decryption process -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -void ltc_cleanup(void) -{ - TRACE_DEBUG("LTC: Cleaning up ...\n\r"); - -#if defined(ENCRYPTION_ECB) - ecb_done(&sECB); -#elif defined(ENCRYPTION_CBC) - cbc_done(&sCBC); -#elif defined(ENCRYPTION_CTR) - ctr_done(&sCTR); -#endif - - TRACE_DEBUG("LTC: Cleanup done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Terminates the decryption process for mode CBC -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -#if defined(ENCRYPTION_CBC) -void ltc_cleanup_CBC(void) -{ - TRACE_DEBUG("LTC: Cleaning up CBC...\n\r"); - cbc_done(&sCBC); - TRACE_DEBUG("LTC: Cleanup done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Terminates the decryption process for mode CTR -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -void ltc_cleanup_CTR(void) -{ - TRACE_DEBUG("LTC: Cleaning up CTR...\n\r"); - ctr_done(&sCTR); - TRACE_DEBUG("LTC: Cleanup done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Terminates the decryption process for mode ECB -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) -void ltc_cleanup_ECB(void) -{ - TRACE_DEBUG("LTC: Cleaning up ECB...\n\r"); - ecb_done(&sECB); - TRACE_DEBUG("LTC: Cleanup done.\n\r"); -} -#endif -#endif // ONLY_ONE_ENCRYPTION - -//------------------------------------------------------------------------------ -/// Decrypts a block of data -/// \param Data to decrypt -/// \param Buffer to store decrypted data -/// \param Length of data -/// \return 1 if successful, 0 otherwise. -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -int ltc_decrypt(const unsigned char * cipherText, unsigned char * plainText, unsigned int length) -{ -#if defined(ENCRYPTION_ECB) - if (ecb_decrypt(cipherText, plainText, length, &sECB) != CRYPT_OK) { -#elif defined(ENCRYPTION_CBC) - if (cbc_decrypt(cipherText, plainText, length, &sCBC) != CRYPT_OK) { -#elif defined(ENCRYPTION_CTR) - if (ctr_decrypt(cipherText, plainText, length, &sCTR) != CRYPT_OK) { -#endif - return 0; - } - else { - return 1; - } -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypts a block of data in CBC mode -/// \param Data to decrypt -/// \param Buffer to store decrypted data -/// \param Length of data -/// \return 1 if successful, 0 otherwise. -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -int ltc_decrypt_CBC(const unsigned char * cipherText, unsigned char * plainText, unsigned int length) -{ - if (cbc_decrypt(cipherText, plainText, length, &sCBC) != CRYPT_OK) { - return 0; - } - else { - return 1; - } -} - -//------------------------------------------------------------------------------ -/// Decrypts a block of data in CTR mode -/// \param Data to decrypt -/// \param Buffer to store decrypted data -/// \param Length of data -/// \return 1 if successful, 0 otherwise. -//------------------------------------------------------------------------------ -int ltc_decrypt_CTR(const unsigned char * cipherText, unsigned char * plainText, unsigned int length) -{ - if (ctr_decrypt(cipherText, plainText, length, &sCTR) != CRYPT_OK) { - return 0; - } - else { - return 1; - } -} - -//------------------------------------------------------------------------------ -/// Decrypts a block of data in ECB mode -/// \param Data to decrypt -/// \param Buffer to store decrypted data -/// \param Length of data -/// \return 1 if successful, 0 otherwise. -//------------------------------------------------------------------------------ -int ltc_decrypt_ECB(const unsigned char * cipherText, unsigned char * plainText, unsigned int length) -{ - if (ecb_decrypt(cipherText, plainText, length, &sECB) != CRYPT_OK) { - return 0; - } - else { - return 1; - } -} -#endif // ONLY_ONE_ENCRYPTION - -#endif // defined(USE_ENCRYPTION) && (defined(ENCRYPTION_AES_LTC) || defined(ENCRYPTION_3DES_LTC)) - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/libtomcrypt.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/libtomcrypt.h deleted file mode 100644 index 317b79f28..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/libtomcrypt.h +++ /dev/null @@ -1,149 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// Firmware encryption using libTomCrypt -/// -/// !Usage -/// -/// -# ltc_init: Initialize LibTomCrypt -/// -# ltc_init_AES_CBC -/// -# ltc_init_AES_CTR -/// -# ltc_init_AES_ECB -/// -# ltc_init_3DES_CBC -/// -# ltc_init_3DES_CTR -/// -# ltc_init_3DES_ECB -/// -# ltc_cleanup -/// -# ltc_cleanup_CBC -/// -# ltc_cleanup_CTR -/// -# ltc_cleanup_ECB -/// -# ltc_decrypt -/// -# ltc_decrypt_CBC -/// -# ltc_decrypt_CTR -/// -# ltc_decrypt_ECB -//------------------------------------------------------------------------------ - -#ifndef BOOTLOADER_LIBTOMCRYPT_H -#define BOOTLOADER_LIBTOMCRYPT_H - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include "config.h" - -#if defined(USE_ENCRYPTION) && (defined(ENCRYPTION_AES_LTC) || defined(ENCRYPTION_3DES_LTC)) - -//------------------------------------------------------------------------------ -// Check configuration -//------------------------------------------------------------------------------ - -// Supported modes -#if !defined(ENCRYPTION_CTR) && \ - !defined(ENCRYPTION_CBC) && \ - !defined(ENCRYPTION_ECB) - #error No other mode than ECB, CBC & CTR are supported. -#endif - -// Supported key length -#if defined(ENCRYPTION_AES_LTC) - #if (ENCRYPTION_KEY_LENGTH != 16) && \ - (ENCRYPTION_KEY_LENGTH != 24) && \ - (ENCRYPTION_KEY_LENGTH != 32) - #error Only a key length of 128, 192 or 256 bits are supported with AES. - #endif -#elif defined(ENCRYPTION_3DES_LTC) - #if (ENCRYPTION_KEY_LENGTH != 16) && \ - (ENCRYPTION_KEY_LENGTH != 24) - #error Only a key length of 128 or 192 bits are supported with Triple-DES. - #endif -#endif - -// Supported block length -#if defined(ENCRYPTION_AES_LTC) - #if (ENCRYPTION_BLOCK_LENGTH != 16) - #error Only a block length of 128 bits is supported with AES. - #endif -#elif defined(ENCRYPTION_3DES_LTC) - #if (ENCRYPTION_BLOCK_LENGTH != 8) - #error Only a block length of 64 bits is supported with Triple-DES. - #endif -#endif - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -// Functions -#ifdef ONLY_ONE_ENCRYPTION -#define ENCRYPTION_INIT ltc_init -#define ENCRYPTION_CLEANUP ltc_cleanup -#define ENCRYPTION_DECRYPT ltc_decrypt - -#if defined(ENCRYPTION_AES_LTC) - #define CIPHER_NAME "rijndael" - #define CIPHER_DESC rijndael_desc -#elif defined(ENCRYPTION_3DES_LTC) - #define CIPHER_NAME "3des" - #define CIPHER_DESC des3_desc -#endif -#endif - -//------------------------------------------------------------------------------ -// Prototypes -//------------------------------------------------------------------------------ - -#ifdef ONLY_ONE_ENCRYPTION -extern void ltc_init(void); -#endif -extern void ltc_init_AES_CBC(void); -extern void ltc_init_AES_CTR(void); -extern void ltc_init_AES_ECB(void); -extern void ltc_init_3DES_CBC(void); -extern void ltc_init_3DES_CTR(void); -extern void ltc_init_3DES_ECB(void); - -extern void ltc_cleanup(void); -extern void ltc_cleanup_CBC(void); -extern void ltc_cleanup_CTR(void); -extern void ltc_cleanup_ECB(void); - -extern int ltc_decrypt(const unsigned char * cipherText, unsigned char * plainText, unsigned int length); -extern int ltc_decrypt_CBC(const unsigned char * cipherText, unsigned char * plainText, unsigned int length); -extern int ltc_decrypt_CTR(const unsigned char * cipherText, unsigned char * plainText, unsigned int length); -extern int ltc_decrypt_ECB(const unsigned char * cipherText, unsigned char * plainText, unsigned int length); - -#endif // defined(USE_ENCRYPTION) && (defined(ENCRYPTION_AES_LTC) || defined(ENCRYPTION_3DES_LTC)) -#endif // BOOTLOADER_AES_LIBTOMCRYPT_H - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/tdes_hardware.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/tdes_hardware.c deleted file mode 100644 index 7b5701032..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/tdes_hardware.c +++ /dev/null @@ -1,520 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Function: Firmware encryption using TDES hardware acceleration -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include "tdes_hardware.h" - -#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_3DES_HARD) -#include -#include -#include -#include -#include -#include - -//------------------------------------------------------------------------------ -// Global variables -//------------------------------------------------------------------------------ - -#ifdef ENCRYPTION_CTR - unsigned char CTR[ENCRYPTION_BLOCK_LENGTH]; -#endif - -//------------------------------------------------------------------------------ -// Inline functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Converts an ASCII value to an hexadecimal one -/// \param ASCII string -/// \param Buffer to store integer value -/// \param Length of string -//------------------------------------------------------------------------------ -static inline void ASCII2Hex(const unsigned char * ascii, unsigned char * binary, unsigned int length) -{ - unsigned int i; - - for (i=0; i < length; i++) { - if (ascii[i*2] >= 'A') { - binary[i] = ascii[i*2] - 'A' + 10; - } - else { - binary[i] = ascii[i*2] - '0'; - } - binary[i] <<= 4; - if (ascii[i*2+1] >= 'A') { - binary[i] += ascii[i*2+1] - 'A' + 10; - } - else { - binary[i] += ascii[i*2+1] - '0'; - } - } -} -//------------------------------------------------------------------------------ -// Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Initializes the TDES peripheral -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -void tdes_hard_init(void) -{ - unsigned char key[ENCRYPTION_KEY_LENGTH]; - - TRACE_DEBUG("TDES/HARD: Initializing ...\n\r"); - - // Activate peripheral clock -#ifdef AT91C_ID_AES - PMC_EnablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_EnablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_EnablePeripheral( AT91C_ID_TDES ); -#else -#error AES/TDES undefined -#endif - - // Load mode -#if (ENCRYPTION_KEY_LENGTH == 24) - AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | TDES_MODE - | AT91C_TDES_TDESMOD | TDES_CIPHER; -#else - AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | TDES_MODE | AT91C_TDES_KEYMOD - | AT91C_TDES_TDESMOD | TDES_CIPHER; -#endif - - // Convert and load key - ASCII2Hex((unsigned char*)ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - AT91C_BASE_TDES->TDES_KEY1WxR[0] = ((int *) key)[0]; - AT91C_BASE_TDES->TDES_KEY1WxR[1] = ((int *) key)[1]; - AT91C_BASE_TDES->TDES_KEY2WxR[0] = ((int *) key)[2]; - AT91C_BASE_TDES->TDES_KEY2WxR[1] = ((int *) key)[3]; - -#if (ENCRYPTION_KEY_LENGTH == 24) - AT91C_BASE_TDES->TDES_KEY3WxR[0] = ((int *) key)[4]; - AT91C_BASE_TDES->TDES_KEY3WxR[1] = ((int *) key)[5]; -#endif - -#if defined(ENCRYPTION_CBC) - unsigned char IV[8]; - ASCII2Hex((unsigned char*)ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - AT91C_BASE_TDES->TDES_IVxR[0] = ((int *) IV)[0]; - AT91C_BASE_TDES->TDES_IVxR[1] = ((int *) IV)[1]; - -#elif defined(ENCRYPTION_CTR) - // Convert IV - ASCII2Hex((unsigned char*)ENCRYPTION_IV, CTR, ENCRYPTION_BLOCK_LENGTH); -#endif - - TRACE_DEBUG("TDES/HARD: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the DES peripheral for CBC mode -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -void tdes_hard_init_CBC(void) -{ - unsigned char key[TDES_ENCRYPTION_KEY_LENGTH]; - - TRACE_DEBUG("tdes_hard_init_CBC\n\r"); - - // Activate peripheral clock -#ifdef AT91C_ID_AES - PMC_EnablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_EnablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_EnablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - - // Load mode -#if (TDES_ENCRYPTION_KEY_LENGTH == 24) - AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_CBC - | AT91C_TDES_TDESMOD | 0; -#else - AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_CBC | AT91C_TDES_KEYMOD - | AT91C_TDES_TDESMOD | 0; -#endif - - // Convert and load key - ASCII2Hex((unsigned char*)TDES_ENCRYPTION_KEY, key, TDES_ENCRYPTION_KEY_LENGTH); - - AT91C_BASE_TDES->TDES_KEY1WxR[0] = ((int *) key)[0]; - AT91C_BASE_TDES->TDES_KEY1WxR[1] = ((int *) key)[1]; - AT91C_BASE_TDES->TDES_KEY2WxR[0] = ((int *) key)[2]; - AT91C_BASE_TDES->TDES_KEY2WxR[1] = ((int *) key)[3]; - -#if (TDES_ENCRYPTION_KEY_LENGTH == 24) - AT91C_BASE_TDES->TDES_KEY3WxR[0] = ((int *) key)[4]; - AT91C_BASE_TDES->TDES_KEY3WxR[1] = ((int *) key)[5]; -#endif - - unsigned char IV[8]; - ASCII2Hex((unsigned char*)ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - AT91C_BASE_TDES->TDES_IVxR[0] = ((int *) IV)[0]; - AT91C_BASE_TDES->TDES_IVxR[1] = ((int *) IV)[1]; -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the DES peripheral for CTR mode -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -void tdes_hard_init_CTR(void) -{ - unsigned char key[TDES_ENCRYPTION_KEY_LENGTH]; - - TRACE_DEBUG("tdes_hard_init_CTR\n\r"); - - // Activate peripheral clock -#ifdef AT91C_ID_AES - PMC_EnablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_EnablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_EnablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - - // Load mode -#if (TDES_ENCRYPTION_KEY_LENGTH == 24) - AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_ECB - | AT91C_TDES_TDESMOD | AT91C_TDES_CIPHER; -#else - AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_ECB | AT91C_TDES_KEYMOD - | AT91C_TDES_TDESMOD | AT91C_TDES_CIPHER; -#endif - - // Convert and load key - ASCII2Hex((unsigned char*)TDES_ENCRYPTION_KEY, key, TDES_ENCRYPTION_KEY_LENGTH); - - AT91C_BASE_TDES->TDES_KEY1WxR[0] = ((int *) key)[0]; - AT91C_BASE_TDES->TDES_KEY1WxR[1] = ((int *) key)[1]; - AT91C_BASE_TDES->TDES_KEY2WxR[0] = ((int *) key)[2]; - AT91C_BASE_TDES->TDES_KEY2WxR[1] = ((int *) key)[3]; - -#if (TDES_ENCRYPTION_KEY_LENGTH == 24) - AT91C_BASE_TDES->TDES_KEY3WxR[0] = ((int *) key)[4]; - AT91C_BASE_TDES->TDES_KEY3WxR[1] = ((int *) key)[5]; -#endif - - // Convert IV - ASCII2Hex((unsigned char*)ENCRYPTION_IV, CTR, ENCRYPTION_BLOCK_LENGTH); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the DES peripheral for ECB mode -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -void tdes_hard_init_ECB(void) -{ - unsigned char key[TDES_ENCRYPTION_KEY_LENGTH]; - - TRACE_DEBUG("tdes_hard_init_ECB\n\r"); - - // Activate peripheral clock -#ifdef AT91C_ID_AES - PMC_EnablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_EnablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_EnablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - - // Load mode -#if (TDES_ENCRYPTION_KEY_LENGTH == 24) - AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_ECB - | AT91C_TDES_TDESMOD | 0; -#else - AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_ECB | AT91C_TDES_KEYMOD - | AT91C_TDES_TDESMOD | 0; -#endif - - // Convert and load key - ASCII2Hex((unsigned char*)TDES_ENCRYPTION_KEY, key, TDES_ENCRYPTION_KEY_LENGTH); - - AT91C_BASE_TDES->TDES_KEY1WxR[0] = ((int *) key)[0]; - AT91C_BASE_TDES->TDES_KEY1WxR[1] = ((int *) key)[1]; - AT91C_BASE_TDES->TDES_KEY2WxR[0] = ((int *) key)[2]; - AT91C_BASE_TDES->TDES_KEY2WxR[1] = ((int *) key)[3]; - -#if (TDES_ENCRYPTION_KEY_LENGTH == 24) - AT91C_BASE_TDES->TDES_KEY3WxR[0] = ((int *) key)[4]; - AT91C_BASE_TDES->TDES_KEY3WxR[1] = ((int *) key)[5]; -#endif -} -#endif - -//------------------------------------------------------------------------------ -/// Cleans up the DES peripheral -//------------------------------------------------------------------------------ -void tdes_hard_cleanup(void) -{ - TRACE_DEBUG("TDES/HARD: Cleaning up ...\n\r"); - AT91C_BASE_TDES->TDES_MR = 0; -#ifdef AT91C_ID_AES - PMC_DisablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_DisablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_DisablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - TRACE_DEBUG("TDES/HARD: Cleanup done.\n\r"); -} - -//------------------------------------------------------------------------------ -/// Decrypts a variable-length cipher text -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -int tdes_hard_decrypt(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length) -{ - unsigned int l; - - TRACE_DEBUG("tdes_hard_decrypt\n\r"); - -#if defined(ENCRYPTION_ECB) || defined(ENCRYPTION_CBC) - for (l=0; l < length;) { - - // Load counter and encrypt it - AT91C_BASE_TDES->TDES_IDATAxR[0] = ((int *) &cipherText[l])[0]; - AT91C_BASE_TDES->TDES_IDATAxR[1] = ((int *) &cipherText[l])[1]; - - // Start processing - AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START; - - while (!((AT91C_BASE_TDES->TDES_ISR) & AT91C_TDES_DATRDY)); - - ((int *) &plainText[l])[0] = AT91C_BASE_TDES->TDES_ODATAxR[0]; - ((int *) &plainText[l])[1] = AT91C_BASE_TDES->TDES_ODATAxR[1]; - - l += ENCRYPTION_BLOCK_LENGTH; - } - -#elif defined(ENCRYPTION_CTR) - unsigned int bytes; - unsigned char block[ENCRYPTION_BLOCK_LENGTH]; - unsigned int e; - unsigned int i; - int k; - - // Decrypt - for (e=0; e < length;) { - - // Load counter and encrypt it - AT91C_BASE_TDES->TDES_IDATAxR[0] = ((int *) CTR)[0]; - AT91C_BASE_TDES->TDES_IDATAxR[1] = ((int *) CTR)[1]; - - AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START; - while (!(AT91C_BASE_TDES->TDES_ISR & AT91C_TDES_DATRDY)); - - ((int *) block)[0] = AT91C_BASE_TDES->TDES_ODATAxR[0]; - ((int *) block)[1] = AT91C_BASE_TDES->TDES_ODATAxR[1]; - - // XOR current plain text block with encrypted counter - if ((length-e) < ENCRYPTION_BLOCK_LENGTH) { - bytes = length - e; - } - else { - bytes = ENCRYPTION_BLOCK_LENGTH; - } - - for (i=0; i < bytes; i++) { - plainText[e+i] = cipherText[e+i] ^ ((char *) block)[i]; - } - - // Increment counter (big-endian) and number of encrypted bytes - for (k=ENCRYPTION_BLOCK_LENGTH-1; k >= 0; k--) { - if (++((char *) CTR)[k] != 0) { - break; - } - } - e += bytes; - } -#endif // ENCRYPTION_CTR - - return 1; -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypts a variable-length cipher text for CBC mode -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -int tdes_hard_decrypt_CBC(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length) -{ - unsigned int l; - - TRACE_DEBUG("tdes_hard_decrypt_CBC\n\r"); - - for (l=0; l < length;) { - // Load counter and encrypt it - AT91C_BASE_TDES->TDES_IDATAxR[0] = ((int *) &cipherText[l])[0]; - AT91C_BASE_TDES->TDES_IDATAxR[1] = ((int *) &cipherText[l])[1]; - - // Start processing - AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START; - - while (!((AT91C_BASE_TDES->TDES_ISR) & AT91C_TDES_DATRDY)); - - ((int *) &plainText[l])[0] = AT91C_BASE_TDES->TDES_ODATAxR[0]; - ((int *) &plainText[l])[1] = AT91C_BASE_TDES->TDES_ODATAxR[1]; - - l += ENCRYPTION_BLOCK_LENGTH; - } - return 1; -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypts a variable-length cipher text for CTR mode -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -int tdes_hard_decrypt_CTR(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length) -{ - unsigned int bytes; - unsigned char block[ENCRYPTION_BLOCK_LENGTH]; - unsigned int e; - unsigned int i; - int k; - - TRACE_DEBUG("tdes_hard_decrypt_CTR\n\r"); - - // Decrypt - for (e=0; e < length;) { - - // Load counter and encrypt it - AT91C_BASE_TDES->TDES_IDATAxR[0] = ((int *) CTR)[0]; - AT91C_BASE_TDES->TDES_IDATAxR[1] = ((int *) CTR)[1]; - - AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START; - while (!(AT91C_BASE_TDES->TDES_ISR & AT91C_TDES_DATRDY)); - - ((int *) block)[0] = AT91C_BASE_TDES->TDES_ODATAxR[0]; - ((int *) block)[1] = AT91C_BASE_TDES->TDES_ODATAxR[1]; - - // XOR current plain text block with encrypted counter - if ((length-e) < ENCRYPTION_BLOCK_LENGTH) { - bytes = length - e; - } - else { - bytes = ENCRYPTION_BLOCK_LENGTH; - } - - for (i=0; i < bytes; i++) { - plainText[e+i] = cipherText[e+i] ^ ((char *) block)[i]; - } - - // Increment counter (big-endian) and number of encrypted bytes - for (k=ENCRYPTION_BLOCK_LENGTH-1; k >= 0; k--) { - if (++((char *) CTR)[k] != 0) { - break; - } - } - e += bytes; - } - - return 1; -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypts a variable-length cipher text for ECB mode -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -int tdes_hard_decrypt_ECB(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length) -{ - unsigned int l; - - TRACE_DEBUG("tdes_hard_decrypt_ECB\n\r"); - - for (l=0; l < length;) { - - // Load counter and encrypt it - AT91C_BASE_TDES->TDES_IDATAxR[0] = ((int *) &cipherText[l])[0]; - AT91C_BASE_TDES->TDES_IDATAxR[1] = ((int *) &cipherText[l])[1]; - - // Start processing - AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START; - - while (!((AT91C_BASE_TDES->TDES_ISR) & AT91C_TDES_DATRDY)); - - ((int *) &plainText[l])[0] = AT91C_BASE_TDES->TDES_ODATAxR[0]; - ((int *) &plainText[l])[1] = AT91C_BASE_TDES->TDES_ODATAxR[1]; - - l += ENCRYPTION_BLOCK_LENGTH; - } - return 1; -} -#endif - -#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_3DES_HARD) - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/tdes_hardware.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/tdes_hardware.h deleted file mode 100644 index 28fb774b5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/encryption/tdes_hardware.h +++ /dev/null @@ -1,125 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// Firmware encryption using TDES hardware acceleration -/// -/// !Usage -/// -/// -# tdes_hard_init: Initialize TDES hardware -/// -# tdes_hard_init_CBC: for the CBC mode -/// -# tdes_hard_init_ECB: for the CTR mode -/// -# tdes_hard_init_CTR: for the ECB mode -/// -# tdes_hard_cleanup: Cleans up DES -/// -# tdes_hard_decrypt: Decrypts a variable-length cipher text -/// -# tdes_hard_decrypt_CBC: for CBC mode -/// -# tdes_hard_decrypt_ECB: for ECB mode -/// -# tdes_hard_decrypt_CTR: for CTR mode -//------------------------------------------------------------------------------ -#ifndef BOOTLOADER_TDES_HARDWARE_H -#define BOOTLOADER_TDES_HARDWARE_H - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include "config.h" - -#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_3DES_HARD) - -//------------------------------------------------------------------------------ -// Check configuration -//------------------------------------------------------------------------------ - -#ifdef ONLY_ONE_ENCRYPTION -#if (ENCRYPTION_KEY_LENGTH != 16) && (ENCRYPTION_KEY_LENGTH != 24) - #error Triple-DES hardware acceleration only supports 128 and 192 bits keys. -#endif - -#if (ENCRYPTION_BLOCK_LENGTH != 8) - #error Triple-DES hardware acceleration only supports 64 bits blocks. -#endif - -#if !defined(ENCRYPTION_ECB) && \ - !defined(ENCRYPTION_CBC) && \ - !defined(ENCRYPTION_CTR) - #error Only ECB, CBC & CTR mode are supported. -#endif - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ -#define ENCRYPTION_INIT tdes_hard_init -#define ENCRYPTION_CLEANUP tdes_hard_cleanup -#define ENCRYPTION_DECRYPT tdes_hard_decrypt - -#if defined(ENCRYPTION_ECB) - #define TDES_MODE AT91C_TDES_OPMOD_ECB - #define TDES_CIPHER 0 -#elif defined(ENCRYPTION_CBC) - #define TDES_MODE AT91C_TDES_OPMOD_CBC - #define TDES_CIPHER 0 -#elif defined(ENCRYPTION_CTR) - #define TDES_MODE AT91C_TDES_OPMOD_ECB - #define TDES_CIPHER AT91C_TDES_CIPHER -#endif - -#endif // ONLY_ONE_ENCRYPTION - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -extern void tdes_hard_init(void); -#endif -extern void tdes_hard_init_CBC(void); -extern void tdes_hard_init_CTR(void); -extern void tdes_hard_init_ECB(void); -extern void tdes_hard_cleanup(void); -extern int tdes_hard_decrypt(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length); -extern int tdes_hard_decrypt_CBC(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length); -extern int tdes_hard_decrypt_CTR(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length); -extern int tdes_hard_decrypt_ECB(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length); - - -#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_3DES_HARD) -#endif // BOOTLOADER_DES_HARDWARE_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/hamming.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/hamming.c deleted file mode 100644 index 2b1b89054..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/hamming.c +++ /dev/null @@ -1,335 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "hamming.h" -#include -#include - -//------------------------------------------------------------------------------ -// Internal function -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Counts and return the number of bits set to '1' in the given byte. -/// \param byte Byte to count. -//------------------------------------------------------------------------------ -static unsigned char CountBitsInByte(unsigned char byte) -{ - unsigned char count = 0; - while (byte > 0) { - - if (byte & 1) { - - count++; - } - byte >>= 1; - } - - return count; -} - -//------------------------------------------------------------------------------ -/// Counts and return the number of bits set to '1' in the given hamming code. -/// \param code Hamming code. -//------------------------------------------------------------------------------ -static unsigned char CountBitsInCode256(unsigned char *code) -{ - return CountBitsInByte(code[0]) - + CountBitsInByte(code[1]) - + CountBitsInByte(code[2]); -} - -//------------------------------------------------------------------------------ -/// Calculates the 22-bit hamming code for a 256-bytes block of data. -/// \param data Data buffer to calculate code for. -/// \param code Pointer to a buffer where the code should be stored. -//------------------------------------------------------------------------------ -static void Compute256(const unsigned char *data, unsigned char *code) -{ - unsigned int i; - unsigned char columnSum = 0; - unsigned char evenLineCode = 0; - unsigned char oddLineCode = 0; - unsigned char evenColumnCode = 0; - unsigned char oddColumnCode = 0; - - // Xor all bytes together to get the column sum; - // At the same time, calculate the even and odd line codes - for (i=0; i < 256; i++) { - - columnSum ^= data[i]; - - // If the xor sum of the byte is 0, then this byte has no incidence on - // the computed code; so check if the sum is 1. - if ((CountBitsInByte(data[i]) & 1) == 1) { - - // Parity groups are formed by forcing a particular index bit to 0 - // (even) or 1 (odd). - // Example on one byte: - // - // bits (dec) 7 6 5 4 3 2 1 0 - // (bin) 111 110 101 100 011 010 001 000 - // '---'---'---'----------. - // | - // groups P4' ooooooooooooooo eeeeeeeeeeeeeee P4 | - // P2' ooooooo eeeeeee ooooooo eeeeeee P2 | - // P1' ooo eee ooo eee ooo eee ooo eee P1 | - // | - // We can see that: | - // - P4 -> bit 2 of index is 0 --------------------' - // - P4' -> bit 2 of index is 1. - // - P2 -> bit 1 of index if 0. - // - etc... - // We deduce that a bit position has an impact on all even Px if - // the log2(x)nth bit of its index is 0 - // ex: log2(4) = 2, bit2 of the index must be 0 (-> 0 1 2 3) - // and on all odd Px' if the log2(x)nth bit of its index is 1 - // ex: log2(2) = 1, bit1 of the index must be 1 (-> 0 1 4 5) - // - // As such, we calculate all the possible Px and Px' values at the - // same time in two variables, evenLineCode and oddLineCode, such as - // evenLineCode bits: P128 P64 P32 P16 P8 P4 P2 P1 - // oddLineCode bits: P128' P64' P32' P16' P8' P4' P2' P1' - // - evenLineCode ^= (255 - i); - oddLineCode ^= i; - } - } - - // At this point, we have the line parities, and the column sum. First, We - // must caculate the parity group values on the column sum. - for (i=0; i < 8; i++) { - - if (columnSum & 1) { - - evenColumnCode ^= (7 - i); - oddColumnCode ^= i; - } - columnSum >>= 1; - } - - // Now, we must interleave the parity values, to obtain the following layout: - // Code[0] = Line1 - // Code[1] = Line2 - // Code[2] = Column - // Line = Px' Px P(x-1)- P(x-1) ... - // Column = P4' P4 P2' P2 P1' P1 PadBit PadBit - code[0] = 0; - code[1] = 0; - code[2] = 0; - - for (i=0; i < 4; i++) { - - code[0] <<= 2; - code[1] <<= 2; - code[2] <<= 2; - - // Line 1 - if ((oddLineCode & 0x80) != 0) { - - code[0] |= 2; - } - if ((evenLineCode & 0x80) != 0) { - - code[0] |= 1; - } - - // Line 2 - if ((oddLineCode & 0x08) != 0) { - - code[1] |= 2; - } - if ((evenLineCode & 0x08) != 0) { - - code[1] |= 1; - } - - // Column - if ((oddColumnCode & 0x04) != 0) { - - code[2] |= 2; - } - if ((evenColumnCode & 0x04) != 0) { - - code[2] |= 1; - } - - oddLineCode <<= 1; - evenLineCode <<= 1; - oddColumnCode <<= 1; - evenColumnCode <<= 1; - } - - // Invert codes (linux compatibility) - code[0] = ~code[0]; - code[1] = ~code[1]; - code[2] = ~code[2]; - - TRACE_DEBUG("Computed code = %02X %02X %02X\n\r", - code[0], code[1], code[2]); -} - -//------------------------------------------------------------------------------ -/// Verifies and corrects a 256-bytes block of data using the given 22-bits -/// hamming code. -/// Returns 0 if there is no error, otherwise returns a HAMMING_ERROR code. -/// \param data Data buffer to check. -/// \param originalCode Hamming code to use for verifying the data. -//------------------------------------------------------------------------------ -static unsigned char Verify256( - unsigned char *data, - const unsigned char *originalCode) -{ - // Calculate new code - unsigned char computedCode[3]; - unsigned char correctionCode[3]; - Compute256(data, computedCode); - - // Xor both codes together - correctionCode[0] = computedCode[0] ^ originalCode[0]; - correctionCode[1] = computedCode[1] ^ originalCode[1]; - correctionCode[2] = computedCode[2] ^ originalCode[2]; - - TRACE_DEBUG("Correction code = %02X %02X %02X\n\r", - correctionCode[0], correctionCode[1], correctionCode[2]); - - // If all bytes are 0, there is no error - if ((correctionCode[0] == 0) - && (correctionCode[1] == 0) - && (correctionCode[2] == 0)) { - - return 0; - } - // If there is a single bit error, there are 11 bits set to 1 - if (CountBitsInCode256(correctionCode) == 11) { - - // Get byte and bit indexes - unsigned char byte = correctionCode[0] & 0x80; - byte |= (correctionCode[0] << 1) & 0x40; - byte |= (correctionCode[0] << 2) & 0x20; - byte |= (correctionCode[0] << 3) & 0x10; - - byte |= (correctionCode[1] >> 4) & 0x08; - byte |= (correctionCode[1] >> 3) & 0x04; - byte |= (correctionCode[1] >> 2) & 0x02; - byte |= (correctionCode[1] >> 1) & 0x01; - - unsigned char bit = (correctionCode[2] >> 5) & 0x04; - bit |= (correctionCode[2] >> 4) & 0x02; - bit |= (correctionCode[2] >> 3) & 0x01; - - // Correct bit - TRACE_DEBUG("Correcting byte #%d at bit %d\n\r", byte, bit); - data[byte] ^= (1 << bit); - - return Hamming_ERROR_SINGLEBIT; - } - // Check if ECC has been corrupted - if (CountBitsInCode256(correctionCode) == 1) { - - return Hamming_ERROR_ECC; - } - // Otherwise, this is a multi-bit error - else { - - return Hamming_ERROR_MULTIPLEBITS; - } -} - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Computes 3-bytes hamming codes for a data block whose size is multiple of -/// 256 bytes. Each 256 bytes block gets its own code. -/// \param data Data to compute code for. -/// \param size Data size in bytes. -/// \param code Codes buffer. -//------------------------------------------------------------------------------ -void Hamming_Compute256x( - const unsigned char *data, - unsigned int size, - unsigned char *code) -{ - TRACE_DEBUG("Hamming_Compute256x()\n\r"); - - while (size > 0) { - - Compute256(data, code); - data += 256; - code += 3; - size -= 256; - } -} - -//------------------------------------------------------------------------------ -/// Verifies 3-bytes hamming codes for a data block whose size is multiple of -/// 256 bytes. Each 256-bytes block is verified with its own code. -/// Returns 0 if the data is correct, Hamming_ERROR_SINGLEBIT if one or more -/// block(s) have had a single bit corrected, or either Hamming_ERROR_ECC -/// or Hamming_ERROR_MULTIPLEBITS. -/// \param data Data buffer to verify. -/// \param size Size of the data in bytes. -/// \param code Original codes. -//------------------------------------------------------------------------------ -unsigned char Hamming_Verify256x( - unsigned char *data, - unsigned int size, - const unsigned char *code) -{ - unsigned char error; - unsigned char result = 0; - - TRACE_DEBUG("Hamming_Verify256x()\n\r"); - - while (size > 0) { - - error = Verify256(data, code); - if (error == Hamming_ERROR_SINGLEBIT) { - - result = Hamming_ERROR_SINGLEBIT; - } - else if (error) { - - return error; - } - - data += 256; - code += 3; - size -= 256; - } - - return result; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/hamming.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/hamming.h deleted file mode 100644 index 6e0125d90..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/hamming.h +++ /dev/null @@ -1,72 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef HAMMING_H -#define HAMMING_H - -//------------------------------------------------------------------------------ -// Defines -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "Hamming Code Errors" -/// These are the possible errors when trying to verify a block of data encoded -/// using a Hamming code: -/// -/// !Errors: -/// - Hamming_ERROR_SINGLEBIT -/// - Hamming_ERROR_ECC -/// - Hamming_ERROR_MULTIPLEBITS - -/// A single bit was incorrect but has been recovered. -#define Hamming_ERROR_SINGLEBIT 1 - -/// The original code has been corrupted. -#define Hamming_ERROR_ECC 2 - -/// Multiple bits are incorrect in the data and they cannot be corrected. -#define Hamming_ERROR_MULTIPLEBITS 3 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void Hamming_Compute256x( - const unsigned char *data, - unsigned int size, - unsigned char *code); - -extern unsigned char Hamming_Verify256x( - unsigned char *data, - unsigned int size, - const unsigned char *code); - -#endif //#ifndef HAMMING_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/iap.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/iap.c deleted file mode 100644 index c4657e229..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/iap.c +++ /dev/null @@ -1,98 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: IAP implementation - - About: Purpose - IAP feature is avalaible on ATMEL chip with internal FLASH. This allows - the FLASH memory to be programmed even when the code is also running in - FLASH, without writing some SRAM relocated functions. - The IAP function entry point is written in the 3rd exception vector - (SWI at 0x300008), and is retrieved just by reading the value at this - address. - - ROM function algorithm : - // Send Command - AT91_BASE_MC->MC_FCR = FlashCmd - // Wait Flash is ready - while ((AT91C_BASE_MC->MC_FSR & AT91C_MC_FRDY) != AT91C_MC_FRDY) - return -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "iap.h" -#include -#include - -//------------------------------------------------------------------------------ -// Internal variables -//------------------------------------------------------------------------------ - - - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -/* - Function: IAP_PerformCmd - Perform a FLASH command through the IAP function. - - Returns: - 0 if the IAP function has executed correctly. - -1 if the IAP feature is not implemented in the ROM code. -*/ -unsigned long IAP_PerformCmd(unsigned long FlashCmd) -{ - // Pointer on IAP function in ROM - static void (*IAP_Function)(unsigned int) = 0; - - if (IAP_Function == 0) { - - IAP_Function = (void (*)(unsigned int)) (*((unsigned int *) IAP_FUNC_ADDR)); - TRACE_DEBUG("IAP_PerformCmd : IAP function address in ROM : 0x%08X\n\r", (unsigned int) IAP_Function); - - /* Check if IAP function is implemented (opcode in SWI != 'b' or 'ldr') */ - if ((((((unsigned long)IAP_Function >> 24) & 0xFF) == 0xEA) || - (((unsigned long)IAP_Function >> 24) & 0xFF) == 0xE5)) { - TRACE_ERROR("IAP_PerformCmd : no IAP function address found in ROM\n\r"); - IAP_Function = 0; - return -1; - } - } - - /* Perform FLASH command */ - IAP_Function(FlashCmd); - - return 0; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/iap.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/iap.h deleted file mode 100644 index 87a6bcd50..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/iap.h +++ /dev/null @@ -1,51 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: IAP - - About: Purpose - Small function for using IAP feature. - - About: Usage - Perform a FLASH command using . - -*/ - -#ifndef IAP_H -#define IAP_H - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned long IAP_PerformCmd (unsigned long FlashCmd); - -#endif //#ifndef IAP_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/led.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/led.c deleted file mode 100644 index a216b2a06..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/led.c +++ /dev/null @@ -1,164 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/// \file - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "led.h" -#include -#include - -//------------------------------------------------------------------------------ -// Local Variables -//------------------------------------------------------------------------------ - -#ifdef PINS_LEDS -static const Pin pinsLeds[] = {PINS_LEDS}; -static const unsigned int numLeds = PIO_LISTSIZE(pinsLeds); -#endif - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Configures the pin associated with the given LED number. If the LED does -/// not exist on the board, the function does nothing. -/// \param led Number of the LED to configure. -/// \return 1 if the LED exists and has been configured; otherwise 0. -//------------------------------------------------------------------------------ -unsigned char LED_Configure(unsigned int led) -{ -#ifdef PINS_LEDS - // Check that LED exists - if (led >= numLeds) { - - return 0; - } - - // Configure LED - return (PIO_Configure(&pinsLeds[led], 1)); -#else - return 0; -#endif -} - -//------------------------------------------------------------------------------ -/// Turns the given LED on if it exists; otherwise does nothing. -/// \param led Number of the LED to turn on. -/// \return 1 if the LED has been turned on; 0 otherwise. -//------------------------------------------------------------------------------ -unsigned char LED_Set(unsigned int led) -{ -#ifdef PINS_LEDS - // Check if LED exists - if (led >= numLeds) { - - return 0; - } - - // Turn LED on - if (pinsLeds[led].type == PIO_OUTPUT_0) { - - PIO_Set(&pinsLeds[led]); - } - else { - - PIO_Clear(&pinsLeds[led]); - } - - return 1; -#else - return 0; -#endif -} - -//------------------------------------------------------------------------------ -/// Turns a LED off. -/// \param led Number of the LED to turn off. -/// \param 1 if the LED has been turned off; 0 otherwise. -//------------------------------------------------------------------------------ -unsigned char LED_Clear(unsigned int led) -{ -#ifdef PINS_LEDS - // Check if LED exists - if (led >= numLeds) { - - return 0; - } - - // Turn LED off - if (pinsLeds[led].type == PIO_OUTPUT_0) { - - PIO_Clear(&pinsLeds[led]); - } - else { - - PIO_Set(&pinsLeds[led]); - } - - return 1; -#else - return 0; -#endif -} - -//------------------------------------------------------------------------------ -/// Toggles the current state of a LED. -/// \param led Number of the LED to toggle. -/// \return 1 if the LED has been toggled; otherwise 0. -//------------------------------------------------------------------------------ -unsigned char LED_Toggle(unsigned int led) -{ -#ifdef PINS_LEDS - // Check if LED exists - if (led >= numLeds) { - - return 0; - } - - // Toggle LED - if (PIO_GetOutputDataStatus(&pinsLeds[led])) { - - PIO_Clear(&pinsLeds[led]); - } - else { - - PIO_Set(&pinsLeds[led]); - } - - return 1; -#else - return 0; -#endif -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/led.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/led.h deleted file mode 100644 index 9a08a82dd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/led.h +++ /dev/null @@ -1,70 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \file -/// -/// \par Purpose -/// -/// Small set of functions for simple and portable LED usage. -/// -/// \par Usage -/// -/// -# Configure one or more LEDs using LED_Configure and -/// LED_ConfigureAll. -/// -# Set, clear and toggle LEDs using LED_Set, LED_Clear and -/// LED_Toggle. -/// -/// LEDs are numbered starting from 0; the number of LEDs depend on the -/// board being used. All the functions defined here will compile properly -/// regardless of whether the LED is defined or not; they will simply -/// return 0 when a LED which does not exist is given as an argument. -/// Also, these functions take into account how each LED is connected on to -/// board; thus, might change the level on the corresponding pin -/// to 0 or 1, but it will always light the LED on; same thing for the other -/// methods. -//------------------------------------------------------------------------------ - -#ifndef LED_H -#define LED_H - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -extern unsigned char LED_Configure(unsigned int led); - -extern unsigned char LED_Set(unsigned int led); - -extern unsigned char LED_Clear(unsigned int led); - -extern unsigned char LED_Toggle(unsigned int led); - -#endif //#ifndef LED_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/math.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/math.c deleted file mode 100644 index 39bed568c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/math.c +++ /dev/null @@ -1,91 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "math.h" -#include "trace.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the minimum value between two integers. -/// \param a First integer to compare. -/// \param b Second integer to compare. -//------------------------------------------------------------------------------ -unsigned int min(unsigned int a, unsigned int b) -{ - if (a < b) { - - return a; - } - else { - - return b; - } -} - -//------------------------------------------------------------------------------ -/// Returns the absolute value of an integer. -/// \param value Integer value. -//------------------------------------------------------------------------------ -// Do not call this function "abs", problem with gcc ! -unsigned int absv(signed int value) -{ - if (value < 0) { - - return -value; - } - else { - - return value; - } -} - -//------------------------------------------------------------------------------ -/// Computes and returns x power of y. -/// \param x Value. -/// \param y Power. -//------------------------------------------------------------------------------ -unsigned int power(unsigned int x, unsigned int y) -{ - unsigned int result = 1; - - while (y > 0) { - - result *= x; - y--; - } - return result; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/math.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/math.h deleted file mode 100644 index 6394f2992..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/math.h +++ /dev/null @@ -1,41 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef MATH_H -#define MATH_H - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned int min(unsigned int a, unsigned int b); -extern unsigned int absv(signed int value); -extern unsigned int power(unsigned int x, unsigned int y); -#endif //#ifndef MATH_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/rand.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/rand.c deleted file mode 100644 index 9a0f986de..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/rand.c +++ /dev/null @@ -1,60 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#include "rand.h" - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -static unsigned long int next = 1; - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Initialize the seed for rand generator. -/// \param seed rand initiation seed -//------------------------------------------------------------------------------ -void srand(unsigned int seed) -{ - next = seed; -} - -//------------------------------------------------------------------------------ -/// Return a random number, maxinum assumed to be 65536 -//------------------------------------------------------------------------------ - -int rand(void) -{ - next = next * 1103515245 + 12345; - return (unsigned int)(next/131072) % 65536; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/rand.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/rand.h deleted file mode 100644 index 8a8b21e2a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/rand.h +++ /dev/null @@ -1,49 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Small function for gererating random number. -/// -//------------------------------------------------------------------------------ - -#ifndef RAND_H -#define RAND_H - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -extern void srand(unsigned int seed); -extern int rand(void); - -#endif //#ifndef RAND_H diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/retarget.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/retarget.c deleted file mode 100644 index 1ca875ecd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/retarget.c +++ /dev/null @@ -1,88 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// This file Configures the target-dependent low level functions for character I/O. -/// -/// !Contents -/// The code implement the lower-level functions as follows: -/// - fputc -/// - ferror -/// - _ttywrch -/// - _sys_exit -/// -/// -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ -#include -#include - -// Disable semihosting -#pragma import(__use_no_semihosting_swi) - -struct __FILE { int handle;} ; -FILE __stdout; -FILE __stderr; - -//------------------------------------------------------------------------------ -/// Outputs a character to a file. -//------------------------------------------------------------------------------ -int fputc(int ch, FILE *f) { - if ((f == stdout) || (f == stderr)) { - DBGU_PutChar(ch); - return ch; - } - else { - return EOF; - } -} - -//------------------------------------------------------------------------------ -/// Returns the error status accumulated during file I/O. -//------------------------------------------------------------------------------ -int ferror(FILE *f) { - return EOF; -} - - -void _ttywrch(int ch) { - DBGU_PutChar((unsigned char)ch); -} - - -void _sys_exit(int return_code) { - label: goto label; /* endless loop */ -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/stdio.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/stdio.c deleted file mode 100644 index defbbc08d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/stdio.c +++ /dev/null @@ -1,511 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// Implementation of several stdio.h methods, such as printf(), sprintf() and -/// so on. This reduces the memory footprint of the binary when using those -/// methods, compared to the libc implementation. -/// -/// !Usage -/// -/// Adds stdio.c to the list of file to compile for the project. This will -/// automatically replace libc methods by the custom ones. -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include -#include - -//------------------------------------------------------------------------------ -// Local Definitions -//------------------------------------------------------------------------------ - -// Maximum string size allowed (in bytes). -#define MAX_STRING_SIZE 100 - -//------------------------------------------------------------------------------ -// Global Variables -//------------------------------------------------------------------------------ - -// Required for proper compilation. -struct _reent r = {0, (FILE *) 0, (FILE *) 1, (FILE *) 0}; -struct _reent *_impure_ptr = &r; - -//------------------------------------------------------------------------------ -// Local Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Writes a character inside the given string. Returns 1. -// \param pStr Storage string. -// \param c Character to write. -//------------------------------------------------------------------------------ -signed int PutChar(char *pStr, char c) -{ - *pStr = c; - return 1; -} - -//------------------------------------------------------------------------------ -// Writes a string inside the given string. -// Returns the size of the written -// string. -// \param pStr Storage string. -// \param pSource Source string. -//------------------------------------------------------------------------------ -signed int PutString(char *pStr, const char *pSource) -{ - signed int num = 0; - - while (*pSource != 0) { - - *pStr++ = *pSource++; - num++; - } - - return num; -} - -//------------------------------------------------------------------------------ -// Writes an unsigned int inside the given string, using the provided fill & -// width parameters. -// Returns the size in characters of the written integer. -// \param pStr Storage string. -// \param fill Fill character. -// \param width Minimum integer width. -// \param value Integer value. -//------------------------------------------------------------------------------ -signed int PutUnsignedInt( - char *pStr, - char fill, - signed int width, - unsigned int value) -{ - signed int num = 0; - - // Take current digit into account when calculating width - width--; - - // Recursively write upper digits - if ((value / 10) > 0) { - - num = PutUnsignedInt(pStr, fill, width, value / 10); - pStr += num; - } - // Write filler characters - else { - - while (width > 0) { - - PutChar(pStr, fill); - pStr++; - num++; - width--; - } - } - - // Write lower digit - num += PutChar(pStr, (value % 10) + '0'); - - return num; -} - -//------------------------------------------------------------------------------ -// Writes a signed int inside the given string, using the provided fill & width -// parameters. -// Returns the size of the written integer. -// \param pStr Storage string. -// \param fill Fill character. -// \param width Minimum integer width. -// \param value Signed integer value. -//------------------------------------------------------------------------------ -signed int PutSignedInt( - char *pStr, - char fill, - signed int width, - signed int value) -{ - signed int num = 0; - unsigned int absolute; - - // Compute absolute value - if (value < 0) { - - absolute = -value; - } - else { - - absolute = value; - } - - // Take current digit into account when calculating width - width--; - - // Recursively write upper digits - if ((absolute / 10) > 0) { - - if (value < 0) { - - num = PutSignedInt(pStr, fill, width, -(absolute / 10)); - } - else { - - num = PutSignedInt(pStr, fill, width, absolute / 10); - } - pStr += num; - } - else { - - // Reserve space for sign - if (value < 0) { - - width--; - } - - // Write filler characters - while (width > 0) { - - PutChar(pStr, fill); - pStr++; - num++; - width--; - } - - // Write sign - if (value < 0) { - - num += PutChar(pStr, '-'); - pStr++; - } - } - - // Write lower digit - num += PutChar(pStr, (absolute % 10) + '0'); - - return num; -} - -//------------------------------------------------------------------------------ -// Writes an hexadecimal value into a string, using the given fill, width & -// capital parameters. -// Returns the number of char written. -// \param pStr Storage string. -// \param fill Fill character. -// \param width Minimum integer width. -// \param maj Indicates if the letters must be printed in lower- or upper-case. -// \param value Hexadecimal value. -//------------------------------------------------------------------------------ -signed int PutHexa( - char *pStr, - char fill, - signed int width, - unsigned char maj, - unsigned int value) -{ - signed int num = 0; - - // Decrement width - width--; - - // Recursively output upper digits - if ((value >> 4) > 0) { - - num += PutHexa(pStr, fill, width, maj, value >> 4); - pStr += num; - } - // Write filler chars - else { - - while (width > 0) { - - PutChar(pStr, fill); - pStr++; - num++; - width--; - } - } - - // Write current digit - if ((value & 0xF) < 10) { - - PutChar(pStr, (value & 0xF) + '0'); - } - else if (maj) { - - PutChar(pStr, (value & 0xF) - 10 + 'A'); - } - else { - - PutChar(pStr, (value & 0xF) - 10 + 'a'); - } - num++; - - return num; -} - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Stores the result of a formatted string into another string. Format -/// arguments are given in a va_list instance. -/// Return the number of characters written. -/// \param pStr Destination string. -/// \param length Length of Destination string. -/// \param pFormat Format string. -/// \param ap Argument list. -//------------------------------------------------------------------------------ -signed int vsnprintf(char *pStr, size_t length, const char *pFormat, va_list ap) -{ - char fill; - unsigned char width; - signed int num = 0; - signed int size = 0; - - // Clear the string - if (pStr) { - - *pStr = 0; - } - - // Phase string - while (*pFormat != 0 && size < length) { - - // Normal character - if (*pFormat != '%') { - - *pStr++ = *pFormat++; - size++; - } - // Escaped '%' - else if (*(pFormat+1) == '%') { - - *pStr++ = '%'; - pFormat += 2; - size++; - } - // Token delimiter - else { - - fill = ' '; - width = 0; - pFormat++; - - // Parse filler - if (*pFormat == '0') { - - fill = '0'; - pFormat++; - } - - // Parse width - while ((*pFormat >= '0') && (*pFormat <= '9')) { - - width = (width*10) + *pFormat-'0'; - pFormat++; - } - - // Check if there is enough space - if (size + width > length) { - - width = length - size; - } - - // Parse type - switch (*pFormat) { - case 'd': - case 'i': num = PutSignedInt(pStr, fill, width, va_arg(ap, signed int)); break; - case 'u': num = PutUnsignedInt(pStr, fill, width, va_arg(ap, unsigned int)); break; - case 'x': num = PutHexa(pStr, fill, width, 0, va_arg(ap, unsigned int)); break; - case 'X': num = PutHexa(pStr, fill, width, 1, va_arg(ap, unsigned int)); break; - case 's': num = PutString(pStr, va_arg(ap, char *)); break; - case 'c': num = PutChar(pStr, va_arg(ap, unsigned int)); break; - default: - return EOF; - } - - pFormat++; - pStr += num; - size += num; - } - } - - // NULL-terminated (final \0 is not counted) - if (size < length) { - - *pStr = 0; - } - else { - - *(--pStr) = 0; - size--; - } - - return size; -} - -//------------------------------------------------------------------------------ -/// Stores the result of a formatted string into another string. Format -/// arguments are given in a va_list instance. -/// Return the number of characters written. -/// \param pString Destination string. -/// \param length Length of Destination string. -/// \param pFormat Format string. -/// \param ... Other arguments -//------------------------------------------------------------------------------ -signed int snprintf(char *pString, size_t length, const char *pFormat, ...) -{ - va_list ap; - signed int rc; - - va_start(ap, pFormat); - rc = vsnprintf(pString, length, pFormat, ap); - va_end(ap); - - return rc; -} - -//------------------------------------------------------------------------------ -/// Stores the result of a formatted string into another string. Format -/// arguments are given in a va_list instance. -/// Return the number of characters written. -/// \param pString Destination string. -/// \param pFormat Format string. -/// \param ap Argument list. -//------------------------------------------------------------------------------ -signed int vsprintf(char *pString, const char *pFormat, va_list ap) -{ - return vsnprintf(pString, MAX_STRING_SIZE, pFormat, ap); -} - -//------------------------------------------------------------------------------ -/// Outputs a formatted string on the given stream. Format arguments are given -/// in a va_list instance. -/// \param pStream Output stream. -/// \param pFormat Format string -/// \param ap Argument list. -//------------------------------------------------------------------------------ -signed int vfprintf(FILE *pStream, const char *pFormat, va_list ap) -{ - char pStr[MAX_STRING_SIZE]; - char pError[] = "stdio.c: increase MAX_STRING_SIZE\n\r"; - - // Write formatted string in buffer - if (vsprintf(pStr, pFormat, ap) >= MAX_STRING_SIZE) { - - fputs(pError, stderr); - while (1); // Increase MAX_STRING_SIZE - } - - // Display string - return fputs(pStr, pStream); -} - -//------------------------------------------------------------------------------ -/// Outputs a formatted string on the DBGU stream. Format arguments are given -/// in a va_list instance. -/// \param pFormat Format string -/// \param ap Argument list. -//------------------------------------------------------------------------------ -signed int vprintf(const char *pFormat, va_list ap) -{ - return vfprintf(stdout, pFormat, ap); -} - -//------------------------------------------------------------------------------ -/// Outputs a formatted string on the given stream, using a variable number of -/// arguments. -/// \param pStream Output stream. -/// \param pFormat Format string. -//------------------------------------------------------------------------------ -signed int fprintf(FILE *pStream, const char *pFormat, ...) -{ - va_list ap; - signed int result; - - // Forward call to vfprintf - va_start(ap, pFormat); - result = vfprintf(pStream, pFormat, ap); - va_end(ap); - - return result; -} - -//------------------------------------------------------------------------------ -/// Outputs a formatted string on the DBGU stream, using a variable number of -/// arguments. -/// \param pFormat Format string. -//------------------------------------------------------------------------------ -signed int printf(const char *pFormat, ...) -{ - va_list ap; - signed int result; - - // Forward call to vprintf - va_start(ap, pFormat); - result = vprintf(pFormat, ap); - va_end(ap); - - return result; -} - -//------------------------------------------------------------------------------ -/// Writes a formatted string inside another string. -/// \param pStr Storage string. -/// \param pFormat Format string. -//------------------------------------------------------------------------------ -signed int sprintf(char *pStr, const char *pFormat, ...) -{ - va_list ap; - signed int result; - - // Forward call to vsprintf - va_start(ap, pFormat); - result = vsprintf(pStr, pFormat, ap); - va_end(ap); - - return result; -} - -//------------------------------------------------------------------------------ -/// Outputs a string on stdout. -/// \param pStr String to output. -//------------------------------------------------------------------------------ -signed int puts(const char *pStr) -{ - return fputs(pStr, stdout); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/string.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/string.c deleted file mode 100644 index dbbb0e9ef..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/string.c +++ /dev/null @@ -1,239 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// Implementation of several methods defined in string.h, for reducing the -/// memory footprint when using them (since the whole libc.o file gets included -/// even when using a single method). -/// -/// !Usage -/// -/// Add string.c to the list of files to compile for the project. This will -/// automatically replace standard libc methods by the custom ones. -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Copies data from a source buffer into a destination buffer. The two buffers -/// must NOT overlap. Returns the destination buffer. -/// \param pDestination Destination buffer. -/// \param pSource Source buffer. -/// \param num Number of bytes to copy. -//------------------------------------------------------------------------------ -void * memcpy(void *pDestination, const void *pSource, size_t num) -{ - unsigned char *pByteDestination; - unsigned char *pByteSource; - unsigned int *pAlignedSource = (unsigned int *) pSource; - unsigned int *pAlignedDestination = (unsigned int *) pDestination; - - // If num is more than 4 bytes, and both dest. and source are aligned, - // then copy dwords - if ((((unsigned int) pAlignedDestination & 0x3) == 0) - && (((unsigned int) pAlignedSource & 0x3) == 0) - && (num >= 4)) { - - while (num >= 4) { - - *pAlignedDestination++ = *pAlignedSource++; - num -= 4; - } - } - - // Copy remaining bytes - pByteDestination = (unsigned char *) pAlignedDestination; - pByteSource = (unsigned char *) pAlignedSource; - while (num--) { - - *pByteDestination++ = *pByteSource++; - } - - return pDestination; -} - -//------------------------------------------------------------------------------ -/// Fills a memory region with the given value. Returns a pointer to the -/// memory region. -/// \param pBuffer Pointer to the start of the memory region to fill -/// \param value Value to fill the region with -/// \param num Size to fill in bytes -//------------------------------------------------------------------------------ -void * memset(void *pBuffer, int value, size_t num) -{ - unsigned char *pByteDestination; - unsigned int *pAlignedDestination = (unsigned int *) pBuffer; - unsigned int alignedValue = (value << 24) | (value << 16) | (value << 8) | value; - - // Set words if possible - if ((((unsigned int) pAlignedDestination & 0x3) == 0) && (num >= 4)) { - while (num >= 4) { - *pAlignedDestination++ = alignedValue; - num -= 4; - } - } - // Set remaining bytes - pByteDestination = (unsigned char *) pAlignedDestination; - while (num--) { - *pByteDestination++ = value; - } - return pBuffer; -} - -//----------------------------------------------------------------------------- -/// Search a character in the given string. -/// Returns a pointer to the character location. -/// \param pString Pointer to the start of the string to search. -/// \param character The character to find. -//----------------------------------------------------------------------------- -char * strchr(const char *pString, int character) -{ - char * p = (char *)pString; - char c = character & 0xFF; - - while(*p != c) { - if (*p == 0) { - return 0; - } - p++; - } - return p; -} - -//----------------------------------------------------------------------------- -/// Return the length of a given string -/// \param pString Pointer to the start of the string. -//----------------------------------------------------------------------------- -size_t strlen(const char *pString) -{ - unsigned int length = 0; - - while(*pString++ != 0) { - length++; - } - return length; -} - - -//----------------------------------------------------------------------------- -/// Search a character backword from the end of given string. -/// Returns a pointer to the character location. -/// \param pString Pointer to the start of the string to search. -/// \param character The character to find. -//----------------------------------------------------------------------------- -char * strrchr(const char *pString, int character) -{ - char *p = 0; - - while(*pString != 0) { - if (*pString++ == character) { - p = (char*)pString; - } - } - return p; -} - -//----------------------------------------------------------------------------- -/// Copy from source string to destination string -/// Return a pointer to the destination string -/// \param pDestination Pointer to the destination string. -/// \param pSource Pointer to the source string. -//----------------------------------------------------------------------------- -char * strcpy(char *pDestination, const char *pSource) -{ - char *pSaveDest = pDestination; - - for(; (*pDestination = *pSource) != 0; ++pSource, ++pDestination); - return pSaveDest; -} - -//----------------------------------------------------------------------------- -/// Compare the first specified bytes of 2 given strings -/// Return 0 if equals -/// Return >0 if 1st string > 2nd string -/// Return <0 if 1st string < 2nd string -/// \param pString1 Pointer to the start of the 1st string. -/// \param pString2 Pointer to the start of the 2nd string. -/// \param count Number of bytes that should be compared. -//----------------------------------------------------------------------------- -int strncmp(const char *pString1, const char *pString2, size_t count) -{ - int r; - - while(count) { - r = *pString1 - *pString2; - if (r == 0) { - if (*pString1 == 0) { - break; - } - pString1++; - pString2++; - count--; - continue; - } - return r; - } - return 0; -} - -//----------------------------------------------------------------------------- -/// Copy the first number of bytes from source string to destination string -/// Return the pointer to the destination string. -/// \param pDestination Pointer to the start of destination string. -/// \param pSource Pointer to the start of the source string. -/// \param count Number of bytes that should be copied. -//----------------------------------------------------------------------------- -char * strncpy(char *pDestination, const char *pSource, size_t count) -{ - char *pSaveDest = pDestination; - - while (count) { - *pDestination = *pSource; - if (*pSource == 0) { - break; - } - pDestination++; - pSource++; - count--; - } - return pSaveDest; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/trace.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/trace.c deleted file mode 100644 index 4073bb9bb..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/trace.c +++ /dev/null @@ -1,45 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "trace.h" - -//------------------------------------------------------------------------------ -// Internal variables -//------------------------------------------------------------------------------ - -/// Trace level can be set at applet initialization -#if !defined(NOTRACE) && (DYN_TRACES == 1) - unsigned int traceLevel = TRACE_LEVEL; -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/trace.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/trace.h deleted file mode 100644 index 63e7617a3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/trace.h +++ /dev/null @@ -1,241 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \file -/// -/// \par Purpose -/// -/// Standard output methods for reporting debug information, warnings and -/// errors, which can be easily be turned on/off. -/// -/// \par Usage -/// -# Initialize the DBGU using TRACE_CONFIGURE() if you intend to eventually -/// disable ALL traces; otherwise use DBGU_Configure(). -/// -# Uses the TRACE_DEBUG(), TRACE_INFO(), TRACE_WARNING(), TRACE_ERROR() -/// TRACE_FATAL() macros to output traces throughout the program. -/// -# Each type of trace has a level : Debug 5, Info 4, Warning 3, Error 2 -/// and Fatal 1. Disable a group of traces by changing the value of -/// TRACE_LEVEL during compilation; traces with a level bigger than TRACE_LEVEL -/// are not generated. To generate no trace, use the reserved value 0. -/// -# Trace disabling can be static or dynamic. If dynamic disabling is selected -/// the trace level can be modified in runtime. If static disabling is selected -/// the disabled traces are not compiled. -/// -/// \par traceLevels Trace level description -/// -# TRACE_DEBUG (5): Traces whose only purpose is for debugging the program, -/// and which do not produce meaningful information otherwise. -/// -# TRACE_INFO (4): Informational trace about the program execution. Should -/// enable the user to see the execution flow. -/// -# TRACE_WARNING (3): Indicates that a minor error has happened. In most case -/// it can be discarded safely; it may even be expected. -/// -# TRACE_ERROR (2): Indicates an error which may not stop the program execution, -/// but which indicates there is a problem with the code. -/// -# TRACE_FATAL (1): Indicates a major error which prevents the program from going -/// any further. - -//------------------------------------------------------------------------------ - -#ifndef TRACE_H -#define TRACE_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include -#include -#include - -//------------------------------------------------------------------------------ -// Global Definitions -//------------------------------------------------------------------------------ - -/// Softpack Version -#define SOFTPACK_VERSION "1.0beta1" - -#define TRACE_LEVEL_DEBUG 5 -#define TRACE_LEVEL_INFO 4 -#define TRACE_LEVEL_WARNING 3 -#define TRACE_LEVEL_ERROR 2 -#define TRACE_LEVEL_FATAL 1 -#define TRACE_LEVEL_NO_TRACE 0 - -// By default, all traces are output except the debug one. -#if !defined(TRACE_LEVEL) -#define TRACE_LEVEL TRACE_LEVEL_INFO -#endif - -// By default, trace level is static (not dynamic) -#if !defined(DYN_TRACES) -#define DYN_TRACES 0 -#endif - -#if defined(NOTRACE) -#error "Error: NOTRACE has to be not defined !" -#endif - -#undef NOTRACE -#if (DYN_TRACES==0) - #if (TRACE_LEVEL == TRACE_LEVEL_NO_TRACE) - #define NOTRACE - #endif -#endif - - - -//------------------------------------------------------------------------------ -// Global Macros -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Initializes the DBGU -/// \param mode DBGU mode. -/// \param baudrate DBGU baudrate. -/// \param mck Master clock frequency. -//------------------------------------------------------------------------------ -#define TRACE_CONFIGURE(mode, baudrate, mck) { \ - const Pin pinsDbgu[] = {PINS_DBGU}; \ - PIO_Configure(pinsDbgu, PIO_LISTSIZE(pinsDbgu)); \ - DBGU_Configure(mode, baudrate, mck); \ - } - -//------------------------------------------------------------------------------ -/// Initializes the DBGU for ISP project -/// \param mode DBGU mode. -/// \param baudrate DBGU baudrate. -/// \param mck Master clock frequency. -//------------------------------------------------------------------------------ -#ifndef DYNTRACE -#define DYNTRACE 0 -#endif - -#if (TRACE_LEVEL==0) && (DYNTRACE==0) -#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) {} -#else -#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) { \ - const Pin pinsDbgu[] = {PINS_DBGU}; \ - PIO_Configure(pinsDbgu, PIO_LISTSIZE(pinsDbgu)); \ - DBGU_Configure(mode, baudrate, mck); \ - } -#endif - -//------------------------------------------------------------------------------ -/// Outputs a formatted string using if the log level is high -/// enough. Can be disabled by defining TRACE_LEVEL=0 during compilation. -/// \param format Formatted string to output. -/// \param ... Additional parameters depending on formatted string. -//------------------------------------------------------------------------------ -#if defined(NOTRACE) - -// Empty macro -#define TRACE_DEBUG(...) { } -#define TRACE_INFO(...) { } -#define TRACE_WARNING(...) { } -#define TRACE_ERROR(...) { } -#define TRACE_FATAL(...) { while(1); } - -#define TRACE_DEBUG_WP(...) { } -#define TRACE_INFO_WP(...) { } -#define TRACE_WARNING_WP(...) { } -#define TRACE_ERROR_WP(...) { } -#define TRACE_FATAL_WP(...) { while(1); } - -#elif (DYN_TRACES == 1) - -// Trace output depends on traceLevel value -#define TRACE_DEBUG(...) { if (traceLevel >= TRACE_LEVEL_DEBUG) { printf("-D- " __VA_ARGS__); } } -#define TRACE_INFO(...) { if (traceLevel >= TRACE_LEVEL_INFO) { printf("-I- " __VA_ARGS__); } } -#define TRACE_WARNING(...) { if (traceLevel >= TRACE_LEVEL_WARNING) { printf("-W- " __VA_ARGS__); } } -#define TRACE_ERROR(...) { if (traceLevel >= TRACE_LEVEL_ERROR) { printf("-E- " __VA_ARGS__); } } -#define TRACE_FATAL(...) { if (traceLevel >= TRACE_LEVEL_FATAL) { printf("-F- " __VA_ARGS__); while(1); } } - -#define TRACE_DEBUG_WP(...) { if (traceLevel >= TRACE_LEVEL_DEBUG) { printf(__VA_ARGS__); } } -#define TRACE_INFO_WP(...) { if (traceLevel >= TRACE_LEVEL_INFO) { printf(__VA_ARGS__); } } -#define TRACE_WARNING_WP(...) { if (traceLevel >= TRACE_LEVEL_WARNING) { printf(__VA_ARGS__); } } -#define TRACE_ERROR_WP(...) { if (traceLevel >= TRACE_LEVEL_ERROR) { printf(__VA_ARGS__); } } -#define TRACE_FATAL_WP(...) { if (traceLevel >= TRACE_LEVEL_FATAL) { printf(__VA_ARGS__); while(1); } } - -#else - -// Trace compilation depends on TRACE_LEVEL value -#if (TRACE_LEVEL >= TRACE_LEVEL_DEBUG) -#define TRACE_DEBUG(...) { printf("-D- " __VA_ARGS__); } -#define TRACE_DEBUG_WP(...) { printf(__VA_ARGS__); } -#else -#define TRACE_DEBUG(...) { } -#define TRACE_DEBUG_WP(...) { } -#endif - -#if (TRACE_LEVEL >= TRACE_LEVEL_INFO) -#define TRACE_INFO(...) { printf("-I- " __VA_ARGS__); } -#define TRACE_INFO_WP(...) { printf(__VA_ARGS__); } -#else -#define TRACE_INFO(...) { } -#define TRACE_INFO_WP(...) { } -#endif - -#if (TRACE_LEVEL >= TRACE_LEVEL_WARNING) -#define TRACE_WARNING(...) { printf("-W- " __VA_ARGS__); } -#define TRACE_WARNING_WP(...) { printf(__VA_ARGS__); } -#else -#define TRACE_WARNING(...) { } -#define TRACE_WARNING_WP(...) { } -#endif - -#if (TRACE_LEVEL >= TRACE_LEVEL_ERROR) -#define TRACE_ERROR(...) { printf("-E- " __VA_ARGS__); } -#define TRACE_ERROR_WP(...) { printf(__VA_ARGS__); } -#else -#define TRACE_ERROR(...) { } -#define TRACE_ERROR_WP(...) { } -#endif - -#if (TRACE_LEVEL >= TRACE_LEVEL_FATAL) -#define TRACE_FATAL(...) { printf("-F- " __VA_ARGS__); while(1); } -#define TRACE_FATAL_WP(...) { printf(__VA_ARGS__); while(1); } -#else -#define TRACE_FATAL(...) { while(1); } -#define TRACE_FATAL_WP(...) { while(1); } -#endif - -#endif - - -//------------------------------------------------------------------------------ -// Exported variables -//------------------------------------------------------------------------------ -// Depending on DYN_TRACES, traceLevel is a modifable runtime variable -// or a define -#if !defined(NOTRACE) && (DYN_TRACES == 1) - extern unsigned int traceLevel; -#endif - -#endif //#ifndef TRACE_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/util.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/util.c deleted file mode 100644 index b2bd0dea1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/util.c +++ /dev/null @@ -1,223 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ -#include -#include -#include - -//------------------------------------------------------------------------------ -// Local Variables -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Print char if printable. If not print a point -/// \param c char to -//------------------------------------------------------------------------------ -static void PrintChar(unsigned char c) -{ - if( (/*c >= 0x00 &&*/ c <= 0x1F) || - (c >= 0xB0 && c <= 0xDF) ) { - - printf("."); - } - else { - - printf("%c", c); - } -} - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Displays the content of the given frame on the DBGU. -/// \param pBuffer Pointer to the frame to dump. -/// \param size Buffer size in bytes. -//------------------------------------------------------------------------------ -void UTIL_DbguDumpFrame(unsigned char *pFrame, unsigned int size) -{ - unsigned int i; - - for (i=0; i < size; i++) { - printf("%02X ", pFrame[i]); - } - - printf("\n\r"); -} - -//------------------------------------------------------------------------------ -/// Displays the content of the given buffer on the DBGU. -/// \param pBuffer Pointer to the buffer to dump. -/// \param size Buffer size in bytes. -/// \param address Start address to display -//------------------------------------------------------------------------------ -void UTIL_DbguDumpMemory( - unsigned char *pBuffer, - unsigned int size, - unsigned int address - ) -{ - unsigned int i, j; - unsigned int lastLineStart; - unsigned char* pTmp; - - for (i=0; i < (size / 16); i++) { - - printf("0x%08X: ", address + (i*16)); - pTmp = (unsigned char*)&pBuffer[i*16]; - for (j=0; j < 4; j++) { - printf("%02X%02X%02X%02X ", pTmp[0],pTmp[1],pTmp[2],pTmp[3]); - pTmp += 4; - } - - pTmp = (unsigned char*)&pBuffer[i*16]; - for (j=0; j < 16; j++) { - PrintChar(*pTmp++); - } - - printf("\n\r"); - } - - if( (size%16) != 0) { - lastLineStart = size - (size%16); - printf("0x%08X: ", address + lastLineStart); - - for (j= lastLineStart; j < lastLineStart+16; j++) { - - if( (j!=lastLineStart) && (j%4 == 0) ) { - printf(" "); - } - if(j= '0' && key <= '9' ) { - value = (value * 10) + (key - '0'); - nbNb++; - } - else if(key == 0x0D || key == ' ') { - if(nbNb == 0) { - printf("\n\rWrite a number and press ENTER or SPACE!\n\r"); - return 0; - } else { - printf("\n\r"); - *pValue = value; - return 1; - } - } else { - printf("\n\r'%c' not a number!\n\r", key); - return 0; - } - } -} - -//------------------------------------------------------------------------------ -/// Reads an integer and check the value -//------------------------------------------------------------------------------ -unsigned char UTIL_DbguGetIntegerMinMax( - unsigned int *pValue, - unsigned int min, - unsigned int max - ) -{ - unsigned int value = 0; - - if( UTIL_DbguGetInteger(&value) == 0) { - return 0; - } - - if(value < min || value > max) { - printf("\n\rThe number have to be between %d and %d\n\r", min, max); - return 0; - } - - printf("\n\r"); - *pValue = value; - return 1; -} - -//------------------------------------------------------------------------------ -/// Reads an hexadecimal number -//------------------------------------------------------------------------------ -unsigned char UTIL_DbguGetHexa32(unsigned int *pValue) -{ - unsigned char key; - unsigned int i = 0; - unsigned int value = 0; - for(i = 0; i < 8; i++) { - key = DBGU_GetChar(); - DBGU_PutChar(key); - if(key >= '0' && key <= '9' ) { - value = (value * 16) + (key - '0'); - } - else if(key >= 'A' && key <= 'F' ) { - value = (value * 16) + (key - 'A' + 10) ; - } - else if(key >= 'a' && key <= 'f' ) { - value = (value * 16) + (key - 'a' + 10) ; - } - else { - printf("\n\rIt is not a hexa character!\n\r"); - return 0; - } - } - - printf("\n\r"); - *pValue = value; - return 1; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/util.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/util.h deleted file mode 100644 index f79ffd3f7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/util.h +++ /dev/null @@ -1,48 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef UTIL_H -#define UTIL_H - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -extern void UTIL_DbguDumpFrame(unsigned char *pFrame, unsigned int size); - -extern void UTIL_DbguDumpMemory(unsigned char *pBuffer, unsigned int size, unsigned int address); - -extern unsigned char UTIL_DbguGetInteger(unsigned int *pValue); - -extern unsigned char UTIL_DbguGetIntegerMinMax(unsigned int *pValue, unsigned int min, unsigned int max); - -extern unsigned char UTIL_DbguGetHexa32(unsigned int *pValue); - -#endif //#ifndef UTIL_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/utility.dir b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/utility.dir deleted file mode 100644 index 344ef5a67..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/utility.dir +++ /dev/null @@ -1,50 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \dir -/// -/// !!!Purpose -/// -/// The utility directory contains several very small APIs for performing -/// specific tasks, such as LED configuration, BMP header decoding, etc. -/// -/// !!!Contents -/// -/// Most modules contained here are very small and do not fit in any of the -/// other at91lib categories. They primarily provide helper functions -/// (e.g. for handling BMP and WAV files) and re-implementation of libc code for -/// reducing code size (math, stdio, string). -/// -/// Two important files are assert.h and trace.h. The first one provides macros -/// for run-time verifications of parameters & values. Trace.h enables the -/// programmer to add debug traces to APIs that can be easily turned on or off -/// depending on the debugging needs. -//------------------------------------------------------------------------------ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/video.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/video.c deleted file mode 100644 index 49ec1da24..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/video.c +++ /dev/null @@ -1,130 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ -#include "video.h" - -//----------------------------------------------------------------------------- -/// Conversion YCrCb to RGB:
-/// R = 1.164(Yi 16) + 1.596(Cr 128)
-/// G = 1.164(Yi 16) 0.813(Cr 128) 0.391(Cb 128)
-/// B = 1.164(Yi 16) + 2.018(Cb 128)
-/// -/// Pixel i+1:
-/// YCrCb to RGB:
-/// R = 1.164(Yi+1 16) + 1.596(Cr 128)
-/// G = 1.164(Yi+1 16) 0.813(Cr 128) 0.391(Cb 128)
-/// B = 1.164(Yi+1 16) + 2.018(Cb 128) -/// \param ycc Source buffer (YCC) -/// \param rgb Destination buffer (RGB) -/// \param len Length of buffer -//----------------------------------------------------------------------------- -void VIDEO_Ycc2Rgb(unsigned char *ycc, unsigned short *rgb, unsigned int len) -{ - int r_calc_i; - int g_calc_i; - int b_calc_i; - int r_calc_i_incr; - int g_calc_i_incr; - int b_calc_i_incr; - int cr_i; - int y_i; - int cb_i; - int y_i_incr; - int val; - int val1; - int val2; - int val3; - int val4; - int val5; - int i; - - for(i=0; i 255) - r_calc_i = 255; - - if (g_calc_i < 0) - g_calc_i = 0; - else if (g_calc_i > 255) - g_calc_i = 255; - - if (b_calc_i < 0) - b_calc_i = 0; - else if (b_calc_i > 255) - b_calc_i = 255; - - if (r_calc_i_incr < 0) - r_calc_i_incr = 0; - else if (r_calc_i_incr > 255) - r_calc_i_incr = 255; - - if (g_calc_i_incr < 0) - g_calc_i_incr = 0; - else if (g_calc_i_incr > 255) - g_calc_i_incr = 255; - - if (b_calc_i_incr < 0) - b_calc_i_incr = 0; - else if (b_calc_i_incr > 255) - b_calc_i_incr = 255; - - *rgb++ = (((unsigned short )r_calc_i & 0xF8) >> 3) - | ((((unsigned short)g_calc_i & 0xF8) >> 3) << 5) - | ((((unsigned short)b_calc_i & 0xF8) >> 3) << 10); - - *rgb++ = (((unsigned short )r_calc_i_incr & 0xF8) >> 3) - | ((((unsigned short)g_calc_i_incr & 0xF8) >> 3) << 5) - | ((((unsigned short)b_calc_i_incr & 0xF8) >> 3) << 10); - } -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/video.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/video.h deleted file mode 100644 index c4940e51c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/video.h +++ /dev/null @@ -1,89 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Video structure, used for LCD and ISI. -/// Conversion Video from YCC to RGB -/// -//------------------------------------------------------------------------------ - -#ifndef _VIDEO_H -#define _VIDEO_H - -//----------------------------------------------------------------------------- -// Definitions -//----------------------------------------------------------------------------- -/// Type of video is YUV -#define YUV 0 -/// Type of video is RGB -#define RGB 1 - -//----------------------------------------------------------------------------- -/// Video structure -//----------------------------------------------------------------------------- -typedef struct _AT91S_VIDEO -{ - /// LCD Vertical Size - unsigned int lcd_vsize; - /// LCD Horizontal Size - unsigned int lcd_hsize; - /// LCD Number of Bit Per Pixel - unsigned int lcd_nbpp; - /// LCD Frame Buffer Address - unsigned int lcd_fb_addr; - /// Base address for the frame buffer descriptors list - unsigned int Isi_fbd_base; - /// Start of Line Delay - unsigned int Hblank; - /// Start of frame Delay - unsigned int Vblank; - /// Vertical size of the Image sensor [0..2047] - unsigned int codec_vsize; - /// Horizontal size of the Image sensor [0..2047] - unsigned int codec_hsize; - /// Base address for codec DMA - unsigned int codec_fb_addr; - /// Buffer index - unsigned int IsiPrevBuffIndex; - /// Type of video - unsigned char rgb_or_yuv; -}AT91S_VIDEO, *AT91PS_VIDEO; - - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -extern void VIDEO_Ycc2Rgb(unsigned char *ycc, unsigned short *rgb, unsigned int len); - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/wav.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/wav.c deleted file mode 100644 index cd75b1515..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/wav.c +++ /dev/null @@ -1,84 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "wav.h" -#include - -//------------------------------------------------------------------------------ -// Internal constants -//------------------------------------------------------------------------------ - -/// WAV letters "RIFF" -#define WAV_CHUNKID 0x46464952 -/// WAV letters "WAVE" -#define WAV_FORMAT 0x45564157 -/// WAV letters "fmt " -#define WAV_SUBCHUNKID 0x20746D66 - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns 1 if the header of a Wav file is valid; otherwise returns 0. -/// \param file Buffer holding the file to examinate. -//------------------------------------------------------------------------------ -unsigned char WAV_IsValid(const WavHeader *header) -{ - return ((header->chunkID == WAV_CHUNKID) - && (header->format == WAV_FORMAT) - && (header->subchunk1Size == 0x10)); -} - -//------------------------------------------------------------------------------ -/// Display the information of the WAV file (sample rate, stereo/mono and frame -/// size). -//------------------------------------------------------------------------------ -void WAV_DisplayInfo(const WavHeader *header) -{ - printf( "Wave file header information\n\r"); - printf( "--------------------------------\n\r"); - printf( " - Chunk ID = 0x%08X\n\r", header->chunkID); - printf( " - Chunk Size = %d\n\r", header->chunkSize); - printf( " - Format = 0x%08X\n\r", header->format); - printf( " - SubChunk ID = 0x%08X\n\r", header->subchunk1ID); - printf( " - Subchunk1 Size = %d\n\r", header->subchunk1Size); - printf( " - Audio Format = 0x%04X\n\r", header->audioFormat); - printf( " - Num. Channels = %d\n\r", header->numChannels); - printf( " - Sample Rate = %d\n\r", header->sampleRate); - printf( " - Byte Rate = %d\n\r", header->byteRate); - printf( " - Block Align = %d\n\r", header->blockAlign); - printf( " - Bits Per Sample = %d\n\r", header->bitsPerSample); - printf( " - Subchunk2 ID = 0x%08X\n\r", header->subchunk2ID); - printf( " - Subchunk2 Size = %d\n\r", header->subchunk2Size); -} \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/wav.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/wav.h deleted file mode 100644 index 4d26e84cc..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/utility/wav.h +++ /dev/null @@ -1,82 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef WAV_H -#define WAV_H - -//------------------------------------------------------------------------------ -// Exported types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Standard WAV file header information. -//------------------------------------------------------------------------------ -typedef struct _WavHeader -{ - /// Contains the letters "RIFF" in ASCII form. - unsigned int chunkID; - /// Size of the rest of the chunk following this number. - unsigned int chunkSize; - /// Contains the letters "WAVE". - unsigned int format; - /// Contains the letters "fmt ". - unsigned int subchunk1ID; - /// 16 for PCM. This is the size of the rest of the Subchunk - /// which follows this number. - unsigned int subchunk1Size; - /// PCM = 1 (i.e. Linear quantization). Values other than 1 indicate some - /// form of compression. - unsigned short audioFormat; - /// Mono = 1, Stereo = 2, etc. - unsigned short numChannels; - /// 8000, 44100, etc. - unsigned int sampleRate; - /// SampleRate * NumChannels * BitsPerSample/8 - unsigned int byteRate; - /// NumChannels * BitsPerSample/8 - unsigned short blockAlign; - /// 8 bits = 8, 16 bits = 16, etc. - unsigned short bitsPerSample; - /// Contains the letters "data". - unsigned int subchunk2ID; - /// Number of bytes in the data. - unsigned int subchunk2Size; - -} WavHeader; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char WAV_IsValid(const WavHeader *header); - -extern void WAV_DisplayInfo(const WavHeader *header); - -#endif //#ifndef WAV_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/wdt/wdt.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/wdt/wdt.c deleted file mode 100644 index 6d4f4a3d3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/wdt/wdt.c +++ /dev/null @@ -1,141 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of Watchdog Timer (WDT) controller. - * - */ - -/** \addtogroup wdt_module Working with WDT - * The WDT driver provides the interface to configure and use the WDT - * peripheral. - * - * The WDT can be used to prevent system lock-up if the software becomes - * trapped in a deadlock. It can generate a general reset or a processor - * reset only. It is clocked by slow clock divided by 128. - * - * The WDT is running at reset with 16 seconds watchdog period (slow clock at 32.768 kHz) - * and external reset generation enabled. The user must either disable it or - * reprogram it to meet the application requires. - * - * To use the WDT, the user could follow these few steps: - *
    - *
  • Enable watchdog with given mode using \ref WDT_Enable(). - *
  • Restart the watchdog using \ref WDT_Restart() within the watchdog period. - *
- * - * For more accurate information, please look at the WDT section of the - * Datasheet. - * - * \note - * The Watchdog Mode Register (WDT_MR) can be written only once.\n - * - * Related files :\n - * \ref wdt.c\n - * \ref wdt.h.\n - */ -/*@{*/ -/*@}*/ - -/*--------------------------------------------------------------------------- - * Headers - *---------------------------------------------------------------------------*/ - -/* These headers were introduced in C99 by working group ISO/IEC JTC1/SC22/WG14. */ -#include - -#include -#include "wdt.h" - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Enable watchdog with given mode. - * - * \note The Watchdog Mode Register (WDT_MR) can be written only once. - * Only a processor reset resets it. - * - * \param mode WDT mode to be set - */ -void WDT_Enable(uint32_t mode) -{ - Wdt *pWDT = WDT; - - pWDT->WDT_MR = mode; -} - -/** - * \brief Disable watchdog. - * - * \note The Watchdog Mode Register (WDT_MR) can be written only once. - * Only a processor reset resets it. - */ -void WDT_Disable(void) -{ - Wdt *pWDT = WDT; - - pWDT->WDT_MR = WDT_MR_WDDIS; -} - -/** - * \brief Watchdog restart. - */ -void WDT_Restart(void) -{ - Wdt *pWDT = WDT; - - pWDT->WDT_CR = 0xA5000001; -} - -/** - * \brief Watchdog get status. - */ -uint32_t WDT_GetStatus(void) -{ - Wdt *pWDT = WDT; - - return(pWDT->WDT_SR & 0x3); -} - -/** - * \brief Watchdog get period. - * - * \param ms desired watchdog period in millisecond. - */ -uint32_t WDT_GetPeriod(uint32_t ms) -{ - if ((ms < 4) || (ms > 16000)) { - return 0; - } - return((ms << 8) / 1000); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/wdt/wdt.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/wdt/wdt.h deleted file mode 100644 index ed30bb511..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/libraries/drivers/wdt/wdt.h +++ /dev/null @@ -1,61 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * \par Purpose - * Interface for Watchdog Timer (WDT) controller. - * - * \par Usage - * -# Enable watchdog with given mode using \ref WDT_Enable(). - * -# Disable watchdog using \ref WDT_Disable() - * -# Restart the watchdog using \ref WDT_Restart(). - * -# Get watchdog status using \ref WDT_GetStatus(). - * -# Caculate watchdog period value using \ref WDT_GetPeriod(). - */ - -#ifndef WDT_H -#define WDT_H - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void WDT_Enable(uint32_t mode); - -extern void WDT_Disable(void); - -extern void WDT_Restart(void); - -extern uint32_t WDT_GetStatus(void); - -extern uint32_t WDT_GetPeriod(uint32_t ms); - -#endif /* #ifndef WDT_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/port/port.h deleted file mode 100644 index b13410ecd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/port/port.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * FreeModbus Libary: Atmel AT91SAM3S Demo Application - * Copyright (C) 2010 Christian Walter - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * IF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -/* ----------------------- Platform includes --------------------------------*/ -#include -#include -#include -#include -#include -#include -#include - -/* ----------------------- Defines ------------------------------------------*/ -#define INLINE inline -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#define ENTER_CRITICAL_SECTION( ) vMBPortEnterCritical() -#define EXIT_CRITICAL_SECTION( ) vMBPortExitCritical() - -#define assert( x ) - -typedef char BOOL; - -typedef unsigned char UCHAR; -typedef char CHAR; - -typedef unsigned short USHORT; -typedef short SHORT; - -typedef unsigned long ULONG; -typedef long LONG; - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#define MB_PORT_HAS_CLOSE 1 -#define MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS 2 - -/* ----------------------- Prototypes ---------------------------------------*/ -void vMBPortEnterCritical( void ); -void vMBPortExitCritical( void ); - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/port/portevent.c deleted file mode 100644 index 643eec735..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/port/portevent.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * FreeModbus Libary: Atmel AT91SAM3S Demo Application - * Copyright (C) 2010 Christian Walter - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * IF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static eMBEventType eQueuedEvent; -static BOOL xEventInQueue; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - xEventInQueue = FALSE; - return TRUE; -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - xEventInQueue = TRUE; - eQueuedEvent = eEvent; - return TRUE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - BOOL xEventHappened = FALSE; - - if( xEventInQueue ) - { - *eEvent = eQueuedEvent; - xEventInQueue = FALSE; - xEventHappened = TRUE; - } - return xEventHappened; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/port/portother.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/port/portother.c deleted file mode 100644 index d6b2fb7b8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/port/portother.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * FreeModbus Libary: Atmel AT91SAM3S Demo Application - * Copyright (C) 2010 Christian Walter - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * IF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * File: $Id$ - */ - - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include - -/* ----------------------- Variables ----------------------------------------*/ -static ULONG ulNesting; -static __istate_t xOldState; - -/* ----------------------- Start implementation -----------------------------*/ -void -vMBPortEnterCritical( void ) -{ - __istate_t xCurState; - xCurState = __get_interrupt_state( ); - __disable_interrupt( ); - if( ulNesting == 0 ) - { - xOldState = xCurState; - } - ulNesting++; -} - -void -vMBPortExitCritical( void ) -{ - ulNesting--; - if( 0 == ulNesting ) - { - __set_interrupt_state( xOldState ); - } -} - -void -vMBPortClose( void ) -{ - extern void vMBPortSerialClose( void ); - extern void vMBPortTimerClose( void ); - vMBPortSerialClose( ); - vMBPortTimerClose( ); -} \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/port/portserial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/port/portserial.c deleted file mode 100644 index 53fe5fea0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/port/portserial.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * FreeModbus Libary: Atmel AT91SAM3S Demo Application - * Copyright (C) 2010 Christian Walter - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * IF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * File: $Id$ - */ - -/* ----------------------- Platform includes --------------------------------*/ -#include -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define USART0_ENABLED ( 1 ) -#define USART0_IDX ( 0 ) - -#define USART1_ENABLED ( 1 ) -#define USART1_IDX ( USART0_IDX + USART0_ENABLED * 1 ) - -#define USART_IDX_LAST ( USART1_IDX ) - -#define USART_INVALID_PORT ( 0xFF ) -#define USART_NOT_RE_IDX ( 3 ) -#define USART_DE_IDX ( 4 ) - -/* ----------------------- Static variables ---------------------------------*/ - -#if USART1_ENABLED == 1 -const Pin xUSART0Pins[] = { - PIN_USART0_TXD, - PIN_USART0_RXD -}; -#endif - -#if USART1_ENABLED == 1 -const Pin xUSART1NotREPin = { 1 << 25, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT }; -const Pin xUSART1DEPin = { 1 << 24, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT }; - -const Pin xUSART1Pins[] = { - PIN_USART1_TXD, - PIN_USART1_RXD, - {1 << 23, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} -}; -#endif - -const struct xUSARTHWMappings_t -{ - Usart *pUsart; - unsigned int xUSARTID; - IRQn_Type xUSARTIrq; - const Pin *USARTNotREPin; - const Pin *USARTDEPin; - const Pin *xUSARTPins; - uint32_t xUSARTPinsCnt; - - -} xUSARTHWMappings[] = -{ -#if USART0_ENABLED == 1 - { - USART0, ID_USART0, USART0_IRQn, NULL, NULL, &xUSART0Pins[0], PIO_LISTSIZE( xUSART0Pins )}, -#endif -#if USART1_ENABLED == 1 - { - USART1, ID_USART1, USART1_IRQn, &xUSART1NotREPin, &xUSART1DEPin, &xUSART1Pins[0], PIO_LISTSIZE( xUSART1Pins )}, -#endif -}; - -static UCHAR ucUsedPort = USART_INVALID_PORT; - -void -vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable ) -{ - - if( xRxEnable ) - { - USART_SetReceiverEnabled( xUSARTHWMappings[ucUsedPort].pUsart, 1 ); - USART_EnableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IDR_RXRDY ); - } - else - { - USART_DisableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IDR_RXRDY ); - USART_SetReceiverEnabled( xUSARTHWMappings[ucUsedPort].pUsart, 0 ); - } - - if( xTxEnable ) - { - if( NULL != xUSARTHWMappings[ucUsedPort].USARTNotREPin ) - { - PIO_Set( xUSARTHWMappings[ucUsedPort].USARTNotREPin ); - } - if( NULL != xUSARTHWMappings[ucUsedPort].USARTDEPin ) - { - PIO_Set( xUSARTHWMappings[ucUsedPort].USARTDEPin ); - } - USART_SetTransmitterEnabled( xUSARTHWMappings[ucUsedPort].pUsart, 1 ); - USART_EnableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IER_TXRDY ); - USART_DisableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IER_TXEMPTY ); - } - else - { - USART_DisableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IDR_TXRDY ); - USART_EnableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IER_TXEMPTY ); - } -} - -BOOL -xMBPortSerialInit( UCHAR ucPORT, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity ) -{ - BOOL bStatus = FALSE; - uint32_t uiMode = US_MR_USART_MODE_NORMAL; - if( ( ucPORT <= USART_IDX_LAST ) ) - { - bStatus = TRUE; - switch ( eParity ) - { - case MB_PAR_NONE: - uiMode |= US_MR_PAR_NONE | US_MR_NBSTOP_2_BIT; - break; - case MB_PAR_ODD: - uiMode |= US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT; - break; - case MB_PAR_EVEN: - uiMode |= US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT; - break; - default: - bStatus = FALSE; - break; - } - - switch ( ucDataBits ) - { - case 8: - uiMode |= US_MR_CHRL_8_BITS; - break; - case 7: - uiMode |= US_MR_CHRL_7_BITS; - break; - default: - bStatus = FALSE; - } - - if( TRUE == bStatus ) - { - ucUsedPort = ucPORT; - - NVIC_DisableIRQ( xUSARTHWMappings[ucUsedPort].xUSARTIrq ); - - PIO_Configure( xUSARTHWMappings[ucUsedPort].xUSARTPins, xUSARTHWMappings[ucUsedPort].xUSARTPinsCnt ); - if( NULL != xUSARTHWMappings[ucUsedPort].USARTNotREPin ) - { - PIO_Configure( xUSARTHWMappings[ucUsedPort].USARTNotREPin, 1 ); - } - if( NULL != xUSARTHWMappings[ucUsedPort].USARTDEPin ) - { - PIO_Configure( xUSARTHWMappings[ucUsedPort].USARTDEPin, 1 ); - } - PMC_EnablePeripheral( xUSARTHWMappings[ucUsedPort].xUSARTID ); - USART_Configure( xUSARTHWMappings[ucUsedPort].pUsart, uiMode, ulBaudRate, BOARD_MCK ); - - NVIC_ClearPendingIRQ( xUSARTHWMappings[ucUsedPort].xUSARTIrq ); - NVIC_SetPriority( xUSARTHWMappings[ucUsedPort].xUSARTIrq, 0xF << 4 ); - NVIC_EnableIRQ( xUSARTHWMappings[ucUsedPort].xUSARTIrq ); - } - } - - return bStatus; -} - -void -vMBPortSerialClose( void ) -{ - if( USART_INVALID_PORT != ucUsedPort ) - { - NVIC_DisableIRQ( xUSARTHWMappings[ucUsedPort].xUSARTIrq ); - PMC_DisablePeripheral( xUSARTHWMappings[ucUsedPort].xUSARTID ); - if( NULL != xUSARTHWMappings[ucUsedPort].USARTNotREPin ) - { - PIO_Clear( xUSARTHWMappings[ucUsedPort].USARTDEPin ); - } - if( NULL != xUSARTHWMappings[ucUsedPort].USARTDEPin ) - { - PIO_Clear( xUSARTHWMappings[ucUsedPort].USARTNotREPin ); - } - ucUsedPort = USART_INVALID_PORT; - } -} - -BOOL -xMBPortSerialPutByte( CHAR ucByte ) -{ - USART1->US_THR = ucByte; - return TRUE; -} - -BOOL -xMBPortSerialGetByte( CHAR * pucByte ) -{ - *pucByte = USART1->US_RHR; - return TRUE; -} - -void -vUSARTHandler( void ) -{ - uint32_t uiCSR; - uint32_t uiIMR; - uiCSR = xUSARTHWMappings[ucUsedPort].pUsart->US_CSR; - uiIMR = xUSARTHWMappings[ucUsedPort].pUsart->US_IMR; - uint32_t uiCSRMasked = uiCSR & uiIMR; - if( uiCSRMasked & US_CSR_RXRDY ) - { - pxMBFrameCBByteReceived( ); - } - if( uiCSRMasked & US_CSR_TXRDY ) - { - pxMBFrameCBTransmitterEmpty( ); - } - if( uiCSRMasked & US_CSR_TXEMPTY ) - { - if( NULL != xUSARTHWMappings[ucUsedPort].USARTDEPin ) - { - PIO_Clear( xUSARTHWMappings[ucUsedPort].USARTDEPin ); - } - if( NULL != xUSARTHWMappings[ucUsedPort].USARTNotREPin ) - { - PIO_Clear( xUSARTHWMappings[ucUsedPort].USARTNotREPin ); - } - USART_DisableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IER_TXEMPTY ); - } -} - -#if USART1_ENABLED == 1 -void -USART1_IrqHandler( void ) -{ - vUSARTHandler( ); -} -#endif - -#if USART0_ENABLED == 1 -void -USART0_IrqHandler( void ) -{ - vUSARTHandler( ); -} -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/port/porttimer.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/port/porttimer.c deleted file mode 100644 index aa2393041..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S/port/porttimer.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * FreeModbus Libary: Atmel AT91SAM3S Demo Application - * Copyright (C) 2010 Christian Walter - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * IF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "port.h" -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ - - -#define MB_TIMER_DEBUG ( 0 ) -#define MB_TIMER_PRESCALER ( 128UL ) -#define MB_TIMER_TICKS ( BOARD_MCK / MB_TIMER_PRESCALER ) -#define MB_50US_TICKS ( 20000UL ) - -#define TCX ( TC0 ) -#define TCXIRQ ( TC0_IRQn ) -#define TCCHANNEL ( 0 ) -#define TCX_IRQHANDLER TC0_IrqHandler - -#define TC_CMRX_WAVE ( 0x1 << 15 ) -#define TC_CMRX_TCCLKS_TIMER_DIV4_CLOCK ( 0x3 << 0 ) -#define TC_CMRX_CPCSTOP ( 0x1 << 6 ) -#define TC_CMRX_WAVESEL_UP_RC ( 0x2 << 13 ) - -#define TC_IERX_CPCS ( 0x1 << 4 ) -#define TC_IERX_CPAS ( 0x1 << 2 ) -#define TC_SRX_CPAS ( 0x1 << 2 ) -#if MB_TIMER_DEBUG == 1 -#define TIMER_PIN { 1 << 6, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT } -#endif - -#ifndef SYSTICK_COUNTFLAG -/* missing in CMSIS */ -#define SYSTICK_COUNTFLAG ( 16 ) -#endif -/* ----------------------- Static variables ---------------------------------*/ -#if MB_TIMER_DEBUG == 1 -const static Pin xTimerDebugPins[] = { TIMER_PIN }; -#endif - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortTimersInit( USHORT usTim1Timerout50us ) -{ -#if MB_TIMER_DEBUG == 1 - PIO_Configure( xTimerDebugPins, PIO_LISTSIZE( xTimerDebugPins ) ); -#endif - NVIC_DisableIRQ( TCXIRQ ); - - PMC_EnablePeripheral( ID_TC0 ); - TC_Configure( TCX, 0, TC_CMRX_WAVE | TC_CMRX_TCCLKS_TIMER_DIV4_CLOCK | TC_CMRX_WAVESEL_UP_RC | TC_CMRX_CPCSTOP ); - TCX->TC_CHANNEL[TCCHANNEL].TC_RA = ( MB_TIMER_TICKS * usTim1Timerout50us ) / ( MB_50US_TICKS ); - TCX->TC_CHANNEL[TCCHANNEL].TC_RC = ( MB_TIMER_TICKS * usTim1Timerout50us ) / ( MB_50US_TICKS ); - - NVIC_ClearPendingIRQ( TCXIRQ ); - NVIC_SetPriority( TCXIRQ, 0xF << 4 ); - NVIC_EnableIRQ( TCXIRQ ); - - return TRUE; -} - -void -vMBPortTimerClose( void ) -{ - NVIC_DisableIRQ( TCXIRQ ); - PMC_DisablePeripheral( ID_TC0 ); -} - -void -vMBPortTimersEnable( ) -{ -#if MB_TIMER_DEBUG == 1 - PIO_Set( &xTimerDebugPins[0] ); -#endif - TCX->TC_CHANNEL[TCCHANNEL].TC_IER = TC_IERX_CPAS; - TC_Start( TCX, 0 ); -} - -void -vMBPortTimersDisable( ) -{ - TC_Stop( TCX, 0 ); -#if MB_TIMER_DEBUG == 1 - PIO_Clear( &xTimerDebugPins[0] ); -#endif -} - -void -vMBPortTimersDelay( USHORT usTimeOutMS ) -{ - - SysTick->CTRL = 0; - SysTick->LOAD = BOARD_MCK / 1000; - SysTick->VAL = 0; /* Clear COUNTFLAG */ - SysTick->CTRL = ( 1 << SYSTICK_CLKSOURCE) | ( 1<CTRL & ( 1 << SYSTICK_COUNTFLAG ) ) ); - SysTick->VAL = 0; - usTimeOutMS--; - } -} - -void -TCX_IRQHANDLER( void ) -{ - uint32_t xTCX_IMRX = TCX->TC_CHANNEL[TCCHANNEL].TC_IMR; - uint32_t xTCX_SRX = TCX->TC_CHANNEL[TCCHANNEL].TC_SR; - uint32_t uiSRMasked = xTCX_SRX & xTCX_IMRX; - - if( ( uiSRMasked & TC_SRX_CPAS ) > 0 ) - { -#if MB_TIMER_DEBUG == 1 - PIO_Clear( &xTimerDebugPins[0] ); -#endif - ( void )pxMBPortCBTimerExpired( ); - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/README.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/README.txt deleted file mode 100644 index f459c7004..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/README.txt +++ /dev/null @@ -1,68 +0,0 @@ - - FREEMODBUS 1.5 ATSAM3S EXAMPLE - ============================== - -REQUIREMENTS -============ - -This example contains a simple demo program for FreeMODBUS for the AT91SAM3S -Cortex M3 controllers on the SAM3S-EK [0] evaluation kit. It requires a wired -RS485 connection to a host processor and a MODBUS master software on the PC -side to be useful. Demo versions of MODBUS master stacks can be found in -[1], [2] and [3]. Commercial MODBUS stacks are available from [4]. - -INSTALLATION -============ -The SAM3S-EK evaluation board should be modified as following to enable RS485 -data transmission. - - - Place Jumpers JP11, JP10 and JP12 - - Place a solder drop accross R25 - -Warning: The RS485 shares data lines with USART1. It is therefore absolutely -necessary to set PA23 to a high level. - -SOURCE -====== - -TESTING -======= - -Start the MODBUS sample application and test if the input registers starting -at protocol address 1000 can be read. There are four registers values avai- -lable and the output should look like: - -Polling slave (Ctrl-C to stop) ... -[1000]: 6474 -[1001]: 0 -[1002]: 0 -[1003]: 0 -Polling slave (Ctrl-C to stop) ... -[1000]: -8831 -[1001]: 0 -[1002]: 0 -[1003]: 0 -Polling slave (Ctrl-C to stop) ... - -The simple testing utility used in the 'demo_rtu.bat' script can be found at -[3]. - -PROBLEMS -======== - -In case you can get no communication working make sure that the RS485 line is -biased correctly. The SAM3S-EK does not populate the RS485 bias resistors by -default and if you have a RS485 master which does not bias the lines either -you will get wrong characters. For this R24 and R30 on the bottom side of the -evaluation kit of the PCB should be populated. - -REFERENCES -========== - -[0] Atmel SAM3S-EK: http://www.atmel.com/dyn/products/tools_card_v2.asp?tool_id=4678 -[1] WinTech ModScan32: http://www.win-tech.com/html/modscan32.htm -[2] Modus Poll: http://www.modbustools.com/modbus_poll.asp -[3] FieldTalk Modpoll: http://www.focus-sw.com/fieldtalk/modpoll.html -[4] Embedded Solutions: http://www.embedded-solutions.at - -Version: $Id: README.txt,v 1.1 2010/06/06 13:07:19 wolti Exp $ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/AT91SAM3S4.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/AT91SAM3S4.h deleted file mode 100644 index a11e72a34..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/AT91SAM3S4.h +++ /dev/null @@ -1,7010 +0,0 @@ -/* ---------------------------------------------------------------------------- */ -/* Atmel Microcontroller Software Support */ -/* ---------------------------------------------------------------------------- */ -/* Copyright (c) 2009, Atmel Corporation */ -/* */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following condition is met: */ -/* */ -/* - Redistributions of source code must retain the above copyright notice, */ -/* this list of conditions and the disclaimer below. */ -/* */ -/* Atmel's name may not be used to endorse or promote products derived from */ -/* this software without specific prior written permission. */ -/* */ -/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ -/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ -/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ -/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ -/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ -/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ -/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ -/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ -/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* ---------------------------------------------------------------------------- */ -/* */ -/* File Name : AT91SAM3S.h */ -/* Object : AT91SAM3S definitions */ -/* Generated by : AT91 SW Application Group */ -/* Generated on : 2009-10-26 */ - -#ifndef AT91SAM3S_H -#define AT91SAM3S_H - -/** \addtogroup AT91SAM3S_definitions AT91SAM3S definitions - This file defines all structures and symbols for AT91SAM3S: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __ASSEMBLY__ -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *) value) -#define REG_ACCESS(type, address) (*(type*)address) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ***************************************************************************** */ -/* CMSIS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_cmsis CMSIS Definitions */ - -/*@{*/ - -/** - * \brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __MPU_PRESENT 0 /**< AT91SAM3S does not provide a MPU present or not */ -#define __NVIC_PRIO_BITS 4 /**< AT91SAM3S uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ -/****** AT91SAM3S specific Interrupt Numbers *****************************************/ - - SUPC_IRQn = 0, /**< 0 AT91SAM3S Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 AT91SAM3S Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 AT91SAM3S Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 AT91SAM3S Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 AT91SAM3S Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 AT91SAM3S Power Management Controller (PMC) */ - EFC_IRQn = 6, /**< 6 AT91SAM3S Enhanced Flash Controller (EFC) */ - UART0_IRQn = 8, /**< 8 AT91SAM3S UART 0 (UART0) */ - UART1_IRQn = 9, /**< 9 AT91SAM3S UART 1 (UART1) */ - SMC_IRQn = 10, /**< 10 AT91SAM3S Static Memory Controller (SMC) */ - PIOA_IRQn = 11, /**< 11 AT91SAM3S Parallel I/O Controller A (PIOA) */ - PIOB_IRQn = 12, /**< 12 AT91SAM3S Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 13, /**< 13 AT91SAM3S Parallel I/O Controller C (PIOC) */ - USART0_IRQn = 14, /**< 14 AT91SAM3S USART 0 (USART0) */ - USART1_IRQn = 15, /**< 15 AT91SAM3S USART 1 (USART1) */ - HSMCI_IRQn = 18, /**< 18 AT91SAM3S Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 19, /**< 19 AT91SAM3S Two Wire Interface 0 (TWI0) */ - TWI1_IRQn = 20, /**< 20 AT91SAM3S Two Wire Interface 1 (TWI1) */ - SPI_IRQn = 21, /**< 21 AT91SAM3S Serial Peripheral Interface (SPI) */ - SSC_IRQn = 22, /**< 22 AT91SAM3S Synchronous Serial Controler (SSC) */ - TC0_IRQn = 23, /**< 23 AT91SAM3S Timer/Counter 0 (TC0) */ - TC1_IRQn = 24, /**< 24 AT91SAM3S Timer/Counter 1 (TC1) */ - TC2_IRQn = 25, /**< 25 AT91SAM3S Timer/Counter 2 (TC2) */ - TC3_IRQn = 26, /**< 26 AT91SAM3S Timer/Counter 3 (TC3) */ - TC4_IRQn = 27, /**< 27 AT91SAM3S Timer/Counter 4 (TC4) */ - TC5_IRQn = 28, /**< 28 AT91SAM3S Timer/Counter 5 (TC5) */ - ADC_IRQn = 29, /**< 29 AT91SAM3S Analog To Digital Converter (ADC) */ - DACC_IRQn = 30, /**< 30 AT91SAM3S Digital To Analog Converter (DACC) */ - PWM_IRQn = 31, /**< 31 AT91SAM3S Pulse Width Modulation (PWM) */ - CRCCU_IRQn = 32, /**< 32 AT91SAM3S CRC Calculation Unit (CRCCU) */ - ACC_IRQn = 33, /**< 33 AT91SAM3S Analog Comparator (ACC) */ - UDP_IRQn = 34 /**< 34 AT91SAM3S USB Device Port (UDP) */ -} IRQn_Type; -/*@}*/ - -/* ***************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_api Peripheral Software API */ -/*@{*/ -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_ACC Analog Comparator Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Acc hardware registers */ -typedef struct { - WoReg ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ - RwReg ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ - RwReg Reserved1[7]; - WoReg ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ - WoReg ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ - RoReg ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ - RoReg ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved2[24]; - RwReg ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ - RwReg Reserved3[19]; - RwReg ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */ - RoReg ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */ -} Acc; -#endif /* __ASSEMBLY__ */ -/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ -#define ACC_CR_SWRST (0x1 << 0) /**< \brief (ACC_CR) SoftWare ReSeT */ -/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ -#define ACC_MR_SELPLUS (0x7 << 0) /**< \brief (ACC_MR) SELection for PLUS comparator input */ -#define ACC_MR_SELMINUS (0x7 << 4) /**< \brief (ACC_MR) SELection for MINUS comparator input */ -#define ACC_MR_ACEN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ -#define ACC_MR_ACEN_EN (0x1 << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ -#define ACC_MR_ACEN_DIS (0x0 << 8) /**< \brief (ACC_MR) Analog Comparator Disable */ -#define ACC_MR_EDGETYP (0x3 << 9) /**< \brief (ACC_MR) EDGE TYPe */ -#define ACC_MR_EDGETYP_RISING (0x0 << 9) /**< \brief (ACC_MR) EDGE TYPe ,RISING edge*/ -#define ACC_MR_EDGETYP_FALLING (0x1 << 9) /**< \brief (ACC_MR) EDGE TYPe,falling edge */ -#define ACC_MR_EDGETYP_ANY (0x2 << 9) /**< \brief (ACC_MR) EDGE TYPe,any edge */ -#define ACC_MR_INV (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ -#define ACC_MR_INV_EN (0x1 << 12) /**< \brief (ACC_MR) INVert comparator output */ -#define ACC_MR_INV_DIS (0x0 << 12) /**< \brief (ACC_MR) DIRECTLY */ -#define ACC_MR_SELFS (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_SELFS_CF (0x0 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_SELFS_OUTPUT (0x1 << 13) /**< \brief (ACC_MR) SELection of Fault Source */ -#define ACC_MR_FE (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ -#define ACC_MR_FE_EN (0x1 << 14) /**< \brief (ACC_MR) Fault Enable */ -#define ACC_MR_FE_DIS (0x0 << 14) /**< \brief (ACC_MR) Fault Enable */ -/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ -#define ACC_IER_CE (0x1 << 0) /**< \brief (ACC_IER) Comparison Edge */ -/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ -#define ACC_IDR_CE (0x1 << 0) /**< \brief (ACC_IDR) Comparison Edge */ -/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ -#define ACC_IMR_CE (0x1 << 0) /**< \brief (ACC_IMR) Comparison Edge */ -/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ -#define ACC_ISR_CE (0x1 << 0) /**< \brief (ACC_ISR) Comparison Edge */ -#define ACC_ISR_SCO (0x1 << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ -#define ACC_ISR_MASK (0x1 << 31) /**< \brief (ACC_ISR) */ -/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ -#define ACC_ACR_ISEL (0x1 << 0) /**< \brief (ACC_ACR) Current SELection */ -#define ACC_ACR_HYST (0x3 << 1) /**< \brief (ACC_ACR) HYSTeresis selection */ -/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */ -#define ACC_WPMR_WPEN (0x1 << 0) /**< \brief (ACC_WPMR) Write Protect Enable */ -#define ACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ACC_WPMR) Write Protect KEY */ -/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */ -#define ACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_ADC Analog-to-digital Converter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Adc hardware registers */ -typedef struct { - WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */ - RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */ - RwReg ADC_SEQ1R; /**< \brief (Adc Offset: 0x08) Channel Sequence 1Register */ - RwReg ADC_SEQ2R; /**< \brief (Adc Offset: 0x0C) Channel Sequence 2 Register */ - WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */ - WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */ - RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */ - RwReg Reserved1[1]; - RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */ - WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */ - WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */ - RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */ - RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved2[2]; - RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */ - RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */ - RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */ - RwReg ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */ - RwReg ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */ - RoReg ADC_CDR0; /**< \brief (Adc Offset: 0x50) Channel Data Register 0 */ - RoReg ADC_CDR1; /**< \brief (Adc Offset: 0x54) Channel Data Register 1 */ - RoReg ADC_CDR2; /**< \brief (Adc Offset: 0x58) Channel Data Register 2 */ - RoReg ADC_CDR3; /**< \brief (Adc Offset: 0x5C) Channel Data Register 3 */ - RoReg ADC_CDR4; /**< \brief (Adc Offset: 0x60) Channel Data Register 4 */ - RoReg ADC_CDR5; /**< \brief (Adc Offset: 0x64) Channel Data Register 5 */ - RoReg ADC_CDR6; /**< \brief (Adc Offset: 0x68) Channel Data Register 6 */ - RoReg ADC_CDR7; /**< \brief (Adc Offset: 0x6C) Channel Data Register 7 */ - RoReg ADC_CDR8; /**< \brief (Adc Offset: 0x70) Channel Data Register 8 */ - RoReg ADC_CDR9; /**< \brief (Adc Offset: 0x74) Channel Data Register 9 */ - RoReg ADC_CDR10; /**< \brief (Adc Offset: 0x78) Channel Data Register 10 */ - RoReg ADC_CDR11; /**< \brief (Adc Offset: 0x7C) Channel Data Register 11 */ - RoReg ADC_CDR12; /**< \brief (Adc Offset: 0x80) Channel Data Register 12 */ - RoReg ADC_CDR13; /**< \brief (Adc Offset: 0x84) Channel Data Register 13 */ - RoReg ADC_CDR14; /**< \brief (Adc Offset: 0x88) Channel Data Register 14 */ - RoReg ADC_CDR15; /**< \brief (Adc Offset: 0x8C) Channel Data Register 15 */ - RwReg Reserved3[1]; - RwReg ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */ - RwReg Reserved4[19]; - RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */ - RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved5[5]; - RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */ - RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */ - RwReg ADC_TPR; /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */ - RwReg ADC_TCR; /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */ - RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */ - RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */ - RwReg ADC_TNPR; /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */ - RwReg ADC_TNCR; /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */ - WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */ - RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */ -} Adc; -#endif /* __ASSEMBLY__ */ -/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ -#define ADC_CR_SWRST (0x1 << 0) /**< \brief (ADC_CR) Software Reset */ -#define ADC_CR_START (0x1 << 1) /**< \brief (ADC_CR) Start Conversion */ -/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ -#define ADC_MR_TRGEN (0x1 << 0) /**< \brief (ADC_MR) Trigger Enable */ -#define ADC_MR_TRGEN_DIS (0x0 << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software.*/ -#define ADC_MR_TRGEN_EN (0x1) /**< (ADC) Hardware trigger selected by TRGSEL field is enabled.*/ -#define ADC_MR_TRGSEL (0x7 << 1) /**< \brief (ADC_MR) Trigger Selection */ -#define ADC_MR_TRGSEL_EXT (0x0 << 1) /**< \brief (ADC_MR) Selected TRGSEL = External Trigger*/ -#define ADC_MR_TRGSEL_TIOA0 (0x1 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO0*/ -#define ADC_MR_TRGSEL_TIOA1 (0x2 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO1*/ -#define ADC_MR_TRGSEL_TIOA2 (0x3 << 1) /**< \brief (ADC_MR) Selected TRGSEL = TIAO2*/ -#define ADC_MR_TRGSEL_PWM0_TRIG (0x4 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM trigger*/ -#define ADC_MR_TRGSEL_PWM1_TRIG (0x5 << 1) /**< \brief (ADC_MR) Selected TRGSEL = PWM Trigger*/ -#define ADC_MR_TRGSEL_RESERVED (0x6 << 1) /**< \brief (ADC_MR) Selected TRGSEL = Reserved*/ -#define ADC_MR_LOWRES (0x1 << 4) /**< \brief (ADC_MR) Resolution */ -#define ADC_MR_LOWRES_12_BIT (0x0 << 4) /**< \brief (ADC_MR) 12-bit resolution*/ -#define ADC_MR_LOWRES_10_BIT (0x1 << 4) /**< \brief (ADC_MR) 10-bit resolution*/ -#define ADC_MR_SLEEP (0x1 << 5) /**< \brief (ADC_MR) Sleep Mode */ -#define ADC_MR_SLEEP_NORMAL (0x0 << 5) /**< \brief (ADC12B) Normal Mode*/ -#define ADC_MR_FWUP (0x1 << 6) /**< \brief (ADC_MR) Fast Wake Up */ -#define ADC_MR_FREERUN (0x1 << 7) /**< \brief (ADC_MR) Free Run Mode */ -#define ADC_MR_PRESCAL (0xff << 8) /**< \brief (ADC_MR) Prescaler Rate Selection */ -#define ADC_MR_STARTUP (0xf << 16) /**< \brief (ADC_MR) Start Up Time */ -#define ADC_MR_SETTLING (0x3 << 20) /**< \brief (ADC_MR) Analog Settling Time */ -#define ADC_MR_ANACH (0x1 << 23) /**< \brief (ADC_MR) Analog Change */ -#define ADC_MR_TRACKTIM (0xf << 24) /**< \brief (ADC_MR) Tracking Time */ -#define ADC_MR_TRANSFER (0x3 << 28) /**< \brief (ADC_MR) */ -#define ADC_MR_USEQ (0x1 << 31) /**< \brief (ADC_MR) User Sequence Enable */ -/* -------- ADC_SEQ1R : (ADC Offset: 0x08) Channel Sequence 1Register -------- */ -#define ADC_SEQ1R_USCH1 (0x7 << 0) /**< \brief (ADC_SEQ1R) User Sequence Number 1 */ -#define ADC_SEQ1R_USCH2 (0x7 << 4) /**< \brief (ADC_SEQ1R) User Sequence Number 2 */ -#define ADC_SEQ1R_USCH3 (0x7 << 8) /**< \brief (ADC_SEQ1R) User Sequence Number 3 */ -#define ADC_SEQ1R_USCH4 (0x7 << 12) /**< \brief (ADC_SEQ1R) User Sequence Number 4 */ -#define ADC_SEQ1R_USCH5 (0x7 << 16) /**< \brief (ADC_SEQ1R) User Sequence Number 5 */ -#define ADC_SEQ1R_USCH6 (0x7 << 20) /**< \brief (ADC_SEQ1R) User Sequence Number 6 */ -#define ADC_SEQ1R_USCH7 (0x7 << 24) /**< \brief (ADC_SEQ1R) User Sequence Number 7 */ -#define ADC_SEQ1R_USCH8 (0x7 << 28) /**< \brief (ADC_SEQ1R) User Sequence Number 8 */ -/* -------- ADC_SEQ2R : (ADC Offset: 0x0C) Channel Sequence 2 Register -------- */ -#define ADC_SEQ2R_USCH9 (0x7 << 0) /**< \brief (ADC_SEQ2R) User Sequence Number 9 */ -#define ADC_SEQ2R_USCH10 (0x7 << 4) /**< \brief (ADC_SEQ2R) User Sequence Number 10 */ -#define ADC_SEQ2R_USCH11 (0x7 << 8) /**< \brief (ADC_SEQ2R) User Sequence Number 11 */ -#define ADC_SEQ2R_USCH12 (0x7 << 12) /**< \brief (ADC_SEQ2R) User Sequence Number 12 */ -#define ADC_SEQ2R_USCH13 (0x7 << 16) /**< \brief (ADC_SEQ2R) User Sequence Number 13 */ -#define ADC_SEQ2R_USCH14 (0x7 << 20) /**< \brief (ADC_SEQ2R) User Sequence Number 14 */ -#define ADC_SEQ2R_USCH15 (0x7 << 24) /**< \brief (ADC_SEQ2R) User Sequence Number 15 */ -#define ADC_SEQ2R_USCH16 (0x7 << 28) /**< \brief (ADC_SEQ2R) User Sequence Number 16 */ -/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ -#define ADC_CHER_CH0 (0x1 << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ -#define ADC_CHER_CH1 (0x1 << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ -#define ADC_CHER_CH2 (0x1 << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ -#define ADC_CHER_CH3 (0x1 << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ -#define ADC_CHER_CH4 (0x1 << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ -#define ADC_CHER_CH5 (0x1 << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ -#define ADC_CHER_CH6 (0x1 << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ -#define ADC_CHER_CH7 (0x1 << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ -#define ADC_CHER_CH8 (0x1 << 8) /**< \brief (ADC_CHER) Channel 8 Enable */ -#define ADC_CHER_CH9 (0x1 << 9) /**< \brief (ADC_CHER) Channel 9 Enable */ -#define ADC_CHER_CH10 (0x1 << 10) /**< \brief (ADC_CHER) Channel 10 Enable */ -#define ADC_CHER_CH11 (0x1 << 11) /**< \brief (ADC_CHER) Channel 11 Enable */ -#define ADC_CHER_CH12 (0x1 << 12) /**< \brief (ADC_CHER) Channel 12 Enable */ -#define ADC_CHER_CH13 (0x1 << 13) /**< \brief (ADC_CHER) Channel 13 Enable */ -#define ADC_CHER_CH14 (0x1 << 14) /**< \brief (ADC_CHER) Channel 14 Enable */ -#define ADC_CHER_CH15 (0x1 << 15) /**< \brief (ADC_CHER) Channel 15 Enable */ -/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ -#define ADC_CHDR_CH0 (0x1 << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */ -#define ADC_CHDR_CH1 (0x1 << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */ -#define ADC_CHDR_CH2 (0x1 << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */ -#define ADC_CHDR_CH3 (0x1 << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */ -#define ADC_CHDR_CH4 (0x1 << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */ -#define ADC_CHDR_CH5 (0x1 << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */ -#define ADC_CHDR_CH6 (0x1 << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */ -#define ADC_CHDR_CH7 (0x1 << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */ -#define ADC_CHDR_CH8 (0x1 << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */ -#define ADC_CHDR_CH9 (0x1 << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */ -#define ADC_CHDR_CH10 (0x1 << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */ -#define ADC_CHDR_CH11 (0x1 << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */ -#define ADC_CHDR_CH12 (0x1 << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */ -#define ADC_CHDR_CH13 (0x1 << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */ -#define ADC_CHDR_CH14 (0x1 << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */ -#define ADC_CHDR_CH15 (0x1 << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */ -/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ -#define ADC_CHSR_CH0 (0x1 << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ -#define ADC_CHSR_CH1 (0x1 << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ -#define ADC_CHSR_CH2 (0x1 << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ -#define ADC_CHSR_CH3 (0x1 << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ -#define ADC_CHSR_CH4 (0x1 << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ -#define ADC_CHSR_CH5 (0x1 << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ -#define ADC_CHSR_CH6 (0x1 << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ -#define ADC_CHSR_CH7 (0x1 << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ -#define ADC_CHSR_CH8 (0x1 << 8) /**< \brief (ADC_CHSR) Channel 8 Status */ -#define ADC_CHSR_CH9 (0x1 << 9) /**< \brief (ADC_CHSR) Channel 9 Status */ -#define ADC_CHSR_CH10 (0x1 << 10) /**< \brief (ADC_CHSR) Channel 10 Status */ -#define ADC_CHSR_CH11 (0x1 << 11) /**< \brief (ADC_CHSR) Channel 11 Status */ -#define ADC_CHSR_CH12 (0x1 << 12) /**< \brief (ADC_CHSR) Channel 12 Status */ -#define ADC_CHSR_CH13 (0x1 << 13) /**< \brief (ADC_CHSR) Channel 13 Status */ -#define ADC_CHSR_CH14 (0x1 << 14) /**< \brief (ADC_CHSR) Channel 14 Status */ -#define ADC_CHSR_CH15 (0x1 << 15) /**< \brief (ADC_CHSR) Channel 15 Status */ -/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ -#define ADC_LCDR_LDATA (0xfff << 0) /**< \brief (ADC_LCDR) Last Data Converted */ -#define ADC_LCDR_CHNB (0xf << 12) /**< \brief (ADC_LCDR) Channel Number */ -/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ -#define ADC_IER_EOC0 (0x1 << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ -#define ADC_IER_EOC1 (0x1 << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ -#define ADC_IER_EOC2 (0x1 << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ -#define ADC_IER_EOC3 (0x1 << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ -#define ADC_IER_EOC4 (0x1 << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ -#define ADC_IER_EOC5 (0x1 << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ -#define ADC_IER_EOC6 (0x1 << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ -#define ADC_IER_EOC7 (0x1 << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ -#define ADC_IER_EOC8 (0x1 << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */ -#define ADC_IER_EOC9 (0x1 << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */ -#define ADC_IER_EOC10 (0x1 << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */ -#define ADC_IER_EOC11 (0x1 << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */ -#define ADC_IER_EOC12 (0x1 << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */ -#define ADC_IER_EOC13 (0x1 << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */ -#define ADC_IER_EOC14 (0x1 << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */ -#define ADC_IER_EOC15 (0x1 << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */ -#define ADC_IER_DRDY (0x1 << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ -#define ADC_IER_GOVRE (0x1 << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ -#define ADC_IER_COMPE (0x1 << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */ -#define ADC_IER_ENDRX (0x1 << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ -#define ADC_IER_RXBUFF (0x1 << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ -/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ -#define ADC_IDR_EOC0 (0x1 << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ -#define ADC_IDR_EOC1 (0x1 << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ -#define ADC_IDR_EOC2 (0x1 << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ -#define ADC_IDR_EOC3 (0x1 << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ -#define ADC_IDR_EOC4 (0x1 << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ -#define ADC_IDR_EOC5 (0x1 << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ -#define ADC_IDR_EOC6 (0x1 << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ -#define ADC_IDR_EOC7 (0x1 << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ -#define ADC_IDR_EOC8 (0x1 << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */ -#define ADC_IDR_EOC9 (0x1 << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */ -#define ADC_IDR_EOC10 (0x1 << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */ -#define ADC_IDR_EOC11 (0x1 << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */ -#define ADC_IDR_EOC12 (0x1 << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */ -#define ADC_IDR_EOC13 (0x1 << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */ -#define ADC_IDR_EOC14 (0x1 << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */ -#define ADC_IDR_EOC15 (0x1 << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */ -#define ADC_IDR_DRDY (0x1 << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ -#define ADC_IDR_GOVRE (0x1 << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ -#define ADC_IDR_COMPE (0x1 << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */ -#define ADC_IDR_ENDRX (0x1 << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ -#define ADC_IDR_RXBUFF (0x1 << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ -/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ -#define ADC_IMR_EOC0 (0x1 << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ -#define ADC_IMR_EOC1 (0x1 << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ -#define ADC_IMR_EOC2 (0x1 << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ -#define ADC_IMR_EOC3 (0x1 << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ -#define ADC_IMR_EOC4 (0x1 << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ -#define ADC_IMR_EOC5 (0x1 << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ -#define ADC_IMR_EOC6 (0x1 << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ -#define ADC_IMR_EOC7 (0x1 << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ -#define ADC_IMR_EOC8 (0x1 << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */ -#define ADC_IMR_EOC9 (0x1 << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */ -#define ADC_IMR_EOC10 (0x1 << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */ -#define ADC_IMR_EOC11 (0x1 << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */ -#define ADC_IMR_EOC12 (0x1 << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */ -#define ADC_IMR_EOC13 (0x1 << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */ -#define ADC_IMR_EOC14 (0x1 << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */ -#define ADC_IMR_EOC15 (0x1 << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */ -#define ADC_IMR_DRDY (0x1 << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ -#define ADC_IMR_GOVRE (0x1 << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ -#define ADC_IMR_COMPE (0x1 << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */ -#define ADC_IMR_ENDRX (0x1 << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ -#define ADC_IMR_RXBUFF (0x1 << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ -/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */ -#define ADC_ISR_EOC0 (0x1 << 0) /**< \brief (ADC_ISR) End of Conversion 0 */ -#define ADC_ISR_EOC1 (0x1 << 1) /**< \brief (ADC_ISR) End of Conversion 1 */ -#define ADC_ISR_EOC2 (0x1 << 2) /**< \brief (ADC_ISR) End of Conversion 2 */ -#define ADC_ISR_EOC3 (0x1 << 3) /**< \brief (ADC_ISR) End of Conversion 3 */ -#define ADC_ISR_EOC4 (0x1 << 4) /**< \brief (ADC_ISR) End of Conversion 4 */ -#define ADC_ISR_EOC5 (0x1 << 5) /**< \brief (ADC_ISR) End of Conversion 5 */ -#define ADC_ISR_EOC6 (0x1 << 6) /**< \brief (ADC_ISR) End of Conversion 6 */ -#define ADC_ISR_EOC7 (0x1 << 7) /**< \brief (ADC_ISR) End of Conversion 7 */ -#define ADC_ISR_EOC8 (0x1 << 8) /**< \brief (ADC_ISR) End of Conversion 8 */ -#define ADC_ISR_EOC9 (0x1 << 9) /**< \brief (ADC_ISR) End of Conversion 9 */ -#define ADC_ISR_EOC10 (0x1 << 10) /**< \brief (ADC_ISR) End of Conversion 10 */ -#define ADC_ISR_EOC11 (0x1 << 11) /**< \brief (ADC_ISR) End of Conversion 11 */ -#define ADC_ISR_EOC12 (0x1 << 12) /**< \brief (ADC_ISR) End of Conversion 12 */ -#define ADC_ISR_EOC13 (0x1 << 13) /**< \brief (ADC_ISR) End of Conversion 13 */ -#define ADC_ISR_EOC14 (0x1 << 14) /**< \brief (ADC_ISR) End of Conversion 14 */ -#define ADC_ISR_EOC15 (0x1 << 15) /**< \brief (ADC_ISR) End of Conversion 15 */ -#define ADC_ISR_DRDY (0x1 << 24) /**< \brief (ADC_ISR) Data Ready */ -#define ADC_ISR_GOVRE (0x1 << 25) /**< \brief (ADC_ISR) General Overrun Error */ -#define ADC_ISR_COMPE (0x1 << 26) /**< \brief (ADC_ISR) Comparison Error */ -#define ADC_ISR_ENDRX (0x1 << 27) /**< \brief (ADC_ISR) End of RX Buffer */ -#define ADC_ISR_RXBUFF (0x1 << 28) /**< \brief (ADC_ISR) RX Buffer Full */ -/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */ -#define ADC_OVER_OVRE0 (0x1 << 0) /**< \brief (ADC_OVER) Overrun Error 0 */ -#define ADC_OVER_OVRE1 (0x1 << 1) /**< \brief (ADC_OVER) Overrun Error 1 */ -#define ADC_OVER_OVRE2 (0x1 << 2) /**< \brief (ADC_OVER) Overrun Error 2 */ -#define ADC_OVER_OVRE3 (0x1 << 3) /**< \brief (ADC_OVER) Overrun Error 3 */ -#define ADC_OVER_OVRE4 (0x1 << 4) /**< \brief (ADC_OVER) Overrun Error 4 */ -#define ADC_OVER_OVRE5 (0x1 << 5) /**< \brief (ADC_OVER) Overrun Error 5 */ -#define ADC_OVER_OVRE6 (0x1 << 6) /**< \brief (ADC_OVER) Overrun Error 6 */ -#define ADC_OVER_OVRE7 (0x1 << 7) /**< \brief (ADC_OVER) Overrun Error 7 */ -#define ADC_OVER_OVRE8 (0x1 << 8) /**< \brief (ADC_OVER) Overrun Error 8 */ -#define ADC_OVER_OVRE9 (0x1 << 9) /**< \brief (ADC_OVER) Overrun Error 9 */ -#define ADC_OVER_OVRE10 (0x1 << 10) /**< \brief (ADC_OVER) Overrun Error 10 */ -#define ADC_OVER_OVRE11 (0x1 << 11) /**< \brief (ADC_OVER) Overrun Error 11 */ -#define ADC_OVER_OVRE12 (0x1 << 12) /**< \brief (ADC_OVER) Overrun Error 12 */ -#define ADC_OVER_OVRE13 (0x1 << 13) /**< \brief (ADC_OVER) Overrun Error 13 */ -#define ADC_OVER_OVRE14 (0x1 << 14) /**< \brief (ADC_OVER) Overrun Error 14 */ -#define ADC_OVER_OVRE15 (0x1 << 15) /**< \brief (ADC_OVER) Overrun Error 15 */ -/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */ -#define ADC_EMR_CMPMODE (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode */ -#define ADC_EMR_CMPMODE_LOW (0x0 << 0) /**< \brief (ADC_EMR) Comparison Mode,lower than low threshold */ -#define ADC_EMR_CMPMODE_HIGH (0x1 << 0) /**< \brief (ADC_EMR) Comparison Mode,higher than high threshold */ -#define ADC_EMR_CMPMODE_IN (0x2 << 0) /**< \brief (ADC_EMR) Comparison Mode, in the comparison window */ -#define ADC_EMR_CMPMODE_OUT (0x3 << 0) /**< \brief (ADC_EMR) Comparison Mode, out of the comparison window */ -#define ADC_EMR_CMPSEL (0xf << 4) /**< \brief (ADC_EMR) Comparison Selected Channel */ -#define ADC_EMR_CMPALL (0x1 << 9) /**< \brief (ADC_EMR) Compare All Channels */ -#define ADC_EMR_TAG (0x1 << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */ -/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */ -#define ADC_CWR_LOWTHRES (0xfff << 0) /**< \brief (ADC_CWR) Low Threshold */ -#define ADC_CWR_HIGHTHRES (0xfff << 16) /**< \brief (ADC_CWR) High Threshold */ -/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */ -#define ADC_CGR_GAIN0 (0x3 << 0) /**< \brief (ADC_CGR) Gain for channel 0 */ -#define ADC_CGR_GAIN1 (0x3 << 2) /**< \brief (ADC_CGR) Gain for channel 1 */ -#define ADC_CGR_GAIN2 (0x3 << 4) /**< \brief (ADC_CGR) Gain for channel 2 */ -#define ADC_CGR_GAIN3 (0x3 << 6) /**< \brief (ADC_CGR) Gain for channel 3 */ -#define ADC_CGR_GAIN4 (0x3 << 8) /**< \brief (ADC_CGR) Gain for channel 4 */ -#define ADC_CGR_GAIN5 (0x3 << 10) /**< \brief (ADC_CGR) Gain for channel 5 */ -#define ADC_CGR_GAIN6 (0x3 << 12) /**< \brief (ADC_CGR) Gain for channel 6 */ -#define ADC_CGR_GAIN7 (0x3 << 14) /**< \brief (ADC_CGR) Gain for channel 7 */ -#define ADC_CGR_GAIN8 (0x3 << 16) /**< \brief (ADC_CGR) Gain for channel 8 */ -#define ADC_CGR_GAIN9 (0x3 << 18) /**< \brief (ADC_CGR) Gain for channel 9 */ -#define ADC_CGR_GAIN10 (0x3 << 20) /**< \brief (ADC_CGR) Gain for channel 10 */ -#define ADC_CGR_GAIN11 (0x3 << 22) /**< \brief (ADC_CGR) Gain for channel 11 */ -#define ADC_CGR_GAIN12 (0x3 << 24) /**< \brief (ADC_CGR) Gain for channel 12 */ -#define ADC_CGR_GAIN13 (0x3 << 26) /**< \brief (ADC_CGR) Gain for channel 13 */ -#define ADC_CGR_GAIN14 (0x3 << 28) /**< \brief (ADC_CGR) Gain for channel 14 */ -#define ADC_CGR_GAIN15 (0x3 << 30) /**< \brief (ADC_CGR) Gain for channel 15 */ -/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */ -#define ADC_COR_OFF0 (0x1 << 0) /**< \brief (ADC_COR) Offset for channel 0 */ -#define ADC_COR_OFF1 (0x1 << 1) /**< \brief (ADC_COR) Offset for channel 1 */ -#define ADC_COR_OFF2 (0x1 << 2) /**< \brief (ADC_COR) Offset for channel 2 */ -#define ADC_COR_OFF3 (0x1 << 3) /**< \brief (ADC_COR) Offset for channel 3 */ -#define ADC_COR_OFF4 (0x1 << 4) /**< \brief (ADC_COR) Offset for channel 4 */ -#define ADC_COR_OFF5 (0x1 << 5) /**< \brief (ADC_COR) Offset for channel 5 */ -#define ADC_COR_OFF6 (0x1 << 6) /**< \brief (ADC_COR) Offset for channel 6 */ -#define ADC_COR_OFF7 (0x1 << 7) /**< \brief (ADC_COR) Offset for channel 7 */ -#define ADC_COR_OFF8 (0x1 << 8) /**< \brief (ADC_COR) Offset for channel 8 */ -#define ADC_COR_OFF9 (0x1 << 9) /**< \brief (ADC_COR) Offset for channel 9 */ -#define ADC_COR_OFF10 (0x1 << 10) /**< \brief (ADC_COR) Offset for channel 10 */ -#define ADC_COR_OFF11 (0x1 << 11) /**< \brief (ADC_COR) Offset for channel 11 */ -#define ADC_COR_OFF12 (0x1 << 12) /**< \brief (ADC_COR) Offset for channel 12 */ -#define ADC_COR_OFF13 (0x1 << 13) /**< \brief (ADC_COR) Offset for channel 13 */ -#define ADC_COR_OFF14 (0x1 << 14) /**< \brief (ADC_COR) Offset for channel 14 */ -#define ADC_COR_OFF15 (0x1 << 15) /**< \brief (ADC_COR) Offset for channel 15 */ -#define ADC_COR_DIFF0 (0x1 << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */ -#define ADC_COR_DIFF1 (0x1 << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */ -#define ADC_COR_DIFF2 (0x1 << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */ -#define ADC_COR_DIFF3 (0x1 << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */ -#define ADC_COR_DIFF4 (0x1 << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */ -#define ADC_COR_DIFF5 (0x1 << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */ -#define ADC_COR_DIFF6 (0x1 << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */ -#define ADC_COR_DIFF7 (0x1 << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */ -#define ADC_COR_DIFF8 (0x1 << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */ -#define ADC_COR_DIFF9 (0x1 << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */ -#define ADC_COR_DIFF10 (0x1 << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */ -#define ADC_COR_DIFF11 (0x1 << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */ -#define ADC_COR_DIFF12 (0x1 << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */ -#define ADC_COR_DIFF13 (0x1 << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */ -#define ADC_COR_DIFF14 (0x1 << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */ -#define ADC_COR_DIFF15 (0x1 << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */ -/* -------- ADC_CDR0 : (ADC Offset: 0x50) Channel Data Register 0 -------- */ -#define ADC_CDR0_DATA (0x3ff << 0) /**< \brief (ADC_CDR0) Converted Data */ -/* -------- ADC_CDR1 : (ADC Offset: 0x54) Channel Data Register 1 -------- */ -#define ADC_CDR1_DATA (0x3ff << 0) /**< \brief (ADC_CDR1) Converted Data */ -/* -------- ADC_CDR2 : (ADC Offset: 0x58) Channel Data Register 2 -------- */ -#define ADC_CDR2_DATA (0x3ff << 0) /**< \brief (ADC_CDR2) Converted Data */ -/* -------- ADC_CDR3 : (ADC Offset: 0x5C) Channel Data Register 3 -------- */ -#define ADC_CDR3_DATA (0x3ff << 0) /**< \brief (ADC_CDR3) Converted Data */ -/* -------- ADC_CDR4 : (ADC Offset: 0x60) Channel Data Register 4 -------- */ -#define ADC_CDR4_DATA (0x3ff << 0) /**< \brief (ADC_CDR4) Converted Data */ -/* -------- ADC_CDR5 : (ADC Offset: 0x64) Channel Data Register 5 -------- */ -#define ADC_CDR5_DATA (0x3ff << 0) /**< \brief (ADC_CDR5) Converted Data */ -/* -------- ADC_CDR6 : (ADC Offset: 0x68) Channel Data Register 6 -------- */ -#define ADC_CDR6_DATA (0x3ff << 0) /**< \brief (ADC_CDR6) Converted Data */ -/* -------- ADC_CDR15 : (ADC Offset: 0x6C) Channel Data Register 15 -------- */ -#define ADC_CDR15_DATA (0x3ff << 0) /**< \brief (ADC_CDR15) Converted Data */ -/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */ -#define ADC_ACR_TSON (0x1 << 4) /**< \brief (ADC_ACR) Temperature Sensor On */ -#define ADC_ACR_IBCTL (0x3 << 8) /**< \brief (ADC_ACR) ADC Bias Current Control */ -/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */ -#define ADC_WPMR_WPEN (0x1 << 0) /**< \brief (ADC_WPMR) Write Protect Enable */ -#define ADC_WPMR_WPKEY (0xffffff << 8) /**< \brief (ADC_WPMR) Write Protect KEY */ -/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */ -#define ADC_WPSR_WPVS (0x1 << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */ -#define ADC_WPSR_WPVSRC (0xffff << 8) /**< \brief (ADC_WPSR) Write Protect Violation Source */ -/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ -#define ADC_RPR_RXPTR (0xffffffff << 0) /**< \brief (ADC_RPR) Receive Pointer Register */ -/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */ -#define ADC_RCR_RXCTR (0xffff << 0) /**< \brief (ADC_RCR) Receive Counter Register */ -/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */ -#define ADC_TPR_TXPTR (0xffffffff << 0) /**< \brief (ADC_TPR) Transmit Counter Register */ -/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */ -#define ADC_TCR_TXCTR (0xffff << 0) /**< \brief (ADC_TCR) Transmit Counter Register */ -/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */ -#define ADC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (ADC_RNPR) Receive Next Pointer */ -/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */ -#define ADC_RNCR_RXNCTR (0xffff << 0) /**< \brief (ADC_RNCR) Receive Next Counter */ -/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define ADC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (ADC_TNPR) Transmit Next Pointer */ -/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define ADC_TNCR_TXNCTR (0xffff << 0) /**< \brief (ADC_TNCR) Transmit Counter Next */ -/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */ -#define ADC_PTCR_RXTEN (0x1 << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ -#define ADC_PTCR_RXTDIS (0x1 << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ -#define ADC_PTCR_TXTEN (0x1 << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ -#define ADC_PTCR_TXTDIS (0x1 << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ -/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */ -#define ADC_PTSR_RXTEN (0x1 << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ -#define ADC_PTSR_TXTEN (0x1 << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Chip Identifier */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_CHIPID Chip Identifier */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Chipid hardware registers */ -typedef struct { - RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ - RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ -} Chipid; -#endif /* __ASSEMBLY__ */ -/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ -#define CHIPID_CIDR_VERSION (0x1f << 0) /**< \brief (CHIPID_CIDR) Version of the Device */ -#define CHIPID_CIDR_EPROC (0x7 << 5) /**< \brief (CHIPID_CIDR) Embedded Processor */ -#define CHIPID_CIDR_NVPSIZ (0xf << 8) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ -#define CHIPID_CIDR_NVPSIZ2 (0xf << 12) /**< \brief (CHIPID_CIDR) */ -#define CHIPID_CIDR_SRAMSIZ (0xf << 16) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ -#define CHIPID_CIDR_ARCH (0xff << 20) /**< \brief (CHIPID_CIDR) Architecture Identifier */ -#define CHIPID_CIDR_NVPTYP (0x7 << 28) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ -#define CHIPID_CIDR_EXT (0x1 << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ -/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ -#define CHIPID_EXID_EXID (0xffffffff << 0) /**< \brief (CHIPID_EXID) Chip ID Extension */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_CRCCU Cyclic Redundancy Check Calculation Unit */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Crccu hardware registers */ -typedef struct { - RwReg CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */ - RwReg Reserved1[1]; - WoReg CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */ - WoReg CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */ - RoReg CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */ - WoReg CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */ - WoReg CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */ - RoReg CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */ - RoReg CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */ - RwReg Reserved2[4]; - WoReg CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */ - RwReg CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */ - RoReg CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */ - WoReg CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */ - WoReg CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */ - RoReg CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */ - RoReg CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */ -} Crccu; -#endif /* __ASSEMBLY__ */ -/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */ -#define CRCCU_DSCR_DSCR (0x7fffff << 9) /**< \brief (CRCCU_DSCR) Descriptor Base Address */ -/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */ -#define CRCCU_DMA_EN_DMAEN (0x1 << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */ -/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */ -#define CRCCU_DMA_DIS_DMADIS (0x1 << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */ -/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */ -#define CRCCU_DMA_SR_DMASR (0x1 << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */ -/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */ -#define CRCCU_DMA_IER_DMAIER (0x1 << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */ -/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */ -#define CRCCU_DMA_IDR_DMAIDR (0x1 << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */ -/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */ -#define CRCCU_DMA_IMR_DMAIMR (0x1 << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */ -/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */ -#define CRCCU_DMA_ISR_DMAISR (0x1 << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */ -/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */ -#define CRCCU_CR_RESET (0x1 << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */ -/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */ -#define CRCCU_MR_ENABLE (0x1 << 0) /**< \brief (CRCCU_MR) CRC Enable */ -#define CRCCU_MR_COMPARE (0x1 << 1) /**< \brief (CRCCU_MR) CRC Compare */ -#define CRCCU_MR_PTYPE (0x3 << 2) /**< \brief (CRCCU_MR) Primitive Polynomial */ -#define CRCCU_MR_PTYPE_CCIT8023 (0x0 << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */ -#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1 << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */ -#define CRCCU_MR_PTYPE_CCIT16 (0x2 << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */ -#define CRCCU_MR_DIVIDER (0xf << 4) /**< \brief (CRCCU_MR) Request Divider */ -/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */ -#define CRCCU_SR_CRC (0xffffffff << 0) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */ -/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */ -#define CRCCU_IER_ERRIER (0x1 << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */ -/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */ -#define CRCCU_IDR_ERRIDR (0x1 << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */ -/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */ -#define CRCCU_IMR_ERRIMR (0x1 << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */ -/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */ -#define CRCCU_ISR_ERRISR (0x1 << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_DACC Digital-to-Analog Converter Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Dacc hardware registers */ -typedef struct { - WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ - RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ - RwReg Reserved1[2]; - WoReg DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ - WoReg DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ - RoReg DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ - RwReg Reserved2[1]; - WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */ - WoReg DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ - WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ - RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ - RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ - RwReg Reserved3[24]; - RwReg DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ - RwReg Reserved4[19]; - RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */ - RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */ - RwReg Reserved5[5]; - RwReg DACC_RPR; /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */ - RwReg DACC_RCR; /**< \brief (Dacc Offset: 0x104) Receive Counter Register */ - RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */ - RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */ - RwReg DACC_RNPR; /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */ - RwReg DACC_RNCR; /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */ - RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */ - RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */ - WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */ - RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */ -} Dacc; -#endif /* __ASSEMBLY__ */ -/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ -#define DACC_CR_SWRST (0x1 << 0) /**< \brief (DACC_CR) Software Reset */ -/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ -#define DACC_MR_TRGEN (0x1 << 0) /**< \brief (DACC_MR) Trigger Enable */ -#define DACC_MR_TRGEN_DIS (0x0 << 0) // (DACC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. -#define DACC_MR_TRGEN_EN (0x1 << 0) // (DACC_MR) Hardware trigger selected by TRGSEL field is enabled. - -#define DACC_MR_TRGSEL (0x7 << 1) /**< \brief (DACC_MR) Trigger Selection */ -#define DACC_MR_TRGSEL_EXT_TRIG (0x0 << 1) // (DACC_MR) External trigger -#define DACC_MR_TRGSEL_TIOA_0 (0x1 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 0 -#define DACC_MR_TRGSEL_TIOA_1 (0x2 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 1 -#define DACC_MR_TRGSEL_TIOA_2 (0x3 << 1) // (DACC_MR) TIO Output of the Timer Counter Channel 2 -#define DACC_MR_TRGSEL_PWM_0 (0x4 << 1) // (DACC_MR) PWM Event Line 0 -#define DACC_MR_TRGSEL_PWM_1 (0x5 << 1) // (DACC_MR) PWM Event Line 1 -#define DACC_MR_WORD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ -#define DACC_MR_WORD_HALF (0x0 << 4) /**< \brief (DACC_MR) Half-Word Transfer */ -#define DACC_MR_WORD_WORLD (0x1 << 4) /**< \brief (DACC_MR) Word Transfer */ -#define DACC_MR_SLEEP (0x1 << 5) /**< \brief (DACC_MR) Sleep Mode */ -#define DACC_MR_SLEEP_NORMAL (0x0 << 5) // (DACC_MR) Normal Mode -#define DACC_MR_SLEEP_SLEEP (0x1 << 5) // (DACC_MR) Sleep Modes -#define DACC_MR_FASTWKUP (0x1 << 6) /**< \brief (DACC_MR) Fast Wake up Mode */ -#define DACC_MR_REFRESH (0xff << 8) /**< \brief (DACC_MR) Refresh Period */ -#define DACC_MR_USER_SEL (0x3 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_USER_SEL_0 (0x0 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_USER_SEL_1 (0x1 << 16) /**< \brief (DACC_MR) User Channel Selection */ -#define DACC_MR_TAG (0x1 << 20) /**< \brief (DACC_MR) Tag Selection Mode */ -#define DACC_MR_MAXS (0x1 << 21) /**< \brief (DACC_MR) Max Speed Mode */ -#define DACC_MR_STARTUP (0x3f << 24) /**< \brief (DACC_MR) Startup Time Selection */ -/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ -#define DACC_CHER_CH0 (0x1 << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ -#define DACC_CHER_CH1 (0x1 << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ -#define DACC_CHER_CH2 (0x1 << 2) /**< \brief (DACC_CHER) Channel 2 Enable */ -/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ -#define DACC_CHDR_CH0 (0x1 << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ -#define DACC_CHDR_CH1 (0x1 << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ -#define DACC_CHDR_CH2 (0x1 << 2) /**< \brief (DACC_CHDR) Channel 2 Disable */ -/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ -#define DACC_CHSR_CH0 (0x1 << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ -#define DACC_CHSR_CH1 (0x1 << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ -#define DACC_CHSR_CH2 (0x1 << 2) /**< \brief (DACC_CHSR) Channel 2 Status */ -/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */ -#define DACC_CDR_DATA (0xffffffff << 0) /**< \brief (DACC_CDR) Data to Convert */ -/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ -#define DACC_IER_TXRDY (0x1 << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */ -#define DACC_IER_EOC (0x1 << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */ -#define DACC_IER_ENDTX (0x1 << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */ -#define DACC_IER_TXBUFE (0x1 << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ -#define DACC_IDR_TXRDY (0x1 << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */ -#define DACC_IDR_EOC (0x1 << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */ -#define DACC_IDR_ENDTX (0x1 << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */ -#define DACC_IDR_TXBUFE (0x1 << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ -#define DACC_IMR_TXRDY (0x1 << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */ -#define DACC_IMR_EOC (0x1 << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */ -#define DACC_IMR_ENDTX (0x1 << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */ -#define DACC_IMR_TXBUFE (0x1 << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ -#define DACC_ISR_TXRDY (0x1 << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */ -#define DACC_ISR_EOC (0x1 << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */ -#define DACC_ISR_ENDTX (0x1 << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */ -#define DACC_ISR_TXBUFE (0x1 << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */ -/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ -#define DACC_ACR_IBCTLCH0 (0x3 << 0) /**< \brief (DACC_ACR) Analog Output Current Control */ -#define DACC_ACR_IBCTLCH1 (0x3 << 2) /**< \brief (DACC_ACR) Analog Output Current Control */ -#define DACC_ACR_IBCTLDACCORE (0x3 << 8) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */ -/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */ -#define DACC_WPMR_WPEN (0x1 << 0) /**< \brief (DACC_WPMR) Write Protect Enable */ -#define DACC_WPMR_WPKEY (0xffffff << 8) /**< \brief (DACC_WPMR) Write Protect KEY */ -/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */ -#define DACC_WPSR_WPROTERR (0x1 << 0) /**< \brief (DACC_WPSR) Write protection error */ -#define DACC_WPSR_WPROTADDR (0xff << 8) /**< \brief (DACC_WPSR) Write protection error address */ -/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */ -#define DACC_RPR_RXPTR (0xffffffff << 0) /**< \brief (DACC_RPR) Receive Pointer Register */ -/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */ -#define DACC_RCR_RXCTR (0xffff << 0) /**< \brief (DACC_RCR) Receive Counter Register */ -/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */ -#define DACC_TPR_TXPTR (0xffffffff << 0) /**< \brief (DACC_TPR) Transmit Counter Register */ -/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */ -#define DACC_TCR_TXCTR (0xffff << 0) /**< \brief (DACC_TCR) Transmit Counter Register */ -/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */ -#define DACC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (DACC_RNPR) Receive Next Pointer */ -/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */ -#define DACC_RNCR_RXNCTR (0xffff << 0) /**< \brief (DACC_RNCR) Receive Next Counter */ -/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define DACC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (DACC_TNPR) Transmit Next Pointer */ -/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define DACC_TNCR_TXNCTR (0xffff << 0) /**< \brief (DACC_TNCR) Transmit Counter Next */ -/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */ -#define DACC_PTCR_RXTEN (0x1 << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */ -#define DACC_PTCR_RXTDIS (0x1 << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */ -#define DACC_PTCR_TXTEN (0x1 << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */ -#define DACC_PTCR_TXTDIS (0x1 << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */ -/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */ -#define DACC_PTSR_RXTEN (0x1 << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */ -#define DACC_PTSR_TXTEN (0x1 << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_EFC Embedded Flash Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Efc hardware registers */ -typedef struct { - RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ - WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ - RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ - RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ -} Efc; -#endif /* __ASSEMBLY__ */ -/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ -#define EEFC_FMR_FRDY (0x1 << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ -#define EEFC_FMR_FWS (0xf << 8) /**< \brief (EEFC_FMR) Flash Wait State */ -#define EEFC_FMR_FAM (0x1 << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ -/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ -#define EEFC_FCR_FCMD (0xff << 0) /**< \brief (EEFC_FCR) Flash Command */ -#define EEFC_FCR_FARG (0xffff << 8) /**< \brief (EEFC_FCR) Flash Command Argument */ -#define EEFC_FCR_FKEY (0xff << 24) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ -/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ -#define EEFC_FSR_FRDY (0x1 << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ -#define EEFC_FSR_FCMDE (0x1 << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ -#define EEFC_FSR_FLOCKE (0x1 << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ -/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ -#define EEFC_FRR_FVALUE (0xffffffff << 0) /**< \brief (EEFC_FRR) Flash Result Value */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_GPBR General Purpose Backup Register */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Gpbr hardware registers */ -typedef struct { - RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */ - RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */ - RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */ - RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */ -} Gpbr; -#endif /* __ASSEMBLY__ */ -/* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */ -#define SYS_GPBR0_GPBR_VALUE0 (0xffffffff << 0) /**< \brief (SYS_GPBR0) Value of GPBR x */ -/* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */ -#define SYS_GPBR1_GPBR_VALUE1 (0xffffffff << 0) /**< \brief (SYS_GPBR1) Value of GPBR x */ -/* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */ -#define SYS_GPBR2_GPBR_VALUE2 (0xffffffff << 0) /**< \brief (SYS_GPBR2) Value of GPBR x */ -/* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */ -#define SYS_GPBR3_GPBR_VALUE3 (0xffffffff << 0) /**< \brief (SYS_GPBR3) Value of GPBR x */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_HSMCI High Speed MultiMedia Card Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Hsmci hardware registers */ -typedef struct { - WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ - RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ - RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ - RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ - RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ - WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ - RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ - RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ - RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ - RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ - WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ - RwReg Reserved1[2]; - RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ - WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ - WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ - RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ - RwReg Reserved2[1]; - RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ - RwReg Reserved3[35]; - RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ - RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ - RwReg Reserved4[5]; - RwReg HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */ - RwReg HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */ - RwReg HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */ - RwReg HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */ - RwReg HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */ - RwReg HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */ - RwReg HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */ - RwReg HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */ - WoReg HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */ - RoReg HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */ -} Hsmci; -#endif /* __ASSEMBLY__ */ -/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ -#define HSMCI_CR_MCIEN (0x1 << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ -#define HSMCI_CR_MCIDIS (0x1 << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ -#define HSMCI_CR_PWSEN (0x1 << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ -#define HSMCI_CR_PWSDIS (0x1 << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ -#define HSMCI_CR_SWRST (0x1 << 7) /**< \brief (HSMCI_CR) Software Reset */ -/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ -#define HSMCI_MR_CLKDIV (0xff << 0) /**< \brief (HSMCI_MR) Clock Divider */ -#define HSMCI_MR_PWSDIV (0x7 << 8) /**< \brief (HSMCI_MR) Power Saving Divider */ -#define HSMCI_MR_RDPROOF (0x1 << 11) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_WRPROOF (0x1 << 12) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_FBYTE (0x1 << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ -#define HSMCI_MR_PADV (0x1 << 14) /**< \brief (HSMCI_MR) Padding Value */ -#define HSMCI_MR_PDCMODE (0x1 << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */ -#define HSMCI_MR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_MR) Data Block Length */ -/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ -#define HSMCI_DTOR_DTOCYC (0xf << 0) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ -#define HSMCI_DTOR_DTOMUL (0x7 << 4) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ -/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ -#define HSMCI_SDCR_SDCSEL (0x3 << 0) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ -#define HSMCI_SDCR_SDCBUS (0x3 << 6) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ -/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ -#define HSMCI_ARGR_ARG (0xffffffff << 0) /**< \brief (HSMCI_ARGR) Command Argument */ -/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ -#define HSMCI_CMDR_CMDNB (0x3f << 0) /**< \brief (HSMCI_CMDR) Command Number */ -#define HSMCI_CMDR_RSPTYP (0x3 << 6) /**< \brief (HSMCI_CMDR) Response Type */ -#define HSMCI_CMDR_SPCMD (0x7 << 8) /**< \brief (HSMCI_CMDR) Special Command */ -#define HSMCI_CMDR_OPDCMD (0x1 << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ -#define HSMCI_CMDR_MAXLAT (0x1 << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ -#define HSMCI_CMDR_TRCMD (0x3 << 16) /**< \brief (HSMCI_CMDR) Transfer Command */ -#define HSMCI_CMDR_TRDIR (0x1 << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ -#define HSMCI_CMDR_TRTYP (0x7 << 19) /**< \brief (HSMCI_CMDR) Transfer Type */ -#define HSMCI_CMDR_IOSPCMD (0x3 << 24) /**< \brief (HSMCI_CMDR) SDIO Special Command */ -#define HSMCI_CMDR_ATACS (0x1 << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ -#define HSMCI_CMDR_BOOT_ACK (0x1 << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ -/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ -#define HSMCI_BLKR_BCNT (0xffff << 0) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ -#define HSMCI_BLKR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_BLKR) Data Block Length */ -/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ -#define HSMCI_CSTOR_CSTOCYC (0xf << 0) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ -#define HSMCI_CSTOR_CSTOMUL (0x7 << 4) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ -/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ -#define HSMCI_RSPR_RSP (0xffffffff << 0) /**< \brief (HSMCI_RSPR[4]) Response */ -/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ -#define HSMCI_RDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_RDR) Data to Read */ -/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ -#define HSMCI_TDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_TDR) Data to Write */ -/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ -#define HSMCI_SR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_SR) Command Ready */ -#define HSMCI_SR_RXRDY (0x1 << 1) /**< \brief (HSMCI_SR) Receiver Ready */ -#define HSMCI_SR_TXRDY (0x1 << 2) /**< \brief (HSMCI_SR) Transmit Ready */ -#define HSMCI_SR_BLKE (0x1 << 3) /**< \brief (HSMCI_SR) Data Block Ended */ -#define HSMCI_SR_DTIP (0x1 << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ -#define HSMCI_SR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ -#define HSMCI_SR_ENDRX (0x1 << 6) /**< \brief (HSMCI_SR) End of RX Buffer */ -#define HSMCI_SR_ENDTX (0x1 << 7) /**< \brief (HSMCI_SR) End of TX Buffer */ -#define HSMCI_SR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */ -#define HSMCI_SR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ -#define HSMCI_SR_CSRCV (0x1 << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ -#define HSMCI_SR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_SR) RX Buffer Full */ -#define HSMCI_SR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */ -#define HSMCI_SR_RINDE (0x1 << 16) /**< \brief (HSMCI_SR) Response Index Error */ -#define HSMCI_SR_RDIRE (0x1 << 17) /**< \brief (HSMCI_SR) Response Direction Error */ -#define HSMCI_SR_RCRCE (0x1 << 18) /**< \brief (HSMCI_SR) Response CRC Error */ -#define HSMCI_SR_RENDE (0x1 << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ -#define HSMCI_SR_RTOE (0x1 << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ -#define HSMCI_SR_DCRCE (0x1 << 21) /**< \brief (HSMCI_SR) Data CRC Error */ -#define HSMCI_SR_DTOE (0x1 << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ -#define HSMCI_SR_CSTOE (0x1 << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ -#define HSMCI_SR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ -#define HSMCI_SR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ -#define HSMCI_SR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ -#define HSMCI_SR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ -#define HSMCI_SR_OVRE (0x1 << 30) /**< \brief (HSMCI_SR) Overrun */ -#define HSMCI_SR_UNRE (0x1 << 31) /**< \brief (HSMCI_SR) Underrun */ -/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ -#define HSMCI_IER_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ -#define HSMCI_IER_RXRDY (0x1 << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ -#define HSMCI_IER_TXRDY (0x1 << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ -#define HSMCI_IER_BLKE (0x1 << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ -#define HSMCI_IER_DTIP (0x1 << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ -#define HSMCI_IER_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ -#define HSMCI_IER_ENDRX (0x1 << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */ -#define HSMCI_IER_ENDTX (0x1 << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */ -#define HSMCI_IER_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ -#define HSMCI_IER_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ -#define HSMCI_IER_CSRCV (0x1 << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ -#define HSMCI_IER_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */ -#define HSMCI_IER_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */ -#define HSMCI_IER_RINDE (0x1 << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ -#define HSMCI_IER_RDIRE (0x1 << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ -#define HSMCI_IER_RCRCE (0x1 << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ -#define HSMCI_IER_RENDE (0x1 << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ -#define HSMCI_IER_RTOE (0x1 << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ -#define HSMCI_IER_DCRCE (0x1 << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ -#define HSMCI_IER_DTOE (0x1 << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ -#define HSMCI_IER_CSTOE (0x1 << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ -#define HSMCI_IER_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ -#define HSMCI_IER_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ -#define HSMCI_IER_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ -#define HSMCI_IER_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ -#define HSMCI_IER_OVRE (0x1 << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ -#define HSMCI_IER_UNRE (0x1 << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ -/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ -#define HSMCI_IDR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ -#define HSMCI_IDR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ -#define HSMCI_IDR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ -#define HSMCI_IDR_BLKE (0x1 << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ -#define HSMCI_IDR_DTIP (0x1 << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ -#define HSMCI_IDR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ -#define HSMCI_IDR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */ -#define HSMCI_IDR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */ -#define HSMCI_IDR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ -#define HSMCI_IDR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ -#define HSMCI_IDR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ -#define HSMCI_IDR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */ -#define HSMCI_IDR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define HSMCI_IDR_RINDE (0x1 << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ -#define HSMCI_IDR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ -#define HSMCI_IDR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ -#define HSMCI_IDR_RENDE (0x1 << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ -#define HSMCI_IDR_RTOE (0x1 << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ -#define HSMCI_IDR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ -#define HSMCI_IDR_DTOE (0x1 << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ -#define HSMCI_IDR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ -#define HSMCI_IDR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ -#define HSMCI_IDR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ -#define HSMCI_IDR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ -#define HSMCI_IDR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ -#define HSMCI_IDR_OVRE (0x1 << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ -#define HSMCI_IDR_UNRE (0x1 << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ -/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ -#define HSMCI_IMR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ -#define HSMCI_IMR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ -#define HSMCI_IMR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ -#define HSMCI_IMR_BLKE (0x1 << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ -#define HSMCI_IMR_DTIP (0x1 << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ -#define HSMCI_IMR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ -#define HSMCI_IMR_ENDRX (0x1 << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */ -#define HSMCI_IMR_ENDTX (0x1 << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */ -#define HSMCI_IMR_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ -#define HSMCI_IMR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ -#define HSMCI_IMR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ -#define HSMCI_IMR_RXBUFF (0x1 << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */ -#define HSMCI_IMR_TXBUFE (0x1 << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define HSMCI_IMR_RINDE (0x1 << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ -#define HSMCI_IMR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ -#define HSMCI_IMR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ -#define HSMCI_IMR_RENDE (0x1 << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ -#define HSMCI_IMR_RTOE (0x1 << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ -#define HSMCI_IMR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ -#define HSMCI_IMR_DTOE (0x1 << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ -#define HSMCI_IMR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ -#define HSMCI_IMR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ -#define HSMCI_IMR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ -#define HSMCI_IMR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ -#define HSMCI_IMR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ -#define HSMCI_IMR_OVRE (0x1 << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ -#define HSMCI_IMR_UNRE (0x1 << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ -/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ -#define HSMCI_CFG_FIFOMODE (0x1 << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ -#define HSMCI_CFG_FERRCTRL (0x1 << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ -#define HSMCI_CFG_HSMODE (0x1 << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ -#define HSMCI_CFG_LSYNC (0x1 << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ -/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ -#define HSMCI_WPMR_WP_EN (0x1 << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ -#define HSMCI_WPMR_WP_KEY (0xffffff << 8) /**< \brief (HSMCI_WPMR) Write Protection Key password */ -/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ -#define HSMCI_WPSR_WP_VS (0xf << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ -#define HSMCI_WPSR_WP_VSRC (0xffff << 8) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */ -/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */ -#define HSMCI_RPR_RXPTR (0xffffffff << 0) /**< \brief (HSMCI_RPR) Receive Pointer Register */ -/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */ -#define HSMCI_RCR_RXCTR (0xffff << 0) /**< \brief (HSMCI_RCR) Receive Counter Register */ -/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */ -#define HSMCI_TPR_TXPTR (0xffffffff << 0) /**< \brief (HSMCI_TPR) Transmit Counter Register */ -/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */ -#define HSMCI_TCR_TXCTR (0xffff << 0) /**< \brief (HSMCI_TCR) Transmit Counter Register */ -/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */ -#define HSMCI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (HSMCI_RNPR) Receive Next Pointer */ -/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */ -#define HSMCI_RNCR_RXNCTR (0xffff << 0) /**< \brief (HSMCI_RNCR) Receive Next Counter */ -/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define HSMCI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */ -/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define HSMCI_TNCR_TXNCTR (0xffff << 0) /**< \brief (HSMCI_TNCR) Transmit Counter Next */ -/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */ -#define HSMCI_PTCR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */ -#define HSMCI_PTCR_RXTDIS (0x1 << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */ -#define HSMCI_PTCR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */ -#define HSMCI_PTCR_TXTDIS (0x1 << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */ -/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */ -#define HSMCI_PTSR_RXTEN (0x1 << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */ -#define HSMCI_PTSR_TXTEN (0x1 << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_MATRIX AHB Bus Matrix */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Matrix hardware registers */ -typedef struct { - RwReg MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ - RwReg Reserved1[12]; - RwReg MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ - RwReg Reserved2[11]; - RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ - RwReg Reserved3[1]; - RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ - RwReg Reserved4[1]; - RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ - RwReg Reserved5[1]; - RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ - RwReg Reserved6[1]; - RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ - RwReg Reserved7[28]; - RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System IO Configuration register */ - RwReg Reserved8[1]; - RwReg CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */ - RwReg Reserved9[49]; - RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */ - RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */ -} Matrix; -#endif /* __ASSEMBLY__ */ -/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ -#define MATRIX_MCFG_ULBT (0x7 << 0) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */ -/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ -#define MATRIX_SCFG_SLOT_CYCLE (0xff << 0) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */ -#define MATRIX_SCFG_DEFMSTR_TYPE (0x3 << 16) /**< \brief (MATRIX_SCFG[5]) Default Master Type */ -#define MATRIX_SCFG_FIXED_DEFMSTR (0x7 << 18) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */ -#define MATRIX_SCFG_ARBT (0x3 << 24) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */ -/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ -#define MATRIX_PRAS0_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ -#define MATRIX_PRAS0_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ -#define MATRIX_PRAS0_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ -#define MATRIX_PRAS0_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ -#define MATRIX_PRAS0_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ -/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ -#define MATRIX_PRAS1_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ -#define MATRIX_PRAS1_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ -#define MATRIX_PRAS1_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ -#define MATRIX_PRAS1_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ -#define MATRIX_PRAS1_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ -/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ -#define MATRIX_PRAS2_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ -#define MATRIX_PRAS2_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ -#define MATRIX_PRAS2_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ -#define MATRIX_PRAS2_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ -#define MATRIX_PRAS2_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ -/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ -#define MATRIX_PRAS3_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ -#define MATRIX_PRAS3_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ -#define MATRIX_PRAS3_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ -#define MATRIX_PRAS3_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ -#define MATRIX_PRAS3_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ -/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ -#define MATRIX_PRAS4_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ -#define MATRIX_PRAS4_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ -#define MATRIX_PRAS4_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ -#define MATRIX_PRAS4_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ -#define MATRIX_PRAS4_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ -/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System IO Configuration register -------- */ -#define CCFG_SYSIO_SYSIO4 (0x1 << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ -#define CCFG_SYSIO_SYSIO5 (0x1 << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ -#define CCFG_SYSIO_SYSIO6 (0x1 << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ -#define CCFG_SYSIO_SYSIO7 (0x1 << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ -#define CCFG_SYSIO_SYSIO10 (0x1 << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */ -#define CCFG_SYSIO_SYSIO11 (0x1 << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */ -#define CCFG_SYSIO_SYSIO12 (0x1 << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ -/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */ -#define CCFG_SMCNFCS_SMC_NFCS0 (0x1 << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS1 (0x1 << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS2 (0x1 << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ -#define CCFG_SMCNFCS_SMC_NFCS3 (0x1 << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ -/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */ -#define MATRIX_WPMR_WPEN (0x1 << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */ -#define MATRIX_WPMR_WPKEY (0xffffff << 8) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */ -/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */ -#define MATRIX_WPSR_WPVS (0x1 << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */ -#define MATRIX_WPSR_WPVSRC (0xffff << 8) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PDC Peripheral DMA Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pdc hardware registers */ -typedef struct { - RwReg Reserved1[64]; - RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x100) Receive Pointer Register */ - RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x104) Receive Counter Register */ - RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x108) Transmit Pointer Register */ - RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x10C) Transmit Counter Register */ - RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x110) Receive Next Pointer Register */ - RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x114) Receive Next Counter Register */ - RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x118) Transmit Next Pointer Register */ - RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x11C) Transmit Next Counter Register */ - WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x120) Transfer Control Register */ - RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x124) Transfer Status Register */ -} Pdc; -#endif /* __ASSEMBLY__ */ -/* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */ -#define PERIPH_RPR_RXPTR (0xffffffff << 0) /**< \brief (PERIPH_RPR) Receive Pointer Register */ -/* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */ -#define PERIPH_RCR_RXCTR (0xffff << 0) /**< \brief (PERIPH_RCR) Receive Counter Register */ -/* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */ -#define PERIPH_TPR_TXPTR (0xffffffff << 0) /**< \brief (PERIPH_TPR) Transmit Counter Register */ -/* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */ -#define PERIPH_TCR_TXCTR (0xffff << 0) /**< \brief (PERIPH_TCR) Transmit Counter Register */ -/* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */ -#define PERIPH_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ -/* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */ -#define PERIPH_RNCR_RXNCTR (0xffff << 0) /**< \brief (PERIPH_RNCR) Receive Next Counter */ -/* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PERIPH_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ -/* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PERIPH_TNCR_TXNCTR (0xffff << 0) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ -/* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */ -#define PERIPH_PTCR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ -#define PERIPH_PTCR_RXTDIS (0x1 << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ -#define PERIPH_PTCR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ -#define PERIPH_PTCR_TXTDIS (0x1 << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ -/* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */ -#define PERIPH_PTSR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ -#define PERIPH_PTSR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Parallel Input/Output */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PIO Parallel Input/Output */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pio hardware registers */ -typedef struct { - WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ - WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ - RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ - RwReg Reserved1[1]; - WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ - WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ - RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ - RwReg Reserved2[1]; - WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ - WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ - RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ - RwReg Reserved3[1]; - WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ - WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ - RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ - RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ - WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ - WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ - RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ - RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ - WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ - WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ - RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ - RwReg Reserved4[1]; - WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ - WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ - RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ - RwReg Reserved5[1]; - RwReg PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ - RwReg Reserved6[2]; - WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */ - WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */ - RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */ - RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ - WoReg PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ - WoReg PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ - RoReg PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ - RwReg Reserved7[1]; - WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ - WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ - RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ - RwReg Reserved8[1]; - WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ - WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ - RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ - RwReg Reserved9[1]; - WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ - WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ - RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ - RwReg Reserved10[1]; - WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ - WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ - RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ - RwReg Reserved11[1]; - RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ - RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ - RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ - RwReg Reserved12[5]; - RwReg PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ - RwReg Reserved13[19]; - RwReg PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */ - WoReg PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */ - WoReg PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */ - RoReg PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */ - RoReg PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */ - RoReg PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */ -} Pio; -#endif /* __ASSEMBLY__ */ -/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ -#define PIO_PER_P0 (0x1 << 0) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P1 (0x1 << 1) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P2 (0x1 << 2) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P3 (0x1 << 3) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P4 (0x1 << 4) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P5 (0x1 << 5) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P6 (0x1 << 6) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P7 (0x1 << 7) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P8 (0x1 << 8) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P9 (0x1 << 9) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P10 (0x1 << 10) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P11 (0x1 << 11) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P12 (0x1 << 12) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P13 (0x1 << 13) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P14 (0x1 << 14) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P15 (0x1 << 15) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P16 (0x1 << 16) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P17 (0x1 << 17) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P18 (0x1 << 18) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P19 (0x1 << 19) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P20 (0x1 << 20) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P21 (0x1 << 21) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P22 (0x1 << 22) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P23 (0x1 << 23) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P24 (0x1 << 24) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P25 (0x1 << 25) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P26 (0x1 << 26) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P27 (0x1 << 27) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P28 (0x1 << 28) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P29 (0x1 << 29) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P30 (0x1 << 30) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P31 (0x1 << 31) /**< \brief (PIO_PER) PIO Enable */ -/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ -#define PIO_PDR_P0 (0x1 << 0) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P1 (0x1 << 1) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P2 (0x1 << 2) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P3 (0x1 << 3) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P4 (0x1 << 4) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P5 (0x1 << 5) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P6 (0x1 << 6) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P7 (0x1 << 7) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P8 (0x1 << 8) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P9 (0x1 << 9) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P10 (0x1 << 10) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P11 (0x1 << 11) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P12 (0x1 << 12) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P13 (0x1 << 13) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P14 (0x1 << 14) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P15 (0x1 << 15) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P16 (0x1 << 16) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P17 (0x1 << 17) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P18 (0x1 << 18) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P19 (0x1 << 19) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P20 (0x1 << 20) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P21 (0x1 << 21) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P22 (0x1 << 22) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P23 (0x1 << 23) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P24 (0x1 << 24) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P25 (0x1 << 25) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P26 (0x1 << 26) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P27 (0x1 << 27) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P28 (0x1 << 28) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P29 (0x1 << 29) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P30 (0x1 << 30) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P31 (0x1 << 31) /**< \brief (PIO_PDR) PIO Disable */ -/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ -#define PIO_PSR_P0 (0x1 << 0) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P1 (0x1 << 1) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P2 (0x1 << 2) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P3 (0x1 << 3) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P4 (0x1 << 4) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P5 (0x1 << 5) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P6 (0x1 << 6) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P7 (0x1 << 7) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P8 (0x1 << 8) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P9 (0x1 << 9) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P10 (0x1 << 10) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P11 (0x1 << 11) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P12 (0x1 << 12) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P13 (0x1 << 13) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P14 (0x1 << 14) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P15 (0x1 << 15) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P16 (0x1 << 16) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P17 (0x1 << 17) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P18 (0x1 << 18) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P19 (0x1 << 19) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P20 (0x1 << 20) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P21 (0x1 << 21) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P22 (0x1 << 22) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P23 (0x1 << 23) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P24 (0x1 << 24) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P25 (0x1 << 25) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P26 (0x1 << 26) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P27 (0x1 << 27) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P28 (0x1 << 28) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P29 (0x1 << 29) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P30 (0x1 << 30) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P31 (0x1 << 31) /**< \brief (PIO_PSR) PIO Status */ -/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ -#define PIO_OER_P0 (0x1 << 0) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P1 (0x1 << 1) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P2 (0x1 << 2) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P3 (0x1 << 3) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P4 (0x1 << 4) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P5 (0x1 << 5) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P6 (0x1 << 6) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P7 (0x1 << 7) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P8 (0x1 << 8) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P9 (0x1 << 9) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P10 (0x1 << 10) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P11 (0x1 << 11) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P12 (0x1 << 12) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P13 (0x1 << 13) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P14 (0x1 << 14) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P15 (0x1 << 15) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P16 (0x1 << 16) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P17 (0x1 << 17) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P18 (0x1 << 18) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P19 (0x1 << 19) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P20 (0x1 << 20) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P21 (0x1 << 21) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P22 (0x1 << 22) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P23 (0x1 << 23) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P24 (0x1 << 24) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P25 (0x1 << 25) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P26 (0x1 << 26) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P27 (0x1 << 27) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P28 (0x1 << 28) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P29 (0x1 << 29) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P30 (0x1 << 30) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P31 (0x1 << 31) /**< \brief (PIO_OER) Output Enable */ -/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ -#define PIO_ODR_P0 (0x1 << 0) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P1 (0x1 << 1) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P2 (0x1 << 2) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P3 (0x1 << 3) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P4 (0x1 << 4) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P5 (0x1 << 5) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P6 (0x1 << 6) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P7 (0x1 << 7) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P8 (0x1 << 8) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P9 (0x1 << 9) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P10 (0x1 << 10) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P11 (0x1 << 11) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P12 (0x1 << 12) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P13 (0x1 << 13) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P14 (0x1 << 14) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P15 (0x1 << 15) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P16 (0x1 << 16) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P17 (0x1 << 17) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P18 (0x1 << 18) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P19 (0x1 << 19) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P20 (0x1 << 20) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P21 (0x1 << 21) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P22 (0x1 << 22) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P23 (0x1 << 23) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P24 (0x1 << 24) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P25 (0x1 << 25) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P26 (0x1 << 26) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P27 (0x1 << 27) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P28 (0x1 << 28) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P29 (0x1 << 29) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P30 (0x1 << 30) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P31 (0x1 << 31) /**< \brief (PIO_ODR) Output Disable */ -/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ -#define PIO_OSR_P0 (0x1 << 0) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P1 (0x1 << 1) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P2 (0x1 << 2) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P3 (0x1 << 3) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P4 (0x1 << 4) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P5 (0x1 << 5) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P6 (0x1 << 6) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P7 (0x1 << 7) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P8 (0x1 << 8) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P9 (0x1 << 9) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P10 (0x1 << 10) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P11 (0x1 << 11) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P12 (0x1 << 12) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P13 (0x1 << 13) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P14 (0x1 << 14) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P15 (0x1 << 15) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P16 (0x1 << 16) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P17 (0x1 << 17) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P18 (0x1 << 18) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P19 (0x1 << 19) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P20 (0x1 << 20) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P21 (0x1 << 21) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P22 (0x1 << 22) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P23 (0x1 << 23) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P24 (0x1 << 24) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P25 (0x1 << 25) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P26 (0x1 << 26) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P27 (0x1 << 27) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P28 (0x1 << 28) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P29 (0x1 << 29) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P30 (0x1 << 30) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P31 (0x1 << 31) /**< \brief (PIO_OSR) Output Status */ -/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ -#define PIO_IFER_P0 (0x1 << 0) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P1 (0x1 << 1) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P2 (0x1 << 2) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P3 (0x1 << 3) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P4 (0x1 << 4) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P5 (0x1 << 5) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P6 (0x1 << 6) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P7 (0x1 << 7) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P8 (0x1 << 8) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P9 (0x1 << 9) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P10 (0x1 << 10) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P11 (0x1 << 11) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P12 (0x1 << 12) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P13 (0x1 << 13) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P14 (0x1 << 14) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P15 (0x1 << 15) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P16 (0x1 << 16) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P17 (0x1 << 17) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P18 (0x1 << 18) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P19 (0x1 << 19) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P20 (0x1 << 20) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P21 (0x1 << 21) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P22 (0x1 << 22) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P23 (0x1 << 23) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P24 (0x1 << 24) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P25 (0x1 << 25) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P26 (0x1 << 26) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P27 (0x1 << 27) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P28 (0x1 << 28) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P29 (0x1 << 29) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P30 (0x1 << 30) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P31 (0x1 << 31) /**< \brief (PIO_IFER) Input Filter Enable */ -/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ -#define PIO_IFDR_P0 (0x1 << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P1 (0x1 << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P2 (0x1 << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P3 (0x1 << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P4 (0x1 << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P5 (0x1 << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P6 (0x1 << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P7 (0x1 << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P8 (0x1 << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P9 (0x1 << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P10 (0x1 << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P11 (0x1 << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P12 (0x1 << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P13 (0x1 << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P14 (0x1 << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P15 (0x1 << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P16 (0x1 << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P17 (0x1 << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P18 (0x1 << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P19 (0x1 << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P20 (0x1 << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P21 (0x1 << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P22 (0x1 << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P23 (0x1 << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P24 (0x1 << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P25 (0x1 << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P26 (0x1 << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P27 (0x1 << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P28 (0x1 << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P29 (0x1 << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P30 (0x1 << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P31 (0x1 << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ -/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ -#define PIO_IFSR_P0 (0x1 << 0) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P1 (0x1 << 1) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P2 (0x1 << 2) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P3 (0x1 << 3) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P4 (0x1 << 4) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P5 (0x1 << 5) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P6 (0x1 << 6) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P7 (0x1 << 7) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P8 (0x1 << 8) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P9 (0x1 << 9) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P10 (0x1 << 10) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P11 (0x1 << 11) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P12 (0x1 << 12) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P13 (0x1 << 13) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P14 (0x1 << 14) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P15 (0x1 << 15) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P16 (0x1 << 16) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P17 (0x1 << 17) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P18 (0x1 << 18) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P19 (0x1 << 19) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P20 (0x1 << 20) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P21 (0x1 << 21) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P22 (0x1 << 22) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P23 (0x1 << 23) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P24 (0x1 << 24) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P25 (0x1 << 25) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P26 (0x1 << 26) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P27 (0x1 << 27) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P28 (0x1 << 28) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P29 (0x1 << 29) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P30 (0x1 << 30) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P31 (0x1 << 31) /**< \brief (PIO_IFSR) Input Filer Status */ -/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ -#define PIO_SODR_P0 (0x1 << 0) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P1 (0x1 << 1) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P2 (0x1 << 2) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P3 (0x1 << 3) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P4 (0x1 << 4) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P5 (0x1 << 5) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P6 (0x1 << 6) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P7 (0x1 << 7) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P8 (0x1 << 8) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P9 (0x1 << 9) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P10 (0x1 << 10) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P11 (0x1 << 11) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P12 (0x1 << 12) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P13 (0x1 << 13) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P14 (0x1 << 14) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P15 (0x1 << 15) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P16 (0x1 << 16) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P17 (0x1 << 17) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P18 (0x1 << 18) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P19 (0x1 << 19) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P20 (0x1 << 20) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P21 (0x1 << 21) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P22 (0x1 << 22) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P23 (0x1 << 23) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P24 (0x1 << 24) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P25 (0x1 << 25) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P26 (0x1 << 26) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P27 (0x1 << 27) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P28 (0x1 << 28) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P29 (0x1 << 29) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P30 (0x1 << 30) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P31 (0x1 << 31) /**< \brief (PIO_SODR) Set Output Data */ -/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ -#define PIO_CODR_P0 (0x1 << 0) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P1 (0x1 << 1) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P2 (0x1 << 2) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P3 (0x1 << 3) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P4 (0x1 << 4) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P5 (0x1 << 5) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P6 (0x1 << 6) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P7 (0x1 << 7) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P8 (0x1 << 8) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P9 (0x1 << 9) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P10 (0x1 << 10) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P11 (0x1 << 11) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P12 (0x1 << 12) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P13 (0x1 << 13) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P14 (0x1 << 14) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P15 (0x1 << 15) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P16 (0x1 << 16) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P17 (0x1 << 17) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P18 (0x1 << 18) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P19 (0x1 << 19) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P20 (0x1 << 20) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P21 (0x1 << 21) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P22 (0x1 << 22) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P23 (0x1 << 23) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P24 (0x1 << 24) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P25 (0x1 << 25) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P26 (0x1 << 26) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P27 (0x1 << 27) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P28 (0x1 << 28) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P29 (0x1 << 29) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P30 (0x1 << 30) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P31 (0x1 << 31) /**< \brief (PIO_CODR) Clear Output Data */ -/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ -#define PIO_ODSR_P0 (0x1 << 0) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P1 (0x1 << 1) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P2 (0x1 << 2) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P3 (0x1 << 3) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P4 (0x1 << 4) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P5 (0x1 << 5) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P6 (0x1 << 6) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P7 (0x1 << 7) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P8 (0x1 << 8) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P9 (0x1 << 9) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P10 (0x1 << 10) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P11 (0x1 << 11) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P12 (0x1 << 12) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P13 (0x1 << 13) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P14 (0x1 << 14) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P15 (0x1 << 15) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P16 (0x1 << 16) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P17 (0x1 << 17) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P18 (0x1 << 18) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P19 (0x1 << 19) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P20 (0x1 << 20) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P21 (0x1 << 21) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P22 (0x1 << 22) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P23 (0x1 << 23) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P24 (0x1 << 24) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P25 (0x1 << 25) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P26 (0x1 << 26) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P27 (0x1 << 27) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P28 (0x1 << 28) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P29 (0x1 << 29) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P30 (0x1 << 30) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P31 (0x1 << 31) /**< \brief (PIO_ODSR) Output Data Status */ -/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ -#define PIO_PDSR_P0 (0x1 << 0) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P1 (0x1 << 1) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P2 (0x1 << 2) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P3 (0x1 << 3) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P4 (0x1 << 4) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P5 (0x1 << 5) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P6 (0x1 << 6) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P7 (0x1 << 7) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P8 (0x1 << 8) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P9 (0x1 << 9) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P10 (0x1 << 10) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P11 (0x1 << 11) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P12 (0x1 << 12) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P13 (0x1 << 13) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P14 (0x1 << 14) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P15 (0x1 << 15) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P16 (0x1 << 16) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P17 (0x1 << 17) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P18 (0x1 << 18) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P19 (0x1 << 19) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P20 (0x1 << 20) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P21 (0x1 << 21) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P22 (0x1 << 22) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P23 (0x1 << 23) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P24 (0x1 << 24) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P25 (0x1 << 25) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P26 (0x1 << 26) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P27 (0x1 << 27) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P28 (0x1 << 28) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P29 (0x1 << 29) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P30 (0x1 << 30) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P31 (0x1 << 31) /**< \brief (PIO_PDSR) Output Data Status */ -/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ -#define PIO_IER_P0 (0x1 << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P1 (0x1 << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P2 (0x1 << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P3 (0x1 << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P4 (0x1 << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P5 (0x1 << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P6 (0x1 << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P7 (0x1 << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P8 (0x1 << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P9 (0x1 << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P10 (0x1 << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P11 (0x1 << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P12 (0x1 << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P13 (0x1 << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P14 (0x1 << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P15 (0x1 << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P16 (0x1 << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P17 (0x1 << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P18 (0x1 << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P19 (0x1 << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P20 (0x1 << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P21 (0x1 << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P22 (0x1 << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P23 (0x1 << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P24 (0x1 << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P25 (0x1 << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P26 (0x1 << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P27 (0x1 << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P28 (0x1 << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P29 (0x1 << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P30 (0x1 << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P31 (0x1 << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ -#define PIO_IDR_P0 (0x1 << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P1 (0x1 << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P2 (0x1 << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P3 (0x1 << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P4 (0x1 << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P5 (0x1 << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P6 (0x1 << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P7 (0x1 << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P8 (0x1 << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P9 (0x1 << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P10 (0x1 << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P11 (0x1 << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P12 (0x1 << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P13 (0x1 << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P14 (0x1 << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P15 (0x1 << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P16 (0x1 << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P17 (0x1 << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P18 (0x1 << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P19 (0x1 << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P20 (0x1 << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P21 (0x1 << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P22 (0x1 << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P23 (0x1 << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P24 (0x1 << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P25 (0x1 << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P26 (0x1 << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P27 (0x1 << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P28 (0x1 << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P29 (0x1 << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P30 (0x1 << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P31 (0x1 << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ -#define PIO_IMR_P0 (0x1 << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P1 (0x1 << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P2 (0x1 << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P3 (0x1 << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P4 (0x1 << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P5 (0x1 << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P6 (0x1 << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P7 (0x1 << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P8 (0x1 << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P9 (0x1 << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P10 (0x1 << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P11 (0x1 << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P12 (0x1 << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P13 (0x1 << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P14 (0x1 << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P15 (0x1 << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P16 (0x1 << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P17 (0x1 << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P18 (0x1 << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P19 (0x1 << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P20 (0x1 << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P21 (0x1 << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P22 (0x1 << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P23 (0x1 << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P24 (0x1 << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P25 (0x1 << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P26 (0x1 << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P27 (0x1 << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P28 (0x1 << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P29 (0x1 << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P30 (0x1 << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P31 (0x1 << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ -#define PIO_ISR_P0 (0x1 << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P1 (0x1 << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P2 (0x1 << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P3 (0x1 << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P4 (0x1 << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P5 (0x1 << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P6 (0x1 << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P7 (0x1 << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P8 (0x1 << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P9 (0x1 << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P10 (0x1 << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P11 (0x1 << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P12 (0x1 << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P13 (0x1 << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P14 (0x1 << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P15 (0x1 << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P16 (0x1 << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P17 (0x1 << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P18 (0x1 << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P19 (0x1 << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P20 (0x1 << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P21 (0x1 << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P22 (0x1 << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P23 (0x1 << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P24 (0x1 << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P25 (0x1 << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P26 (0x1 << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P27 (0x1 << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P28 (0x1 << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P29 (0x1 << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P30 (0x1 << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P31 (0x1 << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ -#define PIO_MDER_P0 (0x1 << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P1 (0x1 << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P2 (0x1 << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P3 (0x1 << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P4 (0x1 << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P5 (0x1 << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P6 (0x1 << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P7 (0x1 << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P8 (0x1 << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P9 (0x1 << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P10 (0x1 << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P11 (0x1 << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P12 (0x1 << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P13 (0x1 << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P14 (0x1 << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P15 (0x1 << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P16 (0x1 << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P17 (0x1 << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P18 (0x1 << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P19 (0x1 << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P20 (0x1 << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P21 (0x1 << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P22 (0x1 << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P23 (0x1 << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P24 (0x1 << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P25 (0x1 << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P26 (0x1 << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P27 (0x1 << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P28 (0x1 << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P29 (0x1 << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P30 (0x1 << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P31 (0x1 << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ -/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ -#define PIO_MDDR_P0 (0x1 << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P1 (0x1 << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P2 (0x1 << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P3 (0x1 << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P4 (0x1 << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P5 (0x1 << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P6 (0x1 << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P7 (0x1 << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P8 (0x1 << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P9 (0x1 << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P10 (0x1 << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P11 (0x1 << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P12 (0x1 << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P13 (0x1 << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P14 (0x1 << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P15 (0x1 << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P16 (0x1 << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P17 (0x1 << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P18 (0x1 << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P19 (0x1 << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P20 (0x1 << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P21 (0x1 << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P22 (0x1 << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P23 (0x1 << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P24 (0x1 << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P25 (0x1 << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P26 (0x1 << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P27 (0x1 << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P28 (0x1 << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P29 (0x1 << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P30 (0x1 << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P31 (0x1 << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ -#define PIO_MDSR_P0 (0x1 << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P1 (0x1 << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P2 (0x1 << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P3 (0x1 << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P4 (0x1 << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P5 (0x1 << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P6 (0x1 << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P7 (0x1 << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P8 (0x1 << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P9 (0x1 << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P10 (0x1 << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P11 (0x1 << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P12 (0x1 << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P13 (0x1 << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P14 (0x1 << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P15 (0x1 << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P16 (0x1 << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P17 (0x1 << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P18 (0x1 << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P19 (0x1 << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P20 (0x1 << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P21 (0x1 << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P22 (0x1 << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P23 (0x1 << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P24 (0x1 << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P25 (0x1 << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P26 (0x1 << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P27 (0x1 << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P28 (0x1 << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P29 (0x1 << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P30 (0x1 << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P31 (0x1 << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ -/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ -#define PIO_PUDR_P0 (0x1 << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P1 (0x1 << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P2 (0x1 << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P3 (0x1 << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P4 (0x1 << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P5 (0x1 << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P6 (0x1 << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P7 (0x1 << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P8 (0x1 << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P9 (0x1 << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P10 (0x1 << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P11 (0x1 << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P12 (0x1 << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P13 (0x1 << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P14 (0x1 << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P15 (0x1 << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P16 (0x1 << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P17 (0x1 << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P18 (0x1 << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P19 (0x1 << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P20 (0x1 << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P21 (0x1 << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P22 (0x1 << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P23 (0x1 << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P24 (0x1 << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P25 (0x1 << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P26 (0x1 << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P27 (0x1 << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P28 (0x1 << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P29 (0x1 << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P30 (0x1 << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P31 (0x1 << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ -/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ -#define PIO_PUER_P0 (0x1 << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P1 (0x1 << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P2 (0x1 << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P3 (0x1 << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P4 (0x1 << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P5 (0x1 << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P6 (0x1 << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P7 (0x1 << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P8 (0x1 << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P9 (0x1 << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P10 (0x1 << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P11 (0x1 << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P12 (0x1 << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P13 (0x1 << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P14 (0x1 << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P15 (0x1 << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P16 (0x1 << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P17 (0x1 << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P18 (0x1 << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P19 (0x1 << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P20 (0x1 << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P21 (0x1 << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P22 (0x1 << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P23 (0x1 << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P24 (0x1 << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P25 (0x1 << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P26 (0x1 << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P27 (0x1 << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P28 (0x1 << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P29 (0x1 << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P30 (0x1 << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P31 (0x1 << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ -/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ -#define PIO_PUSR_P0 (0x1 << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P1 (0x1 << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P2 (0x1 << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P3 (0x1 << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P4 (0x1 << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P5 (0x1 << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P6 (0x1 << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P7 (0x1 << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P8 (0x1 << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P9 (0x1 << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P10 (0x1 << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P11 (0x1 << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P12 (0x1 << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P13 (0x1 << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P14 (0x1 << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P15 (0x1 << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P16 (0x1 << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P17 (0x1 << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P18 (0x1 << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P19 (0x1 << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P20 (0x1 << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P21 (0x1 << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P22 (0x1 << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P23 (0x1 << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P24 (0x1 << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P25 (0x1 << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P26 (0x1 << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P27 (0x1 << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P28 (0x1 << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P29 (0x1 << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P30 (0x1 << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P31 (0x1 << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ -/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ -#define PIO_ABCDSR_P0 (0x1 << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P1 (0x1 << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P2 (0x1 << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P3 (0x1 << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P4 (0x1 << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P5 (0x1 << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P6 (0x1 << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P7 (0x1 << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P8 (0x1 << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P9 (0x1 << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P10 (0x1 << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P11 (0x1 << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P12 (0x1 << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P13 (0x1 << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P14 (0x1 << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P15 (0x1 << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P16 (0x1 << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P17 (0x1 << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P18 (0x1 << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P19 (0x1 << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P20 (0x1 << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P21 (0x1 << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P22 (0x1 << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P23 (0x1 << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P24 (0x1 << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P25 (0x1 << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P26 (0x1 << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P27 (0x1 << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P28 (0x1 << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P29 (0x1 << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P30 (0x1 << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -#define PIO_ABCDSR_P31 (0x1 << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ -/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */ -#define PIO_SCIFSR_P0 (0x1 << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P1 (0x1 << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P2 (0x1 << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P3 (0x1 << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P4 (0x1 << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P5 (0x1 << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P6 (0x1 << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P7 (0x1 << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P8 (0x1 << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P9 (0x1 << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P10 (0x1 << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P11 (0x1 << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P12 (0x1 << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P13 (0x1 << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P14 (0x1 << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P15 (0x1 << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P16 (0x1 << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P17 (0x1 << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P18 (0x1 << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P19 (0x1 << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P20 (0x1 << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P21 (0x1 << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P22 (0x1 << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P23 (0x1 << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P24 (0x1 << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P25 (0x1 << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P26 (0x1 << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P27 (0x1 << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P28 (0x1 << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P29 (0x1 << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P30 (0x1 << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P31 (0x1 << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */ -#define PIO_DIFSR_P0 (0x1 << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P1 (0x1 << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P2 (0x1 << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P3 (0x1 << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P4 (0x1 << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P5 (0x1 << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P6 (0x1 << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P7 (0x1 << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P8 (0x1 << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P9 (0x1 << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P10 (0x1 << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P11 (0x1 << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P12 (0x1 << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P13 (0x1 << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P14 (0x1 << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P15 (0x1 << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P16 (0x1 << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P17 (0x1 << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P18 (0x1 << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P19 (0x1 << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P20 (0x1 << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P21 (0x1 << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P22 (0x1 << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P23 (0x1 << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P24 (0x1 << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P25 (0x1 << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P26 (0x1 << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P27 (0x1 << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P28 (0x1 << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P29 (0x1 << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P30 (0x1 << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P31 (0x1 << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */ -#define PIO_IFDGSR_P0 (0x1 << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P1 (0x1 << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P2 (0x1 << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P3 (0x1 << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P4 (0x1 << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P5 (0x1 << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P6 (0x1 << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P7 (0x1 << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P8 (0x1 << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P9 (0x1 << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P10 (0x1 << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P11 (0x1 << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P12 (0x1 << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P13 (0x1 << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P14 (0x1 << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P15 (0x1 << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P16 (0x1 << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P17 (0x1 << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P18 (0x1 << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P19 (0x1 << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P20 (0x1 << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P21 (0x1 << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P22 (0x1 << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P23 (0x1 << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P24 (0x1 << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P25 (0x1 << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P26 (0x1 << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P27 (0x1 << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P28 (0x1 << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P29 (0x1 << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P30 (0x1 << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P31 (0x1 << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ -#define PIO_SCDR_DIV0 (0x1 << 0) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV1 (0x1 << 1) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV2 (0x1 << 2) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV3 (0x1 << 3) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV4 (0x1 << 4) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV5 (0x1 << 5) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV6 (0x1 << 6) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV7 (0x1 << 7) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV8 (0x1 << 8) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV9 (0x1 << 9) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV10 (0x1 << 10) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV11 (0x1 << 11) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV12 (0x1 << 12) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -#define PIO_SCDR_DIV13 (0x1 << 13) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ -/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ -#define PIO_PPDDR_P0 (0x1 << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P1 (0x1 << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P2 (0x1 << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P3 (0x1 << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P4 (0x1 << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P5 (0x1 << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P6 (0x1 << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P7 (0x1 << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P8 (0x1 << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P9 (0x1 << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P10 (0x1 << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P11 (0x1 << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P12 (0x1 << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P13 (0x1 << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P14 (0x1 << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P15 (0x1 << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P16 (0x1 << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P17 (0x1 << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P18 (0x1 << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P19 (0x1 << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P20 (0x1 << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P21 (0x1 << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P22 (0x1 << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P23 (0x1 << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P24 (0x1 << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P25 (0x1 << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P26 (0x1 << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P27 (0x1 << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P28 (0x1 << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P29 (0x1 << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P30 (0x1 << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -#define PIO_PPDDR_P31 (0x1 << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */ -/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ -#define PIO_PPDER_P0 (0x1 << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P1 (0x1 << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P2 (0x1 << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P3 (0x1 << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P4 (0x1 << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P5 (0x1 << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P6 (0x1 << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P7 (0x1 << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P8 (0x1 << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P9 (0x1 << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P10 (0x1 << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P11 (0x1 << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P12 (0x1 << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P13 (0x1 << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P14 (0x1 << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P15 (0x1 << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P16 (0x1 << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P17 (0x1 << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P18 (0x1 << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P19 (0x1 << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P20 (0x1 << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P21 (0x1 << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P22 (0x1 << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P23 (0x1 << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P24 (0x1 << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P25 (0x1 << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P26 (0x1 << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P27 (0x1 << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P28 (0x1 << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P29 (0x1 << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P30 (0x1 << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */ -#define PIO_PPDER_P31 (0x1 << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */ -/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ -#define PIO_PPDSR_P0 (0x1 << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P1 (0x1 << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P2 (0x1 << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P3 (0x1 << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P4 (0x1 << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P5 (0x1 << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P6 (0x1 << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P7 (0x1 << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P8 (0x1 << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P9 (0x1 << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P10 (0x1 << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P11 (0x1 << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P12 (0x1 << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P13 (0x1 << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P14 (0x1 << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P15 (0x1 << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P16 (0x1 << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P17 (0x1 << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P18 (0x1 << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P19 (0x1 << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P20 (0x1 << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P21 (0x1 << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P22 (0x1 << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P23 (0x1 << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P24 (0x1 << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P25 (0x1 << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P26 (0x1 << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P27 (0x1 << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P28 (0x1 << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P29 (0x1 << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P30 (0x1 << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */ -#define PIO_PPDSR_P31 (0x1 << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */ -/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ -#define PIO_OWER_P0 (0x1 << 0) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P1 (0x1 << 1) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P2 (0x1 << 2) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P3 (0x1 << 3) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P4 (0x1 << 4) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P5 (0x1 << 5) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P6 (0x1 << 6) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P7 (0x1 << 7) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P8 (0x1 << 8) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P9 (0x1 << 9) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P10 (0x1 << 10) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P11 (0x1 << 11) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P12 (0x1 << 12) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P13 (0x1 << 13) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P14 (0x1 << 14) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P15 (0x1 << 15) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P16 (0x1 << 16) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P17 (0x1 << 17) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P18 (0x1 << 18) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P19 (0x1 << 19) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P20 (0x1 << 20) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P21 (0x1 << 21) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P22 (0x1 << 22) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P23 (0x1 << 23) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P24 (0x1 << 24) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P25 (0x1 << 25) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P26 (0x1 << 26) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P27 (0x1 << 27) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P28 (0x1 << 28) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P29 (0x1 << 29) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P30 (0x1 << 30) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P31 (0x1 << 31) /**< \brief (PIO_OWER) Output Write Enable. */ -/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ -#define PIO_OWDR_P0 (0x1 << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P1 (0x1 << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P2 (0x1 << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P3 (0x1 << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P4 (0x1 << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P5 (0x1 << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P6 (0x1 << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P7 (0x1 << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P8 (0x1 << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P9 (0x1 << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P10 (0x1 << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P11 (0x1 << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P12 (0x1 << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P13 (0x1 << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P14 (0x1 << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P15 (0x1 << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P16 (0x1 << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P17 (0x1 << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P18 (0x1 << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P19 (0x1 << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P20 (0x1 << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P21 (0x1 << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P22 (0x1 << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P23 (0x1 << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P24 (0x1 << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P25 (0x1 << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P26 (0x1 << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P27 (0x1 << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P28 (0x1 << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P29 (0x1 << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P30 (0x1 << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P31 (0x1 << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ -/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ -#define PIO_OWSR_P0 (0x1 << 0) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P1 (0x1 << 1) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P2 (0x1 << 2) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P3 (0x1 << 3) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P4 (0x1 << 4) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P5 (0x1 << 5) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P6 (0x1 << 6) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P7 (0x1 << 7) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P8 (0x1 << 8) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P9 (0x1 << 9) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P10 (0x1 << 10) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P11 (0x1 << 11) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P12 (0x1 << 12) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P13 (0x1 << 13) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P14 (0x1 << 14) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P15 (0x1 << 15) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P16 (0x1 << 16) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P17 (0x1 << 17) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P18 (0x1 << 18) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P19 (0x1 << 19) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P20 (0x1 << 20) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P21 (0x1 << 21) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P22 (0x1 << 22) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P23 (0x1 << 23) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P24 (0x1 << 24) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P25 (0x1 << 25) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P26 (0x1 << 26) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P27 (0x1 << 27) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P28 (0x1 << 28) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P29 (0x1 << 29) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P30 (0x1 << 30) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P31 (0x1 << 31) /**< \brief (PIO_OWSR) Output Write Status. */ -/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ -#define PIO_AIMER_P0 (0x1 << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P1 (0x1 << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P2 (0x1 << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P3 (0x1 << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P4 (0x1 << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P5 (0x1 << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P6 (0x1 << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P7 (0x1 << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P8 (0x1 << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P9 (0x1 << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P10 (0x1 << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P11 (0x1 << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P12 (0x1 << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P13 (0x1 << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P14 (0x1 << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P15 (0x1 << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P16 (0x1 << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P17 (0x1 << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P18 (0x1 << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P19 (0x1 << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P20 (0x1 << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P21 (0x1 << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P22 (0x1 << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P23 (0x1 << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P24 (0x1 << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P25 (0x1 << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P26 (0x1 << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P27 (0x1 << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P28 (0x1 << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P29 (0x1 << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P30 (0x1 << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P31 (0x1 << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ -#define PIO_AIMDR_P0 (0x1 << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P1 (0x1 << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P2 (0x1 << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P3 (0x1 << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P4 (0x1 << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P5 (0x1 << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P6 (0x1 << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P7 (0x1 << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P8 (0x1 << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P9 (0x1 << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P10 (0x1 << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P11 (0x1 << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P12 (0x1 << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P13 (0x1 << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P14 (0x1 << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P15 (0x1 << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P16 (0x1 << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P17 (0x1 << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P18 (0x1 << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P19 (0x1 << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P20 (0x1 << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P21 (0x1 << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P22 (0x1 << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P23 (0x1 << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P24 (0x1 << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P25 (0x1 << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P26 (0x1 << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P27 (0x1 << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P28 (0x1 << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P29 (0x1 << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P30 (0x1 << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P31 (0x1 << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ -#define PIO_AIMMR_P0 (0x1 << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P1 (0x1 << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P2 (0x1 << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P3 (0x1 << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P4 (0x1 << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P5 (0x1 << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P6 (0x1 << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P7 (0x1 << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P8 (0x1 << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P9 (0x1 << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P10 (0x1 << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P11 (0x1 << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P12 (0x1 << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P13 (0x1 << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P14 (0x1 << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P15 (0x1 << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P16 (0x1 << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P17 (0x1 << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P18 (0x1 << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P19 (0x1 << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P20 (0x1 << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P21 (0x1 << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P22 (0x1 << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P23 (0x1 << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P24 (0x1 << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P25 (0x1 << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P26 (0x1 << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P27 (0x1 << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P28 (0x1 << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P29 (0x1 << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P30 (0x1 << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P31 (0x1 << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ -#define PIO_ESR_P0 (0x1 << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P1 (0x1 << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P2 (0x1 << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P3 (0x1 << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P4 (0x1 << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P5 (0x1 << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P6 (0x1 << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P7 (0x1 << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P8 (0x1 << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P9 (0x1 << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P10 (0x1 << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P11 (0x1 << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P12 (0x1 << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P13 (0x1 << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P14 (0x1 << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P15 (0x1 << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P16 (0x1 << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P17 (0x1 << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P18 (0x1 << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P19 (0x1 << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P20 (0x1 << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P21 (0x1 << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P22 (0x1 << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P23 (0x1 << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P24 (0x1 << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P25 (0x1 << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P26 (0x1 << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P27 (0x1 << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P28 (0x1 << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P29 (0x1 << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P30 (0x1 << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P31 (0x1 << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ -#define PIO_LSR_P0 (0x1 << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P1 (0x1 << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P2 (0x1 << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P3 (0x1 << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P4 (0x1 << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P5 (0x1 << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P6 (0x1 << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P7 (0x1 << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P8 (0x1 << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P9 (0x1 << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P10 (0x1 << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P11 (0x1 << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P12 (0x1 << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P13 (0x1 << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P14 (0x1 << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P15 (0x1 << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P16 (0x1 << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P17 (0x1 << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P18 (0x1 << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P19 (0x1 << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P20 (0x1 << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P21 (0x1 << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P22 (0x1 << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P23 (0x1 << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P24 (0x1 << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P25 (0x1 << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P26 (0x1 << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P27 (0x1 << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P28 (0x1 << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P29 (0x1 << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P30 (0x1 << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P31 (0x1 << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ -#define PIO_ELSR_P0 (0x1 << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P1 (0x1 << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P2 (0x1 << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P3 (0x1 << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P4 (0x1 << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P5 (0x1 << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P6 (0x1 << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P7 (0x1 << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P8 (0x1 << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P9 (0x1 << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P10 (0x1 << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P11 (0x1 << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P12 (0x1 << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P13 (0x1 << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P14 (0x1 << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P15 (0x1 << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P16 (0x1 << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P17 (0x1 << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P18 (0x1 << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P19 (0x1 << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P20 (0x1 << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P21 (0x1 << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P22 (0x1 << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P23 (0x1 << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P24 (0x1 << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P25 (0x1 << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P26 (0x1 << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P27 (0x1 << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P28 (0x1 << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P29 (0x1 << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P30 (0x1 << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P31 (0x1 << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ -#define PIO_FELLSR_P0 (0x1 << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P1 (0x1 << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P2 (0x1 << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P3 (0x1 << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P4 (0x1 << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P5 (0x1 << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P6 (0x1 << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P7 (0x1 << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P8 (0x1 << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P9 (0x1 << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P10 (0x1 << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P11 (0x1 << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P12 (0x1 << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P13 (0x1 << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P14 (0x1 << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P15 (0x1 << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P16 (0x1 << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P17 (0x1 << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P18 (0x1 << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P19 (0x1 << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P20 (0x1 << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P21 (0x1 << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P22 (0x1 << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P23 (0x1 << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P24 (0x1 << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P25 (0x1 << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P26 (0x1 << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P27 (0x1 << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P28 (0x1 << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P29 (0x1 << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P30 (0x1 << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P31 (0x1 << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ -#define PIO_REHLSR_P0 (0x1 << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P1 (0x1 << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P2 (0x1 << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P3 (0x1 << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P4 (0x1 << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P5 (0x1 << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P6 (0x1 << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P7 (0x1 << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P8 (0x1 << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P9 (0x1 << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P10 (0x1 << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P11 (0x1 << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P12 (0x1 << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P13 (0x1 << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P14 (0x1 << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P15 (0x1 << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P16 (0x1 << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P17 (0x1 << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P18 (0x1 << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P19 (0x1 << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P20 (0x1 << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P21 (0x1 << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P22 (0x1 << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P23 (0x1 << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P24 (0x1 << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P25 (0x1 << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P26 (0x1 << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P27 (0x1 << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P28 (0x1 << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P29 (0x1 << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P30 (0x1 << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P31 (0x1 << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ -#define PIO_FRLHSR_P0 (0x1 << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P1 (0x1 << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P2 (0x1 << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P3 (0x1 << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P4 (0x1 << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P5 (0x1 << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P6 (0x1 << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P7 (0x1 << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P8 (0x1 << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P9 (0x1 << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P10 (0x1 << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P11 (0x1 << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P12 (0x1 << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P13 (0x1 << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P14 (0x1 << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P15 (0x1 << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P16 (0x1 << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P17 (0x1 << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P18 (0x1 << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P19 (0x1 << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P20 (0x1 << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P21 (0x1 << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P22 (0x1 << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P23 (0x1 << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P24 (0x1 << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P25 (0x1 << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P26 (0x1 << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P27 (0x1 << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P28 (0x1 << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P29 (0x1 << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P30 (0x1 << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P31 (0x1 << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ -#define PIO_LOCKSR_P0 (0x1 << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P1 (0x1 << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P2 (0x1 << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P3 (0x1 << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P4 (0x1 << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P5 (0x1 << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P6 (0x1 << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P7 (0x1 << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P8 (0x1 << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P9 (0x1 << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P10 (0x1 << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P11 (0x1 << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P12 (0x1 << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P13 (0x1 << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P14 (0x1 << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P15 (0x1 << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P16 (0x1 << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P17 (0x1 << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P18 (0x1 << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P19 (0x1 << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P20 (0x1 << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P21 (0x1 << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P22 (0x1 << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P23 (0x1 << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P24 (0x1 << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P25 (0x1 << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P26 (0x1 << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P27 (0x1 << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P28 (0x1 << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P29 (0x1 << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P30 (0x1 << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P31 (0x1 << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ -/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PIO_WPMR_WPEN (0x1 << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ -#define PIO_WPMR_WPKEY (0xffffff << 8) /**< \brief (PIO_WPMR) Write Protect KEY */ -/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ -#define PIO_WPSR_WPVS (0x1 << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ -#define PIO_WPSR_WPVSRC (0xffff << 8) /**< \brief (PIO_WPSR) Write Protect Violation Source */ -/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ -#define PIO_SCHMITT_SCHMITT0 (0x1 << 0) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT1 (0x1 << 1) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT2 (0x1 << 2) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT3 (0x1 << 3) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT4 (0x1 << 4) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT5 (0x1 << 5) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT6 (0x1 << 6) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT7 (0x1 << 7) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT8 (0x1 << 8) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT9 (0x1 << 9) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT10 (0x1 << 10) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT11 (0x1 << 11) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT12 (0x1 << 12) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT13 (0x1 << 13) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT14 (0x1 << 14) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT15 (0x1 << 15) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT16 (0x1 << 16) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT17 (0x1 << 17) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT18 (0x1 << 18) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT19 (0x1 << 19) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT20 (0x1 << 20) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT21 (0x1 << 21) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT22 (0x1 << 22) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT23 (0x1 << 23) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT24 (0x1 << 24) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT25 (0x1 << 25) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT26 (0x1 << 26) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT27 (0x1 << 27) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT28 (0x1 << 28) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT29 (0x1 << 29) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT30 (0x1 << 30) /**< \brief (PIO_SCHMITT) */ -#define PIO_SCHMITT_SCHMITT31 (0x1 << 31) /**< \brief (PIO_SCHMITT) */ -/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */ -#define PIO_PCMR_PCEN (0x1 << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ -#define PIO_PCMR_DSIZE (0x3 << 4) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ -#define PIO_PCMR_ALWYS (0x1 << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ -#define PIO_PCMR_HALFS (0x1 << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ -#define PIO_PCMR_FRSTS (0x1 << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ -/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */ -#define PIO_PCIER_DRDY (0x1 << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ -#define PIO_PCIER_OVRE (0x1 << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ -#define PIO_PCIER_ENDRX (0x1 << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ -#define PIO_PCIER_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ -/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */ -#define PIO_PCIDR_DRDY (0x1 << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ -#define PIO_PCIDR_OVRE (0x1 << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ -#define PIO_PCIDR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ -#define PIO_PCIDR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ -/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */ -#define PIO_PCIMR_DRDY (0x1 << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ -#define PIO_PCIMR_OVRE (0x1 << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ -#define PIO_PCIMR_ENDRX (0x1 << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ -#define PIO_PCIMR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ -/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */ -#define PIO_PCISR_DRDY (0x1 << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ -#define PIO_PCISR_OVRE (0x1 << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */ -#define PIO_PCISR_ENDRX (0x1 << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */ -#define PIO_PCISR_RXBUFF (0x1 << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */ -/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */ -#define PIO_PCRHR_RDATA (0xffffffff << 0) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Power Management Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PMC Power Management Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pmc hardware registers */ -typedef struct { - WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ - WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ - RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ - RwReg Reserved1[1]; - WoReg PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ - WoReg PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ - RoReg PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ - RwReg Reserved2[1]; - RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ - RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ - RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ - RwReg CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */ - RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ - RwReg Reserved3[1]; - RwReg PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ - RwReg Reserved4[1]; - RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ - RwReg Reserved5[5]; - WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ - WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ - RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ - RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ - RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ - RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ - WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ - RwReg Reserved6[26]; - RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ - RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ - RwReg Reserved7[5]; - WoReg PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ - WoReg PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ - RoReg PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ - RwReg Reserved8[1]; - RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ -} Pmc; -#endif /* __ASSEMBLY__ */ -/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ -#define PMC_SCER_UDP (0x1 << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */ -#define PMC_SCER_PCK0 (0x1 << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ -#define PMC_SCER_PCK1 (0x1 << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ -#define PMC_SCER_PCK2 (0x1 << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ -/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ -#define PMC_SCDR_UDP (0x1 << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */ -#define PMC_SCDR_PCK0 (0x1 << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ -#define PMC_SCDR_PCK1 (0x1 << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ -#define PMC_SCDR_PCK2 (0x1 << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ -/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ -#define PMC_SCSR_UDP (0x1 << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */ -#define PMC_SCSR_PCK0 (0x1 << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ -#define PMC_SCSR_PCK1 (0x1 << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ -#define PMC_SCSR_PCK2 (0x1 << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ -/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ -#define PMC_PCER0_PID2 (0x1 << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */ -#define PMC_PCER0_PID3 (0x1 << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */ -#define PMC_PCER0_PID4 (0x1 << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */ -#define PMC_PCER0_PID5 (0x1 << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */ -#define PMC_PCER0_PID6 (0x1 << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */ -#define PMC_PCER0_PID7 (0x1 << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ -#define PMC_PCER0_PID8 (0x1 << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ -#define PMC_PCER0_PID9 (0x1 << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ -#define PMC_PCER0_PID10 (0x1 << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ -#define PMC_PCER0_PID11 (0x1 << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ -#define PMC_PCER0_PID12 (0x1 << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ -#define PMC_PCER0_PID13 (0x1 << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ -#define PMC_PCER0_PID14 (0x1 << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ -#define PMC_PCER0_PID15 (0x1 << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ -#define PMC_PCER0_PID16 (0x1 << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ -#define PMC_PCER0_PID17 (0x1 << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ -#define PMC_PCER0_PID18 (0x1 << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ -#define PMC_PCER0_PID19 (0x1 << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ -#define PMC_PCER0_PID20 (0x1 << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ -#define PMC_PCER0_PID21 (0x1 << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ -#define PMC_PCER0_PID22 (0x1 << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ -#define PMC_PCER0_PID23 (0x1 << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ -#define PMC_PCER0_PID24 (0x1 << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ -#define PMC_PCER0_PID25 (0x1 << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ -#define PMC_PCER0_PID26 (0x1 << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ -#define PMC_PCER0_PID27 (0x1 << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ -#define PMC_PCER0_PID28 (0x1 << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ -#define PMC_PCER0_PID29 (0x1 << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ -#define PMC_PCER0_PID30 (0x1 << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ -#define PMC_PCER0_PID31 (0x1 << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ -/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ -#define PMC_PCDR0_PID2 (0x1 << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */ -#define PMC_PCDR0_PID3 (0x1 << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */ -#define PMC_PCDR0_PID4 (0x1 << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */ -#define PMC_PCDR0_PID5 (0x1 << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */ -#define PMC_PCDR0_PID6 (0x1 << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */ -#define PMC_PCDR0_PID7 (0x1 << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ -#define PMC_PCDR0_PID8 (0x1 << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ -#define PMC_PCDR0_PID9 (0x1 << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ -#define PMC_PCDR0_PID10 (0x1 << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ -#define PMC_PCDR0_PID11 (0x1 << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ -#define PMC_PCDR0_PID12 (0x1 << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ -#define PMC_PCDR0_PID13 (0x1 << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ -#define PMC_PCDR0_PID14 (0x1 << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ -#define PMC_PCDR0_PID15 (0x1 << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ -#define PMC_PCDR0_PID16 (0x1 << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ -#define PMC_PCDR0_PID17 (0x1 << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ -#define PMC_PCDR0_PID18 (0x1 << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ -#define PMC_PCDR0_PID19 (0x1 << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ -#define PMC_PCDR0_PID20 (0x1 << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ -#define PMC_PCDR0_PID21 (0x1 << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ -#define PMC_PCDR0_PID22 (0x1 << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ -#define PMC_PCDR0_PID23 (0x1 << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ -#define PMC_PCDR0_PID24 (0x1 << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ -#define PMC_PCDR0_PID25 (0x1 << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ -#define PMC_PCDR0_PID26 (0x1 << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ -#define PMC_PCDR0_PID27 (0x1 << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ -#define PMC_PCDR0_PID28 (0x1 << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ -#define PMC_PCDR0_PID29 (0x1 << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ -#define PMC_PCDR0_PID30 (0x1 << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ -#define PMC_PCDR0_PID31 (0x1 << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ -/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ -#define PMC_PCSR0_PID2 (0x1 << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */ -#define PMC_PCSR0_PID3 (0x1 << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */ -#define PMC_PCSR0_PID4 (0x1 << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */ -#define PMC_PCSR0_PID5 (0x1 << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */ -#define PMC_PCSR0_PID6 (0x1 << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */ -#define PMC_PCSR0_PID7 (0x1 << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ -#define PMC_PCSR0_PID8 (0x1 << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ -#define PMC_PCSR0_PID9 (0x1 << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ -#define PMC_PCSR0_PID10 (0x1 << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ -#define PMC_PCSR0_PID11 (0x1 << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ -#define PMC_PCSR0_PID12 (0x1 << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ -#define PMC_PCSR0_PID13 (0x1 << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ -#define PMC_PCSR0_PID14 (0x1 << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ -#define PMC_PCSR0_PID15 (0x1 << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ -#define PMC_PCSR0_PID16 (0x1 << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ -#define PMC_PCSR0_PID17 (0x1 << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ -#define PMC_PCSR0_PID18 (0x1 << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ -#define PMC_PCSR0_PID19 (0x1 << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ -#define PMC_PCSR0_PID20 (0x1 << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ -#define PMC_PCSR0_PID21 (0x1 << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ -#define PMC_PCSR0_PID22 (0x1 << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ -#define PMC_PCSR0_PID23 (0x1 << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ -#define PMC_PCSR0_PID24 (0x1 << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ -#define PMC_PCSR0_PID25 (0x1 << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ -#define PMC_PCSR0_PID26 (0x1 << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ -#define PMC_PCSR0_PID27 (0x1 << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ -#define PMC_PCSR0_PID28 (0x1 << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ -#define PMC_PCSR0_PID29 (0x1 << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ -#define PMC_PCSR0_PID30 (0x1 << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ -#define PMC_PCSR0_PID31 (0x1 << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ -/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ -#define CKGR_MOR_MOSCXTEN (0x1 << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ -#define CKGR_MOR_MOSCXTBY (0x1 << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ -#define CKGR_MOR_WAITMODE (0x1 << 2) /**< \brief (CKGR_MOR) Wait Mode Command */ -#define CKGR_MOR_MOSCRCEN (0x1 << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ -#define CKGR_MOR_MOSCRCF (0x7 << 4) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ -#define CKGR_MOR_MOSCXTST (0xff << 8) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ -#define CKGR_MOR_KEY (0xff << 16) /**< \brief (CKGR_MOR) Password */ -#define CKGR_MOR_MOSCSEL (0x1 << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ -#define CKGR_MOR_CFDEN (0x1 << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ -/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ -#define CKGR_MCFR_MAINF (0xffff << 0) /**< \brief (CKGR_MCFR) Main Clock Frequency */ -#define CKGR_MCFR_MAINFRDY (0x1 << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ -/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ -#define CKGR_PLLAR_DIVA (0xff << 0) /**< \brief (CKGR_PLLAR) Divider */ -#define CKGR_PLLAR_PLLACOUNT (0x3f << 8) /**< \brief (CKGR_PLLAR) PLLA Counter */ -#define CKGR_PLLAR_MULA (0x7ff << 16) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ -#define CKGR_PLLAR_STUCKTO1 (0x1 << 29) /**< \brief (CKGR_PLLAR) */ -/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */ -#define CKGR_PLLBR_DIVB (0xff << 0) /**< \brief (CKGR_PLLBR) Divider */ -#define CKGR_PLLBR_PLLBCOUNT (0x3f << 8) /**< \brief (CKGR_PLLBR) PLLB Counter */ -#define CKGR_PLLBR_MULB (0x7ff << 16) /**< \brief (CKGR_PLLBR) PLLB Multiplier */ -/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ -#define PMC_MCKR_CSS (0x3 << 0) /**< \brief (PMC_MCKR) Master Clock Source Selection */ -#define PMC_MCKR_CSS_SLOW_CLK (0x0 << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ -#define PMC_MCKR_CSS_MAIN_CLK (0x1 << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ -#define PMC_MCKR_CSS_PLLA_CLK (0x2 << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ -#define PMC_MCKR_CSS_PLLB_CLK (0x3 << 0) /**< \brief (PMC_MCKR) PLLB Clock is selected */ -#define PMC_MCKR_PRES (0x7 << 4) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ -#define PMC_MCKR_PRES_CLK (0x0 << 4) /**< \brief (PMC_MCKR) Selected clock */ -#define PMC_MCKR_PRES_CLK_2 (0x1 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ -#define PMC_MCKR_PRES_CLK_4 (0x2 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ -#define PMC_MCKR_PRES_CLK_8 (0x3 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ -#define PMC_MCKR_PRES_CLK_16 (0x4 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ -#define PMC_MCKR_PRES_CLK_32 (0x5 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ -#define PMC_MCKR_PRES_CLK_64 (0x6 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ -#define PMC_MCKR_PLLADIV2 (0x1 << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */ -#define PMC_MCKR_PLLBDIV2 (0x1 << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */ -/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ -#define PMC_USB_USBS (0x1 << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ -#define PMC_USB_USBDIV (0xf << 8) /**< \brief (PMC_USB) Divider for USB Clock. */ -/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ -#define PMC_PCK_CSS (0x7 << 0) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ -#define PMC_PCK_PRES (0x7 << 4) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ -/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ -#define PMC_IER_MOSCXTS (0x1 << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ -#define PMC_IER_LOCKA (0x1 << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ -#define PMC_IER_LOCKB (0x1 << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */ -#define PMC_IER_MCKRDY (0x1 << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ -#define PMC_IER_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ -#define PMC_IER_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ -#define PMC_IER_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ -#define PMC_IER_MOSCSELS (0x1 << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ -#define PMC_IER_MOSCRCS (0x1 << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ -#define PMC_IER_CFDEV (0x1 << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ -/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ -#define PMC_IDR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ -#define PMC_IDR_LOCKA (0x1 << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ -#define PMC_IDR_LOCKB (0x1 << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */ -#define PMC_IDR_MCKRDY (0x1 << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ -#define PMC_IDR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ -#define PMC_IDR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ -#define PMC_IDR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ -#define PMC_IDR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ -#define PMC_IDR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ -#define PMC_IDR_CFDEV (0x1 << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ -/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ -#define PMC_SR_MOSCXTS (0x1 << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ -#define PMC_SR_LOCKA (0x1 << 1) /**< \brief (PMC_SR) PLLA Lock Status */ -#define PMC_SR_LOCKB (0x1 << 2) /**< \brief (PMC_SR) PLLB Lock Status */ -#define PMC_SR_MCKRDY (0x1 << 3) /**< \brief (PMC_SR) Master Clock Status */ -#define PMC_SR_OSCSELS (0x1 << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ -#define PMC_SR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_MOSCSELS (0x1 << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ -#define PMC_SR_MOSCRCS (0x1 << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ -#define PMC_SR_CFDEV (0x1 << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ -#define PMC_SR_CFDS (0x1 << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ -#define PMC_SR_FOS (0x1 << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ -/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ -#define PMC_IMR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ -#define PMC_IMR_LOCKA (0x1 << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ -#define PMC_IMR_LOCKB (0x1 << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */ -#define PMC_IMR_MCKRDY (0x1 << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ -#define PMC_IMR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ -#define PMC_IMR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ -#define PMC_IMR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ -#define PMC_IMR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ -#define PMC_IMR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ -#define PMC_IMR_CFDEV (0x1 << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ -/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ -#define PMC_FSMR_FSTT0 (0x1 << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ -#define PMC_FSMR_FSTT1 (0x1 << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ -#define PMC_FSMR_FSTT2 (0x1 << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ -#define PMC_FSMR_FSTT3 (0x1 << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ -#define PMC_FSMR_FSTT4 (0x1 << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ -#define PMC_FSMR_FSTT5 (0x1 << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ -#define PMC_FSMR_FSTT6 (0x1 << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ -#define PMC_FSMR_FSTT7 (0x1 << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ -#define PMC_FSMR_FSTT8 (0x1 << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ -#define PMC_FSMR_FSTT9 (0x1 << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ -#define PMC_FSMR_FSTT10 (0x1 << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ -#define PMC_FSMR_FSTT11 (0x1 << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ -#define PMC_FSMR_FSTT12 (0x1 << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ -#define PMC_FSMR_FSTT13 (0x1 << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ -#define PMC_FSMR_FSTT14 (0x1 << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ -#define PMC_FSMR_FSTT15 (0x1 << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ -#define PMC_FSMR_RTTAL (0x1 << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ -#define PMC_FSMR_RTCAL (0x1 << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ -#define PMC_FSMR_USBAL (0x1 << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ -#define PMC_FSMR_LPM (0x1 << 20) /**< \brief (PMC_FSMR) Low Power Mode */ -/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ -#define PMC_FSPR_FSTP0 (0x1 << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP1 (0x1 << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP2 (0x1 << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP3 (0x1 << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP4 (0x1 << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP5 (0x1 << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP6 (0x1 << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP7 (0x1 << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP8 (0x1 << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP9 (0x1 << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP10 (0x1 << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP11 (0x1 << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP12 (0x1 << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP13 (0x1 << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP14 (0x1 << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -#define PMC_FSPR_FSTP15 (0x1 << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ -/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ -#define PMC_FOCR_FOCLR (0x1 << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ -/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PMC_WPMR_WPEN (0x1 << 0) /**< \brief (PMC_WPMR) Write Protect Enable */ -#define PMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (PMC_WPMR) Write Protect KEY */ -/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */ -#define PMC_WPSR_WPVS (0x1 << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */ -#define PMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (PMC_WPSR) Write Protect Violation Source */ -/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ -#define PMC_PCER1_PID32 (0x1 << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ -#define PMC_PCER1_PID33 (0x1 << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ -#define PMC_PCER1_PID34 (0x1 << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ -#define PMC_PCER1_PID35 (0x1 << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ -#define PMC_PCER1_PID36 (0x1 << 4) /**< \brief (PMC_PCER1) Peripheral Clock 36 Enable */ -#define PMC_PCER1_PID37 (0x1 << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ -#define PMC_PCER1_PID38 (0x1 << 6) /**< \brief (PMC_PCER1) Peripheral Clock 38 Enable */ -#define PMC_PCER1_PID39 (0x1 << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ -#define PMC_PCER1_PID40 (0x1 << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ -#define PMC_PCER1_PID41 (0x1 << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ -#define PMC_PCER1_PID42 (0x1 << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ -#define PMC_PCER1_PID43 (0x1 << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ -#define PMC_PCER1_PID44 (0x1 << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ -#define PMC_PCER1_PID45 (0x1 << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ -#define PMC_PCER1_PID46 (0x1 << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ -#define PMC_PCER1_PID47 (0x1 << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ -#define PMC_PCER1_PID48 (0x1 << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ -#define PMC_PCER1_PID49 (0x1 << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ -#define PMC_PCER1_PID50 (0x1 << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ -#define PMC_PCER1_PID51 (0x1 << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ -#define PMC_PCER1_PID52 (0x1 << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ -#define PMC_PCER1_PID53 (0x1 << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ -#define PMC_PCER1_PID54 (0x1 << 22) /**< \brief (PMC_PCER1) Peripheral Clock 54 Enable */ -#define PMC_PCER1_PID55 (0x1 << 23) /**< \brief (PMC_PCER1) Peripheral Clock 55 Enable */ -#define PMC_PCER1_PID56 (0x1 << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ -#define PMC_PCER1_PID57 (0x1 << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ -#define PMC_PCER1_PID58 (0x1 << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ -#define PMC_PCER1_PID59 (0x1 << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ -#define PMC_PCER1_PID60 (0x1 << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ -#define PMC_PCER1_PID61 (0x1 << 29) /**< \brief (PMC_PCER1) Peripheral Clock 61 Enable */ -#define PMC_PCER1_PID62 (0x1 << 30) /**< \brief (PMC_PCER1) Peripheral Clock 62 Enable */ -#define PMC_PCER1_PID63 (0x1 << 31) /**< \brief (PMC_PCER1) Peripheral Clock 63 Enable */ -/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ -#define PMC_PCDR1_PID32 (0x1 << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ -#define PMC_PCDR1_PID33 (0x1 << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ -#define PMC_PCDR1_PID34 (0x1 << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ -#define PMC_PCDR1_PID35 (0x1 << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ -#define PMC_PCDR1_PID36 (0x1 << 4) /**< \brief (PMC_PCDR1) Peripheral Clock 36 Disable */ -#define PMC_PCDR1_PID37 (0x1 << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ -#define PMC_PCDR1_PID38 (0x1 << 6) /**< \brief (PMC_PCDR1) Peripheral Clock 38 Disable */ -#define PMC_PCDR1_PID39 (0x1 << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ -#define PMC_PCDR1_PID40 (0x1 << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ -#define PMC_PCDR1_PID41 (0x1 << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ -#define PMC_PCDR1_PID42 (0x1 << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ -#define PMC_PCDR1_PID43 (0x1 << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ -#define PMC_PCDR1_PID44 (0x1 << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ -#define PMC_PCDR1_PID45 (0x1 << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ -#define PMC_PCDR1_PID46 (0x1 << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ -#define PMC_PCDR1_PID47 (0x1 << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ -#define PMC_PCDR1_PID48 (0x1 << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ -#define PMC_PCDR1_PID49 (0x1 << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ -#define PMC_PCDR1_PID50 (0x1 << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ -#define PMC_PCDR1_PID51 (0x1 << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ -#define PMC_PCDR1_PID52 (0x1 << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ -#define PMC_PCDR1_PID53 (0x1 << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ -#define PMC_PCDR1_PID54 (0x1 << 22) /**< \brief (PMC_PCDR1) Peripheral Clock 54 Disable */ -#define PMC_PCDR1_PID55 (0x1 << 23) /**< \brief (PMC_PCDR1) Peripheral Clock 55 Disable */ -#define PMC_PCDR1_PID56 (0x1 << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ -#define PMC_PCDR1_PID57 (0x1 << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ -#define PMC_PCDR1_PID58 (0x1 << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ -#define PMC_PCDR1_PID59 (0x1 << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ -#define PMC_PCDR1_PID60 (0x1 << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ -#define PMC_PCDR1_PID61 (0x1 << 29) /**< \brief (PMC_PCDR1) Peripheral Clock 61 Disable */ -#define PMC_PCDR1_PID62 (0x1 << 30) /**< \brief (PMC_PCDR1) Peripheral Clock 62 Disable */ -#define PMC_PCDR1_PID63 (0x1 << 31) /**< \brief (PMC_PCDR1) Peripheral Clock 63 Disable */ -/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ -#define PMC_PCSR1_PID32 (0x1 << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ -#define PMC_PCSR1_PID33 (0x1 << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ -#define PMC_PCSR1_PID34 (0x1 << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ -#define PMC_PCSR1_PID35 (0x1 << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ -#define PMC_PCSR1_PID36 (0x1 << 4) /**< \brief (PMC_PCSR1) Peripheral Clock 36 Status */ -#define PMC_PCSR1_PID37 (0x1 << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ -#define PMC_PCSR1_PID38 (0x1 << 6) /**< \brief (PMC_PCSR1) Peripheral Clock 38 Status */ -#define PMC_PCSR1_PID39 (0x1 << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ -#define PMC_PCSR1_PID40 (0x1 << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ -#define PMC_PCSR1_PID41 (0x1 << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ -#define PMC_PCSR1_PID42 (0x1 << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ -#define PMC_PCSR1_PID43 (0x1 << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ -#define PMC_PCSR1_PID44 (0x1 << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ -#define PMC_PCSR1_PID45 (0x1 << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ -#define PMC_PCSR1_PID46 (0x1 << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ -#define PMC_PCSR1_PID47 (0x1 << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ -#define PMC_PCSR1_PID48 (0x1 << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ -#define PMC_PCSR1_PID49 (0x1 << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ -#define PMC_PCSR1_PID50 (0x1 << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ -#define PMC_PCSR1_PID51 (0x1 << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ -#define PMC_PCSR1_PID52 (0x1 << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ -#define PMC_PCSR1_PID53 (0x1 << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ -#define PMC_PCSR1_PID54 (0x1 << 22) /**< \brief (PMC_PCSR1) Peripheral Clock 54 Status */ -#define PMC_PCSR1_PID55 (0x1 << 23) /**< \brief (PMC_PCSR1) Peripheral Clock 55 Status */ -#define PMC_PCSR1_PID56 (0x1 << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ -#define PMC_PCSR1_PID57 (0x1 << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ -#define PMC_PCSR1_PID58 (0x1 << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ -#define PMC_PCSR1_PID59 (0x1 << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ -#define PMC_PCSR1_PID60 (0x1 << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ -#define PMC_PCSR1_PID61 (0x1 << 29) /**< \brief (PMC_PCSR1) Peripheral Clock 61 Status */ -#define PMC_PCSR1_PID62 (0x1 << 30) /**< \brief (PMC_PCSR1) Peripheral Clock 62 Status */ -#define PMC_PCSR1_PID63 (0x1 << 31) /**< \brief (PMC_PCSR1) Peripheral Clock 63 Status */ -/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ -#define PMC_OCR_CAL4 (0x7f << 0) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_SEL4 (0x1 << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */ -#define PMC_OCR_CAL8 (0x7f << 8) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_SEL8 (0x1 << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */ -#define PMC_OCR_CAL12 (0x7f << 16) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */ -#define PMC_OCR_SEL12 (0x1 << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_PWM Pulse Width Modulation Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief PwmCh_num hardware registers */ -typedef struct { - RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ - RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ - RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ - RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ - RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ - RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ - RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ - RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ -} PwmCh_num; -/** \brief Pwm hardware registers */ -typedef struct { - RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ - WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ - WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ - RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ - WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ - WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ - RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ - RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ - RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ - RwReg Reserved1[1]; - RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ - RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ - WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ - WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ - WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ - RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ - RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ - RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ - RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ - WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ - WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ - WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ - WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ - RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ - RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ - WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ - RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */ - RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ - RwReg Reserved2[3]; - RwReg PWM_ELxMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ - RwReg Reserved3[11]; - RwReg PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ - RwReg Reserved4[12]; - WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ - RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ - RwReg Reserved5[5]; - RwReg PWM_RPR; /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */ - RwReg PWM_RCR; /**< \brief (Pwm Offset: 0x104) Receive Counter Register */ - RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */ - RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */ - RwReg PWM_RNPR; /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */ - RwReg PWM_RNCR; /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */ - RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */ - RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */ - WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */ - RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */ - RwReg Reserved6[2]; - RwReg PWM_CMP0V; /**< \brief (Pwm Offset: 0x130) PWM Comparison 0 Value Register */ - WoReg PWM_CMP0VUPD; /**< \brief (Pwm Offset: 0x134) PWM Comparison 0 Value Update Register */ - RwReg PWM_CMP0M; /**< \brief (Pwm Offset: 0x138) PWM Comparison 0 Mode Register */ - WoReg PWM_CMP0MUPD; /**< \brief (Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register */ - RwReg PWM_CMP1V; /**< \brief (Pwm Offset: 0x140) PWM Comparison 1 Value Register */ - WoReg PWM_CMP1VUPD; /**< \brief (Pwm Offset: 0x144) PWM Comparison 1 Value Update Register */ - RwReg PWM_CMP1M; /**< \brief (Pwm Offset: 0x148) PWM Comparison 1 Mode Register */ - WoReg PWM_CMP1MUPD; /**< \brief (Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register */ - RwReg PWM_CMP2V; /**< \brief (Pwm Offset: 0x150) PWM Comparison 2 Value Register */ - WoReg PWM_CMP2VUPD; /**< \brief (Pwm Offset: 0x154) PWM Comparison 2 Value Update Register */ - RwReg PWM_CMP2M; /**< \brief (Pwm Offset: 0x158) PWM Comparison 2 Mode Register */ - WoReg PWM_CMP2MUPD; /**< \brief (Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register */ - RwReg PWM_CMP3V; /**< \brief (Pwm Offset: 0x160) PWM Comparison 3 Value Register */ - WoReg PWM_CMP3VUPD; /**< \brief (Pwm Offset: 0x164) PWM Comparison 3 Value Update Register */ - RwReg PWM_CMP3M; /**< \brief (Pwm Offset: 0x168) PWM Comparison 3 Mode Register */ - WoReg PWM_CMP3MUPD; /**< \brief (Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register */ - RwReg PWM_CMP4V; /**< \brief (Pwm Offset: 0x170) PWM Comparison 4 Value Register */ - WoReg PWM_CMP4VUPD; /**< \brief (Pwm Offset: 0x174) PWM Comparison 4 Value Update Register */ - RwReg PWM_CMP4M; /**< \brief (Pwm Offset: 0x178) PWM Comparison 4 Mode Register */ - WoReg PWM_CMP4MUPD; /**< \brief (Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register */ - RwReg PWM_CMP5V; /**< \brief (Pwm Offset: 0x180) PWM Comparison 5 Value Register */ - WoReg PWM_CMP5VUPD; /**< \brief (Pwm Offset: 0x184) PWM Comparison 5 Value Update Register */ - RwReg PWM_CMP5M; /**< \brief (Pwm Offset: 0x188) PWM Comparison 5 Mode Register */ - WoReg PWM_CMP5MUPD; /**< \brief (Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register */ - RwReg PWM_CMP6V; /**< \brief (Pwm Offset: 0x190) PWM Comparison 6 Value Register */ - WoReg PWM_CMP6VUPD; /**< \brief (Pwm Offset: 0x194) PWM Comparison 6 Value Update Register */ - RwReg PWM_CMP6M; /**< \brief (Pwm Offset: 0x198) PWM Comparison 6 Mode Register */ - WoReg PWM_CMP6MUPD; /**< \brief (Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register */ - RwReg PWM_CMP7V; /**< \brief (Pwm Offset: 0x1A0) PWM Comparison 7 Value Register */ - WoReg PWM_CMP7VUPD; /**< \brief (Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register */ - RwReg PWM_CMP7M; /**< \brief (Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register */ - WoReg PWM_CMP7MUPD; /**< \brief (Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register */ - RwReg Reserved7[20]; - PwmCh_num PWM_CH_NUM[4]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ -} Pwm; -#endif /* __ASSEMBLY__ */ -/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ -#define PWM_CLK_DIVA (0xff << 0) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREA (0xf << 8) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -#define PWM_CLK_DIVB (0xff << 16) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREB (0xf << 24) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ -#define PWM_ENA_CHID0 (0x1 << 0) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID1 (0x1 << 1) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID2 (0x1 << 2) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID3 (0x1 << 3) /**< \brief (PWM_ENA) Channel ID */ -/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ -#define PWM_DIS_CHID0 (0x1 << 0) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID1 (0x1 << 1) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID2 (0x1 << 2) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID3 (0x1 << 3) /**< \brief (PWM_DIS) Channel ID */ -/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ -#define PWM_SR_CHID0 (0x1 << 0) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID1 (0x1 << 1) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID2 (0x1 << 2) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID3 (0x1 << 3) /**< \brief (PWM_SR) Channel ID */ -/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ -#define PWM_IER1_CHID0 (0x1 << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ -#define PWM_IER1_CHID1 (0x1 << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ -#define PWM_IER1_CHID2 (0x1 << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ -#define PWM_IER1_CHID3 (0x1 << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ -#define PWM_IER1_FCHID0 (0x1 << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ -#define PWM_IER1_FCHID1 (0x1 << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ -#define PWM_IER1_FCHID2 (0x1 << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ -#define PWM_IER1_FCHID3 (0x1 << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ -/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ -#define PWM_IDR1_CHID0 (0x1 << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ -#define PWM_IDR1_CHID1 (0x1 << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ -#define PWM_IDR1_CHID2 (0x1 << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ -#define PWM_IDR1_CHID3 (0x1 << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ -#define PWM_IDR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ -#define PWM_IDR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ -#define PWM_IDR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ -#define PWM_IDR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ -/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ -#define PWM_IMR1_CHID0 (0x1 << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ -#define PWM_IMR1_CHID1 (0x1 << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ -#define PWM_IMR1_CHID2 (0x1 << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ -#define PWM_IMR1_CHID3 (0x1 << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ -#define PWM_IMR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ -#define PWM_IMR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ -#define PWM_IMR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ -#define PWM_IMR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ -/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ -#define PWM_ISR1_CHID0 (0x1 << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ -#define PWM_ISR1_CHID1 (0x1 << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ -#define PWM_ISR1_CHID2 (0x1 << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ -#define PWM_ISR1_CHID3 (0x1 << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ -#define PWM_ISR1_FCHID0 (0x1 << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ -#define PWM_ISR1_FCHID1 (0x1 << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ -#define PWM_ISR1_FCHID2 (0x1 << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ -#define PWM_ISR1_FCHID3 (0x1 << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ -/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ -#define PWM_SCM_SYNC0 (0x1 << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ -#define PWM_SCM_SYNC1 (0x1 << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ -#define PWM_SCM_SYNC2 (0x1 << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ -#define PWM_SCM_SYNC3 (0x1 << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ -#define PWM_SCM_UPDM (0x3 << 16) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ -#define PWM_SCM_PTRM (0x1 << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */ -#define PWM_SCM_PTRCS (0x7 << 21) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */ -/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ -#define PWM_SCUC_UPDULOCK (0x1 << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ -/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ -#define PWM_SCUP_UPR (0xf << 0) /**< \brief (PWM_SCUP) Update Period */ -#define PWM_SCUP_UPRCNT (0xf << 4) /**< \brief (PWM_SCUP) Update Period Counter */ -/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ -#define PWM_SCUPUPD_UPRUPD (0xf << 0) /**< \brief (PWM_SCUPUPD) Update Period Update */ -/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ -#define PWM_IER2_WRDY (0x1 << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ -#define PWM_IER2_ENDTX (0x1 << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */ -#define PWM_IER2_TXBUFE (0x1 << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */ -#define PWM_IER2_UNRE (0x1 << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ -#define PWM_IER2_CMPM0 (0x1 << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ -#define PWM_IER2_CMPM1 (0x1 << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ -#define PWM_IER2_CMPM2 (0x1 << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ -#define PWM_IER2_CMPM3 (0x1 << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ -#define PWM_IER2_CMPM4 (0x1 << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ -#define PWM_IER2_CMPM5 (0x1 << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ -#define PWM_IER2_CMPM6 (0x1 << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ -#define PWM_IER2_CMPM7 (0x1 << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ -#define PWM_IER2_CMPU0 (0x1 << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ -#define PWM_IER2_CMPU1 (0x1 << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ -#define PWM_IER2_CMPU2 (0x1 << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ -#define PWM_IER2_CMPU3 (0x1 << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ -#define PWM_IER2_CMPU4 (0x1 << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ -#define PWM_IER2_CMPU5 (0x1 << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ -#define PWM_IER2_CMPU6 (0x1 << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ -#define PWM_IER2_CMPU7 (0x1 << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ -/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ -#define PWM_IDR2_WRDY (0x1 << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ -#define PWM_IDR2_ENDTX (0x1 << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */ -#define PWM_IDR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */ -#define PWM_IDR2_UNRE (0x1 << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ -#define PWM_IDR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ -#define PWM_IDR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ -#define PWM_IDR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ -#define PWM_IDR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ -#define PWM_IDR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ -#define PWM_IDR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ -#define PWM_IDR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ -#define PWM_IDR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ -#define PWM_IDR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ -#define PWM_IDR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ -#define PWM_IDR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ -#define PWM_IDR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ -#define PWM_IDR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ -#define PWM_IDR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ -#define PWM_IDR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ -#define PWM_IDR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ -/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ -#define PWM_IMR2_WRDY (0x1 << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ -#define PWM_IMR2_ENDTX (0x1 << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */ -#define PWM_IMR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */ -#define PWM_IMR2_UNRE (0x1 << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ -#define PWM_IMR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ -#define PWM_IMR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ -#define PWM_IMR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ -#define PWM_IMR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ -#define PWM_IMR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ -#define PWM_IMR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ -#define PWM_IMR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ -#define PWM_IMR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ -#define PWM_IMR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ -#define PWM_IMR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ -#define PWM_IMR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ -#define PWM_IMR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ -#define PWM_IMR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ -#define PWM_IMR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ -#define PWM_IMR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ -#define PWM_IMR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ -/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ -#define PWM_ISR2_WRDY (0x1 << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ -#define PWM_ISR2_ENDTX (0x1 << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */ -#define PWM_ISR2_TXBUFE (0x1 << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */ -#define PWM_ISR2_UNRE (0x1 << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ -#define PWM_ISR2_CMPM0 (0x1 << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ -#define PWM_ISR2_CMPM1 (0x1 << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ -#define PWM_ISR2_CMPM2 (0x1 << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ -#define PWM_ISR2_CMPM3 (0x1 << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ -#define PWM_ISR2_CMPM4 (0x1 << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ -#define PWM_ISR2_CMPM5 (0x1 << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ -#define PWM_ISR2_CMPM6 (0x1 << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ -#define PWM_ISR2_CMPM7 (0x1 << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ -#define PWM_ISR2_CMPU0 (0x1 << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ -#define PWM_ISR2_CMPU1 (0x1 << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ -#define PWM_ISR2_CMPU2 (0x1 << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ -#define PWM_ISR2_CMPU3 (0x1 << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ -#define PWM_ISR2_CMPU4 (0x1 << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ -#define PWM_ISR2_CMPU5 (0x1 << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ -#define PWM_ISR2_CMPU6 (0x1 << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ -#define PWM_ISR2_CMPU7 (0x1 << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ -/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ -#define PWM_OOV_OOVH0 (0x1 << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ -#define PWM_OOV_OOVH1 (0x1 << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ -#define PWM_OOV_OOVH2 (0x1 << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ -#define PWM_OOV_OOVH3 (0x1 << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ -#define PWM_OOV_OOVL0 (0x1 << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ -#define PWM_OOV_OOVL1 (0x1 << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ -#define PWM_OOV_OOVL2 (0x1 << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ -#define PWM_OOV_OOVL3 (0x1 << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ -/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ -#define PWM_OS_OSH0 (0x1 << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ -#define PWM_OS_OSH1 (0x1 << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ -#define PWM_OS_OSH2 (0x1 << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ -#define PWM_OS_OSH3 (0x1 << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ -#define PWM_OS_OSL0 (0x1 << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ -#define PWM_OS_OSL1 (0x1 << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ -#define PWM_OS_OSL2 (0x1 << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ -#define PWM_OS_OSL3 (0x1 << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ -/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ -#define PWM_OSS_OSSH0 (0x1 << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSS_OSSH1 (0x1 << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSS_OSSH2 (0x1 << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSS_OSSH3 (0x1 << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSS_OSSL0 (0x1 << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSS_OSSL1 (0x1 << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSS_OSSL2 (0x1 << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSS_OSSL3 (0x1 << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ -#define PWM_OSC_OSCH0 (0x1 << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSC_OSCH1 (0x1 << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSC_OSCH2 (0x1 << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSC_OSCH3 (0x1 << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSC_OSCL0 (0x1 << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSC_OSCL1 (0x1 << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSC_OSCL2 (0x1 << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSC_OSCL3 (0x1 << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ -#define PWM_OSSUPD_OSSUPH0 (0x1 << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSSUPD_OSSUPH1 (0x1 << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSSUPD_OSSUPH2 (0x1 << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSSUPD_OSSUPH3 (0x1 << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSSUPD_OSSUPL0 (0x1 << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSSUPD_OSSUPL1 (0x1 << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSSUPD_OSSUPL2 (0x1 << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSSUPD_OSSUPL3 (0x1 << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ -#define PWM_OSCUPD_OSCUPH0 (0x1 << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSCUPD_OSCUPH1 (0x1 << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSCUPD_OSCUPH2 (0x1 << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSCUPD_OSCUPH3 (0x1 << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSCUPD_OSCUPL0 (0x1 << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSCUPD_OSCUPL1 (0x1 << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSCUPD_OSCUPL2 (0x1 << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSCUPD_OSCUPL3 (0x1 << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ -#define PWM_FMR_FPOL0 (0x1 << 0) /**< \brief (PWM_FMR) Fault 0 Polarity */ -#define PWM_FMR_FPOL1 (0x1 << 1) /**< \brief (PWM_FMR) Fault 1 Polarity */ -#define PWM_FMR_FPOL2 (0x1 << 2) /**< \brief (PWM_FMR) Fault 2 Polarity */ -#define PWM_FMR_FPOL3 (0x1 << 3) /**< \brief (PWM_FMR) Fault 3 Polarity */ -#define PWM_FMR_FMOD0 (0x1 << 8) /**< \brief (PWM_FMR) Fault 0 Activation Mode */ -#define PWM_FMR_FMOD1 (0x1 << 9) /**< \brief (PWM_FMR) Fault 1 Activation Mode */ -#define PWM_FMR_FMOD2 (0x1 << 10) /**< \brief (PWM_FMR) Fault 2 Activation Mode */ -#define PWM_FMR_FMOD3 (0x1 << 11) /**< \brief (PWM_FMR) Fault 3 Activation Mode */ -#define PWM_FMR_FFIL0 (0x1 << 16) /**< \brief (PWM_FMR) Fault 0 Filtering */ -#define PWM_FMR_FFIL1 (0x1 << 17) /**< \brief (PWM_FMR) Fault 1 Filtering */ -#define PWM_FMR_FFIL2 (0x1 << 18) /**< \brief (PWM_FMR) Fault 2 Filtering */ -#define PWM_FMR_FFIL3 (0x1 << 19) /**< \brief (PWM_FMR) Fault 3 Filtering */ -/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ -#define PWM_FSR_FIV0 (0x1 << 0) /**< \brief (PWM_FSR) Fault Input 0 Value */ -#define PWM_FSR_FIV1 (0x1 << 1) /**< \brief (PWM_FSR) Fault Input 1 Value */ -#define PWM_FSR_FIV2 (0x1 << 2) /**< \brief (PWM_FSR) Fault Input 2 Value */ -#define PWM_FSR_FIV3 (0x1 << 3) /**< \brief (PWM_FSR) Fault Input 3 Value */ -#define PWM_FSR_FS0 (0x1 << 8) /**< \brief (PWM_FSR) Fault 0 Status */ -#define PWM_FSR_FS1 (0x1 << 9) /**< \brief (PWM_FSR) Fault 1 Status */ -#define PWM_FSR_FS2 (0x1 << 10) /**< \brief (PWM_FSR) Fault 2 Status */ -#define PWM_FSR_FS3 (0x1 << 11) /**< \brief (PWM_FSR) Fault 3 Status */ -/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ -#define PWM_FCR_FCLR0 (0x1 << 0) /**< \brief (PWM_FCR) Fault 0 Clear */ -#define PWM_FCR_FCLR1 (0x1 << 1) /**< \brief (PWM_FCR) Fault 1 Clear */ -#define PWM_FCR_FCLR2 (0x1 << 2) /**< \brief (PWM_FCR) Fault 2 Clear */ -#define PWM_FCR_FCLR3 (0x1 << 3) /**< \brief (PWM_FCR) Fault 3 Clear */ -/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */ -#define PWM_FPV_FPVH0 (0x1 << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */ -#define PWM_FPV_FPVH1 (0x1 << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */ -#define PWM_FPV_FPVH2 (0x1 << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */ -#define PWM_FPV_FPVH3 (0x1 << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */ -#define PWM_FPV_FPVL0 (0x1 << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */ -#define PWM_FPV_FPVL1 (0x1 << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */ -#define PWM_FPV_FPVL2 (0x1 << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */ -#define PWM_FPV_FPVL3 (0x1 << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */ -/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ -#define PWM_FPE_FPE0 (0xff << 0) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 0 for channel x */ -#define PWM_FPE_FPE1 (0xff << 8) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 1 for channel x */ -#define PWM_FPE_FPE2 (0xff << 16) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 2 for channel x */ -#define PWM_FPE_FPE3 (0xff << 24) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 3 for channel x */ -/* -------- PWM_ELxMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ -#define PWM_ELxMR_CSEL0 (0x1 << 0) /**< \brief (PWM_ELxMR[2]) Comparison 0 Selection */ -#define PWM_ELxMR_CSEL1 (0x1 << 1) /**< \brief (PWM_ELxMR[2]) Comparison 1 Selection */ -#define PWM_ELxMR_CSEL2 (0x1 << 2) /**< \brief (PWM_ELxMR[2]) Comparison 2 Selection */ -#define PWM_ELxMR_CSEL3 (0x1 << 3) /**< \brief (PWM_ELxMR[2]) Comparison 3 Selection */ -#define PWM_ELxMR_CSEL4 (0x1 << 4) /**< \brief (PWM_ELxMR[2]) Comparison 4 Selection */ -#define PWM_ELxMR_CSEL5 (0x1 << 5) /**< \brief (PWM_ELxMR[2]) Comparison 5 Selection */ -#define PWM_ELxMR_CSEL6 (0x1 << 6) /**< \brief (PWM_ELxMR[2]) Comparison 6 Selection */ -#define PWM_ELxMR_CSEL7 (0x1 << 7) /**< \brief (PWM_ELxMR[2]) Comparison 7 Selection */ -/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ -#define PWM_SMMR_GCEN0 (0x1 << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ -#define PWM_SMMR_GCEN1 (0x1 << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ -#define PWM_SMMR_DOWN0 (0x1 << 16) /**< \brief (PWM_SMMR) DOWN Count */ -#define PWM_SMMR_DOWN1 (0x1 << 17) /**< \brief (PWM_SMMR) DOWN Count */ -/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ -#define PWM_WPCR_WPCMD (0x3 << 0) /**< \brief (PWM_WPCR) Write Protect Command */ -#define PWM_WPCR_WPRG0 (0x1 << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ -#define PWM_WPCR_WPRG1 (0x1 << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ -#define PWM_WPCR_WPRG2 (0x1 << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ -#define PWM_WPCR_WPRG3 (0x1 << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ -#define PWM_WPCR_WPRG4 (0x1 << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ -#define PWM_WPCR_WPRG5 (0x1 << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ -#define PWM_WPCR_WPKEY (0xffffff << 8) /**< \brief (PWM_WPCR) Write Protect Key */ -/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ -#define PWM_WPSR_WPSWS0 (0x1 << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS1 (0x1 << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS2 (0x1 << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS3 (0x1 << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS4 (0x1 << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS5 (0x1 << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPVS (0x1 << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ -#define PWM_WPSR_WPHWS0 (0x1 << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS1 (0x1 << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS2 (0x1 << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS3 (0x1 << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS4 (0x1 << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS5 (0x1 << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPVSRC (0xffff << 16) /**< \brief (PWM_WPSR) Write Protect Violation Source */ -/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */ -#define PWM_RPR_RXPTR (0xffffffff << 0) /**< \brief (PWM_RPR) Receive Pointer Register */ -/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */ -#define PWM_RCR_RXCTR (0xffff << 0) /**< \brief (PWM_RCR) Receive Counter Register */ -/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */ -#define PWM_TPR_TXPTR (0xffffffff << 0) /**< \brief (PWM_TPR) Transmit Counter Register */ -/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */ -#define PWM_TCR_TXCTR (0xffff << 0) /**< \brief (PWM_TCR) Transmit Counter Register */ -/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */ -#define PWM_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PWM_RNPR) Receive Next Pointer */ -/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */ -#define PWM_RNCR_RXNCTR (0xffff << 0) /**< \brief (PWM_RNCR) Receive Next Counter */ -/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PWM_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PWM_TNPR) Transmit Next Pointer */ -/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PWM_TNCR_TXNCTR (0xffff << 0) /**< \brief (PWM_TNCR) Transmit Counter Next */ -/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */ -#define PWM_PTCR_RXTEN (0x1 << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */ -#define PWM_PTCR_RXTDIS (0x1 << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */ -#define PWM_PTCR_TXTEN (0x1 << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */ -#define PWM_PTCR_TXTDIS (0x1 << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */ -/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */ -#define PWM_PTSR_RXTEN (0x1 << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */ -#define PWM_PTSR_TXTEN (0x1 << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */ -/* -------- PWM_CMP0V : (PWM Offset: 0x130) PWM Comparison 0 Value Register -------- */ -#define PWM_CMP0V_CV (0xffffff << 0) /**< \brief (PWM_CMP0V) Comparison x Value */ -#define PWM_CMP0V_CVM (0x1 << 24) /**< \brief (PWM_CMP0V) Comparison x Value Mode */ -/* -------- PWM_CMP0VUPD : (PWM Offset: 0x134) PWM Comparison 0 Value Update Register -------- */ -#define PWM_CMP0VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP0VUPD) Comparison x Value Update */ -#define PWM_CMP0VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP0VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP0M : (PWM Offset: 0x138) PWM Comparison 0 Mode Register -------- */ -#define PWM_CMP0M_CEN (0x1 << 0) /**< \brief (PWM_CMP0M) Comparison x Enable */ -#define PWM_CMP0M_CTR (0xf << 4) /**< \brief (PWM_CMP0M) Comparison x Trigger */ -#define PWM_CMP0M_CPR (0xf << 8) /**< \brief (PWM_CMP0M) Comparison x Period */ -#define PWM_CMP0M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP0M) Comparison x Period Counter */ -#define PWM_CMP0M_CUPR (0xf << 16) /**< \brief (PWM_CMP0M) Comparison x Update Period */ -#define PWM_CMP0M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP0M) Comparison x Update Period Counter */ -/* -------- PWM_CMP0MUPD : (PWM Offset: 0x13C) PWM Comparison 0 Mode Update Register -------- */ -#define PWM_CMP0MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP0MUPD) Comparison x Enable Update */ -#define PWM_CMP0MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP0MUPD) Comparison x Trigger Update */ -#define PWM_CMP0MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP0MUPD) Comparison x Period Update */ -#define PWM_CMP0MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP0MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP1V : (PWM Offset: 0x140) PWM Comparison 1 Value Register -------- */ -#define PWM_CMP1V_CV (0xffffff << 0) /**< \brief (PWM_CMP1V) Comparison x Value */ -#define PWM_CMP1V_CVM (0x1 << 24) /**< \brief (PWM_CMP1V) Comparison x Value Mode */ -/* -------- PWM_CMP1VUPD : (PWM Offset: 0x144) PWM Comparison 1 Value Update Register -------- */ -#define PWM_CMP1VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP1VUPD) Comparison x Value Update */ -#define PWM_CMP1VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP1VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP1M : (PWM Offset: 0x148) PWM Comparison 1 Mode Register -------- */ -#define PWM_CMP1M_CEN (0x1 << 0) /**< \brief (PWM_CMP1M) Comparison x Enable */ -#define PWM_CMP1M_CTR (0xf << 4) /**< \brief (PWM_CMP1M) Comparison x Trigger */ -#define PWM_CMP1M_CPR (0xf << 8) /**< \brief (PWM_CMP1M) Comparison x Period */ -#define PWM_CMP1M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP1M) Comparison x Period Counter */ -#define PWM_CMP1M_CUPR (0xf << 16) /**< \brief (PWM_CMP1M) Comparison x Update Period */ -#define PWM_CMP1M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP1M) Comparison x Update Period Counter */ -/* -------- PWM_CMP1MUPD : (PWM Offset: 0x14C) PWM Comparison 1 Mode Update Register -------- */ -#define PWM_CMP1MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP1MUPD) Comparison x Enable Update */ -#define PWM_CMP1MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP1MUPD) Comparison x Trigger Update */ -#define PWM_CMP1MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP1MUPD) Comparison x Period Update */ -#define PWM_CMP1MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP1MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP2V : (PWM Offset: 0x150) PWM Comparison 2 Value Register -------- */ -#define PWM_CMP2V_CV (0xffffff << 0) /**< \brief (PWM_CMP2V) Comparison x Value */ -#define PWM_CMP2V_CVM (0x1 << 24) /**< \brief (PWM_CMP2V) Comparison x Value Mode */ -/* -------- PWM_CMP2VUPD : (PWM Offset: 0x154) PWM Comparison 2 Value Update Register -------- */ -#define PWM_CMP2VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP2VUPD) Comparison x Value Update */ -#define PWM_CMP2VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP2VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP2M : (PWM Offset: 0x158) PWM Comparison 2 Mode Register -------- */ -#define PWM_CMP2M_CEN (0x1 << 0) /**< \brief (PWM_CMP2M) Comparison x Enable */ -#define PWM_CMP2M_CTR (0xf << 4) /**< \brief (PWM_CMP2M) Comparison x Trigger */ -#define PWM_CMP2M_CPR (0xf << 8) /**< \brief (PWM_CMP2M) Comparison x Period */ -#define PWM_CMP2M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP2M) Comparison x Period Counter */ -#define PWM_CMP2M_CUPR (0xf << 16) /**< \brief (PWM_CMP2M) Comparison x Update Period */ -#define PWM_CMP2M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP2M) Comparison x Update Period Counter */ -/* -------- PWM_CMP2MUPD : (PWM Offset: 0x15C) PWM Comparison 2 Mode Update Register -------- */ -#define PWM_CMP2MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP2MUPD) Comparison x Enable Update */ -#define PWM_CMP2MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP2MUPD) Comparison x Trigger Update */ -#define PWM_CMP2MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP2MUPD) Comparison x Period Update */ -#define PWM_CMP2MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP2MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP3V : (PWM Offset: 0x160) PWM Comparison 3 Value Register -------- */ -#define PWM_CMP3V_CV (0xffffff << 0) /**< \brief (PWM_CMP3V) Comparison x Value */ -#define PWM_CMP3V_CVM (0x1 << 24) /**< \brief (PWM_CMP3V) Comparison x Value Mode */ -/* -------- PWM_CMP3VUPD : (PWM Offset: 0x164) PWM Comparison 3 Value Update Register -------- */ -#define PWM_CMP3VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP3VUPD) Comparison x Value Update */ -#define PWM_CMP3VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP3VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP3M : (PWM Offset: 0x168) PWM Comparison 3 Mode Register -------- */ -#define PWM_CMP3M_CEN (0x1 << 0) /**< \brief (PWM_CMP3M) Comparison x Enable */ -#define PWM_CMP3M_CTR (0xf << 4) /**< \brief (PWM_CMP3M) Comparison x Trigger */ -#define PWM_CMP3M_CPR (0xf << 8) /**< \brief (PWM_CMP3M) Comparison x Period */ -#define PWM_CMP3M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP3M) Comparison x Period Counter */ -#define PWM_CMP3M_CUPR (0xf << 16) /**< \brief (PWM_CMP3M) Comparison x Update Period */ -#define PWM_CMP3M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP3M) Comparison x Update Period Counter */ -/* -------- PWM_CMP3MUPD : (PWM Offset: 0x16C) PWM Comparison 3 Mode Update Register -------- */ -#define PWM_CMP3MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP3MUPD) Comparison x Enable Update */ -#define PWM_CMP3MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP3MUPD) Comparison x Trigger Update */ -#define PWM_CMP3MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP3MUPD) Comparison x Period Update */ -#define PWM_CMP3MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP3MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP4V : (PWM Offset: 0x170) PWM Comparison 4 Value Register -------- */ -#define PWM_CMP4V_CV (0xffffff << 0) /**< \brief (PWM_CMP4V) Comparison x Value */ -#define PWM_CMP4V_CVM (0x1 << 24) /**< \brief (PWM_CMP4V) Comparison x Value Mode */ -/* -------- PWM_CMP4VUPD : (PWM Offset: 0x174) PWM Comparison 4 Value Update Register -------- */ -#define PWM_CMP4VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP4VUPD) Comparison x Value Update */ -#define PWM_CMP4VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP4VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP4M : (PWM Offset: 0x178) PWM Comparison 4 Mode Register -------- */ -#define PWM_CMP4M_CEN (0x1 << 0) /**< \brief (PWM_CMP4M) Comparison x Enable */ -#define PWM_CMP4M_CTR (0xf << 4) /**< \brief (PWM_CMP4M) Comparison x Trigger */ -#define PWM_CMP4M_CPR (0xf << 8) /**< \brief (PWM_CMP4M) Comparison x Period */ -#define PWM_CMP4M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP4M) Comparison x Period Counter */ -#define PWM_CMP4M_CUPR (0xf << 16) /**< \brief (PWM_CMP4M) Comparison x Update Period */ -#define PWM_CMP4M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP4M) Comparison x Update Period Counter */ -/* -------- PWM_CMP4MUPD : (PWM Offset: 0x17C) PWM Comparison 4 Mode Update Register -------- */ -#define PWM_CMP4MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP4MUPD) Comparison x Enable Update */ -#define PWM_CMP4MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP4MUPD) Comparison x Trigger Update */ -#define PWM_CMP4MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP4MUPD) Comparison x Period Update */ -#define PWM_CMP4MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP4MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP5V : (PWM Offset: 0x180) PWM Comparison 5 Value Register -------- */ -#define PWM_CMP5V_CV (0xffffff << 0) /**< \brief (PWM_CMP5V) Comparison x Value */ -#define PWM_CMP5V_CVM (0x1 << 24) /**< \brief (PWM_CMP5V) Comparison x Value Mode */ -/* -------- PWM_CMP5VUPD : (PWM Offset: 0x184) PWM Comparison 5 Value Update Register -------- */ -#define PWM_CMP5VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP5VUPD) Comparison x Value Update */ -#define PWM_CMP5VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP5VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP5M : (PWM Offset: 0x188) PWM Comparison 5 Mode Register -------- */ -#define PWM_CMP5M_CEN (0x1 << 0) /**< \brief (PWM_CMP5M) Comparison x Enable */ -#define PWM_CMP5M_CTR (0xf << 4) /**< \brief (PWM_CMP5M) Comparison x Trigger */ -#define PWM_CMP5M_CPR (0xf << 8) /**< \brief (PWM_CMP5M) Comparison x Period */ -#define PWM_CMP5M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP5M) Comparison x Period Counter */ -#define PWM_CMP5M_CUPR (0xf << 16) /**< \brief (PWM_CMP5M) Comparison x Update Period */ -#define PWM_CMP5M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP5M) Comparison x Update Period Counter */ -/* -------- PWM_CMP5MUPD : (PWM Offset: 0x18C) PWM Comparison 5 Mode Update Register -------- */ -#define PWM_CMP5MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP5MUPD) Comparison x Enable Update */ -#define PWM_CMP5MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP5MUPD) Comparison x Trigger Update */ -#define PWM_CMP5MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP5MUPD) Comparison x Period Update */ -#define PWM_CMP5MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP5MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP6V : (PWM Offset: 0x190) PWM Comparison 6 Value Register -------- */ -#define PWM_CMP6V_CV (0xffffff << 0) /**< \brief (PWM_CMP6V) Comparison x Value */ -#define PWM_CMP6V_CVM (0x1 << 24) /**< \brief (PWM_CMP6V) Comparison x Value Mode */ -/* -------- PWM_CMP6VUPD : (PWM Offset: 0x194) PWM Comparison 6 Value Update Register -------- */ -#define PWM_CMP6VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP6VUPD) Comparison x Value Update */ -#define PWM_CMP6VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP6VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP6M : (PWM Offset: 0x198) PWM Comparison 6 Mode Register -------- */ -#define PWM_CMP6M_CEN (0x1 << 0) /**< \brief (PWM_CMP6M) Comparison x Enable */ -#define PWM_CMP6M_CTR (0xf << 4) /**< \brief (PWM_CMP6M) Comparison x Trigger */ -#define PWM_CMP6M_CPR (0xf << 8) /**< \brief (PWM_CMP6M) Comparison x Period */ -#define PWM_CMP6M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP6M) Comparison x Period Counter */ -#define PWM_CMP6M_CUPR (0xf << 16) /**< \brief (PWM_CMP6M) Comparison x Update Period */ -#define PWM_CMP6M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP6M) Comparison x Update Period Counter */ -/* -------- PWM_CMP6MUPD : (PWM Offset: 0x19C) PWM Comparison 6 Mode Update Register -------- */ -#define PWM_CMP6MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP6MUPD) Comparison x Enable Update */ -#define PWM_CMP6MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP6MUPD) Comparison x Trigger Update */ -#define PWM_CMP6MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP6MUPD) Comparison x Period Update */ -#define PWM_CMP6MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP6MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP7V : (PWM Offset: 0x1A0) PWM Comparison 7 Value Register -------- */ -#define PWM_CMP7V_CV (0xffffff << 0) /**< \brief (PWM_CMP7V) Comparison x Value */ -#define PWM_CMP7V_CVM (0x1 << 24) /**< \brief (PWM_CMP7V) Comparison x Value Mode */ -/* -------- PWM_CMP7VUPD : (PWM Offset: 0x1A4) PWM Comparison 7 Value Update Register -------- */ -#define PWM_CMP7VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP7VUPD) Comparison x Value Update */ -#define PWM_CMP7VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP7VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP7M : (PWM Offset: 0x1A8) PWM Comparison 7 Mode Register -------- */ -#define PWM_CMP7M_CEN (0x1 << 0) /**< \brief (PWM_CMP7M) Comparison x Enable */ -#define PWM_CMP7M_CTR (0xf << 4) /**< \brief (PWM_CMP7M) Comparison x Trigger */ -#define PWM_CMP7M_CPR (0xf << 8) /**< \brief (PWM_CMP7M) Comparison x Period */ -#define PWM_CMP7M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP7M) Comparison x Period Counter */ -#define PWM_CMP7M_CUPR (0xf << 16) /**< \brief (PWM_CMP7M) Comparison x Update Period */ -#define PWM_CMP7M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP7M) Comparison x Update Period Counter */ -/* -------- PWM_CMP7MUPD : (PWM Offset: 0x1AC) PWM Comparison 7 Mode Update Register -------- */ -#define PWM_CMP7MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP7MUPD) Comparison x Enable Update */ -#define PWM_CMP7MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP7MUPD) Comparison x Trigger Update */ -#define PWM_CMP7MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP7MUPD) Comparison x Period Update */ -#define PWM_CMP7MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP7MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMR0 : (PWM Offset: 0x200) PWM Channel Mode Register (ch_num = 0) -------- */ -#define PWM_CMR0_CPRE (0xf << 0) /**< \brief (PWM_CMR0) Channel Pre-scaler */ -#define PWM_CMR0_CALG (0x1 << 8) /**< \brief (PWM_CMR0) Channel Alignment */ -#define PWM_CMR0_CPOL (0x1 << 9) /**< \brief (PWM_CMR0) Channel Polarity */ -#define PWM_CMR0_CES (0x1 << 10) /**< \brief (PWM_CMR0) Counter Event Selection */ -#define PWM_CMR0_DTE (0x1 << 16) /**< \brief (PWM_CMR0) Dead-Time Generator Enable */ -#define PWM_CMR0_DTHI (0x1 << 17) /**< \brief (PWM_CMR0) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR0_DTLI (0x1 << 18) /**< \brief (PWM_CMR0) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY0 : (PWM Offset: 0x204) PWM Channel Duty Cycle Register (ch_num = 0) -------- */ -#define PWM_CDTY0_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY0) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD0 : (PWM Offset: 0x208) PWM Channel Duty Cycle Update Register (ch_num = 0) -------- */ -#define PWM_CDTYUPD0_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD0) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD0 : (PWM Offset: 0x20C) PWM Channel Period Register (ch_num = 0) -------- */ -#define PWM_CPRD0_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD0) Channel Period */ -/* -------- PWM_CPRDUPD0 : (PWM Offset: 0x210) PWM Channel Period Update Register (ch_num = 0) -------- */ -#define PWM_CPRDUPD0_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD0) Channel Period Update */ -/* -------- PWM_CCNT0 : (PWM Offset: 0x214) PWM Channel Counter Register (ch_num = 0) -------- */ -#define PWM_CCNT0_CNT (0xffffff << 0) /**< \brief (PWM_CCNT0) Channel Counter Register */ -/* -------- PWM_DT0 : (PWM Offset: 0x218) PWM Channel Dead Time Register (ch_num = 0) -------- */ -#define PWM_DT0_DTH (0xffff << 0) /**< \brief (PWM_DT0) Dead-Time Value for PWMHx Output */ -#define PWM_DT0_DTL (0xffff << 16) /**< \brief (PWM_DT0) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD0 : (PWM Offset: 0x21C) PWM Channel Dead Time Update Register (ch_num = 0) -------- */ -#define PWM_DTUPD0_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD0_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR1 : (PWM Offset: 0x220) PWM Channel Mode Register (ch_num = 1) -------- */ -#define PWM_CMR1_CPRE (0xf << 0) /**< \brief (PWM_CMR1) Channel Pre-scaler */ -#define PWM_CMR1_CALG (0x1 << 8) /**< \brief (PWM_CMR1) Channel Alignment */ -#define PWM_CMR1_CPOL (0x1 << 9) /**< \brief (PWM_CMR1) Channel Polarity */ -#define PWM_CMR1_CES (0x1 << 10) /**< \brief (PWM_CMR1) Counter Event Selection */ -#define PWM_CMR1_DTE (0x1 << 16) /**< \brief (PWM_CMR1) Dead-Time Generator Enable */ -#define PWM_CMR1_DTHI (0x1 << 17) /**< \brief (PWM_CMR1) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR1_DTLI (0x1 << 18) /**< \brief (PWM_CMR1) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY1 : (PWM Offset: 0x224) PWM Channel Duty Cycle Register (ch_num = 1) -------- */ -#define PWM_CDTY1_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY1) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD1 : (PWM Offset: 0x228) PWM Channel Duty Cycle Update Register (ch_num = 1) -------- */ -#define PWM_CDTYUPD1_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD1) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD1 : (PWM Offset: 0x22C) PWM Channel Period Register (ch_num = 1) -------- */ -#define PWM_CPRD1_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD1) Channel Period */ -/* -------- PWM_CPRDUPD1 : (PWM Offset: 0x230) PWM Channel Period Update Register (ch_num = 1) -------- */ -#define PWM_CPRDUPD1_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD1) Channel Period Update */ -/* -------- PWM_CCNT1 : (PWM Offset: 0x234) PWM Channel Counter Register (ch_num = 1) -------- */ -#define PWM_CCNT1_CNT (0xffffff << 0) /**< \brief (PWM_CCNT1) Channel Counter Register */ -/* -------- PWM_DT1 : (PWM Offset: 0x238) PWM Channel Dead Time Register (ch_num = 1) -------- */ -#define PWM_DT1_DTH (0xffff << 0) /**< \brief (PWM_DT1) Dead-Time Value for PWMHx Output */ -#define PWM_DT1_DTL (0xffff << 16) /**< \brief (PWM_DT1) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD1 : (PWM Offset: 0x23C) PWM Channel Dead Time Update Register (ch_num = 1) -------- */ -#define PWM_DTUPD1_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD1_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR2 : (PWM Offset: 0x240) PWM Channel Mode Register (ch_num = 2) -------- */ -#define PWM_CMR2_CPRE (0xf << 0) /**< \brief (PWM_CMR2) Channel Pre-scaler */ -#define PWM_CMR2_CALG (0x1 << 8) /**< \brief (PWM_CMR2) Channel Alignment */ -#define PWM_CMR2_CPOL (0x1 << 9) /**< \brief (PWM_CMR2) Channel Polarity */ -#define PWM_CMR2_CES (0x1 << 10) /**< \brief (PWM_CMR2) Counter Event Selection */ -#define PWM_CMR2_DTE (0x1 << 16) /**< \brief (PWM_CMR2) Dead-Time Generator Enable */ -#define PWM_CMR2_DTHI (0x1 << 17) /**< \brief (PWM_CMR2) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR2_DTLI (0x1 << 18) /**< \brief (PWM_CMR2) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY2 : (PWM Offset: 0x244) PWM Channel Duty Cycle Register (ch_num = 2) -------- */ -#define PWM_CDTY2_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY2) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD2 : (PWM Offset: 0x248) PWM Channel Duty Cycle Update Register (ch_num = 2) -------- */ -#define PWM_CDTYUPD2_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD2) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD2 : (PWM Offset: 0x24C) PWM Channel Period Register (ch_num = 2) -------- */ -#define PWM_CPRD2_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD2) Channel Period */ -/* -------- PWM_CPRDUPD2 : (PWM Offset: 0x250) PWM Channel Period Update Register (ch_num = 2) -------- */ -#define PWM_CPRDUPD2_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD2) Channel Period Update */ -/* -------- PWM_CCNT2 : (PWM Offset: 0x254) PWM Channel Counter Register (ch_num = 2) -------- */ -#define PWM_CCNT2_CNT (0xffffff << 0) /**< \brief (PWM_CCNT2) Channel Counter Register */ -/* -------- PWM_DT2 : (PWM Offset: 0x258) PWM Channel Dead Time Register (ch_num = 2) -------- */ -#define PWM_DT2_DTH (0xffff << 0) /**< \brief (PWM_DT2) Dead-Time Value for PWMHx Output */ -#define PWM_DT2_DTL (0xffff << 16) /**< \brief (PWM_DT2) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD2 : (PWM Offset: 0x25C) PWM Channel Dead Time Update Register (ch_num = 2) -------- */ -#define PWM_DTUPD2_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD2_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR3 : (PWM Offset: 0x260) PWM Channel Mode Register (ch_num = 3) -------- */ -#define PWM_CMR3_CPRE (0xf << 0) /**< \brief (PWM_CMR3) Channel Pre-scaler */ -#define PWM_CMR3_CALG (0x1 << 8) /**< \brief (PWM_CMR3) Channel Alignment */ -#define PWM_CMR3_CPOL (0x1 << 9) /**< \brief (PWM_CMR3) Channel Polarity */ -#define PWM_CMR3_CES (0x1 << 10) /**< \brief (PWM_CMR3) Counter Event Selection */ -#define PWM_CMR3_DTE (0x1 << 16) /**< \brief (PWM_CMR3) Dead-Time Generator Enable */ -#define PWM_CMR3_DTHI (0x1 << 17) /**< \brief (PWM_CMR3) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR3_DTLI (0x1 << 18) /**< \brief (PWM_CMR3) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY3 : (PWM Offset: 0x264) PWM Channel Duty Cycle Register (ch_num = 3) -------- */ -#define PWM_CDTY3_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY3) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD3 : (PWM Offset: 0x268) PWM Channel Duty Cycle Update Register (ch_num = 3) -------- */ -#define PWM_CDTYUPD3_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD3) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD3 : (PWM Offset: 0x26C) PWM Channel Period Register (ch_num = 3) -------- */ -#define PWM_CPRD3_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD3) Channel Period */ -/* -------- PWM_CPRDUPD3 : (PWM Offset: 0x270) PWM Channel Period Update Register (ch_num = 3) -------- */ -#define PWM_CPRDUPD3_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD3) Channel Period Update */ -/* -------- PWM_CCNT3 : (PWM Offset: 0x274) PWM Channel Counter Register (ch_num = 3) -------- */ -#define PWM_CCNT3_CNT (0xffffff << 0) /**< \brief (PWM_CCNT3) Channel Counter Register */ -/* -------- PWM_DT3 : (PWM Offset: 0x278) PWM Channel Dead Time Register (ch_num = 3) -------- */ -#define PWM_DT3_DTH (0xffff << 0) /**< \brief (PWM_DT3) Dead-Time Value for PWMHx Output */ -#define PWM_DT3_DTL (0xffff << 16) /**< \brief (PWM_DT3) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD3 : (PWM Offset: 0x27C) PWM Channel Dead Time Update Register (ch_num = 3) -------- */ -#define PWM_DTUPD3_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD3_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMLx Output */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Reset Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RSTC Reset Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rstc hardware registers */ -typedef struct { - WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ - RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ - RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ -} Rstc; -#endif /* __ASSEMBLY__ */ -/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ -#define RSTC_CR_PROCRST (0x1 << 0) /**< \brief (RSTC_CR) Processor Reset */ -#define RSTC_CR_PERRST (0x1 << 2) /**< \brief (RSTC_CR) Peripheral Reset */ -#define RSTC_CR_EXTRST (0x1 << 3) /**< \brief (RSTC_CR) External Reset */ -#define RSTC_CR_KEY (0xff << 24) /**< \brief (RSTC_CR) Password */ -/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ -#define RSTC_SR_URSTS (0x1 << 0) /**< \brief (RSTC_SR) User Reset Status */ -#define RSTC_SR_RSTTYP (0x7 << 8) /**< \brief (RSTC_SR) Reset Type */ -#define RSTC_SR_NRSTL (0x1 << 16) /**< \brief (RSTC_SR) NRST Pin Level */ -#define RSTC_SR_SRCMP (0x1 << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ -/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ -#define RSTC_MR_URSTEN (0x1 << 0) /**< \brief (RSTC_MR) User Reset Enable */ -#define RSTC_MR_URSTIEN (0x1 << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ -#define RSTC_MR_ERSTL (0xf << 8) /**< \brief (RSTC_MR) External Reset Length */ -#define RSTC_MR_KEY (0xff << 24) /**< \brief (RSTC_MR) Password */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Clock */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RTC Real-time Clock */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtc hardware registers */ -typedef struct { - RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ - RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ - RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ - RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ - RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ - RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ - RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ - WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ - WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ - WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ - RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ - RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ -} Rtc; -#endif /* __ASSEMBLY__ */ -/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ -#define RTC_CR_UPDTIM (0x1 << 0) /**< \brief (RTC_CR) Update Request Time Register */ -#define RTC_CR_UPDCAL (0x1 << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ -#define RTC_CR_TIMEVSEL (0x3 << 8) /**< \brief (RTC_CR) Time Event Selection */ -#define RTC_CR_TIMEVSEL_MINUTE (0x0 << 8) /**< \brief (RTC_CR) Minute change. */ -#define RTC_CR_TIMEVSEL_HOUR (0x1 << 8) /**< \brief (RTC_CR) Hour change. */ -#define RTC_CR_TIMEVSEL_DAY24 (0x2 << 8) /**< \brief (RTC_CR) Every day at midnight. */ -#define RTC_CR_TIMEVSEL_DAY12 (0x3 << 8) /**< \brief (RTC_CR) Every day at noon. */ -#define RTC_CR_CALEVSEL (0x3 << 16) /**< \brief (RTC_CR) Calendar Event Selection */ -#define RTC_CR_CALEVSEL_WEEK (0x0 << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00). */ -#define RTC_CR_CALEVSEL_MONTH (0x1 << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00). */ -/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ -#define RTC_MR_HRMOD (0x1 << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ -/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ -#define RTC_TIMR_SEC (0x7f << 0) /**< \brief (RTC_TIMR) Current Second */ -#define RTC_TIMR_MIN (0x7f << 8) /**< \brief (RTC_TIMR) Current Minute */ -#define RTC_TIMR_HOUR (0x3f << 16) /**< \brief (RTC_TIMR) Current Hour */ -#define RTC_TIMR_AMPM (0x1 << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ -/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ -#define RTC_CALR_CENT (0x7f << 0) /**< \brief (RTC_CALR) Current Century */ -#define RTC_CALR_YEAR (0xff << 8) /**< \brief (RTC_CALR) Current Year */ -#define RTC_CALR_MONTH (0x1f << 16) /**< \brief (RTC_CALR) Current Month */ -#define RTC_CALR_DAY (0x7 << 21) /**< \brief (RTC_CALR) Current Day in Current Week */ -#define RTC_CALR_DATE (0x3f << 24) /**< \brief (RTC_CALR) Current Day in Current Month */ -/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ -#define RTC_TIMALR_SEC (0x7f << 0) /**< \brief (RTC_TIMALR) Second Alarm */ -#define RTC_TIMALR_SECEN (0x1 << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ -#define RTC_TIMALR_MIN (0x7f << 8) /**< \brief (RTC_TIMALR) Minute Alarm */ -#define RTC_TIMALR_MINEN (0x1 << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ -#define RTC_TIMALR_HOUR (0x3f << 16) /**< \brief (RTC_TIMALR) Hour Alarm */ -#define RTC_TIMALR_AMPM (0x1 << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ -#define RTC_TIMALR_HOUREN (0x1 << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ -/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ -#define RTC_CALALR_MONTH (0x1f << 16) /**< \brief (RTC_CALALR) Month Alarm */ -#define RTC_CALALR_MTHEN (0x1 << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ -#define RTC_CALALR_DATE (0x3f << 24) /**< \brief (RTC_CALALR) Date Alarm */ -#define RTC_CALALR_DATEEN (0x1 << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ -/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ -#define RTC_SR_ACKUPD (0x1 << 0) /**< \brief (RTC_SR) Acknowledge for Update */ -#define RTC_SR_ALARM (0x1 << 1) /**< \brief (RTC_SR) Alarm Flag */ -#define RTC_SR_SEC (0x1 << 2) /**< \brief (RTC_SR) Second Event */ -#define RTC_SR_TIMEV (0x1 << 3) /**< \brief (RTC_SR) Time Event */ -#define RTC_SR_CALEV (0x1 << 4) /**< \brief (RTC_SR) Calendar Event */ -/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ -#define RTC_SCCR_ACKCLR (0x1 << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ -#define RTC_SCCR_ALRCLR (0x1 << 1) /**< \brief (RTC_SCCR) Alarm Clear */ -#define RTC_SCCR_SECCLR (0x1 << 2) /**< \brief (RTC_SCCR) Second Clear */ -#define RTC_SCCR_TIMCLR (0x1 << 3) /**< \brief (RTC_SCCR) Time Clear */ -#define RTC_SCCR_CALCLR (0x1 << 4) /**< \brief (RTC_SCCR) Calendar Clear */ -/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ -#define RTC_IER_ACKEN (0x1 << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ -#define RTC_IER_ALREN (0x1 << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ -#define RTC_IER_SECEN (0x1 << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ -#define RTC_IER_TIMEN (0x1 << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ -#define RTC_IER_CALEN (0x1 << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ -/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ -#define RTC_IDR_ACKDIS (0x1 << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ -#define RTC_IDR_ALRDIS (0x1 << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ -#define RTC_IDR_SECDIS (0x1 << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ -#define RTC_IDR_TIMDIS (0x1 << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ -#define RTC_IDR_CALDIS (0x1 << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ -/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ -#define RTC_IMR_ACK (0x1 << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ -#define RTC_IMR_ALR (0x1 << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ -#define RTC_IMR_SEC (0x1 << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ -#define RTC_IMR_TIM (0x1 << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ -#define RTC_IMR_CAL (0x1 << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ -/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ -#define RTC_VER_NVTIM (0x1 << 0) /**< \brief (RTC_VER) Non-valid Time */ -#define RTC_VER_NVCAL (0x1 << 1) /**< \brief (RTC_VER) Non-valid Calendar */ -#define RTC_VER_NVTIMALR (0x1 << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ -#define RTC_VER_NVCALALR (0x1 << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_RTT Real-time Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtt hardware registers */ -typedef struct { - RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ - RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ - RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ - RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ -} Rtt; -#endif /* __ASSEMBLY__ */ -/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ -#define RTT_MR_RTPRES (0xffff << 0) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ -#define RTT_MR_ALMIEN (0x1 << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ -#define RTT_MR_RTTINCIEN (0x1 << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ -#define RTT_MR_RTTRST (0x1 << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ -/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ -#define RTT_AR_ALMV (0xffffffff << 0) /**< \brief (RTT_AR) Alarm Value */ -/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ -#define RTT_VR_CRTV (0xffffffff << 0) /**< \brief (RTT_VR) Current Real-time Value */ -/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ -#define RTT_SR_ALMS (0x1 << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ -#define RTT_SR_RTTINC (0x1 << 1) /**< \brief (RTT_SR) Real-time Timer Increment */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Static Memory Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SMC Static Memory Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief SmcCs_number hardware registers */ -typedef struct { - RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ - RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ - RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ - RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */ -} SmcCs_number; -/** \brief Smc hardware registers */ -typedef struct { - SmcCs_number SMC_CS_NUMBER[5]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 4 */ - RwReg Reserved1[12]; - RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ - WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ - WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ - RwReg Reserved2[22]; - RwReg SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */ - RoReg SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */ -} Smc; -#endif /* __ASSEMBLY__ */ -/* -------- SMC_SETUP0 : (SMC Offset: 0x0) SMC Setup Register (CS_number = 0) -------- */ -#define SMC_SETUP0_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP0) NWE Setup Length */ -#define SMC_SETUP0_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP0) NCS Setup Length in WRITE Access */ -#define SMC_SETUP0_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP0) NRD Setup Length */ -#define SMC_SETUP0_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP0) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE0 : (SMC Offset: 0x4) SMC Pulse Register (CS_number = 0) -------- */ -#define SMC_PULSE0_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE0) NWE Pulse Length */ -#define SMC_PULSE0_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE0) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE0_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE0) NRD Pulse Length */ -#define SMC_PULSE0_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE0) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE0 : (SMC Offset: 0x8) SMC Cycle Register (CS_number = 0) -------- */ -#define SMC_CYCLE0_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE0) Total Write Cycle Length */ -#define SMC_CYCLE0_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE0) Total Read Cycle Length */ -/* -------- SMC_MODE0 : (SMC Offset: 0xC) SMC Mode Register (CS_number = 0) -------- */ -#define SMC_MODE0_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE0) NWAIT Mode */ -#define SMC_MODE0_DBW (0x3 << 12) /**< \brief (SMC_MODE0) Data Bus Width */ -#define SMC_MODE0_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE0) Data Float Time */ -#define SMC_MODE0_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE0) TDF Optimization */ -#define SMC_MODE0_PMEN (0x1 << 24) /**< \brief (SMC_MODE0) Page Mode Enabled */ -#define SMC_MODE0_PS (0x3 << 28) /**< \brief (SMC_MODE0) Page Size */ -/* -------- SMC_SETUP1 : (SMC Offset: 0x10) SMC Setup Register (CS_number = 1) -------- */ -#define SMC_SETUP1_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP1) NWE Setup Length */ -#define SMC_SETUP1_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP1) NCS Setup Length in WRITE Access */ -#define SMC_SETUP1_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP1) NRD Setup Length */ -#define SMC_SETUP1_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP1) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE1 : (SMC Offset: 0x14) SMC Pulse Register (CS_number = 1) -------- */ -#define SMC_PULSE1_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE1) NWE Pulse Length */ -#define SMC_PULSE1_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE1) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE1_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE1) NRD Pulse Length */ -#define SMC_PULSE1_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE1) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE1 : (SMC Offset: 0x18) SMC Cycle Register (CS_number = 1) -------- */ -#define SMC_CYCLE1_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE1) Total Write Cycle Length */ -#define SMC_CYCLE1_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE1) Total Read Cycle Length */ -/* -------- SMC_MODE1 : (SMC Offset: 0x1C) SMC Mode Register (CS_number = 1) -------- */ -#define SMC_MODE1_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE1) NWAIT Mode */ -#define SMC_MODE1_DBW (0x3 << 12) /**< \brief (SMC_MODE1) Data Bus Width */ -#define SMC_MODE1_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE1) Data Float Time */ -#define SMC_MODE1_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE1) TDF Optimization */ -#define SMC_MODE1_PMEN (0x1 << 24) /**< \brief (SMC_MODE1) Page Mode Enabled */ -#define SMC_MODE1_PS (0x3 << 28) /**< \brief (SMC_MODE1) Page Size */ -/* -------- SMC_SETUP2 : (SMC Offset: 0x20) SMC Setup Register (CS_number = 2) -------- */ -#define SMC_SETUP2_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP2) NWE Setup Length */ -#define SMC_SETUP2_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP2) NCS Setup Length in WRITE Access */ -#define SMC_SETUP2_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP2) NRD Setup Length */ -#define SMC_SETUP2_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP2) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE2 : (SMC Offset: 0x24) SMC Pulse Register (CS_number = 2) -------- */ -#define SMC_PULSE2_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE2) NWE Pulse Length */ -#define SMC_PULSE2_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE2) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE2_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE2) NRD Pulse Length */ -#define SMC_PULSE2_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE2) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE2 : (SMC Offset: 0x28) SMC Cycle Register (CS_number = 2) -------- */ -#define SMC_CYCLE2_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE2) Total Write Cycle Length */ -#define SMC_CYCLE2_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE2) Total Read Cycle Length */ -/* -------- SMC_MODE2 : (SMC Offset: 0x2C) SMC Mode Register (CS_number = 2) -------- */ -#define SMC_MODE2_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE2) NWAIT Mode */ -#define SMC_MODE2_DBW (0x3 << 12) /**< \brief (SMC_MODE2) Data Bus Width */ -#define SMC_MODE2_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE2) Data Float Time */ -#define SMC_MODE2_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE2) TDF Optimization */ -#define SMC_MODE2_PMEN (0x1 << 24) /**< \brief (SMC_MODE2) Page Mode Enabled */ -#define SMC_MODE2_PS (0x3 << 28) /**< \brief (SMC_MODE2) Page Size */ -/* -------- SMC_SETUP3 : (SMC Offset: 0x30) SMC Setup Register (CS_number = 3) -------- */ -#define SMC_SETUP3_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP3) NWE Setup Length */ -#define SMC_SETUP3_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP3) NCS Setup Length in WRITE Access */ -#define SMC_SETUP3_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP3) NRD Setup Length */ -#define SMC_SETUP3_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP3) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE3 : (SMC Offset: 0x34) SMC Pulse Register (CS_number = 3) -------- */ -#define SMC_PULSE3_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE3) NWE Pulse Length */ -#define SMC_PULSE3_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE3) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE3_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE3) NRD Pulse Length */ -#define SMC_PULSE3_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE3) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE3 : (SMC Offset: 0x38) SMC Cycle Register (CS_number = 3) -------- */ -#define SMC_CYCLE3_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE3) Total Write Cycle Length */ -#define SMC_CYCLE3_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE3) Total Read Cycle Length */ -/* -------- SMC_MODE3 : (SMC Offset: 0x3C) SMC Mode Register (CS_number = 3) -------- */ -#define SMC_MODE3_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE3) NWAIT Mode */ -#define SMC_MODE3_DBW (0x3 << 12) /**< \brief (SMC_MODE3) Data Bus Width */ -#define SMC_MODE3_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE3) Data Float Time */ -#define SMC_MODE3_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE3) TDF Optimization */ -#define SMC_MODE3_PMEN (0x1 << 24) /**< \brief (SMC_MODE3) Page Mode Enabled */ -#define SMC_MODE3_PS (0x3 << 28) /**< \brief (SMC_MODE3) Page Size */ -/* -------- SMC_SETUP4 : (SMC Offset: 0x40) SMC Setup Register (CS_number = 4) -------- */ -#define SMC_SETUP4_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP4) NWE Setup Length */ -#define SMC_SETUP4_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP4) NCS Setup Length in WRITE Access */ -#define SMC_SETUP4_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP4) NRD Setup Length */ -#define SMC_SETUP4_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP4) NCS Setup Length in READ Access */ -/* -------- SMC_PULSE4 : (SMC Offset: 0x44) SMC Pulse Register (CS_number = 4) -------- */ -#define SMC_PULSE4_NWE_PULSE (0x7f << 0) /**< \brief (SMC_PULSE4) NWE Pulse Length */ -#define SMC_PULSE4_NCS_WR_PULSE (0x7f << 8) /**< \brief (SMC_PULSE4) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE4_NRD_PULSE (0x7f << 16) /**< \brief (SMC_PULSE4) NRD Pulse Length */ -#define SMC_PULSE4_NCS_RD_PULSE (0x7f << 24) /**< \brief (SMC_PULSE4) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE4 : (SMC Offset: 0x48) SMC Cycle Register (CS_number = 4) -------- */ -#define SMC_CYCLE4_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE4) Total Write Cycle Length */ -#define SMC_CYCLE4_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE4) Total Read Cycle Length */ -/* -------- SMC_MODE4 : (SMC Offset: 0x4C) SMC Mode Register (CS_number = 4) -------- */ -#define SMC_MODE4_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE4) */ -#define SMC_MODE4_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE4) */ -#define SMC_MODE4_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE4) NWAIT Mode */ -#define SMC_MODE4_DBW (0x3 << 12) /**< \brief (SMC_MODE4) Data Bus Width */ -#define SMC_MODE4_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE4) Data Float Time */ -#define SMC_MODE4_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE4) TDF Optimization */ -#define SMC_MODE4_PMEN (0x1 << 24) /**< \brief (SMC_MODE4) Page Mode Enabled */ -#define SMC_MODE4_PS (0x3 << 28) /**< \brief (SMC_MODE4) Page Size */ -/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ -#define SMC_OCMS_SMSE (0x1 << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ -#define SMC_OCMS_CS0SE (0x1 << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS1SE (0x1 << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS2SE (0x1 << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -#define SMC_OCMS_CS3SE (0x1 << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ -/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ -#define SMC_KEY1_KEY1 (0xffffffff << 0) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ -/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ -#define SMC_KEY2_KEY2 (0xffffffff << 0) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ -/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */ -#define SMC_WPMR_WPEN (0x1 << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ -#define SMC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SMC_WPMR) Write Protect KEY */ -/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */ -#define SMC_WPSR_WPVS (0x1 << 0) /**< \brief (SMC_WPSR) Write Protect Enable */ -#define SMC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SMC_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SPI Serial Peripheral Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Spi hardware registers */ -typedef struct { - WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ - RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ - RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ - WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ - RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ - WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ - WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ - RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ - RwReg Reserved1[4]; - RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ - RwReg Reserved2[41]; - RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ - RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ - RwReg Reserved3[5]; - RwReg SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */ - RwReg SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */ - RwReg SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */ - RwReg SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */ - RwReg SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */ - RwReg SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */ - RwReg SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */ - RwReg SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */ - WoReg SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */ - RoReg SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */ -} Spi; -#endif /* __ASSEMBLY__ */ -/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ -#define SPI_CR_SPIEN (0x1 << 0) /**< \brief (SPI_CR) SPI Enable */ -#define SPI_CR_SPIDIS (0x1 << 1) /**< \brief (SPI_CR) SPI Disable */ -#define SPI_CR_SWRST (0x1 << 7) /**< \brief (SPI_CR) SPI Software Reset */ -#define SPI_CR_LASTXFER (0x1 << 24) /**< \brief (SPI_CR) Last Transfer */ -/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ -#define SPI_MR_MSTR (0x1 << 0) /**< \brief (SPI_MR) Master/Slave Mode */ -#define SPI_MR_PS (0x1 << 1) /**< \brief (SPI_MR) Peripheral Select */ -#define SPI_MR_PS_FIXED (0x0 << 1) /**< \brief (SPI_MR) Fixed Peripheral Select. */ -#define SPI_MR_PS_VARIABLE (0x1 << 1) /**< \brief (SPI_MR) Variable Peripheral Select. */ -#define SPI_MR_PCSDEC (0x1 << 2) /**< \brief (SPI_MR) Chip Select Decode */ -#define SPI_MR_MODFDIS (0x1 << 4) /**< \brief (SPI_MR) Mode Fault Detection */ -#define SPI_MR_WDRBT (0x1 << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ -#define SPI_MR_LLB (0x1 << 7) /**< \brief (SPI_MR) Local Loopback Enable */ -#define SPI_MR_PCS (0xf << 16) /**< \brief (SPI_MR) Peripheral Chip Select */ -#define SPI_MR_DLYBCS (0xff << 24) /**< \brief (SPI_MR) Delay Between Chip Selects */ -/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ -#define SPI_RDR_RD (0xffff << 0) /**< \brief (SPI_RDR) Receive Data */ -#define SPI_RDR_PCS (0xf << 16) /**< \brief (SPI_RDR) Peripheral Chip Select */ -/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ -#define SPI_TDR_TD (0xffff << 0) /**< \brief (SPI_TDR) Transmit Data */ -#define SPI_TDR_PCS (0xf << 16) /**< \brief (SPI_TDR) Peripheral Chip Select */ -#define SPI_TDR_LASTXFER (0x1 << 24) /**< \brief (SPI_TDR) Last Transfer */ -/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ -#define SPI_SR_RDRF (0x1 << 0) /**< \brief (SPI_SR) Receive Data Register Full */ -#define SPI_SR_TDRE (0x1 << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ -#define SPI_SR_MODF (0x1 << 2) /**< \brief (SPI_SR) Mode Fault Error */ -#define SPI_SR_OVRES (0x1 << 3) /**< \brief (SPI_SR) Overrun Error Status */ -#define SPI_SR_ENDRX (0x1 << 4) /**< \brief (SPI_SR) End of RX buffer */ -#define SPI_SR_ENDTX (0x1 << 5) /**< \brief (SPI_SR) End of TX buffer */ -#define SPI_SR_RXBUFF (0x1 << 6) /**< \brief (SPI_SR) RX Buffer Full */ -#define SPI_SR_TXBUFE (0x1 << 7) /**< \brief (SPI_SR) TX Buffer Empty */ -#define SPI_SR_NSSR (0x1 << 8) /**< \brief (SPI_SR) NSS Rising */ -#define SPI_SR_TXEMPTY (0x1 << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ -#define SPI_SR_UNDES (0x1 << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ -#define SPI_SR_SPIENS (0x1 << 16) /**< \brief (SPI_SR) SPI Enable Status */ -/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ -#define SPI_IER_RDRF (0x1 << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ -#define SPI_IER_TDRE (0x1 << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ -#define SPI_IER_MODF (0x1 << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ -#define SPI_IER_OVRES (0x1 << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ -#define SPI_IER_ENDRX (0x1 << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */ -#define SPI_IER_ENDTX (0x1 << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */ -#define SPI_IER_RXBUFF (0x1 << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */ -#define SPI_IER_TXBUFE (0x1 << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */ -#define SPI_IER_NSSR (0x1 << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ -#define SPI_IER_TXEMPTY (0x1 << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ -#define SPI_IER_UNDES (0x1 << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ -/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ -#define SPI_IDR_RDRF (0x1 << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ -#define SPI_IDR_TDRE (0x1 << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ -#define SPI_IDR_MODF (0x1 << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ -#define SPI_IDR_OVRES (0x1 << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ -#define SPI_IDR_ENDRX (0x1 << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */ -#define SPI_IDR_ENDTX (0x1 << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */ -#define SPI_IDR_RXBUFF (0x1 << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */ -#define SPI_IDR_TXBUFE (0x1 << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SPI_IDR_NSSR (0x1 << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ -#define SPI_IDR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ -#define SPI_IDR_UNDES (0x1 << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ -/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ -#define SPI_IMR_RDRF (0x1 << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ -#define SPI_IMR_TDRE (0x1 << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ -#define SPI_IMR_MODF (0x1 << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ -#define SPI_IMR_OVRES (0x1 << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ -#define SPI_IMR_ENDRX (0x1 << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */ -#define SPI_IMR_ENDTX (0x1 << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */ -#define SPI_IMR_RXBUFF (0x1 << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */ -#define SPI_IMR_TXBUFE (0x1 << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SPI_IMR_NSSR (0x1 << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ -#define SPI_IMR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ -#define SPI_IMR_UNDES (0x1 << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ -/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ -#define SPI_CSR_CPOL (0x1 << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ -#define SPI_CSR_NCPHA (0x1 << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ -#define SPI_CSR_CSNAAT (0x1 << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_CSAAT (0x1 << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_BITS (0xf << 4) /**< \brief (SPI_CSR[4]) Bits Per Transfer (See the (Note:) below the register table; Section 9.9 "SPI Chip Select Register" on page 35.) */ -#define SPI_CSR_BITS_8 (0x0 << 4) /**< \brief (SPI_CSR[4]) 8 */ -#define SPI_CSR_BITS_9 (0x1 << 4) /**< \brief (SPI_CSR[4]) 9 */ -#define SPI_CSR_BITS_10 (0x2 << 4) /**< \brief (SPI_CSR[4]) 10 */ -#define SPI_CSR_BITS_11 (0x3 << 4) /**< \brief (SPI_CSR[4]) 11 */ -#define SPI_CSR_BITS_12 (0x4 << 4) /**< \brief (SPI_CSR[4]) 12 */ -#define SPI_CSR_BITS_13 (0x5 << 4) /**< \brief (SPI_CSR[4]) 13 */ -#define SPI_CSR_BITS_14 (0x6 << 4) /**< \brief (SPI_CSR[4]) 14 */ -#define SPI_CSR_BITS_15 (0x7 << 4) /**< \brief (SPI_CSR[4]) 15 */ -#define SPI_CSR_BITS_16 (0x8 << 4) /**< \brief (SPI_CSR[4]) 16 */ -#define SPI_CSR_SCBR (0xff << 8) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ -#define SPI_CSR_DLYBS (0xff << 16) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ -#define SPI_CSR_DLYBCT (0xff << 24) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ -/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ -#define SPI_WPMR_SPIWPEN (0x1 << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */ -#define SPI_WPMR_SPIWPKEY (0xffffff << 8) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */ -/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ -#define SPI_WPSR_SPIWPVS (0x7 << 0) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */ -#define SPI_WPSR_SPIWPVSRC (0xff << 8) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */ -/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */ -#define SPI_RPR_RXPTR (0xffffffff << 0) /**< \brief (SPI_RPR) Receive Pointer Register */ -/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */ -#define SPI_RCR_RXCTR (0xffff << 0) /**< \brief (SPI_RCR) Receive Counter Register */ -/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */ -#define SPI_TPR_TXPTR (0xffffffff << 0) /**< \brief (SPI_TPR) Transmit Counter Register */ -/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */ -#define SPI_TCR_TXCTR (0xffff << 0) /**< \brief (SPI_TCR) Transmit Counter Register */ -/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */ -#define SPI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SPI_RNPR) Receive Next Pointer */ -/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */ -#define SPI_RNCR_RXNCTR (0xffff << 0) /**< \brief (SPI_RNCR) Receive Next Counter */ -/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define SPI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SPI_TNPR) Transmit Next Pointer */ -/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define SPI_TNCR_TXNCTR (0xffff << 0) /**< \brief (SPI_TNCR) Transmit Counter Next */ -/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */ -#define SPI_PTCR_RXTEN (0x1 << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */ -#define SPI_PTCR_RXTDIS (0x1 << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */ -#define SPI_PTCR_TXTEN (0x1 << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */ -#define SPI_PTCR_TXTDIS (0x1 << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */ -/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */ -#define SPI_PTSR_RXTEN (0x1 << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */ -#define SPI_PTSR_TXTEN (0x1 << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SSC Synchronous Serial Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Ssc hardware registers */ -typedef struct { - WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ - RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ - RwReg Reserved1[2]; - RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ - RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ - RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ - RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ - RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ - WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ - RwReg Reserved2[2]; - RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ - RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ - RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ - RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ - RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ - WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ - WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ - RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ - RwReg Reserved3[37]; - RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */ - RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved4[5]; - RwReg SSC_RPR; /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */ - RwReg SSC_RCR; /**< \brief (Ssc Offset: 0x104) Receive Counter Register */ - RwReg SSC_TPR; /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */ - RwReg SSC_TCR; /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */ - RwReg SSC_RNPR; /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */ - RwReg SSC_RNCR; /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */ - RwReg SSC_TNPR; /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */ - RwReg SSC_TNCR; /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */ - WoReg SSC_PTCR; /**< \brief (Ssc Offset: 0x120) Transfer Control Register */ - RoReg SSC_PTSR; /**< \brief (Ssc Offset: 0x124) Transfer Status Register */ -} Ssc; -#endif /* __ASSEMBLY__ */ -/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ -#define SSC_CR_RXEN (0x1 << 0) /**< \brief (SSC_CR) Receive Enable */ -#define SSC_CR_RXDIS (0x1 << 1) /**< \brief (SSC_CR) Receive Disable */ -#define SSC_CR_TXEN (0x1 << 8) /**< \brief (SSC_CR) Transmit Enable */ -#define SSC_CR_TXDIS (0x1 << 9) /**< \brief (SSC_CR) Transmit Disable */ -#define SSC_CR_SWRST (0x1 << 15) /**< \brief (SSC_CR) Software Reset */ -/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ -#define SSC_CMR_DIV (0xfff << 0) /**< \brief (SSC_CMR) Clock Divider */ -/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ -#define SSC_RCMR_CKS (0x3 << 0) /**< \brief (SSC_RCMR) Receive Clock Selection */ -#define SSC_RCMR_CKS_DIV (0x0 << 0) /**< \brief (SSC_RCMR) Divided Clock */ -#define SSC_RCMR_CKS_TK (0x1 << 0) /**< \brief (SSC_RCMR) TK Clock signal */ -#define SSC_RCMR_CKS_RK (0x2 << 0) /**< \brief (SSC_RCMR) RK pin */ -#define SSC_RCMR_CKO (0x7 << 2) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ -#define SSC_RCMR_CKI (0x1 << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ -#define SSC_RCMR_CKG (0x3 << 6) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ -#define SSC_RCMR_CKG_NONE (0x0 << 6) /**< \brief (SSC_RCMR) None, continuous clock */ -#define SSC_RCMR_CKG_LOW (0x1 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ -#define SSC_RCMR_CKG_HIGH (0x2 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ -#define SSC_RCMR_START (0xf << 8) /**< \brief (SSC_RCMR) Receive Start Selection */ -#define SSC_RCMR_STOP (0x1 << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ -#define SSC_RCMR_STTDLY (0xff << 16) /**< \brief (SSC_RCMR) Receive Start Delay */ -#define SSC_RCMR_PERIOD (0xff << 24) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ -/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ -#define SSC_RFMR_DATLEN (0x1f << 0) /**< \brief (SSC_RFMR) Data Length */ -#define SSC_RFMR_LOOP (0x1 << 5) /**< \brief (SSC_RFMR) Loop Mode */ -#define SSC_RFMR_MSBF (0x1 << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ -#define SSC_RFMR_DATNB (0xf << 8) /**< \brief (SSC_RFMR) Data Number per Frame */ -#define SSC_RFMR_FSLEN (0xf << 16) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ -#define SSC_RFMR_FSOS (0x7 << 20) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ -#define SSC_RFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ -#define SSC_RFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_RFMR) FSLEN Field Extension */ -/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ -#define SSC_TCMR_CKS (0x3 << 0) /**< \brief (SSC_TCMR) Transmit Clock Selection */ -#define SSC_TCMR_CKO (0x7 << 2) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ -#define SSC_TCMR_CKI (0x1 << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ -#define SSC_TCMR_CKG (0x3 << 6) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ -#define SSC_TCMR_START (0xf << 8) /**< \brief (SSC_TCMR) Transmit Start Selection */ -#define SSC_TCMR_STTDLY (0xff << 16) /**< \brief (SSC_TCMR) Transmit Start Delay */ -#define SSC_TCMR_PERIOD (0xff << 24) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ -/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ -#define SSC_TFMR_DATLEN (0x1f << 0) /**< \brief (SSC_TFMR) Data Length */ -#define SSC_TFMR_DATDEF (0x1 << 5) /**< \brief (SSC_TFMR) Data Default Value */ -#define SSC_TFMR_MSBF (0x1 << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ -#define SSC_TFMR_DATNB (0xf << 8) /**< \brief (SSC_TFMR) Data Number per frame */ -#define SSC_TFMR_FSLEN (0xf << 16) /**< \brief (SSC_TFMR) Transmit Frame Syn Length */ -#define SSC_TFMR_FSOS (0x7 << 20) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ -#define SSC_TFMR_FSDEN (0x1 << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ -#define SSC_TFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ -#define SSC_TFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_TFMR) FSLEN Field Extension */ -/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ -#define SSC_RHR_RDAT (0xffffffff << 0) /**< \brief (SSC_RHR) Receive Data */ -/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ -#define SSC_THR_TDAT (0xffffffff << 0) /**< \brief (SSC_THR) Transmit Data */ -/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ -#define SSC_RSHR_RSDAT (0xffff << 0) /**< \brief (SSC_RSHR) Receive Synchronization Data */ -/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ -#define SSC_TSHR_TSDAT (0xffff << 0) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ -/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ -#define SSC_RC0R_CP0 (0xffff << 0) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ -/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ -#define SSC_RC1R_CP1 (0xffff << 0) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ -/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ -#define SSC_SR_TXRDY (0x1 << 0) /**< \brief (SSC_SR) Transmit Ready */ -#define SSC_SR_TXEMPTY (0x1 << 1) /**< \brief (SSC_SR) Transmit Empty */ -#define SSC_SR_ENDTX (0x1 << 2) /**< \brief (SSC_SR) End of Transmission */ -#define SSC_SR_TXBUFE (0x1 << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */ -#define SSC_SR_RXRDY (0x1 << 4) /**< \brief (SSC_SR) Receive Ready */ -#define SSC_SR_OVRUN (0x1 << 5) /**< \brief (SSC_SR) Receive Overrun */ -#define SSC_SR_ENDRX (0x1 << 6) /**< \brief (SSC_SR) End of Reception */ -#define SSC_SR_RXBUFF (0x1 << 7) /**< \brief (SSC_SR) Receive Buffer Full */ -#define SSC_SR_CP0 (0x1 << 8) /**< \brief (SSC_SR) Compare 0 */ -#define SSC_SR_CP1 (0x1 << 9) /**< \brief (SSC_SR) Compare 1 */ -#define SSC_SR_TXSYN (0x1 << 10) /**< \brief (SSC_SR) Transmit Sync */ -#define SSC_SR_RXSYN (0x1 << 11) /**< \brief (SSC_SR) Receive Sync */ -#define SSC_SR_TXEN (0x1 << 16) /**< \brief (SSC_SR) Transmit Enable */ -#define SSC_SR_RXEN (0x1 << 17) /**< \brief (SSC_SR) Receive Enable */ -/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ -#define SSC_IER_TXRDY (0x1 << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ -#define SSC_IER_TXEMPTY (0x1 << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ -#define SSC_IER_ENDTX (0x1 << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */ -#define SSC_IER_TXBUFE (0x1 << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */ -#define SSC_IER_RXRDY (0x1 << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ -#define SSC_IER_OVRUN (0x1 << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ -#define SSC_IER_ENDRX (0x1 << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */ -#define SSC_IER_RXBUFF (0x1 << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */ -#define SSC_IER_CP0 (0x1 << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ -#define SSC_IER_CP1 (0x1 << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ -#define SSC_IER_TXSYN (0x1 << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ -#define SSC_IER_RXSYN (0x1 << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ -/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ -#define SSC_IDR_TXRDY (0x1 << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ -#define SSC_IDR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ -#define SSC_IDR_ENDTX (0x1 << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */ -#define SSC_IDR_TXBUFE (0x1 << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SSC_IDR_RXRDY (0x1 << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ -#define SSC_IDR_OVRUN (0x1 << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ -#define SSC_IDR_ENDRX (0x1 << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */ -#define SSC_IDR_RXBUFF (0x1 << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */ -#define SSC_IDR_CP0 (0x1 << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ -#define SSC_IDR_CP1 (0x1 << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ -#define SSC_IDR_TXSYN (0x1 << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ -#define SSC_IDR_RXSYN (0x1 << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ -/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ -#define SSC_IMR_TXRDY (0x1 << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ -#define SSC_IMR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ -#define SSC_IMR_ENDTX (0x1 << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */ -#define SSC_IMR_TXBUFE (0x1 << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SSC_IMR_RXRDY (0x1 << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ -#define SSC_IMR_OVRUN (0x1 << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ -#define SSC_IMR_ENDRX (0x1 << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */ -#define SSC_IMR_RXBUFF (0x1 << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */ -#define SSC_IMR_CP0 (0x1 << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ -#define SSC_IMR_CP1 (0x1 << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ -#define SSC_IMR_TXSYN (0x1 << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ -#define SSC_IMR_RXSYN (0x1 << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ -/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */ -#define SSC_WPMR_WPEN (0x1 << 0) /**< \brief (SSC_WPMR) Write Protect Enable */ -#define SSC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SSC_WPMR) Write Protect KEY */ -/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */ -#define SSC_WPSR_WPVS (0x1 << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */ -#define SSC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SSC_WPSR) Write Protect Violation Source */ -/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */ -#define SSC_RPR_RXPTR (0xffffffff << 0) /**< \brief (SSC_RPR) Receive Pointer Register */ -/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */ -#define SSC_RCR_RXCTR (0xffff << 0) /**< \brief (SSC_RCR) Receive Counter Register */ -/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */ -#define SSC_TPR_TXPTR (0xffffffff << 0) /**< \brief (SSC_TPR) Transmit Counter Register */ -/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */ -#define SSC_TCR_TXCTR (0xffff << 0) /**< \brief (SSC_TCR) Transmit Counter Register */ -/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */ -#define SSC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (SSC_RNPR) Receive Next Pointer */ -/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */ -#define SSC_RNCR_RXNCTR (0xffff << 0) /**< \brief (SSC_RNCR) Receive Next Counter */ -/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define SSC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (SSC_TNPR) Transmit Next Pointer */ -/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define SSC_TNCR_TXNCTR (0xffff << 0) /**< \brief (SSC_TNCR) Transmit Counter Next */ -/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */ -#define SSC_PTCR_RXTEN (0x1 << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */ -#define SSC_PTCR_RXTDIS (0x1 << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */ -#define SSC_PTCR_TXTEN (0x1 << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */ -#define SSC_PTCR_TXTDIS (0x1 << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */ -/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */ -#define SSC_PTSR_RXTEN (0x1 << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */ -#define SSC_PTSR_TXTEN (0x1 << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Supply Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_SUPC Supply Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Supc hardware registers */ -typedef struct { - WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ - RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ - RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ - RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */ - RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */ - RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ -} Supc; -#endif /* __ASSEMBLY__ */ -/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ -#define SUPC_CR_VROFF (0x1 << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ -#define SUPC_CR_VROFF_NO_EFFECT (0x0 << 2) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_VROFF_STOP_VREG (0x1 << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */ -#define SUPC_CR_XTALSEL (0x1 << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ -#define SUPC_CR_XTALSEL_NO_EFFECT (0x0 << 3) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1 << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ -#define SUPC_CR_KEY (0xff << 24) /**< \brief (SUPC_CR) Password */ -/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ -#define SUPC_SMMR_SMTH (0xf << 0) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ -#define SUPC_SMMR_SMTH_1_9V (0x0 << 0) /**< \brief (SUPC_SMMR) 1.9 V */ -#define SUPC_SMMR_SMTH_2_0V (0x1 << 0) /**< \brief (SUPC_SMMR) 2.0 V */ -#define SUPC_SMMR_SMTH_2_1V (0x2 << 0) /**< \brief (SUPC_SMMR) 2.1 V */ -#define SUPC_SMMR_SMTH_2_2V (0x3 << 0) /**< \brief (SUPC_SMMR) 2.2 V */ -#define SUPC_SMMR_SMTH_2_3V (0x4 << 0) /**< \brief (SUPC_SMMR) 2.3 V */ -#define SUPC_SMMR_SMTH_2_4V (0x5 << 0) /**< \brief (SUPC_SMMR) 2.4 V */ -#define SUPC_SMMR_SMTH_2_5V (0x6 << 0) /**< \brief (SUPC_SMMR) 2.5 V */ -#define SUPC_SMMR_SMTH_2_6V (0x7 << 0) /**< \brief (SUPC_SMMR) 2.6 V */ -#define SUPC_SMMR_SMTH_2_7V (0x8 << 0) /**< \brief (SUPC_SMMR) 2.7 V */ -#define SUPC_SMMR_SMTH_2_8V (0x9 << 0) /**< \brief (SUPC_SMMR) 2.8 V */ -#define SUPC_SMMR_SMTH_2_9V (0xA << 0) /**< \brief (SUPC_SMMR) 2.9 V */ -#define SUPC_SMMR_SMTH_3_0V (0xB << 0) /**< \brief (SUPC_SMMR) 3.0 V */ -#define SUPC_SMMR_SMTH_3_1V (0xC << 0) /**< \brief (SUPC_SMMR) 3.1 V */ -#define SUPC_SMMR_SMTH_3_2V (0xD << 0) /**< \brief (SUPC_SMMR) 3.2 V */ -#define SUPC_SMMR_SMTH_3_3V (0xE << 0) /**< \brief (SUPC_SMMR) 3.3 V */ -#define SUPC_SMMR_SMTH_3_4V (0xF << 0) /**< \brief (SUPC_SMMR) 3.4 V */ -#define SUPC_SMMR_SMSMPL (0x7 << 8) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ -#define SUPC_SMMR_SMSMPL_SMD (0x0 << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ -#define SUPC_SMMR_SMSMPL_CSM (0x1 << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ -#define SUPC_SMMR_SMSMPL_32SLCK (0x2 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ -#define SUPC_SMMR_SMSMPL_256SLCK (0x3 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ -#define SUPC_SMMR_SMSMPL_2048SLCK (0x4 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ -#define SUPC_SMMR_SMRSTEN (0x1 << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ -#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN (0x1 << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ -#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN_ENABLE (0x1 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ -/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ -#define SUPC_MR_BODRSTEN (0x1 << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ -#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ -#define SUPC_MR_BODRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ -#define SUPC_MR_BODDIS (0x1 << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ -#define SUPC_MR_BODDIS_ENABLE (0x0 << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ -#define SUPC_MR_BODDIS_DISABLE (0x1 << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ -#define SUPC_MR_ONREG (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */ -#define SUPC_MR_ONREG_ONREG_UNUSED (0x0 << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */ -#define SUPC_MR_ONREG_ONREG_USED (0x1 << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */ -#define SUPC_MR_OSCBYPASS (0x1 << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ -#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0 << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ -#define SUPC_MR_OSCBYPASS_BYPASS (0x1 << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ -#define SUPC_MR_KEY (0xff << 24) /**< \brief (SUPC_MR) Password Key */ -/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */ -#define SUPC_WUMR_SMEN (0x1 << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */ -#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */ -#define SUPC_WUMR_SMEN_ENABLE (0x1 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTTEN (0x1 << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */ -#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTTEN_ENABLE (0x1 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTCEN (0x1 << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */ -#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTCEN_ENABLE (0x1 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_WKUPDBC (0x7 << 12) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer */ -#define SUPC_WUMR_WKUPDBC_1SCLK (0x0 << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ -#define SUPC_WUMR_WKUPDBC_3SCLK (0x1 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 3 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32SCLK (0x2 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_512SCLK (0x3 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 512 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_4096SCLK (0x4 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 4,096 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32768SCLK (0x5 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32,768 SLCK periods */ -/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */ -#define SUPC_WUIR_WKUPEN0 (0x1 << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */ -#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN0_ENABLE (0x1 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN1 (0x1 << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */ -#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN1_ENABLE (0x1 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN2 (0x1 << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */ -#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN2_ENABLE (0x1 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN3 (0x1 << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */ -#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN3_ENABLE (0x1 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN4 (0x1 << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */ -#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN4_ENABLE (0x1 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN5 (0x1 << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */ -#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN5_ENABLE (0x1 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN6 (0x1 << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */ -#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN6_ENABLE (0x1 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN7 (0x1 << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */ -#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN7_ENABLE (0x1 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN8 (0x1 << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */ -#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN8_ENABLE (0x1 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN9 (0x1 << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */ -#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN9_ENABLE (0x1 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN10 (0x1 << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */ -#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN10_ENABLE (0x1 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN11 (0x1 << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */ -#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN11_ENABLE (0x1 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN12 (0x1 << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */ -#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN12_ENABLE (0x1 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN13 (0x1 << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */ -#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN13_ENABLE (0x1 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN14 (0x1 << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */ -#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN14_ENABLE (0x1 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN15 (0x1 << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */ -#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN15_ENABLE (0x1 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0 (0x1 << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */ -#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0 << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1 << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1 (0x1 << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */ -#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0 << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1 << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2 (0x1 << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */ -#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0 << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1 << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3 (0x1 << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */ -#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0 << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1 << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4 (0x1 << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */ -#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0 << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1 << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5 (0x1 << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */ -#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0 << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1 << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6 (0x1 << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */ -#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0 << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1 << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7 (0x1 << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */ -#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0 << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1 << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8 (0x1 << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */ -#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0 << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1 << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9 (0x1 << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */ -#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0 << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1 << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10 (0x1 << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */ -#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0 << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1 << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11 (0x1 << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */ -#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0 << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1 << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12 (0x1 << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */ -#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0 << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1 << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13 (0x1 << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */ -#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0 << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1 << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14 (0x1 << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */ -#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0 << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1 << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15 (0x1 << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */ -#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0 << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1 << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ -#define SUPC_SR_WKUPS (0x1 << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */ -#define SUPC_SR_WKUPS_NO (0x0 << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_WKUPS_PRESENT (0x1 << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS (0x1 << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */ -#define SUPC_SR_SMWS_NO (0x0 << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS_PRESENT (0x1 << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_BODRSTS (0x1 << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ -#define SUPC_SR_BODRSTS_NO (0x0 << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_BODRSTS_PRESENT (0x1 << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS (0x1 << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ -#define SUPC_SR_SMRSTS_NO (0x0 << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS_PRESENT (0x1 << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMS (0x1 << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ -#define SUPC_SR_SMS_NO (0x0 << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMS_PRESENT (0x1 << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMOS (0x1 << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ -#define SUPC_SR_SMOS_HIGH (0x0 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */ -#define SUPC_SR_SMOS_LOW (0x1 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */ -#define SUPC_SR_OSCSEL (0x1 << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ -#define SUPC_SR_OSCSEL_RC (0x0 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ -#define SUPC_SR_OSCSEL_CRYST (0x1 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ -#define SUPC_SR_WKUPIS0 (0x1 << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ -#define SUPC_SR_WKUPIS0_DIS (0x0 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS0_EN (0x1 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1 (0x1 << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ -#define SUPC_SR_WKUPIS1_DIS (0x0 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1_EN (0x1 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2 (0x1 << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ -#define SUPC_SR_WKUPIS2_DIS (0x0 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2_EN (0x1 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3 (0x1 << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ -#define SUPC_SR_WKUPIS3_DIS (0x0 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3_EN (0x1 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4 (0x1 << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ -#define SUPC_SR_WKUPIS4_DIS (0x0 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4_EN (0x1 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5 (0x1 << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ -#define SUPC_SR_WKUPIS5_DIS (0x0 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5_EN (0x1 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6 (0x1 << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ -#define SUPC_SR_WKUPIS6_DIS (0x0 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6_EN (0x1 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7 (0x1 << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ -#define SUPC_SR_WKUPIS7_DIS (0x0 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7_EN (0x1 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8 (0x1 << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ -#define SUPC_SR_WKUPIS8_DIS (0x0 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8_EN (0x1 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9 (0x1 << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ -#define SUPC_SR_WKUPIS9_DIS (0x0 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9_EN (0x1 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10 (0x1 << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ -#define SUPC_SR_WKUPIS10_DIS (0x0 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10_EN (0x1 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11 (0x1 << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ -#define SUPC_SR_WKUPIS11_DIS (0x0 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11_EN (0x1 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12 (0x1 << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ -#define SUPC_SR_WKUPIS12_DIS (0x0 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12_EN (0x1 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13 (0x1 << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ -#define SUPC_SR_WKUPIS13_DIS (0x0 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13_EN (0x1 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14 (0x1 << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ -#define SUPC_SR_WKUPIS14_DIS (0x0 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14_EN (0x1 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15 (0x1 << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ -#define SUPC_SR_WKUPIS15_DIS (0x0 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15_EN (0x1 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Timer Counter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_TC Timer Counter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief TcChannel hardware registers */ -typedef struct { - RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ - RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ - RwReg Reserved1[2]; - RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ - RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ - RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ - RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ - RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ - RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ - RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ - RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ - RwReg Reserved2[4]; -} TcChannel; -/** \brief Tc hardware registers */ -typedef struct { - TcChannel TC_CHANNEL[3]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ - WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ - RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ - WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ - WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ - RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ - RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ - RwReg TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ - RwReg Reserved1[2]; - RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */ - RwReg Reserved2[5]; - RoReg TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ -} Tc; -#endif /* __ASSEMBLY__ */ -/* -------- TC_CCR0 : (TC Offset: 0x0) Channel Control Register (channel = 0) -------- */ -#define TC_CCR0_CLKEN (0x1 << 0) /**< \brief (TC_CCR0) Counter Clock Enable Command */ -#define TC_CCR0_CLKDIS (0x1 << 1) /**< \brief (TC_CCR0) Counter Clock Disable Command */ -#define TC_CCR0_SWTRG (0x1 << 2) /**< \brief (TC_CCR0) Software Trigger Command */ -/* -------- TC_CMR0 : (TC Offset: 0x4) Channel Mode Register (channel = 0) -------- */ -#define TC_CMR0_TCCLKS (0x7 << 0) /**< \brief (TC_CMR0) Clock Selection */ -#define TC_CM0_TCCLKS_TIMER_DIV1_CLOCK (0x0 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV1_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV2_CLOCK (0x1 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV2_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV3_CLOCK (0x2 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV3_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV4_CLOCK (0x3 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV4_CLOCK*/ -#define TC_CM0_TCCLKS_TIMER_DIV5_CLOCK (0x4 << 0) /**< (TC_CMR0) Clock selected: TIMER_DIV5_CLOCK*/ -#define TC_CM0_TCCLKS_XC0 (0x5 << 0) /**< (TC_CMR0) Clock selected: XC0*/ -#define TC_CM0_TCCLKS_XC1 (0x6 << 0) /**< (TC_CMR0) Clock selected: XC1*/ -#define TC_CM0_TCCLKS_XC2 (0x7 << 0) /**< (TC_CMR0) Clock selected: XC2*/ -#define TC_CMR0_CLKI (0x1 << 3) /**< \brief (TC_CMR0) Clock Invert */ -#define TC_CMR0_BURST (0x3 << 4) /**< \brief (TC_CMR0) Burst Signal Selection */ -#define TC_CMR0_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR0) The clock is not gated by an external signal. */ -#define TC_CMR0_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR0) XC0 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR0) XC1 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR0) XC2 is ANDed with the selected clock. */ -#define TC_CMR0_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR0) Counter Clock Stopped with RB Loading */ -#define TC_CMR0_LDBDIS (0x1 << 7) /**< \brief (TC_CMR0) Counter Clock Disable with RB Loading */ -#define TC_CMR0_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR0) External Trigger Edge Selection */ -#define TC_CMR0_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR0) rising edge */ -#define TC_CMR0_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR0) falling edge */ -#define TC_CMR0_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR0) each edge */ -#define TC_CMR0_ABETRG (0x1 << 10) /**< \brief (TC_CMR0) TIOA or TIOB External Trigger Selection */ -#define TC_CMR0_CPCTRG (0x1 << 14) /**< \brief (TC_CMR0) RC Compare Trigger Enable */ -#define TC_CMR0_WAVE (0x1 << 15) /**< \brief (TC_CMR0) */ -#define TC_CMR0_LDRA (0x3 << 16) /**< \brief (TC_CMR0) RA Loading Selection */ -#define TC_CMR0_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR0) each edge of TIOA */ -#define TC_CMR0_LDRB (0x3 << 18) /**< \brief (TC_CMR0) RB Loading Selection */ -#define TC_CMR0_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR0) each edge of TIOA */ - -#define TC_CMR0_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define TC_CMR0_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define TC_CMR0_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define TC_CMR0_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle - -#define TC_CMR0_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define TC_CMR0_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define TC_CMR0_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define TC_CMR0_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -/* -------- TC_CV0 : (TC Offset: 0x10) Counter Value (channel = 0) -------- */ -#define TC_CV0_CV (0xffff << 0) /**< \brief (TC_CV0) Counter Value */ -/* -------- TC_RA0 : (TC Offset: 0x14) Register A (channel = 0) -------- */ -#define TC_RA0_RA (0xffff << 0) /**< \brief (TC_RA0) Register A */ -/* -------- TC_RB0 : (TC Offset: 0x18) Register B (channel = 0) -------- */ -#define TC_RB0_RB (0xffff << 0) /**< \brief (TC_RB0) Register B */ -/* -------- TC_RC0 : (TC Offset: 0x1C) Register C (channel = 0) -------- */ -#define TC_RC0_RC (0xffff << 0) /**< \brief (TC_RC0) Register C */ -/* -------- TC_SR0 : (TC Offset: 0x20) Status Register (channel = 0) -------- */ -#define TC_SR0_COVFS (0x1 << 0) /**< \brief (TC_SR0) Counter Overflow Status */ -#define TC_SR0_LOVRS (0x1 << 1) /**< \brief (TC_SR0) Load Overrun Status */ -#define TC_SR0_CPAS (0x1 << 2) /**< \brief (TC_SR0) RA Compare Status */ -#define TC_SR0_CPBS (0x1 << 3) /**< \brief (TC_SR0) RB Compare Status */ -#define TC_SR0_CPCS (0x1 << 4) /**< \brief (TC_SR0) RC Compare Status */ -#define TC_SR0_LDRAS (0x1 << 5) /**< \brief (TC_SR0) RA Loading Status */ -#define TC_SR0_LDRBS (0x1 << 6) /**< \brief (TC_SR0) RB Loading Status */ -#define TC_SR0_ETRGS (0x1 << 7) /**< \brief (TC_SR0) External Trigger Status */ -#define TC_SR0_CLKSTA (0x1 << 16) /**< \brief (TC_SR0) Clock Enabling Status */ -#define TC_SR0_MTIOA (0x1 << 17) /**< \brief (TC_SR0) TIOA Mirror */ -#define TC_SR0_MTIOB (0x1 << 18) /**< \brief (TC_SR0) TIOB Mirror */ -/* -------- TC_IER0 : (TC Offset: 0x24) Interrupt Enable Register (channel = 0) -------- */ -#define TC_IER0_COVFS (0x1 << 0) /**< \brief (TC_IER0) Counter Overflow */ -#define TC_IER0_LOVRS (0x1 << 1) /**< \brief (TC_IER0) Load Overrun */ -#define TC_IER0_CPAS (0x1 << 2) /**< \brief (TC_IER0) RA Compare */ -#define TC_IER0_CPBS (0x1 << 3) /**< \brief (TC_IER0) RB Compare */ -#define TC_IER0_CPCS (0x1 << 4) /**< \brief (TC_IER0) RC Compare */ -#define TC_IER0_LDRAS (0x1 << 5) /**< \brief (TC_IER0) RA Loading */ -#define TC_IER0_LDRBS (0x1 << 6) /**< \brief (TC_IER0) RB Loading */ -#define TC_IER0_ETRGS (0x1 << 7) /**< \brief (TC_IER0) External Trigger */ -/* -------- TC_IDR0 : (TC Offset: 0x28) Interrupt Disable Register (channel = 0) -------- */ -#define TC_IDR0_COVFS (0x1 << 0) /**< \brief (TC_IDR0) Counter Overflow */ -#define TC_IDR0_LOVRS (0x1 << 1) /**< \brief (TC_IDR0) Load Overrun */ -#define TC_IDR0_CPAS (0x1 << 2) /**< \brief (TC_IDR0) RA Compare */ -#define TC_IDR0_CPBS (0x1 << 3) /**< \brief (TC_IDR0) RB Compare */ -#define TC_IDR0_CPCS (0x1 << 4) /**< \brief (TC_IDR0) RC Compare */ -#define TC_IDR0_LDRAS (0x1 << 5) /**< \brief (TC_IDR0) RA Loading */ -#define TC_IDR0_LDRBS (0x1 << 6) /**< \brief (TC_IDR0) RB Loading */ -#define TC_IDR0_ETRGS (0x1 << 7) /**< \brief (TC_IDR0) External Trigger */ -/* -------- TC_IMR0 : (TC Offset: 0x2C) Interrupt Mask Register (channel = 0) -------- */ -#define TC_IMR0_COVFS (0x1 << 0) /**< \brief (TC_IMR0) Counter Overflow */ -#define TC_IMR0_LOVRS (0x1 << 1) /**< \brief (TC_IMR0) Load Overrun */ -#define TC_IMR0_CPAS (0x1 << 2) /**< \brief (TC_IMR0) RA Compare */ -#define TC_IMR0_CPBS (0x1 << 3) /**< \brief (TC_IMR0) RB Compare */ -#define TC_IMR0_CPCS (0x1 << 4) /**< \brief (TC_IMR0) RC Compare */ -#define TC_IMR0_LDRAS (0x1 << 5) /**< \brief (TC_IMR0) RA Loading */ -#define TC_IMR0_LDRBS (0x1 << 6) /**< \brief (TC_IMR0) RB Loading */ -#define TC_IMR0_ETRGS (0x1 << 7) /**< \brief (TC_IMR0) External Trigger */ -/* -------- TC_CCR1 : (TC Offset: 0x40) Channel Control Register (channel = 1) -------- */ -#define TC_CCR1_CLKEN (0x1 << 0) /**< \brief (TC_CCR1) Counter Clock Enable Command */ -#define TC_CCR1_CLKDIS (0x1 << 1) /**< \brief (TC_CCR1) Counter Clock Disable Command */ -#define TC_CCR1_SWTRG (0x1 << 2) /**< \brief (TC_CCR1) Software Trigger Command */ -/* -------- TC_CMR1 : (TC Offset: 0x44) Channel Mode Register (channel = 1) -------- */ -#define TC_CMR1_TCCLKS (0x7 << 0) /**< \brief (TC_CMR1) Clock Selection */ -#define TC_CMR1_CLKI (0x1 << 3) /**< \brief (TC_CMR1) Clock Invert */ -#define TC_CMR1_BURST (0x3 << 4) /**< \brief (TC_CMR1) Burst Signal Selection */ -#define TC_CMR1_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR1) The clock is not gated by an external signal. */ -#define TC_CMR1_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR1) XC0 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR1) XC1 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR1) XC2 is ANDed with the selected clock. */ -#define TC_CMR1_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR1) Counter Clock Stopped with RB Loading */ -#define TC_CMR1_LDBDIS (0x1 << 7) /**< \brief (TC_CMR1) Counter Clock Disable with RB Loading */ -#define TC_CMR1_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR1) External Trigger Edge Selection */ -#define TC_CMR1_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR1) rising edge */ -#define TC_CMR1_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR1) falling edge */ -#define TC_CMR1_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR1) each edge */ -#define TC_CMR1_ABETRG (0x1 << 10) /**< \brief (TC_CMR1) TIOA or TIOB External Trigger Selection */ -#define TC_CMR1_CPCTRG (0x1 << 14) /**< \brief (TC_CMR1) RC Compare Trigger Enable */ -#define TC_CMR1_WAVE (0x1 << 15) /**< \brief (TC_CMR1) */ -#define TC_CMR1_LDRA (0x3 << 16) /**< \brief (TC_CMR1) RA Loading Selection */ -#define TC_CMR1_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR1) each edge of TIOA */ -#define TC_CMR1_LDRB (0x3 << 18) /**< \brief (TC_CMR1) RB Loading Selection */ -#define TC_CMR1_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR1) each edge of TIOA */ -/* -------- TC_CV1 : (TC Offset: 0x50) Counter Value (channel = 1) -------- */ -#define TC_CV1_CV (0xffff << 0) /**< \brief (TC_CV1) Counter Value */ -/* -------- TC_RA1 : (TC Offset: 0x54) Register A (channel = 1) -------- */ -#define TC_RA1_RA (0xffff << 0) /**< \brief (TC_RA1) Register A */ -/* -------- TC_RB1 : (TC Offset: 0x58) Register B (channel = 1) -------- */ -#define TC_RB1_RB (0xffff << 0) /**< \brief (TC_RB1) Register B */ -/* -------- TC_RC1 : (TC Offset: 0x5C) Register C (channel = 1) -------- */ -#define TC_RC1_RC (0xffff << 0) /**< \brief (TC_RC1) Register C */ -/* -------- TC_SR1 : (TC Offset: 0x60) Status Register (channel = 1) -------- */ -#define TC_SR1_COVFS (0x1 << 0) /**< \brief (TC_SR1) Counter Overflow Status */ -#define TC_SR1_LOVRS (0x1 << 1) /**< \brief (TC_SR1) Load Overrun Status */ -#define TC_SR1_CPAS (0x1 << 2) /**< \brief (TC_SR1) RA Compare Status */ -#define TC_SR1_CPBS (0x1 << 3) /**< \brief (TC_SR1) RB Compare Status */ -#define TC_SR1_CPCS (0x1 << 4) /**< \brief (TC_SR1) RC Compare Status */ -#define TC_SR1_LDRAS (0x1 << 5) /**< \brief (TC_SR1) RA Loading Status */ -#define TC_SR1_LDRBS (0x1 << 6) /**< \brief (TC_SR1) RB Loading Status */ -#define TC_SR1_ETRGS (0x1 << 7) /**< \brief (TC_SR1) External Trigger Status */ -#define TC_SR1_CLKSTA (0x1 << 16) /**< \brief (TC_SR1) Clock Enabling Status */ -#define TC_SR1_MTIOA (0x1 << 17) /**< \brief (TC_SR1) TIOA Mirror */ -#define TC_SR1_MTIOB (0x1 << 18) /**< \brief (TC_SR1) TIOB Mirror */ -/* -------- TC_IER1 : (TC Offset: 0x64) Interrupt Enable Register (channel = 1) -------- */ -#define TC_IER1_COVFS (0x1 << 0) /**< \brief (TC_IER1) Counter Overflow */ -#define TC_IER1_LOVRS (0x1 << 1) /**< \brief (TC_IER1) Load Overrun */ -#define TC_IER1_CPAS (0x1 << 2) /**< \brief (TC_IER1) RA Compare */ -#define TC_IER1_CPBS (0x1 << 3) /**< \brief (TC_IER1) RB Compare */ -#define TC_IER1_CPCS (0x1 << 4) /**< \brief (TC_IER1) RC Compare */ -#define TC_IER1_LDRAS (0x1 << 5) /**< \brief (TC_IER1) RA Loading */ -#define TC_IER1_LDRBS (0x1 << 6) /**< \brief (TC_IER1) RB Loading */ -#define TC_IER1_ETRGS (0x1 << 7) /**< \brief (TC_IER1) External Trigger */ -/* -------- TC_IDR1 : (TC Offset: 0x68) Interrupt Disable Register (channel = 1) -------- */ -#define TC_IDR1_COVFS (0x1 << 0) /**< \brief (TC_IDR1) Counter Overflow */ -#define TC_IDR1_LOVRS (0x1 << 1) /**< \brief (TC_IDR1) Load Overrun */ -#define TC_IDR1_CPAS (0x1 << 2) /**< \brief (TC_IDR1) RA Compare */ -#define TC_IDR1_CPBS (0x1 << 3) /**< \brief (TC_IDR1) RB Compare */ -#define TC_IDR1_CPCS (0x1 << 4) /**< \brief (TC_IDR1) RC Compare */ -#define TC_IDR1_LDRAS (0x1 << 5) /**< \brief (TC_IDR1) RA Loading */ -#define TC_IDR1_LDRBS (0x1 << 6) /**< \brief (TC_IDR1) RB Loading */ -#define TC_IDR1_ETRGS (0x1 << 7) /**< \brief (TC_IDR1) External Trigger */ -/* -------- TC_IMR1 : (TC Offset: 0x6C) Interrupt Mask Register (channel = 1) -------- */ -#define TC_IMR1_COVFS (0x1 << 0) /**< \brief (TC_IMR1) Counter Overflow */ -#define TC_IMR1_LOVRS (0x1 << 1) /**< \brief (TC_IMR1) Load Overrun */ -#define TC_IMR1_CPAS (0x1 << 2) /**< \brief (TC_IMR1) RA Compare */ -#define TC_IMR1_CPBS (0x1 << 3) /**< \brief (TC_IMR1) RB Compare */ -#define TC_IMR1_CPCS (0x1 << 4) /**< \brief (TC_IMR1) RC Compare */ -#define TC_IMR1_LDRAS (0x1 << 5) /**< \brief (TC_IMR1) RA Loading */ -#define TC_IMR1_LDRBS (0x1 << 6) /**< \brief (TC_IMR1) RB Loading */ -#define TC_IMR1_ETRGS (0x1 << 7) /**< \brief (TC_IMR1) External Trigger */ -/* -------- TC_CCR2 : (TC Offset: 0x80) Channel Control Register (channel = 2) -------- */ -#define TC_CCR2_CLKEN (0x1 << 0) /**< \brief (TC_CCR2) Counter Clock Enable Command */ -#define TC_CCR2_CLKDIS (0x1 << 1) /**< \brief (TC_CCR2) Counter Clock Disable Command */ -#define TC_CCR2_SWTRG (0x1 << 2) /**< \brief (TC_CCR2) Software Trigger Command */ -/* -------- TC_CMR2 : (TC Offset: 0x84) Channel Mode Register (channel = 2) -------- */ -#define TC_CMR2_TCCLKS (0x7 << 0) /**< \brief (TC_CMR2) Clock Selection */ -#define TC_CMR2_CLKI (0x1 << 3) /**< \brief (TC_CMR2) Clock Invert */ -#define TC_CMR2_BURST (0x3 << 4) /**< \brief (TC_CMR2) Burst Signal Selection */ -#define TC_CMR2_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR2) The clock is not gated by an external signal. */ -#define TC_CMR2_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR2) XC0 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR2) XC1 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR2) XC2 is ANDed with the selected clock. */ -#define TC_CMR2_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR2) Counter Clock Stopped with RB Loading */ -#define TC_CMR2_LDBDIS (0x1 << 7) /**< \brief (TC_CMR2) Counter Clock Disable with RB Loading */ -#define TC_CMR2_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR2) External Trigger Edge Selection */ -#define TC_CMR2_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR2) rising edge */ -#define TC_CMR2_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR2) falling edge */ -#define TC_CMR2_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR2) each edge */ -#define TC_CMR2_ABETRG (0x1 << 10) /**< \brief (TC_CMR2) TIOA or TIOB External Trigger Selection */ -#define TC_CMR2_CPCTRG (0x1 << 14) /**< \brief (TC_CMR2) RC Compare Trigger Enable */ -#define TC_CMR2_WAVE (0x1 << 15) /**< \brief (TC_CMR2) */ -#define TC_CMR2_LDRA (0x3 << 16) /**< \brief (TC_CMR2) RA Loading Selection */ -#define TC_CMR2_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR2) each edge of TIOA */ -#define TC_CMR2_LDRB (0x3 << 18) /**< \brief (TC_CMR2) RB Loading Selection */ -#define TC_CMR2_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR2) each edge of TIOA */ -/* -------- TC_CV2 : (TC Offset: 0x90) Counter Value (channel = 2) -------- */ -#define TC_CV2_CV (0xffff << 0) /**< \brief (TC_CV2) Counter Value */ -/* -------- TC_RA2 : (TC Offset: 0x94) Register A (channel = 2) -------- */ -#define TC_RA2_RA (0xffff << 0) /**< \brief (TC_RA2) Register A */ -/* -------- TC_RB2 : (TC Offset: 0x98) Register B (channel = 2) -------- */ -#define TC_RB2_RB (0xffff << 0) /**< \brief (TC_RB2) Register B */ -/* -------- TC_RC2 : (TC Offset: 0x9C) Register C (channel = 2) -------- */ -#define TC_RC2_RC (0xffff << 0) /**< \brief (TC_RC2) Register C */ -/* -------- TC_SR2 : (TC Offset: 0xA0) Status Register (channel = 2) -------- */ -#define TC_SR2_COVFS (0x1 << 0) /**< \brief (TC_SR2) Counter Overflow Status */ -#define TC_SR2_LOVRS (0x1 << 1) /**< \brief (TC_SR2) Load Overrun Status */ -#define TC_SR2_CPAS (0x1 << 2) /**< \brief (TC_SR2) RA Compare Status */ -#define TC_SR2_CPBS (0x1 << 3) /**< \brief (TC_SR2) RB Compare Status */ -#define TC_SR2_CPCS (0x1 << 4) /**< \brief (TC_SR2) RC Compare Status */ -#define TC_SR2_LDRAS (0x1 << 5) /**< \brief (TC_SR2) RA Loading Status */ -#define TC_SR2_LDRBS (0x1 << 6) /**< \brief (TC_SR2) RB Loading Status */ -#define TC_SR2_ETRGS (0x1 << 7) /**< \brief (TC_SR2) External Trigger Status */ -#define TC_SR2_CLKSTA (0x1 << 16) /**< \brief (TC_SR2) Clock Enabling Status */ -#define TC_SR2_MTIOA (0x1 << 17) /**< \brief (TC_SR2) TIOA Mirror */ -#define TC_SR2_MTIOB (0x1 << 18) /**< \brief (TC_SR2) TIOB Mirror */ -/* -------- TC_IER2 : (TC Offset: 0xA4) Interrupt Enable Register (channel = 2) -------- */ -#define TC_IER2_COVFS (0x1 << 0) /**< \brief (TC_IER2) Counter Overflow */ -#define TC_IER2_LOVRS (0x1 << 1) /**< \brief (TC_IER2) Load Overrun */ -#define TC_IER2_CPAS (0x1 << 2) /**< \brief (TC_IER2) RA Compare */ -#define TC_IER2_CPBS (0x1 << 3) /**< \brief (TC_IER2) RB Compare */ -#define TC_IER2_CPCS (0x1 << 4) /**< \brief (TC_IER2) RC Compare */ -#define TC_IER2_LDRAS (0x1 << 5) /**< \brief (TC_IER2) RA Loading */ -#define TC_IER2_LDRBS (0x1 << 6) /**< \brief (TC_IER2) RB Loading */ -#define TC_IER2_ETRGS (0x1 << 7) /**< \brief (TC_IER2) External Trigger */ -/* -------- TC_IDR2 : (TC Offset: 0xA8) Interrupt Disable Register (channel = 2) -------- */ -#define TC_IDR2_COVFS (0x1 << 0) /**< \brief (TC_IDR2) Counter Overflow */ -#define TC_IDR2_LOVRS (0x1 << 1) /**< \brief (TC_IDR2) Load Overrun */ -#define TC_IDR2_CPAS (0x1 << 2) /**< \brief (TC_IDR2) RA Compare */ -#define TC_IDR2_CPBS (0x1 << 3) /**< \brief (TC_IDR2) RB Compare */ -#define TC_IDR2_CPCS (0x1 << 4) /**< \brief (TC_IDR2) RC Compare */ -#define TC_IDR2_LDRAS (0x1 << 5) /**< \brief (TC_IDR2) RA Loading */ -#define TC_IDR2_LDRBS (0x1 << 6) /**< \brief (TC_IDR2) RB Loading */ -#define TC_IDR2_ETRGS (0x1 << 7) /**< \brief (TC_IDR2) External Trigger */ -/* -------- TC_IMR2 : (TC Offset: 0xAC) Interrupt Mask Register (channel = 2) -------- */ -#define TC_IMR2_COVFS (0x1 << 0) /**< \brief (TC_IMR2) Counter Overflow */ -#define TC_IMR2_LOVRS (0x1 << 1) /**< \brief (TC_IMR2) Load Overrun */ -#define TC_IMR2_CPAS (0x1 << 2) /**< \brief (TC_IMR2) RA Compare */ -#define TC_IMR2_CPBS (0x1 << 3) /**< \brief (TC_IMR2) RB Compare */ -#define TC_IMR2_CPCS (0x1 << 4) /**< \brief (TC_IMR2) RC Compare */ -#define TC_IMR2_LDRAS (0x1 << 5) /**< \brief (TC_IMR2) RA Loading */ -#define TC_IMR2_LDRBS (0x1 << 6) /**< \brief (TC_IMR2) RB Loading */ -#define TC_IMR2_ETRGS (0x1 << 7) /**< \brief (TC_IMR2) External Trigger */ -/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ -#define TC_BCR_SYNC (0x1 << 0) /**< \brief (TC_BCR) Synchro Command */ -/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ -#define TC_BMR_TC0XC0S (0x3 << 0) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ -#define TC_BMR_TC0XC0S_TCLK0 (0x0 << 0) /**< \brief (TC_BMR) TCLK0 */ -#define TC_BMR_TC0XC0S_NONE (0x1 << 0) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC0XC0S_TIOA1 (0x2 << 0) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_TC0XC0S_TIOA2 (0x3 << 0) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC1XC1S (0x3 << 2) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ -#define TC_BMR_TC1XC1S_TCLK1 (0x0 << 2) /**< \brief (TC_BMR) TCLK1 */ -#define TC_BMR_TC1XC1S_NONE (0x1 << 2) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC1XC1S_TIOA0 (0x2 << 2) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC1XC1S_TIOA2 (0x3 << 2) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC2XC2S (0x3 << 4) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ -#define TC_BMR_TC2XC2S_TCLK2 (0x0 << 4) /**< \brief (TC_BMR) TCLK2 */ -#define TC_BMR_TC2XC2S_NONE (0x1 << 4) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC2XC2S_TIOA0 (0x2 << 4) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC2XC2S_TIOA1 (0x3 << 4) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_QDEN (0x1 << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ -#define TC_BMR_POSEN (0x1 << 9) /**< \brief (TC_BMR) POSition ENabled */ -#define TC_BMR_SPEEDEN (0x1 << 10) /**< \brief (TC_BMR) SPEED ENabled */ -#define TC_BMR_QDTRANS (0x1 << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ -#define TC_BMR_EDGPHA (0x1 << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ -#define TC_BMR_INVA (0x1 << 13) /**< \brief (TC_BMR) INVerted phA */ -#define TC_BMR_INVB (0x1 << 14) /**< \brief (TC_BMR) INVerted phB */ -#define TC_BMR_INVIDX (0x1 << 15) /**< \brief (TC_BMR) INVerted InDeX */ -#define TC_BMR_SWAP (0x1 << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ -#define TC_BMR_IDXPHB (0x1 << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ -#define TC_BMR_FILTER (0x1 << 19) /**< \brief (TC_BMR) */ -#define TC_BMR_MAXFILT (0x3f << 20) /**< \brief (TC_BMR) MAXimum FILTer */ -/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ -#define TC_QIER_IDX (0x1 << 0) /**< \brief (TC_QIER) InDeX */ -#define TC_QIER_DIRCHG (0x1 << 1) /**< \brief (TC_QIER) DIRection CHanGe */ -#define TC_QIER_QERR (0x1 << 2) /**< \brief (TC_QIER) Quadrature ERRor */ -/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ -#define TC_QIDR_IDX (0x1 << 0) /**< \brief (TC_QIDR) InDeX */ -#define TC_QIDR_DIRCHG (0x1 << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ -#define TC_QIDR_QERR (0x1 << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ -/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ -#define TC_QIMR_IDX (0x1 << 0) /**< \brief (TC_QIMR) InDeX */ -#define TC_QIMR_DIRCHG (0x1 << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ -#define TC_QIMR_QERR (0x1 << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ -/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ -#define TC_QISR_IDX (0x1 << 0) /**< \brief (TC_QISR) InDeX */ -#define TC_QISR_DIRCHG (0x1 << 1) /**< \brief (TC_QISR) DIRection CHanGe */ -#define TC_QISR_QERR (0x1 << 2) /**< \brief (TC_QISR) Quadrature ERRor */ -#define TC_QISR_DIR (0x1 << 8) /**< \brief (TC_QISR) Direction */ -/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ -#define TC_FMR_ENCF0 (0x1 << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */ -#define TC_FMR_ENCF1 (0x1 << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */ -/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */ -#define TC_WPMR_WPEN (0x1 << 0) /**< \brief (TC_WPMR) Write Protect Enable */ -#define TC_WPMR_WPKEY (0xffffff << 8) /**< \brief (TC_WPMR) Write Protect KEY */ -/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ -#define TC_VER_VERSION (0xfff << 0) /**< \brief (TC_VER) */ -#define TC_VER_MFN (0x7 << 16) /**< \brief (TC_VER) */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Two-wire Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_TWI Two-wire Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Twi hardware registers */ -typedef struct { - WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ - RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ - RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ - RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ - RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ - RwReg Reserved1[3]; - RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ - WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ - WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ - RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ - RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ - WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ - RwReg Reserved2[50]; - RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ - RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ - RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ - RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ - RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ - RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ - RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ - RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ - WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ - RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ -} Twi; -#endif /* __ASSEMBLY__ */ -/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ -#define TWI_CR_START (0x1 << 0) /**< \brief (TWI_CR) Send a START Condition */ -#define TWI_CR_STOP (0x1 << 1) /**< \brief (TWI_CR) Send a STOP Condition */ -#define TWI_CR_MSEN (0x1 << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ -#define TWI_CR_MSDIS (0x1 << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ -#define TWI_CR_SVEN (0x1 << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ -#define TWI_CR_SVDIS (0x1 << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ -#define TWI_CR_QUICK (0x1 << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ -#define TWI_CR_SWRST (0x1 << 7) /**< \brief (TWI_CR) Software Reset */ -/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ -#define TWI_MMR_IADRSZ (0x3 << 8) /**< \brief (TWI_MMR) Internal Device Address Size */ -#define TWI_MMR_IADRSZ_NO (0x0 << 8) /**< \brief (TWI_MMR) No internal device address */ -#define TWI_MMR_IADRSZ_1_BYTE (0x1 << 8) /**< \brief (TWI_MMR) One-byte internal device address */ -#define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ -#define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ -#define TWI_MMR_MREAD (0x1 << 12) /**< \brief (TWI_MMR) Master Read Direction */ -#define TWI_MMR_DADR (0x7f << 16) /**< \brief (TWI_MMR) Device Address */ -/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ -#define TWI_SMR_SADR (0x7f << 16) /**< \brief (TWI_SMR) Slave Address */ -/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ -#define TWI_IADR_IADR (0xffffff << 0) /**< \brief (TWI_IADR) Internal Address */ -/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ -#define TWI_CWGR_CLDIV (0xff << 0) /**< \brief (TWI_CWGR) Clock Low Divider */ -#define TWI_CWGR_CHDIV (0xff << 8) /**< \brief (TWI_CWGR) Clock High Divider */ -#define TWI_CWGR_CKDIV (0x7 << 16) /**< \brief (TWI_CWGR) Clock Divider */ -/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ -#define TWI_SR_TXCOMP (0x1 << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ -#define TWI_SR_RXRDY (0x1 << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ -#define TWI_SR_TXRDY (0x1 << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ -#define TWI_SR_SVREAD (0x1 << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ -#define TWI_SR_SVACC (0x1 << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ -#define TWI_SR_GACC (0x1 << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ -#define TWI_SR_OVRE (0x1 << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ -#define TWI_SR_NACK (0x1 << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ -#define TWI_SR_ARBLST (0x1 << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ -#define TWI_SR_SCLWS (0x1 << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ -#define TWI_SR_EOSACC (0x1 << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ -#define TWI_SR_ENDRX (0x1 << 12) /**< \brief (TWI_SR) End of RX buffer */ -#define TWI_SR_ENDTX (0x1 << 13) /**< \brief (TWI_SR) End of TX buffer */ -#define TWI_SR_RXBUFF (0x1 << 14) /**< \brief (TWI_SR) RX Buffer Full */ -#define TWI_SR_TXBUFE (0x1 << 15) /**< \brief (TWI_SR) TX Buffer Empty */ -/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ -#define TWI_IER_TXCOMP (0x1 << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ -#define TWI_IER_RXRDY (0x1 << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ -#define TWI_IER_TXRDY (0x1 << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ -#define TWI_IER_SVACC (0x1 << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ -#define TWI_IER_GACC (0x1 << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ -#define TWI_IER_OVRE (0x1 << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ -#define TWI_IER_NACK (0x1 << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ -#define TWI_IER_ARBLST (0x1 << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ -#define TWI_IER_SCL_WS (0x1 << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ -#define TWI_IER_EOSACC (0x1 << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ -#define TWI_IER_ENDRX (0x1 << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ -#define TWI_IER_ENDTX (0x1 << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ -#define TWI_IER_RXBUFF (0x1 << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ -#define TWI_IER_TXBUFE (0x1 << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ -#define TWI_IDR_TXCOMP (0x1 << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ -#define TWI_IDR_RXRDY (0x1 << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ -#define TWI_IDR_TXRDY (0x1 << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ -#define TWI_IDR_SVACC (0x1 << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ -#define TWI_IDR_GACC (0x1 << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ -#define TWI_IDR_OVRE (0x1 << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ -#define TWI_IDR_NACK (0x1 << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ -#define TWI_IDR_ARBLST (0x1 << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ -#define TWI_IDR_SCL_WS (0x1 << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ -#define TWI_IDR_EOSACC (0x1 << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ -#define TWI_IDR_ENDRX (0x1 << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ -#define TWI_IDR_ENDTX (0x1 << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ -#define TWI_IDR_RXBUFF (0x1 << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ -#define TWI_IDR_TXBUFE (0x1 << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ -#define TWI_IMR_TXCOMP (0x1 << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ -#define TWI_IMR_RXRDY (0x1 << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ -#define TWI_IMR_TXRDY (0x1 << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ -#define TWI_IMR_SVACC (0x1 << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ -#define TWI_IMR_GACC (0x1 << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ -#define TWI_IMR_OVRE (0x1 << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ -#define TWI_IMR_NACK (0x1 << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ -#define TWI_IMR_ARBLST (0x1 << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ -#define TWI_IMR_SCL_WS (0x1 << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ -#define TWI_IMR_EOSACC (0x1 << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ -#define TWI_IMR_ENDRX (0x1 << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ -#define TWI_IMR_ENDTX (0x1 << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ -#define TWI_IMR_RXBUFF (0x1 << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ -#define TWI_IMR_TXBUFE (0x1 << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ -#define TWI_RHR_RXDATA (0xff << 0) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ -/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ -#define TWI_THR_TXDATA (0xff << 0) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ -/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ -#define TWI_RPR_RXPTR (0xffffffff << 0) /**< \brief (TWI_RPR) Receive Pointer Register */ -/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ -#define TWI_RCR_RXCTR (0xffff << 0) /**< \brief (TWI_RCR) Receive Counter Register */ -/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ -#define TWI_TPR_TXPTR (0xffffffff << 0) /**< \brief (TWI_TPR) Transmit Counter Register */ -/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ -#define TWI_TCR_TXCTR (0xffff << 0) /**< \brief (TWI_TCR) Transmit Counter Register */ -/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ -#define TWI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (TWI_RNPR) Receive Next Pointer */ -/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ -#define TWI_RNCR_RXNCTR (0xffff << 0) /**< \brief (TWI_RNCR) Receive Next Counter */ -/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define TWI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (TWI_TNPR) Transmit Next Pointer */ -/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define TWI_TNCR_TXNCTR (0xffff << 0) /**< \brief (TWI_TNCR) Transmit Counter Next */ -/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ -#define TWI_PTCR_RXTEN (0x1 << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ -#define TWI_PTCR_RXTDIS (0x1 << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ -#define TWI_PTCR_TXTEN (0x1 << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ -#define TWI_PTCR_TXTDIS (0x1 << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ -/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ -#define TWI_PTSR_RXTEN (0x1 << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ -#define TWI_PTSR_TXTEN (0x1 << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_UART Universal Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Uart hardware registers */ -typedef struct { - WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ - RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ - WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ - WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ - RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ - RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ - RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ - WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ - RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ - RwReg Reserved1[55]; - RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ - RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ - RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ - RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ - RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ - RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ - RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ - RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ - WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ - RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ -} Uart; -#endif /* __ASSEMBLY__ */ -/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ -#define UART_CR_RSTRX (0x1 << 2) /**< \brief (UART_CR) Reset Receiver */ -#define UART_CR_RSTTX (0x1 << 3) /**< \brief (UART_CR) Reset Transmitter */ -#define UART_CR_RXEN (0x1 << 4) /**< \brief (UART_CR) Receiver Enable */ -#define UART_CR_RXDIS (0x1 << 5) /**< \brief (UART_CR) Receiver Disable */ -#define UART_CR_TXEN (0x1 << 6) /**< \brief (UART_CR) Transmitter Enable */ -#define UART_CR_TXDIS (0x1 << 7) /**< \brief (UART_CR) Transmitter Disable */ -#define UART_CR_RSTSTA (0x1 << 8) /**< \brief (UART_CR) Reset Status Bits */ -/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ -#define UART_MR_PAR (0x7 << 9) /**< \brief (UART_MR) Parity Type */ -#define UART_MR_CHMODE (0x3 << 14) /**< \brief (UART_MR) Channel Mode */ -/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ -#define UART_IER_RXRDY (0x1 << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ -#define UART_IER_TXRDY (0x1 << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ -#define UART_IER_ENDRX (0x1 << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ -#define UART_IER_ENDTX (0x1 << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ -#define UART_IER_OVRE (0x1 << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ -#define UART_IER_FRAME (0x1 << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ -#define UART_IER_PARE (0x1 << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ -#define UART_IER_TXEMPTY (0x1 << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ -#define UART_IER_TXBUFE (0x1 << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ -#define UART_IER_RXBUFF (0x1 << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ -/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ -#define UART_IDR_RXRDY (0x1 << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ -#define UART_IDR_TXRDY (0x1 << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ -#define UART_IDR_ENDRX (0x1 << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ -#define UART_IDR_ENDTX (0x1 << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ -#define UART_IDR_OVRE (0x1 << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ -#define UART_IDR_FRAME (0x1 << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ -#define UART_IDR_PARE (0x1 << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ -#define UART_IDR_TXEMPTY (0x1 << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ -#define UART_IDR_TXBUFE (0x1 << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ -#define UART_IDR_RXBUFF (0x1 << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ -/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ -#define UART_IMR_RXRDY (0x1 << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ -#define UART_IMR_TXRDY (0x1 << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ -#define UART_IMR_ENDRX (0x1 << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ -#define UART_IMR_ENDTX (0x1 << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ -#define UART_IMR_OVRE (0x1 << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ -#define UART_IMR_FRAME (0x1 << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ -#define UART_IMR_PARE (0x1 << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ -#define UART_IMR_TXEMPTY (0x1 << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ -#define UART_IMR_TXBUFE (0x1 << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ -#define UART_IMR_RXBUFF (0x1 << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ -/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ -#define UART_SR_RXRDY (0x1 << 0) /**< \brief (UART_SR) Receiver Ready */ -#define UART_SR_TXRDY (0x1 << 1) /**< \brief (UART_SR) Transmitter Ready */ -#define UART_SR_ENDRX (0x1 << 3) /**< \brief (UART_SR) End of Receiver Transfer */ -#define UART_SR_ENDTX (0x1 << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ -#define UART_SR_OVRE (0x1 << 5) /**< \brief (UART_SR) Overrun Error */ -#define UART_SR_FRAME (0x1 << 6) /**< \brief (UART_SR) Framing Error */ -#define UART_SR_PARE (0x1 << 7) /**< \brief (UART_SR) Parity Error */ -#define UART_SR_TXEMPTY (0x1 << 9) /**< \brief (UART_SR) Transmitter Empty */ -#define UART_SR_TXBUFE (0x1 << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ -#define UART_SR_RXBUFF (0x1 << 12) /**< \brief (UART_SR) Receive Buffer Full */ -/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ -#define UART_RHR_RXCHR (0xff << 0) /**< \brief (UART_RHR) Received Character */ -/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ -#define UART_THR_TXCHR (0xff << 0) /**< \brief (UART_THR) Character to be Transmitted */ -/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define UART_BRGR_CD (0xffff << 0) /**< \brief (UART_BRGR) Clock Divisor */ -/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ -#define UART_RPR_RXPTR (0xffffffff << 0) /**< \brief (UART_RPR) Receive Pointer Register */ -/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ -#define UART_RCR_RXCTR (0xffff << 0) /**< \brief (UART_RCR) Receive Counter Register */ -/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ -#define UART_TPR_TXPTR (0xffffffff << 0) /**< \brief (UART_TPR) Transmit Counter Register */ -/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ -#define UART_TCR_TXCTR (0xffff << 0) /**< \brief (UART_TCR) Transmit Counter Register */ -/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ -#define UART_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (UART_RNPR) Receive Next Pointer */ -/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ -#define UART_RNCR_RXNCTR (0xffff << 0) /**< \brief (UART_RNCR) Receive Next Counter */ -/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define UART_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (UART_TNPR) Transmit Next Pointer */ -/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define UART_TNCR_TXNCTR (0xffff << 0) /**< \brief (UART_TNCR) Transmit Counter Next */ -/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ -#define UART_PTCR_RXTEN (0x1 << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ -#define UART_PTCR_RXTDIS (0x1 << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ -#define UART_PTCR_TXTEN (0x1 << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ -#define UART_PTCR_TXTDIS (0x1 << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ -/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ -#define UART_PTSR_RXTEN (0x1 << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ -#define UART_PTSR_TXTEN (0x1 << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR USB Device Port */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_UDP USB Device Port */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Udp hardware registers */ -typedef struct { - RoReg UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */ - RwReg UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */ - RwReg UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */ - RwReg Reserved1[1]; - WoReg UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */ - WoReg UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */ - RoReg UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */ - RoReg UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */ - WoReg UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */ - RwReg Reserved2[1]; - RwReg UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */ - RwReg Reserved3[1]; - RwReg UDP_CSR[8]; /**< \brief (Udp Offset: 0x30) Endpoint Control and Status Register (ept_num = 0) */ - RwReg UDP_FDR[8]; /**< \brief (Udp Offset: 0x50) Endpoint FIFO Data Register (ept_num = 0) */ - RwReg Reserved4[1]; - RwReg UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */ -} Udp; -#endif /* __ASSEMBLY__ */ -/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */ -#define UDP_FRM_NUM_FRM_NUM (0x7ff << 0) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */ -#define UDP_FRM_NUM_FRM_ERR (0x1 << 16) /**< \brief (UDP_FRM_NUM) Frame Error */ -#define UDP_FRM_NUM_FRM_OK (0x1 << 17) /**< \brief (UDP_FRM_NUM) Frame OK */ -/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */ -#define UDP_GLB_STAT_FADDEN (0x1 << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */ -#define UDP_GLB_STAT_CONFG (0x1 << 1) /**< \brief (UDP_GLB_STAT) Configured */ -#define UDP_GLB_STAT_ESR (0x1 << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */ -#define UDP_GLB_STAT_RSMINPR (0x1 << 3) /**< \brief (UDP_GLB_STAT) */ -#define UDP_GLB_STAT_RMWUPE (0x1 << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */ -/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */ -#define UDP_FADDR_FADD (0x7f << 0) /**< \brief (UDP_FADDR) Function Address Value */ -#define UDP_FADDR_FEN (0x1 << 8) /**< \brief (UDP_FADDR) Function Enable */ -/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */ -#define UDP_IER_EP0INT (0x1 << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */ -#define UDP_IER_EP1INT (0x1 << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */ -#define UDP_IER_EP2INT (0x1 << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */ -#define UDP_IER_EP3INT (0x1 << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */ -#define UDP_IER_EP4INT (0x1 << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */ -#define UDP_IER_EP5INT (0x1 << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */ -#define UDP_IER_EP6INT (0x1 << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */ -#define UDP_IER_EP7INT (0x1 << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */ -#define UDP_IER_RXSUSP (0x1 << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */ -#define UDP_IER_RXRSM (0x1 << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */ -#define UDP_IER_EXTRSM (0x1 << 10) /**< \brief (UDP_IER) */ -#define UDP_IER_SOFINT (0x1 << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */ -#define UDP_IER_WAKEUP (0x1 << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */ -/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */ -#define UDP_IDR_EP0INT (0x1 << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */ -#define UDP_IDR_EP1INT (0x1 << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */ -#define UDP_IDR_EP2INT (0x1 << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */ -#define UDP_IDR_EP3INT (0x1 << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */ -#define UDP_IDR_EP4INT (0x1 << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */ -#define UDP_IDR_EP5INT (0x1 << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */ -#define UDP_IDR_EP6INT (0x1 << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */ -#define UDP_IDR_EP7INT (0x1 << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */ -#define UDP_IDR_RXSUSP (0x1 << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */ -#define UDP_IDR_RXRSM (0x1 << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */ -#define UDP_IDR_EXTRSM (0x1 << 10) /**< \brief (UDP_IDR) */ -#define UDP_IDR_SOFINT (0x1 << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */ -#define UDP_IDR_WAKEUP (0x1 << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */ -/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */ -#define UDP_IMR_EP0INT (0x1 << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */ -#define UDP_IMR_EP1INT (0x1 << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */ -#define UDP_IMR_EP2INT (0x1 << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */ -#define UDP_IMR_EP3INT (0x1 << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */ -#define UDP_IMR_EP4INT (0x1 << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */ -#define UDP_IMR_EP5INT (0x1 << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */ -#define UDP_IMR_EP6INT (0x1 << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */ -#define UDP_IMR_EP7INT (0x1 << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */ -#define UDP_IMR_RXSUSP (0x1 << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */ -#define UDP_IMR_RXRSM (0x1 << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */ -#define UDP_IMR_EXTRSM (0x1 << 10) /**< \brief (UDP_IMR) */ -#define UDP_IMR_SOFINT (0x1 << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */ -#define UDP_IMR_BIT12 (0x1 << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */ -#define UDP_IMR_WAKEUP (0x1 << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */ -/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */ -#define UDP_ISR_EP0INT (0x1 << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */ -#define UDP_ISR_EP1INT (0x1 << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */ -#define UDP_ISR_EP2INT (0x1 << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */ -#define UDP_ISR_EP3INT (0x1 << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */ -#define UDP_ISR_EP4INT (0x1 << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */ -#define UDP_ISR_EP5INT (0x1 << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */ -#define UDP_ISR_EP6INT (0x1 << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */ -#define UDP_ISR_EP7INT (0x1 << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */ -#define UDP_ISR_RXSUSP (0x1 << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */ -#define UDP_ISR_RXRSM (0x1 << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -#define UDP_ISR_EXTRSM (0x1 << 10) /**< \brief (UDP_ISR) */ -#define UDP_ISR_SOFINT (0x1 << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */ -#define UDP_ISR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */ -#define UDP_ISR_WAKEUP (0x1 << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ -/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */ -#define UDP_ICR_RXSUSP (0x1 << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */ -#define UDP_ICR_RXRSM (0x1 << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */ -#define UDP_ICR_EXTRSM (0x1 << 10) /**< \brief (UDP_ICR) */ -#define UDP_ICR_SOFINT (0x1 << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */ -#define UDP_ICR_ENDBUSRES (0x1 << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */ -#define UDP_ICR_WAKEUP (0x1 << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */ -/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */ -#define UDP_RST_EP_EP0 (0x1 << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */ -#define UDP_RST_EP_EP1 (0x1 << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */ -#define UDP_RST_EP_EP2 (0x1 << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */ -#define UDP_RST_EP_EP3 (0x1 << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */ -#define UDP_RST_EP_EP4 (0x1 << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */ -#define UDP_RST_EP_EP5 (0x1 << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */ -#define UDP_RST_EP_EP6 (0x1 << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */ -#define UDP_RST_EP_EP7 (0x1 << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */ -/* -------- UDP_CSR[8] : (UDP Offset: 0x2C) Endpoint Control and Status Register (ept_num = 0) -------- */ -#define UDP_CSR_TXCOMP (0x1 << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */ -#define UDP_CSR_RX_DATA_BK0 (0x1 << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */ -#define UDP_CSR_RXSETUP (0x1 << 2) /**< \brief (UDP_CSR[8]) Received Setup */ -#define UDP_CSR_STALLSENTISOERROR (0x1 << 3) /**< \brief (UDP_CSR[8]) */ -#define UDP_CSR_TXPKTRDY (0x1 << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */ -#define UDP_CSR_FORCESTALL (0x1 << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */ -#define UDP_CSR_RX_DATA_BK1 (0x1 << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */ -#define UDP_CSR_DIR (0x1 << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */ -#define UDP_CSR_EPTYPE (0x7 << 8) /**< \brief (UDP_CSR[8]) Endpoint Type */ -#define UDP_CSR_EPTYPE_CTRL (0x0 << 8) /**< \brief (UDP_CSR[8]) Control */ -#define UDP_CSR_EPTYPE_ISO_OUT (0x1 << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */ -#define UDP_CSR_EPTYPE_BULK_OUT (0x2 << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */ -#define UDP_CSR_EPTYPE_INT_OUT (0x3 << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */ -#define UDP_CSR_EPTYPE_ISO_IN (0x5 << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */ -#define UDP_CSR_EPTYPE_BULK_IN (0x6 << 8) /**< \brief (UDP_CSR[8]) Bulk IN */ -#define UDP_CSR_EPTYPE_INT_IN (0x7 << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */ -#define UDP_CSR_DTGLE (0x1 << 11) /**< \brief (UDP_CSR[8]) Data Toggle */ -#define UDP_CSR_EPEDS (0x1 << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */ -#define UDP_CSR_RXBYTECNT (0x7ff << 16) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */ -/* -------- UDP_FDR[8] : (UDP Offset: 0x4C) Endpoint FIFO Data Register (ept_num = 0) -------- */ -#define UDP_FDR_FIFO_DATA (0xff << 0) /**< \brief (UDP_FDR[8]) FIFO Data Value */ -/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */ -#define UDP_TXVC_TXVDIS (0x1 << 8) /**< \brief (UDP_TXVC) Transceiver Disable */ -#define UDP_TXVC_PUON (0x1 << 9) /**< \brief (UDP_TXVC) Pullup On */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_USART Universal Synchronous Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Usart hardware registers */ -typedef struct { - WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ - RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ - WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ - WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ - RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ - RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ - RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ - WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ - RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ - RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ - RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ - RwReg Reserved1[5]; - RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ - RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ - RwReg Reserved2[1]; - RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ - RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ - RwReg Reserved3[36]; - RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */ - RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved4[4]; - RoReg US_VERSION; /**< \brief (Usart Offset: 0xFC) Version Register */ - RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ - RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ - RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ - RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ - RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ - RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ - RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ - RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ - WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ - RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ -} Usart; -#endif /* __ASSEMBLY__ */ -/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ -#define US_CR_RSTRX (0x1 << 2) /**< \brief (US_CR) Reset Receiver */ -#define US_CR_RSTTX (0x1 << 3) /**< \brief (US_CR) Reset Transmitter */ -#define US_CR_RXEN (0x1 << 4) /**< \brief (US_CR) Receiver Enable */ -#define US_CR_RXDIS (0x1 << 5) /**< \brief (US_CR) Receiver Disable */ -#define US_CR_TXEN (0x1 << 6) /**< \brief (US_CR) Transmitter Enable */ -#define US_CR_TXDIS (0x1 << 7) /**< \brief (US_CR) Transmitter Disable */ -#define US_CR_RSTSTA (0x1 << 8) /**< \brief (US_CR) Reset Status Bits */ -#define US_CR_STTBRK (0x1 << 9) /**< \brief (US_CR) Start Break */ -#define US_CR_STPBRK (0x1 << 10) /**< \brief (US_CR) Stop Break */ -#define US_CR_STTTO (0x1 << 11) /**< \brief (US_CR) Start Time-out */ -#define US_CR_SENDA (0x1 << 12) /**< \brief (US_CR) Send Address */ -#define US_CR_RSTIT (0x1 << 13) /**< \brief (US_CR) Reset Iterations */ -#define US_CR_RSTNACK (0x1 << 14) /**< \brief (US_CR) Reset Non Acknowledge */ -#define US_CR_RETTO (0x1 << 15) /**< \brief (US_CR) Rearm Time-out */ -#define US_CR_DTREN (0x1 << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ -#define US_CR_DTRDIS (0x1 << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ -#define US_CR_RTSEN__FCS (0x1 << 18) /**< \brief (US_CR) Request to Send Enable/Force SPI Chip Select */ -#define US_CR_RTSDIS__RCS (0x1 << 19) /**< \brief (US_CR) Request to Send Disable/Release SPI Chip Select */ -/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ -#define US_MR_USART_MODE (0xf << 0) /**< \brief (US_MR) */ -#define US_MR_USART_MODE_NORMAL (0x0) /**< (USART) Normal*/ -#define US_MR_USART_MODE_RS485 (0x1) /**< (USART) RS485*/ -#define US_MR_USART_MODE_HWHSH (0x2) /**< (USART) Hardware Handshaking*/ -#define US_MR_USART_MODE_ISO7816_0 (0x4) /**< (USART) ISO7816 protocol: T = 0*/ -#define US_MR_USART_MODE_ISO7816_1 (0x6) /**< (USART) ISO7816 protocol: T = 1*/ -#define US_MR_USART_MODE_IRDA (0x8) /**< (USART) IrDA*/ -#define US_MR_USART_MODE_SPIM (0xE) /**< (USART) SPI Master*/ -#define US_MR_USART_MODE_SPIS (0xF) /**< (USART) SPI Slave*/ -#define US_MR_USCLKS (0x3 << 4) /**< \brief (US_MR) Clock Selection */ -#define US_MR_USCLKS_CLOCK (0x0 << 4) /**< (USART) MCK*/ -#define US_MR_USCLKS_FDIV1 (0x1 << 4) /**< (USART) MCK/DIV(DIV=8)*/ -#define US_MR_USCLKS_SLOW (0x2 << 4) /**< (USART) Reserved*/ -#define US_MR_USCLKS_EXT (0x3 << 4) /**< (USART) SCK*/ -#define US_MR_CHRL (0x3 << 6) /**< \brief (US_MR) Character Length. */ -#define US_MR_CHRL_5_BITS (0x0 << 6) /**< (USART) Character Length: 5 bits*/ -#define US_MR_CHRL_6_BITS (0x1 << 6) /**< (USART) Character Length: 6 bits*/ -#define US_MR_CHRL_7_BITS (0x2 << 6) /**< (USART) Character Length: 7 bits*/ -#define US_MR_CHRL_8_BITS (0x3 << 6) /**< (USART) Character Length: 8 bits*/ -#define US_MR_SYNC__CPHA (0x1 << 8) /**< \brief (US_MR) Synchronous Mode Select or SPI Clock Phase */ -#define US_MR_PAR (0x7 << 9) /**< \brief (US_MR) Parity Type */ -#define US_MR_PAR_EVEN (0x0 << 9) /**< (USART) Even Parity*/ -#define US_MR_PAR_ODD (0x1 << 9) /**< (USART) Odd Parity*/ -#define US_MR_PAR_SPACE (0x2 << 9) /**< (USART) Parity forced to 0 (Space)*/ -#define US_MR_PAR_MARK (0x3 << 9) /**< (USART) Parity forced to 1 (Mark)*/ -#define US_MR_PAR_NONE (0x4 << 9) /**< (USART) No Parity*/ -#define US_MR_PAR_MULTI_DROP (0x6 << 9) /**< (USART) Multi-drop mode*/ -#define US_MR_NBSTOP (0x3 << 12) /**< \brief (US_MR) Number of Stop Bits */ -#define US_MR_NBSTOP_1_BIT (0x0 << 12) /**< (USART) 1 stop bit*/ -#define US_MR_NBSTOP_15_BIT (0x1 << 12) /**< (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits*/ -#define US_MR_NBSTOP_2_BIT (0x2 << 12) /**< (USART) 2 stop bits*/ -#define US_MR_CHMODE (0x3 << 14) /**< \brief (US_MR) Channel Mode */ -#define US_MR_CHMODE_NORMAL (0x0 << 14) /**< (USART) Normal Mode: The USART channel operates as an RX/TX USART.*/ -#define US_MR_CHMODE_AUTO (0x1 << 14) /**< (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.*/ -#define US_MR_CHMODE_LOCAL (0x2 << 14) /**< (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.*/ -#define US_MR_CHMODE_REMOTE (0x3 << 14) /**< (USART) Remote Loopback: RXD pin is internally connected to TXD pin.*/ -#define US_MR_MSBF__CPOL (0x1 << 16) /**< \brief (US_MR) Bit Order or SPI Clock Polarity */ -#define US_MR_MODE9 (0x1 << 17) /**< \brief (US_MR) 9-bit Character Length */ -#define US_MR_CLKO (0x1 << 18) /**< \brief (US_MR) Clock Output Select */ -#define US_MR_OVER (0x1 << 19) /**< \brief (US_MR) Oversampling Mode */ -#define US_MR_INACK (0x1 << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ -#define US_MR_DSNACK (0x1 << 21) /**< \brief (US_MR) Disable Successive NACK */ -#define US_MR_VAR_SYNC (0x1 << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ -#define US_MR_INVDATA (0x1 << 23) /**< \brief (US_MR) INverted Data */ -#define US_MR_MAX_ITERATION (0x7 << 24) /**< \brief (US_MR) */ -#define US_MR_FILTER (0x1 << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ -#define US_MR_MAN (0x1 << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ -#define US_MR_MODSYNC_ (0x1 << 30) /**< \brief (US_MR) */ -#define US_MR_ONEBIT (0x1 << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ -/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ -#define US_IER_RXRDY (0x1 << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ -#define US_IER_TXRDY (0x1 << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ -#define US_IER_RXBRK (0x1 << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ -#define US_IER_ENDRX (0x1 << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */ -#define US_IER_ENDTX (0x1 << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */ -#define US_IER_OVRE (0x1 << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ -#define US_IER_FRAME (0x1 << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ -#define US_IER_PARE (0x1 << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ -#define US_IER_TIMEOUT (0x1 << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ -#define US_IER_TXEMPTY (0x1 << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ -#define US_IER_ITER__UNRE (0x1 << 10) /**< \brief (US_IER) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IER_TXBUFE (0x1 << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */ -#define US_IER_RXBUFF (0x1 << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */ -#define US_IER_NACK (0x1 << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ -#define US_IER_RIIC (0x1 << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ -#define US_IER_DSRIC (0x1 << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ -#define US_IER_DCDIC (0x1 << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ -#define US_IER_CTSIC (0x1 << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ -#define US_IER_MANE (0x1 << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ -/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ -#define US_IDR_RXRDY (0x1 << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ -#define US_IDR_TXRDY (0x1 << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ -#define US_IDR_RXBRK (0x1 << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ -#define US_IDR_ENDRX (0x1 << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */ -#define US_IDR_ENDTX (0x1 << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */ -#define US_IDR_OVRE (0x1 << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */ -#define US_IDR_FRAME (0x1 << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ -#define US_IDR_PARE (0x1 << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ -#define US_IDR_TIMEOUT (0x1 << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ -#define US_IDR_TXEMPTY (0x1 << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ -#define US_IDR_ITER__UNRE (0x1 << 10) /**< \brief (US_IDR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IDR_TXBUFE (0x1 << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */ -#define US_IDR_RXBUFF (0x1 << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */ -#define US_IDR_NACK (0x1 << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ -#define US_IDR_RIIC (0x1 << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ -#define US_IDR_DSRIC (0x1 << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ -#define US_IDR_DCDIC (0x1 << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ -#define US_IDR_CTSIC (0x1 << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ -#define US_IDR_MANE (0x1 << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ -/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ -#define US_IMR_RXRDY (0x1 << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ -#define US_IMR_TXRDY (0x1 << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ -#define US_IMR_RXBRK (0x1 << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ -#define US_IMR_ENDRX (0x1 << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */ -#define US_IMR_ENDTX (0x1 << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */ -#define US_IMR_OVRE (0x1 << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ -#define US_IMR_FRAME (0x1 << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ -#define US_IMR_PARE (0x1 << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ -#define US_IMR_TIMEOUT (0x1 << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ -#define US_IMR_TXEMPTY (0x1 << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ -#define US_IMR_ITER__UNRE (0x1 << 10) /**< \brief (US_IMR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IMR_TXBUFE (0x1 << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */ -#define US_IMR_RXBUFF (0x1 << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */ -#define US_IMR_NACK (0x1 << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ -#define US_IMR_RIIC (0x1 << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ -#define US_IMR_DSRIC (0x1 << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ -#define US_IMR_DCDIC (0x1 << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ -#define US_IMR_CTSIC (0x1 << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ -#define US_IMR_MANE (0x1 << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ -/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ -#define US_CSR_RXRDY (0x1 << 0) /**< \brief (US_CSR) Receiver Ready */ -#define US_CSR_TXRDY (0x1 << 1) /**< \brief (US_CSR) Transmitter Ready */ -#define US_CSR_RXBRK (0x1 << 2) /**< \brief (US_CSR) Break Received/End of Break */ -#define US_CSR_ENDRX (0x1 << 3) /**< \brief (US_CSR) End of Receiver Transfer */ -#define US_CSR_ENDTX (0x1 << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ -#define US_CSR_OVRE (0x1 << 5) /**< \brief (US_CSR) Overrun Error */ -#define US_CSR_FRAME (0x1 << 6) /**< \brief (US_CSR) Framing Error */ -#define US_CSR_PARE (0x1 << 7) /**< \brief (US_CSR) Parity Error */ -#define US_CSR_TIMEOUT (0x1 << 8) /**< \brief (US_CSR) Receiver Time-out */ -#define US_CSR_TXEMPTY (0x1 << 9) /**< \brief (US_CSR) Transmitter Empty */ -#define US_CSR_ITER__UNRE (0x1 << 10) /**< \brief (US_CSR) Max number of Repetitions Reached or SPI Underrun Error */ -#define US_CSR_TXBUFE (0x1 << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ -#define US_CSR_RXBUFF (0x1 << 12) /**< \brief (US_CSR) Reception Buffer Full */ -#define US_CSR_NACK (0x1 << 13) /**< \brief (US_CSR) */ -#define US_CSR_RIIC (0x1 << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */ -#define US_CSR_DSRIC (0x1 << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */ -#define US_CSR_DCDIC (0x1 << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */ -#define US_CSR_CTSIC (0x1 << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ -#define US_CSR_RI (0x1 << 20) /**< \brief (US_CSR) Image of RI Input */ -#define US_CSR_DSR (0x1 << 21) /**< \brief (US_CSR) Image of DSR Input */ -#define US_CSR_DCD (0x1 << 22) /**< \brief (US_CSR) Image of DCD Input */ -#define US_CSR_CTS (0x1 << 23) /**< \brief (US_CSR) Image of CTS Input */ -#define US_CSR_MANERR (0x1 << 24) /**< \brief (US_CSR) Manchester Error */ -/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ -#define US_RHR_RXCHR (0x1ff << 0) /**< \brief (US_RHR) Received Character */ -#define US_RHR_RXSYNH (0x1 << 15) /**< \brief (US_RHR) Received Sync */ -/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ -#define US_THR_TXCHR (0x1ff << 0) /**< \brief (US_THR) Character to be Transmitted */ -#define US_THR_TXSYNH (0x1 << 15) /**< \brief (US_THR) Sync Field to be transmitted */ -/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define US_BRGR_CD (0xffff << 0) /**< \brief (US_BRGR) Clock Divider */ -#define US_BRGR_FP (0x7 << 16) /**< \brief (US_BRGR) Fractional Part */ -/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ -#define US_RTOR_TO (0xffff << 0) /**< \brief (US_RTOR) Time-out Value */ -/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ -#define US_TTGR_TG (0xff << 0) /**< \brief (US_TTGR) Timeguard Value */ -/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ -#define US_FIDI_FI_DI_RATIO (0x7ff << 0) /**< \brief (US_FIDI) FI Over DI Ratio Value */ -/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ -#define US_NER_NB_ERRORS (0xff << 0) /**< \brief (US_NER) Number of Errors */ -/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ -#define US_IF_IRDA_FILTER (0xff << 0) /**< \brief (US_IF) IrDA Filter */ -/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ -#define US_MAN_TX_PL (0xf << 0) /**< \brief (US_MAN) Transmitter Preamble Length */ -#define US_MAN_TX_PP (0x3 << 8) /**< \brief (US_MAN) Transmitter Preamble Pattern */ -#define US_MAN_TX_MPOL (0x1 << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ -#define US_MAN_RX_PL (0xf << 16) /**< \brief (US_MAN) Receiver Preamble Length */ -#define US_MAN_RX_PP (0x3 << 24) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ -#define US_MAN_RX_MPOL (0x1 << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ -#define US_MAN_STUCKTO1 (0x1 << 29) /**< \brief (US_MAN) */ -#define US_MAN_DRIFT (0x1 << 30) /**< \brief (US_MAN) Drift compensation */ -/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */ -#define US_WPMR_WPEN (0x1 << 0) /**< \brief (US_WPMR) Write Protect Enable */ -#define US_WPMR_WPKEY (0xffffff << 8) /**< \brief (US_WPMR) Write Protect KEY */ -/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */ -#define US_WPSR_WPVS (0x1 << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ -#define US_WPSR_WPVSRC (0xffff << 8) /**< \brief (US_WPSR) Write Protect Violation Source */ -/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */ -#define US_VERSION_VERSION (0xfff << 0) /**< \brief (US_VERSION) */ -#define US_VERSION_MFN (0x7 << 16) /**< \brief (US_VERSION) */ -/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ -#define US_RPR_RXPTR (0xffffffff << 0) /**< \brief (US_RPR) Receive Pointer Register */ -/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ -#define US_RCR_RXCTR (0xffff << 0) /**< \brief (US_RCR) Receive Counter Register */ -/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ -#define US_TPR_TXPTR (0xffffffff << 0) /**< \brief (US_TPR) Transmit Counter Register */ -/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ -#define US_TCR_TXCTR (0xffff << 0) /**< \brief (US_TCR) Transmit Counter Register */ -/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ -#define US_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (US_RNPR) Receive Next Pointer */ -/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ -#define US_RNCR_RXNCTR (0xffff << 0) /**< \brief (US_RNCR) Receive Next Counter */ -/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define US_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (US_TNPR) Transmit Next Pointer */ -/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define US_TNCR_TXNCTR (0xffff << 0) /**< \brief (US_TNCR) Transmit Counter Next */ -/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ -#define US_PTCR_RXTEN (0x1 << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ -#define US_PTCR_RXTDIS (0x1 << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ -#define US_PTCR_TXTEN (0x1 << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ -#define US_PTCR_TXTDIS (0x1 << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ -/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ -#define US_PTSR_RXTEN (0x1 << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ -#define US_PTSR_TXTEN (0x1 << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Watchdog Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3S_WDT Watchdog Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Wdt hardware registers */ -typedef struct { - WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ - RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ - RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ -} Wdt; -#endif /* __ASSEMBLY__ */ -/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ -#define WDT_CR_WDRSTT (0x1 << 0) /**< \brief (WDT_CR) Watchdog Restart */ -#define WDT_CR_KEY (0xff << 24) /**< \brief (WDT_CR) Password */ -/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ -#define WDT_MR_WDV (0xfff << 0) /**< \brief (WDT_MR) Watchdog Counter Value */ -#define WDT_MR_WDFIEN (0x1 << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ -#define WDT_MR_WDRSTEN (0x1 << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ -#define WDT_MR_WDRPROC (0x1 << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ -#define WDT_MR_WDDIS (0x1 << 15) /**< \brief (WDT_MR) Watchdog Disable */ -#define WDT_MR_WDD (0xfff << 16) /**< \brief (WDT_MR) Watchdog Delta Value */ -#define WDT_MR_WDDBGHLT (0x1 << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ -#define WDT_MR_WDIDLEHLT (0x1 << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ -/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ -#define WDT_SR_WDUNF (0x1 << 0) /**< \brief (WDT_SR) Watchdog Underflow */ -#define WDT_SR_WDERR (0x1 << 1) /**< \brief (WDT_SR) Watchdog Error */ - -/*@}*/ - -/*@}*/ - -/* ***************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_reg Registers Access Definitions */ -/*@{*/ - -/* ========== Register definition for HSMCI peripheral ========== */ -#define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */ -#define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */ -#define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ -#define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ -#define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */ -#define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */ -#define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */ -#define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ -#define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */ -#define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */ -#define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ -#define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */ -#define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ -#define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ -#define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ -#define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */ -#define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ -#define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ -#define REG_HSMCI_RPR REG_ACCESS(RwReg, 0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */ -#define REG_HSMCI_RCR REG_ACCESS(RwReg, 0x40000104U) /**< \brief (HSMCI) Receive Counter Register */ -#define REG_HSMCI_TPR REG_ACCESS(RwReg, 0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */ -#define REG_HSMCI_TCR REG_ACCESS(RwReg, 0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */ -#define REG_HSMCI_RNPR REG_ACCESS(RwReg, 0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */ -#define REG_HSMCI_RNCR REG_ACCESS(RwReg, 0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */ -#define REG_HSMCI_TNPR REG_ACCESS(RwReg, 0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */ -#define REG_HSMCI_TNCR REG_ACCESS(RwReg, 0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */ -#define REG_HSMCI_PTCR REG_ACCESS(WoReg, 0x40000120U) /**< \brief (HSMCI) Transfer Control Register */ -#define REG_HSMCI_PTSR REG_ACCESS(RoReg, 0x40000124U) /**< \brief (HSMCI) Transfer Status Register */ -/* ========== Register definition for SSC peripheral ========== */ -#define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */ -#define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */ -#define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ -#define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ -#define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ -#define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ -#define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */ -#define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */ -#define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ -#define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ -#define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ -#define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ -#define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */ -#define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ -#define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ -#define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ -#define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ -#define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ -#define REG_SSC_RPR REG_ACCESS(RwReg, 0x40004100U) /**< \brief (SSC) Receive Pointer Register */ -#define REG_SSC_RCR REG_ACCESS(RwReg, 0x40004104U) /**< \brief (SSC) Receive Counter Register */ -#define REG_SSC_TPR REG_ACCESS(RwReg, 0x40004108U) /**< \brief (SSC) Transmit Pointer Register */ -#define REG_SSC_TCR REG_ACCESS(RwReg, 0x4000410CU) /**< \brief (SSC) Transmit Counter Register */ -#define REG_SSC_RNPR REG_ACCESS(RwReg, 0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */ -#define REG_SSC_RNCR REG_ACCESS(RwReg, 0x40004114U) /**< \brief (SSC) Receive Next Counter Register */ -#define REG_SSC_TNPR REG_ACCESS(RwReg, 0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */ -#define REG_SSC_TNCR REG_ACCESS(RwReg, 0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */ -#define REG_SSC_PTCR REG_ACCESS(WoReg, 0x40004120U) /**< \brief (SSC) Transfer Control Register */ -#define REG_SSC_PTSR REG_ACCESS(RoReg, 0x40004124U) /**< \brief (SSC) Transfer Status Register */ -/* ========== Register definition for SPI peripheral ========== */ -#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */ -#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */ -#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */ -#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */ -#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */ -#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ -#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ -#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ -#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */ -#define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ -#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ -#define REG_SPI_RPR REG_ACCESS(RwReg, 0x40008100U) /**< \brief (SPI) Receive Pointer Register */ -#define REG_SPI_RCR REG_ACCESS(RwReg, 0x40008104U) /**< \brief (SPI) Receive Counter Register */ -#define REG_SPI_TPR REG_ACCESS(RwReg, 0x40008108U) /**< \brief (SPI) Transmit Pointer Register */ -#define REG_SPI_TCR REG_ACCESS(RwReg, 0x4000810CU) /**< \brief (SPI) Transmit Counter Register */ -#define REG_SPI_RNPR REG_ACCESS(RwReg, 0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */ -#define REG_SPI_RNCR REG_ACCESS(RwReg, 0x40008114U) /**< \brief (SPI) Receive Next Counter Register */ -#define REG_SPI_TNPR REG_ACCESS(RwReg, 0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */ -#define REG_SPI_TNCR REG_ACCESS(RwReg, 0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */ -#define REG_SPI_PTCR REG_ACCESS(WoReg, 0x40008120U) /**< \brief (SPI) Transfer Control Register */ -#define REG_SPI_PTSR REG_ACCESS(RoReg, 0x40008124U) /**< \brief (SPI) Transfer Status Register */ -/* ========== Register definition for TC0 peripheral ========== */ -#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ -#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ -#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ -#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ -#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ -#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ -#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ -#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ -#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ -#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ -#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ -#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ -#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ -#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ -#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ -#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ -#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ -#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ -#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ -#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ -#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ -#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ -#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ -#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ -#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ -#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ -#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ -#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ -#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ -#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ -#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400100C0U) /**< \brief (TC0) Block Control Register */ -#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400100C4U) /**< \brief (TC0) Block Mode Register */ -#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ -#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ -#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ -#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ -#define REG_TC0_FMR REG_ACCESS(RwReg, 0x400100D8U) /**< \brief (TC0) Fault Mode Register */ -#define REG_TC0_WPMR REG_ACCESS(RwReg, 0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */ -#define REG_TC0_VER REG_ACCESS(RoReg, 0x400100FCU) /**< \brief (TC0) Version Register */ -/* ========== Register definition for TC1 peripheral ========== */ -#define REG_TC1_CCR0 REG_ACCESS(WoReg, 0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ -#define REG_TC1_CMR0 REG_ACCESS(RwReg, 0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ -#define REG_TC1_CV0 REG_ACCESS(RoReg, 0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ -#define REG_TC1_RA0 REG_ACCESS(RwReg, 0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ -#define REG_TC1_RB0 REG_ACCESS(RwReg, 0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ -#define REG_TC1_RC0 REG_ACCESS(RwReg, 0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ -#define REG_TC1_SR0 REG_ACCESS(RoReg, 0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ -#define REG_TC1_IER0 REG_ACCESS(WoReg, 0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ -#define REG_TC1_IDR0 REG_ACCESS(WoReg, 0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ -#define REG_TC1_IMR0 REG_ACCESS(RoReg, 0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ -#define REG_TC1_CCR1 REG_ACCESS(WoReg, 0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ -#define REG_TC1_CMR1 REG_ACCESS(RwReg, 0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ -#define REG_TC1_CV1 REG_ACCESS(RoReg, 0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ -#define REG_TC1_RA1 REG_ACCESS(RwReg, 0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ -#define REG_TC1_RB1 REG_ACCESS(RwReg, 0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ -#define REG_TC1_RC1 REG_ACCESS(RwReg, 0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ -#define REG_TC1_SR1 REG_ACCESS(RoReg, 0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ -#define REG_TC1_IER1 REG_ACCESS(WoReg, 0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ -#define REG_TC1_IDR1 REG_ACCESS(WoReg, 0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ -#define REG_TC1_IMR1 REG_ACCESS(RoReg, 0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ -#define REG_TC1_CCR2 REG_ACCESS(WoReg, 0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ -#define REG_TC1_CMR2 REG_ACCESS(RwReg, 0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ -#define REG_TC1_CV2 REG_ACCESS(RoReg, 0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ -#define REG_TC1_RA2 REG_ACCESS(RwReg, 0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ -#define REG_TC1_RB2 REG_ACCESS(RwReg, 0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ -#define REG_TC1_RC2 REG_ACCESS(RwReg, 0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ -#define REG_TC1_SR2 REG_ACCESS(RoReg, 0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ -#define REG_TC1_IER2 REG_ACCESS(WoReg, 0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ -#define REG_TC1_IDR2 REG_ACCESS(WoReg, 0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ -#define REG_TC1_IMR2 REG_ACCESS(RoReg, 0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ -#define REG_TC1_BCR REG_ACCESS(WoReg, 0x400140C0U) /**< \brief (TC1) Block Control Register */ -#define REG_TC1_BMR REG_ACCESS(RwReg, 0x400140C4U) /**< \brief (TC1) Block Mode Register */ -#define REG_TC1_QIER REG_ACCESS(WoReg, 0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ -#define REG_TC1_QIDR REG_ACCESS(WoReg, 0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ -#define REG_TC1_QIMR REG_ACCESS(RoReg, 0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ -#define REG_TC1_QISR REG_ACCESS(RoReg, 0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ -#define REG_TC1_FMR REG_ACCESS(RwReg, 0x400140D8U) /**< \brief (TC1) Fault Mode Register */ -#define REG_TC1_WPMR REG_ACCESS(RwReg, 0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */ -#define REG_TC1_VER REG_ACCESS(RoReg, 0x400140FCU) /**< \brief (TC1) Version Register */ -/* ========== Register definition for TWI0 peripheral ========== */ -#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40018000U) /**< \brief (TWI0) Control Register */ -#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40018004U) /**< \brief (TWI0) Master Mode Register */ -#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40018008U) /**< \brief (TWI0) Slave Mode Register */ -#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4001800CU) /**< \brief (TWI0) Internal Address Register */ -#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */ -#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40018020U) /**< \brief (TWI0) Status Register */ -#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */ -#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */ -#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */ -#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40018030U) /**< \brief (TWI0) Receive Holding Register */ -#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40018034U) /**< \brief (TWI0) Transmit Holding Register */ -#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40018100U) /**< \brief (TWI0) Receive Pointer Register */ -#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40018104U) /**< \brief (TWI0) Receive Counter Register */ -#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */ -#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */ -#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */ -#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */ -#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */ -#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */ -#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40018120U) /**< \brief (TWI0) Transfer Control Register */ -#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40018124U) /**< \brief (TWI0) Transfer Status Register */ -/* ========== Register definition for TWI1 peripheral ========== */ -#define REG_TWI1_CR REG_ACCESS(WoReg, 0x4001C000U) /**< \brief (TWI1) Control Register */ -#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x4001C004U) /**< \brief (TWI1) Master Mode Register */ -#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x4001C008U) /**< \brief (TWI1) Slave Mode Register */ -#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4001C00CU) /**< \brief (TWI1) Internal Address Register */ -#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */ -#define REG_TWI1_SR REG_ACCESS(RoReg, 0x4001C020U) /**< \brief (TWI1) Status Register */ -#define REG_TWI1_IER REG_ACCESS(WoReg, 0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */ -#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */ -#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */ -#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x4001C030U) /**< \brief (TWI1) Receive Holding Register */ -#define REG_TWI1_THR REG_ACCESS(WoReg, 0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */ -#define REG_TWI1_RPR REG_ACCESS(RwReg, 0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */ -#define REG_TWI1_RCR REG_ACCESS(RwReg, 0x4001C104U) /**< \brief (TWI1) Receive Counter Register */ -#define REG_TWI1_TPR REG_ACCESS(RwReg, 0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */ -#define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */ -#define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */ -#define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */ -#define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */ -#define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */ -#define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x4001C120U) /**< \brief (TWI1) Transfer Control Register */ -#define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x4001C124U) /**< \brief (TWI1) Transfer Status Register */ -/* ========== Register definition for PWM peripheral ========== */ -#define REG_PWM_CLK REG_ACCESS(RwReg, 0x40020000U) /**< \brief (PWM) PWM Clock Register */ -#define REG_PWM_ENA REG_ACCESS(WoReg, 0x40020004U) /**< \brief (PWM) PWM Enable Register */ -#define REG_PWM_DIS REG_ACCESS(WoReg, 0x40020008U) /**< \brief (PWM) PWM Disable Register */ -#define REG_PWM_SR REG_ACCESS(RoReg, 0x4002000CU) /**< \brief (PWM) PWM Status Register */ -#define REG_PWM_IER1 REG_ACCESS(WoReg, 0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ -#define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ -#define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ -#define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ -#define REG_PWM_SCM REG_ACCESS(RwReg, 0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ -#define REG_PWM_SCUC REG_ACCESS(RwReg, 0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ -#define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ -#define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ -#define REG_PWM_IER2 REG_ACCESS(WoReg, 0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ -#define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ -#define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ -#define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ -#define REG_PWM_OOV REG_ACCESS(RwReg, 0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */ -#define REG_PWM_OS REG_ACCESS(RwReg, 0x40020048U) /**< \brief (PWM) PWM Output Selection Register */ -#define REG_PWM_OSS REG_ACCESS(WoReg, 0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */ -#define REG_PWM_OSC REG_ACCESS(WoReg, 0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */ -#define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ -#define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ -#define REG_PWM_FMR REG_ACCESS(RwReg, 0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */ -#define REG_PWM_FSR REG_ACCESS(RoReg, 0x40020060U) /**< \brief (PWM) PWM Fault Status Register */ -#define REG_PWM_FCR REG_ACCESS(WoReg, 0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */ -#define REG_PWM_FPV REG_ACCESS(RwReg, 0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */ -#define REG_PWM_FPE REG_ACCESS(RwReg, 0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ -#define REG_PWM_ELxMR REG_ACCESS(RwReg, 0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ -#define REG_PWM_SMMR REG_ACCESS(RwReg, 0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ -#define REG_PWM_WPCR REG_ACCESS(WoReg, 0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */ -#define REG_PWM_WPSR REG_ACCESS(RoReg, 0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */ -#define REG_PWM_RPR REG_ACCESS(RwReg, 0x40020100U) /**< \brief (PWM) Receive Pointer Register */ -#define REG_PWM_RCR REG_ACCESS(RwReg, 0x40020104U) /**< \brief (PWM) Receive Counter Register */ -#define REG_PWM_TPR REG_ACCESS(RwReg, 0x40020108U) /**< \brief (PWM) Transmit Pointer Register */ -#define REG_PWM_TCR REG_ACCESS(RwReg, 0x4002010CU) /**< \brief (PWM) Transmit Counter Register */ -#define REG_PWM_RNPR REG_ACCESS(RwReg, 0x40020110U) /**< \brief (PWM) Receive Next Pointer Register */ -#define REG_PWM_RNCR REG_ACCESS(RwReg, 0x40020114U) /**< \brief (PWM) Receive Next Counter Register */ -#define REG_PWM_TNPR REG_ACCESS(RwReg, 0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */ -#define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */ -#define REG_PWM_PTCR REG_ACCESS(WoReg, 0x40020120U) /**< \brief (PWM) Transfer Control Register */ -#define REG_PWM_PTSR REG_ACCESS(RoReg, 0x40020124U) /**< \brief (PWM) Transfer Status Register */ -#define REG_PWM_CMP0V REG_ACCESS(RwReg, 0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ -#define REG_PWM_CMP0VUPD REG_ACCESS(WoReg, 0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ -#define REG_PWM_CMP0M REG_ACCESS(RwReg, 0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ -#define REG_PWM_CMP0MUPD REG_ACCESS(WoReg, 0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ -#define REG_PWM_CMP1V REG_ACCESS(RwReg, 0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ -#define REG_PWM_CMP1VUPD REG_ACCESS(WoReg, 0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ -#define REG_PWM_CMP1M REG_ACCESS(RwReg, 0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ -#define REG_PWM_CMP1MUPD REG_ACCESS(WoReg, 0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ -#define REG_PWM_CMP2V REG_ACCESS(RwReg, 0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ -#define REG_PWM_CMP2VUPD REG_ACCESS(WoReg, 0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ -#define REG_PWM_CMP2M REG_ACCESS(RwReg, 0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ -#define REG_PWM_CMP2MUPD REG_ACCESS(WoReg, 0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ -#define REG_PWM_CMP3V REG_ACCESS(RwReg, 0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ -#define REG_PWM_CMP3VUPD REG_ACCESS(WoReg, 0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ -#define REG_PWM_CMP3M REG_ACCESS(RwReg, 0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ -#define REG_PWM_CMP3MUPD REG_ACCESS(WoReg, 0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ -#define REG_PWM_CMP4V REG_ACCESS(RwReg, 0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ -#define REG_PWM_CMP4VUPD REG_ACCESS(WoReg, 0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ -#define REG_PWM_CMP4M REG_ACCESS(RwReg, 0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ -#define REG_PWM_CMP4MUPD REG_ACCESS(WoReg, 0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ -#define REG_PWM_CMP5V REG_ACCESS(RwReg, 0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ -#define REG_PWM_CMP5VUPD REG_ACCESS(WoReg, 0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ -#define REG_PWM_CMP5M REG_ACCESS(RwReg, 0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ -#define REG_PWM_CMP5MUPD REG_ACCESS(WoReg, 0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ -#define REG_PWM_CMP6V REG_ACCESS(RwReg, 0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ -#define REG_PWM_CMP6VUPD REG_ACCESS(WoReg, 0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ -#define REG_PWM_CMP6M REG_ACCESS(RwReg, 0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ -#define REG_PWM_CMP6MUPD REG_ACCESS(WoReg, 0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ -#define REG_PWM_CMP7V REG_ACCESS(RwReg, 0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ -#define REG_PWM_CMP7VUPD REG_ACCESS(WoReg, 0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ -#define REG_PWM_CMP7M REG_ACCESS(RwReg, 0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ -#define REG_PWM_CMP7MUPD REG_ACCESS(WoReg, 0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ -#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ -#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ -#define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ -#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ -#define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ -#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ -#define REG_PWM_DT0 REG_ACCESS(RwReg, 0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ -#define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ -#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ -#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ -#define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ -#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ -#define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ -#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ -#define REG_PWM_DT1 REG_ACCESS(RwReg, 0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ -#define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ -#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ -#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ -#define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ -#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ -#define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ -#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ -#define REG_PWM_DT2 REG_ACCESS(RwReg, 0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ -#define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ -#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ -#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ -#define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ -#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ -#define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ -#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ -#define REG_PWM_DT3 REG_ACCESS(RwReg, 0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ -#define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ -/* ========== Register definition for USART0 peripheral ========== */ -#define REG_USART0_CR REG_ACCESS(WoReg, 0x40024000U) /**< \brief (USART0) Control Register */ -#define REG_USART0_MR REG_ACCESS(RwReg, 0x40024004U) /**< \brief (USART0) Mode Register */ -#define REG_USART0_IER REG_ACCESS(WoReg, 0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ -#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ -#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ -#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40024014U) /**< \brief (USART0) Channel Status Register */ -#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40024018U) /**< \brief (USART0) Receiver Holding Register */ -#define REG_USART0_THR REG_ACCESS(WoReg, 0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */ -#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ -#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ -#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ -#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ -#define REG_USART0_NER REG_ACCESS(RoReg, 0x40024044U) /**< \brief (USART0) Number of Errors Register */ -#define REG_USART0_IF REG_ACCESS(RwReg, 0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ -#define REG_USART0_MAN REG_ACCESS(RwReg, 0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ -#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */ -#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400240E8U) /**< \brief (USART0) Write Protect Status Register */ -#define REG_USART0_VERSION REG_ACCESS(RoReg, 0x400240FCU) /**< \brief (USART0) Version Register */ -#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40024100U) /**< \brief (USART0) Receive Pointer Register */ -#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40024104U) /**< \brief (USART0) Receive Counter Register */ -#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40024108U) /**< \brief (USART0) Transmit Pointer Register */ -#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4002410CU) /**< \brief (USART0) Transmit Counter Register */ -#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */ -#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40024114U) /**< \brief (USART0) Receive Next Counter Register */ -#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */ -#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */ -#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40024120U) /**< \brief (USART0) Transfer Control Register */ -#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40024124U) /**< \brief (USART0) Transfer Status Register */ -/* ========== Register definition for USART1 peripheral ========== */ -#define REG_USART1_CR REG_ACCESS(WoReg, 0x40028000U) /**< \brief (USART1) Control Register */ -#define REG_USART1_MR REG_ACCESS(RwReg, 0x40028004U) /**< \brief (USART1) Mode Register */ -#define REG_USART1_IER REG_ACCESS(WoReg, 0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ -#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ -#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ -#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40028014U) /**< \brief (USART1) Channel Status Register */ -#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40028018U) /**< \brief (USART1) Receiver Holding Register */ -#define REG_USART1_THR REG_ACCESS(WoReg, 0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */ -#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ -#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ -#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ -#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ -#define REG_USART1_NER REG_ACCESS(RoReg, 0x40028044U) /**< \brief (USART1) Number of Errors Register */ -#define REG_USART1_IF REG_ACCESS(RwReg, 0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ -#define REG_USART1_MAN REG_ACCESS(RwReg, 0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ -#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */ -#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400280E8U) /**< \brief (USART1) Write Protect Status Register */ -#define REG_USART1_VERSION REG_ACCESS(RoReg, 0x400280FCU) /**< \brief (USART1) Version Register */ -#define REG_USART1_RPR REG_ACCESS(RwReg, 0x40028100U) /**< \brief (USART1) Receive Pointer Register */ -#define REG_USART1_RCR REG_ACCESS(RwReg, 0x40028104U) /**< \brief (USART1) Receive Counter Register */ -#define REG_USART1_TPR REG_ACCESS(RwReg, 0x40028108U) /**< \brief (USART1) Transmit Pointer Register */ -#define REG_USART1_TCR REG_ACCESS(RwReg, 0x4002810CU) /**< \brief (USART1) Transmit Counter Register */ -#define REG_USART1_RNPR REG_ACCESS(RwReg, 0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */ -#define REG_USART1_RNCR REG_ACCESS(RwReg, 0x40028114U) /**< \brief (USART1) Receive Next Counter Register */ -#define REG_USART1_TNPR REG_ACCESS(RwReg, 0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */ -#define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */ -#define REG_USART1_PTCR REG_ACCESS(WoReg, 0x40028120U) /**< \brief (USART1) Transfer Control Register */ -#define REG_USART1_PTSR REG_ACCESS(RoReg, 0x40028124U) /**< \brief (USART1) Transfer Status Register */ -/* ========== Register definition for UDP peripheral ========== */ -#define REG_UDP_FRM_NUM REG_ACCESS(RoReg, 0x40034000U) /**< \brief (UDP) Frame Number Register */ -#define REG_UDP_GLB_STAT REG_ACCESS(RwReg, 0x40034004U) /**< \brief (UDP) Global State Register */ -#define REG_UDP_FADDR REG_ACCESS(RwReg, 0x40034008U) /**< \brief (UDP) Function Address Register */ -#define REG_UDP_IER REG_ACCESS(WoReg, 0x40034010U) /**< \brief (UDP) Interrupt Enable Register */ -#define REG_UDP_IDR REG_ACCESS(WoReg, 0x40034014U) /**< \brief (UDP) Interrupt Disable Register */ -#define REG_UDP_IMR REG_ACCESS(RoReg, 0x40034018U) /**< \brief (UDP) Interrupt Mask Register */ -#define REG_UDP_ISR REG_ACCESS(RoReg, 0x4003401CU) /**< \brief (UDP) Interrupt Status Register */ -#define REG_UDP_ICR REG_ACCESS(WoReg, 0x40034020U) /**< \brief (UDP) Interrupt Clear Register */ -#define REG_UDP_RST_EP REG_ACCESS(RwReg, 0x40034028U) /**< \brief (UDP) Reset Endpoint Register */ -#define REG_UDP_CSR REG_ACCESS(RwReg, 0x4003402CU) /**< \brief (UDP) Endpoint Control and Status Register (ept_num = 0) */ -#define REG_UDP_FDR REG_ACCESS(RwReg, 0x4003404CU) /**< \brief (UDP) Endpoint FIFO Data Register (ept_num = 0) */ -#define REG_UDP_TXVC REG_ACCESS(RwReg, 0x40034074U) /**< \brief (UDP) Transceiver Control Register */ -/* ========== Register definition for ADC peripheral ========== */ -#define REG_ADC_CR REG_ACCESS(WoReg, 0x40038000U) /**< \brief (ADC) Control Register */ -#define REG_ADC_MR REG_ACCESS(RwReg, 0x40038004U) /**< \brief (ADC) Mode Register */ -#define REG_ADC_SEQ1R REG_ACCESS(RwReg, 0x40038008U) /**< \brief (ADC) Channel Sequence 1Register */ -#define REG_ADC_SEQ2R REG_ACCESS(RwReg, 0x4003800CU) /**< \brief (ADC) Channel Sequence 2 Register */ -#define REG_ADC_CHER REG_ACCESS(WoReg, 0x40038010U) /**< \brief (ADC) Channel Enable Register */ -#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x40038014U) /**< \brief (ADC) Channel Disable Register */ -#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x40038018U) /**< \brief (ADC) Channel Status Register */ -#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x40038020U) /**< \brief (ADC) Last Converted Data Register */ -#define REG_ADC_IER REG_ACCESS(WoReg, 0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ -#define REG_ADC_IDR REG_ACCESS(WoReg, 0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ -#define REG_ADC_IMR REG_ACCESS(RoReg, 0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ -#define REG_ADC_ISR REG_ACCESS(RoReg, 0x40038030U) /**< \brief (ADC) Interrupt Status Register */ -#define REG_ADC_OVER REG_ACCESS(RoReg, 0x4003803CU) /**< \brief (ADC) Overrun Status Register */ -#define REG_ADC_EMR REG_ACCESS(RwReg, 0x40038040U) /**< \brief (ADC) Extended Mode Register */ -#define REG_ADC_CWR REG_ACCESS(RwReg, 0x40038044U) /**< \brief (ADC) Compare Window Register */ -#define REG_ADC_CGR REG_ACCESS(RwReg, 0x40038048U) /**< \brief (ADC) Channel Gain Register */ -#define REG_ADC_COR REG_ACCESS(RwReg, 0x4003804CU) /**< \brief (ADC) Channel Offset Register */ -#define REG_ADC_CDR0 REG_ACCESS(RoReg, 0x40038050U) /**< \brief (ADC) Channel Data Register 0 */ -#define REG_ADC_CDR1 REG_ACCESS(RoReg, 0x40038054U) /**< \brief (ADC) Channel Data Register 1 */ -#define REG_ADC_CDR2 REG_ACCESS(RoReg, 0x40038058U) /**< \brief (ADC) Channel Data Register 2 */ -#define REG_ADC_CDR3 REG_ACCESS(RoReg, 0x4003805CU) /**< \brief (ADC) Channel Data Register 3 */ -#define REG_ADC_CDR4 REG_ACCESS(RoReg, 0x40038060U) /**< \brief (ADC) Channel Data Register 4 */ -#define REG_ADC_CDR5 REG_ACCESS(RoReg, 0x40038064U) /**< \brief (ADC) Channel Data Register 5 */ -#define REG_ADC_CDR6 REG_ACCESS(RoReg, 0x40038068U) /**< \brief (ADC) Channel Data Register 6 */ -#define REG_ADC_CDR15 REG_ACCESS(RoReg, 0x4003806CU) /**< \brief (ADC) Channel Data Register 15 */ -#define REG_ADC_ACR REG_ACCESS(RwReg, 0x40038094U) /**< \brief (ADC) Analog Control Register */ -#define REG_ADC_WPMR REG_ACCESS(RwReg, 0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */ -#define REG_ADC_WPSR REG_ACCESS(RoReg, 0x400380E8U) /**< \brief (ADC) Write Protect Status Register */ -#define REG_ADC_RPR REG_ACCESS(RwReg, 0x40038100U) /**< \brief (ADC) Receive Pointer Register */ -#define REG_ADC_RCR REG_ACCESS(RwReg, 0x40038104U) /**< \brief (ADC) Receive Counter Register */ -#define REG_ADC_TPR REG_ACCESS(RwReg, 0x40038108U) /**< \brief (ADC) Transmit Pointer Register */ -#define REG_ADC_TCR REG_ACCESS(RwReg, 0x4003810CU) /**< \brief (ADC) Transmit Counter Register */ -#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ -#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ -#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */ -#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */ -#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x40038120U) /**< \brief (ADC) Transfer Control Register */ -#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x40038124U) /**< \brief (ADC) Transfer Status Register */ -/* ========== Register definition for DACC peripheral ========== */ -#define REG_DACC_CR REG_ACCESS(WoReg, 0x4003C000U) /**< \brief (DACC) Control Register */ -#define REG_DACC_MR REG_ACCESS(RwReg, 0x4003C004U) /**< \brief (DACC) Mode Register */ -#define REG_DACC_CHER REG_ACCESS(WoReg, 0x4003C010U) /**< \brief (DACC) Channel Enable Register */ -#define REG_DACC_CHDR REG_ACCESS(WoReg, 0x4003C014U) /**< \brief (DACC) Channel Disable Register */ -#define REG_DACC_CHSR REG_ACCESS(RoReg, 0x4003C018U) /**< \brief (DACC) Channel Status Register */ -#define REG_DACC_CDR REG_ACCESS(WoReg, 0x4003C020U) /**< \brief (DACC) Conversion Data Register */ -#define REG_DACC_IER REG_ACCESS(WoReg, 0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */ -#define REG_DACC_IDR REG_ACCESS(WoReg, 0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */ -#define REG_DACC_IMR REG_ACCESS(RoReg, 0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */ -#define REG_DACC_ISR REG_ACCESS(RoReg, 0x4003C030U) /**< \brief (DACC) Interrupt Status Register */ -#define REG_DACC_ACR REG_ACCESS(RwReg, 0x4003C094U) /**< \brief (DACC) Analog Current Register */ -#define REG_DACC_WPMR REG_ACCESS(RwReg, 0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */ -#define REG_DACC_WPSR REG_ACCESS(RoReg, 0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */ -#define REG_DACC_RPR REG_ACCESS(RwReg, 0x4003C100U) /**< \brief (DACC) Receive Pointer Register */ -#define REG_DACC_RCR REG_ACCESS(RwReg, 0x4003C104U) /**< \brief (DACC) Receive Counter Register */ -#define REG_DACC_TPR REG_ACCESS(RwReg, 0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */ -#define REG_DACC_TCR REG_ACCESS(RwReg, 0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */ -#define REG_DACC_RNPR REG_ACCESS(RwReg, 0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */ -#define REG_DACC_RNCR REG_ACCESS(RwReg, 0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */ -#define REG_DACC_TNPR REG_ACCESS(RwReg, 0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */ -#define REG_DACC_TNCR REG_ACCESS(RwReg, 0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */ -#define REG_DACC_PTCR REG_ACCESS(WoReg, 0x4003C120U) /**< \brief (DACC) Transfer Control Register */ -#define REG_DACC_PTSR REG_ACCESS(RoReg, 0x4003C124U) /**< \brief (DACC) Transfer Status Register */ -/* ========== Register definition for ACC peripheral ========== */ -#define REG_ACC_CR REG_ACCESS(WoReg, 0x40040000U) /**< \brief (ACC) Control Register */ -#define REG_ACC_MR REG_ACCESS(RwReg, 0x40040004U) /**< \brief (ACC) Mode Register */ -#define REG_ACC_IER REG_ACCESS(WoReg, 0x40040024U) /**< \brief (ACC) Interrupt Enable Register */ -#define REG_ACC_IDR REG_ACCESS(WoReg, 0x40040028U) /**< \brief (ACC) Interrupt Disable Register */ -#define REG_ACC_IMR REG_ACCESS(RoReg, 0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */ -#define REG_ACC_ISR REG_ACCESS(RoReg, 0x40040030U) /**< \brief (ACC) Interrupt Status Register */ -#define REG_ACC_ACR REG_ACCESS(RwReg, 0x40040094U) /**< \brief (ACC) Analog Control Register */ -#define REG_ACC_WPMR REG_ACCESS(RwReg, 0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */ -#define REG_ACC_WPSR REG_ACCESS(RoReg, 0x400400E8U) /**< \brief (ACC) Write Protect Status Register */ -/* ========== Register definition for CRCCU peripheral ========== */ -#define REG_CRCCU_DSCR REG_ACCESS(RwReg, 0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ -#define REG_CRCCU_DMA_EN REG_ACCESS(WoReg, 0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ -#define REG_CRCCU_DMA_DIS REG_ACCESS(WoReg, 0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ -#define REG_CRCCU_DMA_SR REG_ACCESS(RoReg, 0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ -#define REG_CRCCU_DMA_IER REG_ACCESS(WoReg, 0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ -#define REG_CRCCU_DMA_IDR REG_ACCESS(WoReg, 0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ -#define REG_CRCCU_DMA_IMR REG_ACCESS(RoReg, 0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ -#define REG_CRCCU_DMA_ISR REG_ACCESS(RoReg, 0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ -#define REG_CRCCU_CR REG_ACCESS(WoReg, 0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */ -#define REG_CRCCU_MR REG_ACCESS(RwReg, 0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */ -#define REG_CRCCU_SR REG_ACCESS(RoReg, 0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */ -#define REG_CRCCU_IER REG_ACCESS(WoReg, 0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ -#define REG_CRCCU_IDR REG_ACCESS(WoReg, 0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ -#define REG_CRCCU_IMR REG_ACCESS(RoReg, 0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ -#define REG_CRCCU_ISR REG_ACCESS(RoReg, 0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ -/* ========== Register definition for SMC peripheral ========== */ -#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ -#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ -#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ -#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ -#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ -#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ -#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ -#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ -#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ -#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ -#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ -#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ -#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ -#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ -#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ -#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ -#define REG_SMC_SETUP4 REG_ACCESS(RwReg, 0x400E0040U) /**< \brief (SMC) SMC Setup Register (CS_number = 4) */ -#define REG_SMC_PULSE4 REG_ACCESS(RwReg, 0x400E0044U) /**< \brief (SMC) SMC Pulse Register (CS_number = 4) */ -#define REG_SMC_CYCLE4 REG_ACCESS(RwReg, 0x400E0048U) /**< \brief (SMC) SMC Cycle Register (CS_number = 4) */ -#define REG_SMC_MODE4 REG_ACCESS(RwReg, 0x400E004CU) /**< \brief (SMC) SMC Mode Register (CS_number = 4) */ -#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */ -#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ -#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ -#define REG_SMC_WPMR REG_ACCESS(RwReg, 0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ -#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */ -/* ========== Register definition for MATRIX peripheral ========== */ -#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ -#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ -#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ -#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ -#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ -#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ -#define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ -#define REG_MATRIX_SYSIO REG_ACCESS(RwReg, 0x400E0314U) /**< \brief (MATRIX) System IO Configuration register */ -#define REG_MATRIX_SMCNFCS REG_ACCESS(RwReg, 0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */ -#define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ -#define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ -/* ========== Register definition for PMC peripheral ========== */ -#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ -#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ -#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */ -#define REG_PMC_PCER0 REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ -#define REG_PMC_PCDR0 REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ -#define REG_PMC_PCSR0 REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ -#define REG_PMC_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ -#define REG_PMC_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ -#define REG_PMC_PLLAR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */ -#define REG_PMC_PLLBR REG_ACCESS(RwReg, 0x400E042CU) /**< \brief (PMC) PLLB Register */ -#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */ -#define REG_PMC_USB REG_ACCESS(RwReg, 0x400E0438U) /**< \brief (PMC) USB Clock Register */ -#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ -#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ -#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ -#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */ -#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ -#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ -#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ -#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ -#define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ -#define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ -#define REG_PMC_PCER1 REG_ACCESS(WoReg, 0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ -#define REG_PMC_PCDR1 REG_ACCESS(WoReg, 0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ -#define REG_PMC_PCSR1 REG_ACCESS(RoReg, 0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ -#define REG_PMC_OCR REG_ACCESS(RwReg, 0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ -/* ========== Register definition for UART0 peripheral ========== */ -#define REG_UART0_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART0) Control Register */ -#define REG_UART0_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART0) Mode Register */ -#define REG_UART0_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */ -#define REG_UART0_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */ -#define REG_UART0_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */ -#define REG_UART0_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART0) Status Register */ -#define REG_UART0_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART0) Receive Holding Register */ -#define REG_UART0_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART0) Transmit Holding Register */ -#define REG_UART0_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */ -#define REG_UART0_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART0) Receive Pointer Register */ -#define REG_UART0_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART0) Receive Counter Register */ -#define REG_UART0_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */ -#define REG_UART0_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART0) Transmit Counter Register */ -#define REG_UART0_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */ -#define REG_UART0_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */ -#define REG_UART0_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */ -#define REG_UART0_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */ -#define REG_UART0_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART0) Transfer Control Register */ -#define REG_UART0_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART0) Transfer Status Register */ -/* ========== Register definition for CHIPID peripheral ========== */ -#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ -#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ -/* ========== Register definition for UART1 peripheral ========== */ -#define REG_UART1_CR REG_ACCESS(WoReg, 0x400E0800U) /**< \brief (UART1) Control Register */ -#define REG_UART1_MR REG_ACCESS(RwReg, 0x400E0804U) /**< \brief (UART1) Mode Register */ -#define REG_UART1_IER REG_ACCESS(WoReg, 0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */ -#define REG_UART1_IDR REG_ACCESS(WoReg, 0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */ -#define REG_UART1_IMR REG_ACCESS(RoReg, 0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */ -#define REG_UART1_SR REG_ACCESS(RoReg, 0x400E0814U) /**< \brief (UART1) Status Register */ -#define REG_UART1_RHR REG_ACCESS(RoReg, 0x400E0818U) /**< \brief (UART1) Receive Holding Register */ -#define REG_UART1_THR REG_ACCESS(WoReg, 0x400E081CU) /**< \brief (UART1) Transmit Holding Register */ -#define REG_UART1_BRGR REG_ACCESS(RwReg, 0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */ -#define REG_UART1_RPR REG_ACCESS(RwReg, 0x400E0900U) /**< \brief (UART1) Receive Pointer Register */ -#define REG_UART1_RCR REG_ACCESS(RwReg, 0x400E0904U) /**< \brief (UART1) Receive Counter Register */ -#define REG_UART1_TPR REG_ACCESS(RwReg, 0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */ -#define REG_UART1_TCR REG_ACCESS(RwReg, 0x400E090CU) /**< \brief (UART1) Transmit Counter Register */ -#define REG_UART1_RNPR REG_ACCESS(RwReg, 0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */ -#define REG_UART1_RNCR REG_ACCESS(RwReg, 0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */ -#define REG_UART1_TNPR REG_ACCESS(RwReg, 0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */ -#define REG_UART1_TNCR REG_ACCESS(RwReg, 0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */ -#define REG_UART1_PTCR REG_ACCESS(WoReg, 0x400E0920U) /**< \brief (UART1) Transfer Control Register */ -#define REG_UART1_PTSR REG_ACCESS(RoReg, 0x400E0924U) /**< \brief (UART1) Transfer Status Register */ -/* ========== Register definition for EFC peripheral ========== */ -#define REG_EFC_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ -#define REG_EFC_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ -#define REG_EFC_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ -#define REG_EFC_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ -/* ========== Register definition for PIOA peripheral ========== */ -#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ -#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ -#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ -#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ -#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ -#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOA) Output Status Register */ -#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ -#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ -#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ -#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ -#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ -#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ -#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ -#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ -#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ -#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ -#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ -#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ -#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ -#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ -#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ -#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ -#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ -#define REG_PIOA_ABCDSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ -#define REG_PIOA_SCIFSR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ -#define REG_PIOA_DIFSR REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ -#define REG_PIOA_IFDGSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ -#define REG_PIOA_PPDDR REG_ACCESS(WoReg, 0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ -#define REG_PIOA_PPDER REG_ACCESS(WoReg, 0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ -#define REG_PIOA_PPDSR REG_ACCESS(RoReg, 0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ -#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ -#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ -#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ -#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ -#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ -#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ -#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ -#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ -#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ -#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ -#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ -#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ -#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOA) Lock Status */ -#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ -#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ -#define REG_PIOA_SCHMITT REG_ACCESS(RwReg, 0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ -#define REG_PIOA_PCMR REG_ACCESS(RwReg, 0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ -#define REG_PIOA_PCIER REG_ACCESS(WoReg, 0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ -#define REG_PIOA_PCIDR REG_ACCESS(WoReg, 0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ -#define REG_PIOA_PCIMR REG_ACCESS(RoReg, 0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ -#define REG_PIOA_PCISR REG_ACCESS(RoReg, 0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ -#define REG_PIOA_PCRHR REG_ACCESS(RoReg, 0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ -/* ========== Register definition for PIOB peripheral ========== */ -#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ -#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ -#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOB) PIO Status Register */ -#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOB) Output Enable Register */ -#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOB) Output Disable Register */ -#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOB) Output Status Register */ -#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ -#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ -#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ -#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ -#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ -#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ -#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ -#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ -#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ -#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ -#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ -#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ -#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ -#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ -#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ -#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ -#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ -#define REG_PIOB_ABCDSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ -#define REG_PIOB_SCIFSR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ -#define REG_PIOB_DIFSR REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ -#define REG_PIOB_IFDGSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ -#define REG_PIOB_PPDDR REG_ACCESS(WoReg, 0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ -#define REG_PIOB_PPDER REG_ACCESS(WoReg, 0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ -#define REG_PIOB_PPDSR REG_ACCESS(RoReg, 0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ -#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ -#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ -#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ -#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ -#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ -#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ -#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ -#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOB) Level Select Register */ -#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ -#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ -#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ -#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ -#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOB) Lock Status */ -#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ -#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ -#define REG_PIOB_SCHMITT REG_ACCESS(RwReg, 0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ -#define REG_PIOB_PCMR REG_ACCESS(RwReg, 0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ -#define REG_PIOB_PCIER REG_ACCESS(WoReg, 0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ -#define REG_PIOB_PCIDR REG_ACCESS(WoReg, 0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ -#define REG_PIOB_PCIMR REG_ACCESS(RoReg, 0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ -#define REG_PIOB_PCISR REG_ACCESS(RoReg, 0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ -#define REG_PIOB_PCRHR REG_ACCESS(RoReg, 0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ -/* ========== Register definition for PIOC peripheral ========== */ -#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ -#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ -#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1208U) /**< \brief (PIOC) PIO Status Register */ -#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (PIOC) Output Enable Register */ -#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1214U) /**< \brief (PIOC) Output Disable Register */ -#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1218U) /**< \brief (PIOC) Output Status Register */ -#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ -#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ -#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ -#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ -#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ -#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ -#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ -#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ -#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ -#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ -#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ -#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ -#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ -#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ -#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ -#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ -#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ -#define REG_PIOC_ABCDSR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ -#define REG_PIOC_SCIFSR REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ -#define REG_PIOC_DIFSR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ -#define REG_PIOC_IFDGSR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ -#define REG_PIOC_PPDDR REG_ACCESS(WoReg, 0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ -#define REG_PIOC_PPDER REG_ACCESS(WoReg, 0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ -#define REG_PIOC_PPDSR REG_ACCESS(RoReg, 0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ -#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ -#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ -#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ -#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ -#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ -#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ -#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ -#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E12C4U) /**< \brief (PIOC) Level Select Register */ -#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ -#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ -#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ -#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ -#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E12E0U) /**< \brief (PIOC) Lock Status */ -#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ -#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ -#define REG_PIOC_SCHMITT REG_ACCESS(RwReg, 0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ -#define REG_PIOC_PCMR REG_ACCESS(RwReg, 0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ -#define REG_PIOC_PCIER REG_ACCESS(WoReg, 0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ -#define REG_PIOC_PCIDR REG_ACCESS(WoReg, 0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ -#define REG_PIOC_PCIMR REG_ACCESS(RoReg, 0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ -#define REG_PIOC_PCISR REG_ACCESS(RoReg, 0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ -#define REG_PIOC_PCRHR REG_ACCESS(RoReg, 0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ -/* ========== Register definition for RSTC peripheral ========== */ -#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1400U) /**< \brief (RSTC) Control Register */ -#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1404U) /**< \brief (RSTC) Status Register */ -#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1408U) /**< \brief (RSTC) Mode Register */ -/* ========== Register definition for SUPC peripheral ========== */ -#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ -#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ -#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ -#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ -#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ -#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ -/* ========== Register definition for RTT peripheral ========== */ -#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1430U) /**< \brief (RTT) Mode Register */ -#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1434U) /**< \brief (RTT) Alarm Register */ -#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1438U) /**< \brief (RTT) Value Register */ -#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E143CU) /**< \brief (RTT) Status Register */ -/* ========== Register definition for WDT peripheral ========== */ -#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1450U) /**< \brief (WDT) Control Register */ -#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1454U) /**< \brief (WDT) Mode Register */ -#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1458U) /**< \brief (WDT) Status Register */ -/* ========== Register definition for RTC peripheral ========== */ -#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1460U) /**< \brief (RTC) Control Register */ -#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1464U) /**< \brief (RTC) Mode Register */ -#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1468U) /**< \brief (RTC) Time Register */ -#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E146CU) /**< \brief (RTC) Calendar Register */ -#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1470U) /**< \brief (RTC) Time Alarm Register */ -#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ -#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1478U) /**< \brief (RTC) Status Register */ -#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ -#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ -#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ -#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ -#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E148CU) /**< \brief (RTC) Valid Entry Register */ -/* ========== Register definition for GPBR peripheral ========== */ -#define REG_GPBR_GPBR0 REG_ACCESS(RwReg, 0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register 0 */ -#define REG_GPBR_GPBR1 REG_ACCESS(RwReg, 0x400E1494U) /**< \brief (GPBR) General Purpose Backup Register 1 */ -#define REG_GPBR_GPBR2 REG_ACCESS(RwReg, 0x400E1498U) /**< \brief (GPBR) General Purpose Backup Register 2 */ -#define REG_GPBR_GPBR3 REG_ACCESS(RwReg, 0x400E149CU) /**< \brief (GPBR) General Purpose Backup Register 3 */ -/*@}*/ - -/* ***************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */ -#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ -#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ -#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */ -#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ -#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ -#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ -#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ -#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ -#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ -#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ -#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ -#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ -#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ -#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ -#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ -#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ -#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ -#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ -#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ -#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ -#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ -/*@}*/ - -/* ***************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_base Peripheral Base Address Definitions */ -/*@{*/ - -#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define PDC_HSMCI CAST(Pdc , 0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ -#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */ -#define PDC_SSC CAST(Pdc , 0x40004100U) /**< \brief (PDC_SSC ) Base Address */ -#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */ -#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */ -#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */ -#define TC1 CAST(Tc , 0x40014000U) /**< \brief (TC1 ) Base Address */ -#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 CAST(Pdc , 0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM CAST(Pdc , 0x40020100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 CAST(Usart , 0x40028000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 CAST(Pdc , 0x40028100U) /**< \brief (PDC_USART1) Base Address */ -#define UDP CAST(Udp , 0x40034000U) /**< \brief (UDP ) Base Address */ -#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */ -#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */ -#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ -#define ACC CAST(Acc , 0x40040000U) /**< \brief (ACC ) Base Address */ -#define CRCCU CAST(Crccu , 0x40044000U) /**< \brief (CRCCU ) Base Address */ -#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */ -#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */ -#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */ -#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ -#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */ -#define PDC_UART1 CAST(Pdc , 0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ -#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */ -#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */ -#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */ -#define PIOC CAST(Pio , 0x400E1200U) /**< \brief (PIOC ) Base Address */ -#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */ -#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */ -#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */ -#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */ -#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */ -#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */ -/*@}*/ - -/* ***************************************************************************** */ -/* PIO DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3S_pio Peripheral Pio Definitions */ -/*@{*/ - -#define PIO_PA0 (1 << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1 << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1 << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1 << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1 << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1 << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1 << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1 << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1 << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1 << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1 << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1 << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1 << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1 << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1 << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1 << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1 << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1 << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1 << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1 << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1 << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1 << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1 << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1 << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1 << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1 << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1 << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1 << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1 << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1 << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1 << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1 << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1 << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1 << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1 << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1 << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1 << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1 << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1 << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1 << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1 << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1 << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1 << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1 << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1 << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1 << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1 << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PC0 (1 << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1 << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1 << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1 << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1 << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1 << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1 << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1 << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1 << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1 << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1 << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1 << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1 << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1 << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1 << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1 << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1 << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1 << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1 << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1 << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1 << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1 << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1 << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1 << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1 << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1 << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1 << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1 << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1 << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1 << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1 << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PC31 (1 << 31) /**< \brief Pin Controlled by PC31 */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA28C_MCCDA (1 << 28) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PA29C_MCCK (1 << 29) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA30C_MCDA0 (1 << 30) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA31C_MCDA1 (1 << 31) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA26C_MCDA2 (1 << 26) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA27C_MCDA3 (1 << 27) /**< \brief Hsmci signal: MCDA3 */ -/* ========== Pio definition for SSC peripheral ========== */ -#define PIO_PA18A_RD (1 << 18) /**< \brief Ssc signal: RD */ -#define PIO_PA20A_RF (1 << 20) /**< \brief Ssc signal: RF */ -#define PIO_PA19A_RK (1 << 19) /**< \brief Ssc signal: RK */ -#define PIO_PA17A_TD (1 << 17) /**< \brief Ssc signal: TD */ -#define PIO_PA15A_TF (1 << 15) /**< \brief Ssc signal: TF */ -#define PIO_PA16A_TK (1 << 16) /**< \brief Ssc signal: TK */ -/* ========== Pio definition for SPI peripheral ========== */ -#define PIO_PA12A_MISO (1 << 12) /**< \brief Spi signal: MISO */ -#define PIO_PA13A_MOSI (1 << 13) /**< \brief Spi signal: MOSI */ -#define PIO_PA11A_NPCS0 (1 << 11) /**< \brief Spi signal: NPCS0 */ -#define PIO_PA31A_NPCS1 (1 << 31) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA9B_NPCS1 (1 << 9) /**< \brief Spi signal: NPCS1 */ -#define PIO_PB14A_NPCS1 (1 << 14) /**< \brief Spi signal: NPCS1 */ -#define PIO_PC4B_NPCS1 (1 << 4) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA10B_NPCS2 (1 << 10) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA30B_NPCS2 (1 << 30) /**< \brief Spi signal: NPCS2 */ -#define PIO_PB2B_NPCS2 (1 << 2) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA22B_NPCS3 (1 << 22) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA3B_NPCS3 (1 << 3) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA5B_NPCS3 (1 << 5) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA14A_SPCK (1 << 14) /**< \brief Spi signal: SPCK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA4B_TCLK0 (1 << 4) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PA28B_TCLK1 (1 << 28) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA29B_TCLK2 (1 << 29) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA0B_TIOA0 (1 << 0) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PA15B_TIOA1 (1 << 15) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA26B_TIOA2 (1 << 26) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA1B_TIOB0 (1 << 1) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PA16B_TIOB1 (1 << 16) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA27B_TIOB2 (1 << 27) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TC1 peripheral ========== */ -#define PIO_PC25B_TCLK3 (1 << 25) /**< \brief Tc1 signal: TCLK3 */ -#define PIO_PC28B_TCLK4 (1 << 28) /**< \brief Tc1 signal: TCLK4 */ -#define PIO_PC31B_TCLK5 (1 << 31) /**< \brief Tc1 signal: TCLK5 */ -#define PIO_PC23B_TIOA3 (1 << 23) /**< \brief Tc1 signal: TIOA3 */ -#define PIO_PC26B_TIOA4 (1 << 26) /**< \brief Tc1 signal: TIOA4 */ -#define PIO_PC29B_TIOA5 (1 << 29) /**< \brief Tc1 signal: TIOA5 */ -#define PIO_PC24B_TIOB3 (1 << 24) /**< \brief Tc1 signal: TIOB3 */ -#define PIO_PC27B_TIOB4 (1 << 27) /**< \brief Tc1 signal: TIOB4 */ -#define PIO_PC30B_TIOB5 (1 << 30) /**< \brief Tc1 signal: TIOB5 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA4A_TWCK0 (1 << 4) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA3A_TWD0 (1 << 3) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PB5A_TWCK1 (1 << 5) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PB4A_TWD1 (1 << 4) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA9C_PWMFI0 (1 << 9) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA11B_PWMH0 (1 << 11) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA23B_PWMH0 (1 << 23) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC18B_PWMH0 (1 << 18) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA12B_PWMH1 (1 << 12) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA24B_PWMH1 (1 << 24) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC19B_PWMH1 (1 << 19) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA13B_PWMH2 (1 << 13) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA2A_PWMH2 (1 << 2) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA25B_PWMH2 (1 << 25) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB4B_PWMH2 (1 << 4) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC20B_PWMH2 (1 << 20) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA17C_PWMH3 (1 << 17) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA7B_PWMH3 (1 << 7) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB14B_PWMH3 (1 << 14) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC21B_PWMH3 (1 << 21) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA19B_PWML0 (1 << 19) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB5B_PWML0 (1 << 5) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC0B_PWML0 (1 << 0) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC13B_PWML0 (1 << 13) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA20B_PWML1 (1 << 20) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB12A_PWML1 (1 << 12) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC1B_PWML1 (1 << 1) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC15B_PWML1 (1 << 15) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA16C_PWML2 (1 << 16) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA30A_PWML2 (1 << 30) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB13A_PWML2 (1 << 13) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC2B_PWML2 (1 << 2) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA15C_PWML3 (1 << 15) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC22B_PWML3 (1 << 22) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC3B_PWML3 (1 << 3) /**< \brief Pwm signal: PWML3 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PA8A_CTS0 (1 << 8) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PA7A_RTS0 (1 << 7) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PA5A_RXD0 (1 << 5) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PA2B_SCK0 (1 << 2) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PA6A_TXD0 (1 << 6) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA25A_CTS1 (1 << 25) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA26A_DCD1 (1 << 26) /**< \brief Usart1 signal: DCD1 */ -#define PIO_PA28A_DSR1 (1 << 28) /**< \brief Usart1 signal: DSR1 */ -#define PIO_PA27A_DTR1 (1 << 27) /**< \brief Usart1 signal: DTR1 */ -#define PIO_PA29A_RI1 (1 << 29) /**< \brief Usart1 signal: RI1 */ -#define PIO_PA24A_RTS1 (1 << 24) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA21A_RXD1 (1 << 21) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA23A_SCK1 (1 << 23) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA22A_TXD1 (1 << 22) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA17X1_AD0 (1 << 17) /**< \brief Adc signal: AD0 */ -#define PIO_PA18X1_AD1 (1 << 18) /**< \brief Adc signal: AD1 */ -#define PIO_PC13X1_AD10 (1 << 13) /**< \brief Adc signal: AD10 */ -#define PIO_PC15X1_AD11 (1 << 15) /**< \brief Adc signal: AD11 */ -#define PIO_PC12X1_AD12 (1 << 12) /**< \brief Adc signal: AD12 */ -#define PIO_PC29X1_AD13 (1 << 29) /**< \brief Adc signal: AD13 */ -#define PIO_PC30X1_AD14 (1 << 30) /**< \brief Adc signal: AD14 */ -#define PIO_PA19X1_AD2 (1 << 19) /**< \brief Adc signal: AD2 */ -#define PIO_PA20X1_AD3 (1 << 20) /**< \brief Adc signal: AD3 */ -#define PIO_PB0X1_AD4 (1 << 0) /**< \brief Adc signal: AD4 */ -#define PIO_PB1X1_AD5 (1 << 1) /**< \brief Adc signal: AD5 */ -#define PIO_PB2X1_AD6 (1 << 2) /**< \brief Adc signal: AD6 */ -#define PIO_PB3X1_AD7 (1 << 3) /**< \brief Adc signal: AD7 */ -#define PIO_PA21X1_AD8 (1 << 21) /**< \brief Adc signal: AD8 */ -#define PIO_PA22X1_AD9 (1 << 22) /**< \brief Adc signal: AD9 */ -#define PIO_PA8B_ADTRG (1 << 8) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for DACC peripheral ========== */ -#define PIO_PB13X1_DAC0 (1 << 13) /**< \brief Dacc signal: DAC0 */ -#define PIO_PB14X1_DAC1 (1 << 14) /**< \brief Dacc signal: DAC1 */ -#define PIO_PA2C_DATRG (1 << 2) /**< \brief Dacc signal: DATRG */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA6B_PCK0 (1 << 6) /**< \brief Pmc signal: PCK0 */ -#define PIO_PB13B_PCK0 (1 << 13) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA17B_PCK1 (1 << 17) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA21B_PCK1 (1 << 21) /**< \brief Pmc signal: PCK1 */ -#define PIO_PA18B_PCK2 (1 << 18) /**< \brief Pmc signal: PCK2 */ -#define PIO_PA31B_PCK2 (1 << 31) /**< \brief Pmc signal: PCK2 */ -#define PIO_PB3B_PCK2 (1 << 3) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for UART0 peripheral ========== */ -#define PIO_PA9A_URXD0 (1 << 9) /**< \brief Uart0 signal: URXD0 */ -#define PIO_PA10A_UTXD0 (1 << 10) /**< \brief Uart0 signal: UTXD0 */ -/* ========== Pio definition for UART1 peripheral ========== */ -#define PIO_PB2A_URXD1 (1 << 2) /**< \brief Uart1 signal: URXD1 */ -#define PIO_PB3A_UTXD1 (1 << 3) /**< \brief Uart1 signal: UTXD1 */ -/* ========== Pio definition for PIOA peripheral ========== */ -#define PIO_PA24X1_PIODC0 (1 << 24) /**< \brief Pioa signal: PIODC0 */ -#define PIO_PA25X1_PIODC1 (1 << 25) /**< \brief Pioa signal: PIODC1 */ -#define PIO_PA26X1_PIODC2 (1 << 26) /**< \brief Pioa signal: PIODC2 */ -#define PIO_PA27X1_PIODC3 (1 << 27) /**< \brief Pioa signal: PIODC3 */ -#define PIO_PA28X1_PIODC4 (1 << 28) /**< \brief Pioa signal: PIODC4 */ -#define PIO_PA29X1_PIODC5 (1 << 29) /**< \brief Pioa signal: PIODC5 */ -#define PIO_PA30X1_PIODC6 (1 << 30) /**< \brief Pioa signal: PIODC6 */ -#define PIO_PA31X1_PIODC7 (1 << 31) /**< \brief Pioa signal: PIODC7 */ -#define PIO_PA23X1_PIODCCLK (1 << 23) /**< \brief Pioa signal: PIODCCLK */ -#define PIO_PA15X1_PIODCEN1 (1 << 15) /**< \brief Pioa signal: PIODCEN1 */ -#define PIO_PA16X1_PIODCEN2 (1 << 16) /**< \brief Pioa signal: PIODCEN2 */ -/*@}*/ - -/* ***************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR AT91SAM3S */ -/* ***************************************************************************** */ - -#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -#define AT91C_IFLASH (0x00400000) /**< Internal Flash base address */ -#define AT91C_IROM (0x00800000) /**< Internal ROM base address */ -#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -#define AT91C_EBI_CS0 (0x60000000) /**< EBI Chip Select 0 base address */ -#define AT91C_EBI_CS1 (0x61000000) /**< EBI Chip Select 1 base address */ -#define AT91C_EBI_CS2 (0x62000000) /**< EBI Chip Select 2 base address */ -#define AT91C_EBI_CS3 (0x63000000) /**< EBI Chip Select 3 base address */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* AT91SAM3S_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/chip.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/chip.h deleted file mode 100644 index 8b6984086..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/chip.h +++ /dev/null @@ -1,130 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// Definition of AT91SAM3S4 characteristics and features -/// -/// !Usage -/// -# For ARM core feature, see "AT91SAM3S4 - ARM core features". -/// -# For IP features, see "AT91SAM3S4 - IP features". -/// -# For misc, see "AT91SAM3S4 - Misc". -//------------------------------------------------------------------------------ - -#ifndef CHIP_H -#define CHIP_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "AT91SAM3S4 - ARM core features" -/// This page lists several characteristics related to the ARM core -/// - -//ARM core features - -/// ARM core definition. -#define cortexm3 - -/// family definition. -#define at91sam3s - -//------------------------------------------------------------------------------ -/// \page "AT91SAM3S4 - IP features" -/// This page lists several characteristics related to the embedded IP -/// - -//IP FEATURES - -// EFC GPNVM number -#define CHIP_EFC_NUM_GPNVMS 3 - -/// Indicates chip has an Enhanced EFC. -#define CHIP_FLASH_EEFC - -// DMA channels number -#define CHIP_DMA_CHANNEL_NUM 4 - -// Indicate chip's MCI interface. -#define MCI2_INTERFACE - -// Indicate chip SSC has DMA interface. -#define CHIP_SSC_DMA - -// Indicate chip SPI has DMA interface. -#define CHIP_SPI_DMA - -/// Indicates chip has an UDP Full Speed. -#define CHIP_USB_UDP - -/// Indicates chip has an internal pull-up. -#define CHIP_USB_PULLUP_INTERNAL - -/// Number of USB endpoints -#define CHIP_USB_NUMENDPOINTS 8 - -/// Endpoints max paxcket size -#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) \ - ((i == 0) ? 64 : \ - ((i == 1) ? 64 : \ - ((i == 2) ? 64 : \ - ((i == 3) ? 64 : \ - ((i == 4) ? 512 : \ - ((i == 5) ? 512 : \ - ((i == 6) ? 64 : \ - ((i == 7) ? 64 : 0 )))))))) - -/// Endpoints Number of Bank -#define CHIP_USB_ENDPOINTS_BANKS(i) \ - ((i == 0) ? 1 : \ - ((i == 1) ? 2 : \ - ((i == 2) ? 2 : \ - ((i == 3) ? 1 : \ - ((i == 4) ? 2 : \ - ((i == 5) ? 2 : \ - ((i == 6) ? 2 : \ - ((i == 7) ? 2 : 0 )))))))) - -//------------------------------------------------------------------------------ -/// \page "AT91SAM3S4 - Misc " -/// This page lists misc features -/// - -//Misc - -#endif //#ifndef CHIP_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/flash.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/flash.icf deleted file mode 100644 index 65ac33120..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/flash.icf +++ /dev/null @@ -1,30 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Vector table start*/ -define symbol __ICFEDIT_vector_start__ = 0x000400000; /*Add for CMSIS*/ -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2000BFFF; -define symbol __ICFEDIT_region_ROM_start__ = 0x00400000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0043FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; -define symbol __ICFEDIT_size_heap__ = 0x200; - -export symbol __ICFEDIT_vector_start__; /*Add for CMSIS*/ -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors }; /*Add for CMSIS*/ -place in ROM_region { readonly }; -place in RAM_region { readwrite,,block CSTACK, block HEAP }; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/flash.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/flash.lds deleted file mode 100644 index 9d01841e2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/flash.lds +++ /dev/null @@ -1,81 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Linker script for running in internal FLASH on the AT91SAM3S4 - *----------------------------------------------------------------------------*/ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(ResetException) - -/* Memory Spaces Definitions */ -MEMORY -{ - sram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x0000C000 /* sram, 48K */ - flash (W!RX) : ORIGIN = 0x00400000, LENGTH = 0x00040000 /* Flash, 256K */ -} - -SECTIONS -{ - .fixed : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors)) - *(.text*) - *(.rodata*) - *(.glue_7) - *(.glue_7t) - . = ALIGN(4); - _efixed = .; /* End of text section */ - } >flash - - .relocate : AT (_efixed) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc); - *(.data); - . = ALIGN(4); - _erelocate = .; - } >sram - - .bss (NOLOAD) : { - . = ALIGN(4); - _szero = .; - *(.bss) - . = ALIGN(4); - _ezero = .; - } >sram - - /* Stack in the end of SRAM */ - _estack = 0x2000BFFC; -} -end = .; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/sram.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/sram.icf deleted file mode 100644 index 22eb374b1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/sram.icf +++ /dev/null @@ -1,27 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Vector table start*/ -define symbol __ICFEDIT_vector_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2000BFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x900; -define symbol __ICFEDIT_size_heap__ = 0x200; -/*-Exports-*/ -export symbol __ICFEDIT_vector_start__; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -/* define block RamVect with alignment = 8, size = __ICFEDIT_size_vectors__ { }; */ -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors }; -place in RAM_region { readonly, readwrite, block CSTACK, block HEAP }; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/sram.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/sram.lds deleted file mode 100644 index 2d38cfcc9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/sram.lds +++ /dev/null @@ -1,81 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Linker script for running in internal SRAM on the AT91SAM3S4 - *----------------------------------------------------------------------------*/ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(ResetException) - -/* Memory Spaces Definitions */ -MEMORY -{ - sram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x0000C000 /* sram, 48K */ -} - -SECTIONS -{ - .fixed : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors)) - *(.text*) - *(.ramfunc) - *(.rodata*) - *(.glue_7) - *(.glue_7t) - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > sram - - .relocate : AT (_efixed) - { - . = ALIGN(4); - _srelocate = .; - *(.data) - . = ALIGN(4); - _erelocate = .; - } >sram - - .bss (NOLOAD) : { - . = ALIGN(4); - _szero = .; - *(.bss) - . = ALIGN(4); - _ezero = .; - } >sram - - /* Stack in the end of SRAM */ - _estack = 0x2000BFFC; - -} -end = .; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/sram_flashloader.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/sram_flashloader.icf deleted file mode 100644 index a954d2cba..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/sram_flashloader.icf +++ /dev/null @@ -1,33 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x0; -define symbol __ICFEDIT_region_ROM_end__ = 0x0; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000040; -define symbol __ICFEDIT_region_RAM_end__ = 0x2000BFFF; - -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x0200; -define symbol __ICFEDIT_size_heap__ = 0x000; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -//initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { section .intvec }; - -place at start of RAM_region { block RamTop with fixed order {readonly, section LOWEND}}; -place at end of RAM_region { block RamBottom with fixed order {section HIGHSTART, readwrite, section .init, - block CSTACK, block HEAP}}; - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/sram_samba.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/sram_samba.lds deleted file mode 100644 index 16b1dc962..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3s4/sram_samba.lds +++ /dev/null @@ -1,91 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Linker script for running in internal SRAM on the AT91SAM3S4 - *----------------------------------------------------------------------------*/ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(entry) - -/* Memory Spaces Definitions */ -MEMORY -{ - romcodesram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x01000 - sram (W!RX) : ORIGIN = 0x20001000, LENGTH = 0x0000B000 /* sram, 48K - sizeof(romcodesram) */ -} - -/* Entry point */ -/*ENTRY (ResetException)*/ - -SECTIONS -{ - /* startup code in the .isr_vector */ - .text : - { - . = ALIGN(4); - _stext = .; - KEEP(*(.isr_vector .isr_vector.*)) - *(.mailbox) - *(.text .text.*) - *(.rodata .rodata.*) - *(.glue_7) - *(.glue_7t) - *(.gcc_except_table) - *(.rodata .rodata*) - *(.gnu.linkonce.r.*) - . = ALIGN(4); - _etext = .; - } > sram - - /* data */ - .data : - { - . = ALIGN(4); - _sidata = .; - _sdata = .; - - *(.data) - *(.data.*) - . = ALIGN(4); - _edata = .; - } > sram - - .bss (NOLOAD) : { - _szero = .; - *(.bss) - . = ALIGN(4); - _ezero = .; - } >sram - - /* Stack in SRAM */ - _sstack = 0x2000BFFC; -} -end = .; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/AT91SAM3U4.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/AT91SAM3U4.h deleted file mode 100644 index 64101aa0c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/AT91SAM3U4.h +++ /dev/null @@ -1,7439 +0,0 @@ -/* ---------------------------------------------------------------------------- */ -/* Atmel Microcontroller Software Support */ -/* ---------------------------------------------------------------------------- */ -/* Copyright (c) 2009, Atmel Corporation */ -/* */ -/* All rights reserved. */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following condition is met: */ -/* */ -/* - Redistributions of source code must retain the above copyright notice, */ -/* this list of conditions and the disclaimer below. */ -/* */ -/* Atmel's name may not be used to endorse or promote products derived from */ -/* this software without specific prior written permission. */ -/* */ -/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ -/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ -/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ -/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ -/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ -/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ -/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ -/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ -/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* ---------------------------------------------------------------------------- */ -/* */ -/* File Name : AT91SAM3U.h */ -/* Object : AT91SAM3U definitions */ -/* Generated by : AT91 SW Application Group */ -/* Generated on : 2009-09-10 */ - -#ifndef AT91SAM3U_H -#define AT91SAM3U_H - -/** \addtogroup AT91SAM3U_definitions AT91SAM3U definitions - This file defines all structures and symbols for AT91SAM3U: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __ASSEMBLY__ -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *) value) -#define REG_ACCESS(type, address) (*(type*)address) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ***************************************************************************** */ -/* CMSIS DEFINITIONS FOR AT91SAM3U */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3U_cmsis CMSIS Definitions */ - -/*@{*/ - -/** - * \brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __MPU_PRESENT 0 /**< AT91SAM3U does not provide a MPU present or not */ -#define __NVIC_PRIO_BITS 4 /**< AT91SAM3U uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ - -/**< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************/ - NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ -/****** AT91SAM3U specific Interrupt Numbers *****************************************/ - - SUPC_IRQn = 0, /**< 0 AT91SAM3U Supply Controller (SUPC) */ - RSTC_IRQn = 1, /**< 1 AT91SAM3U Reset Controller (RSTC) */ - RTC_IRQn = 2, /**< 2 AT91SAM3U Real Time Clock (RTC) */ - RTT_IRQn = 3, /**< 3 AT91SAM3U Real Time Timer (RTT) */ - WDT_IRQn = 4, /**< 4 AT91SAM3U Watchdog Timer (WDT) */ - PMC_IRQn = 5, /**< 5 AT91SAM3U Power Management Controller (PMC) */ - EFC0_IRQn = 6, /**< 6 AT91SAM3U Enhanced Embedded Flash Controller 0 (EFC0) */ - EFC1_IRQn = 7, /**< 7 AT91SAM3U Enhanced Embedded Flash Controller 1 (EFC1) */ - UART_IRQn = 8, /**< 8 AT91SAM3U Universal Asynchronous Receiver Transmitter (UART) */ - SMC_IRQn = 9, /**< 9 AT91SAM3U Static Memory Controller (SMC) */ - PIOA_IRQn = 10, /**< 10 AT91SAM3U Parallel I/O Controller A, (PIOA) */ - PIOB_IRQn = 11, /**< 11 AT91SAM3U Parallel I/O Controller B (PIOB) */ - PIOC_IRQn = 12, /**< 12 AT91SAM3U Parallel I/O Controller C (PIOC) */ - USART0_IRQn = 13, /**< 13 AT91SAM3U USART 0 (USART0) */ - USART1_IRQn = 14, /**< 14 AT91SAM3U USART 1 (USART1) */ - USART2_IRQn = 15, /**< 15 AT91SAM3U USART 2 (USART2) */ - USART3_IRQn = 16, /**< 16 AT91SAM3U USART 3 (USART3) */ - HSMCI_IRQn = 17, /**< 17 AT91SAM3U High Speed Multimedia Card Interface (HSMCI) */ - TWI0_IRQn = 18, /**< 18 AT91SAM3U Two-Wire Interface 0 (TWI0) */ - TWI1_IRQn = 19, /**< 19 AT91SAM3U Two-Wire Interface 1 (TWI1) */ - SPI_IRQn = 20, /**< 20 AT91SAM3U Serial Peripheral Interface (SPI) */ - SSC_IRQn = 21, /**< 21 AT91SAM3U Synchronous Serial Controller (SSC) */ - TC0_IRQn = 22, /**< 22 AT91SAM3U Timer Counter 0 (TC0) */ - TC1_IRQn = 23, /**< 23 AT91SAM3U Timer Counter 1 (TC1) */ - TC2_IRQn = 24, /**< 24 AT91SAM3U Timer Counter 2 (TC2) */ - PWM_IRQn = 25, /**< 25 AT91SAM3U Pulse Width Modulation Controller (PWM) */ - ADC12B_IRQn = 26, /**< 26 AT91SAM3U 12-bit ADC Controller (ADC12B) */ - ADC_IRQn = 27, /**< 27 AT91SAM3U 10-bit ADC Controller (ADC) */ - DMAC_IRQn = 28, /**< 28 AT91SAM3U DMA Controller (DMAC) */ - UDPHS_IRQn = 29, /**< 29 AT91SAM3U USB Device High Speed (UDPHS) */ -} IRQn_Type; -/*@}*/ - -/* ***************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR AT91SAM3U */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3U_api Peripheral Software API */ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_ADC12B Analog-to-digital Converter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Adc12b hardware registers */ -typedef struct { - WoReg ADC_CR; /**< \brief (Adc12b Offset: 0x00) Control Register */ - RwReg ADC_MR; /**< \brief (Adc12b Offset: 0x04) Mode Register */ - RwReg Reserved1[2]; - WoReg ADC_CHER; /**< \brief (Adc12b Offset: 0x10) Channel Enable Register */ - WoReg ADC_CHDR; /**< \brief (Adc12b Offset: 0x14) Channel Disable Register */ - RoReg ADC_CHSR; /**< \brief (Adc12b Offset: 0x18) Channel Status Register */ - RoReg ADC_SR; /**< \brief (Adc12b Offset: 0x1C) Status Register */ - RoReg ADC_LCDR; /**< \brief (Adc12b Offset: 0x20) Last Converted Data Register */ - WoReg ADC_IER; /**< \brief (Adc12b Offset: 0x24) Interrupt Enable Register */ - WoReg ADC_IDR; /**< \brief (Adc12b Offset: 0x28) Interrupt Disable Register */ - RoReg ADC_IMR; /**< \brief (Adc12b Offset: 0x2C) Interrupt Mask Register */ - RoReg ADC_CDR[8]; /**< \brief (Adc12b Offset: 0x30) Channel Data Register */ - RwReg Reserved2[5]; - RwReg ADC_ACR; /**< \brief (Adc12b Offset: 0x64) Analog Control Register */ - RwReg ADC_EMR; /**< \brief (Adc12b Offset: 0x68) Extended Mode Register */ - RwReg Reserved3[37]; - RwReg ADC_RPR; /**< \brief (Adc12b Offset: 0x100) Receive Pointer Register */ - RwReg ADC_RCR; /**< \brief (Adc12b Offset: 0x104) Receive Counter Register */ - RwReg ADC_TPR; /**< \brief (Adc12b Offset: 0x108) Transmit Pointer Register */ - RwReg ADC_TCR; /**< \brief (Adc12b Offset: 0x10C) Transmit Counter Register */ - RwReg ADC_RNPR; /**< \brief (Adc12b Offset: 0x110) Receive Next Pointer Register */ - RwReg ADC_RNCR; /**< \brief (Adc12b Offset: 0x114) Receive Next Counter Register */ - RwReg ADC_TNPR; /**< \brief (Adc12b Offset: 0x118) Transmit Next Pointer Register */ - RwReg ADC_TNCR; /**< \brief (Adc12b Offset: 0x11C) Transmit Next Counter Register */ - WoReg ADC_PTCR; /**< \brief (Adc12b Offset: 0x120) Transfer Control Register */ - RoReg ADC_PTSR; /**< \brief (Adc12b Offset: 0x124) Transfer Status Register */ -} Adc12b; -#endif /* __ASSEMBLY__ */ -/* -------- ADC_CR : (ADC12B Offset: 0x00) Control Register -------- */ -#define ADC_CR_SWRST (0x1 << 0) /**< \brief (ADC_CR) Software Reset */ -#define ADC_CR_START (0x1 << 1) /**< \brief (ADC_CR) Start Conversion */ -/* -------- ADC_MR : (ADC12B Offset: 0x04) Mode Register -------- */ -#define ADC_MR_TRGEN (0x1 << 0) /**< \brief (ADC_MR) Trigger Enable */ -#define ADC_MR_TRGSEL (0x7 << 1) /**< \brief (ADC_MR) Trigger Selection */ -#define ADC_MR_LOWRES (0x1 << 4) /**< \brief (ADC_MR) Resolution */ -#define ADC_MR_SLEEP (0x1 << 5) /**< \brief (ADC_MR) Sleep Mode */ -#define ADC_MR_PRESCAL (0xff << 8) /**< \brief (ADC_MR) Prescaler Rate Selection */ -#define ADC_MR_STARTUP (0xff << 16) /**< \brief (ADC_MR) Start Up Time */ -#define ADC_MR_SHTIM (0xf << 24) /**< \brief (ADC_MR) Sample & Hold Time */ -/* -------- ADC_CHER : (ADC12B Offset: 0x10) Channel Enable Register -------- */ -#define ADC_CHER_CH0 (0x1 << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ -#define ADC_CHER_CH1 (0x1 << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ -#define ADC_CHER_CH2 (0x1 << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ -#define ADC_CHER_CH3 (0x1 << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ -#define ADC_CHER_CH4 (0x1 << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ -#define ADC_CHER_CH5 (0x1 << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ -#define ADC_CHER_CH6 (0x1 << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ -#define ADC_CHER_CH7 (0x1 << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ -/* -------- ADC_CHDR : (ADC12B Offset: 0x14) Channel Disable Register -------- */ -#define ADC_CHDR_CH0 (0x1 << 0) /**< \brief (ADC_CHDR) */ -#define ADC_CHDR_CH1 (0x1 << 1) /**< \brief (ADC_CHDR) */ -#define ADC_CHDR_CH2 (0x1 << 2) /**< \brief (ADC_CHDR) */ -#define ADC_CHDR_CH3 (0x1 << 3) /**< \brief (ADC_CHDR) */ -#define ADC_CHDR_CH4 (0x1 << 4) /**< \brief (ADC_CHDR) */ -#define ADC_CHDR_CH5 (0x1 << 5) /**< \brief (ADC_CHDR) */ -#define ADC_CHDR_CH6 (0x1 << 6) /**< \brief (ADC_CHDR) */ -#define ADC_CHDR_CH7 (0x1 << 7) /**< \brief (ADC_CHDR) */ -/* -------- ADC_CHSR : (ADC12B Offset: 0x18) Channel Status Register -------- */ -#define ADC_CHSR_CH0 (0x1 << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ -#define ADC_CHSR_CH1 (0x1 << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ -#define ADC_CHSR_CH2 (0x1 << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ -#define ADC_CHSR_CH3 (0x1 << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ -#define ADC_CHSR_CH4 (0x1 << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ -#define ADC_CHSR_CH5 (0x1 << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ -#define ADC_CHSR_CH6 (0x1 << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ -#define ADC_CHSR_CH7 (0x1 << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ -/* -------- ADC_SR : (ADC12B Offset: 0x1C) Status Register -------- */ -#define ADC_SR_EOC0 (0x1 << 0) /**< \brief (ADC_SR) End of Conversion 0 */ -#define ADC_SR_EOC1 (0x1 << 1) /**< \brief (ADC_SR) End of Conversion 1 */ -#define ADC_SR_EOC2 (0x1 << 2) /**< \brief (ADC_SR) End of Conversion 2 */ -#define ADC_SR_EOC3 (0x1 << 3) /**< \brief (ADC_SR) End of Conversion 3 */ -#define ADC_SR_EOC4 (0x1 << 4) /**< \brief (ADC_SR) End of Conversion 4 */ -#define ADC_SR_EOC5 (0x1 << 5) /**< \brief (ADC_SR) End of Conversion 5 */ -#define ADC_SR_EOC6 (0x1 << 6) /**< \brief (ADC_SR) End of Conversion 6 */ -#define ADC_SR_EOC7 (0x1 << 7) /**< \brief (ADC_SR) End of Conversion 7 */ -#define ADC_SR_OVRE0 (0x1 << 8) /**< \brief (ADC_SR) Overrun Error 0 */ -#define ADC_SR_OVRE1 (0x1 << 9) /**< \brief (ADC_SR) Overrun Error 1 */ -#define ADC_SR_OVRE2 (0x1 << 10) /**< \brief (ADC_SR) Overrun Error 2 */ -#define ADC_SR_OVRE3 (0x1 << 11) /**< \brief (ADC_SR) Overrun Error 3 */ -#define ADC_SR_OVRE4 (0x1 << 12) /**< \brief (ADC_SR) Overrun Error 4 */ -#define ADC_SR_OVRE5 (0x1 << 13) /**< \brief (ADC_SR) Overrun Error 5 */ -#define ADC_SR_OVRE6 (0x1 << 14) /**< \brief (ADC_SR) Overrun Error 6 */ -#define ADC_SR_OVRE7 (0x1 << 15) /**< \brief (ADC_SR) Overrun Error 7 */ -#define ADC_SR_DRDY (0x1 << 16) /**< \brief (ADC_SR) Data Ready */ -#define ADC_SR_GOVRE (0x1 << 17) /**< \brief (ADC_SR) General Overrun Error */ -#define ADC_SR_ENDRX (0x1 << 18) /**< \brief (ADC_SR) End of RX Buffer */ -#define ADC_SR_RXBUFF (0x1 << 19) /**< \brief (ADC_SR) RX Buffer Full */ -/* -------- ADC_LCDR : (ADC12B Offset: 0x20) Last Converted Data Register -------- */ -#define ADC_LCDR_LDATA (0xfff << 0) /**< \brief (ADC_LCDR) Last Data Converted */ -/* -------- ADC_IER : (ADC12B Offset: 0x24) Interrupt Enable Register -------- */ -#define ADC_IER_EOC0 (0x1 << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ -#define ADC_IER_EOC1 (0x1 << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ -#define ADC_IER_EOC2 (0x1 << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ -#define ADC_IER_EOC3 (0x1 << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ -#define ADC_IER_EOC4 (0x1 << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ -#define ADC_IER_EOC5 (0x1 << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ -#define ADC_IER_EOC6 (0x1 << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ -#define ADC_IER_EOC7 (0x1 << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ -#define ADC_IER_OVRE0 (0x1 << 8) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 0 */ -#define ADC_IER_OVRE1 (0x1 << 9) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 1 */ -#define ADC_IER_OVRE2 (0x1 << 10) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 2 */ -#define ADC_IER_OVRE3 (0x1 << 11) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 3 */ -#define ADC_IER_OVRE4 (0x1 << 12) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 4 */ -#define ADC_IER_OVRE5 (0x1 << 13) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 5 */ -#define ADC_IER_OVRE6 (0x1 << 14) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 6 */ -#define ADC_IER_OVRE7 (0x1 << 15) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 7 */ -#define ADC_IER_DRDY (0x1 << 16) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ -#define ADC_IER_GOVRE (0x1 << 17) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ -#define ADC_IER_ENDRX (0x1 << 18) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ -#define ADC_IER_RXBUFF (0x1 << 19) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ -/* -------- ADC_IDR : (ADC12B Offset: 0x28) Interrupt Disable Register -------- */ -#define ADC_IDR_EOC0 (0x1 << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ -#define ADC_IDR_EOC1 (0x1 << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ -#define ADC_IDR_EOC2 (0x1 << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ -#define ADC_IDR_EOC3 (0x1 << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ -#define ADC_IDR_EOC4 (0x1 << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ -#define ADC_IDR_EOC5 (0x1 << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ -#define ADC_IDR_EOC6 (0x1 << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ -#define ADC_IDR_EOC7 (0x1 << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ -#define ADC_IDR_OVRE0 (0x1 << 8) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 0 */ -#define ADC_IDR_OVRE1 (0x1 << 9) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 1 */ -#define ADC_IDR_OVRE2 (0x1 << 10) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 2 */ -#define ADC_IDR_OVRE3 (0x1 << 11) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 3 */ -#define ADC_IDR_OVRE4 (0x1 << 12) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 4 */ -#define ADC_IDR_OVRE5 (0x1 << 13) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 5 */ -#define ADC_IDR_OVRE6 (0x1 << 14) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 6 */ -#define ADC_IDR_OVRE7 (0x1 << 15) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 7 */ -#define ADC_IDR_DRDY (0x1 << 16) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ -#define ADC_IDR_GOVRE (0x1 << 17) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ -#define ADC_IDR_ENDRX (0x1 << 18) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ -#define ADC_IDR_RXBUFF (0x1 << 19) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ -/* -------- ADC_IMR : (ADC12B Offset: 0x2C) Interrupt Mask Register -------- */ -#define ADC_IMR_EOC0 (0x1 << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ -#define ADC_IMR_EOC1 (0x1 << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ -#define ADC_IMR_EOC2 (0x1 << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ -#define ADC_IMR_EOC3 (0x1 << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ -#define ADC_IMR_EOC4 (0x1 << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ -#define ADC_IMR_EOC5 (0x1 << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ -#define ADC_IMR_EOC6 (0x1 << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ -#define ADC_IMR_EOC7 (0x1 << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ -#define ADC_IMR_OVRE0 (0x1 << 8) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 0 */ -#define ADC_IMR_OVRE1 (0x1 << 9) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 1 */ -#define ADC_IMR_OVRE2 (0x1 << 10) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 2 */ -#define ADC_IMR_OVRE3 (0x1 << 11) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 3 */ -#define ADC_IMR_OVRE4 (0x1 << 12) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 4 */ -#define ADC_IMR_OVRE5 (0x1 << 13) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 5 */ -#define ADC_IMR_OVRE6 (0x1 << 14) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 6 */ -#define ADC_IMR_OVRE7 (0x1 << 15) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 7 */ -#define ADC_IMR_DRDY (0x1 << 16) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ -#define ADC_IMR_GOVRE (0x1 << 17) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ -#define ADC_IMR_ENDRX (0x1 << 18) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ -#define ADC_IMR_RXBUFF (0x1 << 19) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ -/* -------- ADC_CDR[8] : (ADC12B Offset: 0x30) Channel Data Register -------- */ -#define ADC_CDR_DATA (0xfff << 0) /**< \brief (ADC_CDR[8]) Converted Data */ -/* -------- ADC_ACR : (ADC12B Offset: 0x64) Analog Control Register -------- */ -#define ADC_ACR_GAIN (0x3 << 0) /**< \brief (ADC_ACR) Input Gain */ -#define ADC_ACR_IBCTL (0x3 << 6) /**< \brief (ADC_ACR) Bias Current Control */ -#define ADC_ACR_DIFF (0x1 << 16) /**< \brief (ADC_ACR) Differential Mode */ -#define ADC_ACR_OFFSET (0x1 << 17) /**< \brief (ADC_ACR) Input OFFSET */ -/* -------- ADC_EMR : (ADC12B Offset: 0x68) Extended Mode Register -------- */ -#define ADC_EMR_OFFMODES (0x1 << 0) /**< \brief (ADC_EMR) Off Mode if Sleep Bit (ADC_MR) = 1 */ -#define ADC_EMR_OFF_MODE_STARTUP_TIME (0xff << 16) /**< \brief (ADC_EMR) Startup Time */ -/* -------- ADC_RPR : (ADC12B Offset: 0x100) Receive Pointer Register -------- */ -#define ADC_RPR_RXPTR (0xffffffff << 0) /**< \brief (ADC_RPR) Receive Pointer Register */ -/* -------- ADC_RCR : (ADC12B Offset: 0x104) Receive Counter Register -------- */ -#define ADC_RCR_RXCTR (0xffff << 0) /**< \brief (ADC_RCR) Receive Counter Register */ -/* -------- ADC_TPR : (ADC12B Offset: 0x108) Transmit Pointer Register -------- */ -#define ADC_TPR_TXPTR (0xffffffff << 0) /**< \brief (ADC_TPR) Transmit Counter Register */ -/* -------- ADC_TCR : (ADC12B Offset: 0x10C) Transmit Counter Register -------- */ -#define ADC_TCR_TXCTR (0xffff << 0) /**< \brief (ADC_TCR) Transmit Counter Register */ -/* -------- ADC_RNPR : (ADC12B Offset: 0x110) Receive Next Pointer Register -------- */ -#define ADC_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (ADC_RNPR) Receive Next Pointer */ -/* -------- ADC_RNCR : (ADC12B Offset: 0x114) Receive Next Counter Register -------- */ -#define ADC_RNCR_RXNCTR (0xffff << 0) /**< \brief (ADC_RNCR) Receive Next Counter */ -/* -------- ADC_TNPR : (ADC12B Offset: 0x118) Transmit Next Pointer Register -------- */ -#define ADC_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (ADC_TNPR) Transmit Next Pointer */ -/* -------- ADC_TNCR : (ADC12B Offset: 0x11C) Transmit Next Counter Register -------- */ -#define ADC_TNCR_TXNCTR (0xffff << 0) /**< \brief (ADC_TNCR) Transmit Counter Next */ -/* -------- ADC_PTCR : (ADC12B Offset: 0x120) Transfer Control Register -------- */ -#define ADC_PTCR_RXTEN (0x1 << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ -#define ADC_PTCR_RXTDIS (0x1 << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ -#define ADC_PTCR_TXTEN (0x1 << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ -#define ADC_PTCR_TXTDIS (0x1 << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ -/* -------- ADC_PTSR : (ADC12B Offset: 0x124) Transfer Status Register -------- */ -#define ADC_PTSR_RXTEN (0x1 << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ -#define ADC_PTSR_TXTEN (0x1 << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Chip Identifier */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_CHIPID Chip Identifier */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Chipid hardware registers */ -typedef struct { - RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ - RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ -} Chipid; -#endif /* __ASSEMBLY__ */ -/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ -#define CHIPID_CIDR_VERSION (0x1f << 0) /**< \brief (CHIPID_CIDR) Version of the Device */ -#define CHIPID_CIDR_EPROC (0x7 << 5) /**< \brief (CHIPID_CIDR) Embedded Processor */ -#define CHIPID_CIDR_NVPSIZ (0xf << 8) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ -#define CHIPID_CIDR_NVPSIZ2 (0xf << 12) /**< \brief (CHIPID_CIDR) */ -#define CHIPID_CIDR_SRAMSIZ (0xf << 16) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ -#define CHIPID_CIDR_ARCH (0xff << 20) /**< \brief (CHIPID_CIDR) Architecture Identifier */ -#define CHIPID_CIDR_NVPTYP (0x7 << 28) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ -#define CHIPID_CIDR_EXT (0x1 << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ -/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ -#define CHIPID_EXID_EXID (0xffffffff << 0) /**< \brief (CHIPID_EXID) Chip ID Extension */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR DMA Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_DMAC DMA Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief DmacCh_num hardware registers */ -typedef struct { - RwReg DMAC_SADDR; /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */ - RwReg DMAC_DADDR; /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */ - RwReg DMAC_DSCR; /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */ - RwReg DMAC_CTRLA; /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */ - RwReg DMAC_CTRLB; /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */ - RwReg DMAC_CFG; /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */ - RwReg Reserved1[4]; -} DmacCh_num; -/** \brief Dmac hardware registers */ -typedef struct { - RwReg DMAC_GCFG; /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */ - RwReg DMAC_EN; /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */ - RwReg DMAC_SREQ; /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */ - RwReg DMAC_CREQ; /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */ - RwReg DMAC_LAST; /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */ - RwReg Reserved1[1]; - WoReg DMAC_EBCIER; /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. */ - WoReg DMAC_EBCIDR; /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. */ - RoReg DMAC_EBCIMR; /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. */ - RoReg DMAC_EBCISR; /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. */ - WoReg DMAC_CHER; /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */ - WoReg DMAC_CHDR; /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */ - RoReg DMAC_CHSR; /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */ - RwReg Reserved2[2]; - DmacCh_num DMAC_CH_NUM[4]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 3 */ -} Dmac; -#endif /* __ASSEMBLY__ */ -/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */ -#define DMAC_GCFG_ARB_CFG (0x1 << 4) /**< \brief (DMAC_GCFG) */ -/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */ -#define DMAC_EN_ENABLE (0x1 << 0) /**< \brief (DMAC_EN) */ -/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */ -#define DMAC_SREQ_SSREQ0 (0x1 << 0) /**< \brief (DMAC_SREQ) */ -#define DMAC_SREQ_DSREQ0 (0x1 << 1) /**< \brief (DMAC_SREQ) */ -#define DMAC_SREQ_SSREQ1 (0x1 << 2) /**< \brief (DMAC_SREQ) */ -#define DMAC_SREQ_DSREQ1 (0x1 << 3) /**< \brief (DMAC_SREQ) */ -#define DMAC_SREQ_SSREQ2_ (0x1 << 4) /**< \brief (DMAC_SREQ) */ -#define DMAC_SREQ_DSREQ2_ (0x1 << 5) /**< \brief (DMAC_SREQ) */ -#define DMAC_SREQ_SSREQ3 (0x1 << 6) /**< \brief (DMAC_SREQ) */ -#define DMAC_SREQ_DSREQ3 (0x1 << 7) /**< \brief (DMAC_SREQ) */ -/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */ -#define DMAC_CREQ_SCREQ0 (0x1 << 0) /**< \brief (DMAC_CREQ) */ -#define DMAC_CREQ_DCREQ0 (0x1 << 1) /**< \brief (DMAC_CREQ) */ -#define DMAC_CREQ_SCREQ1 (0x1 << 2) /**< \brief (DMAC_CREQ) */ -#define DMAC_CREQ_DCREQ1 (0x1 << 3) /**< \brief (DMAC_CREQ) */ -#define DMAC_CREQ_SCREQ2_ (0x1 << 4) /**< \brief (DMAC_CREQ) */ -#define DMAC_CREQ_DCREQ2_ (0x1 << 5) /**< \brief (DMAC_CREQ) */ -#define DMAC_CREQ_SCREQ3 (0x1 << 6) /**< \brief (DMAC_CREQ) */ -#define DMAC_CREQ_DCREQ3 (0x1 << 7) /**< \brief (DMAC_CREQ) */ -/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */ -#define DMAC_LAST_SLAST0 (0x1 << 0) /**< \brief (DMAC_LAST) */ -#define DMAC_LAST_DLAST0 (0x1 << 1) /**< \brief (DMAC_LAST) */ -#define DMAC_LAST_SLAST1 (0x1 << 2) /**< \brief (DMAC_LAST) */ -#define DMAC_LAST_DLAST1 (0x1 << 3) /**< \brief (DMAC_LAST) */ -#define DMAC_LAST_SLAST2 (0x1 << 4) /**< \brief (DMAC_LAST) */ -#define DMAC_LAST_DLAST2 (0x1 << 5) /**< \brief (DMAC_LAST) */ -#define DMAC_LAST_SLAST3 (0x1 << 6) /**< \brief (DMAC_LAST) */ -#define DMAC_LAST_DLAST3 (0x1 << 7) /**< \brief (DMAC_LAST) */ -/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. -------- */ -#define DMAC_EBCIER_BTC0 (0x1 << 0) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_BTC1 (0x1 << 1) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_BTC2 (0x1 << 2) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_BTC3 (0x1 << 3) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_CBTC0 (0x1 << 8) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_CBTC1 (0x1 << 9) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_CBTC2 (0x1 << 10) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_CBTC3 (0x1 << 11) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_ERR0 (0x1 << 16) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_ERR1 (0x1 << 17) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_ERR2 (0x1 << 18) /**< \brief (DMAC_EBCIER) */ -#define DMAC_EBCIER_ERR3 (0x1 << 19) /**< \brief (DMAC_EBCIER) */ -/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. -------- */ -#define DMAC_EBCIDR_BTC0 (0x1 << 0) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_BTC1 (0x1 << 1) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_BTC2 (0x1 << 2) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_BTC3 (0x1 << 3) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_CBTC0 (0x1 << 8) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_CBTC1 (0x1 << 9) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_CBTC2 (0x1 << 10) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_CBTC3 (0x1 << 11) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_ERR0 (0x1 << 16) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_ERR1 (0x1 << 17) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_ERR2 (0x1 << 18) /**< \brief (DMAC_EBCIDR) */ -#define DMAC_EBCIDR_ERR3 (0x1 << 19) /**< \brief (DMAC_EBCIDR) */ -/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. -------- */ -#define DMAC_EBCIMR_BTC0 (0x1 << 0) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_BTC1 (0x1 << 1) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_BTC2 (0x1 << 2) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_BTC3 (0x1 << 3) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_CBTC0 (0x1 << 8) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_CBTC1 (0x1 << 9) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_CBTC2 (0x1 << 10) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_CBTC3 (0x1 << 11) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_ERR0 (0x1 << 16) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_ERR1 (0x1 << 17) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_ERR2 (0x1 << 18) /**< \brief (DMAC_EBCIMR) */ -#define DMAC_EBCIMR_ERR3 (0x1 << 19) /**< \brief (DMAC_EBCIMR) */ -/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. -------- */ -#define DMAC_EBCISR_BTC0 (0x1 << 0) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_BTC1 (0x1 << 1) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_BTC2 (0x1 << 2) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_BTC3 (0x1 << 3) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_CBTC0 (0x1 << 8) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_CBTC1 (0x1 << 9) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_CBTC2 (0x1 << 10) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_CBTC3 (0x1 << 11) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_ERR0 (0x1 << 16) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_ERR1 (0x1 << 17) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_ERR2 (0x1 << 18) /**< \brief (DMAC_EBCISR) */ -#define DMAC_EBCISR_ERR3 (0x1 << 19) /**< \brief (DMAC_EBCISR) */ -/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */ -#define DMAC_CHER_ENA0 (0x1 << 0) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_ENA1 (0x1 << 1) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_ENA2 (0x1 << 2) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_ENA3 (0x1 << 3) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_SUSP0 (0x1 << 8) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_SUSP1 (0x1 << 9) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_SUSP2 (0x1 << 10) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_SUSP3 (0x1 << 11) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_KEEP0 (0x1 << 24) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_KEEP1 (0x1 << 25) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_KEEP2 (0x1 << 26) /**< \brief (DMAC_CHER) */ -#define DMAC_CHER_KEEP3 (0x1 << 27) /**< \brief (DMAC_CHER) */ -/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */ -#define DMAC_CHDR_DIS0 (0x1 << 0) /**< \brief (DMAC_CHDR) */ -#define DMAC_CHDR_DIS1 (0x1 << 1) /**< \brief (DMAC_CHDR) */ -#define DMAC_CHDR_DIS2 (0x1 << 2) /**< \brief (DMAC_CHDR) */ -#define DMAC_CHDR_DIS3 (0x1 << 3) /**< \brief (DMAC_CHDR) */ -#define DMAC_CHDR_RES0 (0x1 << 8) /**< \brief (DMAC_CHDR) */ -#define DMAC_CHDR_RES1 (0x1 << 9) /**< \brief (DMAC_CHDR) */ -#define DMAC_CHDR_RES2 (0x1 << 10) /**< \brief (DMAC_CHDR) */ -#define DMAC_CHDR_RES3 (0x1 << 11) /**< \brief (DMAC_CHDR) */ -/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */ -#define DMAC_CHSR_ENA0 (0x1 << 0) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_ENA1 (0x1 << 1) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_ENA2 (0x1 << 2) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_ENA3 (0x1 << 3) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_SUSP0 (0x1 << 8) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_SUSP1 (0x1 << 9) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_SUSP2 (0x1 << 10) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_SUSP3 (0x1 << 11) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_EMPT0 (0x1 << 16) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_EMPT1 (0x1 << 17) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_EMPT2 (0x1 << 18) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_EMPT3 (0x1 << 19) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_STAL0 (0x1 << 24) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_STAL1 (0x1 << 25) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_STAL2 (0x1 << 26) /**< \brief (DMAC_CHSR) */ -#define DMAC_CHSR_STAL3 (0x1 << 27) /**< \brief (DMAC_CHSR) */ -/* -------- DMAC_SADDR0 : (DMAC Offset: 0x3C) DMAC Channel Source Address Register (ch_num = 0) -------- */ -#define DMAC_SADDR0_SADDRx (0xffffffff << 0) /**< \brief (DMAC_SADDR0) */ -/* -------- DMAC_DADDR0 : (DMAC Offset: 0x40) DMAC Channel Destination Address Register (ch_num = 0) -------- */ -#define DMAC_DADDR0_DADDRx (0xffffffff << 0) /**< \brief (DMAC_DADDR0) */ -/* -------- DMAC_DSCR0 : (DMAC Offset: 0x44) DMAC Channel Descriptor Address Register (ch_num = 0) -------- */ -#define DMAC_DSCR0_DSCRx (0x3fffffff << 2) /**< \brief (DMAC_DSCR0) */ -/* -------- DMAC_CTRLA0 : (DMAC Offset: 0x48) DMAC Channel Control A Register (ch_num = 0) -------- */ -#define DMAC_CTRLA0_BTSIZE (0xfff << 0) /**< \brief (DMAC_CTRLA0) */ -#define DMAC_CTRLA0_SCSIZE (0x1 << 16) /**< \brief (DMAC_CTRLA0) */ -#define DMAC_CTRLA0_DCSIZE (0x1 << 20) /**< \brief (DMAC_CTRLA0) */ -#define DMAC_CTRLA0_SRC_WIDTH (0x3 << 24) /**< \brief (DMAC_CTRLA0) */ -#define DMAC_CTRLA0_DST_WIDTH (0x3 << 28) /**< \brief (DMAC_CTRLA0) */ -#define DMAC_CTRLA0_DONE (0x1 << 31) /**< \brief (DMAC_CTRLA0) */ -/* -------- DMAC_CTRLB0 : (DMAC Offset: 0x4C) DMAC Channel Control B Register (ch_num = 0) -------- */ -#define DMAC_CTRLB0_SRC_DSCR (0x1 << 16) /**< \brief (DMAC_CTRLB0) */ -#define DMAC_CTRLB0_DST_DSCR (0x1 << 20) /**< \brief (DMAC_CTRLB0) */ -#define DMAC_CTRLB0_FC (0x3 << 21) /**< \brief (DMAC_CTRLB0) */ -#define DMAC_CTRLB0_SRC_INCR (0x3 << 24) /**< \brief (DMAC_CTRLB0) */ -#define DMAC_CTRLB0_DST_INCR (0x3 << 28) /**< \brief (DMAC_CTRLB0) */ -#define DMAC_CTRLB0_IEN (0x1 << 30) /**< \brief (DMAC_CTRLB0) */ -/* -------- DMAC_CFG0 : (DMAC Offset: 0x50) DMAC Channel Configuration Register (ch_num = 0) -------- */ -#define DMAC_CFG0_SRC_PER (0xf << 0) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_DST_PER (0xf << 4) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_SRC_H2SEL (0x1 << 9) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_DST_H2SEL (0x1 << 13) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_SOD (0x1 << 16) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_LOCK_IF (0x1 << 20) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_LOCK_B (0x1 << 21) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_LOCK_IF_L (0x1 << 22) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_AHB_PROT (0x7 << 24) /**< \brief (DMAC_CFG0) */ -#define DMAC_CFG0_FIFOCFG (0x3 << 28) /**< \brief (DMAC_CFG0) */ -/* -------- DMAC_SADDR1 : (DMAC Offset: 0x64) DMAC Channel Source Address Register (ch_num = 1) -------- */ -#define DMAC_SADDR1_SADDRx (0xffffffff << 0) /**< \brief (DMAC_SADDR1) */ -/* -------- DMAC_DADDR1 : (DMAC Offset: 0x68) DMAC Channel Destination Address Register (ch_num = 1) -------- */ -#define DMAC_DADDR1_DADDRx (0xffffffff << 0) /**< \brief (DMAC_DADDR1) */ -/* -------- DMAC_DSCR1 : (DMAC Offset: 0x6C) DMAC Channel Descriptor Address Register (ch_num = 1) -------- */ -#define DMAC_DSCR1_DSCRx (0x3fffffff << 2) /**< \brief (DMAC_DSCR1) */ -/* -------- DMAC_CTRLA1 : (DMAC Offset: 0x70) DMAC Channel Control A Register (ch_num = 1) -------- */ -#define DMAC_CTRLA1_BTSIZE (0xfff << 0) /**< \brief (DMAC_CTRLA1) */ -#define DMAC_CTRLA1_SCSIZE (0x1 << 16) /**< \brief (DMAC_CTRLA1) */ -#define DMAC_CTRLA1_DCSIZE (0x1 << 20) /**< \brief (DMAC_CTRLA1) */ -#define DMAC_CTRLA1_SRC_WIDTH (0x3 << 24) /**< \brief (DMAC_CTRLA1) */ -#define DMAC_CTRLA1_DST_WIDTH (0x3 << 28) /**< \brief (DMAC_CTRLA1) */ -#define DMAC_CTRLA1_DONE (0x1 << 31) /**< \brief (DMAC_CTRLA1) */ -/* -------- DMAC_CTRLB1 : (DMAC Offset: 0x74) DMAC Channel Control B Register (ch_num = 1) -------- */ -#define DMAC_CTRLB1_SRC_DSCR (0x1 << 16) /**< \brief (DMAC_CTRLB1) */ -#define DMAC_CTRLB1_DST_DSCR (0x1 << 20) /**< \brief (DMAC_CTRLB1) */ -#define DMAC_CTRLB1_FC (0x3 << 21) /**< \brief (DMAC_CTRLB1) */ -#define DMAC_CTRLB1_SRC_INCR (0x3 << 24) /**< \brief (DMAC_CTRLB1) */ -#define DMAC_CTRLB1_DST_INCR (0x3 << 28) /**< \brief (DMAC_CTRLB1) */ -#define DMAC_CTRLB1_IEN (0x1 << 30) /**< \brief (DMAC_CTRLB1) */ -/* -------- DMAC_CFG1 : (DMAC Offset: 0x78) DMAC Channel Configuration Register (ch_num = 1) -------- */ -#define DMAC_CFG1_SRC_PER (0xf << 0) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_DST_PER (0xf << 4) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_SRC_H2SEL (0x1 << 9) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_DST_H2SEL (0x1 << 13) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_SOD (0x1 << 16) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_LOCK_IF (0x1 << 20) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_LOCK_B (0x1 << 21) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_LOCK_IF_L (0x1 << 22) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_AHB_PROT (0x7 << 24) /**< \brief (DMAC_CFG1) */ -#define DMAC_CFG1_FIFOCFG (0x3 << 28) /**< \brief (DMAC_CFG1) */ -/* -------- DMAC_SADDR2 : (DMAC Offset: 0x8C) DMAC Channel Source Address Register (ch_num = 2) -------- */ -#define DMAC_SADDR2_SADDRx (0xffffffff << 0) /**< \brief (DMAC_SADDR2) */ -/* -------- DMAC_DADDR2 : (DMAC Offset: 0x90) DMAC Channel Destination Address Register (ch_num = 2) -------- */ -#define DMAC_DADDR2_DADDRx (0xffffffff << 0) /**< \brief (DMAC_DADDR2) */ -/* -------- DMAC_DSCR2 : (DMAC Offset: 0x94) DMAC Channel Descriptor Address Register (ch_num = 2) -------- */ -#define DMAC_DSCR2_DSCRx (0x3fffffff << 2) /**< \brief (DMAC_DSCR2) */ -/* -------- DMAC_CTRLA2 : (DMAC Offset: 0x98) DMAC Channel Control A Register (ch_num = 2) -------- */ -#define DMAC_CTRLA2_BTSIZE (0xfff << 0) /**< \brief (DMAC_CTRLA2) */ -#define DMAC_CTRLA2_SCSIZE (0x1 << 16) /**< \brief (DMAC_CTRLA2) */ -#define DMAC_CTRLA2_DCSIZE (0x1 << 20) /**< \brief (DMAC_CTRLA2) */ -#define DMAC_CTRLA2_SRC_WIDTH (0x3 << 24) /**< \brief (DMAC_CTRLA2) */ -#define DMAC_CTRLA2_DST_WIDTH (0x3 << 28) /**< \brief (DMAC_CTRLA2) */ -#define DMAC_CTRLA2_DONE (0x1 << 31) /**< \brief (DMAC_CTRLA2) */ -/* -------- DMAC_CTRLB2 : (DMAC Offset: 0x9C) DMAC Channel Control B Register (ch_num = 2) -------- */ -#define DMAC_CTRLB2_SRC_DSCR (0x1 << 16) /**< \brief (DMAC_CTRLB2) */ -#define DMAC_CTRLB2_DST_DSCR (0x1 << 20) /**< \brief (DMAC_CTRLB2) */ -#define DMAC_CTRLB2_FC (0x3 << 21) /**< \brief (DMAC_CTRLB2) */ -#define DMAC_CTRLB2_SRC_INCR (0x3 << 24) /**< \brief (DMAC_CTRLB2) */ -#define DMAC_CTRLB2_DST_INCR (0x3 << 28) /**< \brief (DMAC_CTRLB2) */ -#define DMAC_CTRLB2_IEN (0x1 << 30) /**< \brief (DMAC_CTRLB2) */ -/* -------- DMAC_CFG2 : (DMAC Offset: 0xA0) DMAC Channel Configuration Register (ch_num = 2) -------- */ -#define DMAC_CFG2_SRC_PER (0xf << 0) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_DST_PER (0xf << 4) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_SRC_H2SEL (0x1 << 9) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_DST_H2SEL (0x1 << 13) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_SOD (0x1 << 16) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_LOCK_IF (0x1 << 20) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_LOCK_B (0x1 << 21) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_LOCK_IF_L (0x1 << 22) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_AHB_PROT (0x7 << 24) /**< \brief (DMAC_CFG2) */ -#define DMAC_CFG2_FIFOCFG (0x3 << 28) /**< \brief (DMAC_CFG2) */ -/* -------- DMAC_SADDR3 : (DMAC Offset: 0xB4) DMAC Channel Source Address Register (ch_num = 3) -------- */ -#define DMAC_SADDR3_SADDRx (0xffffffff << 0) /**< \brief (DMAC_SADDR3) */ -/* -------- DMAC_DADDR3 : (DMAC Offset: 0xB8) DMAC Channel Destination Address Register (ch_num = 3) -------- */ -#define DMAC_DADDR3_DADDRx (0xffffffff << 0) /**< \brief (DMAC_DADDR3) */ -/* -------- DMAC_DSCR3 : (DMAC Offset: 0xBC) DMAC Channel Descriptor Address Register (ch_num = 3) -------- */ -#define DMAC_DSCR3_DSCRx (0x3fffffff << 2) /**< \brief (DMAC_DSCR3) */ -/* -------- DMAC_CTRLA3 : (DMAC Offset: 0xC0) DMAC Channel Control A Register (ch_num = 3) -------- */ -#define DMAC_CTRLA3_BTSIZE (0xfff << 0) /**< \brief (DMAC_CTRLA3) */ -#define DMAC_CTRLA3_SCSIZE (0x1 << 16) /**< \brief (DMAC_CTRLA3) */ -#define DMAC_CTRLA3_DCSIZE (0x1 << 20) /**< \brief (DMAC_CTRLA3) */ -#define DMAC_CTRLA3_SRC_WIDTH (0x3 << 24) /**< \brief (DMAC_CTRLA3) */ -#define DMAC_CTRLA3_DST_WIDTH (0x3 << 28) /**< \brief (DMAC_CTRLA3) */ -#define DMAC_CTRLA3_DONE (0x1 << 31) /**< \brief (DMAC_CTRLA3) */ -/* -------- DMAC_CTRLB3 : (DMAC Offset: 0xC4) DMAC Channel Control B Register (ch_num = 3) -------- */ -#define DMAC_CTRLB3_SRC_DSCR (0x1 << 16) /**< \brief (DMAC_CTRLB3) */ -#define DMAC_CTRLB3_DST_DSCR (0x1 << 20) /**< \brief (DMAC_CTRLB3) */ -#define DMAC_CTRLB3_FC (0x3 << 21) /**< \brief (DMAC_CTRLB3) */ -#define DMAC_CTRLB3_SRC_INCR (0x3 << 24) /**< \brief (DMAC_CTRLB3) */ -#define DMAC_CTRLB3_DST_INCR (0x3 << 28) /**< \brief (DMAC_CTRLB3) */ -#define DMAC_CTRLB3_IEN (0x1 << 30) /**< \brief (DMAC_CTRLB3) */ -/* -------- DMAC_CFG3 : (DMAC Offset: 0xC8) DMAC Channel Configuration Register (ch_num = 3) -------- */ -#define DMAC_CFG3_SRC_PER (0xf << 0) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_DST_PER (0xf << 4) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_SRC_H2SEL (0x1 << 9) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_DST_H2SEL (0x1 << 13) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_SOD (0x1 << 16) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_LOCK_IF (0x1 << 20) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_LOCK_B (0x1 << 21) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_LOCK_IF_L (0x1 << 22) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_AHB_PROT (0x7 << 24) /**< \brief (DMAC_CFG3) */ -#define DMAC_CFG3_FIFOCFG (0x3 << 28) /**< \brief (DMAC_CFG3) */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_EFC Embedded Flash Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Efc hardware registers */ -typedef struct { - RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ - WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ - RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ - RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ -} Efc; -#endif /* __ASSEMBLY__ */ -/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ -#define EEFC_FMR_FRDY (0x1 << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ -#define EEFC_FMR_FWS (0xf << 8) /**< \brief (EEFC_FMR) Flash Wait State */ -#define EEFC_FMR_FAM (0x1 << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ -/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ -#define EEFC_FCR_FCMD (0xff << 0) /**< \brief (EEFC_FCR) Flash Command */ -#define EEFC_FCR_FARG (0xffff << 8) /**< \brief (EEFC_FCR) Flash Command Argument */ -#define EEFC_FCR_FKEY (0xff << 24) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ -/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ -#define EEFC_FSR_FRDY (0x1 << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ -#define EEFC_FSR_FCMDE (0x1 << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ -#define EEFC_FSR_FLOCKE (0x1 << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ -/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ -#define EEFC_FRR_FVALUE (0xffffffff << 0) /**< \brief (EEFC_FRR) Flash Result Value */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_GPBR General Purpose Backup Register */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Gpbr hardware registers */ -typedef struct { - RwReg SYS_GPBR0; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register 0 */ - RwReg SYS_GPBR1; /**< \brief (Gpbr Offset: 0x4) General Purpose Backup Register 1 */ - RwReg SYS_GPBR2; /**< \brief (Gpbr Offset: 0x8) General Purpose Backup Register 2 */ - RwReg SYS_GPBR3; /**< \brief (Gpbr Offset: 0xC) General Purpose Backup Register 3 */ -} Gpbr; -#endif /* __ASSEMBLY__ */ -/* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */ -#define SYS_GPBR0_GPBR_VALUE0 (0xffffffff << 0) /**< \brief (SYS_GPBR0) Value of GPBR x */ -/* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */ -#define SYS_GPBR1_GPBR_VALUE1 (0xffffffff << 0) /**< \brief (SYS_GPBR1) Value of GPBR x */ -/* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */ -#define SYS_GPBR2_GPBR_VALUE2 (0xffffffff << 0) /**< \brief (SYS_GPBR2) Value of GPBR x */ -/* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */ -#define SYS_GPBR3_GPBR_VALUE3 (0xffffffff << 0) /**< \brief (SYS_GPBR3) Value of GPBR x */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR MultiMedia Card Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_HSMCI MultiMedia Card Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Hsmci hardware registers */ -typedef struct { - WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ - RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ - RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ - RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ - RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ - WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ - RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ - RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ - RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ - RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ - WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ - RwReg Reserved1[2]; - RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ - WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ - WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ - RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ - RwReg HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */ - RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ - RwReg Reserved2[35]; - RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ - RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ -} Hsmci; -#endif /* __ASSEMBLY__ */ -/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ -#define HSMCI_CR_MCIEN (0x1 << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ -#define HSMCI_CR_HSMCIDIS (0x1 << 1) /**< \brief (HSMCI_CR) */ -#define HSMCI_CR_PWSEN (0x1 << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ -#define HSMCI_CR_PWSDIS (0x1 << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ -#define HSMCI_CR_SWRST (0x1 << 7) /**< \brief (HSMCI_CR) Software Reset */ -/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ -#define HSMCI_MR_CLKDIV (0xff << 0) /**< \brief (HSMCI_MR) Clock Divider */ -#define HSMCI_MR_PWSDIV (0x7 << 8) /**< \brief (HSMCI_MR) Power Saving Divider */ -#define HSMCI_MR_RDPROOF (0x1 << 11) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_WRPROOF (0x1 << 12) /**< \brief (HSMCI_MR) */ -#define HSMCI_MR_FBYTE (0x1 << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ -#define HSMCI_MR_PADV (0x1 << 14) /**< \brief (HSMCI_MR) Padding Value */ -#define HSMCI_MR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_MR) Data Block Length */ -/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ -#define HSMCI_DTOR_DTOCYC (0xf << 0) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ -#define HSMCI_DTOR_DTOMUL (0x7 << 4) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ -/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ -#define HSMCI_SDCR_SDCSEL (0x3 << 0) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ -#define HSMCI_SDCR_SDCBUS (0x3 << 6) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ -/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ -#define HSMCI_ARGR_ARG (0xffffffff << 0) /**< \brief (HSMCI_ARGR) Command Argument */ -/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ -#define HSMCI_CMDR_CMDNB (0x3f << 0) /**< \brief (HSMCI_CMDR) Command Number */ -#define HSMCI_CMDR_RSPTYP (0x3 << 6) /**< \brief (HSMCI_CMDR) Response Type */ -#define HSMCI_CMDR_SPCMD (0x7 << 8) /**< \brief (HSMCI_CMDR) Special Command */ -#define HSMCI_CMDR_OPDCMD (0x1 << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ -#define HSMCI_CMDR_MAXLAT (0x1 << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ -#define HSMCI_CMDR_TRCMD (0x3 << 16) /**< \brief (HSMCI_CMDR) Transfer Command */ -#define HSMCI_CMDR_TRDIR (0x1 << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ -#define HSMCI_CMDR_TRTYP (0x7 << 19) /**< \brief (HSMCI_CMDR) Transfer Type */ -#define HSMCI_CMDR_IOSPCMD (0x3 << 24) /**< \brief (HSMCI_CMDR) SDIO Special Command */ -#define HSMCI_CMDR_ATACS (0x1 << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ -#define HSMCI_CMDR_BOOT_ACK (0x1 << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ -/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ -#define HSMCI_BLKR_BCNT (0xffff << 0) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ -#define HSMCI_BLKR_BLKLEN (0xffff << 16) /**< \brief (HSMCI_BLKR) Data Block Length */ -/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ -#define HSMCI_CSTOR_CSTOCYC (0xf << 0) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ -#define HSMCI_CSTOR_CSTOMUL (0x7 << 4) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ -/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ -#define HSMCI_RSPR_RSP (0xffffffff << 0) /**< \brief (HSMCI_RSPR[4]) Response */ -/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ -#define HSMCI_RDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_RDR) Data to Read */ -/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ -#define HSMCI_TDR_DATA (0xffffffff << 0) /**< \brief (HSMCI_TDR) Data to Write */ -/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ -#define HSMCI_SR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_SR) Command Ready */ -#define HSMCI_SR_RXRDY (0x1 << 1) /**< \brief (HSMCI_SR) Receiver Ready */ -#define HSMCI_SR_TXRDY (0x1 << 2) /**< \brief (HSMCI_SR) Transmit Ready */ -#define HSMCI_SR_BLKE (0x1 << 3) /**< \brief (HSMCI_SR) Data Block Ended */ -#define HSMCI_SR_DTIP (0x1 << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ -#define HSMCI_SR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ -#define HSMCI_SR_MCI_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_SR) */ -#define HSMCI_SR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ -#define HSMCI_SR_CSRCV (0x1 << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ -#define HSMCI_SR_RINDE (0x1 << 16) /**< \brief (HSMCI_SR) Response Index Error */ -#define HSMCI_SR_RDIRE (0x1 << 17) /**< \brief (HSMCI_SR) Response Direction Error */ -#define HSMCI_SR_RCRCE (0x1 << 18) /**< \brief (HSMCI_SR) Response CRC Error */ -#define HSMCI_SR_RENDE (0x1 << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ -#define HSMCI_SR_RTOE (0x1 << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ -#define HSMCI_SR_DCRCE (0x1 << 21) /**< \brief (HSMCI_SR) Data CRC Error */ -#define HSMCI_SR_DTOE (0x1 << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ -#define HSMCI_SR_CSTOE (0x1 << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ -#define HSMCI_SR_BLKOVRE (0x1 << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error */ -#define HSMCI_SR_DMADONE (0x1 << 25) /**< \brief (HSMCI_SR) DMA Transfer done */ -#define HSMCI_SR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ -#define HSMCI_SR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ -#define HSMCI_SR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ -#define HSMCI_SR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ -#define HSMCI_SR_OVRE (0x1 << 30) /**< \brief (HSMCI_SR) Overrun */ -#define HSMCI_SR_UNRE (0x1 << 31) /**< \brief (HSMCI_SR) Underrun */ -/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ -#define HSMCI_IER_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ -#define HSMCI_IER_RXRDY (0x1 << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ -#define HSMCI_IER_TXRDY (0x1 << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ -#define HSMCI_IER_BLKE (0x1 << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ -#define HSMCI_IER_DTIP (0x1 << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ -#define HSMCI_IER_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ -#define HSMCI_IER_MCI_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IER) */ -#define HSMCI_IER_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ -#define HSMCI_IER_CSRCV (0x1 << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ -#define HSMCI_IER_RINDE (0x1 << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ -#define HSMCI_IER_RDIRE (0x1 << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ -#define HSMCI_IER_RCRCE (0x1 << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ -#define HSMCI_IER_RENDE (0x1 << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ -#define HSMCI_IER_RTOE (0x1 << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ -#define HSMCI_IER_DCRCE (0x1 << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ -#define HSMCI_IER_DTOE (0x1 << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ -#define HSMCI_IER_CSTOE (0x1 << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ -#define HSMCI_IER_BLKOVRE (0x1 << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */ -#define HSMCI_IER_DMADONE (0x1 << 25) /**< \brief (HSMCI_IER) DMA Transfer completed Interrupt Enable */ -#define HSMCI_IER_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ -#define HSMCI_IER_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ -#define HSMCI_IER_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ -#define HSMCI_IER_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ -#define HSMCI_IER_OVRE (0x1 << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ -#define HSMCI_IER_UNRE (0x1 << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ -/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ -#define HSMCI_IDR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ -#define HSMCI_IDR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ -#define HSMCI_IDR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ -#define HSMCI_IDR_BLKE (0x1 << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ -#define HSMCI_IDR_DTIP (0x1 << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ -#define HSMCI_IDR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ -#define HSMCI_IDR_MCI_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IDR) */ -#define HSMCI_IDR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ -#define HSMCI_IDR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt disable */ -#define HSMCI_IDR_RINDE (0x1 << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ -#define HSMCI_IDR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ -#define HSMCI_IDR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ -#define HSMCI_IDR_RENDE (0x1 << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ -#define HSMCI_IDR_RTOE (0x1 << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ -#define HSMCI_IDR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ -#define HSMCI_IDR_DTOE (0x1 << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ -#define HSMCI_IDR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ -#define HSMCI_IDR_BLKOVRE (0x1 << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */ -#define HSMCI_IDR_DMADONE (0x1 << 25) /**< \brief (HSMCI_IDR) DMA Transfer completed Interrupt Disable */ -#define HSMCI_IDR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ -#define HSMCI_IDR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ -#define HSMCI_IDR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ -#define HSMCI_IDR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ -#define HSMCI_IDR_OVRE (0x1 << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ -#define HSMCI_IDR_UNRE (0x1 << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ -/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ -#define HSMCI_IMR_CMDRDY (0x1 << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ -#define HSMCI_IMR_RXRDY (0x1 << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ -#define HSMCI_IMR_TXRDY (0x1 << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ -#define HSMCI_IMR_BLKE (0x1 << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ -#define HSMCI_IMR_DTIP (0x1 << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ -#define HSMCI_IMR_NOTBUSY (0x1 << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ -#define HSMCI_IMR_MCI_SDIOIRQA (0x1 << 8) /**< \brief (HSMCI_IMR) */ -#define HSMCI_IMR_SDIOWAIT (0x1 << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ -#define HSMCI_IMR_CSRCV (0x1 << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ -#define HSMCI_IMR_RINDE (0x1 << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ -#define HSMCI_IMR_RDIRE (0x1 << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ -#define HSMCI_IMR_RCRCE (0x1 << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ -#define HSMCI_IMR_RENDE (0x1 << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ -#define HSMCI_IMR_RTOE (0x1 << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ -#define HSMCI_IMR_DCRCE (0x1 << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ -#define HSMCI_IMR_DTOE (0x1 << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ -#define HSMCI_IMR_CSTOE (0x1 << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ -#define HSMCI_IMR_BLKOVRE (0x1 << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */ -#define HSMCI_IMR_DMADONE (0x1 << 25) /**< \brief (HSMCI_IMR) DMA Transfer Completed Interrupt Mask */ -#define HSMCI_IMR_FIFOEMPTY (0x1 << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ -#define HSMCI_IMR_XFRDONE (0x1 << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ -#define HSMCI_IMR_ACKRCV (0x1 << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ -#define HSMCI_IMR_ACKRCVE (0x1 << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ -#define HSMCI_IMR_OVRE (0x1 << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ -#define HSMCI_IMR_UNRE (0x1 << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ -/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */ -#define HSMCI_DMA_OFFSET (0x3 << 0) /**< \brief (HSMCI_DMA) DMA Write Buffer Offset */ -#define HSMCI_DMA_CHKSIZE (0x1 << 4) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */ -#define HSMCI_DMA_DMAEN (0x1 << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */ -#define HSMCI_DMA_ROPT (0x1 << 12) /**< \brief (HSMCI_DMA) Read Optimization with padding */ -/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ -#define HSMCI_CFG_FIFOMODE (0x1 << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ -#define HSMCI_CFG_FERRCTRL (0x1 << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ -#define HSMCI_CFG_HSMODE (0x1 << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ -#define HSMCI_CFG_LSYNC (0x1 << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ -/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ -#define HSMCI_WPMR_WP_EN (0x1 << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ -#define HSMCI_WPMR_WP_KEY (0xffffff << 8) /**< \brief (HSMCI_WPMR) Write Protection Key password */ -/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ -#define HSMCI_WPSR_WP_VS (0xf << 0) /**< \brief (HSMCI_WPSR) */ -#define HSMCI_WPSR_WP_VSRC (0xffff << 8) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_MATRIX AHB Bus Matrix */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Matrix hardware registers */ -typedef struct { - RwReg MATRIX_MCFG[5]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ - RwReg Reserved1[11]; - RwReg MATRIX_SCFG[10]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ - RwReg Reserved2[6]; - RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ - RwReg Reserved3[1]; - RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ - RwReg Reserved4[1]; - RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ - RwReg Reserved5[1]; - RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ - RwReg Reserved6[1]; - RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ - RwReg Reserved7[1]; - RwReg MATRIX_PRAS5; /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */ - RwReg Reserved8[1]; - RwReg MATRIX_PRAS6; /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */ - RwReg Reserved9[1]; - RwReg MATRIX_PRAS7; /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */ - RwReg Reserved10[1]; - RwReg MATRIX_PRAS8; /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */ - RwReg Reserved11[1]; - RwReg MATRIX_PRAS9; /**< \brief (Matrix Offset: 0x00C8) Priority Register A for Slave 9 */ - RwReg Reserved12[13]; - RwReg MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */ -} Matrix; -#endif /* __ASSEMBLY__ */ -/* -------- MATRIX_MCFG[5] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ -#define MATRIX_MCFG_ULBT (0x7 << 0) /**< \brief (MATRIX_MCFG[5]) Undefined Length Burst Type */ -/* -------- MATRIX_SCFG[10] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ -#define MATRIX_SCFG_SLOT_CYCLE (0xff << 0) /**< \brief (MATRIX_SCFG[10]) Maximum Number of Allowed Cycles for a Burst */ -#define MATRIX_SCFG_DEFMSTR_TYPE (0x3 << 16) /**< \brief (MATRIX_SCFG[10]) Default Master Type */ -#define MATRIX_SCFG_FIXED_DEFMSTR (0x7 << 18) /**< \brief (MATRIX_SCFG[10]) Fixed Default Master */ -#define MATRIX_SCFG_ARBT (0x3 << 24) /**< \brief (MATRIX_SCFG[10]) Arbitration Type */ -/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ -#define MATRIX_PRAS0_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ -#define MATRIX_PRAS0_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ -#define MATRIX_PRAS0_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ -#define MATRIX_PRAS0_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ -#define MATRIX_PRAS0_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ -/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ -#define MATRIX_PRAS1_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ -#define MATRIX_PRAS1_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ -#define MATRIX_PRAS1_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ -#define MATRIX_PRAS1_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ -#define MATRIX_PRAS1_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ -/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ -#define MATRIX_PRAS2_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ -#define MATRIX_PRAS2_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ -#define MATRIX_PRAS2_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ -#define MATRIX_PRAS2_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ -#define MATRIX_PRAS2_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ -/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ -#define MATRIX_PRAS3_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ -#define MATRIX_PRAS3_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ -#define MATRIX_PRAS3_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ -#define MATRIX_PRAS3_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ -#define MATRIX_PRAS3_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ -/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ -#define MATRIX_PRAS4_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ -#define MATRIX_PRAS4_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ -#define MATRIX_PRAS4_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ -#define MATRIX_PRAS4_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ -#define MATRIX_PRAS4_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ -/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */ -#define MATRIX_PRAS5_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS5) Master 0 Priority */ -#define MATRIX_PRAS5_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS5) Master 1 Priority */ -#define MATRIX_PRAS5_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS5) Master 2 Priority */ -#define MATRIX_PRAS5_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS5) Master 3 Priority */ -#define MATRIX_PRAS5_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS5) Master 4 Priority */ -/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */ -#define MATRIX_PRAS6_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS6) Master 0 Priority */ -#define MATRIX_PRAS6_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS6) Master 1 Priority */ -#define MATRIX_PRAS6_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS6) Master 2 Priority */ -#define MATRIX_PRAS6_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS6) Master 3 Priority */ -#define MATRIX_PRAS6_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS6) Master 4 Priority */ -/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */ -#define MATRIX_PRAS7_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS7) Master 0 Priority */ -#define MATRIX_PRAS7_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS7) Master 1 Priority */ -#define MATRIX_PRAS7_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS7) Master 2 Priority */ -#define MATRIX_PRAS7_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS7) Master 3 Priority */ -#define MATRIX_PRAS7_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS7) Master 4 Priority */ -/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */ -#define MATRIX_PRAS8_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS8) Master 0 Priority */ -#define MATRIX_PRAS8_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS8) Master 1 Priority */ -#define MATRIX_PRAS8_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS8) Master 2 Priority */ -#define MATRIX_PRAS8_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS8) Master 3 Priority */ -#define MATRIX_PRAS8_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS8) Master 4 Priority */ -/* -------- MATRIX_PRAS9 : (MATRIX Offset: 0x00C8) Priority Register A for Slave 9 -------- */ -#define MATRIX_PRAS9_M0PR (0x3 << 0) /**< \brief (MATRIX_PRAS9) Master 0 Priority */ -#define MATRIX_PRAS9_M1PR (0x3 << 4) /**< \brief (MATRIX_PRAS9) Master 1 Priority */ -#define MATRIX_PRAS9_M2PR (0x3 << 8) /**< \brief (MATRIX_PRAS9) Master 2 Priority */ -#define MATRIX_PRAS9_M3PR (0x3 << 12) /**< \brief (MATRIX_PRAS9) Master 3 Priority */ -#define MATRIX_PRAS9_M4PR (0x3 << 16) /**< \brief (MATRIX_PRAS9) Master 4 Priority */ -/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */ -#define MATRIX_MRCR_RCB0 (0x1 << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 0 */ -#define MATRIX_MRCR_RCB1 (0x1 << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 1 */ -#define MATRIX_MRCR_RCB2 (0x1 << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 2 */ -#define MATRIX_MRCR_RCB3 (0x1 << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 3 */ -#define MATRIX_MRCR_RCB4 (0x1 << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 4 */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_PDC Peripheral DMA Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pdc hardware registers */ -typedef struct { - RwReg Reserved1[64]; - RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x100) Receive Pointer Register */ - RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x104) Receive Counter Register */ - RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x108) Transmit Pointer Register */ - RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0x10C) Transmit Counter Register */ - RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x110) Receive Next Pointer Register */ - RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x114) Receive Next Counter Register */ - RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x118) Transmit Next Pointer Register */ - RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x11C) Transmit Next Counter Register */ - WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x120) Transfer Control Register */ - RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x124) Transfer Status Register */ -} Pdc; -#endif /* __ASSEMBLY__ */ -/* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */ -#define PERIPH_RPR_RXPTR (0xffffffff << 0) /**< \brief (PERIPH_RPR) Receive Pointer Register */ -/* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */ -#define PERIPH_RCR_RXCTR (0xffff << 0) /**< \brief (PERIPH_RCR) Receive Counter Register */ -/* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */ -#define PERIPH_TPR_TXPTR (0xffffffff << 0) /**< \brief (PERIPH_TPR) Transmit Counter Register */ -/* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */ -#define PERIPH_TCR_TXCTR (0xffff << 0) /**< \brief (PERIPH_TCR) Transmit Counter Register */ -/* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */ -#define PERIPH_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ -/* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */ -#define PERIPH_RNCR_RXNCTR (0xffff << 0) /**< \brief (PERIPH_RNCR) Receive Next Counter */ -/* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PERIPH_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ -/* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PERIPH_TNCR_TXNCTR (0xffff << 0) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ -/* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */ -#define PERIPH_PTCR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ -#define PERIPH_PTCR_RXTDIS (0x1 << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ -#define PERIPH_PTCR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ -#define PERIPH_PTCR_TXTDIS (0x1 << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ -/* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */ -#define PERIPH_PTSR_RXTEN (0x1 << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ -#define PERIPH_PTSR_TXTEN (0x1 << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Parallel Input/Output */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_PIO Parallel Input/Output */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pio hardware registers */ -typedef struct { - WoReg PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ - WoReg PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ - RoReg PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ - RwReg Reserved1[1]; - WoReg PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ - WoReg PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ - RoReg PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ - RwReg Reserved2[1]; - WoReg PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ - WoReg PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ - RoReg PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ - RwReg Reserved3[1]; - WoReg PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ - WoReg PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ - RwReg PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ - RoReg PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ - WoReg PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ - WoReg PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ - RoReg PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ - RoReg PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ - WoReg PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ - WoReg PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ - RoReg PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ - RwReg Reserved4[1]; - WoReg PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ - WoReg PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ - RoReg PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ - RwReg Reserved5[1]; - RwReg PIO_ABSR; /**< \brief (Pio Offset: 0x0070) Peripheral AB Select Register */ - RwReg Reserved6[3]; - WoReg PIO_SCIFSR; /**< \brief (Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register */ - WoReg PIO_DIFSR; /**< \brief (Pio Offset: 0x0084) Debouncing Input Filter Select Register */ - RoReg PIO_IFDGSR; /**< \brief (Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register */ - RwReg PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ - RwReg Reserved7[4]; - WoReg PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ - WoReg PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ - RoReg PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ - RwReg Reserved8[1]; - WoReg PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ - WoReg PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ - RoReg PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ - RwReg Reserved9[1]; - WoReg PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ - WoReg PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ - RoReg PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ - RwReg Reserved10[1]; - WoReg PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ - WoReg PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ - RoReg PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ - RwReg Reserved11[1]; - RoReg PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ - RwReg PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ - RoReg PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ -} Pio; -#endif /* __ASSEMBLY__ */ -/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ -#define PIO_PER_P0 (0x1 << 0) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P1 (0x1 << 1) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P2 (0x1 << 2) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P3 (0x1 << 3) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P4 (0x1 << 4) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P5 (0x1 << 5) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P6 (0x1 << 6) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P7 (0x1 << 7) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P8 (0x1 << 8) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P9 (0x1 << 9) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P10 (0x1 << 10) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P11 (0x1 << 11) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P12 (0x1 << 12) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P13 (0x1 << 13) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P14 (0x1 << 14) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P15 (0x1 << 15) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P16 (0x1 << 16) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P17 (0x1 << 17) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P18 (0x1 << 18) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P19 (0x1 << 19) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P20 (0x1 << 20) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P21 (0x1 << 21) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P22 (0x1 << 22) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P23 (0x1 << 23) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P24 (0x1 << 24) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P25 (0x1 << 25) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P26 (0x1 << 26) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P27 (0x1 << 27) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P28 (0x1 << 28) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P29 (0x1 << 29) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P30 (0x1 << 30) /**< \brief (PIO_PER) PIO Enable */ -#define PIO_PER_P31 (0x1 << 31) /**< \brief (PIO_PER) PIO Enable */ -/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ -#define PIO_PDR_P0 (0x1 << 0) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P1 (0x1 << 1) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P2 (0x1 << 2) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P3 (0x1 << 3) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P4 (0x1 << 4) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P5 (0x1 << 5) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P6 (0x1 << 6) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P7 (0x1 << 7) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P8 (0x1 << 8) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P9 (0x1 << 9) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P10 (0x1 << 10) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P11 (0x1 << 11) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P12 (0x1 << 12) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P13 (0x1 << 13) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P14 (0x1 << 14) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P15 (0x1 << 15) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P16 (0x1 << 16) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P17 (0x1 << 17) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P18 (0x1 << 18) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P19 (0x1 << 19) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P20 (0x1 << 20) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P21 (0x1 << 21) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P22 (0x1 << 22) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P23 (0x1 << 23) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P24 (0x1 << 24) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P25 (0x1 << 25) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P26 (0x1 << 26) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P27 (0x1 << 27) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P28 (0x1 << 28) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P29 (0x1 << 29) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P30 (0x1 << 30) /**< \brief (PIO_PDR) PIO Disable */ -#define PIO_PDR_P31 (0x1 << 31) /**< \brief (PIO_PDR) PIO Disable */ -/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ -#define PIO_PSR_P0 (0x1 << 0) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P1 (0x1 << 1) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P2 (0x1 << 2) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P3 (0x1 << 3) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P4 (0x1 << 4) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P5 (0x1 << 5) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P6 (0x1 << 6) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P7 (0x1 << 7) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P8 (0x1 << 8) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P9 (0x1 << 9) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P10 (0x1 << 10) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P11 (0x1 << 11) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P12 (0x1 << 12) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P13 (0x1 << 13) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P14 (0x1 << 14) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P15 (0x1 << 15) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P16 (0x1 << 16) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P17 (0x1 << 17) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P18 (0x1 << 18) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P19 (0x1 << 19) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P20 (0x1 << 20) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P21 (0x1 << 21) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P22 (0x1 << 22) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P23 (0x1 << 23) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P24 (0x1 << 24) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P25 (0x1 << 25) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P26 (0x1 << 26) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P27 (0x1 << 27) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P28 (0x1 << 28) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P29 (0x1 << 29) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P30 (0x1 << 30) /**< \brief (PIO_PSR) PIO Status */ -#define PIO_PSR_P31 (0x1 << 31) /**< \brief (PIO_PSR) PIO Status */ -/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ -#define PIO_OER_P0 (0x1 << 0) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P1 (0x1 << 1) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P2 (0x1 << 2) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P3 (0x1 << 3) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P4 (0x1 << 4) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P5 (0x1 << 5) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P6 (0x1 << 6) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P7 (0x1 << 7) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P8 (0x1 << 8) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P9 (0x1 << 9) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P10 (0x1 << 10) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P11 (0x1 << 11) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P12 (0x1 << 12) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P13 (0x1 << 13) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P14 (0x1 << 14) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P15 (0x1 << 15) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P16 (0x1 << 16) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P17 (0x1 << 17) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P18 (0x1 << 18) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P19 (0x1 << 19) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P20 (0x1 << 20) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P21 (0x1 << 21) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P22 (0x1 << 22) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P23 (0x1 << 23) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P24 (0x1 << 24) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P25 (0x1 << 25) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P26 (0x1 << 26) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P27 (0x1 << 27) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P28 (0x1 << 28) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P29 (0x1 << 29) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P30 (0x1 << 30) /**< \brief (PIO_OER) Output Enable */ -#define PIO_OER_P31 (0x1 << 31) /**< \brief (PIO_OER) Output Enable */ -/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ -#define PIO_ODR_P0 (0x1 << 0) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P1 (0x1 << 1) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P2 (0x1 << 2) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P3 (0x1 << 3) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P4 (0x1 << 4) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P5 (0x1 << 5) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P6 (0x1 << 6) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P7 (0x1 << 7) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P8 (0x1 << 8) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P9 (0x1 << 9) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P10 (0x1 << 10) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P11 (0x1 << 11) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P12 (0x1 << 12) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P13 (0x1 << 13) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P14 (0x1 << 14) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P15 (0x1 << 15) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P16 (0x1 << 16) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P17 (0x1 << 17) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P18 (0x1 << 18) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P19 (0x1 << 19) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P20 (0x1 << 20) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P21 (0x1 << 21) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P22 (0x1 << 22) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P23 (0x1 << 23) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P24 (0x1 << 24) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P25 (0x1 << 25) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P26 (0x1 << 26) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P27 (0x1 << 27) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P28 (0x1 << 28) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P29 (0x1 << 29) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P30 (0x1 << 30) /**< \brief (PIO_ODR) Output Disable */ -#define PIO_ODR_P31 (0x1 << 31) /**< \brief (PIO_ODR) Output Disable */ -/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ -#define PIO_OSR_P0 (0x1 << 0) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P1 (0x1 << 1) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P2 (0x1 << 2) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P3 (0x1 << 3) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P4 (0x1 << 4) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P5 (0x1 << 5) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P6 (0x1 << 6) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P7 (0x1 << 7) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P8 (0x1 << 8) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P9 (0x1 << 9) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P10 (0x1 << 10) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P11 (0x1 << 11) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P12 (0x1 << 12) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P13 (0x1 << 13) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P14 (0x1 << 14) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P15 (0x1 << 15) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P16 (0x1 << 16) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P17 (0x1 << 17) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P18 (0x1 << 18) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P19 (0x1 << 19) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P20 (0x1 << 20) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P21 (0x1 << 21) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P22 (0x1 << 22) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P23 (0x1 << 23) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P24 (0x1 << 24) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P25 (0x1 << 25) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P26 (0x1 << 26) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P27 (0x1 << 27) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P28 (0x1 << 28) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P29 (0x1 << 29) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P30 (0x1 << 30) /**< \brief (PIO_OSR) Output Status */ -#define PIO_OSR_P31 (0x1 << 31) /**< \brief (PIO_OSR) Output Status */ -/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ -#define PIO_IFER_P0 (0x1 << 0) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P1 (0x1 << 1) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P2 (0x1 << 2) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P3 (0x1 << 3) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P4 (0x1 << 4) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P5 (0x1 << 5) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P6 (0x1 << 6) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P7 (0x1 << 7) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P8 (0x1 << 8) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P9 (0x1 << 9) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P10 (0x1 << 10) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P11 (0x1 << 11) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P12 (0x1 << 12) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P13 (0x1 << 13) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P14 (0x1 << 14) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P15 (0x1 << 15) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P16 (0x1 << 16) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P17 (0x1 << 17) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P18 (0x1 << 18) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P19 (0x1 << 19) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P20 (0x1 << 20) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P21 (0x1 << 21) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P22 (0x1 << 22) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P23 (0x1 << 23) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P24 (0x1 << 24) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P25 (0x1 << 25) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P26 (0x1 << 26) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P27 (0x1 << 27) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P28 (0x1 << 28) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P29 (0x1 << 29) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P30 (0x1 << 30) /**< \brief (PIO_IFER) Input Filter Enable */ -#define PIO_IFER_P31 (0x1 << 31) /**< \brief (PIO_IFER) Input Filter Enable */ -/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ -#define PIO_IFDR_P0 (0x1 << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P1 (0x1 << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P2 (0x1 << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P3 (0x1 << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P4 (0x1 << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P5 (0x1 << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P6 (0x1 << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P7 (0x1 << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P8 (0x1 << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P9 (0x1 << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P10 (0x1 << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P11 (0x1 << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P12 (0x1 << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P13 (0x1 << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P14 (0x1 << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P15 (0x1 << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P16 (0x1 << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P17 (0x1 << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P18 (0x1 << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P19 (0x1 << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P20 (0x1 << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P21 (0x1 << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P22 (0x1 << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P23 (0x1 << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P24 (0x1 << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P25 (0x1 << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P26 (0x1 << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P27 (0x1 << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P28 (0x1 << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P29 (0x1 << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P30 (0x1 << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ -#define PIO_IFDR_P31 (0x1 << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ -/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ -#define PIO_IFSR_P0 (0x1 << 0) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P1 (0x1 << 1) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P2 (0x1 << 2) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P3 (0x1 << 3) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P4 (0x1 << 4) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P5 (0x1 << 5) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P6 (0x1 << 6) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P7 (0x1 << 7) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P8 (0x1 << 8) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P9 (0x1 << 9) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P10 (0x1 << 10) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P11 (0x1 << 11) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P12 (0x1 << 12) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P13 (0x1 << 13) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P14 (0x1 << 14) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P15 (0x1 << 15) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P16 (0x1 << 16) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P17 (0x1 << 17) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P18 (0x1 << 18) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P19 (0x1 << 19) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P20 (0x1 << 20) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P21 (0x1 << 21) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P22 (0x1 << 22) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P23 (0x1 << 23) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P24 (0x1 << 24) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P25 (0x1 << 25) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P26 (0x1 << 26) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P27 (0x1 << 27) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P28 (0x1 << 28) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P29 (0x1 << 29) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P30 (0x1 << 30) /**< \brief (PIO_IFSR) Input Filer Status */ -#define PIO_IFSR_P31 (0x1 << 31) /**< \brief (PIO_IFSR) Input Filer Status */ -/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ -#define PIO_SODR_P0 (0x1 << 0) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P1 (0x1 << 1) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P2 (0x1 << 2) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P3 (0x1 << 3) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P4 (0x1 << 4) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P5 (0x1 << 5) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P6 (0x1 << 6) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P7 (0x1 << 7) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P8 (0x1 << 8) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P9 (0x1 << 9) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P10 (0x1 << 10) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P11 (0x1 << 11) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P12 (0x1 << 12) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P13 (0x1 << 13) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P14 (0x1 << 14) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P15 (0x1 << 15) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P16 (0x1 << 16) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P17 (0x1 << 17) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P18 (0x1 << 18) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P19 (0x1 << 19) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P20 (0x1 << 20) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P21 (0x1 << 21) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P22 (0x1 << 22) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P23 (0x1 << 23) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P24 (0x1 << 24) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P25 (0x1 << 25) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P26 (0x1 << 26) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P27 (0x1 << 27) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P28 (0x1 << 28) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P29 (0x1 << 29) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P30 (0x1 << 30) /**< \brief (PIO_SODR) Set Output Data */ -#define PIO_SODR_P31 (0x1 << 31) /**< \brief (PIO_SODR) Set Output Data */ -/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ -#define PIO_CODR_P0 (0x1 << 0) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P1 (0x1 << 1) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P2 (0x1 << 2) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P3 (0x1 << 3) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P4 (0x1 << 4) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P5 (0x1 << 5) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P6 (0x1 << 6) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P7 (0x1 << 7) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P8 (0x1 << 8) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P9 (0x1 << 9) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P10 (0x1 << 10) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P11 (0x1 << 11) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P12 (0x1 << 12) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P13 (0x1 << 13) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P14 (0x1 << 14) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P15 (0x1 << 15) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P16 (0x1 << 16) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P17 (0x1 << 17) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P18 (0x1 << 18) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P19 (0x1 << 19) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P20 (0x1 << 20) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P21 (0x1 << 21) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P22 (0x1 << 22) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P23 (0x1 << 23) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P24 (0x1 << 24) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P25 (0x1 << 25) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P26 (0x1 << 26) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P27 (0x1 << 27) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P28 (0x1 << 28) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P29 (0x1 << 29) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P30 (0x1 << 30) /**< \brief (PIO_CODR) Clear Output Data */ -#define PIO_CODR_P31 (0x1 << 31) /**< \brief (PIO_CODR) Clear Output Data */ -/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ -#define PIO_ODSR_P0 (0x1 << 0) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P1 (0x1 << 1) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P2 (0x1 << 2) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P3 (0x1 << 3) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P4 (0x1 << 4) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P5 (0x1 << 5) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P6 (0x1 << 6) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P7 (0x1 << 7) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P8 (0x1 << 8) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P9 (0x1 << 9) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P10 (0x1 << 10) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P11 (0x1 << 11) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P12 (0x1 << 12) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P13 (0x1 << 13) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P14 (0x1 << 14) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P15 (0x1 << 15) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P16 (0x1 << 16) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P17 (0x1 << 17) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P18 (0x1 << 18) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P19 (0x1 << 19) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P20 (0x1 << 20) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P21 (0x1 << 21) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P22 (0x1 << 22) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P23 (0x1 << 23) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P24 (0x1 << 24) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P25 (0x1 << 25) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P26 (0x1 << 26) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P27 (0x1 << 27) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P28 (0x1 << 28) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P29 (0x1 << 29) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P30 (0x1 << 30) /**< \brief (PIO_ODSR) Output Data Status */ -#define PIO_ODSR_P31 (0x1 << 31) /**< \brief (PIO_ODSR) Output Data Status */ -/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ -#define PIO_PDSR_P0 (0x1 << 0) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P1 (0x1 << 1) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P2 (0x1 << 2) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P3 (0x1 << 3) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P4 (0x1 << 4) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P5 (0x1 << 5) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P6 (0x1 << 6) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P7 (0x1 << 7) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P8 (0x1 << 8) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P9 (0x1 << 9) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P10 (0x1 << 10) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P11 (0x1 << 11) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P12 (0x1 << 12) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P13 (0x1 << 13) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P14 (0x1 << 14) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P15 (0x1 << 15) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P16 (0x1 << 16) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P17 (0x1 << 17) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P18 (0x1 << 18) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P19 (0x1 << 19) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P20 (0x1 << 20) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P21 (0x1 << 21) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P22 (0x1 << 22) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P23 (0x1 << 23) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P24 (0x1 << 24) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P25 (0x1 << 25) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P26 (0x1 << 26) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P27 (0x1 << 27) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P28 (0x1 << 28) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P29 (0x1 << 29) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P30 (0x1 << 30) /**< \brief (PIO_PDSR) Output Data Status */ -#define PIO_PDSR_P31 (0x1 << 31) /**< \brief (PIO_PDSR) Output Data Status */ -/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ -#define PIO_IER_P0 (0x1 << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P1 (0x1 << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P2 (0x1 << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P3 (0x1 << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P4 (0x1 << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P5 (0x1 << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P6 (0x1 << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P7 (0x1 << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P8 (0x1 << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P9 (0x1 << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P10 (0x1 << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P11 (0x1 << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P12 (0x1 << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P13 (0x1 << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P14 (0x1 << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P15 (0x1 << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P16 (0x1 << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P17 (0x1 << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P18 (0x1 << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P19 (0x1 << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P20 (0x1 << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P21 (0x1 << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P22 (0x1 << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P23 (0x1 << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P24 (0x1 << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P25 (0x1 << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P26 (0x1 << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P27 (0x1 << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P28 (0x1 << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P29 (0x1 << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P30 (0x1 << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -#define PIO_IER_P31 (0x1 << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ -/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ -#define PIO_IDR_P0 (0x1 << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P1 (0x1 << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P2 (0x1 << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P3 (0x1 << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P4 (0x1 << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P5 (0x1 << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P6 (0x1 << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P7 (0x1 << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P8 (0x1 << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P9 (0x1 << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P10 (0x1 << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P11 (0x1 << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P12 (0x1 << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P13 (0x1 << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P14 (0x1 << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P15 (0x1 << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P16 (0x1 << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P17 (0x1 << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P18 (0x1 << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P19 (0x1 << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P20 (0x1 << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P21 (0x1 << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P22 (0x1 << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P23 (0x1 << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P24 (0x1 << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P25 (0x1 << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P26 (0x1 << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P27 (0x1 << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P28 (0x1 << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P29 (0x1 << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P30 (0x1 << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -#define PIO_IDR_P31 (0x1 << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ -/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ -#define PIO_IMR_P0 (0x1 << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P1 (0x1 << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P2 (0x1 << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P3 (0x1 << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P4 (0x1 << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P5 (0x1 << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P6 (0x1 << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P7 (0x1 << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P8 (0x1 << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P9 (0x1 << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P10 (0x1 << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P11 (0x1 << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P12 (0x1 << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P13 (0x1 << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P14 (0x1 << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P15 (0x1 << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P16 (0x1 << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P17 (0x1 << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P18 (0x1 << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P19 (0x1 << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P20 (0x1 << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P21 (0x1 << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P22 (0x1 << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P23 (0x1 << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P24 (0x1 << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P25 (0x1 << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P26 (0x1 << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P27 (0x1 << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P28 (0x1 << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P29 (0x1 << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P30 (0x1 << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -#define PIO_IMR_P31 (0x1 << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ -/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ -#define PIO_ISR_P0 (0x1 << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P1 (0x1 << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P2 (0x1 << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P3 (0x1 << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P4 (0x1 << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P5 (0x1 << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P6 (0x1 << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P7 (0x1 << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P8 (0x1 << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P9 (0x1 << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P10 (0x1 << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P11 (0x1 << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P12 (0x1 << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P13 (0x1 << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P14 (0x1 << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P15 (0x1 << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P16 (0x1 << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P17 (0x1 << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P18 (0x1 << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P19 (0x1 << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P20 (0x1 << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P21 (0x1 << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P22 (0x1 << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P23 (0x1 << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P24 (0x1 << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P25 (0x1 << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P26 (0x1 << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P27 (0x1 << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P28 (0x1 << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P29 (0x1 << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P30 (0x1 << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -#define PIO_ISR_P31 (0x1 << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ -/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ -#define PIO_MDER_P0 (0x1 << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P1 (0x1 << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P2 (0x1 << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P3 (0x1 << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P4 (0x1 << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P5 (0x1 << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P6 (0x1 << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P7 (0x1 << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P8 (0x1 << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P9 (0x1 << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P10 (0x1 << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P11 (0x1 << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P12 (0x1 << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P13 (0x1 << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P14 (0x1 << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P15 (0x1 << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P16 (0x1 << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P17 (0x1 << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P18 (0x1 << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P19 (0x1 << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P20 (0x1 << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P21 (0x1 << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P22 (0x1 << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P23 (0x1 << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P24 (0x1 << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P25 (0x1 << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P26 (0x1 << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P27 (0x1 << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P28 (0x1 << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P29 (0x1 << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P30 (0x1 << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ -#define PIO_MDER_P31 (0x1 << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ -/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ -#define PIO_MDDR_P0 (0x1 << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P1 (0x1 << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P2 (0x1 << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P3 (0x1 << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P4 (0x1 << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P5 (0x1 << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P6 (0x1 << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P7 (0x1 << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P8 (0x1 << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P9 (0x1 << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P10 (0x1 << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P11 (0x1 << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P12 (0x1 << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P13 (0x1 << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P14 (0x1 << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P15 (0x1 << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P16 (0x1 << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P17 (0x1 << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P18 (0x1 << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P19 (0x1 << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P20 (0x1 << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P21 (0x1 << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P22 (0x1 << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P23 (0x1 << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P24 (0x1 << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P25 (0x1 << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P26 (0x1 << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P27 (0x1 << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P28 (0x1 << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P29 (0x1 << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P30 (0x1 << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -#define PIO_MDDR_P31 (0x1 << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ -/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ -#define PIO_MDSR_P0 (0x1 << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P1 (0x1 << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P2 (0x1 << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P3 (0x1 << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P4 (0x1 << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P5 (0x1 << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P6 (0x1 << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P7 (0x1 << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P8 (0x1 << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P9 (0x1 << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P10 (0x1 << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P11 (0x1 << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P12 (0x1 << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P13 (0x1 << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P14 (0x1 << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P15 (0x1 << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P16 (0x1 << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P17 (0x1 << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P18 (0x1 << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P19 (0x1 << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P20 (0x1 << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P21 (0x1 << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P22 (0x1 << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P23 (0x1 << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P24 (0x1 << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P25 (0x1 << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P26 (0x1 << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P27 (0x1 << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P28 (0x1 << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P29 (0x1 << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P30 (0x1 << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ -#define PIO_MDSR_P31 (0x1 << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ -/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ -#define PIO_PUDR_P0 (0x1 << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P1 (0x1 << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P2 (0x1 << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P3 (0x1 << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P4 (0x1 << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P5 (0x1 << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P6 (0x1 << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P7 (0x1 << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P8 (0x1 << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P9 (0x1 << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P10 (0x1 << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P11 (0x1 << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P12 (0x1 << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P13 (0x1 << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P14 (0x1 << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P15 (0x1 << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P16 (0x1 << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P17 (0x1 << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P18 (0x1 << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P19 (0x1 << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P20 (0x1 << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P21 (0x1 << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P22 (0x1 << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P23 (0x1 << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P24 (0x1 << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P25 (0x1 << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P26 (0x1 << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P27 (0x1 << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P28 (0x1 << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P29 (0x1 << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P30 (0x1 << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ -#define PIO_PUDR_P31 (0x1 << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ -/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ -#define PIO_PUER_P0 (0x1 << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P1 (0x1 << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P2 (0x1 << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P3 (0x1 << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P4 (0x1 << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P5 (0x1 << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P6 (0x1 << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P7 (0x1 << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P8 (0x1 << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P9 (0x1 << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P10 (0x1 << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P11 (0x1 << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P12 (0x1 << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P13 (0x1 << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P14 (0x1 << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P15 (0x1 << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P16 (0x1 << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P17 (0x1 << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P18 (0x1 << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P19 (0x1 << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P20 (0x1 << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P21 (0x1 << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P22 (0x1 << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P23 (0x1 << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P24 (0x1 << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P25 (0x1 << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P26 (0x1 << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P27 (0x1 << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P28 (0x1 << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P29 (0x1 << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P30 (0x1 << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ -#define PIO_PUER_P31 (0x1 << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ -/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ -#define PIO_PUSR_P0 (0x1 << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P1 (0x1 << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P2 (0x1 << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P3 (0x1 << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P4 (0x1 << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P5 (0x1 << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P6 (0x1 << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P7 (0x1 << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P8 (0x1 << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P9 (0x1 << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P10 (0x1 << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P11 (0x1 << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P12 (0x1 << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P13 (0x1 << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P14 (0x1 << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P15 (0x1 << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P16 (0x1 << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P17 (0x1 << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P18 (0x1 << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P19 (0x1 << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P20 (0x1 << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P21 (0x1 << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P22 (0x1 << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P23 (0x1 << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P24 (0x1 << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P25 (0x1 << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P26 (0x1 << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P27 (0x1 << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P28 (0x1 << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P29 (0x1 << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P30 (0x1 << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ -#define PIO_PUSR_P31 (0x1 << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ -/* -------- PIO_ABSR : (PIO Offset: 0x0070) Peripheral AB Select Register -------- */ -#define PIO_ABSR_P0 (0x1 << 0) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P1 (0x1 << 1) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P2 (0x1 << 2) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P3 (0x1 << 3) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P4 (0x1 << 4) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P5 (0x1 << 5) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P6 (0x1 << 6) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P7 (0x1 << 7) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P8 (0x1 << 8) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P9 (0x1 << 9) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P10 (0x1 << 10) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P11 (0x1 << 11) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P12 (0x1 << 12) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P13 (0x1 << 13) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P14 (0x1 << 14) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P15 (0x1 << 15) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P16 (0x1 << 16) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P17 (0x1 << 17) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P18 (0x1 << 18) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P19 (0x1 << 19) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P20 (0x1 << 20) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P21 (0x1 << 21) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P22 (0x1 << 22) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P23 (0x1 << 23) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P24 (0x1 << 24) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P25 (0x1 << 25) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P26 (0x1 << 26) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P27 (0x1 << 27) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P28 (0x1 << 28) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P29 (0x1 << 29) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P30 (0x1 << 30) /**< \brief (PIO_ABSR) Peripheral A Select. */ -#define PIO_ABSR_P31 (0x1 << 31) /**< \brief (PIO_ABSR) Peripheral A Select. */ -/* -------- PIO_SCIFSR : (PIO Offset: 0x0080) System Clock Glitch Input Filter Select Register -------- */ -#define PIO_SCIFSR_P0 (0x1 << 0) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P1 (0x1 << 1) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P2 (0x1 << 2) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P3 (0x1 << 3) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P4 (0x1 << 4) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P5 (0x1 << 5) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P6 (0x1 << 6) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P7 (0x1 << 7) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P8 (0x1 << 8) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P9 (0x1 << 9) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P10 (0x1 << 10) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P11 (0x1 << 11) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P12 (0x1 << 12) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P13 (0x1 << 13) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P14 (0x1 << 14) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P15 (0x1 << 15) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P16 (0x1 << 16) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P17 (0x1 << 17) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P18 (0x1 << 18) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P19 (0x1 << 19) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P20 (0x1 << 20) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P21 (0x1 << 21) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P22 (0x1 << 22) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P23 (0x1 << 23) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P24 (0x1 << 24) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P25 (0x1 << 25) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P26 (0x1 << 26) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P27 (0x1 << 27) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P28 (0x1 << 28) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P29 (0x1 << 29) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P30 (0x1 << 30) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -#define PIO_SCIFSR_P31 (0x1 << 31) /**< \brief (PIO_SCIFSR) System Clock Glitch Filtering Select. */ -/* -------- PIO_DIFSR : (PIO Offset: 0x0084) Debouncing Input Filter Select Register -------- */ -#define PIO_DIFSR_P0 (0x1 << 0) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P1 (0x1 << 1) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P2 (0x1 << 2) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P3 (0x1 << 3) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P4 (0x1 << 4) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P5 (0x1 << 5) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P6 (0x1 << 6) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P7 (0x1 << 7) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P8 (0x1 << 8) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P9 (0x1 << 9) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P10 (0x1 << 10) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P11 (0x1 << 11) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P12 (0x1 << 12) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P13 (0x1 << 13) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P14 (0x1 << 14) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P15 (0x1 << 15) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P16 (0x1 << 16) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P17 (0x1 << 17) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P18 (0x1 << 18) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P19 (0x1 << 19) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P20 (0x1 << 20) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P21 (0x1 << 21) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P22 (0x1 << 22) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P23 (0x1 << 23) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P24 (0x1 << 24) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P25 (0x1 << 25) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P26 (0x1 << 26) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P27 (0x1 << 27) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P28 (0x1 << 28) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P29 (0x1 << 29) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P30 (0x1 << 30) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -#define PIO_DIFSR_P31 (0x1 << 31) /**< \brief (PIO_DIFSR) Debouncing Filtering Select. */ -/* -------- PIO_IFDGSR : (PIO Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register -------- */ -#define PIO_IFDGSR_P0 (0x1 << 0) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P1 (0x1 << 1) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P2 (0x1 << 2) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P3 (0x1 << 3) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P4 (0x1 << 4) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P5 (0x1 << 5) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P6 (0x1 << 6) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P7 (0x1 << 7) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P8 (0x1 << 8) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P9 (0x1 << 9) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P10 (0x1 << 10) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P11 (0x1 << 11) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P12 (0x1 << 12) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P13 (0x1 << 13) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P14 (0x1 << 14) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P15 (0x1 << 15) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P16 (0x1 << 16) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P17 (0x1 << 17) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P18 (0x1 << 18) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P19 (0x1 << 19) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P20 (0x1 << 20) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P21 (0x1 << 21) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P22 (0x1 << 22) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P23 (0x1 << 23) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P24 (0x1 << 24) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P25 (0x1 << 25) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P26 (0x1 << 26) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P27 (0x1 << 27) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P28 (0x1 << 28) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P29 (0x1 << 29) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P30 (0x1 << 30) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -#define PIO_IFDGSR_P31 (0x1 << 31) /**< \brief (PIO_IFDGSR) Glitch or Debouncing Filter Selection Status */ -/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ -#define PIO_SCDR_DIV0 (0x1 << 0) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV1 (0x1 << 1) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV2 (0x1 << 2) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV3 (0x1 << 3) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV4 (0x1 << 4) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV5 (0x1 << 5) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV6 (0x1 << 6) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV7 (0x1 << 7) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV8 (0x1 << 8) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV9 (0x1 << 9) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV10 (0x1 << 10) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV11 (0x1 << 11) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV12 (0x1 << 12) /**< \brief (PIO_SCDR) */ -#define PIO_SCDR_DIV13 (0x1 << 13) /**< \brief (PIO_SCDR) */ -/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ -#define PIO_OWER_P0 (0x1 << 0) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P1 (0x1 << 1) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P2 (0x1 << 2) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P3 (0x1 << 3) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P4 (0x1 << 4) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P5 (0x1 << 5) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P6 (0x1 << 6) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P7 (0x1 << 7) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P8 (0x1 << 8) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P9 (0x1 << 9) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P10 (0x1 << 10) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P11 (0x1 << 11) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P12 (0x1 << 12) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P13 (0x1 << 13) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P14 (0x1 << 14) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P15 (0x1 << 15) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P16 (0x1 << 16) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P17 (0x1 << 17) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P18 (0x1 << 18) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P19 (0x1 << 19) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P20 (0x1 << 20) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P21 (0x1 << 21) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P22 (0x1 << 22) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P23 (0x1 << 23) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P24 (0x1 << 24) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P25 (0x1 << 25) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P26 (0x1 << 26) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P27 (0x1 << 27) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P28 (0x1 << 28) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P29 (0x1 << 29) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P30 (0x1 << 30) /**< \brief (PIO_OWER) Output Write Enable. */ -#define PIO_OWER_P31 (0x1 << 31) /**< \brief (PIO_OWER) Output Write Enable. */ -/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ -#define PIO_OWDR_P0 (0x1 << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P1 (0x1 << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P2 (0x1 << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P3 (0x1 << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P4 (0x1 << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P5 (0x1 << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P6 (0x1 << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P7 (0x1 << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P8 (0x1 << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P9 (0x1 << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P10 (0x1 << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P11 (0x1 << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P12 (0x1 << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P13 (0x1 << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P14 (0x1 << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P15 (0x1 << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P16 (0x1 << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P17 (0x1 << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P18 (0x1 << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P19 (0x1 << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P20 (0x1 << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P21 (0x1 << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P22 (0x1 << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P23 (0x1 << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P24 (0x1 << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P25 (0x1 << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P26 (0x1 << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P27 (0x1 << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P28 (0x1 << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P29 (0x1 << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P30 (0x1 << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ -#define PIO_OWDR_P31 (0x1 << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ -/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ -#define PIO_OWSR_P0 (0x1 << 0) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P1 (0x1 << 1) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P2 (0x1 << 2) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P3 (0x1 << 3) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P4 (0x1 << 4) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P5 (0x1 << 5) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P6 (0x1 << 6) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P7 (0x1 << 7) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P8 (0x1 << 8) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P9 (0x1 << 9) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P10 (0x1 << 10) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P11 (0x1 << 11) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P12 (0x1 << 12) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P13 (0x1 << 13) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P14 (0x1 << 14) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P15 (0x1 << 15) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P16 (0x1 << 16) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P17 (0x1 << 17) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P18 (0x1 << 18) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P19 (0x1 << 19) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P20 (0x1 << 20) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P21 (0x1 << 21) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P22 (0x1 << 22) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P23 (0x1 << 23) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P24 (0x1 << 24) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P25 (0x1 << 25) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P26 (0x1 << 26) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P27 (0x1 << 27) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P28 (0x1 << 28) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P29 (0x1 << 29) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P30 (0x1 << 30) /**< \brief (PIO_OWSR) Output Write Status. */ -#define PIO_OWSR_P31 (0x1 << 31) /**< \brief (PIO_OWSR) Output Write Status. */ -/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ -#define PIO_AIMER_P0 (0x1 << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P1 (0x1 << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P2 (0x1 << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P3 (0x1 << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P4 (0x1 << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P5 (0x1 << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P6 (0x1 << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P7 (0x1 << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P8 (0x1 << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P9 (0x1 << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P10 (0x1 << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P11 (0x1 << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P12 (0x1 << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P13 (0x1 << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P14 (0x1 << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P15 (0x1 << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P16 (0x1 << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P17 (0x1 << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P18 (0x1 << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P19 (0x1 << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P20 (0x1 << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P21 (0x1 << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P22 (0x1 << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P23 (0x1 << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P24 (0x1 << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P25 (0x1 << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P26 (0x1 << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P27 (0x1 << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P28 (0x1 << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P29 (0x1 << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P30 (0x1 << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -#define PIO_AIMER_P31 (0x1 << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ -/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ -#define PIO_AIMDR_P0 (0x1 << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P1 (0x1 << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P2 (0x1 << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P3 (0x1 << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P4 (0x1 << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P5 (0x1 << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P6 (0x1 << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P7 (0x1 << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P8 (0x1 << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P9 (0x1 << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P10 (0x1 << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P11 (0x1 << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P12 (0x1 << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P13 (0x1 << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P14 (0x1 << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P15 (0x1 << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P16 (0x1 << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P17 (0x1 << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P18 (0x1 << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P19 (0x1 << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P20 (0x1 << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P21 (0x1 << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P22 (0x1 << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P23 (0x1 << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P24 (0x1 << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P25 (0x1 << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P26 (0x1 << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P27 (0x1 << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P28 (0x1 << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P29 (0x1 << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P30 (0x1 << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -#define PIO_AIMDR_P31 (0x1 << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ -/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ -#define PIO_AIMMR_P0 (0x1 << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P1 (0x1 << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P2 (0x1 << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P3 (0x1 << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P4 (0x1 << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P5 (0x1 << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P6 (0x1 << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P7 (0x1 << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P8 (0x1 << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P9 (0x1 << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P10 (0x1 << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P11 (0x1 << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P12 (0x1 << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P13 (0x1 << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P14 (0x1 << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P15 (0x1 << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P16 (0x1 << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P17 (0x1 << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P18 (0x1 << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P19 (0x1 << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P20 (0x1 << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P21 (0x1 << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P22 (0x1 << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P23 (0x1 << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P24 (0x1 << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P25 (0x1 << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P26 (0x1 << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P27 (0x1 << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P28 (0x1 << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P29 (0x1 << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P30 (0x1 << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -#define PIO_AIMMR_P31 (0x1 << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ -/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ -#define PIO_ESR_P0 (0x1 << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P1 (0x1 << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P2 (0x1 << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P3 (0x1 << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P4 (0x1 << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P5 (0x1 << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P6 (0x1 << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P7 (0x1 << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P8 (0x1 << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P9 (0x1 << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P10 (0x1 << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P11 (0x1 << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P12 (0x1 << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P13 (0x1 << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P14 (0x1 << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P15 (0x1 << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P16 (0x1 << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P17 (0x1 << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P18 (0x1 << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P19 (0x1 << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P20 (0x1 << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P21 (0x1 << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P22 (0x1 << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P23 (0x1 << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P24 (0x1 << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P25 (0x1 << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P26 (0x1 << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P27 (0x1 << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P28 (0x1 << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P29 (0x1 << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P30 (0x1 << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -#define PIO_ESR_P31 (0x1 << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ -/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ -#define PIO_LSR_P0 (0x1 << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P1 (0x1 << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P2 (0x1 << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P3 (0x1 << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P4 (0x1 << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P5 (0x1 << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P6 (0x1 << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P7 (0x1 << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P8 (0x1 << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P9 (0x1 << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P10 (0x1 << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P11 (0x1 << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P12 (0x1 << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P13 (0x1 << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P14 (0x1 << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P15 (0x1 << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P16 (0x1 << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P17 (0x1 << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P18 (0x1 << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P19 (0x1 << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P20 (0x1 << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P21 (0x1 << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P22 (0x1 << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P23 (0x1 << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P24 (0x1 << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P25 (0x1 << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P26 (0x1 << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P27 (0x1 << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P28 (0x1 << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P29 (0x1 << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P30 (0x1 << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -#define PIO_LSR_P31 (0x1 << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ -/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ -#define PIO_ELSR_P0 (0x1 << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P1 (0x1 << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P2 (0x1 << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P3 (0x1 << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P4 (0x1 << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P5 (0x1 << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P6 (0x1 << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P7 (0x1 << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P8 (0x1 << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P9 (0x1 << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P10 (0x1 << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P11 (0x1 << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P12 (0x1 << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P13 (0x1 << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P14 (0x1 << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P15 (0x1 << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P16 (0x1 << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P17 (0x1 << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P18 (0x1 << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P19 (0x1 << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P20 (0x1 << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P21 (0x1 << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P22 (0x1 << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P23 (0x1 << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P24 (0x1 << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P25 (0x1 << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P26 (0x1 << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P27 (0x1 << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P28 (0x1 << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P29 (0x1 << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P30 (0x1 << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -#define PIO_ELSR_P31 (0x1 << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ -/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ -#define PIO_FELLSR_P0 (0x1 << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P1 (0x1 << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P2 (0x1 << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P3 (0x1 << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P4 (0x1 << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P5 (0x1 << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P6 (0x1 << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P7 (0x1 << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P8 (0x1 << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P9 (0x1 << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P10 (0x1 << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P11 (0x1 << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P12 (0x1 << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P13 (0x1 << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P14 (0x1 << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P15 (0x1 << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P16 (0x1 << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P17 (0x1 << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P18 (0x1 << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P19 (0x1 << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P20 (0x1 << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P21 (0x1 << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P22 (0x1 << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P23 (0x1 << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P24 (0x1 << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P25 (0x1 << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P26 (0x1 << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P27 (0x1 << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P28 (0x1 << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P29 (0x1 << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P30 (0x1 << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -#define PIO_FELLSR_P31 (0x1 << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ -/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ -#define PIO_REHLSR_P0 (0x1 << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P1 (0x1 << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P2 (0x1 << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P3 (0x1 << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P4 (0x1 << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P5 (0x1 << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P6 (0x1 << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P7 (0x1 << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P8 (0x1 << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P9 (0x1 << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P10 (0x1 << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P11 (0x1 << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P12 (0x1 << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P13 (0x1 << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P14 (0x1 << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P15 (0x1 << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P16 (0x1 << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P17 (0x1 << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P18 (0x1 << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P19 (0x1 << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P20 (0x1 << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P21 (0x1 << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P22 (0x1 << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P23 (0x1 << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P24 (0x1 << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P25 (0x1 << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P26 (0x1 << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P27 (0x1 << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P28 (0x1 << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P29 (0x1 << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P30 (0x1 << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -#define PIO_REHLSR_P31 (0x1 << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ -/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ -#define PIO_FRLHSR_P0 (0x1 << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P1 (0x1 << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P2 (0x1 << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P3 (0x1 << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P4 (0x1 << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P5 (0x1 << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P6 (0x1 << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P7 (0x1 << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P8 (0x1 << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P9 (0x1 << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P10 (0x1 << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P11 (0x1 << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P12 (0x1 << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P13 (0x1 << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P14 (0x1 << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P15 (0x1 << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P16 (0x1 << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P17 (0x1 << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P18 (0x1 << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P19 (0x1 << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P20 (0x1 << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P21 (0x1 << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P22 (0x1 << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P23 (0x1 << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P24 (0x1 << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P25 (0x1 << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P26 (0x1 << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P27 (0x1 << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P28 (0x1 << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P29 (0x1 << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P30 (0x1 << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -#define PIO_FRLHSR_P31 (0x1 << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ -/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ -#define PIO_LOCKSR_P0 (0x1 << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P1 (0x1 << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P2 (0x1 << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P3 (0x1 << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P4 (0x1 << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P5 (0x1 << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P6 (0x1 << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P7 (0x1 << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P8 (0x1 << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P9 (0x1 << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P10 (0x1 << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P11 (0x1 << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P12 (0x1 << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P13 (0x1 << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P14 (0x1 << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P15 (0x1 << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P16 (0x1 << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P17 (0x1 << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P18 (0x1 << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P19 (0x1 << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P20 (0x1 << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P21 (0x1 << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P22 (0x1 << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P23 (0x1 << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P24 (0x1 << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P25 (0x1 << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P26 (0x1 << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P27 (0x1 << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P28 (0x1 << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P29 (0x1 << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P30 (0x1 << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ -#define PIO_LOCKSR_P31 (0x1 << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ -/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ -#define PIO_WPMR_WPEN (0x1 << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ -#define PIO_WPMR_WPKEY (0xffffff << 8) /**< \brief (PIO_WPMR) Write Protect KEY */ -/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ -#define PIO_WPSR_WPVS (0x1 << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ -#define PIO_WPSR_WPVSRC (0xffff << 8) /**< \brief (PIO_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Power Management Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_PMC Power Management Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Pmc hardware registers */ -typedef struct { - WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ - WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ - RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ - RwReg Reserved1[1]; - WoReg PMC_PCER; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register */ - WoReg PMC_PCDR; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register */ - RoReg PMC_PCSR; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register */ - RwReg CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */ - RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ - RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ - RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ - RwReg Reserved2[1]; - RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ - RwReg Reserved3[3]; - RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ - RwReg Reserved4[5]; - WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ - WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ - RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ - RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ - RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ - RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ - WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ -} Pmc; -#endif /* __ASSEMBLY__ */ -/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ -#define PMC_SCER_PCK0 (0x1 << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ -#define PMC_SCER_PCK1 (0x1 << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ -#define PMC_SCER_PCK2 (0x1 << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ -/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ -#define PMC_SCDR_PCK0 (0x1 << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ -#define PMC_SCDR_PCK1 (0x1 << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ -#define PMC_SCDR_PCK2 (0x1 << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ -/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ -#define PMC_SCSR_PCK0 (0x1 << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ -#define PMC_SCSR_PCK1 (0x1 << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ -#define PMC_SCSR_PCK2 (0x1 << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ -/* -------- PMC_PCER : (PMC Offset: 0x0010) Peripheral Clock Enable Register -------- */ -#define PMC_PCER_PID2 (0x1 << 2) /**< \brief (PMC_PCER) Peripheral Clock 2 Enable */ -#define PMC_PCER_PID3 (0x1 << 3) /**< \brief (PMC_PCER) Peripheral Clock 3 Enable */ -#define PMC_PCER_PID4 (0x1 << 4) /**< \brief (PMC_PCER) Peripheral Clock 4 Enable */ -#define PMC_PCER_PID5 (0x1 << 5) /**< \brief (PMC_PCER) Peripheral Clock 5 Enable */ -#define PMC_PCER_PID6 (0x1 << 6) /**< \brief (PMC_PCER) Peripheral Clock 6 Enable */ -#define PMC_PCER_PID7 (0x1 << 7) /**< \brief (PMC_PCER) Peripheral Clock 7 Enable */ -#define PMC_PCER_PID8 (0x1 << 8) /**< \brief (PMC_PCER) Peripheral Clock 8 Enable */ -#define PMC_PCER_PID9 (0x1 << 9) /**< \brief (PMC_PCER) Peripheral Clock 9 Enable */ -#define PMC_PCER_PID10 (0x1 << 10) /**< \brief (PMC_PCER) Peripheral Clock 10 Enable */ -#define PMC_PCER_PID11 (0x1 << 11) /**< \brief (PMC_PCER) Peripheral Clock 11 Enable */ -#define PMC_PCER_PID12 (0x1 << 12) /**< \brief (PMC_PCER) Peripheral Clock 12 Enable */ -#define PMC_PCER_PID13 (0x1 << 13) /**< \brief (PMC_PCER) Peripheral Clock 13 Enable */ -#define PMC_PCER_PID14 (0x1 << 14) /**< \brief (PMC_PCER) Peripheral Clock 14 Enable */ -#define PMC_PCER_PID15 (0x1 << 15) /**< \brief (PMC_PCER) Peripheral Clock 15 Enable */ -#define PMC_PCER_PID16 (0x1 << 16) /**< \brief (PMC_PCER) Peripheral Clock 16 Enable */ -#define PMC_PCER_PID17 (0x1 << 17) /**< \brief (PMC_PCER) Peripheral Clock 17 Enable */ -#define PMC_PCER_PID18 (0x1 << 18) /**< \brief (PMC_PCER) Peripheral Clock 18 Enable */ -#define PMC_PCER_PID19 (0x1 << 19) /**< \brief (PMC_PCER) Peripheral Clock 19 Enable */ -#define PMC_PCER_PID20 (0x1 << 20) /**< \brief (PMC_PCER) Peripheral Clock 20 Enable */ -#define PMC_PCER_PID21 (0x1 << 21) /**< \brief (PMC_PCER) Peripheral Clock 21 Enable */ -#define PMC_PCER_PID22 (0x1 << 22) /**< \brief (PMC_PCER) Peripheral Clock 22 Enable */ -#define PMC_PCER_PID23 (0x1 << 23) /**< \brief (PMC_PCER) Peripheral Clock 23 Enable */ -#define PMC_PCER_PID24 (0x1 << 24) /**< \brief (PMC_PCER) Peripheral Clock 24 Enable */ -#define PMC_PCER_PID25 (0x1 << 25) /**< \brief (PMC_PCER) Peripheral Clock 25 Enable */ -#define PMC_PCER_PID26 (0x1 << 26) /**< \brief (PMC_PCER) Peripheral Clock 26 Enable */ -#define PMC_PCER_PID27 (0x1 << 27) /**< \brief (PMC_PCER) Peripheral Clock 27 Enable */ -#define PMC_PCER_PID28 (0x1 << 28) /**< \brief (PMC_PCER) Peripheral Clock 28 Enable */ -#define PMC_PCER_PID29 (0x1 << 29) /**< \brief (PMC_PCER) Peripheral Clock 29 Enable */ -#define PMC_PCER_PID30 (0x1 << 30) /**< \brief (PMC_PCER) Peripheral Clock 30 Enable */ -#define PMC_PCER_PID31 (0x1 << 31) /**< \brief (PMC_PCER) Peripheral Clock 31 Enable */ -/* -------- PMC_PCDR : (PMC Offset: 0x0014) Peripheral Clock Disable Register -------- */ -#define PMC_PCDR_PID2 (0x1 << 2) /**< \brief (PMC_PCDR) Peripheral Clock 2 Disable */ -#define PMC_PCDR_PID3 (0x1 << 3) /**< \brief (PMC_PCDR) Peripheral Clock 3 Disable */ -#define PMC_PCDR_PID4 (0x1 << 4) /**< \brief (PMC_PCDR) Peripheral Clock 4 Disable */ -#define PMC_PCDR_PID5 (0x1 << 5) /**< \brief (PMC_PCDR) Peripheral Clock 5 Disable */ -#define PMC_PCDR_PID6 (0x1 << 6) /**< \brief (PMC_PCDR) Peripheral Clock 6 Disable */ -#define PMC_PCDR_PID7 (0x1 << 7) /**< \brief (PMC_PCDR) Peripheral Clock 7 Disable */ -#define PMC_PCDR_PID8 (0x1 << 8) /**< \brief (PMC_PCDR) Peripheral Clock 8 Disable */ -#define PMC_PCDR_PID9 (0x1 << 9) /**< \brief (PMC_PCDR) Peripheral Clock 9 Disable */ -#define PMC_PCDR_PID10 (0x1 << 10) /**< \brief (PMC_PCDR) Peripheral Clock 10 Disable */ -#define PMC_PCDR_PID11 (0x1 << 11) /**< \brief (PMC_PCDR) Peripheral Clock 11 Disable */ -#define PMC_PCDR_PID12 (0x1 << 12) /**< \brief (PMC_PCDR) Peripheral Clock 12 Disable */ -#define PMC_PCDR_PID13 (0x1 << 13) /**< \brief (PMC_PCDR) Peripheral Clock 13 Disable */ -#define PMC_PCDR_PID14 (0x1 << 14) /**< \brief (PMC_PCDR) Peripheral Clock 14 Disable */ -#define PMC_PCDR_PID15 (0x1 << 15) /**< \brief (PMC_PCDR) Peripheral Clock 15 Disable */ -#define PMC_PCDR_PID16 (0x1 << 16) /**< \brief (PMC_PCDR) Peripheral Clock 16 Disable */ -#define PMC_PCDR_PID17 (0x1 << 17) /**< \brief (PMC_PCDR) Peripheral Clock 17 Disable */ -#define PMC_PCDR_PID18 (0x1 << 18) /**< \brief (PMC_PCDR) Peripheral Clock 18 Disable */ -#define PMC_PCDR_PID19 (0x1 << 19) /**< \brief (PMC_PCDR) Peripheral Clock 19 Disable */ -#define PMC_PCDR_PID20 (0x1 << 20) /**< \brief (PMC_PCDR) Peripheral Clock 20 Disable */ -#define PMC_PCDR_PID21 (0x1 << 21) /**< \brief (PMC_PCDR) Peripheral Clock 21 Disable */ -#define PMC_PCDR_PID22 (0x1 << 22) /**< \brief (PMC_PCDR) Peripheral Clock 22 Disable */ -#define PMC_PCDR_PID23 (0x1 << 23) /**< \brief (PMC_PCDR) Peripheral Clock 23 Disable */ -#define PMC_PCDR_PID24 (0x1 << 24) /**< \brief (PMC_PCDR) Peripheral Clock 24 Disable */ -#define PMC_PCDR_PID25 (0x1 << 25) /**< \brief (PMC_PCDR) Peripheral Clock 25 Disable */ -#define PMC_PCDR_PID26 (0x1 << 26) /**< \brief (PMC_PCDR) Peripheral Clock 26 Disable */ -#define PMC_PCDR_PID27 (0x1 << 27) /**< \brief (PMC_PCDR) Peripheral Clock 27 Disable */ -#define PMC_PCDR_PID28 (0x1 << 28) /**< \brief (PMC_PCDR) Peripheral Clock 28 Disable */ -#define PMC_PCDR_PID29 (0x1 << 29) /**< \brief (PMC_PCDR) Peripheral Clock 29 Disable */ -#define PMC_PCDR_PID30 (0x1 << 30) /**< \brief (PMC_PCDR) Peripheral Clock 30 Disable */ -#define PMC_PCDR_PID31 (0x1 << 31) /**< \brief (PMC_PCDR) Peripheral Clock 31 Disable */ -/* -------- PMC_PCSR : (PMC Offset: 0x0018) Peripheral Clock Status Register -------- */ -#define PMC_PCSR_PID2 (0x1 << 2) /**< \brief (PMC_PCSR) Peripheral Clock 2 Status */ -#define PMC_PCSR_PID3 (0x1 << 3) /**< \brief (PMC_PCSR) Peripheral Clock 3 Status */ -#define PMC_PCSR_PID4 (0x1 << 4) /**< \brief (PMC_PCSR) Peripheral Clock 4 Status */ -#define PMC_PCSR_PID5 (0x1 << 5) /**< \brief (PMC_PCSR) Peripheral Clock 5 Status */ -#define PMC_PCSR_PID6 (0x1 << 6) /**< \brief (PMC_PCSR) Peripheral Clock 6 Status */ -#define PMC_PCSR_PID7 (0x1 << 7) /**< \brief (PMC_PCSR) Peripheral Clock 7 Status */ -#define PMC_PCSR_PID8 (0x1 << 8) /**< \brief (PMC_PCSR) Peripheral Clock 8 Status */ -#define PMC_PCSR_PID9 (0x1 << 9) /**< \brief (PMC_PCSR) Peripheral Clock 9 Status */ -#define PMC_PCSR_PID10 (0x1 << 10) /**< \brief (PMC_PCSR) Peripheral Clock 10 Status */ -#define PMC_PCSR_PID11 (0x1 << 11) /**< \brief (PMC_PCSR) Peripheral Clock 11 Status */ -#define PMC_PCSR_PID12 (0x1 << 12) /**< \brief (PMC_PCSR) Peripheral Clock 12 Status */ -#define PMC_PCSR_PID13 (0x1 << 13) /**< \brief (PMC_PCSR) Peripheral Clock 13 Status */ -#define PMC_PCSR_PID14 (0x1 << 14) /**< \brief (PMC_PCSR) Peripheral Clock 14 Status */ -#define PMC_PCSR_PID15 (0x1 << 15) /**< \brief (PMC_PCSR) Peripheral Clock 15 Status */ -#define PMC_PCSR_PID16 (0x1 << 16) /**< \brief (PMC_PCSR) Peripheral Clock 16 Status */ -#define PMC_PCSR_PID17 (0x1 << 17) /**< \brief (PMC_PCSR) Peripheral Clock 17 Status */ -#define PMC_PCSR_PID18 (0x1 << 18) /**< \brief (PMC_PCSR) Peripheral Clock 18 Status */ -#define PMC_PCSR_PID19 (0x1 << 19) /**< \brief (PMC_PCSR) Peripheral Clock 19 Status */ -#define PMC_PCSR_PID20 (0x1 << 20) /**< \brief (PMC_PCSR) Peripheral Clock 20 Status */ -#define PMC_PCSR_PID21 (0x1 << 21) /**< \brief (PMC_PCSR) Peripheral Clock 21 Status */ -#define PMC_PCSR_PID22 (0x1 << 22) /**< \brief (PMC_PCSR) Peripheral Clock 22 Status */ -#define PMC_PCSR_PID23 (0x1 << 23) /**< \brief (PMC_PCSR) Peripheral Clock 23 Status */ -#define PMC_PCSR_PID24 (0x1 << 24) /**< \brief (PMC_PCSR) Peripheral Clock 24 Status */ -#define PMC_PCSR_PID25 (0x1 << 25) /**< \brief (PMC_PCSR) Peripheral Clock 25 Status */ -#define PMC_PCSR_PID26 (0x1 << 26) /**< \brief (PMC_PCSR) Peripheral Clock 26 Status */ -#define PMC_PCSR_PID27 (0x1 << 27) /**< \brief (PMC_PCSR) Peripheral Clock 27 Status */ -#define PMC_PCSR_PID28 (0x1 << 28) /**< \brief (PMC_PCSR) Peripheral Clock 28 Status */ -#define PMC_PCSR_PID29 (0x1 << 29) /**< \brief (PMC_PCSR) Peripheral Clock 29 Status */ -#define PMC_PCSR_PID30 (0x1 << 30) /**< \brief (PMC_PCSR) Peripheral Clock 30 Status */ -#define PMC_PCSR_PID31 (0x1 << 31) /**< \brief (PMC_PCSR) Peripheral Clock 31 Status */ -/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */ -#define CKGR_UCKR_UPLLEN (0x1 << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */ -#define CKGR_UCKR_UPLLCOUNT (0xf << 20) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */ -/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ -#define CKGR_MOR_MOSCXTEN (0x1 << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ -#define CKGR_MOR_MOSCXTBY (0x1 << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ -#define CKGR_MOR_WAITMODE (0x1 << 2) /**< \brief (CKGR_MOR) Wait Mode Command */ -#define CKGR_MOR_MOSCRCEN (0x1 << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ -#define CKGR_MOR_MOSCRCF (0x7 << 4) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ -#define CKGR_MOR_MOSCXTST (0xff << 8) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ -#define CKGR_MOR_KEY (0xff << 16) /**< \brief (CKGR_MOR) Password */ -#define CKGR_MOR_MOSCSEL (0x1 << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ -#define CKGR_MOR_CFDEN (0x1 << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ -/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ -#define CKGR_MCFR_MAINF (0xffff << 0) /**< \brief (CKGR_MCFR) Main Clock Frequency */ -#define CKGR_MCFR_MAINFRDY (0x1 << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ -/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ -#define CKGR_PLLAR_DIVA (0xff << 0) /**< \brief (CKGR_PLLAR) Divider */ -#define CKGR_PLLAR_PLLACOUNT (0x3f << 8) /**< \brief (CKGR_PLLAR) PLLA Counter */ -#define CKGR_PLLAR_STMODE (0x3 << 14) /**< \brief (CKGR_PLLAR) Start Mode */ -#define CKGR_PLLAR_MULA (0x7ff << 16) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ -#define CKGR_PLLAR_STUCKTO1 (0x1 << 29) /**< \brief (CKGR_PLLAR) */ -/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ -#define PMC_MCKR_CSS (0x3 << 0) /**< \brief (PMC_MCKR) Master Clock Source Selection */ -#define PMC_MCKR_CSS_SLOW_CLK (0x0 << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ -#define PMC_MCKR_CSS_MAIN_CLK (0x1 << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ -#define PMC_MCKR_CSS_PLLA_CLK (0x2 << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ -#define PMC_MCKR_CSS_PLLB_CLK (0x3 << 0) /**< \brief (PMC_MCKR) UPLL Clock is selected */ -#define PMC_MCKR_PRES (0x7 << 4) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ -#define PMC_MCKR_PRES_CLK (0x0 << 4) /**< \brief (PMC_MCKR) Selected clock */ -#define PMC_MCKR_PRES_CLK_2 (0x1 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ -#define PMC_MCKR_PRES_CLK_4 (0x2 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ -#define PMC_MCKR_PRES_CLK_8 (0x3 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ -#define PMC_MCKR_PRES_CLK_16 (0x4 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ -#define PMC_MCKR_PRES_CLK_32 (0x5 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ -#define PMC_MCKR_PRES_CLK_64 (0x6 << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ -/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ -#define PMC_PCK_CSS (0x7 << 0) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ -#define PMC_PCK_PRES (0x7 << 4) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ -/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ -#define PMC_IER_MOSCXTS (0x1 << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ -#define PMC_IER_LOCKA (0x1 << 1) /**< \brief (PMC_IER) PLL A Lock Interrupt Enable */ -#define PMC_IER_MCKRDY (0x1 << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ -#define PMC_IER_LOCKU (0x1 << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */ -#define PMC_IER_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ -#define PMC_IER_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ -#define PMC_IER_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ -#define PMC_IER_MOSCSELS (0x1 << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ -#define PMC_IER_MOSCRCS (0x1 << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ -#define PMC_IER_CFDEV (0x1 << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ -/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ -#define PMC_IDR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ -#define PMC_IDR_LOCKA (0x1 << 1) /**< \brief (PMC_IDR) PLL A Lock Interrupt Disable */ -#define PMC_IDR_MCKRDY (0x1 << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ -#define PMC_IDR_LOCKU (0x1 << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */ -#define PMC_IDR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ -#define PMC_IDR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ -#define PMC_IDR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ -#define PMC_IDR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ -#define PMC_IDR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ -#define PMC_IDR_CFDEV (0x1 << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ -/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ -#define PMC_SR_MOSCXTS (0x1 << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ -#define PMC_SR_LOCKA (0x1 << 1) /**< \brief (PMC_SR) PLL A Lock Status */ -#define PMC_SR_MCKRDY (0x1 << 3) /**< \brief (PMC_SR) Master Clock Status */ -#define PMC_SR_LOCKU (0x1 << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */ -#define PMC_SR_OSCSELS (0x1 << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ -#define PMC_SR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ -#define PMC_SR_MOSCSELS (0x1 << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ -#define PMC_SR_MOSCRCS (0x1 << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ -#define PMC_SR_CFDEV (0x1 << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ -#define PMC_SR_CFDS (0x1 << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ -#define PMC_SR_FOS (0x1 << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ -/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ -#define PMC_IMR_MOSCXTS (0x1 << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ -#define PMC_IMR_LOCKA (0x1 << 1) /**< \brief (PMC_IMR) PLL A Lock Interrupt Mask */ -#define PMC_IMR_MCKRDY (0x1 << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ -#define PMC_IMR_LOCKU (0x1 << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */ -#define PMC_IMR_PCKRDY0 (0x1 << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ -#define PMC_IMR_PCKRDY1 (0x1 << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ -#define PMC_IMR_PCKRDY2 (0x1 << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ -#define PMC_IMR_MOSCSELS (0x1 << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ -#define PMC_IMR_MOSCRCS (0x1 << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ -#define PMC_IMR_CFDEV (0x1 << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ -/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ -#define PMC_FSMR_FSTT0 (0x1 << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ -#define PMC_FSMR_FSTT1 (0x1 << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ -#define PMC_FSMR_FSTT2 (0x1 << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ -#define PMC_FSMR_FSTT3 (0x1 << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ -#define PMC_FSMR_FSTT4 (0x1 << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ -#define PMC_FSMR_FSTT5 (0x1 << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ -#define PMC_FSMR_FSTT6 (0x1 << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ -#define PMC_FSMR_FSTT7 (0x1 << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ -#define PMC_FSMR_FSTT8 (0x1 << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ -#define PMC_FSMR_FSTT9 (0x1 << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ -#define PMC_FSMR_FSTT10 (0x1 << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ -#define PMC_FSMR_FSTT11 (0x1 << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ -#define PMC_FSMR_FSTT12 (0x1 << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ -#define PMC_FSMR_FSTT13 (0x1 << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ -#define PMC_FSMR_FSTT14 (0x1 << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ -#define PMC_FSMR_FSTT15 (0x1 << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ -#define PMC_FSMR_RTTAL (0x1 << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ -#define PMC_FSMR_RTCAL (0x1 << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ -#define PMC_FSMR_USBAL (0x1 << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ -#define PMC_FSMR_LPM (0x1 << 20) /**< \brief (PMC_FSMR) Low Power Mode */ -/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ -#define PMC_FSPR_FSTP0 (0x1 << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 0 */ -#define PMC_FSPR_FSTP1 (0x1 << 1) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP2 (0x1 << 2) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP3 (0x1 << 3) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP4 (0x1 << 4) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP5 (0x1 << 5) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP6 (0x1 << 6) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP7 (0x1 << 7) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP8 (0x1 << 8) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP9 (0x1 << 9) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP10 (0x1 << 10) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP11 (0x1 << 11) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP12 (0x1 << 12) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP13 (0x1 << 13) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP14 (0x1 << 14) /**< \brief (PMC_FSPR) */ -#define PMC_FSPR_FSTP15 (0x1 << 15) /**< \brief (PMC_FSPR) */ -/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ -#define PMC_FOCR_FOCLR (0x1 << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_PWM Pulse Width Modulation Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief PwmCh_num hardware registers */ -typedef struct { - RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ - RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ - RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ - RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ - RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ - RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ - RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ - RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ -} PwmCh_num; -/** \brief Pwm hardware registers */ -typedef struct { - RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ - WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ - WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ - RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ - WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ - WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ - RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ - RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ - RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ - RwReg Reserved1[1]; - RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ - RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ - WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ - WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ - WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ - RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ - RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ - RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ - RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ - WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ - WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ - WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ - WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ - RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ - RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ - WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ - RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */ - RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ - RwReg Reserved2[3]; - RwReg PWM_ELxMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ - RwReg Reserved3[24]; - WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ - RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ - RwReg Reserved4[5]; - RwReg PWM_RPR; /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */ - RwReg PWM_RCR; /**< \brief (Pwm Offset: 0x104) Receive Counter Register */ - RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */ - RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */ - RwReg PWM_RNPR; /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */ - RwReg PWM_RNCR; /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */ - RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */ - RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */ - WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */ - RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */ - RwReg Reserved5[2]; - RwReg PWM_CMP0V; /**< \brief (Pwm Offset: 0x130) PWM Comparison 0 Value Register */ - WoReg PWM_CMP0VUPD; /**< \brief (Pwm Offset: 0x134) PWM Comparison 0 Value Update Register */ - RwReg PWM_CMP0M; /**< \brief (Pwm Offset: 0x138) PWM Comparison 0 Mode Register */ - WoReg PWM_CMP0MUPD; /**< \brief (Pwm Offset: 0x13C) PWM Comparison 0 Mode Update Register */ - RwReg PWM_CMP1V; /**< \brief (Pwm Offset: 0x140) PWM Comparison 1 Value Register */ - WoReg PWM_CMP1VUPD; /**< \brief (Pwm Offset: 0x144) PWM Comparison 1 Value Update Register */ - RwReg PWM_CMP1M; /**< \brief (Pwm Offset: 0x148) PWM Comparison 1 Mode Register */ - WoReg PWM_CMP1MUPD; /**< \brief (Pwm Offset: 0x14C) PWM Comparison 1 Mode Update Register */ - RwReg PWM_CMP2V; /**< \brief (Pwm Offset: 0x150) PWM Comparison 2 Value Register */ - WoReg PWM_CMP2VUPD; /**< \brief (Pwm Offset: 0x154) PWM Comparison 2 Value Update Register */ - RwReg PWM_CMP2M; /**< \brief (Pwm Offset: 0x158) PWM Comparison 2 Mode Register */ - WoReg PWM_CMP2MUPD; /**< \brief (Pwm Offset: 0x15C) PWM Comparison 2 Mode Update Register */ - RwReg PWM_CMP3V; /**< \brief (Pwm Offset: 0x160) PWM Comparison 3 Value Register */ - WoReg PWM_CMP3VUPD; /**< \brief (Pwm Offset: 0x164) PWM Comparison 3 Value Update Register */ - RwReg PWM_CMP3M; /**< \brief (Pwm Offset: 0x168) PWM Comparison 3 Mode Register */ - WoReg PWM_CMP3MUPD; /**< \brief (Pwm Offset: 0x16C) PWM Comparison 3 Mode Update Register */ - RwReg PWM_CMP4V; /**< \brief (Pwm Offset: 0x170) PWM Comparison 4 Value Register */ - WoReg PWM_CMP4VUPD; /**< \brief (Pwm Offset: 0x174) PWM Comparison 4 Value Update Register */ - RwReg PWM_CMP4M; /**< \brief (Pwm Offset: 0x178) PWM Comparison 4 Mode Register */ - WoReg PWM_CMP4MUPD; /**< \brief (Pwm Offset: 0x17C) PWM Comparison 4 Mode Update Register */ - RwReg PWM_CMP5V; /**< \brief (Pwm Offset: 0x180) PWM Comparison 5 Value Register */ - WoReg PWM_CMP5VUPD; /**< \brief (Pwm Offset: 0x184) PWM Comparison 5 Value Update Register */ - RwReg PWM_CMP5M; /**< \brief (Pwm Offset: 0x188) PWM Comparison 5 Mode Register */ - WoReg PWM_CMP5MUPD; /**< \brief (Pwm Offset: 0x18C) PWM Comparison 5 Mode Update Register */ - RwReg PWM_CMP6V; /**< \brief (Pwm Offset: 0x190) PWM Comparison 6 Value Register */ - WoReg PWM_CMP6VUPD; /**< \brief (Pwm Offset: 0x194) PWM Comparison 6 Value Update Register */ - RwReg PWM_CMP6M; /**< \brief (Pwm Offset: 0x198) PWM Comparison 6 Mode Register */ - WoReg PWM_CMP6MUPD; /**< \brief (Pwm Offset: 0x19C) PWM Comparison 6 Mode Update Register */ - RwReg PWM_CMP7V; /**< \brief (Pwm Offset: 0x1A0) PWM Comparison 7 Value Register */ - WoReg PWM_CMP7VUPD; /**< \brief (Pwm Offset: 0x1A4) PWM Comparison 7 Value Update Register */ - RwReg PWM_CMP7M; /**< \brief (Pwm Offset: 0x1A8) PWM Comparison 7 Mode Register */ - WoReg PWM_CMP7MUPD; /**< \brief (Pwm Offset: 0x1AC) PWM Comparison 7 Mode Update Register */ - RwReg Reserved6[20]; - PwmCh_num PWM_CH_NUM[4]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ -} Pwm; -#endif /* __ASSEMBLY__ */ -/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ -#define PWM_CLK_DIVA (0xff << 0) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREA (0xf << 8) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -#define PWM_CLK_DIVB (0xff << 16) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ -#define PWM_CLK_PREB (0xf << 24) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ -/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ -#define PWM_ENA_CHID0 (0x1 << 0) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID1 (0x1 << 1) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID2 (0x1 << 2) /**< \brief (PWM_ENA) Channel ID */ -#define PWM_ENA_CHID3 (0x1 << 3) /**< \brief (PWM_ENA) Channel ID */ -/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ -#define PWM_DIS_CHID0 (0x1 << 0) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID1 (0x1 << 1) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID2 (0x1 << 2) /**< \brief (PWM_DIS) Channel ID */ -#define PWM_DIS_CHID3 (0x1 << 3) /**< \brief (PWM_DIS) Channel ID */ -/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ -#define PWM_SR_CHID0 (0x1 << 0) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID1 (0x1 << 1) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID2 (0x1 << 2) /**< \brief (PWM_SR) Channel ID */ -#define PWM_SR_CHID3 (0x1 << 3) /**< \brief (PWM_SR) Channel ID */ -/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ -#define PWM_IER1_CHID0 (0x1 << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ -#define PWM_IER1_CHID1 (0x1 << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ -#define PWM_IER1_CHID2 (0x1 << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ -#define PWM_IER1_CHID3 (0x1 << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ -#define PWM_IER1_FCHID0 (0x1 << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ -#define PWM_IER1_FCHID1 (0x1 << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ -#define PWM_IER1_FCHID2 (0x1 << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ -#define PWM_IER1_FCHID3 (0x1 << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ -/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ -#define PWM_IDR1_CHID0 (0x1 << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ -#define PWM_IDR1_CHID1 (0x1 << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ -#define PWM_IDR1_CHID2 (0x1 << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ -#define PWM_IDR1_CHID3 (0x1 << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ -#define PWM_IDR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ -#define PWM_IDR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ -#define PWM_IDR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ -#define PWM_IDR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ -/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ -#define PWM_IMR1_CHID0 (0x1 << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ -#define PWM_IMR1_CHID1 (0x1 << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ -#define PWM_IMR1_CHID2 (0x1 << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ -#define PWM_IMR1_CHID3 (0x1 << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ -#define PWM_IMR1_FCHID0 (0x1 << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ -#define PWM_IMR1_FCHID1 (0x1 << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ -#define PWM_IMR1_FCHID2 (0x1 << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ -#define PWM_IMR1_FCHID3 (0x1 << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ -/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ -#define PWM_ISR1_CHID0 (0x1 << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ -#define PWM_ISR1_CHID1 (0x1 << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ -#define PWM_ISR1_CHID2 (0x1 << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ -#define PWM_ISR1_CHID3 (0x1 << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ -#define PWM_ISR1_FCHID0 (0x1 << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ -#define PWM_ISR1_FCHID1 (0x1 << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ -#define PWM_ISR1_FCHID2 (0x1 << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ -#define PWM_ISR1_FCHID3 (0x1 << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ -/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ -#define PWM_SCM_SYNC0 (0x1 << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ -#define PWM_SCM_SYNC1 (0x1 << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ -#define PWM_SCM_SYNC2 (0x1 << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ -#define PWM_SCM_SYNC3 (0x1 << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ -#define PWM_SCM_UPDM (0x3 << 16) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ -#define PWM_SCM_UPDM_MODE0 (0x0 << 16) // (PWMC) Manual write of data and manual trigger of the update -#define PWM_SCM_UPDM_MODE1 (0x1 << 16) // (PWMC) Manual write of data and automatic trigger of the update -#define PWM_SCM_UPDM_MODE2 (0x2 << 16) // (PWMC) Automatic write of data and automatic trigger of the update -#define PWM_SCM_PTRM (0x1 << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */ -#define PWM_SCM_PTRCS (0x7 << 21) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */ -/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ -#define PWM_SCUC_UPDULOCK (0x1 << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ -/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ -#define PWM_SCUP_UPR (0xf << 0) /**< \brief (PWM_SCUP) Update Period */ -#define PWM_SCUP_UPRCNT (0xf << 4) /**< \brief (PWM_SCUP) Update Period Counter */ -/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ -#define PWM_SCUPUPD_UPRUPD (0xf << 0) /**< \brief (PWM_SCUPUPD) Update Period Update */ -/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ -#define PWM_IER2_WRDY (0x1 << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ -#define PWM_IER2_ENDTX (0x1 << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */ -#define PWM_IER2_TXBUFE (0x1 << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */ -#define PWM_IER2_UNRE (0x1 << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ -#define PWM_IER2_CMPM0 (0x1 << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ -#define PWM_IER2_CMPM1 (0x1 << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ -#define PWM_IER2_CMPM2 (0x1 << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ -#define PWM_IER2_CMPM3 (0x1 << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ -#define PWM_IER2_CMPM4 (0x1 << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ -#define PWM_IER2_CMPM5 (0x1 << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ -#define PWM_IER2_CMPM6 (0x1 << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ -#define PWM_IER2_CMPM7 (0x1 << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ -#define PWM_IER2_CMPU0 (0x1 << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ -#define PWM_IER2_CMPU1 (0x1 << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ -#define PWM_IER2_CMPU2 (0x1 << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ -#define PWM_IER2_CMPU3 (0x1 << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ -#define PWM_IER2_CMPU4 (0x1 << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ -#define PWM_IER2_CMPU5 (0x1 << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ -#define PWM_IER2_CMPU6 (0x1 << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ -#define PWM_IER2_CMPU7 (0x1 << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ -/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ -#define PWM_IDR2_WRDY (0x1 << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ -#define PWM_IDR2_ENDTX (0x1 << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */ -#define PWM_IDR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */ -#define PWM_IDR2_UNRE (0x1 << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ -#define PWM_IDR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ -#define PWM_IDR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ -#define PWM_IDR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ -#define PWM_IDR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ -#define PWM_IDR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ -#define PWM_IDR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ -#define PWM_IDR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ -#define PWM_IDR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ -#define PWM_IDR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ -#define PWM_IDR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ -#define PWM_IDR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ -#define PWM_IDR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ -#define PWM_IDR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ -#define PWM_IDR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ -#define PWM_IDR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ -#define PWM_IDR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ -/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ -#define PWM_IMR2_WRDY (0x1 << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ -#define PWM_IMR2_ENDTX (0x1 << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */ -#define PWM_IMR2_TXBUFE (0x1 << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */ -#define PWM_IMR2_UNRE (0x1 << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ -#define PWM_IMR2_CMPM0 (0x1 << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ -#define PWM_IMR2_CMPM1 (0x1 << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ -#define PWM_IMR2_CMPM2 (0x1 << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ -#define PWM_IMR2_CMPM3 (0x1 << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ -#define PWM_IMR2_CMPM4 (0x1 << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ -#define PWM_IMR2_CMPM5 (0x1 << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ -#define PWM_IMR2_CMPM6 (0x1 << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ -#define PWM_IMR2_CMPM7 (0x1 << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ -#define PWM_IMR2_CMPU0 (0x1 << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ -#define PWM_IMR2_CMPU1 (0x1 << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ -#define PWM_IMR2_CMPU2 (0x1 << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ -#define PWM_IMR2_CMPU3 (0x1 << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ -#define PWM_IMR2_CMPU4 (0x1 << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ -#define PWM_IMR2_CMPU5 (0x1 << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ -#define PWM_IMR2_CMPU6 (0x1 << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ -#define PWM_IMR2_CMPU7 (0x1 << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ -/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ -#define PWM_ISR2_WRDY (0x1 << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ -#define PWM_ISR2_ENDTX (0x1 << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */ -#define PWM_ISR2_TXBUFE (0x1 << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */ -#define PWM_ISR2_UNRE (0x1 << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ -#define PWM_ISR2_CMPM0 (0x1 << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ -#define PWM_ISR2_CMPM1 (0x1 << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ -#define PWM_ISR2_CMPM2 (0x1 << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ -#define PWM_ISR2_CMPM3 (0x1 << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ -#define PWM_ISR2_CMPM4 (0x1 << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ -#define PWM_ISR2_CMPM5 (0x1 << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ -#define PWM_ISR2_CMPM6 (0x1 << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ -#define PWM_ISR2_CMPM7 (0x1 << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ -#define PWM_ISR2_CMPU0 (0x1 << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ -#define PWM_ISR2_CMPU1 (0x1 << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ -#define PWM_ISR2_CMPU2 (0x1 << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ -#define PWM_ISR2_CMPU3 (0x1 << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ -#define PWM_ISR2_CMPU4 (0x1 << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ -#define PWM_ISR2_CMPU5 (0x1 << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ -#define PWM_ISR2_CMPU6 (0x1 << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ -#define PWM_ISR2_CMPU7 (0x1 << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ -/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ -#define PWM_OOV_OOVH0 (0x1 << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ -#define PWM_OOV_OOVH1 (0x1 << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ -#define PWM_OOV_OOVH2 (0x1 << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ -#define PWM_OOV_OOVH3 (0x1 << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ -#define PWM_OOV_OOVL0 (0x1 << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ -#define PWM_OOV_OOVL1 (0x1 << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ -#define PWM_OOV_OOVL2 (0x1 << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ -#define PWM_OOV_OOVL3 (0x1 << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ -/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ -#define PWM_OS_OSH0 (0x1 << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ -#define PWM_OS_OSH1 (0x1 << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ -#define PWM_OS_OSH2 (0x1 << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ -#define PWM_OS_OSH3 (0x1 << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ -#define PWM_OS_OSL0 (0x1 << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ -#define PWM_OS_OSL1 (0x1 << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ -#define PWM_OS_OSL2 (0x1 << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ -#define PWM_OS_OSL3 (0x1 << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ -/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ -#define PWM_OSS_OSSH0 (0x1 << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSS_OSSH1 (0x1 << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSS_OSSH2 (0x1 << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSS_OSSH3 (0x1 << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSS_OSSL0 (0x1 << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSS_OSSL1 (0x1 << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSS_OSSL2 (0x1 << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSS_OSSL3 (0x1 << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ -#define PWM_OSC_OSCH0 (0x1 << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSC_OSCH1 (0x1 << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSC_OSCH2 (0x1 << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSC_OSCH3 (0x1 << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSC_OSCL0 (0x1 << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSC_OSCL1 (0x1 << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSC_OSCL2 (0x1 << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSC_OSCL3 (0x1 << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ -#define PWM_OSSUPD_OSSUPH0 (0x1 << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ -#define PWM_OSSUPD_OSSUPH1 (0x1 << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ -#define PWM_OSSUPD_OSSUPH2 (0x1 << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ -#define PWM_OSSUPD_OSSUPH3 (0x1 << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ -#define PWM_OSSUPD_OSSUPL0 (0x1 << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ -#define PWM_OSSUPD_OSSUPL1 (0x1 << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ -#define PWM_OSSUPD_OSSUPL2 (0x1 << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ -#define PWM_OSSUPD_OSSUPL3 (0x1 << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ -/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ -#define PWM_OSCUPD_OSCUPH0 (0x1 << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ -#define PWM_OSCUPD_OSCUPH1 (0x1 << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ -#define PWM_OSCUPD_OSCUPH2 (0x1 << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ -#define PWM_OSCUPD_OSCUPH3 (0x1 << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ -#define PWM_OSCUPD_OSCUPL0 (0x1 << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ -#define PWM_OSCUPD_OSCUPL1 (0x1 << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ -#define PWM_OSCUPD_OSCUPL2 (0x1 << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ -#define PWM_OSCUPD_OSCUPL3 (0x1 << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ -/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ -#define PWM_FMR_FPOL0 (0x1 << 0) /**< \brief (PWM_FMR) Fault 0 Polarity */ -#define PWM_FMR_FPOL1 (0x1 << 1) /**< \brief (PWM_FMR) Fault 1 Polarity */ -#define PWM_FMR_FPOL2 (0x1 << 2) /**< \brief (PWM_FMR) Fault 2 Polarity */ -#define PWM_FMR_FPOL3 (0x1 << 3) /**< \brief (PWM_FMR) Fault 3 Polarity */ -#define PWM_FMR_FMOD0 (0x1 << 8) /**< \brief (PWM_FMR) Fault 0 Activation Mode */ -#define PWM_FMR_FMOD1 (0x1 << 9) /**< \brief (PWM_FMR) Fault 1 Activation Mode */ -#define PWM_FMR_FMOD2 (0x1 << 10) /**< \brief (PWM_FMR) Fault 2 Activation Mode */ -#define PWM_FMR_FMOD3 (0x1 << 11) /**< \brief (PWM_FMR) Fault 3 Activation Mode */ -#define PWM_FMR_FFIL0 (0x1 << 16) /**< \brief (PWM_FMR) Fault 0 Filtering */ -#define PWM_FMR_FFIL1 (0x1 << 17) /**< \brief (PWM_FMR) Fault 1 Filtering */ -#define PWM_FMR_FFIL2 (0x1 << 18) /**< \brief (PWM_FMR) Fault 2 Filtering */ -#define PWM_FMR_FFIL3 (0x1 << 19) /**< \brief (PWM_FMR) Fault 3 Filtering */ -/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ -#define PWM_FSR_FIV0 (0x1 << 0) /**< \brief (PWM_FSR) Fault Input 0 Value */ -#define PWM_FSR_FIV1 (0x1 << 1) /**< \brief (PWM_FSR) Fault Input 1 Value */ -#define PWM_FSR_FIV2 (0x1 << 2) /**< \brief (PWM_FSR) Fault Input 2 Value */ -#define PWM_FSR_FIV3 (0x1 << 3) /**< \brief (PWM_FSR) Fault Input 3 Value */ -#define PWM_FSR_FS0 (0x1 << 8) /**< \brief (PWM_FSR) Fault 0 Status */ -#define PWM_FSR_FS1 (0x1 << 9) /**< \brief (PWM_FSR) Fault 1 Status */ -#define PWM_FSR_FS2 (0x1 << 10) /**< \brief (PWM_FSR) Fault 2 Status */ -#define PWM_FSR_FS3 (0x1 << 11) /**< \brief (PWM_FSR) Fault 3 Status */ -/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ -#define PWM_FCR_FCLR0 (0x1 << 0) /**< \brief (PWM_FCR) Fault 0 Clear */ -#define PWM_FCR_FCLR1 (0x1 << 1) /**< \brief (PWM_FCR) Fault 1 Clear */ -#define PWM_FCR_FCLR2 (0x1 << 2) /**< \brief (PWM_FCR) Fault 2 Clear */ -#define PWM_FCR_FCLR3 (0x1 << 3) /**< \brief (PWM_FCR) Fault 3 Clear */ -/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */ -#define PWM_FPV_FPVH0 (0x1 << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */ -#define PWM_FPV_FPVH1 (0x1 << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */ -#define PWM_FPV_FPVH2 (0x1 << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */ -#define PWM_FPV_FPVH3 (0x1 << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */ -#define PWM_FPV_FPVL0 (0x1 << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */ -#define PWM_FPV_FPVL1 (0x1 << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */ -#define PWM_FPV_FPVL2 (0x1 << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */ -#define PWM_FPV_FPVL3 (0x1 << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */ -/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ -#define PWM_FPE_FPE0 (0xff << 0) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 0 for channel x */ -#define PWM_FPE_FPE1 (0xff << 8) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 1 for channel x */ -#define PWM_FPE_FPE2 (0xff << 16) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 2 for channel x */ -#define PWM_FPE_FPE3 (0xff << 24) /**< \brief (PWM_FPE) Fault Protection Enable with Fault 3 for channel x */ -/* -------- PWM_ELxMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ -#define PWM_ELxMR_CSEL0 (0x1 << 0) /**< \brief (PWM_ELxMR[2]) Comparison 0 Selection */ -#define PWM_ELxMR_CSEL1 (0x1 << 1) /**< \brief (PWM_ELxMR[2]) Comparison 1 Selection */ -#define PWM_ELxMR_CSEL2 (0x1 << 2) /**< \brief (PWM_ELxMR[2]) Comparison 2 Selection */ -#define PWM_ELxMR_CSEL3 (0x1 << 3) /**< \brief (PWM_ELxMR[2]) Comparison 3 Selection */ -#define PWM_ELxMR_CSEL4 (0x1 << 4) /**< \brief (PWM_ELxMR[2]) Comparison 4 Selection */ -#define PWM_ELxMR_CSEL5 (0x1 << 5) /**< \brief (PWM_ELxMR[2]) Comparison 5 Selection */ -#define PWM_ELxMR_CSEL6 (0x1 << 6) /**< \brief (PWM_ELxMR[2]) Comparison 6 Selection */ -#define PWM_ELxMR_CSEL7 (0x1 << 7) /**< \brief (PWM_ELxMR[2]) Comparison 7 Selection */ -/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ -#define PWM_WPCR_WPCMD (0x3 << 0) /**< \brief (PWM_WPCR) Write Protect Command */ -#define PWM_WPCR_WPRG0 (0x1 << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ -#define PWM_WPCR_WPRG1 (0x1 << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ -#define PWM_WPCR_WPRG2 (0x1 << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ -#define PWM_WPCR_WPRG3 (0x1 << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ -#define PWM_WPCR_WPRG4 (0x1 << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ -#define PWM_WPCR_WPRG5 (0x1 << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ -#define PWM_WPCR_WPKEY (0xffffff << 8) /**< \brief (PWM_WPCR) Write Protect Key */ -/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ -#define PWM_WPSR_WPSWS0 (0x1 << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS1 (0x1 << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS2 (0x1 << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS3 (0x1 << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS4 (0x1 << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPSWS5 (0x1 << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ -#define PWM_WPSR_WPVS (0x1 << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ -#define PWM_WPSR_WPHWS0 (0x1 << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS1 (0x1 << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS2 (0x1 << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS3 (0x1 << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS4 (0x1 << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPHWS5 (0x1 << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ -#define PWM_WPSR_WPVSRC (0xffff << 16) /**< \brief (PWM_WPSR) Write Protect Violation Source */ -/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */ -#define PWM_RPR_RXPTR (0xffffffff << 0) /**< \brief (PWM_RPR) Receive Pointer Register */ -/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */ -#define PWM_RCR_RXCTR (0xffff << 0) /**< \brief (PWM_RCR) Receive Counter Register */ -/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */ -#define PWM_TPR_TXPTR (0xffffffff << 0) /**< \brief (PWM_TPR) Transmit Counter Register */ -/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */ -#define PWM_TCR_TXCTR (0xffff << 0) /**< \brief (PWM_TCR) Transmit Counter Register */ -/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */ -#define PWM_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (PWM_RNPR) Receive Next Pointer */ -/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */ -#define PWM_RNCR_RXNCTR (0xffff << 0) /**< \brief (PWM_RNCR) Receive Next Counter */ -/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */ -#define PWM_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (PWM_TNPR) Transmit Next Pointer */ -/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */ -#define PWM_TNCR_TXNCTR (0xffff << 0) /**< \brief (PWM_TNCR) Transmit Counter Next */ -/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */ -#define PWM_PTCR_RXTEN (0x1 << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */ -#define PWM_PTCR_RXTDIS (0x1 << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */ -#define PWM_PTCR_TXTEN (0x1 << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */ -#define PWM_PTCR_TXTDIS (0x1 << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */ -/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */ -#define PWM_PTSR_RXTEN (0x1 << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */ -#define PWM_PTSR_TXTEN (0x1 << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */ -/* -------- PWM_CMP0V : (PWM Offset: 0x130) PWM Comparison 0 Value Register -------- */ -#define PWM_CMP0V_CV (0xffffff << 0) /**< \brief (PWM_CMP0V) Comparison x Value */ -#define PWM_CMP0V_CVM (0x1 << 24) /**< \brief (PWM_CMP0V) Comparison x Value Mode */ -/* -------- PWM_CMP0VUPD : (PWM Offset: 0x134) PWM Comparison 0 Value Update Register -------- */ -#define PWM_CMP0VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP0VUPD) Comparison x Value Update */ -#define PWM_CMP0VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP0VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP0M : (PWM Offset: 0x138) PWM Comparison 0 Mode Register -------- */ -#define PWM_CMP0M_CEN (0x1 << 0) /**< \brief (PWM_CMP0M) Comparison x Enable */ -#define PWM_CMP0M_CTR (0xf << 4) /**< \brief (PWM_CMP0M) Comparison x Trigger */ -#define PWM_CMP0M_CPR (0xf << 8) /**< \brief (PWM_CMP0M) Comparison x Period */ -#define PWM_CMP0M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP0M) Comparison x Period Counter */ -#define PWM_CMP0M_CUPR (0xf << 16) /**< \brief (PWM_CMP0M) Comparison x Update Period */ -#define PWM_CMP0M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP0M) Comparison x Update Period Counter */ -/* -------- PWM_CMP0MUPD : (PWM Offset: 0x13C) PWM Comparison 0 Mode Update Register -------- */ -#define PWM_CMP0MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP0MUPD) Comparison x Enable Update */ -#define PWM_CMP0MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP0MUPD) Comparison x Trigger Update */ -#define PWM_CMP0MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP0MUPD) Comparison x Period Update */ -#define PWM_CMP0MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP0MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP1V : (PWM Offset: 0x140) PWM Comparison 1 Value Register -------- */ -#define PWM_CMP1V_CV (0xffffff << 0) /**< \brief (PWM_CMP1V) Comparison x Value */ -#define PWM_CMP1V_CVM (0x1 << 24) /**< \brief (PWM_CMP1V) Comparison x Value Mode */ -/* -------- PWM_CMP1VUPD : (PWM Offset: 0x144) PWM Comparison 1 Value Update Register -------- */ -#define PWM_CMP1VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP1VUPD) Comparison x Value Update */ -#define PWM_CMP1VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP1VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP1M : (PWM Offset: 0x148) PWM Comparison 1 Mode Register -------- */ -#define PWM_CMP1M_CEN (0x1 << 0) /**< \brief (PWM_CMP1M) Comparison x Enable */ -#define PWM_CMP1M_CTR (0xf << 4) /**< \brief (PWM_CMP1M) Comparison x Trigger */ -#define PWM_CMP1M_CPR (0xf << 8) /**< \brief (PWM_CMP1M) Comparison x Period */ -#define PWM_CMP1M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP1M) Comparison x Period Counter */ -#define PWM_CMP1M_CUPR (0xf << 16) /**< \brief (PWM_CMP1M) Comparison x Update Period */ -#define PWM_CMP1M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP1M) Comparison x Update Period Counter */ -/* -------- PWM_CMP1MUPD : (PWM Offset: 0x14C) PWM Comparison 1 Mode Update Register -------- */ -#define PWM_CMP1MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP1MUPD) Comparison x Enable Update */ -#define PWM_CMP1MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP1MUPD) Comparison x Trigger Update */ -#define PWM_CMP1MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP1MUPD) Comparison x Period Update */ -#define PWM_CMP1MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP1MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP2V : (PWM Offset: 0x150) PWM Comparison 2 Value Register -------- */ -#define PWM_CMP2V_CV (0xffffff << 0) /**< \brief (PWM_CMP2V) Comparison x Value */ -#define PWM_CMP2V_CVM (0x1 << 24) /**< \brief (PWM_CMP2V) Comparison x Value Mode */ -/* -------- PWM_CMP2VUPD : (PWM Offset: 0x154) PWM Comparison 2 Value Update Register -------- */ -#define PWM_CMP2VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP2VUPD) Comparison x Value Update */ -#define PWM_CMP2VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP2VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP2M : (PWM Offset: 0x158) PWM Comparison 2 Mode Register -------- */ -#define PWM_CMP2M_CEN (0x1 << 0) /**< \brief (PWM_CMP2M) Comparison x Enable */ -#define PWM_CMP2M_CTR (0xf << 4) /**< \brief (PWM_CMP2M) Comparison x Trigger */ -#define PWM_CMP2M_CPR (0xf << 8) /**< \brief (PWM_CMP2M) Comparison x Period */ -#define PWM_CMP2M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP2M) Comparison x Period Counter */ -#define PWM_CMP2M_CUPR (0xf << 16) /**< \brief (PWM_CMP2M) Comparison x Update Period */ -#define PWM_CMP2M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP2M) Comparison x Update Period Counter */ -/* -------- PWM_CMP2MUPD : (PWM Offset: 0x15C) PWM Comparison 2 Mode Update Register -------- */ -#define PWM_CMP2MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP2MUPD) Comparison x Enable Update */ -#define PWM_CMP2MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP2MUPD) Comparison x Trigger Update */ -#define PWM_CMP2MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP2MUPD) Comparison x Period Update */ -#define PWM_CMP2MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP2MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP3V : (PWM Offset: 0x160) PWM Comparison 3 Value Register -------- */ -#define PWM_CMP3V_CV (0xffffff << 0) /**< \brief (PWM_CMP3V) Comparison x Value */ -#define PWM_CMP3V_CVM (0x1 << 24) /**< \brief (PWM_CMP3V) Comparison x Value Mode */ -/* -------- PWM_CMP3VUPD : (PWM Offset: 0x164) PWM Comparison 3 Value Update Register -------- */ -#define PWM_CMP3VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP3VUPD) Comparison x Value Update */ -#define PWM_CMP3VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP3VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP3M : (PWM Offset: 0x168) PWM Comparison 3 Mode Register -------- */ -#define PWM_CMP3M_CEN (0x1 << 0) /**< \brief (PWM_CMP3M) Comparison x Enable */ -#define PWM_CMP3M_CTR (0xf << 4) /**< \brief (PWM_CMP3M) Comparison x Trigger */ -#define PWM_CMP3M_CPR (0xf << 8) /**< \brief (PWM_CMP3M) Comparison x Period */ -#define PWM_CMP3M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP3M) Comparison x Period Counter */ -#define PWM_CMP3M_CUPR (0xf << 16) /**< \brief (PWM_CMP3M) Comparison x Update Period */ -#define PWM_CMP3M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP3M) Comparison x Update Period Counter */ -/* -------- PWM_CMP3MUPD : (PWM Offset: 0x16C) PWM Comparison 3 Mode Update Register -------- */ -#define PWM_CMP3MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP3MUPD) Comparison x Enable Update */ -#define PWM_CMP3MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP3MUPD) Comparison x Trigger Update */ -#define PWM_CMP3MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP3MUPD) Comparison x Period Update */ -#define PWM_CMP3MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP3MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP4V : (PWM Offset: 0x170) PWM Comparison 4 Value Register -------- */ -#define PWM_CMP4V_CV (0xffffff << 0) /**< \brief (PWM_CMP4V) Comparison x Value */ -#define PWM_CMP4V_CVM (0x1 << 24) /**< \brief (PWM_CMP4V) Comparison x Value Mode */ -/* -------- PWM_CMP4VUPD : (PWM Offset: 0x174) PWM Comparison 4 Value Update Register -------- */ -#define PWM_CMP4VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP4VUPD) Comparison x Value Update */ -#define PWM_CMP4VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP4VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP4M : (PWM Offset: 0x178) PWM Comparison 4 Mode Register -------- */ -#define PWM_CMP4M_CEN (0x1 << 0) /**< \brief (PWM_CMP4M) Comparison x Enable */ -#define PWM_CMP4M_CTR (0xf << 4) /**< \brief (PWM_CMP4M) Comparison x Trigger */ -#define PWM_CMP4M_CPR (0xf << 8) /**< \brief (PWM_CMP4M) Comparison x Period */ -#define PWM_CMP4M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP4M) Comparison x Period Counter */ -#define PWM_CMP4M_CUPR (0xf << 16) /**< \brief (PWM_CMP4M) Comparison x Update Period */ -#define PWM_CMP4M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP4M) Comparison x Update Period Counter */ -/* -------- PWM_CMP4MUPD : (PWM Offset: 0x17C) PWM Comparison 4 Mode Update Register -------- */ -#define PWM_CMP4MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP4MUPD) Comparison x Enable Update */ -#define PWM_CMP4MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP4MUPD) Comparison x Trigger Update */ -#define PWM_CMP4MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP4MUPD) Comparison x Period Update */ -#define PWM_CMP4MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP4MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP5V : (PWM Offset: 0x180) PWM Comparison 5 Value Register -------- */ -#define PWM_CMP5V_CV (0xffffff << 0) /**< \brief (PWM_CMP5V) Comparison x Value */ -#define PWM_CMP5V_CVM (0x1 << 24) /**< \brief (PWM_CMP5V) Comparison x Value Mode */ -/* -------- PWM_CMP5VUPD : (PWM Offset: 0x184) PWM Comparison 5 Value Update Register -------- */ -#define PWM_CMP5VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP5VUPD) Comparison x Value Update */ -#define PWM_CMP5VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP5VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP5M : (PWM Offset: 0x188) PWM Comparison 5 Mode Register -------- */ -#define PWM_CMP5M_CEN (0x1 << 0) /**< \brief (PWM_CMP5M) Comparison x Enable */ -#define PWM_CMP5M_CTR (0xf << 4) /**< \brief (PWM_CMP5M) Comparison x Trigger */ -#define PWM_CMP5M_CPR (0xf << 8) /**< \brief (PWM_CMP5M) Comparison x Period */ -#define PWM_CMP5M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP5M) Comparison x Period Counter */ -#define PWM_CMP5M_CUPR (0xf << 16) /**< \brief (PWM_CMP5M) Comparison x Update Period */ -#define PWM_CMP5M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP5M) Comparison x Update Period Counter */ -/* -------- PWM_CMP5MUPD : (PWM Offset: 0x18C) PWM Comparison 5 Mode Update Register -------- */ -#define PWM_CMP5MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP5MUPD) Comparison x Enable Update */ -#define PWM_CMP5MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP5MUPD) Comparison x Trigger Update */ -#define PWM_CMP5MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP5MUPD) Comparison x Period Update */ -#define PWM_CMP5MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP5MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP6V : (PWM Offset: 0x190) PWM Comparison 6 Value Register -------- */ -#define PWM_CMP6V_CV (0xffffff << 0) /**< \brief (PWM_CMP6V) Comparison x Value */ -#define PWM_CMP6V_CVM (0x1 << 24) /**< \brief (PWM_CMP6V) Comparison x Value Mode */ -/* -------- PWM_CMP6VUPD : (PWM Offset: 0x194) PWM Comparison 6 Value Update Register -------- */ -#define PWM_CMP6VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP6VUPD) Comparison x Value Update */ -#define PWM_CMP6VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP6VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP6M : (PWM Offset: 0x198) PWM Comparison 6 Mode Register -------- */ -#define PWM_CMP6M_CEN (0x1 << 0) /**< \brief (PWM_CMP6M) Comparison x Enable */ -#define PWM_CMP6M_CTR (0xf << 4) /**< \brief (PWM_CMP6M) Comparison x Trigger */ -#define PWM_CMP6M_CPR (0xf << 8) /**< \brief (PWM_CMP6M) Comparison x Period */ -#define PWM_CMP6M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP6M) Comparison x Period Counter */ -#define PWM_CMP6M_CUPR (0xf << 16) /**< \brief (PWM_CMP6M) Comparison x Update Period */ -#define PWM_CMP6M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP6M) Comparison x Update Period Counter */ -/* -------- PWM_CMP6MUPD : (PWM Offset: 0x19C) PWM Comparison 6 Mode Update Register -------- */ -#define PWM_CMP6MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP6MUPD) Comparison x Enable Update */ -#define PWM_CMP6MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP6MUPD) Comparison x Trigger Update */ -#define PWM_CMP6MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP6MUPD) Comparison x Period Update */ -#define PWM_CMP6MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP6MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMP7V : (PWM Offset: 0x1A0) PWM Comparison 7 Value Register -------- */ -#define PWM_CMP7V_CV (0xffffff << 0) /**< \brief (PWM_CMP7V) Comparison x Value */ -#define PWM_CMP7V_CVM (0x1 << 24) /**< \brief (PWM_CMP7V) Comparison x Value Mode */ -/* -------- PWM_CMP7VUPD : (PWM Offset: 0x1A4) PWM Comparison 7 Value Update Register -------- */ -#define PWM_CMP7VUPD_CVUPD (0xffffff << 0) /**< \brief (PWM_CMP7VUPD) Comparison x Value Update */ -#define PWM_CMP7VUPD_CVMUPD (0x1 << 24) /**< \brief (PWM_CMP7VUPD) Comparison x Value Mode Update */ -/* -------- PWM_CMP7M : (PWM Offset: 0x1A8) PWM Comparison 7 Mode Register -------- */ -#define PWM_CMP7M_CEN (0x1 << 0) /**< \brief (PWM_CMP7M) Comparison x Enable */ -#define PWM_CMP7M_CTR (0xf << 4) /**< \brief (PWM_CMP7M) Comparison x Trigger */ -#define PWM_CMP7M_CPR (0xf << 8) /**< \brief (PWM_CMP7M) Comparison x Period */ -#define PWM_CMP7M_CPRCNT (0xf << 12) /**< \brief (PWM_CMP7M) Comparison x Period Counter */ -#define PWM_CMP7M_CUPR (0xf << 16) /**< \brief (PWM_CMP7M) Comparison x Update Period */ -#define PWM_CMP7M_CUPRCNT (0xf << 20) /**< \brief (PWM_CMP7M) Comparison x Update Period Counter */ -/* -------- PWM_CMP7MUPD : (PWM Offset: 0x1AC) PWM Comparison 7 Mode Update Register -------- */ -#define PWM_CMP7MUPD_CENUPD (0x1 << 0) /**< \brief (PWM_CMP7MUPD) Comparison x Enable Update */ -#define PWM_CMP7MUPD_CTRUPD (0xf << 4) /**< \brief (PWM_CMP7MUPD) Comparison x Trigger Update */ -#define PWM_CMP7MUPD_CPRUPD (0xf << 8) /**< \brief (PWM_CMP7MUPD) Comparison x Period Update */ -#define PWM_CMP7MUPD_CUPRUPD (0xf << 16) /**< \brief (PWM_CMP7MUPD) Comparison x Update Period Update */ -/* -------- PWM_CMR0 : (PWM Offset: 0x200) PWM Channel Mode Register (ch_num = 0) -------- */ -#define PWM_CMR0_CPRE (0xf << 0) /**< \brief (PWM_CMR0) Channel Pre-scaler */ -#define PWM_CMR0_CPRE_MCK_DIV_2 (0x1) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_4 (0x2) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_8 (0x3) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_16 (0x4) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_32 (0x5) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_64 (0x6) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_128 (0x7) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_256 (0x8) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_512 (0x9) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCK_DIV_1024 (0xA) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCKA (0xB) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCKB (0xC) // (PWMC_CH) -#define PWM_CMR0_CALG (0x1 << 8) /**< \brief (PWM_CMR0) Channel Alignment */ -#define PWM_CMR0_CPOL (0x1 << 9) /**< \brief (PWM_CMR0) Channel Polarity */ -#define PWM_CMR0_CES (0x1 << 10) /**< \brief (PWM_CMR0) Counter Event Selection */ -#define PWM_CMR0_DTE (0x1 << 16) /**< \brief (PWM_CMR0) Dead-Time Generator Enable */ -#define PWM_CMR0_DTHI (0x1 << 17) /**< \brief (PWM_CMR0) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR0_DTLI (0x1 << 18) /**< \brief (PWM_CMR0) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY0 : (PWM Offset: 0x204) PWM Channel Duty Cycle Register (ch_num = 0) -------- */ -#define PWM_CDTY0_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY0) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD0 : (PWM Offset: 0x208) PWM Channel Duty Cycle Update Register (ch_num = 0) -------- */ -#define PWM_CDTYUPD0_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD0) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD0 : (PWM Offset: 0x20C) PWM Channel Period Register (ch_num = 0) -------- */ -#define PWM_CPRD0_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD0) Channel Period */ -/* -------- PWM_CPRDUPD0 : (PWM Offset: 0x210) PWM Channel Period Update Register (ch_num = 0) -------- */ -#define PWM_CPRDUPD0_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD0) Channel Period Update */ -/* -------- PWM_CCNT0 : (PWM Offset: 0x214) PWM Channel Counter Register (ch_num = 0) -------- */ -#define PWM_CCNT0_CNT (0xffffff << 0) /**< \brief (PWM_CCNT0) Channel Counter Register */ -/* -------- PWM_DT0 : (PWM Offset: 0x218) PWM Channel Dead Time Register (ch_num = 0) -------- */ -#define PWM_DT0_DTH (0xffff << 0) /**< \brief (PWM_DT0) Dead-Time Value for PWMHx Output */ -#define PWM_DT0_DTL (0xffff << 16) /**< \brief (PWM_DT0) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD0 : (PWM Offset: 0x21C) PWM Channel Dead Time Update Register (ch_num = 0) -------- */ -#define PWM_DTUPD0_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD0_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD0) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR1 : (PWM Offset: 0x220) PWM Channel Mode Register (ch_num = 1) -------- */ -#define PWM_CMR1_CPRE (0xf << 0) /**< \brief (PWM_CMR1) Channel Pre-scaler */ -#define PWM_CMR1_CPRE_MCK_DIV_2 (0x1) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_4 (0x2) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_8 (0x3) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_16 (0x4) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_32 (0x5) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_64 (0x6) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_128 (0x7) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_256 (0x8) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_512 (0x9) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCK_DIV_1024 (0xA) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCKA (0xB) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCKB (0xC) // (PWMC_CH) -#define PWM_CMR1_CALG (0x1 << 8) /**< \brief (PWM_CMR1) Channel Alignment */ -#define PWM_CMR1_CPOL (0x1 << 9) /**< \brief (PWM_CMR1) Channel Polarity */ -#define PWM_CMR1_CES (0x1 << 10) /**< \brief (PWM_CMR1) Counter Event Selection */ -#define PWM_CMR1_DTE (0x1 << 16) /**< \brief (PWM_CMR1) Dead-Time Generator Enable */ -#define PWM_CMR1_DTHI (0x1 << 17) /**< \brief (PWM_CMR1) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR1_DTLI (0x1 << 18) /**< \brief (PWM_CMR1) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY1 : (PWM Offset: 0x224) PWM Channel Duty Cycle Register (ch_num = 1) -------- */ -#define PWM_CDTY1_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY1) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD1 : (PWM Offset: 0x228) PWM Channel Duty Cycle Update Register (ch_num = 1) -------- */ -#define PWM_CDTYUPD1_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD1) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD1 : (PWM Offset: 0x22C) PWM Channel Period Register (ch_num = 1) -------- */ -#define PWM_CPRD1_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD1) Channel Period */ -/* -------- PWM_CPRDUPD1 : (PWM Offset: 0x230) PWM Channel Period Update Register (ch_num = 1) -------- */ -#define PWM_CPRDUPD1_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD1) Channel Period Update */ -/* -------- PWM_CCNT1 : (PWM Offset: 0x234) PWM Channel Counter Register (ch_num = 1) -------- */ -#define PWM_CCNT1_CNT (0xffffff << 0) /**< \brief (PWM_CCNT1) Channel Counter Register */ -/* -------- PWM_DT1 : (PWM Offset: 0x238) PWM Channel Dead Time Register (ch_num = 1) -------- */ -#define PWM_DT1_DTH (0xffff << 0) /**< \brief (PWM_DT1) Dead-Time Value for PWMHx Output */ -#define PWM_DT1_DTL (0xffff << 16) /**< \brief (PWM_DT1) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD1 : (PWM Offset: 0x23C) PWM Channel Dead Time Update Register (ch_num = 1) -------- */ -#define PWM_DTUPD1_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD1_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD1) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR2 : (PWM Offset: 0x240) PWM Channel Mode Register (ch_num = 2) -------- */ -#define PWM_CMR2_CPRE (0xf << 0) /**< \brief (PWM_CMR2) Channel Pre-scaler */ -#define PWM_CMR2_CPRE_MCK_DIV_2 (0x1) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_4 (0x2) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_8 (0x3) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_16 (0x4) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_32 (0x5) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_64 (0x6) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_128 (0x7) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_256 (0x8) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_512 (0x9) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCK_DIV_1024 (0xA) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCKA (0xB) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCKB (0xC) // (PWMC_CH) -#define PWM_CMR2_CALG (0x1 << 8) /**< \brief (PWM_CMR2) Channel Alignment */ -#define PWM_CMR2_CPOL (0x1 << 9) /**< \brief (PWM_CMR2) Channel Polarity */ -#define PWM_CMR2_CES (0x1 << 10) /**< \brief (PWM_CMR2) Counter Event Selection */ -#define PWM_CMR2_DTE (0x1 << 16) /**< \brief (PWM_CMR2) Dead-Time Generator Enable */ -#define PWM_CMR2_DTHI (0x1 << 17) /**< \brief (PWM_CMR2) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR2_DTLI (0x1 << 18) /**< \brief (PWM_CMR2) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY2 : (PWM Offset: 0x244) PWM Channel Duty Cycle Register (ch_num = 2) -------- */ -#define PWM_CDTY2_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY2) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD2 : (PWM Offset: 0x248) PWM Channel Duty Cycle Update Register (ch_num = 2) -------- */ -#define PWM_CDTYUPD2_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD2) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD2 : (PWM Offset: 0x24C) PWM Channel Period Register (ch_num = 2) -------- */ -#define PWM_CPRD2_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD2) Channel Period */ -/* -------- PWM_CPRDUPD2 : (PWM Offset: 0x250) PWM Channel Period Update Register (ch_num = 2) -------- */ -#define PWM_CPRDUPD2_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD2) Channel Period Update */ -/* -------- PWM_CCNT2 : (PWM Offset: 0x254) PWM Channel Counter Register (ch_num = 2) -------- */ -#define PWM_CCNT2_CNT (0xffffff << 0) /**< \brief (PWM_CCNT2) Channel Counter Register */ -/* -------- PWM_DT2 : (PWM Offset: 0x258) PWM Channel Dead Time Register (ch_num = 2) -------- */ -#define PWM_DT2_DTH (0xffff << 0) /**< \brief (PWM_DT2) Dead-Time Value for PWMHx Output */ -#define PWM_DT2_DTL (0xffff << 16) /**< \brief (PWM_DT2) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD2 : (PWM Offset: 0x25C) PWM Channel Dead Time Update Register (ch_num = 2) -------- */ -#define PWM_DTUPD2_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD2_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD2) Dead-Time Value Update for PWMLx Output */ -/* -------- PWM_CMR3 : (PWM Offset: 0x260) PWM Channel Mode Register (ch_num = 3) -------- */ -#define PWM_CMR3_CPRE (0xf << 0) /**< \brief (PWM_CMR3) Channel Pre-scaler */ -#define PWM_CMR3_CPRE_MCK_DIV_2 (0x1) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_4 (0x2) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_8 (0x3) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_16 (0x4) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_32 (0x5) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_64 (0x6) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_128 (0x7) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_256 (0x8) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_512 (0x9) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCK_DIV_1024 (0xA) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCKA (0xB) // (PWMC_CH) -#define PWM_CMR3_CPRE_MCKB (0xC) // (PWMC_CH) -#define PWM_CMR3_CALG (0x1 << 8) /**< \brief (PWM_CMR3) Channel Alignment */ -#define PWM_CMR3_CPOL (0x1 << 9) /**< \brief (PWM_CMR3) Channel Polarity */ -#define PWM_CMR3_CES (0x1 << 10) /**< \brief (PWM_CMR3) Counter Event Selection */ -#define PWM_CMR3_DTE (0x1 << 16) /**< \brief (PWM_CMR3) Dead-Time Generator Enable */ -#define PWM_CMR3_DTHI (0x1 << 17) /**< \brief (PWM_CMR3) Dead-Time PWMHx Output Inverted */ -#define PWM_CMR3_DTLI (0x1 << 18) /**< \brief (PWM_CMR3) Dead-Time PWMLx Output Inverted */ -/* -------- PWM_CDTY3 : (PWM Offset: 0x264) PWM Channel Duty Cycle Register (ch_num = 3) -------- */ -#define PWM_CDTY3_CDTY (0xffffff << 0) /**< \brief (PWM_CDTY3) Channel Duty-Cycle */ -/* -------- PWM_CDTYUPD3 : (PWM Offset: 0x268) PWM Channel Duty Cycle Update Register (ch_num = 3) -------- */ -#define PWM_CDTYUPD3_CDTYUPD (0xffffff << 0) /**< \brief (PWM_CDTYUPD3) Channel Duty-Cycle Update */ -/* -------- PWM_CPRD3 : (PWM Offset: 0x26C) PWM Channel Period Register (ch_num = 3) -------- */ -#define PWM_CPRD3_CPRD (0xffffff << 0) /**< \brief (PWM_CPRD3) Channel Period */ -/* -------- PWM_CPRDUPD3 : (PWM Offset: 0x270) PWM Channel Period Update Register (ch_num = 3) -------- */ -#define PWM_CPRDUPD3_CPRDUPD (0xffffff << 0) /**< \brief (PWM_CPRDUPD3) Channel Period Update */ -/* -------- PWM_CCNT3 : (PWM Offset: 0x274) PWM Channel Counter Register (ch_num = 3) -------- */ -#define PWM_CCNT3_CNT (0xffffff << 0) /**< \brief (PWM_CCNT3) Channel Counter Register */ -/* -------- PWM_DT3 : (PWM Offset: 0x278) PWM Channel Dead Time Register (ch_num = 3) -------- */ -#define PWM_DT3_DTH (0xffff << 0) /**< \brief (PWM_DT3) Dead-Time Value for PWMHx Output */ -#define PWM_DT3_DTL (0xffff << 16) /**< \brief (PWM_DT3) Dead-Time Value for PWMLx Output */ -/* -------- PWM_DTUPD3 : (PWM Offset: 0x27C) PWM Channel Dead Time Update Register (ch_num = 3) -------- */ -#define PWM_DTUPD3_DTHUPD (0xffff << 0) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMHx Output */ -#define PWM_DTUPD3_DTLUPD (0xffff << 16) /**< \brief (PWM_DTUPD3) Dead-Time Value Update for PWMLx Output */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Reset Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_RSTC Reset Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rstc hardware registers */ -typedef struct { - WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ - RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ - RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ -} Rstc; -#endif /* __ASSEMBLY__ */ -/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ -#define RSTC_CR_PROCRST (0x1 << 0) /**< \brief (RSTC_CR) Processor Reset */ -#define RSTC_CR_PERRST (0x1 << 2) /**< \brief (RSTC_CR) Peripheral Reset */ -#define RSTC_CR_EXTRST (0x1 << 3) /**< \brief (RSTC_CR) External Reset */ -#define RSTC_CR_KEY (0xff << 24) /**< \brief (RSTC_CR) Password */ -/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ -#define RSTC_SR_URSTS (0x1 << 0) /**< \brief (RSTC_SR) User Reset Status */ -#define RSTC_SR_RSTTYP (0x7 << 8) /**< \brief (RSTC_SR) Reset Type */ -#define RSTC_SR_NRSTL (0x1 << 16) /**< \brief (RSTC_SR) NRST Pin Level */ -#define RSTC_SR_SRCMP (0x1 << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ -/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ -#define RSTC_MR_URSTEN (0x1 << 0) /**< \brief (RSTC_MR) User Reset Enable */ -#define RSTC_MR_URSTIEN (0x1 << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ -#define RSTC_MR_ERSTL (0xf << 8) /**< \brief (RSTC_MR) External Reset Length */ -#define RSTC_MR_KEY (0xff << 24) /**< \brief (RSTC_MR) Password */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Clock */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_RTC Real-time Clock */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtc hardware registers */ -typedef struct { - RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ - RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ - RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ - RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ - RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ - RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ - RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ - WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ - WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ - WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ - RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ - RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ -} Rtc; -#endif /* __ASSEMBLY__ */ -/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ -#define RTC_CR_UPDTIM (0x1 << 0) /**< \brief (RTC_CR) Update Request Time Register */ -#define RTC_CR_UPDCAL (0x1 << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ -#define RTC_CR_TIMEVSEL (0x3 << 8) /**< \brief (RTC_CR) Time Event Selection */ -#define RTC_CR_TIMEVSEL_MINUTE (0x0 << 8) /**< \brief (RTC_CR) Minute change. */ -#define RTC_CR_TIMEVSEL_HOUR (0x1 << 8) /**< \brief (RTC_CR) Hour change. */ -#define RTC_CR_TIMEVSEL_DAY24 (0x2 << 8) /**< \brief (RTC_CR) Every day at midnight. */ -#define RTC_CR_TIMEVSEL_DAY12 (0x3 << 8) /**< \brief (RTC_CR) Every day at noon. */ -#define RTC_CR_CALEVSEL (0x3 << 16) /**< \brief (RTC_CR) Calendar Event Selection */ -#define RTC_CR_CALEVSEL_WEEK (0x0 << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00). */ -#define RTC_CR_CALEVSEL_MONTH (0x1 << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00). */ -/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ -#define RTC_MR_HRMOD (0x1 << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ -/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ -#define RTC_TIMR_SEC (0x7f << 0) /**< \brief (RTC_TIMR) Current Second */ -#define RTC_TIMR_MIN (0x7f << 8) /**< \brief (RTC_TIMR) Current Minute */ -#define RTC_TIMR_HOUR (0x3f << 16) /**< \brief (RTC_TIMR) Current Hour */ -#define RTC_TIMR_AMPM (0x1 << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ -/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ -#define RTC_CALR_CENT (0x7f << 0) /**< \brief (RTC_CALR) Current Century */ -#define RTC_CALR_YEAR (0xff << 8) /**< \brief (RTC_CALR) Current Year */ -#define RTC_CALR_MONTH (0x1f << 16) /**< \brief (RTC_CALR) Current Month */ -#define RTC_CALR_DAY (0x7 << 21) /**< \brief (RTC_CALR) Current Day in Current Week */ -#define RTC_CALR_DATE (0x3f << 24) /**< \brief (RTC_CALR) Current Day in Current Month */ -/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ -#define RTC_TIMALR_SEC (0x7f << 0) /**< \brief (RTC_TIMALR) Second Alarm */ -#define RTC_TIMALR_SECEN (0x1 << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ -#define RTC_TIMALR_MIN (0x7f << 8) /**< \brief (RTC_TIMALR) Minute Alarm */ -#define RTC_TIMALR_MINEN (0x1 << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ -#define RTC_TIMALR_HOUR (0x3f << 16) /**< \brief (RTC_TIMALR) Hour Alarm */ -#define RTC_TIMALR_AMPM (0x1 << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ -#define RTC_TIMALR_HOUREN (0x1 << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ -/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ -#define RTC_CALALR_MONTH (0x1f << 16) /**< \brief (RTC_CALALR) Month Alarm */ -#define RTC_CALALR_MTHEN (0x1 << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ -#define RTC_CALALR_DATE (0x3f << 24) /**< \brief (RTC_CALALR) Date Alarm */ -#define RTC_CALALR_DATEEN (0x1 << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ -/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ -#define RTC_SR_ACKUPD (0x1 << 0) /**< \brief (RTC_SR) Acknowledge for Update */ -#define RTC_SR_ALARM (0x1 << 1) /**< \brief (RTC_SR) Alarm Flag */ -#define RTC_SR_SEC (0x1 << 2) /**< \brief (RTC_SR) Second Event */ -#define RTC_SR_TIMEV (0x1 << 3) /**< \brief (RTC_SR) Time Event */ -#define RTC_SR_CALEV (0x1 << 4) /**< \brief (RTC_SR) Calendar Event */ -/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ -#define RTC_SCCR_ACKCLR (0x1 << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ -#define RTC_SCCR_ALRCLR (0x1 << 1) /**< \brief (RTC_SCCR) Alarm Clear */ -#define RTC_SCCR_SECCLR (0x1 << 2) /**< \brief (RTC_SCCR) Second Clear */ -#define RTC_SCCR_TIMCLR (0x1 << 3) /**< \brief (RTC_SCCR) Time Clear */ -#define RTC_SCCR_CALCLR (0x1 << 4) /**< \brief (RTC_SCCR) Calendar Clear */ -/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ -#define RTC_IER_ACKEN (0x1 << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ -#define RTC_IER_ALREN (0x1 << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ -#define RTC_IER_SECEN (0x1 << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ -#define RTC_IER_TIMEN (0x1 << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ -#define RTC_IER_CALEN (0x1 << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ -/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ -#define RTC_IDR_ACKDIS (0x1 << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ -#define RTC_IDR_ALRDIS (0x1 << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ -#define RTC_IDR_SECDIS (0x1 << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ -#define RTC_IDR_TIMDIS (0x1 << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ -#define RTC_IDR_CALDIS (0x1 << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ -/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ -#define RTC_IMR_ACK (0x1 << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ -#define RTC_IMR_ALR (0x1 << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ -#define RTC_IMR_SEC (0x1 << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ -#define RTC_IMR_TIM (0x1 << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ -#define RTC_IMR_CAL (0x1 << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ -/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ -#define RTC_VER_NVTIM (0x1 << 0) /**< \brief (RTC_VER) Non-valid Time */ -#define RTC_VER_NVCAL (0x1 << 1) /**< \brief (RTC_VER) Non-valid Calendar */ -#define RTC_VER_NVTIMALR (0x1 << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ -#define RTC_VER_NVCALALR (0x1 << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Real-time Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_RTT Real-time Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Rtt hardware registers */ -typedef struct { - RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ - RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ - RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ - RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ -} Rtt; -#endif /* __ASSEMBLY__ */ -/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ -#define RTT_MR_RTPRES (0xffff << 0) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ -#define RTT_MR_ALMIEN (0x1 << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ -#define RTT_MR_RTTINCIEN (0x1 << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ -#define RTT_MR_RTTRST (0x1 << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ -/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ -#define RTT_AR_ALMV (0xffffffff << 0) /**< \brief (RTT_AR) Alarm Value */ -/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ -#define RTT_VR_CRTV (0xffffffff << 0) /**< \brief (RTT_VR) Current Real-time Value */ -/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ -#define RTT_SR_ALMS (0x1 << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ -#define RTT_SR_RTTINC (0x1 << 1) /**< \brief (RTT_SR) Real-time Timer Increment */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Static Memory Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_SMC Static Memory Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief SmcCs_number hardware registers */ -typedef struct { - RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC SETUP Register */ - RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC PULSE Register */ - RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC CYCLE Register */ - RwReg SMC_TIMINGS; /**< \brief (SmcCs_number Offset: 0xC) SMC TIMINGS Register */ - RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0x10) SMC MODE Register */ -} SmcCs_number; -/** \brief Smc hardware registers */ -typedef struct { - RwReg SMC_CFG; /**< \brief (Smc Offset: 0x000) SMC NFC Configuration Register */ - WoReg SMC_CTRL; /**< \brief (Smc Offset: 0x004) SMC NFC Control Register */ - RoReg SMC_SR; /**< \brief (Smc Offset: 0x008) SMC NFC Status Register */ - WoReg SMC_IER; /**< \brief (Smc Offset: 0x00C) SMC NFC Interrupt Enable Register */ - WoReg SMC_IDR; /**< \brief (Smc Offset: 0x010) SMC NFC Interrupt Disable Register */ - RoReg SMC_IMR; /**< \brief (Smc Offset: 0x014) SMC NFC Interrupt Mask Register */ - RwReg SMC_ADDR; /**< \brief (Smc Offset: 0x018) SMC NFC Address Cycle Zero Register */ - RwReg SMC_BANK; /**< \brief (Smc Offset: 0x01C) SMC Bank Address Register */ - WoReg SMC_ECC_CTRL; /**< \brief (Smc Offset: 0x020) SMC ECC Control Register */ - RwReg SMC_ECC_MD; /**< \brief (Smc Offset: 0x024) SMC ECC Mode Register */ - RoReg SMC_ECC_SR1; /**< \brief (Smc Offset: 0x028) SMC ECC Status 1 Register */ - RoReg SMC_ECC_PR0; /**< \brief (Smc Offset: 0x02C) SMC ECC Parity 0 Register */ - RoReg SMC_ECC_PR1; /**< \brief (Smc Offset: 0x030) SMC ECC parity 1 Register */ - RoReg SMC_ECC_SR2; /**< \brief (Smc Offset: 0x034) SMC ECC status 2 Register */ - RoReg SMC_ECC_PR2; /**< \brief (Smc Offset: 0x038) SMC ECC parity 2 Register */ - RoReg SMC_ECC_PR3; /**< \brief (Smc Offset: 0x03C) SMC ECC parity 3 Register */ - RoReg SMC_ECC_PR4; /**< \brief (Smc Offset: 0x040) SMC ECC parity 4 Register */ - RoReg SMC_ECC_PR5; /**< \brief (Smc Offset: 0x044) SMC ECC parity 5 Register */ - RoReg SMC_ECC_PR6; /**< \brief (Smc Offset: 0x048) SMC ECC parity 6 Register */ - RoReg SMC_ECC_PR7; /**< \brief (Smc Offset: 0x04C) SMC ECC parity 7 Register */ - RoReg SMC_ECC_PR8; /**< \brief (Smc Offset: 0x050) SMC ECC parity 8 Register */ - RoReg SMC_ECC_PR9; /**< \brief (Smc Offset: 0x054) SMC ECC parity 9 Register */ - RoReg SMC_ECC_PR10; /**< \brief (Smc Offset: 0x058) SMC ECC parity 10 Register */ - RoReg SMC_ECC_PR11; /**< \brief (Smc Offset: 0x05C) SMC ECC parity 11 Register */ - RoReg SMC_ECC_PR12; /**< \brief (Smc Offset: 0x060) SMC ECC parity 12 Register */ - RoReg SMC_ECC_PR13; /**< \brief (Smc Offset: 0x064) SMC ECC parity 13 Register */ - RoReg SMC_ECC_PR14; /**< \brief (Smc Offset: 0x068) SMC ECC parity 14 Register */ - RoReg SMC_ECC_PR15; /**< \brief (Smc Offset: 0x06C) SMC ECC parity 15 Register */ - SmcCs_number SMC_CS_NUMBER[4]; /**< \brief (Smc Offset: 0x70) CS_number = 0 .. 3 */ - RwReg Reserved1[20]; - RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x110) SMC OCMS MODE Register */ - WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x114) SMC KEY1 Register */ - WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x118) SMC KEY2 Register */ - RwReg Reserved2[50]; - WoReg SMC_WPCR; /**< \brief (Smc Offset: 0x1E4) Write Protection Control Register */ - RoReg SMC_WPSR; /**< \brief (Smc Offset: 0x1E8) Write Protection Status Register */ -} Smc; -#endif /* __ASSEMBLY__ */ -/* -------- SMC_CFG : (SMC Offset: 0x000) SMC NFC Configuration Register -------- */ -#define SMC_CFG_PAGESIZE (0x3 << 0) /**< \brief (SMC_CFG) */ -#define SMC_CFG_WSPARE (0x1 << 8) /**< \brief (SMC_CFG) Write Spare Area */ -#define SMC_CFG_RSPARE (0x1 << 9) /**< \brief (SMC_CFG) Read Spare Area */ -#define SMC_CFG_EDGECTRL (0x1 << 12) /**< \brief (SMC_CFG) Rising/Falling Edge Detection Control */ -#define SMC_CFG_RBEDGE (0x1 << 13) /**< \brief (SMC_CFG) Ready/Busy Signal Edge Detection */ -#define SMC_CFG_DTOCYC (0xf << 16) /**< \brief (SMC_CFG) Data Timeout Cycle Number */ -#define SMC_CFG_DTOMUL (0x7 << 20) /**< \brief (SMC_CFG) Data Timeout Multiplier */ -/* -------- SMC_CTRL : (SMC Offset: 0x004) SMC NFC Control Register -------- */ -#define SMC_CTRL_NFCEN (0x1 << 0) /**< \brief (SMC_CTRL) NAND Flash Controller Enable */ -#define SMC_CTRL_NFCDIS (0x1 << 1) /**< \brief (SMC_CTRL) NAND Flash Controller Disable */ -/* -------- SMC_SR : (SMC Offset: 0x008) SMC NFC Status Register -------- */ -#define SMC_SR_SMCSTS (0x1 << 0) /**< \brief (SMC_SR) NAND Flash Controller status (this field cannot be reset) */ -#define SMC_SR_RB_RISE (0x1 << 4) /**< \brief (SMC_SR) Selected Ready Busy Rising Edge Detected */ -#define SMC_SR_RB_FALL (0x1 << 5) /**< \brief (SMC_SR) Selected Ready Busy Falling Edge Detected */ -#define SMC_SR_NFCBUSY (0x1 << 8) /**< \brief (SMC_SR) NFC Busy (this field cannot be reset) */ -#define SMC_SR_NFCWR (0x1 << 11) /**< \brief (SMC_SR) NFC Write/Read Operation (this field cannot be reset) */ -#define SMC_SR_NFCSID (0x7 << 12) /**< \brief (SMC_SR) NFC Chip Select ID (this field cannot be reset) */ -#define SMC_SR_XFRDONE (0x1 << 16) /**< \brief (SMC_SR) NFC Data Transfer Terminated */ -#define SMC_SR_CMDDONE (0x1 << 17) /**< \brief (SMC_SR) Command Done */ -#define SMC_SR_DTOE (0x1 << 20) /**< \brief (SMC_SR) Data Timeout Error */ -#define SMC_SR_UNDEF (0x1 << 21) /**< \brief (SMC_SR) Undefined Area Error */ -#define SMC_SR_AWB (0x1 << 22) /**< \brief (SMC_SR) Accessing While Busy */ -#define SMC_SR_NFCASE (0x1 << 23) /**< \brief (SMC_SR) NFC Access Size Error */ -#define SMC_SR_RB_EDGE0 (0x1 << 24) /**< \brief (SMC_SR) Ready/Busy Line 0 Edge Detected */ -/* -------- SMC_IER : (SMC Offset: 0x00C) SMC NFC Interrupt Enable Register -------- */ -#define SMC_IER_RB_RISE (0x1 << 4) /**< \brief (SMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */ -#define SMC_IER_RB_FALL (0x1 << 5) /**< \brief (SMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */ -#define SMC_IER_XFRDONE (0x1 << 16) /**< \brief (SMC_IER) Transfer Done Interrupt Enable */ -#define SMC_IER_CMDDONE (0x1 << 17) /**< \brief (SMC_IER) Command Done Interrupt Enable */ -#define SMC_IER_DTOE (0x1 << 20) /**< \brief (SMC_IER) Data Timeout Error Interrupt Enable */ -#define SMC_IER_UNDEF (0x1 << 21) /**< \brief (SMC_IER) Undefined Area Access Interrupt Enable */ -#define SMC_IER_AWB (0x1 << 22) /**< \brief (SMC_IER) Accessing While Busy Interrupt Enable */ -#define SMC_IER_NFCASE (0x1 << 23) /**< \brief (SMC_IER) NFC Access Size Error Interrupt Enable */ -#define SMC_IER_RB_EDGE0 (0x1 << 24) /**< \brief (SMC_IER) Ready/Busy Line 0 Interrupt Enable */ -/* -------- SMC_IDR : (SMC Offset: 0x010) SMC NFC Interrupt Disable Register -------- */ -#define SMC_IDR_RB_RISE (0x1 << 4) /**< \brief (SMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */ -#define SMC_IDR_RB_FALL (0x1 << 5) /**< \brief (SMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */ -#define SMC_IDR_XFRDONE (0x1 << 16) /**< \brief (SMC_IDR) Transfer Done Interrupt Disable */ -#define SMC_IDR_CMDDONE (0x1 << 17) /**< \brief (SMC_IDR) Command Done Interrupt Disable */ -#define SMC_IDR_DTOE (0x1 << 20) /**< \brief (SMC_IDR) Data Timeout Error Interrupt Disable */ -#define SMC_IDR_UNDEF (0x1 << 21) /**< \brief (SMC_IDR) Undefined Area Access Interrupt Disable */ -#define SMC_IDR_AWB (0x1 << 22) /**< \brief (SMC_IDR) Accessing While Busy Interrupt Disable */ -#define SMC_IDR_NFCASE (0x1 << 23) /**< \brief (SMC_IDR) NFC Access Size Error Interrupt Disable */ -#define SMC_IDR_RB_EDGE0 (0x1 << 24) /**< \brief (SMC_IDR) Ready/Busy Line 0 Interrupt Disable */ -/* -------- SMC_IMR : (SMC Offset: 0x014) SMC NFC Interrupt Mask Register -------- */ -#define SMC_IMR_RB_RISE (0x1 << 4) /**< \brief (SMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */ -#define SMC_IMR_RB_FALL (0x1 << 5) /**< \brief (SMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */ -#define SMC_IMR_XFRDONE (0x1 << 16) /**< \brief (SMC_IMR) Transfer Done Interrupt Mask */ -#define SMC_IMR_CMDDONE (0x1 << 17) /**< \brief (SMC_IMR) Command Done Interrupt Mask */ -#define SMC_IMR_DTOE (0x1 << 20) /**< \brief (SMC_IMR) Data Timeout Error Interrupt Mask */ -#define SMC_IMR_UNDEF (0x1 << 21) /**< \brief (SMC_IMR) Undefined Area Access Interrupt Mask5 */ -#define SMC_IMR_AWB (0x1 << 22) /**< \brief (SMC_IMR) Accessing While Busy Interrupt Mask */ -#define SMC_IMR_NFCASE (0x1 << 23) /**< \brief (SMC_IMR) NFC Access Size Error Interrupt Mask */ -#define SMC_IMR_RB_EDGE0 (0x1 << 24) /**< \brief (SMC_IMR) Ready/Busy Line 0 Interrupt Mask */ -/* -------- SMC_ADDR : (SMC Offset: 0x018) SMC NFC Address Cycle Zero Register -------- */ -#define SMC_ADDR_ADDR_CYCLE0 (0xff << 0) /**< \brief (SMC_ADDR) NAND Flash Array Address cycle 0 */ -/* -------- SMC_BANK : (SMC Offset: 0x01C) SMC Bank Address Register -------- */ -#define SMC_BANK_BANK (0x7 << 0) /**< \brief (SMC_BANK) Bank Identifier */ -/* -------- SMC_ECC_CTRL : (SMC Offset: 0x020) SMC ECC Control Register -------- */ -#define SMC_ECC_CTRL_RST (0x1 << 0) /**< \brief (SMC_ECC_CTRL) Reset ECC */ -#define SMC_ECC_CTRL_SWRST (0x1 << 1) /**< \brief (SMC_ECC_CTRL) Software Reset */ -/* -------- SMC_ECC_MD : (SMC Offset: 0x024) SMC ECC Mode Register -------- */ -#define SMC_ECC_MD_ECC_PAGESIZE (0x3 << 0) /**< \brief (SMC_ECC_MD) */ -#define SMC_ECC_MD_TYPCORREC (0x3 << 4) /**< \brief (SMC_ECC_MD) type of correction */ -/* -------- SMC_ECC_SR1 : (SMC Offset: 0x028) SMC ECC Status 1 Register -------- */ -#define SMC_ECC_SR1_RECERR0 (0x1 << 0) /**< \brief (SMC_ECC_SR1) Recoverable Error */ -#define SMC_ECC_SR1_ECCERR0 (0x3 << 1) /**< \brief (SMC_ECC_SR1) ECC Error */ -#define SMC_ECC_SR1_RECERR1 (0x1 << 4) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes */ -#define SMC_ECC_SR1_ECCERR1 (0x1 << 5) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */ -#define SMC_ECC_SR1_MULERR1 (0x1 << 6) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */ -#define SMC_ECC_SR1_RECERR2 (0x1 << 8) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */ -#define SMC_ECC_SR1_ECCERR2 (0x1 << 9) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */ -#define SMC_ECC_SR1_MULERR2 (0x1 << 10) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */ -#define SMC_ECC_SR1_RECERR3 (0x1 << 12) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */ -#define SMC_ECC_SR1_ECCERR3 (0x1 << 13) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */ -#define SMC_ECC_SR1_MULERR3 (0x1 << 14) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */ -#define SMC_ECC_SR1_RECERR4 (0x1 << 16) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */ -#define SMC_ECC_SR1_ECCERR4 (0x3 << 17) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */ -#define SMC_ECC_SR1_RECERR5 (0x1 << 20) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */ -#define SMC_ECC_SR1_ECCERR5 (0x3 << 21) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */ -#define SMC_ECC_SR1_RECERR6 (0x1 << 24) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */ -#define SMC_ECC_SR1_ECCERR6 (0x3 << 25) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */ -#define SMC_ECC_SR1_RECERR7 (0x1 << 28) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */ -#define SMC_ECC_SR1_ECCERR7 (0x3 << 29) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */ -/* -------- SMC_ECC_PR0 : (SMC Offset: 0x02C) SMC ECC Parity 0 Register -------- */ -#define SMC_ECC_PR0_BITADDR (0xf << 0) /**< \brief (SMC_ECC_PR0) Bit Address */ -#define SMC_ECC_PR0_WORDADDR (0xfff << 4) /**< \brief (SMC_ECC_PR0) Word Address */ -/* -------- SMC_ECC_PR1 : (SMC Offset: 0x030) SMC ECC parity 1 Register -------- */ -#define SMC_ECC_PR1_NPARITY (0xffff << 0) /**< \brief (SMC_ECC_PR1) */ -/* -------- SMC_ECC_SR2 : (SMC Offset: 0x034) SMC ECC status 2 Register -------- */ -#define SMC_ECC_SR2_RECERR8 (0x1 << 0) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2048th and the 2303rd bytes */ -#define SMC_ECC_SR2_ECCERR8 (0x3 << 1) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2048th and the 2303rd bytes */ -#define SMC_ECC_SR2_RECERR9 (0x1 << 4) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2304th and the 2559th bytes */ -#define SMC_ECC_SR2_ECCERR9 (0x1 << 5) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2304th and the 2559th bytes */ -#define SMC_ECC_SR2_MULERR9 (0x1 << 6) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2304th and the 2559th bytes */ -#define SMC_ECC_SR2_RECERR10 (0x1 << 8) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2560th and the 2815th bytes */ -#define SMC_ECC_SR2_ECCERR10 (0x1 << 9) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2560th and the 2815th bytes */ -#define SMC_ECC_SR2_MULERR10 (0x1 << 10) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2560th and the 2815th bytes */ -#define SMC_ECC_SR2_RECERR11 (0x1 << 12) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2816th and the 3071st bytes */ -#define SMC_ECC_SR2_ECCERR11 (0x1 << 13) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2816th and the 3071st bytes */ -#define SMC_ECC_SR2_MULERR11 (0x1 << 14) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2816th and the 3071st bytes */ -#define SMC_ECC_SR2_RECERR12 (0x1 << 16) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3072nd and the 3327th bytes */ -#define SMC_ECC_SR2_ECCERR12 (0x3 << 17) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3072nd and the 3327th bytes */ -#define SMC_ECC_SR2_RECERR13 (0x1 << 20) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3328th and the 3583rd bytes */ -#define SMC_ECC_SR2_ECCERR13 (0x3 << 21) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3328th and the 3583rd bytes */ -#define SMC_ECC_SR2_RECERR14 (0x1 << 24) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3584th and the 3839th bytes */ -#define SMC_ECC_SR2_ECCERR14 (0x3 << 25) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3584th and the 3839th bytes */ -#define SMC_ECC_SR2_RECERR15 (0x1 << 28) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3840th and the 4095th bytes */ -#define SMC_ECC_SR2_ECCERR15 (0x3 << 29) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3840th and the 4095th bytes */ -/* -------- SMC_ECC_PR2 : (SMC Offset: 0x038) SMC ECC parity 2 Register -------- */ -/* -------- SMC_ECC_PR3 : (SMC Offset: 0x03C) SMC ECC parity 3 Register -------- */ -/* -------- SMC_ECC_PR4 : (SMC Offset: 0x040) SMC ECC parity 4 Register -------- */ -/* -------- SMC_ECC_PR5 : (SMC Offset: 0x044) SMC ECC parity 5 Register -------- */ -/* -------- SMC_ECC_PR6 : (SMC Offset: 0x048) SMC ECC parity 6 Register -------- */ -/* -------- SMC_ECC_PR7 : (SMC Offset: 0x04C) SMC ECC parity 7 Register -------- */ -/* -------- SMC_ECC_PR8 : (SMC Offset: 0x050) SMC ECC parity 8 Register -------- */ -/* -------- SMC_ECC_PR9 : (SMC Offset: 0x054) SMC ECC parity 9 Register -------- */ -/* -------- SMC_ECC_PR10 : (SMC Offset: 0x058) SMC ECC parity 10 Register -------- */ -/* -------- SMC_ECC_PR11 : (SMC Offset: 0x05C) SMC ECC parity 11 Register -------- */ -/* -------- SMC_ECC_PR12 : (SMC Offset: 0x060) SMC ECC parity 12 Register -------- */ -/* -------- SMC_ECC_PR13 : (SMC Offset: 0x064) SMC ECC parity 13 Register -------- */ -/* -------- SMC_ECC_PR14 : (SMC Offset: 0x068) SMC ECC parity 14 Register -------- */ -/* -------- SMC_ECC_PR15 : (SMC Offset: 0x06C) SMC ECC parity 15 Register -------- */ -/* -------- SMC_SETUP0 : (SMC Offset: 0x70) SMC SETUP Register (CS_number = 0) -------- */ -#define SMC_SETUP0_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP0) NWE Setup length */ -#define SMC_SETUP0_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP0) NCS Setup length in Write access */ -#define SMC_SETUP0_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP0) NRD Setup length */ -#define SMC_SETUP0_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP0) NCS Setup length in Read access */ -/* -------- SMC_PULSE0 : (SMC Offset: 0x74) SMC PULSE Register (CS_number = 0) -------- */ -#define SMC_PULSE0_NWE_PULSE (0x3f << 0) /**< \brief (SMC_PULSE0) NWE Pulse Length */ -#define SMC_PULSE0_NCS_WR_PULSE (0x3f << 8) /**< \brief (SMC_PULSE0) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE0_NRD_PULSE (0x3f << 16) /**< \brief (SMC_PULSE0) NRD Pulse Length */ -#define SMC_PULSE0_NCS_RD_PULSE (0x3f << 24) /**< \brief (SMC_PULSE0) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE0 : (SMC Offset: 0x78) SMC CYCLE Register (CS_number = 0) -------- */ -#define SMC_CYCLE0_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE0) Total Write Cycle Length */ -#define SMC_CYCLE0_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE0) Total Read Cycle Length */ -/* -------- SMC_TIMINGS0 : (SMC Offset: 0x7C) SMC TIMINGS Register (CS_number = 0) -------- */ -#define SMC_TIMINGS0_TCLR (0xf << 0) /**< \brief (SMC_TIMINGS0) CLE to REN Low Delay */ -#define SMC_TIMINGS0_TADL (0xf << 4) /**< \brief (SMC_TIMINGS0) ALE to Data Start */ -#define SMC_TIMINGS0_TAR (0xf << 8) /**< \brief (SMC_TIMINGS0) ALE to REN Low Delay */ -#define SMC_TIMINGS0_OCMS (0x1 << 12) /**< \brief (SMC_TIMINGS0) Off Chip Memory Scrambling Enable */ -#define SMC_TIMINGS0_TRR (0xf << 16) /**< \brief (SMC_TIMINGS0) Ready to REN Low Delay */ -#define SMC_TIMINGS0_TWB (0xf << 24) /**< \brief (SMC_TIMINGS0) WEN High to REN to Busy */ -#define SMC_TIMINGS0_RBNSEL (0x7 << 28) /**< \brief (SMC_TIMINGS0) Ready/Busy Line Selection */ -#define SMC_TIMINGS0_NFSEL (0x1 << 31) /**< \brief (SMC_TIMINGS0) NAND Flash Selection */ -/* -------- SMC_MODE0 : (SMC Offset: 0x80) SMC MODE Register (CS_number = 0) -------- */ -#define SMC_MODE0_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE0) */ -#define SMC_MODE0_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE0) NWAIT Mode */ -#define SMC_MODE0_BAT (0x1 << 8) /**< \brief (SMC_MODE0) Byte Access Type */ -#define SMC_MODE0_DBW (0x1 << 12) /**< \brief (SMC_MODE0) Data Bus Width */ -#define SMC_MODE0_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE0) Data Float Time */ -#define SMC_MODE0_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE0) TDF Optimization */ -/* -------- SMC_SETUP1 : (SMC Offset: 0x84) SMC SETUP Register (CS_number = 1) -------- */ -#define SMC_SETUP1_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP1) NWE Setup length */ -#define SMC_SETUP1_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP1) NCS Setup length in Write access */ -#define SMC_SETUP1_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP1) NRD Setup length */ -#define SMC_SETUP1_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP1) NCS Setup length in Read access */ -/* -------- SMC_PULSE1 : (SMC Offset: 0x88) SMC PULSE Register (CS_number = 1) -------- */ -#define SMC_PULSE1_NWE_PULSE (0x3f << 0) /**< \brief (SMC_PULSE1) NWE Pulse Length */ -#define SMC_PULSE1_NCS_WR_PULSE (0x3f << 8) /**< \brief (SMC_PULSE1) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE1_NRD_PULSE (0x3f << 16) /**< \brief (SMC_PULSE1) NRD Pulse Length */ -#define SMC_PULSE1_NCS_RD_PULSE (0x3f << 24) /**< \brief (SMC_PULSE1) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE1 : (SMC Offset: 0x8C) SMC CYCLE Register (CS_number = 1) -------- */ -#define SMC_CYCLE1_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE1) Total Write Cycle Length */ -#define SMC_CYCLE1_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE1) Total Read Cycle Length */ -/* -------- SMC_TIMINGS1 : (SMC Offset: 0x90) SMC TIMINGS Register (CS_number = 1) -------- */ -#define SMC_TIMINGS1_TCLR (0xf << 0) /**< \brief (SMC_TIMINGS1) CLE to REN Low Delay */ -#define SMC_TIMINGS1_TADL (0xf << 4) /**< \brief (SMC_TIMINGS1) ALE to Data Start */ -#define SMC_TIMINGS1_TAR (0xf << 8) /**< \brief (SMC_TIMINGS1) ALE to REN Low Delay */ -#define SMC_TIMINGS1_OCMS (0x1 << 12) /**< \brief (SMC_TIMINGS1) Off Chip Memory Scrambling Enable */ -#define SMC_TIMINGS1_TRR (0xf << 16) /**< \brief (SMC_TIMINGS1) Ready to REN Low Delay */ -#define SMC_TIMINGS1_TWB (0xf << 24) /**< \brief (SMC_TIMINGS1) WEN High to REN to Busy */ -#define SMC_TIMINGS1_RBNSEL (0x7 << 28) /**< \brief (SMC_TIMINGS1) Ready/Busy Line Selection */ -#define SMC_TIMINGS1_NFSEL (0x1 << 31) /**< \brief (SMC_TIMINGS1) NAND Flash Selection */ -/* -------- SMC_MODE1 : (SMC Offset: 0x94) SMC MODE Register (CS_number = 1) -------- */ -#define SMC_MODE1_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE1) */ -#define SMC_MODE1_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE1) NWAIT Mode */ -#define SMC_MODE1_BAT (0x1 << 8) /**< \brief (SMC_MODE1) Byte Access Type */ -#define SMC_MODE1_DBW (0x1 << 12) /**< \brief (SMC_MODE1) Data Bus Width */ -#define SMC_MODE1_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE1) Data Float Time */ -#define SMC_MODE1_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE1) TDF Optimization */ -/* -------- SMC_SETUP2 : (SMC Offset: 0x98) SMC SETUP Register (CS_number = 2) -------- */ -#define SMC_SETUP2_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP2) NWE Setup length */ -#define SMC_SETUP2_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP2) NCS Setup length in Write access */ -#define SMC_SETUP2_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP2) NRD Setup length */ -#define SMC_SETUP2_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP2) NCS Setup length in Read access */ -/* -------- SMC_PULSE2 : (SMC Offset: 0x9C) SMC PULSE Register (CS_number = 2) -------- */ -#define SMC_PULSE2_NWE_PULSE (0x3f << 0) /**< \brief (SMC_PULSE2) NWE Pulse Length */ -#define SMC_PULSE2_NCS_WR_PULSE (0x3f << 8) /**< \brief (SMC_PULSE2) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE2_NRD_PULSE (0x3f << 16) /**< \brief (SMC_PULSE2) NRD Pulse Length */ -#define SMC_PULSE2_NCS_RD_PULSE (0x3f << 24) /**< \brief (SMC_PULSE2) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE2 : (SMC Offset: 0xA0) SMC CYCLE Register (CS_number = 2) -------- */ -#define SMC_CYCLE2_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE2) Total Write Cycle Length */ -#define SMC_CYCLE2_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE2) Total Read Cycle Length */ -/* -------- SMC_TIMINGS2 : (SMC Offset: 0xA4) SMC TIMINGS Register (CS_number = 2) -------- */ -#define SMC_TIMINGS2_TCLR (0xf << 0) /**< \brief (SMC_TIMINGS2) CLE to REN Low Delay */ -#define SMC_TIMINGS2_TADL (0xf << 4) /**< \brief (SMC_TIMINGS2) ALE to Data Start */ -#define SMC_TIMINGS2_TAR (0xf << 8) /**< \brief (SMC_TIMINGS2) ALE to REN Low Delay */ -#define SMC_TIMINGS2_OCMS (0x1 << 12) /**< \brief (SMC_TIMINGS2) Off Chip Memory Scrambling Enable */ -#define SMC_TIMINGS2_TRR (0xf << 16) /**< \brief (SMC_TIMINGS2) Ready to REN Low Delay */ -#define SMC_TIMINGS2_TWB (0xf << 24) /**< \brief (SMC_TIMINGS2) WEN High to REN to Busy */ -#define SMC_TIMINGS2_RBNSEL (0x7 << 28) /**< \brief (SMC_TIMINGS2) Ready/Busy Line Selection */ -#define SMC_TIMINGS2_NFSEL (0x1 << 31) /**< \brief (SMC_TIMINGS2) NAND Flash Selection */ -/* -------- SMC_MODE2 : (SMC Offset: 0xA8) SMC MODE Register (CS_number = 2) -------- */ -#define SMC_MODE2_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE2) */ -#define SMC_MODE2_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE2) NWAIT Mode */ -#define SMC_MODE2_BAT (0x1 << 8) /**< \brief (SMC_MODE2) Byte Access Type */ -#define SMC_MODE2_DBW (0x1 << 12) /**< \brief (SMC_MODE2) Data Bus Width */ -#define SMC_MODE2_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE2) Data Float Time */ -#define SMC_MODE2_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE2) TDF Optimization */ -/* -------- SMC_SETUP3 : (SMC Offset: 0xAC) SMC SETUP Register (CS_number = 3) -------- */ -#define SMC_SETUP3_NWE_SETUP (0x3f << 0) /**< \brief (SMC_SETUP3) NWE Setup length */ -#define SMC_SETUP3_NCS_WR_SETUP (0x3f << 8) /**< \brief (SMC_SETUP3) NCS Setup length in Write access */ -#define SMC_SETUP3_NRD_SETUP (0x3f << 16) /**< \brief (SMC_SETUP3) NRD Setup length */ -#define SMC_SETUP3_NCS_RD_SETUP (0x3f << 24) /**< \brief (SMC_SETUP3) NCS Setup length in Read access */ -/* -------- SMC_PULSE3 : (SMC Offset: 0xB0) SMC PULSE Register (CS_number = 3) -------- */ -#define SMC_PULSE3_NWE_PULSE (0x3f << 0) /**< \brief (SMC_PULSE3) NWE Pulse Length */ -#define SMC_PULSE3_NCS_WR_PULSE (0x3f << 8) /**< \brief (SMC_PULSE3) NCS Pulse Length in WRITE Access */ -#define SMC_PULSE3_NRD_PULSE (0x3f << 16) /**< \brief (SMC_PULSE3) NRD Pulse Length */ -#define SMC_PULSE3_NCS_RD_PULSE (0x3f << 24) /**< \brief (SMC_PULSE3) NCS Pulse Length in READ Access */ -/* -------- SMC_CYCLE3 : (SMC Offset: 0xB4) SMC CYCLE Register (CS_number = 3) -------- */ -#define SMC_CYCLE3_NWE_CYCLE (0x1ff << 0) /**< \brief (SMC_CYCLE3) Total Write Cycle Length */ -#define SMC_CYCLE3_NRD_CYCLE (0x1ff << 16) /**< \brief (SMC_CYCLE3) Total Read Cycle Length */ -/* -------- SMC_TIMINGS3 : (SMC Offset: 0xB8) SMC TIMINGS Register (CS_number = 3) -------- */ -#define SMC_TIMINGS3_TCLR (0xf << 0) /**< \brief (SMC_TIMINGS3) CLE to REN Low Delay */ -#define SMC_TIMINGS3_TADL (0xf << 4) /**< \brief (SMC_TIMINGS3) ALE to Data Start */ -#define SMC_TIMINGS3_TAR (0xf << 8) /**< \brief (SMC_TIMINGS3) ALE to REN Low Delay */ -#define SMC_TIMINGS3_OCMS (0x1 << 12) /**< \brief (SMC_TIMINGS3) Off Chip Memory Scrambling Enable */ -#define SMC_TIMINGS3_TRR (0xf << 16) /**< \brief (SMC_TIMINGS3) Ready to REN Low Delay */ -#define SMC_TIMINGS3_TWB (0xf << 24) /**< \brief (SMC_TIMINGS3) WEN High to REN to Busy */ -#define SMC_TIMINGS3_RBNSEL (0x7 << 28) /**< \brief (SMC_TIMINGS3) Ready/Busy Line Selection */ -#define SMC_TIMINGS3_NFSEL (0x1 << 31) /**< \brief (SMC_TIMINGS3) NAND Flash Selection */ -/* -------- SMC_MODE3 : (SMC Offset: 0xBC) SMC MODE Register (CS_number = 3) -------- */ -#define SMC_MODE3_READ_MODE (0x1 << 0) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_WRITE_MODE (0x1 << 1) /**< \brief (SMC_MODE3) */ -#define SMC_MODE3_EXNW_MODE (0x3 << 4) /**< \brief (SMC_MODE3) NWAIT Mode */ -#define SMC_MODE3_BAT (0x1 << 8) /**< \brief (SMC_MODE3) Byte Access Type */ -#define SMC_MODE3_DBW (0x1 << 12) /**< \brief (SMC_MODE3) Data Bus Width */ -#define SMC_MODE3_TDF_CYCLES (0xf << 16) /**< \brief (SMC_MODE3) Data Float Time */ -#define SMC_MODE3_TDF_MODE (0x1 << 20) /**< \brief (SMC_MODE3) TDF Optimization */ -/* -------- SMC_OCMS : (SMC Offset: 0x110) SMC OCMS MODE Register -------- */ -#define SMC_OCMS_SMSE (0x1 << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ -#define SMC_OCMS_SRSE (0x1 << 1) /**< \brief (SMC_OCMS) SRAM Scrambling Enable */ -/* -------- SMC_KEY1 : (SMC Offset: 0x114) SMC KEY1 Register -------- */ -#define SMC_KEY1_KEY1 (0xffffffff << 0) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ -/* -------- SMC_KEY2 : (SMC Offset: 0x118) SMC KEY2 Register -------- */ -#define SMC_KEY2_KEY2 (0xffffffff << 0) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ -/* -------- SMC_WPCR : (SMC Offset: 0x1E4) Write Protection Control Register -------- */ -#define SMC_WPCR_WP_EN (0x1 << 0) /**< \brief (SMC_WPCR) */ -#define SMC_WPCR_WP_KEY (0xffffff << 8) /**< \brief (SMC_WPCR) Write Protection KEY password */ -/* -------- SMC_WPSR : (SMC Offset: 0x1E8) Write Protection Status Register -------- */ -#define SMC_WPSR_WP_VS (0xf << 0) /**< \brief (SMC_WPSR) Write Protection Violation Status */ -#define SMC_WPSR_WP_VSRC (0xffff << 8) /**< \brief (SMC_WPSR) Write Protection Violation SouRCe */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_SPI Serial Peripheral Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Spi hardware registers */ -typedef struct { - WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ - RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ - RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ - WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ - RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ - WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ - WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ - RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ - RwReg Reserved1[4]; - RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ - RwReg Reserved2[41]; - RwReg SPI_WPCR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ - RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ -} Spi; -#endif /* __ASSEMBLY__ */ -/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ -#define SPI_CR_SPIEN (0x1 << 0) /**< \brief (SPI_CR) SPI Enable */ -#define SPI_CR_SPIDIS (0x1 << 1) /**< \brief (SPI_CR) SPI Disable */ -#define SPI_CR_SWRST (0x1 << 7) /**< \brief (SPI_CR) SPI Software Reset */ -#define SPI_CR_LASTXFER (0x1 << 24) /**< \brief (SPI_CR) Last Transfer */ -/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ -#define SPI_MR_MSTR (0x1 << 0) /**< \brief (SPI_MR) Master/Slave Mode */ -#define SPI_MR_PS (0x1 << 1) /**< \brief (SPI_MR) Peripheral Select */ -#define SPI_MR_PS_FIXED (0x0 << 1) /**< \brief (SPI_MR) Fixed Peripheral Select. */ -#define SPI_MR_PS_VARIABLE (0x1 << 1) /**< \brief (SPI_MR) Variable Peripheral Select. */ -#define SPI_MR_PCSDEC (0x1 << 2) /**< \brief (SPI_MR) Chip Select Decode */ -#define SPI_MR_MODFDIS (0x1 << 4) /**< \brief (SPI_MR) Mode Fault Detection */ -#define SPI_MR_WDRBT (0x1 << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ -#define SPI_MR_LLB (0x1 << 7) /**< \brief (SPI_MR) Local Loopback Enable */ -#define SPI_MR_PCS (0xf << 16) /**< \brief (SPI_MR) Peripheral Chip Select */ -#define SPI_MR_DLYBCS (0xff << 24) /**< \brief (SPI_MR) Delay Between Chip Selects */ -/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ -#define SPI_RDR_RD (0xffff << 0) /**< \brief (SPI_RDR) Receive Data */ -#define SPI_RDR_PCS (0xf << 16) /**< \brief (SPI_RDR) Peripheral Chip Select */ -/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ -#define SPI_TDR_TD (0xffff << 0) /**< \brief (SPI_TDR) Transmit Data */ -#define SPI_TDR_PCS (0xf << 16) /**< \brief (SPI_TDR) Peripheral Chip Select */ -#define SPI_TDR_LASTXFER (0x1 << 24) /**< \brief (SPI_TDR) Last Transfer */ -/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ -#define SPI_SR_RDRF (0x1 << 0) /**< \brief (SPI_SR) Receive Data Register Full */ -#define SPI_SR_TDRE (0x1 << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ -#define SPI_SR_MODF (0x1 << 2) /**< \brief (SPI_SR) Mode Fault Error */ -#define SPI_SR_OVRES (0x1 << 3) /**< \brief (SPI_SR) Overrun Error Status */ -#define SPI_SR_RXBUFF (0x1 << 6) /**< \brief (SPI_SR) */ -#define SPI_SR_NSSR (0x1 << 8) /**< \brief (SPI_SR) NSS Rising */ -#define SPI_SR_TXEMPTY (0x1 << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ -#define SPI_SR_UNDES (0x1 << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ -#define SPI_SR_SPIENS (0x1 << 16) /**< \brief (SPI_SR) SPI Enable Status */ -/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ -#define SPI_IER_RDRF (0x1 << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ -#define SPI_IER_TDRE (0x1 << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ -#define SPI_IER_MODF (0x1 << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ -#define SPI_IER_OVRES (0x1 << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ -#define SPI_IER_RXBUFF (0x1 << 6) /**< \brief (SPI_IER) */ -#define SPI_IER_NSSR (0x1 << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ -#define SPI_IER_TXEMPTY (0x1 << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ -#define SPI_IER_UNDES (0x1 << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ -/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ -#define SPI_IDR_RDRF (0x1 << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ -#define SPI_IDR_TDRE (0x1 << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ -#define SPI_IDR_MODF (0x1 << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ -#define SPI_IDR_OVRES (0x1 << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ -#define SPI_IDR_RXBUFF (0x1 << 6) /**< \brief (SPI_IDR) */ -#define SPI_IDR_NSSR (0x1 << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ -#define SPI_IDR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ -#define SPI_IDR_UNDES (0x1 << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ -/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ -#define SPI_IMR_RDRF (0x1 << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ -#define SPI_IMR_TDRE (0x1 << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ -#define SPI_IMR_MODF (0x1 << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ -#define SPI_IMR_OVRES (0x1 << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ -#define SPI_IMR_RXBUFF (0x1 << 6) /**< \brief (SPI_IMR) */ -#define SPI_IMR_NSSR (0x1 << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ -#define SPI_IMR_TXEMPTY (0x1 << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ -#define SPI_IMR_UNDES (0x1 << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ -/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ -#define SPI_CSR_CPOL (0x1 << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ -#define SPI_CSR_NCPHA (0x1 << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ -#define SPI_CSR_CSNAAT (0x1 << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_CSAAT (0x1 << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ -#define SPI_CSR_BITS (0xf << 4) /**< \brief (SPI_CSR[4]) Bits Per Transfer (See the (Note:) below the register table; Section 9.9 "SPI Chip Select Register" on page 37.) */ -#define SPI_CSR_BITS_8 (0x0 << 4) /**< \brief (SPI_CSR[4]) 8 */ -#define SPI_CSR_BITS_9 (0x1 << 4) /**< \brief (SPI_CSR[4]) 9 */ -#define SPI_CSR_BITS_10 (0x2 << 4) /**< \brief (SPI_CSR[4]) 10 */ -#define SPI_CSR_BITS_11 (0x3 << 4) /**< \brief (SPI_CSR[4]) 11 */ -#define SPI_CSR_BITS_12 (0x4 << 4) /**< \brief (SPI_CSR[4]) 12 */ -#define SPI_CSR_BITS_13 (0x5 << 4) /**< \brief (SPI_CSR[4]) 13 */ -#define SPI_CSR_BITS_14 (0x6 << 4) /**< \brief (SPI_CSR[4]) 14 */ -#define SPI_CSR_BITS_15 (0x7 << 4) /**< \brief (SPI_CSR[4]) 15 */ -#define SPI_CSR_BITS_16 (0x8 << 4) /**< \brief (SPI_CSR[4]) 16 */ -#define SPI_CSR_SCBR (0xff << 8) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ -#define SPI_CSR_DLYBS (0xff << 16) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ -#define SPI_CSR_DLYBCT (0xff << 24) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ -/* -------- SPI_WPCR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ -#define SPI_WPCR_SPIWPEN (0x1 << 0) /**< \brief (SPI_WPCR) SPI Write Protection Enable */ -#define SPI_WPCR_SPIWPKEY (0xffffff << 8) /**< \brief (SPI_WPCR) SPI Write Protection Key Password */ -/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ -#define SPI_WPSR_SPIWPVS (0x7 << 0) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */ -#define SPI_WPSR_SPIWPVSRC (0xff << 8) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_SSC Synchronous Serial Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Ssc hardware registers */ -typedef struct { - WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ - RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ - RwReg Reserved1[2]; - RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ - RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ - RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ - RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ - RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ - WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ - RwReg Reserved2[2]; - RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ - RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ - RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ - RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ - RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ - WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ - WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ - RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ - RwReg Reserved3[37]; - RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */ - RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */ -} Ssc; -#endif /* __ASSEMBLY__ */ -/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ -#define SSC_CR_RXEN (0x1 << 0) /**< \brief (SSC_CR) Receive Enable */ -#define SSC_CR_RXDIS (0x1 << 1) /**< \brief (SSC_CR) Receive Disable */ -#define SSC_CR_TXEN (0x1 << 8) /**< \brief (SSC_CR) Transmit Enable */ -#define SSC_CR_TXDIS (0x1 << 9) /**< \brief (SSC_CR) Transmit Disable */ -#define SSC_CR_SWRST (0x1 << 15) /**< \brief (SSC_CR) Software Reset */ -/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ -#define SSC_CMR_DIV (0xfff << 0) /**< \brief (SSC_CMR) Clock Divider */ -/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ -#define SSC_RCMR_CKS (0x3 << 0) /**< \brief (SSC_RCMR) Receive Clock Selection */ -#define SSC_RCMR_CKS_DIV (0x0 << 0) /**< \brief (SSC_RCMR) Divided Clock */ -#define SSC_RCMR_CKS_TK (0x1 << 0) /**< \brief (SSC_RCMR) TK Clock signal */ -#define SSC_RCMR_CKS_RK (0x2 << 0) /**< \brief (SSC_RCMR) RK pin */ -#define SSC_RCMR_CKO (0x7 << 2) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ -#define SSC_RCMR_CKI (0x1 << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ -#define SSC_RCMR_CKG (0x3 << 6) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ -#define SSC_RCMR_CKG_NONE (0x0 << 6) /**< \brief (SSC_RCMR) None, continuous clock */ -#define SSC_RCMR_CKG_LOW (0x1 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ -#define SSC_RCMR_CKG_HIGH (0x2 << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ -#define SSC_RCMR_START (0xf << 8) /**< \brief (SSC_RCMR) Receive Start Selection */ -#define SSC_RCMR_STOP (0x1 << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ -#define SSC_RCMR_STTDLY (0xff << 16) /**< \brief (SSC_RCMR) Receive Start Delay */ -#define SSC_RCMR_PERIOD (0xff << 24) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ -/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ -#define SSC_RFMR_DATLEN (0x1f << 0) /**< \brief (SSC_RFMR) Data Length */ -#define SSC_RFMR_LOOP (0x1 << 5) /**< \brief (SSC_RFMR) Loop Mode */ -#define SSC_RFMR_MSBF (0x1 << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ -#define SSC_RFMR_DATNB (0xf << 8) /**< \brief (SSC_RFMR) Data Number per Frame */ -#define SSC_RFMR_FSLEN (0xf << 16) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ -#define SSC_RFMR_FSOS (0x7 << 20) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ -#define SSC_RFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ -#define SSC_RFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_RFMR) FSLEN Field Extension */ -/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ -#define SSC_TCMR_CKS (0x3 << 0) /**< \brief (SSC_TCMR) Transmit Clock Selection */ -#define SSC_TCMR_CKO (0x7 << 2) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ -#define SSC_TCMR_CKI (0x1 << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ -#define SSC_TCMR_CKG (0x3 << 6) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ -#define SSC_TCMR_START (0xf << 8) /**< \brief (SSC_TCMR) Transmit Start Selection */ -#define SSC_TCMR_STTDLY (0xff << 16) /**< \brief (SSC_TCMR) Transmit Start Delay */ -#define SSC_TCMR_PERIOD (0xff << 24) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ -/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ -#define SSC_TFMR_DATLEN (0x1f << 0) /**< \brief (SSC_TFMR) Data Length */ -#define SSC_TFMR_DATDEF (0x1 << 5) /**< \brief (SSC_TFMR) Data Default Value */ -#define SSC_TFMR_MSBF (0x1 << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ -#define SSC_TFMR_DATNB (0xf << 8) /**< \brief (SSC_TFMR) Data Number per frame */ -#define SSC_TFMR_FSLEN (0xf << 16) /**< \brief (SSC_TFMR) Transmit Frame Syn Length */ -#define SSC_TFMR_FSOS (0x7 << 20) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ -#define SSC_TFMR_FSDEN (0x1 << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ -#define SSC_TFMR_FSEDGE (0x1 << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ -#define SSC_TFMR_FSLEN_EXT (0xf << 28) /**< \brief (SSC_TFMR) FSLEN Field Extension */ -/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ -#define SSC_RHR_RDAT (0xffffffff << 0) /**< \brief (SSC_RHR) Receive Data */ -/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ -#define SSC_THR_TDAT (0xffffffff << 0) /**< \brief (SSC_THR) Transmit Data */ -/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ -#define SSC_RSHR_RSDAT (0xffff << 0) /**< \brief (SSC_RSHR) Receive Synchronization Data */ -/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ -#define SSC_TSHR_TSDAT (0xffff << 0) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ -/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ -#define SSC_RC0R_CP0 (0xffff << 0) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ -/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ -#define SSC_RC1R_CP1 (0xffff << 0) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ -/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ -#define SSC_SR_TXRDY (0x1 << 0) /**< \brief (SSC_SR) Transmit Ready */ -#define SSC_SR_TXEMPTY (0x1 << 1) /**< \brief (SSC_SR) Transmit Empty */ -#define SSC_SR_ENDTX (0x1 << 2) /**< \brief (SSC_SR) End of Transmission */ -#define SSC_SR_TXBUFE (0x1 << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */ -#define SSC_SR_RXRDY (0x1 << 4) /**< \brief (SSC_SR) Receive Ready */ -#define SSC_SR_OVRUN (0x1 << 5) /**< \brief (SSC_SR) Receive Overrun */ -#define SSC_SR_ENDRX (0x1 << 6) /**< \brief (SSC_SR) End of Reception */ -#define SSC_SR_RXBUFF (0x1 << 7) /**< \brief (SSC_SR) Receive Buffer Full */ -#define SSC_SR_CP0 (0x1 << 8) /**< \brief (SSC_SR) Compare 0 */ -#define SSC_SR_CP1 (0x1 << 9) /**< \brief (SSC_SR) Compare 1 */ -#define SSC_SR_TXSYN (0x1 << 10) /**< \brief (SSC_SR) Transmit Sync */ -#define SSC_SR_RXSYN (0x1 << 11) /**< \brief (SSC_SR) Receive Sync */ -#define SSC_SR_TXEN (0x1 << 16) /**< \brief (SSC_SR) Transmit Enable */ -#define SSC_SR_RXEN (0x1 << 17) /**< \brief (SSC_SR) Receive Enable */ -/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ -#define SSC_IER_TXRDY (0x1 << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ -#define SSC_IER_TXEMPTY (0x1 << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ -#define SSC_IER_ENDTX (0x1 << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */ -#define SSC_IER_TXBUFE (0x1 << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */ -#define SSC_IER_RXRDY (0x1 << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ -#define SSC_IER_OVRUN (0x1 << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ -#define SSC_IER_ENDRX (0x1 << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */ -#define SSC_IER_RXBUFF (0x1 << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */ -#define SSC_IER_CP0 (0x1 << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ -#define SSC_IER_CP1 (0x1 << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ -#define SSC_IER_TXSYN (0x1 << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ -#define SSC_IER_RXSYN (0x1 << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ -/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ -#define SSC_IDR_TXRDY (0x1 << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ -#define SSC_IDR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ -#define SSC_IDR_ENDTX (0x1 << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */ -#define SSC_IDR_TXBUFE (0x1 << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */ -#define SSC_IDR_RXRDY (0x1 << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ -#define SSC_IDR_OVRUN (0x1 << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ -#define SSC_IDR_ENDRX (0x1 << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */ -#define SSC_IDR_RXBUFF (0x1 << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */ -#define SSC_IDR_CP0 (0x1 << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ -#define SSC_IDR_CP1 (0x1 << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ -#define SSC_IDR_TXSYN (0x1 << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ -#define SSC_IDR_RXSYN (0x1 << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ -/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ -#define SSC_IMR_TXRDY (0x1 << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ -#define SSC_IMR_TXEMPTY (0x1 << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ -#define SSC_IMR_ENDTX (0x1 << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */ -#define SSC_IMR_TXBUFE (0x1 << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */ -#define SSC_IMR_RXRDY (0x1 << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ -#define SSC_IMR_OVRUN (0x1 << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ -#define SSC_IMR_ENDRX (0x1 << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */ -#define SSC_IMR_RXBUFF (0x1 << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */ -#define SSC_IMR_CP0 (0x1 << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ -#define SSC_IMR_CP1 (0x1 << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ -#define SSC_IMR_TXSYN (0x1 << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ -#define SSC_IMR_RXSYN (0x1 << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ -/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */ -#define SSC_WPMR_WPEN (0x1 << 0) /**< \brief (SSC_WPMR) Write Protect Enable */ -#define SSC_WPMR_WPKEY (0xffffff << 8) /**< \brief (SSC_WPMR) Write Protect KEY */ -/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */ -#define SSC_WPSR_WPVS (0x1 << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */ -#define SSC_WPSR_WPVSRC (0xffff << 8) /**< \brief (SSC_WPSR) Write Protect Violation Source */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Supply Controller */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_SUPC Supply Controller */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Supc hardware registers */ -typedef struct { - WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ - RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ - RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ - RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */ - RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */ - RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ -} Supc; -#endif /* __ASSEMBLY__ */ -/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ -#define SUPC_CR_VROFF (0x1 << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ -#define SUPC_CR_VROFF_NO_EFFECT (0x0 << 2) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_VROFF_STOP_VREG (0x1 << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */ -#define SUPC_CR_XTALSEL (0x1 << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ -#define SUPC_CR_XTALSEL_NO_EFFECT (0x0 << 3) /**< \brief (SUPC_CR) no effect. */ -#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1 << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ -#define SUPC_CR_KEY (0xff << 24) /**< \brief (SUPC_CR) Password */ -/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ -#define SUPC_SMMR_SMTH (0xf << 0) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ -#define SUPC_SMMR_SMTH_1_9V (0x0 << 0) /**< \brief (SUPC_SMMR) 1.9 V */ -#define SUPC_SMMR_SMTH_2_0V (0x1 << 0) /**< \brief (SUPC_SMMR) 2.0 V */ -#define SUPC_SMMR_SMTH_2_1V (0x2 << 0) /**< \brief (SUPC_SMMR) 2.1 V */ -#define SUPC_SMMR_SMTH_2_2V (0x3 << 0) /**< \brief (SUPC_SMMR) 2.2 V */ -#define SUPC_SMMR_SMTH_2_3V (0x4 << 0) /**< \brief (SUPC_SMMR) 2.3 V */ -#define SUPC_SMMR_SMTH_2_4V (0x5 << 0) /**< \brief (SUPC_SMMR) 2.4 V */ -#define SUPC_SMMR_SMTH_2_5V (0x6 << 0) /**< \brief (SUPC_SMMR) 2.5 V */ -#define SUPC_SMMR_SMTH_2_6V (0x7 << 0) /**< \brief (SUPC_SMMR) 2.6 V */ -#define SUPC_SMMR_SMTH_2_7V (0x8 << 0) /**< \brief (SUPC_SMMR) 2.7 V */ -#define SUPC_SMMR_SMTH_2_8V (0x9 << 0) /**< \brief (SUPC_SMMR) 2.8 V */ -#define SUPC_SMMR_SMTH_2_9V (0xA << 0) /**< \brief (SUPC_SMMR) 2.9 V */ -#define SUPC_SMMR_SMTH_3_0V (0xB << 0) /**< \brief (SUPC_SMMR) 3.0 V */ -#define SUPC_SMMR_SMTH_3_1V (0xC << 0) /**< \brief (SUPC_SMMR) 3.1 V */ -#define SUPC_SMMR_SMTH_3_2V (0xD << 0) /**< \brief (SUPC_SMMR) 3.2 V */ -#define SUPC_SMMR_SMTH_3_3V (0xE << 0) /**< \brief (SUPC_SMMR) 3.3 V */ -#define SUPC_SMMR_SMTH_3_4V (0xF << 0) /**< \brief (SUPC_SMMR) 3.4 V */ -#define SUPC_SMMR_SMSMPL (0x7 << 8) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ -#define SUPC_SMMR_SMSMPL_SMD (0x0 << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ -#define SUPC_SMMR_SMSMPL_CSM (0x1 << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ -#define SUPC_SMMR_SMSMPL_32SLCK (0x2 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ -#define SUPC_SMMR_SMSMPL_256SLCK (0x3 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ -#define SUPC_SMMR_SMSMPL_2048SLCK (0x4 << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ -#define SUPC_SMMR_SMRSTEN (0x1 << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ -#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN (0x1 << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ -#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ -#define SUPC_SMMR_SMIEN_ENABLE (0x1 << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ -/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ -#define SUPC_MR_BODRSTEN (0x1 << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ -#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ -#define SUPC_MR_BODRSTEN_ENABLE (0x1 << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ -#define SUPC_MR_BODDIS (0x1 << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ -#define SUPC_MR_BODDIS_ENABLE (0x0 << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ -#define SUPC_MR_BODDIS_DISABLE (0x1 << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ -#define SUPC_MR_VDDIORDY (0x1 << 14) /**< \brief (SUPC_MR) VDDIO Ready */ -#define SUPC_MR_VDDIORDY_VDDIO_REMOVED (0x0 << 14) /**< \brief (SUPC_MR) VDDIO is removed (used before going to backup mode when backup batteries are used) */ -#define SUPC_MR_VDDIORDY_VDDIO_PRESENT (0x1 << 14) /**< \brief (SUPC_MR) VDDIO is present (used before going to backup mode when backup batteries are used) */ -#define SUPC_MR_OSCBYPASS (0x1 << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ -#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0 << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ -#define SUPC_MR_OSCBYPASS_BYPASS (0x1 << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ -#define SUPC_MR_KEY (0xff << 24) /**< \brief (SUPC_MR) Password Key */ -/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */ -#define SUPC_WUMR_FWUPEN (0x1 << 0) /**< \brief (SUPC_WUMR) Force Wake Up Enable */ -#define SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0 << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin has no wake up effect. */ -#define SUPC_WUMR_FWUPEN_ENABLE (0x1 << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin low forces the wake up of the core power supply. */ -#define SUPC_WUMR_SMEN (0x1 << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */ -#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */ -#define SUPC_WUMR_SMEN_ENABLE (0x1 << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTTEN (0x1 << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */ -#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTTEN_ENABLE (0x1 << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_RTCEN (0x1 << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */ -#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */ -#define SUPC_WUMR_RTCEN_ENABLE (0x1 << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */ -#define SUPC_WUMR_FWUPDBC (0x7 << 8) /**< \brief (SUPC_WUMR) Force Wake Up Debouncer */ -#define SUPC_WUMR_FWUPDBC_1SCLK (0x0 << 8) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ -#define SUPC_WUMR_FWUPDBC_3SCLK (0x1 << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 3 SLCK periods */ -#define SUPC_WUMR_FWUPDBC_32SCLK (0x2 << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32 SLCK periods */ -#define SUPC_WUMR_FWUPDBC_512SCLK (0x3 << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 512 SLCK periods */ -#define SUPC_WUMR_FWUPDBC_4096SCLK (0x4 << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 4,096 SLCK periods */ -#define SUPC_WUMR_FWUPDBC_32768SCLK (0x5 << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32,768 SLCK periods */ -#define SUPC_WUMR_WKUPDBC (0x7 << 12) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer */ -#define SUPC_WUMR_WKUPDBC_1SCLK (0x0 << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ -#define SUPC_WUMR_WKUPDBC_3SCLK (0x1 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 3 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32SCLK (0x2 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_512SCLK (0x3 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 512 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_4096SCLK (0x4 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 4,096 SLCK periods */ -#define SUPC_WUMR_WKUPDBC_32768SCLK (0x5 << 12) /**< \brief (SUPC_WUMR) An enabled wake-up input shall be active for at least 32,768 SLCK periods */ -/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */ -#define SUPC_WUIR_WKUPEN0 (0x1 << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */ -#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN0_ENABLE (0x1 << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN1 (0x1 << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */ -#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN1_ENABLE (0x1 << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN2 (0x1 << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */ -#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN2_ENABLE (0x1 << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN3 (0x1 << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */ -#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN3_ENABLE (0x1 << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN4 (0x1 << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */ -#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN4_ENABLE (0x1 << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN5 (0x1 << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */ -#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN5_ENABLE (0x1 << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN6 (0x1 << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */ -#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN6_ENABLE (0x1 << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN7 (0x1 << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */ -#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN7_ENABLE (0x1 << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN8 (0x1 << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */ -#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN8_ENABLE (0x1 << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN9 (0x1 << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */ -#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN9_ENABLE (0x1 << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN10 (0x1 << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */ -#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN10_ENABLE (0x1 << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN11 (0x1 << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */ -#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN11_ENABLE (0x1 << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN12 (0x1 << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */ -#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN12_ENABLE (0x1 << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN13 (0x1 << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */ -#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN13_ENABLE (0x1 << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN14 (0x1 << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */ -#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN14_ENABLE (0x1 << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPEN15 (0x1 << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */ -#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ -#define SUPC_WUIR_WKUPEN15_ENABLE (0x1 << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0 (0x1 << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */ -#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0 << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1 << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1 (0x1 << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */ -#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0 << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1 << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2 (0x1 << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */ -#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0 << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1 << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3 (0x1 << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */ -#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0 << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1 << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4 (0x1 << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */ -#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0 << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1 << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5 (0x1 << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */ -#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0 << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1 << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6 (0x1 << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */ -#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0 << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1 << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7 (0x1 << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */ -#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0 << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1 << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8 (0x1 << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */ -#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0 << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1 << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9 (0x1 << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */ -#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0 << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1 << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10 (0x1 << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */ -#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0 << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1 << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11 (0x1 << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */ -#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0 << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1 << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12 (0x1 << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */ -#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0 << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1 << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13 (0x1 << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */ -#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0 << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1 << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14 (0x1 << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */ -#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0 << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1 << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15 (0x1 << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */ -#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0 << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1 << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */ -/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ -#define SUPC_SR_FWUPS (0x1 << 0) /**< \brief (SUPC_SR) FWUP Wake Up Status */ -#define SUPC_SR_FWUPS_NO (0x0 << 0) /**< \brief (SUPC_SR) no wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_FWUPS_PRESENT (0x1 << 0) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_WKUPS (0x1 << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */ -#define SUPC_SR_WKUPS_NO (0x0 << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_WKUPS_PRESENT (0x1 << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS (0x1 << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */ -#define SUPC_SR_SMWS_NO (0x0 << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_SMWS_PRESENT (0x1 << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ -#define SUPC_SR_BODRSTS (0x1 << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ -#define SUPC_SR_BODRSTS_NO (0x0 << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_BODRSTS_PRESENT (0x1 << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS (0x1 << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ -#define SUPC_SR_SMRSTS_NO (0x0 << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMRSTS_PRESENT (0x1 << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ -#define SUPC_SR_SMS (0x1 << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ -#define SUPC_SR_SMS_NO (0x0 << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMS_PRESENT (0x1 << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ -#define SUPC_SR_SMOS (0x1 << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ -#define SUPC_SR_SMOS_HIGH (0x0 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI higher than its threshold at its last measurement. */ -#define SUPC_SR_SMOS_LOW (0x1 << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI lower than its threshold at its last measurement. */ -#define SUPC_SR_OSCSEL (0x1 << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ -#define SUPC_SR_OSCSEL_RC (0x0 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ -#define SUPC_SR_OSCSEL_CRYST (0x1 << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ -#define SUPC_SR_FWUPIS (0x1 << 12) /**< \brief (SUPC_SR) FWUP Input Status */ -#define SUPC_SR_FWUPIS_LOW (0x0 << 12) /**< \brief (SUPC_SR) FWUP input is tied low. */ -#define SUPC_SR_FWUPIS_HIGH (0x1 << 12) /**< \brief (SUPC_SR) FWUP input is tied high. */ -#define SUPC_SR_WKUPIS0 (0x1 << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ -#define SUPC_SR_WKUPIS0_DIS (0x0 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS0_EN (0x1 << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1 (0x1 << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ -#define SUPC_SR_WKUPIS1_DIS (0x0 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS1_EN (0x1 << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2 (0x1 << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ -#define SUPC_SR_WKUPIS2_DIS (0x0 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS2_EN (0x1 << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3 (0x1 << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ -#define SUPC_SR_WKUPIS3_DIS (0x0 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS3_EN (0x1 << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4 (0x1 << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ -#define SUPC_SR_WKUPIS4_DIS (0x0 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS4_EN (0x1 << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5 (0x1 << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ -#define SUPC_SR_WKUPIS5_DIS (0x0 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS5_EN (0x1 << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6 (0x1 << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ -#define SUPC_SR_WKUPIS6_DIS (0x0 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS6_EN (0x1 << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7 (0x1 << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ -#define SUPC_SR_WKUPIS7_DIS (0x0 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS7_EN (0x1 << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8 (0x1 << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ -#define SUPC_SR_WKUPIS8_DIS (0x0 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS8_EN (0x1 << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9 (0x1 << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ -#define SUPC_SR_WKUPIS9_DIS (0x0 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS9_EN (0x1 << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10 (0x1 << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ -#define SUPC_SR_WKUPIS10_DIS (0x0 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS10_EN (0x1 << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11 (0x1 << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ -#define SUPC_SR_WKUPIS11_DIS (0x0 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS11_EN (0x1 << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12 (0x1 << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ -#define SUPC_SR_WKUPIS12_DIS (0x0 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS12_EN (0x1 << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13 (0x1 << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ -#define SUPC_SR_WKUPIS13_DIS (0x0 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS13_EN (0x1 << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14 (0x1 << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ -#define SUPC_SR_WKUPIS14_DIS (0x0 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS14_EN (0x1 << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15 (0x1 << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ -#define SUPC_SR_WKUPIS15_DIS (0x0 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ -#define SUPC_SR_WKUPIS15_EN (0x1 << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Timer Counter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_TC Timer Counter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief TcChannel hardware registers */ -typedef struct { - RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ - RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ - RwReg Reserved1[2]; - RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ - RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ - RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ - RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ - RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ - RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ - RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ - RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ - RwReg Reserved2[4]; -} TcChannel; -/** \brief Tc hardware registers */ -typedef struct { - TcChannel TC_CHANNEL[3]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ - WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ - RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ - WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ - WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ - RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ - RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ - RwReg Reserved1[9]; - RoReg TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ -} Tc; -#endif /* __ASSEMBLY__ */ -/* -------- TC_CCR0 : (TC Offset: 0x0) Channel Control Register (channel = 0) -------- */ -#define TC_CCR0_CLKEN (0x1 << 0) /**< \brief (TC_CCR0) Counter Clock Enable Command */ -#define TC_CCR0_CLKDIS (0x1 << 1) /**< \brief (TC_CCR0) Counter Clock Disable Command */ -#define TC_CCR0_SWTRG (0x1 << 2) /**< \brief (TC_CCR0) Software Trigger Command */ -/* -------- TC_CMR0 : (TC Offset: 0x4) Channel Mode Register (channel = 0) -------- */ -#define TC_CMR0_TCCLKS (0x7 << 0) /**< \brief (TC_CMR0) Clock Selection */ -#define TC_CMR0_CLKI (0x1 << 3) /**< \brief (TC_CMR0) Clock Invert */ -#define TC_CMR0_BURST (0x3 << 4) /**< \brief (TC_CMR0) Burst Signal Selection */ -#define TC_CMR0_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR0) The clock is not gated by an external signal. */ -#define TC_CMR0_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR0) XC0 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR0) XC1 is ANDed with the selected clock. */ -#define TC_CMR0_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR0) XC2 is ANDed with the selected clock. */ -#define TC_CMR0_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR0) Counter Clock Stopped with RB Loading */ -#define TC_CMR0_LDBDIS (0x1 << 7) /**< \brief (TC_CMR0) Counter Clock Disable with RB Loading */ -#define TC_CMR0_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR0) External Trigger Edge Selection */ -#define TC_CMR0_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR0) rising edge */ -#define TC_CMR0_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR0) falling edge */ -#define TC_CMR0_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR0) each edge */ -#define TC_CMR0_ABETRG (0x1 << 10) /**< \brief (TC_CMR0) TIOA or TIOB External Trigger Selection */ -#define TC_CMR0_CPCTRG (0x1 << 14) /**< \brief (TC_CMR0) RC Compare Trigger Enable */ -#define TC_CMR0_WAVE (0x1 << 15) /**< \brief (TC_CMR0) */ -#define TC_CMR0_LDRA (0x3 << 16) /**< \brief (TC_CMR0) RA Loading Selection */ -#define TC_CMR0_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR0) each edge of TIOA */ -#define TC_CMR0_LDRB (0x3 << 18) /**< \brief (TC_CMR0) RB Loading Selection */ -#define TC_CMR0_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR0) none */ -#define TC_CMR0_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR0) rising edge of TIOA */ -#define TC_CMR0_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR0) falling edge of TIOA */ -#define TC_CMR0_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR0) each edge of TIOA */ -/* -------- TC_CV0 : (TC Offset: 0x10) Counter Value (channel = 0) -------- */ -#define TC_CV0_CV (0xffff << 0) /**< \brief (TC_CV0) Counter Value */ -/* -------- TC_RA0 : (TC Offset: 0x14) Register A (channel = 0) -------- */ -#define TC_RA0_RA (0xffff << 0) /**< \brief (TC_RA0) Register A */ -/* -------- TC_RB0 : (TC Offset: 0x18) Register B (channel = 0) -------- */ -#define TC_RB0_RB (0xffff << 0) /**< \brief (TC_RB0) Register B */ -/* -------- TC_RC0 : (TC Offset: 0x1C) Register C (channel = 0) -------- */ -#define TC_RC0_RC (0xffff << 0) /**< \brief (TC_RC0) Register C */ -/* -------- TC_SR0 : (TC Offset: 0x20) Status Register (channel = 0) -------- */ -#define TC_SR0_COVFS (0x1 << 0) /**< \brief (TC_SR0) Counter Overflow Status */ -#define TC_SR0_LOVRS (0x1 << 1) /**< \brief (TC_SR0) Load Overrun Status */ -#define TC_SR0_CPAS (0x1 << 2) /**< \brief (TC_SR0) RA Compare Status */ -#define TC_SR0_CPBS (0x1 << 3) /**< \brief (TC_SR0) RB Compare Status */ -#define TC_SR0_CPCS (0x1 << 4) /**< \brief (TC_SR0) RC Compare Status */ -#define TC_SR0_LDRAS (0x1 << 5) /**< \brief (TC_SR0) RA Loading Status */ -#define TC_SR0_LDRBS (0x1 << 6) /**< \brief (TC_SR0) RB Loading Status */ -#define TC_SR0_ETRGS (0x1 << 7) /**< \brief (TC_SR0) External Trigger Status */ -#define TC_SR0_CLKSTA (0x1 << 16) /**< \brief (TC_SR0) Clock Enabling Status */ -#define TC_SR0_MTIOA (0x1 << 17) /**< \brief (TC_SR0) TIOA Mirror */ -#define TC_SR0_MTIOB (0x1 << 18) /**< \brief (TC_SR0) TIOB Mirror */ -/* -------- TC_IER0 : (TC Offset: 0x24) Interrupt Enable Register (channel = 0) -------- */ -#define TC_IER0_COVFS (0x1 << 0) /**< \brief (TC_IER0) Counter Overflow */ -#define TC_IER0_LOVRS (0x1 << 1) /**< \brief (TC_IER0) Load Overrun */ -#define TC_IER0_CPAS (0x1 << 2) /**< \brief (TC_IER0) RA Compare */ -#define TC_IER0_CPBS (0x1 << 3) /**< \brief (TC_IER0) RB Compare */ -#define TC_IER0_CPCS (0x1 << 4) /**< \brief (TC_IER0) RC Compare */ -#define TC_IER0_LDRAS (0x1 << 5) /**< \brief (TC_IER0) RA Loading */ -#define TC_IER0_LDRBS (0x1 << 6) /**< \brief (TC_IER0) RB Loading */ -#define TC_IER0_ETRGS (0x1 << 7) /**< \brief (TC_IER0) External Trigger */ -/* -------- TC_IDR0 : (TC Offset: 0x28) Interrupt Disable Register (channel = 0) -------- */ -#define TC_IDR0_COVFS (0x1 << 0) /**< \brief (TC_IDR0) Counter Overflow */ -#define TC_IDR0_LOVRS (0x1 << 1) /**< \brief (TC_IDR0) Load Overrun */ -#define TC_IDR0_CPAS (0x1 << 2) /**< \brief (TC_IDR0) RA Compare */ -#define TC_IDR0_CPBS (0x1 << 3) /**< \brief (TC_IDR0) RB Compare */ -#define TC_IDR0_CPCS (0x1 << 4) /**< \brief (TC_IDR0) RC Compare */ -#define TC_IDR0_LDRAS (0x1 << 5) /**< \brief (TC_IDR0) RA Loading */ -#define TC_IDR0_LDRBS (0x1 << 6) /**< \brief (TC_IDR0) RB Loading */ -#define TC_IDR0_ETRGS (0x1 << 7) /**< \brief (TC_IDR0) External Trigger */ -/* -------- TC_IMR0 : (TC Offset: 0x2C) Interrupt Mask Register (channel = 0) -------- */ -#define TC_IMR0_COVFS (0x1 << 0) /**< \brief (TC_IMR0) Counter Overflow */ -#define TC_IMR0_LOVRS (0x1 << 1) /**< \brief (TC_IMR0) Load Overrun */ -#define TC_IMR0_CPAS (0x1 << 2) /**< \brief (TC_IMR0) RA Compare */ -#define TC_IMR0_CPBS (0x1 << 3) /**< \brief (TC_IMR0) RB Compare */ -#define TC_IMR0_CPCS (0x1 << 4) /**< \brief (TC_IMR0) RC Compare */ -#define TC_IMR0_LDRAS (0x1 << 5) /**< \brief (TC_IMR0) RA Loading */ -#define TC_IMR0_LDRBS (0x1 << 6) /**< \brief (TC_IMR0) RB Loading */ -#define TC_IMR0_ETRGS (0x1 << 7) /**< \brief (TC_IMR0) External Trigger */ -/* -------- TC_CCR1 : (TC Offset: 0x40) Channel Control Register (channel = 1) -------- */ -#define TC_CCR1_CLKEN (0x1 << 0) /**< \brief (TC_CCR1) Counter Clock Enable Command */ -#define TC_CCR1_CLKDIS (0x1 << 1) /**< \brief (TC_CCR1) Counter Clock Disable Command */ -#define TC_CCR1_SWTRG (0x1 << 2) /**< \brief (TC_CCR1) Software Trigger Command */ -/* -------- TC_CMR1 : (TC Offset: 0x44) Channel Mode Register (channel = 1) -------- */ -#define TC_CMR1_TCCLKS (0x7 << 0) /**< \brief (TC_CMR1) Clock Selection */ -#define TC_CMR1_CLKI (0x1 << 3) /**< \brief (TC_CMR1) Clock Invert */ -#define TC_CMR1_BURST (0x3 << 4) /**< \brief (TC_CMR1) Burst Signal Selection */ -#define TC_CMR1_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR1) The clock is not gated by an external signal. */ -#define TC_CMR1_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR1) XC0 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR1) XC1 is ANDed with the selected clock. */ -#define TC_CMR1_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR1) XC2 is ANDed with the selected clock. */ -#define TC_CMR1_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR1) Counter Clock Stopped with RB Loading */ -#define TC_CMR1_LDBDIS (0x1 << 7) /**< \brief (TC_CMR1) Counter Clock Disable with RB Loading */ -#define TC_CMR1_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR1) External Trigger Edge Selection */ -#define TC_CMR1_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR1) rising edge */ -#define TC_CMR1_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR1) falling edge */ -#define TC_CMR1_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR1) each edge */ -#define TC_CMR1_ABETRG (0x1 << 10) /**< \brief (TC_CMR1) TIOA or TIOB External Trigger Selection */ -#define TC_CMR1_CPCTRG (0x1 << 14) /**< \brief (TC_CMR1) RC Compare Trigger Enable */ -#define TC_CMR1_WAVE (0x1 << 15) /**< \brief (TC_CMR1) */ -#define TC_CMR1_LDRA (0x3 << 16) /**< \brief (TC_CMR1) RA Loading Selection */ -#define TC_CMR1_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR1) each edge of TIOA */ -#define TC_CMR1_LDRB (0x3 << 18) /**< \brief (TC_CMR1) RB Loading Selection */ -#define TC_CMR1_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR1) none */ -#define TC_CMR1_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR1) rising edge of TIOA */ -#define TC_CMR1_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR1) falling edge of TIOA */ -#define TC_CMR1_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR1) each edge of TIOA */ -/* -------- TC_CV1 : (TC Offset: 0x50) Counter Value (channel = 1) -------- */ -#define TC_CV1_CV (0xffff << 0) /**< \brief (TC_CV1) Counter Value */ -/* -------- TC_RA1 : (TC Offset: 0x54) Register A (channel = 1) -------- */ -#define TC_RA1_RA (0xffff << 0) /**< \brief (TC_RA1) Register A */ -/* -------- TC_RB1 : (TC Offset: 0x58) Register B (channel = 1) -------- */ -#define TC_RB1_RB (0xffff << 0) /**< \brief (TC_RB1) Register B */ -/* -------- TC_RC1 : (TC Offset: 0x5C) Register C (channel = 1) -------- */ -#define TC_RC1_RC (0xffff << 0) /**< \brief (TC_RC1) Register C */ -/* -------- TC_SR1 : (TC Offset: 0x60) Status Register (channel = 1) -------- */ -#define TC_SR1_COVFS (0x1 << 0) /**< \brief (TC_SR1) Counter Overflow Status */ -#define TC_SR1_LOVRS (0x1 << 1) /**< \brief (TC_SR1) Load Overrun Status */ -#define TC_SR1_CPAS (0x1 << 2) /**< \brief (TC_SR1) RA Compare Status */ -#define TC_SR1_CPBS (0x1 << 3) /**< \brief (TC_SR1) RB Compare Status */ -#define TC_SR1_CPCS (0x1 << 4) /**< \brief (TC_SR1) RC Compare Status */ -#define TC_SR1_LDRAS (0x1 << 5) /**< \brief (TC_SR1) RA Loading Status */ -#define TC_SR1_LDRBS (0x1 << 6) /**< \brief (TC_SR1) RB Loading Status */ -#define TC_SR1_ETRGS (0x1 << 7) /**< \brief (TC_SR1) External Trigger Status */ -#define TC_SR1_CLKSTA (0x1 << 16) /**< \brief (TC_SR1) Clock Enabling Status */ -#define TC_SR1_MTIOA (0x1 << 17) /**< \brief (TC_SR1) TIOA Mirror */ -#define TC_SR1_MTIOB (0x1 << 18) /**< \brief (TC_SR1) TIOB Mirror */ -/* -------- TC_IER1 : (TC Offset: 0x64) Interrupt Enable Register (channel = 1) -------- */ -#define TC_IER1_COVFS (0x1 << 0) /**< \brief (TC_IER1) Counter Overflow */ -#define TC_IER1_LOVRS (0x1 << 1) /**< \brief (TC_IER1) Load Overrun */ -#define TC_IER1_CPAS (0x1 << 2) /**< \brief (TC_IER1) RA Compare */ -#define TC_IER1_CPBS (0x1 << 3) /**< \brief (TC_IER1) RB Compare */ -#define TC_IER1_CPCS (0x1 << 4) /**< \brief (TC_IER1) RC Compare */ -#define TC_IER1_LDRAS (0x1 << 5) /**< \brief (TC_IER1) RA Loading */ -#define TC_IER1_LDRBS (0x1 << 6) /**< \brief (TC_IER1) RB Loading */ -#define TC_IER1_ETRGS (0x1 << 7) /**< \brief (TC_IER1) External Trigger */ -/* -------- TC_IDR1 : (TC Offset: 0x68) Interrupt Disable Register (channel = 1) -------- */ -#define TC_IDR1_COVFS (0x1 << 0) /**< \brief (TC_IDR1) Counter Overflow */ -#define TC_IDR1_LOVRS (0x1 << 1) /**< \brief (TC_IDR1) Load Overrun */ -#define TC_IDR1_CPAS (0x1 << 2) /**< \brief (TC_IDR1) RA Compare */ -#define TC_IDR1_CPBS (0x1 << 3) /**< \brief (TC_IDR1) RB Compare */ -#define TC_IDR1_CPCS (0x1 << 4) /**< \brief (TC_IDR1) RC Compare */ -#define TC_IDR1_LDRAS (0x1 << 5) /**< \brief (TC_IDR1) RA Loading */ -#define TC_IDR1_LDRBS (0x1 << 6) /**< \brief (TC_IDR1) RB Loading */ -#define TC_IDR1_ETRGS (0x1 << 7) /**< \brief (TC_IDR1) External Trigger */ -/* -------- TC_IMR1 : (TC Offset: 0x6C) Interrupt Mask Register (channel = 1) -------- */ -#define TC_IMR1_COVFS (0x1 << 0) /**< \brief (TC_IMR1) Counter Overflow */ -#define TC_IMR1_LOVRS (0x1 << 1) /**< \brief (TC_IMR1) Load Overrun */ -#define TC_IMR1_CPAS (0x1 << 2) /**< \brief (TC_IMR1) RA Compare */ -#define TC_IMR1_CPBS (0x1 << 3) /**< \brief (TC_IMR1) RB Compare */ -#define TC_IMR1_CPCS (0x1 << 4) /**< \brief (TC_IMR1) RC Compare */ -#define TC_IMR1_LDRAS (0x1 << 5) /**< \brief (TC_IMR1) RA Loading */ -#define TC_IMR1_LDRBS (0x1 << 6) /**< \brief (TC_IMR1) RB Loading */ -#define TC_IMR1_ETRGS (0x1 << 7) /**< \brief (TC_IMR1) External Trigger */ -/* -------- TC_CCR2 : (TC Offset: 0x80) Channel Control Register (channel = 2) -------- */ -#define TC_CCR2_CLKEN (0x1 << 0) /**< \brief (TC_CCR2) Counter Clock Enable Command */ -#define TC_CCR2_CLKDIS (0x1 << 1) /**< \brief (TC_CCR2) Counter Clock Disable Command */ -#define TC_CCR2_SWTRG (0x1 << 2) /**< \brief (TC_CCR2) Software Trigger Command */ -/* -------- TC_CMR2 : (TC Offset: 0x84) Channel Mode Register (channel = 2) -------- */ -#define TC_CMR2_TCCLKS (0x7 << 0) /**< \brief (TC_CMR2) Clock Selection */ -#define TC_CMR2_CLKI (0x1 << 3) /**< \brief (TC_CMR2) Clock Invert */ -#define TC_CMR2_BURST (0x3 << 4) /**< \brief (TC_CMR2) Burst Signal Selection */ -#define TC_CMR2_BURST_NONE (0x0 << 4) /**< \brief (TC_CMR2) The clock is not gated by an external signal. */ -#define TC_CMR2_BURST_XC0 (0x1 << 4) /**< \brief (TC_CMR2) XC0 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC1 (0x2 << 4) /**< \brief (TC_CMR2) XC1 is ANDed with the selected clock. */ -#define TC_CMR2_BURST_XC2 (0x3 << 4) /**< \brief (TC_CMR2) XC2 is ANDed with the selected clock. */ -#define TC_CMR2_LDBSTOP (0x1 << 6) /**< \brief (TC_CMR2) Counter Clock Stopped with RB Loading */ -#define TC_CMR2_LDBDIS (0x1 << 7) /**< \brief (TC_CMR2) Counter Clock Disable with RB Loading */ -#define TC_CMR2_ETRGEDG (0x3 << 8) /**< \brief (TC_CMR2) External Trigger Edge Selection */ -#define TC_CMR2_ETRGEDG_NONE (0x0 << 8) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_ETRGEDG_RISING (0x1 << 8) /**< \brief (TC_CMR2) rising edge */ -#define TC_CMR2_ETRGEDG_FALLING (0x2 << 8) /**< \brief (TC_CMR2) falling edge */ -#define TC_CMR2_ETRGEDG_BOTH (0x3 << 8) /**< \brief (TC_CMR2) each edge */ -#define TC_CMR2_ABETRG (0x1 << 10) /**< \brief (TC_CMR2) TIOA or TIOB External Trigger Selection */ -#define TC_CMR2_CPCTRG (0x1 << 14) /**< \brief (TC_CMR2) RC Compare Trigger Enable */ -#define TC_CMR2_WAVE (0x1 << 15) /**< \brief (TC_CMR2) */ -#define TC_CMR2_LDRA (0x3 << 16) /**< \brief (TC_CMR2) RA Loading Selection */ -#define TC_CMR2_LDRA_NONE (0x0 << 16) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRA_RISING (0x1 << 16) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRA_FALLING (0x2 << 16) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRA_BOTH (0x3 << 16) /**< \brief (TC_CMR2) each edge of TIOA */ -#define TC_CMR2_LDRB (0x3 << 18) /**< \brief (TC_CMR2) RB Loading Selection */ -#define TC_CMR2_LDRB_NONE (0x0 << 18) /**< \brief (TC_CMR2) none */ -#define TC_CMR2_LDRB_RISING (0x1 << 18) /**< \brief (TC_CMR2) rising edge of TIOA */ -#define TC_CMR2_LDRB_FALLING (0x2 << 18) /**< \brief (TC_CMR2) falling edge of TIOA */ -#define TC_CMR2_LDRB_BOTH (0x3 << 18) /**< \brief (TC_CMR2) each edge of TIOA */ -/* -------- TC_CV2 : (TC Offset: 0x90) Counter Value (channel = 2) -------- */ -#define TC_CV2_CV (0xffff << 0) /**< \brief (TC_CV2) Counter Value */ -/* -------- TC_RA2 : (TC Offset: 0x94) Register A (channel = 2) -------- */ -#define TC_RA2_RA (0xffff << 0) /**< \brief (TC_RA2) Register A */ -/* -------- TC_RB2 : (TC Offset: 0x98) Register B (channel = 2) -------- */ -#define TC_RB2_RB (0xffff << 0) /**< \brief (TC_RB2) Register B */ -/* -------- TC_RC2 : (TC Offset: 0x9C) Register C (channel = 2) -------- */ -#define TC_RC2_RC (0xffff << 0) /**< \brief (TC_RC2) Register C */ -/* -------- TC_SR2 : (TC Offset: 0xA0) Status Register (channel = 2) -------- */ -#define TC_SR2_COVFS (0x1 << 0) /**< \brief (TC_SR2) Counter Overflow Status */ -#define TC_SR2_LOVRS (0x1 << 1) /**< \brief (TC_SR2) Load Overrun Status */ -#define TC_SR2_CPAS (0x1 << 2) /**< \brief (TC_SR2) RA Compare Status */ -#define TC_SR2_CPBS (0x1 << 3) /**< \brief (TC_SR2) RB Compare Status */ -#define TC_SR2_CPCS (0x1 << 4) /**< \brief (TC_SR2) RC Compare Status */ -#define TC_SR2_LDRAS (0x1 << 5) /**< \brief (TC_SR2) RA Loading Status */ -#define TC_SR2_LDRBS (0x1 << 6) /**< \brief (TC_SR2) RB Loading Status */ -#define TC_SR2_ETRGS (0x1 << 7) /**< \brief (TC_SR2) External Trigger Status */ -#define TC_SR2_CLKSTA (0x1 << 16) /**< \brief (TC_SR2) Clock Enabling Status */ -#define TC_SR2_MTIOA (0x1 << 17) /**< \brief (TC_SR2) TIOA Mirror */ -#define TC_SR2_MTIOB (0x1 << 18) /**< \brief (TC_SR2) TIOB Mirror */ -/* -------- TC_IER2 : (TC Offset: 0xA4) Interrupt Enable Register (channel = 2) -------- */ -#define TC_IER2_COVFS (0x1 << 0) /**< \brief (TC_IER2) Counter Overflow */ -#define TC_IER2_LOVRS (0x1 << 1) /**< \brief (TC_IER2) Load Overrun */ -#define TC_IER2_CPAS (0x1 << 2) /**< \brief (TC_IER2) RA Compare */ -#define TC_IER2_CPBS (0x1 << 3) /**< \brief (TC_IER2) RB Compare */ -#define TC_IER2_CPCS (0x1 << 4) /**< \brief (TC_IER2) RC Compare */ -#define TC_IER2_LDRAS (0x1 << 5) /**< \brief (TC_IER2) RA Loading */ -#define TC_IER2_LDRBS (0x1 << 6) /**< \brief (TC_IER2) RB Loading */ -#define TC_IER2_ETRGS (0x1 << 7) /**< \brief (TC_IER2) External Trigger */ -/* -------- TC_IDR2 : (TC Offset: 0xA8) Interrupt Disable Register (channel = 2) -------- */ -#define TC_IDR2_COVFS (0x1 << 0) /**< \brief (TC_IDR2) Counter Overflow */ -#define TC_IDR2_LOVRS (0x1 << 1) /**< \brief (TC_IDR2) Load Overrun */ -#define TC_IDR2_CPAS (0x1 << 2) /**< \brief (TC_IDR2) RA Compare */ -#define TC_IDR2_CPBS (0x1 << 3) /**< \brief (TC_IDR2) RB Compare */ -#define TC_IDR2_CPCS (0x1 << 4) /**< \brief (TC_IDR2) RC Compare */ -#define TC_IDR2_LDRAS (0x1 << 5) /**< \brief (TC_IDR2) RA Loading */ -#define TC_IDR2_LDRBS (0x1 << 6) /**< \brief (TC_IDR2) RB Loading */ -#define TC_IDR2_ETRGS (0x1 << 7) /**< \brief (TC_IDR2) External Trigger */ -/* -------- TC_IMR2 : (TC Offset: 0xAC) Interrupt Mask Register (channel = 2) -------- */ -#define TC_IMR2_COVFS (0x1 << 0) /**< \brief (TC_IMR2) Counter Overflow */ -#define TC_IMR2_LOVRS (0x1 << 1) /**< \brief (TC_IMR2) Load Overrun */ -#define TC_IMR2_CPAS (0x1 << 2) /**< \brief (TC_IMR2) RA Compare */ -#define TC_IMR2_CPBS (0x1 << 3) /**< \brief (TC_IMR2) RB Compare */ -#define TC_IMR2_CPCS (0x1 << 4) /**< \brief (TC_IMR2) RC Compare */ -#define TC_IMR2_LDRAS (0x1 << 5) /**< \brief (TC_IMR2) RA Loading */ -#define TC_IMR2_LDRBS (0x1 << 6) /**< \brief (TC_IMR2) RB Loading */ -#define TC_IMR2_ETRGS (0x1 << 7) /**< \brief (TC_IMR2) External Trigger */ -/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ -#define TC_BCR_SYNC (0x1 << 0) /**< \brief (TC_BCR) Synchro Command */ -/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ -#define TC_BMR_TC0XC0S (0x3 << 0) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ -#define TC_BMR_TC0XC0S_TCLK0 (0x0 << 0) /**< \brief (TC_BMR) TCLK0 */ -#define TC_BMR_TC0XC0S_NONE (0x1 << 0) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC0XC0S_TIOA1 (0x2 << 0) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_TC0XC0S_TIOA2 (0x3 << 0) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC1XC1S (0x3 << 2) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ -#define TC_BMR_TC1XC1S_TCLK1 (0x0 << 2) /**< \brief (TC_BMR) TCLK1 */ -#define TC_BMR_TC1XC1S_NONE (0x1 << 2) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC1XC1S_TIOA0 (0x2 << 2) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC1XC1S_TIOA2 (0x3 << 2) /**< \brief (TC_BMR) TIOA2 */ -#define TC_BMR_TC2XC2S (0x3 << 4) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ -#define TC_BMR_TC2XC2S_TCLK2 (0x0 << 4) /**< \brief (TC_BMR) TCLK2 */ -#define TC_BMR_TC2XC2S_NONE (0x1 << 4) /**< \brief (TC_BMR) none */ -#define TC_BMR_TC2XC2S_TIOA0 (0x2 << 4) /**< \brief (TC_BMR) TIOA0 */ -#define TC_BMR_TC2XC2S_TIOA1 (0x3 << 4) /**< \brief (TC_BMR) TIOA1 */ -#define TC_BMR_QDEN (0x1 << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ -#define TC_BMR_POSEN (0x1 << 9) /**< \brief (TC_BMR) POSition ENabled */ -#define TC_BMR_SPEEDEN (0x1 << 10) /**< \brief (TC_BMR) SPEED ENabled */ -#define TC_BMR_QDTRANS (0x1 << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ -#define TC_BMR_EDGPHA (0x1 << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ -#define TC_BMR_INVA (0x1 << 13) /**< \brief (TC_BMR) INVerted phA */ -#define TC_BMR_INVB (0x1 << 14) /**< \brief (TC_BMR) INVerted phB */ -#define TC_BMR_INVIDX (0x1 << 15) /**< \brief (TC_BMR) INVerted InDeX */ -#define TC_BMR_SWAP (0x1 << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ -#define TC_BMR_IDXPHB (0x1 << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ -#define TC_BMR_FILTER (0x1 << 19) /**< \brief (TC_BMR) */ -#define TC_BMR_MAXFILT (0x3f << 20) /**< \brief (TC_BMR) MAXimum FILTer */ -/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ -#define TC_QIER_IDX (0x1 << 0) /**< \brief (TC_QIER) InDeX */ -#define TC_QIER_DIRCHG (0x1 << 1) /**< \brief (TC_QIER) DIRection CHanGe */ -#define TC_QIER_QERR (0x1 << 2) /**< \brief (TC_QIER) Quadrature ERRor */ -/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ -#define TC_QIDR_IDX (0x1 << 0) /**< \brief (TC_QIDR) InDeX */ -#define TC_QIDR_DIRCHG (0x1 << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ -#define TC_QIDR_QERR (0x1 << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ -/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ -#define TC_QIMR_IDX (0x1 << 0) /**< \brief (TC_QIMR) InDeX */ -#define TC_QIMR_DIRCHG (0x1 << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ -#define TC_QIMR_QERR (0x1 << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ -/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ -#define TC_QISR_IDX (0x1 << 0) /**< \brief (TC_QISR) InDeX */ -#define TC_QISR_DIRCHG (0x1 << 1) /**< \brief (TC_QISR) DIRection CHanGe */ -#define TC_QISR_QERR (0x1 << 2) /**< \brief (TC_QISR) Quadrature ERRor */ -#define TC_QISR_DIR (0x1 << 8) /**< \brief (TC_QISR) Direction */ -/* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ -#define TC_VER_VERSION (0xfff << 0) /**< \brief (TC_VER) */ -#define TC_VER_MFN (0x7 << 16) /**< \brief (TC_VER) */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Two-wire Interface */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_TWI Two-wire Interface */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Twi hardware registers */ -typedef struct { - WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ - RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ - RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ - RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ - RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ - RwReg Reserved1[3]; - RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ - WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ - WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ - RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ - RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ - WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ - RwReg Reserved2[50]; - RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ - RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ - RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ - RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ - RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ - RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ - RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ - RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ - WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ - RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ -} Twi; -#endif /* __ASSEMBLY__ */ -/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ -#define TWI_CR_START (0x1 << 0) /**< \brief (TWI_CR) Send a START Condition */ -#define TWI_CR_STOP (0x1 << 1) /**< \brief (TWI_CR) Send a STOP Condition */ -#define TWI_CR_MSEN (0x1 << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ -#define TWI_CR_MSDIS (0x1 << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ -#define TWI_CR_SVEN (0x1 << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ -#define TWI_CR_SVDIS (0x1 << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ -#define TWI_CR_QUICK (0x1 << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ -#define TWI_CR_SWRST (0x1 << 7) /**< \brief (TWI_CR) Software Reset */ -/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ -#define TWI_MMR_IADRSZ (0x3 << 8) /**< \brief (TWI_MMR) Internal Device Address Size */ -#define TWI_MMR_IADRSZ_NO (0x0 << 8) /**< \brief (TWI_MMR) No internal device address */ -#define TWI_MMR_IADRSZ_1_BYTE (0x1 << 8) /**< \brief (TWI_MMR) One-byte internal device address */ -#define TWI_MMR_IADRSZ_2_BYTE (0x2 << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ -#define TWI_MMR_IADRSZ_3_BYTE (0x3 << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ -#define TWI_MMR_MREAD (0x1 << 12) /**< \brief (TWI_MMR) Master Read Direction */ -#define TWI_MMR_DADR (0x7f << 16) /**< \brief (TWI_MMR) Device Address */ -/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ -#define TWI_SMR_SADR (0x7f << 16) /**< \brief (TWI_SMR) Slave Address */ -/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ -#define TWI_IADR_IADR (0xffffff << 0) /**< \brief (TWI_IADR) Internal Address */ -/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ -#define TWI_CWGR_CLDIV (0xff << 0) /**< \brief (TWI_CWGR) Clock Low Divider */ -#define TWI_CWGR_CHDIV (0xff << 8) /**< \brief (TWI_CWGR) Clock High Divider */ -#define TWI_CWGR_CKDIV (0x7 << 16) /**< \brief (TWI_CWGR) Clock Divider */ -/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ -#define TWI_SR_TXCOMP (0x1 << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ -#define TWI_SR_RXRDY (0x1 << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ -#define TWI_SR_TXRDY (0x1 << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ -#define TWI_SR_SVREAD (0x1 << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ -#define TWI_SR_SVACC (0x1 << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ -#define TWI_SR_GACC (0x1 << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ -#define TWI_SR_OVRE (0x1 << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ -#define TWI_SR_NACK (0x1 << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ -#define TWI_SR_ARBLST (0x1 << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ -#define TWI_SR_SCLWS (0x1 << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ -#define TWI_SR_EOSACC (0x1 << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ -#define TWI_SR_ENDRX (0x1 << 12) /**< \brief (TWI_SR) End of RX buffer */ -#define TWI_SR_ENDTX (0x1 << 13) /**< \brief (TWI_SR) End of TX buffer */ -#define TWI_SR_RXBUFF (0x1 << 14) /**< \brief (TWI_SR) RX Buffer Full */ -#define TWI_SR_TXBUFE (0x1 << 15) /**< \brief (TWI_SR) TX Buffer Empty */ -/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ -#define TWI_IER_TXCOMP (0x1 << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ -#define TWI_IER_RXRDY (0x1 << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ -#define TWI_IER_TXRDY (0x1 << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ -#define TWI_IER_SVACC (0x1 << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ -#define TWI_IER_GACC (0x1 << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ -#define TWI_IER_OVRE (0x1 << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ -#define TWI_IER_NACK (0x1 << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ -#define TWI_IER_ARBLST (0x1 << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ -#define TWI_IER_SCL_WS (0x1 << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ -#define TWI_IER_EOSACC (0x1 << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ -#define TWI_IER_ENDRX (0x1 << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ -#define TWI_IER_ENDTX (0x1 << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ -#define TWI_IER_RXBUFF (0x1 << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ -#define TWI_IER_TXBUFE (0x1 << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ -/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ -#define TWI_IDR_TXCOMP (0x1 << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ -#define TWI_IDR_RXRDY (0x1 << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ -#define TWI_IDR_TXRDY (0x1 << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ -#define TWI_IDR_SVACC (0x1 << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ -#define TWI_IDR_GACC (0x1 << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ -#define TWI_IDR_OVRE (0x1 << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ -#define TWI_IDR_NACK (0x1 << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ -#define TWI_IDR_ARBLST (0x1 << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ -#define TWI_IDR_SCL_WS (0x1 << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ -#define TWI_IDR_EOSACC (0x1 << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ -#define TWI_IDR_ENDRX (0x1 << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ -#define TWI_IDR_ENDTX (0x1 << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ -#define TWI_IDR_RXBUFF (0x1 << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ -#define TWI_IDR_TXBUFE (0x1 << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ -/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ -#define TWI_IMR_TXCOMP (0x1 << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ -#define TWI_IMR_RXRDY (0x1 << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ -#define TWI_IMR_TXRDY (0x1 << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ -#define TWI_IMR_SVACC (0x1 << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ -#define TWI_IMR_GACC (0x1 << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ -#define TWI_IMR_OVRE (0x1 << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ -#define TWI_IMR_NACK (0x1 << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ -#define TWI_IMR_ARBLST (0x1 << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ -#define TWI_IMR_SCL_WS (0x1 << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ -#define TWI_IMR_EOSACC (0x1 << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ -#define TWI_IMR_ENDRX (0x1 << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ -#define TWI_IMR_ENDTX (0x1 << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ -#define TWI_IMR_RXBUFF (0x1 << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ -#define TWI_IMR_TXBUFE (0x1 << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ -/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ -#define TWI_RHR_RXDATA (0xff << 0) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ -/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ -#define TWI_THR_TXDATA (0xff << 0) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ -/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ -#define TWI_RPR_RXPTR (0xffffffff << 0) /**< \brief (TWI_RPR) Receive Pointer Register */ -/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ -#define TWI_RCR_RXCTR (0xffff << 0) /**< \brief (TWI_RCR) Receive Counter Register */ -/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ -#define TWI_TPR_TXPTR (0xffffffff << 0) /**< \brief (TWI_TPR) Transmit Counter Register */ -/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ -#define TWI_TCR_TXCTR (0xffff << 0) /**< \brief (TWI_TCR) Transmit Counter Register */ -/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ -#define TWI_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (TWI_RNPR) Receive Next Pointer */ -/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ -#define TWI_RNCR_RXNCTR (0xffff << 0) /**< \brief (TWI_RNCR) Receive Next Counter */ -/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ -#define TWI_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (TWI_TNPR) Transmit Next Pointer */ -/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ -#define TWI_TNCR_TXNCTR (0xffff << 0) /**< \brief (TWI_TNCR) Transmit Counter Next */ -/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ -#define TWI_PTCR_RXTEN (0x1 << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ -#define TWI_PTCR_RXTDIS (0x1 << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ -#define TWI_PTCR_TXTEN (0x1 << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ -#define TWI_PTCR_TXTDIS (0x1 << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ -/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ -#define TWI_PTSR_RXTEN (0x1 << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ -#define TWI_PTSR_TXTEN (0x1 << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_UART Universal Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Uart hardware registers */ -typedef struct { - WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ - RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ - WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ - WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ - RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ - RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ - RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ - WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ - RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ - RwReg Reserved1[55]; - RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ - RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ - RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ - RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ - RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ - RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ - RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ - RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ - WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ - RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ -} Uart; -#endif /* __ASSEMBLY__ */ -/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ -#define UART_CR_RSTRX (0x1 << 2) /**< \brief (UART_CR) Reset Receiver */ -#define UART_CR_RSTTX (0x1 << 3) /**< \brief (UART_CR) Reset Transmitter */ -#define UART_CR_RXEN (0x1 << 4) /**< \brief (UART_CR) Receiver Enable */ -#define UART_CR_RXDIS (0x1 << 5) /**< \brief (UART_CR) Receiver Disable */ -#define UART_CR_TXEN (0x1 << 6) /**< \brief (UART_CR) Transmitter Enable */ -#define UART_CR_TXDIS (0x1 << 7) /**< \brief (UART_CR) Transmitter Disable */ -#define UART_CR_RSTSTA (0x1 << 8) /**< \brief (UART_CR) Reset Status Bits */ -/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ -#define UART_MR_PAR (0x7 << 9) /**< \brief (UART_MR) Parity Type */ -#define UART_MR_CHMODE (0x3 << 14) /**< \brief (UART_MR) Channel Mode */ -/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ -#define UART_IER_RXRDY (0x1 << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ -#define UART_IER_TXRDY (0x1 << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ -#define UART_IER_ENDRX (0x1 << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ -#define UART_IER_ENDTX (0x1 << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ -#define UART_IER_OVRE (0x1 << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ -#define UART_IER_FRAME (0x1 << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ -#define UART_IER_PARE (0x1 << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ -#define UART_IER_TXEMPTY (0x1 << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ -#define UART_IER_TXBUFE (0x1 << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ -#define UART_IER_RXBUFF (0x1 << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ -/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ -#define UART_IDR_RXRDY (0x1 << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ -#define UART_IDR_TXRDY (0x1 << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ -#define UART_IDR_ENDRX (0x1 << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ -#define UART_IDR_ENDTX (0x1 << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ -#define UART_IDR_OVRE (0x1 << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ -#define UART_IDR_FRAME (0x1 << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ -#define UART_IDR_PARE (0x1 << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ -#define UART_IDR_TXEMPTY (0x1 << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ -#define UART_IDR_TXBUFE (0x1 << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ -#define UART_IDR_RXBUFF (0x1 << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ -/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ -#define UART_IMR_RXRDY (0x1 << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ -#define UART_IMR_TXRDY (0x1 << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ -#define UART_IMR_ENDRX (0x1 << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ -#define UART_IMR_ENDTX (0x1 << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ -#define UART_IMR_OVRE (0x1 << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ -#define UART_IMR_FRAME (0x1 << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ -#define UART_IMR_PARE (0x1 << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ -#define UART_IMR_TXEMPTY (0x1 << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ -#define UART_IMR_TXBUFE (0x1 << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ -#define UART_IMR_RXBUFF (0x1 << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ -/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ -#define UART_SR_RXRDY (0x1 << 0) /**< \brief (UART_SR) Receiver Ready */ -#define UART_SR_TXRDY (0x1 << 1) /**< \brief (UART_SR) Transmitter Ready */ -#define UART_SR_ENDRX (0x1 << 3) /**< \brief (UART_SR) End of Receiver Transfer */ -#define UART_SR_ENDTX (0x1 << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ -#define UART_SR_OVRE (0x1 << 5) /**< \brief (UART_SR) Overrun Error */ -#define UART_SR_FRAME (0x1 << 6) /**< \brief (UART_SR) Framing Error */ -#define UART_SR_PARE (0x1 << 7) /**< \brief (UART_SR) Parity Error */ -#define UART_SR_TXEMPTY (0x1 << 9) /**< \brief (UART_SR) Transmitter Empty */ -#define UART_SR_TXBUFE (0x1 << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ -#define UART_SR_RXBUFF (0x1 << 12) /**< \brief (UART_SR) Receive Buffer Full */ -/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ -#define UART_RHR_RXCHR (0xff << 0) /**< \brief (UART_RHR) Received Character */ -/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ -#define UART_THR_TXCHR (0xff << 0) /**< \brief (UART_THR) Character to be Transmitted */ -/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define UART_BRGR_CD (0xffff << 0) /**< \brief (UART_BRGR) Clock Divisor */ -/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ -#define UART_RPR_RXPTR (0xffffffff << 0) /**< \brief (UART_RPR) Receive Pointer Register */ -/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ -#define UART_RCR_RXCTR (0xffff << 0) /**< \brief (UART_RCR) Receive Counter Register */ -/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ -#define UART_TPR_TXPTR (0xffffffff << 0) /**< \brief (UART_TPR) Transmit Counter Register */ -/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ -#define UART_TCR_TXCTR (0xffff << 0) /**< \brief (UART_TCR) Transmit Counter Register */ -/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ -#define UART_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (UART_RNPR) Receive Next Pointer */ -/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ -#define UART_RNCR_RXNCTR (0xffff << 0) /**< \brief (UART_RNCR) Receive Next Counter */ -/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define UART_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (UART_TNPR) Transmit Next Pointer */ -/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define UART_TNCR_TXNCTR (0xffff << 0) /**< \brief (UART_TNCR) Transmit Counter Next */ -/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ -#define UART_PTCR_RXTEN (0x1 << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ -#define UART_PTCR_RXTDIS (0x1 << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ -#define UART_PTCR_TXTEN (0x1 << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ -#define UART_PTCR_TXTDIS (0x1 << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ -/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ -#define UART_PTSR_RXTEN (0x1 << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ -#define UART_PTSR_TXTEN (0x1 << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR USB High Speed Device Port */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_UDPHS USB High Speed Device Port */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief UdphsDma hardware registers */ -typedef struct { - RwReg UDPHS_DMANXTDSC; /**< \brief (UdphsDma Offset: 0x0) UDPHS DMA Next Descriptor Address Register */ - RwReg UDPHS_DMAADDRESS; /**< \brief (UdphsDma Offset: 0x4) UDPHS DMA Channel Address Register */ - RwReg UDPHS_DMACONTROL; /**< \brief (UdphsDma Offset: 0x8) UDPHS DMA Channel Control Register */ - RwReg UDPHS_DMASTATUS; /**< \brief (UdphsDma Offset: 0xC) UDPHS DMA Channel Status Register */ -} UdphsDma; -/** \brief UdphsEpt hardware registers */ -typedef struct { - RwReg UDPHS_EPTCFG; /**< \brief (UdphsEpt Offset: 0x0) UDPHS Endpoint Configuration Register */ - RwReg UDPHS_EPTCTLENB; /**< \brief (UdphsEpt Offset: 0x4) UDPHS Endpoint Control Enable Register */ - RwReg UDPHS_EPTCTLDIS; /**< \brief (UdphsEpt Offset: 0x8) UDPHS Endpoint Control Disable Register */ - RwReg UDPHS_EPTCTL; /**< \brief (UdphsEpt Offset: 0xC) UDPHS Endpoint Control Register */ - RwReg Reserved1[1]; - RwReg UDPHS_EPTSETSTA; /**< \brief (UdphsEpt Offset: 0x14) UDPHS Endpoint Set Status Register */ - RwReg UDPHS_EPTCLRSTA; /**< \brief (UdphsEpt Offset: 0x18) UDPHS Endpoint Clear Status Register */ - RwReg UDPHS_EPTSTA; /**< \brief (UdphsEpt Offset: 0x1C) UDPHS Endpoint Status Register */ -} UdphsEpt; -/** \brief Udphs hardware registers */ -typedef struct { - RwReg UDPHS_CTRL; /**< \brief (Udphs Offset: 0x00) UDPHS Control Register */ - RoReg UDPHS_FNUM; /**< \brief (Udphs Offset: 0x04) UDPHS Frame Number Register */ - RwReg Reserved1[2]; - RwReg UDPHS_IEN; /**< \brief (Udphs Offset: 0x10) UDPHS Interrupt Enable Register */ - RoReg UDPHS_INTSTA; /**< \brief (Udphs Offset: 0x14) UDPHS Interrupt Status Register */ - WoReg UDPHS_CLRINT; /**< \brief (Udphs Offset: 0x18) UDPHS Clear Interrupt Register */ - WoReg UDPHS_EPTRST; /**< \brief (Udphs Offset: 0x1C) UDPHS Endpoints Reset Register */ - RwReg Reserved2[48]; - RwReg UDPHS_TST; /**< \brief (Udphs Offset: 0xE0) UDPHS Test Register */ - RwReg Reserved3[3]; - RoReg UDPHS_IPNAME1; /**< \brief (Udphs Offset: 0xF0) UDPHS Name1 Register */ - RoReg UDPHS_IPNAME2; /**< \brief (Udphs Offset: 0xF4) UDPHS Name2 Register */ - RoReg UDPHS_IPFEATURES; /**< \brief (Udphs Offset: 0xF8) UDPHS Features Register */ - RwReg Reserved4[1]; - UdphsEpt UDPHS_EPT[7]; /**< \brief (Udphs Offset: 0x100) endpoint = 0 .. 6 */ - RwReg Reserved5[80]; - UdphsDma UDPHS_DMA[5]; /**< \brief (Udphs Offset: 0x320) channel = 1 .. 5 */ -} Udphs; -#endif /* __ASSEMBLY__ */ -/* -------- UDPHS_CTRL : (UDPHS Offset: 0x00) UDPHS Control Register -------- */ -#define UDPHS_CTRL_DEV_ADDR (0x7f << 0) /**< \brief (UDPHS_CTRL) UDPHS Address */ -#define UDPHS_CTRL_FADDR_EN (0x1 << 7) /**< \brief (UDPHS_CTRL) Function Address Enable */ -#define UDPHS_CTRL_EN_UDPHS (0x1 << 8) /**< \brief (UDPHS_CTRL) UDPHS Enable */ -#define UDPHS_CTRL_DETACH (0x1 << 9) /**< \brief (UDPHS_CTRL) Detach Command */ -#define UDPHS_CTRL_REWAKEUP (0x1 << 10) /**< \brief (UDPHS_CTRL) Send Remote Wake Up */ -#define UDPHS_CTRL_PULLD_DIS (0x1 << 11) /**< \brief (UDPHS_CTRL) Pull-Down Disable */ -/* -------- UDPHS_FNUM : (UDPHS Offset: 0x04) UDPHS Frame Number Register -------- */ -#define UDPHS_FNUM_MICRO_FRAME_NUM (0x7 << 0) /**< \brief (UDPHS_FNUM) Microframe Number */ -#define UDPHS_FNUM_FRAME_NUMBER (0x7ff << 3) /**< \brief (UDPHS_FNUM) Frame Number as defined in the Packet Field Formats */ -#define UDPHS_FNUM_FNUM_ERR (0x1 << 31) /**< \brief (UDPHS_FNUM) Frame Number CRC Error */ -/* -------- UDPHS_IEN : (UDPHS Offset: 0x10) UDPHS Interrupt Enable Register -------- */ -#define UDPHS_IEN_DET_SUSPD (0x1 << 1) /**< \brief (UDPHS_IEN) Suspend Interrupt Enable */ -#define UDPHS_IEN_MICRO_SOF (0x1 << 2) /**< \brief (UDPHS_IEN) Micro-SOF Interrupt Enable */ -#define UDPHS_IEN_INT_SOF (0x1 << 3) /**< \brief (UDPHS_IEN) SOF Interrupt Enable */ -#define UDPHS_IEN_ENDRESET (0x1 << 4) /**< \brief (UDPHS_IEN) End Of Reset Interrupt Enable */ -#define UDPHS_IEN_WAKE_UP (0x1 << 5) /**< \brief (UDPHS_IEN) Wake Up CPU Interrupt Enable */ -#define UDPHS_IEN_ENDOFRSM (0x1 << 6) /**< \brief (UDPHS_IEN) End Of Resume Interrupt Enable */ -#define UDPHS_IEN_UPSTR_RES (0x1 << 7) /**< \brief (UDPHS_IEN) Upstream Resume Interrupt Enable */ -#define UDPHS_IEN_EPT_0 (0x1 << 8) /**< \brief (UDPHS_IEN) Endpoint 0 Interrupt Enable */ -#define UDPHS_IEN_EPT_1 (0x1 << 9) /**< \brief (UDPHS_IEN) Endpoint 1 Interrupt Enable */ -#define UDPHS_IEN_EPT_2 (0x1 << 10) /**< \brief (UDPHS_IEN) Endpoint 2 Interrupt Enable */ -#define UDPHS_IEN_EPT_3 (0x1 << 11) /**< \brief (UDPHS_IEN) Endpoint 3 Interrupt Enable */ -#define UDPHS_IEN_EPT_4 (0x1 << 12) /**< \brief (UDPHS_IEN) Endpoint 4 Interrupt Enable */ -#define UDPHS_IEN_EPT_5 (0x1 << 13) /**< \brief (UDPHS_IEN) Endpoint 5 Interrupt Enable */ -#define UDPHS_IEN_EPT_6 (0x1 << 14) /**< \brief (UDPHS_IEN) Endpoint 6 Interrupt Enable */ -#define UDPHS_IEN_DMA_1 (0x1 << 25) /**< \brief (UDPHS_IEN) DMA Channel 1 Interrupt Enable */ -#define UDPHS_IEN_DMA_2 (0x1 << 26) /**< \brief (UDPHS_IEN) DMA Channel 2 Interrupt Enable */ -#define UDPHS_IEN_DMA_3 (0x1 << 27) /**< \brief (UDPHS_IEN) DMA Channel 3 Interrupt Enable */ -#define UDPHS_IEN_DMA_4 (0x1 << 28) /**< \brief (UDPHS_IEN) DMA Channel 4 Interrupt Enable */ -#define UDPHS_IEN_DMA_5 (0x1 << 29) /**< \brief (UDPHS_IEN) DMA Channel 5 Interrupt Enable */ -#define UDPHS_IEN_DMA_6 (0x1 << 30) /**< \brief (UDPHS_IEN) DMA Channel 6 Interrupt Enable */ -/* -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) UDPHS Interrupt Status Register -------- */ -#define UDPHS_INTSTA_SPEED (0x1 << 0) /**< \brief (UDPHS_INTSTA) Speed Status */ -#define UDPHS_INTSTA_DET_SUSPD (0x1 << 1) /**< \brief (UDPHS_INTSTA) Suspend Interrupt */ -#define UDPHS_INTSTA_MICRO_SOF (0x1 << 2) /**< \brief (UDPHS_INTSTA) Micro Start Of Frame Interrupt */ -#define UDPHS_INTSTA_INT_SOF (0x1 << 3) /**< \brief (UDPHS_INTSTA) Start Of Frame Interrupt */ -#define UDPHS_INTSTA_ENDRESET (0x1 << 4) /**< \brief (UDPHS_INTSTA) End Of Reset Interrupt */ -#define UDPHS_INTSTA_WAKE_UP (0x1 << 5) /**< \brief (UDPHS_INTSTA) Wake Up CPU Interrupt */ -#define UDPHS_INTSTA_ENDOFRSM (0x1 << 6) /**< \brief (UDPHS_INTSTA) End Of Resume Interrupt */ -#define UDPHS_INTSTA_UPSTR_RES (0x1 << 7) /**< \brief (UDPHS_INTSTA) Upstream Resume Interrupt */ -#define UDPHS_INTSTA_EPT_0 (0x1 << 8) /**< \brief (UDPHS_INTSTA) Endpoint 0 Interrupt */ -#define UDPHS_INTSTA_EPT_1 (0x1 << 9) /**< \brief (UDPHS_INTSTA) Endpoint 1 Interrupt */ -#define UDPHS_INTSTA_EPT_2 (0x1 << 10) /**< \brief (UDPHS_INTSTA) Endpoint 2 Interrupt */ -#define UDPHS_INTSTA_EPT_3 (0x1 << 11) /**< \brief (UDPHS_INTSTA) Endpoint 3 Interrupt */ -#define UDPHS_INTSTA_EPT_4 (0x1 << 12) /**< \brief (UDPHS_INTSTA) Endpoint 4 Interrupt */ -#define UDPHS_INTSTA_EPT_5 (0x1 << 13) /**< \brief (UDPHS_INTSTA) Endpoint 5 Interrupt */ -#define UDPHS_INTSTA_EPT_6 (0x1 << 14) /**< \brief (UDPHS_INTSTA) Endpoint 6 Interrupt */ -#define UDPHS_INTSTA_DMA_1 (0x1 << 25) /**< \brief (UDPHS_INTSTA) DMA Channel 1 Interrupt */ -#define UDPHS_INTSTA_DMA_2 (0x1 << 26) /**< \brief (UDPHS_INTSTA) DMA Channel 2 Interrupt */ -#define UDPHS_INTSTA_DMA_3 (0x1 << 27) /**< \brief (UDPHS_INTSTA) DMA Channel 3 Interrupt */ -#define UDPHS_INTSTA_DMA_4 (0x1 << 28) /**< \brief (UDPHS_INTSTA) DMA Channel 4 Interrupt */ -#define UDPHS_INTSTA_DMA_5 (0x1 << 29) /**< \brief (UDPHS_INTSTA) DMA Channel 5 Interrupt */ -#define UDPHS_INTSTA_DMA_6 (0x1 << 30) /**< \brief (UDPHS_INTSTA) DMA Channel 6 Interrupt */ -/* -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) UDPHS Clear Interrupt Register -------- */ -#define UDPHS_CLRINT_DET_SUSPD (0x1 << 1) /**< \brief (UDPHS_CLRINT) Suspend Interrupt Clear */ -#define UDPHS_CLRINT_MICRO_SOF (0x1 << 2) /**< \brief (UDPHS_CLRINT) Micro Start Of Frame Interrupt Clear */ -#define UDPHS_CLRINT_INT_SOF (0x1 << 3) /**< \brief (UDPHS_CLRINT) Start Of Frame Interrupt Clear */ -#define UDPHS_CLRINT_ENDRESET (0x1 << 4) /**< \brief (UDPHS_CLRINT) End Of Reset Interrupt Clear */ -#define UDPHS_CLRINT_WAKE_UP (0x1 << 5) /**< \brief (UDPHS_CLRINT) Wake Up CPU Interrupt Clear */ -#define UDPHS_CLRINT_ENDOFRSM (0x1 << 6) /**< \brief (UDPHS_CLRINT) End Of Resume Interrupt Clear */ -#define UDPHS_CLRINT_UPSTR_RES (0x1 << 7) /**< \brief (UDPHS_CLRINT) Upstream Resume Interrupt Clear */ -/* -------- UDPHS_EPTRST : (UDPHS Offset: 0x1C) UDPHS Endpoints Reset Register -------- */ -#define UDPHS_EPTRST_EPT_0 (0x1 << 0) /**< \brief (UDPHS_EPTRST) Endpoint 0 Reset */ -#define UDPHS_EPTRST_EPT_1 (0x1 << 1) /**< \brief (UDPHS_EPTRST) Endpoint 1 Reset */ -#define UDPHS_EPTRST_EPT_2 (0x1 << 2) /**< \brief (UDPHS_EPTRST) Endpoint 2 Reset */ -#define UDPHS_EPTRST_EPT_3 (0x1 << 3) /**< \brief (UDPHS_EPTRST) Endpoint 3 Reset */ -#define UDPHS_EPTRST_EPT_4 (0x1 << 4) /**< \brief (UDPHS_EPTRST) Endpoint 4 Reset */ -#define UDPHS_EPTRST_EPT_5 (0x1 << 5) /**< \brief (UDPHS_EPTRST) Endpoint 5 Reset */ -#define UDPHS_EPTRST_EPT_6 (0x1 << 6) /**< \brief (UDPHS_EPTRST) Endpoint 6 Reset */ -/* -------- UDPHS_TST : (UDPHS Offset: 0xE0) UDPHS Test Register -------- */ -#define UDPHS_TST_SPEED_CFG (0x3 << 0) /**< \brief (UDPHS_TST) Speed Configuration */ -#define UDPHS_TST_TST_J (0x1 << 2) /**< \brief (UDPHS_TST) Test J Mode */ -#define UDPHS_TST_TST_K (0x1 << 3) /**< \brief (UDPHS_TST) Test K Mode */ -#define UDPHS_TST_TST_PKT (0x1 << 4) /**< \brief (UDPHS_TST) Test Packet Mode */ -#define UDPHS_TST_OPMODE2 (0x1 << 5) /**< \brief (UDPHS_TST) OpMode2 */ -/* -------- UDPHS_IPNAME1 : (UDPHS Offset: 0xF0) UDPHS Name1 Register -------- */ -#define UDPHS_IPNAME1_IP_NAME1 (0xffffffff << 0) /**< \brief (UDPHS_IPNAME1) */ -/* -------- UDPHS_IPNAME2 : (UDPHS Offset: 0xF4) UDPHS Name2 Register -------- */ -#define UDPHS_IPNAME2_IP_NAME2 (0xffffffff << 0) /**< \brief (UDPHS_IPNAME2) */ -/* -------- UDPHS_IPFEATURES : (UDPHS Offset: 0xF8) UDPHS Features Register -------- */ -#define UDPHS_IPFEATURES_EPT_NBR_MAX (0xf << 0) /**< \brief (UDPHS_IPFEATURES) Max Number of Endpoints */ -#define UDPHS_IPFEATURES_DMA_CHANNEL_NBR (0x7 << 4) /**< \brief (UDPHS_IPFEATURES) Number of DMA Channels */ -#define UDPHS_IPFEATURES_DMA_B_SIZ (0x1 << 7) /**< \brief (UDPHS_IPFEATURES) DMA Buffer Size */ -#define UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH (0xf << 8) /**< \brief (UDPHS_IPFEATURES) DMA FIFO Depth in Words */ -#define UDPHS_IPFEATURES_FIFO_MAX_SIZE (0x7 << 12) /**< \brief (UDPHS_IPFEATURES) DPRAM Size */ -#define UDPHS_IPFEATURES_BW_DPRAM (0x1 << 15) /**< \brief (UDPHS_IPFEATURES) DPRAM Byte Write Capability */ -#define UDPHS_IPFEATURES_DATAB16_8 (0x1 << 16) /**< \brief (UDPHS_IPFEATURES) UTMI DataBus16_8 */ -#define UDPHS_IPFEATURES_ISO_EPT_1 (0x1 << 17) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_2 (0x1 << 18) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_3 (0x1 << 19) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_4 (0x1 << 20) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_5 (0x1 << 21) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_6 (0x1 << 22) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_7 (0x1 << 23) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_8 (0x1 << 24) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_9 (0x1 << 25) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_10 (0x1 << 26) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_11 (0x1 << 27) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_12 (0x1 << 28) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_13 (0x1 << 29) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_14 (0x1 << 30) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -#define UDPHS_IPFEATURES_ISO_EPT_15 (0x1 << 31) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */ -/* -------- UDPHS_EPTCFG0 : (UDPHS Offset: 0x100) UDPHS Endpoint Configuration Register (endpoint = 0) -------- */ -#define UDPHS_EPTCFG0_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG0) Endpoint Size */ -#define UDPHS_EPTCFG0_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG0) 8 bytes */ -#define UDPHS_EPTCFG0_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG0) 16 bytes */ -#define UDPHS_EPTCFG0_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG0) 32 bytes */ -#define UDPHS_EPTCFG0_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG0) 64 bytes */ -#define UDPHS_EPTCFG0_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG0) 128 bytes */ -#define UDPHS_EPTCFG0_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG0) 256 bytes */ -#define UDPHS_EPTCFG0_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG0) 512 bytes */ -#define UDPHS_EPTCFG0_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG0) 1024 bytes */ -#define UDPHS_EPTCFG0_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG0) Endpoint Direction */ -#define UDPHS_EPTCFG0_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG0) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG0_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG0) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG0_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG0) Endpoint Type */ -#define UDPHS_EPTCFG0_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG0) Control endpoint */ -#define UDPHS_EPTCFG0_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG0) Isochronous endpoint */ -#define UDPHS_EPTCFG0_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG0) Bulk endpoint */ -#define UDPHS_EPTCFG0_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG0) Interrupt endpoint */ -#define UDPHS_EPTCFG0_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG0) Number of Banks */ -#define UDPHS_EPTCFG0_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG0) Zero bank, the endpoint is not mapped in memory */ -#define UDPHS_EPTCFG0_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG0) One bank (bank 0) */ -#define UDPHS_EPTCFG0_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG0) Double bank (Ping-Pong: bank 0/bank 1) */ -#define UDPHS_EPTCFG0_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG0) Triple bank (bank 0/bank 1/bank 2) */ -#define UDPHS_EPTCFG0_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG0) Number Of Transaction per Microframe */ -#define UDPHS_EPTCFG0_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG0) Endpoint Mapped */ -/* -------- UDPHS_EPTCTLENB0 : (UDPHS Offset: 0x104) UDPHS Endpoint Control Enable Register (endpoint = 0) -------- */ -#define UDPHS_EPTCTLENB0_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB0) Endpoint Enable */ -#define UDPHS_EPTCTLENB0_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB0) Packet Auto-Valid Enable */ -#define UDPHS_EPTCTLENB0_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB0) Interrupts Disable DMA */ -#define UDPHS_EPTCTLENB0_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB0) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLENB0_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB0) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB0_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB0) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB0_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB0) Overflow Error Interrupt Enable */ -#define UDPHS_EPTCTLENB0_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB0) Received OUT Data Interrupt Enable */ -#define UDPHS_EPTCTLENB0_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB0) Transmitted IN Data Complete Interrupt Enable */ -#define UDPHS_EPTCTLENB0_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB0) TX Packet Ready/Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB0_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB0) Received SETUP/Error Flow Interrupt Enable */ -#define UDPHS_EPTCTLENB0_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB0) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB0_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB0) NAKIN/Bank Flush Error Interrupt Enable */ -#define UDPHS_EPTCTLENB0_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB0) NAKOUT Interrupt Enable */ -#define UDPHS_EPTCTLENB0_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB0) Busy Bank Interrupt Enable */ -#define UDPHS_EPTCTLENB0_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB0) Short Packet Send/Short Packet Interrupt Enable */ -/* -------- UDPHS_EPTCTLDIS0 : (UDPHS Offset: 0x108) UDPHS Endpoint Control Disable Register (endpoint = 0) -------- */ -#define UDPHS_EPTCTLDIS0_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS0) Endpoint Disable */ -#define UDPHS_EPTCTLDIS0_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS0) Packet Auto-Valid Disable */ -#define UDPHS_EPTCTLDIS0_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS0) Interrupts Disable DMA */ -#define UDPHS_EPTCTLDIS0_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS0) NYET Enable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLDIS0_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS0) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS0_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS0) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS0_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS0) Overflow Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS0) Received OUT Data Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS0) Transmitted IN Data Complete Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS0) TX Packet Ready/Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS0) Received SETUP/Error Flow Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS0) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS0) NAKIN/bank flush error Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS0) NAKOUT Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS0) Busy Bank Interrupt Disable */ -#define UDPHS_EPTCTLDIS0_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS0) Short Packet Interrupt Disable */ -/* -------- UDPHS_EPTCTL0 : (UDPHS Offset: 0x10C) UDPHS Endpoint Control Register (endpoint = 0) -------- */ -#define UDPHS_EPTCTL0_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL0) Endpoint Enable */ -#define UDPHS_EPTCTL0_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL0) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */ -#define UDPHS_EPTCTL0_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL0) Interrupt Disables DMA */ -#define UDPHS_EPTCTL0_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL0) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTL0_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL0) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL0_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL0) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL0_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL0) Overflow Error Interrupt Enabled */ -#define UDPHS_EPTCTL0_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL0) Received OUT Data Interrupt Enabled */ -#define UDPHS_EPTCTL0_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL0) Transmitted IN Data Complete Interrupt Enabled */ -#define UDPHS_EPTCTL0_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL0) TX Packet Ready/Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL0_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL0) Received SETUP/Error Flow Interrupt Enabled */ -#define UDPHS_EPTCTL0_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL0) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL0_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL0) NAKIN/Bank Flush Error Interrupt Enabled */ -#define UDPHS_EPTCTL0_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL0) NAKOUT Interrupt Enabled */ -#define UDPHS_EPTCTL0_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL0) Busy Bank Interrupt Enabled */ -#define UDPHS_EPTCTL0_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL0) Short Packet Interrupt Enabled */ -/* -------- UDPHS_EPTSETSTA0 : (UDPHS Offset: 0x114) UDPHS Endpoint Set Status Register (endpoint = 0) -------- */ -#define UDPHS_EPTSETSTA0_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA0) Stall Handshake Request Set */ -#define UDPHS_EPTSETSTA0_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA0) KILL Bank Set (for IN Endpoint) */ -#define UDPHS_EPTSETSTA0_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA0) TX Packet Ready Set */ -/* -------- UDPHS_EPTCLRSTA0 : (UDPHS Offset: 0x118) UDPHS Endpoint Clear Status Register (endpoint = 0) -------- */ -#define UDPHS_EPTCLRSTA0_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA0) Stall Handshake Request Clear */ -#define UDPHS_EPTCLRSTA0_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA0) Data Toggle Clear */ -#define UDPHS_EPTCLRSTA0_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA0) Received OUT Data Clear */ -#define UDPHS_EPTCLRSTA0_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA0) Transmitted IN Data Complete Clear */ -#define UDPHS_EPTCLRSTA0_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA0) Received SETUP/Error Flow Clear */ -#define UDPHS_EPTCLRSTA0_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA0) Stall Sent/Number of Transaction Error Clear */ -#define UDPHS_EPTCLRSTA0_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA0) NAKIN/Bank Flush Error Clear */ -#define UDPHS_EPTCLRSTA0_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA0) NAKOUT Clear */ -/* -------- UDPHS_EPTSTA0 : (UDPHS Offset: 0x11C) UDPHS Endpoint Status Register (endpoint = 0) -------- */ -#define UDPHS_EPTSTA0_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA0) Stall Handshake Request */ -#define UDPHS_EPTSTA0_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA0) Toggle Sequencing */ -#define UDPHS_EPTSTA0_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA0) Overflow Error */ -#define UDPHS_EPTSTA0_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA0) Received OUT Data/KILL Bank */ -#define UDPHS_EPTSTA0_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA0) Transmitted IN Data Complete */ -#define UDPHS_EPTSTA0_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA0) TX Packet Ready/Transaction Error */ -#define UDPHS_EPTSTA0_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA0) Received SETUP/Error Flow */ -#define UDPHS_EPTSTA0_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA0) Stall Sent/CRC ISO Error/Number of Transaction Error */ -#define UDPHS_EPTSTA0_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA0) NAK IN/Bank Flush Error */ -#define UDPHS_EPTSTA0_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA0) NAK OUT */ -#define UDPHS_EPTSTA0_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA0) Current Bank/Control Direction */ -#define UDPHS_EPTSTA0_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA0) Busy Bank Number */ -#define UDPHS_EPTSTA0_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA0) UDPHS Byte Count */ -#define UDPHS_EPTSTA0_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA0) Short Packet */ -/* -------- UDPHS_EPTCFG1 : (UDPHS Offset: 0x120) UDPHS Endpoint Configuration Register (endpoint = 1) -------- */ -#define UDPHS_EPTCFG1_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG1) Endpoint Size */ -#define UDPHS_EPTCFG1_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG1) 8 bytes */ -#define UDPHS_EPTCFG1_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG1) 16 bytes */ -#define UDPHS_EPTCFG1_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG1) 32 bytes */ -#define UDPHS_EPTCFG1_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG1) 64 bytes */ -#define UDPHS_EPTCFG1_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG1) 128 bytes */ -#define UDPHS_EPTCFG1_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG1) 256 bytes */ -#define UDPHS_EPTCFG1_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG1) 512 bytes */ -#define UDPHS_EPTCFG1_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG1) 1024 bytes */ -#define UDPHS_EPTCFG1_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG1) Endpoint Direction */ -#define UDPHS_EPTCFG1_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG1) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG1_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG1) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG1_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG1) Endpoint Type */ -#define UDPHS_EPTCFG1_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG1) Control endpoint */ -#define UDPHS_EPTCFG1_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG1) Isochronous endpoint */ -#define UDPHS_EPTCFG1_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG1) Bulk endpoint */ -#define UDPHS_EPTCFG1_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG1) Interrupt endpoint */ -#define UDPHS_EPTCFG1_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG1) Number of Banks */ -#define UDPHS_EPTCFG1_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG1) Zero bank, the endpoint is not mapped in memory */ -#define UDPHS_EPTCFG1_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG1) One bank (bank 0) */ -#define UDPHS_EPTCFG1_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG1) Double bank (Ping-Pong: bank 0/bank 1) */ -#define UDPHS_EPTCFG1_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG1) Triple bank (bank 0/bank 1/bank 2) */ -#define UDPHS_EPTCFG1_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG1) Number Of Transaction per Microframe */ -#define UDPHS_EPTCFG1_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG1) Endpoint Mapped */ -/* -------- UDPHS_EPTCTLENB1 : (UDPHS Offset: 0x124) UDPHS Endpoint Control Enable Register (endpoint = 1) -------- */ -#define UDPHS_EPTCTLENB1_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB1) Endpoint Enable */ -#define UDPHS_EPTCTLENB1_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB1) Packet Auto-Valid Enable */ -#define UDPHS_EPTCTLENB1_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB1) Interrupts Disable DMA */ -#define UDPHS_EPTCTLENB1_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB1) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLENB1_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB1) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB1_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB1) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB1_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB1) Overflow Error Interrupt Enable */ -#define UDPHS_EPTCTLENB1_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB1) Received OUT Data Interrupt Enable */ -#define UDPHS_EPTCTLENB1_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB1) Transmitted IN Data Complete Interrupt Enable */ -#define UDPHS_EPTCTLENB1_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB1) TX Packet Ready/Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB1_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB1) Received SETUP/Error Flow Interrupt Enable */ -#define UDPHS_EPTCTLENB1_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB1) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB1_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB1) NAKIN/Bank Flush Error Interrupt Enable */ -#define UDPHS_EPTCTLENB1_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB1) NAKOUT Interrupt Enable */ -#define UDPHS_EPTCTLENB1_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB1) Busy Bank Interrupt Enable */ -#define UDPHS_EPTCTLENB1_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB1) Short Packet Send/Short Packet Interrupt Enable */ -/* -------- UDPHS_EPTCTLDIS1 : (UDPHS Offset: 0x128) UDPHS Endpoint Control Disable Register (endpoint = 1) -------- */ -#define UDPHS_EPTCTLDIS1_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS1) Endpoint Disable */ -#define UDPHS_EPTCTLDIS1_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS1) Packet Auto-Valid Disable */ -#define UDPHS_EPTCTLDIS1_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS1) Interrupts Disable DMA */ -#define UDPHS_EPTCTLDIS1_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS1) NYET Enable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLDIS1_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS1) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS1_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS1) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS1_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS1) Overflow Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS1) Received OUT Data Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS1) Transmitted IN Data Complete Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS1) TX Packet Ready/Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS1) Received SETUP/Error Flow Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS1) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS1) NAKIN/bank flush error Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS1) NAKOUT Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS1) Busy Bank Interrupt Disable */ -#define UDPHS_EPTCTLDIS1_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS1) Short Packet Interrupt Disable */ -/* -------- UDPHS_EPTCTL1 : (UDPHS Offset: 0x12C) UDPHS Endpoint Control Register (endpoint = 1) -------- */ -#define UDPHS_EPTCTL1_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL1) Endpoint Enable */ -#define UDPHS_EPTCTL1_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL1) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */ -#define UDPHS_EPTCTL1_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL1) Interrupt Disables DMA */ -#define UDPHS_EPTCTL1_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL1) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTL1_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL1) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL1_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL1) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL1_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL1) Overflow Error Interrupt Enabled */ -#define UDPHS_EPTCTL1_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL1) Received OUT Data Interrupt Enabled */ -#define UDPHS_EPTCTL1_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL1) Transmitted IN Data Complete Interrupt Enabled */ -#define UDPHS_EPTCTL1_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL1) TX Packet Ready/Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL1_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL1) Received SETUP/Error Flow Interrupt Enabled */ -#define UDPHS_EPTCTL1_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL1) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL1_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL1) NAKIN/Bank Flush Error Interrupt Enabled */ -#define UDPHS_EPTCTL1_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL1) NAKOUT Interrupt Enabled */ -#define UDPHS_EPTCTL1_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL1) Busy Bank Interrupt Enabled */ -#define UDPHS_EPTCTL1_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL1) Short Packet Interrupt Enabled */ -/* -------- UDPHS_EPTSETSTA1 : (UDPHS Offset: 0x134) UDPHS Endpoint Set Status Register (endpoint = 1) -------- */ -#define UDPHS_EPTSETSTA1_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA1) Stall Handshake Request Set */ -#define UDPHS_EPTSETSTA1_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA1) KILL Bank Set (for IN Endpoint) */ -#define UDPHS_EPTSETSTA1_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA1) TX Packet Ready Set */ -/* -------- UDPHS_EPTCLRSTA1 : (UDPHS Offset: 0x138) UDPHS Endpoint Clear Status Register (endpoint = 1) -------- */ -#define UDPHS_EPTCLRSTA1_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA1) Stall Handshake Request Clear */ -#define UDPHS_EPTCLRSTA1_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA1) Data Toggle Clear */ -#define UDPHS_EPTCLRSTA1_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA1) Received OUT Data Clear */ -#define UDPHS_EPTCLRSTA1_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA1) Transmitted IN Data Complete Clear */ -#define UDPHS_EPTCLRSTA1_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA1) Received SETUP/Error Flow Clear */ -#define UDPHS_EPTCLRSTA1_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA1) Stall Sent/Number of Transaction Error Clear */ -#define UDPHS_EPTCLRSTA1_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA1) NAKIN/Bank Flush Error Clear */ -#define UDPHS_EPTCLRSTA1_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA1) NAKOUT Clear */ -/* -------- UDPHS_EPTSTA1 : (UDPHS Offset: 0x13C) UDPHS Endpoint Status Register (endpoint = 1) -------- */ -#define UDPHS_EPTSTA1_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA1) Stall Handshake Request */ -#define UDPHS_EPTSTA1_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA1) Toggle Sequencing */ -#define UDPHS_EPTSTA1_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA1) Overflow Error */ -#define UDPHS_EPTSTA1_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA1) Received OUT Data/KILL Bank */ -#define UDPHS_EPTSTA1_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA1) Transmitted IN Data Complete */ -#define UDPHS_EPTSTA1_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA1) TX Packet Ready/Transaction Error */ -#define UDPHS_EPTSTA1_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA1) Received SETUP/Error Flow */ -#define UDPHS_EPTSTA1_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA1) Stall Sent/CRC ISO Error/Number of Transaction Error */ -#define UDPHS_EPTSTA1_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA1) NAK IN/Bank Flush Error */ -#define UDPHS_EPTSTA1_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA1) NAK OUT */ -#define UDPHS_EPTSTA1_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA1) Current Bank/Control Direction */ -#define UDPHS_EPTSTA1_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA1) Busy Bank Number */ -#define UDPHS_EPTSTA1_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA1) UDPHS Byte Count */ -#define UDPHS_EPTSTA1_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA1) Short Packet */ -/* -------- UDPHS_EPTCFG2 : (UDPHS Offset: 0x140) UDPHS Endpoint Configuration Register (endpoint = 2) -------- */ -#define UDPHS_EPTCFG2_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG2) Endpoint Size */ -#define UDPHS_EPTCFG2_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG2) 8 bytes */ -#define UDPHS_EPTCFG2_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG2) 16 bytes */ -#define UDPHS_EPTCFG2_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG2) 32 bytes */ -#define UDPHS_EPTCFG2_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG2) 64 bytes */ -#define UDPHS_EPTCFG2_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG2) 128 bytes */ -#define UDPHS_EPTCFG2_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG2) 256 bytes */ -#define UDPHS_EPTCFG2_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG2) 512 bytes */ -#define UDPHS_EPTCFG2_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG2) 1024 bytes */ -#define UDPHS_EPTCFG2_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG2) Endpoint Direction */ -#define UDPHS_EPTCFG2_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG2) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG2_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG2) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG2_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG2) Endpoint Type */ -#define UDPHS_EPTCFG2_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG2) Control endpoint */ -#define UDPHS_EPTCFG2_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG2) Isochronous endpoint */ -#define UDPHS_EPTCFG2_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG2) Bulk endpoint */ -#define UDPHS_EPTCFG2_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG2) Interrupt endpoint */ -#define UDPHS_EPTCFG2_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG2) Number of Banks */ -#define UDPHS_EPTCFG2_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG2) Zero bank, the endpoint is not mapped in memory */ -#define UDPHS_EPTCFG2_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG2) One bank (bank 0) */ -#define UDPHS_EPTCFG2_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG2) Double bank (Ping-Pong: bank 0/bank 1) */ -#define UDPHS_EPTCFG2_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG2) Triple bank (bank 0/bank 1/bank 2) */ -#define UDPHS_EPTCFG2_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG2) Number Of Transaction per Microframe */ -#define UDPHS_EPTCFG2_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG2) Endpoint Mapped */ -/* -------- UDPHS_EPTCTLENB2 : (UDPHS Offset: 0x144) UDPHS Endpoint Control Enable Register (endpoint = 2) -------- */ -#define UDPHS_EPTCTLENB2_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB2) Endpoint Enable */ -#define UDPHS_EPTCTLENB2_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB2) Packet Auto-Valid Enable */ -#define UDPHS_EPTCTLENB2_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB2) Interrupts Disable DMA */ -#define UDPHS_EPTCTLENB2_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB2) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLENB2_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB2) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB2_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB2) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB2_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB2) Overflow Error Interrupt Enable */ -#define UDPHS_EPTCTLENB2_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB2) Received OUT Data Interrupt Enable */ -#define UDPHS_EPTCTLENB2_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB2) Transmitted IN Data Complete Interrupt Enable */ -#define UDPHS_EPTCTLENB2_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB2) TX Packet Ready/Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB2_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB2) Received SETUP/Error Flow Interrupt Enable */ -#define UDPHS_EPTCTLENB2_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB2) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB2_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB2) NAKIN/Bank Flush Error Interrupt Enable */ -#define UDPHS_EPTCTLENB2_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB2) NAKOUT Interrupt Enable */ -#define UDPHS_EPTCTLENB2_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB2) Busy Bank Interrupt Enable */ -#define UDPHS_EPTCTLENB2_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB2) Short Packet Send/Short Packet Interrupt Enable */ -/* -------- UDPHS_EPTCTLDIS2 : (UDPHS Offset: 0x148) UDPHS Endpoint Control Disable Register (endpoint = 2) -------- */ -#define UDPHS_EPTCTLDIS2_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS2) Endpoint Disable */ -#define UDPHS_EPTCTLDIS2_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS2) Packet Auto-Valid Disable */ -#define UDPHS_EPTCTLDIS2_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS2) Interrupts Disable DMA */ -#define UDPHS_EPTCTLDIS2_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS2) NYET Enable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLDIS2_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS2) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS2_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS2) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS2_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS2) Overflow Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS2) Received OUT Data Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS2) Transmitted IN Data Complete Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS2) TX Packet Ready/Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS2) Received SETUP/Error Flow Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS2) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS2) NAKIN/bank flush error Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS2) NAKOUT Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS2) Busy Bank Interrupt Disable */ -#define UDPHS_EPTCTLDIS2_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS2) Short Packet Interrupt Disable */ -/* -------- UDPHS_EPTCTL2 : (UDPHS Offset: 0x14C) UDPHS Endpoint Control Register (endpoint = 2) -------- */ -#define UDPHS_EPTCTL2_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL2) Endpoint Enable */ -#define UDPHS_EPTCTL2_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL2) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */ -#define UDPHS_EPTCTL2_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL2) Interrupt Disables DMA */ -#define UDPHS_EPTCTL2_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL2) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTL2_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL2) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL2_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL2) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL2_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL2) Overflow Error Interrupt Enabled */ -#define UDPHS_EPTCTL2_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL2) Received OUT Data Interrupt Enabled */ -#define UDPHS_EPTCTL2_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL2) Transmitted IN Data Complete Interrupt Enabled */ -#define UDPHS_EPTCTL2_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL2) TX Packet Ready/Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL2_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL2) Received SETUP/Error Flow Interrupt Enabled */ -#define UDPHS_EPTCTL2_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL2) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL2_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL2) NAKIN/Bank Flush Error Interrupt Enabled */ -#define UDPHS_EPTCTL2_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL2) NAKOUT Interrupt Enabled */ -#define UDPHS_EPTCTL2_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL2) Busy Bank Interrupt Enabled */ -#define UDPHS_EPTCTL2_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL2) Short Packet Interrupt Enabled */ -/* -------- UDPHS_EPTSETSTA2 : (UDPHS Offset: 0x154) UDPHS Endpoint Set Status Register (endpoint = 2) -------- */ -#define UDPHS_EPTSETSTA2_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA2) Stall Handshake Request Set */ -#define UDPHS_EPTSETSTA2_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA2) KILL Bank Set (for IN Endpoint) */ -#define UDPHS_EPTSETSTA2_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA2) TX Packet Ready Set */ -/* -------- UDPHS_EPTCLRSTA2 : (UDPHS Offset: 0x158) UDPHS Endpoint Clear Status Register (endpoint = 2) -------- */ -#define UDPHS_EPTCLRSTA2_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA2) Stall Handshake Request Clear */ -#define UDPHS_EPTCLRSTA2_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA2) Data Toggle Clear */ -#define UDPHS_EPTCLRSTA2_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA2) Received OUT Data Clear */ -#define UDPHS_EPTCLRSTA2_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA2) Transmitted IN Data Complete Clear */ -#define UDPHS_EPTCLRSTA2_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA2) Received SETUP/Error Flow Clear */ -#define UDPHS_EPTCLRSTA2_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA2) Stall Sent/Number of Transaction Error Clear */ -#define UDPHS_EPTCLRSTA2_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA2) NAKIN/Bank Flush Error Clear */ -#define UDPHS_EPTCLRSTA2_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA2) NAKOUT Clear */ -/* -------- UDPHS_EPTSTA2 : (UDPHS Offset: 0x15C) UDPHS Endpoint Status Register (endpoint = 2) -------- */ -#define UDPHS_EPTSTA2_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA2) Stall Handshake Request */ -#define UDPHS_EPTSTA2_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA2) Toggle Sequencing */ -#define UDPHS_EPTSTA2_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA2) Overflow Error */ -#define UDPHS_EPTSTA2_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA2) Received OUT Data/KILL Bank */ -#define UDPHS_EPTSTA2_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA2) Transmitted IN Data Complete */ -#define UDPHS_EPTSTA2_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA2) TX Packet Ready/Transaction Error */ -#define UDPHS_EPTSTA2_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA2) Received SETUP/Error Flow */ -#define UDPHS_EPTSTA2_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA2) Stall Sent/CRC ISO Error/Number of Transaction Error */ -#define UDPHS_EPTSTA2_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA2) NAK IN/Bank Flush Error */ -#define UDPHS_EPTSTA2_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA2) NAK OUT */ -#define UDPHS_EPTSTA2_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA2) Current Bank/Control Direction */ -#define UDPHS_EPTSTA2_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA2) Busy Bank Number */ -#define UDPHS_EPTSTA2_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA2) UDPHS Byte Count */ -#define UDPHS_EPTSTA2_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA2) Short Packet */ -/* -------- UDPHS_EPTCFG3 : (UDPHS Offset: 0x160) UDPHS Endpoint Configuration Register (endpoint = 3) -------- */ -#define UDPHS_EPTCFG3_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG3) Endpoint Size */ -#define UDPHS_EPTCFG3_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG3) 8 bytes */ -#define UDPHS_EPTCFG3_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG3) 16 bytes */ -#define UDPHS_EPTCFG3_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG3) 32 bytes */ -#define UDPHS_EPTCFG3_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG3) 64 bytes */ -#define UDPHS_EPTCFG3_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG3) 128 bytes */ -#define UDPHS_EPTCFG3_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG3) 256 bytes */ -#define UDPHS_EPTCFG3_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG3) 512 bytes */ -#define UDPHS_EPTCFG3_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG3) 1024 bytes */ -#define UDPHS_EPTCFG3_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG3) Endpoint Direction */ -#define UDPHS_EPTCFG3_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG3) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG3_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG3) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG3_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG3) Endpoint Type */ -#define UDPHS_EPTCFG3_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG3) Control endpoint */ -#define UDPHS_EPTCFG3_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG3) Isochronous endpoint */ -#define UDPHS_EPTCFG3_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG3) Bulk endpoint */ -#define UDPHS_EPTCFG3_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG3) Interrupt endpoint */ -#define UDPHS_EPTCFG3_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG3) Number of Banks */ -#define UDPHS_EPTCFG3_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG3) Zero bank, the endpoint is not mapped in memory */ -#define UDPHS_EPTCFG3_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG3) One bank (bank 0) */ -#define UDPHS_EPTCFG3_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG3) Double bank (Ping-Pong: bank 0/bank 1) */ -#define UDPHS_EPTCFG3_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG3) Triple bank (bank 0/bank 1/bank 2) */ -#define UDPHS_EPTCFG3_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG3) Number Of Transaction per Microframe */ -#define UDPHS_EPTCFG3_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG3) Endpoint Mapped */ -/* -------- UDPHS_EPTCTLENB3 : (UDPHS Offset: 0x164) UDPHS Endpoint Control Enable Register (endpoint = 3) -------- */ -#define UDPHS_EPTCTLENB3_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB3) Endpoint Enable */ -#define UDPHS_EPTCTLENB3_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB3) Packet Auto-Valid Enable */ -#define UDPHS_EPTCTLENB3_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB3) Interrupts Disable DMA */ -#define UDPHS_EPTCTLENB3_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB3) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLENB3_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB3) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB3_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB3) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB3_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB3) Overflow Error Interrupt Enable */ -#define UDPHS_EPTCTLENB3_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB3) Received OUT Data Interrupt Enable */ -#define UDPHS_EPTCTLENB3_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB3) Transmitted IN Data Complete Interrupt Enable */ -#define UDPHS_EPTCTLENB3_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB3) TX Packet Ready/Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB3_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB3) Received SETUP/Error Flow Interrupt Enable */ -#define UDPHS_EPTCTLENB3_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB3) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB3_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB3) NAKIN/Bank Flush Error Interrupt Enable */ -#define UDPHS_EPTCTLENB3_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB3) NAKOUT Interrupt Enable */ -#define UDPHS_EPTCTLENB3_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB3) Busy Bank Interrupt Enable */ -#define UDPHS_EPTCTLENB3_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB3) Short Packet Send/Short Packet Interrupt Enable */ -/* -------- UDPHS_EPTCTLDIS3 : (UDPHS Offset: 0x168) UDPHS Endpoint Control Disable Register (endpoint = 3) -------- */ -#define UDPHS_EPTCTLDIS3_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS3) Endpoint Disable */ -#define UDPHS_EPTCTLDIS3_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS3) Packet Auto-Valid Disable */ -#define UDPHS_EPTCTLDIS3_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS3) Interrupts Disable DMA */ -#define UDPHS_EPTCTLDIS3_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS3) NYET Enable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLDIS3_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS3) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS3_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS3) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS3_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS3) Overflow Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS3) Received OUT Data Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS3) Transmitted IN Data Complete Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS3) TX Packet Ready/Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS3) Received SETUP/Error Flow Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS3) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS3) NAKIN/bank flush error Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS3) NAKOUT Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS3) Busy Bank Interrupt Disable */ -#define UDPHS_EPTCTLDIS3_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS3) Short Packet Interrupt Disable */ -/* -------- UDPHS_EPTCTL3 : (UDPHS Offset: 0x16C) UDPHS Endpoint Control Register (endpoint = 3) -------- */ -#define UDPHS_EPTCTL3_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL3) Endpoint Enable */ -#define UDPHS_EPTCTL3_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL3) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */ -#define UDPHS_EPTCTL3_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL3) Interrupt Disables DMA */ -#define UDPHS_EPTCTL3_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL3) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTL3_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL3) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL3_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL3) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL3_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL3) Overflow Error Interrupt Enabled */ -#define UDPHS_EPTCTL3_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL3) Received OUT Data Interrupt Enabled */ -#define UDPHS_EPTCTL3_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL3) Transmitted IN Data Complete Interrupt Enabled */ -#define UDPHS_EPTCTL3_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL3) TX Packet Ready/Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL3_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL3) Received SETUP/Error Flow Interrupt Enabled */ -#define UDPHS_EPTCTL3_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL3) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL3_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL3) NAKIN/Bank Flush Error Interrupt Enabled */ -#define UDPHS_EPTCTL3_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL3) NAKOUT Interrupt Enabled */ -#define UDPHS_EPTCTL3_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL3) Busy Bank Interrupt Enabled */ -#define UDPHS_EPTCTL3_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL3) Short Packet Interrupt Enabled */ -/* -------- UDPHS_EPTSETSTA3 : (UDPHS Offset: 0x174) UDPHS Endpoint Set Status Register (endpoint = 3) -------- */ -#define UDPHS_EPTSETSTA3_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA3) Stall Handshake Request Set */ -#define UDPHS_EPTSETSTA3_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA3) KILL Bank Set (for IN Endpoint) */ -#define UDPHS_EPTSETSTA3_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA3) TX Packet Ready Set */ -/* -------- UDPHS_EPTCLRSTA3 : (UDPHS Offset: 0x178) UDPHS Endpoint Clear Status Register (endpoint = 3) -------- */ -#define UDPHS_EPTCLRSTA3_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA3) Stall Handshake Request Clear */ -#define UDPHS_EPTCLRSTA3_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA3) Data Toggle Clear */ -#define UDPHS_EPTCLRSTA3_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA3) Received OUT Data Clear */ -#define UDPHS_EPTCLRSTA3_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA3) Transmitted IN Data Complete Clear */ -#define UDPHS_EPTCLRSTA3_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA3) Received SETUP/Error Flow Clear */ -#define UDPHS_EPTCLRSTA3_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA3) Stall Sent/Number of Transaction Error Clear */ -#define UDPHS_EPTCLRSTA3_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA3) NAKIN/Bank Flush Error Clear */ -#define UDPHS_EPTCLRSTA3_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA3) NAKOUT Clear */ -/* -------- UDPHS_EPTSTA3 : (UDPHS Offset: 0x17C) UDPHS Endpoint Status Register (endpoint = 3) -------- */ -#define UDPHS_EPTSTA3_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA3) Stall Handshake Request */ -#define UDPHS_EPTSTA3_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA3) Toggle Sequencing */ -#define UDPHS_EPTSTA3_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA3) Overflow Error */ -#define UDPHS_EPTSTA3_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA3) Received OUT Data/KILL Bank */ -#define UDPHS_EPTSTA3_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA3) Transmitted IN Data Complete */ -#define UDPHS_EPTSTA3_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA3) TX Packet Ready/Transaction Error */ -#define UDPHS_EPTSTA3_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA3) Received SETUP/Error Flow */ -#define UDPHS_EPTSTA3_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA3) Stall Sent/CRC ISO Error/Number of Transaction Error */ -#define UDPHS_EPTSTA3_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA3) NAK IN/Bank Flush Error */ -#define UDPHS_EPTSTA3_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA3) NAK OUT */ -#define UDPHS_EPTSTA3_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA3) Current Bank/Control Direction */ -#define UDPHS_EPTSTA3_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA3) Busy Bank Number */ -#define UDPHS_EPTSTA3_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA3) UDPHS Byte Count */ -#define UDPHS_EPTSTA3_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA3) Short Packet */ -/* -------- UDPHS_EPTCFG4 : (UDPHS Offset: 0x180) UDPHS Endpoint Configuration Register (endpoint = 4) -------- */ -#define UDPHS_EPTCFG4_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG4) Endpoint Size */ -#define UDPHS_EPTCFG4_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG4) 8 bytes */ -#define UDPHS_EPTCFG4_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG4) 16 bytes */ -#define UDPHS_EPTCFG4_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG4) 32 bytes */ -#define UDPHS_EPTCFG4_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG4) 64 bytes */ -#define UDPHS_EPTCFG4_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG4) 128 bytes */ -#define UDPHS_EPTCFG4_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG4) 256 bytes */ -#define UDPHS_EPTCFG4_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG4) 512 bytes */ -#define UDPHS_EPTCFG4_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG4) 1024 bytes */ -#define UDPHS_EPTCFG4_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG4) Endpoint Direction */ -#define UDPHS_EPTCFG4_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG4) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG4_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG4) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG4_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG4) Endpoint Type */ -#define UDPHS_EPTCFG4_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG4) Control endpoint */ -#define UDPHS_EPTCFG4_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG4) Isochronous endpoint */ -#define UDPHS_EPTCFG4_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG4) Bulk endpoint */ -#define UDPHS_EPTCFG4_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG4) Interrupt endpoint */ -#define UDPHS_EPTCFG4_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG4) Number of Banks */ -#define UDPHS_EPTCFG4_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG4) Zero bank, the endpoint is not mapped in memory */ -#define UDPHS_EPTCFG4_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG4) One bank (bank 0) */ -#define UDPHS_EPTCFG4_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG4) Double bank (Ping-Pong: bank 0/bank 1) */ -#define UDPHS_EPTCFG4_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG4) Triple bank (bank 0/bank 1/bank 2) */ -#define UDPHS_EPTCFG4_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG4) Number Of Transaction per Microframe */ -#define UDPHS_EPTCFG4_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG4) Endpoint Mapped */ -/* -------- UDPHS_EPTCTLENB4 : (UDPHS Offset: 0x184) UDPHS Endpoint Control Enable Register (endpoint = 4) -------- */ -#define UDPHS_EPTCTLENB4_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB4) Endpoint Enable */ -#define UDPHS_EPTCTLENB4_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB4) Packet Auto-Valid Enable */ -#define UDPHS_EPTCTLENB4_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB4) Interrupts Disable DMA */ -#define UDPHS_EPTCTLENB4_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB4) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLENB4_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB4) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB4_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB4) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB4_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB4) Overflow Error Interrupt Enable */ -#define UDPHS_EPTCTLENB4_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB4) Received OUT Data Interrupt Enable */ -#define UDPHS_EPTCTLENB4_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB4) Transmitted IN Data Complete Interrupt Enable */ -#define UDPHS_EPTCTLENB4_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB4) TX Packet Ready/Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB4_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB4) Received SETUP/Error Flow Interrupt Enable */ -#define UDPHS_EPTCTLENB4_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB4) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB4_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB4) NAKIN/Bank Flush Error Interrupt Enable */ -#define UDPHS_EPTCTLENB4_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB4) NAKOUT Interrupt Enable */ -#define UDPHS_EPTCTLENB4_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB4) Busy Bank Interrupt Enable */ -#define UDPHS_EPTCTLENB4_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB4) Short Packet Send/Short Packet Interrupt Enable */ -/* -------- UDPHS_EPTCTLDIS4 : (UDPHS Offset: 0x188) UDPHS Endpoint Control Disable Register (endpoint = 4) -------- */ -#define UDPHS_EPTCTLDIS4_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS4) Endpoint Disable */ -#define UDPHS_EPTCTLDIS4_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS4) Packet Auto-Valid Disable */ -#define UDPHS_EPTCTLDIS4_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS4) Interrupts Disable DMA */ -#define UDPHS_EPTCTLDIS4_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS4) NYET Enable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLDIS4_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS4) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS4_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS4) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS4_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS4) Overflow Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS4) Received OUT Data Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS4) Transmitted IN Data Complete Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS4) TX Packet Ready/Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS4) Received SETUP/Error Flow Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS4) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS4) NAKIN/bank flush error Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS4) NAKOUT Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS4) Busy Bank Interrupt Disable */ -#define UDPHS_EPTCTLDIS4_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS4) Short Packet Interrupt Disable */ -/* -------- UDPHS_EPTCTL4 : (UDPHS Offset: 0x18C) UDPHS Endpoint Control Register (endpoint = 4) -------- */ -#define UDPHS_EPTCTL4_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL4) Endpoint Enable */ -#define UDPHS_EPTCTL4_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL4) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */ -#define UDPHS_EPTCTL4_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL4) Interrupt Disables DMA */ -#define UDPHS_EPTCTL4_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL4) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTL4_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL4) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL4_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL4) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL4_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL4) Overflow Error Interrupt Enabled */ -#define UDPHS_EPTCTL4_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL4) Received OUT Data Interrupt Enabled */ -#define UDPHS_EPTCTL4_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL4) Transmitted IN Data Complete Interrupt Enabled */ -#define UDPHS_EPTCTL4_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL4) TX Packet Ready/Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL4_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL4) Received SETUP/Error Flow Interrupt Enabled */ -#define UDPHS_EPTCTL4_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL4) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL4_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL4) NAKIN/Bank Flush Error Interrupt Enabled */ -#define UDPHS_EPTCTL4_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL4) NAKOUT Interrupt Enabled */ -#define UDPHS_EPTCTL4_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL4) Busy Bank Interrupt Enabled */ -#define UDPHS_EPTCTL4_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL4) Short Packet Interrupt Enabled */ -/* -------- UDPHS_EPTSETSTA4 : (UDPHS Offset: 0x194) UDPHS Endpoint Set Status Register (endpoint = 4) -------- */ -#define UDPHS_EPTSETSTA4_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA4) Stall Handshake Request Set */ -#define UDPHS_EPTSETSTA4_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA4) KILL Bank Set (for IN Endpoint) */ -#define UDPHS_EPTSETSTA4_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA4) TX Packet Ready Set */ -/* -------- UDPHS_EPTCLRSTA4 : (UDPHS Offset: 0x198) UDPHS Endpoint Clear Status Register (endpoint = 4) -------- */ -#define UDPHS_EPTCLRSTA4_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA4) Stall Handshake Request Clear */ -#define UDPHS_EPTCLRSTA4_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA4) Data Toggle Clear */ -#define UDPHS_EPTCLRSTA4_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA4) Received OUT Data Clear */ -#define UDPHS_EPTCLRSTA4_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA4) Transmitted IN Data Complete Clear */ -#define UDPHS_EPTCLRSTA4_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA4) Received SETUP/Error Flow Clear */ -#define UDPHS_EPTCLRSTA4_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA4) Stall Sent/Number of Transaction Error Clear */ -#define UDPHS_EPTCLRSTA4_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA4) NAKIN/Bank Flush Error Clear */ -#define UDPHS_EPTCLRSTA4_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA4) NAKOUT Clear */ -/* -------- UDPHS_EPTSTA4 : (UDPHS Offset: 0x19C) UDPHS Endpoint Status Register (endpoint = 4) -------- */ -#define UDPHS_EPTSTA4_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA4) Stall Handshake Request */ -#define UDPHS_EPTSTA4_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA4) Toggle Sequencing */ -#define UDPHS_EPTSTA4_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA4) Overflow Error */ -#define UDPHS_EPTSTA4_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA4) Received OUT Data/KILL Bank */ -#define UDPHS_EPTSTA4_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA4) Transmitted IN Data Complete */ -#define UDPHS_EPTSTA4_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA4) TX Packet Ready/Transaction Error */ -#define UDPHS_EPTSTA4_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA4) Received SETUP/Error Flow */ -#define UDPHS_EPTSTA4_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA4) Stall Sent/CRC ISO Error/Number of Transaction Error */ -#define UDPHS_EPTSTA4_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA4) NAK IN/Bank Flush Error */ -#define UDPHS_EPTSTA4_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA4) NAK OUT */ -#define UDPHS_EPTSTA4_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA4) Current Bank/Control Direction */ -#define UDPHS_EPTSTA4_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA4) Busy Bank Number */ -#define UDPHS_EPTSTA4_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA4) UDPHS Byte Count */ -#define UDPHS_EPTSTA4_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA4) Short Packet */ -/* -------- UDPHS_EPTCFG5 : (UDPHS Offset: 0x1A0) UDPHS Endpoint Configuration Register (endpoint = 5) -------- */ -#define UDPHS_EPTCFG5_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG5) Endpoint Size */ -#define UDPHS_EPTCFG5_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG5) 8 bytes */ -#define UDPHS_EPTCFG5_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG5) 16 bytes */ -#define UDPHS_EPTCFG5_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG5) 32 bytes */ -#define UDPHS_EPTCFG5_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG5) 64 bytes */ -#define UDPHS_EPTCFG5_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG5) 128 bytes */ -#define UDPHS_EPTCFG5_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG5) 256 bytes */ -#define UDPHS_EPTCFG5_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG5) 512 bytes */ -#define UDPHS_EPTCFG5_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG5) 1024 bytes */ -#define UDPHS_EPTCFG5_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG5) Endpoint Direction */ -#define UDPHS_EPTCFG5_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG5) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG5_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG5) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG5_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG5) Endpoint Type */ -#define UDPHS_EPTCFG5_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG5) Control endpoint */ -#define UDPHS_EPTCFG5_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG5) Isochronous endpoint */ -#define UDPHS_EPTCFG5_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG5) Bulk endpoint */ -#define UDPHS_EPTCFG5_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG5) Interrupt endpoint */ -#define UDPHS_EPTCFG5_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG5) Number of Banks */ -#define UDPHS_EPTCFG5_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG5) Zero bank, the endpoint is not mapped in memory */ -#define UDPHS_EPTCFG5_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG5) One bank (bank 0) */ -#define UDPHS_EPTCFG5_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG5) Double bank (Ping-Pong: bank 0/bank 1) */ -#define UDPHS_EPTCFG5_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG5) Triple bank (bank 0/bank 1/bank 2) */ -#define UDPHS_EPTCFG5_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG5) Number Of Transaction per Microframe */ -#define UDPHS_EPTCFG5_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG5) Endpoint Mapped */ -/* -------- UDPHS_EPTCTLENB5 : (UDPHS Offset: 0x1A4) UDPHS Endpoint Control Enable Register (endpoint = 5) -------- */ -#define UDPHS_EPTCTLENB5_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB5) Endpoint Enable */ -#define UDPHS_EPTCTLENB5_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB5) Packet Auto-Valid Enable */ -#define UDPHS_EPTCTLENB5_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB5) Interrupts Disable DMA */ -#define UDPHS_EPTCTLENB5_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB5) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLENB5_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB5) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB5_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB5) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB5_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB5) Overflow Error Interrupt Enable */ -#define UDPHS_EPTCTLENB5_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB5) Received OUT Data Interrupt Enable */ -#define UDPHS_EPTCTLENB5_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB5) Transmitted IN Data Complete Interrupt Enable */ -#define UDPHS_EPTCTLENB5_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB5) TX Packet Ready/Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB5_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB5) Received SETUP/Error Flow Interrupt Enable */ -#define UDPHS_EPTCTLENB5_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB5) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB5_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB5) NAKIN/Bank Flush Error Interrupt Enable */ -#define UDPHS_EPTCTLENB5_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB5) NAKOUT Interrupt Enable */ -#define UDPHS_EPTCTLENB5_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB5) Busy Bank Interrupt Enable */ -#define UDPHS_EPTCTLENB5_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB5) Short Packet Send/Short Packet Interrupt Enable */ -/* -------- UDPHS_EPTCTLDIS5 : (UDPHS Offset: 0x1A8) UDPHS Endpoint Control Disable Register (endpoint = 5) -------- */ -#define UDPHS_EPTCTLDIS5_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS5) Endpoint Disable */ -#define UDPHS_EPTCTLDIS5_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS5) Packet Auto-Valid Disable */ -#define UDPHS_EPTCTLDIS5_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS5) Interrupts Disable DMA */ -#define UDPHS_EPTCTLDIS5_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS5) NYET Enable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLDIS5_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS5) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS5_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS5) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS5_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS5) Overflow Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS5) Received OUT Data Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS5) Transmitted IN Data Complete Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS5) TX Packet Ready/Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS5) Received SETUP/Error Flow Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS5) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS5) NAKIN/bank flush error Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS5) NAKOUT Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS5) Busy Bank Interrupt Disable */ -#define UDPHS_EPTCTLDIS5_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS5) Short Packet Interrupt Disable */ -/* -------- UDPHS_EPTCTL5 : (UDPHS Offset: 0x1AC) UDPHS Endpoint Control Register (endpoint = 5) -------- */ -#define UDPHS_EPTCTL5_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL5) Endpoint Enable */ -#define UDPHS_EPTCTL5_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL5) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */ -#define UDPHS_EPTCTL5_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL5) Interrupt Disables DMA */ -#define UDPHS_EPTCTL5_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL5) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTL5_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL5) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL5_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL5) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL5_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL5) Overflow Error Interrupt Enabled */ -#define UDPHS_EPTCTL5_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL5) Received OUT Data Interrupt Enabled */ -#define UDPHS_EPTCTL5_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL5) Transmitted IN Data Complete Interrupt Enabled */ -#define UDPHS_EPTCTL5_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL5) TX Packet Ready/Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL5_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL5) Received SETUP/Error Flow Interrupt Enabled */ -#define UDPHS_EPTCTL5_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL5) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL5_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL5) NAKIN/Bank Flush Error Interrupt Enabled */ -#define UDPHS_EPTCTL5_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL5) NAKOUT Interrupt Enabled */ -#define UDPHS_EPTCTL5_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL5) Busy Bank Interrupt Enabled */ -#define UDPHS_EPTCTL5_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL5) Short Packet Interrupt Enabled */ -/* -------- UDPHS_EPTSETSTA5 : (UDPHS Offset: 0x1B4) UDPHS Endpoint Set Status Register (endpoint = 5) -------- */ -#define UDPHS_EPTSETSTA5_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA5) Stall Handshake Request Set */ -#define UDPHS_EPTSETSTA5_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA5) KILL Bank Set (for IN Endpoint) */ -#define UDPHS_EPTSETSTA5_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA5) TX Packet Ready Set */ -/* -------- UDPHS_EPTCLRSTA5 : (UDPHS Offset: 0x1B8) UDPHS Endpoint Clear Status Register (endpoint = 5) -------- */ -#define UDPHS_EPTCLRSTA5_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA5) Stall Handshake Request Clear */ -#define UDPHS_EPTCLRSTA5_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA5) Data Toggle Clear */ -#define UDPHS_EPTCLRSTA5_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA5) Received OUT Data Clear */ -#define UDPHS_EPTCLRSTA5_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA5) Transmitted IN Data Complete Clear */ -#define UDPHS_EPTCLRSTA5_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA5) Received SETUP/Error Flow Clear */ -#define UDPHS_EPTCLRSTA5_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA5) Stall Sent/Number of Transaction Error Clear */ -#define UDPHS_EPTCLRSTA5_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA5) NAKIN/Bank Flush Error Clear */ -#define UDPHS_EPTCLRSTA5_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA5) NAKOUT Clear */ -/* -------- UDPHS_EPTSTA5 : (UDPHS Offset: 0x1BC) UDPHS Endpoint Status Register (endpoint = 5) -------- */ -#define UDPHS_EPTSTA5_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA5) Stall Handshake Request */ -#define UDPHS_EPTSTA5_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA5) Toggle Sequencing */ -#define UDPHS_EPTSTA5_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA5) Overflow Error */ -#define UDPHS_EPTSTA5_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA5) Received OUT Data/KILL Bank */ -#define UDPHS_EPTSTA5_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA5) Transmitted IN Data Complete */ -#define UDPHS_EPTSTA5_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA5) TX Packet Ready/Transaction Error */ -#define UDPHS_EPTSTA5_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA5) Received SETUP/Error Flow */ -#define UDPHS_EPTSTA5_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA5) Stall Sent/CRC ISO Error/Number of Transaction Error */ -#define UDPHS_EPTSTA5_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA5) NAK IN/Bank Flush Error */ -#define UDPHS_EPTSTA5_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA5) NAK OUT */ -#define UDPHS_EPTSTA5_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA5) Current Bank/Control Direction */ -#define UDPHS_EPTSTA5_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA5) Busy Bank Number */ -#define UDPHS_EPTSTA5_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA5) UDPHS Byte Count */ -#define UDPHS_EPTSTA5_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA5) Short Packet */ -/* -------- UDPHS_EPTCFG6 : (UDPHS Offset: 0x1C0) UDPHS Endpoint Configuration Register (endpoint = 6) -------- */ -#define UDPHS_EPTCFG6_EPT_SIZE (0x7 << 0) /**< \brief (UDPHS_EPTCFG6) Endpoint Size */ -#define UDPHS_EPTCFG6_EPT_SIZE_8 (0x0 << 0) /**< \brief (UDPHS_EPTCFG6) 8 bytes */ -#define UDPHS_EPTCFG6_EPT_SIZE_16 (0x1 << 0) /**< \brief (UDPHS_EPTCFG6) 16 bytes */ -#define UDPHS_EPTCFG6_EPT_SIZE_32 (0x2 << 0) /**< \brief (UDPHS_EPTCFG6) 32 bytes */ -#define UDPHS_EPTCFG6_EPT_SIZE_64 (0x3 << 0) /**< \brief (UDPHS_EPTCFG6) 64 bytes */ -#define UDPHS_EPTCFG6_EPT_SIZE_128 (0x4 << 0) /**< \brief (UDPHS_EPTCFG6) 128 bytes */ -#define UDPHS_EPTCFG6_EPT_SIZE_256 (0x5 << 0) /**< \brief (UDPHS_EPTCFG6) 256 bytes */ -#define UDPHS_EPTCFG6_EPT_SIZE_512 (0x6 << 0) /**< \brief (UDPHS_EPTCFG6) 512 bytes */ -#define UDPHS_EPTCFG6_EPT_SIZE_1024 (0x7 << 0) /**< \brief (UDPHS_EPTCFG6) 1024 bytes */ -#define UDPHS_EPTCFG6_EPT_DIR (0x1 << 3) /**< \brief (UDPHS_EPTCFG6) Endpoint Direction */ -#define UDPHS_EPTCFG6_EPT_DIR_OUT (0x0 << 3) /**< \brief (UDPHS_EPTCFG6) Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG6_EPT_DIR_IN (0x1 << 3) /**< \brief (UDPHS_EPTCFG6) set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. */ -#define UDPHS_EPTCFG6_EPT_TYPE (0x3 << 4) /**< \brief (UDPHS_EPTCFG6) Endpoint Type */ -#define UDPHS_EPTCFG6_EPT_TYPE_CTL_EPT (0x0 << 4) /**< \brief (UDPHS_EPTCFG6) Control endpoint */ -#define UDPHS_EPTCFG6_EPT_TYPE_ISO_EPT (0x1 << 4) /**< \brief (UDPHS_EPTCFG6) Isochronous endpoint */ -#define UDPHS_EPTCFG6_EPT_TYPE_BUL_EPT (0x2 << 4) /**< \brief (UDPHS_EPTCFG6) Bulk endpoint */ -#define UDPHS_EPTCFG6_EPT_TYPE_INT_EPT (0x3 << 4) /**< \brief (UDPHS_EPTCFG6) Interrupt endpoint */ -#define UDPHS_EPTCFG6_BK_NUMBER (0x3 << 6) /**< \brief (UDPHS_EPTCFG6) Number of Banks */ -#define UDPHS_EPTCFG6_BK_NUMBER_0 (0x0 << 6) /**< \brief (UDPHS_EPTCFG6) Zero bank, the endpoint is not mapped in memory */ -#define UDPHS_EPTCFG6_BK_NUMBER_1 (0x1 << 6) /**< \brief (UDPHS_EPTCFG6) One bank (bank 0) */ -#define UDPHS_EPTCFG6_BK_NUMBER_2 (0x2 << 6) /**< \brief (UDPHS_EPTCFG6) Double bank (Ping-Pong: bank 0/bank 1) */ -#define UDPHS_EPTCFG6_BK_NUMBER_3 (0x3 << 6) /**< \brief (UDPHS_EPTCFG6) Triple bank (bank 0/bank 1/bank 2) */ -#define UDPHS_EPTCFG6_NB_TRANS (0x3 << 8) /**< \brief (UDPHS_EPTCFG6) Number Of Transaction per Microframe */ -#define UDPHS_EPTCFG6_EPT_MAPD (0x1 << 31) /**< \brief (UDPHS_EPTCFG6) Endpoint Mapped */ -/* -------- UDPHS_EPTCTLENB6 : (UDPHS Offset: 0x1C4) UDPHS Endpoint Control Enable Register (endpoint = 6) -------- */ -#define UDPHS_EPTCTLENB6_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLENB6) Endpoint Enable */ -#define UDPHS_EPTCTLENB6_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLENB6) Packet Auto-Valid Enable */ -#define UDPHS_EPTCTLENB6_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLENB6) Interrupts Disable DMA */ -#define UDPHS_EPTCTLENB6_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLENB6) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLENB6_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLENB6) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB6_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLENB6) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLENB6_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLENB6) Overflow Error Interrupt Enable */ -#define UDPHS_EPTCTLENB6_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLENB6) Received OUT Data Interrupt Enable */ -#define UDPHS_EPTCTLENB6_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLENB6) Transmitted IN Data Complete Interrupt Enable */ -#define UDPHS_EPTCTLENB6_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLENB6) TX Packet Ready/Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB6_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLENB6) Received SETUP/Error Flow Interrupt Enable */ -#define UDPHS_EPTCTLENB6_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLENB6) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */ -#define UDPHS_EPTCTLENB6_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLENB6) NAKIN/Bank Flush Error Interrupt Enable */ -#define UDPHS_EPTCTLENB6_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLENB6) NAKOUT Interrupt Enable */ -#define UDPHS_EPTCTLENB6_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLENB6) Busy Bank Interrupt Enable */ -#define UDPHS_EPTCTLENB6_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLENB6) Short Packet Send/Short Packet Interrupt Enable */ -/* -------- UDPHS_EPTCTLDIS6 : (UDPHS Offset: 0x1C8) UDPHS Endpoint Control Disable Register (endpoint = 6) -------- */ -#define UDPHS_EPTCTLDIS6_EPT_DISABL (0x1 << 0) /**< \brief (UDPHS_EPTCTLDIS6) Endpoint Disable */ -#define UDPHS_EPTCTLDIS6_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTLDIS6) Packet Auto-Valid Disable */ -#define UDPHS_EPTCTLDIS6_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTLDIS6) Interrupts Disable DMA */ -#define UDPHS_EPTCTLDIS6_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTLDIS6) NYET Enable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTLDIS6_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTLDIS6) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS6_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTLDIS6) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTLDIS6_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTLDIS6) Overflow Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTLDIS6) Received OUT Data Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTLDIS6) Transmitted IN Data Complete Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTLDIS6) TX Packet Ready/Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTLDIS6) Received SETUP/Error Flow Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTLDIS6) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTLDIS6) NAKIN/bank flush error Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTLDIS6) NAKOUT Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTLDIS6) Busy Bank Interrupt Disable */ -#define UDPHS_EPTCTLDIS6_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTLDIS6) Short Packet Interrupt Disable */ -/* -------- UDPHS_EPTCTL6 : (UDPHS Offset: 0x1CC) UDPHS Endpoint Control Register (endpoint = 6) -------- */ -#define UDPHS_EPTCTL6_EPT_ENABL (0x1 << 0) /**< \brief (UDPHS_EPTCTL6) Endpoint Enable */ -#define UDPHS_EPTCTL6_AUTO_VALID (0x1 << 1) /**< \brief (UDPHS_EPTCTL6) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */ -#define UDPHS_EPTCTL6_INTDIS_DMA (0x1 << 3) /**< \brief (UDPHS_EPTCTL6) Interrupt Disables DMA */ -#define UDPHS_EPTCTL6_NYET_DIS (0x1 << 4) /**< \brief (UDPHS_EPTCTL6) NYET Disable (Only for High Speed Bulk OUT endpoints) */ -#define UDPHS_EPTCTL6_DATAX_RX (0x1 << 6) /**< \brief (UDPHS_EPTCTL6) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL6_MDATA_RX (0x1 << 7) /**< \brief (UDPHS_EPTCTL6) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */ -#define UDPHS_EPTCTL6_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTCTL6) Overflow Error Interrupt Enabled */ -#define UDPHS_EPTCTL6_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCTL6) Received OUT Data Interrupt Enabled */ -#define UDPHS_EPTCTL6_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCTL6) Transmitted IN Data Complete Interrupt Enabled */ -#define UDPHS_EPTCTL6_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTCTL6) TX Packet Ready/Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL6_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCTL6) Received SETUP/Error Flow Interrupt Enabled */ -#define UDPHS_EPTCTL6_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCTL6) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */ -#define UDPHS_EPTCTL6_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCTL6) NAKIN/Bank Flush Error Interrupt Enabled */ -#define UDPHS_EPTCTL6_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCTL6) NAKOUT Interrupt Enabled */ -#define UDPHS_EPTCTL6_BUSY_BANK (0x1 << 18) /**< \brief (UDPHS_EPTCTL6) Busy Bank Interrupt Enabled */ -#define UDPHS_EPTCTL6_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTCTL6) Short Packet Interrupt Enabled */ -/* -------- UDPHS_EPTSETSTA6 : (UDPHS Offset: 0x1D4) UDPHS Endpoint Set Status Register (endpoint = 6) -------- */ -#define UDPHS_EPTSETSTA6_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSETSTA6) Stall Handshake Request Set */ -#define UDPHS_EPTSETSTA6_KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSETSTA6) KILL Bank Set (for IN Endpoint) */ -#define UDPHS_EPTSETSTA6_TX_PK_RDY (0x1 << 11) /**< \brief (UDPHS_EPTSETSTA6) TX Packet Ready Set */ -/* -------- UDPHS_EPTCLRSTA6 : (UDPHS Offset: 0x1D8) UDPHS Endpoint Clear Status Register (endpoint = 6) -------- */ -#define UDPHS_EPTCLRSTA6_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTCLRSTA6) Stall Handshake Request Clear */ -#define UDPHS_EPTCLRSTA6_TOGGLESQ (0x1 << 6) /**< \brief (UDPHS_EPTCLRSTA6) Data Toggle Clear */ -#define UDPHS_EPTCLRSTA6_RX_BK_RDY (0x1 << 9) /**< \brief (UDPHS_EPTCLRSTA6) Received OUT Data Clear */ -#define UDPHS_EPTCLRSTA6_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTCLRSTA6) Transmitted IN Data Complete Clear */ -#define UDPHS_EPTCLRSTA6_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTCLRSTA6) Received SETUP/Error Flow Clear */ -#define UDPHS_EPTCLRSTA6_STALL_SNT__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTCLRSTA6) Stall Sent/Number of Transaction Error Clear */ -#define UDPHS_EPTCLRSTA6_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTCLRSTA6) NAKIN/Bank Flush Error Clear */ -#define UDPHS_EPTCLRSTA6_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTCLRSTA6) NAKOUT Clear */ -/* -------- UDPHS_EPTSTA6 : (UDPHS Offset: 0x1DC) UDPHS Endpoint Status Register (endpoint = 6) -------- */ -#define UDPHS_EPTSTA6_FRCESTALL (0x1 << 5) /**< \brief (UDPHS_EPTSTA6) Stall Handshake Request */ -#define UDPHS_EPTSTA6_TOGGLESQ_STA (0x3 << 6) /**< \brief (UDPHS_EPTSTA6) Toggle Sequencing */ -#define UDPHS_EPTSTA6_ERR_OVFLW (0x1 << 8) /**< \brief (UDPHS_EPTSTA6) Overflow Error */ -#define UDPHS_EPTSTA6_RX_BK_RDY__KILL_BANK (0x1 << 9) /**< \brief (UDPHS_EPTSTA6) Received OUT Data/KILL Bank */ -#define UDPHS_EPTSTA6_TX_COMPLT (0x1 << 10) /**< \brief (UDPHS_EPTSTA6) Transmitted IN Data Complete */ -#define UDPHS_EPTSTA6_TX_PK_RDY__ERR_TRANS (0x1 << 11) /**< \brief (UDPHS_EPTSTA6) TX Packet Ready/Transaction Error */ -#define UDPHS_EPTSTA6_RX_SETUP__ERR_FL_ISO (0x1 << 12) /**< \brief (UDPHS_EPTSTA6) Received SETUP/Error Flow */ -#define UDPHS_EPTSTA6_STALL_SNT__ERR_CRISO__ERR_NBTRA (0x1 << 13) /**< \brief (UDPHS_EPTSTA6) Stall Sent/CRC ISO Error/Number of Transaction Error */ -#define UDPHS_EPTSTA6_NAK_IN__ERR_FLUSH (0x1 << 14) /**< \brief (UDPHS_EPTSTA6) NAK IN/Bank Flush Error */ -#define UDPHS_EPTSTA6_NAK_OUT (0x1 << 15) /**< \brief (UDPHS_EPTSTA6) NAK OUT */ -#define UDPHS_EPTSTA6_CURRENT_BANK__CONTROL_DIR (0x3 << 16) /**< \brief (UDPHS_EPTSTA6) Current Bank/Control Direction */ -#define UDPHS_EPTSTA6_BUSY_BANK_STA (0x3 << 18) /**< \brief (UDPHS_EPTSTA6) Busy Bank Number */ -#define UDPHS_EPTSTA6_BYTE_COUNT (0x7ff << 20) /**< \brief (UDPHS_EPTSTA6) UDPHS Byte Count */ -#define UDPHS_EPTSTA6_SHRT_PCKT (0x1 << 31) /**< \brief (UDPHS_EPTSTA6) Short Packet */ -/* -------- UDPHS_DMANXTDSC1 : (UDPHS Offset: 0x320) UDPHS DMA Next Descriptor Address Register (channel = 1) -------- */ -#define UDPHS_DMANXTDSC1_NXT_DSC_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMANXTDSC1) */ -/* -------- UDPHS_DMAADDRESS1 : (UDPHS Offset: 0x324) UDPHS DMA Channel Address Register (channel = 1) -------- */ -#define UDPHS_DMAADDRESS1_BUFF_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMAADDRESS1) */ -/* -------- UDPHS_DMACONTROL1 : (UDPHS Offset: 0x328) UDPHS DMA Channel Control Register (channel = 1) -------- */ -#define UDPHS_DMACONTROL1_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMACONTROL1) */ -#define UDPHS_DMACONTROL1_LDNXT_DSC (0x1 << 1) /**< \brief (UDPHS_DMACONTROL1) Load Next Channel Transfer Descriptor Enable (Command) */ -#define UDPHS_DMACONTROL1_END_TR_EN (0x1 << 2) /**< \brief (UDPHS_DMACONTROL1) End of Transfer Enable (Control) */ -#define UDPHS_DMACONTROL1_END_B_EN (0x1 << 3) /**< \brief (UDPHS_DMACONTROL1) End of Buffer Enable (Control) */ -#define UDPHS_DMACONTROL1_END_TR_IT (0x1 << 4) /**< \brief (UDPHS_DMACONTROL1) End of Transfer Interrupt Enable */ -#define UDPHS_DMACONTROL1_END_BUFFIT (0x1 << 5) /**< \brief (UDPHS_DMACONTROL1) End of Buffer Interrupt Enable */ -#define UDPHS_DMACONTROL1_DESC_LD_IT (0x1 << 6) /**< \brief (UDPHS_DMACONTROL1) Descriptor Loaded Interrupt Enable */ -#define UDPHS_DMACONTROL1_BURST_LCK (0x1 << 7) /**< \brief (UDPHS_DMACONTROL1) Burst Lock Enable */ -#define UDPHS_DMACONTROL1_BUFF_LENGTH (0xffff << 16) /**< \brief (UDPHS_DMACONTROL1) Buffer Byte Length (Write-only) */ -/* -------- UDPHS_DMASTATUS1 : (UDPHS Offset: 0x32C) UDPHS DMA Channel Status Register (channel = 1) -------- */ -#define UDPHS_DMASTATUS1_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMASTATUS1) Channel Enable Status */ -#define UDPHS_DMASTATUS1_CHANN_ACT (0x1 << 1) /**< \brief (UDPHS_DMASTATUS1) Channel Active Status */ -#define UDPHS_DMASTATUS1_END_TR_ST (0x1 << 4) /**< \brief (UDPHS_DMASTATUS1) End of Channel Transfer Status */ -#define UDPHS_DMASTATUS1_END_BF_ST (0x1 << 5) /**< \brief (UDPHS_DMASTATUS1) End of Channel Buffer Status */ -#define UDPHS_DMASTATUS1_DESC_LDST (0x1 << 6) /**< \brief (UDPHS_DMASTATUS1) Descriptor Loaded Status */ -#define UDPHS_DMASTATUS1_BUFF_COUNT (0xffff << 16) /**< \brief (UDPHS_DMASTATUS1) Buffer Byte Count */ -/* -------- UDPHS_DMANXTDSC2 : (UDPHS Offset: 0x330) UDPHS DMA Next Descriptor Address Register (channel = 2) -------- */ -#define UDPHS_DMANXTDSC2_NXT_DSC_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMANXTDSC2) */ -/* -------- UDPHS_DMAADDRESS2 : (UDPHS Offset: 0x334) UDPHS DMA Channel Address Register (channel = 2) -------- */ -#define UDPHS_DMAADDRESS2_BUFF_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMAADDRESS2) */ -/* -------- UDPHS_DMACONTROL2 : (UDPHS Offset: 0x338) UDPHS DMA Channel Control Register (channel = 2) -------- */ -#define UDPHS_DMACONTROL2_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMACONTROL2) */ -#define UDPHS_DMACONTROL2_LDNXT_DSC (0x1 << 1) /**< \brief (UDPHS_DMACONTROL2) Load Next Channel Transfer Descriptor Enable (Command) */ -#define UDPHS_DMACONTROL2_END_TR_EN (0x1 << 2) /**< \brief (UDPHS_DMACONTROL2) End of Transfer Enable (Control) */ -#define UDPHS_DMACONTROL2_END_B_EN (0x1 << 3) /**< \brief (UDPHS_DMACONTROL2) End of Buffer Enable (Control) */ -#define UDPHS_DMACONTROL2_END_TR_IT (0x1 << 4) /**< \brief (UDPHS_DMACONTROL2) End of Transfer Interrupt Enable */ -#define UDPHS_DMACONTROL2_END_BUFFIT (0x1 << 5) /**< \brief (UDPHS_DMACONTROL2) End of Buffer Interrupt Enable */ -#define UDPHS_DMACONTROL2_DESC_LD_IT (0x1 << 6) /**< \brief (UDPHS_DMACONTROL2) Descriptor Loaded Interrupt Enable */ -#define UDPHS_DMACONTROL2_BURST_LCK (0x1 << 7) /**< \brief (UDPHS_DMACONTROL2) Burst Lock Enable */ -#define UDPHS_DMACONTROL2_BUFF_LENGTH (0xffff << 16) /**< \brief (UDPHS_DMACONTROL2) Buffer Byte Length (Write-only) */ -/* -------- UDPHS_DMASTATUS2 : (UDPHS Offset: 0x33C) UDPHS DMA Channel Status Register (channel = 2) -------- */ -#define UDPHS_DMASTATUS2_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMASTATUS2) Channel Enable Status */ -#define UDPHS_DMASTATUS2_CHANN_ACT (0x1 << 1) /**< \brief (UDPHS_DMASTATUS2) Channel Active Status */ -#define UDPHS_DMASTATUS2_END_TR_ST (0x1 << 4) /**< \brief (UDPHS_DMASTATUS2) End of Channel Transfer Status */ -#define UDPHS_DMASTATUS2_END_BF_ST (0x1 << 5) /**< \brief (UDPHS_DMASTATUS2) End of Channel Buffer Status */ -#define UDPHS_DMASTATUS2_DESC_LDST (0x1 << 6) /**< \brief (UDPHS_DMASTATUS2) Descriptor Loaded Status */ -#define UDPHS_DMASTATUS2_BUFF_COUNT (0xffff << 16) /**< \brief (UDPHS_DMASTATUS2) Buffer Byte Count */ -/* -------- UDPHS_DMANXTDSC3 : (UDPHS Offset: 0x340) UDPHS DMA Next Descriptor Address Register (channel = 3) -------- */ -#define UDPHS_DMANXTDSC3_NXT_DSC_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMANXTDSC3) */ -/* -------- UDPHS_DMAADDRESS3 : (UDPHS Offset: 0x344) UDPHS DMA Channel Address Register (channel = 3) -------- */ -#define UDPHS_DMAADDRESS3_BUFF_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMAADDRESS3) */ -/* -------- UDPHS_DMACONTROL3 : (UDPHS Offset: 0x348) UDPHS DMA Channel Control Register (channel = 3) -------- */ -#define UDPHS_DMACONTROL3_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMACONTROL3) */ -#define UDPHS_DMACONTROL3_LDNXT_DSC (0x1 << 1) /**< \brief (UDPHS_DMACONTROL3) Load Next Channel Transfer Descriptor Enable (Command) */ -#define UDPHS_DMACONTROL3_END_TR_EN (0x1 << 2) /**< \brief (UDPHS_DMACONTROL3) End of Transfer Enable (Control) */ -#define UDPHS_DMACONTROL3_END_B_EN (0x1 << 3) /**< \brief (UDPHS_DMACONTROL3) End of Buffer Enable (Control) */ -#define UDPHS_DMACONTROL3_END_TR_IT (0x1 << 4) /**< \brief (UDPHS_DMACONTROL3) End of Transfer Interrupt Enable */ -#define UDPHS_DMACONTROL3_END_BUFFIT (0x1 << 5) /**< \brief (UDPHS_DMACONTROL3) End of Buffer Interrupt Enable */ -#define UDPHS_DMACONTROL3_DESC_LD_IT (0x1 << 6) /**< \brief (UDPHS_DMACONTROL3) Descriptor Loaded Interrupt Enable */ -#define UDPHS_DMACONTROL3_BURST_LCK (0x1 << 7) /**< \brief (UDPHS_DMACONTROL3) Burst Lock Enable */ -#define UDPHS_DMACONTROL3_BUFF_LENGTH (0xffff << 16) /**< \brief (UDPHS_DMACONTROL3) Buffer Byte Length (Write-only) */ -/* -------- UDPHS_DMASTATUS3 : (UDPHS Offset: 0x34C) UDPHS DMA Channel Status Register (channel = 3) -------- */ -#define UDPHS_DMASTATUS3_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMASTATUS3) Channel Enable Status */ -#define UDPHS_DMASTATUS3_CHANN_ACT (0x1 << 1) /**< \brief (UDPHS_DMASTATUS3) Channel Active Status */ -#define UDPHS_DMASTATUS3_END_TR_ST (0x1 << 4) /**< \brief (UDPHS_DMASTATUS3) End of Channel Transfer Status */ -#define UDPHS_DMASTATUS3_END_BF_ST (0x1 << 5) /**< \brief (UDPHS_DMASTATUS3) End of Channel Buffer Status */ -#define UDPHS_DMASTATUS3_DESC_LDST (0x1 << 6) /**< \brief (UDPHS_DMASTATUS3) Descriptor Loaded Status */ -#define UDPHS_DMASTATUS3_BUFF_COUNT (0xffff << 16) /**< \brief (UDPHS_DMASTATUS3) Buffer Byte Count */ -/* -------- UDPHS_DMANXTDSC4 : (UDPHS Offset: 0x350) UDPHS DMA Next Descriptor Address Register (channel = 4) -------- */ -#define UDPHS_DMANXTDSC4_NXT_DSC_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMANXTDSC4) */ -/* -------- UDPHS_DMAADDRESS4 : (UDPHS Offset: 0x354) UDPHS DMA Channel Address Register (channel = 4) -------- */ -#define UDPHS_DMAADDRESS4_BUFF_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMAADDRESS4) */ -/* -------- UDPHS_DMACONTROL4 : (UDPHS Offset: 0x358) UDPHS DMA Channel Control Register (channel = 4) -------- */ -#define UDPHS_DMACONTROL4_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMACONTROL4) */ -#define UDPHS_DMACONTROL4_LDNXT_DSC (0x1 << 1) /**< \brief (UDPHS_DMACONTROL4) Load Next Channel Transfer Descriptor Enable (Command) */ -#define UDPHS_DMACONTROL4_END_TR_EN (0x1 << 2) /**< \brief (UDPHS_DMACONTROL4) End of Transfer Enable (Control) */ -#define UDPHS_DMACONTROL4_END_B_EN (0x1 << 3) /**< \brief (UDPHS_DMACONTROL4) End of Buffer Enable (Control) */ -#define UDPHS_DMACONTROL4_END_TR_IT (0x1 << 4) /**< \brief (UDPHS_DMACONTROL4) End of Transfer Interrupt Enable */ -#define UDPHS_DMACONTROL4_END_BUFFIT (0x1 << 5) /**< \brief (UDPHS_DMACONTROL4) End of Buffer Interrupt Enable */ -#define UDPHS_DMACONTROL4_DESC_LD_IT (0x1 << 6) /**< \brief (UDPHS_DMACONTROL4) Descriptor Loaded Interrupt Enable */ -#define UDPHS_DMACONTROL4_BURST_LCK (0x1 << 7) /**< \brief (UDPHS_DMACONTROL4) Burst Lock Enable */ -#define UDPHS_DMACONTROL4_BUFF_LENGTH (0xffff << 16) /**< \brief (UDPHS_DMACONTROL4) Buffer Byte Length (Write-only) */ -/* -------- UDPHS_DMASTATUS4 : (UDPHS Offset: 0x35C) UDPHS DMA Channel Status Register (channel = 4) -------- */ -#define UDPHS_DMASTATUS4_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMASTATUS4) Channel Enable Status */ -#define UDPHS_DMASTATUS4_CHANN_ACT (0x1 << 1) /**< \brief (UDPHS_DMASTATUS4) Channel Active Status */ -#define UDPHS_DMASTATUS4_END_TR_ST (0x1 << 4) /**< \brief (UDPHS_DMASTATUS4) End of Channel Transfer Status */ -#define UDPHS_DMASTATUS4_END_BF_ST (0x1 << 5) /**< \brief (UDPHS_DMASTATUS4) End of Channel Buffer Status */ -#define UDPHS_DMASTATUS4_DESC_LDST (0x1 << 6) /**< \brief (UDPHS_DMASTATUS4) Descriptor Loaded Status */ -#define UDPHS_DMASTATUS4_BUFF_COUNT (0xffff << 16) /**< \brief (UDPHS_DMASTATUS4) Buffer Byte Count */ -/* -------- UDPHS_DMANXTDSC5 : (UDPHS Offset: 0x360) UDPHS DMA Next Descriptor Address Register (channel = 5) -------- */ -#define UDPHS_DMANXTDSC5_NXT_DSC_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMANXTDSC5) */ -/* -------- UDPHS_DMAADDRESS5 : (UDPHS Offset: 0x364) UDPHS DMA Channel Address Register (channel = 5) -------- */ -#define UDPHS_DMAADDRESS5_BUFF_ADD (0xffffffff << 0) /**< \brief (UDPHS_DMAADDRESS5) */ -/* -------- UDPHS_DMACONTROL5 : (UDPHS Offset: 0x368) UDPHS DMA Channel Control Register (channel = 5) -------- */ -#define UDPHS_DMACONTROL5_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMACONTROL5) */ -#define UDPHS_DMACONTROL5_LDNXT_DSC (0x1 << 1) /**< \brief (UDPHS_DMACONTROL5) Load Next Channel Transfer Descriptor Enable (Command) */ -#define UDPHS_DMACONTROL5_END_TR_EN (0x1 << 2) /**< \brief (UDPHS_DMACONTROL5) End of Transfer Enable (Control) */ -#define UDPHS_DMACONTROL5_END_B_EN (0x1 << 3) /**< \brief (UDPHS_DMACONTROL5) End of Buffer Enable (Control) */ -#define UDPHS_DMACONTROL5_END_TR_IT (0x1 << 4) /**< \brief (UDPHS_DMACONTROL5) End of Transfer Interrupt Enable */ -#define UDPHS_DMACONTROL5_END_BUFFIT (0x1 << 5) /**< \brief (UDPHS_DMACONTROL5) End of Buffer Interrupt Enable */ -#define UDPHS_DMACONTROL5_DESC_LD_IT (0x1 << 6) /**< \brief (UDPHS_DMACONTROL5) Descriptor Loaded Interrupt Enable */ -#define UDPHS_DMACONTROL5_BURST_LCK (0x1 << 7) /**< \brief (UDPHS_DMACONTROL5) Burst Lock Enable */ -#define UDPHS_DMACONTROL5_BUFF_LENGTH (0xffff << 16) /**< \brief (UDPHS_DMACONTROL5) Buffer Byte Length (Write-only) */ -/* -------- UDPHS_DMASTATUS5 : (UDPHS Offset: 0x36C) UDPHS DMA Channel Status Register (channel = 5) -------- */ -#define UDPHS_DMASTATUS5_CHANN_ENB (0x1 << 0) /**< \brief (UDPHS_DMASTATUS5) Channel Enable Status */ -#define UDPHS_DMASTATUS5_CHANN_ACT (0x1 << 1) /**< \brief (UDPHS_DMASTATUS5) Channel Active Status */ -#define UDPHS_DMASTATUS5_END_TR_ST (0x1 << 4) /**< \brief (UDPHS_DMASTATUS5) End of Channel Transfer Status */ -#define UDPHS_DMASTATUS5_END_BF_ST (0x1 << 5) /**< \brief (UDPHS_DMASTATUS5) End of Channel Buffer Status */ -#define UDPHS_DMASTATUS5_DESC_LDST (0x1 << 6) /**< \brief (UDPHS_DMASTATUS5) Descriptor Loaded Status */ -#define UDPHS_DMASTATUS5_BUFF_COUNT (0xffff << 16) /**< \brief (UDPHS_DMASTATUS5) Buffer Byte Count */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_USART Universal Synchronous Asynchronous Receiver Transmitter */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Usart hardware registers */ -typedef struct { - WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ - RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ - WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ - WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ - RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ - RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ - RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ - WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ - RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ - RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ - RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ - RwReg Reserved1[5]; - RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ - RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ - RwReg Reserved2[1]; - RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ - RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ - RwReg Reserved3[36]; - RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */ - RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */ - RwReg Reserved4[4]; - RoReg US_VERSION; /**< \brief (Usart Offset: 0xFC) Version Register */ - RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ - RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ - RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ - RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ - RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ - RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ - RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ - RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ - WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ - RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ -} Usart; -#endif /* __ASSEMBLY__ */ -/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ -#define US_CR_RSTRX (0x1 << 2) /**< \brief (US_CR) Reset Receiver */ -#define US_CR_RSTTX (0x1 << 3) /**< \brief (US_CR) Reset Transmitter */ -#define US_CR_RXEN (0x1 << 4) /**< \brief (US_CR) Receiver Enable */ -#define US_CR_RXDIS (0x1 << 5) /**< \brief (US_CR) Receiver Disable */ -#define US_CR_TXEN (0x1 << 6) /**< \brief (US_CR) Transmitter Enable */ -#define US_CR_TXDIS (0x1 << 7) /**< \brief (US_CR) Transmitter Disable */ -#define US_CR_RSTSTA (0x1 << 8) /**< \brief (US_CR) Reset Status Bits */ -#define US_CR_STTBRK (0x1 << 9) /**< \brief (US_CR) Start Break */ -#define US_CR_STPBRK (0x1 << 10) /**< \brief (US_CR) Stop Break */ -#define US_CR_STTTO (0x1 << 11) /**< \brief (US_CR) Start Time-out */ -#define US_CR_SENDA (0x1 << 12) /**< \brief (US_CR) Send Address */ -#define US_CR_RSTIT (0x1 << 13) /**< \brief (US_CR) Reset Iterations */ -#define US_CR_RSTNACK (0x1 << 14) /**< \brief (US_CR) Reset Non Acknowledge */ -#define US_CR_RETTO (0x1 << 15) /**< \brief (US_CR) Rearm Time-out */ -#define US_CR_RTSEN__FCS (0x1 << 18) /**< \brief (US_CR) Request to Send Enable/Force SPI Chip Select */ -#define US_CR_RTSDIS__RCS (0x1 << 19) /**< \brief (US_CR) Request to Send Disable/Release SPI Chip Select */ -/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ -#define US_MR_USART_MODE (0xf << 0) /**< \brief (US_MR) */ -#define US_MR_USCLKS (0x3 << 4) /**< \brief (US_MR) Clock Selection */ -#define US_MR_CHRL (0x3 << 6) /**< \brief (US_MR) Character Length. */ -#define US_MR_SYNC__CPHA (0x1 << 8) /**< \brief (US_MR) Synchronous Mode Select or SPI Clock Phase */ -#define US_MR_PAR (0x7 << 9) /**< \brief (US_MR) Parity Type */ -#define US_MR_NBSTOP (0x3 << 12) /**< \brief (US_MR) Number of Stop Bits */ -#define US_MR_CHMODE (0x3 << 14) /**< \brief (US_MR) Channel Mode */ -#define US_MR_MSBF__CPOL (0x1 << 16) /**< \brief (US_MR) Bit Order or SPI Clock Polarity */ -#define US_MR_MODE9 (0x1 << 17) /**< \brief (US_MR) 9-bit Character Length */ -#define US_MR_CLKO (0x1 << 18) /**< \brief (US_MR) Clock Output Select */ -#define US_MR_OVER (0x1 << 19) /**< \brief (US_MR) Oversampling Mode */ -#define US_MR_INACK (0x1 << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ -#define US_MR_DSNACK (0x1 << 21) /**< \brief (US_MR) Disable Successive NACK */ -#define US_MR_VAR_SYNC (0x1 << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ -#define US_MR_INVDATA (0x1 << 23) /**< \brief (US_MR) INverted Data */ -#define US_MR_MAX_ITERATION (0x7 << 24) /**< \brief (US_MR) */ -#define US_MR_FILTER (0x1 << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ -#define US_MR_MAN (0x1 << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ -#define US_MR_MODSYNC_ (0x1 << 30) /**< \brief (US_MR) */ -#define US_MR_ONEBIT (0x1 << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ -/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ -#define US_IER_RXRDY (0x1 << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ -#define US_IER_TXRDY (0x1 << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ -#define US_IER_RXBRK (0x1 << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ -#define US_IER_ENDRX (0x1 << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */ -#define US_IER_ENDTX (0x1 << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */ -#define US_IER_OVRE (0x1 << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ -#define US_IER_FRAME (0x1 << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ -#define US_IER_PARE (0x1 << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ -#define US_IER_TIMEOUT (0x1 << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ -#define US_IER_TXEMPTY (0x1 << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ -#define US_IER_ITER__UNRE (0x1 << 10) /**< \brief (US_IER) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IER_TXBUFE (0x1 << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */ -#define US_IER_RXBUFF (0x1 << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */ -#define US_IER_NACK (0x1 << 13) /**< \brief (US_IER) Non Acknowledge Interrupt Enable */ -#define US_IER_CTSIC (0x1 << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ -#define US_IER_MANE (0x1 << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ -/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ -#define US_IDR_RXRDY (0x1 << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ -#define US_IDR_TXRDY (0x1 << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ -#define US_IDR_RXBRK (0x1 << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ -#define US_IDR_ENDRX (0x1 << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */ -#define US_IDR_ENDTX (0x1 << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */ -#define US_IDR_OVRE (0x1 << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */ -#define US_IDR_FRAME (0x1 << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ -#define US_IDR_PARE (0x1 << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ -#define US_IDR_TIMEOUT (0x1 << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ -#define US_IDR_TXEMPTY (0x1 << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ -#define US_IDR_ITER__UNRE (0x1 << 10) /**< \brief (US_IDR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IDR_TXBUFE (0x1 << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */ -#define US_IDR_RXBUFF (0x1 << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */ -#define US_IDR_NACK (0x1 << 13) /**< \brief (US_IDR) Non Acknowledge Interrupt Disable */ -#define US_IDR_CTSIC (0x1 << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ -#define US_IDR_MANE (0x1 << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ -/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ -#define US_IMR_RXRDY (0x1 << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ -#define US_IMR_TXRDY (0x1 << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ -#define US_IMR_RXBRK (0x1 << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ -#define US_IMR_ENDRX (0x1 << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */ -#define US_IMR_ENDTX (0x1 << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */ -#define US_IMR_OVRE (0x1 << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ -#define US_IMR_FRAME (0x1 << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ -#define US_IMR_PARE (0x1 << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ -#define US_IMR_TIMEOUT (0x1 << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ -#define US_IMR_TXEMPTY (0x1 << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ -#define US_IMR_ITER__UNRE (0x1 << 10) /**< \brief (US_IMR) Iteration or SPI Underrun Error Interrupt Enable */ -#define US_IMR_TXBUFE (0x1 << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */ -#define US_IMR_RXBUFF (0x1 << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */ -#define US_IMR_NACK (0x1 << 13) /**< \brief (US_IMR) Non Acknowledge Interrupt Mask */ -#define US_IMR_CTSIC (0x1 << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ -#define US_IMR_MANE (0x1 << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ -/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ -#define US_CSR_RXRDY (0x1 << 0) /**< \brief (US_CSR) Receiver Ready */ -#define US_CSR_TXRDY (0x1 << 1) /**< \brief (US_CSR) Transmitter Ready */ -#define US_CSR_RXBRK (0x1 << 2) /**< \brief (US_CSR) Break Received/End of Break */ -#define US_CSR_ENDRX (0x1 << 3) /**< \brief (US_CSR) End of Receiver Transfer */ -#define US_CSR_ENDTX (0x1 << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ -#define US_CSR_OVRE (0x1 << 5) /**< \brief (US_CSR) Overrun Error */ -#define US_CSR_FRAME (0x1 << 6) /**< \brief (US_CSR) Framing Error */ -#define US_CSR_PARE (0x1 << 7) /**< \brief (US_CSR) Parity Error */ -#define US_CSR_TIMEOUT (0x1 << 8) /**< \brief (US_CSR) Receiver Time-out */ -#define US_CSR_TXEMPTY (0x1 << 9) /**< \brief (US_CSR) Transmitter Empty */ -#define US_CSR_ITER__UNRE (0x1 << 10) /**< \brief (US_CSR) Max number of Repetitions Reached or SPI Underrun Error */ -#define US_CSR_TXBUFE (0x1 << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ -#define US_CSR_RXBUFF (0x1 << 12) /**< \brief (US_CSR) Reception Buffer Full */ -#define US_CSR_NACK (0x1 << 13) /**< \brief (US_CSR) */ -#define US_CSR_CTSIC (0x1 << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ -#define US_CSR_CTS (0x1 << 23) /**< \brief (US_CSR) Image of CTS Input */ -#define US_CSR_MANERR (0x1 << 24) /**< \brief (US_CSR) Manchester Error */ -/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ -#define US_RHR_RXCHR (0x1ff << 0) /**< \brief (US_RHR) Received Character */ -#define US_RHR_RXSYNH (0x1 << 15) /**< \brief (US_RHR) Received Sync */ -/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ -#define US_THR_TXCHR (0x1ff << 0) /**< \brief (US_THR) Character to be Transmitted */ -#define US_THR_TXSYNH (0x1 << 15) /**< \brief (US_THR) Sync Field to be transmitted */ -/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ -#define US_BRGR_CD (0xffff << 0) /**< \brief (US_BRGR) Clock Divider */ -#define US_BRGR_FP (0x7 << 16) /**< \brief (US_BRGR) Fractional Part */ -/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ -#define US_RTOR_TO (0xffff << 0) /**< \brief (US_RTOR) Time-out Value */ -/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ -#define US_TTGR_TG (0xff << 0) /**< \brief (US_TTGR) Timeguard Value */ -/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ -#define US_FIDI_FI_DI_RATIO (0x7ff << 0) /**< \brief (US_FIDI) FI Over DI Ratio Value */ -/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ -#define US_NER_NB_ERRORS (0xff << 0) /**< \brief (US_NER) Number of Errors */ -/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ -#define US_IF_IRDA_FILTER (0xff << 0) /**< \brief (US_IF) IrDA Filter */ -/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ -#define US_MAN_TX_PL (0xf << 0) /**< \brief (US_MAN) Transmitter Preamble Length */ -#define US_MAN_TX_PP (0x3 << 8) /**< \brief (US_MAN) Transmitter Preamble Pattern */ -#define US_MAN_TX_MPOL (0x1 << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ -#define US_MAN_RX_PL (0xf << 16) /**< \brief (US_MAN) Receiver Preamble Length */ -#define US_MAN_RX_PP (0x3 << 24) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ -#define US_MAN_RX_MPOL (0x1 << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ -#define US_MAN_STUCKTO1 (0x1 << 29) /**< \brief (US_MAN) */ -#define US_MAN_DRIFT (0x1 << 30) /**< \brief (US_MAN) Drift compensation */ -/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */ -#define US_WPMR_WPEN (0x1 << 0) /**< \brief (US_WPMR) Write Protect Enable */ -#define US_WPMR_WPKEY (0xffffff << 8) /**< \brief (US_WPMR) Write Protect KEY */ -/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */ -#define US_WPSR_WPVS (0x1 << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ -#define US_WPSR_WPVSRC (0xffff << 8) /**< \brief (US_WPSR) Write Protect Violation Source */ -/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */ -#define US_VERSION_VERSION (0xfff << 0) /**< \brief (US_VERSION) */ -#define US_VERSION_MFN (0x7 << 16) /**< \brief (US_VERSION) */ -/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ -#define US_RPR_RXPTR (0xffffffff << 0) /**< \brief (US_RPR) Receive Pointer Register */ -/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ -#define US_RCR_RXCTR (0xffff << 0) /**< \brief (US_RCR) Receive Counter Register */ -/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ -#define US_TPR_TXPTR (0xffffffff << 0) /**< \brief (US_TPR) Transmit Counter Register */ -/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ -#define US_TCR_TXCTR (0xffff << 0) /**< \brief (US_TCR) Transmit Counter Register */ -/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ -#define US_RNPR_RXNPTR (0xffffffff << 0) /**< \brief (US_RNPR) Receive Next Pointer */ -/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ -#define US_RNCR_RXNCTR (0xffff << 0) /**< \brief (US_RNCR) Receive Next Counter */ -/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ -#define US_TNPR_TXNPTR (0xffffffff << 0) /**< \brief (US_TNPR) Transmit Next Pointer */ -/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ -#define US_TNCR_TXNCTR (0xffff << 0) /**< \brief (US_TNCR) Transmit Counter Next */ -/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ -#define US_PTCR_RXTEN (0x1 << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ -#define US_PTCR_RXTDIS (0x1 << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ -#define US_PTCR_TXTEN (0x1 << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ -#define US_PTCR_TXTDIS (0x1 << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ -/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ -#define US_PTSR_RXTEN (0x1 << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ -#define US_PTSR_TXTEN (0x1 << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ - -/*@}*/ - -/* ============================================================================= */ -/** SOFTWARE API DEFINITION FOR Watchdog Timer */ -/* ============================================================================= */ -/** \addtogroup AT91SAM3U_WDT Watchdog Timer */ -/*@{*/ - -#ifndef __ASSEMBLY__ -/** \brief Wdt hardware registers */ -typedef struct { - WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ - RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ - RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ -} Wdt; -#endif /* __ASSEMBLY__ */ -/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ -#define WDT_CR_WDRSTT (0x1 << 0) /**< \brief (WDT_CR) Watchdog Restart */ -#define WDT_CR_KEY (0xff << 24) /**< \brief (WDT_CR) Password */ -/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ -#define WDT_MR_WDV (0xfff << 0) /**< \brief (WDT_MR) Watchdog Counter Value */ -#define WDT_MR_WDFIEN (0x1 << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ -#define WDT_MR_WDRSTEN (0x1 << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ -#define WDT_MR_WDRPROC (0x1 << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ -#define WDT_MR_WDDIS (0x1 << 15) /**< \brief (WDT_MR) Watchdog Disable */ -#define WDT_MR_WDD (0xfff << 16) /**< \brief (WDT_MR) Watchdog Delta Value */ -#define WDT_MR_WDDBGHLT (0x1 << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ -#define WDT_MR_WDIDLEHLT (0x1 << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ -/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ -#define WDT_SR_WDUNF (0x1 << 0) /**< \brief (WDT_SR) Watchdog Underflow */ -#define WDT_SR_WDERR (0x1 << 1) /**< \brief (WDT_SR) Watchdog Error */ - -/*@}*/ - -/*@}*/ - -/* ***************************************************************************** */ -/* REGISTER ACCESS DEFINITIONS FOR AT91SAM3U */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3U_reg Registers Access Definitions */ -/*@{*/ - -/* ========== Register definition for HSMCI peripheral ========== */ -#define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */ -#define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */ -#define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ -#define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ -#define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */ -#define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */ -#define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */ -#define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ -#define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */ -#define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */ -#define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ -#define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */ -#define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ -#define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ -#define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ -#define REG_HSMCI_DMA REG_ACCESS(RwReg, 0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ -#define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */ -#define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ -#define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ -/* ========== Register definition for SSC peripheral ========== */ -#define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */ -#define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */ -#define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ -#define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ -#define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ -#define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ -#define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */ -#define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */ -#define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ -#define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ -#define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ -#define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ -#define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */ -#define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ -#define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ -#define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ -#define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ -#define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ -/* ========== Register definition for SPI peripheral ========== */ -#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */ -#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */ -#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */ -#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */ -#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */ -#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ -#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ -#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ -#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */ -#define REG_SPI_WPCR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ -#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ -/* ========== Register definition for TC0 peripheral ========== */ -#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ -#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ -#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */ -#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40080014U) /**< \brief (TC0) Register A (channel = 0) */ -#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40080018U) /**< \brief (TC0) Register B (channel = 0) */ -#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */ -#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */ -#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ -#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ -#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ -#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ -#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ -#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */ -#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40080054U) /**< \brief (TC0) Register A (channel = 1) */ -#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40080058U) /**< \brief (TC0) Register B (channel = 1) */ -#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */ -#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */ -#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ -#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ -#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ -#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ -#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ -#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */ -#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40080094U) /**< \brief (TC0) Register A (channel = 2) */ -#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40080098U) /**< \brief (TC0) Register B (channel = 2) */ -#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */ -#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */ -#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ -#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ -#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ -#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400800C0U) /**< \brief (TC0) Block Control Register */ -#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400800C4U) /**< \brief (TC0) Block Mode Register */ -#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ -#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ -#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ -#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ -#define REG_TC0_VER REG_ACCESS(RoReg, 0x400800FCU) /**< \brief (TC0) Version Register */ -/* ========== Register definition for TWI0 peripheral ========== */ -#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40084000U) /**< \brief (TWI0) Control Register */ -#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40084004U) /**< \brief (TWI0) Master Mode Register */ -#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40084008U) /**< \brief (TWI0) Slave Mode Register */ -#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4008400CU) /**< \brief (TWI0) Internal Address Register */ -#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40084010U) /**< \brief (TWI0) Clock Waveform Generator Register */ -#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40084020U) /**< \brief (TWI0) Status Register */ -#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40084024U) /**< \brief (TWI0) Interrupt Enable Register */ -#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40084028U) /**< \brief (TWI0) Interrupt Disable Register */ -#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4008402CU) /**< \brief (TWI0) Interrupt Mask Register */ -#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40084030U) /**< \brief (TWI0) Receive Holding Register */ -#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40084034U) /**< \brief (TWI0) Transmit Holding Register */ -#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40084100U) /**< \brief (TWI0) Receive Pointer Register */ -#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40084104U) /**< \brief (TWI0) Receive Counter Register */ -#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40084108U) /**< \brief (TWI0) Transmit Pointer Register */ -#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4008410CU) /**< \brief (TWI0) Transmit Counter Register */ -#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40084110U) /**< \brief (TWI0) Receive Next Pointer Register */ -#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40084114U) /**< \brief (TWI0) Receive Next Counter Register */ -#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40084118U) /**< \brief (TWI0) Transmit Next Pointer Register */ -#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4008411CU) /**< \brief (TWI0) Transmit Next Counter Register */ -#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40084120U) /**< \brief (TWI0) Transfer Control Register */ -#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40084124U) /**< \brief (TWI0) Transfer Status Register */ -/* ========== Register definition for TWI1 peripheral ========== */ -#define REG_TWI1_CR REG_ACCESS(WoReg, 0x40088000U) /**< \brief (TWI1) Control Register */ -#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x40088004U) /**< \brief (TWI1) Master Mode Register */ -#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x40088008U) /**< \brief (TWI1) Slave Mode Register */ -#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4008800CU) /**< \brief (TWI1) Internal Address Register */ -#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x40088010U) /**< \brief (TWI1) Clock Waveform Generator Register */ -#define REG_TWI1_SR REG_ACCESS(RoReg, 0x40088020U) /**< \brief (TWI1) Status Register */ -#define REG_TWI1_IER REG_ACCESS(WoReg, 0x40088024U) /**< \brief (TWI1) Interrupt Enable Register */ -#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x40088028U) /**< \brief (TWI1) Interrupt Disable Register */ -#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4008802CU) /**< \brief (TWI1) Interrupt Mask Register */ -#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x40088030U) /**< \brief (TWI1) Receive Holding Register */ -#define REG_TWI1_THR REG_ACCESS(WoReg, 0x40088034U) /**< \brief (TWI1) Transmit Holding Register */ -#define REG_TWI1_RPR REG_ACCESS(RwReg, 0x40088100U) /**< \brief (TWI1) Receive Pointer Register */ -#define REG_TWI1_RCR REG_ACCESS(RwReg, 0x40088104U) /**< \brief (TWI1) Receive Counter Register */ -#define REG_TWI1_TPR REG_ACCESS(RwReg, 0x40088108U) /**< \brief (TWI1) Transmit Pointer Register */ -#define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4008810CU) /**< \brief (TWI1) Transmit Counter Register */ -#define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x40088110U) /**< \brief (TWI1) Receive Next Pointer Register */ -#define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x40088114U) /**< \brief (TWI1) Receive Next Counter Register */ -#define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x40088118U) /**< \brief (TWI1) Transmit Next Pointer Register */ -#define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4008811CU) /**< \brief (TWI1) Transmit Next Counter Register */ -#define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x40088120U) /**< \brief (TWI1) Transfer Control Register */ -#define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x40088124U) /**< \brief (TWI1) Transfer Status Register */ -/* ========== Register definition for PWM peripheral ========== */ -#define REG_PWM_CLK REG_ACCESS(RwReg, 0x4008C000U) /**< \brief (PWM) PWM Clock Register */ -#define REG_PWM_ENA REG_ACCESS(WoReg, 0x4008C004U) /**< \brief (PWM) PWM Enable Register */ -#define REG_PWM_DIS REG_ACCESS(WoReg, 0x4008C008U) /**< \brief (PWM) PWM Disable Register */ -#define REG_PWM_SR REG_ACCESS(RoReg, 0x4008C00CU) /**< \brief (PWM) PWM Status Register */ -#define REG_PWM_IER1 REG_ACCESS(WoReg, 0x4008C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ -#define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x4008C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ -#define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x4008C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ -#define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4008C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ -#define REG_PWM_SCM REG_ACCESS(RwReg, 0x4008C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ -#define REG_PWM_SCUC REG_ACCESS(RwReg, 0x4008C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ -#define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4008C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ -#define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x4008C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ -#define REG_PWM_IER2 REG_ACCESS(WoReg, 0x4008C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ -#define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x4008C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ -#define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4008C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ -#define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x4008C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ -#define REG_PWM_OOV REG_ACCESS(RwReg, 0x4008C044U) /**< \brief (PWM) PWM Output Override Value Register */ -#define REG_PWM_OS REG_ACCESS(RwReg, 0x4008C048U) /**< \brief (PWM) PWM Output Selection Register */ -#define REG_PWM_OSS REG_ACCESS(WoReg, 0x4008C04CU) /**< \brief (PWM) PWM Output Selection Set Register */ -#define REG_PWM_OSC REG_ACCESS(WoReg, 0x4008C050U) /**< \brief (PWM) PWM Output Selection Clear Register */ -#define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x4008C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ -#define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x4008C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ -#define REG_PWM_FMR REG_ACCESS(RwReg, 0x4008C05CU) /**< \brief (PWM) PWM Fault Mode Register */ -#define REG_PWM_FSR REG_ACCESS(RoReg, 0x4008C060U) /**< \brief (PWM) PWM Fault Status Register */ -#define REG_PWM_FCR REG_ACCESS(WoReg, 0x4008C064U) /**< \brief (PWM) PWM Fault Clear Register */ -#define REG_PWM_FPV REG_ACCESS(RwReg, 0x4008C068U) /**< \brief (PWM) PWM Fault Protection Value Register */ -#define REG_PWM_FPE REG_ACCESS(RwReg, 0x4008C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ -#define REG_PWM_ELxMR REG_ACCESS(RwReg, 0x4008C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ -#define REG_PWM_WPCR REG_ACCESS(WoReg, 0x4008C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */ -#define REG_PWM_WPSR REG_ACCESS(RoReg, 0x4008C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */ -#define REG_PWM_RPR REG_ACCESS(RwReg, 0x4008C100U) /**< \brief (PWM) Receive Pointer Register */ -#define REG_PWM_RCR REG_ACCESS(RwReg, 0x4008C104U) /**< \brief (PWM) Receive Counter Register */ -#define REG_PWM_TPR REG_ACCESS(RwReg, 0x4008C108U) /**< \brief (PWM) Transmit Pointer Register */ -#define REG_PWM_TCR REG_ACCESS(RwReg, 0x4008C10CU) /**< \brief (PWM) Transmit Counter Register */ -#define REG_PWM_RNPR REG_ACCESS(RwReg, 0x4008C110U) /**< \brief (PWM) Receive Next Pointer Register */ -#define REG_PWM_RNCR REG_ACCESS(RwReg, 0x4008C114U) /**< \brief (PWM) Receive Next Counter Register */ -#define REG_PWM_TNPR REG_ACCESS(RwReg, 0x4008C118U) /**< \brief (PWM) Transmit Next Pointer Register */ -#define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4008C11CU) /**< \brief (PWM) Transmit Next Counter Register */ -#define REG_PWM_PTCR REG_ACCESS(WoReg, 0x4008C120U) /**< \brief (PWM) Transfer Control Register */ -#define REG_PWM_PTSR REG_ACCESS(RoReg, 0x4008C124U) /**< \brief (PWM) Transfer Status Register */ -#define REG_PWM_CMP0V REG_ACCESS(RwReg, 0x4008C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ -#define REG_PWM_CMP0VUPD REG_ACCESS(WoReg, 0x4008C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ -#define REG_PWM_CMP0M REG_ACCESS(RwReg, 0x4008C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ -#define REG_PWM_CMP0MUPD REG_ACCESS(WoReg, 0x4008C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ -#define REG_PWM_CMP1V REG_ACCESS(RwReg, 0x4008C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ -#define REG_PWM_CMP1VUPD REG_ACCESS(WoReg, 0x4008C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ -#define REG_PWM_CMP1M REG_ACCESS(RwReg, 0x4008C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ -#define REG_PWM_CMP1MUPD REG_ACCESS(WoReg, 0x4008C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ -#define REG_PWM_CMP2V REG_ACCESS(RwReg, 0x4008C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ -#define REG_PWM_CMP2VUPD REG_ACCESS(WoReg, 0x4008C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ -#define REG_PWM_CMP2M REG_ACCESS(RwReg, 0x4008C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ -#define REG_PWM_CMP2MUPD REG_ACCESS(WoReg, 0x4008C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ -#define REG_PWM_CMP3V REG_ACCESS(RwReg, 0x4008C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ -#define REG_PWM_CMP3VUPD REG_ACCESS(WoReg, 0x4008C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ -#define REG_PWM_CMP3M REG_ACCESS(RwReg, 0x4008C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ -#define REG_PWM_CMP3MUPD REG_ACCESS(WoReg, 0x4008C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ -#define REG_PWM_CMP4V REG_ACCESS(RwReg, 0x4008C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ -#define REG_PWM_CMP4VUPD REG_ACCESS(WoReg, 0x4008C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ -#define REG_PWM_CMP4M REG_ACCESS(RwReg, 0x4008C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ -#define REG_PWM_CMP4MUPD REG_ACCESS(WoReg, 0x4008C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ -#define REG_PWM_CMP5V REG_ACCESS(RwReg, 0x4008C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ -#define REG_PWM_CMP5VUPD REG_ACCESS(WoReg, 0x4008C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ -#define REG_PWM_CMP5M REG_ACCESS(RwReg, 0x4008C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ -#define REG_PWM_CMP5MUPD REG_ACCESS(WoReg, 0x4008C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ -#define REG_PWM_CMP6V REG_ACCESS(RwReg, 0x4008C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ -#define REG_PWM_CMP6VUPD REG_ACCESS(WoReg, 0x4008C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ -#define REG_PWM_CMP6M REG_ACCESS(RwReg, 0x4008C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ -#define REG_PWM_CMP6MUPD REG_ACCESS(WoReg, 0x4008C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ -#define REG_PWM_CMP7V REG_ACCESS(RwReg, 0x4008C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ -#define REG_PWM_CMP7VUPD REG_ACCESS(WoReg, 0x4008C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ -#define REG_PWM_CMP7M REG_ACCESS(RwReg, 0x4008C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ -#define REG_PWM_CMP7MUPD REG_ACCESS(WoReg, 0x4008C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ -#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x4008C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ -#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x4008C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ -#define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x4008C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ -#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4008C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ -#define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x4008C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ -#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x4008C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ -#define REG_PWM_DT0 REG_ACCESS(RwReg, 0x4008C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ -#define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4008C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ -#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x4008C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ -#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x4008C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ -#define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x4008C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ -#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4008C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ -#define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x4008C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ -#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x4008C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ -#define REG_PWM_DT1 REG_ACCESS(RwReg, 0x4008C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ -#define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4008C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ -#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x4008C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ -#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x4008C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ -#define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x4008C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ -#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4008C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ -#define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x4008C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ -#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x4008C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ -#define REG_PWM_DT2 REG_ACCESS(RwReg, 0x4008C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ -#define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4008C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ -#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x4008C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ -#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x4008C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ -#define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x4008C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ -#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4008C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ -#define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x4008C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ -#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x4008C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ -#define REG_PWM_DT3 REG_ACCESS(RwReg, 0x4008C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ -#define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4008C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ -/* ========== Register definition for USART0 peripheral ========== */ -#define REG_USART0_CR REG_ACCESS(WoReg, 0x40090000U) /**< \brief (USART0) Control Register */ -#define REG_USART0_MR REG_ACCESS(RwReg, 0x40090004U) /**< \brief (USART0) Mode Register */ -#define REG_USART0_IER REG_ACCESS(WoReg, 0x40090008U) /**< \brief (USART0) Interrupt Enable Register */ -#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4009000CU) /**< \brief (USART0) Interrupt Disable Register */ -#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40090010U) /**< \brief (USART0) Interrupt Mask Register */ -#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40090014U) /**< \brief (USART0) Channel Status Register */ -#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40090018U) /**< \brief (USART0) Receiver Holding Register */ -#define REG_USART0_THR REG_ACCESS(WoReg, 0x4009001CU) /**< \brief (USART0) Transmitter Holding Register */ -#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40090020U) /**< \brief (USART0) Baud Rate Generator Register */ -#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40090024U) /**< \brief (USART0) Receiver Time-out Register */ -#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40090028U) /**< \brief (USART0) Transmitter Timeguard Register */ -#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40090040U) /**< \brief (USART0) FI DI Ratio Register */ -#define REG_USART0_NER REG_ACCESS(RoReg, 0x40090044U) /**< \brief (USART0) Number of Errors Register */ -#define REG_USART0_IF REG_ACCESS(RwReg, 0x4009004CU) /**< \brief (USART0) IrDA Filter Register */ -#define REG_USART0_MAN REG_ACCESS(RwReg, 0x40090050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ -#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400900E4U) /**< \brief (USART0) Write Protect Mode Register */ -#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400900E8U) /**< \brief (USART0) Write Protect Status Register */ -#define REG_USART0_VERSION REG_ACCESS(RoReg, 0x400900FCU) /**< \brief (USART0) Version Register */ -#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40090100U) /**< \brief (USART0) Receive Pointer Register */ -#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40090104U) /**< \brief (USART0) Receive Counter Register */ -#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40090108U) /**< \brief (USART0) Transmit Pointer Register */ -#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4009010CU) /**< \brief (USART0) Transmit Counter Register */ -#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40090110U) /**< \brief (USART0) Receive Next Pointer Register */ -#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40090114U) /**< \brief (USART0) Receive Next Counter Register */ -#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40090118U) /**< \brief (USART0) Transmit Next Pointer Register */ -#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4009011CU) /**< \brief (USART0) Transmit Next Counter Register */ -#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40090120U) /**< \brief (USART0) Transfer Control Register */ -#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40090124U) /**< \brief (USART0) Transfer Status Register */ -/* ========== Register definition for USART1 peripheral ========== */ -#define REG_USART1_CR REG_ACCESS(WoReg, 0x40094000U) /**< \brief (USART1) Control Register */ -#define REG_USART1_MR REG_ACCESS(RwReg, 0x40094004U) /**< \brief (USART1) Mode Register */ -#define REG_USART1_IER REG_ACCESS(WoReg, 0x40094008U) /**< \brief (USART1) Interrupt Enable Register */ -#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4009400CU) /**< \brief (USART1) Interrupt Disable Register */ -#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40094010U) /**< \brief (USART1) Interrupt Mask Register */ -#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40094014U) /**< \brief (USART1) Channel Status Register */ -#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40094018U) /**< \brief (USART1) Receiver Holding Register */ -#define REG_USART1_THR REG_ACCESS(WoReg, 0x4009401CU) /**< \brief (USART1) Transmitter Holding Register */ -#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40094020U) /**< \brief (USART1) Baud Rate Generator Register */ -#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40094024U) /**< \brief (USART1) Receiver Time-out Register */ -#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40094028U) /**< \brief (USART1) Transmitter Timeguard Register */ -#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40094040U) /**< \brief (USART1) FI DI Ratio Register */ -#define REG_USART1_NER REG_ACCESS(RoReg, 0x40094044U) /**< \brief (USART1) Number of Errors Register */ -#define REG_USART1_IF REG_ACCESS(RwReg, 0x4009404CU) /**< \brief (USART1) IrDA Filter Register */ -#define REG_USART1_MAN REG_ACCESS(RwReg, 0x40094050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ -#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400940E4U) /**< \brief (USART1) Write Protect Mode Register */ -#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400940E8U) /**< \brief (USART1) Write Protect Status Register */ -#define REG_USART1_VERSION REG_ACCESS(RoReg, 0x400940FCU) /**< \brief (USART1) Version Register */ -#define REG_USART1_RPR REG_ACCESS(RwReg, 0x40094100U) /**< \brief (USART1) Receive Pointer Register */ -#define REG_USART1_RCR REG_ACCESS(RwReg, 0x40094104U) /**< \brief (USART1) Receive Counter Register */ -#define REG_USART1_TPR REG_ACCESS(RwReg, 0x40094108U) /**< \brief (USART1) Transmit Pointer Register */ -#define REG_USART1_TCR REG_ACCESS(RwReg, 0x4009410CU) /**< \brief (USART1) Transmit Counter Register */ -#define REG_USART1_RNPR REG_ACCESS(RwReg, 0x40094110U) /**< \brief (USART1) Receive Next Pointer Register */ -#define REG_USART1_RNCR REG_ACCESS(RwReg, 0x40094114U) /**< \brief (USART1) Receive Next Counter Register */ -#define REG_USART1_TNPR REG_ACCESS(RwReg, 0x40094118U) /**< \brief (USART1) Transmit Next Pointer Register */ -#define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4009411CU) /**< \brief (USART1) Transmit Next Counter Register */ -#define REG_USART1_PTCR REG_ACCESS(WoReg, 0x40094120U) /**< \brief (USART1) Transfer Control Register */ -#define REG_USART1_PTSR REG_ACCESS(RoReg, 0x40094124U) /**< \brief (USART1) Transfer Status Register */ -/* ========== Register definition for USART2 peripheral ========== */ -#define REG_USART2_CR REG_ACCESS(WoReg, 0x40098000U) /**< \brief (USART2) Control Register */ -#define REG_USART2_MR REG_ACCESS(RwReg, 0x40098004U) /**< \brief (USART2) Mode Register */ -#define REG_USART2_IER REG_ACCESS(WoReg, 0x40098008U) /**< \brief (USART2) Interrupt Enable Register */ -#define REG_USART2_IDR REG_ACCESS(WoReg, 0x4009800CU) /**< \brief (USART2) Interrupt Disable Register */ -#define REG_USART2_IMR REG_ACCESS(RoReg, 0x40098010U) /**< \brief (USART2) Interrupt Mask Register */ -#define REG_USART2_CSR REG_ACCESS(RoReg, 0x40098014U) /**< \brief (USART2) Channel Status Register */ -#define REG_USART2_RHR REG_ACCESS(RoReg, 0x40098018U) /**< \brief (USART2) Receiver Holding Register */ -#define REG_USART2_THR REG_ACCESS(WoReg, 0x4009801CU) /**< \brief (USART2) Transmitter Holding Register */ -#define REG_USART2_BRGR REG_ACCESS(RwReg, 0x40098020U) /**< \brief (USART2) Baud Rate Generator Register */ -#define REG_USART2_RTOR REG_ACCESS(RwReg, 0x40098024U) /**< \brief (USART2) Receiver Time-out Register */ -#define REG_USART2_TTGR REG_ACCESS(RwReg, 0x40098028U) /**< \brief (USART2) Transmitter Timeguard Register */ -#define REG_USART2_FIDI REG_ACCESS(RwReg, 0x40098040U) /**< \brief (USART2) FI DI Ratio Register */ -#define REG_USART2_NER REG_ACCESS(RoReg, 0x40098044U) /**< \brief (USART2) Number of Errors Register */ -#define REG_USART2_IF REG_ACCESS(RwReg, 0x4009804CU) /**< \brief (USART2) IrDA Filter Register */ -#define REG_USART2_MAN REG_ACCESS(RwReg, 0x40098050U) /**< \brief (USART2) Manchester Encoder Decoder Register */ -#define REG_USART2_WPMR REG_ACCESS(RwReg, 0x400980E4U) /**< \brief (USART2) Write Protect Mode Register */ -#define REG_USART2_WPSR REG_ACCESS(RoReg, 0x400980E8U) /**< \brief (USART2) Write Protect Status Register */ -#define REG_USART2_VERSION REG_ACCESS(RoReg, 0x400980FCU) /**< \brief (USART2) Version Register */ -#define REG_USART2_RPR REG_ACCESS(RwReg, 0x40098100U) /**< \brief (USART2) Receive Pointer Register */ -#define REG_USART2_RCR REG_ACCESS(RwReg, 0x40098104U) /**< \brief (USART2) Receive Counter Register */ -#define REG_USART2_TPR REG_ACCESS(RwReg, 0x40098108U) /**< \brief (USART2) Transmit Pointer Register */ -#define REG_USART2_TCR REG_ACCESS(RwReg, 0x4009810CU) /**< \brief (USART2) Transmit Counter Register */ -#define REG_USART2_RNPR REG_ACCESS(RwReg, 0x40098110U) /**< \brief (USART2) Receive Next Pointer Register */ -#define REG_USART2_RNCR REG_ACCESS(RwReg, 0x40098114U) /**< \brief (USART2) Receive Next Counter Register */ -#define REG_USART2_TNPR REG_ACCESS(RwReg, 0x40098118U) /**< \brief (USART2) Transmit Next Pointer Register */ -#define REG_USART2_TNCR REG_ACCESS(RwReg, 0x4009811CU) /**< \brief (USART2) Transmit Next Counter Register */ -#define REG_USART2_PTCR REG_ACCESS(WoReg, 0x40098120U) /**< \brief (USART2) Transfer Control Register */ -#define REG_USART2_PTSR REG_ACCESS(RoReg, 0x40098124U) /**< \brief (USART2) Transfer Status Register */ -/* ========== Register definition for USART3 peripheral ========== */ -#define REG_USART3_CR REG_ACCESS(WoReg, 0x4009C000U) /**< \brief (USART3) Control Register */ -#define REG_USART3_MR REG_ACCESS(RwReg, 0x4009C004U) /**< \brief (USART3) Mode Register */ -#define REG_USART3_IER REG_ACCESS(WoReg, 0x4009C008U) /**< \brief (USART3) Interrupt Enable Register */ -#define REG_USART3_IDR REG_ACCESS(WoReg, 0x4009C00CU) /**< \brief (USART3) Interrupt Disable Register */ -#define REG_USART3_IMR REG_ACCESS(RoReg, 0x4009C010U) /**< \brief (USART3) Interrupt Mask Register */ -#define REG_USART3_CSR REG_ACCESS(RoReg, 0x4009C014U) /**< \brief (USART3) Channel Status Register */ -#define REG_USART3_RHR REG_ACCESS(RoReg, 0x4009C018U) /**< \brief (USART3) Receiver Holding Register */ -#define REG_USART3_THR REG_ACCESS(WoReg, 0x4009C01CU) /**< \brief (USART3) Transmitter Holding Register */ -#define REG_USART3_BRGR REG_ACCESS(RwReg, 0x4009C020U) /**< \brief (USART3) Baud Rate Generator Register */ -#define REG_USART3_RTOR REG_ACCESS(RwReg, 0x4009C024U) /**< \brief (USART3) Receiver Time-out Register */ -#define REG_USART3_TTGR REG_ACCESS(RwReg, 0x4009C028U) /**< \brief (USART3) Transmitter Timeguard Register */ -#define REG_USART3_FIDI REG_ACCESS(RwReg, 0x4009C040U) /**< \brief (USART3) FI DI Ratio Register */ -#define REG_USART3_NER REG_ACCESS(RoReg, 0x4009C044U) /**< \brief (USART3) Number of Errors Register */ -#define REG_USART3_IF REG_ACCESS(RwReg, 0x4009C04CU) /**< \brief (USART3) IrDA Filter Register */ -#define REG_USART3_MAN REG_ACCESS(RwReg, 0x4009C050U) /**< \brief (USART3) Manchester Encoder Decoder Register */ -#define REG_USART3_WPMR REG_ACCESS(RwReg, 0x4009C0E4U) /**< \brief (USART3) Write Protect Mode Register */ -#define REG_USART3_WPSR REG_ACCESS(RoReg, 0x4009C0E8U) /**< \brief (USART3) Write Protect Status Register */ -#define REG_USART3_VERSION REG_ACCESS(RoReg, 0x4009C0FCU) /**< \brief (USART3) Version Register */ -#define REG_USART3_RPR REG_ACCESS(RwReg, 0x4009C100U) /**< \brief (USART3) Receive Pointer Register */ -#define REG_USART3_RCR REG_ACCESS(RwReg, 0x4009C104U) /**< \brief (USART3) Receive Counter Register */ -#define REG_USART3_TPR REG_ACCESS(RwReg, 0x4009C108U) /**< \brief (USART3) Transmit Pointer Register */ -#define REG_USART3_TCR REG_ACCESS(RwReg, 0x4009C10CU) /**< \brief (USART3) Transmit Counter Register */ -#define REG_USART3_RNPR REG_ACCESS(RwReg, 0x4009C110U) /**< \brief (USART3) Receive Next Pointer Register */ -#define REG_USART3_RNCR REG_ACCESS(RwReg, 0x4009C114U) /**< \brief (USART3) Receive Next Counter Register */ -#define REG_USART3_TNPR REG_ACCESS(RwReg, 0x4009C118U) /**< \brief (USART3) Transmit Next Pointer Register */ -#define REG_USART3_TNCR REG_ACCESS(RwReg, 0x4009C11CU) /**< \brief (USART3) Transmit Next Counter Register */ -#define REG_USART3_PTCR REG_ACCESS(WoReg, 0x4009C120U) /**< \brief (USART3) Transfer Control Register */ -#define REG_USART3_PTSR REG_ACCESS(RoReg, 0x4009C124U) /**< \brief (USART3) Transfer Status Register */ -/* ========== Register definition for UDPHS peripheral ========== */ -#define REG_UDPHS_CTRL REG_ACCESS(RwReg, 0x400A4000U) /**< \brief (UDPHS) UDPHS Control Register */ -#define REG_UDPHS_FNUM REG_ACCESS(RoReg, 0x400A4004U) /**< \brief (UDPHS) UDPHS Frame Number Register */ -#define REG_UDPHS_IEN REG_ACCESS(RwReg, 0x400A4010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */ -#define REG_UDPHS_INTSTA REG_ACCESS(RoReg, 0x400A4014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */ -#define REG_UDPHS_CLRINT REG_ACCESS(WoReg, 0x400A4018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */ -#define REG_UDPHS_EPTRST REG_ACCESS(WoReg, 0x400A401CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */ -#define REG_UDPHS_TST REG_ACCESS(RwReg, 0x400A40E0U) /**< \brief (UDPHS) UDPHS Test Register */ -#define REG_UDPHS_IPNAME1 REG_ACCESS(RoReg, 0x400A40F0U) /**< \brief (UDPHS) UDPHS Name1 Register */ -#define REG_UDPHS_IPNAME2 REG_ACCESS(RoReg, 0x400A40F4U) /**< \brief (UDPHS) UDPHS Name2 Register */ -#define REG_UDPHS_IPFEATURES REG_ACCESS(RoReg, 0x400A40F8U) /**< \brief (UDPHS) UDPHS Features Register */ -#define REG_UDPHS_EPTCFG0 REG_ACCESS(RwReg, 0x400A4100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */ -#define REG_UDPHS_EPTCTLENB0 REG_ACCESS(WoReg, 0x400A4104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */ -#define REG_UDPHS_EPTCTLDIS0 REG_ACCESS(WoReg, 0x400A4108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */ -#define REG_UDPHS_EPTCTL0 REG_ACCESS(RoReg, 0x400A410CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */ -#define REG_UDPHS_EPTSETSTA0 REG_ACCESS(WoReg, 0x400A4114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */ -#define REG_UDPHS_EPTCLRSTA0 REG_ACCESS(WoReg, 0x400A4118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */ -#define REG_UDPHS_EPTSTA0 REG_ACCESS(RoReg, 0x400A411CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */ -#define REG_UDPHS_EPTCFG1 REG_ACCESS(RwReg, 0x400A4120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */ -#define REG_UDPHS_EPTCTLENB1 REG_ACCESS(WoReg, 0x400A4124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */ -#define REG_UDPHS_EPTCTLDIS1 REG_ACCESS(WoReg, 0x400A4128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */ -#define REG_UDPHS_EPTCTL1 REG_ACCESS(RoReg, 0x400A412CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */ -#define REG_UDPHS_EPTSETSTA1 REG_ACCESS(WoReg, 0x400A4134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */ -#define REG_UDPHS_EPTCLRSTA1 REG_ACCESS(WoReg, 0x400A4138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */ -#define REG_UDPHS_EPTSTA1 REG_ACCESS(RoReg, 0x400A413CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */ -#define REG_UDPHS_EPTCFG2 REG_ACCESS(RwReg, 0x400A4140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */ -#define REG_UDPHS_EPTCTLENB2 REG_ACCESS(WoReg, 0x400A4144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */ -#define REG_UDPHS_EPTCTLDIS2 REG_ACCESS(WoReg, 0x400A4148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */ -#define REG_UDPHS_EPTCTL2 REG_ACCESS(RoReg, 0x400A414CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */ -#define REG_UDPHS_EPTSETSTA2 REG_ACCESS(WoReg, 0x400A4154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */ -#define REG_UDPHS_EPTCLRSTA2 REG_ACCESS(WoReg, 0x400A4158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */ -#define REG_UDPHS_EPTSTA2 REG_ACCESS(RoReg, 0x400A415CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */ -#define REG_UDPHS_EPTCFG3 REG_ACCESS(RwReg, 0x400A4160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */ -#define REG_UDPHS_EPTCTLENB3 REG_ACCESS(WoReg, 0x400A4164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */ -#define REG_UDPHS_EPTCTLDIS3 REG_ACCESS(WoReg, 0x400A4168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */ -#define REG_UDPHS_EPTCTL3 REG_ACCESS(RoReg, 0x400A416CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */ -#define REG_UDPHS_EPTSETSTA3 REG_ACCESS(WoReg, 0x400A4174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */ -#define REG_UDPHS_EPTCLRSTA3 REG_ACCESS(WoReg, 0x400A4178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */ -#define REG_UDPHS_EPTSTA3 REG_ACCESS(RoReg, 0x400A417CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */ -#define REG_UDPHS_EPTCFG4 REG_ACCESS(RwReg, 0x400A4180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */ -#define REG_UDPHS_EPTCTLENB4 REG_ACCESS(WoReg, 0x400A4184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */ -#define REG_UDPHS_EPTCTLDIS4 REG_ACCESS(WoReg, 0x400A4188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */ -#define REG_UDPHS_EPTCTL4 REG_ACCESS(RoReg, 0x400A418CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */ -#define REG_UDPHS_EPTSETSTA4 REG_ACCESS(WoReg, 0x400A4194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */ -#define REG_UDPHS_EPTCLRSTA4 REG_ACCESS(WoReg, 0x400A4198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */ -#define REG_UDPHS_EPTSTA4 REG_ACCESS(RoReg, 0x400A419CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */ -#define REG_UDPHS_EPTCFG5 REG_ACCESS(RwReg, 0x400A41A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */ -#define REG_UDPHS_EPTCTLENB5 REG_ACCESS(WoReg, 0x400A41A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */ -#define REG_UDPHS_EPTCTLDIS5 REG_ACCESS(WoReg, 0x400A41A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */ -#define REG_UDPHS_EPTCTL5 REG_ACCESS(RoReg, 0x400A41ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */ -#define REG_UDPHS_EPTSETSTA5 REG_ACCESS(WoReg, 0x400A41B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */ -#define REG_UDPHS_EPTCLRSTA5 REG_ACCESS(WoReg, 0x400A41B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */ -#define REG_UDPHS_EPTSTA5 REG_ACCESS(RoReg, 0x400A41BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */ -#define REG_UDPHS_EPTCFG6 REG_ACCESS(RwReg, 0x400A41C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */ -#define REG_UDPHS_EPTCTLENB6 REG_ACCESS(WoReg, 0x400A41C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */ -#define REG_UDPHS_EPTCTLDIS6 REG_ACCESS(WoReg, 0x400A41C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */ -#define REG_UDPHS_EPTCTL6 REG_ACCESS(RoReg, 0x400A41CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */ -#define REG_UDPHS_EPTSETSTA6 REG_ACCESS(WoReg, 0x400A41D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */ -#define REG_UDPHS_EPTCLRSTA6 REG_ACCESS(WoReg, 0x400A41D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */ -#define REG_UDPHS_EPTSTA6 REG_ACCESS(RoReg, 0x400A41DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */ -#define REG_UDPHS_DMANXTDSC1 REG_ACCESS(RwReg, 0x400A4320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */ -#define REG_UDPHS_DMAADDRESS1 REG_ACCESS(RwReg, 0x400A4324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */ -#define REG_UDPHS_DMACONTROL1 REG_ACCESS(RwReg, 0x400A4328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */ -#define REG_UDPHS_DMASTATUS1 REG_ACCESS(RwReg, 0x400A432CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */ -#define REG_UDPHS_DMANXTDSC2 REG_ACCESS(RwReg, 0x400A4330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */ -#define REG_UDPHS_DMAADDRESS2 REG_ACCESS(RwReg, 0x400A4334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */ -#define REG_UDPHS_DMACONTROL2 REG_ACCESS(RwReg, 0x400A4338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */ -#define REG_UDPHS_DMASTATUS2 REG_ACCESS(RwReg, 0x400A433CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */ -#define REG_UDPHS_DMANXTDSC3 REG_ACCESS(RwReg, 0x400A4340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */ -#define REG_UDPHS_DMAADDRESS3 REG_ACCESS(RwReg, 0x400A4344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */ -#define REG_UDPHS_DMACONTROL3 REG_ACCESS(RwReg, 0x400A4348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */ -#define REG_UDPHS_DMASTATUS3 REG_ACCESS(RwReg, 0x400A434CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */ -#define REG_UDPHS_DMANXTDSC4 REG_ACCESS(RwReg, 0x400A4350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */ -#define REG_UDPHS_DMAADDRESS4 REG_ACCESS(RwReg, 0x400A4354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */ -#define REG_UDPHS_DMACONTROL4 REG_ACCESS(RwReg, 0x400A4358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */ -#define REG_UDPHS_DMASTATUS4 REG_ACCESS(RwReg, 0x400A435CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */ -#define REG_UDPHS_DMANXTDSC5 REG_ACCESS(RwReg, 0x400A4360U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */ -#define REG_UDPHS_DMAADDRESS5 REG_ACCESS(RwReg, 0x400A4364U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */ -#define REG_UDPHS_DMACONTROL5 REG_ACCESS(RwReg, 0x400A4368U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */ -#define REG_UDPHS_DMASTATUS5 REG_ACCESS(RwReg, 0x400A436CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */ -/* ========== Register definition for ADC12B peripheral ========== */ -#define REG_ADC12B_CR REG_ACCESS(WoReg, 0x400A8000U) /**< \brief (ADC12B) Control Register */ -#define REG_ADC12B_MR REG_ACCESS(RwReg, 0x400A8004U) /**< \brief (ADC12B) Mode Register */ -#define REG_ADC12B_CHER REG_ACCESS(WoReg, 0x400A8010U) /**< \brief (ADC12B) Channel Enable Register */ -#define REG_ADC12B_CHDR REG_ACCESS(WoReg, 0x400A8014U) /**< \brief (ADC12B) Channel Disable Register */ -#define REG_ADC12B_CHSR REG_ACCESS(RoReg, 0x400A8018U) /**< \brief (ADC12B) Channel Status Register */ -#define REG_ADC12B_SR REG_ACCESS(RoReg, 0x400A801CU) /**< \brief (ADC12B) Status Register */ -#define REG_ADC12B_LCDR REG_ACCESS(RoReg, 0x400A8020U) /**< \brief (ADC12B) Last Converted Data Register */ -#define REG_ADC12B_IER REG_ACCESS(WoReg, 0x400A8024U) /**< \brief (ADC12B) Interrupt Enable Register */ -#define REG_ADC12B_IDR REG_ACCESS(WoReg, 0x400A8028U) /**< \brief (ADC12B) Interrupt Disable Register */ -#define REG_ADC12B_IMR REG_ACCESS(RoReg, 0x400A802CU) /**< \brief (ADC12B) Interrupt Mask Register */ -#define REG_ADC12B_CDR REG_ACCESS(RoReg, 0x400A8030U) /**< \brief (ADC12B) Channel Data Register */ -#define REG_ADC12B_ACR REG_ACCESS(RwReg, 0x400A8064U) /**< \brief (ADC12B) Analog Control Register */ -#define REG_ADC12B_EMR REG_ACCESS(RwReg, 0x400A8068U) /**< \brief (ADC12B) Extended Mode Register */ -#define REG_ADC12B_RPR REG_ACCESS(RwReg, 0x400A8100U) /**< \brief (ADC12B) Receive Pointer Register */ -#define REG_ADC12B_RCR REG_ACCESS(RwReg, 0x400A8104U) /**< \brief (ADC12B) Receive Counter Register */ -#define REG_ADC12B_TPR REG_ACCESS(RwReg, 0x400A8108U) /**< \brief (ADC12B) Transmit Pointer Register */ -#define REG_ADC12B_TCR REG_ACCESS(RwReg, 0x400A810CU) /**< \brief (ADC12B) Transmit Counter Register */ -#define REG_ADC12B_RNPR REG_ACCESS(RwReg, 0x400A8110U) /**< \brief (ADC12B) Receive Next Pointer Register */ -#define REG_ADC12B_RNCR REG_ACCESS(RwReg, 0x400A8114U) /**< \brief (ADC12B) Receive Next Counter Register */ -#define REG_ADC12B_TNPR REG_ACCESS(RwReg, 0x400A8118U) /**< \brief (ADC12B) Transmit Next Pointer Register */ -#define REG_ADC12B_TNCR REG_ACCESS(RwReg, 0x400A811CU) /**< \brief (ADC12B) Transmit Next Counter Register */ -#define REG_ADC12B_PTCR REG_ACCESS(WoReg, 0x400A8120U) /**< \brief (ADC12B) Transfer Control Register */ -#define REG_ADC12B_PTSR REG_ACCESS(RoReg, 0x400A8124U) /**< \brief (ADC12B) Transfer Status Register */ -/* ========== Register definition for ADC peripheral ========== */ -#define REG_ADC_CR REG_ACCESS(WoReg, 0x400AC000U) /**< \brief (ADC) Control Register */ -#define REG_ADC_MR REG_ACCESS(RwReg, 0x400AC004U) /**< \brief (ADC) Mode Register */ -#define REG_ADC_CHER REG_ACCESS(WoReg, 0x400AC010U) /**< \brief (ADC) Channel Enable Register */ -#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x400AC014U) /**< \brief (ADC) Channel Disable Register */ -#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x400AC018U) /**< \brief (ADC) Channel Status Register */ -#define REG_ADC_SR REG_ACCESS(RoReg, 0x400AC01CU) /**< \brief (ADC) Status Register */ -#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x400AC020U) /**< \brief (ADC) Last Converted Data Register */ -#define REG_ADC_IER REG_ACCESS(WoReg, 0x400AC024U) /**< \brief (ADC) Interrupt Enable Register */ -#define REG_ADC_IDR REG_ACCESS(WoReg, 0x400AC028U) /**< \brief (ADC) Interrupt Disable Register */ -#define REG_ADC_IMR REG_ACCESS(RoReg, 0x400AC02CU) /**< \brief (ADC) Interrupt Mask Register */ -#define REG_ADC_CDR REG_ACCESS(RoReg, 0x400AC030U) /**< \brief (ADC) Channel Data Register */ -#define REG_ADC_RPR REG_ACCESS(RwReg, 0x400AC100U) /**< \brief (ADC) Receive Pointer Register */ -#define REG_ADC_RCR REG_ACCESS(RwReg, 0x400AC104U) /**< \brief (ADC) Receive Counter Register */ -#define REG_ADC_TPR REG_ACCESS(RwReg, 0x400AC108U) /**< \brief (ADC) Transmit Pointer Register */ -#define REG_ADC_TCR REG_ACCESS(RwReg, 0x400AC10CU) /**< \brief (ADC) Transmit Counter Register */ -#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x400AC110U) /**< \brief (ADC) Receive Next Pointer Register */ -#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x400AC114U) /**< \brief (ADC) Receive Next Counter Register */ -#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x400AC118U) /**< \brief (ADC) Transmit Next Pointer Register */ -#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x400AC11CU) /**< \brief (ADC) Transmit Next Counter Register */ -#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x400AC120U) /**< \brief (ADC) Transfer Control Register */ -#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x400AC124U) /**< \brief (ADC) Transfer Status Register */ -/* ========== Register definition for DMAC peripheral ========== */ -#define REG_DMAC_GCFG REG_ACCESS(RwReg, 0x400B0000U) /**< \brief (DMAC) DMAC Global Configuration Register */ -#define REG_DMAC_EN REG_ACCESS(RwReg, 0x400B0004U) /**< \brief (DMAC) DMAC Enable Register */ -#define REG_DMAC_SREQ REG_ACCESS(RwReg, 0x400B0008U) /**< \brief (DMAC) DMAC Software Single Request Register */ -#define REG_DMAC_CREQ REG_ACCESS(RwReg, 0x400B000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */ -#define REG_DMAC_LAST REG_ACCESS(RwReg, 0x400B0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */ -#define REG_DMAC_EBCIER REG_ACCESS(WoReg, 0x400B0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. */ -#define REG_DMAC_EBCIDR REG_ACCESS(WoReg, 0x400B001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. */ -#define REG_DMAC_EBCIMR REG_ACCESS(RoReg, 0x400B0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. */ -#define REG_DMAC_EBCISR REG_ACCESS(RoReg, 0x400B0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. */ -#define REG_DMAC_CHER REG_ACCESS(WoReg, 0x400B0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */ -#define REG_DMAC_CHDR REG_ACCESS(WoReg, 0x400B002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */ -#define REG_DMAC_CHSR REG_ACCESS(RoReg, 0x400B0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */ -#define REG_DMAC_SADDR0 REG_ACCESS(RwReg, 0x400B003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */ -#define REG_DMAC_DADDR0 REG_ACCESS(RwReg, 0x400B0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */ -#define REG_DMAC_DSCR0 REG_ACCESS(RwReg, 0x400B0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */ -#define REG_DMAC_CTRLA0 REG_ACCESS(RwReg, 0x400B0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */ -#define REG_DMAC_CTRLB0 REG_ACCESS(RwReg, 0x400B004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */ -#define REG_DMAC_CFG0 REG_ACCESS(RwReg, 0x400B0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */ -#define REG_DMAC_SADDR1 REG_ACCESS(RwReg, 0x400B0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */ -#define REG_DMAC_DADDR1 REG_ACCESS(RwReg, 0x400B0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */ -#define REG_DMAC_DSCR1 REG_ACCESS(RwReg, 0x400B006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */ -#define REG_DMAC_CTRLA1 REG_ACCESS(RwReg, 0x400B0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */ -#define REG_DMAC_CTRLB1 REG_ACCESS(RwReg, 0x400B0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */ -#define REG_DMAC_CFG1 REG_ACCESS(RwReg, 0x400B0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */ -#define REG_DMAC_SADDR2 REG_ACCESS(RwReg, 0x400B008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */ -#define REG_DMAC_DADDR2 REG_ACCESS(RwReg, 0x400B0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */ -#define REG_DMAC_DSCR2 REG_ACCESS(RwReg, 0x400B0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */ -#define REG_DMAC_CTRLA2 REG_ACCESS(RwReg, 0x400B0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */ -#define REG_DMAC_CTRLB2 REG_ACCESS(RwReg, 0x400B009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */ -#define REG_DMAC_CFG2 REG_ACCESS(RwReg, 0x400B00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */ -#define REG_DMAC_SADDR3 REG_ACCESS(RwReg, 0x400B00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */ -#define REG_DMAC_DADDR3 REG_ACCESS(RwReg, 0x400B00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */ -#define REG_DMAC_DSCR3 REG_ACCESS(RwReg, 0x400B00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */ -#define REG_DMAC_CTRLA3 REG_ACCESS(RwReg, 0x400B00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */ -#define REG_DMAC_CTRLB3 REG_ACCESS(RwReg, 0x400B00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */ -#define REG_DMAC_CFG3 REG_ACCESS(RwReg, 0x400B00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */ -/* ========== Register definition for SMC peripheral ========== */ -#define REG_SMC_CFG REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */ -#define REG_SMC_CTRL REG_ACCESS(WoReg, 0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */ -#define REG_SMC_SR REG_ACCESS(RoReg, 0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */ -#define REG_SMC_IER REG_ACCESS(WoReg, 0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */ -#define REG_SMC_IDR REG_ACCESS(WoReg, 0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */ -#define REG_SMC_IMR REG_ACCESS(RoReg, 0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */ -#define REG_SMC_ADDR REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */ -#define REG_SMC_BANK REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */ -#define REG_SMC_ECC_CTRL REG_ACCESS(WoReg, 0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */ -#define REG_SMC_ECC_MD REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */ -#define REG_SMC_ECC_SR1 REG_ACCESS(RoReg, 0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */ -#define REG_SMC_ECC_PR0 REG_ACCESS(RoReg, 0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */ -#define REG_SMC_ECC_PR1 REG_ACCESS(RoReg, 0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */ -#define REG_SMC_ECC_SR2 REG_ACCESS(RoReg, 0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */ -#define REG_SMC_ECC_PR2 REG_ACCESS(RoReg, 0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */ -#define REG_SMC_ECC_PR3 REG_ACCESS(RoReg, 0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */ -#define REG_SMC_ECC_PR4 REG_ACCESS(RoReg, 0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */ -#define REG_SMC_ECC_PR5 REG_ACCESS(RoReg, 0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */ -#define REG_SMC_ECC_PR6 REG_ACCESS(RoReg, 0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */ -#define REG_SMC_ECC_PR7 REG_ACCESS(RoReg, 0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */ -#define REG_SMC_ECC_PR8 REG_ACCESS(RoReg, 0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */ -#define REG_SMC_ECC_PR9 REG_ACCESS(RoReg, 0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */ -#define REG_SMC_ECC_PR10 REG_ACCESS(RoReg, 0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */ -#define REG_SMC_ECC_PR11 REG_ACCESS(RoReg, 0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */ -#define REG_SMC_ECC_PR12 REG_ACCESS(RoReg, 0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */ -#define REG_SMC_ECC_PR13 REG_ACCESS(RoReg, 0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */ -#define REG_SMC_ECC_PR14 REG_ACCESS(RoReg, 0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */ -#define REG_SMC_ECC_PR15 REG_ACCESS(RoReg, 0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */ -#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0070U) /**< \brief (SMC) SMC SETUP Register (CS_number = 0) */ -#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0074U) /**< \brief (SMC) SMC PULSE Register (CS_number = 0) */ -#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0078U) /**< \brief (SMC) SMC CYCLE Register (CS_number = 0) */ -#define REG_SMC_TIMINGS0 REG_ACCESS(RwReg, 0x400E007CU) /**< \brief (SMC) SMC TIMINGS Register (CS_number = 0) */ -#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC MODE Register (CS_number = 0) */ -#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0084U) /**< \brief (SMC) SMC SETUP Register (CS_number = 1) */ -#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0088U) /**< \brief (SMC) SMC PULSE Register (CS_number = 1) */ -#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E008CU) /**< \brief (SMC) SMC CYCLE Register (CS_number = 1) */ -#define REG_SMC_TIMINGS1 REG_ACCESS(RwReg, 0x400E0090U) /**< \brief (SMC) SMC TIMINGS Register (CS_number = 1) */ -#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E0094U) /**< \brief (SMC) SMC MODE Register (CS_number = 1) */ -#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0098U) /**< \brief (SMC) SMC SETUP Register (CS_number = 2) */ -#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E009CU) /**< \brief (SMC) SMC PULSE Register (CS_number = 2) */ -#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E00A0U) /**< \brief (SMC) SMC CYCLE Register (CS_number = 2) */ -#define REG_SMC_TIMINGS2 REG_ACCESS(RwReg, 0x400E00A4U) /**< \brief (SMC) SMC TIMINGS Register (CS_number = 2) */ -#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E00A8U) /**< \brief (SMC) SMC MODE Register (CS_number = 2) */ -#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E00ACU) /**< \brief (SMC) SMC SETUP Register (CS_number = 3) */ -#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E00B0U) /**< \brief (SMC) SMC PULSE Register (CS_number = 3) */ -#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E00B4U) /**< \brief (SMC) SMC CYCLE Register (CS_number = 3) */ -#define REG_SMC_TIMINGS3 REG_ACCESS(RwReg, 0x400E00B8U) /**< \brief (SMC) SMC TIMINGS Register (CS_number = 3) */ -#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E00BCU) /**< \brief (SMC) SMC MODE Register (CS_number = 3) */ -#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0110U) /**< \brief (SMC) SMC OCMS MODE Register */ -#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0114U) /**< \brief (SMC) SMC KEY1 Register */ -#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0118U) /**< \brief (SMC) SMC KEY2 Register */ -#define REG_SMC_WPCR REG_ACCESS(WoReg, 0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */ -#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */ -/* ========== Register definition for MATRIX peripheral ========== */ -#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ -#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ -#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ -#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ -#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ -#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ -#define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ -#define REG_MATRIX_PRAS5 REG_ACCESS(RwReg, 0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ -#define REG_MATRIX_PRAS6 REG_ACCESS(RwReg, 0x400E02B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ -#define REG_MATRIX_PRAS7 REG_ACCESS(RwReg, 0x400E02B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ -#define REG_MATRIX_PRAS8 REG_ACCESS(RwReg, 0x400E02C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ -#define REG_MATRIX_PRAS9 REG_ACCESS(RwReg, 0x400E02C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */ -#define REG_MATRIX_MRCR REG_ACCESS(RwReg, 0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */ -/* ========== Register definition for PMC peripheral ========== */ -#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ -#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ -#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */ -#define REG_PMC_PCER REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register */ -#define REG_PMC_PCDR REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register */ -//#define REG_PMC_PCSR REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register */ -#define REG_PMC_UCKR REG_ACCESS(RwReg, 0x400E041CU) /**< \brief (PMC) UTMI Clock Register */ -#define REG_PMC_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ -#define REG_PMC_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ -#define REG_PMC_PLLAR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */ -#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */ -#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ -#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ -#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ -#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */ -#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ -#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ -#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ -#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ -/* ========== Register definition for UART peripheral ========== */ -#define REG_UART_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART) Control Register */ -#define REG_UART_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART) Mode Register */ -#define REG_UART_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART) Interrupt Enable Register */ -#define REG_UART_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART) Interrupt Disable Register */ -#define REG_UART_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART) Interrupt Mask Register */ -#define REG_UART_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART) Status Register */ -#define REG_UART_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART) Receive Holding Register */ -#define REG_UART_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART) Transmit Holding Register */ -#define REG_UART_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART) Baud Rate Generator Register */ -#define REG_UART_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART) Receive Pointer Register */ -#define REG_UART_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART) Receive Counter Register */ -#define REG_UART_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART) Transmit Pointer Register */ -#define REG_UART_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART) Transmit Counter Register */ -#define REG_UART_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART) Receive Next Pointer Register */ -#define REG_UART_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART) Receive Next Counter Register */ -#define REG_UART_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART) Transmit Next Pointer Register */ -#define REG_UART_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART) Transmit Next Counter Register */ -#define REG_UART_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART) Transfer Control Register */ -#define REG_UART_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART) Transfer Status Register */ -/* ========== Register definition for CHIPID peripheral ========== */ -#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ -#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ -/* ========== Register definition for EFC0 peripheral ========== */ -#define REG_EFC0_FMR REG_ACCESS(RwReg, 0x400E0800U) /**< \brief (EFC0) EEFC Flash Mode Register */ -#define REG_EFC0_FCR REG_ACCESS(WoReg, 0x400E0804U) /**< \brief (EFC0) EEFC Flash Command Register */ -#define REG_EFC0_FSR REG_ACCESS(RoReg, 0x400E0808U) /**< \brief (EFC0) EEFC Flash Status Register */ -#define REG_EFC0_FRR REG_ACCESS(RoReg, 0x400E080CU) /**< \brief (EFC0) EEFC Flash Result Register */ -/* ========== Register definition for EFC1 peripheral ========== */ -#define REG_EFC1_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC1) EEFC Flash Mode Register */ -#define REG_EFC1_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC1) EEFC Flash Command Register */ -#define REG_EFC1_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC1) EEFC Flash Status Register */ -#define REG_EFC1_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC1) EEFC Flash Result Register */ -/* ========== Register definition for PIOA peripheral ========== */ -#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0C00U) /**< \brief (PIOA) PIO Enable Register */ -#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0C04U) /**< \brief (PIOA) PIO Disable Register */ -#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0C08U) /**< \brief (PIOA) PIO Status Register */ -#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0C10U) /**< \brief (PIOA) Output Enable Register */ -#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0C14U) /**< \brief (PIOA) Output Disable Register */ -#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0C18U) /**< \brief (PIOA) Output Status Register */ -#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0C20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ -#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0C24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ -#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0C28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ -#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0C30U) /**< \brief (PIOA) Set Output Data Register */ -#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0C34U) /**< \brief (PIOA) Clear Output Data Register */ -#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0C38U) /**< \brief (PIOA) Output Data Status Register */ -#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0C3CU) /**< \brief (PIOA) Pin Data Status Register */ -#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0C40U) /**< \brief (PIOA) Interrupt Enable Register */ -#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0C44U) /**< \brief (PIOA) Interrupt Disable Register */ -#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0C48U) /**< \brief (PIOA) Interrupt Mask Register */ -#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0C4CU) /**< \brief (PIOA) Interrupt Status Register */ -#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0C50U) /**< \brief (PIOA) Multi-driver Enable Register */ -#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0C54U) /**< \brief (PIOA) Multi-driver Disable Register */ -#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0C58U) /**< \brief (PIOA) Multi-driver Status Register */ -#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0C60U) /**< \brief (PIOA) Pull-up Disable Register */ -#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0C64U) /**< \brief (PIOA) Pull-up Enable Register */ -#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0C68U) /**< \brief (PIOA) Pad Pull-up Status Register */ -#define REG_PIOA_ABSR REG_ACCESS(RwReg, 0x400E0C70U) /**< \brief (PIOA) Peripheral AB Select Register */ -#define REG_PIOA_SCIFSR REG_ACCESS(WoReg, 0x400E0C80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */ -#define REG_PIOA_DIFSR REG_ACCESS(WoReg, 0x400E0C84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */ -#define REG_PIOA_IFDGSR REG_ACCESS(RoReg, 0x400E0C88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0C8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ -#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0CA0U) /**< \brief (PIOA) Output Write Enable */ -#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0CA4U) /**< \brief (PIOA) Output Write Disable */ -#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0CA8U) /**< \brief (PIOA) Output Write Status Register */ -#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0CB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ -#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0CB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ -#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0CB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ -#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0CC0U) /**< \brief (PIOA) Edge Select Register */ -#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0CC4U) /**< \brief (PIOA) Level Select Register */ -#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0CC8U) /**< \brief (PIOA) Edge/Level Status Register */ -#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0CD0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ -#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0CD4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ -#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0CD8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ -#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0CE0U) /**< \brief (PIOA) Lock Status */ -#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0CE4U) /**< \brief (PIOA) Write Protect Mode Register */ -#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0CE8U) /**< \brief (PIOA) Write Protect Status Register */ -/* ========== Register definition for PIOB peripheral ========== */ -#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOB) PIO Enable Register */ -#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOB) PIO Disable Register */ -#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOB) PIO Status Register */ -#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOB) Output Enable Register */ -#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOB) Output Disable Register */ -#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOB) Output Status Register */ -#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ -#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ -#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOB) Glitch Input Filter Status Register */ -#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOB) Set Output Data Register */ -#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOB) Clear Output Data Register */ -#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOB) Output Data Status Register */ -#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOB) Pin Data Status Register */ -#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOB) Interrupt Enable Register */ -#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOB) Interrupt Disable Register */ -#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOB) Interrupt Mask Register */ -#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOB) Interrupt Status Register */ -#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOB) Multi-driver Enable Register */ -#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOB) Multi-driver Disable Register */ -#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOB) Multi-driver Status Register */ -#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOB) Pull-up Disable Register */ -#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOB) Pull-up Enable Register */ -#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOB) Pad Pull-up Status Register */ -#define REG_PIOB_ABSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOB) Peripheral AB Select Register */ -#define REG_PIOB_SCIFSR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */ -#define REG_PIOB_DIFSR REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOB) Debouncing Input Filter Select Register */ -#define REG_PIOB_IFDGSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ -#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOB) Output Write Enable */ -#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOB) Output Write Disable */ -#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOB) Output Write Status Register */ -#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ -#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ -#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ -#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOB) Edge Select Register */ -#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOB) Level Select Register */ -#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOB) Edge/Level Status Register */ -#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ -#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ -#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ -#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOB) Lock Status */ -#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOB) Write Protect Mode Register */ -#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOB) Write Protect Status Register */ -/* ========== Register definition for PIOC peripheral ========== */ -#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOC) PIO Enable Register */ -#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOC) PIO Disable Register */ -#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOC) PIO Status Register */ -#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOC) Output Enable Register */ -#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOC) Output Disable Register */ -#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOC) Output Status Register */ -#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ -#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ -#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOC) Glitch Input Filter Status Register */ -#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOC) Set Output Data Register */ -#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOC) Clear Output Data Register */ -#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOC) Output Data Status Register */ -#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOC) Pin Data Status Register */ -#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOC) Interrupt Enable Register */ -#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOC) Interrupt Disable Register */ -#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOC) Interrupt Mask Register */ -#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOC) Interrupt Status Register */ -#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOC) Multi-driver Enable Register */ -#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOC) Multi-driver Disable Register */ -#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOC) Multi-driver Status Register */ -#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOC) Pull-up Disable Register */ -#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOC) Pull-up Enable Register */ -#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOC) Pad Pull-up Status Register */ -#define REG_PIOC_ABSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOC) Peripheral AB Select Register */ -#define REG_PIOC_SCIFSR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */ -#define REG_PIOC_DIFSR REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOC) Debouncing Input Filter Select Register */ -#define REG_PIOC_IFDGSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */ -#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ -#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOC) Output Write Enable */ -#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOC) Output Write Disable */ -#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOC) Output Write Status Register */ -#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ -#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ -#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ -#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOC) Edge Select Register */ -#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOC) Level Select Register */ -#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOC) Edge/Level Status Register */ -#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ -#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ -#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ -#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOC) Lock Status */ -#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOC) Write Protect Mode Register */ -#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOC) Write Protect Status Register */ -/* ========== Register definition for RSTC peripheral ========== */ -#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (RSTC) Control Register */ -#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1204U) /**< \brief (RSTC) Status Register */ -#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1208U) /**< \brief (RSTC) Mode Register */ -/* ========== Register definition for SUPC peripheral ========== */ -#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (SUPC) Supply Controller Control Register */ -#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1214U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ -#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1218U) /**< \brief (SUPC) Supply Controller Mode Register */ -#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E121CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ -#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1220U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ -#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1224U) /**< \brief (SUPC) Supply Controller Status Register */ -/* ========== Register definition for RTT peripheral ========== */ -#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1230U) /**< \brief (RTT) Mode Register */ -#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1234U) /**< \brief (RTT) Alarm Register */ -#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1238U) /**< \brief (RTT) Value Register */ -#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (RTT) Status Register */ -/* ========== Register definition for WDT peripheral ========== */ -#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (WDT) Control Register */ -#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1254U) /**< \brief (WDT) Mode Register */ -#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (WDT) Status Register */ -/* ========== Register definition for RTC peripheral ========== */ -#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1260U) /**< \brief (RTC) Control Register */ -#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1264U) /**< \brief (RTC) Mode Register */ -#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1268U) /**< \brief (RTC) Time Register */ -#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E126CU) /**< \brief (RTC) Calendar Register */ -#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (RTC) Time Alarm Register */ -#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1274U) /**< \brief (RTC) Calendar Alarm Register */ -#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1278U) /**< \brief (RTC) Status Register */ -#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E127CU) /**< \brief (RTC) Status Clear Command Register */ -#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (RTC) Interrupt Enable Register */ -#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (RTC) Interrupt Disable Register */ -#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (RTC) Interrupt Mask Register */ -#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E128CU) /**< \brief (RTC) Valid Entry Register */ -/* ========== Register definition for GPBR peripheral ========== */ -#define REG_GPBR_GPBR0 REG_ACCESS(RwReg, 0x400E1290U) /**< \brief (GPBR) General Purpose Backup Register 0 */ -#define REG_GPBR_GPBR1 REG_ACCESS(RwReg, 0x400E1294U) /**< \brief (GPBR) General Purpose Backup Register 1 */ -#define REG_GPBR_GPBR2 REG_ACCESS(RwReg, 0x400E1298U) /**< \brief (GPBR) General Purpose Backup Register 2 */ -#define REG_GPBR_GPBR3 REG_ACCESS(RwReg, 0x400E129CU) /**< \brief (GPBR) General Purpose Backup Register 3 */ -/*@}*/ - -/* ***************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR AT91SAM3U */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3U_id Peripheral Ids Definitions */ -/*@{*/ - -#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ -#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ -#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ -#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ -#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ -#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ -#define ID_EFC0 ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */ -#define ID_EFC1 ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */ -#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */ -#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ -#define ID_PIOA (10) /**< \brief Parallel I/O Controller A, (PIOA) */ -#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ -#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ -#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ -#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ -#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ -#define ID_USART3 (16) /**< \brief USART 3 (USART3) */ -#define ID_HSMCI (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */ -#define ID_TWI0 (18) /**< \brief Two-Wire Interface 0 (TWI0) */ -#define ID_TWI1 (19) /**< \brief Two-Wire Interface 1 (TWI1) */ -#define ID_SPI (20) /**< \brief Serial Peripheral Interface (SPI) */ -#define ID_SSC (21) /**< \brief Synchronous Serial Controller (SSC) */ -#define ID_TC0 (22) /**< \brief Timer Counter 0 (TC0) */ -#define ID_TC1 (23) /**< \brief Timer Counter 1 (TC1) */ -#define ID_TC2 (24) /**< \brief Timer Counter 2 (TC2) */ -#define ID_PWM (25) /**< \brief Pulse Width Modulation Controller (PWM) */ -#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */ -#define ID_ADC (27) /**< \brief 10-bit ADC Controller (ADC) */ -#define ID_DMAC (28) /**< \brief DMA Controller (DMAC) */ -#define ID_UDPHS (29) /**< \brief USB Device High Speed (UDPHS) */ -/*@}*/ - -/* ***************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR AT91SAM3U */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3U_base Peripheral Base Address Definitions */ -/*@{*/ - -#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */ -#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */ -#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */ -#define TC0 CAST(Tc , 0x40080000U) /**< \brief (TC0 ) Base Address */ -#define TWI0 CAST(Twi , 0x40084000U) /**< \brief (TWI0 ) Base Address */ -#define PDC_TWI0 CAST(Pdc , 0x40084100U) /**< \brief (PDC_TWI0 ) Base Address */ -#define TWI1 CAST(Twi , 0x40088000U) /**< \brief (TWI1 ) Base Address */ -#define PDC_TWI1 CAST(Pdc , 0x40088100U) /**< \brief (PDC_TWI1 ) Base Address */ -#define PWM CAST(Pwm , 0x4008C000U) /**< \brief (PWM ) Base Address */ -#define PDC_PWM CAST(Pdc , 0x4008C100U) /**< \brief (PDC_PWM ) Base Address */ -#define USART0 CAST(Usart , 0x40090000U) /**< \brief (USART0 ) Base Address */ -#define PDC_USART0 CAST(Pdc , 0x40090100U) /**< \brief (PDC_USART0) Base Address */ -#define USART1 CAST(Usart , 0x40094000U) /**< \brief (USART1 ) Base Address */ -#define PDC_USART1 CAST(Pdc , 0x40094100U) /**< \brief (PDC_USART1) Base Address */ -#define USART2 CAST(Usart , 0x40098000U) /**< \brief (USART2 ) Base Address */ -#define PDC_USART2 CAST(Pdc , 0x40098100U) /**< \brief (PDC_USART2) Base Address */ -#define USART3 CAST(Usart , 0x4009C000U) /**< \brief (USART3 ) Base Address */ -#define PDC_USART3 CAST(Pdc , 0x4009C100U) /**< \brief (PDC_USART3) Base Address */ -#define UDPHS CAST(Udphs , 0x400A4000U) /**< \brief (UDPHS ) Base Address */ -#define ADC12B CAST(Adc12b , 0x400A8000U) /**< \brief (ADC12B ) Base Address */ -#define PDC_ADC12B CAST(Pdc , 0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */ -#define ADC CAST(Adc , 0x400AC000U) /**< \brief (ADC ) Base Address */ -#define PDC_ADC CAST(Pdc , 0x400AC100U) /**< \brief (PDC_ADC ) Base Address */ -#define DMAC CAST(Dmac , 0x400B0000U) /**< \brief (DMAC ) Base Address */ -#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */ -#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */ -#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */ -#define UART CAST(Uart , 0x400E0600U) /**< \brief (UART ) Base Address */ -#define PDC_UART CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART ) Base Address */ -#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */ -#define EFC0 CAST(Efc , 0x400E0800U) /**< \brief (EFC0 ) Base Address */ -#define EFC1 CAST(Efc , 0x400E0A00U) /**< \brief (EFC1 ) Base Address */ -#define PIOA CAST(Pio , 0x400E0C00U) /**< \brief (PIOA ) Base Address */ -#define PIOB CAST(Pio , 0x400E0E00U) /**< \brief (PIOB ) Base Address */ -#define PIOC CAST(Pio , 0x400E1000U) /**< \brief (PIOC ) Base Address */ -#define RSTC CAST(Rstc , 0x400E1200U) /**< \brief (RSTC ) Base Address */ -#define SUPC CAST(Supc , 0x400E1210U) /**< \brief (SUPC ) Base Address */ -#define RTT CAST(Rtt , 0x400E1230U) /**< \brief (RTT ) Base Address */ -#define WDT CAST(Wdt , 0x400E1250U) /**< \brief (WDT ) Base Address */ -#define RTC CAST(Rtc , 0x400E1260U) /**< \brief (RTC ) Base Address */ -#define GPBR CAST(Gpbr , 0x400E1290U) /**< \brief (GPBR ) Base Address */ -/*@}*/ - -/* ***************************************************************************** */ -/* PIO DEFINITIONS FOR AT91SAM3U */ -/* ***************************************************************************** */ -/** \addtogroup AT91SAM3U_pio Peripheral Pio Definitions */ -/*@{*/ - -#define PIO_PA0 (1 << 0) /**< \brief Pin Controlled by PA0 */ -#define PIO_PA1 (1 << 1) /**< \brief Pin Controlled by PA1 */ -#define PIO_PA2 (1 << 2) /**< \brief Pin Controlled by PA2 */ -#define PIO_PA3 (1 << 3) /**< \brief Pin Controlled by PA3 */ -#define PIO_PA4 (1 << 4) /**< \brief Pin Controlled by PA4 */ -#define PIO_PA5 (1 << 5) /**< \brief Pin Controlled by PA5 */ -#define PIO_PA6 (1 << 6) /**< \brief Pin Controlled by PA6 */ -#define PIO_PA7 (1 << 7) /**< \brief Pin Controlled by PA7 */ -#define PIO_PA8 (1 << 8) /**< \brief Pin Controlled by PA8 */ -#define PIO_PA9 (1 << 9) /**< \brief Pin Controlled by PA9 */ -#define PIO_PA10 (1 << 10) /**< \brief Pin Controlled by PA10 */ -#define PIO_PA11 (1 << 11) /**< \brief Pin Controlled by PA11 */ -#define PIO_PA12 (1 << 12) /**< \brief Pin Controlled by PA12 */ -#define PIO_PA13 (1 << 13) /**< \brief Pin Controlled by PA13 */ -#define PIO_PA14 (1 << 14) /**< \brief Pin Controlled by PA14 */ -#define PIO_PA15 (1 << 15) /**< \brief Pin Controlled by PA15 */ -#define PIO_PA16 (1 << 16) /**< \brief Pin Controlled by PA16 */ -#define PIO_PA17 (1 << 17) /**< \brief Pin Controlled by PA17 */ -#define PIO_PA18 (1 << 18) /**< \brief Pin Controlled by PA18 */ -#define PIO_PA19 (1 << 19) /**< \brief Pin Controlled by PA19 */ -#define PIO_PA20 (1 << 20) /**< \brief Pin Controlled by PA20 */ -#define PIO_PA21 (1 << 21) /**< \brief Pin Controlled by PA21 */ -#define PIO_PA22 (1 << 22) /**< \brief Pin Controlled by PA22 */ -#define PIO_PA23 (1 << 23) /**< \brief Pin Controlled by PA23 */ -#define PIO_PA24 (1 << 24) /**< \brief Pin Controlled by PA24 */ -#define PIO_PA25 (1 << 25) /**< \brief Pin Controlled by PA25 */ -#define PIO_PA26 (1 << 26) /**< \brief Pin Controlled by PA26 */ -#define PIO_PA27 (1 << 27) /**< \brief Pin Controlled by PA27 */ -#define PIO_PA28 (1 << 28) /**< \brief Pin Controlled by PA28 */ -#define PIO_PA29 (1 << 29) /**< \brief Pin Controlled by PA29 */ -#define PIO_PA30 (1 << 30) /**< \brief Pin Controlled by PA30 */ -#define PIO_PA31 (1 << 31) /**< \brief Pin Controlled by PA31 */ -#define PIO_PB0 (1 << 0) /**< \brief Pin Controlled by PB0 */ -#define PIO_PB1 (1 << 1) /**< \brief Pin Controlled by PB1 */ -#define PIO_PB2 (1 << 2) /**< \brief Pin Controlled by PB2 */ -#define PIO_PB3 (1 << 3) /**< \brief Pin Controlled by PB3 */ -#define PIO_PB4 (1 << 4) /**< \brief Pin Controlled by PB4 */ -#define PIO_PB5 (1 << 5) /**< \brief Pin Controlled by PB5 */ -#define PIO_PB6 (1 << 6) /**< \brief Pin Controlled by PB6 */ -#define PIO_PB7 (1 << 7) /**< \brief Pin Controlled by PB7 */ -#define PIO_PB8 (1 << 8) /**< \brief Pin Controlled by PB8 */ -#define PIO_PB9 (1 << 9) /**< \brief Pin Controlled by PB9 */ -#define PIO_PB10 (1 << 10) /**< \brief Pin Controlled by PB10 */ -#define PIO_PB11 (1 << 11) /**< \brief Pin Controlled by PB11 */ -#define PIO_PB12 (1 << 12) /**< \brief Pin Controlled by PB12 */ -#define PIO_PB13 (1 << 13) /**< \brief Pin Controlled by PB13 */ -#define PIO_PB14 (1 << 14) /**< \brief Pin Controlled by PB14 */ -#define PIO_PB15 (1 << 15) /**< \brief Pin Controlled by PB15 */ -#define PIO_PB16 (1 << 16) /**< \brief Pin Controlled by PB16 */ -#define PIO_PB17 (1 << 17) /**< \brief Pin Controlled by PB17 */ -#define PIO_PB18 (1 << 18) /**< \brief Pin Controlled by PB18 */ -#define PIO_PB19 (1 << 19) /**< \brief Pin Controlled by PB19 */ -#define PIO_PB20 (1 << 20) /**< \brief Pin Controlled by PB20 */ -#define PIO_PB21 (1 << 21) /**< \brief Pin Controlled by PB21 */ -#define PIO_PB22 (1 << 22) /**< \brief Pin Controlled by PB22 */ -#define PIO_PB23 (1 << 23) /**< \brief Pin Controlled by PB23 */ -#define PIO_PB24 (1 << 24) /**< \brief Pin Controlled by PB24 */ -#define PIO_PB25 (1 << 25) /**< \brief Pin Controlled by PB25 */ -#define PIO_PB26 (1 << 26) /**< \brief Pin Controlled by PB26 */ -#define PIO_PB27 (1 << 27) /**< \brief Pin Controlled by PB27 */ -#define PIO_PB28 (1 << 28) /**< \brief Pin Controlled by PB28 */ -#define PIO_PB29 (1 << 29) /**< \brief Pin Controlled by PB29 */ -#define PIO_PB30 (1 << 30) /**< \brief Pin Controlled by PB30 */ -#define PIO_PB31 (1 << 31) /**< \brief Pin Controlled by PB31 */ -#define PIO_PC0 (1 << 0) /**< \brief Pin Controlled by PC0 */ -#define PIO_PC1 (1 << 1) /**< \brief Pin Controlled by PC1 */ -#define PIO_PC2 (1 << 2) /**< \brief Pin Controlled by PC2 */ -#define PIO_PC3 (1 << 3) /**< \brief Pin Controlled by PC3 */ -#define PIO_PC4 (1 << 4) /**< \brief Pin Controlled by PC4 */ -#define PIO_PC5 (1 << 5) /**< \brief Pin Controlled by PC5 */ -#define PIO_PC6 (1 << 6) /**< \brief Pin Controlled by PC6 */ -#define PIO_PC7 (1 << 7) /**< \brief Pin Controlled by PC7 */ -#define PIO_PC8 (1 << 8) /**< \brief Pin Controlled by PC8 */ -#define PIO_PC9 (1 << 9) /**< \brief Pin Controlled by PC9 */ -#define PIO_PC10 (1 << 10) /**< \brief Pin Controlled by PC10 */ -#define PIO_PC11 (1 << 11) /**< \brief Pin Controlled by PC11 */ -#define PIO_PC12 (1 << 12) /**< \brief Pin Controlled by PC12 */ -#define PIO_PC13 (1 << 13) /**< \brief Pin Controlled by PC13 */ -#define PIO_PC14 (1 << 14) /**< \brief Pin Controlled by PC14 */ -#define PIO_PC15 (1 << 15) /**< \brief Pin Controlled by PC15 */ -#define PIO_PC16 (1 << 16) /**< \brief Pin Controlled by PC16 */ -#define PIO_PC17 (1 << 17) /**< \brief Pin Controlled by PC17 */ -#define PIO_PC18 (1 << 18) /**< \brief Pin Controlled by PC18 */ -#define PIO_PC19 (1 << 19) /**< \brief Pin Controlled by PC19 */ -#define PIO_PC20 (1 << 20) /**< \brief Pin Controlled by PC20 */ -#define PIO_PC21 (1 << 21) /**< \brief Pin Controlled by PC21 */ -#define PIO_PC22 (1 << 22) /**< \brief Pin Controlled by PC22 */ -#define PIO_PC23 (1 << 23) /**< \brief Pin Controlled by PC23 */ -#define PIO_PC24 (1 << 24) /**< \brief Pin Controlled by PC24 */ -#define PIO_PC25 (1 << 25) /**< \brief Pin Controlled by PC25 */ -#define PIO_PC26 (1 << 26) /**< \brief Pin Controlled by PC26 */ -#define PIO_PC27 (1 << 27) /**< \brief Pin Controlled by PC27 */ -#define PIO_PC28 (1 << 28) /**< \brief Pin Controlled by PC28 */ -#define PIO_PC29 (1 << 29) /**< \brief Pin Controlled by PC29 */ -#define PIO_PC30 (1 << 30) /**< \brief Pin Controlled by PC30 */ -#define PIO_PC31 (1 << 31) /**< \brief Pin Controlled by PC31 */ -/* ========== Pio definition for HSMCI peripheral ========== */ -#define PIO_PA4A_MCCDA (1 << 4) /**< \brief Hsmci signal: MCCDA */ -#define PIO_PA3A_MCCK (1 << 3) /**< \brief Hsmci signal: MCCK */ -#define PIO_PA5A_MCDA0 (1 << 5) /**< \brief Hsmci signal: MCDA0 */ -#define PIO_PA6A_MCDA1 (1 << 6) /**< \brief Hsmci signal: MCDA1 */ -#define PIO_PA7A_MCDA2 (1 << 7) /**< \brief Hsmci signal: MCDA2 */ -#define PIO_PA8A_MCDA3 (1 << 8) /**< \brief Hsmci signal: MCDA3 */ -#define PIO_PC28B_MCDA4 (1 << 28) /**< \brief Hsmci signal: MCDA4 */ -#define PIO_PC29B_MCDA5 (1 << 29) /**< \brief Hsmci signal: MCDA5 */ -#define PIO_PC30B_MCDA6 (1 << 30) /**< \brief Hsmci signal: MCDA6 */ -#define PIO_PC31B_MCDA7 (1 << 31) /**< \brief Hsmci signal: MCDA7 */ -/* ========== Pio definition for SSC peripheral ========== */ -#define PIO_PA27A_RD (1 << 27) /**< \brief Ssc signal: RD */ -#define PIO_PA31A_RF (1 << 31) /**< \brief Ssc signal: RF */ -#define PIO_PA29A_RK (1 << 29) /**< \brief Ssc signal: RK */ -#define PIO_PA26A_TD (1 << 26) /**< \brief Ssc signal: TD */ -#define PIO_PA30A_TF (1 << 30) /**< \brief Ssc signal: TF */ -#define PIO_PA28A_TK (1 << 28) /**< \brief Ssc signal: TK */ -/* ========== Pio definition for SPI peripheral ========== */ -#define PIO_PA13A_MISO (1 << 13) /**< \brief Spi signal: MISO */ -#define PIO_PA14A_MOSI (1 << 14) /**< \brief Spi signal: MOSI */ -#define PIO_PA16A_NPCS0 (1 << 16) /**< \brief Spi signal: NPCS0 */ -#define PIO_PA0B_NPCS1 (1 << 0) /**< \brief Spi signal: NPCS1 */ -#define PIO_PC19B_NPCS1 (1 << 19) /**< \brief Spi signal: NPCS1 */ -#define PIO_PC3B_NPCS1 (1 << 3) /**< \brief Spi signal: NPCS1 */ -#define PIO_PA1B_NPCS2 (1 << 1) /**< \brief Spi signal: NPCS2 */ -#define PIO_PC14B_NPCS2 (1 << 14) /**< \brief Spi signal: NPCS2 */ -#define PIO_PC4B_NPCS2 (1 << 4) /**< \brief Spi signal: NPCS2 */ -#define PIO_PA19B_NPCS3 (1 << 19) /**< \brief Spi signal: NPCS3 */ -#define PIO_PC5B_NPCS3 (1 << 5) /**< \brief Spi signal: NPCS3 */ -#define PIO_PA15A_SPCK (1 << 15) /**< \brief Spi signal: SPCK */ -/* ========== Pio definition for TC0 peripheral ========== */ -#define PIO_PA2A_TCLK0 (1 << 2) /**< \brief Tc0 signal: TCLK0 */ -#define PIO_PB4A_TCLK1 (1 << 4) /**< \brief Tc0 signal: TCLK1 */ -#define PIO_PA26B_TCLK2 (1 << 26) /**< \brief Tc0 signal: TCLK2 */ -#define PIO_PA1A_TIOA0 (1 << 1) /**< \brief Tc0 signal: TIOA0 */ -#define PIO_PB5A_TIOA1 (1 << 5) /**< \brief Tc0 signal: TIOA1 */ -#define PIO_PA30B_TIOA2 (1 << 30) /**< \brief Tc0 signal: TIOA2 */ -#define PIO_PA0A_TIOB0 (1 << 0) /**< \brief Tc0 signal: TIOB0 */ -#define PIO_PB6A_TIOB1 (1 << 6) /**< \brief Tc0 signal: TIOB1 */ -#define PIO_PA31B_TIOB2 (1 << 31) /**< \brief Tc0 signal: TIOB2 */ -/* ========== Pio definition for TWI0 peripheral ========== */ -#define PIO_PA10A_TWCK0 (1 << 10) /**< \brief Twi0 signal: TWCK0 */ -#define PIO_PA9A_TWD0 (1 << 9) /**< \brief Twi0 signal: TWD0 */ -/* ========== Pio definition for TWI1 peripheral ========== */ -#define PIO_PA25A_TWCK1 (1 << 25) /**< \brief Twi1 signal: TWCK1 */ -#define PIO_PA24A_TWD1 (1 << 24) /**< \brief Twi1 signal: TWD1 */ -/* ========== Pio definition for PWM peripheral ========== */ -#define PIO_PA11B_PWMFI0 (1 << 11) /**< \brief Pwm signal: PWMFI0 */ -#define PIO_PA12B_PWMFI1 (1 << 12) /**< \brief Pwm signal: PWMFI1 */ -#define PIO_PA18B_PWMFI2 (1 << 18) /**< \brief Pwm signal: PWMFI2 */ -#define PIO_PA28B_PWMH0 (1 << 28) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA4B_PWMH0 (1 << 4) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB0A_PWMH0 (1 << 0) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PB13B_PWMH0 (1 << 13) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PC24B_PWMH0 (1 << 24) /**< \brief Pwm signal: PWMH0 */ -#define PIO_PA29B_PWMH1 (1 << 29) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA5B_PWMH1 (1 << 5) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB1A_PWMH1 (1 << 1) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PB14B_PWMH1 (1 << 14) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PC25B_PWMH1 (1 << 25) /**< \brief Pwm signal: PWMH1 */ -#define PIO_PA15B_PWMH2 (1 << 15) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA6B_PWMH2 (1 << 6) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB15B_PWMH2 (1 << 15) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PB2A_PWMH2 (1 << 2) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PC26B_PWMH2 (1 << 26) /**< \brief Pwm signal: PWMH2 */ -#define PIO_PA20B_PWMH3 (1 << 20) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB16B_PWMH3 (1 << 16) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PB3A_PWMH3 (1 << 3) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PC27B_PWMH3 (1 << 27) /**< \brief Pwm signal: PWMH3 */ -#define PIO_PA7B_PWML0 (1 << 7) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB17B_PWML0 (1 << 17) /**< \brief Pwm signal: PWML0 */ -#define PIO_PB25B_PWML0 (1 << 25) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC29A_PWML0 (1 << 29) /**< \brief Pwm signal: PWML0 */ -#define PIO_PC6B_PWML0 (1 << 6) /**< \brief Pwm signal: PWML0 */ -#define PIO_PA8B_PWML1 (1 << 8) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB18B_PWML1 (1 << 18) /**< \brief Pwm signal: PWML1 */ -#define PIO_PB26B_PWML1 (1 << 26) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC30A_PWML1 (1 << 30) /**< \brief Pwm signal: PWML1 */ -#define PIO_PC7B_PWML1 (1 << 7) /**< \brief Pwm signal: PWML1 */ -#define PIO_PA9B_PWML2 (1 << 9) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB19B_PWML2 (1 << 19) /**< \brief Pwm signal: PWML2 */ -#define PIO_PB27B_PWML2 (1 << 27) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC31A_PWML2 (1 << 31) /**< \brief Pwm signal: PWML2 */ -#define PIO_PC8B_PWML2 (1 << 8) /**< \brief Pwm signal: PWML2 */ -#define PIO_PA10B_PWML3 (1 << 10) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB20B_PWML3 (1 << 20) /**< \brief Pwm signal: PWML3 */ -#define PIO_PB28B_PWML3 (1 << 28) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC16B_PWML3 (1 << 16) /**< \brief Pwm signal: PWML3 */ -#define PIO_PC9B_PWML3 (1 << 9) /**< \brief Pwm signal: PWML3 */ -/* ========== Pio definition for USART0 peripheral ========== */ -#define PIO_PB8A_CTS0 (1 << 8) /**< \brief Usart0 signal: CTS0 */ -#define PIO_PB11B_DCD0 (1 << 11) /**< \brief Usart0 signal: DCD0 */ -#define PIO_PB10B_DSR0 (1 << 10) /**< \brief Usart0 signal: DSR0 */ -#define PIO_PB9B_DTR0 (1 << 9) /**< \brief Usart0 signal: DTR0 */ -#define PIO_PB12B_RI0 (1 << 12) /**< \brief Usart0 signal: RI0 */ -#define PIO_PB7A_RTS0 (1 << 7) /**< \brief Usart0 signal: RTS0 */ -#define PIO_PA19A_RXD0 (1 << 19) /**< \brief Usart0 signal: RXD0 */ -#define PIO_PA17A_SCK0 (1 << 17) /**< \brief Usart0 signal: SCK0 */ -#define PIO_PA18A_TXD0 (1 << 18) /**< \brief Usart0 signal: TXD0 */ -/* ========== Pio definition for USART1 peripheral ========== */ -#define PIO_PA23B_CTS1 (1 << 23) /**< \brief Usart1 signal: CTS1 */ -#define PIO_PA22B_RTS1 (1 << 22) /**< \brief Usart1 signal: RTS1 */ -#define PIO_PA21A_RXD1 (1 << 21) /**< \brief Usart1 signal: RXD1 */ -#define PIO_PA24B_SCK1 (1 << 24) /**< \brief Usart1 signal: SCK1 */ -#define PIO_PA20A_TXD1 (1 << 20) /**< \brief Usart1 signal: TXD1 */ -/* ========== Pio definition for USART2 peripheral ========== */ -#define PIO_PB22B_CTS2 (1 << 22) /**< \brief Usart2 signal: CTS2 */ -#define PIO_PB21B_RTS2 (1 << 21) /**< \brief Usart2 signal: RTS2 */ -#define PIO_PA23A_RXD2 (1 << 23) /**< \brief Usart2 signal: RXD2 */ -#define PIO_PA25B_SCK2 (1 << 25) /**< \brief Usart2 signal: SCK2 */ -#define PIO_PA22A_TXD2 (1 << 22) /**< \brief Usart2 signal: TXD2 */ -/* ========== Pio definition for USART3 peripheral ========== */ -#define PIO_PC10B_CTS3 (1 << 10) /**< \brief Usart3 signal: CTS3 */ -#define PIO_PC11B_RTS3 (1 << 11) /**< \brief Usart3 signal: RTS3 */ -#define PIO_PC13B_RXD3 (1 << 13) /**< \brief Usart3 signal: RXD3 */ -#define PIO_PC19A_SCK3 (1 << 19) /**< \brief Usart3 signal: SCK3 */ -#define PIO_PC12B_TXD3 (1 << 12) /**< \brief Usart3 signal: TXD3 */ -/* ========== Pio definition for ADC12B peripheral ========== */ -#define PIO_PA2B_AD12BTRG (1 << 2) /**< \brief Adc12b signal: AD12BTRG */ -/* ========== Pio definition for ADC peripheral ========== */ -#define PIO_PA17B_ADTRG (1 << 17) /**< \brief Adc signal: ADTRG */ -/* ========== Pio definition for PMC peripheral ========== */ -#define PIO_PA21B_PCK0 (1 << 21) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA27B_PCK0 (1 << 27) /**< \brief Pmc signal: PCK0 */ -#define PIO_PA3B_PCK1 (1 << 3) /**< \brief Pmc signal: PCK1 */ -#define PIO_PB24B_PCK1 (1 << 24) /**< \brief Pmc signal: PCK1 */ -#define PIO_PB23B_PCK2 (1 << 23) /**< \brief Pmc signal: PCK2 */ -/* ========== Pio definition for UART peripheral ========== */ -#define PIO_PA11A_URXD (1 << 11) /**< \brief Uart signal: URXD */ -#define PIO_PA12A_UTXD (1 << 12) /**< \brief Uart signal: UTXD */ -/*@}*/ - -/* ***************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR AT91SAM3U */ -/* ***************************************************************************** */ - -#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -#define AT91C_IFLASH (0x00080000) /**< Internal Flash base address */ -//#define AT91C_IFLASH (0x00100000) /**< Internal Flash base address */ -#define AT91C_IROM (0x00180000) /**< Internal ROM base address */ -//#define AT91C_IRAM (0x20000000) /**< Internal RAM base address */ -//#define AT91C_IRAM (0x20080000) /**< Internal RAM base address */ - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* AT91SAM3U_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/chip.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/chip.h deleted file mode 100644 index 03133de4e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/chip.h +++ /dev/null @@ -1,77 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - - -#ifndef CHIP_H -#define CHIP_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - - -//ARM core features - -// ARM core definition. -#define cortexm3 - -// family definition. -#define at91sam3u - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ - -//IP FEATURES - -// EFC GPNVM number -#define CHIP_EFC_NUM_GPNVMS 3 - -// Indicates chip has an Enhanced EFC. -#define CHIP_FLASH_EEFC - -// DMA channels number -#define CHIP_DMA_CHANNEL_NUM 4 - -// Indicate chip has a nandflash controller. -#define CHIP_NAND_CTRL - -//------------------------------------------------------------------------------ - - -//Misc - -//------------------------------------------------------------------------------ - -#endif //#ifndef CHIP_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/flash.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/flash.icf deleted file mode 100644 index a8911758c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/flash.icf +++ /dev/null @@ -1,47 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Vector table start*/ -define symbol __ICFEDIT_vector_start__ = 0x00080000; /*Add for CMSIS*/ -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM0_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM0_end__ = 0x20007FFF; -define symbol __ICFEDIT_region_RAM1_start__ = 0x20080000; -define symbol __ICFEDIT_region_RAM1_end__ = 0x20083FFF; -define symbol __ICFEDIT_region_ROM0_start__ = 0x00080000; -define symbol __ICFEDIT_region_ROM0_end__ = 0x0009FFFF; -define symbol __ICFEDIT_region_ROM1_start__ = 0x00100000; -define symbol __ICFEDIT_region_ROM1_end__ = 0x0011FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; -define symbol __ICFEDIT_size_heap__ = 0x200; -/*-Specials-*/ -/*define symbol __ICFEDIT_region_RAM_VECT_start__ = __ICFEDIT_region_RAM0_start__;*/ /*Referenced for CMSIS*/ -/*define symbol __ICFEDIT_size_vectors__ = 0x100;*/ /*Referenced for CMSIS*/ -/*-Exports-*/ -/*export symbol __ICFEDIT_region_RAM_VECT_start__;*/ -export symbol __ICFEDIT_vector_start__; /*Add for CMSIS*/ -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -/*define region RAM_VECT_region = mem:[from __ICFEDIT_region_RAM_VECT_start__ size __ICFEDIT_size_vectors__];*/ /*Referenced for CMSIS*/ -/*define region RAM0_region = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__];*/ /*Referenced for CMSIS*/ -define region RAM0_region = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__]; -define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__]; -/*define region RAM_region = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] | - mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/ /*Referenced for CMSIS*/ -define region ROM0_region = mem:[from __ICFEDIT_region_ROM0_start__ to __ICFEDIT_region_ROM0_end__]; -define region ROM1_region = mem:[from __ICFEDIT_region_ROM1_start__ to __ICFEDIT_region_ROM1_end__]; - -/*define block RamVect with alignment = 8, size = __ICFEDIT_size_vectors__ { };*/ -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -/*place at start of ROM0_region { readonly section .vectors };*/ /*Referenced for CMSIS*/ -place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors }; /*Add for CMSIS*/ -place in ROM0_region { readonly }; -place in RAM0_region { readwrite, block CSTACK, block HEAP }; -/*place in RAM_VECT_region { block RamVect };*/ /*Referenced for CMSIS*/ \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/flash.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/flash.lds deleted file mode 100644 index 0355f9223..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/flash.lds +++ /dev/null @@ -1,87 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Linker script for running in internal FLASH on the AT91SAM3U4 - *----------------------------------------------------------------------------*/ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(ResetException) - -/* Vector Definition */ -/* vector is put at very begin adress of SRAM0, the preserved size is 0x100 */ -_vect_start = 0x20000000; - -/* Memory Spaces Definitions */ -MEMORY -{ - sram0 (W!RX) : ORIGIN = 0x20000100, LENGTH = 0x00007F00 /* Sram0, 32K */ - sram1 (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */ - flash0 (W!RX) : ORIGIN = 0x00080000, LENGTH = 0x00020000 /* Flash0, 128K */ - flash1 (W!RX) : ORIGIN = 0x00100000, LENGTH = 0x00020000 /* Flash1, 128K */ -} - -SECTIONS -{ - .fixed : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors)) - *(.text*) - *(.rodata*) - *(.glue_7) - *(.glue_7t) - . = ALIGN(4); - _efixed = .; /* End of text section */ - } >flash0 - - .relocate : AT (_efixed) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc); - *(.data); - . = ALIGN(4); - _erelocate = .; - } >sram0 - - .bss (NOLOAD) : { - . = ALIGN(4); - _szero = .; - *(.bss) - . = ALIGN(4); - _ezero = .; - } >sram0 - - /* Stack in the end of SRAM0 */ - _estack = 0x20007FFC; -} -end = .; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/flash.sct b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/flash.sct deleted file mode 100644 index 3ec4fac7b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/flash.sct +++ /dev/null @@ -1,58 +0,0 @@ -; * ---------------------------------------------------------------------------- -; * ATMEL Microcontroller Software Support -; * ---------------------------------------------------------------------------- -; * Copyright (c) 2008, Atmel Corporation -; * -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without -; * modification, are permitted provided that the following conditions are met: -; * -; * - Redistributions of source code must retain the above copyright notice, -; * this list of conditions and the disclaimer below. -; * -; * Atmel's name may not be used to endorse or promote products derived from -; * this software without specific prior written permission. -; * -; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * ---------------------------------------------------------------------------- - -; *------------------------------------------------------------------------------ -; * Linker scatter for running in internal SRAM on the AT91SAM3U4 -; *----------------------------------------------------------------------------*/ - -; /* vector is put at very begin adress of SRAM0, the preserved size is 0x100 */ -Load_region 0x80000 0x20000 -{ - ; Flash 128K - Vector_region 0x80000 - { - board_cstartup_keil.o (vectors, +FIRST) - } - Fixed_region +0 - { - .ANY (+RO) - } - ; SRAM0 32K - Relocate_region 0x20000100 (0x8000-0x100) - { - .ANY (+RW +ZI) - } - ; Configure Stack and Heap - ARM_LIB_HEAP 0x20007000 EMPTY 0x400 - { - } - - ARM_LIB_STACK 0x20007FFC EMPTY -0x400 - { - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/psram.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/psram.icf deleted file mode 100644 index bdd5f4d10..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/psram.icf +++ /dev/null @@ -1,43 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Vector table start*/ -define symbol __ICFEDIT_vector_start__ = 0x60000000; /*Add for CMSIS*/ -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM0_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM0_end__ = 0x20007FFF; -define symbol __ICFEDIT_region_RAM1_start__ = 0x20080000; -define symbol __ICFEDIT_region_RAM1_end__ = 0x20083FFF; -define symbol __ICFEDIT_region_PSRAM_start__ = 0x60000000; -define symbol __ICFEDIT_region_RSRAM_end__ = 0x600FFFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/*-Specials-*/ -/*define symbol __ICFEDIT_region_RAM_VECT_start__ = __ICFEDIT_region_RAM0_start__;*/ /*Referenced for CMSIS*/ -/*define symbol __ICFEDIT_size_vectors__ = 0x100;*/ /*Referenced for CMSIS*/ -/*-Exports-*/ -export symbol __ICFEDIT_region_RAM_VECT_start__; /*Add for CMSIS*/ -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -/*define region RAM_VECT_region = mem:[from __ICFEDIT_region_RAM_VECT_start__ size __ICFEDIT_size_vectors__];*/ -/*define region RAM0_region = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__];*/ /*Referenced for CMSIS*/ -define region RAM0_region = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__]; -define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__]; -/*define region RAM_region = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] | - mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/ /*Referenced for CMSIS*/ -define region PSRAM_region = mem:[from __ICFEDIT_region_PSRAM_start__ to __ICFEDIT_region_RSRAM_end__]; - -/*define block RamVect with alignment = 8, size = __ICFEDIT_size_vectors__ { };*/ /*Referenced for CMSIS*/ -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -/*place at start of PSRAM_region { readonly section .vectors };*/ /*Referenced for CMSIS*/ -place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors }; /*Add for CMSIS*/ -place in PSRAM_region { readonly }; -place in PSRAM_region { readwrite, block CSTACK, block HEAP }; -/*place in RAM_VECT_region { block RamVect };*/ /*Referenced for CMSIS*/ \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/psram.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/psram.lds deleted file mode 100644 index b5b8c8d57..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/psram.lds +++ /dev/null @@ -1,86 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Linker script for running in internal PSRAM on the AT91SAM3U4 - *----------------------------------------------------------------------------*/ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(ResetException) - -/* Vector Definition */ -/* vector is put at very begin adress of SRAM0, the preserved size is 0x100 */ -_vect_start = 0x20000000; - -/* Memory Spaces Definitions */ -MEMORY -{ - sram0 (W!RX) : ORIGIN = 0x20000100, LENGTH = 0x00007F00 /* Sram0, 32K */ - sram1 (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */ - psram (W!RX) : ORIGIN = 0x60000000, LENGTH = 0x00100000 /* PSRAM, 1M */ -} - -SECTIONS -{ - .fixed : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors)) - *(.text*) - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.data) - . = ALIGN(4); - _efixed = .; /* End of text section */ - } >psram - - .relocate : AT (_efixed) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc); - . = ALIGN(4); - _erelocate = .; - } >sram0 - - .bss (NOLOAD) : { - . = ALIGN(4); - _szero = .; - *(.bss) - . = ALIGN(4); - _ezero = .; - } >psram - - /* Stack in the end of SRAM0 */ - _estack = 0x20007FFC; -} -end = .; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/psram.sct b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/psram.sct deleted file mode 100644 index 162f57b6b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/psram.sct +++ /dev/null @@ -1,59 +0,0 @@ -; * ---------------------------------------------------------------------------- -; * ATMEL Microcontroller Software Support -; * ---------------------------------------------------------------------------- -; * Copyright (c) 2008, Atmel Corporation -; * -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without -; * modification, are permitted provided that the following conditions are met: -; * -; * - Redistributions of source code must retain the above copyright notice, -; * this list of conditions and the disclaimer below. -; * -; * Atmel's name may not be used to endorse or promote products derived from -; * this software without specific prior written permission. -; * -; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * ---------------------------------------------------------------------------- - -; *------------------------------------------------------------------------------ -; * Linker scatter for running in internal SRAM on the AT91SAM3U4 -; *----------------------------------------------------------------------------*/ - -; /* vector is put at very begin adress of SRAM0, the preserved size is 0x100 */ -Load_region 0x60000000 0x100000 -{ - ; PSRAM 1M - Vector_region 0x60000000 - { - board_cstartup_keil.o (vectors, +FIRST) - } - - Fixed_region +0 - { - .ANY (+RO) - .ANY (+RW +ZI) - } - - ; SRAM0 32K - IVector_region 0x20000000 0x100 {} - - ; Configure Stack and Heap - ARM_LIB_HEAP 0x20007000 EMPTY 0x400 - { - } - - ARM_LIB_STACK 0x20007FFC EMPTY -0x400 - { - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/sram.icf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/sram.icf deleted file mode 100644 index 242942af3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/sram.icf +++ /dev/null @@ -1,33 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Vector table start*/ -define symbol __ICFEDIT_vector_start__ = 0x20000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_RAM0_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM0_end__ = 0x20007FFF; -define symbol __ICFEDIT_region_RAM1_start__ = 0x20080000; -define symbol __ICFEDIT_region_RAM1_end__ = 0x20083FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/*-Exports-*/ -export symbol __ICFEDIT_vector_start__; -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region RAM0_region = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__]; -define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__]; -/*define region RAM_region = mem:[from __ICFEDIT_region_RAM0_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM0_end__] | - mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];*/ - -/* define block RamVect with alignment = 8, size = __ICFEDIT_size_vectors__ { }; */ -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_vector_start__ { readonly section .vectors }; -place in RAM0_region { readonly }; -place in RAM1_region { readwrite, block CSTACK, block HEAP }; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/sram.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/sram.lds deleted file mode 100644 index 12029473e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/sram.lds +++ /dev/null @@ -1,84 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Linker script for running in internal SRAM on the AT91SAM3U4 - *----------------------------------------------------------------------------*/ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(ResetException) - -/* Vector Definition */ -_vect_start = 0x20000000; - -/* Memory Spaces Definitions */ -MEMORY -{ - sram0 (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* Sram0, 32K */ - sram1 (W!RX) : ORIGIN = 0x20080000, LENGTH = 0x00004000 /* Sram1, 16K */ -} - -SECTIONS -{ - .fixed : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors)) - *(.text*) - *(.ramfunc) - *(.rodata*) - *(.glue_7) - *(.glue_7t) - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > sram0 - - .relocate : AT (_efixed) - { - . = ALIGN(4); - _srelocate = .; - *(.data) - . = ALIGN(4); - _erelocate = .; - } >sram1 - - .bss (NOLOAD) : { - . = ALIGN(4); - _szero = .; - *(.bss) - . = ALIGN(4); - _ezero = .; - } >sram1 - - /* Stack in the end of SRAM1 */ - _estack = 0x20083FFC; -} -end = .; diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/sram.sct b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/sram.sct deleted file mode 100644 index f279cf79c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/sram.sct +++ /dev/null @@ -1,60 +0,0 @@ -; * ---------------------------------------------------------------------------- -; * ATMEL Microcontroller Software Support -; * ---------------------------------------------------------------------------- -; * Copyright (c) 2008, Atmel Corporation -; * -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without -; * modification, are permitted provided that the following conditions are met: -; * -; * - Redistributions of source code must retain the above copyright notice, -; * this list of conditions and the disclaimer below. -; * -; * Atmel's name may not be used to endorse or promote products derived from -; * this software without specific prior written permission. -; * -; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * ---------------------------------------------------------------------------- - -; *------------------------------------------------------------------------------ -; * Linker scatter for running in internal SRAM on the AT91SAM3U4 -; *----------------------------------------------------------------------------*/ - -Load_region 0x20000000 0x8000 -{ - ; RAM0 32K - Vector_region 0x20000000 0x100 - { - board_cstartup_keil.o (vectors, +FIRST) - } - - Fixed_region +0 - { - .ANY (+RO) - } - - ; RAM1 16K - Relocate_region 0x20080000 0x4000 - { - .ANY (+RW +ZI) - } - - ; Configure Stack and Heap - ARM_LIB_HEAP 0x20083000 EMPTY 0x400 - { - } - - ARM_LIB_STACK 0x20083FFC EMPTY -0x400 - { - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/sram_samba.lds b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/sram_samba.lds deleted file mode 100644 index 226b4595b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/at91sam3u4/sram_samba.lds +++ /dev/null @@ -1,92 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Linker script for running in internal SRAM on the AT91SAM3U4 - *----------------------------------------------------------------------------*/ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(entry) - -/* Memory Spaces Definitions */ -MEMORY -{ - romcodesram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x01000 - sram0 (W!RX) : ORIGIN = 0x20001000, LENGTH = 0x00007000 /* Sram0, 32K */ -} - -/* Entry point */ -/*ENTRY (ResetException)*/ - -SECTIONS -{ - /* startup code in the .isr_vector */ - .text : - { - . = ALIGN(4); - _stext = .; - KEEP(*(.isr_vector .isr_vector.*)) - *(.mailbox) - *(.text .text.*) - *(.rodata .rodata.*) - *(.glue_7) - *(.glue_7t) - *(.gcc_except_table) - *(.rodata .rodata*) - *(.gnu.linkonce.r.*) - . = ALIGN(4); - _etext = .; - } > sram0 - - /* data */ - .data : - { - . = ALIGN(4); - _sidata = .; - _sdata = .; - - *(.data) - *(.data.*) - . = ALIGN(4); - _edata = .; - } > sram0 - - .bss (NOLOAD) : { - _szero = .; - *(.bss) - . = ALIGN(4); - _ezero = .; - } >sram0 - - /* Stack in SRAM0 */ - _sstack = 0x20008000; -} -end = .; - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board.h deleted file mode 100644 index 766ae4746..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board.h +++ /dev/null @@ -1,665 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/** - * \page sam3s_ek_board_desc "SAM3S-EK - Board Description" - * - * \section - * A file is dedicated to descibe the AT91SAM3S-EK board. - * - * \section Contents - * - The code for booting the board is provided by board_cstartup.S and - * board_lowlevel.c. - * - For using board PIOs, board characteristics (clock, etc.) and external - * components, see board.h. - * - For manipulating memories (remapping, SDRAM, etc.), see board_memories.h. - * - * To get more software details and the full list of parameters related to the - * SAM3S-EK board configuration, please have a look at the source file: \n - * \ref board.h\n - * - * This file can be used as a template and modified to fit a custom board, with - * specific PIOs usage or memory connections. - **/ -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// \file board.h -/// -/// \par Purpose -/// -/// Definition of AT91SAM3S-EK characteristics, AT91SAM3S-dependant PIOs and -/// external components interfacing. -/// -/// \par Usage -/// -# For operating frequency information, see "SAM3S-EK - Operating frequencies". -/// -# For using portable PIO definitions, see "SAM3S-EK - PIO definitions". -/// -# Several USB definitions are included here (see "SAM3S-EK - USB device"). -//------------------------------------------------------------------------------ - -#ifndef BOARD_H -#define BOARD_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -/* These headers were introduced in C99 by working group ISO/IEC JTC1/SC22/WG14. */ -#include -#include - -#if defined(at91sam3s4) - #include "at91sam3s4/chip.h" - #include "at91sam3s4/AT91SAM3S4.h" -#else - #error Board does not support the specified chip. -#endif - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par -/// This page lists several definition related to the board description. -/// -/// Definitions -/// - BOARD_NAME - -/// Name of the board. -#define BOARD_NAME "AT91SAM3S-EK" -/// Board definition. -#define at91sam3sek -/// Family definition (already defined). -#define at91sam3s -/// Core definition -#define cortexm3 - -//#define BOARD_REV_A -#define BOARD_REV_B - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_opfreq "SAM3S-EK - Operating frequencies" -/// This page lists several definition related to the board operating frequency -/// (when using the initialization done by board_lowlevel.c). -/// -/// !Definitions -/// - BOARD_MAINOSC -/// - BOARD_MCK - -/// Frequency of the board main oscillator. -#define BOARD_MAINOSC 12000000 - -/// Master clock frequency (when using board_lowlevel.c). -//#define BOARD_MCK 48000000 -#define BOARD_MCK 64000000 - -//------------------------------------------------------------------------------ -// ADC -//------------------------------------------------------------------------------ - -/// Startup time max, return from Idle mode (in s) -#define ADC_STARTUP_TIME_MAX 15 -/// Track and hold Acquisition Time min (in ns) -#define ADC_TRACK_HOLD_TIME_MIN 1200 - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// USB attributes configuration descriptor (bus or self powered, remote wakeup) -//#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_RWAKEUP -#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_piodef "SAM3S-EK - PIO definitions" -/// This pages lists all the pio definitions contained in board.h. The constants -/// are named using the following convention: PIN_* for a constant which defines -/// a single Pin instance (but may include several PIOs sharing the same -/// controller), and PINS_* for a list of Pin instances. -/// -/// !ADC -/// - PIN_ADC0_AD0 -/// - PIN_ADC0_AD1 -/// - PIN_ADC0_AD2 -/// - PIN_ADC0_AD3 -/// - PIN_ADC0_AD4 -/// - PIN_ADC0_AD5 -/// - PIN_ADC0_AD6 -/// - PIN_ADC0_AD7 -/// - PINS_ADC0 -/// -/// !UART -/// - PINS_UART -/// -/// !EBI -/// - PIN_EBI_DATA_BUS -/// - PIN_EBI_NCS0 -/// - PIN_EBI_NRD -/// - PIN_EBI_NWE -/// - PIN_EBI_ADDR_BUS -/// - PIN_EBI_PSRAM_NBS -/// - PIN_EBI_A1 -/// - PIN_EBI_LCD_RS -/// -/// !LEDs -/// - PIN_LED_0 -/// - PIN_LED_1 -/// - PIN_LED_2 -/// - PINS_LEDS -/// -/// !MCI -/// - PINS_MCI -/// -/// !Push buttons -/// - PIN_PUSHBUTTON_1 -/// - PIN_PUSHBUTTON_2 -/// - PINS_PUSHBUTTONS -/// - PUSHBUTTON_BP1 -/// - PUSHBUTTON_BP2 -/// -/// !PWMC -/// - PIN_PWMC_PWMH0 -/// - PIN_PWMC_PWML0 -/// - PIN_PWMC_PWMH1 -/// - PIN_PWMC_PWML1 -/// - PIN_PWMC_PWMH2 -/// - PIN_PWMC_PWML2 -/// - PIN_PWMC_PWMH3 -/// - PIN_PWMC_PWML3 -/// - PIN_PWM_LED0 -/// - PIN_PWM_LED1 -/// - PIN_PWM_LED2 -/// - CHANNEL_PWM_LED0 -/// - CHANNEL_PWM_LED1 -/// - CHANNEL_PWM_LED2 -/// -/// !SPI -/// - PIN_SPI_MISO -/// - PIN_SPI_MOSI -/// - PIN_SPI_SPCK -/// - PINS_SPI -/// - PIN_SPI_NPCS0_PA11 -/// -/// ! SSC -/// - PIN_SSC_TD -/// - PIN_SSC_TK -/// - PIN_SSC_TF -/// - PINS_SSC_CODEC -/// -/// ! PCK0 -/// - PIN_PCK0 -/// -/// !TWI -/// - PIN_TWI_TWD0 -/// - PIN_TWI_TWCK0 -/// - PINS_TWI -/// -/// !USART0 -/// - PIN_USART0_RXD -/// - PIN_USART0_TXD -/// - PIN_USART0_CTS -/// - PIN_USART0_RTS -/// - PIN_USART0_SCK -/// -/// !USB -/// - PIN_USB_PULLUP -/// - -/// ADC_AD0 pin definition. -#define PIN_ADC0_AD0 {1 << 21, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD1 pin definition. -#define PIN_ADC0_AD1 {1 << 30, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD2 pin definition. -#define PIN_ADC0_AD2 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD3 pin definition. -#define PIN_ADC0_AD3 {1 << 4, PIOB, ID_PIOB, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD4 pin definition. -#define PIN_ADC0_AD4 {1 << 15, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD5 pin definition. -#define PIN_ADC0_AD5 {1 << 16, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD6 pin definition. -#define PIN_ADC0_AD6 {1 << 17, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -/// ADC_AD7 pin definition. -#define PIN_ADC0_AD7 {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} - -/// Pins ADC -#define PINS_ADC PIN_ADC0_AD0, PIN_ADC0_AD1, PIN_ADC0_AD2, PIN_ADC0_AD3, PIN_ADC0_AD4, PIN_ADC0_AD5, PIN_ADC0_AD6, PIN_ADC0_AD7 - -/** UART pins (UTXD0 and URXD0) definitions, PA9,10. */ -#define PINS_UART {0x00000600, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} - -/// EBI -#define PIN_EBI_DATA_BUS {0xFF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NRD {1 << 11, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NWE {1 << 8, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} - -#define PIN_EBI_NCS0 {1 << 20, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_PSRAM_ADDR_BUS {0x3f00fff, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_PSRAM_NBS {1 << 7, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_PULLUP}, \ - {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_A1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} - -#define PIN_EBI_NCS1 {1 << 15, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD CS pin */ -#define PIN_EBI_LCD_RS {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} /* LCD RS pin */ - -#ifdef BOARD_REV_A -/** LED #0 pin definition. */ -#define PIN_LED_0 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #1 pin definition. */ -#define PIN_LED_1 {1 << 21, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #2 pin definition. */ -#define PIN_LED_2 {1 << 22, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -#endif -#ifdef BOARD_REV_B -/** LED #0 pin definition. */ -#define PIN_LED_0 {1 << 19, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #1 pin definition. */ -#define PIN_LED_1 {1 << 20, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} -/** LED #2 pin definition. */ -#define PIN_LED_2 {1 << 20, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -#endif - -/** List of all LEDs definitions. */ -#define PINS_LEDS PIN_LED_0, PIN_LED_1, PIN_LED_2 - -/// MCI pins definition. -#define PINS_MCI {0x1f8, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_PULLUP}, \ - {1 << 3, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} - -/// MCI pin Card Detect -#define PIN_MCI_CD \ - {AT91C_PIO_PA25, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} - -/** Push button #0 definition. Attributes = pull-up + debounce + interrupt on rising edge. */ -#define PIN_PUSHBUTTON_1 {1 << 3, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE} -/** Push button #1 definition. Attributes = pull-up + debounce + interrupt on falling edge. */ -#define PIN_PUSHBUTTON_2 {1 << 12, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE} -/** List of all push button definitions. */ -#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2 - -/** Push button #1 index. */ -#define PUSHBUTTON_BP1 0 -/** Push button #2 index. */ -#define PUSHBUTTON_BP2 1 - -/// Simulated joystick LEFT index. -#define JOYSTICK_LEFT 0 -/// Simulated joystick RIGHT index. -#define JOYSTICK_RIGHT 1 - -/** PWMC PWM0 pin definition. */ -#define PIN_PWMC_PWMH0 {1 << 18, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML0 {1 << 19, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} -/** PWMC PWM1 pin definition. */ -#define PIN_PWMC_PWMH1 {1 << 19, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML1 {1 << 20, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} -/** PWMC PWM2 pin definition. */ -#define PIN_PWMC_PWMH2 {1 << 20, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML2 {1 << 16, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} -/** PWMC PWM3 pin definition. */ -#define PIN_PWMC_PWMH3 {1 << 21, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} -#define PIN_PWMC_PWML3 {1 << 15, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} -/** PWM pin definition for LED0 */ -#define PIN_PWM_LED0 PIN_PWMC_PWMH0, PIN_PWMC_PWML0 -/** PWM pin definition for LED1 */ -#define PIN_PWM_LED1 PIN_PWMC_PWMH2, PIN_PWMC_PWML2 -/** PWM pin definition for LED2 */ -#define PIN_PWM_LED2 PIN_PWMC_PWMH3, PIN_PWMC_PWML3 -/** PWM channel for LED0 */ -#define CHANNEL_PWM_LED0 0 -/** PWM channel for LED1 */ -#define CHANNEL_PWM_LED1 2 -/** PWM channel for LED2 */ -#define CHANNEL_PWM_LED2 3 - -/** SPI MISO pin definition. */ -#define PIN_SPI_MISO {1 << 12, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** SPI MOSI pin definition. */ -#define PIN_SPI_MOSI {1 << 13, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** SPI SPCK pin definition. */ -#define PIN_SPI_SPCK {1 << 14, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** SPI chip select pin definition. */ -#define PIN_SPI_NPCS0_PA11 {1 << 11, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -/** List of SPI pin definitions (MISO, MOSI & SPCK). */ -#define PINS_SPI PIN_SPI_MISO, PIN_SPI_MOSI, PIN_SPI_SPCK - -/// SSC pins definition. -#define PIN_SSC_TD {0x1 << 26, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_SSC_TK {0x1 << 28, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_SSC_TF {0x1 << 30, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PINS_SSC_CODEC PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF - -/// PCK0 -#define PIN_PCK0 {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} - -/// TWI pins definition. -#define TWI_V3XX -#define PIN_TWI_TWD0 {0x1 << 9, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_TWI_TWCK0 {0x1 << 10, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PINS_TWI0 PIN_TWI_TWD0, PIN_TWI_TWCK0 -#define PIN_TWI_TWD1 {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_TWI_TWCK1 {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PINS_TWI1 PIN_TWI_TWD1, PIN_TWI_TWCK1 - -/// USART0 -#define PIN_USART0_RXD {0x1 << 19, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_TXD {0x1 << 18, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_CTS {0x1 << 8, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_RTS {0x1 << 7, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART0_SCK {0x1 << 17, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} - -/// USART1 -#define PIN_USART1_RXD {0x1 << 21, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_TXD {0x1 << 22, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_CTS {0x1 << 25, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_RTS {0x1 << 24, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} -#define PIN_USART1_EN {0x1 << 23, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} - - - -/// USB VBus monitoring pin definition. -#ifdef BOARD_REV_A -#define PIN_USB_VBUS {1 << 23, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -#endif -#ifdef BOARD_REV_B -#define PIN_USB_VBUS {1 << 21, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} -#endif - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_extcomp "SAM3S-EK - External components" -/// This page lists the definitions related to external on-board components -/// located in the board.h file for the AT91SAM3S-EK. -/// -/// !AT45 Dataflash Card -/// - BOARD_AT45_A_SPI_BASE -/// - BOARD_AT45_A_SPI_ID -/// - BOARD_AT45_A_SPI_PINS -/// - BOARD_AT45_A_SPI -/// - BOARD_AT45_A_NPCS -/// - BOARD_AT45_A_NPCS_PIN -/// -/// !AT45 Dataflash (serial onboard DataFlash) -/// - BOARD_AT45_B_SPI_BASE -/// - BOARD_AT45_B_SPI_ID -/// - BOARD_AT45_B_SPI_PINS -/// - BOARD_AT45_B_SPI -/// - BOARD_AT45_B_NPCS -/// - BOARD_AT45_B_NPCS_PIN -/// -/// !AT26 Serial Flash -/// - BOARD_AT26_A_SPI_BASE -/// - BOARD_AT26_A_SPI_ID -/// - BOARD_AT26_A_SPI_PINS -/// - BOARD_AT26_A_SPI -/// - BOARD_AT26_A_NPCS -/// - BOARD_AT26_A_NPCS_PIN -/// -/// !SD Card -/// - MCI2_INTERFACE -/// - BOARD_SD_MCI_BASE -/// - BOARD_SD_MCI_ID -/// - BOARD_SD_PINS -/// - BOARD_SD_SLOT -/// -/// !PSRAM -/// - BOARD_PSRAM_PINS -/// -/// !LCD -/// - BOARD_LCD_ILI9325 -/// - BOARD_LCD_PINS -/// - BOARD_BACKLIGHT_PIN -/// - BOARD_LCD_BASE -/// - BOARD_LCD_RS -/// - BOARD_LCD_WIDTH -/// - BOARD_LCD_HEIGHT -/// -/// !TouchScreen -/// - BOARD_TSC_ADS7843 -/// - PIN_TCS_IRQ -/// - PIN_TCS_BUSY -/// - BOARD_TSC_SPI_BASE -/// - BOARD_TSC_SPI_ID -/// - BOARD_TSC_SPI_PINS -/// - BOARD_TSC_NPCS -/// - BOARD_TSC_NPCS_PIN -/// -/// Base address of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_A_SPI_BASE SPI0 -///// Identifier of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_A_SPI_ID ID_SPI0 -///// Pins of the SPI peripheral connected to the dataflash. -//#define BOARD_AT45_A_SPI_PINS PINS_SPI0 -///// Dataflahs SPI number. -//#define BOARD_AT45_A_SPI 0 -///// Chip select connected to the dataflash. -//#define BOARD_AT45_A_NPCS 3 -///// Chip select pin connected to the dataflash. -//#define BOARD_AT45_A_NPCS_PIN PIN_SPI0_NPCS3 - -/// Base address of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_B_SPI_BASE SPI1 -///// Identifier of SPI peripheral connected to the dataflash. -//#define BOARD_AT45_B_SPI_ID ID_SPI1 -///// Pins of the SPI peripheral connected to the dataflash. -//#define BOARD_AT45_B_SPI_PINS PINS_SPI1 -///// Dataflahs SPI number. -//#define BOARD_AT45_B_SPI 1 -///// Chip select connected to the dataflash. -//#define BOARD_AT45_B_NPCS 3 -///// Chip select pin connected to the dataflash. -//#define BOARD_AT45_B_NPCS_PIN PIN_SPI1_NPCS3 - -/// Base address of SPI peripheral connected to the serialflash. -//#define BOARD_AT26_A_SPI_BASE SPI0 -///// Identifier of SPI peripheral connected to the serialflash. -//#define BOARD_AT26_A_SPI_ID ID_SPI0 -///// Pins of the SPI peripheral connected to the serialflash. -//#define BOARD_AT26_A_SPI_PINS PINS_SPI0 -///// Serialflash SPI number. -//#define BOARD_AT26_A_SPI 0 -///// Chip select connected to the serialflash. -//#define BOARD_AT26_A_NPCS 3 -///// Chip select pin connected to the serialflash. -//#define BOARD_AT26_A_NPCS_PIN PIN_SPI0_NPCS3 - -/// ISO7816 -/// - PIN_SMARTCARD_CONNECT -/// - PIN_ISO7816_RSTMC -/// - PINS_ISO7816 - -/// Smartcard detection pin -//#define PIN_SMARTCARD_CONNECT {1 << 5, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} -/// PIN used for reset the smartcard -//#define PIN_ISO7816_RSTMC {1 << 7, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} -/// Pins used for connect the smartcard -//#define PINS_ISO7816 PIN_USART0_TXD, PIN_USART0_SCK, PIN_ISO7816_RSTMC - -/// Dma channel number -#define BOARD_MCI_DMA_CHANNEL 0 -/// MCI0 DMA hardware handshaking ID -#define DMA_HW_SRC_REQ_ID_MCI0 AT91C_HDMA_SRC_PER_0 -#define DMA_HW_DEST_REQ_ID_MCI0 AT91C_HDMA_DST_PER_0 -/// MCI1 DMA hardware handshaking ID -#define DMA_HW_SRC_REQ_ID_MCI1 AT91C_HDMA_SRC_PER_13 -#define DMA_HW_DEST_REQ_ID_MCI1 AT91C_HDMA_DST_PER_13 -/// SD DMA hardware handshaking ID -#define BOARD_SD_DMA_HW_SRC_REQ_ID DMA_HW_SRC_REQ_ID_MCI0 -#define BOARD_SD_DMA_HW_DEST_REQ_ID DMA_HW_DEST_REQ_ID_MCI0 - - -/// HS MCI interface -#define MCI2_INTERFACE -/// Base address of the MCI peripheral connected to the SD card. -#define BOARD_SD_MCI_BASE MCI0//MCI -///// Peripheral identifier of the MCI connected to the SD card. -#define BOARD_SD_MCI_ID ID_MCI0 //ID_MCI -///// MCI pins that shall be configured to access the SD card. -#define BOARD_SD_PINS PINS_MCI -///// MCI slot to which the SD card is connected to. -#define BOARD_SD_SLOT MCI_SD_SLOTA -///// MCI Card Detect pin. -#define BOARD_SD_PIN_CD PIN_MCI_CD - -//#define BOARD_PSRAM_PINS PIN_EBI_DATA_BUS, PIN_EBI_NCS0, PIN_EBI_NRD, PIN_EBI_NWE, \ - PIN_EBI_PSRAM_ADDR_BUS, PIN_EBI_PSRAM_NBS, PIN_EBI_A1 - -/** Indicates board has an ILI9325 external component to manage LCD. */ -#define BOARD_LCD_ILI9325 - -/** LCD pins definition. */ -#define BOARD_LCD_PINS PIN_EBI_DATA_BUS, PIN_EBI_NRD, PIN_EBI_NWE, \ - PIN_EBI_NCS1, PIN_EBI_LCD_RS -/** Backlight pin definition. */ -#define BOARD_BACKLIGHT_PIN {1 << 13, PIOC, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT} -/** Define ILI9325 base address. */ -#define BOARD_LCD_BASE 0x61000000 -/** Define ILI9325 register select signal. */ -#define BOARD_LCD_RS (1 << 1) -/** Display width in pixels. */ -#define BOARD_LCD_WIDTH 240 -/** Display height in pixels. */ -#define BOARD_LCD_HEIGHT 320 - -/** Indicates board has an ADS7843 external component to manage Touch Screen */ -#define BOARD_TSC_ADS7843 - -#ifdef BOARD_REV_A -/** Touchscreen controller IRQ pin definition. */ -#define PIN_TCS_IRQ {PIO_PA4, PIOA, ID_PIOA, PIO_INPUT, PIO_DEBOUNCE | PIO_IT_AIME | PIO_IT_EDGE} -#define PIN_TCS_IRQ_WUP_ID (1 << 3) -/** Touchscreen controller Busy pin definition. */ -#define PIN_TCS_BUSY {PIO_PA5, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} -#endif -#ifdef BOARD_REV_B -/** Touchscreen controller IRQ pin definition. */ -#define PIN_TCS_IRQ {PIO_PA16, PIOA, ID_PIOA, PIO_INPUT, PIO_DEBOUNCE | PIO_IT_AIME | PIO_IT_EDGE} -#define PIN_TCS_IRQ_WUP_ID (1 << 15) -/** Touchscreen controller Busy pin definition. */ -#define PIN_TCS_BUSY {PIO_PA17, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP} -#endif - -/** Base address of SPI peripheral connected to the touchscreen controller. */ -#define BOARD_TSC_SPI_BASE SPI -/** Identifier of SPI peripheral connected to the touchscreen controller. */ -#define BOARD_TSC_SPI_ID ID_SPI -/** Pins of the SPI peripheral connected to the touchscreen controller. */ -#define BOARD_TSC_SPI_PINS PINS_SPI -/** Chip select connected to the touchscreen controller. */ -#define BOARD_TSC_NPCS 0 -/** Chip select pin connected to the touchscreen controller. */ -#define BOARD_TSC_NPCS_PIN PIN_SPI_NPCS0_PA11 - -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_mem "SAM3S-EK - Memories" -/// This page lists definitions related to internal & external on-board memories. -/// -/// !Embedded Flash -/// - BOARD_FLASH_EFC - -/// Internal SRAM address -#define AT91C_ISRAM AT91C_IRAM -#define AT91C_ISRAM_SIZE 0x00008000 - -#define AT91C_IFLASH_SIZE (0x40000) -#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH 0 Page Size: 256 bytes -#define AT91C_IFLASH_NB_OF_PAGES (1024) // Internal FLASH 0 Number of Pages: 512 -#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH 0 Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (16) // Internal FLASH 0 Number of Lock Bits: 16 - -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// \section sam3s_ek_extcomp "SAM3S-EK - External components" -/// This page lists the definitions related to external on-board components -/// located in the board.h file for the SAM3S-EK. -/// -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \par sam3s_ek_chipdef "SAM3S-EK - Individual chip definition" -/// This page lists the definitions related to different chip's definition -/// located in the board.h file for the SAM3S-EK. - -/// DBGU -#define BOARD_DBGU_ID ID_DBGU - -/// Rtc -#define BOARD_RTC_ID ID_RTC - -/// Twi eeprom -#define BOARD_ID_TWI_EEPROM ID_TWI1 -#define BOARD_BASE_TWI_EEPROM TWI1 -#define BOARD_PINS_TWI_EEPROM PINS_TWI1 - -/// USART -#define BOARD_PIN_USART_RXD PIN_USART1_RXD -#define BOARD_PIN_USART_TXD PIN_USART1_TXD -#define BOARD_PIN_USART_CTS PIN_USART1_CTS -#define BOARD_PIN_USART_RTS PIN_USART1_RTS -#define BOARD_PIN_USART_EN PIN_USART1_EN -#define BOARD_USART_BASE USART1 -#define BOARD_ID_USART ID_USART1 - -//------------------------------------------------------------------------------ - - -#define PIN_EBI_NANDOE {1 << 9, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDWE {1 << 10, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDCLE {1 << 17, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDALE {1 << 16, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} -#define PIN_EBI_NANDIO {0x000000FF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} - -/// Nandflash chip enable pin definition. -#define BOARD_NF_CE_PIN {1 << 14, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} -/// Nandflash ready/busy pin definition. -#define BOARD_NF_RB_PIN {1 << 18, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP} - -/// Nandflash controller peripheral pins definition. -#define PINS_NANDFLASH PIN_EBI_NANDIO, BOARD_NF_CE_PIN, BOARD_NF_RB_PIN, PIN_EBI_NANDOE, \ - PIN_EBI_NANDWE, PIN_EBI_NANDCLE, PIN_EBI_NANDALE - -/// Address for transferring command bytes to the nandflash. -#define BOARD_NF_COMMAND_ADDR 0x60400000 -/// Address for transferring address bytes to the nandflash. -#define BOARD_NF_ADDRESS_ADDR 0x60200000 -/// Address for transferring data bytes to the nandflash. -#define BOARD_NF_DATA_ADDR 0x60000000 - -#endif //#ifndef BOARD_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_cstartup_gnu.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_cstartup_gnu.c deleted file mode 100644 index 632cdaca3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_cstartup_gnu.c +++ /dev/null @@ -1,172 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "board.h" -#include "exceptions.h" -#include "board_lowlevel.h" - -#include - -/*---------------------------------------------------------------------------- - * Exported variables - *----------------------------------------------------------------------------*/ - -/* Stack top */ -extern uint32_t _estack; - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -/* The mask of VTOR register */ -#define SCB_VTOR_MASK 0x3FFFFFF8 - -/*---------------------------------------------------------------------------- - * ProtoTypes - *----------------------------------------------------------------------------*/ - -extern int main(void); -void ResetException(void); - -/*---------------------------------------------------------------------------- - * Local variables - *----------------------------------------------------------------------------*/ - -/* Exception Table */ -__attribute__((section(".vectors"))) -IntFunc exception_table[] = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - (IntFunc)&_estack, - ResetException, - - NMI_Handler, - HardFault_Handler, - MemManage_Handler, - BusFault_Handler, - UsageFault_Handler, - 0, 0, 0, 0, /* Reserved */ - SVC_Handler, - DebugMon_Handler, - 0, /* Reserved */ - PendSV_Handler, - SysTick_Handler, - - /* Configurable interrupts */ - SUPC_IrqHandler, /* 0 Supply Controller */ - RSTC_IrqHandler, /* 1 Reset Controller */ - RTC_IrqHandler, /* 2 Real Time Clock */ - RTT_IrqHandler, /* 3 Real Time Timer */ - WDT_IrqHandler, /* 4 Watchdog Timer */ - PMC_IrqHandler, /* 5 PMC */ - EEFC_IrqHandler, /* 6 EEFC */ - IrqHandlerNotUsed, /* 7 Reserved */ - UART0_IrqHandler, /* 8 UART0 */ - UART1_IrqHandler, /* 9 UART1 */ - SMC_IrqHandler, /* 10 SMC */ - PIOA_IrqHandler, /* 11 Parallel IO Controller A */ - PIOB_IrqHandler, /* 12 Parallel IO Controller B */ - PIOC_IrqHandler, /* 13 Parallel IO Controller C */ - USART0_IrqHandler, /* 14 USART 0 */ - USART1_IrqHandler, /* 15 USART 1 */ - IrqHandlerNotUsed, /* 16 Reserved */ - IrqHandlerNotUsed, /* 17 Reserved */ - MCI_IrqHandler, /* 18 MCI */ - TWI0_IrqHandler, /* 19 TWI 0 */ - TWI1_IrqHandler, /* 20 TWI 1 */ - SPI_IrqHandler, /* 21 SPI */ - SSC_IrqHandler, /* 22 SSC */ - TC0_IrqHandler, /* 23 Timer Counter 0 */ - TC1_IrqHandler, /* 24 Timer Counter 1 */ - TC2_IrqHandler, /* 25 Timer Counter 2 */ - TC3_IrqHandler, /* 26 Timer Counter 3 */ - TC4_IrqHandler, /* 27 Timer Counter 4 */ - TC5_IrqHandler, /* 28 Timer Counter 5 */ - ADC_IrqHandler, /* 29 ADC controller */ - DAC_IrqHandler, /* 30 DAC controller */ - PWM_IrqHandler, /* 31 PWM */ - CRCCU_IrqHandler, /* 32 CRC Calculation Unit */ - ACC_IrqHandler, /* 33 Analog Comparator */ - USBD_IrqHandler, /* 34 USB Device Port */ - IrqHandlerNotUsed /* 35 not used */ -}; - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void ResetException(void) -{ - uint32_t *pSrc, *pDest; - - LowLevelInit(); - - /* Initialize the relocate segment */ - pSrc = &_efixed; - pDest = &_srelocate; - if (pSrc != pDest) { - for(; pDest < &_erelocate;) { - - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for(pDest = &_szero; pDest < &_ezero;) { - - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *)&_sfixed; - SCB->VTOR = ((uint32_t)(pSrc)) & 0x2FFFFFF8; - - /* Branch to main function */ - main(); - - /* Infinite loop */ - while(1); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_cstartup_iar.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_cstartup_iar.c deleted file mode 100644 index fbfcca218..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_cstartup_iar.c +++ /dev/null @@ -1,143 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Headers - *------------------------------------------------------------------------------*/ - -#include "board.h" -#include - -#include "exceptions.h" -#include "board_lowlevel.h" - -/*------------------------------------------------------------------------------ - * Types - *------------------------------------------------------------------------------*/ -typedef union { IntFunc __fun; void * __ptr; } IntVector; - -/*------------------------------------------------------------------------------ - * ProtoTypes - *------------------------------------------------------------------------------*/ -extern void __iar_program_start( void ); - -int __low_level_init( void ); - -/*------------------------------------------------------------------------------ - * Variables - *------------------------------------------------------------------------------*/ -extern unsigned int __ICFEDIT_vector_start__; - - -/*------------------------------------------------------------------------------ - * Exception Table - *------------------------------------------------------------------------------*/ -#pragma language=extended -#pragma segment="CSTACK" - -/* The name "__vector_table" has special meaning for C-SPY: */ -/* it is where the SP start value is found, and the NVIC vector */ -/* table register (VTOR) is initialized to this address if != 0. */ - -#pragma section = ".vectors" -#pragma location = ".vectors" -const IntVector __vector_table[] = -{ - { .__ptr = __sfe( "CSTACK" ) }, - __iar_program_start, - - NMI_Handler, - HardFault_Handler, - MemManage_Handler, - BusFault_Handler, - UsageFault_Handler, - 0, 0, 0, 0, /* Reserved */ - SVC_Handler, - DebugMon_Handler, - 0, /* Reserved */ - PendSV_Handler, - SysTick_Handler, - - /* Configurable interrupts */ - SUPC_IrqHandler, /* 0 SUPPLY CONTROLLER */ - RSTC_IrqHandler, /* 1 RESET CONTROLLER */ - RTC_IrqHandler, /* 2 REAL TIME CLOCK */ - RTT_IrqHandler, /* 3 REAL TIME TIMER */ - WDT_IrqHandler, /* 4 WATCHDOG TIMER */ - PMC_IrqHandler, /* 5 PMC */ - EEFC_IrqHandler, /* 6 EEFC */ - IrqHandlerNotUsed, /* 7 Reserved */ - UART0_IrqHandler, /* 8 UART0 */ - UART1_IrqHandler, /* 9 UART1 */ - SMC_IrqHandler, /* 10 SMC */ - PIOA_IrqHandler, /* 11 Parallel IO Controller A */ - PIOB_IrqHandler, /* 12 Parallel IO Controller B */ - PIOC_IrqHandler, /* 13 Parallel IO Controller C */ - USART0_IrqHandler, /* 14 USART 0 */ - USART1_IrqHandler, /* 15 USART 1 */ - IrqHandlerNotUsed, /* 16 Reserved */ - IrqHandlerNotUsed, /* 17 Reserved */ - MCI_IrqHandler, /* 18 MCI */ - TWI0_IrqHandler, /* 19 TWI 0 */ - TWI1_IrqHandler, /* 20 TWI 1 */ - SPI_IrqHandler, /* 21 SPI */ - SSC_IrqHandler, /* 22 SSC */ - TC0_IrqHandler, /* 23 Timer Counter 0 */ - TC1_IrqHandler, /* 24 Timer Counter 1 */ - TC2_IrqHandler, /* 25 Timer Counter 2 */ - TC3_IrqHandler, /* 26 Timer Counter 3 */ - TC4_IrqHandler, /* 27 Timer Counter 4 */ - TC5_IrqHandler, /* 28 Timer Counter 5 */ - ADC_IrqHandler, /* 29 ADC controller */ - DAC_IrqHandler, /* 30 DAC controller */ - PWM_IrqHandler, /* 31 PWM */ - CRCCU_IrqHandler, /* 32 CRC Calculation Unit */ - ACC_IrqHandler, /* 33 Analog Comparator */ - USBD_IrqHandler, /* 34 USB Device Port */ - IrqHandlerNotUsed /* 35 not used */ -}; - -/*------------------------------------------------------------------------------ - * Exception Table - *------------------------------------------------------------------------------*/ - -/**------------------------------------------------------------------------------ - * This is the code that gets called on processor reset. To initialize the - * device. - *------------------------------------------------------------------------------*/ -int __low_level_init( void ) -{ - unsigned int * src = __section_begin(".vectors"); - - LowLevelInit(); - - SCB->VTOR = ((unsigned int)(src)) | (0x0 << 7); - - return 1; /* if return 0, the data sections will not be initialized. */ -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_cstartup_keil.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_cstartup_keil.c deleted file mode 100644 index aeb935866..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_cstartup_keil.c +++ /dev/null @@ -1,131 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ -#include "board.h" -#include "exceptions.h" -#include "board_lowlevel.h" - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Types -//------------------------------------------------------------------------------ -typedef union { IntFunc __fun; void * __ptr; } IrqVector; - -//------------------------------------------------------------------------------ -// ProtoTypes -//------------------------------------------------------------------------------ -extern int Image$$ARM_LIB_STACK$$ZI$$Limit; -extern int Image$$Vector_region$$Base; -extern int Image$$Vector_region$$Limit; - -extern void __main(void); -void resetHandler( void ); - -//------------------------------------------------------------------------------ -// Variables -//------------------------------------------------------------------------------ - -#pragma arm section rodata="vectors" -const IrqVector __vector_table[] = -{ - (IntFunc)&Image$$ARM_LIB_STACK$$ZI$$Limit, - resetHandler, - - NMI_Handler, - HardFault_Handler, - MemManage_Handler, - BusFault_Handler, - UsageFault_Handler, - 0, 0, 0, 0, // Reserved - SVC_Handler, - DebugMon_Handler, - 0, // Reserved - PendSV_Handler, - SysTick_Handler, - - // Configurable interrupts - SUPC_IrqHandler, // 0 SUPPLY CONTROLLER - RSTC_IrqHandler, // 1 RESET CONTROLLER - RTC_IrqHandler, // 2 REAL TIME CLOCK - RTT_IrqHandler, // 3 REAL TIME TIMER - WDT_IrqHandler, // 4 WATCHDOG TIMER - PMC_IrqHandler, // 5 PMC - EFC0_IrqHandler, // 6 EFC0 - EFC1_IrqHandler, // 7 EFC1 - DBGU_IrqHandler, // 8 DBGU - HSMC4_IrqHandler, // 9 HSMC4 - PIOA_IrqHandler, // 10 Parallel IO Controller A - PIOB_IrqHandler, // 11 Parallel IO Controller B - PIOC_IrqHandler, // 12 Parallel IO Controller C - USART0_IrqHandler, // 13 USART 0 - USART1_IrqHandler, // 14 USART 1 - USART2_IrqHandler, // 15 USART 2 - USART3_IrqHandler, // 16 USART 3 - MCI0_IrqHandler, // 17 Multimedia Card Interface - TWI0_IrqHandler, // 18 TWI 0 - TWI1_IrqHandler, // 19 TWI 1 - SPI0_IrqHandler, // 20 Serial Peripheral Interface - SSC0_IrqHandler, // 21 Serial Synchronous Controller 0 - TC0_IrqHandler, // 22 Timer Counter 0 - TC1_IrqHandler, // 23 Timer Counter 1 - TC2_IrqHandler, // 24 Timer Counter 2 - PWM_IrqHandler, // 25 Pulse Width Modulation Controller - ADCC0_IrqHandler, // 26 ADC controller0 - ADCC1_IrqHandler, // 27 ADC controller1 - HDMA_IrqHandler, // 28 HDMA - UDPD_IrqHandler, // 29 USB Device High Speed UDP_HS - IrqHandlerNotUsed // 30 not used -}; -#pragma arm section - -//------------------------------------------------------------------------------ -/// This is the code that gets called on processor reset. To initialize the -/// device. -//------------------------------------------------------------------------------ -void resetHandler( void ) -{ - unsigned int *pSrc = (unsigned int *)&Image$$Vector_region$$Base; - - // Low level Initialize - LowLevelInit(); - - AT91C_BASE_NVIC->NVIC_VTOFFR = ((unsigned int)(pSrc)) | (0x0 << 7); - - // Enter C library entry point - __main(); - - /* Infinite loop */ - while(1); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_lowlevel.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_lowlevel.c deleted file mode 100644 index 63ce7117d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_lowlevel.c +++ /dev/null @@ -1,141 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "board.h" -#include "board_memories.h" -#include "board_lowlevel.h" -#include - -/*---------------------------------------------------------------------------- - * Local definitions - *----------------------------------------------------------------------------*/ -/** Define clock timeout */ -#define CLOCK_TIMEOUT 5000 - -/*---------------------------------------------------------------------------- - * Local functions - *----------------------------------------------------------------------------*/ -static void BOARD_ConfigurePmc(void) -{ - -#define AT91C_CKGR_MUL_SHIFT 16 -#define AT91C_CKGR_PLLCOUNT_SHIFT 8 -#define AT91C_CKGR_DIV_SHIFT 0 - -// Settings at 64 MHz for MCK - -#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST & (0x8 << 8)) - -// PLLA Settings 64 MHz : 12 / 3 * 32 -#define BOARD_PLLAR ((1 << 29) | (0x1F << AT91C_CKGR_MUL_SHIFT) \ - | (0x1 << AT91C_CKGR_PLLCOUNT_SHIFT) | (0x3 << AT91C_CKGR_DIV_SHIFT)) - -// PLLB Settings 96 MHz -#define BOARD_PLLBR ((1 << 29) | (0x7 << AT91C_CKGR_MUL_SHIFT) \ - | (0x1 << AT91C_CKGR_PLLCOUNT_SHIFT) | (0x1 << AT91C_CKGR_DIV_SHIFT)) - -// USB on PLLB, MCK/PCK on PLLA -#define BOARD_MCKR ( PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK) - -// Define clock timeout -#undef CLOCK_TIMEOUT -#define CLOCK_TIMEOUT 0xFFFFFFFF - - uint32_t timeout = 0; - - /* Enable NRST reset - ************************************/ - //AT91C_BASE_RSTC->RSTC_RMR |= AT91C_RSTC_URSTEN; - - /* Initialize main oscillator - ****************************/ - if(!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) - { - - PMC->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; - timeout = 0; - while (!(PMC->PMC_SR & PMC_SR_MOSCXTS) && (timeout++ < CLOCK_TIMEOUT)); - - } - - /* Switch to 3-20MHz Xtal oscillator */ - PMC->CKGR_MOR = (0x37 << 16) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; - timeout = 0; - while (!(PMC->PMC_SR & PMC_SR_MOSCSELS) && (timeout++ < CLOCK_TIMEOUT)); - PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; - timeout = 0; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - - /** Set 3 WS for Embedded Flash Access */ - EFC->EEFC_FMR = (3 << 8); - - /* Initialize PLLA */ - PMC->CKGR_PLLAR = BOARD_PLLAR; - timeout = 0; - while (!(PMC->PMC_SR & PMC_SR_LOCKA) && (timeout++ < CLOCK_TIMEOUT)); - - /* Initialize PLLB */ - PMC->CKGR_PLLBR = BOARD_PLLBR; - timeout = 0; - while (!(PMC->PMC_SR & PMC_SR_LOCKB) && (timeout++ < CLOCK_TIMEOUT)); - - // Set USB clock on PLLB - REG_PMC_USB = PMC_USB_USBS | (PMC_USB_USBDIV & (1 << 8)); - - /* Switch to fast clock - **********************/ - PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS) | PMC_MCKR_CSS_MAIN_CLK; - timeout = 0; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - - PMC->PMC_MCKR = BOARD_MCKR; - timeout = 0; - while (!(PMC->PMC_SR & PMC_SR_MCKRDY) && (timeout++ < CLOCK_TIMEOUT)); - -} - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------------*/ -/** - * \brief Performs the low-level initialization of the chip. This includes EFC, - * master clock and watchdog configuration. - */ -/*----------------------------------------------------------------------------*/ -void LowLevelInit (void) -{ - /** Configure PMC */ - BOARD_ConfigurePmc(); -} \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_lowlevel.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_lowlevel.h deleted file mode 100644 index c7effdf1f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_lowlevel.h +++ /dev/null @@ -1,49 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Collection of methods for lowlevel. -/// -//------------------------------------------------------------------------------ - -#ifndef BOARD_LOWLEVEL_H -#define BOARD_LOWLEVEL_H - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -extern void LowLevelInit(void); -extern void OptimizeCpuSpeed(void); - -#endif // BOARD_LOWLEVEL_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_memories.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_memories.c deleted file mode 100644 index 6c2242635..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_memories.c +++ /dev/null @@ -1,96 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: Memories implementation -*/ -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include -#include "board_memories.h" - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - - -/** - * \brief Configures the EBI for NandFlash access. - * - */ -extern void BOARD_ConfigureNandFlash( void ) -{ - // Open EBI clock - PMC->PMC_PCER0 = (1<< ID_SMC); - // NCS0 is assigned to a NAND Flash (NANDOE and NANWE used for NCS0) - MATRIX->CCFG_SMCNFCS = CCFG_SMCNFCS_SMC_NFCS0; - -#if 0 - SMC->SMC_CS_NUMBER[0].SMC_SETUP = 0 - | ((0 << 0) & SMC_SETUP0_NWE_SETUP) - | ((1 << 8) & SMC_SETUP0_NCS_WR_SETUP) - | ((0 << 16) & SMC_SETUP0_NRD_SETUP) - | ((1 << 24) & SMC_SETUP0_NCS_RD_SETUP); - - SMC->SMC_CS_NUMBER[0].SMC_PULSE = 0 - | ((2 << 0) & SMC_PULSE0_NWE_PULSE) - | ((3 << 8) & SMC_PULSE0_NCS_WR_PULSE) - | ((4 << 16) & SMC_PULSE0_NRD_PULSE) - | ((4 << 24) & SMC_PULSE0_NCS_RD_PULSE); - - SMC->SMC_CS_NUMBER[0].SMC_CYCLE = 0 - | ((4 << 0) & SMC_CYCLE0_NWE_CYCLE) - | ((7 << 16) & SMC_CYCLE0_NRD_CYCLE); - - SMC->SMC_CS_NUMBER[0].SMC_MODE = SMC_MODE0_READ_MODE | SMC_MODE0_WRITE_MODE; -#else - SMC->SMC_CS_NUMBER[0].SMC_SETUP = 0 - | ((0 << 0) & SMC_SETUP0_NWE_SETUP) - | ((0 << 8) & SMC_SETUP0_NCS_WR_SETUP) - | ((0 << 16) & SMC_SETUP0_NRD_SETUP) - | ((0 << 24) & SMC_SETUP0_NCS_RD_SETUP); - - SMC->SMC_CS_NUMBER[0].SMC_PULSE = 0 - | ((2 << 0) & SMC_PULSE0_NWE_PULSE) - | ((2 << 8) & SMC_PULSE0_NCS_WR_PULSE) - | ((2 << 16) & SMC_PULSE0_NRD_PULSE) - | ((2 << 24) & SMC_PULSE0_NCS_RD_PULSE); - - SMC->SMC_CS_NUMBER[0].SMC_CYCLE = 0 - | ((3 << 0) & SMC_CYCLE0_NWE_CYCLE) - | ((3 << 16) & SMC_CYCLE0_NRD_CYCLE); - - SMC->SMC_CS_NUMBER[0].SMC_MODE = SMC_MODE1_READ_MODE | SMC_MODE1_WRITE_MODE; -#endif - - - -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_memories.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_memories.h deleted file mode 100644 index b9f472ff8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/board_memories.h +++ /dev/null @@ -1,49 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// !Purpose -/// -/// -/// !Usage -/// -//------------------------------------------------------------------------------ - -#ifndef BOARD_MEMORIES_H -#define BOARD_MEMORIES_H - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void BOARD_ConfigureNandFlash( void ) ; - -#endif //#ifndef BOARD_MEMORIES_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/exceptions.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/exceptions.c deleted file mode 100644 index b9b329bf5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/exceptions.c +++ /dev/null @@ -1,385 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * This file contains the default exception handlers. - * - * \note - * The exception handler has weak aliases. - * As they are weak aliases, any function with the same name will override - * this definition. - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "exceptions.h" -#include - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Default interrupt handler for not used irq. - */ -void IrqHandlerNotUsed(void) -{ - while(1); -} - -/** - * \brief Default NMI interrupt handler. - */ -WEAK void NMI_Handler(void) -{ - while(1); -} - -/** - * \brief Default HardFault interrupt handler. - */ -WEAK void HardFault_Handler(void) -{ - while(1); -} - -/** - * \brief Default MemManage interrupt handler. - */ -WEAK void MemManage_Handler(void) -{ - while(1); -} - -/** - * \brief Default BusFault interrupt handler. - */ -WEAK void BusFault_Handler(void) -{ - while(1); -} - -/** - * \brief Default UsageFault interrupt handler. - */ -WEAK void UsageFault_Handler(void) -{ - while(1); -} - -/** - * \brief Default SVC interrupt handler. - */ -WEAK void SVC_Handler(void) -{ - while(1); -} - -/** - * \brief Default DebugMon interrupt handler. - */ -WEAK void DebugMon_Handler(void) -{ - while(1); -} - -/** - * \brief Default PendSV interrupt handler. - */ -WEAK void PendSV_Handler(void) -{ - while(1); -} - -/** - * \brief Default SysTick interrupt handler. - */ -WEAK void SysTick_Handler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for Supply Controller. - */ -WEAK void SUPC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for Reset Controller. - */ -WEAK void RSTC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for Real Time Clock. - */ -WEAK void RTC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for Real Time Timer. - */ -WEAK void RTT_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for Watchdog Timer. - */ -WEAK void WDT_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for PMC. - */ -WEAK void PMC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for EEFC. - */ -WEAK void EEFC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for UART0. - */ -WEAK void UART0_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for UART1. - */ -WEAK void UART1_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for SMC. - */ -WEAK void SMC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for PIOA Controller. - */ -WEAK void PIOA_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for PIOB Controller. - */ -WEAK void PIOB_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for PIOC Controller. - */ -WEAK void PIOC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for USART0. - */ -WEAK void USART0_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for USART1. - */ -WEAK void USART1_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for MCI. - */ -WEAK void MCI_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for TWI0. - */ -WEAK void TWI0_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for TWI1. - */ -WEAK void TWI1_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for SPI. - */ -WEAK void SPI_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for SSC. - */ -WEAK void SSC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for TC0. - */ -WEAK void TC0_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for TC1. - */ -WEAK void TC1_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default interrupt handler for TC2. - */ -WEAK void TC2_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for TC3. - */ -WEAK void TC3_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for TC4. - */ -WEAK void TC4_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for TC5. - */ -WEAK void TC5_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for ADC. - */ -WEAK void ADC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for DAC. - */ -WEAK void DAC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for PWM. - */ -WEAK void PWM_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for CRCCU. - */ -WEAK void CRCCU_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for ACC. - */ -WEAK void ACC_IrqHandler(void) -{ - while(1); -} - -/** - * \brief Default SUPC interrupt handler for USBD. - */ -WEAK void USBD_IrqHandler(void) -{ - while(1); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/exceptions.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/exceptions.h deleted file mode 100644 index b6b366c65..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/board/exceptions.h +++ /dev/null @@ -1,103 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * Interface for default exception handlers. - */ - -#ifndef EXCEPTIONS_H -#define EXCEPTIONS_H - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - -/* Function prototype for exception table items (interrupt handler). */ -typedef void( *IntFunc )( void ); - -/* Define WEAK attribute */ -#if defined ( __CC_ARM ) - #define WEAK __attribute__ ((weak)) -#elif defined ( __ICCARM__ ) - #define WEAK __weak -#elif defined ( __GNUC__ ) - #define WEAK __attribute__ ((weak)) -#endif - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void IrqHandlerNotUsed(void); - -extern WEAK void NMI_Handler( void ); -extern WEAK void HardFault_Handler( void ); -extern WEAK void MemManage_Handler( void ); -extern WEAK void BusFault_Handler( void ); -extern WEAK void UsageFault_Handler( void ); -extern WEAK void SVC_Handler( void ); -extern WEAK void DebugMon_Handler( void ); -extern WEAK void PendSV_Handler( void ); -extern WEAK void SysTick_Handler( void ); - -extern WEAK void SUPC_IrqHandler(void); -extern WEAK void RSTC_IrqHandler(void); -extern WEAK void RTC_IrqHandler(void); -extern WEAK void RTT_IrqHandler(void); -extern WEAK void WDT_IrqHandler(void); -extern WEAK void PMC_IrqHandler(void); -extern WEAK void EEFC_IrqHandler(void); -extern WEAK void UART0_IrqHandler(void); -extern WEAK void UART1_IrqHandler(void); -extern WEAK void SMC_IrqHandler(void); -extern WEAK void PIOA_IrqHandler(void); -extern WEAK void PIOB_IrqHandler(void); -extern WEAK void PIOC_IrqHandler(void); -extern WEAK void USART0_IrqHandler(void); -extern WEAK void USART1_IrqHandler(void); -extern WEAK void MCI_IrqHandler(void); -extern WEAK void TWI0_IrqHandler(void); -extern WEAK void TWI1_IrqHandler(void); -extern WEAK void SPI_IrqHandler(void); -extern WEAK void SSC_IrqHandler(void); -extern WEAK void TC0_IrqHandler(void); -extern WEAK void TC1_IrqHandler(void); -extern WEAK void TC2_IrqHandler(void); -extern WEAK void TC3_IrqHandler(void); -extern WEAK void TC4_IrqHandler(void); -extern WEAK void TC5_IrqHandler(void); -extern WEAK void ADC_IrqHandler(void); -extern WEAK void DAC_IrqHandler(void); -extern WEAK void PWM_IrqHandler(void); -extern WEAK void CRCCU_IrqHandler(void); -extern WEAK void ACC_IrqHandler(void); -extern WEAK void USBD_IrqHandler(void); - -#endif /* #ifndef EXCEPTIONS_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/demo.c deleted file mode 100644 index cb56cabac..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/demo.c +++ /dev/null @@ -1,241 +0,0 @@ -/* - * FreeModbus Libary: Atmel AT91SAM3S Demo Application - * Copyright (C) 2010 Christian Walter - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * IF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include -#include - -/* ----------------------- AT91SAM3S includes -------------------------------*/ -#include -#include - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define REG_INPUT_START ( 1000 ) -#define REG_INPUT_NREGS ( 64 ) - -#define REG_HOLDING_START ( 1 ) -#define REG_HOLDING_NREGS ( 32 ) - -#define TASK_MODBUS_STACK_SIZE ( 256 ) -#define TASK_MODBUS_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -#define TASK_APPL_STACK_SIZE ( 256 ) -#define TASK_APPL_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* ----------------------- Static functions ---------------------------------*/ -static void _SetupHardware( void ); -static void vTaskApplication( void *pvArg ); -static void vTaskMODBUS( void *pvArg ); - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegInputStart = REG_INPUT_START; -static USHORT usRegInputBuf[REG_INPUT_NREGS]; -static USHORT usRegHoldingStart = REG_HOLDING_START; -static USHORT usRegHoldingBuf[REG_HOLDING_NREGS]; - -/* ----------------------- Start implementation -----------------------------*/ -int -main( void ) -{ - _SetupHardware( ); - - if( pdPASS != xTaskCreate( vTaskMODBUS, "MODBUS", TASK_MODBUS_STACK_SIZE, NULL, TASK_MODBUS_PRIORITY, NULL ) ) - { - } - else if( pdPASS != xTaskCreate( vTaskApplication, "APPL", TASK_APPL_STACK_SIZE, NULL, TASK_APPL_PRIORITY, NULL ) ) - { - } - else - { - vTaskStartScheduler( ); - } - return 1; -} - -static void -vTaskApplication( void *pvArg ) -{ - for( ;; ) - { - vTaskDelay( 1000 ); - } -} - -static void -vTaskMODBUS( void *pvArg ) -{ - const UCHAR ucSlaveID[] = { 0xAA, 0xBB, 0xCC }; - eMBErrorCode eStatus; - - for( ;; ) - { - if( MB_ENOERR != ( eStatus = eMBInit( MB_ASCII, 0x0A, 1, 38400, MB_PAR_EVEN ) ) ) - { - /* Can not initialize. Add error handling code here. */ - } - else - { - if( MB_ENOERR != ( eStatus = eMBSetSlaveID( 0x34, TRUE, ucSlaveID, 3 ) ) ) - { - /* Can not set slave id. Check arguments */ - } - else if( MB_ENOERR != ( eStatus = eMBEnable( ) ) ) - { - /* Enable failed. */ - } - else - { - usRegHoldingBuf[0] = 1; - do - { - ( void )eMBPoll( ); - - /* Here we simply count the number of poll cycles. */ - usRegInputBuf[0]++; - } - while( usRegHoldingBuf[0] ); - } - ( void )eMBDisable( ); - ( void )eMBClose( ); - } - vTaskDelay( 50 ); - } -} - -static void -_SetupHardware( void ) -{ - WDT_Disable( ); - - uint32_t i = 0; - for( i = 0; i < 35; i++ ) - { - NVIC_SetPriority( ( IRQn_Type ) i, 0xF << 4 ); - } -} - -void -vApplicationStackOverflowHook( xTaskHandle * pxTask, signed char *pcTaskName ) -{ - ( void )pxTask; - ( void )pcTaskName; - for( ;; ); -} - -void -vApplicationIdleHook( void ) -{ -} - -void -vApplicationTickHook( void ) -{ -} - - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_HOLDING_START ) && ( usAddress + usNRegs <= REG_HOLDING_START + REG_HOLDING_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegHoldingStart ); - switch ( eMode ) - { - case MB_REG_READ: - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegHoldingBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegHoldingBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - break; - - case MB_REG_WRITE: - while( usNRegs > 0 ) - { - usRegHoldingBuf[iRegIndex] = *pucRegBuffer++ << 8; - usRegHoldingBuf[iRegIndex] |= *pucRegBuffer++; - iRegIndex++; - usNRegs--; - } - } - } - else - { - eStatus = MB_ENOREG; - } - return eStatus; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/demo.ewp b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/demo.ewp deleted file mode 100644 index 0997336e7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/demo.ewp +++ /dev/null @@ -1,1791 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 17 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 22 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 7 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 17 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 22 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 7 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 9 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - board - - $PROJ_DIR$\board\board_cstartup_iar.c - - - $PROJ_DIR$\board\board_lowlevel.c - - - $PROJ_DIR$\board\board_memories.c - - - $PROJ_DIR$\board\exceptions.c - - - - drivers - - $PROJ_DIR$\libraries\drivers\pio\pio.c - - - $PROJ_DIR$\libraries\drivers\pmc\pmc.c - - - $PROJ_DIR$\libraries\drivers\tc\tc.c - - - $PROJ_DIR$\libraries\drivers\usart\usart.c - - - $PROJ_DIR$\libraries\drivers\wdt\wdt.c - - - - freertos - - $PROJ_DIR$\freertos\croutine.c - - - $PROJ_DIR$\freertos\FreeRTOSConfig.h - - - $PROJ_DIR$\freertos\portable\MemMang\heap_2.c - - - $PROJ_DIR$\freertos\list.c - - - $PROJ_DIR$\freertos\portable\IAR\ARM_CM3\port.c - - - $PROJ_DIR$\freertos\portable\IAR\ARM_CM3\portasm.s - - - $PROJ_DIR$\freertos\portable\IAR\ARM_CM3\portmacro.h - - - $PROJ_DIR$\freertos\queue.c - - - $PROJ_DIR$\freertos\tasks.c - - - - modbus - - $PROJ_DIR$\..\..\modbus\mb.c - - - $PROJ_DIR$\..\..\modbus\include\mb.h - - - $PROJ_DIR$\..\..\modbus\ascii\mbascii.c - - - $PROJ_DIR$\..\..\modbus\ascii\mbascii.h - - - $PROJ_DIR$\..\..\modbus\include\mbconfig.h - - - $PROJ_DIR$\..\..\modbus\rtu\mbcrc.c - - - $PROJ_DIR$\..\..\modbus\rtu\mbcrc.h - - - $PROJ_DIR$\..\..\modbus\include\mbframe.h - - - $PROJ_DIR$\..\..\modbus\include\mbfunc.h - - - $PROJ_DIR$\..\..\modbus\functions\mbfunccoils.c - - - $PROJ_DIR$\..\..\modbus\functions\mbfuncdiag.c - - - $PROJ_DIR$\..\..\modbus\functions\mbfuncdisc.c - - - $PROJ_DIR$\..\..\modbus\functions\mbfuncholding.c - - - $PROJ_DIR$\..\..\modbus\functions\mbfuncinput.c - - - $PROJ_DIR$\..\..\modbus\functions\mbfuncother.c - - - $PROJ_DIR$\..\..\modbus\include\mbport.h - - - $PROJ_DIR$\..\..\modbus\include\mbproto.h - - - $PROJ_DIR$\..\..\modbus\rtu\mbrtu.c - - - $PROJ_DIR$\..\..\modbus\rtu\mbrtu.h - - - $PROJ_DIR$\..\..\modbus\functions\mbutils.c - - - $PROJ_DIR$\..\..\modbus\include\mbutils.h - - - - port - - $PROJ_DIR$\port\port.h - - - $PROJ_DIR$\port\portevent.c - - - $PROJ_DIR$\port\portother.c - - - $PROJ_DIR$\port\portserial.c - - - $PROJ_DIR$\port\porttimer.c - - - - $PROJ_DIR$\demo.c - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/demo.eww b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/demo.eww deleted file mode 100644 index 2b25c1341..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/demo.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\demo.ewp - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/demo_rtu.bat b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/demo_rtu.bat deleted file mode 100644 index 402b47572..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/demo_rtu.bat +++ /dev/null @@ -1 +0,0 @@ -..\..\tools\modpoll.exe -m rtu -a 10 -r 1000 -c 4 -t 3 -b 38400 -d 8 -p even COM1 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/FreeRTOSConfig.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/FreeRTOSConfig.h deleted file mode 100644 index 2ada12d81..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/FreeRTOSConfig.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html. - *----------------------------------------------------------*/ - - -//#define configUSE_PREEMPTION 1 -#define configUSE_PREEMPTION 0 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 1 -#define configCPU_CLOCK_HZ ( ( unsigned long ) 64000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 70 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 0x2C00 ) ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 0 -#define configUSE_CO_ROUTINES 0 -#define configUSE_MUTEXES 1 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configCHECK_FOR_STACK_OVERFLOW 2 - -#define configGENERATE_RUN_TIME_STATS 0 -#define configUSE_TRACE_FACILITY 1 - -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) -#define configQUEUE_REGISTRY_SIZE 10 - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 1 - - - -#define configKERNEL_INTERRUPT_PRIORITY ( 0x0f << 4 ) /* Priority 15, or 255 as only the top four bits are implemented. This is the lowest priority. */ -#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 5 << 4 ) /* Priority 5, or 80 as only the top four bits are implemented. */ - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/croutine.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/croutine.c deleted file mode 100644 index fea7c5415..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/croutine.c +++ /dev/null @@ -1,371 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/* - * Some kernel aware debuggers require data to be viewed to be global, rather - * than file scope. - */ -#ifdef portREMOVE_STATIC_QUALIFIER - #define static -#endif - - -/* Lists for ready and blocked co-routines. --------------------*/ -static xList pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ -static xList xDelayedCoRoutineList1; /*< Delayed co-routines. */ -static xList xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ -static xList * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */ -static xList * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ -static xList xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ - -/* Other file private variables. --------------------------------*/ -corCRCB * pxCurrentCoRoutine = NULL; -static unsigned portBASE_TYPE uxTopCoRoutineReadyPriority = 0; -static portTickType xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0; - -/* The initial state of the co-routine when it is created. */ -#define corINITIAL_STATE ( 0 ) - -/* - * Place the co-routine represented by pxCRCB into the appropriate ready queue - * for the priority. It is inserted at the end of the list. - * - * This macro accesses the co-routine ready lists and therefore must not be - * used from within an ISR. - */ -#define prvAddCoRoutineToReadyQueue( pxCRCB ) \ -{ \ - if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ - { \ - uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ - } \ - vListInsertEnd( ( xList * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ -} - -/* - * Utility to ready all the lists used by the scheduler. This is called - * automatically upon the creation of the first co-routine. - */ -static void prvInitialiseCoRoutineLists( void ); - -/* - * Co-routines that are readied by an interrupt cannot be placed directly into - * the ready lists (there is no mutual exclusion). Instead they are placed in - * in the pending ready list in order that they can later be moved to the ready - * list by the co-routine scheduler. - */ -static void prvCheckPendingReadyList( void ); - -/* - * Macro that looks at the list of co-routines that are currently delayed to - * see if any require waking. - * - * Co-routines are stored in the queue in the order of their wake time - - * meaning once one co-routine has been found whose timer has not expired - * we need not look any further down the list. - */ -static void prvCheckDelayedList( void ); - -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ) -{ -signed portBASE_TYPE xReturn; -corCRCB *pxCoRoutine; - - /* Allocate the memory that will store the co-routine control block. */ - pxCoRoutine = ( corCRCB * ) pvPortMalloc( sizeof( corCRCB ) ); - if( pxCoRoutine ) - { - /* If pxCurrentCoRoutine is NULL then this is the first co-routine to - be created and the co-routine data structures need initialising. */ - if( pxCurrentCoRoutine == NULL ) - { - pxCurrentCoRoutine = pxCoRoutine; - prvInitialiseCoRoutineLists(); - } - - /* Check the priority is within limits. */ - if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) - { - uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; - } - - /* Fill out the co-routine control block from the function parameters. */ - pxCoRoutine->uxState = corINITIAL_STATE; - pxCoRoutine->uxPriority = uxPriority; - pxCoRoutine->uxIndex = uxIndex; - pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; - - /* Initialise all the other co-routine control block parameters. */ - vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); - vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); - - /* Set the co-routine control block as a link back from the xListItem. - This is so we can get back to the containing CRCB from a generic item - in a list. */ - listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); - listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); - - /* Event lists are always in priority order. */ - listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); - - /* Now the co-routine has been initialised it can be added to the ready - list at the correct priority. */ - prvAddCoRoutineToReadyQueue( pxCoRoutine ); - - xReturn = pdPASS; - } - else - { - xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList ) -{ -portTickType xTimeToWake; - - /* Calculate the time to wake - this may overflow but this is - not a problem. */ - xTimeToWake = xCoRoutineTickCount + xTicksToDelay; - - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xCoRoutineTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - } - - if( pxEventList ) - { - /* Also add the co-routine to an event list. If this is done then the - function must be called with interrupts disabled. */ - vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); - } -} -/*-----------------------------------------------------------*/ - -static void prvCheckPendingReadyList( void ) -{ - /* Are there any co-routines waiting to get moved to the ready list? These - are co-routines that have been readied by an ISR. The ISR cannot access - the ready lists itself. */ - while( !listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) ) - { - corCRCB *pxUnblockedCRCB; - - /* The pending ready list can be accessed by an ISR. */ - portDISABLE_INTERRUPTS(); - { - pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) ); - vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); - } - portENABLE_INTERRUPTS(); - - vListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); - prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); - } -} -/*-----------------------------------------------------------*/ - -static void prvCheckDelayedList( void ) -{ -corCRCB *pxCRCB; - - xPassedTicks = xTaskGetTickCount() - xLastTickCount; - while( xPassedTicks ) - { - xCoRoutineTickCount++; - xPassedTicks--; - - /* If the tick count has overflowed we need to swap the ready lists. */ - if( xCoRoutineTickCount == 0 ) - { - xList * pxTemp; - - /* Tick count has overflowed so we need to swap the delay lists. If there are - any items in pxDelayedCoRoutineList here then there is an error! */ - pxTemp = pxDelayedCoRoutineList; - pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; - pxOverflowDelayedCoRoutineList = pxTemp; - } - - /* See if this tick has made a timeout expire. */ - while( ( pxCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ) ) != NULL ) - { - if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) - { - /* Timeout not yet expired. */ - break; - } - - portDISABLE_INTERRUPTS(); - { - /* The event could have occurred just before this critical - section. If this is the case then the generic list item will - have been moved to the pending ready list and the following - line is still valid. Also the pvContainer parameter will have - been set to NULL so the following lines are also valid. */ - vListRemove( &( pxCRCB->xGenericListItem ) ); - - /* Is the co-routine waiting on an event also? */ - if( pxCRCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxCRCB->xEventListItem ) ); - } - } - portENABLE_INTERRUPTS(); - - prvAddCoRoutineToReadyQueue( pxCRCB ); - } - } - - xLastTickCount = xCoRoutineTickCount; -} -/*-----------------------------------------------------------*/ - -void vCoRoutineSchedule( void ) -{ - /* See if any co-routines readied by events need moving to the ready lists. */ - prvCheckPendingReadyList(); - - /* See if any delayed co-routines have timed out. */ - prvCheckDelayedList(); - - /* Find the highest priority queue that contains ready co-routines. */ - while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) - { - if( uxTopCoRoutineReadyPriority == 0 ) - { - /* No more co-routines to check. */ - return; - } - --uxTopCoRoutineReadyPriority; - } - - /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines - of the same priority get an equal share of the processor time. */ - listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); - - /* Call the co-routine. */ - ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); - - return; -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseCoRoutineLists( void ) -{ -unsigned portBASE_TYPE uxPriority; - - for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) - { - vListInitialise( ( xList * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); - } - - vListInitialise( ( xList * ) &xDelayedCoRoutineList1 ); - vListInitialise( ( xList * ) &xDelayedCoRoutineList2 ); - vListInitialise( ( xList * ) &xPendingReadyCoRoutineList ); - - /* Start with pxDelayedCoRoutineList using list1 and the - pxOverflowDelayedCoRoutineList using list2. */ - pxDelayedCoRoutineList = &xDelayedCoRoutineList1; - pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList ) -{ -corCRCB *pxUnblockedCRCB; -signed portBASE_TYPE xReturn; - - /* This function is called from within an interrupt. It can only access - event lists and the pending ready list. */ - pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); - vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); - vListInsertEnd( ( xList * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) ); - - if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) - { - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/FreeRTOS.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/FreeRTOS.h deleted file mode 100644 index ed7a36f5b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/FreeRTOS.h +++ /dev/null @@ -1,420 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -#ifndef INC_FREERTOS_H -#define INC_FREERTOS_H - - -/* - * Include the generic headers required for the FreeRTOS port being used. - */ -#include - -/* Basic FreeRTOS definitions. */ -#include "projdefs.h" - -/* Application specific configuration options. */ -#include "FreeRTOSConfig.h" - -/* Definitions specific to the port being used. */ -#include "portable.h" - - -/* Defines the prototype to which the application task hook function must -conform. */ -typedef portBASE_TYPE (*pdTASK_HOOK_CODE)( void * ); - - - - - -/* - * Check all the required application specific macros have been defined. - * These macros are application specific and (as downloaded) are defined - * within FreeRTOSConfig.h. - */ - -#ifndef configUSE_PREEMPTION - #error Missing definition: configUSE_PREEMPTION should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_IDLE_HOOK - #error Missing definition: configUSE_IDLE_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_TICK_HOOK - #error Missing definition: configUSE_TICK_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_CO_ROUTINES - #error Missing definition: configUSE_CO_ROUTINES should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskPrioritySet - #error Missing definition: INCLUDE_vTaskPrioritySet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_uxTaskPriorityGet - #error Missing definition: INCLUDE_uxTaskPriorityGet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelete - #error Missing definition: INCLUDE_vTaskDelete should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskCleanUpResources - #error Missing definition: INCLUDE_vTaskCleanUpResources should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskSuspend - #error Missing definition: INCLUDE_vTaskSuspend should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelayUntil - #error Missing definition: INCLUDE_vTaskDelayUntil should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelay - #error Missing definition: INCLUDE_vTaskDelay should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_16_BIT_TICKS - #error Missing definition: configUSE_16_BIT_TICKS should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_APPLICATION_TASK_TAG - #define configUSE_APPLICATION_TASK_TAG 0 -#endif - -#ifndef INCLUDE_uxTaskGetStackHighWaterMark - #define INCLUDE_uxTaskGetStackHighWaterMark 0 -#endif - -#ifndef configUSE_RECURSIVE_MUTEXES - #define configUSE_RECURSIVE_MUTEXES 0 -#endif - -#ifndef configUSE_MUTEXES - #define configUSE_MUTEXES 0 -#endif - -#ifndef configUSE_COUNTING_SEMAPHORES - #define configUSE_COUNTING_SEMAPHORES 0 -#endif - -#ifndef configUSE_ALTERNATIVE_API - #define configUSE_ALTERNATIVE_API 0 -#endif - -#ifndef portCRITICAL_NESTING_IN_TCB - #define portCRITICAL_NESTING_IN_TCB 0 -#endif - -#ifndef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 16 -#endif - -#ifndef configIDLE_SHOULD_YIELD - #define configIDLE_SHOULD_YIELD 1 -#endif - -#if configMAX_TASK_NAME_LEN < 1 - #undef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 1 -#endif - -#ifndef INCLUDE_xTaskResumeFromISR - #define INCLUDE_xTaskResumeFromISR 1 -#endif - -#ifndef INCLUDE_xTaskGetSchedulerState - #define INCLUDE_xTaskGetSchedulerState 0 -#endif - -#if ( configUSE_MUTEXES == 1 ) - /* xTaskGetCurrentTaskHandle is used by the priority inheritance mechanism - within the mutex implementation so must be available if mutexes are used. */ - #undef INCLUDE_xTaskGetCurrentTaskHandle - #define INCLUDE_xTaskGetCurrentTaskHandle 1 -#else - #ifndef INCLUDE_xTaskGetCurrentTaskHandle - #define INCLUDE_xTaskGetCurrentTaskHandle 0 - #endif -#endif - - -#ifndef portSET_INTERRUPT_MASK_FROM_ISR - #define portSET_INTERRUPT_MASK_FROM_ISR() 0 -#endif - -#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue -#endif - - -#ifndef configQUEUE_REGISTRY_SIZE - #define configQUEUE_REGISTRY_SIZE 0 -#endif - -#if configQUEUE_REGISTRY_SIZE < 1 - #define configQUEUE_REGISTRY_SIZE 0 - #define vQueueAddToRegistry( xQueue, pcName ) - #define vQueueUnregisterQueue( xQueue ) -#endif - - -/* Remove any unused trace macros. */ -#ifndef traceSTART - /* Used to perform any necessary initialisation - for example, open a file - into which trace is to be written. */ - #define traceSTART() -#endif - -#ifndef traceEND - /* Use to close a trace, for example close a file into which trace has been - written. */ - #define traceEND() -#endif - -#ifndef traceTASK_SWITCHED_IN - /* Called after a task has been selected to run. pxCurrentTCB holds a pointer - to the task control block of the selected task. */ - #define traceTASK_SWITCHED_IN() -#endif - -#ifndef traceTASK_SWITCHED_OUT - /* Called before a task has been selected to run. pxCurrentTCB holds a pointer - to the task control block of the task being switched out. */ - #define traceTASK_SWITCHED_OUT() -#endif - -#ifndef traceBLOCKING_ON_QUEUE_RECEIVE - /* Task is about to block because it cannot read from a - queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore - upon which the read was attempted. pxCurrentTCB points to the TCB of the - task that attempted the read. */ - #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) -#endif - -#ifndef traceBLOCKING_ON_QUEUE_SEND - /* Task is about to block because it cannot write to a - queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore - upon which the write was attempted. pxCurrentTCB points to the TCB of the - task that attempted the write. */ - #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) -#endif - -#ifndef configCHECK_FOR_STACK_OVERFLOW - #define configCHECK_FOR_STACK_OVERFLOW 0 -#endif - -/* The following event macros are embedded in the kernel API calls. */ - -#ifndef traceQUEUE_CREATE - #define traceQUEUE_CREATE( pxNewQueue ) -#endif - -#ifndef traceQUEUE_CREATE_FAILED - #define traceQUEUE_CREATE_FAILED() -#endif - -#ifndef traceCREATE_MUTEX - #define traceCREATE_MUTEX( pxNewQueue ) -#endif - -#ifndef traceCREATE_MUTEX_FAILED - #define traceCREATE_MUTEX_FAILED() -#endif - -#ifndef traceGIVE_MUTEX_RECURSIVE - #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) -#endif - -#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED - #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) -#endif - -#ifndef traceTAKE_MUTEX_RECURSIVE - #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) -#endif - -#ifndef traceCREATE_COUNTING_SEMAPHORE - #define traceCREATE_COUNTING_SEMAPHORE() -#endif - -#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED - #define traceCREATE_COUNTING_SEMAPHORE_FAILED() -#endif - -#ifndef traceQUEUE_SEND - #define traceQUEUE_SEND( pxQueue ) -#endif - -#ifndef traceQUEUE_SEND_FAILED - #define traceQUEUE_SEND_FAILED( pxQueue ) -#endif - -#ifndef traceQUEUE_RECEIVE - #define traceQUEUE_RECEIVE( pxQueue ) -#endif - -#ifndef traceQUEUE_PEEK - #define traceQUEUE_PEEK( pxQueue ) -#endif - -#ifndef traceQUEUE_RECEIVE_FAILED - #define traceQUEUE_RECEIVE_FAILED( pxQueue ) -#endif - -#ifndef traceQUEUE_SEND_FROM_ISR - #define traceQUEUE_SEND_FROM_ISR( pxQueue ) -#endif - -#ifndef traceQUEUE_SEND_FROM_ISR_FAILED - #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) -#endif - -#ifndef traceQUEUE_RECEIVE_FROM_ISR - #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) -#endif - -#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED - #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) -#endif - -#ifndef traceQUEUE_DELETE - #define traceQUEUE_DELETE( pxQueue ) -#endif - -#ifndef traceTASK_CREATE - #define traceTASK_CREATE( pxNewTCB ) -#endif - -#ifndef traceTASK_CREATE_FAILED - #define traceTASK_CREATE_FAILED( pxNewTCB ) -#endif - -#ifndef traceTASK_DELETE - #define traceTASK_DELETE( pxTaskToDelete ) -#endif - -#ifndef traceTASK_DELAY_UNTIL - #define traceTASK_DELAY_UNTIL() -#endif - -#ifndef traceTASK_DELAY - #define traceTASK_DELAY() -#endif - -#ifndef traceTASK_PRIORITY_SET - #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) -#endif - -#ifndef traceTASK_SUSPEND - #define traceTASK_SUSPEND( pxTaskToSuspend ) -#endif - -#ifndef traceTASK_RESUME - #define traceTASK_RESUME( pxTaskToResume ) -#endif - -#ifndef traceTASK_RESUME_FROM_ISR - #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) -#endif - -#ifndef traceTASK_INCREMENT_TICK - #define traceTASK_INCREMENT_TICK( xTickCount ) -#endif - -#ifndef configGENERATE_RUN_TIME_STATS - #define configGENERATE_RUN_TIME_STATS 0 -#endif - -#if ( configGENERATE_RUN_TIME_STATS == 1 ) - - #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS - #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. - #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ - - #ifndef portGET_RUN_TIME_COUNTER_VALUE - #error If configGENERATE_RUN_TIME_STATS is defined then portGET_RUN_TIME_COUNTER_VALUE must also be defined. portGET_RUN_TIME_COUNTER_VALUE should evaluate to the counter value of the timer/counter peripheral used as the run time counter time base. - #endif /* portGET_RUN_TIME_COUNTER_VALUE */ - -#endif /* configGENERATE_RUN_TIME_STATS */ - -#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS - #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() -#endif - -#ifndef configUSE_MALLOC_FAILED_HOOK - #define configUSE_MALLOC_FAILED_HOOK 0 -#endif - -#ifndef portPRIVILEGE_BIT - #define portPRIVILEGE_BIT ( ( unsigned portBASE_TYPE ) 0x00 ) -#endif - -#ifndef portYIELD_WITHIN_API - #define portYIELD_WITHIN_API portYIELD -#endif - -#ifndef pvPortMallocAligned - #define pvPortMallocAligned( xSize, pvBuffer ) pvPortMalloc( xSize ); ( void ) pvBuffer -#endif - -#ifndef vPortFreeAligned - #define vPortFreeAligned( pvBlockToFree ) vPortFree( pvBlockToFree ) -#endif - -#endif /* INC_FREERTOS_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/StackMacros.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/StackMacros.h deleted file mode 100644 index b0c48224c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/StackMacros.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -#ifndef STACK_MACROS_H -#define STACK_MACROS_H - -/* - * Call the stack overflow hook function if the stack of the task being swapped - * out is currently overflowed, or looks like it might have overflowed in the - * past. - * - * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check - * the current stack state only - comparing the current top of stack value to - * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1 - * will also cause the last few stack bytes to be checked to ensure the value - * to which the bytes were set when the task was created have not been - * overwritten. Note this second test does not guarantee that an overflowed - * stack will always be recognised. - */ - -/*-----------------------------------------------------------*/ - -#if( configCHECK_FOR_STACK_OVERFLOW == 0 ) - - /* FreeRTOSConfig.h is not set to check for stack overflows. */ - #define taskFIRST_CHECK_FOR_STACK_OVERFLOW() - #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() - -#endif /* configCHECK_FOR_STACK_OVERFLOW == 0 */ -/*-----------------------------------------------------------*/ - -#if( configCHECK_FOR_STACK_OVERFLOW == 1 ) - - /* FreeRTOSConfig.h is only set to use the first method of - overflow checking. */ - #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() - -#endif -/*-----------------------------------------------------------*/ - -#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH < 0 ) ) - - /* Only the current stack state is to be checked. */ - #define taskFIRST_CHECK_FOR_STACK_OVERFLOW() \ - { \ - extern void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName ); \ - \ - /* Is the currently saved stack pointer within the stack limit? */ \ - if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) \ - { \ - vApplicationStackOverflowHook( ( xTaskHandle ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ - } \ - } - -#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ -/*-----------------------------------------------------------*/ - -#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH > 0 ) ) - - /* Only the current stack state is to be checked. */ - #define taskFIRST_CHECK_FOR_STACK_OVERFLOW() \ - { \ - extern void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName ); \ - \ - /* Is the currently saved stack pointer within the stack limit? */ \ - if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack ) \ - { \ - vApplicationStackOverflowHook( ( xTaskHandle ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ - } \ - } - -#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ -/*-----------------------------------------------------------*/ - -#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) ) - - #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() \ - { \ - extern void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName ); \ - static const unsigned char ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ - tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ - tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ - tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ - tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \ - \ - \ - /* Has the extremity of the task stack ever been written over? */ \ - if( memcmp( ( void * ) pxCurrentTCB->pxStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \ - { \ - vApplicationStackOverflowHook( ( xTaskHandle ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ - } \ - } - -#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ -/*-----------------------------------------------------------*/ - -#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) ) - - #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() \ - { \ - extern void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName ); \ - char *pcEndOfStack = ( char * ) pxCurrentTCB->pxEndOfStack; \ - static const unsigned char ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ - tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ - tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ - tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ - tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \ - \ - \ - pcEndOfStack -= sizeof( ucExpectedStackBytes ); \ - \ - /* Has the extremity of the task stack ever been written over? */ \ - if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \ - { \ - vApplicationStackOverflowHook( ( xTaskHandle ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ - } \ - } - -#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ -/*-----------------------------------------------------------*/ - -#endif /* STACK_MACROS_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/croutine.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/croutine.h deleted file mode 100644 index dc52c0f62..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/croutine.h +++ /dev/null @@ -1,749 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -#ifndef INC_FREERTOS_H - #error "#include FreeRTOS.h" must appear in source files before "#include croutine.h" -#endif - - - - -#ifndef CO_ROUTINE_H -#define CO_ROUTINE_H - -#include "list.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Used to hide the implementation of the co-routine control block. The -control block structure however has to be included in the header due to -the macro implementation of the co-routine functionality. */ -typedef void * xCoRoutineHandle; - -/* Defines the prototype to which co-routine functions must conform. */ -typedef void (*crCOROUTINE_CODE)( xCoRoutineHandle, unsigned portBASE_TYPE ); - -typedef struct corCoRoutineControlBlock -{ - crCOROUTINE_CODE pxCoRoutineFunction; - xListItem xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ - xListItem xEventListItem; /*< List item used to place the CRCB in event lists. */ - unsigned portBASE_TYPE uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ - unsigned portBASE_TYPE uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ - unsigned short uxState; /*< Used internally by the co-routine implementation. */ -} corCRCB; /* Co-routine control block. Note must be identical in size down to uxPriority with tskTCB. */ - -/** - * croutine. h - *
- portBASE_TYPE xCoRoutineCreate(
-                                 crCOROUTINE_CODE pxCoRoutineCode,
-                                 unsigned portBASE_TYPE uxPriority,
-                                 unsigned portBASE_TYPE uxIndex
-                               );
- * - * Create a new co-routine and add it to the list of co-routines that are - * ready to run. - * - * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine - * functions require special syntax - see the co-routine section of the WEB - * documentation for more information. - * - * @param uxPriority The priority with respect to other co-routines at which - * the co-routine will run. - * - * @param uxIndex Used to distinguish between different co-routines that - * execute the same function. See the example below and the co-routine section - * of the WEB documentation for further information. - * - * @return pdPASS if the co-routine was successfully created and added to a ready - * list, otherwise an error code defined with ProjDefs.h. - * - * Example usage: -
- // Co-routine to be created.
- void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- // This may not be necessary for const variables.
- static const char cLedToFlash[ 2 ] = { 5, 6 };
- static const portTickType xTimeToDelay[ 2 ] = { 200, 400 };
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // This co-routine just delays for a fixed period, then toggles
-         // an LED.  Two co-routines are created using this function, so
-         // the uxIndex parameter is used to tell the co-routine which
-         // LED to flash and how long to delay.  This assumes xQueue has
-         // already been created.
-         vParTestToggleLED( cLedToFlash[ uxIndex ] );
-         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
-
- // Function that creates two co-routines.
- void vOtherFunction( void )
- {
- unsigned char ucParameterToPass;
- xTaskHandle xHandle;
-		
-     // Create two co-routines at priority 0.  The first is given index 0
-     // so (from the code above) toggles LED 5 every 200 ticks.  The second
-     // is given index 1 so toggles LED 6 every 400 ticks.
-     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
-     {
-         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
-     }
- }
-   
- * \defgroup xCoRoutineCreate xCoRoutineCreate - * \ingroup Tasks - */ -signed portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ); - - -/** - * croutine. h - *
- void vCoRoutineSchedule( void );
- * - * Run a co-routine. - * - * vCoRoutineSchedule() executes the highest priority co-routine that is able - * to run. The co-routine will execute until it either blocks, yields or is - * preempted by a task. Co-routines execute cooperatively so one - * co-routine cannot be preempted by another, but can be preempted by a task. - * - * If an application comprises of both tasks and co-routines then - * vCoRoutineSchedule should be called from the idle task (in an idle task - * hook). - * - * Example usage: -
- // This idle task hook will schedule a co-routine each time it is called.
- // The rest of the idle task will execute between co-routine calls.
- void vApplicationIdleHook( void )
- {
-	vCoRoutineSchedule();
- }
-
- // Alternatively, if you do not require any other part of the idle task to
- // execute, the idle task hook can call vCoRoutineScheduler() within an
- // infinite loop.
- void vApplicationIdleHook( void )
- {
-    for( ;; )
-    {
-        vCoRoutineSchedule();
-    }
- }
- 
- * \defgroup vCoRoutineSchedule vCoRoutineSchedule - * \ingroup Tasks - */ -void vCoRoutineSchedule( void ); - -/** - * croutine. h - *
- crSTART( xCoRoutineHandle xHandle );
- * - * This macro MUST always be called at the start of a co-routine function. - * - * Example usage: -
- // Co-routine to be created.
- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static long ulAVariable;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-          // Co-routine functionality goes here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
- * \defgroup crSTART crSTART - * \ingroup Tasks - */ -#define crSTART( pxCRCB ) switch( ( ( corCRCB * )pxCRCB )->uxState ) { case 0: - -/** - * croutine. h - *
- crEND();
- * - * This macro MUST always be called at the end of a co-routine function. - * - * Example usage: -
- // Co-routine to be created.
- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static long ulAVariable;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-          // Co-routine functionality goes here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
- * \defgroup crSTART crSTART - * \ingroup Tasks - */ -#define crEND() } - -/* - * These macros are intended for internal use by the co-routine implementation - * only. The macros should not be used directly by application writers. - */ -#define crSET_STATE0( xHandle ) ( ( corCRCB * )xHandle)->uxState = (__LINE__ * 2); return; case (__LINE__ * 2): -#define crSET_STATE1( xHandle ) ( ( corCRCB * )xHandle)->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1): - -/** - * croutine. h - *
- crDELAY( xCoRoutineHandle xHandle, portTickType xTicksToDelay );
- * - * Delay a co-routine for a fixed period of time. - * - * crDELAY can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * @param xHandle The handle of the co-routine to delay. This is the xHandle - * parameter of the co-routine function. - * - * @param xTickToDelay The number of ticks that the co-routine should delay - * for. The actual amount of time this equates to is defined by - * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_RATE_MS - * can be used to convert ticks to milliseconds. - * - * Example usage: -
- // Co-routine to be created.
- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- // This may not be necessary for const variables.
- // We are to delay for 200ms.
- static const xTickType xDelayTime = 200 / portTICK_RATE_MS;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-        // Delay for 200ms.
-        crDELAY( xHandle, xDelayTime );
-
-        // Do something here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
- * \defgroup crDELAY crDELAY - * \ingroup Tasks - */ -#define crDELAY( xHandle, xTicksToDelay ) \ - if( xTicksToDelay > 0 ) \ - { \ - vCoRoutineAddToDelayedList( xTicksToDelay, NULL ); \ - } \ - crSET_STATE0( xHandle ); - -/** - *
- crQUEUE_SEND(
-                  xCoRoutineHandle xHandle,
-                  xQueueHandle pxQueue,
-                  void *pvItemToQueue,
-                  portTickType xTicksToWait,
-                  portBASE_TYPE *pxResult
-             )
- * - * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine - * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. - * - * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas - * xQueueSend() and xQueueReceive() can only be used from tasks. - * - * crQUEUE_SEND can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xHandle The handle of the calling co-routine. This is the xHandle - * parameter of the co-routine function. - * - * @param pxQueue The handle of the queue on which the data will be posted. - * The handle is obtained as the return value when the queue is created using - * the xQueueCreate() API function. - * - * @param pvItemToQueue A pointer to the data being posted onto the queue. - * The number of bytes of each queued item is specified when the queue is - * created. This number of bytes is copied from pvItemToQueue into the queue - * itself. - * - * @param xTickToDelay The number of ticks that the co-routine should block - * to wait for space to become available on the queue, should space not be - * available immediately. The actual amount of time this equates to is defined - * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant - * portTICK_RATE_MS can be used to convert ticks to milliseconds (see example - * below). - * - * @param pxResult The variable pointed to by pxResult will be set to pdPASS if - * data was successfully posted onto the queue, otherwise it will be set to an - * error defined within ProjDefs.h. - * - * Example usage: -
- // Co-routine function that blocks for a fixed period then posts a number onto
- // a queue.
- static void prvCoRoutineFlashTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portBASE_TYPE xNumberToPost = 0;
- static portBASE_TYPE xResult;
-
-    // Co-routines must begin with a call to crSTART().
-    crSTART( xHandle );
-
-    for( ;; )
-    {
-        // This assumes the queue has already been created.
-        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
-
-        if( xResult != pdPASS )
-        {
-            // The message was not posted!
-        }
-
-        // Increment the number to be posted onto the queue.
-        xNumberToPost++;
-
-        // Delay for 100 ticks.
-        crDELAY( xHandle, 100 );
-    }
-
-    // Co-routines must end with a call to crEND().
-    crEND();
- }
- * \defgroup crQUEUE_SEND crQUEUE_SEND - * \ingroup Tasks - */ -#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ -{ \ - *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, xTicksToWait ); \ - if( *pxResult == errQUEUE_BLOCKED ) \ - { \ - crSET_STATE0( xHandle ); \ - *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, 0 ); \ - } \ - if( *pxResult == errQUEUE_YIELD ) \ - { \ - crSET_STATE1( xHandle ); \ - *pxResult = pdPASS; \ - } \ -} - -/** - * croutine. h - *
-  crQUEUE_RECEIVE(
-                     xCoRoutineHandle xHandle,
-                     xQueueHandle pxQueue,
-                     void *pvBuffer,
-                     portTickType xTicksToWait,
-                     portBASE_TYPE *pxResult
-                 )
- * - * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine - * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. - * - * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas - * xQueueSend() and xQueueReceive() can only be used from tasks. - * - * crQUEUE_RECEIVE can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xHandle The handle of the calling co-routine. This is the xHandle - * parameter of the co-routine function. - * - * @param pxQueue The handle of the queue from which the data will be received. - * The handle is obtained as the return value when the queue is created using - * the xQueueCreate() API function. - * - * @param pvBuffer The buffer into which the received item is to be copied. - * The number of bytes of each queued item is specified when the queue is - * created. This number of bytes is copied into pvBuffer. - * - * @param xTickToDelay The number of ticks that the co-routine should block - * to wait for data to become available from the queue, should data not be - * available immediately. The actual amount of time this equates to is defined - * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant - * portTICK_RATE_MS can be used to convert ticks to milliseconds (see the - * crQUEUE_SEND example). - * - * @param pxResult The variable pointed to by pxResult will be set to pdPASS if - * data was successfully retrieved from the queue, otherwise it will be set to - * an error code as defined within ProjDefs.h. - * - * Example usage: -
- // A co-routine receives the number of an LED to flash from a queue.  It
- // blocks on the queue until the number is received.
- static void prvCoRoutineFlashWorkTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portBASE_TYPE xResult;
- static unsigned portBASE_TYPE uxLEDToFlash;
-
-    // All co-routines must start with a call to crSTART().
-    crSTART( xHandle );
-
-    for( ;; )
-    {
-        // Wait for data to become available on the queue.
-        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
-
-        if( xResult == pdPASS )
-        {
-            // We received the LED to flash - flash it!
-            vParTestToggleLED( uxLEDToFlash );
-        }
-    }
-
-    crEND();
- }
- * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE - * \ingroup Tasks - */ -#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ -{ \ - *pxResult = xQueueCRReceive( pxQueue, pvBuffer, xTicksToWait ); \ - if( *pxResult == errQUEUE_BLOCKED ) \ - { \ - crSET_STATE0( xHandle ); \ - *pxResult = xQueueCRReceive( pxQueue, pvBuffer, 0 ); \ - } \ - if( *pxResult == errQUEUE_YIELD ) \ - { \ - crSET_STATE1( xHandle ); \ - *pxResult = pdPASS; \ - } \ -} - -/** - * croutine. h - *
-  crQUEUE_SEND_FROM_ISR(
-                            xQueueHandle pxQueue,
-                            void *pvItemToQueue,
-                            portBASE_TYPE xCoRoutinePreviouslyWoken
-                       )
- * - * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the - * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() - * functions used by tasks. - * - * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to - * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and - * xQueueReceiveFromISR() can only be used to pass data between a task and and - * ISR. - * - * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue - * that is being used from within a co-routine. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto - * the same queue multiple times from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. - * - * @return pdTRUE if a co-routine was woken by posting onto the queue. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage: -
- // A co-routine that blocks on a queue waiting for characters to be received.
- static void vReceivingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- char cRxedChar;
- portBASE_TYPE xResult;
-
-     // All co-routines must start with a call to crSTART().
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // Wait for data to become available on the queue.  This assumes the
-         // queue xCommsRxQueue has already been created!
-         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
-
-         // Was a character received?
-         if( xResult == pdPASS )
-         {
-             // Process the character here.
-         }
-     }
-
-     // All co-routines must end with a call to crEND().
-     crEND();
- }
-
- // An ISR that uses a queue to send characters received on a serial port to
- // a co-routine.
- void vUART_ISR( void )
- {
- char cRxedChar;
- portBASE_TYPE xCRWokenByPost = pdFALSE;
-
-     // We loop around reading characters until there are none left in the UART.
-     while( UART_RX_REG_NOT_EMPTY() )
-     {
-         // Obtain the character from the UART.
-         cRxedChar = UART_RX_REG;
-
-         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
-         // the first time around the loop.  If the post causes a co-routine
-         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
-         // In this manner we can ensure that if more than one co-routine is
-         // blocked on the queue only one is woken by this ISR no matter how
-         // many characters are posted to the queue.
-         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
-     }
- }
- * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR - * \ingroup Tasks - */ -#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) - - -/** - * croutine. h - *
-  crQUEUE_SEND_FROM_ISR(
-                            xQueueHandle pxQueue,
-                            void *pvBuffer,
-                            portBASE_TYPE * pxCoRoutineWoken
-                       )
- * - * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the - * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() - * functions used by tasks. - * - * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to - * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and - * xQueueReceiveFromISR() can only be used to pass data between a task and and - * ISR. - * - * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data - * from a queue that is being used from within a co-routine (a co-routine - * posted to the queue). - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvBuffer A pointer to a buffer into which the received item will be - * placed. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from the queue into - * pvBuffer. - * - * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become - * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a - * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise - * *pxCoRoutineWoken will remain unchanged. - * - * @return pdTRUE an item was successfully received from the queue, otherwise - * pdFALSE. - * - * Example usage: -
- // A co-routine that posts a character to a queue then blocks for a fixed
- // period.  The character is incremented each time.
- static void vSendingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // cChar holds its value while this co-routine is blocked and must therefore
- // be declared static.
- static char cCharToTx = 'a';
- portBASE_TYPE xResult;
-
-     // All co-routines must start with a call to crSTART().
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // Send the next character to the queue.
-         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
-
-         if( xResult == pdPASS )
-         {
-             // The character was successfully posted to the queue.
-         }
-		 else
-		 {
-			// Could not post the character to the queue.
-		 }
-
-         // Enable the UART Tx interrupt to cause an interrupt in this
-		 // hypothetical UART.  The interrupt will obtain the character
-		 // from the queue and send it.
-		 ENABLE_RX_INTERRUPT();
-
-		 // Increment to the next character then block for a fixed period.
-		 // cCharToTx will maintain its value across the delay as it is
-		 // declared static.
-		 cCharToTx++;
-		 if( cCharToTx > 'x' )
-		 {
-			cCharToTx = 'a';
-		 }
-		 crDELAY( 100 );
-     }
-
-     // All co-routines must end with a call to crEND().
-     crEND();
- }
-
- // An ISR that uses a queue to receive characters to send on a UART.
- void vUART_ISR( void )
- {
- char cCharToTx;
- portBASE_TYPE xCRWokenByPost = pdFALSE;
-
-     while( UART_TX_REG_EMPTY() )
-     {
-         // Are there any characters in the queue waiting to be sent?
-		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
-		 // is woken by the post - ensuring that only a single co-routine is
-		 // woken no matter how many times we go around this loop.
-         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
-		 {
-			 SEND_CHARACTER( cCharToTx );
-		 }
-     }
- }
- * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR - * \ingroup Tasks - */ -#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( pxQueue, pvBuffer, pxCoRoutineWoken ) - -/* - * This function is intended for internal use by the co-routine macros only. - * The macro nature of the co-routine implementation requires that the - * prototype appears here. The function should not be used by application - * writers. - * - * Removes the current co-routine from its ready list and places it in the - * appropriate delayed list. - */ -void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList ); - -/* - * This function is intended for internal use by the queue implementation only. - * The function should not be used by application writers. - * - * Removes the highest priority co-routine from the event list and places it in - * the pending ready list. - */ -signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList ); - -#ifdef __cplusplus -} -#endif - -#endif /* CO_ROUTINE_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/list.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/list.h deleted file mode 100644 index 759d8d320..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/list.h +++ /dev/null @@ -1,305 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -/* - * This is the list implementation used by the scheduler. While it is tailored - * heavily for the schedulers needs, it is also available for use by - * application code. - * - * xLists can only store pointers to xListItems. Each xListItem contains a - * numeric value (xItemValue). Most of the time the lists are sorted in - * descending item value order. - * - * Lists are created already containing one list item. The value of this - * item is the maximum possible that can be stored, it is therefore always at - * the end of the list and acts as a marker. The list member pxHead always - * points to this marker - even though it is at the tail of the list. This - * is because the tail contains a wrap back pointer to the true head of - * the list. - * - * In addition to it's value, each list item contains a pointer to the next - * item in the list (pxNext), a pointer to the list it is in (pxContainer) - * and a pointer to back to the object that contains it. These later two - * pointers are included for efficiency of list manipulation. There is - * effectively a two way link between the object containing the list item and - * the list item itself. - * - * - * \page ListIntroduction List Implementation - * \ingroup FreeRTOSIntro - */ - -/* - Changes from V4.3.1 - - + Included local const within listGET_OWNER_OF_NEXT_ENTRY() to assist - compiler with optimisation. Thanks B.R. -*/ - -#ifndef LIST_H -#define LIST_H - -#ifdef __cplusplus -extern "C" { -#endif -/* - * Definition of the only type of object that a list can contain. - */ -struct xLIST_ITEM -{ - portTickType xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ - volatile struct xLIST_ITEM * pxNext; /*< Pointer to the next xListItem in the list. */ - volatile struct xLIST_ITEM * pxPrevious;/*< Pointer to the previous xListItem in the list. */ - void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ - void * pvContainer; /*< Pointer to the list in which this list item is placed (if any). */ -}; -typedef struct xLIST_ITEM xListItem; /* For some reason lint wants this as two separate definitions. */ - -struct xMINI_LIST_ITEM -{ - portTickType xItemValue; - volatile struct xLIST_ITEM *pxNext; - volatile struct xLIST_ITEM *pxPrevious; -}; -typedef struct xMINI_LIST_ITEM xMiniListItem; - -/* - * Definition of the type of queue used by the scheduler. - */ -typedef struct xLIST -{ - volatile unsigned portBASE_TYPE uxNumberOfItems; - volatile xListItem * pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to pvListGetOwnerOfNextEntry (). */ - volatile xMiniListItem xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ -} xList; - -/* - * Access macro to set the owner of a list item. The owner of a list item - * is the object (usually a TCB) that contains the list item. - * - * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( pxListItem )->pvOwner = ( void * ) pxOwner - -/* - * Access macro to set the value of the list item. In most cases the value is - * used to sort the list in descending order. - * - * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( pxListItem )->xItemValue = xValue - -/* - * Access macro the retrieve the value of the list item. The value can - * represent anything - for example a the priority of a task, or the time at - * which a task should be unblocked. - * - * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) - -/* - * Access macro to determine if a list contains any items. The macro will - * only have the value true if the list is empty. - * - * \page listLIST_IS_EMPTY listLIST_IS_EMPTY - * \ingroup LinkedList - */ -#define listLIST_IS_EMPTY( pxList ) ( ( pxList )->uxNumberOfItems == ( unsigned portBASE_TYPE ) 0 ) - -/* - * Access macro to return the number of items in the list. - */ -#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) - -/* - * Access function to obtain the owner of the next entry in a list. - * - * The list member pxIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list - * and returns that entries pxOwner parameter. Using multiple calls to this - * function it is therefore possible to move through every item contained in - * a list. - * - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the next item owner is to be returned. - * - * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ -{ \ -xList * const pxConstList = pxList; \ - /* Increment the index to the next item and return the item, ensuring */ \ - /* we don't return the marker used at the end of the list. */ \ - ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ - if( ( pxConstList )->pxIndex == ( xListItem * ) &( ( pxConstList )->xListEnd ) ) \ - { \ - ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ - } \ - pxTCB = ( pxConstList )->pxIndex->pvOwner; \ -} - - -/* - * Access function to obtain the owner of the first entry in a list. Lists - * are normally sorted in ascending item value order. - * - * This function returns the pxOwner member of the first item in the list. - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the owner of the head item is to be - * returned. - * - * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( pxList->uxNumberOfItems != ( unsigned portBASE_TYPE ) 0 ) ? ( (&( pxList->xListEnd ))->pxNext->pvOwner ) : ( NULL ) ) - -/* - * Check to see if a list item is within a list. The list item maintains a - * "container" pointer that points to the list it is in. All this macro does - * is check to see if the container and the list match. - * - * @param pxList The list we want to know if the list item is within. - * @param pxListItem The list item we want to know if is in the list. - * @return pdTRUE is the list item is in the list, otherwise pdFALSE. - * pointer against - */ -#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( pxListItem )->pvContainer == ( void * ) pxList ) - -/* - * Must be called before a list is used! This initialises all the members - * of the list structure and inserts the xListEnd item into the list as a - * marker to the back of the list. - * - * @param pxList Pointer to the list being initialised. - * - * \page vListInitialise vListInitialise - * \ingroup LinkedList - */ -void vListInitialise( xList *pxList ); - -/* - * Must be called before a list item is used. This sets the list container to - * null so the item does not think that it is already contained in a list. - * - * @param pxItem Pointer to the list item being initialised. - * - * \page vListInitialiseItem vListInitialiseItem - * \ingroup LinkedList - */ -void vListInitialiseItem( xListItem *pxItem ); - -/* - * Insert a list item into a list. The item will be inserted into the list in - * a position determined by its item value (descending item value order). - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The item to that is to be placed in the list. - * - * \page vListInsert vListInsert - * \ingroup LinkedList - */ -void vListInsert( xList *pxList, xListItem *pxNewListItem ); - -/* - * Insert a list item into a list. The item will be inserted in a position - * such that it will be the last item within the list returned by multiple - * calls to listGET_OWNER_OF_NEXT_ENTRY. - * - * The list member pvIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list. - * Placing an item in a list using vListInsertEnd effectively places the item - * in the list position pointed to by pvIndex. This means that every other - * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before - * the pvIndex parameter again points to the item being inserted. - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The list item to be inserted into the list. - * - * \page vListInsertEnd vListInsertEnd - * \ingroup LinkedList - */ -void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ); - -/* - * Remove an item from a list. The list item has a pointer to the list that - * it is in, so only the list item need be passed into the function. - * - * @param vListRemove The item to be removed. The item will remove itself from - * the list pointed to by it's pxContainer parameter. - * - * \page vListRemove vListRemove - * \ingroup LinkedList - */ -void vListRemove( xListItem *pxItemToRemove ); - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/mpu_wrappers.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/mpu_wrappers.h deleted file mode 100644 index a64c41987..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/mpu_wrappers.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -#ifndef MPU_WRAPPERS_H -#define MPU_WRAPPERS_H - -/* This file redefines API functions to be called through a wrapper macro, but -only for ports that are using the MPU. */ -#ifdef portUSING_MPU_WRAPPERS - - /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is - included from queue.c or task.c to prevent it from having an effict within - those files. */ - #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE - - #define xTaskGenericCreate MPU_xTaskGenericCreate - #define vTaskAllocateMPURegions MPU_vTaskAllocateMPURegions - #define vTaskDelete MPU_vTaskDelete - #define vTaskDelayUntil MPU_vTaskDelayUntil - #define vTaskDelay MPU_vTaskDelay - #define uxTaskPriorityGet MPU_uxTaskPriorityGet - #define vTaskPrioritySet MPU_vTaskPrioritySet - #define vTaskSuspend MPU_vTaskSuspend - #define xTaskIsTaskSuspended MPU_xTaskIsTaskSuspended - #define vTaskResume MPU_vTaskResume - #define vTaskSuspendAll MPU_vTaskSuspendAll - #define xTaskResumeAll MPU_xTaskResumeAll - #define xTaskGetTickCount MPU_xTaskGetTickCount - #define uxTaskGetNumberOfTasks MPU_uxTaskGetNumberOfTasks - #define vTaskList MPU_vTaskList - #define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats - #define vTaskStartTrace MPU_vTaskStartTrace - #define ulTaskEndTrace MPU_ulTaskEndTrace - #define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag - #define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag - #define xTaskCallApplicationTaskHook MPU_xTaskCallApplicationTaskHook - #define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark - #define xTaskGetCurrentTaskHandle MPU_xTaskGetCurrentTaskHandle - #define xTaskGetSchedulerState MPU_xTaskGetSchedulerState - - #define xQueueCreate MPU_xQueueCreate - #define xQueueCreateMutex MPU_xQueueCreateMutex - #define xQueueGiveMutexRecursive MPU_xQueueGiveMutexRecursive - #define xQueueTakeMutexRecursive MPU_xQueueTakeMutexRecursive - #define xQueueCreateCountingSemaphore MPU_xQueueCreateCountingSemaphore - #define xQueueGenericSend MPU_xQueueGenericSend - #define xQueueAltGenericSend MPU_xQueueAltGenericSend - #define xQueueAltGenericReceive MPU_xQueueAltGenericReceive - #define xQueueGenericReceive MPU_xQueueGenericReceive - #define uxQueueMessagesWaiting MPU_uxQueueMessagesWaiting - #define vQueueDelete MPU_vQueueDelete - - #define pvPortMalloc MPU_pvPortMalloc - #define vPortFree MPU_vPortFree - #define xPortGetFreeHeapSize MPU_xPortGetFreeHeapSize - #define vPortInitialiseBlocks MPU_vPortInitialiseBlocks - - #if configQUEUE_REGISTRY_SIZE > 0 - #define vQueueAddToRegistry MPU_vQueueAddToRegistry - #define vQueueUnregisterQueue MPU_vQueueUnregisterQueue - #endif - - /* Remove the privileged function macro. */ - #define PRIVILEGED_FUNCTION - - #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ - - /* Ensure API functions go in the privileged execution section. */ - #define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions"))) - #define PRIVILEGED_DATA __attribute__((section("privileged_data"))) - //#define PRIVILEGED_DATA - - #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ - -#else /* portUSING_MPU_WRAPPERS */ - - #define PRIVILEGED_FUNCTION - #define PRIVILEGED_DATA - #define portUSING_MPU_WRAPPERS 0 - -#endif /* portUSING_MPU_WRAPPERS */ - - -#endif /* MPU_WRAPPERS_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/portable.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/portable.h deleted file mode 100644 index eef3d355c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/portable.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -/*----------------------------------------------------------- - * Portable layer API. Each function must be defined for each port. - *----------------------------------------------------------*/ - -#ifndef PORTABLE_H -#define PORTABLE_H - -/* Include the macro file relevant to the port being used. */ - -#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT - #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT - #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef GCC_MEGA_AVR - #include "../portable/GCC/ATMega323/portmacro.h" -#endif - -#ifdef IAR_MEGA_AVR - #include "../portable/IAR/ATMega323/portmacro.h" -#endif - -#ifdef MPLAB_PIC24_PORT - #include "..\..\Source\portable\MPLAB\PIC24_dsPIC\portmacro.h" -#endif - -#ifdef MPLAB_DSPIC_PORT - #include "..\..\Source\portable\MPLAB\PIC24_dsPIC\portmacro.h" -#endif - -#ifdef MPLAB_PIC18F_PORT - #include "..\..\Source\portable\MPLAB\PIC18F\portmacro.h" -#endif - -#ifdef MPLAB_PIC32MX_PORT - #include "..\..\Source\portable\MPLAB\PIC32MX\portmacro.h" -#endif - -#ifdef _FEDPICC - #include "libFreeRTOS/Include/portmacro.h" -#endif - -#ifdef SDCC_CYGNAL - #include "../../Source/portable/SDCC/Cygnal/portmacro.h" -#endif - -#ifdef GCC_ARM7 - #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" -#endif - -#ifdef GCC_ARM7_ECLIPSE - #include "portmacro.h" -#endif - -#ifdef ROWLEY_LPC23xx - #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" -#endif - -#ifdef IAR_MSP430 - #include "..\..\Source\portable\IAR\MSP430\portmacro.h" -#endif - -#ifdef GCC_MSP430 - #include "../../Source/portable/GCC/MSP430F449/portmacro.h" -#endif - -#ifdef ROWLEY_MSP430 - #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" -#endif - -#ifdef ARM7_LPC21xx_KEIL_RVDS - #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h" -#endif - -#ifdef SAM7_GCC - #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" -#endif - -#ifdef SAM7_IAR - #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" -#endif - -#ifdef SAM9XE_IAR - #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h" -#endif - -#ifdef LPC2000_IAR - #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" -#endif - -#ifdef STR71X_IAR - #include "..\..\Source\portable\IAR\STR71x\portmacro.h" -#endif - -#ifdef STR75X_IAR - #include "..\..\Source\portable\IAR\STR75x\portmacro.h" -#endif - -#ifdef STR75X_GCC - #include "..\..\Source\portable\GCC\STR75x\portmacro.h" -#endif - -#ifdef STR91X_IAR - #include "..\..\Source\portable\IAR\STR91x\portmacro.h" -#endif - -#ifdef GCC_H8S - #include "../../Source/portable/GCC/H8S2329/portmacro.h" -#endif - -#ifdef GCC_AT91FR40008 - #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" -#endif - -#ifdef RVDS_ARMCM3_LM3S102 - #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" -#endif - -#ifdef GCC_ARMCM3_LM3S102 - #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" -#endif - -#ifdef GCC_ARMCM3 - #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" -#endif - -#ifdef IAR_ARM_CM3 - #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" -#endif - -#ifdef IAR_ARMCM3_LM - #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" -#endif - -#ifdef HCS12_CODE_WARRIOR - #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" -#endif - -#ifdef MICROBLAZE_GCC - #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" -#endif - -#ifdef TERN_EE - #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" -#endif - -#ifdef GCC_HCS12 - #include "../../Source/portable/GCC/HCS12/portmacro.h" -#endif - -#ifdef GCC_MCF5235 - #include "../../Source/portable/GCC/MCF5235/portmacro.h" -#endif - -#ifdef COLDFIRE_V2_GCC - #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h" -#endif - -#ifdef COLDFIRE_V2_CODEWARRIOR - #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h" -#endif - -#ifdef GCC_PPC405 - #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h" -#endif - -#ifdef GCC_PPC440 - #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h" -#endif - -#ifdef _16FX_SOFTUNE - #include "..\..\Source\portable\Softune\MB96340\portmacro.h" -#endif - -#ifdef BCC_INDUSTRIAL_PC_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef BCC_FLASH_LITE_186_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef __GNUC__ - #ifdef __AVR32_AVR32A__ - #include "portmacro.h" - #endif -#endif - -#ifdef __ICCAVR32__ - #ifdef __CORE__ - #if __CORE__ == __AVR32A__ - #include "portmacro.h" - #endif - #endif -#endif - -#ifdef __91467D - #include "portmacro.h" -#endif - -#ifdef __96340 - #include "portmacro.h" -#endif - - -#ifdef __IAR_V850ES_Fx3__ - #include "../../Source/portable/IAR/V850ES/portmacro.h" -#endif - -#ifdef __IAR_V850ES_Jx3__ - #include "../../Source/portable/IAR/V850ES/portmacro.h" -#endif - -#ifdef __IAR_V850ES_Jx3_L__ - #include "../../Source/portable/IAR/V850ES/portmacro.h" -#endif - -#ifdef __IAR_V850ES_Jx2__ - #include "../../Source/portable/IAR/V850ES/portmacro.h" -#endif - -#ifdef __IAR_V850ES_Hx2__ - #include "../../Source/portable/IAR/V850ES/portmacro.h" -#endif - -#ifdef __IAR_78K0R_Kx3__ - #include "../../Source/portable/IAR/78K0R/portmacro.h" -#endif - -#ifdef __IAR_78K0R_Kx3L__ - #include "../../Source/portable/IAR/78K0R/portmacro.h" -#endif - -/* Catch all to ensure portmacro.h is included in the build. Newer demos -have the path as part of the project options, rather than as relative from -the project location. If portENTER_CRITICAL() has not been defined then -portmacro.h has not yet been included - as every portmacro.h provides a -portENTER_CRITICAL() definition. Check the demo application for your demo -to find the path to the correct portmacro.h file. */ -#ifndef portENTER_CRITICAL - #include "portmacro.h" -#endif - -#if portBYTE_ALIGNMENT == 8 - #define portBYTE_ALIGNMENT_MASK ( 0x0007 ) -#endif - -#if portBYTE_ALIGNMENT == 4 - #define portBYTE_ALIGNMENT_MASK ( 0x0003 ) -#endif - -#if portBYTE_ALIGNMENT == 2 - #define portBYTE_ALIGNMENT_MASK ( 0x0001 ) -#endif - -#if portBYTE_ALIGNMENT == 1 - #define portBYTE_ALIGNMENT_MASK ( 0x0000 ) -#endif - -#ifndef portBYTE_ALIGNMENT_MASK - #error "Invalid portBYTE_ALIGNMENT definition" -#endif - -#ifndef portNUM_CONFIGURABLE_REGIONS - #define portNUM_CONFIGURABLE_REGIONS 1 -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#include "mpu_wrappers.h" - -/* - * Setup the stack of a new task so it is ready to be placed under the - * scheduler control. The registers have to be placed on the stack in - * the order that the port expects to find them. - * - */ -#if( portUSING_MPU_WRAPPERS == 1 ) - portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters, portBASE_TYPE xRunPrivileged ) PRIVILEGED_FUNCTION; -#else - portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ); -#endif - -/* - * Map to the memory management routines required for the port. - */ -void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION; -void vPortFree( void *pv ) PRIVILEGED_FUNCTION; -void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION; -size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION; - -/* - * Setup the hardware ready for the scheduler to take control. This generally - * sets up a tick interrupt and sets timers for the correct tick frequency. - */ -portBASE_TYPE xPortStartScheduler( void ) PRIVILEGED_FUNCTION; - -/* - * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so - * the hardware is left in its original condition after the scheduler stops - * executing. - */ -void vPortEndScheduler( void ) PRIVILEGED_FUNCTION; - -/* - * The structures and methods of manipulating the MPU are contained within the - * port layer. - * - * Fills the xMPUSettings structure with the memory region information - * contained in xRegions. - */ -#if( portUSING_MPU_WRAPPERS == 1 ) - struct xMEMORY_REGION; - void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, portSTACK_TYPE *pxBottomOfStack, unsigned short usStackDepth ) PRIVILEGED_FUNCTION; -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* PORTABLE_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/projdefs.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/projdefs.h deleted file mode 100644 index c5539d9e9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/projdefs.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -#ifndef PROJDEFS_H -#define PROJDEFS_H - -/* Defines the prototype to which task functions must conform. */ -typedef void (*pdTASK_CODE)( void * ); - -#define pdTRUE ( 1 ) -#define pdFALSE ( 0 ) - -#define pdPASS ( 1 ) -#define pdFAIL ( 0 ) -#define errQUEUE_EMPTY ( 0 ) -#define errQUEUE_FULL ( 0 ) - -/* Error definitions. */ -#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 ) -#define errNO_TASK_TO_RUN ( -2 ) -#define errQUEUE_BLOCKED ( -4 ) -#define errQUEUE_YIELD ( -5 ) - -#endif /* PROJDEFS_H */ - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/queue.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/queue.h deleted file mode 100644 index 992bff367..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/queue.h +++ /dev/null @@ -1,1261 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -#ifndef INC_FREERTOS_H - #error "#include FreeRTOS.h" must appear in source files before "#include queue.h" -#endif - - - - -#ifndef QUEUE_H -#define QUEUE_H - -#ifdef __cplusplus -extern "C" { -#endif - - -#include "mpu_wrappers.h" - - -typedef void * xQueueHandle; - - -/* For internal use only. */ -#define queueSEND_TO_BACK ( 0 ) -#define queueSEND_TO_FRONT ( 1 ) - - -/** - * queue. h - *
- xQueueHandle xQueueCreate(
-							  unsigned portBASE_TYPE uxQueueLength,
-							  unsigned portBASE_TYPE uxItemSize
-						  );
- * 
- * - * Creates a new queue instance. This allocates the storage required by the - * new queue and returns a handle for the queue. - * - * @param uxQueueLength The maximum number of items that the queue can contain. - * - * @param uxItemSize The number of bytes each item in the queue will require. - * Items are queued by copy, not by reference, so this is the number of bytes - * that will be copied for each posted item. Each item on the queue must be - * the same size. - * - * @return If the queue is successfully create then a handle to the newly - * created queue is returned. If the queue cannot be created then 0 is - * returned. - * - * Example usage: -
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- };
-
- void vATask( void *pvParameters )
- {
- xQueueHandle xQueue1, xQueue2;
-
-	// Create a queue capable of containing 10 unsigned long values.
-	xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) );
-	if( xQueue1 == 0 )
-	{
-		// Queue was not created and must not be used.
-	}
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-	if( xQueue2 == 0 )
-	{
-		// Queue was not created and must not be used.
-	}
-
-	// ... Rest of task code.
- }
- 
- * \defgroup xQueueCreate xQueueCreate - * \ingroup QueueManagement - */ -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); - -/** - * queue. h - *
- portBASE_TYPE xQueueSendToToFront(
-								   xQueueHandle	xQueue,
-								   const	void	*	pvItemToQueue,
-								   portTickType	xTicksToWait
-							   );
- * 
- * - * This is a macro that calls xQueueGenericSend(). - * - * Post an item to the front of a queue. The item is queued by copy, not by - * reference. This function must not be called from an interrupt service - * routine. See xQueueSendFromISR () for an alternative which may be used - * in an ISR. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for space to become available on the queue, should it already - * be full. The call will return immediately if this is set to 0 and the - * queue is full. The time is defined in tick periods so the constant - * portTICK_RATE_MS should be used to convert to real time if this is required. - * - * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. - * - * Example usage: -
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- unsigned long ulVar = 10UL;
-
- void vATask( void *pvParameters )
- {
- xQueueHandle xQueue1, xQueue2;
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 unsigned long values.
-	xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) );
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-
-	// ...
-
-	if( xQueue1 != 0 )
-	{
-		// Send an unsigned long.  Wait for 10 ticks for space to become
-		// available if necessary.
-		if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )
-		{
-			// Failed to post the message, even after 10 ticks.
-		}
-	}
-
-	if( xQueue2 != 0 )
-	{
-		// Send a pointer to a struct AMessage object.  Don't block if the
-		// queue is already full.
-		pxMessage = & xMessage;
-		xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );
-	}
-
-	// ... Rest of task code.
- }
- 
- * \defgroup xQueueSend xQueueSend - * \ingroup QueueManagement - */ -#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, queueSEND_TO_FRONT ) - -/** - * queue. h - *
- portBASE_TYPE xQueueSendToBack(
-								   xQueueHandle	xQueue,
-								   const	void	*	pvItemToQueue,
-								   portTickType	xTicksToWait
-							   );
- * 
- * - * This is a macro that calls xQueueGenericSend(). - * - * Post an item to the back of a queue. The item is queued by copy, not by - * reference. This function must not be called from an interrupt service - * routine. See xQueueSendFromISR () for an alternative which may be used - * in an ISR. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for space to become available on the queue, should it already - * be full. The call will return immediately if this is set to 0 and the queue - * is full. The time is defined in tick periods so the constant - * portTICK_RATE_MS should be used to convert to real time if this is required. - * - * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. - * - * Example usage: -
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- unsigned long ulVar = 10UL;
-
- void vATask( void *pvParameters )
- {
- xQueueHandle xQueue1, xQueue2;
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 unsigned long values.
-	xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) );
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-
-	// ...
-
-	if( xQueue1 != 0 )
-	{
-		// Send an unsigned long.  Wait for 10 ticks for space to become
-		// available if necessary.
-		if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )
-		{
-			// Failed to post the message, even after 10 ticks.
-		}
-	}
-
-	if( xQueue2 != 0 )
-	{
-		// Send a pointer to a struct AMessage object.  Don't block if the
-		// queue is already full.
-		pxMessage = & xMessage;
-		xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );
-	}
-
-	// ... Rest of task code.
- }
- 
- * \defgroup xQueueSend xQueueSend - * \ingroup QueueManagement - */ -#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, queueSEND_TO_BACK ) - -/** - * queue. h - *
- portBASE_TYPE xQueueSend(
-							  xQueueHandle xQueue,
-							  const void * pvItemToQueue,
-							  portTickType xTicksToWait
-						 );
- * 
- * - * This is a macro that calls xQueueGenericSend(). It is included for - * backward compatibility with versions of FreeRTOS.org that did not - * include the xQueueSendToFront() and xQueueSendToBack() macros. It is - * equivalent to xQueueSendToBack(). - * - * Post an item on a queue. The item is queued by copy, not by reference. - * This function must not be called from an interrupt service routine. - * See xQueueSendFromISR () for an alternative which may be used in an ISR. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for space to become available on the queue, should it already - * be full. The call will return immediately if this is set to 0 and the - * queue is full. The time is defined in tick periods so the constant - * portTICK_RATE_MS should be used to convert to real time if this is required. - * - * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. - * - * Example usage: -
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- unsigned long ulVar = 10UL;
-
- void vATask( void *pvParameters )
- {
- xQueueHandle xQueue1, xQueue2;
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 unsigned long values.
-	xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) );
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-
-	// ...
-
-	if( xQueue1 != 0 )
-	{
-		// Send an unsigned long.  Wait for 10 ticks for space to become
-		// available if necessary.
-		if( xQueueSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )
-		{
-			// Failed to post the message, even after 10 ticks.
-		}
-	}
-
-	if( xQueue2 != 0 )
-	{
-		// Send a pointer to a struct AMessage object.  Don't block if the
-		// queue is already full.
-		pxMessage = & xMessage;
-		xQueueSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );
-	}
-
-	// ... Rest of task code.
- }
- 
- * \defgroup xQueueSend xQueueSend - * \ingroup QueueManagement - */ -#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, queueSEND_TO_BACK ) - - -/** - * queue. h - *
- portBASE_TYPE xQueueGenericSend(
-									xQueueHandle xQueue,
-									const void * pvItemToQueue,
-									portTickType xTicksToWait
-									portBASE_TYPE xCopyPosition
-								);
- * 
- * - * It is preferred that the macros xQueueSend(), xQueueSendToFront() and - * xQueueSendToBack() are used in place of calling this function directly. - * - * Post an item on a queue. The item is queued by copy, not by reference. - * This function must not be called from an interrupt service routine. - * See xQueueSendFromISR () for an alternative which may be used in an ISR. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for space to become available on the queue, should it already - * be full. The call will return immediately if this is set to 0 and the - * queue is full. The time is defined in tick periods so the constant - * portTICK_RATE_MS should be used to convert to real time if this is required. - * - * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the - * item at the back of the queue, or queueSEND_TO_FRONT to place the item - * at the front of the queue (for high priority messages). - * - * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. - * - * Example usage: -
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- unsigned long ulVar = 10UL;
-
- void vATask( void *pvParameters )
- {
- xQueueHandle xQueue1, xQueue2;
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 unsigned long values.
-	xQueue1 = xQueueCreate( 10, sizeof( unsigned long ) );
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-
-	// ...
-
-	if( xQueue1 != 0 )
-	{
-		// Send an unsigned long.  Wait for 10 ticks for space to become
-		// available if necessary.
-		if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10, queueSEND_TO_BACK ) != pdPASS )
-		{
-			// Failed to post the message, even after 10 ticks.
-		}
-	}
-
-	if( xQueue2 != 0 )
-	{
-		// Send a pointer to a struct AMessage object.  Don't block if the
-		// queue is already full.
-		pxMessage = & xMessage;
-		xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0, queueSEND_TO_BACK );
-	}
-
-	// ... Rest of task code.
- }
- 
- * \defgroup xQueueSend xQueueSend - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ); - -/** - * queue. h - *
- portBASE_TYPE xQueuePeek(
-							 xQueueHandle xQueue,
-							 void *pvBuffer,
-							 portTickType xTicksToWait
-						 );
- * - * This is a macro that calls the xQueueGenericReceive() function. - * - * Receive an item from a queue without removing the item from the queue. - * The item is received by copy so a buffer of adequate size must be - * provided. The number of bytes copied into the buffer was defined when - * the queue was created. - * - * Successfully received items remain on the queue so will be returned again - * by the next call, or a call to xQueueReceive(). - * - * This macro must not be used in an interrupt service routine. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pvBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for an item to receive should the queue be empty at the time - * of the call. The time is defined in tick periods so the constant - * portTICK_RATE_MS should be used to convert to real time if this is required. - * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue - * is empty. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: -
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- xQueueHandle xQueue;
-
- // Task to create a queue and post a value.
- void vATask( void *pvParameters )
- {
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
-	if( xQueue == 0 )
-	{
-		// Failed to create the queue.
-	}
-
-	// ...
-
-	// Send a pointer to a struct AMessage object.  Don't block if the
-	// queue is already full.
-	pxMessage = & xMessage;
-	xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );
-
-	// ... Rest of task code.
- }
-
- // Task to peek the data from the queue.
- void vADifferentTask( void *pvParameters )
- {
- struct AMessage *pxRxedMessage;
-
-	if( xQueue != 0 )
-	{
-		// Peek a message on the created queue.  Block for 10 ticks if a
-		// message is not immediately available.
-		if( xQueuePeek( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )
-		{
-			// pcRxedMessage now points to the struct AMessage variable posted
-			// by vATask, but the item still remains on the queue.
-		}
-	}
-
-	// ... Rest of task code.
- }
- 
- * \defgroup xQueueReceive xQueueReceive - * \ingroup QueueManagement - */ -#define xQueuePeek( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( xQueue, pvBuffer, xTicksToWait, pdTRUE ) - -/** - * queue. h - *
- portBASE_TYPE xQueueReceive(
-								 xQueueHandle xQueue,
-								 void *pvBuffer,
-								 portTickType xTicksToWait
-							);
- * - * This is a macro that calls the xQueueGenericReceive() function. - * - * Receive an item from a queue. The item is received by copy so a buffer of - * adequate size must be provided. The number of bytes copied into the buffer - * was defined when the queue was created. - * - * Successfully received items are removed from the queue. - * - * This function must not be used in an interrupt service routine. See - * xQueueReceiveFromISR for an alternative that can. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pvBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for an item to receive should the queue be empty at the time - * of the call. xQueueReceive() will return immediately if xTicksToWait - * is zero and the queue is empty. The time is defined in tick periods so the - * constant portTICK_RATE_MS should be used to convert to real time if this is - * required. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: -
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- xQueueHandle xQueue;
-
- // Task to create a queue and post a value.
- void vATask( void *pvParameters )
- {
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
-	if( xQueue == 0 )
-	{
-		// Failed to create the queue.
-	}
-
-	// ...
-
-	// Send a pointer to a struct AMessage object.  Don't block if the
-	// queue is already full.
-	pxMessage = & xMessage;
-	xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );
-
-	// ... Rest of task code.
- }
-
- // Task to receive from the queue.
- void vADifferentTask( void *pvParameters )
- {
- struct AMessage *pxRxedMessage;
-
-	if( xQueue != 0 )
-	{
-		// Receive a message on the created queue.  Block for 10 ticks if a
-		// message is not immediately available.
-		if( xQueueReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )
-		{
-			// pcRxedMessage now points to the struct AMessage variable posted
-			// by vATask.
-		}
-	}
-
-	// ... Rest of task code.
- }
- 
- * \defgroup xQueueReceive xQueueReceive - * \ingroup QueueManagement - */ -#define xQueueReceive( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( xQueue, pvBuffer, xTicksToWait, pdFALSE ) - - -/** - * queue. h - *
- portBASE_TYPE xQueueGenericReceive(
-									   xQueueHandle	xQueue,
-									   void	*pvBuffer,
-									   portTickType	xTicksToWait
-									   portBASE_TYPE	xJustPeek
-									);
- * - * It is preferred that the macro xQueueReceive() be used rather than calling - * this function directly. - * - * Receive an item from a queue. The item is received by copy so a buffer of - * adequate size must be provided. The number of bytes copied into the buffer - * was defined when the queue was created. - * - * This function must not be used in an interrupt service routine. See - * xQueueReceiveFromISR for an alternative that can. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pvBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for an item to receive should the queue be empty at the time - * of the call. The time is defined in tick periods so the constant - * portTICK_RATE_MS should be used to convert to real time if this is required. - * xQueueGenericReceive() will return immediately if the queue is empty and - * xTicksToWait is 0. - * - * @param xJustPeek When set to true, the item received from the queue is not - * actually removed from the queue - meaning a subsequent call to - * xQueueReceive() will return the same item. When set to false, the item - * being received from the queue is also removed from the queue. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: -
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- xQueueHandle xQueue;
-
- // Task to create a queue and post a value.
- void vATask( void *pvParameters )
- {
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
-	if( xQueue == 0 )
-	{
-		// Failed to create the queue.
-	}
-
-	// ...
-
-	// Send a pointer to a struct AMessage object.  Don't block if the
-	// queue is already full.
-	pxMessage = & xMessage;
-	xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );
-
-	// ... Rest of task code.
- }
-
- // Task to receive from the queue.
- void vADifferentTask( void *pvParameters )
- {
- struct AMessage *pxRxedMessage;
-
-	if( xQueue != 0 )
-	{
-		// Receive a message on the created queue.  Block for 10 ticks if a
-		// message is not immediately available.
-		if( xQueueGenericReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )
-		{
-			// pcRxedMessage now points to the struct AMessage variable posted
-			// by vATask.
-		}
-	}
-
-	// ... Rest of task code.
- }
- 
- * \defgroup xQueueReceive xQueueReceive - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueGenericReceive( xQueueHandle xQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeek ); - -/** - * queue. h - *
unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle xQueue );
- * - * Return the number of messages stored in a queue. - * - * @param xQueue A handle to the queue being queried. - * - * @return The number of messages available in the queue. - * - * \page uxQueueMessagesWaiting uxQueueMessagesWaiting - * \ingroup QueueManagement - */ -unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle xQueue ); - -/** - * queue. h - *
void vQueueDelete( xQueueHandle xQueue );
- * - * Delete a queue - freeing all the memory allocated for storing of items - * placed on the queue. - * - * @param xQueue A handle to the queue to be deleted. - * - * \page vQueueDelete vQueueDelete - * \ingroup QueueManagement - */ -void vQueueDelete( xQueueHandle xQueue ); - -/** - * queue. h - *
- portBASE_TYPE xQueueSendToFrontFromISR(
-										 xQueueHandle pxQueue,
-										 const void *pvItemToQueue,
-										 portBASE_TYPE *pxHigherPriorityTaskWoken
-									  );
- 
- * - * This is a macro that calls xQueueGenericSendFromISR(). - * - * Post an item to the front of a queue. It is safe to use this macro from - * within an interrupt service routine. - * - * Items are queued by copy not reference so it is preferable to only - * queue small items, especially when called from an ISR. In most cases - * it would be preferable to store a pointer to the item being queued. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set - * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task - * to unblock, and the unblocked task has a priority higher than the currently - * running task. If xQueueSendToFromFromISR() sets this value to pdTRUE then - * a context switch should be requested before the interrupt is exited. - * - * @return pdTRUE if the data was successfully sent to the queue, otherwise - * errQUEUE_FULL. - * - * Example usage for buffered IO (where the ISR can obtain more than one value - * per call): -
- void vBufferISR( void )
- {
- char cIn;
- portBASE_TYPE xHigherPrioritTaskWoken;
-
-	// We have not woken a task at the start of the ISR.
-	xHigherPriorityTaskWoken = pdFALSE;
-
-	// Loop until the buffer is empty.
-	do
-	{
-		// Obtain a byte from the buffer.
-		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
-
-		// Post the byte.
-		xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
-
-	} while( portINPUT_BYTE( BUFFER_COUNT ) );
-
-	// Now the buffer is empty we can switch context if necessary.
-	if( xHigherPriorityTaskWoken )
-	{
-		taskYIELD ();
-	}
- }
- 
- * - * \defgroup xQueueSendFromISR xQueueSendFromISR - * \ingroup QueueManagement - */ -#define xQueueSendToFrontFromISR( pxQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( pxQueue, pvItemToQueue, pxHigherPriorityTaskWoken, queueSEND_TO_FRONT ) - - -/** - * queue. h - *
- portBASE_TYPE xQueueSendToBackFromISR(
-										 xQueueHandle pxQueue,
-										 const void *pvItemToQueue,
-										 portBASE_TYPE *pxHigherPriorityTaskWoken
-									  );
- 
- * - * This is a macro that calls xQueueGenericSendFromISR(). - * - * Post an item to the back of a queue. It is safe to use this macro from - * within an interrupt service routine. - * - * Items are queued by copy not reference so it is preferable to only - * queue small items, especially when called from an ISR. In most cases - * it would be preferable to store a pointer to the item being queued. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set - * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task - * to unblock, and the unblocked task has a priority higher than the currently - * running task. If xQueueSendToBackFromISR() sets this value to pdTRUE then - * a context switch should be requested before the interrupt is exited. - * - * @return pdTRUE if the data was successfully sent to the queue, otherwise - * errQUEUE_FULL. - * - * Example usage for buffered IO (where the ISR can obtain more than one value - * per call): -
- void vBufferISR( void )
- {
- char cIn;
- portBASE_TYPE xHigherPriorityTaskWoken;
-
-	// We have not woken a task at the start of the ISR.
-	xHigherPriorityTaskWoken = pdFALSE;
-
-	// Loop until the buffer is empty.
-	do
-	{
-		// Obtain a byte from the buffer.
-		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
-
-		// Post the byte.
-		xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
-
-	} while( portINPUT_BYTE( BUFFER_COUNT ) );
-
-	// Now the buffer is empty we can switch context if necessary.
-	if( xHigherPriorityTaskWoken )
-	{
-		taskYIELD ();
-	}
- }
- 
- * - * \defgroup xQueueSendFromISR xQueueSendFromISR - * \ingroup QueueManagement - */ -#define xQueueSendToBackFromISR( pxQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( pxQueue, pvItemToQueue, pxHigherPriorityTaskWoken, queueSEND_TO_BACK ) - -/** - * queue. h - *
- portBASE_TYPE xQueueSendFromISR(
-									 xQueueHandle pxQueue,
-									 const void *pvItemToQueue,
-									 portBASE_TYPE *pxHigherPriorityTaskWoken
-								);
- 
- * - * This is a macro that calls xQueueGenericSendFromISR(). It is included - * for backward compatibility with versions of FreeRTOS.org that did not - * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR() - * macros. - * - * Post an item to the back of a queue. It is safe to use this function from - * within an interrupt service routine. - * - * Items are queued by copy not reference so it is preferable to only - * queue small items, especially when called from an ISR. In most cases - * it would be preferable to store a pointer to the item being queued. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set - * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task - * to unblock, and the unblocked task has a priority higher than the currently - * running task. If xQueueSendFromISR() sets this value to pdTRUE then - * a context switch should be requested before the interrupt is exited. - * - * @return pdTRUE if the data was successfully sent to the queue, otherwise - * errQUEUE_FULL. - * - * Example usage for buffered IO (where the ISR can obtain more than one value - * per call): -
- void vBufferISR( void )
- {
- char cIn;
- portBASE_TYPE xHigherPriorityTaskWoken;
-
-	// We have not woken a task at the start of the ISR.
-	xHigherPriorityTaskWoken = pdFALSE;
-
-	// Loop until the buffer is empty.
-	do
-	{
-		// Obtain a byte from the buffer.
-		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
-
-		// Post the byte.
-		xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
-
-	} while( portINPUT_BYTE( BUFFER_COUNT ) );
-
-	// Now the buffer is empty we can switch context if necessary.
-	if( xHigherPriorityTaskWoken )
-	{
-		// Actual macro used here is port specific.
-		taskYIELD_FROM_ISR ();
-	}
- }
- 
- * - * \defgroup xQueueSendFromISR xQueueSendFromISR - * \ingroup QueueManagement - */ -#define xQueueSendFromISR( pxQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( pxQueue, pvItemToQueue, pxHigherPriorityTaskWoken, queueSEND_TO_BACK ) - -/** - * queue. h - *
- portBASE_TYPE xQueueGenericSendFromISR(
-										   xQueueHandle	pxQueue,
-										   const	void	*pvItemToQueue,
-										   portBASE_TYPE	*pxHigherPriorityTaskWoken,
-										   portBASE_TYPE	xCopyPosition
-									   );
- 
- * - * It is preferred that the macros xQueueSendFromISR(), - * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place - * of calling this function directly. - * - * Post an item on a queue. It is safe to use this function from within an - * interrupt service routine. - * - * Items are queued by copy not reference so it is preferable to only - * queue small items, especially when called from an ISR. In most cases - * it would be preferable to store a pointer to the item being queued. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set - * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task - * to unblock, and the unblocked task has a priority higher than the currently - * running task. If xQueueGenericSendFromISR() sets this value to pdTRUE then - * a context switch should be requested before the interrupt is exited. - * - * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the - * item at the back of the queue, or queueSEND_TO_FRONT to place the item - * at the front of the queue (for high priority messages). - * - * @return pdTRUE if the data was successfully sent to the queue, otherwise - * errQUEUE_FULL. - * - * Example usage for buffered IO (where the ISR can obtain more than one value - * per call): -
- void vBufferISR( void )
- {
- char cIn;
- portBASE_TYPE xHigherPriorityTaskWokenByPost;
-
-	// We have not woken a task at the start of the ISR.
-	xHigherPriorityTaskWokenByPost = pdFALSE;
-
-	// Loop until the buffer is empty.
-	do
-	{
-		// Obtain a byte from the buffer.
-		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
-
-		// Post each byte.
-		xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
-
-	} while( portINPUT_BYTE( BUFFER_COUNT ) );
-
-	// Now the buffer is empty we can switch context if necessary.  Note that the
-	// name of the yield function required is port specific.
-	if( xHigherPriorityTaskWokenByPost )
-	{
-		taskYIELD_YIELD_FROM_ISR();
-	}
- }
- 
- * - * \defgroup xQueueSendFromISR xQueueSendFromISR - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueGenericSendFromISR( xQueueHandle pxQueue, const void * const pvItemToQueue, signed portBASE_TYPE *pxHigherPriorityTaskWoken, portBASE_TYPE xCopyPosition ); - -/** - * queue. h - *
- portBASE_TYPE xQueueReceiveFromISR(
-									   xQueueHandle	pxQueue,
-									   void	*pvBuffer,
-									   portBASE_TYPE	*pxTaskWoken
-								   );
- * 
- * - * Receive an item from a queue. It is safe to use this function from within an - * interrupt service routine. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pvBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param pxTaskWoken A task may be blocked waiting for space to become - * available on the queue. If xQueueReceiveFromISR causes such a task to - * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will - * remain unchanged. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: -
-
- xQueueHandle xQueue;
-
- // Function to create a queue and post some values.
- void vAFunction( void *pvParameters )
- {
- char cValueToPost;
- const portTickType xBlockTime = ( portTickType )0xff;
-
-	// Create a queue capable of containing 10 characters.
-	xQueue = xQueueCreate( 10, sizeof( char ) );
-	if( xQueue == 0 )
-	{
-		// Failed to create the queue.
-	}
-
-	// ...
-
-	// Post some characters that will be used within an ISR.  If the queue
-	// is full then this task will block for xBlockTime ticks.
-	cValueToPost = 'a';
-	xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
-	cValueToPost = 'b';
-	xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
-
-	// ... keep posting characters ... this task may block when the queue
-	// becomes full.
-
-	cValueToPost = 'c';
-	xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
- }
-
- // ISR that outputs all the characters received on the queue.
- void vISR_Routine( void )
- {
- portBASE_TYPE xTaskWokenByReceive = pdFALSE;
- char cRxedChar;
-
-	while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
-	{
-		// A character was received.  Output the character now.
-		vOutputCharacter( cRxedChar );
-
-		// If removing the character from the queue woke the task that was
-		// posting onto the queue cTaskWokenByReceive will have been set to
-		// pdTRUE.  No matter how many times this loop iterates only one
-		// task will be woken.
-	}
-
-	if( cTaskWokenByPost != ( char ) pdFALSE;
-	{
-		taskYIELD ();
-	}
- }
- 
- * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void * const pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - -/* - * Utilities to query queue that are safe to use from an ISR. These utilities - * should be used only from witin an ISR, or within a critical section. - */ -signed portBASE_TYPE xQueueIsQueueEmptyFromISR( const xQueueHandle pxQueue ); -signed portBASE_TYPE xQueueIsQueueFullFromISR( const xQueueHandle pxQueue ); -unsigned portBASE_TYPE uxQueueMessagesWaitingFromISR( const xQueueHandle pxQueue ); - - -/* - * xQueueAltGenericSend() is an alternative version of xQueueGenericSend(). - * Likewise xQueueAltGenericReceive() is an alternative version of - * xQueueGenericReceive(). - * - * The source code that implements the alternative (Alt) API is much - * simpler because it executes everything from within a critical section. - * This is the approach taken by many other RTOSes, but FreeRTOS.org has the - * preferred fully featured API too. The fully featured API has more - * complex code that takes longer to execute, but makes much less use of - * critical sections. Therefore the alternative API sacrifices interrupt - * responsiveness to gain execution speed, whereas the fully featured API - * sacrifices execution speed to ensure better interrupt responsiveness. - */ -signed portBASE_TYPE xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ); -signed portBASE_TYPE xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ); -#define xQueueAltSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( xQueue, pvItemToQueue, xTicksToWait, queueSEND_TO_FRONT ) -#define xQueueAltSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( xQueue, pvItemToQueue, xTicksToWait, queueSEND_TO_BACK ) -#define xQueueAltReceive( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( xQueue, pvBuffer, xTicksToWait, pdFALSE ) -#define xQueueAltPeek( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( xQueue, pvBuffer, xTicksToWait, pdTRUE ) - -/* - * The functions defined above are for passing data to and from tasks. The - * functions below are the equivalents for passing data to and from - * co-routines. - * - * These functions are called from the co-routine macro implementation and - * should not be called directly from application code. Instead use the macro - * wrappers defined within croutine.h. - */ -signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ); -signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); -signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ); -signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); - -/* - * For internal use only. Use xSemaphoreCreateMutex() or - * xSemaphoreCreateCounting() instead of calling these functions directly. - */ -xQueueHandle xQueueCreateMutex( void ); -xQueueHandle xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount ); - -/* - * For internal use only. Use xSemaphoreTakeMutexRecursive() or - * xSemaphoreGiveMutexRecursive() instead of calling these functions directly. - */ -portBASE_TYPE xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime ); -portBASE_TYPE xQueueGiveMutexRecursive( xQueueHandle xMutex ); - -/* - * The registry is provided as a means for kernel aware debuggers to - * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add - * a queue, semaphore or mutex handle to the registry if you want the handle - * to be available to a kernel aware debugger. If you are not using a kernel - * aware debugger then this function can be ignored. - * - * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the - * registry can hold. configQUEUE_REGISTRY_SIZE must be greater than 0 - * within FreeRTOSConfig.h for the registry to be available. Its value - * does not effect the number of queues, semaphores and mutexes that can be - * created - just the number that the registry can hold. - * - * @param xQueue The handle of the queue being added to the registry. This - * is the handle returned by a call to xQueueCreate(). Semaphore and mutex - * handles can also be passed in here. - * - * @param pcName The name to be associated with the handle. This is the - * name that the kernel aware debugger will display. - */ -#if configQUEUE_REGISTRY_SIZE > 0 - void vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcName ); -#endif - - - - -#ifdef __cplusplus -} -#endif - -#endif /* QUEUE_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/semphr.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/semphr.h deleted file mode 100644 index a01902b1d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/semphr.h +++ /dev/null @@ -1,711 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -#ifndef INC_FREERTOS_H - #error "#include FreeRTOS.h" must appear in source files before "#include semphr.h" -#endif - -#ifndef SEMAPHORE_H -#define SEMAPHORE_H - -#include "queue.h" - -typedef xQueueHandle xSemaphoreHandle; - -#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( unsigned char ) 1 ) -#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( unsigned char ) 0 ) -#define semGIVE_BLOCK_TIME ( ( portTickType ) 0 ) - - -/** - * semphr. h - *
vSemaphoreCreateBinary( xSemaphoreHandle xSemaphore )
- * - * Macro that implements a semaphore by using the existing queue mechanism. - * The queue length is 1 as this is a binary semaphore. The data size is 0 - * as we don't want to actually store any data - we just want to know if the - * queue is empty or full. - * - * This type of semaphore can be used for pure synchronisation between tasks or - * between an interrupt and a task. The semaphore need not be given back once - * obtained, so one task/interrupt can continuously 'give' the semaphore while - * another continuously 'takes' the semaphore. For this reason this type of - * semaphore does not use a priority inheritance mechanism. For an alternative - * that does use priority inheritance see xSemaphoreCreateMutex(). - * - * @param xSemaphore Handle to the created semaphore. Should be of type xSemaphoreHandle. - * - * Example usage: -
- xSemaphoreHandle xSemaphore;
-
- void vATask( void * pvParameters )
- {
-    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
-    // This is a macro so pass the variable in directly.
-    vSemaphoreCreateBinary( xSemaphore );
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.  
-    }
- }
- 
- * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary - * \ingroup Semaphores - */ -#define vSemaphoreCreateBinary( xSemaphore ) { \ - xSemaphore = xQueueCreate( ( unsigned portBASE_TYPE ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH ); \ - if( xSemaphore != NULL ) \ - { \ - xSemaphoreGive( xSemaphore ); \ - } \ - } - -/** - * semphr. h - * xSemaphoreTake( - * xSemaphoreHandle xSemaphore, - * portTickType xBlockTime - * ) - * - * Macro to obtain a semaphore. The semaphore must have previously been - * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or - * xSemaphoreCreateCounting(). - * - * @param xSemaphore A handle to the semaphore being taken - obtained when - * the semaphore was created. - * - * @param xBlockTime The time in ticks to wait for the semaphore to become - * available. The macro portTICK_RATE_MS can be used to convert this to a - * real time. A block time of zero can be used to poll the semaphore. A block - * time of portMAX_DELAY can be used to block indefinitely (provided - * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h). - * - * @return pdTRUE if the semaphore was obtained. pdFALSE - * if xBlockTime expired without the semaphore becoming available. - * - * Example usage: -
- xSemaphoreHandle xSemaphore = NULL;
-
- // A task that creates a semaphore.
- void vATask( void * pvParameters )
- {
-    // Create the semaphore to guard a shared resource.
-    vSemaphoreCreateBinary( xSemaphore );
- }
-
- // A task that uses the semaphore.
- void vAnotherTask( void * pvParameters )
- {
-    // ... Do other things.
-
-    if( xSemaphore != NULL )
-    {
-        // See if we can obtain the semaphore.  If the semaphore is not available
-        // wait 10 ticks to see if it becomes free.	
-        if( xSemaphoreTake( xSemaphore, ( portTickType ) 10 ) == pdTRUE )
-        {
-            // We were able to obtain the semaphore and can now access the
-            // shared resource.
-
-            // ...
-
-            // We have finished accessing the shared resource.  Release the 
-            // semaphore.
-            xSemaphoreGive( xSemaphore );
-        }
-        else
-        {
-            // We could not obtain the semaphore and can therefore not access
-            // the shared resource safely.
-        }
-    }
- }
- 
- * \defgroup xSemaphoreTake xSemaphoreTake - * \ingroup Semaphores - */ -#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueGenericReceive( ( xQueueHandle ) xSemaphore, NULL, xBlockTime, pdFALSE ) - -/** - * semphr. h - * xSemaphoreTakeRecursive( - * xSemaphoreHandle xMutex, - * portTickType xBlockTime - * ) - * - * Macro to recursively obtain, or 'take', a mutex type semaphore. - * The mutex must have previously been created using a call to - * xSemaphoreCreateRecursiveMutex(); - * - * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this - * macro to be available. - * - * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). - * - * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex - * doesn't become available again until the owner has called - * xSemaphoreGiveRecursive() for each successful 'take' request. For example, - * if a task successfully 'takes' the same mutex 5 times then the mutex will - * not be available to any other task until it has also 'given' the mutex back - * exactly five times. - * - * @param xMutex A handle to the mutex being obtained. This is the - * handle returned by xSemaphoreCreateRecursiveMutex(); - * - * @param xBlockTime The time in ticks to wait for the semaphore to become - * available. The macro portTICK_RATE_MS can be used to convert this to a - * real time. A block time of zero can be used to poll the semaphore. If - * the task already owns the semaphore then xSemaphoreTakeRecursive() will - * return immediately no matter what the value of xBlockTime. - * - * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime - * expired without the semaphore becoming available. - * - * Example usage: -
- xSemaphoreHandle xMutex = NULL;
-
- // A task that creates a mutex.
- void vATask( void * pvParameters )
- {
-    // Create the mutex to guard a shared resource.
-    xMutex = xSemaphoreCreateRecursiveMutex();
- }
-
- // A task that uses the mutex.
- void vAnotherTask( void * pvParameters )
- {
-    // ... Do other things.
-
-    if( xMutex != NULL )
-    {
-        // See if we can obtain the mutex.  If the mutex is not available
-        // wait 10 ticks to see if it becomes free.	
-        if( xSemaphoreTakeRecursive( xSemaphore, ( portTickType ) 10 ) == pdTRUE )
-        {
-            // We were able to obtain the mutex and can now access the
-            // shared resource.
-
-            // ...
-            // For some reason due to the nature of the code further calls to 
-			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
-			// code these would not be just sequential calls as this would make
-			// no sense.  Instead the calls are likely to be buried inside
-			// a more complex call structure.
-            xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 );
-            xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 );
-
-            // The mutex has now been 'taken' three times, so will not be 
-			// available to another task until it has also been given back
-			// three times.  Again it is unlikely that real code would have
-			// these calls sequentially, but instead buried in a more complex
-			// call structure.  This is just for illustrative purposes.
-            xSemaphoreGiveRecursive( xMutex );
-			xSemaphoreGiveRecursive( xMutex );
-			xSemaphoreGiveRecursive( xMutex );
-
-			// Now the mutex can be taken by other tasks.
-        }
-        else
-        {
-            // We could not obtain the mutex and can therefore not access
-            // the shared resource safely.
-        }
-    }
- }
- 
- * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive - * \ingroup Semaphores - */ -#define xSemaphoreTakeRecursive( xMutex, xBlockTime ) xQueueTakeMutexRecursive( xMutex, xBlockTime ) - - -/* - * xSemaphoreAltTake() is an alternative version of xSemaphoreTake(). - * - * The source code that implements the alternative (Alt) API is much - * simpler because it executes everything from within a critical section. - * This is the approach taken by many other RTOSes, but FreeRTOS.org has the - * preferred fully featured API too. The fully featured API has more - * complex code that takes longer to execute, but makes much less use of - * critical sections. Therefore the alternative API sacrifices interrupt - * responsiveness to gain execution speed, whereas the fully featured API - * sacrifices execution speed to ensure better interrupt responsiveness. - */ -#define xSemaphoreAltTake( xSemaphore, xBlockTime ) xQueueAltGenericReceive( ( xQueueHandle ) xSemaphore, NULL, xBlockTime, pdFALSE ) - -/** - * semphr. h - *
xSemaphoreGive( xSemaphoreHandle xSemaphore )
- * - * Macro to release a semaphore. The semaphore must have previously been - * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or - * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake(). - * - * This macro must not be used from an ISR. See xSemaphoreGiveFromISR () for - * an alternative which can be used from an ISR. - * - * This macro must also not be used on semaphores created using - * xSemaphoreCreateRecursiveMutex(). - * - * @param xSemaphore A handle to the semaphore being released. This is the - * handle returned when the semaphore was created. - * - * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. - * Semaphores are implemented using queues. An error can occur if there is - * no space on the queue to post a message - indicating that the - * semaphore was not first obtained correctly. - * - * Example usage: -
- xSemaphoreHandle xSemaphore = NULL;
-
- void vATask( void * pvParameters )
- {
-    // Create the semaphore to guard a shared resource.
-    vSemaphoreCreateBinary( xSemaphore );
-
-    if( xSemaphore != NULL )
-    {
-        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
-        {
-            // We would expect this call to fail because we cannot give
-            // a semaphore without first "taking" it!
-        }
-
-        // Obtain the semaphore - don't block if the semaphore is not
-        // immediately available.
-        if( xSemaphoreTake( xSemaphore, ( portTickType ) 0 ) )
-        {
-            // We now have the semaphore and can access the shared resource.
-
-            // ...
-
-            // We have finished accessing the shared resource so can free the
-            // semaphore.
-            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
-            {
-                // We would not expect this call to fail because we must have
-                // obtained the semaphore to get here.
-            }
-        }
-    }
- }
- 
- * \defgroup xSemaphoreGive xSemaphoreGive - * \ingroup Semaphores - */ -#define xSemaphoreGive( xSemaphore ) xQueueGenericSend( ( xQueueHandle ) xSemaphore, NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK ) - -/** - * semphr. h - *
xSemaphoreGiveRecursive( xSemaphoreHandle xMutex )
- * - * Macro to recursively release, or 'give', a mutex type semaphore. - * The mutex must have previously been created using a call to - * xSemaphoreCreateRecursiveMutex(); - * - * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this - * macro to be available. - * - * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). - * - * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex - * doesn't become available again until the owner has called - * xSemaphoreGiveRecursive() for each successful 'take' request. For example, - * if a task successfully 'takes' the same mutex 5 times then the mutex will - * not be available to any other task until it has also 'given' the mutex back - * exactly five times. - * - * @param xMutex A handle to the mutex being released, or 'given'. This is the - * handle returned by xSemaphoreCreateMutex(); - * - * @return pdTRUE if the semaphore was given. - * - * Example usage: -
- xSemaphoreHandle xMutex = NULL;
-
- // A task that creates a mutex.
- void vATask( void * pvParameters )
- {
-    // Create the mutex to guard a shared resource.
-    xMutex = xSemaphoreCreateRecursiveMutex();
- }
-
- // A task that uses the mutex.
- void vAnotherTask( void * pvParameters )
- {
-    // ... Do other things.
-
-    if( xMutex != NULL )
-    {
-        // See if we can obtain the mutex.  If the mutex is not available
-        // wait 10 ticks to see if it becomes free.	
-        if( xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 ) == pdTRUE )
-        {
-            // We were able to obtain the mutex and can now access the
-            // shared resource.
-
-            // ...
-            // For some reason due to the nature of the code further calls to 
-			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
-			// code these would not be just sequential calls as this would make
-			// no sense.  Instead the calls are likely to be buried inside
-			// a more complex call structure.
-            xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 );
-            xSemaphoreTakeRecursive( xMutex, ( portTickType ) 10 );
-
-            // The mutex has now been 'taken' three times, so will not be 
-			// available to another task until it has also been given back
-			// three times.  Again it is unlikely that real code would have
-			// these calls sequentially, it would be more likely that the calls
-			// to xSemaphoreGiveRecursive() would be called as a call stack
-			// unwound.  This is just for demonstrative purposes.
-            xSemaphoreGiveRecursive( xMutex );
-			xSemaphoreGiveRecursive( xMutex );
-			xSemaphoreGiveRecursive( xMutex );
-
-			// Now the mutex can be taken by other tasks.
-        }
-        else
-        {
-            // We could not obtain the mutex and can therefore not access
-            // the shared resource safely.
-        }
-    }
- }
- 
- * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive - * \ingroup Semaphores - */ -#define xSemaphoreGiveRecursive( xMutex ) xQueueGiveMutexRecursive( xMutex ) - -/* - * xSemaphoreAltGive() is an alternative version of xSemaphoreGive(). - * - * The source code that implements the alternative (Alt) API is much - * simpler because it executes everything from within a critical section. - * This is the approach taken by many other RTOSes, but FreeRTOS.org has the - * preferred fully featured API too. The fully featured API has more - * complex code that takes longer to execute, but makes much less use of - * critical sections. Therefore the alternative API sacrifices interrupt - * responsiveness to gain execution speed, whereas the fully featured API - * sacrifices execution speed to ensure better interrupt responsiveness. - */ -#define xSemaphoreAltGive( xSemaphore ) xQueueAltGenericSend( ( xQueueHandle ) xSemaphore, NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK ) - -/** - * semphr. h - *
- xSemaphoreGiveFromISR( 
-                          xSemaphoreHandle xSemaphore, 
-                          portBASE_TYPE *pxHigherPriorityTaskWoken
-                      )
- * - * Macro to release a semaphore. The semaphore must have previously been - * created with a call to vSemaphoreCreateBinary() or xSemaphoreCreateCounting(). - * - * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex()) - * must not be used with this macro. - * - * This macro can be used from an ISR. - * - * @param xSemaphore A handle to the semaphore being released. This is the - * handle returned when the semaphore was created. - * - * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set - * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task - * to unblock, and the unblocked task has a priority higher than the currently - * running task. If xSemaphoreGiveFromISR() sets this value to pdTRUE then - * a context switch should be requested before the interrupt is exited. - * - * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL. - * - * Example usage: -
- #define LONG_TIME 0xffff
- #define TICKS_TO_WAIT	10
- xSemaphoreHandle xSemaphore = NULL;
-
- // Repetitive task.
- void vATask( void * pvParameters )
- {
-    for( ;; )
-    {
-        // We want this task to run every 10 ticks of a timer.  The semaphore 
-        // was created before this task was started.
-
-        // Block waiting for the semaphore to become available.
-        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
-        {
-            // It is time to execute.
-
-            // ...
-
-            // We have finished our task.  Return to the top of the loop where
-            // we will block on the semaphore until it is time to execute 
-            // again.  Note when using the semaphore for synchronisation with an
-			// ISR in this manner there is no need to 'give' the semaphore back.
-        }
-    }
- }
-
- // Timer ISR
- void vTimerISR( void * pvParameters )
- {
- static unsigned char ucLocalTickCount = 0;
- static portBASE_TYPE xHigherPriorityTaskWoken;
-
-    // A timer tick has occurred.
-
-    // ... Do other time functions.
-
-    // Is it time for vATask () to run?
-	xHigherPriorityTaskWoken = pdFALSE;
-    ucLocalTickCount++;
-    if( ucLocalTickCount >= TICKS_TO_WAIT )
-    {
-        // Unblock the task by releasing the semaphore.
-        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
-
-        // Reset the count so we release the semaphore again in 10 ticks time.
-        ucLocalTickCount = 0;
-    }
-
-    if( xHigherPriorityTaskWoken != pdFALSE )
-    {
-        // We can force a context switch here.  Context switching from an
-        // ISR uses port specific syntax.  Check the demo task for your port
-        // to find the syntax required.
-    }
- }
- 
- * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR - * \ingroup Semaphores - */ -#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueueHandle ) xSemaphore, NULL, pxHigherPriorityTaskWoken, queueSEND_TO_BACK ) - -/** - * semphr. h - *
xSemaphoreHandle xSemaphoreCreateMutex( void )
- * - * Macro that implements a mutex semaphore by using the existing queue - * mechanism. - * - * Mutexes created using this macro can be accessed using the xSemaphoreTake() - * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and - * xSemaphoreGiveRecursive() macros should not be used. - * - * This type of semaphore uses a priority inheritance mechanism so a task - * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the - * semaphore it is no longer required. - * - * Mutex type semaphores cannot be used from within interrupt service routines. - * - * See vSemaphoreCreateBinary() for an alternative implementation that can be - * used for pure synchronisation (where one task or interrupt always 'gives' the - * semaphore and another always 'takes' the semaphore) and from within interrupt - * service routines. - * - * @return xSemaphore Handle to the created mutex semaphore. Should be of type - * xSemaphoreHandle. - * - * Example usage: -
- xSemaphoreHandle xSemaphore;
-
- void vATask( void * pvParameters )
- {
-    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
-    // This is a macro so pass the variable in directly.
-    xSemaphore = xSemaphoreCreateMutex();
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.  
-    }
- }
- 
- * \defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex - * \ingroup Semaphores - */ -#define xSemaphoreCreateMutex() xQueueCreateMutex() - - -/** - * semphr. h - *
xSemaphoreHandle xSemaphoreCreateRecursiveMutex( void )
- * - * Macro that implements a recursive mutex by using the existing queue - * mechanism. - * - * Mutexes created using this macro can be accessed using the - * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The - * xSemaphoreTake() and xSemaphoreGive() macros should not be used. - * - * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex - * doesn't become available again until the owner has called - * xSemaphoreGiveRecursive() for each successful 'take' request. For example, - * if a task successfully 'takes' the same mutex 5 times then the mutex will - * not be available to any other task until it has also 'given' the mutex back - * exactly five times. - * - * This type of semaphore uses a priority inheritance mechanism so a task - * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the - * semaphore it is no longer required. - * - * Mutex type semaphores cannot be used from within interrupt service routines. - * - * See vSemaphoreCreateBinary() for an alternative implementation that can be - * used for pure synchronisation (where one task or interrupt always 'gives' the - * semaphore and another always 'takes' the semaphore) and from within interrupt - * service routines. - * - * @return xSemaphore Handle to the created mutex semaphore. Should be of type - * xSemaphoreHandle. - * - * Example usage: -
- xSemaphoreHandle xSemaphore;
-
- void vATask( void * pvParameters )
- {
-    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
-    // This is a macro so pass the variable in directly.
-    xSemaphore = xSemaphoreCreateRecursiveMutex();
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.  
-    }
- }
- 
- * \defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex - * \ingroup Semaphores - */ -#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex() - -/** - * semphr. h - *
xSemaphoreHandle xSemaphoreCreateCounting( unsigned portBASE_TYPE uxMaxCount, unsigned portBASE_TYPE uxInitialCount )
- * - * Macro that creates a counting semaphore by using the existing - * queue mechanism. - * - * Counting semaphores are typically used for two things: - * - * 1) Counting events. - * - * In this usage scenario an event handler will 'give' a semaphore each time - * an event occurs (incrementing the semaphore count value), and a handler - * task will 'take' a semaphore each time it processes an event - * (decrementing the semaphore count value). The count value is therefore - * the difference between the number of events that have occurred and the - * number that have been processed. In this case it is desirable for the - * initial count value to be zero. - * - * 2) Resource management. - * - * In this usage scenario the count value indicates the number of resources - * available. To obtain control of a resource a task must first obtain a - * semaphore - decrementing the semaphore count value. When the count value - * reaches zero there are no free resources. When a task finishes with the - * resource it 'gives' the semaphore back - incrementing the semaphore count - * value. In this case it is desirable for the initial count value to be - * equal to the maximum count value, indicating that all resources are free. - * - * @param uxMaxCount The maximum count value that can be reached. When the - * semaphore reaches this value it can no longer be 'given'. - * - * @param uxInitialCount The count value assigned to the semaphore when it is - * created. - * - * @return Handle to the created semaphore. Null if the semaphore could not be - * created. - * - * Example usage: -
- xSemaphoreHandle xSemaphore;
-
- void vATask( void * pvParameters )
- {
- xSemaphoreHandle xSemaphore = NULL;
-
-    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
-    // The max value to which the semaphore can count should be 10, and the
-    // initial value assigned to the count should be 0.
-    xSemaphore = xSemaphoreCreateCounting( 10, 0 );
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.  
-    }
- }
- 
- * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting - * \ingroup Semaphores - */ -#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( uxMaxCount, uxInitialCount ) - - -#endif /* SEMAPHORE_H */ - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/task.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/task.h deleted file mode 100644 index 61e01f833..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/include/task.h +++ /dev/null @@ -1,1267 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - - -#ifndef INC_FREERTOS_H - #error "#include FreeRTOS.h" must appear in source files before "#include task.h" -#endif - - - -#ifndef TASK_H -#define TASK_H - -#include "portable.h" -#include "list.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*----------------------------------------------------------- - * MACROS AND DEFINITIONS - *----------------------------------------------------------*/ - -#define tskKERNEL_VERSION_NUMBER "V6.0.0" - -/** - * task. h - * - * Type by which tasks are referenced. For example, a call to xTaskCreate - * returns (via a pointer parameter) an xTaskHandle variable that can then - * be used as a parameter to vTaskDelete to delete the task. - * - * \page xTaskHandle xTaskHandle - * \ingroup Tasks - */ -typedef void * xTaskHandle; - -/* - * Used internally only. - */ -typedef struct xTIME_OUT -{ - portBASE_TYPE xOverflowCount; - portTickType xTimeOnEntering; -} xTimeOutType; - -/* - * Defines the memory ranges allocated to the task when an MPU is used. - */ -typedef struct xMEMORY_REGION -{ - void *pvBaseAddress; - unsigned long ulLengthInBytes; - unsigned long ulParameters; -} xMemoryRegion; - -/* - * Parameters required to create an MPU protected task. - */ -typedef struct xTASK_PARAMTERS -{ - pdTASK_CODE pvTaskCode; - const signed char * const pcName; - unsigned short usStackDepth; - void *pvParameters; - unsigned portBASE_TYPE uxPriority; - portSTACK_TYPE *puxStackBuffer; - xMemoryRegion xRegions[ portNUM_CONFIGURABLE_REGIONS ]; -} xTaskParameters; - -/* - * Defines the priority used by the idle task. This must not be modified. - * - * \ingroup TaskUtils - */ -#define tskIDLE_PRIORITY ( ( unsigned portBASE_TYPE ) 0 ) - -/** - * task. h - * - * Macro for forcing a context switch. - * - * \page taskYIELD taskYIELD - * \ingroup SchedulerControl - */ -#define taskYIELD() portYIELD() - -/** - * task. h - * - * Macro to mark the start of a critical code region. Preemptive context - * switches cannot occur when in a critical region. - * - * NOTE: This may alter the stack (depending on the portable implementation) - * so must be used with care! - * - * \page taskENTER_CRITICAL taskENTER_CRITICAL - * \ingroup SchedulerControl - */ -#define taskENTER_CRITICAL() portENTER_CRITICAL() - -/** - * task. h - * - * Macro to mark the end of a critical code region. Preemptive context - * switches cannot occur when in a critical region. - * - * NOTE: This may alter the stack (depending on the portable implementation) - * so must be used with care! - * - * \page taskEXIT_CRITICAL taskEXIT_CRITICAL - * \ingroup SchedulerControl - */ -#define taskEXIT_CRITICAL() portEXIT_CRITICAL() - -/** - * task. h - * - * Macro to disable all maskable interrupts. - * - * \page taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS - * \ingroup SchedulerControl - */ -#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() - -/** - * task. h - * - * Macro to enable microcontroller interrupts. - * - * \page taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS - * \ingroup SchedulerControl - */ -#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() - -/* Definitions returned by xTaskGetSchedulerState(). */ -#define taskSCHEDULER_NOT_STARTED 0 -#define taskSCHEDULER_RUNNING 1 -#define taskSCHEDULER_SUSPENDED 2 - -/*----------------------------------------------------------- - * TASK CREATION API - *----------------------------------------------------------*/ - -/** - * task. h - *
- portBASE_TYPE xTaskCreate(
-							  pdTASK_CODE pvTaskCode,
-							  const char * const pcName,
-							  unsigned short usStackDepth,
-							  void *pvParameters,
-							  unsigned portBASE_TYPE uxPriority,
-							  xTaskHandle *pvCreatedTask
-						  );
- * - * Create a new task and add it to the list of tasks that are ready to run. - * - * xTaskCreate() can only be used to create a task that has unrestricted - * access to the entire microcontroller memory map. Systems that include MPU - * support can alternatively create an MPU constrained task using - * xTaskCreateRestricted(). - * - * @param pvTaskCode Pointer to the task entry function. Tasks - * must be implemented to never return (i.e. continuous loop). - * - * @param pcName A descriptive name for the task. This is mainly used to - * facilitate debugging. Max length defined by tskMAX_TASK_NAME_LEN - default - * is 16. - * - * @param usStackDepth The size of the task stack specified as the number of - * variables the stack can hold - not the number of bytes. For example, if - * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes - * will be allocated for stack storage. - * - * @param pvParameters Pointer that will be used as the parameter for the task - * being created. - * - * @param uxPriority The priority at which the task should run. Systems that - * include MPU support can optionally create tasks in a privileged (system) - * mode by setting bit portPRIVILEGE_BIT of the priority parameter. For - * example, to create a privileged task at priority 2 the uxPriority parameter - * should be set to ( 2 | portPRIVILEGE_BIT ). - * - * @param pvCreatedTask Used to pass back a handle by which the created task - * can be referenced. - * - * @return pdPASS if the task was successfully created and added to a ready - * list, otherwise an error code defined in the file errors. h - * - * Example usage: -
- // Task to be created.
- void vTaskCode( void * pvParameters )
- {
-	 for( ;; )
-	 {
-		 // Task code goes here.
-	 }
- }
-
- // Function that creates a task.
- void vOtherFunction( void )
- {
- static unsigned char ucParameterToPass;
- xTaskHandle xHandle;
-
-	 // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
-	 // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
-	 // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
-	 // the new task attempts to access it.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
-
-	 // Use the handle to delete the task.
-	 vTaskDelete( xHandle );
- }
-   
- * \defgroup xTaskCreate xTaskCreate - * \ingroup Tasks - */ -#define xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask ) xTaskGenericCreate( ( pvTaskCode ), ( pcName ), ( usStackDepth ), ( pvParameters ), ( uxPriority ), ( pxCreatedTask ), ( NULL ), ( NULL ) ) - -/** - * task. h - *
- portBASE_TYPE xTaskCreateRestricted( xTaskParameters *pxTaskDefinition, xTaskHandle pxCreatedTask );
- * - * xTaskCreateRestricted() should only be used in systems that include an MPU - * implementation. - * - * Create a new task and add it to the list of tasks that are ready to run. - * The function parameters define the memory regions and associated access - * permissions allocated to the task. - * - * @param pxTaskDefinition Pointer to a structure that contains a member - * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API - * documentation) plus an optional stack buffer and the memory region - * definitions. - * - * @param pcName A descriptive name for the task. This is mainly used to - * facilitate debugging. Max length defined by tskMAX_TASK_NAME_LEN - default - * is 16. - * - * @param pxCreatedTask Used to pass back a handle by which the created task - * can be referenced. - * - * @return pdPASS if the task was successfully created and added to a ready - * list, otherwise an error code defined in the file errors. h - * - * Example usage: -
-// Create an xTaskParameters structure that defines the task to be created.
-static const xTaskParameters xCheckTaskParameters =
-{
-	vATask,		// pvTaskCode - the function that implements the task.
-	"ATask",	// pcName - just a text name for the task to assist debugging.
-	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
-	NULL,		// pvParameters - passed into the task function as the function parameters.
-	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
-	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
-
-	// xRegions - Allocate up to three separate memory regions for access by
-	// the task, with appropriate access permissions.  Different processors have
-	// different memory alignment requirements - refer to the FreeRTOS documentation
-	// for full information.
-	{											
-		// Base address					Length	Parameters
-        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
-        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
-        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
-	}
-};
-
-int main( void )
-{
-xTaskHandle xHandle;
-
-	// Create a task from the const structure defined above.  The task handle
-	// is requested (the second parameter is not NULL) but in this case just for
-	// demonstration purposes as its not actually used.
-	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
-
-	// Start the scheduler.
-	vTaskStartScheduler();
-
-	// Will only get here if there was insufficient memory to create the idle
-	// task.
-	for( ;; );
-}
-   
- * \defgroup xTaskCreateRestricted xTaskCreateRestricted - * \ingroup Tasks - */ -#define xTaskCreateRestricted( x, pxCreatedTask ) xTaskGenericCreate( ((x)->pvTaskCode), ((x)->pcName), ((x)->usStackDepth), ((x)->pvParameters), ((x)->uxPriority), (pxCreatedTask), ((x)->puxStackBuffer), ((x)->xRegions) ) - -/** - * task. h - *
- void vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const pxRegions );
- * - * Memory regions are assigned to a restricted task when the task is created by - * a call to xTaskCreateRestricted(). These regions can be redefined using - * vTaskAllocateMPURegions(). - * - * @param xTask The handle of the task being updated. - * - * @param xRegions A pointer to an xMemoryRegion structure that contains the - * new memory region definitions. - * - * Example usage: -
-// Define an array of xMemoryRegion structures that configures an MPU region
-// allowing read/write access for 1024 bytes starting at the beginning of the
-// ucOneKByte array.  The other two of the maximum 3 definable regions are
-// unused so set to zero.
-static const xMemoryRegion xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
-{											
-	// Base address		Length		Parameters
-	{ ucOneKByte,		1024,		portMPU_REGION_READ_WRITE },
-	{ 0,				0,			0 },
-	{ 0,				0,			0 }
-};
-
-void vATask( void *pvParameters )
-{
-	// This task was created such that it has access to certain regions of
-	// memory as defined by the MPU configuration.  At some point it is 
-	// desired that these MPU regions are replaced with that defined in the
-	// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
-	// for this purpose.  NULL is used as the task handle to indicate that this
-	// function should modify the MPU regions of the calling task.
-	vTaskAllocateMPURegions( NULL, xAltRegions );
-	
-	// Now the task can continue its function, but from this point on can only
-	// access its stack and the ucOneKByte array (unless any other statically
-	// defined or shared regions have been declared elsewhere).
-}
-   
- * \defgroup xTaskCreateRestricted xTaskCreateRestricted - * \ingroup Tasks - */ -void vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const pxRegions ) PRIVILEGED_FUNCTION; - -/** - * task. h - *
void vTaskDelete( xTaskHandle pxTask );
- * - * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Remove a task from the RTOS real time kernels management. The task being - * deleted will be removed from all ready, blocked, suspended and event lists. - * - * NOTE: The idle task is responsible for freeing the kernel allocated - * memory from tasks that have been deleted. It is therefore important that - * the idle task is not starved of microcontroller processing time if your - * application makes any calls to vTaskDelete (). Memory allocated by the - * task code is not automatically freed, and should be freed before the task - * is deleted. - * - * See the demo application file death.c for sample code that utilises - * vTaskDelete (). - * - * @param pxTask The handle of the task to be deleted. Passing NULL will - * cause the calling task to be deleted. - * - * Example usage: -
- void vOtherFunction( void )
- {
- xTaskHandle xHandle;
-
-	 // Create the task, storing the handle.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-	 // Use the handle to delete the task.
-	 vTaskDelete( xHandle );
- }
-   
- * \defgroup vTaskDelete vTaskDelete - * \ingroup Tasks - */ -void vTaskDelete( xTaskHandle pxTask ) PRIVILEGED_FUNCTION; - - -/*----------------------------------------------------------- - * TASK CONTROL API - *----------------------------------------------------------*/ - -/** - * task. h - *
void vTaskDelay( portTickType xTicksToDelay );
- * - * Delay a task for a given number of ticks. The actual time that the - * task remains blocked depends on the tick rate. The constant - * portTICK_RATE_MS can be used to calculate real time from the tick - * rate - with the resolution of one tick period. - * - * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * - * vTaskDelay() specifies a time at which the task wishes to unblock relative to - * the time at which vTaskDelay() is called. For example, specifying a block - * period of 100 ticks will cause the task to unblock 100 ticks after - * vTaskDelay() is called. vTaskDelay() does not therefore provide a good method - * of controlling the frequency of a cyclical task as the path taken through the - * code, as well as other task and interrupt activity, will effect the frequency - * at which vTaskDelay() gets called and therefore the time at which the task - * next executes. See vTaskDelayUntil() for an alternative API function designed - * to facilitate fixed frequency execution. It does this by specifying an - * absolute time (rather than a relative time) at which the calling task should - * unblock. - * - * @param xTicksToDelay The amount of time, in tick periods, that - * the calling task should block. - * - * Example usage: - - void vTaskFunction( void * pvParameters ) - { - void vTaskFunction( void * pvParameters ) - { - // Block for 500ms. - const portTickType xDelay = 500 / portTICK_RATE_MS; - - for( ;; ) - { - // Simply toggle the LED every 500ms, blocking between each toggle. - vToggleLED(); - vTaskDelay( xDelay ); - } - } - - * \defgroup vTaskDelay vTaskDelay - * \ingroup TaskCtrl - */ -void vTaskDelay( portTickType xTicksToDelay ) PRIVILEGED_FUNCTION; - -/** - * task. h - *
void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement );
- * - * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Delay a task until a specified time. This function can be used by cyclical - * tasks to ensure a constant execution frequency. - * - * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will - * cause a task to block for the specified number of ticks from the time vTaskDelay () is - * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed - * execution frequency as the time between a task starting to execute and that task - * calling vTaskDelay () may not be fixed [the task may take a different path though the - * code between calls, or may get interrupted or preempted a different number of times - * each time it executes]. - * - * Whereas vTaskDelay () specifies a wake time relative to the time at which the function - * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to - * unblock. - * - * The constant portTICK_RATE_MS can be used to calculate real time from the tick - * rate - with the resolution of one tick period. - * - * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the - * task was last unblocked. The variable must be initialised with the current time - * prior to its first use (see the example below). Following this the variable is - * automatically updated within vTaskDelayUntil (). - * - * @param xTimeIncrement The cycle time period. The task will be unblocked at - * time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the - * same xTimeIncrement parameter value will cause the task to execute with - * a fixed interface period. - * - * Example usage: -
- // Perform an action every 10 ticks.
- void vTaskFunction( void * pvParameters )
- {
- portTickType xLastWakeTime;
- const portTickType xFrequency = 10;
-
-	 // Initialise the xLastWakeTime variable with the current time.
-	 xLastWakeTime = xTaskGetTickCount ();
-	 for( ;; )
-	 {
-		 // Wait for the next cycle.
-		 vTaskDelayUntil( &xLastWakeTime, xFrequency );
-
-		 // Perform action here.
-	 }
- }
-   
- * \defgroup vTaskDelayUntil vTaskDelayUntil - * \ingroup TaskCtrl - */ -void vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement ) PRIVILEGED_FUNCTION; - -/** - * task. h - *
unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask );
- * - * INCLUDE_xTaskPriorityGet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Obtain the priority of any task. - * - * @param pxTask Handle of the task to be queried. Passing a NULL - * handle results in the priority of the calling task being returned. - * - * @return The priority of pxTask. - * - * Example usage: -
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-
-	 // Create a task, storing the handle.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-	 // ...
-
-	 // Use the handle to obtain the priority of the created task.
-	 // It was created with tskIDLE_PRIORITY, but may have changed
-	 // it itself.
-	 if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
-	 {
-		 // The task has changed it's priority.
-	 }
-
-	 // ...
-
-	 // Is our priority higher than the created task?
-	 if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
-	 {
-		 // Our priority (obtained using NULL handle) is higher.
-	 }
- }
-   
- * \defgroup uxTaskPriorityGet uxTaskPriorityGet - * \ingroup TaskCtrl - */ -unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ) PRIVILEGED_FUNCTION; - -/** - * task. h - *
void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );
- * - * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Set the priority of any task. - * - * A context switch will occur before the function returns if the priority - * being set is higher than the currently executing task. - * - * @param pxTask Handle to the task for which the priority is being set. - * Passing a NULL handle results in the priority of the calling task being set. - * - * @param uxNewPriority The priority to which the task will be set. - * - * Example usage: -
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-
-	 // Create a task, storing the handle.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-	 // ...
-
-	 // Use the handle to raise the priority of the created task.
-	 vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
-
-	 // ...
-
-	 // Use a NULL handle to raise our priority to the same value.
-	 vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
- }
-   
- * \defgroup vTaskPrioritySet vTaskPrioritySet - * \ingroup TaskCtrl - */ -void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ) PRIVILEGED_FUNCTION; - -/** - * task. h - *
void vTaskSuspend( xTaskHandle pxTaskToSuspend );
- * - * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Suspend any task. When suspended a task will never get any microcontroller - * processing time, no matter what its priority. - * - * Calls to vTaskSuspend are not accumulative - - * i.e. calling vTaskSuspend () twice on the same task still only requires one - * call to vTaskResume () to ready the suspended task. - * - * @param pxTaskToSuspend Handle to the task being suspended. Passing a NULL - * handle will cause the calling task to be suspended. - * - * Example usage: -
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-
-	 // Create a task, storing the handle.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-	 // ...
-
-	 // Use the handle to suspend the created task.
-	 vTaskSuspend( xHandle );
-
-	 // ...
-
-	 // The created task will not run during this period, unless
-	 // another task calls vTaskResume( xHandle ).
-
-	 //...
-
-
-	 // Suspend ourselves.
-	 vTaskSuspend( NULL );
-
-	 // We cannot get here unless another task calls vTaskResume
-	 // with our handle as the parameter.
- }
-   
- * \defgroup vTaskSuspend vTaskSuspend - * \ingroup TaskCtrl - */ -void vTaskSuspend( xTaskHandle pxTaskToSuspend ) PRIVILEGED_FUNCTION; - -/** - * task. h - *
void vTaskResume( xTaskHandle pxTaskToResume );
- * - * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Resumes a suspended task. - * - * A task that has been suspended by one of more calls to vTaskSuspend () - * will be made available for running again by a single call to - * vTaskResume (). - * - * @param pxTaskToResume Handle to the task being readied. - * - * Example usage: -
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-
-	 // Create a task, storing the handle.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-	 // ...
-
-	 // Use the handle to suspend the created task.
-	 vTaskSuspend( xHandle );
-
-	 // ...
-
-	 // The created task will not run during this period, unless
-	 // another task calls vTaskResume( xHandle ).
-
-	 //...
-
-
-	 // Resume the suspended task ourselves.
-	 vTaskResume( xHandle );
-
-	 // The created task will once again get microcontroller processing
-	 // time in accordance with it priority within the system.
- }
-   
- * \defgroup vTaskResume vTaskResume - * \ingroup TaskCtrl - */ -void vTaskResume( xTaskHandle pxTaskToResume ) PRIVILEGED_FUNCTION; - -/** - * task. h - *
void xTaskResumeFromISR( xTaskHandle pxTaskToResume );
- * - * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be - * available. See the configuration section for more information. - * - * An implementation of vTaskResume() that can be called from within an ISR. - * - * A task that has been suspended by one of more calls to vTaskSuspend () - * will be made available for running again by a single call to - * xTaskResumeFromISR (). - * - * @param pxTaskToResume Handle to the task being readied. - * - * \defgroup vTaskResumeFromISR vTaskResumeFromISR - * \ingroup TaskCtrl - */ -portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ) PRIVILEGED_FUNCTION; - -/*----------------------------------------------------------- - * SCHEDULER CONTROL - *----------------------------------------------------------*/ - -/** - * task. h - *
void vTaskStartScheduler( void );
- * - * Starts the real time kernel tick processing. After calling the kernel - * has control over which tasks are executed and when. This function - * does not return until an executing task calls vTaskEndScheduler (). - * - * At least one task should be created via a call to xTaskCreate () - * before calling vTaskStartScheduler (). The idle task is created - * automatically when the first application task is created. - * - * See the demo application file main.c for an example of creating - * tasks and starting the kernel. - * - * Example usage: -
- void vAFunction( void )
- {
-	 // Create at least one task before starting the kernel.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
-	 // Start the real time kernel with preemption.
-	 vTaskStartScheduler ();
-
-	 // Will not get here unless a task calls vTaskEndScheduler ()
- }
-   
- * - * \defgroup vTaskStartScheduler vTaskStartScheduler - * \ingroup SchedulerControl - */ -void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION; - -/** - * task. h - *
void vTaskEndScheduler( void );
- * - * Stops the real time kernel tick. All created tasks will be automatically - * deleted and multitasking (either preemptive or cooperative) will - * stop. Execution then resumes from the point where vTaskStartScheduler () - * was called, as if vTaskStartScheduler () had just returned. - * - * See the demo application file main. c in the demo/PC directory for an - * example that uses vTaskEndScheduler (). - * - * vTaskEndScheduler () requires an exit function to be defined within the - * portable layer (see vPortEndScheduler () in port. c for the PC port). This - * performs hardware specific operations such as stopping the kernel tick. - * - * vTaskEndScheduler () will cause all of the resources allocated by the - * kernel to be freed - but will not free resources allocated by application - * tasks. - * - * Example usage: -
- void vTaskCode( void * pvParameters )
- {
-	 for( ;; )
-	 {
-		 // Task code goes here.
-
-		 // At some point we want to end the real time kernel processing
-		 // so call ...
-		 vTaskEndScheduler ();
-	 }
- }
-
- void vAFunction( void )
- {
-	 // Create at least one task before starting the kernel.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
-	 // Start the real time kernel with preemption.
-	 vTaskStartScheduler ();
-
-	 // Will only get here when the vTaskCode () task has called
-	 // vTaskEndScheduler ().  When we get here we are back to single task
-	 // execution.
- }
-   
- * - * \defgroup vTaskEndScheduler vTaskEndScheduler - * \ingroup SchedulerControl - */ -void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION; - -/** - * task. h - *
void vTaskSuspendAll( void );
- * - * Suspends all real time kernel activity while keeping interrupts (including the - * kernel tick) enabled. - * - * After calling vTaskSuspendAll () the calling task will continue to execute - * without risk of being swapped out until a call to xTaskResumeAll () has been - * made. - * - * API functions that have the potential to cause a context switch (for example, - * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler - * is suspended. - * - * Example usage: -
- void vTask1( void * pvParameters )
- {
-	 for( ;; )
-	 {
-		 // Task code goes here.
-
-		 // ...
-
-		 // At some point the task wants to perform a long operation during
-		 // which it does not want to get swapped out.  It cannot use
-		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
-		 // operation may cause interrupts to be missed - including the
-		 // ticks.
-
-		 // Prevent the real time kernel swapping out the task.
-		 vTaskSuspendAll ();
-
-		 // Perform the operation here.  There is no need to use critical
-		 // sections as we have all the microcontroller processing time.
-		 // During this time interrupts will still operate and the kernel
-		 // tick count will be maintained.
-
-		 // ...
-
-		 // The operation is complete.  Restart the kernel.
-		 xTaskResumeAll ();
-	 }
- }
-   
- * \defgroup vTaskSuspendAll vTaskSuspendAll - * \ingroup SchedulerControl - */ -void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION; - -/** - * task. h - *
char xTaskResumeAll( void );
- * - * Resumes real time kernel activity following a call to vTaskSuspendAll (). - * After a call to vTaskSuspendAll () the kernel will take control of which - * task is executing at any time. - * - * @return If resuming the scheduler caused a context switch then pdTRUE is - * returned, otherwise pdFALSE is returned. - * - * Example usage: -
- void vTask1( void * pvParameters )
- {
-	 for( ;; )
-	 {
-		 // Task code goes here.
-
-		 // ...
-
-		 // At some point the task wants to perform a long operation during
-		 // which it does not want to get swapped out.  It cannot use
-		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
-		 // operation may cause interrupts to be missed - including the
-		 // ticks.
-
-		 // Prevent the real time kernel swapping out the task.
-		 vTaskSuspendAll ();
-
-		 // Perform the operation here.  There is no need to use critical
-		 // sections as we have all the microcontroller processing time.
-		 // During this time interrupts will still operate and the real
-		 // time kernel tick count will be maintained.
-
-		 // ...
-
-		 // The operation is complete.  Restart the kernel.  We want to force
-		 // a context switch - but there is no point if resuming the scheduler
-		 // caused a context switch already.
-		 if( !xTaskResumeAll () )
-		 {
-			  taskYIELD ();
-		 }
-	 }
- }
-   
- * \defgroup xTaskResumeAll xTaskResumeAll - * \ingroup SchedulerControl - */ -signed portBASE_TYPE xTaskResumeAll( void ) PRIVILEGED_FUNCTION; - -/** - * task. h - *
signed portBASE_TYPE xTaskIsTaskSuspended( xTaskHandle xTask );
- * - * Utility task that simply returns pdTRUE if the task referenced by xTask is - * currently in the Suspended state, or pdFALSE if the task referenced by xTask - * is in any other state. - * - */ -signed portBASE_TYPE xTaskIsTaskSuspended( xTaskHandle xTask ) PRIVILEGED_FUNCTION; - -/*----------------------------------------------------------- - * TASK UTILITIES - *----------------------------------------------------------*/ - -/** - * task. h - *
volatile portTickType xTaskGetTickCount( void );
- * - * @return The count of ticks since vTaskStartScheduler was called. - * - * \page xTaskGetTickCount xTaskGetTickCount - * \ingroup TaskUtils - */ -portTickType xTaskGetTickCount( void ) PRIVILEGED_FUNCTION; - -/** - * task. h - *
unsigned short uxTaskGetNumberOfTasks( void );
- * - * @return The number of tasks that the real time kernel is currently managing. - * This includes all ready, blocked and suspended tasks. A task that - * has been deleted but not yet freed by the idle task will also be - * included in the count. - * - * \page uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks - * \ingroup TaskUtils - */ -unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION; - -/** - * task. h - *
void vTaskList( char *pcWriteBuffer );
- * - * configUSE_TRACE_FACILITY must be defined as 1 for this function to be - * available. See the configuration section for more information. - * - * NOTE: This function will disable interrupts for its duration. It is - * not intended for normal application runtime use but as a debug aid. - * - * Lists all the current tasks, along with their current state and stack - * usage high water mark. - * - * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or - * suspended ('S'). - * - * @param pcWriteBuffer A buffer into which the above mentioned details - * will be written, in ascii form. This buffer is assumed to be large - * enough to contain the generated report. Approximately 40 bytes per - * task should be sufficient. - * - * \page vTaskList vTaskList - * \ingroup TaskUtils - */ -void vTaskList( signed char *pcWriteBuffer ) PRIVILEGED_FUNCTION; - -/** - * task. h - *
void vTaskGetRunTimeStats( char *pcWriteBuffer );
- * - * configGENERATE_RUN_TIME_STATS must be defined as 1 for this function - * to be available. The application must also then provide definitions - * for portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and - * portGET_RUN_TIME_COUNTER_VALUE to configure a peripheral timer/counter - * and return the timers current count value respectively. The counter - * should be at least 10 times the frequency of the tick count. - * - * NOTE: This function will disable interrupts for its duration. It is - * not intended for normal application runtime use but as a debug aid. - * - * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total - * accumulated execution time being stored for each task. The resolution - * of the accumulated time value depends on the frequency of the timer - * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. - * Calling vTaskGetRunTimeStats() writes the total execution time of each - * task into a buffer, both as an absolute count value and as a percentage - * of the total system execution time. - * - * @param pcWriteBuffer A buffer into which the execution times will be - * written, in ascii form. This buffer is assumed to be large enough to - * contain the generated report. Approximately 40 bytes per task should - * be sufficient. - * - * \page vTaskGetRunTimeStats vTaskGetRunTimeStats - * \ingroup TaskUtils - */ -void vTaskGetRunTimeStats( signed char *pcWriteBuffer ) PRIVILEGED_FUNCTION; - -/** - * task. h - *
void vTaskStartTrace( char * pcBuffer, unsigned portBASE_TYPE uxBufferSize );
- * - * Starts a real time kernel activity trace. The trace logs the identity of - * which task is running when. - * - * The trace file is stored in binary format. A separate DOS utility called - * convtrce.exe is used to convert this into a tab delimited text file which - * can be viewed and plotted in a spread sheet. - * - * @param pcBuffer The buffer into which the trace will be written. - * - * @param ulBufferSize The size of pcBuffer in bytes. The trace will continue - * until either the buffer in full, or ulTaskEndTrace () is called. - * - * \page vTaskStartTrace vTaskStartTrace - * \ingroup TaskUtils - */ -void vTaskStartTrace( signed char * pcBuffer, unsigned long ulBufferSize ) PRIVILEGED_FUNCTION; - -/** - * task. h - *
unsigned long ulTaskEndTrace( void );
- * - * Stops a kernel activity trace. See vTaskStartTrace (). - * - * @return The number of bytes that have been written into the trace buffer. - * - * \page usTaskEndTrace usTaskEndTrace - * \ingroup TaskUtils - */ -unsigned long ulTaskEndTrace( void ) PRIVILEGED_FUNCTION; - -/** - * task.h - *
unsigned portBASE_TYPE uxTaskGetStackHighWaterMark( xTaskHandle xTask );
- * - * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for - * this function to be available. - * - * Returns the high water mark of the stack associated with xTask. That is, - * the minimum free stack space there has been (in bytes) since the task - * started. The smaller the returned number the closer the task has come - * to overflowing its stack. - * - * @param xTask Handle of the task associated with the stack to be checked. - * Set xTask to NULL to check the stack of the calling task. - * - * @return The smallest amount of free stack space there has been (in bytes) - * since the task referenced by xTask was created. - */ -unsigned portBASE_TYPE uxTaskGetStackHighWaterMark( xTaskHandle xTask ) PRIVILEGED_FUNCTION; - -/** - * task.h - *
void vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxHookFunction );
- * - * Sets pxHookFunction to be the task hook function used by the task xTask. - * Passing xTask as NULL has the effect of setting the calling tasks hook - * function. - */ -void vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxHookFunction ) PRIVILEGED_FUNCTION; - -/** - * task.h - *
void xTaskGetApplicationTaskTag( xTaskHandle xTask );
- * - * Returns the pxHookFunction value assigned to the task xTask. - */ -pdTASK_HOOK_CODE xTaskGetApplicationTaskTag( xTaskHandle xTask ) PRIVILEGED_FUNCTION; - -/** - * task.h - *
portBASE_TYPE xTaskCallApplicationTaskHook( xTaskHandle xTask, pdTASK_HOOK_CODE pxHookFunction );
- * - * Calls the hook function associated with xTask. Passing xTask as NULL has - * the effect of calling the Running tasks (the calling task) hook function. - * - * pvParameter is passed to the hook function for the task to interpret as it - * wants. - */ -portBASE_TYPE xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter ) PRIVILEGED_FUNCTION; - - -/*----------------------------------------------------------- - * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES - *----------------------------------------------------------*/ - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY - * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS - * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * Called from the real time kernel tick (either preemptive or cooperative), - * this increments the tick count and checks if any tasks that are blocked - * for a finite period required removing from a blocked list and placing on - * a ready list. - */ -void vTaskIncrementTick( void ) PRIVILEGED_FUNCTION; - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. - * - * Removes the calling task from the ready list and places it both - * on the list of tasks waiting for a particular event, and the - * list of delayed tasks. The task will be removed from both lists - * and replaced on the ready list should either the event occur (and - * there be no higher priority tasks waiting on the same event) or - * the delay period expires. - * - * @param pxEventList The list containing tasks that are blocked waiting - * for the event to occur. - * - * @param xTicksToWait The maximum amount of time that the task should wait - * for the event to occur. This is specified in kernel ticks,the constant - * portTICK_RATE_MS can be used to convert kernel ticks into a real time - * period. - */ -void vTaskPlaceOnEventList( const xList * const pxEventList, portTickType xTicksToWait ) PRIVILEGED_FUNCTION; - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. - * - * Removes a task from both the specified event list and the list of blocked - * tasks, and places it on a ready queue. - * - * xTaskRemoveFromEventList () will be called if either an event occurs to - * unblock a task, or the block timeout period expires. - * - * @return pdTRUE if the task being removed has a higher priority than the task - * making the call, otherwise pdFALSE. - */ -signed portBASE_TYPE xTaskRemoveFromEventList( const xList * const pxEventList ) PRIVILEGED_FUNCTION; - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * INCLUDE_vTaskCleanUpResources and INCLUDE_vTaskSuspend must be defined as 1 - * for this function to be available. - * See the configuration section for more information. - * - * Empties the ready and delayed queues of task control blocks, freeing the - * memory allocated for the task control block and task stacks as it goes. - */ -void vTaskCleanUpResources( void ) PRIVILEGED_FUNCTION; - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY - * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS - * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * Sets the pointer to the current TCB to the TCB of the highest priority task - * that is ready to run. - */ -void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION; - -/* - * Return the handle of the calling task. - */ -xTaskHandle xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION; - -/* - * Capture the current time status for future reference. - */ -void vTaskSetTimeOutState( xTimeOutType * const pxTimeOut ) PRIVILEGED_FUNCTION; - -/* - * Compare the time status now with that previously captured to see if the - * timeout has expired. - */ -portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType * const pxTimeOut, portTickType * const pxTicksToWait ) PRIVILEGED_FUNCTION; - -/* - * Shortcut used by the queue implementation to prevent unnecessary call to - * taskYIELD(); - */ -void vTaskMissedYield( void ) PRIVILEGED_FUNCTION; - -/* - * Returns the scheduler state as taskSCHEDULER_RUNNING, - * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED. - */ -portBASE_TYPE xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION; - -/* - * Raises the priority of the mutex holder to that of the calling task should - * the mutex holder have a priority less than the calling task. - */ -void vTaskPriorityInherit( xTaskHandle * const pxMutexHolder ) PRIVILEGED_FUNCTION; - -/* - * Set the priority of a task back to its proper priority in the case that it - * inherited a higher priority while it was holding a semaphore. - */ -void vTaskPriorityDisinherit( xTaskHandle * const pxMutexHolder ) PRIVILEGED_FUNCTION; - -/* - * Generic version of the task creation function which is in turn called by the - * xTaskCreate() and xTaskCreateProtected() macros. - */ -signed portBASE_TYPE xTaskGenericCreate( pdTASK_CODE pvTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions ) PRIVILEGED_FUNCTION; - -#ifdef __cplusplus -} -#endif -#endif /* TASK_H */ - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/list.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/list.c deleted file mode 100644 index 0a12ff299..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/list.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - - -#include -#include "FreeRTOS.h" -#include "list.h" - -/*----------------------------------------------------------- - * PUBLIC LIST API documented in list.h - *----------------------------------------------------------*/ - -void vListInitialise( xList *pxList ) -{ - /* The list structure contains a list item which is used to mark the - end of the list. To initialise the list the list end is inserted - as the only list entry. */ - pxList->pxIndex = ( xListItem * ) &( pxList->xListEnd ); - - /* The list end value is the highest possible value in the list to - ensure it remains at the end of the list. */ - pxList->xListEnd.xItemValue = portMAX_DELAY; - - /* The list end next and previous pointers point to itself so we know - when the list is empty. */ - pxList->xListEnd.pxNext = ( xListItem * ) &( pxList->xListEnd ); - pxList->xListEnd.pxPrevious = ( xListItem * ) &( pxList->xListEnd ); - - pxList->uxNumberOfItems = 0; -} -/*-----------------------------------------------------------*/ - -void vListInitialiseItem( xListItem *pxItem ) -{ - /* Make sure the list item is not recorded as being on a list. */ - pxItem->pvContainer = NULL; -} -/*-----------------------------------------------------------*/ - -void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ) -{ -volatile xListItem * pxIndex; - - /* Insert a new list item into pxList, but rather than sort the list, - makes the new list item the last item to be removed by a call to - pvListGetOwnerOfNextEntry. This means it has to be the item pointed to by - the pxIndex member. */ - pxIndex = pxList->pxIndex; - - pxNewListItem->pxNext = pxIndex->pxNext; - pxNewListItem->pxPrevious = pxList->pxIndex; - pxIndex->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; - pxIndex->pxNext = ( volatile xListItem * ) pxNewListItem; - pxList->pxIndex = ( volatile xListItem * ) pxNewListItem; - - /* Remember which list the item is in. */ - pxNewListItem->pvContainer = ( void * ) pxList; - - ( pxList->uxNumberOfItems )++; -} -/*-----------------------------------------------------------*/ - -void vListInsert( xList *pxList, xListItem *pxNewListItem ) -{ -volatile xListItem *pxIterator; -portTickType xValueOfInsertion; - - /* Insert the new list item into the list, sorted in ulListItem order. */ - xValueOfInsertion = pxNewListItem->xItemValue; - - /* If the list already contains a list item with the same item value then - the new list item should be placed after it. This ensures that TCB's which - are stored in ready lists (all of which have the same ulListItem value) - get an equal share of the CPU. However, if the xItemValue is the same as - the back marker the iteration loop below will not end. This means we need - to guard against this by checking the value first and modifying the - algorithm slightly if necessary. */ - if( xValueOfInsertion == portMAX_DELAY ) - { - pxIterator = pxList->xListEnd.pxPrevious; - } - else - { - /* *** NOTE *********************************************************** - If you find your application is crashing here then likely causes are: - 1) Stack overflow - - see http://www.freertos.org/Stacks-and-stack-overflow-checking.html - 2) Incorrect interrupt priority assignment, especially on Cortex M3 - parts where numerically high priority values denote low actual - interrupt priories, which can seem counter intuitive. See - configMAX_SYSCALL_INTERRUPT_PRIORITY on http://www.freertos.org/a00110.html - 3) Calling an API function from within a critical section or when - the scheduler is suspended. - 4) Using a queue or semaphore before it has been initialised or - before the scheduler has been started (are interrupts firing - before vTaskStartScheduler() has been called?). - See http://www.freertos.org/FAQHelp.html for more tips. - **********************************************************************/ - - for( pxIterator = ( xListItem * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) - { - /* There is nothing to do here, we are just iterating to the - wanted insertion position. */ - } - } - - pxNewListItem->pxNext = pxIterator->pxNext; - pxNewListItem->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; - pxNewListItem->pxPrevious = pxIterator; - pxIterator->pxNext = ( volatile xListItem * ) pxNewListItem; - - /* Remember which list the item is in. This allows fast removal of the - item later. */ - pxNewListItem->pvContainer = ( void * ) pxList; - - ( pxList->uxNumberOfItems )++; -} -/*-----------------------------------------------------------*/ - -void vListRemove( xListItem *pxItemToRemove ) -{ -xList * pxList; - - pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; - pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; - - /* The list item knows which list it is in. Obtain the list from the list - item. */ - pxList = ( xList * ) pxItemToRemove->pvContainer; - - /* Make sure the index is left pointing to a valid item. */ - if( pxList->pxIndex == pxItemToRemove ) - { - pxList->pxIndex = pxItemToRemove->pxPrevious; - } - - pxItemToRemove->pvContainer = NULL; - ( pxList->uxNumberOfItems )--; -} -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/GCC/ARM_CM3/port.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/GCC/ARM_CM3/port.c deleted file mode 100644 index ae018c43c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/GCC/ARM_CM3/port.c +++ /dev/null @@ -1,280 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ARM CM3 port. - *----------------------------------------------------------*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is -defined. The value should also ensure backward compatibility. -FreeRTOS.org versions prior to V4.4.0 did not include this definition. */ -#ifndef configKERNEL_INTERRUPT_PRIORITY - #define configKERNEL_INTERRUPT_PRIORITY 255 -#endif - -/* Constants required to manipulate the NVIC. */ -#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long *) 0xe000e010 ) -#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long *) 0xe000e014 ) -#define portNVIC_INT_CTRL ( ( volatile unsigned long *) 0xe000ed04 ) -#define portNVIC_SYSPRI2 ( ( volatile unsigned long *) 0xe000ed20 ) -#define portNVIC_SYSTICK_CLK 0x00000004 -#define portNVIC_SYSTICK_INT 0x00000002 -#define portNVIC_SYSTICK_ENABLE 0x00000001 -#define portNVIC_PENDSVSET 0x10000000 -#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 ) -#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 ) - -/* Constants required to set up the initial stack. */ -#define portINITIAL_XPSR ( 0x01000000 ) - -/* The priority used by the kernel is assigned to a variable to make access -from inline assembler easier. */ -const unsigned long ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY; - -/* Each task maintains its own interrupt status in the critical nesting -variable. */ -static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa; - -/* - * Setup the timer to generate the tick interrupts. - */ -static void prvSetupTimerInterrupt( void ); - -/* - * Exception handlers. - */ -void xPortPendSVHandler( void ) __attribute__ (( naked )); -void xPortSysTickHandler( void ); -void vPortSVCHandler( void ) __attribute__ (( naked )); - -/* - * Start first task is a separate function so it can be tested in isolation. - */ -void vPortStartFirstTask( void ) __attribute__ (( naked )); - -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ - /* Simulate the stack frame as it would be created by a context switch - interrupt. */ - *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */ - pxTopOfStack--; - *pxTopOfStack = 0; /* LR */ - pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -void vPortSVCHandler( void ) -{ - __asm volatile ( - " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */ - " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ - " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ - " ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ - " msr psp, r0 \n" /* Restore the task stack pointer. */ - " mov r0, #0 \n" - " msr basepri, r0 \n" - " orr r14, #0xd \n" - " bx r14 \n" - " \n" - " .align 2 \n" - "pxCurrentTCBConst2: .word pxCurrentTCB \n" - ); -} -/*-----------------------------------------------------------*/ - -void vPortStartFirstTask( void ) -{ - __asm volatile( - " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ - " ldr r0, [r0] \n" - " ldr r0, [r0] \n" - " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ - " svc 0 \n" /* System call to start first task. */ - ); -} -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */ - *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI; - *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI; - - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Initialise the critical nesting count ready for the first task. */ - uxCriticalNesting = 0; - - /* Start the first task. */ - vPortStartFirstTask(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the CM3 port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -void vPortYieldFromISR( void ) -{ - /* Set a PendSV to request a context switch. */ - *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; -} -/*-----------------------------------------------------------*/ - -void vPortEnterCritical( void ) -{ - portDISABLE_INTERRUPTS(); - uxCriticalNesting++; -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) -{ - uxCriticalNesting--; - if( uxCriticalNesting == 0 ) - { - portENABLE_INTERRUPTS(); - } -} -/*-----------------------------------------------------------*/ - -void xPortPendSVHandler( void ) -{ - /* This is a naked function. */ - - __asm volatile - ( - " mrs r0, psp \n" - " \n" - " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */ - " ldr r2, [r3] \n" - " \n" - " stmdb r0!, {r4-r11} \n" /* Save the remaining registers. */ - " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */ - " \n" - " stmdb sp!, {r3, r14} \n" - " mov r0, %0 \n" - " msr basepri, r0 \n" - " bl vTaskSwitchContext \n" - " mov r0, #0 \n" - " msr basepri, r0 \n" - " ldmia sp!, {r3, r14} \n" - " \n" /* Restore the context, including the critical nesting count. */ - " ldr r1, [r3] \n" - " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */ - " ldmia r0!, {r4-r11} \n" /* Pop the registers. */ - " msr psp, r0 \n" - " bx r14 \n" - " \n" - " .align 2 \n" - "pxCurrentTCBConst: .word pxCurrentTCB \n" - ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) - ); -} -/*-----------------------------------------------------------*/ - -void xPortSysTickHandler( void ) -{ -unsigned long ulDummy; - - /* If using preemption, also force a context switch. */ - #if configUSE_PREEMPTION == 1 - *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; - #endif - - ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); - { - vTaskIncrementTick(); - } - portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); -} -/*-----------------------------------------------------------*/ - -/* - * Setup the systick timer to generate the tick interrupts at the required - * frequency. - */ -void prvSetupTimerInterrupt( void ) -{ - /* Configure SysTick to interrupt at the requested rate. */ - *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; - *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; -} -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/GCC/ARM_CM3/portmacro.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/GCC/ARM_CM3/portmacro.h deleted file mode 100644 index 13d0e82c1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/GCC/ARM_CM3/portmacro.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE long - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -/*-----------------------------------------------------------*/ - - -/* Scheduler utilities. */ -extern void vPortYieldFromISR( void ); - -#define portYIELD() vPortYieldFromISR() - -#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR() -/*-----------------------------------------------------------*/ - - -/* Critical section management. */ - -/* - * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other - * registers. r0 is clobbered. - */ -#define portSET_INTERRUPT_MASK() \ - __asm volatile \ - ( \ - " mov r0, %0 \n" \ - " msr basepri, r0 \n" \ - ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY):"r0" \ - ) - -/* - * Set basepri back to 0 without effective other registers. - * r0 is clobbered. - */ -#define portCLEAR_INTERRUPT_MASK() \ - __asm volatile \ - ( \ - " mov r0, #0 \n" \ - " msr basepri, r0 \n" \ - :::"r0" \ - ) - -#define portSET_INTERRUPT_MASK_FROM_ISR() 0;portSET_INTERRUPT_MASK() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) portCLEAR_INTERRUPT_MASK();(void)x - - -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK() -#define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK() -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#define portNOP() - -#ifdef __cplusplus -} -#endif - -#endif /* PORTMACRO_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/GCC/ARM_CM3_MPU/port.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/GCC/ARM_CM3_MPU/port.c deleted file mode 100644 index b75f601e5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/GCC/ARM_CM3_MPU/port.c +++ /dev/null @@ -1,1057 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ARM CM3 port. - *----------------------------------------------------------*/ - -/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining -all the API functions to use the MPU wrappers. That should only be done when -task.h is included from an application file. */ -#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE - -/* Constants required to access and manipulate the NVIC. */ -#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long * ) 0xe000e010 ) -#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long * ) 0xe000e014 ) -#define portNVIC_SYSPRI2 ( ( volatile unsigned long * ) 0xe000ed20 ) -#define portNVIC_SYSPRI1 ( ( volatile unsigned long * ) 0xe000ed1c ) -#define portNVIC_SYS_CTRL_STATE ( ( volatile unsigned long * ) 0xe000ed24 ) -#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL ) - -/* Constants required to access and manipulate the MPU. */ -#define portMPU_TYPE ( ( volatile unsigned long * ) 0xe000ed90 ) -#define portMPU_REGION_BASE_ADDRESS ( ( volatile unsigned long * ) 0xe000ed9C ) -#define portMPU_REGION_ATTRIBUTE ( ( volatile unsigned long * ) 0xe000edA0 ) -#define portMPU_CTRL ( ( volatile unsigned long * ) 0xe000ed94 ) -#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */ -#define portMPU_ENABLE ( 0x01UL ) -#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL ) -#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL ) -#define portMPU_REGION_VALID ( 0x10UL ) -#define portMPU_REGION_ENABLE ( 0x01UL ) -#define portPERIPHERALS_START_ADDRESS 0x40000000UL -#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL - -/* Constants required to access and manipulate the SysTick. */ -#define portNVIC_SYSTICK_CLK ( 0x00000004UL ) -#define portNVIC_SYSTICK_INT ( 0x00000002UL ) -#define portNVIC_SYSTICK_ENABLE ( 0x00000001UL ) -#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) -#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) -#define portNVIC_SVC_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) - -/* Constants required to set up the initial stack. */ -#define portINITIAL_XPSR ( 0x01000000 ) -#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 ) -#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 ) - -/* Offsets in the stack to the parameters when inside the SVC handler. */ -#define portOFFSET_TO_PC ( 6 ) - -/* Set the privilege level to user mode if xRunningPrivileged is false. */ -#define portRESET_PRIVILEGE( xRunningPrivileged ) if( xRunningPrivileged != pdTRUE ) __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ) - -/* Each task maintains its own interrupt status in the critical nesting -variable. Note this is not saved as part of the task context as context -switches can only occur when uxCriticalNesting is zero. */ -static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa; - -/* - * Setup the timer to generate the tick interrupts. - */ -static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION; - -/* - * Configure a number of standard MPU regions that are used by all tasks. - */ -static void prvSetupMPU( void ) PRIVILEGED_FUNCTION; - -/* - * Return the smallest MPU region size that a given number of bytes will fit - * into. The region size is returned as the value that should be programmed - * into the region attribute register for that region. - */ -static unsigned long prvGetMPURegionSizeSetting( unsigned long ulActualSizeInBytes ) PRIVILEGED_FUNCTION; - -/* - * Checks to see if being called from the context of an unprivileged task, and - * if so raises the privilege level and returns false - otherwise does nothing - * other than return true. - */ -static portBASE_TYPE prvRaisePrivilege( void ) __attribute__(( naked )); - -/* - * Standard FreeRTOS exception handlers. - */ -void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; -void xPortSysTickHandler( void ) __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION; -void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION; - -/* - * Starts the scheduler by restoring the context of the first task to run. - */ -static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION; - -/* - * C portion of the SVC handler. The SVC handler is split between an asm entry - * and a C wrapper for simplicity of coding and maintenance. - */ -static void prvSVCHandler( unsigned long *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION; - -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters, portBASE_TYPE xRunPrivileged ) -{ - /* Simulate the stack frame as it would be created by a context switch - interrupt. */ - *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */ - pxTopOfStack--; - *pxTopOfStack = 0; /* LR */ - pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ - - if( xRunPrivileged == pdTRUE ) - { - *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED; - } - else - { - *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED; - } - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -void vPortSVCHandler( void ) -{ - /* Assumes psp was in use. */ - __asm volatile - ( - #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */ - " tst lr, #4 \n" - " ite eq \n" - " mrseq r0, msp \n" - " mrsne r0, psp \n" - #else - " mrs r0, psp \n" - #endif - " b prvSVCHandler \n" - :::"r0" - ); - - /* This will never get executed, but is required to prevent prvSVCHandler - being removed by the optimiser. */ - prvSVCHandler( NULL ); -} -/*-----------------------------------------------------------*/ - -static void prvSVCHandler( unsigned long *pulParam ) -{ -unsigned char ucSVCNumber; - - /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and - xPSR. The first argument (r0) is pulParam[ 0 ]. */ - ucSVCNumber = ( ( unsigned char * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ]; - switch( ucSVCNumber ) - { - case portSVC_START_SCHEDULER : *(portNVIC_SYSPRI1) |= portNVIC_SVC_PRI; - prvRestoreContextOfFirstTask(); - break; - - case portSVC_YIELD : *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; - break; - - case portSVC_prvRaisePrivilege : __asm volatile - ( - " mrs r1, control \n" /* Obtain current control value. */ - " bic r1, #1 \n" /* Set privilege bit. */ - " msr control, r1 \n" /* Write back new control value. */ - :::"r1" - ); - break; - - default : /* Unknown SVC call. */ - break; - } -} -/*-----------------------------------------------------------*/ - -static void prvRestoreContextOfFirstTask( void ) -{ - __asm volatile - ( - " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */ - " ldr r0, [r0] \n" - " ldr r0, [r0] \n" - " msr msp, r0 \n" /* Set the msp back to the start of the stack. */ - " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */ - " ldr r1, [r3] \n" - " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */ - " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */ - " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */ - " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */ - " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */ - " ldmia r0!, {r3, r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry. */ - " msr control, r3 \n" - " msr psp, r0 \n" /* Restore the task stack pointer. */ - " mov r0, #0 \n" - " msr basepri, r0 \n" - " ldr r14, =0xfffffffd \n" /* Load exec return code. */ - " bx r14 \n" - " \n" - " .align 2 \n" - "pxCurrentTCBConst2: .word pxCurrentTCB \n" - ); -} -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Make PendSV and SysTick the same priroity as the kernel. */ - *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI; - *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI; - - /* Configure the regions in the MPU that are common to all tasks. */ - prvSetupMPU(); - - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Initialise the critical nesting count ready for the first task. */ - uxCriticalNesting = 0; - - /* Start the first task. */ - __asm volatile( " svc %0 \n" - :: "i" (portSVC_START_SCHEDULER) ); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the CM3 port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -void vPortEnterCritical( void ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - portDISABLE_INTERRUPTS(); - uxCriticalNesting++; - - portRESET_PRIVILEGE( xRunningPrivileged ); -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - uxCriticalNesting--; - if( uxCriticalNesting == 0 ) - { - portENABLE_INTERRUPTS(); - } - portRESET_PRIVILEGE( xRunningPrivileged ); -} -/*-----------------------------------------------------------*/ - -void xPortPendSVHandler( void ) -{ - /* This is a naked function. */ - - __asm volatile - ( - " mrs r0, psp \n" - " \n" - " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */ - " ldr r2, [r3] \n" - " \n" - " mrs r1, control \n" - " stmdb r0!, {r1, r4-r11} \n" /* Save the remaining registers. */ - " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */ - " \n" - " stmdb sp!, {r3, r14} \n" - " mov r0, %0 \n" - " msr basepri, r0 \n" - " bl vTaskSwitchContext \n" - " mov r0, #0 \n" - " msr basepri, r0 \n" - " ldmia sp!, {r3, r14} \n" - " \n" /* Restore the context. */ - " ldr r1, [r3] \n" - " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */ - " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */ - " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */ - " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */ - " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */ - " ldmia r0!, {r3, r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry. */ - " msr control, r3 \n" - " \n" - " msr psp, r0 \n" - " bx r14 \n" - " \n" - " .align 2 \n" - "pxCurrentTCBConst: .word pxCurrentTCB \n" - ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) - ); -} -/*-----------------------------------------------------------*/ - -void xPortSysTickHandler( void ) -{ -unsigned long ulDummy; - - /* If using preemption, also force a context switch. */ - #if configUSE_PREEMPTION == 1 - *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; - #endif - - ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); - { - vTaskIncrementTick(); - } - portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); -} -/*-----------------------------------------------------------*/ - -/* - * Setup the systick timer to generate the tick interrupts at the required - * frequency. - */ -static void prvSetupTimerInterrupt( void ) -{ - /* Configure SysTick to interrupt at the requested rate. */ - *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; - *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; -} -/*-----------------------------------------------------------*/ - -static void prvSetupMPU( void ) -{ -extern unsigned long __privileged_functions_end__[]; -extern unsigned long __FLASH_segment_start__[]; -extern unsigned long __FLASH_segment_end__[]; -extern unsigned long __privileged_data_start__[]; -extern unsigned long __privileged_data_end__[]; - - /* Check the expected MPU is present. */ - if( *portMPU_TYPE == portEXPECTED_MPU_TYPE_VALUE ) - { - /* First setup the entire flash for unprivileged read only access. */ - *portMPU_REGION_BASE_ADDRESS = ( ( unsigned long ) __FLASH_segment_start__ ) | /* Base address. */ - ( portMPU_REGION_VALID ) | - ( portUNPRIVILEGED_FLASH_REGION ); - - *portMPU_REGION_ATTRIBUTE = ( portMPU_REGION_READ_ONLY ) | - ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | - ( prvGetMPURegionSizeSetting( ( unsigned long ) __FLASH_segment_end__ - ( unsigned long ) __FLASH_segment_start__ ) ) | - ( portMPU_REGION_ENABLE ); - - /* Setup the first 16K for privileged only access (even though less - than 10K is actually being used). This is where the kernel code is - placed. */ - *portMPU_REGION_BASE_ADDRESS = ( ( unsigned long ) __FLASH_segment_start__ ) | /* Base address. */ - ( portMPU_REGION_VALID ) | - ( portPRIVILEGED_FLASH_REGION ); - - *portMPU_REGION_ATTRIBUTE = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) | - ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | - ( prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_functions_end__ - ( unsigned long ) __FLASH_segment_start__ ) ) | - ( portMPU_REGION_ENABLE ); - - /* Setup the privileged data RAM region. This is where the kernel data - is placed. */ - *portMPU_REGION_BASE_ADDRESS = ( ( unsigned long ) __privileged_data_start__ ) | /* Base address. */ - ( portMPU_REGION_VALID ) | - ( portPRIVILEGED_RAM_REGION ); - - *portMPU_REGION_ATTRIBUTE = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | - ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | - prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_data_end__ - ( unsigned long ) __privileged_data_start__ ) | - ( portMPU_REGION_ENABLE ); - - /* By default allow everything to access the general peripherals. The - system peripherals and registers are protected. */ - *portMPU_REGION_BASE_ADDRESS = ( portPERIPHERALS_START_ADDRESS ) | - ( portMPU_REGION_VALID ) | - ( portGENERAL_PERIPHERALS_REGION ); - - *portMPU_REGION_ATTRIBUTE = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) | - ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) | - ( portMPU_REGION_ENABLE ); - - /* Enable the memory fault exception. */ - *portNVIC_SYS_CTRL_STATE |= portNVIC_MEM_FAULT_ENABLE; - - /* Enable the MPU with the background region configured. */ - *portMPU_CTRL |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE ); - } -} -/*-----------------------------------------------------------*/ - -static unsigned long prvGetMPURegionSizeSetting( unsigned long ulActualSizeInBytes ) -{ -unsigned long ulRegionSize, ulReturnValue = 4; - - /* 32 is the smallest region size, 31 is the largest valid value for - ulReturnValue. */ - for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) ) - { - if( ulActualSizeInBytes <= ulRegionSize ) - { - break; - } - else - { - ulReturnValue++; - } - } - - /* Shift the code by one before returning so it can be written directly - into the the correct bit position of the attribute register. */ - return ( ulReturnValue << 1UL ); -} -/*-----------------------------------------------------------*/ - -static portBASE_TYPE prvRaisePrivilege( void ) -{ - __asm volatile - ( - " mrs r0, control \n" - " tst r0, #1 \n" /* Is the task running privileged? */ - " itte ne \n" - " movne r0, #0 \n" /* CONTROL[0]!=0, return false. */ - " svcne %0 \n" /* Switch to privileged. */ - " moveq r0, #1 \n" /* CONTROL[0]==0, return true. */ - " bx lr \n" - :: "i" (portSVC_prvRaisePrivilege) : "r0" - ); - - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, portSTACK_TYPE *pxBottomOfStack, unsigned short usStackDepth ) -{ -extern unsigned long __SRAM_segment_start__[]; -extern unsigned long __SRAM_segment_end__[]; -extern unsigned long __privileged_data_start__[]; -extern unsigned long __privileged_data_end__[]; -long lIndex; -unsigned long ul; - - if( xRegions == NULL ) - { - /* No MPU regions are specified so allow access to all RAM. */ - xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = - ( ( unsigned long ) __SRAM_segment_start__ ) | /* Base address. */ - ( portMPU_REGION_VALID ) | - ( portSTACK_REGION ); - - xMPUSettings->xRegion[ 0 ].ulRegionAttribute = - ( portMPU_REGION_READ_WRITE ) | - ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | - ( prvGetMPURegionSizeSetting( ( unsigned long ) __SRAM_segment_end__ - ( unsigned long ) __SRAM_segment_start__ ) ) | - ( portMPU_REGION_ENABLE ); - - /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have - just removed the privileged only parameters. */ - xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress = - ( ( unsigned long ) __privileged_data_start__ ) | /* Base address. */ - ( portMPU_REGION_VALID ) | - ( portSTACK_REGION + 1 ); - - xMPUSettings->xRegion[ 1 ].ulRegionAttribute = - ( portMPU_REGION_PRIVILEGED_READ_WRITE ) | - ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | - prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_data_end__ - ( unsigned long ) __privileged_data_start__ ) | - ( portMPU_REGION_ENABLE ); - - /* Invalidate all other regions. */ - for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) - { - xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID; - xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; - } - } - else - { - /* This function is called automatically when the task is created - in - which case the stack region parameters will be valid. At all other - times the stack parameters will not be valid and it is assumed that the - stack region has already been configured. */ - if( usStackDepth > 0 ) - { - /* Define the region that allows access to the stack. */ - xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress = - ( ( unsigned long ) pxBottomOfStack ) | - ( portMPU_REGION_VALID ) | - ( portSTACK_REGION ); /* Region number. */ - - xMPUSettings->xRegion[ 0 ].ulRegionAttribute = - ( portMPU_REGION_READ_WRITE ) | /* Read and write. */ - ( prvGetMPURegionSizeSetting( ( unsigned long ) usStackDepth * ( unsigned long ) sizeof( portSTACK_TYPE ) ) ) | - ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | - ( portMPU_REGION_ENABLE ); - } - - lIndex = 0; - - for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ ) - { - if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL ) - { - /* Translate the generic region definition contained in - xRegions into the CM3 specific MPU settings that are then - stored in xMPUSettings. */ - xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = - ( ( unsigned long ) xRegions[ lIndex ].pvBaseAddress ) | - ( portMPU_REGION_VALID ) | - ( portSTACK_REGION + ul ); /* Region number. */ - - xMPUSettings->xRegion[ ul ].ulRegionAttribute = - ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) | - ( xRegions[ lIndex ].ulParameters ) | - ( portMPU_REGION_ENABLE ); - } - else - { - /* Invalidate the region. */ - xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID; - xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL; - } - - lIndex++; - } - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE MPU_xTaskGenericCreate( pdTASK_CODE pvTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions ) -{ -signed portBASE_TYPE xReturn; -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xTaskGenericCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask, puxStackBuffer, xRegions ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; -} -/*-----------------------------------------------------------*/ - -void MPU_vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const xRegions ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskAllocateMPURegions( xTask, xRegions ); - portRESET_PRIVILEGE( xRunningPrivileged ); -} -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelete == 1 ) - void MPU_vTaskDelete( xTaskHandle pxTaskToDelete ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskDelete( pxTaskToDelete ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelayUntil == 1 ) - void MPU_vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelay == 1 ) - void MPU_vTaskDelay( portTickType xTicksToDelay ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskDelay( xTicksToDelay ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_uxTaskPriorityGet == 1 ) - unsigned portBASE_TYPE MPU_uxTaskPriorityGet( xTaskHandle pxTask ) - { - unsigned portBASE_TYPE uxReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - uxReturn = uxTaskPriorityGet( pxTask ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return uxReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskPrioritySet == 1 ) - void MPU_vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskPrioritySet( pxTask, uxNewPriority ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - void MPU_vTaskSuspend( xTaskHandle pxTaskToSuspend ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskSuspend( pxTaskToSuspend ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - signed portBASE_TYPE MPU_xTaskIsTaskSuspended( xTaskHandle xTask ) - { - signed portBASE_TYPE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xTaskIsTaskSuspended( xTask ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - void MPU_vTaskResume( xTaskHandle pxTaskToResume ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskResume( pxTaskToResume ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -void MPU_vTaskSuspendAll( void ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskSuspendAll(); - portRESET_PRIVILEGE( xRunningPrivileged ); -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE MPU_xTaskResumeAll( void ) -{ -signed portBASE_TYPE xReturn; -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xTaskResumeAll(); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; -} -/*-----------------------------------------------------------*/ - -portTickType MPU_xTaskGetTickCount( void ) -{ -portTickType xReturn; -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xTaskGetTickCount(); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE MPU_uxTaskGetNumberOfTasks( void ) -{ -unsigned portBASE_TYPE uxReturn; -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - uxReturn = uxTaskGetNumberOfTasks(); - portRESET_PRIVILEGE( xRunningPrivileged ); - return uxReturn; -} -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - void MPU_vTaskList( signed char *pcWriteBuffer ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskList( pcWriteBuffer ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configGENERATE_RUN_TIME_STATS == 1 ) - void MPU_vTaskGetRunTimeStats( signed char *pcWriteBuffer ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskGetRunTimeStats( pcWriteBuffer ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - void MPU_vTaskStartTrace( signed char * pcBuffer, unsigned long ulBufferSize ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskStartTrace( pcBuffer, ulBufferSize ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - unsigned long MPU_ulTaskEndTrace( void ) - { - unsigned long ulReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - ulReturn = ulTaskEndTrace(); - portRESET_PRIVILEGE( xRunningPrivileged ); - return ulReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_APPLICATION_TASK_TAG == 1 ) - void MPU_vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxTagValue ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vTaskSetApplicationTaskTag( xTask, pxTagValue ); - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_APPLICATION_TASK_TAG == 1 ) - pdTASK_HOOK_CODE MPU_xTaskGetApplicationTaskTag( xTaskHandle xTask ) - { - pdTASK_HOOK_CODE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xTaskGetApplicationTaskTag( xTask ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_APPLICATION_TASK_TAG == 1 ) - portBASE_TYPE MPU_xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter ) - { - portBASE_TYPE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) - unsigned portBASE_TYPE MPU_uxTaskGetStackHighWaterMark( xTaskHandle xTask ) - { - unsigned portBASE_TYPE uxReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - uxReturn = uxTaskGetStackHighWaterMark( xTask ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return uxReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) - xTaskHandle MPU_xTaskGetCurrentTaskHandle( void ) - { - xTaskHandle xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xTaskGetCurrentTaskHandle(); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_xTaskGetSchedulerState == 1 ) - portBASE_TYPE MPU_xTaskGetSchedulerState( void ) - { - portBASE_TYPE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xTaskGetSchedulerState(); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -xQueueHandle MPU_xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ) -{ -xQueueHandle xReturn; -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueCreate( uxQueueLength, uxItemSize ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE MPU_xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ) -{ -signed portBASE_TYPE xReturn; -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE MPU_uxQueueMessagesWaiting( const xQueueHandle pxQueue ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); -unsigned portBASE_TYPE uxReturn; - - uxReturn = uxQueueMessagesWaiting( pxQueue ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return uxReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE MPU_xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); -signed portBASE_TYPE xReturn; - - xReturn = xQueueGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if ( configUSE_MUTEXES == 1 ) - xQueueHandle MPU_xQueueCreateMutex( void ) - { - xQueueHandle xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueCreateMutex(); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_COUNTING_SEMAPHORES == 1 - xQueueHandle MPU_xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount ) - { - xQueueHandle xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueHandle xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_MUTEXES == 1 ) - portBASE_TYPE MPU_xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime ) - { - portBASE_TYPE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_MUTEXES == 1 ) - portBASE_TYPE MPU_xQueueGiveMutexRecursive( xQueueHandle xMutex ) - { - portBASE_TYPE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueGiveMutexRecursive( xMutex ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_ALTERNATIVE_API == 1 - signed portBASE_TYPE MPU_xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ) - { - signed portBASE_TYPE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = signed portBASE_TYPE xQueueAltGenericSend( pxQueue, pvItemToQueue, xTicksToWait, xCopyPosition ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_ALTERNATIVE_API == 1 - signed portBASE_TYPE MPU_xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ) - { - signed portBASE_TYPE xReturn; - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xQueueAltGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking ); - portRESET_PRIVILEGE( xRunningPrivileged ); - return xReturn; - } -#endif -/*-----------------------------------------------------------*/ - -#if configQUEUE_REGISTRY_SIZE > 0 - void MPU_vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcName ) - { - portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vQueueAddToRegistry( xQueue, pcName ); - - portRESET_PRIVILEGE( xRunningPrivileged ); - } -#endif -/*-----------------------------------------------------------*/ - -void *MPU_pvPortMalloc( size_t xSize ) -{ -void *pvReturn; -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - pvReturn = pvPortMalloc( xSize ); - - portRESET_PRIVILEGE( xRunningPrivileged ); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void MPU_vPortFree( void *pv ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vPortFree( pv ); - - portRESET_PRIVILEGE( xRunningPrivileged ); -} -/*-----------------------------------------------------------*/ - -void MPU_vPortInitialiseBlocks( void ) -{ -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - vPortInitialiseBlocks(); - - portRESET_PRIVILEGE( xRunningPrivileged ); -} -/*-----------------------------------------------------------*/ - -size_t MPU_xPortGetFreeHeapSize( void ) -{ -size_t xReturn; -portBASE_TYPE xRunningPrivileged = prvRaisePrivilege(); - - xReturn = xPortGetFreeHeapSize(); - - portRESET_PRIVILEGE( xRunningPrivileged ); - - return xReturn; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/GCC/ARM_CM3_MPU/portmacro.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/GCC/ARM_CM3_MPU/portmacro.h deleted file mode 100644 index 48c8fd424..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/GCC/ARM_CM3_MPU/portmacro.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE long - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* MPU specific constants. */ -#define portUSING_MPU_WRAPPERS 1 -#define portPRIVILEGE_BIT ( 0x80000000UL ) - -#define portMPU_REGION_READ_WRITE ( 0x03UL << 24UL ) -#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 0x05UL << 24UL ) -#define portMPU_REGION_READ_ONLY ( 0x06UL << 24UL ) -#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0x01UL << 24UL ) -#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) -#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) - -#define portUNPRIVILEGED_FLASH_REGION ( 0UL ) -#define portPRIVILEGED_FLASH_REGION ( 1UL ) -#define portPRIVILEGED_RAM_REGION ( 2UL ) -#define portGENERAL_PERIPHERALS_REGION ( 3UL ) -#define portSTACK_REGION ( 4UL ) -#define portFIRST_CONFIGURABLE_REGION ( 5UL ) -#define portLAST_CONFIGURABLE_REGION ( 7UL ) -#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) -#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ - -#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " :::"r0" ) - -typedef struct MPU_REGION_REGISTERS -{ - unsigned portLONG ulRegionBaseAddress; - unsigned portLONG ulRegionAttribute; -} xMPU_REGION_REGISTERS; - -/* Plus 1 to create space for the stack region. */ -typedef struct MPU_SETTINGS -{ - xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ]; -} xMPU_SETTINGS; - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -/*-----------------------------------------------------------*/ - -/* SVC numbers for various services. */ -#define portSVC_START_SCHEDULER 0 -#define portSVC_YIELD 1 -#define portSVC_prvRaisePrivilege 2 - -/* Scheduler utilities. */ - -#define portYIELD() __asm volatile ( " SVC %0 \n" :: "i" (portSVC_YIELD) ) -#define portYIELD_WITHIN_API() *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET - -#define portNVIC_INT_CTRL ( ( volatile unsigned portLONG *) 0xe000ed04 ) -#define portNVIC_PENDSVSET 0x10000000 -#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET -/*-----------------------------------------------------------*/ - - -/* Critical section management. */ - -/* - * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other - * registers. r0 is clobbered. - */ -#define portSET_INTERRUPT_MASK() \ - __asm volatile \ - ( \ - " mov r0, %0 \n" \ - " msr basepri, r0 \n" \ - ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY):"r0" \ - ) - -/* - * Set basepri back to 0 without effective other registers. - * r0 is clobbered. - */ -#define portCLEAR_INTERRUPT_MASK() \ - __asm volatile \ - ( \ - " mov r0, #0 \n" \ - " msr basepri, r0 \n" \ - :::"r0" \ - ) - -#define portSET_INTERRUPT_MASK_FROM_ISR() 0;portSET_INTERRUPT_MASK() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) portCLEAR_INTERRUPT_MASK();(void)x - - -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portDISABLE_INTERRUPTS() portSET_INTERRUPT_MASK() -#define portENABLE_INTERRUPTS() portCLEAR_INTERRUPT_MASK() -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#define portNOP() - - - -#ifdef __cplusplus -} -#endif - -#endif /* PORTMACRO_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/IAR/ARM_CM3/port.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/IAR/ARM_CM3/port.c deleted file mode 100644 index ffffbf976..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/IAR/ARM_CM3/port.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -/* - Change from V4.2.1: - - + Introduced usage of configKERNEL_INTERRUPT_PRIORITY macro to set the - interrupt priority used by the kernel. -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ARM CM3 port. - *----------------------------------------------------------*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "exceptions.h" - -/* Constants required to manipulate the NVIC. */ -#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long *) 0xe000e010 ) -#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long *) 0xe000e014 ) -#define portNVIC_INT_CTRL ( ( volatile unsigned long *) 0xe000ed04 ) -#define portNVIC_SYSPRI2 ( ( volatile unsigned long *) 0xe000ed20 ) -#define portNVIC_SYSTICK_CLK 0x00000004 -#define portNVIC_SYSTICK_INT 0x00000002 -#define portNVIC_SYSTICK_ENABLE 0x00000001 -#define portNVIC_PENDSVSET 0x10000000 -#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 ) -#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 ) - -/* Constants required to set up the initial stack. */ -#define portINITIAL_XPSR ( 0x01000000 ) - -/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is -defined. The value 255 should also ensure backward compatibility. -FreeRTOS.org versions prior to V4.3.0 did not include this definition. */ -#ifndef configKERNEL_INTERRUPT_PRIORITY - #define configKERNEL_INTERRUPT_PRIORITY 0 -#endif - -/* Each task maintains its own interrupt status in the critical nesting -variable. */ -static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa; - -/* - * Setup the timer to generate the tick interrupts. - */ -static void prvSetupTimerInterrupt( void ); - -/* - * Exception handlers. - */ -void xPortSysTickHandler( void ); - -/* - * Start first task is a separate function so it can be tested in isolation. - */ -extern void vPortStartFirstTask( void ); - -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ - /* Simulate the stack frame as it would be created by a context switch - interrupt. */ - *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */ - pxTopOfStack--; - *pxTopOfStack = 0; /* LR */ - pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Make PendSV and SysTick the lowest priority interrupts. */ - *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI; - *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI; - - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Initialise the critical nesting count ready for the first task. */ - uxCriticalNesting = 0; - - /* Start the first task. */ - vPortStartFirstTask(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the CM3 port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -void vPortYieldFromISR( void ) -{ - /* Set a PendSV to request a context switch. */ - *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; -} -/*-----------------------------------------------------------*/ - -void vPortEnterCritical( void ) -{ - portDISABLE_INTERRUPTS(); - uxCriticalNesting++; -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) -{ - uxCriticalNesting--; - if( uxCriticalNesting == 0 ) - { - portENABLE_INTERRUPTS(); - } -} -/*-----------------------------------------------------------*/ - -//void xPortSysTickHandler( void ) -void SysTick_Handler( void ) -{ - unsigned long ulDummy; - - /* If using preemption, also force a context switch. */ - #if configUSE_PREEMPTION == 1 - *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; - #endif - - ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); - { - vTaskIncrementTick(); - } - portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); -} -/*-----------------------------------------------------------*/ - -/* - * Setup the systick timer to generate the tick interrupts at the required - * frequency. - */ -void prvSetupTimerInterrupt( void ) -{ - /* Configure SysTick to interrupt at the requested rate. */ - *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; - *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; -} -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/IAR/ARM_CM3/portasm.s b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/IAR/ARM_CM3/portasm.s deleted file mode 100644 index 7fbfa4a60..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/IAR/ARM_CM3/portasm.s +++ /dev/null @@ -1,167 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -/* - Change from V4.2.1: - - + Introduced usage of configKERNEL_INTERRUPT_PRIORITY macro to set the - interrupt priority used by the kernel. -*/ - -#include - -/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is -defined. The value zero should also ensure backward compatibility. -FreeRTOS.org versions prior to V4.3.0 did not include this definition. */ -#ifndef configKERNEL_INTERRUPT_PRIORITY - #define configKERNEL_INTERRUPT_PRIORITY 0 -#endif - - - RSEG CODE:CODE(2) - thumb - - EXTERN vPortYieldFromISR - EXTERN pxCurrentTCB - EXTERN vTaskSwitchContext - - PUBLIC vSetMSP -// PUBLIC xPortPendSVHandler - PUBLIC PendSV_Handler - PUBLIC vPortSetInterruptMask - PUBLIC vPortClearInterruptMask -// PUBLIC vPortSVCHandler - PUBLIC SVC_Handler - PUBLIC vPortStartFirstTask - - -/*-----------------------------------------------------------*/ - -vSetMSP: - msr msp, r0 - bx lr - -/*-----------------------------------------------------------*/ - -//xPortPendSVHandler: -PendSV_Handler: - mrs r0, psp - ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */ - ldr r2, [r3] - - stmdb r0!, {r4-r11} /* Save the remaining registers. */ - str r0, [r2] /* Save the new top of stack into the first member of the TCB. */ - - stmdb sp!, {r3, r14} - mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 - bl vTaskSwitchContext - mov r0, #0 - msr basepri, r0 - ldmia sp!, {r3, r14} - - ldr r1, [r3] - ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */ - ldmia r0!, {r4-r11} /* Pop the registers. */ - msr psp, r0 - bx r14 - - -/*-----------------------------------------------------------*/ - -vPortSetInterruptMask: - push { r0 } - mov R0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr BASEPRI, R0 - pop { R0 } - - bx r14 - -/*-----------------------------------------------------------*/ - -vPortClearInterruptMask: - PUSH { r0 } - MOV R0, #0 - MSR BASEPRI, R0 - POP { R0 } - - bx r14 - -/*-----------------------------------------------------------*/ - -SVC_Handler: -//vPortSVCHandler; - ldr r3, =pxCurrentTCB - ldr r1, [r3] - ldr r0, [r1] - ldmia r0!, {r4-r11} - msr psp, r0 - mov r0, #0 - msr basepri, r0 - orr r14, r14, #13 - bx r14 - -/*-----------------------------------------------------------*/ - -vPortStartFirstTask: - /* Use the NVIC offset register to locate the stack. */ - ldr r0, =0xE000ED08 - ldr r0, [r0] - ldr r0, [r0] - /* Set the msp back to the start of the stack. */ - msr msp, r0 - /* Call SVC to start the first task. */ - svc 0 - - END - \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/IAR/ARM_CM3/portmacro.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/IAR/ARM_CM3/portmacro.h deleted file mode 100644 index b3205d552..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/IAR/ARM_CM3/portmacro.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE long - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -/*-----------------------------------------------------------*/ - - -/* Scheduler utilities. */ -extern void vPortYieldFromISR( void ); - -#define portYIELD() vPortYieldFromISR() - -#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR() -/*-----------------------------------------------------------*/ - - -/* Critical section management. */ - -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); -extern void vPortSetInterruptMask( void ); -extern void vPortClearInterruptMask( void ); - -#define portDISABLE_INTERRUPTS() vPortSetInterruptMask() -#define portENABLE_INTERRUPTS() vPortClearInterruptMask() -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() -#define portSET_INTERRUPT_MASK_FROM_ISR() 0;vPortSetInterruptMask() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask();(void)x - -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#define portNOP() - -#ifdef __cplusplus -} -#endif - -#endif /* PORTMACRO_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/MemMang/heap_1.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/MemMang/heap_1.c deleted file mode 100644 index ac065cb86..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/MemMang/heap_1.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - - -/* - * The simplest possible implementation of pvPortMalloc(). Note that this - * implementation does NOT allow allocated memory to be freed again. - * - * See heap_2.c and heap_3.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ -#include - -/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining -all the API functions to use the MPU wrappers. That should only be done when -task.h is included from an application file. */ -#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE - -#include "FreeRTOS.h" -#include "task.h" - -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE - -/* Allocate the memory for the heap. The struct is used to force byte -alignment without using any non-portable code. */ -static union xRTOS_HEAP -{ - #if portBYTE_ALIGNMENT == 8 - volatile portDOUBLE dDummy; - #else - volatile unsigned long ulDummy; - #endif - unsigned char ucHeap[ configTOTAL_HEAP_SIZE ]; -} xHeap; - -static size_t xNextFreeByte = ( size_t ) 0; -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -void *pvReturn = NULL; - - /* Ensure that blocks are always aligned to the required number of bytes. */ - #if portBYTE_ALIGNMENT != 1 - if( xWantedSize & portBYTE_ALIGNMENT_MASK ) - { - /* Byte alignment required. */ - xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); - } - #endif - - vTaskSuspendAll(); - { - /* Check there is enough room left for the allocation. */ - if( ( ( xNextFreeByte + xWantedSize ) < configTOTAL_HEAP_SIZE ) && - ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) )/* Check for overflow. */ - { - /* Return the next free byte then increment the index past this - block. */ - pvReturn = &( xHeap.ucHeap[ xNextFreeByte ] ); - xNextFreeByte += xWantedSize; - } - } - xTaskResumeAll(); - - #if( configUSE_MALLOC_FAILED_HOOK == 1 ) - { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - } - #endif - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ - /* Memory cannot be freed using this scheme. See heap_2.c and heap_3.c - for alternative implementations, and the memory management pages of - http://www.FreeRTOS.org for more information. */ - ( void ) pv; -} -/*-----------------------------------------------------------*/ - -void vPortInitialiseBlocks( void ) -{ - /* Only required when static memory is not cleared. */ - xNextFreeByte = ( size_t ) 0; -} -/*-----------------------------------------------------------*/ - -size_t xPortGetFreeHeapSize( void ) -{ - return ( configTOTAL_HEAP_SIZE - xNextFreeByte ); -} - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/MemMang/heap_2.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/MemMang/heap_2.c deleted file mode 100644 index 35bf87ca2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/MemMang/heap_2.c +++ /dev/null @@ -1,280 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -/* - * A sample implementation of pvPortMalloc() and vPortFree() that permits - * allocated blocks to be freed, but does not combine adjacent free blocks - * into a single larger block. - * - * See heap_1.c and heap_3.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ -#include - -/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining -all the API functions to use the MPU wrappers. That should only be done when -task.h is included from an application file. */ -#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE - -#include "FreeRTOS.h" -#include "task.h" - -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE - -/* Allocate the memory for the heap. The struct is used to force byte -alignment without using any non-portable code. */ -static union xRTOS_HEAP -{ - #if portBYTE_ALIGNMENT == 8 - volatile portDOUBLE dDummy; - #else - volatile unsigned long ulDummy; - #endif - unsigned char ucHeap[ configTOTAL_HEAP_SIZE ]; -} xHeap; - -/* Define the linked list structure. This is used to link free blocks in order -of their size. */ -typedef struct A_BLOCK_LINK -{ - struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */ - size_t xBlockSize; /*<< The size of the free block. */ -} xBlockLink; - - -static const unsigned short heapSTRUCT_SIZE = ( sizeof( xBlockLink ) + portBYTE_ALIGNMENT - ( sizeof( xBlockLink ) % portBYTE_ALIGNMENT ) ); -#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) ) - -/* Create a couple of list links to mark the start and end of the list. */ -static xBlockLink xStart, xEnd; - -/* Keeps track of the number of free bytes remaining, but says nothing about -fragmentation. */ -static size_t xFreeBytesRemaining; - -/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */ - -/* - * Insert a block into the list of free blocks - which is ordered by size of - * the block. Small blocks at the start of the list and large blocks at the end - * of the list. - */ -#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \ -{ \ -xBlockLink *pxIterator; \ -size_t xBlockSize; \ - \ - xBlockSize = pxBlockToInsert->xBlockSize; \ - \ - /* Iterate through the list until a block is found that has a larger size */ \ - /* than the block we are inserting. */ \ - for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \ - { \ - /* There is nothing to do here - just iterate to the correct position. */ \ - } \ - \ - /* Update the list to include the block being inserted in the correct */ \ - /* position. */ \ - pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \ - pxIterator->pxNextFreeBlock = pxBlockToInsert; \ -} -/*-----------------------------------------------------------*/ - -#define prvHeapInit() \ -{ \ -xBlockLink *pxFirstFreeBlock; \ - \ - /* xStart is used to hold a pointer to the first item in the list of free */ \ - /* blocks. The void cast is used to prevent compiler warnings. */ \ - xStart.pxNextFreeBlock = ( void * ) xHeap.ucHeap; \ - xStart.xBlockSize = ( size_t ) 0; \ - \ - /* xEnd is used to mark the end of the list of free blocks. */ \ - xEnd.xBlockSize = configTOTAL_HEAP_SIZE; \ - xEnd.pxNextFreeBlock = NULL; \ - \ - /* To start with there is a single free block that is sized to take up the \ - entire heap space. */ \ - pxFirstFreeBlock = ( void * ) xHeap.ucHeap; \ - pxFirstFreeBlock->xBlockSize = configTOTAL_HEAP_SIZE; \ - pxFirstFreeBlock->pxNextFreeBlock = &xEnd; \ - \ - xFreeBytesRemaining = configTOTAL_HEAP_SIZE; \ -} -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -xBlockLink *pxBlock, *pxPreviousBlock, *pxNewBlockLink; -static portBASE_TYPE xHeapHasBeenInitialised = pdFALSE; -void *pvReturn = NULL; - - vTaskSuspendAll(); - { - /* If this is the first call to malloc then the heap will require - initialisation to setup the list of free blocks. */ - if( xHeapHasBeenInitialised == pdFALSE ) - { - prvHeapInit(); - xHeapHasBeenInitialised = pdTRUE; - } - - /* The wanted size is increased so it can contain a xBlockLink - structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) - { - xWantedSize += heapSTRUCT_SIZE; - - /* Ensure that blocks are always aligned to the required number of bytes. */ - if( xWantedSize & portBYTE_ALIGNMENT_MASK ) - { - /* Byte alignment required. */ - xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); - } - } - - if( ( xWantedSize > 0 ) && ( xWantedSize < configTOTAL_HEAP_SIZE ) ) - { - /* Blocks are stored in byte order - traverse the list from the start - (smallest) block until one of adequate size is found. */ - pxPreviousBlock = &xStart; - pxBlock = xStart.pxNextFreeBlock; - while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock ) ) - { - pxPreviousBlock = pxBlock; - pxBlock = pxBlock->pxNextFreeBlock; - } - - /* If we found the end marker then a block of adequate size was not found. */ - if( pxBlock != &xEnd ) - { - /* Return the memory space - jumping over the xBlockLink structure - at its start. */ - pvReturn = ( void * ) ( ( ( unsigned char * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE ); - - /* This block is being returned for use so must be taken our of the - list of free blocks. */ - pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; - - /* If the block is larger than required it can be split into two. */ - if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) - { - /* This block is to be split into two. Create a new block - following the number of bytes requested. The void cast is - used to prevent byte alignment warnings from the compiler. */ - pxNewBlockLink = ( void * ) ( ( ( unsigned char * ) pxBlock ) + xWantedSize ); - - /* Calculate the sizes of two blocks split from the single - block. */ - pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; - pxBlock->xBlockSize = xWantedSize; - - /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); - } - - xFreeBytesRemaining -= xWantedSize; - } - } - } - xTaskResumeAll(); - - #if( configUSE_MALLOC_FAILED_HOOK == 1 ) - { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - } - #endif - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ -unsigned char *puc = ( unsigned char * ) pv; -xBlockLink *pxLink; - - if( pv ) - { - /* The memory being freed will have an xBlockLink structure immediately - before it. */ - puc -= heapSTRUCT_SIZE; - - /* This casting is to keep the compiler from issuing warnings. */ - pxLink = ( void * ) puc; - - vTaskSuspendAll(); - { - /* Add this block to the list of free blocks. */ - prvInsertBlockIntoFreeList( ( ( xBlockLink * ) pxLink ) ); - xFreeBytesRemaining += pxLink->xBlockSize; - } - xTaskResumeAll(); - } -} -/*-----------------------------------------------------------*/ - -size_t xPortGetFreeHeapSize( void ) -{ - return xFreeBytesRemaining; -} -/*-----------------------------------------------------------*/ - -void vPortInitialiseBlocks( void ) -{ - /* This just exists to keep the linker quiet. */ -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/MemMang/heap_3.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/MemMang/heap_3.c deleted file mode 100644 index c817c0e16..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/MemMang/heap_3.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - - -/* - * Implementation of pvPortMalloc() and vPortFree() that relies on the - * compilers own malloc() and free() implementations. - * - * This file can only be used if the linker is configured to to generate - * a heap memory area. - * - * See heap_2.c and heap_1.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ - -#include - -/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining -all the API functions to use the MPU wrappers. That should only be done when -task.h is included from an application file. */ -#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE - -#include "FreeRTOS.h" -#include "task.h" - -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE - -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -void *pvReturn; - - vTaskSuspendAll(); - { - pvReturn = malloc( xWantedSize ); - } - xTaskResumeAll(); - - #if( configUSE_MALLOC_FAILED_HOOK == 1 ) - { - if( pvReturn == NULL ) - { - extern void vApplicationMallocFailedHook( void ); - vApplicationMallocFailedHook(); - } - } - #endif - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ - if( pv ) - { - vTaskSuspendAll(); - { - free( pv ); - } - xTaskResumeAll(); - } -} - -/*-----------------------------------------------------------*/ - -size_t xPortGetFreeHeapSize( void ) -{ - return 0 ; -} -/*-----------------------------------------------------------*/ - -void vPortInitialiseBlocks( void ) -{ - /* This just exists to keep the linker quiet. */ -} - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/RVDS/ARM_CM3/port.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/RVDS/ARM_CM3/port.c deleted file mode 100644 index c24091623..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/RVDS/ARM_CM3/port.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ARM CM3 port. - *----------------------------------------------------------*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -#ifndef configKERNEL_INTERRUPT_PRIORITY - #define configKERNEL_INTERRUPT_PRIORITY 255 -#endif - -/* Constants required to manipulate the NVIC. */ -#define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long *) 0xe000e010 ) -#define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long *) 0xe000e014 ) -#define portNVIC_INT_CTRL ( ( volatile unsigned long *) 0xe000ed04 ) -#define portNVIC_SYSPRI2 ( ( volatile unsigned long *) 0xe000ed20 ) -#define portNVIC_SYSTICK_CLK 0x00000004 -#define portNVIC_SYSTICK_INT 0x00000002 -#define portNVIC_SYSTICK_ENABLE 0x00000001 -#define portNVIC_PENDSVSET 0x10000000 -#define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 ) -#define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 ) - -/* Constants required to set up the initial stack. */ -#define portINITIAL_XPSR ( 0x01000000 ) - -/* Each task maintains its own interrupt status in the critical nesting -variable. */ -static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa; - -/* - * Setup the timer to generate the tick interrupts. - */ -static void prvSetupTimerInterrupt( void ); - -/* - * Exception handlers. - */ -void xPortPendSVHandler( void ); -void xPortSysTickHandler( void ); -void vPortSVCHandler( void ); - -/* - * Start first task is a separate function so it can be tested in isolation. - */ -void vPortStartFirstTask( void ); - -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ - /* Simulate the stack frame as it would be created by a context switch - interrupt. */ - *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */ - pxTopOfStack--; - *pxTopOfStack = 0; /* LR */ - pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -//__asm void vPortSVCHandler( void ) -__asm void SVC_Handler( void ) -{ - PRESERVE8 - - ldr r3, =pxCurrentTCB /* Restore the context. */ - ldr r1, [r3] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ - ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */ - ldmia r0!, {r4-r11} /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ - msr psp, r0 /* Restore the task stack pointer. */ - mov r0, #0 - msr basepri, r0 - orr r14, #0xd - bx r14 -} -/*-----------------------------------------------------------*/ - -__asm void vPortStartFirstTask( void ) -{ - PRESERVE8 - - /* Use the NVIC offset register to locate the stack. */ - ldr r0, =0xE000ED08 - ldr r0, [r0] - ldr r0, [r0] - /* Set the msp back to the start of the stack. */ - msr msp, r0 - /* Call SVC to start the first task. */ - svc 0 -} -/*-----------------------------------------------------------*/ - -/* - * See header file for description. - */ -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */ - *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI; - *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI; - - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Initialise the critical nesting count ready for the first task. */ - uxCriticalNesting = 0; - - /* Start the first task. */ - vPortStartFirstTask(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the CM3 port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -void vPortYieldFromISR( void ) -{ - /* Set a PendSV to request a context switch. */ - *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; -} -/*-----------------------------------------------------------*/ - -void vPortEnterCritical( void ) -{ - portDISABLE_INTERRUPTS(); - uxCriticalNesting++; -} -/*-----------------------------------------------------------*/ - -void vPortExitCritical( void ) -{ - uxCriticalNesting--; - if( uxCriticalNesting == 0 ) - { - portENABLE_INTERRUPTS(); - } -} -/*-----------------------------------------------------------*/ - -//__asm void xPortPendSVHandler( void ) -__asm void PendSV_Handler( void ) -{ - extern uxCriticalNesting; - extern pxCurrentTCB; - extern vTaskSwitchContext; - - PRESERVE8 - - mrs r0, psp - - ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */ - ldr r2, [r3] - - stmdb r0!, {r4-r11} /* Save the remaining registers. */ - str r0, [r2] /* Save the new top of stack into the first member of the TCB. */ - - stmdb sp!, {r3, r14} - mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 - bl vTaskSwitchContext - mov r0, #0 - msr basepri, r0 - ldmia sp!, {r3, r14} - - ldr r1, [r3] - ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */ - ldmia r0!, {r4-r11} /* Pop the registers and the critical nesting count. */ - msr psp, r0 - bx r14 - nop -} -/*-----------------------------------------------------------*/ - -void xPortSysTickHandler( void ) -{ -unsigned long ulDummy; - - /* If using preemption, also force a context switch. */ - #if configUSE_PREEMPTION == 1 - *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET; - #endif - - ulDummy = portSET_INTERRUPT_MASK_FROM_ISR(); - { - vTaskIncrementTick(); - } - portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy ); -} -/*-----------------------------------------------------------*/ - -/* - * Setup the systick timer to generate the tick interrupts at the required - * frequency. - */ -void prvSetupTimerInterrupt( void ) -{ - /* Configure SysTick to interrupt at the requested rate. */ - *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; - *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE; -} -/*-----------------------------------------------------------*/ - -__asm void vPortSetInterruptMask( void ) -{ - PRESERVE8 - - push { r0 } - mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY - msr basepri, r0 - pop { r0 } - bx r14 -} - -/*-----------------------------------------------------------*/ - -__asm void vPortClearInterruptMask( void ) -{ - PRESERVE8 - - push { r0 } - mov r0, #0 - msr basepri, r0 - pop { r0 } - bx r14 -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/RVDS/ARM_CM3/portmacro.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/RVDS/ARM_CM3/portmacro.h deleted file mode 100644 index 2dbeb2031..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/RVDS/ARM_CM3/portmacro.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE long - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 8 -/*-----------------------------------------------------------*/ - - -/* Scheduler utilities. */ -extern void vPortYield( void ); -extern void vPortYieldFromISR( void ); - -#define portYIELD() vPortYieldFromISR() -#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYieldFromISR() -/*-----------------------------------------------------------*/ - - -/* Critical section management. */ - -extern void vPortSetInterruptMask( void ); -extern void vPortClearInterruptMask( void ); -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portDISABLE_INTERRUPTS() vPortSetInterruptMask() -#define portENABLE_INTERRUPTS() vPortClearInterruptMask() -#define portENTER_CRITICAL() vPortEnterCritical() -#define portEXIT_CRITICAL() vPortExitCritical() -#define portSET_INTERRUPT_MASK_FROM_ISR() 0;vPortSetInterruptMask() -#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask();(void)x - -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#define portNOP() - -#ifdef __cplusplus -} -#endif - -#endif /* PORTMACRO_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/readme.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/readme.txt deleted file mode 100644 index 43e7c1d55..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/portable/readme.txt +++ /dev/null @@ -1,19 +0,0 @@ -Each real time kernel port consists of three files that contain the core kernel -components and are common to every port, and one or more files that are -specific to a particular microcontroller and/or compiler. - - -+ The FreeRTOS/Source/Portable/MemMang directory contains the three sample -memory allocators as described on the http://www.FreeRTOS.org WEB site. - -+ The other directories each contain files specific to a particular -microcontroller or compiler. - - - -For example, if you are interested in the GCC port for the ATMega323 -microcontroller then the port specific files are contained in -FreeRTOS/Source/Portable/GCC/ATMega323 directory. If this is the only -port you are interested in then all the other directories can be -ignored. - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/queue.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/queue.c deleted file mode 100644 index 69ea2bde9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/queue.c +++ /dev/null @@ -1,1465 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - -#include -#include - -/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining -all the API functions to use the MPU wrappers. That should only be done when -task.h is included from an application file. */ -#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE - -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE - -/*----------------------------------------------------------- - * PUBLIC LIST API documented in list.h - *----------------------------------------------------------*/ - -/* Constants used with the cRxLock and cTxLock structure members. */ -#define queueUNLOCKED ( ( signed portBASE_TYPE ) -1 ) -#define queueLOCKED_UNMODIFIED ( ( signed portBASE_TYPE ) 0 ) - -#define queueERRONEOUS_UNBLOCK ( -1 ) - -/* For internal use only. */ -#define queueSEND_TO_BACK ( 0 ) -#define queueSEND_TO_FRONT ( 1 ) - -/* Effectively make a union out of the xQUEUE structure. */ -#define pxMutexHolder pcTail -#define uxQueueType pcHead -#define uxRecursiveCallCount pcReadFrom -#define queueQUEUE_IS_MUTEX NULL - -/* Semaphores do not actually store or copy data, so have an items size of -zero. */ -#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( 0 ) -#define queueDONT_BLOCK ( ( portTickType ) 0 ) -#define queueMUTEX_GIVE_BLOCK_TIME ( ( portTickType ) 0 ) - -/* - * Definition of the queue used by the scheduler. - * Items are queued by copy, not reference. - */ -typedef struct QueueDefinition -{ - signed char *pcHead; /*< Points to the beginning of the queue storage area. */ - signed char *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */ - - signed char *pcWriteTo; /*< Points to the free next place in the storage area. */ - signed char *pcReadFrom; /*< Points to the last place that a queued item was read from. */ - - xList xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */ - xList xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */ - - volatile unsigned portBASE_TYPE uxMessagesWaiting;/*< The number of items currently in the queue. */ - unsigned portBASE_TYPE uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */ - unsigned portBASE_TYPE uxItemSize; /*< The size of each items that the queue will hold. */ - - signed portBASE_TYPE xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ - signed portBASE_TYPE xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ - -} xQUEUE; -/*-----------------------------------------------------------*/ - -/* - * Inside this file xQueueHandle is a pointer to a xQUEUE structure. - * To keep the definition private the API header file defines it as a - * pointer to void. - */ -typedef xQUEUE * xQueueHandle; - -/* - * Prototypes for public functions are included here so we don't have to - * include the API header file (as it defines xQueueHandle differently). These - * functions are documented in the API header file. - */ -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ) PRIVILEGED_FUNCTION; -signed portBASE_TYPE xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ) PRIVILEGED_FUNCTION; -unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION; -void vQueueDelete( xQueueHandle xQueue ) PRIVILEGED_FUNCTION; -signed portBASE_TYPE xQueueGenericSendFromISR( xQueueHandle pxQueue, const void * const pvItemToQueue, signed portBASE_TYPE *pxHigherPriorityTaskWoken, portBASE_TYPE xCopyPosition ) PRIVILEGED_FUNCTION; -signed portBASE_TYPE xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ) PRIVILEGED_FUNCTION; -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void * const pvBuffer, signed portBASE_TYPE *pxTaskWoken ) PRIVILEGED_FUNCTION; -xQueueHandle xQueueCreateMutex( void ) PRIVILEGED_FUNCTION; -xQueueHandle xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount ) PRIVILEGED_FUNCTION; -portBASE_TYPE xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime ) PRIVILEGED_FUNCTION; -portBASE_TYPE xQueueGiveMutexRecursive( xQueueHandle xMutex ) PRIVILEGED_FUNCTION; -signed portBASE_TYPE xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ) PRIVILEGED_FUNCTION; -signed portBASE_TYPE xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ) PRIVILEGED_FUNCTION; -signed portBASE_TYPE xQueueIsQueueEmptyFromISR( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION; -signed portBASE_TYPE xQueueIsQueueFullFromISR( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION; -unsigned portBASE_TYPE uxQueueMessagesWaitingFromISR( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION; - -/* - * Co-routine queue functions differ from task queue functions. Co-routines are - * an optional component. - */ -#if configUSE_CO_ROUTINES == 1 - signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ) PRIVILEGED_FUNCTION; - signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ) PRIVILEGED_FUNCTION; - signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) PRIVILEGED_FUNCTION; - signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) PRIVILEGED_FUNCTION; -#endif - -/* - * The queue registry is just a means for kernel aware debuggers to locate - * queue structures. It has no other purpose so is an optional component. - */ -#if configQUEUE_REGISTRY_SIZE > 0 - - /* The type stored within the queue registry array. This allows a name - to be assigned to each queue making kernel aware debugging a little - more user friendly. */ - typedef struct QUEUE_REGISTRY_ITEM - { - signed char *pcQueueName; - xQueueHandle xHandle; - } xQueueRegistryItem; - - /* The queue registry is simply an array of xQueueRegistryItem structures. - The pcQueueName member of a structure being NULL is indicative of the - array position being vacant. */ - xQueueRegistryItem xQueueRegistry[ configQUEUE_REGISTRY_SIZE ]; - - /* Removes a queue from the registry by simply setting the pcQueueName - member to NULL. */ - static void vQueueUnregisterQueue( xQueueHandle xQueue ) PRIVILEGED_FUNCTION; - void vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcQueueName ) PRIVILEGED_FUNCTION; -#endif - -/* - * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not - * prevent an ISR from adding or removing items to the queue, but does prevent - * an ISR from removing tasks from the queue event lists. If an ISR finds a - * queue is locked it will instead increment the appropriate queue lock count - * to indicate that a task may require unblocking. When the queue in unlocked - * these lock counts are inspected, and the appropriate action taken. - */ -static void prvUnlockQueue( xQueueHandle pxQueue ) PRIVILEGED_FUNCTION; - -/* - * Uses a critical section to determine if there is any data in a queue. - * - * @return pdTRUE if the queue contains no items, otherwise pdFALSE. - */ -static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION; - -/* - * Uses a critical section to determine if there is any space in a queue. - * - * @return pdTRUE if there is no space, otherwise pdFALSE; - */ -static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ) PRIVILEGED_FUNCTION; - -/* - * Copies an item into the queue, either at the front of the queue or the - * back of the queue. - */ -static void prvCopyDataToQueue( xQUEUE *pxQueue, const void *pvItemToQueue, portBASE_TYPE xPosition ) PRIVILEGED_FUNCTION; - -/* - * Copies an item out of a queue. - */ -static void prvCopyDataFromQueue( xQUEUE * const pxQueue, const void *pvBuffer ) PRIVILEGED_FUNCTION; -/*-----------------------------------------------------------*/ - -/* - * Macro to mark a queue as locked. Locking a queue prevents an ISR from - * accessing the queue event lists. - */ -#define prvLockQueue( pxQueue ) \ -{ \ - taskENTER_CRITICAL(); \ - { \ - if( pxQueue->xRxLock == queueUNLOCKED ) \ - { \ - pxQueue->xRxLock = queueLOCKED_UNMODIFIED; \ - } \ - if( pxQueue->xTxLock == queueUNLOCKED ) \ - { \ - pxQueue->xTxLock = queueLOCKED_UNMODIFIED; \ - } \ - } \ - taskEXIT_CRITICAL(); \ -} -/*-----------------------------------------------------------*/ - - -/*----------------------------------------------------------- - * PUBLIC QUEUE MANAGEMENT API documented in queue.h - *----------------------------------------------------------*/ - -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ) -{ -xQUEUE *pxNewQueue; -size_t xQueueSizeInBytes; - - /* Allocate the new queue structure. */ - if( uxQueueLength > ( unsigned portBASE_TYPE ) 0 ) - { - pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) ); - if( pxNewQueue != NULL ) - { - /* Create the list of pointers to queue items. The queue is one byte - longer than asked for to make wrap checking easier/faster. */ - xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1; - - pxNewQueue->pcHead = ( signed char * ) pvPortMalloc( xQueueSizeInBytes ); - if( pxNewQueue->pcHead != NULL ) - { - /* Initialise the queue members as described above where the - queue type is defined. */ - pxNewQueue->pcTail = pxNewQueue->pcHead + ( uxQueueLength * uxItemSize ); - pxNewQueue->uxMessagesWaiting = 0; - pxNewQueue->pcWriteTo = pxNewQueue->pcHead; - pxNewQueue->pcReadFrom = pxNewQueue->pcHead + ( ( uxQueueLength - 1 ) * uxItemSize ); - pxNewQueue->uxLength = uxQueueLength; - pxNewQueue->uxItemSize = uxItemSize; - pxNewQueue->xRxLock = queueUNLOCKED; - pxNewQueue->xTxLock = queueUNLOCKED; - - /* Likewise ensure the event queues start with the correct state. */ - vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) ); - vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) ); - - traceQUEUE_CREATE( pxNewQueue ); - return pxNewQueue; - } - else - { - traceQUEUE_CREATE_FAILED(); - vPortFree( pxNewQueue ); - } - } - } - - /* Will only reach here if we could not allocate enough memory or no memory - was required. */ - return NULL; -} -/*-----------------------------------------------------------*/ - -#if ( configUSE_MUTEXES == 1 ) - - xQueueHandle xQueueCreateMutex( void ) - { - xQUEUE *pxNewQueue; - - /* Allocate the new queue structure. */ - pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) ); - if( pxNewQueue != NULL ) - { - /* Information required for priority inheritance. */ - pxNewQueue->pxMutexHolder = NULL; - pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; - - /* Queues used as a mutex no data is actually copied into or out - of the queue. */ - pxNewQueue->pcWriteTo = NULL; - pxNewQueue->pcReadFrom = NULL; - - /* Each mutex has a length of 1 (like a binary semaphore) and - an item size of 0 as nothing is actually copied into or out - of the mutex. */ - pxNewQueue->uxMessagesWaiting = 0; - pxNewQueue->uxLength = 1; - pxNewQueue->uxItemSize = 0; - pxNewQueue->xRxLock = queueUNLOCKED; - pxNewQueue->xTxLock = queueUNLOCKED; - - /* Ensure the event queues start with the correct state. */ - vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) ); - vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) ); - - /* Start with the semaphore in the expected state. */ - xQueueGenericSend( pxNewQueue, NULL, 0, queueSEND_TO_BACK ); - - traceCREATE_MUTEX( pxNewQueue ); - } - else - { - traceCREATE_MUTEX_FAILED(); - } - - return pxNewQueue; - } - -#endif /* configUSE_MUTEXES */ -/*-----------------------------------------------------------*/ - -#if configUSE_RECURSIVE_MUTEXES == 1 - - portBASE_TYPE xQueueGiveMutexRecursive( xQueueHandle pxMutex ) - { - portBASE_TYPE xReturn; - - /* If this is the task that holds the mutex then pxMutexHolder will not - change outside of this task. If this task does not hold the mutex then - pxMutexHolder can never coincidentally equal the tasks handle, and as - this is the only condition we are interested in it does not matter if - pxMutexHolder is accessed simultaneously by another task. Therefore no - mutual exclusion is required to test the pxMutexHolder variable. */ - if( pxMutex->pxMutexHolder == xTaskGetCurrentTaskHandle() ) - { - traceGIVE_MUTEX_RECURSIVE( pxMutex ); - - /* uxRecursiveCallCount cannot be zero if pxMutexHolder is equal to - the task handle, therefore no underflow check is required. Also, - uxRecursiveCallCount is only modified by the mutex holder, and as - there can only be one, no mutual exclusion is required to modify the - uxRecursiveCallCount member. */ - ( pxMutex->uxRecursiveCallCount )--; - - /* Have we unwound the call count? */ - if( pxMutex->uxRecursiveCallCount == 0 ) - { - /* Return the mutex. This will automatically unblock any other - task that might be waiting to access the mutex. */ - xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); - } - - xReturn = pdPASS; - } - else - { - /* We cannot give the mutex because we are not the holder. */ - xReturn = pdFAIL; - - traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); - } - - return xReturn; - } - -#endif /* configUSE_RECURSIVE_MUTEXES */ -/*-----------------------------------------------------------*/ - -#if configUSE_RECURSIVE_MUTEXES == 1 - - portBASE_TYPE xQueueTakeMutexRecursive( xQueueHandle pxMutex, portTickType xBlockTime ) - { - portBASE_TYPE xReturn; - - /* Comments regarding mutual exclusion as per those within - xQueueGiveMutexRecursive(). */ - - traceTAKE_MUTEX_RECURSIVE( pxMutex ); - - if( pxMutex->pxMutexHolder == xTaskGetCurrentTaskHandle() ) - { - ( pxMutex->uxRecursiveCallCount )++; - xReturn = pdPASS; - } - else - { - xReturn = xQueueGenericReceive( pxMutex, NULL, xBlockTime, pdFALSE ); - - /* pdPASS will only be returned if we successfully obtained the mutex, - we may have blocked to reach here. */ - if( xReturn == pdPASS ) - { - ( pxMutex->uxRecursiveCallCount )++; - } - } - - return xReturn; - } - -#endif /* configUSE_RECURSIVE_MUTEXES */ -/*-----------------------------------------------------------*/ - -#if configUSE_COUNTING_SEMAPHORES == 1 - - xQueueHandle xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount ) - { - xQueueHandle pxHandle; - - pxHandle = xQueueCreate( ( unsigned portBASE_TYPE ) uxCountValue, queueSEMAPHORE_QUEUE_ITEM_LENGTH ); - - if( pxHandle != NULL ) - { - pxHandle->uxMessagesWaiting = uxInitialCount; - - traceCREATE_COUNTING_SEMAPHORE(); - } - else - { - traceCREATE_COUNTING_SEMAPHORE_FAILED(); - } - - return pxHandle; - } - -#endif /* configUSE_COUNTING_SEMAPHORES */ -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ) -{ -signed portBASE_TYPE xEntryTimeSet = pdFALSE; -xTimeOutType xTimeOut; - - /* This function relaxes the coding standard somewhat to allow return - statements within the function itself. This is done in the interest - of execution time efficiency. */ - for( ;; ) - { - taskENTER_CRITICAL(); - { - /* Is there room on the queue now? To be running we must be - the highest priority task wanting to access the queue. */ - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - traceQUEUE_SEND( pxQueue ); - prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); - - /* If there was a task waiting for data to arrive on the - queue then unblock it now. */ - if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE ) - { - /* The unblocked task has a priority higher than - our own so yield immediately. Yes it is ok to do - this from within the critical section - the kernel - takes care of that. */ - portYIELD_WITHIN_API(); - } - } - - taskEXIT_CRITICAL(); - - /* Return to the original privilege level before exiting the - function. */ - return pdPASS; - } - else - { - if( xTicksToWait == ( portTickType ) 0 ) - { - /* The queue was full and no block time is specified (or - the block time has expired) so leave now. */ - taskEXIT_CRITICAL(); - - /* Return to the original privilege level before exiting - the function. */ - traceQUEUE_SEND_FAILED( pxQueue ); - return errQUEUE_FULL; - } - else if( xEntryTimeSet == pdFALSE ) - { - /* The queue was full and a block time was specified so - configure the timeout structure. */ - vTaskSetTimeOutState( &xTimeOut ); - xEntryTimeSet = pdTRUE; - } - } - } - taskEXIT_CRITICAL(); - - /* Interrupts and other tasks can send to and receive from the queue - now the critical section has been exited. */ - - vTaskSuspendAll(); - prvLockQueue( pxQueue ); - - /* Update the timeout state to see if it has expired yet. */ - if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) - { - if( prvIsQueueFull( pxQueue ) ) - { - traceBLOCKING_ON_QUEUE_SEND( pxQueue ); - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); - - /* Unlocking the queue means queue events can effect the - event list. It is possible that interrupts occurring now - remove this task from the event list again - but as the - scheduler is suspended the task will go onto the pending - ready last instead of the actual ready list. */ - prvUnlockQueue( pxQueue ); - - /* Resuming the scheduler will move tasks from the pending - ready list into the ready list - so it is feasible that this - task is already in a ready list before it yields - in which - case the yield will not cause a context switch unless there - is also a higher priority task in the pending ready list. */ - if( !xTaskResumeAll() ) - { - portYIELD_WITHIN_API(); - } - } - else - { - /* Try again. */ - prvUnlockQueue( pxQueue ); - ( void ) xTaskResumeAll(); - } - } - else - { - /* The timeout has expired. */ - prvUnlockQueue( pxQueue ); - ( void ) xTaskResumeAll(); - - /* Return to the original privilege level before exiting the - function. */ - traceQUEUE_SEND_FAILED( pxQueue ); - return errQUEUE_FULL; - } - } -} -/*-----------------------------------------------------------*/ - -#if configUSE_ALTERNATIVE_API == 1 - - signed portBASE_TYPE xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition ) - { - signed portBASE_TYPE xEntryTimeSet = pdFALSE; - xTimeOutType xTimeOut; - - for( ;; ) - { - taskENTER_CRITICAL(); - { - /* Is there room on the queue now? To be running we must be - the highest priority task wanting to access the queue. */ - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - traceQUEUE_SEND( pxQueue ); - prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); - - /* If there was a task waiting for data to arrive on the - queue then unblock it now. */ - if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE ) - { - /* The unblocked task has a priority higher than - our own so yield immediately. */ - portYIELD_WITHIN_API(); - } - } - - taskEXIT_CRITICAL(); - return pdPASS; - } - else - { - if( xTicksToWait == ( portTickType ) 0 ) - { - taskEXIT_CRITICAL(); - return errQUEUE_FULL; - } - else if( xEntryTimeSet == pdFALSE ) - { - vTaskSetTimeOutState( &xTimeOut ); - xEntryTimeSet = pdTRUE; - } - } - } - taskEXIT_CRITICAL(); - - taskENTER_CRITICAL(); - { - if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) - { - if( prvIsQueueFull( pxQueue ) ) - { - traceBLOCKING_ON_QUEUE_SEND( pxQueue ); - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); - portYIELD_WITHIN_API(); - } - } - else - { - taskEXIT_CRITICAL(); - traceQUEUE_SEND_FAILED( pxQueue ); - return errQUEUE_FULL; - } - } - taskEXIT_CRITICAL(); - } - } - -#endif /* configUSE_ALTERNATIVE_API */ -/*-----------------------------------------------------------*/ - -#if configUSE_ALTERNATIVE_API == 1 - - signed portBASE_TYPE xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ) - { - signed portBASE_TYPE xEntryTimeSet = pdFALSE; - xTimeOutType xTimeOut; - signed char *pcOriginalReadPosition; - - for( ;; ) - { - taskENTER_CRITICAL(); - { - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Remember our read position in case we are just peeking. */ - pcOriginalReadPosition = pxQueue->pcReadFrom; - - prvCopyDataFromQueue( pxQueue, pvBuffer ); - - if( xJustPeeking == pdFALSE ) - { - traceQUEUE_RECEIVE( pxQueue ); - - /* We are actually removing data. */ - --( pxQueue->uxMessagesWaiting ); - - #if ( configUSE_MUTEXES == 1 ) - { - if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) - { - /* Record the information required to implement - priority inheritance should it become necessary. */ - pxQueue->pxMutexHolder = xTaskGetCurrentTaskHandle(); - } - } - #endif - - if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE ) - { - portYIELD_WITHIN_API(); - } - } - } - else - { - traceQUEUE_PEEK( pxQueue ); - - /* We are not removing the data, so reset our read - pointer. */ - pxQueue->pcReadFrom = pcOriginalReadPosition; - - /* The data is being left in the queue, so see if there are - any other tasks waiting for the data. */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - /* Tasks that are removed from the event list will get added to - the pending ready list as the scheduler is still suspended. */ - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority than this task. */ - portYIELD_WITHIN_API(); - } - } - - } - - taskEXIT_CRITICAL(); - return pdPASS; - } - else - { - if( xTicksToWait == ( portTickType ) 0 ) - { - taskEXIT_CRITICAL(); - traceQUEUE_RECEIVE_FAILED( pxQueue ); - return errQUEUE_EMPTY; - } - else if( xEntryTimeSet == pdFALSE ) - { - vTaskSetTimeOutState( &xTimeOut ); - xEntryTimeSet = pdTRUE; - } - } - } - taskEXIT_CRITICAL(); - - taskENTER_CRITICAL(); - { - if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) - { - if( prvIsQueueEmpty( pxQueue ) ) - { - traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); - - #if ( configUSE_MUTEXES == 1 ) - { - if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) - { - portENTER_CRITICAL(); - vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder ); - portEXIT_CRITICAL(); - } - } - #endif - - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); - portYIELD_WITHIN_API(); - } - } - else - { - taskEXIT_CRITICAL(); - traceQUEUE_RECEIVE_FAILED( pxQueue ); - return errQUEUE_EMPTY; - } - } - taskEXIT_CRITICAL(); - } - } - - -#endif /* configUSE_ALTERNATIVE_API */ -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueGenericSendFromISR( xQueueHandle pxQueue, const void * const pvItemToQueue, signed portBASE_TYPE *pxHigherPriorityTaskWoken, portBASE_TYPE xCopyPosition ) -{ -signed portBASE_TYPE xReturn; -unsigned portBASE_TYPE uxSavedInterruptStatus; - - /* Similar to xQueueGenericSend, except we don't block if there is no room - in the queue. Also we don't directly wake a task that was blocked on a - queue read, instead we return a flag to say whether a context switch is - required or not (i.e. has a task with a higher priority than us been woken - by this post). */ - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); - { - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - traceQUEUE_SEND_FROM_ISR( pxQueue ); - - prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); - - /* If the queue is locked we do not alter the event list. This will - be done when the queue is unlocked later. */ - if( pxQueue->xTxLock == queueUNLOCKED ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority so record that a - context switch is required. */ - *pxHigherPriorityTaskWoken = pdTRUE; - } - } - } - else - { - /* Increment the lock count so the task that unlocks the queue - knows that data was posted while it was locked. */ - ++( pxQueue->xTxLock ); - } - - xReturn = pdPASS; - } - else - { - traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); - xReturn = errQUEUE_FULL; - } - } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking ) -{ -signed portBASE_TYPE xEntryTimeSet = pdFALSE; -xTimeOutType xTimeOut; -signed char *pcOriginalReadPosition; - - /* This function relaxes the coding standard somewhat to allow return - statements within the function itself. This is done in the interest - of execution time efficiency. */ - - for( ;; ) - { - taskENTER_CRITICAL(); - { - /* Is there data in the queue now? To be running we must be - the highest priority task wanting to access the queue. */ - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Remember our read position in case we are just peeking. */ - pcOriginalReadPosition = pxQueue->pcReadFrom; - - prvCopyDataFromQueue( pxQueue, pvBuffer ); - - if( xJustPeeking == pdFALSE ) - { - traceQUEUE_RECEIVE( pxQueue ); - - /* We are actually removing data. */ - --( pxQueue->uxMessagesWaiting ); - - #if ( configUSE_MUTEXES == 1 ) - { - if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) - { - /* Record the information required to implement - priority inheritance should it become necessary. */ - pxQueue->pxMutexHolder = xTaskGetCurrentTaskHandle(); - } - } - #endif - - if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE ) - { - portYIELD_WITHIN_API(); - } - } - } - else - { - traceQUEUE_PEEK( pxQueue ); - - /* We are not removing the data, so reset our read - pointer. */ - pxQueue->pcReadFrom = pcOriginalReadPosition; - - /* The data is being left in the queue, so see if there are - any other tasks waiting for the data. */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - /* Tasks that are removed from the event list will get added to - the pending ready list as the scheduler is still suspended. */ - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority than this task. */ - portYIELD_WITHIN_API(); - } - } - - } - - taskEXIT_CRITICAL(); - return pdPASS; - } - else - { - if( xTicksToWait == ( portTickType ) 0 ) - { - /* The queue was empty and no block time is specified (or - the block time has expired) so leave now. */ - taskEXIT_CRITICAL(); - traceQUEUE_RECEIVE_FAILED( pxQueue ); - return errQUEUE_EMPTY; - } - else if( xEntryTimeSet == pdFALSE ) - { - /* The queue was empty and a block time was specified so - configure the timeout structure. */ - vTaskSetTimeOutState( &xTimeOut ); - xEntryTimeSet = pdTRUE; - } - } - } - taskEXIT_CRITICAL(); - - /* Interrupts and other tasks can send to and receive from the queue - now the critical section has been exited. */ - - vTaskSuspendAll(); - prvLockQueue( pxQueue ); - - /* Update the timeout state to see if it has expired yet. */ - if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) - { - if( prvIsQueueEmpty( pxQueue ) ) - { - traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); - - #if ( configUSE_MUTEXES == 1 ) - { - if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) - { - portENTER_CRITICAL(); - { - vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder ); - } - portEXIT_CRITICAL(); - } - } - #endif - - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); - prvUnlockQueue( pxQueue ); - if( !xTaskResumeAll() ) - { - portYIELD_WITHIN_API(); - } - } - else - { - /* Try again. */ - prvUnlockQueue( pxQueue ); - ( void ) xTaskResumeAll(); - } - } - else - { - prvUnlockQueue( pxQueue ); - ( void ) xTaskResumeAll(); - traceQUEUE_RECEIVE_FAILED( pxQueue ); - return errQUEUE_EMPTY; - } - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void * const pvBuffer, signed portBASE_TYPE *pxTaskWoken ) -{ -signed portBASE_TYPE xReturn; -unsigned portBASE_TYPE uxSavedInterruptStatus; - - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); - { - /* We cannot block from an ISR, so check there is data available. */ - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); - - prvCopyDataFromQueue( pxQueue, pvBuffer ); - --( pxQueue->uxMessagesWaiting ); - - /* If the queue is locked we will not modify the event list. Instead - we update the lock count so the task that unlocks the queue will know - that an ISR has removed data while the queue was locked. */ - if( pxQueue->xRxLock == queueUNLOCKED ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - /* The task waiting has a higher priority than us so - force a context switch. */ - *pxTaskWoken = pdTRUE; - } - } - } - else - { - /* Increment the lock count so the task that unlocks the queue - knows that data was removed while it was locked. */ - ++( pxQueue->xRxLock ); - } - - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); - } - } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxQueueMessagesWaiting( const xQueueHandle pxQueue ) -{ -unsigned portBASE_TYPE uxReturn; - - taskENTER_CRITICAL(); - uxReturn = pxQueue->uxMessagesWaiting; - taskEXIT_CRITICAL(); - - return uxReturn; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxQueueMessagesWaitingFromISR( const xQueueHandle pxQueue ) -{ -unsigned portBASE_TYPE uxReturn; - - uxReturn = pxQueue->uxMessagesWaiting; - - return uxReturn; -} -/*-----------------------------------------------------------*/ - -void vQueueDelete( xQueueHandle pxQueue ) -{ - traceQUEUE_DELETE( pxQueue ); - vQueueUnregisterQueue( pxQueue ); - vPortFree( pxQueue->pcHead ); - vPortFree( pxQueue ); -} -/*-----------------------------------------------------------*/ - -static void prvCopyDataToQueue( xQUEUE *pxQueue, const void *pvItemToQueue, portBASE_TYPE xPosition ) -{ - if( pxQueue->uxItemSize == ( unsigned portBASE_TYPE ) 0 ) - { - #if ( configUSE_MUTEXES == 1 ) - { - if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) - { - /* The mutex is no longer being held. */ - vTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder ); - pxQueue->pxMutexHolder = NULL; - } - } - #endif - } - else if( xPosition == queueSEND_TO_BACK ) - { - memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize ); - pxQueue->pcWriteTo += pxQueue->uxItemSize; - if( pxQueue->pcWriteTo >= pxQueue->pcTail ) - { - pxQueue->pcWriteTo = pxQueue->pcHead; - } - } - else - { - memcpy( ( void * ) pxQueue->pcReadFrom, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize ); - pxQueue->pcReadFrom -= pxQueue->uxItemSize; - if( pxQueue->pcReadFrom < pxQueue->pcHead ) - { - pxQueue->pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize ); - } - } - - ++( pxQueue->uxMessagesWaiting ); -} -/*-----------------------------------------------------------*/ - -static void prvCopyDataFromQueue( xQUEUE * const pxQueue, const void *pvBuffer ) -{ - if( pxQueue->uxQueueType != queueQUEUE_IS_MUTEX ) - { - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - } -} -/*-----------------------------------------------------------*/ - -static void prvUnlockQueue( xQueueHandle pxQueue ) -{ - /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */ - - /* The lock counts contains the number of extra data items placed or - removed from the queue while the queue was locked. When a queue is - locked items can be added or removed, but the event lists cannot be - updated. */ - taskENTER_CRITICAL(); - { - /* See if data was added to the queue while it was locked. */ - while( pxQueue->xTxLock > queueLOCKED_UNMODIFIED ) - { - /* Data was posted while the queue was locked. Are any tasks - blocked waiting for data to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - /* Tasks that are removed from the event list will get added to - the pending ready list as the scheduler is still suspended. */ - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority so record that a - context switch is required. */ - vTaskMissedYield(); - } - - --( pxQueue->xTxLock ); - } - else - { - break; - } - } - - pxQueue->xTxLock = queueUNLOCKED; - } - taskEXIT_CRITICAL(); - - /* Do the same for the Rx lock. */ - taskENTER_CRITICAL(); - { - while( pxQueue->xRxLock > queueLOCKED_UNMODIFIED ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - vTaskMissedYield(); - } - - --( pxQueue->xRxLock ); - } - else - { - break; - } - } - - pxQueue->xRxLock = queueUNLOCKED; - } - taskEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - taskENTER_CRITICAL(); - xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ); - taskEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueIsQueueEmptyFromISR( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - taskENTER_CRITICAL(); - xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength ); - taskEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueIsQueueFullFromISR( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength ); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* If the queue is already full we may have to block. A critical section - is required to prevent an interrupt removing something from the queue - between the check to see if the queue is full and blocking on the queue. */ - portDISABLE_INTERRUPTS(); - { - if( prvIsQueueFull( pxQueue ) ) - { - /* The queue is full - do we want to block or just leave without - posting? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* As this is called from a coroutine we cannot block directly, but - return indicating that we need to block. */ - vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) ); - portENABLE_INTERRUPTS(); - return errQUEUE_BLOCKED; - } - else - { - portENABLE_INTERRUPTS(); - return errQUEUE_FULL; - } - } - } - portENABLE_INTERRUPTS(); - - portNOP(); - - portDISABLE_INTERRUPTS(); - { - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - /* There is room in the queue, copy the data into the queue. */ - prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK ); - xReturn = pdPASS; - - /* Were any co-routines waiting for data to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - /* In this instance the co-routine could be placed directly - into the ready list as we are within a critical section. - Instead the same pending ready list mechanism is used as if - the event were caused from within an interrupt. */ - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The co-routine waiting has a higher priority so record - that a yield might be appropriate. */ - xReturn = errQUEUE_YIELD; - } - } - } - else - { - xReturn = errQUEUE_FULL; - } - } - portENABLE_INTERRUPTS(); - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* If the queue is already empty we may have to block. A critical section - is required to prevent an interrupt adding something to the queue - between the check to see if the queue is empty and blocking on the queue. */ - portDISABLE_INTERRUPTS(); - { - if( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ) - { - /* There are no messages in the queue, do we want to block or just - leave with nothing? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* As this is a co-routine we cannot block directly, but return - indicating that we need to block. */ - vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) ); - portENABLE_INTERRUPTS(); - return errQUEUE_BLOCKED; - } - else - { - portENABLE_INTERRUPTS(); - return errQUEUE_FULL; - } - } - } - portENABLE_INTERRUPTS(); - - portNOP(); - - portDISABLE_INTERRUPTS(); - { - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Data is available from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - xReturn = pdPASS; - - /* Were any co-routines waiting for space to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - /* In this instance the co-routine could be placed directly - into the ready list as we are within a critical section. - Instead the same pending ready list mechanism is used as if - the event were caused from within an interrupt. */ - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - xReturn = errQUEUE_YIELD; - } - } - } - else - { - xReturn = pdFAIL; - } - } - portENABLE_INTERRUPTS(); - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - - - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ) -{ - /* Cannot block within an ISR so if there is no space on the queue then - exit without doing anything. */ - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK ); - - /* We only want to wake one co-routine per ISR, so check that a - co-routine has not already been woken. */ - if( !xCoRoutinePreviouslyWoken ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - return pdTRUE; - } - } - } - } - - return xCoRoutinePreviouslyWoken; -} -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxCoRoutineWoken ) -{ -signed portBASE_TYPE xReturn; - - /* We cannot block from an ISR, so check there is data available. If - not then just leave without doing anything. */ - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Copy the data from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - if( !( *pxCoRoutineWoken ) ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - *pxCoRoutineWoken = pdTRUE; - } - } - } - - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - -#if configQUEUE_REGISTRY_SIZE > 0 - - void vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcQueueName ) - { - unsigned portBASE_TYPE ux; - - /* See if there is an empty space in the registry. A NULL name denotes - a free slot. */ - for( ux = 0; ux < configQUEUE_REGISTRY_SIZE; ux++ ) - { - if( xQueueRegistry[ ux ].pcQueueName == NULL ) - { - /* Store the information on this queue. */ - xQueueRegistry[ ux ].pcQueueName = pcQueueName; - xQueueRegistry[ ux ].xHandle = xQueue; - break; - } - } - } - -#endif - /*-----------------------------------------------------------*/ - -#if configQUEUE_REGISTRY_SIZE > 0 - - static void vQueueUnregisterQueue( xQueueHandle xQueue ) - { - unsigned portBASE_TYPE ux; - - /* See if the handle of the queue being unregistered in actually in the - registry. */ - for( ux = 0; ux < configQUEUE_REGISTRY_SIZE; ux++ ) - { - if( xQueueRegistry[ ux ].xHandle == xQueue ) - { - /* Set the name to NULL to show that this slot if free again. */ - xQueueRegistry[ ux ].pcQueueName = NULL; - break; - } - } - - } - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/readme.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/readme.txt deleted file mode 100644 index 58480c56b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/readme.txt +++ /dev/null @@ -1,17 +0,0 @@ -Each real time kernel port consists of three files that contain the core kernel -components and are common to every port, and one or more files that are -specific to a particular microcontroller and or compiler. - -+ The FreeRTOS/Source directory contains the three files that are common to -every port - list.c, queue.c and tasks.c. The kernel is contained within these -three files. croutine.c implements the optional co-routine functionality - which -is normally only used on very memory limited systems. - -+ The FreeRTOS/Source/Portable directory contains the files that are specific to -a particular microcontroller and or compiler. - -+ The FreeRTOS/Source/include directory contains the real time kernel header -files. - -See the readme file in the FreeRTOS/Source/Portable directory for more -information. \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/tasks.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/tasks.c deleted file mode 100644 index ac22bf942..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/freertos/tasks.c +++ /dev/null @@ -1,2307 +0,0 @@ -/* - FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd. - - *************************************************************************** - * * - * If you are: * - * * - * + New to FreeRTOS, * - * + Wanting to learn FreeRTOS or multitasking in general quickly * - * + Looking for basic training, * - * + Wanting to improve your FreeRTOS skills and productivity * - * * - * then take a look at the FreeRTOS eBook * - * * - * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * - * http://www.FreeRTOS.org/Documentation * - * * - * A pdf reference manual is also available. Both are usually delivered * - * to your inbox within 20 minutes to two hours when purchased between 8am * - * and 8pm GMT (although please allow up to 24 hours in case of * - * exceptional circumstances). Thank you for your support! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - ***NOTE*** The exception to the GPL is included to allow you to distribute - a combined work that includes FreeRTOS without being obliged to provide the - source code for proprietary components outside of the FreeRTOS kernel. - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - more details. You should have received a copy of the GNU General Public - License and the FreeRTOS license exception along with FreeRTOS; if not it - can be viewed here: http://www.freertos.org/a00114.html and also obtained - by writing to Richard Barry, contact details for whom are available on the - FreeRTOS WEB site. - - 1 tab == 4 spaces! - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - - -#include -#include -#include - -/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining -all the API functions to use the MPU wrappers. That should only be done when -task.h is included from an application file. */ -#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE - -#include "FreeRTOS.h" -#include "task.h" -#include "StackMacros.h" - -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE - -/* - * Macro to define the amount of stack available to the idle task. - */ -#define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE - -#define tskIDLE_PRIORITY ( ( unsigned portBASE_TYPE ) 0 ) - -/* - * Task control block. A task control block (TCB) is allocated to each task, - * and stores the context of the task. - */ -typedef struct tskTaskControlBlock -{ - volatile portSTACK_TYPE *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE STRUCT. */ - - #if ( portUSING_MPU_WRAPPERS == 1 ) - xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE STRUCT. */ - #endif - - xListItem xGenericListItem; /*< List item used to place the TCB in ready and blocked queues. */ - xListItem xEventListItem; /*< List item used to place the TCB in event lists. */ - unsigned portBASE_TYPE uxPriority; /*< The priority of the task where 0 is the lowest priority. */ - portSTACK_TYPE *pxStack; /*< Points to the start of the stack. */ - signed char pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */ - - #if ( portSTACK_GROWTH > 0 ) - portSTACK_TYPE *pxEndOfStack; /*< Used for stack overflow checking on architectures where the stack grows up from low memory. */ - #endif - - #if ( portCRITICAL_NESTING_IN_TCB == 1 ) - unsigned portBASE_TYPE uxCriticalNesting; - #endif - - #if ( configUSE_TRACE_FACILITY == 1 ) - unsigned portBASE_TYPE uxTCBNumber; /*< This is used for tracing the scheduler and making debugging easier only. */ - #endif - - #if ( configUSE_MUTEXES == 1 ) - unsigned portBASE_TYPE uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */ - #endif - - #if ( configUSE_APPLICATION_TASK_TAG == 1 ) - pdTASK_HOOK_CODE pxTaskTag; - #endif - - #if ( configGENERATE_RUN_TIME_STATS == 1 ) - unsigned long ulRunTimeCounter; /*< Used for calculating how much CPU time each task is utilising. */ - #endif - -} tskTCB; - - -/* - * Some kernel aware debuggers require data to be viewed to be global, rather - * than file scope. - */ -#ifdef portREMOVE_STATIC_QUALIFIER - #define static -#endif - -/*lint -e956 */ -PRIVILEGED_DATA tskTCB * volatile pxCurrentTCB = NULL; - -/* Lists for ready and blocked tasks. --------------------*/ - -PRIVILEGED_DATA static xList pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */ -PRIVILEGED_DATA static xList xDelayedTaskList1; /*< Delayed tasks. */ -PRIVILEGED_DATA static xList xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */ -PRIVILEGED_DATA static xList * volatile pxDelayedTaskList ; /*< Points to the delayed task list currently being used. */ -PRIVILEGED_DATA static xList * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */ -PRIVILEGED_DATA static xList xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready queue when the scheduler is resumed. */ - -#if ( INCLUDE_vTaskDelete == 1 ) - - PRIVILEGED_DATA static volatile xList xTasksWaitingTermination; /*< Tasks that have been deleted - but the their memory not yet freed. */ - PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxTasksDeleted = ( unsigned portBASE_TYPE ) 0; - -#endif - -#if ( INCLUDE_vTaskSuspend == 1 ) - - PRIVILEGED_DATA static xList xSuspendedTaskList; /*< Tasks that are currently suspended. */ - -#endif - -/* File private variables. --------------------------------*/ -PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxCurrentNumberOfTasks = ( unsigned portBASE_TYPE ) 0; -PRIVILEGED_DATA static volatile portTickType xTickCount = ( portTickType ) 0; -PRIVILEGED_DATA static unsigned portBASE_TYPE uxTopUsedPriority = tskIDLE_PRIORITY; -PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxTopReadyPriority = tskIDLE_PRIORITY; -PRIVILEGED_DATA static volatile signed portBASE_TYPE xSchedulerRunning = pdFALSE; -PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxSchedulerSuspended = ( unsigned portBASE_TYPE ) pdFALSE; -PRIVILEGED_DATA static volatile unsigned portBASE_TYPE uxMissedTicks = ( unsigned portBASE_TYPE ) 0; -PRIVILEGED_DATA static volatile portBASE_TYPE xMissedYield = ( portBASE_TYPE ) pdFALSE; -PRIVILEGED_DATA static volatile portBASE_TYPE xNumOfOverflows = ( portBASE_TYPE ) 0; -PRIVILEGED_DATA static unsigned portBASE_TYPE uxTaskNumber = ( unsigned portBASE_TYPE ) 0; - -#if ( configGENERATE_RUN_TIME_STATS == 1 ) - - PRIVILEGED_DATA static char pcStatsString[ 50 ] ; - PRIVILEGED_DATA static unsigned long ulTaskSwitchedInTime = 0UL; /*< Holds the value of a timer/counter the last time a task was switched in. */ - static void prvGenerateRunTimeStatsForTasksInList( const signed char *pcWriteBuffer, xList *pxList, unsigned long ulTotalRunTime ) PRIVILEGED_FUNCTION; - -#endif - -/* Debugging and trace facilities private variables and macros. ------------*/ - -/* - * The value used to fill the stack of a task when the task is created. This - * is used purely for checking the high water mark for tasks. - */ -#define tskSTACK_FILL_BYTE ( 0xa5 ) - -/* - * Macros used by vListTask to indicate which state a task is in. - */ -#define tskBLOCKED_CHAR ( ( signed char ) 'B' ) -#define tskREADY_CHAR ( ( signed char ) 'R' ) -#define tskDELETED_CHAR ( ( signed char ) 'D' ) -#define tskSUSPENDED_CHAR ( ( signed char ) 'S' ) - -/* - * Macros and private variables used by the trace facility. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - #define tskSIZE_OF_EACH_TRACE_LINE ( ( unsigned long ) ( sizeof( unsigned long ) + sizeof( unsigned long ) ) ) - PRIVILEGED_DATA static volatile signed char * volatile pcTraceBuffer; - PRIVILEGED_DATA static signed char *pcTraceBufferStart; - PRIVILEGED_DATA static signed char *pcTraceBufferEnd; - PRIVILEGED_DATA static signed portBASE_TYPE xTracing = pdFALSE; - static unsigned portBASE_TYPE uxPreviousTask = 255; - PRIVILEGED_DATA static char pcStatusString[ 50 ]; - -#endif - -/*-----------------------------------------------------------*/ - -/* - * Macro that writes a trace of scheduler activity to a buffer. This trace - * shows which task is running when and is very useful as a debugging tool. - * As this macro is called each context switch it is a good idea to undefine - * it if not using the facility. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - #define vWriteTraceToBuffer() \ - { \ - if( xTracing ) \ - { \ - if( uxPreviousTask != pxCurrentTCB->uxTCBNumber ) \ - { \ - if( ( pcTraceBuffer + tskSIZE_OF_EACH_TRACE_LINE ) < pcTraceBufferEnd ) \ - { \ - uxPreviousTask = pxCurrentTCB->uxTCBNumber; \ - *( unsigned long * ) pcTraceBuffer = ( unsigned long ) xTickCount; \ - pcTraceBuffer += sizeof( unsigned long ); \ - *( unsigned long * ) pcTraceBuffer = ( unsigned long ) uxPreviousTask; \ - pcTraceBuffer += sizeof( unsigned long ); \ - } \ - else \ - { \ - xTracing = pdFALSE; \ - } \ - } \ - } \ - } - -#else - - #define vWriteTraceToBuffer() - -#endif -/*-----------------------------------------------------------*/ - -/* - * Place the task represented by pxTCB into the appropriate ready queue for - * the task. It is inserted at the end of the list. One quirk of this is - * that if the task being inserted is at the same priority as the currently - * executing task, then it will only be rescheduled after the currently - * executing task has been rescheduled. - */ -#define prvAddTaskToReadyQueue( pxTCB ) \ -{ \ - if( pxTCB->uxPriority > uxTopReadyPriority ) \ - { \ - uxTopReadyPriority = pxTCB->uxPriority; \ - } \ - vListInsertEnd( ( xList * ) &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ); \ -} -/*-----------------------------------------------------------*/ - -/* - * Macro that looks at the list of tasks that are currently delayed to see if - * any require waking. - * - * Tasks are stored in the queue in the order of their wake time - meaning - * once one tasks has been found whose timer has not expired we need not look - * any further down the list. - */ -#define prvCheckDelayedTasks() \ -{ \ -register tskTCB *pxTCB; \ - \ - while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ) ) != NULL ) \ - { \ - if( xTickCount < listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) ) ) \ - { \ - break; \ - } \ - vListRemove( &( pxTCB->xGenericListItem ) ); \ - /* Is the task waiting on an event also? */ \ - if( pxTCB->xEventListItem.pvContainer ) \ - { \ - vListRemove( &( pxTCB->xEventListItem ) ); \ - } \ - prvAddTaskToReadyQueue( pxTCB ); \ - } \ -} -/*-----------------------------------------------------------*/ - -/* - * Several functions take an xTaskHandle parameter that can optionally be NULL, - * where NULL is used to indicate that the handle of the currently executing - * task should be used in place of the parameter. This macro simply checks to - * see if the parameter is NULL and returns a pointer to the appropriate TCB. - */ -#define prvGetTCBFromHandle( pxHandle ) ( ( pxHandle == NULL ) ? ( tskTCB * ) pxCurrentTCB : ( tskTCB * ) pxHandle ) - - -/* File private functions. --------------------------------*/ - -/* - * Utility to ready a TCB for a given task. Mainly just copies the parameters - * into the TCB structure. - */ -static void prvInitialiseTCBVariables( tskTCB *pxTCB, const signed char * const pcName, unsigned portBASE_TYPE uxPriority, const xMemoryRegion * const xRegions, unsigned short usStackDepth ) PRIVILEGED_FUNCTION; - -/* - * Utility to ready all the lists used by the scheduler. This is called - * automatically upon the creation of the first task. - */ -static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION; - -/* - * The idle task, which as all tasks is implemented as a never ending loop. - * The idle task is automatically created and added to the ready lists upon - * creation of the first user task. - * - * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific - * language extensions. The equivalent prototype for this function is: - * - * void prvIdleTask( void *pvParameters ); - * - */ -static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ); - -/* - * Utility to free all memory allocated by the scheduler to hold a TCB, - * including the stack pointed to by the TCB. - * - * This does not free memory allocated by the task itself (i.e. memory - * allocated by calls to pvPortMalloc from within the tasks application code). - */ -#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) - - static void prvDeleteTCB( tskTCB *pxTCB ) PRIVILEGED_FUNCTION; - -#endif - -/* - * Used only by the idle task. This checks to see if anything has been placed - * in the list of tasks waiting to be deleted. If so the task is cleaned up - * and its TCB deleted. - */ -static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION; - -/* - * Allocates memory from the heap for a TCB and associated stack. Checks the - * allocation was successful. - */ -static tskTCB *prvAllocateTCBAndStack( unsigned short usStackDepth, portSTACK_TYPE *puxStackBuffer ) PRIVILEGED_FUNCTION; - -/* - * Called from vTaskList. vListTasks details all the tasks currently under - * control of the scheduler. The tasks may be in one of a number of lists. - * prvListTaskWithinSingleList accepts a list and details the tasks from - * within just that list. - * - * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM - * NORMAL APPLICATION CODE. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - static void prvListTaskWithinSingleList( const signed char *pcWriteBuffer, xList *pxList, signed char cStatus ) PRIVILEGED_FUNCTION; - -#endif - -/* - * When a task is created, the stack of the task is filled with a known value. - * This function determines the 'high water mark' of the task stack by - * determining how much of the stack remains at the original preset value. - */ -#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) - - static unsigned short usTaskCheckFreeStackSpace( const unsigned char * pucStackByte ) PRIVILEGED_FUNCTION; - -#endif - - -/*lint +e956 */ - - - -/*----------------------------------------------------------- - * TASK CREATION API documented in task.h - *----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskGenericCreate( pdTASK_CODE pxTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions ) -{ -signed portBASE_TYPE xReturn; -tskTCB * pxNewTCB; -portBASE_TYPE xRunPrivileged; - - /* Allocate the memory required by the TCB and stack for the new task, - checking that the allocation was successful. */ - pxNewTCB = prvAllocateTCBAndStack( usStackDepth, puxStackBuffer ); - - if( pxNewTCB != NULL ) - { - portSTACK_TYPE *pxTopOfStack; - - /* Should the task be created in privileged mode? */ - if( ( uxPriority & portPRIVILEGE_BIT ) != 0x00 ) - { - xRunPrivileged = pdTRUE; - } - else - { - xRunPrivileged = pdFALSE; - } - uxPriority &= ~portPRIVILEGE_BIT; - - /* Calculate the top of stack address. This depends on whether the - stack grows from high memory to low (as per the 80x86) or visa versa. - portSTACK_GROWTH is used to make the result positive or negative as - required by the port. */ - #if( portSTACK_GROWTH < 0 ) - { - pxTopOfStack = pxNewTCB->pxStack + ( usStackDepth - 1 ); - pxTopOfStack = ( portSTACK_TYPE * ) ( ( ( unsigned long ) pxTopOfStack ) & ( ( unsigned long ) ~portBYTE_ALIGNMENT_MASK ) ); - } - #else - { - pxTopOfStack = pxNewTCB->pxStack; - - /* If we want to use stack checking on architectures that use - a positive stack growth direction then we also need to store the - other extreme of the stack space. */ - pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( usStackDepth - 1 ); - } - #endif - - /* Setup the newly allocated TCB with the initial state of the task. */ - prvInitialiseTCBVariables( pxNewTCB, pcName, uxPriority, xRegions, usStackDepth ); - - /* Initialize the TCB stack to look as if the task was already running, - but had been interrupted by the scheduler. The return address is set - to the start of the task function. Once the stack has been initialised - the top of stack variable is updated. */ - #if( portUSING_MPU_WRAPPERS == 1 ) - { - pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged ); - } - #else - { - pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); - ( void ) xRunPrivileged; - } - #endif - - /* We are going to manipulate the task queues to add this task to a - ready list, so must make sure no interrupts occur. */ - portENTER_CRITICAL(); - { - uxCurrentNumberOfTasks++; - if( uxCurrentNumberOfTasks == ( unsigned portBASE_TYPE ) 1 ) - { - /* As this is the first task it must also be the current task. */ - pxCurrentTCB = pxNewTCB; - - /* This is the first task to be created so do the preliminary - initialisation required. We will not recover if this call - fails, but we will report the failure. */ - prvInitialiseTaskLists(); - } - else - { - /* If the scheduler is not already running, make this task the - current task if it is the highest priority task to be created - so far. */ - if( xSchedulerRunning == pdFALSE ) - { - if( pxCurrentTCB->uxPriority <= uxPriority ) - { - pxCurrentTCB = pxNewTCB; - } - } - } - - /* Remember the top priority to make context switching faster. Use - the priority in pxNewTCB as this has been capped to a valid value. */ - if( pxNewTCB->uxPriority > uxTopUsedPriority ) - { - uxTopUsedPriority = pxNewTCB->uxPriority; - } - - #if ( configUSE_TRACE_FACILITY == 1 ) - { - /* Add a counter into the TCB for tracing only. */ - pxNewTCB->uxTCBNumber = uxTaskNumber; - } - #endif - uxTaskNumber++; - - prvAddTaskToReadyQueue( pxNewTCB ); - - xReturn = pdPASS; - traceTASK_CREATE( pxNewTCB ); - } - portEXIT_CRITICAL(); - } - else - { - xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - traceTASK_CREATE_FAILED( pxNewTCB ); - } - - if( xReturn == pdPASS ) - { - if( ( void * ) pxCreatedTask != NULL ) - { - /* Pass the TCB out - in an anonymous way. The calling function/ - task can use this as a handle to delete the task later if - required.*/ - *pxCreatedTask = ( xTaskHandle ) pxNewTCB; - } - - if( xSchedulerRunning != pdFALSE ) - { - /* If the created task is of a higher priority than the current task - then it should run now. */ - if( pxCurrentTCB->uxPriority < uxPriority ) - { - portYIELD_WITHIN_API(); - } - } - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelete == 1 ) - - void vTaskDelete( xTaskHandle pxTaskToDelete ) - { - tskTCB *pxTCB; - - portENTER_CRITICAL(); - { - /* Ensure a yield is performed if the current task is being - deleted. */ - if( pxTaskToDelete == pxCurrentTCB ) - { - pxTaskToDelete = NULL; - } - - /* If null is passed in here then we are deleting ourselves. */ - pxTCB = prvGetTCBFromHandle( pxTaskToDelete ); - - /* Remove task from the ready list and place in the termination list. - This will stop the task from be scheduled. The idle task will check - the termination list and free up any memory allocated by the - scheduler for the TCB and stack. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Is the task waiting on an event also? */ - if( pxTCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - } - - vListInsertEnd( ( xList * ) &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) ); - - /* Increment the ucTasksDeleted variable so the idle task knows - there is a task that has been deleted and that it should therefore - check the xTasksWaitingTermination list. */ - ++uxTasksDeleted; - - /* Increment the uxTaskNumberVariable also so kernel aware debuggers - can detect that the task lists need re-generating. */ - uxTaskNumber++; - - traceTASK_DELETE( pxTCB ); - } - portEXIT_CRITICAL(); - - /* Force a reschedule if we have just deleted the current task. */ - if( xSchedulerRunning != pdFALSE ) - { - if( ( void * ) pxTaskToDelete == NULL ) - { - portYIELD_WITHIN_API(); - } - } - } - -#endif - - - - - - -/*----------------------------------------------------------- - * TASK CONTROL API documented in task.h - *----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelayUntil == 1 ) - - void vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement ) - { - portTickType xTimeToWake; - portBASE_TYPE xAlreadyYielded, xShouldDelay = pdFALSE; - - vTaskSuspendAll(); - { - /* Generate the tick time at which the task wants to wake. */ - xTimeToWake = *pxPreviousWakeTime + xTimeIncrement; - - if( xTickCount < *pxPreviousWakeTime ) - { - /* The tick count has overflowed since this function was - lasted called. In this case the only time we should ever - actually delay is if the wake time has also overflowed, - and the wake time is greater than the tick time. When this - is the case it is as if neither time had overflowed. */ - if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xTickCount ) ) - { - xShouldDelay = pdTRUE; - } - } - else - { - /* The tick time has not overflowed. In this case we will - delay if either the wake time has overflowed, and/or the - tick time is less than the wake time. */ - if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xTickCount ) ) - { - xShouldDelay = pdTRUE; - } - } - - /* Update the wake time ready for the next call. */ - *pxPreviousWakeTime = xTimeToWake; - - if( xShouldDelay ) - { - traceTASK_DELAY_UNTIL(); - - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - } - xAlreadyYielded = xTaskResumeAll(); - - /* Force a reschedule if xTaskResumeAll has not already done so, we may - have put ourselves to sleep. */ - if( !xAlreadyYielded ) - { - portYIELD_WITHIN_API(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelay == 1 ) - - void vTaskDelay( portTickType xTicksToDelay ) - { - portTickType xTimeToWake; - signed portBASE_TYPE xAlreadyYielded = pdFALSE; - - /* A delay time of zero just forces a reschedule. */ - if( xTicksToDelay > ( portTickType ) 0 ) - { - vTaskSuspendAll(); - { - traceTASK_DELAY(); - - /* A task that is removed from the event list while the - scheduler is suspended will not get placed in the ready - list or removed from the blocked list until the scheduler - is resumed. - - This task cannot be in an event list as it is the currently - executing task. */ - - /* Calculate the time to wake - this may overflow but this is - not a problem. */ - xTimeToWake = xTickCount + xTicksToDelay; - - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - xAlreadyYielded = xTaskResumeAll(); - } - - /* Force a reschedule if xTaskResumeAll has not already done so, we may - have put ourselves to sleep. */ - if( !xAlreadyYielded ) - { - portYIELD_WITHIN_API(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_uxTaskPriorityGet == 1 ) - - unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ) - { - tskTCB *pxTCB; - unsigned portBASE_TYPE uxReturn; - - portENTER_CRITICAL(); - { - /* If null is passed in here then we are changing the - priority of the calling function. */ - pxTCB = prvGetTCBFromHandle( pxTask ); - uxReturn = pxTCB->uxPriority; - } - portEXIT_CRITICAL(); - - return uxReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskPrioritySet == 1 ) - - void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ) - { - tskTCB *pxTCB; - unsigned portBASE_TYPE uxCurrentPriority, xYieldRequired = pdFALSE; - - /* Ensure the new priority is valid. */ - if( uxNewPriority >= configMAX_PRIORITIES ) - { - uxNewPriority = configMAX_PRIORITIES - 1; - } - - portENTER_CRITICAL(); - { - if( pxTask == pxCurrentTCB ) - { - pxTask = NULL; - } - - /* If null is passed in here then we are changing the - priority of the calling function. */ - pxTCB = prvGetTCBFromHandle( pxTask ); - - traceTASK_PRIORITY_SET( pxTask, uxNewPriority ); - - #if ( configUSE_MUTEXES == 1 ) - { - uxCurrentPriority = pxTCB->uxBasePriority; - } - #else - { - uxCurrentPriority = pxTCB->uxPriority; - } - #endif - - if( uxCurrentPriority != uxNewPriority ) - { - /* The priority change may have readied a task of higher - priority than the calling task. */ - if( uxNewPriority > uxCurrentPriority ) - { - if( pxTask != NULL ) - { - /* The priority of another task is being raised. If we - were raising the priority of the currently running task - there would be no need to switch as it must have already - been the highest priority task. */ - xYieldRequired = pdTRUE; - } - } - else if( pxTask == NULL ) - { - /* Setting our own priority down means there may now be another - task of higher priority that is ready to execute. */ - xYieldRequired = pdTRUE; - } - - - - #if ( configUSE_MUTEXES == 1 ) - { - /* Only change the priority being used if the task is not - currently using an inherited priority. */ - if( pxTCB->uxBasePriority == pxTCB->uxPriority ) - { - pxTCB->uxPriority = uxNewPriority; - } - - /* The base priority gets set whatever. */ - pxTCB->uxBasePriority = uxNewPriority; - } - #else - { - pxTCB->uxPriority = uxNewPriority; - } - #endif - - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( configMAX_PRIORITIES - ( portTickType ) uxNewPriority ) ); - - /* If the task is in the blocked or suspended list we need do - nothing more than change it's priority variable. However, if - the task is in a ready list it needs to be removed and placed - in the queue appropriate to its new priority. */ - if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxCurrentPriority ] ), &( pxTCB->xGenericListItem ) ) ) - { - /* The task is currently in its ready list - remove before adding - it to it's new ready list. As we are in a critical section we - can do this even if the scheduler is suspended. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - } - - if( xYieldRequired == pdTRUE ) - { - portYIELD_WITHIN_API(); - } - } - } - portEXIT_CRITICAL(); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - void vTaskSuspend( xTaskHandle pxTaskToSuspend ) - { - tskTCB *pxTCB; - - portENTER_CRITICAL(); - { - /* Ensure a yield is performed if the current task is being - suspended. */ - if( pxTaskToSuspend == pxCurrentTCB ) - { - pxTaskToSuspend = NULL; - } - - /* If null is passed in here then we are suspending ourselves. */ - pxTCB = prvGetTCBFromHandle( pxTaskToSuspend ); - - traceTASK_SUSPEND( pxTCB ); - - /* Remove task from the ready/delayed list and place in the suspended list. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Is the task waiting on an event also? */ - if( pxTCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - } - - vListInsertEnd( ( xList * ) &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ); - } - portEXIT_CRITICAL(); - - /* We may have just suspended the current task. */ - if( ( void * ) pxTaskToSuspend == NULL ) - { - portYIELD_WITHIN_API(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - signed portBASE_TYPE xTaskIsTaskSuspended( xTaskHandle xTask ) - { - portBASE_TYPE xReturn = pdFALSE; - const tskTCB * const pxTCB = ( tskTCB * ) xTask; - - /* Is the task we are attempting to resume actually in the - suspended list? */ - if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE ) - { - /* Has the task already been resumed from within an ISR? */ - if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdTRUE ) - { - /* Is it in the suspended list because it is in the - Suspended state? It is possible to be in the suspended - list because it is blocked on a task with no timeout - specified. */ - if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) == pdTRUE ) - { - xReturn = pdTRUE; - } - } - } - - return xReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - void vTaskResume( xTaskHandle pxTaskToResume ) - { - tskTCB *pxTCB; - - /* Remove the task from whichever list it is currently in, and place - it in the ready list. */ - pxTCB = ( tskTCB * ) pxTaskToResume; - - /* The parameter cannot be NULL as it is impossible to resume the - currently executing task. */ - if( ( pxTCB != NULL ) && ( pxTCB != pxCurrentTCB ) ) - { - portENTER_CRITICAL(); - { - if( xTaskIsTaskSuspended( pxTCB ) == pdTRUE ) - { - traceTASK_RESUME( pxTCB ); - - /* As we are in a critical section we can access the ready - lists even if the scheduler is suspended. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - - /* We may have just resumed a higher priority task. */ - if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - /* This yield may not cause the task just resumed to run, but - will leave the lists in the correct state for the next yield. */ - portYIELD_WITHIN_API(); - } - } - } - portEXIT_CRITICAL(); - } - } - -#endif - -/*-----------------------------------------------------------*/ - -#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ) - { - portBASE_TYPE xYieldRequired = pdFALSE; - tskTCB *pxTCB; - - pxTCB = ( tskTCB * ) pxTaskToResume; - - if( xTaskIsTaskSuspended( pxTCB ) == pdTRUE ) - { - traceTASK_RESUME_FROM_ISR( pxTCB ); - - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - xYieldRequired = ( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ); - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - } - else - { - /* We cannot access the delayed or ready lists, so will hold this - task pending until the scheduler is resumed, at which point a - yield will be performed if necessary. */ - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); - } - } - - return xYieldRequired; - } - -#endif - - - - -/*----------------------------------------------------------- - * PUBLIC SCHEDULER CONTROL documented in task.h - *----------------------------------------------------------*/ - - -void vTaskStartScheduler( void ) -{ -portBASE_TYPE xReturn; - - /* Add the idle task at the lowest priority. */ - xReturn = xTaskCreate( prvIdleTask, ( signed char * ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), ( xTaskHandle * ) NULL ); - - if( xReturn == pdPASS ) - { - /* Interrupts are turned off here, to ensure a tick does not occur - before or during the call to xPortStartScheduler(). The stacks of - the created tasks contain a status word with interrupts switched on - so interrupts will automatically get re-enabled when the first task - starts to run. - - STEPPING THROUGH HERE USING A DEBUGGER CAN CAUSE BIG PROBLEMS IF THE - DEBUGGER ALLOWS INTERRUPTS TO BE PROCESSED. */ - portDISABLE_INTERRUPTS(); - - xSchedulerRunning = pdTRUE; - xTickCount = ( portTickType ) 0; - - /* If configGENERATE_RUN_TIME_STATS is defined then the following - macro must be defined to configure the timer/counter used to generate - the run time counter time base. */ - portCONFIGURE_TIMER_FOR_RUN_TIME_STATS(); - - /* Setting up the timer tick is hardware specific and thus in the - portable interface. */ - if( xPortStartScheduler() ) - { - /* Should not reach here as if the scheduler is running the - function will not return. */ - } - else - { - /* Should only reach here if a task calls xTaskEndScheduler(). */ - } - } -} -/*-----------------------------------------------------------*/ - -void vTaskEndScheduler( void ) -{ - /* Stop the scheduler interrupts and call the portable scheduler end - routine so the original ISRs can be restored if necessary. The port - layer must ensure interrupts enable bit is left in the correct state. */ - portDISABLE_INTERRUPTS(); - xSchedulerRunning = pdFALSE; - vPortEndScheduler(); -} -/*----------------------------------------------------------*/ - -void vTaskSuspendAll( void ) -{ - /* A critical section is not required as the variable is of type - portBASE_TYPE. */ - ++uxSchedulerSuspended; -} -/*----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskResumeAll( void ) -{ -register tskTCB *pxTCB; -signed portBASE_TYPE xAlreadyYielded = pdFALSE; - - /* It is possible that an ISR caused a task to be removed from an event - list while the scheduler was suspended. If this was the case then the - removed task will have been added to the xPendingReadyList. Once the - scheduler has been resumed it is safe to move all the pending ready - tasks from this list into their appropriate ready list. */ - portENTER_CRITICAL(); - { - --uxSchedulerSuspended; - - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - if( uxCurrentNumberOfTasks > ( unsigned portBASE_TYPE ) 0 ) - { - portBASE_TYPE xYieldRequired = pdFALSE; - - /* Move any readied tasks from the pending list into the - appropriate ready list. */ - while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xPendingReadyList ) ) ) != NULL ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - - /* If we have moved a task that has a priority higher than - the current task then we should yield. */ - if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - xYieldRequired = pdTRUE; - } - } - - /* If any ticks occurred while the scheduler was suspended then - they should be processed now. This ensures the tick count does not - slip, and that any delayed tasks are resumed at the correct time. */ - if( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) - { - while( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) - { - vTaskIncrementTick(); - --uxMissedTicks; - } - - /* As we have processed some ticks it is appropriate to yield - to ensure the highest priority task that is ready to run is - the task actually running. */ - #if configUSE_PREEMPTION == 1 - { - xYieldRequired = pdTRUE; - } - #endif - } - - if( ( xYieldRequired == pdTRUE ) || ( xMissedYield == pdTRUE ) ) - { - xAlreadyYielded = pdTRUE; - xMissedYield = pdFALSE; - portYIELD_WITHIN_API(); - } - } - } - } - portEXIT_CRITICAL(); - - return xAlreadyYielded; -} - - - - - - -/*----------------------------------------------------------- - * PUBLIC TASK UTILITIES documented in task.h - *----------------------------------------------------------*/ - - - -portTickType xTaskGetTickCount( void ) -{ -portTickType xTicks; - - /* Critical section required if running on a 16 bit processor. */ - portENTER_CRITICAL(); - { - xTicks = xTickCount; - } - portEXIT_CRITICAL(); - - return xTicks; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ) -{ - /* A critical section is not required because the variables are of type - portBASE_TYPE. */ - return uxCurrentNumberOfTasks; -} -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - void vTaskList( signed char *pcWriteBuffer ) - { - unsigned portBASE_TYPE uxQueue; - - /* This is a VERY costly function that should be used for debug only. - It leaves interrupts disabled for a LONG time. */ - - vTaskSuspendAll(); - { - /* Run through all the lists that could potentially contain a TCB and - report the task name, state and stack high water mark. */ - - pcWriteBuffer[ 0 ] = ( signed char ) 0x00; - strcat( ( char * ) pcWriteBuffer, ( const char * ) "\r\n" ); - - uxQueue = uxTopUsedPriority + 1; - - do - { - uxQueue--; - - if( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), tskREADY_CHAR ); - } - }while( uxQueue > ( unsigned short ) tskIDLE_PRIORITY ); - - if( !listLIST_IS_EMPTY( pxDelayedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, tskBLOCKED_CHAR ); - } - - if( !listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, tskBLOCKED_CHAR ); - } - - #if( INCLUDE_vTaskDelete == 1 ) - { - if( !listLIST_IS_EMPTY( &xTasksWaitingTermination ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xTasksWaitingTermination, tskDELETED_CHAR ); - } - } - #endif - - #if ( INCLUDE_vTaskSuspend == 1 ) - { - if( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xSuspendedTaskList, tskSUSPENDED_CHAR ); - } - } - #endif - } - xTaskResumeAll(); - } - -#endif -/*----------------------------------------------------------*/ - -#if ( configGENERATE_RUN_TIME_STATS == 1 ) - - void vTaskGetRunTimeStats( signed char *pcWriteBuffer ) - { - unsigned portBASE_TYPE uxQueue; - unsigned long ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE(); - - /* This is a VERY costly function that should be used for debug only. - It leaves interrupts disabled for a LONG time. */ - - vTaskSuspendAll(); - { - /* Run through all the lists that could potentially contain a TCB, - generating a table of run timer percentages in the provided - buffer. */ - - pcWriteBuffer[ 0 ] = ( signed char ) 0x00; - strcat( ( char * ) pcWriteBuffer, ( const char * ) "\r\n" ); - - uxQueue = uxTopUsedPriority + 1; - - do - { - uxQueue--; - - if( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) ) - { - prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), ulTotalRunTime ); - } - }while( uxQueue > ( unsigned short ) tskIDLE_PRIORITY ); - - if( !listLIST_IS_EMPTY( pxDelayedTaskList ) ) - { - prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, ulTotalRunTime ); - } - - if( !listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) ) - { - prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, ulTotalRunTime ); - } - - #if ( INCLUDE_vTaskDelete == 1 ) - { - if( !listLIST_IS_EMPTY( &xTasksWaitingTermination ) ) - { - prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, ( xList * ) &xTasksWaitingTermination, ulTotalRunTime ); - } - } - #endif - - #if ( INCLUDE_vTaskSuspend == 1 ) - { - if( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) - { - prvGenerateRunTimeStatsForTasksInList( pcWriteBuffer, ( xList * ) &xSuspendedTaskList, ulTotalRunTime ); - } - } - #endif - } - xTaskResumeAll(); - } - -#endif -/*----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - void vTaskStartTrace( signed char * pcBuffer, unsigned long ulBufferSize ) - { - portENTER_CRITICAL(); - { - pcTraceBuffer = ( signed char * )pcBuffer; - pcTraceBufferStart = pcBuffer; - pcTraceBufferEnd = pcBuffer + ( ulBufferSize - tskSIZE_OF_EACH_TRACE_LINE ); - xTracing = pdTRUE; - } - portEXIT_CRITICAL(); - } - -#endif -/*----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - unsigned long ulTaskEndTrace( void ) - { - unsigned long ulBufferLength; - - portENTER_CRITICAL(); - xTracing = pdFALSE; - portEXIT_CRITICAL(); - - ulBufferLength = ( unsigned long ) ( pcTraceBuffer - pcTraceBufferStart ); - - return ulBufferLength; - } - -#endif - - - -/*----------------------------------------------------------- - * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES - * documented in task.h - *----------------------------------------------------------*/ - - -void vTaskIncrementTick( void ) -{ - /* Called by the portable layer each time a tick interrupt occurs. - Increments the tick then checks to see if the new tick value will cause any - tasks to be unblocked. */ - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - ++xTickCount; - if( xTickCount == ( portTickType ) 0 ) - { - xList *pxTemp; - - /* Tick count has overflowed so we need to swap the delay lists. - If there are any items in pxDelayedTaskList here then there is - an error! */ - pxTemp = pxDelayedTaskList; - pxDelayedTaskList = pxOverflowDelayedTaskList; - pxOverflowDelayedTaskList = pxTemp; - xNumOfOverflows++; - } - - /* See if this tick has made a timeout expire. */ - prvCheckDelayedTasks(); - } - else - { - ++uxMissedTicks; - - /* The tick hook gets called at regular intervals, even if the - scheduler is locked. */ - #if ( configUSE_TICK_HOOK == 1 ) - { - extern void vApplicationTickHook( void ); - - vApplicationTickHook(); - } - #endif - } - - #if ( configUSE_TICK_HOOK == 1 ) - { - extern void vApplicationTickHook( void ); - - /* Guard against the tick hook being called when the missed tick - count is being unwound (when the scheduler is being unlocked. */ - if( uxMissedTicks == 0 ) - { - vApplicationTickHook(); - } - } - #endif - - traceTASK_INCREMENT_TICK( xTickCount ); -} -/*-----------------------------------------------------------*/ - -#if ( ( INCLUDE_vTaskCleanUpResources == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - void vTaskCleanUpResources( void ) - { - unsigned short usQueue; - volatile tskTCB *pxTCB; - - usQueue = ( unsigned short ) uxTopUsedPriority + ( unsigned short ) 1; - - /* Remove any TCB's from the ready queues. */ - do - { - usQueue--; - - while( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ usQueue ] ) ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &( pxReadyTasksLists[ usQueue ] ) ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - }while( usQueue > ( unsigned short ) tskIDLE_PRIORITY ); - - /* Remove any TCB's from the delayed queue. */ - while( !listLIST_IS_EMPTY( &xDelayedTaskList1 ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList1 ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - /* Remove any TCB's from the overflow delayed queue. */ - while( !listLIST_IS_EMPTY( &xDelayedTaskList2 ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList2 ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - while( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xSuspendedTaskList ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_APPLICATION_TASK_TAG == 1 ) - - void vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxTagValue ) - { - tskTCB *xTCB; - - /* If xTask is NULL then we are setting our own task hook. */ - if( xTask == NULL ) - { - xTCB = ( tskTCB * ) pxCurrentTCB; - } - else - { - xTCB = ( tskTCB * ) xTask; - } - - /* Save the hook function in the TCB. A critical section is required as - the value can be accessed from an interrupt. */ - portENTER_CRITICAL(); - xTCB->pxTaskTag = pxTagValue; - portEXIT_CRITICAL(); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_APPLICATION_TASK_TAG == 1 ) - - pdTASK_HOOK_CODE xTaskGetApplicationTaskTag( xTaskHandle xTask ) - { - tskTCB *xTCB; - pdTASK_HOOK_CODE xReturn; - - /* If xTask is NULL then we are setting our own task hook. */ - if( xTask == NULL ) - { - xTCB = ( tskTCB * ) pxCurrentTCB; - } - else - { - xTCB = ( tskTCB * ) xTask; - } - - /* Save the hook function in the TCB. A critical section is required as - the value can be accessed from an interrupt. */ - portENTER_CRITICAL(); - xReturn = xTCB->pxTaskTag; - portEXIT_CRITICAL(); - - return xReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_APPLICATION_TASK_TAG == 1 ) - - portBASE_TYPE xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter ) - { - tskTCB *xTCB; - portBASE_TYPE xReturn; - - /* If xTask is NULL then we are calling our own task hook. */ - if( xTask == NULL ) - { - xTCB = ( tskTCB * ) pxCurrentTCB; - } - else - { - xTCB = ( tskTCB * ) xTask; - } - - if( xTCB->pxTaskTag != NULL ) - { - xReturn = xTCB->pxTaskTag( pvParameter ); - } - else - { - xReturn = pdFAIL; - } - - return xReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -void vTaskSwitchContext( void ) -{ - if( uxSchedulerSuspended != ( unsigned portBASE_TYPE ) pdFALSE ) - { - /* The scheduler is currently suspended - do not allow a context - switch. */ - xMissedYield = pdTRUE; - return; - } - - traceTASK_SWITCHED_OUT(); - - #if ( configGENERATE_RUN_TIME_STATS == 1 ) - { - unsigned long ulTempCounter = portGET_RUN_TIME_COUNTER_VALUE(); - - /* Add the amount of time the task has been running to the accumulated - time so far. The time the task started running was stored in - ulTaskSwitchedInTime. Note that there is no overflow protection here - so count values are only valid until the timer overflows. Generally - this will be about 1 hour assuming a 1uS timer increment. */ - pxCurrentTCB->ulRunTimeCounter += ( ulTempCounter - ulTaskSwitchedInTime ); - ulTaskSwitchedInTime = ulTempCounter; - } - #endif - - taskFIRST_CHECK_FOR_STACK_OVERFLOW(); - taskSECOND_CHECK_FOR_STACK_OVERFLOW(); - - /* Find the highest priority queue that contains ready tasks. */ - while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) ) - { - --uxTopReadyPriority; - } - - /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the tasks of the - same priority get an equal share of the processor time. */ - listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) ); - - traceTASK_SWITCHED_IN(); - vWriteTraceToBuffer(); -} -/*-----------------------------------------------------------*/ - -void vTaskPlaceOnEventList( const xList * const pxEventList, portTickType xTicksToWait ) -{ -portTickType xTimeToWake; - - /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE - SCHEDULER SUSPENDED. */ - - /* Place the event list item of the TCB in the appropriate event list. - This is placed in the list in priority order so the highest priority task - is the first to be woken by the event. */ - vListInsert( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) ); - - /* We must remove ourselves from the ready list before adding ourselves - to the blocked list as the same list item is used for both lists. We have - exclusive access to the ready lists as the scheduler is locked. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - - #if ( INCLUDE_vTaskSuspend == 1 ) - { - if( xTicksToWait == portMAX_DELAY ) - { - /* Add ourselves to the suspended task list instead of a delayed task - list to ensure we are not woken by a timing event. We will block - indefinitely. */ - vListInsertEnd( ( xList * ) &xSuspendedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* Calculate the time at which the task should be woken if the event does - not occur. This may overflow but this doesn't matter. */ - xTimeToWake = xTickCount + xTicksToWait; - - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - } - #else - { - /* Calculate the time at which the task should be woken if the event does - not occur. This may overflow but this doesn't matter. */ - xTimeToWake = xTickCount + xTicksToWait; - - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - #endif -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskRemoveFromEventList( const xList * const pxEventList ) -{ -tskTCB *pxUnblockedTCB; -portBASE_TYPE xReturn; - - /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE - SCHEDULER SUSPENDED. It can also be called from within an ISR. */ - - /* The event list is sorted in priority order, so we can remove the - first in the list, remove the TCB from the delayed list, and add - it to the ready list. - - If an event is for a queue that is locked then this function will never - get called - the lock count on the queue will get modified instead. This - means we can always expect exclusive access to the event list here. */ - pxUnblockedTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); - vListRemove( &( pxUnblockedTCB->xEventListItem ) ); - - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - vListRemove( &( pxUnblockedTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxUnblockedTCB ); - } - else - { - /* We cannot access the delayed or ready lists, so will hold this - task pending until the scheduler is resumed. */ - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); - } - - if( pxUnblockedTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - /* Return true if the task removed from the event list has - a higher priority than the calling task. This allows - the calling task to know if it should force a context - switch now. */ - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vTaskSetTimeOutState( xTimeOutType * const pxTimeOut ) -{ - pxTimeOut->xOverflowCount = xNumOfOverflows; - pxTimeOut->xTimeOnEntering = xTickCount; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType * const pxTimeOut, portTickType * const pxTicksToWait ) -{ -portBASE_TYPE xReturn; - - portENTER_CRITICAL(); - { - #if ( INCLUDE_vTaskSuspend == 1 ) - /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is - the maximum block time then the task should block indefinitely, and - therefore never time out. */ - if( *pxTicksToWait == portMAX_DELAY ) - { - xReturn = pdFALSE; - } - else /* We are not blocking indefinitely, perform the checks below. */ - #endif - - if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( ( portTickType ) xTickCount >= ( portTickType ) pxTimeOut->xTimeOnEntering ) ) - { - /* The tick count is greater than the time at which vTaskSetTimeout() - was called, but has also overflowed since vTaskSetTimeOut() was called. - It must have wrapped all the way around and gone past us again. This - passed since vTaskSetTimeout() was called. */ - xReturn = pdTRUE; - } - else if( ( ( portTickType ) xTickCount - ( portTickType ) pxTimeOut->xTimeOnEntering ) < ( portTickType ) *pxTicksToWait ) - { - /* Not a genuine timeout. Adjust parameters for time remaining. */ - *pxTicksToWait -= ( ( portTickType ) xTickCount - ( portTickType ) pxTimeOut->xTimeOnEntering ); - vTaskSetTimeOutState( pxTimeOut ); - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - } - portEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vTaskMissedYield( void ) -{ - xMissedYield = pdTRUE; -} - -/* - * ----------------------------------------------------------- - * The Idle task. - * ---------------------------------------------------------- - * - * The portTASK_FUNCTION() macro is used to allow port/compiler specific - * language extensions. The equivalent prototype for this function is: - * - * void prvIdleTask( void *pvParameters ); - * - */ -static portTASK_FUNCTION( prvIdleTask, pvParameters ) -{ - /* Stop warnings. */ - ( void ) pvParameters; - - for( ;; ) - { - /* See if any tasks have been deleted. */ - prvCheckTasksWaitingTermination(); - - #if ( configUSE_PREEMPTION == 0 ) - { - /* If we are not using preemption we keep forcing a task switch to - see if any other task has become available. If we are using - preemption we don't need to do this as any task becoming available - will automatically get the processor anyway. */ - taskYIELD(); - } - #endif - - #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) - { - /* When using preemption tasks of equal priority will be - timesliced. If a task that is sharing the idle priority is ready - to run then the idle task should yield before the end of the - timeslice. - - A critical region is not required here as we are just reading from - the list, and an occasional incorrect value will not matter. If - the ready list at the idle priority contains more than one task - then a task other than the idle task is ready to execute. */ - if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( unsigned portBASE_TYPE ) 1 ) - { - taskYIELD(); - } - } - #endif - - #if ( configUSE_IDLE_HOOK == 1 ) - { - extern void vApplicationIdleHook( void ); - - /* Call the user defined function from within the idle task. This - allows the application designer to add background functionality - without the overhead of a separate task. - NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, - CALL A FUNCTION THAT MIGHT BLOCK. */ - vApplicationIdleHook(); - } - #endif - } -} /*lint !e715 pvParameters is not accessed but all task functions require the same prototype. */ - - - - - - - -/*----------------------------------------------------------- - * File private functions documented at the top of the file. - *----------------------------------------------------------*/ - - - -static void prvInitialiseTCBVariables( tskTCB *pxTCB, const signed char * const pcName, unsigned portBASE_TYPE uxPriority, const xMemoryRegion * const xRegions, unsigned short usStackDepth ) -{ - /* Store the function name in the TCB. */ - #if configMAX_TASK_NAME_LEN > 1 - { - /* Don't bring strncpy into the build unnecessarily. */ - strncpy( ( char * ) pxTCB->pcTaskName, ( const char * ) pcName, ( unsigned short ) configMAX_TASK_NAME_LEN ); - } - #endif - pxTCB->pcTaskName[ ( unsigned short ) configMAX_TASK_NAME_LEN - ( unsigned short ) 1 ] = '\0'; - - /* This is used as an array index so must ensure it's not too large. First - remove the privilege bit if one is present. */ - if( uxPriority >= configMAX_PRIORITIES ) - { - uxPriority = configMAX_PRIORITIES - 1; - } - - pxTCB->uxPriority = uxPriority; - #if ( configUSE_MUTEXES == 1 ) - { - pxTCB->uxBasePriority = uxPriority; - } - #endif - - vListInitialiseItem( &( pxTCB->xGenericListItem ) ); - vListInitialiseItem( &( pxTCB->xEventListItem ) ); - - /* Set the pxTCB as a link back from the xListItem. This is so we can get - back to the containing TCB from a generic item in a list. */ - listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB ); - - /* Event lists are always in priority order. */ - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); - listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB ); - - #if ( portCRITICAL_NESTING_IN_TCB == 1 ) - { - pxTCB->uxCriticalNesting = ( unsigned portBASE_TYPE ) 0; - } - #endif - - #if ( configUSE_APPLICATION_TASK_TAG == 1 ) - { - pxTCB->pxTaskTag = NULL; - } - #endif - - #if ( configGENERATE_RUN_TIME_STATS == 1 ) - { - pxTCB->ulRunTimeCounter = 0UL; - } - #endif - - #if ( portUSING_MPU_WRAPPERS == 1 ) - { - vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, pxTCB->pxStack, usStackDepth ); - } - #else - { - ( void ) xRegions; - ( void ) usStackDepth; - } - #endif -} -/*-----------------------------------------------------------*/ - -#if ( portUSING_MPU_WRAPPERS == 1 ) - - void vTaskAllocateMPURegions( xTaskHandle xTaskToModify, const xMemoryRegion * const xRegions ) - { - tskTCB *pxTCB; - - if( xTaskToModify == pxCurrentTCB ) - { - xTaskToModify = NULL; - } - - /* If null is passed in here then we are deleting ourselves. */ - pxTCB = prvGetTCBFromHandle( xTaskToModify ); - - vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 ); - } - /*-----------------------------------------------------------*/ -#endif - -static void prvInitialiseTaskLists( void ) -{ -unsigned portBASE_TYPE uxPriority; - - for( uxPriority = 0; uxPriority < configMAX_PRIORITIES; uxPriority++ ) - { - vListInitialise( ( xList * ) &( pxReadyTasksLists[ uxPriority ] ) ); - } - - vListInitialise( ( xList * ) &xDelayedTaskList1 ); - vListInitialise( ( xList * ) &xDelayedTaskList2 ); - vListInitialise( ( xList * ) &xPendingReadyList ); - - #if ( INCLUDE_vTaskDelete == 1 ) - { - vListInitialise( ( xList * ) &xTasksWaitingTermination ); - } - #endif - - #if ( INCLUDE_vTaskSuspend == 1 ) - { - vListInitialise( ( xList * ) &xSuspendedTaskList ); - } - #endif - - /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList - using list2. */ - pxDelayedTaskList = &xDelayedTaskList1; - pxOverflowDelayedTaskList = &xDelayedTaskList2; -} -/*-----------------------------------------------------------*/ - -static void prvCheckTasksWaitingTermination( void ) -{ - #if ( INCLUDE_vTaskDelete == 1 ) - { - portBASE_TYPE xListIsEmpty; - - /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called - too often in the idle task. */ - if( uxTasksDeleted > ( unsigned portBASE_TYPE ) 0 ) - { - vTaskSuspendAll(); - xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination ); - xTaskResumeAll(); - - if( !xListIsEmpty ) - { - tskTCB *pxTCB; - - portENTER_CRITICAL(); - { - pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xTasksWaitingTermination ) ); - vListRemove( &( pxTCB->xGenericListItem ) ); - --uxCurrentNumberOfTasks; - --uxTasksDeleted; - } - portEXIT_CRITICAL(); - - prvDeleteTCB( pxTCB ); - } - } - } - #endif -} -/*-----------------------------------------------------------*/ - -static tskTCB *prvAllocateTCBAndStack( unsigned short usStackDepth, portSTACK_TYPE *puxStackBuffer ) -{ -tskTCB *pxNewTCB; - - /* Allocate space for the TCB. Where the memory comes from depends on - the implementation of the port malloc function. */ - pxNewTCB = ( tskTCB * ) pvPortMalloc( sizeof( tskTCB ) ); - - if( pxNewTCB != NULL ) - { - /* Allocate space for the stack used by the task being created. - The base of the stack memory stored in the TCB so the task can - be deleted later if required. */ - pxNewTCB->pxStack = ( portSTACK_TYPE * ) pvPortMallocAligned( ( ( ( size_t )usStackDepth ) * sizeof( portSTACK_TYPE ) ), puxStackBuffer ); - - if( pxNewTCB->pxStack == NULL ) - { - /* Could not allocate the stack. Delete the allocated TCB. */ - vPortFree( pxNewTCB ); - pxNewTCB = NULL; - } - else - { - /* Just to help debugging. */ - memset( pxNewTCB->pxStack, tskSTACK_FILL_BYTE, usStackDepth * sizeof( portSTACK_TYPE ) ); - } - } - - return pxNewTCB; -} -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - static void prvListTaskWithinSingleList( const signed char *pcWriteBuffer, xList *pxList, signed char cStatus ) - { - volatile tskTCB *pxNextTCB, *pxFirstTCB; - unsigned short usStackRemaining; - - /* Write the details of all the TCB's in pxList into the buffer. */ - listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); - do - { - listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); - usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned char * ) pxNextTCB->pxStack ); - sprintf( pcStatusString, ( char * ) "%s\t\t%c\t%u\t%u\t%u\r\n", pxNextTCB->pcTaskName, cStatus, ( unsigned int ) pxNextTCB->uxPriority, usStackRemaining, ( unsigned int ) pxNextTCB->uxTCBNumber ); - strcat( ( char * ) pcWriteBuffer, ( char * ) pcStatusString ); - - } while( pxNextTCB != pxFirstTCB ); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( configGENERATE_RUN_TIME_STATS == 1 ) - - static void prvGenerateRunTimeStatsForTasksInList( const signed char *pcWriteBuffer, xList *pxList, unsigned long ulTotalRunTime ) - { - volatile tskTCB *pxNextTCB, *pxFirstTCB; - unsigned long ulStatsAsPercentage; - - /* Write the run time stats of all the TCB's in pxList into the buffer. */ - listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); - do - { - /* Get next TCB in from the list. */ - listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); - - /* Divide by zero check. */ - if( ulTotalRunTime > 0UL ) - { - /* Has the task run at all? */ - if( pxNextTCB->ulRunTimeCounter == 0 ) - { - /* The task has used no CPU time at all. */ - sprintf( pcStatsString, ( char * ) "%s\t\t0\t\t0%%\r\n", pxNextTCB->pcTaskName ); - } - else - { - /* What percentage of the total run time as the task used? - This will always be rounded down to the nearest integer. */ - ulStatsAsPercentage = ( 100UL * pxNextTCB->ulRunTimeCounter ) / ulTotalRunTime; - - if( ulStatsAsPercentage > 0UL ) - { - sprintf( pcStatsString, ( char * ) "%s\t\t%u\t\t%u%%\r\n", pxNextTCB->pcTaskName, ( unsigned int ) pxNextTCB->ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); - } - else - { - /* If the percentage is zero here then the task has - consumed less than 1% of the total run time. */ - sprintf( pcStatsString, ( char * ) "%s\t\t%u\t\t<1%%\r\n", pxNextTCB->pcTaskName, ( unsigned int ) pxNextTCB->ulRunTimeCounter ); - } - } - - strcat( ( char * ) pcWriteBuffer, ( char * ) pcStatsString ); - } - - } while( pxNextTCB != pxFirstTCB ); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) - - static unsigned short usTaskCheckFreeStackSpace( const unsigned char * pucStackByte ) - { - register unsigned short usCount = 0; - - while( *pucStackByte == tskSTACK_FILL_BYTE ) - { - pucStackByte -= portSTACK_GROWTH; - usCount++; - } - - usCount /= sizeof( portSTACK_TYPE ); - - return usCount; - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) - - unsigned portBASE_TYPE uxTaskGetStackHighWaterMark( xTaskHandle xTask ) - { - tskTCB *pxTCB; - unsigned char *pcEndOfStack; - unsigned portBASE_TYPE uxReturn; - - pxTCB = prvGetTCBFromHandle( xTask ); - - #if portSTACK_GROWTH < 0 - { - pcEndOfStack = ( unsigned char * ) pxTCB->pxStack; - } - #else - { - pcEndOfStack = ( unsigned char * ) pxTCB->pxEndOfStack; - } - #endif - - uxReturn = ( unsigned portBASE_TYPE ) usTaskCheckFreeStackSpace( pcEndOfStack ); - - return uxReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) - - static void prvDeleteTCB( tskTCB *pxTCB ) - { - /* Free up the memory allocated by the scheduler for the task. It is up to - the task to free any memory allocated at the application level. */ - vPortFreeAligned( pxTCB->pxStack ); - vPortFree( pxTCB ); - } - -#endif - - -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) - - xTaskHandle xTaskGetCurrentTaskHandle( void ) - { - xTaskHandle xReturn; - - /* A critical section is not required as this is not called from - an interrupt and the current TCB will always be the same for any - individual execution thread. */ - xReturn = pxCurrentTCB; - - return xReturn; - } - -#endif - -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_xTaskGetSchedulerState == 1 ) - - portBASE_TYPE xTaskGetSchedulerState( void ) - { - portBASE_TYPE xReturn; - - if( xSchedulerRunning == pdFALSE ) - { - xReturn = taskSCHEDULER_NOT_STARTED; - } - else - { - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - xReturn = taskSCHEDULER_RUNNING; - } - else - { - xReturn = taskSCHEDULER_SUSPENDED; - } - } - - return xReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_MUTEXES == 1 ) - - void vTaskPriorityInherit( xTaskHandle * const pxMutexHolder ) - { - tskTCB * const pxTCB = ( tskTCB * ) pxMutexHolder; - - if( pxTCB->uxPriority < pxCurrentTCB->uxPriority ) - { - /* Adjust the mutex holder state to account for its new priority. */ - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) pxCurrentTCB->uxPriority ); - - /* If the task being modified is in the ready state it will need to - be moved in to a new list. */ - if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ) ) - { - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Inherit the priority before being moved into the new list. */ - pxTCB->uxPriority = pxCurrentTCB->uxPriority; - prvAddTaskToReadyQueue( pxTCB ); - } - else - { - /* Just inherit the priority. */ - pxTCB->uxPriority = pxCurrentTCB->uxPriority; - } - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_MUTEXES == 1 ) - - void vTaskPriorityDisinherit( xTaskHandle * const pxMutexHolder ) - { - tskTCB * const pxTCB = ( tskTCB * ) pxMutexHolder; - - if( pxMutexHolder != NULL ) - { - if( pxTCB->uxPriority != pxTCB->uxBasePriority ) - { - /* We must be the running task to be able to give the mutex back. - Remove ourselves from the ready list we currently appear in. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Disinherit the priority before adding ourselves into the new - ready list. */ - pxTCB->uxPriority = pxTCB->uxBasePriority; - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) pxTCB->uxPriority ); - prvAddTaskToReadyQueue( pxTCB ); - } - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( portCRITICAL_NESTING_IN_TCB == 1 ) - - void vTaskEnterCritical( void ) - { - portDISABLE_INTERRUPTS(); - - if( xSchedulerRunning != pdFALSE ) - { - pxCurrentTCB->uxCriticalNesting++; - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( portCRITICAL_NESTING_IN_TCB == 1 ) - -void vTaskExitCritical( void ) -{ - if( xSchedulerRunning != pdFALSE ) - { - if( pxCurrentTCB->uxCriticalNesting > 0 ) - { - pxCurrentTCB->uxCriticalNesting--; - - if( pxCurrentTCB->uxCriticalNesting == 0 ) - { - portENABLE_INTERRUPTS(); - } - } - } -} - -#endif -/*-----------------------------------------------------------*/ - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/cmsis/core_cm3.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/cmsis/core_cm3.c deleted file mode 100644 index b3a9a886d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/cmsis/core_cm3.c +++ /dev/null @@ -1,804 +0,0 @@ -/****************************************************************************** - * @file: core_cm3.c - * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version: V1.10 - * @date: 24. Feb. 2009 - *---------------------------------------------------------------------------- - * - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-Mx - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - - -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for armcc */ - #define __INLINE __inline /*!< inline keyword for armcc */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for iarcc */ - #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */ - #define __nop __no_operation /*!< no operation intrinsic in iarcc */ - -#elif defined ( __GNUC__ ) - #define __ASM asm /*!< asm keyword for gcc */ - #define __INLINE inline /*!< inline keyword for gcc */ -#endif - - - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param int16_t value to reverse - * @return int32_t reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * @param none - * @return none - * - * Removes the exclusive lock which is created by ldrex. - */ -__ASM void __CLREX(void) -{ - clrex -} - -/** - * @brief Return the Base Priority value - * - * @param none - * @return uint32_t BasePriority - * - * Return the content of the base priority register - */ -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} - -/** - * @brief Set the Base Priority value - * - * @param uint32_t BasePriority - * @return none - * - * Set the base priority register - */ -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} - -/** - * @brief Return the Priority Mask value - * - * @param none - * @return uint32_t PriMask - * - * Return the state of the priority mask bit from the priority mask - * register - */ -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} - -/** - * @brief Set the Priority Mask value - * - * @param uint32_t PriMask - * @return none - * - * Set the priority mask bit in the priority mask register - */ -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} - -/** - * @brief Return the Fault Mask value - * - * @param none - * @return uint32_t FaultMask - * - * Return the content of the fault mask register - */ -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} - -/** - * @brief Set the Fault Mask value - * - * @param uint32_t faultMask value - * @return none - * - * Set the fault mask register - */ -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} - -/** - * @brief Return the Control Register value - * - * @param none - * @return uint32_t Control value - * - * Return the content of the control register - */ -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} - -/** - * @brief Set the Control Register value - * - * @param uint32_t Control value - * @return none - * - * Set the control register - */ -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} - -#endif /* __ARMCC_VERSION */ - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -#pragma diag_suppress=Pe940 - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse bit order of value - * - * @param uint32_t value to reverse - * @return uint32_t reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive - * - * @param uint8_t* address - * @return uint8_t value of (*address) - * - * Exclusive LDR command - */ -uint8_t __LDREXB(uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive - * - * @param uint16_t* address - * @return uint16_t value of (*address) - * - * Exclusive LDR command - */ -uint16_t __LDREXH(uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive - * - * @param uint32_t* address - * @return uint32_t value of (*address) - * - * Exclusive LDR command - */ -uint32_t __LDREXW(uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive - * - * @param uint8_t *address - * @param uint8_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive - * - * @param uint16_t *address - * @param uint16_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive - * - * @param uint32_t *address - * @param uint32_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); - __ASM("bx lr"); -} - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) ); -} - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) ); -} - -/** - * @brief Return the Base Priority value - * - * @param none - * @return uint32_t BasePriority - * - * Return the content of the base priority register - */ -uint32_t __get_BASEPRI(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Base Priority value - * - * @param uint32_t BasePriority - * @return none - * - * Set the base priority register - */ -void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - -/** - * @brief Return the Priority Mask value - * - * @param none - * @return uint32_t PriMask - * - * Return the state of the priority mask bit from the priority mask - * register - */ -uint32_t __get_PRIMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Priority Mask value - * - * @param uint32_t PriMask - * @return none - * - * Set the priority mask bit in the priority mask register - */ -void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - -/** - * @brief Return the Fault Mask value - * - * @param none - * @return uint32_t FaultMask - * - * Return the content of the fault mask register - */ -uint32_t __get_FAULTMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Fault Mask value - * - * @param uint32_t faultMask value - * @return none - * - * Set the fault mask register - */ -void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -/** - * @brief Reverse byte order in integer value - * - * @param uint32_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in integer value - */ -uint32_t __REV(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param int32_t value to reverse - * @return int32_t reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -int32_t __REVSH(int16_t value) -{ - uint32_t result=0; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse bit order of value - * - * @param uint32_t value to reverse - * @return uint32_t reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief LDR Exclusive - * - * @param uint8_t* address - * @return uint8_t value of (*address) - * - * Exclusive LDR command - */ -uint8_t __LDREXB(uint8_t *addr) -{ - uint8_t result=0; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive - * - * @param uint16_t* address - * @return uint16_t value of (*address) - * - * Exclusive LDR command - */ -uint16_t __LDREXH(uint16_t *addr) -{ - uint16_t result=0; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive - * - * @param uint32_t* address - * @return uint32_t value of (*address) - * - * Exclusive LDR command - */ -uint32_t __LDREXW(uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief STR Exclusive - * - * @param uint8_t *address - * @param uint8_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive - * - * @param uint16_t *address - * @param uint16_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive - * - * @param uint32_t *address - * @param uint32_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief Return the Control Register value - * - * @param none - * @return uint32_t Control value - * - * Return the content of the control register - */ -uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param uint32_t Control value - * @return none - * - * Set the control register - */ -void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - -#endif - - - - - - - - - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/cmsis/core_cm3.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/cmsis/core_cm3.h deleted file mode 100644 index 59b054ded..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/cmsis/core_cm3.h +++ /dev/null @@ -1,1265 +0,0 @@ -/****************************************************************************** - * @file: core_cm3.h - * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version: V1.10 - * @date: 24. Feb. 2009 - *---------------------------------------------------------------------------- - * - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-Mx - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - - - -#ifndef __CM3_CORE_H__ -#define __CM3_CORE_H__ - - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -/** - * Lint configuration \n - * ----------------------- \n - * - * The following Lint messages will be suppressed and not shown: \n - * \n - * --- Error 10: --- \n - * register uint32_t __regBasePri __asm("basepri"); \n - * Error 10: Expecting ';' \n - * \n - * --- Error 530: --- \n - * return(__regBasePri); \n - * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n - * \n - * --- Error 550: --- \n - * __regBasePri = (basePri & 0x1ff); \n - * } \n - * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n - * \n - * --- Error 754: --- \n - * uint32_t RESERVED0[24]; \n - * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced \n - * \n - * --- Error 750: --- \n - * #define __CM3_CORE_H__ \n - * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n - * \n - * --- Error 528: --- \n - * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n - * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n - * \n - * --- Error 751: --- \n - * } InterruptType_Type; \n - * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n - * \n - * \n - * Note: To re-enable a Message, insert a space before 'lint' * \n - * - */ - -/*lint -save */ -/*lint -e10 */ -/*lint -e530 */ -/*lint -e550 */ -/*lint -e754 */ -/*lint -e750 */ -/*lint -e528 */ -/*lint -e751 */ - - -#include /* Include standard types */ - -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ -#endif - - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#define __I volatile const /*!< defines 'read only' permissions */ -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ - - -/* System Reset */ -#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */ -#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */ -#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */ -#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */ - -/* Core Debug */ -#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */ -#define ITM_TCR_ITMENA 1 /*!< ITM enable */ - - - - -/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Software Trigger Interrupt Register */ -} NVIC_Type; - - -/* memory mapping struct for System Control Block */ -typedef struct -{ - __I uint32_t CPUID; /*!< CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< System Control Register */ - __IO uint32_t CCR; /*!< Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Processor Feature Register */ - __I uint32_t DFR; /*!< Debug Feature Register */ - __I uint32_t ADR; /*!< Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< ISA Feature Register */ -} SCB_Type; - - -/* memory mapping struct for SysTick */ -typedef struct -{ - __IO uint32_t CTRL; /*!< SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< SysTick Current Value Register */ - __I uint32_t CALIB; /*!< SysTick Calibration Register */ -} SysTick_Type; - - -/* memory mapping structur for ITM */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< ITM Integration Write Register */ - __IO uint32_t IRR; /*!< ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< ITM Lock Access Register */ - __IO uint32_t LSR; /*!< ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< ITM Product ID Registers */ - __I uint32_t PID5; - __I uint32_t PID6; - __I uint32_t PID7; - __I uint32_t PID0; - __I uint32_t PID1; - __I uint32_t PID2; - __I uint32_t PID3; - __I uint32_t CID0; - __I uint32_t CID1; - __I uint32_t CID2; - __I uint32_t CID3; -} ITM_Type; - - -/* memory mapped struct for Interrupt Type */ -typedef struct -{ - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Interrupt Control Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Auxiliary Control Register */ -#else - uint32_t RESERVED1; -#endif -} InterruptType_Type; - - -/* Memory Protection Unit */ -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) -typedef struct -{ - __I uint32_t TYPE; /*!< MPU Type Register */ - __IO uint32_t CTRL; /*!< MPU Control Register */ - __IO uint32_t RNR; /*!< MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; -#endif - - -/* Core Debug Register */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ -#endif - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - #define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ - -#elif defined ( __GNUC__ ) - #define __ASM asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#define __enable_fault_irq __enable_fiq -#define __disable_fault_irq __disable_fiq - -#define __NOP __nop -#define __WFI __wfi -#define __WFE __wfe -#define __SEV __sev -#define __ISB() __isb(0) -#define __DSB() __dsb(0) -#define __DMB() __dmb(0) -#define __REV __rev -#define __RBIT __rbit -#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) -#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) -#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) -#define __STREXB(value, ptr) __strex(value, ptr) -#define __STREXH(value, ptr) __strex(value, ptr) -#define __STREXW(value, ptr) __strex(value, ptr) - - - /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ - /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ - /* intrinsic void __enable_irq(); */ - /* intrinsic void __disable_irq(); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/* - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param int16_t value to reverse - * @return int32_t reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * @param none - * @return none - * - * Removes the exclusive lock which is created by ldrex. - */ -extern void __CLREX(void); - -/** - * @brief Return the Base Priority value - * - * @param none - * @return uint32_t BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param uint32_t BasePriority - * @return none - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @param none - * @return uint32_t PriMask - * - * Return the state of the priority mask bit from the priority mask - * register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param uint32_t PriMask - * @return none - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @param none - * @return uint32_t FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param uint32_t faultMask value - * @return none - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value - * - * @param none - * @return uint32_t Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param uint32_t Control value - * @return none - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -#else /* (__ARMCC_VERSION >= 400000) */ - - -/** - * @brief Remove the exclusive lock created by ldrex - * - * @param none - * @return none - * - * Removes the exclusive lock which is created by ldrex. - */ -#define __CLREX __clrex - -/** - * @brief Return the Base Priority value - * - * @param none - * @return uint32_t BasePriority - * - * Return the content of the base priority register - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - -/** - * @brief Set the Base Priority value - * - * @param uint32_t BasePriority - * @return none - * - * Set the base priority register - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0x1ff); -} - -/** - * @brief Return the Priority Mask value - * - * @param none - * @return uint32_t PriMask - * - * Return the state of the priority mask bit from the priority mask - * register - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - -/** - * @brief Set the Priority Mask value - * - * @param uint32_t PriMask - * @return none - * - * Set the priority mask bit in the priority mask register - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - -/** - * @brief Return the Fault Mask value - * - * @param none - * @return uint32_t FaultMask - * - * Return the content of the fault mask register - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - -/** - * @brief Set the Fault Mask value - * - * @param uint32_t faultMask value - * @return none - * - * Set the fault mask register - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); -} - -/** - * @brief Return the Control Register value - * - * @param none - * @return uint32_t Control value - * - * Return the content of the control register - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - -/** - * @brief Set the Control Register value - * - * @param uint32_t Control value - * @return none - * - * Set the control register - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ -#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ - -static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } - -static __INLINE void __WFI() { __ASM ("wfi"); } -static __INLINE void __WFE() { __ASM ("wfe"); } -static __INLINE void __SEV() { __ASM ("sev"); } -static __INLINE void __CLREX() { __ASM ("clrex"); } - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse bit order of value - * - * @param uint32_t value to reverse - * @return uint32_t reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive - * - * @param uint8_t* address - * @return uint8_t value of (*address) - * - * Exclusive LDR command - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive - * - * @param uint16_t* address - * @return uint16_t value of (*address) - * - * Exclusive LDR command - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive - * - * @param uint32_t* address - * @return uint32_t value of (*address) - * - * Exclusive LDR command - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint8_t *address - * @param uint8_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint16_t *address - * @param uint16_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint32_t *address - * @param uint32_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - -/* intrinsic void __set_PRIMASK(); */ -/* intrinsic void __get_PRIMASK(); */ -/* intrinsic void __set_FAULTMASK(); */ -/* intrinsic void __get_FAULTMASK(); */ -/* intrinsic uint32_t __REV(uint32_t value); */ -/* intrinsic uint32_t __REVSH(uint32_t value); */ -/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ -/* intrinsic unsigned long __LDREX(unsigned long *); */ - - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -static __INLINE void __NOP() { __ASM volatile ("nop"); } -static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } -static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } - -static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } - -static __INLINE void __WFI() { __ASM volatile ("wfi"); } -static __INLINE void __WFE() { __ASM volatile ("wfe"); } -static __INLINE void __SEV() { __ASM volatile ("sev"); } -static __INLINE void __ISB(arg) { __ASM volatile ("isb"); } -static __INLINE void __DSB(arg) { __ASM volatile ("dsb"); } -static __INLINE void __DMB(arg) { __ASM volatile ("dmb"); } -static __INLINE void __CLREX() { __ASM volatile ("clrex"); } - - -/** - * @brief Return the Process Stack Pointer - * - * @param none - * @return uint32_t ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param uint32_t Process Stack Pointer - * @return none - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @param none - * @return uint32_t Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param uint32_t Main Stack Pointer - * @return none - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Return the Base Priority value - * - * @param none - * @return uint32_t BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param uint32_t BasePriority - * @return none - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @param none - * @return uint32_t PriMask - * - * Return the state of the priority mask bit from the priority mask - * register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param uint32_t PriMask - * @return none - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @param none - * @return uint32_t FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param uint32_t faultMask value - * @return none - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value -* -* @param none -* @return uint32_t Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param uint32_t Control value - * @return none - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -/** - * @brief Reverse byte order in integer value - * - * @param uint32_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in integer value - */ -extern uint32_t __REV(uint32_t value); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param uint16_t value to reverse - * @return uint32_t reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/* - * Reverse byte order in signed short value with sign extension to integer - * - * @param int16_t value to reverse - * @return int32_t reversed value - * - * @brief Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - -/** - * @brief Reverse bit order of value - * - * @param uint32_t value to reverse - * @return uint32_t reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive - * - * @param uint8_t* address - * @return uint8_t value of (*address) - * - * Exclusive LDR command - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive - * - * @param uint16_t* address - * @return uint16_t value of (*address) - * - * Exclusive LDR command - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive - * - * @param uint32_t* address - * @return uint32_t value of (*address) - * - * Exclusive LDR command - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint8_t *address - * @param uint8_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint16_t *address - * @param uint16_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive - * - * @param uint32_t *address - * @param uint32_t value to store - * @return uint32_t successful / failed - * - * Exclusive STR command - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - -#endif - - - -/* ########################## NVIC functions #################################### */ - -/** - * @brief Set the Priority Grouping in NVIC Interrupt Controller - * - * @param uint32_t priority_grouping is priority grouping field - * @return - * - * Set the priority grouping field using the required unlock sequence. - * The parameter priority_grouping is assigned to the field - * SCB->AIRCR [10:8] PRIGROUP field. - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t priority_grouping) -{ - uint32_t reg_value=0; - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */ - reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (priority_grouping << 8))); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn_Type IRQn specifies the interrupt number - * @return none - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn_Type IRQn is the positive number of the external interrupt - * @return none - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - -/** - * @brief Read the interrupt pending bit for a device specific interrupt source - * - * @param IRQn_Type IRQn is the number of the device specifc interrupt - * @return IRQn_Type Number of pending interrupt or zero - * - * Read the pending register in NVIC and return the number of the - * specified interrupt if its status is pending, otherwise it returns - * zero. The interrupt number cannot be a negative value. - */ -static __INLINE IRQn_Type NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((IRQn_Type) (NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))); /* Return Interrupt bit or 'zero' */ -} - -/** - * @brief Set the pending bit for an external interrupt - * - * @param IRQn_Type IRQn is the Number of the interrupt - * @return none - * - * Set the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - -/** - * @brief Clear the pending bit for an external interrupt - * - * @param IRQn_Type IRQn is the Number of the interrupt - * @return none - * - * Clear the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - -/** - * @brief Read the active bit for an external interrupt - * - * @param IRQn_Type IRQn is the Number of the interrupt - * @return IRQn_Type Number of pending interrupt or zero - * - * Read the active register in NVIC and returns the number of the - * specified interrupt if its status is active, otherwise it - * returns zero. The interrupt number cannot be a negative value. - */ -static __INLINE IRQn_Type NVIC_GetActive(IRQn_Type IRQn) -{ - return((IRQn_Type)(NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))); /* Return Interruptnumber or 'zero' */ -} - -/** - * @brief Set the priority for an interrupt - * - * @param IRQn_Type IRQn is the Number of the interrupt - * @param priority is the priority for the interrupt - * @return none - * - * Set the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. \n - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, int32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ - else { - //NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ - NVIC->IP[(uint32_t)(IRQn)] = (priority & 0xff); } /* set Priority for device specific Interrupts */ -} - -/** - * @brief Read the priority for an interrupt - * - * @param IRQn_Type IRQn is the Number of the interrupt - * @return priority is the priority for the interrupt - * - * Read the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * The returned priority value is automatically aligned to the implemented - * priority bits of the microcontroller. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - - -/* ################################## SysTick function ############################################ */ - -#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) - -/* SysTick constants */ -#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */ -#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */ -#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */ -#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */ - -/** - * @brief Initialize and start the SysTick counter and its interrupt. - * - * @param uint32_t ticks is the number of ticks between two interrupts - * @return none - * - * Initialise the system tick timer and its interrupt and start the - * system tick timer / counter in free running mode to generate - * periodical interrupts. - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = (0x00); /* Load the SysTick Counter Value */ - SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<DEMCR & CoreDebug_DEMCR_TRCENA) && - (ITM->TCR & ITM_TCR_ITMENA) && - (ITM->TER & (1UL << 0)) ) - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - -#endif - -/*lint -restore */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/acc/acc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/acc/acc.c deleted file mode 100644 index 2c3e00809..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/acc/acc.c +++ /dev/null @@ -1,164 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup adc_module Working with ACC - * The ACC driver provides the interface to configure and use the ACC peripheral.\n - * - * It converts the analog input to digital format. The converted result could be 12bit - * or 10bit. The ACC supports up to 16 analog lines. - * - * To Enable a ACC conversion,the user has to follow these few steps: - *
    - *
  • Select an appropriate reference voltage on ADVREF
  • - *
  • Configure the ACC according to its requirements and special needs,which could be - broken down into several parts: - * -# Select the resolution by setting or clearing ACC_MR_LOWRES bit in ACC_MR (Mode Register) - * -# Set ACC clock by setting ACC_MR_PRESCAL bits in ACC_MR, the clock is caculated with - ACCClock = MCK / ( (PRESCAL+1) * 2 ) - * -# Set Startup Time,Tracking Clock cycles and Transfer Clock respeticively in ACC_MR. -
  • - *
  • Start conversion by setting ACC_CR_START in ACC_CR.
  • - *
- * - * For more accurate information, please look at the ACC section of the - * Datasheet. - * - * Related files :\n - * \ref adc.c\n - * \ref adc.h\n -*/ -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include -#include - - - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Initialize the ACC controller - * \param pAcc Pointer to an Acc instance. - * \param idAcc ACC identifier - * \param selplus input connected to inp, 0~7 - * \param selminus input connected to inm,0~7 - * \param ac_en Analog comprator enabled/disabled,use pattern - * \param edge CF flag triggering mode,use pattern - * \param invert INVert comparator output,use pattern defined in the device header - file -*/ -void ACC_Configure(Acc *pAcc, - uint8_t idAcc, - uint8_t selplus, - uint8_t selminus, - uint16_t ac_en, - uint16_t edge, - uint16_t invert) -{ - - /* Enable peripheral clock*/ - PMC->PMC_PCER1 = 1 << (idAcc-32); - - /* Reset the controller */ - pAcc->ACC_CR |= ACC_CR_SWRST; - - /* Write to the MR register */ - ACC_CfgModeReg( pAcc, - ( selplus & ACC_MR_SELPLUS) - | (( selminus<<4) & ACC_MR_SELMINUS) - | ( ac_en & ACC_MR_ACEN) - | ( edge & ACC_MR_EDGETYP) - | ( invert & ACC_MR_INV) ); - //pAcc->ACC_MR |= (ACC_MR_SELFS_OUTPUT|ACC_MR_FE_EN); - - pAcc->ACC_ACR = 0x7; - - while(pAcc->ACC_ISR & (uint32_t)ACC_ISR_MASK); -} - - -/** - * Return the Channel Converted Data - * \param pAdc Pointer to an Adc instance. - * \param channel channel to get converted value - * \return Channel converted data of the specified channel - */ -void ACC_SetComparisionPair(Acc *pAcc, uint8_t selplus,uint8_t selminus) -{ - - uint32_t temp; - - ASSERT(selplus < 8 && selminus < 8,"The assigned channel number is invalid!"); - - temp = pAcc->ACC_MR; - - pAcc->ACC_MR = temp & (~ACC_MR_SELMINUS)&(~ACC_MR_SELPLUS); - - pAcc->ACC_MR |= ((selplus & ACC_MR_SELPLUS)|((selminus<<4) & ACC_MR_SELMINUS)); - -} -/** - * Return Comparison Result - * \param pAcc Pointer to an Acc instance. - * \param status value of ACC_ISR - */ -uint8_t ACC_GetComparisionResult(Acc *pAcc,uint32_t status) -{ - uint32_t temp = pAcc->ACC_MR; - if( (temp & ACC_MR_INV)== ACC_MR_INV) - { - - if( status & ACC_ISR_SCO) - { - return 0; /* inn>inp*/ - } - else return 1;/* inp>inn*/ - - } - else - { - - if( status & ACC_ISR_SCO) - { - return 1; /* inp>inn*/ - } - else return 0;/* inn>inp*/ - } - -} - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/acc/acc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/acc/acc.h deleted file mode 100644 index 284d8d44a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/acc/acc.h +++ /dev/null @@ -1,144 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \unit - * - * !Purpose - * - * Interface for configuration the Analog-to-Digital Converter (ACC) peripheral. - * - * !Usage - * - * -# Configurate the pins for ACC - * -# Initialize the ACC with ACC_Initialize(). - * -# Select the active channel using ACC_EnableChannel() - * -# Start the conversion with ACC_StartConversion() - * -# Wait the end of the conversion by polling status with ACC_GetStatus() - * -# Finally, get the converted data using ACC_GetConvertedData() - * -*/ -#ifndef ACC_H -#define ACC_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include - -/*------------------------------------------------------------------------------ - * Definitions - *------------------------------------------------------------------------------*/ -#define ACC_SELPLUS_AD12B0 0 -#define ACC_SELPLUS_AD12B1 1 -#define ACC_SELPLUS_AD12B2 2 -#define ACC_SELPLUS_AD12B3 3 -#define ACC_SELPLUS_AD12B4 4 -#define ACC_SELPLUS_AD12B5 5 -#define ACC_SELPLUS_AD12B6 6 -#define ACC_SELPLUS_AD12B7 7 -#define ACC_SELMINUS_TS 0 -#define ACC_SELMINUS_ADVREF 1 -#define ACC_SELMINUS_DAC0 2 -#define ACC_SELMINUS_DAC1 3 -#define ACC_SELMINUS_AD12B0 4 -#define ACC_SELMINUS_AD12B1 5 -#define ACC_SELMINUS_AD12B2 6 -#define ACC_SELMINUS_AD12B3 7 - - -/*------------------------------------------------------------------------------ - * Macros function of register access - *------------------------------------------------------------------------------*/ -#define ACC_CfgModeReg(pAcc, mode) { \ - (pAcc)->ACC_MR = (mode);\ - } - -#define ACC_GetModeReg(pAcc) ((pAcc)->ACC_MR) - -#define ACC_StartConversion(pAcc) ((pAcc)->ACC_CR = ACC_CR_START) - -#define ACC_SoftReset(pAcc) ((pAcc)->ACC_CR = ACC_CR_SWRST) - -#define ACC_EnableChannel(pAcc, channel) {\ - ASSERT(channel < 16, "ACC Channel not exist");\ - (pAcc)->ACC_CHER = (1 << (channel));\ - } - -#define ACC_DisableChannel (pAcc, channel) {\ - ASSERT((channel) < 16, "ACC Channel not exist");\ - (pAcc)->ACC_CHDR = (1 << (channel));\ - } - -#define ACC_EnableIt(pAcc, mode) {\ - ASSERT(((mode)&0xFFF00000)== 0, "ACC bad interrupt IER");\ - (pAcc)->ACC_IER = (mode);\ - } - -#define ACC_DisableIt(pAcc, mode) {\ - ASSERT(((mode)&0xFFF00000)== 0, "ACC bad interrupt IDR");\ - (pAcc)->ACC_IDR = (mode);\ - } - -#define ACC_EnableDataReadyIt(pAcc) ((pAcc)->ACC_IER = AT91C_ACC_DRDY) - -#define ACC_GetStatus(pAcc) ((pAcc)->ACC_ISR) - -#define ACC_GetChannelStatus(pAcc) ((pAcc)->ACC_CHSR) - -#define ACC_GetInterruptMaskStatus(pAcc) ((pAcc)->ACC_IMR) - -#define ACC_GetLastConvertedData(pAcc) ((pAcc)->ACC_LCDR) - -#define ACC_CfgAnalogCtrlReg(pAcc,mode) {\ - ASSERT(((mode) & 0xFFFCFF3C)==0, "ACC bad analog control config");\ - (pAcc)->ACC_ACR = (mode);\ - } - -#define ACC_CfgExtModeReg(pAcc, extmode) {\ - ASSERT(((extmode) & 0xFF00FFFE)==0, "ACC bad extended mode config");\ - (pAcc)->ACC_EMR = (extmode);\ - } - -#define ACC_GetAnalogCtrlReg(pAcc) ((pAcc)->ACC_ACR) - -/*------------------------------------------------------------------------------ - * Exported functions - *------------------------------------------------------------------------------*/ -void ACC_Configure(Acc *pAcc, - uint8_t idAcc, - uint8_t selplus, - uint8_t selminus, - uint16_t ac_en, - uint16_t edge, - uint16_t invert); - -extern uint8_t ACC_GetComparisionResult(Acc *pAcc,uint32_t status); - -#endif //#ifndef ACC_H diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/adc/adc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/adc/adc.c deleted file mode 100644 index 241a8d935..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/adc/adc.c +++ /dev/null @@ -1,231 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup adc_module Working with ADC - * The ADC driver provides the interface to configure and use the ADC peripheral. - * \n - * - * It converts the analog input to digital format. The converted result could be - * 12bit or 10bit. The ADC supports up to 16 analog lines. - * - * To Enable a ADC conversion,the user has to follow these few steps: - *
    - *
  • Select an appropriate reference voltage on ADVREF
  • - *
  • Configure the ADC according to its requirements and special needs,which - * could be broken down into several parts: - * -# Select the resolution by setting or clearing ADC_MR_LOWRES bit in - * ADC_MR (Mode Register) - * -# Set ADC clock by setting ADC_MR_PRESCAL bits in ADC_MR, the clock is - * calculated with ADCClock = MCK / ( (PRESCAL+1) * 2 ) - * -# Set Startup Time,Tracking Clock cycles and Transfer Clock respectively - * in ADC_MR. -
  • - *
  • Start conversion by setting ADC_CR_START in ADC_CR.
  • - *
- * - * For more accurate information, please look at the ADC section of the - * Datasheet. - * - * Related files :\n - * \ref adc.c\n - * \ref adc.h\n -*/ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include -#include - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Initialize the ADC controller - * \param pAdc Pointer to an Adc instance. - * \param trgEn trigger mode, software or Hardware - * \param trgSel hardware trigger selection - * \param sleepMode sleep mode selection - * \param resolution resolution selection 10 bits or 12 bits - * \param mckClock value of MCK in Hz - * \param adcClock value of the ADC clock in Hz - * \param startupTime value of the start up time (in ADCClock) (see datasheet) - * \param trackingt Tracking Time (in ADCClock cycle) -*/ -void ADC_Initialize(Adc *pAdc, uint8_t idAdc, uint8_t trgEn, uint8_t trgSel, - uint8_t sleepMode, uint8_t resolution, uint32_t mckClock, - uint32_t adcClock, uint32_t startup, uint32_t tracking) { - uint32_t prescal; - prescal = (mckClock / (2*adcClock)) - 1; - - ASSERT( (prescal<0x3F), "ADC Bad PRESCAL\n\r"); - - TRACE_DEBUG("adcClock:%lu MasterClock:%lu\n\r", (mckClock/((prescal+1)*2)), - mckClock); - - if( adcClock != (mckClock/((prescal+1)*2)) ) { - TRACE_WARNING("User and calculated adcClocks are different : " - "user=%lu calc=%lu\n\r", - adcClock, (mckClock/((prescal+1)*2))); - } - - /* Enable peripheral clock*/ - PMC->PMC_PCER0 = 1 << idAdc; - - /* Reset the controller */ - ADC_SoftReset(pAdc); - - /* Write to the MR register */ - ADC_CfgModeReg( pAdc, - ( trgEn & ADC_MR_TRGEN) - | ( trgSel & ADC_MR_TRGSEL) - | ( resolution & ADC_MR_LOWRES) - | ( sleepMode & ADC_MR_SLEEP) - | ( (prescal<<8) & ADC_MR_PRESCAL) - | ( (startup<<16) & ADC_MR_STARTUP) - | ( (tracking<<24) & ADC_MR_TRACKTIM) ); -} - -/** - * Return the Channel Converted Data - * \param pAdc Pointer to an Adc instance. - * \param channel channel to get converted value - */ -uint32_t ADC_GetConvertedData(Adc *pAdc, uint32_t channel) { - uint32_t data=0; - - if (15 >= channel) { - data = *((RoReg *)((uint32_t)&(pAdc->ADC_CDR0)+ channel*4)); - } - return data; -} -/** - * Set compare channel - * \param pAdc Pointer to an Adc instance. - * \param channel channel number to be set,16 for all channels - */ -void ADC_SetCompareChannel(Adc *pAdc, uint8_t channel) { - ASSERT(channel<=16, "Invalid channel number"); - if (channel < 16) { - pAdc->ADC_EMR &= ~(ADC_EMR_CMPALL); - pAdc->ADC_EMR &= ~(ADC_EMR_CMPSEL); - pAdc->ADC_EMR |= (channel << 4); - } else { - pAdc->ADC_EMR |= ADC_EMR_CMPALL; - } -} -/** - * Set compare mode - * \param pAdc Pointer to an Adc instance. - * \param mode compare mode - */ -void ADC_SetCompareMode(Adc *pAdc, uint8_t mode) { - pAdc->ADC_EMR &= ~(ADC_EMR_CMPMODE); - pAdc->ADC_EMR |= mode; -} -/** - * Set comparsion window,one thereshold each time - * \param pAdc Pointer to an Adc instance. - * \param hi_lo Comparison Window - */ -void ADC_SetComparisonWindow(Adc *pAdc, uint32_t hi_lo) { - pAdc->ADC_CWR = hi_lo; -} - -/**---------------------------------------------------------------------------- -* Test if ADC Interrupt is Masked -* \param pAdc Pointer to an Adc instance. -* \param flag flag to be tested -* \return 1 if interrupt is masked, otherwise 0 -*/ -uint32_t ADC_IsInterruptMasked(Adc *pAdc, uint32_t flag) { - return (ADC_GetInterruptMaskStatus(pAdc) & flag); -} - -/**---------------------------------------------------------------------------- -* Test if ADC Status is Set -* \param pAdc Pointer to an Adc instance. -* \param flag flag to be tested -* \return 1 if the staus is set; 0 otherwise -*/ -uint32_t ADC_IsStatusSet(Adc *pAdc, uint32_t flag) { - return (ADC_GetStatus(pAdc) & flag); -} - -/**---------------------------------------------------------------------------- -* Test if ADC channel interrupt Status is Set -* \param adc_sr Value of SR register -* \param channel Channel to be tested -* \return 1 if interrupt status is set, otherwise 0 -*/ -uint8_t ADC_IsChannelInterruptStatusSet(uint32_t adc_sr, uint32_t channel) { - uint8_t status; - - if((adc_sr & (1<ADC_RCR == 0) && (pADC->ADC_RNCR == 0)) { - - pADC->ADC_RPR = (uint32_t) pBuffer; - pADC->ADC_RCR = size; - pADC->ADC_PTCR = ADC_PTCR_RXTEN; - - return 1; - } - /* Check if the second PDC bank is free*/ - else if (pADC->ADC_RNCR == 0) { - - pADC->ADC_RNPR = (uint32_t) pBuffer; - pADC->ADC_RNCR = size; - - return 1; - } else { - - return 0; - } - -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/adc/adc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/adc/adc.h deleted file mode 100644 index 702143f0e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/adc/adc.h +++ /dev/null @@ -1,158 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \unit - * - * !Purpose - * - * Interface for configuration the Analog-to-Digital Converter (ADC) peripheral. - * - * !Usage - * - * -# Configurate the pins for ADC - * -# Initialize the ADC with ADC_Initialize(). - * -# Select the active channel using ADC_EnableChannel() - * -# Start the conversion with ADC_StartConversion() - * -# Wait the end of the conversion by polling status with ADC_GetStatus() - * -# Finally, get the converted data using ADC_GetConvertedData() - * -*/ -#ifndef ADC_H -#define ADC_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include - -/*------------------------------------------------------------------------------ - * Definitions - *------------------------------------------------------------------------------*/ -#define ADC_CHANNEL_0 0 -#define ADC_CHANNEL_1 1 -#define ADC_CHANNEL_2 2 -#define ADC_CHANNEL_3 3 -#define ADC_CHANNEL_4 4 -#define ADC_CHANNEL_5 5 -#define ADC_CHANNEL_6 6 -#define ADC_CHANNEL_7 7 -#define ADC_CHANNEL_8 8 -#define ADC_CHANNEL_9 9 -#define ADC_CHANNEL_10 10 -#define ADC_CHANNEL_11 11 -#define ADC_CHANNEL_12 12 -#define ADC_CHANNEL_13 13 -#define ADC_CHANNEL_14 14 -#define ADC_CHANNEL_15 15 - -/*------------------------------------------------------------------------------ - * Macros function of register access - *------------------------------------------------------------------------------*/ -#define ADC_CfgModeReg(pAdc, mode) { \ - ASSERT(((mode)&0xF00000C0)== 0, "ADC Bad configuration ADC MR");\ - (pAdc)->ADC_MR = (mode);\ - } - -#define ADC_GetModeReg(pAdc) ((pAdc)->ADC_MR) - -#define ADC_StartConversion(pAdc) ((pAdc)->ADC_CR = ADC_CR_START) - -#define ADC_SoftReset(pAdc) ((pAdc)->ADC_CR = ADC_CR_SWRST) - -#define ADC_EnableChannel(pAdc, channel) {\ - ASSERT(channel < 16, "ADC Channel not exist");\ - (pAdc)->ADC_CHER = (1 << (channel));\ - } - -#define ADC_DisableChannel (pAdc, channel) {\ - ASSERT((channel) < 16, "ADC Channel not exist");\ - (pAdc)->ADC_CHDR = (1 << (channel));\ - } - -#define ADC_EnableIt(pAdc, mode) {\ - (pAdc)->ADC_IER = (mode);\ - } - -#define ADC_DisableIt(pAdc, mode) {\ - (pAdc)->ADC_IDR = (mode);\ - } - -#define ADC_EnbaleTS(pAdc,mode) {\ - (pAdc)->ADC_ACR |= mode;\ - } - -#define ADC_EnableDataReadyIt(pAdc) ((pAdc)->ADC_IER = AT91C_ADC_DRDY) - -#define ADC_GetStatus(pAdc) ((pAdc)->ADC_ISR) - -#define ADC_GetCompareMode(pAdc) (((pAdc)->ADC_EMR)& (ADC_EMR_CMPMODE)) - -#define ADC_GetChannelStatus(pAdc) ((pAdc)->ADC_CHSR) - -#define ADC_GetInterruptMaskStatus(pAdc) ((pAdc)->ADC_IMR) - -#define ADC_GetLastConvertedData(pAdc) ((pAdc)->ADC_LCDR) - -#define ADC_CfgAnalogCtrlReg(pAdc,mode) {\ - ASSERT(((mode) & 0xFFFCFF3C)==0, "ADC bad analog control config");\ - (pAdc)->ADC_ACR = (mode);\ - } - -#define ADC_CfgExtModeReg(pAdc, extmode) {\ - ASSERT(((extmode) & 0xFF00FFFE)==0, "ADC bad extended mode config");\ - (pAdc)->ADC_EMR = (extmode);\ - } - -#define ADC_GetAnalogCtrlReg(pAdc) ((pAdc)->ADC_ACR) - -/*------------------------------------------------------------------------------ - * Exported functions - *------------------------------------------------------------------------------*/ -extern void ADC_Initialize (Adc *pAdc, - uint8_t idAdc, - uint8_t trgEn, - uint8_t trgSel, - uint8_t sleepMode, - uint8_t resolution, - uint32_t mckClock, - uint32_t adcClock, - uint32_t startupTime, - uint32_t sampleAndHoldTime); -extern uint32_t ADC_GetConvertedData(Adc *pAdc, uint32_t channel); -extern void ADC_SetCompareChannel(Adc *pAdc, uint8_t channel); -extern void ADC_SetCompareMode(Adc *pAdc, uint8_t mode); -extern void ADC_SetComparisonWindow(Adc *pAdc, uint32_t hi_lo); -extern uint32_t ADC_IsInterruptMasked(Adc *pAdc, uint32_t flag); -extern uint32_t ADC_IsStatusSet(Adc *pAdc, uint32_t flag); -extern uint8_t ADC_IsChannelInterruptStatusSet(uint32_t adc_sr, - uint32_t channel); -extern int8_t ADC_ReadBuffer(Adc *pADC,int16_t *pBuffer,int32_t size); - -#endif //#ifndef ADC_H diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/async/async.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/async/async.c deleted file mode 100644 index 65ba73a6e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/async/async.c +++ /dev/null @@ -1,54 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Provide a routine for asynchronos transfer. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include -#include "async.h" - -/*---------------------------------------------------------------------------- - * Global functions - *----------------------------------------------------------------------------*/ - /** - * \brief Returns 1 if the given transfer has ended; otherwise returns 0. - * \param pAsync Pointer to an Async instance. - */ -uint8_t ASYNC_IsFinished(Async *pAsync) -{ - return (pAsync->status != ASYNC_STATUS_PENDING); -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/async/async.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/async/async.h deleted file mode 100644 index af03d0e22..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/async/async.h +++ /dev/null @@ -1,67 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - - /** - * \file - * - * Provide a routine for asynchronos transfer. - * - */ - -#ifndef ASYNC_H -#define ASYNC_H - - -/*---------------------------------------------------------------------------- - * Definition - *----------------------------------------------------------------------------*/ -/** Transfer is still pending.*/ -#define ASYNC_STATUS_PENDING 0xFF - -/*---------------------------------------------------------------------------- - * Type - *----------------------------------------------------------------------------*/ -/** Asynchronous transfer descriptor. */ -typedef struct _Async { - - /** Asynchronous transfer status.*/ - volatile uint8_t status; - /** Callback function to invoke when transfer completes or fails.*/ - void *callback; - /** Driver storage area; do not use.*/ - uint32_t pStorage[4]; -} Async; - -/*---------------------------------------------------------------------------- - * Global functions - *----------------------------------------------------------------------------*/ -extern uint8_t ASYNC_IsFinished(Async *pAsync); - -#endif //#ifndef ASYNC_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/crccu/crccu.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/crccu/crccu.c deleted file mode 100644 index 0e4acec88..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/crccu/crccu.c +++ /dev/null @@ -1,134 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup crccu_module Working with CRCCU - * The CRCCU driver provides the interface to configure and use the CRCCU - * peripheral. - * - * It performs a CRC computation on a Memory Area. CRC computation is performed - * from the LSB to MSB bit. Three different polynomials are available: - * CCIT802.3, CASTAGNOLI and CCIT16. - * - * To computes CRC of a buffer, the user has to follow these few steps: - *
    - *
  • Reset initial CRC by setting RESET bit in CRCCU_CRC_CR,
  • - *
  • Configure CRC descriptor and working mode,
  • - *
  • Start to compute CRC by setting DMAEN in CRCCU_DMA_EN,
  • - *
  • Get CRC value in CRCCU_CRC_SR.
  • - *
- * - * For more accurate information, please look at the CRCCU section of the - * Datasheet. - * - * Related files :\n - * \ref crccu.c\n - * \ref crccu.h.\n -*/ -/*@{*/ -/*@}*/ - -/** - * \file - * - * Implementation of Cyclic Redundancy Check Calculation Unit (CRCCU). - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include "crccu.h" -#include - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ -#define CRCCU_TIMEOUT 0xFFFFFFFF - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ -/** - * \brief Reset initial CRC to 0xFFFFFFFF. - */ -void CRCCU_ResetCrcValue(void) -{ - Crccu *pCrccu = CRCCU; - - pCrccu->CRCCU_CR = CRCCU_CR_RESET; -} - -/** - * \brief Configure the CRCCU. - * - * \param dscrAddr CRC decscriptor address. - * \param mode CRC work mode - */ -void CRCCU_Configure(uint32_t dscrAddr, uint32_t mode) -{ - Crccu *pCrccu = CRCCU; - - pCrccu->CRCCU_DSCR = dscrAddr; - pCrccu->CRCCU_MR = mode; -} - -/** - * \brief Start to compute the CRC of a buffer. - * - * \return The CRC of the buffer. - */ -uint32_t CRCCU_ComputeCrc(void) -{ - Crccu *pCrccu = CRCCU; - uint32_t timeout = 0; - - pCrccu->CRCCU_DMA_EN = CRCCU_DMA_EN_DMAEN; - while (((pCrccu->CRCCU_DMA_SR & CRCCU_DMA_SR_DMASR) == CRCCU_DMA_SR_DMASR) - && (timeout++ < CRCCU_TIMEOUT)); - - return (pCrccu->CRCCU_SR); -} - -/** - * \brief Compare the CRC of a buffer is match to reference CRC. - * - * \return if 0 CRC is match, else dismatch. - */ -uint32_t CRCCU_CompareCrc(void) -{ - Crccu *pCrccu = CRCCU; - - if ((pCrccu->CRCCU_ISR & CRCCU_ISR_ERRISR) == CRCCU_ISR_ERRISR) { - return 1; - } else { - return 0; - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/crccu/crccu.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/crccu/crccu.h deleted file mode 100644 index 7298f6109..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/crccu/crccu.h +++ /dev/null @@ -1,66 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for Cyclic Redundancy Check Calculation Unit (CRCCU). - */ - -#ifndef CRCCU_H -#define CRCCU_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - -typedef struct { - unsigned int TR_ADDR; - unsigned int TR_CTRL; - unsigned int reserved[2]; - unsigned int TR_CRC; -} CrcDscr; - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ -void CRCCU_ResetCrcValue(void); -void CRCCU_Configure(uint32_t dscrAddr, uint32_t mode); -uint32_t CRCCU_ComputeCrc(void); -uint32_t CRCCU_CompareCrc(void); - -#endif /* #ifndef CRCCU_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/dacc/dacc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/dacc/dacc.c deleted file mode 100644 index f576aa497..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/dacc/dacc.c +++ /dev/null @@ -1,172 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup dacc_module Working with DACC - * The DACC driver provides the interface to configure and use the DACC peripheral.\n - * - * The DACC(Digital-to-Analog Converter Controller) converts digital code to analog output. - * The data to be converted are sent in a common register for all channels. It offers up to 2 - * analog outputs.The output voltage ranges from (1/6)ADVREF to (5/6)ADVREF. - * - * To Enable a DACC conversion,the user has to follow these few steps: - *
    - *
  • Select an appropriate reference voltage on ADVREF
  • - *
  • Configure the DACC according to its requirements and special needs,which could be - broken down into several parts: - * -# Enable DACC in free running mode by clearing TRGEN in DACC_MR; - * -# Configure Startup Time and Refresh Period through setting STARTUP and REFRESH fields - * in DACC_MR; The refresh mechanism is used to protect the output analog value from - * decreasing. - * -# Enable channels and write digital code to DACC_CDR,in free running mode, the conversion - * is started right after at least one channel is enabled and data is written . -
  • - *
- * - * For more accurate information, please look at the DACC section of the - * Datasheet. - * - * Related files :\n - * \ref DACC.c\n - * \ref DACC.h\n -*/ -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include -#include - - - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Initialize the DACC controller - * \param pDACC Pointer to an DACC instance. - * \param idDACC identifier of DAC peripheral - * \param trgEn trigger mode, free running mode or external Hardware trigger - * \param word transfer size,word or half word - * \param trgSel hardware trigger selection - * \param sleepMode sleep mode selection - * \param mck value of MCK in Hz - * \param refresh refresh period - * \param user_sel user channel selection ,0 or 1 - * \param startup value of the start up time (in DACCClock) (see datasheet) -*/ -void DACC_Initialize (Dacc *pDACC, - uint8_t idDACC, - uint8_t trgEn, - uint8_t trgSel, - uint8_t word, - uint8_t sleepMode, - uint32_t mck, - uint8_t refresh,/*refresh period*/ - uint8_t user_sel,/*user channel selection*/ - uint32_t startup - ) -{ - ASSERT(1024*refresh*1000/(mck/2)<20,"Refresh preriod is too big!"); - - - /* Enable peripheral clock*/ - PMC->PMC_PCER0 = 1 << idDACC; - - /* Reset the controller */ - DACC_SoftReset(pDACC); - - /* Write to the MR register */ - DACC_CfgModeReg( pDACC, - ( trgEn & DACC_MR_TRGEN) - | ( trgSel & DACC_MR_TRGSEL) - | ( word & DACC_MR_WORD) - | ( sleepMode & DACC_MR_SLEEP) - | ( (refresh<<8) & DACC_MR_REFRESH) - | ( (user_sel<<16)& DACC_MR_USER_SEL) - | ( (startup<<24) & DACC_MR_STARTUP)); -} - - -/** - * Set the Conversion Data - * \param pDACC Pointer to an Dacc instance. - * \param channel channel to get converted value - * \return Channel converted data of the specified channel - */ -void DACC_SetConversionData(Dacc *pDACC, uint32_t data) -{ - uint32_t mr = pDACC->DACC_MR; - - if(mr & DACC_MR_WORD) - { - pDACC->DACC_CDR = data; - } - else - { - pDACC->DACC_CDR = (data&0xFFFF); - } -} - - -/** - * \brief Write converted data through PDC channel - * \param pDACC the pointer of DACC peripheral - * \param pBuffer the destination buffer - * \param size the size of the buffer -*/ -int8_t DACC_WriteBuffer(Dacc *pDACC,int16_t *pBuffer,int32_t size) -{ - - /* Check if the first PDC bank is free*/ - if ((pDACC->DACC_TCR == 0) && (pDACC->DACC_TNCR == 0)) { - - pDACC->DACC_TPR = (uint32_t) pBuffer; - pDACC->DACC_TCR = size; - pDACC->DACC_PTCR = DACC_PTCR_RXTEN; - - return 1; - } - /* Check if the second PDC bank is free*/ - else if (pDACC->DACC_TNCR == 0) { - - pDACC->DACC_TNPR = (uint32_t) pBuffer; - pDACC->DACC_TNCR = size; - - return 1; - } - else { - - return 0; - } - -} - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/dacc/dacc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/dacc/dacc.h deleted file mode 100644 index c2aebada3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/dacc/dacc.h +++ /dev/null @@ -1,133 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \unit - * - * !Purpose - * - * Interface for configuration the Analog-to-Digital Converter (DACC) peripheral. - * - * !Usage - * - * -# Configurate the pins for DACC - * -# Initialize the DACC with DACC_Initialize(). - * -# Select the active channel using DACC_EnableChannel() - * -# Start the conversion with DACC_StartConversion() - * -# Wait the end of the conversion by polling status with DACC_GetStatus() - * -# Finally, get the converted data using DACC_GetConvertedData() - * -*/ -#ifndef DACC_H -#define DACC_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include - -/*------------------------------------------------------------------------------ - * Definitions - *------------------------------------------------------------------------------*/ -#define DACC_CHANNEL_0 0 -#define DACC_CHANNEL_1 1 - - -/*------------------------------------------------------------------------------ - * Macros function of register access - *------------------------------------------------------------------------------*/ -#define DACC_CfgModeReg(pDACC, mode) { \ - (pDACC)->DACC_MR = (mode);\ - } - -#define DACC_GetModeReg(pDACC) ((pDACC)->DACC_MR) - -#define DACC_StartConversion(pDACC) ((pDACC)->DACC_CR = DACC_CR_START) - -#define DACC_SoftReset(pDACC) ((pDACC)->DACC_CR = DACC_CR_SWRST) - -#define DACC_EnableChannel(pDACC, channel) {\ - (pDACC)->DACC_CHER = (1 << (channel));\ - } - -#define DACC_DisableChannel (pDACC, channel) {\ - (pDACC)->DACC_CHDR = (1 << (channel));\ - } - -#define DACC_EnableIt(pDACC, mode) {\ - ASSERT(((mode)&0xFFF00000)== 0, "DACC bad interrupt IER");\ - (pDACC)->DACC_IER = (mode);\ - } - -#define DACC_DisableIt(pDACC, mode) {\ - ASSERT(((mode)&0xFFF00000)== 0, "DACC bad interrupt IDR");\ - (pDACC)->DACC_IDR = (mode);\ - } - -#define DACC_EnableDataReadyIt(pDACC) ((pDACC)->DACC_IER = AT91C_DACC_DRDY) - -#define DACC_GetStatus(pDACC) ((pDACC)->DACC_ISR) - -#define DACC_GetChannelStatus(pDACC) ((pDACC)->DACC_CHSR) - -#define DACC_GetInterruptMaskStatus(pDACC) ((pDACC)->DACC_IMR) - -#define DACC_GetLastConvertedData(pDACC) ((pDACC)->DACC_LCDR) - -#define DACC_CfgAnalogCtrlReg(pDACC,mode) {\ - ASSERT(((mode) & 0xFFFCFF3C)==0, "DACC bad analog control config");\ - (pDACC)->DACC_ACR = (mode);\ - } - -#define DACC_CfgExtModeReg(pDACC, extmode) {\ - ASSERT(((extmode) & 0xFF00FFFE)==0, "DACC bad extended mode config");\ - (pDACC)->DACC_EMR = (extmode);\ - } - -#define DACC_GetAnalogCtrlReg(pDACC) ((pDACC)->DACC_ACR) - -/*------------------------------------------------------------------------------ - * Exported functions - *------------------------------------------------------------------------------*/ -extern void DACC_Initialize (Dacc *pDACC, - uint8_t idDACC, - uint8_t trgEn, - uint8_t trgSel, - uint8_t word, - uint8_t sleepMode, - uint32_t mck, - uint8_t refresh,/*refresh period*/ - uint8_t user_sel,/*user channel selection*/ - uint32_t startup - ); - - -extern void DACC_SetConversionData(Dacc *pDACC, uint32_t data); - -#endif //#ifndef DACC_H diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/efc/efc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/efc/efc.c deleted file mode 100644 index 56ace4b0f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/efc/efc.c +++ /dev/null @@ -1,286 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup efc_module Working with Enhanced Embedded Flash - * The EEFC driver provides the interface to configure and use the EEFC - * peripheral. - * - * The user needs to set the number of wait states depending on the frequency used.\n - * Configure number of cycles for flash read/write operations in the FWS field of EEFC_FMR. - * - * It offers a function to send flash command to EEFC and waits for the - * flash to be ready. - * - * To send flash command, the user could do in either of following way: - *
    - *
  • Write a correct key, command and argument in EEFC_FCR.
  • - *
  • Or, Use IAP (In Application Programming) function which is executed from - * ROM directly, this allows flash programming to be done by code running in flash.
  • - *
  • Once the command is achieved, it can be detected even by polling EEFC_FSR or interrupt. - *
- * - * The command argument could be a page number,GPNVM number or nothing, it depends on - * the command itself. Some useful functions in this driver could help user tranlate physical - * flash address into a page number and vice verse. - * - * For more accurate information, please look at the EEFC section of the - * Datasheet. - * - * Related files :\n - * \ref efc.c\n - * \ref efc.h.\n -*/ -/*@{*/ -/*@}*/ - - -/** - * \file - * - * Implementation of Emhance embedded Flash (EEFC) controller. - * - */ - - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include -#include "efc.h" -#include -#include - - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Enables the flash ready interrupt source on the EEFC peripheral. - * - * \param efc Pointer to a Efc instance - */ -void EFC_EnableFrdyIt(Efc *efc) -{ - efc->EEFC_FMR |= EEFC_FMR_FRDY; -} - -/** - * \brief Disables the flash ready interrupt source on the EEFC peripheral. - * - * \param efc Pointer to a Efc instance - */ - -void EFC_DisableFrdyIt(Efc *efc) -{ - efc->EEFC_FMR &= ~EEFC_FMR_FRDY; -} - - -/** - * \brief Set read/write wait state on the EEFC perpherial. - * - * \param efc Pointer to a Efc instance - * \param cycles the number of wait states in cycle. - */ - -void EFC_SetWaitState(Efc *efc, uint8_t cycles) -{ - uint32_t value; - value = efc->EEFC_FMR; - value &= ~EEFC_FMR_FWS; - value |= cycles << 8; - efc->EEFC_FMR = value; -} - -/** - * \brief Returns the current status of the EEFC. - * - * \note Keep in mind that this function clears the value of some status bits (LOCKE, PROGE). - * - * \param efc Pointer to a Efc instance - */ -uint32_t EFC_GetStatus(Efc *efc) -{ - return efc->EEFC_FSR; -} - -/** - * \brief Returns the result of the last executed command. - * - * \param efc Pointer to a Efc instance - */ -uint32_t EFC_GetResult(Efc *efc) { - - return efc->EEFC_FRR; -} - -/** - * \brief Translates the given address page and offset values. - * \note The resulting values are stored in the provided variables if they are not null. - * - * \param efc Pointer to a Efc instance - * \param address Address to translate. - * \param pPage First page accessed. - * \param pOffset Byte offset in first page. - */ -void EFC_TranslateAddress( - Efc **efc, - uint32_t address, - unsigned short *pPage, - unsigned short *pOffset) -{ - Efc *pEfc; - unsigned short page; - unsigned short offset; - - SANITY_CHECK(address >= AT91C_IFLASH); - SANITY_CHECK(address <= (AT91C_IFLASH + AT91C_IFLASH_SIZE)); - - pEfc = EFC; - page = (address - AT91C_IFLASH) / AT91C_IFLASH_PAGE_SIZE; - offset = (address - AT91C_IFLASH) % AT91C_IFLASH_PAGE_SIZE; - - TRACE_DEBUG("Translated 0x%08X to page=%d and offset=%d\n\r", address, page, offset); - // Store values - if (pEfc) { - *efc = pEfc; - } - if (pPage) { - *pPage = page; - } - if (pOffset) { - *pOffset = offset; - } -} - -/** - * \brief Computes the address of a flash access given the page and offset. - * - * \param efc Pointer to a Efc instance - * \param page Page number. - * \param offset Byte offset inside page. - * \param pAddress Computed address (optional). - */ -void EFC_ComputeAddress( - Efc *efc, - unsigned short page, - unsigned short offset, - uint32_t *pAddress) -{ - uint32_t address; - SANITY_CHECK(efc); - SANITY_CHECK(page <= AT91C_IFLASH_NB_OF_PAGES); - SANITY_CHECK(offset < AT91C_IFLASH_PAGE_SIZE); - // Compute address - address = AT91C_IFLASH + page * AT91C_IFLASH_PAGE_SIZE + offset; - // Store result - if (pAddress) { - *pAddress = address; - } -} - -/** - * \brief Starts the executing the given command on the EEFC and returns as soon as the command is started. - * - * \note It does NOT set the FMCN field automatically. - * \param efc Pointer to a Efc instance - * \param command Command to execute. - * \param argument Command argument (should be 0 if not used). - */ -void EFC_StartCommand(Efc *efc, uint8_t command, unsigned short argument) -{ - // Check command & argument - switch (command) { - - case EFC_FCMD_WP: - case EFC_FCMD_WPL: - case EFC_FCMD_EWP: - case EFC_FCMD_EWPL: - case EFC_FCMD_SLB: - case EFC_FCMD_CLB: - ASSERT(argument < AT91C_IFLASH_NB_OF_PAGES, - "-F- Embedded flash has only %d pages\n\r", - AT91C_IFLASH_NB_OF_PAGES); - break; - - case EFC_FCMD_SFB: - case EFC_FCMD_CFB: - ASSERT(argument < 2, "-F- Embedded flash has only %d GPNVMs\n\r", 2); - break; - - case EFC_FCMD_GETD: - case EFC_FCMD_EA: - case EFC_FCMD_GLB: - case EFC_FCMD_GFB: - case EFC_FCMD_STUI: - ASSERT(argument == 0, "-F- Argument is meaningless for the given command.\n\r"); - break; - - default: ASSERT(0, "-F- Unknown command %d\n\r", command); - } - - // Start command Embedded flash - ASSERT((efc->EEFC_FSR & EEFC_FMR_FRDY) == EEFC_FMR_FRDY, "-F- EEFC is not ready\n\r"); - efc->EEFC_FCR = (0x5A << 24) | (argument << 8) | command; -} - -/** - * \brief Performs the given command and wait until its completion (or an error). - * - * \param efc Pointer to a Efc instance - * \param command Command to perform. - * \param argument Optional command argument. - * \return 0 if successful, otherwise returns an error code. - */ - -uint8_t EFC_PerformCommand(Efc *efc, uint8_t command, unsigned short argument) -{ - -#if defined(flash) || defined(USE_IAP_FEATURE) - // Pointer on IAP function in ROM - static uint32_t (*IAP_PerformCommand)(uint32_t, uint32_t); - IAP_PerformCommand = (uint32_t (*)(uint32_t, uint32_t)) *((uint32_t *) CHIP_FLASH_IAP_ADDRESS); - IAP_PerformCommand(0, (0x5A << 24) | (argument << 8) | command); - return (efc->EEFC_FSR & (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE)); - -#else - uint32_t status; - efc->EEFC_FCR = (0x5A << 24) | (argument << 8) | command; - do { - - status = efc->EEFC_FSR; - } - while ((status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY); - - return (status & (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE)); -#endif -} - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/efc/efc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/efc/efc.h deleted file mode 100644 index 84fabc38f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/efc/efc.h +++ /dev/null @@ -1,112 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * \par Purpose - * - * Interface for configuration the Enhanced Embedded Flash Controller (EEFC) peripheral. - * - * \par Usage - * - * -# Enable/disable %flash ready interrupt sources using EFC_EnableFrdyIt() - * and EFC_DisableFrdyIt(). - * -# Translates the given address into which EEFC, page and offset values - * for difference density %flash memory using EFC_TranslateAddress(). - * -# Computes the address of a %flash access given the EFC, page and offset - * for difference density %flash memory using EFC_ComputeAddress(). - * -# Start the executing command with EFC_StartCommand() - * -# Retrieve the current status of the EFC using EFC_GetStatus(). - * -# Retrieve the result of the last executed command with EFC_GetResult(). - */ - -#ifndef EFC_H -#define EFC_H - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ -/* EFC command */ -#define EFC_FCMD_GETD 0x00 -#define EFC_FCMD_WP 0x01 -#define EFC_FCMD_WPL 0x02 -#define EFC_FCMD_EWP 0x03 -#define EFC_FCMD_EWPL 0x04 -#define EFC_FCMD_EA 0x05 -#define EFC_FCMD_SLB 0x08 -#define EFC_FCMD_CLB 0x09 -#define EFC_FCMD_GLB 0x0A -#define EFC_FCMD_SFB 0x0B -#define EFC_FCMD_CFB 0x0C -#define EFC_FCMD_GFB 0x0D -#define EFC_FCMD_STUI 0x0E -#define EFC_FCMD_SPUI 0x0F - -/* The IAP function entry addreass */ -#define CHIP_FLASH_IAP_ADDRESS (0x00800008) - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void EFC_EnableFrdyIt(Efc *efc); - -extern void EFC_DisableFrdyIt(Efc *efc); - -extern void EFC_SetWaitState(Efc *efc, uint8_t cycles); - -extern void EFC_TranslateAddress( - Efc **pEfc, - uint32_t address, - unsigned short *pPage, - unsigned short *pOffset); - -extern void EFC_ComputeAddress( - Efc *efc, - unsigned short page, - unsigned short offset, - uint32_t *pAddress); - -extern void EFC_StartCommand( - Efc *efc, - uint8_t command, - unsigned short argument); - -extern uint8_t EFC_PerformCommand( - Efc *efc, - uint8_t command, - unsigned short argument); - -extern uint32_t EFC_GetStatus(Efc *efc); - -extern uint32_t EFC_GetResult(Efc *efc); - -#endif //#ifndef EFC_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/flash/flashd.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/flash/flashd.c deleted file mode 100644 index c0e669132..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/flash/flashd.c +++ /dev/null @@ -1,494 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup flashd_module Flash Memory Interface - * The flash driver manages the programming, erasing, locking and unlocking sequences - * with dedicated commands. - * - * To implement flash programing operation, the user has to follow these few steps : - *
    - *
  • Configue flash wait states to initializes the flash.
  • - *
  • Checks whether a region to be programmed is locked.
  • - *
  • Unlocks the user region to be programmed if the region have locked before.
  • - *
  • Erases the user page before program (optional).
  • - *
  • Writes the user page from the page buffer.
  • - *
  • Locks the region of programmed area if any.
  • - *
- * - * Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption. - * A check of this validity and padding for 32-bit alignment should be done in write algorithm. - - * Lock/unlock range associated with the user address range is automatically translated. - * - * This security bit can be enabled through the command "Set General Purpose NVM Bit 0". - * - * A 128-bit factory programmed unique ID could be read to serve several purposes. - * - * The driver accesses the flash memory by calling the lowlevel module provided in \ref efc_module. - * For more accurate information, please look at the EEFC section of the Datasheet. - * - * Related files :\n - * \ref flashd.c\n - * \ref flashd.h.\n - * \ref efc.c\n - * \ref efc.h.\n -*/ -/*@{*/ -/*@}*/ - - -/** - * \file - * - * The flash driver provides the unified interface for flash program operations. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include "flashd.h" -#include - -#include -#include -#include -#include - -#include - - -/*---------------------------------------------------------------------------- - * Local functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Computes the lock range associated with the given address range. - * - * \param start Start address of lock range. - * \param end End address of lock range. - * \param pActualStart Actual start address of lock range. - * \param pActualEnd Actual end address of lock range. - */ -static void ComputeLockRange( - uint32_t start, - uint32_t end, - uint32_t *pActualStart, - uint32_t *pActualEnd) -{ - Efc *pStartEfc, *pEndEfc; - uint16_t startPage, endPage; - uint16_t numPagesInRegion; - uint16_t actualStartPage, actualEndPage; - - // Convert start and end address in page numbers - EFC_TranslateAddress(&pStartEfc, start, &startPage, 0); - EFC_TranslateAddress(&pEndEfc, end, &endPage, 0); - - // Find out the first page of the first region to lock - numPagesInRegion = AT91C_IFLASH_LOCK_REGION_SIZE / AT91C_IFLASH_PAGE_SIZE; - actualStartPage = startPage - (startPage % numPagesInRegion); - actualEndPage = endPage; - if ((endPage % numPagesInRegion) != 0) { - - actualEndPage += numPagesInRegion - (endPage % numPagesInRegion); - } - // Store actual page numbers - EFC_ComputeAddress(pStartEfc, actualStartPage, 0, pActualStart); - EFC_ComputeAddress(pEndEfc, actualEndPage, 0, pActualEnd); - TRACE_DEBUG("Actual lock range is 0x%06X - 0x%06X\n\r", *pActualStart, *pActualEnd); -} - - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Initializes the flash driver. - * - * \param mck Master clock frequency in Hz. - */ - -void FLASHD_Initialize(uint32_t mck) -{ - EFC_DisableFrdyIt(EFC); - if ((mck/1000000) >= 64) { - EFC_SetWaitState(EFC, 2); - } - else if ((mck/1000000) >= 50) { - EFC_SetWaitState(EFC, 1); - } - else { - EFC_SetWaitState(EFC, 0); - } -} - -/** - * \brief Erases the entire flash. - * - * \param address Flash start address. - * \return 0 if successful; otherwise returns an error code. - */ -uint8_t FLASHD_Erase(uint32_t address) -{ - Efc *pEfc; - uint16_t page; - uint16_t offset; - uint8_t error; - SANITY_CHECK((address >=AT91C_IFLASH) || (address <= (AT91C_IFLASH + AT91C_IFLASH_SIZE))); - // Translate write address - EFC_TranslateAddress(&pEfc, address, &page, &offset); - error = EFC_PerformCommand(pEfc, EFC_FCMD_EA, 0); - return error; -} - - -static uint8_t pPageBuffer[AT91C_IFLASH_PAGE_SIZE]; -/** - * \brief Writes a data buffer in the internal flash - * - * \note This function works in polling mode, and thus only returns when the - * data has been effectively written. - * \param address Write address. - * \param pBuffer Data buffer. - * \param size Size of data buffer in bytes. - * \return 0 if successful, otherwise returns an error code. - */ -uint8_t FLASHD_Write( - uint32_t address, - const void *pBuffer, - uint32_t size) -{ - Efc *pEfc; - uint16_t page; - uint16_t offset; - uint32_t writeSize; - uint32_t pageAddress; - uint16_t padding; - uint8_t error; - - uint32_t sizeTmp; - uint32_t *pAlignedDestination; - uint32_t *pAlignedSource; - - SANITY_CHECK(pBuffer); - SANITY_CHECK(address >=AT91C_IFLASH); - SANITY_CHECK((address + size) <= (AT91C_IFLASH + AT91C_IFLASH_SIZE)); - // Translate write address - EFC_TranslateAddress(&pEfc, address, &page, &offset); - - // Write all pages - while (size > 0) { - - // Copy data in temporary buffer to avoid alignment problems - writeSize = min(AT91C_IFLASH_PAGE_SIZE - offset, size); - EFC_ComputeAddress(pEfc, page, 0, &pageAddress); - padding = AT91C_IFLASH_PAGE_SIZE - offset - writeSize; - - // Pre-buffer data - memcpy(pPageBuffer, (void *) pageAddress, offset); - - // Buffer data - memcpy(pPageBuffer + offset, pBuffer, writeSize); - - // Post-buffer data - memcpy(pPageBuffer + offset + writeSize, (void *) (pageAddress + offset + writeSize), padding); - - // Write page - // Writing 8-bit and 16-bit data is not allowed - // and may lead to unpredictable data corruption - pAlignedDestination = (uint32_t*)pageAddress; - pAlignedSource = (uint32_t*)pPageBuffer; - sizeTmp = AT91C_IFLASH_PAGE_SIZE; - while (sizeTmp >= 4) { - - *pAlignedDestination++ = *pAlignedSource++; - sizeTmp -= 4; - } - - // Send writing command - error = EFC_PerformCommand(pEfc, EFC_FCMD_EWP, page); - if (error) { - - return error; - } - - // Progression - address += AT91C_IFLASH_PAGE_SIZE; - pBuffer = (void *) ((uint32_t) pBuffer + writeSize); - size -= writeSize; - page++; - offset = 0; - } - - return 0; -} -/** - * \brief Locks all the regions in the given address range. The actual lock range is - * reported through two output parameters. - * \param address Start address of lock range. - * \param end End address of lock range. - * \param pActualStart Start address of the actual lock range (optional). - * \param pActualEnd End address of the actual lock range (optional). - * \return 0 if successful, otherwise returns an error code. - */ -uint8_t FLASHD_Lock( - uint32_t start, - uint32_t end, - uint32_t *pActualStart, - uint32_t *pActualEnd) -{ - Efc *pEfc; - uint32_t actualStart, actualEnd; - uint16_t startPage, endPage; - uint8_t error; - uint16_t numPagesInRegion = AT91C_IFLASH_LOCK_REGION_SIZE / AT91C_IFLASH_PAGE_SIZE; - - // Compute actual lock range and store it - ComputeLockRange(start, end, &actualStart, &actualEnd); - if (pActualStart) { - - *pActualStart = actualStart; - } - if (pActualEnd) { - - *pActualEnd = actualEnd; - } - - // Compute page numbers - EFC_TranslateAddress(&pEfc, actualStart, &startPage, 0); - EFC_TranslateAddress(0, actualEnd, &endPage, 0); - - // Lock all pages - while (startPage < endPage) { - - error = EFC_PerformCommand(pEfc, EFC_FCMD_SLB, startPage); - if (error) { - - return error; - } - startPage += numPagesInRegion; - } - - return 0; -} - -/** - * \brief Unlocks all the regions in the given address range. The actual unlock range is - * reported through two output parameters. - * \param address Start address of unlock range. - * \param end End address of unlock range. - * \param pActualStart Start address of the actual unlock range (optional). - * \param pActualEnd End address of the actual unlock range (optional). - * \return 0 if successful, otherwise returns an error code. - */ -uint8_t FLASHD_Unlock( - uint32_t start, - uint32_t end, - uint32_t *pActualStart, - uint32_t *pActualEnd) -{ - Efc *pEfc; - uint32_t actualStart, actualEnd; - uint16_t startPage, endPage; - uint8_t error; - uint16_t numPagesInRegion = AT91C_IFLASH_LOCK_REGION_SIZE / AT91C_IFLASH_PAGE_SIZE; - - // Compute actual unlock range and store it - ComputeLockRange(start, end, &actualStart, &actualEnd); - if (pActualStart) { - - *pActualStart = actualStart; - } - if (pActualEnd) { - - *pActualEnd = actualEnd; - } - - // Compute page numbers - EFC_TranslateAddress(&pEfc, actualStart, &startPage, 0); - EFC_TranslateAddress(0, actualEnd, &endPage, 0); - - // Unlock all pages - while (startPage < endPage) { - - error = EFC_PerformCommand(pEfc, EFC_FCMD_CLB, startPage); - if (error) { - - return error; - } - startPage += numPagesInRegion; - } - return 0; -} - -/** - * \brief Returns the number of locked regions inside the given address range. - * - * \param address Start address of range - * \param end End address of range. - */ -uint8_t FLASHD_IsLocked(uint32_t start, uint32_t end) -{ - Efc *pEfc; - uint16_t startPage, endPage; - uint8_t startRegion, endRegion; - uint32_t numPagesInRegion; - uint32_t status; - uint8_t error; - uint32_t numLockedRegions = 0; - - SANITY_CHECK(end >= start); - SANITY_CHECK((start >=AT91C_IFLASH) && (end <= AT91C_IFLASH + AT91C_IFLASH_SIZE)); - - // Compute page numbers - EFC_TranslateAddress(&pEfc, start, &startPage, 0); - EFC_TranslateAddress(0, end, &endPage, 0); - - // Compute region numbers - numPagesInRegion = AT91C_IFLASH_LOCK_REGION_SIZE / AT91C_IFLASH_PAGE_SIZE; - startRegion = startPage / numPagesInRegion; - endRegion = endPage / numPagesInRegion; - if ((endPage % numPagesInRegion) != 0) { - - endRegion++; - } - - // Retrieve lock status - error = EFC_PerformCommand(pEfc, EFC_FCMD_GLB, 0); - ASSERT(!error, "-F- Error while trying to fetch lock bits status (0x%02X)\n\r", error); - status = EFC_GetResult(pEfc); - - // Check status of each involved region - while (startRegion < endRegion) { - - if ((status & (1 << startRegion)) != 0) { - - numLockedRegions++; - } - startRegion++; - } - - return numLockedRegions; -} - -/** - * \brief Check if the given GPNVM bit is set or not. - * - * \param gpnvm GPNVM bit index. - * \returns 1 if the given GPNVM bit is currently set; otherwise returns 0. - */ -uint8_t FLASHD_IsGPNVMSet(uint8_t gpnvm) -{ - uint8_t error; - uint32_t status; - - SANITY_CHECK(gpnvm < 2); - - // Get GPNVMs status - error = EFC_PerformCommand(EFC, EFC_FCMD_GFB, 0); - ASSERT(!error, "-F- Error while trying to fetch GPNVMs status (0x%02X)\n\r", error); - status = EFC_GetResult(EFC); - - // Check if GPNVM is set - if ((status & (1 << gpnvm)) != 0) { - return 1; - } - else { - return 0; - } -} -/** - * \brief Sets the selected GPNVM bit. - * - * \param gpnvm GPNVM bit index. - * \returns 0 if successful; otherwise returns an error code. - */ -uint8_t FLASHD_SetGPNVM(uint8_t gpnvm) -{ - SANITY_CHECK(gpnvm < 2); - - if (!FLASHD_IsGPNVMSet(gpnvm)) { - - return EFC_PerformCommand(EFC, EFC_FCMD_SFB, gpnvm); - } - else { - - return 0; - } -} - -/** - * \brief Clears the selected GPNVM bit. - * - * \param gpnvm GPNVM bit index. - * \returns 0 if successful; otherwise returns an error code. - */ -uint8_t FLASHD_ClearGPNVM(uint8_t gpnvm) -{ - SANITY_CHECK(gpnvm < 2); - - if (FLASHD_IsGPNVMSet(gpnvm)) { - - return EFC_PerformCommand(EFC, EFC_FCMD_CFB, gpnvm); - } - else { - - return 0; - } -} -/** - * \brief Read the unique ID. - * - * \param uniqueID pointer on a 4bytes char containing the unique ID value. - * \returns 0 if successful; otherwise returns an error code. - */ -uint8_t FLASHD_ReadUniqueID (uint32_t * uniqueID) -{ - uint8_t error; - SANITY_CHECK(uniqueID != NULL); - - uniqueID[0] = 0; - uniqueID[1] = 0; - uniqueID[2] = 0; - uniqueID[3] = 0; - - EFC_StartCommand(EFC, EFC_FCMD_STUI, 0); - - uniqueID[0] = *(uint32_t *)AT91C_IFLASH; - uniqueID[1] = *(uint32_t *)(AT91C_IFLASH + 4); - uniqueID[2] = *(uint32_t *)(AT91C_IFLASH + 8); - uniqueID[3] = *(uint32_t *)(AT91C_IFLASH + 12); - - error = EFC_PerformCommand(EFC, EFC_FCMD_SPUI, 0); - if (error) return error; - - return 0; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/flash/flashd.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/flash/flashd.h deleted file mode 100644 index 14b765b2f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/flash/flashd.h +++ /dev/null @@ -1,84 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- -*/ - -/** - * \file - * - * The flash driver provides the unified interface for flash program operations. - * - */ - -#ifndef FLASHD_H -#define FLASHD_H - -#include - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void FLASHD_Initialize(uint32_t mck); - -extern uint8_t FLASHD_Erase(uint32_t address); - -extern uint8_t FLASHD_Write( - uint32_t address, - const void *pBuffer, - uint32_t size); - -extern uint8_t FLASHD_Lock( - uint32_t start, - uint32_t end, - uint32_t *pActualStart, - uint32_t *pActualEnd); - -extern uint8_t FLASHD_Unlock( - uint32_t start, - uint32_t end, - uint32_t *pActualStart, - uint32_t *pActualEnd); - -extern uint8_t FLASHD_IsLocked( - uint32_t start, - uint32_t end); - -extern uint8_t FLASHD_SetGPNVM(uint8_t gpnvm); - -extern uint8_t FLASHD_ClearGPNVM(uint8_t gpnvm); - -extern uint8_t FLASHD_IsGPNVMSet(uint8_t gpnvm); - -#define FLASHD_IsSecurityBitSet() FLASHD_IsGPNVMSet(0) - -#define FLASHD_SetSecurityBit() FLASHD_SetGPNVM(0) - -extern uint8_t FLASHD_ReadUniqueID(uint32_t * uniqueID); - -#endif //#ifndef FLASHD_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/color.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/color.h deleted file mode 100644 index 3258b82cc..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/color.h +++ /dev/null @@ -1,85 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef COLOR_H -#define COLOR_H - -/** - * \file - * - * RGB 24-bits color table definition. - * - */ - -/* - * RGB 24 Bpp - * RGB 888 - * R7R6R5R4 R3R2R1R0 G7G6G5G4 G3G2G1G0 B7B6B5B4 B3B2B1B0 - */ -#define COLOR_BLACK 0x000000 -#define COLOR_WHITE 0xFFFFFF - -#define COLOR_BLUE 0x0000FF -#define COLOR_GREEN 0x00FF00 -#define COLOR_RED 0xFF0000 - -#define COLOR_NAVY 0x000080 -#define COLOR_DARKBLUE 0x00008B -#define COLOR_DARKGREEN 0x006400 -#define COLOR_DARKCYAN 0x008B8B -#define COLOR_CYAN 0x00FFFF -#define COLOR_TURQUOISE 0x40E0D0 -#define COLOR_INDIGO 0x4B0082 -#define COLOR_DARKRED 0x800000 -#define COLOR_OLIVE 0x808000 -#define COLOR_GRAY 0x808080 -#define COLOR_SKYBLUE 0x87CEEB -#define COLOR_BLUEVIOLET 0x8A2BE2 -#define COLOR_LIGHTGREEN 0x90EE90 -#define COLOR_DARKVIOLET 0x9400D3 -#define COLOR_YELLOWGREEN 0x9ACD32 -#define COLOR_BROWN 0xA52A2A -#define COLOR_DARKGRAY 0xA9A9A9 -#define COLOR_SIENNA 0xA0522D -#define COLOR_LIGHTBLUE 0xADD8E6 -#define COLOR_GREENYELLOW 0xADFF2F -#define COLOR_SILVER 0xC0C0C0 -#define COLOR_LIGHTGREY 0xD3D3D3 -#define COLOR_LIGHTCYAN 0xE0FFFF -#define COLOR_VIOLET 0xEE82EE -#define COLOR_AZUR 0xF0FFFF -#define COLOR_BEIGE 0xF5F5DC -#define COLOR_MAGENTA 0xFF00FF -#define COLOR_TOMATO 0xFF6347 -#define COLOR_GOLD 0xFFD700 -#define COLOR_ORANGE 0xFFA500 -#define COLOR_SNOW 0xFFFAFA -#define COLOR_YELLOW 0xFFFF00 - -#endif /* #define COLOR_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/draw.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/draw.c deleted file mode 100644 index 4e1975be0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/draw.c +++ /dev/null @@ -1,333 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of draw function on LCD, Include draw text, image - * and basic shapes (line, rectangle, circle). - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include - -#include "draw.h" -#include "font.h" -#include -#include -#include - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Fills the given LCD buffer with a particular color. - * - * \param color Fill color. - */ -void LCDD_Fill(uint32_t color) -{ - uint32_t i; - - LCD_SetCursor(0, 0); - LCD_WriteRAM_Prepare(); - for (i = 0; i < (BOARD_LCD_WIDTH * BOARD_LCD_HEIGHT); i++) { - - LCD_WriteRAM(color); - } -} - -/** - * \brief Draw a pixel on LCD of given color. - * - * \param x X-coordinate of pixel. - * \param y Y-coordinate of pixel. - * \param color Pixel color. - */ -void LCDD_DrawPixel( - uint32_t x, - uint32_t y, - uint32_t color) -{ - LCD_SetCursor(x, y); - LCD_WriteRAM_Prepare(); - LCD_WriteRAM(color); -} - -/** - * \brief Read a pixel from LCD. - * - * \param x X-coordinate of pixel. - * \param y Y-coordinate of pixel. - * - * \return color Readed pixel color. - */ -uint32_t LCDD_ReadPixel( - uint32_t x, - uint32_t y) -{ - uint32_t color; - - LCD_SetCursor(x, y); - LCD_ReadRAM_Prepare(); - color = LCD_ReadRAM(); - - return color; -} - -/* - * \brief Draw a line on LCD, horizontal and vertical line are supported. - * - * \param x X-coordinate of line start. - * \param y Y-coordinate of line start. - * \param length line length. - * \param direction line direction: 0 - horizontal, 1 - vertical. - * \param color Pixel color. - */ -void LCDD_DrawLine( - uint32_t x, - uint32_t y, - uint32_t length, - uint32_t direction, - uint32_t color) -{ - uint32_t i = 0; - - LCD_SetCursor(x, y); - - if(direction == DIRECTION_HLINE) { - LCD_WriteRAM_Prepare(); - for(i = 0; i < length; i++) { - LCD_WriteRAM(color); - } - } - else { - for(i = 0; i < length; i++) { - LCD_WriteRAM_Prepare(); - LCD_WriteRAM(color); - y++; - LCD_SetCursor(x, y); - } - } -} - -/* - * \brief Draws a rectangle on LCD, at the given coordinates. - * - * \param x X-coordinate of upper-left rectangle corner. - * \param y Y-coordinate of upper-left rectangle corner. - * \param width Rectangle width in pixels. - * \param height Rectangle height in pixels. - * \param color Rectangle color. - */ -void LCDD_DrawRectangle( - uint32_t x, - uint32_t y, - uint32_t width, - uint32_t height, - uint32_t color) -{ - LCDD_DrawLine(x, y, width, DIRECTION_HLINE, color); - LCDD_DrawLine(x, (y + height), width, DIRECTION_HLINE, color); - - LCDD_DrawLine(x, y, height, DIRECTION_VLINE, color); - LCDD_DrawLine((x + width), y, height, DIRECTION_VLINE, color); -} - -/* - * \brief Draws a rectangle with fill inside on LCD, at the given coordinates. - * - * \param x X-coordinate of upper-left rectangle corner. - * \param y Y-coordinate of upper-left rectangle corner. - * \param width Rectangle width in pixels. - * \param height Rectangle height in pixels. - * \param color Rectangle color. - */ -void LCDD_DrawRectangleWithFill( - uint32_t x, - uint32_t y, - uint32_t width, - uint32_t height, - uint32_t color) -{ - uint32_t i; - - for (i = 0; i < height; i++) { - LCDD_DrawLine(x, y+i, width, DIRECTION_HLINE, color); - } -} - -/** - * \brief Draws a circle on LCD, at the given coordinates. - * - * \param x X-coordinate of circle center. - * \param y Y-coordinate of circle center. - * \param r circle radius. - * \param color circle color. - */ -void LCDD_DrawCircle( - uint32_t x, - uint32_t y, - uint32_t r, - uint32_t color) -{ - signed int d; /* Decision Variable */ - uint32_t curX; /* Current X Value */ - uint32_t curY; /* Current Y Value */ - - d = 3 - (r << 1); - curX = 0; - curY = r; - - while (curX <= curY) - { - LCDD_DrawPixel(x + curX, y + curY, color); - LCDD_DrawPixel(x + curX, y - curY, color); - LCDD_DrawPixel(x - curX, y + curY, color); - LCDD_DrawPixel(x - curX, y - curY, color); - LCDD_DrawPixel(x + curY, y + curX, color); - LCDD_DrawPixel(x + curY, y - curX, color); - LCDD_DrawPixel(x - curY, y + curX, color); - LCDD_DrawPixel(x - curY, y - curX, color); - - if (d < 0) { - d += (curX << 2) + 6; - } - else { - d += ((curX - curY) << 2) + 10; - curY--; - } - curX++; - } -} - -/** - * \brief Draws a string inside a LCD buffer, at the given coordinates. Line breaks - * will be honored. - * - * \param x X-coordinate of string top-left corner. - * \param y Y-coordinate of string top-left corner. - * \param pString String to display. - * \param color String color. - */ -void LCDD_DrawString( - uint32_t x, - uint32_t y, - const uint8_t *pString, - uint32_t color) -{ - unsigned xorg = x; - - while (*pString != 0) { - if (*pString == '\n') { - - y += gFont.height + 2; - x = xorg; - } - else { - - LCDD_DrawChar(x, y, *pString, color); - x += gFont.width + 2; - } - pString++; - } -} - -/** - * \brief Returns the width & height in pixels that a string will occupy on the screen - * if drawn using LCDD_DrawString. - * - * \param pString String. - * \param pWidth Pointer for storing the string width (optional). - * \param pHeight Pointer for storing the string height (optional). - * - * \return String width in pixels. - */ -void LCDD_GetStringSize( - const uint8_t *pString, - uint32_t *pWidth, - uint32_t *pHeight) -{ - uint32_t width = 0; - uint32_t height = gFont.height; - - while (*pString != 0) { - - if (*pString == '\n') { - - height += gFont.height + 2; - } - else { - - width += gFont.width + 2; - } - pString++; - } - - if (width > 0) width -= 2; - - if (pWidth) *pWidth = width; - if (pHeight) *pHeight = height; -} - -/* - * \brief Draw a raw image at given position on LCD. - * - * \param x X-coordinate of image start. - * \param y Y-coordinate of image start. - * \param pImage Image buffer. - * \param width Image width. - * \param height Image height. - */ -void LCDD_DrawImage( - uint32_t x, - uint32_t y, - const uint8_t *pImage, - uint32_t width, - uint32_t height) -{ - uint32_t row, col; - - for(row = y; row < (y + height); row++) { - LCD_SetCursor(x, row); - LCD_WriteRAM_Prepare(); - for(col = x; col < (x + width); col++) { - LCD_D() = *pImage++; - LCD_D() = *pImage++; - LCD_D() = *pImage++; - } - } -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/draw.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/draw.h deleted file mode 100644 index e7fb7a57f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/draw.h +++ /dev/null @@ -1,114 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - - /** - * \file - * - * Interface for draw function on LCD. - * - */ - -#ifndef DRAW_H -#define DRAW_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -/** Horizontal direction line definition */ -#define DIRECTION_HLINE 0 -/** Vertical direction line definition */ -#define DIRECTION_VLINE 1 - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ -extern void LCDD_Fill(uint32_t color); - -extern void LCDD_DrawPixel( - uint32_t x, - uint32_t y, - uint32_t c); - -extern uint32_t LCDD_ReadPixel( - uint32_t x, - uint32_t y); - -extern void LCDD_DrawLine( - uint32_t x, - uint32_t y, - uint32_t length, - uint32_t direction, - uint32_t color); - -extern void LCDD_DrawRectangle( - uint32_t x, - uint32_t y, - uint32_t width, - uint32_t height, - uint32_t color); - -extern void LCDD_DrawRectangleWithFill( - uint32_t x, - uint32_t y, - uint32_t width, - uint32_t height, - uint32_t color); - -extern void LCDD_DrawCircle( - uint32_t x, - uint32_t y, - uint32_t r, - uint32_t color); - -extern void LCDD_DrawString( - uint32_t x, - uint32_t y, - const uint8_t *pString, - uint32_t color); - -extern void LCDD_GetStringSize( - const uint8_t *pString, - uint32_t *pWidth, - uint32_t *pHeight); - -extern void LCDD_DrawImage( - uint32_t x, - uint32_t y, - const uint8_t *pImage, - uint32_t width, - uint32_t height); - -#endif /* #ifndef DRAW_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/font.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/font.c deleted file mode 100644 index 4a1612980..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/font.c +++ /dev/null @@ -1,95 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of draw font on LCD. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include "color.h" -#include "font.h" -#include "draw.h" -#include "font10x14.h" -#include - -/*---------------------------------------------------------------------------- - * Local variables - *----------------------------------------------------------------------------*/ - -/** Global variable describing the font being instancied. */ -const Font gFont = {10, 14}; - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Draws an ASCII character on LCD. - * - * \param x X-coordinate of character upper-left corner. - * \param y Y-coordinate of character upper-left corner. - * \param c Character to output. - * \param color Character color. -*/ -void LCDD_DrawChar( - uint32_t x, - uint32_t y, - uint8_t c, - uint32_t color) -{ - uint32_t row, col; - - SANITY_CHECK((c >= 0x20) && (c <= 0x7F)); - - for (col = 0; col < 10; col++) { - - for (row = 0; row < 8; row++) { - - if ((pCharset10x14[((c - 0x20) * 20) + col * 2] >> (7 - row)) & 0x1) { - - LCDD_DrawPixel(x+col, y+row, color); - } - } - for (row = 0; row < 6; row++) { - - if ((pCharset10x14[((c - 0x20) * 20) + col * 2 + 1] >> (7 - row)) & 0x1) { - - LCDD_DrawPixel(x+col, y+row+8, color); - } - } - } -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/font.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/font.h deleted file mode 100644 index d46cf6c45..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/font.h +++ /dev/null @@ -1,92 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for draw font on LCD. - * - */ - -/** - * - * \section Purpose - * - * The font.h files declares a font structure and a LCDD_DrawChar function - * that must be implemented by a font definition file to be used with the - * LCDD_DrawString method of draw.h. - * - * The font10x14.c implements the necessary variable and function for a 10x14 - * font. - * - * \section Usage - * - * -# Declare a gFont global variable with the necessary Font information. - * -# Implement an LCDD_DrawChar function which displays the specified - * character on the LCD. - * -# Use the LCDD_DrawString method defined in draw.h to display a complete - * string. - */ - -#ifndef FONT_H -#define FONT_H - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - - -/** Describes the font (width, height, supported characters, etc.) used by - * the LCD driver draw API. - */ -typedef struct _Font { - /* Font width in pixels. */ - uint8_t width; - /* Font height in pixels. */ - uint8_t height; -} Font; - -/*---------------------------------------------------------------------------- - * Variables - *----------------------------------------------------------------------------*/ - -/** Global variable describing the font being instancied. */ -extern const Font gFont; - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void LCDD_DrawChar( - uint32_t x, - uint32_t y, - uint8_t c, - uint32_t color); - -#endif /* #ifndef FONT_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/font10x14.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/font10x14.h deleted file mode 100644 index 2ce2589ea..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/font10x14.h +++ /dev/null @@ -1,236 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - - /** - * \file - * - * Font 10x14 table definition. - * - */ - -#ifndef LCD_FONT_10x14_H -#define LCD_FONT_10x14_H - -/** Char set of font 10x14 */ -const uint8_t pCharset10x14[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xCC, - 0xFF, 0xCC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00, - 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x0C, 0xC0, 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0, - 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0, - 0x0C, 0x60, 0x1E, 0x70, 0x3F, 0x30, 0x33, 0x30, 0xFF, 0xFC, - 0xFF, 0xFC, 0x33, 0x30, 0x33, 0xF0, 0x39, 0xE0, 0x18, 0xC0, - 0x60, 0x00, 0xF0, 0x0C, 0xF0, 0x3C, 0x60, 0xF0, 0x03, 0xC0, - 0x0F, 0x00, 0x3C, 0x18, 0xF0, 0x3C, 0xC0, 0x3C, 0x00, 0x18, - 0x3C, 0xF0, 0x7F, 0xF8, 0xC3, 0x1C, 0xC7, 0x8C, 0xCF, 0xCC, - 0xDC, 0xEC, 0x78, 0x78, 0x30, 0x30, 0x00, 0xFC, 0x00, 0xCC, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0xEC, 0x00, - 0xF8, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x0F, 0xC0, 0x3F, 0xF0, 0x78, 0x78, - 0x60, 0x18, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0x60, 0x18, - 0x78, 0x78, 0x3F, 0xF0, 0x0F, 0xC0, 0x00, 0x00, 0x00, 0x00, - 0x0C, 0x60, 0x0E, 0xE0, 0x07, 0xC0, 0x03, 0x80, 0x3F, 0xF8, - 0x3F, 0xF8, 0x03, 0x80, 0x07, 0xC0, 0x0E, 0xE0, 0x0C, 0x60, - 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x3F, 0xF0, - 0x3F, 0xF0, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, - 0x00, 0x44, 0x00, 0xEC, 0x00, 0xF8, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, - 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, - 0x00, 0x18, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x18, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x0C, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0, - 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x00, 0xC0, 0x00, 0x00, 0x00, - 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0xFC, 0xC1, 0xCC, 0xC3, 0x8C, - 0xC7, 0x0C, 0xCE, 0x0C, 0xFC, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0, - 0x00, 0x00, 0x00, 0x00, 0x30, 0x0C, 0x70, 0x0C, 0xFF, 0xFC, - 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, - 0x30, 0x0C, 0x70, 0x1C, 0xE0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC, - 0xC1, 0xCC, 0xC3, 0x8C, 0xE7, 0x0C, 0x7E, 0x0C, 0x3C, 0x0C, - 0x30, 0x30, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, - 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x7F, 0xF8, 0x3C, 0xF0, - 0x03, 0xC0, 0x07, 0xC0, 0x0E, 0xC0, 0x1C, 0xC0, 0x38, 0xC0, - 0x70, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xC0, 0x00, 0xC0, - 0xFC, 0x30, 0xFC, 0x38, 0xCC, 0x1C, 0xCC, 0x0C, 0xCC, 0x0C, - 0xCC, 0x0C, 0xCC, 0x0C, 0xCE, 0x1C, 0xC7, 0xF8, 0xC3, 0xF0, - 0x3F, 0xF0, 0x7F, 0xF8, 0xE3, 0x1C, 0xC3, 0x0C, 0xC3, 0x0C, - 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x9C, 0x71, 0xF8, 0x30, 0xF0, - 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC3, 0xFC, - 0xC7, 0xFC, 0xCE, 0x00, 0xDC, 0x00, 0xF8, 0x00, 0xF0, 0x00, - 0x3C, 0xF0, 0x7F, 0xF8, 0xE7, 0x9C, 0xC3, 0x0C, 0xC3, 0x0C, - 0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0, - 0x3C, 0x00, 0x7E, 0x00, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x1C, - 0xC3, 0x38, 0xC3, 0x70, 0xE7, 0xE0, 0x7F, 0xC0, 0x3F, 0x80, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x60, 0x3C, 0xF0, - 0x3C, 0xF0, 0x18, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x44, 0x3C, 0xEC, - 0x3C, 0xF8, 0x18, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0, - 0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0x00, 0x00, - 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, - 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, - 0x00, 0x00, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x38, 0x70, - 0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00, - 0x30, 0x00, 0x70, 0x00, 0xE0, 0x00, 0xC0, 0x00, 0xC1, 0xEC, - 0xC3, 0xEC, 0xC3, 0x00, 0xE6, 0x00, 0x7E, 0x00, 0x3C, 0x00, - 0x30, 0xF0, 0x71, 0xF8, 0xE3, 0x9C, 0xC3, 0x0C, 0xC3, 0xFC, - 0xC3, 0xFC, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0, - 0x3F, 0xFC, 0x7F, 0xFC, 0xE0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, - 0xC0, 0xC0, 0xC0, 0xC0, 0xE0, 0xC0, 0x7F, 0xFC, 0x3F, 0xFC, - 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, - 0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0, - 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, - 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x30, 0x30, - 0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, - 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0, - 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, - 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, - 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00, - 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00, 0xC0, 0x00, 0xC0, 0x00, - 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, - 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x73, 0xF8, 0x33, 0xF0, - 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, - 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, - 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC, - 0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x30, 0x00, 0x38, 0xC0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, - 0xC0, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0, 0xC0, 0x00, 0xC0, 0x00, - 0xFF, 0xFC, 0xFF, 0xFC, 0x07, 0x80, 0x07, 0x80, 0x0F, 0xC0, - 0x1C, 0xE0, 0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, - 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, - 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, - 0xFF, 0xFC, 0xFF, 0xFC, 0x70, 0x00, 0x38, 0x00, 0x1F, 0x00, - 0x1F, 0x00, 0x38, 0x00, 0x70, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, - 0xFF, 0xFC, 0xFF, 0xFC, 0x1C, 0x00, 0x0E, 0x00, 0x07, 0x00, - 0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0xFF, 0xFC, 0xFF, 0xFC, - 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, - 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0, - 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00, - 0xC3, 0x00, 0xC3, 0x00, 0xE7, 0x00, 0x7E, 0x00, 0x3C, 0x00, - 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0xCC, - 0xC0, 0xEC, 0xC0, 0x7C, 0xE0, 0x38, 0x7F, 0xFC, 0x3F, 0xEC, - 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x80, 0xC3, 0x80, - 0xC3, 0xC0, 0xC3, 0xC0, 0xE7, 0x70, 0x7E, 0x3C, 0x3C, 0x1C, - 0x3C, 0x18, 0x7E, 0x1C, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, - 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x9C, 0xE1, 0xF8, 0x60, 0xF0, - 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xFF, 0xFC, - 0xFF, 0xFC, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, - 0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C, - 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0, - 0xFF, 0xC0, 0xFF, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, - 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0xFF, 0xE0, 0xFF, 0xC0, - 0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x3C, 0x00, 0xF8, - 0x00, 0xF8, 0x00, 0x3C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0, - 0xF0, 0x3C, 0xF8, 0x7C, 0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80, - 0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0, 0xF8, 0x7C, 0xF0, 0x3C, - 0xFC, 0x00, 0xFE, 0x00, 0x07, 0x00, 0x03, 0x80, 0x01, 0xFC, - 0x01, 0xFC, 0x03, 0x80, 0x07, 0x00, 0xFE, 0x00, 0xFC, 0x00, - 0xC0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC, 0xC1, 0xCC, 0xC3, 0x8C, - 0xC7, 0x0C, 0xCE, 0x0C, 0xDC, 0x0C, 0xF8, 0x0C, 0xF0, 0x0C, - 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C, - 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x30, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x03, 0x00, - 0x03, 0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x30, - 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, - 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x0C, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x00, 0xE0, 0x00, - 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C, 0x00, - 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, - 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, - 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00, - 0x38, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x30, 0x06, 0x78, 0x0E, 0xFC, 0x0C, 0xCC, 0x0C, 0xCC, - 0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xCC, 0x07, 0xFC, 0x03, 0xF8, - 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C, - 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x9C, 0x01, 0xF8, 0x00, 0xF0, - 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C, - 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0x30, - 0x00, 0xF0, 0x01, 0xF8, 0x03, 0x9C, 0x03, 0x0C, 0x03, 0x0C, - 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C, 0xFF, 0xFC, 0xFF, 0xFC, - 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0xDC, 0x0C, 0xCC, 0x0C, 0xCC, - 0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xDC, 0x07, 0xD8, 0x03, 0x90, - 0x00, 0x00, 0x03, 0x00, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x00, - 0xE3, 0x00, 0x70, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC, - 0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xDC, 0x0F, 0xF8, 0x07, 0xF0, - 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, - 0x03, 0x00, 0x03, 0x80, 0x01, 0xFC, 0x00, 0xFC, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0xFC, - 0x1B, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x30, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C, - 0x00, 0x0C, 0x00, 0x1C, 0xCF, 0xF8, 0xCF, 0xF0, 0x00, 0x00, - 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xE0, 0x01, 0xE0, - 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC, - 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, - 0x0F, 0xFC, 0x0F, 0xFC, 0x0E, 0x00, 0x07, 0x00, 0x03, 0xC0, - 0x03, 0xC0, 0x07, 0x00, 0x0E, 0x00, 0x0F, 0xFC, 0x0F, 0xFC, - 0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x00, 0x07, 0x00, 0x0E, 0x00, - 0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0xFC, 0x03, 0xFC, - 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C, - 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0xF8, 0x03, 0xF0, - 0x0F, 0xFC, 0x0F, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, - 0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00, - 0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, - 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xFC, 0x0F, 0xFC, - 0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, - 0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x03, 0x00, - 0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC, - 0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xFC, 0x0E, 0x78, 0x06, 0x30, - 0x00, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0xFF, 0xF0, 0xFF, 0xF8, - 0x0C, 0x1C, 0x0C, 0x1C, 0x0C, 0x38, 0x0C, 0x30, 0x00, 0x00, - 0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C, - 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0, - 0x0F, 0xC0, 0x0F, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, - 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x0F, 0xE0, 0x0F, 0xC0, - 0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0xF8, - 0x00, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0, - 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0xF0, 0x01, 0xE0, - 0x01, 0xE0, 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C, - 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x0C, 0x03, 0x9C, 0x01, 0xF8, - 0x01, 0xF0, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, 0x0C, 0x00, - 0x0C, 0x0C, 0x0C, 0x1C, 0x0C, 0x3C, 0x0C, 0x7C, 0x0C, 0xEC, - 0x0D, 0xCC, 0x0F, 0x8C, 0x0F, 0x0C, 0x0E, 0x0C, 0x0C, 0x0C, - 0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x3F, 0xF0, 0x7C, 0xF8, - 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, - 0x03, 0x0C, 0x03, 0x0C, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x0C, - 0xC3, 0x0C, 0xC0, 0x0C, 0xE0, 0x0C, 0x70, 0x0C, 0x30, 0x0C, - 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, - 0x7C, 0xF8, 0x3F, 0xF0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00, - 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, - 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, - 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, - 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC -}; - -#endif /* #ifdef _LCD_FONT_10x14_h */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/lcdd.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/lcdd.c deleted file mode 100644 index 1d7b158a8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/lcdd.c +++ /dev/null @@ -1,149 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of LCD driver, Include LCD initialization, - * LCD on/off and LCD backlight control. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include "lcdd.h" -#include -#include -#include -#include - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Initializes the LCD controller. - * Configure SMC to access LCD controller at 64MHz MCK. - */ -void LCDD_Initialize(void) -{ - const Pin pPins[] = {BOARD_LCD_PINS}; - Smc *pSmc = SMC; - - /* Enable pins */ - PIO_Configure(pPins, PIO_LISTSIZE(pPins)); - - /* Enable peripheral clock */ - PMC_EnablePeripheral(ID_SMC); - - /* EBI SMC Configuration */ - pSmc->SMC_CS_NUMBER[1].SMC_SETUP = 0 - | ((2 << 0) & SMC_SETUP1_NWE_SETUP) - | ((2 << 8) & SMC_SETUP1_NCS_WR_SETUP) - | ((2 << 16) & SMC_SETUP1_NRD_SETUP) - | ((2 << 24) & SMC_SETUP1_NCS_RD_SETUP) - ; - - pSmc->SMC_CS_NUMBER[1].SMC_PULSE = 0 - | ((4 << 0) & SMC_PULSE1_NWE_PULSE) - | ((4 << 8) & SMC_PULSE1_NCS_WR_PULSE) - | ((10 << 16) & SMC_PULSE1_NRD_PULSE) - | ((10 << 24) & SMC_PULSE1_NCS_RD_PULSE) - ; - - pSmc->SMC_CS_NUMBER[1].SMC_CYCLE = 0 - | ((10 << 0) & SMC_CYCLE1_NWE_CYCLE) - | ((22 << 16) & SMC_CYCLE1_NRD_CYCLE) - ; - - pSmc->SMC_CS_NUMBER[1].SMC_MODE = 0 - | (SMC_MODE1_READ_MODE) - | (SMC_MODE1_WRITE_MODE) - | (0) /* Set 8 bit width. TODO: replace with definition in device header file */ - ; - - /* Initialize LCD controller */ - LCD_Initialize(); - - /* Set LCD backlight */ - LCDD_SetBacklight(2); -} - -/** - * \brief Turn on the LCD. - */ -void LCDD_On(void) -{ - LCD_On(); -} - -/** - * \brief Turn off the LCD. - */ -void LCDD_Off(void) -{ - LCD_Off(); -} - -/** - * \brief Set the backlight of the LCD. - * - * \param level Backlight brightness level [1..16], 1 means maximum brightness. - */ -void LCDD_SetBacklight (uint32_t level) -{ - uint32_t i; - const Pin pPins[] = {BOARD_BACKLIGHT_PIN}; - - /* Ensure valid level */ - level = (level < 1) ? 1 : level; - level = (level > 16) ? 16 : level; - - /* Enable pins */ - PIO_Configure(pPins, PIO_LISTSIZE(pPins)); - - /* Switch off backlight */ - PIO_Clear(pPins); - i = 600 * (BOARD_MCK / 1000000); /* wait for at least 500us */ - while(i--); - - /* Set new backlight level */ - for (i = 0; i < level; i++) { - PIO_Clear(pPins); - PIO_Clear(pPins); - PIO_Clear(pPins); - - PIO_Set(pPins); - PIO_Set(pPins); - PIO_Set(pPins); - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/lcdd.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/lcdd.h deleted file mode 100644 index 8ba19f05b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/lcd/lcdd.h +++ /dev/null @@ -1,52 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for LCD driver. - * - */ - -#ifndef LCDD_H -#define LCDD_H - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void LCDD_Initialize(void); - -extern void LCDD_On(void); - -extern void LCDD_Off(void); - -extern void LCDD_SetBacklight (uint32_t step); - -#endif /* #ifndef LCDD_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio.c deleted file mode 100644 index db13b2b40..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio.c +++ /dev/null @@ -1,464 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/// \file - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "pio.h" -#include -#include - -//------------------------------------------------------------------------------ -// Local Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Configures one or more pin(s) of a PIO controller as being controlled by -/// peripheral A. Optionally, the corresponding internal pull-up(s) can be -/// enabled. -/// \param pio Pointer to a PIO controller. -/// \param mask Bitmask of one or more pin(s) to configure. -/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be -/// configured. -//------------------------------------------------------------------------------ -static void PIO_SetPeripheralA( - Pio *pio, - unsigned int mask, - unsigned char enablePullUp) -{ - unsigned int abcdsr; - // Disable interrupts on the pin(s) - pio->PIO_IDR = mask; - - // Enable the pull-up(s) if necessary - if (enablePullUp) { - pio->PIO_PUER = mask; - } - else { - - pio->PIO_PUDR = mask; - } - - abcdsr = pio->PIO_ABCDSR[0]; - pio->PIO_ABCDSR[0] &= (~mask & abcdsr); - abcdsr = pio->PIO_ABCDSR[1]; - pio->PIO_ABCDSR[1] &= (~mask & abcdsr); - pio->PIO_PDR = mask; -} - -//------------------------------------------------------------------------------ -/// Configures one or more pin(s) of a PIO controller as being controlled by -/// peripheral B. Optionally, the corresponding internal pull-up(s) can be -/// enabled. -/// \param pio Pointer to a PIO controller. -/// \param mask Bitmask of one or more pin(s) to configure. -/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be -/// configured. -//------------------------------------------------------------------------------ -static void PIO_SetPeripheralB( - Pio *pio, - unsigned int mask, - unsigned char enablePullUp) -{ - unsigned int abcdsr; - // Disable interrupts on the pin(s) - pio->PIO_IDR = mask; - - // Enable the pull-up(s) if necessary - if (enablePullUp) { - - pio->PIO_PUER = mask; - } - else { - - pio->PIO_PUDR = mask; - } - - abcdsr = pio->PIO_ABCDSR[0]; - pio->PIO_ABCDSR[0] = (mask | abcdsr); - abcdsr = pio->PIO_ABCDSR[1]; - pio->PIO_ABCDSR[1] &= (~mask & abcdsr); - - pio->PIO_PDR = mask; -} - -//------------------------------------------------------------------------------ -/// Configures one or more pin(s) of a PIO controller as being controlled by -/// peripheral C. Optionally, the corresponding internal pull-up(s) can be -/// enabled. -/// \param pio Pointer to a PIO controller. -/// \param mask Bitmask of one or more pin(s) to configure. -/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be -/// configured. -//------------------------------------------------------------------------------ -static void PIO_SetPeripheralC( - Pio *pio, - unsigned int mask, - unsigned char enablePullUp) -{ - unsigned int abcdsr; - // Disable interrupts on the pin(s) - pio->PIO_IDR = mask; - - // Enable the pull-up(s) if necessary - if (enablePullUp) { - - pio->PIO_PUER = mask; - } - else { - - pio->PIO_PUDR = mask; - } - - abcdsr = pio->PIO_ABCDSR[0]; - pio->PIO_ABCDSR[0] &= (~mask & abcdsr); - abcdsr = pio->PIO_ABCDSR[1]; - pio->PIO_ABCDSR[1] = (mask | abcdsr); - - pio->PIO_PDR = mask; -} - -//------------------------------------------------------------------------------ -/// Configures one or more pin(s) of a PIO controller as being controlled by -/// peripheral D. Optionally, the corresponding internal pull-up(s) can be -/// enabled. -/// \param pio Pointer to a PIO controller. -/// \param mask Bitmask of one or more pin(s) to configure. -/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be -/// configured. -//------------------------------------------------------------------------------ -static void PIO_SetPeripheralD( - Pio *pio, - unsigned int mask, - unsigned char enablePullUp) -{ - unsigned int abcdsr; - // Disable interrupts on the pin(s) - pio->PIO_IDR = mask; - - // Enable the pull-up(s) if necessary - if (enablePullUp) { - - pio->PIO_PUER = mask; - } - else { - - pio->PIO_PUDR = mask; - } - - abcdsr = pio->PIO_ABCDSR[0]; - pio->PIO_ABCDSR[0] = (mask | abcdsr); - abcdsr = pio->PIO_ABCDSR[1]; - pio->PIO_ABCDSR[1] = (mask | abcdsr); - - pio->PIO_PDR = mask; -} - -//------------------------------------------------------------------------------ -/// Configures one or more pin(s) or a PIO controller as inputs. Optionally, -/// the corresponding internal pull-up(s) and glitch filter(s) can be -/// enabled. -/// \param pio Pointer to a PIO controller. -/// \param mask Bitmask indicating which pin(s) to configure as input(s). -/// \param enablePullUp Indicates if the internal pull-up(s) must be enabled. -/// \param enableFilter Indicates if the glitch filter(s) must be enabled. -//------------------------------------------------------------------------------ -static void PIO_SetInput( - Pio *pio, - unsigned int mask, - unsigned char attribute) -{ - // Disable interrupts - pio->PIO_IDR = mask; - - // Enable pull-up(s) if necessary - if (attribute & PIO_PULLUP) - pio->PIO_PUER = mask; - else - pio->PIO_PUDR = mask; - - // Enable de-glitch(s) if necessary - if (attribute & PIO_DEGLITCH) - pio->PIO_IFER = mask; - else - pio->PIO_IFDR = mask; - - // Enable de-bounce if necessary - if (attribute & PIO_DEBOUNCE) { - pio->PIO_DIFSR = mask; - } - - // Configure pin as input - pio->PIO_ODR = mask; - pio->PIO_PER = mask; -} - -//------------------------------------------------------------------------------ -/// Configures one or more pin(s) of a PIO controller as outputs, with the -/// given default value. Optionally, the multi-drive feature can be enabled -/// on the pin(s). -/// \param pio Pointer to a PIO controller. -/// \param mask Bitmask indicating which pin(s) to configure. -/// \param defaultValue Default level on the pin(s). -/// \param enableMultiDrive Indicates if the pin(s) shall be configured as -/// open-drain. -/// \param enablePullUp Indicates if the pin shall have its pull-up activated. -//------------------------------------------------------------------------------ -static void PIO_SetOutput( - Pio *pio, - unsigned int mask, - unsigned char defaultValue, - unsigned char enableMultiDrive, - unsigned char enablePullUp) -{ - // Disable interrupts - pio->PIO_IDR = mask; - - // Enable pull-up(s) if necessary - if (enablePullUp) { - - pio->PIO_PUER = mask; - } - else { - - pio->PIO_PUDR = mask; - } - - // Enable multi-drive if necessary - if (enableMultiDrive) { - - pio->PIO_MDER = mask; - } - else { - - pio->PIO_MDDR = mask; - } - - // Set default value - if (defaultValue) { - - pio->PIO_SODR = mask; - } - else { - - pio->PIO_CODR = mask; - } - - // Configure pin(s) as output(s) - pio->PIO_OER = mask; - pio->PIO_PER = mask; -} - -//------------------------------------------------------------------------------ -/// Configures interrupt mode for input Pins -/// \param pio Pointer to a PIO controller. -/// \param mask Bitmask indicating which pin(s) to configure. -/// \param additionnalItMode Enable Pio Additionnal It Mode. -/// \param edgeMode Enable the edge mode. -/// \param risingEdgeOrHighLevel Enable IT on rising edge or high level. -//------------------------------------------------------------------------------ -static void PIO_SetInterrupt( - Pio *pio, - unsigned int mask, - unsigned char additionnalItMode, - unsigned char edgeMode, - unsigned char risingEdgeOrHighLevel) -{ - /* Configure the Interrupt mode in the PIO controller */ - if (additionnalItMode) { - /* enable additional interrupt mode */ - pio->PIO_AIMER = mask; - - /* if bit field of selected pin is 1, set as Rising Edge/High level detection event */ - if (risingEdgeOrHighLevel) - pio->PIO_REHLSR = mask; - else - pio->PIO_FELLSR = mask; - - /* if bit field of selected pin is 1, set as edge detection source */ - if (edgeMode) - pio->PIO_ESR = mask; - else - pio->PIO_LSR = mask; - } else { - /* disable additional interrupt mode */ - pio->PIO_AIMDR = mask; - } -} - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Configures a list of Pin instances, each of which can either hold a single -/// pin or a group of pins, depending on the mask value; all pins are configured -/// by this function. The size of the array must also be provided and is easily -/// computed using PIO_LISTSIZE whenever its length is not known in advance. -/// \param list Pointer to a list of Pin instances. -/// \param size Size of the Pin list (calculated using PIO_LISTSIZE). -/// \return 1 if the pins have been configured properly; otherwise 0. -//------------------------------------------------------------------------------ -unsigned char PIO_Configure(const Pin *list, unsigned int size) -{ - // Configure pins - while (size > 0) { - - switch (list->type) { - - case PIO_PERIPH_A: - PIO_SetPeripheralA(list->pio, - list->mask, - (list->attribute & PIO_PULLUP) ? 1 : 0); - break; - - case PIO_PERIPH_B: - PIO_SetPeripheralB(list->pio, - list->mask, - (list->attribute & PIO_PULLUP) ? 1 : 0); - break; - - case PIO_PERIPH_C: - PIO_SetPeripheralC(list->pio, - list->mask, - (list->attribute & PIO_PULLUP) ? 1 : 0); - break; - - case PIO_PERIPH_D: - PIO_SetPeripheralD(list->pio, - list->mask, - (list->attribute & PIO_PULLUP) ? 1 : 0); - break; - case PIO_INPUT: - PMC_EnablePeripheral(list->id); - PIO_SetInput(list->pio, - list->mask, - list->attribute); - PIO_SetInterrupt(list->pio, - list->mask, - (list->attribute & PIO_IT_AIME) ? 1 : 0, - (list->attribute & PIO_IT_EDGE) ? 1 : 0, - (list->attribute & PIO_IT_RE_OR_HL) ? 1 : 0); - break; - - case PIO_OUTPUT_0: - case PIO_OUTPUT_1: - PIO_SetOutput(list->pio, - list->mask, - (list->type == PIO_OUTPUT_1), - (list->attribute & PIO_OPENDRAIN) ? 1 : 0, - (list->attribute & PIO_PULLUP) ? 1 : 0); - break; - - default: return 0; - } - - list++; - size--; - } - - return 1; -} - -//------------------------------------------------------------------------------ -/// Sets a high output level on all the PIOs defined in the given Pin instance. -/// This has no immediate effects on PIOs that are not output, but the PIO -/// controller will memorize the value they are changed to outputs. -/// \param pin Pointer to a Pin instance describing one or more pins. -//------------------------------------------------------------------------------ -void PIO_Set(const Pin *pin) -{ - pin->pio->PIO_SODR = pin->mask; -} - -//------------------------------------------------------------------------------ -/// Sets a low output level on all the PIOs defined in the given Pin instance. -/// This has no immediate effects on PIOs that are not output, but the PIO -/// controller will memorize the value they are changed to outputs. -/// \param pin Pointer to a Pin instance describing one or more pins. -//------------------------------------------------------------------------------ -void PIO_Clear(const Pin *pin) -{ - pin->pio->PIO_CODR = pin->mask; -} - -//------------------------------------------------------------------------------ -/// Returns 1 if one or more PIO of the given Pin instance currently have a high -/// level; otherwise returns 0. This method returns the actual value that is -/// being read on the pin. To return the supposed output value of a pin, use -/// PIO_GetOutputDataStatus() instead. -/// \param pin Pointer to a Pin instance describing one or more pins. -/// \return 1 if the Pin instance contains at least one PIO that currently has -/// a high level; otherwise 0. -//------------------------------------------------------------------------------ -unsigned char PIO_Get(const Pin *pin) -{ - unsigned int reg; - if ((pin->type == PIO_OUTPUT_0) || (pin->type == PIO_OUTPUT_1)) { - - reg = pin->pio->PIO_ODSR; - } - else { - - reg = pin->pio->PIO_PDSR; - } - - if ((reg & pin->mask) == 0) { - - return 0; - } - else { - - return 1; - } -} - - -//------------------------------------------------------------------------------ -/// Returns 1 if one or more PIO of the given Pin are configured to output a -/// high level (even if they are not output). -/// To get the actual value of the pin, use PIO_Get() instead. -/// \param pin Pointer to a Pin instance describing one or more pins. -/// \return 1 if the Pin instance contains at least one PIO that is configured -/// to output a high level; otherwise 0. -//------------------------------------------------------------------------------ -unsigned char PIO_GetOutputDataStatus(const Pin *pin) -{ - if ((pin->pio->PIO_ODSR & pin->mask) == 0) { - - return 0; - } - else { - - return 1; - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio.h deleted file mode 100644 index 52fd593bd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio.h +++ /dev/null @@ -1,215 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \file -/// -/// \par Purpose -/// -/// This file provides a basic API for PIO configuration and usage of -/// user-controlled pins. Please refer to the board.h file for a list of -/// available pin definitions. -/// -/// \par Usage -/// -/// -# Define a constant pin description array such as the following one, using -/// the existing definitions provided by the board.h file if possible: -/// \code -/// const Pin pPins[] = {PIN_USART0_TXD, PIN_USART0_RXD}; -/// \endcode -/// Alternatively, it is possible to add new pins by provided the full Pin -/// structure: -/// \code -/// // Pin instance to configure PA10 & PA11 as inputs with the internal -/// // pull-up enabled. -/// const Pin pPins = { -/// (1 << 10) | (1 << 11), -/// REG_PIOA, -/// ID_PIOA, -/// PIO_INPUT, -/// PIO_PULLUP -/// }; -/// \endcode -/// -# Configure a pin array by calling PIO_Configure() with a pointer to the -/// array and its size (which is computed using the PIO_LISTSIZE macro). -/// -# Change and get the value of a user-controlled pin using the PIO_Set, -/// PIO_Clear and PIO_Get methods. -/// -# Get the level being currently output by a user-controlled pin configured -/// as an output using PIO_GetOutputDataStatus(). -//------------------------------------------------------------------------------ - -#ifndef PIO_H -#define PIO_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Global Definitions -//------------------------------------------------------------------------------ - -/// The pin is controlled by the associated signal of peripheral A. -#define PIO_PERIPH_A 0 -/// The pin is controlled by the associated signal of peripheral B. -#define PIO_PERIPH_B 1 -/// The pin is controlled by the associated signal of peripheral C. -#define PIO_PERIPH_C 2 -/// The pin is controlled by the associated signal of peripheral D. -#define PIO_PERIPH_D 3 -/// The pin is an input. -#define PIO_INPUT 4 -/// The pin is an output and has a default level of 0. -#define PIO_OUTPUT_0 5 -/// The pin is an output and has a default level of 1. -#define PIO_OUTPUT_1 6 - -/// Default pin configuration (no attribute). -#define PIO_DEFAULT (0 << 0) -/// The internal pin pull-up is active. -#define PIO_PULLUP (1 << 0) -/// The internal glitch filter is active. -#define PIO_DEGLITCH (1 << 1) -/// The pin is open-drain. -#define PIO_OPENDRAIN (1 << 2) - -/// The internal debouncing filter is active. -#define PIO_DEBOUNCE (1 << 3) - -/// Enable additional interrupt modes. -#define PIO_IT_AIME (1 << 4) - -/// Interrupt High Level/Rising Edge detection is active. -#define PIO_IT_RE_OR_HL (1 << 5) -/// Interrupt Edge detection is active. -#define PIO_IT_EDGE (1 << 6) - -/// Low level interrupt is active -#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME) -/// High level interrupt is active -#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME) -/// Falling edge interrupt is active -#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME) -/// Rising edge interrupt is active -#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME) - -//------------------------------------------------------------------------------ -// Global Macros -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Calculates the size of an array of Pin instances. The array must be defined -/// locally (i.e. not a pointer), otherwise the computation will not be correct. -/// \param pPins Local array of Pin instances. -/// \return Number of elements in array. -//------------------------------------------------------------------------------ -#define PIO_LISTSIZE(pPins) (sizeof(pPins) / sizeof(Pin)) - -//------------------------------------------------------------------------------ -// Global Types -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// Describes the type and attribute of one PIO pin or a group of similar pins. -/// The #type# field can have the following values: -/// - PIO_PERIPH_A -/// - PIO_PERIPH_B -/// - PIO_OUTPUT_0 -/// - PIO_OUTPUT_1 -/// - PIO_INPUT -/// -/// The #attribute# field is a bitmask that can either be set to PIO_DEFAULt, -/// or combine (using bitwise OR '|') any number of the following constants: -/// - PIO_PULLUP -/// - PIO_DEGLITCH -/// - PIO_DEBOUNCE -/// - PIO_OPENDRAIN -/// - PIO_IT_LOW_LEVEL -/// - PIO_IT_HIGH_LEVEL -/// - PIO_IT_FALL_EDGE -/// - PIO_IT_RISE_EDGE -//------------------------------------------------------------------------------ -typedef struct { - - /// Bitmask indicating which pin(s) to configure. - unsigned int mask; - /// Pointer to the PIO controller which has the pin(s). - Pio *pio; - /// Peripheral ID of the PIO controller which has the pin(s). - unsigned char id; - /// Pin type. - unsigned char type; - /// Pin attribute. - unsigned char attribute; -} Pin; - -//------------------------------------------------------------------------------ -// Global Access Macros -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// Configures Glitch or Debouncing filter for input -/// \param pin Pointer to a Pin instance describing one or more pins. -/// \param cuttoff Cutt off frequency for debounce filter -//------------------------------------------------------------------------------ -static inline void PIO_SetDebounceFilter( - const Pin *pin, - unsigned int cuttoff) - { - Pio *pio = pin->pio; - - pio->PIO_DIFSR = pin->mask;//set Debouncing, 0 bit field no effect - pio->PIO_SCDR = ((32678/(2*(cuttoff))) - 1) & 0x3FFF;//the lowest 14 bits work -} - - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -extern unsigned char PIO_Configure(const Pin *list, unsigned int size); - -extern void PIO_Set(const Pin *pin); - -extern void PIO_Clear(const Pin *pin); - -extern unsigned char PIO_Get(const Pin *pin); - -//extern unsigned int PIO_GetISR(const Pin *pin); - -extern unsigned char PIO_GetOutputDataStatus(const Pin *pin); - -extern void PIO_EnableDebounce(const Pin *pin, unsigned int clkDiv); - -#endif //#ifndef PIO_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio_it.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio_it.c deleted file mode 100644 index e04a07c5b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio_it.c +++ /dev/null @@ -1,411 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/// \file - -/// Disable traces for this file -#undef TRACE_LEVEL -#define TRACE_LEVEL 0 - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "pio_it.h" -#include "pio.h" -#include -#include -#include -#include -#include - -//------------------------------------------------------------------------------ -// Local definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Local types -//------------------------------------------------------------------------------ -/* Define WEAK attribute */ -#if defined ( __CC_ARM ) - #define WEAK __attribute__ ((weak)) -#elif defined ( __ICCARM__ ) - #define WEAK __weak -#elif defined ( __GNUC__ ) - #define WEAK __attribute__ ((weak)) -#endif - - -//------------------------------------------------------------------------------ -// Local variables -//------------------------------------------------------------------------------ -typedef void (*PioHandler) (unsigned char id); - -/* Default PIO handlers defined as weak functions which have to be redefined by - * the application */ -WEAK void PIOA_Irq0Handler(unsigned char id) {} -WEAK void PIOA_Irq1Handler(unsigned char id) {} -WEAK void PIOA_Irq2Handler(unsigned char id) {} -WEAK void PIOA_Irq3Handler(unsigned char id) {} -WEAK void PIOA_Irq4Handler(unsigned char id) {} -WEAK void PIOA_Irq5Handler(unsigned char id) {} -WEAK void PIOA_Irq6Handler(unsigned char id) {} -WEAK void PIOA_Irq7Handler(unsigned char id) {} -WEAK void PIOA_Irq8Handler(unsigned char id) {} -WEAK void PIOA_Irq9Handler(unsigned char id) {} -WEAK void PIOA_Irq10Handler(unsigned char id) {} -WEAK void PIOA_Irq11Handler(unsigned char id) {} -WEAK void PIOA_Irq12Handler(unsigned char id) {} -WEAK void PIOA_Irq13Handler(unsigned char id) {} -WEAK void PIOA_Irq14Handler(unsigned char id) {} -WEAK void PIOA_Irq15Handler(unsigned char id) {} -WEAK void PIOA_Irq16Handler(unsigned char id) {} -WEAK void PIOA_Irq17Handler(unsigned char id) {} -WEAK void PIOA_Irq18Handler(unsigned char id) {} -WEAK void PIOA_Irq19Handler(unsigned char id) {} -WEAK void PIOA_Irq20Handler(unsigned char id) {} -WEAK void PIOA_Irq21Handler(unsigned char id) {} -WEAK void PIOA_Irq22Handler(unsigned char id) {} -WEAK void PIOA_Irq23Handler(unsigned char id) {} -WEAK void PIOA_Irq24Handler(unsigned char id) {} -WEAK void PIOA_Irq25Handler(unsigned char id) {} -WEAK void PIOA_Irq26Handler(unsigned char id) {} -WEAK void PIOA_Irq27Handler(unsigned char id) {} -WEAK void PIOA_Irq28Handler(unsigned char id) {} -WEAK void PIOA_Irq29Handler(unsigned char id) {} -WEAK void PIOA_Irq30Handler(unsigned char id) {} -WEAK void PIOA_Irq31Handler(unsigned char id) {} - - -/** pioAHandlers records ISR routines for each PIO Id for PIO controller A */ -static const PioHandler pioAHandlers[32] = { - (PioHandler) PIOA_Irq0Handler, /**< PA0 IT Handler */ - (PioHandler) PIOA_Irq1Handler, /**< PA1 IT Handler */ - (PioHandler) PIOA_Irq2Handler, /**< PA2 IT Handler */ - (PioHandler) PIOA_Irq3Handler, /**< PA3 IT Handler */ - (PioHandler) PIOA_Irq4Handler, /**< PA4 IT Handler */ - (PioHandler) PIOA_Irq5Handler, /**< PA5 IT Handler */ - (PioHandler) PIOA_Irq6Handler, /**< PA6 IT Handler */ - (PioHandler) PIOA_Irq7Handler, /**< PA7 IT Handler */ - (PioHandler) PIOA_Irq8Handler, /**< PA8 IT Handler */ - (PioHandler) PIOA_Irq9Handler, /**< PA9 IT Handler */ - (PioHandler) PIOA_Irq10Handler, /**< PA10 IT Handler */ - (PioHandler) PIOA_Irq11Handler, /**< PA11 IT Handler */ - (PioHandler) PIOA_Irq12Handler, /**< PA12 IT Handler */ - (PioHandler) PIOA_Irq13Handler, /**< PA13 IT Handler */ - (PioHandler) PIOA_Irq14Handler, /**< PA14 IT Handler */ - (PioHandler) PIOA_Irq15Handler, /**< PA15 IT Handler */ - (PioHandler) PIOA_Irq16Handler, /**< PA16 IT Handler */ - (PioHandler) PIOA_Irq17Handler, /**< PA17 IT Handler */ - (PioHandler) PIOA_Irq18Handler, /**< PA18 IT Handler */ - (PioHandler) PIOA_Irq19Handler, /**< PA19 IT Handler */ - (PioHandler) PIOA_Irq20Handler, /**< PA20 IT Handler */ - (PioHandler) PIOA_Irq21Handler, /**< PA21 IT Handler */ - (PioHandler) PIOA_Irq22Handler, /**< PA22 IT Handler */ - (PioHandler) PIOA_Irq23Handler, /**< PA23 IT Handler */ - (PioHandler) PIOA_Irq24Handler, /**< PA24 IT Handler */ - (PioHandler) PIOA_Irq25Handler, /**< PA25 IT Handler */ - (PioHandler) PIOA_Irq26Handler, /**< PA26 IT Handler */ - (PioHandler) PIOA_Irq27Handler, /**< PA27 IT Handler */ - (PioHandler) PIOA_Irq28Handler, /**< PA28 IT Handler */ - (PioHandler) PIOA_Irq29Handler, /**< PA29 IT Handler */ - (PioHandler) PIOA_Irq30Handler, /**< PA30 IT Handler */ - (PioHandler) PIOA_Irq31Handler /**< PA31 IT Handler */ -}; - -/* Default PIO handlers defined as weak functions which have to be redefined by - * the application */ -WEAK void PIOB_Irq0Handler(unsigned char id) {} -WEAK void PIOB_Irq1Handler(unsigned char id) {} -WEAK void PIOB_Irq2Handler(unsigned char id) {} -WEAK void PIOB_Irq3Handler(unsigned char id) {} -WEAK void PIOB_Irq4Handler(unsigned char id) {} -WEAK void PIOB_Irq5Handler(unsigned char id) {} -WEAK void PIOB_Irq6Handler(unsigned char id) {} -WEAK void PIOB_Irq7Handler(unsigned char id) {} -WEAK void PIOB_Irq8Handler(unsigned char id) {} -WEAK void PIOB_Irq9Handler(unsigned char id) {} -WEAK void PIOB_Irq10Handler(unsigned char id) {} -WEAK void PIOB_Irq11Handler(unsigned char id) {} -WEAK void PIOB_Irq12Handler(unsigned char id) {} -WEAK void PIOB_Irq13Handler(unsigned char id) {} -WEAK void PIOB_Irq14Handler(unsigned char id) {} -WEAK void PIOB_Irq15Handler(unsigned char id) {} -WEAK void PIOB_Irq16Handler(unsigned char id) {} -WEAK void PIOB_Irq17Handler(unsigned char id) {} -WEAK void PIOB_Irq18Handler(unsigned char id) {} -WEAK void PIOB_Irq19Handler(unsigned char id) {} -WEAK void PIOB_Irq20Handler(unsigned char id) {} -WEAK void PIOB_Irq21Handler(unsigned char id) {} -WEAK void PIOB_Irq22Handler(unsigned char id) {} -WEAK void PIOB_Irq23Handler(unsigned char id) {} -WEAK void PIOB_Irq24Handler(unsigned char id) {} -WEAK void PIOB_Irq25Handler(unsigned char id) {} -WEAK void PIOB_Irq26Handler(unsigned char id) {} -WEAK void PIOB_Irq27Handler(unsigned char id) {} -WEAK void PIOB_Irq28Handler(unsigned char id) {} -WEAK void PIOB_Irq29Handler(unsigned char id) {} -WEAK void PIOB_Irq30Handler(unsigned char id) {} -WEAK void PIOB_Irq31Handler(unsigned char id) {} - - -/** PIOBHandlers records ISR routines for each PIO Id for PIO controller A */ -static const PioHandler pioBHandlers[32] = { - (PioHandler) PIOB_Irq0Handler, /**< PB0 IT Handler */ - (PioHandler) PIOB_Irq1Handler, /**< PB1 IT Handler */ - (PioHandler) PIOB_Irq2Handler, /**< PB2 IT Handler */ - (PioHandler) PIOB_Irq3Handler, /**< PB3 IT Handler */ - (PioHandler) PIOB_Irq4Handler, /**< PB4 IT Handler */ - (PioHandler) PIOB_Irq5Handler, /**< PB5 IT Handler */ - (PioHandler) PIOB_Irq6Handler, /**< PB6 IT Handler */ - (PioHandler) PIOB_Irq7Handler, /**< PB7 IT Handler */ - (PioHandler) PIOB_Irq8Handler, /**< PB8 IT Handler */ - (PioHandler) PIOB_Irq9Handler, /**< PB9 IT Handler */ - (PioHandler) PIOB_Irq10Handler, /**< PB10 IT Handler */ - (PioHandler) PIOB_Irq11Handler, /**< PB11 IT Handler */ - (PioHandler) PIOB_Irq12Handler, /**< PB12 IT Handler */ - (PioHandler) PIOB_Irq13Handler, /**< PB13 IT Handler */ - (PioHandler) PIOB_Irq14Handler, /**< PB14 IT Handler */ - (PioHandler) PIOB_Irq15Handler, /**< PB15 IT Handler */ - (PioHandler) PIOB_Irq16Handler, /**< PB16 IT Handler */ - (PioHandler) PIOB_Irq17Handler, /**< PB17 IT Handler */ - (PioHandler) PIOB_Irq18Handler, /**< PB18 IT Handler */ - (PioHandler) PIOB_Irq19Handler, /**< PB19 IT Handler */ - (PioHandler) PIOB_Irq20Handler, /**< PB20 IT Handler */ - (PioHandler) PIOB_Irq21Handler, /**< PB21 IT Handler */ - (PioHandler) PIOB_Irq22Handler, /**< PB22 IT Handler */ - (PioHandler) PIOB_Irq23Handler, /**< PB23 IT Handler */ - (PioHandler) PIOB_Irq24Handler, /**< PB24 IT Handler */ - (PioHandler) PIOB_Irq25Handler, /**< PB25 IT Handler */ - (PioHandler) PIOB_Irq26Handler, /**< PB26 IT Handler */ - (PioHandler) PIOB_Irq27Handler, /**< PB27 IT Handler */ - (PioHandler) PIOB_Irq28Handler, /**< PB28 IT Handler */ - (PioHandler) PIOB_Irq29Handler, /**< PB29 IT Handler */ - (PioHandler) PIOB_Irq30Handler, /**< PB30 IT Handler */ - (PioHandler) PIOB_Irq31Handler /**< PB31 IT Handler */ -}; - -/* Default PIO handlers defined as weak functions which have to be redefined by - * the application */ -WEAK void PIOC_Irq0Handler(unsigned char id) {} -WEAK void PIOC_Irq1Handler(unsigned char id) {} -WEAK void PIOC_Irq2Handler(unsigned char id) {} -WEAK void PIOC_Irq3Handler(unsigned char id) {} -WEAK void PIOC_Irq4Handler(unsigned char id) {} -WEAK void PIOC_Irq5Handler(unsigned char id) {} -WEAK void PIOC_Irq6Handler(unsigned char id) {} -WEAK void PIOC_Irq7Handler(unsigned char id) {} -WEAK void PIOC_Irq8Handler(unsigned char id) {} -WEAK void PIOC_Irq9Handler(unsigned char id) {} -WEAK void PIOC_Irq10Handler(unsigned char id) {} -WEAK void PIOC_Irq11Handler(unsigned char id) {} -WEAK void PIOC_Irq12Handler(unsigned char id) {} -WEAK void PIOC_Irq13Handler(unsigned char id) {} -WEAK void PIOC_Irq14Handler(unsigned char id) {} -WEAK void PIOC_Irq15Handler(unsigned char id) {} -WEAK void PIOC_Irq16Handler(unsigned char id) {} -WEAK void PIOC_Irq17Handler(unsigned char id) {} -WEAK void PIOC_Irq18Handler(unsigned char id) {} -WEAK void PIOC_Irq19Handler(unsigned char id) {} -WEAK void PIOC_Irq20Handler(unsigned char id) {} -WEAK void PIOC_Irq21Handler(unsigned char id) {} -WEAK void PIOC_Irq22Handler(unsigned char id) {} -WEAK void PIOC_Irq23Handler(unsigned char id) {} -WEAK void PIOC_Irq24Handler(unsigned char id) {} -WEAK void PIOC_Irq25Handler(unsigned char id) {} -WEAK void PIOC_Irq26Handler(unsigned char id) {} -WEAK void PIOC_Irq27Handler(unsigned char id) {} -WEAK void PIOC_Irq28Handler(unsigned char id) {} -WEAK void PIOC_Irq29Handler(unsigned char id) {} -WEAK void PIOC_Irq30Handler(unsigned char id) {} -WEAK void PIOC_Irq31Handler(unsigned char id) {} - - -/** PIOCHandlers records ISR routines for each PIO Id for PIO controller A */ -static const PioHandler pioCHandlers[32] = { - (PioHandler) PIOC_Irq0Handler, /**< PC0 IT Handler */ - (PioHandler) PIOC_Irq1Handler, /**< PC1 IT Handler */ - (PioHandler) PIOC_Irq2Handler, /**< PC2 IT Handler */ - (PioHandler) PIOC_Irq3Handler, /**< PC3 IT Handler */ - (PioHandler) PIOC_Irq4Handler, /**< PC4 IT Handler */ - (PioHandler) PIOC_Irq5Handler, /**< PC5 IT Handler */ - (PioHandler) PIOC_Irq6Handler, /**< PC6 IT Handler */ - (PioHandler) PIOC_Irq7Handler, /**< PC7 IT Handler */ - (PioHandler) PIOC_Irq8Handler, /**< PC8 IT Handler */ - (PioHandler) PIOC_Irq9Handler, /**< PC9 IT Handler */ - (PioHandler) PIOC_Irq10Handler, /**< PC10 IT Handler */ - (PioHandler) PIOC_Irq11Handler, /**< PC11 IT Handler */ - (PioHandler) PIOC_Irq12Handler, /**< PC12 IT Handler */ - (PioHandler) PIOC_Irq13Handler, /**< PC13 IT Handler */ - (PioHandler) PIOC_Irq14Handler, /**< PC14 IT Handler */ - (PioHandler) PIOC_Irq15Handler, /**< PC15 IT Handler */ - (PioHandler) PIOC_Irq16Handler, /**< PC16 IT Handler */ - (PioHandler) PIOC_Irq17Handler, /**< PC17 IT Handler */ - (PioHandler) PIOC_Irq18Handler, /**< PC18 IT Handler */ - (PioHandler) PIOC_Irq19Handler, /**< PC19 IT Handler */ - (PioHandler) PIOC_Irq20Handler, /**< PC20 IT Handler */ - (PioHandler) PIOC_Irq21Handler, /**< PC21 IT Handler */ - (PioHandler) PIOC_Irq22Handler, /**< PC22 IT Handler */ - (PioHandler) PIOC_Irq23Handler, /**< PC23 IT Handler */ - (PioHandler) PIOC_Irq24Handler, /**< PC24 IT Handler */ - (PioHandler) PIOC_Irq25Handler, /**< PC25 IT Handler */ - (PioHandler) PIOC_Irq26Handler, /**< PC26 IT Handler */ - (PioHandler) PIOC_Irq27Handler, /**< PC27 IT Handler */ - (PioHandler) PIOC_Irq28Handler, /**< PC28 IT Handler */ - (PioHandler) PIOC_Irq29Handler, /**< PC29 IT Handler */ - (PioHandler) PIOC_Irq30Handler, /**< PC30 IT Handler */ - (PioHandler) PIOC_Irq31Handler /**< PC31 IT Handler */ -}; - -//------------------------------------------------------------------------------ -/// \brief Generic PIO Handler. -/// The NVIC branches to the PIOx_IrqHandler() registered in exeption.c -/// PIOx_IrqHandler() invokes PIO_IrqHandler which scans which id has triggered -/// an interrupt and call the corresponding routine for the Id (<=> for the pin) -/// \param pPio PIO controller base address. -/// \param pPioHandlers Constant table which contains IT routines for each PIO Id -//------------------------------------------------------------------------------ -static void PIO_IrqHandler(Pio *pPio, const PioHandler *pPioHandlers) -{ - unsigned int status, id; - - status = pPio->PIO_ISR; - status &= pPio->PIO_IMR; - - for (id = 0; id < 32; ++id) { - if (status & (1 << id)) { - pPioHandlers[id](id); - } - } - -} - -//------------------------------------------------------------------------------ -// Global functions -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -/// \brief Parallel IO Controller A interrupt handler -/// Redefined PIOA interrupt handler for NVIC interrupt table. -//------------------------------------------------------------------------------ -void PIOA_IrqHandler(void) -{ - PIO_IrqHandler(PIOA, pioAHandlers); -} - -//------------------------------------------------------------------------------ -/// \brief Parallel IO Controller B interrupt handler -/// Redefined PIOB interrupt handler for NVIC interrupt table. -//------------------------------------------------------------------------------ -void PIOB_IrqHandler(void) -{ - PIO_IrqHandler(PIOB, pioBHandlers); -} - -//------------------------------------------------------------------------------ -/// \brief Parallel IO Controller C interrupt handler -/// Redefined PIOC interrupt handler for NVIC interrupt table. -//------------------------------------------------------------------------------ -void PIOC_IrqHandler(void) -{ - PIO_IrqHandler(PIOC, pioCHandlers); -} - -//------------------------------------------------------------------------------ -/// Enables the given interrupt source. The status -/// register of the corresponding PIO controller is cleared prior to enabling -/// the interrupt. -/// \param pPin Interrupt source to enable. -//------------------------------------------------------------------------------ -void PIO_EnableIt(const Pin *pPin) -{ - Pio* pio = pPin->pio; - TRACE_DEBUG("PIO_EnableIt()\n\r"); - -// SANITY_CHECK(pPin); - - /* Enable the interrupt in the PIO controller */ - pio->PIO_ISR; - pio->PIO_IER = pPin->mask; - - -} - -//------------------------------------------------------------------------------ -/// Disables a given interrupt source, with no added side effects. -/// \param pPin Interrupt source to disable. -//------------------------------------------------------------------------------ -void PIO_DisableIt(const Pin *pPin) -{ - Pio* pio = pPin->pio; - SANITY_CHECK(pPin); - - TRACE_DEBUG("PIO_DisableIt()\n\r"); - - /* Disable the interrupt in the PIO controller */ - pio->PIO_IDR = pPin->mask; -} - -//------------------------------------------------------------------------------ -/// \brief Initializes the PIO interrupt management logic -/// The desired priority of PIO interrupts must be provided. -/// Calling this function multiple times result in the reset of currently -/// configured interrupts. -/// \param priority PIO controller interrupts priority. -//------------------------------------------------------------------------------ -void PIO_InitializeInterrupts(unsigned int priority) -{ - TRACE_DEBUG("PIO_Initialize()\n\r"); - - // Configure PIO interrupt sources - TRACE_DEBUG("PIO_Initialize: Configuring PIOA\n\r"); - PIOA->PIO_ISR; - PIOA->PIO_IDR = 0xFFFFFFFF; - NVIC_DisableIRQ(PIOA_IRQn); - NVIC_ClearPendingIRQ(PIOA_IRQn); - NVIC_SetPriority(PIOA_IRQn, priority); - NVIC_EnableIRQ(PIOA_IRQn); - - TRACE_DEBUG("PIO_Initialize: Configuring PIOB\n\r"); - PIOB->PIO_ISR; - PIOB->PIO_IDR = 0xFFFFFFFF; - NVIC_DisableIRQ(PIOB_IRQn); - NVIC_ClearPendingIRQ(PIOB_IRQn); - NVIC_SetPriority(PIOB_IRQn, priority); - NVIC_EnableIRQ(PIOB_IRQn); - - TRACE_DEBUG("PIO_Initialize: Configuring PIOC\n\r"); - PIOC->PIO_ISR; - PIOC->PIO_IDR = 0xFFFFFFFF; - NVIC_DisableIRQ(PIOC_IRQn); - NVIC_ClearPendingIRQ(PIOC_IRQn); - NVIC_SetPriority(PIOC_IRQn, priority); - NVIC_EnableIRQ(PIOC_IRQn); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio_it.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio_it.h deleted file mode 100644 index cc44903ae..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio_it.h +++ /dev/null @@ -1,153 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \file -/// -/// \par Purpose -/// -/// Configuration and handling of interrupts on PIO status changes. The API -/// provided here have several advantages over the traditional PIO interrupt -/// configuration approach: -/// - It is highly portable -/// - It automatically demultiplexes interrupts when multiples pins have been -/// configured on a single PIO controller -/// - It allows a group of pins to share the same interrupt -/// -/// However, it also has several minor drawbacks that may prevent from using it -/// in particular applications: -/// - It enables the clocks of all PIO controllers -/// - PIO controllers all share the same interrupt handler, which does the -/// demultiplexing and can be slower than direct configuration -/// - It reserves space for a fixed number of interrupts, which can be -/// increased by modifying the appropriate constant in pio_it.c. -/// -/// \par Usage -/// -/// -# Initialize the PIO interrupt mechanism using PIO_InitializeInterrupts() -/// with the desired priority (0 ... 7). -/// -# Configure a status change interrupt on one or more pin(s) with -/// PIO_ConfigureIt(). -/// -# Enable & disable interrupts on pins using PIO_EnableIt() and -/// PIO_DisableIt(). -//------------------------------------------------------------------------------ - -#ifndef PIO_IT_H -#define PIO_IT_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "pio.h" - -//------------------------------------------------------------------------------ -// Global functions -//------------------------------------------------------------------------------ - -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/// \file - -/// Disable traces for this file -#undef TRACE_LEVEL -#define TRACE_LEVEL 0 - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "pio_it.h" -#include "pio.h" - -//------------------------------------------------------------------------------ -/// \brief Parallel IO Controller A interrupt handler -/// Redefined PIOA interrupt handler for NVIC interrupt table. -//------------------------------------------------------------------------------ -extern void PIOA_IrqHandler(void); -//------------------------------------------------------------------------------ -/// \brief Parallel IO Controller B interrupt handler -/// Redefined PIOB interrupt handler for NVIC interrupt table. -//------------------------------------------------------------------------------ -extern void PIOB_IrqHandler(void); -//------------------------------------------------------------------------------ -/// \brief Parallel IO Controller C interrupt handler -/// Redefined PIOC interrupt handler for NVIC interrupt table. -//------------------------------------------------------------------------------ -extern void PIOC_IrqHandler(void); -//------------------------------------------------------------------------------ -/// Configures and enables the given interrupt source. The status -/// register of the corresponding PIO controller is cleared prior to enabling -/// the interrupt. -/// \param pPin Interrupt source to enable. -//------------------------------------------------------------------------------ -extern void PIO_EnableIt(const Pin *pPin); -//------------------------------------------------------------------------------ -/// Disables a given interrupt source, with no added side effects. -/// \param pPin Interrupt source to disable. -//------------------------------------------------------------------------------ -extern void PIO_DisableIt(const Pin *pPin); -//------------------------------------------------------------------------------ -/// \brief Initializes the PIO interrupt management logic -/// The desired priority of PIO interrupts must be provided. -/// Calling this function multiple times result in the reset of currently -/// configured interrupts. -/// \param priority PIO controller interrupts priority. -//------------------------------------------------------------------------------ -extern void PIO_InitializeInterrupts(unsigned int priority); - -#endif //#ifndef PIO_IT_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio_keypad.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio_keypad.c deleted file mode 100644 index e0fad2675..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio_keypad.c +++ /dev/null @@ -1,147 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include -#include "pio.h" -#include "pio_keypad.h" - - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Configures keypad controller -/// \param pPIO Pointer to a PIO instance -/// \param config Configuration data for given pin,see head file for detail -//------------------------------------------------------------------------------ -void PIO_KeyPadConfig(AT91S_PIO *pPIO, KeyPadConfig *config) -{ - //enable/disable keypad controller - pPIO->PIO_KER = config->enable; - - //if enable, set keypad matrix and debouncing - if(config->enable == TRUE) { - //set key matrix - pPIO->PIO_KRCR = (config->row | config->col<<8) ; - - //set debouncing - pPIO->PIO_KDR = config->debouncing; - - } -} - - -//------------------------------------------------------------------------------ -/// Get Key Press/Release status -/// \param pPIO Pointer to a PIO instance -/// \param event Pointer to a instance of KeyEvent for storing keypad status -//------------------------------------------------------------------------------ -void PIO_GetKeyStatus(AT91S_PIO *pPIO, KeyEvent *event) -{ - int i,j; - - //get key press event - event->kdEvent.press = (pPIO->KSR&0x1)?TRUE:FALSE; - event->kdEvent.keyPressNum = (pPIO->KSR>>8)&0x3; - j=event->kdEvent.keyPressNum+1; - for(i=0; ikdEvent.preKeyMatrix[i].row = ((pPIO->KKPR) >> (8*i)) & 0x7; - event->kdEvent.preKeyMatrix[i].col = ((pPIO->KKPR) >> (8*i+4)) & 0x7; - } - - //get key release event - event->kuEvent.release = ((pPIO->KSR>>1) & 0x1)?TRUE:FALSE; - event->kuEvent.keyRelNum = (pPIO->KSR>>16)&0x3; - j=event->kdEvent.keyPressNum+1; - for(i=0;ikuEvent.relKeyMatrix[i].row = ((pPIO->KKRR) >> (8*i)) & 0x7; - event->kuEvent.relKeyMatrix[i].col = ((pPIO->KKRR) >> (8*i+4)) & 0x7; - } - -} - - -//------------------------------------------------------------------------------ -/// Enable keypad interrupt as Key Press Interrupt or Key Release Interrupt or both -/// \param pPIO Pointer to a PIO instance -/// \param mode Select key interrupt mode to enable, -/// 0x1 Key Press Interrupt -/// 0x2 Key Release Interrupt -/// 0x3 both of two type -//------------------------------------------------------------------------------ -void PIO_KeypadEnableIt(AT91S_PIO *pPIO, unsigned int mode) -{ - switch(mode){ - case 1:PIO_KeyPadEnableKPIt(pPIO); - break; - - case 2:PIO_KeyPadEnableKRIt(pPIO); - break; - - case 3:PIO_KeyPadEnableKPIt(pPIO); - PIO_KeyPadEnableKRIt(pPIO); - break; - - default:break; - } - -} - -//------------------------------------------------------------------------------ -/// Disable Key Press Interrupt or Key Release Interrupt or both of them -/// \param pPIO Pointer to a PIO instance -/// \param mode Select key interrupt mode to disable, -/// 0x1 Key Press Interrupt -/// 0x2 Key Release Interrupt -/// 0x3 both of two type -//------------------------------------------------------------------------------ -void PIO_KeypadDisableIt(AT91S_PIO *pPIO, unsigned int mode) -{ - switch(mode){ - case 1:PIO_KeyPadDisableKPIt(pPIO); - break; - - case 2:PIO_KeyPadDisableKRIt(pPIO); - break; - - case 3:PIO_KeyPadDisableKPIt(pPIO); - PIO_KeyPadDisableKRIt(pPIO); - break; - - default:break; - } - -} - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio_keypad.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio_keypad.h deleted file mode 100644 index 54021f6bd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pio/pio_keypad.h +++ /dev/null @@ -1,153 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef PIO_KEYPAD_H -#define PIO_KEYPAD_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Global Definitions -//------------------------------------------------------------------------------ - - - - -//------------------------------------------------------------------------------ -// Global Macros -//------------------------------------------------------------------------------ -//enable keypad press interrupt -#define PIO_KeyPadEnableKPIt(pPIO) ((pPIO)->KIER = 1<<0) - -//enable keypad release interrupt -#define PIO_KeyPadEnableKRIt(pPIO) ((pPIO)->KIER = 1<<1) - -//disable keypad press interrupt -#define PIO_KeyPadDisableKPIt(pPIO) ((pPIO)->KIDR = 1<<0) - -//disable keypad release interrupt -#define PIO_KeyPadDisableKRIt(pPIO) ((pPIO)->KIDR = 1<<1) - -//enable keypad controller interrupt -#define PIO_KeyPadEnableIt(pPIO, mode) {switch(mode):\ - case 1:PIO_KeyPadEnableKPIt(pPIO);break;\ - case 2:PIO_KeyPadEnableKRIt(pPIO);break;\ - case 3:PIO_KeyPadEnableKPIt(pPIO);\ - PIO_KeyPadEnableKRIt(pPIO);break;\ - default:break;\ - } - -//disable keypad controller interrupt -#define PIO_KeyPadDisableIt(pPIO, mode) {switch(mode):\ - case 1:PIO_KeyPadDisableKPIt(pPIO);break;\ - case 2:PIO_KeyPadDisableKRIt(pPIO);break;\ - case 3:PIO_KeyPadDisableKPIt(pPIO);\ - PIO_KeyPadDisableKRIt(pPIO);break;\ - default:break;\ - } - -//get keypad controller interrupt mask -#define PIO_KeyPadGetItMask(pPIO) ((pPIO)->PIO_KIMR) - - -//------------------------------------------------------------------------------ -/// Calculates the size of an array of Pin instances. The array must be defined -/// locally (i.e. not a pointer), otherwise the computation will not be correct. -/// \param pPins Local array of Pin instances. -/// \return Number of elements in array. -//------------------------------------------------------------------------------ -#define PIO_LISTSIZE(pPins) (sizeof(pPins) / sizeof(Pin)) - -//------------------------------------------------------------------------------ -// Global Types -//------------------------------------------------------------------------------ -typedef enum { - FALSE, - TRUE -} bool; - -typedef struct _KeyPadConfig { - bool enable;//keypad controller enable or disable - unsigned char col:3;//config column size - unsigned char row:3;//config row size - unsigned int debouncing;//config debouncing -} KeyPadConfig; - - -typedef struct _KeyColRow { - unsigned char row:3; - unsigned char col:3; -} KeyColRow; - - -typedef struct _KeyDownEvent { - bool press;//at least 1 pressed key detected, or 0 - unsigned char keyPressNum;//simultaneously pressed key number - KeyColRow preKeyMatrix[4];//pressed key matrix -} KeyDownEvent; - - - -typedef struct _KeyUpEvent { - bool release;//at least 1 released key detected, or 0 - unsigned char keyRelNum;//simultaneously released key number - KeyColRow relKeyMatrix[4];//released key matrix -} KeyUpEvent; - - - -typedef struct _KeyEvent { - KeyDownEvent kdEvent; - KeyUpEvent kuEvent; -} KeyEvent; - -//------------------------------------------------------------------------------ -// Global Access Macros -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -void PIO_KeyPadConfig(AT91S_PIO *pPIO, KeyPadConfig *config); - -void PIO_GetKeyStatus(AT91S_PIO *pPIO, KeyEvent *event); - -void PIO_KeypadEnableIt(AT91S_PIO *pio, unsigned int mode); - -void PIO_KeypadDisableIt(AT91S_PIO *pio, unsigned int mode); - - -#endif //#ifndef PIO_KEYPAD_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pmc/pmc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pmc/pmc.c deleted file mode 100644 index 2c72eff31..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pmc/pmc.c +++ /dev/null @@ -1,143 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "pmc.h" -#include -#include - -//------------------------------------------------------------------------------ -// Local definitions -//------------------------------------------------------------------------------ -#define MASK_STATUS0 0xFFFFFFFC -#define MASK_STATUS1 0xFFFFFFFF - - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Enables the clock of a peripheral. The peripheral ID is used - * to identify which peripheral is targetted. - * \note The ID must NOT be shifted (i.e. 1 << ID_xxx). - * \param id Peripheral ID (ID_xxx). - */ -void PMC_EnablePeripheral(unsigned int id) -{ - SANITY_CHECK(id < 35); - if (id < 32) { - if ((PMC->PMC_PCSR0 & (1 << id)) == (1 << id)) { - - TRACE_DEBUG("PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", id); - } - else { - PMC->PMC_PCER0 = 1 << id; - } - } - else { - id -= 32; - if ((PMC->PMC_PCSR1 & (1 << id)) == (1 << id)) { - - TRACE_DEBUG("PMC_EnablePeripheral: clock of peripheral" " %u is already enabled\n\r", id + 32); - } - else { - PMC->PMC_PCER1 = 1 << id; - } - } -} - -/** - * \brief Disables the clock of a peripheral. The peripheral ID is used - * to identify which peripheral is targetted. - * \note The ID must NOT be shifted (i.e. 1 << ID_xxx). - * \param id Peripheral ID (ID_xxx). - */ -void PMC_DisablePeripheral(unsigned int id) -{ - SANITY_CHECK(id < 35); - if (id < 32) { - if ((PMC->PMC_PCSR0 & (1 << id)) != (1 << id)) { - TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", id); - } - else { - PMC->PMC_PCDR0 = 1 << id; - } - } - else { - id -= 32; - if ((PMC->PMC_PCSR1 & (1 << id)) != (1 << id)) { - TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", id + 32); - } - else { - PMC->PMC_PCDR1 = 1 << id; - } - } -} - -/** - * \brief Enable all the periph clock via PMC - */ -void PMC_EnableAllPeripherals(void) -{ - PMC->PMC_PCER0 = MASK_STATUS0; - while( (PMC->PMC_PCSR0 & MASK_STATUS0) != MASK_STATUS0); - PMC->PMC_PCER1 = MASK_STATUS1; - while( (PMC->PMC_PCSR1 & MASK_STATUS1) != MASK_STATUS1); - TRACE_DEBUG("Enable all periph clocks\n\r"); -} -/** - * \brief Disable all the periph clock via PMC - */ -void PMC_DisableAllPeripherals(void) -{ - PMC->PMC_PCDR0 = MASK_STATUS0; - while((PMC->PMC_PCSR0 & MASK_STATUS0) != 0); - PMC->PMC_PCDR1 = MASK_STATUS1; - while((PMC->PMC_PCSR1 & MASK_STATUS1) != 0); - TRACE_DEBUG("Disable all periph clocks\n\r"); -} - -/** - * \brief Get Periph Status for the given peripheral ID. - * \param id Peripheral ID (ID_xxx). - */ -unsigned int PMC_IsPeriphEnabled(unsigned int id) -{ - SANITY_CHECK(id < 35); - if (id < 32) { - return (PMC->PMC_PCSR0 & (1 << id)); - } - else { - return (PMC->PMC_PCSR1 & (1 << (id - 32))); - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pmc/pmc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pmc/pmc.h deleted file mode 100644 index 0e5bd33e8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pmc/pmc.h +++ /dev/null @@ -1,62 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef PMC_H -#define PMC_H - -//------------------------------------------------------------------------------ -// Global functions -//------------------------------------------------------------------------------ - -#if defined(at91sam7l64) || defined(at91sam7l128) -extern void PMC_SetFastWakeUpInputs(unsigned int inputs); -extern void PMC_DisableMainOscillator(void); -extern -#ifdef __ICCARM__ -__ramfunc -#endif //__ICCARM__ -void PMC_DisableMainOscillatorForWaitMode(void); -#endif // at91sam7l64 at91sam7l128 - -extern void PMC_DisableProcessorClock(void); -extern void PMC_EnablePeripheral(unsigned int id); -extern void PMC_DisablePeripheral(unsigned int id); -extern void PMC_CPUInIdleMode(void); - - -extern void PMC_EnableAllPeripherals(void); - -extern void PMC_DisableAllPeripherals(void); - -extern unsigned int PMC_IsAllPeriphEnabled(void); - -extern unsigned int PMC_IsPeriphEnabled(unsigned int id); - -#endif //#ifndef PMC_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pwmc/pwmc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pwmc/pwmc.c deleted file mode 100644 index 406a5c8ad..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pwmc/pwmc.c +++ /dev/null @@ -1,648 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup pwm_module Working with PWM - * The PWM driver provides the interface to configure and use the PWM - * peripheral. - * - * The PWM macrocell controls square output waveforms of 4 channels. - * Characteristics of output waveforms such as period, duty-cycle, - * dead-time can be configured.\n - * Some of PWM channels can be linked together as synchronous channel and - * duty-cycle of synchronous channels can be updated by PDC automaticly. - * - * Before enabling the channels, they must have been configured first. - * The main settings include: - *
    - *
  • Configuration of the clock generator.
  • - *
  • Selection of the clock for each channel.
  • - *
  • Configuration of output waveform characteristics, such as period, duty-cycle etc.
  • - *
  • Configuration for synchronous channels if needed.
  • - * - Selection of the synchronous channels. - * - Selection of the moment when the WRDY flag and the corresponding PDC - * transfer request are set (PTRM and PTRCS in the PWM_SCM register). - * - Configuration of the update mode (UPDM in the PWM_SCM register). - * - Configuration of the update period (UPR in the PWM_SCUP register). - *
- * - * After the channels is enabled, the user must use respective update registers - * to change the wave characteristics to prevent unexpected output waveform. - * i.e. PWM_CDTYUPDx register should be used if user want to change duty-cycle - * when the channel is enabled. - * - * For more accurate information, please look at the PWM section of the - * Datasheet. - * - * Related files :\n - * \ref pwmc.c\n - * \ref pwmc.h.\n - */ -/*@{*/ -/*@}*/ - -/** - * \file - * - * Implementation of the Pulse Width Modulation Controller (PWM) peripheral. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -/* These headers were introduced in C99 by working group ISO/IEC JTC1/SC22/WG14. */ -#include - -#include "pwmc.h" -#include -#include -#include - -/*---------------------------------------------------------------------------- - * Local functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Finds a prescaler/divisor couple to generate the desired frequency - * from MCK. - * - * Returns the value to enter in PWM_CLK or 0 if the configuration cannot be - * met. - * - * \param frequency Desired frequency in Hz. - * \param mck Master clock frequency in Hz. - */ -static uint16_t FindClockConfiguration( - uint32_t frequency, - uint32_t mck) -{ - uint32_t divisors[11] = {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024}; - uint8_t divisor = 0; - uint32_t prescaler; - - SANITY_CHECK(frequency < mck); - - /* Find prescaler and divisor values */ - prescaler = (mck / divisors[divisor]) / frequency; - while ((prescaler > 255) && (divisor < 11)) { - - divisor++; - prescaler = (mck / divisors[divisor]) / frequency; - } - - /* Return result */ - if (divisor < 11) { - - TRACE_DEBUG("Found divisor=%u and prescaler=%u for freq=%uHz\n\r", - divisors[divisor], prescaler, frequency); - return prescaler | (divisor << 8); - } - else { - - return 0; - } -} - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Configures PWM a channel with the given parameters, basic configure function. - * - * The PWM controller must have been clocked in the PMC prior to calling this - * function. - * Beware: this function disables the channel. It waits until disable is effective. - * - * \param channel Channel number. - * \param prescaler Channel prescaler. - * \param alignment Channel alignment. - * \param polarity Channel polarity. - */ -void PWMC_ConfigureChannel( - uint8_t channel, - uint32_t prescaler, - uint32_t alignment, - uint32_t polarity) -{ - SANITY_CHECK(prescaler < PWM_CMR0_CPRE_MCKB); - SANITY_CHECK((alignment & ~PWM_CMR0_CALG) == 0); - SANITY_CHECK((polarity & ~PWM_CMR0_CPOL) == 0); - - /* Disable channel (effective at the end of the current period) */ - if ((PWM->PWM_SR & (1 << channel)) != 0) { - PWM->PWM_DIS = 1 << channel; - while ((PWM->PWM_SR & (1 << channel)) != 0); - } - - /* Configure channel */ - PWM->PWM_CH_NUM[channel].PWM_CMR = prescaler | alignment | polarity; -} - -/** - * \brief Configures PWM a channel with the given parameters, extend configure function. - * - * The PWM controller must have been clocked in the PMC prior to calling this - * function. - * Beware: this function disables the channel. It waits until disable is effective. - * - * \param channel Channel number. - * \param prescaler Channel prescaler. - * \param alignment Channel alignment. - * \param polarity Channel polarity. - * \param countEventSelect Channel counter event selection. - * \param DTEnable Channel dead time generator enable. - * \param DTHInverte Channel Dead-Time PWMHx output Inverted. - * \param DTLInverte Channel Dead-Time PWMHx output Inverted. - */ -void PWMC_ConfigureChannelExt( - uint8_t channel, - uint32_t prescaler, - uint32_t alignment, - uint32_t polarity, - uint32_t countEventSelect, - uint32_t DTEnable, - uint32_t DTHInverte, - uint32_t DTLInverte) -{ - SANITY_CHECK(prescaler < PWM_CMR0_CPRE_MCKB); - SANITY_CHECK((alignment & ~PWM_CMR0_CALG) == 0); - SANITY_CHECK((polarity & ~PWM_CMR0_CPOL) == 0); - SANITY_CHECK((countEventSelect & ~PWM_CMR0_CES) == 0); - SANITY_CHECK((DTEnable & ~PWM_CMR0_DTE) == 0); - SANITY_CHECK((DTHInverte & ~PWM_CMR0_DTHI) == 0); - SANITY_CHECK((DTLInverte & ~PWM_CMR0_DTLI) == 0); - - /* Disable channel (effective at the end of the current period) */ - if ((PWM->PWM_SR & (1 << channel)) != 0) { - PWM->PWM_DIS = 1 << channel; - while ((PWM->PWM_SR & (1 << channel)) != 0); - } - - /* Configure channel */ - PWM->PWM_CH_NUM[channel].PWM_CMR = prescaler | alignment | polarity | - countEventSelect | DTEnable | DTHInverte | DTLInverte; -} - -/** - * \brief Configures PWM clocks A & B to run at the given frequencies. - * - * This function finds the best MCK divisor and prescaler values automatically. - * - * \param clka Desired clock A frequency (0 if not used). - * \param clkb Desired clock B frequency (0 if not used). - * \param mck Master clock frequency. - */ -void PWMC_ConfigureClocks(uint32_t clka, uint32_t clkb, uint32_t mck) -{ - uint32_t mode = 0; - uint32_t result; - - /* Clock A */ - if (clka != 0) { - - result = FindClockConfiguration(clka, mck); - ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", (unsigned int)clka); - mode |= result; - } - - /* Clock B */ - if (clkb != 0) { - - result = FindClockConfiguration(clkb, mck); - ASSERT(result != 0, "-F- Could not generate the desired PWM frequency (%uHz)\n\r", (unsigned int)clkb); - mode |= (result << 16); - } - - /* Configure clocks */ - TRACE_DEBUG("Setting PWM_CLK = 0x%08X\n\r", mode); - PWM->PWM_CLK = mode; -} - -/** - * \brief Sets the period value used by a PWM channel. - * - * This function writes directly to the CPRD register if the channel is disabled; - * otherwise, it uses the update register CPRDUPD. - * - * \param channel Channel number. - * \param period Period value. - */ -void PWMC_SetPeriod(uint8_t channel, uint16_t period) -{ - /* If channel is disabled, write to CPRD */ - if ((PWM->PWM_SR & (1 << channel)) == 0) { - - PWM->PWM_CH_NUM[channel].PWM_CPRD = period; - } - /* Otherwise use update register */ - else { - - PWM->PWM_CH_NUM[channel].PWM_CPRDUPD = period; - } -} - -/** - * \brief Sets the duty cycle used by a PWM channel. - * This function writes directly to the CDTY register if the channel is disabled; - * otherwise it uses the update register CDTYUPD. - * Note that the duty cycle must always be inferior or equal to the channel - * period. - * - * \param channel Channel number. - * \param duty Duty cycle value. - */ -void PWMC_SetDutyCycle(uint8_t channel, uint16_t duty) -{ - SANITY_CHECK(duty <= PWM->PWM_CH_NUM[channel].PWM_CPRD); - - /* If channel is disabled, write to CDTY */ - if ((PWM->PWM_SR & (1 << channel)) == 0) { - - PWM->PWM_CH_NUM[channel].PWM_CDTY = duty; - } - /* Otherwise use update register */ - else { - - PWM->PWM_CH_NUM[channel].PWM_CDTYUPD = duty; - } -} - -/** - * \brief Sets the dead time used by a PWM channel. - * This function writes directly to the DT register if the channel is disabled; - * otherwise it uses the update register DTUPD. - * Note that the dead time must always be inferior or equal to the channel - * period. - * - * \param channel Channel number. - * \param timeH Dead time value for PWMHx output. - * \param timeL Dead time value for PWMLx output. - */ -void PWMC_SetDeadTime(uint8_t channel, uint16_t timeH, uint16_t timeL) -{ - SANITY_CHECK(timeH <= PWM->PWM_CH_NUM[channel].PWM_CPRD); - SANITY_CHECK(timeL <= PWM->PWM_CH_NUM[channel].PWM_CPRD); - - /* If channel is disabled, write to DT */ - if ((PWM->PWM_SR & (1 << channel)) == 0) { - - PWM->PWM_CH_NUM[channel].PWM_DT = timeH | (timeL << 16); - } - /* Otherwise use update register */ - else { - PWM->PWM_CH_NUM[channel].PWM_DTUPD = timeH | (timeL << 16); - } -} - -/** - * \brief Configures Syncronous channel with the given parameters. - * Beware: At this time, the channels should be disabled. - * - * \param channels Bitwise OR of Syncronous channels. - * \param updateMode Syncronous channel update mode. - * \param requestMode PDC transfer request mode. - * \param requestComparisonSelect PDC transfer request comparison selection. - */ -void PWMC_ConfigureSyncChannel( - uint32_t channels, - uint32_t updateMode, - uint32_t requestMode, - uint32_t requestComparisonSelect) -{ - PWM->PWM_SCM = channels | updateMode | requestMode - | requestComparisonSelect; -} - -/** - * \brief Sets the update period of the synchronous channels. - * This function writes directly to the SCUP register if the channel #0 is disabled; - * otherwise it uses the update register SCUPUPD. - * - * \param period update period. - */ -void PWMC_SetSyncChannelUpdatePeriod(uint8_t period) -{ - /* If channel is disabled, write to SCUP */ - if ((PWM->PWM_SR & (1 << 0)) == 0) { - - PWM->PWM_SCUP = period; - } - /* Otherwise use update register */ - else { - - PWM->PWM_SCUPUPD = period; - } -} - -/** - * \brief Sets synchronous channels update unlock. - * - * Note: If the UPDM field is set to 0, writing the UPDULOCK bit to 1 - * triggers the update of the period value, the duty-cycle and - * the dead-time values of synchronous channels at the beginning - * of the next PWM period. If the field UPDM is set to 1 or 2, - * writing the UPDULOCK bit to 1 triggers only the update of - * the period value and of the dead-time values of synchronous channels. - * This bit is automatically reset when the update is done. - */ -void PWMC_SetSyncChannelUpdateUnlock(void) -{ - PWM->PWM_SCUC = PWM_SCUC_UPDULOCK; -} - -/** - * \brief Enables the given PWM channel. - * - * This does NOT enable the corresponding pin;this must be done in the user code. - * - * \param channel Channel number. - */ -void PWMC_EnableChannel(uint8_t channel) -{ - PWM->PWM_ENA = 1 << channel; -} - -/** - * \brief Disables the given PWM channel. - * - * Beware, channel will be effectively disabled at the end of the current period. - * Application can check channel is disabled using the following wait loop: - * while ((PWM->PWM_SR & (1 << channel)) != 0); - * - * \param channel Channel number. - */ -void PWMC_DisableChannel(uint8_t channel) -{ - PWM->PWM_DIS = 1 << channel; -} - -/** - * \brief Enables the period interrupt for the given PWM channel. - * - * \param channel Channel number. - */ -void PWMC_EnableChannelIt(uint8_t channel) -{ - PWM->PWM_IER1 = 1 << channel; -} - -/** - * \brief Disables the period interrupt for the given PWM channel. - * - * \param channel Channel number. - */ -void PWMC_DisableChannelIt(uint8_t channel) -{ - PWM->PWM_IDR1 = 1 << channel; -} - -/** - * \brief Enables the selected interrupts sources on a PWMC peripheral. - * - * \param sources1 Bitwise OR of selected interrupt sources of PWM_IER1. - * \param sources2 Bitwise OR of selected interrupt sources of PWM_IER2. - */ -void PWMC_EnableIt(uint32_t sources1, uint32_t sources2) -{ - PWM->PWM_IER1 = sources1; - PWM->PWM_IER2 = sources2; -} - -/** - * \brief Disables the selected interrupts sources on a PWMC peripheral. - * - * \param sources1 Bitwise OR of selected interrupt sources of PWM_IDR1. - * \param sources2 Bitwise OR of selected interrupt sources of PWM_IDR2. - */ -void PWMC_DisableIt(uint32_t sources1, uint32_t sources2) -{ - PWM->PWM_IDR1 = sources1; - PWM->PWM_IDR2 = sources2; -} - -/** - * \brief Sends the contents of buffer through a PWMC peripheral, using the PDC to - * take care of the transfer. - * - * Note: Duty cycle of syncronous channels can update by PDC - * when the field UPDM (Update Mode) in the PWM_SCM register is set to 2. - * - * \param pwmc Pointer to an Pwm instance. - * \param buffer Data buffer to send. - * \param length Length of the data buffer. - */ -uint8_t PWMC_WriteBuffer(Pwm *pwmc, - void *buffer, - uint32_t length) -{ - /* Check if first bank is free */ - if (pwmc->PWM_TCR == 0) { - - pwmc->PWM_TPR = (uint32_t) buffer; - pwmc->PWM_TCR = length; - pwmc->PWM_PTCR = PERIPH_PTCR_TXTEN; - return 1; - } - /* Check if second bank is free */ - else if (pwmc->PWM_TNCR == 0) { - - pwmc->PWM_TNPR = (uint32_t) buffer; - pwmc->PWM_TNCR = length; - return 1; - } - - /* No free banks */ - return 0; -} - -/** - * \brief Set PWM output override value. - * - * \param value Bitwise OR of output override value. - */ -void PWMC_SetOverrideValue(uint32_t value) -{ - PWM->PWM_OOV = value; -} - -/** - * \brief Enalbe override output. - * - * \param value Bitwise OR of output selection. - * \param sync 0: enable the output asyncronously, 1: enable it syncronously - */ -void PWMC_EnableOverrideOutput(uint32_t value, uint32_t sync) -{ - if (sync) { - - PWM->PWM_OSSUPD = value; - } else { - - PWM->PWM_OSS = value; - } -} - -/** - * \brief Disalbe override output. - * - * \param value Bitwise OR of output selection. - * \param sync 0: enable the output asyncronously, 1: enable it syncronously - */ -void PWMC_DisableOverrideOutput(uint32_t value, uint32_t sync) -{ - if (sync) { - - PWM->PWM_OSCUPD = value; - } else { - - PWM->PWM_OSC = value; - } -} - -/** - * \brief Set PWM fault mode. - * - * \param mode Bitwise OR of fault mode. - */ -void PWMC_SetFaultMode(uint32_t mode) -{ - PWM->PWM_FMR = mode; -} - -/** - * \brief PWM fault clear. - * - * \param fault Bitwise OR of fault to clear. - */ -void PWMC_FaultClear(uint32_t fault) -{ - PWM->PWM_FCR = fault; -} - -/** - * \brief Set PWM fault protection value. - * - * \param value Bitwise OR of fault protection value. - */ -void PWMC_SetFaultProtectionValue(uint32_t value) -{ - PWM->PWM_FPV = value; -} - -/** - * \brief Enable PWM fault protection. - * - * \param value Bitwise OR of FPEx[y]. - */ -void PWMC_EnableFaultProtection(uint32_t value) -{ - PWM->PWM_FPE = value; -} - -/** - * \brief Configure comparison unit. - * - * \param x comparison x index - * \param value comparison x value. - * \param mode comparison x mode - */ -void PWMC_ConfigureComparisonUnit(uint32_t x, uint32_t value, uint32_t mode) -{ - /* If channel is disabled, write to CMPxM & CMPxV */ - if ((PWM->PWM_SR & (1 << 0)) == 0) { - if (x == 0) { - PWM->PWM_CMP0M = mode; - PWM->PWM_CMP0V = value; - } else if (x == 1) { - PWM->PWM_CMP1M = mode; - PWM->PWM_CMP1V = value; - } else if (x == 2) { - PWM->PWM_CMP2M = mode; - PWM->PWM_CMP2V = value; - } else if (x == 3) { - PWM->PWM_CMP3M = mode; - PWM->PWM_CMP3V = value; - } else if (x == 4) { - PWM->PWM_CMP4M = mode; - PWM->PWM_CMP4V = value; - } else if (x == 5) { - PWM->PWM_CMP5M = mode; - PWM->PWM_CMP5V = value; - } else if (x == 6) { - PWM->PWM_CMP6M = mode; - PWM->PWM_CMP6V = value; - } else if (x == 7) { - PWM->PWM_CMP7M = mode; - PWM->PWM_CMP7V = value; - } - } - /* Otherwise use update register */ - else { - if (x == 0) { - PWM->PWM_CMP0MUPD = mode; - PWM->PWM_CMP0VUPD = value; - } else if (x == 1) { - PWM->PWM_CMP1MUPD = mode; - PWM->PWM_CMP1VUPD = value; - } else if (x == 2) { - PWM->PWM_CMP2MUPD = mode; - PWM->PWM_CMP2VUPD = value; - } else if (x == 3) { - PWM->PWM_CMP3MUPD = mode; - PWM->PWM_CMP3VUPD = value; - } else if (x == 4) { - PWM->PWM_CMP4MUPD = mode; - PWM->PWM_CMP4VUPD = value; - } else if (x == 5) { - PWM->PWM_CMP5MUPD = mode; - PWM->PWM_CMP5VUPD = value; - } else if (x == 6) { - PWM->PWM_CMP6MUPD = mode; - PWM->PWM_CMP6VUPD = value; - } else if (x == 7) { - PWM->PWM_CMP7MUPD = mode; - PWM->PWM_CMP7VUPD = value; - } - } -} - -/** - * \brief Configure event line mode. - * - * \param x Line x - * \param mode Bitwise OR of line mode selection - */ -void PWMC_ConfigureEventLineMode(uint32_t x, uint32_t mode) -{ - SANITY_CHECK(x < 2); - - PWM->PWM_ELxMR[x] = mode; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pwmc/pwmc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pwmc/pwmc.h deleted file mode 100644 index 1c0a5b29d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/pwmc/pwmc.h +++ /dev/null @@ -1,159 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * \par Purpose - * - * Interface for configuration the Pulse Width Modulation Controller (PWM) peripheral. - * - * \par Usage - * - * -# Configures PWM clocks A & B to run at the given frequencies using - * \ref PWMC_ConfigureClocks(). - * -# Configure PWMC channel using \ref PWMC_ConfigureChannel(), \ref PWMC_ConfigureChannelExt() - * \ref PWMC_SetPeriod(), \ref PWMC_SetDutyCycle() and \ref PWMC_SetDeadTime(). - * -# Enable & disable channel using \ref PWMC_EnableChannel() and - * \ref PWMC_DisableChannel(). - * -# Enable & disable the period interrupt for the given PWM channel using - * \ref PWMC_EnableChannelIt() and \ref PWMC_DisableChannelIt(). - * -# Enable & disable the selected interrupts sources on a PWMC peripheral - * using \ref PWMC_EnableIt() and \ref PWMC_DisableIt(). - * -# Control syncronous channel using \ref PWMC_ConfigureSyncChannel(), - * \ref PWMC_SetSyncChannelUpdatePeriod() and \ref PWMC_SetSyncChannelUpdateUnlock(). - * -# Control PWM override output using \ref PWMC_SetOverrideValue(), - * \ref PWMC_EnableOverrideOutput() and \ref PWMC_DisableOverrideOutput(). - * -# \ref Send data through the transmitter using \ref PWMC_WriteBuffer(). - * - */ - -#ifndef PWMC_H -#define PWMC_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -/* PWM sub-bit field definition. begin */ -/* TODO: remove them when AT91SAM3S4.h have the definitions. */ -// PWM_CMRx -#define PWM_CMR0_CPRE_MCKA (0xB) // (PWMC_CH) -#define PWM_CMR0_CPRE_MCKB (0xC) // (PWMC_CH) -#define PWM_CMR1_CPRE_MCKA (0xB) // (PWMC_CH) -#define PWM_CMR2_CPRE_MCKA (0xB) // (PWMC_CH) -// PWM_SCM -#define PWM_SCM_UPDM_MODE0 (0x0 << 16) // (PWMC) Manual write of data and manual trigger of the update -#define PWM_SCM_UPDM_MODE1 (0x1 << 16) // (PWMC) Manual write of data and automatic trigger of the update -#define PWM_SCM_UPDM_MODE2 (0x2 << 16) // (PWMC) Automatic write of data and automatic trigger of the update -/* end */ - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void PWMC_ConfigureChannel( - uint8_t channel, - uint32_t prescaler, - uint32_t alignment, - uint32_t polarity); - -extern void PWMC_ConfigureChannelExt( - uint8_t channel, - uint32_t prescaler, - uint32_t alignment, - uint32_t polarity, - uint32_t countEventSelect, - uint32_t DTEnable, - uint32_t DTHInverte, - uint32_t DTLInverte); - -extern void PWMC_ConfigureClocks - (uint32_t clka, - uint32_t clkb, - uint32_t mck); - -extern void PWMC_SetPeriod(uint8_t channel, uint16_t period); - -extern void PWMC_SetDutyCycle(uint8_t channel, uint16_t duty); - -extern void PWMC_SetDeadTime(uint8_t channel, uint16_t timeH, uint16_t timeL); - -extern void PWMC_ConfigureSyncChannel( - uint32_t channels, - uint32_t updateMode, - uint32_t requestMode, - uint32_t requestComparisonSelect); - -extern void PWMC_SetSyncChannelUpdatePeriod(uint8_t period); - -extern void PWMC_SetSyncChannelUpdateUnlock(void); - -extern void PWMC_EnableChannel(uint8_t channel); - -extern void PWMC_DisableChannel(uint8_t channel); - -extern void PWMC_EnableChannelIt(uint8_t channel); - -extern void PWMC_DisableChannelIt(uint8_t channel); - -extern void PWMC_EnableIt(uint32_t sources1, uint32_t sources2); - -extern void PWMC_DisableIt(uint32_t sources1, uint32_t sources2); - -extern uint8_t PWMC_WriteBuffer(Pwm *pwmc, - void *buffer, - uint32_t length); - -extern void PWMC_SetOverrideValue(uint32_t value); - -extern void PWMC_EnableOverrideOutput(uint32_t value, uint32_t sync); - -extern void PWMC_DisableOverrideOutput(uint32_t value, uint32_t sync); - -extern void PWMC_SetFaultMode(uint32_t mode); - -extern void PWMC_FaultClear(uint32_t fault); - -extern void PWMC_SetFaultProtectionValue(uint32_t value); - -extern void PWMC_EnableFaultProtection(uint32_t value); - -extern void PWMC_ConfigureComparisonUnit(uint32_t x, uint32_t value, uint32_t mode); - -extern void PWMC_ConfigureEventLineMode(uint32_t x, uint32_t mode); - -#endif /* #ifndef PWMC_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta1.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta1.txt deleted file mode 100644 index a0aa300d0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta1.txt +++ /dev/null @@ -1,6 +0,0 @@ -QTouch library for AT91SAM3S-EK board version A. -Modified board. - -Burst pulses 5 CPU cycles wide. - -Slider on pins PA0, PA1, PA2, PA3, PA4, PA5 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta2.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta2.txt deleted file mode 100644 index 3ae67b9dd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/qtouch/libQTouchIarCfg3SRevABeta2.txt +++ /dev/null @@ -1,10 +0,0 @@ -QTouch library for AT91SAM3S-EK board version A. -Modified board. - -Burst pulses 5 CPU cycles wide. - -A Valid key on pins PC22 and PC23 -A UP key on pins PC24 and PC25 -A Down key on pins PC26 and PC27 -A Left key on pins PC28 and PC29 -A right key on pins PC30 and PC31 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/qtouch/libQTouchIarCfg3SRevB.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/qtouch/libQTouchIarCfg3SRevB.txt deleted file mode 100644 index b05f3865e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/qtouch/libQTouchIarCfg3SRevB.txt +++ /dev/null @@ -1,11 +0,0 @@ -QTouch library for AT91SAM3S-EK board version B. - -Burst pulses 5 CPU cycles wide. - -Slider on pins PA0, PA1, PA2, PA3, PA4, PA5 - -A Valid key on pins PC22 and PC23 -A UP key on pins PC24 and PC25 -A Down key on pins PC26 and PC27 -A Left key on pins PC28 and PC29 -A right key on pins PC30 and PC31 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/rtc/rtc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/rtc/rtc.c deleted file mode 100644 index 8ed4d4305..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/rtc/rtc.c +++ /dev/null @@ -1,467 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup rtc_module Working with RTC - * The RTC driver provides the interface to configure and use the RTC - * peripheral. - * - * It manages date, time, and alarms.\n - * This timer is clocked by the 32kHz system clock, and is not impacted by - * power management settings (PMC). To be accurate, it is better to use an - * external 32kHz crystal instead of the internal 32kHz RC.\n - * - * It uses BCD format, and time can be set in AM/PM or 24h mode through a - * configuration bit in the mode register.\n - * - * To update date or time, the user has to follow these few steps : - *
    - *
  • Set UPDTIM and/or UPDCAL bit(s) in RTC_CR,
  • - *
  • Polling or IRQ on the ACKUPD bit of RTC_CR,
  • - *
  • Clear ACKUPD bit in RTC_SCCR,
  • - *
  • Update Time and/or Calendar values in RTC_TIMR/RTC_CALR (BCD format),
  • - *
  • Clear UPDTIM and/or UPDCAL bit in RTC_CR.
  • - *
- * An alarm can be set to happen on month, date, hours, minutes or seconds, - * by setting the proper "Enable" bit of each of these fields in the Time and - * Calendar registers. - * This allows a large number of configurations to be available for the user. - * Alarm occurence can be detected even by polling or interrupt. - * - * A check of the validity of the date and time format and values written by the user is automatically done. - * Errors are reported through the Valid Entry Register. - * - * For more accurate information, please look at the RTC section of the - * Datasheet. - * - * Related files :\n - * \ref rtc.c\n - * \ref rtc.h.\n -*/ -/*@{*/ -/*@}*/ - - -/** - * \file - * - * Implementation of Real Time Clock (RTC) controller. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -/* These headers were introduced in C99 by working group ISO/IEC JTC1/SC22/WG14. */ -#include - -#include "rtc.h" -#include -#include -#include - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Sets the RTC in either 12 or 24 hour mode. - * - * \param mode Hour mode. - */ -void RTC_SetHourMode(uint32_t mode) -{ - SANITY_CHECK((mode & 0xFFFFFFFE) == 0); - - TRACE_DEBUG("RTC_SetHourMode()\n\r"); - - RTC->RTC_MR = mode; -} - -/** - * \brief Gets the RTC mode. - * - * \return Hour mode. - */ -uint32_t RTC_GetHourMode( void ) -{ - uint32_t hmode; - - TRACE_DEBUG("RTC_SetHourMode()\n\r"); - - hmode = RTC->RTC_MR; - hmode &= 0xFFFFFFFE; - - return hmode; -} - -/** - * \brief Enables the selected interrupt sources of the RTC. - * - * \param sources Interrupt sources to enable. - */ -void RTC_EnableIt(uint32_t sources) -{ - SANITY_CHECK((sources & ~0x1F) == 0); - - TRACE_DEBUG("RTC_EnableIt()\n\r"); - - RTC->RTC_IER = sources; -} - -/** -* \brief Disables the selected interrupt sources of the RTC. -* -* \param sources Interrupt sources to disable. -*/ -void RTC_DisableIt(uint32_t sources) -{ - SANITY_CHECK((sources & ~0x1F) == 0); - - TRACE_DEBUG("RTC_DisableIt()\n\r"); - - RTC->RTC_IDR = sources; -} - -/** - * \brief Sets the current time in the RTC. - * - * \param hour Current hour in 12 or 24 hour mode. - * \param minute Current minute. - * \param second Current second. - * \return 0 sucess, 1 fail to set - */ -int RTC_SetTime(uint8_t hour, uint8_t minute, uint8_t second) -{ - uint32_t time=0; - uint8_t hour_bcd; - uint8_t min_bcd; - uint8_t sec_bcd; - - TRACE_DEBUG("RTC_SetTime(%02d:%02d:%02d)\n\r", hour, minute, second); - - /* if 12-hour mode, set AMPM bit */ - if ((RTC->RTC_MR & RTC_MR_HRMOD) == RTC_MR_HRMOD) { - - if (hour > 12) { - - hour -= 12; - time |= RTC_TIMR_AMPM; - } - } - hour_bcd = (hour%10) | ((hour/10)<<4); - min_bcd = (minute%10) | ((minute/10)<<4); - sec_bcd = (second%10) | ((second/10)<<4); - - /* value overflow */ - if((hour_bcd & (uint8_t)(~RTC_HOUR_BIT_LEN_MASK)) | - (min_bcd & (uint8_t)(~RTC_MIN_BIT_LEN_MASK)) | - (sec_bcd & (uint8_t)(~RTC_SEC_BIT_LEN_MASK))) - return 1; - - time = sec_bcd | (min_bcd << 8) | (hour_bcd<<16); - - /* Set time */ - while ((RTC->RTC_SR & RTC_SR_SEC) != RTC_SR_SEC); /* wait from previous set */ - RTC->RTC_CR |= RTC_CR_UPDTIM; - while ((RTC->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD); - RTC->RTC_SCCR = RTC_SCCR_ACKCLR; - RTC->RTC_TIMR = time; - RTC->RTC_CR &= ~RTC_CR_UPDTIM; - RTC->RTC_SCCR |= RTC_SCCR_SECCLR; /* clear SECENV in SCCR */ - - return (int)(RTC->RTC_VER & RTC_VER_NVTIM); -} - -/** - * \brief Retrieves the current time as stored in the RTC in several variables. - * - * \param pHour If not null, current hour is stored in this variable. - * \param pMinute If not null, current minute is stored in this variable. - * \param pSecond If not null, current second is stored in this variable. - */ -void RTC_GetTime( - uint8_t *pHour, - uint8_t *pMinute, - uint8_t *pSecond) -{ - uint32_t time; - - TRACE_DEBUG("RTC_GetTime()\n\r"); - - /* Get current RTC time */ - time = RTC->RTC_TIMR; - while (time != RTC->RTC_TIMR) { - - time = RTC->RTC_TIMR; - } - - /* Hour */ - if (pHour) { - - *pHour = ((time & 0x00300000) >> 20) * 10 - + ((time & 0x000F0000) >> 16); - if ((time & RTC_TIMR_AMPM) == RTC_TIMR_AMPM) { - - *pHour += 12; - } - } - - /* Minute */ - if (pMinute) { - - *pMinute = ((time & 0x00007000) >> 12) * 10 - + ((time & 0x00000F00) >> 8); - } - - /* Second */ - if (pSecond) { - - *pSecond = ((time & 0x00000070) >> 4) * 10 - + (time & 0x0000000F); - } -} - -/** - * \brief Sets a time alarm on the RTC. - * The match is performed only on the provided variables; - * Setting all pointers to 0 disables the time alarm. - * - * \note In AM/PM mode, the hour value must have bit #7 set for PM, cleared for - * AM (as expected in the time registers). - * - * \param pHour If not null, the time alarm will hour-match this value. - * \param pMinute If not null, the time alarm will minute-match this value. - * \param pSecond If not null, the time alarm will second-match this value. - * \return 0 success, 1 fail to set - */ -int RTC_SetTimeAlarm( - uint8_t *pHour, - uint8_t *pMinute, - uint8_t *pSecond) -{ - uint32_t alarm = 0; - - TRACE_DEBUG("RTC_SetTimeAlarm()\n\r"); - - /* Hour */ - if (pHour) { - - alarm |= RTC_TIMALR_HOUREN | ((*pHour / 10) << 20) | ((*pHour % 10) << 16); - } - - /* Minute */ - if (pMinute) { - - alarm |= RTC_TIMALR_MINEN | ((*pMinute / 10) << 12) | ((*pMinute % 10) << 8); - } - - /* Second */ - if (pSecond) { - - alarm |= RTC_TIMALR_SECEN | ((*pSecond / 10) << 4) | (*pSecond % 10); - } - - RTC->RTC_TIMALR = alarm; - - return (int)(RTC->RTC_VER & RTC_VER_NVTIMALR); -} - -/** - * \brief Retrieves the current year, month and day from the RTC. - * Month, day and week values are numbered starting at 1. - * - * \param pYear Current year (optional). - * \param pMonth Current month (optional). - * \param pDay Current day (optional). - * \param pWeek Current day in current week (optional). - */ -void RTC_GetDate( - unsigned short *pYear, - uint8_t *pMonth, - uint8_t *pDay, - uint8_t *pWeek) -{ - uint32_t date; - - /* Get current date (multiple reads are necessary to insure a stable value) */ - do { - - date = RTC->RTC_CALR; - } - while (date != RTC->RTC_CALR); - - /* Retrieve year */ - if (pYear) { - - *pYear = (((date >> 4) & 0x7) * 1000) - + ((date & 0xF) * 100) - + (((date >> 12) & 0xF) * 10) - + ((date >> 8) & 0xF); - } - - /* Retrieve month */ - if (pMonth) { - - *pMonth = (((date >> 20) & 1) * 10) + ((date >> 16) & 0xF); - } - - /* Retrieve day */ - if (pDay) { - - *pDay = (((date >> 28) & 0x3) * 10) + ((date >> 24) & 0xF); - } - - /* Retrieve week */ - if (pWeek) { - - *pWeek = ((date >> 21) & 0x7); - } -} - -/** - * \brief Sets the current year, month and day in the RTC. - * Month, day and week values must be numbered starting from 1. - * - * \param year Current year. - * \param month Current month. - * \param day Current day. - * \param week Day number in current week. - * \return 0 success, 1 fail to set - */ -int RTC_SetDate( - unsigned short year, - uint8_t month, - uint8_t day, - uint8_t week) -{ - uint32_t date; - uint8_t cent_bcd; - uint8_t year_bcd; - uint8_t month_bcd; - uint8_t day_bcd; - uint8_t week_bcd; - - cent_bcd = ((year/100)%10) | ((year/1000)<<4); - year_bcd = (year%10) | (((year/10)%10)<<4); - month_bcd = ((month%10) | (month/10)<<4); - day_bcd = ((day%10) | (day/10)<<4); - week_bcd = ((week%10) | (week/10)<<4); - - /* value over flow */ - if((cent_bcd & (uint8_t)(~RTC_CENT_BIT_LEN_MASK)) | - (year_bcd & (uint8_t)(~RTC_YEAR_BIT_LEN_MASK)) | - (month_bcd & (uint8_t)(~RTC_MONTH_BIT_LEN_MASK)) | - (week_bcd & (uint8_t)(~RTC_WEEK_BIT_LEN_MASK)) | - (day_bcd & (uint8_t)(~RTC_DATE_BIT_LEN_MASK))) - return 1; - - - /* Convert values to date register value */ - date = cent_bcd | - (year_bcd << 8) | - (month_bcd << 16) | - (week_bcd << 21) | - (day_bcd << 24); - - - /* Update calendar register */ - while ((RTC->RTC_SR & RTC_SR_SEC) != RTC_SR_SEC); /* wait from previous set */ - RTC->RTC_CR |= RTC_CR_UPDCAL; - while ((RTC->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD); - RTC->RTC_SCCR = RTC_SCCR_ACKCLR; - RTC->RTC_CALR = date; - RTC->RTC_CR &= ~RTC_CR_UPDCAL; - RTC->RTC_SCCR |= RTC_SCCR_SECCLR; /* clear SECENV in SCCR */ - - return (int)(RTC->RTC_VER & RTC_VER_NVCAL); -} - -/** - * \brief Sets a date alarm in the RTC. - * The alarm will match only the provided values; - * Passing a null-pointer disables the corresponding field match. - * - * \param pMonth If not null, the RTC alarm will month-match this value. - * \param pDay If not null, the RTC alarm will day-match this value. - * \return 0 success, 1 fail to set - */ -int RTC_SetDateAlarm(uint8_t *pMonth, uint8_t *pDay) -{ - uint32_t alarm; - - alarm = ((pMonth) || (pDay)) ? (0) : (0x01010000); - - TRACE_DEBUG("RTC_SetDateAlarm()\n\r"); - - /* Compute alarm field value */ - if (pMonth) { - - alarm |= RTC_CALALR_MTHEN | ((*pMonth / 10) << 20) | ((*pMonth % 10) << 16); - } - if (pDay) { - - alarm |= RTC_CALALR_DATEEN | ((*pDay / 10) << 28) | ((*pDay % 10) << 24); - } - - /* Set alarm */ - RTC->RTC_CALALR = alarm; - - return (int)(RTC->RTC_VER & RTC_VER_NVCALALR); -} - -/** - * \brief Clear flag bits of status clear command register in the RTC. - * - * \param mask Bits mask of cleared events - */ -void RTC_ClearSCCR(uint32_t mask) -{ - /* Clear all flag bits in status clear command register */ - mask &= RTC_SCCR_ACKCLR | RTC_SCCR_ALRCLR | RTC_SCCR_SECCLR | \ - RTC_SCCR_TIMCLR | RTC_SCCR_CALCLR; - - RTC->RTC_SCCR = mask; -} - -/** - * \brief Get flag bits of status register in the RTC. - * - * \param mask Bits mask of Status Register - * \return Status register & mask - */ -uint32_t RTC_GetSR(uint32_t mask) -{ - uint32_t event; - - event = RTC->RTC_SR; - - return (event & mask); -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/rtc/rtc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/rtc/rtc.h deleted file mode 100644 index 5f821d3d9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/rtc/rtc.h +++ /dev/null @@ -1,99 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for Real Time Clock (RTC) controller. - * - */ - -#ifndef RTC_H -#define RTC_H - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -#define RTC_HOUR_BIT_LEN_MASK 0x3F -#define RTC_MIN_BIT_LEN_MASK 0x7F -#define RTC_SEC_BIT_LEN_MASK 0x7F -#define RTC_CENT_BIT_LEN_MASK 0x7F -#define RTC_YEAR_BIT_LEN_MASK 0xFF -#define RTC_MONTH_BIT_LEN_MASK 0x1F -#define RTC_DATE_BIT_LEN_MASK 0x3F -#define RTC_WEEK_BIT_LEN_MASK 0x07 - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void RTC_SetHourMode(uint32_t mode); - -extern uint32_t RTC_GetHourMode( void ) ; - -extern void RTC_EnableIt(uint32_t sources); - -extern void RTC_DisableIt(uint32_t sources); - -extern int RTC_SetTime( - uint8_t hour, - uint8_t minute, - uint8_t second); - -extern void RTC_GetTime( - uint8_t *pHour, - uint8_t *pMinute, - uint8_t *pSecond); - -extern int RTC_SetTimeAlarm( - uint8_t *pHour, - uint8_t *pMinute, - uint8_t *pSecond); - -extern void RTC_GetDate( - unsigned short *pYear, - uint8_t *pMonth, - uint8_t *pDay, - uint8_t *pWeek); - -extern int RTC_SetDate( - unsigned short year, - uint8_t month, - uint8_t day, - uint8_t week); - -extern int RTC_SetDateAlarm(uint8_t *pMonth, uint8_t *pDay); - -extern void RTC_ClearSCCR(uint32_t mask); - -extern uint32_t RTC_GetSR(uint32_t mask); - -#endif /* #ifndef RTC_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/rtt/rtt.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/rtt/rtt.c deleted file mode 100644 index f225ad355..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/rtt/rtt.c +++ /dev/null @@ -1,136 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup rtt_module Working with RTT - * The RTT driver provides the interface to configure and use the RTT - * peripheral. - * - * The Real-time Timer is used to count elapsed seconds.\n - * This timer is clocked by the 32kHz system clock divided by a programmable - * 16-bit balue. To be accurate, it is better to use an - * external 32kHz crystal instead of the internal 32kHz RC.\n - * - * To count elapsed seconds, the user could follow these few steps: - *
    - *
  • Programming PTPRES in RTT_MR to feeding the timer with a 1Hz signal.
  • - *
  • Writing the bit RTTRST in RTT_MR to restart the timer with new settings.
  • - *
- * - * An alarm can be set to happen on second by setting alarm value in RTT_AR. - * Alarm occurence can be detected by polling or interrupt. - * - * For more accurate information, please look at the RTT section of the - * Datasheet. - * - * Related files :\n - * \ref rtt.c\n - * \ref rtt.h.\n - */ -/*@{*/ -/*@}*/ - -/** - * \file - * - * Implementation of Real Time Timer (RTT) controller. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -/* These headers were introduced in C99 by working group ISO/IEC JTC1/SC22/WG14. */ -#include - -#include "rtt.h" -#include - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Changes the prescaler value of the given RTT and restarts it. - * - * \note This function disables RTT interrupt sources. - * - * \param rtt Pointer to a Rtt instance. - * \param prescaler Prescaler value for the RTT. - */ -void RTT_SetPrescaler(Rtt *rtt, uint16_t prescaler) -{ - rtt->RTT_MR = (prescaler | RTT_MR_RTTRST); -} - -/** - * \brief Returns the current value of the RTT timer value. - * - * \param rtt Pointer to a Rtt instance. - */ -uint32_t RTT_GetTime(Rtt *rtt) -{ - return rtt->RTT_VR; -} - -/** - * \brief Enables the specified RTT interrupt sources. - * - * \param rtt Pointer to a Rtt instance. - * \param sources Bitmask of interrupts to enable. - */ -void RTT_EnableIT(Rtt *rtt, uint32_t sources) -{ - ASSERT((sources & 0x0004FFFF) == 0, - "RTT_EnableIT: Wrong sources value.\n\r"); - rtt->RTT_MR |= sources; -} - -/** - * \brief Returns the status register value of the given RTT. - * - * \param rtt Pointer to an Rtt instance. - */ -uint32_t RTT_GetStatus(Rtt *rtt) -{ - return rtt->RTT_SR; -} - -/** - * \brief Configures the RTT to generate an alarm at the given time. - * - * \param pRtt Pointer to an Rtt instance. - * \param time Alarm time. - */ -void RTT_SetAlarm(Rtt *pRtt, uint32_t time) -{ - SANITY_CHECK(time > 0); - - pRtt->RTT_AR = time - 1; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/rtt/rtt.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/rtt/rtt.h deleted file mode 100644 index 13d4b716d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/rtt/rtt.h +++ /dev/null @@ -1,80 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * \par Purpose - * - * Interface for Real Time Timer (RTT) controller. - * - * \par Usage - * - * -# Changes the prescaler value of the given RTT and restarts it - * using \ref RTT_SetPrescaler(). - * -# Get current value of the RTT using \ref RTT_GetTime(). - * -# Enables the specified RTT interrupt using \ref RTT_EnableIT(). - * -# Get the status register value of the given RTT using \ref RTT_GetStatus(). - * -# Configures the RTT to generate an alarm at the given time - * using \ref RTT_SetAlarm(). - */ - -#ifndef RTT_H -#define RTT_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -#ifndef AT91C_BASE_RTTC - #define AT91C_BASE_RTTC RTT -#endif - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void RTT_SetPrescaler(Rtt *rtt, uint16_t prescaler); - -extern uint32_t RTT_GetTime(Rtt *rtt); - -extern void RTT_EnableIT(Rtt *rtt, uint32_t sources); - -extern uint32_t RTT_GetStatus(Rtt *rtt); - -extern void RTT_SetAlarm(Rtt *pRtt, uint32_t time); - -#endif /* #ifndef RTT_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/at45d.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/at45d.c deleted file mode 100644 index 4a6088373..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/at45d.c +++ /dev/null @@ -1,253 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup at45d_module AT45 driver. - * The AT45 Dataflash driver is based on the corresponding AT45 driver. - * A AT45 instance has to be initialized using the Dataflash levle function - * AT45_Configure(). AT45 Dataflash can be automatically detected using - * the AT45_FindDevice() function. Then AT45 dataflash operations such as - * read, write and erase DF can be launched using AT45_SendCommand function - * with corresponding AT45 command set. - * - * \usage - *
    - *
  • Reads data from the At45 at the specified address using AT45D_Read().
  • - *
  • Writes data on the At45 at the specified address using AT45D_Write().
  • - *
  • Erases a page of data at the given address using AT45D_Erase().
  • - *
  • Poll until the At45 has completed of corresponding operations using - * AT45D_WaitReady().
  • - *
  • Retrieves and returns the At45 current using AT45D_GetStatus().
  • - *
- * Related files :\n - * \ref at45d.c\n - * \ref at45d.h.\n - */ - /*@{*/ - /*@}*/ - - -/** - * \file - * - * Implementation of At45 driver. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "spi_at45.h" -#include "at45d.h" -#include -#include - -/*---------------------------------------------------------------------------- - * Local functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Wait for transfer to finish calling the SPI driver ISR (interrupts are - * disabled). - * - * \param pAt45 Pointer to an AT45 driver instance. - */ -static void AT45D_Wait(At45 *pAt45) -{ - SANITY_CHECK(pAt45); - - /* Wait for transfer to finish*/ - while (AT45_IsBusy(pAt45)) { - - SPID_Handler(pAt45->pSpid); - } -} - -/*---------------------------------------------------------------------------- - * Global functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Waits for the At45 to be ready to accept new commands. - * - * \param pAt45 Pointer to an AT45 driver instance. - */ -void AT45D_WaitReady(At45 *pAt45) -{ - uint8_t ready = 0; - - SANITY_CHECK(pAt45); - /* Poll device until it is ready.*/ - while (!ready) { - ready = AT45_STATUS_READY(AT45D_GetStatus(pAt45)); - } -} - -/** - * \brief Retrieves and returns the At45 current status, or 0 if an error happened. - * - * \param pAt45 Pointer to an AT45 driver instance. - */ -uint8_t AT45D_GetStatus(At45 *pAt45) -{ - uint8_t error; - uint8_t status; - - SANITY_CHECK(pAt45); - - /* Issue a status register read command*/ - error = AT45_SendCommand(pAt45, AT45_STATUS_READ, 1, &status, 1, 0, 0, 0); - ASSERT(!error, "-F- AT45_GetStatus: Failed to issue command.\n\r"); - - /* Wait for command to terminate*/ - while (AT45_IsBusy(pAt45)) { - AT45D_Wait(pAt45); - } - return status; -} - -/** - * \brief Reads data from the At45 inside the provided buffer. Since a continuous - * read command is used, there is no restriction on the buffer size and read address. - * - * \param pAt45 Pointer to an AT45 driver instance. - * \param pBuffer Data buffer. - * \param size Number of bytes to read. - * \param address Address at which data shall be read. - */ -void AT45D_Read( - At45 *pAt45, - uint8_t *pBuffer, - uint32_t size, - uint32_t address) -{ - uint8_t error; - - SANITY_CHECK(pAt45); - SANITY_CHECK(pBuffer); - - /* Issue a continuous read array command.*/ - error = AT45_SendCommand(pAt45, AT45_CONTINUOUS_READ_LEG, 8, pBuffer, size, address, 0, 0); - ASSERT(!error, "-F- AT45_Read: Failed to issue command\n\r"); - - /* Wait for the read command to execute.*/ - while (AT45_IsBusy(pAt45)) { - - AT45D_Wait(pAt45); - } -} - -/** - * \brief Writes data on the At45 at the specified address. Only one page of - * data is written that way; if the address is not at the beginning of the - * page, the data is written starting from this address and wraps around to - * the beginning of the page. - * \param pAt45 Pointer to an AT45 driver instance. - * \param pBuffer Data buffer. - * \param size Number of bytes to write. - * \param address Destination address on the At45. - */ -void AT45D_Write( - At45 *pAt45, - uint8_t *pBuffer, - uint32_t size, - uint32_t address) -{ - uint8_t error; - - SANITY_CHECK(pAt45); - SANITY_CHECK(pBuffer); - SANITY_CHECK(size <= pAt45->pDesc->pageSize); - - /* Issue a page write through buffer 1 command. */ - error = AT45_SendCommand(pAt45, AT45_PAGE_WRITE_BUF1, 4, pBuffer, size, address, 0, 0); - ASSERT(!error, "-F- AT45_Write: Could not issue command.\n\r"); - - /* Wait until the command is sent. */ - while (AT45_IsBusy(pAt45)) { - - AT45D_Wait(pAt45); - } - - /* Wait until the At45 becomes ready again.*/ - AT45D_WaitReady(pAt45); -} - -/** - * \brief Erases a page of data at the given address in the At45. - * - * \param pAt45 Pointer to an AT45 driver instance. - * \param address Address of page to erase. - */ -void AT45D_Erase(At45 *pAt45, uint32_t address) -{ - uint8_t error; - - SANITY_CHECK(pAt45); - - /* Issue a page erase command. */ - error = AT45_SendCommand(pAt45, AT45_PAGE_ERASE, 4, 0, 0, address, 0, 0); - ASSERT(!error, "-F- AT45_Erase: Could not issue command.\n\r"); - - /* Wait for end of transfer. */ - while (AT45_IsBusy(pAt45)) { - - AT45D_Wait(pAt45); - } - - /* Poll until the At45 has completed the erase operation.*/ - AT45D_WaitReady(pAt45); -} - -/** - * \brief Configure power-of-2 binary page size in the At45. - * - * \param pAt45 Pointer to an AT45 driver instance. - */ -void AT45D_BinaryPage(At45 *pAt45) -{ - uint8_t error; - uint8_t opcode[3]= {AT45_BINARY_PAGE}; - SANITY_CHECK(pAt45); - - /* Issue a binary page command. */ - - error = AT45_SendCommand(pAt45, AT45_BINARY_PAGE_FIRST_OPCODE, 1, opcode, 3, 0, 0, 0); - - ASSERT(!error, "-F- AT45_Erase: Could not issue command.\n\r"); - - /* Wait for end of transfer.*/ - while (AT45_IsBusy(pAt45)) { - - AT45D_Wait(pAt45); - } - - /* Wait until the At45 becomes ready again.*/ - AT45D_WaitReady(pAt45); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/at45d.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/at45d.h deleted file mode 100644 index 31a06ab66..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/at45d.h +++ /dev/null @@ -1,72 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of At45 driver. - * - */ - - -#ifndef AT45D_H -#define AT45D_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "spi_at45.h" - -/*---------------------------------------------------------------------------- - * Global functions - *----------------------------------------------------------------------------*/ - -extern void AT45D_WaitReady(At45 *pAt45); - -extern uint8_t AT45D_GetStatus(At45 *pAt45); - -extern void AT45D_Read( - At45 *pAt45, - uint8_t *pBuffer, - uint32_t size, - uint32_t address); - -extern void AT45D_Write( - At45 *pAt45, - uint8_t *pBuffer, - uint32_t size, - uint32_t address); - -extern void AT45D_Erase(At45 *pAt45, uint32_t address); - -extern void AT45D_BinaryPage(At45 *pAt45); - -#endif //#ifndef AT45D_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/spi_at45.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/spi_at45.c deleted file mode 100644 index 679a7d787..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/spi_at45.c +++ /dev/null @@ -1,311 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup spi_at45_module SPI AT45 driver. - * The Dataflash driver is based on top of the corresponding Spi driver. - * A Dataflash structure instance has to be initialized using the DF_Init - * function. Then basic dataflash operations can be launched using macros such - * as DF_continuous_read. These macros invoke the DF_Command() function which - * invokes the DPI low driver using the SPI_SendCommand() function. - * Beware to compute the dataflash internal address, the dataflash sector - * description must be known (DataflashDesc). Dataflash can be automatically - * detected using the DF_Scan() function. - * - * \usage - *
    - *
  • Initializes an AT45 instance and configures SPI chip select pin - * using AT45_Configure().
  • - *
  • Detect DF and returns DF description corresponding to the device - * connected using AT45_FindDevice().This function shall be called by - * the application before AT45_SendCommand.
  • - *
  • Sends a command to the DF through the SPI using AT45_SendCommand(). - * The command is identified by its command code and the number of - * bytes to transfer.
  • - *
  • Example code for sending command to write a page to DF.
  • - * \code - * // Issue a page write through buffer 1 command - * error = AT45_SendCommand(pAt45, AT45_PAGE_WRITE_BUF1, 4, - * pBuffer, size, address, 0, 0); - * \endcode - *
  • Example code for sending command to read a page from DF. - * If data needs to be received, then a data buffer must be - * provided.
  • - * \code - * // Issue a continuous read array command - * error = AT45_SendCommand(pAt45, AT45_CONTINUOUS_READ_LEG, 8, - * pBuffer, size, address, 0, 0); - * \endcode - *
  • This function does not block; its optional callback will - * be invoked when the transfer completes.
  • - *
  • Check the AT45 driver is ready or not by polling AT45_IsBusy(). - *
- * Related files :\n - * \ref spi_at45.c\n - * \ref spi_at45.h.\n -*/ -/*@{*/ -/*@}*/ - - -/** - * \file - * - * Implementation of SPI At45 driver. - * - */ - - - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "spi_at45.h" -#include -#include -#include - -/*---------------------------------------------------------------------------- - * Internal definitions - *----------------------------------------------------------------------------*/ - -/** Number of dataflash which can be recognized.*/ -#define NUMDATAFLASH (sizeof(at45Devices) / sizeof(At45Desc)) - -/*---------------------------------------------------------------------------- - * Local variables - *----------------------------------------------------------------------------*/ - -/** indicate if the device is configured as binary page or not.*/ -static uint8_t configuredBinaryPage; - -/** At45 device descriptor structure. */ -static const At45Desc at45Devices[] = { - { 512, 1, 264, 9, 0x0C, "AT45DB011D"}, - { 1024, 1, 264, 9, 0x14, "AT45DB021D"}, - { 2048, 1, 264, 9, 0x1C, "AT45DB041D"}, - { 4096, 1, 264, 9, 0x24, "AT45DB081D"}, - { 4096, 1, 528, 10, 0x2C, "AT45DB161D"}, - { 8192, 1, 528, 10, 0x34, "AT45DB321D"}, - { 8192, 1, 1056, 11, 0x3C, "AT45DB642D"}, - {16384, 1, 1056, 11, 0x10, "AT45DB1282"}, - {16384, 1, 2112, 12, 0x18, "AT45DB2562"}, - {32768, 1, 2112, 12, 0x20, "AT45DB5122"} -}; - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Initializes an AT45 instance and configures SPI chip select register. - * - * \param pAt45 Pointer to the At45 instance to initialize. - * \param pSpid Pointer to the underlying SPI driver. - * \param spiCs Chip select value to connect to the At45. - * \return 0. - */ -uint8_t AT45_Configure(At45 *pAt45, Spid *pSpid, uint8_t spiCs) -{ - SpidCmd *pCommand; - - /* Sanity checks */ - ASSERT(pSpid, "AT45_Configure: pSpid is 0.\n\r"); - ASSERT(pAt45, "AT45_Configure: pAt45 is 0.\n\r"); - - /* Initialize the At45 instance */ - pAt45->pSpid = pSpid; - pAt45->pDesc = 0; - memset(pAt45->pCmdBuffer, 0, 8); - - /* Initialize the spidCmd structure*/ - pCommand = &(pAt45->command); - pCommand->pCmd = pAt45->pCmdBuffer; - pCommand->callback = 0; - pCommand->pArgument = 0; - pCommand->spiCs = spiCs; - - return 0; -} - -/** - * \brief Check if the At45 driver is in busy. - * - * \param pAt45 Pointer to the At45 instance to initialize. - * \return 1 if the At45 driver is not executing any command,otherwise it returns 0. - */ -uint8_t AT45_IsBusy(At45 *pAt45) -{ - return SPID_IsBusy(pAt45->pSpid); -} - -/** - * \brief Sends a command to the dataflash through the SPI. - * The command is identified by its command code and the number of bytes to transfer - * (1 + number of address bytes + number of dummy bytes).If data needs to be received, - * then a data buffer must be provided. - * \note This function does not block; its optional callback will be invoked when - * the transfer completes. - * \param pAt45 Pointer to the At45 instance to initialize. - * \param cmd Command code. - * \param cmdSize Size of command code + address bytes + dummy bytes. - * \param pData Data buffer. - * \param dataSize Number of data bytes to send/receive. - * \param address Address at which the command is performed if meaningful. - * \param callback Optional callback to invoke at end of transfer. - * \param pArgument Optional parameter to the callback function. - * \return 0. - */ -uint8_t AT45_SendCommand( - At45 *pAt45, - uint8_t cmd, - uint8_t cmdSize, - uint8_t *pData, - uint32_t dataSize, - uint32_t address, - SpidCallback callback, - void *pArgument) -{ - SpidCmd *pCommand; - const At45Desc *pDesc = pAt45->pDesc; - uint32_t dfAddress = 0; - - /* Sanity checks*/ - ASSERT(pAt45, "AT45_Command: pAt45 is 0.\n\r"); - ASSERT(pDesc || (cmd == AT45_STATUS_READ), - "AT45_Command: Device has no descriptor, only STATUS_READ command allowed\n\r"); - - /* Check if the SPI driver is available*/ - if (AT45_IsBusy(pAt45)) { - - return AT45_ERROR_LOCK; - } - - /* Compute command pattern*/ - pAt45->pCmdBuffer[0] = cmd; - - /* Add address bytes if necessary*/ - if (cmdSize > 1) { - - ASSERT(pDesc, "AT45_Command: No descriptor for dataflash.\n\r"); - if (!configuredBinaryPage) { - dfAddress = - ((address / (pDesc->pageSize)) << pDesc->pageOffset) - + (address % (pDesc->pageSize)); - } - else { - dfAddress = address; - } - /* Write address bytes*/ - if (pDesc->pageNumber >= 16384) { - - pAt45->pCmdBuffer[1] = ((dfAddress & 0x0F000000) >> 24); - pAt45->pCmdBuffer[2] = ((dfAddress & 0x00FF0000) >> 16); - pAt45->pCmdBuffer[3] = ((dfAddress & 0x0000FF00) >> 8); - pAt45->pCmdBuffer[4] = ((dfAddress & 0x000000FF) >> 0); - - if ((cmd != AT45_CONTINUOUS_READ) && (cmd != AT45_PAGE_READ)) { - - cmdSize++; - } - } - else { - - pAt45->pCmdBuffer[1] = ((dfAddress & 0x00FF0000) >> 16); - pAt45->pCmdBuffer[2] = ((dfAddress & 0x0000FF00) >> 8); - pAt45->pCmdBuffer[3] = ((dfAddress & 0x000000FF) >> 0); - } - } - - /* Update the SPI Transfer descriptors*/ - pCommand = &(pAt45->command); - pCommand->cmdSize = cmdSize; - pCommand->pData = pData; - pCommand->dataSize = dataSize; - pCommand->callback = callback; - pCommand->pArgument = pArgument; - - /* Send Command and data through the SPI*/ - if (SPID_SendCommand(pAt45->pSpid, pCommand)) { - - return AT45_ERROR_SPI; - } - - return 0; -} - -/** - * \brief returns the At45Desc structure corresponding to the device connected. - * It automatically initializes pAt45->pDesc field structure. - * \note This function shall be called by the application before AT45_SendCommand. - * \param pAt45 Pointer to the At45 instance to initialize. - * \param status Device status register value. - * \return 0 if successful; Otherwise, returns AT45_ERROR_LOCK if the At45 - * driver is in use or AT45_ERROR_SPI if there was an error with the SPI driver. - */ -const At45Desc * AT45_FindDevice(At45 *pAt45, uint8_t status) -{ - uint32_t i; - uint8_t id = AT45_STATUS_ID(status); - - /* Check if status is all one; in which case, it is assumed that no device is connected*/ - if (status == 0xFF) { - - return 0; - } - - /* Look in device array */ - i = 0; - pAt45->pDesc = 0; - while ((i < NUMDATAFLASH) && !(pAt45->pDesc)) { - - if (at45Devices[i].id == id) { - - pAt45->pDesc = &(at45Devices[i]); - } - i++; - } - configuredBinaryPage = AT45_STATUS_BINARY(status); - return pAt45->pDesc; -} - -/** - * \brief returns the pagesize corresponding to the device connected. - * \param pAt45 Pointer to the At45 instance to initialize. - * \param status Device status register value. - * \return page size. - */ -uint32_t AT45_PageSize(At45 *pAt45) -{ - uint32_t pagesize = pAt45->pDesc->pageSize; - if(((pAt45->pDesc->hasBinaryPage) == 0) || !configuredBinaryPage){ - return pagesize; - } - return ((pagesize >> 8) << 8); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/spi_at45.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/spi_at45.h deleted file mode 100644 index fc1fca4e7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/spi_at45.h +++ /dev/null @@ -1,202 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of SPI At45 driver. - * - */ - -#ifndef SPI_AT45_H -#define SPI_AT45_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include "spi_pdc.h" - -/*---------------------------------------------------------------------------- - * Macros - *----------------------------------------------------------------------------*/ -/** Returns 1 if the device is ready; otherwise 0.*/ -#define AT45_STATUS_READY(status) (status & 0x80) -/** Returns the device ID code.*/ -#define AT45_STATUS_ID(status) (status & 0x3c) -/** Returns 1 if the device is configured in binary page mode; otherwise 0.*/ -#define AT45_STATUS_BINARY(status) (status & 0x01) - -#define AT45_PageOffset(pAt45) ((pAt45)->pDesc->pageOffset) -#define AT45_PageNumber(pAt45) ((pAt45)->pDesc->pageNumber) - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -/** The dataflash driver is currently in use.*/ -#define AT45_ERROR_LOCK 1 -/** There was an error with the SPI driver.*/ -#define AT45_ERROR_SPI 2 - -/** AT45 dataflash SPI CSR settings given MCK and SPCK.*/ -#define AT45_CSR(mck, spck) (SPI_CSR_NCPHA | SPID_CSR_DLYBCT(mck, 250) | SPID_CSR_DLYBS(mck, 250) | SPID_CSR_SCBR(mck, spck)) - -/** Main memory page read command code. */ -#define AT45_PAGE_READ 0xD2 -/** Continous array read (legacy) command code.*/ -#define AT45_CONTINUOUS_READ_LEG 0xE8 -/** Continous array read (low frequency) command code.*/ -#define AT45_CONTINUOUS_READ_LF 0x03 -/** Continous array read command code.*/ -#define AT45_CONTINUOUS_READ 0x0B -/** Buffer 1 read (low frequency) command code.*/ -#define AT45_BUF1_READ_LF 0xD1 -/** Buffer 2 read (low frequency) command code.*/ -#define AT45_BUF2_READ_LF 0xD3 -/** Buffer 1 read (serial) command code.*/ -#define AT45_BUF1_READ_SER 0xD4 -/** Buffer 2 read (serial) command code.*/ -#define AT45_BUF2_READ_SER 0xD6 -/** Buffer 1 read (8-bit) command code.*/ -#define AT45_BUF1_READ_8B 0x54 -/** Buffer 2 read (8-bit) command code.*/ -#define AT45_BUF2_READ_8B 0x56 - -/** Buffer 1 write command code.*/ -#define AT45_BUF1_WRITE 0x84 -/** Buffer 2 write command code.*/ -#define AT45_BUF2_WRITE 0x87 -/** Buffer 1 to main memory page program with erase command code.*/ -#define AT45_BUF1_MEM_ERASE 0x83 -/** Buffer 2 to main memory page program with erase command code.*/ -#define AT45_BUF2_MEM_ERASE 0x86 -/** Buffer 1 to main memory page program without erase command code.*/ -#define AT45_BUF1_MEM_NOERASE 0x88 -/** Buffer 2 to main memory page program without erase command code.*/ -#define AT45_BUF2_MEM_NOERASE 0x89 -/** Page erase command code.*/ -#define AT45_PAGE_ERASE 0x81 -/** Block erase command code.*/ -#define AT45_BLOCK_ERASE 0x50 -/** Sector erase command code.*/ -#define AT45_SECTOR_ERASE 0x7C -/** Chip erase command code.*/ -#define AT45_CHIP_ERASE 0xC7, 0x94, 0x80, 0x9A -/** Main memory page program through buffer 1 command code.*/ -#define AT45_PAGE_WRITE_BUF1 0x82 -/** Main memory page program through buffer 2 command code.*/ -#define AT45_PAGE_WRITE_BUF2 0x85 - -/** Main memory page to buffer 1 transfer command code.*/ -#define AT45_PAGE_BUF1_TX 0x53 -/** Main memory page to buffer 2 transfer command code.*/ -#define AT45_PAGE_BUF2_TX 0x55 -/** Main memory page to buffer 1 compare command code.*/ -#define AT45_PAGE_BUF1_CMP 0x60 -/** Main memory page to buffer 2 compare command code.*/ -#define AT45_PAGE_BUF2_CMP 0x61 -/** Auto page rewrite through buffer 1 command code.*/ -#define AT45_AUTO_REWRITE_BUF1 0x58 -/** Auto page rewrite through buffer 2 command code.*/ -#define AT45_AUTO_REWRITE_BUF2 0x59 -/** Deep power-down command code.*/ -#define AT45_DEEP_PDOWN 0xB9 -/** Resume from deep power-down command code.*/ -#define AT45_RES_DEEP_PDOWN 0xAB -/** Status register read command code.*/ -#define AT45_STATUS_READ 0xD7 -/** Manufacturer and device ID read command code.*/ -#define AT45_ID_READ 0x9F - -/** Power-of-2 binary page size configuration command code.*/ -#define AT45_BINARY_PAGE_FIRST_OPCODE 0x3D -#define AT45_BINARY_PAGE 0x2A, 0x80, 0xA6 - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - -/** Dataflash description. A constant array of DataflashDesc instance is defined - in at45.c. The DF_Scan() function returns the corresponding descriptor according - to the dataflash ID detected. This description (page_size, page_offset) is used - to compute the internal dataflash address by the DF_Command() function. */ -typedef struct { - /** dataflash page number. */ - uint32_t pageNumber; - // indicate if power-of-2 binary page supported.*/ - uint32_t hasBinaryPage; - /** dataflash page size.*/ - uint32_t pageSize; - /** page offset in command.*/ - uint32_t pageOffset; - /** Dataflash ID.*/ - uint8_t id; - /** Identifier.*/ - const char *name; -} At45Desc; - -/** Dataflash driver structure. It holds the current command being processed. - This structure is initialized by the DF_Init() command. - pDfDesc field can be initialized by the DF_Scan() function. - cmdBuffer is a private driver area used to compute the dataflash address to - be sent to the dataflash. Beware the PDC master must have access to this area.*/ -typedef struct _Dataflash { - /** Pointer to Spi Structure (SPI low level driver).*/ - Spid *pSpid; - /** Current SPI command sent to the SPI low level driver.*/ - SpidCmd command; - /** Pointer to the dataflash description.*/ - const At45Desc *pDesc; - /** Buffer to store the current command (opcode + dataflash address.*/ - uint8_t pCmdBuffer[8]; -} At45; - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern uint8_t AT45_Configure(At45 *pAt45, Spid *pSpid, uint8_t spiCs); - -extern uint8_t AT45_IsBusy(At45 *pAt45); - -extern uint8_t AT45_SendCommand( - At45 *pAt45, - uint8_t cmd, - uint8_t cmdSize, - uint8_t *pData, - uint32_t dataSize, - uint32_t address, - SpidCallback callback, - void *pArgument); - -extern const At45Desc * AT45_FindDevice(At45 *pAt45, uint8_t status); - -extern uint32_t AT45_PageSize(At45 *pAt45); -#endif // #ifndef SPI_AT45_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/spi_pdc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/spi_pdc.c deleted file mode 100644 index d0998b041..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/spi_pdc.c +++ /dev/null @@ -1,275 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup spi_pdc_module SPI PDC driver - * The Spi driver is a low level spi driver which performs SPI device Initializes, - * spi transfer and receive. It can be used by upper SPI driver such as AT45 - * driver and AT26 driver. - * - * \usage - *
    - *
  • Initializes a SPI instance and the corresponding SPI hardware, - * Configure SPI in Master Mode using SPID_Configure().
  • - *
  • Configures the SPI characteristics (such as Clock Polarity, Phase, - * transfers delay and Baud Rate) for the device corresponding to the - * chip select using SPID_ConfigureCS().
  • - *
  • Starts a SPI master transfer using SPID_SendCommand(). - * The transfer is performed using the PDC channels.
  • - *
  • It enable the SPI clock.
  • - *
  • Set the corresponding peripheral chip select.
  • - *
  • Initialize the two SPI PDC buffers.
  • - *
  • Initialize SPI_TPR and SPI_TCR with SPI command data and size - * to send command data first.
  • - *
  • Initialize SPI_RPR and SPI_RCR with SPI command data and size - * as dummy value.
  • - *
  • Initialize SPI_TNPR and SPI_TNCR with rest of the data to be - * transfered.(if the data specified in cmd structure)
  • - *
  • Initialize SPI_RNPR and SPI_RNCR with rest of the data to be - * received.(if the data specified in cmd structure)
  • - *
  • Initialize the callback function if specified.
  • - *
  • Enable transmitter and receiver.
  • - *
  • Example for sending a command to the dataflash through the SPI.
  • - * \code - * /// Build command to be sent. - * ... - * // Send Command and data through the SPI - * if (SPID_SendCommand(pAt45->pSpid, pCommand)) { - * return AT45_ERROR_SPI; - * } - * \endcode - *
  • The SPI_Handler() must be called by the SPI Interrupt Service Routine - * with the corresponding Spi instance. It is invokes to check for pending - * interrupts.
  • - *
  • Example for initializing SPI interrupt handler in upper application.
  • - * \code - * AIC_ConfigureIT(AT91C_ID_SPI, 0, SPI_Handler); - * \endcode - *
- * Related files :\n - * \ref spi_pdc.c\n - * \ref spi_pdc.h.\n -*/ -/*@{*/ -/*@}*/ - - -/** - * \file - * - * Implementation of SPI PDC driver. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "spi_pdc.h" -#include - -/*---------------------------------------------------------------------------- - * Macros - *----------------------------------------------------------------------------*/ - -/** Write PMC register*/ -#define WRITE_PMC(pPmc, regName, value) pPmc->regName = (value) - -/** Write SPI register*/ -#define WRITE_SPI(pSpi, regName, value) pSpi->regName = (value) - -/** Read SPI registers */ -#define READ_SPI(pSpi, regName) (pSpi->regName) - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Initializes the Spid structure and the corresponding SPI hardware. - * - * \param pSpid Pointer to a Spid instance. - * \param pSpiHw Associated SPI peripheral. - * \param spiId SPI peripheral identifier. - * \return 0. - */ -uint8_t SPID_Configure(Spid *pSpid, Spi *pSpiHw, uint8_t spiId) -{ - /* Initialize the SPI structure*/ - pSpid->pSpiHw = pSpiHw; - pSpid->spiId = spiId; - pSpid->semaphore = 1; - pSpid->pCurrentCommand = 0; - - /* Enable the SPI clock*/ - WRITE_PMC(PMC, PMC_PCER0, (1 << pSpid->spiId)); - - /* Execute a software reset of the SPI twice */ - WRITE_SPI(pSpiHw, SPI_CR, SPI_CR_SWRST); - WRITE_SPI(pSpiHw, SPI_CR, SPI_CR_SWRST); - - /* Configure SPI in Master Mode with No CS selected !!! */ - WRITE_SPI(pSpiHw, SPI_MR, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PCS); - - /* Enable the SPI*/ - WRITE_SPI(pSpiHw, SPI_CR, SPI_CR_SPIEN); - - /* Enable the SPI clock*/ - WRITE_PMC(PMC, PMC_PCDR0, (1 << pSpid->spiId)); - - return 0; -} - -/** - * \brief Configures the parameters for the device corresponding to the cs. - * - * \param pSpid Pointer to a Spid instance. - * \param cs number corresponding to the SPI chip select. - * \param csr SPI_CSR value to setup. - */ -void SPID_ConfigureCS(Spid *pSpid, uint8_t cs, uint32_t csr) -{ - Spi *pSpiHw = pSpid->pSpiHw; - WRITE_SPI(pSpiHw, SPI_CSR[cs], csr); -} - -/** - * \brief Starts a SPI master transfer. This is a non blocking function. It will - * return as soon as the transfer is started. - * - * \param pSpid Pointer to a Spid instance. - * \param pCommand Pointer to the SPI command to execute. - * \return 0 if the transfer has been started successfully; otherwise returns - * SPID_ERROR_LOCK is the driver is in use, or SPID_ERROR if the command is not - * valid. - */ -uint8_t SPID_SendCommand(Spid *pSpid, SpidCmd *pCommand) -{ - Spi *pSpiHw = pSpid->pSpiHw; - uint32_t spiMr; - - /* Try to get the dataflash semaphore */ - if (pSpid->semaphore == 0) { - - return SPID_ERROR_LOCK; - } - pSpid->semaphore--; - - /* Enable the SPI clock */ - WRITE_PMC(PMC, PMC_PCER0, (1 << pSpid->spiId)); - - /* Disable transmitter and receiver*/ - WRITE_SPI(pSpiHw, SPI_PTCR, SPI_PTCR_RXTDIS | SPI_PTCR_TXTDIS); - - /* Write to the MR register*/ - spiMr = READ_SPI(pSpiHw, SPI_MR); - spiMr |= SPI_MR_PCS; - spiMr &= ~((1 << pCommand->spiCs) << 16); - WRITE_SPI(pSpiHw, SPI_MR, spiMr); - - /* Initialize the two SPI PDC buffer*/ - WRITE_SPI(pSpiHw, SPI_RPR, (int) pCommand->pCmd); - WRITE_SPI(pSpiHw, SPI_RCR, pCommand->cmdSize); - WRITE_SPI(pSpiHw, SPI_TPR, (int) pCommand->pCmd); - WRITE_SPI(pSpiHw, SPI_TCR, pCommand->cmdSize); - - WRITE_SPI(pSpiHw, SPI_RNPR, (int) pCommand->pData); - WRITE_SPI(pSpiHw, SPI_RNCR, pCommand->dataSize); - WRITE_SPI(pSpiHw, SPI_TNPR, (int) pCommand->pData); - WRITE_SPI(pSpiHw, SPI_TNCR, pCommand->dataSize); - - /* Initialize the callback*/ - pSpid->pCurrentCommand = pCommand; - - /* Enable transmitter and receiver*/ - WRITE_SPI(pSpiHw, SPI_PTCR, SPI_PTCR_RXTEN | SPI_PTCR_TXTEN); - - /* Enable buffer complete interrupt*/ - WRITE_SPI(pSpiHw, SPI_IER, SPI_IER_RXBUFF); - - return 0; -} - - -/** - * \brief The SPI_Handler must be called by the SPI Interrupt Service Routine with the - * corresponding Spi instance. - * - * \note The SPI_Handler will unlock the Spi semaphore and invoke the upper application - * callback. - * \param pSpid Pointer to a Spid instance. - */ -void SPID_Handler(Spid *pSpid) -{ - SpidCmd *pSpidCmd = pSpid->pCurrentCommand; - Spi *pSpiHw = pSpid->pSpiHw; - volatile uint32_t spiSr; - - /* Read the status register*/ - spiSr = READ_SPI(pSpiHw, SPI_SR); - if (spiSr & SPI_SR_RXBUFF) { - - /* Disable transmitter and receiver */ - WRITE_SPI(pSpiHw, SPI_PTCR, SPI_PTCR_RXTDIS | SPI_PTCR_TXTDIS); - - /* Disable the SPI clock*/ - WRITE_PMC(PMC, PMC_PCDR0, (1 << pSpid->spiId)); - - /* Disable buffer complete interrupt */ - WRITE_SPI(pSpiHw, SPI_IDR, SPI_IDR_RXBUFF); - - /* Release the dataflash semaphore*/ - pSpid->semaphore++; - - /* Invoke the callback associated with the current command*/ - if (pSpidCmd && pSpidCmd->callback) { - - pSpidCmd->callback(0, pSpidCmd->pArgument); - } - - /* Nothing must be done after. A new DF operation may have been started - in the callback function.*/ - } -} - -/** - * \brief Returns 1 if the SPI driver is currently busy executing a command; otherwise - * returns 0. - * \param pSpid Pointer to a Spid instance. - */ -uint8_t SPID_IsBusy(const Spid *pSpid) -{ - if (pSpid->semaphore == 0) { - - return 1; - } - else { - - return 0; - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/spi_pdc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/spi_pdc.h deleted file mode 100644 index bace9efca..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi-flash/spi_pdc.h +++ /dev/null @@ -1,133 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of SPI PDC driver. - * - */ - -#ifndef SPI_PDC_H -#define SPI_PDC_H - - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ -#include - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -/** An unspecified error has occured.*/ -#define SPID_ERROR 1 - -/** SPI driver is currently in use.*/ -#define SPID_ERROR_LOCK 2 - -/*---------------------------------------------------------------------------- - * Macros - *----------------------------------------------------------------------------*/ - -/** Calculates the value of the SCBR field of the Chip Select Register given MCK and SPCK.*/ -#define SPID_CSR_SCBR(mck, spck) ((((mck) / (spck)) << 8) & SPI_CSR_SCBR) - -/** Calculates the value of the DLYBS field of the Chip Select Register given delay in ns and MCK.*/ -#define SPID_CSR_DLYBS(mck, delay) ((((((delay) * ((mck) / 1000000)) / 1000) + 1) << 16) & SPI_CSR_DLYBS) - -/** Calculates the value of the DLYBCT field of the Chip Select Register given delay in ns and MCK.*/ -#define SPID_CSR_DLYBCT(mck, delay) ((((((delay) / 32 * ((mck) / 1000000)) / 1000) + 1) << 24) & SPI_CSR_DLYBCT) - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - -/** SPI transfer complete callback.*/ -typedef void (*SpidCallback )(uint8_t, void *); - -/** Spi Transfer Request prepared by the application upper layer. This structure - is sent to the SPI_SendCommand function to start the transfer. At the end of - the transfer, the callback is invoked by the interrupt handler.*/ -typedef struct _SpidCmd { - - /** Pointer to the command data.*/ - uint8_t *pCmd; - /** Command size in bytes.*/ - uint8_t cmdSize; - /** Pointer to the data to be sent.*/ - uint8_t *pData; - /** Data size in bytes.*/ - unsigned short dataSize; - /** SPI chip select.*/ - uint8_t spiCs; - /** Callback function invoked at the end of transfer.*/ - SpidCallback callback; - /** Callback arguments.*/ - void *pArgument; - -} SpidCmd; - -/** Constant structure associated with SPI port. This structure prevents - client applications to have access in the same time.*/ -typedef struct { - - /** Pointer to SPI Hardware registers*/ - Spi *pSpiHw; - /** SPI Id as defined in the product datasheet*/ - char spiId; - /** Current SpiCommand being processed*/ - SpidCmd *pCurrentCommand; - /** Mutual exclusion semaphore.*/ - volatile char semaphore; - -} Spid; - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern uint8_t SPID_Configure( - Spid *pSpid, - Spi *pSpiHw, - uint8_t spiId); - -extern void SPID_ConfigureCS(Spid *pSpid, uint8_t cs, uint32_t csr); - -extern uint8_t SPID_SendCommand( - Spid *pSpid, - SpidCmd *pCommand); - -extern void SPID_Handler(Spid *pSpid); - -extern uint8_t SPID_IsBusy(const Spid *pSpid); - -#endif // #ifndef SPI_PDC_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi/spi.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi/spi.c deleted file mode 100644 index 4e6ba29a7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi/spi.c +++ /dev/null @@ -1,241 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup spi_module Working with SPI - * The SPI driver provides the interface to configure and use the SPI - * peripheral. - * - * The Serial Peripheral Interface (SPI) circuit is a synchronous serial - * data link that provides communication with external devices in Master - * or Slave Mode. - * - * To use the SPI, the user has to follow these few steps: - * -# Enable the SPI pins required by the application (see pio.h). - * -# Configure the SPI using the \ref SPI_Configure(). This enables the - * peripheral clock. The mode register is loaded with the given value. - * -# Configure all the necessary chip selects with \ref SPI_ConfigureNPCS(). - * -# Enable the SPI by calling \ref SPI_Enable(). - * -# Send/receive data using \ref SPI_Write() and \ref SPI_Read(). Note that \ref SPI_Read() - * must be called after \ref SPI_Write() to retrieve the last value read. - * -# Send/receive data using the PDC with the \ref SPI_WriteBuffer() and - * \ref SPI_ReadBuffer() functions. - * -# Disable the SPI by calling \ref SPI_Disable(). - * - * For more accurate information, please look at the SPI section of the - * Datasheet. - * - * Related files :\n - * \ref spi.c\n - * \ref spi.h.\n -*/ -/*@{*/ -/*@}*/ - -/** - * \file - * - * Implementation of Serial Peripheral Interface (SPI) controller. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include "spi.h" -#include "pmc/pmc.h" - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Enables a SPI peripheral. - * - * \param spi Pointer to an Spi instance. - */ -void SPI_Enable(Spi *spi) -{ - spi->SPI_CR = SPI_CR_SPIEN; -} - -/** - * \brief Disables a SPI peripheral. - * - * \param spi Pointer to an Spi instance. - */ -void SPI_Disable(Spi *spi) -{ - spi->SPI_CR = SPI_CR_SPIDIS; -} - -/** - * \brief Configures a SPI peripheral as specified. The configuration can be computed - * using several macros (see \ref spi_configuration_macros). - * - * \param spi Pointer to an Spi instance. - * \param id Peripheral ID of the SPI. - * \param configuration Value of the SPI configuration register. - */ -void SPI_Configure(Spi *spi, - uint32_t id, - uint32_t configuration) -{ - PMC_EnablePeripheral(ID_SPI); - spi->SPI_CR = SPI_CR_SPIDIS; - - /* Execute a software reset of the SPI twice */ - spi->SPI_CR = SPI_CR_SWRST; - spi->SPI_CR = SPI_CR_SWRST; - spi->SPI_MR = configuration; -} - -/** - * \brief Configures a chip select of a SPI peripheral. The chip select configuration - * is computed using several macros (see \ref spi_configuration_macros). - * - * \param spi Pointer to an Spi instance. - * \param npcs Chip select to configure (0, 1, 2 or 3). - * \param configuration Desired chip select configuration. - */ -void SPI_ConfigureNPCS(Spi *spi, - uint32_t npcs, - uint32_t configuration) -{ - spi->SPI_CSR[npcs] = configuration; -} - -/** - * \brief Sends data through a SPI peripheral. If the SPI is configured to use a fixed - * peripheral select, the npcs value is meaningless. Otherwise, it identifies - * the component which shall be addressed. - * - * \param spi Pointer to an Spi instance. - * \param npcs Chip select of the component to address (0, 1, 2 or 3). - * \param data Word of data to send. - */ -void SPI_Write(Spi *spi, uint32_t npcs, uint16_t data) -{ - /* Send data */ - while ((spi->SPI_SR & SPI_SR_TXEMPTY) == 0); - spi->SPI_TDR = data | SPI_PCS(npcs); - while ((spi->SPI_SR & SPI_SR_TDRE) == 0); -} - -/** - * \brief Sends the contents of buffer through a SPI peripheral, using the PDC to - * take care of the transfer. - * - * \param spi Pointer to an Spi instance. - * \param buffer Data buffer to send. - * \param length Length of the data buffer. - */ -uint8_t SPI_WriteBuffer(Spi *spi, - void *buffer, - uint32_t length) -{ - /* Check if first bank is free */ - if (spi->SPI_TCR == 0) { - - spi->SPI_TPR = (uint32_t) buffer; - spi->SPI_TCR = length; - spi->SPI_PTCR = PERIPH_PTCR_TXTEN; - return 1; - } - /* Check if second bank is free */ - else if (spi->SPI_TNCR == 0) { - - spi->SPI_TNPR = (uint32_t) buffer; - spi->SPI_TNCR = length; - return 1; - } - - /* No free banks */ - return 0; -} - -/** - * \brief Check if SPI transfer finish. - * - * \param spi Pointer to an Spi instance. - * - * \return Returns 1 if there is no pending write operation on the SPI; otherwise - * returns 0. - */ -uint8_t SPI_IsFinished(Spi *spi) -{ - return ((spi->SPI_SR & SPI_SR_TXEMPTY) != 0); -} - -/** - * \brief Reads and returns the last word of data received by a SPI peripheral. This - * method must be called after a successful SPI_Write call. - * - * \param spi Pointer to an Spi instance. - * - * \return readed data. - */ -uint16_t SPI_Read(Spi *spi) -{ - while ((spi->SPI_SR & SPI_SR_RDRF) == 0); - return spi->SPI_RDR & 0xFFFF; -} - -/** - * \brief Reads data from a SPI peripheral until the provided buffer is filled. This - * method does NOT need to be called after SPI_Write or SPI_WriteBuffer. - * - * \param spi Pointer to an Spi instance. - * \param buffer Data buffer to store incoming bytes. - * \param length Length in bytes of the data buffer. - */ -uint8_t SPI_ReadBuffer(Spi *spi, - void *buffer, - uint32_t length) -{ - /* Check if the first bank is free */ - if (spi->SPI_RCR == 0) { - - spi->SPI_RPR = (uint32_t) buffer; - spi->SPI_RCR = length; - spi->SPI_PTCR = PERIPH_PTCR_RXTEN; - return 1; - } - /* Check if second bank is free */ - else if (spi->SPI_RNCR == 0) { - - spi->SPI_RNPR = (uint32_t) buffer; - spi->SPI_RNCR = length; - return 1; - } - - /* No free bank */ - return 0; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi/spi.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi/spi.h deleted file mode 100644 index f78a34baf..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/spi/spi.h +++ /dev/null @@ -1,104 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for Serial Peripheral Interface (SPI) controller. - * - */ - -#ifndef SPI_H -#define SPI_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include - -/*---------------------------------------------------------------------------- - * Macros - *----------------------------------------------------------------------------*/ - -/** - * \page spi_configuration_macros SPI configuration macros - * - * This page lists several macros which should be used when configuring a SPI - * peripheral. - * - * \par Macros: - * - \ref SPI_PCS - * - \ref SPI_SCBR - * - \ref SPI_DLYBS - * - \ref SPI_DLYBCT - */ - -/** Calculate the PCS field value given the chip select NPCS value */ -#define SPI_PCS(npcs) ((~(1 << npcs) & 0xF) << 16) - -/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */ -#define SPI_SCBR(baudrate, masterClock) \ - ((uint32_t) (masterClock / baudrate) << 8) - -/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */ -#define SPI_DLYBS(delay, masterClock) \ - ((uint32_t) (((masterClock / 1000000) * delay) / 1000) << 16) - -/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */ -#define SPI_DLYBCT(delay, masterClock) \ - ((uint32_t) (((masterClock / 1000000) * delay) / 32000) << 24) -/*------------------------------------------------------------------------------ */ - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void SPI_Enable(Spi *spi); -extern void SPI_Disable(Spi *spi); -extern void SPI_Configure(Spi *spi, - uint32_t id, - uint32_t configuration); -extern void SPI_ConfigureNPCS(Spi *spi, - uint32_t npcs, - uint32_t configuration); -extern void SPI_Write(Spi *spi, uint32_t npcs, uint16_t data); -extern uint8_t SPI_WriteBuffer(Spi *spi, - void *buffer, - uint32_t length); - -extern uint8_t SPI_IsFinished(Spi *pSpi); - -extern uint16_t SPI_Read(Spi *spi); -extern uint8_t SPI_ReadBuffer(Spi *spi, - void *buffer, - uint32_t length); - -#endif /* #ifndef SPI_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/ssc/ssc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/ssc/ssc.c deleted file mode 100644 index 3fb0cc045..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/ssc/ssc.c +++ /dev/null @@ -1,248 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup ssc module Working with SSC - * The SSC driver provides the interface to configure and use the SSC - * peripheral. - * - * !Usage - * - * -# Enable the SSC interface pins. - * -# Configure the SSC to operate at a specific frequency by calling - * SSC_Configure(). This function enables the peripheral clock of the SSC, - * but not its PIOs. - * -# Configure the transmitter and/or the receiver using the - * SSC_ConfigureTransmitter() and SSC_ConfigureEmitter() functions. - * -# Enable the PIOs or the transmitter and/or the received. - * -# Enable the transmitter and/or the receiver using SSC_EnableTransmitter() - * and SSC_EnableReceiver() - * -# Send data through the transmitter using SSC_Write() and SSC_WriteBuffer() - * -# Receive data from the receiver using SSC_Read() and SSC_ReadBuffer() - * -# Disable the transmitter and/or the receiver using SSC_DisableTransmitter() - * and SSC_DisableReceiver() - * - * For more accurate information, please look at the RTC section of the - * Datasheet. - * - * Related files :\n - * \ref ssc.c\n - * \ref ssc.h.\n -*/ -/*@{*/ -/*@}*/ - - -/** - * \file - * - * Implementation of Synchronous Serial (SSC) controller. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include "ssc.h" - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Configures a SSC peripheral.If the divided clock is not used, the master - * clock frequency can be set to 0. - * \note The emitter and transmitter are disabled by this function. - * \param bitRate bit rate. - * \param masterClock master clock. - */ -void SSC_Configure(uint32_t bitRate, uint32_t masterClock) -{ - /* Enable SSC peripheral clock */ - PMC->PMC_PCER0 = 1 << ID_SSC; - - /* Reset, disable receiver & transmitter */ - SSC->SSC_CR = SSC_CR_RXDIS | SSC_CR_TXDIS | SSC_CR_SWRST; - - SSC->SSC_PTCR = SSC_PTCR_RXTDIS | SSC_PTCR_TXTDIS; - /* Configure clock frequency */ - if (bitRate != 0) { - - SSC->SSC_CMR = masterClock / (2 * bitRate); - } - else { - - SSC->SSC_CMR = 0; - } -} - -/** - * \brief Configures the transmitter of a SSC peripheral. - * \param tcmr Transmit Clock Mode Register value. - * \param tfmr Transmit Frame Mode Register value. - */ -void SSC_ConfigureTransmitter(uint32_t tcmr, uint32_t tfmr) -{ - SSC->SSC_TCMR = tcmr; - SSC->SSC_TFMR = tfmr; -} - -/** - * \brief Configures the receiver of a SSC peripheral. - * \param rcmr Receive Clock Mode Register value. - * \param rfmr Receive Frame Mode Register value. - */ -void SSC_ConfigureReceiver(uint32_t rcmr, uint32_t rfmr) -{ - SSC->SSC_RCMR = rcmr; - SSC->SSC_RFMR = rfmr; -} - -/** - * \brief Enables the transmitter of a SSC peripheral. - */ -void SSC_EnableTransmitter(void) -{ - SSC->SSC_CR = SSC_CR_TXEN; -} - -/** - * \brief Disables the transmitter of a SSC peripheral. - */ -void SSC_DisableTransmitter(void) -{ - SSC->SSC_CR = SSC_CR_TXDIS; -} - -/** - * \brief Enables the receiver of a SSC peripheral. - */ -void SSC_EnableReceiver(void) -{ - SSC->SSC_CR = SSC_CR_RXEN; -} - -/** - * \brief Disables the receiver of a SSC peripheral. - */ -void SSC_DisableReceiver(void) -{ - SSC->SSC_CR = SSC_CR_RXDIS; -} - -/** - * \brief Enables one or more interrupt sources of a SSC peripheral. - * \param Bitwise OR of selected interrupt sources. - */ -void SSC_EnableInterrupts(uint32_t sources) -{ - SSC->SSC_IER = sources; -} - -/** - * \brief Disables one or more interrupt sources of a SSC peripheral. - * \param Bitwise OR of selected interrupt sources. - */ -void SSC_DisableInterrupts(uint32_t sources) -{ - SSC->SSC_IDR = sources; -} - -/** - * \brief Sends one data frame through a SSC peripheral. If another frame is currently - * being sent, this function waits for the previous transfer to complete. - * \param frame Data frame to send. - */ -void SSC_Write(uint32_t frame) -{ - while ((SSC->SSC_SR & SSC_SR_TXRDY) == 0); - SSC->SSC_THR = frame; -} - -/** - * \brief Waits until one frame is received on a SSC peripheral, and returns it. - */ -uint32_t SSC_Read(void) -{ - while ((SSC->SSC_SR & SSC_SR_RXRDY) == 0); - return SSC->SSC_RHR; -} - -/** - * \brief Sends the contents of a data buffer a SSC peripheral, using the PDC. - * \param buffer Data buffer to send. - * \param length Size of the data buffer. - * \return 1 if the buffer has been queued for transmission; otherwise returns 0. - */ -uint8_t SSC_WriteBuffer(void *buffer, uint32_t length) -{ - /* Check if first bank is free*/ - if (SSC->SSC_TCR == 0) { - - SSC->SSC_TPR = (uint32_t) buffer; - SSC->SSC_TCR = length; - SSC->SSC_PTCR = SSC_PTCR_TXTEN; - return 1; - } - /* Check if second bank is free*/ - else if (SSC->SSC_TNCR == 0) { - - SSC->SSC_TNPR = (uint32_t) buffer; - SSC->SSC_TNCR = length; - return 1; - } - return 0; -} - -/** - * \brief Reads data coming from a SSC peripheral receiver and stores it into the - * giving buffer with PDC. - * \param buffer ata buffer used for reception. - * \param length Size of the data buffer. - * \return 1 if the buffer has been queued for reception; otherwise returns 0. - */ -uint8_t SSC_ReadBuffer(void *buffer, uint32_t length) -{ - /* Check if the first bank is free*/ - if (SSC->SSC_RCR == 0) { - - SSC->SSC_RPR = (uint32_t) buffer; - SSC->SSC_RCR = length; - SSC->SSC_PTCR = SSC_PTCR_RXTEN; - return 1; - } - /* Check if second bank is free*/ - else if (SSC->SSC_RNCR == 0) { - SSC->SSC_RNPR = (uint32_t) buffer; - SSC->SSC_RNCR = length; - return 1; - } - return 0; -} \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/ssc/ssc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/ssc/ssc.h deleted file mode 100644 index 1dd5185c6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/ssc/ssc.h +++ /dev/null @@ -1,58 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for Synchronous Serial (SSC) controller. - * - */ - -#ifndef SSC_H -#define SSC_H - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ -extern void SSC_Configure(uint32_t bitRate, uint32_t masterClock); -extern void SSC_ConfigureTransmitter(uint32_t tcmr, uint32_t tfmr); -extern void SSC_ConfigureReceiver(uint32_t rcmr, uint32_t rfmr); -extern void SSC_EnableTransmitter(void); -extern void SSC_DisableTransmitter(void); -extern void SSC_EnableReceiver(void); -extern void SSC_DisableReceiver(void); -extern void SSC_EnableInterrupts(uint32_t sources); -extern void SSC_DisableInterrupts(uint32_t sources); -extern void SSC_Write(uint32_t frame); -extern uint32_t SSC_Read(void); -extern uint8_t SSC_WriteBuffer(void *buffer, uint32_t length); -extern uint8_t SSC_ReadBuffer(void *buffer, uint32_t length); - -#endif //#ifndef SSC_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tc/tc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tc/tc.c deleted file mode 100644 index 70ed8fa34..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tc/tc.c +++ /dev/null @@ -1,148 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/*------------------------------------------------------------------------------ - * Headers - *------------------------------------------------------------------------------*/ - -#include "tc.h" - -/*------------------------------------------------------------------------------ - * Global functions - *------------------------------------------------------------------------------*/ - -/**------------------------------------------------------------------------------ - * \brief Configures a Timer Counter Channel - * Configures a Timer Counter to operate in the given mode. Timer is stopped - * after configuration and must be restarted with TC_Start(). All the - * interrupts of the timer are also disabled. - * \param pTc Pointer to an AT91S_TC instance. - * \param channel Channel number. - * \param mode Operating mode (TC_CMR value). - *------------------------------------------------------------------------------*/ -void TC_Configure(Tc *pTc, unsigned char channel, unsigned int mode) -{ - TcChannel *pTcCh = &pTc->TC_CHANNEL[channel]; - - /* Disable TC clock */ - pTcCh->TC_CCR = TC_CCR0_CLKDIS; - - /* Disable interrupts */ - pTcCh->TC_IDR = 0xFFFFFFFF; - - /* Clear status register */ - pTcCh->TC_SR; - - /* Set mode */ - pTcCh->TC_CMR = mode; -} - -/**------------------------------------------------------------------------------ - * \brief Reset and Start the TC Channel - * Enables the timer clock and performs a software reset to start the counting. - * \param pTc Pointer to an AT91S_TC instance. - * \param channel Channel number. - *------------------------------------------------------------------------------*/ -void TC_Start(Tc *pTc, unsigned char channel) -{ - TcChannel *pTcCh = &pTc->TC_CHANNEL[channel]; - pTcCh->TC_CCR = TC_CCR0_CLKEN | TC_CCR0_SWTRG; -} - -/**------------------------------------------------------------------------------ - * \brief Stop TC Channel - * Disables the timer clock, stopping the counting. - * \param pTc Pointer to an AT91S_TC instance. - * \param channel Channel number. - *------------------------------------------------------------------------------*/ -void TC_Stop(Tc *pTc, unsigned char channel) -{ - TcChannel *pTcCh = &pTc->TC_CHANNEL[channel]; - pTcCh->TC_CCR = TC_CCR0_CLKDIS; -} - -/**------------------------------------------------------------------------------ - * \brief Find best MCK divisor - * Finds the best MCK divisor given the timer frequency and MCK. The result - * is guaranteed to satisfy the following equation: - * \pre - * (MCK / (DIV * 65536)) <= freq <= (MCK / DIV) - * \endpre - * with DIV being the highest possible value. - * \param freq Desired timer frequency. - * \param mck Master clock frequency. - * \param div Divisor value. - * \param tcclks TCCLKS field value for divisor. - * \return 1 if a proper divisor has been found; otherwise 0. - *------------------------------------------------------------------------------*/ -unsigned char TC_FindMckDivisor( - unsigned int freq, - unsigned int mck, - unsigned int *div, - unsigned int *tcclks) -{ - const unsigned int divisors[5] = {2, 8, 32, 128,BOARD_MCK / 32768}; - - unsigned int index = 0; - - /* Satisfy lower bound */ - while (freq < ((mck / divisors[index]) / 65536)) { - - index++; - - /* If no divisor can be found, return 0 */ - if (index == 5) { - - return 0; - } - } - - /* Try to maximize DIV while satisfying upper bound */ - while (index < 4) { - - if (freq > (mck / divisors[index + 1])) { - - break; - } - index++; - } - - /* Store results */ - if (div) { - - *div = divisors[index]; - } - if (tcclks) { - - *tcclks = index; - } - - return 1; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tc/tc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tc/tc.h deleted file mode 100644 index 43cb83df8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tc/tc.h +++ /dev/null @@ -1,70 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/**------------------------------------------------------------------------------ - * \unit - * - * Purpose - * - * API for configuring and using Timer Counter (TC) peripherals. - * - * Usage - * -# Optionally, use TC_FindMckDivisor() to let the program find the best - * TCCLKS field value automatically. - * -# Configure a Timer Counter in the desired mode using TC_Configure(). - * -# Start or stop the timer clock using TC_Start() and TC_Stop(). - *------------------------------------------------------------------------------*/ - -#ifndef TC_H -#define TC_H - -/*------------------------------------------------------------------------------ - * Headers - *------------------------------------------------------------------------------*/ - -#include - -/*------------------------------------------------------------------------------ - * Global functions - *------------------------------------------------------------------------------*/ - -extern void TC_Configure(Tc *pTc, unsigned char ch, unsigned int mode); - -extern void TC_Start(Tc *pTc, unsigned char ch); - -extern void TC_Stop(Tc *pTc, unsigned char ch); - -extern unsigned char TC_FindMckDivisor( - unsigned int freq, - unsigned int mck, - unsigned int *div, - unsigned int *tcclks); - -#endif /* #ifndef TC_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tsd/tsd.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tsd/tsd.h deleted file mode 100644 index 38f0d8df4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tsd/tsd.h +++ /dev/null @@ -1,69 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for touchscreen driver which includes touchscreen calibration, - * retrieving measurements etc. - * - * \par Usage - * - * -# Call TSD_Initialize() whenever the touchscreen should start the - * calibration process (as it is done in the function). - * -# Declare a global TSD_PenPressed function anywhere in your code. This - * function will get called every time the pen is pressed on the screen. - * -# Declare a global TSD_PenMoved function, which will get called whenever - * the pen stays in contact with the screen but changes position. - * -# Declare a global TSD_PenReleased function, which will be invoked as the - * pen is lifted from the screen. - */ - -#ifndef TSD_H -#define TSD_H - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "tsd_com.h" - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void TSD_Initialize(int8_t calEn); - -extern uint8_t TSD_Calibrate(void); - -extern void TSD_Reset(void); - -extern void TSD_TimerHandler(void); - -#endif /* #ifndef TSD_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tsd/tsd_ads7843.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tsd/tsd_ads7843.c deleted file mode 100644 index ee0fc869d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tsd/tsd_ads7843.c +++ /dev/null @@ -1,302 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of ADS7843 driver. - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include -#include - -#ifdef BOARD_TSC_ADS7843 - -#include "tsd.h" -#include "tsd_com.h" -#include -#include -#include -#include -#include -#include -#include "tsd/tsd_ads7843.h" - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -/** Delay for pushbutton debouncing (the time-base is 10 ms). */ -#define DEBOUNCE_TIME 6 /* 10 * 6 = 60 ms */ - -/** Color of calibration points. */ -#define POINTS_COLOR 0x0000FF - -/** Size in pixels of calibration points. */ -#define POINTS_SIZE 4 - -/** Maximum difference in pixels between the test point and the measured point. */ -#define POINTS_MAX_ERROR 5 - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - -/** pen state */ -typedef enum { - STATE_PEN_RELEASED = 0, - STATE_PEN_PRESSED = 1, - STATE_PEN_DEBOUNCE = 2 -} e_pen_state; - -/*---------------------------------------------------------------------------- - * Local variables - *----------------------------------------------------------------------------*/ - -/** Pins used by Interrupt Signal for Touch Screen Controller */ -static const Pin pinPenIRQ = PIN_TCS_IRQ; - -/** Global timestamp in milliseconds since start of application. */ -static volatile uint32_t timestamp = 0; - -/** last time when the pen is pressed on the touchscreen */ -static volatile uint32_t timePress = 0; - -/** last time when the pen is released */ -static volatile uint32_t timeRelease = 0; - -/** pen state */ -static volatile e_pen_state penState = STATE_PEN_RELEASED; - -/** Touch screen initiallized flag */ -static uint32_t tsInitFlag = 0; - -/*---------------------------------------------------------------------------- - * Local functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Timer handler for touch screen. Increments the timestamp counter. - * Determine the state "Pen Pressed" or "Pen Released". To change state, - * the penIRQ has to keep the same value during DEBOUNCE_TIME. - * - * \note External timer interrupt should call it per 10ms. - */ -extern void TSD_TimerHandler( void ) -{ - uint32_t data[2]; - static uint32_t point[2]; - - if (!tsInitFlag) return; - - timestamp++; - /* Get the current position of the pen if penIRQ has low value (pen pressed) */ - if (PIO_Get(&pinPenIRQ) == 0) { - /* Get the current position of the pressed pen */ - if(TSDCom_IsCalibrationOk()) { - TSD_GetRawMeasurement(data); - TSDCom_InterpolateMeasurement(data, point); - } - - /* call the callback function */ - if(penState == STATE_PEN_PRESSED) { - if(TSDCom_IsCalibrationOk()) { - TSD_PenMoved(point[0], point[1]); - } - } - } - - /* Determine the pen state */ - if (PIO_Get(&pinPenIRQ) == 0) { - - /* reinit the last time when release */ - timeRelease = timestamp; - if(penState == STATE_PEN_DEBOUNCE) { - if( (timestamp - timePress) > DEBOUNCE_TIME) { - /* pen is pressed during an enough time : the state change */ - penState = STATE_PEN_PRESSED; - /* call the callback function */ - if(TSDCom_IsCalibrationOk()) { - TSD_PenPressed(point[0], point[1]); - } - } - } - } - else { - /* reinit the last time when release */ - timePress = timestamp; - - if(penState == STATE_PEN_DEBOUNCE) { - if( (timestamp - timeRelease) > DEBOUNCE_TIME) { - /* pen is released during an enough time : the state change */ - penState = STATE_PEN_RELEASED; - /* call the callback function */ - if(TSDCom_IsCalibrationOk()) { - TSD_PenReleased(point[0], point[1]); - } - } - } - } -} - -/** - * \breif Interrupt handler for Touchscreen. - */ -static void ISR_PenIRQ(void) -{ - /* Check if the pen has been pressed */ - if (!PIO_Get(&pinPenIRQ)) { - if(penState == STATE_PEN_RELEASED) { - - timePress = timestamp; - penState = STATE_PEN_DEBOUNCE; - } - } - else { - if(penState == STATE_PEN_PRESSED) { - - timeRelease = timestamp; - penState = STATE_PEN_DEBOUNCE; - } - } -} - -/** - * \brief Configure PENIRQ for interrupt. - */ -static void ConfigurePenIRQ(void) -{ - /* Configure pios */ - PIO_Configure(&pinPenIRQ, PIO_LISTSIZE(pinPenIRQ)); - - /* Initialize interrupts */ - PIO_InitializeInterrupts(0); - PIO_ConfigureIt(&pinPenIRQ, (void (*)(const Pin *)) ISR_PenIRQ); - - /* Enable the interrupt */ - PIO_EnableIt(&pinPenIRQ); -} - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Reads and store a touchscreen measurement in the provided array. - * - * \param pData Array where the measurements will be stored - */ -extern void TSD_GetRawMeasurement(uint32_t *pData) -{ - /* Get the current position of the pressed pen */ - PIO_DisableIt(&pinPenIRQ); - ADS7843_GetPosition(&pData[0], &pData[1]); - PIO_EnableIt(&pinPenIRQ); -} - -/** - * \brief Wait pen pressed. - */ -extern void TSD_WaitPenPressed( void ) -{ - /* Wait for touch & end of conversion */ - while (penState != STATE_PEN_RELEASED); - /*while (penState != STATE_PEN_PRESSED); */ - while (penState != STATE_PEN_PRESSED) { - } -} - -/** - * \brief Wait pen released. - */ -extern void TSD_WaitPenReleased( void ) -{ - /* Wait for contact loss */ - while (penState != STATE_PEN_PRESSED); - while (penState != STATE_PEN_RELEASED); -} - -/** - * \brief Do calibration. - * - * \return 1 if calibration is Ok, 0 else. - */ -uint8_t TSD_Calibrate(void) -{ - uint8_t ret = 0; - - /* Calibration is done only once */ - if(TSDCom_IsCalibrationOk()) { - return 1; - } - - /* Do calibration */ - ret = TSDCom_Calibrate(); - - return ret; -} - -/** - * \brief Initializes the touchscreen driver and starts the calibration process. When - * finished, the touchscreen is operational. - * - * \note Important: the LCD driver must have been initialized prior to calling this - * function. - */ -extern void TSD_Initialize( int8_t calEn ) -{ - ADS7843_Initialize(); - ConfigurePenIRQ(); - - tsInitFlag = 1; - - /* Calibration */ - if(calEn) { - while (!TSD_Calibrate()); - } -} - -/** - * \brief Stop the Touchscreen, disable interrupt. - */ -void TSD_Reset(void) -{ - /* Disable SPI 0 */ - ADS7843_Reset(); - - /* Disable the interrupt */ - PIO_DisableIt(&pinPenIRQ); -} - -#endif /* #ifdef BOARD_TSC_ADS7843 */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tsd/tsd_ads7843.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tsd/tsd_ads7843.h deleted file mode 100644 index 3f4bf2eff..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tsd/tsd_ads7843.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef _TSD_ADS7843_ -#define _TSD_ADS7843_ - -/*---------------------------------------------------------------------------- - * External functions - *----------------------------------------------------------------------------*/ -extern void TSD_PenPressed( uint32_t dwX, uint32_t dwY ) ; -extern void TSD_PenMoved( uint32_t dwX, uint32_t dwY ) ; -extern void TSD_PenReleased( uint32_t dwX, uint32_t dwY ) ; - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ -extern void TSD_WaitPenPressed( void ) ; -extern void TSD_WaitPenReleased( void ) ; -extern void TSD_GetRawMeasurement( uint32_t *pData ) ; -extern void TSD_Initialize( int8_t calEn ) ; - - -#endif // _TSD_ADS7843_ \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tsd/tsd_com.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tsd/tsd_com.c deleted file mode 100644 index 2e0360fe9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tsd/tsd_com.c +++ /dev/null @@ -1,380 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of touchscreen driver device irrelevance code. - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include - -#include "tsd.h" -#include -#include -#include -#include -#include -#include -#include -#include "tsd/tsd_ads7843.h" - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -/** Size in pixels of calibration points. */ -#define POINTS_SIZE 4 -/** Maximum difference in pixels between the test point and the measured point. */ -#define POINTS_MAX_ERROR 8 - -/** Delay at the end of calibartion for result display */ -#define DELAY_RESULT_DISPLAY 4000000 - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - -/** Point used during the touchscreen calibration process. */ -typedef struct _CalibrationPoint { - - /** Coordinate of point along the X-axis of the screen. */ - uint32_t x; - /** Coordinate of point along the Y-axis of the screen. */ - uint32_t y; - /** Calibration data of point. */ - uint32_t data[2]; - -} CalibrationPoint; - -/*---------------------------------------------------------------------------- - * Variables - *----------------------------------------------------------------------------*/ - -/** indicates if the touch screen has been calibrated. */ -/** If not, Callback functions are not called. */ -static volatile uint8_t bCalibrationOk = 1 ; //0; -/** Slope for interpoling touchscreen measurements along the X-axis. */ -static int32_t xSlope; -/** Slope for interpoling touchscreen measurements along the Y-axis. */ -static int32_t ySlope; - -/** Calibration points. */ -static CalibrationPoint calibrationPoints[] = { - - /* Top-left corner calibration point */ - { - BOARD_LCD_WIDTH / 10, - BOARD_LCD_HEIGHT / 10, - {0, 0} - }, - /* Top-right corner calibration point */ - { - BOARD_LCD_WIDTH - BOARD_LCD_WIDTH / 10, - BOARD_LCD_HEIGHT / 10, - {0, 0} - }, - /* Bottom-right corner calibration point */ - { - BOARD_LCD_WIDTH - BOARD_LCD_WIDTH / 10, - BOARD_LCD_HEIGHT - BOARD_LCD_HEIGHT / 10, - {0, 0} - }, - /* Bottom-left corner calibration point */ - { - BOARD_LCD_WIDTH / 10, - BOARD_LCD_HEIGHT - BOARD_LCD_HEIGHT / 10, - {0, 0} - } -}; - -/** Test point */ -static const CalibrationPoint testPoint = { - BOARD_LCD_WIDTH / 2, - BOARD_LCD_HEIGHT / 2, - {0, 0} -}; - -/*---------------------------------------------------------------------------- - * External functions - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - * Local functions - *----------------------------------------------------------------------------*/ - -/* - * \brief Display a calibration point on the given buffer. - * - * \param pPoint Calibration point to display. - */ -static void DrawCalibrationPoint(const CalibrationPoint *pPoint) -{ - LCDD_DrawRectangleWithFill(pPoint->x - POINTS_SIZE / 2, - pPoint->y - POINTS_SIZE / 2, - POINTS_SIZE, - POINTS_SIZE, - COLOR_RED); -} - -/** - * \brief Clears a calibration point from the given buffer. - * - * \param pPoint Calibration point to clear. - */ -static void ClearCalibrationPoint(const CalibrationPoint *pPoint) -{ - LCDD_DrawRectangleWithFill(pPoint->x - POINTS_SIZE / 2, - pPoint->y - POINTS_SIZE / 2, - POINTS_SIZE, - POINTS_SIZE, - COLOR_WHITE); -} - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \breif Indicates if the calibration of the touch screen is Ok. - * - * \return 1 calibration Ok, 0 if not. - */ -uint8_t TSDCom_IsCalibrationOk(void) -{ - if (bCalibrationOk == 1) { - return 1; - } else { - return 0; - } -} - -/** - * \brief Interpolates the provided raw measurements using the previously calculated - * slope. The resulting x and y coordinates are stored in an array. - * - * \param pData Raw measurement data, as returned by TSD_GetRawMeasurement(). - * \param pPoint Array in which x and y will be stored. - */ -void TSDCom_InterpolateMeasurement(const uint32_t *pData, uint32_t *pPoint) -{ - pPoint[0] = calibrationPoints[0].x - - (((int32_t) calibrationPoints[0].data[0] - (int32_t) pData[0]) * 1024) - / xSlope; - - pPoint[1] = calibrationPoints[0].y - - (((int32_t) calibrationPoints[0].data[1] - (int32_t) pData[1]) * 1024) - / ySlope; - - if(pPoint[0] & 0x80000000) /* Is pPoint[0] negative ? */ - { - pPoint[0] = 0; - } - - if(pPoint[0] > BOARD_LCD_WIDTH) /* Is pPoint[0] bigger than the LCD width ? */ - { - pPoint[0] = BOARD_LCD_WIDTH; - } - - if(pPoint[1] & 0x80000000) /* Is pPoint[1] negative ? */ - { - pPoint[1] = 0; - } - - if(pPoint[1] > BOARD_LCD_HEIGHT) /* Is pPoint[1] bigger than the LCD width ? */ - { - pPoint[1] = BOARD_LCD_HEIGHT; - } -} - -/** - * \brief Performs the calibration process using the provided buffer to display - * information. - * - * \return True if calibration was successful; otherwise false. - */ -uint8_t TSDCom_Calibrate(void) -{ - volatile uint32_t i; /* to keep the tempo with gcc code optimisation */ - int32_t slope1, slope2; - CalibrationPoint measuredPoint; - uint8_t xOk, yOk; - int32_t xDiff, yDiff; - - /* Calibration setup */ - LCDD_Fill(COLOR_WHITE); - LCDD_DrawString(30, 50, (uint8_t *)"LCD calibration", COLOR_BLACK); - LCDD_DrawString(1, 140, (uint8_t *)"Touch the dots to\ncalibrate the screen", COLOR_DARKBLUE); - - /* Calibration points */ - for (i=0; i < 4; i++) { - - DrawCalibrationPoint(&calibrationPoints[i]); - - /* Wait for touch & end of conversion */ - TSD_WaitPenPressed(); - TSD_GetRawMeasurement(calibrationPoints[i].data); - ClearCalibrationPoint(&calibrationPoints[i]); - - /* Wait for contact loss */ - TSD_WaitPenReleased(); - } - - /** - * Calculate slopes using the calibration data - * Theory behind those calculations: - * - We suppose the touchscreen measurements are linear, so the following equations are true (simple - * linear regression) for any two 'a' and 'b' points of the screen: - * dx = (a.data[0] - b.data[0]) / (a.x - b.x) - * dy = (a.data[1] - b.data[1]) / (a.y - b.y) - * - * - We calculate dx and dy (called xslope and yslope here) using the calibration points. - * - * - We can then use dx and dy to infer the position of a point 'p' given the measurements performed - * by the touchscreen ('c' is any of the calibration points): - * dx = (p.data[0] - c.data[0]) / (p.x - c.x) - * dy = (p.data[1] - c.data[1]) / (p.y - c.y) - * Thus: - * p.x = c.x - (p.data[0] - c.data[0]) / dx - * p.y = c.y - (p.data[1] - c.data[1]) / dy - * - * - Since there are four calibration points, dx and dy can be calculated twice, so we average - * the two values. - */ - slope1 = ((int32_t) calibrationPoints[0].data[0]) - ((int32_t) calibrationPoints[1].data[0]); - slope1 *= 1024; - slope1 /= ((int32_t) calibrationPoints[0].x) - ((int32_t) calibrationPoints[1].x); - slope2 = ((int32_t) calibrationPoints[2].data[0]) - ((int32_t) calibrationPoints[3].data[0]); - slope2 *= 1024; - slope2 /= ((int32_t) calibrationPoints[2].x) - ((int32_t) calibrationPoints[3].x); - xSlope = (slope1 + slope2) / 2; - - slope1 = ((int32_t) calibrationPoints[0].data[1]) - ((int32_t) calibrationPoints[2].data[1]); - slope1 *= 1024; - slope1 /= ((int32_t) calibrationPoints[0].y) - ((int32_t) calibrationPoints[2].y); - slope2 = ((int32_t) calibrationPoints[1].data[1]) - ((int32_t) calibrationPoints[3].data[1]); - slope2 *= 1024; - slope2 /= ((int32_t) calibrationPoints[1].y) - ((int32_t) calibrationPoints[3].y); - ySlope = (slope1 + slope2) / 2; - - /* Test point */ - LCDD_Fill(0xFFFFFF); - LCDD_DrawString(30, 50, (uint8_t *)"LCD calibration", COLOR_BLACK); - LCDD_DrawString(1, 100, (uint8_t *)" Touch the point to\nvalidate calibration", COLOR_DARKBLUE); - DrawCalibrationPoint(&testPoint); - - /* Wait for touch & end of conversion */ - TSD_WaitPenPressed(); - - TSD_GetRawMeasurement(measuredPoint.data); - TSDCom_InterpolateMeasurement(measuredPoint.data, (uint32_t *) &measuredPoint); - DrawCalibrationPoint(&measuredPoint); - - /* Check resulting x and y */ - xDiff = (int32_t) measuredPoint.x - (int32_t) testPoint.x; - yDiff = (int32_t) measuredPoint.y - (int32_t) testPoint.y; - xOk = (xDiff >= -POINTS_MAX_ERROR) && (xDiff <= POINTS_MAX_ERROR); - yOk = (yDiff >= -POINTS_MAX_ERROR) && (yDiff <= POINTS_MAX_ERROR); - - /* Wait for contact loss */ - TSD_WaitPenReleased(); - - /* Check calibration result */ - if (xOk && yOk) { - - bCalibrationOk = 1; - LCDD_Fill(COLOR_WHITE); - LCDD_DrawString(30, 50, (uint8_t *)"LCD calibration", COLOR_BLACK); - LCDD_DrawString(80, 140, (uint8_t *)"Success !", COLOR_GREEN); - - } - else { - - bCalibrationOk = 0; - LCDD_Fill(COLOR_WHITE); - LCDD_DrawString(30, 50, (uint8_t *)"LCD calibration", COLOR_BLACK); - LCDD_DrawString(40, 140, (uint8_t *)"Error too big", COLOR_RED); - } - - /* Slight delay */ - for (i = 0; i < DELAY_RESULT_DISPLAY; i++); - - return (xOk && yOk); -} - -/** - * \brief Read calibrate data to buffer. - * - * \param pBuffer Data buffer. - * \param size Size of data buffer in bytes. - */ -void TSDCom_ReadCalibrateData(void *pBuffer, uint32_t size) -{ - uint8_t *pDest = (uint8_t *)pBuffer; - - SANITY_CHECK((sizeof(bCalibrationOk) + sizeof(xSlope) + - sizeof(ySlope) + sizeof(calibrationPoints[0].data)) < size); - - memcpy(pDest, (void const *)&bCalibrationOk, sizeof(bCalibrationOk)); - pDest += sizeof(bCalibrationOk); - memcpy(pDest, &xSlope, sizeof(xSlope)); - pDest += sizeof(xSlope); - memcpy(pDest, &ySlope, sizeof(ySlope)); - pDest += sizeof(ySlope); - memcpy(pDest, &calibrationPoints[0].data, sizeof(calibrationPoints[0].data)); - pDest += sizeof(calibrationPoints[0].data); -} - -/** - * \brief Restore calibrate data with buffer data. - * - * \param pBuffer Data buffer. - * \param size Size of data buffer in bytes. - */ -void TSDCom_RestoreCalibrateData(void *pBuffer, uint32_t size) -{ - uint8_t *pSrc = (uint8_t *)pBuffer; - - SANITY_CHECK((sizeof(bCalibrationOk) + sizeof(xSlope) + - sizeof(ySlope) + sizeof(calibrationPoints[0].data)) < size); - - memcpy((void *)&bCalibrationOk, pSrc, sizeof(bCalibrationOk)); - pSrc += sizeof(bCalibrationOk); - memcpy(&xSlope, pSrc, sizeof(xSlope)); - pSrc += sizeof(xSlope); - memcpy(&ySlope, pSrc, sizeof(ySlope)); - pSrc += sizeof(ySlope); - memcpy(&calibrationPoints[0].data, pSrc, sizeof(calibrationPoints[0].data)); - pSrc += sizeof(calibrationPoints[0].data); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tsd/tsd_com.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tsd/tsd_com.h deleted file mode 100644 index ca6f285d6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/tsd/tsd_com.h +++ /dev/null @@ -1,54 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for touchscreen driver device irrelevance code. - */ - -#ifndef TSD_COM_H -#define TSD_COM_H - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void TSDCom_InterpolateMeasurement( - const uint32_t *pData, - uint32_t *pPoint); - -uint8_t TSDCom_Calibrate(void); - -uint8_t TSDCom_IsCalibrationOk(void); - -void TSDCom_ReadCalibrateData(void *pBuffer, uint32_t size); -void TSDCom_RestoreCalibrateData(void *pBuffer, uint32_t size); - -#endif /* #ifndef TSD_COM_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/twi/twi.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/twi/twi.c deleted file mode 100644 index 5de7b2ee5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/twi/twi.c +++ /dev/null @@ -1,377 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup twi_module Working with TWI - * The TWI driver provides the interface to configure and use the TWI - * peripheral. - * - * \usage - *
    - *
  • Configures a TWI peripheral to operate in master mode, at the given - * frequency (in Hz) using TWI_Configure().
  • - *
  • Sends a STOP condition on the TWI using TWI_Stop().
  • - *
  • Starts a read operation on the TWI bus with the specified slave using - * TWI_StartRead(). Data must then be read using TWI_ReadByte() whenever - * a byte is available (poll using TWI_ByteReceived()).
  • - *
  • Starts a write operation on the TWI to access the selected slave using - * TWI_StartWrite(). A byte of data must be provided to start the write; - * other bytes are written next.
  • - *
  • Sends a byte of data to one of the TWI slaves on the bus using TWI_WriteByte(). - * This function must be called once before TWI_StartWrite() with the first byte of data - * to send, then it shall be called repeatedly after that to send the remaining bytes.
  • - *
  • Check if a byte has been received and can be read on the given TWI - * peripheral using TWI_ByteReceived().< - * Check if a byte has been sent using TWI_ByteSent().
  • - *
  • Check if the current transmission is complete (the STOP has been sent) - * using TWI_TransferComplete().
  • - *
  • Enables & disable the selected interrupts sources on a TWI peripheral - * using TWI_EnableIt() and TWI_DisableIt().
  • - *
  • Get current status register of the given TWI peripheral using - * TWI_GetStatus(). Get current status register of the given TWI peripheral, but - * masking interrupt sources which are not currently enabled using - * TWI_GetMaskedStatus().
  • - *
- * For more accurate information, please look at the TWI section of the - * Datasheet. - * - * Related files :\n - * \ref twi.c\n - * \ref twi.h.\n -*/ -/*@{*/ -/*@}*/ - - -/** - * \file - * - * Implementation of Two Wire Interface (TWI). - * - */ - - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include "twi.h" -#include -#include -#include - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Configures a TWI peripheral to operate in master mode, at the given - * frequency (in Hz). The duty cycle of the TWI clock is set to 50%. - * \param pTwi Pointer to an Twi instance. - * \param twck Desired TWI clock frequency. - * \param mck Master clock frequency. - */ -void TWI_ConfigureMaster(Twi *pTwi, uint32_t twck, uint32_t mck) -{ - uint32_t ckdiv = 0; - uint32_t cldiv; - uint8_t ok = 0; - - TRACE_DEBUG("TWI_ConfigureMaster()\n\r"); - SANITY_CHECK(pTwi); - - /* SVEN: TWI Slave Mode Enabled */ - pTwi->TWI_CR = TWI_CR_SVEN; - /* Reset the TWI*/ - pTwi->TWI_CR = TWI_CR_SWRST; - pTwi->TWI_RHR; - - /* TWI Slave Mode Disabled, TWI Master Mode Disabled. */ - pTwi->TWI_CR = TWI_CR_SVDIS; - pTwi->TWI_CR = TWI_CR_MSDIS; - - /* Set master mode */ - pTwi->TWI_CR = TWI_CR_MSEN; - - /* Configure clock */ - while (!ok) { - cldiv = ((mck / (2 * twck)) - 3) / power(2, ckdiv); - if (cldiv <= 255) { - ok = 1; - } - else { - ckdiv++; - } - } - ASSERT(ckdiv < 8, "-F- Cannot find valid TWI clock parameters\n\r"); - TRACE_DEBUG("Using CKDIV = %u and CLDIV/CHDIV = %u\n\r", ckdiv, cldiv); - pTwi->TWI_CWGR = 0; - pTwi->TWI_CWGR = (ckdiv << 16) | (cldiv << 8) | cldiv; -} - -/** - * \brief Configures a TWI peripheral to operate in slave mode. - * \param pTwi Pointer to an Twi instance. - * \param slaveAddress Slave address. - */ -void TWI_ConfigureSlave(Twi *pTwi, uint8_t slaveAddress) -{ - uint32_t i; - - /* TWI software reset */ - pTwi->TWI_CR = TWI_CR_SWRST; - pTwi->TWI_RHR; - - /* Wait at least 10 ms */ - for (i=0; i < 1000000; i++); - - /* TWI Slave Mode Disabled, TWI Master Mode Disabled*/ - pTwi->TWI_CR = TWI_CR_SVDIS | TWI_CR_MSDIS; - - /* Configure slave address. */ - pTwi->TWI_SMR = 0; - pTwi->TWI_SMR = (slaveAddress << 16) & TWI_SMR_SADR; - - /* SVEN: TWI Slave Mode Enabled */ - pTwi->TWI_CR = TWI_CR_SVEN; - - /* Wait at least 10 ms */ - for (i=0; i < 1000000; i++); - ASSERT( (pTwi->TWI_CR & TWI_CR_SVDIS)!= TWI_CR_SVDIS, "Can't configure TWI slave mode"); -} - -/** - * \brief Sends a STOP condition on the TWI. - * \param pTwi Pointer to an Twi instance. - */ -void TWI_Stop(Twi *pTwi) -{ - SANITY_CHECK(pTwi); - pTwi->TWI_CR = TWI_CR_STOP; -} - -/** - * \brief Starts a read operation on the TWI bus with the specified slave, it returns - * immediately. Data must then be read using TWI_ReadByte() whenever a byte is - * available (poll using TWI_ByteReceived()). - * \param pTwi Pointer to an Twi instance. - * \param address Slave address on the bus. - * \param iaddress Optional internal address bytes. - * \param isize Number of internal address bytes. - */ -void TWI_StartRead( - Twi *pTwi, - uint8_t address, - uint32_t iaddress, - uint8_t isize) -{ - SANITY_CHECK(pTwi); - SANITY_CHECK((address & 0x80) == 0); - SANITY_CHECK((iaddress & 0xFF000000) == 0); - SANITY_CHECK(isize < 4); - - /* Set slave address and number of internal address bytes. */ - pTwi->TWI_MMR = 0; - pTwi->TWI_MMR = (isize << 8) | TWI_MMR_MREAD | (address << 16); - - /* Set internal address bytes */ - pTwi->TWI_IADR = 0; - pTwi->TWI_IADR = iaddress; - - /* Send START condition */ - pTwi->TWI_CR = TWI_CR_START; -} - -/** - * \brief Reads a byte from the TWI bus. The read operation must have been started - * using TWI_StartRead() and a byte must be available (check with TWI_ByteReceived()). - * \param pTwi Pointer to an Twi instance. - * \return byte read. - */ -uint8_t TWI_ReadByte(Twi *pTwi) -{ - SANITY_CHECK(pTwi); - - return pTwi->TWI_RHR; -} - -/** - * \brief Sends a byte of data to one of the TWI slaves on the bus. - * \note This function must be called once before TWI_StartWrite() with - * the first byte of data to send, then it shall be called repeatedly - * after that to send the remaining bytes. - * \param pTwi Pointer to an Twi instance. - * \param byte Byte to send. - */ -void TWI_WriteByte(Twi *pTwi, uint8_t byte) -{ - SANITY_CHECK(pTwi); - - pTwi->TWI_THR = byte; -} - -/** - * \brief Starts a write operation on the TWI to access the selected slave, then - * returns immediately. A byte of data must be provided to start the write; - * other bytes are written next. - * after that to send the remaining bytes. - * \param pTwi Pointer to an Twi instance. - * \param address Address of slave to acccess on the bus. - * \param iaddress Optional slave internal address. - * \param isize Number of internal address bytes. - * \param byte First byte to send. - */ -void TWI_StartWrite( - Twi *pTwi, - uint8_t address, - uint32_t iaddress, - uint8_t isize, - uint8_t byte) -{ - SANITY_CHECK(pTwi); - SANITY_CHECK((address & 0x80) == 0); - SANITY_CHECK((iaddress & 0xFF000000) == 0); - SANITY_CHECK(isize < 4); - - /* Set slave address and number of internal address bytes. */ - pTwi->TWI_MMR = 0; - pTwi->TWI_MMR = (isize << 8) | (address << 16); - - /* Set internal address bytes. */ - pTwi->TWI_IADR = 0; - pTwi->TWI_IADR = iaddress; - - /* Write first byte to send.*/ - TWI_WriteByte(pTwi, byte); -} - -/** - * \brief Check if a byte have been receiced from TWI. - * \param pTwi Pointer to an Twi instance. - * \return 1 if a byte has been received and can be read on the given TWI - * peripheral; otherwise, returns 0. This function resets the status register. - */ -uint8_t TWI_ByteReceived(Twi *pTwi) -{ - return ((pTwi->TWI_SR & TWI_SR_RXRDY) == TWI_SR_RXRDY); -} - -/** - * \brief Check if a byte have been sent to TWI. - * \param pTwi Pointer to an Twi instance. - * \return 1 if a byte has been sent so another one can be stored for - * transmission; otherwise returns 0. This function clears the status register. - */ -uint8_t TWI_ByteSent(Twi *pTwi) -{ - return ((pTwi->TWI_SR & TWI_SR_TXRDY) == TWI_SR_TXRDY); -} - -/** - * \brief Check if current transmission is complet. - * \param pTwi Pointer to an Twi instance. - * \return 1 if the current transmission is complete (the STOP has been sent); - * otherwise returns 0. - */ -uint8_t TWI_TransferComplete(Twi *pTwi) -{ - return ((pTwi->TWI_SR & TWI_SR_TXCOMP) == TWI_SR_TXCOMP); -} - -/** - * \brief Enables the selected interrupts sources on a TWI peripheral. - * \param pTwi Pointer to an Twi instance. - * \param sources Bitwise OR of selected interrupt sources. - */ -void TWI_EnableIt(Twi *pTwi, uint32_t sources) -{ - SANITY_CHECK(pTwi); - SANITY_CHECK((sources & 0xFFFFF088) == 0); - - pTwi->TWI_IER = sources; -} - -/** - * \brief Disables the selected interrupts sources on a TWI peripheral. - * \param pTwi Pointer to an Twi instance. - * \param sources Bitwise OR of selected interrupt sources. - */ -void TWI_DisableIt(Twi *pTwi, uint32_t sources) -{ - SANITY_CHECK(pTwi); - SANITY_CHECK((sources & 0xFFFFF088) == 0); - - pTwi->TWI_IDR = sources; -} - -/** - * \brief Get the current status register of the given TWI peripheral. - * \note This resets the internal value of the status register, so further - * read may yield different values. - * \param pTwi Pointer to an Twi instance. - * \return TWI status register. - */ -uint32_t TWI_GetStatus(Twi *pTwi) -{ - SANITY_CHECK(pTwi); - - return pTwi->TWI_SR; -} - -/** - * \brief Returns the current status register of the given TWI peripheral, but - * masking interrupt sources which are not currently enabled. - * \note This resets the internal value of the status register, so further - * read may yield different values. - * \param pTwi Pointer to an Twi instance. - */ -uint32_t TWI_GetMaskedStatus(Twi *pTwi) -{ - uint32_t status; - - SANITY_CHECK(pTwi); - - status = pTwi->TWI_SR; - status &= pTwi->TWI_IMR; - - return status; -} - -/** - * \brief Sends a STOP condition. STOP Condition is sent just after completing - * the current byte transmission in master read mode. - * \param pTwi Pointer to an Twi instance. - */ -void TWI_SendSTOPCondition(Twi *pTwi) -{ - SANITY_CHECK(pTwi); - - pTwi->TWI_CR |= TWI_CR_STOP; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/twi/twi.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/twi/twi.h deleted file mode 100644 index a23740486..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/twi/twi.h +++ /dev/null @@ -1,95 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Interface for configuration the Two Wire Interface (TWI) peripheral. - * - */ - -#ifndef TWI_H -#define TWI_H - -/*---------------------------------------------------------------------------- - * Macros - *----------------------------------------------------------------------------*/ -/* Returns 1 if the TXRDY bit (ready to transmit data) is set in the given status register value.*/ -#define TWI_STATUS_TXRDY(status) ((status & TWI_SR_TXRDY) == TWI_SR_TXRDY) - -/* Returns 1 if the RXRDY bit (ready to receive data) is set in the given status register value.*/ -#define TWI_STATUS_RXRDY(status) ((status & TWI_SR_RXRDY) == TWI_SR_RXRDY) - -/* Returns 1 if the TXCOMP bit (transfer complete) is set in the given status register value.*/ -#define TWI_STATUS_TXCOMP(status) ((status & TWI_SR_TXCOMP) == TWI_SR_TXCOMP) - -/*---------------------------------------------------------------------------- - * External function - *----------------------------------------------------------------------------*/ - -extern void TWI_ConfigureMaster(Twi *pTwi, uint32_t twck, uint32_t mck); - -extern void TWI_ConfigureSlave(Twi *pTwi, uint8_t slaveAddress); - -extern void TWI_Stop(Twi *pTwi); - -extern void TWI_StartRead( - Twi *pTwi, - uint8_t address, - uint32_t iaddress, - uint8_t isize); - -extern uint8_t TWI_ReadByte(Twi *pTwi); - -extern void TWI_WriteByte(Twi *pTwi, uint8_t byte); - -extern void TWI_StartWrite( - Twi *pTwi, - uint8_t address, - uint32_t iaddress, - uint8_t isize, - uint8_t byte); - -extern uint8_t TWI_ByteReceived(Twi *pTwi); - -extern uint8_t TWI_ByteSent(Twi *pTwi); - -extern uint8_t TWI_TransferComplete(Twi *pTwi); - -extern void TWI_EnableIt(Twi *pTwi, uint32_t sources); - -extern void TWI_DisableIt(Twi *pTwi, uint32_t sources); - -extern uint32_t TWI_GetStatus(Twi *pTwi); - -extern uint32_t TWI_GetMaskedStatus(Twi *pTwi); - -extern void TWI_SendSTOPCondition(Twi *pTwi); - -#endif //#ifndef TWI_H diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/twi/twid.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/twi/twid.c deleted file mode 100644 index 6d1774de3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/twi/twid.c +++ /dev/null @@ -1,342 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - - - - - - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "twid.h" -#include -#include -#include - -/*---------------------------------------------------------------------------- - * Definition - *----------------------------------------------------------------------------*/ -#define TWITIMEOUTMAX 50000 - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - -/** TWI driver callback function.*/ -typedef void (*TwiCallback)(Async *); - -/** TWI asynchronous transfer descriptor.*/ -typedef struct _AsyncTwi { - - /** Asynchronous transfer status. */ - volatile uint8_t status; - // Callback function to invoke when transfer completes or fails.*/ - TwiCallback callback; - /** Pointer to the data buffer.*/ - uint8_t *pData; - /** Total number of bytes to transfer.*/ - uint32_t num; - /** Number of already transferred bytes.*/ - uint32_t transferred; - -} AsyncTwi; - -/*---------------------------------------------------------------------------- - * Global functions - *----------------------------------------------------------------------------*/ -/** - * \brief Initializes a TWI driver instance, using the given TWI peripheral. - * \note The peripheral must have been initialized properly before calling this function. - * \param pTwid Pointer to the Twid instance to initialize. - * \param pTwi Pointer to the TWI peripheral to use. - */ -void TWID_Initialize(Twid *pTwid, Twi *pTwi) -{ - TRACE_DEBUG("TWID_Initialize()\n\r"); - SANITY_CHECK(pTwid); - SANITY_CHECK(pTwi); - - /* Initialize driver. */ - pTwid->pTwi = pTwi; - pTwid->pTransfer = 0; -} - - -/** - * \brief Interrupt handler for a TWI peripheral. Manages asynchronous transfer - * occuring on the bus. This function MUST be called by the interrupt service - * routine of the TWI peripheral if asynchronous read/write are needed. - * \param pTwid Pointer to a Twid instance. - */ -void TWID_Handler(Twid *pTwid) -{ - uint8_t status; - AsyncTwi *pTransfer = (AsyncTwi *) pTwid->pTransfer; - Twi *pTwi = pTwid->pTwi; - - SANITY_CHECK(pTwid); - - /* Retrieve interrupt status */ - status = TWI_GetMaskedStatus(pTwi); - - /* Byte received */ - if (TWI_STATUS_RXRDY(status)) { - - pTransfer->pData[pTransfer->transferred] = TWI_ReadByte(pTwi); - pTransfer->transferred++; - - /* check for transfer finish */ - if (pTransfer->transferred == pTransfer->num) { - - TWI_DisableIt(pTwi, TWI_IDR_RXRDY); - TWI_EnableIt(pTwi, TWI_IER_TXCOMP); - } - /* Last byte? */ - else if (pTransfer->transferred == (pTransfer->num - 1)) { - - TWI_Stop(pTwi); - } - } - /* Byte sent*/ - else if (TWI_STATUS_TXRDY(status)) { - - /* Transfer finished ? */ - if (pTransfer->transferred == pTransfer->num) { - - TWI_DisableIt(pTwi, TWI_IDR_TXRDY); - TWI_EnableIt(pTwi, TWI_IER_TXCOMP); - TWI_SendSTOPCondition(pTwi); - } - /* Bytes remaining */ - else { - - TWI_WriteByte(pTwi, pTransfer->pData[pTransfer->transferred]); - pTransfer->transferred++; - } - } - /* Transfer complete*/ - else if (TWI_STATUS_TXCOMP(status)) { - - TWI_DisableIt(pTwi, TWI_IDR_TXCOMP); - pTransfer->status = 0; - if (pTransfer->callback) { - - pTransfer->callback((Async *) pTransfer); - } - pTwid->pTransfer = 0; - } -} - -/** - * \brief Asynchronously reads data from a slave on the TWI bus. An optional - * callback function is triggered when the transfer is complete. - * \param pTwid Pointer to a Twid instance. - * \param address TWI slave address. - * \param iaddress Optional slave internal address. - * \param isize Internal address size in bytes. - * \param pData Data buffer for storing received bytes. - * \param num Number of bytes to read. - * \param pAsync Asynchronous transfer descriptor. - * \return 0 if the transfer has been started; otherwise returns a TWI error code. - */ -uint8_t TWID_Read( - Twid *pTwid, - uint8_t address, - uint32_t iaddress, - uint8_t isize, - uint8_t *pData, - uint32_t num, - Async *pAsync) -{ - Twi *pTwi = pTwid->pTwi; - AsyncTwi *pTransfer = (AsyncTwi *) pTwid->pTransfer; - uint32_t timeout; - - SANITY_CHECK(pTwid); - SANITY_CHECK((address & 0x80) == 0); - SANITY_CHECK((iaddress & 0xFF000000) == 0); - SANITY_CHECK(isize < 4); - - /* Check that no transfer is already pending*/ - if (pTransfer) { - - TRACE_ERROR("TWID_Read: A transfer is already pending\n\r"); - return TWID_ERROR_BUSY; - } - - /* Set STOP signal if only one byte is sent*/ - if (num == 1) { - - TWI_Stop(pTwi); - } - - /* Asynchronous transfer*/ - if (pAsync) { - - /* Update the transfer descriptor */ - pTwid->pTransfer = pAsync; - pTransfer = (AsyncTwi *) pAsync; - pTransfer->status = ASYNC_STATUS_PENDING; - pTransfer->pData = pData; - pTransfer->num = num; - pTransfer->transferred = 0; - - /* Enable read interrupt and start the transfer */ - TWI_EnableIt(pTwi, TWI_IER_RXRDY); - TWI_StartRead(pTwi, address, iaddress, isize); - } - /* Synchronous transfer*/ - else { - - /* Start read*/ - TWI_StartRead(pTwi, address, iaddress, isize); - - /* Read all bytes, setting STOP before the last byte*/ - while (num > 0) { - - /* Last byte ?*/ - if (num == 1) { - - TWI_Stop(pTwi); - } - - /* Wait for byte then read and store it*/ - timeout = 0; - while( !TWI_ByteReceived(pTwi) && (++timeoutpTwi; - AsyncTwi *pTransfer = (AsyncTwi *) pTwid->pTransfer; - uint32_t timeout; - - SANITY_CHECK(pTwi); - SANITY_CHECK((address & 0x80) == 0); - SANITY_CHECK((iaddress & 0xFF000000) == 0); - SANITY_CHECK(isize < 4); - - /* Check that no transfer is already pending */ - if (pTransfer) { - - TRACE_ERROR("TWI_Write: A transfer is already pending\n\r"); - return TWID_ERROR_BUSY; - } - - /* Asynchronous transfer */ - if (pAsync) { - - /* Update the transfer descriptor */ - pTwid->pTransfer = pAsync; - pTransfer = (AsyncTwi *) pAsync; - pTransfer->status = ASYNC_STATUS_PENDING; - pTransfer->pData = pData; - pTransfer->num = num; - pTransfer->transferred = 1; - - /* Enable write interrupt and start the transfer */ - TWI_StartWrite(pTwi, address, iaddress, isize, *pData); - TWI_EnableIt(pTwi, TWI_IER_TXRDY); - } - /* Synchronous transfer*/ - else { - - // Start write - TWI_StartWrite(pTwi, address, iaddress, isize, *pData++); - num--; - - /* Send all bytes */ - while (num > 0) { - - /* Wait before sending the next byte */ - timeout = 0; - while( !TWI_ByteSent(pTwi) && (++timeout -#include - -/*---------------------------------------------------------------------------- - * Definition - *----------------------------------------------------------------------------*/ - -/** TWI driver is currently busy. */ -#define TWID_ERROR_BUSY 1 - -/*---------------------------------------------------------------------------- - * Types - *----------------------------------------------------------------------------*/ - -/** TWI driver structure. Holds the internal state of the driver.*/ -typedef struct _Twid { - /** Pointer to the underlying TWI peripheral.*/ - Twi *pTwi; - /** Current asynchronous transfer being processed.*/ - Async *pTransfer; - -} Twid; - -/*---------------------------------------------------------------------------- - * Export functions - *----------------------------------------------------------------------------*/ -extern void TWID_Initialize(Twid *pTwid, Twi *pTwi); - -extern void TWID_Handler(Twid *pTwid); - -extern uint8_t TWID_Read( - Twid *pTwid, - uint8_t address, - uint32_t iaddress, - uint8_t isize, - uint8_t *pData, - uint32_t num, - Async *pAsync); - -extern uint8_t TWID_Write( - Twid *pTwid, - uint8_t address, - uint32_t iaddress, - uint8_t isize, - uint8_t *pData, - uint32_t num, - Async *pAsync); - -#endif //#ifndef TWID_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/usart/uart_console.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/usart/uart_console.c deleted file mode 100644 index 07eaeec38..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/usart/uart_console.c +++ /dev/null @@ -1,288 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implements UART console. - * - */ - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include -#include -#include -#include -#include -#include - -#include "usart/uart_console.h" - -/*---------------------------------------------------------------------------- - * Definitions - *----------------------------------------------------------------------------*/ - -/** Console baudrate always using 115200. */ -#define CONSOLE_BAUDRATE 115200 -/** Usart Hw interface used by the console (UART0). */ -#define CONSOLE_USART UART0 -/** Usart Hw ID used by the console (UART0). */ -#define CONSOLE_ID ID_UART0 -/** Pins description corresponding to Rxd,Txd, (UART pins) */ -#define CONSOLE_PINS {PINS_UART} - -/*---------------------------------------------------------------------------- - * Variables - *----------------------------------------------------------------------------*/ - -/** Is Console Initialized. */ -static uint8_t isConsolInitialized = 0; - -/** - * \brief Configures an USART peripheral with the specified parameters. - * - * \param baudrate Baudrate at which the USART should operate (in Hz). - * \param masterClock Frequency of the system master clock (in Hz). - */ -static void UART_Configure( uint32_t baudrate, - uint32_t masterClock) -{ - const Pin pPins[] = CONSOLE_PINS; - Uart *pUart = CONSOLE_USART; - - /* Configure PIO */ - PIO_Configure(pPins, PIO_LISTSIZE(pPins)); - - /* Configure PMC */ - PMC->PMC_PCER0 = 1 << CONSOLE_ID; - - /* Reset and disable receiver & transmitter */ - pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX - | UART_CR_RXDIS | UART_CR_TXDIS; - - /* Configure mode */ - pUart->UART_MR = (0x4 << 9); /* TODO: Change with new symbols: AT91C_UART_CHRL_8_BITS | AT91C_UART_PAR_NONE */ - - /* Configure baudrate */ - /* Asynchronous, no oversampling */ - pUart->UART_BRGR = (masterClock / baudrate) / 16; - - /* Disable PDC channel */ - pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS; - - /* Enable receiver and transmitter */ - pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; - - isConsolInitialized = 1; -} - -/** - * \brief Outputs a character on the UART line. - * - * \note This function is synchronous (i.e. uses polling). - * \param c Character to send. - */ -void UART_PutChar(uint8_t c) -{ - Uart *pUart = CONSOLE_USART; - - if (!isConsolInitialized) - UART_Configure(CONSOLE_BAUDRATE, BOARD_MCK); - - /* Wait for the transmitter to be ready */ - while ((pUart->UART_SR & UART_SR_TXEMPTY) == 0); - - /* Send character */ - pUart->UART_THR = c; - -} - -/** - * \brief Input a character from the UART line. - * - * \note This function is synchronous - * \return character received. - */ -uint8_t UART_GetChar(void) -{ - Uart *pUart = CONSOLE_USART; - - if (!isConsolInitialized) - UART_Configure(CONSOLE_BAUDRATE, BOARD_MCK); - - while((pUart->UART_SR & UART_SR_RXRDY) == 0); - return pUart->UART_RHR; -} - -/** - * \brief Check if there is Input from UART line. - * - * \return true if there is Input. - */ -bool UART_IsRxReady(void) -{ - Uart *pUart = CONSOLE_USART; - - if (!isConsolInitialized) - UART_Configure(CONSOLE_BAUDRATE, BOARD_MCK); - - return (pUart->UART_SR & UART_SR_RXRDY) > 0; -} - -/* \cond NOFPUT */ -#ifndef NOFPUT -#include -#include -/** - * \brief Implementation of fputc using the UART as the standard output. Required - * for printf(). - * - * \param c Character to write. - * \param pStream Output stream. - * - * \return The character written if successful, or -1 if the output stream is - * not stdout or stderr. - */ -int fputc ( int c, FILE * pStream ) -{ - if ((pStream == stdout) || (pStream == stderr)) { - UART_PutChar(c); - return c; - } - else { - - return EOF; - } -} - -/** - * \brief Implementation of fputs using the UART as the standard output. Required - * for printf(). Does NOT currently use the PDC. - * - * \param pStr String to write. - * \param pStream Output stream. - * - * \return Number of characters written if successful, or -1 if the output - * stream is not stdout or stderr. - */ -signed int fputs(const char *pStr, FILE *pStream) -{ - signed int num = 0; - - while (*pStr != 0) { - - if (fputc(*pStr, pStream) == -1) { - - return -1; - } - num++; - pStr++; - } - - return num; -} - -#undef putchar - -/** - * \brief Outputs a character on the UART. - * - * \param c Character to output. - * - * \return The character that was output. - */ -signed int putchar(signed int c) -{ - return fputc(c, stdout); -} - -/* The char which has been ungotten, or EOF. */ -static int _UngetChar = EOF; - -/** - * \brief Implementation of fputc using the UART as the standard output. Required - * for printf(). - * - * \param c Character to write. - * \param pStream Output stream. - * - * \return The character written if successful, or -1 if the output stream is - * not stdout or stderr. - */ -int fgetc (FILE * pStream ) -{ - int c; - - if (pStream == stdin) { - c = UART_GetChar(); - return c; - } - else { - - return EOF; - } -} - -#undef getchar -/** - * \brief Get a character from UART. - * - * \return The character received. - */ -signed int getchar(void) -{ - if (_UngetChar != EOF) - { - int res = _UngetChar; - _UngetChar = EOF; - return res; - } - else - { - return fgetc(stdin); - } -} - -#undef __ungetchar -/** - * \brief Unget a character from stdin. - * - * \return The unget character. - */ -signed int __ungetchar(int c) -{ - _UngetChar = c; - return c; -} - -#endif /* #ifndef NOFPUT */ -/* \endcond */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/usart/uart_console.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/usart/uart_console.h deleted file mode 100644 index dfa192178..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/usart/uart_console.h +++ /dev/null @@ -1,38 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - - -#ifndef UART_CONSOLE_H_ -#define UART_CONSOLE_H_ - -extern void UART_PutChar(uint8_t c); -extern uint8_t UART_GetChar(void); -extern bool UART_IsRxReady(void); - -#endif /* UART_CONSOLE_H_ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/usart/usart.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/usart/usart.c deleted file mode 100644 index 5aa10e5dd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/usart/usart.c +++ /dev/null @@ -1,395 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** \addtogroup usart_module Working with USART - * The USART driver provides the interface to configure and use the USART peripheral.\n - * - * The USART supports several kinds of comminication modes such as full-duplex asynchronous/ - * synchronous serial commnunication,RS485 with driver control signal,ISO7816,SPI and Test modes. - * - * To start a USART transfer with \ref AT91SAM3S_PDC "PDC" support, the user could follow these steps: - *
    - *
  • Configure USART with expected mode and baudrate(see \ref USART_Configure), which could be done by: - * -# Resetting and disabling transmitter and receiver by setting US_CR(Control Register).
  • - * -# Conifguring the USART in a specific mode by setting USART_MODE bits in US_MR(Mode Register) - * -# Setting baudrate which is different from mode to mode. - - *
  • Enable transmitter or receiver respectively by set US_CR_TXEN or US_CR_RXEN in US_CR.
  • - *
  • Read from or write to the peripheral with \ref USART_ReadBuffer or \ref USART_WriteBuffer. - These operations could be done by polling or interruption.
  • - *
  • For polling, check the status bit US_CSR_ENDRX/US_CSR_RXBUFF (READ) or US_CSR_ENDTX/ - US_CSR_TXBUFE (WRITE).
  • - *
  • For interruption,"enable" the status bit through US_IER and - realize the hanler with USARTx_IrqHandler according to IRQ vector - table which is defined in board_cstartup_.c - To enable the interruption of USART,it should be configured with priority and enabled first through - NVIC .
  • - *
- * - * For more accurate information, please look at the USART section of the - * Datasheet. - * - * Related files :\n - * \ref usart.c\n - * \ref usart.h\n -*/ - - - -/** - * \file - * - * Implementation of USART (Universal Synchronous Asynchronous Receiver Transmitter) - * controller. - * - */ -/*------------------------------------------------------------------------------ - * Headers - *------------------------------------------------------------------------------*/ -#include - -#include "usart.h" -#include -#include - -/*---------------------------------------------------------------------------- - * Local definitions - *----------------------------------------------------------------------------*/ - - -/*------------------------------------------------------------------------------ - * Exported functions - *------------------------------------------------------------------------------*/ - -/** - * \brief Configures an USART peripheral with the specified parameters. - * - * - * \param usart Pointer to the USART peripheral to configure. - * \param mode Desired value for the USART mode register (see the datasheet). - * \param baudrate Baudrate at which the USART should operate (in Hz). - * \param masterClock Frequency of the system master clock (in Hz). - */ -void USART_Configure(Usart *usart, - uint32_t mode, - uint32_t baudrate, - uint32_t masterClock) -{ - /* Reset and disable receiver & transmitter*/ - usart->US_CR = US_CR_RSTRX | US_CR_RSTTX - | US_CR_RXDIS | US_CR_TXDIS; - - /* Configure mode*/ - usart->US_MR = mode; - - /* Configure baudrate*/ - /* Asynchronous, no oversampling*/ - if (((mode & US_MR_SYNC__CPHA) == 0) - && ((mode & US_MR_OVER) == 0)) { - - usart->US_BRGR = (masterClock / baudrate) / 16; - } - /* TODO other modes*/ -} -/** - * \brief Enables or disables the transmitter of an USART peripheral. - * - * - * \param usart Pointer to an USART peripheral - * \param enabled If true, the transmitter is enabled; otherwise it is - * disabled. - */ -void USART_SetTransmitterEnabled(Usart *usart, uint8_t enabled) -{ - if (enabled) { - - usart->US_CR = US_CR_TXEN; - } - else { - - usart->US_CR = US_CR_TXDIS; - } -} - -/** - * \brief Enables or disables the receiver of an USART peripheral - * - * - * \param usart Pointer to an USART peripheral - * \param enabled If true, the receiver is enabled; otherwise it is disabled. - */ -void USART_SetReceiverEnabled(Usart *usart, - uint8_t enabled) -{ - if (enabled) { - - usart->US_CR = US_CR_RXEN; - } - else { - - usart->US_CR = US_CR_RXDIS; - } -} - -/** - * \brief Sends one packet of data through the specified USART peripheral. This - * function operates synchronously, so it only returns when the data has been - * actually sent. - * - * - * \param usart Pointer to an USART peripheral. - * \param data Data to send including 9nth bit and sync field if necessary (in - * the same format as the US_THR register in the datasheet). - * \param timeOut Time out value (0 = no timeout). - */ -void USART_Write( - Usart *usart, - uint16_t data, - volatile uint32_t timeOut) -{ - if (timeOut == 0) { - - while ((usart->US_CSR & US_CSR_TXEMPTY) == 0); - } - else { - - while ((usart->US_CSR & US_CSR_TXEMPTY) == 0) { - - if (timeOut == 0) { - - TRACE_ERROR("USART_Write: Timed out.\n\r"); - return; - } - timeOut--; - } - } - - usart->US_THR = data; -} - -/** - * \brief Sends the contents of a data buffer through the specified USART peripheral. - * This function returns immediately (1 if the buffer has been queued, 0 - * otherwise); poll the ENDTX and TXBUFE bits of the USART status register - * to check for the transfer completion. - * - * \param usart Pointer to an USART peripheral. - * \param buffer Pointer to the data buffer to send. - * \param size Size of the data buffer (in bytes). - */ -uint8_t USART_WriteBuffer( - Usart *usart, - void *buffer, - uint32_t size) -{ - /* Check if the first PDC bank is free*/ - if ((usart->US_TCR == 0) && (usart->US_TNCR == 0)) { - - usart->US_TPR = (uint32_t) buffer; - usart->US_TCR = size; - usart->US_PTCR = US_PTCR_TXTEN; - - return 1; - } - /* Check if the second PDC bank is free*/ - else if (usart->US_TNCR == 0) { - - usart->US_TNPR = (uint32_t) buffer; - usart->US_TNCR = size; - - return 1; - } - else { - - return 0; - } -} - - -/** - * \brief Reads and return a packet of data on the specified USART peripheral. This - * function operates asynchronously, so it waits until some data has been - * received. - * - * \param usart Pointer to an USART peripheral. - * \param timeOut Time out value (0 -> no timeout). - */ -uint16_t USART_Read( - Usart *usart, - volatile uint32_t timeOut) -{ - if (timeOut == 0) { - - while ((usart->US_CSR & US_CSR_RXRDY) == 0); - } - else { - - while ((usart->US_CSR & US_CSR_RXRDY) == 0) { - - if (timeOut == 0) { - - TRACE_ERROR("USART_Read: Timed out.\n\r"); - return 0; - } - timeOut--; - } - } - - return usart->US_RHR; -} - -/** - * \brief Reads data from an USART peripheral, filling the provided buffer until it - * becomes full. This function returns immediately with 1 if the buffer has - * been queued for transmission; otherwise 0. - * - * \param usart Pointer to an USART peripheral. - * \param buffer Pointer to the buffer where the received data will be stored. - * \param size Size of the data buffer (in bytes). - */ -uint8_t USART_ReadBuffer(Usart *usart, - void *buffer, - uint32_t size) -{ - /* Check if the first PDC bank is free*/ - if ((usart->US_RCR == 0) && (usart->US_RNCR == 0)) { - - usart->US_RPR = (uint32_t) buffer; - usart->US_RCR = size; - usart->US_PTCR = US_PTCR_RXTEN; - - return 1; - } - /* Check if the second PDC bank is free*/ - else if (usart->US_RNCR == 0) { - - usart->US_RNPR = (uint32_t) buffer; - usart->US_RNCR = size; - - return 1; - } - else { - - return 0; - } -} - -/** - * \brief Returns 1 if some data has been received and can be read from an USART; - * otherwise returns 0. - * - * \param usart Pointer to an Usart instance. - */ -uint8_t USART_IsDataAvailable(Usart *usart) -{ - if ((usart->US_CSR & US_CSR_RXRDY) != 0) { - - return 1; - } - else { - - return 0; - } -} - -/** - * \brief Sets the filter value for the IRDA demodulator. - * - * \param pUsart Pointer to an Usart instance. - * \param filter Filter value. - */ -void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter) -{ - SANITY_CHECK(pUsart); - - pUsart->US_IF = filter; -} - -/** - * \brief Sends one packet of data through the specified USART peripheral. This - * function operates synchronously, so it only returns when the data has been - * actually sent. - * - * \param usart Pointer to an USART peripheral. - * \param c Character to send - */ -void USART_PutChar( - Usart *usart, - uint8_t c) -{ - /* Wait for the transmitter to be ready*/ - while ((usart->US_CSR & US_CSR_TXEMPTY) == 0); - - /* Send character*/ - usart->US_THR = c; - - /* Wait for the transfer to complete*/ - while ((usart->US_CSR & US_CSR_TXEMPTY) == 0); -} - -/** - * \brief Return 1 if a character can be read in USART - */ -uint32_t USART_IsRxReady(Usart *usart) -{ - return (usart->US_CSR & US_CSR_RXRDY); -} -/** - * \brief Get present status - */ -uint32_t USART_GetStatus(Usart *usart) -{ - return usart->US_CSR; -} -/** - * \brief Enable interrupt - */ -void USART_EnableIt(Usart *usart,uint32_t mode) -{ - usart->US_IER = mode; -} -/** - * \brief Disable interrupt - */ -void USART_DisableIt(Usart *usart,uint32_t mode) -{ - usart->US_IDR = mode; -} -/** - * \brief Reads and returns a character from the USART. - * - * \note This function is synchronous (i.e. uses polling). - * \param usart Pointer to an USART peripheral. - * \return Character received. - */ -uint8_t USART_GetChar(Usart *usart) -{ - while ((usart->US_CSR & US_CSR_RXRDY) == 0); - return usart->US_RHR; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/usart/usart.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/usart/usart.h deleted file mode 100644 index 8c50f87eb..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/usart/usart.h +++ /dev/null @@ -1,129 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * \par Purpose - * - * This module provides several definitions and methods for using an USART - * peripheral. - * - * \par Usage - * - * -# Enable the USART peripheral clock in the PMC. - * -# Enable the required USART PIOs (see pio.h). - * -# Configure the UART by calling USART_Configure. - * -# Enable the transmitter and/or the receiver of the USART using - * USART_SetTransmitterEnabled and USART_SetReceiverEnabled. - * -# Send data through the USART using the USART_Write and - * USART_WriteBuffer methods. - * -# Receive data from the USART using the USART_Read and - * USART_ReadBuffer functions; the availability of data can be polled - * with USART_IsDataAvailable. - * -# Disable the transmitter and/or the receiver of the USART with - * USART_SetTransmitterEnabled and USART_SetReceiverEnabled. - */ - -#ifndef USART_H -#define USART_H - -/*------------------------------------------------------------------------------ - * Headers - *------------------------------------------------------------------------------*/ - -#include - -/*------------------------------------------------------------------------------ - * Definitions - *------------------------------------------------------------------------------*/ - -/** \section USART_mode USART modes - * This section lists several common operating modes for an USART peripheral. - * - * \b Modes - * - USART_MODE_ASYNCHRONOUS - * - USART_MODE_IRDA - */ - -/** Basic asynchronous mode, i.e. 8 bits no parity.*/ -#define USART_MODE_ASYNCHRONOUS (AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE) - -/** IRDA mode*/ -#define USART_MODE_IRDA (AT91C_US_USMODE_IRDA | AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_FILTER) - - -/*------------------------------------------------------------------------------*/ -/* Exported functions*/ -/*------------------------------------------------------------------------------*/ - -extern void USART_Configure( - Usart *usart, - uint32_t mode, - uint32_t baudrate, - uint32_t masterClock); -extern uint32_t USART_GetStatus(Usart *usart); -extern void USART_EnableIt(Usart *usart,uint32_t mode); -extern void USART_DisableIt(Usart *usart,uint32_t mode); -extern void USART_SetTransmitterEnabled(Usart *usart, uint8_t enabled); - -extern void USART_SetReceiverEnabled(Usart *usart, uint8_t enabled); - -extern void USART_Write( - Usart *usart, - uint16_t data, - volatile uint32_t timeOut); - -extern uint8_t USART_WriteBuffer( - Usart *usart, - void *buffer, - uint32_t size); - -extern uint16_t USART_Read( - Usart *usart, - volatile uint32_t timeOut); - -extern uint8_t USART_ReadBuffer( - Usart *usart, - void *buffer, - uint32_t size); - -extern uint8_t USART_IsDataAvailable(Usart *usart); - -extern void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter); - -extern void USART_PutChar(Usart *usart, uint8_t c); - -extern uint32_t USART_IsRxReady(Usart *usart); - -extern uint8_t USART_GetChar(Usart *usart); - - -#endif /*#ifndef USART_H*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/assert.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/assert.h deleted file mode 100644 index 5c21781de..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/assert.h +++ /dev/null @@ -1,114 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// Definition of the ASSERT() and SANITY_CHECK() macros, which are used for -/// runtime condition & parameter verifying. -/// -/// !Usage -/// -/// -# Use ASSERT() in your code to check the value of function parameters, -/// return values, etc. *Warning:* the ASSERT() condition must not have -/// any side-effect; otherwise, the program may not work properly -/// anymore when assertions are disabled. -/// -# Use SANITY_CHECK() to perform checks with a default error message -/// (outputs the file and line number where the error occured). This -/// reduces memory overhead caused by assertion error strings. -/// -# Initialize the dbgu to see failed assertions at run-time. -/// -# Assertions can be entirely disabled by defining the NOASSERT symbol -/// at compilation time. -//------------------------------------------------------------------------------ - -#ifndef ASSERT_H -#define ASSERT_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include -#include "trace.h" - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ -#if defined(NOASSERT) - #define ASSERT(...) - #define SANITY_CHECK(...) -#else - - #if (TRACE_LEVEL == 0) - /// Checks that the given condition is true, - /// otherwise stops the program execution. - /// \param condition Condition to verify. - #define ASSERT(condition, ...) { \ - if (!(condition)) { \ - while (1); \ - } \ - } - - /// Performs the same duty as the ASSERT() macro - /// \param condition Condition to verify. - #define SANITY_CHECK(condition) ASSERT(condition, ...) - - #else - /// Checks that the given condition is true, otherwise displays an error - /// message and stops the program execution. - /// \param condition Condition to verify. - #define ASSERT(condition, ...) { \ - if (!(condition)) { \ - printf("-F- ASSERT: "); \ - printf(__VA_ARGS__); \ - while (1); \ - } \ - } - #define SANITY_ERROR "Sanity check failed at %s:%d\n\r" - - /// Performs the same duty as the ASSERT() macro, except a default error - /// message is output if the condition is false. - /// \param condition Condition to verify. - #define SANITY_CHECK(condition) ASSERT(condition, SANITY_ERROR, __FILE__, __LINE__) - #endif -#endif - - - - - - - - - - -#endif //#ifndef ASSERT_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/bitbanding.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/bitbanding.h deleted file mode 100644 index 8ef5976cf..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/bitbanding.h +++ /dev/null @@ -1,108 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef BITBANDING_H -#define BITBANDING_H - -//------------------------------------------------------------------------------ -/// \file bitbanding.h -/// Include Defines & macros for bit-banding. -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Header files -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Global Macros -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \def IS_BITBAND_SRAM_ADDR(x) -/// \brief Check if the address is in bit banding sram region. -/// \note The address should be in area of 0x2000000 ~ 0x200FFFFF -/// \param x The address to check. -//------------------------------------------------------------------------------ -#define IS_BITBAND_SRAM_ADDR(x) \ - ( ((uint32_t)(x)) >= 0x20000000 && \ - ((uint32_t)(x)) < (0x20000000+0x100000) ) - -//------------------------------------------------------------------------------ -/// \def IS_BITBAND_PERIPH_ADDR(x) -/// \brief Check if the address is in bit banding peripheral region -/// \note The address should be in area of 0x4000000 ~ 0x400FFFFF -/// \param x The address to check -//------------------------------------------------------------------------------ -#define IS_BITBAND_PERIPH_ADDR(x) \ - ( ((uint32_t)(x)) >= 0x40000000 && \ - ((uint32_t)(x)) < (0x40000000+0x100000) ) - -//------------------------------------------------------------------------------ -/// \def BITBAND_ALIAS_ADDRESS(addr, bit) -/// \brief Calculate bit band alias address. -/// -/// Calculate the bit band alias address and return a pointer address to word. -/// \param addr The byte address of bitbanding bit. -/// \param bit The bit position of bitbanding bit. -/// \callergraph -//------------------------------------------------------------------------------ -#define BITBAND_ALIAS_ADDRESS(addr, bit) \ - ((volatile uint32_t*)((((uint32_t)(addr) & 0xF0000000) + 0x02000000) \ - +((((uint32_t)(addr)&0xFFFFF)*32)\ - +( (uint32_t)(bit)*4)))) - -//------------------------------------------------------------------------------ -/// \def WRITE_BITBANDING(addr32, bit, val) -/// \brief Bit write through bit banding. -/// \param addr32 32-bit aligned byte address where the bit exists. -/// \param bit Bit position. -/// \param val The value that the bit is set to. -/// \callergraph -//------------------------------------------------------------------------------ -#define WRITE_BITBANDING(addr32, bit, val) do {\ - *BITBAND_ALIAS_ADDRESS(addr32,bit) = (val); \ - } while (0); - -//------------------------------------------------------------------------------ -/// \def TOGGLE_BITBANDING(addr32, bit) -/// \brief Toggle bit through bit banding -/// \param addr32 32-bit aligned byte address where the bit exists. -/// \param bit Bit position. -//------------------------------------------------------------------------------ -#define TOGGLE_BITBANDING(addr32, bit) do {\ - volatile uint32_t * p = \ - BITBAND_ALIAS_ADDRESS(addr32,bit); \ - if (*p) *p = 0; \ - else *p = 1; \ - }while(0); - -#endif //#ifndef BITBANDING_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/bmp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/bmp.c deleted file mode 100644 index fe3058757..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/bmp.c +++ /dev/null @@ -1,322 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "bmp.h" -#include -#include - -#include - -//----------------------------------------------------------------------------- -// Define -//----------------------------------------------------------------------------- -/// BMP offset for header -#define IMAGE_OFFSET 0x100 - - -//------------------------------------------------------------------------------ -// Internal constants -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Internal types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Describe the BMP palette -//------------------------------------------------------------------------------ -struct BMPPaletteEntry { - - /// Blue value - unsigned char b; - /// Green value - unsigned char g; - /// Red value - unsigned char r; - /// Filler character value - unsigned char filler; -}; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Test if BMP is valid -/// \param file Buffer holding the file to examinate. -/// \return 1 if the header of a BMP file is valid; otherwise returns 0. -//------------------------------------------------------------------------------ -unsigned char BMP_IsValid(void *file) -{ - return ((struct BMPHeader *) file)->type == BMP_TYPE; -} - -//------------------------------------------------------------------------------ -/// Returns the size of a BMP image given at least its header (the file does -/// not have to be complete). -/// \param file Pointer to the buffer which holds the BMP file. -/// \return size of BMP image -//------------------------------------------------------------------------------ -unsigned int BMP_GetFileSize(void *file) -{ - return ((struct BMPHeader *) file)->fileSize; -} - -//----------------------------------------------------------------------------- -/// Write a BMP header -/// \param pAddressHeader Begin address of the BMP -/// \param bmpHSize BMP heigth size -/// \param bmpVSize BMP width size -/// \param bmpRgb Type of BMP (YUV or RGB) -/// \param nbByte_Pixels Number of byte per pixels -//----------------------------------------------------------------------------- -void WriteBMPheader(unsigned int* pAddressHeader, - unsigned int bmpHSize, - unsigned int bmpVSize, - unsigned char bmpRgb, - unsigned char nbByte_Pixels) -{ - unsigned int i; - unsigned int* fill; - struct BMPHeader *Header; - - fill = pAddressHeader; - for (i=0; itype = BMP_TYPE; - Header->fileSize = (bmpHSize * bmpVSize * nbByte_Pixels) + IMAGE_OFFSET; - Header->reserved1 = 0; - Header->reserved2 = 0; - Header->offset = IMAGE_OFFSET; - Header->headerSize = BITMAPINFOHEADER; - Header->width = bmpHSize; - Header->height = bmpVSize; - Header->planes = 1; - Header->bits = nbByte_Pixels * 8; - Header->compression = 0; - Header->imageSize = bmpHSize * bmpVSize * nbByte_Pixels; - Header->xresolution = 0; - Header->yresolution = 0; - Header->ncolours = 0; - Header->importantcolours = 0; -} - - -//------------------------------------------------------------------------------ -/// debug function, dislay BMP header -/// \param pAddressHeader Address of the BMP -//------------------------------------------------------------------------------ -void BMP_displayHeader(unsigned int* pAddressHeader) -{ - struct BMPHeader *header; - - header = (struct BMPHeader*) pAddressHeader; - - TRACE_INFO("BMP\n\r"); - TRACE_INFO("type 0x%X \n\r", header->type); - TRACE_INFO("fileSize %d \n\r", header->fileSize); - TRACE_INFO("reserved1 %d \n\r", header->reserved1); - TRACE_INFO("reserved2 %d \n\r", header->reserved2); - TRACE_INFO("offset %d \n\r", header->offset); - TRACE_INFO("headerSize %d \n\r", header->headerSize); - TRACE_INFO("width %d \n\r", header->width); - TRACE_INFO("height %d \n\r", header->height); - TRACE_INFO("planes %d \n\r", header->planes); - TRACE_INFO("bits %d \n\r", header->bits); - TRACE_INFO("compression %d \n\r", header->compression); - TRACE_INFO("imageSize %d \n\r", header->imageSize); - TRACE_INFO("xresolution %d \n\r", header->xresolution); - TRACE_INFO("yresolution %d \n\r", header->yresolution); - TRACE_INFO("ncolours %d \n\r", header->ncolours); - TRACE_INFO("importantcolours %d\n\r", header->importantcolours); -} - - -//------------------------------------------------------------------------------ -/// Loads a BMP image located at the given address, decodes it and stores the -/// resulting image inside the provided buffer. Image must have the specified -/// width & height. -/// If no buffer is provided, this function simply checks if it is able to -/// decode the image. -/// \param file Buffer which holds the BMP file. -/// \param buffer Buffer in which to store the decoded image. -/// \param width Buffer width in pixels. -/// \param height Buffer height in pixels. -/// \param bpp Number of bits per pixels that the buffer stores. -/// \return 0 if the image has been loaded; otherwise returns an error code. -//------------------------------------------------------------------------------ -unsigned char BMP_Decode( - void *file, - unsigned char *buffer, - unsigned int width, - unsigned int height, - unsigned char bpp) -{ - struct BMPHeader *header; - unsigned int i, j; - unsigned char r, g, b; - unsigned char *image; - - // Read header information - header = (struct BMPHeader *) file; - - // Verify that the file is valid - if (!BMP_IsValid(file)) { - - TRACE_ERROR("BMP_Decode: File type is not 'BM' (0x%04X).\n\r",header->type); - return 1; - } - - // Check that parameters match - if ((header->compression != 0) - || (header->width != width) - || (header->height != height)) { - - TRACE_ERROR("BMP_Decode: File format not supported\n\r"); - TRACE_ERROR(" -> .compression = %u\n\r", header->compression); - TRACE_ERROR(" -> .width = %u\n\r", header->width); - TRACE_ERROR(" -> .height = %u\n\r", header->height); - TRACE_ERROR(" -> .bits = %d\n\r", header->bits); - return 2; - } - - // Get image data - image = (unsigned char *) ((unsigned int) file + header->offset); - - // Check that the bpp resolution is supported - // Only a 24-bit output & 24- or 8-bit input are supported - if (bpp != 24) { - - TRACE_ERROR("BMP_Decode: Output resolution not supported\n\r"); - return 3; - } - else if (header->bits == 24) { - - // Decoding is ok - if (!buffer) return 0; - - // Get image data (swapping red & blue) - for (i=0; i < height; i++) { - for (j=0; j < width; j++) { - - r = image[((height - i - 1) * width + j) * 3 + 2]; - g = image[((height - i - 1) * width + j) * 3 + 1]; - b = image[((height - i - 1) * width + j) * 3]; - -#if defined(BOARD_LCD_RGB565) - // Interlacing - r = ((r << 1) & 0xF0) | ((g & 0x80) >> 4) | ((r & 0x80) >> 5); - g = (g << 1) & 0xF8; - b = b & 0xF8; - - buffer[(i * width + j) * 3] = b; - buffer[(i * width + j) * 3 + 1] = g; - buffer[(i * width + j) * 3 + 2] = r; - -#else - buffer[(i * width + j) * 3] = r; - buffer[(i * width + j) * 3 + 1] = g; - buffer[(i * width + j) * 3 + 2] = b; -#endif //#if defined(BOARD_LCD_RGB565) - } - } - } - else if (header->bits == 8) { - - // Decoding is ok - if (!buffer) return 0; - - // Retrieve palette - struct BMPPaletteEntry palette[256]; - memcpy(palette, - (unsigned char *) ((unsigned int) file + sizeof(struct BMPHeader)), - header->offset - sizeof(struct BMPHeader)); - - // Decode image (reversing row order) - for (i=0; i < height; i++) { - for (j=0; j < width; j++) { - - r = palette[image[(height - i - 1) * width + j]].r; - g = palette[image[(height - i - 1) * width + j]].g; - b = palette[image[(height - i - 1) * width + j]].b; - - buffer[(i * width + j) * 3] = r; - buffer[(i * width + j) * 3 + 1] = g; - buffer[(i * width + j) * 3 + 2] = b; - } - } - } - else { - - TRACE_ERROR("BMP_Decode: Input resolution not supported\n\r"); - TRACE_INFO("header->bits 0x%X \n\r", header->bits); - return 4; - } - - return 0; -} - -//------------------------------------------------------------------------------ -/// Convert RGB 565 to RGB 555 (RGB 555 is adapted to LCD) -/// \param fileSource Buffer which holds the RGB file -/// \param fileDestination Buffer in which to store the decoded image -/// \param width Buffer width in pixels. -/// \param height Buffer height in pixels. -/// \param bpp Number of bits per pixels that the buffer stores. -//------------------------------------------------------------------------------ -void RGB565toBGR555( - unsigned char *fileSource, - unsigned char *fileDestination, - unsigned int width, - unsigned int height, - unsigned char bpp) -{ - unsigned int i; - unsigned int j; - unsigned int row; - - for (i=0; i < height*(bpp/8); i++) { - row = (i*width*(bpp/8)); - for (j=0; j <= width*(bpp/8); j+=2) { - fileDestination[row+j] = ((fileSource[row+j+1]>>3)&0x1F) - | (fileSource[row+j]&0xE0); - fileDestination[row+j+1] = (fileSource[row+j+1]&0x03) - | ((fileSource[row+j]&0x1F)<<2); - } - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/bmp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/bmp.h deleted file mode 100644 index 81280b226..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/bmp.h +++ /dev/null @@ -1,130 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Utility for BMP -/// -//------------------------------------------------------------------------------ - -#ifndef BMP_H -#define BMP_H - -/// BMP magic number ('BM'). -#define BMP_TYPE 0x4D42 - -/// headerSize must be set to 40 -#define BITMAPINFOHEADER 40 - -//------------------------------------------------------------------------------ -// Exported types -//------------------------------------------------------------------------------ - -#ifdef __ICCARM__ // IAR -#pragma pack(1) // IAR -#define __attribute__(...) // IAR -#endif // IAR - -// BMP (Windows) Header Format -struct BMPHeader { - /// signature, must be 4D42 hex - unsigned short type; - /// size of BMP file in bytes (unreliable) - unsigned int fileSize; - /// reserved, must be zero - unsigned short reserved1; - /// reserved, must be zero - unsigned short reserved2; - /// offset to start of image data in bytes - unsigned int offset; - /// size of BITMAPINFOHEADER structure, must be 40 - unsigned int headerSize; - /// image width in pixels - unsigned int width; - /// image height in pixels - unsigned int height; - /// number of planes in the image, must be 1 - unsigned short planes; - /// number of bits per pixel (1, 4, 8, 16, 24, 32) - unsigned short bits; - /// compression type (0=none, 1=RLE-8, 2=RLE-4) - unsigned int compression; - /// size of image data in bytes (including padding) - unsigned int imageSize; - /// horizontal resolution in pixels per meter (unreliable) - unsigned int xresolution; - /// vertical resolution in pixels per meter (unreliable) - unsigned int yresolution; - /// number of colors in image, or zero - unsigned int ncolours; - /// number of important colors, or zero - unsigned int importantcolours; - -} __attribute__ ((packed)); // GCC - -#ifdef __ICCARM__ // IAR -#pragma pack() // IAR -#endif // IAR - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char BMP_IsValid(void *file); - -extern unsigned int BMP_GetFileSize(void *file); - -extern unsigned char BMP_Decode( - void *file, - unsigned char *buffer, - unsigned int width, - unsigned int height, - unsigned char bpp); - -extern void WriteBMPheader(unsigned int* pAddressHeader, - unsigned int bmpHSize, - unsigned int bmpVSize, - unsigned char bmpRgb, - unsigned char nbByte_Pixels); - -extern void BMP_displayHeader(unsigned int* pAddressHeader); - -extern void RGB565toBGR555( - unsigned char *fileSource, - unsigned char *fileDestination, - unsigned int width, - unsigned int height, - unsigned char bpp); - - -#endif //#ifndef BMP_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/clock.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/clock.c deleted file mode 100644 index c298fb799..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/clock.c +++ /dev/null @@ -1,259 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "clock.h" -#include -#include - -//------------------------------------------------------------------------------ -// Internal types -//------------------------------------------------------------------------------ -int currentConfig = 0; // 0 have to be the default configuration - -//------------------------------------------------------------------------------ -/// Describes a possible clock configuration (processor clock & master clock), -/// including the necessary register values. -//------------------------------------------------------------------------------ -struct ClockConfiguration { - - /// Processor clock frequency (in MHz). - unsigned short pck; - /// Master clock frequency (in MHz). - unsigned short mck; - /// CKGR_PLL reqister value. - unsigned int pllr; - /// PMC_MCKR register value. - unsigned int mckr; -}; - -//------------------------------------------------------------------------------ -// Internal variables -//------------------------------------------------------------------------------ - -// Clock configurations for the AT91SAM9263-EK -#if defined(at91sam9263) - -#define AT91C_CKGR_PLLR AT91C_CKGR_PLLAR -#define AT91C_PMC_LOCK AT91C_PMC_LOCKA - -static const struct ClockConfiguration clockConfigurations[] = { - // PCK = 200 MHz, MCK = 100 MHz - {200, 100, 0x206DBF09, 0x00000102}, - // PCK = 240 MHz, MCK = 120 MHz - {240, 120, 0x202BC003, 0x00000102}, - // PCK = 120 MHz, MCK = 120 MHz - {120, 120, 0x20156003, 0x00000002}, - // PCK = 96 MHz, MCK = 48 MHz - {96, 48, 0x2057400F, 0x00000102}, - // PCK = 48 MHz, MCK = 48 MHz - {48, 48, 0x2057400F, 0x00000006} -}; - -// Clock configurations for the AT91SAM9G20-EK -#elif defined(at91sam9g20) - -#define AT91C_CKGR_PLLR AT91C_CKGR_PLLAR -#define AT91C_PMC_LOCK AT91C_PMC_LOCKA - -static const struct ClockConfiguration clockConfigurations[] = { - - // PCK = 400 MHz, MCK = 133 MHz - {400, 133, 0x202A0101, 0x00001302}, - // PCK = 200 MHz, MCK = 100 MHz - {200, 100, 0x202A3F01, 0x0000010A}, - // PCK = 96 MHz, MCK = 48 MHz - {96, 48, 0x207C3F03, 0x0000010E}, - // PCK = 48 MHz, MCK = 48 MHz - {48, 48, 0x207C3F03, 0x00000012} -}; - -// Clock configurations for the AT91SAM9XE-EK, AT91SAM9261-EK -#elif defined(at91sam9xe128) || \ - defined(at91sam9xe256) || \ - defined(at91sam9xe512) || \ - defined(at91sam9261) - -#define AT91C_CKGR_PLLR AT91C_CKGR_PLLAR -#define AT91C_PMC_LOCK AT91C_PMC_LOCKA - -static const struct ClockConfiguration clockConfigurations[] = { - - // PCK = 200 MHz, MCK = 100 MHz - {200, 100, 0x208CBF0D, 0x00000102}, - // PCK = 100 MHz, MCK = 100 MHz - {100, 100, 0x20273F07, 0x00000002}, - // PCK = 96 MHz, MCK = 48 MHz - {96, 48, 0x20483F0E, 0x00000102}, - // PCK = 48 MHz, MCK = 48 MHz - {48, 48, 0x20483F0E, 0x00000006} -}; - -// Clock configurations for the AT91SAM9RL64-EK, AT91CAP9-DK, AT91CAP9-STK -#elif defined(at91sam9rl64) || \ - defined(at91cap9) - -#define AT91C_CKGR_PLLR AT91C_CKGR_PLLAR -#define AT91C_PMC_LOCK AT91C_PMC_LOCKA - -static const struct ClockConfiguration clockConfigurations[] = { - - // PCK = 200 MHz, MCK = 100 MHz - {200, 100, 0x2031BF03, 0x00000102}, - // PCK = 100 MHz, MCK = 100 MHz - {100, 100, 0x20183F03, 0x00000002}, - // PCK = 96 MHz, MCK = 48 MHz - {96, 48, 0x20073F01, 0x00000102}, - // PCK = 48 MHz, MCK = 48 MHz - {48, 48, 0x20073F01, 0x00000006} -}; - -// Clock configuration for the AT91SAM7X-EK, AT91SAM7S-EK, AT91SAM7SE-EK -#elif defined(at91sam7x128) || defined(at91sam7x256) || defined(at91sam7x512) \ - || defined(at91sam7xc128) || defined(at91sam7xc256) || defined(at91sam7xc512) \ - || defined(at91sam7s16) || defined(at91sam7s161) || defined(at91sam7s32) \ - || defined(at91sam7s321) || defined(at91sam7s64) || defined(at91sam7s128) \ - || defined(at91sam7s256) || defined(at91sam7s512) || defined(at91sam7se32) \ - || defined(at91sam7se256) || defined(at91sam7se512) - -static const struct ClockConfiguration clockConfigurations[] = { - - // PCK = 55 MHz, MCK = 55 MHz - {55, 55, 0x006A3F12, 0x00000007}, - // PCK = 48 MHz, MCK = 48 MHz - {48, 48, 0x00483F0E, 0x00000007}, -}; - -// Clock configuration for the AT91SAM7A3 -#elif defined(at91sam7a3) - -static const struct ClockConfiguration clockConfigurations[] = { - - // PCK = 60 MHz, MCK = 60 MHz - {60, 60, 0x000C3F02, 0x00000007}, - // PCK = 48 MHz, MCK = 48 MHz - {48, 48, 0x00483F0E, 0x00000007} -}; - -// No clock configuration -#else - #error No clock configuration for this board. -#endif - -/// Number of available clock configurations -#define NB_CLOCK_CONFIGURATION (sizeof(clockConfigurations)/sizeof(clockConfigurations[0])) - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Sets the specified clock configuration. -/// \param configuration Index of the configuration to set. -//------------------------------------------------------------------------------ -void CLOCK_SetConfig(unsigned char configuration) -{ - printf("Setting clock configuration #%d ... ", configuration); - currentConfig = configuration; - - // Switch to main oscillator in two operations - PMC->PMC_MCKR = (PMC->PMC_MCKR & ~AT91C_PMC_CSS) | AT91C_PMC_CSS_MAIN_CLK; - while ((PMC->PMC_SR & AT91C_PMC_MCKRDY) == 0); - - // Configure PLL - *AT91C_CKGR_PLLAR = clockConfigurations[configuration].pllr; - while ((PMC->PMC_SR & AT91C_PMC_LOCKA) == 0); - - // Configure master clock in two operations - PMC->PMC_MCKR = (clockConfigurations[configuration].mckr & ~AT91C_PMC_CSS) | AT91C_PMC_CSS_MAIN_CLK; - while ((PMC->PMC_SR & AT91C_PMC_MCKRDY) == 0); - PMC->PMC_MCKR = clockConfigurations[configuration].mckr; - while ((PMC->PMC_SR & AT91C_PMC_MCKRDY) == 0); - - // DBGU reconfiguration - DBGU_Configure(DBGU_STANDARD, 115200, clockConfigurations[configuration].mck*1000000); - printf("done.\n\r"); -} - -//------------------------------------------------------------------------------ -/// Display the user menu on the DBGU. -//------------------------------------------------------------------------------ -void CLOCK_DisplayMenu(void) -{ - unsigned int i; - - printf("\n\rMenu Clock configuration:\n\r"); - for (i = 0; i < NB_CLOCK_CONFIGURATION; i++) { - - printf(" %d: Set PCK = %3d MHz, MCK = %3d MHz %s\n\r", - i, - clockConfigurations[i].pck, - clockConfigurations[i].mck, - (currentConfig==i)?"(curr)":""); - } -} - -//------------------------------------------------------------------------------ -/// Get the current MCK -//------------------------------------------------------------------------------ -unsigned short CLOCK_GetCurrMCK(void) -{ - return clockConfigurations[currentConfig].mck; -} - -//------------------------------------------------------------------------------ -/// Get the current PCK -//------------------------------------------------------------------------------ -unsigned short CLOCK_GetCurrPCK(void) -{ - return clockConfigurations[currentConfig].pck; -} - -//------------------------------------------------------------------------------ -/// Change clock configuration. -//------------------------------------------------------------------------------ -void CLOCK_UserChangeConfig(void) -{ - unsigned char key = 0; - - while (1) - { - CLOCK_DisplayMenu(); - key = DBGU_GetChar(); - - if ((key >= '0') && (key <= ('0' + NB_CLOCK_CONFIGURATION - 1))) - { - CLOCK_SetConfig(key - '0'); - break; - } - } -} \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/clock.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/clock.h deleted file mode 100644 index 54083008d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/clock.h +++ /dev/null @@ -1,47 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef CLOCK_H -#define CLOCK_H - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -extern void CLOCK_SetConfig(unsigned char configuration); - -extern void CLOCK_DisplayMenu(void); - -extern void CLOCK_UserChangeConfig(void); - -extern unsigned short CLOCK_GetCurrMCK(void); - -extern unsigned short CLOCK_GetCurrPCK(void); - -#endif //#ifndef FREQCONF_H diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/aes_hardware.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/aes_hardware.c deleted file mode 100644 index 1501afef0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/aes_hardware.c +++ /dev/null @@ -1,316 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Function: Firmware encryption using hardware acceleration -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include "aes_hardware.h" - -#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_HARD) -#include -#include -#include -#include -#include -#include -#include - -//------------------------------------------------------------------------------ -// Inline functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Converts an ASCII value to an hexadecimal one -/// \param ASCII string -/// \param Buffer to store integer value -/// \param Length of string -//------------------------------------------------------------------------------ -static inline void ASCII2Hex(const unsigned char * ascii, - unsigned char * binary, - unsigned int length) -{ - unsigned int i; - - for (i=0; i < length; i++) { - if (ascii[i*2] >= 'A') { - binary[i] = ascii[i*2] - 'A' + 10; - } - else { - binary[i] = ascii[i*2] - '0'; - } - binary[i] <<= 4; - if (ascii[i*2+1] >= 'A') { - binary[i] += ascii[i*2+1] - 'A' + 10; - } - else { - binary[i] += ascii[i*2+1] - '0'; - } - } -} - -//------------------------------------------------------------------------------ -// Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Initializes the AES peripheral -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -void aes_hard_init(void) -{ - unsigned char key[16]; - -#if defined(ENCRYPTION_CTR) || defined(ENCRYPTION_CBC) - unsigned char IV[16]; -#endif - - TRACE_DEBUG("AES/HARD: Initializing ...\n\r"); - - // Activate peripheral clock -#ifdef AT91C_ID_AES - PMC_EnablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_EnablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_EnablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - - // Load mode -#if defined(ENCRYPTION_ECB) - //AES_Configure(AT91C_AES_CIPHER, AT91C_AES_SMOD_PDC, AT91C_AES_OPMOD_ECB); - - AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_ECB; -#elif defined(ENCRYPTION_CBC) - AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_CBC; -#elif defined(ENCRYPTION_CTR) - AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_CTR; -#endif - - // Convert and load key - ASCII2Hex((unsigned char*)ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - AES_SetKey((unsigned int*)key); - - // Convert and load IV -#if defined(ENCRYPTION_CTR) || defined(ENCRYPTION_CBC) - ASCII2Hex((unsigned char*)ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - AES_SetVector((unsigned int*)IV); -#endif - - TRACE_DEBUG("AES/HARD: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the AES peripheral for CBC mode -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -#if defined(ENCRYPTION_CBC) -void aes_hard_init_CBC(void) -{ - unsigned char key[16]; - unsigned char IV[16]; - - TRACE_DEBUG("aes_hard_init_CBC\n\r"); - - // Activate peripheral clock -#ifdef AT91C_ID_AES - PMC_EnablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_EnablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_EnablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - - // Load mode - AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_CBC; - - // Convert and load key - ASCII2Hex((unsigned char*)ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - AES_SetKey((unsigned int*)key); - - // Convert and load IV - ASCII2Hex((unsigned char*)ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - AES_SetVector((unsigned int*)IV); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the AES peripheral for CTR mode -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -void aes_hard_init_CTR(void) -{ - unsigned char key[16]; - unsigned char IV[16]; - - TRACE_DEBUG("aes_hard_init_CTR\n\r"); - - // Activate peripheral clock -#ifdef AT91C_ID_AES - PMC_EnablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_EnablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_EnablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - - // Load mode - AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_CTR; - - // Convert and load key - ASCII2Hex((unsigned char*)ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - AES_SetKey((unsigned int*)key); - - // Convert and load IV - ASCII2Hex((unsigned char*)ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - AES_SetVector((unsigned int*)IV); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the AES peripheral for ECB mode -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) -void aes_hard_init_ECB(void) -{ - unsigned char key[16]; - - TRACE_DEBUG("aes_hard_init_ECB\n\r"); - - // Activate peripheral clock -#ifdef AT91C_ID_AES - PMC_EnablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_EnablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_EnablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - - // Load mode - //AES_Configure(AT91C_AES_CIPHER, AT91C_AES_SMOD_MANUAL, AT91C_AES_OPMOD_ECB); - AT91C_BASE_AES->AES_MR = AT91C_AES_SMOD_PDC | AT91C_AES_OPMOD_ECB; - - // Convert and load key - ASCII2Hex((unsigned char*)ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - AES_SetKey((unsigned int*)key); -} -#endif -#endif // ONLY_ONE_ENCRYPTION - -//------------------------------------------------------------------------------ -/// Cleans up the AES peripheral -//------------------------------------------------------------------------------ -void aes_hard_cleanup(void) -{ - TRACE_DEBUG("AES/HARD: Cleaning up ...\n\r"); - - AT91C_BASE_AES->AES_MR = 0; - -#ifdef AT91C_ID_AES - PMC_DisablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_DisablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_DisablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - - // Close PDC - AT91C_BASE_PDC_AES->PDC_PTCR = AT91C_PDC_RXTDIS; - AT91C_BASE_PDC_AES->PDC_PTCR = AT91C_PDC_TXTDIS; - - // Reset all Counter register Next buffer first - AT91C_BASE_PDC_AES->PDC_TNPR = 0; - AT91C_BASE_PDC_AES->PDC_TNCR = 0; - AT91C_BASE_PDC_AES->PDC_RPR = 0; - AT91C_BASE_PDC_AES->PDC_RCR = 0; - AT91C_BASE_PDC_AES->PDC_TPR = 0; - AT91C_BASE_PDC_AES->PDC_TCR = 0; - AT91C_BASE_PDC_AES->PDC_RPR = 0; - AT91C_BASE_PDC_AES->PDC_RCR = 0; - - TRACE_DEBUG("AES/HARD: Cleanup done.\n\r"); -} - -//------------------------------------------------------------------------------ -/// Decrypts a variable-length cipher text -/// \param pCipherText text to decrypt -/// \param pPlainText to store plain text -/// \param length of cipher text (in bytes) -/// \return: 1 if ok, 0 if error -//------------------------------------------------------------------------------ -int aes_hard_decrypt(const unsigned char *pCipherText, - unsigned char *pPlainText, - unsigned int length) -{ - TRACE_DEBUG("aes_hard_decrypt\n\r"); - - // Check parameters - if ((pCipherText == NULL) || (pPlainText == NULL)) { - return 0; - } - - // Set source and destination buffers in PDC - AT91C_BASE_PDC_AES->PDC_TPR = (unsigned int) pCipherText; - AT91C_BASE_PDC_AES->PDC_RPR = (unsigned int) pPlainText; - - AT91C_BASE_PDC_AES->PDC_TCR = length >> 2; - AT91C_BASE_PDC_AES->PDC_RCR = length >> 2; - - // Start decryption and wait - AT91C_BASE_PDC_AES->PDC_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN; - while (((AES_GetStatus()) & AT91C_AES_ENDRX) == 0); - - return 1; -} - -#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_HARD) - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/aes_hardware.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/aes_hardware.h deleted file mode 100644 index 62f38a7fe..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/aes_hardware.h +++ /dev/null @@ -1,100 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// Firmware encryption using AES hardware acceleration -/// This code is based on the AES reference implementation published by Paulo -/// Barreto and Vincent Rijmen. -/// -/// !Usage -/// -/// -# aes_hard_init: Initialize AES hardware -/// -# aes_hard_init_CBC: for the CBC mode -/// -# aes_hard_init_CTR: for the CTR mode -/// -# aes_hard_init_ECB: for the ECB mode -/// -# aes_hard_cleanup: Cleans up AES -/// -# aes_hard_decrypt: Decrypts a variable-length cipher text -//------------------------------------------------------------------------------ - -#ifndef BOOTLOADER_AES_HARDWARE_H -#define BOOTLOADER_AES_HARDWARE_H - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "config.h" - -#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_HARD) - -//------------------------------------------------------------------------------ -// Check configuration -//------------------------------------------------------------------------------ -#if (ENCRYPTION_KEY_LENGTH != 16) - #error Hardware AES acceleration only supports 128 bits keys. -#endif - -#if (ENCRYPTION_BLOCK_LENGTH != 16) - #error Hardware AES acceleration only supports 128 bits blocks. -#endif - -#if !defined(ENCRYPTION_ECB) && \ - !defined(ENCRYPTION_CBC) && \ - !defined(ENCRYPTION_CTR) - #error Only ECB, CBC & CTR modes are supported. -#endif - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -#define ENCRYPTION_INIT aes_hard_init -#define ENCRYPTION_CLEANUP aes_hard_cleanup -#define ENCRYPTION_DECRYPT aes_hard_decrypt -#endif - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -extern void aes_hard_init(void); -#ifndef ONLY_ONE_ENCRYPTION -extern void aes_hard_init_CBC(void); -extern void aes_hard_init_CTR(void); -extern void aes_hard_init_ECB(void); -#endif -extern void aes_hard_cleanup(void); -extern int aes_hard_decrypt(const unsigned char *, unsigned char *, unsigned int); - -#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_HARD) -#endif // BOOTLOADER_AES_HARDWARE_H - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/aes_reference.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/aes_reference.c deleted file mode 100644 index a94844ab3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/aes_reference.c +++ /dev/null @@ -1,801 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Firmware encryption using AES reference implementation -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "aes_reference.h" - -#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_REF) -#include -#include -#include -#include -#include -#include - -//------------------------------------------------------------------------------ -// Global variables -//------------------------------------------------------------------------------ -#define word8 static unsigned char -#define word32 static unsigned int - -#include "boxes-ref.dat" - -static unsigned char shifts[3][2][4] = { - {{0,1,2,3}, {0,3,2,1}}, - {{0,1,2,3}, {0,5,4,3}}, - {{0,7,5,5}, {0,1,3,4}} -}; - -static unsigned char key[KC][4]; -static unsigned char expandedKey[ROUNDS+1][BC][4]; -static unsigned int T0[256], T1[256], T2[256], T3[256], TF[256]; - -#if defined(ENCRYPTION_CBC) || defined(ENCRYPTION_CTR) -static unsigned char IV[BC][4]; -#endif - -//------------------------------------------------------------------------------ -// Inline functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Multiply two elements of GF(2^m) needed for MixColumn and InvMixColumn -/// \param a first element -/// \param b second element -/// \return result of operation -//------------------------------------------------------------------------------ -static unsigned char mul(unsigned char a, unsigned char b) -{ - if (a && b) { - return Alogtable[(Logtable[a] + Logtable[b])%255]; - } - else { - return 0; - } -} - -//------------------------------------------------------------------------------ -/// Returns the minimum between two numbers -/// \param First number -/// \param Second number -/// \return Minimum between the two operands -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -static unsigned int min(unsigned int number1, unsigned int number2) -{ - if (number1 > number2) { - return number2; - } - else { - return number1; - } -} -#endif - -//------------------------------------------------------------------------------ -/// XOR text and round key together -/// \param Plain text -/// \param Round key -//------------------------------------------------------------------------------ -static inline void addRoundKey(unsigned char a[BC][4], const unsigned char rk[BC][4]) -{ - unsigned int i; - - for (i=0; i < BC; i++) { - ((int *) a)[i] ^= ((int *) rk)[i]; - } -} - -//------------------------------------------------------------------------------ -/// Performs the AES key schedule -/// \param Key to use -/// \param Buffer to store expanded key schedule -//------------------------------------------------------------------------------ -static inline void keySchedule(unsigned char k[KC][4], unsigned char W[ROUNDS+1][BC][4]) -{ - int t; - int rconpointer = 0; - unsigned int j; - unsigned char tk[KC][4]; - - for(j=0; j < KC; j++) { - ((int *) tk)[j] = ((int *) k)[j]; - } - - t = 0; - /* copy values into round key array */ - for(j=0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) { - ((int *) W[t / BC])[t%BC] = ((int *) tk)[j]; - } - - while (t < (ROUNDS+1)*BC) { - - tk[0][0] ^= S[tk[KC-1][1]] ^ rcon[rconpointer++]; - tk[0][1] ^= S[tk[KC-1][2]]; - tk[0][2] ^= S[tk[KC-1][3]]; - tk[0][3] ^= S[tk[KC-1][0]]; - - if (KC != 8) { - for(j=1; j < KC; j++) { - ((int *) tk)[j] ^= ((int *) tk)[j-1]; - } - } - else { - for(j=1; j < KC/2; j++) { - ((int *) tk)[j] ^= ((int *) tk)[j-1]; - } - tk[KC/2][0] ^= S[tk[KC/2 - 1][0]]; - tk[KC/2][1] ^= S[tk[KC/2 - 1][1]]; - tk[KC/2][2] ^= S[tk[KC/2 - 1][2]]; - tk[KC/2][3] ^= S[tk[KC/2 - 1][3]]; - - for(j=KC/2+1; j < KC; j++) { - ((int *) tk)[j] ^= ((int *) tk)[j-1]; - } - } - - // copy values into round key array - for(j=0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) { - ((int *) W[t/BC])[t%BC] = ((int *) tk)[j]; - } - } -} - -//------------------------------------------------------------------------------ -/// Performs the AES inverse key schedule -/// \param Key to use -/// \param Buffer to store expanded key schedule -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) || defined(ENCRYPTION_CBC) -static inline void invKeySchedule(unsigned char k[KC][4], - unsigned char W[ROUNDS+1][BC][4]) -{ - unsigned int r; - unsigned int j; - unsigned char tmp[4]; - - // Expand key normally - keySchedule(k, W); - - // Apply invMixColumns to all rounds except first and last one - for (r=1; r < ROUNDS; r++) { - for (j=0; j < BC; j++) { - tmp[0] = mul(0x0E, W[r][j][0]) ^ mul(0x0B, W[r][j][1]) ^ - mul(0x0D, W[r][j][2]) ^ mul(0x09, W[r][j][3]); - tmp[1] = mul(0x0E, W[r][j][1]) ^ mul(0x0B, W[r][j][2]) ^ - mul(0x0D, W[r][j][3]) ^ mul(0x09, W[r][j][0]); - tmp[2] = mul(0x0E, W[r][j][2]) ^ mul(0x0B, W[r][j][3]) ^ - mul(0x0D, W[r][j][0]) ^ mul(0x09, W[r][j][1]); - tmp[3] = mul(0x0E, W[r][j][3]) ^ mul(0x0B, W[r][j][0]) ^ - mul(0x0D, W[r][j][1]) ^ mul(0x09, W[r][j][2]); - W[r][j][0] = tmp[0]; - W[r][j][1] = tmp[1]; - W[r][j][2] = tmp[2]; - W[r][j][3] = tmp[3]; - } - } -} -#endif - -//------------------------------------------------------------------------------ -/// Perform the RotBytes operation needed by the AES cipher -/// \param input to rotate -/// \return Rotated word -//------------------------------------------------------------------------------ -static inline unsigned int rotBytes(unsigned int input) -{ - return ((input << 8) | (input >> 24)); -} - -//------------------------------------------------------------------------------ -/// Generates the lookup tables needed for encryption -/// \param Pointer to t0 -/// \param Pointer to t1 -/// \param Pointer to t2 -/// \param Pointer to t3 -/// \param Pointer to tf -/// \param Box -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -static inline void generateEncryptionLUTs(unsigned int * t0, - unsigned int * t1, - unsigned int * t2, - unsigned int * t3, - unsigned int * tf, - unsigned char box[256]) -{ - unsigned int a; - - for (a=0; a <= 255; a++) { - // Calc t0 - t0[a] = (mul(2, box[a])) | - (box[a] << 8) | - (box[a] << 16) | - (mul(3, box[a]) << 24); - - // Calc t1, t2, t3 - t1[a] = rotBytes(t0[a]); - t2[a] = rotBytes(t1[a]); - t3[a] = rotBytes(t2[a]); - - // Calc tf - tf[a] = box[a] | (box[a] << 8) | (box[a] << 16) | (box[a] << 24); - } -} -#endif - -//------------------------------------------------------------------------------ -/// Generates the lookup tables needed for decryption -/// \param Pointer to t0 -/// \param Pointer to t1 -/// \param Pointer to t2 -/// \param Pointer to t3 -/// \param Pointer to tf -/// \param Box -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) || defined(ENCRYPTION_CBC) -static inline void generateDecryptionLUTs(unsigned int * t0, - unsigned int * t1, - unsigned int * t2, - unsigned int * t3, - unsigned int * tf, - unsigned char box[256]) -{ - unsigned int a; - - for (a=0; a <= 255; a++) { - - // Calc t0 - t0[a] = (mul(0x0E, box[a])) | - (mul(0x09, box[a]) << 8) | - (mul(0x0D, box[a]) << 16) | - (mul(0x0B, box[a]) << 24); - - // Calc t1, t2, t3 - t1[a] = rotBytes(t0[a]); - t2[a] = rotBytes(t1[a]); - t3[a] = rotBytes(t2[a]); - - // Calc tf - tf[a] = box[a] | (box[a] << 8) | (box[a] << 16) | (box[a] << 24); - } -} -#endif - -//------------------------------------------------------------------------------ -/// Copies a block to a buffer -/// \param Block to copy -/// \param Buffer to store copy -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -static void copyBlock(unsigned char input[BC][4], unsigned char output[BC][4]) -{ - unsigned int j; - - for (j=0; j < BC; j++) { - ((int *) output)[j] = ((int *) input)[j]; - } -} -#endif - -//------------------------------------------------------------------------------ -/// Encrypts a block of plain text using precalculated LUTs -/// \param Block of plain text to encrypt -/// \param Expanded key -/// \param Pointer to t0 -/// \param Pointer to t1 -/// \param Pointer to t2 -/// \param Pointer to t3 -/// \param Pointer to tf -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -static inline void encrypt(unsigned char a[BC][4], - const unsigned char rk[ROUNDS+1][BC][4], - unsigned int * t0, - unsigned int * t1, - unsigned int * t2, - unsigned int * t3, - unsigned int * tf) -{ - unsigned char b[BC][4]; - unsigned int r; - unsigned int j; - - // First key addition - addRoundKey(a, rk[0]); - - // ROUNDS-1 ordinary rounds - for(r=1; r < ROUNDS; r++) { - for (j=0; j < BC; j++) { - - ((int *) b)[j] = t0[a[j][0]] ^ - t1[a[(j+shifts[SC][0][1])%BC][1]] ^ - t2[a[(j+shifts[SC][0][2])%BC][2]] ^ - t3[a[(j+shifts[SC][0][3])%BC][3]] ^ - ((int *) rk[r])[j]; - } - if ((++r) == ROUNDS) { - break; - } - for (j=0; j < BC; j++) { - ((int *) a)[j] = t0[b[j][0]] ^ - t1[b[(j+shifts[SC][0][1])%BC][1]] ^ - t2[b[(j+shifts[SC][0][2])%BC][2]] ^ - t3[b[(j+shifts[SC][0][3])%BC][3]] ^ - ((int *) rk[r])[j]; - } - } - - // Last round (no MixColumns) - for (j=0; j < BC; j++) { - ((int *) a)[j] = (t0f[b[j][0]]) ^ - (t1f[b[(j+shifts[SC][0][1])%BC][1]]) ^ - (t2f[b[(j+shifts[SC][0][2])%BC][2]]) ^ - (t3f[b[(j+shifts[SC][0][3])%BC][3]]) ^ - ((int *) rk[ROUNDS])[j]; - } -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypts a block of plain text using precalculated LUTs -/// \param Block of cipher text to decrypt -/// \param Expanded key -/// \param Pointer to t0 -/// \param Pointer to t1 -/// \param Pointer to t2 -/// \param Pointer to t3 -/// \param Pointer to tf -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) || defined(ENCRYPTION_CBC) -static inline void decrypt(unsigned char a[BC][4], - const unsigned char rk[ROUNDS+1][BC][4], - unsigned int * t0, - unsigned int * t1, - unsigned int * t2, - unsigned int * t3, - unsigned int * tf) -{ - unsigned char b[BC][4]; - unsigned int r; - unsigned int j; - - // First key addition - addRoundKey(a, rk[ROUNDS]); - - // ROUNDS-1 ordinary rounds - for(r=ROUNDS-1; r > 0; r--) { - for (j=0; j < BC; j++) { - ((int *) b)[j] = t0[a[j][0]] ^ - t1[a[(j+shifts[SC][1][1])%BC][1]] ^ - t2[a[(j+shifts[SC][1][2])%BC][2]] ^ - t3[a[(j+shifts[SC][1][3])%BC][3]] ^ - ((int *) rk[r])[j]; - } - if ((--r) == 0) { - break; - } - for (j=0; j < BC; j++) { - ((int *) a)[j] = t0[b[j][0]] ^ - t1[b[(j+shifts[SC][1][1])%BC][1]] ^ - t2[b[(j+shifts[SC][1][2])%BC][2]] ^ - t3[b[(j+shifts[SC][1][3])%BC][3]] ^ - ((int *) rk[r])[j]; - } - } - // Last round (no MixColumns) - for (j=0; j < BC; j++) { - ((int *) a)[j] = (t0f[b[j][0]]) ^ - (t1f[b[(j+shifts[SC][1][1])%BC][1]]) ^ - (t2f[b[(j+shifts[SC][1][2])%BC][2]]) ^ - (t3f[b[(j+shifts[SC][1][3])%BC][3]]) ^ - ((int *) rk[0])[j]; - } -} -#endif - -//------------------------------------------------------------------------------ -/// Converts an ASCII hexadecimal representation to a raw binary one -/// \param ASCII value -/// \param Buffer to store binary value -/// \param Size of value -//------------------------------------------------------------------------------ -static void ASCII2RawHex(const unsigned char * ascii, - unsigned char * binary, - unsigned int length) -{ - unsigned char * ptr; - unsigned int i; - - ptr = (unsigned char *) binary; - for (i=0; i < length; i++, ptr++, ascii++) { - if (*ascii >= 'A') { - *ptr = *ascii - 'A' + 10; - } - else { - *ptr = *ascii - '0'; - } - *ptr <<= 4; - ascii++; - if (*ascii >= 'A') { - *ptr += *ascii - 'A' + 10; - } - else { - *ptr += *ascii - '0'; - } - } -} - -//------------------------------------------------------------------------------ -/// Decrypts a cipher text using ECB mode -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text -/// \param Expanded key to use -/// \return 0 if successful, 0 otherwise -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) -static unsigned int ecb_decrypt(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length, - unsigned char expandedKey[ROUNDS+1][BC][4]) -{ - unsigned char block[BC][4]; - unsigned int i; - unsigned int l; - - // Check input parameters - if ((cipherText == NULL) || (plainText == NULL) || (expandedKey == NULL)) { - TRACE_DEBUG("AES/REF: NULL parameter(s).\n\r"); - return 0; - } - if (length%ENCRYPTION_BLOCK_LENGTH != 0) { - TRACE_DEBUG("AES/REF: Data length must be a multiple of the cipher block size.\n\r"); - return 0; - } - // ECB decryption - for (l=0; l < length;) { - // Copy cipher text block, decrypt it and copy result - for (i=0; i < ENCRYPTION_BLOCK_LENGTH; i++) { - ((char *) block)[i] = cipherText[l+i]; - } - decrypt(block, expandedKey, T0, T1, T2, T3, TF); - for (i=0; i < ENCRYPTION_BLOCK_LENGTH; i++) { - plainText[l+i] = ((char *) block)[i]; - } - l += ENCRYPTION_BLOCK_LENGTH; - } - - return 1; -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypts a cipher text using CBC mode -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -/// \param Expanded key to use -/// \param Initialization vector to use -/// \return 1 if successful, 0 otherwise */ -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CBC) -static unsigned int cbc_decrypt(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length, - const unsigned char expandedKey[ROUNDS+1][BC][4], - unsigned char IV[BC][4]) -{ - unsigned char block[BC][4]; - unsigned int i; - unsigned int l; - - // Check input parameters - if ((cipherText == NULL) || (plainText == NULL)) { - TRACE_DEBUG("AES/REF: NULL parameter(s).\n\r"); - return 0; - } - if (length%ENCRYPTION_BLOCK_LENGTH != 0) { - TRACE_DEBUG("AES/REF: Cipher text length must be a multiple of the cipher block length.\n\r"); - return 0; - } - // Decrypt data - for (l=0; l < length;) { - // Copy and decrypt a block of cipher text - for (i=0; i < BC; i++) { - ((int *) block)[i] = ((int *) &cipherText[l])[i]; - } - decrypt(block, expandedKey, T0, T1, T2, T3, TF); - // Xor decrypted text & IV, copy new IV - for (i=0; i < BC; i++) { - unsigned int tmp = ((int *) block)[i] ^ ((int *) IV)[i]; - ((int *) IV)[i] = ((int *) &cipherText[l])[i]; - ((int *) &plainText[l])[i] = tmp; - } - - // Loop progression - l += ENCRYPTION_BLOCK_LENGTH; - } - return 1; -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypts a cipher text using CTR mode -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text -/// \param Expanded key to use -/// \param Initialization vector to use -/// \return 1 if successful, 0 otherwise -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -static unsigned int ctr_decrypt(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length, - const unsigned char expandedKey[ROUNDS+1][BC][4], - unsigned char IV[BC][4]) -{ - unsigned char block[BC][4]; - unsigned int bytes; - unsigned int i; - unsigned int l; - int k; - - // Check input parameters - if ((cipherText == NULL) || (plainText == NULL)) { - return 0; - } - for (l=0; l < length;) { - // Copy counter and encrypt it - copyBlock(IV, block); - encrypt(block, expandedKey, T0, T1, T2, T3, TF); - - // XOR current plain text block with encrypted counter - bytes = min(length - l, ENCRYPTION_BLOCK_LENGTH); - - for (i=0; i < bytes; i++) { - plainText[l+i] = cipherText[l+i] ^ ((char *) block)[i]; - } - // Increment counter (big-endian) and number of encrypted bytes - for (k=ENCRYPTION_BLOCK_LENGTH-1; k >= 0; k--) { - if (++((char *) IV)[k] != 0) { - break; - } - } - l += bytes; - } - return 1; -} -#endif - -//------------------------------------------------------------------------------ -// Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Initializes the AES algorithm -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -void aes_ref_init(void) -{ - TRACE_DEBUG("AES/REF: Initializing ...\n\r"); - - ASCII2RawHex((unsigned char*)ENCRYPTION_KEY, (unsigned char*)key, ENCRYPTION_KEY_LENGTH); - -#if defined(ENCRYPTION_ECB) || defined(ENCRYPTION_CBC) - - // Initialize key schedule - invKeySchedule(key, expandedKey); - - // Generate lookup tables - generateDecryptionLUTs(T0, T1, T2, T3, TF, Si); - -#elif defined(ENCRYPTION_CTR) - - // Initialize key schedule - keySchedule(key, expandedKey); - - // Generate lookup tables - generateEncryptionLUTs(T0, T1, T2, T3, TF, S); -#endif - -#if defined(ENCRYPTION_CBC) || defined(ENCRYPTION_CTR) - // Initialize counter - ASCII2RawHex((unsigned char*)ENCRYPTION_IV, (unsigned char*)IV, ENCRYPTION_BLOCK_LENGTH); -#endif - - TRACE_DEBUG("AES/REF: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the AES algorithm mode CBC -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -#if defined(ENCRYPTION_CBC) -void aes_ref_init_CBC(void) -{ - TRACE_DEBUG("aes_ref_init_CBC\n\r"); - - ASCII2RawHex((unsigned char*)ENCRYPTION_KEY, (unsigned char*)key, ENCRYPTION_KEY_LENGTH); - - // Initialize key schedule - invKeySchedule(key, expandedKey); - - // Generate lookup tables - generateDecryptionLUTs(T0, T1, T2, T3, TF, Si); - - // Initialize counter - ASCII2RawHex((unsigned char*)ENCRYPTION_IV, (unsigned char*)IV, ENCRYPTION_BLOCK_LENGTH); - - TRACE_DEBUG("AES/REF: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the AES algorithm mode ECB -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) -void aes_ref_init_ECB(void) -{ - TRACE_DEBUG("aes_ref_init_ECB\n\r"); - - ASCII2RawHex((unsigned char*)ENCRYPTION_KEY, (unsigned char*)key, ENCRYPTION_KEY_LENGTH); - - // Initialize key schedule - invKeySchedule(key, expandedKey); - - // Generate lookup tables - generateDecryptionLUTs(T0, T1, T2, T3, TF, Si); - - TRACE_DEBUG("AES/REF: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the AES algorithm mode CTR -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -void aes_ref_init_CTR(void) -{ - TRACE_DEBUG("aes_ref_init_CTR\n\r"); - - ASCII2RawHex((unsigned char*)ENCRYPTION_KEY, (unsigned char*)key, ENCRYPTION_KEY_LENGTH); - - // Initialize key schedule - keySchedule(key, expandedKey); - - // Generate lookup tables - generateEncryptionLUTs(T0, T1, T2, T3, TF, S); - - // Initialize counter - ASCII2RawHex((unsigned char*)ENCRYPTION_IV, (unsigned char*)IV, ENCRYPTION_BLOCK_LENGTH); - - TRACE_DEBUG("AES/REF: Initialization done.\n\r"); -} -#endif -#endif // ONLY_ONE_ENCRYPTION - -//------------------------------------------------------------------------------ -/// Cleanup the AES algorithm -//------------------------------------------------------------------------------ -void aes_ref_cleanup(void) -{ - TRACE_DEBUG("AES/REF: Cleaning up ...\n\r"); - TRACE_DEBUG("AES/REF: Cleanup done.\n\r"); -} - -//------------------------------------------------------------------------------ -/// Decrypt a cipher text of variable length -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -/// \return 1 if decryption was successful, 0 otherwise. -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -int aes_ref_decrypt(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length) -{ - TRACE_DEBUG("aes_ref_decrypt\n\r"); -#if defined(ENCRYPTION_ECB) - return ecb_decrypt(cipherText, plainText, length, expandedKey); -#elif defined(ENCRYPTION_CBC) - return cbc_decrypt(cipherText, plainText, length, expandedKey, IV);; -#elif defined(ENCRYPTION_CTR) - return ctr_decrypt(cipherText, plainText, length, expandedKey, IV); -#endif -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypt a cipher text of variable length, mode CBC -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -/// \return 1 if decryption was successful, 0 otherwise. -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -#if defined(ENCRYPTION_CBC) -int aes_ref_decrypt_CBC(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length) -{ - TRACE_DEBUG("aes_ref_decrypt_CBC\n\r"); - return cbc_decrypt(cipherText, plainText, length, expandedKey, IV);; -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypt a cipher text of variable length, mode ECB -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -/// \return 1 if decryption was successful, 0 otherwise. -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) -int aes_ref_decrypt_ECB(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length) -{ - TRACE_DEBUG("aes_ref_decrypt_ECB\n\r"); - return ecb_decrypt(cipherText, plainText, length, expandedKey); -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypt a cipher text of variable length, mode CTR -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -/// \return 1 if decryption was successful, 0 otherwise. -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -int aes_ref_decrypt_CTR(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length) -{ - TRACE_DEBUG("aes_ref_decrypt_CTR\n\r"); - return ctr_decrypt(cipherText, plainText, length, expandedKey, IV); -} -#endif - -#endif // ONLY_ONE_ENCRYPTION - -#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_REF) - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/aes_reference.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/aes_reference.h deleted file mode 100644 index a47907bd9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/aes_reference.h +++ /dev/null @@ -1,132 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// Firmware encryption using AES reference implementation -/// -/// !Usage -/// -/// -# aes_ref_init: Initialize AES hardware -/// -# aes_ref_init_CBC: for the CBC mode -/// -# aes_ref_init_ECB: for the CTR mode -/// -# aes_ref_init_CTR: for the ECB mode -/// -# aes_ref_cleanup: Cleans up AES -/// -# aes_ref_decrypt: Decrypts a variable-length cipher text -/// -# aes_ref_decrypt_CBC: for CBC mode -/// -# aes_ref_decrypt_ECB: for ECB mode -/// -# aes_ref_decrypt_CTR: for CTR mode -//------------------------------------------------------------------------------ - -#ifndef BOOTLOADER_AES_REFERENCE_H -#define BOOTLOADER_AES_REFERENCE_H - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "config.h" - - -#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_REF) - -//------------------------------------------------------------------------------ -// Check configuration -//------------------------------------------------------------------------------ - -// Supported modes -#if !defined(ENCRYPTION_ECB) && \ - !defined(ENCRYPTION_CBC) && \ - !defined(ENCRYPTION_CTR) - #error No other mode than ECB, CBC & CTR are supported. -#endif - -// Supported key length -#if (ENCRYPTION_KEY_LENGTH != 16) && \ - (ENCRYPTION_KEY_LENGTH != 24) && \ - (ENCRYPTION_KEY_LENGTH != 32) - #error Only key lengths of 128, 192 or 256 bits are supported. -#endif - -// Supported block length -#if (ENCRYPTION_BLOCK_LENGTH != 16) - #error Only block length of 128 bits is supported. -#endif - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ -#define BC (ENCRYPTION_BLOCK_LENGTH / 4) -#define SC ((BC - 4) >> 1) -#define KC (ENCRYPTION_KEY_LENGTH / 4) -#define t0f 0x000000FF & tf -#define t1f 0x0000FF00 & tf -#define t2f 0x00FF0000 & tf -#define t3f 0xFF000000 & tf - -#if (KC >= BC) - #define ROUNDS (KC + 6) -#else - #define ROUNDS (BC + 6) -#endif - -#ifdef ONLY_ONE_ENCRYPTION -#define ENCRYPTION_INIT aes_ref_init -#define ENCRYPTION_CLEANUP aes_ref_cleanup -#define ENCRYPTION_DECRYPT aes_ref_decrypt -#endif - -//------------------------------------------------------------------------------ -// Prototypes -//------------------------------------------------------------------------------ -extern void aes_ref_init(void); -extern void aes_ref_init_CBC(void); -extern void aes_ref_init_ECB(void); -extern void aes_ref_init_CTR(void); -extern void aes_ref_cleanup(void); -extern int aes_ref_decrypt(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length); -extern int aes_ref_decrypt_CBC(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length); -extern int aes_ref_decrypt_ECB(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length); -extern int aes_ref_decrypt_CTR(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length); - -#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_AES_REF) - -#endif // BOOTLOADER_AES_REFERENCE_H - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/encryption.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/encryption.h deleted file mode 100644 index 8b2850091..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/encryption.h +++ /dev/null @@ -1,98 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// Firmware encryption -/// -/// !Usage -/// -/// This file must include the header of every encryption module implemented for -/// the bootloader. It is also responsible for defining mock functions if no -/// encryption module is selected, as well as checking that parameters are -/// correctly set. -// -/// An encryption module must define the following functions: -/// -# void encryption_init(void); -/// -# void encryption_cleanup(void); -/// -# int encryption_decrypt(const unsigned char *, unsigned char *, unsigned int) -//------------------------------------------------------------------------------ - -#ifndef BOOTLOADER_ENCRYPTION_H -#define BOOTLOADER_ENCRYPTION_H - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "config.h" - - -//------------------------------------------------------------------------------ -// Check configuration -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -#if !defined(ENCRYPTION_INIT) && !defined(USE_ENCRYPTION) - #define ENCRYPTION_INIT(); - #define ENCRYPTION_CLEANUP(); - #define ENCRYPTION_DECRYPT(...) 1 - -#elif !defined(ENCRYPTION_INIT) && defined(USE_ENCRYPTION) - #error USE_ENCRYPTION defined but no encryption method selected. - -#elif !defined(ENCRYPTION_AES_LTC) && \ - !defined(ENCRYPTION_AES_REF) && \ - !defined(ENCRYPTION_AES_HARD) && \ - !defined(ENCRYPTION_3DES_LTC) && \ - !defined(ENCRYPTION_3DES_HARD) - #error No algorithm selected. - -#elif !defined(ENCRYPTION_ECB) && \ - !defined(ENCRYPTION_CBC) && \ - !defined(ENCRYPTION_CTR) - #error No encryption mode selected. - -#elif !defined(ENCRYPTION_KEY) - #error No key defined. - -#elif !defined(ENCRYPTION_KEY_LENGTH) - #error No key length selected. - -#elif !defined(ENCRYPTION_IV) - #error No initialization vector defined. - -#elif !defined(ENCRYPTION_BLOCK_LENGTH) - #error No block length selected. - -#endif -#endif // ONLY_ONE_ENCRYPTION -#endif // BOOTLOADER_ENCRYPTION_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/libtomcrypt.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/libtomcrypt.c deleted file mode 100644 index c21b20c91..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/libtomcrypt.c +++ /dev/null @@ -1,445 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Function: Firmware encryption using libTomCrypt -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include "libtomcrypt.h" -#include -#include -#include "config.h" - -#if defined(USE_ENCRYPTION) && (defined(ENCRYPTION_AES_LTC) || defined(ENCRYPTION_3DES_LTC)) -#include -#include -#include -#include -#include - -//------------------------------------------------------------------------------ -// Global variables -//------------------------------------------------------------------------------ - -#if defined(ENCRYPTION_ECB) - symmetric_ECB sECB; -#endif -#if defined(ENCRYPTION_CBC) - symmetric_CBC sCBC; -#endif -#if defined(ENCRYPTION_CTR) - symmetric_CTR sCTR; -#endif - -//------------------------------------------------------------------------------ -// Inline functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Converts an ASCII string to an hexadecimal value -/// \param ASCII string to convert -/// \param Buffer to store converted value -/// \param Length of buffer -//------------------------------------------------------------------------------ -static inline void ASCII2Hex(const char * ascii, unsigned char * binary, unsigned int length) -{ - unsigned int i; - - for (i=0; i < length; i++) { - if (ascii[i*2] >= 'A') { - binary[i] = ascii[i*2] - 'A' + 10; - } - else { - binary[i] = ascii[i*2] - '0'; - } - binary[i] <<= 4; - if (ascii[i*2+1] >= 'A') { - binary[i] += ascii[i*2+1] - 'A' + 10; - } - else { - binary[i] += ascii[i*2+1] - '0'; - } - } -} - -//------------------------------------------------------------------------------ -// Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Initializes the decryption process -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -void ltc_init(void) -{ - int cipherID; - unsigned char key[ENCRYPTION_KEY_LENGTH]; - -#if defined(ENCRYPTION_CTR) || defined(ENCRYPTION_CBC) - unsigned char IV[ENCRYPTION_BLOCK_LENGTH]; -#endif - - TRACE_DEBUG("LTC: Initializing ...\n\r"); - - // Register cipher - register_cipher(&CIPHER_DESC); - cipherID = find_cipher(CIPHER_NAME); - - // Load key - ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - -#if defined(ENCRYPTION_CTR) || defined(ENCRYPTION_CBC) - // Load IV - ASCII2Hex(ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); -#endif - - // Start decryption mode -#if defined(ENCRYPTION_ECB) - ecb_start(cipherID, key, ENCRYPTION_KEY_LENGTH, 0, &sECB); -#elif defined(ENCRYPTION_CBC) - cbc_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, &sCBC); -#elif defined(ENCRYPTION_CTR) - ctr_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, CTR_COUNTER_BIG_ENDIAN, &sCTR); -#endif - - TRACE_DEBUG("LTC: Initialization done.\n\r"); -} -#endif // ONLY_ONE_ENCRYPTION - -//------------------------------------------------------------------------------ -/// Initializes the decryption process for AES, mode CBC -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -#if defined(ENCRYPTION_CBC) -void ltc_init_AES_CBC(void) -{ - int cipherID; - unsigned char key[ENCRYPTION_KEY_LENGTH]; - unsigned char IV[ENCRYPTION_BLOCK_LENGTH]; - - TRACE_DEBUG("LTC: Initializing CBC...\n\r"); - - // Register cipher - register_cipher(&rijndael_desc); - cipherID = find_cipher("rijndael"); - - // Load key - ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - // Load IV - ASCII2Hex(ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - // Start decryption mode - cbc_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, &sCBC); - - TRACE_DEBUG("LTC: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the decryption process for AES, mode CTR -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -void ltc_init_AES_CTR(void) -{ - int cipherID; - unsigned char key[ENCRYPTION_KEY_LENGTH]; - unsigned char IV[ENCRYPTION_BLOCK_LENGTH]; - - TRACE_DEBUG("LTC: Initializing CTR...\n\r"); - - // Register cipher - register_cipher(&rijndael_desc); - cipherID = find_cipher("rijndael"); - - // Load key - ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - // Load IV - ASCII2Hex(ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - // Start decryption mode - ctr_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, CTR_COUNTER_BIG_ENDIAN, &sCTR); - - TRACE_DEBUG("LTC: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the decryption process for AES, mode ECB -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) -void ltc_init_AES_ECB(void) -{ - int cipherID; - unsigned char key[ENCRYPTION_KEY_LENGTH]; - - TRACE_DEBUG("LTC: Initializing ECB...\n\r"); - - // Register cipher - register_cipher(&rijndael_desc); - cipherID = find_cipher("rijndael"); - - // Load key - ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - // Start decryption mode - ecb_start(cipherID, key, ENCRYPTION_KEY_LENGTH, 0, &sECB); - - TRACE_DEBUG("LTC: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the decryption process for 3DES, mode CBC -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CBC) -void ltc_init_3DES_CBC(void) -{ - int cipherID; - unsigned char key[ENCRYPTION_KEY_LENGTH]; - unsigned char IV[ENCRYPTION_BLOCK_LENGTH]; - - TRACE_DEBUG("LTC: Initializing CBC...\n\r"); - - // Register cipher - register_cipher(&des3_desc); - cipherID = find_cipher("3des"); - - // Load key - ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - // Load IV - ASCII2Hex(ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - // Start decryption mode - cbc_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, &sCBC); - - TRACE_DEBUG("LTC: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the decryption process for 3DES, mode CTR -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -void ltc_init_3DES_CTR(void) -{ - int cipherID; - unsigned char key[ENCRYPTION_KEY_LENGTH]; - unsigned char IV[ENCRYPTION_BLOCK_LENGTH]; - - TRACE_DEBUG("LTC: Initializing CTR...\n\r"); - - // Register cipher - register_cipher(&des3_desc); - cipherID = find_cipher("3des"); - - // Load key - ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - // Load IV - ASCII2Hex(ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - // Start decryption mode - ctr_start(cipherID, IV, key, ENCRYPTION_KEY_LENGTH, 0, CTR_COUNTER_BIG_ENDIAN, &sCTR); - - TRACE_DEBUG("LTC: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the decryption process for 3DES, mode ECB -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) -void ltc_init_3DES_ECB(void) -{ - int cipherID; - unsigned char key[ENCRYPTION_KEY_LENGTH]; - - TRACE_DEBUG("LTC: Initializing ECB...\n\r"); - - // Register cipher - register_cipher(&des3_desc); - cipherID = find_cipher("3des"); - - // Load key - ASCII2Hex(ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - // Start decryption mode - ecb_start(cipherID, key, ENCRYPTION_KEY_LENGTH, 0, &sECB); - - TRACE_DEBUG("LTC: Initialization done.\n\r"); -} -#endif -#endif // ONLY_ONE_ENCRYPTION - - -//------------------------------------------------------------------------------ -/// Terminates the decryption process -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -void ltc_cleanup(void) -{ - TRACE_DEBUG("LTC: Cleaning up ...\n\r"); - -#if defined(ENCRYPTION_ECB) - ecb_done(&sECB); -#elif defined(ENCRYPTION_CBC) - cbc_done(&sCBC); -#elif defined(ENCRYPTION_CTR) - ctr_done(&sCTR); -#endif - - TRACE_DEBUG("LTC: Cleanup done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Terminates the decryption process for mode CBC -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -#if defined(ENCRYPTION_CBC) -void ltc_cleanup_CBC(void) -{ - TRACE_DEBUG("LTC: Cleaning up CBC...\n\r"); - cbc_done(&sCBC); - TRACE_DEBUG("LTC: Cleanup done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Terminates the decryption process for mode CTR -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_CTR) -void ltc_cleanup_CTR(void) -{ - TRACE_DEBUG("LTC: Cleaning up CTR...\n\r"); - ctr_done(&sCTR); - TRACE_DEBUG("LTC: Cleanup done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Terminates the decryption process for mode ECB -//------------------------------------------------------------------------------ -#if defined(ENCRYPTION_ECB) -void ltc_cleanup_ECB(void) -{ - TRACE_DEBUG("LTC: Cleaning up ECB...\n\r"); - ecb_done(&sECB); - TRACE_DEBUG("LTC: Cleanup done.\n\r"); -} -#endif -#endif // ONLY_ONE_ENCRYPTION - -//------------------------------------------------------------------------------ -/// Decrypts a block of data -/// \param Data to decrypt -/// \param Buffer to store decrypted data -/// \param Length of data -/// \return 1 if successful, 0 otherwise. -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -int ltc_decrypt(const unsigned char * cipherText, unsigned char * plainText, unsigned int length) -{ -#if defined(ENCRYPTION_ECB) - if (ecb_decrypt(cipherText, plainText, length, &sECB) != CRYPT_OK) { -#elif defined(ENCRYPTION_CBC) - if (cbc_decrypt(cipherText, plainText, length, &sCBC) != CRYPT_OK) { -#elif defined(ENCRYPTION_CTR) - if (ctr_decrypt(cipherText, plainText, length, &sCTR) != CRYPT_OK) { -#endif - return 0; - } - else { - return 1; - } -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypts a block of data in CBC mode -/// \param Data to decrypt -/// \param Buffer to store decrypted data -/// \param Length of data -/// \return 1 if successful, 0 otherwise. -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -int ltc_decrypt_CBC(const unsigned char * cipherText, unsigned char * plainText, unsigned int length) -{ - if (cbc_decrypt(cipherText, plainText, length, &sCBC) != CRYPT_OK) { - return 0; - } - else { - return 1; - } -} - -//------------------------------------------------------------------------------ -/// Decrypts a block of data in CTR mode -/// \param Data to decrypt -/// \param Buffer to store decrypted data -/// \param Length of data -/// \return 1 if successful, 0 otherwise. -//------------------------------------------------------------------------------ -int ltc_decrypt_CTR(const unsigned char * cipherText, unsigned char * plainText, unsigned int length) -{ - if (ctr_decrypt(cipherText, plainText, length, &sCTR) != CRYPT_OK) { - return 0; - } - else { - return 1; - } -} - -//------------------------------------------------------------------------------ -/// Decrypts a block of data in ECB mode -/// \param Data to decrypt -/// \param Buffer to store decrypted data -/// \param Length of data -/// \return 1 if successful, 0 otherwise. -//------------------------------------------------------------------------------ -int ltc_decrypt_ECB(const unsigned char * cipherText, unsigned char * plainText, unsigned int length) -{ - if (ecb_decrypt(cipherText, plainText, length, &sECB) != CRYPT_OK) { - return 0; - } - else { - return 1; - } -} -#endif // ONLY_ONE_ENCRYPTION - -#endif // defined(USE_ENCRYPTION) && (defined(ENCRYPTION_AES_LTC) || defined(ENCRYPTION_3DES_LTC)) - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/libtomcrypt.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/libtomcrypt.h deleted file mode 100644 index 317b79f28..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/libtomcrypt.h +++ /dev/null @@ -1,149 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// Firmware encryption using libTomCrypt -/// -/// !Usage -/// -/// -# ltc_init: Initialize LibTomCrypt -/// -# ltc_init_AES_CBC -/// -# ltc_init_AES_CTR -/// -# ltc_init_AES_ECB -/// -# ltc_init_3DES_CBC -/// -# ltc_init_3DES_CTR -/// -# ltc_init_3DES_ECB -/// -# ltc_cleanup -/// -# ltc_cleanup_CBC -/// -# ltc_cleanup_CTR -/// -# ltc_cleanup_ECB -/// -# ltc_decrypt -/// -# ltc_decrypt_CBC -/// -# ltc_decrypt_CTR -/// -# ltc_decrypt_ECB -//------------------------------------------------------------------------------ - -#ifndef BOOTLOADER_LIBTOMCRYPT_H -#define BOOTLOADER_LIBTOMCRYPT_H - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include "config.h" - -#if defined(USE_ENCRYPTION) && (defined(ENCRYPTION_AES_LTC) || defined(ENCRYPTION_3DES_LTC)) - -//------------------------------------------------------------------------------ -// Check configuration -//------------------------------------------------------------------------------ - -// Supported modes -#if !defined(ENCRYPTION_CTR) && \ - !defined(ENCRYPTION_CBC) && \ - !defined(ENCRYPTION_ECB) - #error No other mode than ECB, CBC & CTR are supported. -#endif - -// Supported key length -#if defined(ENCRYPTION_AES_LTC) - #if (ENCRYPTION_KEY_LENGTH != 16) && \ - (ENCRYPTION_KEY_LENGTH != 24) && \ - (ENCRYPTION_KEY_LENGTH != 32) - #error Only a key length of 128, 192 or 256 bits are supported with AES. - #endif -#elif defined(ENCRYPTION_3DES_LTC) - #if (ENCRYPTION_KEY_LENGTH != 16) && \ - (ENCRYPTION_KEY_LENGTH != 24) - #error Only a key length of 128 or 192 bits are supported with Triple-DES. - #endif -#endif - -// Supported block length -#if defined(ENCRYPTION_AES_LTC) - #if (ENCRYPTION_BLOCK_LENGTH != 16) - #error Only a block length of 128 bits is supported with AES. - #endif -#elif defined(ENCRYPTION_3DES_LTC) - #if (ENCRYPTION_BLOCK_LENGTH != 8) - #error Only a block length of 64 bits is supported with Triple-DES. - #endif -#endif - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ - -// Functions -#ifdef ONLY_ONE_ENCRYPTION -#define ENCRYPTION_INIT ltc_init -#define ENCRYPTION_CLEANUP ltc_cleanup -#define ENCRYPTION_DECRYPT ltc_decrypt - -#if defined(ENCRYPTION_AES_LTC) - #define CIPHER_NAME "rijndael" - #define CIPHER_DESC rijndael_desc -#elif defined(ENCRYPTION_3DES_LTC) - #define CIPHER_NAME "3des" - #define CIPHER_DESC des3_desc -#endif -#endif - -//------------------------------------------------------------------------------ -// Prototypes -//------------------------------------------------------------------------------ - -#ifdef ONLY_ONE_ENCRYPTION -extern void ltc_init(void); -#endif -extern void ltc_init_AES_CBC(void); -extern void ltc_init_AES_CTR(void); -extern void ltc_init_AES_ECB(void); -extern void ltc_init_3DES_CBC(void); -extern void ltc_init_3DES_CTR(void); -extern void ltc_init_3DES_ECB(void); - -extern void ltc_cleanup(void); -extern void ltc_cleanup_CBC(void); -extern void ltc_cleanup_CTR(void); -extern void ltc_cleanup_ECB(void); - -extern int ltc_decrypt(const unsigned char * cipherText, unsigned char * plainText, unsigned int length); -extern int ltc_decrypt_CBC(const unsigned char * cipherText, unsigned char * plainText, unsigned int length); -extern int ltc_decrypt_CTR(const unsigned char * cipherText, unsigned char * plainText, unsigned int length); -extern int ltc_decrypt_ECB(const unsigned char * cipherText, unsigned char * plainText, unsigned int length); - -#endif // defined(USE_ENCRYPTION) && (defined(ENCRYPTION_AES_LTC) || defined(ENCRYPTION_3DES_LTC)) -#endif // BOOTLOADER_AES_LIBTOMCRYPT_H - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/tdes_hardware.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/tdes_hardware.c deleted file mode 100644 index 7b5701032..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/tdes_hardware.c +++ /dev/null @@ -1,520 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Function: Firmware encryption using TDES hardware acceleration -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include "tdes_hardware.h" - -#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_3DES_HARD) -#include -#include -#include -#include -#include -#include - -//------------------------------------------------------------------------------ -// Global variables -//------------------------------------------------------------------------------ - -#ifdef ENCRYPTION_CTR - unsigned char CTR[ENCRYPTION_BLOCK_LENGTH]; -#endif - -//------------------------------------------------------------------------------ -// Inline functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Converts an ASCII value to an hexadecimal one -/// \param ASCII string -/// \param Buffer to store integer value -/// \param Length of string -//------------------------------------------------------------------------------ -static inline void ASCII2Hex(const unsigned char * ascii, unsigned char * binary, unsigned int length) -{ - unsigned int i; - - for (i=0; i < length; i++) { - if (ascii[i*2] >= 'A') { - binary[i] = ascii[i*2] - 'A' + 10; - } - else { - binary[i] = ascii[i*2] - '0'; - } - binary[i] <<= 4; - if (ascii[i*2+1] >= 'A') { - binary[i] += ascii[i*2+1] - 'A' + 10; - } - else { - binary[i] += ascii[i*2+1] - '0'; - } - } -} -//------------------------------------------------------------------------------ -// Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Initializes the TDES peripheral -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -void tdes_hard_init(void) -{ - unsigned char key[ENCRYPTION_KEY_LENGTH]; - - TRACE_DEBUG("TDES/HARD: Initializing ...\n\r"); - - // Activate peripheral clock -#ifdef AT91C_ID_AES - PMC_EnablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_EnablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_EnablePeripheral( AT91C_ID_TDES ); -#else -#error AES/TDES undefined -#endif - - // Load mode -#if (ENCRYPTION_KEY_LENGTH == 24) - AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | TDES_MODE - | AT91C_TDES_TDESMOD | TDES_CIPHER; -#else - AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | TDES_MODE | AT91C_TDES_KEYMOD - | AT91C_TDES_TDESMOD | TDES_CIPHER; -#endif - - // Convert and load key - ASCII2Hex((unsigned char*)ENCRYPTION_KEY, key, ENCRYPTION_KEY_LENGTH); - - AT91C_BASE_TDES->TDES_KEY1WxR[0] = ((int *) key)[0]; - AT91C_BASE_TDES->TDES_KEY1WxR[1] = ((int *) key)[1]; - AT91C_BASE_TDES->TDES_KEY2WxR[0] = ((int *) key)[2]; - AT91C_BASE_TDES->TDES_KEY2WxR[1] = ((int *) key)[3]; - -#if (ENCRYPTION_KEY_LENGTH == 24) - AT91C_BASE_TDES->TDES_KEY3WxR[0] = ((int *) key)[4]; - AT91C_BASE_TDES->TDES_KEY3WxR[1] = ((int *) key)[5]; -#endif - -#if defined(ENCRYPTION_CBC) - unsigned char IV[8]; - ASCII2Hex((unsigned char*)ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - AT91C_BASE_TDES->TDES_IVxR[0] = ((int *) IV)[0]; - AT91C_BASE_TDES->TDES_IVxR[1] = ((int *) IV)[1]; - -#elif defined(ENCRYPTION_CTR) - // Convert IV - ASCII2Hex((unsigned char*)ENCRYPTION_IV, CTR, ENCRYPTION_BLOCK_LENGTH); -#endif - - TRACE_DEBUG("TDES/HARD: Initialization done.\n\r"); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the DES peripheral for CBC mode -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -void tdes_hard_init_CBC(void) -{ - unsigned char key[TDES_ENCRYPTION_KEY_LENGTH]; - - TRACE_DEBUG("tdes_hard_init_CBC\n\r"); - - // Activate peripheral clock -#ifdef AT91C_ID_AES - PMC_EnablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_EnablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_EnablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - - // Load mode -#if (TDES_ENCRYPTION_KEY_LENGTH == 24) - AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_CBC - | AT91C_TDES_TDESMOD | 0; -#else - AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_CBC | AT91C_TDES_KEYMOD - | AT91C_TDES_TDESMOD | 0; -#endif - - // Convert and load key - ASCII2Hex((unsigned char*)TDES_ENCRYPTION_KEY, key, TDES_ENCRYPTION_KEY_LENGTH); - - AT91C_BASE_TDES->TDES_KEY1WxR[0] = ((int *) key)[0]; - AT91C_BASE_TDES->TDES_KEY1WxR[1] = ((int *) key)[1]; - AT91C_BASE_TDES->TDES_KEY2WxR[0] = ((int *) key)[2]; - AT91C_BASE_TDES->TDES_KEY2WxR[1] = ((int *) key)[3]; - -#if (TDES_ENCRYPTION_KEY_LENGTH == 24) - AT91C_BASE_TDES->TDES_KEY3WxR[0] = ((int *) key)[4]; - AT91C_BASE_TDES->TDES_KEY3WxR[1] = ((int *) key)[5]; -#endif - - unsigned char IV[8]; - ASCII2Hex((unsigned char*)ENCRYPTION_IV, IV, ENCRYPTION_BLOCK_LENGTH); - - AT91C_BASE_TDES->TDES_IVxR[0] = ((int *) IV)[0]; - AT91C_BASE_TDES->TDES_IVxR[1] = ((int *) IV)[1]; -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the DES peripheral for CTR mode -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -void tdes_hard_init_CTR(void) -{ - unsigned char key[TDES_ENCRYPTION_KEY_LENGTH]; - - TRACE_DEBUG("tdes_hard_init_CTR\n\r"); - - // Activate peripheral clock -#ifdef AT91C_ID_AES - PMC_EnablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_EnablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_EnablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - - // Load mode -#if (TDES_ENCRYPTION_KEY_LENGTH == 24) - AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_ECB - | AT91C_TDES_TDESMOD | AT91C_TDES_CIPHER; -#else - AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_ECB | AT91C_TDES_KEYMOD - | AT91C_TDES_TDESMOD | AT91C_TDES_CIPHER; -#endif - - // Convert and load key - ASCII2Hex((unsigned char*)TDES_ENCRYPTION_KEY, key, TDES_ENCRYPTION_KEY_LENGTH); - - AT91C_BASE_TDES->TDES_KEY1WxR[0] = ((int *) key)[0]; - AT91C_BASE_TDES->TDES_KEY1WxR[1] = ((int *) key)[1]; - AT91C_BASE_TDES->TDES_KEY2WxR[0] = ((int *) key)[2]; - AT91C_BASE_TDES->TDES_KEY2WxR[1] = ((int *) key)[3]; - -#if (TDES_ENCRYPTION_KEY_LENGTH == 24) - AT91C_BASE_TDES->TDES_KEY3WxR[0] = ((int *) key)[4]; - AT91C_BASE_TDES->TDES_KEY3WxR[1] = ((int *) key)[5]; -#endif - - // Convert IV - ASCII2Hex((unsigned char*)ENCRYPTION_IV, CTR, ENCRYPTION_BLOCK_LENGTH); -} -#endif - -//------------------------------------------------------------------------------ -/// Initializes the DES peripheral for ECB mode -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -void tdes_hard_init_ECB(void) -{ - unsigned char key[TDES_ENCRYPTION_KEY_LENGTH]; - - TRACE_DEBUG("tdes_hard_init_ECB\n\r"); - - // Activate peripheral clock -#ifdef AT91C_ID_AES - PMC_EnablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_EnablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_EnablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - - // Load mode -#if (TDES_ENCRYPTION_KEY_LENGTH == 24) - AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_ECB - | AT91C_TDES_TDESMOD | 0; -#else - AT91C_BASE_TDES->TDES_MR = AT91C_TDES_SMOD_MANUAL | AT91C_TDES_OPMOD_ECB | AT91C_TDES_KEYMOD - | AT91C_TDES_TDESMOD | 0; -#endif - - // Convert and load key - ASCII2Hex((unsigned char*)TDES_ENCRYPTION_KEY, key, TDES_ENCRYPTION_KEY_LENGTH); - - AT91C_BASE_TDES->TDES_KEY1WxR[0] = ((int *) key)[0]; - AT91C_BASE_TDES->TDES_KEY1WxR[1] = ((int *) key)[1]; - AT91C_BASE_TDES->TDES_KEY2WxR[0] = ((int *) key)[2]; - AT91C_BASE_TDES->TDES_KEY2WxR[1] = ((int *) key)[3]; - -#if (TDES_ENCRYPTION_KEY_LENGTH == 24) - AT91C_BASE_TDES->TDES_KEY3WxR[0] = ((int *) key)[4]; - AT91C_BASE_TDES->TDES_KEY3WxR[1] = ((int *) key)[5]; -#endif -} -#endif - -//------------------------------------------------------------------------------ -/// Cleans up the DES peripheral -//------------------------------------------------------------------------------ -void tdes_hard_cleanup(void) -{ - TRACE_DEBUG("TDES/HARD: Cleaning up ...\n\r"); - AT91C_BASE_TDES->TDES_MR = 0; -#ifdef AT91C_ID_AES - PMC_DisablePeripheral( AT91C_ID_AES ); -#elif AT91C_ID_AESTDES - PMC_DisablePeripheral( AT91C_ID_AESTDES ); -#elif AT91C_ID_TDES - PMC_DisablePeripheral( AT91C_ID_TDES ); -#else -#error AES undefined -#endif - TRACE_DEBUG("TDES/HARD: Cleanup done.\n\r"); -} - -//------------------------------------------------------------------------------ -/// Decrypts a variable-length cipher text -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -int tdes_hard_decrypt(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length) -{ - unsigned int l; - - TRACE_DEBUG("tdes_hard_decrypt\n\r"); - -#if defined(ENCRYPTION_ECB) || defined(ENCRYPTION_CBC) - for (l=0; l < length;) { - - // Load counter and encrypt it - AT91C_BASE_TDES->TDES_IDATAxR[0] = ((int *) &cipherText[l])[0]; - AT91C_BASE_TDES->TDES_IDATAxR[1] = ((int *) &cipherText[l])[1]; - - // Start processing - AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START; - - while (!((AT91C_BASE_TDES->TDES_ISR) & AT91C_TDES_DATRDY)); - - ((int *) &plainText[l])[0] = AT91C_BASE_TDES->TDES_ODATAxR[0]; - ((int *) &plainText[l])[1] = AT91C_BASE_TDES->TDES_ODATAxR[1]; - - l += ENCRYPTION_BLOCK_LENGTH; - } - -#elif defined(ENCRYPTION_CTR) - unsigned int bytes; - unsigned char block[ENCRYPTION_BLOCK_LENGTH]; - unsigned int e; - unsigned int i; - int k; - - // Decrypt - for (e=0; e < length;) { - - // Load counter and encrypt it - AT91C_BASE_TDES->TDES_IDATAxR[0] = ((int *) CTR)[0]; - AT91C_BASE_TDES->TDES_IDATAxR[1] = ((int *) CTR)[1]; - - AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START; - while (!(AT91C_BASE_TDES->TDES_ISR & AT91C_TDES_DATRDY)); - - ((int *) block)[0] = AT91C_BASE_TDES->TDES_ODATAxR[0]; - ((int *) block)[1] = AT91C_BASE_TDES->TDES_ODATAxR[1]; - - // XOR current plain text block with encrypted counter - if ((length-e) < ENCRYPTION_BLOCK_LENGTH) { - bytes = length - e; - } - else { - bytes = ENCRYPTION_BLOCK_LENGTH; - } - - for (i=0; i < bytes; i++) { - plainText[e+i] = cipherText[e+i] ^ ((char *) block)[i]; - } - - // Increment counter (big-endian) and number of encrypted bytes - for (k=ENCRYPTION_BLOCK_LENGTH-1; k >= 0; k--) { - if (++((char *) CTR)[k] != 0) { - break; - } - } - e += bytes; - } -#endif // ENCRYPTION_CTR - - return 1; -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypts a variable-length cipher text for CBC mode -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -int tdes_hard_decrypt_CBC(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length) -{ - unsigned int l; - - TRACE_DEBUG("tdes_hard_decrypt_CBC\n\r"); - - for (l=0; l < length;) { - // Load counter and encrypt it - AT91C_BASE_TDES->TDES_IDATAxR[0] = ((int *) &cipherText[l])[0]; - AT91C_BASE_TDES->TDES_IDATAxR[1] = ((int *) &cipherText[l])[1]; - - // Start processing - AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START; - - while (!((AT91C_BASE_TDES->TDES_ISR) & AT91C_TDES_DATRDY)); - - ((int *) &plainText[l])[0] = AT91C_BASE_TDES->TDES_ODATAxR[0]; - ((int *) &plainText[l])[1] = AT91C_BASE_TDES->TDES_ODATAxR[1]; - - l += ENCRYPTION_BLOCK_LENGTH; - } - return 1; -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypts a variable-length cipher text for CTR mode -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -int tdes_hard_decrypt_CTR(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length) -{ - unsigned int bytes; - unsigned char block[ENCRYPTION_BLOCK_LENGTH]; - unsigned int e; - unsigned int i; - int k; - - TRACE_DEBUG("tdes_hard_decrypt_CTR\n\r"); - - // Decrypt - for (e=0; e < length;) { - - // Load counter and encrypt it - AT91C_BASE_TDES->TDES_IDATAxR[0] = ((int *) CTR)[0]; - AT91C_BASE_TDES->TDES_IDATAxR[1] = ((int *) CTR)[1]; - - AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START; - while (!(AT91C_BASE_TDES->TDES_ISR & AT91C_TDES_DATRDY)); - - ((int *) block)[0] = AT91C_BASE_TDES->TDES_ODATAxR[0]; - ((int *) block)[1] = AT91C_BASE_TDES->TDES_ODATAxR[1]; - - // XOR current plain text block with encrypted counter - if ((length-e) < ENCRYPTION_BLOCK_LENGTH) { - bytes = length - e; - } - else { - bytes = ENCRYPTION_BLOCK_LENGTH; - } - - for (i=0; i < bytes; i++) { - plainText[e+i] = cipherText[e+i] ^ ((char *) block)[i]; - } - - // Increment counter (big-endian) and number of encrypted bytes - for (k=ENCRYPTION_BLOCK_LENGTH-1; k >= 0; k--) { - if (++((char *) CTR)[k] != 0) { - break; - } - } - e += bytes; - } - - return 1; -} -#endif - -//------------------------------------------------------------------------------ -/// Decrypts a variable-length cipher text for ECB mode -/// \param Cipher text to decrypt -/// \param Buffer to store plain text -/// \param Length of cipher text (in bytes) -//------------------------------------------------------------------------------ -#ifndef ONLY_ONE_ENCRYPTION -int tdes_hard_decrypt_ECB(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length) -{ - unsigned int l; - - TRACE_DEBUG("tdes_hard_decrypt_ECB\n\r"); - - for (l=0; l < length;) { - - // Load counter and encrypt it - AT91C_BASE_TDES->TDES_IDATAxR[0] = ((int *) &cipherText[l])[0]; - AT91C_BASE_TDES->TDES_IDATAxR[1] = ((int *) &cipherText[l])[1]; - - // Start processing - AT91C_BASE_TDES->TDES_CR = AT91C_TDES_START; - - while (!((AT91C_BASE_TDES->TDES_ISR) & AT91C_TDES_DATRDY)); - - ((int *) &plainText[l])[0] = AT91C_BASE_TDES->TDES_ODATAxR[0]; - ((int *) &plainText[l])[1] = AT91C_BASE_TDES->TDES_ODATAxR[1]; - - l += ENCRYPTION_BLOCK_LENGTH; - } - return 1; -} -#endif - -#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_3DES_HARD) - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/tdes_hardware.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/tdes_hardware.h deleted file mode 100644 index 28fb774b5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/encryption/tdes_hardware.h +++ /dev/null @@ -1,125 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// Firmware encryption using TDES hardware acceleration -/// -/// !Usage -/// -/// -# tdes_hard_init: Initialize TDES hardware -/// -# tdes_hard_init_CBC: for the CBC mode -/// -# tdes_hard_init_ECB: for the CTR mode -/// -# tdes_hard_init_CTR: for the ECB mode -/// -# tdes_hard_cleanup: Cleans up DES -/// -# tdes_hard_decrypt: Decrypts a variable-length cipher text -/// -# tdes_hard_decrypt_CBC: for CBC mode -/// -# tdes_hard_decrypt_ECB: for ECB mode -/// -# tdes_hard_decrypt_CTR: for CTR mode -//------------------------------------------------------------------------------ -#ifndef BOOTLOADER_TDES_HARDWARE_H -#define BOOTLOADER_TDES_HARDWARE_H - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include "config.h" - -#if defined(USE_ENCRYPTION) && defined(ENCRYPTION_3DES_HARD) - -//------------------------------------------------------------------------------ -// Check configuration -//------------------------------------------------------------------------------ - -#ifdef ONLY_ONE_ENCRYPTION -#if (ENCRYPTION_KEY_LENGTH != 16) && (ENCRYPTION_KEY_LENGTH != 24) - #error Triple-DES hardware acceleration only supports 128 and 192 bits keys. -#endif - -#if (ENCRYPTION_BLOCK_LENGTH != 8) - #error Triple-DES hardware acceleration only supports 64 bits blocks. -#endif - -#if !defined(ENCRYPTION_ECB) && \ - !defined(ENCRYPTION_CBC) && \ - !defined(ENCRYPTION_CTR) - #error Only ECB, CBC & CTR mode are supported. -#endif - -//------------------------------------------------------------------------------ -// Definitions -//------------------------------------------------------------------------------ -#define ENCRYPTION_INIT tdes_hard_init -#define ENCRYPTION_CLEANUP tdes_hard_cleanup -#define ENCRYPTION_DECRYPT tdes_hard_decrypt - -#if defined(ENCRYPTION_ECB) - #define TDES_MODE AT91C_TDES_OPMOD_ECB - #define TDES_CIPHER 0 -#elif defined(ENCRYPTION_CBC) - #define TDES_MODE AT91C_TDES_OPMOD_CBC - #define TDES_CIPHER 0 -#elif defined(ENCRYPTION_CTR) - #define TDES_MODE AT91C_TDES_OPMOD_ECB - #define TDES_CIPHER AT91C_TDES_CIPHER -#endif - -#endif // ONLY_ONE_ENCRYPTION - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -#ifdef ONLY_ONE_ENCRYPTION -extern void tdes_hard_init(void); -#endif -extern void tdes_hard_init_CBC(void); -extern void tdes_hard_init_CTR(void); -extern void tdes_hard_init_ECB(void); -extern void tdes_hard_cleanup(void); -extern int tdes_hard_decrypt(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length); -extern int tdes_hard_decrypt_CBC(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length); -extern int tdes_hard_decrypt_CTR(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length); -extern int tdes_hard_decrypt_ECB(const unsigned char * cipherText, - unsigned char * plainText, - unsigned int length); - - -#endif // defined(USE_ENCRYPTION) && defined(ENCRYPTION_3DES_HARD) -#endif // BOOTLOADER_DES_HARDWARE_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/hamming.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/hamming.c deleted file mode 100644 index 2b1b89054..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/hamming.c +++ /dev/null @@ -1,335 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "hamming.h" -#include -#include - -//------------------------------------------------------------------------------ -// Internal function -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Counts and return the number of bits set to '1' in the given byte. -/// \param byte Byte to count. -//------------------------------------------------------------------------------ -static unsigned char CountBitsInByte(unsigned char byte) -{ - unsigned char count = 0; - while (byte > 0) { - - if (byte & 1) { - - count++; - } - byte >>= 1; - } - - return count; -} - -//------------------------------------------------------------------------------ -/// Counts and return the number of bits set to '1' in the given hamming code. -/// \param code Hamming code. -//------------------------------------------------------------------------------ -static unsigned char CountBitsInCode256(unsigned char *code) -{ - return CountBitsInByte(code[0]) - + CountBitsInByte(code[1]) - + CountBitsInByte(code[2]); -} - -//------------------------------------------------------------------------------ -/// Calculates the 22-bit hamming code for a 256-bytes block of data. -/// \param data Data buffer to calculate code for. -/// \param code Pointer to a buffer where the code should be stored. -//------------------------------------------------------------------------------ -static void Compute256(const unsigned char *data, unsigned char *code) -{ - unsigned int i; - unsigned char columnSum = 0; - unsigned char evenLineCode = 0; - unsigned char oddLineCode = 0; - unsigned char evenColumnCode = 0; - unsigned char oddColumnCode = 0; - - // Xor all bytes together to get the column sum; - // At the same time, calculate the even and odd line codes - for (i=0; i < 256; i++) { - - columnSum ^= data[i]; - - // If the xor sum of the byte is 0, then this byte has no incidence on - // the computed code; so check if the sum is 1. - if ((CountBitsInByte(data[i]) & 1) == 1) { - - // Parity groups are formed by forcing a particular index bit to 0 - // (even) or 1 (odd). - // Example on one byte: - // - // bits (dec) 7 6 5 4 3 2 1 0 - // (bin) 111 110 101 100 011 010 001 000 - // '---'---'---'----------. - // | - // groups P4' ooooooooooooooo eeeeeeeeeeeeeee P4 | - // P2' ooooooo eeeeeee ooooooo eeeeeee P2 | - // P1' ooo eee ooo eee ooo eee ooo eee P1 | - // | - // We can see that: | - // - P4 -> bit 2 of index is 0 --------------------' - // - P4' -> bit 2 of index is 1. - // - P2 -> bit 1 of index if 0. - // - etc... - // We deduce that a bit position has an impact on all even Px if - // the log2(x)nth bit of its index is 0 - // ex: log2(4) = 2, bit2 of the index must be 0 (-> 0 1 2 3) - // and on all odd Px' if the log2(x)nth bit of its index is 1 - // ex: log2(2) = 1, bit1 of the index must be 1 (-> 0 1 4 5) - // - // As such, we calculate all the possible Px and Px' values at the - // same time in two variables, evenLineCode and oddLineCode, such as - // evenLineCode bits: P128 P64 P32 P16 P8 P4 P2 P1 - // oddLineCode bits: P128' P64' P32' P16' P8' P4' P2' P1' - // - evenLineCode ^= (255 - i); - oddLineCode ^= i; - } - } - - // At this point, we have the line parities, and the column sum. First, We - // must caculate the parity group values on the column sum. - for (i=0; i < 8; i++) { - - if (columnSum & 1) { - - evenColumnCode ^= (7 - i); - oddColumnCode ^= i; - } - columnSum >>= 1; - } - - // Now, we must interleave the parity values, to obtain the following layout: - // Code[0] = Line1 - // Code[1] = Line2 - // Code[2] = Column - // Line = Px' Px P(x-1)- P(x-1) ... - // Column = P4' P4 P2' P2 P1' P1 PadBit PadBit - code[0] = 0; - code[1] = 0; - code[2] = 0; - - for (i=0; i < 4; i++) { - - code[0] <<= 2; - code[1] <<= 2; - code[2] <<= 2; - - // Line 1 - if ((oddLineCode & 0x80) != 0) { - - code[0] |= 2; - } - if ((evenLineCode & 0x80) != 0) { - - code[0] |= 1; - } - - // Line 2 - if ((oddLineCode & 0x08) != 0) { - - code[1] |= 2; - } - if ((evenLineCode & 0x08) != 0) { - - code[1] |= 1; - } - - // Column - if ((oddColumnCode & 0x04) != 0) { - - code[2] |= 2; - } - if ((evenColumnCode & 0x04) != 0) { - - code[2] |= 1; - } - - oddLineCode <<= 1; - evenLineCode <<= 1; - oddColumnCode <<= 1; - evenColumnCode <<= 1; - } - - // Invert codes (linux compatibility) - code[0] = ~code[0]; - code[1] = ~code[1]; - code[2] = ~code[2]; - - TRACE_DEBUG("Computed code = %02X %02X %02X\n\r", - code[0], code[1], code[2]); -} - -//------------------------------------------------------------------------------ -/// Verifies and corrects a 256-bytes block of data using the given 22-bits -/// hamming code. -/// Returns 0 if there is no error, otherwise returns a HAMMING_ERROR code. -/// \param data Data buffer to check. -/// \param originalCode Hamming code to use for verifying the data. -//------------------------------------------------------------------------------ -static unsigned char Verify256( - unsigned char *data, - const unsigned char *originalCode) -{ - // Calculate new code - unsigned char computedCode[3]; - unsigned char correctionCode[3]; - Compute256(data, computedCode); - - // Xor both codes together - correctionCode[0] = computedCode[0] ^ originalCode[0]; - correctionCode[1] = computedCode[1] ^ originalCode[1]; - correctionCode[2] = computedCode[2] ^ originalCode[2]; - - TRACE_DEBUG("Correction code = %02X %02X %02X\n\r", - correctionCode[0], correctionCode[1], correctionCode[2]); - - // If all bytes are 0, there is no error - if ((correctionCode[0] == 0) - && (correctionCode[1] == 0) - && (correctionCode[2] == 0)) { - - return 0; - } - // If there is a single bit error, there are 11 bits set to 1 - if (CountBitsInCode256(correctionCode) == 11) { - - // Get byte and bit indexes - unsigned char byte = correctionCode[0] & 0x80; - byte |= (correctionCode[0] << 1) & 0x40; - byte |= (correctionCode[0] << 2) & 0x20; - byte |= (correctionCode[0] << 3) & 0x10; - - byte |= (correctionCode[1] >> 4) & 0x08; - byte |= (correctionCode[1] >> 3) & 0x04; - byte |= (correctionCode[1] >> 2) & 0x02; - byte |= (correctionCode[1] >> 1) & 0x01; - - unsigned char bit = (correctionCode[2] >> 5) & 0x04; - bit |= (correctionCode[2] >> 4) & 0x02; - bit |= (correctionCode[2] >> 3) & 0x01; - - // Correct bit - TRACE_DEBUG("Correcting byte #%d at bit %d\n\r", byte, bit); - data[byte] ^= (1 << bit); - - return Hamming_ERROR_SINGLEBIT; - } - // Check if ECC has been corrupted - if (CountBitsInCode256(correctionCode) == 1) { - - return Hamming_ERROR_ECC; - } - // Otherwise, this is a multi-bit error - else { - - return Hamming_ERROR_MULTIPLEBITS; - } -} - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Computes 3-bytes hamming codes for a data block whose size is multiple of -/// 256 bytes. Each 256 bytes block gets its own code. -/// \param data Data to compute code for. -/// \param size Data size in bytes. -/// \param code Codes buffer. -//------------------------------------------------------------------------------ -void Hamming_Compute256x( - const unsigned char *data, - unsigned int size, - unsigned char *code) -{ - TRACE_DEBUG("Hamming_Compute256x()\n\r"); - - while (size > 0) { - - Compute256(data, code); - data += 256; - code += 3; - size -= 256; - } -} - -//------------------------------------------------------------------------------ -/// Verifies 3-bytes hamming codes for a data block whose size is multiple of -/// 256 bytes. Each 256-bytes block is verified with its own code. -/// Returns 0 if the data is correct, Hamming_ERROR_SINGLEBIT if one or more -/// block(s) have had a single bit corrected, or either Hamming_ERROR_ECC -/// or Hamming_ERROR_MULTIPLEBITS. -/// \param data Data buffer to verify. -/// \param size Size of the data in bytes. -/// \param code Original codes. -//------------------------------------------------------------------------------ -unsigned char Hamming_Verify256x( - unsigned char *data, - unsigned int size, - const unsigned char *code) -{ - unsigned char error; - unsigned char result = 0; - - TRACE_DEBUG("Hamming_Verify256x()\n\r"); - - while (size > 0) { - - error = Verify256(data, code); - if (error == Hamming_ERROR_SINGLEBIT) { - - result = Hamming_ERROR_SINGLEBIT; - } - else if (error) { - - return error; - } - - data += 256; - code += 3; - size -= 256; - } - - return result; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/hamming.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/hamming.h deleted file mode 100644 index 6e0125d90..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/hamming.h +++ /dev/null @@ -1,72 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef HAMMING_H -#define HAMMING_H - -//------------------------------------------------------------------------------ -// Defines -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// \page "Hamming Code Errors" -/// These are the possible errors when trying to verify a block of data encoded -/// using a Hamming code: -/// -/// !Errors: -/// - Hamming_ERROR_SINGLEBIT -/// - Hamming_ERROR_ECC -/// - Hamming_ERROR_MULTIPLEBITS - -/// A single bit was incorrect but has been recovered. -#define Hamming_ERROR_SINGLEBIT 1 - -/// The original code has been corrupted. -#define Hamming_ERROR_ECC 2 - -/// Multiple bits are incorrect in the data and they cannot be corrected. -#define Hamming_ERROR_MULTIPLEBITS 3 -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern void Hamming_Compute256x( - const unsigned char *data, - unsigned int size, - unsigned char *code); - -extern unsigned char Hamming_Verify256x( - unsigned char *data, - unsigned int size, - const unsigned char *code); - -#endif //#ifndef HAMMING_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/iap.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/iap.c deleted file mode 100644 index c4657e229..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/iap.c +++ /dev/null @@ -1,98 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: IAP implementation - - About: Purpose - IAP feature is avalaible on ATMEL chip with internal FLASH. This allows - the FLASH memory to be programmed even when the code is also running in - FLASH, without writing some SRAM relocated functions. - The IAP function entry point is written in the 3rd exception vector - (SWI at 0x300008), and is retrieved just by reading the value at this - address. - - ROM function algorithm : - // Send Command - AT91_BASE_MC->MC_FCR = FlashCmd - // Wait Flash is ready - while ((AT91C_BASE_MC->MC_FSR & AT91C_MC_FRDY) != AT91C_MC_FRDY) - return -*/ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "iap.h" -#include -#include - -//------------------------------------------------------------------------------ -// Internal variables -//------------------------------------------------------------------------------ - - - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -/* - Function: IAP_PerformCmd - Perform a FLASH command through the IAP function. - - Returns: - 0 if the IAP function has executed correctly. - -1 if the IAP feature is not implemented in the ROM code. -*/ -unsigned long IAP_PerformCmd(unsigned long FlashCmd) -{ - // Pointer on IAP function in ROM - static void (*IAP_Function)(unsigned int) = 0; - - if (IAP_Function == 0) { - - IAP_Function = (void (*)(unsigned int)) (*((unsigned int *) IAP_FUNC_ADDR)); - TRACE_DEBUG("IAP_PerformCmd : IAP function address in ROM : 0x%08X\n\r", (unsigned int) IAP_Function); - - /* Check if IAP function is implemented (opcode in SWI != 'b' or 'ldr') */ - if ((((((unsigned long)IAP_Function >> 24) & 0xFF) == 0xEA) || - (((unsigned long)IAP_Function >> 24) & 0xFF) == 0xE5)) { - TRACE_ERROR("IAP_PerformCmd : no IAP function address found in ROM\n\r"); - IAP_Function = 0; - return -1; - } - } - - /* Perform FLASH command */ - IAP_Function(FlashCmd); - - return 0; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/iap.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/iap.h deleted file mode 100644 index 87a6bcd50..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/iap.h +++ /dev/null @@ -1,51 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/* - Title: IAP - - About: Purpose - Small function for using IAP feature. - - About: Usage - Perform a FLASH command using . - -*/ - -#ifndef IAP_H -#define IAP_H - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned long IAP_PerformCmd (unsigned long FlashCmd); - -#endif //#ifndef IAP_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/led.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/led.c deleted file mode 100644 index a216b2a06..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/led.c +++ /dev/null @@ -1,164 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/// \file - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "led.h" -#include -#include - -//------------------------------------------------------------------------------ -// Local Variables -//------------------------------------------------------------------------------ - -#ifdef PINS_LEDS -static const Pin pinsLeds[] = {PINS_LEDS}; -static const unsigned int numLeds = PIO_LISTSIZE(pinsLeds); -#endif - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Configures the pin associated with the given LED number. If the LED does -/// not exist on the board, the function does nothing. -/// \param led Number of the LED to configure. -/// \return 1 if the LED exists and has been configured; otherwise 0. -//------------------------------------------------------------------------------ -unsigned char LED_Configure(unsigned int led) -{ -#ifdef PINS_LEDS - // Check that LED exists - if (led >= numLeds) { - - return 0; - } - - // Configure LED - return (PIO_Configure(&pinsLeds[led], 1)); -#else - return 0; -#endif -} - -//------------------------------------------------------------------------------ -/// Turns the given LED on if it exists; otherwise does nothing. -/// \param led Number of the LED to turn on. -/// \return 1 if the LED has been turned on; 0 otherwise. -//------------------------------------------------------------------------------ -unsigned char LED_Set(unsigned int led) -{ -#ifdef PINS_LEDS - // Check if LED exists - if (led >= numLeds) { - - return 0; - } - - // Turn LED on - if (pinsLeds[led].type == PIO_OUTPUT_0) { - - PIO_Set(&pinsLeds[led]); - } - else { - - PIO_Clear(&pinsLeds[led]); - } - - return 1; -#else - return 0; -#endif -} - -//------------------------------------------------------------------------------ -/// Turns a LED off. -/// \param led Number of the LED to turn off. -/// \param 1 if the LED has been turned off; 0 otherwise. -//------------------------------------------------------------------------------ -unsigned char LED_Clear(unsigned int led) -{ -#ifdef PINS_LEDS - // Check if LED exists - if (led >= numLeds) { - - return 0; - } - - // Turn LED off - if (pinsLeds[led].type == PIO_OUTPUT_0) { - - PIO_Clear(&pinsLeds[led]); - } - else { - - PIO_Set(&pinsLeds[led]); - } - - return 1; -#else - return 0; -#endif -} - -//------------------------------------------------------------------------------ -/// Toggles the current state of a LED. -/// \param led Number of the LED to toggle. -/// \return 1 if the LED has been toggled; otherwise 0. -//------------------------------------------------------------------------------ -unsigned char LED_Toggle(unsigned int led) -{ -#ifdef PINS_LEDS - // Check if LED exists - if (led >= numLeds) { - - return 0; - } - - // Toggle LED - if (PIO_GetOutputDataStatus(&pinsLeds[led])) { - - PIO_Clear(&pinsLeds[led]); - } - else { - - PIO_Set(&pinsLeds[led]); - } - - return 1; -#else - return 0; -#endif -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/led.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/led.h deleted file mode 100644 index 9a08a82dd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/led.h +++ /dev/null @@ -1,70 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \file -/// -/// \par Purpose -/// -/// Small set of functions for simple and portable LED usage. -/// -/// \par Usage -/// -/// -# Configure one or more LEDs using LED_Configure and -/// LED_ConfigureAll. -/// -# Set, clear and toggle LEDs using LED_Set, LED_Clear and -/// LED_Toggle. -/// -/// LEDs are numbered starting from 0; the number of LEDs depend on the -/// board being used. All the functions defined here will compile properly -/// regardless of whether the LED is defined or not; they will simply -/// return 0 when a LED which does not exist is given as an argument. -/// Also, these functions take into account how each LED is connected on to -/// board; thus, might change the level on the corresponding pin -/// to 0 or 1, but it will always light the LED on; same thing for the other -/// methods. -//------------------------------------------------------------------------------ - -#ifndef LED_H -#define LED_H - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -extern unsigned char LED_Configure(unsigned int led); - -extern unsigned char LED_Set(unsigned int led); - -extern unsigned char LED_Clear(unsigned int led); - -extern unsigned char LED_Toggle(unsigned int led); - -#endif //#ifndef LED_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/math.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/math.c deleted file mode 100644 index 39bed568c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/math.c +++ /dev/null @@ -1,91 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "math.h" -#include "trace.h" - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns the minimum value between two integers. -/// \param a First integer to compare. -/// \param b Second integer to compare. -//------------------------------------------------------------------------------ -unsigned int min(unsigned int a, unsigned int b) -{ - if (a < b) { - - return a; - } - else { - - return b; - } -} - -//------------------------------------------------------------------------------ -/// Returns the absolute value of an integer. -/// \param value Integer value. -//------------------------------------------------------------------------------ -// Do not call this function "abs", problem with gcc ! -unsigned int absv(signed int value) -{ - if (value < 0) { - - return -value; - } - else { - - return value; - } -} - -//------------------------------------------------------------------------------ -/// Computes and returns x power of y. -/// \param x Value. -/// \param y Power. -//------------------------------------------------------------------------------ -unsigned int power(unsigned int x, unsigned int y) -{ - unsigned int result = 1; - - while (y > 0) { - - result *= x; - y--; - } - return result; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/math.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/math.h deleted file mode 100644 index 6394f2992..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/math.h +++ /dev/null @@ -1,41 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef MATH_H -#define MATH_H - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned int min(unsigned int a, unsigned int b); -extern unsigned int absv(signed int value); -extern unsigned int power(unsigned int x, unsigned int y); -#endif //#ifndef MATH_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/rand.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/rand.c deleted file mode 100644 index 9a0f986de..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/rand.c +++ /dev/null @@ -1,60 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#include "rand.h" - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -static unsigned long int next = 1; - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Initialize the seed for rand generator. -/// \param seed rand initiation seed -//------------------------------------------------------------------------------ -void srand(unsigned int seed) -{ - next = seed; -} - -//------------------------------------------------------------------------------ -/// Return a random number, maxinum assumed to be 65536 -//------------------------------------------------------------------------------ - -int rand(void) -{ - next = next * 1103515245 + 12345; - return (unsigned int)(next/131072) % 65536; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/rand.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/rand.h deleted file mode 100644 index 8a8b21e2a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/rand.h +++ /dev/null @@ -1,49 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Small function for gererating random number. -/// -//------------------------------------------------------------------------------ - -#ifndef RAND_H -#define RAND_H - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -extern void srand(unsigned int seed); -extern int rand(void); - -#endif //#ifndef RAND_H diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/retarget.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/retarget.c deleted file mode 100644 index 1ca875ecd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/retarget.c +++ /dev/null @@ -1,88 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// This file Configures the target-dependent low level functions for character I/O. -/// -/// !Contents -/// The code implement the lower-level functions as follows: -/// - fputc -/// - ferror -/// - _ttywrch -/// - _sys_exit -/// -/// -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ -#include -#include - -// Disable semihosting -#pragma import(__use_no_semihosting_swi) - -struct __FILE { int handle;} ; -FILE __stdout; -FILE __stderr; - -//------------------------------------------------------------------------------ -/// Outputs a character to a file. -//------------------------------------------------------------------------------ -int fputc(int ch, FILE *f) { - if ((f == stdout) || (f == stderr)) { - DBGU_PutChar(ch); - return ch; - } - else { - return EOF; - } -} - -//------------------------------------------------------------------------------ -/// Returns the error status accumulated during file I/O. -//------------------------------------------------------------------------------ -int ferror(FILE *f) { - return EOF; -} - - -void _ttywrch(int ch) { - DBGU_PutChar((unsigned char)ch); -} - - -void _sys_exit(int return_code) { - label: goto label; /* endless loop */ -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/stdio.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/stdio.c deleted file mode 100644 index defbbc08d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/stdio.c +++ /dev/null @@ -1,511 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// Implementation of several stdio.h methods, such as printf(), sprintf() and -/// so on. This reduces the memory footprint of the binary when using those -/// methods, compared to the libc implementation. -/// -/// !Usage -/// -/// Adds stdio.c to the list of file to compile for the project. This will -/// automatically replace libc methods by the custom ones. -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include -#include - -//------------------------------------------------------------------------------ -// Local Definitions -//------------------------------------------------------------------------------ - -// Maximum string size allowed (in bytes). -#define MAX_STRING_SIZE 100 - -//------------------------------------------------------------------------------ -// Global Variables -//------------------------------------------------------------------------------ - -// Required for proper compilation. -struct _reent r = {0, (FILE *) 0, (FILE *) 1, (FILE *) 0}; -struct _reent *_impure_ptr = &r; - -//------------------------------------------------------------------------------ -// Local Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Writes a character inside the given string. Returns 1. -// \param pStr Storage string. -// \param c Character to write. -//------------------------------------------------------------------------------ -signed int PutChar(char *pStr, char c) -{ - *pStr = c; - return 1; -} - -//------------------------------------------------------------------------------ -// Writes a string inside the given string. -// Returns the size of the written -// string. -// \param pStr Storage string. -// \param pSource Source string. -//------------------------------------------------------------------------------ -signed int PutString(char *pStr, const char *pSource) -{ - signed int num = 0; - - while (*pSource != 0) { - - *pStr++ = *pSource++; - num++; - } - - return num; -} - -//------------------------------------------------------------------------------ -// Writes an unsigned int inside the given string, using the provided fill & -// width parameters. -// Returns the size in characters of the written integer. -// \param pStr Storage string. -// \param fill Fill character. -// \param width Minimum integer width. -// \param value Integer value. -//------------------------------------------------------------------------------ -signed int PutUnsignedInt( - char *pStr, - char fill, - signed int width, - unsigned int value) -{ - signed int num = 0; - - // Take current digit into account when calculating width - width--; - - // Recursively write upper digits - if ((value / 10) > 0) { - - num = PutUnsignedInt(pStr, fill, width, value / 10); - pStr += num; - } - // Write filler characters - else { - - while (width > 0) { - - PutChar(pStr, fill); - pStr++; - num++; - width--; - } - } - - // Write lower digit - num += PutChar(pStr, (value % 10) + '0'); - - return num; -} - -//------------------------------------------------------------------------------ -// Writes a signed int inside the given string, using the provided fill & width -// parameters. -// Returns the size of the written integer. -// \param pStr Storage string. -// \param fill Fill character. -// \param width Minimum integer width. -// \param value Signed integer value. -//------------------------------------------------------------------------------ -signed int PutSignedInt( - char *pStr, - char fill, - signed int width, - signed int value) -{ - signed int num = 0; - unsigned int absolute; - - // Compute absolute value - if (value < 0) { - - absolute = -value; - } - else { - - absolute = value; - } - - // Take current digit into account when calculating width - width--; - - // Recursively write upper digits - if ((absolute / 10) > 0) { - - if (value < 0) { - - num = PutSignedInt(pStr, fill, width, -(absolute / 10)); - } - else { - - num = PutSignedInt(pStr, fill, width, absolute / 10); - } - pStr += num; - } - else { - - // Reserve space for sign - if (value < 0) { - - width--; - } - - // Write filler characters - while (width > 0) { - - PutChar(pStr, fill); - pStr++; - num++; - width--; - } - - // Write sign - if (value < 0) { - - num += PutChar(pStr, '-'); - pStr++; - } - } - - // Write lower digit - num += PutChar(pStr, (absolute % 10) + '0'); - - return num; -} - -//------------------------------------------------------------------------------ -// Writes an hexadecimal value into a string, using the given fill, width & -// capital parameters. -// Returns the number of char written. -// \param pStr Storage string. -// \param fill Fill character. -// \param width Minimum integer width. -// \param maj Indicates if the letters must be printed in lower- or upper-case. -// \param value Hexadecimal value. -//------------------------------------------------------------------------------ -signed int PutHexa( - char *pStr, - char fill, - signed int width, - unsigned char maj, - unsigned int value) -{ - signed int num = 0; - - // Decrement width - width--; - - // Recursively output upper digits - if ((value >> 4) > 0) { - - num += PutHexa(pStr, fill, width, maj, value >> 4); - pStr += num; - } - // Write filler chars - else { - - while (width > 0) { - - PutChar(pStr, fill); - pStr++; - num++; - width--; - } - } - - // Write current digit - if ((value & 0xF) < 10) { - - PutChar(pStr, (value & 0xF) + '0'); - } - else if (maj) { - - PutChar(pStr, (value & 0xF) - 10 + 'A'); - } - else { - - PutChar(pStr, (value & 0xF) - 10 + 'a'); - } - num++; - - return num; -} - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Stores the result of a formatted string into another string. Format -/// arguments are given in a va_list instance. -/// Return the number of characters written. -/// \param pStr Destination string. -/// \param length Length of Destination string. -/// \param pFormat Format string. -/// \param ap Argument list. -//------------------------------------------------------------------------------ -signed int vsnprintf(char *pStr, size_t length, const char *pFormat, va_list ap) -{ - char fill; - unsigned char width; - signed int num = 0; - signed int size = 0; - - // Clear the string - if (pStr) { - - *pStr = 0; - } - - // Phase string - while (*pFormat != 0 && size < length) { - - // Normal character - if (*pFormat != '%') { - - *pStr++ = *pFormat++; - size++; - } - // Escaped '%' - else if (*(pFormat+1) == '%') { - - *pStr++ = '%'; - pFormat += 2; - size++; - } - // Token delimiter - else { - - fill = ' '; - width = 0; - pFormat++; - - // Parse filler - if (*pFormat == '0') { - - fill = '0'; - pFormat++; - } - - // Parse width - while ((*pFormat >= '0') && (*pFormat <= '9')) { - - width = (width*10) + *pFormat-'0'; - pFormat++; - } - - // Check if there is enough space - if (size + width > length) { - - width = length - size; - } - - // Parse type - switch (*pFormat) { - case 'd': - case 'i': num = PutSignedInt(pStr, fill, width, va_arg(ap, signed int)); break; - case 'u': num = PutUnsignedInt(pStr, fill, width, va_arg(ap, unsigned int)); break; - case 'x': num = PutHexa(pStr, fill, width, 0, va_arg(ap, unsigned int)); break; - case 'X': num = PutHexa(pStr, fill, width, 1, va_arg(ap, unsigned int)); break; - case 's': num = PutString(pStr, va_arg(ap, char *)); break; - case 'c': num = PutChar(pStr, va_arg(ap, unsigned int)); break; - default: - return EOF; - } - - pFormat++; - pStr += num; - size += num; - } - } - - // NULL-terminated (final \0 is not counted) - if (size < length) { - - *pStr = 0; - } - else { - - *(--pStr) = 0; - size--; - } - - return size; -} - -//------------------------------------------------------------------------------ -/// Stores the result of a formatted string into another string. Format -/// arguments are given in a va_list instance. -/// Return the number of characters written. -/// \param pString Destination string. -/// \param length Length of Destination string. -/// \param pFormat Format string. -/// \param ... Other arguments -//------------------------------------------------------------------------------ -signed int snprintf(char *pString, size_t length, const char *pFormat, ...) -{ - va_list ap; - signed int rc; - - va_start(ap, pFormat); - rc = vsnprintf(pString, length, pFormat, ap); - va_end(ap); - - return rc; -} - -//------------------------------------------------------------------------------ -/// Stores the result of a formatted string into another string. Format -/// arguments are given in a va_list instance. -/// Return the number of characters written. -/// \param pString Destination string. -/// \param pFormat Format string. -/// \param ap Argument list. -//------------------------------------------------------------------------------ -signed int vsprintf(char *pString, const char *pFormat, va_list ap) -{ - return vsnprintf(pString, MAX_STRING_SIZE, pFormat, ap); -} - -//------------------------------------------------------------------------------ -/// Outputs a formatted string on the given stream. Format arguments are given -/// in a va_list instance. -/// \param pStream Output stream. -/// \param pFormat Format string -/// \param ap Argument list. -//------------------------------------------------------------------------------ -signed int vfprintf(FILE *pStream, const char *pFormat, va_list ap) -{ - char pStr[MAX_STRING_SIZE]; - char pError[] = "stdio.c: increase MAX_STRING_SIZE\n\r"; - - // Write formatted string in buffer - if (vsprintf(pStr, pFormat, ap) >= MAX_STRING_SIZE) { - - fputs(pError, stderr); - while (1); // Increase MAX_STRING_SIZE - } - - // Display string - return fputs(pStr, pStream); -} - -//------------------------------------------------------------------------------ -/// Outputs a formatted string on the DBGU stream. Format arguments are given -/// in a va_list instance. -/// \param pFormat Format string -/// \param ap Argument list. -//------------------------------------------------------------------------------ -signed int vprintf(const char *pFormat, va_list ap) -{ - return vfprintf(stdout, pFormat, ap); -} - -//------------------------------------------------------------------------------ -/// Outputs a formatted string on the given stream, using a variable number of -/// arguments. -/// \param pStream Output stream. -/// \param pFormat Format string. -//------------------------------------------------------------------------------ -signed int fprintf(FILE *pStream, const char *pFormat, ...) -{ - va_list ap; - signed int result; - - // Forward call to vfprintf - va_start(ap, pFormat); - result = vfprintf(pStream, pFormat, ap); - va_end(ap); - - return result; -} - -//------------------------------------------------------------------------------ -/// Outputs a formatted string on the DBGU stream, using a variable number of -/// arguments. -/// \param pFormat Format string. -//------------------------------------------------------------------------------ -signed int printf(const char *pFormat, ...) -{ - va_list ap; - signed int result; - - // Forward call to vprintf - va_start(ap, pFormat); - result = vprintf(pFormat, ap); - va_end(ap); - - return result; -} - -//------------------------------------------------------------------------------ -/// Writes a formatted string inside another string. -/// \param pStr Storage string. -/// \param pFormat Format string. -//------------------------------------------------------------------------------ -signed int sprintf(char *pStr, const char *pFormat, ...) -{ - va_list ap; - signed int result; - - // Forward call to vsprintf - va_start(ap, pFormat); - result = vsprintf(pStr, pFormat, ap); - va_end(ap); - - return result; -} - -//------------------------------------------------------------------------------ -/// Outputs a string on stdout. -/// \param pStr String to output. -//------------------------------------------------------------------------------ -signed int puts(const char *pStr) -{ - return fputs(pStr, stdout); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/string.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/string.c deleted file mode 100644 index dbbb0e9ef..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/string.c +++ /dev/null @@ -1,239 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !Purpose -/// -/// Implementation of several methods defined in string.h, for reducing the -/// memory footprint when using them (since the whole libc.o file gets included -/// even when using a single method). -/// -/// !Usage -/// -/// Add string.c to the list of files to compile for the project. This will -/// automatically replace standard libc methods by the custom ones. -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Copies data from a source buffer into a destination buffer. The two buffers -/// must NOT overlap. Returns the destination buffer. -/// \param pDestination Destination buffer. -/// \param pSource Source buffer. -/// \param num Number of bytes to copy. -//------------------------------------------------------------------------------ -void * memcpy(void *pDestination, const void *pSource, size_t num) -{ - unsigned char *pByteDestination; - unsigned char *pByteSource; - unsigned int *pAlignedSource = (unsigned int *) pSource; - unsigned int *pAlignedDestination = (unsigned int *) pDestination; - - // If num is more than 4 bytes, and both dest. and source are aligned, - // then copy dwords - if ((((unsigned int) pAlignedDestination & 0x3) == 0) - && (((unsigned int) pAlignedSource & 0x3) == 0) - && (num >= 4)) { - - while (num >= 4) { - - *pAlignedDestination++ = *pAlignedSource++; - num -= 4; - } - } - - // Copy remaining bytes - pByteDestination = (unsigned char *) pAlignedDestination; - pByteSource = (unsigned char *) pAlignedSource; - while (num--) { - - *pByteDestination++ = *pByteSource++; - } - - return pDestination; -} - -//------------------------------------------------------------------------------ -/// Fills a memory region with the given value. Returns a pointer to the -/// memory region. -/// \param pBuffer Pointer to the start of the memory region to fill -/// \param value Value to fill the region with -/// \param num Size to fill in bytes -//------------------------------------------------------------------------------ -void * memset(void *pBuffer, int value, size_t num) -{ - unsigned char *pByteDestination; - unsigned int *pAlignedDestination = (unsigned int *) pBuffer; - unsigned int alignedValue = (value << 24) | (value << 16) | (value << 8) | value; - - // Set words if possible - if ((((unsigned int) pAlignedDestination & 0x3) == 0) && (num >= 4)) { - while (num >= 4) { - *pAlignedDestination++ = alignedValue; - num -= 4; - } - } - // Set remaining bytes - pByteDestination = (unsigned char *) pAlignedDestination; - while (num--) { - *pByteDestination++ = value; - } - return pBuffer; -} - -//----------------------------------------------------------------------------- -/// Search a character in the given string. -/// Returns a pointer to the character location. -/// \param pString Pointer to the start of the string to search. -/// \param character The character to find. -//----------------------------------------------------------------------------- -char * strchr(const char *pString, int character) -{ - char * p = (char *)pString; - char c = character & 0xFF; - - while(*p != c) { - if (*p == 0) { - return 0; - } - p++; - } - return p; -} - -//----------------------------------------------------------------------------- -/// Return the length of a given string -/// \param pString Pointer to the start of the string. -//----------------------------------------------------------------------------- -size_t strlen(const char *pString) -{ - unsigned int length = 0; - - while(*pString++ != 0) { - length++; - } - return length; -} - - -//----------------------------------------------------------------------------- -/// Search a character backword from the end of given string. -/// Returns a pointer to the character location. -/// \param pString Pointer to the start of the string to search. -/// \param character The character to find. -//----------------------------------------------------------------------------- -char * strrchr(const char *pString, int character) -{ - char *p = 0; - - while(*pString != 0) { - if (*pString++ == character) { - p = (char*)pString; - } - } - return p; -} - -//----------------------------------------------------------------------------- -/// Copy from source string to destination string -/// Return a pointer to the destination string -/// \param pDestination Pointer to the destination string. -/// \param pSource Pointer to the source string. -//----------------------------------------------------------------------------- -char * strcpy(char *pDestination, const char *pSource) -{ - char *pSaveDest = pDestination; - - for(; (*pDestination = *pSource) != 0; ++pSource, ++pDestination); - return pSaveDest; -} - -//----------------------------------------------------------------------------- -/// Compare the first specified bytes of 2 given strings -/// Return 0 if equals -/// Return >0 if 1st string > 2nd string -/// Return <0 if 1st string < 2nd string -/// \param pString1 Pointer to the start of the 1st string. -/// \param pString2 Pointer to the start of the 2nd string. -/// \param count Number of bytes that should be compared. -//----------------------------------------------------------------------------- -int strncmp(const char *pString1, const char *pString2, size_t count) -{ - int r; - - while(count) { - r = *pString1 - *pString2; - if (r == 0) { - if (*pString1 == 0) { - break; - } - pString1++; - pString2++; - count--; - continue; - } - return r; - } - return 0; -} - -//----------------------------------------------------------------------------- -/// Copy the first number of bytes from source string to destination string -/// Return the pointer to the destination string. -/// \param pDestination Pointer to the start of destination string. -/// \param pSource Pointer to the start of the source string. -/// \param count Number of bytes that should be copied. -//----------------------------------------------------------------------------- -char * strncpy(char *pDestination, const char *pSource, size_t count) -{ - char *pSaveDest = pDestination; - - while (count) { - *pDestination = *pSource; - if (*pSource == 0) { - break; - } - pDestination++; - pSource++; - count--; - } - return pSaveDest; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/trace.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/trace.c deleted file mode 100644 index 4073bb9bb..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/trace.c +++ /dev/null @@ -1,45 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "trace.h" - -//------------------------------------------------------------------------------ -// Internal variables -//------------------------------------------------------------------------------ - -/// Trace level can be set at applet initialization -#if !defined(NOTRACE) && (DYN_TRACES == 1) - unsigned int traceLevel = TRACE_LEVEL; -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/trace.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/trace.h deleted file mode 100644 index 63e7617a3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/trace.h +++ /dev/null @@ -1,241 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \file -/// -/// \par Purpose -/// -/// Standard output methods for reporting debug information, warnings and -/// errors, which can be easily be turned on/off. -/// -/// \par Usage -/// -# Initialize the DBGU using TRACE_CONFIGURE() if you intend to eventually -/// disable ALL traces; otherwise use DBGU_Configure(). -/// -# Uses the TRACE_DEBUG(), TRACE_INFO(), TRACE_WARNING(), TRACE_ERROR() -/// TRACE_FATAL() macros to output traces throughout the program. -/// -# Each type of trace has a level : Debug 5, Info 4, Warning 3, Error 2 -/// and Fatal 1. Disable a group of traces by changing the value of -/// TRACE_LEVEL during compilation; traces with a level bigger than TRACE_LEVEL -/// are not generated. To generate no trace, use the reserved value 0. -/// -# Trace disabling can be static or dynamic. If dynamic disabling is selected -/// the trace level can be modified in runtime. If static disabling is selected -/// the disabled traces are not compiled. -/// -/// \par traceLevels Trace level description -/// -# TRACE_DEBUG (5): Traces whose only purpose is for debugging the program, -/// and which do not produce meaningful information otherwise. -/// -# TRACE_INFO (4): Informational trace about the program execution. Should -/// enable the user to see the execution flow. -/// -# TRACE_WARNING (3): Indicates that a minor error has happened. In most case -/// it can be discarded safely; it may even be expected. -/// -# TRACE_ERROR (2): Indicates an error which may not stop the program execution, -/// but which indicates there is a problem with the code. -/// -# TRACE_FATAL (1): Indicates a major error which prevents the program from going -/// any further. - -//------------------------------------------------------------------------------ - -#ifndef TRACE_H -#define TRACE_H - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include -#include -#include - -//------------------------------------------------------------------------------ -// Global Definitions -//------------------------------------------------------------------------------ - -/// Softpack Version -#define SOFTPACK_VERSION "1.0beta1" - -#define TRACE_LEVEL_DEBUG 5 -#define TRACE_LEVEL_INFO 4 -#define TRACE_LEVEL_WARNING 3 -#define TRACE_LEVEL_ERROR 2 -#define TRACE_LEVEL_FATAL 1 -#define TRACE_LEVEL_NO_TRACE 0 - -// By default, all traces are output except the debug one. -#if !defined(TRACE_LEVEL) -#define TRACE_LEVEL TRACE_LEVEL_INFO -#endif - -// By default, trace level is static (not dynamic) -#if !defined(DYN_TRACES) -#define DYN_TRACES 0 -#endif - -#if defined(NOTRACE) -#error "Error: NOTRACE has to be not defined !" -#endif - -#undef NOTRACE -#if (DYN_TRACES==0) - #if (TRACE_LEVEL == TRACE_LEVEL_NO_TRACE) - #define NOTRACE - #endif -#endif - - - -//------------------------------------------------------------------------------ -// Global Macros -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Initializes the DBGU -/// \param mode DBGU mode. -/// \param baudrate DBGU baudrate. -/// \param mck Master clock frequency. -//------------------------------------------------------------------------------ -#define TRACE_CONFIGURE(mode, baudrate, mck) { \ - const Pin pinsDbgu[] = {PINS_DBGU}; \ - PIO_Configure(pinsDbgu, PIO_LISTSIZE(pinsDbgu)); \ - DBGU_Configure(mode, baudrate, mck); \ - } - -//------------------------------------------------------------------------------ -/// Initializes the DBGU for ISP project -/// \param mode DBGU mode. -/// \param baudrate DBGU baudrate. -/// \param mck Master clock frequency. -//------------------------------------------------------------------------------ -#ifndef DYNTRACE -#define DYNTRACE 0 -#endif - -#if (TRACE_LEVEL==0) && (DYNTRACE==0) -#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) {} -#else -#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) { \ - const Pin pinsDbgu[] = {PINS_DBGU}; \ - PIO_Configure(pinsDbgu, PIO_LISTSIZE(pinsDbgu)); \ - DBGU_Configure(mode, baudrate, mck); \ - } -#endif - -//------------------------------------------------------------------------------ -/// Outputs a formatted string using if the log level is high -/// enough. Can be disabled by defining TRACE_LEVEL=0 during compilation. -/// \param format Formatted string to output. -/// \param ... Additional parameters depending on formatted string. -//------------------------------------------------------------------------------ -#if defined(NOTRACE) - -// Empty macro -#define TRACE_DEBUG(...) { } -#define TRACE_INFO(...) { } -#define TRACE_WARNING(...) { } -#define TRACE_ERROR(...) { } -#define TRACE_FATAL(...) { while(1); } - -#define TRACE_DEBUG_WP(...) { } -#define TRACE_INFO_WP(...) { } -#define TRACE_WARNING_WP(...) { } -#define TRACE_ERROR_WP(...) { } -#define TRACE_FATAL_WP(...) { while(1); } - -#elif (DYN_TRACES == 1) - -// Trace output depends on traceLevel value -#define TRACE_DEBUG(...) { if (traceLevel >= TRACE_LEVEL_DEBUG) { printf("-D- " __VA_ARGS__); } } -#define TRACE_INFO(...) { if (traceLevel >= TRACE_LEVEL_INFO) { printf("-I- " __VA_ARGS__); } } -#define TRACE_WARNING(...) { if (traceLevel >= TRACE_LEVEL_WARNING) { printf("-W- " __VA_ARGS__); } } -#define TRACE_ERROR(...) { if (traceLevel >= TRACE_LEVEL_ERROR) { printf("-E- " __VA_ARGS__); } } -#define TRACE_FATAL(...) { if (traceLevel >= TRACE_LEVEL_FATAL) { printf("-F- " __VA_ARGS__); while(1); } } - -#define TRACE_DEBUG_WP(...) { if (traceLevel >= TRACE_LEVEL_DEBUG) { printf(__VA_ARGS__); } } -#define TRACE_INFO_WP(...) { if (traceLevel >= TRACE_LEVEL_INFO) { printf(__VA_ARGS__); } } -#define TRACE_WARNING_WP(...) { if (traceLevel >= TRACE_LEVEL_WARNING) { printf(__VA_ARGS__); } } -#define TRACE_ERROR_WP(...) { if (traceLevel >= TRACE_LEVEL_ERROR) { printf(__VA_ARGS__); } } -#define TRACE_FATAL_WP(...) { if (traceLevel >= TRACE_LEVEL_FATAL) { printf(__VA_ARGS__); while(1); } } - -#else - -// Trace compilation depends on TRACE_LEVEL value -#if (TRACE_LEVEL >= TRACE_LEVEL_DEBUG) -#define TRACE_DEBUG(...) { printf("-D- " __VA_ARGS__); } -#define TRACE_DEBUG_WP(...) { printf(__VA_ARGS__); } -#else -#define TRACE_DEBUG(...) { } -#define TRACE_DEBUG_WP(...) { } -#endif - -#if (TRACE_LEVEL >= TRACE_LEVEL_INFO) -#define TRACE_INFO(...) { printf("-I- " __VA_ARGS__); } -#define TRACE_INFO_WP(...) { printf(__VA_ARGS__); } -#else -#define TRACE_INFO(...) { } -#define TRACE_INFO_WP(...) { } -#endif - -#if (TRACE_LEVEL >= TRACE_LEVEL_WARNING) -#define TRACE_WARNING(...) { printf("-W- " __VA_ARGS__); } -#define TRACE_WARNING_WP(...) { printf(__VA_ARGS__); } -#else -#define TRACE_WARNING(...) { } -#define TRACE_WARNING_WP(...) { } -#endif - -#if (TRACE_LEVEL >= TRACE_LEVEL_ERROR) -#define TRACE_ERROR(...) { printf("-E- " __VA_ARGS__); } -#define TRACE_ERROR_WP(...) { printf(__VA_ARGS__); } -#else -#define TRACE_ERROR(...) { } -#define TRACE_ERROR_WP(...) { } -#endif - -#if (TRACE_LEVEL >= TRACE_LEVEL_FATAL) -#define TRACE_FATAL(...) { printf("-F- " __VA_ARGS__); while(1); } -#define TRACE_FATAL_WP(...) { printf(__VA_ARGS__); while(1); } -#else -#define TRACE_FATAL(...) { while(1); } -#define TRACE_FATAL_WP(...) { while(1); } -#endif - -#endif - - -//------------------------------------------------------------------------------ -// Exported variables -//------------------------------------------------------------------------------ -// Depending on DYN_TRACES, traceLevel is a modifable runtime variable -// or a define -#if !defined(NOTRACE) && (DYN_TRACES == 1) - extern unsigned int traceLevel; -#endif - -#endif //#ifndef TRACE_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/util.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/util.c deleted file mode 100644 index b2bd0dea1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/util.c +++ /dev/null @@ -1,223 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ -#include -#include -#include - -//------------------------------------------------------------------------------ -// Local Variables -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Print char if printable. If not print a point -/// \param c char to -//------------------------------------------------------------------------------ -static void PrintChar(unsigned char c) -{ - if( (/*c >= 0x00 &&*/ c <= 0x1F) || - (c >= 0xB0 && c <= 0xDF) ) { - - printf("."); - } - else { - - printf("%c", c); - } -} - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Displays the content of the given frame on the DBGU. -/// \param pBuffer Pointer to the frame to dump. -/// \param size Buffer size in bytes. -//------------------------------------------------------------------------------ -void UTIL_DbguDumpFrame(unsigned char *pFrame, unsigned int size) -{ - unsigned int i; - - for (i=0; i < size; i++) { - printf("%02X ", pFrame[i]); - } - - printf("\n\r"); -} - -//------------------------------------------------------------------------------ -/// Displays the content of the given buffer on the DBGU. -/// \param pBuffer Pointer to the buffer to dump. -/// \param size Buffer size in bytes. -/// \param address Start address to display -//------------------------------------------------------------------------------ -void UTIL_DbguDumpMemory( - unsigned char *pBuffer, - unsigned int size, - unsigned int address - ) -{ - unsigned int i, j; - unsigned int lastLineStart; - unsigned char* pTmp; - - for (i=0; i < (size / 16); i++) { - - printf("0x%08X: ", address + (i*16)); - pTmp = (unsigned char*)&pBuffer[i*16]; - for (j=0; j < 4; j++) { - printf("%02X%02X%02X%02X ", pTmp[0],pTmp[1],pTmp[2],pTmp[3]); - pTmp += 4; - } - - pTmp = (unsigned char*)&pBuffer[i*16]; - for (j=0; j < 16; j++) { - PrintChar(*pTmp++); - } - - printf("\n\r"); - } - - if( (size%16) != 0) { - lastLineStart = size - (size%16); - printf("0x%08X: ", address + lastLineStart); - - for (j= lastLineStart; j < lastLineStart+16; j++) { - - if( (j!=lastLineStart) && (j%4 == 0) ) { - printf(" "); - } - if(j= '0' && key <= '9' ) { - value = (value * 10) + (key - '0'); - nbNb++; - } - else if(key == 0x0D || key == ' ') { - if(nbNb == 0) { - printf("\n\rWrite a number and press ENTER or SPACE!\n\r"); - return 0; - } else { - printf("\n\r"); - *pValue = value; - return 1; - } - } else { - printf("\n\r'%c' not a number!\n\r", key); - return 0; - } - } -} - -//------------------------------------------------------------------------------ -/// Reads an integer and check the value -//------------------------------------------------------------------------------ -unsigned char UTIL_DbguGetIntegerMinMax( - unsigned int *pValue, - unsigned int min, - unsigned int max - ) -{ - unsigned int value = 0; - - if( UTIL_DbguGetInteger(&value) == 0) { - return 0; - } - - if(value < min || value > max) { - printf("\n\rThe number have to be between %d and %d\n\r", min, max); - return 0; - } - - printf("\n\r"); - *pValue = value; - return 1; -} - -//------------------------------------------------------------------------------ -/// Reads an hexadecimal number -//------------------------------------------------------------------------------ -unsigned char UTIL_DbguGetHexa32(unsigned int *pValue) -{ - unsigned char key; - unsigned int i = 0; - unsigned int value = 0; - for(i = 0; i < 8; i++) { - key = DBGU_GetChar(); - DBGU_PutChar(key); - if(key >= '0' && key <= '9' ) { - value = (value * 16) + (key - '0'); - } - else if(key >= 'A' && key <= 'F' ) { - value = (value * 16) + (key - 'A' + 10) ; - } - else if(key >= 'a' && key <= 'f' ) { - value = (value * 16) + (key - 'a' + 10) ; - } - else { - printf("\n\rIt is not a hexa character!\n\r"); - return 0; - } - } - - printf("\n\r"); - *pValue = value; - return 1; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/util.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/util.h deleted file mode 100644 index f79ffd3f7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/util.h +++ /dev/null @@ -1,48 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef UTIL_H -#define UTIL_H - -//------------------------------------------------------------------------------ -// Global Functions -//------------------------------------------------------------------------------ - -extern void UTIL_DbguDumpFrame(unsigned char *pFrame, unsigned int size); - -extern void UTIL_DbguDumpMemory(unsigned char *pBuffer, unsigned int size, unsigned int address); - -extern unsigned char UTIL_DbguGetInteger(unsigned int *pValue); - -extern unsigned char UTIL_DbguGetIntegerMinMax(unsigned int *pValue, unsigned int min, unsigned int max); - -extern unsigned char UTIL_DbguGetHexa32(unsigned int *pValue); - -#endif //#ifndef UTIL_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/utility.dir b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/utility.dir deleted file mode 100644 index 344ef5a67..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/utility.dir +++ /dev/null @@ -1,50 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \dir -/// -/// !!!Purpose -/// -/// The utility directory contains several very small APIs for performing -/// specific tasks, such as LED configuration, BMP header decoding, etc. -/// -/// !!!Contents -/// -/// Most modules contained here are very small and do not fit in any of the -/// other at91lib categories. They primarily provide helper functions -/// (e.g. for handling BMP and WAV files) and re-implementation of libc code for -/// reducing code size (math, stdio, string). -/// -/// Two important files are assert.h and trace.h. The first one provides macros -/// for run-time verifications of parameters & values. Trace.h enables the -/// programmer to add debug traces to APIs that can be easily turned on or off -/// depending on the debugging needs. -//------------------------------------------------------------------------------ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/video.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/video.c deleted file mode 100644 index 49ec1da24..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/video.c +++ /dev/null @@ -1,130 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ -#include "video.h" - -//----------------------------------------------------------------------------- -/// Conversion YCrCb to RGB:
-/// R = 1.164(Yi 16) + 1.596(Cr 128)
-/// G = 1.164(Yi 16) 0.813(Cr 128) 0.391(Cb 128)
-/// B = 1.164(Yi 16) + 2.018(Cb 128)
-/// -/// Pixel i+1:
-/// YCrCb to RGB:
-/// R = 1.164(Yi+1 16) + 1.596(Cr 128)
-/// G = 1.164(Yi+1 16) 0.813(Cr 128) 0.391(Cb 128)
-/// B = 1.164(Yi+1 16) + 2.018(Cb 128) -/// \param ycc Source buffer (YCC) -/// \param rgb Destination buffer (RGB) -/// \param len Length of buffer -//----------------------------------------------------------------------------- -void VIDEO_Ycc2Rgb(unsigned char *ycc, unsigned short *rgb, unsigned int len) -{ - int r_calc_i; - int g_calc_i; - int b_calc_i; - int r_calc_i_incr; - int g_calc_i_incr; - int b_calc_i_incr; - int cr_i; - int y_i; - int cb_i; - int y_i_incr; - int val; - int val1; - int val2; - int val3; - int val4; - int val5; - int i; - - for(i=0; i 255) - r_calc_i = 255; - - if (g_calc_i < 0) - g_calc_i = 0; - else if (g_calc_i > 255) - g_calc_i = 255; - - if (b_calc_i < 0) - b_calc_i = 0; - else if (b_calc_i > 255) - b_calc_i = 255; - - if (r_calc_i_incr < 0) - r_calc_i_incr = 0; - else if (r_calc_i_incr > 255) - r_calc_i_incr = 255; - - if (g_calc_i_incr < 0) - g_calc_i_incr = 0; - else if (g_calc_i_incr > 255) - g_calc_i_incr = 255; - - if (b_calc_i_incr < 0) - b_calc_i_incr = 0; - else if (b_calc_i_incr > 255) - b_calc_i_incr = 255; - - *rgb++ = (((unsigned short )r_calc_i & 0xF8) >> 3) - | ((((unsigned short)g_calc_i & 0xF8) >> 3) << 5) - | ((((unsigned short)b_calc_i & 0xF8) >> 3) << 10); - - *rgb++ = (((unsigned short )r_calc_i_incr & 0xF8) >> 3) - | ((((unsigned short)g_calc_i_incr & 0xF8) >> 3) << 5) - | ((((unsigned short)b_calc_i_incr & 0xF8) >> 3) << 10); - } -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/video.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/video.h deleted file mode 100644 index c4940e51c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/video.h +++ /dev/null @@ -1,89 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -/// \unit -/// -/// !!!Purpose -/// -/// Video structure, used for LCD and ISI. -/// Conversion Video from YCC to RGB -/// -//------------------------------------------------------------------------------ - -#ifndef _VIDEO_H -#define _VIDEO_H - -//----------------------------------------------------------------------------- -// Definitions -//----------------------------------------------------------------------------- -/// Type of video is YUV -#define YUV 0 -/// Type of video is RGB -#define RGB 1 - -//----------------------------------------------------------------------------- -/// Video structure -//----------------------------------------------------------------------------- -typedef struct _AT91S_VIDEO -{ - /// LCD Vertical Size - unsigned int lcd_vsize; - /// LCD Horizontal Size - unsigned int lcd_hsize; - /// LCD Number of Bit Per Pixel - unsigned int lcd_nbpp; - /// LCD Frame Buffer Address - unsigned int lcd_fb_addr; - /// Base address for the frame buffer descriptors list - unsigned int Isi_fbd_base; - /// Start of Line Delay - unsigned int Hblank; - /// Start of frame Delay - unsigned int Vblank; - /// Vertical size of the Image sensor [0..2047] - unsigned int codec_vsize; - /// Horizontal size of the Image sensor [0..2047] - unsigned int codec_hsize; - /// Base address for codec DMA - unsigned int codec_fb_addr; - /// Buffer index - unsigned int IsiPrevBuffIndex; - /// Type of video - unsigned char rgb_or_yuv; -}AT91S_VIDEO, *AT91PS_VIDEO; - - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ -extern void VIDEO_Ycc2Rgb(unsigned char *ycc, unsigned short *rgb, unsigned int len); - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/wav.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/wav.c deleted file mode 100644 index cd75b1515..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/wav.c +++ /dev/null @@ -1,84 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -//------------------------------------------------------------------------------ -// Headers -//------------------------------------------------------------------------------ - -#include "wav.h" -#include - -//------------------------------------------------------------------------------ -// Internal constants -//------------------------------------------------------------------------------ - -/// WAV letters "RIFF" -#define WAV_CHUNKID 0x46464952 -/// WAV letters "WAVE" -#define WAV_FORMAT 0x45564157 -/// WAV letters "fmt " -#define WAV_SUBCHUNKID 0x20746D66 - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Returns 1 if the header of a Wav file is valid; otherwise returns 0. -/// \param file Buffer holding the file to examinate. -//------------------------------------------------------------------------------ -unsigned char WAV_IsValid(const WavHeader *header) -{ - return ((header->chunkID == WAV_CHUNKID) - && (header->format == WAV_FORMAT) - && (header->subchunk1Size == 0x10)); -} - -//------------------------------------------------------------------------------ -/// Display the information of the WAV file (sample rate, stereo/mono and frame -/// size). -//------------------------------------------------------------------------------ -void WAV_DisplayInfo(const WavHeader *header) -{ - printf( "Wave file header information\n\r"); - printf( "--------------------------------\n\r"); - printf( " - Chunk ID = 0x%08X\n\r", header->chunkID); - printf( " - Chunk Size = %d\n\r", header->chunkSize); - printf( " - Format = 0x%08X\n\r", header->format); - printf( " - SubChunk ID = 0x%08X\n\r", header->subchunk1ID); - printf( " - Subchunk1 Size = %d\n\r", header->subchunk1Size); - printf( " - Audio Format = 0x%04X\n\r", header->audioFormat); - printf( " - Num. Channels = %d\n\r", header->numChannels); - printf( " - Sample Rate = %d\n\r", header->sampleRate); - printf( " - Byte Rate = %d\n\r", header->byteRate); - printf( " - Block Align = %d\n\r", header->blockAlign); - printf( " - Bits Per Sample = %d\n\r", header->bitsPerSample); - printf( " - Subchunk2 ID = 0x%08X\n\r", header->subchunk2ID); - printf( " - Subchunk2 Size = %d\n\r", header->subchunk2Size); -} \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/wav.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/wav.h deleted file mode 100644 index 4d26e84cc..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/utility/wav.h +++ /dev/null @@ -1,82 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2008, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -#ifndef WAV_H -#define WAV_H - -//------------------------------------------------------------------------------ -// Exported types -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -/// Standard WAV file header information. -//------------------------------------------------------------------------------ -typedef struct _WavHeader -{ - /// Contains the letters "RIFF" in ASCII form. - unsigned int chunkID; - /// Size of the rest of the chunk following this number. - unsigned int chunkSize; - /// Contains the letters "WAVE". - unsigned int format; - /// Contains the letters "fmt ". - unsigned int subchunk1ID; - /// 16 for PCM. This is the size of the rest of the Subchunk - /// which follows this number. - unsigned int subchunk1Size; - /// PCM = 1 (i.e. Linear quantization). Values other than 1 indicate some - /// form of compression. - unsigned short audioFormat; - /// Mono = 1, Stereo = 2, etc. - unsigned short numChannels; - /// 8000, 44100, etc. - unsigned int sampleRate; - /// SampleRate * NumChannels * BitsPerSample/8 - unsigned int byteRate; - /// NumChannels * BitsPerSample/8 - unsigned short blockAlign; - /// 8 bits = 8, 16 bits = 16, etc. - unsigned short bitsPerSample; - /// Contains the letters "data". - unsigned int subchunk2ID; - /// Number of bytes in the data. - unsigned int subchunk2Size; - -} WavHeader; - -//------------------------------------------------------------------------------ -// Exported functions -//------------------------------------------------------------------------------ - -extern unsigned char WAV_IsValid(const WavHeader *header); - -extern void WAV_DisplayInfo(const WavHeader *header); - -#endif //#ifndef WAV_H - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/wdt/wdt.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/wdt/wdt.c deleted file mode 100644 index 6d4f4a3d3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/wdt/wdt.c +++ /dev/null @@ -1,141 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * Implementation of Watchdog Timer (WDT) controller. - * - */ - -/** \addtogroup wdt_module Working with WDT - * The WDT driver provides the interface to configure and use the WDT - * peripheral. - * - * The WDT can be used to prevent system lock-up if the software becomes - * trapped in a deadlock. It can generate a general reset or a processor - * reset only. It is clocked by slow clock divided by 128. - * - * The WDT is running at reset with 16 seconds watchdog period (slow clock at 32.768 kHz) - * and external reset generation enabled. The user must either disable it or - * reprogram it to meet the application requires. - * - * To use the WDT, the user could follow these few steps: - *
    - *
  • Enable watchdog with given mode using \ref WDT_Enable(). - *
  • Restart the watchdog using \ref WDT_Restart() within the watchdog period. - *
- * - * For more accurate information, please look at the WDT section of the - * Datasheet. - * - * \note - * The Watchdog Mode Register (WDT_MR) can be written only once.\n - * - * Related files :\n - * \ref wdt.c\n - * \ref wdt.h.\n - */ -/*@{*/ -/*@}*/ - -/*--------------------------------------------------------------------------- - * Headers - *---------------------------------------------------------------------------*/ - -/* These headers were introduced in C99 by working group ISO/IEC JTC1/SC22/WG14. */ -#include - -#include -#include "wdt.h" - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -/** - * \brief Enable watchdog with given mode. - * - * \note The Watchdog Mode Register (WDT_MR) can be written only once. - * Only a processor reset resets it. - * - * \param mode WDT mode to be set - */ -void WDT_Enable(uint32_t mode) -{ - Wdt *pWDT = WDT; - - pWDT->WDT_MR = mode; -} - -/** - * \brief Disable watchdog. - * - * \note The Watchdog Mode Register (WDT_MR) can be written only once. - * Only a processor reset resets it. - */ -void WDT_Disable(void) -{ - Wdt *pWDT = WDT; - - pWDT->WDT_MR = WDT_MR_WDDIS; -} - -/** - * \brief Watchdog restart. - */ -void WDT_Restart(void) -{ - Wdt *pWDT = WDT; - - pWDT->WDT_CR = 0xA5000001; -} - -/** - * \brief Watchdog get status. - */ -uint32_t WDT_GetStatus(void) -{ - Wdt *pWDT = WDT; - - return(pWDT->WDT_SR & 0x3); -} - -/** - * \brief Watchdog get period. - * - * \param ms desired watchdog period in millisecond. - */ -uint32_t WDT_GetPeriod(uint32_t ms) -{ - if ((ms < 4) || (ms > 16000)) { - return 0; - } - return((ms << 8) / 1000); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/wdt/wdt.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/wdt/wdt.h deleted file mode 100644 index ed30bb511..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/libraries/drivers/wdt/wdt.h +++ /dev/null @@ -1,61 +0,0 @@ -/* ---------------------------------------------------------------------------- - * ATMEL Microcontroller Software Support - * ---------------------------------------------------------------------------- - * Copyright (c) 2009, Atmel Corporation - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * - Redistributions of source code must retain the above copyright notice, - * this list of conditions and the disclaimer below. - * - * Atmel's name may not be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ---------------------------------------------------------------------------- - */ - -/** - * \file - * - * \par Purpose - * Interface for Watchdog Timer (WDT) controller. - * - * \par Usage - * -# Enable watchdog with given mode using \ref WDT_Enable(). - * -# Disable watchdog using \ref WDT_Disable() - * -# Restart the watchdog using \ref WDT_Restart(). - * -# Get watchdog status using \ref WDT_GetStatus(). - * -# Caculate watchdog period value using \ref WDT_GetPeriod(). - */ - -#ifndef WDT_H -#define WDT_H - -/*---------------------------------------------------------------------------- - * Exported functions - *----------------------------------------------------------------------------*/ - -extern void WDT_Enable(uint32_t mode); - -extern void WDT_Disable(void); - -extern void WDT_Restart(void); - -extern uint32_t WDT_GetStatus(void); - -extern uint32_t WDT_GetPeriod(uint32_t ms); - -#endif /* #ifndef WDT_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/port/port.h deleted file mode 100644 index fe87134a4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/port/port.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * FreeModbus Libary: Atmel AT91SAM3S Demo Application - * Copyright (C) 2010 Christian Walter - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * IF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -/* ----------------------- Platform includes --------------------------------*/ -#include -#include -#include -#include -#include -#include -#include - -/* ----------------------- Defines ------------------------------------------*/ -#define INLINE inline -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#define ENTER_CRITICAL_SECTION( ) vMBPortEnterCritical() -#define EXIT_CRITICAL_SECTION( ) vMBPortExitCritical() - -#define assert( x ) - -typedef char BOOL; - -typedef unsigned char UCHAR; -typedef char CHAR; - -typedef unsigned short USHORT; -typedef short SHORT; - -typedef unsigned long ULONG; -typedef long LONG; - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#define MB_PORT_HAS_CLOSE 1 -#define MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS 2 - -/* ----------------------- Prototypes ---------------------------------------*/ -void vMBPortSetWithinException( BOOL bInException ); -BOOL bMBPortIsWithinException( void ); - -void vMBPortEnterCritical( void ); -void vMBPortExitCritical( void ); - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/port/portevent.c deleted file mode 100644 index 35583bfb6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/port/portevent.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * FreeModbus Libary: Atmel AT91SAM3S Demo Application - * Copyright (C) 2010 Christian Walter - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * IF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include -#include -#include - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static xQueueHandle xQueueHdl; - - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - BOOL bStatus = FALSE; - if( 0 != ( xQueueHdl = xQueueCreate( 1, sizeof( eMBEventType ) ) ) ) - { - bStatus = TRUE; - } - return bStatus; -} - -void -vMBPortEventClose( void ) -{ - if( 0 != xQueueHdl ) - { - vQueueDelete( xQueueHdl ); - xQueueHdl = 0; - } -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - BOOL bStatus = TRUE; - if( bMBPortIsWithinException( ) ) - { - ( void )xQueueSendFromISR( xQueueHdl, ( const void * )&eEvent, pdFALSE ); - } - else - { - ( void )xQueueSend( xQueueHdl, ( const void * )&eEvent, pdFALSE ); - } - - return bStatus; -} - -BOOL -xMBPortEventGet( eMBEventType * peEvent ) -{ - BOOL xEventHappened = FALSE; - - if( pdTRUE == xQueueReceive( xQueueHdl, peEvent, portTICK_RATE_MS * 50 ) ) - { - xEventHappened = TRUE; - } - return xEventHappened; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/port/portother.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/port/portother.c deleted file mode 100644 index 507931954..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/port/portother.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * FreeModbus Libary: Atmel AT91SAM3S Demo Application - * Copyright (C) 2010 Christian Walter - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * IF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include -#include -#include -#include - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include - -/* ----------------------- Variables ----------------------------------------*/ -static BOOL bIsWithinException = FALSE; - -/* ----------------------- Start implementation -----------------------------*/ - -void -vMBPortSetWithinException( BOOL bInException ) -{ - bIsWithinException = bInException; -} - -BOOL -bMBPortIsWithinException( void ) -{ - return bIsWithinException; -} - -void -vMBPortEnterCritical( void ) -{ - taskENTER_CRITICAL( ); -} - -void -vMBPortExitCritical( void ) -{ - taskEXIT_CRITICAL( ); -} - -void -vMBPortClose( void ) -{ - extern void vMBPortSerialClose( void ); - extern void vMBPortTimerClose( void ); - extern void vMBPortEventClose( void ); - vMBPortSerialClose( ); - vMBPortTimerClose( ); - vMBPortEventClose( ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/port/portserial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/port/portserial.c deleted file mode 100644 index 8c22e74f5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/port/portserial.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * FreeModbus Libary: Atmel AT91SAM3S Demo Application - * Copyright (C) 2010 Christian Walter - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * IF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include -#include -#include -#include - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "port.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define USART0_ENABLED ( 1 ) -#define USART0_IDX ( 0 ) - -#define USART1_ENABLED ( 1 ) -#define USART1_IDX ( USART0_IDX + USART0_ENABLED * 1 ) - -#define USART_IDX_LAST ( USART1_IDX ) - -#define USART_INVALID_PORT ( 0xFF ) -#define USART_NOT_RE_IDX ( 3 ) -#define USART_DE_IDX ( 4 ) - -/* ----------------------- Static variables ---------------------------------*/ - -#if USART1_ENABLED == 1 -const Pin xUSART0Pins[] = { - PIN_USART0_TXD, - PIN_USART0_RXD -}; -#endif - -#if USART1_ENABLED == 1 -const Pin xUSART1NotREPin = { 1 << 25, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT }; -const Pin xUSART1DEPin = { 1 << 24, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT }; - -const Pin xUSART1Pins[] = { - PIN_USART1_TXD, - PIN_USART1_RXD, - {1 << 23, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} -}; -#endif - -const struct xUSARTHWMappings_t -{ - Usart *pUsart; - unsigned int xUSARTID; - IRQn_Type xUSARTIrq; - const Pin *USARTNotREPin; - const Pin *USARTDEPin; - const Pin *xUSARTPins; - uint32_t xUSARTPinsCnt; - - -} xUSARTHWMappings[] = -{ -#if USART0_ENABLED == 1 - { - USART0, ID_USART0, USART0_IRQn, NULL, NULL, &xUSART0Pins[0], PIO_LISTSIZE( xUSART0Pins )}, -#endif -#if USART1_ENABLED == 1 - { - USART1, ID_USART1, USART1_IRQn, &xUSART1NotREPin, &xUSART1DEPin, &xUSART1Pins[0], PIO_LISTSIZE( xUSART1Pins )}, -#endif -}; - -static UCHAR ucUsedPort = USART_INVALID_PORT; - -void -vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable ) -{ - - if( xRxEnable ) - { - USART_SetReceiverEnabled( xUSARTHWMappings[ucUsedPort].pUsart, 1 ); - USART_EnableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IDR_RXRDY ); - } - else - { - USART_DisableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IDR_RXRDY ); - USART_SetReceiverEnabled( xUSARTHWMappings[ucUsedPort].pUsart, 0 ); - } - - if( xTxEnable ) - { - if( NULL != xUSARTHWMappings[ucUsedPort].USARTNotREPin ) - { - PIO_Set( xUSARTHWMappings[ucUsedPort].USARTNotREPin ); - } - if( NULL != xUSARTHWMappings[ucUsedPort].USARTDEPin ) - { - PIO_Set( xUSARTHWMappings[ucUsedPort].USARTDEPin ); - } - USART_SetTransmitterEnabled( xUSARTHWMappings[ucUsedPort].pUsart, 1 ); - USART_EnableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IER_TXRDY ); - USART_DisableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IER_TXEMPTY ); - } - else - { - USART_DisableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IDR_TXRDY ); - USART_EnableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IER_TXEMPTY ); - } -} - -BOOL -xMBPortSerialInit( UCHAR ucPORT, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity ) -{ - BOOL bStatus = FALSE; - uint32_t uiMode = US_MR_USART_MODE_NORMAL; - if( ( ucPORT <= USART_IDX_LAST ) ) - { - bStatus = TRUE; - switch ( eParity ) - { - case MB_PAR_NONE: - uiMode |= US_MR_PAR_NONE | US_MR_NBSTOP_2_BIT; - break; - case MB_PAR_ODD: - uiMode |= US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT; - break; - case MB_PAR_EVEN: - uiMode |= US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT; - break; - default: - bStatus = FALSE; - break; - } - - switch ( ucDataBits ) - { - case 8: - uiMode |= US_MR_CHRL_8_BITS; - break; - case 7: - uiMode |= US_MR_CHRL_7_BITS; - break; - default: - bStatus = FALSE; - } - - if( TRUE == bStatus ) - { - ucUsedPort = ucPORT; - - NVIC_DisableIRQ( xUSARTHWMappings[ucUsedPort].xUSARTIrq ); - - PIO_Configure( xUSARTHWMappings[ucUsedPort].xUSARTPins, xUSARTHWMappings[ucUsedPort].xUSARTPinsCnt ); - if( NULL != xUSARTHWMappings[ucUsedPort].USARTNotREPin ) - { - PIO_Configure( xUSARTHWMappings[ucUsedPort].USARTNotREPin, 1 ); - } - if( NULL != xUSARTHWMappings[ucUsedPort].USARTDEPin ) - { - PIO_Configure( xUSARTHWMappings[ucUsedPort].USARTDEPin, 1 ); - } - PMC_EnablePeripheral( xUSARTHWMappings[ucUsedPort].xUSARTID ); - USART_Configure( xUSARTHWMappings[ucUsedPort].pUsart, uiMode, ulBaudRate, BOARD_MCK ); - - NVIC_ClearPendingIRQ( xUSARTHWMappings[ucUsedPort].xUSARTIrq ); - NVIC_SetPriority( xUSARTHWMappings[ucUsedPort].xUSARTIrq, 0xF << 4 ); - NVIC_EnableIRQ( xUSARTHWMappings[ucUsedPort].xUSARTIrq ); - } - } - - return bStatus; -} - -void -vMBPortSerialClose( void ) -{ - if( USART_INVALID_PORT != ucUsedPort ) - { - NVIC_DisableIRQ( xUSARTHWMappings[ucUsedPort].xUSARTIrq ); - PMC_DisablePeripheral( xUSARTHWMappings[ucUsedPort].xUSARTID ); - if( NULL != xUSARTHWMappings[ucUsedPort].USARTNotREPin ) - { - PIO_Clear( xUSARTHWMappings[ucUsedPort].USARTDEPin ); - } - if( NULL != xUSARTHWMappings[ucUsedPort].USARTDEPin ) - { - PIO_Clear( xUSARTHWMappings[ucUsedPort].USARTNotREPin ); - } - ucUsedPort = USART_INVALID_PORT; - } -} - -BOOL -xMBPortSerialPutByte( CHAR ucByte ) -{ - USART1->US_THR = ucByte; - return TRUE; -} - -BOOL -xMBPortSerialGetByte( CHAR * pucByte ) -{ - *pucByte = USART1->US_RHR; - return TRUE; -} - -void -vUSARTHandler( void ) -{ - uint32_t uiCSR; - uint32_t uiIMR; - BOOL bTaskWoken = FALSE; - - vMBPortSetWithinException( TRUE ); - - uiCSR = xUSARTHWMappings[ucUsedPort].pUsart->US_CSR; - uiIMR = xUSARTHWMappings[ucUsedPort].pUsart->US_IMR; - uint32_t uiCSRMasked = uiCSR & uiIMR; - - if( uiCSRMasked & US_CSR_RXRDY ) - { - bTaskWoken = pxMBFrameCBByteReceived( ); - } - if( uiCSRMasked & US_CSR_TXRDY ) - { - bTaskWoken = pxMBFrameCBTransmitterEmpty( ); - } - if( uiCSRMasked & US_CSR_TXEMPTY ) - { - if( NULL != xUSARTHWMappings[ucUsedPort].USARTDEPin ) - { - PIO_Clear( xUSARTHWMappings[ucUsedPort].USARTDEPin ); - } - if( NULL != xUSARTHWMappings[ucUsedPort].USARTNotREPin ) - { - PIO_Clear( xUSARTHWMappings[ucUsedPort].USARTNotREPin ); - } - USART_DisableIt( xUSARTHWMappings[ucUsedPort].pUsart, US_IER_TXEMPTY ); - } - vMBPortSetWithinException( FALSE ); - - portEND_SWITCHING_ISR( bTaskWoken ? pdTRUE : pdFALSE ); -} - -#if USART1_ENABLED == 1 -void -USART1_IrqHandler( void ) -{ - vUSARTHandler( ); -} -#endif - -#if USART0_ENABLED == 1 -void -USART0_IrqHandler( void ) -{ - vUSARTHandler( ); -} -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/port/porttimer.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/port/porttimer.c deleted file mode 100644 index 16cc1ab43..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/ATSAM3S_FREERTOS/port/porttimer.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * FreeModbus Libary: Atmel AT91SAM3S Demo Application - * Copyright (C) 2010 Christian Walter - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * IF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include -#include -#include -#include - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "port.h" -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_TIMER_DEBUG ( 0 ) -#define MB_TIMER_PRESCALER ( 128UL ) -#define MB_TIMER_TICKS ( BOARD_MCK / MB_TIMER_PRESCALER ) -#define MB_50US_TICKS ( 20000UL ) - -#define TCX ( TC0 ) -#define TCXIRQ ( TC0_IRQn ) -#define TCCHANNEL ( 0 ) -#define TCX_IRQHANDLER TC0_IrqHandler - -#define TC_CMRX_WAVE ( 0x1 << 15 ) -#define TC_CMRX_TCCLKS_TIMER_DIV4_CLOCK ( 0x3 << 0 ) -#define TC_CMRX_CPCSTOP ( 0x1 << 6 ) -#define TC_CMRX_WAVESEL_UP_RC ( 0x2 << 13 ) - -#define TC_IERX_CPCS ( 0x1 << 4 ) -#define TC_IERX_CPAS ( 0x1 << 2 ) -#define TC_SRX_CPAS ( 0x1 << 2 ) -#if MB_TIMER_DEBUG == 1 -#define TIMER_PIN { 1 << 6, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT } -#endif - -/* ----------------------- Static variables ---------------------------------*/ -#if MB_TIMER_DEBUG == 1 -const static Pin xTimerDebugPins[] = { TIMER_PIN }; -#endif - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortTimersInit( USHORT usTim1Timerout50us ) -{ -#if MB_TIMER_DEBUG == 1 - PIO_Configure( xTimerDebugPins, PIO_LISTSIZE( xTimerDebugPins ) ); -#endif - NVIC_DisableIRQ( TCXIRQ ); - - PMC_EnablePeripheral( ID_TC0 ); - TC_Configure( TCX, 0, TC_CMRX_WAVE | TC_CMRX_TCCLKS_TIMER_DIV4_CLOCK | TC_CMRX_WAVESEL_UP_RC | TC_CMRX_CPCSTOP ); - TCX->TC_CHANNEL[TCCHANNEL].TC_RA = ( MB_TIMER_TICKS * usTim1Timerout50us ) / ( MB_50US_TICKS ); - TCX->TC_CHANNEL[TCCHANNEL].TC_RC = ( MB_TIMER_TICKS * usTim1Timerout50us ) / ( MB_50US_TICKS ); - - NVIC_ClearPendingIRQ( TCXIRQ ); - NVIC_SetPriority( TCXIRQ, 0xF << 4 ); - NVIC_EnableIRQ( TCXIRQ ); - - return TRUE; -} - -void -vMBPortTimerClose( void ) -{ - NVIC_DisableIRQ( TCXIRQ ); - PMC_DisablePeripheral( ID_TC0 ); -} - -void -vMBPortTimersEnable( ) -{ -#if MB_TIMER_DEBUG == 1 - PIO_Set( &xTimerDebugPins[0] ); -#endif - TCX->TC_CHANNEL[TCCHANNEL].TC_IER = TC_IERX_CPAS; - TC_Start( TCX, 0 ); -} - -void -vMBPortTimersDisable( ) -{ - TC_Stop( TCX, 0 ); -#if MB_TIMER_DEBUG == 1 - PIO_Clear( &xTimerDebugPins[0] ); -#endif -} - -void -vMBPortTimersDelay( USHORT usTimeOutMS ) -{ - vTaskDelay( usTimeOutMS / portTICK_RATE_MS ); -} - -void -TCX_IRQHANDLER( void ) -{ - uint32_t xTCX_IMRX = TCX->TC_CHANNEL[TCCHANNEL].TC_IMR; - uint32_t xTCX_SRX = TCX->TC_CHANNEL[TCCHANNEL].TC_SR; - uint32_t uiSRMasked = xTCX_SRX & xTCX_IMRX; - BOOL bTaskWoken = FALSE; - - vMBPortSetWithinException( TRUE ); - - if( ( uiSRMasked & TC_SRX_CPAS ) > 0 ) - { -#if MB_TIMER_DEBUG == 1 - PIO_Clear( &xTimerDebugPins[0] ); -#endif - ( void )pxMBPortCBTimerExpired( ); - } - vMBPortSetWithinException( FALSE ); - - portEND_SWITCHING_ISR( bTaskWoken ? pdTRUE : pdFALSE ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/Makefile b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/Makefile deleted file mode 100644 index 5bc60a72f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/Makefile +++ /dev/null @@ -1,103 +0,0 @@ -############################################################################### -# Makefile for the project AVR -############################################################################### - -## General Flags -PROJECT = demo -MCU = atmega168 -TARGET = demo - -CC=/opt/gcc-avr/bin/avr-gcc -OBJCOPY=/opt/gcc-avr/bin/avr-objcopy -AVRDUDE=/opt/gcc-avr/bin/avrdude - -## Options common to compile, link and assembly rules -COMMON = -mmcu=$(MCU) - -## Compile options common for all C compilation units. -CFLAGS = $(COMMON) \ - -Iport -I. \ - -I../../modbus/rtu -I../../modbus/ascii -I../../modbus/include -CFLAGS += -Wall -gstabs -DF_CPU=20000000UL -Os -Wall -Wstrict-prototypes - -CFLAGS += -Wp,-M,-MP,-MT,$(*F).o,-MF,dep/$(@F).d - -## Assembly specific flags -ASMFLAGS = $(COMMON) -ASMFLAGS += -x assembler-with-cpp -Wa,-gstabs - -## Linker flags -LDFLAGS = $(COMMON) -LDFLAGS += -Wl,-Map=$(TARGET).map,--cref - -## Intel Hex file production flags -HEX_FLASH_FLAGS = -R .eeprom - -HEX_EEPROM_FLAGS = -j .eeprom -HEX_EEPROM_FLAGS += --set-section-flags=.eeprom="alloc,load" -HEX_EEPROM_FLAGS += --change-section-lma .eeprom=0 - - -## Objects that must be built in order to link -#OBJECTS = excoils.o -OBJECTS = demo.o -MBPORTOBJECTS = port/portserial.o \ - port/portevent.o \ - port/porttimer.o \ - port/mbcrc.o -MBOBJECTS = ../../modbus/mb.o \ - ../../modbus/rtu/mbrtu.o \ - ../../modbus/ascii/mbascii.o \ - ../../modbus/functions/mbfunccoils.o \ - ../../modbus/functions/mbfuncdiag.o \ - ../../modbus/functions/mbfuncholding.o \ - ../../modbus/functions/mbfuncinput.o \ - ../../modbus/functions/mbfuncother.o \ - ../../modbus/functions/mbfuncdisc.o \ - ../../modbus/functions/mbutils.o - - -## Build -all: $(TARGET).elf $(TARGET).cof $(TARGET).hex $(TARGET).eep - -## Compile -demo.o: demo.c - $(CC) $(INCLUDES) $(CFLAGS) -c $< - -##Link -$(TARGET).elf: $(OBJECTS) $(MBOBJECTS) $(MBPORTOBJECTS) - $(CC) $(LDFLAGS) $(OBJECTS) $(MBPORTOBJECTS) $(MBOBJECTS) $(LIBDIRS) $(LIBS) -o $(TARGET).elf - -%.hex: $(TARGET).elf - $(OBJCOPY) -O ihex $(HEX_FLASH_FLAGS) $< $@ - -%.cof: $(TARGET).elf - $(OBJCOPY) --debugging \ - --change-section-address .data-0x800000 \ - --change-section-address .bss-0x800000 \ - --change-section-address .noinit-0x800000 \ - --change-section-address .eeprom-0x810000 -O coff-avr $< $@ - -%.eep: $(TARGET).elf - $(OBJCOPY) $(HEX_EEPROM_FLAGS) -O ihex $< $@ - -%.lss: $(TARGET) - $(OBJCOPY) -h -S $< > $@ - -flash: - $(AVRDUDE) -p m168 -c stk200 -U flash:w:$(TARGET).hex - -#size: ${TARGET} -# @echo -# @sh avr-mem.sh ${TARGET} ${MCU} - -## Clean target -.PHONY: clean -clean: - -rm -rf $(OBJECTS) $(MBOBJECTS) $(MBPORTOBJECTS) - -rm -rf $(TARGET).elf $(TARGET).hex $(TARGET).eep $(TARGET).cof $(TARGET).map - -rm -rf dep - -## Other dependencies --include $(shell mkdir dep 2>/dev/null) $(wildcard dep/*) - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/README.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/README.txt deleted file mode 100644 index bdceaf1b0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/README.txt +++ /dev/null @@ -1,81 +0,0 @@ - - FREEMODBUS 0.4 AVR EXAMPLE - ========================== - -REQUIREMENTS -============ - -This example contains a simple demo program for FreeMODBUS for an ATMega168 -processor. It requires a wired serial port to a host processor and a Modbus -Master Software on the PC side to be useful. Demo versions of Modbus Masters -can be found in [1] and [2]. - -In addition it requires an ATMega168 target microcontroller. The micro- -controller must be configured for 20Mhz if the binary image is going to -be used. Otherwise the constant F_CPU in the Makefile must be changed -and the source code recompiled. - -INSTALLATION -============ - -If avrdude [3] is used for flashing the Makefile contains a target 'flash' -which can be executed by calling 'make flash'. This programs the micro- -controller with the current binary named 'demo.hex'. - -SOURCE -====== - -If one wants to recompile the software the WinAVR tools should be installed -if the host platform is Microsoft Windows. For Unix the necessary tools -must be recompiled from source. The WinAVR tools can be found at [4]. - -TESTING -======= - -Start the Modbus Sample Application and test if the input registers starting -at protocol address 1000 can be read. There are four registers value available -and the output should look like: - -Polling slave (Ctrl-C to stop) ... -[1000]: 6474 -[1001]: 0 -[1002]: 0 -[1003]: 0 -Polling slave (Ctrl-C to stop) ... -[1000]: -8831 -[1001]: 0 -[1002]: 0 -[1003]: 0 -Polling slave (Ctrl-C to stop) ... - -The simple testing utility used in the 'demo_rtu.bat' script can be found -at [5]. - -PROBLEMS -======== - -If the provided binary is not working as expected make sure that the fuse -bits for the microcontroller are programmed correctly. In addition it would -be a good idea to download a simple serial test programm to test serial -communication with the host. The fuse bits required for an ATMega168 with -an 20Mhz crystal must be set to the following values: - - Fuse Low Byte: 1XXXXXX - | - CKDIV8 - -The other values depend on the crystal used and the startup time. The -authors configuration used a value of 0xFF. Again if avrdude is used the -value can be set by: - - avrdude -p m168 -c stk200 -U lfuse:w:0xFF:m - -where the 0xFF at the end of line is the actual value. - -[1] WinTech ModScan32: http://www.win-tech.com/html/modscan32.htm -[2] Modus Poll: http://www.modbustools.com/modbus_poll.asp -[3] AVRDUDE AVR Downloader/UploaDEr: http://www.nongnu.org/avrdude/ -[4] WinAVR: http://winavr.sourceforge.net/ -[5] FieldTalk Modpoll: http://www.focus-sw.com/fieldtalk/modpoll.html - -Version: $Id: README.txt,v 1.1 2006/05/08 21:07:01 wolti Exp $ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/avrdude.conf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/avrdude.conf deleted file mode 100644 index 09f2bc3c6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/avrdude.conf +++ /dev/null @@ -1,6846 +0,0 @@ -# $Id: avrdude.conf,v 1.1 2006/02/25 18:40:46 wolti Exp $ -# -# AVRDUDE Configuration File -# -# This file contains configuration data used by AVRDUDE which describes -# the programming hardware pinouts and also provides part definitions. -# AVRDUDE's "-C" command line option specifies the location of the -# configuration file. The "-c" option names the programmer configuration -# which must match one of the entry's "id" parameter. The "-p" option -# identifies which part AVRDUDE is going to be programming and must match -# one of the parts' "id" parameter. -# -# Possible entry formats are: -# -# programmer -# id = [, [, ] ...] ; # are quoted strings -# desc = ; # quoted string -# type = par | stk500 | stk500v2 | avr910 | jtagmki | jtagmkii; # programmer type -# baudrate = ; # baudrate for avr910-programmer -# vcc = [, ... ] ; # pin number(s) -# reset = ; # pin number -# sck = ; # pin number -# mosi = ; # pin number -# miso = ; # pin number -# errled = ; # pin number -# rdyled = ; # pin number -# pgmled = ; # pin number -# vfyled = ; # pin number -# ; -# -# part -# id = ; # quoted string -# desc = ; # quoted string -# has_jtag = ; # part has JTAG i/f -# devicecode = ; # deprecated, use stk500_devcode -# stk500_devcode = ; # numeric -# avr910_devcode = ; # numeric -# chip_erase_delay = ; # micro-seconds -# reset = dedicated | io; -# retry_pulse = reset | sck; -# pgm_enable = ; -# chip_erase = ; -# chip_erase_delay = ; # chip erase delay (us) -# # STK500 parameters (parallel programming IO lines) -# pagel = ; # pin name in hex, i.e., 0xD7 -# bs2 = ; # pin name in hex, i.e., 0xA0 -# serial = ; # can use serial downloading -# parallel = ; # can use par. programming -# # STK500v2 parameters, to be taken from Atmel's XML files -# timeout = ; -# stabdelay = ; -# cmdexdelay = ; -# synchloops = ; -# bytedelay = ; -# pollvalue = ; -# pollindex = ; -# predelay = ; -# postdelay = ; -# pollmethod = ; -# mode = ; -# delay = ; -# blocksize = ; -# readsize = ; -# # JTAG ICE mkII parameters, also from XML files -# allowfullpagebitstream = ; -# enablepageprogramming = ; -# idr = ; # IO addr of IDR (OCD) reg. -# rampz = ; # IO addr of RAMPZ reg. -# spmcr = ; # mem addr of SPMC[S]R reg. -# eecr = ; # mem addr of EECR reg. -# # (only when != 0x3c) -# -# memory -# paged = ; # yes / no -# size = ; # bytes -# page_size = ; # bytes -# num_pages = ; # numeric -# min_write_delay = ; # micro-seconds -# max_write_delay = ; # micro-seconds -# readback_p1 = ; # byte value -# readback_p2 = ; # byte value -# pwroff_after_write = ; # yes / no -# read = ; -# write = ; -# read_lo = ; -# read_hi = ; -# write_lo = ; -# write_hi = ; -# loadpage_lo = ; -# loadpage_hi = ; -# writepage = ; -# ; -# ; -# -# If any of the above parameters are not specified, the default value -# of 0 is used for numerics or the empty string ("") for string -# values. If a required parameter is left empty, AVRDUDE will -# complain. -# -# NOTES: -# * 'devicecode' is the device code used by the STK500 (see codes -# listed below) -# * Not all memory types will implement all instructions. -# * AVR Fuse bits and Lock bits are implemented as a type of memory. -# * Example memory types are: -# "flash", "eeprom", "fuse", "lfuse" (low fuse), "hfuse" (high -# fuse), "signature", "calibration", "lock" -# * The memory type specified on the avrdude command line must match -# one of the memory types defined for the specified chip. -# * The pwroff_after_write flag causes avrdude to attempt to -# power the device off and back on after an unsuccessful write to -# the affected memory area if VCC programmer pins are defined. If -# VCC pins are not defined for the programmer, a message -# indicating that the device needs a power-cycle is printed out. -# This flag was added to work around a problem with the -# at90s4433/2333's; see the at90s4433 errata at: -# -# http://www.atmel.com/atmel/acrobat/doc1280.pdf -# -# INSTRUCTION FORMATS -# -# Instruction formats are specified as a comma seperated list of -# string values containing information (bit specifiers) about each -# of the 32 bits of the instruction. Bit specifiers may be one of -# the following formats: -# -# '1' = the bit is always set on input as well as output -# -# '0' = the bit is always clear on input as well as output -# -# 'x' = the bit is ignored on input and output -# -# 'a' = the bit is an address bit, the bit-number matches this bit -# specifier's position within the current instruction byte -# -# 'aN' = the bit is the Nth address bit, bit-number = N, i.e., a12 -# is address bit 12 on input, a0 is address bit 0. -# -# 'i' = the bit is an input data bit -# -# 'o' = the bit is an output data bit -# -# Each instruction must be composed of 32 bit specifiers. The -# instruction specification closely follows the instruction data -# provided in Atmel's data sheets for their parts. -# -# See below for some examples. -# -# -# The following are STK500 part device codes to use for the -# "devicecode" field of the part. These came from Atmel's software -# section avr061.zip which accompanies the application note -# AVR061 available from: -# -# http://www.atmel.com/atmel/acrobat/doc2525.pdf -# - -#define ATTINY10 0x10 -#define ATTINY11 0x11 -#define ATTINY12 0x12 -#define ATTINY15 0x13 -#define ATTINY13 0x14 - -#define ATTINY22 0x20 -#define ATTINY26 0x21 -#define ATTINY28 0x22 -#define ATTINY2313 0x23 - -#define AT90S1200 0x33 - -#define AT90S2313 0x40 -#define AT90S2323 0x41 -#define AT90S2333 0x42 -#define AT90S2343 0x43 - -#define AT90S4414 0x50 -#define AT90S4433 0x51 -#define AT90S4434 0x52 -#define ATMEGA48 0x59 - -#define AT90S8515 0x60 -#define AT90S8535 0x61 -#define AT90C8534 0x62 -#define ATMEGA8515 0x63 -#define ATMEGA8535 0x64 - -#define ATMEGA8 0x70 -#define ATMEGA88 0x73 -#define ATMEGA168 0x86 - -#define ATMEGA161 0x80 -#define ATMEGA163 0x81 -#define ATMEGA16 0x82 -#define ATMEGA162 0x83 -#define ATMEGA169 0x84 - -#define ATMEGA323 0x90 -#define ATMEGA32 0x91 - -#define ATMEGA64 0xA0 - -#define ATMEGA103 0xB1 -#define ATMEGA128 0xB2 -#define AT90CAN128 0xB3 - -#define AT86RF401 0xD0 - -#define AT89START 0xE0 -#define AT89S51 0xE0 -#define AT89S52 0xE1 - - -# -# Overall avrdude defaults -# -default_parallel = "lpt1"; -default_serial = "com1"; - - -# -# PROGRAMMER DEFINITIONS -# - -programmer - id = "avrisp"; - desc = "Atmel AVR ISP"; - type = stk500; -; - -programmer - id = "avrispv2"; - desc = "Atmel AVR ISP V2"; - type = stk500v2; -; - -programmer - id = "avrispmkII"; - desc = "Atmel AVR ISP mkII"; - type = stk500v2; -; - -programmer - id = "avrisp2"; - desc = "Atmel AVR ISP mkII"; - type = stk500v2; -; - -programmer - id = "stk500"; - desc = "Atmel STK500"; - type = stk500; -; - -programmer - id = "stk500v2"; - desc = "Atmel STK500 V2"; - type = stk500v2; -; - -programmer - id = "avr910"; - desc = "Atmel Low Cost Serial Programmer"; - type = avr910; -; - -programmer - id = "butterfly"; - desc = "Atmel Butterfly Development Board"; - type = butterfly; -; - -programmer - id = "avr109"; - desc = "Atmel AppNote AVR109 Boot Loader"; - type = butterfly; -; - -programmer - id = "avr911"; - desc = "Atmel AppNote AVR911 AVROSP"; - type = butterfly; -; - -programmer - id = "jtagmkI"; - desc = "Atmel JTAG ICE (mkI)"; - baudrate = 115200; # default is 115200 - type = jtagmki; -; - -# easier to type -programmer - id = "jtag1"; - desc = "Atmel JTAG ICE (mkI)"; - baudrate = 115200; # default is 115200 - type = jtagmki; -; - -# easier to type -programmer - id = "jtag1slow"; - desc = "Atmel JTAG ICE (mkI)"; - baudrate = 19200; - type = jtagmki; -; - -programmer - id = "jtagmkII"; - desc = "Atmel JTAG ICE mkII"; - baudrate = 19200; # default is 19200 - type = jtagmkii; -; - -# easier to type -programmer - id = "jtag2slow"; - desc = "Atmel JTAG ICE mkII"; - baudrate = 19200; # default is 19200 - type = jtagmkii; -; - -# JTAG ICE mkII @ 115200 Bd -programmer - id = "jtag2fast"; - desc = "Atmel JTAG ICE mkII"; - baudrate = 115200; - type = jtagmkii; -; - -# make the fast one the default, people will love that -programmer - id = "jtag2"; - desc = "Atmel JTAG ICE mkII"; - baudrate = 115200; - type = jtagmkii; -; - -programmer - id = "pavr"; - desc = "Jason Kyle's pAVR Serial Programmer"; - type = avr910; -; - -# Parallel port programmers. - -programmer - id = "bsd"; - desc = "Brian Dean's Programmer, http://www.bsdhome.com/avrdude/"; - type = par; - vcc = 2, 3, 4, 5; - reset = 7; - sck = 8; - mosi = 9; - miso = 10; -; - -programmer - id = "stk200"; - desc = "STK200"; - type = par; - buff = 4, 5; - sck = 6; - mosi = 7; - reset = 9; - miso = 10; -; - -# The programming dongle used by the popular Ponyprog -# utility. It is almost similar to the STK200 one, -# except that there is a LED indicating that the -# programming is currently in progress. - -programmer - id = "pony-stk200"; - desc = "Pony Prog STK200"; - type = par; - buff = 4, 5; - sck = 6; - mosi = 7; - reset = 9; - miso = 10; - pgmled = 8; -; - -programmer - id = "dt006"; - desc = "Dontronics DT006"; - type = par; - reset = 4; - sck = 5; - mosi = 2; - miso = 11; -; - -programmer - id = "bascom"; - desc = "Bascom SAMPLE programming cable"; - type = par; - reset = 4; - sck = 5; - mosi = 2; - miso = 11; -; - -programmer - id = "alf"; - desc = "Nightshade ALF-PgmAVR, http://nightshade.homeip.net/"; - type = par; - vcc = 2, 3, 4, 5; - buff = 6; - reset = 7; - sck = 8; - mosi = 9; - miso = 10; - errled = 1; - rdyled = 14; - pgmled = 16; - vfyled = 17; -; - -programmer - id = "sp12"; - desc = "Steve Bolt's Programmer"; - type = par; - vcc = 4,5,6,7,8; - reset = 3; - sck = 2; - mosi = 9; - miso = 11; -; - -programmer - id = "picoweb"; - desc = "Picoweb Programming Cable, http://www.picoweb.net/"; - type = par; - reset = 2; - sck = 3; - mosi = 4; - miso = 13; -; - -programmer - id = "abcmini"; - desc = "ABCmini Board, aka Dick Smith HOTCHIP"; - type = par; - reset = 4; - sck = 3; - mosi = 2; - miso = 10; -; - -programmer - id = "futurlec"; - desc = "Futurlec.com programming cable."; - type = par; - reset = 3; - sck = 2; - mosi = 1; - miso = 10; -; - - -# From the contributor of the "xil" jtag cable: -# The "vcc" definition isn't really vcc (the cable gets its power from -# the programming circuit) but is necessary to switch one of the -# buffer lines (trying to add it to the "buff" lines doesn't work). -# With this, TMS connects to RESET, TDI to MOSI, TDO to MISO and TCK -# to SCK (plus vcc/gnd of course) -programmer - id = "xil"; - desc = "Xilinx JTAG cable"; - type = par; - mosi = 2; - sck = 3; - reset = 4; - buff = 5; - miso = 13; - vcc = 6; -; - - -programmer - id = "dapa"; - desc = "Direct AVR Parallel Access cable"; - type = par; - vcc = 3; - reset = 16; - sck = 1; - mosi = 2; - miso = 11; -; - - -# -# some ultra cheap programmers use bitbanging on the -# serialport. -# - -# serial ponyprog design (dasa2 in uisp) -# reset=!txd sck=rts mosi=dtr miso=cts - -programmer - id = "ponyser"; - desc = "serial port banging, design ponyprog serial"; - type = serbb; - reset = ~3; - sck = 6; - mosi = 4; - miso = 7; -; - -# unknown (dasa in uisp) -# reset=rts sck=dtr mosi=txd miso=cts - -programmer - id = "dasa"; - desc = "serial port banging, reset=rts sck=dtr mosi=txd miso=cts"; - type = serbb; - reset = 6; - sck = 4; - mosi = 3; - miso = 7; -; - -# unknown (dasa3 in uisp) -# reset=!dtr sck=rts mosi=txd miso=cts - -programmer - id = "dasa3"; - desc = "serial port banging, reset=!dtr sck=rts mosi=txd miso=cts"; - type = serbb; - reset = ~4; - sck = 6; - mosi = 3; - miso = 7; -; - -# -# PART DEFINITIONS -# - -#------------------------------------------------------------ -# ATtiny12 -#------------------------------------------------------------ - -part - id = "t12"; - desc = "ATtiny12"; - stk500_devcode = 0x12; - avr910_devcode = 0x55; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - memory "eeprom" - size = 64; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 x x x x x x x x", - "x x a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 x x x x x x x x", - "x x a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 8; - blocksize = 64; - readsize = 256; - ; - - memory "flash" - size = 1024; - min_write_delay = 4500; - max_write_delay = 20000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 5; - blocksize = 128; - readsize = 256; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x o o x"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "fuse" - size = 1; - read = "0 1 0 1 0 0 0 0 x x x x x x x x", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 x x x x x", - "x x x x x x x x i i i i i i i i"; - ; -; - -#------------------------------------------------------------ -# ATtiny13 -#------------------------------------------------------------ - -part - id = "t13"; - desc = "ATtiny13"; - stk500_devcode = 0x14; - chip_erase_delay = 4000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - memory "eeprom" - size = 64; - min_write_delay = 4000; - max_write_delay = 4000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", - "x x a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", - "x x a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x41; - delay = 5; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 1024; - page_size = 32; - num_pages = 32; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 0 0 0 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 0 0 0 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 0 0 0 a8", - " a7 a6 a5 a4 x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - -; - - -#------------------------------------------------------------ -# ATtiny15 -#------------------------------------------------------------ - -part - id = "t15"; - desc = "ATtiny15"; - stk500_devcode = 0x13; - avr910_devcode = 0x56; - chip_erase_delay = 8200; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - memory "eeprom" - size = 64; - min_write_delay = 8200; - max_write_delay = 8200; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 x x x x x x x x", - "x x a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 x x x x x x x x", - "x x a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 10; - blocksize = 64; - readsize = 256; - ; - - memory "flash" - size = 1024; - min_write_delay = 4100; - max_write_delay = 4100; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 5; - blocksize = 128; - readsize = 256; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x o o x"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "fuse" - size = 1; - read = "0 1 0 1 0 0 0 0 x x x x x x x x", - "x x x x x x x x o o o o x x o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 x x x x x", - "x x x x x x x x i i i i 1 1 i i"; - ; -; - -#------------------------------------------------------------ -# AT90s1200 -#------------------------------------------------------------ - -part - id = "1200"; - desc = "AT90S1200"; - stk500_devcode = 0x33; - avr910_devcode = 0x13; - pagel = 0xd7; - bs2 = 0xa0; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 1; - bytedelay = 0; - pollindex = 0; - pollvalue = 0xFF; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - memory "eeprom" - size = 64; - min_write_delay = 4000; - max_write_delay = 9000; - readback_p1 = 0x00; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 x x x x x x x x", - "x x a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 x x x x x x x x", - "x x a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 20; - blocksize = 32; - readsize = 256; - ; - memory "flash" - size = 1024; - min_write_delay = 4000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x02; - delay = 15; - blocksize = 128; - readsize = 256; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "fuse" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - read = "0 1 0 1 0 0 0 0 x x x x x x x x", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 i i i i i", - "x x x x x x x x x x x x x x x x"; - ; - memory "lock" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x o o x"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - ; - ; - -#------------------------------------------------------------ -# AT90s4414 -#------------------------------------------------------------ - -part - id = "4414"; - desc = "AT90S4414"; - stk500_devcode = 0x50; - avr910_devcode = 0x28; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - memory "eeprom" - size = 256; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0x80; - readback_p2 = 0x7f; - read = " 1 0 1 0 0 0 0 0 x x x x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0 x x x x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 64; - readsize = 256; - ; - memory "flash" - size = 4096; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0x7f; - readback_p2 = 0x7f; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 64; - readsize = 256; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# AT90s2313 -#------------------------------------------------------------ - -part - id = "2313"; - desc = "AT90S2313"; - stk500_devcode = 0x40; - avr910_devcode = 0x20; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - memory "eeprom" - size = 128; - min_write_delay = 4000; - max_write_delay = 9000; - readback_p1 = 0x80; - readback_p2 = 0x7f; - read = "1 0 1 0 0 0 0 0 x x x x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 x x x x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 64; - readsize = 256; - ; - memory "flash" - size = 2048; - min_write_delay = 4000; - max_write_delay = 9000; - readback_p1 = 0x7f; - readback_p2 = 0x7f; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 256; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x i i x", - "x x x x x x x x x x x x x x x x"; - ; - ; - -#------------------------------------------------------------ -# AT90s2333 -#------------------------------------------------------------ - -part - id = "2333"; -##### WARNING: No XML file for device 'AT90S2333'! ##### - desc = "AT90S2333"; - stk500_devcode = 0x42; - avr910_devcode = 0x34; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - memory "eeprom" - size = 128; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0x00; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 x x x x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 x x x x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - ; - memory "flash" - size = 2048; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "fuse" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - pwroff_after_write = yes; - read = "0 1 0 1 0 0 0 0 x x x x x x x x", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 i i i i i", - "x x x x x x x x x x x x x x x x"; - ; - memory "lock" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x o o x"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - ; - ; - - -#------------------------------------------------------------ -# AT90s2343 (also AT90s2323 and ATtiny22) -#------------------------------------------------------------ - -part - id = "2343"; - desc = "AT90S2343"; - stk500_devcode = 0x43; - avr910_devcode = 0x4c; - chip_erase_delay = 18000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - memory "eeprom" - size = 128; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0x00; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0", - "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0", - "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 64; - readsize = 256; - ; - memory "flash" - size = 2048; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 128; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "fuse" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x o o o x x x x o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 i", - "x x x x x x x x x x x x x x x x"; - ; - memory "lock" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x o o o x x x x o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - ; - ; - - -#------------------------------------------------------------ -# AT90s4433 -#------------------------------------------------------------ - -part - id = "4433"; - desc = "AT90S4433"; - stk500_devcode = 0x51; - avr910_devcode = 0x30; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - memory "eeprom" - size = 256; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0x00; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0 x x x x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0 x x x x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 256; - ; - memory "flash" - size = 4096; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 256; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "fuse" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - pwroff_after_write = yes; - read = "0 1 0 1 0 0 0 0 x x x x x x x x", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 i i i i i", - "x x x x x x x x x x x x x x x x"; - ; - memory "lock" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x o o x"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - ; - ; - -#------------------------------------------------------------ -# AT90s4434 -#------------------------------------------------------------ - -part - id = "4434"; -##### WARNING: No XML file for device 'AT90S4434'! ##### - desc = "AT90S4434"; - stk500_devcode = 0x52; - avr910_devcode = 0x6c; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - memory "eeprom" - size = 256; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0x00; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0 x x x x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0 x x x x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - ; - memory "flash" - size = 4096; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "fuse" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - read = "0 1 0 1 0 0 0 0 x x x x x x x x", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 i i i i i", - "x x x x x x x x x x x x x x x x"; - ; - memory "lock" - size = 1; - min_write_delay = 9000; - max_write_delay = 20000; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x o o x"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - ; - ; - -#------------------------------------------------------------ -# AT90s8515 -#------------------------------------------------------------ - -part - id = "8515"; - desc = "AT90S8515"; - stk500_devcode = 0x60; - avr910_devcode = 0x38; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - memory "eeprom" - size = 512; - min_write_delay = 4000; - max_write_delay = 9000; - readback_p1 = 0x80; - readback_p2 = 0x7f; - read = " 1 0 1 0 0 0 0 0 x x x x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0 x x x x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 256; - ; - memory "flash" - size = 8192; - min_write_delay = 4000; - max_write_delay = 9000; - readback_p1 = 0x7f; - readback_p2 = 0x7f; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 256; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "fuse" - size = 1; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x x x o"; - write = "1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 i", - "x x x x x x x x x x x x x x x x"; - ; - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x o o x x x x x x"; - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - ; - ; - -#------------------------------------------------------------ -# AT90s8535 -#------------------------------------------------------------ - -part - id = "8535"; - desc = "AT90S8535"; - stk500_devcode = 0x61; - avr910_devcode = 0x68; - chip_erase_delay = 20000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - memory "eeprom" - size = 512; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0x00; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0 x x x x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0 x x x x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 256; - ; - memory "flash" - size = 8192; - min_write_delay = 9000; - max_write_delay = 20000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write_lo = " 0 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - write_hi = " 0 1 0 0 1 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 128; - readsize = 256; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "fuse" - size = 1; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x x x o"; - write = "1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 i", - "x x x x x x x x x x x x x x x x"; - ; - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x o o x x x x x x"; - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - ; - ; - -#------------------------------------------------------------ -# ATmega103 -#------------------------------------------------------------ - -part - id = "m103"; - desc = "ATMEGA103"; - stk500_devcode = 0xB1; - avr910_devcode = 0x41; - chip_erase_delay = 112000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - memory "eeprom" - size = 4096; - min_write_delay = 4000; - max_write_delay = 9000; - readback_p1 = 0x80; - readback_p2 = 0x7f; - read = " 1 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 64; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 131072; - page_size = 256; - num_pages = 512; - min_write_delay = 22000; - max_write_delay = 56000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x11; - delay = 70; - blocksize = 256; - readsize = 256; - ; - - memory "fuse" - size = 1; - read = "0 1 0 1 0 0 0 0 x x x x x x x x", - "x x x x x x x x x x o x o 1 o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 1 i 1 i i", - "x x x x x x x x x x x x x x x x"; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x o o x"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 i i 1", - "x x x x x x x x x x x x x x x x"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - - -#------------------------------------------------------------ -# ATmega64 -#------------------------------------------------------------ - -part - id = "m64"; - desc = "ATMEGA64"; - has_jtag = yes; - stk500_devcode = 0xA0; - chip_erase_delay = 9000; - pagel = 0xD7; - bs2 = 0xA0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - idr = 0x22; - spmcr = 0x68; - allowfullpagebitstream = yes; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 2048; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 20; - blocksize = 64; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 65536; - page_size = 256; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 128; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - - - - -#------------------------------------------------------------ -# ATmega128 -#------------------------------------------------------------ - -part - id = "m128"; - desc = "ATMEGA128"; - has_jtag = yes; - stk500_devcode = 0xB2; - avr910_devcode = 0x43; - chip_erase_delay = 9000; - pagel = 0xD7; - bs2 = 0xA0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - idr = 0x22; - spmcr = 0x68; - rampz = 0x3b; - allowfullpagebitstream = yes; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 4096; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 12; - blocksize = 64; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 131072; - page_size = 256; - num_pages = 512; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 128; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 4; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# AT90CAN128 -#------------------------------------------------------------ - -part - id = "c128"; - desc = "AT90CAN128"; - has_jtag = yes; - stk500_devcode = 0xB3; -# avr910_devcode = 0x43; - chip_erase_delay = 9000; - pagel = 0xD7; - bs2 = 0xA0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - idr = 0x31; - spmcr = 0x57; - rampz = 0x3b; - eecr = 0x3f; - allowfullpagebitstream = no; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 4096; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x41; - delay = 20; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 131072; - page_size = 256; - num_pages = 512; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - - -#------------------------------------------------------------ -# ATmega16 -#------------------------------------------------------------ - -part - id = "m16"; - desc = "ATMEGA16"; - has_jtag = yes; - stk500_devcode = 0x82; - avr910_devcode = 0x74; - pagel = 0xd7; - bs2 = 0xa0; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - idr = 0x31; - spmcr = 0x57; - allowfullpagebitstream = yes; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 512; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 10; - blocksize = 128; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 16384; - page_size = 128; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 128; - readsize = 256; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "lfuse" - size = 1; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "calibration" - size = 1; - - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - - -#------------------------------------------------------------ -# ATmega164 -#------------------------------------------------------------ - -# close to ATmega16 - -part - id = "m164"; - desc = "ATMEGA164"; - has_jtag = yes; -# stk500_devcode = 0x82; # no STK500v1 support -# avr910_devcode = 0x?; # try the ATmega16 one:^ - avr910_devcode = 0x74; - pagel = 0xd7; - bs2 = 0xa0; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - idr = 0x31; - spmcr = 0x57; - allowfullpagebitstream = no; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 512; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 10; - blocksize = 128; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 16384; - page_size = 128; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 128; - readsize = 256; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "lfuse" - size = 1; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x 1 1 1 1 1 i i i"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - - -#------------------------------------------------------------ -# ATmega324 -#------------------------------------------------------------ - -# similar to ATmega164 - -part - id = "m324"; - desc = "ATMEGA324"; - has_jtag = yes; -# stk500_devcode = 0x82; # no STK500v1 support -# avr910_devcode = 0x?; # try the ATmega16 one:^ - avr910_devcode = 0x74; - pagel = 0xd7; - bs2 = 0xa0; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - idr = 0x31; - spmcr = 0x57; - allowfullpagebitstream = no; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 1024; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 10; - blocksize = 128; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 32768; - page_size = 256; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "lfuse" - size = 1; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x 1 1 1 1 1 i i i"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - - -#------------------------------------------------------------ -# ATmega644 -#------------------------------------------------------------ - -# similar to ATmega164 - -part - id = "m644"; - desc = "ATMEGA644"; - has_jtag = yes; -# stk500_devcode = 0x82; # no STK500v1 support -# avr910_devcode = 0x?; # try the ATmega16 one:^ - avr910_devcode = 0x74; - pagel = 0xd7; - bs2 = 0xa0; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - idr = 0x31; - spmcr = 0x57; - allowfullpagebitstream = no; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 2048; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 10; - blocksize = 128; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 65536; - page_size = 256; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "lfuse" - size = 1; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x 1 1 1 1 1 i i i"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - - -#------------------------------------------------------------ -# ATmega162 -#------------------------------------------------------------ - -part - id = "m162"; - desc = "ATMEGA162"; - has_jtag = yes; - stk500_devcode = 0x83; - chip_erase_delay = 9000; - pagel = 0xd7; - bs2 = 0xa0; - - idr = 0x04; - spmcr = 0x57; - allowfullpagebitstream = yes; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - memory "flash" - paged = yes; - size = 16384; - page_size = 128; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - mode = 0x41; - delay = 10; - blocksize = 128; - readsize = 256; - - ; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 512; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x41; - delay = 20; - blocksize = 4; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 16000; - max_write_delay = 16000; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 16000; - max_write_delay = 16000; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - min_write_delay = 16000; - max_write_delay = 16000; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x 1 1 1 1 1 i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 16000; - max_write_delay = 16000; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "signature" - size = 3; - - read = "0 0 1 1 0 0 0 0 0 0 x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - - read = "0 0 1 1 1 0 0 0 0 0 x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; -; - - - -#------------------------------------------------------------ -# ATmega163 -#------------------------------------------------------------ - -part - id = "m163"; - desc = "ATMEGA163"; - stk500_devcode = 0x81; - avr910_devcode = 0x64; - chip_erase_delay = 32000; - pagel = 0xd7; - bs2 = 0xa0; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - memory "eeprom" - size = 512; - min_write_delay = 4000; - max_write_delay = 4000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - ; - - memory "flash" - paged = yes; - size = 16384; - page_size = 128; - num_pages = 128; - min_write_delay = 16000; - max_write_delay = 16000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 128; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o x x o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i 1 1 i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x x x x x 1 o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x 1 1 1 1 1 i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x 0 x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega169 -#------------------------------------------------------------ - -part - id = "m169"; - desc = "ATMEGA169"; - has_jtag = yes; - stk500_devcode = 0x85; - avr910_devcode = 0x75; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - idr = 0x31; - spmcr = 0x57; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 512; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_lo = " 1 1 0 0 0 0 0 1", - " 0 0 0 0 0 0 0 0", - " 0 0 0 0 0 0 a1 a0", - " i i i i i i i i"; - - writepage = " 1 1 0 0 0 0 1 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 0 0", - " x x x x x x x x"; - - mode = 0x41; - delay = 20; - blocksize = 4; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 16384; - page_size = 128; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 128; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "lock" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega329 -#------------------------------------------------------------ - -part - id = "m329"; - desc = "ATMEGA329"; - has_jtag = yes; -# stk500_devcode = 0x85; # no STK500 support, only STK500v2 -# avr910_devcode = 0x?; # try the ATmega169 one: - avr910_devcode = 0x75; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - idr = 0x31; - spmcr = 0x57; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 1024; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x41; - delay = 20; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 32768; - page_size = 128; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x i i i x"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega3290 -#------------------------------------------------------------ - -# identical to ATmega329 - -part - id = "m3290"; - desc = "ATMEGA3290"; - has_jtag = yes; -# stk500_devcode = 0x85; # no STK500 support, only STK500v2 -# avr910_devcode = 0x?; # try the ATmega169 one: - avr910_devcode = 0x75; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - idr = 0x31; - spmcr = 0x57; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 1024; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x41; - delay = 20; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 32768; - page_size = 128; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x i i i x"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega649 -#------------------------------------------------------------ - -part - id = "m649"; - desc = "ATMEGA649"; - has_jtag = yes; -# stk500_devcode = 0x85; # no STK500 support, only STK500v2 -# avr910_devcode = 0x?; # try the ATmega169 one: - avr910_devcode = 0x75; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - idr = 0x31; - spmcr = 0x57; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 2048; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x41; - delay = 20; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 65536; - page_size = 256; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x i i i x"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega6490 -#------------------------------------------------------------ - -# identical to ATmega649 - -part - id = "m6490"; - desc = "ATMEGA6490"; - has_jtag = yes; -# stk500_devcode = 0x85; # no STK500 support, only STK500v2 -# avr910_devcode = 0x?; # try the ATmega169 one: - avr910_devcode = 0x75; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - idr = 0x31; - spmcr = 0x57; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 2048; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x x a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x41; - delay = 20; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 65536; - page_size = 256; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x i i i x"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega32 -#------------------------------------------------------------ - -part - id = "m32"; - desc = "ATMEGA32"; - has_jtag = yes; - stk500_devcode = 0x91; - avr910_devcode = 0x72; - chip_erase_delay = 9000; - pagel = 0xd7; - bs2 = 0xa0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - idr = 0x31; - spmcr = 0x57; - allowfullpagebitstream = yes; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 4; /* for parallel programming */ - size = 1024; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 10; - blocksize = 64; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 32768; - page_size = 128; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 a13 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 64; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega161 -#------------------------------------------------------------ - -part - id = "m161"; - desc = "ATMEGA161"; - stk500_devcode = 0x80; - avr910_devcode = 0x60; - chip_erase_delay = 28000; - pagel = 0xd7; - bs2 = 0xa0; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - memory "eeprom" - size = 512; - min_write_delay = 3400; - max_write_delay = 3400; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 5; - blocksize = 128; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 16384; - page_size = 128; - num_pages = 128; - min_write_delay = 14000; - max_write_delay = 14000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x x x a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 16; - blocksize = 128; - readsize = 256; - ; - - memory "fuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 0 0 0 0 x x x x x x x x", - "x x x x x x x x x o x o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 x x x x x", - "x x x x x x x x 1 i 1 i i i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - - -#------------------------------------------------------------ -# ATmega8 -#------------------------------------------------------------ - -part - id = "m8"; - desc = "ATMEGA8"; - stk500_devcode = 0x70; - avr910_devcode = 0x76; - pagel = 0xd7; - bs2 = 0xc2; - chip_erase_delay = 10000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - memory "eeprom" - size = 512; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 10; - blocksize = 128; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 8192; - page_size = 64; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 0 x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 0 x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 64; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 4; - read = "0 0 1 1 1 0 0 0 0 0 x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - - - -#------------------------------------------------------------ -# ATmega8515 -#------------------------------------------------------------ - -part - id = "m8515"; - desc = "ATMEGA8515"; - stk500_devcode = 0x63; - avr910_devcode = 0x3A; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - memory "eeprom" - size = 512; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 10; - blocksize = 128; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 8192; - page_size = 64; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 0 x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 0 x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 64; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 4; - read = "0 0 1 1 1 0 0 0 0 0 x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - - - - -#------------------------------------------------------------ -# ATmega8535 -#------------------------------------------------------------ - -part - id = "m8535"; - desc = "ATMEGA8535"; - stk500_devcode = 0x64; - pagel = 0xd7; - bs2 = 0xa0; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - memory "eeprom" - size = 512; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 x x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x04; - delay = 10; - blocksize = 128; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 8192; - page_size = 64; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 0 x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 0 x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 64; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 2000; - max_write_delay = 2000; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - - -#------------------------------------------------------------ -# ATtiny26 -#------------------------------------------------------------ - -part - id = "t26"; - desc = "ATTINY26"; - stk500_devcode = 0x21; - avr910_devcode = 0x5e; - pagel = 0xb3; - bs2 = 0xb2; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 0; - - memory "eeprom" - size = 128; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 x x x x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 x x x x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x04; - delay = 10; - blocksize = 64; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 2048; - page_size = 32; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " x x x x x x a9 a8", - " a7 a6 a5 a4 x x x x", - " x x x x x x x x"; - - mode = 0x21; - delay = 6; - blocksize = 16; - readsize = 256; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 x x x x x x x x", - "x x x x x x x x x x x x x x o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 1 1 1 i i", - "x x x x x x x x x x x x x x x x"; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x x x x i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x x x x o o o o o"; - ; - - memory "calibration" - size = 4; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 a1 a0 o o o o o o o o"; - ; - -; - - -#------------------------------------------------------------ -# ATmega48 -#------------------------------------------------------------ - -part - id = "m48"; - desc = "ATMEGA48"; - stk500_devcode = 0x59; -# avr910_devcode = 0x; - pagel = 0xd7; - bs2 = 0xc2; - chip_erase_delay = 45000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - memory "eeprom" - size = 256; - min_write_delay = 3600; - max_write_delay = 3600; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 x x x x x", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x41; - delay = 5; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 4096; - page_size = 64; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 64; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x x x x x x x x o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - - -#------------------------------------------------------------ -# ATmega88 -#------------------------------------------------------------ - -part - id = "m88"; - desc = "ATMEGA88"; - stk500_devcode = 0x73; -# avr910_devcode = 0x; - pagel = 0xd7; - bs2 = 0xc2; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - memory "eeprom" - size = 512; - min_write_delay = 3600; - max_write_delay = 3600; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x41; - delay = 5; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 8192; - page_size = 64; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 64; - readsize = 256; - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x x x x x x o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega168 -#------------------------------------------------------------ - -part - id = "m168"; - desc = "ATMEGA168"; - stk500_devcode = 0x86; - # avr910_devcode = 0x; - pagel = 0xd7; - bs2 = 0xc2; - chip_erase_delay = 9000; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - memory "eeprom" - size = 512; - min_write_delay = 3600; - max_write_delay = 3600; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = " 1 0 1 0 0 0 0 0", - " 0 0 0 x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " 0 0 0 x x x x a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - ; - - memory "flash" - paged = yes; - size = 16384; - page_size = 128; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 a12 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 128; - readsize = 256; - - ; - - memory "lfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "hfuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - ; - - memory "efuse" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x x x x x x o o o"; - - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x i i i"; - ; - - memory "lock" - size = 1; - min_write_delay = 4500; - max_write_delay = 4500; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; -; - -#------------------------------------------------------------ -# ATtiny2313 -#------------------------------------------------------------ - -part - id = "t2313"; - desc = "ATtiny2313"; - stk500_devcode = 0x23; -## avr910_devcode = ?; -## Try the AT90S2313 devcode: - avr910_devcode = 0x20; - pagel = 0xD4; - bs2 = 0xD6; - reset = io; - chip_erase_delay = 9000; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - memory "eeprom" - size = 128; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x41; - delay = 6; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 2048; - page_size = 32; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - -# The information in the data sheet of April/2004 is wrong, this works: - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - -# The information in the data sheet of April/2004 is wrong, this works: - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - -# The information in the data sheet of April/2004 is wrong, this works: - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; -# ATtiny2313 has Signature Bytes: 0x1E 0x91 0x0A. - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; -# The Tiny2313 has calibration data for both 4 MHz and 8 MHz. -# The information in the data sheet of April/2004 is wrong, this works: - - memory "calibration" - size = 2; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# AT90PWM2 -#------------------------------------------------------------ - -part - id = "pwm2"; - desc = "AT90PWM2"; - stk500_devcode = 0x65; -## avr910_devcode = ?; - pagel = 0xD8; - bs2 = 0xE2; - reset = io; - chip_erase_delay = 9000; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - memory "eeprom" - size = 512; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x41; - delay = 6; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 8192; - page_size = 64; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 64; - readsize = 256; - ; -# AT90PWM2 has Signature Bytes: 0x1E 0x93 0x81. - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# AT90PWM3 -#------------------------------------------------------------ - -# Completely identical to AT90PWM2 (including the signature!) - -part - id = "pwm3"; - desc = "AT90PWM3"; - stk500_devcode = 0x65; -## avr910_devcode = ?; - pagel = 0xD8; - bs2 = 0xE2; - reset = io; - chip_erase_delay = 9000; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - memory "eeprom" - size = 512; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x41; - delay = 6; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 8192; - page_size = 64; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 64; - readsize = 256; - ; -# AT90PWM2 has Signature Bytes: 0x1E 0x93 0x81. - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATtiny25 -#------------------------------------------------------------ - -part - id = "t25"; - desc = "ATtiny25"; -## no STK500 devcode in XML file, use the ATtiny45 one - stk500_devcode = 0x14; -## avr910_devcode = ?; -## Try the AT90S2313 devcode: - avr910_devcode = 0x20; - reset = io; - chip_erase_delay = 4500; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - memory "eeprom" - size = 128; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x41; - delay = 6; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 2048; - page_size = 32; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; -# ATtiny25 has Signature Bytes: 0x1E 0x91 0x08. - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATtiny45 -#------------------------------------------------------------ - -part - id = "t45"; - desc = "ATtiny45"; - stk500_devcode = 0x14; -## avr910_devcode = ?; -## Try the AT90S2313 devcode: - avr910_devcode = 0x20; - reset = io; - chip_erase_delay = 4500; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - memory "eeprom" - size = 256; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x41; - delay = 6; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 4096; - page_size = 64; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; -# ATtiny45 has Signature Bytes: 0x1E 0x92 0x08. - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATtiny85 -#------------------------------------------------------------ - -part - id = "t85"; - desc = "ATtiny85"; -## no STK500 devcode in XML file, use the ATtiny45 one - stk500_devcode = 0x14; -## avr910_devcode = ?; -## Try the AT90S2313 devcode: - avr910_devcode = 0x20; - reset = io; - chip_erase_delay = 4500; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - memory "eeprom" - size = 512; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x a8", - "a8 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x41; - delay = 6; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 8192; - page_size = 64; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; -# ATtiny85 has Signature Bytes: 0x1E 0x93 0x08. - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega640 -#------------------------------------------------------------ -# Almost same as ATmega1280, except for different memory sizes - -part - id = "m640"; - desc = "ATMEGA640"; -# Device ID 0x1e 0x96 0x08 - has_jtag = yes; -# stk500_devcode = 0xB2; -# avr910_devcode = 0x43; - chip_erase_delay = 9000; - pagel = 0xD7; - bs2 = 0xA0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - idr = 0x31; - spmcr = 0x57; - rampz = 0x3b; - allowfullpagebitstream = no; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 4096; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read = " 1 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x41; - delay = 10; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 65536; - page_size = 256; - num_pages = 256; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega1280 -#------------------------------------------------------------ - -part - id = "m1280"; - desc = "ATMEGA1280"; -# Device ID 0x1e 0x97 0x03 - has_jtag = yes; -# stk500_devcode = 0xB2; -# avr910_devcode = 0x43; - chip_erase_delay = 9000; - pagel = 0xD7; - bs2 = 0xA0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - idr = 0x31; - spmcr = 0x57; - rampz = 0x3b; - allowfullpagebitstream = no; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 4096; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read = " 1 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x41; - delay = 10; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 131072; - page_size = 256; - num_pages = 512; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATmega1281 -#------------------------------------------------------------ -# Identical to ATmega1280 - -part - id = "m1281"; - desc = "ATMEGA1281"; -# Device ID 0x1e 0x97 0x04 - has_jtag = yes; -# stk500_devcode = 0xB2; -# avr910_devcode = 0x43; - chip_erase_delay = 9000; - pagel = 0xD7; - bs2 = 0xA0; - reset = dedicated; - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - idr = 0x31; - spmcr = 0x57; - rampz = 0x3b; - allowfullpagebitstream = no; - - memory "eeprom" - paged = no; /* leave this "no" */ - page_size = 8; /* for parallel programming */ - size = 4096; - min_write_delay = 9000; - max_write_delay = 9000; - readback_p1 = 0x00; - readback_p2 = 0x00; - read = " 1 0 1 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - write = " 1 1 0 0 0 0 0 0", - " x x x x a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - mode = 0x41; - delay = 10; - blocksize = 8; - readsize = 256; - ; - - memory "flash" - paged = yes; - size = 131072; - page_size = 256; - num_pages = 512; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0x00; - readback_p2 = 0x00; - read_lo = " 0 0 1 0 0 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " x x x x x x x x", - " x a6 a5 a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - "a15 a14 a13 a12 a11 a10 a9 a8", - " a7 x x x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 256; - readsize = 256; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "lock" - size = 1; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x x x o o o o o o"; - - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x 1 1 i i i i i i"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 x x x x x x x x", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 x x x x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATtiny24 -#------------------------------------------------------------ - -part - id = "t24"; - desc = "ATtiny24"; -## no STK500 devcode in XML file, use the ATtiny45 one - stk500_devcode = 0x14; -## avr910_devcode = ?; -## Try the AT90S2313 devcode: - avr910_devcode = 0x20; - reset = io; - chip_erase_delay = 4500; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - memory "eeprom" - size = 128; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", - "x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x41; - delay = 6; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 2048; - page_size = 32; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x x a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 0 0 a9 a8", - " a7 a6 a5 a4 x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; -# ATtiny24 has Signature Bytes: 0x1E 0x91 0x0B. - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x x x x x x x i i"; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATtiny44 -#------------------------------------------------------------ - -part - id = "t44"; - desc = "ATtiny44"; -## no STK500 devcode in XML file, use the ATtiny45 one - stk500_devcode = 0x14; -## avr910_devcode = ?; -## Try the AT90S2313 devcode: - avr910_devcode = 0x20; - reset = io; - chip_erase_delay = 4500; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - memory "eeprom" - size = 256; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x x", - "a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x41; - delay = 6; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 4096; - page_size = 64; - num_pages = 64; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 0 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; -# ATtiny44 has Signature Bytes: 0x1E 0x92 0x07. - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x x x x x x x i i"; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 a0 o o o o o o o o"; - ; - ; - -#------------------------------------------------------------ -# ATtiny84 -#------------------------------------------------------------ - -part - id = "t84"; - desc = "ATtiny84"; -## no STK500 devcode in XML file, use the ATtiny45 one - stk500_devcode = 0x14; -## avr910_devcode = ?; -## Try the AT90S2313 devcode: - avr910_devcode = 0x20; - reset = io; - chip_erase_delay = 4500; - - pgm_enable = "1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1", - "x x x x x x x x x x x x x x x x"; - - chip_erase = "1 0 1 0 1 1 0 0 1 0 0 x x x x x", - "x x x x x x x x x x x x x x x x"; - - timeout = 200; - stabdelay = 100; - cmdexedelay = 25; - synchloops = 32; - bytedelay = 0; - pollindex = 3; - pollvalue = 0x53; - predelay = 1; - postdelay = 1; - pollmethod = 1; - - memory "eeprom" - size = 512; - min_write_delay = 4000; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read = "1 0 1 0 0 0 0 0 0 0 0 x x x x a8", - "a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o"; - - write = "1 1 0 0 0 0 0 0 0 0 0 x x x x a8", - "a8 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i"; - - mode = 0x41; - delay = 6; - blocksize = 4; - readsize = 256; - ; - memory "flash" - paged = yes; - size = 8192; - page_size = 64; - num_pages = 128; - min_write_delay = 4500; - max_write_delay = 4500; - readback_p1 = 0xff; - readback_p2 = 0xff; - read_lo = " 0 0 1 0 0 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - read_hi = " 0 0 1 0 1 0 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 a4 a3 a2 a1 a0", - " o o o o o o o o"; - - loadpage_lo = " 0 1 0 0 0 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - loadpage_hi = " 0 1 0 0 1 0 0 0", - " 0 0 0 x x x x x", - " x x x a4 a3 a2 a1 a0", - " i i i i i i i i"; - - writepage = " 0 1 0 0 1 1 0 0", - " 0 0 0 0 a11 a10 a9 a8", - " a7 a6 a5 x x x x x", - " x x x x x x x x"; - - mode = 0x41; - delay = 6; - blocksize = 32; - readsize = 256; - ; -# ATtiny84 has Signature Bytes: 0x1E 0x93 0x0C. - memory "signature" - size = 3; - read = "0 0 1 1 0 0 0 0 0 0 0 x x x x x", - "x x x x x x a1 a0 o o o o o o o o"; - ; - - memory "lock" - size = 1; - write = "1 0 1 0 1 1 0 0 1 1 1 x x x x x", - "x x x x x x x x x x x x x x i i"; - read = "0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0", - "0 0 0 0 0 0 0 0 o o o o o o o o"; - ; - - memory "lfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "hfuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0", - "x x x x x x x x i i i i i i i i"; - - read = "0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "efuse" - size = 1; - write = "1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0", - "x x x x x x x x x x x x x x x i"; - - read = "0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0", - "x x x x x x x x o o o o o o o o"; - ; - - memory "calibration" - size = 1; - read = "0 0 1 1 1 0 0 0 0 0 0 x x x x x", - "0 0 0 0 0 0 0 a0 o o o o o o o o"; - ; - ; - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/demo.c deleted file mode 100644 index aefb6302e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/demo.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * FreeModbus Libary: AVR Demo Application - * Copyright (C) 2006 Christian Walter - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- AVR includes -------------------------------------*/ -#include "avr/io.h" -#include "avr/interrupt.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define REG_INPUT_START 1000 -#define REG_INPUT_NREGS 4 - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegInputStart = REG_INPUT_START; -static USHORT usRegInputBuf[REG_INPUT_NREGS]; - -/* ----------------------- Start implementation -----------------------------*/ -int -main( void ) -{ - const UCHAR ucSlaveID[] = { 0xAA, 0xBB, 0xCC }; - eMBErrorCode eStatus; - - eStatus = eMBInit( MB_RTU, 0x0A, 0, 38400, MB_PAR_EVEN ); - - eStatus = eMBSetSlaveID( 0x34, TRUE, ucSlaveID, 3 ); - sei( ); - - /* Enable the Modbus Protocol Stack. */ - eStatus = eMBEnable( ); - - for( ;; ) - { - ( void )eMBPoll( ); - - /* Here we simply count the number of poll cycles. */ - usRegInputBuf[0]++; - } -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = - ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = - ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, - eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, - eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/demo_rtu.bat b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/demo_rtu.bat deleted file mode 100644 index 402b47572..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/demo_rtu.bat +++ /dev/null @@ -1 +0,0 @@ -..\..\tools\modpoll.exe -m rtu -a 10 -r 1000 -c 4 -t 3 -b 38400 -d 8 -p even COM1 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/demo_rtu.sh b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/demo_rtu.sh deleted file mode 100644 index 882c08764..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/demo_rtu.sh +++ /dev/null @@ -1 +0,0 @@ -../../tools/modpoll -m rtu -a 10 -r 1000 -c 4 -t 3 -b 38400 -d 8 -p even /dev/ttyS0 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/excoils.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/excoils.c deleted file mode 100644 index e3438efbe..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/excoils.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * FreeModbus Libary: AVR Demo Application - * Copyright (C) 2006 Christian Walter - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbutils.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define REG_COILS_START 1000 -#define REG_COILS_SIZE 16 - -/* ----------------------- Static variables ---------------------------------*/ -static unsigned char ucRegCoilsBuf[REG_COILS_SIZE / 8]; - -/* ----------------------- Start implementation -----------------------------*/ -int -main( void ) -{ - - /* Select either ASCII or RTU Mode. */ - ( void )eMBInit( MB_RTU, 0x0A, 0, 9600, MB_PAR_EVEN ); - - /* Enable the Modbus Protocol Stack. */ - ( void )eMBEnable( ); - for( ;; ) - { - /* Call the main polling loop of the Modbus protocol stack. */ - ( void )eMBPoll( ); - } -} - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, - eMBRegisterMode eMode ) -{ - eMBErrorCode eStatus = MB_ENOERR; - short iNCoils = ( short )usNCoils; - unsigned short usBitOffset; - - /* Check if we have registers mapped at this block. */ - if( ( usAddress >= REG_COILS_START ) && - ( usAddress + usNCoils <= REG_COILS_START + REG_COILS_SIZE ) ) - { - usBitOffset = ( unsigned short )( usAddress - REG_COILS_START ); - switch ( eMode ) - { - /* Read current values and pass to protocol stack. */ - case MB_REG_READ: - while( iNCoils > 0 ) - { - *pucRegBuffer++ = - xMBUtilGetBits( ucRegCoilsBuf, usBitOffset, - ( unsigned char )( iNCoils > - 8 ? 8 : - iNCoils ) ); - iNCoils -= 8; - usBitOffset += 8; - } - break; - - /* Update current register values. */ - case MB_REG_WRITE: - while( iNCoils > 0 ) - { - xMBUtilSetBits( ucRegCoilsBuf, usBitOffset, - ( unsigned char )( iNCoils > 8 ? 8 : iNCoils ), - *pucRegBuffer++ ); - iNCoils -= 8; - } - break; - } - - } - else - { - eStatus = MB_ENOREG; - } - return eStatus; -} - - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, - eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/port/mbcrc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/port/mbcrc.c deleted file mode 100644 index ce09811bc..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/port/mbcrc.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * FreeModbus Libary: ATMega168 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ - -#include - -/* ----------------------- Platform includes --------------------------------*/ -#include "port.h" - -static const PROGMEM UCHAR aucCRCHi[] = { - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, - 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, - 0x40, 0x01, 0xC0, - 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, - 0x81, 0x40, 0x01, - 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, - 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, - 0x00, 0xC1, 0x81, - 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, - 0x41, 0x01, 0xC0, - 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, - 0x80, 0x41, 0x01, - 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, - 0xC1, 0x81, 0x40, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, - 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, - 0x40, 0x01, 0xC0, - 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, - 0x81, 0x40, 0x01, - 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, - 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, - 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, - 0x40, 0x01, 0xC0, - 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, - 0x80, 0x41, 0x01, - 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, - 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, - 0x40 -}; - -static const PROGMEM UCHAR aucCRCLo[] = { - 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7, - 0x05, 0xC5, 0xC4, - 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E, 0x0A, 0xCA, 0xCB, - 0x0B, 0xC9, 0x09, - 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, - 0xDF, 0x1F, 0xDD, - 0x1D, 0x1C, 0xDC, 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, - 0x12, 0x13, 0xD3, - 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32, - 0x36, 0xF6, 0xF7, - 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, - 0xFE, 0xFA, 0x3A, - 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38, 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, - 0x2A, 0xEA, 0xEE, - 0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, - 0xE7, 0xE6, 0x26, - 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1, - 0x63, 0xA3, 0xA2, - 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4, 0x6C, 0xAC, 0xAD, - 0x6D, 0xAF, 0x6F, - 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, - 0xB9, 0x79, 0xBB, - 0x7B, 0x7A, 0xBA, 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, - 0x74, 0x75, 0xB5, - 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0, - 0x50, 0x90, 0x91, - 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, - 0x54, 0x9C, 0x5C, - 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E, 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, - 0x58, 0x98, 0x88, - 0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, - 0x4D, 0x4C, 0x8C, - 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83, - 0x41, 0x81, 0x80, - 0x40 -}; - -USHORT -usMBCRC16( UCHAR * pucFrame, USHORT usLen ) -{ - UCHAR ucCRCHi = 0xFF; - UCHAR ucCRCLo = 0xFF; - int iIndex; - - while( usLen-- ) - { - iIndex = ucCRCLo ^ *( pucFrame++ ); - ucCRCLo = ucCRCHi ^ pgm_read_byte( &aucCRCHi[iIndex] ); - ucCRCHi = pgm_read_byte( &aucCRCLo[iIndex] );; - } - return ucCRCHi << 8 | ucCRCLo; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/port/port.h deleted file mode 100644 index 665724d36..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/port/port.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * FreeModbus Libary: AVR Port - * Copyright (C) 2006 Christian Walter - * - Initial version + ATmega168 support - * Modfications Copyright (C) 2006 Tran Minh Hoang: - * - ATmega8, ATmega16, ATmega32 support - * - RS485 support for DS75176 - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -/* ----------------------- Platform includes --------------------------------*/ - -#include -#include - -/* ----------------------- Defines ------------------------------------------*/ -#define INLINE inline -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#define ENTER_CRITICAL_SECTION( ) cli() -#define EXIT_CRITICAL_SECTION( ) sei() - -#define assert( x ) - -typedef char BOOL; - -typedef unsigned char UCHAR; -typedef char CHAR; - -typedef unsigned short USHORT; -typedef short SHORT; - -typedef unsigned long ULONG; -typedef long LONG; - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -/* ----------------------- AVR platform specifics ---------------------------*/ - -#if defined (__AVR_ATmega168__) -#define UCSRB UCSR0B -#define TXEN TXEN0 -#define RXEN RXEN0 -#define RXCIE RXCIE0 -#define TXCIE TXCIE0 -#define UDRE UDRE0 -#define UBRR UBRR0 -#define UCSRC UCSR0C -#define UPM1 UPM01 -#define UPM0 UPM00 -#define UCSZ0 UCSZ00 -#define UCSZ1 UCSZ01 -#define UDR UDR0 -#define SIG_UART_TRANS SIG_USART_TRANS - -#elif defined (__AVR_ATmega169__) - -#define SIG_UART_TRANS SIG_USART_TRANS - -#elif defined (__AVR_ATmega8__) -#define UBRR UBRRL -#define TCCR1C TCCR1A /* dummy */ -#define TIMSK1 TIMSK -#define TIFR1 TIFR -#define SIG_USART_DATA SIG_UART_DATA -#define SIG_USART_RECV SIG_UART_RECV - -#elif defined (__AVR_ATmega16__) -#define UBRR UBRRL -#define TCCR1C TCCR1A /* dummy */ -#define TIMSK1 TIMSK -#define TIFR1 TIFR - -#elif defined (__AVR_ATmega32__) -#define UBRR UBRRL -#define TCCR1C TCCR1A /* dummy */ -#define TIMSK1 TIMSK -#define TIFR1 TIFR - -#elif defined (__AVR_ATmega128__) -#define UCSRB UCSR0B -#define UBRR UBRR0L -#define UDR UDR0 -#define TIMSK1 TIMSK -#define TIFR1 TIFR -#define SIG_UART_TRANS SIG_USART0_TRANS -#define SIG_USART_DATA SIG_USART0_DATA -#define SIG_USART_RECV SIG_USART0_RECV -#define UCSZ0 UCSZ00 -#define UCSZ1 UCSZ01 -#define UPM0 UPM00 -#define UPM1 UPM01 -#define UCSRC UCSR0C - -#endif - -/* ----------------------- RS485 specifics ----------------------------------*/ -#ifdef RTS_ENABLE - -#define RTS_PIN PB0 -#define RTS_DDR DDRB -#define RTS_PORT PORTB - -#define RTS_INIT \ - do { \ - RTS_DDR |= _BV( RTS_PIN ); \ - RTS_PORT &= ~( _BV( RTS_PIN ) ); \ - } while( 0 ); - -#define RTS_HIGH \ - do { \ - RTS_PORT |= _BV( RTS_PIN ); \ - } while( 0 ); - -#define RTS_LOW \ - do { \ - RTS_PORT &= ~( _BV( RTS_PIN ) ); \ - } while( 0 ); - -#endif - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/port/portevent.c deleted file mode 100644 index 5026d723e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/port/portevent.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * FreeModbus Libary: ATMega168 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static eMBEventType eQueuedEvent; -static BOOL xEventInQueue; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - xEventInQueue = FALSE; - return TRUE; -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - xEventInQueue = TRUE; - eQueuedEvent = eEvent; - return TRUE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - BOOL xEventHappened = FALSE; - - if( xEventInQueue ) - { - *eEvent = eQueuedEvent; - xEventInQueue = FALSE; - xEventHappened = TRUE; - } - return xEventHappened; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/port/portserial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/port/portserial.c deleted file mode 100644 index 0651f5849..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/port/portserial.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * FreeModbus Libary: ATMega168 Port - * Copyright (C) 2006 Christian Walter - * - Initial version and ATmega168 support - * Modfications Copyright (C) 2006 Tran Minh Hoang: - * - ATmega8, ATmega16, ATmega32 support - * - RS485 support for DS75176 - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#include -#include -#include - -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -#define UART_BAUD_RATE 9600 -#define UART_BAUD_CALC(UART_BAUD_RATE,F_OSC) \ - ( ( F_OSC ) / ( ( UART_BAUD_RATE ) * 16UL ) - 1 ) - -//#define UART_UCSRB UCSR0B - -void -vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable ) -{ -#ifdef RTS_ENABLE - UCSRB |= _BV( TXEN ) | _BV(TXCIE); -#else - UCSRB |= _BV( TXEN ); -#endif - - if( xRxEnable ) - { - UCSRB |= _BV( RXEN ) | _BV( RXCIE ); - } - else - { - UCSRB &= ~( _BV( RXEN ) | _BV( RXCIE ) ); - } - - if( xTxEnable ) - { - UCSRB |= _BV( TXEN ) | _BV( UDRE ); -#ifdef RTS_ENABLE - RTS_HIGH; -#endif - } - else - { - UCSRB &= ~( _BV( UDRE ) ); - } -} - -BOOL -xMBPortSerialInit( UCHAR ucPORT, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity ) -{ - UCHAR ucUCSRC = 0; - - /* prevent compiler warning. */ - (void)ucPORT; - - UBRR = UART_BAUD_CALC( ulBaudRate, F_CPU ); - - switch ( eParity ) - { - case MB_PAR_EVEN: - ucUCSRC |= _BV( UPM1 ); - break; - case MB_PAR_ODD: - ucUCSRC |= _BV( UPM1 ) | _BV( UPM0 ); - break; - case MB_PAR_NONE: - break; - } - - switch ( ucDataBits ) - { - case 8: - ucUCSRC |= _BV( UCSZ0 ) | _BV( UCSZ1 ); - break; - case 7: - ucUCSRC |= _BV( UCSZ1 ); - break; - } - -#if defined (__AVR_ATmega168__) - UCSRC |= ucUCSRC; -#elif defined (__AVR_ATmega169__) - UCSRC |= ucUCSRC; -#elif defined (__AVR_ATmega8__) - UCSRC = _BV( URSEL ) | ucUCSRC; -#elif defined (__AVR_ATmega16__) - UCSRC = _BV( URSEL ) | ucUCSRC; -#elif defined (__AVR_ATmega32__) - UCSRC = _BV( URSEL ) | ucUCSRC; -#elif defined (__AVR_ATmega128__) - UCSRC |= ucUCSRC; -#endif - - vMBPortSerialEnable( FALSE, FALSE ); - -#ifdef RTS_ENABLE - RTS_INIT; -#endif - return TRUE; -} - -BOOL -xMBPortSerialPutByte( CHAR ucByte ) -{ - UDR = ucByte; - return TRUE; -} - -BOOL -xMBPortSerialGetByte( CHAR * pucByte ) -{ - *pucByte = UDR; - return TRUE; -} - -SIGNAL( SIG_USART_DATA ) -{ - pxMBFrameCBTransmitterEmpty( ); -} - -SIGNAL( SIG_USART_RECV ) -{ - pxMBFrameCBByteReceived( ); -} - -#ifdef RTS_ENABLE -SIGNAL( SIG_UART_TRANS ) -{ - RTS_LOW; -} -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/port/porttimer.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/port/porttimer.c deleted file mode 100644 index 2a25cd710..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/AVR/port/porttimer.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * FreeModbus Libary: ATMega168 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- AVR includes -------------------------------------*/ -#include -#include -#include - -/* ----------------------- Platform includes --------------------------------*/ -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_TIMER_PRESCALER ( 1024UL ) -#define MB_TIMER_TICKS ( F_CPU / MB_TIMER_PRESCALER ) -#define MB_50US_TICKS ( 20000UL ) - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usTimerOCRADelta; -static USHORT usTimerOCRBDelta; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortTimersInit( USHORT usTim1Timerout50us ) -{ - /* Calculate overflow counter an OCR values for Timer1. */ - usTimerOCRADelta = - ( MB_TIMER_TICKS * usTim1Timerout50us ) / ( MB_50US_TICKS ); - - TCCR1A = 0x00; - TCCR1B = 0x00; - TCCR1C = 0x00; - - vMBPortTimersDisable( ); - - return TRUE; -} - - -inline void -vMBPortTimersEnable( ) -{ - TCNT1 = 0x0000; - if( usTimerOCRADelta > 0 ) - { - TIMSK1 |= _BV( OCIE1A ); - OCR1A = usTimerOCRADelta; - } - - TCCR1B |= _BV( CS12 ) | _BV( CS10 ); -} - -inline void -vMBPortTimersDisable( ) -{ - /* Disable the timer. */ - TCCR1B &= ~( _BV( CS12 ) | _BV( CS10 ) ); - /* Disable the output compare interrupts for channel A/B. */ - TIMSK1 &= ~( _BV( OCIE1A ) ); - /* Clear output compare flags for channel A/B. */ - TIFR1 |= _BV( OCF1A ) ; -} - -SIGNAL( SIG_OUTPUT_COMPARE1A ) -{ - ( void )pxMBPortCBTimerExpired( ); -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/Makefile b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/Makefile deleted file mode 100644 index f7ea32b06..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/Makefile +++ /dev/null @@ -1,67 +0,0 @@ -############################################################################### -# Makefile for the BARE project -############################################################################### - -## General Flags -PROJECT = demo -TARGET = demo - -CC=gcc -OBJCOPY=/cygdrive/c/WinAVR/bin/avr-objcopy - -## Options common to compile, link and assembly rules -COMMON = - -## Compile options common for all C compilation units. -CFLAGS = $(COMMON) \ - -Iport -I. \ - -I../../modbus/rtu -I../../modbus/ascii -I../../modbus/include -CFLAGS += -Wall -gstabs -Os -Wall -Wstrict-prototypes - -CFLAGS += -Wp,-M,-MP,-MT,$(*F).o,-MF,dep/$(@F).d - -## Assembly specific flags -ASMFLAGS = $(COMMON) -ASMFLAGS += -x assembler-with-cpp -Wa,-gstabs - -## Linker flags -LDFLAGS = $(COMMON) -LDFLAGS += -Wl,-Map=$(TARGET).map,--cref - -## Objects that must be built in order to link -OBJECTS = demo.o -MBPORTOBJECTS = port/portserial.o \ - port/portevent.o \ - port/porttimer.o -MBOBJECTS = ../../modbus/mb.o \ - ../../modbus/rtu/mbrtu.o \ - ../../modbus/rtu/mbcrc.o \ - ../../modbus/ascii/mbascii.o \ - ../../modbus/functions/mbfunccoils.o \ - ../../modbus/functions/mbfuncdiag.o \ - ../../modbus/functions/mbfuncholding.o \ - ../../modbus/functions/mbfuncinput.o \ - ../../modbus/functions/mbfuncother.o \ - ../../modbus/functions/mbfuncdisc.o \ - ../../modbus/functions/mbutils.o - - -## Build -all: $(TARGET).elf - -## Compile -demo.o: demo.c - $(CC) $(INCLUDES) $(CFLAGS) -c $< - -##Link -$(TARGET).elf: $(OBJECTS) $(MBOBJECTS) $(MBPORTOBJECTS) - $(CC) $(LDFLAGS) $(OBJECTS) $(MBPORTOBJECTS) $(MBOBJECTS) $(LIBDIRS) $(LIBS) -o $(TARGET).elf - -## Clean target -.PHONY: clean -clean: - -rm -rf $(OBJECTS) $(MBOBJECTS) $(MBPORTOBJECTS) $(TARGET).elf $(TARGET).map - -## Other dependencies --include $(shell mkdir dep 2>/dev/null) $(wildcard dep/*) - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/demo.c deleted file mode 100644 index 2ae19a65a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/demo.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * FreeModbus Libary: BARE Demo Application - * Copyright (C) 2006 Christian Walter - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define REG_INPUT_START 1000 -#define REG_INPUT_NREGS 4 - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegInputStart = REG_INPUT_START; -static USHORT usRegInputBuf[REG_INPUT_NREGS]; - -/* ----------------------- Start implementation -----------------------------*/ -int -main( void ) -{ - eMBErrorCode eStatus; - - eStatus = eMBInit( MB_RTU, 0x0A, 0, 38400, MB_PAR_EVEN ); - - /* Enable the Modbus Protocol Stack. */ - eStatus = eMBEnable( ); - - for( ;; ) - { - ( void )eMBPoll( ); - - /* Here we simply count the number of poll cycles. */ - usRegInputBuf[0]++; - } -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = - ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = - ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, - eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, - eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/port/port.h deleted file mode 100644 index c2a0f7d4b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/port/port.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * FreeModbus Libary: BARE Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -#include -#include - -#define INLINE inline -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#define ENTER_CRITICAL_SECTION( ) -#define EXIT_CRITICAL_SECTION( ) - -typedef uint8_t BOOL; - -typedef unsigned char UCHAR; -typedef char CHAR; - -typedef uint16_t USHORT; -typedef int16_t SHORT; - -typedef uint32_t ULONG; -typedef int32_t LONG; - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/port/portevent.c deleted file mode 100644 index e700a471c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/port/portevent.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * FreeModbus Libary: BARE Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static eMBEventType eQueuedEvent; -static BOOL xEventInQueue; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - xEventInQueue = FALSE; - return TRUE; -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - xEventInQueue = TRUE; - eQueuedEvent = eEvent; - return TRUE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - BOOL xEventHappened = FALSE; - - if( xEventInQueue ) - { - *eEvent = eQueuedEvent; - xEventInQueue = FALSE; - xEventHappened = TRUE; - } - return xEventHappened; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/port/portserial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/port/portserial.c deleted file mode 100644 index 45d17fa3a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/port/portserial.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * FreeModbus Libary: BARE Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- static functions ---------------------------------*/ -static void prvvUARTTxReadyISR( void ); -static void prvvUARTRxISR( void ); - -/* ----------------------- Start implementation -----------------------------*/ -void -vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable ) -{ - /* If xRXEnable enable serial receive interrupts. If xTxENable enable - * transmitter empty interrupts. - */ -} - -BOOL -xMBPortSerialInit( UCHAR ucPORT, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity ) -{ - return FALSE; -} - -BOOL -xMBPortSerialPutByte( CHAR ucByte ) -{ - /* Put a byte in the UARTs transmit buffer. This function is called - * by the protocol stack if pxMBFrameCBTransmitterEmpty( ) has been - * called. */ - return TRUE; -} - -BOOL -xMBPortSerialGetByte( CHAR * pucByte ) -{ - /* Return the byte in the UARTs receive buffer. This function is called - * by the protocol stack after pxMBFrameCBByteReceived( ) has been called. - */ - return TRUE; -} - -/* Create an interrupt handler for the transmit buffer empty interrupt - * (or an equivalent) for your target processor. This function should then - * call pxMBFrameCBTransmitterEmpty( ) which tells the protocol stack that - * a new character can be sent. The protocol stack will then call - * xMBPortSerialPutByte( ) to send the character. - */ -static void prvvUARTTxReadyISR( void ) -{ - pxMBFrameCBTransmitterEmpty( ); -} - -/* Create an interrupt handler for the receive interrupt for your target - * processor. This function should then call pxMBFrameCBByteReceived( ). The - * protocol stack will then call xMBPortSerialGetByte( ) to retrieve the - * character. - */ -static void prvvUARTRxISR( void ) -{ - pxMBFrameCBByteReceived( ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/port/porttimer.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/port/porttimer.c deleted file mode 100644 index e130ff831..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/BARE/port/porttimer.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * FreeModbus Libary: BARE Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Platform includes --------------------------------*/ -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- static functions ---------------------------------*/ -static void prvvTIMERExpiredISR( void ); - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortTimersInit( USHORT usTim1Timerout50us ) -{ - return FALSE; -} - - -inline void -vMBPortTimersEnable( ) -{ - /* Enable the timer with the timeout passed to xMBPortTimersInit( ) */ -} - -inline void -vMBPortTimersDisable( ) -{ - /* Disable any pending timers. */ -} - -/* Create an ISR which is called whenever the timer has expired. This function - * must then call pxMBPortCBTimerExpired( ) to notify the protocol stack that - * the timer has expired. - */ -static void prvvTIMERExpiredISR( void ) -{ - ( void )pxMBPortCBTimerExpired( ); -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/HCS08/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/HCS08/demo.c deleted file mode 100644 index b955112a7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/HCS08/demo.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * FreeModbus Libary: HCS08 Port - * Copyright (C) 2006 Christian Walter - * Copyright (C) 2008 Trond Melen - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define REG_INPUT_START 1000 -#define REG_INPUT_NREGS 4 - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegInputStart = REG_INPUT_START; -static USHORT usRegInputBuf[REG_INPUT_NREGS]; - -UCHAR CCR_reg; // SaveStatusReg stores the Condition Code Register here - -/* ----------------------- Start implementation -----------------------------*/ - -void -main( void ) -{ - eMBErrorCode eStatus; - - /* Use external 32.768 Hz crystal to generate 4.194.304 Hz bus clock */ - ICGC1 = 0x38; // ??=0,RANGE=0,REFS=1,CLKS=1:1,OSCSTEN=0,??=0:0 - while( ICGS2_DCOS == 0 ); - -#if 0 - /* Test code for porting - */ -#if 1 - /* Timer test - * Comment out call to pxMBPortCBTimerExpired() in prvvTIMERExpiredISR when testing the timer - */ - - /* Disable the COP watchdog */ - SOPT = 0x53; // COPE=0,COPT=1,STOPE=0,??=1:0:0,BKGDPE=1,??=1 - - ( void )xMBPortTimersInit( 20000 ); - - EnableInterrupts; - for( ;; ) - { - vMBPortTimersEnable( ); - _Wait; // wait for an interrupt - - /* toggle LED1 */ - PTFD_PTFD0 = !PTFD_PTFD0; - PTFDD_PTFDD0 = 1; - } - -#else - /* Receiver test - * Comment out call to pxMBFrameCBByteReceived() in prvvUARTRxISR() when testing the receiver - */ - - /* Disable the COP watchdog */ - SOPT = 0x53; // COPE=0,COPT=1,STOPE=0,??=1:0:0,BKGDPE=1,??=1 - - /* Enable the receiver. */ - assert( xMBPortSerialInit( 0, 9600, 8, MB_PAR_NONE ) ); - - EnableInterrupts; - for( ;; ) - { - UCHAR ucByte; - - vMBPortSerialEnable( TRUE, FALSE ); - _Wait; // wait for an interrupt - assert( xMBPortSerialGetByte( &ucByte ) ); - - /* toggle LED1 */ - PTFD_PTFD0 = !PTFD_PTFD0; - PTFDD_PTFDD0 = 1; - - /* Transmitter test - * Comment out call to pxMBFrameCBTransmitterEmpty() in prvvUARTTxReadyISR() when testing the transmitter - */ -#if 0 - vMBPortSerialEnable( FALSE, TRUE ); - assert( xMBPortSerialPutByte( ucByte ) ); - _Wait; // wait for an interrupt - - /* toggle LED1 */ - PTFD_PTFD0 = !PTFD_PTFD0; -#endif // Transmitter test - } -#endif // Receiver test - -#else - /* Demo - * NOTE: Make sure the callbacks in the three ISPs have been restored after above testing - */ - - /* Initialization */ - eStatus = eMBInit( MB_RTU, 0x0A, 0, 38400, MB_PAR_EVEN ); -// eStatus = eMBInit( MB_ASCII, 0x0A, 0, 38400, MB_PAR_EVEN ); - - /* Enable the Modbus Protocol Stack. */ - eStatus = eMBEnable( ); - - /* Start polling */ - EnableInterrupts; - for( ;; ) - { - /* Poll for Modbus events */ - ( void )eMBPoll( ); - - /* Count the number of polls */ - usRegInputBuf[0]++; - - /* Count the number of timer overflows */ - if( TPM1SC_TOF ) - { - TPM1SC_TOF = 0; - ENTER_CRITICAL_SECTION( ); - if( ++usRegInputBuf[1] == 0 ) // Happens every 2 seconds - usRegInputBuf[2]++; // Happens every 36.4 hours - EXIT_CRITICAL_SECTION( ); - } - - /* Keep the COP watchdog happy */ - __RESET_WATCHDOG( ); - } -#endif // Test code when porting -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/HCS08/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/HCS08/port/port.h deleted file mode 100644 index 047dae168..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/HCS08/port/port.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * FreeModbus Libary: HCS08 Port - * Copyright (C) 2006 Christian Walter - * Copyright (C) 2008 Trond Melen - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -#include - -/* The include file "derivative.h" is automatically generated by Code Warrior */ -#include "derivative.h" - -/* Tne include fila inttypes.h is not available for HCS08, so we use our own definitions instead */ -//#include -typedef char int8_t; -typedef unsigned char uint8_t; -typedef int int16_t; -typedef unsigned int uint16_t; -typedef long int32_t; -typedef unsigned long uint32_t; - - -/* Michael Barrs verification code */ -#pragma MESSAGE ERROR DISABLE C1135 -static union -{ - char int8_t_incorrect[sizeof( int8_t ) == 1]; - char uint8_t_incorrect[sizeof( uint8_t ) == 1]; - char int16_t_incorrect[sizeof( int16_t ) == 2]; - char uint16_t_incorrect[sizeof( uint16_t ) == 2]; - char int32_t_incorrect[sizeof( int32_t ) == 4]; - char uint32_t_incorrect[sizeof( uint32_t ) == 4]; -}; - -#define INLINE -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } -#define memcpy (void) memcpy // gets wid of a warning in mbfuncother.c - -/* Next 2 lines copied from code generated by Processor Expert */ -#define SaveStatusReg() { asm PSHA; asm TPA; asm SEI; asm STA CCR_reg; asm PULA; } /* This macro is used by Processor Expert. It saves CCR register and disable global interrupts. */ -#define RestoreStatusReg() { asm PSHA; asm LDA CCR_reg; asm TAP; asm PULA; } /* This macro is used by Processor Expert. It restores CCR register saved in SaveStatusReg(). */ - -#define ENTER_CRITICAL_SECTION( ) DisableInterrupts; -#define EXIT_CRITICAL_SECTION( ) EnableInterrupts; - -typedef uint8_t BOOL; -typedef unsigned char UCHAR; -typedef char CHAR; -typedef uint16_t USHORT; -typedef int16_t SHORT; -typedef uint32_t ULONG; -typedef int32_t LONG; - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -/* SaveStatusReg() stores the Condition Code Register here */ -extern UCHAR CCR_reg; - -/* The bus clock is used for computing timer and baud rate register values */ -#define BM_BUS_CLOCK 4194304 // Hz - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/HCS08/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/HCS08/port/portevent.c deleted file mode 100644 index e700a471c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/HCS08/port/portevent.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * FreeModbus Libary: BARE Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static eMBEventType eQueuedEvent; -static BOOL xEventInQueue; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - xEventInQueue = FALSE; - return TRUE; -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - xEventInQueue = TRUE; - eQueuedEvent = eEvent; - return TRUE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - BOOL xEventHappened = FALSE; - - if( xEventInQueue ) - { - *eEvent = eQueuedEvent; - xEventInQueue = FALSE; - xEventHappened = TRUE; - } - return xEventHappened; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/HCS08/port/portserial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/HCS08/port/portserial.c deleted file mode 100644 index 7e29348a5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/HCS08/port/portserial.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * FreeModbus Libary: HCS08 Port - * Copyright (C) 2006 Christian Walter - * Copyright (C) 2008 Trond Melen - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- static functions ---------------------------------*/ -static void prvvUARTTxReadyISR( void ); -static void prvvUARTRxISR( void ); - -/* ----------------------- Start implementation -----------------------------*/ - -void -vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable ) -{ - /* If xRXEnable enable serial receive interrupts. - * If xTxENable enable transmitter empty interrupts. - */ - - /* Compute control register value */ - SCI1C2 = 0x0C; // TIE=0,TCIE=0,RIE=0,ILIE=0,TE=1,RE=1,RWU=0,SBK=0 - - /* Enable the requested interrupts */ - if( xRxEnable ) - SCI1C2_RIE = 1; - if( xTxEnable ) - SCI1C2_TIE = 1; -} - -BOOL -xMBPortSerialInit( UCHAR ucPORT, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity ) -{ - /* Compute baud rate generator divider */ - SCI1BD = ( USHORT ) ( ( ( BM_BUS_CLOCK + 16 / 2 ) / 16 + ulBaudRate / 2 ) / ulBaudRate ); - - /* Configure the serial port */ -// SCI1C1 = 0x00; // LOOPS=0,SCISWAI=0,RSRC=0,M=0,ILT=0,PE=0,PT=0 - if( ucDataBits == 8 && eParity != MB_PAR_NONE ) - SCI1C1_M = 1; - if( eParity != MB_PAR_NONE ) - SCI1C1_PE = 1; - if( eParity == MB_PAR_ODD || ( eParity == MB_PAR_NONE && ucDataBits == 7 ) ) - SCI1C1_PT = 1; - - return TRUE; -} - -BOOL -xMBPortSerialPutByte( CHAR ucByte ) -{ - /* Put a byte in the UARTs transmit buffer. This function is called - * by the protocol stack if pxMBFrameCBTransmitterEmpty( ) has been - * called. */ - while( SCI1S1_TDRE == FALSE ); - SCI1D = ucByte; - SCI1C2_TIE = TRUE; - - return TRUE; -} - -BOOL -xMBPortSerialGetByte( CHAR * pucByte ) -{ - /* Return the byte in the UARTs receive buffer. This function is called - * by the protocol stack after pxMBFrameCBByteReceived( ) has been called. - */ - BOOL parityOK; - - while( SCI1S1_RDRF == FALSE ); - parityOK = !SCI1S1_PF; - if( SCI1C1_M ) - *pucByte = SCI1C3; // for coherent 9 bit reads of the receiver buffer - *pucByte = SCI1D; - if( !SCI1C1_M ) - if( SCI1C1_PE || ( !SCI1C1_PE && SCI1C1_PT ) ) - *pucByte &= 0x7F; - SCI1C2_RIE = TRUE; - - return parityOK; // return TRUE if Parity Error Flag was not set -} - -/* Create an interrupt handler for the transmit buffer empty interrupt - * (or an equivalent) for your target processor. This function should then - * call pxMBFrameCBTransmitterEmpty( ) which tells the protocol stack that - * a new character can be sent. The protocol stack will then call - * xMBPortSerialPutByte( ) to send the character. - */ -interrupt VectorNumber_Vsci1tx void -prvvUARTTxReadyISR( void ) -{ - SCI1C2_TIE = FALSE; - ( void )pxMBFrameCBTransmitterEmpty( ); -} - -/* Create an interrupt handler for the receive interrupt for your target - * processor. This function should then call pxMBFrameCBByteReceived( ). The - * protocol stack will then call xMBPortSerialGetByte( ) to retrieve the - * character. - */ -interrupt VectorNumber_Vsci1rx void -prvvUARTRxISR( void ) -{ - SCI1C2_RIE = FALSE; - ( void )pxMBFrameCBByteReceived( ); -} - - -/* assert( FALSE ) generate software interrupts so they should be handled somehow - * This implementation will generate padding charactres until the stack overflows - */ -interrupt VectorNumber_Vswi void -prvvAssertISR( void ) -{ - ( void )xMBPortSerialPutByte( 0x00 ); - SCI1C2_TIE = FALSE; - EnableInterrupts; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/HCS08/port/porttimer.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/HCS08/port/porttimer.c deleted file mode 100644 index 7d1fcab8a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/HCS08/port/porttimer.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * FreeModbus Libary: HCS08 Port - * Copyright (C) 2006 Christian Walter - * Copyright (C) 2008 Trond Melen - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Platform includes --------------------------------*/ -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Persistent variable ------------------------------*/ -static USHORT usDelta; - -/* ----------------------- Start implementation -----------------------------*/ - -USHORT -usMBMulDiv( USHORT a, USHORT b, USHORT c ) -{ - ULONG x; - - x = a; - x *= b; - x /= c; - - return ( USHORT ) x; -} - - -/* Initialize Timer 1 as free running, and Channel 0 as output compare (with no pin) - */ -BOOL -xMBPortTimersInit( USHORT usTim1Timerout50us ) -{ - /* We assume 4194304 Hz bus clock and let the timer run at 1/128 of this frequency, ie. 32768 Hz */ - ( void )assert( BM_BUS_CLOCK == 4194304 ); - TPM1SC = 0x0F; // TOF=0,TOIE=0,CPWMS=0,CLKS=0:1,PS=1:1:1 - TPM1C0SC = 0x10; // CH0F=0,CH0IE=0,MS0=0:1,ELS0=0:0;??=0:0 - - /* Compute numer of timer tics corresponding to the given timeout periode */ - usDelta = usMBMulDiv( usTim1Timerout50us, 1024, 625 ); - - return TRUE; -} - -/* Set the output compare register value and enable timer interrupt - */ -INLINE void -vMBPortTimersEnable( ) -{ - /* Enable the timer with the timeout passed to xMBPortTimersInit( ) */ - SaveStatusReg( ); - TPM1C0V = TPM1CNT + usDelta; - RestoreStatusReg( ); - if( TPM1C0SC_CH0F ) - TPM1C0SC_CH0F = FALSE; - TPM1C0SC_CH0IE = TRUE; -} - -/* Disable timer interrupts - */ -INLINE void -vMBPortTimersDisable( ) -{ - TPM1C0SC_CH0IE = FALSE; -} - -/* Handle the interrupt and disable further timeouts - */ -interrupt VectorNumber_Vtpm1ch0 void -prvvTIMERExpiredISR( void ) -{ - TPM1C0SC_CH0IE = FALSE; - ( void )pxMBPortCBTimerExpired( ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/Makefile b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/Makefile deleted file mode 100644 index 20a61de22..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/Makefile +++ /dev/null @@ -1,80 +0,0 @@ -# -# FreeModbus Linux PORT - Makefile -# -# Copyright (c) 2006 Christian Walter, © s::can, Vienna 2006. -# -# --------------------------------------------------------------------------- - -# --------------------------------------------------------------------------- -# platform dependencies -# --------------------------------------------------------------------------- -ifneq ($(strip $(shell gcc -v 2>&1 |grep "cygwin")),) - CYGWIN_BUILD = YES -endif -CC = gcc -CXX = g++ -OBJCOPY = objcopy -INSIGHT = /opt/insight-x86/bin/insight - -# --------------------------------------------------------------------------- -# project specifics -# --------------------------------------------------------------------------- -CFLAGS = -MD -g3 -Wall -Iport -I../../modbus/rtu \ - -I../../modbus/ascii -I../../modbus/include -LDFLAGS = -ifeq ($(CYGWIN_BUILD),YES) -else -LDFLAGS += -lpthread -CFLAGS += -pthread -endif - -TGT = demo -OTHER_CSRC = -OTHER_ASRC = -CSRC = demo.c port/portserial.c port/portother.c \ - port/portevent.c port/porttimer.c \ - ../../modbus/mb.c \ - ../../modbus/rtu/mbrtu.c ../../modbus/rtu/mbcrc.c \ - ../../modbus/ascii/mbascii.c \ - ../../modbus/functions/mbfunccoils.c \ - ../../modbus/functions/mbfuncdiag.c \ - ../../modbus/functions/mbfuncholding.c \ - ../../modbus/functions/mbfuncinput.c \ - ../../modbus/functions/mbfuncother.c \ - ../../modbus/functions/mbfuncdisc.c \ - ../../modbus/functions/mbutils.c -ASRC = -OBJS = $(CSRC:.c=.o) $(ASRC:.S=.o) -NOLINK_OBJS = $(OTHER_CSRC:.c=.o) $(OTHER_ASRC:.S=.o) -DEPS = $(OBJS:.o=.d) $(NOLINK_OBJS:.o=.d) -BIN = $(TGT) - -.PHONY: clean all - -all: $(BIN) - -debug: - $(INSIGHT) --se=$(TGT) - -$(BIN): $(OBJS) $(NOLINK_OBJS) - $(CC) $(LDFLAGS) $(OBJS) $(LDLIBS) -o $@ - -clean: - rm -f $(DEPS) - rm -f $(OBJS) $(NOLINK_OBJS) - rm -f $(BIN) - -# --------------------------------------------------------------------------- -# rules for code generation -# --------------------------------------------------------------------------- -%.o: %.c - $(CC) $(CFLAGS) -o $@ -c $< - -%.o: %.S - $(CC) $(ASFLAGS) -o $@ -c $< - -# --------------------------------------------------------------------------- -# # compiler generated dependencies -# --------------------------------------------------------------------------- --include $(LWOS_DEPS) $(PORT_DEPS) $(APPL_DEPS) - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/README.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/README.txt deleted file mode 100644 index 2fbd17c71..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/README.txt +++ /dev/null @@ -1,45 +0,0 @@ - - FREEMODBUS 0.8 LINUX EXAMPLE - ============================ - -REQUIREMENTS -============ - -This example contains a simple demo program for a Linux host. The default -demo opens the serial port on /dev/ttyS0 and waits for commands from an -Modbus master. Demo versions of Modbus Masters can be found in [1] and [2]. - -INSTALLATION -============ - -The program can be built by calling 'make flash'. This demo application -was tested on Redhat Enterprise Linux 4 (RHEL4) but should work on any -recent distribution. - -TESTING -======= - -Install a Null-Modem cable between /dev/ttyS0 and /dev/ttyS1. Next start -the Modbus Sample Application and test if the input registers starting at -protocol address 1000 can be read. There are four registers value available -and the output should look like: - -Polling slave (Ctrl-C to stop) ... -[1000]: 6474 -[1001]: 0 -[1002]: 0 -[1003]: 0 -Polling slave (Ctrl-C to stop) ... -[1000]: -8831 -[1001]: 0 -[1002]: 0 -[1003]: 0 -Polling slave (Ctrl-C to stop) ... - -The simple testing utility used in the 'demo.sh' script can be found at [3]. - -[1] WinTech ModScan32: http://www.win-tech.com/html/modscan32.htm -[2] Modus Poll: http://www.modbustools.com/modbus_poll.asp -[3] FieldTalk Modpoll: http://www.focus-sw.com/fieldtalk/modpoll.html - -Version: $Id: README.txt,v 1.1 2006/08/01 20:58:49 wolti Exp $ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/demo.c deleted file mode 100644 index ae47c0127..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/demo.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - * FreeModbus Libary: Linux Demo Application - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Standard includes --------------------------------*/ -#include -#include -#include -#include -#include -#include -#include - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define PROG "freemodbus" - -#define REG_INPUT_START 1000 -#define REG_INPUT_NREGS 4 -#define REG_HOLDING_START 2000 -#define REG_HOLDING_NREGS 130 - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegInputStart = REG_INPUT_START; -static USHORT usRegInputBuf[REG_INPUT_NREGS]; -static USHORT usRegHoldingStart = REG_HOLDING_START; -static USHORT usRegHoldingBuf[REG_HOLDING_NREGS]; - -static enum ThreadState -{ - STOPPED, - RUNNING, - SHUTDOWN -} ePollThreadState; - -static pthread_mutex_t xLock = PTHREAD_MUTEX_INITIALIZER; -static BOOL bDoExit; - -/* ----------------------- Static functions ---------------------------------*/ -static BOOL bCreatePollingThread( void ); -static enum ThreadState eGetPollingThreadState( void ); -static void vSetPollingThreadState( enum ThreadState eNewState ); -static void *pvPollingThread( void *pvParameter ); - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -bSetSignal( int iSignalNr, void ( *pSigHandler ) ( int ) ) -{ - BOOL bResult; - struct sigaction xNewSig, xOldSig; - - xNewSig.sa_handler = pSigHandler; - sigemptyset( &xNewSig.sa_mask ); - xNewSig.sa_flags = 0; - if( sigaction( iSignalNr, &xNewSig, &xOldSig ) != 0 ) - { - bResult = FALSE; - } - else - { - bResult = TRUE; - } - return bResult; -} - -void -vSigShutdown( int xSigNr ) -{ - switch ( xSigNr ) - { - case SIGQUIT: - case SIGINT: - case SIGTERM: - vSetPollingThreadState( SHUTDOWN ); - bDoExit = TRUE; - } -} - -int -main( int argc, char *argv[] ) -{ - int iExitCode; - CHAR cCh; - - const UCHAR ucSlaveID[] = { 0xAA, 0xBB, 0xCC }; - if( !bSetSignal( SIGQUIT, vSigShutdown ) || - !bSetSignal( SIGINT, vSigShutdown ) || !bSetSignal( SIGTERM, vSigShutdown ) ) - { - fprintf( stderr, "%s: can't install signal handlers: %s!\n", PROG, strerror( errno ) ); - iExitCode = EXIT_FAILURE; - } - else if( eMBInit( MB_RTU, 0x0A, 0, 38400, MB_PAR_EVEN ) != MB_ENOERR ) - { - fprintf( stderr, "%s: can't initialize modbus stack!\n", PROG ); - iExitCode = EXIT_FAILURE; - } - else if( eMBSetSlaveID( 0x34, TRUE, ucSlaveID, 3 ) != MB_ENOERR ) - { - fprintf( stderr, "%s: can't set slave id!\n", PROG ); - iExitCode = EXIT_FAILURE; - } - else - { - vSetPollingThreadState( STOPPED ); - - /* CLI interface. */ - printf( "Type 'q' for quit or 'h' for help!\n" ); - bDoExit = FALSE; - do - { - printf( "> " ); - cCh = getchar( ); - - switch ( cCh ) - { - case 'q': - bDoExit = TRUE; - break; - case 'd': - vSetPollingThreadState( SHUTDOWN ); - break; - case 'e': - if( bCreatePollingThread( ) != TRUE ) - { - printf( "Can't start protocol stack! Already running?\n" ); - } - break; - case 's': - switch ( eGetPollingThreadState( ) ) - { - case RUNNING: - printf( "Protocol stack is running.\n" ); - break; - case STOPPED: - printf( "Protocol stack is stopped.\n" ); - break; - case SHUTDOWN: - printf( "Protocol stack is shuting down.\n" ); - break; - } - break; - case 'h': - printf( "FreeModbus demo application help:\n" ); - printf( " 'd' ... disable protocol stack.\n" ); - printf( " 'e' ... enabled the protocol stack.\n" ); - printf( " 's' ... show current status.\n" ); - printf( " 'q' ... quit application.\n" ); - printf( " 'h' ... this information.\n" ); - printf( "\n" ); - printf( "Copyright 2006 Christian Walter \n" ); - break; - default: - if( !bDoExit && ( cCh != '\n' ) ) - { - printf( "illegal command '%c'!\n", cCh ); - } - break; - } - - /* eat up everything untill return character. */ - while( !bDoExit && ( cCh != '\n' ) ) - { - cCh = getchar( ); - } - } - while( !bDoExit ); - - /* Release hardware resources. */ - ( void )eMBClose( ); - iExitCode = EXIT_SUCCESS; - } - return iExitCode; -} - -BOOL -bCreatePollingThread( void ) -{ - BOOL bResult; - pthread_t xThread; - - if( eGetPollingThreadState( ) == STOPPED ) - { - if( pthread_create( &xThread, NULL, pvPollingThread, NULL ) != 0 ) - { - bResult = FALSE; - } - else - { - bResult = TRUE; - } - } - else - { - bResult = FALSE; - } - - return bResult; -} - -void * -pvPollingThread( void *pvParameter ) -{ - vSetPollingThreadState( RUNNING ); - - if( eMBEnable( ) == MB_ENOERR ) - { - do - { - if( eMBPoll( ) != MB_ENOERR ) - break; - usRegInputBuf[0] = ( USHORT ) rand( ); - } - while( eGetPollingThreadState( ) != SHUTDOWN ); - } - - ( void )eMBDisable( ); - - vSetPollingThreadState( STOPPED ); - - return 0; -} - -enum ThreadState -eGetPollingThreadState( ) -{ - enum ThreadState eCurState; - - ( void )pthread_mutex_lock( &xLock ); - eCurState = ePollThreadState; - ( void )pthread_mutex_unlock( &xLock ); - - return eCurState; -} - -void -vSetPollingThreadState( enum ThreadState eNewState ) -{ - ( void )pthread_mutex_lock( &xLock ); - ePollThreadState = eNewState; - ( void )pthread_mutex_unlock( &xLock ); -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_HOLDING_START ) && - ( usAddress + usNRegs <= REG_HOLDING_START + REG_HOLDING_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegHoldingStart ); - switch ( eMode ) - { - /* Pass current register values to the protocol stack. */ - case MB_REG_READ: - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( UCHAR ) ( usRegHoldingBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( UCHAR ) ( usRegHoldingBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - break; - - /* Update current register values with new values from the - * protocol stack. */ - case MB_REG_WRITE: - while( usNRegs > 0 ) - { - usRegHoldingBuf[iRegIndex] = *pucRegBuffer++ << 8; - usRegHoldingBuf[iRegIndex] |= *pucRegBuffer++; - iRegIndex++; - usNRegs--; - } - } - } - else - { - eStatus = MB_ENOREG; - } - return eStatus; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/demo.sh b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/demo.sh deleted file mode 100644 index 3cfff54b6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/demo.sh +++ /dev/null @@ -1 +0,0 @@ -./modpoll -b 38400 -d 8 -p even -a 10 -t 3 -r 1000 /dev/ttyS1 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/demo.vpj b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/demo.vpj deleted file mode 100644 index d17136f62..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/demo.vpj +++ /dev/null @@ -1,246 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/port/port.h deleted file mode 100644 index 79afcde7e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/port/port.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * FreeModbus Libary: Linux Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -#include - -#define INLINE -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif -/* ----------------------- Defines ------------------------------------------*/ -#define ENTER_CRITICAL_SECTION( ) vMBPortEnterCritical() -#define EXIT_CRITICAL_SECTION( ) vMBPortExitCritical() -#define MB_PORT_HAS_CLOSE 1 -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif -/* ----------------------- Type definitions ---------------------------------*/ - typedef enum -{ - MB_LOG_ERROR = 0, - MB_LOG_WARN = 1, - MB_LOG_INFO = 2, - MB_LOG_DEBUG = 3 -} eMBPortLogLevel; - -typedef char BOOL; -typedef unsigned char UCHAR; -typedef char CHAR; -typedef unsigned short USHORT; -typedef short SHORT; - -typedef unsigned long ULONG; -typedef long LONG; - -/* ----------------------- Function prototypes ------------------------------*/ - -void vMBPortEnterCritical( void ); -void vMBPortExitCritical( void ); -void vMBPortLog( eMBPortLogLevel eLevel, const CHAR * szModule, - const CHAR * szFmt, ... ); -void vMBPortTimerPoll( ); -BOOL xMBPortSerialPoll( ); -BOOL xMBPortSerialSetTimeout( ULONG dwTimeoutMs ); - -#ifdef __cplusplus -PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/port/portevent.c deleted file mode 100644 index 12d78f586..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/port/portevent.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * FreeModbus Libary: Linux Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static eMBEventType eQueuedEvent; -static BOOL xEventInQueue; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - xEventInQueue = FALSE; - return TRUE; -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - xEventInQueue = TRUE; - eQueuedEvent = eEvent; - return TRUE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - BOOL xEventHappened = FALSE; - - if( xEventInQueue ) - { - *eEvent = eQueuedEvent; - xEventInQueue = FALSE; - xEventHappened = TRUE; - } - else - { - /* Poll the serial device. The serial device timeouts if no - * characters have been received within for t3.5 during an - * active transmission or if nothing happens within a specified - * amount of time. Both timeouts are configured from the timer - * init functions. - */ - ( void )xMBPortSerialPoll( ); - - /* Check if any of the timers have expired. */ - vMBPortTimerPoll( ); - - } - return xEventHappened; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/port/portother.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/port/portother.c deleted file mode 100644 index 681efc27c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/port/portother.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * FreeModbus Libary: Linux Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Standard includes --------------------------------*/ -#include -#include -#include -#include -#include -#include - -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" -#include "mbconfig.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define NELEMS( x ) ( sizeof( ( x ) )/sizeof( ( x )[0] ) ) - -/* ----------------------- Static variables ---------------------------------*/ -static FILE *fLogFile = NULL; -static eMBPortLogLevel eLevelMax = MB_LOG_DEBUG; -static pthread_mutex_t xLock = PTHREAD_MUTEX_INITIALIZER; - -/* ----------------------- Start implementation -----------------------------*/ -void -vMBPortLogLevel( eMBPortLogLevel eNewLevelMax ) -{ - eLevelMax = eNewLevelMax; -} - -void -vMBPortLogFile( FILE * fNewLogFile ) -{ - fLogFile = fNewLogFile; -} - -void -vMBPortLog( eMBPortLogLevel eLevel, const CHAR * szModule, const CHAR * szFmt, ... ) -{ - CHAR szBuf[512]; - int i; - va_list args; - FILE *fOutput = fLogFile == NULL ? stderr : fLogFile; - - static const char *arszLevel2Str[] = { "ERROR", "WARN", "INFO", "DEBUG" }; - - i = snprintf( szBuf, NELEMS( szBuf ), "%s: %s: ", arszLevel2Str[eLevel], szModule ); - - if( i != 0 ) - { - va_start( args, szFmt ); - i += vsnprintf( &szBuf[i], NELEMS( szBuf ) - i, szFmt, args ); - va_end( args ); - } - - if( i != 0 ) - { - if( eLevel <= eLevelMax ) - { - fputs( szBuf, fOutput ); - } - } -} - -void -vMBPortEnterCritical( void ) -{ - if( pthread_mutex_lock( &xLock ) != 0 ) - { - vMBPortLog( MB_LOG_ERROR, "OTHER", "Locking primitive failed: %s\n", strerror( errno ) ); - } -} - -void -vMBPortExitCritical( void ) -{ - if( pthread_mutex_unlock( &xLock ) != 0 ) - { - vMBPortLog( MB_LOG_ERROR, "OTHER", "Locking primitive failed: %s\n", strerror( errno ) ); - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/port/portserial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/port/portserial.c deleted file mode 100644 index ee04158b8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/port/portserial.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * FreeModbus Libary: Linux Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Standard includes --------------------------------*/ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" -#include "mbconfig.h" - -/* ----------------------- Defines -----------------------------------------*/ -#if MB_ASCII_ENABLED == 1 -#define BUF_SIZE 513 /* must hold a complete ASCII frame. */ -#else -#define BUF_SIZE 256 /* must hold a complete RTU frame. */ -#endif - -/* ----------------------- Static variables ---------------------------------*/ -static int iSerialFd = -1; -static BOOL bRxEnabled; -static BOOL bTxEnabled; - -static ULONG ulTimeoutMs; -static UCHAR ucBuffer[BUF_SIZE]; -static int uiRxBufferPos; -static int uiTxBufferPos; - -static struct termios xOldTIO; - -/* ----------------------- Function prototypes ------------------------------*/ -static BOOL prvbMBPortSerialRead( UCHAR * pucBuffer, USHORT usNBytes, USHORT * usNBytesRead ); -static BOOL prvbMBPortSerialWrite( UCHAR * pucBuffer, USHORT usNBytes ); - -/* ----------------------- Begin implementation -----------------------------*/ -void -vMBPortSerialEnable( BOOL bEnableRx, BOOL bEnableTx ) -{ - /* it is not allowed that both receiver and transmitter are enabled. */ - assert( !bEnableRx || !bEnableTx ); - - if( bEnableRx ) - { - ( void )tcflush( iSerialFd, TCIFLUSH ); - uiRxBufferPos = 0; - bRxEnabled = TRUE; - } - else - { - bRxEnabled = FALSE; - } - if( bEnableTx ) - { - bTxEnabled = TRUE; - uiTxBufferPos = 0; - } - else - { - bTxEnabled = FALSE; - } -} - -BOOL -xMBPortSerialInit( UCHAR ucPort, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity ) -{ - CHAR szDevice[16]; - BOOL bStatus = TRUE; - - struct termios xNewTIO; - speed_t xNewSpeed; - - snprintf( szDevice, 16, "/dev/ttyS%d", ucPort ); - - if( ( iSerialFd = open( szDevice, O_RDWR | O_NOCTTY ) ) < 0 ) - { - vMBPortLog( MB_LOG_ERROR, "SER-INIT", "Can't open serial port %s: %s\n", szDevice, - strerror( errno ) ); - } - else if( tcgetattr( iSerialFd, &xOldTIO ) != 0 ) - { - vMBPortLog( MB_LOG_ERROR, "SER-INIT", "Can't get settings from port %s: %s\n", szDevice, - strerror( errno ) ); - } - else - { - bzero( &xNewTIO, sizeof( struct termios ) ); - - xNewTIO.c_iflag |= IGNBRK | INPCK; - xNewTIO.c_cflag |= CREAD | CLOCAL; - switch ( eParity ) - { - case MB_PAR_NONE: - break; - case MB_PAR_EVEN: - xNewTIO.c_cflag |= PARENB; - break; - case MB_PAR_ODD: - xNewTIO.c_cflag |= PARENB | PARODD; - break; - default: - bStatus = FALSE; - } - switch ( ucDataBits ) - { - case 8: - xNewTIO.c_cflag |= CS8; - break; - case 7: - xNewTIO.c_cflag |= CS7; - break; - default: - bStatus = FALSE; - } - switch ( ulBaudRate ) - { - case 9600: - xNewSpeed = B9600; - break; - case 19200: - xNewSpeed = B19200; - break; - case 38400: - xNewSpeed = B38400; - break; - case 57600: - xNewSpeed = B57600; - break; - case 115200: - xNewSpeed = B115200; - break; - default: - bStatus = FALSE; - } - if( bStatus ) - { - if( cfsetispeed( &xNewTIO, xNewSpeed ) != 0 ) - { - vMBPortLog( MB_LOG_ERROR, "SER-INIT", "Can't set baud rate %ld for port %s: %s\n", - ulBaudRate, strerror( errno ) ); - } - else if( cfsetospeed( &xNewTIO, xNewSpeed ) != 0 ) - { - vMBPortLog( MB_LOG_ERROR, "SER-INIT", "Can't set baud rate %ld for port %s: %s\n", - ulBaudRate, szDevice, strerror( errno ) ); - } - else if( tcsetattr( iSerialFd, TCSANOW, &xNewTIO ) != 0 ) - { - vMBPortLog( MB_LOG_ERROR, "SER-INIT", "Can't set settings for port %s: %s\n", - szDevice, strerror( errno ) ); - } - else - { - vMBPortSerialEnable( FALSE, FALSE ); - bStatus = TRUE; - } - } - } - return bStatus; -} - -BOOL -xMBPortSerialSetTimeout( ULONG ulNewTimeoutMs ) -{ - if( ulNewTimeoutMs > 0 ) - { - ulTimeoutMs = ulNewTimeoutMs; - } - else - { - ulTimeoutMs = 1; - } - return TRUE; -} - -void -vMBPortClose( void ) -{ - if( iSerialFd != -1 ) - { - ( void )tcsetattr( iSerialFd, TCSANOW, &xOldTIO ); - ( void )close( iSerialFd ); - iSerialFd = -1; - } -} - -BOOL -prvbMBPortSerialRead( UCHAR * pucBuffer, USHORT usNBytes, USHORT * usNBytesRead ) -{ - BOOL bResult = TRUE; - ssize_t res; - fd_set rfds; - struct timeval tv; - - tv.tv_sec = 0; - tv.tv_usec = 50000; - FD_ZERO( &rfds ); - FD_SET( iSerialFd, &rfds ); - - /* Wait until character received or timeout. Recover in case of an - * interrupted read system call. */ - do - { - if( select( iSerialFd + 1, &rfds, NULL, NULL, &tv ) == -1 ) - { - if( errno != EINTR ) - { - bResult = FALSE; - } - } - else if( FD_ISSET( iSerialFd, &rfds ) ) - { - if( ( res = read( iSerialFd, pucBuffer, usNBytes ) ) == -1 ) - { - bResult = FALSE; - } - else - { - *usNBytesRead = ( USHORT ) res; - break; - } - } - else - { - *usNBytesRead = 0; - break; - } - } - while( bResult == TRUE ); - return bResult; -} - -BOOL -prvbMBPortSerialWrite( UCHAR * pucBuffer, USHORT usNBytes ) -{ - ssize_t res; - size_t left = ( size_t ) usNBytes; - size_t done = 0; - - while( left > 0 ) - { - if( ( res = write( iSerialFd, pucBuffer + done, left ) ) == -1 ) - { - if( errno != EINTR ) - { - break; - } - /* call write again because of interrupted system call. */ - continue; - } - done += res; - left -= res; - } - return left == 0 ? TRUE : FALSE; -} - -BOOL -xMBPortSerialPoll( ) -{ - BOOL bStatus = TRUE; - USHORT usBytesRead; - int i; - - while( bRxEnabled ) - { - if( prvbMBPortSerialRead( &ucBuffer[0], BUF_SIZE, &usBytesRead ) ) - { - if( usBytesRead == 0 ) - { - /* timeout with no bytes. */ - break; - } - else if( usBytesRead > 0 ) - { - for( i = 0; i < usBytesRead; i++ ) - { - /* Call the modbus stack and let him fill the buffers. */ - ( void )pxMBFrameCBByteReceived( ); - } - uiRxBufferPos = 0; - } - } - else - { - vMBPortLog( MB_LOG_ERROR, "SER-POLL", "read failed on serial device: %s\n", - strerror( errno ) ); - bStatus = FALSE; - } - } - if( bTxEnabled ) - { - while( bTxEnabled ) - { - ( void )pxMBFrameCBTransmitterEmpty( ); - /* Call the modbus stack to let him fill the buffer. */ - } - if( !prvbMBPortSerialWrite( &ucBuffer[0], uiTxBufferPos ) ) - { - vMBPortLog( MB_LOG_ERROR, "SER-POLL", "write failed on serial device: %s\n", - strerror( errno ) ); - bStatus = FALSE; - } - } - - return bStatus; -} - -BOOL -xMBPortSerialPutByte( CHAR ucByte ) -{ - assert( uiTxBufferPos < BUF_SIZE ); - ucBuffer[uiTxBufferPos] = ucByte; - uiTxBufferPos++; - return TRUE; -} - -BOOL -xMBPortSerialGetByte( CHAR * pucByte ) -{ - assert( uiRxBufferPos < BUF_SIZE ); - *pucByte = ucBuffer[uiRxBufferPos]; - uiRxBufferPos++; - return TRUE; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/port/porttimer.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/port/porttimer.c deleted file mode 100644 index a65a0fa3d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUX/port/porttimer.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * FreeModbus Libary: Linux Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Standard includes --------------------------------*/ -#include -#include - -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ - -/* ----------------------- Static variables ---------------------------------*/ -ULONG ulTimeOut; -BOOL bTimeoutEnable; - -static struct timeval xTimeLast; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortTimersInit( USHORT usTim1Timerout50us ) -{ - ulTimeOut = usTim1Timerout50us / 20U; - if( ulTimeOut == 0 ) - ulTimeOut = 1; - - return xMBPortSerialSetTimeout( ulTimeOut ); -} - -void -xMBPortTimersClose( ) -{ - /* Does not use any hardware resources. */ -} - -void -vMBPortTimerPoll( ) -{ - ULONG ulDeltaMS; - struct timeval xTimeCur; - - /* Timers are called from the serial layer because we have no high - * res timer in Win32. */ - if( bTimeoutEnable ) - { - if( gettimeofday( &xTimeCur, NULL ) != 0 ) - { - /* gettimeofday failed - retry next time. */ - } - else - { - ulDeltaMS = ( xTimeCur.tv_sec - xTimeLast.tv_sec ) * 1000L + - ( xTimeCur.tv_usec - xTimeLast.tv_usec ) * 1000L; - if( ulDeltaMS > ulTimeOut ) - { - bTimeoutEnable = FALSE; - ( void )pxMBPortCBTimerExpired( ); - } - } - } -} - -void -vMBPortTimersEnable( ) -{ - int res = gettimeofday( &xTimeLast, NULL ); - - assert( res == 0 ); - bTimeoutEnable = TRUE; -} - -void -vMBPortTimersDisable( ) -{ - bTimeoutEnable = FALSE; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/Makefile b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/Makefile deleted file mode 100644 index 2a7d4eab0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/Makefile +++ /dev/null @@ -1,78 +0,0 @@ -# -# Makefile for tcp freemodbus -# -# Copyright (c) 2007 Steven Guo -# -# --------------------------------------------------------------------------- - -# --------------------------------------------------------------------------- -# platform dependencies -# --------------------------------------------------------------------------- -ifneq ($(strip $(shell gcc -v 2>&1 |grep "cygwin")),) - CYGWIN_BUILD = YES -endif -CC = gcc -CXX = g++ -OBJCOPY = objcopy -INSIGHT = /opt/insight-x86/bin/insight - -# --------------------------------------------------------------------------- -# project specifics -# --------------------------------------------------------------------------- -CFLAGS = -g -Wall -Iport -I../../modbus/rtu \ - -I../../modbus/ascii -I../../modbus/include -I../../modbus/tcp -LDFLAGS = -ifeq ($(CYGWIN_BUILD),YES) -else -LDFLAGS += -lpthread -CFLAGS += -pthread -endif - -TGT = tcpmodbus -OTHER_CSRC = -OTHER_ASRC = -CSRC = demo.c port/portother.c \ - port/portevent.c port/porttcp.c \ - ../../modbus/mb.c ../../modbus/tcp/mbtcp.c \ - ../../modbus/functions/mbfunccoils.c \ - ../../modbus/functions/mbfuncdiag.c \ - ../../modbus/functions/mbfuncholding.c \ - ../../modbus/functions/mbfuncinput.c \ - ../../modbus/functions/mbfuncother.c \ - ../../modbus/functions/mbfuncdisc.c \ - ../../modbus/functions/mbutils.c -ASRC = -OBJS = $(CSRC:.c=.o) $(ASRC:.S=.o) -NOLINK_OBJS = $(OTHER_CSRC:.c=.o) $(OTHER_ASRC:.S=.o) -DEPS = $(OBJS:.o=.d) $(NOLINK_OBJS:.o=.d) -BIN = $(TGT) - -.PHONY: clean all - -all: $(BIN) - -debug: - $(INSIGHT) --se=$(TGT) - -$(BIN): $(OBJS) $(NOLINK_OBJS) - $(CC) $(LDFLAGS) $(OBJS) $(LDLIBS) -o $@ - -clean: - rm -f $(DEPS) - rm -f $(OBJS) $(NOLINK_OBJS) - rm -f $(BIN) - -# --------------------------------------------------------------------------- -# rules for code generation -# --------------------------------------------------------------------------- -%.o: %.c - $(CC) $(CFLAGS) -o $@ -c $< - -%.o: %.S - $(CC) $(ASFLAGS) -o $@ -c $< - -# --------------------------------------------------------------------------- -# # compiler generated dependencies -# --------------------------------------------------------------------------- --include $(LWOS_DEPS) $(PORT_DEPS) $(APPL_DEPS) - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/demo.c deleted file mode 100644 index a6183f458..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/demo.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - * FreeModbus Libary: Win32 Demo Application - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - - /********************************************************** - * Linux TCP support. - * Based on Walter's project. - * Modified by Steven Guo - ***********************************************************/ - -/* ----------------------- Standard C Libs includes --------------------------*/ -#include -#include -#include -#include -#include -#include -#include - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define PROG "freemodbus" - -#define REG_INPUT_START 1000 -#define REG_INPUT_NREGS 4 -#define REG_HOLDING_START 2000 -#define REG_HOLDING_NREGS 130 - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegInputStart = REG_INPUT_START; -static USHORT usRegInputBuf[REG_INPUT_NREGS]; -static USHORT usRegHoldingStart = REG_HOLDING_START; -static USHORT usRegHoldingBuf[REG_HOLDING_NREGS]; -static pthread_mutex_t xLock = PTHREAD_MUTEX_INITIALIZER; -static enum ThreadState -{ - STOPPED, - RUNNING, - SHUTDOWN -} ePollThreadState; - -/* ----------------------- Static functions ---------------------------------*/ -static BOOL bCreatePollingThread( void ); -static enum ThreadState eGetPollingThreadState( void ); -static void eSetPollingThreadState( enum ThreadState eNewState ); -static void* pvPollingThread( void *pvParameter ); - -/* ----------------------- Start implementation -----------------------------*/ -int -main( int argc, char *argv[] ) -{ - int iExitCode; - CHAR cCh; - BOOL bDoExit; - - if( eMBTCPInit( MB_TCP_PORT_USE_DEFAULT ) != MB_ENOERR ) - { - fprintf( stderr, "%s: can't initialize modbus stack!\r\n", PROG ); - iExitCode = EXIT_FAILURE; - } - else - { - eSetPollingThreadState( STOPPED ); - /* CLI interface. */ - printf( "Type 'q' for quit or 'h' for help!\r\n" ); - bDoExit = FALSE; - do - { - printf( "> " ); - cCh = getchar( ); - switch ( cCh ) - { - case 'q' : - bDoExit = TRUE; - break; - case 'd' : - eSetPollingThreadState( SHUTDOWN ); - break; - case 'e' : - if( bCreatePollingThread( ) != TRUE ) - { - printf( "Can't start protocol stack! Already running?\r\n" ); - } - break; - case 's' : - switch ( eGetPollingThreadState( ) ) - { - case RUNNING: - printf( "Protocol stack is running.\r\n" ); - break; - case STOPPED: - printf( "Protocol stack is stopped.\r\n" ); - break; - case SHUTDOWN: - printf( "Protocol stack is shuting down.\r\n" ); - break; - } - break; - case 'h': - printf( "FreeModbus demo application help:\r\n" ); - printf( " 'd' ... disable protocol stack.\r\n" ); - printf( " 'e' ... enabled the protocol stack\r\n" ); - printf( " 's' ... show current status\r\n" ); - printf( " 'q' ... quit applicationr\r\n" ); - printf( " 'h' ... this information\r\n" ); - printf( "\r\n" ); - printf( "Copyright 2007 Steven Guo \r\n" ); - break; - default: - if( cCh != '\n' ) - { - printf( "illegal command '%c'!\r\n" , cCh ); - } - break; - } - - /* eat up everything untill return character. */ - while( cCh != '\n' ) - { - cCh = getchar( ); - } - } - while( !bDoExit ); - - /* Release hardware resources. */ - ( void )eMBClose( ); - iExitCode = EXIT_SUCCESS; - } - return iExitCode; -} - -BOOL -bCreatePollingThread( void ) -{ - BOOL bResult; - pthread_t xThread; - if( eGetPollingThreadState( ) == STOPPED ) - { - if( pthread_create( &xThread, NULL, pvPollingThread, NULL ) != 0 ) - { - /* Can't create the polling thread. */ - bResult = FALSE; - } - else - { - bResult = TRUE; - } - } - else - { - bResult = FALSE; - } - - return bResult; -} - -void* pvPollingThread( void *pvParameter ) -{ - eSetPollingThreadState( RUNNING ); - - if( eMBEnable( ) == MB_ENOERR ) - { - do - { - if( eMBPoll( ) != MB_ENOERR ) - break; - } - while( eGetPollingThreadState( ) != SHUTDOWN ); - } - - ( void )eMBDisable( ); - - eSetPollingThreadState( STOPPED ); - - return 0; -} - -enum ThreadState -eGetPollingThreadState( ) -{ - enum ThreadState eCurState; - - ( void )pthread_mutex_lock( &xLock ); - eCurState = ePollThreadState; - ( void )pthread_mutex_unlock( &xLock ); - - return eCurState; -} - -void -eSetPollingThreadState( enum ThreadState eNewState ) -{ - ( void )pthread_mutex_lock( &xLock ); - ePollThreadState = eNewState; - ( void )pthread_mutex_unlock( &xLock ); -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_HOLDING_START ) && - ( usAddress + usNRegs <= REG_HOLDING_START + REG_HOLDING_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegHoldingStart ); - switch ( eMode ) - { - /* Pass current register values to the protocol stack. */ - case MB_REG_READ: - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( UCHAR ) ( usRegHoldingBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( UCHAR ) ( usRegHoldingBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - break; - - /* Update current register values with new values from the - * protocol stack. */ - case MB_REG_WRITE: - while( usNRegs > 0 ) - { - usRegHoldingBuf[iRegIndex] = *pucRegBuffer++ << 8; - usRegHoldingBuf[iRegIndex] |= *pucRegBuffer++; - iRegIndex++; - usNRegs--; - } - } - } - else - { - eStatus = MB_ENOREG; - } - return eStatus; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/port/port.h deleted file mode 100644 index d9f047b32..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/port/port.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * FreeModbus Libary: BSD Socket Library Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - - /********************************************************** - * Linux TCP support. - * Based on Walter's project. - * Modified by Steven Guo - ***********************************************************/ - -#ifndef _PORT_H -#define _PORT_H - - -#include - -#define INLINE -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif -/* ----------------------- Defines ------------------------------------------*/ -#define ENTER_CRITICAL_SECTION( ) -#define EXIT_CRITICAL_SECTION( ) -#define MB_PORT_HAS_CLOSE 1 -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif -/* ----------------------- Type definitions ---------------------------------*/ -typedef int SOCKET; - -#define SOCKET_ERROR (-1) -#define INVALID_SOCKET (~0) -typedef char BOOL; -typedef unsigned char UCHAR; -typedef unsigned char BYTE; -typedef char CHAR; -typedef unsigned short USHORT; -typedef short SHORT; - -typedef unsigned long ULONG; -typedef long LONG; -typedef enum -{ - MB_LOG_DEBUG, - MB_LOG_INFO, - MB_LOG_WARN, - MB_LOG_ERROR -} eMBPortLogLevel; - -/* ----------------------- Function prototypes ------------------------------*/ - -void TcpvMBPortLog( eMBPortLogLevel eLevel, const CHAR * szModule, const CHAR * szFmt, - ... ); - -#ifdef __cplusplus -PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/port/portevent.c deleted file mode 100644 index b56fa4f0e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/port/portevent.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * FreeModbus Libary: Win32 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - - /********************************************************** - * Linux TCP support. - * Based on Walter's project. - * Modified by Steven Guo - ***********************************************************/ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static eMBEventType eQueuedEvent; -static BOOL xEventInQueue; - -/* ----------------------- Function prototypes ------------------------------*/ -BOOL xMBPortTCPPool( void ); - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - xEventInQueue = FALSE; - return TRUE; -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - xEventInQueue = TRUE; - eQueuedEvent = eEvent; - return TRUE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - BOOL xEventHappened = FALSE; - - if( xEventInQueue ) - { - *eEvent = eQueuedEvent; - xEventInQueue = FALSE; - xEventHappened = TRUE; - } - else - { - /* We can't do anything with errors from the pooling module. */ - ( void )xMBPortTCPPool( ); - } - return xEventHappened; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/port/portother.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/port/portother.c deleted file mode 100644 index 70ec43bbf..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/port/portother.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * FreeModbus Libary: Win32 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - - /********************************************************** - * Linux TCP support. - * Based on Walter's project. - * Modified by Steven Guo - ***********************************************************/ - -#include -#include -#include - -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" -#include "mbconfig.h" - - -BOOL -prvMBTCPPortAddressToString( SOCKET xSocket, CHAR * szAddr, USHORT usBufSize ) -{ - return TRUE; -} - -CHAR * -prvMBTCPPortFrameToString( UCHAR * pucFrame, USHORT usFrameLen ) -{ - return NULL; -} - -CHAR * -WsaError2String( int iError ) -{ - return NULL; -} - -void -vMBPortLog( eMBPortLogLevel eLevel, const CHAR * szModule, const CHAR * szFmt, ... ) -{ - va_list args; - static const CHAR *arszLevel2Str[] = { "DEBUG", "INFO", "WARN", "ERROR" }; - - fprintf( stderr, "%s: %s: ", arszLevel2Str[eLevel], szModule ); - - va_start( args, szFmt ); - fprintf( stderr, szFmt, args ); - va_end( args ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/port/porttcp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/port/porttcp.c deleted file mode 100644 index 5cfc2fb40..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LINUXTCP/port/porttcp.c +++ /dev/null @@ -1,367 +0,0 @@ -/* - * FreeModbus Libary: Win32 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* - * Design Notes: - * - * The xMBPortTCPInit function allocates a socket and binds the socket to - * all available interfaces ( bind with INADDR_ANY ). In addition it - * creates an array of event objects which is used to check the state of - * the clients. On event object is used to handle new connections or - * closed ones. The other objects are used on a per client basis for - * processing. - */ - - /********************************************************** - * Linux TCP support. - * Based on Walter's project. - * Modified by Steven Guo - ***********************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - - - -/* ----------------------- MBAP Header --------------------------------------*/ -#define MB_TCP_UID 6 -#define MB_TCP_LEN 4 -#define MB_TCP_FUNC 7 - -/* ----------------------- Defines -----------------------------------------*/ -#define MB_TCP_DEFAULT_PORT 502 /* TCP listening port. */ -#define MB_TCP_POOL_TIMEOUT 50 /* pool timeout for event waiting. */ -#define MB_TCP_READ_TIMEOUT 1000 /* Maximum timeout to wait for packets. */ -#define MB_TCP_READ_CYCLE 100 /* Time between checking for new data. */ - -#define MB_TCP_DEBUG 1 /* Set to 1 for additional debug output. */ - -#define MB_TCP_BUF_SIZE ( 256 + 7 ) /* Must hold a complete Modbus TCP frame. */ - -#define EV_CONNECTION 0 -#define EV_CLIENT 1 -#define EV_NEVENTS EV_CLIENT + 1 - -/* ----------------------- Static variables ---------------------------------*/ -SOCKET xListenSocket; -SOCKET xClientSocket = INVALID_SOCKET; -static fd_set allset; - -static UCHAR aucTCPBuf[MB_TCP_BUF_SIZE]; -static USHORT usTCPBufPos; -static USHORT usTCPFrameBytesLeft; - -/* ----------------------- External functions -------------------------------*/ -CHAR *WsaError2String( int dwError ); - -/* ----------------------- Static functions ---------------------------------*/ -BOOL prvMBTCPPortAddressToString( SOCKET xSocket, CHAR * szAddr, USHORT usBufSize ); -CHAR *prvMBTCPPortFrameToString( UCHAR * pucFrame, USHORT usFrameLen ); -static BOOL prvbMBPortAcceptClient( void ); -static void prvvMBPortReleaseClient( void ); - - -/* ----------------------- Begin implementation -----------------------------*/ - -BOOL -xMBTCPPortInit( USHORT usTCPPort ) -{ - USHORT usPort; - struct sockaddr_in serveraddr; - - if( usTCPPort == 0 ) - { - usPort = MB_TCP_DEFAULT_PORT; - } - else - { - usPort = ( USHORT ) usTCPPort; - } - memset( &serveraddr, 0, sizeof( serveraddr ) ); - serveraddr.sin_family = AF_INET; - serveraddr.sin_addr.s_addr = htonl( INADDR_ANY ); - serveraddr.sin_port = htons( usPort ); - if( ( xListenSocket = socket( AF_INET, SOCK_STREAM, IPPROTO_TCP ) ) == -1 ) - { - fprintf( stderr, "Create socket failed.\r\n" ); - return FALSE; - } - else if( bind( xListenSocket, ( struct sockaddr * )&serveraddr, sizeof( serveraddr ) ) == -1 ) - { - fprintf( stderr, "Bind socket failed.\r\n" ); - return FALSE; - } - else if( listen( xListenSocket, 5 ) == -1 ) - { - fprintf( stderr, "Listen socket failed.\r\n" ); - return FALSE; - } - FD_ZERO( &allset ); - FD_SET( xListenSocket, &allset ); - return TRUE; -} - -void -vMBTCPPortClose( ) -{ - // Close all client sockets. - if( xClientSocket != SOCKET_ERROR ) - { - prvvMBPortReleaseClient( ); - } - // Close the listener socket. - if( xListenSocket != SOCKET_ERROR ) - { - close( xListenSocket ); - } -} - -void -vMBTCPPortDisable( void ) -{ - /* Close all client sockets. */ - if( xClientSocket != SOCKET_ERROR ) - { - prvvMBPortReleaseClient( ); - } -} - -/*! \ingroup port_win32tcp - * - * \brief Pool the listening socket and currently connected Modbus TCP clients - * for new events. - * \internal - * - * This function checks if new clients want to connect or if already connected - * clients are sending requests. If a new client is connected and there are - * still client slots left (The current implementation supports only one) - * then the connection is accepted and an event object for the new client - * socket is activated (See prvbMBPortAcceptClient() ). - * Events for already existing clients in \c FD_READ and \c FD_CLOSE. In case of - * an \c FD_CLOSE the client connection is released (See prvvMBPortReleaseClient() ). - * In case of an \c FD_READ command the existing data is read from the client - * and if a complete frame has been received the Modbus Stack is notified. - * - * \return FALSE in case of an internal I/O error. For example if the internal - * event objects are in an invalid state. Note that this does not include any - * client errors. In all other cases returns TRUE. - */ -BOOL -xMBPortTCPPool( void ) -{ - int n; - fd_set fread; - struct timeval tval; - - tval.tv_sec = 0; - tval.tv_usec = 5000; - int ret; - USHORT usLength; - - if( xClientSocket == INVALID_SOCKET ) - { - /* Accept to client */ - if( ( n = select( xListenSocket + 1, &allset, NULL, NULL, NULL ) ) < 0 ) - { - if( errno == EINTR ) - { - ; - } - else - { - ; - } - } - if( FD_ISSET( xListenSocket, &allset ) ) - { - ( void )prvbMBPortAcceptClient( ); - } - } - while( TRUE ) - { - FD_ZERO( &fread ); - FD_SET( xClientSocket, &fread ); - if( ( ( ret = select( xClientSocket + 1, &fread, NULL, NULL, &tval ) ) == SOCKET_ERROR ) - || !ret ) - { - continue; - } - if( ret > 0 ) - { - if( FD_ISSET( xClientSocket, &fread ) ) - { - if( ( ( ret = - recv( xClientSocket, &aucTCPBuf[usTCPBufPos], usTCPFrameBytesLeft, - 0 ) ) == SOCKET_ERROR ) || ( !ret ) ) - { - close( xClientSocket ); - xClientSocket = INVALID_SOCKET; - return TRUE; - } - usTCPBufPos += ret; - usTCPFrameBytesLeft -= ret; - if( usTCPBufPos >= MB_TCP_FUNC ) - { - /* Length is a byte count of Modbus PDU (function code + data) and the - * unit identifier. */ - usLength = aucTCPBuf[MB_TCP_LEN] << 8U; - usLength |= aucTCPBuf[MB_TCP_LEN + 1]; - - /* Is the frame already complete. */ - if( usTCPBufPos < ( MB_TCP_UID + usLength ) ) - { - usTCPFrameBytesLeft = usLength + MB_TCP_UID - usTCPBufPos; - } - /* The frame is complete. */ - else if( usTCPBufPos == ( MB_TCP_UID + usLength ) ) - { - ( void )xMBPortEventPost( EV_FRAME_RECEIVED ); - return TRUE; - } - /* This can not happend because we always calculate the number of bytes - * to receive. */ - else - { - assert( usTCPBufPos <= ( MB_TCP_UID + usLength ) ); - } - } - } - } - } - return TRUE; -} - -/*! - * \ingroup port_win32tcp - * \brief Receives parts of a Modbus TCP frame and if complete notifies - * the protocol stack. - * \internal - * - * This function reads a complete Modbus TCP frame from the protocol stack. - * It starts by reading the header with an initial request size for - * usTCPFrameBytesLeft = MB_TCP_FUNC. If the header is complete the - * number of bytes left can be calculated from it (See Length in MBAP header). - * Further read calls are issued until the frame is complete. - * - * \return \c TRUE if part of a Modbus TCP frame could be processed. In case - * of a communication error the function returns \c FALSE. - */ - -BOOL -xMBTCPPortGetRequest( UCHAR ** ppucMBTCPFrame, USHORT * usTCPLength ) -{ - *ppucMBTCPFrame = &aucTCPBuf[0]; - *usTCPLength = usTCPBufPos; - - /* Reset the buffer. */ - usTCPBufPos = 0; - usTCPFrameBytesLeft = MB_TCP_FUNC; - return TRUE; -} - -BOOL -xMBTCPPortSendResponse( const UCHAR * pucMBTCPFrame, USHORT usTCPLength ) -{ - BOOL bFrameSent = FALSE; - BOOL bAbort = FALSE; - int res; - int iBytesSent = 0; - int iTimeOut = MB_TCP_READ_TIMEOUT; - - do - { - res = send( xClientSocket, &pucMBTCPFrame[iBytesSent], usTCPLength - iBytesSent, 0 ); - switch ( res ) - { - case -1: - if( iTimeOut > 0 ) - { - iTimeOut -= MB_TCP_READ_CYCLE; - usleep( MB_TCP_READ_CYCLE ); - } - else - { - bAbort = TRUE; - } - break; - case 0: - prvvMBPortReleaseClient( ); - bAbort = TRUE; - break; - default: - iBytesSent += res; - break; - } - } - while( ( iBytesSent != usTCPLength ) && !bAbort ); - - bFrameSent = iBytesSent == usTCPLength ? TRUE : FALSE; - - return bFrameSent; -} - -void -prvvMBPortReleaseClient( ) -{ - ( void )recv( xClientSocket, &aucTCPBuf[0], MB_TCP_BUF_SIZE, 0 ); - - ( void )close( xClientSocket ); - xClientSocket = INVALID_SOCKET; -} - -BOOL -prvbMBPortAcceptClient( ) -{ - SOCKET xNewSocket; - BOOL bOkay; - - /* Check if we can handle a new connection. */ - - if( xClientSocket != INVALID_SOCKET ) - { - fprintf( stderr, "can't accept new client. all connections in use.\n" ); - bOkay = FALSE; - } - else if( ( xNewSocket = accept( xListenSocket, NULL, NULL ) ) == INVALID_SOCKET ) - { - bOkay = FALSE; - } - else - { - xClientSocket = xNewSocket; - usTCPBufPos = 0; - usTCPFrameBytesLeft = MB_TCP_FUNC; - bOkay = TRUE; - } - return bOkay; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/README.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/README.txt deleted file mode 100644 index e55bb3f69..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/README.txt +++ /dev/null @@ -1,46 +0,0 @@ - - FREEMODBUS 1.2 LPC214X PORT - =========================== - -REQUIREMENTS -============ - -This demo application provides a port for the LPC214X series of processors -from NXP Semiconductors. The port was done using the MCB2140 from Keil[1] -which features a LPC2148 MCU. -It requires a wired serial port to a host processor and a Modbus Master -Software on the PC side to be useful. Demo versions of Modbus Masters -can be found in [2] and [3]. - - -TESTING -======= - -Start the Modbus Sample Application and test if the input registers starting -at protocol address 1000 can be read. There are four registers value avai- -lable and the output should look like: - -Polling slave (Ctrl-C to stop) ... -[1000]: 6474 -[1001]: 0 -[1002]: 0 -[1003]: 0 -Polling slave (Ctrl-C to stop) ... -[1000]: -8831 -[1001]: 0 -[1002]: 0 -[1003]: 0 -Polling slave (Ctrl-C to stop) ... - -The simple testing utility used in the 'demo_rtu.bat' script can be found -at [4]. - - -[1] Keil MCB2140 kit: http://www.keil.com/mcb2140/ -[2] WinTech ModScan32: http://www.win-tech.com/html/modscan32.htm -[3] Modus Poll: http://www.modbustools.com/modbus_poll.asp -[4] FieldTalk Modpoll: http://www.focus-sw.com/fieldtalk/modpoll.html - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/Startup.s b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/Startup.s deleted file mode 100644 index 4ff44ebee..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/Startup.s +++ /dev/null @@ -1,435 +0,0 @@ -/***********************************************************************/ -/* This file is part of the uVision/ARM development tools */ -/* Copyright KEIL ELEKTRONIK GmbH 2002-2005 */ -/***********************************************************************/ -/* */ -/* STARTUP.S: Startup file for Philips LPC2000 device series */ -/* */ -/***********************************************************************/ - - -/* -//*** <<< Use Configuration Wizard in Context Menu >>> *** -*/ - - -/* - * The STARTUP.S code is executed after CPU Reset. This file may be - * translated with the following SET symbols. In uVision these SET - * symbols are entered under Options - ASM - Set. - * - * REMAP: when set the startup code initializes the register MEMMAP - * which overwrites the settings of the CPU configuration pins. The - * startup and interrupt vectors are remapped from: - * 0x00000000 default setting (not remapped) - * 0x80000000 when EXTMEM_MODE is used - * 0x40000000 when RAM_MODE is used - * - * EXTMEM_MODE: when set the device is configured for code execution - * from external memory starting at address 0x80000000. The startup - * vectors are located to 0x80000000. - * - * RAM_MODE: when set the device is configured for code execution - * from on-chip RAM starting at address 0x40000000. The startup - * vectors are located to 0x40000000. - */ - - -// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs - - Mode_USR EQU 0x10 - Mode_FIQ EQU 0x11 - Mode_IRQ EQU 0x12 - Mode_SVC EQU 0x13 - Mode_ABT EQU 0x17 - Mode_UND EQU 0x1B - Mode_SYS EQU 0x1F - - I_Bit EQU 0x80 /* when I bit is set, IRQ is disabled */ - F_Bit EQU 0x40 /* when F bit is set, FIQ is disabled */ - - -/* -// Stack Configuration (Stack Sizes in Bytes) -// Undefined Mode <0x0-0xFFFFFFFF:4> -// Supervisor Mode <0x0-0xFFFFFFFF:4> -// Abort Mode <0x0-0xFFFFFFFF:4> -// Fast Interrupt Mode <0x0-0xFFFFFFFF:4> -// Interrupt Mode <0x0-0xFFFFFFFF:4> -// User/System Mode <0x0-0xFFFFFFFF:4> -// -*/ - UND_Stack_Size EQU 0x00000004 - SVC_Stack_Size EQU 0x00000004 - ABT_Stack_Size EQU 0x00000004 - FIQ_Stack_Size EQU 0x00000004 - IRQ_Stack_Size EQU 0x00000080 - USR_Stack_Size EQU 0x00000400 - -AREA STACK, DATA, READWRITE, ALIGN=2 - DS (USR_Stack_Size+3)&~3 ; Stack for User/System Mode - DS (SVC_Stack_Size+3)&~3 ; Stack for Supervisor Mode - DS (IRQ_Stack_Size+3)&~3 ; Stack for Interrupt Mode - DS (FIQ_Stack_Size+3)&~3 ; Stack for Fast Interrupt Mode - DS (ABT_Stack_Size+3)&~3 ; Stack for Abort Mode - DS (UND_Stack_Size+3)&~3 ; Stack for Undefined Mode -Top_Stack: - - -// VPBDIV definitions - VPBDIV EQU 0xE01FC100 /* VPBDIV Address */ - -/* -// VPBDIV Setup -// Peripheral Bus Clock Rate -// VPBDIV: VPB Clock -// <0=> VPB Clock = CPU Clock / 4 -// <1=> VPB Clock = CPU Clock -// <2=> VPB Clock = CPU Clock / 2 -// XCLKDIV: XCLK Pin -// <0=> XCLK Pin = CPU Clock / 4 -// <1=> XCLK Pin = CPU Clock -// <2=> XCLK Pin = CPU Clock / 2 -// -*/ - VPBDIV_SETUP EQU 0 - VPBDIV_Val EQU 0x00000000 - - -// Phase Locked Loop (PLL) definitions - PLL_BASE EQU 0xE01FC080 /* PLL Base Address */ - PLLCON_OFS EQU 0x00 /* PLL Control Offset*/ - PLLCFG_OFS EQU 0x04 /* PLL Configuration Offset */ - PLLSTAT_OFS EQU 0x08 /* PLL Status Offset */ - PLLFEED_OFS EQU 0x0C /* PLL Feed Offset */ - PLLCON_PLLE EQU (1<<0) /* PLL Enable */ - PLLCON_PLLC EQU (1<<1) /* PLL Connect */ - PLLCFG_MSEL EQU (0x1F<<0) /* PLL Multiplier */ - PLLCFG_PSEL EQU (0x03<<5) /* PLL Divider */ - PLLSTAT_PLOCK EQU (1<<10) /* PLL Lock Status */ - -/* -// PLL Setup -// Phase Locked Loop -// CCLK - Processor Clock -// Fcco - PLL Oscillator -// MSEL: PLL Multiplier Selection -// <1-32><#-1> -// PLL Multiplier "M" Value -// CCLK = M * Fosc -// PSEL: PLL Divider Selection -// <0=> 1 <1=> 2 <2=> 4 <3=> 8 -// PLL Divider "P" Value -// Fcco = CCLK * 2 * P -// 156MHz <= Fcco <= 320MHz -// -*/ - PLL_SETUP EQU 1 - PLLCFG_Val EQU 0x00000024 - - -// Memory Accelerator Module (MAM) definitions - MAM_BASE EQU 0xE01FC000 /* MAM Base Address */ - MAMCR_OFS EQU 0x00 /* MAM Control Offset*/ - MAMTIM_OFS EQU 0x04 /* MAM Timing Offset */ - -/* -// MAM Setup -// Memory Accelerator Module -// MAM Control -// <0=> Disabled -// <1=> Partially Enabled -// <2=> Fully Enabled -// Mode -// MAM Timing -// <0=> Reserved <1=> 1 <2=> 2 <3=> 3 -// <4=> 4 <5=> 5 <6=> 6 <7=> 7 -// Fetch Cycles -// -*/ - MAM_SETUP EQU 1 - MAMCR_Val EQU 0x00000002 - MAMTIM_Val EQU 0x00000004 - - -// External Memory Controller (EMC) definitions - EMC_BASE EQU 0xFFE00000 /* EMC Base Address */ - BCFG0_OFS EQU 0x00 /* BCFG0 Offset */ - BCFG1_OFS EQU 0x04 /* BCFG1 Offset */ - BCFG2_OFS EQU 0x08 /* BCFG2 Offset */ - BCFG3_OFS EQU 0x0C /* BCFG3 Offset */ - -/* -// External Memory Controller (EMC) -*/ - EMC_SETUP EQU 0 - -/* -// Bank Configuration 0 (BCFG0) -// IDCY: Idle Cycles <0-15> -// WST1: Wait States 1 <0-31> -// WST2: Wait States 2 <0-31> -// RBLE: Read Byte Lane Enable -// WP: Write Protect -// BM: Burst ROM -// MW: Memory Width <0=> 8-bit <1=> 16-bit -// <2=> 32-bit <3=> Reserved -// -*/ - BCFG0_SETUP EQU 0 - BCFG0_Val EQU 0x0000FBEF - -/* -// Bank Configuration 1 (BCFG1) -// IDCY: Idle Cycles <0-15> -// WST1: Wait States 1 <0-31> -// WST2: Wait States 2 <0-31> -// RBLE: Read Byte Lane Enable -// WP: Write Protect -// BM: Burst ROM -// MW: Memory Width <0=> 8-bit <1=> 16-bit -// <2=> 32-bit <3=> Reserved -// -*/ - BCFG1_SETUP EQU 0 - BCFG1_Val EQU 0x0000FBEF - -/* -// Bank Configuration 2 (BCFG2) -// IDCY: Idle Cycles <0-15> -// WST1: Wait States 1 <0-31> -// WST2: Wait States 2 <0-31> -// RBLE: Read Byte Lane Enable -// WP: Write Protect -// BM: Burst ROM -// MW: Memory Width <0=> 8-bit <1=> 16-bit -// <2=> 32-bit <3=> Reserved -// -*/ - BCFG2_SETUP EQU 0 - BCFG2_Val EQU 0x0000FBEF - -/* -// Bank Configuration 3 (BCFG3) -// IDCY: Idle Cycles <0-15> -// WST1: Wait States 1 <0-31> -// WST2: Wait States 2 <0-31> -// RBLE: Read Byte Lane Enable -// WP: Write Protect -// BM: Burst ROM -// MW: Memory Width <0=> 8-bit <1=> 16-bit -// <2=> 32-bit <3=> Reserved -// -*/ - BCFG3_SETUP EQU 0 - BCFG3_Val EQU 0x0000FBEF - -/* -// End of EMC -*/ - - -// External Memory Pins definitions - PINSEL2 EQU 0xE002C014 /* PINSEL2 Address */ - PINSEL2_Val EQU 0x0E6149E4 /* CS0..3, OE, WE, BLS0..3, - D0..31, A2..23, JTAG Pins */ - - -// Starupt Code must be linked first at Address at which it expects to run. - -$IF (EXTMEM_MODE) - CODE_BASE EQU 0x80000000 -$ELSEIF (RAM_MODE) - CODE_BASE EQU 0x40000000 -$ELSE - CODE_BASE EQU 0x00000000 -$ENDIF - -AREA STARTUPCODE, CODE, AT CODE_BASE // READONLY, ALIGN=4 - PUBLIC __startup - - EXTERN CODE32 (?C?INIT) - -__startup PROC CODE32 - -// Pre-defined interrupt handlers that may be directly -// overwritten by C interrupt functions -EXTERN CODE32 (Undef_Handler?A) -EXTERN CODE32 (SWI_Handler?A) -EXTERN CODE32 (PAbt_Handler?A) -EXTERN CODE32 (DAbt_Handler?A) -EXTERN CODE32 (IRQ_Handler?A) -EXTERN CODE32 (FIQ_Handler?A) - -// Exception Vectors -// Mapped to Address 0. -// Absolute addressing mode must be used. - -Vectors: LDR PC,Reset_Addr - LDR PC,Undef_Addr - LDR PC,SWI_Addr - LDR PC,PAbt_Addr - LDR PC,DAbt_Addr - NOP /* Reserved Vector */ -; LDR PC,IRQ_Addr - LDR PC,[PC, #-0x0FF0] /* Vector from VicVectAddr */ - LDR PC,FIQ_Addr - -Reset_Addr: DD Reset_Handler -Undef_Addr: DD Undef_Handler?A -SWI_Addr: DD SWI_Handler?A -PAbt_Addr: DD PAbt_Handler?A -DAbt_Addr: DD DAbt_Handler?A - DD 0 /* Reserved Address */ -IRQ_Addr: DD IRQ_Handler?A -FIQ_Addr: DD FIQ_Handler?A - - -// Reset Handler - -Reset_Handler: - - -$IF (EXTMEM_MODE) - LDR R0, =PINSEL2 - LDR R1, =PINSEL2_Val - STR R1, [R0] -$ENDIF - - -IF (EMC_SETUP != 0) - LDR R0, =EMC_BASE - -IF (BCFG0_SETUP != 0) - LDR R1, =BCFG0_Val - STR R1, [R0, #BCFG0_OFS] -ENDIF - -IF (BCFG1_SETUP != 0) - LDR R1, =BCFG1_Val - STR R1, [R0, #BCFG1_OFS] -ENDIF - -IF (BCFG2_SETUP != 0) - LDR R1, =BCFG2_Val - STR R1, [R0, #BCFG2_OFS] -ENDIF - -IF (BCFG3_SETUP != 0) - LDR R1, =BCFG3_Val - STR R1, [R0, #BCFG3_OFS] -ENDIF - -ENDIF - - -IF (VPBDIV_SETUP != 0) - LDR R0, =VPBDIV - LDR R1, =VPBDIV_Val - STR R1, [R0] -ENDIF - - -IF (PLL_SETUP != 0) - LDR R0, =PLL_BASE - MOV R1, #0xAA - MOV R2, #0x55 - -// Configure and Enable PLL - MOV R3, #PLLCFG_Val - STR R3, [R0, #PLLCFG_OFS] - MOV R3, #PLLCON_PLLE - STR R3, [R0, #PLLCON_OFS] - STR R1, [R0, #PLLFEED_OFS] - STR R2, [R0, #PLLFEED_OFS] - -// Wait until PLL Locked -PLL_Loop: LDR R3, [R0, #PLLSTAT_OFS] - ANDS R3, R3, #PLLSTAT_PLOCK - BEQ PLL_Loop - -// Switch to PLL Clock - MOV R3, #(PLLCON_PLLE | PLLCON_PLLC) - STR R3, [R0, #PLLCON_OFS] - STR R1, [R0, #PLLFEED_OFS] - STR R2, [R0, #PLLFEED_OFS] -ENDIF - - -IF (MAM_SETUP != 0) - LDR R0, =MAM_BASE - MOV R1, #MAMTIM_Val - STR R1, [R0, #MAMTIM_OFS] - MOV R1, #MAMCR_Val - STR R1, [R0, #MAMCR_OFS] -ENDIF - - -// Memory Mapping - MEMMAP EQU 0xE01FC040 /* Memory Mapping Control */ - -$IF (REMAP) - LDR R0, =MEMMAP -$IF (EXTMEM_MODE) - MOV R1, #3 -$ELSEIF (RAM_MODE) - MOV R1, #2 -$ELSE - MOV R1, #1 -$ENDIF - STR R1, [R0] -$ENDIF - - -// Setup Stack for each mode - LDR R0, =Top_Stack - -// Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_c, #Mode_UND|I_Bit|F_Bit - MOV SP, R0 - SUB R0, R0, #UND_Stack_Size - -// Enter Abort Mode and set its Stack Pointer - MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit - MOV SP, R0 - SUB R0, R0, #ABT_Stack_Size - -// Enter FIQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit - MOV SP, R0 - SUB R0, R0, #FIQ_Stack_Size - -// Enter IRQ Mode and set its Stack Pointer - MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit - MOV SP, R0 - SUB R0, R0, #IRQ_Stack_Size - -// Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit - MOV SP, R0 - SUB R0, R0, #SVC_Stack_Size - -// Enter User Mode and set its Stack Pointer - MSR CPSR_c, #Mode_USR - MOV SP, R0 - -// Enter the C code - LDR R0,=?C?INIT - TST R0,#1 ; Bit-0 set: INIT is Thumb - LDREQ LR,=exit?A ; ARM Mode - LDRNE LR,=exit?T ; Thumb Mode - BX R0 - ENDP - -PUBLIC exit?A -exit?A PROC CODE32 - B exit?A - ENDP - -PUBLIC exit?T -exit?T PROC CODE16 -exit: B exit?T - ENDP - - - END diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/build/.dont_remove b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/build/.dont_remove deleted file mode 100644 index e69de29bb..000000000 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/build/bin/.dont_remove b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/build/bin/.dont_remove deleted file mode 100644 index e69de29bb..000000000 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/build/lst/.dont_remove b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/build/lst/.dont_remove deleted file mode 100644 index e69de29bb..000000000 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/build/obj/.dont_remove b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/build/obj/.dont_remove deleted file mode 100644 index e69de29bb..000000000 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/demo.Opt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/demo.Opt deleted file mode 100644 index 7eb4b89ee..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/demo.Opt +++ /dev/null @@ -1,56 +0,0 @@ -### uVision2 Project, (C) Keil Software -### Do not modify ! - - cExt (*.c) - aExt (*.s*; *.src; *.a*) - oExt (*.obj) - lExt (*.lib) - tExt (*.txt; *.h; *.inc) - pExt (*.plm) - CppX (*.cpp) - DaveTm { 0,0,0,0,0,0,0,0 } - -Target (Demo), 0x0005 // Tools: '' -GRPOPT 1,(Demo),1,0,0 -GRPOPT 2,(FreeModbus),1,0,0 - -OPTFFF 1,1,1,0,0,0,0,0,<.\demo.c> -OPTFFF 1,2,1,0,0,0,0,0,<.\port\porttimer.c> -OPTFFF 1,3,1,0,0,0,0,0,<.\port\port.c> -OPTFFF 1,4,1,0,0,0,0,0,<.\port\portevent.c> -OPTFFF 1,5,1,0,0,0,0,0,<.\port\portserial.c> -OPTFFF 1,6,2,855638016,0,0,0,0,<.\Startup.s> -OPTFFF 2,7,1,0,0,0,0,0,<..\..\modbus\mb.c> -OPTFFF 2,8,1,0,0,0,0,0,<..\..\modbus\functions\mbutils.c> -OPTFFF 2,9,1,0,0,0,0,0,<..\..\modbus\functions\mbfunccoils.c> -OPTFFF 2,10,1,369098752,0,0,0,0,<..\..\modbus\functions\mbfuncdiag.c> -OPTFFF 2,11,1,0,0,0,0,0,<..\..\modbus\functions\mbfuncdisc.c> -OPTFFF 2,12,1,0,0,0,0,0,<..\..\modbus\functions\mbfuncholding.c> -OPTFFF 2,13,1,0,0,0,0,0,<..\..\modbus\functions\mbfuncinput.c> -OPTFFF 2,14,1,0,0,0,0,0,<..\..\modbus\functions\mbfuncother.c> -OPTFFF 2,15,1,0,0,0,0,0,<..\..\modbus\rtu\mbrtu.c> -OPTFFF 2,16,1,0,0,0,0,0,<..\..\modbus\rtu\mbcrc.c> -OPTFFF 2,17,1,0,0,0,0,0,<..\..\modbus\ascii\mbascii.c> - - -TARGOPT 1, (Demo) - KACLK=12000000 - OPTTT 1,1,1,0 - OPTHX 0,65535,0,0,0 - OPTLX 120,65,8,<.\build\lst\> - OPTOX 16 - OPTLT 1,1,1,0,1,1,0,1,0,0,0,0 - OPTXL 1,1,1,1,1,1,1,0,0 - OPTFL 1,0,1 - OPTBL 0,(Data Sheet) - OPTBL 1,(User Manual) - OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC2148)(SARM.DLL)()(TARMP.DLL)(-pLPC2148) - OPTDBG 48125,0,()()()()()()()()()() (BIN\UL2ARM.DLL)()()() - OPTKEY 0,(UL2ARM)(-U268761108 -O7 -C0 -FO15 -FD40000000 -FC800 -FN1 -FF0LPC_IAP2_512 -FS00 -FL07D000)) - OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(153=-1,-1,-1,-1,0)(154=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(145=-1,-1,-1,-1,0)(147=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(149=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(137=-1,-1,-1,-1,0)(138=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(146=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(141=-1,-1,-1,-1,0)(142=-1,-1,-1,-1,0)(143=-1,-1,-1,-1,0)(144=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0)) - OPTKEY 0,(ARMDBGFLAGS)(-T5F) - OPTDF 0x82 - OPTLE <> - OPTLC <> -EndOpt - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/demo.Uv2 b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/demo.Uv2 deleted file mode 100644 index 36ef5de1f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/demo.Uv2 +++ /dev/null @@ -1,111 +0,0 @@ -### uVision2 Project, (C) Keil Software -### Do not modify ! - -Target (Demo), 0x0005 // Tools: '' - -Group (Demo) -Group (FreeModbus) - -File 1,1,<.\demo.c> 0x0 -File 1,1,<.\port\porttimer.c> 0x0 -File 1,1,<.\port\port.c> 0x0 -File 1,1,<.\port\portevent.c> 0x0 -File 1,1,<.\port\portserial.c> 0x0 -File 1,2,<.\Startup.s> 0x0 -File 2,1,<..\..\modbus\mb.c> 0x0 -File 2,1,<..\..\modbus\functions\mbutils.c> 0x0 -File 2,1,<..\..\modbus\functions\mbfunccoils.c> 0x0 -File 2,1,<..\..\modbus\functions\mbfuncdiag.c> 0x0 -File 2,1,<..\..\modbus\functions\mbfuncdisc.c> 0x0 -File 2,1,<..\..\modbus\functions\mbfuncholding.c> 0x0 -File 2,1,<..\..\modbus\functions\mbfuncinput.c> 0x0 -File 2,1,<..\..\modbus\functions\mbfuncother.c> 0x0 -File 2,1,<..\..\modbus\rtu\mbrtu.c> 0x0 -File 2,1,<..\..\modbus\rtu\mbcrc.c> 0x0 -File 2,1,<..\..\modbus\ascii\mbascii.c> 0x0 - - -Options 1,0,0 // Target 'Demo' - Device (LPC2148) - Vendor (Philips) - Cpu (IRAM(0x40000000-0x40007FFF) IROM(0-0x7FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI)) - FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 38400 1)) - StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code")) - FlashDR (UL2ARM(-U268761108 -O7 -C0 -FO15 -FD40000000 -FC800 -FN1 -FF0LPC_IAP2_512 -FS00 -FL07D000)) - DevID () - Rgf (LPC214X.H) - Mem () - C () - A () - RL () - OH () - DBC_IFX () - DBC_CMS () - DBC_AMS () - DBC_LMS () - UseEnv=0 - EnvBin () - EnvInc () - EnvLib () - EnvReg (Philips\) - OrgReg (Philips\) - TgStat=16 - OutDir (.\build\obj\) - OutName (demo) - GenApp=1 - GenLib=0 - GenHex=0 - Debug=1 - Browse=1 - LstDir (.\build\lst\) - HexSel=0 - MG32K=0 - TGMORE=0 - RunUsr 0 0 <> - RunUsr 1 0 <> - BrunUsr 0 0 <> - BrunUsr 1 0 <> - SVCSID <> - KACPU (ARM7TDMI) - TKAFL { 0,27,183,0,0,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - KIROM { 1,0,0,0,0,0,0,8,0 } - KIRAM { 0,0,0,0,64,0,128,0,0 } - KXRAM { 0,0,0,0,0,0,0,0,0 } - KAOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - KCAFLG { 197,152,20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - KCAMSC () - KCADEF () - KCAUDF () - KCAINC (..\..\modbus\include;..\..\modbus\rtu;..\..\modbus\ascii;.\port) - KAAFLG { 20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - KAAMSC () - KAASET () - KAARST () - KAAINC () - PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - IncBld=1 - AlwaysBuild=0 - GenAsm=0 - AsmAsm=0 - PublicsOnly=0 - StopCode=3 - CustArgs () - LibMods () - KLAFLG { 44,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - KLAMSC () - KLADWN () - KLACFI () - KLAASN () - KLARES () - KLACCL () - KLAUCL () - KLACSC () - KLAUCS () - OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC2148)(SARM.DLL)()(TARMP.DLL)(-pLPC2148) - OPTDBG 48125,0,()()()()()()()()()() (BIN\UL2ARM.DLL)()()() - FLASH1 { 2,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } - FLASH2 (BIN\UL2ARM.DLL) - FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 38400 1)) - FLASH4 () -EndOpt - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/demo.c deleted file mode 100644 index 57b0e81b7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/demo.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * FreeModbus Libary: LPC214X Port - * Copyright (C) 2007 Tiago Prado Lone - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define REG_INPUT_START 1000 -#define REG_INPUT_NREGS 4 - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegInputStart = REG_INPUT_START; -static USHORT usRegInputBuf[REG_INPUT_NREGS]; - -/* ----------------------- Start implementation -----------------------------*/ -int -main( void ) -{ - eMBErrorCode eStatus; - - eStatus = eMBInit( MB_RTU, 0x0A, 0, 38400, MB_PAR_EVEN ); - - /* Enable the Modbus Protocol Stack. */ - eStatus = eMBEnable( ); - - for( ;; ) - { - ( void )eMBPoll( ); - - /* Here we simply count the number of poll cycles. */ - usRegInputBuf[0]++; - } -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode ) -{ - ( void )pucRegBuffer; - ( void )usAddress; - ( void )usNRegs; - ( void )eMode; - return MB_ENOREG; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, eMBRegisterMode eMode ) -{ - ( void )pucRegBuffer; - ( void )usAddress; - ( void )usNCoils; - ( void )eMode; - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - ( void )pucRegBuffer; - ( void )usAddress; - ( void )usNDiscrete; - return MB_ENOREG; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/port/port.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/port/port.c deleted file mode 100644 index 5e3bc66f3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/port/port.c +++ /dev/null @@ -1,42 +0,0 @@ - /* - * FreeModbus Libary: LPC214X Port - * Copyright (C) 2007 Tiago Prado Lone - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes --------------------------------*/ -#include - -/* ----------------------- Modbus includes ----------------------------------*/ - -/* ----------------------- Variables ----------------------------------------*/ -int VIC_Temp; - -/* ----------------------- Start implementation -----------------------------*/ -void -EnterCriticalSection( ) -{ - VIC_Temp = VICIntEnable; /* Save VICIntEnable */ - VICIntEnClr = VIC_Temp; /* Disable Interruptions */ -} - -void -ExitCriticalSection( ) -{ - VICIntEnable = VIC_Temp; /* Restore VICIntEnable */ -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/port/port.h deleted file mode 100644 index 5bf5e5386..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/port/port.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * FreeModbus Libary: BARE Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -#include -#include - -#define INLINE -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#define ENTER_CRITICAL_SECTION( ) EnterCriticalSection( ) -#define EXIT_CRITICAL_SECTION( ) ExitCriticalSection( ) - -#define CCLK 60000000L -#define PCLK CCLK/4 - -void EnterCriticalSection( void ); -void ExitCriticalSection( void ); - -typedef uint8_t BOOL; - -typedef unsigned char UCHAR; -typedef char CHAR; - -typedef uint16_t USHORT; -typedef int16_t SHORT; - -typedef uint32_t ULONG; -typedef int32_t LONG; - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/port/portevent.c deleted file mode 100644 index 3e431c670..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/port/portevent.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * FreeModbus Libary: LPC214X Port - * Copyright (C) 2007 Tiago Prado Lone - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static eMBEventType eQueuedEvent; -static BOOL xEventInQueue; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - xEventInQueue = FALSE; - return TRUE; -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - xEventInQueue = TRUE; - eQueuedEvent = eEvent; - return TRUE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - BOOL xEventHappened = FALSE; - - if( xEventInQueue ) - { - *eEvent = eQueuedEvent; - xEventInQueue = FALSE; - xEventHappened = TRUE; - } - return xEventHappened; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/port/portserial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/port/portserial.c deleted file mode 100644 index b77aa50e9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/port/portserial.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * FreeModbus Libary: LPC214X Port - * Copyright (C) 2007 Tiago Prado Lone - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#include -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- static functions ---------------------------------*/ -static void -sio_irq( void ) - __irq; - static void prvvUARTTxReadyISR( void ); - static void prvvUARTRxISR( void ); - -/* ----------------------- Start implementation -----------------------------*/ - void vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable ) -{ - if( xRxEnable ) - { - U1IER |= 0x01; - } - else - { - U1IER &= ~0x01; - } - if( xTxEnable ) - { - U1IER |= 0x02; - prvvUARTTxReadyISR( ); - } - else - { - U1IER &= ~0x02; - } -} - -void -vMBPortClose( void ) -{ -} - -BOOL -xMBPortSerialInit( UCHAR ucPORT, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity ) -{ - BOOL bInitialized = TRUE; - USHORT cfg = 0; - ULONG reload = ( ( PCLK / ulBaudRate ) / 16UL ); - volatile char dummy; - - ( void )ucPORT; - /* Configure UART1 Pins */ - PINSEL0 = 0x00050000; /* Enable RxD1 and TxD1 */ - - switch ( ucDataBits ) - { - case 5: - break; - - case 6: - cfg |= 0x00000001; - break; - - case 7: - cfg |= 0x00000002; - break; - - case 8: - cfg |= 0x00000003; - break; - - default: - bInitialized = FALSE; - } - - switch ( eParity ) - { - case MB_PAR_NONE: - break; - - case MB_PAR_ODD: - cfg |= 0x00000008; - break; - - case MB_PAR_EVEN: - cfg |= 0x00000018; - break; - } - - if( bInitialized ) - { - U1LCR = cfg; /* Configure Data Bits and Parity */ - U1IER = 0; /* Disable UART1 Interrupts */ - - U1LCR |= 0x80; /* Set DLAB */ - U1DLL = reload; /* Set Baud */ - U1DLM = reload >> 8; /* Set Baud */ - U1LCR &= ~0x80; /* Clear DLAB */ - - /* Configure UART1 Interrupt */ - VICVectAddr0 = ( unsigned long )sio_irq; - VICVectCntl0 = 0x20 | 7; - VICIntEnable = 1 << 7; /* Enable UART1 Interrupt */ - - dummy = U1IIR; /* Required to Get Interrupts Started */ - } - - return bInitialized; -} - -BOOL -xMBPortSerialPutByte( CHAR ucByte ) -{ - U1THR = ucByte; - - /* Wait till U0THR and U0TSR are both empty */ - while( !( U1LSR & 0x20 ) ) - { - } - - return TRUE; -} - -BOOL -xMBPortSerialGetByte( CHAR * pucByte ) -{ - while( !( U1LSR & 0x01 ) ) - { - } - - /* Receive Byte */ - *pucByte = U1RBR; - - return TRUE; -} - - -void -sio_irq( void ) - __irq -{ - volatile char dummy; - volatile char IIR; - - while( ( ( IIR = U1IIR ) & 0x01 ) == 0 ) - { - switch ( IIR & 0x0E ) - { - case 0x06: /* Receive Line Status */ - dummy = U1LSR; /* Just clear the interrupt source */ - break; - - case 0x04: /* Receive Data Available */ - case 0x0C: /* Character Time-Out */ - prvvUARTRxISR( ); - break; - - case 0x02: /* THRE Interrupt */ - prvvUARTTxReadyISR( ); - break; - - case 0x00: /* Modem Interrupt */ - dummy = U1MSR; /* Just clear the interrupt source */ - break; - - default: - break; - } - } - - VICVectAddr = 0xFF; /* Acknowledge Interrupt */ -} - - -/* - * Create an interrupt handler for the transmit buffer empty interrupt - * (or an equivalent) for your target processor. This function should then - * call pxMBFrameCBTransmitterEmpty( ) which tells the protocol stack that - * a new character can be sent. The protocol stack will then call - * xMBPortSerialPutByte( ) to send the character. - */ -static void -prvvUARTTxReadyISR( void ) -{ - pxMBFrameCBTransmitterEmpty( ); -} - -/* - * Create an interrupt handler for the receive interrupt for your target - * processor. This function should then call pxMBFrameCBByteReceived( ). The - * protocol stack will then call xMBPortSerialGetByte( ) to retrieve the - * character. - */ -static void -prvvUARTRxISR( void ) -{ - pxMBFrameCBByteReceived( ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/port/porttimer.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/port/porttimer.c deleted file mode 100644 index e73e0b2f3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/LPC214X/port/porttimer.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * FreeModbus Libary: LPC214X Port - * Copyright (C) 2007 Tiago Prado Lone - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Platform includes --------------------------------*/ -#include -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- static functions ---------------------------------*/ -static void -prvvTIMERExpiredISR( void ) - __irq; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortTimersInit( USHORT usTim1Timerout50us ) -{ - // Timer0 Configuration - T0PR = 0; // Prscaler Register = 0 - T0PC = 0; // Prscaler Counter = 0 - - T0TC = 0; // Timer Counter = 0 - - T0MR0 = ( PCLK / 20000 ) * usTim1Timerout50us; // Interval of (50us * usTim1Timerout50us) - T0MCR = 3; // Bit 0 = 1 - Interruption on MR0 - // Bit 1 = 1 - Reset on MR0 - - T0TCR = 0; // Timer Counter and Prescale Counter Disabled - - // Configure Timer0 Interruption - VICVectAddr1 = ( unsigned int )prvvTIMERExpiredISR; // Timer0 Interruption - Priority 1 - VICVectCntl1 = 0x20 | 4; - VICIntEnable = ( 1 << 4 ); // Enable Timer0 Interruption - - return TRUE; -} - - -void -vMBPortTimersEnable( ) -{ - T0TCR = 0x02; // Disable Timer and Reset Counter - T0TCR = 0x01; // Enable Timer -} - -void -vMBPortTimersDisable( ) -{ - T0TCR = 0x02; // Disable Timer and Reset Counter -} - -static void -prvvTIMERExpiredISR( void ) - __irq -{ - ( void )pxMBPortCBTimerExpired( ); - - T0IR = 0xFF; - VICVectAddr = 0xFF; // Acknowledge Interrupt -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/Makefile b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/Makefile deleted file mode 100644 index 8b6556e1b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/Makefile +++ /dev/null @@ -1,74 +0,0 @@ -# -# FreeModbus MCF5235 port- Makefile -# -# Copyright (c) 2006 Christian Walter, Vienna 2006. -# -# $Id: Makefile,v 1.2 2006/08/30 23:18:06 wolti Exp $ -# -# --------------------------------------------------------------------------- - -BASE = /opt/gcc-m68k/bin -CC = $(BASE)/m68k-elf-gcc -CXX = $(BASE)/m68k-elf-g++ -OBJCOPY = $(BASE)/m68k-elf-objcopy -INSIGHT = $(BASE)/m68k-bdm-elf-insight - -CFLAGS = -MD -gdwarf-2 -g3 -m528x -Wall \ - -Imcf523x -Iport -I../../modbus/rtu \ - -I../../modbus/ascii -I../../modbus/include \ - -D'__IPSBAR=((vuint8 *) 0x40000000)' \ - -D'FCPU=25000000UL' -ASFLAGS = -MD -gdwarf-2 -g3 -m528x -Wa,--register-prefix-optional -LDSCRIPT = m5235-ram.ld -LDFLAGS = -nostartfiles -m528x -Wl,--script=$(LDSCRIPT) - -TGT = demo -OTHER_CSRC = -OTHER_ASRC = vector.S crt0.S -CSRC = demo.c init.c port/portserial.c port/portother.c \ - port/portevent.c port/porttimer.c \ - ../../modbus/mb.c \ - ../../modbus/rtu/mbrtu.c ../../modbus/rtu/mbcrc.c \ - ../../modbus/ascii/mbascii.c \ - ../../modbus/functions/mbfunccoils.c \ - ../../modbus/functions/mbfuncdiag.c \ - ../../modbus/functions/mbfuncholding.c \ - ../../modbus/functions/mbfuncinput.c \ - ../../modbus/functions/mbfuncother.c \ - ../../modbus/functions/mbfuncdisc.c \ - ../../modbus/functions/mbutils.c -ASRC = -OBJS = $(CSRC:.c=.o) $(ASRC:.S=.o) -NOLINK_OBJS = $(OTHER_CSRC:.c=.o) $(OTHER_ASRC:.S=.o) -DEPS = $(OBJS:.o=.d) $(NOLINK_OBJS:.o=.d) -BIN = $(TGT).elf - -.PHONY: clean all - -all: $(BIN) - -debug: - $(INSIGHT) --command=support/m5235.gdb --se=$(TGT).elf - -$(BIN): $(OBJS) $(NOLINK_OBJS) - $(CC) $(LDFLAGS) -Wl,-Map=$(TGT).map $(OBJS) $(LDLIBS) -o $@ - -clean: - rm -f $(DEPS) - rm -f $(OBJS) $(NOLINK_OBJS) - rm -f $(BIN) $(TGT).map - -# --------------------------------------------------------------------------- -# rules for code generation -# --------------------------------------------------------------------------- -%.o: %.c - $(CC) $(CFLAGS) -o $@ -c $< - -%.o: %.S - $(CC) $(ASFLAGS) -o $@ -c $< - -# --------------------------------------------------------------------------- -# # compiler generated dependencies -# --------------------------------------------------------------------------- --include $(LWOS_DEPS) $(PORT_DEPS) $(APPL_DEPS) - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/crt0.S b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/crt0.S deleted file mode 100644 index ed553a806..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/crt0.S +++ /dev/null @@ -1,80 +0,0 @@ -/* - * FreeModbus Libary: MCF5235 Demo Application - * Copyright (C) 2006 Christian Walter - * Parts of crt0.S Copyright (c) 1995, 1996, 1998 Cygnus Support - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id: crt0.S,v 1.1 2006/05/14 21:59:16 wolti Exp $ - */ - - .title "crt0.S" - - .extern main - .extern __stack - .extern __bss_start - .extern __text_start - .extern init_main - .global start - -start: - /* disable all interrupts on startup. */ - move.w #0x2700, sr - - /* prepare internal SRAM. */ - move.l #__text_start, %d0 - addq.l #1, %d0 - movec %d0, %rambar - - /* prepare stack and frame pointer. */ - move.l #__stack, sp - link a6, #-8 - - /* initialize hardware. */ - jsr init_main - - /* zero out the bss section. */ - move.l #__bss_start, d1 - move.l #_end, d0 - cmp.l d0, d1 - jbeq 3f - move.l d1, a0 - sub.l d1, d0 - subq.l #1, d0 -2: - clr.b (a0)+ - subq.l #1, d0 - jbpl 2b -3: - - /* C library */ - move.l #__FINI_SECTION__, -(%sp) - jsr atexit - jsr __INIT_SECTION__ - - /* enable interrupts. */ - move.w #0x2000, sr - - /* call main(int argc, char *argv[] */ - move.l #0, -(sp) - move.l #0, -(sp) - move.l #0, -(sp) - jsr main - lea (sp, 12), %sp - - /* stop on exit from main. */ -1: - halt - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/demo.c deleted file mode 100644 index adf2c2931..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/demo.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * FreeModbus Libary: MCF5235 Demo Application - * Copyright (C) 2006 Christian Walter - * Parts of crt0.S Copyright (c) 1995, 1996, 1998 Cygnus Support - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#include "mcf5xxx.h" -#include "mcf523x.h" - -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define REG_INPUT_START 1000 -#define REG_INPUT_NREGS 4 - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegInputStart = REG_INPUT_START; -static USHORT usRegInputBuf[REG_INPUT_NREGS]; - - -int -main( int argc, char *argv[], char *envp[] ) -{ - //xMBPortSerialInit (9600UL, 8, MB_PAR_EVEN); - //vMBPortSerialEnable (TRUE , FALSE); - //xMBPortTimersInit( 200 ); - //vMBPortTimersEnable(); - // - const UCHAR ucSlaveID[] = { 0xAA, 0xBB, 0xCC }; - eMBErrorCode eStatus; - - eStatus = eMBInit( MB_RTU, 0x0A, 0, 38400, MB_PAR_EVEN ); - - eStatus = eMBSetSlaveID( 0x34, TRUE, ucSlaveID, 3 ); - - /* Enable the Modbus Protocol Stack. */ - eStatus = eMBEnable( ); - - for( ;; ) - { - ( void )eMBPoll( ); - - /* Here we simply count the number of poll cycles. */ - usRegInputBuf[0]++; - } - return 0; -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = - ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = - ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, - eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, - eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/init.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/init.c deleted file mode 100644 index 17e6830df..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/init.c +++ /dev/null @@ -1,683 +0,0 @@ - /* - * FreeModbus Libary: MCF5235 Demo Application - * Copyright (C) 2006 Christian Walter - * Parts of crt0.S Copyright (c) 1995, 1996, 1998 Cygnus Support - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#include "mcf5xxx.h" -#include "mcf523x.h" - -/* Function prototypes */ -void init_main( void ); -static void disable_interrupts( void ); -static void disable_watchdog_timer( void ); -static void disable_cache( void ); -static void init_ipsbar( void ); -static void init_basics( void ); -static void init_clock_config( void ); -static void init_chip_selects( void ); -static void init_bus_config( void ); -static void init_cache( void ); -static void init_eport( void ); -static void init_flexcan( void ); -static void init_power_management( void ); -static void init_dma_timers( void ); -static void init_interrupt_timers( void ); -static void init_watchdog_timers( void ); -static void init_pin_assignments( void ); -static void init_sdram_controller( void ); -static void init_interrupt_controller( void ); - -/********************************************************************* -* init_main - Main entry point for initialisation code * -**********************************************************************/ -void -init_main( void ) -{ - /* Initialise base address of peripherals, VBR, etc */ - init_ipsbar( ); - init_basics( ); - init_clock_config( ); - - /* Disable interrupts, watchdog timer, cache */ - disable_interrupts( ); - disable_watchdog_timer( ); - disable_cache( ); - - /* Initialise individual modules */ - init_chip_selects( ); - init_bus_config( ); - init_cache( ); - init_eport( ); - init_flexcan( ); - init_power_management( ); - init_dma_timers( ); - init_interrupt_timers( ); - init_watchdog_timers( ); - init_pin_assignments( ); - init_sdram_controller( ); - - /* Initialise interrupt controller */ - init_interrupt_controller( ); -} - -/********************************************************************* -* disable_interrupts - Disable all interrupt sources * -**********************************************************************/ -static void -disable_interrupts( void ) -{ - vuint8 *p; - int i; - - /* Set ICR008-ICR063 to 0x0 */ - p = ( vuint8 * ) & MCF_INTC0_ICR8; - for( i = 8; i <= 63; i++ ) - *p++ = 0x0; - - /* Set ICR108-ICR163 to 0x0 */ - p = ( vuint8 * ) & MCF_INTC1_ICR8; - for( i = 108; i <= 163; i++ ) - *p++ = 0x0; -} - -/********************************************************************* -* disable_watchdog_timer - Disable system watchdog timer * -**********************************************************************/ -static void -disable_watchdog_timer( void ) -{ - /* Disable Core Watchdog Timer */ - MCF_SCM_CWCR = 0; -} - -/********************************************************************* -* disable_cache - Disable and invalidate cache * -**********************************************************************/ -static void -disable_cache( void ) -{ - asm( "move.l #0x01000000,%d0" ); - asm( "movec %d0,%cacr" ); -} - -/********************************************************************* -* init_basics - Configuration Information & VBR * -**********************************************************************/ -static void -init_basics( void ) -{ - extern void ramvec_start; - extern void romvec_start; - - /* Transfer size not driven on SIZ[1:0] pins during external cycles - Processor Status (PST) and Debug Data (DDATA) functions disabled - Bus monitor disabled - Output pads configured for full strength - */ - MCF_CCM_CCR = ( 0x1 << 15 ) | MCF_CCM_CCR_BME; - - /* Exception vector table at $00000000 */ - asm( "move.l %0,%%d0": :"i"( &romvec_start ) ); - asm( "movec %d0,%vbr" ); -} - -/********************************************************************* -* init_clock_config - Clock Module * -**********************************************************************/ -static void -init_clock_config( void ) -{ - /* Clock module uses normal PLL mode with 25.0000 MHz external reference (Fref) - MFD = 0, RFD = 1 - Bus clock frequency = 25.00 MHz - Processor clock frequency = 2 x bus clock = 50.00 MHz - Frequency Modulation disabled - Loss of clock detection disabled - Reset/Interrupt on loss of lock disabled - */ - - MCF_FMPLL_SYNCR = 0x00100000; /* Set RFD=RFD+1 to avoid frequency overshoot */ - while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */ - ; - MCF_FMPLL_SYNCR = 0x00080000; /* Set desired RFD */ - while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */ - ; -} - -/********************************************************************* -* init_ipsbar - Internal Peripheral System Base Address (IPSBAR) * -**********************************************************************/ -static void -init_ipsbar( void ) -{ - /* Base address of internal peripherals (IPSBAR) = 0x40000000 - - Note: Processor powers up with IPS base address = 0x40000000 - Write to IPS base + 0x00000000 to set new value - */ - *( vuint32 * ) 0x40000000 = ( vuint32 ) __IPSBAR + 1; /* +1 for Enable */ -} - -/********************************************************************* -* init_chip_selects - Chip Select Module * -**********************************************************************/ -static void -init_chip_selects( void ) -{ - /* Chip Select 0 disabled (CSMR0[V] = 0) */ - MCF_CS_CSAR0 = 0; - MCF_CS_CSMR0 = 0; - MCF_CS_CSCR0 = MCF_CS_CSCR_IWS( 0xf ) | MCF_CS_CSCR_AA; - - /* Chip Select 1 disabled (CSMR1[V] = 0) */ - MCF_CS_CSAR1 = 0; - MCF_CS_CSMR1 = 0; - MCF_CS_CSCR1 = 0; - - /* Chip Select 2 disabled (CSMR2[V] = 0) */ - MCF_CS_CSAR2 = 0; - MCF_CS_CSMR2 = 0; - MCF_CS_CSCR2 = 0; - - /* Chip Select 3 disabled (CSMR3[V] = 0) */ - MCF_CS_CSAR3 = 0; - MCF_CS_CSMR3 = 0; - MCF_CS_CSCR3 = 0; - - /* Chip Select 4 disabled (CSMR4[V] = 0) */ - MCF_CS_CSAR4 = 0; - MCF_CS_CSMR4 = 0; - MCF_CS_CSCR4 = 0; - - /* Chip Select 5 disabled (CSMR5[V] = 0) */ - MCF_CS_CSAR5 = 0; - MCF_CS_CSMR5 = 0; - MCF_CS_CSCR5 = 0; - - /* Chip Select 6 disabled (CSMR6[V] = 0) */ - MCF_CS_CSAR6 = 0; - MCF_CS_CSMR6 = 0; - MCF_CS_CSCR6 = 0; - - /* Chip Select 7 disabled (CSMR7[V] = 0) */ - MCF_CS_CSAR7 = 0; - MCF_CS_CSMR7 = 0; - MCF_CS_CSCR7 = 0; -} - -/********************************************************************* -* init_bus_config - Internal Bus Arbitration * -**********************************************************************/ -static void -init_bus_config( void ) -{ - /* Use round robin arbitration scheme - Assigned priorities (highest first): - Ethernet - DMA Controller - ColdFire Core - DMA bandwidth control disabled - Park on last active bus master - */ - MCF_SCM_MPARK = MCF_SCM_MPARK_M3_PRTY( 0x3 ) | - MCF_SCM_MPARK_M2_PRTY( 0x2 ) | MCF_SCM_MPARK_M1_PRTY( 0x1 ); -} - -/********************************************************************* -* init_cache - Instruction/Data Cache * -**********************************************************************/ -static void -init_cache( void ) -{ - /* Instruction/Data cache disabled */ - asm( "move.l #0x00000000, %d0" ); - asm( "movec %d0,%cacr" ); -} - -/********************************************************************* -* init_eport - Edge Port Module (EPORT) * -**********************************************************************/ -static void -init_eport( void ) -{ - /* Pins 1-7 configured as GPIO inputs */ - MCF_EPORT_EPPAR = 0; - MCF_EPORT_EPDDR = 0; - MCF_EPORT_EPIER = 0; -} - -/********************************************************************* -* init_flexcan - FlexCAN Module * -**********************************************************************/ -static void -init_flexcan( void ) -{ - /* FlexCAN controller 0 disabled (CANMCR0[MDIS]=1) */ - MCF_CAN_IMASK0 = 0; - MCF_CAN_RXGMASK0 = MCF_CAN_RXGMASK_MI( 0x1fffffff ); - MCF_CAN_RX14MASK0 = MCF_CAN_RX14MASK_MI( 0x1fffffff ); - MCF_CAN_RX15MASK0 = MCF_CAN_RX15MASK_MI( 0x1fffffff ); - MCF_CAN_CANCTRL0 = 0; - MCF_CAN_CANMCR0 = MCF_CAN_CANMCR_MDIS | - MCF_CAN_CANMCR_FRZ | - MCF_CAN_CANMCR_HALT | - MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf ); - - /* FlexCAN controller 1 disabled (CANMCR1[MDIS]=1) */ - MCF_CAN_IMASK1 = 0; - MCF_CAN_RXGMASK1 = MCF_CAN_RXGMASK_MI( 0x1fffffff ); - MCF_CAN_RX14MASK1 = MCF_CAN_RX14MASK_MI( 0x1fffffff ); - MCF_CAN_RX15MASK1 = MCF_CAN_RX15MASK_MI( 0x1fffffff ); - MCF_CAN_CANCTRL1 = 0; - MCF_CAN_CANMCR1 = MCF_CAN_CANMCR_MDIS | - MCF_CAN_CANMCR_FRZ | - MCF_CAN_CANMCR_HALT | - MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf ); -} - -/********************************************************************* -* init_power_management - Power Management * -**********************************************************************/ -static void -init_power_management( void ) -{ - /* On executing STOP instruction, processor enters RUN mode - Mode is exited when an interrupt of level 1 or higher is received - */ - MCF_SCM_LPICR = MCF_SCM_LPICR_ENBSTOP; - MCF_CCM_LPCR = 0; -} - -/********************************************************************* -* init_sdram_controller - SDRAM Controller * -**********************************************************************/ -static void -init_sdram_controller( void ) -{ - /* DRAM type is Synchronous (SDRAM) - SDRAM refresh timings: - Number of clocks spent in refresh state = 3 - Refresh count = 511 (Refresh every 327.68 microseconds at 25.0 MHz bus clock) - */ - MCF_SDRAMC_DCR = MCF_SDRAMC_DCR_RC( 0x1ff ); - - /* Memory block 0 not in use (DMR0[V] = 0) */ - MCF_SDRAMC_DMR0 = MCF_SDRAMC_DMR_BAM_256K; - MCF_SDRAMC_DACR0 = 0; - - /* Memory block 1 not in use (DMR1[V] = 0) */ - MCF_SDRAMC_DMR1 = MCF_SDRAMC_DMR_BAM_256K; - MCF_SDRAMC_DACR1 = 0; -} - -/********************************************************************* -* init_dma_timers - DMA Timer Modules * -**********************************************************************/ -static void -init_dma_timers( void ) -{ - /* DMA Timer 0 disabled (DTMR0[RST] = 0) */ - MCF_TIMER_DTMR0 = 0; - MCF_TIMER_DTXMR0 = 0; - MCF_TIMER_DTRR0 = 0xffffffff; - - /* DMA Timer 1 disabled (DTMR1[RST] = 0) */ - MCF_TIMER_DTMR1 = 0; - MCF_TIMER_DTXMR1 = 0; - MCF_TIMER_DTRR1 = 0xffffffff; - - /* DMA Timer 2 disabled (DTMR2[RST] = 0) */ - MCF_TIMER_DTMR2 = 0; - MCF_TIMER_DTXMR2 = 0; - MCF_TIMER_DTRR2 = 0xffffffff; - - /* DMA Timer 3 disabled (DTMR3[RST] = 0) */ - MCF_TIMER_DTMR3 = 0; - MCF_TIMER_DTXMR3 = 0; - MCF_TIMER_DTRR3 = 0xffffffff; -} - -/********************************************************************** -* init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules * -***********************************************************************/ -static void -init_interrupt_timers( void ) -{ - /* PIT0 disabled (PCSR0[EN]=0) */ - MCF_PIT_PCSR0 = 0; - - /* PIT1 disabled (PCSR1[EN]=0) */ - MCF_PIT_PCSR1 = 0; - - /* PIT2 disabled (PCSR2[EN]=0) */ - MCF_PIT_PCSR2 = 0; - - /* PIT3 disabled (PCSR3[EN]=0) */ - MCF_PIT_PCSR3 = 0; -} - -/********************************************************************* -* init_watchdog_timers - Watchdog Timer Modules * -**********************************************************************/ -static void -init_watchdog_timers( void ) -{ - /* Watchdog Timer disabled (WCR[EN]=0) - NOTE: WCR and WMR cannot be written again until after the - processor is reset. - */ - MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED; - MCF_WTM_WMR = 0xffff; - - /* Core Watchdog Timer disabled (CWCR[CWE]=0) */ - MCF_SCM_CWCR = 0; -} - -/********************************************************************* -* init_interrupt_controller - Interrupt Controller * -**********************************************************************/ -static void -init_interrupt_controller( void ) -{ - /* Configured interrupt sources in order of priority... - Level 7: External interrupt /IRQ7, (initially masked) - Level 6: External interrupt /IRQ6, (initially masked) - Level 5: External interrupt /IRQ5, (initially masked) - Level 4: External interrupt /IRQ4, (initially masked) - Level 3: External interrupt /IRQ3, (initially masked) - Level 2: External interrupt /IRQ2, (initially masked) - Level 1: External interrupt /IRQ1, (initially masked) - */ - MCF_INTC0_ICR1 = 0; - MCF_INTC0_ICR2 = 0; - MCF_INTC0_ICR3 = 0; - MCF_INTC0_ICR4 = 0; - MCF_INTC0_ICR5 = 0; - MCF_INTC0_ICR6 = 0; - MCF_INTC0_ICR7 = 0; - MCF_INTC0_ICR8 = 0; - MCF_INTC0_ICR9 = 0; - MCF_INTC0_ICR10 = 0; - MCF_INTC0_ICR11 = 0; - MCF_INTC0_ICR12 = 0; - MCF_INTC0_ICR13 = 0; - MCF_INTC0_ICR14 = 0; - MCF_INTC0_ICR15 = 0; - MCF_INTC0_ICR17 = 0; - MCF_INTC0_ICR18 = 0; - MCF_INTC0_ICR19 = 0; - MCF_INTC0_ICR20 = 0; - MCF_INTC0_ICR21 = 0; - MCF_INTC0_ICR22 = 0; - MCF_INTC0_ICR23 = 0; - MCF_INTC0_ICR24 = 0; - MCF_INTC0_ICR25 = 0; - MCF_INTC0_ICR26 = 0; - MCF_INTC0_ICR27 = 0; - MCF_INTC0_ICR28 = 0; - MCF_INTC0_ICR29 = 0; - MCF_INTC0_ICR30 = 0; - MCF_INTC0_ICR31 = 0; - MCF_INTC0_ICR32 = 0; - MCF_INTC0_ICR33 = 0; - MCF_INTC0_ICR34 = 0; - MCF_INTC0_ICR35 = 0; - MCF_INTC0_ICR36 = 0; - MCF_INTC0_ICR37 = 0; - MCF_INTC0_ICR38 = 0; - MCF_INTC0_ICR39 = 0; - MCF_INTC0_ICR40 = 0; - MCF_INTC0_ICR41 = 0; - MCF_INTC0_ICR42 = 0; - MCF_INTC0_ICR43 = 0; - MCF_INTC0_ICR44 = 0; - MCF_INTC0_ICR45 = 0; - MCF_INTC0_ICR46 = 0; - MCF_INTC0_ICR47 = 0; - MCF_INTC0_ICR48 = 0; - MCF_INTC0_ICR49 = 0; - MCF_INTC0_ICR50 = 0; - MCF_INTC0_ICR51 = 0; - MCF_INTC0_ICR52 = 0; - MCF_INTC0_ICR53 = 0; - MCF_INTC0_ICR54 = 0; - MCF_INTC0_ICR55 = 0; - MCF_INTC0_ICR56 = 0; - MCF_INTC0_ICR57 = 0; - MCF_INTC0_ICR58 = 0; - MCF_INTC0_ICR59 = 0; - MCF_INTC0_ICR60 = 0; - MCF_INTC1_ICR8 = 0; - MCF_INTC1_ICR9 = 0; - MCF_INTC1_ICR10 = 0; - MCF_INTC1_ICR11 = 0; - MCF_INTC1_ICR12 = 0; - MCF_INTC1_ICR13 = 0; - MCF_INTC1_ICR14 = 0; - MCF_INTC1_ICR15 = 0; - MCF_INTC1_ICR16 = 0; - MCF_INTC1_ICR17 = 0; - MCF_INTC1_ICR18 = 0; - MCF_INTC1_ICR19 = 0; - MCF_INTC1_ICR20 = 0; - MCF_INTC1_ICR21 = 0; - MCF_INTC1_ICR22 = 0; - MCF_INTC1_ICR23 = 0; - MCF_INTC1_ICR24 = 0; - MCF_INTC1_ICR25 = 0; - MCF_INTC1_ICR27 = 0; - MCF_INTC1_ICR28 = 0; - MCF_INTC1_ICR29 = 0; - MCF_INTC1_ICR30 = 0; - MCF_INTC1_ICR31 = 0; - MCF_INTC1_ICR32 = 0; - MCF_INTC1_ICR33 = 0; - MCF_INTC1_ICR34 = 0; - MCF_INTC1_ICR35 = 0; - MCF_INTC1_ICR36 = 0; - MCF_INTC1_ICR37 = 0; - MCF_INTC1_ICR38 = 0; - MCF_INTC1_ICR39 = 0; - MCF_INTC1_ICR40 = 0; - MCF_INTC1_ICR41 = 0; - MCF_INTC1_ICR42 = 0; - MCF_INTC1_ICR59 = 0; - MCF_INTC0_IMRH = 0xffffffff; - MCF_INTC0_IMRL = MCF_INTC0_IMRL_INT_MASK31 | - MCF_INTC0_IMRL_INT_MASK30 | - MCF_INTC0_IMRL_INT_MASK29 | - MCF_INTC0_IMRL_INT_MASK28 | - MCF_INTC0_IMRL_INT_MASK27 | - MCF_INTC0_IMRL_INT_MASK26 | - MCF_INTC0_IMRL_INT_MASK25 | - MCF_INTC0_IMRL_INT_MASK24 | - MCF_INTC0_IMRL_INT_MASK23 | - MCF_INTC0_IMRL_INT_MASK22 | - MCF_INTC0_IMRL_INT_MASK21 | - MCF_INTC0_IMRL_INT_MASK20 | - MCF_INTC0_IMRL_INT_MASK19 | - MCF_INTC0_IMRL_INT_MASK18 | - MCF_INTC0_IMRL_INT_MASK17 | - MCF_INTC0_IMRL_INT_MASK16 | - MCF_INTC0_IMRL_INT_MASK15 | - MCF_INTC0_IMRL_INT_MASK14 | - MCF_INTC0_IMRL_INT_MASK13 | - MCF_INTC0_IMRL_INT_MASK12 | - MCF_INTC0_IMRL_INT_MASK11 | - MCF_INTC0_IMRL_INT_MASK10 | - MCF_INTC0_IMRL_INT_MASK9 | - MCF_INTC0_IMRL_INT_MASK8 | - MCF_INTC0_IMRL_INT_MASK7 | - MCF_INTC0_IMRL_INT_MASK6 | - MCF_INTC0_IMRL_INT_MASK5 | - MCF_INTC0_IMRL_INT_MASK4 | - MCF_INTC0_IMRL_INT_MASK3 | - MCF_INTC0_IMRL_INT_MASK2 | MCF_INTC0_IMRL_INT_MASK1; - MCF_INTC1_IMRH = 0xffffffff; - MCF_INTC1_IMRL = MCF_INTC1_IMRL_INT_MASK31 | - MCF_INTC1_IMRL_INT_MASK30 | - MCF_INTC1_IMRL_INT_MASK29 | - MCF_INTC1_IMRL_INT_MASK28 | - MCF_INTC1_IMRL_INT_MASK27 | - MCF_INTC1_IMRL_INT_MASK26 | - MCF_INTC1_IMRL_INT_MASK25 | - MCF_INTC1_IMRL_INT_MASK24 | - MCF_INTC1_IMRL_INT_MASK23 | - MCF_INTC1_IMRL_INT_MASK22 | - MCF_INTC1_IMRL_INT_MASK21 | - MCF_INTC1_IMRL_INT_MASK20 | - MCF_INTC1_IMRL_INT_MASK19 | - MCF_INTC1_IMRL_INT_MASK18 | - MCF_INTC1_IMRL_INT_MASK17 | - MCF_INTC1_IMRL_INT_MASK16 | - MCF_INTC1_IMRL_INT_MASK15 | - MCF_INTC1_IMRL_INT_MASK14 | - MCF_INTC1_IMRL_INT_MASK13 | - MCF_INTC1_IMRL_INT_MASK12 | - MCF_INTC1_IMRL_INT_MASK11 | - MCF_INTC1_IMRL_INT_MASK10 | - MCF_INTC1_IMRL_INT_MASK9 | - MCF_INTC1_IMRL_INT_MASK8 | - MCF_INTC1_IMRL_INT_MASK7 | - MCF_INTC1_IMRL_INT_MASK6 | - MCF_INTC1_IMRL_INT_MASK5 | - MCF_INTC1_IMRL_INT_MASK4 | - MCF_INTC1_IMRL_INT_MASK3 | - MCF_INTC1_IMRL_INT_MASK2 | MCF_INTC1_IMRL_INT_MASK1; -} - -/********************************************************************* -* init_pin_assignments - Pin Assignment and General Purpose I/O * -**********************************************************************/ -static void -init_pin_assignments( void ) -{ - /* Pin assignments for port ADDR - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_APDDR = 0; - MCF_GPIO_PAR_AD = 0; - - /* Pin assignments for ports DATAH and DATAL - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_DATAH = 0; - MCF_GPIO_PDDR_DATAL = 0; - - /* Pin assignments for port BUSCTL - Pin /OE : External bus output enable, /OE - Pin /TA : External bus transfer acknowledge, /TA - Pin /TEA : External bus transfer error acknowledge, /TEA - Pin R/W : External bus read/write indication, R/W - Pin TSIZ1 : External bus transfer size TSIZ1 or DMA acknowledge /DACK1 - Pin TSIZ0 : External bus transfer size TSIZ0 or DMA acknowledge /DACK0 - Pin /TS : External bus transfer start, /TS - Pin /TIP : External bus transfer in progess, /TIP - */ - MCF_GPIO_PDDR_BUSCTL = 0; - MCF_GPIO_PAR_BUSCTL = MCF_GPIO_PAR_BUSCTL_PAR_OE | - MCF_GPIO_PAR_BUSCTL_PAR_TA | - MCF_GPIO_PAR_BUSCTL_PAR_TEA( 0x3 ) | - MCF_GPIO_PAR_BUSCTL_PAR_RWB | - MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 | - MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 | - MCF_GPIO_PAR_BUSCTL_PAR_TS( 0x3 ) | - MCF_GPIO_PAR_BUSCTL_PAR_TIP( 0x3 ); - - /* Pin assignments for port BS - Pin /BS3 : External byte strobe /BS3 - Pin /BS2 : External byte strobe /BS2 - Pin /BS1 : External byte strobe /BS1 - Pin /BS0 : External byte strobe /BS0 - */ - MCF_GPIO_PDDR_BS = 0; - MCF_GPIO_PAR_BS = MCF_GPIO_PAR_BS_PAR_BS3 | - MCF_GPIO_PAR_BS_PAR_BS2 | - MCF_GPIO_PAR_BS_PAR_BS1 | MCF_GPIO_PAR_BS_PAR_BS0; - - /* Pin assignments for port CS - Pin /CS7 : Chip select /CS7 - Pin /CS6 : Chip select /CS6 - Pin /CS5 : Chip select /CS5 - Pin /CS4 : Chip select /CS4 - Pin /CS3 : Chip select /CS3 - Pin /CS2 : Chip select /CS2 - Pin /CS1 : Chip select /CS1 - */ - MCF_GPIO_PDDR_CS = 0; - MCF_GPIO_PAR_CS = MCF_GPIO_PAR_CS_PAR_CS7 | - MCF_GPIO_PAR_CS_PAR_CS6 | - MCF_GPIO_PAR_CS_PAR_CS5 | - MCF_GPIO_PAR_CS_PAR_CS4 | - MCF_GPIO_PAR_CS_PAR_CS3 | - MCF_GPIO_PAR_CS_PAR_CS2 | MCF_GPIO_PAR_CS_PAR_CS1; - - /* Pin assignments for port SDRAM - Pin /SD_WE : SDRAM controller /SD_WE - Pin /SD_SCAS : SDRAM controller /SD_SCAS - Pin /SD_SRAS : SDRAM controller /SD_SRAS - Pin /SD_SCKE : SDRAM controller /SD_SCKE - Pin /SD_CS1 : SDRAM controller /SD_CS1 - Pin /SD_CS0 : SDRAM controller /SD_CS0 - */ - MCF_GPIO_PDDR_SDRAM = 0; - MCF_GPIO_PAR_SDRAM = MCF_GPIO_PAR_SDRAM_PAR_SDWE | - MCF_GPIO_PAR_SDRAM_PAR_SCAS | - MCF_GPIO_PAR_SDRAM_PAR_SRAS | - MCF_GPIO_PAR_SDRAM_PAR_SCKE | - MCF_GPIO_PAR_SDRAM_PAR_SDCS1 | MCF_GPIO_PAR_SDRAM_PAR_SDCS0; - - /* Pin assignments for port FECI2C - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_FECI2C = 0; - MCF_GPIO_PAR_FECI2C = 0; - - /* Pin assignments for port UARTL - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_UARTL = 0; - MCF_GPIO_PAR_UART = 0; - - /* Pin assignments for port UARTH - Pin U2TXD : GPIO input - Pin U2RXD : GPIO input - Pin /IRQ2 : Interrupt request /IRQ2 or GPIO - */ - MCF_GPIO_PDDR_UARTH = 0; - - /* Pin assignments for port QSPI - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_QSPI = 0; - MCF_GPIO_PAR_QSPI = 0; - - /* Pin assignments for port TIMER - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_TIMER = 0; - MCF_GPIO_PAR_TIMER = 0; - - /* Pin assignments for port ETPU - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_ETPU = 0; - MCF_GPIO_PAR_ETPU = 0; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/m5235-ram.ld b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/m5235-ram.ld deleted file mode 100644 index 9f3a2b56b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/m5235-ram.ld +++ /dev/null @@ -1,104 +0,0 @@ -STARTUP(crt0.o) -INPUT(vector.o) -OUTPUT_ARCH(m68k) -SEARCH_DIR(.) -GROUP(-lc -lgcc) - -__DYNAMIC = 0; - -MEMORY -{ - ram (rwx) : ORIGIN = 0x00100000, LENGTH = 0x00010000 - per (rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000 -} - -PROVIDE (__stack = 0x10FFFC); - -SECTIONS -{ - .text : - { - __text_start = . ; - *(.vector) - . = ALIGN (0x100); - *(.text) - . = ALIGN (16); - - *(.eh_frame) - . = ALIGN (16); - - *(.gnu.linkonce.t.*) - - . = ALIGN(0x4); - __CTOR_LIST__ = .; - ___CTOR_LIST__ = .; - LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) - *(.ctors) - LONG(0) - __CTOR_END__ = .; - __DTOR_LIST__ = .; - ___DTOR_LIST__ = .; - LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) - *(.dtors) - LONG(0) - __DTOR_END__ = .; - *(.rodata) - *(.gcc_except_table) - - . = ALIGN(0x2); - __INIT_SECTION__ = . ; - LONG (0x4e560000) /* linkw %fp,#0 */ - *(.init) - SHORT (0x4e5e) /* unlk %fp */ - SHORT (0x4e75) /* rts */ - - __FINI_SECTION__ = . ; - LONG (0x4e560000) /* linkw %fp,#0 */ - *(.fini) - SHORT (0x4e5e) /* unlk %fp */ - SHORT (0x4e75) /* rts */ - - *(.lit) - . = ALIGN(16); - _etext = .; - etext = .; - } > ram - - .data : - { - copy_start = .; - *(.shdata) - *(.data) - *(.gnu.linkonce.d.*) - . = ALIGN (16); - _edata = .; - copy_end = .; - } > ram - - .bss : - { - . = ALIGN(0x4); - __bss_start = . ; - *(.shbss) - *(.bss) - *(COMMON) - _end = ALIGN (0x8); - __end = _end; - } > ram - - .peripheral (NOLOAD): - { - __per_start = . ; - *(.peripheral) - } > per - - .stab 0 (NOLOAD) : - { - *(.stab) - } - - .stabstr 0 (NOLOAD) : - { - *(.stabstr) - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/descriptors.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/descriptors.h deleted file mode 100644 index 1b14ea12e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/descriptors.h +++ /dev/null @@ -1,147 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: descriptors.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * USB Descriptors definitions. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - - -#ifndef DESCRIPTOR_H -#define DESCRIPTOR_H - -/********************************************************************/ - -/* USB descriptor types */ -#define DEVICE 1 -#define CONFIGURATION 2 -#define STRING 3 -#define INTERFACE 4 -#define ENDPOINT 5 - -/* USB Standard Request Types - bRequestType */ -#define IN 0x80 -#define OUT 0x00 -#define STANDARD 0x00 -#define CLASS 0x20 -#define VENDOR 0x40 -#define RQ_DEVICE 0x00 -#define RQ_INTERFACE 0x01 -#define RQ_ENDPOINT 0x02 - -/* USB Standard Request Codes - bRequest */ -#define GET_STATUS 0 -#define CLEAR_FEATURE 1 -#define SET_FEATURE 3 -#define SET_ADDRESS 5 -#define GET_DESCRIPTOR 6 -#define SET_DESCRIPTOR 7 -#define GET_CONFIGURATION 8 -#define SET_CONFIGURATION 9 -#define GET_INTERFACE 10 -#define SET_INTERFACE 11 -#define SYNCH_FRAME 12 - -/* Configuration bmAttributes fields */ -#define BUS_POWERED 0x80 -#define SELF_POWERED 0xC0 -#define REMOTE_WAKEUP 0xA0 - -/* Endpoint bmAttributes fields */ -#define CONTROL 0x00 -#define ISOCHRONOUS 0x01 -#define BULK 0x02 -#define INTERRUPT 0x03 -#define DISABLED 0xFF - -/* Standard Feature Selectors */ -#define DEVICE_REMOTE_WAKEUP 1 -#define ENDPOINT_HALT 0 - -/* Structure for USB Device Descriptors */ -typedef struct -{ - uint8 bLength; - uint8 bDescriptorType; - uint8 bcdUSBL; - uint8 bcdUSBH; - uint8 bDeviceClass; - uint8 bDeviceSubClass; - uint8 bDeviceProtocol; - uint8 bMaxPacketSize0; - uint8 idVendorL; - uint8 idVendorH; - uint8 idProductL; - uint8 idProductH; - uint8 bcdDeviceL; - uint8 bcdDeviceH; - uint8 iManufacturer; - uint8 iProduct; - uint8 iSerialNumber; - uint8 bNumConfigurations; -} USB_DEVICE_DESC; - -/* Structure for USB Configuration Descriptors */ -typedef struct -{ - uint8 bLength; - uint8 bDescriptorType; - uint8 wTotalLengthL; - uint8 wTotalLengthH; - uint8 bNumInterfaces; - uint8 bConfigurationValue; - uint8 iConfiguration; - uint8 bmAttributes; - uint8 maxPower; -} USB_CONFIG_DESC; - -/* Structure for USB Interface Descriptors */ -typedef struct -{ - uint8 bLength; - uint8 bDescriptorType; - uint8 bInterfaceNumber; - uint8 bAlternateSetting; - uint8 bNumEndpoints; - uint8 bInterfaceClass; - uint8 bInterfaceSubClass; - uint8 bInterfaceProtocol; - uint8 iInterface; -} USB_INTERFACE_DESC; - -/* Structure for USB Endpoint Descriptors */ -typedef struct -{ - uint8 bLength; - uint8 bDescriptorType; - uint8 bEndpointAddress; - uint8 bmAttributes; - uint8 wMaxPacketSizeL; - uint8 wMaxPacketSizeH; - uint8 bInterval; -} USB_ENDPOINT_DESC; - -/* Structure for USB String Descriptors */ -typedef struct -{ - uint8 bLength; - uint8 bDescriptorType; - uint8 *bString; -} USB_STRING_DESC; - -/********************************************************************/ - -#endif /* DESCRIPTOR_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/m523xevb.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/m523xevb.h deleted file mode 100644 index 23bf868ac..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/m523xevb.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * File: m523xevb.h - * Purpose: Evaluation board definitions and memory map information - * - * Notes: - */ - -#ifndef _M523XEVB_H -#define _M523XEVB_H - -/********************************************************************/ - -#include "mcf5xxx.h" -#include "mcf523x.h" -#include "io.h" - -/********************************************************************/ - -/* - * Debug prints ON (#undef) or OFF (#define) - */ -#undef DEBUG - -/* - * System Bus Clock Info - */ -#define SYSTEM_CLOCK 75 /* system bus frequency in MHz */ -#define PERIOD 13.33 /* system bus period in ns */ - -#define UART_BAUD 19200 /* 19200 */ - -/* - * Flash Device Info - */ -#define AMD_FLASH_AM29PL160CB_16BIT - -/* - * Ethernet Port Info - */ -#define FEC_PHY0 (0x01) - -/* - * Memory map definitions from linker command files - */ -extern uint8 __IPSBAR[]; -extern uint8 __SDRAM[]; -extern uint8 __SDRAM_SIZE[]; -extern uint8 __SRAM[]; -extern uint8 __SRAM_SIZE[]; -extern uint8 __EXT_SRAM[]; -extern uint8 __EXT_SRAM_SIZE[]; -extern uint8 __EXT_FLASH[]; -extern uint8 __EXT_FLASH_SIZE[]; - -/* - * Memory Map Info - */ -#define IPSBAR_ADDRESS (uint32)__IPSBAR - -#define SDRAM_ADDRESS (uint32)__SDRAM -#define SDRAM_SIZE (uint32)__SDRAM_SIZE - -#define SRAM_ADDRESS (uint32)__SRAM -#define SRAM_SIZE (uint32)__SRAM_SIZE - -#define EXT_SRAM_ADDRESS (uint32)__EXT_SRAM -#define EXT_SRAM_SIZE (uint32)__EXT_SRAM_SIZE - -#define EXT_FLASH_ADDRESS (uint32)__EXT_FLASH -#define EXT_FLASH_SIZE (uint32)__EXT_FLASH_SIZE - -/* - * Interrupt Controller Definitions - */ -#define TIMER_NETWORK_LEVEL 3 -#define FEC_LEVEL 4 - -/* - * Timer period info - */ -#define TIMER_NETWORK_PERIOD 1000000000/0x10000 /* 1 sec / max timeout */ - -/********************************************************************/ - -#endif /* _M523XEVB_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x.h deleted file mode 100644 index af8e773a3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x.h +++ /dev/null @@ -1,56 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_H__ -#define __MCF523X_H__ - -/*********************************************************************/ - -#include "mcf523x_fec.h" -#include "mcf523x_rng.h" -#include "mcf523x_fmpll.h" -#include "mcf523x_cs.h" -#include "mcf523x_intc0.h" -#include "mcf523x_intc1.h" -#include "mcf523x_sdramc.h" -#include "mcf523x_sram.h" -#include "mcf523x_uart.h" -#include "mcf523x_timer.h" -#include "mcf523x_qspi.h" -#include "mcf523x_eport.h" -#include "mcf523x_i2c.h" -#include "mcf523x_scm.h" -#include "mcf523x_pit.h" -#include "mcf523x_can.h" -#include "mcf523x_wtm.h" -#include "mcf523x_gpio.h" -#include "mcf523x_mdha.h" -#include "mcf523x_ccm.h" -#include "mcf523x_rcm.h" -#include "mcf523x_etpu.h" -#include "mcf523x_etpu_struc.h" - - - - -/********************************************************************/ - -#endif /* __MCF523X_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_can.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_can.h deleted file mode 100644 index e90c8f288..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_can.h +++ /dev/null @@ -1,332 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_can.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_CAN_H__ -#define __MCF523X_CAN_H__ - -/********************************************************************* -* -* FlexCAN Module (CAN) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CAN_CANMCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0000])) -#define MCF_CAN_CANCTRL0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0004])) -#define MCF_CAN_TIMER0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0008])) -#define MCF_CAN_RXGMASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0010])) -#define MCF_CAN_RX14MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0014])) -#define MCF_CAN_RX15MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0018])) -#define MCF_CAN_ERRCNT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C001C])) -#define MCF_CAN_ERRSTAT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0020])) -#define MCF_CAN_IMASK0 (*(vuint16*)(void*)(&__IPSBAR[0x1C002A])) -#define MCF_CAN_IFLAG0 (*(vuint16*)(void*)(&__IPSBAR[0x1C0032])) -#define MCF_CAN_CANMCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0000])) -#define MCF_CAN_CANCTRL1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0004])) -#define MCF_CAN_TIMER1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0008])) -#define MCF_CAN_RXGMASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0010])) -#define MCF_CAN_RX14MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0014])) -#define MCF_CAN_RX15MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0018])) -#define MCF_CAN_ERRCNT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F001C])) -#define MCF_CAN_ERRSTAT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0020])) -#define MCF_CAN_IMASK1 (*(vuint16*)(void*)(&__IPSBAR[0x1F002A])) -#define MCF_CAN_IFLAG1 (*(vuint16*)(void*)(&__IPSBAR[0x1F0032])) -#define MCF_CAN_CANMCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0000+((x)*0x30000)])) -#define MCF_CAN_CANCTRL(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0004+((x)*0x30000)])) -#define MCF_CAN_TIMER(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0008+((x)*0x30000)])) -#define MCF_CAN_RXGMASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0010+((x)*0x30000)])) -#define MCF_CAN_RX14MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0014+((x)*0x30000)])) -#define MCF_CAN_RX15MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0018+((x)*0x30000)])) -#define MCF_CAN_ERRCNT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C001C+((x)*0x30000)])) -#define MCF_CAN_ERRSTAT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0020+((x)*0x30000)])) -#define MCF_CAN_IMASK(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C002A+((x)*0x30000)])) -#define MCF_CAN_IFLAG(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C0032+((x)*0x30000)])) - -#define MCF_CAN_MBUF0_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0080+((x)*0x30000)])) -#define MCF_CAN_MBUF0_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0082+((x)*0x30000)])) -#define MCF_CAN_MBUF0_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0084+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0089+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008A+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008B+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008D+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008E+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008F+((x)*0x30000)])) -#define MCF_CAN_MBUF1_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0090+((x)*0x30000)])) -#define MCF_CAN_MBUF1_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0092+((x)*0x30000)])) -#define MCF_CAN_MBUF1_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0094+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0099+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009A+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009B+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009D+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009E+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009F+((x)*0x30000)])) -#define MCF_CAN_MBUF2_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00A0+((x)*0x30000)])) -#define MCF_CAN_MBUF2_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A4+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A9+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AA+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AB+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AD+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AE+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AF+((x)*0x30000)])) -#define MCF_CAN_MBUF3_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00B0+((x)*0x30000)])) -#define MCF_CAN_MBUF3_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00B4+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B8+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B9+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BA+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BB+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BC+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BD+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BE+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BF+((x)*0x30000)])) -#define MCF_CAN_MBUF4_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00C0+((x)*0x30000)])) -#define MCF_CAN_MBUF4_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00C4+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C8+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C9+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CA+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CB+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CC+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CD+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CE+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CF+((x)*0x30000)])) -#define MCF_CAN_MBUF5_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00D0+((x)*0x30000)])) -#define MCF_CAN_MBUF5_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00D4+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D8+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D9+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DA+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DB+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DC+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DD+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DE+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DF+((x)*0x30000)])) -#define MCF_CAN_MBUF6_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00E0+((x)*0x30000)])) -#define MCF_CAN_MBUF6_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00E4+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E8+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E9+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EA+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EB+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EC+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00ED+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EE+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EF+((x)*0x30000)])) -#define MCF_CAN_MBUF7_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00F0+((x)*0x30000)])) -#define MCF_CAN_MBUF7_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00F4+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F8+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F9+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FA+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FB+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FC+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FD+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FE+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FF+((x)*0x30000)])) -#define MCF_CAN_MBUF8_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)])) -#define MCF_CAN_MBUF8_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0104+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0108+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0109+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010A+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010B+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010C+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010D+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010E+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010F+((x)*0x30000)])) -#define MCF_CAN_MBUF9_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)])) -#define MCF_CAN_MBUF9_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0114+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0118+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0119+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011A+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011B+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011C+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011D+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011E+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011F+((x)*0x30000)])) -#define MCF_CAN_MBUF10_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0120+((x)*0x30000)])) -#define MCF_CAN_MBUF10_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0124+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0128+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0129+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012A+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012B+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012C+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012D+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012E+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012F+((x)*0x30000)])) -#define MCF_CAN_MBUF11_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0130+((x)*0x30000)])) -#define MCF_CAN_MBUF11_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0134+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0138+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0139+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013A+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013B+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013C+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013D+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013E+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013F+((x)*0x30000)])) -#define MCF_CAN_MBUF12_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0140+((x)*0x30000)])) -#define MCF_CAN_MBUF12_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0144+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0148+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0149+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014A+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014B+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014C+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014D+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014E+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014F+((x)*0x30000)])) -#define MCF_CAN_MBUF13_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0150+((x)*0x30000)])) -#define MCF_CAN_MBUF13_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0154+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0158+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0159+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015A+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015B+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015C+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015D+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015E+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015F+((x)*0x30000)])) -#define MCF_CAN_MBUF14_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0160+((x)*0x30000)])) -#define MCF_CAN_MBUF14_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0164+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0168+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0169+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016A+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016B+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016C+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016D+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016E+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016F+((x)*0x30000)])) -#define MCF_CAN_MBUF15_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0170+((x)*0x30000)])) -#define MCF_CAN_MBUF15_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0174+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0178+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0179+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017A+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017B+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017C+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017D+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017E+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017F+((x)*0x30000)])) - - -#define MCF_CAN_MBUF0_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)])) -#define MCF_CAN_MBUF0_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)])) -#define MCF_CAN_MBUF1_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)])) -#define MCF_CAN_MBUF1_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)])) -#define MCF_CAN_MBUF2_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)])) -#define MCF_CAN_MBUF2_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)])) - - -/* Bit definitions and macros for MCF_CAN_CANMCR */ -#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) -#define MCF_CAN_CANMCR_SUPV (0x00800000) -#define MCF_CAN_CANMCR_FRZACK (0x01000000) -#define MCF_CAN_CANMCR_SOFTRST (0x02000000) -#define MCF_CAN_CANMCR_HALT (0x10000000) -#define MCF_CAN_CANMCR_FRZ (0x40000000) -#define MCF_CAN_CANMCR_MDIS (0x80000000) - -/* Bit definitions and macros for MCF_CAN_CANCTRL */ -#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) -#define MCF_CAN_CANCTRL_LOM (0x00000008) -#define MCF_CAN_CANCTRL_LBUF (0x00000010) -#define MCF_CAN_CANCTRL_TSYNC (0x00000020) -#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) -#define MCF_CAN_CANCTRL_SAMP (0x00000080) -#define MCF_CAN_CANCTRL_LPB (0x00001000) -#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) -#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) -#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) -#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) -#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) -#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) -#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_CAN_TIMER */ -#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RXGMASK */ -#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX14MASK */ -#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX15MASK */ -#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_ERRCNT */ -#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) -#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) - -/* Bit definitions and macros for MCF_CAN_ERRSTAT */ -#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) -#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) -#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) -#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) -#define MCF_CAN_ERRSTAT_TXRX (0x00000040) -#define MCF_CAN_ERRSTAT_IDLE (0x00000080) -#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) -#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) -#define MCF_CAN_ERRSTAT_STFERR (0x00000400) -#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) -#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) -#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) -#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) -#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) -#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) -#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) - -/* Bit definitions and macros for MCF_CAN_IMASK */ -#define MCF_CAN_IMASK_BUF0M (0x0001) -#define MCF_CAN_IMASK_BUF1M (0x0002) -#define MCF_CAN_IMASK_BUF2M (0x0004) -#define MCF_CAN_IMASK_BUF3M (0x0008) -#define MCF_CAN_IMASK_BUF4M (0x0010) -#define MCF_CAN_IMASK_BUF5M (0x0020) -#define MCF_CAN_IMASK_BUF6M (0x0040) -#define MCF_CAN_IMASK_BUF7M (0x0080) -#define MCF_CAN_IMASK_BUF8M (0x0100) -#define MCF_CAN_IMASK_BUF9M (0x0200) -#define MCF_CAN_IMASK_BUF10M (0x0400) -#define MCF_CAN_IMASK_BUF11M (0x0800) -#define MCF_CAN_IMASK_BUF12M (0x1000) -#define MCF_CAN_IMASK_BUF13M (0x2000) -#define MCF_CAN_IMASK_BUF14M (0x4000) -#define MCF_CAN_IMASK_BUF15M (0x8000) - -/* Bit definitions and macros for MCF_CAN_IFLAG */ -#define MCF_CAN_IFLAG_BUF0I (0x0001) -#define MCF_CAN_IFLAG_BUF1I (0x0002) -#define MCF_CAN_IFLAG_BUF2I (0x0004) -#define MCF_CAN_IFLAG_BUF3I (0x0008) -#define MCF_CAN_IFLAG_BUF4I (0x0010) -#define MCF_CAN_IFLAG_BUF5I (0x0020) -#define MCF_CAN_IFLAG_BUF6I (0x0040) -#define MCF_CAN_IFLAG_BUF7I (0x0080) -#define MCF_CAN_IFLAG_BUF8I (0x0100) -#define MCF_CAN_IFLAG_BUF9I (0x0200) -#define MCF_CAN_IFLAG_BUF10I (0x0400) -#define MCF_CAN_IFLAG_BUF11I (0x0800) -#define MCF_CAN_IFLAG_BUF12I (0x1000) -#define MCF_CAN_IFLAG_BUF13I (0x2000) -#define MCF_CAN_IFLAG_BUF14I (0x4000) -#define MCF_CAN_IFLAG_BUF15I (0x8000) - -/********************************************************************/ - -#endif /* __MCF523X_CAN_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_ccm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_ccm.h deleted file mode 100644 index 6a0c78ab6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_ccm.h +++ /dev/null @@ -1,63 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_ccm.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_CCM_H__ -#define __MCF523X_CCM_H__ - -/********************************************************************* -* -* Chip Configuration Module (CCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CCM_CCR (*(vuint16*)(void*)(&__IPSBAR[0x110004])) -#define MCF_CCM_LPCR (*(vuint8 *)(void*)(&__IPSBAR[0x110007])) -#define MCF_CCM_CIR (*(vuint16*)(void*)(&__IPSBAR[0x11000A])) -#define MCF_CCM_RCON (*(vuint16*)(void*)(&__IPSBAR[0x110008])) - -/* Bit definitions and macros for MCF_CCM_CCR */ -#define MCF_CCM_CCR_BMT(x) (((x)&0x0007)<<0) -#define MCF_CCM_CCR_BME (0x0008) -#define MCF_CCM_CCR_SZEN (0x0040) -#define MCF_CCM_CCR_MODE(x) (((x)&0x0007)<<8) - -/* Bit definitions and macros for MCF_CCM_LPCR */ -#define MCF_CCM_LPCR_STPMD(x) (((x)&0x03)<<3) -#define MCF_CCM_LPCR_LPMD(x) (((x)&0x03)<<6) -#define MCF_CCM_LPCR_LPMD_STOP (0xC0) -#define MCF_CCM_LPCR_LPMD_WAIT (0x80) -#define MCF_CCM_LPCR_LPMD_DOZE (0x40) -#define MCF_CCM_LPCR_LPMD_RUN (0x00) - -/* Bit definitions and macros for MCF_CCM_CIR */ -#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0) -#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6) - -/* Bit definitions and macros for MCF_CCM_RCON */ -#define MCF_CCM_RCON_MODE (0x0001) -#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3) -#define MCF_CCM_RCON_RLOAD (0x0020) -#define MCF_CCM_RCON_RCSC(x) (((x)&0x0003)<<8) - -/********************************************************************/ - -#endif /* __MCF523X_CCM_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_cfm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_cfm.h deleted file mode 100644 index 2cf7c7ecc..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_cfm.h +++ /dev/null @@ -1,66 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_cfm.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_CFM_H__ -#define __MCF523X_CFM_H__ - -/********************************************************************* -* -* Chip Configuration Module (CFM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CFM_CCR (*(vuint16*)(void*)(&__IPSBAR[0x110004])) -#define MCF_CFM_LPCR (*(vuint8 *)(void*)(&__IPSBAR[0x110007])) -#define MCF_CFM_CIR (*(vuint16*)(void*)(&__IPSBAR[0x11000A])) -#define MCF_CFM_RCON (*(vuint16*)(void*)(&__IPSBAR[0x110008])) - -/* Bit definitions and macros for MCF_CFM_CCR */ -#define MCF_CFM_CCR_BMT(x) (((x)&0x0007)<<0) -#define MCF_CFM_CCR_BME (0x0008) -#define MCF_CFM_CCR_SZEN (0x0040) -#define MCF_CFM_CCR_MODE(x) (((x)&0x0007)<<8) -#define MCF_CFM_CCR_MODE(x) ((uint16)(((x)&0x0007)<<8)) -#define MCF_CFM_CCR_BMT(x) ((uint16)(((x)&0x0007))) - -/* Bit definitions and macros for MCF_CFM_LPCR */ -#define MCF_CFM_LPCR_STPMD(x) (((x)&0x03)<<3) -#define MCF_CFM_LPCR_LPMD(x) (((x)&0x03)<<6) -#define MCF_CFM_LPCR_LPMD_STOP (0xC0) -#define MCF_CFM_LPCR_LPMD_WAIT (0x80) -#define MCF_CFM_LPCR_LPMD_DOZE (0x40) -#define MCF_CFM_LPCR_LPMD_RUN (0x00) -#define MCF_CFM_LPCR_STPMD(x) ((uint8)(((x)&0x0003)<<3)) - -/* Bit definitions and macros for MCF_CFM_CIR */ -#define MCF_CFM_CIR_PRN(x) (((x)&0x003F)<<0) -#define MCF_CFM_CIR_PIN(x) (((x)&0x03FF)<<6) - -/* Bit definitions and macros for MCF_CFM_RCON */ -#define MCF_CFM_RCON_MODE (0x0001) -#define MCF_CFM_RCON_BOOTPS(x) (((x)&0x0003)<<3) -#define MCF_CFM_RCON_RLOAD (0x0020) -#define MCF_CFM_RCON_RCSC(x) (((x)&0x0003)<<8) - -/********************************************************************/ - -#endif /* __MCF523X_CFM_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_cs.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_cs.h deleted file mode 100644 index a48de5e06..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_cs.h +++ /dev/null @@ -1,108 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_cs.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_CS_H__ -#define __MCF523X_CS_H__ - -/********************************************************************* -* -* Chip Selects (CS) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CS_CSAR0 (*(vuint16*)(void*)(&__IPSBAR[0x000080])) -#define MCF_CS_CSMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000084])) -#define MCF_CS_CSCR0 (*(vuint16*)(void*)(&__IPSBAR[0x00008A])) -#define MCF_CS_CSAR1 (*(vuint16*)(void*)(&__IPSBAR[0x00008C])) -#define MCF_CS_CSMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000090])) -#define MCF_CS_CSCR1 (*(vuint16*)(void*)(&__IPSBAR[0x000096])) -#define MCF_CS_CSAR2 (*(vuint16*)(void*)(&__IPSBAR[0x000098])) -#define MCF_CS_CSMR2 (*(vuint32*)(void*)(&__IPSBAR[0x00009C])) -#define MCF_CS_CSCR2 (*(vuint16*)(void*)(&__IPSBAR[0x0000A2])) -#define MCF_CS_CSAR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000A4])) -#define MCF_CS_CSMR3 (*(vuint32*)(void*)(&__IPSBAR[0x0000A8])) -#define MCF_CS_CSCR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000AE])) -#define MCF_CS_CSAR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000B0])) -#define MCF_CS_CSMR4 (*(vuint32*)(void*)(&__IPSBAR[0x0000B4])) -#define MCF_CS_CSCR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000BA])) -#define MCF_CS_CSAR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000BC])) -#define MCF_CS_CSMR5 (*(vuint32*)(void*)(&__IPSBAR[0x0000C0])) -#define MCF_CS_CSCR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000C6])) -#define MCF_CS_CSAR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000C8])) -#define MCF_CS_CSMR6 (*(vuint32*)(void*)(&__IPSBAR[0x0000CC])) -#define MCF_CS_CSCR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000D2])) -#define MCF_CS_CSAR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000D4])) -#define MCF_CS_CSMR7 (*(vuint32*)(void*)(&__IPSBAR[0x0000D8])) -#define MCF_CS_CSCR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000DE])) -#define MCF_CS_CSAR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000080+((x)*0x00C)])) -#define MCF_CS_CSMR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000084+((x)*0x00C)])) -#define MCF_CS_CSCR(x) (*(vuint16*)(void*)(&__IPSBAR[0x00008A+((x)*0x00C)])) - -/* Bit definitions and macros for MCF_CS_CSAR */ -#define MCF_CS_CSAR_BA(x) ((uint16)(((x)&0xFFFF0000)>>16)) - -/* Bit definitions and macros for MCF_CS_CSMR */ -#define MCF_CS_CSMR_V (0x00000001) -#define MCF_CS_CSMR_UD (0x00000002) -#define MCF_CS_CSMR_UC (0x00000004) -#define MCF_CS_CSMR_SD (0x00000008) -#define MCF_CS_CSMR_SC (0x00000010) -#define MCF_CS_CSMR_CI (0x00000020) -#define MCF_CS_CSMR_AM (0x00000040) -#define MCF_CS_CSMR_WP (0x00000100) -#define MCF_CS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) -#define MCF_CS_CSMR_BAM_4G (0xFFFF0000) -#define MCF_CS_CSMR_BAM_2G (0x7FFF0000) -#define MCF_CS_CSMR_BAM_1G (0x3FFF0000) -#define MCF_CS_CSMR_BAM_1024M (0x3FFF0000) -#define MCF_CS_CSMR_BAM_512M (0x1FFF0000) -#define MCF_CS_CSMR_BAM_256M (0x0FFF0000) -#define MCF_CS_CSMR_BAM_128M (0x07FF0000) -#define MCF_CS_CSMR_BAM_64M (0x03FF0000) -#define MCF_CS_CSMR_BAM_32M (0x01FF0000) -#define MCF_CS_CSMR_BAM_16M (0x00FF0000) -#define MCF_CS_CSMR_BAM_8M (0x007F0000) -#define MCF_CS_CSMR_BAM_4M (0x003F0000) -#define MCF_CS_CSMR_BAM_2M (0x001F0000) -#define MCF_CS_CSMR_BAM_1M (0x000F0000) -#define MCF_CS_CSMR_BAM_1024K (0x000F0000) -#define MCF_CS_CSMR_BAM_512K (0x00070000) -#define MCF_CS_CSMR_BAM_256K (0x00030000) -#define MCF_CS_CSMR_BAM_128K (0x00010000) -#define MCF_CS_CSMR_BAM_64K (0x00000000) - -/* Bit definitions and macros for MCF_CS_CSCR */ -#define MCF_CS_CSCR_SWWS(x) (((x)&0x0007)<<0) -#define MCF_CS_CSCR_BSTW (0x0008) -#define MCF_CS_CSCR_BSTR (0x0010) -#define MCF_CS_CSCR_BEM (0x0020) -#define MCF_CS_CSCR_PS(x) (((x)&0x0003)<<6) -#define MCF_CS_CSCR_AA (0x0100) -#define MCF_CS_CSCR_IWS(x) (((x)&0x000F)<<10) -#define MCF_CS_CSCR_SRWS(x) (((x)&0x0003)<<14) -#define MCF_CS_CSCR_PS_8 (0x0040) -#define MCF_CS_CSCR_PS_16 (0x0080) -#define MCF_CS_CSCR_PS_32 (0x0000) - -/********************************************************************/ - -#endif /* __MCF523X_CS_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_eport.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_eport.h deleted file mode 100644 index 1981e260b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_eport.h +++ /dev/null @@ -1,99 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_eport.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_EPORT_H__ -#define __MCF523X_EPORT_H__ - -/********************************************************************* -* -* Edge Port Module (EPORT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_EPORT_EPPAR (*(vuint16*)(void*)(&__IPSBAR[0x130000])) -#define MCF_EPORT_EPDDR (*(vuint8 *)(void*)(&__IPSBAR[0x130002])) -#define MCF_EPORT_EPIER (*(vuint8 *)(void*)(&__IPSBAR[0x130003])) -#define MCF_EPORT_EPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130004])) -#define MCF_EPORT_EPPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130005])) -#define MCF_EPORT_EPFR (*(vuint8 *)(void*)(&__IPSBAR[0x130006])) - -/* Bit definitions and macros for MCF_EPORT_EPPAR */ -#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) -#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) -#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) -#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) -#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) -#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) -#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) -#define MCF_EPORT_EPPAR_EPPAx_LEVEL (0) -#define MCF_EPORT_EPPAR_EPPAx_RISING (1) -#define MCF_EPORT_EPPAR_EPPAx_FALLING (2) -#define MCF_EPORT_EPPAR_EPPAx_BOTH (3) - -/* Bit definitions and macros for MCF_EPORT_EPDDR */ -#define MCF_EPORT_EPDDR_EPDD1 (0x02) -#define MCF_EPORT_EPDDR_EPDD2 (0x04) -#define MCF_EPORT_EPDDR_EPDD3 (0x08) -#define MCF_EPORT_EPDDR_EPDD4 (0x10) -#define MCF_EPORT_EPDDR_EPDD5 (0x20) -#define MCF_EPORT_EPDDR_EPDD6 (0x40) -#define MCF_EPORT_EPDDR_EPDD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPIER */ -#define MCF_EPORT_EPIER_EPIE1 (0x02) -#define MCF_EPORT_EPIER_EPIE2 (0x04) -#define MCF_EPORT_EPIER_EPIE3 (0x08) -#define MCF_EPORT_EPIER_EPIE4 (0x10) -#define MCF_EPORT_EPIER_EPIE5 (0x20) -#define MCF_EPORT_EPIER_EPIE6 (0x40) -#define MCF_EPORT_EPIER_EPIE7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPDR */ -#define MCF_EPORT_EPDR_EPD1 (0x02) -#define MCF_EPORT_EPDR_EPD2 (0x04) -#define MCF_EPORT_EPDR_EPD3 (0x08) -#define MCF_EPORT_EPDR_EPD4 (0x10) -#define MCF_EPORT_EPDR_EPD5 (0x20) -#define MCF_EPORT_EPDR_EPD6 (0x40) -#define MCF_EPORT_EPDR_EPD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPPDR */ -#define MCF_EPORT_EPPDR_EPPD1 (0x02) -#define MCF_EPORT_EPPDR_EPPD2 (0x04) -#define MCF_EPORT_EPPDR_EPPD3 (0x08) -#define MCF_EPORT_EPPDR_EPPD4 (0x10) -#define MCF_EPORT_EPPDR_EPPD5 (0x20) -#define MCF_EPORT_EPPDR_EPPD6 (0x40) -#define MCF_EPORT_EPPDR_EPPD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPFR */ -#define MCF_EPORT_EPFR_EPF1 (0x02) -#define MCF_EPORT_EPFR_EPF2 (0x04) -#define MCF_EPORT_EPFR_EPF3 (0x08) -#define MCF_EPORT_EPFR_EPF4 (0x10) -#define MCF_EPORT_EPFR_EPF5 (0x20) -#define MCF_EPORT_EPFR_EPF6 (0x40) -#define MCF_EPORT_EPFR_EPF7 (0x80) - -/********************************************************************/ - -#endif /* __MCF523X_EPORT_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_etpu.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_etpu.h deleted file mode 100644 index d8e42017d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_etpu.h +++ /dev/null @@ -1,500 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_etpu.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_ETPU_H__ -#define __MCF523X_ETPU_H__ - -/********************************************************************* -* -* enhanced Time Processor Unit (ETPU) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_ETPU_EMCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0000])) -#define MCF_ETPU_ECDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0004])) -#define MCF_ETPU_EMISCCR (*(vuint32*)(void*)(&__IPSBAR[0x1D000C])) -#define MCF_ETPU_ESCMODR (*(vuint32*)(void*)(&__IPSBAR[0x1D0010])) -#define MCF_ETPU_EECR (*(vuint32*)(void*)(&__IPSBAR[0x1D0014])) -#define MCF_ETPU_ETBCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0020])) -#define MCF_ETPU_ETB1R (*(vuint32*)(void*)(&__IPSBAR[0x1D0024])) -#define MCF_ETPU_ETB2R (*(vuint32*)(void*)(&__IPSBAR[0x1D0028])) -#define MCF_ETPU_EREDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D002C])) -#define MCF_ETPU_ECISR (*(vuint32*)(void*)(&__IPSBAR[0x1D0200])) -#define MCF_ETPU_ECDTRSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0210])) -#define MCF_ETPU_ECIOSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0220])) -#define MCF_ETPU_ECDTROSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0230])) -#define MCF_ETPU_ECIER (*(vuint32*)(void*)(&__IPSBAR[0x1D0240])) -#define MCF_ETPU_ECDTRER (*(vuint32*)(void*)(&__IPSBAR[0x1D0250])) -#define MCF_ETPU_ECPSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0280])) -#define MCF_ETPU_ECSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0290])) -#define MCF_ETPU_EC0SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0404])) -#define MCF_ETPU_EC1SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0414])) -#define MCF_ETPU_EC2SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0424])) -#define MCF_ETPU_EC3SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0434])) -#define MCF_ETPU_EC4SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0444])) -#define MCF_ETPU_EC5SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0454])) -#define MCF_ETPU_EC6SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0464])) -#define MCF_ETPU_EC7SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0474])) -#define MCF_ETPU_EC8SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0484])) -#define MCF_ETPU_EC9SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0494])) -#define MCF_ETPU_EC10SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A4])) -#define MCF_ETPU_EC11SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B4])) -#define MCF_ETPU_EC12SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C4])) -#define MCF_ETPU_EC13SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D4])) -#define MCF_ETPU_EC14SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E4])) -#define MCF_ETPU_EC15SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F4])) -#define MCF_ETPU_EC16SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0504])) -#define MCF_ETPU_EC17SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0514])) -#define MCF_ETPU_EC18SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0524])) -#define MCF_ETPU_EC19SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0534])) -#define MCF_ETPU_EC20SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0544])) -#define MCF_ETPU_EC21SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0554])) -#define MCF_ETPU_EC22SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0564])) -#define MCF_ETPU_EC23SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0574])) -#define MCF_ETPU_EC24SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0584])) -#define MCF_ETPU_EC25SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0594])) -#define MCF_ETPU_EC26SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A4])) -#define MCF_ETPU_EC27SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B4])) -#define MCF_ETPU_EC28SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C4])) -#define MCF_ETPU_EC29SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D4])) -#define MCF_ETPU_EC30SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E4])) -#define MCF_ETPU_EC31SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F4])) -#define MCF_ETPU_ECnSCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0404+((x)*0x010)])) -#define MCF_ETPU_EC0CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0400])) -#define MCF_ETPU_EC1CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0410])) -#define MCF_ETPU_EC2CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0420])) -#define MCF_ETPU_EC3CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0430])) -#define MCF_ETPU_EC4CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0440])) -#define MCF_ETPU_EC5CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0450])) -#define MCF_ETPU_EC6CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0460])) -#define MCF_ETPU_EC7CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0470])) -#define MCF_ETPU_EC8CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0480])) -#define MCF_ETPU_EC9CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0490])) -#define MCF_ETPU_EC10CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A0])) -#define MCF_ETPU_EC11CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B0])) -#define MCF_ETPU_EC12CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C0])) -#define MCF_ETPU_EC13CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D0])) -#define MCF_ETPU_EC14CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E0])) -#define MCF_ETPU_EC15CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F0])) -#define MCF_ETPU_EC16CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0500])) -#define MCF_ETPU_EC17CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0510])) -#define MCF_ETPU_EC18CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0520])) -#define MCF_ETPU_EC19CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0530])) -#define MCF_ETPU_EC20CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0540])) -#define MCF_ETPU_EC21CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0550])) -#define MCF_ETPU_EC22CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0560])) -#define MCF_ETPU_EC23CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0570])) -#define MCF_ETPU_EC24CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0580])) -#define MCF_ETPU_EC25CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0590])) -#define MCF_ETPU_EC26CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A0])) -#define MCF_ETPU_EC27CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B0])) -#define MCF_ETPU_EC28CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C0])) -#define MCF_ETPU_EC29CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D0])) -#define MCF_ETPU_EC30CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E0])) -#define MCF_ETPU_EC31CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F0])) -#define MCF_ETPU_ECnCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0400+((x)*0x010)])) -#define MCF_ETPU_EC0HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0408])) -#define MCF_ETPU_EC1HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0418])) -#define MCF_ETPU_EC2HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0428])) -#define MCF_ETPU_EC3HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0438])) -#define MCF_ETPU_EC4HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0448])) -#define MCF_ETPU_EC5HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0458])) -#define MCF_ETPU_EC6HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0468])) -#define MCF_ETPU_EC7HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0478])) -#define MCF_ETPU_EC8HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0488])) -#define MCF_ETPU_EC9HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0498])) -#define MCF_ETPU_EC10HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A8])) -#define MCF_ETPU_EC11HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B8])) -#define MCF_ETPU_EC12HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C8])) -#define MCF_ETPU_EC13HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D8])) -#define MCF_ETPU_EC14HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E8])) -#define MCF_ETPU_EC15HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F8])) -#define MCF_ETPU_EC16HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0508])) -#define MCF_ETPU_EC17HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0518])) -#define MCF_ETPU_EC18HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0528])) -#define MCF_ETPU_EC19HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0538])) -#define MCF_ETPU_EC20HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0548])) -#define MCF_ETPU_EC21HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0558])) -#define MCF_ETPU_EC22HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0568])) -#define MCF_ETPU_EC23HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0578])) -#define MCF_ETPU_EC24HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0588])) -#define MCF_ETPU_EC25HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0598])) -#define MCF_ETPU_EC26HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A8])) -#define MCF_ETPU_EC27HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B8])) -#define MCF_ETPU_EC28HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C8])) -#define MCF_ETPU_EC29HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D8])) -#define MCF_ETPU_EC30HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E8])) -#define MCF_ETPU_EC31HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F8])) -#define MCF_ETPU_ECnHSSR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0408+((x)*0x010)])) - -/* Bit definitions and macros for MCF_ETPU_EMCR */ -#define MCF_ETPU_EMCR_GTBE (0x00000001) -#define MCF_ETPU_EMCR_VIS (0x00000040) -#define MCF_ETPU_EMCR_SCMMISEN (0x00000200) -#define MCF_ETPU_EMCR_SCMMISF (0x00000400) -#define MCF_ETPU_EMCR_SCMSIZE(x) (((x)&0x0000001F)<<16) -#define MCF_ETPU_EMCR_ILF2 (0x01000000) -#define MCF_ETPU_EMCR_ILF1 (0x02000000) -#define MCF_ETPU_EMCR_MGE2 (0x04000000) -#define MCF_ETPU_EMCR_MGE1 (0x08000000) -#define MCF_ETPU_EMCR_GEC (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECDCR */ -#define MCF_ETPU_ECDCR_PARM1(x) (((x)&0x0000007F)<<0) -#define MCF_ETPU_ECDCR_WR (0x00000080) -#define MCF_ETPU_ECDCR_PARM0(x) (((x)&0x0000007F)<<8) -#define MCF_ETPU_ECDCR_PWIDTH (0x00008000) -#define MCF_ETPU_ECDCR_PBASE(x) (((x)&0x000003FF)<<16) -#define MCF_ETPU_ECDCR_CTBASE(x) (((x)&0x0000001F)<<26) -#define MCF_ETPU_ECDCR_STS (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_EECR */ -#define MCF_ETPU_EECR_ETB(x) (((x)&0x0000001F)<<0) -#define MCF_ETPU_EECR_CDFC(x) (((x)&0x00000003)<<14) -#define MCF_ETPU_EECR_FPSK(x) (((x)&0x00000007)<<16) -#define MCF_ETPU_EECR_HLTF (0x00800000) -#define MCF_ETPU_EECR_STF (0x10000000) -#define MCF_ETPU_EECR_MDIS (0x40000000) -#define MCF_ETPU_EECR_FEND (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ETBCR */ -#define MCF_ETPU_ETBCR_TCR1P(x) (((x)&0x000000FF)<<0) -#define MCF_ETPU_ETBCR_TCR1CTL(x) (((x)&0x00000003)<<14) -#define MCF_ETPU_ETBCR_TCR2P(x) (((x)&0x0000003F)<<16) -#define MCF_ETPU_ETBCR_AM (0x02000000) -#define MCF_ETPU_ETBCR_TCRCF(x) (((x)&0x00000003)<<27) -#define MCF_ETPU_ETBCR_TCR2CTL(x) (((x)&0x00000007)<<29) - -/* Bit definitions and macros for MCF_ETPU_ETB1R */ -#define MCF_ETPU_ETB1R_TCR1(x) (((x)&0x00FFFFFF)<<0) - -/* Bit definitions and macros for MCF_ETPU_ETB2R */ -#define MCF_ETPU_ETB2R_TCR2(x) (((x)&0x00FFFFFF)<<0) - -/* Bit definitions and macros for MCF_ETPU_EREDCR */ -#define MCF_ETPU_EREDCR_SRV2(x) (((x)&0x0000000F)<<0) -#define MCF_ETPU_EREDCR_SERVER_ID2(x) (((x)&0x0000000F)<<8) -#define MCF_ETPU_EREDCR_RSC2 (0x00004000) -#define MCF_ETPU_EREDCR_REN2 (0x00008000) -#define MCF_ETPU_EREDCR_SRV1(x) (((x)&0x0000000F)<<16) -#define MCF_ETPU_EREDCR_SERVER_ID1(x) (((x)&0x0000000F)<<24) -#define MCF_ETPU_EREDCR_RSC1 (0x40000000) -#define MCF_ETPU_EREDCR_REN1 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECISR */ -#define MCF_ETPU_ECISR_CIS0 (0x00000001) -#define MCF_ETPU_ECISR_CIS1 (0x00000002) -#define MCF_ETPU_ECISR_CIS2 (0x00000004) -#define MCF_ETPU_ECISR_CIS3 (0x00000008) -#define MCF_ETPU_ECISR_CIS4 (0x00000010) -#define MCF_ETPU_ECISR_CIS5 (0x00000020) -#define MCF_ETPU_ECISR_CIS6 (0x00000040) -#define MCF_ETPU_ECISR_CIS7 (0x00000080) -#define MCF_ETPU_ECISR_CIS8 (0x00000100) -#define MCF_ETPU_ECISR_CIS9 (0x00000200) -#define MCF_ETPU_ECISR_CIS10 (0x00000400) -#define MCF_ETPU_ECISR_CIS11 (0x00000800) -#define MCF_ETPU_ECISR_CIS12 (0x00001000) -#define MCF_ETPU_ECISR_CIS13 (0x00002000) -#define MCF_ETPU_ECISR_CIS14 (0x00004000) -#define MCF_ETPU_ECISR_CIS15 (0x00008000) -#define MCF_ETPU_ECISR_CIS16 (0x00010000) -#define MCF_ETPU_ECISR_CIS17 (0x00020000) -#define MCF_ETPU_ECISR_CIS18 (0x00040000) -#define MCF_ETPU_ECISR_CIS19 (0x00080000) -#define MCF_ETPU_ECISR_CIS20 (0x00100000) -#define MCF_ETPU_ECISR_CIS21 (0x00200000) -#define MCF_ETPU_ECISR_CIS22 (0x00400000) -#define MCF_ETPU_ECISR_CIS23 (0x00800000) -#define MCF_ETPU_ECISR_CIS24 (0x01000000) -#define MCF_ETPU_ECISR_CIS25 (0x02000000) -#define MCF_ETPU_ECISR_CIS26 (0x04000000) -#define MCF_ETPU_ECISR_CIS27 (0x08000000) -#define MCF_ETPU_ECISR_CIS28 (0x10000000) -#define MCF_ETPU_ECISR_CIS29 (0x20000000) -#define MCF_ETPU_ECISR_CIS30 (0x40000000) -#define MCF_ETPU_ECISR_CIS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECDTRSR */ -#define MCF_ETPU_ECDTRSR_DTRS0 (0x00000001) -#define MCF_ETPU_ECDTRSR_DTRS1 (0x00000002) -#define MCF_ETPU_ECDTRSR_DTRS2 (0x00000004) -#define MCF_ETPU_ECDTRSR_DTRS3 (0x00000008) -#define MCF_ETPU_ECDTRSR_DTRS4 (0x00000010) -#define MCF_ETPU_ECDTRSR_DTRS5 (0x00000020) -#define MCF_ETPU_ECDTRSR_DTRS6 (0x00000040) -#define MCF_ETPU_ECDTRSR_DTRS7 (0x00000080) -#define MCF_ETPU_ECDTRSR_DTRS8 (0x00000100) -#define MCF_ETPU_ECDTRSR_DTRS9 (0x00000200) -#define MCF_ETPU_ECDTRSR_DTRS10 (0x00000400) -#define MCF_ETPU_ECDTRSR_DTRS11 (0x00000800) -#define MCF_ETPU_ECDTRSR_DTRS12 (0x00001000) -#define MCF_ETPU_ECDTRSR_DTRS13 (0x00002000) -#define MCF_ETPU_ECDTRSR_DTRS14 (0x00004000) -#define MCF_ETPU_ECDTRSR_DTRS15 (0x00008000) -#define MCF_ETPU_ECDTRSR_DTRS16 (0x00010000) -#define MCF_ETPU_ECDTRSR_DTRS17 (0x00020000) -#define MCF_ETPU_ECDTRSR_DTRS18 (0x00040000) -#define MCF_ETPU_ECDTRSR_DTRS19 (0x00080000) -#define MCF_ETPU_ECDTRSR_DTRS20 (0x00100000) -#define MCF_ETPU_ECDTRSR_DTRS21 (0x00200000) -#define MCF_ETPU_ECDTRSR_DTRS22 (0x00400000) -#define MCF_ETPU_ECDTRSR_DTRS23 (0x00800000) -#define MCF_ETPU_ECDTRSR_DTRS24 (0x01000000) -#define MCF_ETPU_ECDTRSR_DTRS25 (0x02000000) -#define MCF_ETPU_ECDTRSR_DTRS26 (0x04000000) -#define MCF_ETPU_ECDTRSR_DTRS27 (0x08000000) -#define MCF_ETPU_ECDTRSR_DTRS28 (0x10000000) -#define MCF_ETPU_ECDTRSR_DTRS29 (0x20000000) -#define MCF_ETPU_ECDTRSR_DTRS30 (0x40000000) -#define MCF_ETPU_ECDTRSR_DTRS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECIOSR */ -#define MCF_ETPU_ECIOSR_CIOS0 (0x00000001) -#define MCF_ETPU_ECIOSR_CIOS1 (0x00000002) -#define MCF_ETPU_ECIOSR_CIOS2 (0x00000004) -#define MCF_ETPU_ECIOSR_CIOS3 (0x00000008) -#define MCF_ETPU_ECIOSR_CIOS4 (0x00000010) -#define MCF_ETPU_ECIOSR_CIOS5 (0x00000020) -#define MCF_ETPU_ECIOSR_CIOS6 (0x00000040) -#define MCF_ETPU_ECIOSR_CIOS7 (0x00000080) -#define MCF_ETPU_ECIOSR_CIOS8 (0x00000100) -#define MCF_ETPU_ECIOSR_CIOS9 (0x00000200) -#define MCF_ETPU_ECIOSR_CIOS10 (0x00000400) -#define MCF_ETPU_ECIOSR_CIOS11 (0x00000800) -#define MCF_ETPU_ECIOSR_CIOS12 (0x00001000) -#define MCF_ETPU_ECIOSR_CIOS13 (0x00002000) -#define MCF_ETPU_ECIOSR_CIOS14 (0x00004000) -#define MCF_ETPU_ECIOSR_CIOS15 (0x00008000) -#define MCF_ETPU_ECIOSR_CIOS16 (0x00010000) -#define MCF_ETPU_ECIOSR_CIOS17 (0x00020000) -#define MCF_ETPU_ECIOSR_CIOS18 (0x00040000) -#define MCF_ETPU_ECIOSR_CIOS19 (0x00080000) -#define MCF_ETPU_ECIOSR_CIOS20 (0x00100000) -#define MCF_ETPU_ECIOSR_CIOS21 (0x00200000) -#define MCF_ETPU_ECIOSR_CIOS22 (0x00400000) -#define MCF_ETPU_ECIOSR_CIOS23 (0x00800000) -#define MCF_ETPU_ECIOSR_CIOS24 (0x01000000) -#define MCF_ETPU_ECIOSR_CIOS25 (0x02000000) -#define MCF_ETPU_ECIOSR_CIOS26 (0x04000000) -#define MCF_ETPU_ECIOSR_CIOS27 (0x08000000) -#define MCF_ETPU_ECIOSR_CIOS28 (0x10000000) -#define MCF_ETPU_ECIOSR_CIOS29 (0x20000000) -#define MCF_ETPU_ECIOSR_CIOS30 (0x40000000) -#define MCF_ETPU_ECIOSR_CIOS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECDTROSR */ -#define MCF_ETPU_ECDTROSR_DTROS0 (0x00000001) -#define MCF_ETPU_ECDTROSR_DTROS1 (0x00000002) -#define MCF_ETPU_ECDTROSR_DTROS2 (0x00000004) -#define MCF_ETPU_ECDTROSR_DTROS3 (0x00000008) -#define MCF_ETPU_ECDTROSR_DTROS4 (0x00000010) -#define MCF_ETPU_ECDTROSR_DTROS5 (0x00000020) -#define MCF_ETPU_ECDTROSR_DTROS6 (0x00000040) -#define MCF_ETPU_ECDTROSR_DTROS7 (0x00000080) -#define MCF_ETPU_ECDTROSR_DTROS8 (0x00000100) -#define MCF_ETPU_ECDTROSR_DTROS9 (0x00000200) -#define MCF_ETPU_ECDTROSR_DTROS10 (0x00000400) -#define MCF_ETPU_ECDTROSR_DTROS11 (0x00000800) -#define MCF_ETPU_ECDTROSR_DTROS12 (0x00001000) -#define MCF_ETPU_ECDTROSR_DTROS13 (0x00002000) -#define MCF_ETPU_ECDTROSR_DTROS14 (0x00004000) -#define MCF_ETPU_ECDTROSR_DTROS15 (0x00008000) -#define MCF_ETPU_ECDTROSR_DTROS16 (0x00010000) -#define MCF_ETPU_ECDTROSR_DTROS17 (0x00020000) -#define MCF_ETPU_ECDTROSR_DTROS18 (0x00040000) -#define MCF_ETPU_ECDTROSR_DTROS19 (0x00080000) -#define MCF_ETPU_ECDTROSR_DTROS20 (0x00100000) -#define MCF_ETPU_ECDTROSR_DTROS21 (0x00200000) -#define MCF_ETPU_ECDTROSR_DTROS22 (0x00400000) -#define MCF_ETPU_ECDTROSR_DTROS23 (0x00800000) -#define MCF_ETPU_ECDTROSR_DTROS24 (0x01000000) -#define MCF_ETPU_ECDTROSR_DTROS25 (0x02000000) -#define MCF_ETPU_ECDTROSR_DTROS26 (0x04000000) -#define MCF_ETPU_ECDTROSR_DTROS27 (0x08000000) -#define MCF_ETPU_ECDTROSR_DTROS28 (0x10000000) -#define MCF_ETPU_ECDTROSR_DTROS29 (0x20000000) -#define MCF_ETPU_ECDTROSR_DTROS30 (0x40000000) -#define MCF_ETPU_ECDTROSR_DTROS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECIER */ -#define MCF_ETPU_ECIER_CIE0 (0x00000001) -#define MCF_ETPU_ECIER_CIE1 (0x00000002) -#define MCF_ETPU_ECIER_CIE2 (0x00000004) -#define MCF_ETPU_ECIER_CIE3 (0x00000008) -#define MCF_ETPU_ECIER_CIE4 (0x00000010) -#define MCF_ETPU_ECIER_CIE5 (0x00000020) -#define MCF_ETPU_ECIER_CIE6 (0x00000040) -#define MCF_ETPU_ECIER_CIE7 (0x00000080) -#define MCF_ETPU_ECIER_CIE8 (0x00000100) -#define MCF_ETPU_ECIER_CIE9 (0x00000200) -#define MCF_ETPU_ECIER_CIE10 (0x00000400) -#define MCF_ETPU_ECIER_CIE11 (0x00000800) -#define MCF_ETPU_ECIER_CIE12 (0x00001000) -#define MCF_ETPU_ECIER_CIE13 (0x00002000) -#define MCF_ETPU_ECIER_CIE14 (0x00004000) -#define MCF_ETPU_ECIER_CIE15 (0x00008000) -#define MCF_ETPU_ECIER_CIE16 (0x00010000) -#define MCF_ETPU_ECIER_CIE17 (0x00020000) -#define MCF_ETPU_ECIER_CIE18 (0x00040000) -#define MCF_ETPU_ECIER_CIE19 (0x00080000) -#define MCF_ETPU_ECIER_CIE20 (0x00100000) -#define MCF_ETPU_ECIER_CIE21 (0x00200000) -#define MCF_ETPU_ECIER_CIE22 (0x00400000) -#define MCF_ETPU_ECIER_CIE23 (0x00800000) -#define MCF_ETPU_ECIER_CIE24 (0x01000000) -#define MCF_ETPU_ECIER_CIE25 (0x02000000) -#define MCF_ETPU_ECIER_CIE26 (0x04000000) -#define MCF_ETPU_ECIER_CIE27 (0x08000000) -#define MCF_ETPU_ECIER_CIE28 (0x10000000) -#define MCF_ETPU_ECIER_CIE29 (0x20000000) -#define MCF_ETPU_ECIER_CIE30 (0x40000000) -#define MCF_ETPU_ECIER_CIE31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECDTRER */ -#define MCF_ETPU_ECDTRER_DTRE0 (0x00000001) -#define MCF_ETPU_ECDTRER_DTRE1 (0x00000002) -#define MCF_ETPU_ECDTRER_DTRE2 (0x00000004) -#define MCF_ETPU_ECDTRER_DTRE3 (0x00000008) -#define MCF_ETPU_ECDTRER_DTRE4 (0x00000010) -#define MCF_ETPU_ECDTRER_DTRE5 (0x00000020) -#define MCF_ETPU_ECDTRER_DTRE6 (0x00000040) -#define MCF_ETPU_ECDTRER_DTRE7 (0x00000080) -#define MCF_ETPU_ECDTRER_DTRE8 (0x00000100) -#define MCF_ETPU_ECDTRER_DTRE9 (0x00000200) -#define MCF_ETPU_ECDTRER_DTRE10 (0x00000400) -#define MCF_ETPU_ECDTRER_DTRE11 (0x00000800) -#define MCF_ETPU_ECDTRER_DTRE12 (0x00001000) -#define MCF_ETPU_ECDTRER_DTRE13 (0x00002000) -#define MCF_ETPU_ECDTRER_DTRE14 (0x00004000) -#define MCF_ETPU_ECDTRER_DTRE15 (0x00008000) -#define MCF_ETPU_ECDTRER_DTRE16 (0x00010000) -#define MCF_ETPU_ECDTRER_DTRE17 (0x00020000) -#define MCF_ETPU_ECDTRER_DTRE18 (0x00040000) -#define MCF_ETPU_ECDTRER_DTRE19 (0x00080000) -#define MCF_ETPU_ECDTRER_DTRE20 (0x00100000) -#define MCF_ETPU_ECDTRER_DTRE21 (0x00200000) -#define MCF_ETPU_ECDTRER_DTRE22 (0x00400000) -#define MCF_ETPU_ECDTRER_DTRE23 (0x00800000) -#define MCF_ETPU_ECDTRER_DTRE24 (0x01000000) -#define MCF_ETPU_ECDTRER_DTRE25 (0x02000000) -#define MCF_ETPU_ECDTRER_DTRE26 (0x04000000) -#define MCF_ETPU_ECDTRER_DTRE27 (0x08000000) -#define MCF_ETPU_ECDTRER_DTRE28 (0x10000000) -#define MCF_ETPU_ECDTRER_DTRE29 (0x20000000) -#define MCF_ETPU_ECDTRER_DTRE30 (0x40000000) -#define MCF_ETPU_ECDTRER_DTRE31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECPSSR */ -#define MCF_ETPU_ECPSSR_SR0 (0x00000001) -#define MCF_ETPU_ECPSSR_SR1 (0x00000002) -#define MCF_ETPU_ECPSSR_SR2 (0x00000004) -#define MCF_ETPU_ECPSSR_SR3 (0x00000008) -#define MCF_ETPU_ECPSSR_SR4 (0x00000010) -#define MCF_ETPU_ECPSSR_SR5 (0x00000020) -#define MCF_ETPU_ECPSSR_SR6 (0x00000040) -#define MCF_ETPU_ECPSSR_SR7 (0x00000080) -#define MCF_ETPU_ECPSSR_SR8 (0x00000100) -#define MCF_ETPU_ECPSSR_SR9 (0x00000200) -#define MCF_ETPU_ECPSSR_SR10 (0x00000400) -#define MCF_ETPU_ECPSSR_SR11 (0x00000800) -#define MCF_ETPU_ECPSSR_SR12 (0x00001000) -#define MCF_ETPU_ECPSSR_SR13 (0x00002000) -#define MCF_ETPU_ECPSSR_SR14 (0x00004000) -#define MCF_ETPU_ECPSSR_SR15 (0x00008000) -#define MCF_ETPU_ECPSSR_SR16 (0x00010000) -#define MCF_ETPU_ECPSSR_SR17 (0x00020000) -#define MCF_ETPU_ECPSSR_SR18 (0x00040000) -#define MCF_ETPU_ECPSSR_SR19 (0x00080000) -#define MCF_ETPU_ECPSSR_SR20 (0x00100000) -#define MCF_ETPU_ECPSSR_SR21 (0x00200000) -#define MCF_ETPU_ECPSSR_SR22 (0x00400000) -#define MCF_ETPU_ECPSSR_SR23 (0x00800000) -#define MCF_ETPU_ECPSSR_SR24 (0x01000000) -#define MCF_ETPU_ECPSSR_SR25 (0x02000000) -#define MCF_ETPU_ECPSSR_SR26 (0x04000000) -#define MCF_ETPU_ECPSSR_SR27 (0x08000000) -#define MCF_ETPU_ECPSSR_SR28 (0x10000000) -#define MCF_ETPU_ECPSSR_SR29 (0x20000000) -#define MCF_ETPU_ECPSSR_SR30 (0x40000000) -#define MCF_ETPU_ECPSSR_SR31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECSSR */ -#define MCF_ETPU_ECSSR_SS0 (0x00000001) -#define MCF_ETPU_ECSSR_SS1 (0x00000002) -#define MCF_ETPU_ECSSR_SS2 (0x00000004) -#define MCF_ETPU_ECSSR_SS3 (0x00000008) -#define MCF_ETPU_ECSSR_SS4 (0x00000010) -#define MCF_ETPU_ECSSR_SS5 (0x00000020) -#define MCF_ETPU_ECSSR_SS6 (0x00000040) -#define MCF_ETPU_ECSSR_SS7 (0x00000080) -#define MCF_ETPU_ECSSR_SS8 (0x00000100) -#define MCF_ETPU_ECSSR_SS9 (0x00000200) -#define MCF_ETPU_ECSSR_SS10 (0x00000400) -#define MCF_ETPU_ECSSR_SS11 (0x00000800) -#define MCF_ETPU_ECSSR_SS12 (0x00001000) -#define MCF_ETPU_ECSSR_SS13 (0x00002000) -#define MCF_ETPU_ECSSR_SS14 (0x00004000) -#define MCF_ETPU_ECSSR_SS15 (0x00008000) -#define MCF_ETPU_ECSSR_SS16 (0x00010000) -#define MCF_ETPU_ECSSR_SS17 (0x00020000) -#define MCF_ETPU_ECSSR_SS18 (0x00040000) -#define MCF_ETPU_ECSSR_SS19 (0x00080000) -#define MCF_ETPU_ECSSR_SS20 (0x00100000) -#define MCF_ETPU_ECSSR_SS21 (0x00200000) -#define MCF_ETPU_ECSSR_SS22 (0x00400000) -#define MCF_ETPU_ECSSR_SS23 (0x00800000) -#define MCF_ETPU_ECSSR_SS24 (0x01000000) -#define MCF_ETPU_ECSSR_SS25 (0x02000000) -#define MCF_ETPU_ECSSR_SS26 (0x04000000) -#define MCF_ETPU_ECSSR_SS27 (0x08000000) -#define MCF_ETPU_ECSSR_SS28 (0x10000000) -#define MCF_ETPU_ECSSR_SS29 (0x20000000) -#define MCF_ETPU_ECSSR_SS30 (0x40000000) -#define MCF_ETPU_ECSSR_SS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECnSCR */ -#define MCF_ETPU_ECnSCR_FM(x) (((x)&0x00000003)<<0) -#define MCF_ETPU_ECnSCR_OBE (0x00002000) -#define MCF_ETPU_ECnSCR_OPS (0x00004000) -#define MCF_ETPU_ECnSCR_IPS (0x00008000) -#define MCF_ETPU_ECnSCR_DTROS (0x00400000) -#define MCF_ETPU_ECnSCR_DTRS (0x00800000) -#define MCF_ETPU_ECnSCR_CIOS (0x40000000) -#define MCF_ETPU_ECnSCR_CIS (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECnCR */ -#define MCF_ETPU_ECnCR_CPBA(x) (((x)&0x000007FF)<<0) -#define MCF_ETPU_ECnCR_OPOL (0x00004000) -#define MCF_ETPU_ECnCR_ODIS (0x00008000) -#define MCF_ETPU_ECnCR_CFS(x) (((x)&0x0000001F)<<16) -#define MCF_ETPU_ECnCR_ETCS (0x01000000) -#define MCF_ETPU_ECnCR_CPR(x) (((x)&0x00000003)<<28) -#define MCF_ETPU_ECnCR_DTRE (0x40000000) -#define MCF_ETPU_ECnCR_CIE (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECnHSSR */ -#define MCF_ETPU_ECnHSSR_HSR(x) (((x)&0x00000007)<<0) - -/********************************************************************/ - -#endif /* __MCF523X_ETPU_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_etpu_struc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_etpu_struc.h deleted file mode 100644 index 93547be17..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_etpu_struc.h +++ /dev/null @@ -1,980 +0,0 @@ -/**************************************************************************/ -/* FILE NAME: mcf523x_eTPU_struc.h */ -/* COPYRIGHT (c) Freescale Semiconductor 2004 */ -/* VERSION: 0.02 All Rights Reserved */ -/* */ -/* DESCRIPTION: */ -/* This file contains eTPU register and bit field definitions for MCF523x.*/ -/* Part of mpc5554.h auto-generated code by J.Loeliger. */ -/*========================================================================*/ -/* UPDATE HISTORY */ -/* REV AUTHOR DATE DESCRIPTION OF CHANGE */ -/* --- ----------- --------- --------------------- */ -/* 0.01 J.Loeliger 30/Apr/04 Initial version of file. */ -/* M.Princ */ -/* 0.02 J.Loeliger 20/Jul/04 Update eTPU structure to match mpc5554.*/ -/**************************************************************************/ - - -#ifndef _MCF523x_eTPU_struc_H_ -#define _MCF523x_eTPU_struc_H_ - -#include "typedefs.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -#ifdef __MWERKS__ -#pragma push -#pragma ANSI_strict off -#endif - -/***************************Configuration Registers**************************/ - - struct ETPU_tag - { - union - { /* MODULE CONFIGURATION REGISTER */ - vuint32_t R; - struct - { - vuint32_t GEC:1; /* Global Exception Clear */ - vuint32_t:3; - vuint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */ - - vuint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */ - - vuint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */ - - vuint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */ - - vuint32_t:3; - vuint32_t SCMSIZE:5; /* Shared Code Memory size */ - vuint32_t:5; - vuint32_t SCMMISF:1; /* SCM MISC Flag */ - vuint32_t SCMMISEN:1; /* SCM MISC Enable */ - vuint32_t:2; - vuint32_t VIS:1; /* SCM Visability */ - vuint32_t:5; - vuint32_t GTBE:1; /* Global Time Base Enable */ - } B; - } MCR; - - union - { /* COHERENT DUAL-PARAMETER CONTROL */ - vuint32_t R; - struct - { - vuint32_t STS:1; /* Start Status bit */ - vuint32_t CTBASE:5; /* Channel Transfer Base */ - vuint32_t PBASE:10; /* Parameter Buffer Base Address */ - vuint32_t PWIDTH:1; /* Parameter Width */ - vuint32_t PARAM0:7; /* Channel Parameter 0 */ - vuint32_t WR:1; - vuint32_t PARAM1:7; /* Channel Parameter 1 */ - } B; - } CDCR; - - uint32_t etpu_reserved1; - - union - { /* MISC Compare Register */ - uint32_t R; - } MISCCMPR; - - uint32_t etpu_reserved2; - - union - { /* ETPU_A Configuration Register */ - vuint32_t R; - struct - { - vuint32_t FEND:1; /* Force END */ - vuint32_t MDIS:1; /* Low power Stop */ - vuint32_t:1; - vuint32_t STF:1; /* Stop Flag */ - vuint32_t:4; - vuint32_t HLTF:1; /* Halt Mode Flag */ - vuint32_t:4; - vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */ - vuint32_t CDFC:2; - vuint32_t:9; - vuint32_t ETB:5; /* Entry Table Base */ - } B; - } ECR_A; - - union - { /* ETPU_B Configuration Register */ - vuint32_t R; - struct - { - vuint32_t FEND:1; /* Force END */ - vuint32_t MDIS:1; /* Low power Stop */ - vuint32_t:1; - vuint32_t STF:1; /* Stop Flag */ - vuint32_t:4; - vuint32_t HLTF:1; /* Halt Mode Flag */ - vuint32_t:4; - vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */ - vuint32_t CDFC:2; - vuint32_t:9; - vuint32_t ETB:5; /* Entry Table Base */ - } B; - } ECR_B; - - uint32_t etpu_reserved4; - - union - { /* ETPU_A Timebase Configuration Register */ - uint32_t R; - struct - { - uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ - uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ - uint32_t:1; - uint32_t AM:1; /* Angle Mode */ - uint32_t:3; - uint32_t TCR2P:6; /* TCR2 Prescaler Control */ - uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ - uint32_t:6; - uint32_t TCR1P:8; /* TCR1 Prescaler Control */ - } B; - } TBCR_A; - - union - { /* ETPU_A TCR1 Visibility Register */ - vuint32_t R; - } TB1R_A; - - union - { /* ETPU_A TCR2 Visibility Register */ - vuint32_t R; - } TB2R_A; - - union - { /* ETPU_A STAC Configuration Register */ - vuint32_t R; - struct - { - vuint32_t REN1:1; /* Resource Enable TCR1 */ - vuint32_t RSC1:1; /* Resource Control TCR1 */ - vuint32_t VALID1:1; /* TCR1 Server Valid */ - vuint32_t:9; - vuint32_t SRV1:4; /* Resource Server Slot */ - vuint32_t REN2:1; /* Resource Enable TCR2 */ - vuint32_t RSC2:1; /* Resource Control TCR2 */ - vuint32_t VALID2:1; /* TCR2 Server Valid */ - vuint32_t:9; - vuint32_t SRV2:4; /* Resource Server Slot */ - } B; - } REDCR_A; - - uint32_t etpu_reserved5[4]; - - union - { /* ETPU_B Timebase Configuration Register */ - uint32_t R; - struct - { - uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ - uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ - uint32_t:1; - uint32_t AM:1; /* Angle Mode */ - uint32_t:3; - uint32_t TCR2P:6; /* TCR2 Prescaler Control */ - uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ - uint32_t:6; - uint32_t TCR1P:8; /* TCR1 Prescaler Control */ - } B; - } TBCR_B; - - union - { /* ETPU_B TCR1 Visibility Register */ - vuint32_t R; - } TB1R_B; - - union - { /* ETPU_B TCR2 Visibility Register */ - vuint32_t R; - } TB2R_B; - - union - { /* ETPU_B STAC Configuration Register */ - vuint32_t R; - struct - { - vuint32_t REN1:1; /* Resource Enable TCR1 */ - vuint32_t RSC1:1; /* Resource Control TCR1 */ - vuint32_t VALID1:1; /* TCR1 Server Valid */ - vuint32_t:9; - vuint32_t SRV1:4; /* Resource Server Slot */ - vuint32_t REN2:1; /* Resource Enable TCR2 */ - vuint32_t RSC2:1; /* Resource Control TCR2 */ - vuint32_t VALID2:1; /* TCR2 Server Valid */ - vuint32_t:9; - vuint32_t SRV2:4; /* Resource Server Slot */ - } B; - } REDCR_B; - - uint32_t etpu_reserved7[108]; - -/*****************************Status and Control Registers**************************/ - - union - { /* ETPU_A Channel Interrut Status */ - vuint32_t R; - struct - { - vuint32_t CIS31:1; /* Channel 31 Interrut Status */ - vuint32_t CIS30:1; /* Channel 30 Interrut Status */ - vuint32_t CIS29:1; /* Channel 29 Interrut Status */ - vuint32_t CIS28:1; /* Channel 28 Interrut Status */ - vuint32_t CIS27:1; /* Channel 27 Interrut Status */ - vuint32_t CIS26:1; /* Channel 26 Interrut Status */ - vuint32_t CIS25:1; /* Channel 25 Interrut Status */ - vuint32_t CIS24:1; /* Channel 24 Interrut Status */ - vuint32_t CIS23:1; /* Channel 23 Interrut Status */ - vuint32_t CIS22:1; /* Channel 22 Interrut Status */ - vuint32_t CIS21:1; /* Channel 21 Interrut Status */ - vuint32_t CIS20:1; /* Channel 20 Interrut Status */ - vuint32_t CIS19:1; /* Channel 19 Interrut Status */ - vuint32_t CIS18:1; /* Channel 18 Interrut Status */ - vuint32_t CIS17:1; /* Channel 17 Interrut Status */ - vuint32_t CIS16:1; /* Channel 16 Interrut Status */ - vuint32_t CIS15:1; /* Channel 15 Interrut Status */ - vuint32_t CIS14:1; /* Channel 14 Interrut Status */ - vuint32_t CIS13:1; /* Channel 13 Interrut Status */ - vuint32_t CIS12:1; /* Channel 12 Interrut Status */ - vuint32_t CIS11:1; /* Channel 11 Interrut Status */ - vuint32_t CIS10:1; /* Channel 10 Interrut Status */ - vuint32_t CIS9:1; /* Channel 9 Interrut Status */ - vuint32_t CIS8:1; /* Channel 8 Interrut Status */ - vuint32_t CIS7:1; /* Channel 7 Interrut Status */ - vuint32_t CIS6:1; /* Channel 6 Interrut Status */ - vuint32_t CIS5:1; /* Channel 5 Interrut Status */ - vuint32_t CIS4:1; /* Channel 4 Interrut Status */ - vuint32_t CIS3:1; /* Channel 3 Interrut Status */ - vuint32_t CIS2:1; /* Channel 2 Interrut Status */ - vuint32_t CIS1:1; /* Channel 1 Interrut Status */ - vuint32_t CIS0:1; /* Channel 0 Interrut Status */ - } B; - } CISR_A; - - union - { /* ETPU_B Channel Interruput Status */ - vuint32_t R; - struct - { - vuint32_t CIS31:1; /* Channel 31 Interrut Status */ - vuint32_t CIS30:1; /* Channel 30 Interrut Status */ - vuint32_t CIS29:1; /* Channel 29 Interrut Status */ - vuint32_t CIS28:1; /* Channel 28 Interrut Status */ - vuint32_t CIS27:1; /* Channel 27 Interrut Status */ - vuint32_t CIS26:1; /* Channel 26 Interrut Status */ - vuint32_t CIS25:1; /* Channel 25 Interrut Status */ - vuint32_t CIS24:1; /* Channel 24 Interrut Status */ - vuint32_t CIS23:1; /* Channel 23 Interrut Status */ - vuint32_t CIS22:1; /* Channel 22 Interrut Status */ - vuint32_t CIS21:1; /* Channel 21 Interrut Status */ - vuint32_t CIS20:1; /* Channel 20 Interrut Status */ - vuint32_t CIS19:1; /* Channel 19 Interrut Status */ - vuint32_t CIS18:1; /* Channel 18 Interrut Status */ - vuint32_t CIS17:1; /* Channel 17 Interrut Status */ - vuint32_t CIS16:1; /* Channel 16 Interrut Status */ - vuint32_t CIS15:1; /* Channel 15 Interrut Status */ - vuint32_t CIS14:1; /* Channel 14 Interrut Status */ - vuint32_t CIS13:1; /* Channel 13 Interrut Status */ - vuint32_t CIS12:1; /* Channel 12 Interrut Status */ - vuint32_t CIS11:1; /* Channel 11 Interrut Status */ - vuint32_t CIS10:1; /* Channel 10 Interrut Status */ - vuint32_t CIS9:1; /* Channel 9 Interrut Status */ - vuint32_t CIS8:1; /* Channel 8 Interrut Status */ - vuint32_t CIS7:1; /* Channel 7 Interrut Status */ - vuint32_t CIS6:1; /* Channel 6 Interrut Status */ - vuint32_t CIS5:1; /* Channel 5 Interrut Status */ - vuint32_t CIS4:1; /* Channel 4 Interrut Status */ - vuint32_t CIS3:1; /* Channel 3 Interrut Status */ - vuint32_t CIS2:1; /* Channel 2 Interrut Status */ - vuint32_t CIS1:1; /* Channel 1 Interrupt Status */ - vuint32_t CIS0:1; /* Channel 0 Interrupt Status */ - } B; - } CISR_B; - - uint32_t etpu_reserved9[2]; - - union - { /* ETPU_A Data Transfer Request Status */ - vuint32_t R; - struct - { - vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ - vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ - vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ - vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ - vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ - vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ - vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ - vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ - vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ - vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ - vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ - vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ - vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ - vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ - vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ - vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ - vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ - vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ - vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ - vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ - vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ - vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ - vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ - vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ - vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ - vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ - vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ - vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ - vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ - vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ - vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ - vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ - } B; - } CDTRSR_A; - - union - { /* ETPU_B Data Transfer Request Status */ - vuint32_t R; - struct - { - vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ - vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ - vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ - vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ - vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ - vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ - vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ - vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ - vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ - vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ - vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ - vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ - vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ - vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ - vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ - vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ - vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ - vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ - vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ - vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ - vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ - vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ - vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ - vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ - vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ - vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ - vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ - vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ - vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ - vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ - vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ - vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ - } B; - } CDTRSR_B; - - uint32_t etpu_reserved11[2]; - - union - { /* ETPU_A Interruput Overflow Status */ - vuint32_t R; - struct - { - vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ - vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ - vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ - vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ - vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ - vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ - vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ - vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ - vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ - vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ - vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ - vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ - vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ - vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ - vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ - vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ - vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ - vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ - vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ - vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ - vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ - vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ - vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ - vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ - vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ - vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ - vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ - vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ - vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ - vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ - vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ - vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ - } B; - } CIOSR_A; - - union - { /* ETPU_B Interruput Overflow Status */ - vuint32_t R; - struct - { - vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ - vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ - vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ - vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ - vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ - vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ - vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ - vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ - vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ - vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ - vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ - vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ - vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ - vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ - vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ - vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ - vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ - vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ - vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ - vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ - vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ - vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ - vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ - vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ - vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ - vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ - vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ - vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ - vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ - vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ - vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ - vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ - } B; - } CIOSR_B; - - uint32_t etpu_reserved13[2]; - - union - { /* ETPU_A Data Transfer Overflow Status */ - vuint32_t R; - struct - { - vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ - vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ - vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ - vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ - vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ - vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ - vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ - vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ - vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ - vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ - vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ - vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ - vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ - vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ - vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ - vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ - vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ - vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ - vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ - vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ - vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ - vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ - vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ - vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ - vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ - vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ - vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ - vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ - vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ - vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ - vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ - vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ - } B; - } CDTROSR_A; - - union - { /* ETPU_B Data Transfer Overflow Status */ - vuint32_t R; - struct - { - vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ - vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ - vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ - vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ - vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ - vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ - vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ - vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ - vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ - vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ - vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ - vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ - vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ - vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ - vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ - vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ - vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ - vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ - vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ - vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ - vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ - vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ - vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ - vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ - vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ - vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ - vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ - vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ - vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ - vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ - vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ - vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ - } B; - } CDTROSR_B; - - uint32_t etpu_reserved15[2]; - - union - { /* ETPU_A Channel Interruput Enable */ - vuint32_t R; - struct - { - vuint32_t CIE31:1; /* Channel 31 Interruput Enable */ - vuint32_t CIE30:1; /* Channel 30 Interruput Enable */ - vuint32_t CIE29:1; /* Channel 29 Interruput Enable */ - vuint32_t CIE28:1; /* Channel 28 Interruput Enable */ - vuint32_t CIE27:1; /* Channel 27 Interruput Enable */ - vuint32_t CIE26:1; /* Channel 26 Interruput Enable */ - vuint32_t CIE25:1; /* Channel 25 Interruput Enable */ - vuint32_t CIE24:1; /* Channel 24 Interruput Enable */ - vuint32_t CIE23:1; /* Channel 23 Interruput Enable */ - vuint32_t CIE22:1; /* Channel 22 Interruput Enable */ - vuint32_t CIE21:1; /* Channel 21 Interruput Enable */ - vuint32_t CIE20:1; /* Channel 20 Interruput Enable */ - vuint32_t CIE19:1; /* Channel 19 Interruput Enable */ - vuint32_t CIE18:1; /* Channel 18 Interruput Enable */ - vuint32_t CIE17:1; /* Channel 17 Interruput Enable */ - vuint32_t CIE16:1; /* Channel 16 Interruput Enable */ - vuint32_t CIE15:1; /* Channel 15 Interruput Enable */ - vuint32_t CIE14:1; /* Channel 14 Interruput Enable */ - vuint32_t CIE13:1; /* Channel 13 Interruput Enable */ - vuint32_t CIE12:1; /* Channel 12 Interruput Enable */ - vuint32_t CIE11:1; /* Channel 11 Interruput Enable */ - vuint32_t CIE10:1; /* Channel 10 Interruput Enable */ - vuint32_t CIE9:1; /* Channel 9 Interruput Enable */ - vuint32_t CIE8:1; /* Channel 8 Interruput Enable */ - vuint32_t CIE7:1; /* Channel 7 Interruput Enable */ - vuint32_t CIE6:1; /* Channel 6 Interruput Enable */ - vuint32_t CIE5:1; /* Channel 5 Interruput Enable */ - vuint32_t CIE4:1; /* Channel 4 Interruput Enable */ - vuint32_t CIE3:1; /* Channel 3 Interruput Enable */ - vuint32_t CIE2:1; /* Channel 2 Interruput Enable */ - vuint32_t CIE1:1; /* Channel 1 Interruput Enable */ - vuint32_t CIE0:1; /* Channel 0 Interruput Enable */ - } B; - } CIER_A; - - union - { /* ETPU_B Channel Interruput Enable */ - vuint32_t R; - struct - { - vuint32_t CIE31:1; /* Channel 31 Interruput Enable */ - vuint32_t CIE30:1; /* Channel 30 Interruput Enable */ - vuint32_t CIE29:1; /* Channel 29 Interruput Enable */ - vuint32_t CIE28:1; /* Channel 28 Interruput Enable */ - vuint32_t CIE27:1; /* Channel 27 Interruput Enable */ - vuint32_t CIE26:1; /* Channel 26 Interruput Enable */ - vuint32_t CIE25:1; /* Channel 25 Interruput Enable */ - vuint32_t CIE24:1; /* Channel 24 Interruput Enable */ - vuint32_t CIE23:1; /* Channel 23 Interruput Enable */ - vuint32_t CIE22:1; /* Channel 22 Interruput Enable */ - vuint32_t CIE21:1; /* Channel 21 Interruput Enable */ - vuint32_t CIE20:1; /* Channel 20 Interruput Enable */ - vuint32_t CIE19:1; /* Channel 19 Interruput Enable */ - vuint32_t CIE18:1; /* Channel 18 Interruput Enable */ - vuint32_t CIE17:1; /* Channel 17 Interruput Enable */ - vuint32_t CIE16:1; /* Channel 16 Interruput Enable */ - vuint32_t CIE15:1; /* Channel 15 Interruput Enable */ - vuint32_t CIE14:1; /* Channel 14 Interruput Enable */ - vuint32_t CIE13:1; /* Channel 13 Interruput Enable */ - vuint32_t CIE12:1; /* Channel 12 Interruput Enable */ - vuint32_t CIE11:1; /* Channel 11 Interruput Enable */ - vuint32_t CIE10:1; /* Channel 10 Interruput Enable */ - vuint32_t CIE9:1; /* Channel 9 Interruput Enable */ - vuint32_t CIE8:1; /* Channel 8 Interruput Enable */ - vuint32_t CIE7:1; /* Channel 7 Interruput Enable */ - vuint32_t CIE6:1; /* Channel 6 Interruput Enable */ - vuint32_t CIE5:1; /* Channel 5 Interruput Enable */ - vuint32_t CIE4:1; /* Channel 4 Interruput Enable */ - vuint32_t CIE3:1; /* Channel 3 Interruput Enable */ - vuint32_t CIE2:1; /* Channel 2 Interruput Enable */ - vuint32_t CIE1:1; /* Channel 1 Interruput Enable */ - vuint32_t CIE0:1; /* Channel 0 Interruput Enable */ - } B; - } CIER_B; - - uint32_t etpu_reserved17[2]; - - union - { /* ETPU_A Channel Data Transfer Request Enable */ - vuint32_t R; - struct - { - vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ - vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ - vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ - vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ - vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ - vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ - vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ - vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ - vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ - vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ - vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ - vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ - vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ - vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ - vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ - vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ - vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ - vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ - vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ - vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ - vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ - vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ - vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ - vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ - vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ - vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ - vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ - vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ - vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ - vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ - vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ - vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ - } B; - } CDTRER_A; - - union - { /* ETPU_B Channel Data Transfer Request Enable */ - vuint32_t R; - struct - { - vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ - vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ - vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ - vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ - vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ - vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ - vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ - vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ - vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ - vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ - vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ - vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ - vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ - vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ - vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ - vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ - vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ - vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ - vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ - vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ - vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ - vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ - vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ - vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ - vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ - vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ - vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ - vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ - vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ - vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ - vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ - vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ - } B; - } CDTRER_B; - - uint32_t etpu_reserved20[10]; - union - { /* ETPU_A Channel Pending Service Status */ - vuint32_t R; - struct - { - vuint32_t SR31:1; /* Channel 31 Pending Service Status */ - vuint32_t SR30:1; /* Channel 30 Pending Service Status */ - vuint32_t SR29:1; /* Channel 29 Pending Service Status */ - vuint32_t SR28:1; /* Channel 28 Pending Service Status */ - vuint32_t SR27:1; /* Channel 27 Pending Service Status */ - vuint32_t SR26:1; /* Channel 26 Pending Service Status */ - vuint32_t SR25:1; /* Channel 25 Pending Service Status */ - vuint32_t SR24:1; /* Channel 24 Pending Service Status */ - vuint32_t SR23:1; /* Channel 23 Pending Service Status */ - vuint32_t SR22:1; /* Channel 22 Pending Service Status */ - vuint32_t SR21:1; /* Channel 21 Pending Service Status */ - vuint32_t SR20:1; /* Channel 20 Pending Service Status */ - vuint32_t SR19:1; /* Channel 19 Pending Service Status */ - vuint32_t SR18:1; /* Channel 18 Pending Service Status */ - vuint32_t SR17:1; /* Channel 17 Pending Service Status */ - vuint32_t SR16:1; /* Channel 16 Pending Service Status */ - vuint32_t SR15:1; /* Channel 15 Pending Service Status */ - vuint32_t SR14:1; /* Channel 14 Pending Service Status */ - vuint32_t SR13:1; /* Channel 13 Pending Service Status */ - vuint32_t SR12:1; /* Channel 12 Pending Service Status */ - vuint32_t SR11:1; /* Channel 11 Pending Service Status */ - vuint32_t SR10:1; /* Channel 10 Pending Service Status */ - vuint32_t SR9:1; /* Channel 9 Pending Service Status */ - vuint32_t SR8:1; /* Channel 8 Pending Service Status */ - vuint32_t SR7:1; /* Channel 7 Pending Service Status */ - vuint32_t SR6:1; /* Channel 6 Pending Service Status */ - vuint32_t SR5:1; /* Channel 5 Pending Service Status */ - vuint32_t SR4:1; /* Channel 4 Pending Service Status */ - vuint32_t SR3:1; /* Channel 3 Pending Service Status */ - vuint32_t SR2:1; /* Channel 2 Pending Service Status */ - vuint32_t SR1:1; /* Channel 1 Pending Service Status */ - vuint32_t SR0:1; /* Channel 0 Pending Service Status */ - } B; - } CPSSR_A; - - union - { /* ETPU_B Channel Pending Service Status */ - vuint32_t R; - struct - { - vuint32_t SR31:1; /* Channel 31 Pending Service Status */ - vuint32_t SR30:1; /* Channel 30 Pending Service Status */ - vuint32_t SR29:1; /* Channel 29 Pending Service Status */ - vuint32_t SR28:1; /* Channel 28 Pending Service Status */ - vuint32_t SR27:1; /* Channel 27 Pending Service Status */ - vuint32_t SR26:1; /* Channel 26 Pending Service Status */ - vuint32_t SR25:1; /* Channel 25 Pending Service Status */ - vuint32_t SR24:1; /* Channel 24 Pending Service Status */ - vuint32_t SR23:1; /* Channel 23 Pending Service Status */ - vuint32_t SR22:1; /* Channel 22 Pending Service Status */ - vuint32_t SR21:1; /* Channel 21 Pending Service Status */ - vuint32_t SR20:1; /* Channel 20 Pending Service Status */ - vuint32_t SR19:1; /* Channel 19 Pending Service Status */ - vuint32_t SR18:1; /* Channel 18 Pending Service Status */ - vuint32_t SR17:1; /* Channel 17 Pending Service Status */ - vuint32_t SR16:1; /* Channel 16 Pending Service Status */ - vuint32_t SR15:1; /* Channel 15 Pending Service Status */ - vuint32_t SR14:1; /* Channel 14 Pending Service Status */ - vuint32_t SR13:1; /* Channel 13 Pending Service Status */ - vuint32_t SR12:1; /* Channel 12 Pending Service Status */ - vuint32_t SR11:1; /* Channel 11 Pending Service Status */ - vuint32_t SR10:1; /* Channel 10 Pending Service Status */ - vuint32_t SR9:1; /* Channel 9 Pending Service Status */ - vuint32_t SR8:1; /* Channel 8 Pending Service Status */ - vuint32_t SR7:1; /* Channel 7 Pending Service Status */ - vuint32_t SR6:1; /* Channel 6 Pending Service Status */ - vuint32_t SR5:1; /* Channel 5 Pending Service Status */ - vuint32_t SR4:1; /* Channel 4 Pending Service Status */ - vuint32_t SR3:1; /* Channel 3 Pending Service Status */ - vuint32_t SR2:1; /* Channel 2 Pending Service Status */ - vuint32_t SR1:1; /* Channel 1 Pending Service Status */ - vuint32_t SR0:1; /* Channel 0 Pending Service Status */ - } B; - } CPSSR_B; - - uint32_t etpu_reserved20a[2]; - - union - { /* ETPU_A Channel Service Status */ - vuint32_t R; - struct - { - vuint32_t SS31:1; /* Channel 31 Service Status */ - vuint32_t SS30:1; /* Channel 30 Service Status */ - vuint32_t SS29:1; /* Channel 29 Service Status */ - vuint32_t SS28:1; /* Channel 28 Service Status */ - vuint32_t SS27:1; /* Channel 27 Service Status */ - vuint32_t SS26:1; /* Channel 26 Service Status */ - vuint32_t SS25:1; /* Channel 25 Service Status */ - vuint32_t SS24:1; /* Channel 24 Service Status */ - vuint32_t SS23:1; /* Channel 23 Service Status */ - vuint32_t SS22:1; /* Channel 22 Service Status */ - vuint32_t SS21:1; /* Channel 21 Service Status */ - vuint32_t SS20:1; /* Channel 20 Service Status */ - vuint32_t SS19:1; /* Channel 19 Service Status */ - vuint32_t SS18:1; /* Channel 18 Service Status */ - vuint32_t SS17:1; /* Channel 17 Service Status */ - vuint32_t SS16:1; /* Channel 16 Service Status */ - vuint32_t SS15:1; /* Channel 15 Service Status */ - vuint32_t SS14:1; /* Channel 14 Service Status */ - vuint32_t SS13:1; /* Channel 13 Service Status */ - vuint32_t SS12:1; /* Channel 12 Service Status */ - vuint32_t SS11:1; /* Channel 11 Service Status */ - vuint32_t SS10:1; /* Channel 10 Service Status */ - vuint32_t SS9:1; /* Channel 9 Service Status */ - vuint32_t SS8:1; /* Channel 8 Service Status */ - vuint32_t SS7:1; /* Channel 7 Service Status */ - vuint32_t SS6:1; /* Channel 6 Service Status */ - vuint32_t SS5:1; /* Channel 5 Service Status */ - vuint32_t SS4:1; /* Channel 4 Service Status */ - vuint32_t SS3:1; /* Channel 3 Service Status */ - vuint32_t SS2:1; /* Channel 2 Service Status */ - vuint32_t SS1:1; /* Channel 1 Service Status */ - vuint32_t SS0:1; /* Channel 0 Service Status */ - } B; - } CSSR_A; - - union - { /* ETPU_B Channel Service Status */ - vuint32_t R; - struct - { - vuint32_t SS31:1; /* Channel 31 Service Status */ - vuint32_t SS30:1; /* Channel 30 Service Status */ - vuint32_t SS29:1; /* Channel 29 Service Status */ - vuint32_t SS28:1; /* Channel 28 Service Status */ - vuint32_t SS27:1; /* Channel 27 Service Status */ - vuint32_t SS26:1; /* Channel 26 Service Status */ - vuint32_t SS25:1; /* Channel 25 Service Status */ - vuint32_t SS24:1; /* Channel 24 Service Status */ - vuint32_t SS23:1; /* Channel 23 Service Status */ - vuint32_t SS22:1; /* Channel 22 Service Status */ - vuint32_t SS21:1; /* Channel 21 Service Status */ - vuint32_t SS20:1; /* Channel 20 Service Status */ - vuint32_t SS19:1; /* Channel 19 Service Status */ - vuint32_t SS18:1; /* Channel 18 Service Status */ - vuint32_t SS17:1; /* Channel 17 Service Status */ - vuint32_t SS16:1; /* Channel 16 Service Status */ - vuint32_t SS15:1; /* Channel 15 Service Status */ - vuint32_t SS14:1; /* Channel 14 Service Status */ - vuint32_t SS13:1; /* Channel 13 Service Status */ - vuint32_t SS12:1; /* Channel 12 Service Status */ - vuint32_t SS11:1; /* Channel 11 Service Status */ - vuint32_t SS10:1; /* Channel 10 Service Status */ - vuint32_t SS9:1; /* Channel 9 Service Status */ - vuint32_t SS8:1; /* Channel 8 Service Status */ - vuint32_t SS7:1; /* Channel 7 Service Status */ - vuint32_t SS6:1; /* Channel 6 Service Status */ - vuint32_t SS5:1; /* Channel 5 Service Status */ - vuint32_t SS4:1; /* Channel 4 Service Status */ - vuint32_t SS3:1; /* Channel 3 Service Status */ - vuint32_t SS2:1; /* Channel 2 Service Status */ - vuint32_t SS1:1; /* Channel 1 Service Status */ - vuint32_t SS0:1; /* Channel 0 Service Status */ - } B; - } CSSR_B; - - uint32_t etpu_reserved23[90]; - -/*****************************Channels********************************/ - - struct - { - union - { - vuint32_t R; /* Channel Configuration Register */ - struct - { - vuint32_t CIE:1; /* Channel Interruput Enable */ - vuint32_t DTRE:1; /* Data Transfer Request Enable */ - vuint32_t CPR:2; /* Channel Priority */ - vuint32_t:3; - vuint32_t ETCS:1; /* Entry Table Condition Select */ - vuint32_t:3; - vuint32_t CFS:5; /* Channel Function Select */ - vuint32_t ODIS:1; /* Output disable */ - vuint32_t OPOL:1; /* output polarity */ - vuint32_t:3; - vuint32_t CPBA:11; /* Channel Parameter Base Address */ - } B; - } CR; - union - { - vuint32_t R; /* Channel Status Control Register */ - struct - { - vuint32_t CIS:1; /* Channel Interruput Status */ - vuint32_t CIOS:1; /* Channel Interruput Overflow Status */ - vuint32_t:6; - vuint32_t DTRS:1; /* Data Transfer Status */ - vuint32_t DTROS:1; /* Data Transfer Overflow Status */ - vuint32_t:6; - vuint32_t IPS:1; /* Input Pin State */ - vuint32_t OPS:1; /* Output Pin State */ - vuint32_t OBE:1; /* Output Buffer Enable */ - vuint32_t:11; - vuint32_t FM1:1; /* Function mode */ - vuint32_t FM0:1; /* Function mode */ - } B; - } SCR; - union - { - vuint32_t R; /* Channel Host Service Request Register */ - struct - { - vuint32_t:29; /* Host Service Request */ - vuint32_t HSR:3; - } B; - } HSRR; - uint32_t etpu_reserved23; - } CHAN[127]; - - }; - -// Define instances of modules -#define ETPU (*( struct ETPU_tag *) 0x401D0000) -#define ETPU_DATA_RAM (*( uint32_t *) 0x401D8000) -#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0x401DC000) -#define ETPU_DATA_RAM_END (0x401D9800) -#define CODE_RAM (*( uint32_t *) 0x401E0000) - -#ifdef __MWERKS__ -#pragma pop -#endif - -#ifdef __cplusplus -} -#endif -#endif /* ifdef _MCF523x_eTPU_struc_H */ - - -/********************************************************************* - * - * Copyright: - * Freescale Semiconductor, INC. All Rights Reserved. - * You are hereby granted a copyright license to use, modify, and - * distribute the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Freescale - * Semiconductor, Inc. This software is provided on an "AS IS" - * basis and without warranty. - * - * To the maximum extent permitted by applicable law, Freescale - * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, - * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A - * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH - * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) - * AND ANY ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, - * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER - * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Freescale Semiconductor assumes no responsibility for the - * maintenance and support of this software - ********************************************************************/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_fec.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_fec.h deleted file mode 100644 index 19bc720e1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_fec.h +++ /dev/null @@ -1,215 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_fec.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_FEC_H__ -#define __MCF523X_FEC_H__ - -/********************************************************************* -* -* Fast Ethernet Controller (FEC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_FEC_EIR (*(vuint32*)(void*)(&__IPSBAR[0x001004])) -#define MCF_FEC_EIMR (*(vuint32*)(void*)(&__IPSBAR[0x001008])) -#define MCF_FEC_RDAR (*(vuint32*)(void*)(&__IPSBAR[0x001010])) -#define MCF_FEC_TDAR (*(vuint32*)(void*)(&__IPSBAR[0x001014])) -#define MCF_FEC_ECR (*(vuint32*)(void*)(&__IPSBAR[0x001024])) -#define MCF_FEC_MMFR (*(vuint32*)(void*)(&__IPSBAR[0x001040])) -#define MCF_FEC_MSCR (*(vuint32*)(void*)(&__IPSBAR[0x001044])) -#define MCF_FEC_MIBC (*(vuint32*)(void*)(&__IPSBAR[0x001064])) -#define MCF_FEC_RCR (*(vuint32*)(void*)(&__IPSBAR[0x001084])) -#define MCF_FEC_TCR (*(vuint32*)(void*)(&__IPSBAR[0x0010C4])) -#define MCF_FEC_PALR (*(vuint32*)(void*)(&__IPSBAR[0x0010E4])) -#define MCF_FEC_PAUR (*(vuint32*)(void*)(&__IPSBAR[0x0010E8])) -#define MCF_FEC_OPD (*(vuint32*)(void*)(&__IPSBAR[0x0010EC])) -#define MCF_FEC_IAUR (*(vuint32*)(void*)(&__IPSBAR[0x001118])) -#define MCF_FEC_IALR (*(vuint32*)(void*)(&__IPSBAR[0x00111C])) -#define MCF_FEC_GAUR (*(vuint32*)(void*)(&__IPSBAR[0x001120])) -#define MCF_FEC_GALR (*(vuint32*)(void*)(&__IPSBAR[0x001124])) -#define MCF_FEC_TFWR (*(vuint32*)(void*)(&__IPSBAR[0x001144])) -#define MCF_FEC_FRBR (*(vuint32*)(void*)(&__IPSBAR[0x00114C])) -#define MCF_FEC_FRSR (*(vuint32*)(void*)(&__IPSBAR[0x001150])) -#define MCF_FEC_ERDSR (*(vuint32*)(void*)(&__IPSBAR[0x001180])) -#define MCF_FEC_ETDSR (*(vuint32*)(void*)(&__IPSBAR[0x001184])) -#define MCF_FEC_EMRBR (*(vuint32*)(void*)(&__IPSBAR[0x001188])) -#define MCF_FEC_RMON_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001200])) -#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001204])) -#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001208])) -#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00120C])) -#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001210])) -#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001214])) -#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001218])) -#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00121C])) -#define MCF_FEC_RMON_T_JAB (*(vuint32*)(void*)(&__IPSBAR[0x001220])) -#define MCF_FEC_RMON_T_COL (*(vuint32*)(void*)(&__IPSBAR[0x001224])) -#define MCF_FEC_RMON_T_P64 (*(vuint32*)(void*)(&__IPSBAR[0x001228])) -#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x00122C])) -#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x001230])) -#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x001234])) -#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x001238])) -#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x00123C])) -#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x001240])) -#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x001244])) -#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001248])) -#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x00124C])) -#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(void*)(&__IPSBAR[0x001250])) -#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(void*)(&__IPSBAR[0x001254])) -#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(void*)(&__IPSBAR[0x001258])) -#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(void*)(&__IPSBAR[0x00125C])) -#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(void*)(&__IPSBAR[0x001260])) -#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x001264])) -#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(void*)(&__IPSBAR[0x001268])) -#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(void*)(&__IPSBAR[0x00126C])) -#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x001270])) -#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x001274])) -#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001284])) -#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001288])) -#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00128C])) -#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001290])) -#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001294])) -#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001298])) -#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00129C])) -#define MCF_FEC_RMON_R_JAB (*(vuint32*)(void*)(&__IPSBAR[0x0012A0])) -#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(void*)(&__IPSBAR[0x0012A4])) -#define MCF_FEC_RMON_R_P64 (*(vuint32*)(void*)(&__IPSBAR[0x0012A8])) -#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x0012AC])) -#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x0012B0])) -#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x0012B4])) -#define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x0012B8])) -#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x0012C0])) -#define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x0012BC])) -#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x0012C4])) -#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(void*)(&__IPSBAR[0x0012C8])) -#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012CC])) -#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(void*)(&__IPSBAR[0x0012D0])) -#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x0012D4])) -#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x0012D8])) -#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x0012DC])) -#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012E0])) - -/* Bit definitions and macros for MCF_FEC_EIR */ -#define MCF_FEC_EIR_UN (0x00080000) -#define MCF_FEC_EIR_RL (0x00100000) -#define MCF_FEC_EIR_LC (0x00200000) -#define MCF_FEC_EIR_EBERR (0x00400000) -#define MCF_FEC_EIR_MII (0x00800000) -#define MCF_FEC_EIR_RXB (0x01000000) -#define MCF_FEC_EIR_RXF (0x02000000) -#define MCF_FEC_EIR_TXB (0x04000000) -#define MCF_FEC_EIR_TXF (0x08000000) -#define MCF_FEC_EIR_GRA (0x10000000) -#define MCF_FEC_EIR_BABT (0x20000000) -#define MCF_FEC_EIR_BABR (0x40000000) -#define MCF_FEC_EIR_HBERR (0x80000000) - -/* Bit definitions and macros for MCF_FEC_EIMR */ -#define MCF_FEC_EIMR_UN (0x00080000) -#define MCF_FEC_EIMR_RL (0x00100000) -#define MCF_FEC_EIMR_LC (0x00200000) -#define MCF_FEC_EIMR_EBERR (0x00400000) -#define MCF_FEC_EIMR_MII (0x00800000) -#define MCF_FEC_EIMR_RXB (0x01000000) -#define MCF_FEC_EIMR_RXF (0x02000000) -#define MCF_FEC_EIMR_TXB (0x04000000) -#define MCF_FEC_EIMR_TXF (0x08000000) -#define MCF_FEC_EIMR_GRA (0x10000000) -#define MCF_FEC_EIMR_BABT (0x20000000) -#define MCF_FEC_EIMR_BABR (0x40000000) -#define MCF_FEC_EIMR_HBERR (0x80000000) - -/* Bit definitions and macros for MCF_FEC_RDAR */ -#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for MCF_FEC_TDAR */ -#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for MCF_FEC_ECR */ -#define MCF_FEC_ECR_RESET (0x00000001) -#define MCF_FEC_ECR_ETHER_EN (0x00000002) - -/* Bit definitions and macros for MCF_FEC_MMFR */ -#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) -#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) -#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) -#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) -#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) -#define MCF_FEC_MMFR_ST_01 (0x40000000) -#define MCF_FEC_MMFR_OP_READ (0x20000000) -#define MCF_FEC_MMFR_OP_WRITE (0x10000000) -#define MCF_FEC_MMFR_TA_10 (0x00020000) - - -/* Bit definitions and macros for MCF_FEC_MSCR */ -#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) -#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080) - -/* Bit definitions and macros for MCF_FEC_MIBC */ -#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) -#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) - -/* Bit definitions and macros for MCF_FEC_RCR */ -#define MCF_FEC_RCR_LOOP (0x00000001) -#define MCF_FEC_RCR_DRT (0x00000002) -#define MCF_FEC_RCR_MII_MODE (0x00000004) -#define MCF_FEC_RCR_PROM (0x00000008) -#define MCF_FEC_RCR_BC_REJ (0x00000010) -#define MCF_FEC_RCR_FCE (0x00000020) -#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) - -/* Bit definitions and macros for MCF_FEC_TCR */ -#define MCF_FEC_TCR_GTS (0x00000001) -#define MCF_FEC_TCR_HBC (0x00000002) -#define MCF_FEC_TCR_FDEN (0x00000004) -#define MCF_FEC_TCR_TFC_PAUSE (0x00000008) -#define MCF_FEC_TCR_RFC_PAUSE (0x00000010) - -/* Bit definitions and macros for MCF_FEC_PAUR */ -#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_OPD */ -#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_TFWR */ -#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0) - -/* Bit definitions and macros for MCF_FEC_FRBR */ -#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2) - -/* Bit definitions and macros for MCF_FEC_FRSR */ -#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2) - -/* Bit definitions and macros for MCF_FEC_ERDSR */ -#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_FEC_ETDSR */ -#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_FEC_EMRBR */ -#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4) - -/********************************************************************/ - -#endif /* __MCF523X_FEC_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_fmpll.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_fmpll.h deleted file mode 100644 index acf8505ac..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_fmpll.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * File: mcf523x_fmpll.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_FMPLL_H__ -#define __MCF523X_FMPLL_H__ - -/********************************************************************* -* -* Frequency Modulated Phase Locked Loop (FMPLL) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_FMPLL_SYNCR (*(vuint32*)(void*)(&__IPSBAR[0x120000])) -#define MCF_FMPLL_SYNSR (*(vuint32*)(void*)(&__IPSBAR[0x120004])) - -/* Bit definitions and macros for MCF_FMPLL_SYNCR */ -#define MCF_FMPLL_SYNCR_EXP(x) (((x)&0x000003FF)<<0) -#define MCF_FMPLL_SYNCR_DEPTH(x) (((x)&0x00000003)<<10) -#define MCF_FMPLL_SYNCR_RATE (0x00001000) -#define MCF_FMPLL_SYNCR_LOCIRQ (0x00002000) -#define MCF_FMPLL_SYNCR_LOLIRQ (0x00004000) -#define MCF_FMPLL_SYNCR_DISCLK (0x00008000) -#define MCF_FMPLL_SYNCR_LOCRE (0x00010000) -#define MCF_FMPLL_SYNCR_LOLRE (0x00020000) -#define MCF_FMPLL_SYNCR_LOCEN (0x00040000) -#define MCF_FMPLL_SYNCR_RFD(x) (((x)&0x00000007)<<19) -#define MCF_FMPLL_SYNCR_MFD(x) (((x)&0x00000007)<<24) - -/* Bit definitions and macros for MCF_FMPLL_SYNSR */ -#define MCF_FMPLL_SYNSR_CALPASS (0x00000001) -#define MCF_FMPLL_SYNSR_CALDONE (0x00000002) -#define MCF_FMPLL_SYNSR_LOCF (0x00000004) -#define MCF_FMPLL_SYNSR_LOCK (0x00000008) -#define MCF_FMPLL_SYNSR_LOCKS (0x00000010) -#define MCF_FMPLL_SYNSR_PLLREF (0x00000020) -#define MCF_FMPLL_SYNSR_PLLSEL (0x00000040) -#define MCF_FMPLL_SYNSR_MODE (0x00000080) -#define MCF_FMPLL_SYNSR_LOC (0x00000100) -#define MCF_FMPLL_SYNSR_LOLF (0x00000200) - -/********************************************************************/ - -#endif /* __MCF523X_FMPLL_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_gpio.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_gpio.h deleted file mode 100644 index bf1f61311..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_gpio.h +++ /dev/null @@ -1,683 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_gpio.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_GPIO_H__ -#define __MCF523X_GPIO_H__ - -/********************************************************************* -* -* General Purpose I/O (GPIO) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_GPIO_PODR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100000])) -#define MCF_GPIO_PODR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100001])) -#define MCF_GPIO_PODR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100002])) -#define MCF_GPIO_PODR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100003])) -#define MCF_GPIO_PODR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100004])) -#define MCF_GPIO_PODR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100005])) -#define MCF_GPIO_PODR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100006])) -#define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100007])) -#define MCF_GPIO_PODR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100008])) -#define MCF_GPIO_PODR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100009])) -#define MCF_GPIO_PODR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10000A])) -#define MCF_GPIO_PODR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10000B])) -#define MCF_GPIO_PODR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10000C])) -#define MCF_GPIO_PDDR_APDDR (*(vuint8 *)(void*)(&__IPSBAR[0x100010])) -#define MCF_GPIO_PDDR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100011])) -#define MCF_GPIO_PDDR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100012])) -#define MCF_GPIO_PDDR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100013])) -#define MCF_GPIO_PDDR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100014])) -#define MCF_GPIO_PDDR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100015])) -#define MCF_GPIO_PDDR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100016])) -#define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100017])) -#define MCF_GPIO_PDDR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100018])) -#define MCF_GPIO_PDDR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100019])) -#define MCF_GPIO_PDDR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10001A])) -#define MCF_GPIO_PDDR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10001B])) -#define MCF_GPIO_PDDR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10001C])) -#define MCF_GPIO_PPDSDR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100020])) -#define MCF_GPIO_PPDSDR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100021])) -#define MCF_GPIO_PPDSDR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100022])) -#define MCF_GPIO_PPDSDR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100023])) -#define MCF_GPIO_PPDSDR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100024])) -#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100027])) -#define MCF_GPIO_PPDSDR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100025])) -#define MCF_GPIO_PPDSDR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100026])) -#define MCF_GPIO_PPDSDR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100028])) -#define MCF_GPIO_PPDSDR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100029])) -#define MCF_GPIO_PPDSDR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10002A])) -#define MCF_GPIO_PPDSDR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10002B])) -#define MCF_GPIO_PPDSDR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10002C])) -#define MCF_GPIO_PCLRR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100030])) -#define MCF_GPIO_PCLRR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100031])) -#define MCF_GPIO_PCLRR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100032])) -#define MCF_GPIO_PCLRR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100033])) -#define MCF_GPIO_PCLRR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100034])) -#define MCF_GPIO_PCLRR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100035])) -#define MCF_GPIO_PCLRR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100036])) -#define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100037])) -#define MCF_GPIO_PCLRR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100038])) -#define MCF_GPIO_PCLRR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100039])) -#define MCF_GPIO_PCLRR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10003A])) -#define MCF_GPIO_PCLRR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10003B])) -#define MCF_GPIO_PCLRR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10003C])) -#define MCF_GPIO_PAR_AD (*(vuint8 *)(void*)(&__IPSBAR[0x100040])) -#define MCF_GPIO_PAR_BUSCTL (*(vuint16*)(void*)(&__IPSBAR[0x100042])) -#define MCF_GPIO_PAR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100044])) -#define MCF_GPIO_PAR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100045])) -#define MCF_GPIO_PAR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100046])) -#define MCF_GPIO_PAR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100047])) -#define MCF_GPIO_PAR_UART (*(vuint16*)(void*)(&__IPSBAR[0x100048])) -#define MCF_GPIO_PAR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10004A])) -#define MCF_GPIO_PAR_TIMER (*(vuint16*)(void*)(&__IPSBAR[0x10004C])) -#define MCF_GPIO_PAR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10004E])) -#define MCF_GPIO_DSCR_EIM (*(vuint8 *)(void*)(&__IPSBAR[0x100050])) -#define MCF_GPIO_DSCR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x100051])) -#define MCF_GPIO_DSCR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100052])) -#define MCF_GPIO_DSCR_UART (*(vuint8 *)(void*)(&__IPSBAR[0x100053])) -#define MCF_GPIO_DSCR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x100054])) -#define MCF_GPIO_DSCR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x100055])) - -/* Bit definitions and macros for MCF_GPIO_PODR_ADDR */ -#define MCF_GPIO_PODR_ADDR_PODR_ADDR5 (0x20) -#define MCF_GPIO_PODR_ADDR_PODR_ADDR6 (0x40) -#define MCF_GPIO_PODR_ADDR_PODR_ADDR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_DATAH */ -#define MCF_GPIO_PODR_DATAH_PODR_DATAH0 (0x01) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH1 (0x02) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH2 (0x04) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH3 (0x08) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH4 (0x10) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH5 (0x20) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH6 (0x40) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_DATAL */ -#define MCF_GPIO_PODR_DATAL_PODR_DATAL0 (0x01) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL1 (0x02) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL2 (0x04) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL3 (0x08) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL4 (0x10) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL5 (0x20) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL6 (0x40) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */ -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL0 (0x01) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL4 (0x10) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL5 (0x20) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL6 (0x40) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_BS */ -#define MCF_GPIO_PODR_BS_PODR_BS0 (0x01) -#define MCF_GPIO_PODR_BS_PODR_BS1 (0x02) -#define MCF_GPIO_PODR_BS_PODR_BS2 (0x04) -#define MCF_GPIO_PODR_BS_PODR_BS3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_CS */ -#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02) -#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04) -#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08) -#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10) -#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20) -#define MCF_GPIO_PODR_CS_PODR_CS6 (0x40) -#define MCF_GPIO_PODR_CS_PODR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_SDRAM */ -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM0 (0x01) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM1 (0x02) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM2 (0x04) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM3 (0x08) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM4 (0x10) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_UARTH */ -#define MCF_GPIO_PODR_UARTH_PODR_UARTH0 (0x01) -#define MCF_GPIO_PODR_UARTH_PODR_UARTH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PODR_UARTL */ -#define MCF_GPIO_PODR_UARTL_PODR_UARTL0 (0x01) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL1 (0x02) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL2 (0x04) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL3 (0x08) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL4 (0x10) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL5 (0x20) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL6 (0x40) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */ -#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */ -#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER4 (0x10) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER5 (0x20) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER6 (0x40) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_ETPU */ -#define MCF_GPIO_PODR_ETPU_PODR_ETPU0 (0x01) -#define MCF_GPIO_PODR_ETPU_PODR_ETPU1 (0x02) -#define MCF_GPIO_PODR_ETPU_PODR_ETPU2 (0x04) - -/* Bit definitions and macros for MCF_GPIO_PDDR_APDDR */ -#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR5 (0x20) -#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR6 (0x40) -#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_DATAH */ -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH0 (0x01) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH1 (0x02) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH2 (0x04) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH3 (0x08) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH4 (0x10) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH5 (0x20) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH6 (0x40) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_DATAL */ -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL0 (0x01) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL1 (0x02) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL2 (0x04) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL3 (0x08) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL4 (0x10) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL5 (0x20) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL6 (0x40) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */ -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0 (0x01) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL4 (0x10) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL5 (0x20) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL6 (0x40) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_BS */ -#define MCF_GPIO_PDDR_BS_PDDR_BS0 (0x01) -#define MCF_GPIO_PDDR_BS_PDDR_BS3(x) (((x)&0x07)<<1) - -/* Bit definitions and macros for MCF_GPIO_PDDR_CS */ -#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02) -#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04) -#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08) -#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10) -#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20) -#define MCF_GPIO_PDDR_CS_PDDR_CS6 (0x40) -#define MCF_GPIO_PDDR_CS_PDDR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_SDRAM */ -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM0 (0x01) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM1 (0x02) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM2 (0x04) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM3 (0x08) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM4 (0x10) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_UARTH */ -#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH0 (0x01) -#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PDDR_UARTL */ -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL0 (0x01) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL1 (0x02) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL2 (0x04) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL3 (0x08) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL4 (0x10) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL5 (0x20) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL6 (0x40) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */ -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */ -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER4 (0x10) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER5 (0x20) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER6 (0x40) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_ETPU */ -#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU0 (0x01) -#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU1 (0x02) -#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU2 (0x04) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_ADDR */ -#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR5 (0x20) -#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR6 (0x40) -#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAH */ -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH0 (0x01) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH1 (0x02) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH2 (0x04) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH3 (0x08) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH4 (0x10) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH5 (0x20) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH6 (0x40) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAL */ -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL0 (0x01) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL1 (0x02) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL2 (0x04) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL3 (0x08) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL4 (0x10) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL5 (0x20) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL6 (0x40) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */ -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL0 (0x01) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL4 (0x10) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL5 (0x20) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL6 (0x40) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_BS */ -#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS0 (0x01) -#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS1 (0x02) -#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS2 (0x04) -#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */ -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS6 (0x40) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_SDRAM */ -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM0 (0x01) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM1 (0x02) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM2 (0x04) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM3 (0x08) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM4 (0x10) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM5 (0x20) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM6 (0x40) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTH */ -#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH0 (0x01) -#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTL */ -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL0 (0x01) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL1 (0x02) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL2 (0x04) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL3 (0x08) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL4 (0x10) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL5 (0x20) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL6 (0x40) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */ -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */ -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER4 (0x10) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER5 (0x20) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER6 (0x40) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_ETPU */ -#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU0 (0x01) -#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU1 (0x02) -#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU2 (0x04) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_ADDR */ -#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR5 (0x20) -#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR6 (0x40) -#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAH */ -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH0 (0x01) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH1 (0x02) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH2 (0x04) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH3 (0x08) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH4 (0x10) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH5 (0x20) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH6 (0x40) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAL */ -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL0 (0x01) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL1 (0x02) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL2 (0x04) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL3 (0x08) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL4 (0x10) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL5 (0x20) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL6 (0x40) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */ -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL0 (0x01) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL4 (0x10) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL5 (0x20) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL6 (0x40) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_BS */ -#define MCF_GPIO_PCLRR_BS_PCLRR_BS0 (0x01) -#define MCF_GPIO_PCLRR_BS_PCLRR_BS1 (0x02) -#define MCF_GPIO_PCLRR_BS_PCLRR_BS2 (0x04) -#define MCF_GPIO_PCLRR_BS_PCLRR_BS3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */ -#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS6 (0x40) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_SDRAM */ -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM0 (0x01) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM1 (0x02) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM2 (0x04) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM3 (0x08) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM4 (0x10) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTH */ -#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH0 (0x01) -#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTL */ -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL0 (0x01) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL1 (0x02) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL2 (0x04) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL3 (0x08) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL4 (0x10) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL5 (0x20) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL6 (0x40) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */ -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */ -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER4 (0x10) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER5 (0x20) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER6 (0x40) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_ETPU */ -#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU0 (0x01) -#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU1 (0x02) -#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU2 (0x04) - -/* Bit definitions and macros for MCF_GPIO_PAR_AD */ -#define MCF_GPIO_PAR_AD_PAR_DATAL (0x01) -#define MCF_GPIO_PAR_AD_PAR_ADDR21 (0x20) -#define MCF_GPIO_PAR_AD_PAR_ADDR22 (0x40) -#define MCF_GPIO_PAR_AD_PAR_ADDR23 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */ -#define MCF_GPIO_PAR_BUSCTL_PAR_TIP(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 (0x0010) -#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 (0x0040) -#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x0100) -#define MCF_GPIO_PAR_BUSCTL_PAR_TEA(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x1000) -#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x4000) -#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_GPIO (0x0000) -#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_DMA (0x0800) -#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_TEA (0x0C00) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x0000) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DMA (0x0080) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x00C0) -#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_GPIO (0x0000) -#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_DMA (0x0002) -#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_TEA (0x0003) - -/* Bit definitions and macros for MCF_GPIO_PAR_BS */ -#define MCF_GPIO_PAR_BS_PAR_BS0 (0x01) -#define MCF_GPIO_PAR_BS_PAR_BS1 (0x02) -#define MCF_GPIO_PAR_BS_PAR_BS2 (0x04) -#define MCF_GPIO_PAR_BS_PAR_BS3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PAR_CS */ -#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02) -#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04) -#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08) -#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10) -#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20) -#define MCF_GPIO_PAR_CS_PAR_CS6 (0x40) -#define MCF_GPIO_PAR_CS_PAR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PAR_SDRAM */ -#define MCF_GPIO_PAR_SDRAM_PAR_SDCS0 (0x01) -#define MCF_GPIO_PAR_SDRAM_PAR_SDCS1 (0x02) -#define MCF_GPIO_PAR_SDRAM_PAR_SCKE (0x04) -#define MCF_GPIO_PAR_SDRAM_PAR_SRAS (0x08) -#define MCF_GPIO_PAR_SDRAM_PAR_SCAS (0x10) -#define MCF_GPIO_PAR_SDRAM_PAR_SDWE (0x20) -#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) - -/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */ -#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_UART2 (0x40) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_I2C (0x80) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC (0xC0) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_UART2 (0x10) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_I2C (0x20) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC (0x30) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_FLEX (0x08) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_I2C (0x0C) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_FLEX (0x02) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_I2C (0x03) - -/* Bit definitions and macros for MCF_GPIO_PAR_UART */ -#define MCF_GPIO_PAR_UART_PAR_U0RTS (0x0001) -#define MCF_GPIO_PAR_UART_PAR_U0CTS (0x0002) -#define MCF_GPIO_PAR_UART_PAR_U0TXD (0x0004) -#define MCF_GPIO_PAR_UART_PAR_U0RXD (0x0008) -#define MCF_GPIO_PAR_UART_PAR_U1RTS(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_UART_PAR_U1CTS(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_UART_PAR_U1TXD(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_UART_PAR_U1RXD(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_UART_PAR_U2TXD (0x1000) -#define MCF_GPIO_PAR_UART_PAR_U2RXD (0x2000) -#define MCF_GPIO_PAR_UART_PAR_CAN1EN (0x4000) -#define MCF_GPIO_PAR_UART_PAR_DREQ2 (0x8000) -#define MCF_GPIO_PAR_UART_PAR_U1RXD_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_U1RXD_FLEX (0x0800) -#define MCF_GPIO_PAR_UART_PAR_U1RXD_UART1 (0x0C00) -#define MCF_GPIO_PAR_UART_PAR_U1TXD_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_U1TXD_FLEX (0x0200) -#define MCF_GPIO_PAR_UART_PAR_U1TXD_UART1 (0x0300) -#define MCF_GPIO_PAR_UART_PAR_U1CTS_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART2 (0x0080) -#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART1 (0x00C0) -#define MCF_GPIO_PAR_UART_PAR_U1RTS_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART2 (0x0020) -#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART1 (0x0030) - -/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */ -#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_QSPI_PAR_DOUT (0x04) -#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x03)<<3) -#define MCF_GPIO_PAR_QSPI_PAR_PCS0 (0x20) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1_GPIO (0x00) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1_SDRAMC (0x80) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1_QSPI (0xC0) -#define MCF_GPIO_PAR_QSPI_PAR_DIN_GPIO (0x00) -#define MCF_GPIO_PAR_QSPI_PAR_DIN_I2C (0x10) -#define MCF_GPIO_PAR_QSPI_PAR_DIN_QSPI (0x1C) -#define MCF_GPIO_PAR_QSPI_PAR_SCK_GPIO (0x00) -#define MCF_GPIO_PAR_QSPI_PAR_SCK_I2C (0x02) -#define MCF_GPIO_PAR_QSPI_PAR_SCK_QSPI (0x03) - -/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ -#define MCF_GPIO_PAR_TIMER_PAR_T0OUT(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_TIMER_PAR_T1OUT(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PAR_TIMER_PAR_T2OUT(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_TIMER_PAR_T0IN(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN(x) (((x)&0x0003)<<12) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN(x) (((x)&0x0003)<<14) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN_QSPI (0x4000) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN_UART2 (0x8000) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN_T3IN (0xC000) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2OUT (0x1000) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN_DMA (0x2000) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2IN (0x3000) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1OUT (0x0400) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN_DMA (0x0800) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1IN (0x0C00) -#define MCF_GPIO_PAR_TIMER_PAR_T0IN_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T0IN_DMA (0x0200) -#define MCF_GPIO_PAR_TIMER_PAR_T0IN_T0IN (0x0300) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_QSPI (0x0040) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_UART2 (0x0080) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_T3OUT (0x00C0) -#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_DMA (0x0020) -#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_T2OUT (0x0030) -#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_DMA (0x0008) -#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_T1OUT (0x000C) -#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_DMA (0x0002) -#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_T0OUT (0x0003) - -/* Bit definitions and macros for MCF_GPIO_PAR_ETPU */ -#define MCF_GPIO_PAR_ETPU_PAR_LTPU_ODIS (0x01) -#define MCF_GPIO_PAR_ETPU_PAR_UTPU_ODIS (0x02) -#define MCF_GPIO_PAR_ETPU_PAR_TCRCLK (0x04) - -/* Bit definitions and macros for MCF_GPIO_DSCR_EIM */ -#define MCF_GPIO_DSCR_EIM_DSCR_EIM0 (0x01) -#define MCF_GPIO_DSCR_EIM_DSCR_EIM1 (0x10) - -/* Bit definitions and macros for MCF_GPIO_DSCR_ETPU */ -#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_7_0 (0x01) -#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_15_8 (0x04) -#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_23_16 (0x10) -#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_31_24 (0x40) - -/* Bit definitions and macros for MCF_GPIO_DSCR_FECI2C */ -#define MCF_GPIO_DSCR_FECI2C_DSCR_I2C (0x01) -#define MCF_GPIO_DSCR_FECI2C_DSCR_FEC (0x10) - -/* Bit definitions and macros for MCF_GPIO_DSCR_UART */ -#define MCF_GPIO_DSCR_UART_DSCR_UART0 (0x01) -#define MCF_GPIO_DSCR_UART_DSCR_UART1 (0x04) -#define MCF_GPIO_DSCR_UART_DSCR_UART2 (0x10) -#define MCF_GPIO_DSCR_UART_DSCR_IRQ (0x40) - -/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */ -#define MCF_GPIO_DSCR_QSPI_DSCR_QSPI (0x01) - -/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */ -#define MCF_GPIO_DSCR_TIMER_DSCR_TIMER (0x01) - -/********************************************************************/ - -#endif /* __MCF523X_GPIO_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_i2c.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_i2c.h deleted file mode 100644 index 6708b6b94..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_i2c.h +++ /dev/null @@ -1,70 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_i2c.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_I2C_H__ -#define __MCF523X_I2C_H__ - -/********************************************************************* -* -* I2C Module (I2C) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_I2C_I2AR (*(vuint8 *)(void*)(&__IPSBAR[0x000300])) -#define MCF_I2C_I2FDR (*(vuint8 *)(void*)(&__IPSBAR[0x000304])) -#define MCF_I2C_I2CR (*(vuint8 *)(void*)(&__IPSBAR[0x000308])) -#define MCF_I2C_I2SR (*(vuint8 *)(void*)(&__IPSBAR[0x00030C])) -#define MCF_I2C_I2DR (*(vuint8 *)(void*)(&__IPSBAR[0x000310])) -#define MCF_I2C_I2ICR (*(vuint8 *)(void*)(&__IPSBAR[0x000320])) - -/* Bit definitions and macros for MCF_I2C_I2AR */ -#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_I2C_I2FDR */ -#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) - -/* Bit definitions and macros for MCF_I2C_I2CR */ -#define MCF_I2C_I2CR_RSTA (0x04) -#define MCF_I2C_I2CR_TXAK (0x08) -#define MCF_I2C_I2CR_MTX (0x10) -#define MCF_I2C_I2CR_MSTA (0x20) -#define MCF_I2C_I2CR_IIEN (0x40) -#define MCF_I2C_I2CR_IEN (0x80) - -/* Bit definitions and macros for MCF_I2C_I2SR */ -#define MCF_I2C_I2SR_RXAK (0x01) -#define MCF_I2C_I2SR_IIF (0x02) -#define MCF_I2C_I2SR_SRW (0x04) -#define MCF_I2C_I2SR_IAL (0x10) -#define MCF_I2C_I2SR_IBB (0x20) -#define MCF_I2C_I2SR_IAAS (0x40) -#define MCF_I2C_I2SR_ICF (0x80) - -/* Bit definitions and macros for MCF_I2C_I2ICR */ -#define MCF_I2C_I2ICR_IE (0x01) -#define MCF_I2C_I2ICR_RE (0x02) -#define MCF_I2C_I2ICR_TE (0x04) -#define MCF_I2C_I2ICR_BNBE (0x08) - -/********************************************************************/ - -#endif /* __MCF523X_I2C_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_intc0.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_intc0.h deleted file mode 100644 index 989825479..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_intc0.h +++ /dev/null @@ -1,330 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_intc0.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_INTC0_H__ -#define __MCF523X_INTC0_H__ - -/********************************************************************* -* -* Interrupt Controller 0 (INTC0) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_INTC0_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000C00])) -#define MCF_INTC0_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000C04])) -#define MCF_INTC0_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000C08])) -#define MCF_INTC0_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000C0C])) -#define MCF_INTC0_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000C10])) -#define MCF_INTC0_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000C14])) -#define MCF_INTC0_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000C18])) -#define MCF_INTC0_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000C19])) -#define MCF_INTC0_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000C40])) -#define MCF_INTC0_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000C41])) -#define MCF_INTC0_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000C42])) -#define MCF_INTC0_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000C43])) -#define MCF_INTC0_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000C44])) -#define MCF_INTC0_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000C45])) -#define MCF_INTC0_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000C46])) -#define MCF_INTC0_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000C47])) -#define MCF_INTC0_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000C48])) -#define MCF_INTC0_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000C49])) -#define MCF_INTC0_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4A])) -#define MCF_INTC0_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4B])) -#define MCF_INTC0_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4C])) -#define MCF_INTC0_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4D])) -#define MCF_INTC0_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4E])) -#define MCF_INTC0_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4F])) -#define MCF_INTC0_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000C50])) -#define MCF_INTC0_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000C51])) -#define MCF_INTC0_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000C52])) -#define MCF_INTC0_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000C53])) -#define MCF_INTC0_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000C54])) -#define MCF_INTC0_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000C55])) -#define MCF_INTC0_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000C56])) -#define MCF_INTC0_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000C57])) -#define MCF_INTC0_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000C58])) -#define MCF_INTC0_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000C59])) -#define MCF_INTC0_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5A])) -#define MCF_INTC0_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5B])) -#define MCF_INTC0_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5C])) -#define MCF_INTC0_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5D])) -#define MCF_INTC0_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5E])) -#define MCF_INTC0_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5F])) -#define MCF_INTC0_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000C60])) -#define MCF_INTC0_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000C61])) -#define MCF_INTC0_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000C62])) -#define MCF_INTC0_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000C63])) -#define MCF_INTC0_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000C64])) -#define MCF_INTC0_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000C65])) -#define MCF_INTC0_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000C66])) -#define MCF_INTC0_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000C67])) -#define MCF_INTC0_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000C68])) -#define MCF_INTC0_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000C69])) -#define MCF_INTC0_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6A])) -#define MCF_INTC0_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6B])) -#define MCF_INTC0_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6C])) -#define MCF_INTC0_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6D])) -#define MCF_INTC0_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6E])) -#define MCF_INTC0_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6F])) -#define MCF_INTC0_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000C70])) -#define MCF_INTC0_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000C71])) -#define MCF_INTC0_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000C72])) -#define MCF_INTC0_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000C73])) -#define MCF_INTC0_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000C74])) -#define MCF_INTC0_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000C75])) -#define MCF_INTC0_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000C76])) -#define MCF_INTC0_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000C77])) -#define MCF_INTC0_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000C78])) -#define MCF_INTC0_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000C79])) -#define MCF_INTC0_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7A])) -#define MCF_INTC0_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7B])) -#define MCF_INTC0_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7C])) -#define MCF_INTC0_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7D])) -#define MCF_INTC0_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7E])) -#define MCF_INTC0_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7F])) -#define MCF_INTC0_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000C40+((x)*0x001)])) -#define MCF_INTC0_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE0])) -#define MCF_INTC0_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4])) -#define MCF_INTC0_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE8])) -#define MCF_INTC0_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CEC])) -#define MCF_INTC0_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF0])) -#define MCF_INTC0_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF4])) -#define MCF_INTC0_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF8])) -#define MCF_INTC0_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CFC])) -#define MCF_INTC0_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4+((x)*0x004)])) - -/* Bit definitions and macros for MCF_INTC0_IPRH */ -#define MCF_INTC0_IPRH_INT32 (0x00000001) -#define MCF_INTC0_IPRH_INT33 (0x00000002) -#define MCF_INTC0_IPRH_INT34 (0x00000004) -#define MCF_INTC0_IPRH_INT35 (0x00000008) -#define MCF_INTC0_IPRH_INT36 (0x00000010) -#define MCF_INTC0_IPRH_INT37 (0x00000020) -#define MCF_INTC0_IPRH_INT38 (0x00000040) -#define MCF_INTC0_IPRH_INT39 (0x00000080) -#define MCF_INTC0_IPRH_INT40 (0x00000100) -#define MCF_INTC0_IPRH_INT41 (0x00000200) -#define MCF_INTC0_IPRH_INT42 (0x00000400) -#define MCF_INTC0_IPRH_INT43 (0x00000800) -#define MCF_INTC0_IPRH_INT44 (0x00001000) -#define MCF_INTC0_IPRH_INT45 (0x00002000) -#define MCF_INTC0_IPRH_INT46 (0x00004000) -#define MCF_INTC0_IPRH_INT47 (0x00008000) -#define MCF_INTC0_IPRH_INT48 (0x00010000) -#define MCF_INTC0_IPRH_INT49 (0x00020000) -#define MCF_INTC0_IPRH_INT50 (0x00040000) -#define MCF_INTC0_IPRH_INT51 (0x00080000) -#define MCF_INTC0_IPRH_INT52 (0x00100000) -#define MCF_INTC0_IPRH_INT53 (0x00200000) -#define MCF_INTC0_IPRH_INT54 (0x00400000) -#define MCF_INTC0_IPRH_INT55 (0x00800000) -#define MCF_INTC0_IPRH_INT56 (0x01000000) -#define MCF_INTC0_IPRH_INT57 (0x02000000) -#define MCF_INTC0_IPRH_INT58 (0x04000000) -#define MCF_INTC0_IPRH_INT59 (0x08000000) -#define MCF_INTC0_IPRH_INT60 (0x10000000) -#define MCF_INTC0_IPRH_INT61 (0x20000000) -#define MCF_INTC0_IPRH_INT62 (0x40000000) -#define MCF_INTC0_IPRH_INT63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_IPRL */ -#define MCF_INTC0_IPRL_INT1 (0x00000002) -#define MCF_INTC0_IPRL_INT2 (0x00000004) -#define MCF_INTC0_IPRL_INT3 (0x00000008) -#define MCF_INTC0_IPRL_INT4 (0x00000010) -#define MCF_INTC0_IPRL_INT5 (0x00000020) -#define MCF_INTC0_IPRL_INT6 (0x00000040) -#define MCF_INTC0_IPRL_INT7 (0x00000080) -#define MCF_INTC0_IPRL_INT8 (0x00000100) -#define MCF_INTC0_IPRL_INT9 (0x00000200) -#define MCF_INTC0_IPRL_INT10 (0x00000400) -#define MCF_INTC0_IPRL_INT11 (0x00000800) -#define MCF_INTC0_IPRL_INT12 (0x00001000) -#define MCF_INTC0_IPRL_INT13 (0x00002000) -#define MCF_INTC0_IPRL_INT14 (0x00004000) -#define MCF_INTC0_IPRL_INT15 (0x00008000) -#define MCF_INTC0_IPRL_INT16 (0x00010000) -#define MCF_INTC0_IPRL_INT17 (0x00020000) -#define MCF_INTC0_IPRL_INT18 (0x00040000) -#define MCF_INTC0_IPRL_INT19 (0x00080000) -#define MCF_INTC0_IPRL_INT20 (0x00100000) -#define MCF_INTC0_IPRL_INT21 (0x00200000) -#define MCF_INTC0_IPRL_INT22 (0x00400000) -#define MCF_INTC0_IPRL_INT23 (0x00800000) -#define MCF_INTC0_IPRL_INT24 (0x01000000) -#define MCF_INTC0_IPRL_INT25 (0x02000000) -#define MCF_INTC0_IPRL_INT26 (0x04000000) -#define MCF_INTC0_IPRL_INT27 (0x08000000) -#define MCF_INTC0_IPRL_INT28 (0x10000000) -#define MCF_INTC0_IPRL_INT29 (0x20000000) -#define MCF_INTC0_IPRL_INT30 (0x40000000) -#define MCF_INTC0_IPRL_INT31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_IMRH */ -#define MCF_INTC0_IMRH_INT_MASK32 (0x00000001) -#define MCF_INTC0_IMRH_INT_MASK33 (0x00000002) -#define MCF_INTC0_IMRH_INT_MASK34 (0x00000004) -#define MCF_INTC0_IMRH_INT_MASK35 (0x00000008) -#define MCF_INTC0_IMRH_INT_MASK36 (0x00000010) -#define MCF_INTC0_IMRH_INT_MASK37 (0x00000020) -#define MCF_INTC0_IMRH_INT_MASK38 (0x00000040) -#define MCF_INTC0_IMRH_INT_MASK39 (0x00000080) -#define MCF_INTC0_IMRH_INT_MASK40 (0x00000100) -#define MCF_INTC0_IMRH_INT_MASK41 (0x00000200) -#define MCF_INTC0_IMRH_INT_MASK42 (0x00000400) -#define MCF_INTC0_IMRH_INT_MASK43 (0x00000800) -#define MCF_INTC0_IMRH_INT_MASK44 (0x00001000) -#define MCF_INTC0_IMRH_INT_MASK45 (0x00002000) -#define MCF_INTC0_IMRH_INT_MASK46 (0x00004000) -#define MCF_INTC0_IMRH_INT_MASK47 (0x00008000) -#define MCF_INTC0_IMRH_INT_MASK48 (0x00010000) -#define MCF_INTC0_IMRH_INT_MASK49 (0x00020000) -#define MCF_INTC0_IMRH_INT_MASK50 (0x00040000) -#define MCF_INTC0_IMRH_INT_MASK51 (0x00080000) -#define MCF_INTC0_IMRH_INT_MASK52 (0x00100000) -#define MCF_INTC0_IMRH_INT_MASK53 (0x00200000) -#define MCF_INTC0_IMRH_INT_MASK54 (0x00400000) -#define MCF_INTC0_IMRH_INT_MASK55 (0x00800000) -#define MCF_INTC0_IMRH_INT_MASK56 (0x01000000) -#define MCF_INTC0_IMRH_INT_MASK57 (0x02000000) -#define MCF_INTC0_IMRH_INT_MASK58 (0x04000000) -#define MCF_INTC0_IMRH_INT_MASK59 (0x08000000) -#define MCF_INTC0_IMRH_INT_MASK60 (0x10000000) -#define MCF_INTC0_IMRH_INT_MASK61 (0x20000000) -#define MCF_INTC0_IMRH_INT_MASK62 (0x40000000) -#define MCF_INTC0_IMRH_INT_MASK63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_IMRL */ -#define MCF_INTC0_IMRL_MASKALL (0x00000001) -#define MCF_INTC0_IMRL_INT_MASK1 (0x00000002) -#define MCF_INTC0_IMRL_INT_MASK2 (0x00000004) -#define MCF_INTC0_IMRL_INT_MASK3 (0x00000008) -#define MCF_INTC0_IMRL_INT_MASK4 (0x00000010) -#define MCF_INTC0_IMRL_INT_MASK5 (0x00000020) -#define MCF_INTC0_IMRL_INT_MASK6 (0x00000040) -#define MCF_INTC0_IMRL_INT_MASK7 (0x00000080) -#define MCF_INTC0_IMRL_INT_MASK8 (0x00000100) -#define MCF_INTC0_IMRL_INT_MASK9 (0x00000200) -#define MCF_INTC0_IMRL_INT_MASK10 (0x00000400) -#define MCF_INTC0_IMRL_INT_MASK11 (0x00000800) -#define MCF_INTC0_IMRL_INT_MASK12 (0x00001000) -#define MCF_INTC0_IMRL_INT_MASK13 (0x00002000) -#define MCF_INTC0_IMRL_INT_MASK14 (0x00004000) -#define MCF_INTC0_IMRL_INT_MASK15 (0x00008000) -#define MCF_INTC0_IMRL_INT_MASK16 (0x00010000) -#define MCF_INTC0_IMRL_INT_MASK17 (0x00020000) -#define MCF_INTC0_IMRL_INT_MASK18 (0x00040000) -#define MCF_INTC0_IMRL_INT_MASK19 (0x00080000) -#define MCF_INTC0_IMRL_INT_MASK20 (0x00100000) -#define MCF_INTC0_IMRL_INT_MASK21 (0x00200000) -#define MCF_INTC0_IMRL_INT_MASK22 (0x00400000) -#define MCF_INTC0_IMRL_INT_MASK23 (0x00800000) -#define MCF_INTC0_IMRL_INT_MASK24 (0x01000000) -#define MCF_INTC0_IMRL_INT_MASK25 (0x02000000) -#define MCF_INTC0_IMRL_INT_MASK26 (0x04000000) -#define MCF_INTC0_IMRL_INT_MASK27 (0x08000000) -#define MCF_INTC0_IMRL_INT_MASK28 (0x10000000) -#define MCF_INTC0_IMRL_INT_MASK29 (0x20000000) -#define MCF_INTC0_IMRL_INT_MASK30 (0x40000000) -#define MCF_INTC0_IMRL_INT_MASK31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_INTFRCH */ -#define MCF_INTC0_INTFRCH_INTFRC32 (0x00000001) -#define MCF_INTC0_INTFRCH_INTFRC33 (0x00000002) -#define MCF_INTC0_INTFRCH_INTFRC34 (0x00000004) -#define MCF_INTC0_INTFRCH_INTFRC35 (0x00000008) -#define MCF_INTC0_INTFRCH_INTFRC36 (0x00000010) -#define MCF_INTC0_INTFRCH_INTFRC37 (0x00000020) -#define MCF_INTC0_INTFRCH_INTFRC38 (0x00000040) -#define MCF_INTC0_INTFRCH_INTFRC39 (0x00000080) -#define MCF_INTC0_INTFRCH_INTFRC40 (0x00000100) -#define MCF_INTC0_INTFRCH_INTFRC41 (0x00000200) -#define MCF_INTC0_INTFRCH_INTFRC42 (0x00000400) -#define MCF_INTC0_INTFRCH_INTFRC43 (0x00000800) -#define MCF_INTC0_INTFRCH_INTFRC44 (0x00001000) -#define MCF_INTC0_INTFRCH_INTFRC45 (0x00002000) -#define MCF_INTC0_INTFRCH_INTFRC46 (0x00004000) -#define MCF_INTC0_INTFRCH_INTFRC47 (0x00008000) -#define MCF_INTC0_INTFRCH_INTFRC48 (0x00010000) -#define MCF_INTC0_INTFRCH_INTFRC49 (0x00020000) -#define MCF_INTC0_INTFRCH_INTFRC50 (0x00040000) -#define MCF_INTC0_INTFRCH_INTFRC51 (0x00080000) -#define MCF_INTC0_INTFRCH_INTFRC52 (0x00100000) -#define MCF_INTC0_INTFRCH_INTFRC53 (0x00200000) -#define MCF_INTC0_INTFRCH_INTFRC54 (0x00400000) -#define MCF_INTC0_INTFRCH_INTFRC55 (0x00800000) -#define MCF_INTC0_INTFRCH_INTFRC56 (0x01000000) -#define MCF_INTC0_INTFRCH_INTFRC57 (0x02000000) -#define MCF_INTC0_INTFRCH_INTFRC58 (0x04000000) -#define MCF_INTC0_INTFRCH_INTFRC59 (0x08000000) -#define MCF_INTC0_INTFRCH_INTFRC60 (0x10000000) -#define MCF_INTC0_INTFRCH_INTFRC61 (0x20000000) -#define MCF_INTC0_INTFRCH_INTFRC62 (0x40000000) -#define MCF_INTC0_INTFRCH_INTFRC63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_INTFRCL */ -#define MCF_INTC0_INTFRCL_INTFRC1 (0x00000002) -#define MCF_INTC0_INTFRCL_INTFRC2 (0x00000004) -#define MCF_INTC0_INTFRCL_INTFRC3 (0x00000008) -#define MCF_INTC0_INTFRCL_INTFRC4 (0x00000010) -#define MCF_INTC0_INTFRCL_INTFRC5 (0x00000020) -#define MCF_INTC0_INTFRCL_INT6 (0x00000040) -#define MCF_INTC0_INTFRCL_INT7 (0x00000080) -#define MCF_INTC0_INTFRCL_INT8 (0x00000100) -#define MCF_INTC0_INTFRCL_INT9 (0x00000200) -#define MCF_INTC0_INTFRCL_INT10 (0x00000400) -#define MCF_INTC0_INTFRCL_INTFRC11 (0x00000800) -#define MCF_INTC0_INTFRCL_INTFRC12 (0x00001000) -#define MCF_INTC0_INTFRCL_INTFRC13 (0x00002000) -#define MCF_INTC0_INTFRCL_INTFRC14 (0x00004000) -#define MCF_INTC0_INTFRCL_INT15 (0x00008000) -#define MCF_INTC0_INTFRCL_INTFRC16 (0x00010000) -#define MCF_INTC0_INTFRCL_INTFRC17 (0x00020000) -#define MCF_INTC0_INTFRCL_INTFRC18 (0x00040000) -#define MCF_INTC0_INTFRCL_INTFRC19 (0x00080000) -#define MCF_INTC0_INTFRCL_INTFRC20 (0x00100000) -#define MCF_INTC0_INTFRCL_INTFRC21 (0x00200000) -#define MCF_INTC0_INTFRCL_INTFRC22 (0x00400000) -#define MCF_INTC0_INTFRCL_INTFRC23 (0x00800000) -#define MCF_INTC0_INTFRCL_INTFRC24 (0x01000000) -#define MCF_INTC0_INTFRCL_INTFRC25 (0x02000000) -#define MCF_INTC0_INTFRCL_INTFRC26 (0x04000000) -#define MCF_INTC0_INTFRCL_INTFRC27 (0x08000000) -#define MCF_INTC0_INTFRCL_INTFRC28 (0x10000000) -#define MCF_INTC0_INTFRCL_INTFRC29 (0x20000000) -#define MCF_INTC0_INTFRCL_INTFRC30 (0x40000000) -#define MCF_INTC0_INTFRCL_INTFRC31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_IRLR */ -#define MCF_INTC0_IRLR_IRQ(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_INTC0_IACKLPR */ -#define MCF_INTC0_IACKLPR_PRI(x) (((x)&0x0F)<<0) -#define MCF_INTC0_IACKLPR_LEVEL(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF_INTC0_ICRn */ -#define MCF_INTC0_ICRn_IP(x) (((x)&0x07)<<0) -#define MCF_INTC0_ICRn_IL(x) (((x)&0x07)<<3) - -/********************************************************************/ - -#endif /* __MCF523X_INTC0_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_intc1.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_intc1.h deleted file mode 100644 index f8f766583..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_intc1.h +++ /dev/null @@ -1,330 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_intc1.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_INTC1_H__ -#define __MCF523X_INTC1_H__ - -/********************************************************************* -* -* Interrupt Controller 1 (INTC1) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_INTC1_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000D00])) -#define MCF_INTC1_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000D04])) -#define MCF_INTC1_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000D08])) -#define MCF_INTC1_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000D0C])) -#define MCF_INTC1_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000D10])) -#define MCF_INTC1_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000D14])) -#define MCF_INTC1_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000D18])) -#define MCF_INTC1_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000D19])) -#define MCF_INTC1_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000D40])) -#define MCF_INTC1_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000D41])) -#define MCF_INTC1_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000D42])) -#define MCF_INTC1_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000D43])) -#define MCF_INTC1_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000D44])) -#define MCF_INTC1_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000D45])) -#define MCF_INTC1_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000D46])) -#define MCF_INTC1_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000D47])) -#define MCF_INTC1_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000D48])) -#define MCF_INTC1_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000D49])) -#define MCF_INTC1_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4A])) -#define MCF_INTC1_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4B])) -#define MCF_INTC1_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4C])) -#define MCF_INTC1_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4D])) -#define MCF_INTC1_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4E])) -#define MCF_INTC1_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4F])) -#define MCF_INTC1_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000D50])) -#define MCF_INTC1_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000D51])) -#define MCF_INTC1_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000D52])) -#define MCF_INTC1_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000D53])) -#define MCF_INTC1_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000D54])) -#define MCF_INTC1_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000D55])) -#define MCF_INTC1_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000D56])) -#define MCF_INTC1_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000D57])) -#define MCF_INTC1_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000D58])) -#define MCF_INTC1_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000D59])) -#define MCF_INTC1_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5A])) -#define MCF_INTC1_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5B])) -#define MCF_INTC1_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5C])) -#define MCF_INTC1_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5D])) -#define MCF_INTC1_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5E])) -#define MCF_INTC1_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5F])) -#define MCF_INTC1_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000D60])) -#define MCF_INTC1_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000D61])) -#define MCF_INTC1_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000D62])) -#define MCF_INTC1_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000D63])) -#define MCF_INTC1_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000D64])) -#define MCF_INTC1_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000D65])) -#define MCF_INTC1_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000D66])) -#define MCF_INTC1_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000D67])) -#define MCF_INTC1_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000D68])) -#define MCF_INTC1_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000D69])) -#define MCF_INTC1_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6A])) -#define MCF_INTC1_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6B])) -#define MCF_INTC1_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6C])) -#define MCF_INTC1_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6D])) -#define MCF_INTC1_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6E])) -#define MCF_INTC1_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6F])) -#define MCF_INTC1_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000D70])) -#define MCF_INTC1_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000D71])) -#define MCF_INTC1_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000D72])) -#define MCF_INTC1_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000D73])) -#define MCF_INTC1_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000D74])) -#define MCF_INTC1_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000D75])) -#define MCF_INTC1_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000D76])) -#define MCF_INTC1_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000D77])) -#define MCF_INTC1_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000D78])) -#define MCF_INTC1_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000D79])) -#define MCF_INTC1_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7A])) -#define MCF_INTC1_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7B])) -#define MCF_INTC1_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7C])) -#define MCF_INTC1_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7D])) -#define MCF_INTC1_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7E])) -#define MCF_INTC1_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7F])) -#define MCF_INTC1_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000D40+((x)*0x001)])) -#define MCF_INTC1_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE0])) -#define MCF_INTC1_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4])) -#define MCF_INTC1_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE8])) -#define MCF_INTC1_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DEC])) -#define MCF_INTC1_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF0])) -#define MCF_INTC1_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF4])) -#define MCF_INTC1_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF8])) -#define MCF_INTC1_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DFC])) -#define MCF_INTC1_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4+((x)*0x004)])) - -/* Bit definitions and macros for MCF_INTC1_IPRH */ -#define MCF_INTC1_IPRH_INT32 (0x00000001) -#define MCF_INTC1_IPRH_INT33 (0x00000002) -#define MCF_INTC1_IPRH_INT34 (0x00000004) -#define MCF_INTC1_IPRH_INT35 (0x00000008) -#define MCF_INTC1_IPRH_INT36 (0x00000010) -#define MCF_INTC1_IPRH_INT37 (0x00000020) -#define MCF_INTC1_IPRH_INT38 (0x00000040) -#define MCF_INTC1_IPRH_INT39 (0x00000080) -#define MCF_INTC1_IPRH_INT40 (0x00000100) -#define MCF_INTC1_IPRH_INT41 (0x00000200) -#define MCF_INTC1_IPRH_INT42 (0x00000400) -#define MCF_INTC1_IPRH_INT43 (0x00000800) -#define MCF_INTC1_IPRH_INT44 (0x00001000) -#define MCF_INTC1_IPRH_INT45 (0x00002000) -#define MCF_INTC1_IPRH_INT46 (0x00004000) -#define MCF_INTC1_IPRH_INT47 (0x00008000) -#define MCF_INTC1_IPRH_INT48 (0x00010000) -#define MCF_INTC1_IPRH_INT49 (0x00020000) -#define MCF_INTC1_IPRH_INT50 (0x00040000) -#define MCF_INTC1_IPRH_INT51 (0x00080000) -#define MCF_INTC1_IPRH_INT52 (0x00100000) -#define MCF_INTC1_IPRH_INT53 (0x00200000) -#define MCF_INTC1_IPRH_INT54 (0x00400000) -#define MCF_INTC1_IPRH_INT55 (0x00800000) -#define MCF_INTC1_IPRH_INT56 (0x01000000) -#define MCF_INTC1_IPRH_INT57 (0x02000000) -#define MCF_INTC1_IPRH_INT58 (0x04000000) -#define MCF_INTC1_IPRH_INT59 (0x08000000) -#define MCF_INTC1_IPRH_INT60 (0x10000000) -#define MCF_INTC1_IPRH_INT61 (0x20000000) -#define MCF_INTC1_IPRH_INT62 (0x40000000) -#define MCF_INTC1_IPRH_INT63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_IPRL */ -#define MCF_INTC1_IPRL_INT1 (0x00000002) -#define MCF_INTC1_IPRL_INT2 (0x00000004) -#define MCF_INTC1_IPRL_INT3 (0x00000008) -#define MCF_INTC1_IPRL_INT4 (0x00000010) -#define MCF_INTC1_IPRL_INT5 (0x00000020) -#define MCF_INTC1_IPRL_INT6 (0x00000040) -#define MCF_INTC1_IPRL_INT7 (0x00000080) -#define MCF_INTC1_IPRL_INT8 (0x00000100) -#define MCF_INTC1_IPRL_INT9 (0x00000200) -#define MCF_INTC1_IPRL_INT10 (0x00000400) -#define MCF_INTC1_IPRL_INT11 (0x00000800) -#define MCF_INTC1_IPRL_INT12 (0x00001000) -#define MCF_INTC1_IPRL_INT13 (0x00002000) -#define MCF_INTC1_IPRL_INT14 (0x00004000) -#define MCF_INTC1_IPRL_INT15 (0x00008000) -#define MCF_INTC1_IPRL_INT16 (0x00010000) -#define MCF_INTC1_IPRL_INT17 (0x00020000) -#define MCF_INTC1_IPRL_INT18 (0x00040000) -#define MCF_INTC1_IPRL_INT19 (0x00080000) -#define MCF_INTC1_IPRL_INT20 (0x00100000) -#define MCF_INTC1_IPRL_INT21 (0x00200000) -#define MCF_INTC1_IPRL_INT22 (0x00400000) -#define MCF_INTC1_IPRL_INT23 (0x00800000) -#define MCF_INTC1_IPRL_INT24 (0x01000000) -#define MCF_INTC1_IPRL_INT25 (0x02000000) -#define MCF_INTC1_IPRL_INT26 (0x04000000) -#define MCF_INTC1_IPRL_INT27 (0x08000000) -#define MCF_INTC1_IPRL_INT28 (0x10000000) -#define MCF_INTC1_IPRL_INT29 (0x20000000) -#define MCF_INTC1_IPRL_INT30 (0x40000000) -#define MCF_INTC1_IPRL_INT31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_IMRH */ -#define MCF_INTC1_IMRH_INT_MASK32 (0x00000001) -#define MCF_INTC1_IMRH_INT_MASK33 (0x00000002) -#define MCF_INTC1_IMRH_INT_MASK34 (0x00000004) -#define MCF_INTC1_IMRH_INT_MASK35 (0x00000008) -#define MCF_INTC1_IMRH_INT_MASK36 (0x00000010) -#define MCF_INTC1_IMRH_INT_MASK37 (0x00000020) -#define MCF_INTC1_IMRH_INT_MASK38 (0x00000040) -#define MCF_INTC1_IMRH_INT_MASK39 (0x00000080) -#define MCF_INTC1_IMRH_INT_MASK40 (0x00000100) -#define MCF_INTC1_IMRH_INT_MASK41 (0x00000200) -#define MCF_INTC1_IMRH_INT_MASK42 (0x00000400) -#define MCF_INTC1_IMRH_INT_MASK43 (0x00000800) -#define MCF_INTC1_IMRH_INT_MASK44 (0x00001000) -#define MCF_INTC1_IMRH_INT_MASK45 (0x00002000) -#define MCF_INTC1_IMRH_INT_MASK46 (0x00004000) -#define MCF_INTC1_IMRH_INT_MASK47 (0x00008000) -#define MCF_INTC1_IMRH_INT_MASK48 (0x00010000) -#define MCF_INTC1_IMRH_INT_MASK49 (0x00020000) -#define MCF_INTC1_IMRH_INT_MASK50 (0x00040000) -#define MCF_INTC1_IMRH_INT_MASK51 (0x00080000) -#define MCF_INTC1_IMRH_INT_MASK52 (0x00100000) -#define MCF_INTC1_IMRH_INT_MASK53 (0x00200000) -#define MCF_INTC1_IMRH_INT_MASK54 (0x00400000) -#define MCF_INTC1_IMRH_INT_MASK55 (0x00800000) -#define MCF_INTC1_IMRH_INT_MASK56 (0x01000000) -#define MCF_INTC1_IMRH_INT_MASK57 (0x02000000) -#define MCF_INTC1_IMRH_INT_MASK58 (0x04000000) -#define MCF_INTC1_IMRH_INT_MASK59 (0x08000000) -#define MCF_INTC1_IMRH_INT_MASK60 (0x10000000) -#define MCF_INTC1_IMRH_INT_MASK61 (0x20000000) -#define MCF_INTC1_IMRH_INT_MASK62 (0x40000000) -#define MCF_INTC1_IMRH_INT_MASK63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_IMRL */ -#define MCF_INTC1_IMRL_MASKALL (0x00000001) -#define MCF_INTC1_IMRL_INT_MASK1 (0x00000002) -#define MCF_INTC1_IMRL_INT_MASK2 (0x00000004) -#define MCF_INTC1_IMRL_INT_MASK3 (0x00000008) -#define MCF_INTC1_IMRL_INT_MASK4 (0x00000010) -#define MCF_INTC1_IMRL_INT_MASK5 (0x00000020) -#define MCF_INTC1_IMRL_INT_MASK6 (0x00000040) -#define MCF_INTC1_IMRL_INT_MASK7 (0x00000080) -#define MCF_INTC1_IMRL_INT_MASK8 (0x00000100) -#define MCF_INTC1_IMRL_INT_MASK9 (0x00000200) -#define MCF_INTC1_IMRL_INT_MASK10 (0x00000400) -#define MCF_INTC1_IMRL_INT_MASK11 (0x00000800) -#define MCF_INTC1_IMRL_INT_MASK12 (0x00001000) -#define MCF_INTC1_IMRL_INT_MASK13 (0x00002000) -#define MCF_INTC1_IMRL_INT_MASK14 (0x00004000) -#define MCF_INTC1_IMRL_INT_MASK15 (0x00008000) -#define MCF_INTC1_IMRL_INT_MASK16 (0x00010000) -#define MCF_INTC1_IMRL_INT_MASK17 (0x00020000) -#define MCF_INTC1_IMRL_INT_MASK18 (0x00040000) -#define MCF_INTC1_IMRL_INT_MASK19 (0x00080000) -#define MCF_INTC1_IMRL_INT_MASK20 (0x00100000) -#define MCF_INTC1_IMRL_INT_MASK21 (0x00200000) -#define MCF_INTC1_IMRL_INT_MASK22 (0x00400000) -#define MCF_INTC1_IMRL_INT_MASK23 (0x00800000) -#define MCF_INTC1_IMRL_INT_MASK24 (0x01000000) -#define MCF_INTC1_IMRL_INT_MASK25 (0x02000000) -#define MCF_INTC1_IMRL_INT_MASK26 (0x04000000) -#define MCF_INTC1_IMRL_INT_MASK27 (0x08000000) -#define MCF_INTC1_IMRL_INT_MASK28 (0x10000000) -#define MCF_INTC1_IMRL_INT_MASK29 (0x20000000) -#define MCF_INTC1_IMRL_INT_MASK30 (0x40000000) -#define MCF_INTC1_IMRL_INT_MASK31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_INTFRCH */ -#define MCF_INTC1_INTFRCH_INTFRC32 (0x00000001) -#define MCF_INTC1_INTFRCH_INTFRC33 (0x00000002) -#define MCF_INTC1_INTFRCH_INTFRC34 (0x00000004) -#define MCF_INTC1_INTFRCH_INTFRC35 (0x00000008) -#define MCF_INTC1_INTFRCH_INTFRC36 (0x00000010) -#define MCF_INTC1_INTFRCH_INTFRC37 (0x00000020) -#define MCF_INTC1_INTFRCH_INTFRC38 (0x00000040) -#define MCF_INTC1_INTFRCH_INTFRC39 (0x00000080) -#define MCF_INTC1_INTFRCH_INTFRC40 (0x00000100) -#define MCF_INTC1_INTFRCH_INTFRC41 (0x00000200) -#define MCF_INTC1_INTFRCH_INTFRC42 (0x00000400) -#define MCF_INTC1_INTFRCH_INTFRC43 (0x00000800) -#define MCF_INTC1_INTFRCH_INTFRC44 (0x00001000) -#define MCF_INTC1_INTFRCH_INTFRC45 (0x00002000) -#define MCF_INTC1_INTFRCH_INTFRC46 (0x00004000) -#define MCF_INTC1_INTFRCH_INTFRC47 (0x00008000) -#define MCF_INTC1_INTFRCH_INTFRC48 (0x00010000) -#define MCF_INTC1_INTFRCH_INTFRC49 (0x00020000) -#define MCF_INTC1_INTFRCH_INTFRC50 (0x00040000) -#define MCF_INTC1_INTFRCH_INTFRC51 (0x00080000) -#define MCF_INTC1_INTFRCH_INTFRC52 (0x00100000) -#define MCF_INTC1_INTFRCH_INTFRC53 (0x00200000) -#define MCF_INTC1_INTFRCH_INTFRC54 (0x00400000) -#define MCF_INTC1_INTFRCH_INTFRC55 (0x00800000) -#define MCF_INTC1_INTFRCH_INTFRC56 (0x01000000) -#define MCF_INTC1_INTFRCH_INTFRC57 (0x02000000) -#define MCF_INTC1_INTFRCH_INTFRC58 (0x04000000) -#define MCF_INTC1_INTFRCH_INTFRC59 (0x08000000) -#define MCF_INTC1_INTFRCH_INTFRC60 (0x10000000) -#define MCF_INTC1_INTFRCH_INTFRC61 (0x20000000) -#define MCF_INTC1_INTFRCH_INTFRC62 (0x40000000) -#define MCF_INTC1_INTFRCH_INTFRC63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_INTFRCL */ -#define MCF_INTC1_INTFRCL_INTFRC1 (0x00000002) -#define MCF_INTC1_INTFRCL_INTFRC2 (0x00000004) -#define MCF_INTC1_INTFRCL_INTFRC3 (0x00000008) -#define MCF_INTC1_INTFRCL_INTFRC4 (0x00000010) -#define MCF_INTC1_INTFRCL_INTFRC5 (0x00000020) -#define MCF_INTC1_INTFRCL_INT6 (0x00000040) -#define MCF_INTC1_INTFRCL_INT7 (0x00000080) -#define MCF_INTC1_INTFRCL_INT8 (0x00000100) -#define MCF_INTC1_INTFRCL_INT9 (0x00000200) -#define MCF_INTC1_INTFRCL_INT10 (0x00000400) -#define MCF_INTC1_INTFRCL_INTFRC11 (0x00000800) -#define MCF_INTC1_INTFRCL_INTFRC12 (0x00001000) -#define MCF_INTC1_INTFRCL_INTFRC13 (0x00002000) -#define MCF_INTC1_INTFRCL_INTFRC14 (0x00004000) -#define MCF_INTC1_INTFRCL_INT15 (0x00008000) -#define MCF_INTC1_INTFRCL_INTFRC16 (0x00010000) -#define MCF_INTC1_INTFRCL_INTFRC17 (0x00020000) -#define MCF_INTC1_INTFRCL_INTFRC18 (0x00040000) -#define MCF_INTC1_INTFRCL_INTFRC19 (0x00080000) -#define MCF_INTC1_INTFRCL_INTFRC20 (0x00100000) -#define MCF_INTC1_INTFRCL_INTFRC21 (0x00200000) -#define MCF_INTC1_INTFRCL_INTFRC22 (0x00400000) -#define MCF_INTC1_INTFRCL_INTFRC23 (0x00800000) -#define MCF_INTC1_INTFRCL_INTFRC24 (0x01000000) -#define MCF_INTC1_INTFRCL_INTFRC25 (0x02000000) -#define MCF_INTC1_INTFRCL_INTFRC26 (0x04000000) -#define MCF_INTC1_INTFRCL_INTFRC27 (0x08000000) -#define MCF_INTC1_INTFRCL_INTFRC28 (0x10000000) -#define MCF_INTC1_INTFRCL_INTFRC29 (0x20000000) -#define MCF_INTC1_INTFRCL_INTFRC30 (0x40000000) -#define MCF_INTC1_INTFRCL_INTFRC31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_IRLR */ -#define MCF_INTC1_IRLR_IRQ(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_INTC1_IACKLPR */ -#define MCF_INTC1_IACKLPR_PRI(x) (((x)&0x0F)<<0) -#define MCF_INTC1_IACKLPR_LEVEL(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF_INTC1_ICRn */ -#define MCF_INTC1_ICRn_IP(x) (((x)&0x07)<<0) -#define MCF_INTC1_ICRn_IL(x) (((x)&0x07)<<3) - -/********************************************************************/ - -#endif /* __MCF523X_INTC1_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_mdha.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_mdha.h deleted file mode 100644 index 1d61bf57d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_mdha.h +++ /dev/null @@ -1,108 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_mdha.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_MDHA_H__ -#define __MCF523X_MDHA_H__ - -/********************************************************************* -* -* Message Digest Hardware Accelerator (MDHA) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_MDHA_MDMR (*(vuint32*)(void*)(&__IPSBAR[0x190000])) -#define MCF_MDHA_MDCR (*(vuint32*)(void*)(&__IPSBAR[0x190004])) -#define MCF_MDHA_MDCMR (*(vuint32*)(void*)(&__IPSBAR[0x190008])) -#define MCF_MDHA_MDSR (*(vuint32*)(void*)(&__IPSBAR[0x19000C])) -#define MCF_MDHA_MDISR (*(vuint32*)(void*)(&__IPSBAR[0x190010])) -#define MCF_MDHA_MDIMR (*(vuint32*)(void*)(&__IPSBAR[0x190014])) -#define MCF_MDHA_MDDSR (*(vuint32*)(void*)(&__IPSBAR[0x19001C])) -#define MCF_MDHA_MDIN (*(vuint32*)(void*)(&__IPSBAR[0x190020])) -#define MCF_MDHA_MDA0 (*(vuint32*)(void*)(&__IPSBAR[0x190030])) -#define MCF_MDHA_MDB0 (*(vuint32*)(void*)(&__IPSBAR[0x190034])) -#define MCF_MDHA_MDC0 (*(vuint32*)(void*)(&__IPSBAR[0x190038])) -#define MCF_MDHA_MDD0 (*(vuint32*)(void*)(&__IPSBAR[0x19003C])) -#define MCF_MDHA_MDE0 (*(vuint32*)(void*)(&__IPSBAR[0x190040])) -#define MCF_MDHA_MDMDS (*(vuint32*)(void*)(&__IPSBAR[0x190044])) -#define MCF_MDHA_MDA1 (*(vuint32*)(void*)(&__IPSBAR[0x190070])) -#define MCF_MDHA_MDB1 (*(vuint32*)(void*)(&__IPSBAR[0x190074])) -#define MCF_MDHA_MDC1 (*(vuint32*)(void*)(&__IPSBAR[0x190078])) -#define MCF_MDHA_MDD1 (*(vuint32*)(void*)(&__IPSBAR[0x19007C])) -#define MCF_MDHA_MDE1 (*(vuint32*)(void*)(&__IPSBAR[0x190080])) - -/* Bit definitions and macros for MCF_MDHA_MDMR */ -#define MCF_MDHA_MDMR_ALG (0x00000001) -#define MCF_MDHA_MDMR_PDATA (0x00000004) -#define MCF_MDHA_MDMR_MAC(x) (((x)&0x00000003)<<3) -#define MCF_MDHA_MDMR_INIT (0x00000020) -#define MCF_MDHA_MDMR_IPAD (0x00000040) -#define MCF_MDHA_MDMR_OPAD (0x00000080) -#define MCF_MDHA_MDMR_SWAP (0x00000100) -#define MCF_MDHA_MDMR_MACFULL (0x00000200) -#define MCF_MDHA_MDMR_SSL (0x00000400) - -/* Bit definitions and macros for MCF_MDHA_MDCR */ -#define MCF_MDHA_MDCR_IE (0x00000001) - -/* Bit definitions and macros for MCF_MDHA_MDCMR */ -#define MCF_MDHA_MDCMR_IE (0x00000001) -#define MCF_MDHA_MDCMR_RI (0x00000002) -#define MCF_MDHA_MDCMR_CI (0x00000004) -#define MCF_MDHA_MDCMR_GO (0x00000008) - -/* Bit definitions and macros for MCF_MDHA_MDSR */ -#define MCF_MDHA_MDSR_INT (0x00000001) -#define MCF_MDHA_MDSR_DONE (0x00000002) -#define MCF_MDHA_MDSR_ERR (0x00000004) -#define MCF_MDHA_MDSR_RD (0x00000008) -#define MCF_MDHA_MDSR_BUSY (0x00000010) -#define MCF_MDHA_MDSR_END (0x00000020) -#define MCF_MDHA_MDSR_HSH (0x00000040) -#define MCF_MDHA_MDSR_GNW (0x00000080) -#define MCF_MDHA_MDSR_FS(x) (((x)&0x00000007)<<8) -#define MCF_MDHA_MDSR_APD(x) (((x)&0x00000007)<<13) -#define MCF_MDHA_MDSR_IFL(x) (((x)&0x000000FF)<<16) - -/* Bit definitions and macros for MCF_MDHA_MDIR */ -#define MCF_MDHA_MDIR_IFO (0x00000001) -#define MCF_MDHA_MDIR_NON (0x00000004) -#define MCF_MDHA_MDIR_IME (0x00000010) -#define MCF_MDHA_MDIR_IDS (0x00000020) -#define MCF_MDHA_MDIR_RMDP (0x00000080) -#define MCF_MDHA_MDIR_ERE (0x00000100) -#define MCF_MDHA_MDIR_GTDS (0x00000200) - -/* Bit definitions and macros for MCF_MDHA_MDIMR */ -#define MCF_MDHA_MDIMR_IFO (0x00000001) -#define MCF_MDHA_MDIMR_NON (0x00000004) -#define MCF_MDHA_MDIMR_IME (0x00000010) -#define MCF_MDHA_MDIMR_IDS (0x00000020) -#define MCF_MDHA_MDIMR_RMDP (0x00000080) -#define MCF_MDHA_MDIMR_ERE (0x00000100) -#define MCF_MDHA_MDIMR_GTDS (0x00000200) - -/* Bit definitions and macros for MCF_MDHA_MDDSR */ -#define MCF_MDHA_MDDSR_DATASIZE(x) (((x)&0x1FFFFFFF)<<0) - -/********************************************************************/ - -#endif /* __MCF523X_MDHA_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_pit.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_pit.h deleted file mode 100644 index 9aece7b8b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_pit.h +++ /dev/null @@ -1,96 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_pit.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_PIT_H__ -#define __MCF523X_PIT_H__ - -/********************************************************************* -* -* Programmable Interrupt Timer Modules (PIT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PIT_PCSR0 (*(vuint16*)(void*)(&__IPSBAR[0x150000])) -#define MCF_PIT_PMR0 (*(vuint16*)(void*)(&__IPSBAR[0x150002])) -#define MCF_PIT_PCNTR0 (*(vuint16*)(void*)(&__IPSBAR[0x150004])) -#define MCF_PIT_PCSR1 (*(vuint16*)(void*)(&__IPSBAR[0x160000])) -#define MCF_PIT_PMR1 (*(vuint16*)(void*)(&__IPSBAR[0x160002])) -#define MCF_PIT_PCNTR1 (*(vuint16*)(void*)(&__IPSBAR[0x160004])) -#define MCF_PIT_PCSR2 (*(vuint16*)(void*)(&__IPSBAR[0x170000])) -#define MCF_PIT_PMR2 (*(vuint16*)(void*)(&__IPSBAR[0x170002])) -#define MCF_PIT_PCNTR2 (*(vuint16*)(void*)(&__IPSBAR[0x170004])) -#define MCF_PIT_PCSR3 (*(vuint16*)(void*)(&__IPSBAR[0x180000])) -#define MCF_PIT_PMR3 (*(vuint16*)(void*)(&__IPSBAR[0x180002])) -#define MCF_PIT_PCNTR3 (*(vuint16*)(void*)(&__IPSBAR[0x180004])) -#define MCF_PIT_PCSR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150000+((x)*0x10000)])) -#define MCF_PIT_PMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150002+((x)*0x10000)])) -#define MCF_PIT_PCNTR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150004+((x)*0x10000)])) - -/* Bit definitions and macros for MCF_PIT_PCSR */ -#define MCF_PIT_PCSR_EN (0x0001) -#define MCF_PIT_PCSR_RLD (0x0002) -#define MCF_PIT_PCSR_PIF (0x0004) -#define MCF_PIT_PCSR_PIE (0x0008) -#define MCF_PIT_PCSR_OVW (0x0010) -#define MCF_PIT_PCSR_HALTED (0x0020) -#define MCF_PIT_PCSR_DOZE (0x0040) -#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) - -/* Bit definitions and macros for MCF_PIT_PMR */ -#define MCF_PIT_PMR_PM0 (0x0001) -#define MCF_PIT_PMR_PM1 (0x0002) -#define MCF_PIT_PMR_PM2 (0x0004) -#define MCF_PIT_PMR_PM3 (0x0008) -#define MCF_PIT_PMR_PM4 (0x0010) -#define MCF_PIT_PMR_PM5 (0x0020) -#define MCF_PIT_PMR_PM6 (0x0040) -#define MCF_PIT_PMR_PM7 (0x0080) -#define MCF_PIT_PMR_PM8 (0x0100) -#define MCF_PIT_PMR_PM9 (0x0200) -#define MCF_PIT_PMR_PM10 (0x0400) -#define MCF_PIT_PMR_PM11 (0x0800) -#define MCF_PIT_PMR_PM12 (0x1000) -#define MCF_PIT_PMR_PM13 (0x2000) -#define MCF_PIT_PMR_PM14 (0x4000) -#define MCF_PIT_PMR_PM15 (0x8000) - -/* Bit definitions and macros for MCF_PIT_PCNTR */ -#define MCF_PIT_PCNTR_PC0 (0x0001) -#define MCF_PIT_PCNTR_PC1 (0x0002) -#define MCF_PIT_PCNTR_PC2 (0x0004) -#define MCF_PIT_PCNTR_PC3 (0x0008) -#define MCF_PIT_PCNTR_PC4 (0x0010) -#define MCF_PIT_PCNTR_PC5 (0x0020) -#define MCF_PIT_PCNTR_PC6 (0x0040) -#define MCF_PIT_PCNTR_PC7 (0x0080) -#define MCF_PIT_PCNTR_PC8 (0x0100) -#define MCF_PIT_PCNTR_PC9 (0x0200) -#define MCF_PIT_PCNTR_PC10 (0x0400) -#define MCF_PIT_PCNTR_PC11 (0x0800) -#define MCF_PIT_PCNTR_PC12 (0x1000) -#define MCF_PIT_PCNTR_PC13 (0x2000) -#define MCF_PIT_PCNTR_PC14 (0x4000) -#define MCF_PIT_PCNTR_PC15 (0x8000) - -/********************************************************************/ - -#endif /* __MCF523X_PIT_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_qspi.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_qspi.h deleted file mode 100644 index e6c2edc54..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_qspi.h +++ /dev/null @@ -1,76 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_qspi.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_QSPI_H__ -#define __MCF523X_QSPI_H__ - -/********************************************************************* -* -* Queued Serial Peripheral Interface (QSPI) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_QSPI_QMR (*(vuint16*)(void*)(&__IPSBAR[0x000340])) -#define MCF_QSPI_QDLYR (*(vuint16*)(void*)(&__IPSBAR[0x000344])) -#define MCF_QSPI_QWR (*(vuint16*)(void*)(&__IPSBAR[0x000348])) -#define MCF_QSPI_QIR (*(vuint16*)(void*)(&__IPSBAR[0x00034C])) -#define MCF_QSPI_QAR (*(vuint16*)(void*)(&__IPSBAR[0x000350])) -#define MCF_QSPI_QDR (*(vuint16*)(void*)(&__IPSBAR[0x000354])) - -/* Bit definitions and macros for MCF_QSPI_QMR */ -#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) -#define MCF_QSPI_QMR_CPHA (0x0100) -#define MCF_QSPI_QMR_CPOL (0x0200) -#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) -#define MCF_QSPI_QMR_DOHIE (0x4000) -#define MCF_QSPI_QMR_MSTR (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QDLYR */ -#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) -#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) -#define MCF_QSPI_QDLYR_SPE (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QWR */ -#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) -#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) -#define MCF_QSPI_QWR_CSIV (0x1000) -#define MCF_QSPI_QWR_WRTO (0x2000) -#define MCF_QSPI_QWR_WREN (0x4000) -#define MCF_QSPI_QWR_HALT (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QIR */ -#define MCF_QSPI_QIR_SPIF (0x0001) -#define MCF_QSPI_QIR_ABRT (0x0004) -#define MCF_QSPI_QIR_WCEF (0x0008) -#define MCF_QSPI_QIR_SPIFE (0x0100) -#define MCF_QSPI_QIR_ABRTE (0x0400) -#define MCF_QSPI_QIR_WCEFE (0x0800) -#define MCF_QSPI_QIR_ABRTL (0x1000) -#define MCF_QSPI_QIR_ABRTB (0x4000) -#define MCF_QSPI_QIR_WCEFB (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QAR */ -#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) - -/********************************************************************/ - -#endif /* __MCF523X_QSPI_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_rcm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_rcm.h deleted file mode 100644 index ec4d66ac1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_rcm.h +++ /dev/null @@ -1,49 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_rcm.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_RCM_H__ -#define __MCF523X_RCM_H__ - -/********************************************************************* -* -* Reset Configuration Module (RCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_RCM_RCR (*(vuint8 *)(void*)(&__IPSBAR[0x110000])) -#define MCF_RCM_RSR (*(vuint8 *)(void*)(&__IPSBAR[0x110001])) - -/* Bit definitions and macros for MCF_RCM_RCR */ -#define MCF_RCM_RCR_FRCRSTOUT (0x40) -#define MCF_RCM_RCR_SOFTRST (0x80) - -/* Bit definitions and macros for MCF_RCM_RSR */ -#define MCF_RCM_RSR_LOL (0x01) -#define MCF_RCM_RSR_LOC (0x02) -#define MCF_RCM_RSR_EXT (0x04) -#define MCF_RCM_RSR_POR (0x08) -#define MCF_RCM_RSR_WDR (0x10) -#define MCF_RCM_RSR_SOFT (0x20) - -/********************************************************************/ - -#endif /* __MCF523X_RCM_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_rng.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_rng.h deleted file mode 100644 index ebad773bb..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_rng.h +++ /dev/null @@ -1,54 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_rng.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - - -#ifndef __MCF523X_RNG_H__ -#define __MCF523X_RNG_H__ - -/********************************************************************* -* -* Random Number Generator (RNG) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_RNG_RNGCR (*(vuint32*)(void*)(&__IPSBAR[0x1A0000])) -#define MCF_RNG_RNGSR (*(vuint32*)(void*)(&__IPSBAR[0x1A0004])) -#define MCF_RNG_RNGER (*(vuint32*)(void*)(&__IPSBAR[0x1A0008])) -#define MCF_RNG_RNGOUT (*(vuint32*)(void*)(&__IPSBAR[0x1A000C])) - -/* Bit definitions and macros for MCF_RNG_RNGCR */ -#define MCF_RNG_RNGCR_GO (0x00000001) -#define MCF_RNG_RNGCR_HA (0x00000002) -#define MCF_RNG_RNGCR_IM (0x00000004) -#define MCF_RNG_RNGCR_CI (0x00000008) - -/* Bit definitions and macros for MCF_RNG_RNGSR */ -#define MCF_RNG_RNGSR_SV (0x00000001) -#define MCF_RNG_RNGSR_LRS (0x00000002) -#define MCF_RNG_RNGSR_FUF (0x00000004) -#define MCF_RNG_RNGSR_EI (0x00000008) -#define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8) -#define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16) - -/********************************************************************/ - -#endif /* __MCF523X_RNG_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_scm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_scm.h deleted file mode 100644 index 9f13bd2fd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_scm.h +++ /dev/null @@ -1,158 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_scm.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - - -#ifndef __MCF523X_SCM_H__ -#define __MCF523X_SCM_H__ - -/********************************************************************* -* -* System Control Module (SCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SCM_IPSBAR (*(vuint32*)(void*)(&__IPSBAR[0x000000])) -#define MCF_SCM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x000008])) -#define MCF_SCM_CRSR (*(vuint8 *)(void*)(&__IPSBAR[0x000010])) -#define MCF_SCM_CWCR (*(vuint8 *)(void*)(&__IPSBAR[0x000011])) -#define MCF_SCM_LPICR (*(vuint8 *)(void*)(&__IPSBAR[0x000012])) -#define MCF_SCM_CWSR (*(vuint8 *)(void*)(&__IPSBAR[0x000013])) -#define MCF_SCM_DMAREQC (*(vuint32*)(void*)(&__IPSBAR[0x000014])) -#define MCF_SCM_MPARK (*(vuint32*)(void*)(&__IPSBAR[0x00001C])) -#define MCF_SCM_MPR (*(vuint8 *)(void*)(&__IPSBAR[0x000020])) -#define MCF_SCM_PACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000024])) -#define MCF_SCM_PACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000025])) -#define MCF_SCM_PACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000026])) -#define MCF_SCM_PACR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000027])) -#define MCF_SCM_PACR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000028])) -#define MCF_SCM_PACR5 (*(vuint8 *)(void*)(&__IPSBAR[0x00002A])) -#define MCF_SCM_PACR6 (*(vuint8 *)(void*)(&__IPSBAR[0x00002B])) -#define MCF_SCM_PACR7 (*(vuint8 *)(void*)(&__IPSBAR[0x00002C])) -#define MCF_SCM_PACR8 (*(vuint8 *)(void*)(&__IPSBAR[0x00002E])) -#define MCF_SCM_GPACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000030])) - -/* Bit definitions and macros for MCF_SCM_IPSBAR */ -#define MCF_SCM_IPSBAR_V (0x00000001) -#define MCF_SCM_IPSBAR_BA(x) (((x)&0x00000003)<<30) - -/* Bit definitions and macros for MCF_SCM_RAMBAR */ -#define MCF_SCM_RAMBAR_BDE (0x00000200) -#define MCF_SCM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_SCM_CRSR */ -#define MCF_SCM_CRSR_CWDR (0x20) -#define MCF_SCM_CRSR_EXT (0x80) - -/* Bit definitions and macros for MCF_SCM_CWCR */ -#define MCF_SCM_CWCR_CWTIC (0x01) -#define MCF_SCM_CWCR_CWTAVAL (0x02) -#define MCF_SCM_CWCR_CWTA (0x04) -#define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3) -#define MCF_SCM_CWCR_CWRI (0x40) -#define MCF_SCM_CWCR_CWE (0x80) - -/* Bit definitions and macros for MCF_SCM_LPICR */ -#define MCF_SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4) -#define MCF_SCM_LPICR_ENBSTOP (0x80) - -/* Bit definitions and macros for MCF_SCM_DMAREQC */ -#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0) -#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4) -#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8) -#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12) - -/* Bit definitions and macros for MCF_SCM_MPARK */ -#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8) -#define MCF_SCM_MPARK_PRKLAST (0x00001000) -#define MCF_SCM_MPARK_TIMEOUT (0x00002000) -#define MCF_SCM_MPARK_FIXED (0x00004000) -#define MCF_SCM_MPARK_M1_PRTY(x) (((x)&0x00000003)<<16) -#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x00000003)<<18) -#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x00000003)<<20) -#define MCF_SCM_MPARK_M3_PRTY(x) (((x)&0x00000003)<<22) -#define MCF_SCM_MPARK_BCR24BIT (0x01000000) -#define MCF_SCM_MPARK_M2_P_EN (0x02000000) - -/* Bit definitions and macros for MCF_SCM_MPR */ -#define MCF_SCM_MPR_MPR(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF_SCM_PACR0 */ -#define MCF_SCM_PACR0_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR0_LOCK0 (0x08) -#define MCF_SCM_PACR0_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR0_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR1 */ -#define MCF_SCM_PACR1_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR1_LOCK0 (0x08) -#define MCF_SCM_PACR1_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR1_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR2 */ -#define MCF_SCM_PACR2_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR2_LOCK0 (0x08) -#define MCF_SCM_PACR2_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR2_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR3 */ -#define MCF_SCM_PACR3_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR3_LOCK0 (0x08) -#define MCF_SCM_PACR3_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR3_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR4 */ -#define MCF_SCM_PACR4_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR4_LOCK0 (0x08) -#define MCF_SCM_PACR4_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR4_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR5 */ -#define MCF_SCM_PACR5_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR5_LOCK0 (0x08) -#define MCF_SCM_PACR5_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR5_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR6 */ -#define MCF_SCM_PACR6_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR6_LOCK0 (0x08) -#define MCF_SCM_PACR6_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR6_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR7 */ -#define MCF_SCM_PACR7_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR7_LOCK0 (0x08) -#define MCF_SCM_PACR7_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR7_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR8 */ -#define MCF_SCM_PACR8_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR8_LOCK0 (0x08) -#define MCF_SCM_PACR8_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR8_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_GPACR0 */ -#define MCF_SCM_GPACR0_ACCESS_CTRL(x) (((x)&0x0F)<<0) -#define MCF_SCM_GPACR0_LOCK (0x80) - -/********************************************************************/ - -#endif /* __MCF523X_SCM_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_sdramc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_sdramc.h deleted file mode 100644 index ff99eb3c0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_sdramc.h +++ /dev/null @@ -1,101 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_sdramc.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_SDRAMC_H__ -#define __MCF523X_SDRAMC_H__ - -/********************************************************************* -* -* SDRAM Controller (SDRAMC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SDRAMC_DCR (*(vuint16*)(void*)(&__IPSBAR[0x000040])) -#define MCF_SDRAMC_DACR0 (*(vuint32*)(void*)(&__IPSBAR[0x000048])) -#define MCF_SDRAMC_DMR0 (*(vuint32*)(void*)(&__IPSBAR[0x00004C])) -#define MCF_SDRAMC_DACR1 (*(vuint32*)(void*)(&__IPSBAR[0x000050])) -#define MCF_SDRAMC_DMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000054])) - -/* Bit definitions and macros for MCF_SDRAMC_DCR */ -#define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0) -#define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9) -#define MCF_SDRAMC_DCR_IS (0x0800) -#define MCF_SDRAMC_DCR_COC (0x1000) -#define MCF_SDRAMC_DCR_NAM (0x2000) - -/* Bit definitions and macros for MCF_SDRAMC_DACR0 */ -#define MCF_SDRAMC_DACR0_IP (0x00000008) -#define MCF_SDRAMC_DACR0_PS(x) (((x)&0x00000003)<<4) -#define MCF_SDRAMC_DACR0_MRS (0x00000040) -#define MCF_SDRAMC_DACR0_CBM(x) (((x)&0x00000007)<<8) -#define MCF_SDRAMC_DACR0_CASL(x) (((x)&0x00000003)<<12) -#define MCF_SDRAMC_DACR0_RE (0x00008000) -#define MCF_SDRAMC_DACR0_BA(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF_SDRAMC_DMR0 */ -#define MCF_SDRAMC_DMR0_V (0x00000001) -#define MCF_SDRAMC_DMR0_WP (0x00000100) -#define MCF_SDRAMC_DMR0_BAM(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF_SDRAMC_DACR1 */ -#define MCF_SDRAMC_DACR1_IP (0x00000008) -#define MCF_SDRAMC_DACR1_PS(x) (((x)&0x00000003)<<4) -#define MCF_SDRAMC_DACR1_MRS (0x00000040) -#define MCF_SDRAMC_DACR1_CBM(x) (((x)&0x00000007)<<8) -#define MCF_SDRAMC_DACR1_CASL(x) (((x)&0x00000003)<<12) -#define MCF_SDRAMC_DACR1_RE (0x00008000) -#define MCF_SDRAMC_DACR1_BA(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF_SDRAMC_DMR1 */ -#define MCF_SDRAMC_DMR1_V (0x00000001) -#define MCF_SDRAMC_DMR1_WP (0x00000100) -#define MCF_SDRAMC_DMR1_BAM(x) (((x)&0x00003FFF)<<18) - -/********************************************************************/ - -#define MCF_SDRAMC_DMR_BAM_4G (0xFFFC0000) -#define MCF_SDRAMC_DMR_BAM_2G (0x7FFC0000) -#define MCF_SDRAMC_DMR_BAM_1G (0x3FFC0000) -#define MCF_SDRAMC_DMR_BAM_1024M (0x3FFC0000) -#define MCF_SDRAMC_DMR_BAM_512M (0x1FFC0000) -#define MCF_SDRAMC_DMR_BAM_256M (0x0FFC0000) -#define MCF_SDRAMC_DMR_BAM_128M (0x07FC0000) -#define MCF_SDRAMC_DMR_BAM_64M (0x03FC0000) -#define MCF_SDRAMC_DMR_BAM_32M (0x01FC0000) -#define MCF_SDRAMC_DMR_BAM_16M (0x00FC0000) -#define MCF_SDRAMC_DMR_BAM_8M (0x007C0000) -#define MCF_SDRAMC_DMR_BAM_4M (0x003C0000) -#define MCF_SDRAMC_DMR_BAM_2M (0x001C0000) -#define MCF_SDRAMC_DMR_BAM_1M (0x000C0000) -#define MCF_SDRAMC_DMR_BAM_1024K (0x000C0000) -#define MCF_SDRAMC_DMR_BAM_512K (0x00040000) -#define MCF_SDRAMC_DMR_BAM_256K (0x00000000) -#define MCF_SDRAMC_DMR_WP (0x00000100) -#define MCF_SDRAMC_DMR_CI (0x00000040) -#define MCF_SDRAMC_DMR_AM (0x00000020) -#define MCF_SDRAMC_DMR_SC (0x00000010) -#define MCF_SDRAMC_DMR_SD (0x00000008) -#define MCF_SDRAMC_DMR_UC (0x00000004) -#define MCF_SDRAMC_DMR_UD (0x00000002) -#define MCF_SDRAMC_DMR_V (0x00000001) - -#endif /* __MCF523X_SDRAMC_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_skha.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_skha.h deleted file mode 100644 index 9b613f765..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_skha.h +++ /dev/null @@ -1,127 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_skha.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_SKHA_H__ -#define __MCF523X_SKHA_H__ - -/********************************************************************* -* -* Symmetric Key Hardware Accelerator (SKHA) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SKHA_SKMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0000])) -#define MCF_SKHA_SKCR (*(vuint32*)(void*)(&__IPSBAR[0x1B0004])) -#define MCF_SKHA_SKCMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0008])) -#define MCF_SKHA_SKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B000C])) -#define MCF_SKHA_SKIR (*(vuint32*)(void*)(&__IPSBAR[0x1B0010])) -#define MCF_SKHA_SKIMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0014])) -#define MCF_SKHA_SKKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B0018])) -#define MCF_SKHA_SKDSR (*(vuint32*)(void*)(&__IPSBAR[0x1B001C])) -#define MCF_SKHA_SKIN (*(vuint32*)(void*)(&__IPSBAR[0x1B0020])) -#define MCF_SKHA_SKOUT (*(vuint32*)(void*)(&__IPSBAR[0x1B0024])) -#define MCF_SKHA_SKKDR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0030])) -#define MCF_SKHA_SKKDR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0034])) -#define MCF_SKHA_SKKDR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0038])) -#define MCF_SKHA_SKKDR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B003C])) -#define MCF_SKHA_SKKDR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0040])) -#define MCF_SKHA_SKKDR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0044])) -#define MCF_SKHA_SKKDRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0030+((x)*0x004)])) -#define MCF_SKHA_SKCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0070])) -#define MCF_SKHA_SKCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0074])) -#define MCF_SKHA_SKCR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0078])) -#define MCF_SKHA_SKCR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B007C])) -#define MCF_SKHA_SKCR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0080])) -#define MCF_SKHA_SKCR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0084])) -#define MCF_SKHA_SKCR6 (*(vuint32*)(void*)(&__IPSBAR[0x1B0088])) -#define MCF_SKHA_SKCR7 (*(vuint32*)(void*)(&__IPSBAR[0x1B008C])) -#define MCF_SKHA_SKCR8 (*(vuint32*)(void*)(&__IPSBAR[0x1B0090])) -#define MCF_SKHA_SKCR9 (*(vuint32*)(void*)(&__IPSBAR[0x1B0094])) -#define MCF_SKHA_SKCR10 (*(vuint32*)(void*)(&__IPSBAR[0x1B0098])) -#define MCF_SKHA_SKCR11 (*(vuint32*)(void*)(&__IPSBAR[0x1B009C])) -#define MCF_SKHA_SKCRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0070+((x)*0x004)])) - -/* Bit definitions and macros for MCF_SKHA_SKMR */ -#define MCF_SKHA_SKMR_ALG(x) (((x)&0x00000003)<<0) -#define MCF_SKHA_SKMR_DIR (0x00000004) -#define MCF_SKHA_SKMR_CM(x) (((x)&0x00000003)<<3) -#define MCF_SKHA_SKMR_DKP (0x00000100) -#define MCF_SKHA_SKMR_CTRM(x) (((x)&0x0000000F)<<9) -#define MCF_SKHA_SKMR_CM_ECB (0x00000000) -#define MCF_SKHA_SKMR_CM_CBC (0x00000008) -#define MCF_SKHA_SKMR_CM_CTR (0x00000018) -#define MCF_SKHA_SKMR_DIR_DEC (0x00000000) -#define MCF_SKHA_SKMR_DIR_ENC (0x00000004) -#define MCF_SKHA_SKMR_ALG_AES (0x00000000) -#define MCF_SKHA_SKMR_ALG_DES (0x00000001) -#define MCF_SKHA_SKMR_ALG_TDES (0x00000002) - -/* Bit definitions and macros for MCF_SKHA_SKCR */ -#define MCF_SKHA_SKCR_IE (0x00000001) - -/* Bit definitions and macros for MCF_SKHA_SKCMR */ -#define MCF_SKHA_SKCMR_SWR (0x00000001) -#define MCF_SKHA_SKCMR_RI (0x00000002) -#define MCF_SKHA_SKCMR_CI (0x00000004) -#define MCF_SKHA_SKCMR_GO (0x00000008) - -/* Bit definitions and macros for MCF_SKHA_SKSR */ -#define MCF_SKHA_SKSR_INT (0x00000001) -#define MCF_SKHA_SKSR_DONE (0x00000002) -#define MCF_SKHA_SKSR_ERR (0x00000004) -#define MCF_SKHA_SKSR_RD (0x00000008) -#define MCF_SKHA_SKSR_BUSY (0x00000010) -#define MCF_SKHA_SKSR_IFL(x) (((x)&0x000000FF)<<16) -#define MCF_SKHA_SKSR_OFL(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_SKHA_SKIR */ -#define MCF_SKHA_SKIR_IFO (0x00000001) -#define MCF_SKHA_SKIR_OFU (0x00000002) -#define MCF_SKHA_SKIR_NEIF (0x00000004) -#define MCF_SKHA_SKIR_NEOF (0x00000008) -#define MCF_SKHA_SKIR_IME (0x00000010) -#define MCF_SKHA_SKIR_DSE (0x00000020) -#define MCF_SKHA_SKIR_KSE (0x00000040) -#define MCF_SKHA_SKIR_RMDP (0x00000080) -#define MCF_SKHA_SKIR_ERE (0x00000100) -#define MCF_SKHA_SKIR_KPE (0x00000200) -#define MCF_SKHA_SKIR_KRE (0x00000400) - -/* Bit definitions and macros for MCF_SKHA_SKIMR */ -#define MCF_SKHA_SKIMR_IFO (0x00000001) -#define MCF_SKHA_SKIMR_OFU (0x00000002) -#define MCF_SKHA_SKIMR_NEIF (0x00000004) -#define MCF_SKHA_SKIMR_NEOF (0x00000008) -#define MCF_SKHA_SKIMR_IME (0x00000010) -#define MCF_SKHA_SKIMR_DSE (0x00000020) -#define MCF_SKHA_SKIMR_KSE (0x00000040) -#define MCF_SKHA_SKIMR_RMDP (0x00000080) -#define MCF_SKHA_SKIMR_ERE (0x00000100) -#define MCF_SKHA_SKIMR_KPE (0x00000200) -#define MCF_SKHA_SKIMR_KRE (0x00000400) - -/* Bit definitions and macros for MCF_SKHA_SKKSR */ -#define MCF_SKHA_SKKSR_KEYSIZE(x) (((x)&0x0000003F)<<0) - -/********************************************************************/ - -#endif /* __MCF523X_SKHA_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_sram.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_sram.h deleted file mode 100644 index 9b5fafd0b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_sram.h +++ /dev/null @@ -1,49 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_sram.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_SRAM_H__ -#define __MCF523X_SRAM_H__ - -/********************************************************************* -* -* 64KByte System SRAM (SRAM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SRAM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x20000000])) - -/* Bit definitions and macros for MCF_SRAM_RAMBAR */ -#define MCF_SRAM_RAMBAR_V (0x00000001) -#define MCF_SRAM_RAMBAR_UD (0x00000002) -#define MCF_SRAM_RAMBAR_UC (0x00000004) -#define MCF_SRAM_RAMBAR_SD (0x00000008) -#define MCF_SRAM_RAMBAR_SC (0x00000010) -#define MCF_SRAM_RAMBAR_CI (0x00000020) -#define MCF_SRAM_RAMBAR_WP (0x00000100) -#define MCF_SRAM_RAMBAR_SPV (0x00000200) -#define MCF_SRAM_RAMBAR_PRI2 (0x00000400) -#define MCF_SRAM_RAMBAR_PRI1 (0x00000800) -#define MCF_SRAM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16) - -/********************************************************************/ - -#endif /* __MCF523X_SRAM_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_timer.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_timer.h deleted file mode 100644 index b192a2b7c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_timer.h +++ /dev/null @@ -1,90 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_timer.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_TIMER_H__ -#define __MCF523X_TIMER_H__ - -/********************************************************************* -* -* DMA Timers (TIMER) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_TIMER_DTMR0 (*(vuint16*)(void*)(&__IPSBAR[0x000400])) -#define MCF_TIMER_DTXMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000402])) -#define MCF_TIMER_DTER0 (*(vuint8 *)(void*)(&__IPSBAR[0x000403])) -#define MCF_TIMER_DTRR0 (*(vuint32*)(void*)(&__IPSBAR[0x000404])) -#define MCF_TIMER_DTCR0 (*(vuint32*)(void*)(&__IPSBAR[0x000408])) -#define MCF_TIMER_DTCN0 (*(vuint32*)(void*)(&__IPSBAR[0x00040C])) -#define MCF_TIMER_DTMR1 (*(vuint16*)(void*)(&__IPSBAR[0x000440])) -#define MCF_TIMER_DTXMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000442])) -#define MCF_TIMER_DTER1 (*(vuint8 *)(void*)(&__IPSBAR[0x000443])) -#define MCF_TIMER_DTRR1 (*(vuint32*)(void*)(&__IPSBAR[0x000444])) -#define MCF_TIMER_DTCR1 (*(vuint32*)(void*)(&__IPSBAR[0x000448])) -#define MCF_TIMER_DTCN1 (*(vuint32*)(void*)(&__IPSBAR[0x00044C])) -#define MCF_TIMER_DTMR2 (*(vuint16*)(void*)(&__IPSBAR[0x000480])) -#define MCF_TIMER_DTXMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000482])) -#define MCF_TIMER_DTER2 (*(vuint8 *)(void*)(&__IPSBAR[0x000483])) -#define MCF_TIMER_DTRR2 (*(vuint32*)(void*)(&__IPSBAR[0x000484])) -#define MCF_TIMER_DTCR2 (*(vuint32*)(void*)(&__IPSBAR[0x000488])) -#define MCF_TIMER_DTCN2 (*(vuint32*)(void*)(&__IPSBAR[0x00048C])) -#define MCF_TIMER_DTMR3 (*(vuint16*)(void*)(&__IPSBAR[0x0004C0])) -#define MCF_TIMER_DTXMR3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C2])) -#define MCF_TIMER_DTER3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C3])) -#define MCF_TIMER_DTRR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C4])) -#define MCF_TIMER_DTCR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C8])) -#define MCF_TIMER_DTCN3 (*(vuint32*)(void*)(&__IPSBAR[0x0004CC])) -#define MCF_TIMER_DTMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000400+((x)*0x040)])) -#define MCF_TIMER_DTXMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000402+((x)*0x040)])) -#define MCF_TIMER_DTER(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000403+((x)*0x040)])) -#define MCF_TIMER_DTRR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000404+((x)*0x040)])) -#define MCF_TIMER_DTCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000408+((x)*0x040)])) -#define MCF_TIMER_DTCN(x) (*(vuint32*)(void*)(&__IPSBAR[0x00040C+((x)*0x040)])) - -/* Bit definitions and macros for MCF_TIMER_DTMR */ -#define MCF_TIMER_DTMR_RST (0x0001) -#define MCF_TIMER_DTMR_CLK(x) (((x)&0x0003)<<1) -#define MCF_TIMER_DTMR_FRR (0x0008) -#define MCF_TIMER_DTMR_ORRI (0x0010) -#define MCF_TIMER_DTMR_OM (0x0020) -#define MCF_TIMER_DTMR_CE(x) (((x)&0x0003)<<6) -#define MCF_TIMER_DTMR_PS(x) (((x)&0x00FF)<<8) -#define MCF_TIMER_DTMR_CE_ANY (0x00C0) -#define MCF_TIMER_DTMR_CE_FALL (0x0080) -#define MCF_TIMER_DTMR_CE_RISE (0x0040) -#define MCF_TIMER_DTMR_CE_NONE (0x0000) -#define MCF_TIMER_DTMR_CLK_DTIN (0x0006) -#define MCF_TIMER_DTMR_CLK_DIV16 (0x0004) -#define MCF_TIMER_DTMR_CLK_DIV1 (0x0002) -#define MCF_TIMER_DTMR_CLK_STOP (0x0000) - -/* Bit definitions and macros for MCF_TIMER_DTXMR */ -#define MCF_TIMER_DTXMR_MODE16 (0x01) -#define MCF_TIMER_DTXMR_DMAEN (0x80) - -/* Bit definitions and macros for MCF_TIMER_DTER */ -#define MCF_TIMER_DTER_CAP (0x01) -#define MCF_TIMER_DTER_REF (0x02) - -/********************************************************************/ - -#endif /* __MCF523X_TIMER_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_uart.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_uart.h deleted file mode 100644 index c84b02c3b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_uart.h +++ /dev/null @@ -1,193 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_uart.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_UART_H__ -#define __MCF523X_UART_H__ - -/********************************************************************* -* -* Universal Asynchronous Receiver Transmitter (UART) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_UART_UMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000200])) -#define MCF_UART_USR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204])) -#define MCF_UART_UCSR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204])) -#define MCF_UART_UCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000208])) -#define MCF_UART_URB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C])) -#define MCF_UART_UTB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C])) -#define MCF_UART_UIPCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210])) -#define MCF_UART_UACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210])) -#define MCF_UART_UISR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214])) -#define MCF_UART_UIMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214])) -#define MCF_UART_UBG10 (*(vuint8 *)(void*)(&__IPSBAR[0x000218])) -#define MCF_UART_UBG20 (*(vuint8 *)(void*)(&__IPSBAR[0x00021C])) -#define MCF_UART_UIP0 (*(vuint8 *)(void*)(&__IPSBAR[0x000234])) -#define MCF_UART_UOP10 (*(vuint8 *)(void*)(&__IPSBAR[0x000238])) -#define MCF_UART_UOP00 (*(vuint8 *)(void*)(&__IPSBAR[0x00023C])) -#define MCF_UART_UMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000240])) -#define MCF_UART_USR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244])) -#define MCF_UART_UCSR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244])) -#define MCF_UART_UCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000248])) -#define MCF_UART_URB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C])) -#define MCF_UART_UTB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C])) -#define MCF_UART_UIPCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250])) -#define MCF_UART_UACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250])) -#define MCF_UART_UISR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254])) -#define MCF_UART_UIMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254])) -#define MCF_UART_UBG11 (*(vuint8 *)(void*)(&__IPSBAR[0x000258])) -#define MCF_UART_UBG21 (*(vuint8 *)(void*)(&__IPSBAR[0x00025C])) -#define MCF_UART_UIP1 (*(vuint8 *)(void*)(&__IPSBAR[0x000274])) -#define MCF_UART_UOP11 (*(vuint8 *)(void*)(&__IPSBAR[0x000278])) -#define MCF_UART_UOP01 (*(vuint8 *)(void*)(&__IPSBAR[0x00027C])) -#define MCF_UART_UMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000280])) -#define MCF_UART_USR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284])) -#define MCF_UART_UCSR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284])) -#define MCF_UART_UCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000288])) -#define MCF_UART_URB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C])) -#define MCF_UART_UTB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C])) -#define MCF_UART_UIPCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290])) -#define MCF_UART_UACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290])) -#define MCF_UART_UISR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294])) -#define MCF_UART_UIMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294])) -#define MCF_UART_UBG12 (*(vuint8 *)(void*)(&__IPSBAR[0x000298])) -#define MCF_UART_UBG22 (*(vuint8 *)(void*)(&__IPSBAR[0x00029C])) -#define MCF_UART_UIP2 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B4])) -#define MCF_UART_UOP12 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B8])) -#define MCF_UART_UOP02 (*(vuint8 *)(void*)(&__IPSBAR[0x0002BC])) -#define MCF_UART_UMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000200+((x)*0x040)])) -#define MCF_UART_USR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)])) -#define MCF_UART_UCSR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)])) -#define MCF_UART_UCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000208+((x)*0x040)])) -#define MCF_UART_URB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)])) -#define MCF_UART_UTB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)])) -#define MCF_UART_UIPCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)])) -#define MCF_UART_UACR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)])) -#define MCF_UART_UISR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)])) -#define MCF_UART_UIMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)])) -#define MCF_UART_UBG1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000218+((x)*0x040)])) -#define MCF_UART_UBG2(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00021C+((x)*0x040)])) -#define MCF_UART_UIP(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000234+((x)*0x040)])) -#define MCF_UART_UOP1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000238+((x)*0x040)])) -#define MCF_UART_UOP0(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00023C+((x)*0x040)])) - -/* Bit definitions and macros for MCF_UART_UMR */ -#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) -#define MCF_UART_UMR_PT (0x04) -#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) -#define MCF_UART_UMR_ERR (0x20) -#define MCF_UART_UMR_RXIRQ (0x40) -#define MCF_UART_UMR_RXRTS (0x80) -#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) -#define MCF_UART_UMR_TXCTS (0x10) -#define MCF_UART_UMR_TXRTS (0x20) -#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) -#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) -#define MCF_UART_UMR_PM_MULTI_DATA (0x18) -#define MCF_UART_UMR_PM_NONE (0x10) -#define MCF_UART_UMR_PM_FORCE_HI (0x0C) -#define MCF_UART_UMR_PM_FORCE_LO (0x08) -#define MCF_UART_UMR_PM_ODD (0x04) -#define MCF_UART_UMR_PM_EVEN (0x00) -#define MCF_UART_UMR_BC_5 (0x00) -#define MCF_UART_UMR_BC_6 (0x01) -#define MCF_UART_UMR_BC_7 (0x02) -#define MCF_UART_UMR_BC_8 (0x03) -#define MCF_UART_UMR_CM_NORMAL (0x00) -#define MCF_UART_UMR_CM_ECHO (0x40) -#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) -#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) -#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) -#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) -#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) - -/* Bit definitions and macros for MCF_UART_USR */ -#define MCF_UART_USR_RXRDY (0x01) -#define MCF_UART_USR_FFULL (0x02) -#define MCF_UART_USR_TXRDY (0x04) -#define MCF_UART_USR_TXEMP (0x08) -#define MCF_UART_USR_OE (0x10) -#define MCF_UART_USR_PE (0x20) -#define MCF_UART_USR_FE (0x40) -#define MCF_UART_USR_RB (0x80) - -/* Bit definitions and macros for MCF_UART_UCSR */ -#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) -#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) -#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) -#define MCF_UART_UCSR_RCS_CTM16 (0xE0) -#define MCF_UART_UCSR_RCS_CTM (0xF0) -#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) -#define MCF_UART_UCSR_TCS_CTM16 (0x0E) -#define MCF_UART_UCSR_TCS_CTM (0x0F) - -/* Bit definitions and macros for MCF_UART_UCR */ -#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) -#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) -#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) -#define MCF_UART_UCR_NONE (0x00) -#define MCF_UART_UCR_STOP_BREAK (0x70) -#define MCF_UART_UCR_START_BREAK (0x60) -#define MCF_UART_UCR_BKCHGINT (0x50) -#define MCF_UART_UCR_RESET_ERROR (0x40) -#define MCF_UART_UCR_RESET_TX (0x30) -#define MCF_UART_UCR_RESET_RX (0x20) -#define MCF_UART_UCR_RESET_MR (0x10) -#define MCF_UART_UCR_TX_DISABLED (0x08) -#define MCF_UART_UCR_TX_ENABLED (0x04) -#define MCF_UART_UCR_RX_DISABLED (0x02) -#define MCF_UART_UCR_RX_ENABLED (0x01) - -/* Bit definitions and macros for MCF_UART_UIPCR */ -#define MCF_UART_UIPCR_CTS (0x01) -#define MCF_UART_UIPCR_COS (0x10) - -/* Bit definitions and macros for MCF_UART_UACR */ -#define MCF_UART_UACR_IEC (0x01) - -/* Bit definitions and macros for MCF_UART_UISR */ -#define MCF_UART_UISR_TXRDY (0x01) -#define MCF_UART_UISR_RXRDY_FU (0x02) -#define MCF_UART_UISR_DB (0x04) -#define MCF_UART_UISR_RXFTO (0x08) -#define MCF_UART_UISR_TXFIFO (0x10) -#define MCF_UART_UISR_RXFIFO (0x20) -#define MCF_UART_UISR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIMR */ -#define MCF_UART_UIMR_TXRDY (0x01) -#define MCF_UART_UIMR_RXRDY_FU (0x02) -#define MCF_UART_UIMR_DB (0x04) -#define MCF_UART_UIMR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIP */ -#define MCF_UART_UIP_CTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP1 */ -#define MCF_UART_UOP1_RTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP0 */ -#define MCF_UART_UOP0_RTS (0x01) - -/********************************************************************/ - -#endif /* __MCF523X_UART_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_vars.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_vars.h deleted file mode 100644 index 9608e63dd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_vars.h +++ /dev/null @@ -1,48 +0,0 @@ -/************************************************************************** - * FILE NAME: mcf523x_vars.h,v $ COPYRIGHT (c) Freescale 2004 * - * DESCRIPTION: All Rights Reserved * - * Variables that define some features of the MCF523x. * - * !!!!This file must only be included once in every project!!!! * - *========================================================================* - * ORIGINAL AUTHOR: Geoff Emerson [r47354] * - - **************************************************************************/ - -/* eTPU characteristics definition */ -struct eTPU_struct *eTPU = ( struct eTPU_struct * )0x401D0000; - -uint32_t fs_etpu_code_start = 0x401E0000; -uint32_t fs_etpu_data_ram_start = 0x401D8000; -uint32_t fs_etpu_data_ram_end = 0x401D85FC; -uint32_t fs_etpu_data_ram_ext = 0x401DC000; - -/********************************************************************* - * - * Copyright: - * Freescale Semiconductor, INC. All Rights Reserved. - * You are hereby granted a copyright license to use, modify, and - * distribute the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Freescale - * Semiconductor, Inc. This software is provided on an "AS IS" - * basis and without warranty. - * - * To the maximum extent permitted by applicable law, Freescale - * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, - * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A - * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH - * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) - * AND ANY ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, - * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER - * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Freescale Semiconductor assumes no responsibility for the - * maintenance and support of this software - * - ********************************************************************/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_wtm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_wtm.h deleted file mode 100644 index f221322d8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf523x_wtm.h +++ /dev/null @@ -1,100 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf523x_wtm.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - - -#ifndef __MCF523X_WTM_H__ -#define __MCF523X_WTM_H__ - -/********************************************************************* -* -* Watchdog Timer Modules (WTM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_WTM_WCR (*(vuint16*)(void*)(&__IPSBAR[0x140000])) -#define MCF_WTM_WMR (*(vuint16*)(void*)(&__IPSBAR[0x140002])) -#define MCF_WTM_WCNTR (*(vuint16*)(void*)(&__IPSBAR[0x140004])) -#define MCF_WTM_WSR (*(vuint16*)(void*)(&__IPSBAR[0x140006])) - -/* Bit definitions and macros for MCF_WTM_WCR */ -#define MCF_WTM_WCR_EN (0x0001) -#define MCF_WTM_WCR_HALTED (0x0002) -#define MCF_WTM_WCR_DOZE (0x0004) -#define MCF_WTM_WCR_WAIT (0x0008) - -/* Bit definitions and macros for MCF_WTM_WMR */ -#define MCF_WTM_WMR_WM0 (0x0001) -#define MCF_WTM_WMR_WM1 (0x0002) -#define MCF_WTM_WMR_WM2 (0x0004) -#define MCF_WTM_WMR_WM3 (0x0008) -#define MCF_WTM_WMR_WM4 (0x0010) -#define MCF_WTM_WMR_WM5 (0x0020) -#define MCF_WTM_WMR_WM6 (0x0040) -#define MCF_WTM_WMR_WM7 (0x0080) -#define MCF_WTM_WMR_WM8 (0x0100) -#define MCF_WTM_WMR_WM9 (0x0200) -#define MCF_WTM_WMR_WM10 (0x0400) -#define MCF_WTM_WMR_WM11 (0x0800) -#define MCF_WTM_WMR_WM12 (0x1000) -#define MCF_WTM_WMR_WM13 (0x2000) -#define MCF_WTM_WMR_WM14 (0x4000) -#define MCF_WTM_WMR_WM15 (0x8000) - -/* Bit definitions and macros for MCF_WTM_WCNTR */ -#define MCF_WTM_WCNTR_WC0 (0x0001) -#define MCF_WTM_WCNTR_WC1 (0x0002) -#define MCF_WTM_WCNTR_WC2 (0x0004) -#define MCF_WTM_WCNTR_WC3 (0x0008) -#define MCF_WTM_WCNTR_WC4 (0x0010) -#define MCF_WTM_WCNTR_WC5 (0x0020) -#define MCF_WTM_WCNTR_WC6 (0x0040) -#define MCF_WTM_WCNTR_WC7 (0x0080) -#define MCF_WTM_WCNTR_WC8 (0x0100) -#define MCF_WTM_WCNTR_WC9 (0x0200) -#define MCF_WTM_WCNTR_WC10 (0x0400) -#define MCF_WTM_WCNTR_WC11 (0x0800) -#define MCF_WTM_WCNTR_WC12 (0x1000) -#define MCF_WTM_WCNTR_WC13 (0x2000) -#define MCF_WTM_WCNTR_WC14 (0x4000) -#define MCF_WTM_WCNTR_WC15 (0x8000) - -/* Bit definitions and macros for MCF_WTM_WSR */ -#define MCF_WTM_WSR_WS0 (0x0001) -#define MCF_WTM_WSR_WS1 (0x0002) -#define MCF_WTM_WSR_WS2 (0x0004) -#define MCF_WTM_WSR_WS3 (0x0008) -#define MCF_WTM_WSR_WS4 (0x0010) -#define MCF_WTM_WSR_WS5 (0x0020) -#define MCF_WTM_WSR_WS6 (0x0040) -#define MCF_WTM_WSR_WS7 (0x0080) -#define MCF_WTM_WSR_WS8 (0x0100) -#define MCF_WTM_WSR_WS9 (0x0200) -#define MCF_WTM_WSR_WS10 (0x0400) -#define MCF_WTM_WSR_WS11 (0x0800) -#define MCF_WTM_WSR_WS12 (0x1000) -#define MCF_WTM_WSR_WS13 (0x2000) -#define MCF_WTM_WSR_WS14 (0x4000) -#define MCF_WTM_WSR_WS15 (0x8000) - -/********************************************************************/ - -#endif /* __MCF523X_WTM_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf5xxx.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf5xxx.h deleted file mode 100644 index 2a7d199f0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/mcf5xxx.h +++ /dev/null @@ -1,203 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 metrowerks inc. All rights reserved. * - * * - * * - * $RCSfile: mcf5xxx.h,v $ * - * $Revision$ * - * $Date$ * - * * - * DESCRIPTION * - * Definitions common to all ColdFire processors. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef _CPU_MCF5XXX_H -#define _CPU_MCF5XXX_H - -/***********************************************************************/ -/* - * Misc. Defines - */ - -#ifdef FALSE -#undef FALSE -#endif -#define FALSE (0) - -#ifdef TRUE -#undef TRUE -#endif -#define TRUE (1) - -#ifdef NULL -#undef NULL -#endif -#define NULL (0) - -/***********************************************************************/ -/* - * The basic data types - */ - -typedef unsigned char uint8; /* 8 bits */ -typedef unsigned short int uint16; /* 16 bits */ -typedef unsigned long int uint32; /* 32 bits */ - -typedef signed char int8; /* 8 bits */ -typedef signed short int int16; /* 16 bits */ -typedef signed long int int32; /* 32 bits */ - -typedef volatile uint8 vuint8; /* 8 bits */ -typedef volatile uint16 vuint16; /* 16 bits */ -typedef volatile uint32 vuint32; /* 32 bits */ - -/***********************************************************************/ -/* - * Common M68K & ColdFire definitions - */ - -#define ADDRESS uint32 -#define INSTRUCTION uint16 -#define ILLEGAL 0x4AFC -#define CPU_WORD_SIZE 16 - -#define MCF5XXX_SR_T (0x8000) -#define MCF5XXX_SR_S (0x2000) -#define MCF5XXX_SR_M (0x1000) -#define MCF5XXX_SR_IPL (0x0700) -#define MCF5XXX_SR_IPL_0 (0x0000) -#define MCF5XXX_SR_IPL_1 (0x0100) -#define MCF5XXX_SR_IPL_2 (0x0200) -#define MCF5XXX_SR_IPL_3 (0x0300) -#define MCF5XXX_SR_IPL_4 (0x0400) -#define MCF5XXX_SR_IPL_5 (0x0500) -#define MCF5XXX_SR_IPL_6 (0x0600) -#define MCF5XXX_SR_IPL_7 (0x0700) -#define MCF5XXX_SR_X (0x0010) -#define MCF5XXX_SR_N (0x0008) -#define MCF5XXX_SR_Z (0x0004) -#define MCF5XXX_SR_V (0x0002) -#define MCF5XXX_SR_C (0x0001) - -#define MCF5XXX_CACR_CENB (0x80000000) -#define MCF5XXX_CACR_CPDI (0x10000000) -#define MCF5XXX_CACR_CPD (0x10000000) -#define MCF5XXX_CACR_CFRZ (0x08000000) -#define MCF5XXX_CACR_CINV (0x01000000) -#define MCF5XXX_CACR_DIDI (0x00800000) -#define MCF5XXX_CACR_DISD (0x00400000) -#define MCF5XXX_CACR_INVI (0x00200000) -#define MCF5XXX_CACR_INVD (0x00100000) -#define MCF5XXX_CACR_CEIB (0x00000400) -#define MCF5XXX_CACR_DCM_WR (0x00000000) -#define MCF5XXX_CACR_DCM_CB (0x00000100) -#define MCF5XXX_CACR_DCM_IP (0x00000200) -#define MCF5XXX_CACR_DCM (0x00000200) -#define MCF5XXX_CACR_DCM_II (0x00000300) -#define MCF5XXX_CACR_DBWE (0x00000100) -#define MCF5XXX_CACR_DWP (0x00000020) -#define MCF5XXX_CACR_EUST (0x00000010) -#define MCF5XXX_CACR_CLNF_00 (0x00000000) -#define MCF5XXX_CACR_CLNF_01 (0x00000002) -#define MCF5XXX_CACR_CLNF_10 (0x00000004) -#define MCF5XXX_CACR_CLNF_11 (0x00000006) - -#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000) -#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8) -#define MCF5XXX_ACR_EN (0x00008000) -#define MCF5XXX_ACR_SM_USER (0x00000000) -#define MCF5XXX_ACR_SM_SUPER (0x00002000) -#define MCF5XXX_ACR_SM_IGNORE (0x00006000) -#define MCF5XXX_ACR_ENIB (0x00000080) -#define MCF5XXX_ACR_CM (0x00000040) -#define MCF5XXX_ACR_DCM_WR (0x00000000) -#define MCF5XXX_ACR_DCM_CB (0x00000020) -#define MCF5XXX_ACR_DCM_IP (0x00000040) -#define MCF5XXX_ACR_DCM_II (0x00000060) -#define MCF5XXX_ACR_CM (0x00000040) -#define MCF5XXX_ACR_BWE (0x00000020) -#define MCF5XXX_ACR_WP (0x00000004) - -#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000) -#define MCF5XXX_RAMBAR_PRI_00 (0x00000000) -#define MCF5XXX_RAMBAR_PRI_01 (0x00004000) -#define MCF5XXX_RAMBAR_PRI_10 (0x00008000) -#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000) -#define MCF5XXX_RAMBAR_WP (0x00000100) -#define MCF5XXX_RAMBAR_CI (0x00000020) -#define MCF5XXX_RAMBAR_SC (0x00000010) -#define MCF5XXX_RAMBAR_SD (0x00000008) -#define MCF5XXX_RAMBAR_UC (0x00000004) -#define MCF5XXX_RAMBAR_UD (0x00000002) -#define MCF5XXX_RAMBAR_V (0x00000001) - -/***********************************************************************/ -/* - * The ColdFire family of processors has a simplified exception stack - * frame that looks like the following: - * - * 3322222222221111 111111 - * 1098765432109876 5432109876543210 - * 8 +----------------+----------------+ - * | Program Counter | - * 4 +----------------+----------------+ - * |FS/Fmt/Vector/FS| SR | - * SP --> 0 +----------------+----------------+ - * - * The stack self-aligns to a 4-byte boundary at an exception, with - * the FS/Fmt/Vector/FS field indicating the size of the adjustment - * (SP += 0,1,2,3 bytes). - */ - -#define MCF5XXX_RD_SF_FORMAT(PTR) \ - ((*((uint16 *)(PTR)) >> 12) & 0x00FF) - -#define MCF5XXX_RD_SF_VECTOR(PTR) \ - ((*((uint16 *)(PTR)) >> 2) & 0x00FF) - -#define MCF5XXX_RD_SF_FS(PTR) \ - ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) ) - -#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1) -#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1) - -/********************************************************************/ -/* - * Functions provided by mcf5xxx.s - */ - -int asm_set_ipl( uint32 ); -void mcf5xxx_wr_cacr( uint32 ); -void mcf5xxx_wr_acr0( uint32 ); -void mcf5xxx_wr_acr1( uint32 ); -void mcf5xxx_wr_acr2( uint32 ); -void mcf5xxx_wr_acr3( uint32 ); -void mcf5xxx_wr_other_a7( uint32 ); -void mcf5xxx_wr_other_sp( uint32 ); -void mcf5xxx_wr_vbr( uint32 ); -void mcf5xxx_wr_macsr( uint32 ); -void mcf5xxx_wr_mask( uint32 ); -void mcf5xxx_wr_acc0( uint32 ); -void mcf5xxx_wr_accext01( uint32 ); -void mcf5xxx_wr_accext23( uint32 ); -void mcf5xxx_wr_acc1( uint32 ); -void mcf5xxx_wr_acc2( uint32 ); -void mcf5xxx_wr_acc3( uint32 ); -void mcf5xxx_wr_sr( uint32 ); -void mcf5xxx_wr_rambar0( uint32 ); -void mcf5xxx_wr_rambar1( uint32 ); -void mcf5xxx_wr_mbar( uint32 ); -void mcf5xxx_wr_mbar0( uint32 ); -void mcf5xxx_wr_mbar1( uint32 ); - -/********************************************************************/ - -#endif /* _CPU_MCF5XXX_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/typedefs.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/typedefs.h deleted file mode 100644 index 8bb64e45b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/mcf523x/typedefs.h +++ /dev/null @@ -1,113 +0,0 @@ -/************************************************************************** - * FILE NAME: $RCSfile: typedefs.h,v $ COPYRIGHT (c) Freescale 2004 * - * DESCRIPTION: All Rights Reserved * - * This file defines all of the data types for the Motorola header file. * - *========================================================================* - * ORIGINAL AUTHOR: Jeff Loeliger (r12110) * - * $Log: typedefs.h,v $ - * Revision 1.1 2006/05/14 21:59:16 wolti - * - initial version of MCF5235 port - * - * Revision 1.1.1.1 2005/05/26 17:07:05 C-machim - * CF 6.0 Stationeries - * - * Revision 1.2 2004/11/17 12:43:12 r12110 - * -Removed #ifdef DEBUG from around initial comment block. - * - * Revision 1.1 2004/11/17 12:38:48 r12110 - * -Initial version checked into CVS. - * -Updated copyright from Motorola to Freescale. - * - *........................................................................* - * 0.1 J. Loeliger 17/Feb/03 Initial version of file. * - * 0.2 J. Loeliger 06/Mar/03 Added DCC support. * - * 0.3 J. Loeliger 07/May/03 Change to fully use ISO data types. * - * 0.4 J. Loeliger 17/Jun/03 Change name to motint.h and merge * - * MPC5500 and MAC7100 files. * - * 0.5 J. Loeliger 04/Nov/03 Changed name to typedefs.h. * - * 0.6 J. Loeliger 09/May/04 Changed to support GHS and GCC. * - **************************************************************************/ - -#ifndef _TYPEDEFS_H_ -#define _TYPEDEFS_H_ - -#ifdef __MWERKS__ //Metrowerk CodeWarrior -#include - - // Standard typedefs used by header files, based on ISO C standard -typedef volatile int8_t vint8_t; -typedef volatile uint8_t vuint8_t; - -typedef volatile int16_t vint16_t; -typedef volatile uint16_t vuint16_t; - -typedef volatile int32_t vint32_t; -typedef volatile uint32_t vuint32_t; - -#else -#ifdef __GHS__ //GreenHills -#include - - // Standard typedefs used by header files, based on ISO C standard -typedef volatile int8_t vint8_t; -typedef volatile uint8_t vuint8_t; - -typedef volatile int16_t vint16_t; -typedef volatile uint16_t vuint16_t; - -typedef volatile int32_t vint32_t; -typedef volatile uint32_t vuint32_t; - -#else - - // This is needed for compilers that don't have a stdint.h file - -typedef signed char int8_t; -typedef unsigned char uint8_t; -typedef volatile signed char vint8_t; -typedef volatile unsigned char vuint8_t; - -typedef signed short int16_t; -typedef unsigned short uint16_t; -typedef volatile signed short vint16_t; -typedef volatile unsigned short vuint16_t; - -typedef signed int int32_t; -typedef unsigned int uint32_t; -typedef volatile signed int vint32_t; -typedef volatile unsigned int vuint32_t; - -#endif -#endif -#endif - -/********************************************************************* - * - * Copyright: - * Freescale Semiconductor, INC. All Rights Reserved. - * You are hereby granted a copyright license to use, modify, and - * distribute the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Freescale - * Semiconductor, Inc. This software is provided on an "AS IS" - * basis and without warranty. - * - * To the maximum extent permitted by applicable law, Freescale - * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, - * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A - * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH - * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) - * AND ANY ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, - * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER - * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Freescale Semiconductor assumes no responsibility for the - * maintenance and support of this software - * - ********************************************************************/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/port/port.h deleted file mode 100644 index a01e5b82c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/port/port.h +++ /dev/null @@ -1,57 +0,0 @@ - /* - * FreeModbus Libary: MCF5235 Port - * Copyright (C) 2006 Christian Walter - * Parts of crt0.S Copyright (c) 1995, 1996, 1998 Cygnus Support - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -#define INLINE inline -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#define ENTER_CRITICAL_SECTION( ) prvvPortEnterCritical() -#define EXIT_CRITICAL_SECTION( ) prvvPortExitCritical() - -#define assert( x ) - -inline void prvvPortEnterCritical( ); -inline void prvvPortExitCritical( ); - -typedef char BOOL; - -typedef unsigned char UCHAR; -typedef char CHAR; - -typedef unsigned short USHORT; -typedef short SHORT; - -typedef unsigned long ULONG; -typedef long LONG; - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/port/portevent.c deleted file mode 100644 index 963269a2c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/port/portevent.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * FreeModbus Libary: MCF5235 Port - * Copyright (C) 2006 Christian Walter - * Parts of crt0.S Copyright (c) 1995, 1996, 1998 Cygnus Support - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static eMBEventType eQueuedEvent; -static BOOL xEventInQueue; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - xEventInQueue = FALSE; - return TRUE; -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - xEventInQueue = TRUE; - eQueuedEvent = eEvent; - return TRUE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - BOOL xEventHappened = FALSE; - - if( xEventInQueue ) - { - *eEvent = eQueuedEvent; - xEventInQueue = FALSE; - xEventHappened = TRUE; - } - return xEventHappened; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/port/portother.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/port/portother.c deleted file mode 100644 index f92f14083..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/port/portother.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * FreeModbus Libary: MCF5235 Port - * Copyright (C) 2006 Christian Walter - * Parts of crt0.S Copyright (c) 1995, 1996, 1998 Cygnus Support - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "port.h" -#include "mcf5xxx.h" -#include "mcf523x.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegSR; -static char *heap_ptr; - -/* ----------------------- Start implementation -----------------------------*/ -void -prvvPortEnterCritical( ) -{ - asm volatile ( "move.w %%sr, %%d0\n" - "move.w %%d0, %0\n" - "move.w #0x2700, %%sr":"=m" ( usRegSR )::"%%d0" ); -} - -void -prvvPortExitCritical( ) -{ - asm volatile ( "move.w %0, %%d0\n" - "move.w %%d0, %%sr\n"::"m" ( usRegSR ):"%%d0" ); -} - - -char * -sbrk( int nbytes ) -{ - extern void _end; - char *base; - - if( !heap_ptr ) - heap_ptr = ( char * )&_end; - base = heap_ptr; - heap_ptr += nbytes; - return base; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/port/portserial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/port/portserial.c deleted file mode 100644 index 5a0bd7264..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/port/portserial.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * FreeModbus Libary: MCF5235 Port - * Copyright (C) 2006 Christian Walter - * Parts of crt0.S Copyright (c) 1995, 1996, 1998 Cygnus Support - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes --------------------------------- */ -#include "port.h" -#include "mcf5xxx.h" -#include "mcf523x.h" - -/* ----------------------- Modbus includes --------------------------------- */ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ----------------------------------------- */ -#define BAUDRATE_VALUE(fsys, baud) ( ( fsys )/(32UL * baud) ) - -/* ----------------------- Static variables -------------------------------- */ -BOOL bTXEnabled; -BOOL bRXEnabled; - -/* ----------------------- Start implementation ---------------------------- */ - -void -vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable ) -{ - UCHAR ucUCR = 0; - UCHAR ucIMR = 0; - - if( xRxEnable ) - { - ucUCR |= MCF_UART_UCR_RXC( 0x1 ); - ucIMR |= MCF_UART_UIMR_RXRDY_FU; - bRXEnabled = TRUE; - } - else - { - ucUCR |= MCF_UART_UCR_RXC( 0x2 ); - bRXEnabled = FALSE; - } - if( xTxEnable ) - { - ucUCR |= MCF_UART_UCR_TXC( 0x1 ); - ucIMR |= MCF_UART_UIMR_TXRDY; - bTXEnabled = TRUE; - } - else - { - ucUCR |= MCF_UART_UCR_TXC( 0x2 ); - bTXEnabled = FALSE; - } - MCF_UART_UCR0 = ucUCR; - MCF_UART_UIMR0 = ucIMR; -} - -BOOL -xMBPortSerialInit( UCHAR ucPort, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity ) -{ - BOOL bStatus = TRUE; - UCHAR ucMode = 0; - - (void)ucPort; - - switch ( eParity ) - { - case MB_PAR_EVEN: - ucMode |= MCF_UART_UMR_PM( 0x0 ); - break; - case MB_PAR_ODD: - ucMode |= MCF_UART_UMR_PM( 0x0 ) | MCF_UART_UMR_PT; - break; - case MB_PAR_NONE: - ucMode |= MCF_UART_UMR_PM( 0x3 ); - break; - default: - bStatus = FALSE; - } - - switch ( ucDataBits ) - { - case 8: - ucMode |= MCF_UART_UMR_BC( 0x3 ); - break; - case 7: - ucMode |= MCF_UART_UMR_BC( 0x2 ); - break; - default: - bStatus = FALSE; - } - if( bStatus == TRUE ) - { - /* UART 0: Reset transmitter, receiver and mode register pointer */ - MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x3 ); - MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x2 ); - MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x1 ); - - /* UART 0: Configure parity, databits and stopbits. */ - MCF_UART_UMR0 = ucMode; - MCF_UART_UMR0 = MCF_UART_UMR_SB( 0x7 ); - - /* UART 0 Clocking */ - MCF_UART_UCSR0 = MCF_UART_UCSR_RCS( 0xd ) | MCF_UART_UCSR_TCS( 0xd ); - MCF_UART_UBG10 = BAUDRATE_VALUE( FCPU, ulBaudRate ) >> 8U; - MCF_UART_UBG20 = BAUDRATE_VALUE( FCPU, ulBaudRate ) & 0xFFU; - - /* UART 0: Enable interrupts */ - MCF_INTC0_ICR13 = MCF_INTC0_ICRn_IL( 0x1 ) | MCF_INTC0_ICRn_IP( 0x1 ); - MCF_INTC0_IMRL &= ~MCF_INTC0_IMRL_INT_MASK13; - - /* UART 0 Miscellaneous */ - MCF_UART_UACR0 = 0; - - /* UART 0: Enable pins */ - MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_U0RXD | - MCF_GPIO_PAR_UART_PAR_U0TXD; - vMBPortSerialEnable( FALSE, FALSE ); - } - - return TRUE; -} - -BOOL -xMBPortSerialPutByte( CHAR ucByte ) -{ - MCF_UART_UTB0 = ucByte; - return TRUE; -} - -BOOL -xMBPortSerialGetByte( CHAR * pucByte ) -{ - *pucByte = MCF_UART_URB0; - return TRUE; -} - -void -prvvMBPortSerialISR( ) -{ - if( bTXEnabled && ( MCF_UART_UISR0 & MCF_UART_UISR_TXRDY ) ) - { - ( void )pxMBFrameCBTransmitterEmpty( ); - } - if( bRXEnabled && ( MCF_UART_UISR0 & MCF_UART_UISR_RXRDY_FU ) ) - { - ( void )pxMBFrameCBByteReceived( ); - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/port/porttimer.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/port/porttimer.c deleted file mode 100644 index b09e81996..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/port/porttimer.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * FreeModbus Libary: MCF5235 Port - * Copyright (C) 2006 Christian Walter - * Parts of crt0.S Copyright (c) 1995, 1996, 1998 Cygnus Support - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes --------------------------------- */ -#include "port.h" -#include "mcf5xxx.h" -#include "mcf523x.h" - -/* ----------------------- Modbus includes --------------------------------- */ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ----------------------------------------- */ -#define PIT_PRESCALER 1024UL -#define PIT_TIMER_TICKS ( FCPU / PIT_PRESCALER ) -#define PIT_MODULUS_REGISTER(t50us) \ - ( (t50us * PIT_TIMER_TICKS )/20000UL - 1UL) - -/* ----------------------- Static variables -------------------------------- */ -USHORT usTimerModulus; - -/* ----------------------- Start implementation ---------------------------- */ - -BOOL -xMBPortTimersInit( USHORT usTim1Timerout50us ) -{ - usTimerModulus = PIT_MODULUS_REGISTER( usTim1Timerout50us ); - /* Configure prescaler */ - MCF_PIT_PCSR0 = MCF_PIT_PCSR_PRE( 0x9 ) | MCF_PIT_PCSR_OVW; - /* Configure interrupt priority and level */ - MCF_INTC0_ICR36 = MCF_INTC0_ICRn_IL( 0x1 ) | MCF_INTC0_ICRn_IP( 0x2 ); - /* Unmask interrupt */ - MCF_INTC0_IMRH &= ~MCF_INTC0_IMRH_INT_MASK36; - - return TRUE; -} - -inline void -vMBPortTimersEnable( ) -{ - MCF_PIT_PMR0 = usTimerModulus; - MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_EN | MCF_PIT_PCSR_PIF; -} - -inline void -vMBPortTimersDisable( ) -{ - MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF; - MCF_PIT_PCSR0 &= ~MCF_PIT_PCSR_PIE; - MCF_PIT_PCSR0 &= ~MCF_PIT_PCSR_EN; -} - -void -prvvMBPortTimerISR( ) -{ - ( void )pxMBPortCBTimerExpired( ); - MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/support/AM29_160BB.CFP b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/support/AM29_160BB.CFP deleted file mode 100644 index 403603932..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/support/AM29_160BB.CFP +++ /dev/null @@ -1,57 +0,0 @@ -;version 1.00, 01/14/2005, Copyright P&E Microcomputer Systems, www.pemicro.com -;device AMD, 29F160D-B, 1x16x1meg -;device AMD, 29LV160B-B, 1x16x1meg -;device AMD, 29LV160D-B, 1x16x1meg -;device Alliance, 29LV160-B, 1x16x1meg -;device Fujitsu, 29F160E-B, 1x16x1meg -;device Fujitsu, 29LV160-B, 1x16x1meg -;device Hyundai, 29LV160-B, 1x16x1meg -;device MXIC, 29LV160-B, 1x16x1meg -;device MXIC, 29LV160A-B, 1x16x1meg -;device MXIC, 29LV160B-B, 1x16x1meg -;device MXIC, 29LV161-B, 1x16x1meg -;device ST, 29F160B-B, 1x16x1meg -;device ST, 29W160B-B, 1x16x1meg -;device ST, 29W160D-B, 1x16x1meg -;device ST, 29W160E-B, 1x16x1meg -;device Toshiba, 50VFS1481-B, 1x16x1meg -;device Toshiba, 50VFS2481-B, 1x16x1meg -;device Toshiba, 58FV160-B, 1x16x1meg -;begin_cs device=$00000000, length=$00200000, ram=$10000000 -;end_cs -NO_ON_CHIP_RAM -CONTROL=10000021/0C05/ ;ram at $10000000 -NO_TIMING_TEST -USER=BE Block Erase 2Block > /00000000/00000022/ -; -S31510000000100001F0100002100000010000000000B6 -S315100000100020000000000000100000FE000000009C -S3151000002000000000100001520000000010000190B6 -S31510000030100000EC100000EE100000F000000000B0 -S315100000400000000000000000100000D800000000B2 -S315100000500000400000006000000080000001000069 -S31510000060000200000003000000040000000500006C -S31510000070000600000007000000080000000900004C -S31510000080000A0000000B0000000C0000000D00002C -S31510000090000E0000000F000000100000001100000C -S315100000A000120000001300000014000000150000EC -S315100000B000160000001700000018000000190000CC -S315100000C0001A0000001B0000001C0000001D0000AC -S315100000D0001E0000001F0000227C1000004C207142 -S315100000E00C00D1FC00000000600000324AC84AC86B -S315100000F02A7C0000AAAA2C7C000055544AC8223C2F -S31510000100FFFFFFFF32180C81FFFFFFFF66065580C9 -S3151000011066F24AC8203CFFFFFFFF4AC83ABCAAAAAB -S315100001203CBC55553ABC80803ABCAAAA3CBC555535 -S3151000013030BC3030223CFFFFFFFF32100C81FFFF36 -S31510000140FFFF66F632100C81FFFFFFFF66EC428060 -S315100001504AC83ABCAAAA3CBC55553ABC80803ABC9F -S31510000160AAAA3CBC55553ABC1010223CFFFFFFFF13 -S315100001703239000000000C81FFFFFFFF66F23239B2 -S31510000180000000000C81FFFFFFFF66E442804AC8B2 -S31510000190287C10000210204B2403428042813ABC76 -S315100001A0AAAA3CBC55553ABCA0A0301C30C0322877 -S315100001B0FFFEB28066F83228FFFEB28066F05582E6 -S315100001C066DC287C10000210301C321BB2806608D8 -S315100001D0558366F442804AC8203CFFFFFFFF4AC899 -S804000000FB diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/support/m5235.gdb b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/support/m5235.gdb deleted file mode 100644 index fc1379b17..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/support/m5235.gdb +++ /dev/null @@ -1,67 +0,0 @@ -define setup-and-load - set $rambar=0x100001 - tbreak start - tbreak main -end - -define debug-printexception - printf "vector: %d", *(unsigned short *)$sp >> 2 &0x1F - printf "old pc: 0x%08x", *(unsigned long *)($sp + 4) - printf "old sr: 0x%02x", *(unsigned short *)($sp + 2) -end - -define execute -# set $sp = *(long *)0x20000 - set $pc = *(long *)0x100004 - tk gdbtk_update -end - -define write - set *0x1000000 = 33 -end - -define simple - write - print /x *0x1000000 -end - -define wait - set $delay = 10000 - while $delay > 0 - set $delay = $delay - 1 - end -end - -define debug-sramtest - set $srambase = 0x20000000 - set $sramsize = 0x00010000 - printf "Testing SRAM : 0x%08X - 0x%08X\n", $srambase, ($srambase + $sramsize) - set $i = $srambase - while $i < ($srambase + $sramsize) - set *(unsigned long *)($i) = 0xAA55AA55 - wait - if 0xAA55AA55 != *(unsigned long *)$i - printf " 0x%08X = FAIL\n", $i - else - printf " 0x%08X = OK\n", $i - end - set $i = $i + 0x1000 - end -end - -define debug-sdramtest - set $sdrambase = 0x00000000 - set $sdramsize = 0x01100000 - printf "Testing SDRAM : 0x%08X - 0x%08X\n", $sdrambase, ($sdrambase + $sdramsize) - set $i = $sdrambase - while $i < ($sdrambase + $sdramsize) - set *(unsigned long *)($i) = 0xAA55AA55 - wait - if 0xAA55AA55 != *(unsigned long *)$i - printf " 0x%08X = FAIL\n", $i - else - printf " 0x%08X = OK\n", $i - end - set $i = $i + 0x10000 - end -end diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/support/mcf5235.CF b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/support/mcf5235.CF deleted file mode 100644 index 4236b66bb..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/support/mcf5235.CF +++ /dev/null @@ -1,320 +0,0 @@ -ColdFire Initialisation Utility 2.7.0 -PROCESSOR = ColdFire MCF5235 Processor -INTERNAL_CS = 0x00400001, 0x00000000 -INTERNAL_MODUSE = 0x80000000, 0x00000000 -INTERNAL_CONFIG = 0x000c443f, 0x00000000 -INTERNAL_MISC = 0x05529470, 0x00000000 -INTERNAL_MISC2 = 0x00000000, 0x00000000 -VBR = 0x00000000, 0x00000000 -SR = 0x2700, 0x0000 -RAMBAR = 0x00100001, 0x00000000 -IPSBAR = 0x40000001, 0x00000000 -CCON = 0x8008, 0x0000 -SYNCR = 0x00080000, 0x00000000 -SYNSR = 0x00000000, 0x00000000 -CACR = 0x00000000, 0x00000000 -ACR0 = 0x00000000, 0x00000000 -ACR1 = 0x00000000, 0x00000000 -CSAR0 = 0x0000, 0x0000 -CSAR1 = 0x0000, 0x0000 -CSAR2 = 0x0000, 0x0000 -CSAR3 = 0x0000, 0x0000 -CSAR4 = 0x0000, 0x0000 -CSAR5 = 0x0000, 0x0000 -CSAR6 = 0x0000, 0x0000 -CSAR7 = 0x0000, 0x0000 -CSMR0 = 0x00000000, 0x00000000 -CSMR1 = 0x00000000, 0x00000000 -CSMR2 = 0x00000000, 0x00000000 -CSMR3 = 0x00000000, 0x00000000 -CSMR4 = 0x00000000, 0x00000000 -CSMR5 = 0x00000000, 0x00000000 -CSMR6 = 0x00000000, 0x00000000 -CSMR7 = 0x00000000, 0x00000000 -CSCR0 = 0x3d00, 0x0000 -CSCR1 = 0x0000, 0x0000 -CSCR2 = 0x0000, 0x0000 -CSCR3 = 0x0000, 0x0000 -CSCR4 = 0x0000, 0x0000 -CSCR5 = 0x0000, 0x0000 -CSCR6 = 0x0000, 0x0000 -CSCR7 = 0x0000, 0x0000 -DCR = 0x01ff, 0x0000 -DACR0 = 0x00000000, 0x00000000 -DACR1 = 0x00000000, 0x00000000 -DMR0 = 0x00000000, 0x00000000 -DMR1 = 0x00000000, 0x00000000 -EPPAR = 0x0000, 0x0000 -EPDDR = 0x00, 0x00 -EPIER = 0x00, 0x00 -LPICR = 0x00, 0x00 -LPCR = 0x02, 0x00 -MPARK = 0x30e10000, 0x00000000 -QMR = 0x0104, 0x0000 -QDLYR = 0x0404, 0x0000 -QWR = 0x0000, 0x0000 -QIR = 0x0000, 0x0000 -CWCR = 0x00, 0x00 -WCR = 0x000e, 0x0000 -WMR = 0xffff, 0x0000 -DTMR0 = 0x0000, 0x0000 -DTXMR0 = 0x00, 0x00 -DTRR0 = 0xffffffff, 0x00000000 -DTCN0 = 0x00000000, 0x00000000 -DTMR1 = 0x0000, 0x0000 -DTXMR1 = 0x00, 0x00 -DTRR1 = 0xffffffff, 0x00000000 -DTCN1 = 0x00000000, 0x00000000 -DTMR2 = 0x0000, 0x0000 -DTXMR2 = 0x00, 0x00 -DTRR2 = 0xffffffff, 0x00000000 -DTCN2 = 0x00000000, 0x00000000 -DTMR3 = 0x0000, 0x0000 -DTXMR3 = 0x00, 0x00 -DTRR3 = 0xffffffff, 0x00000000 -DTCN3 = 0x00000000, 0x00000000 -PCSR0 = 0x0000, 0x0000 -PMR0 = 0xffff, 0x0000 -PCSR1 = 0x0000, 0x0000 -PMR1 = 0xffff, 0x0000 -PCSR2 = 0x0000, 0x0000 -PMR2 = 0xffff, 0x0000 -PCSR3 = 0x0000, 0x0000 -PMR3 = 0xffff, 0x0000 -UMR10 = 0x03, 0x00 -UMR20 = 0x07, 0x00 -UCSR0 = 0xdd, 0x00 -UACR0 = 0x00, 0x00 -UIMR0 = 0x03, 0x00 -UDU0 = 0x00, 0x00 -UDL0 = 0x51, 0x00 -UCR0 = 0x01, 0x00 -UMR11 = 0x13, 0x00 -UMR21 = 0x07, 0x00 -UCSR1 = 0xdd, 0x00 -UACR1 = 0x00, 0x00 -UIMR1 = 0x00, 0x00 -UDU1 = 0x00, 0x00 -UDL1 = 0x00, 0x00 -UCR1 = 0x00, 0x00 -UMR12 = 0x13, 0x00 -UMR22 = 0x07, 0x00 -UCSR2 = 0xdd, 0x00 -UACR2 = 0x00, 0x00 -UIMR2 = 0x00, 0x00 -UDU2 = 0x00, 0x00 -UDL2 = 0x00, 0x00 -UCR2 = 0x00, 0x00 -EIMR0 = 0x00000000, 0x00000000 -ECR0 = 0xf0000000, 0x00000000 -RCR0 = 0x05ee0000, 0x00000000 -TCR0 = 0x00000000, 0x00000000 -FRSR0 = 0x00000500, 0x00000000 -TFWR0 = 0x00000000, 0x00000000 -PALR0 = 0x00000000, 0x00000000 -PAUR0 = 0x00008808, 0x00000000 -OPD0 = 0x00010000, 0x00000000 -GAUR0 = 0x00000000, 0x00000000 -GALR0 = 0x00000000, 0x00000000 -IAUR0 = 0x00000000, 0x00000000 -IALR0 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF0_0 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF1_0 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF2_0 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF3_0 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF4_0 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF5_0 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF6_0 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF7_0 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF8_0 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF9_0 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF10_0 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF11_0 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF12_0 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF13_0 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF14_0 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF15_0 = 0x00000000, 0x00000000 -CANMCR0 = 0xd890000f, 0x00000000 -CANCTRL0 = 0x00000000, 0x00000000 -RXGMASK0 = 0x1fffffff, 0x00000000 -RX14MASK0 = 0x1fffffff, 0x00000000 -RX15MASK0 = 0x1fffffff, 0x00000000 -IMASK0 = 0x0000, 0x0000 -INTERNAL_MSGBUFF0_1 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF1_1 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF2_1 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF3_1 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF4_1 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF5_1 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF6_1 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF7_1 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF8_1 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF9_1 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF10_1 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF11_1 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF12_1 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF13_1 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF14_1 = 0x00000000, 0x00000000 -INTERNAL_MSGBUFF15_1 = 0x00000000, 0x00000000 -CANMCR1 = 0xd890000f, 0x00000000 -CANCTRL1 = 0x00000000, 0x00000000 -RXGMASK1 = 0x1fffffff, 0x00000000 -RX14MASK1 = 0x1fffffff, 0x00000000 -RX15MASK1 = 0x1fffffff, 0x00000000 -IMASK1 = 0x0000, 0x0000 -IMRH0 = 0xffffffff, 0x00000000 -IMRH1 = 0xffffffff, 0x00000000 -IMRL0 = 0xffffdffe, 0x00000000 -IMRL1 = 0xfffffffe, 0x00000000 -ICR001 = 0x00, 0x00 -ICR002 = 0x00, 0x00 -ICR003 = 0x00, 0x00 -ICR004 = 0x00, 0x00 -ICR005 = 0x00, 0x00 -ICR006 = 0x00, 0x00 -ICR007 = 0x00, 0x00 -ICR008 = 0x00, 0x00 -ICR009 = 0x00, 0x00 -ICR010 = 0x00, 0x00 -ICR011 = 0x00, 0x00 -ICR012 = 0x00, 0x00 -ICR013 = 0x09, 0x00 -ICR014 = 0x00, 0x00 -ICR015 = 0x00, 0x00 -ICR017 = 0x00, 0x00 -ICR018 = 0x00, 0x00 -ICR019 = 0x00, 0x00 -ICR020 = 0x00, 0x00 -ICR021 = 0x00, 0x00 -ICR022 = 0x00, 0x00 -ICR023 = 0x00, 0x00 -ICR024 = 0x00, 0x00 -ICR025 = 0x00, 0x00 -ICR026 = 0x00, 0x00 -ICR027 = 0x00, 0x00 -ICR028 = 0x00, 0x00 -ICR029 = 0x00, 0x00 -ICR030 = 0x00, 0x00 -ICR031 = 0x00, 0x00 -ICR032 = 0x00, 0x00 -ICR033 = 0x00, 0x00 -ICR034 = 0x00, 0x00 -ICR035 = 0x00, 0x00 -ICR036 = 0x00, 0x00 -ICR037 = 0x00, 0x00 -ICR038 = 0x00, 0x00 -ICR039 = 0x00, 0x00 -ICR040 = 0x00, 0x00 -ICR041 = 0x00, 0x00 -ICR042 = 0x00, 0x00 -ICR043 = 0x00, 0x00 -ICR044 = 0x00, 0x00 -ICR045 = 0x00, 0x00 -ICR046 = 0x00, 0x00 -ICR047 = 0x00, 0x00 -ICR048 = 0x00, 0x00 -ICR049 = 0x00, 0x00 -ICR050 = 0x00, 0x00 -ICR051 = 0x00, 0x00 -ICR052 = 0x00, 0x00 -ICR053 = 0x00, 0x00 -ICR054 = 0x00, 0x00 -ICR055 = 0x00, 0x00 -ICR056 = 0x00, 0x00 -ICR057 = 0x00, 0x00 -ICR058 = 0x00, 0x00 -ICR059 = 0x00, 0x00 -ICR060 = 0x00, 0x00 -ICR108 = 0x00, 0x00 -ICR109 = 0x00, 0x00 -ICR110 = 0x00, 0x00 -ICR111 = 0x00, 0x00 -ICR112 = 0x00, 0x00 -ICR113 = 0x00, 0x00 -ICR114 = 0x00, 0x00 -ICR115 = 0x00, 0x00 -ICR116 = 0x00, 0x00 -ICR117 = 0x00, 0x00 -ICR118 = 0x00, 0x00 -ICR119 = 0x00, 0x00 -ICR120 = 0x00, 0x00 -ICR121 = 0x00, 0x00 -ICR122 = 0x00, 0x00 -ICR123 = 0x00, 0x00 -ICR124 = 0x00, 0x00 -ICR125 = 0x00, 0x00 -ICR127 = 0x00, 0x00 -ICR128 = 0x00, 0x00 -ICR129 = 0x00, 0x00 -ICR130 = 0x00, 0x00 -ICR131 = 0x00, 0x00 -ICR132 = 0x00, 0x00 -ICR133 = 0x00, 0x00 -ICR134 = 0x00, 0x00 -ICR135 = 0x00, 0x00 -ICR136 = 0x00, 0x00 -ICR137 = 0x00, 0x00 -ICR138 = 0x00, 0x00 -ICR139 = 0x00, 0x00 -ICR140 = 0x00, 0x00 -ICR141 = 0x00, 0x00 -ICR142 = 0x00, 0x00 -ICR143 = 0x00, 0x00 -ICR144 = 0x00, 0x00 -ICR145 = 0x00, 0x00 -ICR146 = 0x00, 0x00 -ICR147 = 0x00, 0x00 -ICR148 = 0x00, 0x00 -ICR149 = 0x00, 0x00 -ICR150 = 0x00, 0x00 -ICR151 = 0x00, 0x00 -ICR152 = 0x00, 0x00 -ICR153 = 0x00, 0x00 -ICR154 = 0x00, 0x00 -ICR155 = 0x00, 0x00 -ICR156 = 0x00, 0x00 -ICR157 = 0x00, 0x00 -ICR158 = 0x00, 0x00 -ICR159 = 0x00, 0x00 -PDDR_ADDR = 0x00, 0x00 -PDDR_DATAH = 0x00, 0x00 -PDDR_DATAL = 0x00, 0x00 -PDDR_BUSCTL = 0x00, 0x00 -PDDR_BS = 0x00, 0x00 -PDDR_CS = 0x00, 0x00 -PDDR_SDRAM = 0x00, 0x00 -PDDR_FECI2C = 0x00, 0x00 -PDDR_UARTH = 0x00, 0x00 -PDDR_UARTL = 0x00, 0x00 -PDDR_QSPI = 0x00, 0x00 -PDDR_TIMER = 0x00, 0x00 -PDDR_ETPU = 0x00, 0x00 -PAR_AD = 0x00, 0x00 -PAR_BUSCTL = 0x5d5f, 0x0000 -PAR_BS = 0x0f, 0x00 -PAR_CS = 0xfe, 0x00 -PAR_SDRAM = 0x3f, 0x00 -PAR_FECI2C = 0x00, 0x00 -PAR_UART = 0x000c, 0x0000 -PAR_QSPI = 0x00, 0x00 -PAR_TIMER = 0x0000, 0x0000 -PAR_ETPU = 0x00, 0x00 -DSCR_EIM = 0x00, 0x00 -DSCR_ETPU = 0x00, 0x00 -DSCR_FECI2C = 0x00, 0x00 -DSCR_UART = 0x00, 0x00 -DSCR_QSPI = 0x00, 0x00 -DSCR_TIMER = 0x00, 0x00 -string: External Clock Reference=25.0000 MHz -string: External frequency DMA Timer 0=1.0 MHz -string: External frequency DMA Timer 1=1.0 MHz -string: External frequency DMA Timer 2=1.0 MHz -string: External frequency DMA Timer 3=1.0 MHz -string: Baud Rate UART 0=9600 -string: Baud Rate UART 1=9600 -string: Baud Rate UART 2=9600 -string: Baud Rate UART 3=9600 -string: External frequency Timer 0=1.0 MHz -string: External frequency Timer 1=1.0 MHz -string: External frequency Timer 2=1.0 MHz -string: External frequency Timer 3=1.0 MHz diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/support/mcf5235.mac b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/support/mcf5235.mac deleted file mode 100644 index 4da2d616c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/support/mcf5235.mac +++ /dev/null @@ -1,8 +0,0 @@ -; set IPSBAR address -mbar 40000000 -; set RAMBAR for processor -control c05 100001 -; load debug file -hload ..\demo.elf -; set breakpoint at main -br main diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/vector.S b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/vector.S deleted file mode 100644 index 320c2d298..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235/vector.S +++ /dev/null @@ -1,322 +0,0 @@ - /* - * FreeModbus Libary: MCF5235 Demo Application - * Copyright (C) 2006 Christian Walter - * Parts of crt0.S Copyright (c) 1995, 1996, 1998 Cygnus Support - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id: vector.S,v 1.1 2006/05/14 21:59:16 wolti Exp $ - */ - - - .extern __stack - .extern start - .global ramvec_start - .global ramvec_end - .global romvec_start - .global romvec_end - .global vPortVecInit - - .section .vector, "x" -romvec_start: - .long __stack | Reset: Initial Stack Pointer - .long start | Reset: Initial Program Counter - .long VecDefault | Bus Error - .long VecDefault | Address Error - .long VecDefault | Illegal Instruction - .long VecDefault | Zero Divison - .space 4 | reserved - .space 4 | reserved - .long VecDefault | Privilege Violation - .long VecDefault | Trace - .long VecDefault | Unimplemented line-a opcode - .long VecDefault | Unimplemented line-b opcode - .long VecDefault | Non-PC breakpoint debug interrupt - .long VecDefault | PC breakpoint debug interrupt - .long VecDefault | Format Error - .long VecDefault | Uninitialized Interrupt - .org 0x60 - .long IRQSpurious | Spurious Interrupt - .long IRQDefault | Level 1 Interrupt - .long IRQDefault | Level 2 Interrupt - .long IRQDefault | Level 3 Interrupt - .long IRQDefault | Level 4 Interrupt - .long IRQDefault | Level 5 Interrupt - .long IRQDefault | Level 6 Interrupt - .long IRQDefault | Level 7 Interrupt - .org 0x80 - .long TrapDefault | TRAP 0 - .long TrapDefault | TRAP 1 - .long TrapDefault | TRAP 2 - .long TrapDefault | TRAP 3 - .long TrapDefault | TRAP 4 - .long TrapDefault | TRAP 5 - .long TrapDefault | TRAP 6 - .long TrapDefault | TRAP 7 - .long TrapDefault | TRAP 8 - .long TrapDefault | TRAP 9 - .long TrapDefault | TRAP 10 - .long TrapDefault | TRAP 11 - .long TrapDefault | TRAP 12 - .long TrapDefault | TRAP 13 - .long TrapDefault | TRAP 14 - .long TrapDefault | TRAP 15 - .org 0x100 - .long IRQDefault | User-Defined Interrupt 0 - .long IRQDefault | User-Defined Interrupt 1 - .long IRQDefault | User-Defined Interrupt 2 - .long IRQDefault | User-Defined Interrupt 3 - .long IRQDefault | User-Defined Interrupt 4 - .long IRQDefault | User-Defined Interrupt 5 - .long IRQDefault | User-Defined Interrupt 6 - .long IRQDefault | User-Defined Interrupt 7 - .long IRQDefault | User-Defined Interrupt 8 - .long IRQDefault | User-Defined Interrupt 9 - .long IRQDefault | User-Defined Interrupt 10 - .long IRQDefault | User-Defined Interrupt 11 - .long IRQDefault | User-Defined Interrupt 12 - .long IRQUart0 | User-Defined Interrupt 13 - .long IRQDefault | User-Defined Interrupt 14 - .long IRQDefault | User-Defined Interrupt 15 - .long IRQDefault | User-Defined Interrupt 16 - .long IRQDefault | User-Defined Interrupt 17 - .long IRQDefault | User-Defined Interrupt 18 - .long IRQDefault | User-Defined Interrupt 19 - .long IRQDefault | User-Defined Interrupt 20 - .long IRQDefault | User-Defined Interrupt 21 - .long IRQDefault | User-Defined Interrupt 22 - .long IRQDefault | User-Defined Interrupt 23 - .long IRQDefault | User-Defined Interrupt 24 - .long IRQDefault | User-Defined Interrupt 25 - .long IRQDefault | User-Defined Interrupt 26 - .long IRQDefault | User-Defined Interrupt 27 - .long IRQDefault | User-Defined Interrupt 28 - .long IRQDefault | User-Defined Interrupt 29 - .long IRQDefault | User-Defined Interrupt 30 - .long IRQDefault | User-Defined Interrupt 31 - .long IRQDefault | User-Defined Interrupt 32 - .long IRQDefault | User-Defined Interrupt 33 - .long IRQDefault | User-Defined Interrupt 34 - .long IRQDefault | User-Defined Interrupt 35 - .long IRQPIT0 | User-Defined Interrupt 36 - .long IRQDefault | User-Defined Interrupt 37 - .long IRQDefault | User-Defined Interrupt 38 - .long IRQDefault | User-Defined Interrupt 39 - .long IRQDefault | User-Defined Interrupt 40 - .long IRQDefault | User-Defined Interrupt 41 - .long IRQDefault | User-Defined Interrupt 42 - .long IRQDefault | User-Defined Interrupt 43 - .long IRQDefault | User-Defined Interrupt 44 - .long IRQDefault | User-Defined Interrupt 45 - .long IRQDefault | User-Defined Interrupt 46 - .long IRQDefault | User-Defined Interrupt 47 - .long IRQDefault | User-Defined Interrupt 48 - .long IRQDefault | User-Defined Interrupt 49 - .long IRQDefault | User-Defined Interrupt 50 - .long IRQDefault | User-Defined Interrupt 51 - .long IRQDefault | User-Defined Interrupt 52 - .long IRQDefault | User-Defined Interrupt 53 - .long IRQDefault | User-Defined Interrupt 54 - .long IRQDefault | User-Defined Interrupt 55 - .long IRQDefault | User-Defined Interrupt 56 - .long IRQDefault | User-Defined Interrupt 57 - .long IRQDefault | User-Defined Interrupt 58 - .long IRQDefault | User-Defined Interrupt 59 - .long IRQDefault | User-Defined Interrupt 60 - .long IRQDefault | User-Defined Interrupt 61 - .long IRQDefault | User-Defined Interrupt 62 - .long IRQDefault | User-Defined Interrupt 63 - .long IRQDefault | User-Defined Interrupt 64 - .long IRQDefault | User-Defined Interrupt 65 - .long IRQDefault | User-Defined Interrupt 66 - .long IRQDefault | User-Defined Interrupt 67 - .long IRQDefault | User-Defined Interrupt 68 - .long IRQDefault | User-Defined Interrupt 69 - .long IRQDefault | User-Defined Interrupt 70 - .long IRQDefault | User-Defined Interrupt 71 - .long IRQDefault | User-Defined Interrupt 72 - .long IRQDefault | User-Defined Interrupt 73 - .long IRQDefault | User-Defined Interrupt 74 - .long IRQDefault | User-Defined Interrupt 75 - .long IRQDefault | User-Defined Interrupt 76 - .long IRQDefault | User-Defined Interrupt 77 - .long IRQDefault | User-Defined Interrupt 78 - .long IRQDefault | User-Defined Interrupt 79 - .long IRQDefault | User-Defined Interrupt 80 - .long IRQDefault | User-Defined Interrupt 81 - .long IRQDefault | User-Defined Interrupt 82 - .long IRQDefault | User-Defined Interrupt 83 - .long IRQDefault | User-Defined Interrupt 84 - .long IRQDefault | User-Defined Interrupt 85 - .long IRQDefault | User-Defined Interrupt 86 - .long IRQDefault | User-Defined Interrupt 87 - .long IRQDefault | User-Defined Interrupt 88 - .long IRQDefault | User-Defined Interrupt 89 - .long IRQDefault | User-Defined Interrupt 90 - .long IRQDefault | User-Defined Interrupt 91 - .long IRQDefault | User-Defined Interrupt 92 - .long IRQDefault | User-Defined Interrupt 93 - .long IRQDefault | User-Defined Interrupt 94 - .long IRQDefault | User-Defined Interrupt 95 - .long IRQDefault | User-Defined Interrupt 96 - .long IRQDefault | User-Defined Interrupt 97 - .long IRQDefault | User-Defined Interrupt 98 - .long IRQDefault | User-Defined Interrupt 99 - .long IRQDefault | User-Defined Interrupt 100 - .long IRQDefault | User-Defined Interrupt 101 - .long IRQDefault | User-Defined Interrupt 102 - .long IRQDefault | User-Defined Interrupt 103 - .long IRQDefault | User-Defined Interrupt 104 - .long IRQDefault | User-Defined Interrupt 105 - .long IRQDefault | User-Defined Interrupt 106 - .long IRQDefault | User-Defined Interrupt 107 - .long IRQDefault | User-Defined Interrupt 108 - .long IRQDefault | User-Defined Interrupt 109 - .long IRQDefault | User-Defined Interrupt 110 - .long IRQDefault | User-Defined Interrupt 111 - .long IRQDefault | User-Defined Interrupt 112 - .long IRQDefault | User-Defined Interrupt 113 - .long IRQDefault | User-Defined Interrupt 114 - .long IRQDefault | User-Defined Interrupt 115 - .long IRQDefault | User-Defined Interrupt 116 - .long IRQDefault | User-Defined Interrupt 117 - .long IRQDefault | User-Defined Interrupt 118 - .long IRQDefault | User-Defined Interrupt 119 - .long IRQDefault | User-Defined Interrupt 120 - .long IRQDefault | User-Defined Interrupt 121 - .long IRQDefault | User-Defined Interrupt 122 - .long IRQDefault | User-Defined Interrupt 123 - .long IRQDefault | User-Defined Interrupt 124 - .long IRQDefault | User-Defined Interrupt 125 - .long IRQDefault | User-Defined Interrupt 126 - .long IRQDefault | User-Defined Interrupt 127 - .long IRQDefault | User-Defined Interrupt 128 - .long IRQDefault | User-Defined Interrupt 129 - .long IRQDefault | User-Defined Interrupt 130 - .long IRQDefault | User-Defined Interrupt 131 - .long IRQDefault | User-Defined Interrupt 132 - .long IRQDefault | User-Defined Interrupt 133 - .long IRQDefault | User-Defined Interrupt 134 - .long IRQDefault | User-Defined Interrupt 135 - .long IRQDefault | User-Defined Interrupt 136 - .long IRQDefault | User-Defined Interrupt 137 - .long IRQDefault | User-Defined Interrupt 138 - .long IRQDefault | User-Defined Interrupt 139 - .long IRQDefault | User-Defined Interrupt 140 - .long IRQDefault | User-Defined Interrupt 141 - .long IRQDefault | User-Defined Interrupt 142 - .long IRQDefault | User-Defined Interrupt 143 - .long IRQDefault | User-Defined Interrupt 144 - .long IRQDefault | User-Defined Interrupt 145 - .long IRQDefault | User-Defined Interrupt 146 - .long IRQDefault | User-Defined Interrupt 147 - .long IRQDefault | User-Defined Interrupt 148 - .long IRQDefault | User-Defined Interrupt 149 - .long IRQDefault | User-Defined Interrupt 150 - .long IRQDefault | User-Defined Interrupt 151 - .long IRQDefault | User-Defined Interrupt 152 - .long IRQDefault | User-Defined Interrupt 153 - .long IRQDefault | User-Defined Interrupt 154 - .long IRQDefault | User-Defined Interrupt 155 - .long IRQDefault | User-Defined Interrupt 156 - .long IRQDefault | User-Defined Interrupt 157 - .long IRQDefault | User-Defined Interrupt 158 - .long IRQDefault | User-Defined Interrupt 159 - .long IRQDefault | User-Defined Interrupt 160 - .long IRQDefault | User-Defined Interrupt 161 - .long IRQDefault | User-Defined Interrupt 162 - .long IRQDefault | User-Defined Interrupt 163 - .long IRQDefault | User-Defined Interrupt 164 - .long IRQDefault | User-Defined Interrupt 165 - .long IRQDefault | User-Defined Interrupt 166 - .long IRQDefault | User-Defined Interrupt 167 - .long IRQDefault | User-Defined Interrupt 168 - .long IRQDefault | User-Defined Interrupt 169 - .long IRQDefault | User-Defined Interrupt 170 - .long IRQDefault | User-Defined Interrupt 171 - .long IRQDefault | User-Defined Interrupt 172 - .long IRQDefault | User-Defined Interrupt 173 - .long IRQDefault | User-Defined Interrupt 174 - .long IRQDefault | User-Defined Interrupt 175 - .long IRQDefault | User-Defined Interrupt 176 - .long IRQDefault | User-Defined Interrupt 177 - .long IRQDefault | User-Defined Interrupt 178 - .long IRQDefault | User-Defined Interrupt 179 - .long IRQDefault | User-Defined Interrupt 180 - .long IRQDefault | User-Defined Interrupt 181 - .long IRQDefault | User-Defined Interrupt 182 - .long IRQDefault | User-Defined Interrupt 183 - .long IRQDefault | User-Defined Interrupt 184 - .long IRQDefault | User-Defined Interrupt 185 - .long IRQDefault | User-Defined Interrupt 186 - .long IRQDefault | User-Defined Interrupt 187 - .long IRQDefault | User-Defined Interrupt 188 - .long IRQDefault | User-Defined Interrupt 189 - .long IRQDefault | User-Defined Interrupt 190 - .long IRQDefault | User-Defined Interrupt 191 - .org 0x00000400 -romvec_end: - -/* - .section .bss -ramvec_start: - .space 0x400 -ramvec_end: - - .section .text -vPortVecInit: - move.l #romvec_start, a0 - move.l #ramvec_start, a1 - move.l #256, d0 -1: - move.l (a0)+, (a1)+ - subq.l #1, d0 - bne 1b - move.l #ramvec_start, a1 - movec a1, vbr - rts -*/ - .section .text -VecDefault: - halt - bra VecDefault - -IRQDefault: - halt - bra IRQDefault - -IRQSpurious: - halt - bra IRQSpurious - -TrapDefault: - halt - bra TrapDefault - -IRQUart0: - lea.l (-16, %sp), %sp - movem.l %d0-%d1/%a0-a1, (%sp) - jsr prvvMBPortSerialISR; - movem.l (%sp),%d0-%d1/%a0-%a1 - lea.l (16, %sp), %sp - rte - -IRQPIT0: - lea.l (-16, %sp), %sp - movem.l %d0-%d1/%a0-a1, (%sp) - jsr prvvMBPortTimerISR; - movem.l (%sp),%d0-%d1/%a0-%a1 - lea.l (16, %sp), %sp - rte diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/demo.c deleted file mode 100644 index 1c261009a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/demo.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * FreeModbus Libary: MCF5235 Demo Application - * Copyright (c) 2007 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * File: $Id$ - */ - -/* ------------------------ System includes ------------------------------- */ -#include -#include -#include -#include - -/* ------------------------ FreeRTOS includes ----------------------------- */ -#include "FreeRTOS.h" -#include "task.h" - -/* ------------------------ FreeModbus includes --------------------------- */ -#include "mb.h" - -/* ------------------------ Project includes ------------------------------ */ -#include "mcf5xxx.h" -#include "mcf523x.h" -#include "m523xbcc.h" - -/* ------------------------ Defines ------------------------------------------*/ -#define REG_INPUT_START 1000 -#define REG_INPUT_NREGS 4 - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegInputStart = REG_INPUT_START; -static USHORT usRegInputBuf[REG_INPUT_NREGS]; - -/* ----------------------- Static functions ---------------------------------*/ -static void vModbusTask( void *pvParameters ); -static void vTestTask( void *pvParameters ); - -/* ------------------------ Implementation -------------------------------- */ -void -main( void ) -{ - ( void )xTaskCreate( vModbusTask, NULL, configMINIMAL_STACK_SIZE, NULL, - tskIDLE_PRIORITY, NULL ); - /* Now all the tasks have been started - start the scheduler. */ - - vTaskStartScheduler( ); -} - -static void -vModbusTask( void *pvParameters ) -{ - ( void )pvParameters; - - /* Select either ASCII or RTU Mode. */ - ( void )eMBInit( MB_RTU, 0x0A, 0, 38400, MB_PAR_EVEN ); - - /* Enable the Modbus Protocol Stack. */ - ( void )eMBEnable( ); - - /* Enter main loop. */ - for( ;; ) - { - /* Call the main polling loop of the Modbus protocol stack. */ - ( void )eMBPoll( ); - } -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode ) -{ - ( void )pucRegBuffer; - ( void )usAddress; - ( void )usNRegs; - ( void )eMode; - return MB_ENOREG; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, eMBRegisterMode eMode ) -{ - ( void )pucRegBuffer; - ( void )usAddress; - ( void )usNCoils; - ( void )eMode; - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - ( void )pucRegBuffer; - ( void )usAddress; - ( void )usNDiscrete; - return MB_ENOREG; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/demo.cww b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/demo.cww deleted file mode 100644 index 427e87350..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/demo.cww +++ /dev/null @@ -1,89 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -]> - - - - -1 - 0 - true - demo.mcp - - 442 - 280 - - - 392 - 344 - - - 1 - 0 - 0 - 59420 - 1.000000 - 463 - - 0 - 0 - - - - - -1 - 32 - true - - 0 - 0 - - - 790 - 1360 - - - 0 - - - - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/demo.mcp b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/demo.mcp deleted file mode 100644 index 81ade40dd..000000000 Binary files a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/demo.mcp and /dev/null differ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/croutine.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/croutine.c deleted file mode 100644 index aa1e96fc3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/croutine.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/* Lists for ready and blocked co-routines. --------------------*/ -static xList pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ -static xList xDelayedCoRoutineList1; /*< Delayed co-routines. */ -static xList xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ -static xList * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */ -static xList * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ -static xList xPendingReadyList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ - -/* Other file private variables. --------------------------------*/ -corCRCB * pxCurrentCoRoutine = NULL; -static unsigned portBASE_TYPE uxTopCoRoutineReadyPriority = 0; -static portTickType xCoRoutineTickCount = 0; - -/* The initial state of the co-routine when it is created. */ -#define corINITIAL_STATE ( 0 ) - -/* - * Place the co-routine represented by pxCRCB into the appropriate ready queue - * for the priority. It is inserted at the end of the list. - * - * This macro accesses the co-routine ready lists and therefore must not be - * used from within an ISR. - */ -#define prvAddCoRoutineToReadyQueue( pxCRCB ) \ -{ \ - if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ - { \ - uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ - } \ - vListInsertEnd( ( xList * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ -} - -/* - * Utility to ready all the lists used by the scheduler. This is called - * automatically upon the creation of the first co-routine. - */ -static void prvInitialiseCoRoutineLists( void ); - -/* - * Co-routines that are readied by an interrupt cannot be placed directly into - * the ready lists (there is no mutual exclusion). Instead they are placed in - * in the pending ready list in order that they can later be moved to the ready - * list by the co-routine scheduler. - */ -static inline void prvCheckPendingReadyList( void ); - -/* - * Macro that looks at the list of co-routines that are currently delayed to - * see if any require waking. - * - * Co-routines are stored in the queue in the order of their wake time - - * meaning once one co-routine has been found whose timer has not expired - * we need not look any further down the list. - */ -static inline void prvCheckDelayedList( void ); - -/*-----------------------------------------------------------*/ - -portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ) -{ -portBASE_TYPE xReturn; -corCRCB *pxCoRoutine; - - /* Allocate the memory that will store the co-routine control block. */ - pxCoRoutine = ( corCRCB * ) pvPortMalloc( sizeof( corCRCB ) ); - if( pxCoRoutine ) - { - /* If pxCurrentCoRoutine is NULL then this is the first co-routine to - be created and the co-routine data structures need initialising. */ - if( pxCurrentCoRoutine == NULL ) - { - pxCurrentCoRoutine = pxCoRoutine; - prvInitialiseCoRoutineLists(); - } - - /* Check the priority is within limits. */ - if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) - { - uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; - } - - /* Fill out the co-routine control block from the function parameters. */ - pxCoRoutine->uxState = corINITIAL_STATE; - pxCoRoutine->uxPriority = uxPriority; - pxCoRoutine->uxIndex = uxIndex; - pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; - - /* Initialise all the other co-routine control block parameters. */ - vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); - vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); - - /* Set the co-routine control block as a link back from the xListItem. - This is so we can get back to the containing CRCB from a generic item - in a list. */ - listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); - listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); - - /* Event lists are always in priority order. */ - listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); - - /* Now the co-routine has been initialised it can be added to the ready - list at the correct priority. */ - prvAddCoRoutineToReadyQueue( pxCoRoutine ); - - xReturn = pdPASS; - } - else - { - xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList ) -{ -portTickType xTimeToWake; - - /* Calculate the time to wake - this may overflow but this is - not a problem. */ - xTimeToWake = xCoRoutineTickCount + xTicksToDelay; - - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xCoRoutineTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - } - - if( pxEventList ) - { - /* Also add the co-routine to an event list. If this is done then the - function must be called with interrupts disabled. */ - vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); - } -} -/*-----------------------------------------------------------*/ - -static inline void prvCheckPendingReadyList( void ) -{ - /* Are there any co-routines waiting to get moved to the ready list? These - are co-routines that have been readied by an ISR. The ISR cannot access - the ready lists itself. */ - while( !listLIST_IS_EMPTY( &xPendingReadyList ) ) - { - corCRCB *pxUnblockedCRCB; - - /* The pending ready list can be accessed by an ISR. */ - portDISABLE_INTERRUPTS(); - { - pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyList) ); - vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); - } - portENABLE_INTERRUPTS(); - - vListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); - prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); - } -} -/*-----------------------------------------------------------*/ - -static inline void prvCheckDelayedList( void ) -{ -static portTickType xLastTickCount, xPassedTicks; -corCRCB *pxCRCB; - - xPassedTicks = xTaskGetTickCount() - xLastTickCount; - while( xPassedTicks ) - { - xCoRoutineTickCount++; - xPassedTicks--; - - /* If the tick count has overflowed we need to swap the ready lists. */ - if( xCoRoutineTickCount == 0 ) - { - xList * pxTemp; - - /* Tick count has overflowed so we need to swap the delay lists. If there are - any items in pxDelayedCoRoutineList here then there is an error! */ - pxTemp = pxDelayedCoRoutineList; - pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; - pxOverflowDelayedCoRoutineList = pxTemp; - } - - /* See if this tick has made a timeout expire. */ - while( ( pxCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ) ) != NULL ) - { - if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) - { - /* Timeout not yet expired. */ - break; - } - - portDISABLE_INTERRUPTS(); - { - /* The event could have occurred just before this critical - section. If this is the case then the generic list item will - have been moved to the pending ready list and the following - line is still valid. Also the pvContainer parameter will have - been set to NULL so the following lines are also valid. */ - vListRemove( &( pxCRCB->xGenericListItem ) ); - - /* Is the co-routine waiting on an event also? */ - if( pxCRCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxCRCB->xEventListItem ) ); - } - } - portENABLE_INTERRUPTS(); - - prvAddCoRoutineToReadyQueue( pxCRCB ); - } - } - - xLastTickCount = xCoRoutineTickCount; -} -/*-----------------------------------------------------------*/ - -void vCoRoutineSchedule( void ) -{ - /* See if any co-routines readied by events need moving to the ready lists. */ - prvCheckPendingReadyList(); - - /* See if any delayed co-routines have timed out. */ - prvCheckDelayedList(); - - /* Find the highest priority queue that contains ready co-routines. */ - while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) - { - if( uxTopCoRoutineReadyPriority == 0 ) - { - /* No more co-routines to check. */ - return; - } - --uxTopCoRoutineReadyPriority; - } - - /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines - of the same priority get an equal share of the processor time. */ - listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); - - /* Call the co-routine. */ - ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); - - return; -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseCoRoutineLists( void ) -{ -unsigned portBASE_TYPE uxPriority; - - for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) - { - vListInitialise( ( xList * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); - } - - vListInitialise( ( xList * ) &xDelayedCoRoutineList1 ); - vListInitialise( ( xList * ) &xDelayedCoRoutineList2 ); - vListInitialise( ( xList * ) &xPendingReadyList ); - - /* Start with pxDelayedCoRoutineList using list1 and the - pxOverflowDelayedCoRoutineList using list2. */ - pxDelayedCoRoutineList = &xDelayedCoRoutineList1; - pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList ) -{ -corCRCB *pxUnblockedCRCB; -portBASE_TYPE xReturn; - - /* This function is called from within an interrupt. It can only access - event lists and the pending ready list. */ - pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); - vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedCRCB->xEventListItem ) ); - - if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) - { - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/FreeRTOS.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/FreeRTOS.h deleted file mode 100644 index dcf4f444b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/FreeRTOS.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef INC_FREERTOS_H -#define INC_FREERTOS_H - - -/* - * Include the generic headers required for the FreeRTOS port being used. - */ -#include - -/* Basic FreeRTOS definitions. */ -#include "projdefs.h" - -/* Application specific configuration options. */ -#include "FreeRTOSConfig.h" - -/* Definitions specific to the port being used. */ -#include "portable.h" - - - - - - - -/* - * Check all the required application specific macros have been defined. - * These macros are application specific and (as downloaded) are defined - * within FreeRTOSConfig.h. - */ - -#ifndef configUSE_PREEMPTION - #error Missing definition: configUSE_PREEMPTION should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_IDLE_HOOK - #error Missing definition: configUSE_IDLE_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_TICK_HOOK - #error Missing definition: configUSE_TICK_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_CO_ROUTINES - #error Missing definition: configUSE_CO_ROUTINES should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskPrioritySet - #error Missing definition: INCLUDE_vTaskPrioritySet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_uxTaskPriorityGet - #error Missing definition: INCLUDE_uxTaskPriorityGet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelete - #error Missing definition: INCLUDE_vTaskDelete should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskCleanUpResources - #error Missing definition: INCLUDE_vTaskCleanUpResources should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskSuspend - #error Missing definition: INCLUDE_vTaskSuspend should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelayUntil - #error Missing definition: INCLUDE_vTaskDelayUntil should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelay - #error Missing definition: INCLUDE_vTaskDelay should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_16_BIT_TICKS - #error Missing definition: configUSE_16_BIT_TICKS should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/croutine.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/croutine.h deleted file mode 100644 index e154ef758..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/croutine.h +++ /dev/null @@ -1,713 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ -#ifndef CO_ROUTINE_H -#define CO_ROUTINE_H - -#include "list.h" - -/* Used to hide the implementation of the co-routine control block. The -control block structure however has to be included in the header due to -the macro implementation of the co-routine functionality. */ -typedef void * xCoRoutineHandle; - -/* Defines the prototype to which co-routine functions must conform. */ -typedef void (*crCOROUTINE_CODE)( xCoRoutineHandle, unsigned portBASE_TYPE ); - -typedef struct corCoRoutineControlBlock -{ - crCOROUTINE_CODE pxCoRoutineFunction; - xListItem xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ - xListItem xEventListItem; /*< List item used to place the CRCB in event lists. */ - unsigned portBASE_TYPE uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ - unsigned portBASE_TYPE uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ - unsigned portSHORT uxState; /*< Used internally by the co-routine implementation. */ -} corCRCB; /* Co-routine control block. Note must be identical in size down to uxPriority with tskTCB. */ - -/** - * croutine. h - *
- portBASE_TYPE xCoRoutineCreate(
-                                 crCOROUTINE_CODE pxCoRoutineCode,
-                                 unsigned portBASE_TYPE uxPriority,
-                                 unsigned portBASE_TYPE uxIndex
-                               );
- * - * Create a new co-routine and add it to the list of co-routines that are - * ready to run. - * - * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine - * functions require special syntax - see the co-routine section of the WEB - * documentation for more information. - * - * @param uxPriority The priority with respect to other co-routines at which - * the co-routine will run. - * - * @param uxIndex Used to distinguish between different co-routines that - * execute the same function. See the example below and the co-routine section - * of the WEB documentation for further information. - * - * @return pdPASS if the co-routine was successfully created and added to a ready - * list, otherwise an error code defined with ProjDefs.h. - * - * Example usage: -
- // Co-routine to be created.
- void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- // This may not be necessary for const variables.
- static const char cLedToFlash[ 2 ] = { 5, 6 };
- static const portTickType xTimeToDelay[ 2 ] = { 200, 400 };
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // This co-routine just delays for a fixed period, then toggles
-         // an LED.  Two co-routines are created using this function, so
-         // the uxIndex parameter is used to tell the co-routine which
-         // LED to flash and how long to delay.  This assumes xQueue has
-         // already been created.
-         vParTestToggleLED( cLedToFlash[ uxIndex ] );
-         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
-
- // Function that creates two co-routines.
- void vOtherFunction( void )
- {
- unsigned char ucParameterToPass;
- xTaskHandle xHandle;
-		
-     // Create two co-routines at priority 0.  The first is given index 0
-     // so (from the code above) toggles LED 5 every 200 ticks.  The second
-     // is given index 1 so toggles LED 6 every 400 ticks.
-     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
-     {
-         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
-     }  
- }
-   
- * \defgroup xCoRoutineCreate xCoRoutineCreate - * \ingroup Tasks - */ -portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ); - - -/** - * croutine. h - *
- void vCoRoutineSchedule( void );
- * - * Run a co-routine. - * - * vCoRoutineSchedule() executes the highest priority co-routine that is able - * to run. The co-routine will execute until it either blocks, yields or is - * preempted by a task. Co-routines execute cooperatively so one - * co-routine cannot be preempted by another, but can be preempted by a task. - * - * If an application comprises of both tasks and co-routines then - * vCoRoutineSchedule should be called from the idle task (in an idle task - * hook). - * - * Example usage: -
- // This idle task hook will schedule a co-routine each time it is called.
- // The rest of the idle task will execute between co-routine calls.
- void vApplicationIdleHook( void )
- {
-	vCoRoutineSchedule();
- }
-
- // Alternatively, if you do not require any other part of the idle task to 
- // execute, the idle task hook can call vCoRoutineScheduler() within an
- // infinite loop.
- void vApplicationIdleHook( void )
- {
-    for( ;; )
-    {
-        vCoRoutineSchedule();
-    }
- }
- 
- * \defgroup vCoRoutineSchedule vCoRoutineSchedule - * \ingroup Tasks - */ -void vCoRoutineSchedule( void ); - -/** - * croutine. h - *
- crSTART( xCoRoutineHandle xHandle );
- * - * This macro MUST always be called at the start of a co-routine function. - * - * Example usage: -
- // Co-routine to be created.
- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portLONG ulAVariable;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-          // Co-routine functionality goes here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
- * \defgroup crSTART crSTART - * \ingroup Tasks - */ -#define crSTART( pxCRCB ) switch( ( ( corCRCB * )pxCRCB )->uxState ) { case 0: - -/** - * croutine. h - *
- crEND();
- * - * This macro MUST always be called at the end of a co-routine function. - * - * Example usage: -
- // Co-routine to be created.
- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portLONG ulAVariable;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-          // Co-routine functionality goes here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
- * \defgroup crSTART crSTART - * \ingroup Tasks - */ -#define crEND() } - -/* - * These macros are intended for internal use by the co-routine implementation - * only. The macros should not be used directly by application writers. - */ -#define crSET_STATE0( xHandle ) ( ( corCRCB * )xHandle)->uxState = (__LINE__ * 2); return; case (__LINE__ * 2): -#define crSET_STATE1( xHandle ) ( ( corCRCB * )xHandle)->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1): - -/** - * croutine. h - *
- crDELAY( xCoRoutineHandle xHandle, portTickType xTicksToDelay );
- * - * Delay a co-routine for a fixed period of time. - * - * crDELAY can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * @param xHandle The handle of the co-routine to delay. This is the xHandle - * parameter of the co-routine function. - * - * @param xTickToDelay The number of ticks that the co-routine should delay - * for. The actual amount of time this equates to is defined by - * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_RATE_MS - * can be used to convert ticks to milliseconds. - * - * Example usage: -
- // Co-routine to be created.
- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- // This may not be necessary for const variables.
- // We are to delay for 200ms.
- static const xTickType xDelayTime = 200 / portTICK_RATE_MS;
-
-     // Must start every co-routine with a call to crSTART();
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-        // Delay for 200ms.
-        crDELAY( xHandle, xDelayTime );
-
-        // Do something here.
-     }
-
-     // Must end every co-routine with a call to crEND();
-     crEND();
- }
- * \defgroup crDELAY crDELAY - * \ingroup Tasks - */ -#define crDELAY( xHandle, xTicksToDelay ) \ - if( xTicksToDelay > 0 ) \ - { \ - vCoRoutineAddToDelayedList( xTicksToDelay, NULL ); \ - } \ - crSET_STATE0( xHandle ); - -/** - *
- crQUEUE_SEND( 
-                  xCoRoutineHandle xHandle, 
-                  xQueueHandle pxQueue, 
-                  void *pvItemToQueue, 
-                  portTickType xTicksToWait, 
-                  portBASE_TYPE *pxResult 
-             )
- * - * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine - * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. - * - * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas - * xQueueSend() and xQueueReceive() can only be used from tasks. - * - * crQUEUE_SEND can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xHandle The handle of the calling co-routine. This is the xHandle - * parameter of the co-routine function. - * - * @param pxQueue The handle of the queue on which the data will be posted. - * The handle is obtained as the return value when the queue is created using - * the xQueueCreate() API function. - * - * @param pvItemToQueue A pointer to the data being posted onto the queue. - * The number of bytes of each queued item is specified when the queue is - * created. This number of bytes is copied from pvItemToQueue into the queue - * itself. - * - * @param xTickToDelay The number of ticks that the co-routine should block - * to wait for space to become available on the queue, should space not be - * available immediately. The actual amount of time this equates to is defined - * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant - * portTICK_RATE_MS can be used to convert ticks to milliseconds (see example - * below). - * - * @param pxResult The variable pointed to by pxResult will be set to pdPASS if - * data was successfully posted onto the queue, otherwise it will be set to an - * error defined within ProjDefs.h. - * - * Example usage: -
- // Co-routine function that blocks for a fixed period then posts a number onto
- // a queue.
- static void prvCoRoutineFlashTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portBASE_TYPE xNumberToPost = 0;
- static portBASE_TYPE xResult;
-
-    // Co-routines must begin with a call to crSTART().
-    crSTART( xHandle );
-
-    for( ;; )
-    {
-        // This assumes the queue has already been created.
-        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
-
-        if( xResult != pdPASS )
-        {
-            // The message was not posted!
-        }
-
-        // Increment the number to be posted onto the queue.
-        xNumberToPost++;
- 
-        // Delay for 100 ticks.
-        crDELAY( xHandle, 100 );
-    }
-
-    // Co-routines must end with a call to crEND().
-    crEND();
- }
- * \defgroup crQUEUE_SEND crQUEUE_SEND - * \ingroup Tasks - */ -#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ -{ \ - *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, xTicksToWait ); \ - if( *pxResult == errQUEUE_BLOCKED ) \ - { \ - crSET_STATE0( xHandle ); \ - *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, 0 ); \ - } \ - if( *pxResult == errQUEUE_YIELD ) \ - { \ - crSET_STATE1( xHandle ); \ - *pxResult = pdPASS; \ - } \ -} - -/** - * croutine. h - *
-  crQUEUE_RECEIVE( 
-                     xCoRoutineHandle xHandle, 
-                     xQueueHandle pxQueue, 
-                     void *pvBuffer, 
-                     portTickType xTicksToWait, 
-                     portBASE_TYPE *pxResult 
-                 )
- * - * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine - * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. - * - * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas - * xQueueSend() and xQueueReceive() can only be used from tasks. - * - * crQUEUE_RECEIVE can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xHandle The handle of the calling co-routine. This is the xHandle - * parameter of the co-routine function. - * - * @param pxQueue The handle of the queue from which the data will be received. - * The handle is obtained as the return value when the queue is created using - * the xQueueCreate() API function. - * - * @param pvBuffer The buffer into which the received item is to be copied. - * The number of bytes of each queued item is specified when the queue is - * created. This number of bytes is copied into pvBuffer. - * - * @param xTickToDelay The number of ticks that the co-routine should block - * to wait for data to become available from the queue, should data not be - * available immediately. The actual amount of time this equates to is defined - * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant - * portTICK_RATE_MS can be used to convert ticks to milliseconds (see the - * crQUEUE_SEND example). - * - * @param pxResult The variable pointed to by pxResult will be set to pdPASS if - * data was successfully retrieved from the queue, otherwise it will be set to - * an error code as defined within ProjDefs.h. - * - * Example usage: -
- // A co-routine receives the number of an LED to flash from a queue.  It 
- // blocks on the queue until the number is received.
- static void prvCoRoutineFlashWorkTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // Variables in co-routines must be declared static if they must maintain value across a blocking call.
- static portBASE_TYPE xResult;
- static unsigned portBASE_TYPE uxLEDToFlash;
-
-    // All co-routines must start with a call to crSTART().
-    crSTART( xHandle );
-
-    for( ;; )
-    {
-        // Wait for data to become available on the queue.
-        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
-
-        if( xResult == pdPASS )
-        {
-            // We received the LED to flash - flash it!
-            vParTestToggleLED( uxLEDToFlash );
-        }
-    }
-
-    crEND();
- }
- * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE - * \ingroup Tasks - */ -#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ -{ \ - *pxResult = xQueueCRReceive( pxQueue, pvBuffer, xTicksToWait ); \ - if( *pxResult == errQUEUE_BLOCKED ) \ - { \ - crSET_STATE0( xHandle ); \ - *pxResult = xQueueCRReceive( pxQueue, pvBuffer, 0 ); \ - } \ - if( *pxResult == errQUEUE_YIELD ) \ - { \ - crSET_STATE1( xHandle ); \ - *pxResult = pdPASS; \ - } \ -} - -/** - * croutine. h - *
-  crQUEUE_SEND_FROM_ISR( 
-                            xQueueHandle pxQueue, 
-                            void *pvItemToQueue, 
-                            portBASE_TYPE xCoRoutinePreviouslyWoken
-                       )
- * - * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the - * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() - * functions used by tasks. - * - * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to - * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and - * xQueueReceiveFromISR() can only be used to pass data between a task and and - * ISR. - * - * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue - * that is being used from within a co-routine. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto - * the same queue multiple times from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. - * - * @return pdTRUE if a co-routine was woken by posting onto the queue. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage: -
- // A co-routine that blocks on a queue waiting for characters to be received.
- static void vReceivingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- portCHAR cRxedChar;
- portBASE_TYPE xResult;
-
-     // All co-routines must start with a call to crSTART().
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // Wait for data to become available on the queue.  This assumes the
-         // queue xCommsRxQueue has already been created!
-         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
-    
-         // Was a character received?
-         if( xResult == pdPASS )
-         {
-             // Process the character here.
-         }
-     }
-
-     // All co-routines must end with a call to crEND().
-     crEND();
- }
-
- // An ISR that uses a queue to send characters received on a serial port to
- // a co-routine.
- void vUART_ISR( void )
- {
- portCHAR cRxedChar;
- portBASE_TYPE xCRWokenByPost = pdFALSE;
-
-     // We loop around reading characters until there are none left in the UART.
-     while( UART_RX_REG_NOT_EMPTY() )
-     {
-         // Obtain the character from the UART.
-         cRxedChar = UART_RX_REG;
-        
-         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE 
-         // the first time around the loop.  If the post causes a co-routine
-         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
-         // In this manner we can ensure that if more than one co-routine is
-         // blocked on the queue only one is woken by this ISR no matter how
-         // many characters are posted to the queue.
-         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
-     }
- }
- * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR - * \ingroup Tasks - */ -#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) - - -/** - * croutine. h - *
-  crQUEUE_SEND_FROM_ISR( 
-                            xQueueHandle pxQueue, 
-                            void *pvBuffer, 
-                            portBASE_TYPE * pxCoRoutineWoken
-                       )
- * - * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the - * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() - * functions used by tasks. - * - * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to - * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and - * xQueueReceiveFromISR() can only be used to pass data between a task and and - * ISR. - * - * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data - * from a queue that is being used from within a co-routine (a co-routine - * posted to the queue). - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvBuffer A pointer to a buffer into which the received item will be - * placed. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from the queue into - * pvBuffer. - * - * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become - * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a - * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise - * *pxCoRoutineWoken will remain unchanged. - * - * @return pdTRUE an item was successfully received from the queue, otherwise - * pdFALSE. - * - * Example usage: -
- // A co-routine that posts a character to a queue then blocks for a fixed 
- // period.  The character is incremented each time.
- static void vSendingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )
- {
- // cChar holds its value while this co-routine is blocked and must therefore
- // be declared static.
- static portCHAR cCharToTx = 'a';
- portBASE_TYPE xResult;
-
-     // All co-routines must start with a call to crSTART().
-     crSTART( xHandle );
-
-     for( ;; )
-     {
-         // Send the next character to the queue.
-         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
-    
-         if( xResult == pdPASS )
-         {
-             // The character was successfully posted to the queue.
-         }
-		 else
-		 {
-			// Could not post the character to the queue.
-		 }
-
-         // Enable the UART Tx interrupt to cause an interrupt in this
-		 // hypothetical UART.  The interrupt will obtain the character
-		 // from the queue and send it.
-		 ENABLE_RX_INTERRUPT();
-
-		 // Increment to the next character then block for a fixed period. 
-		 // cCharToTx will maintain its value across the delay as it is
-		 // declared static.
-		 cCharToTx++;
-		 if( cCharToTx > 'x' )
-		 {
-			cCharToTx = 'a';
-		 }
-		 crDELAY( 100 );
-     }
-
-     // All co-routines must end with a call to crEND().
-     crEND();
- }
-
- // An ISR that uses a queue to receive characters to send on a UART.
- void vUART_ISR( void )
- {
- portCHAR cCharToTx;
- portBASE_TYPE xCRWokenByPost = pdFALSE;
-
-     while( UART_TX_REG_EMPTY() )
-     {
-         // Are there any characters in the queue waiting to be sent?
-		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
-		 // is woken by the post - ensuring that only a single co-routine is
-		 // woken no matter how many times we go around this loop.
-         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
-		 {
-			 SEND_CHARACTER( cCharToTx );
-		 }
-     }
- }
- * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR - * \ingroup Tasks - */ -#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( pxQueue, pvBuffer, pxCoRoutineWoken ) - -/* - * This function is intended for internal use by the co-routine macros only. - * The macro nature of the co-routine implementation requires that the - * prototype appears here. The function should not be used by application - * writers. - * - * Removes the current co-routine from its ready list and places it in the - * appropriate delayed list. - */ -void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList ); - -/* - * This function is intended for internal use by the queue implementation only. - * The function should not be used by application writers. - * - * Removes the highest priority co-routine from the event list and places it in - * the pending ready list. - */ -portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList ); - - -#endif /* CO_ROUTINE_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/list.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/list.h deleted file mode 100644 index 44786cfa2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/list.h +++ /dev/null @@ -1,270 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This is the list implementation used by the scheduler. While it is tailored - * heavily for the schedulers needs, it is also available for use by - * application code. - * - * xLists can only store pointers to xListItems. Each xListItem contains a - * numeric value (xItemValue). Most of the time the lists are sorted in - * descending item value order. - * - * Lists are created already containing one list item. The value of this - * item is the maximum possible that can be stored, it is therefore always at - * the end of the list and acts as a marker. The list member pxHead always - * points to this marker - even though it is at the tail of the list. This - * is because the tail contains a wrap back pointer to the true head of - * the list. - * - * In addition to it's value, each list item contains a pointer to the next - * item in the list (pxNext), a pointer to the list it is in (pxContainer) - * and a pointer to back to the object that contains it. These later two - * pointers are included for efficiency of list manipulation. There is - * effectively a two way link between the object containing the list item and - * the list item itself. - * - * - * \page ListIntroduction List Implementation - * \ingroup FreeRTOSIntro - */ - - -#ifndef LIST_H -#define LIST_H - -/* - * Definition of the only type of object that a list can contain. - */ -struct xLIST_ITEM -{ - portTickType xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ - volatile struct xLIST_ITEM * pxNext; /*< Pointer to the next xListItem in the list. */ - volatile struct xLIST_ITEM * pxPrevious;/*< Pointer to the previous xListItem in the list. */ - void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ - void * pvContainer; /*< Pointer to the list in which this list item is placed (if any). */ -}; -typedef struct xLIST_ITEM xListItem; /* For some reason lint wants this as two separate definitions. */ - -struct xMINI_LIST_ITEM -{ - portTickType xItemValue; - volatile struct xLIST_ITEM *pxNext; - volatile struct xLIST_ITEM *pxPrevious; -}; -typedef struct xMINI_LIST_ITEM xMiniListItem; - -/* - * Definition of the type of queue used by the scheduler. - */ -typedef struct xLIST -{ - volatile unsigned portBASE_TYPE uxNumberOfItems; - volatile xListItem * pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to pvListGetOwnerOfNextEntry (). */ - volatile xMiniListItem xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ -} xList; - -/* - * Access macro to set the owner of a list item. The owner of a list item - * is the object (usually a TCB) that contains the list item. - * - * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( pxListItem )->pvOwner = ( void * ) pxOwner - -/* - * Access macro to set the value of the list item. In most cases the value is - * used to sort the list in descending order. - * - * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( pxListItem )->xItemValue = xValue - -/* - * Access macro the retrieve the value of the list item. The value can - * represent anything - for example a the priority of a task, or the time at - * which a task should be unblocked. - * - * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) - -/* - * Access macro to determine if a list contains any items. The macro will - * only have the value true if the list is empty. - * - * \page listLIST_IS_EMPTY listLIST_IS_EMPTY - * \ingroup LinkedList - */ -#define listLIST_IS_EMPTY( pxList ) ( ( pxList )->uxNumberOfItems == ( unsigned portBASE_TYPE ) 0 ) - -/* - * Access macro to return the number of items in the list. - */ -#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) - -/* - * Access function to obtain the owner of the next entry in a list. - * - * The list member pxIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list - * and returns that entries pxOwner parameter. Using multiple calls to this - * function it is therefore possible to move through every item contained in - * a list. - * - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the next item owner is to be returned. - * - * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ - /* Increment the index to the next item and return the item, ensuring */ \ - /* we don't return the marker used at the end of the list. */ \ - ( pxList )->pxIndex = ( pxList )->pxIndex->pxNext; \ - if( ( pxList )->pxIndex == ( xListItem * ) &( ( pxList )->xListEnd ) ) \ - { \ - ( pxList )->pxIndex = ( pxList )->pxIndex->pxNext; \ - } \ - pxTCB = ( pxList )->pxIndex->pvOwner - - -/* - * Access function to obtain the owner of the first entry in a list. Lists - * are normally sorted in ascending item value order. - * - * This function returns the pxOwner member of the first item in the list. - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the owner of the head item is to be - * returned. - * - * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( pxList->uxNumberOfItems != ( unsigned portBASE_TYPE ) 0 ) ? ( (&( pxList->xListEnd ))->pxNext->pvOwner ) : ( NULL ) ) - -/* - * Check to see if a list item is within a list. The list item maintains a - * "container" pointer that points to the list it is in. All this macro does - * is check to see if the container and the list match. - * - * @param pxList The list we want to know if the list item is within. - * @param pxListItem The list item we want to know if is in the list. - * @return pdTRUE is the list item is in the list, otherwise pdFALSE. - * pointer against - */ -#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( pxListItem )->pvContainer == ( void * ) pxList ) - -/* - * Must be called before a list is used! This initialises all the members - * of the list structure and inserts the xListEnd item into the list as a - * marker to the back of the list. - * - * @param pxList Pointer to the list being initialised. - * - * \page vListInitialise vListInitialise - * \ingroup LinkedList - */ -void vListInitialise( xList *pxList ); - -/* - * Must be called before a list item is used. This sets the list container to - * null so the item does not think that it is already contained in a list. - * - * @param pxItem Pointer to the list item being initialised. - * - * \page vListInitialiseItem vListInitialiseItem - * \ingroup LinkedList - */ -void vListInitialiseItem( xListItem *pxItem ); - -/* - * Insert a list item into a list. The item will be inserted into the list in - * a position determined by its item value (descending item value order). - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The item to that is to be placed in the list. - * - * \page vListInsert vListInsert - * \ingroup LinkedList - */ -void vListInsert( xList *pxList, xListItem *pxNewListItem ); - -/* - * Insert a list item into a list. The item will be inserted in a position - * such that it will be the last item within the list returned by multiple - * calls to listGET_OWNER_OF_NEXT_ENTRY. - * - * The list member pvIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list. - * Placing an item in a list using vListInsertEnd effectively places the item - * in the list position pointed to by pvIndex. This means that every other - * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before - * the pvIndex parameter again points to the item being inserted. - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The list item to be inserted into the list. - * - * \page vListInsertEnd vListInsertEnd - * \ingroup LinkedList - */ -void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ); - -/* - * Remove an item from a list. The list item has a pointer to the list that - * it is in, so only the list item need be passed into the function. - * - * @param vListRemove The item to be removed. The item will remove itself from - * the list pointed to by it's pxContainer parameter. - * - * \page vListRemove vListRemove - * \ingroup LinkedList - */ -void vListRemove( xListItem *pxItemToRemove ); - - - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/portable.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/portable.h deleted file mode 100644 index 998ba5687..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/portable.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http:www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http:www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Portable layer API. Each function must be defined for each port. - *----------------------------------------------------------*/ - -#ifndef PORTABLE_H -#define PORTABLE_H - -/* Include the macro file relevant to the port being used. */ - -#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT - #include "..\..\source\portable\owatcom\16bitdos\pc\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT - #include "..\..\source\portable\owatcom\16bitdos\flsh186\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef GCC_MEGA_AVR - #include "../portable/GCC/ATMega323/portmacro.h" -#endif - -#ifdef IAR_MEGA_AVR - #include "../portable/IAR/ATMega323/portmacro.h" -#endif - -#ifdef MPLAB_PIC18F_PORT - #include "..\..\source\portable\MPLAB\PIC18F\portmacro.h" -#endif - -#ifdef _FEDPICC - #include "libFreeRTOS/Include/portmacro.h" -#endif - -#ifdef SDCC_CYGNAL - #include "../../Source/portable/SDCC/Cygnal/portmacro.h" -#endif - -#ifdef GCC_ARM7 - #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" -#endif - -#ifdef GCC_MSP430 - #include "../../Source/portable/GCC/MSP430F449/portmacro.h" -#endif - -#ifdef ROWLEY_MSP430 - #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" -#endif - -#ifdef KEIL_ARM7 - #include "..\..\Source\portable\Keil\ARM7\portmacro.h" -#endif - -#ifdef SAM7_GCC - #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" -#endif - -#ifdef SAM7_IAR - #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" -#endif - -#ifdef LPC2000_IAR - #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" -#endif - -#ifdef STR71X_IAR - #include "..\..\Source\portable\IAR\STR71x\portmacro.h" -#endif - -#ifdef STR91X_IAR - #include "..\..\Source\portable\IAR\STR91x\portmacro.h" -#endif - -#ifdef GCC_H8S - #include "../../Source/portable/GCC/H8S2329/portmacro.h" -#endif - -#ifdef GCC_AT91FR40008 - #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" -#endif - -#ifdef RVDS_ARMCM3_LM3S102 - #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" -#endif - -#ifdef GCC_ARMCM3_LM3S102 - #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" -#endif - -#ifdef IAR_ARMCM3_LM - #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" -#endif - -#ifdef HCS12_CODE_WARRIOR - #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" -#endif - -#ifdef MICROBLAZE_GCC - #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" -#endif - -#ifdef TERN_EE - #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" -#endif - -#ifdef GCC_HCS12 - #include "../../Source/portable/GCC/HCS12/portmacro.h" -#endif - -#ifdef GCC_MCF5235 - #include "../portable/GCC/MCF5235/portmacro.h" -#endif - -#ifdef CODEWARRIOR_MCF5235 - #include "../portable/CodeWarrior/MCF5235/portmacro.h" -#endif - -#ifdef BCC_INDUSTRIAL_PC_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef BCC_FLASH_LITE_186_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif -/* - * Setup the stack of a new task so it is ready to be placed under the - * scheduler control. The registers have to be placed on the stack in - * the order that the port expects to find them. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ); - -/* - * Map to the memory management routines required for the port. - */ -void *pvPortMalloc( size_t xSize ); -void vPortFree( void *pv ); -void vPortInitialiseBlocks( void ); - -/* - * Setup the hardware ready for the scheduler to take control. This generally - * sets up a tick interrupt and sets timers for the correct tick frequency. - */ -portBASE_TYPE xPortStartScheduler( void ); - -/* - * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so - * the hardware is left in its original condition after the scheduler stops - * executing. - */ -void vPortEndScheduler( void ); - - -#endif /* PORTABLE_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/projdefs.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/projdefs.h deleted file mode 100644 index 79ea48373..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/projdefs.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PROJDEFS_H -#define PROJDEFS_H - -/* Defines to prototype to which task functions must conform. */ -typedef void (*pdTASK_CODE)( void * ); - -#define pdTRUE ( 1 ) -#define pdFALSE ( 0 ) - -#define pdPASS ( 1 ) -#define pdFAIL ( 0 ) - -/* Error definitions. */ -#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 ) -#define errNO_TASK_TO_RUN ( -2 ) -#define errQUEUE_FULL ( -3 ) -#define errQUEUE_BLOCKED ( -4 ) -#define errQUEUE_YIELD ( -5 ) - -#endif - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/queue.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/queue.h deleted file mode 100644 index 25f1772c5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/queue.h +++ /dev/null @@ -1,471 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef QUEUE_H -#define QUEUE_H - -typedef void * xQueueHandle; - -/** - * queue. h - *
- xQueueHandle xQueueCreate( 
-                              unsigned portBASE_TYPE uxQueueLength, 
-                              unsigned portBASE_TYPE uxItemSize 
-                          );
- * 
- * - * Creates a new queue instance. This allocates the storage required by the - * new queue and returns a handle for the queue. - * - * @param uxQueueLength The maximum number of items that the queue can contain. - * - * @param uxItemSize The number of bytes each item in the queue will require. - * Items are queued by copy, not by reference, so this is the number of bytes - * that will be copied for each posted item. Each item on the queue must be - * the same size. - * - * @return If the queue is successfully create then a handle to the newly - * created queue is returned. If the queue cannot be created then 0 is - * returned. - * - * Example usage: -
- struct AMessage
- {
-    portCHAR ucMessageID;
-    portCHAR ucData[ 20 ];
- };
-
- void vATask( void *pvParameters )
- {
- xQueueHandle xQueue1, xQueue2;
-
-    // Create a queue capable of containing 10 unsigned long values.
-    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );
-    if( xQueue1 == 0 )
-    {
-        // Queue was not created and must not be used.
-    }
-
-    // Create a queue capable of containing 10 pointers to AMessage structures.
-    // These should be passed by pointer as they contain a lot of data.
-    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-    if( xQueue2 == 0 )
-    {
-        // Queue was not created and must not be used.
-    }
-
-    // ... Rest of task code.
- }
- 
- * \defgroup xQueueCreate xQueueCreate - * \ingroup QueueManagement - */ -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); - -/** - * queue. h - *
- portBASE_TYPE xQueueSend( 
-                             xQueueHandle xQueue, 
-                             const void * pvItemToQueue, 
-                             portTickType xTicksToWait 
-                         );
- * 
- * - * Post an item on a queue. The item is queued by copy, not by reference. - * This function must not be called from an interrupt service routine. - * See xQueueSendFromISR () for an alternative which may be used in an ISR. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for space to become available on the queue, should it already - * be full. The call will return immediately if this is set to 0. The - * time is defined in tick periods so the constant portTICK_RATE_MS - * should be used to convert to real time if this is required. - * - * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. - * - * Example usage: -
- struct AMessage
- {
-    portCHAR ucMessageID;
-    portCHAR ucData[ 20 ];
- } xMessage;
-
- unsigned portLONG ulVar = 10UL;
-
- void vATask( void *pvParameters )
- {
- xQueueHandle xQueue1, xQueue2;
- struct AMessage *pxMessage;
-
-    // Create a queue capable of containing 10 unsigned long values.
-    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );
-
-    // Create a queue capable of containing 10 pointers to AMessage structures.
-    // These should be passed by pointer as they contain a lot of data.
-    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-
-    // ...
-
-    if( xQueue1 != 0 )
-    {
-        // Send an unsigned long.  Wait for 10 ticks for space to become 
-        // available if necessary.
-        if( xQueueSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )
-        {
-            // Failed to post the message, even after 10 ticks.
-        }
-    }
-
-    if( xQueue2 != 0 )
-    {
-        // Send a pointer to a struct AMessage object.  Don't block if the
-        // queue is already full.
-        pxMessage = & xMessage;
-        xQueueSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );
-    }
-
-	// ... Rest of task code.
- }
- 
- * \defgroup xQueueSend xQueueSend - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); - -/** - * queue. h - *
- portBASE_TYPE xQueueReceive( 
-                                xQueueHandle xQueue, 
-                                void *pvBuffer, 
-                                portTickType xTicksToWait 
-                            );
- * - * Receive an item from a queue. The item is received by copy so a buffer of - * adequate size must be provided. The number of bytes copied into the buffer - * was defined when the queue was created. - * - * This function must not be used in an interrupt service routine. See - * xQueueReceiveFromISR for an alternative that can. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pvBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for an item to receive should the queue be empty at the time - * of the call. The time is defined in tick periods so the constant - * portTICK_RATE_MS should be used to convert to real time if this is required. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: -
- struct AMessage
- {
-    portCHAR ucMessageID;
-    portCHAR ucData[ 20 ];
- } xMessage;
-
- xQueueHandle xQueue;
- 
- // Task to create a queue and post a value.
- void vATask( void *pvParameters )
- {
- struct AMessage *pxMessage;
-
-    // Create a queue capable of containing 10 pointers to AMessage structures.
-    // These should be passed by pointer as they contain a lot of data.
-    xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
-    if( xQueue == 0 )
-    {
-        // Failed to create the queue.
-    }
-
-    // ...
-
-    // Send a pointer to a struct AMessage object.  Don't block if the
-    // queue is already full.
-    pxMessage = & xMessage;
-    xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );
-
-	// ... Rest of task code.
- }
-
- // Task to receive from the queue.
- void vADifferentTask( void *pvParameters )
- {
- struct AMessage *pxRxedMessage;
-
-    if( xQueue != 0 )
-    {
-        // Receive a message on the created queue.  Block for 10 ticks if a
-        // message is not immediately available.
-        if( xQueueReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )
-        {
-            // pcRxedMessage now points to the struct AMessage variable posted
-            // by vATask.
-        }
-    }
-
-	// ... Rest of task code.
- }
- 
- * \defgroup xQueueReceive xQueueReceive - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueReceive( xQueueHandle xQueue, void *pvBuffer, portTickType xTicksToWait ); - -/** - * queue. h - *
unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue );
- * - * Return the number of messages stored in a queue. - * - * @param xQueue A handle to the queue being queried. - * - * @return The number of messages available in the queue. - * - * \page uxQueueMessagesWaiting uxQueueMessagesWaiting - * \ingroup QueueManagement - */ -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue ); - -/** - * queue. h - *
void vQueueDelete( xQueueHandle xQueue );
- * - * Delete a queue - freeing all the memory allocated for storing of items - * placed on the queue. - * - * @param xQueue A handle to the queue to be deleted. - * - * \page vQueueDelete vQueueDelete - * \ingroup QueueManagement - */ -void vQueueDelete( xQueueHandle xQueue ); - -/** - * queue. h - *
- portBASE_TYPE xQueueSendFromISR( 
-                                    xQueueHandle pxQueue, 
-                                    const void *pvItemToQueue, 
-                                    portBASE_TYPE xTaskPreviouslyWoken 
-                                );
- 
- * - * Post an item on a queue. It is safe to use this function from within an - * interrupt service routine. - * - * Items are queued by copy not reference so it is preferable to only - * queue small items, especially when called from an ISR. In most cases - * it would be preferable to store a pointer to the item being queued. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param cTaskPreviouslyWoken This is included so an ISR can post onto - * the same queue multiple times from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. See the file serial .c in the - * PC port for a good example of this mechanism. - * - * @return pdTRUE if a task was woken by posting onto the queue. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage for buffered IO (where the ISR can obtain more than one value - * per call): -
- void vBufferISR( void )
- {
- portCHAR cIn;
- portBASE_TYPE xTaskWokenByPost;
-
-    // We have not woken a task at the start of the ISR.
-    cTaskWokenByPost = pdFALSE;
-
-    // Loop until the buffer is empty.
-    do
-    {
-        // Obtain a byte from the buffer.
-        cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );						
-
-        // Post the byte.  The first time round the loop cTaskWokenByPost
-        // will be pdFALSE.  If the queue send causes a task to wake we do
-        // not want the task to run until we have finished the ISR, so
-        // xQueueSendFromISR does not cause a context switch.  Also we 
-        // don't want subsequent posts to wake any other tasks, so we store
-        // the return value back into cTaskWokenByPost so xQueueSendFromISR
-        // knows not to wake any task the next iteration of the loop.
-        xTaskWokenByPost = xQueueSendFromISR( xRxQueue, &cIn, cTaskWokenByPost );
-
-    } while( portINPUT_BYTE( BUFFER_COUNT ) );
-
-    // Now the buffer is empty we can switch context if necessary.
-    if( cTaskWokenByPost )
-    {
-        taskYIELD ();
-    }
- }
- 
- * - * \defgroup xQueueSendFromISR xQueueSendFromISR - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ); - -/** - * queue. h - *
- portBASE_TYPE xQueueReceiveFromISR( 
-                                       xQueueHandle pxQueue, 
-                                       void *pvBuffer, 
-                                       portBASE_TYPE *pxTaskWoken 
-                                   ); 
- * 
- * - * Receive an item from a queue. It is safe to use this function from within an - * interrupt service routine. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pvBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param pxTaskWoken A task may be blocked waiting for space to become - * available on the queue. If xQueueReceiveFromISR causes such a task to - * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will - * remain unchanged. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: -
- 
- xQueueHandle xQueue;
- 
- // Function to create a queue and post some values.
- void vAFunction( void *pvParameters )
- {
- portCHAR cValueToPost;
- const portTickType xBlockTime = ( portTickType )0xff;
-
-    // Create a queue capable of containing 10 characters.
-    xQueue = xQueueCreate( 10, sizeof( portCHAR ) );
-    if( xQueue == 0 )
-    {
-        // Failed to create the queue.
-    }
-
-    // ...
-
-    // Post some characters that will be used within an ISR.  If the queue
-    // is full then this task will block for xBlockTime ticks.
-    cValueToPost = 'a';
-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
-    cValueToPost = 'b';
-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
-
-    // ... keep posting characters ... this task may block when the queue
-    // becomes full.
-
-    cValueToPost = 'c';
-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
- }
-
- // ISR that outputs all the characters received on the queue. 
- void vISR_Routine( void )
- {
- portBASE_TYPE xTaskWokenByReceive = pdFALSE;
- portCHAR cRxedChar;
-
-    while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
-    {
-        // A character was received.  Output the character now.
-        vOutputCharacter( cRxedChar );
-
-        // If removing the character from the queue woke the task that was 
-        // posting onto the queue cTaskWokenByReceive will have been set to
-        // pdTRUE.  No matter how many times this loop iterates only one
-        // task will be woken.
-    }
-
-    if( cTaskWokenByPost != ( portCHAR ) pdFALSE;
-    {
-        taskYIELD ();
-    }
- }
- 
- * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - - -/* - * The functions defined above are for passing data to and from tasks. The - * functions below are the equivalents for passing data to and from - * co-rtoutines. - * - * These functions are called from the co-routine macro implementation and - * should not be called directly from application code. Instead use the macro - * wrappers defined within croutine.h. - */ -signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ); -signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); -signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ); -signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/semphr.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/semphr.h deleted file mode 100644 index 6d8718d26..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/semphr.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include "queue.h" - -#ifndef SEMAPHORE_H -#define SEMAPHORE_H - -typedef xQueueHandle xSemaphoreHandle; - -#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( unsigned portCHAR ) 1 ) -#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( unsigned portCHAR ) 0 ) -#define semGIVE_BLOCK_TIME ( ( portTickType ) 0 ) - - -/** - * semphr. h - *
vSemaphoreCreateBinary( xSemaphoreHandle xSemaphore )
- * - * Macro that implements a semaphore by using the existing queue mechanism. - * The queue length is 1 as this is a binary semaphore. The data size is 0 - * as we don't want to actually store any data - we just want to know if the - * queue is empty or full. - * - * @param xSemaphore Handle to the created semaphore. Should be of type xSemaphoreHandle. - * - * Example usage: -
- xSemaphoreHandle xSemaphore;
-
- void vATask( void * pvParameters )
- {
-    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
-    // This is a macro so pass the variable in directly.
-    vSemaphoreCreateBinary( xSemaphore );
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.  
-    }
- }
- 
- * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary - * \ingroup Semaphores - */ -#define vSemaphoreCreateBinary( xSemaphore ) { \ - xSemaphore = xQueueCreate( ( unsigned portCHAR ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH ); \ - if( xSemaphore != NULL ) \ - { \ - xSemaphoreGive( xSemaphore ); \ - } \ - } - -/** - * semphr. h - * xSemaphoreTake( - * xSemaphoreHandle xSemaphore, - * portTickType xBlockTime - * ) - * - * Macro to obtain a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (). - * - * @param xSemaphore A handle to the semaphore being obtained. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @param xBlockTime The time in ticks to wait for the semaphore to become - * available. The macro portTICK_RATE_MS can be used to convert this to a - * real time. A block time of zero can be used to poll the semaphore. - * - * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime - * expired without the semaphore becoming available. - * - * Example usage: -
- xSemaphoreHandle xSemaphore = NULL;
-
- // A task that creates a semaphore.
- void vATask( void * pvParameters )
- {
-    // Create the semaphore to guard a shared resource.
-    vSemaphoreCreateBinary( xSemaphore );
- }
-
- // A task that uses the semaphore.
- void vAnotherTask( void * pvParameters )
- {
-    // ... Do other things.
-
-    if( xSemaphore != NULL )
-    {
-        // See if we can obtain the semaphore.  If the semaphore is not available
-        // wait 10 ticks to see if it becomes free.	
-        if( xSemaphoreTake( xSemaphore, ( portTickType ) 10 ) == pdTRUE )
-        {
-            // We were able to obtain the semaphore and can now access the
-            // shared resource.
-
-            // ...
-
-            // We have finished accessing the shared resource.  Release the 
-            // semaphore.
-            xSemaphoreGive( xSemaphore );
-        }
-        else
-        {
-            // We could not obtain the semaphore and can therefore not access
-            // the shared resource safely.
-        }
-    }
- }
- 
- * \defgroup xSemaphoreTake xSemaphoreTake - * \ingroup Semaphores - */ -#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueReceive( ( xQueueHandle ) xSemaphore, NULL, xBlockTime ) - -/** - * semphr. h - *
xSemaphoreGive( xSemaphoreHandle xSemaphore )
- * - * Macro to release a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (), and obtained using sSemaphoreTake (). - * - * This must not be used from an ISR. See xSemaphoreGiveFromISR () for - * an alternative which can be used from an ISR. - * - * @param xSemaphore A handle to the semaphore being released. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. - * Semaphores are implemented using queues. An error can occur if there is - * no space on the queue to post a message - indicating that the - * semaphore was not first obtained correctly. - * - * Example usage: -
- xSemaphoreHandle xSemaphore = NULL;
-
- void vATask( void * pvParameters )
- {
-    // Create the semaphore to guard a shared resource.
-    vSemaphoreCreateBinary( xSemaphore );
-
-    if( xSemaphore != NULL )
-    {
-        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
-        {
-            // We would expect this call to fail because we cannot give
-            // a semaphore without first "taking" it!
-        }
-
-        // Obtain the semaphore - don't block if the semaphore is not
-        // immediately available.
-        if( xSemaphoreTake( xSemaphore, ( portTickType ) 0 ) )
-        {
-            // We now have the semaphore and can access the shared resource.
-
-            // ...
-
-            // We have finished accessing the shared resource so can free the
-            // semaphore.
-            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
-            {
-                // We would not expect this call to fail because we must have
-                // obtained the semaphore to get here.
-            }
-        }
-    }
- }
- 
- * \defgroup xSemaphoreGive xSemaphoreGive - * \ingroup Semaphores - */ -#define xSemaphoreGive( xSemaphore ) xQueueSend( ( xQueueHandle ) xSemaphore, NULL, semGIVE_BLOCK_TIME ) - -/** - * semphr. h - *
- xSemaphoreGiveFromISR( 
-                          xSemaphoreHandle xSemaphore, 
-                          portSHORT sTaskPreviouslyWoken 
-                      )
- * - * Macro to release a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (), and obtained using xSemaphoreTake (). - * - * This macro can be used from an ISR. - * - * @param xSemaphore A handle to the semaphore being released. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @param sTaskPreviouslyWoken This is included so an ISR can make multiple calls - * to xSemaphoreGiveFromISR () from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. See the file serial .c in the - * PC port for a good example of using xSemaphoreGiveFromISR (). - * - * @return pdTRUE if a task was woken by releasing the semaphore. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage: -
- #define LONG_TIME 0xffff
- #define TICKS_TO_WAIT	10
- xSemaphoreHandle xSemaphore = NULL;
-
- // Repetitive task.
- void vATask( void * pvParameters )
- {
-    for( ;; )
-    {
-        // We want this task to run every 10 ticks or a timer.  The semaphore 
-        // was created before this task was started
-
-        // Block waiting for the semaphore to become available.
-        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
-        {
-            // It is time to execute.
-
-            // ...
-
-            // We have finished our task.  Return to the top of the loop where
-            // we will block on the semaphore until it is time to execute 
-            // again.
-        }
-    }
- }
-
- // Timer ISR
- void vTimerISR( void * pvParameters )
- {
- static unsigned portCHAR ucLocalTickCount = 0;
-
-    // A timer tick has occurred.
-
-    // ... Do other time functions.
-
-    // Is it time for vATask () to run?
-    ucLocalTickCount++;
-    if( ucLocalTickCount >= TICKS_TO_WAIT )
-    {
-        // Unblock the task by releasing the semaphore.
-        xSemaphoreGive( xSemaphore );
-
-        // Reset the count so we release the semaphore again in 10 ticks time.
-        ucLocalTickCount = 0;
-    }
- }
- 
- * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR - * \ingroup Semaphores - */ -#define xSemaphoreGiveFromISR( xSemaphore, xTaskPreviouslyWoken ) xQueueSendFromISR( ( xQueueHandle ) xSemaphore, NULL, xTaskPreviouslyWoken ) - - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/serial.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/serial.h deleted file mode 100644 index 19634d836..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/serial.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef SERIAL_COMMS_H -#define SERIAL_COMMS_H - -typedef void * xComPortHandle; - -typedef enum -{ - serCOM1, - serCOM2, - serCOM3, - serCOM4, - serCOM5, - serCOM6, - serCOM7, - serCOM8 -} eCOMPort; - -typedef enum -{ - serNO_PARITY, - serODD_PARITY, - serEVEN_PARITY, - serMARK_PARITY, - serSPACE_PARITY -} eParity; - -typedef enum -{ - serSTOP_1, - serSTOP_2 -} eStopBits; - -typedef enum -{ - serBITS_5, - serBITS_6, - serBITS_7, - serBITS_8 -} eDataBits; - -typedef enum -{ - ser50, - ser75, - ser110, - ser134, - ser150, - ser200, - ser300, - ser600, - ser1200, - ser1800, - ser2400, - ser4800, - ser9600, - ser19200, - ser38400, - ser57600, - ser115200 -} eBaud; - -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ); -xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ); -void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ); -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ); -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ); -portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ); -void vSerialClose( xComPortHandle xPort ); - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/task.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/task.h deleted file mode 100644 index d280110fc..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/include/task.h +++ /dev/null @@ -1,926 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef TASK_H -#define TASK_H - -#include "portable.h" -#include "list.h" - -/*----------------------------------------------------------- - * MACROS AND DEFINITIONS - *----------------------------------------------------------*/ - -#define tskKERNEL_VERSION_NUMBER "V4.0.5" - -/** - * task. h - * - * Type by which tasks are referenced. For example, a call to xTaskCreate - * returns (via a pointer parameter) an xTaskHandle variable that can then - * be used as a parameter to vTaskDelete to delete the task. - * - * \page xTaskHandle xTaskHandle - * \ingroup Tasks - */ -typedef void * xTaskHandle; - -/* - * Defines the priority used by the idle task. This must not be modified. - * - * \ingroup TaskUtils - */ -#define tskIDLE_PRIORITY ( ( unsigned portBASE_TYPE ) 0 ) - -/** - * task. h - * - * Macro for forcing a context switch. - * - * \page taskYIELD taskYIELD - * \ingroup SchedulerControl - */ -#define taskYIELD() portYIELD() - -/** - * task. h - * - * Macro to mark the start of a critical code region. Preemptive context - * switches cannot occur when in a critical region. - * - * NOTE: This may alter the stack (depending on the portable implementation) - * so must be used with care! - * - * \page taskENTER_CRITICAL taskENTER_CRITICAL - * \ingroup SchedulerControl - */ -#define taskENTER_CRITICAL() portENTER_CRITICAL() - -/** - * task. h - * - * Macro to mark the end of a critical code region. Preemptive context - * switches cannot occur when in a critical region. - * - * NOTE: This may alter the stack (depending on the portable implementation) - * so must be used with care! - * - * \page taskEXIT_CRITICAL taskEXIT_CRITICAL - * \ingroup SchedulerControl - */ -#define taskEXIT_CRITICAL() portEXIT_CRITICAL() - -/** - * task. h - * - * Macro to disable all maskable interrupts. - * - * \page taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS - * \ingroup SchedulerControl - */ -#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() - -/** - * task. h - * - * Macro to enable microcontroller interrupts. - * - * \page taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS - * \ingroup SchedulerControl - */ -#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() - - -/*----------------------------------------------------------- - * TASK CREATION API - *----------------------------------------------------------*/ - -/** - * task. h - *
- portBASE_TYPE xTaskCreate(
-                              pdTASK_CODE pvTaskCode,
-                              const portCHAR * const pcName,
-                              unsigned portSHORT usStackDepth,
-                              void *pvParameters,
-                              unsigned portBASE_TYPE uxPriority,
-                              xTaskHandle *pvCreatedTask
-                          );
- * - * Create a new task and add it to the list of tasks that are ready to run. - * - * @param pvTaskCode Pointer to the task entry function. Tasks - * must be implemented to never return (i.e. continuous loop). - * - * @param pcName A descriptive name for the task. This is mainly used to - * facilitate debugging. Max length defined by tskMAX_TASK_NAME_LEN - default - * is 16. - * - * @param usStackDepth The size of the task stack specified as the number of - * variables the stack can hold - not the number of bytes. For example, if - * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes - * will be allocated for stack storage. - * - * @param pvParameters Pointer that will be used as the parameter for the task - * being created. - * - * @param uxPriority The priority at which the task should run. - * - * @param pvCreatedTask Used to pass back a handle by which the created task - * can be referenced. - * - * @return pdPASS if the task was successfully created and added to a ready - * list, otherwise an error code defined in the file errors. h - * - * Example usage: -
- // Task to be created.
- void vTaskCode( void * pvParameters )
- {
-     for( ;; )
-     {
-         // Task code goes here.
-     }
- }
-
- // Function that creates a task.
- void vOtherFunction( void )
- {
- unsigned char ucParameterToPass;
- xTaskHandle xHandle;
-		
-     // Create the task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
-		
-     // Use the handle to delete the task.
-     vTaskDelete( xHandle );
- }
-   
- * \defgroup xTaskCreate xTaskCreate - * \ingroup Tasks - */ -signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pvCreatedTask ); - -/** - * task. h - *
void vTaskDelete( xTaskHandle pxTask );
- * - * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Remove a task from the RTOS real time kernels management. The task being - * deleted will be removed from all ready, blocked, suspended and event lists. - * - * NOTE: The idle task is responsible for freeing the kernel allocated - * memory from tasks that have been deleted. It is therefore important that - * the idle task is not starved of microcontroller processing time if your - * application makes any calls to vTaskDelete (). Memory allocated by the - * task code is not automatically freed, and should be freed before the task - * is deleted. - * - * See the demo application file death.c for sample code that utilises - * vTaskDelete (). - * - * @param pxTask The handle of the task to be deleted. Passing NULL will - * cause the calling task to be deleted. - * - * Example usage: -
- void vOtherFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create the task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-		
-     // Use the handle to delete the task.
-     vTaskDelete( xHandle );
- }
-   
- * \defgroup vTaskDelete vTaskDelete - * \ingroup Tasks - */ -void vTaskDelete( xTaskHandle pxTask ); - - -/*----------------------------------------------------------- - * TASK CONTROL API - *----------------------------------------------------------*/ - -/** - * task. h - *
void vTaskDelay( portTickType xTicksToDelay );
- * - * Delay a task for a given number of ticks. The actual time that the - * task remains blocked depends on the tick rate. The constant - * portTICK_RATE_MS can be used to calculate real time from the tick - * rate - with the resolution of one tick period. - * - * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * @param xTicksToDelay The amount of time, in tick periods, that - * the calling task should block. - * - * Example usage: -
- // Wait 10 ticks before performing an action.
- // NOTE:
- // This is for demonstration only and would be better achieved
- // using vTaskDelayUntil ().
- void vTaskFunction( void * pvParameters )
- {
- portTickType xDelay, xNextTime;
-
-     // Calc the time at which we want to perform the action
-     // next.
-     xNextTime = xTaskGetTickCount () + ( portTickType ) 10;
-
-     for( ;; )
-     {
-         xDelay = xNextTime - xTaskGetTickCount ();
-         xNextTime += ( portTickType ) 10;
-
-         // Guard against overflow
-         if( xDelay <= ( portTickType ) 10 )
-         {
-             vTaskDelay( xDelay );
-         }
-
-         // Perform action here.
-     }
- }
-   
- * \defgroup vTaskDelay vTaskDelay - * \ingroup TaskCtrl - */ -void vTaskDelay( portTickType xTicksToDelay ); - -/** - * task. h - *
void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement );
- * - * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Delay a task until a specified time. This function can be used by cyclical - * tasks to ensure a constant execution frequency. - * - * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will - * cause a task to block for the specified number of ticks from the time vTaskDelay () is - * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed - * execution frequency as the time between a task starting to execute and that task - * calling vTaskDelay () may not be fixed [the task may take a different path though the - * code between calls, or may get interrupted or preempted a different number of times - * each time it executes]. - * - * Whereas vTaskDelay () specifies a wake time relative to the time at which the function - * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to - * unblock. - * - * The constant portTICK_RATE_MS can be used to calculate real time from the tick - * rate - with the resolution of one tick period. - * - * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the - * task was last unblocked. The variable must be initialised with the current time - * prior to its first use (see the example below). Following this the variable is - * automatically updated within vTaskDelayUntil (). - * - * @param xTimeIncrement The cycle time period. The task will be unblocked at - * time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the - * same xTimeIncrement parameter value will cause the task to execute with - * a fixed interface period. - * - * Example usage: -
- // Perform an action every 10 ticks.
- void vTaskFunction( void * pvParameters )
- {
- portTickType xLastWakeTime;
- const portTickType xFrequency = 10;
-
-     // Initialise the xLastWakeTime variable with the current time.
-     xLastWakeTime = xTaskGetTickCount ();
-     for( ;; )
-     {
-         // Wait for the next cycle.
-         vTaskDelayUntil( &xLastWakeTime, xFrequency );
-
-         // Perform action here.
-     }
- }
-   
- * \defgroup vTaskDelayUntil vTaskDelayUntil - * \ingroup TaskCtrl - */ -void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement ); - -/** - * task. h - *
unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask );
- * - * INCLUDE_xTaskPriorityGet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Obtain the priority of any task. - * - * @param pxTask Handle of the task to be queried. Passing a NULL - * handle results in the priority of the calling task being returned. - * - * @return The priority of pxTask. - * - * Example usage: -
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create a task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-		
-     // ...
-
-     // Use the handle to obtain the priority of the created task.
-     // It was created with tskIDLE_PRIORITY, but may have changed
-     // it itself.
-     if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
-     {
-         // The task has changed it's priority.
-     }
-
-     // ...
-
-     // Is our priority higher than the created task?
-     if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
-     {
-         // Our priority (obtained using NULL handle) is higher.
-     }
- }
-   
- * \defgroup uxTaskPriorityGet uxTaskPriorityGet - * \ingroup TaskCtrl - */ -unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ); - -/** - * task. h - *
void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );
- * - * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Set the priority of any task. - * - * A context switch will occur before the function returns if the priority - * being set is higher than the currently executing task. - * - * @param pxTask Handle to the task for which the priority is being set. - * Passing a NULL handle results in the priority of the calling task being set. - * - * @param uxNewPriority The priority to which the task will be set. - * - * Example usage: -
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create a task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-     // ...
-
-     // Use the handle to raise the priority of the created task.
-     vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
-
-     // ...
-
-     // Use a NULL handle to raise our priority to the same value.
-     vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
- }
-   
- * \defgroup vTaskPrioritySet vTaskPrioritySet - * \ingroup TaskCtrl - */ -void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ); - -/** - * task. h - *
void vTaskSuspend( xTaskHandle pxTaskToSuspend );
- * - * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Suspend any task. When suspended a task will never get any microcontroller - * processing time, no matter what its priority. - * - * Calls to vTaskSuspend are not accumulative - - * i.e. calling vTaskSuspend () twice on the same task still only requires one - * call to vTaskResume () to ready the suspended task. - * - * @param pxTaskToSuspend Handle to the task being suspended. Passing a NULL - * handle will cause the calling task to be suspended. - * - * Example usage: -
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create a task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-		
-     // ...
-
-     // Use the handle to suspend the created task.
-     vTaskSuspend( xHandle );
-
-     // ...
-		
-     // The created task will not run during this period, unless
-     // another task calls vTaskResume( xHandle ).
-		
-     //...
-		
-
-     // Suspend ourselves.
-     vTaskSuspend( NULL );
-
-     // We cannot get here unless another task calls vTaskResume
-     // with our handle as the parameter.
- }
-   
- * \defgroup vTaskSuspend vTaskSuspend - * \ingroup TaskCtrl - */ -void vTaskSuspend( xTaskHandle pxTaskToSuspend ); - -/** - * task. h - *
void vTaskResume( xTaskHandle pxTaskToResume );
- * - * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Resumes a suspended task. - * - * A task that has been suspended by one of more calls to vTaskSuspend () - * will be made available for running again by a single call to - * vTaskResume (). - * - * @param pxTaskToResume Handle to the task being readied. - * - * Example usage: -
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create a task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-		
-     // ...
-
-     // Use the handle to suspend the created task.
-     vTaskSuspend( xHandle );
-
-     // ...
-	
-     // The created task will not run during this period, unless
-     // another task calls vTaskResume( xHandle ).
-		
-     //...
-		
-
-     // Resume the suspended task ourselves.
-     vTaskResume( xHandle );
-
-     // The created task will once again get microcontroller processing
-     // time in accordance with it priority within the system.
- }
-   
- * \defgroup vTaskResume vTaskResume - * \ingroup TaskCtrl - */ -void vTaskResume( xTaskHandle pxTaskToResume ); - -/** - * task. h - *
void xTaskResumeFromISR( xTaskHandle pxTaskToResume );
- * - * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be - * available. See the configuration section for more information. - * - * An implementation of vTaskResume() that can be called from within an ISR. - * - * A task that has been suspended by one of more calls to vTaskSuspend () - * will be made available for running again by a single call to - * xTaskResumeFromISR (). - * - * @param pxTaskToResume Handle to the task being readied. - * - * \defgroup vTaskResumeFromISR vTaskResumeFromISR - * \ingroup TaskCtrl - */ -portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ); - -/*----------------------------------------------------------- - * SCHEDULER CONTROL - *----------------------------------------------------------*/ - -/** - * task. h - *
void vTaskStartScheduler( void );
- * - * Starts the real time kernel tick processing. After calling the kernel - * has control over which tasks are executed and when. This function - * does not return until an executing task calls vTaskEndScheduler (). - * - * At least one task should be created via a call to xTaskCreate () - * before calling vTaskStartScheduler (). The idle task is created - * automatically when the first application task is created. - * - * See the demo application file main.c for an example of creating - * tasks and starting the kernel. - * - * Example usage: -
- void vAFunction( void )
- {
-     // Create at least one task before starting the kernel.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
-     // Start the real time kernel with preemption.
-     vTaskStartScheduler ();
-
-     // Will not get here unless a task calls vTaskEndScheduler ()
- }
-   
- * - * \defgroup vTaskStartScheduler vTaskStartScheduler - * \ingroup SchedulerControl - */ -void vTaskStartScheduler( void ); - -/** - * task. h - *
void vTaskEndScheduler( void );
- * - * Stops the real time kernel tick. All created tasks will be automatically - * deleted and multitasking (either preemptive or cooperative) will - * stop. Execution then resumes from the point where vTaskStartScheduler () - * was called, as if vTaskStartScheduler () had just returned. - * - * See the demo application file main. c in the demo/PC directory for an - * example that uses vTaskEndScheduler (). - * - * vTaskEndScheduler () requires an exit function to be defined within the - * portable layer (see vPortEndScheduler () in port. c for the PC port). This - * performs hardware specific operations such as stopping the kernel tick. - * - * vTaskEndScheduler () will cause all of the resources allocated by the - * kernel to be freed - but will not free resources allocated by application - * tasks. - * - * Example usage: -
- void vTaskCode( void * pvParameters )
- {
-     for( ;; )
-     {
-         // Task code goes here.
-
-         // At some point we want to end the real time kernel processing
-         // so call ...
-         vTaskEndScheduler ();
-     }
- }
-
- void vAFunction( void )
- {
-     // Create at least one task before starting the kernel.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
-     // Start the real time kernel with preemption.
-     vTaskStartScheduler ();
-
-     // Will only get here when the vTaskCode () task has called
-     // vTaskEndScheduler ().  When we get here we are back to single task
-     // execution.
- }
-   
- * - * \defgroup vTaskEndScheduler vTaskEndScheduler - * \ingroup SchedulerControl - */ -void vTaskEndScheduler( void ); - -/** - * task. h - *
void vTaskSuspendAll( void );
- * - * Suspends all real time kernel activity while keeping interrupts (including the - * kernel tick) enabled. - * - * After calling vTaskSuspendAll () the calling task will continue to execute - * without risk of being swapped out until a call to xTaskResumeAll () has been - * made. - * - * Example usage: -
- void vTask1( void * pvParameters )
- {
-     for( ;; )
-     {
-         // Task code goes here.
-
-         // ...
-
-         // At some point the task wants to perform a long operation during
-         // which it does not want to get swapped out.  It cannot use
-         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
-         // operation may cause interrupts to be missed - including the
-         // ticks.
-
-         // Prevent the real time kernel swapping out the task.
-         vTaskSuspendAll ();
-
-         // Perform the operation here.  There is no need to use critical
-         // sections as we have all the microcontroller processing time.
-         // During this time interrupts will still operate and the kernel
-         // tick count will be maintained.
-
-         // ...
-
-         // The operation is complete.  Restart the kernel.
-         xTaskResumeAll ();
-     }
- }
-   
- * \defgroup vTaskSuspendAll vTaskSuspendAll - * \ingroup SchedulerControl - */ -void vTaskSuspendAll( void ); - -/** - * task. h - *
portCHAR xTaskResumeAll( void );
- * - * Resumes real time kernel activity following a call to vTaskSuspendAll (). - * After a call to vTaskSuspendAll () the kernel will take control of which - * task is executing at any time. - * - * @return If resuming the scheduler caused a context switch then pdTRUE is - * returned, otherwise pdFALSE is returned. - * - * Example usage: -
- void vTask1( void * pvParameters )
- {
-     for( ;; )
-     {
-         // Task code goes here.
-
-         // ...
-
-         // At some point the task wants to perform a long operation during
-         // which it does not want to get swapped out.  It cannot use
-         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
-         // operation may cause interrupts to be missed - including the
-         // ticks.
-
-         // Prevent the real time kernel swapping out the task.
-         vTaskSuspendAll ();
-
-         // Perform the operation here.  There is no need to use critical
-         // sections as we have all the microcontroller processing time.
-         // During this time interrupts will still operate and the real
-         // time kernel tick count will be maintained.
-
-         // ...
-
-         // The operation is complete.  Restart the kernel.  We want to force
-         // a context switch - but there is no point if resuming the scheduler
-         // caused a context switch already.
-         if( !xTaskResumeAll () )
-         {
-              taskYIELD ();
-         }
-     }
- }
-   
- * \defgroup xTaskResumeAll xTaskResumeAll - * \ingroup SchedulerControl - */ -signed portBASE_TYPE xTaskResumeAll( void ); - - -/*----------------------------------------------------------- - * TASK UTILITIES - *----------------------------------------------------------*/ - -/** - * task. h - *
volatile portTickType xTaskGetTickCount( void );
- * - * @return The count of ticks since vTaskStartScheduler was called. - * - * \page xTaskGetTickCount xTaskGetTickCount - * \ingroup TaskUtils - */ -portTickType xTaskGetTickCount( void ); - -/** - * task. h - *
unsigned portSHORT uxTaskGetNumberOfTasks( void );
- * - * @return The number of tasks that the real time kernel is currently managing. - * This includes all ready, blocked and suspended tasks. A task that - * has been deleted but not yet freed by the idle task will also be - * included in the count. - * - * \page uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks - * \ingroup TaskUtils - */ -unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ); - -/** - * task. h - *
void vTaskList( portCHAR *pcWriteBuffer );
- * - * configUSE_TRACE_FACILITY, INCLUDE_vTaskDelete and INCLUDE_vTaskSuspend - * must all be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * NOTE: This function will disable interrupts for its duration. It is - * not intended for normal application runtime use but as a debug aid. - * - * Lists all the current tasks, along with their current state and stack - * usage high water mark. - * - * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or - * suspended ('S'). - * - * @param pcWriteBuffer A buffer into which the above mentioned details - * will be written, in ascii form. This buffer is assumed to be large - * enough to contain the generated report. Approximately 40 bytes per - * task should be sufficient. - * - * \page vTaskList vTaskList - * \ingroup TaskUtils - */ -void vTaskList( signed portCHAR *pcWriteBuffer ); - -/** - * task. h - *
void vTaskStartTrace( portCHAR * pcBuffer, unsigned portBASE_TYPE uxBufferSize );
- * - * Starts a real time kernel activity trace. The trace logs the identity of - * which task is running when. - * - * The trace file is stored in binary format. A separate DOS utility called - * convtrce.exe is used to convert this into a tab delimited text file which - * can be viewed and plotted in a spread sheet. - * - * @param pcBuffer The buffer into which the trace will be written. - * - * @param ulBufferSize The size of pcBuffer in bytes. The trace will continue - * until either the buffer in full, or ulTaskEndTrace () is called. - * - * \page vTaskStartTrace vTaskStartTrace - * \ingroup TaskUtils - */ -void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ); - -/** - * task. h - *
unsigned portLONG ulTaskEndTrace( void );
- * - * Stops a kernel activity trace. See vTaskStartTrace (). - * - * @return The number of bytes that have been written into the trace buffer. - * - * \page usTaskEndTrace usTaskEndTrace - * \ingroup TaskUtils - */ -unsigned portLONG ulTaskEndTrace( void ); - - -/*----------------------------------------------------------- - * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES - *----------------------------------------------------------*/ - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY - * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS - * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * Called from the real time kernel tick (either preemptive or cooperative), - * this increments the tick count and checks if any tasks that are blocked - * for a finite period required removing from a blocked list and placing on - * a ready list. - */ -inline void vTaskIncrementTick( void ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. - * - * Removes the calling task from the ready list and places it both - * on the list of tasks waiting for a particular event, and the - * list of delayed tasks. The task will be removed from both lists - * and replaced on the ready list should either the event occur (and - * there be no higher priority tasks waiting on the same event) or - * the delay period expires. - * - * @param pxEventList The list containing tasks that are blocked waiting - * for the event to occur. - * - * @param xTicksToWait The maximum amount of time that the task should wait - * for the event to occur. This is specified in kernel ticks,the constant - * portTICK_RATE_MS can be used to convert kernel ticks into a real time - * period. - */ -void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. - * - * Removes a task from both the specified event list and the list of blocked - * tasks, and places it on a ready queue. - * - * xTaskRemoveFromEventList () will be called if either an event occurs to - * unblock a task, or the block timeout period expires. - * - * @return pdTRUE if the task being removed has a higher priority than the task - * making the call, otherwise pdFALSE. - */ -signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * INCLUDE_vTaskCleanUpResources and INCLUDE_vTaskSuspend must be defined as 1 - * for this function to be available. - * See the configuration section for more information. - * - * Empties the ready and delayed queues of task control blocks, freeing the - * memory allocated for the task control block and task stacks as it goes. - */ -void vTaskCleanUpResources( void ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY - * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS - * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * Sets the pointer to the current TCB to the TCB of the highest priority task - * that is ready to run. - */ -void vTaskSwitchContext( void ); - -/* - * Return the handle of the calling task. - */ -xTaskHandle xTaskGetCurrentTaskHandle( void ); - - -#endif /* TASK_H */ - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/list.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/list.c deleted file mode 100644 index 4a6c536a7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/list.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.2.0 - - + Removed the volatile modifier from the function parameters. This was - only ever included to prevent compiler warnings. Now warnings are - removed by casting parameters where the calls are made. - - + prvListGetOwnerOfNextEntry() and prvListGetOwnerOfHeadEntry() have been - removed from the c file and added as macros to the h file. - - + uxNumberOfItems has been added to the list structure. This removes the - need for a pointer comparison when checking if a list is empty, and so - is slightly faster. - - + Removed the NULL check in vListRemove(). This makes the call faster but - necessitates any application code utilising the list implementation to - ensure NULL pointers are not passed. - -Changes from V2.0.0 - - + Double linked the lists to allow faster removal item removal. - -Changes from V2.6.1 - - + Make use of the new portBASE_TYPE definition where ever appropriate. - -Changes from V3.0.0 - - + API changes as described on the FreeRTOS.org WEB site. - -Changes from V3.2.4 - - + Removed the pxHead member of the xList structure. This always pointed - to the same place so has been removed to free a few bytes of RAM. - - + Introduced the xMiniListItem structure that does not include the - xListItem members that are not required by the xListEnd member of a list. - Again this was done to reduce RAM usage. - - + Changed the volatile definitions of some structure members to clean up - the code where the list structures are used. - -Changes from V4.0.4 - - + Optimised vListInsert() in the case when the wake time is the maximum - tick count value. -*/ - -#include -#include "FreeRTOS.h" -#include "list.h" - -/*----------------------------------------------------------- - * PUBLIC LIST API documented in list.h - *----------------------------------------------------------*/ - -void vListInitialise( xList *pxList ) -{ - /* The list structure contains a list item which is used to mark the - end of the list. To initialise the list the list end is inserted - as the only list entry. */ - pxList->pxIndex = ( xListItem * ) &( pxList->xListEnd ); - - /* The list end value is the highest possible value in the list to - ensure it remains at the end of the list. */ - pxList->xListEnd.xItemValue = portMAX_DELAY; - - /* The list end next and previous pointers point to itself so we know - when the list is empty. */ - pxList->xListEnd.pxNext = ( xListItem * ) &( pxList->xListEnd ); - pxList->xListEnd.pxPrevious = ( xListItem * ) &( pxList->xListEnd ); - - pxList->uxNumberOfItems = 0; -} -/*-----------------------------------------------------------*/ - -void vListInitialiseItem( xListItem *pxItem ) -{ - /* Make sure the list item is not recorded as being on a list. */ - pxItem->pvContainer = NULL; -} -/*-----------------------------------------------------------*/ - -void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ) -{ -volatile xListItem * pxIndex; - - /* Insert a new list item into pxList, but rather than sort the list, - makes the new list item the last item to be removed by a call to - pvListGetOwnerOfNextEntry. This means it has to be the item pointed to by - the pxIndex member. */ - pxIndex = pxList->pxIndex; - - pxNewListItem->pxNext = pxIndex->pxNext; - pxNewListItem->pxPrevious = pxList->pxIndex; - pxIndex->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; - pxIndex->pxNext = ( volatile xListItem * ) pxNewListItem; - pxList->pxIndex = ( volatile xListItem * ) pxNewListItem; - - /* Remember which list the item is in. */ - pxNewListItem->pvContainer = ( void * ) pxList; - - ( pxList->uxNumberOfItems )++; -} -/*-----------------------------------------------------------*/ - -void vListInsert( xList *pxList, xListItem *pxNewListItem ) -{ -volatile xListItem *pxIterator; -portTickType xValueOfInsertion; - - /* Insert the new list item into the list, sorted in ulListItem order. */ - xValueOfInsertion = pxNewListItem->xItemValue; - - /* If the list already contains a list item with the same item value then - the new list item should be placed after it. This ensures that TCB's which - are stored in ready lists (all of which have the same ulListItem value) - get an equal share of the CPU. However, if the xItemValue is the same as - the back marker the iteration loop below will not end. This means we need - to guard against this by checking the value first and modifying the - algorithm slightly if necessary. */ - if( xValueOfInsertion == portMAX_DELAY ) - { - pxIterator = pxList->xListEnd.pxPrevious; - } - else - { - for( pxIterator = ( xListItem * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) - { - /* There is nothing to do here, we are just iterating to the - wanted insertion position. */ - } - } - - pxNewListItem->pxNext = pxIterator->pxNext; - pxNewListItem->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; - pxNewListItem->pxPrevious = pxIterator; - pxIterator->pxNext = ( volatile xListItem * ) pxNewListItem; - - /* Remember which list the item is in. This allows fast removal of the - item later. */ - pxNewListItem->pvContainer = ( void * ) pxList; - - ( pxList->uxNumberOfItems )++; -} -/*-----------------------------------------------------------*/ - -void vListRemove( xListItem *pxItemToRemove ) -{ -xList * pxList; - - pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; - pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; - - /* The list item knows which list it is in. Obtain the list from the list - item. */ - pxList = ( xList * ) pxItemToRemove->pvContainer; - - /* Make sure the index is left pointing to a valid item. */ - if( pxList->pxIndex == pxItemToRemove ) - { - pxList->pxIndex = pxItemToRemove->pxPrevious; - } - - pxItemToRemove->pvContainer = NULL; - ( pxList->uxNumberOfItems )--; -} -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/portable/CodeWarrior/MCF5235/port.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/portable/CodeWarrior/MCF5235/port.c deleted file mode 100644 index 1bf51984a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/portable/CodeWarrior/MCF5235/port.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. - MCF5235 Port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* ----------------------- Stamdard cludes --------------------------------- */ -#include - -/* ----------------------- FreeRTOS includes ------------------------------- */ -#include "FreeRTOS.h" -#include "FreeRTOSConfig.h" -#include "task.h" - -/* ----------------------- System includes --------------------------------- */ -#include "port.h" -#include "m523xbcc.h" - -/* ------------------------ Defines --------------------------------------- */ -#define portVECTOR_TABLE __VECTOR_RAM -#define portVECTOR_SYSCALL ( 32 + portTRAP_YIELD ) -#define portVECTOR_TIMER ( 64 + 36 ) - -#define MCF_PIT_PRESCALER 512UL -#define MCF_PIT_TIMER_TICKS ( FSYS_2 / MCF_PIT_PRESCALER ) -#define MCF_PIT_MODULUS_REGISTER(freq) ( MCF_PIT_TIMER_TICKS / ( freq ) - 1UL) - -#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) -#define portINITIAL_CRITICAL_NESTING ( ( unsigned portLONG ) 10 ) - -#define TIMER_RESET_ASM_IMPL \ - lea __IPSBAR,a0; \ - adda.l #0x150000,a0; \ - move.w (a0),d1; \ - moveq #0,d0; \ - move.w d1,d0; \ - ori.l #0x4,d0; \ - move.w d0,(a0) - -/* ------------------------ Global variables ------------------------------ */ -extern volatile void *pxCurrentTCB; - -/* ------------------------ Static variables ------------------------------ */ -volatile unsigned portLONG ulCriticalNesting = portINITIAL_CRITICAL_NESTING; - -/* ------------------------ Static functions ------------------------------ */ - -/* ------------------------ Start implementation -------------------------- */ - -portSTACK_TYPE * -pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ - /* Place the parameter on the stack in the expected location. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; - pxTopOfStack--; - - /* Place dummy return address on stack. Tasks should never terminate so - * we can set this to anything. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0; - pxTopOfStack--; - - /* Create a Motorola Coldfire exception stack frame. First comes the return - * address. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode; - pxTopOfStack--; - - /* Format, fault-status, vector number for exception stack frame. Task - * run in supervisor mode. */ - *pxTopOfStack = 0x40002000UL | ( portVECTOR_SYSCALL + 32 ) << 18; - pxTopOfStack--; - - /* Set the initial critical section nesting counter to zero. This value - * is used to restore the value of ulCriticalNesting. */ - *pxTopOfStack = 0; - *pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xA6; /* A6 / FP */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA5; /* A5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA4; /* A4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA3; /* A3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA2; /* A2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA1; /* A1 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA0; /* A0 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD7; /* D7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD6; /* D6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD5; /* D5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD4; /* D4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD3; /* D3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD2; /* D2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD1; /* D1 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD0; /* D0 */ - - return pxTopOfStack; -} - -/* - * Called by portYIELD() or taskYIELD() to manually force a context switch. - */ -asm void -prvPortYield( void ) -{ - move.w #0x2700, sr; - /* Perform the context switch. First save the context of the current task. */ - portSAVE_CONTEXT_IMPL( ); - /* Find the highest priority task that is ready to run. */ - jsr vTaskSwitchContext; - /* Restore the context of the new task. */ - portRESTORE_CONTEXT_IMPL( ); -} - -#if configUSE_PREEMPTION == 0 -/* - * The ISR used for the scheduler tick depends on whether the cooperative or - * the preemptive scheduler is being used. - */ -__declspec( interrupt ) -static void prvPortPreemptiveTick( void ) -{ - /* The cooperative scheduler requires a normal IRQ service routine to - * simply increment the system tick. - */ - vTaskIncrementTick( ); - MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF; -} - -#else - -asm void -prvPortPreemptiveTick( ) -{ - move.w #0x2700, sr; - /* Perform the context switch. First save the context of the current task. */ - portSAVE_CONTEXT_IMPL( ); - TIMER_RESET_ASM_IMPL; - jsr vTaskIncrementTick; - /* Find the highest priority task that is ready to run. */ - jsr vTaskSwitchContext; - /* Restore the context of the new task. */ - portRESTORE_CONTEXT_IMPL( ); -} - -#endif - -void -vPortEnterCritical( ) -{ - /* FIXME: We should store the old IPL here - How are we supposed to do - * this. - */ - ( void )portSET_IPL( portIPL_MAX ); - - /* Now interrupts are disabled ulCriticalNesting can be accessed - * directly. Increment ulCriticalNesting to keep a count of how many times - * portENTER_CRITICAL() has been called. */ - ulCriticalNesting++; -} - -void -vPortExitCritical( ) -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - ( void )portSET_IPL( 0 ); - } - } -} - -portBASE_TYPE -xPortStartScheduler( void ) -{ - extern void ( *portVECTOR_TABLE[] ) ( ); - - /* Add entry in vector table for yield system call. */ - portVECTOR_TABLE[portVECTOR_SYSCALL] = prvPortYield; - /* Add entry in vector table for periodic timer. */ - portVECTOR_TABLE[portVECTOR_TIMER] = prvPortPreemptiveTick; - - /* Configure the timer for the system clock. */ - if( configTICK_RATE_HZ > 0 ) - { - /* Configure prescaler */ - MCF_PIT_PCSR0 = MCF_PIT_PCSR_PRE( 0x9 ) | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_OVW; - /* Initialize the periodic timer interrupt. */ - MCF_PIT_PMR0 = MCF_PIT_MODULUS_REGISTER( configTICK_RATE_HZ ); - /* Configure interrupt priority and level and unmask interrupt. */ - MCF_INTC0_ICR36 = MCF_INTC0_ICRn_IL( 0x1 ) | MCF_INTC0_ICRn_IP( 0x1 ); - MCF_INTC0_IMRH &= ~( MCF_INTC0_IMRH_INT_MASK36 ); - MCF_INTC0_IMRL &= ~( MCF_INTC0_IMRL_MASKALL ); - /* Enable interrupts */ - MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_EN | MCF_PIT_PCSR_PIF; - } - - /* Restore the context of the first task that is going to run. */ - portRESTORE_CONTEXT( ); - - /* Should not get here. */ - return pdTRUE; -} - -void -vPortEndScheduler( void ) -{ -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/portable/CodeWarrior/MCF5235/portmacro.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/portable/CodeWarrior/MCF5235/portmacro.h deleted file mode 100644 index 7b5587864..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/portable/CodeWarrior/MCF5235/portmacro.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. - MCF5235 Port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/* ------------------------ Data types for Coldfire ----------------------- */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned int -#define portBASE_TYPE int - -#if defined( USE_16_BIT_TICKS ) && ( USE_16_BIT_TICKS == 1 ) -typedef unsigned portSHORT portTickType; - -#define portMAX_DELAY ( portTickType ) 0xFFFFU -#else -typedef unsigned portLONG portTickType; - -#define portMAX_DELAY ( portTickType ) 0xFFFFFFFFUL -#endif - -/* ------------------------ Global variables ------------------------------ */ -extern volatile unsigned portLONG ulCriticalNesting; - -/* ------------------------ Architecture specifics ------------------------ */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 - -#define portTRAP_YIELD 0 /* Trap 0 */ -#define portIPL_MAX 7 /* Only NMI interrupt 7 allowed. */ - -/* ------------------------ FreeRTOS macros for port ---------------------- */ - -/* - * This function must be called when the current state of the active task - * should be stored. It must be called immediately after exception - * processing from the CPU, i.e. there exists a Coldfire exception frame at - * the current position in the stack. The function reserves space on - * the stack for the CPU registers and other task dependent values (e.g - * ulCriticalNesting) and updates the top of the stack in the TCB. - */ - -#define portSAVE_CONTEXT_IMPL( ) \ - /* reserve space for task state. */ \ - lea -64(a7), a7; \ - /* push data register %d0-%d7/%a0-%a6 on stack. */ \ - movem.l d0-d7/a0-a6, (sp); \ - /* push ulCriticalNesting counter on stack. */ \ - lea 60(a7), a0; \ - move.l ulCriticalNesting, (a0); \ - /* set the new top of the stack in the TCB. */ \ - move.l pxCurrentTCB, a0; \ - move.l sp, (a0) - -#define portSAVE_CONTEXT( ) asm { \ - portSAVE_CONTEXT_IMPL( ); \ -} - -/* - * This function restores the current active and continues its execution. - * It loads the current TCB and restores the processor registers, the - * task dependent values (e.g ulCriticalNesting). Finally execution - * is continued by executing an rte instruction. - */ - -#define portRESTORE_CONTEXT_IMPL( ) \ - move.l pxCurrentTCB, a7; \ - move.l (a7), a7; \ - /* stack pointer now points to the saved registers. */ \ - movem.l (a7), d0-d7/a0-a6; \ - /* restore ulCriticalNesting counter from stack. */ \ - lea 60(a7), a7; \ - move.l (a7)+, ulCriticalNesting; \ - /* stack pointer now points to exception frame. */ \ - rte - -#define portRESTORE_CONTEXT() asm{ \ - portRESTORE_CONTEXT_IMPL( ); \ -} - -#define portENTER_CRITICAL() \ - vPortEnterCritical(); - -#define portEXIT_CRITICAL() \ - vPortExitCritical(); - -#define portSET_IPL( xIPL ) \ - asm_set_ipl( xIPL ) - -#define portDISABLE_INTERRUPTS() \ - do { ( void )portSET_IPL( portIPL_MAX ); } while( 0 ) -#define portENABLE_INTERRUPTS() \ - do { ( void )portSET_IPL( 0 ); } while( 0 ) - -#define portYIELD() \ - asm { trap #0; } - -#define portNOP() \ - asm ( "nop\n\t" ) - -#define portENTER_SWITCHING_ISR() \ - asm volatile ( "move.w #0x2700, %sr" ); \ - /* Save the context of the interrupted task. */ \ - portSAVE_CONTEXT( ); \ - { - -#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ - /* If a switch is required we call vTaskSwitchContext(). */ \ - if( SwitchRequired ) \ - { \ - vTaskSwitchContext( ); \ - } \ - } \ - portRESTORE_CONTEXT( ); - -/* ------------------------ Function prototypes --------------------------- */ -void vPortEnterCritical( void ); -void vPortExitCritical( void ); - -/* ------------------------ Compiler specifics ---------------------------- */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) \ - void vFunction( void *pvParameters ) - -#define portTASK_FUNCTION( vFunction, pvParameters ) \ - void vFunction( void *pvParameters ) -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/portable/MemMang/heap_1.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/portable/MemMang/heap_1.c deleted file mode 100644 index b33632264..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/portable/MemMang/heap_1.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - -Changes between V2.5.1 and V2.5.1 - - + The memory pool has been defined within a struct to ensure correct memory - alignment on 32bit systems. - -Changes between V2.6.1 and V3.0.0 - - + An overflow check has been added to ensure the next free byte variable - does not wrap around. -*/ - - -/* - * The simplest possible implementation of pvPortMalloc(). Note that this - * implementation does NOT allow allocated memory to be freed again. - * - * See heap_2.c and heap_3.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ -#include -#include "FreeRTOS.h" -#include "task.h" - -/* Setup the correct byte alignment mask for the defined byte alignment. */ -#if portBYTE_ALIGNMENT == 4 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) -#endif - -#if portBYTE_ALIGNMENT == 2 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) -#endif - -#if portBYTE_ALIGNMENT == 1 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) -#endif - -#ifndef heapBYTE_ALIGNMENT_MASK - #error "Invalid portBYTE_ALIGNMENT definition" -#endif - -/* Allocate the memory for the heap. The struct is used to force byte -alignment without using any non-portable code. */ -static struct xRTOS_HEAP -{ - unsigned portLONG ulDummy; - unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; -} xHeap; - -static size_t xNextFreeByte = ( size_t ) 0; -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -void *pvReturn = NULL; - - /* Ensure that blocks are always aligned to the required number of bytes. */ - #if portBYTE_ALIGNMENT != 1 - if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) - { - /* Byte alignment required. */ - xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); - } - #endif - - vTaskSuspendAll(); - { - /* Check there is enough room left for the allocation. */ - if( ( ( xNextFreeByte + xWantedSize ) < configTOTAL_HEAP_SIZE ) && - ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) )/* Check for overflow. */ - { - /* Return the next free byte then increment the index past this - block. */ - pvReturn = &( xHeap.ucHeap[ xNextFreeByte ] ); - xNextFreeByte += xWantedSize; - } - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ - /* Memory cannot be freed using this scheme. See heap_2.c and heap_3.c - for alternative implementations, and the memory management pages of - http://www.FreeRTOS.org for more information. */ - ( void ) pv; -} -/*-----------------------------------------------------------*/ - -void vPortInitialiseBlocks( void ) -{ - /* Only required when static memory is not cleared. */ - xNextFreeByte = ( size_t ) 0; -} - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/portable/MemMang/heap_2.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/portable/MemMang/heap_2.c deleted file mode 100644 index b0215ebe4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/portable/MemMang/heap_2.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * A sample implementation of pvPortMalloc() and vPortFree() that permits - * allocated blocks to be freed, but does not combine adjacent free blocks - * into a single larger block. - * - * See heap_1.c and heap_3.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ -#include - -#include "FreeRTOS.h" -#include "task.h" - -/* Setup the correct byte alignment mask for the defined byte alignment. */ -#if portBYTE_ALIGNMENT == 4 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) -#endif - -#if portBYTE_ALIGNMENT == 2 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) -#endif - -#if portBYTE_ALIGNMENT == 1 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) -#endif - -#ifndef heapBYTE_ALIGNMENT_MASK - #error "Invalid portBYTE_ALIGNMENT definition" -#endif - -/* Allocate the memory for the heap. The struct is used to force byte -alignment without using any non-portable code. */ -static struct xRTOS_HEAP -{ - unsigned portLONG ulDummy; - unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; -} xHeap; - -/* Define the linked list structure. This is used to link free blocks in order -of their size. */ -typedef struct A_BLOCK_LINK -{ - struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */ - size_t xBlockSize; /*<< The size of the free block. */ -} xBlockLink; - - -static const unsigned portSHORT heapSTRUCT_SIZE = ( sizeof( xBlockLink ) + ( sizeof( xBlockLink ) % portBYTE_ALIGNMENT ) ); -#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) ) - -/* Create a couple of list links to mark the start and end of the list. */ -static xBlockLink xStart, xEnd; - -/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */ - -/* - * Insert a block into the list of free blocks - which is ordered by size of - * the block. Small blocks at the start of the list and large blocks at the end - * of the list. - */ -#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \ -{ \ -xBlockLink *pxIterator; \ -size_t xBlockSize; \ - \ - xBlockSize = pxBlockToInsert->xBlockSize; \ - \ - /* Iterate through the list until a block is found that has a larger size */ \ - /* than the block we are inserting. */ \ - for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \ - { \ - /* There is nothing to do here - just iterate to the correct position. */ \ - } \ - \ - /* Update the list to include the block being inserted in the correct */ \ - /* position. */ \ - pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \ - pxIterator->pxNextFreeBlock = pxBlockToInsert; \ -} -/*-----------------------------------------------------------*/ - -#define prvHeapInit() \ -{ \ -xBlockLink *pxFirstFreeBlock; \ - \ - /* xStart is used to hold a pointer to the first item in the list of free */ \ - /* blocks. The void cast is used to prevent compiler warnings. */ \ - xStart.pxNextFreeBlock = ( void * ) xHeap.ucHeap; \ - xStart.xBlockSize = ( size_t ) 0; \ - \ - /* xEnd is used to mark the end of the list of free blocks. */ \ - xEnd.xBlockSize = configTOTAL_HEAP_SIZE; \ - xEnd.pxNextFreeBlock = NULL; \ - \ - /* To start with there is a single free block that is sized to take up the \ - entire heap space. */ \ - pxFirstFreeBlock = ( void * ) xHeap.ucHeap; \ - pxFirstFreeBlock->xBlockSize = configTOTAL_HEAP_SIZE; \ - pxFirstFreeBlock->pxNextFreeBlock = &xEnd; \ -} -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -xBlockLink *pxBlock, *pxPreviousBlock, *pxNewBlockLink; -static portBASE_TYPE xHeapHasBeenInitialised = pdFALSE; -void *pvReturn = NULL; - - vTaskSuspendAll(); - { - /* If this is the first call to malloc then the heap will require - initialisation to setup the list of free blocks. */ - if( xHeapHasBeenInitialised == pdFALSE ) - { - prvHeapInit(); - xHeapHasBeenInitialised = pdTRUE; - } - - /* The wanted size is increased so it can contain a xBlockLink - structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) - { - xWantedSize += heapSTRUCT_SIZE; - - /* Ensure that blocks are always aligned to the required number of bytes. */ - if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) - { - /* Byte alignment required. */ - xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); - } - } - - if( ( xWantedSize > 0 ) && ( xWantedSize < configTOTAL_HEAP_SIZE ) ) - { - /* Blocks are stored in byte order - traverse the list from the start - (smallest) block until one of adequate size is found. */ - pxPreviousBlock = &xStart; - pxBlock = xStart.pxNextFreeBlock; - while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock ) ) - { - pxPreviousBlock = pxBlock; - pxBlock = pxBlock->pxNextFreeBlock; - } - - /* If we found the end marker then a block of adequate size was not found. */ - if( pxBlock != &xEnd ) - { - /* Return the memory space - jumping over the xBlockLink structure - at its start. */ - pvReturn = ( void * ) ( ( ( unsigned portCHAR * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE ); - - /* This block is being returned for use so must be taken our of the - list of free blocks. */ - pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; - - /* If the block is larger than required it can be split into two. */ - if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) - { - /* This block is to be split into two. Create a new block - following the number of bytes requested. The void cast is - used to prevent byte alignment warnings from the compiler. */ - pxNewBlockLink = ( void * ) ( ( ( unsigned portCHAR * ) pxBlock ) + xWantedSize ); - - /* Calculate the sizes of two blocks split from the single - block. */ - pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; - pxBlock->xBlockSize = xWantedSize; - - /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); - } - } - } - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ -unsigned portCHAR *puc = ( unsigned portCHAR * ) pv; -xBlockLink *pxLink; - - if( pv ) - { - /* The memory being freed will have an xBlockLink structure immediately - before it. */ - puc -= heapSTRUCT_SIZE; - - /* This casting is to keep the compiler from issuing warnings. */ - pxLink = ( void * ) puc; - - vTaskSuspendAll(); - { - /* Add this block to the list of free blocks. */ - prvInsertBlockIntoFreeList( ( ( xBlockLink * ) pxLink ) ); - } - xTaskResumeAll(); - } -} -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/portable/MemMang/heap_3.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/portable/MemMang/heap_3.c deleted file mode 100644 index 11a302313..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/portable/MemMang/heap_3.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * Implementation of pvPortMalloc() and vPortFree() that relies on the - * compilers own malloc() and free() implementations. - * - * This file can only be used if the linker is configured to to generate - * a heap memory area. - * - * See heap_2.c and heap_1.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ - -#include - -#include "FreeRTOS.h" -#include "task.h" - -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -void *pvReturn; - - vTaskSuspendAll(); - { - pvReturn = malloc( xWantedSize ); - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ - if( pv ) - { - vTaskSuspendAll(); - { - free( pv ); - } - xTaskResumeAll(); - } -} - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/queue.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/queue.c deleted file mode 100644 index 17d88dd52..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/queue.c +++ /dev/null @@ -1,869 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.01 - - + More use of 8bit data types. - + Function name prefixes changed where the data type returned has changed. - -Changed from V2.0.0 - - + Added the queue locking mechanism and make more use of the scheduler - suspension feature to minimise the time interrupts have to be disabled - when accessing a queue. - -Changed from V2.2.0 - - + Explicit use of 'signed' qualifier on portCHAR types added. - -Changes from V3.0.0 - - + API changes as described on the FreeRTOS.org WEB site. - -Changes from V3.2.3 - - + Added the queue functions that can be used from co-routines. - -*/ - -#include -#include -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/*----------------------------------------------------------- - * PUBLIC LIST API documented in list.h - *----------------------------------------------------------*/ - -/* Constants used with the cRxLock and cTxLock structure members. */ -#define queueUNLOCKED ( ( signed portBASE_TYPE ) -1 ) - -/* - * Definition of the queue used by the scheduler. - * Items are queued by copy, not reference. - */ -typedef struct QueueDefinition -{ - signed portCHAR *pcHead; /*< Points to the beginning of the queue storage area. */ - signed portCHAR *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */ - - signed portCHAR *pcWriteTo; /*< Points to the free next place in the storage area. */ - signed portCHAR *pcReadFrom; /*< Points to the last place that a queued item was read from. */ - - xList xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */ - xList xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */ - - unsigned portBASE_TYPE uxMessagesWaiting;/*< The number of items currently in the queue. */ - unsigned portBASE_TYPE uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */ - unsigned portBASE_TYPE uxItemSize; /*< The size of each items that the queue will hold. */ - - signed portBASE_TYPE xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ - signed portBASE_TYPE xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ -} xQUEUE; -/*-----------------------------------------------------------*/ - -/* - * Inside this file xQueueHandle is a pointer to a xQUEUE structure. - * To keep the definition private the API header file defines it as a - * pointer to void. - */ -typedef xQUEUE * xQueueHandle; - -/* - * Prototypes for public functions are included here so we don't have to - * include the API header file (as it defines xQueueHandle differently). These - * functions are documented in the API header file. - */ -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); -signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue ); -void vQueueDelete( xQueueHandle xQueue ); -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ); -signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - -#if configUSE_CO_ROUTINES == 1 - signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ); - signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ); - signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); -#endif - -/* - * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not - * prevent an ISR from adding or removing items to the queue, but does prevent - * an ISR from removing tasks from the queue event lists. If an ISR finds a - * queue is locked it will instead increment the appropriate queue lock count - * to indicate that a task may require unblocking. When the queue in unlocked - * these lock counts are inspected, and the appropriate action taken. - */ -static signed portBASE_TYPE prvUnlockQueue( xQueueHandle pxQueue ); - -/* - * Uses a critical section to determine if there is any data in a queue. - * - * @return pdTRUE if the queue contains no items, otherwise pdFALSE. - */ -static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ); - -/* - * Uses a critical section to determine if there is any space in a queue. - * - * @return pdTRUE if there is no space, otherwise pdFALSE; - */ -static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ); - -/* - * Macro that copies an item into the queue. This is done by copying the item - * byte for byte, not by reference. Updates the queue state to ensure it's - * integrity after the copy. - */ -#define prvCopyQueueData( pxQueue, pvItemToQueue ) \ -{ \ - memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize ); \ - ++( pxQueue->uxMessagesWaiting ); \ - pxQueue->pcWriteTo += pxQueue->uxItemSize; \ - if( pxQueue->pcWriteTo >= pxQueue->pcTail ) \ - { \ - pxQueue->pcWriteTo = pxQueue->pcHead; \ - } \ -} -/*-----------------------------------------------------------*/ - -/* - * Macro to mark a queue as locked. Locking a queue prevents an ISR from - * accessing the queue event lists. - */ -#define prvLockQueue( pxQueue ) \ -{ \ - taskENTER_CRITICAL(); \ - ++( pxQueue->xRxLock ); \ - ++( pxQueue->xTxLock ); \ - taskEXIT_CRITICAL(); \ -} -/*-----------------------------------------------------------*/ - - -/*----------------------------------------------------------- - * PUBLIC QUEUE MANAGEMENT API documented in queue.h - *----------------------------------------------------------*/ - -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ) -{ -xQUEUE *pxNewQueue; -size_t xQueueSizeInBytes; - - /* Allocate the new queue structure. */ - if( uxQueueLength > ( unsigned portBASE_TYPE ) 0 ) - { - pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) ); - if( pxNewQueue != NULL ) - { - /* Create the list of pointers to queue items. The queue is one byte - longer than asked for to make wrap checking easier/faster. */ - xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1; - - pxNewQueue->pcHead = ( signed portCHAR * ) pvPortMalloc( xQueueSizeInBytes ); - if( pxNewQueue->pcHead != NULL ) - { - /* Initialise the queue members as described above where the - queue type is defined. */ - pxNewQueue->pcTail = pxNewQueue->pcHead + ( uxQueueLength * uxItemSize ); - pxNewQueue->uxMessagesWaiting = 0; - pxNewQueue->pcWriteTo = pxNewQueue->pcHead; - pxNewQueue->pcReadFrom = pxNewQueue->pcHead + ( ( uxQueueLength - 1 ) * uxItemSize ); - pxNewQueue->uxLength = uxQueueLength; - pxNewQueue->uxItemSize = uxItemSize; - pxNewQueue->xRxLock = queueUNLOCKED; - pxNewQueue->xTxLock = queueUNLOCKED; - - /* Likewise ensure the event queues start with the correct state. */ - vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) ); - vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) ); - - return pxNewQueue; - } - else - { - vPortFree( pxNewQueue ); - } - } - } - - /* Will only reach here if we could not allocate enough memory or no memory - was required. */ - return NULL; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* Make sure other tasks do not access the queue. */ - vTaskSuspendAll(); - - /* It is important that this is the only thread/ISR that modifies the - ready or delayed lists until xTaskResumeAll() is called. Places where - the ready/delayed lists are modified include: - - + vTaskDelay() - Nothing can call vTaskDelay as the scheduler is - suspended, vTaskDelay() cannot be called from an ISR. - + vTaskPrioritySet() - Has a critical section around the access. - + vTaskSwitchContext() - This will not get executed while the scheduler - is suspended. - + prvCheckDelayedTasks() - This will not get executed while the - scheduler is suspended. - + xTaskCreate() - Has a critical section around the access. - + vTaskResume() - Has a critical section around the access. - + xTaskResumeAll() - Has a critical section around the access. - + xTaskRemoveFromEventList - Checks to see if the scheduler is - suspended. If so then the TCB being removed from the event is - removed from the event and added to the xPendingReadyList. - */ - - /* Make sure interrupts do not access the queue event list. */ - prvLockQueue( pxQueue ); - - /* It is important that interrupts to not access the event list of the - queue being modified here. Places where the event list is modified - include: - - + xQueueSendFromISR(). This checks the lock on the queue to see if - it has access. If the queue is locked then the Tx lock count is - incremented to signify that a task waiting for data can be made ready - once the queue lock is removed. If the queue is not locked then - a task can be moved from the event list, but will not be removed - from the delayed list or placed in the ready list until the scheduler - is unlocked. - - + xQueueReceiveFromISR(). As per xQueueSendFromISR(). - */ - - /* If the queue is already full we may have to block. */ - if( prvIsQueueFull( pxQueue ) ) - { - /* The queue is full - do we want to block or just leave without - posting? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* We are going to place ourselves on the xTasksWaitingToSend event - list, and will get woken should the delay expire, or space become - available on the queue. - - As detailed above we do not require mutual exclusion on the event - list as nothing else can modify it or the ready lists while we - have the scheduler suspended and queue locked. - - It is possible that an ISR has removed data from the queue since we - checked if any was available. If this is the case then the data - will have been copied from the queue, and the queue variables - updated, but the event list will not yet have been checked to see if - anything is waiting as the queue is locked. */ - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); - - /* Force a context switch now as we are blocked. We can do - this from within a critical section as the task we are - switching to has its own context. When we return here (i.e. we - unblock) we will leave the critical section as normal. - - It is possible that an ISR has caused an event on an unrelated and - unlocked queue. If this was the case then the event list for that - queue will have been updated but the ready lists left unchanged - - instead the readied task will have been added to the pending ready - list. */ - taskENTER_CRITICAL(); - { - /* We can safely unlock the queue and scheduler here as - interrupts are disabled. We must not yield with anything - locked, but we can yield from within a critical section. - - Tasks that have been placed on the pending ready list cannot - be tasks that are waiting for events on this queue. See - in comment xTaskRemoveFromEventList(). */ - prvUnlockQueue( pxQueue ); - - /* Resuming the scheduler may cause a yield. If so then there - is no point yielding again here. */ - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - - /* Before leaving the critical section we have to ensure - exclusive access again. */ - vTaskSuspendAll(); - prvLockQueue( pxQueue ); - } - taskEXIT_CRITICAL(); - } - } - - /* When we are here it is possible that we unblocked as space became - available on the queue. It is also possible that an ISR posted to the - queue since we left the critical section, so it may be that again there - is no space. This would only happen if a task and ISR post onto the - same queue. */ - taskENTER_CRITICAL(); - { - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - /* There is room in the queue, copy the data into the queue. */ - prvCopyQueueData( pxQueue, pvItemToQueue ); - xReturn = pdPASS; - - /* Update the TxLock count so prvUnlockQueue knows to check for - tasks waiting for data to become available in the queue. */ - ++( pxQueue->xTxLock ); - } - else - { - xReturn = errQUEUE_FULL; - } - } - taskEXIT_CRITICAL(); - - /* We no longer require exclusive access to the queue. prvUnlockQueue - will remove any tasks suspended on a receive if either this function - or an ISR has posted onto the queue. */ - if( prvUnlockQueue( pxQueue ) ) - { - /* Resume the scheduler - making ready any tasks that were woken - by an event while the scheduler was locked. Resuming the - scheduler may cause a yield, in which case there is no point - yielding again here. */ - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - } - else - { - /* Resume the scheduler - making ready any tasks that were woken - by an event while the scheduler was locked. */ - xTaskResumeAll(); - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ) -{ - /* Similar to xQueueSend, except we don't block if there is no room in the - queue. Also we don't directly wake a task that was blocked on a queue - read, instead we return a flag to say whether a context switch is required - or not (i.e. has a task with a higher priority than us been woken by this - post). */ - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - prvCopyQueueData( pxQueue, pvItemToQueue ); - - /* If the queue is locked we do not alter the event list. This will - be done when the queue is unlocked later. */ - if( pxQueue->xTxLock == queueUNLOCKED ) - { - /* We only want to wake one task per ISR, so check that a task has - not already been woken. */ - if( !xTaskPreviouslyWoken ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority so record that a - context switch is required. */ - return pdTRUE; - } - } - } - } - else - { - /* Increment the lock count so the task that unlocks the queue - knows that data was posted while it was locked. */ - ++( pxQueue->xTxLock ); - } - } - - return xTaskPreviouslyWoken; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* This function is very similar to xQueueSend(). See comments within - xQueueSend() for a more detailed explanation. - - Make sure other tasks do not access the queue. */ - vTaskSuspendAll(); - - /* Make sure interrupts do not access the queue. */ - prvLockQueue( pxQueue ); - - /* If there are no messages in the queue we may have to block. */ - if( prvIsQueueEmpty( pxQueue ) ) - { - /* There are no messages in the queue, do we want to block or just - leave with nothing? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); - taskENTER_CRITICAL(); - { - prvUnlockQueue( pxQueue ); - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - - vTaskSuspendAll(); - prvLockQueue( pxQueue ); - } - taskEXIT_CRITICAL(); - } - } - - taskENTER_CRITICAL(); - { - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - /* Increment the lock count so prvUnlockQueue knows to check for - tasks waiting for space to become available on the queue. */ - ++( pxQueue->xRxLock ); - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - } - taskEXIT_CRITICAL(); - - /* We no longer require exclusive access to the queue. */ - if( prvUnlockQueue( pxQueue ) ) - { - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - } - else - { - xTaskResumeAll(); - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ) -{ -signed portBASE_TYPE xReturn; - - /* We cannot block from an ISR, so check there is data available. */ - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Copy the data from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - /* If the queue is locked we will not modify the event list. Instead - we update the lock count so the task that unlocks the queue will know - that an ISR has removed data while the queue was locked. */ - if( pxQueue->xRxLock == queueUNLOCKED ) - { - /* We only want to wake one task per ISR, so check that a task has - not already been woken. */ - if( !( *pxTaskWoken ) ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - /* The task waiting has a higher priority than us so - force a context switch. */ - *pxTaskWoken = pdTRUE; - } - } - } - } - else - { - /* Increment the lock count so the task that unlocks the queue - knows that data was removed while it was locked. */ - ++( pxQueue->xRxLock ); - } - - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue ) -{ -unsigned portBASE_TYPE uxReturn; - - taskENTER_CRITICAL(); - uxReturn = pxQueue->uxMessagesWaiting; - taskEXIT_CRITICAL(); - - return uxReturn; -} -/*-----------------------------------------------------------*/ - -void vQueueDelete( xQueueHandle pxQueue ) -{ - vPortFree( pxQueue->pcHead ); - vPortFree( pxQueue ); -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvUnlockQueue( xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xYieldRequired = pdFALSE; - - /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */ - - /* The lock counts contains the number of extra data items placed or - removed from the queue while the queue was locked. When a queue is - locked items can be added or removed, but the event lists cannot be - updated. */ - taskENTER_CRITICAL(); - { - --( pxQueue->xTxLock ); - - /* See if data was added to the queue while it was locked. */ - if( pxQueue->xTxLock > queueUNLOCKED ) - { - pxQueue->xTxLock = queueUNLOCKED; - - /* Data was posted while the queue was locked. Are any tasks - blocked waiting for data to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - /* Tasks that are removed from the event list will get added to - the pending ready list as the scheduler is still suspended. */ - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority so record that a - context switch is required. */ - xYieldRequired = pdTRUE; - } - } - } - } - taskEXIT_CRITICAL(); - - /* Do the same for the Rx lock. */ - taskENTER_CRITICAL(); - { - --( pxQueue->xRxLock ); - - if( pxQueue->xRxLock > queueUNLOCKED ) - { - pxQueue->xRxLock = queueUNLOCKED; - - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - xYieldRequired = pdTRUE; - } - } - } - } - taskEXIT_CRITICAL(); - - return xYieldRequired; -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - taskENTER_CRITICAL(); - xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ); - taskEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - taskENTER_CRITICAL(); - xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength ); - taskEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* If the queue is already full we may have to block. A critical section - is required to prevent an interrupt removing something from the queue - between the check to see if the queue is full and blocking on the queue. */ - portDISABLE_INTERRUPTS(); - { - if( prvIsQueueFull( pxQueue ) ) - { - /* The queue is full - do we want to block or just leave without - posting? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* As this is called from a coroutine we cannot block directly, but - return indicating that we need to block. */ - vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) ); - portENABLE_INTERRUPTS(); - return errQUEUE_BLOCKED; - } - else - { - portENABLE_INTERRUPTS(); - return errQUEUE_FULL; - } - } - } - portENABLE_INTERRUPTS(); - - portNOP(); - - portDISABLE_INTERRUPTS(); - { - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - /* There is room in the queue, copy the data into the queue. */ - prvCopyQueueData( pxQueue, pvItemToQueue ); - xReturn = pdPASS; - - /* Were any co-routines waiting for data to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - /* In this instance the co-routine could be placed directly - into the ready list as we are within a critical section. - Instead the same pending ready list mechansim is used as if - the event were caused from within an interrupt. */ - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The co-routine waiting has a higher priority so record - that a yield might be appropriate. */ - xReturn = errQUEUE_YIELD; - } - } - } - else - { - xReturn = errQUEUE_FULL; - } - } - portENABLE_INTERRUPTS(); - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* If the queue is already empty we may have to block. A critical section - is required to prevent an interrupt adding something to the queue - between the check to see if the queue is empty and blocking on the queue. */ - portDISABLE_INTERRUPTS(); - { - if( prvIsQueueEmpty( pxQueue ) ) - { - /* There are no messages in the queue, do we want to block or just - leave with nothing? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* As this is a co-routine we cannot block directly, but return - indicating that we need to block. */ - vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) ); - portENABLE_INTERRUPTS(); - return errQUEUE_BLOCKED; - } - else - { - portENABLE_INTERRUPTS(); - return errQUEUE_FULL; - } - } - } - portENABLE_INTERRUPTS(); - - portNOP(); - - portDISABLE_INTERRUPTS(); - { - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Data is available from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - xReturn = pdPASS; - - /* Were any co-routines waiting for space to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - /* In this instance the co-routine could be placed directly - into the ready list as we are within a critical section. - Instead the same pending ready list mechansim is used as if - the event were caused from within an interrupt. */ - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - xReturn = errQUEUE_YIELD; - } - } - } - else - { - xReturn = pdFAIL; - } - } - portENABLE_INTERRUPTS(); - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - - - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ) -{ - /* Cannot block within an ISR so if there is no space on the queue then - exit without doing anything. */ - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - prvCopyQueueData( pxQueue, pvItemToQueue ); - - /* We only want to wake one co-routine per ISR, so check that a - co-routine has not already been woken. */ - if( !xCoRoutinePreviouslyWoken ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - return pdTRUE; - } - } - } - } - - return xCoRoutinePreviouslyWoken; -} -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxCoRoutineWoken ) -{ -signed portBASE_TYPE xReturn; - - /* We cannot block from an ISR, so check there is data available. If - not then just leave without doing anything. */ - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Copy the data from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - if( !( *pxCoRoutineWoken ) ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - *pxCoRoutineWoken = pdTRUE; - } - } - } - - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/tasks.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/tasks.c deleted file mode 100644 index 83a2d5733..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/freertos/tasks.c +++ /dev/null @@ -1,1771 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.00: - - + Call to portRESTORE_CONTEXT has been removed. The first context - switch is now performed within sPortStartScheduler(). - -Changes from V1.01: - - + More use of 8bit data types. - + Function name prefixes changed where the data type returned has changed. - + configUSE_TRACE_FACILITY is no longer defined by default. - -Changes from V1.2.0 - - + Introduced ucTopReadyPriority. This tracks the highest priority ready - queue that contains a valid TCB and thus makes the context switch - slightly faster. - - + prvAddTaskToReadyQueue() has been made a macro. - -Changes from V1.2.6 - - + Added conditional compilation directives. - + Extended API. - + Rearranged function order. - + Creating a task now causes a context switch if the task being created - has a higher priority than the calling task - assuming the kernel is - running. - + vTaskDelete() now only causes a context switch if the calling task is - the task being deleted. - -Changes from V2.0.0 - - + Allow the type of the tick count to be 16 or 32 bits. - + Introduce xPendingReadyList feature to allow the time interrupts have to - be disabled to be minimised. - + Remove the #if( INCLUDE_vTaskSuspendAll ) statements. vTaskSuspendAll() - is now always included as it is used by the scheduler itself. - -Changes from V2.1.0 - - + Bug fix - pxCurrentTCB is now initialised before the call to - prvInitializeTaskLists(). Previously pxCurrentTCB could be accessed - while null. - -Changed from V2.1.1 - - + Change to where lStackSize is declared within sTaskCreate() to prevent - compiler warnings with 8051 port. - -Changes from V2.2.0 - - + Explicit use of 'signed' qualifier on portCHAR types added. - + Changed odd calculation of initial pxTopOfStack value when - portSTACK_GROWTH < 0. - + Removed pcVersionNumber definition. - -Changes from V2.5.3 - - + cTaskResumeAll() modified to ensure it can be called prior to the task - lists being initialised. - -Changes from V2.5.5 - - + Added API function vTaskDelayUntil(). - + Added INCLUDE_vTaskDelay conditional compilation. - -Changes from V2.6.0 - - + Updated the vWriteTraceToBuffer macro to always be 4 byte aligned so it - can be used on ARM architectures. - + tskMAX_TASK_NAME_LEN definition replaced with the port specific - configMAX_TASK_NAME_LEN definition. - + Removed the call to strcpy when copying across the task name into the - TCB. - + Added ucTasksDeleted variable to prevent vTaskSuspendAll() being called - too often in the idle task. - -Changes between V3.0.0 and V2.6.1 - - + When resuming the scheduler a yield is performed if either a tick has - been missed, or a task is moved from the pending ready list into a ready - list. Previously a yield was not performed on this second condition. - + Introduced the type portBASE_TYPE. This necessitates several API - changes. - + Removed the sUsingPreemption variable. The constant defined in - portmacro.h is now used directly. - + The idle task can now include an optional hook function - and no longer - completes its time slice if other tasks with equal priority to it are - ready to run. - + See the FreeRTOS.org documentation for more information on V2.x.x to - V3.x.x modifications. - -Changes from V3.1.1 - - + Modified vTaskPrioritySet() and vTaskResume() to allow these functions to - be called while the scheduler is suspended. - + Corrected the task ordering within event lists. - -Changes from V3.2.0 - - + Added function xTaskGetCurrentTaskHandle(). - -Changes from V3.2.4 - - + Changed the volatile declarations on some variables to reflect the - changes to the list definitions. - + Changed the order of the TCB definition so there is commonality between - the task control block and a co-routine control block. - + Allow the scheduler to be started even if no tasks other than the idle - task has been created. This allows co-routines to run even when no tasks - have been created. - + The need for a context switch is now signalled if a task woken by an - event has a priority greater or equal to the currently running task. - Previously this was only greater than. - -Changes from V4.0.0 - - + Added the xMissedYield handling. - -Changes from V4.0.1 - - + The function vTaskList() now suspends the scheduler rather than disabling - interrupts during the creation of the task list. - + Allow a task to delete itself by passing in its own handle. Previously - this could only be done by passing in NULL. - + The tick hook function is now called only within a tick isr. Previously - it was also called when the tick function was called during the scheduler - unlocking process. - -Changes from V4.0.3 - - + Extra checks have been placed in vTaskPrioritySet() to avoid unnecessary - yields. - -Changed from V4.0.4 - - + Bug fix: The 'value' of the event list item is updated when the priority - of a task is changed. Previously only the priority of the TCB itself was - changed. - + When resuming a task a check is first made to see if the task is actually - suspended. - + vTaskPrioritySet() and vTaskResume() no longer use the event list item. - This has not been necessary since V4.0.1 when the xMissedYield handling - was added. - + Implement xTaskResumeFromISR(). -*/ - -#include -#include -#include - -#include "FreeRTOS.h" -#include "task.h" - -/* - * Macro to define the amount of stack available to the idle task. - */ -#define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE - - -/* - * Default a definitions for backwards compatibility with old - * portmacro.h files. - */ -#ifndef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 16 -#endif - -#ifndef INCLUDE_xTaskGetCurrentTaskHandle - #define INCLUDE_xTaskGetCurrentTaskHandle 0 -#endif - -#ifndef configIDLE_SHOULD_YIELD - #define configIDLE_SHOULD_YIELD 1 -#endif - -#if configMAX_TASK_NAME_LEN < 1 - #undef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 1 -#endif - -#ifndef INCLUDE_xTaskResumeFromISR - #define INCLUDE_xTaskResumeFromISR 1 -#endif - -/* - * Task control block. A task control block (TCB) is allocated to each task, - * and stores the context of the task. - */ -typedef struct tskTaskControlBlock -{ - volatile portSTACK_TYPE *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE STRUCT. */ - xListItem xGenericListItem; /*< List item used to place the TCB in ready and blocked queues. */ - xListItem xEventListItem; /*< List item used to place the TCB in event lists. */ - unsigned portBASE_TYPE uxPriority; /*< The priority of the task where 0 is the lowest priority. */ - portSTACK_TYPE *pxStack; /*< Points to the start of the stack. */ - unsigned portBASE_TYPE uxTCBNumber; /*< This is used for tracing the scheduler and making debugging easier only. */ - signed portCHAR pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */ - unsigned portSHORT usStackDepth; /*< Total depth of the stack (when empty). This is defined as the number of variables the stack can hold, not the number of bytes. */ -} tskTCB; - -/*lint -e956 */ - -tskTCB * volatile pxCurrentTCB = NULL; - -/* Lists for ready and blocked tasks. --------------------*/ - -static xList pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */ -static xList xDelayedTaskList1; /*< Delayed tasks. */ -static xList xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */ -static xList * volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */ -static xList * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */ -static xList xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready queue when the scheduler is resumed. */ - -#if ( INCLUDE_vTaskDelete == 1 ) - - static volatile xList xTasksWaitingTermination; /*< Tasks that have been deleted - but the their memory not yet freed. */ - static volatile unsigned portBASE_TYPE uxTasksDeleted = ( unsigned portBASE_TYPE ) 0; - -#endif - -#if ( INCLUDE_vTaskSuspend == 1 ) - - static xList xSuspendedTaskList; /*< Tasks that are currently suspended. */ - -#endif - -/* File private variables. --------------------------------*/ -static volatile unsigned portBASE_TYPE uxCurrentNumberOfTasks = ( unsigned portBASE_TYPE ) 0; -static volatile portTickType xTickCount = ( portTickType ) 0; -static unsigned portBASE_TYPE uxTopUsedPriority = tskIDLE_PRIORITY; -static volatile unsigned portBASE_TYPE uxTopReadyPriority = tskIDLE_PRIORITY; -static volatile signed portBASE_TYPE xSchedulerRunning = pdFALSE; -static volatile unsigned portBASE_TYPE uxSchedulerSuspended = ( unsigned portBASE_TYPE ) pdFALSE; -static volatile unsigned portBASE_TYPE uxMissedTicks = ( unsigned portBASE_TYPE ) 0; -static volatile portBASE_TYPE xMissedYield = ( portBASE_TYPE ) pdFALSE; - -/* Debugging and trace facilities private variables and macros. ------------*/ - -/* - * The value used to fill the stack of a task when the task is created. This - * is used purely for checking the high water mark for tasks. - */ -#define tskSTACK_FILL_BYTE ( 0xa5 ) - -/* - * Macros used by vListTask to indicate which state a task is in. - */ -#define tskBLOCKED_CHAR ( ( signed portCHAR ) 'B' ) -#define tskREADY_CHAR ( ( signed portCHAR ) 'R' ) -#define tskDELETED_CHAR ( ( signed portCHAR ) 'D' ) -#define tskSUSPENDED_CHAR ( ( signed portCHAR ) 'S' ) - -/* - * Macros and private variables used by the trace facility. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - #define tskSIZE_OF_EACH_TRACE_LINE ( ( unsigned portLONG ) ( sizeof( unsigned portLONG ) + sizeof( unsigned portLONG ) ) ) - static volatile signed portCHAR * volatile pcTraceBuffer; - static signed portCHAR *pcTraceBufferStart; - static signed portCHAR *pcTraceBufferEnd; - static signed portBASE_TYPE xTracing = pdFALSE; - -#endif - -/* - * Macro that writes a trace of scheduler activity to a buffer. This trace - * shows which task is running when and is very useful as a debugging tool. - * As this macro is called each context switch it is a good idea to undefine - * it if not using the facility. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - #define vWriteTraceToBuffer() \ - { \ - if( xTracing ) \ - { \ - static unsigned portBASE_TYPE uxPreviousTask = 255; \ - \ - if( uxPreviousTask != pxCurrentTCB->uxTCBNumber ) \ - { \ - if( ( pcTraceBuffer + tskSIZE_OF_EACH_TRACE_LINE ) < pcTraceBufferEnd ) \ - { \ - uxPreviousTask = pxCurrentTCB->uxTCBNumber; \ - *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) xTickCount; \ - pcTraceBuffer += sizeof( unsigned portLONG ); \ - *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) uxPreviousTask; \ - pcTraceBuffer += sizeof( unsigned portLONG ); \ - } \ - else \ - { \ - xTracing = pdFALSE; \ - } \ - } \ - } \ - } - -#else - - #define vWriteTraceToBuffer() - -#endif - - -/* - * Place the task represented by pxTCB into the appropriate ready queue for - * the task. It is inserted at the end of the list. One quirk of this is - * that if the task being inserted is at the same priority as the currently - * executing task, then it will only be rescheduled after the currently - * executing task has been rescheduled. - */ -#define prvAddTaskToReadyQueue( pxTCB ) \ -{ \ - if( pxTCB->uxPriority > uxTopReadyPriority ) \ - { \ - uxTopReadyPriority = pxTCB->uxPriority; \ - } \ - vListInsertEnd( ( xList * ) &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ); \ -} - -/* - * Macro that looks at the list of tasks that are currently delayed to see if - * any require waking. - * - * Tasks are stored in the queue in the order of their wake time - meaning - * once one tasks has been found whose timer has not expired we need not look - * any further down the list. - */ -#define prvCheckDelayedTasks() \ -{ \ -register tskTCB *pxTCB; \ - \ - while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ) ) != NULL ) \ - { \ - if( xTickCount < listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) ) ) \ - { \ - break; \ - } \ - vListRemove( &( pxTCB->xGenericListItem ) ); \ - /* Is the task waiting on an event also? */ \ - if( pxTCB->xEventListItem.pvContainer ) \ - { \ - vListRemove( &( pxTCB->xEventListItem ) ); \ - } \ - prvAddTaskToReadyQueue( pxTCB ); \ - } \ -} - -/* - * Several functions take an xTaskHandle parameter that can optionally be NULL, - * where NULL is used to indicate that the handle of the currently executing - * task should be used in place of the parameter. This macro simply checks to - * see if the parameter is NULL and returns a pointer to the appropriate TCB. - */ -#define prvGetTCBFromHandle( pxHandle ) ( ( pxHandle == NULL ) ? ( tskTCB * ) pxCurrentTCB : ( tskTCB * ) pxHandle ) - - -/* File private functions. --------------------------------*/ - -/* - * Utility to ready a TCB for a given task. Mainly just copies the parameters - * into the TCB structure. - */ -static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ); - -/* - * Utility to ready all the lists used by the scheduler. This is called - * automatically upon the creation of the first task. - */ -static void prvInitialiseTaskLists( void ); - -/* - * The idle task, which as all tasks is implemented as a never ending loop. - * The idle task is automatically created and added to the ready lists upon - * creation of the first user task. - * - * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific - * language extensions. The equivalent prototype for this function is: - * - * void prvIdleTask( void *pvParameters ); - * - */ -static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ); - -/* - * Utility to free all memory allocated by the scheduler to hold a TCB, - * including the stack pointed to by the TCB. - * - * This does not free memory allocated by the task itself (i.e. memory - * allocated by calls to pvPortMalloc from within the tasks application code). - */ -#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) - static void prvDeleteTCB( tskTCB *pxTCB ); -#endif - -/* - * Used only by the idle task. This checks to see if anything has been placed - * in the list of tasks waiting to be deleted. If so the task is cleaned up - * and its TCB deleted. - */ -static void prvCheckTasksWaitingTermination( void ); - -/* - * Allocates memory from the heap for a TCB and associated stack. Checks the - * allocation was successful. - */ -static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ); - -/* - * Called from vTaskList. vListTasks details all the tasks currently under - * control of the scheduler. The tasks may be in one of a number of lists. - * prvListTaskWithinSingleList accepts a list and details the tasks from - * within just that list. - * - * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM - * NORMAL APPLICATION CODE. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ); - -#endif - -/* - * When a task is created, the stack of the task is filled with a known value. - * This function determines the 'high water mark' of the task stack by - * determining how much of the stack remains at the original preset value. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte ); - -#endif - -/*lint +e956 */ - - - - - -/*----------------------------------------------------------- - * TASK CREATION API documented in task.h - *----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask ) -{ -signed portBASE_TYPE xReturn; -tskTCB * pxNewTCB; -static unsigned portBASE_TYPE uxTaskNumber = 0; /*lint !e956 Static is deliberate - this is guarded before use. */ - - /* Allocate the memory required by the TCB and stack for the new task. - checking that the allocation was successful. */ - pxNewTCB = prvAllocateTCBAndStack( usStackDepth ); - - if( pxNewTCB != NULL ) - { - portSTACK_TYPE *pxTopOfStack; - - /* Setup the newly allocated TCB with the initial state of the task. */ - prvInitialiseTCBVariables( pxNewTCB, usStackDepth, pcName, uxPriority ); - - /* Calculate the top of stack address. This depends on whether the - stack grows from high memory to low (as per the 80x86) or visa versa. - portSTACK_GROWTH is used to make the result positive or negative as - required by the port. */ - #if portSTACK_GROWTH < 0 - { - pxTopOfStack = pxNewTCB->pxStack + ( pxNewTCB->usStackDepth - 1 ); - } - #else - { - pxTopOfStack = pxNewTCB->pxStack; - } - #endif - - /* Initialize the TCB stack to look as if the task was already running, - but had been interrupted by the scheduler. The return address is set - to the start of the task function. Once the stack has been initialised - the top of stack variable is updated. */ - pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pvTaskCode, pvParameters ); - - /* We are going to manipulate the task queues to add this task to a - ready list, so must make sure no interrupts occur. */ - portENTER_CRITICAL(); - { - uxCurrentNumberOfTasks++; - if( uxCurrentNumberOfTasks == ( unsigned portBASE_TYPE ) 1 ) - { - /* As this is the first task it must also be the current task. */ - pxCurrentTCB = pxNewTCB; - - /* This is the first task to be created so do the preliminary - initialisation required. We will not recover if this call - fails, but we will report the failure. */ - prvInitialiseTaskLists(); - } - else - { - /* If the scheduler is not already running, make this task the - current task if it is the highest priority task to be created - so far. */ - if( xSchedulerRunning == pdFALSE ) - { - if( pxCurrentTCB->uxPriority <= uxPriority ) - { - pxCurrentTCB = pxNewTCB; - } - } - } - - /* Remember the top priority to make context switching faster. Use - the priority in pxNewTCB as this has been capped to a valid value. */ - if( pxNewTCB->uxPriority > uxTopUsedPriority ) - { - uxTopUsedPriority = pxNewTCB->uxPriority; - } - - /* Add a counter into the TCB for tracing only. */ - pxNewTCB->uxTCBNumber = uxTaskNumber; - uxTaskNumber++; - - prvAddTaskToReadyQueue( pxNewTCB ); - - xReturn = pdPASS; - } - portEXIT_CRITICAL(); - } - else - { - xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - } - - if( xReturn == pdPASS ) - { - if( ( void * ) pxCreatedTask != NULL ) - { - /* Pass the TCB out - in an anonymous way. The calling function/ - task can use this as a handle to delete the task later if - required.*/ - *pxCreatedTask = ( xTaskHandle ) pxNewTCB; - } - - if( xSchedulerRunning != pdFALSE ) - { - /* If the created task is of a higher priority than the current task - then it should run now. */ - if( pxCurrentTCB->uxPriority < uxPriority ) - { - taskYIELD(); - } - } - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelete == 1 ) - - void vTaskDelete( xTaskHandle pxTaskToDelete ) - { - tskTCB *pxTCB; - - taskENTER_CRITICAL(); - { - /* Ensure a yield is performed if the current task is being - deleted. */ - if( pxTaskToDelete == pxCurrentTCB ) - { - pxTaskToDelete = NULL; - } - - /* If null is passed in here then we are deleting ourselves. */ - pxTCB = prvGetTCBFromHandle( pxTaskToDelete ); - - /* Remove task from the ready list and place in the termination list. - This will stop the task from be scheduled. The idle task will check - the termination list and free up any memory allocated by the - scheduler for the TCB and stack. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Is the task waiting on an event also? */ - if( pxTCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - } - - vListInsertEnd( ( xList * ) &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) ); - - /* Increment the ucTasksDeleted variable so the idle task knows - there is a task that has been deleted and that it should therefore - check the xTasksWaitingTermination list. */ - ++uxTasksDeleted; - } - taskEXIT_CRITICAL(); - - /* Force a reschedule if we have just deleted the current task. */ - if( xSchedulerRunning != pdFALSE ) - { - if( ( void * ) pxTaskToDelete == NULL ) - { - taskYIELD(); - } - } - } - -#endif - - - - - - -/*----------------------------------------------------------- - * TASK CONTROL API documented in task.h - *----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelayUntil == 1 ) - - void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement ) - { - portTickType xTimeToWake; - portBASE_TYPE xAlreadyYielded, xShouldDelay = pdFALSE; - - vTaskSuspendAll(); - { - /* Generate the tick time at which the task wants to wake. */ - xTimeToWake = *pxPreviousWakeTime + xTimeIncrement; - - if( xTickCount < *pxPreviousWakeTime ) - { - /* The tick count has overflowed since this function was - lasted called. In this case the only time we should ever - actually delay is if the wake time has also overflowed, - and the wake time is greater than the tick time. When this - is the case it is as if neither time had overflowed. */ - if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xTickCount ) ) - { - xShouldDelay = pdTRUE; - } - } - else - { - /* The tick time has not overflowed. In this case we will - delay if either the wake time has overflowed, and/or the - tick time is less than the wake time. */ - if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xTickCount ) ) - { - xShouldDelay = pdTRUE; - } - } - - /* Update the wake time ready for the next call. */ - *pxPreviousWakeTime = xTimeToWake; - - if( xShouldDelay ) - { - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - } - xAlreadyYielded = xTaskResumeAll(); - - /* Force a reschedule if xTaskResumeAll has not already done so, we may - have put ourselves to sleep. */ - if( !xAlreadyYielded ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelay == 1 ) - - void vTaskDelay( portTickType xTicksToDelay ) - { - portTickType xTimeToWake; - signed portBASE_TYPE xAlreadyYielded = pdFALSE; - - /* A delay time of zero just forces a reschedule. */ - if( xTicksToDelay > ( portTickType ) 0 ) - { - vTaskSuspendAll(); - { - /* A task that is removed from the event list while the - scheduler is suspended will not get placed in the ready - list or removed from the blocked list until the scheduler - is resumed. - - This task cannot be in an event list as it is the currently - executing task. */ - - /* Calculate the time to wake - this may overflow but this is - not a problem. */ - xTimeToWake = xTickCount + xTicksToDelay; - - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - xAlreadyYielded = xTaskResumeAll(); - } - - /* Force a reschedule if xTaskResumeAll has not already done so, we may - have put ourselves to sleep. */ - if( !xAlreadyYielded ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_uxTaskPriorityGet == 1 ) - - unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ) - { - tskTCB *pxTCB; - unsigned portBASE_TYPE uxReturn; - - taskENTER_CRITICAL(); - { - /* If null is passed in here then we are changing the - priority of the calling function. */ - pxTCB = prvGetTCBFromHandle( pxTask ); - uxReturn = pxTCB->uxPriority; - } - taskEXIT_CRITICAL(); - - return uxReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskPrioritySet == 1 ) - - void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ) - { - tskTCB *pxTCB; - unsigned portBASE_TYPE uxCurrentPriority, xYieldRequired = pdFALSE; - - /* Ensure the new priority is valid. */ - if( uxNewPriority >= configMAX_PRIORITIES ) - { - uxNewPriority = configMAX_PRIORITIES - 1; - } - - taskENTER_CRITICAL(); - { - /* If null is passed in here then we are changing the - priority of the calling function. */ - pxTCB = prvGetTCBFromHandle( pxTask ); - uxCurrentPriority = pxTCB->uxPriority; - - if( uxCurrentPriority != uxNewPriority ) - { - /* The priority change may have readied a task of higher - priority than the calling task. */ - if( uxNewPriority > pxCurrentTCB->uxPriority ) - { - if( pxTask != NULL ) - { - /* The priority of another task is being raised. If we - were raising the priority of the currently running task - there would be no need to switch as it must have already - been the highest priority task. */ - xYieldRequired = pdTRUE; - } - } - else if( pxTask == NULL ) - { - /* Setting our own priority down means there may now be another - task of higher priority that is ready to execute. */ - xYieldRequired = pdTRUE; - } - - pxTCB->uxPriority = uxNewPriority; - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxNewPriority ); - - /* If the task is in the blocked or suspended list we need do - nothing more than change it's priority variable. However, if - the task is in a ready list it needs to be removed and placed - in the queue appropriate to its new priority. */ - if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxCurrentPriority ] ), &( pxTCB->xGenericListItem ) ) ) - { - /* The task is currently in its ready list - remove before adding - it to it's new ready list. As we are in a critical section we - can do this even if the scheduler is suspended. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - } - - if( xYieldRequired == pdTRUE ) - { - taskYIELD(); - } - } - } - taskEXIT_CRITICAL(); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - void vTaskSuspend( xTaskHandle pxTaskToSuspend ) - { - tskTCB *pxTCB; - - taskENTER_CRITICAL(); - { - /* Ensure a yield is performed if the current task is being - suspended. */ - if( pxTaskToSuspend == pxCurrentTCB ) - { - pxTaskToSuspend = NULL; - } - - /* If null is passed in here then we are suspending ourselves. */ - pxTCB = prvGetTCBFromHandle( pxTaskToSuspend ); - - /* Remove task from the ready/delayed list and place in the suspended list. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Is the task waiting on an event also? */ - if( pxTCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - } - - vListInsertEnd( ( xList * ) &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ); - } - taskEXIT_CRITICAL(); - - /* We may have just suspended the current task. */ - if( ( void * ) pxTaskToSuspend == NULL ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - void vTaskResume( xTaskHandle pxTaskToResume ) - { - tskTCB *pxTCB; - - /* Remove the task from whichever list it is currently in, and place - it in the ready list. */ - pxTCB = ( tskTCB * ) pxTaskToResume; - - /* The parameter cannot be NULL as it is impossible to resume the - currently executing task. */ - if( pxTCB != NULL ) - { - taskENTER_CRITICAL(); - { - /* Is the task we are attempting to resume actually suspended? */ - if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE ) - { - /* Has the task already been resumed from within an ISR? */ - if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdTRUE ) - { - /* As we are in a critical section we can access the ready - lists even if the scheduler is suspended. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - - /* We may have just resumed a higher priority task. */ - if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - /* This yield may not cause the task just resumed to run, but - will leave the lists in the correct state for the next yield. */ - taskYIELD(); - } - } - } - } - taskEXIT_CRITICAL(); - } - } - -#endif - -/*-----------------------------------------------------------*/ - -#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ) - { - portBASE_TYPE xYieldRequired = pdFALSE; - tskTCB *pxTCB; - - pxTCB = ( tskTCB * ) pxTaskToResume; - - /* Is the task we are attempting to resume actually suspended? */ - if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE ) - { - /* Has the task already been resumed from within an ISR? */ - if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdTRUE ) - { - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - xYieldRequired = ( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ); - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - } - else - { - /* We cannot access the delayed or ready lists, so will hold this - task pending until the scheduler is resumed, at which point a - yield will be preformed if necessary. */ - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); - } - } - } - - return xYieldRequired; - } - -#endif - - - - -/*----------------------------------------------------------- - * PUBLIC SCHEDULER CONTROL documented in task.h - *----------------------------------------------------------*/ - - -void vTaskStartScheduler( void ) -{ -portBASE_TYPE xReturn; - - /* Add the idle task at the lowest priority. */ - xReturn = xTaskCreate( prvIdleTask, ( signed portCHAR * ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); - - if( xReturn == pdPASS ) - { - /* Interrupts are turned off here, to ensure a tick does not occur - before or during the call to xPortStartScheduler(). The stacks of - the created tasks contain a status word with interrupts switched on - so interrupts will automatically get re-enabled when the first task - starts to run. - - STEPPING THROUGH HERE USING A DEBUGGER CAN CAUSE BIG PROBLEMS IF THE - DEBUGGER ALLOWS INTERRUPTS TO BE PROCESSED. */ - portDISABLE_INTERRUPTS(); - - xSchedulerRunning = pdTRUE; - xTickCount = ( portTickType ) 0; - - /* Setting up the timer tick is hardware specific and thus in the - portable interface. */ - if( xPortStartScheduler() ) - { - /* Should not reach here as if the scheduler is running the - function will not return. */ - } - else - { - /* Should only reach here if a task calls xTaskEndScheduler(). */ - } - } -} -/*-----------------------------------------------------------*/ - -void vTaskEndScheduler( void ) -{ - /* Stop the scheduler interrupts and call the portable scheduler end - routine so the original ISRs can be restored if necessary. The port - layer must ensure interrupts enable bit is left in the correct state. */ - portDISABLE_INTERRUPTS(); - xSchedulerRunning = pdFALSE; - vPortEndScheduler(); -} -/*----------------------------------------------------------*/ - -void vTaskSuspendAll( void ) -{ - portENTER_CRITICAL(); - ++uxSchedulerSuspended; - portEXIT_CRITICAL(); -} -/*----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskResumeAll( void ) -{ -register tskTCB *pxTCB; -signed portBASE_TYPE xAlreadyYielded = pdFALSE; - - /* It is possible that an ISR caused a task to be removed from an event - list while the scheduler was suspended. If this was the case then the - removed task will have been added to the xPendingReadyList. Once the - scheduler has been resumed it is safe to move all the pending ready - tasks from this list into their appropriate ready list. */ - portENTER_CRITICAL(); - { - --uxSchedulerSuspended; - - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - if( uxCurrentNumberOfTasks > ( unsigned portBASE_TYPE ) 0 ) - { - portBASE_TYPE xYieldRequired = pdFALSE; - - /* Move any readied tasks from the pending list into the - appropriate ready list. */ - while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xPendingReadyList ) ) ) != NULL ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - - /* If we have moved a task that has a priority higher than - the current task then we should yield. */ - if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - xYieldRequired = pdTRUE; - } - } - - /* If any ticks occurred while the scheduler was suspended then - they should be processed now. This ensures the tick count does not - slip, and that any delayed tasks are resumed at the correct time. */ - if( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) - { - while( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) - { - vTaskIncrementTick(); - --uxMissedTicks; - } - - /* As we have processed some ticks it is appropriate to yield - to ensure the highest priority task that is ready to run is - the task actually running. */ - xYieldRequired = pdTRUE; - } - - if( ( xYieldRequired == pdTRUE ) || ( xMissedYield == pdTRUE ) ) - { - xAlreadyYielded = pdTRUE; - xMissedYield = pdFALSE; - taskYIELD(); - } - } - } - } - portEXIT_CRITICAL(); - - return xAlreadyYielded; -} - - - - - - -/*----------------------------------------------------------- - * PUBLIC TASK UTILITIES documented in task.h - *----------------------------------------------------------*/ - - - -portTickType xTaskGetTickCount( void ) -{ -portTickType xTicks; - - /* Critical section required if running on a 16 bit processor. */ - taskENTER_CRITICAL(); - { - xTicks = xTickCount; - } - taskEXIT_CRITICAL(); - - return xTicks; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ) -{ -unsigned portBASE_TYPE uxNumberOfTasks; - - taskENTER_CRITICAL(); - uxNumberOfTasks = uxCurrentNumberOfTasks; - taskEXIT_CRITICAL(); - - return uxNumberOfTasks; -} -/*-----------------------------------------------------------*/ - -#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_vTaskDelete == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - void vTaskList( signed portCHAR *pcWriteBuffer ) - { - unsigned portBASE_TYPE uxQueue; - - /* This is a VERY costly function that should be used for debug only. - It leaves interrupts disabled for a LONG time. */ - - vTaskSuspendAll(); - { - /* Run through all the lists that could potentially contain a TCB and - report the task name, state and stack high water mark. */ - - pcWriteBuffer[ 0 ] = ( signed portCHAR ) 0x00; - strcat( ( portCHAR * ) pcWriteBuffer, ( const portCHAR * ) "\r\n" ); - - uxQueue = uxTopUsedPriority + 1; - - do - { - uxQueue--; - - if( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), tskREADY_CHAR ); - } - }while( uxQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); - - if( !listLIST_IS_EMPTY( pxDelayedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, tskBLOCKED_CHAR ); - } - - if( !listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, tskBLOCKED_CHAR ); - } - - if( !listLIST_IS_EMPTY( &xTasksWaitingTermination ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xTasksWaitingTermination, tskDELETED_CHAR ); - } - - if( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xSuspendedTaskList, tskSUSPENDED_CHAR ); - } - } - xTaskResumeAll(); - } - -#endif -/*----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ) - { - portENTER_CRITICAL(); - { - pcTraceBuffer = ( volatile signed portCHAR * volatile )pcBuffer; - pcTraceBufferStart = pcBuffer; - pcTraceBufferEnd = pcBuffer + ( ulBufferSize - tskSIZE_OF_EACH_TRACE_LINE ); - xTracing = pdTRUE; - } - portEXIT_CRITICAL(); - } - -#endif -/*----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - unsigned portLONG ulTaskEndTrace( void ) - { - unsigned portLONG ulBufferLength; - - portENTER_CRITICAL(); - xTracing = pdFALSE; - portEXIT_CRITICAL(); - - ulBufferLength = ( unsigned portLONG ) ( pcTraceBuffer - pcTraceBufferStart ); - - return ulBufferLength; - } - -#endif - - - -/*----------------------------------------------------------- - * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES - * documented in task.h - *----------------------------------------------------------*/ - - -inline void vTaskIncrementTick( void ) -{ - /* Called by the portable layer each time a tick interrupt occurs. - Increments the tick then checks to see if the new tick value will cause any - tasks to be unblocked. */ - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - ++xTickCount; - if( xTickCount == ( portTickType ) 0 ) - { - xList *pxTemp; - - /* Tick count has overflowed so we need to swap the delay lists. - If there are any items in pxDelayedTaskList here then there is - an error! */ - pxTemp = pxDelayedTaskList; - pxDelayedTaskList = pxOverflowDelayedTaskList; - pxOverflowDelayedTaskList = pxTemp; - } - - /* See if this tick has made a timeout expire. */ - prvCheckDelayedTasks(); - } - else - { - ++uxMissedTicks; - - /* The tick hook gets called at regular intervals, even if the - scheduler is locked. */ - #if ( configUSE_TICK_HOOK == 1 ) - { - extern void vApplicationTickHook( void ); - - vApplicationTickHook(); - } - #endif - } - - #if ( configUSE_TICK_HOOK == 1 ) - { - extern void vApplicationTickHook( void ); - - /* Guard against the tick hook being called when the missed tick - count is being unwound (when the scheduler is being unlocked. */ - if( uxMissedTicks == 0 ) - { - vApplicationTickHook(); - } - } - #endif -} -/*-----------------------------------------------------------*/ - -#if ( ( INCLUDE_vTaskCleanUpResources == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - void vTaskCleanUpResources( void ) - { - unsigned portSHORT usQueue; - volatile tskTCB *pxTCB; - - usQueue = ( unsigned portSHORT ) uxTopUsedPriority + ( unsigned portSHORT ) 1; - - /* Remove any TCB's from the ready queues. */ - do - { - usQueue--; - - while( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ usQueue ] ) ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &( pxReadyTasksLists[ usQueue ] ) ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - }while( usQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); - - /* Remove any TCB's from the delayed queue. */ - while( !listLIST_IS_EMPTY( &xDelayedTaskList1 ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList1 ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - /* Remove any TCB's from the overflow delayed queue. */ - while( !listLIST_IS_EMPTY( &xDelayedTaskList2 ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList2 ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - while( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xSuspendedTaskList ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - while( !listLIST_IS_EMPTY( &xPendingReadyList ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xPendingReadyList ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - } - -#endif -/*-----------------------------------------------------------*/ - -void vTaskSwitchContext( void ) -{ - if( uxSchedulerSuspended != ( unsigned portBASE_TYPE ) pdFALSE ) - { - /* The scheduler is currently suspended - do not allow a context - switch. */ - xMissedYield = pdTRUE; - return; - } - - /* Find the highest priority queue that contains ready tasks. */ - while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) ) - { - --uxTopReadyPriority; - } - - /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the tasks of the - same priority get an equal share of the processor time. */ - listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) ); - vWriteTraceToBuffer(); -} -/*-----------------------------------------------------------*/ - -void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait ) -{ -portTickType xTimeToWake; - - /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE - SCHEDULER SUSPENDED. */ - - /* Place the event list item of the TCB in the appropriate event list. - This is placed in the list in priority order so the highest priority task - is the first to be woken by the event. */ - vListInsert( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) ); - - /* Calculate the time at which the task should be woken if the event does - not occur. This may overflow but this doesn't matter. */ - xTimeToWake = xTickCount + xTicksToWait; - - /* We must remove ourselves from the ready list before adding ourselves - to the blocked list as the same list item is used for both lists. We have - exclusive access to the ready lists as the scheduler is locked. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList ) -{ -tskTCB *pxUnblockedTCB; -portBASE_TYPE xReturn; - - /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE - SCHEDULER SUSPENDED. It can also be called from within an ISR. */ - - /* The event list is sorted in priority order, so we can remove the - first in the list, remove the TCB from the delayed list, and add - it to the ready list. - - If an event is for a queue that is locked then this function will never - get called - the lock count on the queue will get modified instead. This - means we can always expect exclusive access to the event list here. */ - pxUnblockedTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); - vListRemove( &( pxUnblockedTCB->xEventListItem ) ); - - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - vListRemove( &( pxUnblockedTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxUnblockedTCB ); - } - else - { - /* We cannot access the delayed or ready lists, so will hold this - task pending until the scheduler is resumed. */ - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); - } - - if( pxUnblockedTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - /* Return true if the task removed from the event list has - a higher priority than the calling task. This allows - the calling task to know if it should force a context - switch now. */ - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} - - - - - -/* - * ----------------------------------------------------------- - * The Idle task. - * ---------------------------------------------------------- - * - * The portTASK_FUNCTION() macro is used to allow port/compiler specific - * language extensions. The equivalent prototype for this function is: - * - * void prvIdleTask( void *pvParameters ); - * - */ -static portTASK_FUNCTION( prvIdleTask, pvParameters ) -{ - /* Stop warnings. */ - ( void ) pvParameters; - - for( ;; ) - { - /* See if any tasks have been deleted. */ - prvCheckTasksWaitingTermination(); - - #if ( configUSE_PREEMPTION == 0 ) - { - /* If we are not using preemption we keep forcing a task switch to - see if any other task has become available. If we are using - preemption we don't need to do this as any task becoming available - will automatically get the processor anyway. */ - taskYIELD(); - } - #endif - - #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) - { - /* When using preemption tasks of equal priority will be - timesliced. If a task that is sharing the idle priority is ready - to run then the idle task should yield before the end of the - timeslice. - - A critical region is not required here as we are just reading from - the list, and an occasional incorrect value will not matter. If - the ready list at the idle priority contains more than one task - then a task other than the idle task is ready to execute. */ - if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( unsigned portBASE_TYPE ) 1 ) - { - taskYIELD(); - } - } - #endif - - #if ( configUSE_IDLE_HOOK == 1 ) - { - extern void vApplicationIdleHook( void ); - - /* Call the user defined function from within the idle task. This - allows the application designer to add background functionality - without the overhead of a separate task. - NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, - CALL A FUNCTION THAT MIGHT BLOCK. */ - vApplicationIdleHook(); - } - #endif - } -} /*lint !e715 pvParameters is not accessed but all task functions require the same prototype. */ - - - - - - - -/*----------------------------------------------------------- - * File private functions documented at the top of the file. - *----------------------------------------------------------*/ - - - -static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ) -{ - pxTCB->usStackDepth = usStackDepth; - - /* Store the function name in the TCB. */ - strncpy( ( char * ) pxTCB->pcTaskName, ( const char * ) pcName, ( unsigned portSHORT ) configMAX_TASK_NAME_LEN ); - pxTCB->pcTaskName[ ( unsigned portSHORT ) configMAX_TASK_NAME_LEN - ( unsigned portSHORT ) 1 ] = '\0'; - - /* This is used as an array index so must ensure it's not too large. */ - if( uxPriority >= configMAX_PRIORITIES ) - { - uxPriority = configMAX_PRIORITIES - 1; - } - - pxTCB->uxPriority = uxPriority; - - vListInitialiseItem( &( pxTCB->xGenericListItem ) ); - vListInitialiseItem( &( pxTCB->xEventListItem ) ); - - /* Set the pxTCB as a link back from the xListItem. This is so we can get - back to the containing TCB from a generic item in a list. */ - listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB ); - - /* Event lists are always in priority order. */ - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); - listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB ); -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseTaskLists( void ) -{ -unsigned portBASE_TYPE uxPriority; - - for( uxPriority = 0; uxPriority < configMAX_PRIORITIES; uxPriority++ ) - { - vListInitialise( ( xList * ) &( pxReadyTasksLists[ uxPriority ] ) ); - } - - vListInitialise( ( xList * ) &xDelayedTaskList1 ); - vListInitialise( ( xList * ) &xDelayedTaskList2 ); - vListInitialise( ( xList * ) &xPendingReadyList ); - - #if ( INCLUDE_vTaskDelete == 1 ) - { - vListInitialise( ( xList * ) &xTasksWaitingTermination ); - } - #endif - - #if ( INCLUDE_vTaskSuspend == 1 ) - { - vListInitialise( ( xList * ) &xSuspendedTaskList ); - } - #endif - - /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList - using list2. */ - pxDelayedTaskList = &xDelayedTaskList1; - pxOverflowDelayedTaskList = &xDelayedTaskList2; -} -/*-----------------------------------------------------------*/ - -static void prvCheckTasksWaitingTermination( void ) -{ - #if ( INCLUDE_vTaskDelete == 1 ) - { - portBASE_TYPE xListIsEmpty; - - /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called - too often in the idle task. */ - if( uxTasksDeleted > ( unsigned portBASE_TYPE ) 0 ) - { - vTaskSuspendAll(); - xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination ); - xTaskResumeAll(); - - if( !xListIsEmpty ) - { - tskTCB *pxTCB; - - portENTER_CRITICAL(); - { - pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xTasksWaitingTermination ) ); - vListRemove( &( pxTCB->xGenericListItem ) ); - --uxCurrentNumberOfTasks; - --uxTasksDeleted; - } - portEXIT_CRITICAL(); - - prvDeleteTCB( pxTCB ); - } - } - } - #endif -} -/*-----------------------------------------------------------*/ - -static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ) -{ -tskTCB *pxNewTCB; - - /* Allocate space for the TCB. Where the memory comes from depends on - the implementation of the port malloc function. */ - pxNewTCB = ( tskTCB * ) pvPortMalloc( sizeof( tskTCB ) ); - - if( pxNewTCB != NULL ) - { - /* Allocate space for the stack used by the task being created. - The base of the stack memory stored in the TCB so the task can - be deleted later if required. */ - pxNewTCB->pxStack = ( portSTACK_TYPE * ) pvPortMalloc( ( ( size_t )usStackDepth ) * sizeof( portSTACK_TYPE ) ); - - if( pxNewTCB->pxStack == NULL ) - { - /* Could not allocate the stack. Delete the allocated TCB. */ - vPortFree( pxNewTCB ); - pxNewTCB = NULL; - } - else - { - /* Just to help debugging. */ - memset( pxNewTCB->pxStack, tskSTACK_FILL_BYTE, usStackDepth * sizeof( portSTACK_TYPE ) ); - } - } - - return pxNewTCB; -} -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ) - { - volatile tskTCB *pxNextTCB, *pxFirstTCB; - static portCHAR pcStatusString[ 50 ]; - unsigned portSHORT usStackRemaining; - - /* Write the details of all the TCB's in pxList into the buffer. */ - listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); - do - { - listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); - usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned portCHAR * ) pxNextTCB->pxStack ); - sprintf( pcStatusString, ( portCHAR * ) "%s\t\t%c\t%u\t%u\t%u\r\n", pxNextTCB->pcTaskName, cStatus, ( unsigned int ) pxNextTCB->uxPriority, usStackRemaining, ( unsigned int ) pxNextTCB->uxTCBNumber ); - strcat( ( portCHAR * ) pcWriteBuffer, ( portCHAR * ) pcStatusString ); - - } while( pxNextTCB != pxFirstTCB ); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte ) - { - register unsigned portSHORT usCount = 0; - - while( *pucStackByte == tskSTACK_FILL_BYTE ) - { - pucStackByte -= portSTACK_GROWTH; - usCount++; - } - - usCount /= sizeof( portSTACK_TYPE ); - - return usCount; - } -#endif -/*-----------------------------------------------------------*/ - - - -#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) - - static void prvDeleteTCB( tskTCB *pxTCB ) - { - /* Free up the memory allocated by the scheduler for the task. It is up to - the task to free any memory allocated at the application level. */ - vPortFree( pxTCB->pxStack ); - vPortFree( pxTCB ); - } - -#endif - - -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) - - xTaskHandle xTaskGetCurrentTaskHandle( void ) - { - xTaskHandle xReturn; - - portENTER_CRITICAL(); - { - xReturn = ( xTaskHandle ) pxCurrentTCB; - } - portEXIT_CRITICAL(); - - return xReturn; - } - -#endif - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/FreeRTOSConfig.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/FreeRTOSConfig.h deleted file mode 100644 index 3656e12df..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/FreeRTOSConfig.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. - MCF5235 Port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetCurrentTaskHandle 1 - -#endif /* FREERTOS_CONFIG_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/m523xbcc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/m523xbcc.h deleted file mode 100644 index b8b0459d9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/m523xbcc.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * File: m523xbcc.h - * Purpose: Evaluation board definitions and memory map information - * - * Notes: - */ - -#ifndef _M523XBCC_H -#define _M523XBCC_H - -/********************************************************************/ - -#include "mcf5xxx.h" -#include "mcf523x.h" -#include "io.h" - -/********************************************************************/ - -/* - * Debug prints ON (#undef) or OFF (#define) - */ -#undef DEBUG - -/* - * System Bus Clock Info - */ -#define SYSTEM_CLOCK 75 /* system bus frequency in MHz */ -#define PERIOD 13.33 /* system bus period in ns */ - -/* - * Flash Device Info - */ -#define AMD_FLASH_AM29PL160CB_16BIT - -/* - * Ethernet Port Info - */ -#define FEC_PHY0 (0x01) - -/* - * Memory map definitions from linker command files - */ -extern uint8 __IPSBAR[]; -extern uint8 __SDRAM[]; -extern uint8 __SDRAM_SIZE[]; -extern uint8 __SRAM[]; -extern uint8 __SRAM_SIZE[]; -extern uint8 __EXT_FLASH[]; -extern uint8 __EXT_FLASH_SIZE[]; - -/* - * Memory Map Info - */ -#define IPSBAR_ADDRESS (uint32)__IPSBAR - -#define SDRAM_ADDRESS (uint32)__SDRAM -#define SDRAM_SIZE (uint32)__SDRAM_SIZE - -#define SRAM_ADDRESS (uint32)__SRAM -#define SRAM_SIZE (uint32)__SRAM_SIZE - -#define EXT_FLASH_ADDRESS (uint32)__EXT_FLASH -#define EXT_FLASH_SIZE (uint32)__EXT_FLASH_SIZE - -/* - * Interrupt Controller Definitions - */ -#define TIMER_NETWORK_LEVEL 3 -#define FEC_LEVEL 4 - -/* - * Timer period info - */ -#define TIMER_NETWORK_PERIOD 1000000000/0x10000 /* 1 sec / max timeout */ - -/********************************************************************/ - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x.h deleted file mode 100644 index ca131c5bb..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x.h +++ /dev/null @@ -1,53 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_H__ -#define __MCF523X_H__ - -/*********************************************************************/ - -#include "mcf523x_fec.h" -#include "mcf523x_rng.h" -#include "mcf523x_fmpll.h" -#include "mcf523x_cs.h" -#include "mcf523x_intc0.h" -#include "mcf523x_intc1.h" -#include "mcf523x_sdramc.h" -#include "mcf523x_sram.h" -#include "mcf523x_uart.h" -#include "mcf523x_timer.h" -#include "mcf523x_qspi.h" -#include "mcf523x_eport.h" -#include "mcf523x_i2c.h" -#include "mcf523x_scm.h" -#include "mcf523x_pit.h" -#include "mcf523x_can.h" -#include "mcf523x_wtm.h" -#include "mcf523x_gpio.h" -#include "mcf523x_mdha.h" -#include "mcf523x_ccm.h" -#include "mcf523x_rcm.h" -#include "mcf523x_etpu.h" -#include "mcf523x_etpu_struc.h" - - - - -/********************************************************************/ - -#endif /* __MCF523X_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/descriptors.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/descriptors.h deleted file mode 100644 index 2543f90b8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/descriptors.h +++ /dev/null @@ -1,140 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * USB Descriptors definitions. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - - -#ifndef DESCRIPTOR_H -#define DESCRIPTOR_H - -/********************************************************************/ - -/* USB descriptor types */ -#define DEVICE 1 -#define CONFIGURATION 2 -#define STRING 3 -#define INTERFACE 4 -#define ENDPOINT 5 - -/* USB Standard Request Types - bRequestType */ -#define IN 0x80 -#define OUT 0x00 -#define STANDARD 0x00 -#define CLASS 0x20 -#define VENDOR 0x40 -#define RQ_DEVICE 0x00 -#define RQ_INTERFACE 0x01 -#define RQ_ENDPOINT 0x02 - -/* USB Standard Request Codes - bRequest */ -#define GET_STATUS 0 -#define CLEAR_FEATURE 1 -#define SET_FEATURE 3 -#define SET_ADDRESS 5 -#define GET_DESCRIPTOR 6 -#define SET_DESCRIPTOR 7 -#define GET_CONFIGURATION 8 -#define SET_CONFIGURATION 9 -#define GET_INTERFACE 10 -#define SET_INTERFACE 11 -#define SYNCH_FRAME 12 - -/* Configuration bmAttributes fields */ -#define BUS_POWERED 0x80 -#define SELF_POWERED 0xC0 -#define REMOTE_WAKEUP 0xA0 - -/* Endpoint bmAttributes fields */ -#define CONTROL 0x00 -#define ISOCHRONOUS 0x01 -#define BULK 0x02 -#define INTERRUPT 0x03 -#define DISABLED 0xFF - -/* Standard Feature Selectors */ -#define DEVICE_REMOTE_WAKEUP 1 -#define ENDPOINT_HALT 0 - -/* Structure for USB Device Descriptors */ -typedef struct { - uint8 bLength; - uint8 bDescriptorType; - uint8 bcdUSBL; - uint8 bcdUSBH; - uint8 bDeviceClass; - uint8 bDeviceSubClass; - uint8 bDeviceProtocol; - uint8 bMaxPacketSize0; - uint8 idVendorL; - uint8 idVendorH; - uint8 idProductL; - uint8 idProductH; - uint8 bcdDeviceL; - uint8 bcdDeviceH; - uint8 iManufacturer; - uint8 iProduct; - uint8 iSerialNumber; - uint8 bNumConfigurations; -} USB_DEVICE_DESC; - -/* Structure for USB Configuration Descriptors */ -typedef struct { - uint8 bLength; - uint8 bDescriptorType; - uint8 wTotalLengthL; - uint8 wTotalLengthH; - uint8 bNumInterfaces; - uint8 bConfigurationValue; - uint8 iConfiguration; - uint8 bmAttributes; - uint8 maxPower; -} USB_CONFIG_DESC; - -/* Structure for USB Interface Descriptors */ -typedef struct { - uint8 bLength; - uint8 bDescriptorType; - uint8 bInterfaceNumber; - uint8 bAlternateSetting; - uint8 bNumEndpoints; - uint8 bInterfaceClass; - uint8 bInterfaceSubClass; - uint8 bInterfaceProtocol; - uint8 iInterface; -} USB_INTERFACE_DESC; - -/* Structure for USB Endpoint Descriptors */ -typedef struct { - uint8 bLength; - uint8 bDescriptorType; - uint8 bEndpointAddress; - uint8 bmAttributes; - uint8 wMaxPacketSizeL; - uint8 wMaxPacketSizeH; - uint8 bInterval; -} USB_ENDPOINT_DESC; - -/* Structure for USB String Descriptors */ -typedef struct { - uint8 bLength; - uint8 bDescriptorType; - uint8 * bString; -} USB_STRING_DESC; - -/********************************************************************/ - -#endif /* DESCRIPTOR_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_can.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_can.h deleted file mode 100644 index 31ca71c6d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_can.h +++ /dev/null @@ -1,329 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_CAN_H__ -#define __MCF523X_CAN_H__ - -/********************************************************************* -* -* FlexCAN Module (CAN) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CAN_CANMCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0000])) -#define MCF_CAN_CANCTRL0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0004])) -#define MCF_CAN_TIMER0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0008])) -#define MCF_CAN_RXGMASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0010])) -#define MCF_CAN_RX14MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0014])) -#define MCF_CAN_RX15MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0018])) -#define MCF_CAN_ERRCNT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C001C])) -#define MCF_CAN_ERRSTAT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0020])) -#define MCF_CAN_IMASK0 (*(vuint16*)(void*)(&__IPSBAR[0x1C002A])) -#define MCF_CAN_IFLAG0 (*(vuint16*)(void*)(&__IPSBAR[0x1C0032])) -#define MCF_CAN_CANMCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0000])) -#define MCF_CAN_CANCTRL1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0004])) -#define MCF_CAN_TIMER1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0008])) -#define MCF_CAN_RXGMASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0010])) -#define MCF_CAN_RX14MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0014])) -#define MCF_CAN_RX15MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0018])) -#define MCF_CAN_ERRCNT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F001C])) -#define MCF_CAN_ERRSTAT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0020])) -#define MCF_CAN_IMASK1 (*(vuint16*)(void*)(&__IPSBAR[0x1F002A])) -#define MCF_CAN_IFLAG1 (*(vuint16*)(void*)(&__IPSBAR[0x1F0032])) -#define MCF_CAN_CANMCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0000+((x)*0x30000)])) -#define MCF_CAN_CANCTRL(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0004+((x)*0x30000)])) -#define MCF_CAN_TIMER(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0008+((x)*0x30000)])) -#define MCF_CAN_RXGMASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0010+((x)*0x30000)])) -#define MCF_CAN_RX14MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0014+((x)*0x30000)])) -#define MCF_CAN_RX15MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0018+((x)*0x30000)])) -#define MCF_CAN_ERRCNT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C001C+((x)*0x30000)])) -#define MCF_CAN_ERRSTAT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0020+((x)*0x30000)])) -#define MCF_CAN_IMASK(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C002A+((x)*0x30000)])) -#define MCF_CAN_IFLAG(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C0032+((x)*0x30000)])) - -#define MCF_CAN_MBUF0_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0080+((x)*0x30000)])) -#define MCF_CAN_MBUF0_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0082+((x)*0x30000)])) -#define MCF_CAN_MBUF0_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0084+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0089+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008A+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008B+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008D+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008E+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008F+((x)*0x30000)])) -#define MCF_CAN_MBUF1_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0090+((x)*0x30000)])) -#define MCF_CAN_MBUF1_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0092+((x)*0x30000)])) -#define MCF_CAN_MBUF1_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0094+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0099+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009A+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009B+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009D+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009E+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009F+((x)*0x30000)])) -#define MCF_CAN_MBUF2_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00A0+((x)*0x30000)])) -#define MCF_CAN_MBUF2_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A4+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A9+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AA+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AB+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AD+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AE+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AF+((x)*0x30000)])) -#define MCF_CAN_MBUF3_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00B0+((x)*0x30000)])) -#define MCF_CAN_MBUF3_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00B4+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B8+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B9+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BA+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BB+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BC+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BD+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BE+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BF+((x)*0x30000)])) -#define MCF_CAN_MBUF4_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00C0+((x)*0x30000)])) -#define MCF_CAN_MBUF4_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00C4+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C8+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C9+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CA+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CB+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CC+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CD+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CE+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CF+((x)*0x30000)])) -#define MCF_CAN_MBUF5_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00D0+((x)*0x30000)])) -#define MCF_CAN_MBUF5_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00D4+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D8+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D9+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DA+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DB+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DC+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DD+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DE+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DF+((x)*0x30000)])) -#define MCF_CAN_MBUF6_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00E0+((x)*0x30000)])) -#define MCF_CAN_MBUF6_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00E4+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E8+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E9+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EA+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EB+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EC+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00ED+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EE+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EF+((x)*0x30000)])) -#define MCF_CAN_MBUF7_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00F0+((x)*0x30000)])) -#define MCF_CAN_MBUF7_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00F4+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F8+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F9+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FA+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FB+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FC+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FD+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FE+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FF+((x)*0x30000)])) -#define MCF_CAN_MBUF8_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)])) -#define MCF_CAN_MBUF8_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0104+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0108+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0109+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010A+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010B+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010C+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010D+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010E+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010F+((x)*0x30000)])) -#define MCF_CAN_MBUF9_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)])) -#define MCF_CAN_MBUF9_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0114+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0118+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0119+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011A+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011B+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011C+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011D+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011E+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011F+((x)*0x30000)])) -#define MCF_CAN_MBUF10_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0120+((x)*0x30000)])) -#define MCF_CAN_MBUF10_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0124+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0128+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0129+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012A+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012B+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012C+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012D+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012E+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012F+((x)*0x30000)])) -#define MCF_CAN_MBUF11_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0130+((x)*0x30000)])) -#define MCF_CAN_MBUF11_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0134+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0138+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0139+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013A+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013B+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013C+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013D+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013E+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013F+((x)*0x30000)])) -#define MCF_CAN_MBUF12_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0140+((x)*0x30000)])) -#define MCF_CAN_MBUF12_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0144+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0148+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0149+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014A+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014B+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014C+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014D+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014E+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014F+((x)*0x30000)])) -#define MCF_CAN_MBUF13_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0150+((x)*0x30000)])) -#define MCF_CAN_MBUF13_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0154+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0158+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0159+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015A+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015B+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015C+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015D+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015E+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015F+((x)*0x30000)])) -#define MCF_CAN_MBUF14_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0160+((x)*0x30000)])) -#define MCF_CAN_MBUF14_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0164+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0168+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0169+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016A+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016B+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016C+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016D+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016E+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016F+((x)*0x30000)])) -#define MCF_CAN_MBUF15_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0170+((x)*0x30000)])) -#define MCF_CAN_MBUF15_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0174+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0178+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0179+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017A+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017B+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017C+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017D+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017E+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017F+((x)*0x30000)])) - - -#define MCF_CAN_MBUF0_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)])) -#define MCF_CAN_MBUF0_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)])) -#define MCF_CAN_MBUF1_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)])) -#define MCF_CAN_MBUF1_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)])) -#define MCF_CAN_MBUF2_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)])) -#define MCF_CAN_MBUF2_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)])) - - -/* Bit definitions and macros for MCF_CAN_CANMCR */ -#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) -#define MCF_CAN_CANMCR_SUPV (0x00800000) -#define MCF_CAN_CANMCR_FRZACK (0x01000000) -#define MCF_CAN_CANMCR_SOFTRST (0x02000000) -#define MCF_CAN_CANMCR_HALT (0x10000000) -#define MCF_CAN_CANMCR_FRZ (0x40000000) -#define MCF_CAN_CANMCR_MDIS (0x80000000) - -/* Bit definitions and macros for MCF_CAN_CANCTRL */ -#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) -#define MCF_CAN_CANCTRL_LOM (0x00000008) -#define MCF_CAN_CANCTRL_LBUF (0x00000010) -#define MCF_CAN_CANCTRL_TSYNC (0x00000020) -#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) -#define MCF_CAN_CANCTRL_SAMP (0x00000080) -#define MCF_CAN_CANCTRL_LPB (0x00001000) -#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) -#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) -#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) -#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) -#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) -#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) -#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_CAN_TIMER */ -#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RXGMASK */ -#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX14MASK */ -#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX15MASK */ -#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_ERRCNT */ -#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) -#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) - -/* Bit definitions and macros for MCF_CAN_ERRSTAT */ -#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) -#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) -#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) -#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) -#define MCF_CAN_ERRSTAT_TXRX (0x00000040) -#define MCF_CAN_ERRSTAT_IDLE (0x00000080) -#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) -#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) -#define MCF_CAN_ERRSTAT_STFERR (0x00000400) -#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) -#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) -#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) -#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) -#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) -#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) -#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) - -/* Bit definitions and macros for MCF_CAN_IMASK */ -#define MCF_CAN_IMASK_BUF0M (0x0001) -#define MCF_CAN_IMASK_BUF1M (0x0002) -#define MCF_CAN_IMASK_BUF2M (0x0004) -#define MCF_CAN_IMASK_BUF3M (0x0008) -#define MCF_CAN_IMASK_BUF4M (0x0010) -#define MCF_CAN_IMASK_BUF5M (0x0020) -#define MCF_CAN_IMASK_BUF6M (0x0040) -#define MCF_CAN_IMASK_BUF7M (0x0080) -#define MCF_CAN_IMASK_BUF8M (0x0100) -#define MCF_CAN_IMASK_BUF9M (0x0200) -#define MCF_CAN_IMASK_BUF10M (0x0400) -#define MCF_CAN_IMASK_BUF11M (0x0800) -#define MCF_CAN_IMASK_BUF12M (0x1000) -#define MCF_CAN_IMASK_BUF13M (0x2000) -#define MCF_CAN_IMASK_BUF14M (0x4000) -#define MCF_CAN_IMASK_BUF15M (0x8000) - -/* Bit definitions and macros for MCF_CAN_IFLAG */ -#define MCF_CAN_IFLAG_BUF0I (0x0001) -#define MCF_CAN_IFLAG_BUF1I (0x0002) -#define MCF_CAN_IFLAG_BUF2I (0x0004) -#define MCF_CAN_IFLAG_BUF3I (0x0008) -#define MCF_CAN_IFLAG_BUF4I (0x0010) -#define MCF_CAN_IFLAG_BUF5I (0x0020) -#define MCF_CAN_IFLAG_BUF6I (0x0040) -#define MCF_CAN_IFLAG_BUF7I (0x0080) -#define MCF_CAN_IFLAG_BUF8I (0x0100) -#define MCF_CAN_IFLAG_BUF9I (0x0200) -#define MCF_CAN_IFLAG_BUF10I (0x0400) -#define MCF_CAN_IFLAG_BUF11I (0x0800) -#define MCF_CAN_IFLAG_BUF12I (0x1000) -#define MCF_CAN_IFLAG_BUF13I (0x2000) -#define MCF_CAN_IFLAG_BUF14I (0x4000) -#define MCF_CAN_IFLAG_BUF15I (0x8000) - -/********************************************************************/ - -#endif /* __MCF523X_CAN_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_ccm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_ccm.h deleted file mode 100644 index b13cbc4b9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_ccm.h +++ /dev/null @@ -1,60 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_CCM_H__ -#define __MCF523X_CCM_H__ - -/********************************************************************* -* -* Chip Configuration Module (CCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CCM_CCR (*(vuint16*)(void*)(&__IPSBAR[0x110004])) -#define MCF_CCM_LPCR (*(vuint8 *)(void*)(&__IPSBAR[0x110007])) -#define MCF_CCM_CIR (*(vuint16*)(void*)(&__IPSBAR[0x11000A])) -#define MCF_CCM_RCON (*(vuint16*)(void*)(&__IPSBAR[0x110008])) - -/* Bit definitions and macros for MCF_CCM_CCR */ -#define MCF_CCM_CCR_BMT(x) (((x)&0x0007)<<0) -#define MCF_CCM_CCR_BME (0x0008) -#define MCF_CCM_CCR_SZEN (0x0040) -#define MCF_CCM_CCR_MODE(x) (((x)&0x0007)<<8) - -/* Bit definitions and macros for MCF_CCM_LPCR */ -#define MCF_CCM_LPCR_STPMD(x) (((x)&0x03)<<3) -#define MCF_CCM_LPCR_LPMD(x) (((x)&0x03)<<6) -#define MCF_CCM_LPCR_LPMD_STOP (0xC0) -#define MCF_CCM_LPCR_LPMD_WAIT (0x80) -#define MCF_CCM_LPCR_LPMD_DOZE (0x40) -#define MCF_CCM_LPCR_LPMD_RUN (0x00) - -/* Bit definitions and macros for MCF_CCM_CIR */ -#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0) -#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6) - -/* Bit definitions and macros for MCF_CCM_RCON */ -#define MCF_CCM_RCON_MODE (0x0001) -#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3) -#define MCF_CCM_RCON_RLOAD (0x0020) -#define MCF_CCM_RCON_RCSC(x) (((x)&0x0003)<<8) - -/********************************************************************/ - -#endif /* __MCF523X_CCM_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_cfm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_cfm.h deleted file mode 100644 index 597e1174a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_cfm.h +++ /dev/null @@ -1,63 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_CFM_H__ -#define __MCF523X_CFM_H__ - -/********************************************************************* -* -* Chip Configuration Module (CFM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CFM_CCR (*(vuint16*)(void*)(&__IPSBAR[0x110004])) -#define MCF_CFM_LPCR (*(vuint8 *)(void*)(&__IPSBAR[0x110007])) -#define MCF_CFM_CIR (*(vuint16*)(void*)(&__IPSBAR[0x11000A])) -#define MCF_CFM_RCON (*(vuint16*)(void*)(&__IPSBAR[0x110008])) - -/* Bit definitions and macros for MCF_CFM_CCR */ -#define MCF_CFM_CCR_BMT(x) (((x)&0x0007)<<0) -#define MCF_CFM_CCR_BME (0x0008) -#define MCF_CFM_CCR_SZEN (0x0040) -#define MCF_CFM_CCR_MODE(x) (((x)&0x0007)<<8) -#define MCF_CFM_CCR_MODE(x) ((uint16)(((x)&0x0007)<<8)) -#define MCF_CFM_CCR_BMT(x) ((uint16)(((x)&0x0007))) - -/* Bit definitions and macros for MCF_CFM_LPCR */ -#define MCF_CFM_LPCR_STPMD(x) (((x)&0x03)<<3) -#define MCF_CFM_LPCR_LPMD(x) (((x)&0x03)<<6) -#define MCF_CFM_LPCR_LPMD_STOP (0xC0) -#define MCF_CFM_LPCR_LPMD_WAIT (0x80) -#define MCF_CFM_LPCR_LPMD_DOZE (0x40) -#define MCF_CFM_LPCR_LPMD_RUN (0x00) -#define MCF_CFM_LPCR_STPMD(x) ((uint8)(((x)&0x0003)<<3)) - -/* Bit definitions and macros for MCF_CFM_CIR */ -#define MCF_CFM_CIR_PRN(x) (((x)&0x003F)<<0) -#define MCF_CFM_CIR_PIN(x) (((x)&0x03FF)<<6) - -/* Bit definitions and macros for MCF_CFM_RCON */ -#define MCF_CFM_RCON_MODE (0x0001) -#define MCF_CFM_RCON_BOOTPS(x) (((x)&0x0003)<<3) -#define MCF_CFM_RCON_RLOAD (0x0020) -#define MCF_CFM_RCON_RCSC(x) (((x)&0x0003)<<8) - -/********************************************************************/ - -#endif /* __MCF523X_CFM_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_cs.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_cs.h deleted file mode 100644 index ac5c53fd1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_cs.h +++ /dev/null @@ -1,105 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_CS_H__ -#define __MCF523X_CS_H__ - -/********************************************************************* -* -* Chip Selects (CS) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CS_CSAR0 (*(vuint16*)(void*)(&__IPSBAR[0x000080])) -#define MCF_CS_CSMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000084])) -#define MCF_CS_CSCR0 (*(vuint16*)(void*)(&__IPSBAR[0x00008A])) -#define MCF_CS_CSAR1 (*(vuint16*)(void*)(&__IPSBAR[0x00008C])) -#define MCF_CS_CSMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000090])) -#define MCF_CS_CSCR1 (*(vuint16*)(void*)(&__IPSBAR[0x000096])) -#define MCF_CS_CSAR2 (*(vuint16*)(void*)(&__IPSBAR[0x000098])) -#define MCF_CS_CSMR2 (*(vuint32*)(void*)(&__IPSBAR[0x00009C])) -#define MCF_CS_CSCR2 (*(vuint16*)(void*)(&__IPSBAR[0x0000A2])) -#define MCF_CS_CSAR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000A4])) -#define MCF_CS_CSMR3 (*(vuint32*)(void*)(&__IPSBAR[0x0000A8])) -#define MCF_CS_CSCR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000AE])) -#define MCF_CS_CSAR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000B0])) -#define MCF_CS_CSMR4 (*(vuint32*)(void*)(&__IPSBAR[0x0000B4])) -#define MCF_CS_CSCR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000BA])) -#define MCF_CS_CSAR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000BC])) -#define MCF_CS_CSMR5 (*(vuint32*)(void*)(&__IPSBAR[0x0000C0])) -#define MCF_CS_CSCR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000C6])) -#define MCF_CS_CSAR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000C8])) -#define MCF_CS_CSMR6 (*(vuint32*)(void*)(&__IPSBAR[0x0000CC])) -#define MCF_CS_CSCR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000D2])) -#define MCF_CS_CSAR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000D4])) -#define MCF_CS_CSMR7 (*(vuint32*)(void*)(&__IPSBAR[0x0000D8])) -#define MCF_CS_CSCR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000DE])) -#define MCF_CS_CSAR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000080+((x)*0x00C)])) -#define MCF_CS_CSMR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000084+((x)*0x00C)])) -#define MCF_CS_CSCR(x) (*(vuint16*)(void*)(&__IPSBAR[0x00008A+((x)*0x00C)])) - -/* Bit definitions and macros for MCF_CS_CSAR */ -#define MCF_CS_CSAR_BA(x) ((uint16)(((x)&0xFFFF0000)>>16)) - -/* Bit definitions and macros for MCF_CS_CSMR */ -#define MCF_CS_CSMR_V (0x00000001) -#define MCF_CS_CSMR_UD (0x00000002) -#define MCF_CS_CSMR_UC (0x00000004) -#define MCF_CS_CSMR_SD (0x00000008) -#define MCF_CS_CSMR_SC (0x00000010) -#define MCF_CS_CSMR_CI (0x00000020) -#define MCF_CS_CSMR_AM (0x00000040) -#define MCF_CS_CSMR_WP (0x00000100) -#define MCF_CS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) -#define MCF_CS_CSMR_BAM_4G (0xFFFF0000) -#define MCF_CS_CSMR_BAM_2G (0x7FFF0000) -#define MCF_CS_CSMR_BAM_1G (0x3FFF0000) -#define MCF_CS_CSMR_BAM_1024M (0x3FFF0000) -#define MCF_CS_CSMR_BAM_512M (0x1FFF0000) -#define MCF_CS_CSMR_BAM_256M (0x0FFF0000) -#define MCF_CS_CSMR_BAM_128M (0x07FF0000) -#define MCF_CS_CSMR_BAM_64M (0x03FF0000) -#define MCF_CS_CSMR_BAM_32M (0x01FF0000) -#define MCF_CS_CSMR_BAM_16M (0x00FF0000) -#define MCF_CS_CSMR_BAM_8M (0x007F0000) -#define MCF_CS_CSMR_BAM_4M (0x003F0000) -#define MCF_CS_CSMR_BAM_2M (0x001F0000) -#define MCF_CS_CSMR_BAM_1M (0x000F0000) -#define MCF_CS_CSMR_BAM_1024K (0x000F0000) -#define MCF_CS_CSMR_BAM_512K (0x00070000) -#define MCF_CS_CSMR_BAM_256K (0x00030000) -#define MCF_CS_CSMR_BAM_128K (0x00010000) -#define MCF_CS_CSMR_BAM_64K (0x00000000) - -/* Bit definitions and macros for MCF_CS_CSCR */ -#define MCF_CS_CSCR_SWWS(x) (((x)&0x0007)<<0) -#define MCF_CS_CSCR_BSTW (0x0008) -#define MCF_CS_CSCR_BSTR (0x0010) -#define MCF_CS_CSCR_BEM (0x0020) -#define MCF_CS_CSCR_PS(x) (((x)&0x0003)<<6) -#define MCF_CS_CSCR_AA (0x0100) -#define MCF_CS_CSCR_IWS(x) (((x)&0x000F)<<10) -#define MCF_CS_CSCR_SRWS(x) (((x)&0x0003)<<14) -#define MCF_CS_CSCR_PS_8 (0x0040) -#define MCF_CS_CSCR_PS_16 (0x0080) -#define MCF_CS_CSCR_PS_32 (0x0000) - -/********************************************************************/ - -#endif /* __MCF523X_CS_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_eport.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_eport.h deleted file mode 100644 index 78861a244..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_eport.h +++ /dev/null @@ -1,96 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_EPORT_H__ -#define __MCF523X_EPORT_H__ - -/********************************************************************* -* -* Edge Port Module (EPORT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_EPORT_EPPAR (*(vuint16*)(void*)(&__IPSBAR[0x130000])) -#define MCF_EPORT_EPDDR (*(vuint8 *)(void*)(&__IPSBAR[0x130002])) -#define MCF_EPORT_EPIER (*(vuint8 *)(void*)(&__IPSBAR[0x130003])) -#define MCF_EPORT_EPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130004])) -#define MCF_EPORT_EPPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130005])) -#define MCF_EPORT_EPFR (*(vuint8 *)(void*)(&__IPSBAR[0x130006])) - -/* Bit definitions and macros for MCF_EPORT_EPPAR */ -#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) -#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) -#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) -#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) -#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) -#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) -#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) -#define MCF_EPORT_EPPAR_EPPAx_LEVEL (0) -#define MCF_EPORT_EPPAR_EPPAx_RISING (1) -#define MCF_EPORT_EPPAR_EPPAx_FALLING (2) -#define MCF_EPORT_EPPAR_EPPAx_BOTH (3) - -/* Bit definitions and macros for MCF_EPORT_EPDDR */ -#define MCF_EPORT_EPDDR_EPDD1 (0x02) -#define MCF_EPORT_EPDDR_EPDD2 (0x04) -#define MCF_EPORT_EPDDR_EPDD3 (0x08) -#define MCF_EPORT_EPDDR_EPDD4 (0x10) -#define MCF_EPORT_EPDDR_EPDD5 (0x20) -#define MCF_EPORT_EPDDR_EPDD6 (0x40) -#define MCF_EPORT_EPDDR_EPDD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPIER */ -#define MCF_EPORT_EPIER_EPIE1 (0x02) -#define MCF_EPORT_EPIER_EPIE2 (0x04) -#define MCF_EPORT_EPIER_EPIE3 (0x08) -#define MCF_EPORT_EPIER_EPIE4 (0x10) -#define MCF_EPORT_EPIER_EPIE5 (0x20) -#define MCF_EPORT_EPIER_EPIE6 (0x40) -#define MCF_EPORT_EPIER_EPIE7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPDR */ -#define MCF_EPORT_EPDR_EPD1 (0x02) -#define MCF_EPORT_EPDR_EPD2 (0x04) -#define MCF_EPORT_EPDR_EPD3 (0x08) -#define MCF_EPORT_EPDR_EPD4 (0x10) -#define MCF_EPORT_EPDR_EPD5 (0x20) -#define MCF_EPORT_EPDR_EPD6 (0x40) -#define MCF_EPORT_EPDR_EPD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPPDR */ -#define MCF_EPORT_EPPDR_EPPD1 (0x02) -#define MCF_EPORT_EPPDR_EPPD2 (0x04) -#define MCF_EPORT_EPPDR_EPPD3 (0x08) -#define MCF_EPORT_EPPDR_EPPD4 (0x10) -#define MCF_EPORT_EPPDR_EPPD5 (0x20) -#define MCF_EPORT_EPPDR_EPPD6 (0x40) -#define MCF_EPORT_EPPDR_EPPD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPFR */ -#define MCF_EPORT_EPFR_EPF1 (0x02) -#define MCF_EPORT_EPFR_EPF2 (0x04) -#define MCF_EPORT_EPFR_EPF3 (0x08) -#define MCF_EPORT_EPFR_EPF4 (0x10) -#define MCF_EPORT_EPFR_EPF5 (0x20) -#define MCF_EPORT_EPFR_EPF6 (0x40) -#define MCF_EPORT_EPFR_EPF7 (0x80) - -/********************************************************************/ - -#endif /* __MCF523X_EPORT_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_etpu.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_etpu.h deleted file mode 100644 index 476be9b3f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_etpu.h +++ /dev/null @@ -1,497 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_ETPU_H__ -#define __MCF523X_ETPU_H__ - -/********************************************************************* -* -* enhanced Time Processor Unit (ETPU) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_ETPU_EMCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0000])) -#define MCF_ETPU_ECDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0004])) -#define MCF_ETPU_EMISCCR (*(vuint32*)(void*)(&__IPSBAR[0x1D000C])) -#define MCF_ETPU_ESCMODR (*(vuint32*)(void*)(&__IPSBAR[0x1D0010])) -#define MCF_ETPU_EECR (*(vuint32*)(void*)(&__IPSBAR[0x1D0014])) -#define MCF_ETPU_ETBCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0020])) -#define MCF_ETPU_ETB1R (*(vuint32*)(void*)(&__IPSBAR[0x1D0024])) -#define MCF_ETPU_ETB2R (*(vuint32*)(void*)(&__IPSBAR[0x1D0028])) -#define MCF_ETPU_EREDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D002C])) -#define MCF_ETPU_ECISR (*(vuint32*)(void*)(&__IPSBAR[0x1D0200])) -#define MCF_ETPU_ECDTRSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0210])) -#define MCF_ETPU_ECIOSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0220])) -#define MCF_ETPU_ECDTROSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0230])) -#define MCF_ETPU_ECIER (*(vuint32*)(void*)(&__IPSBAR[0x1D0240])) -#define MCF_ETPU_ECDTRER (*(vuint32*)(void*)(&__IPSBAR[0x1D0250])) -#define MCF_ETPU_ECPSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0280])) -#define MCF_ETPU_ECSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0290])) -#define MCF_ETPU_EC0SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0404])) -#define MCF_ETPU_EC1SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0414])) -#define MCF_ETPU_EC2SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0424])) -#define MCF_ETPU_EC3SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0434])) -#define MCF_ETPU_EC4SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0444])) -#define MCF_ETPU_EC5SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0454])) -#define MCF_ETPU_EC6SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0464])) -#define MCF_ETPU_EC7SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0474])) -#define MCF_ETPU_EC8SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0484])) -#define MCF_ETPU_EC9SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0494])) -#define MCF_ETPU_EC10SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A4])) -#define MCF_ETPU_EC11SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B4])) -#define MCF_ETPU_EC12SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C4])) -#define MCF_ETPU_EC13SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D4])) -#define MCF_ETPU_EC14SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E4])) -#define MCF_ETPU_EC15SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F4])) -#define MCF_ETPU_EC16SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0504])) -#define MCF_ETPU_EC17SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0514])) -#define MCF_ETPU_EC18SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0524])) -#define MCF_ETPU_EC19SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0534])) -#define MCF_ETPU_EC20SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0544])) -#define MCF_ETPU_EC21SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0554])) -#define MCF_ETPU_EC22SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0564])) -#define MCF_ETPU_EC23SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0574])) -#define MCF_ETPU_EC24SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0584])) -#define MCF_ETPU_EC25SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0594])) -#define MCF_ETPU_EC26SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A4])) -#define MCF_ETPU_EC27SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B4])) -#define MCF_ETPU_EC28SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C4])) -#define MCF_ETPU_EC29SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D4])) -#define MCF_ETPU_EC30SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E4])) -#define MCF_ETPU_EC31SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F4])) -#define MCF_ETPU_ECnSCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0404+((x)*0x010)])) -#define MCF_ETPU_EC0CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0400])) -#define MCF_ETPU_EC1CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0410])) -#define MCF_ETPU_EC2CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0420])) -#define MCF_ETPU_EC3CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0430])) -#define MCF_ETPU_EC4CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0440])) -#define MCF_ETPU_EC5CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0450])) -#define MCF_ETPU_EC6CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0460])) -#define MCF_ETPU_EC7CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0470])) -#define MCF_ETPU_EC8CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0480])) -#define MCF_ETPU_EC9CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0490])) -#define MCF_ETPU_EC10CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A0])) -#define MCF_ETPU_EC11CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B0])) -#define MCF_ETPU_EC12CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C0])) -#define MCF_ETPU_EC13CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D0])) -#define MCF_ETPU_EC14CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E0])) -#define MCF_ETPU_EC15CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F0])) -#define MCF_ETPU_EC16CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0500])) -#define MCF_ETPU_EC17CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0510])) -#define MCF_ETPU_EC18CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0520])) -#define MCF_ETPU_EC19CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0530])) -#define MCF_ETPU_EC20CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0540])) -#define MCF_ETPU_EC21CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0550])) -#define MCF_ETPU_EC22CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0560])) -#define MCF_ETPU_EC23CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0570])) -#define MCF_ETPU_EC24CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0580])) -#define MCF_ETPU_EC25CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0590])) -#define MCF_ETPU_EC26CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A0])) -#define MCF_ETPU_EC27CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B0])) -#define MCF_ETPU_EC28CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C0])) -#define MCF_ETPU_EC29CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D0])) -#define MCF_ETPU_EC30CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E0])) -#define MCF_ETPU_EC31CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F0])) -#define MCF_ETPU_ECnCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0400+((x)*0x010)])) -#define MCF_ETPU_EC0HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0408])) -#define MCF_ETPU_EC1HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0418])) -#define MCF_ETPU_EC2HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0428])) -#define MCF_ETPU_EC3HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0438])) -#define MCF_ETPU_EC4HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0448])) -#define MCF_ETPU_EC5HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0458])) -#define MCF_ETPU_EC6HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0468])) -#define MCF_ETPU_EC7HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0478])) -#define MCF_ETPU_EC8HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0488])) -#define MCF_ETPU_EC9HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0498])) -#define MCF_ETPU_EC10HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A8])) -#define MCF_ETPU_EC11HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B8])) -#define MCF_ETPU_EC12HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C8])) -#define MCF_ETPU_EC13HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D8])) -#define MCF_ETPU_EC14HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E8])) -#define MCF_ETPU_EC15HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F8])) -#define MCF_ETPU_EC16HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0508])) -#define MCF_ETPU_EC17HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0518])) -#define MCF_ETPU_EC18HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0528])) -#define MCF_ETPU_EC19HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0538])) -#define MCF_ETPU_EC20HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0548])) -#define MCF_ETPU_EC21HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0558])) -#define MCF_ETPU_EC22HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0568])) -#define MCF_ETPU_EC23HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0578])) -#define MCF_ETPU_EC24HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0588])) -#define MCF_ETPU_EC25HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0598])) -#define MCF_ETPU_EC26HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A8])) -#define MCF_ETPU_EC27HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B8])) -#define MCF_ETPU_EC28HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C8])) -#define MCF_ETPU_EC29HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D8])) -#define MCF_ETPU_EC30HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E8])) -#define MCF_ETPU_EC31HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F8])) -#define MCF_ETPU_ECnHSSR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0408+((x)*0x010)])) - -/* Bit definitions and macros for MCF_ETPU_EMCR */ -#define MCF_ETPU_EMCR_GTBE (0x00000001) -#define MCF_ETPU_EMCR_VIS (0x00000040) -#define MCF_ETPU_EMCR_SCMMISEN (0x00000200) -#define MCF_ETPU_EMCR_SCMMISF (0x00000400) -#define MCF_ETPU_EMCR_SCMSIZE(x) (((x)&0x0000001F)<<16) -#define MCF_ETPU_EMCR_ILF2 (0x01000000) -#define MCF_ETPU_EMCR_ILF1 (0x02000000) -#define MCF_ETPU_EMCR_MGE2 (0x04000000) -#define MCF_ETPU_EMCR_MGE1 (0x08000000) -#define MCF_ETPU_EMCR_GEC (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECDCR */ -#define MCF_ETPU_ECDCR_PARM1(x) (((x)&0x0000007F)<<0) -#define MCF_ETPU_ECDCR_WR (0x00000080) -#define MCF_ETPU_ECDCR_PARM0(x) (((x)&0x0000007F)<<8) -#define MCF_ETPU_ECDCR_PWIDTH (0x00008000) -#define MCF_ETPU_ECDCR_PBASE(x) (((x)&0x000003FF)<<16) -#define MCF_ETPU_ECDCR_CTBASE(x) (((x)&0x0000001F)<<26) -#define MCF_ETPU_ECDCR_STS (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_EECR */ -#define MCF_ETPU_EECR_ETB(x) (((x)&0x0000001F)<<0) -#define MCF_ETPU_EECR_CDFC(x) (((x)&0x00000003)<<14) -#define MCF_ETPU_EECR_FPSK(x) (((x)&0x00000007)<<16) -#define MCF_ETPU_EECR_HLTF (0x00800000) -#define MCF_ETPU_EECR_STF (0x10000000) -#define MCF_ETPU_EECR_MDIS (0x40000000) -#define MCF_ETPU_EECR_FEND (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ETBCR */ -#define MCF_ETPU_ETBCR_TCR1P(x) (((x)&0x000000FF)<<0) -#define MCF_ETPU_ETBCR_TCR1CTL(x) (((x)&0x00000003)<<14) -#define MCF_ETPU_ETBCR_TCR2P(x) (((x)&0x0000003F)<<16) -#define MCF_ETPU_ETBCR_AM (0x02000000) -#define MCF_ETPU_ETBCR_TCRCF(x) (((x)&0x00000003)<<27) -#define MCF_ETPU_ETBCR_TCR2CTL(x) (((x)&0x00000007)<<29) - -/* Bit definitions and macros for MCF_ETPU_ETB1R */ -#define MCF_ETPU_ETB1R_TCR1(x) (((x)&0x00FFFFFF)<<0) - -/* Bit definitions and macros for MCF_ETPU_ETB2R */ -#define MCF_ETPU_ETB2R_TCR2(x) (((x)&0x00FFFFFF)<<0) - -/* Bit definitions and macros for MCF_ETPU_EREDCR */ -#define MCF_ETPU_EREDCR_SRV2(x) (((x)&0x0000000F)<<0) -#define MCF_ETPU_EREDCR_SERVER_ID2(x) (((x)&0x0000000F)<<8) -#define MCF_ETPU_EREDCR_RSC2 (0x00004000) -#define MCF_ETPU_EREDCR_REN2 (0x00008000) -#define MCF_ETPU_EREDCR_SRV1(x) (((x)&0x0000000F)<<16) -#define MCF_ETPU_EREDCR_SERVER_ID1(x) (((x)&0x0000000F)<<24) -#define MCF_ETPU_EREDCR_RSC1 (0x40000000) -#define MCF_ETPU_EREDCR_REN1 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECISR */ -#define MCF_ETPU_ECISR_CIS0 (0x00000001) -#define MCF_ETPU_ECISR_CIS1 (0x00000002) -#define MCF_ETPU_ECISR_CIS2 (0x00000004) -#define MCF_ETPU_ECISR_CIS3 (0x00000008) -#define MCF_ETPU_ECISR_CIS4 (0x00000010) -#define MCF_ETPU_ECISR_CIS5 (0x00000020) -#define MCF_ETPU_ECISR_CIS6 (0x00000040) -#define MCF_ETPU_ECISR_CIS7 (0x00000080) -#define MCF_ETPU_ECISR_CIS8 (0x00000100) -#define MCF_ETPU_ECISR_CIS9 (0x00000200) -#define MCF_ETPU_ECISR_CIS10 (0x00000400) -#define MCF_ETPU_ECISR_CIS11 (0x00000800) -#define MCF_ETPU_ECISR_CIS12 (0x00001000) -#define MCF_ETPU_ECISR_CIS13 (0x00002000) -#define MCF_ETPU_ECISR_CIS14 (0x00004000) -#define MCF_ETPU_ECISR_CIS15 (0x00008000) -#define MCF_ETPU_ECISR_CIS16 (0x00010000) -#define MCF_ETPU_ECISR_CIS17 (0x00020000) -#define MCF_ETPU_ECISR_CIS18 (0x00040000) -#define MCF_ETPU_ECISR_CIS19 (0x00080000) -#define MCF_ETPU_ECISR_CIS20 (0x00100000) -#define MCF_ETPU_ECISR_CIS21 (0x00200000) -#define MCF_ETPU_ECISR_CIS22 (0x00400000) -#define MCF_ETPU_ECISR_CIS23 (0x00800000) -#define MCF_ETPU_ECISR_CIS24 (0x01000000) -#define MCF_ETPU_ECISR_CIS25 (0x02000000) -#define MCF_ETPU_ECISR_CIS26 (0x04000000) -#define MCF_ETPU_ECISR_CIS27 (0x08000000) -#define MCF_ETPU_ECISR_CIS28 (0x10000000) -#define MCF_ETPU_ECISR_CIS29 (0x20000000) -#define MCF_ETPU_ECISR_CIS30 (0x40000000) -#define MCF_ETPU_ECISR_CIS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECDTRSR */ -#define MCF_ETPU_ECDTRSR_DTRS0 (0x00000001) -#define MCF_ETPU_ECDTRSR_DTRS1 (0x00000002) -#define MCF_ETPU_ECDTRSR_DTRS2 (0x00000004) -#define MCF_ETPU_ECDTRSR_DTRS3 (0x00000008) -#define MCF_ETPU_ECDTRSR_DTRS4 (0x00000010) -#define MCF_ETPU_ECDTRSR_DTRS5 (0x00000020) -#define MCF_ETPU_ECDTRSR_DTRS6 (0x00000040) -#define MCF_ETPU_ECDTRSR_DTRS7 (0x00000080) -#define MCF_ETPU_ECDTRSR_DTRS8 (0x00000100) -#define MCF_ETPU_ECDTRSR_DTRS9 (0x00000200) -#define MCF_ETPU_ECDTRSR_DTRS10 (0x00000400) -#define MCF_ETPU_ECDTRSR_DTRS11 (0x00000800) -#define MCF_ETPU_ECDTRSR_DTRS12 (0x00001000) -#define MCF_ETPU_ECDTRSR_DTRS13 (0x00002000) -#define MCF_ETPU_ECDTRSR_DTRS14 (0x00004000) -#define MCF_ETPU_ECDTRSR_DTRS15 (0x00008000) -#define MCF_ETPU_ECDTRSR_DTRS16 (0x00010000) -#define MCF_ETPU_ECDTRSR_DTRS17 (0x00020000) -#define MCF_ETPU_ECDTRSR_DTRS18 (0x00040000) -#define MCF_ETPU_ECDTRSR_DTRS19 (0x00080000) -#define MCF_ETPU_ECDTRSR_DTRS20 (0x00100000) -#define MCF_ETPU_ECDTRSR_DTRS21 (0x00200000) -#define MCF_ETPU_ECDTRSR_DTRS22 (0x00400000) -#define MCF_ETPU_ECDTRSR_DTRS23 (0x00800000) -#define MCF_ETPU_ECDTRSR_DTRS24 (0x01000000) -#define MCF_ETPU_ECDTRSR_DTRS25 (0x02000000) -#define MCF_ETPU_ECDTRSR_DTRS26 (0x04000000) -#define MCF_ETPU_ECDTRSR_DTRS27 (0x08000000) -#define MCF_ETPU_ECDTRSR_DTRS28 (0x10000000) -#define MCF_ETPU_ECDTRSR_DTRS29 (0x20000000) -#define MCF_ETPU_ECDTRSR_DTRS30 (0x40000000) -#define MCF_ETPU_ECDTRSR_DTRS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECIOSR */ -#define MCF_ETPU_ECIOSR_CIOS0 (0x00000001) -#define MCF_ETPU_ECIOSR_CIOS1 (0x00000002) -#define MCF_ETPU_ECIOSR_CIOS2 (0x00000004) -#define MCF_ETPU_ECIOSR_CIOS3 (0x00000008) -#define MCF_ETPU_ECIOSR_CIOS4 (0x00000010) -#define MCF_ETPU_ECIOSR_CIOS5 (0x00000020) -#define MCF_ETPU_ECIOSR_CIOS6 (0x00000040) -#define MCF_ETPU_ECIOSR_CIOS7 (0x00000080) -#define MCF_ETPU_ECIOSR_CIOS8 (0x00000100) -#define MCF_ETPU_ECIOSR_CIOS9 (0x00000200) -#define MCF_ETPU_ECIOSR_CIOS10 (0x00000400) -#define MCF_ETPU_ECIOSR_CIOS11 (0x00000800) -#define MCF_ETPU_ECIOSR_CIOS12 (0x00001000) -#define MCF_ETPU_ECIOSR_CIOS13 (0x00002000) -#define MCF_ETPU_ECIOSR_CIOS14 (0x00004000) -#define MCF_ETPU_ECIOSR_CIOS15 (0x00008000) -#define MCF_ETPU_ECIOSR_CIOS16 (0x00010000) -#define MCF_ETPU_ECIOSR_CIOS17 (0x00020000) -#define MCF_ETPU_ECIOSR_CIOS18 (0x00040000) -#define MCF_ETPU_ECIOSR_CIOS19 (0x00080000) -#define MCF_ETPU_ECIOSR_CIOS20 (0x00100000) -#define MCF_ETPU_ECIOSR_CIOS21 (0x00200000) -#define MCF_ETPU_ECIOSR_CIOS22 (0x00400000) -#define MCF_ETPU_ECIOSR_CIOS23 (0x00800000) -#define MCF_ETPU_ECIOSR_CIOS24 (0x01000000) -#define MCF_ETPU_ECIOSR_CIOS25 (0x02000000) -#define MCF_ETPU_ECIOSR_CIOS26 (0x04000000) -#define MCF_ETPU_ECIOSR_CIOS27 (0x08000000) -#define MCF_ETPU_ECIOSR_CIOS28 (0x10000000) -#define MCF_ETPU_ECIOSR_CIOS29 (0x20000000) -#define MCF_ETPU_ECIOSR_CIOS30 (0x40000000) -#define MCF_ETPU_ECIOSR_CIOS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECDTROSR */ -#define MCF_ETPU_ECDTROSR_DTROS0 (0x00000001) -#define MCF_ETPU_ECDTROSR_DTROS1 (0x00000002) -#define MCF_ETPU_ECDTROSR_DTROS2 (0x00000004) -#define MCF_ETPU_ECDTROSR_DTROS3 (0x00000008) -#define MCF_ETPU_ECDTROSR_DTROS4 (0x00000010) -#define MCF_ETPU_ECDTROSR_DTROS5 (0x00000020) -#define MCF_ETPU_ECDTROSR_DTROS6 (0x00000040) -#define MCF_ETPU_ECDTROSR_DTROS7 (0x00000080) -#define MCF_ETPU_ECDTROSR_DTROS8 (0x00000100) -#define MCF_ETPU_ECDTROSR_DTROS9 (0x00000200) -#define MCF_ETPU_ECDTROSR_DTROS10 (0x00000400) -#define MCF_ETPU_ECDTROSR_DTROS11 (0x00000800) -#define MCF_ETPU_ECDTROSR_DTROS12 (0x00001000) -#define MCF_ETPU_ECDTROSR_DTROS13 (0x00002000) -#define MCF_ETPU_ECDTROSR_DTROS14 (0x00004000) -#define MCF_ETPU_ECDTROSR_DTROS15 (0x00008000) -#define MCF_ETPU_ECDTROSR_DTROS16 (0x00010000) -#define MCF_ETPU_ECDTROSR_DTROS17 (0x00020000) -#define MCF_ETPU_ECDTROSR_DTROS18 (0x00040000) -#define MCF_ETPU_ECDTROSR_DTROS19 (0x00080000) -#define MCF_ETPU_ECDTROSR_DTROS20 (0x00100000) -#define MCF_ETPU_ECDTROSR_DTROS21 (0x00200000) -#define MCF_ETPU_ECDTROSR_DTROS22 (0x00400000) -#define MCF_ETPU_ECDTROSR_DTROS23 (0x00800000) -#define MCF_ETPU_ECDTROSR_DTROS24 (0x01000000) -#define MCF_ETPU_ECDTROSR_DTROS25 (0x02000000) -#define MCF_ETPU_ECDTROSR_DTROS26 (0x04000000) -#define MCF_ETPU_ECDTROSR_DTROS27 (0x08000000) -#define MCF_ETPU_ECDTROSR_DTROS28 (0x10000000) -#define MCF_ETPU_ECDTROSR_DTROS29 (0x20000000) -#define MCF_ETPU_ECDTROSR_DTROS30 (0x40000000) -#define MCF_ETPU_ECDTROSR_DTROS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECIER */ -#define MCF_ETPU_ECIER_CIE0 (0x00000001) -#define MCF_ETPU_ECIER_CIE1 (0x00000002) -#define MCF_ETPU_ECIER_CIE2 (0x00000004) -#define MCF_ETPU_ECIER_CIE3 (0x00000008) -#define MCF_ETPU_ECIER_CIE4 (0x00000010) -#define MCF_ETPU_ECIER_CIE5 (0x00000020) -#define MCF_ETPU_ECIER_CIE6 (0x00000040) -#define MCF_ETPU_ECIER_CIE7 (0x00000080) -#define MCF_ETPU_ECIER_CIE8 (0x00000100) -#define MCF_ETPU_ECIER_CIE9 (0x00000200) -#define MCF_ETPU_ECIER_CIE10 (0x00000400) -#define MCF_ETPU_ECIER_CIE11 (0x00000800) -#define MCF_ETPU_ECIER_CIE12 (0x00001000) -#define MCF_ETPU_ECIER_CIE13 (0x00002000) -#define MCF_ETPU_ECIER_CIE14 (0x00004000) -#define MCF_ETPU_ECIER_CIE15 (0x00008000) -#define MCF_ETPU_ECIER_CIE16 (0x00010000) -#define MCF_ETPU_ECIER_CIE17 (0x00020000) -#define MCF_ETPU_ECIER_CIE18 (0x00040000) -#define MCF_ETPU_ECIER_CIE19 (0x00080000) -#define MCF_ETPU_ECIER_CIE20 (0x00100000) -#define MCF_ETPU_ECIER_CIE21 (0x00200000) -#define MCF_ETPU_ECIER_CIE22 (0x00400000) -#define MCF_ETPU_ECIER_CIE23 (0x00800000) -#define MCF_ETPU_ECIER_CIE24 (0x01000000) -#define MCF_ETPU_ECIER_CIE25 (0x02000000) -#define MCF_ETPU_ECIER_CIE26 (0x04000000) -#define MCF_ETPU_ECIER_CIE27 (0x08000000) -#define MCF_ETPU_ECIER_CIE28 (0x10000000) -#define MCF_ETPU_ECIER_CIE29 (0x20000000) -#define MCF_ETPU_ECIER_CIE30 (0x40000000) -#define MCF_ETPU_ECIER_CIE31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECDTRER */ -#define MCF_ETPU_ECDTRER_DTRE0 (0x00000001) -#define MCF_ETPU_ECDTRER_DTRE1 (0x00000002) -#define MCF_ETPU_ECDTRER_DTRE2 (0x00000004) -#define MCF_ETPU_ECDTRER_DTRE3 (0x00000008) -#define MCF_ETPU_ECDTRER_DTRE4 (0x00000010) -#define MCF_ETPU_ECDTRER_DTRE5 (0x00000020) -#define MCF_ETPU_ECDTRER_DTRE6 (0x00000040) -#define MCF_ETPU_ECDTRER_DTRE7 (0x00000080) -#define MCF_ETPU_ECDTRER_DTRE8 (0x00000100) -#define MCF_ETPU_ECDTRER_DTRE9 (0x00000200) -#define MCF_ETPU_ECDTRER_DTRE10 (0x00000400) -#define MCF_ETPU_ECDTRER_DTRE11 (0x00000800) -#define MCF_ETPU_ECDTRER_DTRE12 (0x00001000) -#define MCF_ETPU_ECDTRER_DTRE13 (0x00002000) -#define MCF_ETPU_ECDTRER_DTRE14 (0x00004000) -#define MCF_ETPU_ECDTRER_DTRE15 (0x00008000) -#define MCF_ETPU_ECDTRER_DTRE16 (0x00010000) -#define MCF_ETPU_ECDTRER_DTRE17 (0x00020000) -#define MCF_ETPU_ECDTRER_DTRE18 (0x00040000) -#define MCF_ETPU_ECDTRER_DTRE19 (0x00080000) -#define MCF_ETPU_ECDTRER_DTRE20 (0x00100000) -#define MCF_ETPU_ECDTRER_DTRE21 (0x00200000) -#define MCF_ETPU_ECDTRER_DTRE22 (0x00400000) -#define MCF_ETPU_ECDTRER_DTRE23 (0x00800000) -#define MCF_ETPU_ECDTRER_DTRE24 (0x01000000) -#define MCF_ETPU_ECDTRER_DTRE25 (0x02000000) -#define MCF_ETPU_ECDTRER_DTRE26 (0x04000000) -#define MCF_ETPU_ECDTRER_DTRE27 (0x08000000) -#define MCF_ETPU_ECDTRER_DTRE28 (0x10000000) -#define MCF_ETPU_ECDTRER_DTRE29 (0x20000000) -#define MCF_ETPU_ECDTRER_DTRE30 (0x40000000) -#define MCF_ETPU_ECDTRER_DTRE31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECPSSR */ -#define MCF_ETPU_ECPSSR_SR0 (0x00000001) -#define MCF_ETPU_ECPSSR_SR1 (0x00000002) -#define MCF_ETPU_ECPSSR_SR2 (0x00000004) -#define MCF_ETPU_ECPSSR_SR3 (0x00000008) -#define MCF_ETPU_ECPSSR_SR4 (0x00000010) -#define MCF_ETPU_ECPSSR_SR5 (0x00000020) -#define MCF_ETPU_ECPSSR_SR6 (0x00000040) -#define MCF_ETPU_ECPSSR_SR7 (0x00000080) -#define MCF_ETPU_ECPSSR_SR8 (0x00000100) -#define MCF_ETPU_ECPSSR_SR9 (0x00000200) -#define MCF_ETPU_ECPSSR_SR10 (0x00000400) -#define MCF_ETPU_ECPSSR_SR11 (0x00000800) -#define MCF_ETPU_ECPSSR_SR12 (0x00001000) -#define MCF_ETPU_ECPSSR_SR13 (0x00002000) -#define MCF_ETPU_ECPSSR_SR14 (0x00004000) -#define MCF_ETPU_ECPSSR_SR15 (0x00008000) -#define MCF_ETPU_ECPSSR_SR16 (0x00010000) -#define MCF_ETPU_ECPSSR_SR17 (0x00020000) -#define MCF_ETPU_ECPSSR_SR18 (0x00040000) -#define MCF_ETPU_ECPSSR_SR19 (0x00080000) -#define MCF_ETPU_ECPSSR_SR20 (0x00100000) -#define MCF_ETPU_ECPSSR_SR21 (0x00200000) -#define MCF_ETPU_ECPSSR_SR22 (0x00400000) -#define MCF_ETPU_ECPSSR_SR23 (0x00800000) -#define MCF_ETPU_ECPSSR_SR24 (0x01000000) -#define MCF_ETPU_ECPSSR_SR25 (0x02000000) -#define MCF_ETPU_ECPSSR_SR26 (0x04000000) -#define MCF_ETPU_ECPSSR_SR27 (0x08000000) -#define MCF_ETPU_ECPSSR_SR28 (0x10000000) -#define MCF_ETPU_ECPSSR_SR29 (0x20000000) -#define MCF_ETPU_ECPSSR_SR30 (0x40000000) -#define MCF_ETPU_ECPSSR_SR31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECSSR */ -#define MCF_ETPU_ECSSR_SS0 (0x00000001) -#define MCF_ETPU_ECSSR_SS1 (0x00000002) -#define MCF_ETPU_ECSSR_SS2 (0x00000004) -#define MCF_ETPU_ECSSR_SS3 (0x00000008) -#define MCF_ETPU_ECSSR_SS4 (0x00000010) -#define MCF_ETPU_ECSSR_SS5 (0x00000020) -#define MCF_ETPU_ECSSR_SS6 (0x00000040) -#define MCF_ETPU_ECSSR_SS7 (0x00000080) -#define MCF_ETPU_ECSSR_SS8 (0x00000100) -#define MCF_ETPU_ECSSR_SS9 (0x00000200) -#define MCF_ETPU_ECSSR_SS10 (0x00000400) -#define MCF_ETPU_ECSSR_SS11 (0x00000800) -#define MCF_ETPU_ECSSR_SS12 (0x00001000) -#define MCF_ETPU_ECSSR_SS13 (0x00002000) -#define MCF_ETPU_ECSSR_SS14 (0x00004000) -#define MCF_ETPU_ECSSR_SS15 (0x00008000) -#define MCF_ETPU_ECSSR_SS16 (0x00010000) -#define MCF_ETPU_ECSSR_SS17 (0x00020000) -#define MCF_ETPU_ECSSR_SS18 (0x00040000) -#define MCF_ETPU_ECSSR_SS19 (0x00080000) -#define MCF_ETPU_ECSSR_SS20 (0x00100000) -#define MCF_ETPU_ECSSR_SS21 (0x00200000) -#define MCF_ETPU_ECSSR_SS22 (0x00400000) -#define MCF_ETPU_ECSSR_SS23 (0x00800000) -#define MCF_ETPU_ECSSR_SS24 (0x01000000) -#define MCF_ETPU_ECSSR_SS25 (0x02000000) -#define MCF_ETPU_ECSSR_SS26 (0x04000000) -#define MCF_ETPU_ECSSR_SS27 (0x08000000) -#define MCF_ETPU_ECSSR_SS28 (0x10000000) -#define MCF_ETPU_ECSSR_SS29 (0x20000000) -#define MCF_ETPU_ECSSR_SS30 (0x40000000) -#define MCF_ETPU_ECSSR_SS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECnSCR */ -#define MCF_ETPU_ECnSCR_FM(x) (((x)&0x00000003)<<0) -#define MCF_ETPU_ECnSCR_OBE (0x00002000) -#define MCF_ETPU_ECnSCR_OPS (0x00004000) -#define MCF_ETPU_ECnSCR_IPS (0x00008000) -#define MCF_ETPU_ECnSCR_DTROS (0x00400000) -#define MCF_ETPU_ECnSCR_DTRS (0x00800000) -#define MCF_ETPU_ECnSCR_CIOS (0x40000000) -#define MCF_ETPU_ECnSCR_CIS (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECnCR */ -#define MCF_ETPU_ECnCR_CPBA(x) (((x)&0x000007FF)<<0) -#define MCF_ETPU_ECnCR_OPOL (0x00004000) -#define MCF_ETPU_ECnCR_ODIS (0x00008000) -#define MCF_ETPU_ECnCR_CFS(x) (((x)&0x0000001F)<<16) -#define MCF_ETPU_ECnCR_ETCS (0x01000000) -#define MCF_ETPU_ECnCR_CPR(x) (((x)&0x00000003)<<28) -#define MCF_ETPU_ECnCR_DTRE (0x40000000) -#define MCF_ETPU_ECnCR_CIE (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECnHSSR */ -#define MCF_ETPU_ECnHSSR_HSR(x) (((x)&0x00000007)<<0) - -/********************************************************************/ - -#endif /* __MCF523X_ETPU_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_etpu_struc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_etpu_struc.h deleted file mode 100644 index f35278a0d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_etpu_struc.h +++ /dev/null @@ -1,919 +0,0 @@ -/**************************************************************************/ -/* FILE NAME: mcf523x_eTPU_struc.h */ -/* COPYRIGHT (c) Freescale Semiconductor 2004 */ -/* VERSION: 0.02 All Rights Reserved */ -/* */ -/* DESCRIPTION: */ -/* This file contains eTPU register and bit field definitions for MCF523x.*/ -/* Part of mpc5554.h auto-generated code by J.Loeliger. */ -/*========================================================================*/ -/* UPDATE HISTORY */ -/* REV AUTHOR DATE DESCRIPTION OF CHANGE */ -/* --- ----------- --------- --------------------- */ -/* 0.01 J.Loeliger 30/Apr/04 Initial version of file. */ -/* M.Princ */ -/* 0.02 J.Loeliger 20/Jul/04 Update eTPU structure to match mpc5554.*/ -/**************************************************************************/ - - -#ifndef _MCF523x_eTPU_struc_H_ -#define _MCF523x_eTPU_struc_H_ - -#include "typedefs.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __MWERKS__ -#pragma push -#pragma ANSI_strict off -#endif - -/***************************Configuration Registers**************************/ - - struct ETPU_tag { - union { /* MODULE CONFIGURATION REGISTER */ - vuint32_t R; - struct { - vuint32_t GEC:1; /* Global Exception Clear */ - vuint32_t:3; - vuint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */ - - vuint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */ - - vuint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */ - - vuint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */ - - vuint32_t:3; - vuint32_t SCMSIZE:5; /* Shared Code Memory size */ - vuint32_t:5; - vuint32_t SCMMISF:1; /* SCM MISC Flag */ - vuint32_t SCMMISEN:1; /* SCM MISC Enable */ - vuint32_t:2; - vuint32_t VIS:1; /* SCM Visability */ - vuint32_t:5; - vuint32_t GTBE:1; /* Global Time Base Enable */ - } B; - } MCR; - - union { /* COHERENT DUAL-PARAMETER CONTROL */ - vuint32_t R; - struct { - vuint32_t STS:1; /* Start Status bit */ - vuint32_t CTBASE:5; /* Channel Transfer Base */ - vuint32_t PBASE:10; /* Parameter Buffer Base Address */ - vuint32_t PWIDTH:1; /* Parameter Width */ - vuint32_t PARAM0:7; /* Channel Parameter 0 */ - vuint32_t WR:1; - vuint32_t PARAM1:7; /* Channel Parameter 1 */ - } B; - } CDCR; - - uint32_t etpu_reserved1; - - union { /* MISC Compare Register */ - uint32_t R; - } MISCCMPR; - - uint32_t etpu_reserved2; - - union { /* ETPU_A Configuration Register */ - vuint32_t R; - struct { - vuint32_t FEND:1; /* Force END */ - vuint32_t MDIS:1; /* Low power Stop */ - vuint32_t:1; - vuint32_t STF:1; /* Stop Flag */ - vuint32_t:4; - vuint32_t HLTF:1; /* Halt Mode Flag */ - vuint32_t:4; - vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */ - vuint32_t CDFC:2; - vuint32_t:9; - vuint32_t ETB:5; /* Entry Table Base */ - } B; - } ECR_A; - - union { /* ETPU_B Configuration Register */ - vuint32_t R; - struct { - vuint32_t FEND:1; /* Force END */ - vuint32_t MDIS:1; /* Low power Stop */ - vuint32_t:1; - vuint32_t STF:1; /* Stop Flag */ - vuint32_t:4; - vuint32_t HLTF:1; /* Halt Mode Flag */ - vuint32_t:4; - vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */ - vuint32_t CDFC:2; - vuint32_t:9; - vuint32_t ETB:5; /* Entry Table Base */ - } B; - } ECR_B; - - uint32_t etpu_reserved4; - - union { /* ETPU_A Timebase Configuration Register */ - uint32_t R; - struct { - uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ - uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ - uint32_t:1; - uint32_t AM:1; /* Angle Mode */ - uint32_t:3; - uint32_t TCR2P:6; /* TCR2 Prescaler Control */ - uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ - uint32_t:6; - uint32_t TCR1P:8; /* TCR1 Prescaler Control */ - } B; - } TBCR_A; - - union { /* ETPU_A TCR1 Visibility Register */ - vuint32_t R; - } TB1R_A; - - union { /* ETPU_A TCR2 Visibility Register */ - vuint32_t R; - } TB2R_A; - - union { /* ETPU_A STAC Configuration Register */ - vuint32_t R; - struct { - vuint32_t REN1:1; /* Resource Enable TCR1 */ - vuint32_t RSC1:1; /* Resource Control TCR1 */ - vuint32_t VALID1:1; /* TCR1 Server Valid */ - vuint32_t:9; - vuint32_t SRV1:4; /* Resource Server Slot */ - vuint32_t REN2:1; /* Resource Enable TCR2 */ - vuint32_t RSC2:1; /* Resource Control TCR2 */ - vuint32_t VALID2:1; /* TCR2 Server Valid */ - vuint32_t:9; - vuint32_t SRV2:4; /* Resource Server Slot */ - } B; - } REDCR_A; - - uint32_t etpu_reserved5[4]; - - union { /* ETPU_B Timebase Configuration Register */ - uint32_t R; - struct { - uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ - uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ - uint32_t:1; - uint32_t AM:1; /* Angle Mode */ - uint32_t:3; - uint32_t TCR2P:6; /* TCR2 Prescaler Control */ - uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ - uint32_t:6; - uint32_t TCR1P:8; /* TCR1 Prescaler Control */ - } B; - } TBCR_B; - - union { /* ETPU_B TCR1 Visibility Register */ - vuint32_t R; - } TB1R_B; - - union { /* ETPU_B TCR2 Visibility Register */ - vuint32_t R; - } TB2R_B; - - union { /* ETPU_B STAC Configuration Register */ - vuint32_t R; - struct { - vuint32_t REN1:1; /* Resource Enable TCR1 */ - vuint32_t RSC1:1; /* Resource Control TCR1 */ - vuint32_t VALID1:1; /* TCR1 Server Valid */ - vuint32_t:9; - vuint32_t SRV1:4; /* Resource Server Slot */ - vuint32_t REN2:1; /* Resource Enable TCR2 */ - vuint32_t RSC2:1; /* Resource Control TCR2 */ - vuint32_t VALID2:1; /* TCR2 Server Valid */ - vuint32_t:9; - vuint32_t SRV2:4; /* Resource Server Slot */ - } B; - } REDCR_B; - - uint32_t etpu_reserved7[108]; - -/*****************************Status and Control Registers**************************/ - - union { /* ETPU_A Channel Interrut Status */ - vuint32_t R; - struct { - vuint32_t CIS31:1; /* Channel 31 Interrut Status */ - vuint32_t CIS30:1; /* Channel 30 Interrut Status */ - vuint32_t CIS29:1; /* Channel 29 Interrut Status */ - vuint32_t CIS28:1; /* Channel 28 Interrut Status */ - vuint32_t CIS27:1; /* Channel 27 Interrut Status */ - vuint32_t CIS26:1; /* Channel 26 Interrut Status */ - vuint32_t CIS25:1; /* Channel 25 Interrut Status */ - vuint32_t CIS24:1; /* Channel 24 Interrut Status */ - vuint32_t CIS23:1; /* Channel 23 Interrut Status */ - vuint32_t CIS22:1; /* Channel 22 Interrut Status */ - vuint32_t CIS21:1; /* Channel 21 Interrut Status */ - vuint32_t CIS20:1; /* Channel 20 Interrut Status */ - vuint32_t CIS19:1; /* Channel 19 Interrut Status */ - vuint32_t CIS18:1; /* Channel 18 Interrut Status */ - vuint32_t CIS17:1; /* Channel 17 Interrut Status */ - vuint32_t CIS16:1; /* Channel 16 Interrut Status */ - vuint32_t CIS15:1; /* Channel 15 Interrut Status */ - vuint32_t CIS14:1; /* Channel 14 Interrut Status */ - vuint32_t CIS13:1; /* Channel 13 Interrut Status */ - vuint32_t CIS12:1; /* Channel 12 Interrut Status */ - vuint32_t CIS11:1; /* Channel 11 Interrut Status */ - vuint32_t CIS10:1; /* Channel 10 Interrut Status */ - vuint32_t CIS9:1; /* Channel 9 Interrut Status */ - vuint32_t CIS8:1; /* Channel 8 Interrut Status */ - vuint32_t CIS7:1; /* Channel 7 Interrut Status */ - vuint32_t CIS6:1; /* Channel 6 Interrut Status */ - vuint32_t CIS5:1; /* Channel 5 Interrut Status */ - vuint32_t CIS4:1; /* Channel 4 Interrut Status */ - vuint32_t CIS3:1; /* Channel 3 Interrut Status */ - vuint32_t CIS2:1; /* Channel 2 Interrut Status */ - vuint32_t CIS1:1; /* Channel 1 Interrut Status */ - vuint32_t CIS0:1; /* Channel 0 Interrut Status */ - } B; - } CISR_A; - - union { /* ETPU_B Channel Interruput Status */ - vuint32_t R; - struct { - vuint32_t CIS31:1; /* Channel 31 Interrut Status */ - vuint32_t CIS30:1; /* Channel 30 Interrut Status */ - vuint32_t CIS29:1; /* Channel 29 Interrut Status */ - vuint32_t CIS28:1; /* Channel 28 Interrut Status */ - vuint32_t CIS27:1; /* Channel 27 Interrut Status */ - vuint32_t CIS26:1; /* Channel 26 Interrut Status */ - vuint32_t CIS25:1; /* Channel 25 Interrut Status */ - vuint32_t CIS24:1; /* Channel 24 Interrut Status */ - vuint32_t CIS23:1; /* Channel 23 Interrut Status */ - vuint32_t CIS22:1; /* Channel 22 Interrut Status */ - vuint32_t CIS21:1; /* Channel 21 Interrut Status */ - vuint32_t CIS20:1; /* Channel 20 Interrut Status */ - vuint32_t CIS19:1; /* Channel 19 Interrut Status */ - vuint32_t CIS18:1; /* Channel 18 Interrut Status */ - vuint32_t CIS17:1; /* Channel 17 Interrut Status */ - vuint32_t CIS16:1; /* Channel 16 Interrut Status */ - vuint32_t CIS15:1; /* Channel 15 Interrut Status */ - vuint32_t CIS14:1; /* Channel 14 Interrut Status */ - vuint32_t CIS13:1; /* Channel 13 Interrut Status */ - vuint32_t CIS12:1; /* Channel 12 Interrut Status */ - vuint32_t CIS11:1; /* Channel 11 Interrut Status */ - vuint32_t CIS10:1; /* Channel 10 Interrut Status */ - vuint32_t CIS9:1; /* Channel 9 Interrut Status */ - vuint32_t CIS8:1; /* Channel 8 Interrut Status */ - vuint32_t CIS7:1; /* Channel 7 Interrut Status */ - vuint32_t CIS6:1; /* Channel 6 Interrut Status */ - vuint32_t CIS5:1; /* Channel 5 Interrut Status */ - vuint32_t CIS4:1; /* Channel 4 Interrut Status */ - vuint32_t CIS3:1; /* Channel 3 Interrut Status */ - vuint32_t CIS2:1; /* Channel 2 Interrut Status */ - vuint32_t CIS1:1; /* Channel 1 Interrupt Status */ - vuint32_t CIS0:1; /* Channel 0 Interrupt Status */ - } B; - } CISR_B; - - uint32_t etpu_reserved9[2]; - - union { /* ETPU_A Data Transfer Request Status */ - vuint32_t R; - struct { - vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ - vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ - vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ - vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ - vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ - vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ - vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ - vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ - vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ - vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ - vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ - vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ - vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ - vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ - vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ - vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ - vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ - vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ - vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ - vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ - vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ - vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ - vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ - vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ - vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ - vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ - vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ - vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ - vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ - vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ - vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ - vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ - } B; - } CDTRSR_A; - - union { /* ETPU_B Data Transfer Request Status */ - vuint32_t R; - struct { - vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ - vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ - vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ - vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ - vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ - vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ - vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ - vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ - vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ - vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ - vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ - vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ - vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ - vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ - vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ - vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ - vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ - vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ - vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ - vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ - vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ - vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ - vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ - vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ - vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ - vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ - vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ - vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ - vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ - vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ - vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ - vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ - } B; - } CDTRSR_B; - - uint32_t etpu_reserved11[2]; - - union { /* ETPU_A Interruput Overflow Status */ - vuint32_t R; - struct { - vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ - vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ - vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ - vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ - vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ - vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ - vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ - vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ - vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ - vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ - vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ - vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ - vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ - vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ - vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ - vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ - vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ - vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ - vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ - vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ - vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ - vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ - vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ - vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ - vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ - vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ - vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ - vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ - vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ - vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ - vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ - vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ - } B; - } CIOSR_A; - - union { /* ETPU_B Interruput Overflow Status */ - vuint32_t R; - struct { - vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ - vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ - vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ - vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ - vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ - vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ - vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ - vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ - vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ - vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ - vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ - vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ - vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ - vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ - vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ - vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ - vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ - vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ - vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ - vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ - vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ - vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ - vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ - vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ - vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ - vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ - vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ - vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ - vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ - vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ - vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ - vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ - } B; - } CIOSR_B; - - uint32_t etpu_reserved13[2]; - - union { /* ETPU_A Data Transfer Overflow Status */ - vuint32_t R; - struct { - vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ - vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ - vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ - vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ - vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ - vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ - vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ - vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ - vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ - vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ - vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ - vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ - vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ - vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ - vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ - vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ - vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ - vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ - vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ - vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ - vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ - vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ - vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ - vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ - vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ - vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ - vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ - vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ - vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ - vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ - vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ - vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ - } B; - } CDTROSR_A; - - union { /* ETPU_B Data Transfer Overflow Status */ - vuint32_t R; - struct { - vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ - vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ - vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ - vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ - vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ - vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ - vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ - vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ - vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ - vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ - vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ - vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ - vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ - vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ - vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ - vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ - vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ - vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ - vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ - vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ - vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ - vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ - vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ - vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ - vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ - vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ - vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ - vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ - vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ - vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ - vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ - vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ - } B; - } CDTROSR_B; - - uint32_t etpu_reserved15[2]; - - union { /* ETPU_A Channel Interruput Enable */ - vuint32_t R; - struct { - vuint32_t CIE31:1; /* Channel 31 Interruput Enable */ - vuint32_t CIE30:1; /* Channel 30 Interruput Enable */ - vuint32_t CIE29:1; /* Channel 29 Interruput Enable */ - vuint32_t CIE28:1; /* Channel 28 Interruput Enable */ - vuint32_t CIE27:1; /* Channel 27 Interruput Enable */ - vuint32_t CIE26:1; /* Channel 26 Interruput Enable */ - vuint32_t CIE25:1; /* Channel 25 Interruput Enable */ - vuint32_t CIE24:1; /* Channel 24 Interruput Enable */ - vuint32_t CIE23:1; /* Channel 23 Interruput Enable */ - vuint32_t CIE22:1; /* Channel 22 Interruput Enable */ - vuint32_t CIE21:1; /* Channel 21 Interruput Enable */ - vuint32_t CIE20:1; /* Channel 20 Interruput Enable */ - vuint32_t CIE19:1; /* Channel 19 Interruput Enable */ - vuint32_t CIE18:1; /* Channel 18 Interruput Enable */ - vuint32_t CIE17:1; /* Channel 17 Interruput Enable */ - vuint32_t CIE16:1; /* Channel 16 Interruput Enable */ - vuint32_t CIE15:1; /* Channel 15 Interruput Enable */ - vuint32_t CIE14:1; /* Channel 14 Interruput Enable */ - vuint32_t CIE13:1; /* Channel 13 Interruput Enable */ - vuint32_t CIE12:1; /* Channel 12 Interruput Enable */ - vuint32_t CIE11:1; /* Channel 11 Interruput Enable */ - vuint32_t CIE10:1; /* Channel 10 Interruput Enable */ - vuint32_t CIE9:1; /* Channel 9 Interruput Enable */ - vuint32_t CIE8:1; /* Channel 8 Interruput Enable */ - vuint32_t CIE7:1; /* Channel 7 Interruput Enable */ - vuint32_t CIE6:1; /* Channel 6 Interruput Enable */ - vuint32_t CIE5:1; /* Channel 5 Interruput Enable */ - vuint32_t CIE4:1; /* Channel 4 Interruput Enable */ - vuint32_t CIE3:1; /* Channel 3 Interruput Enable */ - vuint32_t CIE2:1; /* Channel 2 Interruput Enable */ - vuint32_t CIE1:1; /* Channel 1 Interruput Enable */ - vuint32_t CIE0:1; /* Channel 0 Interruput Enable */ - } B; - } CIER_A; - - union { /* ETPU_B Channel Interruput Enable */ - vuint32_t R; - struct { - vuint32_t CIE31:1; /* Channel 31 Interruput Enable */ - vuint32_t CIE30:1; /* Channel 30 Interruput Enable */ - vuint32_t CIE29:1; /* Channel 29 Interruput Enable */ - vuint32_t CIE28:1; /* Channel 28 Interruput Enable */ - vuint32_t CIE27:1; /* Channel 27 Interruput Enable */ - vuint32_t CIE26:1; /* Channel 26 Interruput Enable */ - vuint32_t CIE25:1; /* Channel 25 Interruput Enable */ - vuint32_t CIE24:1; /* Channel 24 Interruput Enable */ - vuint32_t CIE23:1; /* Channel 23 Interruput Enable */ - vuint32_t CIE22:1; /* Channel 22 Interruput Enable */ - vuint32_t CIE21:1; /* Channel 21 Interruput Enable */ - vuint32_t CIE20:1; /* Channel 20 Interruput Enable */ - vuint32_t CIE19:1; /* Channel 19 Interruput Enable */ - vuint32_t CIE18:1; /* Channel 18 Interruput Enable */ - vuint32_t CIE17:1; /* Channel 17 Interruput Enable */ - vuint32_t CIE16:1; /* Channel 16 Interruput Enable */ - vuint32_t CIE15:1; /* Channel 15 Interruput Enable */ - vuint32_t CIE14:1; /* Channel 14 Interruput Enable */ - vuint32_t CIE13:1; /* Channel 13 Interruput Enable */ - vuint32_t CIE12:1; /* Channel 12 Interruput Enable */ - vuint32_t CIE11:1; /* Channel 11 Interruput Enable */ - vuint32_t CIE10:1; /* Channel 10 Interruput Enable */ - vuint32_t CIE9:1; /* Channel 9 Interruput Enable */ - vuint32_t CIE8:1; /* Channel 8 Interruput Enable */ - vuint32_t CIE7:1; /* Channel 7 Interruput Enable */ - vuint32_t CIE6:1; /* Channel 6 Interruput Enable */ - vuint32_t CIE5:1; /* Channel 5 Interruput Enable */ - vuint32_t CIE4:1; /* Channel 4 Interruput Enable */ - vuint32_t CIE3:1; /* Channel 3 Interruput Enable */ - vuint32_t CIE2:1; /* Channel 2 Interruput Enable */ - vuint32_t CIE1:1; /* Channel 1 Interruput Enable */ - vuint32_t CIE0:1; /* Channel 0 Interruput Enable */ - } B; - } CIER_B; - - uint32_t etpu_reserved17[2]; - - union { /* ETPU_A Channel Data Transfer Request Enable */ - vuint32_t R; - struct { - vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ - vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ - vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ - vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ - vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ - vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ - vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ - vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ - vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ - vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ - vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ - vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ - vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ - vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ - vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ - vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ - vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ - vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ - vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ - vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ - vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ - vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ - vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ - vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ - vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ - vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ - vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ - vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ - vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ - vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ - vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ - vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ - } B; - } CDTRER_A; - - union { /* ETPU_B Channel Data Transfer Request Enable */ - vuint32_t R; - struct { - vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ - vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ - vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ - vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ - vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ - vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ - vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ - vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ - vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ - vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ - vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ - vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ - vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ - vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ - vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ - vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ - vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ - vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ - vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ - vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ - vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ - vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ - vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ - vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ - vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ - vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ - vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ - vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ - vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ - vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ - vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ - vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ - } B; - } CDTRER_B; - - uint32_t etpu_reserved20[10]; - union { /* ETPU_A Channel Pending Service Status */ - vuint32_t R; - struct { - vuint32_t SR31:1; /* Channel 31 Pending Service Status */ - vuint32_t SR30:1; /* Channel 30 Pending Service Status */ - vuint32_t SR29:1; /* Channel 29 Pending Service Status */ - vuint32_t SR28:1; /* Channel 28 Pending Service Status */ - vuint32_t SR27:1; /* Channel 27 Pending Service Status */ - vuint32_t SR26:1; /* Channel 26 Pending Service Status */ - vuint32_t SR25:1; /* Channel 25 Pending Service Status */ - vuint32_t SR24:1; /* Channel 24 Pending Service Status */ - vuint32_t SR23:1; /* Channel 23 Pending Service Status */ - vuint32_t SR22:1; /* Channel 22 Pending Service Status */ - vuint32_t SR21:1; /* Channel 21 Pending Service Status */ - vuint32_t SR20:1; /* Channel 20 Pending Service Status */ - vuint32_t SR19:1; /* Channel 19 Pending Service Status */ - vuint32_t SR18:1; /* Channel 18 Pending Service Status */ - vuint32_t SR17:1; /* Channel 17 Pending Service Status */ - vuint32_t SR16:1; /* Channel 16 Pending Service Status */ - vuint32_t SR15:1; /* Channel 15 Pending Service Status */ - vuint32_t SR14:1; /* Channel 14 Pending Service Status */ - vuint32_t SR13:1; /* Channel 13 Pending Service Status */ - vuint32_t SR12:1; /* Channel 12 Pending Service Status */ - vuint32_t SR11:1; /* Channel 11 Pending Service Status */ - vuint32_t SR10:1; /* Channel 10 Pending Service Status */ - vuint32_t SR9:1; /* Channel 9 Pending Service Status */ - vuint32_t SR8:1; /* Channel 8 Pending Service Status */ - vuint32_t SR7:1; /* Channel 7 Pending Service Status */ - vuint32_t SR6:1; /* Channel 6 Pending Service Status */ - vuint32_t SR5:1; /* Channel 5 Pending Service Status */ - vuint32_t SR4:1; /* Channel 4 Pending Service Status */ - vuint32_t SR3:1; /* Channel 3 Pending Service Status */ - vuint32_t SR2:1; /* Channel 2 Pending Service Status */ - vuint32_t SR1:1; /* Channel 1 Pending Service Status */ - vuint32_t SR0:1; /* Channel 0 Pending Service Status */ - } B; - } CPSSR_A; - - union { /* ETPU_B Channel Pending Service Status */ - vuint32_t R; - struct { - vuint32_t SR31:1; /* Channel 31 Pending Service Status */ - vuint32_t SR30:1; /* Channel 30 Pending Service Status */ - vuint32_t SR29:1; /* Channel 29 Pending Service Status */ - vuint32_t SR28:1; /* Channel 28 Pending Service Status */ - vuint32_t SR27:1; /* Channel 27 Pending Service Status */ - vuint32_t SR26:1; /* Channel 26 Pending Service Status */ - vuint32_t SR25:1; /* Channel 25 Pending Service Status */ - vuint32_t SR24:1; /* Channel 24 Pending Service Status */ - vuint32_t SR23:1; /* Channel 23 Pending Service Status */ - vuint32_t SR22:1; /* Channel 22 Pending Service Status */ - vuint32_t SR21:1; /* Channel 21 Pending Service Status */ - vuint32_t SR20:1; /* Channel 20 Pending Service Status */ - vuint32_t SR19:1; /* Channel 19 Pending Service Status */ - vuint32_t SR18:1; /* Channel 18 Pending Service Status */ - vuint32_t SR17:1; /* Channel 17 Pending Service Status */ - vuint32_t SR16:1; /* Channel 16 Pending Service Status */ - vuint32_t SR15:1; /* Channel 15 Pending Service Status */ - vuint32_t SR14:1; /* Channel 14 Pending Service Status */ - vuint32_t SR13:1; /* Channel 13 Pending Service Status */ - vuint32_t SR12:1; /* Channel 12 Pending Service Status */ - vuint32_t SR11:1; /* Channel 11 Pending Service Status */ - vuint32_t SR10:1; /* Channel 10 Pending Service Status */ - vuint32_t SR9:1; /* Channel 9 Pending Service Status */ - vuint32_t SR8:1; /* Channel 8 Pending Service Status */ - vuint32_t SR7:1; /* Channel 7 Pending Service Status */ - vuint32_t SR6:1; /* Channel 6 Pending Service Status */ - vuint32_t SR5:1; /* Channel 5 Pending Service Status */ - vuint32_t SR4:1; /* Channel 4 Pending Service Status */ - vuint32_t SR3:1; /* Channel 3 Pending Service Status */ - vuint32_t SR2:1; /* Channel 2 Pending Service Status */ - vuint32_t SR1:1; /* Channel 1 Pending Service Status */ - vuint32_t SR0:1; /* Channel 0 Pending Service Status */ - } B; - } CPSSR_B; - - uint32_t etpu_reserved20a[2]; - - union { /* ETPU_A Channel Service Status */ - vuint32_t R; - struct { - vuint32_t SS31:1; /* Channel 31 Service Status */ - vuint32_t SS30:1; /* Channel 30 Service Status */ - vuint32_t SS29:1; /* Channel 29 Service Status */ - vuint32_t SS28:1; /* Channel 28 Service Status */ - vuint32_t SS27:1; /* Channel 27 Service Status */ - vuint32_t SS26:1; /* Channel 26 Service Status */ - vuint32_t SS25:1; /* Channel 25 Service Status */ - vuint32_t SS24:1; /* Channel 24 Service Status */ - vuint32_t SS23:1; /* Channel 23 Service Status */ - vuint32_t SS22:1; /* Channel 22 Service Status */ - vuint32_t SS21:1; /* Channel 21 Service Status */ - vuint32_t SS20:1; /* Channel 20 Service Status */ - vuint32_t SS19:1; /* Channel 19 Service Status */ - vuint32_t SS18:1; /* Channel 18 Service Status */ - vuint32_t SS17:1; /* Channel 17 Service Status */ - vuint32_t SS16:1; /* Channel 16 Service Status */ - vuint32_t SS15:1; /* Channel 15 Service Status */ - vuint32_t SS14:1; /* Channel 14 Service Status */ - vuint32_t SS13:1; /* Channel 13 Service Status */ - vuint32_t SS12:1; /* Channel 12 Service Status */ - vuint32_t SS11:1; /* Channel 11 Service Status */ - vuint32_t SS10:1; /* Channel 10 Service Status */ - vuint32_t SS9:1; /* Channel 9 Service Status */ - vuint32_t SS8:1; /* Channel 8 Service Status */ - vuint32_t SS7:1; /* Channel 7 Service Status */ - vuint32_t SS6:1; /* Channel 6 Service Status */ - vuint32_t SS5:1; /* Channel 5 Service Status */ - vuint32_t SS4:1; /* Channel 4 Service Status */ - vuint32_t SS3:1; /* Channel 3 Service Status */ - vuint32_t SS2:1; /* Channel 2 Service Status */ - vuint32_t SS1:1; /* Channel 1 Service Status */ - vuint32_t SS0:1; /* Channel 0 Service Status */ - } B; - } CSSR_A; - - union { /* ETPU_B Channel Service Status */ - vuint32_t R; - struct { - vuint32_t SS31:1; /* Channel 31 Service Status */ - vuint32_t SS30:1; /* Channel 30 Service Status */ - vuint32_t SS29:1; /* Channel 29 Service Status */ - vuint32_t SS28:1; /* Channel 28 Service Status */ - vuint32_t SS27:1; /* Channel 27 Service Status */ - vuint32_t SS26:1; /* Channel 26 Service Status */ - vuint32_t SS25:1; /* Channel 25 Service Status */ - vuint32_t SS24:1; /* Channel 24 Service Status */ - vuint32_t SS23:1; /* Channel 23 Service Status */ - vuint32_t SS22:1; /* Channel 22 Service Status */ - vuint32_t SS21:1; /* Channel 21 Service Status */ - vuint32_t SS20:1; /* Channel 20 Service Status */ - vuint32_t SS19:1; /* Channel 19 Service Status */ - vuint32_t SS18:1; /* Channel 18 Service Status */ - vuint32_t SS17:1; /* Channel 17 Service Status */ - vuint32_t SS16:1; /* Channel 16 Service Status */ - vuint32_t SS15:1; /* Channel 15 Service Status */ - vuint32_t SS14:1; /* Channel 14 Service Status */ - vuint32_t SS13:1; /* Channel 13 Service Status */ - vuint32_t SS12:1; /* Channel 12 Service Status */ - vuint32_t SS11:1; /* Channel 11 Service Status */ - vuint32_t SS10:1; /* Channel 10 Service Status */ - vuint32_t SS9:1; /* Channel 9 Service Status */ - vuint32_t SS8:1; /* Channel 8 Service Status */ - vuint32_t SS7:1; /* Channel 7 Service Status */ - vuint32_t SS6:1; /* Channel 6 Service Status */ - vuint32_t SS5:1; /* Channel 5 Service Status */ - vuint32_t SS4:1; /* Channel 4 Service Status */ - vuint32_t SS3:1; /* Channel 3 Service Status */ - vuint32_t SS2:1; /* Channel 2 Service Status */ - vuint32_t SS1:1; /* Channel 1 Service Status */ - vuint32_t SS0:1; /* Channel 0 Service Status */ - } B; - } CSSR_B; - - uint32_t etpu_reserved23[90]; - -/*****************************Channels********************************/ - - struct { - union { - vuint32_t R; /* Channel Configuration Register */ - struct { - vuint32_t CIE:1; /* Channel Interruput Enable */ - vuint32_t DTRE:1; /* Data Transfer Request Enable */ - vuint32_t CPR:2; /* Channel Priority */ - vuint32_t:3; - vuint32_t ETCS:1; /* Entry Table Condition Select */ - vuint32_t:3; - vuint32_t CFS:5; /* Channel Function Select */ - vuint32_t ODIS:1; /* Output disable */ - vuint32_t OPOL:1; /* output polarity */ - vuint32_t:3; - vuint32_t CPBA:11; /* Channel Parameter Base Address */ - } B; - } CR; - union { - vuint32_t R; /* Channel Status Control Register */ - struct { - vuint32_t CIS:1; /* Channel Interruput Status */ - vuint32_t CIOS:1; /* Channel Interruput Overflow Status */ - vuint32_t:6; - vuint32_t DTRS:1; /* Data Transfer Status */ - vuint32_t DTROS:1; /* Data Transfer Overflow Status */ - vuint32_t:6; - vuint32_t IPS:1; /* Input Pin State */ - vuint32_t OPS:1; /* Output Pin State */ - vuint32_t OBE:1; /* Output Buffer Enable */ - vuint32_t:11; - vuint32_t FM1:1; /* Function mode */ - vuint32_t FM0:1; /* Function mode */ - } B; - } SCR; - union { - vuint32_t R; /* Channel Host Service Request Register */ - struct { - vuint32_t:29; /* Host Service Request */ - vuint32_t HSR:3; - } B; - } HSRR; - uint32_t etpu_reserved23; - } CHAN[127]; - - }; - -// Define instances of modules -#define ETPU (*( struct ETPU_tag *) 0x401D0000) -#define ETPU_DATA_RAM (*( uint32_t *) 0x401D8000) -#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0x401DC000) -#define ETPU_DATA_RAM_END (0x401D9800) -#define CODE_RAM (*( uint32_t *) 0x401E0000) - -#ifdef __MWERKS__ -#pragma pop -#endif - -#ifdef __cplusplus -} -#endif -#endif /* ifdef _MCF523x_eTPU_struc_H */ - - -/********************************************************************* - * - * Copyright: - * Freescale Semiconductor, INC. All Rights Reserved. - * You are hereby granted a copyright license to use, modify, and - * distribute the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Freescale - * Semiconductor, Inc. This software is provided on an "AS IS" - * basis and without warranty. - * - * To the maximum extent permitted by applicable law, Freescale - * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, - * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A - * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH - * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) - * AND ANY ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, - * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER - * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Freescale Semiconductor assumes no responsibility for the - * maintenance and support of this software - ********************************************************************/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_fec.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_fec.h deleted file mode 100644 index 15139b93d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_fec.h +++ /dev/null @@ -1,212 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_FEC_H__ -#define __MCF523X_FEC_H__ - -/********************************************************************* -* -* Fast Ethernet Controller (FEC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_FEC_EIR (*(vuint32*)(void*)(&__IPSBAR[0x001004])) -#define MCF_FEC_EIMR (*(vuint32*)(void*)(&__IPSBAR[0x001008])) -#define MCF_FEC_RDAR (*(vuint32*)(void*)(&__IPSBAR[0x001010])) -#define MCF_FEC_TDAR (*(vuint32*)(void*)(&__IPSBAR[0x001014])) -#define MCF_FEC_ECR (*(vuint32*)(void*)(&__IPSBAR[0x001024])) -#define MCF_FEC_MMFR (*(vuint32*)(void*)(&__IPSBAR[0x001040])) -#define MCF_FEC_MSCR (*(vuint32*)(void*)(&__IPSBAR[0x001044])) -#define MCF_FEC_MIBC (*(vuint32*)(void*)(&__IPSBAR[0x001064])) -#define MCF_FEC_RCR (*(vuint32*)(void*)(&__IPSBAR[0x001084])) -#define MCF_FEC_TCR (*(vuint32*)(void*)(&__IPSBAR[0x0010C4])) -#define MCF_FEC_PALR (*(vuint32*)(void*)(&__IPSBAR[0x0010E4])) -#define MCF_FEC_PAUR (*(vuint32*)(void*)(&__IPSBAR[0x0010E8])) -#define MCF_FEC_OPD (*(vuint32*)(void*)(&__IPSBAR[0x0010EC])) -#define MCF_FEC_IAUR (*(vuint32*)(void*)(&__IPSBAR[0x001118])) -#define MCF_FEC_IALR (*(vuint32*)(void*)(&__IPSBAR[0x00111C])) -#define MCF_FEC_GAUR (*(vuint32*)(void*)(&__IPSBAR[0x001120])) -#define MCF_FEC_GALR (*(vuint32*)(void*)(&__IPSBAR[0x001124])) -#define MCF_FEC_TFWR (*(vuint32*)(void*)(&__IPSBAR[0x001144])) -#define MCF_FEC_FRBR (*(vuint32*)(void*)(&__IPSBAR[0x00114C])) -#define MCF_FEC_FRSR (*(vuint32*)(void*)(&__IPSBAR[0x001150])) -#define MCF_FEC_ERDSR (*(vuint32*)(void*)(&__IPSBAR[0x001180])) -#define MCF_FEC_ETDSR (*(vuint32*)(void*)(&__IPSBAR[0x001184])) -#define MCF_FEC_EMRBR (*(vuint32*)(void*)(&__IPSBAR[0x001188])) -#define MCF_FEC_RMON_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001200])) -#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001204])) -#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001208])) -#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00120C])) -#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001210])) -#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001214])) -#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001218])) -#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00121C])) -#define MCF_FEC_RMON_T_JAB (*(vuint32*)(void*)(&__IPSBAR[0x001220])) -#define MCF_FEC_RMON_T_COL (*(vuint32*)(void*)(&__IPSBAR[0x001224])) -#define MCF_FEC_RMON_T_P64 (*(vuint32*)(void*)(&__IPSBAR[0x001228])) -#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x00122C])) -#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x001230])) -#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x001234])) -#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x001238])) -#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x00123C])) -#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x001240])) -#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x001244])) -#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001248])) -#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x00124C])) -#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(void*)(&__IPSBAR[0x001250])) -#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(void*)(&__IPSBAR[0x001254])) -#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(void*)(&__IPSBAR[0x001258])) -#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(void*)(&__IPSBAR[0x00125C])) -#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(void*)(&__IPSBAR[0x001260])) -#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x001264])) -#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(void*)(&__IPSBAR[0x001268])) -#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(void*)(&__IPSBAR[0x00126C])) -#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x001270])) -#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x001274])) -#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001284])) -#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001288])) -#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00128C])) -#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001290])) -#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001294])) -#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001298])) -#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00129C])) -#define MCF_FEC_RMON_R_JAB (*(vuint32*)(void*)(&__IPSBAR[0x0012A0])) -#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(void*)(&__IPSBAR[0x0012A4])) -#define MCF_FEC_RMON_R_P64 (*(vuint32*)(void*)(&__IPSBAR[0x0012A8])) -#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x0012AC])) -#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x0012B0])) -#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x0012B4])) -#define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x0012B8])) -#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x0012C0])) -#define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x0012BC])) -#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x0012C4])) -#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(void*)(&__IPSBAR[0x0012C8])) -#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012CC])) -#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(void*)(&__IPSBAR[0x0012D0])) -#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x0012D4])) -#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x0012D8])) -#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x0012DC])) -#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012E0])) - -/* Bit definitions and macros for MCF_FEC_EIR */ -#define MCF_FEC_EIR_UN (0x00080000) -#define MCF_FEC_EIR_RL (0x00100000) -#define MCF_FEC_EIR_LC (0x00200000) -#define MCF_FEC_EIR_EBERR (0x00400000) -#define MCF_FEC_EIR_MII (0x00800000) -#define MCF_FEC_EIR_RXB (0x01000000) -#define MCF_FEC_EIR_RXF (0x02000000) -#define MCF_FEC_EIR_TXB (0x04000000) -#define MCF_FEC_EIR_TXF (0x08000000) -#define MCF_FEC_EIR_GRA (0x10000000) -#define MCF_FEC_EIR_BABT (0x20000000) -#define MCF_FEC_EIR_BABR (0x40000000) -#define MCF_FEC_EIR_HBERR (0x80000000) - -/* Bit definitions and macros for MCF_FEC_EIMR */ -#define MCF_FEC_EIMR_UN (0x00080000) -#define MCF_FEC_EIMR_RL (0x00100000) -#define MCF_FEC_EIMR_LC (0x00200000) -#define MCF_FEC_EIMR_EBERR (0x00400000) -#define MCF_FEC_EIMR_MII (0x00800000) -#define MCF_FEC_EIMR_RXB (0x01000000) -#define MCF_FEC_EIMR_RXF (0x02000000) -#define MCF_FEC_EIMR_TXB (0x04000000) -#define MCF_FEC_EIMR_TXF (0x08000000) -#define MCF_FEC_EIMR_GRA (0x10000000) -#define MCF_FEC_EIMR_BABT (0x20000000) -#define MCF_FEC_EIMR_BABR (0x40000000) -#define MCF_FEC_EIMR_HBERR (0x80000000) - -/* Bit definitions and macros for MCF_FEC_RDAR */ -#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for MCF_FEC_TDAR */ -#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for MCF_FEC_ECR */ -#define MCF_FEC_ECR_RESET (0x00000001) -#define MCF_FEC_ECR_ETHER_EN (0x00000002) - -/* Bit definitions and macros for MCF_FEC_MMFR */ -#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) -#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) -#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) -#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) -#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) -#define MCF_FEC_MMFR_ST_01 (0x40000000) -#define MCF_FEC_MMFR_OP_READ (0x20000000) -#define MCF_FEC_MMFR_OP_WRITE (0x10000000) -#define MCF_FEC_MMFR_TA_10 (0x00020000) - - -/* Bit definitions and macros for MCF_FEC_MSCR */ -#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) -#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080) - -/* Bit definitions and macros for MCF_FEC_MIBC */ -#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) -#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) - -/* Bit definitions and macros for MCF_FEC_RCR */ -#define MCF_FEC_RCR_LOOP (0x00000001) -#define MCF_FEC_RCR_DRT (0x00000002) -#define MCF_FEC_RCR_MII_MODE (0x00000004) -#define MCF_FEC_RCR_PROM (0x00000008) -#define MCF_FEC_RCR_BC_REJ (0x00000010) -#define MCF_FEC_RCR_FCE (0x00000020) -#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) - -/* Bit definitions and macros for MCF_FEC_TCR */ -#define MCF_FEC_TCR_GTS (0x00000001) -#define MCF_FEC_TCR_HBC (0x00000002) -#define MCF_FEC_TCR_FDEN (0x00000004) -#define MCF_FEC_TCR_TFC_PAUSE (0x00000008) -#define MCF_FEC_TCR_RFC_PAUSE (0x00000010) - -/* Bit definitions and macros for MCF_FEC_PAUR */ -#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_OPD */ -#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_TFWR */ -#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0) - -/* Bit definitions and macros for MCF_FEC_FRBR */ -#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2) - -/* Bit definitions and macros for MCF_FEC_FRSR */ -#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2) - -/* Bit definitions and macros for MCF_FEC_ERDSR */ -#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_FEC_ETDSR */ -#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_FEC_EMRBR */ -#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4) - -/********************************************************************/ - -#endif /* __MCF523X_FEC_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_fmpll.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_fmpll.h deleted file mode 100644 index acf8505ac..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_fmpll.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * File: mcf523x_fmpll.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_FMPLL_H__ -#define __MCF523X_FMPLL_H__ - -/********************************************************************* -* -* Frequency Modulated Phase Locked Loop (FMPLL) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_FMPLL_SYNCR (*(vuint32*)(void*)(&__IPSBAR[0x120000])) -#define MCF_FMPLL_SYNSR (*(vuint32*)(void*)(&__IPSBAR[0x120004])) - -/* Bit definitions and macros for MCF_FMPLL_SYNCR */ -#define MCF_FMPLL_SYNCR_EXP(x) (((x)&0x000003FF)<<0) -#define MCF_FMPLL_SYNCR_DEPTH(x) (((x)&0x00000003)<<10) -#define MCF_FMPLL_SYNCR_RATE (0x00001000) -#define MCF_FMPLL_SYNCR_LOCIRQ (0x00002000) -#define MCF_FMPLL_SYNCR_LOLIRQ (0x00004000) -#define MCF_FMPLL_SYNCR_DISCLK (0x00008000) -#define MCF_FMPLL_SYNCR_LOCRE (0x00010000) -#define MCF_FMPLL_SYNCR_LOLRE (0x00020000) -#define MCF_FMPLL_SYNCR_LOCEN (0x00040000) -#define MCF_FMPLL_SYNCR_RFD(x) (((x)&0x00000007)<<19) -#define MCF_FMPLL_SYNCR_MFD(x) (((x)&0x00000007)<<24) - -/* Bit definitions and macros for MCF_FMPLL_SYNSR */ -#define MCF_FMPLL_SYNSR_CALPASS (0x00000001) -#define MCF_FMPLL_SYNSR_CALDONE (0x00000002) -#define MCF_FMPLL_SYNSR_LOCF (0x00000004) -#define MCF_FMPLL_SYNSR_LOCK (0x00000008) -#define MCF_FMPLL_SYNSR_LOCKS (0x00000010) -#define MCF_FMPLL_SYNSR_PLLREF (0x00000020) -#define MCF_FMPLL_SYNSR_PLLSEL (0x00000040) -#define MCF_FMPLL_SYNSR_MODE (0x00000080) -#define MCF_FMPLL_SYNSR_LOC (0x00000100) -#define MCF_FMPLL_SYNSR_LOLF (0x00000200) - -/********************************************************************/ - -#endif /* __MCF523X_FMPLL_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_gpio.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_gpio.h deleted file mode 100644 index e787dbe0e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_gpio.h +++ /dev/null @@ -1,680 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_GPIO_H__ -#define __MCF523X_GPIO_H__ - -/********************************************************************* -* -* General Purpose I/O (GPIO) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_GPIO_PODR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100000])) -#define MCF_GPIO_PODR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100001])) -#define MCF_GPIO_PODR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100002])) -#define MCF_GPIO_PODR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100003])) -#define MCF_GPIO_PODR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100004])) -#define MCF_GPIO_PODR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100005])) -#define MCF_GPIO_PODR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100006])) -#define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100007])) -#define MCF_GPIO_PODR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100008])) -#define MCF_GPIO_PODR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100009])) -#define MCF_GPIO_PODR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10000A])) -#define MCF_GPIO_PODR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10000B])) -#define MCF_GPIO_PODR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10000C])) -#define MCF_GPIO_PDDR_APDDR (*(vuint8 *)(void*)(&__IPSBAR[0x100010])) -#define MCF_GPIO_PDDR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100011])) -#define MCF_GPIO_PDDR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100012])) -#define MCF_GPIO_PDDR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100013])) -#define MCF_GPIO_PDDR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100014])) -#define MCF_GPIO_PDDR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100015])) -#define MCF_GPIO_PDDR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100016])) -#define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100017])) -#define MCF_GPIO_PDDR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100018])) -#define MCF_GPIO_PDDR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100019])) -#define MCF_GPIO_PDDR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10001A])) -#define MCF_GPIO_PDDR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10001B])) -#define MCF_GPIO_PDDR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10001C])) -#define MCF_GPIO_PPDSDR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100020])) -#define MCF_GPIO_PPDSDR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100021])) -#define MCF_GPIO_PPDSDR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100022])) -#define MCF_GPIO_PPDSDR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100023])) -#define MCF_GPIO_PPDSDR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100024])) -#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100027])) -#define MCF_GPIO_PPDSDR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100025])) -#define MCF_GPIO_PPDSDR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100026])) -#define MCF_GPIO_PPDSDR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100028])) -#define MCF_GPIO_PPDSDR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100029])) -#define MCF_GPIO_PPDSDR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10002A])) -#define MCF_GPIO_PPDSDR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10002B])) -#define MCF_GPIO_PPDSDR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10002C])) -#define MCF_GPIO_PCLRR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100030])) -#define MCF_GPIO_PCLRR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100031])) -#define MCF_GPIO_PCLRR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100032])) -#define MCF_GPIO_PCLRR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100033])) -#define MCF_GPIO_PCLRR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100034])) -#define MCF_GPIO_PCLRR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100035])) -#define MCF_GPIO_PCLRR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100036])) -#define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100037])) -#define MCF_GPIO_PCLRR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100038])) -#define MCF_GPIO_PCLRR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100039])) -#define MCF_GPIO_PCLRR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10003A])) -#define MCF_GPIO_PCLRR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10003B])) -#define MCF_GPIO_PCLRR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10003C])) -#define MCF_GPIO_PAR_AD (*(vuint8 *)(void*)(&__IPSBAR[0x100040])) -#define MCF_GPIO_PAR_BUSCTL (*(vuint16*)(void*)(&__IPSBAR[0x100042])) -#define MCF_GPIO_PAR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100044])) -#define MCF_GPIO_PAR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100045])) -#define MCF_GPIO_PAR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100046])) -#define MCF_GPIO_PAR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100047])) -#define MCF_GPIO_PAR_UART (*(vuint16*)(void*)(&__IPSBAR[0x100048])) -#define MCF_GPIO_PAR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10004A])) -#define MCF_GPIO_PAR_TIMER (*(vuint16*)(void*)(&__IPSBAR[0x10004C])) -#define MCF_GPIO_PAR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10004E])) -#define MCF_GPIO_DSCR_EIM (*(vuint8 *)(void*)(&__IPSBAR[0x100050])) -#define MCF_GPIO_DSCR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x100051])) -#define MCF_GPIO_DSCR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100052])) -#define MCF_GPIO_DSCR_UART (*(vuint8 *)(void*)(&__IPSBAR[0x100053])) -#define MCF_GPIO_DSCR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x100054])) -#define MCF_GPIO_DSCR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x100055])) - -/* Bit definitions and macros for MCF_GPIO_PODR_ADDR */ -#define MCF_GPIO_PODR_ADDR_PODR_ADDR5 (0x20) -#define MCF_GPIO_PODR_ADDR_PODR_ADDR6 (0x40) -#define MCF_GPIO_PODR_ADDR_PODR_ADDR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_DATAH */ -#define MCF_GPIO_PODR_DATAH_PODR_DATAH0 (0x01) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH1 (0x02) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH2 (0x04) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH3 (0x08) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH4 (0x10) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH5 (0x20) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH6 (0x40) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_DATAL */ -#define MCF_GPIO_PODR_DATAL_PODR_DATAL0 (0x01) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL1 (0x02) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL2 (0x04) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL3 (0x08) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL4 (0x10) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL5 (0x20) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL6 (0x40) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */ -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL0 (0x01) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL4 (0x10) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL5 (0x20) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL6 (0x40) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_BS */ -#define MCF_GPIO_PODR_BS_PODR_BS0 (0x01) -#define MCF_GPIO_PODR_BS_PODR_BS1 (0x02) -#define MCF_GPIO_PODR_BS_PODR_BS2 (0x04) -#define MCF_GPIO_PODR_BS_PODR_BS3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_CS */ -#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02) -#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04) -#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08) -#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10) -#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20) -#define MCF_GPIO_PODR_CS_PODR_CS6 (0x40) -#define MCF_GPIO_PODR_CS_PODR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_SDRAM */ -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM0 (0x01) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM1 (0x02) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM2 (0x04) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM3 (0x08) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM4 (0x10) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_UARTH */ -#define MCF_GPIO_PODR_UARTH_PODR_UARTH0 (0x01) -#define MCF_GPIO_PODR_UARTH_PODR_UARTH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PODR_UARTL */ -#define MCF_GPIO_PODR_UARTL_PODR_UARTL0 (0x01) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL1 (0x02) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL2 (0x04) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL3 (0x08) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL4 (0x10) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL5 (0x20) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL6 (0x40) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */ -#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */ -#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER4 (0x10) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER5 (0x20) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER6 (0x40) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_ETPU */ -#define MCF_GPIO_PODR_ETPU_PODR_ETPU0 (0x01) -#define MCF_GPIO_PODR_ETPU_PODR_ETPU1 (0x02) -#define MCF_GPIO_PODR_ETPU_PODR_ETPU2 (0x04) - -/* Bit definitions and macros for MCF_GPIO_PDDR_APDDR */ -#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR5 (0x20) -#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR6 (0x40) -#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_DATAH */ -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH0 (0x01) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH1 (0x02) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH2 (0x04) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH3 (0x08) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH4 (0x10) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH5 (0x20) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH6 (0x40) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_DATAL */ -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL0 (0x01) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL1 (0x02) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL2 (0x04) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL3 (0x08) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL4 (0x10) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL5 (0x20) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL6 (0x40) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */ -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0 (0x01) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL4 (0x10) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL5 (0x20) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL6 (0x40) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_BS */ -#define MCF_GPIO_PDDR_BS_PDDR_BS0 (0x01) -#define MCF_GPIO_PDDR_BS_PDDR_BS3(x) (((x)&0x07)<<1) - -/* Bit definitions and macros for MCF_GPIO_PDDR_CS */ -#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02) -#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04) -#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08) -#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10) -#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20) -#define MCF_GPIO_PDDR_CS_PDDR_CS6 (0x40) -#define MCF_GPIO_PDDR_CS_PDDR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_SDRAM */ -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM0 (0x01) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM1 (0x02) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM2 (0x04) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM3 (0x08) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM4 (0x10) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_UARTH */ -#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH0 (0x01) -#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PDDR_UARTL */ -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL0 (0x01) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL1 (0x02) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL2 (0x04) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL3 (0x08) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL4 (0x10) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL5 (0x20) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL6 (0x40) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */ -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */ -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER4 (0x10) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER5 (0x20) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER6 (0x40) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_ETPU */ -#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU0 (0x01) -#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU1 (0x02) -#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU2 (0x04) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_ADDR */ -#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR5 (0x20) -#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR6 (0x40) -#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAH */ -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH0 (0x01) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH1 (0x02) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH2 (0x04) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH3 (0x08) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH4 (0x10) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH5 (0x20) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH6 (0x40) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAL */ -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL0 (0x01) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL1 (0x02) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL2 (0x04) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL3 (0x08) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL4 (0x10) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL5 (0x20) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL6 (0x40) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */ -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL0 (0x01) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL4 (0x10) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL5 (0x20) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL6 (0x40) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_BS */ -#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS0 (0x01) -#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS1 (0x02) -#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS2 (0x04) -#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */ -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS6 (0x40) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_SDRAM */ -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM0 (0x01) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM1 (0x02) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM2 (0x04) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM3 (0x08) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM4 (0x10) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM5 (0x20) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM6 (0x40) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTH */ -#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH0 (0x01) -#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTL */ -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL0 (0x01) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL1 (0x02) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL2 (0x04) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL3 (0x08) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL4 (0x10) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL5 (0x20) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL6 (0x40) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */ -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */ -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER4 (0x10) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER5 (0x20) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER6 (0x40) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_ETPU */ -#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU0 (0x01) -#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU1 (0x02) -#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU2 (0x04) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_ADDR */ -#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR5 (0x20) -#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR6 (0x40) -#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAH */ -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH0 (0x01) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH1 (0x02) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH2 (0x04) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH3 (0x08) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH4 (0x10) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH5 (0x20) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH6 (0x40) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAL */ -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL0 (0x01) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL1 (0x02) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL2 (0x04) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL3 (0x08) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL4 (0x10) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL5 (0x20) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL6 (0x40) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */ -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL0 (0x01) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL4 (0x10) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL5 (0x20) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL6 (0x40) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_BS */ -#define MCF_GPIO_PCLRR_BS_PCLRR_BS0 (0x01) -#define MCF_GPIO_PCLRR_BS_PCLRR_BS1 (0x02) -#define MCF_GPIO_PCLRR_BS_PCLRR_BS2 (0x04) -#define MCF_GPIO_PCLRR_BS_PCLRR_BS3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */ -#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS6 (0x40) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_SDRAM */ -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM0 (0x01) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM1 (0x02) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM2 (0x04) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM3 (0x08) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM4 (0x10) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTH */ -#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH0 (0x01) -#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTL */ -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL0 (0x01) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL1 (0x02) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL2 (0x04) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL3 (0x08) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL4 (0x10) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL5 (0x20) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL6 (0x40) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */ -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */ -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER4 (0x10) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER5 (0x20) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER6 (0x40) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_ETPU */ -#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU0 (0x01) -#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU1 (0x02) -#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU2 (0x04) - -/* Bit definitions and macros for MCF_GPIO_PAR_AD */ -#define MCF_GPIO_PAR_AD_PAR_DATAL (0x01) -#define MCF_GPIO_PAR_AD_PAR_ADDR21 (0x20) -#define MCF_GPIO_PAR_AD_PAR_ADDR22 (0x40) -#define MCF_GPIO_PAR_AD_PAR_ADDR23 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */ -#define MCF_GPIO_PAR_BUSCTL_PAR_TIP(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 (0x0010) -#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 (0x0040) -#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x0100) -#define MCF_GPIO_PAR_BUSCTL_PAR_TEA(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x1000) -#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x4000) -#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_GPIO (0x0000) -#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_DMA (0x0800) -#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_TEA (0x0C00) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x0000) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DMA (0x0080) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x00C0) -#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_GPIO (0x0000) -#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_DMA (0x0002) -#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_TEA (0x0003) - -/* Bit definitions and macros for MCF_GPIO_PAR_BS */ -#define MCF_GPIO_PAR_BS_PAR_BS0 (0x01) -#define MCF_GPIO_PAR_BS_PAR_BS1 (0x02) -#define MCF_GPIO_PAR_BS_PAR_BS2 (0x04) -#define MCF_GPIO_PAR_BS_PAR_BS3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PAR_CS */ -#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02) -#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04) -#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08) -#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10) -#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20) -#define MCF_GPIO_PAR_CS_PAR_CS6 (0x40) -#define MCF_GPIO_PAR_CS_PAR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PAR_SDRAM */ -#define MCF_GPIO_PAR_SDRAM_PAR_SDCS0 (0x01) -#define MCF_GPIO_PAR_SDRAM_PAR_SDCS1 (0x02) -#define MCF_GPIO_PAR_SDRAM_PAR_SCKE (0x04) -#define MCF_GPIO_PAR_SDRAM_PAR_SRAS (0x08) -#define MCF_GPIO_PAR_SDRAM_PAR_SCAS (0x10) -#define MCF_GPIO_PAR_SDRAM_PAR_SDWE (0x20) -#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) - -/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */ -#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_UART2 (0x40) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_I2C (0x80) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC (0xC0) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_UART2 (0x10) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_I2C (0x20) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC (0x30) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_FLEX (0x08) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_I2C (0x0C) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_FLEX (0x02) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_I2C (0x03) - -/* Bit definitions and macros for MCF_GPIO_PAR_UART */ -#define MCF_GPIO_PAR_UART_PAR_U0RTS (0x0001) -#define MCF_GPIO_PAR_UART_PAR_U0CTS (0x0002) -#define MCF_GPIO_PAR_UART_PAR_U0TXD (0x0004) -#define MCF_GPIO_PAR_UART_PAR_U0RXD (0x0008) -#define MCF_GPIO_PAR_UART_PAR_U1RTS(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_UART_PAR_U1CTS(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_UART_PAR_U1TXD(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_UART_PAR_U1RXD(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_UART_PAR_U2TXD (0x1000) -#define MCF_GPIO_PAR_UART_PAR_U2RXD (0x2000) -#define MCF_GPIO_PAR_UART_PAR_CAN1EN (0x4000) -#define MCF_GPIO_PAR_UART_PAR_DREQ2 (0x8000) -#define MCF_GPIO_PAR_UART_PAR_U1RXD_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_U1RXD_FLEX (0x0800) -#define MCF_GPIO_PAR_UART_PAR_U1RXD_UART1 (0x0C00) -#define MCF_GPIO_PAR_UART_PAR_U1TXD_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_U1TXD_FLEX (0x0200) -#define MCF_GPIO_PAR_UART_PAR_U1TXD_UART1 (0x0300) -#define MCF_GPIO_PAR_UART_PAR_U1CTS_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART2 (0x0080) -#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART1 (0x00C0) -#define MCF_GPIO_PAR_UART_PAR_U1RTS_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART2 (0x0020) -#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART1 (0x0030) - -/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */ -#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_QSPI_PAR_DOUT (0x04) -#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x03)<<3) -#define MCF_GPIO_PAR_QSPI_PAR_PCS0 (0x20) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1_GPIO (0x00) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1_SDRAMC (0x80) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1_QSPI (0xC0) -#define MCF_GPIO_PAR_QSPI_PAR_DIN_GPIO (0x00) -#define MCF_GPIO_PAR_QSPI_PAR_DIN_I2C (0x10) -#define MCF_GPIO_PAR_QSPI_PAR_DIN_QSPI (0x1C) -#define MCF_GPIO_PAR_QSPI_PAR_SCK_GPIO (0x00) -#define MCF_GPIO_PAR_QSPI_PAR_SCK_I2C (0x02) -#define MCF_GPIO_PAR_QSPI_PAR_SCK_QSPI (0x03) - -/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ -#define MCF_GPIO_PAR_TIMER_PAR_T0OUT(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_TIMER_PAR_T1OUT(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PAR_TIMER_PAR_T2OUT(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_TIMER_PAR_T0IN(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN(x) (((x)&0x0003)<<12) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN(x) (((x)&0x0003)<<14) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN_QSPI (0x4000) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN_UART2 (0x8000) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN_T3IN (0xC000) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2OUT (0x1000) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN_DMA (0x2000) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2IN (0x3000) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1OUT (0x0400) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN_DMA (0x0800) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1IN (0x0C00) -#define MCF_GPIO_PAR_TIMER_PAR_T0IN_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T0IN_DMA (0x0200) -#define MCF_GPIO_PAR_TIMER_PAR_T0IN_T0IN (0x0300) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_QSPI (0x0040) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_UART2 (0x0080) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_T3OUT (0x00C0) -#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_DMA (0x0020) -#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_T2OUT (0x0030) -#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_DMA (0x0008) -#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_T1OUT (0x000C) -#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_DMA (0x0002) -#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_T0OUT (0x0003) - -/* Bit definitions and macros for MCF_GPIO_PAR_ETPU */ -#define MCF_GPIO_PAR_ETPU_PAR_LTPU_ODIS (0x01) -#define MCF_GPIO_PAR_ETPU_PAR_UTPU_ODIS (0x02) -#define MCF_GPIO_PAR_ETPU_PAR_TCRCLK (0x04) - -/* Bit definitions and macros for MCF_GPIO_DSCR_EIM */ -#define MCF_GPIO_DSCR_EIM_DSCR_EIM0 (0x01) -#define MCF_GPIO_DSCR_EIM_DSCR_EIM1 (0x10) - -/* Bit definitions and macros for MCF_GPIO_DSCR_ETPU */ -#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_7_0 (0x01) -#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_15_8 (0x04) -#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_23_16 (0x10) -#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_31_24 (0x40) - -/* Bit definitions and macros for MCF_GPIO_DSCR_FECI2C */ -#define MCF_GPIO_DSCR_FECI2C_DSCR_I2C (0x01) -#define MCF_GPIO_DSCR_FECI2C_DSCR_FEC (0x10) - -/* Bit definitions and macros for MCF_GPIO_DSCR_UART */ -#define MCF_GPIO_DSCR_UART_DSCR_UART0 (0x01) -#define MCF_GPIO_DSCR_UART_DSCR_UART1 (0x04) -#define MCF_GPIO_DSCR_UART_DSCR_UART2 (0x10) -#define MCF_GPIO_DSCR_UART_DSCR_IRQ (0x40) - -/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */ -#define MCF_GPIO_DSCR_QSPI_DSCR_QSPI (0x01) - -/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */ -#define MCF_GPIO_DSCR_TIMER_DSCR_TIMER (0x01) - -/********************************************************************/ - -#endif /* __MCF523X_GPIO_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_i2c.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_i2c.h deleted file mode 100644 index aa20e8982..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_i2c.h +++ /dev/null @@ -1,67 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_I2C_H__ -#define __MCF523X_I2C_H__ - -/********************************************************************* -* -* I2C Module (I2C) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_I2C_I2AR (*(vuint8 *)(void*)(&__IPSBAR[0x000300])) -#define MCF_I2C_I2FDR (*(vuint8 *)(void*)(&__IPSBAR[0x000304])) -#define MCF_I2C_I2CR (*(vuint8 *)(void*)(&__IPSBAR[0x000308])) -#define MCF_I2C_I2SR (*(vuint8 *)(void*)(&__IPSBAR[0x00030C])) -#define MCF_I2C_I2DR (*(vuint8 *)(void*)(&__IPSBAR[0x000310])) -#define MCF_I2C_I2ICR (*(vuint8 *)(void*)(&__IPSBAR[0x000320])) - -/* Bit definitions and macros for MCF_I2C_I2AR */ -#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_I2C_I2FDR */ -#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) - -/* Bit definitions and macros for MCF_I2C_I2CR */ -#define MCF_I2C_I2CR_RSTA (0x04) -#define MCF_I2C_I2CR_TXAK (0x08) -#define MCF_I2C_I2CR_MTX (0x10) -#define MCF_I2C_I2CR_MSTA (0x20) -#define MCF_I2C_I2CR_IIEN (0x40) -#define MCF_I2C_I2CR_IEN (0x80) - -/* Bit definitions and macros for MCF_I2C_I2SR */ -#define MCF_I2C_I2SR_RXAK (0x01) -#define MCF_I2C_I2SR_IIF (0x02) -#define MCF_I2C_I2SR_SRW (0x04) -#define MCF_I2C_I2SR_IAL (0x10) -#define MCF_I2C_I2SR_IBB (0x20) -#define MCF_I2C_I2SR_IAAS (0x40) -#define MCF_I2C_I2SR_ICF (0x80) - -/* Bit definitions and macros for MCF_I2C_I2ICR */ -#define MCF_I2C_I2ICR_IE (0x01) -#define MCF_I2C_I2ICR_RE (0x02) -#define MCF_I2C_I2ICR_TE (0x04) -#define MCF_I2C_I2ICR_BNBE (0x08) - -/********************************************************************/ - -#endif /* __MCF523X_I2C_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_intc0.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_intc0.h deleted file mode 100644 index a2c327464..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_intc0.h +++ /dev/null @@ -1,327 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_INTC0_H__ -#define __MCF523X_INTC0_H__ - -/********************************************************************* -* -* Interrupt Controller 0 (INTC0) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_INTC0_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000C00])) -#define MCF_INTC0_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000C04])) -#define MCF_INTC0_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000C08])) -#define MCF_INTC0_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000C0C])) -#define MCF_INTC0_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000C10])) -#define MCF_INTC0_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000C14])) -#define MCF_INTC0_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000C18])) -#define MCF_INTC0_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000C19])) -#define MCF_INTC0_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000C40])) -#define MCF_INTC0_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000C41])) -#define MCF_INTC0_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000C42])) -#define MCF_INTC0_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000C43])) -#define MCF_INTC0_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000C44])) -#define MCF_INTC0_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000C45])) -#define MCF_INTC0_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000C46])) -#define MCF_INTC0_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000C47])) -#define MCF_INTC0_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000C48])) -#define MCF_INTC0_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000C49])) -#define MCF_INTC0_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4A])) -#define MCF_INTC0_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4B])) -#define MCF_INTC0_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4C])) -#define MCF_INTC0_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4D])) -#define MCF_INTC0_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4E])) -#define MCF_INTC0_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4F])) -#define MCF_INTC0_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000C50])) -#define MCF_INTC0_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000C51])) -#define MCF_INTC0_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000C52])) -#define MCF_INTC0_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000C53])) -#define MCF_INTC0_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000C54])) -#define MCF_INTC0_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000C55])) -#define MCF_INTC0_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000C56])) -#define MCF_INTC0_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000C57])) -#define MCF_INTC0_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000C58])) -#define MCF_INTC0_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000C59])) -#define MCF_INTC0_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5A])) -#define MCF_INTC0_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5B])) -#define MCF_INTC0_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5C])) -#define MCF_INTC0_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5D])) -#define MCF_INTC0_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5E])) -#define MCF_INTC0_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5F])) -#define MCF_INTC0_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000C60])) -#define MCF_INTC0_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000C61])) -#define MCF_INTC0_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000C62])) -#define MCF_INTC0_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000C63])) -#define MCF_INTC0_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000C64])) -#define MCF_INTC0_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000C65])) -#define MCF_INTC0_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000C66])) -#define MCF_INTC0_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000C67])) -#define MCF_INTC0_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000C68])) -#define MCF_INTC0_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000C69])) -#define MCF_INTC0_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6A])) -#define MCF_INTC0_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6B])) -#define MCF_INTC0_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6C])) -#define MCF_INTC0_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6D])) -#define MCF_INTC0_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6E])) -#define MCF_INTC0_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6F])) -#define MCF_INTC0_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000C70])) -#define MCF_INTC0_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000C71])) -#define MCF_INTC0_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000C72])) -#define MCF_INTC0_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000C73])) -#define MCF_INTC0_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000C74])) -#define MCF_INTC0_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000C75])) -#define MCF_INTC0_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000C76])) -#define MCF_INTC0_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000C77])) -#define MCF_INTC0_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000C78])) -#define MCF_INTC0_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000C79])) -#define MCF_INTC0_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7A])) -#define MCF_INTC0_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7B])) -#define MCF_INTC0_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7C])) -#define MCF_INTC0_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7D])) -#define MCF_INTC0_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7E])) -#define MCF_INTC0_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7F])) -#define MCF_INTC0_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000C40+((x)*0x001)])) -#define MCF_INTC0_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE0])) -#define MCF_INTC0_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4])) -#define MCF_INTC0_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE8])) -#define MCF_INTC0_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CEC])) -#define MCF_INTC0_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF0])) -#define MCF_INTC0_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF4])) -#define MCF_INTC0_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF8])) -#define MCF_INTC0_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CFC])) -#define MCF_INTC0_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4+((x)*0x004)])) - -/* Bit definitions and macros for MCF_INTC0_IPRH */ -#define MCF_INTC0_IPRH_INT32 (0x00000001) -#define MCF_INTC0_IPRH_INT33 (0x00000002) -#define MCF_INTC0_IPRH_INT34 (0x00000004) -#define MCF_INTC0_IPRH_INT35 (0x00000008) -#define MCF_INTC0_IPRH_INT36 (0x00000010) -#define MCF_INTC0_IPRH_INT37 (0x00000020) -#define MCF_INTC0_IPRH_INT38 (0x00000040) -#define MCF_INTC0_IPRH_INT39 (0x00000080) -#define MCF_INTC0_IPRH_INT40 (0x00000100) -#define MCF_INTC0_IPRH_INT41 (0x00000200) -#define MCF_INTC0_IPRH_INT42 (0x00000400) -#define MCF_INTC0_IPRH_INT43 (0x00000800) -#define MCF_INTC0_IPRH_INT44 (0x00001000) -#define MCF_INTC0_IPRH_INT45 (0x00002000) -#define MCF_INTC0_IPRH_INT46 (0x00004000) -#define MCF_INTC0_IPRH_INT47 (0x00008000) -#define MCF_INTC0_IPRH_INT48 (0x00010000) -#define MCF_INTC0_IPRH_INT49 (0x00020000) -#define MCF_INTC0_IPRH_INT50 (0x00040000) -#define MCF_INTC0_IPRH_INT51 (0x00080000) -#define MCF_INTC0_IPRH_INT52 (0x00100000) -#define MCF_INTC0_IPRH_INT53 (0x00200000) -#define MCF_INTC0_IPRH_INT54 (0x00400000) -#define MCF_INTC0_IPRH_INT55 (0x00800000) -#define MCF_INTC0_IPRH_INT56 (0x01000000) -#define MCF_INTC0_IPRH_INT57 (0x02000000) -#define MCF_INTC0_IPRH_INT58 (0x04000000) -#define MCF_INTC0_IPRH_INT59 (0x08000000) -#define MCF_INTC0_IPRH_INT60 (0x10000000) -#define MCF_INTC0_IPRH_INT61 (0x20000000) -#define MCF_INTC0_IPRH_INT62 (0x40000000) -#define MCF_INTC0_IPRH_INT63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_IPRL */ -#define MCF_INTC0_IPRL_INT1 (0x00000002) -#define MCF_INTC0_IPRL_INT2 (0x00000004) -#define MCF_INTC0_IPRL_INT3 (0x00000008) -#define MCF_INTC0_IPRL_INT4 (0x00000010) -#define MCF_INTC0_IPRL_INT5 (0x00000020) -#define MCF_INTC0_IPRL_INT6 (0x00000040) -#define MCF_INTC0_IPRL_INT7 (0x00000080) -#define MCF_INTC0_IPRL_INT8 (0x00000100) -#define MCF_INTC0_IPRL_INT9 (0x00000200) -#define MCF_INTC0_IPRL_INT10 (0x00000400) -#define MCF_INTC0_IPRL_INT11 (0x00000800) -#define MCF_INTC0_IPRL_INT12 (0x00001000) -#define MCF_INTC0_IPRL_INT13 (0x00002000) -#define MCF_INTC0_IPRL_INT14 (0x00004000) -#define MCF_INTC0_IPRL_INT15 (0x00008000) -#define MCF_INTC0_IPRL_INT16 (0x00010000) -#define MCF_INTC0_IPRL_INT17 (0x00020000) -#define MCF_INTC0_IPRL_INT18 (0x00040000) -#define MCF_INTC0_IPRL_INT19 (0x00080000) -#define MCF_INTC0_IPRL_INT20 (0x00100000) -#define MCF_INTC0_IPRL_INT21 (0x00200000) -#define MCF_INTC0_IPRL_INT22 (0x00400000) -#define MCF_INTC0_IPRL_INT23 (0x00800000) -#define MCF_INTC0_IPRL_INT24 (0x01000000) -#define MCF_INTC0_IPRL_INT25 (0x02000000) -#define MCF_INTC0_IPRL_INT26 (0x04000000) -#define MCF_INTC0_IPRL_INT27 (0x08000000) -#define MCF_INTC0_IPRL_INT28 (0x10000000) -#define MCF_INTC0_IPRL_INT29 (0x20000000) -#define MCF_INTC0_IPRL_INT30 (0x40000000) -#define MCF_INTC0_IPRL_INT31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_IMRH */ -#define MCF_INTC0_IMRH_INT_MASK32 (0x00000001) -#define MCF_INTC0_IMRH_INT_MASK33 (0x00000002) -#define MCF_INTC0_IMRH_INT_MASK34 (0x00000004) -#define MCF_INTC0_IMRH_INT_MASK35 (0x00000008) -#define MCF_INTC0_IMRH_INT_MASK36 (0x00000010) -#define MCF_INTC0_IMRH_INT_MASK37 (0x00000020) -#define MCF_INTC0_IMRH_INT_MASK38 (0x00000040) -#define MCF_INTC0_IMRH_INT_MASK39 (0x00000080) -#define MCF_INTC0_IMRH_INT_MASK40 (0x00000100) -#define MCF_INTC0_IMRH_INT_MASK41 (0x00000200) -#define MCF_INTC0_IMRH_INT_MASK42 (0x00000400) -#define MCF_INTC0_IMRH_INT_MASK43 (0x00000800) -#define MCF_INTC0_IMRH_INT_MASK44 (0x00001000) -#define MCF_INTC0_IMRH_INT_MASK45 (0x00002000) -#define MCF_INTC0_IMRH_INT_MASK46 (0x00004000) -#define MCF_INTC0_IMRH_INT_MASK47 (0x00008000) -#define MCF_INTC0_IMRH_INT_MASK48 (0x00010000) -#define MCF_INTC0_IMRH_INT_MASK49 (0x00020000) -#define MCF_INTC0_IMRH_INT_MASK50 (0x00040000) -#define MCF_INTC0_IMRH_INT_MASK51 (0x00080000) -#define MCF_INTC0_IMRH_INT_MASK52 (0x00100000) -#define MCF_INTC0_IMRH_INT_MASK53 (0x00200000) -#define MCF_INTC0_IMRH_INT_MASK54 (0x00400000) -#define MCF_INTC0_IMRH_INT_MASK55 (0x00800000) -#define MCF_INTC0_IMRH_INT_MASK56 (0x01000000) -#define MCF_INTC0_IMRH_INT_MASK57 (0x02000000) -#define MCF_INTC0_IMRH_INT_MASK58 (0x04000000) -#define MCF_INTC0_IMRH_INT_MASK59 (0x08000000) -#define MCF_INTC0_IMRH_INT_MASK60 (0x10000000) -#define MCF_INTC0_IMRH_INT_MASK61 (0x20000000) -#define MCF_INTC0_IMRH_INT_MASK62 (0x40000000) -#define MCF_INTC0_IMRH_INT_MASK63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_IMRL */ -#define MCF_INTC0_IMRL_MASKALL (0x00000001) -#define MCF_INTC0_IMRL_INT_MASK1 (0x00000002) -#define MCF_INTC0_IMRL_INT_MASK2 (0x00000004) -#define MCF_INTC0_IMRL_INT_MASK3 (0x00000008) -#define MCF_INTC0_IMRL_INT_MASK4 (0x00000010) -#define MCF_INTC0_IMRL_INT_MASK5 (0x00000020) -#define MCF_INTC0_IMRL_INT_MASK6 (0x00000040) -#define MCF_INTC0_IMRL_INT_MASK7 (0x00000080) -#define MCF_INTC0_IMRL_INT_MASK8 (0x00000100) -#define MCF_INTC0_IMRL_INT_MASK9 (0x00000200) -#define MCF_INTC0_IMRL_INT_MASK10 (0x00000400) -#define MCF_INTC0_IMRL_INT_MASK11 (0x00000800) -#define MCF_INTC0_IMRL_INT_MASK12 (0x00001000) -#define MCF_INTC0_IMRL_INT_MASK13 (0x00002000) -#define MCF_INTC0_IMRL_INT_MASK14 (0x00004000) -#define MCF_INTC0_IMRL_INT_MASK15 (0x00008000) -#define MCF_INTC0_IMRL_INT_MASK16 (0x00010000) -#define MCF_INTC0_IMRL_INT_MASK17 (0x00020000) -#define MCF_INTC0_IMRL_INT_MASK18 (0x00040000) -#define MCF_INTC0_IMRL_INT_MASK19 (0x00080000) -#define MCF_INTC0_IMRL_INT_MASK20 (0x00100000) -#define MCF_INTC0_IMRL_INT_MASK21 (0x00200000) -#define MCF_INTC0_IMRL_INT_MASK22 (0x00400000) -#define MCF_INTC0_IMRL_INT_MASK23 (0x00800000) -#define MCF_INTC0_IMRL_INT_MASK24 (0x01000000) -#define MCF_INTC0_IMRL_INT_MASK25 (0x02000000) -#define MCF_INTC0_IMRL_INT_MASK26 (0x04000000) -#define MCF_INTC0_IMRL_INT_MASK27 (0x08000000) -#define MCF_INTC0_IMRL_INT_MASK28 (0x10000000) -#define MCF_INTC0_IMRL_INT_MASK29 (0x20000000) -#define MCF_INTC0_IMRL_INT_MASK30 (0x40000000) -#define MCF_INTC0_IMRL_INT_MASK31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_INTFRCH */ -#define MCF_INTC0_INTFRCH_INTFRC32 (0x00000001) -#define MCF_INTC0_INTFRCH_INTFRC33 (0x00000002) -#define MCF_INTC0_INTFRCH_INTFRC34 (0x00000004) -#define MCF_INTC0_INTFRCH_INTFRC35 (0x00000008) -#define MCF_INTC0_INTFRCH_INTFRC36 (0x00000010) -#define MCF_INTC0_INTFRCH_INTFRC37 (0x00000020) -#define MCF_INTC0_INTFRCH_INTFRC38 (0x00000040) -#define MCF_INTC0_INTFRCH_INTFRC39 (0x00000080) -#define MCF_INTC0_INTFRCH_INTFRC40 (0x00000100) -#define MCF_INTC0_INTFRCH_INTFRC41 (0x00000200) -#define MCF_INTC0_INTFRCH_INTFRC42 (0x00000400) -#define MCF_INTC0_INTFRCH_INTFRC43 (0x00000800) -#define MCF_INTC0_INTFRCH_INTFRC44 (0x00001000) -#define MCF_INTC0_INTFRCH_INTFRC45 (0x00002000) -#define MCF_INTC0_INTFRCH_INTFRC46 (0x00004000) -#define MCF_INTC0_INTFRCH_INTFRC47 (0x00008000) -#define MCF_INTC0_INTFRCH_INTFRC48 (0x00010000) -#define MCF_INTC0_INTFRCH_INTFRC49 (0x00020000) -#define MCF_INTC0_INTFRCH_INTFRC50 (0x00040000) -#define MCF_INTC0_INTFRCH_INTFRC51 (0x00080000) -#define MCF_INTC0_INTFRCH_INTFRC52 (0x00100000) -#define MCF_INTC0_INTFRCH_INTFRC53 (0x00200000) -#define MCF_INTC0_INTFRCH_INTFRC54 (0x00400000) -#define MCF_INTC0_INTFRCH_INTFRC55 (0x00800000) -#define MCF_INTC0_INTFRCH_INTFRC56 (0x01000000) -#define MCF_INTC0_INTFRCH_INTFRC57 (0x02000000) -#define MCF_INTC0_INTFRCH_INTFRC58 (0x04000000) -#define MCF_INTC0_INTFRCH_INTFRC59 (0x08000000) -#define MCF_INTC0_INTFRCH_INTFRC60 (0x10000000) -#define MCF_INTC0_INTFRCH_INTFRC61 (0x20000000) -#define MCF_INTC0_INTFRCH_INTFRC62 (0x40000000) -#define MCF_INTC0_INTFRCH_INTFRC63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_INTFRCL */ -#define MCF_INTC0_INTFRCL_INTFRC1 (0x00000002) -#define MCF_INTC0_INTFRCL_INTFRC2 (0x00000004) -#define MCF_INTC0_INTFRCL_INTFRC3 (0x00000008) -#define MCF_INTC0_INTFRCL_INTFRC4 (0x00000010) -#define MCF_INTC0_INTFRCL_INTFRC5 (0x00000020) -#define MCF_INTC0_INTFRCL_INT6 (0x00000040) -#define MCF_INTC0_INTFRCL_INT7 (0x00000080) -#define MCF_INTC0_INTFRCL_INT8 (0x00000100) -#define MCF_INTC0_INTFRCL_INT9 (0x00000200) -#define MCF_INTC0_INTFRCL_INT10 (0x00000400) -#define MCF_INTC0_INTFRCL_INTFRC11 (0x00000800) -#define MCF_INTC0_INTFRCL_INTFRC12 (0x00001000) -#define MCF_INTC0_INTFRCL_INTFRC13 (0x00002000) -#define MCF_INTC0_INTFRCL_INTFRC14 (0x00004000) -#define MCF_INTC0_INTFRCL_INT15 (0x00008000) -#define MCF_INTC0_INTFRCL_INTFRC16 (0x00010000) -#define MCF_INTC0_INTFRCL_INTFRC17 (0x00020000) -#define MCF_INTC0_INTFRCL_INTFRC18 (0x00040000) -#define MCF_INTC0_INTFRCL_INTFRC19 (0x00080000) -#define MCF_INTC0_INTFRCL_INTFRC20 (0x00100000) -#define MCF_INTC0_INTFRCL_INTFRC21 (0x00200000) -#define MCF_INTC0_INTFRCL_INTFRC22 (0x00400000) -#define MCF_INTC0_INTFRCL_INTFRC23 (0x00800000) -#define MCF_INTC0_INTFRCL_INTFRC24 (0x01000000) -#define MCF_INTC0_INTFRCL_INTFRC25 (0x02000000) -#define MCF_INTC0_INTFRCL_INTFRC26 (0x04000000) -#define MCF_INTC0_INTFRCL_INTFRC27 (0x08000000) -#define MCF_INTC0_INTFRCL_INTFRC28 (0x10000000) -#define MCF_INTC0_INTFRCL_INTFRC29 (0x20000000) -#define MCF_INTC0_INTFRCL_INTFRC30 (0x40000000) -#define MCF_INTC0_INTFRCL_INTFRC31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_IRLR */ -#define MCF_INTC0_IRLR_IRQ(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_INTC0_IACKLPR */ -#define MCF_INTC0_IACKLPR_PRI(x) (((x)&0x0F)<<0) -#define MCF_INTC0_IACKLPR_LEVEL(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF_INTC0_ICRn */ -#define MCF_INTC0_ICRn_IP(x) (((x)&0x07)<<0) -#define MCF_INTC0_ICRn_IL(x) (((x)&0x07)<<3) - -/********************************************************************/ - -#endif /* __MCF523X_INTC0_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_intc1.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_intc1.h deleted file mode 100644 index c6d41432a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_intc1.h +++ /dev/null @@ -1,327 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_INTC1_H__ -#define __MCF523X_INTC1_H__ - -/********************************************************************* -* -* Interrupt Controller 1 (INTC1) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_INTC1_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000D00])) -#define MCF_INTC1_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000D04])) -#define MCF_INTC1_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000D08])) -#define MCF_INTC1_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000D0C])) -#define MCF_INTC1_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000D10])) -#define MCF_INTC1_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000D14])) -#define MCF_INTC1_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000D18])) -#define MCF_INTC1_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000D19])) -#define MCF_INTC1_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000D40])) -#define MCF_INTC1_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000D41])) -#define MCF_INTC1_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000D42])) -#define MCF_INTC1_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000D43])) -#define MCF_INTC1_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000D44])) -#define MCF_INTC1_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000D45])) -#define MCF_INTC1_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000D46])) -#define MCF_INTC1_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000D47])) -#define MCF_INTC1_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000D48])) -#define MCF_INTC1_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000D49])) -#define MCF_INTC1_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4A])) -#define MCF_INTC1_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4B])) -#define MCF_INTC1_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4C])) -#define MCF_INTC1_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4D])) -#define MCF_INTC1_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4E])) -#define MCF_INTC1_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4F])) -#define MCF_INTC1_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000D50])) -#define MCF_INTC1_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000D51])) -#define MCF_INTC1_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000D52])) -#define MCF_INTC1_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000D53])) -#define MCF_INTC1_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000D54])) -#define MCF_INTC1_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000D55])) -#define MCF_INTC1_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000D56])) -#define MCF_INTC1_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000D57])) -#define MCF_INTC1_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000D58])) -#define MCF_INTC1_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000D59])) -#define MCF_INTC1_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5A])) -#define MCF_INTC1_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5B])) -#define MCF_INTC1_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5C])) -#define MCF_INTC1_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5D])) -#define MCF_INTC1_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5E])) -#define MCF_INTC1_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5F])) -#define MCF_INTC1_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000D60])) -#define MCF_INTC1_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000D61])) -#define MCF_INTC1_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000D62])) -#define MCF_INTC1_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000D63])) -#define MCF_INTC1_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000D64])) -#define MCF_INTC1_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000D65])) -#define MCF_INTC1_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000D66])) -#define MCF_INTC1_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000D67])) -#define MCF_INTC1_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000D68])) -#define MCF_INTC1_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000D69])) -#define MCF_INTC1_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6A])) -#define MCF_INTC1_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6B])) -#define MCF_INTC1_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6C])) -#define MCF_INTC1_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6D])) -#define MCF_INTC1_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6E])) -#define MCF_INTC1_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6F])) -#define MCF_INTC1_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000D70])) -#define MCF_INTC1_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000D71])) -#define MCF_INTC1_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000D72])) -#define MCF_INTC1_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000D73])) -#define MCF_INTC1_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000D74])) -#define MCF_INTC1_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000D75])) -#define MCF_INTC1_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000D76])) -#define MCF_INTC1_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000D77])) -#define MCF_INTC1_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000D78])) -#define MCF_INTC1_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000D79])) -#define MCF_INTC1_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7A])) -#define MCF_INTC1_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7B])) -#define MCF_INTC1_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7C])) -#define MCF_INTC1_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7D])) -#define MCF_INTC1_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7E])) -#define MCF_INTC1_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7F])) -#define MCF_INTC1_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000D40+((x)*0x001)])) -#define MCF_INTC1_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE0])) -#define MCF_INTC1_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4])) -#define MCF_INTC1_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE8])) -#define MCF_INTC1_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DEC])) -#define MCF_INTC1_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF0])) -#define MCF_INTC1_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF4])) -#define MCF_INTC1_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF8])) -#define MCF_INTC1_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DFC])) -#define MCF_INTC1_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4+((x)*0x004)])) - -/* Bit definitions and macros for MCF_INTC1_IPRH */ -#define MCF_INTC1_IPRH_INT32 (0x00000001) -#define MCF_INTC1_IPRH_INT33 (0x00000002) -#define MCF_INTC1_IPRH_INT34 (0x00000004) -#define MCF_INTC1_IPRH_INT35 (0x00000008) -#define MCF_INTC1_IPRH_INT36 (0x00000010) -#define MCF_INTC1_IPRH_INT37 (0x00000020) -#define MCF_INTC1_IPRH_INT38 (0x00000040) -#define MCF_INTC1_IPRH_INT39 (0x00000080) -#define MCF_INTC1_IPRH_INT40 (0x00000100) -#define MCF_INTC1_IPRH_INT41 (0x00000200) -#define MCF_INTC1_IPRH_INT42 (0x00000400) -#define MCF_INTC1_IPRH_INT43 (0x00000800) -#define MCF_INTC1_IPRH_INT44 (0x00001000) -#define MCF_INTC1_IPRH_INT45 (0x00002000) -#define MCF_INTC1_IPRH_INT46 (0x00004000) -#define MCF_INTC1_IPRH_INT47 (0x00008000) -#define MCF_INTC1_IPRH_INT48 (0x00010000) -#define MCF_INTC1_IPRH_INT49 (0x00020000) -#define MCF_INTC1_IPRH_INT50 (0x00040000) -#define MCF_INTC1_IPRH_INT51 (0x00080000) -#define MCF_INTC1_IPRH_INT52 (0x00100000) -#define MCF_INTC1_IPRH_INT53 (0x00200000) -#define MCF_INTC1_IPRH_INT54 (0x00400000) -#define MCF_INTC1_IPRH_INT55 (0x00800000) -#define MCF_INTC1_IPRH_INT56 (0x01000000) -#define MCF_INTC1_IPRH_INT57 (0x02000000) -#define MCF_INTC1_IPRH_INT58 (0x04000000) -#define MCF_INTC1_IPRH_INT59 (0x08000000) -#define MCF_INTC1_IPRH_INT60 (0x10000000) -#define MCF_INTC1_IPRH_INT61 (0x20000000) -#define MCF_INTC1_IPRH_INT62 (0x40000000) -#define MCF_INTC1_IPRH_INT63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_IPRL */ -#define MCF_INTC1_IPRL_INT1 (0x00000002) -#define MCF_INTC1_IPRL_INT2 (0x00000004) -#define MCF_INTC1_IPRL_INT3 (0x00000008) -#define MCF_INTC1_IPRL_INT4 (0x00000010) -#define MCF_INTC1_IPRL_INT5 (0x00000020) -#define MCF_INTC1_IPRL_INT6 (0x00000040) -#define MCF_INTC1_IPRL_INT7 (0x00000080) -#define MCF_INTC1_IPRL_INT8 (0x00000100) -#define MCF_INTC1_IPRL_INT9 (0x00000200) -#define MCF_INTC1_IPRL_INT10 (0x00000400) -#define MCF_INTC1_IPRL_INT11 (0x00000800) -#define MCF_INTC1_IPRL_INT12 (0x00001000) -#define MCF_INTC1_IPRL_INT13 (0x00002000) -#define MCF_INTC1_IPRL_INT14 (0x00004000) -#define MCF_INTC1_IPRL_INT15 (0x00008000) -#define MCF_INTC1_IPRL_INT16 (0x00010000) -#define MCF_INTC1_IPRL_INT17 (0x00020000) -#define MCF_INTC1_IPRL_INT18 (0x00040000) -#define MCF_INTC1_IPRL_INT19 (0x00080000) -#define MCF_INTC1_IPRL_INT20 (0x00100000) -#define MCF_INTC1_IPRL_INT21 (0x00200000) -#define MCF_INTC1_IPRL_INT22 (0x00400000) -#define MCF_INTC1_IPRL_INT23 (0x00800000) -#define MCF_INTC1_IPRL_INT24 (0x01000000) -#define MCF_INTC1_IPRL_INT25 (0x02000000) -#define MCF_INTC1_IPRL_INT26 (0x04000000) -#define MCF_INTC1_IPRL_INT27 (0x08000000) -#define MCF_INTC1_IPRL_INT28 (0x10000000) -#define MCF_INTC1_IPRL_INT29 (0x20000000) -#define MCF_INTC1_IPRL_INT30 (0x40000000) -#define MCF_INTC1_IPRL_INT31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_IMRH */ -#define MCF_INTC1_IMRH_INT_MASK32 (0x00000001) -#define MCF_INTC1_IMRH_INT_MASK33 (0x00000002) -#define MCF_INTC1_IMRH_INT_MASK34 (0x00000004) -#define MCF_INTC1_IMRH_INT_MASK35 (0x00000008) -#define MCF_INTC1_IMRH_INT_MASK36 (0x00000010) -#define MCF_INTC1_IMRH_INT_MASK37 (0x00000020) -#define MCF_INTC1_IMRH_INT_MASK38 (0x00000040) -#define MCF_INTC1_IMRH_INT_MASK39 (0x00000080) -#define MCF_INTC1_IMRH_INT_MASK40 (0x00000100) -#define MCF_INTC1_IMRH_INT_MASK41 (0x00000200) -#define MCF_INTC1_IMRH_INT_MASK42 (0x00000400) -#define MCF_INTC1_IMRH_INT_MASK43 (0x00000800) -#define MCF_INTC1_IMRH_INT_MASK44 (0x00001000) -#define MCF_INTC1_IMRH_INT_MASK45 (0x00002000) -#define MCF_INTC1_IMRH_INT_MASK46 (0x00004000) -#define MCF_INTC1_IMRH_INT_MASK47 (0x00008000) -#define MCF_INTC1_IMRH_INT_MASK48 (0x00010000) -#define MCF_INTC1_IMRH_INT_MASK49 (0x00020000) -#define MCF_INTC1_IMRH_INT_MASK50 (0x00040000) -#define MCF_INTC1_IMRH_INT_MASK51 (0x00080000) -#define MCF_INTC1_IMRH_INT_MASK52 (0x00100000) -#define MCF_INTC1_IMRH_INT_MASK53 (0x00200000) -#define MCF_INTC1_IMRH_INT_MASK54 (0x00400000) -#define MCF_INTC1_IMRH_INT_MASK55 (0x00800000) -#define MCF_INTC1_IMRH_INT_MASK56 (0x01000000) -#define MCF_INTC1_IMRH_INT_MASK57 (0x02000000) -#define MCF_INTC1_IMRH_INT_MASK58 (0x04000000) -#define MCF_INTC1_IMRH_INT_MASK59 (0x08000000) -#define MCF_INTC1_IMRH_INT_MASK60 (0x10000000) -#define MCF_INTC1_IMRH_INT_MASK61 (0x20000000) -#define MCF_INTC1_IMRH_INT_MASK62 (0x40000000) -#define MCF_INTC1_IMRH_INT_MASK63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_IMRL */ -#define MCF_INTC1_IMRL_MASKALL (0x00000001) -#define MCF_INTC1_IMRL_INT_MASK1 (0x00000002) -#define MCF_INTC1_IMRL_INT_MASK2 (0x00000004) -#define MCF_INTC1_IMRL_INT_MASK3 (0x00000008) -#define MCF_INTC1_IMRL_INT_MASK4 (0x00000010) -#define MCF_INTC1_IMRL_INT_MASK5 (0x00000020) -#define MCF_INTC1_IMRL_INT_MASK6 (0x00000040) -#define MCF_INTC1_IMRL_INT_MASK7 (0x00000080) -#define MCF_INTC1_IMRL_INT_MASK8 (0x00000100) -#define MCF_INTC1_IMRL_INT_MASK9 (0x00000200) -#define MCF_INTC1_IMRL_INT_MASK10 (0x00000400) -#define MCF_INTC1_IMRL_INT_MASK11 (0x00000800) -#define MCF_INTC1_IMRL_INT_MASK12 (0x00001000) -#define MCF_INTC1_IMRL_INT_MASK13 (0x00002000) -#define MCF_INTC1_IMRL_INT_MASK14 (0x00004000) -#define MCF_INTC1_IMRL_INT_MASK15 (0x00008000) -#define MCF_INTC1_IMRL_INT_MASK16 (0x00010000) -#define MCF_INTC1_IMRL_INT_MASK17 (0x00020000) -#define MCF_INTC1_IMRL_INT_MASK18 (0x00040000) -#define MCF_INTC1_IMRL_INT_MASK19 (0x00080000) -#define MCF_INTC1_IMRL_INT_MASK20 (0x00100000) -#define MCF_INTC1_IMRL_INT_MASK21 (0x00200000) -#define MCF_INTC1_IMRL_INT_MASK22 (0x00400000) -#define MCF_INTC1_IMRL_INT_MASK23 (0x00800000) -#define MCF_INTC1_IMRL_INT_MASK24 (0x01000000) -#define MCF_INTC1_IMRL_INT_MASK25 (0x02000000) -#define MCF_INTC1_IMRL_INT_MASK26 (0x04000000) -#define MCF_INTC1_IMRL_INT_MASK27 (0x08000000) -#define MCF_INTC1_IMRL_INT_MASK28 (0x10000000) -#define MCF_INTC1_IMRL_INT_MASK29 (0x20000000) -#define MCF_INTC1_IMRL_INT_MASK30 (0x40000000) -#define MCF_INTC1_IMRL_INT_MASK31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_INTFRCH */ -#define MCF_INTC1_INTFRCH_INTFRC32 (0x00000001) -#define MCF_INTC1_INTFRCH_INTFRC33 (0x00000002) -#define MCF_INTC1_INTFRCH_INTFRC34 (0x00000004) -#define MCF_INTC1_INTFRCH_INTFRC35 (0x00000008) -#define MCF_INTC1_INTFRCH_INTFRC36 (0x00000010) -#define MCF_INTC1_INTFRCH_INTFRC37 (0x00000020) -#define MCF_INTC1_INTFRCH_INTFRC38 (0x00000040) -#define MCF_INTC1_INTFRCH_INTFRC39 (0x00000080) -#define MCF_INTC1_INTFRCH_INTFRC40 (0x00000100) -#define MCF_INTC1_INTFRCH_INTFRC41 (0x00000200) -#define MCF_INTC1_INTFRCH_INTFRC42 (0x00000400) -#define MCF_INTC1_INTFRCH_INTFRC43 (0x00000800) -#define MCF_INTC1_INTFRCH_INTFRC44 (0x00001000) -#define MCF_INTC1_INTFRCH_INTFRC45 (0x00002000) -#define MCF_INTC1_INTFRCH_INTFRC46 (0x00004000) -#define MCF_INTC1_INTFRCH_INTFRC47 (0x00008000) -#define MCF_INTC1_INTFRCH_INTFRC48 (0x00010000) -#define MCF_INTC1_INTFRCH_INTFRC49 (0x00020000) -#define MCF_INTC1_INTFRCH_INTFRC50 (0x00040000) -#define MCF_INTC1_INTFRCH_INTFRC51 (0x00080000) -#define MCF_INTC1_INTFRCH_INTFRC52 (0x00100000) -#define MCF_INTC1_INTFRCH_INTFRC53 (0x00200000) -#define MCF_INTC1_INTFRCH_INTFRC54 (0x00400000) -#define MCF_INTC1_INTFRCH_INTFRC55 (0x00800000) -#define MCF_INTC1_INTFRCH_INTFRC56 (0x01000000) -#define MCF_INTC1_INTFRCH_INTFRC57 (0x02000000) -#define MCF_INTC1_INTFRCH_INTFRC58 (0x04000000) -#define MCF_INTC1_INTFRCH_INTFRC59 (0x08000000) -#define MCF_INTC1_INTFRCH_INTFRC60 (0x10000000) -#define MCF_INTC1_INTFRCH_INTFRC61 (0x20000000) -#define MCF_INTC1_INTFRCH_INTFRC62 (0x40000000) -#define MCF_INTC1_INTFRCH_INTFRC63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_INTFRCL */ -#define MCF_INTC1_INTFRCL_INTFRC1 (0x00000002) -#define MCF_INTC1_INTFRCL_INTFRC2 (0x00000004) -#define MCF_INTC1_INTFRCL_INTFRC3 (0x00000008) -#define MCF_INTC1_INTFRCL_INTFRC4 (0x00000010) -#define MCF_INTC1_INTFRCL_INTFRC5 (0x00000020) -#define MCF_INTC1_INTFRCL_INT6 (0x00000040) -#define MCF_INTC1_INTFRCL_INT7 (0x00000080) -#define MCF_INTC1_INTFRCL_INT8 (0x00000100) -#define MCF_INTC1_INTFRCL_INT9 (0x00000200) -#define MCF_INTC1_INTFRCL_INT10 (0x00000400) -#define MCF_INTC1_INTFRCL_INTFRC11 (0x00000800) -#define MCF_INTC1_INTFRCL_INTFRC12 (0x00001000) -#define MCF_INTC1_INTFRCL_INTFRC13 (0x00002000) -#define MCF_INTC1_INTFRCL_INTFRC14 (0x00004000) -#define MCF_INTC1_INTFRCL_INT15 (0x00008000) -#define MCF_INTC1_INTFRCL_INTFRC16 (0x00010000) -#define MCF_INTC1_INTFRCL_INTFRC17 (0x00020000) -#define MCF_INTC1_INTFRCL_INTFRC18 (0x00040000) -#define MCF_INTC1_INTFRCL_INTFRC19 (0x00080000) -#define MCF_INTC1_INTFRCL_INTFRC20 (0x00100000) -#define MCF_INTC1_INTFRCL_INTFRC21 (0x00200000) -#define MCF_INTC1_INTFRCL_INTFRC22 (0x00400000) -#define MCF_INTC1_INTFRCL_INTFRC23 (0x00800000) -#define MCF_INTC1_INTFRCL_INTFRC24 (0x01000000) -#define MCF_INTC1_INTFRCL_INTFRC25 (0x02000000) -#define MCF_INTC1_INTFRCL_INTFRC26 (0x04000000) -#define MCF_INTC1_INTFRCL_INTFRC27 (0x08000000) -#define MCF_INTC1_INTFRCL_INTFRC28 (0x10000000) -#define MCF_INTC1_INTFRCL_INTFRC29 (0x20000000) -#define MCF_INTC1_INTFRCL_INTFRC30 (0x40000000) -#define MCF_INTC1_INTFRCL_INTFRC31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_IRLR */ -#define MCF_INTC1_IRLR_IRQ(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_INTC1_IACKLPR */ -#define MCF_INTC1_IACKLPR_PRI(x) (((x)&0x0F)<<0) -#define MCF_INTC1_IACKLPR_LEVEL(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF_INTC1_ICRn */ -#define MCF_INTC1_ICRn_IP(x) (((x)&0x07)<<0) -#define MCF_INTC1_ICRn_IL(x) (((x)&0x07)<<3) - -/********************************************************************/ - -#endif /* __MCF523X_INTC1_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_mdha.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_mdha.h deleted file mode 100644 index 55e895859..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_mdha.h +++ /dev/null @@ -1,105 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_MDHA_H__ -#define __MCF523X_MDHA_H__ - -/********************************************************************* -* -* Message Digest Hardware Accelerator (MDHA) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_MDHA_MDMR (*(vuint32*)(void*)(&__IPSBAR[0x190000])) -#define MCF_MDHA_MDCR (*(vuint32*)(void*)(&__IPSBAR[0x190004])) -#define MCF_MDHA_MDCMR (*(vuint32*)(void*)(&__IPSBAR[0x190008])) -#define MCF_MDHA_MDSR (*(vuint32*)(void*)(&__IPSBAR[0x19000C])) -#define MCF_MDHA_MDISR (*(vuint32*)(void*)(&__IPSBAR[0x190010])) -#define MCF_MDHA_MDIMR (*(vuint32*)(void*)(&__IPSBAR[0x190014])) -#define MCF_MDHA_MDDSR (*(vuint32*)(void*)(&__IPSBAR[0x19001C])) -#define MCF_MDHA_MDIN (*(vuint32*)(void*)(&__IPSBAR[0x190020])) -#define MCF_MDHA_MDA0 (*(vuint32*)(void*)(&__IPSBAR[0x190030])) -#define MCF_MDHA_MDB0 (*(vuint32*)(void*)(&__IPSBAR[0x190034])) -#define MCF_MDHA_MDC0 (*(vuint32*)(void*)(&__IPSBAR[0x190038])) -#define MCF_MDHA_MDD0 (*(vuint32*)(void*)(&__IPSBAR[0x19003C])) -#define MCF_MDHA_MDE0 (*(vuint32*)(void*)(&__IPSBAR[0x190040])) -#define MCF_MDHA_MDMDS (*(vuint32*)(void*)(&__IPSBAR[0x190044])) -#define MCF_MDHA_MDA1 (*(vuint32*)(void*)(&__IPSBAR[0x190070])) -#define MCF_MDHA_MDB1 (*(vuint32*)(void*)(&__IPSBAR[0x190074])) -#define MCF_MDHA_MDC1 (*(vuint32*)(void*)(&__IPSBAR[0x190078])) -#define MCF_MDHA_MDD1 (*(vuint32*)(void*)(&__IPSBAR[0x19007C])) -#define MCF_MDHA_MDE1 (*(vuint32*)(void*)(&__IPSBAR[0x190080])) - -/* Bit definitions and macros for MCF_MDHA_MDMR */ -#define MCF_MDHA_MDMR_ALG (0x00000001) -#define MCF_MDHA_MDMR_PDATA (0x00000004) -#define MCF_MDHA_MDMR_MAC(x) (((x)&0x00000003)<<3) -#define MCF_MDHA_MDMR_INIT (0x00000020) -#define MCF_MDHA_MDMR_IPAD (0x00000040) -#define MCF_MDHA_MDMR_OPAD (0x00000080) -#define MCF_MDHA_MDMR_SWAP (0x00000100) -#define MCF_MDHA_MDMR_MACFULL (0x00000200) -#define MCF_MDHA_MDMR_SSL (0x00000400) - -/* Bit definitions and macros for MCF_MDHA_MDCR */ -#define MCF_MDHA_MDCR_IE (0x00000001) - -/* Bit definitions and macros for MCF_MDHA_MDCMR */ -#define MCF_MDHA_MDCMR_IE (0x00000001) -#define MCF_MDHA_MDCMR_RI (0x00000002) -#define MCF_MDHA_MDCMR_CI (0x00000004) -#define MCF_MDHA_MDCMR_GO (0x00000008) - -/* Bit definitions and macros for MCF_MDHA_MDSR */ -#define MCF_MDHA_MDSR_INT (0x00000001) -#define MCF_MDHA_MDSR_DONE (0x00000002) -#define MCF_MDHA_MDSR_ERR (0x00000004) -#define MCF_MDHA_MDSR_RD (0x00000008) -#define MCF_MDHA_MDSR_BUSY (0x00000010) -#define MCF_MDHA_MDSR_END (0x00000020) -#define MCF_MDHA_MDSR_HSH (0x00000040) -#define MCF_MDHA_MDSR_GNW (0x00000080) -#define MCF_MDHA_MDSR_FS(x) (((x)&0x00000007)<<8) -#define MCF_MDHA_MDSR_APD(x) (((x)&0x00000007)<<13) -#define MCF_MDHA_MDSR_IFL(x) (((x)&0x000000FF)<<16) - -/* Bit definitions and macros for MCF_MDHA_MDIR */ -#define MCF_MDHA_MDIR_IFO (0x00000001) -#define MCF_MDHA_MDIR_NON (0x00000004) -#define MCF_MDHA_MDIR_IME (0x00000010) -#define MCF_MDHA_MDIR_IDS (0x00000020) -#define MCF_MDHA_MDIR_RMDP (0x00000080) -#define MCF_MDHA_MDIR_ERE (0x00000100) -#define MCF_MDHA_MDIR_GTDS (0x00000200) - -/* Bit definitions and macros for MCF_MDHA_MDIMR */ -#define MCF_MDHA_MDIMR_IFO (0x00000001) -#define MCF_MDHA_MDIMR_NON (0x00000004) -#define MCF_MDHA_MDIMR_IME (0x00000010) -#define MCF_MDHA_MDIMR_IDS (0x00000020) -#define MCF_MDHA_MDIMR_RMDP (0x00000080) -#define MCF_MDHA_MDIMR_ERE (0x00000100) -#define MCF_MDHA_MDIMR_GTDS (0x00000200) - -/* Bit definitions and macros for MCF_MDHA_MDDSR */ -#define MCF_MDHA_MDDSR_DATASIZE(x) (((x)&0x1FFFFFFF)<<0) - -/********************************************************************/ - -#endif /* __MCF523X_MDHA_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_pit.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_pit.h deleted file mode 100644 index 9eda0f239..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_pit.h +++ /dev/null @@ -1,93 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_PIT_H__ -#define __MCF523X_PIT_H__ - -/********************************************************************* -* -* Programmable Interrupt Timer Modules (PIT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PIT_PCSR0 (*(vuint16*)(void*)(&__IPSBAR[0x150000])) -#define MCF_PIT_PMR0 (*(vuint16*)(void*)(&__IPSBAR[0x150002])) -#define MCF_PIT_PCNTR0 (*(vuint16*)(void*)(&__IPSBAR[0x150004])) -#define MCF_PIT_PCSR1 (*(vuint16*)(void*)(&__IPSBAR[0x160000])) -#define MCF_PIT_PMR1 (*(vuint16*)(void*)(&__IPSBAR[0x160002])) -#define MCF_PIT_PCNTR1 (*(vuint16*)(void*)(&__IPSBAR[0x160004])) -#define MCF_PIT_PCSR2 (*(vuint16*)(void*)(&__IPSBAR[0x170000])) -#define MCF_PIT_PMR2 (*(vuint16*)(void*)(&__IPSBAR[0x170002])) -#define MCF_PIT_PCNTR2 (*(vuint16*)(void*)(&__IPSBAR[0x170004])) -#define MCF_PIT_PCSR3 (*(vuint16*)(void*)(&__IPSBAR[0x180000])) -#define MCF_PIT_PMR3 (*(vuint16*)(void*)(&__IPSBAR[0x180002])) -#define MCF_PIT_PCNTR3 (*(vuint16*)(void*)(&__IPSBAR[0x180004])) -#define MCF_PIT_PCSR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150000+((x)*0x10000)])) -#define MCF_PIT_PMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150002+((x)*0x10000)])) -#define MCF_PIT_PCNTR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150004+((x)*0x10000)])) - -/* Bit definitions and macros for MCF_PIT_PCSR */ -#define MCF_PIT_PCSR_EN (0x0001) -#define MCF_PIT_PCSR_RLD (0x0002) -#define MCF_PIT_PCSR_PIF (0x0004) -#define MCF_PIT_PCSR_PIE (0x0008) -#define MCF_PIT_PCSR_OVW (0x0010) -#define MCF_PIT_PCSR_HALTED (0x0020) -#define MCF_PIT_PCSR_DOZE (0x0040) -#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) - -/* Bit definitions and macros for MCF_PIT_PMR */ -#define MCF_PIT_PMR_PM0 (0x0001) -#define MCF_PIT_PMR_PM1 (0x0002) -#define MCF_PIT_PMR_PM2 (0x0004) -#define MCF_PIT_PMR_PM3 (0x0008) -#define MCF_PIT_PMR_PM4 (0x0010) -#define MCF_PIT_PMR_PM5 (0x0020) -#define MCF_PIT_PMR_PM6 (0x0040) -#define MCF_PIT_PMR_PM7 (0x0080) -#define MCF_PIT_PMR_PM8 (0x0100) -#define MCF_PIT_PMR_PM9 (0x0200) -#define MCF_PIT_PMR_PM10 (0x0400) -#define MCF_PIT_PMR_PM11 (0x0800) -#define MCF_PIT_PMR_PM12 (0x1000) -#define MCF_PIT_PMR_PM13 (0x2000) -#define MCF_PIT_PMR_PM14 (0x4000) -#define MCF_PIT_PMR_PM15 (0x8000) - -/* Bit definitions and macros for MCF_PIT_PCNTR */ -#define MCF_PIT_PCNTR_PC0 (0x0001) -#define MCF_PIT_PCNTR_PC1 (0x0002) -#define MCF_PIT_PCNTR_PC2 (0x0004) -#define MCF_PIT_PCNTR_PC3 (0x0008) -#define MCF_PIT_PCNTR_PC4 (0x0010) -#define MCF_PIT_PCNTR_PC5 (0x0020) -#define MCF_PIT_PCNTR_PC6 (0x0040) -#define MCF_PIT_PCNTR_PC7 (0x0080) -#define MCF_PIT_PCNTR_PC8 (0x0100) -#define MCF_PIT_PCNTR_PC9 (0x0200) -#define MCF_PIT_PCNTR_PC10 (0x0400) -#define MCF_PIT_PCNTR_PC11 (0x0800) -#define MCF_PIT_PCNTR_PC12 (0x1000) -#define MCF_PIT_PCNTR_PC13 (0x2000) -#define MCF_PIT_PCNTR_PC14 (0x4000) -#define MCF_PIT_PCNTR_PC15 (0x8000) - -/********************************************************************/ - -#endif /* __MCF523X_PIT_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_qspi.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_qspi.h deleted file mode 100644 index 02620f384..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_qspi.h +++ /dev/null @@ -1,73 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_QSPI_H__ -#define __MCF523X_QSPI_H__ - -/********************************************************************* -* -* Queued Serial Peripheral Interface (QSPI) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_QSPI_QMR (*(vuint16*)(void*)(&__IPSBAR[0x000340])) -#define MCF_QSPI_QDLYR (*(vuint16*)(void*)(&__IPSBAR[0x000344])) -#define MCF_QSPI_QWR (*(vuint16*)(void*)(&__IPSBAR[0x000348])) -#define MCF_QSPI_QIR (*(vuint16*)(void*)(&__IPSBAR[0x00034C])) -#define MCF_QSPI_QAR (*(vuint16*)(void*)(&__IPSBAR[0x000350])) -#define MCF_QSPI_QDR (*(vuint16*)(void*)(&__IPSBAR[0x000354])) - -/* Bit definitions and macros for MCF_QSPI_QMR */ -#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) -#define MCF_QSPI_QMR_CPHA (0x0100) -#define MCF_QSPI_QMR_CPOL (0x0200) -#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) -#define MCF_QSPI_QMR_DOHIE (0x4000) -#define MCF_QSPI_QMR_MSTR (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QDLYR */ -#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) -#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) -#define MCF_QSPI_QDLYR_SPE (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QWR */ -#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) -#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) -#define MCF_QSPI_QWR_CSIV (0x1000) -#define MCF_QSPI_QWR_WRTO (0x2000) -#define MCF_QSPI_QWR_WREN (0x4000) -#define MCF_QSPI_QWR_HALT (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QIR */ -#define MCF_QSPI_QIR_SPIF (0x0001) -#define MCF_QSPI_QIR_ABRT (0x0004) -#define MCF_QSPI_QIR_WCEF (0x0008) -#define MCF_QSPI_QIR_SPIFE (0x0100) -#define MCF_QSPI_QIR_ABRTE (0x0400) -#define MCF_QSPI_QIR_WCEFE (0x0800) -#define MCF_QSPI_QIR_ABRTL (0x1000) -#define MCF_QSPI_QIR_ABRTB (0x4000) -#define MCF_QSPI_QIR_WCEFB (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QAR */ -#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) - -/********************************************************************/ - -#endif /* __MCF523X_QSPI_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_rcm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_rcm.h deleted file mode 100644 index 35a3c5879..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_rcm.h +++ /dev/null @@ -1,46 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_RCM_H__ -#define __MCF523X_RCM_H__ - -/********************************************************************* -* -* Reset Configuration Module (RCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_RCM_RCR (*(vuint8 *)(void*)(&__IPSBAR[0x110000])) -#define MCF_RCM_RSR (*(vuint8 *)(void*)(&__IPSBAR[0x110001])) - -/* Bit definitions and macros for MCF_RCM_RCR */ -#define MCF_RCM_RCR_FRCRSTOUT (0x40) -#define MCF_RCM_RCR_SOFTRST (0x80) - -/* Bit definitions and macros for MCF_RCM_RSR */ -#define MCF_RCM_RSR_LOL (0x01) -#define MCF_RCM_RSR_LOC (0x02) -#define MCF_RCM_RSR_EXT (0x04) -#define MCF_RCM_RSR_POR (0x08) -#define MCF_RCM_RSR_WDR (0x10) -#define MCF_RCM_RSR_SOFT (0x20) - -/********************************************************************/ - -#endif /* __MCF523X_RCM_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_rng.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_rng.h deleted file mode 100644 index ca74a1a0c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_rng.h +++ /dev/null @@ -1,51 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - - -#ifndef __MCF523X_RNG_H__ -#define __MCF523X_RNG_H__ - -/********************************************************************* -* -* Random Number Generator (RNG) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_RNG_RNGCR (*(vuint32*)(void*)(&__IPSBAR[0x1A0000])) -#define MCF_RNG_RNGSR (*(vuint32*)(void*)(&__IPSBAR[0x1A0004])) -#define MCF_RNG_RNGER (*(vuint32*)(void*)(&__IPSBAR[0x1A0008])) -#define MCF_RNG_RNGOUT (*(vuint32*)(void*)(&__IPSBAR[0x1A000C])) - -/* Bit definitions and macros for MCF_RNG_RNGCR */ -#define MCF_RNG_RNGCR_GO (0x00000001) -#define MCF_RNG_RNGCR_HA (0x00000002) -#define MCF_RNG_RNGCR_IM (0x00000004) -#define MCF_RNG_RNGCR_CI (0x00000008) - -/* Bit definitions and macros for MCF_RNG_RNGSR */ -#define MCF_RNG_RNGSR_SV (0x00000001) -#define MCF_RNG_RNGSR_LRS (0x00000002) -#define MCF_RNG_RNGSR_FUF (0x00000004) -#define MCF_RNG_RNGSR_EI (0x00000008) -#define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8) -#define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16) - -/********************************************************************/ - -#endif /* __MCF523X_RNG_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_scm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_scm.h deleted file mode 100644 index fc21b4806..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_scm.h +++ /dev/null @@ -1,155 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - - -#ifndef __MCF523X_SCM_H__ -#define __MCF523X_SCM_H__ - -/********************************************************************* -* -* System Control Module (SCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SCM_IPSBAR (*(vuint32*)(void*)(&__IPSBAR[0x000000])) -#define MCF_SCM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x000008])) -#define MCF_SCM_CRSR (*(vuint8 *)(void*)(&__IPSBAR[0x000010])) -#define MCF_SCM_CWCR (*(vuint8 *)(void*)(&__IPSBAR[0x000011])) -#define MCF_SCM_LPICR (*(vuint8 *)(void*)(&__IPSBAR[0x000012])) -#define MCF_SCM_CWSR (*(vuint8 *)(void*)(&__IPSBAR[0x000013])) -#define MCF_SCM_DMAREQC (*(vuint32*)(void*)(&__IPSBAR[0x000014])) -#define MCF_SCM_MPARK (*(vuint32*)(void*)(&__IPSBAR[0x00001C])) -#define MCF_SCM_MPR (*(vuint8 *)(void*)(&__IPSBAR[0x000020])) -#define MCF_SCM_PACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000024])) -#define MCF_SCM_PACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000025])) -#define MCF_SCM_PACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000026])) -#define MCF_SCM_PACR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000027])) -#define MCF_SCM_PACR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000028])) -#define MCF_SCM_PACR5 (*(vuint8 *)(void*)(&__IPSBAR[0x00002A])) -#define MCF_SCM_PACR6 (*(vuint8 *)(void*)(&__IPSBAR[0x00002B])) -#define MCF_SCM_PACR7 (*(vuint8 *)(void*)(&__IPSBAR[0x00002C])) -#define MCF_SCM_PACR8 (*(vuint8 *)(void*)(&__IPSBAR[0x00002E])) -#define MCF_SCM_GPACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000030])) - -/* Bit definitions and macros for MCF_SCM_IPSBAR */ -#define MCF_SCM_IPSBAR_V (0x00000001) -#define MCF_SCM_IPSBAR_BA(x) (((x)&0x00000003)<<30) - -/* Bit definitions and macros for MCF_SCM_RAMBAR */ -#define MCF_SCM_RAMBAR_BDE (0x00000200) -#define MCF_SCM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_SCM_CRSR */ -#define MCF_SCM_CRSR_CWDR (0x20) -#define MCF_SCM_CRSR_EXT (0x80) - -/* Bit definitions and macros for MCF_SCM_CWCR */ -#define MCF_SCM_CWCR_CWTIC (0x01) -#define MCF_SCM_CWCR_CWTAVAL (0x02) -#define MCF_SCM_CWCR_CWTA (0x04) -#define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3) -#define MCF_SCM_CWCR_CWRI (0x40) -#define MCF_SCM_CWCR_CWE (0x80) - -/* Bit definitions and macros for MCF_SCM_LPICR */ -#define MCF_SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4) -#define MCF_SCM_LPICR_ENBSTOP (0x80) - -/* Bit definitions and macros for MCF_SCM_DMAREQC */ -#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0) -#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4) -#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8) -#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12) - -/* Bit definitions and macros for MCF_SCM_MPARK */ -#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8) -#define MCF_SCM_MPARK_PRKLAST (0x00001000) -#define MCF_SCM_MPARK_TIMEOUT (0x00002000) -#define MCF_SCM_MPARK_FIXED (0x00004000) -#define MCF_SCM_MPARK_M1_PRTY(x) (((x)&0x00000003)<<16) -#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x00000003)<<18) -#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x00000003)<<20) -#define MCF_SCM_MPARK_M3_PRTY(x) (((x)&0x00000003)<<22) -#define MCF_SCM_MPARK_BCR24BIT (0x01000000) -#define MCF_SCM_MPARK_M2_P_EN (0x02000000) - -/* Bit definitions and macros for MCF_SCM_MPR */ -#define MCF_SCM_MPR_MPR(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF_SCM_PACR0 */ -#define MCF_SCM_PACR0_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR0_LOCK0 (0x08) -#define MCF_SCM_PACR0_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR0_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR1 */ -#define MCF_SCM_PACR1_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR1_LOCK0 (0x08) -#define MCF_SCM_PACR1_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR1_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR2 */ -#define MCF_SCM_PACR2_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR2_LOCK0 (0x08) -#define MCF_SCM_PACR2_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR2_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR3 */ -#define MCF_SCM_PACR3_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR3_LOCK0 (0x08) -#define MCF_SCM_PACR3_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR3_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR4 */ -#define MCF_SCM_PACR4_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR4_LOCK0 (0x08) -#define MCF_SCM_PACR4_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR4_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR5 */ -#define MCF_SCM_PACR5_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR5_LOCK0 (0x08) -#define MCF_SCM_PACR5_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR5_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR6 */ -#define MCF_SCM_PACR6_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR6_LOCK0 (0x08) -#define MCF_SCM_PACR6_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR6_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR7 */ -#define MCF_SCM_PACR7_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR7_LOCK0 (0x08) -#define MCF_SCM_PACR7_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR7_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR8 */ -#define MCF_SCM_PACR8_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR8_LOCK0 (0x08) -#define MCF_SCM_PACR8_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR8_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_GPACR0 */ -#define MCF_SCM_GPACR0_ACCESS_CTRL(x) (((x)&0x0F)<<0) -#define MCF_SCM_GPACR0_LOCK (0x80) - -/********************************************************************/ - -#endif /* __MCF523X_SCM_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_sdramc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_sdramc.h deleted file mode 100644 index 2f4d62991..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_sdramc.h +++ /dev/null @@ -1,98 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_SDRAMC_H__ -#define __MCF523X_SDRAMC_H__ - -/********************************************************************* -* -* SDRAM Controller (SDRAMC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SDRAMC_DCR (*(vuint16*)(void*)(&__IPSBAR[0x000040])) -#define MCF_SDRAMC_DACR0 (*(vuint32*)(void*)(&__IPSBAR[0x000048])) -#define MCF_SDRAMC_DMR0 (*(vuint32*)(void*)(&__IPSBAR[0x00004C])) -#define MCF_SDRAMC_DACR1 (*(vuint32*)(void*)(&__IPSBAR[0x000050])) -#define MCF_SDRAMC_DMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000054])) - -/* Bit definitions and macros for MCF_SDRAMC_DCR */ -#define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0) -#define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9) -#define MCF_SDRAMC_DCR_IS (0x0800) -#define MCF_SDRAMC_DCR_COC (0x1000) -#define MCF_SDRAMC_DCR_NAM (0x2000) - -/* Bit definitions and macros for MCF_SDRAMC_DACR0 */ -#define MCF_SDRAMC_DACR0_IP (0x00000008) -#define MCF_SDRAMC_DACR0_PS(x) (((x)&0x00000003)<<4) -#define MCF_SDRAMC_DACR0_MRS (0x00000040) -#define MCF_SDRAMC_DACR0_CBM(x) (((x)&0x00000007)<<8) -#define MCF_SDRAMC_DACR0_CASL(x) (((x)&0x00000003)<<12) -#define MCF_SDRAMC_DACR0_RE (0x00008000) -#define MCF_SDRAMC_DACR0_BA(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF_SDRAMC_DMR0 */ -#define MCF_SDRAMC_DMR0_V (0x00000001) -#define MCF_SDRAMC_DMR0_WP (0x00000100) -#define MCF_SDRAMC_DMR0_BAM(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF_SDRAMC_DACR1 */ -#define MCF_SDRAMC_DACR1_IP (0x00000008) -#define MCF_SDRAMC_DACR1_PS(x) (((x)&0x00000003)<<4) -#define MCF_SDRAMC_DACR1_MRS (0x00000040) -#define MCF_SDRAMC_DACR1_CBM(x) (((x)&0x00000007)<<8) -#define MCF_SDRAMC_DACR1_CASL(x) (((x)&0x00000003)<<12) -#define MCF_SDRAMC_DACR1_RE (0x00008000) -#define MCF_SDRAMC_DACR1_BA(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF_SDRAMC_DMR1 */ -#define MCF_SDRAMC_DMR1_V (0x00000001) -#define MCF_SDRAMC_DMR1_WP (0x00000100) -#define MCF_SDRAMC_DMR1_BAM(x) (((x)&0x00003FFF)<<18) - -/********************************************************************/ - -#define MCF_SDRAMC_DMR_BAM_4G (0xFFFC0000) -#define MCF_SDRAMC_DMR_BAM_2G (0x7FFC0000) -#define MCF_SDRAMC_DMR_BAM_1G (0x3FFC0000) -#define MCF_SDRAMC_DMR_BAM_1024M (0x3FFC0000) -#define MCF_SDRAMC_DMR_BAM_512M (0x1FFC0000) -#define MCF_SDRAMC_DMR_BAM_256M (0x0FFC0000) -#define MCF_SDRAMC_DMR_BAM_128M (0x07FC0000) -#define MCF_SDRAMC_DMR_BAM_64M (0x03FC0000) -#define MCF_SDRAMC_DMR_BAM_32M (0x01FC0000) -#define MCF_SDRAMC_DMR_BAM_16M (0x00FC0000) -#define MCF_SDRAMC_DMR_BAM_8M (0x007C0000) -#define MCF_SDRAMC_DMR_BAM_4M (0x003C0000) -#define MCF_SDRAMC_DMR_BAM_2M (0x001C0000) -#define MCF_SDRAMC_DMR_BAM_1M (0x000C0000) -#define MCF_SDRAMC_DMR_BAM_1024K (0x000C0000) -#define MCF_SDRAMC_DMR_BAM_512K (0x00040000) -#define MCF_SDRAMC_DMR_BAM_256K (0x00000000) -#define MCF_SDRAMC_DMR_WP (0x00000100) -#define MCF_SDRAMC_DMR_CI (0x00000040) -#define MCF_SDRAMC_DMR_AM (0x00000020) -#define MCF_SDRAMC_DMR_SC (0x00000010) -#define MCF_SDRAMC_DMR_SD (0x00000008) -#define MCF_SDRAMC_DMR_UC (0x00000004) -#define MCF_SDRAMC_DMR_UD (0x00000002) -#define MCF_SDRAMC_DMR_V (0x00000001) - -#endif /* __MCF523X_SDRAMC_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_skha.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_skha.h deleted file mode 100644 index 1ccd55c8a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_skha.h +++ /dev/null @@ -1,124 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_SKHA_H__ -#define __MCF523X_SKHA_H__ - -/********************************************************************* -* -* Symmetric Key Hardware Accelerator (SKHA) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SKHA_SKMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0000])) -#define MCF_SKHA_SKCR (*(vuint32*)(void*)(&__IPSBAR[0x1B0004])) -#define MCF_SKHA_SKCMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0008])) -#define MCF_SKHA_SKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B000C])) -#define MCF_SKHA_SKIR (*(vuint32*)(void*)(&__IPSBAR[0x1B0010])) -#define MCF_SKHA_SKIMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0014])) -#define MCF_SKHA_SKKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B0018])) -#define MCF_SKHA_SKDSR (*(vuint32*)(void*)(&__IPSBAR[0x1B001C])) -#define MCF_SKHA_SKIN (*(vuint32*)(void*)(&__IPSBAR[0x1B0020])) -#define MCF_SKHA_SKOUT (*(vuint32*)(void*)(&__IPSBAR[0x1B0024])) -#define MCF_SKHA_SKKDR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0030])) -#define MCF_SKHA_SKKDR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0034])) -#define MCF_SKHA_SKKDR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0038])) -#define MCF_SKHA_SKKDR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B003C])) -#define MCF_SKHA_SKKDR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0040])) -#define MCF_SKHA_SKKDR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0044])) -#define MCF_SKHA_SKKDRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0030+((x)*0x004)])) -#define MCF_SKHA_SKCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0070])) -#define MCF_SKHA_SKCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0074])) -#define MCF_SKHA_SKCR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0078])) -#define MCF_SKHA_SKCR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B007C])) -#define MCF_SKHA_SKCR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0080])) -#define MCF_SKHA_SKCR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0084])) -#define MCF_SKHA_SKCR6 (*(vuint32*)(void*)(&__IPSBAR[0x1B0088])) -#define MCF_SKHA_SKCR7 (*(vuint32*)(void*)(&__IPSBAR[0x1B008C])) -#define MCF_SKHA_SKCR8 (*(vuint32*)(void*)(&__IPSBAR[0x1B0090])) -#define MCF_SKHA_SKCR9 (*(vuint32*)(void*)(&__IPSBAR[0x1B0094])) -#define MCF_SKHA_SKCR10 (*(vuint32*)(void*)(&__IPSBAR[0x1B0098])) -#define MCF_SKHA_SKCR11 (*(vuint32*)(void*)(&__IPSBAR[0x1B009C])) -#define MCF_SKHA_SKCRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0070+((x)*0x004)])) - -/* Bit definitions and macros for MCF_SKHA_SKMR */ -#define MCF_SKHA_SKMR_ALG(x) (((x)&0x00000003)<<0) -#define MCF_SKHA_SKMR_DIR (0x00000004) -#define MCF_SKHA_SKMR_CM(x) (((x)&0x00000003)<<3) -#define MCF_SKHA_SKMR_DKP (0x00000100) -#define MCF_SKHA_SKMR_CTRM(x) (((x)&0x0000000F)<<9) -#define MCF_SKHA_SKMR_CM_ECB (0x00000000) -#define MCF_SKHA_SKMR_CM_CBC (0x00000008) -#define MCF_SKHA_SKMR_CM_CTR (0x00000018) -#define MCF_SKHA_SKMR_DIR_DEC (0x00000000) -#define MCF_SKHA_SKMR_DIR_ENC (0x00000004) -#define MCF_SKHA_SKMR_ALG_AES (0x00000000) -#define MCF_SKHA_SKMR_ALG_DES (0x00000001) -#define MCF_SKHA_SKMR_ALG_TDES (0x00000002) - -/* Bit definitions and macros for MCF_SKHA_SKCR */ -#define MCF_SKHA_SKCR_IE (0x00000001) - -/* Bit definitions and macros for MCF_SKHA_SKCMR */ -#define MCF_SKHA_SKCMR_SWR (0x00000001) -#define MCF_SKHA_SKCMR_RI (0x00000002) -#define MCF_SKHA_SKCMR_CI (0x00000004) -#define MCF_SKHA_SKCMR_GO (0x00000008) - -/* Bit definitions and macros for MCF_SKHA_SKSR */ -#define MCF_SKHA_SKSR_INT (0x00000001) -#define MCF_SKHA_SKSR_DONE (0x00000002) -#define MCF_SKHA_SKSR_ERR (0x00000004) -#define MCF_SKHA_SKSR_RD (0x00000008) -#define MCF_SKHA_SKSR_BUSY (0x00000010) -#define MCF_SKHA_SKSR_IFL(x) (((x)&0x000000FF)<<16) -#define MCF_SKHA_SKSR_OFL(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_SKHA_SKIR */ -#define MCF_SKHA_SKIR_IFO (0x00000001) -#define MCF_SKHA_SKIR_OFU (0x00000002) -#define MCF_SKHA_SKIR_NEIF (0x00000004) -#define MCF_SKHA_SKIR_NEOF (0x00000008) -#define MCF_SKHA_SKIR_IME (0x00000010) -#define MCF_SKHA_SKIR_DSE (0x00000020) -#define MCF_SKHA_SKIR_KSE (0x00000040) -#define MCF_SKHA_SKIR_RMDP (0x00000080) -#define MCF_SKHA_SKIR_ERE (0x00000100) -#define MCF_SKHA_SKIR_KPE (0x00000200) -#define MCF_SKHA_SKIR_KRE (0x00000400) - -/* Bit definitions and macros for MCF_SKHA_SKIMR */ -#define MCF_SKHA_SKIMR_IFO (0x00000001) -#define MCF_SKHA_SKIMR_OFU (0x00000002) -#define MCF_SKHA_SKIMR_NEIF (0x00000004) -#define MCF_SKHA_SKIMR_NEOF (0x00000008) -#define MCF_SKHA_SKIMR_IME (0x00000010) -#define MCF_SKHA_SKIMR_DSE (0x00000020) -#define MCF_SKHA_SKIMR_KSE (0x00000040) -#define MCF_SKHA_SKIMR_RMDP (0x00000080) -#define MCF_SKHA_SKIMR_ERE (0x00000100) -#define MCF_SKHA_SKIMR_KPE (0x00000200) -#define MCF_SKHA_SKIMR_KRE (0x00000400) - -/* Bit definitions and macros for MCF_SKHA_SKKSR */ -#define MCF_SKHA_SKKSR_KEYSIZE(x) (((x)&0x0000003F)<<0) - -/********************************************************************/ - -#endif /* __MCF523X_SKHA_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_sram.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_sram.h deleted file mode 100644 index 9668ad5c5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_sram.h +++ /dev/null @@ -1,46 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_SRAM_H__ -#define __MCF523X_SRAM_H__ - -/********************************************************************* -* -* 64KByte System SRAM (SRAM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SRAM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x20000000])) - -/* Bit definitions and macros for MCF_SRAM_RAMBAR */ -#define MCF_SRAM_RAMBAR_V (0x00000001) -#define MCF_SRAM_RAMBAR_UD (0x00000002) -#define MCF_SRAM_RAMBAR_UC (0x00000004) -#define MCF_SRAM_RAMBAR_SD (0x00000008) -#define MCF_SRAM_RAMBAR_SC (0x00000010) -#define MCF_SRAM_RAMBAR_C/I (0x00000020) -#define MCF_SRAM_RAMBAR_WP (0x00000100) -#define MCF_SRAM_RAMBAR_SPV (0x00000200) -#define MCF_SRAM_RAMBAR_PRI2 (0x00000400) -#define MCF_SRAM_RAMBAR_PRI1 (0x00000800) -#define MCF_SRAM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16) - -/********************************************************************/ - -#endif /* __MCF523X_SRAM_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_timer.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_timer.h deleted file mode 100644 index 839a1d6f6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_timer.h +++ /dev/null @@ -1,87 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_TIMER_H__ -#define __MCF523X_TIMER_H__ - -/********************************************************************* -* -* DMA Timers (TIMER) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_TIMER_DTMR0 (*(vuint16*)(void*)(&__IPSBAR[0x000400])) -#define MCF_TIMER_DTXMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000402])) -#define MCF_TIMER_DTER0 (*(vuint8 *)(void*)(&__IPSBAR[0x000403])) -#define MCF_TIMER_DTRR0 (*(vuint32*)(void*)(&__IPSBAR[0x000404])) -#define MCF_TIMER_DTCR0 (*(vuint32*)(void*)(&__IPSBAR[0x000408])) -#define MCF_TIMER_DTCN0 (*(vuint32*)(void*)(&__IPSBAR[0x00040C])) -#define MCF_TIMER_DTMR1 (*(vuint16*)(void*)(&__IPSBAR[0x000440])) -#define MCF_TIMER_DTXMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000442])) -#define MCF_TIMER_DTER1 (*(vuint8 *)(void*)(&__IPSBAR[0x000443])) -#define MCF_TIMER_DTRR1 (*(vuint32*)(void*)(&__IPSBAR[0x000444])) -#define MCF_TIMER_DTCR1 (*(vuint32*)(void*)(&__IPSBAR[0x000448])) -#define MCF_TIMER_DTCN1 (*(vuint32*)(void*)(&__IPSBAR[0x00044C])) -#define MCF_TIMER_DTMR2 (*(vuint16*)(void*)(&__IPSBAR[0x000480])) -#define MCF_TIMER_DTXMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000482])) -#define MCF_TIMER_DTER2 (*(vuint8 *)(void*)(&__IPSBAR[0x000483])) -#define MCF_TIMER_DTRR2 (*(vuint32*)(void*)(&__IPSBAR[0x000484])) -#define MCF_TIMER_DTCR2 (*(vuint32*)(void*)(&__IPSBAR[0x000488])) -#define MCF_TIMER_DTCN2 (*(vuint32*)(void*)(&__IPSBAR[0x00048C])) -#define MCF_TIMER_DTMR3 (*(vuint16*)(void*)(&__IPSBAR[0x0004C0])) -#define MCF_TIMER_DTXMR3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C2])) -#define MCF_TIMER_DTER3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C3])) -#define MCF_TIMER_DTRR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C4])) -#define MCF_TIMER_DTCR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C8])) -#define MCF_TIMER_DTCN3 (*(vuint32*)(void*)(&__IPSBAR[0x0004CC])) -#define MCF_TIMER_DTMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000400+((x)*0x040)])) -#define MCF_TIMER_DTXMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000402+((x)*0x040)])) -#define MCF_TIMER_DTER(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000403+((x)*0x040)])) -#define MCF_TIMER_DTRR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000404+((x)*0x040)])) -#define MCF_TIMER_DTCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000408+((x)*0x040)])) -#define MCF_TIMER_DTCN(x) (*(vuint32*)(void*)(&__IPSBAR[0x00040C+((x)*0x040)])) - -/* Bit definitions and macros for MCF_TIMER_DTMR */ -#define MCF_TIMER_DTMR_RST (0x0001) -#define MCF_TIMER_DTMR_CLK(x) (((x)&0x0003)<<1) -#define MCF_TIMER_DTMR_FRR (0x0008) -#define MCF_TIMER_DTMR_ORRI (0x0010) -#define MCF_TIMER_DTMR_OM (0x0020) -#define MCF_TIMER_DTMR_CE(x) (((x)&0x0003)<<6) -#define MCF_TIMER_DTMR_PS(x) (((x)&0x00FF)<<8) -#define MCF_TIMER_DTMR_CE_ANY (0x00C0) -#define MCF_TIMER_DTMR_CE_FALL (0x0080) -#define MCF_TIMER_DTMR_CE_RISE (0x0040) -#define MCF_TIMER_DTMR_CE_NONE (0x0000) -#define MCF_TIMER_DTMR_CLK_DTIN (0x0006) -#define MCF_TIMER_DTMR_CLK_DIV16 (0x0004) -#define MCF_TIMER_DTMR_CLK_DIV1 (0x0002) -#define MCF_TIMER_DTMR_CLK_STOP (0x0000) - -/* Bit definitions and macros for MCF_TIMER_DTXMR */ -#define MCF_TIMER_DTXMR_MODE16 (0x01) -#define MCF_TIMER_DTXMR_DMAEN (0x80) - -/* Bit definitions and macros for MCF_TIMER_DTER */ -#define MCF_TIMER_DTER_CAP (0x01) -#define MCF_TIMER_DTER_REF (0x02) - -/********************************************************************/ - -#endif /* __MCF523X_TIMER_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_uart.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_uart.h deleted file mode 100644 index 88827e37f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_uart.h +++ /dev/null @@ -1,190 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef __MCF523X_UART_H__ -#define __MCF523X_UART_H__ - -/********************************************************************* -* -* Universal Asynchronous Receiver Transmitter (UART) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_UART_UMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000200])) -#define MCF_UART_USR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204])) -#define MCF_UART_UCSR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204])) -#define MCF_UART_UCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000208])) -#define MCF_UART_URB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C])) -#define MCF_UART_UTB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C])) -#define MCF_UART_UIPCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210])) -#define MCF_UART_UACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210])) -#define MCF_UART_UISR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214])) -#define MCF_UART_UIMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214])) -#define MCF_UART_UBG10 (*(vuint8 *)(void*)(&__IPSBAR[0x000218])) -#define MCF_UART_UBG20 (*(vuint8 *)(void*)(&__IPSBAR[0x00021C])) -#define MCF_UART_UIP0 (*(vuint8 *)(void*)(&__IPSBAR[0x000234])) -#define MCF_UART_UOP10 (*(vuint8 *)(void*)(&__IPSBAR[0x000238])) -#define MCF_UART_UOP00 (*(vuint8 *)(void*)(&__IPSBAR[0x00023C])) -#define MCF_UART_UMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000240])) -#define MCF_UART_USR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244])) -#define MCF_UART_UCSR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244])) -#define MCF_UART_UCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000248])) -#define MCF_UART_URB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C])) -#define MCF_UART_UTB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C])) -#define MCF_UART_UIPCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250])) -#define MCF_UART_UACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250])) -#define MCF_UART_UISR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254])) -#define MCF_UART_UIMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254])) -#define MCF_UART_UBG11 (*(vuint8 *)(void*)(&__IPSBAR[0x000258])) -#define MCF_UART_UBG21 (*(vuint8 *)(void*)(&__IPSBAR[0x00025C])) -#define MCF_UART_UIP1 (*(vuint8 *)(void*)(&__IPSBAR[0x000274])) -#define MCF_UART_UOP11 (*(vuint8 *)(void*)(&__IPSBAR[0x000278])) -#define MCF_UART_UOP01 (*(vuint8 *)(void*)(&__IPSBAR[0x00027C])) -#define MCF_UART_UMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000280])) -#define MCF_UART_USR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284])) -#define MCF_UART_UCSR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284])) -#define MCF_UART_UCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000288])) -#define MCF_UART_URB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C])) -#define MCF_UART_UTB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C])) -#define MCF_UART_UIPCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290])) -#define MCF_UART_UACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290])) -#define MCF_UART_UISR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294])) -#define MCF_UART_UIMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294])) -#define MCF_UART_UBG12 (*(vuint8 *)(void*)(&__IPSBAR[0x000298])) -#define MCF_UART_UBG22 (*(vuint8 *)(void*)(&__IPSBAR[0x00029C])) -#define MCF_UART_UIP2 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B4])) -#define MCF_UART_UOP12 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B8])) -#define MCF_UART_UOP02 (*(vuint8 *)(void*)(&__IPSBAR[0x0002BC])) -#define MCF_UART_UMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000200+((x)*0x040)])) -#define MCF_UART_USR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)])) -#define MCF_UART_UCSR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)])) -#define MCF_UART_UCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000208+((x)*0x040)])) -#define MCF_UART_URB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)])) -#define MCF_UART_UTB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)])) -#define MCF_UART_UIPCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)])) -#define MCF_UART_UACR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)])) -#define MCF_UART_UISR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)])) -#define MCF_UART_UIMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)])) -#define MCF_UART_UBG1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000218+((x)*0x040)])) -#define MCF_UART_UBG2(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00021C+((x)*0x040)])) -#define MCF_UART_UIP(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000234+((x)*0x040)])) -#define MCF_UART_UOP1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000238+((x)*0x040)])) -#define MCF_UART_UOP0(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00023C+((x)*0x040)])) - -/* Bit definitions and macros for MCF_UART_UMR */ -#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) -#define MCF_UART_UMR_PT (0x04) -#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) -#define MCF_UART_UMR_ERR (0x20) -#define MCF_UART_UMR_RXIRQ (0x40) -#define MCF_UART_UMR_RXRTS (0x80) -#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) -#define MCF_UART_UMR_TXCTS (0x10) -#define MCF_UART_UMR_TXRTS (0x20) -#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) -#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) -#define MCF_UART_UMR_PM_MULTI_DATA (0x18) -#define MCF_UART_UMR_PM_NONE (0x10) -#define MCF_UART_UMR_PM_FORCE_HI (0x0C) -#define MCF_UART_UMR_PM_FORCE_LO (0x08) -#define MCF_UART_UMR_PM_ODD (0x04) -#define MCF_UART_UMR_PM_EVEN (0x00) -#define MCF_UART_UMR_BC_5 (0x00) -#define MCF_UART_UMR_BC_6 (0x01) -#define MCF_UART_UMR_BC_7 (0x02) -#define MCF_UART_UMR_BC_8 (0x03) -#define MCF_UART_UMR_CM_NORMAL (0x00) -#define MCF_UART_UMR_CM_ECHO (0x40) -#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) -#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) -#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) -#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) -#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) - -/* Bit definitions and macros for MCF_UART_USR */ -#define MCF_UART_USR_RXRDY (0x01) -#define MCF_UART_USR_FFULL (0x02) -#define MCF_UART_USR_TXRDY (0x04) -#define MCF_UART_USR_TXEMP (0x08) -#define MCF_UART_USR_OE (0x10) -#define MCF_UART_USR_PE (0x20) -#define MCF_UART_USR_FE (0x40) -#define MCF_UART_USR_RB (0x80) - -/* Bit definitions and macros for MCF_UART_UCSR */ -#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) -#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) -#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) -#define MCF_UART_UCSR_RCS_CTM16 (0xE0) -#define MCF_UART_UCSR_RCS_CTM (0xF0) -#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) -#define MCF_UART_UCSR_TCS_CTM16 (0x0E) -#define MCF_UART_UCSR_TCS_CTM (0x0F) - -/* Bit definitions and macros for MCF_UART_UCR */ -#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) -#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) -#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) -#define MCF_UART_UCR_NONE (0x00) -#define MCF_UART_UCR_STOP_BREAK (0x70) -#define MCF_UART_UCR_START_BREAK (0x60) -#define MCF_UART_UCR_BKCHGINT (0x50) -#define MCF_UART_UCR_RESET_ERROR (0x40) -#define MCF_UART_UCR_RESET_TX (0x30) -#define MCF_UART_UCR_RESET_RX (0x20) -#define MCF_UART_UCR_RESET_MR (0x10) -#define MCF_UART_UCR_TX_DISABLED (0x08) -#define MCF_UART_UCR_TX_ENABLED (0x04) -#define MCF_UART_UCR_RX_DISABLED (0x02) -#define MCF_UART_UCR_RX_ENABLED (0x01) - -/* Bit definitions and macros for MCF_UART_UIPCR */ -#define MCF_UART_UIPCR_CTS (0x01) -#define MCF_UART_UIPCR_COS (0x10) - -/* Bit definitions and macros for MCF_UART_UACR */ -#define MCF_UART_UACR_IEC (0x01) - -/* Bit definitions and macros for MCF_UART_UISR */ -#define MCF_UART_UISR_TXRDY (0x01) -#define MCF_UART_UISR_RXRDY_FU (0x02) -#define MCF_UART_UISR_DB (0x04) -#define MCF_UART_UISR_RXFTO (0x08) -#define MCF_UART_UISR_TXFIFO (0x10) -#define MCF_UART_UISR_RXFIFO (0x20) -#define MCF_UART_UISR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIMR */ -#define MCF_UART_UIMR_TXRDY (0x01) -#define MCF_UART_UIMR_RXRDY_FU (0x02) -#define MCF_UART_UIMR_DB (0x04) -#define MCF_UART_UIMR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIP */ -#define MCF_UART_UIP_CTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP1 */ -#define MCF_UART_UOP1_RTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP0 */ -#define MCF_UART_UOP0_RTS (0x01) - -/********************************************************************/ - -#endif /* __MCF523X_UART_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_vars.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_vars.h deleted file mode 100644 index 695cef477..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_vars.h +++ /dev/null @@ -1,50 +0,0 @@ -/************************************************************************** - * FILE NAME: mcf523x_vars.h,v $ COPYRIGHT (c) Freescale 2004 * - * DESCRIPTION: All Rights Reserved * - * Variables that define some features of the MCF523x. * - * !!!!This file must only be included once in every project!!!! * - *========================================================================* - * ORIGINAL AUTHOR: Geoff Emerson [r47354] * - - **************************************************************************/ - -/* eTPU characteristics definition */ -struct eTPU_struct *eTPU = (struct eTPU_struct *)0x401D0000; - -uint32_t fs_etpu_code_start = 0x401E0000; -uint32_t fs_etpu_data_ram_start = 0x401D8000; -uint32_t fs_etpu_data_ram_end = 0x401D85FC; -uint32_t fs_etpu_data_ram_ext = 0x401DC000; - -/********************************************************************* - * - * Copyright: - * Freescale Semiconductor, INC. All Rights Reserved. - * You are hereby granted a copyright license to use, modify, and - * distribute the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Freescale - * Semiconductor, Inc. This software is provided on an "AS IS" - * basis and without warranty. - * - * To the maximum extent permitted by applicable law, Freescale - * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, - * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A - * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH - * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) - * AND ANY ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, - * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER - * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Freescale Semiconductor assumes no responsibility for the - * maintenance and support of this software - * - ********************************************************************/ - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_wtm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_wtm.h deleted file mode 100644 index b56f192e7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf523x/mcf523x_wtm.h +++ /dev/null @@ -1,97 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Register and bit definitions for the MCF523X. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - - -#ifndef __MCF523X_WTM_H__ -#define __MCF523X_WTM_H__ - -/********************************************************************* -* -* Watchdog Timer Modules (WTM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_WTM_WCR (*(vuint16*)(void*)(&__IPSBAR[0x140000])) -#define MCF_WTM_WMR (*(vuint16*)(void*)(&__IPSBAR[0x140002])) -#define MCF_WTM_WCNTR (*(vuint16*)(void*)(&__IPSBAR[0x140004])) -#define MCF_WTM_WSR (*(vuint16*)(void*)(&__IPSBAR[0x140006])) - -/* Bit definitions and macros for MCF_WTM_WCR */ -#define MCF_WTM_WCR_EN (0x0001) -#define MCF_WTM_WCR_HALTED (0x0002) -#define MCF_WTM_WCR_DOZE (0x0004) -#define MCF_WTM_WCR_WAIT (0x0008) - -/* Bit definitions and macros for MCF_WTM_WMR */ -#define MCF_WTM_WMR_WM0 (0x0001) -#define MCF_WTM_WMR_WM1 (0x0002) -#define MCF_WTM_WMR_WM2 (0x0004) -#define MCF_WTM_WMR_WM3 (0x0008) -#define MCF_WTM_WMR_WM4 (0x0010) -#define MCF_WTM_WMR_WM5 (0x0020) -#define MCF_WTM_WMR_WM6 (0x0040) -#define MCF_WTM_WMR_WM7 (0x0080) -#define MCF_WTM_WMR_WM8 (0x0100) -#define MCF_WTM_WMR_WM9 (0x0200) -#define MCF_WTM_WMR_WM10 (0x0400) -#define MCF_WTM_WMR_WM11 (0x0800) -#define MCF_WTM_WMR_WM12 (0x1000) -#define MCF_WTM_WMR_WM13 (0x2000) -#define MCF_WTM_WMR_WM14 (0x4000) -#define MCF_WTM_WMR_WM15 (0x8000) - -/* Bit definitions and macros for MCF_WTM_WCNTR */ -#define MCF_WTM_WCNTR_WC0 (0x0001) -#define MCF_WTM_WCNTR_WC1 (0x0002) -#define MCF_WTM_WCNTR_WC2 (0x0004) -#define MCF_WTM_WCNTR_WC3 (0x0008) -#define MCF_WTM_WCNTR_WC4 (0x0010) -#define MCF_WTM_WCNTR_WC5 (0x0020) -#define MCF_WTM_WCNTR_WC6 (0x0040) -#define MCF_WTM_WCNTR_WC7 (0x0080) -#define MCF_WTM_WCNTR_WC8 (0x0100) -#define MCF_WTM_WCNTR_WC9 (0x0200) -#define MCF_WTM_WCNTR_WC10 (0x0400) -#define MCF_WTM_WCNTR_WC11 (0x0800) -#define MCF_WTM_WCNTR_WC12 (0x1000) -#define MCF_WTM_WCNTR_WC13 (0x2000) -#define MCF_WTM_WCNTR_WC14 (0x4000) -#define MCF_WTM_WCNTR_WC15 (0x8000) - -/* Bit definitions and macros for MCF_WTM_WSR */ -#define MCF_WTM_WSR_WS0 (0x0001) -#define MCF_WTM_WSR_WS1 (0x0002) -#define MCF_WTM_WSR_WS2 (0x0004) -#define MCF_WTM_WSR_WS3 (0x0008) -#define MCF_WTM_WSR_WS4 (0x0010) -#define MCF_WTM_WSR_WS5 (0x0020) -#define MCF_WTM_WSR_WS6 (0x0040) -#define MCF_WTM_WSR_WS7 (0x0080) -#define MCF_WTM_WSR_WS8 (0x0100) -#define MCF_WTM_WSR_WS9 (0x0200) -#define MCF_WTM_WSR_WS10 (0x0400) -#define MCF_WTM_WSR_WS11 (0x0800) -#define MCF_WTM_WSR_WS12 (0x1000) -#define MCF_WTM_WSR_WS13 (0x2000) -#define MCF_WTM_WSR_WS14 (0x4000) -#define MCF_WTM_WSR_WS15 (0x8000) - -/********************************************************************/ - -#endif /* __MCF523X_WTM_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf5xxx.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf5xxx.h deleted file mode 100644 index b9a3edf9a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/mcf5xxx.h +++ /dev/null @@ -1,201 +0,0 @@ -/************************************************************************************ - * Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved * - * * - * * - * * - * DESCRIPTION * - * Definitions common to all ColdFire processors. * - * * - * * - * * - * NOTE * - * * - * * - * * - * HISTORY * - * * - ************************************************************************************/ - -#ifndef _CPU_MCF5XXX_H -#define _CPU_MCF5XXX_H - -/***********************************************************************/ -/* - * Misc. Defines - */ - -#ifdef FALSE -#undef FALSE -#endif -#define FALSE (0) - -#ifdef TRUE -#undef TRUE -#endif -#define TRUE (1) - -#ifdef NULL -#undef NULL -#endif -#define NULL (0) - -/***********************************************************************/ -/* - * The basic data types - */ - -typedef unsigned char uint8; /* 8 bits */ -typedef unsigned short int uint16; /* 16 bits */ -typedef unsigned long int uint32; /* 32 bits */ - -typedef signed char int8; /* 8 bits */ -typedef signed short int int16; /* 16 bits */ -typedef signed long int int32; /* 32 bits */ - -typedef volatile uint8 vuint8; /* 8 bits */ -typedef volatile uint16 vuint16; /* 16 bits */ -typedef volatile uint32 vuint32; /* 32 bits */ - -/***********************************************************************/ -/* - * Common M68K & ColdFire definitions - */ - -#define ADDRESS uint32 -#define INSTRUCTION uint16 -#define ILLEGAL 0x4AFC -#define CPU_WORD_SIZE 16 - -#define MCF5XXX_SR_T (0x8000) -#define MCF5XXX_SR_S (0x2000) -#define MCF5XXX_SR_M (0x1000) -#define MCF5XXX_SR_IPL (0x0700) -#define MCF5XXX_SR_IPL_0 (0x0000) -#define MCF5XXX_SR_IPL_1 (0x0100) -#define MCF5XXX_SR_IPL_2 (0x0200) -#define MCF5XXX_SR_IPL_3 (0x0300) -#define MCF5XXX_SR_IPL_4 (0x0400) -#define MCF5XXX_SR_IPL_5 (0x0500) -#define MCF5XXX_SR_IPL_6 (0x0600) -#define MCF5XXX_SR_IPL_7 (0x0700) -#define MCF5XXX_SR_X (0x0010) -#define MCF5XXX_SR_N (0x0008) -#define MCF5XXX_SR_Z (0x0004) -#define MCF5XXX_SR_V (0x0002) -#define MCF5XXX_SR_C (0x0001) - -#define MCF5XXX_CACR_CENB (0x80000000) -#define MCF5XXX_CACR_CPDI (0x10000000) -#define MCF5XXX_CACR_CPD (0x10000000) -#define MCF5XXX_CACR_CFRZ (0x08000000) -#define MCF5XXX_CACR_CINV (0x01000000) -#define MCF5XXX_CACR_DIDI (0x00800000) -#define MCF5XXX_CACR_DISD (0x00400000) -#define MCF5XXX_CACR_INVI (0x00200000) -#define MCF5XXX_CACR_INVD (0x00100000) -#define MCF5XXX_CACR_CEIB (0x00000400) -#define MCF5XXX_CACR_DCM_WR (0x00000000) -#define MCF5XXX_CACR_DCM_CB (0x00000100) -#define MCF5XXX_CACR_DCM_IP (0x00000200) -#define MCF5XXX_CACR_DCM (0x00000200) -#define MCF5XXX_CACR_DCM_II (0x00000300) -#define MCF5XXX_CACR_DBWE (0x00000100) -#define MCF5XXX_CACR_DWP (0x00000020) -#define MCF5XXX_CACR_EUST (0x00000010) -#define MCF5XXX_CACR_CLNF_00 (0x00000000) -#define MCF5XXX_CACR_CLNF_01 (0x00000002) -#define MCF5XXX_CACR_CLNF_10 (0x00000004) -#define MCF5XXX_CACR_CLNF_11 (0x00000006) - -#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000) -#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8) -#define MCF5XXX_ACR_EN (0x00008000) -#define MCF5XXX_ACR_SM_USER (0x00000000) -#define MCF5XXX_ACR_SM_SUPER (0x00002000) -#define MCF5XXX_ACR_SM_IGNORE (0x00006000) -#define MCF5XXX_ACR_ENIB (0x00000080) -#define MCF5XXX_ACR_CM (0x00000040) -#define MCF5XXX_ACR_DCM_WR (0x00000000) -#define MCF5XXX_ACR_DCM_CB (0x00000020) -#define MCF5XXX_ACR_DCM_IP (0x00000040) -#define MCF5XXX_ACR_DCM_II (0x00000060) -#define MCF5XXX_ACR_CM (0x00000040) -#define MCF5XXX_ACR_BWE (0x00000020) -#define MCF5XXX_ACR_WP (0x00000004) - -#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000) -#define MCF5XXX_RAMBAR_PRI_00 (0x00000000) -#define MCF5XXX_RAMBAR_PRI_01 (0x00004000) -#define MCF5XXX_RAMBAR_PRI_10 (0x00008000) -#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000) -#define MCF5XXX_RAMBAR_WP (0x00000100) -#define MCF5XXX_RAMBAR_CI (0x00000020) -#define MCF5XXX_RAMBAR_SC (0x00000010) -#define MCF5XXX_RAMBAR_SD (0x00000008) -#define MCF5XXX_RAMBAR_UC (0x00000004) -#define MCF5XXX_RAMBAR_UD (0x00000002) -#define MCF5XXX_RAMBAR_V (0x00000001) - -/***********************************************************************/ -/* - * The ColdFire family of processors has a simplified exception stack - * frame that looks like the following: - * - * 3322222222221111 111111 - * 1098765432109876 5432109876543210 - * 8 +----------------+----------------+ - * | Program Counter | - * 4 +----------------+----------------+ - * |FS/Fmt/Vector/FS| SR | - * SP --> 0 +----------------+----------------+ - * - * The stack self-aligns to a 4-byte boundary at an exception, with - * the FS/Fmt/Vector/FS field indicating the size of the adjustment - * (SP += 0,1,2,3 bytes). - */ - -#define MCF5XXX_RD_SF_FORMAT(PTR) \ - ((*((uint16 *)(PTR)) >> 12) & 0x00FF) - -#define MCF5XXX_RD_SF_VECTOR(PTR) \ - ((*((uint16 *)(PTR)) >> 2) & 0x00FF) - -#define MCF5XXX_RD_SF_FS(PTR) \ - ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) ) - -#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1) -#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1) - -/********************************************************************/ -/* - * Functions provided by mcf5xxx.s - */ - -int asm_set_ipl (uint32); -void mcf5xxx_wr_cacr (uint32); -void mcf5xxx_wr_acr0 (uint32); -void mcf5xxx_wr_acr1 (uint32); -void mcf5xxx_wr_acr2 (uint32); -void mcf5xxx_wr_acr3 (uint32); -void mcf5xxx_wr_other_a7 (uint32); -void mcf5xxx_wr_other_sp (uint32); -void mcf5xxx_wr_vbr (uint32); -void mcf5xxx_wr_macsr (uint32); -void mcf5xxx_wr_mask (uint32); -void mcf5xxx_wr_acc0 (uint32); -void mcf5xxx_wr_accext01 (uint32); -void mcf5xxx_wr_accext23 (uint32); -void mcf5xxx_wr_acc1 (uint32); -void mcf5xxx_wr_acc2 (uint32); -void mcf5xxx_wr_acc3 (uint32); -void mcf5xxx_wr_sr (uint32); -void mcf5xxx_wr_rambar0 (uint32); -void mcf5xxx_wr_rambar1 (uint32); -void mcf5xxx_wr_mbar (uint32); -void mcf5xxx_wr_mbar0 (uint32); -void mcf5xxx_wr_mbar1 (uint32); - -/********************************************************************/ - -#endif /* _CPU_MCF5XXX_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/typedefs.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/typedefs.h deleted file mode 100644 index 57ae6a33c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/arch/typedefs.h +++ /dev/null @@ -1,86 +0,0 @@ - -#ifndef _TYPEDEFS_H_ -#define _TYPEDEFS_H_ - -#ifdef __MWERKS__ //Metrowerk CodeWarrior - #include - - // Standard typedefs used by header files, based on ISO C standard - typedef volatile int8_t vint8_t; - typedef volatile uint8_t vuint8_t; - - typedef volatile int16_t vint16_t; - typedef volatile uint16_t vuint16_t; - - typedef volatile int32_t vint32_t; - typedef volatile uint32_t vuint32_t; - -#else -#ifdef __GHS__ //GreenHills - #include - - // Standard typedefs used by header files, based on ISO C standard - typedef volatile int8_t vint8_t; - typedef volatile uint8_t vuint8_t; - - typedef volatile int16_t vint16_t; - typedef volatile uint16_t vuint16_t; - - typedef volatile int32_t vint32_t; - typedef volatile uint32_t vuint32_t; - -#else - - // This is needed for compilers that don't have a stdint.h file - - typedef signed char int8_t; - typedef unsigned char uint8_t; - typedef volatile signed char vint8_t; - typedef volatile unsigned char vuint8_t; - - typedef signed short int16_t; - typedef unsigned short uint16_t; - typedef volatile signed short vint16_t; - typedef volatile unsigned short vuint16_t; - - typedef signed int int32_t; - typedef unsigned int uint32_t; - typedef volatile signed int vint32_t; - typedef volatile unsigned int vuint32_t; - -#endif -#endif -#endif - -/********************************************************************* - * - * Copyright: - * Freescale Semiconductor, INC. All Rights Reserved. - * You are hereby granted a copyright license to use, modify, and - * distribute the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Freescale - * Semiconductor, Inc. This software is provided on an "AS IS" - * basis and without warranty. - * - * To the maximum extent permitted by applicable law, Freescale - * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, - * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A - * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH - * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) - * AND ANY ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, - * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER - * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Freescale Semiconductor assumes no responsibility for the - * maintenance and support of this software - * - ********************************************************************/ - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/ram_symbol.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/ram_symbol.h deleted file mode 100644 index 5434e8e20..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/ram_symbol.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Defining DEBUG turns on debug print information */ -#define DEBUG 1 - -/* CodeWarrior looks for an underscore prepended to C function names */ -#define _UNDERSCORE_ - -/* Define a constant to inform files we are using CodeWarrior */ -#ifndef _MWERKS_ -#define _MWERKS_ -#endif - -/* Modify the interrupt type to work with CodeWarrior */ -#define __interrupt__ __declspec(interrupt) - -#define CODEWARRIOR_MCF5235 -#define FCPU ( 150000000UL ) -#define FSYS_2 ( 75000000UL ) diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/rom_symbol.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/rom_symbol.h deleted file mode 100644 index c6742793c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/include/rom_symbol.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Define the board we are running on */ -#define M5249C3 /* HSEVB */ - -/* Defining DEBUG turns on debug print information */ -#define DEBUG 1 - -/* CodeWarrior looks for an underscore prepended to C function names */ -#define _UNDERSCORE_ - -/* Define a constant to inform files we are using CodeWarrior */ -#ifndef _MWERKS_ -#define _MWERKS_ -#endif - -/* Modify the interrupt type to work with CodeWarrior */ -#define __interrupt__ __declspec(interrupt) - -#define ROM_TARGET - -#define CODEWARRIOR_MCF5235 -#define FCPU ( 150000000UL ) -#define FSYS_2 ( 75000000UL ) diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/port/port.h deleted file mode 100644 index 2ea2ed537..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/port/port.h +++ /dev/null @@ -1,62 +0,0 @@ - /* - * FreeModbus Libary: MCF5235 Port - * Copyright (C) 2006 Christian Walter - * Parts of crt0.S Copyright (c) 1995, 1996, 1998 Cygnus Support - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -/* ----------------------- Defines ----------------------------------------- */ -#define INLINE -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#undef assert -#define assert( x ) - -#define ENTER_CRITICAL_SECTION( ) prvvPortEnterCritical() -#define EXIT_CRITICAL_SECTION( ) prvvPortExitCritical() - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -/* ----------------------- Type definitions -------------------------------- */ -typedef char BOOL; - -typedef unsigned char UCHAR; -typedef char CHAR; - -typedef unsigned short USHORT; -typedef short SHORT; - -typedef unsigned long ULONG; -typedef long LONG; - -/* ----------------------- Defines ----------------------------------------- */ -void prvvPortEnterCritical( ); -void prvvPortExitCritical( ); - - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/port/portevent.c deleted file mode 100644 index 963269a2c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/port/portevent.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * FreeModbus Libary: MCF5235 Port - * Copyright (C) 2006 Christian Walter - * Parts of crt0.S Copyright (c) 1995, 1996, 1998 Cygnus Support - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static eMBEventType eQueuedEvent; -static BOOL xEventInQueue; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - xEventInQueue = FALSE; - return TRUE; -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - xEventInQueue = TRUE; - eQueuedEvent = eEvent; - return TRUE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - BOOL xEventHappened = FALSE; - - if( xEventInQueue ) - { - *eEvent = eQueuedEvent; - xEventInQueue = FALSE; - xEventHappened = TRUE; - } - return xEventHappened; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/port/portother.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/port/portother.c deleted file mode 100644 index 1ea8109d3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/port/portother.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * FreeModbus Libary: MCF5235 Port - * Copyright (C) 2006 Christian Walter - * Parts of crt0.S Copyright (c) 1995, 1996, 1998 Cygnus Support - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "port.h" -#include "mcf5xxx.h" -#include "mcf523x.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Static variables ---------------------------------*/ -static int uiRegSR; -static char *heap_ptr; - -/* ----------------------- Start implementation -----------------------------*/ -void -prvvPortEnterCritical( ) -{ - - uiRegSR = asm_set_ipl( 7 ); -} - -void -prvvPortExitCritical( ) -{ - ( void )asm_set_ipl( ( uint32 ) uiRegSR ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/port/portserial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/port/portserial.c deleted file mode 100644 index a5cc60691..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/port/portserial.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * FreeModbus Libary: MCF5235 Port - * Copyright (C) 2006 Christian Walter - * Parts of crt0.S Copyright (c) 1995, 1996, 1998 Cygnus Support - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes --------------------------------- */ -#include "port.h" -#include "m523xbcc.h" - -/* ----------------------- Modbus includes --------------------------------- */ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ----------------------------------------- */ -#define BAUDRATE_VALUE(fsys, baud) ( ( fsys )/(32UL * baud) ) - -/* ----------------------- Static variables -------------------------------- */ -BOOL bTXEnabled; -BOOL bRXEnabled; - -/* ----------------------- Start implementation ---------------------------- */ - -void -vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable ) -{ - UCHAR ucUCR = 0; - UCHAR ucIMR = 0; - - if( xRxEnable ) - { - ucUCR |= MCF_UART_UCR_RXC( 0x1 ); - ucIMR |= MCF_UART_UIMR_RXRDY_FU; - bRXEnabled = TRUE; - } - else - { - ucUCR |= MCF_UART_UCR_RXC( 0x2 ); - bRXEnabled = FALSE; - } - if( xTxEnable ) - { - ucUCR |= MCF_UART_UCR_TXC( 0x1 ); - ucIMR |= MCF_UART_UIMR_TXRDY; - bTXEnabled = TRUE; - } - else - { - ucUCR |= MCF_UART_UCR_TXC( 0x2 ); - bTXEnabled = FALSE; - } - MCF_UART_UCR0 = ucUCR; - MCF_UART_UIMR0 = ucIMR; -} - -BOOL -xMBPortSerialInit( UCHAR ucPort, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity ) -{ - BOOL bStatus = TRUE; - UCHAR ucMode = 0; - - ( void )ucPort; - - switch ( eParity ) - { - case MB_PAR_EVEN: - ucMode |= MCF_UART_UMR_PM( 0x0 ); - break; - case MB_PAR_ODD: - ucMode |= MCF_UART_UMR_PM( 0x0 ) | MCF_UART_UMR_PT; - break; - case MB_PAR_NONE: - ucMode |= MCF_UART_UMR_PM( 0x3 ); - break; - default: - bStatus = FALSE; - } - - switch ( ucDataBits ) - { - case 8: - ucMode |= MCF_UART_UMR_BC( 0x3 ); - break; - case 7: - ucMode |= MCF_UART_UMR_BC( 0x2 ); - break; - default: - bStatus = FALSE; - } - if( bStatus == TRUE ) - { - /* UART 0: Reset transmitter, receiver and mode register pointer */ - MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x3 ); - MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x2 ); - MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x1 ); - - /* UART 0: Configure parity, databits and stopbits. */ - MCF_UART_UMR0 = ucMode; - MCF_UART_UMR0 = MCF_UART_UMR_SB( 0x7 ); - - /* UART 0 Clocking */ - MCF_UART_UCSR0 = MCF_UART_UCSR_RCS( 0xd ) | MCF_UART_UCSR_TCS( 0xd ); - MCF_UART_UBG10 = ( UCHAR ) ( BAUDRATE_VALUE( FSYS_2, ulBaudRate ) >> 8U ); - MCF_UART_UBG20 = ( UCHAR ) ( BAUDRATE_VALUE( FSYS_2, ulBaudRate ) & 0xFFU ); - - /* UART 0: Enable interrupts */ - MCF_INTC0_ICR13 = MCF_INTC0_ICRn_IL( 0x2 ) | MCF_INTC0_ICRn_IP( 0x1 ); - MCF_INTC0_IMRL &= ~MCF_INTC0_IMRL_INT_MASK13; - - /* UART 0 Miscellaneous */ - MCF_UART_UACR0 = 0; - - /* UART 0: Enable pins */ - MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_U0RXD | MCF_GPIO_PAR_UART_PAR_U0TXD; - vMBPortSerialEnable( FALSE, FALSE ); - } - - return TRUE; -} - -BOOL -xMBPortSerialPutByte( CHAR ucByte ) -{ - MCF_UART_UTB0 = ( UCHAR ) ucByte; - return TRUE; -} - -BOOL -xMBPortSerialGetByte( CHAR * pucByte ) -{ - *pucByte = ( CHAR ) MCF_UART_URB0; - return TRUE; -} - -__declspec( interrupt ) - void prvvMBPortSerialISR( ) -{ - if( bTXEnabled && ( MCF_UART_UISR0 & MCF_UART_UISR_TXRDY ) ) - { - ( void )pxMBFrameCBTransmitterEmpty( ); - } - if( bRXEnabled && ( MCF_UART_UISR0 & MCF_UART_UISR_RXRDY_FU ) ) - { - ( void )pxMBFrameCBByteReceived( ); - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/port/porttimer.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/port/porttimer.c deleted file mode 100644 index 185550936..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/port/porttimer.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * FreeModbus Libary: MCF5235 Port - * Copyright (C) 2006 Christian Walter - * Parts of crt0.S Copyright (c) 1995, 1996, 1998 Cygnus Support - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes --------------------------------- */ -#include "port.h" -#include "m523xbcc.h" -#include "FreeRTOS.h" -#include "task.h" - -/* ----------------------- Modbus includes --------------------------------- */ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ----------------------------------------- */ -#define PIT_PRESCALER 4096UL -#define PIT_TIMER_TICKS ( FSYS_2 / PIT_PRESCALER ) -#define PIT_MODULUS_REGISTER(t50us) \ - ( (t50us * PIT_TIMER_TICKS )/20000UL - 1UL) - -/* ----------------------- Static variables -------------------------------- */ -USHORT usTimerModulus; - -/* ----------------------- Start implementation ---------------------------- */ - -BOOL -xMBPortTimersInit( USHORT usTim1Timerout50us ) -{ - usTimerModulus = ( USHORT ) PIT_MODULUS_REGISTER( usTim1Timerout50us ); - /* Configure prescaler */ - MCF_PIT_PCSR1 = MCF_PIT_PCSR_PRE( 12 ) | MCF_PIT_PCSR_OVW; - /* Configure interrupt priority and level */ - MCF_INTC0_ICR37 = MCF_INTC0_ICRn_IL( 0x3 ) | MCF_INTC0_ICRn_IP( 0x1 ); - /* Unmask interrupt */ - MCF_INTC0_IMRH &= ~MCF_INTC0_IMRH_INT_MASK37; - - return TRUE; -} - -void -vMBPortTimersEnable( ) -{ - MCF_GPIO_PPDSDR_FECI2C = MCF_GPIO_PODR_FECI2C_PODR_FECI2C0; - - MCF_PIT_PMR1 = usTimerModulus; - MCF_PIT_PCSR1 |= MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_EN | MCF_PIT_PCSR_PIF; -} - - -void -vMBPortTimersDisable( ) -{ - MCF_GPIO_PCLRR_FECI2C = ( UCHAR ) ~ MCF_GPIO_PODR_FECI2C_PODR_FECI2C0; - - MCF_PIT_PCSR1 |= MCF_PIT_PCSR_PIF; - MCF_PIT_PCSR1 &= ~MCF_PIT_PCSR_PIE; - MCF_PIT_PCSR1 &= ~MCF_PIT_PCSR_EN; -} - -extern volatile void *pxCurrentTCB; - -static BOOL -prvvMBPortTimerISRImpl( void ) -{ - MCF_PIT_PCSR1 |= MCF_PIT_PCSR_PIF; - return pxMBPortCBTimerExpired( ); -} - -asm void -prvvMBPortTimerISR( void ) -{ - move.w #0x2700, sr; - portSAVE_CONTEXT_IMPL( ); - jsr prvvMBPortTimerISRImpl; - - cmp.l #0, d0 - beq exit - jsr vTaskSwitchContext; -exit: - portRESTORE_CONTEXT_IMPL( ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/mcf5235-bcckit-flash.xml b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/mcf5235-bcckit-flash.xml deleted file mode 100644 index 4f776e9f3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/mcf5235-bcckit-flash.xml +++ /dev/null @@ -1,47 +0,0 @@ - - - - - true - 523x - PEMICRO_PARALLEL - true - C:\Projects\freemodbus-new\demo\MCF5235CW\support\mcf523x.cfg - 0x10000000 - 0x10006000 - true - false - - - - 0x00000000 - AM29PL160CB - 1Mx16x1 - 0x00000000 - 0x001FFFFF - - - - true - - Auto Detect - false - 0xFF800000 - 0xFFFFFFFF - false - 0x00000000 - - - - true - - true - - - - FileOnTarg - 0xFF800000 - 0x007FFFFF - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/mcf5235-bcckit-test.xml b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/mcf5235-bcckit-test.xml deleted file mode 100644 index 07054305e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/mcf5235-bcckit-test.xml +++ /dev/null @@ -1,40 +0,0 @@ - - - - - true - Generic - PEMICRO_PARALLEL - true - C:\Projects\freemodbus-new\demo\MCF5235CW\support\mcf523x.cfg - - - - read - byte - 0x01000000 - 67 - - - - read - byte - 0x00100000 - 0x67 - 1000 - - - - true - true - true - 0x00000010 - 0x000000FF - byte - 1 - false - 0x00000100 - 0x0000FFFF - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/mcf523x-simple.cfg b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/mcf523x-simple.cfg deleted file mode 100644 index 093ba7b98..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/mcf523x-simple.cfg +++ /dev/null @@ -1,7 +0,0 @@ -ResetHalt -Delay 200 -Stop - -; --------------------------- WCR DISABLE------------------------------------ -writemem.w 0x40140000 0x0000 - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/mcf523x.cfg b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/mcf523x.cfg deleted file mode 100644 index 09de212e7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/mcf523x.cfg +++ /dev/null @@ -1,50 +0,0 @@ -ResetHalt -Delay 200 -Stop - -; --------------------------- Set VBR to beginning of SRAM ------------------ -; writecontrolreg 0x0801 0x20000000 - -; --------------------------- RAMBAR INIT ----------------------------------- -; Set RAMBAR = 0x20000001 -writecontrolreg 0x0C05 0x20000001 - -; --------------------------- FLASH INIT ------------------------------------ -; 2MB FLASH on CS0 at 0x00000000 -writemem.w 0x40000080 0x0000 -writemem.l 0x40000084 0x001F0001 -writemem.w 0x4000008A 0x1980 -delay 100 - -; --------------------------- SDRAM INIT ------------------------------------ -; 16MB SDRAM at 0x10000000 - -; Set PAR_SDRAM to allow SDRAM signals to be enabled -writemem.b 0x40100046 0x3F -; Set PAR_AD to allow 32-bit SDRAM if the exteranl boot device is 16-bits -writemem.b 0x40100040 0xE1 - -; 16 MB SDRAM -writemem.w 0x40000040 0x0446 -writemem.l 0x40000048 0x10001300 -writemem.l 0x4000004C 0x00FC0001 - -; Set IP in DACR and init precharge. -writemem.l 0x40000048 0x10001308 -writemem.l 0x10000000 0xAA55AA55 - -; Wait a bit -delay 100 - -; Set RE in DACR -writemem.l 0x40000048 0x10009300 -; Issue IMRS -writemem.l 0x40000048 0x10009340 -writemem.l 0x10000400 0xAA55AA55 - -; Wait a bit more -delay 600 - -; --------------------------- WCR DISABLE------------------------------------ -writemem.w 0x40140000 0x0000 - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/mcf523x.mem b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/mcf523x.mem deleted file mode 100644 index beaaec446..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/mcf523x.mem +++ /dev/null @@ -1,865 +0,0 @@ -// Memory Configuration File -// -// Description: -// A memory configuration file contains commands that define the legally -// accessible areas of memory for your specific board. Useful for example -// when the debugger tries to display the content of a "char *" variable, -// that has not yet been initialized. -// In this case the debugger may try to read from a bogus address, which -// could cause a bus error. -// -// Board: -// Freescale M5235BCCKIT -// - -// Memory Map: -// -------------------------------------------------------------------- -range 0x00000000 0x001FFFFF 4 Read // 2 Mbytes External Flash -range 0x10000000 0x10FFFFFF 1 ReadWrite // 16 Mbyte SDRAM -reserved 0x11000000 0x1FFFFFFF -range 0x20000000 0x2000FFFF 1 ReadWrite // 64 Kbytes Internal SRAM -reserved 0x20010000 0x3FFFFFFF -reserved 0x40200000 0xfFFFFFFF - -// Memory Mapped Registers (IPSBAR= 0x40000000): -// ------------------------------------------------------------------- - -// System Control Module Registers -range 0x40000000 0x40000003 4 ReadWrite // IPSBAR -reserved 0x40000004 0x4000000F -range 0x40000010 0x40000010 1 ReadWrite // CRSR -range 0x40000011 0x40000011 1 ReadWrite // CWCR -range 0x40000012 0x40000012 1 ReadWrite // LPICR -range 0x40000013 0x40000013 1 ReadWrite // CWSR -range 0x40000014 0x40000017 4 ReadWrite // DMAREQC -reserved 0x40000018 0x4000001B -range 0x4000001C 0x4000001F 4 ReadWrite // MPARK -range 0x40000020 0x40000020 1 ReadWrite // MPR -reserved 0x40000021 0x40000023 -range 0x40000024 0x40000024 1 ReadWrite // PACR0 -range 0x40000025 0x40000025 1 ReadWrite // PACR1 -range 0x40000026 0x40000026 1 ReadWrite // PACR2 -range 0x40000027 0x40000027 1 ReadWrite // PACR3 -range 0x40000028 0x40000028 1 ReadWrite // PACR4 -reserved 0x40000029 0x40000029 -range 0x4000002A 0x4000002A 1 ReadWrite // PACR5 -range 0x4000002B 0x4000002B 1 ReadWrite // PACR6 -range 0x4000002C 0x4000002C 1 ReadWrite // PACR7 -reserved 0x4000002D 0x4000002D -range 0x4000002E 0x4000002E 1 ReadWrite // PACR8 -reserved 0x4000002F 0x4000002F -range 0x40000030 0x40000030 1 ReadWrite // GPACR0 -reserved 0x40000031 0x40000031 -range 0x40000032 0x40000032 1 ReadWrite // GPACR1 -reserved 0x40000033 0x4000003F - -// SDRAM Registers -range 0x40000040 0x40000041 2 ReadWrite // DCR -reserved 0x40000042 0x40000047 -range 0x40000048 0x4000004B 4 ReadWrite // DACR0 -range 0x4000004C 0x4000004F 4 ReadWrite // DMR0 -range 0x40000050 0x40000053 4 ReadWrite // DACR1 -range 0x40000054 0x40000057 4 ReadWrite // DMR1 -reserved 0x40000058 0x4000007F - -// Chip Select Module Registers -range 0x40000080 0x40000081 2 ReadWrite // CSAR0 -reserved 0x40000082 0x40000083 -range 0x40000084 0x40000087 4 ReadWrite // CSMR0 -reserved 0x40000088 0x40000089 -range 0x4000008A 0x4000008B 2 ReadWrite // CSCR0 -range 0x4000008C 0x4000008D 2 ReadWrite // CSAR1 -reserved 0x4000008E 0x4000008F -range 0x40000090 0x40000093 4 ReadWrite // CSMR1 -reserved 0x40000094 0x40000095 -range 0x40000096 0x40000097 2 ReadWrite // CSCR1 -range 0x40000098 0x40000099 2 ReadWrite // CSAR2 -reserved 0x4000009A 0x4000009B -range 0x4000009C 0x4000009F 4 ReadWrite // CSMR2 -reserved 0x400000A0 0x400000A1 -range 0x400000A2 0x400000A3 2 ReadWrite // CSCR2 -range 0x400000A4 0x400000A5 2 ReadWrite // CSAR3 -reserved 0x400000A6 0x400000A7 -range 0x400000A8 0x400000AB 4 ReadWrite // CSMR3 -reserved 0x400000AC 0x400000AD -range 0x400000AE 0x400000AF 2 ReadWrite // CSCR3 -range 0x400000B0 0x400000B1 2 ReadWrite // CSAR4 -reserved 0x400000B2 0x400000B3 -range 0x400000B4 0x400000B7 4 ReadWrite // CSMR4 -reserved 0x400000B8 0x400000B9 -range 0x400000BA 0x400000BB 2 ReadWrite // CSCR4 -range 0x400000BC 0x400000BD 2 ReadWrite // CSAR5 -reserved 0x400000BE 0x400000BF -range 0x400000C0 0x400000C3 4 ReadWrite // CSMR5 -reserved 0x400000C4 0x400000C5 -range 0x400000C6 0x400000C7 2 ReadWrite // CSCR5 -range 0x400000C8 0x400000C9 2 ReadWrite // CSAR6 -reserved 0x400000CA 0x400000CB -range 0x400000CC 0x400000CF 4 ReadWrite // CSMR6 -reserved 0x400000D0 0x400000D1 -range 0x400000D2 0x400000D3 2 ReadWrite // CSCR6 -range 0x400000D4 0x400000D5 2 ReadWrite // CSAR7 -reserved 0x400000D6 0x400000D7 -range 0x400000D8 0x400000DB 4 ReadWrite // CSMR7 -reserved 0x400000DC 0x400000DD -range 0x400000DE 0x400000DF 2 ReadWrite // CSCR7 -reserved 0x400000E0 0x400000FF - -// DMA Channel 0 Registers -range 0x40000100 0x40000103 4 ReadWrite // SAR0 -range 0x40000104 0x40000107 4 ReadWrite // DAR0 -range 0x40000108 0x40000108 1 ReadWrite // DSR0 -range 0x40000109 0x4000010B 1 ReadWrite // BCR0 -range 0x4000010C 0x4000010F 4 ReadWrite // DCR0 - -// DMA Channel 1 Registers -range 0x40000110 0x40000113 4 ReadWrite // SAR1 -range 0x40000114 0x40000117 4 ReadWrite // DAR1 -range 0x40000118 0x40000118 1 ReadWrite // DSR1 -range 0x40000119 0x4000011B 1 ReadWrite // BCR1 -range 0x4000011C 0x4000011F 4 ReadWrite // DCR1 - -// DMA Channel 2 Registers -range 0x40000120 0x40000123 4 ReadWrite // SAR2 -range 0x40000124 0x40000127 4 ReadWrite // DAR2 -range 0x40000128 0x40000128 1 ReadWrite // DSR2 -range 0x40000129 0x4000012B 1 ReadWrite // BCR2 -range 0x4000012C 0x4000012F 4 ReadWrite // DCR2 - -// DMA Channel 3 Registers -range 0x40000130 0x40000133 4 ReadWrite // SAR3 -range 0x40000134 0x40000137 4 ReadWrite // DAR3 -range 0x40000138 0x40000138 1 ReadWrite // DSR3 -range 0x40000139 0x4000013B 1 ReadWrite // BCR3 -range 0x4000013C 0x4000013F 4 ReadWrite // DCR3 -reserved 0x40000140 0x400001FF - -// UART0 Registers -range 0x40000200 0x40000200 1 ReadWrite // UMR10 (ReadWrite) / UMR20 (ReadWrite) -reserved 0x40000201 0x40000203 -range 0x40000204 0x40000204 1 ReadWrite // USR0 (Read) / UCSR0 (Write) -reserved 0x40000205 0x40000207 -range 0x40000208 0x40000208 1 Write // UCR0 -reserved 0x40000209 0x4000020B -range 0x4000020C 0x4000020C 1 ReadWrite // URB0 (Read) / UTB0 (Write) -reserved 0x4000020D 0x4000020F -range 0x40000210 0x40000210 1 ReadWrite // UIPCR0 (Read) / UACR0 (Write) -reserved 0x40000211 0x40000213 -range 0x40000214 0x40000214 1 ReadWrite // UISR0 (Read) / UIMR0 (Write) -reserved 0x40000215 0x40000217 -range 0x40000218 0x40000218 1 Write // UBG10 -reserved 0x40000219 0x4000021B -range 0x4000021C 0x4000021C 1 Write // UBG20 -reserved 0x4000021D 0x40000233 -range 0x40000234 0x40000234 1 Read // UIP0 -reserved 0x40000235 0x40000237 -range 0x40000238 0x40000238 1 Write // UOP10 -reserved 0x40000239 0x4000023B -range 0x4000023C 0x4000023C 1 Write // UOP00 -reserved 0x4000023D 0x4000023F - -// UART1 Registers -range 0x40000240 0x40000240 1 ReadWrite // UMR11 (ReadWrite) / UMR21 (ReadWrite) -reserved 0x40000241 0x40000243 -range 0x40000244 0x40000244 1 ReadWrite // USR1 (Read) / UCSR1 (Write) -reserved 0x40000245 0x40000247 -range 0x40000248 0x40000248 1 Write // UCR1 -reserved 0x40000249 0x4000024B -range 0x4000024C 0x4000024C 1 ReadWrite // URB1 (Read) / UTB1 (Write) -reserved 0x4000024D 0x4000024F -range 0x40000250 0x40000250 1 ReadWrite // UIPCR1 (Read) / UACR1 (Write) -reserved 0x40000251 0x40000253 -range 0x40000254 0x40000254 1 ReadWrite // UISR1 (Read) / UIMR1 (Write) -reserved 0x40000255 0x40000257 -range 0x40000258 0x40000258 1 Write // UBG11 -reserved 0x40000259 0x4000025B -range 0x4000025C 0x4000025C 1 Write // UBG21 -reserved 0x4000025D 0x40000273 -range 0x40000274 0x40000274 1 Read // UIP1 -reserved 0x40000275 0x40000277 -range 0x40000278 0x40000278 1 Write // UOP11 -reserved 0x40000279 0x4000027B -range 0x4000027C 0x4000027C 1 Write // UOP01 -reserved 0x4000027D 0x4000027F - -// UART2 Registers -range 0x40000280 0x40000280 1 ReadWrite // UMR12 (ReadWrite) / UMR22 (ReadWrite) -reserved 0x40000281 0x40000283 -range 0x40000284 0x40000284 1 ReadWrite // USR2 (Read) / UCSR2 (Write) -reserved 0x40000285 0x40000287 -range 0x40000288 0x40000288 1 Write // UCR2 -reserved 0x40000289 0x4000028B -range 0x4000028C 0x4000028C 1 ReadWrite // URB2 (Read) / UTB2 (Write) -reserved 0x4000028D 0x4000028F -range 0x40000290 0x40000290 1 ReadWrite // UIPCR2 (Read) / UACR2 (Write) -reserved 0x40000291 0x40000293 -range 0x40000294 0x40000294 1 ReadWrite // UISR2 (Read) / UIMR2 (Write) -reserved 0x40000295 0x40000297 -range 0x40000298 0x40000298 1 Write // UBG12 -reserved 0x40000299 0x4000029B -range 0x4000029C 0x4000029C 1 Write // UBG22 -reserved 0x4000029D 0x400002B3 -range 0x400002B4 0x400002B4 1 Read // UIP2 -reserved 0x400002B5 0x400002B7 -range 0x400002B8 0x400002B8 1 Write // UOP12 -reserved 0x400002B9 0x400002BB -range 0x400002BC 0x400002BC 1 Write // UOP02 -reserved 0x400002BD 0x400002FF - -// I2C Registers -range 0x40000300 0x40000300 1 ReadWrite // I2ADR -reserved 0x40000301 0x40000303 -range 0x40000304 0x40000304 1 ReadWrite // I2FDR -reserved 0x40000305 0x40000307 -range 0x40000308 0x40000308 1 ReadWrite // I2CR -reserved 0x40000309 0x4000030B -range 0x4000030C 0x4000030C 1 ReadWrite // I2SR -reserved 0x4000030D 0x4000030F -range 0x40000310 0x40000310 1 ReadWrite // I2DR -reserved 0x40000311 0x4000033F - -// Queued Serial Peripheral Interface Module Registers -range 0x40000340 0x40000341 2 ReadWrite // QMR -reserved 0x40000342 0x40000343 -range 0x40000344 0x40000345 2 ReadWrite // QDLYR -reserved 0x40000346 0x40000347 -range 0x40000348 0x40000349 2 ReadWrite // QWR -reserved 0x4000034A 0x4000034B -range 0x4000034C 0x4000034D 2 ReadWrite // QIR -reserved 0x4000034E 0x4000034F -range 0x40000350 0x40000351 2 ReadWrite // QAR -reserved 0x40000352 0x40000353 -range 0x40000354 0x40000355 2 ReadWrite // QDR -reserved 0x40000356 0x400003FF - -// DMA Timer 0 Registers -range 0x40000400 0x40000401 2 ReadWrite // DTMR0 -range 0x40000402 0x40000402 1 ReadWrite // DTXMR0 -range 0x40000403 0x40000403 1 ReadWrite // DTER0 -range 0x40000404 0x40000407 4 ReadWrite // DTRR0 -range 0x40000408 0x4000040B 4 ReadWrite // DTCR0 -range 0x4000040C 0x4000040F 4 ReadWrite // DTCN0 -reserved 0x40000410 0x4000043F - -// DMA Timer 1 Registers -range 0x40000440 0x40000441 2 ReadWrite // DTMR1 -range 0x40000442 0x40000442 1 ReadWrite // DTXMR1 -range 0x40000443 0x40000443 1 ReadWrite // DTER1 -range 0x40000444 0x40000447 4 ReadWrite // DTRR1 -range 0x40000448 0x4000044B 4 ReadWrite // DTCR1 -range 0x4000044C 0x4000044F 4 ReadWrite // DTCN1 -reserved 0x40000450 0x4000047F - -// DMA Timer 2 Registers -range 0x40000480 0x40000481 2 ReadWrite // DTMR2 -range 0x40000482 0x40000482 1 ReadWrite // DTXMR2 -range 0x40000483 0x40000483 1 ReadWrite // DTER2 -range 0x40000484 0x40000487 4 ReadWrite // DTRR2 -range 0x40000488 0x4000048B 4 ReadWrite // DTCR2 -range 0x4000048C 0x4000048F 4 ReadWrite // DTCN2 -reserved 0x40000490 0x400004BF - -// DMA Timer 3 Registers -range 0x400004C0 0x400004C1 2 ReadWrite // DTMR3 -range 0x400004C2 0x400004C2 1 ReadWrite // DTXMR3 -range 0x400004C3 0x400004C3 1 ReadWrite // DTER3 -range 0x400004C4 0x400004C7 4 ReadWrite // DTRR3 -range 0x400004C8 0x400004CB 4 ReadWrite // DTCR3 -range 0x400004CC 0x400004CF 4 ReadWrite // DTCN3 -reserved 0x400004D0 0x40000BFF - -// Interrupt Controller Registers 0 -range 0x40000C00 0x40000C03 4 Read // IPRH0 -range 0x40000C04 0x40000C07 4 Read // IPRL0 -range 0x40000C08 0x40000C0B 4 ReadWrite // IMRH0 -range 0x40000C0C 0x40000C0F 4 ReadWrite // IMRL0 -range 0x40000C10 0x40000C13 4 ReadWrite // INTFRCH0 -range 0x40000C14 0x40000C17 4 Read // INTFRCL0 -range 0x40000C18 0x40000C18 1 Read // IRLR0 -range 0x40000C19 0x40000C19 1 Read // IACKLPR0 -reserved 0x40000C1A 0x40000C40 -range 0x40000C41 0x40000C41 1 Read // ICR001 -range 0x40000C42 0x40000C42 1 Read // ICR002 -range 0x40000C43 0x40000C43 1 Read // ICR003 -range 0x40000C44 0x40000C44 1 Read // ICR004 -range 0x40000C45 0x40000C45 1 Read // ICR005 -range 0x40000C46 0x40000C46 1 Read // ICR006 -range 0x40000C47 0x40000C47 1 Read // ICR007 -range 0x40000C48 0x40000C48 1 ReadWrite // ICR008 -range 0x40000C49 0x40000C49 1 ReadWrite // ICR009 -range 0x40000C4A 0x40000C4A 1 ReadWrite // ICR010 -range 0x40000C4B 0x40000C4B 1 ReadWrite // ICR011 -range 0x40000C4C 0x40000C4C 1 ReadWrite // ICR012 -range 0x40000C4D 0x40000C4D 1 ReadWrite // ICR013 -range 0x40000C4E 0x40000C4E 1 ReadWrite // ICR014 -range 0x40000C4F 0x40000C4F 1 ReadWrite // ICR015 -range 0x40000C50 0x40000C50 1 ReadWrite // ICR016 -range 0x40000C51 0x40000C51 1 ReadWrite // ICR017 -range 0x40000C52 0x40000C52 1 ReadWrite // ICR018 -range 0x40000C53 0x40000C53 1 ReadWrite // ICR019 -range 0x40000C54 0x40000C54 1 ReadWrite // ICR020 -range 0x40000C55 0x40000C55 1 ReadWrite // ICR021 -range 0x40000C56 0x40000C56 1 ReadWrite // ICR022 -range 0x40000C57 0x40000C57 1 ReadWrite // ICR023 -range 0x40000C58 0x40000C58 1 ReadWrite // ICR024 -range 0x40000C59 0x40000C59 1 ReadWrite // ICR025 -range 0x40000C5A 0x40000C5A 1 ReadWrite // ICR026 -range 0x40000C5B 0x40000C5B 1 ReadWrite // ICR027 -range 0x40000C5C 0x40000C5C 1 ReadWrite // ICR028 -range 0x40000C5D 0x40000C5D 1 ReadWrite // ICR029 -range 0x40000C5E 0x40000C5E 1 ReadWrite // ICR030 -range 0x40000C5F 0x40000C5F 1 ReadWrite // ICR031 -range 0x40000C60 0x40000C60 1 ReadWrite // ICR032 -range 0x40000C61 0x40000C61 1 ReadWrite // ICR033 -range 0x40000C62 0x40000C62 1 ReadWrite // ICR034 -range 0x40000C63 0x40000C63 1 ReadWrite // ICR035 -range 0x40000C64 0x40000C64 1 ReadWrite // ICR036 -range 0x40000C65 0x40000C65 1 ReadWrite // ICR037 -range 0x40000C66 0x40000C66 1 ReadWrite // ICR038 -range 0x40000C67 0x40000C67 1 ReadWrite // ICR039 -range 0x40000C68 0x40000C68 1 ReadWrite // ICR040 -range 0x40000C69 0x40000C69 1 ReadWrite // ICR041 -range 0x40000C6A 0x40000C6A 1 ReadWrite // ICR042 -range 0x40000C6B 0x40000C6B 1 ReadWrite // ICR043 -range 0x40000C6C 0x40000C6C 1 ReadWrite // ICR044 -range 0x40000C6D 0x40000C6D 1 ReadWrite // ICR045 -range 0x40000C6E 0x40000C6E 1 ReadWrite // ICR046 -range 0x40000C6F 0x40000C6F 1 ReadWrite // ICR047 -range 0x40000C70 0x40000C70 1 ReadWrite // ICR048 -range 0x40000C71 0x40000C71 1 ReadWrite // ICR049 -range 0x40000C72 0x40000C72 1 ReadWrite // ICR050 -range 0x40000C73 0x40000C73 1 ReadWrite // ICR051 -range 0x40000C74 0x40000C74 1 ReadWrite // ICR052 -range 0x40000C75 0x40000C75 1 ReadWrite // ICR053 -range 0x40000C76 0x40000C76 1 ReadWrite // ICR054 -range 0x40000C77 0x40000C77 1 ReadWrite // ICR055 -range 0x40000C78 0x40000C78 1 ReadWrite // ICR056 -range 0x40000C79 0x40000C79 1 ReadWrite // ICR057 -range 0x40000C7A 0x40000C7A 1 ReadWrite // ICR058 -range 0x40000C7B 0x40000C7B 1 ReadWrite // ICR059 -range 0x40000C7C 0x40000C7C 1 ReadWrite // ICR060 -range 0x40000C7D 0x40000C7D 1 ReadWrite // ICR061 -range 0x40000C7E 0x40000C7E 1 ReadWrite // ICR062 -range 0x40000C7F 0x40000C7F 1 ReadWrite // ICR063 -reserved 0x40000C80 0x40000CDF -range 0x40000CE0 0x40000CE0 1 Read // SWIACK0 -reserved 0x40000CE1 0x40000CE3 -range 0x40000CE4 0x40000CE4 1 Read // L1IACK0 -reserved 0x40000CE5 0x40000CE7 -range 0x40000CE8 0x40000CE8 1 Read // L2IACK0 -reserved 0x40000CE9 0x40000CEB -range 0x40000CEC 0x40000CEC 1 Read // L3IACK0 -reserved 0x40000CED 0x40000CEF -range 0x40000CF0 0x40000CF0 1 Read // L4IACK0 -reserved 0x40000CF1 0x40000CF3 -range 0x40000CF4 0x40000CF4 1 Read // L5IACK0 -reserved 0x40000CF5 0x40000CF7 -range 0x40000CF8 0x40000CF8 1 Read // L6IACK0 -reserved 0x40000CF9 0x40000CFB -range 0x40000CFC 0x40000CFC 1 Read // L7IACK0 -reserved 0x40000CFD 0x40000CFF - -// Interrupt Controller Registers 1 -range 0x40000D00 0x40000D03 4 Read // IPRH1 -range 0x40000D04 0x40000D07 4 Read // IPRL1 -range 0x40000D08 0x40000D0B 4 ReadWrite // IMRH1 -range 0x40000D0C 0x40000D0F 4 ReadWrite // IMRL1 -range 0x40000D10 0x40000D13 4 ReadWrite // INTFRCH1 -range 0x40000D14 0x40000D17 4 Read // INTFRCL1 -range 0x40000D18 0x40000D18 1 Read // IRLR1 -range 0x40000D19 0x40000D19 1 Read // IACKLPR1 -reserved 0x40000D1A 0x40000D40 -range 0x40000D41 0x40000D41 1 Read // ICR101 -range 0x40000D42 0x40000D42 1 Read // ICR102 -range 0x40000D43 0x40000D43 1 Read // ICR103 -range 0x40000D44 0x40000D44 1 Read // ICR104 -range 0x40000D45 0x40000D45 1 Read // ICR105 -range 0x40000D46 0x40000D46 1 Read // ICR106 -range 0x40000D47 0x40000D47 1 Read // ICR107 -range 0x40000D48 0x40000D48 1 ReadWrite // ICR108 -range 0x40000D49 0x40000D49 1 ReadWrite // ICR109 -range 0x40000D4A 0x40000D4A 1 ReadWrite // ICR110 -range 0x40000D4B 0x40000D4B 1 ReadWrite // ICR111 -range 0x40000D4C 0x40000D4C 1 ReadWrite // ICR112 -range 0x40000D4D 0x40000D4D 1 ReadWrite // ICR113 -range 0x40000D4E 0x40000D4E 1 ReadWrite // ICR114 -range 0x40000D4F 0x40000D4F 1 ReadWrite // ICR115 -range 0x40000D50 0x40000D50 1 ReadWrite // ICR116 -range 0x40000D51 0x40000D51 1 ReadWrite // ICR117 -range 0x40000D52 0x40000D52 1 ReadWrite // ICR118 -range 0x40000D53 0x40000D53 1 ReadWrite // ICR119 -range 0x40000D54 0x40000D54 1 ReadWrite // ICR120 -range 0x40000D55 0x40000D55 1 ReadWrite // ICR121 -range 0x40000D56 0x40000D56 1 ReadWrite // ICR122 -range 0x40000D57 0x40000D57 1 ReadWrite // ICR123 -range 0x40000D58 0x40000D58 1 ReadWrite // ICR124 -range 0x40000D59 0x40000D59 1 ReadWrite // ICR125 -range 0x40000D5A 0x40000D5A 1 ReadWrite // ICR126 -range 0x40000D5B 0x40000D5B 1 ReadWrite // ICR127 -range 0x40000D5C 0x40000D5C 1 ReadWrite // ICR128 -range 0x40000D5D 0x40000D5D 1 ReadWrite // ICR129 -range 0x40000D5E 0x40000D5E 1 ReadWrite // ICR130 -range 0x40000D5F 0x40000D5F 1 ReadWrite // ICR131 -range 0x40000D60 0x40000D60 1 ReadWrite // ICR132 -range 0x40000D61 0x40000D61 1 ReadWrite // ICR133 -range 0x40000D62 0x40000D62 1 ReadWrite // ICR134 -range 0x40000D63 0x40000D63 1 ReadWrite // ICR135 -range 0x40000D64 0x40000D64 1 ReadWrite // ICR136 -range 0x40000D65 0x40000D65 1 ReadWrite // ICR137 -range 0x40000D66 0x40000D66 1 ReadWrite // ICR138 -range 0x40000D67 0x40000D67 1 ReadWrite // ICR139 -range 0x40000D68 0x40000D68 1 ReadWrite // ICR140 -range 0x40000D69 0x40000D69 1 ReadWrite // ICR141 -range 0x40000D6A 0x40000D6A 1 ReadWrite // ICR142 -range 0x40000D6B 0x40000D6B 1 ReadWrite // ICR143 -range 0x40000D6C 0x40000D6C 1 ReadWrite // ICR144 -range 0x40000D6D 0x40000D6D 1 ReadWrite // ICR145 -range 0x40000D6E 0x40000D6E 1 ReadWrite // ICR146 -range 0x40000D6F 0x40000D6F 1 ReadWrite // ICR147 -range 0x40000D70 0x40000D70 1 ReadWrite // ICR148 -range 0x40000D71 0x40000D71 1 ReadWrite // ICR149 -range 0x40000D72 0x40000D72 1 ReadWrite // ICR150 -range 0x40000D73 0x40000D73 1 ReadWrite // ICR151 -range 0x40000D74 0x40000D74 1 ReadWrite // ICR152 -range 0x40000D75 0x40000D75 1 ReadWrite // ICR153 -range 0x40000D76 0x40000D76 1 ReadWrite // ICR154 -range 0x40000D77 0x40000D77 1 ReadWrite // ICR155 -range 0x40000D78 0x40000D78 1 ReadWrite // ICR156 -range 0x40000D79 0x40000D79 1 ReadWrite // ICR157 -range 0x40000D7A 0x40000D7A 1 ReadWrite // ICR158 -range 0x40000D7B 0x40000D7B 1 ReadWrite // ICR159 -range 0x40000D7C 0x40000D7C 1 ReadWrite // ICR160 -range 0x40000D7D 0x40000D7D 1 ReadWrite // ICR161 -range 0x40000D7E 0x40000D7E 1 ReadWrite // ICR162 -range 0x40000D7F 0x40000D7F 1 ReadWrite // ICR163 -reserved 0x40000D80 0x40000DDF -range 0x40000DE0 0x40000DE0 1 Read // SWIACK1 -reserved 0x40000DE1 0x40000DE3 -range 0x40000DE4 0x40000DE4 1 Read // L1IACK1 -reserved 0x40000DE5 0x40000DE7 -range 0x40000DE8 0x40000DE8 1 Read // L2IACK1 -reserved 0x40000DE9 0x40000DEB -range 0x40000DEC 0x40000DEC 1 Read // L3IACK1 -reserved 0x40000DED 0x40000DEF -range 0x40000DF0 0x40000DF0 1 Read // L4IACK1 -reserved 0x40000DF1 0x40000DF3 -range 0x40000DF4 0x40000DF4 1 Read // L5IACK1 -reserved 0x40000DF5 0x40000DF7 -range 0x40000DF8 0x40000DF8 1 Read // L6IACK1 -reserved 0x40000DF9 0x40000DFB -range 0x40000DFC 0x40000DFC 1 Read // L7IACK1 -reserved 0x40000DFD 0x40001003 - -// Fast Ethernet Controllers Registers -range 0x40001004 0x40001007 4 ReadWrite // EIR -range 0x40001008 0x4000100B 4 ReadWrite // EIMR -reserved 0x4000100C 0x4000100F -range 0x40001010 0x40001013 4 ReadWrite // RDAR -range 0x40001014 0x40001017 4 ReadWrite // TDAR -reserved 0x40001018 0x40001023 -range 0x40001024 0x40001027 4 ReadWrite // ECR -reserved 0x40001028 0x4000103F -range 0x40001040 0x40001043 4 ReadWrite // MDATA -range 0x40001044 0x40001047 4 ReadWrite // MSCR -reserved 0x40001048 0x40001063 -range 0x40001064 0x40001067 4 ReadWrite // MIBC -reserved 0x40001068 0x40001083 -range 0x40001084 0x40001087 4 ReadWrite // RCR -reserved 0x40001088 0x400010C3 -range 0x400010C4 0x400010C7 4 ReadWrite // TCR -reserved 0x400010C8 0x400010E3 -range 0x400010E4 0x400010E7 4 ReadWrite // PALR -range 0x400010E8 0x400010EB 4 ReadWrite // PAUR -range 0x400010EC 0x400010EF 4 ReadWrite // OPD -reserved 0x400010F0 0x40001117 -range 0x40001118 0x4000111B 4 ReadWrite // IAUR -range 0x4000111C 0x4000111F 4 ReadWrite // IALR -range 0x40001120 0x40001123 4 ReadWrite // GAUR -range 0x40001124 0x40001127 4 ReadWrite // GALR -reserved 0x40001128 0x40001143 -range 0x40001144 0x40001147 4 ReadWrite // TFWR -reserved 0x40001148 0x4000114B -range 0x4000114C 0x4000114F 4 ReadWrite // FRBR -range 0x40001150 0x40001153 4 ReadWrite // FRSR -reserved 0x40001154 0x4000117F -range 0x40001180 0x40001183 4 ReadWrite // ERDSR -range 0x40001184 0x40001187 4 ReadWrite // ETDSR -range 0x40001188 0x4000118B 4 ReadWrite // EMRBR -reserved 0x4000118C 0x400FFFFF - -// GPIO Registers -range 0x40100000 0x40100000 1 ReadWrite // PODR_ADDR -range 0x40100001 0x40100001 1 ReadWrite // PODR_DATAH -range 0x40100002 0x40100002 1 ReadWrite // PODR_DATAL -range 0x40100003 0x40100003 1 ReadWrite // PODR_BUSCTL -range 0x40100004 0x40100004 1 ReadWrite // PODR_BS -range 0x40100005 0x40100005 1 ReadWrite // PODR_CS -range 0x40100006 0x40100006 1 ReadWrite // PODR_SDRAM -range 0x40100007 0x40100007 1 ReadWrite // PODR_FECI2C -range 0x40100008 0x40100008 1 ReadWrite // PODR_UARTH -range 0x40100009 0x40100009 1 ReadWrite // PODR_UARTL -range 0x4010000A 0x4010000A 1 ReadWrite // PODR_QSPI -range 0x4010000B 0x4010000B 1 ReadWrite // PODR_TIMER -range 0x4010000C 0x4010000C 1 ReadWrite // PODR_ETPU -reserved 0x4010000D 0x4010000F -range 0x40100010 0x40100010 1 ReadWrite // PDDR_ADDR -range 0x40100011 0x40100011 1 ReadWrite // PDDR_DATAH -range 0x40100012 0x40100012 1 ReadWrite // PDDR_DATAL -range 0x40100013 0x40100013 1 ReadWrite // PDDR_BUSCTL -range 0x40100014 0x40100014 1 ReadWrite // PDDR_BS -range 0x40100015 0x40100015 1 ReadWrite // PDDR_CS -range 0x40100016 0x40100016 1 ReadWrite // PDDR_SDRAM -range 0x40100017 0x40100017 1 ReadWrite // PDDR_FECI2C -range 0x40100018 0x40100018 1 ReadWrite // PDDR_UARTH -range 0x40100019 0x40100019 1 ReadWrite // PDDR_UARTL -range 0x4010001A 0x4010001A 1 ReadWrite // PDDR_QSPI -range 0x4010001B 0x4010001B 1 ReadWrite // PDDR_TIMER -range 0x4010001C 0x4010001C 1 ReadWrite // PDDR_ETPU -reserved 0x4010001D 0x4010001F -range 0x40100020 0x40100020 1 ReadWrite // PPDSDR_ADDR -range 0x40100021 0x40100021 1 ReadWrite // PPDSDR_DATAH -range 0x40100022 0x40100022 1 ReadWrite // PPDSDR_DATAL -range 0x40100023 0x40100023 1 ReadWrite // PPDSDR_BUSCTL -range 0x40100024 0x40100024 1 ReadWrite // PPDSDR_BS -range 0x40100025 0x40100025 1 ReadWrite // PPDSDR_CS -range 0x40100026 0x40100026 1 ReadWrite // PPDSDR_SDRAM -range 0x40100027 0x40100027 1 ReadWrite // PPDSDR_FECI2C -range 0x40100028 0x40100028 1 ReadWrite // PPDSDR_UARTH -range 0x40100029 0x40100029 1 ReadWrite // PPDSDR_UARTL -range 0x4010002A 0x4010002A 1 ReadWrite // PPDSDR_QSPI -range 0x4010002B 0x4010002B 1 ReadWrite // PPDSDR_TIMER -range 0x4010002C 0x4010002C 1 ReadWrite // PPDSDR_ETPU -reserved 0x4010002D 0x4010002F -range 0x40100030 0x40100030 1 ReadWrite // PCLRR_ADDR -range 0x40100031 0x40100031 1 ReadWrite // PCLRR_DATAH -range 0x40100032 0x40100032 1 ReadWrite // PCLRR_DATAL -range 0x40100033 0x40100033 1 ReadWrite // PCLRR_BUSCTL -range 0x40100034 0x40100034 1 ReadWrite // PCLRR_BS -range 0x40100035 0x40100035 1 ReadWrite // PCLRR_CS -range 0x40100036 0x40100036 1 ReadWrite // PCLRR_SDRAM -range 0x40100037 0x40100037 1 ReadWrite // PCLRR_FECI2C -range 0x40100038 0x40100038 1 ReadWrite // PCLRR_UARTH -range 0x40100039 0x40100039 1 ReadWrite // PCLRR_UARTL -range 0x4010003A 0x4010003A 1 ReadWrite // PCLRR_QSPI -range 0x4010003B 0x4010003B 1 ReadWrite // PCLRR_TIMER -range 0x4010003C 0x4010003C 1 ReadWrite // PCLRR_ETPU -reserved 0x4010003D 0x4010003F -range 0x40100040 0x40100040 1 ReadWrite // PAR_AD -reserved 0x40100041 0x40100041 -range 0x40100042 0x40100043 2 ReadWrite // PAR_BUSCTL -range 0x40100044 0x40100044 1 ReadWrite // PAR_BS -range 0x40100045 0x40100045 1 ReadWrite // PAR_CS -range 0x40100046 0x40100046 1 ReadWrite // PAR_SDRAM -range 0x40100047 0x40100047 1 ReadWrite // PAR_FECI2C -range 0x40100048 0x40100049 2 ReadWrite // PAR_UART -range 0x4010004A 0x4010004A 1 ReadWrite // PAR_QSPI -reserved 0x4010004B 0x4010004B -range 0x4010004C 0x4010004D 2 ReadWrite // PAR_TIMER -range 0x4010004E 0x4010004E 1 ReadWrite // PAR_ETPU -reserved 0x4010004F 0x4010004F -range 0x40100050 0x40100050 1 ReadWrite // DSCR_EIM -range 0x40100051 0x40100051 1 ReadWrite // DSCR_ETPU -range 0x40100052 0x40100052 1 ReadWrite // DSCR_FECI2C -range 0x40100053 0x40100053 1 ReadWrite // DSCR_UART -range 0x40100054 0x40100054 1 ReadWrite // DSCR_QSPI -range 0x40100055 0x40100055 1 ReadWrite // DSCR_TIMER -reserved 0x40100056 0x4010FFFF - -// Reset controller Module Registers -range 0x40110000 0x40110000 1 ReadWrite // RCR -range 0x40110001 0x40110001 1 Read // RSR -reserved 0x40110002 0x40110003 - -// Chip Configuration Module Registers -range 0x40110004 0x40110005 2 ReadWrite // CCR -reserved 0x40110006 0x40110006 -range 0x40110007 0x40110007 1 ReadWrite // LPCR -range 0x40110008 0x40110009 2 ReadWrite // RCON -range 0x4011000A 0x4011000A 1 ReadWrite // CIR -reserved 0x4011000B 0x4011FFFF - -// Clock Module Registers -range 0x40120000 0x40120003 4 ReadWrite // SYNCR -range 0x40120004 0x40120007 4 Read // SYNSR -reserved 0x40120008 0x4012FFFF - -// Edge Port Registers -range 0x40130000 0x40130001 2 ReadWrite // EPPAR -range 0x40130002 0x40130002 1 ReadWrite // EPDDR -range 0x40130003 0x40130003 1 ReadWrite // EPIER -range 0x40130004 0x40130004 1 ReadWrite // EPDR -range 0x40130005 0x40130005 1 Read // EPPDR -range 0x40130006 0x40130006 1 ReadWrite // EPFR -reserved 0x40130007 0x4013FFFF - -// Watchdog Timer Module Registers -range 0x40140000 0x40140001 2 ReadWrite // WCR -range 0x40140002 0x40140003 2 ReadWrite // WMR -range 0x40140004 0x40140005 2 Read // WCNTR -range 0x40140006 0x40140007 2 ReadWrite // WSR -reserved 0x40140008 0x4014FFFF - -// Programmable Interrupt Timer 0 Modules Registers -range 0x40150000 0x40150001 2 ReadWrite // PCSR0 -range 0x40150002 0x40150003 2 ReadWrite // PMR0 -range 0x40150004 0x40150005 2 Read // PCNTR0 -reserved 0x40150006 0x4015FFFF - -// Programmable Interrupt Timer 1 Modules Registers -range 0x40160000 0x40160001 2 ReadWrite // PCSR1 -range 0x40160002 0x40160003 2 ReadWrite // PMR1 -range 0x40160004 0x40160005 2 Read // PCNTR1 -reserved 0x40160006 0x4016FFFF - -// Programmable Interrupt Timer 2 Modules Registers -range 0x40170000 0x40170001 2 ReadWrite // PCSR2 -range 0x40170002 0x40170003 2 ReadWrite // PMR2 -range 0x40170004 0x40170005 2 Read // PCNTR2 -reserved 0x40170006 0x4017FFFF - -// Programmable Interrupt Timer 3 Modules Registers -range 0x40180000 0x40180001 2 ReadWrite // PCSR3 -range 0x40180002 0x40180003 2 ReadWrite // PMR3 -range 0x40180004 0x40180005 2 Read // PCNTR3 -reserved 0x40180006 0x4018FFFF - -// Message Digest Hardware Accelerator Registers -range 0x40190000 0x40190003 4 ReadWrite // MDMR -range 0x40190004 0x40190007 4 ReadWrite // MDCR -range 0x40190008 0x4019000B 4 Write // MDCMR -range 0x4019000C 0x4019000F 4 Read // MDSR -range 0x40190010 0x40190013 4 Read // MDISR -range 0x40190014 0x40190017 4 ReadWrite // MDIMR -reserved 0x40190018 0x4019001B -range 0x4019001C 0x4019001F 4 ReadWrite // MDDSR -range 0x40190020 0x40190023 4 ReadWrite // MDIN -reserved 0x40190024 0x4019002F -range 0x40190030 0x40190033 4 ReadWrite // MDA0 -range 0x40190034 0x40190037 4 ReadWrite // MDB0 -range 0x40190038 0x4019003B 4 ReadWrite // MDC0 -range 0x4019003C 0x4019003F 4 ReadWrite // MDD0 -range 0x40190040 0x40190043 4 ReadWrite // MDE0 -range 0x40190044 0x40190047 4 ReadWrite // MDMDS -reserved 0x40190048 0x4019006F -range 0x40190070 0x40190073 4 ReadWrite // MDA1 -range 0x40190074 0x40190077 4 ReadWrite // MDB1 -range 0x40190078 0x4019007B 4 ReadWrite // MDC1 -range 0x4019007C 0x4019007F 4 ReadWrite // MDD1 -range 0x40190080 0x40190083 4 ReadWrite // MDE1 -reserved 0x40190084 0x4019FFFF - -// Random Number Generator Registers -range 0x401A0000 0x401A0003 4 ReadWrite // RNGCR -range 0x401A0004 0x401A0007 4 Read // RNGSR -range 0x401A0008 0x401A000B 4 Write // RNGER -range 0x401A000C 0x401A000F 4 Read // RNGOUT -reserved 0x401A0010 0x401AFFFF - -// Symmetric Key Hardware Accelerator Registers -range 0x401B0000 0x401B0003 4 ReadWrite // SKMR -range 0x401B0004 0x401B0007 4 ReadWrite // SKCR -range 0x401B0008 0x401B000B 4 ReadWrite // SKCMR -range 0x401B000C 0x401B000F 4 Read // SKSR -range 0x401B0010 0x401B0013 4 Read // SKESR -range 0x401B0014 0x401B0017 4 ReadWrite // SKESMR -range 0x401B0018 0x401B001B 4 ReadWrite // SKKSR -range 0x401B001C 0x401B001F 4 ReadWrite // SKDSR -range 0x401B0020 0x401B0023 4 ReadWrite // SKIN -range 0x401B0024 0x401B0027 4 ReadWrite // SKOUT -reserved 0x401B0028 0x401B002F -range 0x401B0030 0x401B0033 4 Write // SKK1 -range 0x401B0034 0x401B0037 4 Write // SKK2 -range 0x401B0038 0x401B003B 4 Write // SKK3 -range 0x401B003C 0x401B003F 4 Write // SKK4 -range 0x401B0040 0x401B0043 4 Write // SKK5 -range 0x401B0044 0x401B0047 4 Write // SKK6 -reserved 0x401B0048 0x401BFFFF - -// Flex Controller Area Network 1 Registers -range 0x401C0000 0x401C0003 4 ReadWrite // CANMCR1 -range 0x401C0004 0x401C0007 4 ReadWrite // CANCTRL1 -range 0x401C0008 0x401C000B 4 ReadWrite // TIMER1 -reserved 0x401C000C 0x401C000F -range 0x401C0010 0x401C0013 4 ReadWrite // RXGMASK1 -range 0x401C0014 0x401C0017 4 ReadWrite // RX14MASK1 -range 0x401C0018 0x401C001B 4 ReadWrite // RX15MASK1 -range 0x401C001C 0x401C001F 4 ReadWrite // ERRCNT1 -range 0x401C0020 0x401C0023 4 ReadWrite // ERRSTAT1 -reserved 0x401C0024 0x401C0029 -range 0x401C002A 0x401C002B 2 ReadWrite // IMASK1 -reserved 0x401C002C 0x401C0031 -range 0x401C0032 0x401C0033 2 ReadWrite // IFLAG1 -reserved 0x401C0034 0x401CFFFF - -// Enhanced Time Process Unit Registers -range 0x401D0000 0x401D0003 4 ReadWrite // ETPU_MCR -range 0x401D0004 0x401D0007 4 ReadWrite // ETPU_CDCR -reserved 0x401D0008 0x401D000B -range 0x401D000C 0x401D000F 4 ReadWrite // ETPU_MISCCMPR -reserved 0x401D0010 0x401D0013 -range 0x401D0014 0x401D0017 4 ReadWrite // ETPU_ECR -reserved 0x401D0018 0x401D001F -range 0x401D0020 0x401D0023 4 ReadWrite // ETPU_TBCR -range 0x401D0024 0x401D0027 4 ReadWrite // ETPU_TB1R -range 0x401D0028 0x401D002B 4 ReadWrite // ETPU_TB2R -reserved 0x401D002C 0x401D01FF -range 0x401D0200 0x401D0203 4 ReadWrite // ETPU_CISR -reserved 0x401D0204 0x401D020F -range 0x401D0210 0x401D0213 4 ReadWrite // ETPU_CDTRSR -reserved 0x401D0214 0x401D021F -range 0x401D0220 0x401D0223 4 ReadWrite // ETPU_CIOSR -reserved 0x401D0224 0x401D022F -range 0x401D0230 0x401D0233 4 ReadWrite // ETPU_CDTROSR -reserved 0x401D0234 0x401D023F -range 0x401D0240 0x401D0243 4 ReadWrite // ETPU_CIER -reserved 0x401D0244 0x401D024F -range 0x401D0250 0x401D0253 4 ReadWrite // ETPU_CDTRER -reserved 0x401D0254 0x401D027F -range 0x401D0280 0x401D0283 4 Read // ETPU_CPSSR -reserved 0x401D0284 0x401D028F -range 0x401D0290 0x401D0293 4 Read // ETPU_CSSR -reserved 0x401D0294 0x401D03FF -range 0x401D0400 0x401D0403 4 ReadWrite // ETPU_C0CR -range 0x401D0404 0x401D0407 4 ReadWrite // ETPU_C0SCR -range 0x401D0408 0x401D040B 4 ReadWrite // ETPU_C0HSRR -reserved 0x401D040C 0x401D040F -range 0x401D0410 0x401D0413 4 ReadWrite // ETPU_C1CR -range 0x401D0414 0x401D0417 4 ReadWrite // ETPU_C1SCR -range 0x401D0418 0x401D041B 4 ReadWrite // ETPU_C1HSRR -reserved 0x401D041C 0x401D041F -range 0x401D0420 0x401D0423 4 ReadWrite // ETPU_C2CR -range 0x401D0424 0x401D0427 4 ReadWrite // ETPU_C2SCR -range 0x401D0428 0x401D042B 4 ReadWrite // ETPU_C2HSRR -reserved 0x401D042C 0x401D042F -range 0x401D0430 0x401D0433 4 ReadWrite // ETPU_C3CR -range 0x401D0434 0x401D0437 4 ReadWrite // ETPU_C3SCR -range 0x401D0438 0x401D043B 4 ReadWrite // ETPU_C3HSRR -reserved 0x401D043C 0x401D043F -range 0x401D0440 0x401D0443 4 ReadWrite // ETPU_C4CR -range 0x401D0444 0x401D0447 4 ReadWrite // ETPU_C4SCR -range 0x401D0448 0x401D044B 4 ReadWrite // ETPU_C4HSRR -reserved 0x401D044C 0x401D044F -range 0x401D0450 0x401D0453 4 ReadWrite // ETPU_C5CR -range 0x401D0454 0x401D0457 4 ReadWrite // ETPU_C5SCR -range 0x401D0458 0x401D045B 4 ReadWrite // ETPU_C5HSRR -reserved 0x401D045C 0x401D045F -range 0x401D0460 0x401D0463 4 ReadWrite // ETPU_C6CR -range 0x401D0464 0x401D0467 4 ReadWrite // ETPU_C6SCR -range 0x401D0468 0x401D046B 4 ReadWrite // ETPU_C6HSRR -reserved 0x401D046C 0x401D046F -range 0x401D0470 0x401D0473 4 ReadWrite // ETPU_C7CR -range 0x401D0474 0x401D0477 4 ReadWrite // ETPU_C7SCR -range 0x401D0478 0x401D047B 4 ReadWrite // ETPU_C7HSRR -reserved 0x401D047C 0x401D047F -range 0x401D0480 0x401D0483 4 ReadWrite // ETPU_C8CR -range 0x401D0484 0x401D0487 4 ReadWrite // ETPU_C8SCR -range 0x401D0488 0x401D048B 4 ReadWrite // ETPU_C8HSRR -reserved 0x401D048C 0x401D048F -range 0x401D0490 0x401D0493 4 ReadWrite // ETPU_C9CR -range 0x401D0494 0x401D0497 4 ReadWrite // ETPU_C9SCR -range 0x401D0498 0x401D049B 4 ReadWrite // ETPU_C9HSRR -reserved 0x401D049C 0x401D049F -range 0x401D04A0 0x401D04A3 4 ReadWrite // ETPU_C10CR -range 0x401D04A4 0x401D04A7 4 ReadWrite // ETPU_C10SCR -range 0x401D04A8 0x401D04AB 4 ReadWrite // ETPU_C10HSRR -reserved 0x401D04AC 0x401D04AF -range 0x401D04B0 0x401D04B3 4 ReadWrite // ETPU_C11CR -range 0x401D04B4 0x401D04B7 4 ReadWrite // ETPU_C11SCR -range 0x401D04B8 0x401D04BB 4 ReadWrite // ETPU_C11HSRR -reserved 0x401D04BC 0x401D04BF -range 0x401D04C0 0x401D04C3 4 ReadWrite // ETPU_C12CR -range 0x401D04C4 0x401D04C7 4 ReadWrite // ETPU_C12SCR -range 0x401D04C8 0x401D04CB 4 ReadWrite // ETPU_C12HSRR -reserved 0x401D04CC 0x401D04CF -range 0x401D04D0 0x401D04D3 4 ReadWrite // ETPU_C13CR -range 0x401D04D4 0x401D04D7 4 ReadWrite // ETPU_C13SCR -range 0x401D04D8 0x401D04DB 4 ReadWrite // ETPU_C13HSRR -reserved 0x401D04DC 0x401D04DF -range 0x401D04E0 0x401D04E3 4 ReadWrite // ETPU_C14CR -range 0x401D04E4 0x401D04E7 4 ReadWrite // ETPU_C14SCR -range 0x401D04E8 0x401D04EB 4 ReadWrite // ETPU_C14HSRR -reserved 0x401D04EC 0x401D04EF -range 0x401D04F0 0x401D04F3 4 ReadWrite // ETPU_C15CR -range 0x401D04F4 0x401D04F7 4 ReadWrite // ETPU_C15SCR -range 0x401D04F8 0x401D04FB 4 ReadWrite // ETPU_C15HSRR -reserved 0x401D04FC 0x401D04FF -range 0x401D0500 0x401D0503 4 ReadWrite // ETPU_C16CR -range 0x401D0504 0x401D0507 4 ReadWrite // ETPU_C16SCR -range 0x401D0508 0x401D050B 4 ReadWrite // ETPU_C16HSRR -reserved 0x401D050C 0x401D050F -range 0x401D0510 0x401D0513 4 ReadWrite // ETPU_C17CR -range 0x401D0514 0x401D0517 4 ReadWrite // ETPU_C17SCR -range 0x401D0518 0x401D051B 4 ReadWrite // ETPU_C17HSRR -reserved 0x401D051C 0x401D051F -range 0x401D0520 0x401D0523 4 ReadWrite // ETPU_C18CR -range 0x401D0524 0x401D0527 4 ReadWrite // ETPU_C18SCR -range 0x401D0528 0x401D052B 4 ReadWrite // ETPU_C18HSRR -reserved 0x401D052C 0x401D052F -range 0x401D0530 0x401D0533 4 ReadWrite // ETPU_C19CR -range 0x401D0534 0x401D0537 4 ReadWrite // ETPU_C19SCR -range 0x401D0538 0x401D053B 4 ReadWrite // ETPU_C19HSRR -reserved 0x401D053C 0x401D053F -range 0x401D0540 0x401D0543 4 ReadWrite // ETPU_C20CR -range 0x401D0544 0x401D0547 4 ReadWrite // ETPU_C20SCR -range 0x401D0548 0x401D054B 4 ReadWrite // ETPU_C20HSRR -reserved 0x401D054C 0x401D054F -range 0x401D0550 0x401D0553 4 ReadWrite // ETPU_C21CR -range 0x401D0554 0x401D0557 4 ReadWrite // ETPU_C21SCR -range 0x401D0558 0x401D055B 4 ReadWrite // ETPU_C21HSRR -reserved 0x401D055C 0x401D055F -range 0x401D0560 0x401D0563 4 ReadWrite // ETPU_C22CR -range 0x401D0564 0x401D0567 4 ReadWrite // ETPU_C22SCR -range 0x401D0568 0x401D056B 4 ReadWrite // ETPU_C22HSRR -reserved 0x401D056C 0x401D056F -range 0x401D0570 0x401D0573 4 ReadWrite // ETPU_C23CR -range 0x401D0574 0x401D0577 4 ReadWrite // ETPU_C23SCR -range 0x401D0578 0x401D057B 4 ReadWrite // ETPU_C23HSRR -reserved 0x401D057C 0x401D057F -range 0x401D0580 0x401D0583 4 ReadWrite // ETPU_C24CR -range 0x401D0584 0x401D0587 4 ReadWrite // ETPU_C24SCR -range 0x401D0588 0x401D058B 4 ReadWrite // ETPU_C24HSRR -reserved 0x401D058C 0x401D058F -range 0x401D0590 0x401D0593 4 ReadWrite // ETPU_C25CR -range 0x401D0594 0x401D0597 4 ReadWrite // ETPU_C25SCR -range 0x401D0598 0x401D059B 4 ReadWrite // ETPU_C25HSRR -reserved 0x401D059C 0x401D059F -range 0x401D05A0 0x401D05A3 4 ReadWrite // ETPU_C26CR -range 0x401D05A4 0x401D05A7 4 ReadWrite // ETPU_C26SCR -range 0x401D05A8 0x401D05AB 4 ReadWrite // ETPU_C26HSRR -reserved 0x401D05AC 0x401D05AF -range 0x401D05B0 0x401D05B3 4 ReadWrite // ETPU_C27CR -range 0x401D05B4 0x401D05B7 4 ReadWrite // ETPU_C27SCR -range 0x401D05B8 0x401D05BB 4 ReadWrite // ETPU_C27HSRR -reserved 0x401D05BC 0x401D05BF -range 0x401D05C0 0x401D05C3 4 ReadWrite // ETPU_C28CR -range 0x401D05C4 0x401D05C7 4 ReadWrite // ETPU_C28SCR -range 0x401D05C8 0x401D05CB 4 ReadWrite // ETPU_C28HSRR -reserved 0x401D05CC 0x401D05CF -range 0x401D05D0 0x401D05D3 4 ReadWrite // ETPU_C29CR -range 0x401D05D4 0x401D05D7 4 ReadWrite // ETPU_C29SCR -range 0x401D05D8 0x401D05DB 4 ReadWrite // ETPU_C29HSRR -reserved 0x401D05DC 0x401D05DF -range 0x401D05E0 0x401D05E3 4 ReadWrite // ETPU_C30CR -range 0x401D05E4 0x401D05E7 4 ReadWrite // ETPU_C30SCR -range 0x401D05E8 0x401D05EB 4 ReadWrite // ETPU_C30HSRR -reserved 0x401D05EC 0x401D05EF -range 0x401D05F0 0x401D05F3 4 ReadWrite // ETPU_C31CR -range 0x401D05F4 0x401D05F7 4 ReadWrite // ETPU_C31SCR -range 0x401D05F8 0x401D05FB 4 ReadWrite // ETPU_C31HSRR -reserved 0x401D05FC 0x401EFFFF - -// Flex Controller Area Network 2 Registers -range 0x401F0000 0x401F0003 4 ReadWrite // CANMCR2 -range 0x401F0004 0x401F0007 4 ReadWrite // CANCTRL2 -range 0x401F0008 0x401F000B 4 ReadWrite // TIMER2 -reserved 0x401F000C 0x401F000F -range 0x401F0010 0x401F0013 4 ReadWrite // RXGMASK2 -range 0x401F0014 0x401F0017 4 ReadWrite // RX14MASK2 -range 0x401F0018 0x401F001B 4 ReadWrite // RX15MASK2 -range 0x401F001C 0x401F001F 4 ReadWrite // ERRCNT2 -range 0x401F0020 0x401F0023 4 ReadWrite // ERRSTAT2 -reserved 0x401F0024 0x401F0029 -range 0x401F002A 0x401F002B 2 ReadWrite // IMASK2 -reserved 0x401F002C 0x401F0031 -range 0x401F0032 0x401F0033 2 ReadWrite // IFLAG2 -reserved 0x401F0034 0x401FFFFF diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/ram.lcf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/ram.lcf deleted file mode 100644 index 57e61d9fd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/ram.lcf +++ /dev/null @@ -1,121 +0,0 @@ -# -# FreeModbus Libary: MCF5235 Demo Application -# Copyright (C) 2007 Christian Walter -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# File: $Id: ram.lcf,v 1.1 2007/02/19 00:56:14 wolti Exp $ -# - -MEMORY -{ - ext_flash (RWX) : ORIGIN = 0x00000000, LENGTH = 0x0 - sdram (RWX) : ORIGIN = 0x10000000, LENGTH = 0x0 - vector_ram (RWX) : ORIGIN = 0x10000000, LENGTH = 0x0 - user (RWX) : ORIGIN = 0x10000500, LENGTH = 0x0 - sram (RWX) : ORIGIN = 0x20000000, LENGTH = 0x0 - ipsbar (RWX) : ORIGIN = 0x40000000, LENGTH = 0x0 -} - -SECTIONS -{ - .sdram : {} > sdram - .vector_ram : {} > vector_ram - .ipsbar : {} > ipsbar - .sram : {} > sram - .ext_flash : {} > ext_flash - - .vectors : - { - . = ALIGN (0x4); - } > user - - .text : - { - . = ALIGN (0x4); - *(.text) - . = ALIGN (0x4); - *(.rodata) - . = ALIGN (0x4); - } >> user - - .data : - { - ___sinit__ = .; - STATICINIT - - __START_DATA = .; - *(.data) - __END_DATA = .; - - __START_SDATA = .; - *(.sdata) - __END_SDATA = .; - __SDA_BASE = .; - . = ALIGN (0x4); - - } >> user - - .bss : - { - __START_SBSS = .; - *(.sbss) - *(SCOMMON) - __END_SBSS = .; - - __START_BSS = .; - *(.bss) - *(COMMON) - __END_BSS = .; - . = ALIGN(0x4); - } >> user - - .custom : - { - - ___HEAP_START = .; - ___HEAP_END = ___HEAP_START + 0x10000; - ___SP_END = ___HEAP_END; - ___SP_INIT = ___SP_END + 0x4000; - - . = ALIGN (0x4); - } >> user - - ___IPSBAR = ADDR(.ipsbar); - ___VECTOR_RAM = ADDR(.vector_ram); - - ___SDRAM = ADDR(.sdram); - ___SDRAM_SIZE = 0x01000000; - - ___SRAM = ADDR(.sram); - ___SRAM_SIZE = 0x00010000; - - ___EXT_FLASH = ADDR(.ext_flash); - ___EXT_FLASH_SIZE = 0x00200000; - - ___heap_addr = ___HEAP_START; - ___heap_size = 0x10000; - __SP_INIT = ___SP_INIT; - __S_romp = 0x0; - -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/rom.lcf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/rom.lcf deleted file mode 100644 index 9f33c3792..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/support/rom.lcf +++ /dev/null @@ -1,123 +0,0 @@ -# -# FreeModbus Libary: MCF5235 Demo Application -# Copyright (C) 2007 Christian Walter -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. The name of the author may not be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# File: $Id: rom.lcf,v 1.1 2007/02/19 00:56:14 wolti Exp $ -# - -MEMORY -{ - ext_flash (RWX) : ORIGIN = 0x00000000, LENGTH = 0x0 - sdram (RWX) : ORIGIN = 0x10000000, LENGTH = 0x0 - vector_ram (RWX) : ORIGIN = 0x10000000, LENGTH = 0x0 - user (RWX) : ORIGIN = 0x10000500, LENGTH = 0x0 - sram (RWX) : ORIGIN = 0x20000000, LENGTH = 0x0 - ipsbar (RWX) : ORIGIN = 0x40000000, LENGTH = 0x0 -} - -SECTIONS -{ - - .sdram : {} > sdram - .vector_ram : {} > vector_ram - .ipsbar : {} > ipsbar - .sram : {} > sram - - .boot_flash : - { - vectors.s (.text) - *(.text) - *(.rodata) - .= ALIGN(0x4); - } > ext_flash - - __end_of_text = .; - - ___DATA_ROM = __end_of_text; - - ___DATA_RAM = ADDR(user); - - .sys_sram : AT(___DATA_ROM) - { - __START_DATA = .; - *(.data) - __END_DATA = .; - - __START_SDATA = .; - *(.sdata) - __END_SDATA = .; - - __SDA_BASE = .; - .= ALIGN(0x4); - } > user - - .uninitialized_data : - { - __START_SBSS = .; - *(.sbss) - *(SCOMMON) - __END_SBSS = .; - - __START_BSS = .; - *(.bss) - *(COMMON) - __END_BSS = .; - - . = ALIGN (0x4); - - ___HEAP_START = .; - ___HEAP_END = ___HEAP_START + 0x10000; - ___SP_END = ___HEAP_END; - ___SP_INIT = ___SP_END + 0x1000; - - . = ALIGN(0x4); - } >> user - - _romp_at = ___DATA_ROM + SIZEOF(.sys_sram); - .romp : AT(_romp_at) - { - __S_romp = _romp_at; - WRITEW(___DATA_ROM); - WRITEW(ADDR(.sys_sram)); - WRITEW(SIZEOF(.sys_sram)); - WRITEW(0); - WRITEW(0); - WRITEW(0); - } - - - ___IPSBAR = ADDR(.ipsbar); - ___VECTOR_RAM = ADDR(.vector_ram); - ___SDRAM = ADDR(.sdram); - ___SDRAM_SIZE = 0x01000000; - ___SRAM = ADDR(.sram); - ___SRAM_SIZE = 0x00010000; - ___EXT_FLASH = ADDR(.boot_flash); - ___EXT_FLASH_SIZE = 0x00200000; - ___heap_addr = ___HEAP_START; - ___heap_size = 0x10000; - __SP_INIT = ___SP_INIT; - -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/system/hwinit.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/system/hwinit.c deleted file mode 100644 index bd43c29d8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/system/hwinit.c +++ /dev/null @@ -1,250 +0,0 @@ -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include "m523xbcc.h" - -void mcf523x_init( void ); -void mcf523x_wtm_init( void ); -void mcf523x_pll_init( void ); -void mcf523x_scm_init( void ); -void mcf523x_gpio_init( void ); -void mcf523x_cs_init( void ); -void mcf523x_sdram_init( void ); -void mcf523x_flexcan_init( void ); - -void -mcf523x_init( void ) -{ - extern char __DATA_ROM[]; - extern char __DATA_RAM[]; - extern char __DATA_END[]; - extern char __BSS_START[]; - extern char __BSS_END[]; - extern uint32 VECTOR_TABLE[]; - extern uint32 __VECTOR_RAM[]; - register uint32 n; - - mcf523x_flexcan_init( ); - mcf523x_wtm_init( ); - mcf523x_pll_init( ); - mcf523x_gpio_init( ); - mcf523x_scm_init( ); - mcf523x_cs_init( ); - mcf523x_sdram_init( ); - - /* Turn Instruction Cache ON */ - mcf5xxx_wr_cacr( 0 - | MCF5XXX_CACR_CENB - | MCF5XXX_CACR_CINV - | MCF5XXX_CACR_DISD | MCF5XXX_CACR_CEIB | MCF5XXX_CACR_CLNF_00 ); - - - /* Copy the vector table to RAM */ - if( __VECTOR_RAM != VECTOR_TABLE ) - { - for( n = 0; n < 256; n++ ) - __VECTOR_RAM[n] = VECTOR_TABLE[n]; - } - mcf5xxx_wr_vbr( ( uint32 ) __VECTOR_RAM ); - -} - -void -mcf523x_wtm_init( void ) -{ - /* - * Disable Software Watchdog Timer - */ - MCF_WTM_WCR = 0; -} - -void -mcf523x_pll_init( void ) -{ - /* - * Multiply 25Mhz reference crystal to acheive system clock of 150Mhz - */ - - MCF_FMPLL_SYNCR = MCF_FMPLL_SYNCR_MFD( 1 ) | MCF_FMPLL_SYNCR_RFD( 0 ); - - while( !( MCF_FMPLL_SYNSR & MCF_FMPLL_SYNSR_LOCK ) ) - { - }; -} - -void -mcf523x_scm_init( void ) -{ - /* - * Enable on-chip modules to access internal SRAM - */ - MCF_SCM_RAMBAR = ( 0 | MCF_SCM_RAMBAR_BA( SRAM_ADDRESS >> 16 ) | MCF_SCM_RAMBAR_BDE ); -} - -void -mcf523x_gpio_init( void ) -{ - - /* - * When booting from external Flash, the port-size is less than - * the port-size of SDRAM. In this case it is necessary to enable - * Data[15:0] on Port Address/Data. - */ - MCF_GPIO_PAR_AD = ( 0 - | MCF_GPIO_PAR_AD_PAR_ADDR23 - | MCF_GPIO_PAR_AD_PAR_ADDR22 - | MCF_GPIO_PAR_AD_PAR_ADDR21 | MCF_GPIO_PAR_AD_PAR_DATAL ); - - /* - * Initialize PAR to enable SDRAM signals - */ - MCF_GPIO_PAR_SDRAM = 0x3F; - - /* - * Initialize PAR to enable Ethernet signals - */ - MCF_GPIO_PAR_FECI2C = 0xF0; -} - -void -mcf523x_sdram_init( void ) -{ - int i; - - /* - * Check to see if the SDRAM has already been initialized - * by a run control tool - */ - if( !( MCF_SDRAMC_DACR0 & MCF_SDRAMC_DACR0_RE ) ) - { - /* Initialize DRAM Control Register: DCR */ - MCF_SDRAMC_DCR = ( MCF_SDRAMC_DCR_RTIM( 1 ) | - MCF_SDRAMC_DCR_RC( ( 15 * FSYS_2 ) >> 4 ) ); - - /* Initialize DACR0 */ - MCF_SDRAMC_DACR0 = ( MCF_SDRAMC_DACR0_BA( SDRAM_ADDRESS >> 18UL ) | - MCF_SDRAMC_DACR0_CASL( 1 ) | - MCF_SDRAMC_DACR0_CBM( 3 ) | - MCF_SDRAMC_DACR0_PS( 0 ) ); - - /* - * Initialize DMR0 - */ - MCF_SDRAMC_DMR0 = ( 0 | MCF_SDRAMC_DMR_BAM_16M | MCF_SDRAMC_DMR0_V ); - - /* - * Set IP (bit 3) in DACR - */ - MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_IP; - - /* - * Wait 30ns to allow banks to precharge - */ - for( i = 0; i < 5; i++ ) - { -#ifndef __MWERKS__ - asm( " nop" ); -#else - asm( nop ); -#endif - } - - /* - * Write to this block to initiate precharge - */ - *( uint32 * ) ( SDRAM_ADDRESS ) = 0xA5A59696; - - /* - * Set RE (bit 15) in DACR - */ - MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_RE; - - /* - * Wait for at least 8 auto refresh cycles to occur - */ - for( i = 0; i < 2000; i++ ) - { -#ifndef __MWERKS__ - asm( " nop" ); -#else - asm( nop ); -#endif - } - - /* - * Finish the configuration by issuing the IMRS. - */ - MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_MRS; - - /* - * Write to the SDRAM Mode Register - */ - *( uint32 * ) ( SDRAM_ADDRESS + 0x400 ) = 0xA5A59696; - } - -} - - -void -mcf523x_cs_init( void ) -{ - /* - * ChipSelect 0 - External Flash - */ - MCF_CS_CSAR0 = MCF_CS_CSAR_BA( EXT_FLASH_ADDRESS ); - MCF_CS_CSCR0 = ( 0 | MCF_CS_CSCR_IWS( 6 ) | MCF_CS_CSCR_AA | MCF_CS_CSCR_PS_16 ); - MCF_CS_CSMR0 = MCF_CS_CSMR_BAM_2M | MCF_CS_CSMR_V; -} - -void -mcf523x_flexcan_init( void ) -{ - - /* FlexCAN controller 0 disabled (CANMCR0[MDIS]=1) */ - MCF_CAN_IMASK0 = 0; - MCF_CAN_RXGMASK0 = MCF_CAN_RXGMASK_MI( 0x1fffffff ); - MCF_CAN_RX14MASK0 = MCF_CAN_RX14MASK_MI( 0x1fffffff ); - MCF_CAN_RX15MASK0 = MCF_CAN_RX15MASK_MI( 0x1fffffff ); - MCF_CAN_CANCTRL0 = 0; - MCF_CAN_CANMCR0 = - MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT | - MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf ); - - /* FlexCAN controller 1 disabled (CANMCR1[MDIS]=1) */ - MCF_CAN_IMASK1 = 0; - MCF_CAN_RXGMASK1 = MCF_CAN_RXGMASK_MI( 0x1fffffff ); - MCF_CAN_RX14MASK1 = MCF_CAN_RX14MASK_MI( 0x1fffffff ); - MCF_CAN_RX15MASK1 = MCF_CAN_RX15MASK_MI( 0x1fffffff ); - MCF_CAN_CANCTRL1 = 0; - MCF_CAN_CANMCR1 = - MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT | - MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/system/interrupts.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/system/interrupts.c deleted file mode 100644 index 406da809e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/system/interrupts.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include "m523xbcc.h" - -void -exception_handler( void *framep ) -{ - ( void )framep; -} - -__interrupt__ void -irq_handler( void ) -{ - /* - * This is the catch all interrupt handler for all user defined - * interrupts. To create specific handlers, create a new interrupt - * handler and change vectors.s to point to the new handler. - */ -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/system/mcf523x_lo.s b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/system/mcf523x_lo.s deleted file mode 100644 index 0209b4eca..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/system/mcf523x_lo.s +++ /dev/null @@ -1,353 +0,0 @@ -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** - */ - -#ifdef _UNDERSCORE_ -#define exception_handler _exception_handler -#define mcf523x_init _mcf523x_init -#define _start __start -#endif - - .extern ___IPSBAR - .extern ___SRAM - .extern ___SP_INIT - .extern ___SRAM_SIZE - .extern exception_handler - .extern mcf5xxx_wr_rambar0 - .extern mcf5xxx_wr_rambar1 - .extern mcf523x_init - .extern _start - - .global asm_startmeup - .global _asm_startmeup - .global asm_exception_handler - .global _asm_exception_handler - .global cpu_cache_flush - .global _cpu_cache_flush - .global mcf5xxx_wr_cacr - .global _mcf5xxx_wr_cacr - .global mcf5xxx_wr_vbr - .global _mcf5xxx_wr_vbr - .global asm_set_ipl - .global _asm_set_ipl - .global mcf5xxx_wr_cacr - .global _mcf5xxx_wr_cacr - .global mcf5xxx_wr_acr0 - .global _mcf5xxx_wr_acr0 - .global mcf5xxx_wr_acr1 - .global _mcf5xxx_wr_acr1 - .global mcf5xxx_wr_acr2 - .global _mcf5xxx_wr_acr2 - .global mcf5xxx_wr_acr3 - .global _mcf5xxx_wr_acr3 - .global mcf5xxx_wr_other_sp - .global _mcf5xxx_wr_other_sp - .global mcf5xxx_wr_other_a7 - .global _mcf5xxx_wr_other_a7 - .global mcf5xxx_wr_vbr - .global _mcf5xxx_wr_vbr - .global mcf5xxx_wr_macsr - .global _mcf5xxx_wr_macsr - .global mcf5xxx_wr_mask - .global _mcf5xxx_wr_mask - .global mcf5xxx_wr_acc0 - .global _mcf5xxx_wr_acc0 - .global mcf5xxx_wr_accext01 - .global _mcf5xxx_wr_accext01 - .global mcf5xxx_wr_accext23 - .global _mcf5xxx_wr_accext23 - .global mcf5xxx_wr_acc1 - .global _mcf5xxx_wr_acc1 - .global mcf5xxx_wr_acc2 - .global _mcf5xxx_wr_acc2 - .global mcf5xxx_wr_acc3 - .global _mcf5xxx_wr_acc3 - .global mcf5xxx_wr_sr - .global _mcf5xxx_wr_sr - .global mcf5xxx_wr_rambar0 - .global _mcf5xxx_wr_rambar0 - .global mcf5xxx_wr_rambar1 - .global _mcf5xxx_wr_rambar1 - .global mcf5xxx_wr_mbar - .global _mcf5xxx_wr_mbar - .global mcf5xxx_wr_mbar0 - .global _mcf5xxx_wr_mbar0 - .global mcf5xxx_wr_mbar1 - .global _mcf5xxx_wr_mbar1 - - .text - -/******************************************************************** - * This is the main entry point upon hard reset. - */ -asm_startmeup: -_asm_startmeup: - - move.w #0x2700,sr - - /* Initialize IPSBAR */ - move.l #(___IPSBAR + 1),d0 - move.l d0,0x40000000 - - /* Initialize RAMBAR1: locate SRAM and validate it */ - move.l #(___SRAM + 0x21),d0 - .long 0x4e7b0C05 /* movec d0,RAMBAR1 */ - - /* Point Stack Pointer into SRAM temporarily */ - move.l #(___SRAM + 0x10000),sp - - /* Initialize mcf523x periphs, etc */ - jsr mcf523x_init - - /* Relocate Stack Pointer */ - move.l #___SP_INIT,sp - - /* Jump to the main process */ - jmp _start - - bra . - nop - nop - halt - - -/******************************************************************** -/* - * This routine is the lowest-level exception handler. - */ -asm_exception_handler: -_asm_exception_handler: - - lea -20(sp), sp - movem.l d0-d2/a0-a1, (sp) - pea.l 20(sp) /* push exception frame address */ - jsr exception_handler - movem.l 4(sp), d0-d2/a0-a1 - lea 24(sp), sp - rte - - -/******************************************************************** - * The MCF523x cache can be configured as instruction, data or split. - * Invalidate the entire cache. - */ -cpu_cache_flush: -_cpu_cache_flush: - nop /* sync */ - move.l #0x01000000,d0 /* Invalidate the I-Cache */ - movec d0,cacr - rts - -/********************************************************************/ -/* - * This routines changes the IPL to the value passed into the routine. - * It also returns the old IPL value back. - * Calling convention from C: - * old_ipl = asm_set_ipl(new_ipl); - * For the Diab Data C compiler, it passes return value thru D0. - * Note that only the least significant three bits of the passed - * value are used. - */ - -asm_set_ipl: -_asm_set_ipl: - link a6,#-8 - movem.l d6-d7,(sp) - - move.w sr,d7 /* current sr */ - - move.l d7,d0 /* prepare return value */ - andi.l #0x0700,d0 /* mask out IPL */ - lsr.l #8,d0 /* IPL */ - - move.l 8(a6),d6 /* get argument */ - andi.l #0x07,d6 /* least significant three bits */ - lsl.l #8,d6 /* move over to make mask */ - - andi.l #0x0000F8FF,d7 /* zero out current IPL */ - or.l d6,d7 /* place new IPL in sr */ - move.w d7,sr - - movem.l (sp),d6-d7 - lea 8(sp),sp - unlk a6 - rts - -/********************************************************************/ -/* - * These routines write to the special purpose registers in the ColdFire - * core. Since these registers are write-only in the supervisor model, - * no corresponding read routines exist. - */ - -mcf5xxx_wr_cacr: -_mcf5xxx_wr_cacr: - move.l 4(sp),d0 - .long 0x4e7b0002 /* movec d0,cacr */ - nop - rts - -mcf5xxx_wr_acr0: -_mcf5xxx_wr_acr0: - move.l 4(sp),d0 - .long 0x4e7b0004 /* movec d0,ACR0 */ - nop - rts - -mcf5xxx_wr_acr1: -_mcf5xxx_wr_acr1: - move.l 4(sp),d0 - .long 0x4e7b0005 /* movec d0,ACR1 */ - nop - rts - -mcf5xxx_wr_acr2: -_mcf5xxx_wr_acr2: - move.l 4(sp),d0 - .long 0x4e7b0006 /* movec d0,ACR2 */ - nop - rts - -mcf5xxx_wr_acr3: -_mcf5xxx_wr_acr3: - move.l 4(sp),d0 - .long 0x4e7b0007 /* movec d0,ACR3 */ - nop - rts - -mcf5xxx_wr_other_sp: -_mcf5xxx_wr_other_sp: -mcf5xxx_wr_other_a7: -_mcf5xxx_wr_other_a7: - move.l 4(sp),d0 - .long 0x4e7b0800 /* movec d0,OTHER_A7 */ - nop - rts - -mcf5xxx_wr_vbr: -_mcf5xxx_wr_vbr: - move.l 4(sp),d0 - .long 0x4e7b0801 /* movec d0,VBR */ - nop - rts - -mcf5xxx_wr_macsr: -_mcf5xxx_wr_macsr: - move.l 4(sp),d0 - .long 0x4e7b0804 /* movec d0,MACSR */ - nop - rts - -mcf5xxx_wr_mask: -_mcf5xxx_wr_mask: - move.l 4(sp),d0 - .long 0x4e7b0805 /* movec d0,MASK */ - nop - rts - -mcf5xxx_wr_acc0: -_mcf5xxx_wr_acc0: - move.l 4(sp),d0 - .long 0x4e7b0806 /* movec d0,ACC0 */ - nop - rts - -mcf5xxx_wr_accext01: -_mcf5xxx_wr_accext01: - move.l 4(sp),d0 - .long 0x4e7b0807 /* movec d0,ACCEXT01 */ - nop - rts - -mcf5xxx_wr_accext23: -_mcf5xxx_wr_accext23: - move.l 4(sp),d0 - .long 0x4e7b0808 /* movec d0,ACCEXT23 */ - nop - rts - -mcf5xxx_wr_acc1: -_mcf5xxx_wr_acc1: - move.l 4(sp),d0 - .long 0x4e7b0809 /* movec d0,ACC1 */ - nop - rts - -mcf5xxx_wr_acc2: -_mcf5xxx_wr_acc2: - move.l 4(sp),d0 - .long 0x4e7b080A /* movec d0,ACC2 */ - nop - rts - -mcf5xxx_wr_acc3: -_mcf5xxx_wr_acc3: - move.l 4(sp),d0 - .long 0x4e7b080B /* movec d0,ACC3 */ - nop - rts - -mcf5xxx_wr_sr: -_mcf5xxx_wr_sr: - move.l 4(sp),d0 - move.w d0,SR - rts - -mcf5xxx_wr_rambar0: -_mcf5xxx_wr_rambar0: - move.l 4(sp),d0 - .long 0x4e7b0C04 /* movec d0,RAMBAR0 */ - nop - rts - -mcf5xxx_wr_rambar1: -_mcf5xxx_wr_rambar1: - move.l 4(sp),d0 - .long 0x4e7b0C05 /* movec d0,RAMBAR1 */ - nop - rts - -mcf5xxx_wr_mbar: -_mcf5xxx_wr_mbar: -mcf5xxx_wr_mbar0: -_mcf5xxx_wr_mbar0: - move.l 4(sp),d0 - .long 0x4e7b0C0F /* movec d0,MBAR0 */ - nop - rts - -mcf5xxx_wr_mbar1: -_mcf5xxx_wr_mbar1: - move.l 4(sp),d0 - .long 0x4e7b0C0E /* movec d0,MBAR1 */ - nop - rts - - .end diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/system/mcf5xxx.s b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/system/mcf5xxx.s deleted file mode 100644 index 4aef9e002..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/system/mcf5xxx.s +++ /dev/null @@ -1,35 +0,0 @@ -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** - */ - - - - .end -/********************************************************************/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/system/vectors.s b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/system/vectors.s deleted file mode 100644 index 4466ddb7d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235CW/system/vectors.s +++ /dev/null @@ -1,311 +0,0 @@ -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - Copyright @ 1995-2005 Freescale Semiconductor, Inc. All rights reserved - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - .global VECTOR_TABLE - .global _VECTOR_TABLE - .global start - - .extern ___SP_INIT - .extern _asm_startmeup - .extern _asm_exception_handler - .extern _irq_handler - .extern _prvvMBPortSerialISR - .extern _prvvMBPortTimerISR - .text - -#define _irq_handler _asm_exception_handler - -/* - * Exception Vector Table - */ -VECTOR_TABLE: -_VECTOR_TABLE: -INITSP: .long ___SP_INIT /* Initial SP */ -INITPC: .long start /* Initial PC */ -vector02: .long _asm_exception_handler /* Access Error */ -vector03: .long _asm_exception_handler /* Address Error */ -vector04: .long _asm_exception_handler /* Illegal Instruction */ -vector05: .long _asm_exception_handler /* Reserved */ -vector06: .long _asm_exception_handler /* Reserved */ -vector07: .long _asm_exception_handler /* Reserved */ -vector08: .long _asm_exception_handler /* Privilege Violation */ -vector09: .long _asm_exception_handler /* Trace */ -vector0A: .long _asm_exception_handler /* Unimplemented A-Line */ -vector0B: .long _asm_exception_handler /* Unimplemented F-Line */ -vector0C: .long _asm_exception_handler /* Debug Interrupt */ -vector0D: .long _asm_exception_handler /* Reserved */ -vector0E: .long _asm_exception_handler /* Format Error */ -vector0F: .long _asm_exception_handler /* Unitialized Int. */ -vector10: .long _asm_exception_handler /* Reserved */ -vector11: .long _asm_exception_handler /* Reserved */ -vector12: .long _asm_exception_handler /* Reserved */ -vector13: .long _asm_exception_handler /* Reserved */ -vector14: .long _asm_exception_handler /* Reserved */ -vector15: .long _asm_exception_handler /* Reserved */ -vector16: .long _asm_exception_handler /* Reserved */ -vector17: .long _asm_exception_handler /* Reserved */ -vector18: .long _asm_exception_handler /* Spurious Interrupt */ -vector19: .long _irq_handler /* Autovector Level 1 */ -vector1A: .long _irq_handler /* Autovector Level 2 */ -vector1B: .long _irq_handler /* Autovector Level 3 */ -vector1C: .long _irq_handler /* Autovector Level 4 */ -vector1D: .long _irq_handler /* Autovector Level 5 */ -vector1E: .long _irq_handler /* Autovector Level 6 */ -vector1F: .long _irq_handler /* Autovector Level 7 */ -vector20: .long _asm_exception_handler /* TRAP #0 */ -vector21: .long _asm_exception_handler /* TRAP #1 */ -vector22: .long _asm_exception_handler /* TRAP #2 */ -vector23: .long _asm_exception_handler /* TRAP #3 */ -vector24: .long _asm_exception_handler /* TRAP #4 */ -vector25: .long _asm_exception_handler /* TRAP #5 */ -vector26: .long _asm_exception_handler /* TRAP #6 */ -vector27: .long _asm_exception_handler /* TRAP #7 */ -vector28: .long _asm_exception_handler /* TRAP #8 */ -vector29: .long _asm_exception_handler /* TRAP #9 */ -vector2A: .long _asm_exception_handler /* TRAP #10 */ -vector2B: .long _asm_exception_handler /* TRAP #11 */ -vector2C: .long _asm_exception_handler /* TRAP #12 */ -vector2D: .long _asm_exception_handler /* TRAP #13 */ -vector2E: .long _asm_exception_handler /* TRAP #14 */ -vector2F: .long _asm_exception_handler /* TRAP #15 */ -vector30: .long _asm_exception_handler /* Reserved */ -vector31: .long _asm_exception_handler /* Reserved */ -vector32: .long _asm_exception_handler /* Reserved */ -vector33: .long _asm_exception_handler /* Reserved */ -vector34: .long _asm_exception_handler /* Reserved */ -vector35: .long _asm_exception_handler /* Reserved */ -vector36: .long _asm_exception_handler /* Reserved */ -vector37: .long _asm_exception_handler /* Reserved */ -vector38: .long _asm_exception_handler /* Reserved */ -vector39: .long _asm_exception_handler /* Reserved */ -vector3A: .long _asm_exception_handler /* Reserved */ -vector3B: .long _asm_exception_handler /* Reserved */ -vector3C: .long _asm_exception_handler /* Reserved */ -vector3D: .long _asm_exception_handler /* Reserved */ -vector3E: .long _asm_exception_handler /* Reserved */ -vector3F: .long _asm_exception_handler /* Reserved */ -vector40: .long _irq_handler -vector41: .long _irq_handler -vector42: .long _irq_handler -vector43: .long _irq_handler -vector44: .long _irq_handler -vector45: .long _irq_handler -vector46: .long _irq_handler -vector47: .long _irq_handler -vector48: .long _irq_handler -vector49: .long _irq_handler -vector4A: .long _irq_handler -vector4B: .long _irq_handler -vector4C: .long _irq_handler -vector4D: .long _prvvMBPortSerialISR -vector4E: .long _irq_handler -vector4F: .long _irq_handler -vector50: .long _irq_handler -vector51: .long _irq_handler -vector52: .long _irq_handler -vector53: .long _irq_handler -vector54: .long _irq_handler -vector55: .long _irq_handler -vector56: .long _irq_handler -vector57: .long _irq_handler -vector58: .long _irq_handler -vector59: .long _irq_handler -vector5A: .long _irq_handler -vector5B: .long _irq_handler -vector5C: .long _irq_handler -vector5D: .long _irq_handler -vector5E: .long _irq_handler -vector5F: .long _irq_handler -vector60: .long _irq_handler -vector61: .long _irq_handler -vector62: .long _irq_handler -vector63: .long _irq_handler -vector64: .long _irq_handler -vector65: .long _prvvMBPortTimerISR -vector66: .long _irq_handler -vector67: .long _irq_handler -vector68: .long _irq_handler -vector69: .long _irq_handler -vector6A: .long _irq_handler -vector6B: .long _irq_handler -vector6C: .long _irq_handler -vector6D: .long _irq_handler -vector6E: .long _irq_handler -vector6F: .long _irq_handler -vector70: .long _irq_handler -vector71: .long _irq_handler -vector72: .long _irq_handler -vector73: .long _irq_handler -vector74: .long _irq_handler -vector75: .long _irq_handler -vector76: .long _irq_handler -vector77: .long _irq_handler -vector78: .long _irq_handler -vector79: .long _irq_handler -vector7A: .long _irq_handler -vector7B: .long _irq_handler -vector7C: .long _irq_handler -vector7D: .long _irq_handler -vector7E: .long _irq_handler -vector7F: .long _irq_handler -vector80: .long _irq_handler -vector81: .long _irq_handler -vector82: .long _irq_handler -vector83: .long _irq_handler -vector84: .long _irq_handler -vector85: .long _irq_handler -vector86: .long _irq_handler -vector87: .long _irq_handler -vector88: .long _irq_handler -vector89: .long _irq_handler -vector8A: .long _irq_handler -vector8B: .long _irq_handler -vector8C: .long _irq_handler -vector8D: .long _irq_handler -vector8E: .long _irq_handler -vector8F: .long _irq_handler -vector90: .long _irq_handler -vector91: .long _irq_handler -vector92: .long _irq_handler -vector93: .long _irq_handler -vector94: .long _irq_handler -vector95: .long _irq_handler -vector96: .long _irq_handler -vector97: .long _irq_handler -vector98: .long _irq_handler -vector99: .long _irq_handler -vector9A: .long _irq_handler -vector9B: .long _irq_handler -vector9C: .long _irq_handler -vector9D: .long _irq_handler -vector9E: .long _irq_handler -vector9F: .long _irq_handler -vectorA0: .long _irq_handler -vectorA1: .long _irq_handler -vectorA2: .long _irq_handler -vectorA3: .long _irq_handler -vectorA4: .long _irq_handler -vectorA5: .long _irq_handler -vectorA6: .long _irq_handler -vectorA7: .long _irq_handler -vectorA8: .long _irq_handler -vectorA9: .long _irq_handler -vectorAA: .long _irq_handler -vectorAB: .long _irq_handler -vectorAC: .long _irq_handler -vectorAD: .long _irq_handler -vectorAE: .long _irq_handler -vectorAF: .long _irq_handler -vectorB0: .long _irq_handler -vectorB1: .long _irq_handler -vectorB2: .long _irq_handler -vectorB3: .long _irq_handler -vectorB4: .long _irq_handler -vectorB5: .long _irq_handler -vectorB6: .long _irq_handler -vectorB7: .long _irq_handler -vectorB8: .long _irq_handler -vectorB9: .long _irq_handler -vectorBA: .long _irq_handler -vectorBB: .long _irq_handler -vectorBC: .long _irq_handler -vectorBD: .long _irq_handler -vectorBE: .long _irq_handler -vectorBF: .long _irq_handler -vectorC0: .long _irq_handler -vectorC1: .long _irq_handler -vectorC2: .long _irq_handler -vectorC3: .long _irq_handler -vectorC4: .long _irq_handler -vectorC5: .long _irq_handler -vectorC6: .long _irq_handler -vectorC7: .long _irq_handler -vectorC8: .long _irq_handler -vectorC9: .long _irq_handler -vectorCA: .long _irq_handler -vectorCB: .long _irq_handler -vectorCC: .long _irq_handler -vectorCD: .long _irq_handler -vectorCE: .long _irq_handler -vectorCF: .long _irq_handler -vectorD0: .long _irq_handler -vectorD1: .long _irq_handler -vectorD2: .long _irq_handler -vectorD3: .long _irq_handler -vectorD4: .long _irq_handler -vectorD5: .long _irq_handler -vectorD6: .long _irq_handler -vectorD7: .long _irq_handler -vectorD8: .long _irq_handler -vectorD9: .long _irq_handler -vectorDA: .long _irq_handler -vectorDB: .long _irq_handler -vectorDC: .long _irq_handler -vectorDD: .long _irq_handler -vectorDE: .long _irq_handler -vectorDF: .long _irq_handler -vectorE0: .long _irq_handler -vectorE1: .long _irq_handler -vectorE2: .long _irq_handler -vectorE3: .long _irq_handler -vectorE4: .long _irq_handler -vectorE5: .long _irq_handler -vectorE6: .long _irq_handler -vectorE7: .long _irq_handler -vectorE8: .long _irq_handler -vectorE9: .long _irq_handler -vectorEA: .long _irq_handler -vectorEB: .long _irq_handler -vectorEC: .long _irq_handler -vectorED: .long _irq_handler -vectorEE: .long _irq_handler -vectorEF: .long _irq_handler -vectorF0: .long _irq_handler -vectorF1: .long _irq_handler -vectorF2: .long _irq_handler -vectorF3: .long _irq_handler -vectorF4: .long _irq_handler -vectorF5: .long _irq_handler -vectorF6: .long _irq_handler -vectorF7: .long _irq_handler -vectorF8: .long _irq_handler -vectorF9: .long _irq_handler -vectorFA: .long _irq_handler -vectorFB: .long _irq_handler -vectorFC: .long _irq_handler -vectorFD: .long _irq_handler -vectorFE: .long _irq_handler -vectorFF: .long _irq_handler - -start: - move.w #0x2700,sr - jmp _asm_startmeup - .end diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/FreeRTOSConfig.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/FreeRTOSConfig.h deleted file mode 100644 index 77552aef8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/FreeRTOSConfig.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. - MCF5235 Port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 25000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetCurrentTaskHandle 1 - -#endif /* FREERTOS_CONFIG_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/Makefile b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/Makefile deleted file mode 100644 index 6ed8f15b8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/Makefile +++ /dev/null @@ -1,99 +0,0 @@ -# -# FreeModbus MCF5235 port- Makefile -# -# Copyright (c) 2006 Christian Walter, Vienna 2006. -# -# $Id: Makefile,v 1.1 2006/08/30 23:18:06 wolti Exp $ -# -# --------------------------------------------------------------------------- - -BASE = /opt/gcc-m68k/bin -CC = $(BASE)/m68k-elf-gcc -CXX = $(BASE)/m68k-elf-g++ -OBJCOPY = $(BASE)/m68k-elf-objcopy -SIZE = $(BASE)/m68k-elf-size -INSIGHT = $(BASE)/m68k-bdm-elf-insight -BDMFLASH = $(BASE)/bdmflash - -#CFLAGS = -MD -O2 -m528x -Wall -MB_INC = -Iport -I../../modbus/tcp -I../../modbus/include -RTOS_INC = -Ifreertos/include -I../Common/include -LWIP_INC = -Ilwip/src/include -Ilwip/src/include/ipv4 \ - -Ilwip/src/include -Ilwip/src/include/ipv4 \ - -Ilwip/contrib/port/FreeRTOS/MCF5235 \ - -Ilwip/contrib/port/FreeRTOS/MCF5235/netif -CFLAGS = -MD -gdwarf-2 -g3 -m528x -Wall \ - -D'GCC_MCF5235=1' -D'_GCC_USES_FP=1' \ - -D'__IPSBAR=((vuint8 *) 0x40000000)' -D'FSYS_2=25000000UL' -CFLAGS += -I. -Iinclude -Iinclude/arch $(RTOS_INC) $(MB_INC) $(LWIP_INC) - -ASFLAGS = -MD -gdwarf-2 -g3 -m528x -Wa,--register-prefix-optional \ - -Wa,--bitwise-or -Wa,--defsym,IPSBAR=0x40000000 -LDSCRIPT = m5235-ram.ld -LDFLAGS = -nostartfiles -m528x -Wl,--script=$(LDSCRIPT) - -TGT = demo -OTHER_CSRC = -OTHER_ASRC = $(addprefix system/, crt0.S vector.S) -MB_SRC = $(addprefix ../../modbus/, mb.c tcp/mbtcp.c functions/mbfunccoils.c functions/mbfuncdiag.c functions/mbfuncholding.c functions/mbfuncinput.c functions/mbfuncother.c functions/mbfuncdisc.c functions/mbutils.c) \ - $(addprefix port/, porttcp.c portevent.c portother.c ) - -CSRC = demo.c $(MB_SRC) \ - $(addprefix system/, init.c newlib.c serial.c) \ - $(addprefix freertos/, tasks.c queue.c list.c) \ - $(addprefix freertos/portable/MemMang/, heap_3.c) \ - $(addprefix freertos/portable/GCC/MCF5235/, port.c) \ - $(addprefix lwip/src/core/, tcp_out.c inet.c mem.c memp.c netif.c pbuf.c raw.c stats.c sys.c tcp.c tcp_in.c udp.c ipv4/ip.c ipv4/ip_addr.c ipv4/icmp.c ipv4/ip_frag.c) \ - $(addprefix lwip/src/api/, tcpip.c api_msg.c err.c api_lib.c ) \ - $(addprefix lwip/src/netif/, etharp.c ) \ - $(addprefix lwip/contrib/port/FreeRTOS/MCF5235/, sys_arch.c netif/fec.c netif/nbuf.c) - -ASRC = $(addprefix system/, mcf5xxx.S ) -OBJS = $(CSRC:.c=.o) $(ASRC:.S=.o) -NOLINK_OBJS = $(OTHER_CSRC:.c=.o) $(OTHER_ASRC:.S=.o) -DEPS = $(OBJS:.o=.d) $(NOLINK_OBJS:.o=.d) -BIN = $(TGT).elf - -.PHONY: clean all - -all: $(BIN) - -flash-programm: $(TGT).elf - $(OBJCOPY) -O binary $(TGT).elf $(TGT).bin - @BIN_SIZE=`du -b $(TGT).bin | awk '//{ print $$1; }'`; \ - echo "programming $(TGT).bin with size $$BIN_SIZE to flash..."; \ - $(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 write $(TGT).bin 0 - -flash-verify: - @BIN_SIZE=`du -b $(TGT).bin | awk '//{ print $$1; }'`; \ - echo "loading $$BIN_SIZE bytes from target into $(TGT).vrf..."; \ - $(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 read $(TGT).vrf 0 $$BIN_SIZE - -flash-erase: - $(BDMFLASH) /dev/bdmcf20 0x00000000 1 2 erase - -debug: - $(INSIGHT) --command=m5235.gdb --se=$(TGT).elf - -$(BIN): $(OBJS) $(NOLINK_OBJS) - $(CC) $(LDFLAGS) -Wl,-Map=$(TGT).map $(OBJS) $(LDLIBS) -o $@ - -clean: - rm -f $(DEPS) - rm -f $(OBJS) $(NOLINK_OBJS) - rm -f $(BIN) $(TGT).map - -# --------------------------------------------------------------------------- -# rules for code generation -# --------------------------------------------------------------------------- -%.o: %.c - $(CC) $(CFLAGS) -o $@ -c $< - -%.o: %.S - $(CC) $(ASFLAGS) -o $@ -c $< - -# --------------------------------------------------------------------------- -# # compiler generated dependencies -# --------------------------------------------------------------------------- --include $(DEPS) - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/README.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/README.txt deleted file mode 100644 index 243c7e346..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/README.txt +++ /dev/null @@ -1,60 +0,0 @@ - - FreeModbus Coldfire MC523x PORT with lwIP - -REQUIREMENTS -============ - -The FreeModbus/lwIP port requires are port of the lwIP TCP/IP stack for -the target platform. This port includes a suitable Ethernet driver for -lwIP as well as a FreeRTOS port. -The FreeModbus part itself does NOT depend on FreeRTOS or the Coldfire -ethernet controller and can therefore be used for creating other ports. - -The development environment used is based on the GNU C Compiler for -a m68k-elf target as well as the insight debugger with some patches for -the BDM interface[1]. GDB startup and linker scripts are supplied with -the demo for the M5235BCC evaluation kit from Freescale. - - [1] ... BDM tools: http://sourceforge.net/projects/bdm/ - -USAGE -===== - -A makefile is supplied with the demo application and a binary can be -produced by calling 'make all'. A special target 'debug' is provided -which executes the insight debugger. At the insight debugger prompt -one should select the appropriate target interface (either BDM/Direct -or BDM/TCP) and should download the application to the development -board. It is important that the GDB script setup-and-load is executed -prior to downloading to initialize the SDRAM. After downloading one -should call the GDB function 'execute' and the PC is set to the start -of the executable. Execution can be started by typing 'continue' at -the Insight console interface. -In addition it is possible to download the software to the flash. This can -be done by calling 'make flash-erase' and 'make flash-programm'. - -By default the port using the following settings: - - IP Address : 10.0.10.2 - Netmask : 255.255.255.0 - Gateway : 10.0.10.1 - Modbus TCP Port : 502 - -COMMON PROBLEMS -=============== - -Most of the problems have their origin in the startup scripts. The -following list should serve as a checklist where each point must be -satisfied for the port to work. - - - The FreeRTOS port only works correctly in the supervisor mode. There- - fore the Coldfire CPU must run in the supervisor mode. - - - portVECTOR_TABLE does not point to the currently active vector table. - Please also note that the vector table must be in RAM such that the - FreeRTOS port can install a traphandler for the portYIELD() call. - -$Id: README.txt,v 1.1 2006/08/30 23:18:06 wolti Exp $ - -MCF5235 + lwIP port - Copyright (c) 2006 Christian Walter. - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/demo.c deleted file mode 100644 index d182c2796..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/demo.c +++ /dev/null @@ -1,205 +0,0 @@ -/* ------------------------ System includes ------------------------------- */ -#include -#include -#include -#include - -/* ------------------------ FreeRTOS includes ----------------------------- */ -#include "FreeRTOS.h" -#include "task.h" - -/* ------------------------ LWIP includes --------------------------------- */ -#include "lwip/api.h" -#include "lwip/tcpip.h" -#include "lwip/memp.h" - -/* ------------------------ FreeModbus includes --------------------------- */ -#include "mb.h" - -/* ------------------------ Project includes ------------------------------ */ -#include "mcf5xxx.h" -#include "mcf523x.h" -#include "netif/fec.h" - -#include "serial.h" - -/* ------------------------ Defines --------------------------------------- */ -#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 38400 ) - -#define mainMB_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define PROG "FreeModbus" -#define REG_INPUT_START 1000 -#define REG_INPUT_NREGS 4 -#define REG_HOLDING_START 2000 -#define REG_HOLDING_NREGS 130 - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegInputStart = REG_INPUT_START; -static USHORT usRegInputBuf[REG_INPUT_NREGS]; -static USHORT usRegHoldingStart = REG_HOLDING_START; -static USHORT usRegHoldingBuf[REG_HOLDING_NREGS]; - -xComPortHandle xSTDComPort = NULL; - -/* ------------------------ Static functions ------------------------------ */ -static void vlwIPInit( void ); -static void vMBServerTask( void *arg ); - -/* ------------------------ Implementation -------------------------------- */ -int -main( int argc, char *argv[] ) -{ - asm volatile ( "move.w #0x2000, %sr\n\t" ); - - /* Initialize serial communication device. */ - xSTDComPort = xSerialPortInitMinimal( 38400, 8 ); - - /* Initialize lwIP protocol stack. */ - vlwIPInit( ); - - if( sys_thread_new( vMBServerTask, NULL, mainMB_TASK_PRIORITY ) == NULL ) - { - fprintf( stderr, "%s: can't create modbus task!\r\n", PROG ); - } - else - { - /* Now all the tasks have been started - start the scheduler. */ - vTaskStartScheduler( ); - } - - /* Should never get here! */ - return 0; -} - -void -vlwIPInit( void ) -{ - /* Initialize lwIP and its interface layer. */ - sys_init( ); - mem_init( ); - memp_init( ); - pbuf_init( ); - netif_init( ); - ip_init( ); - tcpip_init( NULL, NULL ); -} - -void -vMBServerTask( void *arg ) -{ - eMBErrorCode xStatus; - struct ip_addr xIpAddr, xNetMast, xGateway; - struct netif xFEC523x; - - IP4_ADDR( &xIpAddr, 10, 0, 10, 2 ); - IP4_ADDR( &xNetMast, 255, 255, 255, 0 ); - IP4_ADDR( &xGateway, 10, 0, 10, 1 ); - netif_add( &xFEC523x, &xIpAddr, &xNetMast, &xGateway, NULL, mcf523xfec_init, tcpip_input ); - /* Make it the default interface */ - netif_set_default( &xFEC523x ); - /* Bring it up */ - netif_set_up( &xFEC523x ); - - - for( ;; ) - { - if( eMBTCPInit( MB_TCP_PORT_USE_DEFAULT ) != MB_ENOERR ) - { - fprintf( stderr, "%s: can't initialize modbus stack!\r\n", PROG ); - } - else if( eMBEnable( ) != MB_ENOERR ) - { - fprintf( stderr, "%s: can't enable modbus stack!\r\n", PROG ); - } - else - { - do - { - xStatus = eMBPoll( ); - } - while( xStatus == MB_ENOERR ); - } - /* An error occured. Maybe we can restart. */ - ( void )eMBDisable( ); - ( void )eMBClose( ); - } -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_HOLDING_START ) && - ( usAddress + usNRegs <= REG_HOLDING_START + REG_HOLDING_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegHoldingStart ); - switch ( eMode ) - { - /* Pass current register values to the protocol stack. */ - case MB_REG_READ: - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( UCHAR ) ( usRegHoldingBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( UCHAR ) ( usRegHoldingBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - break; - - /* Update current register values with new values from the - * protocol stack. */ - case MB_REG_WRITE: - while( usNRegs > 0 ) - { - usRegHoldingBuf[iRegIndex] = *pucRegBuffer++ << 8; - usRegHoldingBuf[iRegIndex] |= *pucRegBuffer++; - iRegIndex++; - usNRegs--; - } - } - } - else - { - eStatus = MB_ENOREG; - } - return eStatus; -} - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/demo.vpj b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/demo.vpj deleted file mode 100644 index 34b255372..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/demo.vpj +++ /dev/null @@ -1,329 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/croutine.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/croutine.c deleted file mode 100644 index a0b304550..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/croutine.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/* Lists for ready and blocked co-routines. --------------------*/ -static xList pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ -static xList xDelayedCoRoutineList1; /*< Delayed co-routines. */ -static xList xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ -static xList * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */ -static xList * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ -static xList xPendingReadyList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ - -/* Other file private variables. --------------------------------*/ -corCRCB * pxCurrentCoRoutine = NULL; -static unsigned portBASE_TYPE uxTopCoRoutineReadyPriority = 0; -static portTickType xCoRoutineTickCount = 0; - -/* The initial state of the co-routine when it is created. */ -#define corINITIAL_STATE ( 0 ) - -/* - * Place the co-routine represented by pxCRCB into the appropriate ready queue - * for the priority. It is inserted at the end of the list. - * - * This macro accesses the co-routine ready lists and therefore must not be - * used from within an ISR. - */ -#define prvAddCoRoutineToReadyQueue( pxCRCB ) \ -{ \ - if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ - { \ - uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ - } \ - vListInsertEnd( ( xList * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ -} - -/* - * Utility to ready all the lists used by the scheduler. This is called - * automatically upon the creation of the first co-routine. - */ -static void prvInitialiseCoRoutineLists( void ); - -/* - * Co-routines that are readied by an interrupt cannot be placed directly into - * the ready lists (there is no mutual exclusion). Instead they are placed in - * in the pending ready list in order that they can later be moved to the ready - * list by the co-routine scheduler. - */ -static inline void prvCheckPendingReadyList( void ); - -/* - * Macro that looks at the list of co-routines that are currently delayed to - * see if any require waking. - * - * Co-routines are stored in the queue in the order of their wake time - - * meaning once one co-routine has been found whose timer has not expired - * we need not look any further down the list. - */ -static inline void prvCheckDelayedList( void ); - -/*-----------------------------------------------------------*/ - -portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ) -{ -portBASE_TYPE xReturn; -corCRCB *pxCoRoutine; - - /* Allocate the memory that will store the co-routine control block. */ - pxCoRoutine = ( corCRCB * ) pvPortMalloc( sizeof( corCRCB ) ); - if( pxCoRoutine ) - { - /* If pxCurrentCoRoutine is NULL then this is the first co-routine to - be created and the co-routine data structures need initialising. */ - if( pxCurrentCoRoutine == NULL ) - { - pxCurrentCoRoutine = pxCoRoutine; - prvInitialiseCoRoutineLists(); - } - - /* Check the priority is within limits. */ - if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) - { - uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; - } - - /* Fill out the co-routine control block from the function parameters. */ - pxCoRoutine->uxState = corINITIAL_STATE; - pxCoRoutine->uxPriority = uxPriority; - pxCoRoutine->uxIndex = uxIndex; - pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; - - /* Initialise all the other co-routine control block parameters. */ - vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); - vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); - - /* Set the co-routine control block as a link back from the xListItem. - This is so we can get back to the containing CRCB from a generic item - in a list. */ - listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); - listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); - - /* Event lists are always in priority order. */ - listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); - - /* Now the co-routine has been initialised it can be added to the ready - list at the correct priority. */ - prvAddCoRoutineToReadyQueue( pxCoRoutine ); - - xReturn = pdPASS; - } - else - { - xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList ) -{ -portTickType xTimeToWake; - - /* Calculate the time to wake - this may overflow but this is - not a problem. */ - xTimeToWake = xCoRoutineTickCount + xTicksToDelay; - - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xCoRoutineTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - } - - if( pxEventList ) - { - /* Also add the co-routine to an event list. If this is done then the - function must be called with interrupts disabled. */ - vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); - } -} -/*-----------------------------------------------------------*/ - -static inline void prvCheckPendingReadyList( void ) -{ - /* Are there any co-routines waiting to get moved to the ready list? These - are co-routines that have been readied by an ISR. The ISR cannot access - the ready lists itself. */ - while( !listLIST_IS_EMPTY( &xPendingReadyList ) ) - { - corCRCB *pxUnblockedCRCB; - - /* The pending ready list can be accessed by an ISR. */ - portDISABLE_INTERRUPTS(); - { - pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyList) ); - vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); - } - portENABLE_INTERRUPTS(); - - vListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); - prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); - } -} -/*-----------------------------------------------------------*/ - -static inline void prvCheckDelayedList( void ) -{ -static portTickType xLastTickCount, xPassedTicks; -corCRCB *pxCRCB; - - xPassedTicks = xTaskGetTickCount() - xLastTickCount; - while( xPassedTicks ) - { - xCoRoutineTickCount++; - xPassedTicks--; - - /* If the tick count has overflowed we need to swap the ready lists. */ - if( xCoRoutineTickCount == 0 ) - { - xList * pxTemp; - - /* Tick count has overflowed so we need to swap the delay lists. If there are - any items in pxDelayedCoRoutineList here then there is an error! */ - pxTemp = pxDelayedCoRoutineList; - pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; - pxOverflowDelayedCoRoutineList = pxTemp; - } - - /* See if this tick has made a timeout expire. */ - while( ( pxCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ) ) != NULL ) - { - if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) - { - /* Timeout not yet expired. */ - break; - } - - portDISABLE_INTERRUPTS(); - { - /* The event could have occurred just before this critical - section. If this is the case then the generic list item will - have been moved to the pending ready list and the following - line is still valid. Also the pvContainer parameter will have - been set to NULL so the following lines are also valid. */ - vListRemove( &( pxCRCB->xGenericListItem ) ); - - /* Is the co-routine waiting on an event also? */ - if( pxCRCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxCRCB->xEventListItem ) ); - } - } - portENABLE_INTERRUPTS(); - - prvAddCoRoutineToReadyQueue( pxCRCB ); - } - } - - xLastTickCount = xCoRoutineTickCount; -} -/*-----------------------------------------------------------*/ - -void vCoRoutineSchedule( void ) -{ - /* See if any co-routines readied by events need moving to the ready lists. */ - prvCheckPendingReadyList(); - - /* See if any delayed co-routines have timed out. */ - prvCheckDelayedList(); - - /* Find the highest priority queue that contains ready co-routines. */ - while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) - { - if( uxTopCoRoutineReadyPriority == 0 ) - { - /* No more co-routines to check. */ - return; - } - --uxTopCoRoutineReadyPriority; - } - - /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines - of the same priority get an equal share of the processor time. */ - listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); - - /* Call the co-routine. */ - ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); - - return; -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseCoRoutineLists( void ) -{ -unsigned portBASE_TYPE uxPriority; - - for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) - { - vListInitialise( ( xList * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); - } - - vListInitialise( ( xList * ) &xDelayedCoRoutineList1 ); - vListInitialise( ( xList * ) &xDelayedCoRoutineList2 ); - vListInitialise( ( xList * ) &xPendingReadyList ); - - /* Start with pxDelayedCoRoutineList using list1 and the - pxOverflowDelayedCoRoutineList using list2. */ - pxDelayedCoRoutineList = &xDelayedCoRoutineList1; - pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList ) -{ -corCRCB *pxUnblockedCRCB; -portBASE_TYPE xReturn; - - /* This function is called from within an interrupt. It can only access - event lists and the pending ready list. */ - pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); - vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedCRCB->xEventListItem ) ); - - if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) - { - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/FreeRTOS.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/FreeRTOS.h deleted file mode 100644 index f3a59d8ca..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/FreeRTOS.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef INC_FREERTOS_H -#define INC_FREERTOS_H - - -/* - * Include the generic headers required for the FreeRTOS port being used. - */ -#include - -/* Basic FreeRTOS definitions. */ -#include "projdefs.h" - -/* Application specific configuration options. */ -#include "FreeRTOSConfig.h" - -/* Definitions specific to the port being used. */ -#include "portable.h" - - - - - - - -/* - * Check all the required application specific macros have been defined. - * These macros are application specific and (as downloaded) are defined - * within FreeRTOSConfig.h. - */ - -#ifndef configUSE_PREEMPTION - #error Missing definition: configUSE_PREEMPTION should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_IDLE_HOOK - #error Missing definition: configUSE_IDLE_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_TICK_HOOK - #error Missing definition: configUSE_TICK_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_CO_ROUTINES - #error Missing definition: configUSE_CO_ROUTINES should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskPrioritySet - #error Missing definition: INCLUDE_vTaskPrioritySet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_uxTaskPriorityGet - #error Missing definition: INCLUDE_uxTaskPriorityGet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelete - #error Missing definition: INCLUDE_vTaskDelete should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskCleanUpResources - #error Missing definition: INCLUDE_vTaskCleanUpResources should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskSuspend - #error Missing definition: INCLUDE_vTaskSuspend should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelayUntil - #error Missing definition: INCLUDE_vTaskDelayUntil should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelay - #error Missing definition: INCLUDE_vTaskDelay should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_16_BIT_TICKS - #error Missing definition: configUSE_16_BIT_TICKS should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/croutine.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/croutine.h deleted file mode 100644 index df28d06bf..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/croutine.h +++ /dev/null @@ -1,713 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ -#ifndef CO_ROUTINE_H -#define CO_ROUTINE_H - -#include "list.h" - -/* Used to hide the implementation of the co-routine control block. The -control block structure however has to be included in the header due to -the macro implementation of the co-routine functionality. */ -typedef void * xCoRoutineHandle; - -/* Defines the prototype to which co-routine functions must conform. */ -typedef void (*crCOROUTINE_CODE)( xCoRoutineHandle, unsigned portBASE_TYPE ); - -typedef struct corCoRoutineControlBlock -{ - crCOROUTINE_CODE pxCoRoutineFunction; - xListItem xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ - xListItem xEventListItem; /*< List item used to place the CRCB in event lists. */ - unsigned portBASE_TYPE uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ - unsigned portBASE_TYPE uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ - unsigned portSHORT uxState; /*< Used internally by the co-routine implementation. */ -} corCRCB; /* Co-routine control block. Note must be identical in size down to uxPriority with tskTCB. */ - -/** - * croutine. h - *

- portBASE_TYPE xCoRoutineCreate(

-                                 crCOROUTINE_CODE pxCoRoutineCode,

-                                 unsigned portBASE_TYPE uxPriority,

-                                 unsigned portBASE_TYPE uxIndex

-                               );
- * - * Create a new co-routine and add it to the list of co-routines that are - * ready to run. - * - * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine - * functions require special syntax - see the co-routine section of the WEB - * documentation for more information. - * - * @param uxPriority The priority with respect to other co-routines at which - * the co-routine will run. - * - * @param uxIndex Used to distinguish between different co-routines that - * execute the same function. See the example below and the co-routine section - * of the WEB documentation for further information. - * - * @return pdPASS if the co-routine was successfully created and added to a ready - * list, otherwise an error code defined with ProjDefs.h. - * - * Example usage: -

- // Co-routine to be created.

- void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- // This may not be necessary for const variables.

- static const char cLedToFlash[ 2 ] = { 5, 6 };

- static const portTickType xTimeToDelay[ 2 ] = { 200, 400 };

-

-     // Must start every co-routine with a call to crSTART();

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-         // This co-routine just delays for a fixed period, then toggles

-         // an LED.  Two co-routines are created using this function, so

-         // the uxIndex parameter is used to tell the co-routine which

-         // LED to flash and how long to delay.  This assumes xQueue has

-         // already been created.

-         vParTestToggleLED( cLedToFlash[ uxIndex ] );

-         crDELAY( xHandle, uxFlashRates[ uxIndex ] );

-     }

-

-     // Must end every co-routine with a call to crEND();

-     crEND();

- }

-

- // Function that creates two co-routines.

- void vOtherFunction( void )

- {

- unsigned char ucParameterToPass;

- xTaskHandle xHandle;

-		

-     // Create two co-routines at priority 0.  The first is given index 0

-     // so (from the code above) toggles LED 5 every 200 ticks.  The second

-     // is given index 1 so toggles LED 6 every 400 ticks.

-     for( uxIndex = 0; uxIndex < 2; uxIndex++ )

-     {

-         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );

-     }  

- }

-   
- * \defgroup xCoRoutineCreate xCoRoutineCreate - * \ingroup Tasks - */ -portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ); - - -/** - * croutine. h - *

- void vCoRoutineSchedule( void );
- * - * Run a co-routine. - * - * vCoRoutineSchedule() executes the highest priority co-routine that is able - * to run. The co-routine will execute until it either blocks, yields or is - * preempted by a task. Co-routines execute cooperatively so one - * co-routine cannot be preempted by another, but can be preempted by a task. - * - * If an application comprises of both tasks and co-routines then - * vCoRoutineSchedule should be called from the idle task (in an idle task - * hook). - * - * Example usage: -

- // This idle task hook will schedule a co-routine each time it is called.

- // The rest of the idle task will execute between co-routine calls.

- void vApplicationIdleHook( void )

- {

-	vCoRoutineSchedule();

- }

-

- // Alternatively, if you do not require any other part of the idle task to 

- // execute, the idle task hook can call vCoRoutineScheduler() within an

- // infinite loop.

- void vApplicationIdleHook( void )

- {

-    for( ;; )

-    {

-        vCoRoutineSchedule();

-    }

- }

- 
- * \defgroup vCoRoutineSchedule vCoRoutineSchedule - * \ingroup Tasks - */ -void vCoRoutineSchedule( void ); - -/** - * croutine. h - *

- crSTART( xCoRoutineHandle xHandle );
- * - * This macro MUST always be called at the start of a co-routine function. - * - * Example usage: -

- // Co-routine to be created.

- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- static portLONG ulAVariable;

-

-     // Must start every co-routine with a call to crSTART();

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-          // Co-routine functionality goes here.

-     }

-

-     // Must end every co-routine with a call to crEND();

-     crEND();

- }
- * \defgroup crSTART crSTART - * \ingroup Tasks - */ -#define crSTART( pxCRCB ) switch( ( ( corCRCB * )pxCRCB )->uxState ) { case 0: - -/** - * croutine. h - *

- crEND();
- * - * This macro MUST always be called at the end of a co-routine function. - * - * Example usage: -

- // Co-routine to be created.

- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- static portLONG ulAVariable;

-

-     // Must start every co-routine with a call to crSTART();

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-          // Co-routine functionality goes here.

-     }

-

-     // Must end every co-routine with a call to crEND();

-     crEND();

- }
- * \defgroup crSTART crSTART - * \ingroup Tasks - */ -#define crEND() } - -/* - * These macros are intended for internal use by the co-routine implementation - * only. The macros should not be used directly by application writers. - */ -#define crSET_STATE0( xHandle ) ( ( corCRCB * )xHandle)->uxState = (__LINE__ * 2); return; case (__LINE__ * 2): -#define crSET_STATE1( xHandle ) ( ( corCRCB * )xHandle)->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1): - -/** - * croutine. h - *

- crDELAY( xCoRoutineHandle xHandle, portTickType xTicksToDelay );
- * - * Delay a co-routine for a fixed period of time. - * - * crDELAY can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * @param xHandle The handle of the co-routine to delay. This is the xHandle - * parameter of the co-routine function. - * - * @param xTickToDelay The number of ticks that the co-routine should delay - * for. The actual amount of time this equates to is defined by - * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_RATE_MS - * can be used to convert ticks to milliseconds. - * - * Example usage: -

- // Co-routine to be created.

- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- // This may not be necessary for const variables.

- // We are to delay for 200ms.

- static const xTickType xDelayTime = 200 / portTICK_RATE_MS;

-

-     // Must start every co-routine with a call to crSTART();

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-        // Delay for 200ms.

-        crDELAY( xHandle, xDelayTime );

-

-        // Do something here.

-     }

-

-     // Must end every co-routine with a call to crEND();

-     crEND();

- }
- * \defgroup crDELAY crDELAY - * \ingroup Tasks - */ -#define crDELAY( xHandle, xTicksToDelay ) \ - if( xTicksToDelay > 0 ) \ - { \ - vCoRoutineAddToDelayedList( xTicksToDelay, NULL ); \ - } \ - crSET_STATE0( xHandle ); - -/** - *

- crQUEUE_SEND( 

-                  xCoRoutineHandle xHandle, 

-                  xQueueHandle pxQueue, 

-                  void *pvItemToQueue, 

-                  portTickType xTicksToWait, 

-                  portBASE_TYPE *pxResult 

-             )
- * - * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine - * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. - * - * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas - * xQueueSend() and xQueueReceive() can only be used from tasks. - * - * crQUEUE_SEND can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xHandle The handle of the calling co-routine. This is the xHandle - * parameter of the co-routine function. - * - * @param pxQueue The handle of the queue on which the data will be posted. - * The handle is obtained as the return value when the queue is created using - * the xQueueCreate() API function. - * - * @param pvItemToQueue A pointer to the data being posted onto the queue. - * The number of bytes of each queued item is specified when the queue is - * created. This number of bytes is copied from pvItemToQueue into the queue - * itself. - * - * @param xTickToDelay The number of ticks that the co-routine should block - * to wait for space to become available on the queue, should space not be - * available immediately. The actual amount of time this equates to is defined - * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant - * portTICK_RATE_MS can be used to convert ticks to milliseconds (see example - * below). - * - * @param pxResult The variable pointed to by pxResult will be set to pdPASS if - * data was successfully posted onto the queue, otherwise it will be set to an - * error defined within ProjDefs.h. - * - * Example usage: -

- // Co-routine function that blocks for a fixed period then posts a number onto

- // a queue.

- static void prvCoRoutineFlashTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- static portBASE_TYPE xNumberToPost = 0;

- static portBASE_TYPE xResult;

-

-    // Co-routines must begin with a call to crSTART().

-    crSTART( xHandle );

-

-    for( ;; )

-    {

-        // This assumes the queue has already been created.

-        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );

-

-        if( xResult != pdPASS )

-        {

-            // The message was not posted!

-        }

-

-        // Increment the number to be posted onto the queue.

-        xNumberToPost++;

- 

-        // Delay for 100 ticks.

-        crDELAY( xHandle, 100 );

-    }

-

-    // Co-routines must end with a call to crEND().

-    crEND();

- }
- * \defgroup crQUEUE_SEND crQUEUE_SEND - * \ingroup Tasks - */ -#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ -{ \ - *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, xTicksToWait ); \ - if( *pxResult == errQUEUE_BLOCKED ) \ - { \ - crSET_STATE0( xHandle ); \ - *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, 0 ); \ - } \ - if( *pxResult == errQUEUE_YIELD ) \ - { \ - crSET_STATE1( xHandle ); \ - *pxResult = pdPASS; \ - } \ -} - -/** - * croutine. h - *

-  crQUEUE_RECEIVE( 

-                     xCoRoutineHandle xHandle, 

-                     xQueueHandle pxQueue, 

-                     void *pvBuffer, 

-                     portTickType xTicksToWait, 

-                     portBASE_TYPE *pxResult 

-                 )
- * - * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine - * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. - * - * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas - * xQueueSend() and xQueueReceive() can only be used from tasks. - * - * crQUEUE_RECEIVE can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xHandle The handle of the calling co-routine. This is the xHandle - * parameter of the co-routine function. - * - * @param pxQueue The handle of the queue from which the data will be received. - * The handle is obtained as the return value when the queue is created using - * the xQueueCreate() API function. - * - * @param pvBuffer The buffer into which the received item is to be copied. - * The number of bytes of each queued item is specified when the queue is - * created. This number of bytes is copied into pvBuffer. - * - * @param xTickToDelay The number of ticks that the co-routine should block - * to wait for data to become available from the queue, should data not be - * available immediately. The actual amount of time this equates to is defined - * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant - * portTICK_RATE_MS can be used to convert ticks to milliseconds (see the - * crQUEUE_SEND example). - * - * @param pxResult The variable pointed to by pxResult will be set to pdPASS if - * data was successfully retrieved from the queue, otherwise it will be set to - * an error code as defined within ProjDefs.h. - * - * Example usage: -

- // A co-routine receives the number of an LED to flash from a queue.  It 

- // blocks on the queue until the number is received.

- static void prvCoRoutineFlashWorkTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- static portBASE_TYPE xResult;

- static unsigned portBASE_TYPE uxLEDToFlash;

-

-    // All co-routines must start with a call to crSTART().

-    crSTART( xHandle );

-

-    for( ;; )

-    {

-        // Wait for data to become available on the queue.

-        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );

-

-        if( xResult == pdPASS )

-        {

-            // We received the LED to flash - flash it!

-            vParTestToggleLED( uxLEDToFlash );

-        }

-    }

-

-    crEND();

- }
- * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE - * \ingroup Tasks - */ -#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ -{ \ - *pxResult = xQueueCRReceive( pxQueue, pvBuffer, xTicksToWait ); \ - if( *pxResult == errQUEUE_BLOCKED ) \ - { \ - crSET_STATE0( xHandle ); \ - *pxResult = xQueueCRReceive( pxQueue, pvBuffer, 0 ); \ - } \ - if( *pxResult == errQUEUE_YIELD ) \ - { \ - crSET_STATE1( xHandle ); \ - *pxResult = pdPASS; \ - } \ -} - -/** - * croutine. h - *

-  crQUEUE_SEND_FROM_ISR( 

-                            xQueueHandle pxQueue, 

-                            void *pvItemToQueue, 

-                            portBASE_TYPE xCoRoutinePreviouslyWoken

-                       )
- * - * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the - * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() - * functions used by tasks. - * - * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to - * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and - * xQueueReceiveFromISR() can only be used to pass data between a task and and - * ISR. - * - * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue - * that is being used from within a co-routine. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto - * the same queue multiple times from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. - * - * @return pdTRUE if a co-routine was woken by posting onto the queue. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage: -

- // A co-routine that blocks on a queue waiting for characters to be received.

- static void vReceivingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- portCHAR cRxedChar;

- portBASE_TYPE xResult;

-

-     // All co-routines must start with a call to crSTART().

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-         // Wait for data to become available on the queue.  This assumes the

-         // queue xCommsRxQueue has already been created!

-         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );

-    

-         // Was a character received?

-         if( xResult == pdPASS )

-         {

-             // Process the character here.

-         }

-     }

-

-     // All co-routines must end with a call to crEND().

-     crEND();

- }

-

- // An ISR that uses a queue to send characters received on a serial port to

- // a co-routine.

- void vUART_ISR( void )

- {

- portCHAR cRxedChar;

- portBASE_TYPE xCRWokenByPost = pdFALSE;

-

-     // We loop around reading characters until there are none left in the UART.

-     while( UART_RX_REG_NOT_EMPTY() )

-     {

-         // Obtain the character from the UART.

-         cRxedChar = UART_RX_REG;

-        

-         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE 

-         // the first time around the loop.  If the post causes a co-routine

-         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.

-         // In this manner we can ensure that if more than one co-routine is

-         // blocked on the queue only one is woken by this ISR no matter how

-         // many characters are posted to the queue.

-         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );

-     }

- }
- * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR - * \ingroup Tasks - */ -#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) - - -/** - * croutine. h - *

-  crQUEUE_SEND_FROM_ISR( 

-                            xQueueHandle pxQueue, 

-                            void *pvBuffer, 

-                            portBASE_TYPE * pxCoRoutineWoken

-                       )
- * - * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the - * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() - * functions used by tasks. - * - * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to - * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and - * xQueueReceiveFromISR() can only be used to pass data between a task and and - * ISR. - * - * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data - * from a queue that is being used from within a co-routine (a co-routine - * posted to the queue). - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvBuffer A pointer to a buffer into which the received item will be - * placed. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from the queue into - * pvBuffer. - * - * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become - * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a - * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise - * *pxCoRoutineWoken will remain unchanged. - * - * @return pdTRUE an item was successfully received from the queue, otherwise - * pdFALSE. - * - * Example usage: -

- // A co-routine that posts a character to a queue then blocks for a fixed 

- // period.  The character is incremented each time.

- static void vSendingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // cChar holds its value while this co-routine is blocked and must therefore

- // be declared static.

- static portCHAR cCharToTx = 'a';

- portBASE_TYPE xResult;

-

-     // All co-routines must start with a call to crSTART().

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-         // Send the next character to the queue.

-         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );

-    

-         if( xResult == pdPASS )

-         {

-             // The character was successfully posted to the queue.

-         }

-		 else

-		 {

-			// Could not post the character to the queue.

-		 }

-

-         // Enable the UART Tx interrupt to cause an interrupt in this

-		 // hypothetical UART.  The interrupt will obtain the character

-		 // from the queue and send it.

-		 ENABLE_RX_INTERRUPT();

-

-		 // Increment to the next character then block for a fixed period. 

-		 // cCharToTx will maintain its value across the delay as it is

-		 // declared static.

-		 cCharToTx++;

-		 if( cCharToTx > 'x' )

-		 {

-			cCharToTx = 'a';

-		 }

-		 crDELAY( 100 );

-     }

-

-     // All co-routines must end with a call to crEND().

-     crEND();

- }

-

- // An ISR that uses a queue to receive characters to send on a UART.

- void vUART_ISR( void )

- {

- portCHAR cCharToTx;

- portBASE_TYPE xCRWokenByPost = pdFALSE;

-

-     while( UART_TX_REG_EMPTY() )

-     {

-         // Are there any characters in the queue waiting to be sent?

-		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine

-		 // is woken by the post - ensuring that only a single co-routine is

-		 // woken no matter how many times we go around this loop.

-         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )

-		 {

-			 SEND_CHARACTER( cCharToTx );

-		 }

-     }

- }
- * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR - * \ingroup Tasks - */ -#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( pxQueue, pvBuffer, pxCoRoutineWoken ) - -/* - * This function is intended for internal use by the co-routine macros only. - * The macro nature of the co-routine implementation requires that the - * prototype appears here. The function should not be used by application - * writers. - * - * Removes the current co-routine from its ready list and places it in the - * appropriate delayed list. - */ -void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList ); - -/* - * This function is intended for internal use by the queue implementation only. - * The function should not be used by application writers. - * - * Removes the highest priority co-routine from the event list and places it in - * the pending ready list. - */ -portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList ); - - -#endif /* CO_ROUTINE_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/list.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/list.h deleted file mode 100644 index ffa920c46..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/list.h +++ /dev/null @@ -1,270 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This is the list implementation used by the scheduler. While it is tailored - * heavily for the schedulers needs, it is also available for use by - * application code. - * - * xLists can only store pointers to xListItems. Each xListItem contains a - * numeric value (xItemValue). Most of the time the lists are sorted in - * descending item value order. - * - * Lists are created already containing one list item. The value of this - * item is the maximum possible that can be stored, it is therefore always at - * the end of the list and acts as a marker. The list member pxHead always - * points to this marker - even though it is at the tail of the list. This - * is because the tail contains a wrap back pointer to the true head of - * the list. - * - * In addition to it's value, each list item contains a pointer to the next - * item in the list (pxNext), a pointer to the list it is in (pxContainer) - * and a pointer to back to the object that contains it. These later two - * pointers are included for efficiency of list manipulation. There is - * effectively a two way link between the object containing the list item and - * the list item itself. - * - * - * \page ListIntroduction List Implementation - * \ingroup FreeRTOSIntro - */ - - -#ifndef LIST_H -#define LIST_H - -/* - * Definition of the only type of object that a list can contain. - */ -struct xLIST_ITEM -{ - portTickType xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ - volatile struct xLIST_ITEM * pxNext; /*< Pointer to the next xListItem in the list. */ - volatile struct xLIST_ITEM * pxPrevious;/*< Pointer to the previous xListItem in the list. */ - void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ - void * pvContainer; /*< Pointer to the list in which this list item is placed (if any). */ -}; -typedef struct xLIST_ITEM xListItem; /* For some reason lint wants this as two separate definitions. */ - -struct xMINI_LIST_ITEM -{ - portTickType xItemValue; - volatile struct xLIST_ITEM *pxNext; - volatile struct xLIST_ITEM *pxPrevious; -}; -typedef struct xMINI_LIST_ITEM xMiniListItem; - -/* - * Definition of the type of queue used by the scheduler. - */ -typedef struct xLIST -{ - volatile unsigned portBASE_TYPE uxNumberOfItems; - volatile xListItem * pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to pvListGetOwnerOfNextEntry (). */ - volatile xMiniListItem xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ -} xList; - -/* - * Access macro to set the owner of a list item. The owner of a list item - * is the object (usually a TCB) that contains the list item. - * - * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( pxListItem )->pvOwner = ( void * ) pxOwner - -/* - * Access macro to set the value of the list item. In most cases the value is - * used to sort the list in descending order. - * - * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( pxListItem )->xItemValue = xValue - -/* - * Access macro the retrieve the value of the list item. The value can - * represent anything - for example a the priority of a task, or the time at - * which a task should be unblocked. - * - * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) - -/* - * Access macro to determine if a list contains any items. The macro will - * only have the value true if the list is empty. - * - * \page listLIST_IS_EMPTY listLIST_IS_EMPTY - * \ingroup LinkedList - */ -#define listLIST_IS_EMPTY( pxList ) ( ( pxList )->uxNumberOfItems == ( unsigned portBASE_TYPE ) 0 ) - -/* - * Access macro to return the number of items in the list. - */ -#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) - -/* - * Access function to obtain the owner of the next entry in a list. - * - * The list member pxIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list - * and returns that entries pxOwner parameter. Using multiple calls to this - * function it is therefore possible to move through every item contained in - * a list. - * - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the next item owner is to be returned. - * - * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ - /* Increment the index to the next item and return the item, ensuring */ \ - /* we don't return the marker used at the end of the list. */ \ - ( pxList )->pxIndex = ( pxList )->pxIndex->pxNext; \ - if( ( pxList )->pxIndex == ( xListItem * ) &( ( pxList )->xListEnd ) ) \ - { \ - ( pxList )->pxIndex = ( pxList )->pxIndex->pxNext; \ - } \ - pxTCB = ( pxList )->pxIndex->pvOwner - - -/* - * Access function to obtain the owner of the first entry in a list. Lists - * are normally sorted in ascending item value order. - * - * This function returns the pxOwner member of the first item in the list. - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the owner of the head item is to be - * returned. - * - * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( pxList->uxNumberOfItems != ( unsigned portBASE_TYPE ) 0 ) ? ( (&( pxList->xListEnd ))->pxNext->pvOwner ) : ( NULL ) ) - -/* - * Check to see if a list item is within a list. The list item maintains a - * "container" pointer that points to the list it is in. All this macro does - * is check to see if the container and the list match. - * - * @param pxList The list we want to know if the list item is within. - * @param pxListItem The list item we want to know if is in the list. - * @return pdTRUE is the list item is in the list, otherwise pdFALSE. - * pointer against - */ -#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( pxListItem )->pvContainer == ( void * ) pxList ) - -/* - * Must be called before a list is used! This initialises all the members - * of the list structure and inserts the xListEnd item into the list as a - * marker to the back of the list. - * - * @param pxList Pointer to the list being initialised. - * - * \page vListInitialise vListInitialise - * \ingroup LinkedList - */ -void vListInitialise( xList *pxList ); - -/* - * Must be called before a list item is used. This sets the list container to - * null so the item does not think that it is already contained in a list. - * - * @param pxItem Pointer to the list item being initialised. - * - * \page vListInitialiseItem vListInitialiseItem - * \ingroup LinkedList - */ -void vListInitialiseItem( xListItem *pxItem ); - -/* - * Insert a list item into a list. The item will be inserted into the list in - * a position determined by its item value (descending item value order). - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The item to that is to be placed in the list. - * - * \page vListInsert vListInsert - * \ingroup LinkedList - */ -void vListInsert( xList *pxList, xListItem *pxNewListItem ); - -/* - * Insert a list item into a list. The item will be inserted in a position - * such that it will be the last item within the list returned by multiple - * calls to listGET_OWNER_OF_NEXT_ENTRY. - * - * The list member pvIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list. - * Placing an item in a list using vListInsertEnd effectively places the item - * in the list position pointed to by pvIndex. This means that every other - * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before - * the pvIndex parameter again points to the item being inserted. - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The list item to be inserted into the list. - * - * \page vListInsertEnd vListInsertEnd - * \ingroup LinkedList - */ -void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ); - -/* - * Remove an item from a list. The list item has a pointer to the list that - * it is in, so only the list item need be passed into the function. - * - * @param vListRemove The item to be removed. The item will remove itself from - * the list pointed to by it's pxContainer parameter. - * - * \page vListRemove vListRemove - * \ingroup LinkedList - */ -void vListRemove( xListItem *pxItemToRemove ); - - - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/portable.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/portable.h deleted file mode 100644 index 0b40be401..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/portable.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http:www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http:www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Portable layer API. Each function must be defined for each port. - *----------------------------------------------------------*/ - -#ifndef PORTABLE_H -#define PORTABLE_H - -/* Include the macro file relevant to the port being used. */ - -#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT - #include "..\..\source\portable\owatcom\16bitdos\pc\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT - #include "..\..\source\portable\owatcom\16bitdos\flsh186\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef GCC_MEGA_AVR - #include "../portable/GCC/ATMega323/portmacro.h" -#endif - -#ifdef IAR_MEGA_AVR - #include "../portable/IAR/ATMega323/portmacro.h" -#endif - -#ifdef MPLAB_PIC18F_PORT - #include "..\..\source\portable\MPLAB\PIC18F\portmacro.h" -#endif - -#ifdef _FEDPICC - #include "libFreeRTOS/Include/portmacro.h" -#endif - -#ifdef SDCC_CYGNAL - #include "../../Source/portable/SDCC/Cygnal/portmacro.h" -#endif - -#ifdef GCC_ARM7 - #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" -#endif - -#ifdef GCC_MSP430 - #include "../../Source/portable/GCC/MSP430F449/portmacro.h" -#endif - -#ifdef ROWLEY_MSP430 - #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" -#endif - -#ifdef KEIL_ARM7 - #include "..\..\Source\portable\Keil\ARM7\portmacro.h" -#endif - -#ifdef SAM7_GCC - #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" -#endif - -#ifdef SAM7_IAR - #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" -#endif - -#ifdef LPC2000_IAR - #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" -#endif - -#ifdef STR71X_IAR - #include "..\..\Source\portable\IAR\STR71x\portmacro.h" -#endif - -#ifdef STR91X_IAR - #include "..\..\Source\portable\IAR\STR91x\portmacro.h" -#endif - -#ifdef GCC_H8S - #include "../../Source/portable/GCC/H8S2329/portmacro.h" -#endif - -#ifdef GCC_AT91FR40008 - #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" -#endif - -#ifdef RVDS_ARMCM3_LM3S102 - #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" -#endif - -#ifdef GCC_ARMCM3_LM3S102 - #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" -#endif - -#ifdef IAR_ARMCM3_LM - #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" -#endif - -#ifdef HCS12_CODE_WARRIOR - #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" -#endif - -#ifdef MICROBLAZE_GCC - #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" -#endif - -#ifdef TERN_EE - #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" -#endif - -#ifdef GCC_HCS12 - #include "../../Source/portable/GCC/HCS12/portmacro.h" -#endif - -#ifdef GCC_MCF5235 - #include "../portable/GCC/MCF5235/portmacro.h" -#endif - -#ifdef BCC_INDUSTRIAL_PC_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef BCC_FLASH_LITE_186_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif -/* - * Setup the stack of a new task so it is ready to be placed under the - * scheduler control. The registers have to be placed on the stack in - * the order that the port expects to find them. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ); - -/* - * Map to the memory management routines required for the port. - */ -void *pvPortMalloc( size_t xSize ); -void vPortFree( void *pv ); -void vPortInitialiseBlocks( void ); - -/* - * Setup the hardware ready for the scheduler to take control. This generally - * sets up a tick interrupt and sets timers for the correct tick frequency. - */ -portBASE_TYPE xPortStartScheduler( void ); - -/* - * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so - * the hardware is left in its original condition after the scheduler stops - * executing. - */ -void vPortEndScheduler( void ); - - -#endif /* PORTABLE_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/projdefs.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/projdefs.h deleted file mode 100644 index 85f27879e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/projdefs.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PROJDEFS_H -#define PROJDEFS_H - -/* Defines to prototype to which task functions must conform. */ -typedef void (*pdTASK_CODE)( void * ); - -#define pdTRUE ( 1 ) -#define pdFALSE ( 0 ) - -#define pdPASS ( 1 ) -#define pdFAIL ( 0 ) - -/* Error definitions. */ -#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 ) -#define errNO_TASK_TO_RUN ( -2 ) -#define errQUEUE_FULL ( -3 ) -#define errQUEUE_BLOCKED ( -4 ) -#define errQUEUE_YIELD ( -5 ) - -#endif - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/queue.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/queue.h deleted file mode 100644 index c78e25a8f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/queue.h +++ /dev/null @@ -1,471 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef QUEUE_H -#define QUEUE_H - -typedef void * xQueueHandle; - -/** - * queue. h - *

- xQueueHandle xQueueCreate( 

-                              unsigned portBASE_TYPE uxQueueLength, 

-                              unsigned portBASE_TYPE uxItemSize 

-                          );

- * 
- * - * Creates a new queue instance. This allocates the storage required by the - * new queue and returns a handle for the queue. - * - * @param uxQueueLength The maximum number of items that the queue can contain. - * - * @param uxItemSize The number of bytes each item in the queue will require. - * Items are queued by copy, not by reference, so this is the number of bytes - * that will be copied for each posted item. Each item on the queue must be - * the same size. - * - * @return If the queue is successfully create then a handle to the newly - * created queue is returned. If the queue cannot be created then 0 is - * returned. - * - * Example usage: -

- struct AMessage

- {

-    portCHAR ucMessageID;

-    portCHAR ucData[ 20 ];

- };

-

- void vATask( void *pvParameters )

- {

- xQueueHandle xQueue1, xQueue2;

-

-    // Create a queue capable of containing 10 unsigned long values.

-    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );

-    if( xQueue1 == 0 )

-    {

-        // Queue was not created and must not be used.

-    }

-

-    // Create a queue capable of containing 10 pointers to AMessage structures.

-    // These should be passed by pointer as they contain a lot of data.

-    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );

-    if( xQueue2 == 0 )

-    {

-        // Queue was not created and must not be used.

-    }

-

-    // ... Rest of task code.

- }

- 
- * \defgroup xQueueCreate xQueueCreate - * \ingroup QueueManagement - */ -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); - -/** - * queue. h - *

- portBASE_TYPE xQueueSend( 

-                             xQueueHandle xQueue, 

-                             const void * pvItemToQueue, 

-                             portTickType xTicksToWait 

-                         );

- * 
- * - * Post an item on a queue. The item is queued by copy, not by reference. - * This function must not be called from an interrupt service routine. - * See xQueueSendFromISR () for an alternative which may be used in an ISR. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for space to become available on the queue, should it already - * be full. The call will return immediately if this is set to 0. The - * time is defined in tick periods so the constant portTICK_RATE_MS - * should be used to convert to real time if this is required. - * - * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. - * - * Example usage: -

- struct AMessage

- {

-    portCHAR ucMessageID;

-    portCHAR ucData[ 20 ];

- } xMessage;

-

- unsigned portLONG ulVar = 10UL;

-

- void vATask( void *pvParameters )

- {

- xQueueHandle xQueue1, xQueue2;

- struct AMessage *pxMessage;

-

-    // Create a queue capable of containing 10 unsigned long values.

-    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );

-

-    // Create a queue capable of containing 10 pointers to AMessage structures.

-    // These should be passed by pointer as they contain a lot of data.

-    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );

-

-    // ...

-

-    if( xQueue1 != 0 )

-    {

-        // Send an unsigned long.  Wait for 10 ticks for space to become 

-        // available if necessary.

-        if( xQueueSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )

-        {

-            // Failed to post the message, even after 10 ticks.

-        }

-    }

-

-    if( xQueue2 != 0 )

-    {

-        // Send a pointer to a struct AMessage object.  Don't block if the

-        // queue is already full.

-        pxMessage = & xMessage;

-        xQueueSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );

-    }

-

-	// ... Rest of task code.

- }

- 
- * \defgroup xQueueSend xQueueSend - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); - -/** - * queue. h - *

- portBASE_TYPE xQueueReceive( 

-                                xQueueHandle xQueue, 

-                                void *pvBuffer, 

-                                portTickType xTicksToWait 

-                            );
- * - * Receive an item from a queue. The item is received by copy so a buffer of - * adequate size must be provided. The number of bytes copied into the buffer - * was defined when the queue was created. - * - * This function must not be used in an interrupt service routine. See - * xQueueReceiveFromISR for an alternative that can. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pvBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for an item to receive should the queue be empty at the time - * of the call. The time is defined in tick periods so the constant - * portTICK_RATE_MS should be used to convert to real time if this is required. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: -

- struct AMessage

- {

-    portCHAR ucMessageID;

-    portCHAR ucData[ 20 ];

- } xMessage;

-

- xQueueHandle xQueue;

- 

- // Task to create a queue and post a value.

- void vATask( void *pvParameters )

- {

- struct AMessage *pxMessage;

-

-    // Create a queue capable of containing 10 pointers to AMessage structures.

-    // These should be passed by pointer as they contain a lot of data.

-    xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );

-    if( xQueue == 0 )

-    {

-        // Failed to create the queue.

-    }

-

-    // ...

-

-    // Send a pointer to a struct AMessage object.  Don't block if the

-    // queue is already full.

-    pxMessage = & xMessage;

-    xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );

-

-	// ... Rest of task code.

- }

-

- // Task to receive from the queue.

- void vADifferentTask( void *pvParameters )

- {

- struct AMessage *pxRxedMessage;

-

-    if( xQueue != 0 )

-    {

-        // Receive a message on the created queue.  Block for 10 ticks if a

-        // message is not immediately available.

-        if( xQueueReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )

-        {

-            // pcRxedMessage now points to the struct AMessage variable posted

-            // by vATask.

-        }

-    }

-

-	// ... Rest of task code.

- }

- 
- * \defgroup xQueueReceive xQueueReceive - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueReceive( xQueueHandle xQueue, void *pvBuffer, portTickType xTicksToWait ); - -/** - * queue. h - *
unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue );
- * - * Return the number of messages stored in a queue. - * - * @param xQueue A handle to the queue being queried. - * - * @return The number of messages available in the queue. - * - * \page uxQueueMessagesWaiting uxQueueMessagesWaiting - * \ingroup QueueManagement - */ -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue ); - -/** - * queue. h - *
void vQueueDelete( xQueueHandle xQueue );
- * - * Delete a queue - freeing all the memory allocated for storing of items - * placed on the queue. - * - * @param xQueue A handle to the queue to be deleted. - * - * \page vQueueDelete vQueueDelete - * \ingroup QueueManagement - */ -void vQueueDelete( xQueueHandle xQueue ); - -/** - * queue. h - *

- portBASE_TYPE xQueueSendFromISR( 

-                                    xQueueHandle pxQueue, 

-                                    const void *pvItemToQueue, 

-                                    portBASE_TYPE xTaskPreviouslyWoken 

-                                );

- 
- * - * Post an item on a queue. It is safe to use this function from within an - * interrupt service routine. - * - * Items are queued by copy not reference so it is preferable to only - * queue small items, especially when called from an ISR. In most cases - * it would be preferable to store a pointer to the item being queued. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param cTaskPreviouslyWoken This is included so an ISR can post onto - * the same queue multiple times from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. See the file serial .c in the - * PC port for a good example of this mechanism. - * - * @return pdTRUE if a task was woken by posting onto the queue. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage for buffered IO (where the ISR can obtain more than one value - * per call): -

- void vBufferISR( void )

- {

- portCHAR cIn;

- portBASE_TYPE xTaskWokenByPost;

-

-    // We have not woken a task at the start of the ISR.

-    cTaskWokenByPost = pdFALSE;

-

-    // Loop until the buffer is empty.

-    do

-    {

-        // Obtain a byte from the buffer.

-        cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );						

-

-        // Post the byte.  The first time round the loop cTaskWokenByPost

-        // will be pdFALSE.  If the queue send causes a task to wake we do

-        // not want the task to run until we have finished the ISR, so

-        // xQueueSendFromISR does not cause a context switch.  Also we 

-        // don't want subsequent posts to wake any other tasks, so we store

-        // the return value back into cTaskWokenByPost so xQueueSendFromISR

-        // knows not to wake any task the next iteration of the loop.

-        xTaskWokenByPost = xQueueSendFromISR( xRxQueue, &cIn, cTaskWokenByPost );

-

-    } while( portINPUT_BYTE( BUFFER_COUNT ) );

-

-    // Now the buffer is empty we can switch context if necessary.

-    if( cTaskWokenByPost )

-    {

-        taskYIELD ();

-    }

- }

- 
- * - * \defgroup xQueueSendFromISR xQueueSendFromISR - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ); - -/** - * queue. h - *

- portBASE_TYPE xQueueReceiveFromISR( 

-                                       xQueueHandle pxQueue, 

-                                       void *pvBuffer, 

-                                       portBASE_TYPE *pxTaskWoken 

-                                   ); 

- * 
- * - * Receive an item from a queue. It is safe to use this function from within an - * interrupt service routine. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pvBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param pxTaskWoken A task may be blocked waiting for space to become - * available on the queue. If xQueueReceiveFromISR causes such a task to - * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will - * remain unchanged. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: -

- 

- xQueueHandle xQueue;

- 

- // Function to create a queue and post some values.

- void vAFunction( void *pvParameters )

- {

- portCHAR cValueToPost;

- const portTickType xBlockTime = ( portTickType )0xff;

-

-    // Create a queue capable of containing 10 characters.

-    xQueue = xQueueCreate( 10, sizeof( portCHAR ) );

-    if( xQueue == 0 )

-    {

-        // Failed to create the queue.

-    }

-

-    // ...

-

-    // Post some characters that will be used within an ISR.  If the queue

-    // is full then this task will block for xBlockTime ticks.

-    cValueToPost = 'a';

-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );

-    cValueToPost = 'b';

-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );

-

-    // ... keep posting characters ... this task may block when the queue

-    // becomes full.

-

-    cValueToPost = 'c';

-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );

- }

-

- // ISR that outputs all the characters received on the queue. 

- void vISR_Routine( void )

- {

- portBASE_TYPE xTaskWokenByReceive = pdFALSE;

- portCHAR cRxedChar;

-

-    while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )

-    {

-        // A character was received.  Output the character now.

-        vOutputCharacter( cRxedChar );

-

-        // If removing the character from the queue woke the task that was 

-        // posting onto the queue cTaskWokenByReceive will have been set to

-        // pdTRUE.  No matter how many times this loop iterates only one

-        // task will be woken.

-    }

-

-    if( cTaskWokenByPost != ( portCHAR ) pdFALSE;

-    {

-        taskYIELD ();

-    }

- }

- 
- * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - - -/* - * The functions defined above are for passing data to and from tasks. The - * functions below are the equivalents for passing data to and from - * co-rtoutines. - * - * These functions are called from the co-routine macro implementation and - * should not be called directly from application code. Instead use the macro - * wrappers defined within croutine.h. - */ -signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ); -signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); -signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ); -signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/semphr.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/semphr.h deleted file mode 100644 index 4b9020b97..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/semphr.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include "queue.h" - -#ifndef SEMAPHORE_H -#define SEMAPHORE_H - -typedef xQueueHandle xSemaphoreHandle; - -#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( unsigned portCHAR ) 1 ) -#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( unsigned portCHAR ) 0 ) -#define semGIVE_BLOCK_TIME ( ( portTickType ) 0 ) - - -/** - * semphr. h - *
vSemaphoreCreateBinary( xSemaphoreHandle xSemaphore )
- * - * Macro that implements a semaphore by using the existing queue mechanism. - * The queue length is 1 as this is a binary semaphore. The data size is 0 - * as we don't want to actually store any data - we just want to know if the - * queue is empty or full. - * - * @param xSemaphore Handle to the created semaphore. Should be of type xSemaphoreHandle. - * - * Example usage: -

- xSemaphoreHandle xSemaphore;

-

- void vATask( void * pvParameters )

- {

-    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().

-    // This is a macro so pass the variable in directly.

-    vSemaphoreCreateBinary( xSemaphore );

-

-    if( xSemaphore != NULL )

-    {

-        // The semaphore was created successfully.

-        // The semaphore can now be used.  

-    }

- }

- 
- * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary - * \ingroup Semaphores - */ -#define vSemaphoreCreateBinary( xSemaphore ) { \ - xSemaphore = xQueueCreate( ( unsigned portCHAR ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH ); \ - if( xSemaphore != NULL ) \ - { \ - xSemaphoreGive( xSemaphore ); \ - } \ - } - -/** - * semphr. h - * xSemaphoreTake( - * xSemaphoreHandle xSemaphore, - * portTickType xBlockTime - * ) - * - * Macro to obtain a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (). - * - * @param xSemaphore A handle to the semaphore being obtained. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @param xBlockTime The time in ticks to wait for the semaphore to become - * available. The macro portTICK_RATE_MS can be used to convert this to a - * real time. A block time of zero can be used to poll the semaphore. - * - * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime - * expired without the semaphore becoming available. - * - * Example usage: -

- xSemaphoreHandle xSemaphore = NULL;

-

- // A task that creates a semaphore.

- void vATask( void * pvParameters )

- {

-    // Create the semaphore to guard a shared resource.

-    vSemaphoreCreateBinary( xSemaphore );

- }

-

- // A task that uses the semaphore.

- void vAnotherTask( void * pvParameters )

- {

-    // ... Do other things.

-

-    if( xSemaphore != NULL )

-    {

-        // See if we can obtain the semaphore.  If the semaphore is not available

-        // wait 10 ticks to see if it becomes free.	

-        if( xSemaphoreTake( xSemaphore, ( portTickType ) 10 ) == pdTRUE )

-        {

-            // We were able to obtain the semaphore and can now access the

-            // shared resource.

-

-            // ...

-

-            // We have finished accessing the shared resource.  Release the 

-            // semaphore.

-            xSemaphoreGive( xSemaphore );

-        }

-        else

-        {

-            // We could not obtain the semaphore and can therefore not access

-            // the shared resource safely.

-        }

-    }

- }

- 
- * \defgroup xSemaphoreTake xSemaphoreTake - * \ingroup Semaphores - */ -#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueReceive( ( xQueueHandle ) xSemaphore, NULL, xBlockTime ) - -/** - * semphr. h - *
xSemaphoreGive( xSemaphoreHandle xSemaphore )
- * - * Macro to release a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (), and obtained using sSemaphoreTake (). - * - * This must not be used from an ISR. See xSemaphoreGiveFromISR () for - * an alternative which can be used from an ISR. - * - * @param xSemaphore A handle to the semaphore being released. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. - * Semaphores are implemented using queues. An error can occur if there is - * no space on the queue to post a message - indicating that the - * semaphore was not first obtained correctly. - * - * Example usage: -

- xSemaphoreHandle xSemaphore = NULL;

-

- void vATask( void * pvParameters )

- {

-    // Create the semaphore to guard a shared resource.

-    vSemaphoreCreateBinary( xSemaphore );

-

-    if( xSemaphore != NULL )

-    {

-        if( xSemaphoreGive( xSemaphore ) != pdTRUE )

-        {

-            // We would expect this call to fail because we cannot give

-            // a semaphore without first "taking" it!

-        }

-

-        // Obtain the semaphore - don't block if the semaphore is not

-        // immediately available.

-        if( xSemaphoreTake( xSemaphore, ( portTickType ) 0 ) )

-        {

-            // We now have the semaphore and can access the shared resource.

-

-            // ...

-

-            // We have finished accessing the shared resource so can free the

-            // semaphore.

-            if( xSemaphoreGive( xSemaphore ) != pdTRUE )

-            {

-                // We would not expect this call to fail because we must have

-                // obtained the semaphore to get here.

-            }

-        }

-    }

- }

- 
- * \defgroup xSemaphoreGive xSemaphoreGive - * \ingroup Semaphores - */ -#define xSemaphoreGive( xSemaphore ) xQueueSend( ( xQueueHandle ) xSemaphore, NULL, semGIVE_BLOCK_TIME ) - -/** - * semphr. h - *

- xSemaphoreGiveFromISR( 

-                          xSemaphoreHandle xSemaphore, 

-                          portSHORT sTaskPreviouslyWoken 

-                      )
- * - * Macro to release a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (), and obtained using xSemaphoreTake (). - * - * This macro can be used from an ISR. - * - * @param xSemaphore A handle to the semaphore being released. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @param sTaskPreviouslyWoken This is included so an ISR can make multiple calls - * to xSemaphoreGiveFromISR () from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. See the file serial .c in the - * PC port for a good example of using xSemaphoreGiveFromISR (). - * - * @return pdTRUE if a task was woken by releasing the semaphore. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage: -

- #define LONG_TIME 0xffff

- #define TICKS_TO_WAIT	10

- xSemaphoreHandle xSemaphore = NULL;

-

- // Repetitive task.

- void vATask( void * pvParameters )

- {

-    for( ;; )

-    {

-        // We want this task to run every 10 ticks or a timer.  The semaphore 

-        // was created before this task was started

-

-        // Block waiting for the semaphore to become available.

-        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )

-        {

-            // It is time to execute.

-

-            // ...

-

-            // We have finished our task.  Return to the top of the loop where

-            // we will block on the semaphore until it is time to execute 

-            // again.

-        }

-    }

- }

-

- // Timer ISR

- void vTimerISR( void * pvParameters )

- {

- static unsigned portCHAR ucLocalTickCount = 0;

-

-    // A timer tick has occurred.

-

-    // ... Do other time functions.

-

-    // Is it time for vATask () to run?

-    ucLocalTickCount++;

-    if( ucLocalTickCount >= TICKS_TO_WAIT )

-    {

-        // Unblock the task by releasing the semaphore.

-        xSemaphoreGive( xSemaphore );

-

-        // Reset the count so we release the semaphore again in 10 ticks time.

-        ucLocalTickCount = 0;

-    }

- }

- 
- * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR - * \ingroup Semaphores - */ -#define xSemaphoreGiveFromISR( xSemaphore, xTaskPreviouslyWoken ) xQueueSendFromISR( ( xQueueHandle ) xSemaphore, NULL, xTaskPreviouslyWoken ) - - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/serial.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/serial.h deleted file mode 100644 index 674ce1c51..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/serial.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef SERIAL_COMMS_H -#define SERIAL_COMMS_H - -typedef void * xComPortHandle; - -typedef enum -{ - serCOM1, - serCOM2, - serCOM3, - serCOM4, - serCOM5, - serCOM6, - serCOM7, - serCOM8 -} eCOMPort; - -typedef enum -{ - serNO_PARITY, - serODD_PARITY, - serEVEN_PARITY, - serMARK_PARITY, - serSPACE_PARITY -} eParity; - -typedef enum -{ - serSTOP_1, - serSTOP_2 -} eStopBits; - -typedef enum -{ - serBITS_5, - serBITS_6, - serBITS_7, - serBITS_8 -} eDataBits; - -typedef enum -{ - ser50, - ser75, - ser110, - ser134, - ser150, - ser200, - ser300, - ser600, - ser1200, - ser1800, - ser2400, - ser4800, - ser9600, - ser19200, - ser38400, - ser57600, - ser115200 -} eBaud; - -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ); -xComPortHandle xSerialPortInit( eCOMPort ePort, eBaud eWantedBaud, eParity eWantedParity, eDataBits eWantedDataBits, eStopBits eWantedStopBits, unsigned portBASE_TYPE uxBufferLength ); -void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength ); -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ); -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ); -portBASE_TYPE xSerialWaitForSemaphore( xComPortHandle xPort ); -void vSerialClose( xComPortHandle xPort ); - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/task.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/task.h deleted file mode 100644 index 4872d73a6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/include/task.h +++ /dev/null @@ -1,926 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef TASK_H -#define TASK_H - -#include "portable.h" -#include "list.h" - -/*----------------------------------------------------------- - * MACROS AND DEFINITIONS - *----------------------------------------------------------*/ - -#define tskKERNEL_VERSION_NUMBER "V4.0.5" - -/** - * task. h - * - * Type by which tasks are referenced. For example, a call to xTaskCreate - * returns (via a pointer parameter) an xTaskHandle variable that can then - * be used as a parameter to vTaskDelete to delete the task. - * - * \page xTaskHandle xTaskHandle - * \ingroup Tasks - */ -typedef void * xTaskHandle; - -/* - * Defines the priority used by the idle task. This must not be modified. - * - * \ingroup TaskUtils - */ -#define tskIDLE_PRIORITY ( ( unsigned portBASE_TYPE ) 0 ) - -/** - * task. h - * - * Macro for forcing a context switch. - * - * \page taskYIELD taskYIELD - * \ingroup SchedulerControl - */ -#define taskYIELD() portYIELD() - -/** - * task. h - * - * Macro to mark the start of a critical code region. Preemptive context - * switches cannot occur when in a critical region. - * - * NOTE: This may alter the stack (depending on the portable implementation) - * so must be used with care! - * - * \page taskENTER_CRITICAL taskENTER_CRITICAL - * \ingroup SchedulerControl - */ -#define taskENTER_CRITICAL() portENTER_CRITICAL() - -/** - * task. h - * - * Macro to mark the end of a critical code region. Preemptive context - * switches cannot occur when in a critical region. - * - * NOTE: This may alter the stack (depending on the portable implementation) - * so must be used with care! - * - * \page taskEXIT_CRITICAL taskEXIT_CRITICAL - * \ingroup SchedulerControl - */ -#define taskEXIT_CRITICAL() portEXIT_CRITICAL() - -/** - * task. h - * - * Macro to disable all maskable interrupts. - * - * \page taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS - * \ingroup SchedulerControl - */ -#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() - -/** - * task. h - * - * Macro to enable microcontroller interrupts. - * - * \page taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS - * \ingroup SchedulerControl - */ -#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() - - -/*----------------------------------------------------------- - * TASK CREATION API - *----------------------------------------------------------*/ - -/** - * task. h - *

- portBASE_TYPE xTaskCreate(

-                              pdTASK_CODE pvTaskCode,

-                              const portCHAR * const pcName,

-                              unsigned portSHORT usStackDepth,

-                              void *pvParameters,

-                              unsigned portBASE_TYPE uxPriority,

-                              xTaskHandle *pvCreatedTask

-                          );
- * - * Create a new task and add it to the list of tasks that are ready to run. - * - * @param pvTaskCode Pointer to the task entry function. Tasks - * must be implemented to never return (i.e. continuous loop). - * - * @param pcName A descriptive name for the task. This is mainly used to - * facilitate debugging. Max length defined by tskMAX_TASK_NAME_LEN - default - * is 16. - * - * @param usStackDepth The size of the task stack specified as the number of - * variables the stack can hold - not the number of bytes. For example, if - * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes - * will be allocated for stack storage. - * - * @param pvParameters Pointer that will be used as the parameter for the task - * being created. - * - * @param uxPriority The priority at which the task should run. - * - * @param pvCreatedTask Used to pass back a handle by which the created task - * can be referenced. - * - * @return pdPASS if the task was successfully created and added to a ready - * list, otherwise an error code defined in the file errors. h - * - * Example usage: -

- // Task to be created.

- void vTaskCode( void * pvParameters )

- {

-     for( ;; )

-     {

-         // Task code goes here.

-     }

- }

-

- // Function that creates a task.

- void vOtherFunction( void )

- {

- unsigned char ucParameterToPass;

- xTaskHandle xHandle;

-		

-     // Create the task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );

-		

-     // Use the handle to delete the task.

-     vTaskDelete( xHandle );

- }

-   
- * \defgroup xTaskCreate xTaskCreate - * \ingroup Tasks - */ -signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pvCreatedTask ); - -/** - * task. h - *
void vTaskDelete( xTaskHandle pxTask );
- * - * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Remove a task from the RTOS real time kernels management. The task being - * deleted will be removed from all ready, blocked, suspended and event lists. - * - * NOTE: The idle task is responsible for freeing the kernel allocated - * memory from tasks that have been deleted. It is therefore important that - * the idle task is not starved of microcontroller processing time if your - * application makes any calls to vTaskDelete (). Memory allocated by the - * task code is not automatically freed, and should be freed before the task - * is deleted. - * - * See the demo application file death.c for sample code that utilises - * vTaskDelete (). - * - * @param pxTask The handle of the task to be deleted. Passing NULL will - * cause the calling task to be deleted. - * - * Example usage: -

- void vOtherFunction( void )

- {

- xTaskHandle xHandle;

-		

-     // Create the task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

-		

-     // Use the handle to delete the task.

-     vTaskDelete( xHandle );

- }

-   
- * \defgroup vTaskDelete vTaskDelete - * \ingroup Tasks - */ -void vTaskDelete( xTaskHandle pxTask ); - - -/*----------------------------------------------------------- - * TASK CONTROL API - *----------------------------------------------------------*/ - -/** - * task. h - *
void vTaskDelay( portTickType xTicksToDelay );
- * - * Delay a task for a given number of ticks. The actual time that the - * task remains blocked depends on the tick rate. The constant - * portTICK_RATE_MS can be used to calculate real time from the tick - * rate - with the resolution of one tick period. - * - * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * @param xTicksToDelay The amount of time, in tick periods, that - * the calling task should block. - * - * Example usage: -

- // Wait 10 ticks before performing an action.

- // NOTE:

- // This is for demonstration only and would be better achieved

- // using vTaskDelayUntil ().

- void vTaskFunction( void * pvParameters )

- {

- portTickType xDelay, xNextTime;

-

-     // Calc the time at which we want to perform the action

-     // next.

-     xNextTime = xTaskGetTickCount () + ( portTickType ) 10;

-

-     for( ;; )

-     {

-         xDelay = xNextTime - xTaskGetTickCount ();

-         xNextTime += ( portTickType ) 10;

-

-         // Guard against overflow

-         if( xDelay <= ( portTickType ) 10 )

-         {

-             vTaskDelay( xDelay );

-         }

-

-         // Perform action here.

-     }

- }

-   
- * \defgroup vTaskDelay vTaskDelay - * \ingroup TaskCtrl - */ -void vTaskDelay( portTickType xTicksToDelay ); - -/** - * task. h - *
void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement );
- * - * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Delay a task until a specified time. This function can be used by cyclical - * tasks to ensure a constant execution frequency. - * - * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will - * cause a task to block for the specified number of ticks from the time vTaskDelay () is - * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed - * execution frequency as the time between a task starting to execute and that task - * calling vTaskDelay () may not be fixed [the task may take a different path though the - * code between calls, or may get interrupted or preempted a different number of times - * each time it executes]. - * - * Whereas vTaskDelay () specifies a wake time relative to the time at which the function - * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to - * unblock. - * - * The constant portTICK_RATE_MS can be used to calculate real time from the tick - * rate - with the resolution of one tick period. - * - * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the - * task was last unblocked. The variable must be initialised with the current time - * prior to its first use (see the example below). Following this the variable is - * automatically updated within vTaskDelayUntil (). - * - * @param xTimeIncrement The cycle time period. The task will be unblocked at - * time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the - * same xTimeIncrement parameter value will cause the task to execute with - * a fixed interface period. - * - * Example usage: -

- // Perform an action every 10 ticks.

- void vTaskFunction( void * pvParameters )

- {

- portTickType xLastWakeTime;

- const portTickType xFrequency = 10;

-

-     // Initialise the xLastWakeTime variable with the current time.

-     xLastWakeTime = xTaskGetTickCount ();

-     for( ;; )

-     {

-         // Wait for the next cycle.

-         vTaskDelayUntil( &xLastWakeTime, xFrequency );

-

-         // Perform action here.

-     }

- }

-   
- * \defgroup vTaskDelayUntil vTaskDelayUntil - * \ingroup TaskCtrl - */ -void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement ); - -/** - * task. h - *
unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask );
- * - * INCLUDE_xTaskPriorityGet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Obtain the priority of any task. - * - * @param pxTask Handle of the task to be queried. Passing a NULL - * handle results in the priority of the calling task being returned. - * - * @return The priority of pxTask. - * - * Example usage: -

- void vAFunction( void )

- {

- xTaskHandle xHandle;

-		

-     // Create a task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

-		

-     // ...

-

-     // Use the handle to obtain the priority of the created task.

-     // It was created with tskIDLE_PRIORITY, but may have changed

-     // it itself.

-     if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )

-     {

-         // The task has changed it's priority.

-     }

-

-     // ...

-

-     // Is our priority higher than the created task?

-     if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )

-     {

-         // Our priority (obtained using NULL handle) is higher.

-     }

- }

-   
- * \defgroup uxTaskPriorityGet uxTaskPriorityGet - * \ingroup TaskCtrl - */ -unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ); - -/** - * task. h - *
void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );
- * - * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Set the priority of any task. - * - * A context switch will occur before the function returns if the priority - * being set is higher than the currently executing task. - * - * @param pxTask Handle to the task for which the priority is being set. - * Passing a NULL handle results in the priority of the calling task being set. - * - * @param uxNewPriority The priority to which the task will be set. - * - * Example usage: -

- void vAFunction( void )

- {

- xTaskHandle xHandle;

-		

-     // Create a task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

-

-     // ...

-

-     // Use the handle to raise the priority of the created task.

-     vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );

-

-     // ...

-

-     // Use a NULL handle to raise our priority to the same value.

-     vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );

- }

-   
- * \defgroup vTaskPrioritySet vTaskPrioritySet - * \ingroup TaskCtrl - */ -void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ); - -/** - * task. h - *
void vTaskSuspend( xTaskHandle pxTaskToSuspend );
- * - * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Suspend any task. When suspended a task will never get any microcontroller - * processing time, no matter what its priority. - * - * Calls to vTaskSuspend are not accumulative - - * i.e. calling vTaskSuspend () twice on the same task still only requires one - * call to vTaskResume () to ready the suspended task. - * - * @param pxTaskToSuspend Handle to the task being suspended. Passing a NULL - * handle will cause the calling task to be suspended. - * - * Example usage: -

- void vAFunction( void )

- {

- xTaskHandle xHandle;

-		

-     // Create a task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

-		

-     // ...

-

-     // Use the handle to suspend the created task.

-     vTaskSuspend( xHandle );

-

-     // ...

-		

-     // The created task will not run during this period, unless

-     // another task calls vTaskResume( xHandle ).

-		

-     //...

-		

-

-     // Suspend ourselves.

-     vTaskSuspend( NULL );

-

-     // We cannot get here unless another task calls vTaskResume

-     // with our handle as the parameter.

- }

-   
- * \defgroup vTaskSuspend vTaskSuspend - * \ingroup TaskCtrl - */ -void vTaskSuspend( xTaskHandle pxTaskToSuspend ); - -/** - * task. h - *
void vTaskResume( xTaskHandle pxTaskToResume );
- * - * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Resumes a suspended task. - * - * A task that has been suspended by one of more calls to vTaskSuspend () - * will be made available for running again by a single call to - * vTaskResume (). - * - * @param pxTaskToResume Handle to the task being readied. - * - * Example usage: -

- void vAFunction( void )

- {

- xTaskHandle xHandle;

-		

-     // Create a task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

-		

-     // ...

-

-     // Use the handle to suspend the created task.

-     vTaskSuspend( xHandle );

-

-     // ...

-	

-     // The created task will not run during this period, unless

-     // another task calls vTaskResume( xHandle ).

-		

-     //...

-		

-

-     // Resume the suspended task ourselves.

-     vTaskResume( xHandle );

-

-     // The created task will once again get microcontroller processing

-     // time in accordance with it priority within the system.

- }

-   
- * \defgroup vTaskResume vTaskResume - * \ingroup TaskCtrl - */ -void vTaskResume( xTaskHandle pxTaskToResume ); - -/** - * task. h - *
void xTaskResumeFromISR( xTaskHandle pxTaskToResume );
- * - * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be - * available. See the configuration section for more information. - * - * An implementation of vTaskResume() that can be called from within an ISR. - * - * A task that has been suspended by one of more calls to vTaskSuspend () - * will be made available for running again by a single call to - * xTaskResumeFromISR (). - * - * @param pxTaskToResume Handle to the task being readied. - * - * \defgroup vTaskResumeFromISR vTaskResumeFromISR - * \ingroup TaskCtrl - */ -portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ); - -/*----------------------------------------------------------- - * SCHEDULER CONTROL - *----------------------------------------------------------*/ - -/** - * task. h - *
void vTaskStartScheduler( void );
- * - * Starts the real time kernel tick processing. After calling the kernel - * has control over which tasks are executed and when. This function - * does not return until an executing task calls vTaskEndScheduler (). - * - * At least one task should be created via a call to xTaskCreate () - * before calling vTaskStartScheduler (). The idle task is created - * automatically when the first application task is created. - * - * See the demo application file main.c for an example of creating - * tasks and starting the kernel. - * - * Example usage: -

- void vAFunction( void )

- {

-     // Create at least one task before starting the kernel.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );

-

-     // Start the real time kernel with preemption.

-     vTaskStartScheduler ();

-

-     // Will not get here unless a task calls vTaskEndScheduler ()

- }

-   
- * - * \defgroup vTaskStartScheduler vTaskStartScheduler - * \ingroup SchedulerControl - */ -void vTaskStartScheduler( void ); - -/** - * task. h - *
void vTaskEndScheduler( void );
- * - * Stops the real time kernel tick. All created tasks will be automatically - * deleted and multitasking (either preemptive or cooperative) will - * stop. Execution then resumes from the point where vTaskStartScheduler () - * was called, as if vTaskStartScheduler () had just returned. - * - * See the demo application file main. c in the demo/PC directory for an - * example that uses vTaskEndScheduler (). - * - * vTaskEndScheduler () requires an exit function to be defined within the - * portable layer (see vPortEndScheduler () in port. c for the PC port). This - * performs hardware specific operations such as stopping the kernel tick. - * - * vTaskEndScheduler () will cause all of the resources allocated by the - * kernel to be freed - but will not free resources allocated by application - * tasks. - * - * Example usage: -

- void vTaskCode( void * pvParameters )

- {

-     for( ;; )

-     {

-         // Task code goes here.

-

-         // At some point we want to end the real time kernel processing

-         // so call ...

-         vTaskEndScheduler ();

-     }

- }

-

- void vAFunction( void )

- {

-     // Create at least one task before starting the kernel.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );

-

-     // Start the real time kernel with preemption.

-     vTaskStartScheduler ();

-

-     // Will only get here when the vTaskCode () task has called

-     // vTaskEndScheduler ().  When we get here we are back to single task

-     // execution.

- }

-   
- * - * \defgroup vTaskEndScheduler vTaskEndScheduler - * \ingroup SchedulerControl - */ -void vTaskEndScheduler( void ); - -/** - * task. h - *
void vTaskSuspendAll( void );
- * - * Suspends all real time kernel activity while keeping interrupts (including the - * kernel tick) enabled. - * - * After calling vTaskSuspendAll () the calling task will continue to execute - * without risk of being swapped out until a call to xTaskResumeAll () has been - * made. - * - * Example usage: -

- void vTask1( void * pvParameters )

- {

-     for( ;; )

-     {

-         // Task code goes here.

-

-         // ...

-

-         // At some point the task wants to perform a long operation during

-         // which it does not want to get swapped out.  It cannot use

-         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the

-         // operation may cause interrupts to be missed - including the

-         // ticks.

-

-         // Prevent the real time kernel swapping out the task.

-         vTaskSuspendAll ();

-

-         // Perform the operation here.  There is no need to use critical

-         // sections as we have all the microcontroller processing time.

-         // During this time interrupts will still operate and the kernel

-         // tick count will be maintained.

-

-         // ...

-

-         // The operation is complete.  Restart the kernel.

-         xTaskResumeAll ();

-     }

- }

-   
- * \defgroup vTaskSuspendAll vTaskSuspendAll - * \ingroup SchedulerControl - */ -void vTaskSuspendAll( void ); - -/** - * task. h - *
portCHAR xTaskResumeAll( void );
- * - * Resumes real time kernel activity following a call to vTaskSuspendAll (). - * After a call to vTaskSuspendAll () the kernel will take control of which - * task is executing at any time. - * - * @return If resuming the scheduler caused a context switch then pdTRUE is - * returned, otherwise pdFALSE is returned. - * - * Example usage: -

- void vTask1( void * pvParameters )

- {

-     for( ;; )

-     {

-         // Task code goes here.

-

-         // ...

-

-         // At some point the task wants to perform a long operation during

-         // which it does not want to get swapped out.  It cannot use

-         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the

-         // operation may cause interrupts to be missed - including the

-         // ticks.

-

-         // Prevent the real time kernel swapping out the task.

-         vTaskSuspendAll ();

-

-         // Perform the operation here.  There is no need to use critical

-         // sections as we have all the microcontroller processing time.

-         // During this time interrupts will still operate and the real

-         // time kernel tick count will be maintained.

-

-         // ...

-

-         // The operation is complete.  Restart the kernel.  We want to force

-         // a context switch - but there is no point if resuming the scheduler

-         // caused a context switch already.

-         if( !xTaskResumeAll () )

-         {

-              taskYIELD ();

-         }

-     }

- }

-   
- * \defgroup xTaskResumeAll xTaskResumeAll - * \ingroup SchedulerControl - */ -signed portBASE_TYPE xTaskResumeAll( void ); - - -/*----------------------------------------------------------- - * TASK UTILITIES - *----------------------------------------------------------*/ - -/** - * task. h - *
volatile portTickType xTaskGetTickCount( void );
- * - * @return The count of ticks since vTaskStartScheduler was called. - * - * \page xTaskGetTickCount xTaskGetTickCount - * \ingroup TaskUtils - */ -portTickType xTaskGetTickCount( void ); - -/** - * task. h - *
unsigned portSHORT uxTaskGetNumberOfTasks( void );
- * - * @return The number of tasks that the real time kernel is currently managing. - * This includes all ready, blocked and suspended tasks. A task that - * has been deleted but not yet freed by the idle task will also be - * included in the count. - * - * \page uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks - * \ingroup TaskUtils - */ -unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ); - -/** - * task. h - *
void vTaskList( portCHAR *pcWriteBuffer );
- * - * configUSE_TRACE_FACILITY, INCLUDE_vTaskDelete and INCLUDE_vTaskSuspend - * must all be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * NOTE: This function will disable interrupts for its duration. It is - * not intended for normal application runtime use but as a debug aid. - * - * Lists all the current tasks, along with their current state and stack - * usage high water mark. - * - * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or - * suspended ('S'). - * - * @param pcWriteBuffer A buffer into which the above mentioned details - * will be written, in ascii form. This buffer is assumed to be large - * enough to contain the generated report. Approximately 40 bytes per - * task should be sufficient. - * - * \page vTaskList vTaskList - * \ingroup TaskUtils - */ -void vTaskList( signed portCHAR *pcWriteBuffer ); - -/** - * task. h - *
void vTaskStartTrace( portCHAR * pcBuffer, unsigned portBASE_TYPE uxBufferSize );
- * - * Starts a real time kernel activity trace. The trace logs the identity of - * which task is running when. - * - * The trace file is stored in binary format. A separate DOS utility called - * convtrce.exe is used to convert this into a tab delimited text file which - * can be viewed and plotted in a spread sheet. - * - * @param pcBuffer The buffer into which the trace will be written. - * - * @param ulBufferSize The size of pcBuffer in bytes. The trace will continue - * until either the buffer in full, or ulTaskEndTrace () is called. - * - * \page vTaskStartTrace vTaskStartTrace - * \ingroup TaskUtils - */ -void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ); - -/** - * task. h - *
unsigned portLONG ulTaskEndTrace( void );
- * - * Stops a kernel activity trace. See vTaskStartTrace (). - * - * @return The number of bytes that have been written into the trace buffer. - * - * \page usTaskEndTrace usTaskEndTrace - * \ingroup TaskUtils - */ -unsigned portLONG ulTaskEndTrace( void ); - - -/*----------------------------------------------------------- - * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES - *----------------------------------------------------------*/ - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY - * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS - * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * Called from the real time kernel tick (either preemptive or cooperative), - * this increments the tick count and checks if any tasks that are blocked - * for a finite period required removing from a blocked list and placing on - * a ready list. - */ -inline void vTaskIncrementTick( void ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. - * - * Removes the calling task from the ready list and places it both - * on the list of tasks waiting for a particular event, and the - * list of delayed tasks. The task will be removed from both lists - * and replaced on the ready list should either the event occur (and - * there be no higher priority tasks waiting on the same event) or - * the delay period expires. - * - * @param pxEventList The list containing tasks that are blocked waiting - * for the event to occur. - * - * @param xTicksToWait The maximum amount of time that the task should wait - * for the event to occur. This is specified in kernel ticks,the constant - * portTICK_RATE_MS can be used to convert kernel ticks into a real time - * period. - */ -void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. - * - * Removes a task from both the specified event list and the list of blocked - * tasks, and places it on a ready queue. - * - * xTaskRemoveFromEventList () will be called if either an event occurs to - * unblock a task, or the block timeout period expires. - * - * @return pdTRUE if the task being removed has a higher priority than the task - * making the call, otherwise pdFALSE. - */ -signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * INCLUDE_vTaskCleanUpResources and INCLUDE_vTaskSuspend must be defined as 1 - * for this function to be available. - * See the configuration section for more information. - * - * Empties the ready and delayed queues of task control blocks, freeing the - * memory allocated for the task control block and task stacks as it goes. - */ -void vTaskCleanUpResources( void ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY - * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS - * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * Sets the pointer to the current TCB to the TCB of the highest priority task - * that is ready to run. - */ -inline void vTaskSwitchContext( void ); - -/* - * Return the handle of the calling task. - */ -xTaskHandle xTaskGetCurrentTaskHandle( void ); - - -#endif /* TASK_H */ - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/list.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/list.c deleted file mode 100644 index a4e6b7e1a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/list.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.2.0 - - + Removed the volatile modifier from the function parameters. This was - only ever included to prevent compiler warnings. Now warnings are - removed by casting parameters where the calls are made. - - + prvListGetOwnerOfNextEntry() and prvListGetOwnerOfHeadEntry() have been - removed from the c file and added as macros to the h file. - - + uxNumberOfItems has been added to the list structure. This removes the - need for a pointer comparison when checking if a list is empty, and so - is slightly faster. - - + Removed the NULL check in vListRemove(). This makes the call faster but - necessitates any application code utilising the list implementation to - ensure NULL pointers are not passed. - -Changes from V2.0.0 - - + Double linked the lists to allow faster removal item removal. - -Changes from V2.6.1 - - + Make use of the new portBASE_TYPE definition where ever appropriate. - -Changes from V3.0.0 - - + API changes as described on the FreeRTOS.org WEB site. - -Changes from V3.2.4 - - + Removed the pxHead member of the xList structure. This always pointed - to the same place so has been removed to free a few bytes of RAM. - - + Introduced the xMiniListItem structure that does not include the - xListItem members that are not required by the xListEnd member of a list. - Again this was done to reduce RAM usage. - - + Changed the volatile definitions of some structure members to clean up - the code where the list structures are used. - -Changes from V4.0.4 - - + Optimised vListInsert() in the case when the wake time is the maximum - tick count value. -*/ - -#include -#include "FreeRTOS.h" -#include "list.h" - -/*----------------------------------------------------------- - * PUBLIC LIST API documented in list.h - *----------------------------------------------------------*/ - -void vListInitialise( xList *pxList ) -{ - /* The list structure contains a list item which is used to mark the - end of the list. To initialise the list the list end is inserted - as the only list entry. */ - pxList->pxIndex = ( xListItem * ) &( pxList->xListEnd ); - - /* The list end value is the highest possible value in the list to - ensure it remains at the end of the list. */ - pxList->xListEnd.xItemValue = portMAX_DELAY; - - /* The list end next and previous pointers point to itself so we know - when the list is empty. */ - pxList->xListEnd.pxNext = ( xListItem * ) &( pxList->xListEnd ); - pxList->xListEnd.pxPrevious = ( xListItem * ) &( pxList->xListEnd ); - - pxList->uxNumberOfItems = 0; -} -/*-----------------------------------------------------------*/ - -void vListInitialiseItem( xListItem *pxItem ) -{ - /* Make sure the list item is not recorded as being on a list. */ - pxItem->pvContainer = NULL; -} -/*-----------------------------------------------------------*/ - -void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ) -{ -volatile xListItem * pxIndex; - - /* Insert a new list item into pxList, but rather than sort the list, - makes the new list item the last item to be removed by a call to - pvListGetOwnerOfNextEntry. This means it has to be the item pointed to by - the pxIndex member. */ - pxIndex = pxList->pxIndex; - - pxNewListItem->pxNext = pxIndex->pxNext; - pxNewListItem->pxPrevious = pxList->pxIndex; - pxIndex->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; - pxIndex->pxNext = ( volatile xListItem * ) pxNewListItem; - pxList->pxIndex = ( volatile xListItem * ) pxNewListItem; - - /* Remember which list the item is in. */ - pxNewListItem->pvContainer = ( void * ) pxList; - - ( pxList->uxNumberOfItems )++; -} -/*-----------------------------------------------------------*/ - -void vListInsert( xList *pxList, xListItem *pxNewListItem ) -{ -volatile xListItem *pxIterator; -portTickType xValueOfInsertion; - - /* Insert the new list item into the list, sorted in ulListItem order. */ - xValueOfInsertion = pxNewListItem->xItemValue; - - /* If the list already contains a list item with the same item value then - the new list item should be placed after it. This ensures that TCB's which - are stored in ready lists (all of which have the same ulListItem value) - get an equal share of the CPU. However, if the xItemValue is the same as - the back marker the iteration loop below will not end. This means we need - to guard against this by checking the value first and modifying the - algorithm slightly if necessary. */ - if( xValueOfInsertion == portMAX_DELAY ) - { - pxIterator = pxList->xListEnd.pxPrevious; - } - else - { - for( pxIterator = ( xListItem * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) - { - /* There is nothing to do here, we are just iterating to the - wanted insertion position. */ - } - } - - pxNewListItem->pxNext = pxIterator->pxNext; - pxNewListItem->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; - pxNewListItem->pxPrevious = pxIterator; - pxIterator->pxNext = ( volatile xListItem * ) pxNewListItem; - - /* Remember which list the item is in. This allows fast removal of the - item later. */ - pxNewListItem->pvContainer = ( void * ) pxList; - - ( pxList->uxNumberOfItems )++; -} -/*-----------------------------------------------------------*/ - -void vListRemove( xListItem *pxItemToRemove ) -{ -xList * pxList; - - pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; - pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; - - /* The list item knows which list it is in. Obtain the list from the list - item. */ - pxList = ( xList * ) pxItemToRemove->pvContainer; - - /* Make sure the index is left pointing to a valid item. */ - if( pxList->pxIndex == pxItemToRemove ) - { - pxList->pxIndex = pxItemToRemove->pxPrevious; - } - - pxItemToRemove->pvContainer = NULL; - ( pxList->uxNumberOfItems )--; -} -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/portable/GCC/MCF5235/port.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/portable/GCC/MCF5235/port.c deleted file mode 100644 index c304b0daa..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/portable/GCC/MCF5235/port.c +++ /dev/null @@ -1,263 +0,0 @@ -/* - FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. - MCF5235 Port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include - -#include "FreeRTOS.h" -#include "FreeRTOSConfig.h" -#include "task.h" - -/* ------------------------ Types ----------------------------------------- */ -typedef volatile unsigned long vuint32; -typedef volatile unsigned short vuint16; -typedef volatile unsigned char vuint8; - -/* ------------------------ Defines --------------------------------------- */ -#define portVECTOR_TABLE __RAMVEC -#define portVECTOR_SYSCALL ( 32 + portTRAP_YIELD ) -#define portVECTOR_TIMER ( 64 + 36 ) - -#define MCF_PIT_PRESCALER 512UL -#define MCF_PIT_TIMER_TICKS ( FSYS_2 / MCF_PIT_PRESCALER ) -#define MCF_PIT_MODULUS_REGISTER(freq) ( MCF_PIT_TIMER_TICKS / ( freq ) - 1UL) - -#define MCF_PIT_PMR0 ( *( vuint16 * )( void * )( &__IPSBAR[ 0x150002 ] ) ) -#define MCF_PIT_PCSR0 ( *( vuint16 * )( void * )( &__IPSBAR[ 0x150000 ] ) ) -#define MCF_PIT_PCSR_PRE(x) ( ( ( x ) & 0x000F ) << 8 ) -#define MCF_PIT_PCSR_EN ( 0x0001 ) -#define MCF_PIT_PCSR_RLD ( 0x0002 ) -#define MCF_PIT_PCSR_PIF ( 0x0004 ) -#define MCF_PIT_PCSR_PIE ( 0x0008 ) -#define MCF_PIT_PCSR_OVW ( 0x0010 ) -#define MCF_INTC0_ICR36 ( *( vuint8 * )( void * )( &__IPSBAR[ 0x000C64 ] ) ) -#define MCF_INTC0_IMRH ( *( vuint32 * )( void * )( &__IPSBAR[ 0x000C08 ] ) ) -#define MCF_INTC0_IMRH_INT_MASK36 ( 0x00000010 ) -#define MCF_INTC0_IMRH_MASKALL ( 0x00000001 ) -#define MCF_INTC0_ICRn_IP(x) ( ( ( x ) & 0x07 ) << 0 ) -#define MCF_INTC0_ICRn_IL(x) ( ( ( x ) & 0x07 ) << 3 ) - -#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) -#define portINITIAL_CRITICAL_NESTING ( ( unsigned portLONG ) 10 ) - -/* ------------------------ Static variables ------------------------------ */ -volatile unsigned portLONG ulCriticalNesting = portINITIAL_CRITICAL_NESTING; - -/* ------------------------ Static functions ------------------------------ */ -#if configUSE_PREEMPTION == 0 -static void prvPortPreemptiveTick ( void ) __attribute__ ((interrupt_handler)); -#else -static void prvPortPreemptiveTick ( void ); -#endif - -/* ------------------------ Start implementation -------------------------- */ - -portSTACK_TYPE * -pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, - void *pvParameters ) -{ - /* Place the parameter on the stack in the expected location. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; - pxTopOfStack--; - - /* Place dummy return address on stack. Tasks should never terminate so - * we can set this to anything. */ - *pxTopOfStack = ( portSTACK_TYPE ) 0; - pxTopOfStack--; - - /* Create a Motorola Coldfire exception stack frame. First comes the return - * address. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode; - pxTopOfStack--; - - /* Format, fault-status, vector number for exception stack frame. Task - * run in supervisor mode. */ - *pxTopOfStack = 0x40002000UL | ( portVECTOR_SYSCALL + 32 ) << 18; - pxTopOfStack--; - - /* Set the initial critical section nesting counter to zero. This value - * is used to restore the value of ulCriticalNesting. */ - *pxTopOfStack = 0; - *pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xA6; /* A6 / FP */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA5; /* A5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA4; /* A4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA3; /* A3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA2; /* A2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA1; /* A1 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xA0; /* A0 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD7; /* D7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD6; /* D6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD5; /* D5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD4; /* D4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD3; /* D3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD2; /* D2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD1; /* D1 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0xD0; /* D0 */ - - return pxTopOfStack; -} - -/* - * Called by portYIELD() or taskYIELD() to manually force a context switch. - */ -static void -prvPortYield( void ) -{ - asm volatile ( "move.w #0x2700, %sr\n\t" ); -#if _GCC_USES_FP == 1 - asm volatile ( "unlk %fp\n\t" ); -#endif - /* Perform the context switch. First save the context of the current task. */ - portSAVE_CONTEXT( ); - - /* Find the highest priority task that is ready to run. */ - vTaskSwitchContext( ); - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT( ); -} - -#if configUSE_PREEMPTION == 0 -/* - * The ISR used for the scheduler tick depends on whether the cooperative or - * the preemptive scheduler is being used. - */ -static void -prvPortPreemptiveTick ( void ) -{ - /* The cooperative scheduler requires a normal IRQ service routine to - * simply increment the system tick. - */ - - vTaskIncrementTick( ); - MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF; -} - -#else - -static void -prvPortPreemptiveTick( void ) -{ - asm volatile ( "move.w #0x2700, %sr\n\t" ); -#if _GCC_USES_FP == 1 - asm volatile ( "unlk %fp\n\t" ); -#endif - portSAVE_CONTEXT( ); - MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF; - vTaskIncrementTick( ); - vTaskSwitchContext( ); - portRESTORE_CONTEXT( ); -} -#endif - -void -vPortEnterCritical() -{ - /* FIXME: We should store the old IPL here - How are we supposed to do - * this. - */ - ( void )portSET_IPL( portIPL_MAX ); - - /* Now interrupts are disabled ulCriticalNesting can be accessed - * directly. Increment ulCriticalNesting to keep a count of how many times - * portENTER_CRITICAL() has been called. */ - ulCriticalNesting++; -} - -void -vPortExitCritical() -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - ( void )portSET_IPL( 0 ); - } - } -} - -portBASE_TYPE -xPortStartScheduler( void ) -{ - extern void ( *portVECTOR_TABLE[ ] ) ( ); - - /* Add entry in vector table for yield system call. */ - portVECTOR_TABLE[ portVECTOR_SYSCALL ] = prvPortYield; - /* Add entry in vector table for periodic timer. */ - portVECTOR_TABLE[ portVECTOR_TIMER ] = prvPortPreemptiveTick; - - /* Configure the timer for the system clock. */ - if ( configTICK_RATE_HZ > 0) - { - /* Configure prescaler */ - MCF_PIT_PCSR0 = MCF_PIT_PCSR_PRE( 0x9 ) | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_OVW; - /* Initialize the periodic timer interrupt. */ - MCF_PIT_PMR0 = MCF_PIT_MODULUS_REGISTER( configTICK_RATE_HZ ); - /* Configure interrupt priority and level and unmask interrupt. */ - MCF_INTC0_ICR36 = MCF_INTC0_ICRn_IL( 0x1 ) | MCF_INTC0_ICRn_IP( 0x1 ); - MCF_INTC0_IMRH &= ~( MCF_INTC0_IMRH_INT_MASK36 | MCF_INTC0_IMRH_MASKALL ); - /* Enable interrupts */ - MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_EN | MCF_PIT_PCSR_PIF; - } - - /* Restore the context of the first task that is going to run. */ - portRESTORE_CONTEXT( ); - - /* Should not get here. */ - return pdTRUE; -} - -void -vPortEndScheduler( void ) -{ -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/portable/GCC/MCF5235/portmacro.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/portable/GCC/MCF5235/portmacro.h deleted file mode 100644 index f583c51e1..000000000 Binary files a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/portable/GCC/MCF5235/portmacro.h and /dev/null differ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/portable/MemMang/heap_1.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/portable/MemMang/heap_1.c deleted file mode 100644 index 35908c1e4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/portable/MemMang/heap_1.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - -Changes between V2.5.1 and V2.5.1 - - + The memory pool has been defined within a struct to ensure correct memory - alignment on 32bit systems. - -Changes between V2.6.1 and V3.0.0 - - + An overflow check has been added to ensure the next free byte variable - does not wrap around. -*/ - - -/* - * The simplest possible implementation of pvPortMalloc(). Note that this - * implementation does NOT allow allocated memory to be freed again. - * - * See heap_2.c and heap_3.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ -#include -#include "FreeRTOS.h" -#include "task.h" - -/* Setup the correct byte alignment mask for the defined byte alignment. */ -#if portBYTE_ALIGNMENT == 4 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) -#endif - -#if portBYTE_ALIGNMENT == 2 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) -#endif - -#if portBYTE_ALIGNMENT == 1 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) -#endif - -#ifndef heapBYTE_ALIGNMENT_MASK - #error "Invalid portBYTE_ALIGNMENT definition" -#endif - -/* Allocate the memory for the heap. The struct is used to force byte -alignment without using any non-portable code. */ -static struct xRTOS_HEAP -{ - unsigned portLONG ulDummy; - unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; -} xHeap; - -static size_t xNextFreeByte = ( size_t ) 0; -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -void *pvReturn = NULL; - - /* Ensure that blocks are always aligned to the required number of bytes. */ - #if portBYTE_ALIGNMENT != 1 - if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) - { - /* Byte alignment required. */ - xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); - } - #endif - - vTaskSuspendAll(); - { - /* Check there is enough room left for the allocation. */ - if( ( ( xNextFreeByte + xWantedSize ) < configTOTAL_HEAP_SIZE ) && - ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) )/* Check for overflow. */ - { - /* Return the next free byte then increment the index past this - block. */ - pvReturn = &( xHeap.ucHeap[ xNextFreeByte ] ); - xNextFreeByte += xWantedSize; - } - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ - /* Memory cannot be freed using this scheme. See heap_2.c and heap_3.c - for alternative implementations, and the memory management pages of - http://www.FreeRTOS.org for more information. */ - ( void ) pv; -} -/*-----------------------------------------------------------*/ - -void vPortInitialiseBlocks( void ) -{ - /* Only required when static memory is not cleared. */ - xNextFreeByte = ( size_t ) 0; -} - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/portable/MemMang/heap_2.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/portable/MemMang/heap_2.c deleted file mode 100644 index e8f0e79ca..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/portable/MemMang/heap_2.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * A sample implementation of pvPortMalloc() and vPortFree() that permits - * allocated blocks to be freed, but does not combine adjacent free blocks - * into a single larger block. - * - * See heap_1.c and heap_3.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ -#include - -#include "FreeRTOS.h" -#include "task.h" - -/* Setup the correct byte alignment mask for the defined byte alignment. */ -#if portBYTE_ALIGNMENT == 4 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) -#endif - -#if portBYTE_ALIGNMENT == 2 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) -#endif - -#if portBYTE_ALIGNMENT == 1 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) -#endif - -#ifndef heapBYTE_ALIGNMENT_MASK - #error "Invalid portBYTE_ALIGNMENT definition" -#endif - -/* Allocate the memory for the heap. The struct is used to force byte -alignment without using any non-portable code. */ -static struct xRTOS_HEAP -{ - unsigned portLONG ulDummy; - unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; -} xHeap; - -/* Define the linked list structure. This is used to link free blocks in order -of their size. */ -typedef struct A_BLOCK_LINK -{ - struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */ - size_t xBlockSize; /*<< The size of the free block. */ -} xBlockLink; - - -static const unsigned portSHORT heapSTRUCT_SIZE = ( sizeof( xBlockLink ) + ( sizeof( xBlockLink ) % portBYTE_ALIGNMENT ) ); -#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) ) - -/* Create a couple of list links to mark the start and end of the list. */ -static xBlockLink xStart, xEnd; - -/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */ - -/* - * Insert a block into the list of free blocks - which is ordered by size of - * the block. Small blocks at the start of the list and large blocks at the end - * of the list. - */ -#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \ -{ \ -xBlockLink *pxIterator; \ -size_t xBlockSize; \ - \ - xBlockSize = pxBlockToInsert->xBlockSize; \ - \ - /* Iterate through the list until a block is found that has a larger size */ \ - /* than the block we are inserting. */ \ - for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \ - { \ - /* There is nothing to do here - just iterate to the correct position. */ \ - } \ - \ - /* Update the list to include the block being inserted in the correct */ \ - /* position. */ \ - pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \ - pxIterator->pxNextFreeBlock = pxBlockToInsert; \ -} -/*-----------------------------------------------------------*/ - -#define prvHeapInit() \ -{ \ -xBlockLink *pxFirstFreeBlock; \ - \ - /* xStart is used to hold a pointer to the first item in the list of free */ \ - /* blocks. The void cast is used to prevent compiler warnings. */ \ - xStart.pxNextFreeBlock = ( void * ) xHeap.ucHeap; \ - xStart.xBlockSize = ( size_t ) 0; \ - \ - /* xEnd is used to mark the end of the list of free blocks. */ \ - xEnd.xBlockSize = configTOTAL_HEAP_SIZE; \ - xEnd.pxNextFreeBlock = NULL; \ - \ - /* To start with there is a single free block that is sized to take up the \ - entire heap space. */ \ - pxFirstFreeBlock = ( void * ) xHeap.ucHeap; \ - pxFirstFreeBlock->xBlockSize = configTOTAL_HEAP_SIZE; \ - pxFirstFreeBlock->pxNextFreeBlock = &xEnd; \ -} -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -xBlockLink *pxBlock, *pxPreviousBlock, *pxNewBlockLink; -static portBASE_TYPE xHeapHasBeenInitialised = pdFALSE; -void *pvReturn = NULL; - - vTaskSuspendAll(); - { - /* If this is the first call to malloc then the heap will require - initialisation to setup the list of free blocks. */ - if( xHeapHasBeenInitialised == pdFALSE ) - { - prvHeapInit(); - xHeapHasBeenInitialised = pdTRUE; - } - - /* The wanted size is increased so it can contain a xBlockLink - structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) - { - xWantedSize += heapSTRUCT_SIZE; - - /* Ensure that blocks are always aligned to the required number of bytes. */ - if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) - { - /* Byte alignment required. */ - xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); - } - } - - if( ( xWantedSize > 0 ) && ( xWantedSize < configTOTAL_HEAP_SIZE ) ) - { - /* Blocks are stored in byte order - traverse the list from the start - (smallest) block until one of adequate size is found. */ - pxPreviousBlock = &xStart; - pxBlock = xStart.pxNextFreeBlock; - while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock ) ) - { - pxPreviousBlock = pxBlock; - pxBlock = pxBlock->pxNextFreeBlock; - } - - /* If we found the end marker then a block of adequate size was not found. */ - if( pxBlock != &xEnd ) - { - /* Return the memory space - jumping over the xBlockLink structure - at its start. */ - pvReturn = ( void * ) ( ( ( unsigned portCHAR * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE ); - - /* This block is being returned for use so must be taken our of the - list of free blocks. */ - pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; - - /* If the block is larger than required it can be split into two. */ - if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) - { - /* This block is to be split into two. Create a new block - following the number of bytes requested. The void cast is - used to prevent byte alignment warnings from the compiler. */ - pxNewBlockLink = ( void * ) ( ( ( unsigned portCHAR * ) pxBlock ) + xWantedSize ); - - /* Calculate the sizes of two blocks split from the single - block. */ - pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; - pxBlock->xBlockSize = xWantedSize; - - /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); - } - } - } - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ -unsigned portCHAR *puc = ( unsigned portCHAR * ) pv; -xBlockLink *pxLink; - - if( pv ) - { - /* The memory being freed will have an xBlockLink structure immediately - before it. */ - puc -= heapSTRUCT_SIZE; - - /* This casting is to keep the compiler from issuing warnings. */ - pxLink = ( void * ) puc; - - vTaskSuspendAll(); - { - /* Add this block to the list of free blocks. */ - prvInsertBlockIntoFreeList( ( ( xBlockLink * ) pxLink ) ); - } - xTaskResumeAll(); - } -} -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/portable/MemMang/heap_3.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/portable/MemMang/heap_3.c deleted file mode 100644 index 9e5d362a7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/portable/MemMang/heap_3.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * Implementation of pvPortMalloc() and vPortFree() that relies on the - * compilers own malloc() and free() implementations. - * - * This file can only be used if the linker is configured to to generate - * a heap memory area. - * - * See heap_2.c and heap_1.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ - -#include - -#include "FreeRTOS.h" -#include "task.h" - -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -void *pvReturn; - - vTaskSuspendAll(); - { - pvReturn = malloc( xWantedSize ); - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ - if( pv ) - { - vTaskSuspendAll(); - { - free( pv ); - } - xTaskResumeAll(); - } -} - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/queue.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/queue.c deleted file mode 100644 index a81755e87..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/queue.c +++ /dev/null @@ -1,869 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.01 - - + More use of 8bit data types. - + Function name prefixes changed where the data type returned has changed. - -Changed from V2.0.0 - - + Added the queue locking mechanism and make more use of the scheduler - suspension feature to minimise the time interrupts have to be disabled - when accessing a queue. - -Changed from V2.2.0 - - + Explicit use of 'signed' qualifier on portCHAR types added. - -Changes from V3.0.0 - - + API changes as described on the FreeRTOS.org WEB site. - -Changes from V3.2.3 - - + Added the queue functions that can be used from co-routines. - -*/ - -#include -#include -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/*----------------------------------------------------------- - * PUBLIC LIST API documented in list.h - *----------------------------------------------------------*/ - -/* Constants used with the cRxLock and cTxLock structure members. */ -#define queueUNLOCKED ( ( signed portBASE_TYPE ) -1 ) - -/* - * Definition of the queue used by the scheduler. - * Items are queued by copy, not reference. - */ -typedef struct QueueDefinition -{ - signed portCHAR *pcHead; /*< Points to the beginning of the queue storage area. */ - signed portCHAR *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */ - - signed portCHAR *pcWriteTo; /*< Points to the free next place in the storage area. */ - signed portCHAR *pcReadFrom; /*< Points to the last place that a queued item was read from. */ - - xList xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */ - xList xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */ - - unsigned portBASE_TYPE uxMessagesWaiting;/*< The number of items currently in the queue. */ - unsigned portBASE_TYPE uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */ - unsigned portBASE_TYPE uxItemSize; /*< The size of each items that the queue will hold. */ - - signed portBASE_TYPE xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ - signed portBASE_TYPE xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ -} xQUEUE; -/*-----------------------------------------------------------*/ - -/* - * Inside this file xQueueHandle is a pointer to a xQUEUE structure. - * To keep the definition private the API header file defines it as a - * pointer to void. - */ -typedef xQUEUE * xQueueHandle; - -/* - * Prototypes for public functions are included here so we don't have to - * include the API header file (as it defines xQueueHandle differently). These - * functions are documented in the API header file. - */ -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); -signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue ); -void vQueueDelete( xQueueHandle xQueue ); -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ); -signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - -#if configUSE_CO_ROUTINES == 1 - signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ); - signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ); - signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); -#endif - -/* - * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not - * prevent an ISR from adding or removing items to the queue, but does prevent - * an ISR from removing tasks from the queue event lists. If an ISR finds a - * queue is locked it will instead increment the appropriate queue lock count - * to indicate that a task may require unblocking. When the queue in unlocked - * these lock counts are inspected, and the appropriate action taken. - */ -static signed portBASE_TYPE prvUnlockQueue( xQueueHandle pxQueue ); - -/* - * Uses a critical section to determine if there is any data in a queue. - * - * @return pdTRUE if the queue contains no items, otherwise pdFALSE. - */ -static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ); - -/* - * Uses a critical section to determine if there is any space in a queue. - * - * @return pdTRUE if there is no space, otherwise pdFALSE; - */ -static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ); - -/* - * Macro that copies an item into the queue. This is done by copying the item - * byte for byte, not by reference. Updates the queue state to ensure it's - * integrity after the copy. - */ -#define prvCopyQueueData( pxQueue, pvItemToQueue ) \ -{ \ - memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize ); \ - ++( pxQueue->uxMessagesWaiting ); \ - pxQueue->pcWriteTo += pxQueue->uxItemSize; \ - if( pxQueue->pcWriteTo >= pxQueue->pcTail ) \ - { \ - pxQueue->pcWriteTo = pxQueue->pcHead; \ - } \ -} -/*-----------------------------------------------------------*/ - -/* - * Macro to mark a queue as locked. Locking a queue prevents an ISR from - * accessing the queue event lists. - */ -#define prvLockQueue( pxQueue ) \ -{ \ - taskENTER_CRITICAL(); \ - ++( pxQueue->xRxLock ); \ - ++( pxQueue->xTxLock ); \ - taskEXIT_CRITICAL(); \ -} -/*-----------------------------------------------------------*/ - - -/*----------------------------------------------------------- - * PUBLIC QUEUE MANAGEMENT API documented in queue.h - *----------------------------------------------------------*/ - -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ) -{ -xQUEUE *pxNewQueue; -size_t xQueueSizeInBytes; - - /* Allocate the new queue structure. */ - if( uxQueueLength > ( unsigned portBASE_TYPE ) 0 ) - { - pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) ); - if( pxNewQueue != NULL ) - { - /* Create the list of pointers to queue items. The queue is one byte - longer than asked for to make wrap checking easier/faster. */ - xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1; - - pxNewQueue->pcHead = ( signed portCHAR * ) pvPortMalloc( xQueueSizeInBytes ); - if( pxNewQueue->pcHead != NULL ) - { - /* Initialise the queue members as described above where the - queue type is defined. */ - pxNewQueue->pcTail = pxNewQueue->pcHead + ( uxQueueLength * uxItemSize ); - pxNewQueue->uxMessagesWaiting = 0; - pxNewQueue->pcWriteTo = pxNewQueue->pcHead; - pxNewQueue->pcReadFrom = pxNewQueue->pcHead + ( ( uxQueueLength - 1 ) * uxItemSize ); - pxNewQueue->uxLength = uxQueueLength; - pxNewQueue->uxItemSize = uxItemSize; - pxNewQueue->xRxLock = queueUNLOCKED; - pxNewQueue->xTxLock = queueUNLOCKED; - - /* Likewise ensure the event queues start with the correct state. */ - vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) ); - vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) ); - - return pxNewQueue; - } - else - { - vPortFree( pxNewQueue ); - } - } - } - - /* Will only reach here if we could not allocate enough memory or no memory - was required. */ - return NULL; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* Make sure other tasks do not access the queue. */ - vTaskSuspendAll(); - - /* It is important that this is the only thread/ISR that modifies the - ready or delayed lists until xTaskResumeAll() is called. Places where - the ready/delayed lists are modified include: - - + vTaskDelay() - Nothing can call vTaskDelay as the scheduler is - suspended, vTaskDelay() cannot be called from an ISR. - + vTaskPrioritySet() - Has a critical section around the access. - + vTaskSwitchContext() - This will not get executed while the scheduler - is suspended. - + prvCheckDelayedTasks() - This will not get executed while the - scheduler is suspended. - + xTaskCreate() - Has a critical section around the access. - + vTaskResume() - Has a critical section around the access. - + xTaskResumeAll() - Has a critical section around the access. - + xTaskRemoveFromEventList - Checks to see if the scheduler is - suspended. If so then the TCB being removed from the event is - removed from the event and added to the xPendingReadyList. - */ - - /* Make sure interrupts do not access the queue event list. */ - prvLockQueue( pxQueue ); - - /* It is important that interrupts to not access the event list of the - queue being modified here. Places where the event list is modified - include: - - + xQueueSendFromISR(). This checks the lock on the queue to see if - it has access. If the queue is locked then the Tx lock count is - incremented to signify that a task waiting for data can be made ready - once the queue lock is removed. If the queue is not locked then - a task can be moved from the event list, but will not be removed - from the delayed list or placed in the ready list until the scheduler - is unlocked. - - + xQueueReceiveFromISR(). As per xQueueSendFromISR(). - */ - - /* If the queue is already full we may have to block. */ - if( prvIsQueueFull( pxQueue ) ) - { - /* The queue is full - do we want to block or just leave without - posting? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* We are going to place ourselves on the xTasksWaitingToSend event - list, and will get woken should the delay expire, or space become - available on the queue. - - As detailed above we do not require mutual exclusion on the event - list as nothing else can modify it or the ready lists while we - have the scheduler suspended and queue locked. - - It is possible that an ISR has removed data from the queue since we - checked if any was available. If this is the case then the data - will have been copied from the queue, and the queue variables - updated, but the event list will not yet have been checked to see if - anything is waiting as the queue is locked. */ - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); - - /* Force a context switch now as we are blocked. We can do - this from within a critical section as the task we are - switching to has its own context. When we return here (i.e. we - unblock) we will leave the critical section as normal. - - It is possible that an ISR has caused an event on an unrelated and - unlocked queue. If this was the case then the event list for that - queue will have been updated but the ready lists left unchanged - - instead the readied task will have been added to the pending ready - list. */ - taskENTER_CRITICAL(); - { - /* We can safely unlock the queue and scheduler here as - interrupts are disabled. We must not yield with anything - locked, but we can yield from within a critical section. - - Tasks that have been placed on the pending ready list cannot - be tasks that are waiting for events on this queue. See - in comment xTaskRemoveFromEventList(). */ - prvUnlockQueue( pxQueue ); - - /* Resuming the scheduler may cause a yield. If so then there - is no point yielding again here. */ - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - - /* Before leaving the critical section we have to ensure - exclusive access again. */ - vTaskSuspendAll(); - prvLockQueue( pxQueue ); - } - taskEXIT_CRITICAL(); - } - } - - /* When we are here it is possible that we unblocked as space became - available on the queue. It is also possible that an ISR posted to the - queue since we left the critical section, so it may be that again there - is no space. This would only happen if a task and ISR post onto the - same queue. */ - taskENTER_CRITICAL(); - { - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - /* There is room in the queue, copy the data into the queue. */ - prvCopyQueueData( pxQueue, pvItemToQueue ); - xReturn = pdPASS; - - /* Update the TxLock count so prvUnlockQueue knows to check for - tasks waiting for data to become available in the queue. */ - ++( pxQueue->xTxLock ); - } - else - { - xReturn = errQUEUE_FULL; - } - } - taskEXIT_CRITICAL(); - - /* We no longer require exclusive access to the queue. prvUnlockQueue - will remove any tasks suspended on a receive if either this function - or an ISR has posted onto the queue. */ - if( prvUnlockQueue( pxQueue ) ) - { - /* Resume the scheduler - making ready any tasks that were woken - by an event while the scheduler was locked. Resuming the - scheduler may cause a yield, in which case there is no point - yielding again here. */ - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - } - else - { - /* Resume the scheduler - making ready any tasks that were woken - by an event while the scheduler was locked. */ - xTaskResumeAll(); - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ) -{ - /* Similar to xQueueSend, except we don't block if there is no room in the - queue. Also we don't directly wake a task that was blocked on a queue - read, instead we return a flag to say whether a context switch is required - or not (i.e. has a task with a higher priority than us been woken by this - post). */ - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - prvCopyQueueData( pxQueue, pvItemToQueue ); - - /* If the queue is locked we do not alter the event list. This will - be done when the queue is unlocked later. */ - if( pxQueue->xTxLock == queueUNLOCKED ) - { - /* We only want to wake one task per ISR, so check that a task has - not already been woken. */ - if( !xTaskPreviouslyWoken ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority so record that a - context switch is required. */ - return pdTRUE; - } - } - } - } - else - { - /* Increment the lock count so the task that unlocks the queue - knows that data was posted while it was locked. */ - ++( pxQueue->xTxLock ); - } - } - - return xTaskPreviouslyWoken; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* This function is very similar to xQueueSend(). See comments within - xQueueSend() for a more detailed explanation. - - Make sure other tasks do not access the queue. */ - vTaskSuspendAll(); - - /* Make sure interrupts do not access the queue. */ - prvLockQueue( pxQueue ); - - /* If there are no messages in the queue we may have to block. */ - if( prvIsQueueEmpty( pxQueue ) ) - { - /* There are no messages in the queue, do we want to block or just - leave with nothing? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); - taskENTER_CRITICAL(); - { - prvUnlockQueue( pxQueue ); - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - - vTaskSuspendAll(); - prvLockQueue( pxQueue ); - } - taskEXIT_CRITICAL(); - } - } - - taskENTER_CRITICAL(); - { - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - /* Increment the lock count so prvUnlockQueue knows to check for - tasks waiting for space to become available on the queue. */ - ++( pxQueue->xRxLock ); - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - } - taskEXIT_CRITICAL(); - - /* We no longer require exclusive access to the queue. */ - if( prvUnlockQueue( pxQueue ) ) - { - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - } - else - { - xTaskResumeAll(); - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ) -{ -signed portBASE_TYPE xReturn; - - /* We cannot block from an ISR, so check there is data available. */ - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Copy the data from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - /* If the queue is locked we will not modify the event list. Instead - we update the lock count so the task that unlocks the queue will know - that an ISR has removed data while the queue was locked. */ - if( pxQueue->xRxLock == queueUNLOCKED ) - { - /* We only want to wake one task per ISR, so check that a task has - not already been woken. */ - if( !( *pxTaskWoken ) ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - /* The task waiting has a higher priority than us so - force a context switch. */ - *pxTaskWoken = pdTRUE; - } - } - } - } - else - { - /* Increment the lock count so the task that unlocks the queue - knows that data was removed while it was locked. */ - ++( pxQueue->xRxLock ); - } - - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue ) -{ -unsigned portBASE_TYPE uxReturn; - - taskENTER_CRITICAL(); - uxReturn = pxQueue->uxMessagesWaiting; - taskEXIT_CRITICAL(); - - return uxReturn; -} -/*-----------------------------------------------------------*/ - -void vQueueDelete( xQueueHandle pxQueue ) -{ - vPortFree( pxQueue->pcHead ); - vPortFree( pxQueue ); -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvUnlockQueue( xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xYieldRequired = pdFALSE; - - /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */ - - /* The lock counts contains the number of extra data items placed or - removed from the queue while the queue was locked. When a queue is - locked items can be added or removed, but the event lists cannot be - updated. */ - taskENTER_CRITICAL(); - { - --( pxQueue->xTxLock ); - - /* See if data was added to the queue while it was locked. */ - if( pxQueue->xTxLock > queueUNLOCKED ) - { - pxQueue->xTxLock = queueUNLOCKED; - - /* Data was posted while the queue was locked. Are any tasks - blocked waiting for data to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - /* Tasks that are removed from the event list will get added to - the pending ready list as the scheduler is still suspended. */ - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority so record that a - context switch is required. */ - xYieldRequired = pdTRUE; - } - } - } - } - taskEXIT_CRITICAL(); - - /* Do the same for the Rx lock. */ - taskENTER_CRITICAL(); - { - --( pxQueue->xRxLock ); - - if( pxQueue->xRxLock > queueUNLOCKED ) - { - pxQueue->xRxLock = queueUNLOCKED; - - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - xYieldRequired = pdTRUE; - } - } - } - } - taskEXIT_CRITICAL(); - - return xYieldRequired; -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - taskENTER_CRITICAL(); - xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ); - taskEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - taskENTER_CRITICAL(); - xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength ); - taskEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* If the queue is already full we may have to block. A critical section - is required to prevent an interrupt removing something from the queue - between the check to see if the queue is full and blocking on the queue. */ - portDISABLE_INTERRUPTS(); - { - if( prvIsQueueFull( pxQueue ) ) - { - /* The queue is full - do we want to block or just leave without - posting? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* As this is called from a coroutine we cannot block directly, but - return indicating that we need to block. */ - vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) ); - portENABLE_INTERRUPTS(); - return errQUEUE_BLOCKED; - } - else - { - portENABLE_INTERRUPTS(); - return errQUEUE_FULL; - } - } - } - portENABLE_INTERRUPTS(); - - portNOP(); - - portDISABLE_INTERRUPTS(); - { - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - /* There is room in the queue, copy the data into the queue. */ - prvCopyQueueData( pxQueue, pvItemToQueue ); - xReturn = pdPASS; - - /* Were any co-routines waiting for data to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - /* In this instance the co-routine could be placed directly - into the ready list as we are within a critical section. - Instead the same pending ready list mechansim is used as if - the event were caused from within an interrupt. */ - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The co-routine waiting has a higher priority so record - that a yield might be appropriate. */ - xReturn = errQUEUE_YIELD; - } - } - } - else - { - xReturn = errQUEUE_FULL; - } - } - portENABLE_INTERRUPTS(); - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* If the queue is already empty we may have to block. A critical section - is required to prevent an interrupt adding something to the queue - between the check to see if the queue is empty and blocking on the queue. */ - portDISABLE_INTERRUPTS(); - { - if( prvIsQueueEmpty( pxQueue ) ) - { - /* There are no messages in the queue, do we want to block or just - leave with nothing? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* As this is a co-routine we cannot block directly, but return - indicating that we need to block. */ - vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) ); - portENABLE_INTERRUPTS(); - return errQUEUE_BLOCKED; - } - else - { - portENABLE_INTERRUPTS(); - return errQUEUE_FULL; - } - } - } - portENABLE_INTERRUPTS(); - - portNOP(); - - portDISABLE_INTERRUPTS(); - { - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Data is available from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - xReturn = pdPASS; - - /* Were any co-routines waiting for space to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - /* In this instance the co-routine could be placed directly - into the ready list as we are within a critical section. - Instead the same pending ready list mechansim is used as if - the event were caused from within an interrupt. */ - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - xReturn = errQUEUE_YIELD; - } - } - } - else - { - xReturn = pdFAIL; - } - } - portENABLE_INTERRUPTS(); - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - - - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ) -{ - /* Cannot block within an ISR so if there is no space on the queue then - exit without doing anything. */ - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - prvCopyQueueData( pxQueue, pvItemToQueue ); - - /* We only want to wake one co-routine per ISR, so check that a - co-routine has not already been woken. */ - if( !xCoRoutinePreviouslyWoken ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - return pdTRUE; - } - } - } - } - - return xCoRoutinePreviouslyWoken; -} -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxCoRoutineWoken ) -{ -signed portBASE_TYPE xReturn; - - /* We cannot block from an ISR, so check there is data available. If - not then just leave without doing anything. */ - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Copy the data from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - if( !( *pxCoRoutineWoken ) ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - *pxCoRoutineWoken = pdTRUE; - } - } - } - - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/tasks.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/tasks.c deleted file mode 100644 index cfc8e3019..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/freertos/tasks.c +++ /dev/null @@ -1,1771 +0,0 @@ -/* - FreeRTOS.org V4.0.5 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.00: - - + Call to portRESTORE_CONTEXT has been removed. The first context - switch is now performed within sPortStartScheduler(). - -Changes from V1.01: - - + More use of 8bit data types. - + Function name prefixes changed where the data type returned has changed. - + configUSE_TRACE_FACILITY is no longer defined by default. - -Changes from V1.2.0 - - + Introduced ucTopReadyPriority. This tracks the highest priority ready - queue that contains a valid TCB and thus makes the context switch - slightly faster. - - + prvAddTaskToReadyQueue() has been made a macro. - -Changes from V1.2.6 - - + Added conditional compilation directives. - + Extended API. - + Rearranged function order. - + Creating a task now causes a context switch if the task being created - has a higher priority than the calling task - assuming the kernel is - running. - + vTaskDelete() now only causes a context switch if the calling task is - the task being deleted. - -Changes from V2.0.0 - - + Allow the type of the tick count to be 16 or 32 bits. - + Introduce xPendingReadyList feature to allow the time interrupts have to - be disabled to be minimised. - + Remove the #if( INCLUDE_vTaskSuspendAll ) statements. vTaskSuspendAll() - is now always included as it is used by the scheduler itself. - -Changes from V2.1.0 - - + Bug fix - pxCurrentTCB is now initialised before the call to - prvInitializeTaskLists(). Previously pxCurrentTCB could be accessed - while null. - -Changed from V2.1.1 - - + Change to where lStackSize is declared within sTaskCreate() to prevent - compiler warnings with 8051 port. - -Changes from V2.2.0 - - + Explicit use of 'signed' qualifier on portCHAR types added. - + Changed odd calculation of initial pxTopOfStack value when - portSTACK_GROWTH < 0. - + Removed pcVersionNumber definition. - -Changes from V2.5.3 - - + cTaskResumeAll() modified to ensure it can be called prior to the task - lists being initialised. - -Changes from V2.5.5 - - + Added API function vTaskDelayUntil(). - + Added INCLUDE_vTaskDelay conditional compilation. - -Changes from V2.6.0 - - + Updated the vWriteTraceToBuffer macro to always be 4 byte aligned so it - can be used on ARM architectures. - + tskMAX_TASK_NAME_LEN definition replaced with the port specific - configMAX_TASK_NAME_LEN definition. - + Removed the call to strcpy when copying across the task name into the - TCB. - + Added ucTasksDeleted variable to prevent vTaskSuspendAll() being called - too often in the idle task. - -Changes between V3.0.0 and V2.6.1 - - + When resuming the scheduler a yield is performed if either a tick has - been missed, or a task is moved from the pending ready list into a ready - list. Previously a yield was not performed on this second condition. - + Introduced the type portBASE_TYPE. This necessitates several API - changes. - + Removed the sUsingPreemption variable. The constant defined in - portmacro.h is now used directly. - + The idle task can now include an optional hook function - and no longer - completes its time slice if other tasks with equal priority to it are - ready to run. - + See the FreeRTOS.org documentation for more information on V2.x.x to - V3.x.x modifications. - -Changes from V3.1.1 - - + Modified vTaskPrioritySet() and vTaskResume() to allow these functions to - be called while the scheduler is suspended. - + Corrected the task ordering within event lists. - -Changes from V3.2.0 - - + Added function xTaskGetCurrentTaskHandle(). - -Changes from V3.2.4 - - + Changed the volatile declarations on some variables to reflect the - changes to the list definitions. - + Changed the order of the TCB definition so there is commonality between - the task control block and a co-routine control block. - + Allow the scheduler to be started even if no tasks other than the idle - task has been created. This allows co-routines to run even when no tasks - have been created. - + The need for a context switch is now signalled if a task woken by an - event has a priority greater or equal to the currently running task. - Previously this was only greater than. - -Changes from V4.0.0 - - + Added the xMissedYield handling. - -Changes from V4.0.1 - - + The function vTaskList() now suspends the scheduler rather than disabling - interrupts during the creation of the task list. - + Allow a task to delete itself by passing in its own handle. Previously - this could only be done by passing in NULL. - + The tick hook function is now called only within a tick isr. Previously - it was also called when the tick function was called during the scheduler - unlocking process. - -Changes from V4.0.3 - - + Extra checks have been placed in vTaskPrioritySet() to avoid unnecessary - yields. - -Changed from V4.0.4 - - + Bug fix: The 'value' of the event list item is updated when the priority - of a task is changed. Previously only the priority of the TCB itself was - changed. - + When resuming a task a check is first made to see if the task is actually - suspended. - + vTaskPrioritySet() and vTaskResume() no longer use the event list item. - This has not been necessary since V4.0.1 when the xMissedYield handling - was added. - + Implement xTaskResumeFromISR(). -*/ - -#include -#include -#include - -#include "FreeRTOS.h" -#include "task.h" - -/* - * Macro to define the amount of stack available to the idle task. - */ -#define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE - - -/* - * Default a definitions for backwards compatibility with old - * portmacro.h files. - */ -#ifndef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 16 -#endif - -#ifndef INCLUDE_xTaskGetCurrentTaskHandle - #define INCLUDE_xTaskGetCurrentTaskHandle 0 -#endif - -#ifndef configIDLE_SHOULD_YIELD - #define configIDLE_SHOULD_YIELD 1 -#endif - -#if configMAX_TASK_NAME_LEN < 1 - #undef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 1 -#endif - -#ifndef INCLUDE_xTaskResumeFromISR - #define INCLUDE_xTaskResumeFromISR 1 -#endif - -/* - * Task control block. A task control block (TCB) is allocated to each task, - * and stores the context of the task. - */ -typedef struct tskTaskControlBlock -{ - volatile portSTACK_TYPE *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE STRUCT. */ - xListItem xGenericListItem; /*< List item used to place the TCB in ready and blocked queues. */ - xListItem xEventListItem; /*< List item used to place the TCB in event lists. */ - unsigned portBASE_TYPE uxPriority; /*< The priority of the task where 0 is the lowest priority. */ - portSTACK_TYPE *pxStack; /*< Points to the start of the stack. */ - unsigned portBASE_TYPE uxTCBNumber; /*< This is used for tracing the scheduler and making debugging easier only. */ - signed portCHAR pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */ - unsigned portSHORT usStackDepth; /*< Total depth of the stack (when empty). This is defined as the number of variables the stack can hold, not the number of bytes. */ -} tskTCB; - -/*lint -e956 */ - -tskTCB * volatile pxCurrentTCB = NULL; - -/* Lists for ready and blocked tasks. --------------------*/ - -static xList pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */ -static xList xDelayedTaskList1; /*< Delayed tasks. */ -static xList xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */ -static xList * volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */ -static xList * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */ -static xList xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready queue when the scheduler is resumed. */ - -#if ( INCLUDE_vTaskDelete == 1 ) - - static volatile xList xTasksWaitingTermination; /*< Tasks that have been deleted - but the their memory not yet freed. */ - static volatile unsigned portBASE_TYPE uxTasksDeleted = ( unsigned portBASE_TYPE ) 0; - -#endif - -#if ( INCLUDE_vTaskSuspend == 1 ) - - static xList xSuspendedTaskList; /*< Tasks that are currently suspended. */ - -#endif - -/* File private variables. --------------------------------*/ -static volatile unsigned portBASE_TYPE uxCurrentNumberOfTasks = ( unsigned portBASE_TYPE ) 0; -static volatile portTickType xTickCount = ( portTickType ) 0; -static unsigned portBASE_TYPE uxTopUsedPriority = tskIDLE_PRIORITY; -static volatile unsigned portBASE_TYPE uxTopReadyPriority = tskIDLE_PRIORITY; -static volatile signed portBASE_TYPE xSchedulerRunning = pdFALSE; -static volatile unsigned portBASE_TYPE uxSchedulerSuspended = ( unsigned portBASE_TYPE ) pdFALSE; -static volatile unsigned portBASE_TYPE uxMissedTicks = ( unsigned portBASE_TYPE ) 0; -static volatile portBASE_TYPE xMissedYield = ( portBASE_TYPE ) pdFALSE; - -/* Debugging and trace facilities private variables and macros. ------------*/ - -/* - * The value used to fill the stack of a task when the task is created. This - * is used purely for checking the high water mark for tasks. - */ -#define tskSTACK_FILL_BYTE ( 0xa5 ) - -/* - * Macros used by vListTask to indicate which state a task is in. - */ -#define tskBLOCKED_CHAR ( ( signed portCHAR ) 'B' ) -#define tskREADY_CHAR ( ( signed portCHAR ) 'R' ) -#define tskDELETED_CHAR ( ( signed portCHAR ) 'D' ) -#define tskSUSPENDED_CHAR ( ( signed portCHAR ) 'S' ) - -/* - * Macros and private variables used by the trace facility. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - #define tskSIZE_OF_EACH_TRACE_LINE ( ( unsigned portLONG ) ( sizeof( unsigned portLONG ) + sizeof( unsigned portLONG ) ) ) - static volatile signed portCHAR * volatile pcTraceBuffer; - static signed portCHAR *pcTraceBufferStart; - static signed portCHAR *pcTraceBufferEnd; - static signed portBASE_TYPE xTracing = pdFALSE; - -#endif - -/* - * Macro that writes a trace of scheduler activity to a buffer. This trace - * shows which task is running when and is very useful as a debugging tool. - * As this macro is called each context switch it is a good idea to undefine - * it if not using the facility. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - #define vWriteTraceToBuffer() \ - { \ - if( xTracing ) \ - { \ - static unsigned portBASE_TYPE uxPreviousTask = 255; \ - \ - if( uxPreviousTask != pxCurrentTCB->uxTCBNumber ) \ - { \ - if( ( pcTraceBuffer + tskSIZE_OF_EACH_TRACE_LINE ) < pcTraceBufferEnd ) \ - { \ - uxPreviousTask = pxCurrentTCB->uxTCBNumber; \ - *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) xTickCount; \ - pcTraceBuffer += sizeof( unsigned portLONG ); \ - *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) uxPreviousTask; \ - pcTraceBuffer += sizeof( unsigned portLONG ); \ - } \ - else \ - { \ - xTracing = pdFALSE; \ - } \ - } \ - } \ - } - -#else - - #define vWriteTraceToBuffer() - -#endif - - -/* - * Place the task represented by pxTCB into the appropriate ready queue for - * the task. It is inserted at the end of the list. One quirk of this is - * that if the task being inserted is at the same priority as the currently - * executing task, then it will only be rescheduled after the currently - * executing task has been rescheduled. - */ -#define prvAddTaskToReadyQueue( pxTCB ) \ -{ \ - if( pxTCB->uxPriority > uxTopReadyPriority ) \ - { \ - uxTopReadyPriority = pxTCB->uxPriority; \ - } \ - vListInsertEnd( ( xList * ) &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ); \ -} - -/* - * Macro that looks at the list of tasks that are currently delayed to see if - * any require waking. - * - * Tasks are stored in the queue in the order of their wake time - meaning - * once one tasks has been found whose timer has not expired we need not look - * any further down the list. - */ -#define prvCheckDelayedTasks() \ -{ \ -register tskTCB *pxTCB; \ - \ - while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ) ) != NULL ) \ - { \ - if( xTickCount < listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) ) ) \ - { \ - break; \ - } \ - vListRemove( &( pxTCB->xGenericListItem ) ); \ - /* Is the task waiting on an event also? */ \ - if( pxTCB->xEventListItem.pvContainer ) \ - { \ - vListRemove( &( pxTCB->xEventListItem ) ); \ - } \ - prvAddTaskToReadyQueue( pxTCB ); \ - } \ -} - -/* - * Several functions take an xTaskHandle parameter that can optionally be NULL, - * where NULL is used to indicate that the handle of the currently executing - * task should be used in place of the parameter. This macro simply checks to - * see if the parameter is NULL and returns a pointer to the appropriate TCB. - */ -#define prvGetTCBFromHandle( pxHandle ) ( ( pxHandle == NULL ) ? ( tskTCB * ) pxCurrentTCB : ( tskTCB * ) pxHandle ) - - -/* File private functions. --------------------------------*/ - -/* - * Utility to ready a TCB for a given task. Mainly just copies the parameters - * into the TCB structure. - */ -static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ); - -/* - * Utility to ready all the lists used by the scheduler. This is called - * automatically upon the creation of the first task. - */ -static void prvInitialiseTaskLists( void ); - -/* - * The idle task, which as all tasks is implemented as a never ending loop. - * The idle task is automatically created and added to the ready lists upon - * creation of the first user task. - * - * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific - * language extensions. The equivalent prototype for this function is: - * - * void prvIdleTask( void *pvParameters ); - * - */ -static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ); - -/* - * Utility to free all memory allocated by the scheduler to hold a TCB, - * including the stack pointed to by the TCB. - * - * This does not free memory allocated by the task itself (i.e. memory - * allocated by calls to pvPortMalloc from within the tasks application code). - */ -#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) - static void prvDeleteTCB( tskTCB *pxTCB ); -#endif - -/* - * Used only by the idle task. This checks to see if anything has been placed - * in the list of tasks waiting to be deleted. If so the task is cleaned up - * and its TCB deleted. - */ -static void prvCheckTasksWaitingTermination( void ); - -/* - * Allocates memory from the heap for a TCB and associated stack. Checks the - * allocation was successful. - */ -static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ); - -/* - * Called from vTaskList. vListTasks details all the tasks currently under - * control of the scheduler. The tasks may be in one of a number of lists. - * prvListTaskWithinSingleList accepts a list and details the tasks from - * within just that list. - * - * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM - * NORMAL APPLICATION CODE. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ); - -#endif - -/* - * When a task is created, the stack of the task is filled with a known value. - * This function determines the 'high water mark' of the task stack by - * determining how much of the stack remains at the original preset value. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte ); - -#endif - -/*lint +e956 */ - - - - - -/*----------------------------------------------------------- - * TASK CREATION API documented in task.h - *----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask ) -{ -signed portBASE_TYPE xReturn; -tskTCB * pxNewTCB; -static unsigned portBASE_TYPE uxTaskNumber = 0; /*lint !e956 Static is deliberate - this is guarded before use. */ - - /* Allocate the memory required by the TCB and stack for the new task. - checking that the allocation was successful. */ - pxNewTCB = prvAllocateTCBAndStack( usStackDepth ); - - if( pxNewTCB != NULL ) - { - portSTACK_TYPE *pxTopOfStack; - - /* Setup the newly allocated TCB with the initial state of the task. */ - prvInitialiseTCBVariables( pxNewTCB, usStackDepth, pcName, uxPriority ); - - /* Calculate the top of stack address. This depends on whether the - stack grows from high memory to low (as per the 80x86) or visa versa. - portSTACK_GROWTH is used to make the result positive or negative as - required by the port. */ - #if portSTACK_GROWTH < 0 - { - pxTopOfStack = pxNewTCB->pxStack + ( pxNewTCB->usStackDepth - 1 ); - } - #else - { - pxTopOfStack = pxNewTCB->pxStack; - } - #endif - - /* Initialize the TCB stack to look as if the task was already running, - but had been interrupted by the scheduler. The return address is set - to the start of the task function. Once the stack has been initialised - the top of stack variable is updated. */ - pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pvTaskCode, pvParameters ); - - /* We are going to manipulate the task queues to add this task to a - ready list, so must make sure no interrupts occur. */ - portENTER_CRITICAL(); - { - uxCurrentNumberOfTasks++; - if( uxCurrentNumberOfTasks == ( unsigned portBASE_TYPE ) 1 ) - { - /* As this is the first task it must also be the current task. */ - pxCurrentTCB = pxNewTCB; - - /* This is the first task to be created so do the preliminary - initialisation required. We will not recover if this call - fails, but we will report the failure. */ - prvInitialiseTaskLists(); - } - else - { - /* If the scheduler is not already running, make this task the - current task if it is the highest priority task to be created - so far. */ - if( xSchedulerRunning == pdFALSE ) - { - if( pxCurrentTCB->uxPriority <= uxPriority ) - { - pxCurrentTCB = pxNewTCB; - } - } - } - - /* Remember the top priority to make context switching faster. Use - the priority in pxNewTCB as this has been capped to a valid value. */ - if( pxNewTCB->uxPriority > uxTopUsedPriority ) - { - uxTopUsedPriority = pxNewTCB->uxPriority; - } - - /* Add a counter into the TCB for tracing only. */ - pxNewTCB->uxTCBNumber = uxTaskNumber; - uxTaskNumber++; - - prvAddTaskToReadyQueue( pxNewTCB ); - - xReturn = pdPASS; - } - portEXIT_CRITICAL(); - } - else - { - xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - } - - if( xReturn == pdPASS ) - { - if( ( void * ) pxCreatedTask != NULL ) - { - /* Pass the TCB out - in an anonymous way. The calling function/ - task can use this as a handle to delete the task later if - required.*/ - *pxCreatedTask = ( xTaskHandle ) pxNewTCB; - } - - if( xSchedulerRunning != pdFALSE ) - { - /* If the created task is of a higher priority than the current task - then it should run now. */ - if( pxCurrentTCB->uxPriority < uxPriority ) - { - taskYIELD(); - } - } - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelete == 1 ) - - void vTaskDelete( xTaskHandle pxTaskToDelete ) - { - tskTCB *pxTCB; - - taskENTER_CRITICAL(); - { - /* Ensure a yield is performed if the current task is being - deleted. */ - if( pxTaskToDelete == pxCurrentTCB ) - { - pxTaskToDelete = NULL; - } - - /* If null is passed in here then we are deleting ourselves. */ - pxTCB = prvGetTCBFromHandle( pxTaskToDelete ); - - /* Remove task from the ready list and place in the termination list. - This will stop the task from be scheduled. The idle task will check - the termination list and free up any memory allocated by the - scheduler for the TCB and stack. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Is the task waiting on an event also? */ - if( pxTCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - } - - vListInsertEnd( ( xList * ) &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) ); - - /* Increment the ucTasksDeleted variable so the idle task knows - there is a task that has been deleted and that it should therefore - check the xTasksWaitingTermination list. */ - ++uxTasksDeleted; - } - taskEXIT_CRITICAL(); - - /* Force a reschedule if we have just deleted the current task. */ - if( xSchedulerRunning != pdFALSE ) - { - if( ( void * ) pxTaskToDelete == NULL ) - { - taskYIELD(); - } - } - } - -#endif - - - - - - -/*----------------------------------------------------------- - * TASK CONTROL API documented in task.h - *----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelayUntil == 1 ) - - void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement ) - { - portTickType xTimeToWake; - portBASE_TYPE xAlreadyYielded, xShouldDelay = pdFALSE; - - vTaskSuspendAll(); - { - /* Generate the tick time at which the task wants to wake. */ - xTimeToWake = *pxPreviousWakeTime + xTimeIncrement; - - if( xTickCount < *pxPreviousWakeTime ) - { - /* The tick count has overflowed since this function was - lasted called. In this case the only time we should ever - actually delay is if the wake time has also overflowed, - and the wake time is greater than the tick time. When this - is the case it is as if neither time had overflowed. */ - if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xTickCount ) ) - { - xShouldDelay = pdTRUE; - } - } - else - { - /* The tick time has not overflowed. In this case we will - delay if either the wake time has overflowed, and/or the - tick time is less than the wake time. */ - if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xTickCount ) ) - { - xShouldDelay = pdTRUE; - } - } - - /* Update the wake time ready for the next call. */ - *pxPreviousWakeTime = xTimeToWake; - - if( xShouldDelay ) - { - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - } - xAlreadyYielded = xTaskResumeAll(); - - /* Force a reschedule if xTaskResumeAll has not already done so, we may - have put ourselves to sleep. */ - if( !xAlreadyYielded ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelay == 1 ) - - void vTaskDelay( portTickType xTicksToDelay ) - { - portTickType xTimeToWake; - signed portBASE_TYPE xAlreadyYielded = pdFALSE; - - /* A delay time of zero just forces a reschedule. */ - if( xTicksToDelay > ( portTickType ) 0 ) - { - vTaskSuspendAll(); - { - /* A task that is removed from the event list while the - scheduler is suspended will not get placed in the ready - list or removed from the blocked list until the scheduler - is resumed. - - This task cannot be in an event list as it is the currently - executing task. */ - - /* Calculate the time to wake - this may overflow but this is - not a problem. */ - xTimeToWake = xTickCount + xTicksToDelay; - - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - xAlreadyYielded = xTaskResumeAll(); - } - - /* Force a reschedule if xTaskResumeAll has not already done so, we may - have put ourselves to sleep. */ - if( !xAlreadyYielded ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_uxTaskPriorityGet == 1 ) - - unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ) - { - tskTCB *pxTCB; - unsigned portBASE_TYPE uxReturn; - - taskENTER_CRITICAL(); - { - /* If null is passed in here then we are changing the - priority of the calling function. */ - pxTCB = prvGetTCBFromHandle( pxTask ); - uxReturn = pxTCB->uxPriority; - } - taskEXIT_CRITICAL(); - - return uxReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskPrioritySet == 1 ) - - void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ) - { - tskTCB *pxTCB; - unsigned portBASE_TYPE uxCurrentPriority, xYieldRequired = pdFALSE; - - /* Ensure the new priority is valid. */ - if( uxNewPriority >= configMAX_PRIORITIES ) - { - uxNewPriority = configMAX_PRIORITIES - 1; - } - - taskENTER_CRITICAL(); - { - /* If null is passed in here then we are changing the - priority of the calling function. */ - pxTCB = prvGetTCBFromHandle( pxTask ); - uxCurrentPriority = pxTCB->uxPriority; - - if( uxCurrentPriority != uxNewPriority ) - { - /* The priority change may have readied a task of higher - priority than the calling task. */ - if( uxNewPriority > pxCurrentTCB->uxPriority ) - { - if( pxTask != NULL ) - { - /* The priority of another task is being raised. If we - were raising the priority of the currently running task - there would be no need to switch as it must have already - been the highest priority task. */ - xYieldRequired = pdTRUE; - } - } - else if( pxTask == NULL ) - { - /* Setting our own priority down means there may now be another - task of higher priority that is ready to execute. */ - xYieldRequired = pdTRUE; - } - - pxTCB->uxPriority = uxNewPriority; - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxNewPriority ); - - /* If the task is in the blocked or suspended list we need do - nothing more than change it's priority variable. However, if - the task is in a ready list it needs to be removed and placed - in the queue appropriate to its new priority. */ - if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxCurrentPriority ] ), &( pxTCB->xGenericListItem ) ) ) - { - /* The task is currently in its ready list - remove before adding - it to it's new ready list. As we are in a critical section we - can do this even if the scheduler is suspended. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - } - - if( xYieldRequired == pdTRUE ) - { - taskYIELD(); - } - } - } - taskEXIT_CRITICAL(); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - void vTaskSuspend( xTaskHandle pxTaskToSuspend ) - { - tskTCB *pxTCB; - - taskENTER_CRITICAL(); - { - /* Ensure a yield is performed if the current task is being - suspended. */ - if( pxTaskToSuspend == pxCurrentTCB ) - { - pxTaskToSuspend = NULL; - } - - /* If null is passed in here then we are suspending ourselves. */ - pxTCB = prvGetTCBFromHandle( pxTaskToSuspend ); - - /* Remove task from the ready/delayed list and place in the suspended list. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Is the task waiting on an event also? */ - if( pxTCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - } - - vListInsertEnd( ( xList * ) &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ); - } - taskEXIT_CRITICAL(); - - /* We may have just suspended the current task. */ - if( ( void * ) pxTaskToSuspend == NULL ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - void vTaskResume( xTaskHandle pxTaskToResume ) - { - tskTCB *pxTCB; - - /* Remove the task from whichever list it is currently in, and place - it in the ready list. */ - pxTCB = ( tskTCB * ) pxTaskToResume; - - /* The parameter cannot be NULL as it is impossible to resume the - currently executing task. */ - if( pxTCB != NULL ) - { - taskENTER_CRITICAL(); - { - /* Is the task we are attempting to resume actually suspended? */ - if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE ) - { - /* Has the task already been resumed from within an ISR? */ - if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdTRUE ) - { - /* As we are in a critical section we can access the ready - lists even if the scheduler is suspended. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - - /* We may have just resumed a higher priority task. */ - if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - /* This yield may not cause the task just resumed to run, but - will leave the lists in the correct state for the next yield. */ - taskYIELD(); - } - } - } - } - taskEXIT_CRITICAL(); - } - } - -#endif - -/*-----------------------------------------------------------*/ - -#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ) - { - portBASE_TYPE xYieldRequired = pdFALSE; - tskTCB *pxTCB; - - pxTCB = ( tskTCB * ) pxTaskToResume; - - /* Is the task we are attempting to resume actually suspended? */ - if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE ) - { - /* Has the task already been resumed from within an ISR? */ - if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdTRUE ) - { - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - xYieldRequired = ( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ); - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - } - else - { - /* We cannot access the delayed or ready lists, so will hold this - task pending until the scheduler is resumed, at which point a - yield will be preformed if necessary. */ - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); - } - } - } - - return xYieldRequired; - } - -#endif - - - - -/*----------------------------------------------------------- - * PUBLIC SCHEDULER CONTROL documented in task.h - *----------------------------------------------------------*/ - - -void vTaskStartScheduler( void ) -{ -portBASE_TYPE xReturn; - - /* Add the idle task at the lowest priority. */ - xReturn = xTaskCreate( prvIdleTask, ( signed portCHAR * ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); - - if( xReturn == pdPASS ) - { - /* Interrupts are turned off here, to ensure a tick does not occur - before or during the call to xPortStartScheduler(). The stacks of - the created tasks contain a status word with interrupts switched on - so interrupts will automatically get re-enabled when the first task - starts to run. - - STEPPING THROUGH HERE USING A DEBUGGER CAN CAUSE BIG PROBLEMS IF THE - DEBUGGER ALLOWS INTERRUPTS TO BE PROCESSED. */ - portDISABLE_INTERRUPTS(); - - xSchedulerRunning = pdTRUE; - xTickCount = ( portTickType ) 0; - - /* Setting up the timer tick is hardware specific and thus in the - portable interface. */ - if( xPortStartScheduler() ) - { - /* Should not reach here as if the scheduler is running the - function will not return. */ - } - else - { - /* Should only reach here if a task calls xTaskEndScheduler(). */ - } - } -} -/*-----------------------------------------------------------*/ - -void vTaskEndScheduler( void ) -{ - /* Stop the scheduler interrupts and call the portable scheduler end - routine so the original ISRs can be restored if necessary. The port - layer must ensure interrupts enable bit is left in the correct state. */ - portDISABLE_INTERRUPTS(); - xSchedulerRunning = pdFALSE; - vPortEndScheduler(); -} -/*----------------------------------------------------------*/ - -void vTaskSuspendAll( void ) -{ - portENTER_CRITICAL(); - ++uxSchedulerSuspended; - portEXIT_CRITICAL(); -} -/*----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskResumeAll( void ) -{ -register tskTCB *pxTCB; -signed portBASE_TYPE xAlreadyYielded = pdFALSE; - - /* It is possible that an ISR caused a task to be removed from an event - list while the scheduler was suspended. If this was the case then the - removed task will have been added to the xPendingReadyList. Once the - scheduler has been resumed it is safe to move all the pending ready - tasks from this list into their appropriate ready list. */ - portENTER_CRITICAL(); - { - --uxSchedulerSuspended; - - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - if( uxCurrentNumberOfTasks > ( unsigned portBASE_TYPE ) 0 ) - { - portBASE_TYPE xYieldRequired = pdFALSE; - - /* Move any readied tasks from the pending list into the - appropriate ready list. */ - while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xPendingReadyList ) ) ) != NULL ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - - /* If we have moved a task that has a priority higher than - the current task then we should yield. */ - if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - xYieldRequired = pdTRUE; - } - } - - /* If any ticks occurred while the scheduler was suspended then - they should be processed now. This ensures the tick count does not - slip, and that any delayed tasks are resumed at the correct time. */ - if( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) - { - while( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) - { - vTaskIncrementTick(); - --uxMissedTicks; - } - - /* As we have processed some ticks it is appropriate to yield - to ensure the highest priority task that is ready to run is - the task actually running. */ - xYieldRequired = pdTRUE; - } - - if( ( xYieldRequired == pdTRUE ) || ( xMissedYield == pdTRUE ) ) - { - xAlreadyYielded = pdTRUE; - xMissedYield = pdFALSE; - taskYIELD(); - } - } - } - } - portEXIT_CRITICAL(); - - return xAlreadyYielded; -} - - - - - - -/*----------------------------------------------------------- - * PUBLIC TASK UTILITIES documented in task.h - *----------------------------------------------------------*/ - - - -portTickType xTaskGetTickCount( void ) -{ -portTickType xTicks; - - /* Critical section required if running on a 16 bit processor. */ - taskENTER_CRITICAL(); - { - xTicks = xTickCount; - } - taskEXIT_CRITICAL(); - - return xTicks; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ) -{ -unsigned portBASE_TYPE uxNumberOfTasks; - - taskENTER_CRITICAL(); - uxNumberOfTasks = uxCurrentNumberOfTasks; - taskEXIT_CRITICAL(); - - return uxNumberOfTasks; -} -/*-----------------------------------------------------------*/ - -#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_vTaskDelete == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - void vTaskList( signed portCHAR *pcWriteBuffer ) - { - unsigned portBASE_TYPE uxQueue; - - /* This is a VERY costly function that should be used for debug only. - It leaves interrupts disabled for a LONG time. */ - - vTaskSuspendAll(); - { - /* Run through all the lists that could potentially contain a TCB and - report the task name, state and stack high water mark. */ - - pcWriteBuffer[ 0 ] = ( signed portCHAR ) 0x00; - strcat( ( portCHAR * ) pcWriteBuffer, ( const portCHAR * ) "\r\n" ); - - uxQueue = uxTopUsedPriority + 1; - - do - { - uxQueue--; - - if( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), tskREADY_CHAR ); - } - }while( uxQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); - - if( !listLIST_IS_EMPTY( pxDelayedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, tskBLOCKED_CHAR ); - } - - if( !listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, tskBLOCKED_CHAR ); - } - - if( !listLIST_IS_EMPTY( &xTasksWaitingTermination ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xTasksWaitingTermination, tskDELETED_CHAR ); - } - - if( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xSuspendedTaskList, tskSUSPENDED_CHAR ); - } - } - xTaskResumeAll(); - } - -#endif -/*----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ) - { - portENTER_CRITICAL(); - { - pcTraceBuffer = ( volatile signed portCHAR * volatile )pcBuffer; - pcTraceBufferStart = pcBuffer; - pcTraceBufferEnd = pcBuffer + ( ulBufferSize - tskSIZE_OF_EACH_TRACE_LINE ); - xTracing = pdTRUE; - } - portEXIT_CRITICAL(); - } - -#endif -/*----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - unsigned portLONG ulTaskEndTrace( void ) - { - unsigned portLONG ulBufferLength; - - portENTER_CRITICAL(); - xTracing = pdFALSE; - portEXIT_CRITICAL(); - - ulBufferLength = ( unsigned portLONG ) ( pcTraceBuffer - pcTraceBufferStart ); - - return ulBufferLength; - } - -#endif - - - -/*----------------------------------------------------------- - * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES - * documented in task.h - *----------------------------------------------------------*/ - - -inline void vTaskIncrementTick( void ) -{ - /* Called by the portable layer each time a tick interrupt occurs. - Increments the tick then checks to see if the new tick value will cause any - tasks to be unblocked. */ - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - ++xTickCount; - if( xTickCount == ( portTickType ) 0 ) - { - xList *pxTemp; - - /* Tick count has overflowed so we need to swap the delay lists. - If there are any items in pxDelayedTaskList here then there is - an error! */ - pxTemp = pxDelayedTaskList; - pxDelayedTaskList = pxOverflowDelayedTaskList; - pxOverflowDelayedTaskList = pxTemp; - } - - /* See if this tick has made a timeout expire. */ - prvCheckDelayedTasks(); - } - else - { - ++uxMissedTicks; - - /* The tick hook gets called at regular intervals, even if the - scheduler is locked. */ - #if ( configUSE_TICK_HOOK == 1 ) - { - extern void vApplicationTickHook( void ); - - vApplicationTickHook(); - } - #endif - } - - #if ( configUSE_TICK_HOOK == 1 ) - { - extern void vApplicationTickHook( void ); - - /* Guard against the tick hook being called when the missed tick - count is being unwound (when the scheduler is being unlocked. */ - if( uxMissedTicks == 0 ) - { - vApplicationTickHook(); - } - } - #endif -} -/*-----------------------------------------------------------*/ - -#if ( ( INCLUDE_vTaskCleanUpResources == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - void vTaskCleanUpResources( void ) - { - unsigned portSHORT usQueue; - volatile tskTCB *pxTCB; - - usQueue = ( unsigned portSHORT ) uxTopUsedPriority + ( unsigned portSHORT ) 1; - - /* Remove any TCB's from the ready queues. */ - do - { - usQueue--; - - while( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ usQueue ] ) ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &( pxReadyTasksLists[ usQueue ] ) ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - }while( usQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); - - /* Remove any TCB's from the delayed queue. */ - while( !listLIST_IS_EMPTY( &xDelayedTaskList1 ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList1 ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - /* Remove any TCB's from the overflow delayed queue. */ - while( !listLIST_IS_EMPTY( &xDelayedTaskList2 ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList2 ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - while( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xSuspendedTaskList ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - while( !listLIST_IS_EMPTY( &xPendingReadyList ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xPendingReadyList ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - } - -#endif -/*-----------------------------------------------------------*/ - -void vTaskSwitchContext( void ) -{ - if( uxSchedulerSuspended != ( unsigned portBASE_TYPE ) pdFALSE ) - { - /* The scheduler is currently suspended - do not allow a context - switch. */ - xMissedYield = pdTRUE; - return; - } - - /* Find the highest priority queue that contains ready tasks. */ - while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) ) - { - --uxTopReadyPriority; - } - - /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the tasks of the - same priority get an equal share of the processor time. */ - listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) ); - vWriteTraceToBuffer(); -} -/*-----------------------------------------------------------*/ - -void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait ) -{ -portTickType xTimeToWake; - - /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE - SCHEDULER SUSPENDED. */ - - /* Place the event list item of the TCB in the appropriate event list. - This is placed in the list in priority order so the highest priority task - is the first to be woken by the event. */ - vListInsert( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) ); - - /* Calculate the time at which the task should be woken if the event does - not occur. This may overflow but this doesn't matter. */ - xTimeToWake = xTickCount + xTicksToWait; - - /* We must remove ourselves from the ready list before adding ourselves - to the blocked list as the same list item is used for both lists. We have - exclusive access to the ready lists as the scheduler is locked. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList ) -{ -tskTCB *pxUnblockedTCB; -portBASE_TYPE xReturn; - - /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE - SCHEDULER SUSPENDED. It can also be called from within an ISR. */ - - /* The event list is sorted in priority order, so we can remove the - first in the list, remove the TCB from the delayed list, and add - it to the ready list. - - If an event is for a queue that is locked then this function will never - get called - the lock count on the queue will get modified instead. This - means we can always expect exclusive access to the event list here. */ - pxUnblockedTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); - vListRemove( &( pxUnblockedTCB->xEventListItem ) ); - - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - vListRemove( &( pxUnblockedTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxUnblockedTCB ); - } - else - { - /* We cannot access the delayed or ready lists, so will hold this - task pending until the scheduler is resumed. */ - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); - } - - if( pxUnblockedTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - /* Return true if the task removed from the event list has - a higher priority than the calling task. This allows - the calling task to know if it should force a context - switch now. */ - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} - - - - - -/* - * ----------------------------------------------------------- - * The Idle task. - * ---------------------------------------------------------- - * - * The portTASK_FUNCTION() macro is used to allow port/compiler specific - * language extensions. The equivalent prototype for this function is: - * - * void prvIdleTask( void *pvParameters ); - * - */ -static portTASK_FUNCTION( prvIdleTask, pvParameters ) -{ - /* Stop warnings. */ - ( void ) pvParameters; - - for( ;; ) - { - /* See if any tasks have been deleted. */ - prvCheckTasksWaitingTermination(); - - #if ( configUSE_PREEMPTION == 0 ) - { - /* If we are not using preemption we keep forcing a task switch to - see if any other task has become available. If we are using - preemption we don't need to do this as any task becoming available - will automatically get the processor anyway. */ - taskYIELD(); - } - #endif - - #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) - { - /* When using preemption tasks of equal priority will be - timesliced. If a task that is sharing the idle priority is ready - to run then the idle task should yield before the end of the - timeslice. - - A critical region is not required here as we are just reading from - the list, and an occasional incorrect value will not matter. If - the ready list at the idle priority contains more than one task - then a task other than the idle task is ready to execute. */ - if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( unsigned portBASE_TYPE ) 1 ) - { - taskYIELD(); - } - } - #endif - - #if ( configUSE_IDLE_HOOK == 1 ) - { - extern void vApplicationIdleHook( void ); - - /* Call the user defined function from within the idle task. This - allows the application designer to add background functionality - without the overhead of a separate task. - NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, - CALL A FUNCTION THAT MIGHT BLOCK. */ - vApplicationIdleHook(); - } - #endif - } -} /*lint !e715 pvParameters is not accessed but all task functions require the same prototype. */ - - - - - - - -/*----------------------------------------------------------- - * File private functions documented at the top of the file. - *----------------------------------------------------------*/ - - - -static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ) -{ - pxTCB->usStackDepth = usStackDepth; - - /* Store the function name in the TCB. */ - strncpy( ( char * ) pxTCB->pcTaskName, ( const char * ) pcName, ( unsigned portSHORT ) configMAX_TASK_NAME_LEN ); - pxTCB->pcTaskName[ ( unsigned portSHORT ) configMAX_TASK_NAME_LEN - ( unsigned portSHORT ) 1 ] = '\0'; - - /* This is used as an array index so must ensure it's not too large. */ - if( uxPriority >= configMAX_PRIORITIES ) - { - uxPriority = configMAX_PRIORITIES - 1; - } - - pxTCB->uxPriority = uxPriority; - - vListInitialiseItem( &( pxTCB->xGenericListItem ) ); - vListInitialiseItem( &( pxTCB->xEventListItem ) ); - - /* Set the pxTCB as a link back from the xListItem. This is so we can get - back to the containing TCB from a generic item in a list. */ - listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB ); - - /* Event lists are always in priority order. */ - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); - listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB ); -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseTaskLists( void ) -{ -unsigned portBASE_TYPE uxPriority; - - for( uxPriority = 0; uxPriority < configMAX_PRIORITIES; uxPriority++ ) - { - vListInitialise( ( xList * ) &( pxReadyTasksLists[ uxPriority ] ) ); - } - - vListInitialise( ( xList * ) &xDelayedTaskList1 ); - vListInitialise( ( xList * ) &xDelayedTaskList2 ); - vListInitialise( ( xList * ) &xPendingReadyList ); - - #if ( INCLUDE_vTaskDelete == 1 ) - { - vListInitialise( ( xList * ) &xTasksWaitingTermination ); - } - #endif - - #if ( INCLUDE_vTaskSuspend == 1 ) - { - vListInitialise( ( xList * ) &xSuspendedTaskList ); - } - #endif - - /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList - using list2. */ - pxDelayedTaskList = &xDelayedTaskList1; - pxOverflowDelayedTaskList = &xDelayedTaskList2; -} -/*-----------------------------------------------------------*/ - -static void prvCheckTasksWaitingTermination( void ) -{ - #if ( INCLUDE_vTaskDelete == 1 ) - { - portBASE_TYPE xListIsEmpty; - - /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called - too often in the idle task. */ - if( uxTasksDeleted > ( unsigned portBASE_TYPE ) 0 ) - { - vTaskSuspendAll(); - xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination ); - xTaskResumeAll(); - - if( !xListIsEmpty ) - { - tskTCB *pxTCB; - - portENTER_CRITICAL(); - { - pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xTasksWaitingTermination ) ); - vListRemove( &( pxTCB->xGenericListItem ) ); - --uxCurrentNumberOfTasks; - --uxTasksDeleted; - } - portEXIT_CRITICAL(); - - prvDeleteTCB( pxTCB ); - } - } - } - #endif -} -/*-----------------------------------------------------------*/ - -static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ) -{ -tskTCB *pxNewTCB; - - /* Allocate space for the TCB. Where the memory comes from depends on - the implementation of the port malloc function. */ - pxNewTCB = ( tskTCB * ) pvPortMalloc( sizeof( tskTCB ) ); - - if( pxNewTCB != NULL ) - { - /* Allocate space for the stack used by the task being created. - The base of the stack memory stored in the TCB so the task can - be deleted later if required. */ - pxNewTCB->pxStack = ( portSTACK_TYPE * ) pvPortMalloc( ( ( size_t )usStackDepth ) * sizeof( portSTACK_TYPE ) ); - - if( pxNewTCB->pxStack == NULL ) - { - /* Could not allocate the stack. Delete the allocated TCB. */ - vPortFree( pxNewTCB ); - pxNewTCB = NULL; - } - else - { - /* Just to help debugging. */ - memset( pxNewTCB->pxStack, tskSTACK_FILL_BYTE, usStackDepth * sizeof( portSTACK_TYPE ) ); - } - } - - return pxNewTCB; -} -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ) - { - volatile tskTCB *pxNextTCB, *pxFirstTCB; - static portCHAR pcStatusString[ 50 ]; - unsigned portSHORT usStackRemaining; - - /* Write the details of all the TCB's in pxList into the buffer. */ - listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); - do - { - listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); - usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned portCHAR * ) pxNextTCB->pxStack ); - sprintf( pcStatusString, ( portCHAR * ) "%s\t\t%c\t%u\t%u\t%u\r\n", pxNextTCB->pcTaskName, cStatus, ( unsigned int ) pxNextTCB->uxPriority, usStackRemaining, ( unsigned int ) pxNextTCB->uxTCBNumber ); - strcat( ( portCHAR * ) pcWriteBuffer, ( portCHAR * ) pcStatusString ); - - } while( pxNextTCB != pxFirstTCB ); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte ) - { - register unsigned portSHORT usCount = 0; - - while( *pucStackByte == tskSTACK_FILL_BYTE ) - { - pucStackByte -= portSTACK_GROWTH; - usCount++; - } - - usCount /= sizeof( portSTACK_TYPE ); - - return usCount; - } -#endif -/*-----------------------------------------------------------*/ - - - -#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) - - static void prvDeleteTCB( tskTCB *pxTCB ) - { - /* Free up the memory allocated by the scheduler for the task. It is up to - the task to free any memory allocated at the application level. */ - vPortFree( pxTCB->pxStack ); - vPortFree( pxTCB ); - } - -#endif - - -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) - - xTaskHandle xTaskGetCurrentTaskHandle( void ) - { - xTaskHandle xReturn; - - portENTER_CRITICAL(); - { - xReturn = ( xTaskHandle ) pxCurrentTCB; - } - portEXIT_CRITICAL(); - - return xReturn; - } - -#endif - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x.h deleted file mode 100644 index 10e1cbc4f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * File: mcf523x.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_H__ -#define __MCF523X_H__ - -/*********************************************************************/ - -#include "mcf523x/mcf523x_fec.h" -#include "mcf523x/mcf523x_rng.h" -#include "mcf523x/mcf523x_fmpll.h" -#include "mcf523x/mcf523x_cs.h" -#include "mcf523x/mcf523x_intc0.h" -#include "mcf523x/mcf523x_intc1.h" -#include "mcf523x/mcf523x_sdramc.h" -#include "mcf523x/mcf523x_sram.h" -#include "mcf523x/mcf523x_uart.h" -#include "mcf523x/mcf523x_timer.h" -#include "mcf523x/mcf523x_qspi.h" -#include "mcf523x/mcf523x_eport.h" -#include "mcf523x/mcf523x_i2c.h" -#include "mcf523x/mcf523x_scm.h" -#include "mcf523x/mcf523x_pit.h" -#include "mcf523x/mcf523x_can.h" -#include "mcf523x/mcf523x_wtm.h" -#include "mcf523x/mcf523x_gpio.h" -#include "mcf523x/mcf523x_mdha.h" -#include "mcf523x/mcf523x_ccm.h" -#include "mcf523x/mcf523x_rcm.h" -#include "mcf523x/mcf523x_etpu.h" - - -/********************************************************************/ - -#endif /* __MCF523X_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_can.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_can.h deleted file mode 100644 index 49862d577..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_can.h +++ /dev/null @@ -1,319 +0,0 @@ -/* - * File: mcf523x_can.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_CAN_H__ -#define __MCF523X_CAN_H__ - -/********************************************************************* -* -* FlexCAN Module (CAN) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CAN_CANMCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0000])) -#define MCF_CAN_CANCTRL0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0004])) -#define MCF_CAN_TIMER0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0008])) -#define MCF_CAN_RXGMASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0010])) -#define MCF_CAN_RX14MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0014])) -#define MCF_CAN_RX15MASK0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0018])) -#define MCF_CAN_ERRCNT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C001C])) -#define MCF_CAN_ERRSTAT0 (*(vuint32*)(void*)(&__IPSBAR[0x1C0020])) -#define MCF_CAN_IMASK0 (*(vuint16*)(void*)(&__IPSBAR[0x1C002A])) -#define MCF_CAN_IFLAG0 (*(vuint16*)(void*)(&__IPSBAR[0x1C0032])) -#define MCF_CAN_CANMCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0000])) -#define MCF_CAN_CANCTRL1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0004])) -#define MCF_CAN_TIMER1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0008])) -#define MCF_CAN_RXGMASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0010])) -#define MCF_CAN_RX14MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0014])) -#define MCF_CAN_RX15MASK1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0018])) -#define MCF_CAN_ERRCNT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F001C])) -#define MCF_CAN_ERRSTAT1 (*(vuint32*)(void*)(&__IPSBAR[0x1F0020])) -#define MCF_CAN_IMASK1 (*(vuint16*)(void*)(&__IPSBAR[0x1F002A])) -#define MCF_CAN_IFLAG1 (*(vuint16*)(void*)(&__IPSBAR[0x1F0032])) -#define MCF_CAN_CANMCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0000+((x)*0x30000)])) -#define MCF_CAN_CANCTRL(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0004+((x)*0x30000)])) -#define MCF_CAN_TIMER(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0008+((x)*0x30000)])) -#define MCF_CAN_RXGMASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0010+((x)*0x30000)])) -#define MCF_CAN_RX14MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0014+((x)*0x30000)])) -#define MCF_CAN_RX15MASK(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0018+((x)*0x30000)])) -#define MCF_CAN_ERRCNT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C001C+((x)*0x30000)])) -#define MCF_CAN_ERRSTAT(x) (*(vuint32*)(void*)(&__IPSBAR[0x1C0020+((x)*0x30000)])) -#define MCF_CAN_IMASK(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C002A+((x)*0x30000)])) -#define MCF_CAN_IFLAG(x) (*(vuint16*)(void*)(&__IPSBAR[0x1C0032+((x)*0x30000)])) - -#define MCF_CAN_MBUF0_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0080+((x)*0x30000)])) -#define MCF_CAN_MBUF0_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0082+((x)*0x30000)])) -#define MCF_CAN_MBUF0_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0084+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0089+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008A+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008B+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008D+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008E+((x)*0x30000)])) -#define MCF_CAN_MBUF0_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C008F+((x)*0x30000)])) -#define MCF_CAN_MBUF1_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0090+((x)*0x30000)])) -#define MCF_CAN_MBUF1_TMSTP(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0092+((x)*0x30000)])) -#define MCF_CAN_MBUF1_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0094+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0099+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009A+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009B+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009D+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009E+((x)*0x30000)])) -#define MCF_CAN_MBUF1_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C009F+((x)*0x30000)])) -#define MCF_CAN_MBUF2_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00A0+((x)*0x30000)])) -#define MCF_CAN_MBUF2_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A4+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00A9+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AA+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AB+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AD+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AE+((x)*0x30000)])) -#define MCF_CAN_MBUF2_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00AF+((x)*0x30000)])) -#define MCF_CAN_MBUF3_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00B0+((x)*0x30000)])) -#define MCF_CAN_MBUF3_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00B4+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B8+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00B9+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BA+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BB+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BC+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BD+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BE+((x)*0x30000)])) -#define MCF_CAN_MBUF3_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00BF+((x)*0x30000)])) -#define MCF_CAN_MBUF4_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00C0+((x)*0x30000)])) -#define MCF_CAN_MBUF4_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00C4+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C8+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00C9+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CA+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CB+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CC+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CD+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CE+((x)*0x30000)])) -#define MCF_CAN_MBUF4_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00CF+((x)*0x30000)])) -#define MCF_CAN_MBUF5_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00D0+((x)*0x30000)])) -#define MCF_CAN_MBUF5_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00D4+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D8+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00D9+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DA+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DB+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DC+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DD+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DE+((x)*0x30000)])) -#define MCF_CAN_MBUF5_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00DF+((x)*0x30000)])) -#define MCF_CAN_MBUF6_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00E0+((x)*0x30000)])) -#define MCF_CAN_MBUF6_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00E4+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E8+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00E9+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EA+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EB+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EC+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00ED+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EE+((x)*0x30000)])) -#define MCF_CAN_MBUF6_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00EF+((x)*0x30000)])) -#define MCF_CAN_MBUF7_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C00F0+((x)*0x30000)])) -#define MCF_CAN_MBUF7_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00F4+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F8+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00F9+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FA+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FB+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FC+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FD+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FE+((x)*0x30000)])) -#define MCF_CAN_MBUF7_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C00FF+((x)*0x30000)])) -#define MCF_CAN_MBUF8_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)])) -#define MCF_CAN_MBUF8_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0104+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0108+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0109+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010A+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010B+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010C+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010D+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010E+((x)*0x30000)])) -#define MCF_CAN_MBUF8_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C010F+((x)*0x30000)])) -#define MCF_CAN_MBUF9_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0100+((x)*0x30000)])) -#define MCF_CAN_MBUF9_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0114+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0118+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0119+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011A+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011B+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011C+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011D+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011E+((x)*0x30000)])) -#define MCF_CAN_MBUF9_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C011F+((x)*0x30000)])) -#define MCF_CAN_MBUF10_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0120+((x)*0x30000)])) -#define MCF_CAN_MBUF10_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0124+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0128+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0129+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012A+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012B+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012C+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012D+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012E+((x)*0x30000)])) -#define MCF_CAN_MBUF10_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C012F+((x)*0x30000)])) -#define MCF_CAN_MBUF11_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0130+((x)*0x30000)])) -#define MCF_CAN_MBUF11_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0134+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0138+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0139+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013A+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013B+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013C+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013D+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013E+((x)*0x30000)])) -#define MCF_CAN_MBUF11_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C013F+((x)*0x30000)])) -#define MCF_CAN_MBUF12_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0140+((x)*0x30000)])) -#define MCF_CAN_MBUF12_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0144+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0148+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0149+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014A+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014B+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014C+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014D+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014E+((x)*0x30000)])) -#define MCF_CAN_MBUF12_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C014F+((x)*0x30000)])) -#define MCF_CAN_MBUF13_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0150+((x)*0x30000)])) -#define MCF_CAN_MBUF13_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0154+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0158+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0159+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015A+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015B+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015C+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015D+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015E+((x)*0x30000)])) -#define MCF_CAN_MBUF13_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C015F+((x)*0x30000)])) -#define MCF_CAN_MBUF14_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0160+((x)*0x30000)])) -#define MCF_CAN_MBUF14_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0164+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0168+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0169+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016A+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016B+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016C+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016D+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016E+((x)*0x30000)])) -#define MCF_CAN_MBUF14_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C016F+((x)*0x30000)])) -#define MCF_CAN_MBUF15_CTRL(x) (*(vuint16 *)(void *)(&__IPSBAR[0x1C0170+((x)*0x30000)])) -#define MCF_CAN_MBUF15_ID(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0174+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE0(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0178+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE1(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C0179+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE2(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017A+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE3(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017B+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE4(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017C+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE5(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017D+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE6(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017E+((x)*0x30000)])) -#define MCF_CAN_MBUF15_BYTE7(x) (*(vuint8 *)(void *)(&__IPSBAR[0x1C017F+((x)*0x30000)])) - - -#define MCF_CAN_MBUF0_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0088+((x)*0x30000)])) -#define MCF_CAN_MBUF0_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C008C+((x)*0x30000)])) -#define MCF_CAN_MBUF1_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C0098+((x)*0x30000)])) -#define MCF_CAN_MBUF1_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C009C+((x)*0x30000)])) -#define MCF_CAN_MBUF2_DATAL(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00A8+((x)*0x30000)])) -#define MCF_CAN_MBUF2_DATAH(x) (*(vuint32 *)(void *)(&__IPSBAR[0x1C00AC+((x)*0x30000)])) - - -/* Bit definitions and macros for MCF_CAN_CANMCR */ -#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) -#define MCF_CAN_CANMCR_SUPV (0x00800000) -#define MCF_CAN_CANMCR_FRZACK (0x01000000) -#define MCF_CAN_CANMCR_SOFTRST (0x02000000) -#define MCF_CAN_CANMCR_HALT (0x10000000) -#define MCF_CAN_CANMCR_FRZ (0x40000000) -#define MCF_CAN_CANMCR_MDIS (0x80000000) - -/* Bit definitions and macros for MCF_CAN_CANCTRL */ -#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) -#define MCF_CAN_CANCTRL_LOM (0x00000008) -#define MCF_CAN_CANCTRL_LBUF (0x00000010) -#define MCF_CAN_CANCTRL_TSYNC (0x00000020) -#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) -#define MCF_CAN_CANCTRL_SAMP (0x00000080) -#define MCF_CAN_CANCTRL_LPB (0x00001000) -#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) -#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) -#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) -#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) -#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) -#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) -#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_CAN_TIMER */ -#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RXGMASK */ -#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX14MASK */ -#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX15MASK */ -#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_ERRCNT */ -#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) -#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) - -/* Bit definitions and macros for MCF_CAN_ERRSTAT */ -#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) -#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) -#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) -#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) -#define MCF_CAN_ERRSTAT_TXRX (0x00000040) -#define MCF_CAN_ERRSTAT_IDLE (0x00000080) -#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) -#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) -#define MCF_CAN_ERRSTAT_STFERR (0x00000400) -#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) -#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) -#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) -#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) -#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) -#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) -#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) - -/* Bit definitions and macros for MCF_CAN_IMASK */ -#define MCF_CAN_IMASK_BUF0M (0x0001) -#define MCF_CAN_IMASK_BUF1M (0x0002) -#define MCF_CAN_IMASK_BUF2M (0x0004) -#define MCF_CAN_IMASK_BUF3M (0x0008) -#define MCF_CAN_IMASK_BUF4M (0x0010) -#define MCF_CAN_IMASK_BUF5M (0x0020) -#define MCF_CAN_IMASK_BUF6M (0x0040) -#define MCF_CAN_IMASK_BUF7M (0x0080) -#define MCF_CAN_IMASK_BUF8M (0x0100) -#define MCF_CAN_IMASK_BUF9M (0x0200) -#define MCF_CAN_IMASK_BUF10M (0x0400) -#define MCF_CAN_IMASK_BUF11M (0x0800) -#define MCF_CAN_IMASK_BUF12M (0x1000) -#define MCF_CAN_IMASK_BUF13M (0x2000) -#define MCF_CAN_IMASK_BUF14M (0x4000) -#define MCF_CAN_IMASK_BUF15M (0x8000) - -/* Bit definitions and macros for MCF_CAN_IFLAG */ -#define MCF_CAN_IFLAG_BUF0I (0x0001) -#define MCF_CAN_IFLAG_BUF1I (0x0002) -#define MCF_CAN_IFLAG_BUF2I (0x0004) -#define MCF_CAN_IFLAG_BUF3I (0x0008) -#define MCF_CAN_IFLAG_BUF4I (0x0010) -#define MCF_CAN_IFLAG_BUF5I (0x0020) -#define MCF_CAN_IFLAG_BUF6I (0x0040) -#define MCF_CAN_IFLAG_BUF7I (0x0080) -#define MCF_CAN_IFLAG_BUF8I (0x0100) -#define MCF_CAN_IFLAG_BUF9I (0x0200) -#define MCF_CAN_IFLAG_BUF10I (0x0400) -#define MCF_CAN_IFLAG_BUF11I (0x0800) -#define MCF_CAN_IFLAG_BUF12I (0x1000) -#define MCF_CAN_IFLAG_BUF13I (0x2000) -#define MCF_CAN_IFLAG_BUF14I (0x4000) -#define MCF_CAN_IFLAG_BUF15I (0x8000) - -/********************************************************************/ - -#endif /* __MCF523X_CAN_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_ccm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_ccm.h deleted file mode 100644 index d9806ae95..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_ccm.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * File: mcf523x_ccm.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_CCM_H__ -#define __MCF523X_CCM_H__ - -/********************************************************************* -* -* Chip Configuration Module (CCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CCM_CCR (*(vuint16*)(void*)(&__IPSBAR[0x110004])) -#define MCF_CCM_LPCR (*(vuint8 *)(void*)(&__IPSBAR[0x110007])) -#define MCF_CCM_CIR (*(vuint16*)(void*)(&__IPSBAR[0x11000A])) -#define MCF_CCM_RCON (*(vuint16*)(void*)(&__IPSBAR[0x110008])) - -/* Bit definitions and macros for MCF_CCM_CCR */ -#define MCF_CCM_CCR_BMT(x) (((x)&0x0007)<<0) -#define MCF_CCM_CCR_BME (0x0008) -#define MCF_CCM_CCR_SZEN (0x0040) -#define MCF_CCM_CCR_MODE(x) (((x)&0x0007)<<8) - -/* Bit definitions and macros for MCF_CCM_LPCR */ -#define MCF_CCM_LPCR_STPMD(x) (((x)&0x03)<<3) -#define MCF_CCM_LPCR_LPMD(x) (((x)&0x03)<<6) -#define MCF_CCM_LPCR_LPMD_STOP (0xC0) -#define MCF_CCM_LPCR_LPMD_WAIT (0x80) -#define MCF_CCM_LPCR_LPMD_DOZE (0x40) -#define MCF_CCM_LPCR_LPMD_RUN (0x00) - -/* Bit definitions and macros for MCF_CCM_CIR */ -#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0) -#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6) - -/* Bit definitions and macros for MCF_CCM_RCON */ -#define MCF_CCM_RCON_MODE (0x0001) -#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3) -#define MCF_CCM_RCON_RLOAD (0x0020) -#define MCF_CCM_RCON_RCSC(x) (((x)&0x0003)<<8) - -/********************************************************************/ - -#endif /* __MCF523X_CCM_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_cs.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_cs.h deleted file mode 100644 index 5761f5f39..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_cs.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * File: mcf523x_cs.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_CS_H__ -#define __MCF523X_CS_H__ - -/********************************************************************* -* -* Chip Selects (CS) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CS_CSAR0 (*(vuint16*)(void*)(&__IPSBAR[0x000080])) -#define MCF_CS_CSMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000084])) -#define MCF_CS_CSCR0 (*(vuint16*)(void*)(&__IPSBAR[0x00008A])) -#define MCF_CS_CSAR1 (*(vuint16*)(void*)(&__IPSBAR[0x00008C])) -#define MCF_CS_CSMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000090])) -#define MCF_CS_CSCR1 (*(vuint16*)(void*)(&__IPSBAR[0x000096])) -#define MCF_CS_CSAR2 (*(vuint16*)(void*)(&__IPSBAR[0x000098])) -#define MCF_CS_CSMR2 (*(vuint32*)(void*)(&__IPSBAR[0x00009C])) -#define MCF_CS_CSCR2 (*(vuint16*)(void*)(&__IPSBAR[0x0000A2])) -#define MCF_CS_CSAR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000A4])) -#define MCF_CS_CSMR3 (*(vuint32*)(void*)(&__IPSBAR[0x0000A8])) -#define MCF_CS_CSCR3 (*(vuint16*)(void*)(&__IPSBAR[0x0000AE])) -#define MCF_CS_CSAR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000B0])) -#define MCF_CS_CSMR4 (*(vuint32*)(void*)(&__IPSBAR[0x0000B4])) -#define MCF_CS_CSCR4 (*(vuint16*)(void*)(&__IPSBAR[0x0000BA])) -#define MCF_CS_CSAR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000BC])) -#define MCF_CS_CSMR5 (*(vuint32*)(void*)(&__IPSBAR[0x0000C0])) -#define MCF_CS_CSCR5 (*(vuint16*)(void*)(&__IPSBAR[0x0000C6])) -#define MCF_CS_CSAR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000C8])) -#define MCF_CS_CSMR6 (*(vuint32*)(void*)(&__IPSBAR[0x0000CC])) -#define MCF_CS_CSCR6 (*(vuint16*)(void*)(&__IPSBAR[0x0000D2])) -#define MCF_CS_CSAR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000D4])) -#define MCF_CS_CSMR7 (*(vuint32*)(void*)(&__IPSBAR[0x0000D8])) -#define MCF_CS_CSCR7 (*(vuint16*)(void*)(&__IPSBAR[0x0000DE])) -#define MCF_CS_CSAR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000080+((x)*0x00C)])) -#define MCF_CS_CSMR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000084+((x)*0x00C)])) -#define MCF_CS_CSCR(x) (*(vuint16*)(void*)(&__IPSBAR[0x00008A+((x)*0x00C)])) - -/* Bit definitions and macros for MCF_CS_CSAR */ -#define MCF_CS_CSAR_BA(x) ((uint16)(((x)&0xFFFF0000)>>16)) - -/* Bit definitions and macros for MCF_CS_CSMR */ -#define MCF_CS_CSMR_V (0x00000001) -#define MCF_CS_CSMR_UD (0x00000002) -#define MCF_CS_CSMR_UC (0x00000004) -#define MCF_CS_CSMR_SD (0x00000008) -#define MCF_CS_CSMR_SC (0x00000010) -#define MCF_CS_CSMR_CI (0x00000020) -#define MCF_CS_CSMR_AM (0x00000040) -#define MCF_CS_CSMR_WP (0x00000100) -#define MCF_CS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) -#define MCF_CS_CSMR_BAM_4G (0xFFFF0000) -#define MCF_CS_CSMR_BAM_2G (0x7FFF0000) -#define MCF_CS_CSMR_BAM_1G (0x3FFF0000) -#define MCF_CS_CSMR_BAM_1024M (0x3FFF0000) -#define MCF_CS_CSMR_BAM_512M (0x1FFF0000) -#define MCF_CS_CSMR_BAM_256M (0x0FFF0000) -#define MCF_CS_CSMR_BAM_128M (0x07FF0000) -#define MCF_CS_CSMR_BAM_64M (0x03FF0000) -#define MCF_CS_CSMR_BAM_32M (0x01FF0000) -#define MCF_CS_CSMR_BAM_16M (0x00FF0000) -#define MCF_CS_CSMR_BAM_8M (0x007F0000) -#define MCF_CS_CSMR_BAM_4M (0x003F0000) -#define MCF_CS_CSMR_BAM_2M (0x001F0000) -#define MCF_CS_CSMR_BAM_1M (0x000F0000) -#define MCF_CS_CSMR_BAM_1024K (0x000F0000) -#define MCF_CS_CSMR_BAM_512K (0x00070000) -#define MCF_CS_CSMR_BAM_256K (0x00030000) -#define MCF_CS_CSMR_BAM_128K (0x00010000) -#define MCF_CS_CSMR_BAM_64K (0x00000000) - -/* Bit definitions and macros for MCF_CS_CSCR */ -#define MCF_CS_CSCR_SWWS(x) (((x)&0x0007)<<0) -#define MCF_CS_CSCR_BSTW (0x0008) -#define MCF_CS_CSCR_BSTR (0x0010) -#define MCF_CS_CSCR_BEM (0x0020) -#define MCF_CS_CSCR_PS(x) (((x)&0x0003)<<6) -#define MCF_CS_CSCR_AA (0x0100) -#define MCF_CS_CSCR_IWS(x) (((x)&0x000F)<<10) -#define MCF_CS_CSCR_SRWS(x) (((x)&0x0003)<<14) -#define MCF_CS_CSCR_PS_8 (0x0040) -#define MCF_CS_CSCR_PS_16 (0x0080) -#define MCF_CS_CSCR_PS_32 (0x0000) - -/********************************************************************/ - -#endif /* __MCF523X_CS_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_eport.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_eport.h deleted file mode 100644 index f84045bdf..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_eport.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * File: mcf523x_eport.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_EPORT_H__ -#define __MCF523X_EPORT_H__ - -/********************************************************************* -* -* Edge Port Module (EPORT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_EPORT_EPPAR (*(vuint16*)(void*)(&__IPSBAR[0x130000])) -#define MCF_EPORT_EPDDR (*(vuint8 *)(void*)(&__IPSBAR[0x130002])) -#define MCF_EPORT_EPIER (*(vuint8 *)(void*)(&__IPSBAR[0x130003])) -#define MCF_EPORT_EPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130004])) -#define MCF_EPORT_EPPDR (*(vuint8 *)(void*)(&__IPSBAR[0x130005])) -#define MCF_EPORT_EPFR (*(vuint8 *)(void*)(&__IPSBAR[0x130006])) - -/* Bit definitions and macros for MCF_EPORT_EPPAR */ -#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) -#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) -#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) -#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) -#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) -#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) -#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) -#define MCF_EPORT_EPPAR_EPPAx_LEVEL (0) -#define MCF_EPORT_EPPAR_EPPAx_RISING (1) -#define MCF_EPORT_EPPAR_EPPAx_FALLING (2) -#define MCF_EPORT_EPPAR_EPPAx_BOTH (3) - -/* Bit definitions and macros for MCF_EPORT_EPDDR */ -#define MCF_EPORT_EPDDR_EPDD1 (0x02) -#define MCF_EPORT_EPDDR_EPDD2 (0x04) -#define MCF_EPORT_EPDDR_EPDD3 (0x08) -#define MCF_EPORT_EPDDR_EPDD4 (0x10) -#define MCF_EPORT_EPDDR_EPDD5 (0x20) -#define MCF_EPORT_EPDDR_EPDD6 (0x40) -#define MCF_EPORT_EPDDR_EPDD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPIER */ -#define MCF_EPORT_EPIER_EPIE1 (0x02) -#define MCF_EPORT_EPIER_EPIE2 (0x04) -#define MCF_EPORT_EPIER_EPIE3 (0x08) -#define MCF_EPORT_EPIER_EPIE4 (0x10) -#define MCF_EPORT_EPIER_EPIE5 (0x20) -#define MCF_EPORT_EPIER_EPIE6 (0x40) -#define MCF_EPORT_EPIER_EPIE7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPDR */ -#define MCF_EPORT_EPDR_EPD1 (0x02) -#define MCF_EPORT_EPDR_EPD2 (0x04) -#define MCF_EPORT_EPDR_EPD3 (0x08) -#define MCF_EPORT_EPDR_EPD4 (0x10) -#define MCF_EPORT_EPDR_EPD5 (0x20) -#define MCF_EPORT_EPDR_EPD6 (0x40) -#define MCF_EPORT_EPDR_EPD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPPDR */ -#define MCF_EPORT_EPPDR_EPPD1 (0x02) -#define MCF_EPORT_EPPDR_EPPD2 (0x04) -#define MCF_EPORT_EPPDR_EPPD3 (0x08) -#define MCF_EPORT_EPPDR_EPPD4 (0x10) -#define MCF_EPORT_EPPDR_EPPD5 (0x20) -#define MCF_EPORT_EPPDR_EPPD6 (0x40) -#define MCF_EPORT_EPPDR_EPPD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPFR */ -#define MCF_EPORT_EPFR_EPF1 (0x02) -#define MCF_EPORT_EPFR_EPF2 (0x04) -#define MCF_EPORT_EPFR_EPF3 (0x08) -#define MCF_EPORT_EPFR_EPF4 (0x10) -#define MCF_EPORT_EPFR_EPF5 (0x20) -#define MCF_EPORT_EPFR_EPF6 (0x40) -#define MCF_EPORT_EPFR_EPF7 (0x80) - -/********************************************************************/ - -#endif /* __MCF523X_EPORT_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_etpu.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_etpu.h deleted file mode 100644 index 5541e8d01..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_etpu.h +++ /dev/null @@ -1,487 +0,0 @@ -/* - * File: mcf523x_etpu.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_ETPU_H__ -#define __MCF523X_ETPU_H__ - -/********************************************************************* -* -* enhanced Time Processor Unit (ETPU) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_ETPU_EMCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0000])) -#define MCF_ETPU_ECDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0004])) -#define MCF_ETPU_EMISCCR (*(vuint32*)(void*)(&__IPSBAR[0x1D000C])) -#define MCF_ETPU_ESCMODR (*(vuint32*)(void*)(&__IPSBAR[0x1D0010])) -#define MCF_ETPU_EECR (*(vuint32*)(void*)(&__IPSBAR[0x1D0014])) -#define MCF_ETPU_ETBCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0020])) -#define MCF_ETPU_ETB1R (*(vuint32*)(void*)(&__IPSBAR[0x1D0024])) -#define MCF_ETPU_ETB2R (*(vuint32*)(void*)(&__IPSBAR[0x1D0028])) -#define MCF_ETPU_EREDCR (*(vuint32*)(void*)(&__IPSBAR[0x1D002C])) -#define MCF_ETPU_ECISR (*(vuint32*)(void*)(&__IPSBAR[0x1D0200])) -#define MCF_ETPU_ECDTRSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0210])) -#define MCF_ETPU_ECIOSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0220])) -#define MCF_ETPU_ECDTROSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0230])) -#define MCF_ETPU_ECIER (*(vuint32*)(void*)(&__IPSBAR[0x1D0240])) -#define MCF_ETPU_ECDTRER (*(vuint32*)(void*)(&__IPSBAR[0x1D0250])) -#define MCF_ETPU_ECPSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0280])) -#define MCF_ETPU_ECSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0290])) -#define MCF_ETPU_EC0SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0404])) -#define MCF_ETPU_EC1SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0414])) -#define MCF_ETPU_EC2SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0424])) -#define MCF_ETPU_EC3SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0434])) -#define MCF_ETPU_EC4SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0444])) -#define MCF_ETPU_EC5SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0454])) -#define MCF_ETPU_EC6SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0464])) -#define MCF_ETPU_EC7SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0474])) -#define MCF_ETPU_EC8SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0484])) -#define MCF_ETPU_EC9SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0494])) -#define MCF_ETPU_EC10SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A4])) -#define MCF_ETPU_EC11SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B4])) -#define MCF_ETPU_EC12SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C4])) -#define MCF_ETPU_EC13SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D4])) -#define MCF_ETPU_EC14SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E4])) -#define MCF_ETPU_EC15SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F4])) -#define MCF_ETPU_EC16SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0504])) -#define MCF_ETPU_EC17SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0514])) -#define MCF_ETPU_EC18SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0524])) -#define MCF_ETPU_EC19SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0534])) -#define MCF_ETPU_EC20SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0544])) -#define MCF_ETPU_EC21SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0554])) -#define MCF_ETPU_EC22SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0564])) -#define MCF_ETPU_EC23SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0574])) -#define MCF_ETPU_EC24SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0584])) -#define MCF_ETPU_EC25SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D0594])) -#define MCF_ETPU_EC26SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A4])) -#define MCF_ETPU_EC27SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B4])) -#define MCF_ETPU_EC28SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C4])) -#define MCF_ETPU_EC29SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D4])) -#define MCF_ETPU_EC30SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E4])) -#define MCF_ETPU_EC31SCR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F4])) -#define MCF_ETPU_ECnSCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0404+((x)*0x010)])) -#define MCF_ETPU_EC0CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0400])) -#define MCF_ETPU_EC1CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0410])) -#define MCF_ETPU_EC2CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0420])) -#define MCF_ETPU_EC3CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0430])) -#define MCF_ETPU_EC4CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0440])) -#define MCF_ETPU_EC5CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0450])) -#define MCF_ETPU_EC6CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0460])) -#define MCF_ETPU_EC7CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0470])) -#define MCF_ETPU_EC8CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0480])) -#define MCF_ETPU_EC9CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0490])) -#define MCF_ETPU_EC10CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A0])) -#define MCF_ETPU_EC11CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B0])) -#define MCF_ETPU_EC12CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C0])) -#define MCF_ETPU_EC13CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D0])) -#define MCF_ETPU_EC14CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E0])) -#define MCF_ETPU_EC15CR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F0])) -#define MCF_ETPU_EC16CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0500])) -#define MCF_ETPU_EC17CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0510])) -#define MCF_ETPU_EC18CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0520])) -#define MCF_ETPU_EC19CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0530])) -#define MCF_ETPU_EC20CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0540])) -#define MCF_ETPU_EC21CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0550])) -#define MCF_ETPU_EC22CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0560])) -#define MCF_ETPU_EC23CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0570])) -#define MCF_ETPU_EC24CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0580])) -#define MCF_ETPU_EC25CR (*(vuint32*)(void*)(&__IPSBAR[0x1D0590])) -#define MCF_ETPU_EC26CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A0])) -#define MCF_ETPU_EC27CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B0])) -#define MCF_ETPU_EC28CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C0])) -#define MCF_ETPU_EC29CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D0])) -#define MCF_ETPU_EC30CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E0])) -#define MCF_ETPU_EC31CR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F0])) -#define MCF_ETPU_ECnCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0400+((x)*0x010)])) -#define MCF_ETPU_EC0HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0408])) -#define MCF_ETPU_EC1HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0418])) -#define MCF_ETPU_EC2HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0428])) -#define MCF_ETPU_EC3HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0438])) -#define MCF_ETPU_EC4HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0448])) -#define MCF_ETPU_EC5HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0458])) -#define MCF_ETPU_EC6HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0468])) -#define MCF_ETPU_EC7HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0478])) -#define MCF_ETPU_EC8HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0488])) -#define MCF_ETPU_EC9HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0498])) -#define MCF_ETPU_EC10HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04A8])) -#define MCF_ETPU_EC11HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04B8])) -#define MCF_ETPU_EC12HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04C8])) -#define MCF_ETPU_EC13HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04D8])) -#define MCF_ETPU_EC14HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04E8])) -#define MCF_ETPU_EC15HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D04F8])) -#define MCF_ETPU_EC16HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0508])) -#define MCF_ETPU_EC17HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0518])) -#define MCF_ETPU_EC18HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0528])) -#define MCF_ETPU_EC19HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0538])) -#define MCF_ETPU_EC20HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0548])) -#define MCF_ETPU_EC21HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0558])) -#define MCF_ETPU_EC22HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0568])) -#define MCF_ETPU_EC23HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0578])) -#define MCF_ETPU_EC24HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0588])) -#define MCF_ETPU_EC25HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D0598])) -#define MCF_ETPU_EC26HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05A8])) -#define MCF_ETPU_EC27HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05B8])) -#define MCF_ETPU_EC28HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05C8])) -#define MCF_ETPU_EC29HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05D8])) -#define MCF_ETPU_EC30HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05E8])) -#define MCF_ETPU_EC31HSSR (*(vuint32*)(void*)(&__IPSBAR[0x1D05F8])) -#define MCF_ETPU_ECnHSSR(x) (*(vuint32*)(void*)(&__IPSBAR[0x1D0408+((x)*0x010)])) - -/* Bit definitions and macros for MCF_ETPU_EMCR */ -#define MCF_ETPU_EMCR_GTBE (0x00000001) -#define MCF_ETPU_EMCR_VIS (0x00000040) -#define MCF_ETPU_EMCR_SCMMISEN (0x00000200) -#define MCF_ETPU_EMCR_SCMMISF (0x00000400) -#define MCF_ETPU_EMCR_SCMSIZE(x) (((x)&0x0000001F)<<16) -#define MCF_ETPU_EMCR_ILF2 (0x01000000) -#define MCF_ETPU_EMCR_ILF1 (0x02000000) -#define MCF_ETPU_EMCR_MGE2 (0x04000000) -#define MCF_ETPU_EMCR_MGE1 (0x08000000) -#define MCF_ETPU_EMCR_GEC (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECDCR */ -#define MCF_ETPU_ECDCR_PARM1(x) (((x)&0x0000007F)<<0) -#define MCF_ETPU_ECDCR_WR (0x00000080) -#define MCF_ETPU_ECDCR_PARM0(x) (((x)&0x0000007F)<<8) -#define MCF_ETPU_ECDCR_PWIDTH (0x00008000) -#define MCF_ETPU_ECDCR_PBASE(x) (((x)&0x000003FF)<<16) -#define MCF_ETPU_ECDCR_CTBASE(x) (((x)&0x0000001F)<<26) -#define MCF_ETPU_ECDCR_STS (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_EECR */ -#define MCF_ETPU_EECR_ETB(x) (((x)&0x0000001F)<<0) -#define MCF_ETPU_EECR_CDFC(x) (((x)&0x00000003)<<14) -#define MCF_ETPU_EECR_FPSK(x) (((x)&0x00000007)<<16) -#define MCF_ETPU_EECR_HLTF (0x00800000) -#define MCF_ETPU_EECR_STF (0x10000000) -#define MCF_ETPU_EECR_MDIS (0x40000000) -#define MCF_ETPU_EECR_FEND (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ETBCR */ -#define MCF_ETPU_ETBCR_TCR1P(x) (((x)&0x000000FF)<<0) -#define MCF_ETPU_ETBCR_TCR1CTL(x) (((x)&0x00000003)<<14) -#define MCF_ETPU_ETBCR_TCR2P(x) (((x)&0x0000003F)<<16) -#define MCF_ETPU_ETBCR_AM (0x02000000) -#define MCF_ETPU_ETBCR_TCRCF(x) (((x)&0x00000003)<<27) -#define MCF_ETPU_ETBCR_TCR2CTL(x) (((x)&0x00000007)<<29) - -/* Bit definitions and macros for MCF_ETPU_ETB1R */ -#define MCF_ETPU_ETB1R_TCR1(x) (((x)&0x00FFFFFF)<<0) - -/* Bit definitions and macros for MCF_ETPU_ETB2R */ -#define MCF_ETPU_ETB2R_TCR2(x) (((x)&0x00FFFFFF)<<0) - -/* Bit definitions and macros for MCF_ETPU_EREDCR */ -#define MCF_ETPU_EREDCR_SRV2(x) (((x)&0x0000000F)<<0) -#define MCF_ETPU_EREDCR_SERVER_ID2(x) (((x)&0x0000000F)<<8) -#define MCF_ETPU_EREDCR_RSC2 (0x00004000) -#define MCF_ETPU_EREDCR_REN2 (0x00008000) -#define MCF_ETPU_EREDCR_SRV1(x) (((x)&0x0000000F)<<16) -#define MCF_ETPU_EREDCR_SERVER_ID1(x) (((x)&0x0000000F)<<24) -#define MCF_ETPU_EREDCR_RSC1 (0x40000000) -#define MCF_ETPU_EREDCR_REN1 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECISR */ -#define MCF_ETPU_ECISR_CIS0 (0x00000001) -#define MCF_ETPU_ECISR_CIS1 (0x00000002) -#define MCF_ETPU_ECISR_CIS2 (0x00000004) -#define MCF_ETPU_ECISR_CIS3 (0x00000008) -#define MCF_ETPU_ECISR_CIS4 (0x00000010) -#define MCF_ETPU_ECISR_CIS5 (0x00000020) -#define MCF_ETPU_ECISR_CIS6 (0x00000040) -#define MCF_ETPU_ECISR_CIS7 (0x00000080) -#define MCF_ETPU_ECISR_CIS8 (0x00000100) -#define MCF_ETPU_ECISR_CIS9 (0x00000200) -#define MCF_ETPU_ECISR_CIS10 (0x00000400) -#define MCF_ETPU_ECISR_CIS11 (0x00000800) -#define MCF_ETPU_ECISR_CIS12 (0x00001000) -#define MCF_ETPU_ECISR_CIS13 (0x00002000) -#define MCF_ETPU_ECISR_CIS14 (0x00004000) -#define MCF_ETPU_ECISR_CIS15 (0x00008000) -#define MCF_ETPU_ECISR_CIS16 (0x00010000) -#define MCF_ETPU_ECISR_CIS17 (0x00020000) -#define MCF_ETPU_ECISR_CIS18 (0x00040000) -#define MCF_ETPU_ECISR_CIS19 (0x00080000) -#define MCF_ETPU_ECISR_CIS20 (0x00100000) -#define MCF_ETPU_ECISR_CIS21 (0x00200000) -#define MCF_ETPU_ECISR_CIS22 (0x00400000) -#define MCF_ETPU_ECISR_CIS23 (0x00800000) -#define MCF_ETPU_ECISR_CIS24 (0x01000000) -#define MCF_ETPU_ECISR_CIS25 (0x02000000) -#define MCF_ETPU_ECISR_CIS26 (0x04000000) -#define MCF_ETPU_ECISR_CIS27 (0x08000000) -#define MCF_ETPU_ECISR_CIS28 (0x10000000) -#define MCF_ETPU_ECISR_CIS29 (0x20000000) -#define MCF_ETPU_ECISR_CIS30 (0x40000000) -#define MCF_ETPU_ECISR_CIS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECDTRSR */ -#define MCF_ETPU_ECDTRSR_DTRS0 (0x00000001) -#define MCF_ETPU_ECDTRSR_DTRS1 (0x00000002) -#define MCF_ETPU_ECDTRSR_DTRS2 (0x00000004) -#define MCF_ETPU_ECDTRSR_DTRS3 (0x00000008) -#define MCF_ETPU_ECDTRSR_DTRS4 (0x00000010) -#define MCF_ETPU_ECDTRSR_DTRS5 (0x00000020) -#define MCF_ETPU_ECDTRSR_DTRS6 (0x00000040) -#define MCF_ETPU_ECDTRSR_DTRS7 (0x00000080) -#define MCF_ETPU_ECDTRSR_DTRS8 (0x00000100) -#define MCF_ETPU_ECDTRSR_DTRS9 (0x00000200) -#define MCF_ETPU_ECDTRSR_DTRS10 (0x00000400) -#define MCF_ETPU_ECDTRSR_DTRS11 (0x00000800) -#define MCF_ETPU_ECDTRSR_DTRS12 (0x00001000) -#define MCF_ETPU_ECDTRSR_DTRS13 (0x00002000) -#define MCF_ETPU_ECDTRSR_DTRS14 (0x00004000) -#define MCF_ETPU_ECDTRSR_DTRS15 (0x00008000) -#define MCF_ETPU_ECDTRSR_DTRS16 (0x00010000) -#define MCF_ETPU_ECDTRSR_DTRS17 (0x00020000) -#define MCF_ETPU_ECDTRSR_DTRS18 (0x00040000) -#define MCF_ETPU_ECDTRSR_DTRS19 (0x00080000) -#define MCF_ETPU_ECDTRSR_DTRS20 (0x00100000) -#define MCF_ETPU_ECDTRSR_DTRS21 (0x00200000) -#define MCF_ETPU_ECDTRSR_DTRS22 (0x00400000) -#define MCF_ETPU_ECDTRSR_DTRS23 (0x00800000) -#define MCF_ETPU_ECDTRSR_DTRS24 (0x01000000) -#define MCF_ETPU_ECDTRSR_DTRS25 (0x02000000) -#define MCF_ETPU_ECDTRSR_DTRS26 (0x04000000) -#define MCF_ETPU_ECDTRSR_DTRS27 (0x08000000) -#define MCF_ETPU_ECDTRSR_DTRS28 (0x10000000) -#define MCF_ETPU_ECDTRSR_DTRS29 (0x20000000) -#define MCF_ETPU_ECDTRSR_DTRS30 (0x40000000) -#define MCF_ETPU_ECDTRSR_DTRS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECIOSR */ -#define MCF_ETPU_ECIOSR_CIOS0 (0x00000001) -#define MCF_ETPU_ECIOSR_CIOS1 (0x00000002) -#define MCF_ETPU_ECIOSR_CIOS2 (0x00000004) -#define MCF_ETPU_ECIOSR_CIOS3 (0x00000008) -#define MCF_ETPU_ECIOSR_CIOS4 (0x00000010) -#define MCF_ETPU_ECIOSR_CIOS5 (0x00000020) -#define MCF_ETPU_ECIOSR_CIOS6 (0x00000040) -#define MCF_ETPU_ECIOSR_CIOS7 (0x00000080) -#define MCF_ETPU_ECIOSR_CIOS8 (0x00000100) -#define MCF_ETPU_ECIOSR_CIOS9 (0x00000200) -#define MCF_ETPU_ECIOSR_CIOS10 (0x00000400) -#define MCF_ETPU_ECIOSR_CIOS11 (0x00000800) -#define MCF_ETPU_ECIOSR_CIOS12 (0x00001000) -#define MCF_ETPU_ECIOSR_CIOS13 (0x00002000) -#define MCF_ETPU_ECIOSR_CIOS14 (0x00004000) -#define MCF_ETPU_ECIOSR_CIOS15 (0x00008000) -#define MCF_ETPU_ECIOSR_CIOS16 (0x00010000) -#define MCF_ETPU_ECIOSR_CIOS17 (0x00020000) -#define MCF_ETPU_ECIOSR_CIOS18 (0x00040000) -#define MCF_ETPU_ECIOSR_CIOS19 (0x00080000) -#define MCF_ETPU_ECIOSR_CIOS20 (0x00100000) -#define MCF_ETPU_ECIOSR_CIOS21 (0x00200000) -#define MCF_ETPU_ECIOSR_CIOS22 (0x00400000) -#define MCF_ETPU_ECIOSR_CIOS23 (0x00800000) -#define MCF_ETPU_ECIOSR_CIOS24 (0x01000000) -#define MCF_ETPU_ECIOSR_CIOS25 (0x02000000) -#define MCF_ETPU_ECIOSR_CIOS26 (0x04000000) -#define MCF_ETPU_ECIOSR_CIOS27 (0x08000000) -#define MCF_ETPU_ECIOSR_CIOS28 (0x10000000) -#define MCF_ETPU_ECIOSR_CIOS29 (0x20000000) -#define MCF_ETPU_ECIOSR_CIOS30 (0x40000000) -#define MCF_ETPU_ECIOSR_CIOS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECDTROSR */ -#define MCF_ETPU_ECDTROSR_DTROS0 (0x00000001) -#define MCF_ETPU_ECDTROSR_DTROS1 (0x00000002) -#define MCF_ETPU_ECDTROSR_DTROS2 (0x00000004) -#define MCF_ETPU_ECDTROSR_DTROS3 (0x00000008) -#define MCF_ETPU_ECDTROSR_DTROS4 (0x00000010) -#define MCF_ETPU_ECDTROSR_DTROS5 (0x00000020) -#define MCF_ETPU_ECDTROSR_DTROS6 (0x00000040) -#define MCF_ETPU_ECDTROSR_DTROS7 (0x00000080) -#define MCF_ETPU_ECDTROSR_DTROS8 (0x00000100) -#define MCF_ETPU_ECDTROSR_DTROS9 (0x00000200) -#define MCF_ETPU_ECDTROSR_DTROS10 (0x00000400) -#define MCF_ETPU_ECDTROSR_DTROS11 (0x00000800) -#define MCF_ETPU_ECDTROSR_DTROS12 (0x00001000) -#define MCF_ETPU_ECDTROSR_DTROS13 (0x00002000) -#define MCF_ETPU_ECDTROSR_DTROS14 (0x00004000) -#define MCF_ETPU_ECDTROSR_DTROS15 (0x00008000) -#define MCF_ETPU_ECDTROSR_DTROS16 (0x00010000) -#define MCF_ETPU_ECDTROSR_DTROS17 (0x00020000) -#define MCF_ETPU_ECDTROSR_DTROS18 (0x00040000) -#define MCF_ETPU_ECDTROSR_DTROS19 (0x00080000) -#define MCF_ETPU_ECDTROSR_DTROS20 (0x00100000) -#define MCF_ETPU_ECDTROSR_DTROS21 (0x00200000) -#define MCF_ETPU_ECDTROSR_DTROS22 (0x00400000) -#define MCF_ETPU_ECDTROSR_DTROS23 (0x00800000) -#define MCF_ETPU_ECDTROSR_DTROS24 (0x01000000) -#define MCF_ETPU_ECDTROSR_DTROS25 (0x02000000) -#define MCF_ETPU_ECDTROSR_DTROS26 (0x04000000) -#define MCF_ETPU_ECDTROSR_DTROS27 (0x08000000) -#define MCF_ETPU_ECDTROSR_DTROS28 (0x10000000) -#define MCF_ETPU_ECDTROSR_DTROS29 (0x20000000) -#define MCF_ETPU_ECDTROSR_DTROS30 (0x40000000) -#define MCF_ETPU_ECDTROSR_DTROS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECIER */ -#define MCF_ETPU_ECIER_CIE0 (0x00000001) -#define MCF_ETPU_ECIER_CIE1 (0x00000002) -#define MCF_ETPU_ECIER_CIE2 (0x00000004) -#define MCF_ETPU_ECIER_CIE3 (0x00000008) -#define MCF_ETPU_ECIER_CIE4 (0x00000010) -#define MCF_ETPU_ECIER_CIE5 (0x00000020) -#define MCF_ETPU_ECIER_CIE6 (0x00000040) -#define MCF_ETPU_ECIER_CIE7 (0x00000080) -#define MCF_ETPU_ECIER_CIE8 (0x00000100) -#define MCF_ETPU_ECIER_CIE9 (0x00000200) -#define MCF_ETPU_ECIER_CIE10 (0x00000400) -#define MCF_ETPU_ECIER_CIE11 (0x00000800) -#define MCF_ETPU_ECIER_CIE12 (0x00001000) -#define MCF_ETPU_ECIER_CIE13 (0x00002000) -#define MCF_ETPU_ECIER_CIE14 (0x00004000) -#define MCF_ETPU_ECIER_CIE15 (0x00008000) -#define MCF_ETPU_ECIER_CIE16 (0x00010000) -#define MCF_ETPU_ECIER_CIE17 (0x00020000) -#define MCF_ETPU_ECIER_CIE18 (0x00040000) -#define MCF_ETPU_ECIER_CIE19 (0x00080000) -#define MCF_ETPU_ECIER_CIE20 (0x00100000) -#define MCF_ETPU_ECIER_CIE21 (0x00200000) -#define MCF_ETPU_ECIER_CIE22 (0x00400000) -#define MCF_ETPU_ECIER_CIE23 (0x00800000) -#define MCF_ETPU_ECIER_CIE24 (0x01000000) -#define MCF_ETPU_ECIER_CIE25 (0x02000000) -#define MCF_ETPU_ECIER_CIE26 (0x04000000) -#define MCF_ETPU_ECIER_CIE27 (0x08000000) -#define MCF_ETPU_ECIER_CIE28 (0x10000000) -#define MCF_ETPU_ECIER_CIE29 (0x20000000) -#define MCF_ETPU_ECIER_CIE30 (0x40000000) -#define MCF_ETPU_ECIER_CIE31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECDTRER */ -#define MCF_ETPU_ECDTRER_DTRE0 (0x00000001) -#define MCF_ETPU_ECDTRER_DTRE1 (0x00000002) -#define MCF_ETPU_ECDTRER_DTRE2 (0x00000004) -#define MCF_ETPU_ECDTRER_DTRE3 (0x00000008) -#define MCF_ETPU_ECDTRER_DTRE4 (0x00000010) -#define MCF_ETPU_ECDTRER_DTRE5 (0x00000020) -#define MCF_ETPU_ECDTRER_DTRE6 (0x00000040) -#define MCF_ETPU_ECDTRER_DTRE7 (0x00000080) -#define MCF_ETPU_ECDTRER_DTRE8 (0x00000100) -#define MCF_ETPU_ECDTRER_DTRE9 (0x00000200) -#define MCF_ETPU_ECDTRER_DTRE10 (0x00000400) -#define MCF_ETPU_ECDTRER_DTRE11 (0x00000800) -#define MCF_ETPU_ECDTRER_DTRE12 (0x00001000) -#define MCF_ETPU_ECDTRER_DTRE13 (0x00002000) -#define MCF_ETPU_ECDTRER_DTRE14 (0x00004000) -#define MCF_ETPU_ECDTRER_DTRE15 (0x00008000) -#define MCF_ETPU_ECDTRER_DTRE16 (0x00010000) -#define MCF_ETPU_ECDTRER_DTRE17 (0x00020000) -#define MCF_ETPU_ECDTRER_DTRE18 (0x00040000) -#define MCF_ETPU_ECDTRER_DTRE19 (0x00080000) -#define MCF_ETPU_ECDTRER_DTRE20 (0x00100000) -#define MCF_ETPU_ECDTRER_DTRE21 (0x00200000) -#define MCF_ETPU_ECDTRER_DTRE22 (0x00400000) -#define MCF_ETPU_ECDTRER_DTRE23 (0x00800000) -#define MCF_ETPU_ECDTRER_DTRE24 (0x01000000) -#define MCF_ETPU_ECDTRER_DTRE25 (0x02000000) -#define MCF_ETPU_ECDTRER_DTRE26 (0x04000000) -#define MCF_ETPU_ECDTRER_DTRE27 (0x08000000) -#define MCF_ETPU_ECDTRER_DTRE28 (0x10000000) -#define MCF_ETPU_ECDTRER_DTRE29 (0x20000000) -#define MCF_ETPU_ECDTRER_DTRE30 (0x40000000) -#define MCF_ETPU_ECDTRER_DTRE31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECPSSR */ -#define MCF_ETPU_ECPSSR_SR0 (0x00000001) -#define MCF_ETPU_ECPSSR_SR1 (0x00000002) -#define MCF_ETPU_ECPSSR_SR2 (0x00000004) -#define MCF_ETPU_ECPSSR_SR3 (0x00000008) -#define MCF_ETPU_ECPSSR_SR4 (0x00000010) -#define MCF_ETPU_ECPSSR_SR5 (0x00000020) -#define MCF_ETPU_ECPSSR_SR6 (0x00000040) -#define MCF_ETPU_ECPSSR_SR7 (0x00000080) -#define MCF_ETPU_ECPSSR_SR8 (0x00000100) -#define MCF_ETPU_ECPSSR_SR9 (0x00000200) -#define MCF_ETPU_ECPSSR_SR10 (0x00000400) -#define MCF_ETPU_ECPSSR_SR11 (0x00000800) -#define MCF_ETPU_ECPSSR_SR12 (0x00001000) -#define MCF_ETPU_ECPSSR_SR13 (0x00002000) -#define MCF_ETPU_ECPSSR_SR14 (0x00004000) -#define MCF_ETPU_ECPSSR_SR15 (0x00008000) -#define MCF_ETPU_ECPSSR_SR16 (0x00010000) -#define MCF_ETPU_ECPSSR_SR17 (0x00020000) -#define MCF_ETPU_ECPSSR_SR18 (0x00040000) -#define MCF_ETPU_ECPSSR_SR19 (0x00080000) -#define MCF_ETPU_ECPSSR_SR20 (0x00100000) -#define MCF_ETPU_ECPSSR_SR21 (0x00200000) -#define MCF_ETPU_ECPSSR_SR22 (0x00400000) -#define MCF_ETPU_ECPSSR_SR23 (0x00800000) -#define MCF_ETPU_ECPSSR_SR24 (0x01000000) -#define MCF_ETPU_ECPSSR_SR25 (0x02000000) -#define MCF_ETPU_ECPSSR_SR26 (0x04000000) -#define MCF_ETPU_ECPSSR_SR27 (0x08000000) -#define MCF_ETPU_ECPSSR_SR28 (0x10000000) -#define MCF_ETPU_ECPSSR_SR29 (0x20000000) -#define MCF_ETPU_ECPSSR_SR30 (0x40000000) -#define MCF_ETPU_ECPSSR_SR31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECSSR */ -#define MCF_ETPU_ECSSR_SS0 (0x00000001) -#define MCF_ETPU_ECSSR_SS1 (0x00000002) -#define MCF_ETPU_ECSSR_SS2 (0x00000004) -#define MCF_ETPU_ECSSR_SS3 (0x00000008) -#define MCF_ETPU_ECSSR_SS4 (0x00000010) -#define MCF_ETPU_ECSSR_SS5 (0x00000020) -#define MCF_ETPU_ECSSR_SS6 (0x00000040) -#define MCF_ETPU_ECSSR_SS7 (0x00000080) -#define MCF_ETPU_ECSSR_SS8 (0x00000100) -#define MCF_ETPU_ECSSR_SS9 (0x00000200) -#define MCF_ETPU_ECSSR_SS10 (0x00000400) -#define MCF_ETPU_ECSSR_SS11 (0x00000800) -#define MCF_ETPU_ECSSR_SS12 (0x00001000) -#define MCF_ETPU_ECSSR_SS13 (0x00002000) -#define MCF_ETPU_ECSSR_SS14 (0x00004000) -#define MCF_ETPU_ECSSR_SS15 (0x00008000) -#define MCF_ETPU_ECSSR_SS16 (0x00010000) -#define MCF_ETPU_ECSSR_SS17 (0x00020000) -#define MCF_ETPU_ECSSR_SS18 (0x00040000) -#define MCF_ETPU_ECSSR_SS19 (0x00080000) -#define MCF_ETPU_ECSSR_SS20 (0x00100000) -#define MCF_ETPU_ECSSR_SS21 (0x00200000) -#define MCF_ETPU_ECSSR_SS22 (0x00400000) -#define MCF_ETPU_ECSSR_SS23 (0x00800000) -#define MCF_ETPU_ECSSR_SS24 (0x01000000) -#define MCF_ETPU_ECSSR_SS25 (0x02000000) -#define MCF_ETPU_ECSSR_SS26 (0x04000000) -#define MCF_ETPU_ECSSR_SS27 (0x08000000) -#define MCF_ETPU_ECSSR_SS28 (0x10000000) -#define MCF_ETPU_ECSSR_SS29 (0x20000000) -#define MCF_ETPU_ECSSR_SS30 (0x40000000) -#define MCF_ETPU_ECSSR_SS31 (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECnSCR */ -#define MCF_ETPU_ECnSCR_FM(x) (((x)&0x00000003)<<0) -#define MCF_ETPU_ECnSCR_OBE (0x00002000) -#define MCF_ETPU_ECnSCR_OPS (0x00004000) -#define MCF_ETPU_ECnSCR_IPS (0x00008000) -#define MCF_ETPU_ECnSCR_DTROS (0x00400000) -#define MCF_ETPU_ECnSCR_DTRS (0x00800000) -#define MCF_ETPU_ECnSCR_CIOS (0x40000000) -#define MCF_ETPU_ECnSCR_CIS (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECnCR */ -#define MCF_ETPU_ECnCR_CPBA(x) (((x)&0x000007FF)<<0) -#define MCF_ETPU_ECnCR_OPOL (0x00004000) -#define MCF_ETPU_ECnCR_ODIS (0x00008000) -#define MCF_ETPU_ECnCR_CFS(x) (((x)&0x0000001F)<<16) -#define MCF_ETPU_ECnCR_ETCS (0x01000000) -#define MCF_ETPU_ECnCR_CPR(x) (((x)&0x00000003)<<28) -#define MCF_ETPU_ECnCR_DTRE (0x40000000) -#define MCF_ETPU_ECnCR_CIE (0x80000000) - -/* Bit definitions and macros for MCF_ETPU_ECnHSSR */ -#define MCF_ETPU_ECnHSSR_HSR(x) (((x)&0x00000007)<<0) - -/********************************************************************/ - -#endif /* __MCF523X_ETPU_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_fec.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_fec.h deleted file mode 100644 index a03c30936..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_fec.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * File: mcf523x_fec.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_FEC_H__ -#define __MCF523X_FEC_H__ - -/********************************************************************* -* -* Fast Ethernet Controller (FEC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_FEC_EIR (*(vuint32*)(void*)(&__IPSBAR[0x001004])) -#define MCF_FEC_EIMR (*(vuint32*)(void*)(&__IPSBAR[0x001008])) -#define MCF_FEC_RDAR (*(vuint32*)(void*)(&__IPSBAR[0x001010])) -#define MCF_FEC_TDAR (*(vuint32*)(void*)(&__IPSBAR[0x001014])) -#define MCF_FEC_ECR (*(vuint32*)(void*)(&__IPSBAR[0x001024])) -#define MCF_FEC_MMFR (*(vuint32*)(void*)(&__IPSBAR[0x001040])) -#define MCF_FEC_MSCR (*(vuint32*)(void*)(&__IPSBAR[0x001044])) -#define MCF_FEC_MIBC (*(vuint32*)(void*)(&__IPSBAR[0x001064])) -#define MCF_FEC_RCR (*(vuint32*)(void*)(&__IPSBAR[0x001084])) -#define MCF_FEC_TCR (*(vuint32*)(void*)(&__IPSBAR[0x0010C4])) -#define MCF_FEC_PALR (*(vuint32*)(void*)(&__IPSBAR[0x0010E4])) -#define MCF_FEC_PAUR (*(vuint32*)(void*)(&__IPSBAR[0x0010E8])) -#define MCF_FEC_OPD (*(vuint32*)(void*)(&__IPSBAR[0x0010EC])) -#define MCF_FEC_IAUR (*(vuint32*)(void*)(&__IPSBAR[0x001118])) -#define MCF_FEC_IALR (*(vuint32*)(void*)(&__IPSBAR[0x00111C])) -#define MCF_FEC_GAUR (*(vuint32*)(void*)(&__IPSBAR[0x001120])) -#define MCF_FEC_GALR (*(vuint32*)(void*)(&__IPSBAR[0x001124])) -#define MCF_FEC_TFWR (*(vuint32*)(void*)(&__IPSBAR[0x001144])) -#define MCF_FEC_FRBR (*(vuint32*)(void*)(&__IPSBAR[0x00114C])) -#define MCF_FEC_FRSR (*(vuint32*)(void*)(&__IPSBAR[0x001150])) -#define MCF_FEC_ERDSR (*(vuint32*)(void*)(&__IPSBAR[0x001180])) -#define MCF_FEC_ETDSR (*(vuint32*)(void*)(&__IPSBAR[0x001184])) -#define MCF_FEC_EMRBR (*(vuint32*)(void*)(&__IPSBAR[0x001188])) -#define MCF_FEC_RMON_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001200])) -#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001204])) -#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001208])) -#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00120C])) -#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001210])) -#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001214])) -#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001218])) -#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00121C])) -#define MCF_FEC_RMON_T_JAB (*(vuint32*)(void*)(&__IPSBAR[0x001220])) -#define MCF_FEC_RMON_T_COL (*(vuint32*)(void*)(&__IPSBAR[0x001224])) -#define MCF_FEC_RMON_T_P64 (*(vuint32*)(void*)(&__IPSBAR[0x001228])) -#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x00122C])) -#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x001230])) -#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x001234])) -#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x001238])) -#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x00123C])) -#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x001240])) -#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x001244])) -#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(void*)(&__IPSBAR[0x001248])) -#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x00124C])) -#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(void*)(&__IPSBAR[0x001250])) -#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(void*)(&__IPSBAR[0x001254])) -#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(void*)(&__IPSBAR[0x001258])) -#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(void*)(&__IPSBAR[0x00125C])) -#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(void*)(&__IPSBAR[0x001260])) -#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x001264])) -#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(void*)(&__IPSBAR[0x001268])) -#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(void*)(&__IPSBAR[0x00126C])) -#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x001270])) -#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x001274])) -#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(void*)(&__IPSBAR[0x001284])) -#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x001288])) -#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(void*)(&__IPSBAR[0x00128C])) -#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x001290])) -#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001294])) -#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(void*)(&__IPSBAR[0x001298])) -#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(void*)(&__IPSBAR[0x00129C])) -#define MCF_FEC_RMON_R_JAB (*(vuint32*)(void*)(&__IPSBAR[0x0012A0])) -#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(void*)(&__IPSBAR[0x0012A4])) -#define MCF_FEC_RMON_R_P64 (*(vuint32*)(void*)(&__IPSBAR[0x0012A8])) -#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(void*)(&__IPSBAR[0x0012AC])) -#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(void*)(&__IPSBAR[0x0012B0])) -#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(void*)(&__IPSBAR[0x0012B4])) -#define MCF_FEC_RMON_R_512TO1023 (*(vuint32*)(void*)(&__IPSBAR[0x0012B8])) -#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(void*)(&__IPSBAR[0x0012C0])) -#define MCF_FEC_RMON_R_1024TO2047 (*(vuint32*)(void*)(&__IPSBAR[0x0012BC])) -#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(void*)(&__IPSBAR[0x0012C4])) -#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(void*)(&__IPSBAR[0x0012C8])) -#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012CC])) -#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(void*)(&__IPSBAR[0x0012D0])) -#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(void*)(&__IPSBAR[0x0012D4])) -#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(void*)(&__IPSBAR[0x0012D8])) -#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(void*)(&__IPSBAR[0x0012DC])) -#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(void*)(&__IPSBAR[0x0012E0])) - -/* Bit definitions and macros for MCF_FEC_EIR */ -#define MCF_FEC_EIR_UN (0x00080000) -#define MCF_FEC_EIR_RL (0x00100000) -#define MCF_FEC_EIR_LC (0x00200000) -#define MCF_FEC_EIR_EBERR (0x00400000) -#define MCF_FEC_EIR_MII (0x00800000) -#define MCF_FEC_EIR_RXB (0x01000000) -#define MCF_FEC_EIR_RXF (0x02000000) -#define MCF_FEC_EIR_TXB (0x04000000) -#define MCF_FEC_EIR_TXF (0x08000000) -#define MCF_FEC_EIR_GRA (0x10000000) -#define MCF_FEC_EIR_BABT (0x20000000) -#define MCF_FEC_EIR_BABR (0x40000000) -#define MCF_FEC_EIR_HBERR (0x80000000) - -/* Bit definitions and macros for MCF_FEC_EIMR */ -#define MCF_FEC_EIMR_UN (0x00080000) -#define MCF_FEC_EIMR_RL (0x00100000) -#define MCF_FEC_EIMR_LC (0x00200000) -#define MCF_FEC_EIMR_EBERR (0x00400000) -#define MCF_FEC_EIMR_MII (0x00800000) -#define MCF_FEC_EIMR_RXB (0x01000000) -#define MCF_FEC_EIMR_RXF (0x02000000) -#define MCF_FEC_EIMR_TXB (0x04000000) -#define MCF_FEC_EIMR_TXF (0x08000000) -#define MCF_FEC_EIMR_GRA (0x10000000) -#define MCF_FEC_EIMR_BABT (0x20000000) -#define MCF_FEC_EIMR_BABR (0x40000000) -#define MCF_FEC_EIMR_HBERR (0x80000000) - -/* Bit definitions and macros for MCF_FEC_RDAR */ -#define MCF_FEC_RDAR_R_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for MCF_FEC_TDAR */ -#define MCF_FEC_TDAR_X_DES_ACTIVE (0x01000000) - -/* Bit definitions and macros for MCF_FEC_ECR */ -#define MCF_FEC_ECR_RESET (0x00000001) -#define MCF_FEC_ECR_ETHER_EN (0x00000002) - -/* Bit definitions and macros for MCF_FEC_MMFR */ -#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) -#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) -#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) -#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) -#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) -#define MCF_FEC_MMFR_ST_01 (0x40000000) -#define MCF_FEC_MMFR_OP_READ (0x20000000) -#define MCF_FEC_MMFR_OP_WRITE (0x10000000) -#define MCF_FEC_MMFR_TA_10 (0x00020000) - - -/* Bit definitions and macros for MCF_FEC_MSCR */ -#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) -#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080) - -/* Bit definitions and macros for MCF_FEC_MIBC */ -#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) -#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) - -/* Bit definitions and macros for MCF_FEC_RCR */ -#define MCF_FEC_RCR_LOOP (0x00000001) -#define MCF_FEC_RCR_DRT (0x00000002) -#define MCF_FEC_RCR_MII_MODE (0x00000004) -#define MCF_FEC_RCR_PROM (0x00000008) -#define MCF_FEC_RCR_BC_REJ (0x00000010) -#define MCF_FEC_RCR_FCE (0x00000020) -#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) - -/* Bit definitions and macros for MCF_FEC_TCR */ -#define MCF_FEC_TCR_GTS (0x00000001) -#define MCF_FEC_TCR_HBC (0x00000002) -#define MCF_FEC_TCR_FDEN (0x00000004) -#define MCF_FEC_TCR_TFC_PAUSE (0x00000008) -#define MCF_FEC_TCR_RFC_PAUSE (0x00000010) - -/* Bit definitions and macros for MCF_FEC_PAUR */ -#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_OPD */ -#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_TFWR */ -#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x00000003)<<0) - -/* Bit definitions and macros for MCF_FEC_FRBR */ -#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0x000000FF)<<2) - -/* Bit definitions and macros for MCF_FEC_FRSR */ -#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0x000000FF)<<2) - -/* Bit definitions and macros for MCF_FEC_ERDSR */ -#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_FEC_ETDSR */ -#define MCF_FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_FEC_EMRBR */ -#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x0000007F)<<4) - -/********************************************************************/ - -#endif /* __MCF523X_FEC_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_fmpll.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_fmpll.h deleted file mode 100644 index acf8505ac..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_fmpll.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * File: mcf523x_fmpll.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_FMPLL_H__ -#define __MCF523X_FMPLL_H__ - -/********************************************************************* -* -* Frequency Modulated Phase Locked Loop (FMPLL) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_FMPLL_SYNCR (*(vuint32*)(void*)(&__IPSBAR[0x120000])) -#define MCF_FMPLL_SYNSR (*(vuint32*)(void*)(&__IPSBAR[0x120004])) - -/* Bit definitions and macros for MCF_FMPLL_SYNCR */ -#define MCF_FMPLL_SYNCR_EXP(x) (((x)&0x000003FF)<<0) -#define MCF_FMPLL_SYNCR_DEPTH(x) (((x)&0x00000003)<<10) -#define MCF_FMPLL_SYNCR_RATE (0x00001000) -#define MCF_FMPLL_SYNCR_LOCIRQ (0x00002000) -#define MCF_FMPLL_SYNCR_LOLIRQ (0x00004000) -#define MCF_FMPLL_SYNCR_DISCLK (0x00008000) -#define MCF_FMPLL_SYNCR_LOCRE (0x00010000) -#define MCF_FMPLL_SYNCR_LOLRE (0x00020000) -#define MCF_FMPLL_SYNCR_LOCEN (0x00040000) -#define MCF_FMPLL_SYNCR_RFD(x) (((x)&0x00000007)<<19) -#define MCF_FMPLL_SYNCR_MFD(x) (((x)&0x00000007)<<24) - -/* Bit definitions and macros for MCF_FMPLL_SYNSR */ -#define MCF_FMPLL_SYNSR_CALPASS (0x00000001) -#define MCF_FMPLL_SYNSR_CALDONE (0x00000002) -#define MCF_FMPLL_SYNSR_LOCF (0x00000004) -#define MCF_FMPLL_SYNSR_LOCK (0x00000008) -#define MCF_FMPLL_SYNSR_LOCKS (0x00000010) -#define MCF_FMPLL_SYNSR_PLLREF (0x00000020) -#define MCF_FMPLL_SYNSR_PLLSEL (0x00000040) -#define MCF_FMPLL_SYNSR_MODE (0x00000080) -#define MCF_FMPLL_SYNSR_LOC (0x00000100) -#define MCF_FMPLL_SYNSR_LOLF (0x00000200) - -/********************************************************************/ - -#endif /* __MCF523X_FMPLL_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_gpio.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_gpio.h deleted file mode 100644 index 8f727370a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_gpio.h +++ /dev/null @@ -1,670 +0,0 @@ -/* - * File: mcf523x_gpio.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_GPIO_H__ -#define __MCF523X_GPIO_H__ - -/********************************************************************* -* -* General Purpose I/O (GPIO) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_GPIO_PODR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100000])) -#define MCF_GPIO_PODR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100001])) -#define MCF_GPIO_PODR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100002])) -#define MCF_GPIO_PODR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100003])) -#define MCF_GPIO_PODR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100004])) -#define MCF_GPIO_PODR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100005])) -#define MCF_GPIO_PODR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100006])) -#define MCF_GPIO_PODR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100007])) -#define MCF_GPIO_PODR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100008])) -#define MCF_GPIO_PODR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100009])) -#define MCF_GPIO_PODR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10000A])) -#define MCF_GPIO_PODR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10000B])) -#define MCF_GPIO_PODR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10000C])) -#define MCF_GPIO_PDDR_APDDR (*(vuint8 *)(void*)(&__IPSBAR[0x100010])) -#define MCF_GPIO_PDDR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100011])) -#define MCF_GPIO_PDDR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100012])) -#define MCF_GPIO_PDDR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100013])) -#define MCF_GPIO_PDDR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100014])) -#define MCF_GPIO_PDDR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100015])) -#define MCF_GPIO_PDDR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100016])) -#define MCF_GPIO_PDDR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100017])) -#define MCF_GPIO_PDDR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100018])) -#define MCF_GPIO_PDDR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100019])) -#define MCF_GPIO_PDDR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10001A])) -#define MCF_GPIO_PDDR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10001B])) -#define MCF_GPIO_PDDR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10001C])) -#define MCF_GPIO_PPDSDR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100020])) -#define MCF_GPIO_PPDSDR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100021])) -#define MCF_GPIO_PPDSDR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100022])) -#define MCF_GPIO_PPDSDR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100023])) -#define MCF_GPIO_PPDSDR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100024])) -#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100027])) -#define MCF_GPIO_PPDSDR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100025])) -#define MCF_GPIO_PPDSDR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100026])) -#define MCF_GPIO_PPDSDR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100028])) -#define MCF_GPIO_PPDSDR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100029])) -#define MCF_GPIO_PPDSDR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10002A])) -#define MCF_GPIO_PPDSDR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10002B])) -#define MCF_GPIO_PPDSDR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10002C])) -#define MCF_GPIO_PCLRR_ADDR (*(vuint8 *)(void*)(&__IPSBAR[0x100030])) -#define MCF_GPIO_PCLRR_DATAH (*(vuint8 *)(void*)(&__IPSBAR[0x100031])) -#define MCF_GPIO_PCLRR_DATAL (*(vuint8 *)(void*)(&__IPSBAR[0x100032])) -#define MCF_GPIO_PCLRR_BUSCTL (*(vuint8 *)(void*)(&__IPSBAR[0x100033])) -#define MCF_GPIO_PCLRR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100034])) -#define MCF_GPIO_PCLRR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100035])) -#define MCF_GPIO_PCLRR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100036])) -#define MCF_GPIO_PCLRR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100037])) -#define MCF_GPIO_PCLRR_UARTH (*(vuint8 *)(void*)(&__IPSBAR[0x100038])) -#define MCF_GPIO_PCLRR_UARTL (*(vuint8 *)(void*)(&__IPSBAR[0x100039])) -#define MCF_GPIO_PCLRR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10003A])) -#define MCF_GPIO_PCLRR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x10003B])) -#define MCF_GPIO_PCLRR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10003C])) -#define MCF_GPIO_PAR_AD (*(vuint8 *)(void*)(&__IPSBAR[0x100040])) -#define MCF_GPIO_PAR_BUSCTL (*(vuint16*)(void*)(&__IPSBAR[0x100042])) -#define MCF_GPIO_PAR_BS (*(vuint8 *)(void*)(&__IPSBAR[0x100044])) -#define MCF_GPIO_PAR_CS (*(vuint8 *)(void*)(&__IPSBAR[0x100045])) -#define MCF_GPIO_PAR_SDRAM (*(vuint8 *)(void*)(&__IPSBAR[0x100046])) -#define MCF_GPIO_PAR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100047])) -#define MCF_GPIO_PAR_UART (*(vuint16*)(void*)(&__IPSBAR[0x100048])) -#define MCF_GPIO_PAR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x10004A])) -#define MCF_GPIO_PAR_TIMER (*(vuint16*)(void*)(&__IPSBAR[0x10004C])) -#define MCF_GPIO_PAR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x10004E])) -#define MCF_GPIO_DSCR_EIM (*(vuint8 *)(void*)(&__IPSBAR[0x100050])) -#define MCF_GPIO_DSCR_ETPU (*(vuint8 *)(void*)(&__IPSBAR[0x100051])) -#define MCF_GPIO_DSCR_FECI2C (*(vuint8 *)(void*)(&__IPSBAR[0x100052])) -#define MCF_GPIO_DSCR_UART (*(vuint8 *)(void*)(&__IPSBAR[0x100053])) -#define MCF_GPIO_DSCR_QSPI (*(vuint8 *)(void*)(&__IPSBAR[0x100054])) -#define MCF_GPIO_DSCR_TIMER (*(vuint8 *)(void*)(&__IPSBAR[0x100055])) - -/* Bit definitions and macros for MCF_GPIO_PODR_ADDR */ -#define MCF_GPIO_PODR_ADDR_PODR_ADDR5 (0x20) -#define MCF_GPIO_PODR_ADDR_PODR_ADDR6 (0x40) -#define MCF_GPIO_PODR_ADDR_PODR_ADDR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_DATAH */ -#define MCF_GPIO_PODR_DATAH_PODR_DATAH0 (0x01) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH1 (0x02) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH2 (0x04) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH3 (0x08) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH4 (0x10) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH5 (0x20) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH6 (0x40) -#define MCF_GPIO_PODR_DATAH_PODR_DATAH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_DATAL */ -#define MCF_GPIO_PODR_DATAL_PODR_DATAL0 (0x01) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL1 (0x02) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL2 (0x04) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL3 (0x08) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL4 (0x10) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL5 (0x20) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL6 (0x40) -#define MCF_GPIO_PODR_DATAL_PODR_DATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */ -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL0 (0x01) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL4 (0x10) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL5 (0x20) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL6 (0x40) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_BS */ -#define MCF_GPIO_PODR_BS_PODR_BS0 (0x01) -#define MCF_GPIO_PODR_BS_PODR_BS1 (0x02) -#define MCF_GPIO_PODR_BS_PODR_BS2 (0x04) -#define MCF_GPIO_PODR_BS_PODR_BS3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_CS */ -#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02) -#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04) -#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08) -#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10) -#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20) -#define MCF_GPIO_PODR_CS_PODR_CS6 (0x40) -#define MCF_GPIO_PODR_CS_PODR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_SDRAM */ -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM0 (0x01) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM1 (0x02) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM2 (0x04) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM3 (0x08) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM4 (0x10) -#define MCF_GPIO_PODR_SDRAM_PODR_SDRAM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_UARTH */ -#define MCF_GPIO_PODR_UARTH_PODR_UARTH0 (0x01) -#define MCF_GPIO_PODR_UARTH_PODR_UARTH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PODR_UARTL */ -#define MCF_GPIO_PODR_UARTL_PODR_UARTL0 (0x01) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL1 (0x02) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL2 (0x04) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL3 (0x08) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL4 (0x10) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL5 (0x20) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL6 (0x40) -#define MCF_GPIO_PODR_UARTL_PODR_UARTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */ -#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */ -#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER4 (0x10) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER5 (0x20) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER6 (0x40) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_ETPU */ -#define MCF_GPIO_PODR_ETPU_PODR_ETPU0 (0x01) -#define MCF_GPIO_PODR_ETPU_PODR_ETPU1 (0x02) -#define MCF_GPIO_PODR_ETPU_PODR_ETPU2 (0x04) - -/* Bit definitions and macros for MCF_GPIO_PDDR_APDDR */ -#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR5 (0x20) -#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR6 (0x40) -#define MCF_GPIO_PDDR_APDDR_PDDR_APDDR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_DATAH */ -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH0 (0x01) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH1 (0x02) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH2 (0x04) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH3 (0x08) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH4 (0x10) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH5 (0x20) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH6 (0x40) -#define MCF_GPIO_PDDR_DATAH_PDDR_DATAH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_DATAL */ -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL0 (0x01) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL1 (0x02) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL2 (0x04) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL3 (0x08) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL4 (0x10) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL5 (0x20) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL6 (0x40) -#define MCF_GPIO_PDDR_DATAL_PDDR_DATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */ -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL0 (0x01) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL4 (0x10) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL5 (0x20) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL6 (0x40) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_BS */ -#define MCF_GPIO_PDDR_BS_PDDR_BS0 (0x01) -#define MCF_GPIO_PDDR_BS_PDDR_BS3(x) (((x)&0x07)<<1) - -/* Bit definitions and macros for MCF_GPIO_PDDR_CS */ -#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02) -#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04) -#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08) -#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10) -#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20) -#define MCF_GPIO_PDDR_CS_PDDR_CS6 (0x40) -#define MCF_GPIO_PDDR_CS_PDDR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_SDRAM */ -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM0 (0x01) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM1 (0x02) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM2 (0x04) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM3 (0x08) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM4 (0x10) -#define MCF_GPIO_PDDR_SDRAM_PDDR_SDRAM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_UARTH */ -#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH0 (0x01) -#define MCF_GPIO_PDDR_UARTH_PDDR_UARTH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PDDR_UARTL */ -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL0 (0x01) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL1 (0x02) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL2 (0x04) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL3 (0x08) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL4 (0x10) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL5 (0x20) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL6 (0x40) -#define MCF_GPIO_PDDR_UARTL_PDDR_UARTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */ -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */ -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER4 (0x10) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER5 (0x20) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER6 (0x40) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_ETPU */ -#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU0 (0x01) -#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU1 (0x02) -#define MCF_GPIO_PDDR_ETPU_PDDR_ETPU2 (0x04) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_ADDR */ -#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR5 (0x20) -#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR6 (0x40) -#define MCF_GPIO_PPDSDR_ADDR_PPDSDR_ADDR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAH */ -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH0 (0x01) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH1 (0x02) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH2 (0x04) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH3 (0x08) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH4 (0x10) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH5 (0x20) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH6 (0x40) -#define MCF_GPIO_PPDSDR_DATAH_PPDSDR_DATAH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_DATAL */ -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL0 (0x01) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL1 (0x02) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL2 (0x04) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL3 (0x08) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL4 (0x10) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL5 (0x20) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL6 (0x40) -#define MCF_GPIO_PPDSDR_DATAL_PPDSDR_DATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */ -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL0 (0x01) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL4 (0x10) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL5 (0x20) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL6 (0x40) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_BS */ -#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS0 (0x01) -#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS1 (0x02) -#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS2 (0x04) -#define MCF_GPIO_PPDSDR_BS_PPDSDR_BS3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */ -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS6 (0x40) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_SDRAM */ -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM0 (0x01) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM1 (0x02) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM2 (0x04) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM3 (0x08) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM4 (0x10) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM5 (0x20) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM6 (0x40) -#define MCF_GPIO_PPDSDR_SDRAM_PPDSDR_SDRAM7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTH */ -#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH0 (0x01) -#define MCF_GPIO_PPDSDR_UARTH_PPDSDR_UARTH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_UARTL */ -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL0 (0x01) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL1 (0x02) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL2 (0x04) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL3 (0x08) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL4 (0x10) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL5 (0x20) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL6 (0x40) -#define MCF_GPIO_PPDSDR_UARTL_PPDSDR_UARTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */ -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */ -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER4 (0x10) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER5 (0x20) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER6 (0x40) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_ETPU */ -#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU0 (0x01) -#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU1 (0x02) -#define MCF_GPIO_PPDSDR_ETPU_PPDSDR_ETPU2 (0x04) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_ADDR */ -#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR5 (0x20) -#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR6 (0x40) -#define MCF_GPIO_PCLRR_ADDR_PCLRR_ADDR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAH */ -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH0 (0x01) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH1 (0x02) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH2 (0x04) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH3 (0x08) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH4 (0x10) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH5 (0x20) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH6 (0x40) -#define MCF_GPIO_PCLRR_DATAH_PCLRR_DATAH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_DATAL */ -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL0 (0x01) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL1 (0x02) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL2 (0x04) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL3 (0x08) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL4 (0x10) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL5 (0x20) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL6 (0x40) -#define MCF_GPIO_PCLRR_DATAL_PCLRR_DATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */ -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL0 (0x01) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL4 (0x10) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL5 (0x20) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL6 (0x40) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_BS */ -#define MCF_GPIO_PCLRR_BS_PCLRR_BS0 (0x01) -#define MCF_GPIO_PCLRR_BS_PCLRR_BS1 (0x02) -#define MCF_GPIO_PCLRR_BS_PCLRR_BS2 (0x04) -#define MCF_GPIO_PCLRR_BS_PCLRR_BS3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */ -#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS6 (0x40) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_SDRAM */ -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM0 (0x01) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM1 (0x02) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM2 (0x04) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM3 (0x08) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM4 (0x10) -#define MCF_GPIO_PCLRR_SDRAM_PCLRR_SDRAM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTH */ -#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH0 (0x01) -#define MCF_GPIO_PCLRR_UARTH_PCLRR_UARTH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_UARTL */ -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL0 (0x01) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL1 (0x02) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL2 (0x04) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL3 (0x08) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL4 (0x10) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL5 (0x20) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL6 (0x40) -#define MCF_GPIO_PCLRR_UARTL_PCLRR_UARTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */ -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */ -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER4 (0x10) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER5 (0x20) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER6 (0x40) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_ETPU */ -#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU0 (0x01) -#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU1 (0x02) -#define MCF_GPIO_PCLRR_ETPU_PCLRR_ETPU2 (0x04) - -/* Bit definitions and macros for MCF_GPIO_PAR_AD */ -#define MCF_GPIO_PAR_AD_PAR_DATAL (0x01) -#define MCF_GPIO_PAR_AD_PAR_ADDR21 (0x20) -#define MCF_GPIO_PAR_AD_PAR_ADDR22 (0x40) -#define MCF_GPIO_PAR_AD_PAR_ADDR23 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */ -#define MCF_GPIO_PAR_BUSCTL_PAR_TIP(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 (0x0010) -#define MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 (0x0040) -#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x0100) -#define MCF_GPIO_PAR_BUSCTL_PAR_TEA(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x1000) -#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x4000) -#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_GPIO (0x0000) -#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_DMA (0x0800) -#define MCF_GPIO_PAR_BUSCTL_PAR_TEA_TEA (0x0C00) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x0000) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DMA (0x0080) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x00C0) -#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_GPIO (0x0000) -#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_DMA (0x0002) -#define MCF_GPIO_PAR_BUSCTL_PAR_TIP_TEA (0x0003) - -/* Bit definitions and macros for MCF_GPIO_PAR_BS */ -#define MCF_GPIO_PAR_BS_PAR_BS0 (0x01) -#define MCF_GPIO_PAR_BS_PAR_BS1 (0x02) -#define MCF_GPIO_PAR_BS_PAR_BS2 (0x04) -#define MCF_GPIO_PAR_BS_PAR_BS3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PAR_CS */ -#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02) -#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04) -#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08) -#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10) -#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20) -#define MCF_GPIO_PAR_CS_PAR_CS6 (0x40) -#define MCF_GPIO_PAR_CS_PAR_CS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PAR_SDRAM */ -#define MCF_GPIO_PAR_SDRAM_PAR_SDCS0 (0x01) -#define MCF_GPIO_PAR_SDRAM_PAR_SDCS1 (0x02) -#define MCF_GPIO_PAR_SDRAM_PAR_SCKE (0x04) -#define MCF_GPIO_PAR_SDRAM_PAR_SRAS (0x08) -#define MCF_GPIO_PAR_SDRAM_PAR_SCAS (0x10) -#define MCF_GPIO_PAR_SDRAM_PAR_SDWE (0x20) -#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) - -/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */ -#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_UART2 (0x40) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_I2C (0x80) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC (0xC0) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_UART2 (0x10) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_I2C (0x20) -#define MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC (0x30) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_FLEX (0x08) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_I2C (0x0C) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_FLEX (0x02) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_I2C (0x03) - -/* Bit definitions and macros for MCF_GPIO_PAR_UART */ -#define MCF_GPIO_PAR_UART_PAR_U0RTS (0x0001) -#define MCF_GPIO_PAR_UART_PAR_U0CTS (0x0002) -#define MCF_GPIO_PAR_UART_PAR_U0TXD (0x0004) -#define MCF_GPIO_PAR_UART_PAR_U0RXD (0x0008) -#define MCF_GPIO_PAR_UART_PAR_U1RTS(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_UART_PAR_U1CTS(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_UART_PAR_U1TXD(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_UART_PAR_U1RXD(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_UART_PAR_U2TXD (0x1000) -#define MCF_GPIO_PAR_UART_PAR_U2RXD (0x2000) -#define MCF_GPIO_PAR_UART_PAR_CAN1EN (0x4000) -#define MCF_GPIO_PAR_UART_PAR_DREQ2 (0x8000) -#define MCF_GPIO_PAR_UART_PAR_U1RXD_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_U1RXD_FLEX (0x0800) -#define MCF_GPIO_PAR_UART_PAR_U1RXD_UART1 (0x0C00) -#define MCF_GPIO_PAR_UART_PAR_U1TXD_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_U1TXD_FLEX (0x0200) -#define MCF_GPIO_PAR_UART_PAR_U1TXD_UART1 (0x0300) -#define MCF_GPIO_PAR_UART_PAR_U1CTS_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART2 (0x0080) -#define MCF_GPIO_PAR_UART_PAR_U1CTS_UART1 (0x00C0) -#define MCF_GPIO_PAR_UART_PAR_U1RTS_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART2 (0x0020) -#define MCF_GPIO_PAR_UART_PAR_U1RTS_UART1 (0x0030) - -/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */ -#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_QSPI_PAR_DOUT (0x04) -#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x03)<<3) -#define MCF_GPIO_PAR_QSPI_PAR_PCS0 (0x20) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1_GPIO (0x00) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1_SDRAMC (0x80) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1_QSPI (0xC0) -#define MCF_GPIO_PAR_QSPI_PAR_DIN_GPIO (0x00) -#define MCF_GPIO_PAR_QSPI_PAR_DIN_I2C (0x10) -#define MCF_GPIO_PAR_QSPI_PAR_DIN_QSPI (0x1C) -#define MCF_GPIO_PAR_QSPI_PAR_SCK_GPIO (0x00) -#define MCF_GPIO_PAR_QSPI_PAR_SCK_I2C (0x02) -#define MCF_GPIO_PAR_QSPI_PAR_SCK_QSPI (0x03) - -/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ -#define MCF_GPIO_PAR_TIMER_PAR_T0OUT(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_TIMER_PAR_T1OUT(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PAR_TIMER_PAR_T2OUT(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_TIMER_PAR_T0IN(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN(x) (((x)&0x0003)<<12) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN(x) (((x)&0x0003)<<14) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN_QSPI (0x4000) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN_UART2 (0x8000) -#define MCF_GPIO_PAR_TIMER_PAR_T3IN_T3IN (0xC000) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2OUT (0x1000) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN_DMA (0x2000) -#define MCF_GPIO_PAR_TIMER_PAR_T2IN_T2IN (0x3000) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1OUT (0x0400) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN_DMA (0x0800) -#define MCF_GPIO_PAR_TIMER_PAR_T1IN_T1IN (0x0C00) -#define MCF_GPIO_PAR_TIMER_PAR_T0IN_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T0IN_DMA (0x0200) -#define MCF_GPIO_PAR_TIMER_PAR_T0IN_T0IN (0x0300) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_QSPI (0x0040) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_UART2 (0x0080) -#define MCF_GPIO_PAR_TIMER_PAR_T3OUT_T3OUT (0x00C0) -#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_DMA (0x0020) -#define MCF_GPIO_PAR_TIMER_PAR_T2OUT_T2OUT (0x0030) -#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_DMA (0x0008) -#define MCF_GPIO_PAR_TIMER_PAR_T1OUT_T1OUT (0x000C) -#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_GPIO (0x0000) -#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_DMA (0x0002) -#define MCF_GPIO_PAR_TIMER_PAR_T0OUT_T0OUT (0x0003) - -/* Bit definitions and macros for MCF_GPIO_PAR_ETPU */ -#define MCF_GPIO_PAR_ETPU_PAR_LTPU_ODIS (0x01) -#define MCF_GPIO_PAR_ETPU_PAR_UTPU_ODIS (0x02) -#define MCF_GPIO_PAR_ETPU_PAR_TCRCLK (0x04) - -/* Bit definitions and macros for MCF_GPIO_DSCR_EIM */ -#define MCF_GPIO_DSCR_EIM_DSCR_EIM0 (0x01) -#define MCF_GPIO_DSCR_EIM_DSCR_EIM1 (0x10) - -/* Bit definitions and macros for MCF_GPIO_DSCR_ETPU */ -#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_7_0 (0x01) -#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_15_8 (0x04) -#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_23_16 (0x10) -#define MCF_GPIO_DSCR_ETPU_DSCR_ETPU_31_24 (0x40) - -/* Bit definitions and macros for MCF_GPIO_DSCR_FECI2C */ -#define MCF_GPIO_DSCR_FECI2C_DSCR_I2C (0x01) -#define MCF_GPIO_DSCR_FECI2C_DSCR_FEC (0x10) - -/* Bit definitions and macros for MCF_GPIO_DSCR_UART */ -#define MCF_GPIO_DSCR_UART_DSCR_UART0 (0x01) -#define MCF_GPIO_DSCR_UART_DSCR_UART1 (0x04) -#define MCF_GPIO_DSCR_UART_DSCR_UART2 (0x10) -#define MCF_GPIO_DSCR_UART_DSCR_IRQ (0x40) - -/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */ -#define MCF_GPIO_DSCR_QSPI_DSCR_QSPI (0x01) - -/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */ -#define MCF_GPIO_DSCR_TIMER_DSCR_TIMER (0x01) - -/********************************************************************/ - -#endif /* __MCF523X_GPIO_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_i2c.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_i2c.h deleted file mode 100644 index 947ea1f79..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_i2c.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * File: mcf523x_i2c.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_I2C_H__ -#define __MCF523X_I2C_H__ - -/********************************************************************* -* -* I2C Module (I2C) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_I2C_I2AR (*(vuint8 *)(void*)(&__IPSBAR[0x000300])) -#define MCF_I2C_I2FDR (*(vuint8 *)(void*)(&__IPSBAR[0x000304])) -#define MCF_I2C_I2CR (*(vuint8 *)(void*)(&__IPSBAR[0x000308])) -#define MCF_I2C_I2SR (*(vuint8 *)(void*)(&__IPSBAR[0x00030C])) -#define MCF_I2C_I2DR (*(vuint8 *)(void*)(&__IPSBAR[0x000310])) -#define MCF_I2C_I2ICR (*(vuint8 *)(void*)(&__IPSBAR[0x000320])) - -/* Bit definitions and macros for MCF_I2C_I2AR */ -#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_I2C_I2FDR */ -#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) - -/* Bit definitions and macros for MCF_I2C_I2CR */ -#define MCF_I2C_I2CR_RSTA (0x04) -#define MCF_I2C_I2CR_TXAK (0x08) -#define MCF_I2C_I2CR_MTX (0x10) -#define MCF_I2C_I2CR_MSTA (0x20) -#define MCF_I2C_I2CR_IIEN (0x40) -#define MCF_I2C_I2CR_IEN (0x80) - -/* Bit definitions and macros for MCF_I2C_I2SR */ -#define MCF_I2C_I2SR_RXAK (0x01) -#define MCF_I2C_I2SR_IIF (0x02) -#define MCF_I2C_I2SR_SRW (0x04) -#define MCF_I2C_I2SR_IAL (0x10) -#define MCF_I2C_I2SR_IBB (0x20) -#define MCF_I2C_I2SR_IAAS (0x40) -#define MCF_I2C_I2SR_ICF (0x80) - -/* Bit definitions and macros for MCF_I2C_I2ICR */ -#define MCF_I2C_I2ICR_IE (0x01) -#define MCF_I2C_I2ICR_RE (0x02) -#define MCF_I2C_I2ICR_TE (0x04) -#define MCF_I2C_I2ICR_BNBE (0x08) - -/********************************************************************/ - -#endif /* __MCF523X_I2C_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_intc0.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_intc0.h deleted file mode 100644 index 21a1d77c2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_intc0.h +++ /dev/null @@ -1,317 +0,0 @@ -/* - * File: mcf523x_intc0.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_INTC0_H__ -#define __MCF523X_INTC0_H__ - -/********************************************************************* -* -* Interrupt Controller 0 (INTC0) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_INTC0_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000C00])) -#define MCF_INTC0_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000C04])) -#define MCF_INTC0_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000C08])) -#define MCF_INTC0_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000C0C])) -#define MCF_INTC0_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000C10])) -#define MCF_INTC0_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000C14])) -#define MCF_INTC0_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000C18])) -#define MCF_INTC0_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000C19])) -#define MCF_INTC0_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000C40])) -#define MCF_INTC0_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000C41])) -#define MCF_INTC0_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000C42])) -#define MCF_INTC0_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000C43])) -#define MCF_INTC0_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000C44])) -#define MCF_INTC0_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000C45])) -#define MCF_INTC0_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000C46])) -#define MCF_INTC0_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000C47])) -#define MCF_INTC0_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000C48])) -#define MCF_INTC0_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000C49])) -#define MCF_INTC0_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4A])) -#define MCF_INTC0_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4B])) -#define MCF_INTC0_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4C])) -#define MCF_INTC0_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4D])) -#define MCF_INTC0_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4E])) -#define MCF_INTC0_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000C4F])) -#define MCF_INTC0_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000C50])) -#define MCF_INTC0_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000C51])) -#define MCF_INTC0_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000C52])) -#define MCF_INTC0_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000C53])) -#define MCF_INTC0_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000C54])) -#define MCF_INTC0_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000C55])) -#define MCF_INTC0_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000C56])) -#define MCF_INTC0_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000C57])) -#define MCF_INTC0_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000C58])) -#define MCF_INTC0_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000C59])) -#define MCF_INTC0_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5A])) -#define MCF_INTC0_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5B])) -#define MCF_INTC0_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5C])) -#define MCF_INTC0_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5D])) -#define MCF_INTC0_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5E])) -#define MCF_INTC0_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000C5F])) -#define MCF_INTC0_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000C60])) -#define MCF_INTC0_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000C61])) -#define MCF_INTC0_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000C62])) -#define MCF_INTC0_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000C63])) -#define MCF_INTC0_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000C64])) -#define MCF_INTC0_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000C65])) -#define MCF_INTC0_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000C66])) -#define MCF_INTC0_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000C67])) -#define MCF_INTC0_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000C68])) -#define MCF_INTC0_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000C69])) -#define MCF_INTC0_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6A])) -#define MCF_INTC0_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6B])) -#define MCF_INTC0_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6C])) -#define MCF_INTC0_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6D])) -#define MCF_INTC0_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6E])) -#define MCF_INTC0_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000C6F])) -#define MCF_INTC0_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000C70])) -#define MCF_INTC0_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000C71])) -#define MCF_INTC0_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000C72])) -#define MCF_INTC0_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000C73])) -#define MCF_INTC0_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000C74])) -#define MCF_INTC0_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000C75])) -#define MCF_INTC0_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000C76])) -#define MCF_INTC0_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000C77])) -#define MCF_INTC0_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000C78])) -#define MCF_INTC0_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000C79])) -#define MCF_INTC0_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7A])) -#define MCF_INTC0_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7B])) -#define MCF_INTC0_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7C])) -#define MCF_INTC0_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7D])) -#define MCF_INTC0_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7E])) -#define MCF_INTC0_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000C7F])) -#define MCF_INTC0_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000C40+((x)*0x001)])) -#define MCF_INTC0_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE0])) -#define MCF_INTC0_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4])) -#define MCF_INTC0_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CE8])) -#define MCF_INTC0_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CEC])) -#define MCF_INTC0_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF0])) -#define MCF_INTC0_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF4])) -#define MCF_INTC0_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CF8])) -#define MCF_INTC0_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000CFC])) -#define MCF_INTC0_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000CE4+((x)*0x004)])) - -/* Bit definitions and macros for MCF_INTC0_IPRH */ -#define MCF_INTC0_IPRH_INT32 (0x00000001) -#define MCF_INTC0_IPRH_INT33 (0x00000002) -#define MCF_INTC0_IPRH_INT34 (0x00000004) -#define MCF_INTC0_IPRH_INT35 (0x00000008) -#define MCF_INTC0_IPRH_INT36 (0x00000010) -#define MCF_INTC0_IPRH_INT37 (0x00000020) -#define MCF_INTC0_IPRH_INT38 (0x00000040) -#define MCF_INTC0_IPRH_INT39 (0x00000080) -#define MCF_INTC0_IPRH_INT40 (0x00000100) -#define MCF_INTC0_IPRH_INT41 (0x00000200) -#define MCF_INTC0_IPRH_INT42 (0x00000400) -#define MCF_INTC0_IPRH_INT43 (0x00000800) -#define MCF_INTC0_IPRH_INT44 (0x00001000) -#define MCF_INTC0_IPRH_INT45 (0x00002000) -#define MCF_INTC0_IPRH_INT46 (0x00004000) -#define MCF_INTC0_IPRH_INT47 (0x00008000) -#define MCF_INTC0_IPRH_INT48 (0x00010000) -#define MCF_INTC0_IPRH_INT49 (0x00020000) -#define MCF_INTC0_IPRH_INT50 (0x00040000) -#define MCF_INTC0_IPRH_INT51 (0x00080000) -#define MCF_INTC0_IPRH_INT52 (0x00100000) -#define MCF_INTC0_IPRH_INT53 (0x00200000) -#define MCF_INTC0_IPRH_INT54 (0x00400000) -#define MCF_INTC0_IPRH_INT55 (0x00800000) -#define MCF_INTC0_IPRH_INT56 (0x01000000) -#define MCF_INTC0_IPRH_INT57 (0x02000000) -#define MCF_INTC0_IPRH_INT58 (0x04000000) -#define MCF_INTC0_IPRH_INT59 (0x08000000) -#define MCF_INTC0_IPRH_INT60 (0x10000000) -#define MCF_INTC0_IPRH_INT61 (0x20000000) -#define MCF_INTC0_IPRH_INT62 (0x40000000) -#define MCF_INTC0_IPRH_INT63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_IPRL */ -#define MCF_INTC0_IPRL_INT1 (0x00000002) -#define MCF_INTC0_IPRL_INT2 (0x00000004) -#define MCF_INTC0_IPRL_INT3 (0x00000008) -#define MCF_INTC0_IPRL_INT4 (0x00000010) -#define MCF_INTC0_IPRL_INT5 (0x00000020) -#define MCF_INTC0_IPRL_INT6 (0x00000040) -#define MCF_INTC0_IPRL_INT7 (0x00000080) -#define MCF_INTC0_IPRL_INT8 (0x00000100) -#define MCF_INTC0_IPRL_INT9 (0x00000200) -#define MCF_INTC0_IPRL_INT10 (0x00000400) -#define MCF_INTC0_IPRL_INT11 (0x00000800) -#define MCF_INTC0_IPRL_INT12 (0x00001000) -#define MCF_INTC0_IPRL_INT13 (0x00002000) -#define MCF_INTC0_IPRL_INT14 (0x00004000) -#define MCF_INTC0_IPRL_INT15 (0x00008000) -#define MCF_INTC0_IPRL_INT16 (0x00010000) -#define MCF_INTC0_IPRL_INT17 (0x00020000) -#define MCF_INTC0_IPRL_INT18 (0x00040000) -#define MCF_INTC0_IPRL_INT19 (0x00080000) -#define MCF_INTC0_IPRL_INT20 (0x00100000) -#define MCF_INTC0_IPRL_INT21 (0x00200000) -#define MCF_INTC0_IPRL_INT22 (0x00400000) -#define MCF_INTC0_IPRL_INT23 (0x00800000) -#define MCF_INTC0_IPRL_INT24 (0x01000000) -#define MCF_INTC0_IPRL_INT25 (0x02000000) -#define MCF_INTC0_IPRL_INT26 (0x04000000) -#define MCF_INTC0_IPRL_INT27 (0x08000000) -#define MCF_INTC0_IPRL_INT28 (0x10000000) -#define MCF_INTC0_IPRL_INT29 (0x20000000) -#define MCF_INTC0_IPRL_INT30 (0x40000000) -#define MCF_INTC0_IPRL_INT31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_IMRH */ -#define MCF_INTC0_IMRH_INT_MASK32 (0x00000001) -#define MCF_INTC0_IMRH_INT_MASK33 (0x00000002) -#define MCF_INTC0_IMRH_INT_MASK34 (0x00000004) -#define MCF_INTC0_IMRH_INT_MASK35 (0x00000008) -#define MCF_INTC0_IMRH_INT_MASK36 (0x00000010) -#define MCF_INTC0_IMRH_INT_MASK37 (0x00000020) -#define MCF_INTC0_IMRH_INT_MASK38 (0x00000040) -#define MCF_INTC0_IMRH_INT_MASK39 (0x00000080) -#define MCF_INTC0_IMRH_INT_MASK40 (0x00000100) -#define MCF_INTC0_IMRH_INT_MASK41 (0x00000200) -#define MCF_INTC0_IMRH_INT_MASK42 (0x00000400) -#define MCF_INTC0_IMRH_INT_MASK43 (0x00000800) -#define MCF_INTC0_IMRH_INT_MASK44 (0x00001000) -#define MCF_INTC0_IMRH_INT_MASK45 (0x00002000) -#define MCF_INTC0_IMRH_INT_MASK46 (0x00004000) -#define MCF_INTC0_IMRH_INT_MASK47 (0x00008000) -#define MCF_INTC0_IMRH_INT_MASK48 (0x00010000) -#define MCF_INTC0_IMRH_INT_MASK49 (0x00020000) -#define MCF_INTC0_IMRH_INT_MASK50 (0x00040000) -#define MCF_INTC0_IMRH_INT_MASK51 (0x00080000) -#define MCF_INTC0_IMRH_INT_MASK52 (0x00100000) -#define MCF_INTC0_IMRH_INT_MASK53 (0x00200000) -#define MCF_INTC0_IMRH_INT_MASK54 (0x00400000) -#define MCF_INTC0_IMRH_INT_MASK55 (0x00800000) -#define MCF_INTC0_IMRH_INT_MASK56 (0x01000000) -#define MCF_INTC0_IMRH_INT_MASK57 (0x02000000) -#define MCF_INTC0_IMRH_INT_MASK58 (0x04000000) -#define MCF_INTC0_IMRH_INT_MASK59 (0x08000000) -#define MCF_INTC0_IMRH_INT_MASK60 (0x10000000) -#define MCF_INTC0_IMRH_INT_MASK61 (0x20000000) -#define MCF_INTC0_IMRH_INT_MASK62 (0x40000000) -#define MCF_INTC0_IMRH_INT_MASK63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_IMRL */ -#define MCF_INTC0_IMRL_MASKALL (0x00000001) -#define MCF_INTC0_IMRL_INT_MASK1 (0x00000002) -#define MCF_INTC0_IMRL_INT_MASK2 (0x00000004) -#define MCF_INTC0_IMRL_INT_MASK3 (0x00000008) -#define MCF_INTC0_IMRL_INT_MASK4 (0x00000010) -#define MCF_INTC0_IMRL_INT_MASK5 (0x00000020) -#define MCF_INTC0_IMRL_INT_MASK6 (0x00000040) -#define MCF_INTC0_IMRL_INT_MASK7 (0x00000080) -#define MCF_INTC0_IMRL_INT_MASK8 (0x00000100) -#define MCF_INTC0_IMRL_INT_MASK9 (0x00000200) -#define MCF_INTC0_IMRL_INT_MASK10 (0x00000400) -#define MCF_INTC0_IMRL_INT_MASK11 (0x00000800) -#define MCF_INTC0_IMRL_INT_MASK12 (0x00001000) -#define MCF_INTC0_IMRL_INT_MASK13 (0x00002000) -#define MCF_INTC0_IMRL_INT_MASK14 (0x00004000) -#define MCF_INTC0_IMRL_INT_MASK15 (0x00008000) -#define MCF_INTC0_IMRL_INT_MASK16 (0x00010000) -#define MCF_INTC0_IMRL_INT_MASK17 (0x00020000) -#define MCF_INTC0_IMRL_INT_MASK18 (0x00040000) -#define MCF_INTC0_IMRL_INT_MASK19 (0x00080000) -#define MCF_INTC0_IMRL_INT_MASK20 (0x00100000) -#define MCF_INTC0_IMRL_INT_MASK21 (0x00200000) -#define MCF_INTC0_IMRL_INT_MASK22 (0x00400000) -#define MCF_INTC0_IMRL_INT_MASK23 (0x00800000) -#define MCF_INTC0_IMRL_INT_MASK24 (0x01000000) -#define MCF_INTC0_IMRL_INT_MASK25 (0x02000000) -#define MCF_INTC0_IMRL_INT_MASK26 (0x04000000) -#define MCF_INTC0_IMRL_INT_MASK27 (0x08000000) -#define MCF_INTC0_IMRL_INT_MASK28 (0x10000000) -#define MCF_INTC0_IMRL_INT_MASK29 (0x20000000) -#define MCF_INTC0_IMRL_INT_MASK30 (0x40000000) -#define MCF_INTC0_IMRL_INT_MASK31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_INTFRCH */ -#define MCF_INTC0_INTFRCH_INTFRC32 (0x00000001) -#define MCF_INTC0_INTFRCH_INTFRC33 (0x00000002) -#define MCF_INTC0_INTFRCH_INTFRC34 (0x00000004) -#define MCF_INTC0_INTFRCH_INTFRC35 (0x00000008) -#define MCF_INTC0_INTFRCH_INTFRC36 (0x00000010) -#define MCF_INTC0_INTFRCH_INTFRC37 (0x00000020) -#define MCF_INTC0_INTFRCH_INTFRC38 (0x00000040) -#define MCF_INTC0_INTFRCH_INTFRC39 (0x00000080) -#define MCF_INTC0_INTFRCH_INTFRC40 (0x00000100) -#define MCF_INTC0_INTFRCH_INTFRC41 (0x00000200) -#define MCF_INTC0_INTFRCH_INTFRC42 (0x00000400) -#define MCF_INTC0_INTFRCH_INTFRC43 (0x00000800) -#define MCF_INTC0_INTFRCH_INTFRC44 (0x00001000) -#define MCF_INTC0_INTFRCH_INTFRC45 (0x00002000) -#define MCF_INTC0_INTFRCH_INTFRC46 (0x00004000) -#define MCF_INTC0_INTFRCH_INTFRC47 (0x00008000) -#define MCF_INTC0_INTFRCH_INTFRC48 (0x00010000) -#define MCF_INTC0_INTFRCH_INTFRC49 (0x00020000) -#define MCF_INTC0_INTFRCH_INTFRC50 (0x00040000) -#define MCF_INTC0_INTFRCH_INTFRC51 (0x00080000) -#define MCF_INTC0_INTFRCH_INTFRC52 (0x00100000) -#define MCF_INTC0_INTFRCH_INTFRC53 (0x00200000) -#define MCF_INTC0_INTFRCH_INTFRC54 (0x00400000) -#define MCF_INTC0_INTFRCH_INTFRC55 (0x00800000) -#define MCF_INTC0_INTFRCH_INTFRC56 (0x01000000) -#define MCF_INTC0_INTFRCH_INTFRC57 (0x02000000) -#define MCF_INTC0_INTFRCH_INTFRC58 (0x04000000) -#define MCF_INTC0_INTFRCH_INTFRC59 (0x08000000) -#define MCF_INTC0_INTFRCH_INTFRC60 (0x10000000) -#define MCF_INTC0_INTFRCH_INTFRC61 (0x20000000) -#define MCF_INTC0_INTFRCH_INTFRC62 (0x40000000) -#define MCF_INTC0_INTFRCH_INTFRC63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_INTFRCL */ -#define MCF_INTC0_INTFRCL_INTFRC1 (0x00000002) -#define MCF_INTC0_INTFRCL_INTFRC2 (0x00000004) -#define MCF_INTC0_INTFRCL_INTFRC3 (0x00000008) -#define MCF_INTC0_INTFRCL_INTFRC4 (0x00000010) -#define MCF_INTC0_INTFRCL_INTFRC5 (0x00000020) -#define MCF_INTC0_INTFRCL_INT6 (0x00000040) -#define MCF_INTC0_INTFRCL_INT7 (0x00000080) -#define MCF_INTC0_INTFRCL_INT8 (0x00000100) -#define MCF_INTC0_INTFRCL_INT9 (0x00000200) -#define MCF_INTC0_INTFRCL_INT10 (0x00000400) -#define MCF_INTC0_INTFRCL_INTFRC11 (0x00000800) -#define MCF_INTC0_INTFRCL_INTFRC12 (0x00001000) -#define MCF_INTC0_INTFRCL_INTFRC13 (0x00002000) -#define MCF_INTC0_INTFRCL_INTFRC14 (0x00004000) -#define MCF_INTC0_INTFRCL_INT15 (0x00008000) -#define MCF_INTC0_INTFRCL_INTFRC16 (0x00010000) -#define MCF_INTC0_INTFRCL_INTFRC17 (0x00020000) -#define MCF_INTC0_INTFRCL_INTFRC18 (0x00040000) -#define MCF_INTC0_INTFRCL_INTFRC19 (0x00080000) -#define MCF_INTC0_INTFRCL_INTFRC20 (0x00100000) -#define MCF_INTC0_INTFRCL_INTFRC21 (0x00200000) -#define MCF_INTC0_INTFRCL_INTFRC22 (0x00400000) -#define MCF_INTC0_INTFRCL_INTFRC23 (0x00800000) -#define MCF_INTC0_INTFRCL_INTFRC24 (0x01000000) -#define MCF_INTC0_INTFRCL_INTFRC25 (0x02000000) -#define MCF_INTC0_INTFRCL_INTFRC26 (0x04000000) -#define MCF_INTC0_INTFRCL_INTFRC27 (0x08000000) -#define MCF_INTC0_INTFRCL_INTFRC28 (0x10000000) -#define MCF_INTC0_INTFRCL_INTFRC29 (0x20000000) -#define MCF_INTC0_INTFRCL_INTFRC30 (0x40000000) -#define MCF_INTC0_INTFRCL_INTFRC31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC0_IRLR */ -#define MCF_INTC0_IRLR_IRQ(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_INTC0_IACKLPR */ -#define MCF_INTC0_IACKLPR_PRI(x) (((x)&0x0F)<<0) -#define MCF_INTC0_IACKLPR_LEVEL(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF_INTC0_ICRn */ -#define MCF_INTC0_ICRn_IP(x) (((x)&0x07)<<0) -#define MCF_INTC0_ICRn_IL(x) (((x)&0x07)<<3) - -/********************************************************************/ - -#endif /* __MCF523X_INTC0_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_intc1.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_intc1.h deleted file mode 100644 index 3a4925704..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_intc1.h +++ /dev/null @@ -1,317 +0,0 @@ -/* - * File: mcf523x_intc1.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_INTC1_H__ -#define __MCF523X_INTC1_H__ - -/********************************************************************* -* -* Interrupt Controller 1 (INTC1) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_INTC1_IPRH (*(vuint32*)(void*)(&__IPSBAR[0x000D00])) -#define MCF_INTC1_IPRL (*(vuint32*)(void*)(&__IPSBAR[0x000D04])) -#define MCF_INTC1_IMRH (*(vuint32*)(void*)(&__IPSBAR[0x000D08])) -#define MCF_INTC1_IMRL (*(vuint32*)(void*)(&__IPSBAR[0x000D0C])) -#define MCF_INTC1_INTFRCH (*(vuint32*)(void*)(&__IPSBAR[0x000D10])) -#define MCF_INTC1_INTFRCL (*(vuint32*)(void*)(&__IPSBAR[0x000D14])) -#define MCF_INTC1_IRLR (*(vuint8 *)(void*)(&__IPSBAR[0x000D18])) -#define MCF_INTC1_IACKLPR (*(vuint8 *)(void*)(&__IPSBAR[0x000D19])) -#define MCF_INTC1_ICR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000D40])) -#define MCF_INTC1_ICR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000D41])) -#define MCF_INTC1_ICR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000D42])) -#define MCF_INTC1_ICR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000D43])) -#define MCF_INTC1_ICR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000D44])) -#define MCF_INTC1_ICR5 (*(vuint8 *)(void*)(&__IPSBAR[0x000D45])) -#define MCF_INTC1_ICR6 (*(vuint8 *)(void*)(&__IPSBAR[0x000D46])) -#define MCF_INTC1_ICR7 (*(vuint8 *)(void*)(&__IPSBAR[0x000D47])) -#define MCF_INTC1_ICR8 (*(vuint8 *)(void*)(&__IPSBAR[0x000D48])) -#define MCF_INTC1_ICR9 (*(vuint8 *)(void*)(&__IPSBAR[0x000D49])) -#define MCF_INTC1_ICR10 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4A])) -#define MCF_INTC1_ICR11 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4B])) -#define MCF_INTC1_ICR12 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4C])) -#define MCF_INTC1_ICR13 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4D])) -#define MCF_INTC1_ICR14 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4E])) -#define MCF_INTC1_ICR15 (*(vuint8 *)(void*)(&__IPSBAR[0x000D4F])) -#define MCF_INTC1_ICR16 (*(vuint8 *)(void*)(&__IPSBAR[0x000D50])) -#define MCF_INTC1_ICR17 (*(vuint8 *)(void*)(&__IPSBAR[0x000D51])) -#define MCF_INTC1_ICR18 (*(vuint8 *)(void*)(&__IPSBAR[0x000D52])) -#define MCF_INTC1_ICR19 (*(vuint8 *)(void*)(&__IPSBAR[0x000D53])) -#define MCF_INTC1_ICR20 (*(vuint8 *)(void*)(&__IPSBAR[0x000D54])) -#define MCF_INTC1_ICR21 (*(vuint8 *)(void*)(&__IPSBAR[0x000D55])) -#define MCF_INTC1_ICR22 (*(vuint8 *)(void*)(&__IPSBAR[0x000D56])) -#define MCF_INTC1_ICR23 (*(vuint8 *)(void*)(&__IPSBAR[0x000D57])) -#define MCF_INTC1_ICR24 (*(vuint8 *)(void*)(&__IPSBAR[0x000D58])) -#define MCF_INTC1_ICR25 (*(vuint8 *)(void*)(&__IPSBAR[0x000D59])) -#define MCF_INTC1_ICR26 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5A])) -#define MCF_INTC1_ICR27 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5B])) -#define MCF_INTC1_ICR28 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5C])) -#define MCF_INTC1_ICR29 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5D])) -#define MCF_INTC1_ICR30 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5E])) -#define MCF_INTC1_ICR31 (*(vuint8 *)(void*)(&__IPSBAR[0x000D5F])) -#define MCF_INTC1_ICR32 (*(vuint8 *)(void*)(&__IPSBAR[0x000D60])) -#define MCF_INTC1_ICR33 (*(vuint8 *)(void*)(&__IPSBAR[0x000D61])) -#define MCF_INTC1_ICR34 (*(vuint8 *)(void*)(&__IPSBAR[0x000D62])) -#define MCF_INTC1_ICR35 (*(vuint8 *)(void*)(&__IPSBAR[0x000D63])) -#define MCF_INTC1_ICR36 (*(vuint8 *)(void*)(&__IPSBAR[0x000D64])) -#define MCF_INTC1_ICR37 (*(vuint8 *)(void*)(&__IPSBAR[0x000D65])) -#define MCF_INTC1_ICR38 (*(vuint8 *)(void*)(&__IPSBAR[0x000D66])) -#define MCF_INTC1_ICR39 (*(vuint8 *)(void*)(&__IPSBAR[0x000D67])) -#define MCF_INTC1_ICR40 (*(vuint8 *)(void*)(&__IPSBAR[0x000D68])) -#define MCF_INTC1_ICR41 (*(vuint8 *)(void*)(&__IPSBAR[0x000D69])) -#define MCF_INTC1_ICR42 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6A])) -#define MCF_INTC1_ICR43 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6B])) -#define MCF_INTC1_ICR44 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6C])) -#define MCF_INTC1_ICR45 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6D])) -#define MCF_INTC1_ICR46 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6E])) -#define MCF_INTC1_ICR47 (*(vuint8 *)(void*)(&__IPSBAR[0x000D6F])) -#define MCF_INTC1_ICR48 (*(vuint8 *)(void*)(&__IPSBAR[0x000D70])) -#define MCF_INTC1_ICR49 (*(vuint8 *)(void*)(&__IPSBAR[0x000D71])) -#define MCF_INTC1_ICR50 (*(vuint8 *)(void*)(&__IPSBAR[0x000D72])) -#define MCF_INTC1_ICR51 (*(vuint8 *)(void*)(&__IPSBAR[0x000D73])) -#define MCF_INTC1_ICR52 (*(vuint8 *)(void*)(&__IPSBAR[0x000D74])) -#define MCF_INTC1_ICR53 (*(vuint8 *)(void*)(&__IPSBAR[0x000D75])) -#define MCF_INTC1_ICR54 (*(vuint8 *)(void*)(&__IPSBAR[0x000D76])) -#define MCF_INTC1_ICR55 (*(vuint8 *)(void*)(&__IPSBAR[0x000D77])) -#define MCF_INTC1_ICR56 (*(vuint8 *)(void*)(&__IPSBAR[0x000D78])) -#define MCF_INTC1_ICR57 (*(vuint8 *)(void*)(&__IPSBAR[0x000D79])) -#define MCF_INTC1_ICR58 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7A])) -#define MCF_INTC1_ICR59 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7B])) -#define MCF_INTC1_ICR60 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7C])) -#define MCF_INTC1_ICR61 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7D])) -#define MCF_INTC1_ICR62 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7E])) -#define MCF_INTC1_ICR63 (*(vuint8 *)(void*)(&__IPSBAR[0x000D7F])) -#define MCF_INTC1_ICRn(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000D40+((x)*0x001)])) -#define MCF_INTC1_SWIACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE0])) -#define MCF_INTC1_L1IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4])) -#define MCF_INTC1_L2IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DE8])) -#define MCF_INTC1_L3IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DEC])) -#define MCF_INTC1_L4IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF0])) -#define MCF_INTC1_L5IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF4])) -#define MCF_INTC1_L6IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DF8])) -#define MCF_INTC1_L7IACK (*(vuint8 *)(void*)(&__IPSBAR[0x000DFC])) -#define MCF_INTC1_LnIACK(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4+((x)*0x004)])) - -/* Bit definitions and macros for MCF_INTC1_IPRH */ -#define MCF_INTC1_IPRH_INT32 (0x00000001) -#define MCF_INTC1_IPRH_INT33 (0x00000002) -#define MCF_INTC1_IPRH_INT34 (0x00000004) -#define MCF_INTC1_IPRH_INT35 (0x00000008) -#define MCF_INTC1_IPRH_INT36 (0x00000010) -#define MCF_INTC1_IPRH_INT37 (0x00000020) -#define MCF_INTC1_IPRH_INT38 (0x00000040) -#define MCF_INTC1_IPRH_INT39 (0x00000080) -#define MCF_INTC1_IPRH_INT40 (0x00000100) -#define MCF_INTC1_IPRH_INT41 (0x00000200) -#define MCF_INTC1_IPRH_INT42 (0x00000400) -#define MCF_INTC1_IPRH_INT43 (0x00000800) -#define MCF_INTC1_IPRH_INT44 (0x00001000) -#define MCF_INTC1_IPRH_INT45 (0x00002000) -#define MCF_INTC1_IPRH_INT46 (0x00004000) -#define MCF_INTC1_IPRH_INT47 (0x00008000) -#define MCF_INTC1_IPRH_INT48 (0x00010000) -#define MCF_INTC1_IPRH_INT49 (0x00020000) -#define MCF_INTC1_IPRH_INT50 (0x00040000) -#define MCF_INTC1_IPRH_INT51 (0x00080000) -#define MCF_INTC1_IPRH_INT52 (0x00100000) -#define MCF_INTC1_IPRH_INT53 (0x00200000) -#define MCF_INTC1_IPRH_INT54 (0x00400000) -#define MCF_INTC1_IPRH_INT55 (0x00800000) -#define MCF_INTC1_IPRH_INT56 (0x01000000) -#define MCF_INTC1_IPRH_INT57 (0x02000000) -#define MCF_INTC1_IPRH_INT58 (0x04000000) -#define MCF_INTC1_IPRH_INT59 (0x08000000) -#define MCF_INTC1_IPRH_INT60 (0x10000000) -#define MCF_INTC1_IPRH_INT61 (0x20000000) -#define MCF_INTC1_IPRH_INT62 (0x40000000) -#define MCF_INTC1_IPRH_INT63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_IPRL */ -#define MCF_INTC1_IPRL_INT1 (0x00000002) -#define MCF_INTC1_IPRL_INT2 (0x00000004) -#define MCF_INTC1_IPRL_INT3 (0x00000008) -#define MCF_INTC1_IPRL_INT4 (0x00000010) -#define MCF_INTC1_IPRL_INT5 (0x00000020) -#define MCF_INTC1_IPRL_INT6 (0x00000040) -#define MCF_INTC1_IPRL_INT7 (0x00000080) -#define MCF_INTC1_IPRL_INT8 (0x00000100) -#define MCF_INTC1_IPRL_INT9 (0x00000200) -#define MCF_INTC1_IPRL_INT10 (0x00000400) -#define MCF_INTC1_IPRL_INT11 (0x00000800) -#define MCF_INTC1_IPRL_INT12 (0x00001000) -#define MCF_INTC1_IPRL_INT13 (0x00002000) -#define MCF_INTC1_IPRL_INT14 (0x00004000) -#define MCF_INTC1_IPRL_INT15 (0x00008000) -#define MCF_INTC1_IPRL_INT16 (0x00010000) -#define MCF_INTC1_IPRL_INT17 (0x00020000) -#define MCF_INTC1_IPRL_INT18 (0x00040000) -#define MCF_INTC1_IPRL_INT19 (0x00080000) -#define MCF_INTC1_IPRL_INT20 (0x00100000) -#define MCF_INTC1_IPRL_INT21 (0x00200000) -#define MCF_INTC1_IPRL_INT22 (0x00400000) -#define MCF_INTC1_IPRL_INT23 (0x00800000) -#define MCF_INTC1_IPRL_INT24 (0x01000000) -#define MCF_INTC1_IPRL_INT25 (0x02000000) -#define MCF_INTC1_IPRL_INT26 (0x04000000) -#define MCF_INTC1_IPRL_INT27 (0x08000000) -#define MCF_INTC1_IPRL_INT28 (0x10000000) -#define MCF_INTC1_IPRL_INT29 (0x20000000) -#define MCF_INTC1_IPRL_INT30 (0x40000000) -#define MCF_INTC1_IPRL_INT31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_IMRH */ -#define MCF_INTC1_IMRH_INT_MASK32 (0x00000001) -#define MCF_INTC1_IMRH_INT_MASK33 (0x00000002) -#define MCF_INTC1_IMRH_INT_MASK34 (0x00000004) -#define MCF_INTC1_IMRH_INT_MASK35 (0x00000008) -#define MCF_INTC1_IMRH_INT_MASK36 (0x00000010) -#define MCF_INTC1_IMRH_INT_MASK37 (0x00000020) -#define MCF_INTC1_IMRH_INT_MASK38 (0x00000040) -#define MCF_INTC1_IMRH_INT_MASK39 (0x00000080) -#define MCF_INTC1_IMRH_INT_MASK40 (0x00000100) -#define MCF_INTC1_IMRH_INT_MASK41 (0x00000200) -#define MCF_INTC1_IMRH_INT_MASK42 (0x00000400) -#define MCF_INTC1_IMRH_INT_MASK43 (0x00000800) -#define MCF_INTC1_IMRH_INT_MASK44 (0x00001000) -#define MCF_INTC1_IMRH_INT_MASK45 (0x00002000) -#define MCF_INTC1_IMRH_INT_MASK46 (0x00004000) -#define MCF_INTC1_IMRH_INT_MASK47 (0x00008000) -#define MCF_INTC1_IMRH_INT_MASK48 (0x00010000) -#define MCF_INTC1_IMRH_INT_MASK49 (0x00020000) -#define MCF_INTC1_IMRH_INT_MASK50 (0x00040000) -#define MCF_INTC1_IMRH_INT_MASK51 (0x00080000) -#define MCF_INTC1_IMRH_INT_MASK52 (0x00100000) -#define MCF_INTC1_IMRH_INT_MASK53 (0x00200000) -#define MCF_INTC1_IMRH_INT_MASK54 (0x00400000) -#define MCF_INTC1_IMRH_INT_MASK55 (0x00800000) -#define MCF_INTC1_IMRH_INT_MASK56 (0x01000000) -#define MCF_INTC1_IMRH_INT_MASK57 (0x02000000) -#define MCF_INTC1_IMRH_INT_MASK58 (0x04000000) -#define MCF_INTC1_IMRH_INT_MASK59 (0x08000000) -#define MCF_INTC1_IMRH_INT_MASK60 (0x10000000) -#define MCF_INTC1_IMRH_INT_MASK61 (0x20000000) -#define MCF_INTC1_IMRH_INT_MASK62 (0x40000000) -#define MCF_INTC1_IMRH_INT_MASK63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_IMRL */ -#define MCF_INTC1_IMRL_MASKALL (0x00000001) -#define MCF_INTC1_IMRL_INT_MASK1 (0x00000002) -#define MCF_INTC1_IMRL_INT_MASK2 (0x00000004) -#define MCF_INTC1_IMRL_INT_MASK3 (0x00000008) -#define MCF_INTC1_IMRL_INT_MASK4 (0x00000010) -#define MCF_INTC1_IMRL_INT_MASK5 (0x00000020) -#define MCF_INTC1_IMRL_INT_MASK6 (0x00000040) -#define MCF_INTC1_IMRL_INT_MASK7 (0x00000080) -#define MCF_INTC1_IMRL_INT_MASK8 (0x00000100) -#define MCF_INTC1_IMRL_INT_MASK9 (0x00000200) -#define MCF_INTC1_IMRL_INT_MASK10 (0x00000400) -#define MCF_INTC1_IMRL_INT_MASK11 (0x00000800) -#define MCF_INTC1_IMRL_INT_MASK12 (0x00001000) -#define MCF_INTC1_IMRL_INT_MASK13 (0x00002000) -#define MCF_INTC1_IMRL_INT_MASK14 (0x00004000) -#define MCF_INTC1_IMRL_INT_MASK15 (0x00008000) -#define MCF_INTC1_IMRL_INT_MASK16 (0x00010000) -#define MCF_INTC1_IMRL_INT_MASK17 (0x00020000) -#define MCF_INTC1_IMRL_INT_MASK18 (0x00040000) -#define MCF_INTC1_IMRL_INT_MASK19 (0x00080000) -#define MCF_INTC1_IMRL_INT_MASK20 (0x00100000) -#define MCF_INTC1_IMRL_INT_MASK21 (0x00200000) -#define MCF_INTC1_IMRL_INT_MASK22 (0x00400000) -#define MCF_INTC1_IMRL_INT_MASK23 (0x00800000) -#define MCF_INTC1_IMRL_INT_MASK24 (0x01000000) -#define MCF_INTC1_IMRL_INT_MASK25 (0x02000000) -#define MCF_INTC1_IMRL_INT_MASK26 (0x04000000) -#define MCF_INTC1_IMRL_INT_MASK27 (0x08000000) -#define MCF_INTC1_IMRL_INT_MASK28 (0x10000000) -#define MCF_INTC1_IMRL_INT_MASK29 (0x20000000) -#define MCF_INTC1_IMRL_INT_MASK30 (0x40000000) -#define MCF_INTC1_IMRL_INT_MASK31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_INTFRCH */ -#define MCF_INTC1_INTFRCH_INTFRC32 (0x00000001) -#define MCF_INTC1_INTFRCH_INTFRC33 (0x00000002) -#define MCF_INTC1_INTFRCH_INTFRC34 (0x00000004) -#define MCF_INTC1_INTFRCH_INTFRC35 (0x00000008) -#define MCF_INTC1_INTFRCH_INTFRC36 (0x00000010) -#define MCF_INTC1_INTFRCH_INTFRC37 (0x00000020) -#define MCF_INTC1_INTFRCH_INTFRC38 (0x00000040) -#define MCF_INTC1_INTFRCH_INTFRC39 (0x00000080) -#define MCF_INTC1_INTFRCH_INTFRC40 (0x00000100) -#define MCF_INTC1_INTFRCH_INTFRC41 (0x00000200) -#define MCF_INTC1_INTFRCH_INTFRC42 (0x00000400) -#define MCF_INTC1_INTFRCH_INTFRC43 (0x00000800) -#define MCF_INTC1_INTFRCH_INTFRC44 (0x00001000) -#define MCF_INTC1_INTFRCH_INTFRC45 (0x00002000) -#define MCF_INTC1_INTFRCH_INTFRC46 (0x00004000) -#define MCF_INTC1_INTFRCH_INTFRC47 (0x00008000) -#define MCF_INTC1_INTFRCH_INTFRC48 (0x00010000) -#define MCF_INTC1_INTFRCH_INTFRC49 (0x00020000) -#define MCF_INTC1_INTFRCH_INTFRC50 (0x00040000) -#define MCF_INTC1_INTFRCH_INTFRC51 (0x00080000) -#define MCF_INTC1_INTFRCH_INTFRC52 (0x00100000) -#define MCF_INTC1_INTFRCH_INTFRC53 (0x00200000) -#define MCF_INTC1_INTFRCH_INTFRC54 (0x00400000) -#define MCF_INTC1_INTFRCH_INTFRC55 (0x00800000) -#define MCF_INTC1_INTFRCH_INTFRC56 (0x01000000) -#define MCF_INTC1_INTFRCH_INTFRC57 (0x02000000) -#define MCF_INTC1_INTFRCH_INTFRC58 (0x04000000) -#define MCF_INTC1_INTFRCH_INTFRC59 (0x08000000) -#define MCF_INTC1_INTFRCH_INTFRC60 (0x10000000) -#define MCF_INTC1_INTFRCH_INTFRC61 (0x20000000) -#define MCF_INTC1_INTFRCH_INTFRC62 (0x40000000) -#define MCF_INTC1_INTFRCH_INTFRC63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_INTFRCL */ -#define MCF_INTC1_INTFRCL_INTFRC1 (0x00000002) -#define MCF_INTC1_INTFRCL_INTFRC2 (0x00000004) -#define MCF_INTC1_INTFRCL_INTFRC3 (0x00000008) -#define MCF_INTC1_INTFRCL_INTFRC4 (0x00000010) -#define MCF_INTC1_INTFRCL_INTFRC5 (0x00000020) -#define MCF_INTC1_INTFRCL_INT6 (0x00000040) -#define MCF_INTC1_INTFRCL_INT7 (0x00000080) -#define MCF_INTC1_INTFRCL_INT8 (0x00000100) -#define MCF_INTC1_INTFRCL_INT9 (0x00000200) -#define MCF_INTC1_INTFRCL_INT10 (0x00000400) -#define MCF_INTC1_INTFRCL_INTFRC11 (0x00000800) -#define MCF_INTC1_INTFRCL_INTFRC12 (0x00001000) -#define MCF_INTC1_INTFRCL_INTFRC13 (0x00002000) -#define MCF_INTC1_INTFRCL_INTFRC14 (0x00004000) -#define MCF_INTC1_INTFRCL_INT15 (0x00008000) -#define MCF_INTC1_INTFRCL_INTFRC16 (0x00010000) -#define MCF_INTC1_INTFRCL_INTFRC17 (0x00020000) -#define MCF_INTC1_INTFRCL_INTFRC18 (0x00040000) -#define MCF_INTC1_INTFRCL_INTFRC19 (0x00080000) -#define MCF_INTC1_INTFRCL_INTFRC20 (0x00100000) -#define MCF_INTC1_INTFRCL_INTFRC21 (0x00200000) -#define MCF_INTC1_INTFRCL_INTFRC22 (0x00400000) -#define MCF_INTC1_INTFRCL_INTFRC23 (0x00800000) -#define MCF_INTC1_INTFRCL_INTFRC24 (0x01000000) -#define MCF_INTC1_INTFRCL_INTFRC25 (0x02000000) -#define MCF_INTC1_INTFRCL_INTFRC26 (0x04000000) -#define MCF_INTC1_INTFRCL_INTFRC27 (0x08000000) -#define MCF_INTC1_INTFRCL_INTFRC28 (0x10000000) -#define MCF_INTC1_INTFRCL_INTFRC29 (0x20000000) -#define MCF_INTC1_INTFRCL_INTFRC30 (0x40000000) -#define MCF_INTC1_INTFRCL_INTFRC31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC1_IRLR */ -#define MCF_INTC1_IRLR_IRQ(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_INTC1_IACKLPR */ -#define MCF_INTC1_IACKLPR_PRI(x) (((x)&0x0F)<<0) -#define MCF_INTC1_IACKLPR_LEVEL(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF_INTC1_ICRn */ -#define MCF_INTC1_ICRn_IP(x) (((x)&0x07)<<0) -#define MCF_INTC1_ICRn_IL(x) (((x)&0x07)<<3) - -/********************************************************************/ - -#endif /* __MCF523X_INTC1_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_mdha.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_mdha.h deleted file mode 100644 index 9611db77c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_mdha.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * File: mcf523x_mdha.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_MDHA_H__ -#define __MCF523X_MDHA_H__ - -/********************************************************************* -* -* Message Digest Hardware Accelerator (MDHA) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_MDHA_MDMR (*(vuint32*)(void*)(&__IPSBAR[0x190000])) -#define MCF_MDHA_MDCR (*(vuint32*)(void*)(&__IPSBAR[0x190004])) -#define MCF_MDHA_MDCMR (*(vuint32*)(void*)(&__IPSBAR[0x190008])) -#define MCF_MDHA_MDSR (*(vuint32*)(void*)(&__IPSBAR[0x19000C])) -#define MCF_MDHA_MDISR (*(vuint32*)(void*)(&__IPSBAR[0x190010])) -#define MCF_MDHA_MDIMR (*(vuint32*)(void*)(&__IPSBAR[0x190014])) -#define MCF_MDHA_MDDSR (*(vuint32*)(void*)(&__IPSBAR[0x19001C])) -#define MCF_MDHA_MDIN (*(vuint32*)(void*)(&__IPSBAR[0x190020])) -#define MCF_MDHA_MDA0 (*(vuint32*)(void*)(&__IPSBAR[0x190030])) -#define MCF_MDHA_MDB0 (*(vuint32*)(void*)(&__IPSBAR[0x190034])) -#define MCF_MDHA_MDC0 (*(vuint32*)(void*)(&__IPSBAR[0x190038])) -#define MCF_MDHA_MDD0 (*(vuint32*)(void*)(&__IPSBAR[0x19003C])) -#define MCF_MDHA_MDE0 (*(vuint32*)(void*)(&__IPSBAR[0x190040])) -#define MCF_MDHA_MDMDS (*(vuint32*)(void*)(&__IPSBAR[0x190044])) -#define MCF_MDHA_MDA1 (*(vuint32*)(void*)(&__IPSBAR[0x190070])) -#define MCF_MDHA_MDB1 (*(vuint32*)(void*)(&__IPSBAR[0x190074])) -#define MCF_MDHA_MDC1 (*(vuint32*)(void*)(&__IPSBAR[0x190078])) -#define MCF_MDHA_MDD1 (*(vuint32*)(void*)(&__IPSBAR[0x19007C])) -#define MCF_MDHA_MDE1 (*(vuint32*)(void*)(&__IPSBAR[0x190080])) - -/* Bit definitions and macros for MCF_MDHA_MDMR */ -#define MCF_MDHA_MDMR_ALG (0x00000001) -#define MCF_MDHA_MDMR_PDATA (0x00000004) -#define MCF_MDHA_MDMR_MAC(x) (((x)&0x00000003)<<3) -#define MCF_MDHA_MDMR_INIT (0x00000020) -#define MCF_MDHA_MDMR_IPAD (0x00000040) -#define MCF_MDHA_MDMR_OPAD (0x00000080) -#define MCF_MDHA_MDMR_SWAP (0x00000100) -#define MCF_MDHA_MDMR_MACFULL (0x00000200) -#define MCF_MDHA_MDMR_SSL (0x00000400) - -/* Bit definitions and macros for MCF_MDHA_MDCR */ -#define MCF_MDHA_MDCR_IE (0x00000001) - -/* Bit definitions and macros for MCF_MDHA_MDCMR */ -#define MCF_MDHA_MDCMR_SWR (0x00000001) -#define MCF_MDHA_MDCMR_RI (0x00000002) -#define MCF_MDHA_MDCMR_CI (0x00000004) -#define MCF_MDHA_MDCMR_GO (0x00000008) - -/* Bit definitions and macros for MCF_MDHA_MDSR */ -#define MCF_MDHA_MDSR_INT (0x00000001) -#define MCF_MDHA_MDSR_DONE (0x00000002) -#define MCF_MDHA_MDSR_ERR (0x00000004) -#define MCF_MDHA_MDSR_RD (0x00000008) -#define MCF_MDHA_MDSR_BUSY (0x00000010) -#define MCF_MDHA_MDSR_END (0x00000020) -#define MCF_MDHA_MDSR_HSH (0x00000040) -#define MCF_MDHA_MDSR_GNW (0x00000080) -#define MCF_MDHA_MDSR_FS(x) (((x)&0x00000007)<<8) -#define MCF_MDHA_MDSR_APD(x) (((x)&0x00000007)<<13) -#define MCF_MDHA_MDSR_IFL(x) (((x)&0x000000FF)<<16) - -/* Bit definitions and macros for MCF_MDHA_MDIR */ -#define MCF_MDHA_MDIR_IFO (0x00000001) -#define MCF_MDHA_MDIR_NON (0x00000004) -#define MCF_MDHA_MDIR_IME (0x00000010) -#define MCF_MDHA_MDIR_IDS (0x00000020) -#define MCF_MDHA_MDIR_RMDP (0x00000080) -#define MCF_MDHA_MDIR_ERE (0x00000100) -#define MCF_MDHA_MDIR_GTDS (0x00000200) - -/* Bit definitions and macros for MCF_MDHA_MDIMR */ -#define MCF_MDHA_MDIMR_IFO (0x00000001) -#define MCF_MDHA_MDIMR_NON (0x00000004) -#define MCF_MDHA_MDIMR_IME (0x00000010) -#define MCF_MDHA_MDIMR_IDS (0x00000020) -#define MCF_MDHA_MDIMR_RMDP (0x00000080) -#define MCF_MDHA_MDIMR_ERE (0x00000100) -#define MCF_MDHA_MDIMR_GTDS (0x00000200) - -/* Bit definitions and macros for MCF_MDHA_MDDSR */ -#define MCF_MDHA_MDDSR_DATASIZE(x) (((x)&0x1FFFFFFF)<<0) - -/********************************************************************/ - -#endif /* __MCF523X_MDHA_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_pit.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_pit.h deleted file mode 100644 index 35d5a7f0f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_pit.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * File: mcf523x_pit.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_PIT_H__ -#define __MCF523X_PIT_H__ - -/********************************************************************* -* -* Programmable Interrupt Timer Modules (PIT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PIT_PCSR0 (*(vuint16*)(void*)(&__IPSBAR[0x150000])) -#define MCF_PIT_PMR0 (*(vuint16*)(void*)(&__IPSBAR[0x150002])) -#define MCF_PIT_PCNTR0 (*(vuint16*)(void*)(&__IPSBAR[0x150004])) -#define MCF_PIT_PCSR1 (*(vuint16*)(void*)(&__IPSBAR[0x160000])) -#define MCF_PIT_PMR1 (*(vuint16*)(void*)(&__IPSBAR[0x160002])) -#define MCF_PIT_PCNTR1 (*(vuint16*)(void*)(&__IPSBAR[0x160004])) -#define MCF_PIT_PCSR2 (*(vuint16*)(void*)(&__IPSBAR[0x170000])) -#define MCF_PIT_PMR2 (*(vuint16*)(void*)(&__IPSBAR[0x170002])) -#define MCF_PIT_PCNTR2 (*(vuint16*)(void*)(&__IPSBAR[0x170004])) -#define MCF_PIT_PCSR3 (*(vuint16*)(void*)(&__IPSBAR[0x180000])) -#define MCF_PIT_PMR3 (*(vuint16*)(void*)(&__IPSBAR[0x180002])) -#define MCF_PIT_PCNTR3 (*(vuint16*)(void*)(&__IPSBAR[0x180004])) -#define MCF_PIT_PCSR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150000+((x)*0x10000)])) -#define MCF_PIT_PMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150002+((x)*0x10000)])) -#define MCF_PIT_PCNTR(x) (*(vuint16*)(void*)(&__IPSBAR[0x150004+((x)*0x10000)])) - -/* Bit definitions and macros for MCF_PIT_PCSR */ -#define MCF_PIT_PCSR_EN (0x0001) -#define MCF_PIT_PCSR_RLD (0x0002) -#define MCF_PIT_PCSR_PIF (0x0004) -#define MCF_PIT_PCSR_PIE (0x0008) -#define MCF_PIT_PCSR_OVW (0x0010) -#define MCF_PIT_PCSR_HALTED (0x0020) -#define MCF_PIT_PCSR_DOZE (0x0040) -#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) - -/* Bit definitions and macros for MCF_PIT_PMR */ -#define MCF_PIT_PMR_PM0 (0x0001) -#define MCF_PIT_PMR_PM1 (0x0002) -#define MCF_PIT_PMR_PM2 (0x0004) -#define MCF_PIT_PMR_PM3 (0x0008) -#define MCF_PIT_PMR_PM4 (0x0010) -#define MCF_PIT_PMR_PM5 (0x0020) -#define MCF_PIT_PMR_PM6 (0x0040) -#define MCF_PIT_PMR_PM7 (0x0080) -#define MCF_PIT_PMR_PM8 (0x0100) -#define MCF_PIT_PMR_PM9 (0x0200) -#define MCF_PIT_PMR_PM10 (0x0400) -#define MCF_PIT_PMR_PM11 (0x0800) -#define MCF_PIT_PMR_PM12 (0x1000) -#define MCF_PIT_PMR_PM13 (0x2000) -#define MCF_PIT_PMR_PM14 (0x4000) -#define MCF_PIT_PMR_PM15 (0x8000) - -/* Bit definitions and macros for MCF_PIT_PCNTR */ -#define MCF_PIT_PCNTR_PC0 (0x0001) -#define MCF_PIT_PCNTR_PC1 (0x0002) -#define MCF_PIT_PCNTR_PC2 (0x0004) -#define MCF_PIT_PCNTR_PC3 (0x0008) -#define MCF_PIT_PCNTR_PC4 (0x0010) -#define MCF_PIT_PCNTR_PC5 (0x0020) -#define MCF_PIT_PCNTR_PC6 (0x0040) -#define MCF_PIT_PCNTR_PC7 (0x0080) -#define MCF_PIT_PCNTR_PC8 (0x0100) -#define MCF_PIT_PCNTR_PC9 (0x0200) -#define MCF_PIT_PCNTR_PC10 (0x0400) -#define MCF_PIT_PCNTR_PC11 (0x0800) -#define MCF_PIT_PCNTR_PC12 (0x1000) -#define MCF_PIT_PCNTR_PC13 (0x2000) -#define MCF_PIT_PCNTR_PC14 (0x4000) -#define MCF_PIT_PCNTR_PC15 (0x8000) - -/********************************************************************/ - -#endif /* __MCF523X_PIT_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_qspi.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_qspi.h deleted file mode 100644 index 16a33687b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_qspi.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * File: mcf523x_qspi.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_QSPI_H__ -#define __MCF523X_QSPI_H__ - -/********************************************************************* -* -* Queued Serial Peripheral Interface (QSPI) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_QSPI_QMR (*(vuint16*)(void*)(&__IPSBAR[0x000340])) -#define MCF_QSPI_QDLYR (*(vuint16*)(void*)(&__IPSBAR[0x000344])) -#define MCF_QSPI_QWR (*(vuint16*)(void*)(&__IPSBAR[0x000348])) -#define MCF_QSPI_QIR (*(vuint16*)(void*)(&__IPSBAR[0x00034C])) -#define MCF_QSPI_QAR (*(vuint16*)(void*)(&__IPSBAR[0x000350])) -#define MCF_QSPI_QDR (*(vuint16*)(void*)(&__IPSBAR[0x000354])) - -/* Bit definitions and macros for MCF_QSPI_QMR */ -#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) -#define MCF_QSPI_QMR_CPHA (0x0100) -#define MCF_QSPI_QMR_CPOL (0x0200) -#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) -#define MCF_QSPI_QMR_DOHIE (0x4000) -#define MCF_QSPI_QMR_MSTR (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QDLYR */ -#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) -#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) -#define MCF_QSPI_QDLYR_SPE (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QWR */ -#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) -#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) -#define MCF_QSPI_QWR_CSIV (0x1000) -#define MCF_QSPI_QWR_WRTO (0x2000) -#define MCF_QSPI_QWR_WREN (0x4000) -#define MCF_QSPI_QWR_HALT (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QIR */ -#define MCF_QSPI_QIR_SPIF (0x0001) -#define MCF_QSPI_QIR_ABRT (0x0004) -#define MCF_QSPI_QIR_WCEF (0x0008) -#define MCF_QSPI_QIR_SPIFE (0x0100) -#define MCF_QSPI_QIR_ABRTE (0x0400) -#define MCF_QSPI_QIR_WCEFE (0x0800) -#define MCF_QSPI_QIR_ABRTL (0x1000) -#define MCF_QSPI_QIR_ABRTB (0x4000) -#define MCF_QSPI_QIR_WCEFB (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QAR */ -#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) - -/********************************************************************/ - -#endif /* __MCF523X_QSPI_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_rcm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_rcm.h deleted file mode 100644 index 6b43ce93f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_rcm.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * File: mcf523x_rcm.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_RCM_H__ -#define __MCF523X_RCM_H__ - -/********************************************************************* -* -* Reset Configuration Module (RCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_RCM_RCR (*(vuint8 *)(void*)(&__IPSBAR[0x110000])) -#define MCF_RCM_RSR (*(vuint8 *)(void*)(&__IPSBAR[0x110001])) - -/* Bit definitions and macros for MCF_RCM_RCR */ -#define MCF_RCM_RCR_FRCRSTOUT (0x40) -#define MCF_RCM_RCR_SOFTRST (0x80) - -/* Bit definitions and macros for MCF_RCM_RSR */ -#define MCF_RCM_RSR_LOL (0x01) -#define MCF_RCM_RSR_LOC (0x02) -#define MCF_RCM_RSR_EXT (0x04) -#define MCF_RCM_RSR_POR (0x08) -#define MCF_RCM_RSR_WDR (0x10) -#define MCF_RCM_RSR_SOFT (0x20) - -/********************************************************************/ - -#endif /* __MCF523X_RCM_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_rng.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_rng.h deleted file mode 100644 index 16058ab6b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_rng.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * File: mcf523x_rng.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_RNG_H__ -#define __MCF523X_RNG_H__ - -/********************************************************************* -* -* Random Number Generator (RNG) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_RNG_RNGCR (*(vuint32*)(void*)(&__IPSBAR[0x1A0000])) -#define MCF_RNG_RNGSR (*(vuint32*)(void*)(&__IPSBAR[0x1A0004])) -#define MCF_RNG_RNGER (*(vuint32*)(void*)(&__IPSBAR[0x1A0008])) -#define MCF_RNG_RNGOUT (*(vuint32*)(void*)(&__IPSBAR[0x1A000C])) - -/* Bit definitions and macros for MCF_RNG_RNGCR */ -#define MCF_RNG_RNGCR_GO (0x00000001) -#define MCF_RNG_RNGCR_HA (0x00000002) -#define MCF_RNG_RNGCR_IM (0x00000004) -#define MCF_RNG_RNGCR_CI (0x00000008) - -/* Bit definitions and macros for MCF_RNG_RNGSR */ -#define MCF_RNG_RNGSR_SV (0x00000001) -#define MCF_RNG_RNGSR_LRS (0x00000002) -#define MCF_RNG_RNGSR_FUF (0x00000004) -#define MCF_RNG_RNGSR_EI (0x00000008) -#define MCF_RNG_RNGSR_OFL(x) (((x)&0x000000FF)<<8) -#define MCF_RNG_RNGSR_OFS(x) (((x)&0x000000FF)<<16) - -/********************************************************************/ - -#endif /* __MCF523X_RNG_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_scm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_scm.h deleted file mode 100644 index 034654e0a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_scm.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * File: mcf523x_scm.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_SCM_H__ -#define __MCF523X_SCM_H__ - -/********************************************************************* -* -* System Control Module (SCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SCM_IPSBAR (*(vuint32*)(void*)(&__IPSBAR[0x000000])) -#define MCF_SCM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x000008])) -#define MCF_SCM_CRSR (*(vuint8 *)(void*)(&__IPSBAR[0x000010])) -#define MCF_SCM_CWCR (*(vuint8 *)(void*)(&__IPSBAR[0x000011])) -#define MCF_SCM_LPICR (*(vuint8 *)(void*)(&__IPSBAR[0x000012])) -#define MCF_SCM_CWSR (*(vuint8 *)(void*)(&__IPSBAR[0x000013])) -#define MCF_SCM_DMAREQC (*(vuint32*)(void*)(&__IPSBAR[0x000014])) -#define MCF_SCM_MPARK (*(vuint32*)(void*)(&__IPSBAR[0x00001C])) -#define MCF_SCM_MPR (*(vuint8 *)(void*)(&__IPSBAR[0x000020])) -#define MCF_SCM_PACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000024])) -#define MCF_SCM_PACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000025])) -#define MCF_SCM_PACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000026])) -#define MCF_SCM_PACR3 (*(vuint8 *)(void*)(&__IPSBAR[0x000027])) -#define MCF_SCM_PACR4 (*(vuint8 *)(void*)(&__IPSBAR[0x000028])) -#define MCF_SCM_PACR5 (*(vuint8 *)(void*)(&__IPSBAR[0x00002A])) -#define MCF_SCM_PACR6 (*(vuint8 *)(void*)(&__IPSBAR[0x00002B])) -#define MCF_SCM_PACR7 (*(vuint8 *)(void*)(&__IPSBAR[0x00002C])) -#define MCF_SCM_PACR8 (*(vuint8 *)(void*)(&__IPSBAR[0x00002E])) -#define MCF_SCM_GPACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000030])) - -/* Bit definitions and macros for MCF_SCM_IPSBAR */ -#define MCF_SCM_IPSBAR_V (0x00000001) -#define MCF_SCM_IPSBAR_BA(x) (((x)&0x00000003)<<30) - -/* Bit definitions and macros for MCF_SCM_RAMBAR */ -#define MCF_SCM_RAMBAR_BDE (0x00000200) -#define MCF_SCM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_SCM_CRSR */ -#define MCF_SCM_CRSR_CWDR (0x20) -#define MCF_SCM_CRSR_EXT (0x80) - -/* Bit definitions and macros for MCF_SCM_CWCR */ -#define MCF_SCM_CWCR_CWTIC (0x01) -#define MCF_SCM_CWCR_CWTAVAL (0x02) -#define MCF_SCM_CWCR_CWTA (0x04) -#define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3) -#define MCF_SCM_CWCR_CWRI (0x40) -#define MCF_SCM_CWCR_CWE (0x80) - -/* Bit definitions and macros for MCF_SCM_LPICR */ -#define MCF_SCM_LPICR_XLPM_IPL(x) (((x)&0x07)<<4) -#define MCF_SCM_LPICR_ENBSTOP (0x80) - -/* Bit definitions and macros for MCF_SCM_DMAREQC */ -#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0) -#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4) -#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8) -#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12) - -/* Bit definitions and macros for MCF_SCM_MPARK */ -#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8) -#define MCF_SCM_MPARK_PRKLAST (0x00001000) -#define MCF_SCM_MPARK_TIMEOUT (0x00002000) -#define MCF_SCM_MPARK_FIXED (0x00004000) -#define MCF_SCM_MPARK_M1_PRTY(x) (((x)&0x00000003)<<16) -#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x00000003)<<18) -#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x00000003)<<20) -#define MCF_SCM_MPARK_M3_PRTY(x) (((x)&0x00000003)<<22) -#define MCF_SCM_MPARK_BCR24BIT (0x01000000) -#define MCF_SCM_MPARK_M2_P_EN (0x02000000) - -/* Bit definitions and macros for MCF_SCM_MPR */ -#define MCF_SCM_MPR_MPR(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF_SCM_PACR0 */ -#define MCF_SCM_PACR0_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR0_LOCK0 (0x08) -#define MCF_SCM_PACR0_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR0_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR1 */ -#define MCF_SCM_PACR1_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR1_LOCK0 (0x08) -#define MCF_SCM_PACR1_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR1_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR2 */ -#define MCF_SCM_PACR2_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR2_LOCK0 (0x08) -#define MCF_SCM_PACR2_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR2_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR3 */ -#define MCF_SCM_PACR3_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR3_LOCK0 (0x08) -#define MCF_SCM_PACR3_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR3_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR4 */ -#define MCF_SCM_PACR4_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR4_LOCK0 (0x08) -#define MCF_SCM_PACR4_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR4_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR5 */ -#define MCF_SCM_PACR5_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR5_LOCK0 (0x08) -#define MCF_SCM_PACR5_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR5_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR6 */ -#define MCF_SCM_PACR6_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR6_LOCK0 (0x08) -#define MCF_SCM_PACR6_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR6_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR7 */ -#define MCF_SCM_PACR7_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR7_LOCK0 (0x08) -#define MCF_SCM_PACR7_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR7_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_PACR8 */ -#define MCF_SCM_PACR8_ACCESS_CTRL0(x) (((x)&0x07)<<0) -#define MCF_SCM_PACR8_LOCK0 (0x08) -#define MCF_SCM_PACR8_ACCESS_CTRL1(x) (((x)&0x07)<<4) -#define MCF_SCM_PACR8_LOCK1 (0x80) - -/* Bit definitions and macros for MCF_SCM_GPACR0 */ -#define MCF_SCM_GPACR0_ACCESS_CTRL(x) (((x)&0x0F)<<0) -#define MCF_SCM_GPACR0_LOCK (0x80) - -/********************************************************************/ - -#endif /* __MCF523X_SCM_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_sdramc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_sdramc.h deleted file mode 100644 index ae29ce739..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_sdramc.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * File: mcf523x_sdramc.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_SDRAMC_H__ -#define __MCF523X_SDRAMC_H__ - -/********************************************************************* -* -* SDRAM Controller (SDRAMC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SDRAMC_DCR (*(vuint16*)(void*)(&__IPSBAR[0x000040])) -#define MCF_SDRAMC_DACR0 (*(vuint32*)(void*)(&__IPSBAR[0x000048])) -#define MCF_SDRAMC_DMR0 (*(vuint32*)(void*)(&__IPSBAR[0x00004C])) -#define MCF_SDRAMC_DACR1 (*(vuint32*)(void*)(&__IPSBAR[0x000050])) -#define MCF_SDRAMC_DMR1 (*(vuint32*)(void*)(&__IPSBAR[0x000054])) - -/* Bit definitions and macros for MCF_SDRAMC_DCR */ -#define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0) -#define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9) -#define MCF_SDRAMC_DCR_IS (0x0800) -#define MCF_SDRAMC_DCR_COC (0x1000) -#define MCF_SDRAMC_DCR_NAM (0x2000) - -/* Bit definitions and macros for MCF_SDRAMC_DACR0 */ -#define MCF_SDRAMC_DACR0_IP (0x00000008) -#define MCF_SDRAMC_DACR0_PS(x) (((x)&0x00000003)<<4) -#define MCF_SDRAMC_DACR0_MRS (0x00000040) -#define MCF_SDRAMC_DACR0_CBM(x) (((x)&0x00000007)<<8) -#define MCF_SDRAMC_DACR0_CASL(x) (((x)&0x00000003)<<12) -#define MCF_SDRAMC_DACR0_RE (0x00008000) -#define MCF_SDRAMC_DACR0_BA(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF_SDRAMC_DMR0 */ -#define MCF_SDRAMC_DMR0_V (0x00000001) -#define MCF_SDRAMC_DMR0_WP (0x00000100) -#define MCF_SDRAMC_DMR0_BAM(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF_SDRAMC_DACR1 */ -#define MCF_SDRAMC_DACR1_IP (0x00000008) -#define MCF_SDRAMC_DACR1_PS(x) (((x)&0x00000003)<<4) -#define MCF_SDRAMC_DACR1_MRS (0x00000040) -#define MCF_SDRAMC_DACR1_CBM(x) (((x)&0x00000007)<<8) -#define MCF_SDRAMC_DACR1_CASL(x) (((x)&0x00000003)<<12) -#define MCF_SDRAMC_DACR1_RE (0x00008000) -#define MCF_SDRAMC_DACR1_BA(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF_SDRAMC_DMR1 */ -#define MCF_SDRAMC_DMR1_V (0x00000001) -#define MCF_SDRAMC_DMR1_WP (0x00000100) -#define MCF_SDRAMC_DMR1_BAM(x) (((x)&0x00003FFF)<<18) - -/********************************************************************/ - -#define MCF_SDRAMC_DMR_BAM_4G (0xFFFC0000) -#define MCF_SDRAMC_DMR_BAM_2G (0x7FFC0000) -#define MCF_SDRAMC_DMR_BAM_1G (0x3FFC0000) -#define MCF_SDRAMC_DMR_BAM_1024M (0x3FFC0000) -#define MCF_SDRAMC_DMR_BAM_512M (0x1FFC0000) -#define MCF_SDRAMC_DMR_BAM_256M (0x0FFC0000) -#define MCF_SDRAMC_DMR_BAM_128M (0x07FC0000) -#define MCF_SDRAMC_DMR_BAM_64M (0x03FC0000) -#define MCF_SDRAMC_DMR_BAM_32M (0x01FC0000) -#define MCF_SDRAMC_DMR_BAM_16M (0x00FC0000) -#define MCF_SDRAMC_DMR_BAM_8M (0x007C0000) -#define MCF_SDRAMC_DMR_BAM_4M (0x003C0000) -#define MCF_SDRAMC_DMR_BAM_2M (0x001C0000) -#define MCF_SDRAMC_DMR_BAM_1M (0x000C0000) -#define MCF_SDRAMC_DMR_BAM_1024K (0x000C0000) -#define MCF_SDRAMC_DMR_BAM_512K (0x00040000) -#define MCF_SDRAMC_DMR_BAM_256K (0x00000000) -#define MCF_SDRAMC_DMR_WP (0x00000100) -#define MCF_SDRAMC_DMR_CI (0x00000040) -#define MCF_SDRAMC_DMR_AM (0x00000020) -#define MCF_SDRAMC_DMR_SC (0x00000010) -#define MCF_SDRAMC_DMR_SD (0x00000008) -#define MCF_SDRAMC_DMR_UC (0x00000004) -#define MCF_SDRAMC_DMR_UD (0x00000002) -#define MCF_SDRAMC_DMR_V (0x00000001) - -#endif /* __MCF523X_SDRAMC_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_skha.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_skha.h deleted file mode 100644 index 437e86d0b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_skha.h +++ /dev/null @@ -1,114 +0,0 @@ -/* - * File: mcf523x_skha.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_SKHA_H__ -#define __MCF523X_SKHA_H__ - -/********************************************************************* -* -* Symmetric Key Hardware Accelerator (SKHA) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SKHA_SKMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0000])) -#define MCF_SKHA_SKCR (*(vuint32*)(void*)(&__IPSBAR[0x1B0004])) -#define MCF_SKHA_SKCMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0008])) -#define MCF_SKHA_SKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B000C])) -#define MCF_SKHA_SKIR (*(vuint32*)(void*)(&__IPSBAR[0x1B0010])) -#define MCF_SKHA_SKIMR (*(vuint32*)(void*)(&__IPSBAR[0x1B0014])) -#define MCF_SKHA_SKKSR (*(vuint32*)(void*)(&__IPSBAR[0x1B0018])) -#define MCF_SKHA_SKDSR (*(vuint32*)(void*)(&__IPSBAR[0x1B001C])) -#define MCF_SKHA_SKIN (*(vuint32*)(void*)(&__IPSBAR[0x1B0020])) -#define MCF_SKHA_SKOUT (*(vuint32*)(void*)(&__IPSBAR[0x1B0024])) -#define MCF_SKHA_SKKDR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0030])) -#define MCF_SKHA_SKKDR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0034])) -#define MCF_SKHA_SKKDR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0038])) -#define MCF_SKHA_SKKDR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B003C])) -#define MCF_SKHA_SKKDR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0040])) -#define MCF_SKHA_SKKDR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0044])) -#define MCF_SKHA_SKKDRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0030+((x)*0x004)])) -#define MCF_SKHA_SKCR0 (*(vuint32*)(void*)(&__IPSBAR[0x1B0070])) -#define MCF_SKHA_SKCR1 (*(vuint32*)(void*)(&__IPSBAR[0x1B0074])) -#define MCF_SKHA_SKCR2 (*(vuint32*)(void*)(&__IPSBAR[0x1B0078])) -#define MCF_SKHA_SKCR3 (*(vuint32*)(void*)(&__IPSBAR[0x1B007C])) -#define MCF_SKHA_SKCR4 (*(vuint32*)(void*)(&__IPSBAR[0x1B0080])) -#define MCF_SKHA_SKCR5 (*(vuint32*)(void*)(&__IPSBAR[0x1B0084])) -#define MCF_SKHA_SKCR6 (*(vuint32*)(void*)(&__IPSBAR[0x1B0088])) -#define MCF_SKHA_SKCR7 (*(vuint32*)(void*)(&__IPSBAR[0x1B008C])) -#define MCF_SKHA_SKCR8 (*(vuint32*)(void*)(&__IPSBAR[0x1B0090])) -#define MCF_SKHA_SKCR9 (*(vuint32*)(void*)(&__IPSBAR[0x1B0094])) -#define MCF_SKHA_SKCR10 (*(vuint32*)(void*)(&__IPSBAR[0x1B0098])) -#define MCF_SKHA_SKCR11 (*(vuint32*)(void*)(&__IPSBAR[0x1B009C])) -#define MCF_SKHA_SKCRn(x) (*(vuint32*)(void*)(&__IPSBAR[0x1B0070+((x)*0x004)])) - -/* Bit definitions and macros for MCF_SKHA_SKMR */ -#define MCF_SKHA_SKMR_ALG(x) (((x)&0x00000003)<<0) -#define MCF_SKHA_SKMR_DIR (0x00000004) -#define MCF_SKHA_SKMR_CM(x) (((x)&0x00000003)<<3) -#define MCF_SKHA_SKMR_DKP (0x00000100) -#define MCF_SKHA_SKMR_CTRM(x) (((x)&0x0000000F)<<9) -#define MCF_SKHA_SKMR_CM_ECB (0x00000000) -#define MCF_SKHA_SKMR_CM_CBC (0x00000008) -#define MCF_SKHA_SKMR_CM_CTR (0x00000018) -#define MCF_SKHA_SKMR_DIR_DEC (0x00000000) -#define MCF_SKHA_SKMR_DIR_ENC (0x00000004) -#define MCF_SKHA_SKMR_ALG_AES (0x00000000) -#define MCF_SKHA_SKMR_ALG_DES (0x00000001) -#define MCF_SKHA_SKMR_ALG_TDES (0x00000002) - -/* Bit definitions and macros for MCF_SKHA_SKCR */ -#define MCF_SKHA_SKCR_IE (0x00000001) - -/* Bit definitions and macros for MCF_SKHA_SKCMR */ -#define MCF_SKHA_SKCMR_SWR (0x00000001) -#define MCF_SKHA_SKCMR_RI (0x00000002) -#define MCF_SKHA_SKCMR_CI (0x00000004) -#define MCF_SKHA_SKCMR_GO (0x00000008) - -/* Bit definitions and macros for MCF_SKHA_SKSR */ -#define MCF_SKHA_SKSR_INT (0x00000001) -#define MCF_SKHA_SKSR_DONE (0x00000002) -#define MCF_SKHA_SKSR_ERR (0x00000004) -#define MCF_SKHA_SKSR_RD (0x00000008) -#define MCF_SKHA_SKSR_BUSY (0x00000010) -#define MCF_SKHA_SKSR_IFL(x) (((x)&0x000000FF)<<16) -#define MCF_SKHA_SKSR_OFL(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_SKHA_SKIR */ -#define MCF_SKHA_SKIR_IFO (0x00000001) -#define MCF_SKHA_SKIR_OFU (0x00000002) -#define MCF_SKHA_SKIR_NEIF (0x00000004) -#define MCF_SKHA_SKIR_NEOF (0x00000008) -#define MCF_SKHA_SKIR_IME (0x00000010) -#define MCF_SKHA_SKIR_DSE (0x00000020) -#define MCF_SKHA_SKIR_KSE (0x00000040) -#define MCF_SKHA_SKIR_RMDP (0x00000080) -#define MCF_SKHA_SKIR_ERE (0x00000100) -#define MCF_SKHA_SKIR_KPE (0x00000200) -#define MCF_SKHA_SKIR_KRE (0x00000400) - -/* Bit definitions and macros for MCF_SKHA_SKIMR */ -#define MCF_SKHA_SKIMR_IFO (0x00000001) -#define MCF_SKHA_SKIMR_OFU (0x00000002) -#define MCF_SKHA_SKIMR_NEIF (0x00000004) -#define MCF_SKHA_SKIMR_NEOF (0x00000008) -#define MCF_SKHA_SKIMR_IME (0x00000010) -#define MCF_SKHA_SKIMR_DSE (0x00000020) -#define MCF_SKHA_SKIMR_KSE (0x00000040) -#define MCF_SKHA_SKIMR_RMDP (0x00000080) -#define MCF_SKHA_SKIMR_ERE (0x00000100) -#define MCF_SKHA_SKIMR_KPE (0x00000200) -#define MCF_SKHA_SKIMR_KRE (0x00000400) - -/* Bit definitions and macros for MCF_SKHA_SKKSR */ -#define MCF_SKHA_SKKSR_KEYSIZE(x) (((x)&0x0000003F)<<0) - -/********************************************************************/ - -#endif /* __MCF523X_SKHA_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_sram.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_sram.h deleted file mode 100644 index 7684d14d4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_sram.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * File: mcf523x_sram.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_SRAM_H__ -#define __MCF523X_SRAM_H__ - -/********************************************************************* -* -* 64KByte System SRAM (SRAM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SRAM_RAMBAR (*(vuint32*)(void*)(&__IPSBAR[0x20000000])) - -/* Bit definitions and macros for MCF_SRAM_RAMBAR */ -#define MCF_SRAM_RAMBAR_V (0x00000001) -#define MCF_SRAM_RAMBAR_UD (0x00000002) -#define MCF_SRAM_RAMBAR_UC (0x00000004) -#define MCF_SRAM_RAMBAR_SD (0x00000008) -#define MCF_SRAM_RAMBAR_SC (0x00000010) -#define MCF_SRAM_RAMBAR_CI (0x00000020) -#define MCF_SRAM_RAMBAR_WP (0x00000100) -#define MCF_SRAM_RAMBAR_SPV (0x00000200) -#define MCF_SRAM_RAMBAR_PRI2 (0x00000400) -#define MCF_SRAM_RAMBAR_PRI1 (0x00000800) -#define MCF_SRAM_RAMBAR_BA(x) (((x)&0x0000FFFF)<<16) - -/********************************************************************/ - -#endif /* __MCF523X_SRAM_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_timer.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_timer.h deleted file mode 100644 index c064b557a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_timer.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * File: mcf523x_timer.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_TIMER_H__ -#define __MCF523X_TIMER_H__ - -/********************************************************************* -* -* DMA Timers (TIMER) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_TIMER_DTMR0 (*(vuint16*)(void*)(&__IPSBAR[0x000400])) -#define MCF_TIMER_DTXMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000402])) -#define MCF_TIMER_DTER0 (*(vuint8 *)(void*)(&__IPSBAR[0x000403])) -#define MCF_TIMER_DTRR0 (*(vuint32*)(void*)(&__IPSBAR[0x000404])) -#define MCF_TIMER_DTCR0 (*(vuint32*)(void*)(&__IPSBAR[0x000408])) -#define MCF_TIMER_DTCN0 (*(vuint32*)(void*)(&__IPSBAR[0x00040C])) -#define MCF_TIMER_DTMR1 (*(vuint16*)(void*)(&__IPSBAR[0x000440])) -#define MCF_TIMER_DTXMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000442])) -#define MCF_TIMER_DTER1 (*(vuint8 *)(void*)(&__IPSBAR[0x000443])) -#define MCF_TIMER_DTRR1 (*(vuint32*)(void*)(&__IPSBAR[0x000444])) -#define MCF_TIMER_DTCR1 (*(vuint32*)(void*)(&__IPSBAR[0x000448])) -#define MCF_TIMER_DTCN1 (*(vuint32*)(void*)(&__IPSBAR[0x00044C])) -#define MCF_TIMER_DTMR2 (*(vuint16*)(void*)(&__IPSBAR[0x000480])) -#define MCF_TIMER_DTXMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000482])) -#define MCF_TIMER_DTER2 (*(vuint8 *)(void*)(&__IPSBAR[0x000483])) -#define MCF_TIMER_DTRR2 (*(vuint32*)(void*)(&__IPSBAR[0x000484])) -#define MCF_TIMER_DTCR2 (*(vuint32*)(void*)(&__IPSBAR[0x000488])) -#define MCF_TIMER_DTCN2 (*(vuint32*)(void*)(&__IPSBAR[0x00048C])) -#define MCF_TIMER_DTMR3 (*(vuint16*)(void*)(&__IPSBAR[0x0004C0])) -#define MCF_TIMER_DTXMR3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C2])) -#define MCF_TIMER_DTER3 (*(vuint8 *)(void*)(&__IPSBAR[0x0004C3])) -#define MCF_TIMER_DTRR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C4])) -#define MCF_TIMER_DTCR3 (*(vuint32*)(void*)(&__IPSBAR[0x0004C8])) -#define MCF_TIMER_DTCN3 (*(vuint32*)(void*)(&__IPSBAR[0x0004CC])) -#define MCF_TIMER_DTMR(x) (*(vuint16*)(void*)(&__IPSBAR[0x000400+((x)*0x040)])) -#define MCF_TIMER_DTXMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000402+((x)*0x040)])) -#define MCF_TIMER_DTER(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000403+((x)*0x040)])) -#define MCF_TIMER_DTRR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000404+((x)*0x040)])) -#define MCF_TIMER_DTCR(x) (*(vuint32*)(void*)(&__IPSBAR[0x000408+((x)*0x040)])) -#define MCF_TIMER_DTCN(x) (*(vuint32*)(void*)(&__IPSBAR[0x00040C+((x)*0x040)])) - -/* Bit definitions and macros for MCF_TIMER_DTMR */ -#define MCF_TIMER_DTMR_RST (0x0001) -#define MCF_TIMER_DTMR_CLK(x) (((x)&0x0003)<<1) -#define MCF_TIMER_DTMR_FRR (0x0008) -#define MCF_TIMER_DTMR_ORRI (0x0010) -#define MCF_TIMER_DTMR_OM (0x0020) -#define MCF_TIMER_DTMR_CE(x) (((x)&0x0003)<<6) -#define MCF_TIMER_DTMR_PS(x) (((x)&0x00FF)<<8) -#define MCF_TIMER_DTMR_CE_ANY (0x00C0) -#define MCF_TIMER_DTMR_CE_FALL (0x0080) -#define MCF_TIMER_DTMR_CE_RISE (0x0040) -#define MCF_TIMER_DTMR_CE_NONE (0x0000) -#define MCF_TIMER_DTMR_CLK_DTIN (0x0006) -#define MCF_TIMER_DTMR_CLK_DIV16 (0x0004) -#define MCF_TIMER_DTMR_CLK_DIV1 (0x0002) -#define MCF_TIMER_DTMR_CLK_STOP (0x0000) - -/* Bit definitions and macros for MCF_TIMER_DTXMR */ -#define MCF_TIMER_DTXMR_MODE16 (0x01) -#define MCF_TIMER_DTXMR_DMAEN (0x80) - -/* Bit definitions and macros for MCF_TIMER_DTER */ -#define MCF_TIMER_DTER_CAP (0x01) -#define MCF_TIMER_DTER_REF (0x02) - -/********************************************************************/ - -#endif /* __MCF523X_TIMER_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_uart.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_uart.h deleted file mode 100644 index 43232f675..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_uart.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * File: mcf523x_uart.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_UART_H__ -#define __MCF523X_UART_H__ - -/********************************************************************* -* -* Universal Asynchronous Receiver Transmitter (UART) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_UART_UMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000200])) -#define MCF_UART_USR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204])) -#define MCF_UART_UCSR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000204])) -#define MCF_UART_UCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000208])) -#define MCF_UART_URB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C])) -#define MCF_UART_UTB0 (*(vuint8 *)(void*)(&__IPSBAR[0x00020C])) -#define MCF_UART_UIPCR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210])) -#define MCF_UART_UACR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000210])) -#define MCF_UART_UISR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214])) -#define MCF_UART_UIMR0 (*(vuint8 *)(void*)(&__IPSBAR[0x000214])) -#define MCF_UART_UBG10 (*(vuint8 *)(void*)(&__IPSBAR[0x000218])) -#define MCF_UART_UBG20 (*(vuint8 *)(void*)(&__IPSBAR[0x00021C])) -#define MCF_UART_UIP0 (*(vuint8 *)(void*)(&__IPSBAR[0x000234])) -#define MCF_UART_UOP10 (*(vuint8 *)(void*)(&__IPSBAR[0x000238])) -#define MCF_UART_UOP00 (*(vuint8 *)(void*)(&__IPSBAR[0x00023C])) -#define MCF_UART_UMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000240])) -#define MCF_UART_USR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244])) -#define MCF_UART_UCSR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000244])) -#define MCF_UART_UCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000248])) -#define MCF_UART_URB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C])) -#define MCF_UART_UTB1 (*(vuint8 *)(void*)(&__IPSBAR[0x00024C])) -#define MCF_UART_UIPCR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250])) -#define MCF_UART_UACR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000250])) -#define MCF_UART_UISR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254])) -#define MCF_UART_UIMR1 (*(vuint8 *)(void*)(&__IPSBAR[0x000254])) -#define MCF_UART_UBG11 (*(vuint8 *)(void*)(&__IPSBAR[0x000258])) -#define MCF_UART_UBG21 (*(vuint8 *)(void*)(&__IPSBAR[0x00025C])) -#define MCF_UART_UIP1 (*(vuint8 *)(void*)(&__IPSBAR[0x000274])) -#define MCF_UART_UOP11 (*(vuint8 *)(void*)(&__IPSBAR[0x000278])) -#define MCF_UART_UOP01 (*(vuint8 *)(void*)(&__IPSBAR[0x00027C])) -#define MCF_UART_UMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000280])) -#define MCF_UART_USR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284])) -#define MCF_UART_UCSR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000284])) -#define MCF_UART_UCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000288])) -#define MCF_UART_URB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C])) -#define MCF_UART_UTB2 (*(vuint8 *)(void*)(&__IPSBAR[0x00028C])) -#define MCF_UART_UIPCR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290])) -#define MCF_UART_UACR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000290])) -#define MCF_UART_UISR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294])) -#define MCF_UART_UIMR2 (*(vuint8 *)(void*)(&__IPSBAR[0x000294])) -#define MCF_UART_UBG12 (*(vuint8 *)(void*)(&__IPSBAR[0x000298])) -#define MCF_UART_UBG22 (*(vuint8 *)(void*)(&__IPSBAR[0x00029C])) -#define MCF_UART_UIP2 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B4])) -#define MCF_UART_UOP12 (*(vuint8 *)(void*)(&__IPSBAR[0x0002B8])) -#define MCF_UART_UOP02 (*(vuint8 *)(void*)(&__IPSBAR[0x0002BC])) -#define MCF_UART_UMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000200+((x)*0x040)])) -#define MCF_UART_USR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)])) -#define MCF_UART_UCSR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000204+((x)*0x040)])) -#define MCF_UART_UCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000208+((x)*0x040)])) -#define MCF_UART_URB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)])) -#define MCF_UART_UTB(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00020C+((x)*0x040)])) -#define MCF_UART_UIPCR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)])) -#define MCF_UART_UACR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000210+((x)*0x040)])) -#define MCF_UART_UISR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)])) -#define MCF_UART_UIMR(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000214+((x)*0x040)])) -#define MCF_UART_UBG1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000218+((x)*0x040)])) -#define MCF_UART_UBG2(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00021C+((x)*0x040)])) -#define MCF_UART_UIP(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000234+((x)*0x040)])) -#define MCF_UART_UOP1(x) (*(vuint8 *)(void*)(&__IPSBAR[0x000238+((x)*0x040)])) -#define MCF_UART_UOP0(x) (*(vuint8 *)(void*)(&__IPSBAR[0x00023C+((x)*0x040)])) - -/* Bit definitions and macros for MCF_UART_UMR */ -#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) -#define MCF_UART_UMR_PT (0x04) -#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) -#define MCF_UART_UMR_ERR (0x20) -#define MCF_UART_UMR_RXIRQ (0x40) -#define MCF_UART_UMR_RXRTS (0x80) -#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) -#define MCF_UART_UMR_TXCTS (0x10) -#define MCF_UART_UMR_TXRTS (0x20) -#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) -#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) -#define MCF_UART_UMR_PM_MULTI_DATA (0x18) -#define MCF_UART_UMR_PM_NONE (0x10) -#define MCF_UART_UMR_PM_FORCE_HI (0x0C) -#define MCF_UART_UMR_PM_FORCE_LO (0x08) -#define MCF_UART_UMR_PM_ODD (0x04) -#define MCF_UART_UMR_PM_EVEN (0x00) -#define MCF_UART_UMR_BC_5 (0x00) -#define MCF_UART_UMR_BC_6 (0x01) -#define MCF_UART_UMR_BC_7 (0x02) -#define MCF_UART_UMR_BC_8 (0x03) -#define MCF_UART_UMR_CM_NORMAL (0x00) -#define MCF_UART_UMR_CM_ECHO (0x40) -#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) -#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) -#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) -#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) -#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) - -/* Bit definitions and macros for MCF_UART_USR */ -#define MCF_UART_USR_RXRDY (0x01) -#define MCF_UART_USR_FFULL (0x02) -#define MCF_UART_USR_TXRDY (0x04) -#define MCF_UART_USR_TXEMP (0x08) -#define MCF_UART_USR_OE (0x10) -#define MCF_UART_USR_PE (0x20) -#define MCF_UART_USR_FE (0x40) -#define MCF_UART_USR_RB (0x80) - -/* Bit definitions and macros for MCF_UART_UCSR */ -#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) -#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) -#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) -#define MCF_UART_UCSR_RCS_CTM16 (0xE0) -#define MCF_UART_UCSR_RCS_CTM (0xF0) -#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) -#define MCF_UART_UCSR_TCS_CTM16 (0x0E) -#define MCF_UART_UCSR_TCS_CTM (0x0F) - -/* Bit definitions and macros for MCF_UART_UCR */ -#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) -#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) -#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) -#define MCF_UART_UCR_NONE (0x00) -#define MCF_UART_UCR_STOP_BREAK (0x70) -#define MCF_UART_UCR_START_BREAK (0x60) -#define MCF_UART_UCR_BKCHGINT (0x50) -#define MCF_UART_UCR_RESET_ERROR (0x40) -#define MCF_UART_UCR_RESET_TX (0x30) -#define MCF_UART_UCR_RESET_RX (0x20) -#define MCF_UART_UCR_RESET_MR (0x10) -#define MCF_UART_UCR_TX_DISABLED (0x08) -#define MCF_UART_UCR_TX_ENABLED (0x04) -#define MCF_UART_UCR_RX_DISABLED (0x02) -#define MCF_UART_UCR_RX_ENABLED (0x01) - -/* Bit definitions and macros for MCF_UART_UIPCR */ -#define MCF_UART_UIPCR_CTS (0x01) -#define MCF_UART_UIPCR_COS (0x10) - -/* Bit definitions and macros for MCF_UART_UACR */ -#define MCF_UART_UACR_IEC (0x01) - -/* Bit definitions and macros for MCF_UART_UISR */ -#define MCF_UART_UISR_TXRDY (0x01) -#define MCF_UART_UISR_RXRDY_FU (0x02) -#define MCF_UART_UISR_DB (0x04) -#define MCF_UART_UISR_RXFTO (0x08) -#define MCF_UART_UISR_TXFIFO (0x10) -#define MCF_UART_UISR_RXFIFO (0x20) -#define MCF_UART_UISR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIMR */ -#define MCF_UART_UIMR_TXRDY (0x01) -#define MCF_UART_UIMR_RXRDY_FU (0x02) -#define MCF_UART_UIMR_DB (0x04) -#define MCF_UART_UIMR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIP */ -#define MCF_UART_UIP_CTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP1 */ -#define MCF_UART_UOP1_RTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP0 */ -#define MCF_UART_UOP0_RTS (0x01) - -/********************************************************************/ - -#endif /* __MCF523X_UART_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_wtm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_wtm.h deleted file mode 100644 index 1a41469aa..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf523x/mcf523x_wtm.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * File: mcf523x_wtm.h - * Purpose: Register and bit definitions for the MCF523X - * - * Notes: - * - */ - -#ifndef __MCF523X_WTM_H__ -#define __MCF523X_WTM_H__ - -/********************************************************************* -* -* Watchdog Timer Modules (WTM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_WTM_WCR (*(vuint16*)(void*)(&__IPSBAR[0x140000])) -#define MCF_WTM_WMR (*(vuint16*)(void*)(&__IPSBAR[0x140002])) -#define MCF_WTM_WCNTR (*(vuint16*)(void*)(&__IPSBAR[0x140004])) -#define MCF_WTM_WSR (*(vuint16*)(void*)(&__IPSBAR[0x140006])) - -/* Bit definitions and macros for MCF_WTM_WCR */ -#define MCF_WTM_WCR_EN (0x0001) -#define MCF_WTM_WCR_HALTED (0x0002) -#define MCF_WTM_WCR_DOZE (0x0004) -#define MCF_WTM_WCR_WAIT (0x0008) - -/* Bit definitions and macros for MCF_WTM_WMR */ -#define MCF_WTM_WMR_WM0 (0x0001) -#define MCF_WTM_WMR_WM1 (0x0002) -#define MCF_WTM_WMR_WM2 (0x0004) -#define MCF_WTM_WMR_WM3 (0x0008) -#define MCF_WTM_WMR_WM4 (0x0010) -#define MCF_WTM_WMR_WM5 (0x0020) -#define MCF_WTM_WMR_WM6 (0x0040) -#define MCF_WTM_WMR_WM7 (0x0080) -#define MCF_WTM_WMR_WM8 (0x0100) -#define MCF_WTM_WMR_WM9 (0x0200) -#define MCF_WTM_WMR_WM10 (0x0400) -#define MCF_WTM_WMR_WM11 (0x0800) -#define MCF_WTM_WMR_WM12 (0x1000) -#define MCF_WTM_WMR_WM13 (0x2000) -#define MCF_WTM_WMR_WM14 (0x4000) -#define MCF_WTM_WMR_WM15 (0x8000) - -/* Bit definitions and macros for MCF_WTM_WCNTR */ -#define MCF_WTM_WCNTR_WC0 (0x0001) -#define MCF_WTM_WCNTR_WC1 (0x0002) -#define MCF_WTM_WCNTR_WC2 (0x0004) -#define MCF_WTM_WCNTR_WC3 (0x0008) -#define MCF_WTM_WCNTR_WC4 (0x0010) -#define MCF_WTM_WCNTR_WC5 (0x0020) -#define MCF_WTM_WCNTR_WC6 (0x0040) -#define MCF_WTM_WCNTR_WC7 (0x0080) -#define MCF_WTM_WCNTR_WC8 (0x0100) -#define MCF_WTM_WCNTR_WC9 (0x0200) -#define MCF_WTM_WCNTR_WC10 (0x0400) -#define MCF_WTM_WCNTR_WC11 (0x0800) -#define MCF_WTM_WCNTR_WC12 (0x1000) -#define MCF_WTM_WCNTR_WC13 (0x2000) -#define MCF_WTM_WCNTR_WC14 (0x4000) -#define MCF_WTM_WCNTR_WC15 (0x8000) - -/* Bit definitions and macros for MCF_WTM_WSR */ -#define MCF_WTM_WSR_WS0 (0x0001) -#define MCF_WTM_WSR_WS1 (0x0002) -#define MCF_WTM_WSR_WS2 (0x0004) -#define MCF_WTM_WSR_WS3 (0x0008) -#define MCF_WTM_WSR_WS4 (0x0010) -#define MCF_WTM_WSR_WS5 (0x0020) -#define MCF_WTM_WSR_WS6 (0x0040) -#define MCF_WTM_WSR_WS7 (0x0080) -#define MCF_WTM_WSR_WS8 (0x0100) -#define MCF_WTM_WSR_WS9 (0x0200) -#define MCF_WTM_WSR_WS10 (0x0400) -#define MCF_WTM_WSR_WS11 (0x0800) -#define MCF_WTM_WSR_WS12 (0x1000) -#define MCF_WTM_WSR_WS13 (0x2000) -#define MCF_WTM_WSR_WS14 (0x4000) -#define MCF_WTM_WSR_WS15 (0x8000) - -/********************************************************************/ - -#endif /* __MCF523X_WTM_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf5xxx.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf5xxx.h deleted file mode 100644 index 6550ddb9e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/include/arch/mcf5xxx.h +++ /dev/null @@ -1,190 +0,0 @@ -/* - * File: mcf5xxx.h - * Purpose: Definitions common to all ColdFire processors - * - * Notes: - */ - -#ifndef _CPU_MCF5XXX_H -#define _CPU_MCF5XXX_H - -/***********************************************************************/ -/* - * Misc. Defines - */ - -#ifdef FALSE -#undef FALSE -#endif -#define FALSE (0) - -#ifdef TRUE -#undef TRUE -#endif -#define TRUE (1) - -#ifdef NULL -#undef NULL -#endif -#define NULL (0) - -/***********************************************************************/ -/* - * The basic data types - */ - -typedef unsigned char uint8; /* 8 bits */ -typedef unsigned short int uint16; /* 16 bits */ -typedef unsigned long int uint32; /* 32 bits */ - -typedef signed char int8; /* 8 bits */ -typedef signed short int int16; /* 16 bits */ -typedef signed long int int32; /* 32 bits */ - -typedef volatile uint8 vuint8; /* 8 bits */ -typedef volatile uint16 vuint16; /* 16 bits */ -typedef volatile uint32 vuint32; /* 32 bits */ - -/***********************************************************************/ -/* - * Common M68K & ColdFire definitions - */ - -#define ADDRESS uint32 -#define INSTRUCTION uint16 -#define ILLEGAL 0x4AFC -#define CPU_WORD_SIZE 16 - -#define MCF5XXX_SR_T (0x8000) -#define MCF5XXX_SR_S (0x2000) -#define MCF5XXX_SR_M (0x1000) -#define MCF5XXX_SR_IPL (0x0700) -#define MCF5XXX_SR_IPL_0 (0x0000) -#define MCF5XXX_SR_IPL_1 (0x0100) -#define MCF5XXX_SR_IPL_2 (0x0200) -#define MCF5XXX_SR_IPL_3 (0x0300) -#define MCF5XXX_SR_IPL_4 (0x0400) -#define MCF5XXX_SR_IPL_5 (0x0500) -#define MCF5XXX_SR_IPL_6 (0x0600) -#define MCF5XXX_SR_IPL_7 (0x0700) -#define MCF5XXX_SR_X (0x0010) -#define MCF5XXX_SR_N (0x0008) -#define MCF5XXX_SR_Z (0x0004) -#define MCF5XXX_SR_V (0x0002) -#define MCF5XXX_SR_C (0x0001) - -#define MCF5XXX_CACR_CENB (0x80000000) -#define MCF5XXX_CACR_CPDI (0x10000000) -#define MCF5XXX_CACR_CPD (0x10000000) -#define MCF5XXX_CACR_CFRZ (0x08000000) -#define MCF5XXX_CACR_CINV (0x01000000) -#define MCF5XXX_CACR_DIDI (0x00800000) -#define MCF5XXX_CACR_DISD (0x00400000) -#define MCF5XXX_CACR_INVI (0x00200000) -#define MCF5XXX_CACR_INVD (0x00100000) -#define MCF5XXX_CACR_CEIB (0x00000400) -#define MCF5XXX_CACR_DCM_WR (0x00000000) -#define MCF5XXX_CACR_DCM_CB (0x00000100) -#define MCF5XXX_CACR_DCM_IP (0x00000200) -#define MCF5XXX_CACR_DCM (0x00000200) -#define MCF5XXX_CACR_DCM_II (0x00000300) -#define MCF5XXX_CACR_DBWE (0x00000100) -#define MCF5XXX_CACR_DWP (0x00000020) -#define MCF5XXX_CACR_EUST (0x00000010) -#define MCF5XXX_CACR_CLNF_00 (0x00000000) -#define MCF5XXX_CACR_CLNF_01 (0x00000002) -#define MCF5XXX_CACR_CLNF_10 (0x00000004) -#define MCF5XXX_CACR_CLNF_11 (0x00000006) - -#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000) -#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8) -#define MCF5XXX_ACR_EN (0x00008000) -#define MCF5XXX_ACR_SM_USER (0x00000000) -#define MCF5XXX_ACR_SM_SUPER (0x00002000) -#define MCF5XXX_ACR_SM_IGNORE (0x00006000) -#define MCF5XXX_ACR_ENIB (0x00000080) -#define MCF5XXX_ACR_CM (0x00000040) -#define MCF5XXX_ACR_DCM_WR (0x00000000) -#define MCF5XXX_ACR_DCM_CB (0x00000020) -#define MCF5XXX_ACR_DCM_IP (0x00000040) -#define MCF5XXX_ACR_DCM_II (0x00000060) -#define MCF5XXX_ACR_CM (0x00000040) -#define MCF5XXX_ACR_BWE (0x00000020) -#define MCF5XXX_ACR_WP (0x00000004) - -#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000) -#define MCF5XXX_RAMBAR_PRI_00 (0x00000000) -#define MCF5XXX_RAMBAR_PRI_01 (0x00004000) -#define MCF5XXX_RAMBAR_PRI_10 (0x00008000) -#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000) -#define MCF5XXX_RAMBAR_WP (0x00000100) -#define MCF5XXX_RAMBAR_CI (0x00000020) -#define MCF5XXX_RAMBAR_SC (0x00000010) -#define MCF5XXX_RAMBAR_SD (0x00000008) -#define MCF5XXX_RAMBAR_UC (0x00000004) -#define MCF5XXX_RAMBAR_UD (0x00000002) -#define MCF5XXX_RAMBAR_V (0x00000001) - -/***********************************************************************/ -/* - * The ColdFire family of processors has a simplified exception stack - * frame that looks like the following: - * - * 3322222222221111 111111 - * 1098765432109876 5432109876543210 - * 8 +----------------+----------------+ - * | Program Counter | - * 4 +----------------+----------------+ - * |FS/Fmt/Vector/FS| SR | - * SP --> 0 +----------------+----------------+ - * - * The stack self-aligns to a 4-byte boundary at an exception, with - * the FS/Fmt/Vector/FS field indicating the size of the adjustment - * (SP += 0,1,2,3 bytes). - */ - -#define MCF5XXX_RD_SF_FORMAT(PTR) \ - ((*((uint16 *)(PTR)) >> 12) & 0x00FF) - -#define MCF5XXX_RD_SF_VECTOR(PTR) \ - ((*((uint16 *)(PTR)) >> 2) & 0x00FF) - -#define MCF5XXX_RD_SF_FS(PTR) \ - ( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) ) - -#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1) -#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1) - -/********************************************************************/ -/* - * Functions provided by mcf5xxx.s - */ - -int asm_set_ipl (uint32); -void mcf5xxx_wr_cacr (uint32); -void mcf5xxx_wr_acr0 (uint32); -void mcf5xxx_wr_acr1 (uint32); -void mcf5xxx_wr_acr2 (uint32); -void mcf5xxx_wr_acr3 (uint32); -void mcf5xxx_wr_other_a7 (uint32); -void mcf5xxx_wr_other_sp (uint32); -void mcf5xxx_wr_vbr (uint32); -void mcf5xxx_wr_macsr (uint32); -void mcf5xxx_wr_mask (uint32); -void mcf5xxx_wr_acc0 (uint32); -void mcf5xxx_wr_accext01 (uint32); -void mcf5xxx_wr_accext23 (uint32); -void mcf5xxx_wr_acc1 (uint32); -void mcf5xxx_wr_acc2 (uint32); -void mcf5xxx_wr_acc3 (uint32); -void mcf5xxx_wr_sr (uint32); -void mcf5xxx_wr_rambar0 (uint32); -void mcf5xxx_wr_rambar1 (uint32); -void mcf5xxx_wr_mbar (uint32); -void mcf5xxx_wr_mbar0 (uint32); -void mcf5xxx_wr_mbar1 (uint32); - -/********************************************************************/ - -#endif /* _CPU_MCF5XXX_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/CHANGELOG b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/CHANGELOG deleted file mode 100644 index 0bf28ac56..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/CHANGELOG +++ /dev/null @@ -1,596 +0,0 @@ -FUTURE - - * TODO: The lwIP source code makes some invalid assumptions on processor - word-length, storage sizes and alignment. See the mailing lists for - problems with exoteric (/DSP) architectures showing these problems. - We still have to fix some of these issues neatly. - - * TODO: the ARP layer is not protected against concurrent access. If - you run from a multitasking OS, serialize access to ARP (called from - your network device driver and from a timeout thread.) - - * TODO: the PPP code is broken in a few ways. There are namespace - collisions on BSD systems and many assumptions on word-length - (sizeof(int)). In ppp.c an assumption is made on the availability of - a thread subsystem. Either PPP needs to be moved to contrib/ports/??? - or rearranged to be more generic. - -HISTORY - -(CVS HEAD) - - * [New changes go here] - -(STABLE-1_1_1) - - 2006-03-03 Christiaan Simons - * ipv4/ip_frag.c: Added bound-checking assertions on ip_reassbitmap - access and added pbuf_alloc() return value checks. - - 2006-01-01 Leon Woestenberg - * tcp_{in,out}.c, tcp_out.c: Removed 'even sndbuf' fix in TCP, which is - now handled by the checksum routine properly. - - 2006-02-27 Leon Woestenberg - * pbuf.c: Fix alignment; pbuf_init() would not work unless - pbuf_pool_memory[] was properly aligned. (Patch by Curt McDowell.) - - 2005-12-20 Leon Woestenberg - * tcp.c: Remove PCBs which stay in LAST_ACK state too long. Patch - submitted by Mitrani Hiroshi. - - 2005-12-15 Christiaan Simons - * inet.c: Disabled the added summing routine to preserve code space. - - 2005-12-14 Leon Woestenberg - * tcp_in.c: Duplicate FIN ACK race condition fix by Kelvin Lawson. - Added Curt McDowell's optimized checksumming routine for future - inclusion. Need to create test case for unaliged, aligned, odd, - even length combination of cases on various endianess machines. - - 2005-12-09 Christiaan Simons - * inet.c: Rewrote standard checksum routine in proper portable C. - - 2005-11-25 Christiaan Simons - * udp.c tcp.c: Removed SO_REUSE hack. Should reside in socket code only. - * *.c: introduced cc.h LWIP_DEBUG formatters matching the u16_t, s16_t, - u32_t, s32_t typedefs. This solves most debug word-length assumes. - - 2005-07-17 Leon Woestenberg - * inet.c: Fixed unaligned 16-bit access in the standard checksum - routine by Peter Jolasson. - * slipif.c: Fixed implementation assumption of single-pbuf datagrams. - - 2005-02-04 Leon Woestenberg - * tcp_out.c: Fixed uninitialized 'queue' referenced in memerr branch. - * tcp_{out|in}.c: Applied patch fixing unaligned access. - - 2005-01-04 Leon Woestenberg - * pbuf.c: Fixed missing semicolon after LWIP_DEBUG statement. - - 2005-01-03 Leon Woestenberg - * udp.c: UDP pcb->recv() was called even when it was NULL. - -(STABLE-1_1_0) - - 2004-12-28 Leon Woestenberg - * etharp.*: Disabled multiple packets on the ARP queue. - This clashes with TCP queueing. - - 2004-11-28 Leon Woestenberg - * etharp.*: Fixed race condition from ARP request to ARP timeout. - Halved the ARP period, doubled the period counts. - ETHARP_MAX_PENDING now should be at least 2. This prevents - the counter from reaching 0 right away (which would allow - too little time for ARP responses to be received). - - 2004-11-25 Leon Woestenberg - * dhcp.c: Decline messages were not multicast but unicast. - * etharp.c: ETHARP_CREATE is renamed to ETHARP_TRY_HARD. - Do not try hard to insert arbitrary packet's source address, - etharp_ip_input() now calls etharp_update() without ETHARP_TRY_HARD. - etharp_query() now always DOES call ETHARP_TRY_HARD so that users - querying an address will see it appear in the cache (DHCP could - suffer from this when a server invalidly gave an in-use address.) - * ipv4/ip_addr.h: Renamed ip_addr_maskcmp() to _netcmp() as we are - comparing network addresses (identifiers), not the network masks - themselves. - * ipv4/ip_addr.c: ip_addr_isbroadcast() now checks that the given - IP address actually belongs to the network of the given interface. - - 2004-11-24 Kieran Mansley - * tcp.c: Increment pcb->snd_buf when ACK is received in SYN_SENT state. - -(STABLE-1_1_0-RC1) - - 2004-10-16 Kieran Mansley - * tcp.c: Add code to tcp_recved() to send an ACK (window update) immediately, - even if one is already pending, if the rcv_wnd is above a threshold - (currently TCP_WND/2). This avoids waiting for a timer to expire to send a - delayed ACK in order to open the window if the stack is only receiving data. - - 2004-09-12 Kieran Mansley - * tcp*.*: Retransmit time-out handling improvement by Sam Jansen. - - 2004-08-20 Tony Mountifield - * etharp.c: Make sure the first pbuf queued on an ARP entry - is properly ref counted. - - 2004-07-27 Tony Mountifield - * debug.h: Added (int) cast in LWIP_DEBUGF() to avoid compiler - warnings about comparison. - * pbuf.c: Stopped compiler complaining of empty if statement - when LWIP_DEBUGF() empty. Closed an unclosed comment. - * tcp.c: Stopped compiler complaining of empty if statement - when LWIP_DEBUGF() empty. - * ip.h Corrected IPH_TOS() macro: returns a byte, so doesn't need htons(). - * inet.c: Added a couple of casts to quiet the compiler. - No need to test isascii(c) before isdigit(c) or isxdigit(c). - - 2004-07-22 Tony Mountifield - * inet.c: Made data types consistent in inet_ntoa(). - Added casts for return values of checksum routines, to pacify compiler. - * ip_frag.c, tcp_out.c, sockets.c, pbuf.c - Small corrections to some debugging statements, to pacify compiler. - - 2004-07-21 Tony Mountifield - * etharp.c: Removed spurious semicolon and added missing end-of-comment. - * ethernetif.c Updated low_level_output() to match prototype for - netif->linkoutput and changed low_level_input() similarly for consistency. - * api_msg.c: Changed recv_raw() from int to u8_t, to match prototype - of raw_recv() in raw.h and so avoid compiler error. - * sockets.c: Added trivial (int) cast to keep compiler happier. - * ip.c, netif.c Changed debug statements to use the tidier ip4_addrN() macros. - -(STABLE-1_0_0) - - ++ Changes: - - 2004-07-05 Leon Woestenberg - * sockets.*: Restructured LWIP_PRIVATE_TIMEVAL. Make sure - your cc.h file defines this either 1 or 0. If non-defined, - defaults to 1. - * .c: Added and includes where used. - * etharp.c: Made some array indices unsigned. - - 2004-06-27 Leon Woestenberg - * netif.*: Added netif_set_up()/down(). - * dhcp.c: Changes to restart program flow. - - 2004-05-07 Leon Woestenberg - * etharp.c: In find_entry(), instead of a list traversal per candidate, do a - single-pass lookup for different candidates. Should exploit locality. - - 2004-04-29 Leon Woestenberg - * tcp*.c: Cleaned up source comment documentation for Doxygen processing. - * opt.h: ETHARP_ALWAYS_INSERT option removed to comply with ARP RFC. - * etharp.c: update_arp_entry() only adds new ARP entries when adviced to by - the caller. This deprecates the ETHARP_ALWAYS_INSERT overrule option. - - ++ Bug fixes: - - 2004-04-27 Leon Woestenberg - * etharp.c: Applied patch of bug #8708 by Toni Mountifield with a solution - suggested by Timmy Brolin. Fix for 32-bit processors that cannot access - non-aligned 32-bit words, such as soms 32-bit TCP/IP header fields. Fix - is to prefix the 14-bit Ethernet headers with two padding bytes. - - 2004-04-23 Leon Woestenberg - * ip_addr.c: Fix in the ip_addr_isbroadcast() check. - * etharp.c: Fixed the case where the packet that initiates the ARP request - is not queued, and gets lost. Fixed the case where the packets destination - address is already known; we now always queue the packet and perform an ARP - request. - -(STABLE-0_7_0) - - ++ Bug fixes: - - * Fixed TCP bug for SYN_SENT to ESTABLISHED state transition. - * Fixed TCP bug in dequeueing of FIN from out of order segment queue. - * Fixed two possible NULL references in rare cases. - -(STABLE-0_6_6) - - ++ Bug fixes: - - * Fixed DHCP which did not include the IP address in DECLINE messages. - - ++ Changes: - - * etharp.c has been hauled over a bit. - -(STABLE-0_6_5) - - ++ Bug fixes: - - * Fixed TCP bug induced by bad window resizing with unidirectional TCP traffic. - * Packets sent from ARP queue had invalid source hardware address. - - ++ Changes: - - * Pass-by ARP requests do now update the cache. - - ++ New features: - - * No longer dependent on ctype.h. - * New socket options. - * Raw IP pcb support. - -(STABLE-0_6_4) - - ++ Bug fixes: - - * Some debug formatters and casts fixed. - * Numereous fixes in PPP. - - ++ Changes: - - * DEBUGF now is LWIP_DEBUGF - * pbuf_dechain() has been re-enabled. - * Mentioned the changed use of CVS branches in README. - -(STABLE-0_6_3) - - ++ Bug fixes: - - * Fixed pool pbuf memory leak in pbuf_alloc(). - Occured if not enough PBUF_POOL pbufs for a packet pbuf chain. - Reported by Savin Zlobec. - - * PBUF_POOL chains had their tot_len field not set for non-first - pbufs. Fixed in pbuf_alloc(). - - ++ New features: - - * Added PPP stack contributed by Marc Boucher - - ++ Changes: - - * Now drops short packets for ICMP/UDP/TCP protocols. More robust. - - * ARP queueuing now queues the latest packet instead of the first. - This is the RFC recommended behaviour, but can be overridden in - lwipopts.h. - -(0.6.2) - - ++ Bugfixes: - - * TCP has been fixed to deal with the new use of the pbuf->ref - counter. - - * DHCP dhcp_inform() crash bug fixed. - - ++ Changes: - - * Removed pbuf_pool_free_cache and pbuf_pool_alloc_cache. Also removed - pbuf_refresh(). This has sped up pbuf pool operations considerably. - Implemented by David Haas. - -(0.6.1) - - ++ New features: - - * The packet buffer implementation has been enhanced to support - zero-copy and copy-on-demand for packet buffers which have their - payloads in application-managed memory. - Implemented by David Haas. - - Use PBUF_REF to make a pbuf refer to RAM. lwIP will use zero-copy - if an outgoing packet can be directly sent on the link, or perform - a copy-on-demand when necessary. - - The application can safely assume the packet is sent, and the RAM - is available to the application directly after calling udp_send() - or similar function. - - ++ Bugfixes: - - * ARP_QUEUEING should now correctly work for all cases, including - PBUF_REF. - Implemented by Leon Woestenberg. - - ++ Changes: - - * IP_ADDR_ANY is no longer a NULL pointer. Instead, it is a pointer - to a '0.0.0.0' IP address. - - * The packet buffer implementation is changed. The pbuf->ref counter - meaning has changed, and several pbuf functions have been - adapted accordingly. - - * netif drivers have to be changed to set the hardware address length field - that must be initialized correctly by the driver (hint: 6 for Ethernet MAC). - See the contrib/ports/c16x cs8900 driver as a driver example. - - * netif's have a dhcp field that must be initialized to NULL by the driver. - See the contrib/ports/c16x cs8900 driver as a driver example. - -(0.5.x) This file has been unmaintained up to 0.6.1. All changes are - logged in CVS but have not been explained here. - -(0.5.3) Changes since version 0.5.2 - - ++ Bugfixes: - - * memp_malloc(MEMP_API_MSG) could fail with multiple application - threads because it wasn't protected by semaphores. - - ++ Other changes: - - * struct ip_addr now packed. - - * The name of the time variable in arp.c has been changed to ctime - to avoid conflicts with the time() function. - -(0.5.2) Changes since version 0.5.1 - - ++ New features: - - * A new TCP function, tcp_tmr(), now handles both TCP timers. - - ++ Bugfixes: - - * A bug in tcp_parseopt() could cause the stack to hang because of a - malformed TCP option. - - * The address of new connections in the accept() function in the BSD - socket library was not handled correctly. - - * pbuf_dechain() did not update the ->tot_len field of the tail. - - * Aborted TCP connections were not handled correctly in all - situations. - - ++ Other changes: - - * All protocol header structs are now packed. - - * The ->len field in the tcp_seg structure now counts the actual - amount of data, and does not add one for SYN and FIN segments. - -(0.5.1) Changes since version 0.5.0 - - ++ New features: - - * Possible to run as a user process under Linux. - - * Preliminary support for cross platform packed structs. - - * ARP timer now implemented. - - ++ Bugfixes: - - * TCP output queue length was badly initialized when opening - connections. - - * TCP delayed ACKs were not sent correctly. - - * Explicit initialization of BSS segment variables. - - * read() in BSD socket library could drop data. - - * Problems with memory alignment. - - * Situations when all TCP buffers were used could lead to - starvation. - - * TCP MSS option wasn't parsed correctly. - - * Problems with UDP checksum calculation. - - * IP multicast address tests had endianess problems. - - * ARP requests had wrong destination hardware address. - - ++ Other changes: - - * struct eth_addr changed from u16_t[3] array to u8_t[6]. - - * A ->linkoutput() member was added to struct netif. - - * TCP and UDP ->dest_* struct members where changed to ->remote_*. - - * ntoh* macros are now null definitions for big endian CPUs. - -(0.5.0) Changes since version 0.4.2 - - ++ New features: - - * Redesigned operating system emulation layer to make porting easier. - - * Better control over TCP output buffers. - - * Documenation added. - - ++ Bugfixes: - - * Locking issues in buffer management. - - * Bugfixes in the sequential API. - - * IP forwarding could cause memory leakage. This has been fixed. - - ++ Other changes: - - * Directory structure somewhat changed; the core/ tree has been - collapsed. - -(0.4.2) Changes since version 0.4.1 - - ++ New features: - - * Experimental ARP implementation added. - - * Skeleton Ethernet driver added. - - * Experimental BSD socket API library added. - - ++ Bugfixes: - - * In very intense situations, memory leakage could occur. This has - been fixed. - - ++ Other changes: - - * Variables named "data" and "code" have been renamed in order to - avoid name conflicts in certain compilers. - - * Variable++ have in appliciable cases been translated to ++variable - since some compilers generate better code in the latter case. - -(0.4.1) Changes since version 0.4 - - ++ New features: - - * TCP: Connection attempts time out earlier than data - transmissions. Nagle algorithm implemented. Push flag set on the - last segment in a burst. - - * UDP: experimental support for UDP-Lite extensions. - - ++ Bugfixes: - - * TCP: out of order segments were in some cases handled incorrectly, - and this has now been fixed. Delayed acknowledgements was broken - in 0.4, has now been fixed. Binding to an address that is in use - now results in an error. Reset connections sometimes hung an - application; this has been fixed. - - * Checksum calculation sometimes failed for chained pbufs with odd - lengths. This has been fixed. - - * API: a lot of bug fixes in the API. The UDP API has been improved - and tested. Error reporting and handling has been - improved. Logical flaws and race conditions for incoming TCP - connections has been found and removed. - - * Memory manager: alignment issues. Reallocating memory sometimes - failed, this has been fixed. - - * Generic library: bcopy was flawed and has been fixed. - - ++ Other changes: - - * API: all datatypes has been changed from generic ones such as - ints, to specified ones such as u16_t. Functions that return - errors now have the correct type (err_t). - - * General: A lot of code cleaned up and debugging code removed. Many - portability issues have been fixed. - - * The license was changed; the advertising clause was removed. - - * C64 port added. - - * Thanks: Huge thanks go to Dagan Galarneau, Horst Garnetzke, Petri - Kosunen, Mikael Caleres, and Frits Wilmink for reporting and - fixing bugs! - -(0.4) Changes since version 0.3.1 - - * Memory management has been radically changed; instead of - allocating memory from a shared heap, memory for objects that are - rapidly allocated and deallocated is now kept in pools. Allocation - and deallocation from those memory pools is very fast. The shared - heap is still present but is used less frequently. - - * The memory, memory pool, and packet buffer subsystems now support - 4-, 2-, or 1-byte alignment. - - * "Out of memory" situations are handled in a more robust way. - - * Stack usage has been reduced. - - * Easier configuration of lwIP parameters such as memory usage, - TTLs, statistics gathering, etc. All configuration parameters are - now kept in a single header file "lwipopts.h". - - * The directory structure has been changed slightly so that all - architecture specific files are kept under the src/arch - hierarchy. - - * Error propagation has been improved, both in the protocol modules - and in the API. - - * The code for the RTXC architecture has been implemented, tested - and put to use. - - * Bugs have been found and corrected in the TCP, UDP, IP, API, and - the Internet checksum modules. - - * Bugs related to porting between a 32-bit and a 16-bit architecture - have been found and corrected. - - * The license has been changed slightly to conform more with the - original BSD license, including the advertisement clause. - -(0.3.1) Changes since version 0.3 - - * Fix of a fatal bug in the buffer management. Pbufs with allocated - RAM never returned the RAM when the pbuf was deallocated. - - * TCP congestion control, window updates and retransmissions did not - work correctly. This has now been fixed. - - * Bugfixes in the API. - -(0.3) Changes since version 0.2 - - * New and improved directory structure. All include files are now - kept in a dedicated include/ directory. - - * The API now has proper error handling. A new function, - netconn_err(), now returns an error code for the connection in - case of errors. - - * Improvements in the memory management subsystem. The system now - keeps a pointer to the lowest free memory block. A new function, - mem_malloc2() tries to allocate memory once, and if it fails tries - to free some memory and retry the allocation. - - * Much testing has been done with limited memory - configurations. lwIP now does a better job when overloaded. - - * Some bugfixes and improvements to the buffer (pbuf) subsystem. - - * Many bugfixes in the TCP code: - - - Fixed a bug in tcp_close(). - - - The TCP receive window was incorrectly closed when out of - sequence segments was received. This has been fixed. - - - Connections are now timed-out of the FIN-WAIT-2 state. - - - The initial congestion window could in some cases be too - large. This has been fixed. - - - The retransmission queue could in some cases be screwed up. This - has been fixed. - - - TCP RST flag now handled correctly. - - - Out of sequence data was in some cases never delivered to the - application. This has been fixed. - - - Retransmitted segments now contain the correct acknowledgment - number and advertised window. - - - TCP retransmission timeout backoffs are not correctly computed - (ala BSD). After a number of retransmissions, TCP now gives up - the connection. - - * TCP connections now are kept on three lists, one for active - connections, one for listening connections, and one for - connections that are in TIME-WAIT. This greatly speeds up the fast - timeout processing for sending delayed ACKs. - - * TCP now provides proper feedback to the application when a - connection has been successfully set up. - - * More comments have been added to the code. The code has also been - somewhat cleaned up. - -(0.2) Initial public release. diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/COPYING b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/COPYING deleted file mode 100644 index e23898b5e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/COPYING +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2001, 2002 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/FILES b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/FILES deleted file mode 100644 index 66253196f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/FILES +++ /dev/null @@ -1,4 +0,0 @@ -src/ - The source code for the lwIP TCP/IP stack. -doc/ - The documentation for lwIP. - -See also the FILES file in each subdirectory. diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/README b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/README deleted file mode 100644 index d9102826f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/README +++ /dev/null @@ -1,74 +0,0 @@ -INTRODUCTION - -lwIP is a small independent implementation of the TCP/IP protocol -suite that has been developed by Adam Dunkels at the Computer and -Networks Architectures (CNA) lab at the Swedish Institute of Computer -Science (SICS). - -The focus of the lwIP TCP/IP implementation is to reduce the RAM usage -while still having a full scale TCP. This making lwIP suitable for use -in embedded systems with tens of kilobytes of free RAM and room for -around 40 kilobytes of code ROM. - -FEATURES - - * IP (Internet Protocol) including packet forwarding over multiple - network interfaces - * ICMP (Internet Control Message Protocol) for network maintenance - and debugging - * UDP (User Datagram Protocol) including experimental UDP-lite - extensions - * TCP (Transmission Control Protocol) with congestion control, RTT - estimation and fast recovery/fast retransmit - * Specialized API for enhanced performance - * Optional Berkeley socket API - -LICENSE - -lwIP is freely available under a BSD license. - -DEVELOPMENT - -lwIP has grown into an excellent TCP/IP stack for embedded devices, -and developers using the stack often submit bug fixes, improvements, -and additions to the stack to further increase its usefulness. - -Development of lwIP is hosted on Savannah, a central point for -software development, maintenance and distribution. Everyone can -help improve lwIP by use of Savannah's interface, CVS and the -mailing list. A core team of developers will commit changes to the -CVS source tree. - -The lwIP TCP/IP stack is maintained in the 'lwip' CVS module and -contributions (such as platform ports) are in the 'contrib' module. - -See doc/savannah.txt for details on CVS server access for users and -developers. - -Last night's CVS tar ball can be downloaded from: - http://savannah.gnu.org/cvs.backups/lwip.tar.gz [CHANGED - NEEDS FIXING] - -The current CVS trees are web-browsable: - http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/lwip/ - http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/contrib/ - -Submit patches and bugs via the lwIP project page: - http://savannah.nongnu.org/projects/lwip/ - - -DOCUMENTATION - -The original out-dated homepage of lwIP and Adam Dunkels' papers on -lwIP are at the official lwIP home page: - http://www.sics.se/~adam/lwip/ - -Self documentation of the source code is regularly extracted from the -current CVS sources and is available from this web page: - http://www.nongnu.org/lwip/ - -Reading Adam's papers, the files in docs/, browsing the source code -documentation and browsing the mailing list archives is a good way to -become familiar with the design of lwIP. - -Adam Dunkels -Leon Woestenberg diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/arch/cc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/arch/cc.h deleted file mode 100644 index ef9214000..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/arch/cc.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * Modifcations: Christian Walter - */ -#ifndef __CC_H__ -#define __CC_H__ - -/* ------------------------ System includes ------------------------------- */ -#include - -/* ------------------------ Project includes ------------------------------ */ -#include "cpu.h" -#include "sys_arch.h" - -/* ------------------------ Defines --------------------------------------- */ - -#define PACK_STRUCT_BEGIN -#define PACK_STRUCT_STRUCT __attribute__ ((__packed__)) -#define PACK_STRUCT_END - -#define PACK_STRUCT_FIELD( x ) x - -#define ALIGN_STRUCT_8_BEGIN -#define ALIGN_STRUCT_8 __attribute__ ((aligned (8))) -#define ALIGN_STRUCT_8_END - -#define LWIP_PLATFORM_ASSERT( x ) sys_assert( x ) -#define LWIP_PLATFORM_DIAG( x, ... ) do{ sys_debug x; } while( 0 ); - -/* Define (sn)printf formatters for these lwIP types */ -#define U16_F "hu" -#define S16_F "hd" -#define X16_F "hx" -#define U32_F "lu" -#define S32_F "ld" -#define X32_F "lx" - -/* ------------------------ Type definitions ------------------------------ */ -typedef unsigned char u8_t; -typedef signed char s8_t; -typedef unsigned short u16_t; -typedef signed short s16_t; -typedef unsigned long u32_t; -typedef signed long s32_t; -typedef u32_t mem_ptr_t; -typedef int sys_prot_t; - -/* ------------------------ Prototypes ------------------------------------ */ - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/arch/cpu.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/arch/cpu.h deleted file mode 100644 index 743f80810..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/arch/cpu.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __CPU_H__ -#define __CPU_H__ - -/* ------------------------ Defines --------------------------------------- */ -#define BYTE_ORDER BIG_ENDIAN - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/arch/perf.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/arch/perf.h deleted file mode 100644 index f94640e9f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/arch/perf.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __PERF_H__ -#define __PERF_H__ - -/* ------------------------ Defines --------------------------------------- */ -#define PERF_START /* null definition */ -#define PERF_STOP(x) /* null definition */ - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/arch/sys_arch.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/arch/sys_arch.h deleted file mode 100644 index 721965e22..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/arch/sys_arch.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __SYS_ARCH_H__ -#define __SYS_ARCH_H__ - -/* ------------------------ Project includes ------------------------------ */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "semphr.h" - -/* ------------------------ Defines --------------------------------------- */ -#define SYS_MBOX_NULL ( xQueueHandle )0 -#define SYS_THREAD_NULL NULL -#define SYS_SEM_NULL ( xSemaphoreHandle )0 -#define SIO_FD_NULL ( sio_fd_t )NULL - -/* ------------------------ Type definitions ------------------------------ */ -typedef xSemaphoreHandle sys_sem_t; -typedef xQueueHandle sys_mbox_t; -typedef xTaskHandle sys_thread_t; - -/* ------------------------ Prototypes ------------------------------------ */ -sys_thread_t sys_arch_thread_new( void ( *thread ) ( void *arg ), void *arg, - int prio, size_t ssize ); -sys_thread_t sys_arch_thread_current( void ); -void sys_arch_thread_remove( sys_thread_t hdl ); -void sys_assert( const char *const msg ); -void sys_debug( const char *const fmt, ... ); - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.c deleted file mode 100644 index 948405688..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.c +++ /dev/null @@ -1,581 +0,0 @@ -/* - * Copyright (c) 2006 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Christian Walter - * - * TODO: - * - Introduce another task create function in the sys_arch layer which allows - * for passing the stack size. - * - Avoid copying the buffers - this requires changeing the nbuf driver code - * to use the lwIP pbuf buffer implementation. - * - * File: $Id$ - */ - -/* ------------------------ System includes ------------------------------- */ -#include - -/* ------------------------ Platform includes ----------------------------- */ -#include "mcf5xxx.h" -#include "mcf523x.h" - -#include "nbuf.h" - -/* ------------------------ lwIP includes --------------------------------- */ -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include "lwip/stats.h" -#include "lwip/debug.h" -#include "netif/etharp.h" - -/* ------------------------ Defines --------------------------------------- */ -#ifdef FEC_DEBUG -#define FEC_DEBUG_INIT \ - do \ - { \ - MCF_GPIO_PDDR_FECI2C = ( MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 | \ - MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 ); \ - } while( 0 ) - -#define FEC_DEBUG_RX_TIMING( x ) \ - do \ - { \ - if( x ) \ - MCF_GPIO_PPDSDR_FECI2C = MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0; \ - else \ - MCF_GPIO_PCLRR_FECI2C = ~( MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 ); \ - } while( 0 ) - -#define FEC_DEBUG_TX_TIMING( x ) \ - do \ - { \ - if( x ) \ - MCF_GPIO_PPDSDR_FECI2C = MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1; \ - else \ - MCF_GPIO_PCLRR_FECI2C = ~( MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 ); \ - } while( 0 ) - -#else -#define FEC_DEBUG DBG_OFF -#define FEC_DEBUG_INIT -#define FEC_DEBUG_RX_TIMING( x ) -#define FEC_DEBUG_TX_TIMING( x ) -#endif - -#define MCF_FEC_INT_LEVEL ( 6 ) -#define MCF_FEC_INT_PRIORITY ( 0 ) -#define MCF_FEC_VEC_RXF ( 64 + 27 ) -#define MCF_FEC_MTU ( 1518 ) - -#define ETH_ADDR_LEN ( 6 ) - -#define TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) - -/* ------------------------ Type definitions ------------------------------ */ -typedef struct -{ - struct netif *netif; /* lwIP network interface. */ - struct eth_addr *self; /* MAC address of FEC interface. */ - sys_sem_t tx_sem; /* Control access to transmitter. */ - sys_sem_t rx_sem; /* Semaphore to signal receive thread. */ -} mcf523xfec_if_t; - -/* ------------------------ Static variables ------------------------------ */ -static mcf523xfec_if_t *fecif_g; - -/* ------------------------ Static functions ------------------------------ */ -static err_t mcf523xfec_output( struct netif *, struct pbuf *, struct ip_addr * ); -static err_t mcf523xfec_output_raw( struct netif *, struct pbuf * ); - -static void mcf523xfec_reset( mcf523xfec_if_t * fecif ); -static void mcf523xfec_enable( mcf523xfec_if_t * fecif ); -static void mcf523xfec_disable( mcf523xfec_if_t * fecif ); -static void mcf523xfec_get_mac( mcf523xfec_if_t * fecif, struct eth_addr *mac ); -static void mcf523xfec_rx_irq( void ); -static void mcf523xfec_rx_task( void *arg ); - -static void arp_timer( void *arg ); -static void eth_input( struct netif *netif, struct pbuf *p ); - -/* ------------------------ Start implementation -------------------------- */ - -static void -arp_timer( void *arg ) -{ - ( void )arg; - etharp_tmr( ); - sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL ); -} - -err_t -mcf523xfec_output_raw( struct netif *netif, struct pbuf *p ) -{ - err_t res; - nbuf_t *pNBuf; - mcf523xfec_if_t *fecif = netif->state; - int i; - struct pbuf *q; - -#if ETH_PAD_SIZE - pbuf_header( p, -ETH_PAD_SIZE ); /* drop the padding word */ -#endif - - - /* Test if we can handle such big frames. If not drop it. */ - if( p->tot_len > MCF_FEC_MTU ) - { -#if LINK_STATS - lwip_stats.link.lenerr++; -#endif - res = ERR_BUF; - } - /* Test if our network buffer scheme can handle a packet of this size. If - * not drop it and return a memory error. */ - else if( p->tot_len > TX_BUFFER_SIZE ) - { -#ifdef LINK_STATS - lwip_stats.link.memerr++; -#endif - res = ERR_MEM; - } - /* Allocate a transmit buffer. If no buffer is available drop the frame. */ - else if( ( pNBuf = nbuf_tx_allocate( ) ) == NULL ) - { - LWIP_ASSERT( "mcf523xfec_output_raw: pNBuf != NULL\n", pNBuf != NULL ); -#ifdef LINK_STATS - lwip_stats.link.memerr++; -#endif - res = ERR_MEM; - } - else - { - q = p; - i = 0; - do - { - memcpy( &pNBuf->data[i], q->payload, q->len ); - i += q->len; - } - while( ( q = q->next ) != NULL ); - pNBuf->length = p->tot_len; - - /* Set Frame ready for transmission. */ - pNBuf->status |= TX_BD_R; - /* Mark the buffer as not in use so the FEC can take it. */ - nbuf_tx_release( pNBuf ); - /* Indicate that a new transmit buffer has been produced. */ - MCF_FEC_TDAR = 1; -#if LINK_STATS - lwip_stats.link.xmit++; -#endif - res = ERR_OK; - } - - sys_sem_signal( fecif->tx_sem ); -#if ETH_PAD_SIZE - buf_header( p, ETH_PAD_SIZE ); -#endif - - return res; -} - -/* This function is called by the TCP/IP stack when an IP packet should be - * sent. It uses the ethernet ARP module provided by lwIP to resolve the - * destination MAC address. The ARP module will later call our low level - * output function mcf523xfec_output_raw. - */ -err_t -mcf523xfec_output( struct netif * netif, struct pbuf * p, struct ip_addr * ipaddr ) -{ - err_t res; - mcf523xfec_if_t *fecif = netif->state; - - FEC_DEBUG_TX_TIMING( 1 ); - /* Make sure only one thread is in this function. */ - sys_sem_wait( fecif->tx_sem ); - res = etharp_output( netif, ipaddr, p ); - FEC_DEBUG_TX_TIMING( 0 ); - return res; -} - -void -mcf523xfec_rx_task( void *arg ) -{ - mcf523xfec_if_t *fecif = arg; - struct pbuf *p, *q; - nbuf_t *pNBuf; - uint8 *pPayLoad; - - do - { - sys_sem_wait( fecif->rx_sem ); - while( nbuf_rx_next_ready( ) ) - { - pNBuf = nbuf_rx_allocate( ); - if( pNBuf != NULL ) - { - LWIP_ASSERT( "mcf523xfec_rx_task: pNBuf->status & RX_BD_L ", - pNBuf->status & RX_BD_L ); - - /* This flags indicate that the frame has been damaged. In - * this case we must update the link stats if enabled and - * remove the frame from the FEC. */ - if( pNBuf->status & ( RX_BD_LG | RX_BD_NO | RX_BD_CR | RX_BD_OV ) ) - { -#ifdef LINK_STATS - lwip_stats.link.drop++; - if( pNBuf->status & RX_BD_LG ) - { - lwip_stats.link.lenerr++; - } - else if( pNBuf->status & ( RX_BD_NO | RX_BD_OV ) ) - { - lwip_stats.link.err++; - } - else - { - lwip_stats.link.chkerr++; - } -#endif - } - else - { - /* The frame must no be valid. Perform some checks to see if the FEC - * driver is working correctly. - */ - LWIP_ASSERT( "mcf523xfec_rx_task: pNBuf->length != 0", pNBuf->length != 0 ); - p = pbuf_alloc( PBUF_RAW, pNBuf->length, PBUF_POOL ); - if( p != NULL ) - { -#if ETH_PAD_SIZE - pbuf_header( p, -ETH_PAD_SIZE ); -#endif - pPayLoad = pNBuf->data; - for( q = p; q != NULL; q = q->next ) - { - memcpy( q->payload, pPayLoad, q->len ); - pPayLoad += q->len; - } -#if ETH_PAD_SIZE - pbuf_header( p, ETH_PAD_SIZE ); -#endif - - /* Ethernet frame received. Handling it is not device - * dependent and therefore done in another function. - */ - eth_input( fecif->netif, p ); - } - } - nbuf_rx_release( pNBuf ); - - /* Tell the HW that there are new free RX buffers. */ - MCF_FEC_RDAR = 1; - } - else - { -#if LINK_STATS - lwip_stats.link.memerr++; - lwip_stats.link.drop++; -#endif - } - } - /* Set RX Debug PIN to low since handling of next frame is possible. */ - FEC_DEBUG_RX_TIMING( 0 ); - } - while( 1 ); -} - -void -eth_input( struct netif *netif, struct pbuf *p ) -{ - struct eth_hdr *eth_hdr = p->payload; - - LWIP_ASSERT( "eth_input: p != NULL ", p != NULL ); - - switch ( htons( eth_hdr->type ) ) - { - case ETHTYPE_IP: - /* Pass to ARP layer. */ - etharp_ip_input( netif, p ); - - /* Skip Ethernet header. */ - pbuf_header( p, ( s16_t ) - sizeof( struct eth_hdr ) ); - - /* Pass to network layer. */ - netif->input( p, netif ); - break; - - case ETHTYPE_ARP: - /* Pass to ARP layer. */ - etharp_arp_input( netif, ( struct eth_addr * )netif->hwaddr, p ); - break; - - default: - pbuf_free( p ); - break; - } -} - -void -mcf523xfec_rx_irq( void ) -{ - static portBASE_TYPE xNeedSwitch = pdFALSE; - - /* Workaround GCC if frame pointers are enabled. This is an ISR and - * we must not modify the stack before portENTER_SWITCHING_ISR( ) - * has been called. */ -#if _GCC_USES_FP == 1 - asm volatile ( "unlk %fp\n\t" ); -#endif - - /* This ISR can cause a context switch, so the first statement must be - * a call to the portENTER_SWITCHING_ISR() macro. - */ - portENTER_SWITCHING_ISR( ); - - /* Set Debug PIN to high to measure RX latency. */ - FEC_DEBUG_RX_TIMING( 1 ); - - /* Clear FEC RX Event from the Event Register (by writing 1) */ - if( MCF_FEC_EIR & ( MCF_FEC_EIR_RXB | MCF_FEC_EIR_RXF ) ) - { - /* Clear interrupt from EIR register immediately */ - MCF_FEC_EIR = ( MCF_FEC_EIR_RXB | MCF_FEC_EIR_RXF ); - xNeedSwitch = xSemaphoreGiveFromISR( fecif_g->rx_sem, pdFALSE ); - } - portEXIT_SWITCHING_ISR( xNeedSwitch ); -} - -void -mcf523xfec_reset( mcf523xfec_if_t * fecif ) -{ - extern void ( *__RAMVEC[] ) ( ); - - int old_ipl = asm_set_ipl( 7 ); - - /* Reset the FEC - equivalent to a hard reset */ - MCF_FEC_ECR = MCF_FEC_ECR_RESET; - - /* Wait for the reset sequence to complete */ - while( MCF_FEC_ECR & MCF_FEC_ECR_RESET ); - - /* Disable all FEC interrupts by clearing the EIMR register */ - MCF_FEC_EIMR = 0; - - /* Clear any interrupts by setting all bits in the EIR register */ - MCF_FEC_EIR = 0xFFFFFFFFUL; - - /* Configure Interrupt vectors. */ - __RAMVEC[MCF_FEC_VEC_RXF] = mcf523xfec_rx_irq; - - /* Set the source address for the controller */ - MCF_FEC_PALR = - ( fecif->self->addr[0] << 24U ) | ( fecif->self->addr[1] << 16U ) | - ( fecif->self->addr[2] << 8U ) | ( fecif->self->addr[3] << 0U ); - MCF_FEC_PAUR = ( fecif->self->addr[4] << 24U ) | ( fecif->self->addr[5] << 16U ); - - /* Initialize the hash table registers */ - MCF_FEC_IAUR = 0; - MCF_FEC_IALR = 0; - - /* Set Receive Buffer Size */ -#if RX_BUFFER_SIZE != 2048 -#error "RX_BUFFER_SIZE must be set to 2048 for safe FEC operation." -#endif - MCF_FEC_EMRBR = RX_BUFFER_SIZE - 1; - - /* Point to the start of the circular Rx buffer descriptor queue */ - MCF_FEC_ERDSR = nbuf_get_start( NBUF_RX ); - - /* Point to the start of the circular Tx buffer descriptor queue */ - MCF_FEC_ETDSR = nbuf_get_start( NBUF_TX ); - - /* Set the tranceiver interface to MII mode */ - MCF_FEC_RCR = MCF_FEC_RCR_MAX_FL( MCF_FEC_MTU ) | MCF_FEC_RCR_MII_MODE; - - /* Set MII Speed Control Register for 2.5Mhz */ - MCF_FEC_MSCR = MCF_FEC_MSCR_MII_SPEED( FSYS_2 / ( 2UL * 2500000UL ) ); - - /* Only operate in half-duplex, no heart beat control */ - MCF_FEC_TCR = 0; - - /* Enable Debug support */ - FEC_DEBUG_INIT; - FEC_DEBUG_RX_TIMING( 0 ); - FEC_DEBUG_TX_TIMING( 0 ); - ( void )asm_set_ipl( old_ipl ); -} - -void -mcf523xfec_get_mac( mcf523xfec_if_t * hw, struct eth_addr *mac ) -{ - int i; - static const struct eth_addr mac_default = { - {0x00, 0xCF, 0x52, 0x35, 0x00, 0x01} - }; - - ( void )hw; - - for( i = 0; i < ETH_ADDR_LEN; i++ ) - { - mac->addr[i] = mac_default.addr[i]; - } -} - -void -mcf523xfec_enable( mcf523xfec_if_t * fecif ) -{ - ( void )fecif; - - int old_ipl = asm_set_ipl( 7 ); - - /* Configure I/O pins for the FEC. */ - MCF_GPIO_PAR_FECI2C = ( MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC ); - - /* Allow interrupts by setting IMR register */ - MCF_FEC_EIMR = MCF_FEC_EIMR_RXF; - - /* Configure the interrupt controller. */ - MCF_INTC0_ICR27 = ( MCF_INTC0_ICRn_IL( MCF_FEC_INT_LEVEL ) | - MCF_INTC0_ICRn_IP( MCF_FEC_INT_PRIORITY ) ); - MCF_INTC0_IMRL &= ~( MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_MASKALL ); - - /* Enable FEC */ - MCF_FEC_ECR = MCF_FEC_ECR_ETHER_EN; - - /* Indicate that there have been empty receive buffers produced */ - MCF_FEC_RDAR = 1; - ( void )asm_set_ipl( old_ipl ); -} - -void -mcf523xfec_disable( mcf523xfec_if_t * fecif ) -{ - ( void )fecif; - - int old_ipl = asm_set_ipl( 7 ); - - /* Set the Graceful Transmit Stop bit */ - MCF_FEC_TCR = ( MCF_FEC_TCR | MCF_FEC_TCR_GTS ); - - /* Wait for the current transmission to complete */ - while( !( MCF_FEC_EIR & MCF_FEC_EIR_GRA ) ); - - /* Clear the GRA event */ - MCF_FEC_EIR = MCF_FEC_EIR_GRA; - - /* Disable the FEC */ - MCF_FEC_ECR = 0; - - /* Disable all FEC interrupts by clearing the IMR register */ - MCF_FEC_EIMR = 0; - - /* Unconfigure the interrupt controller. */ - MCF_INTC0_ICR27 = MCF_INTC0_ICRn_IL( 0 ) | MCF_INTC0_ICRn_IP( 0 ); - MCF_INTC0_IMRL |= MCF_INTC0_IMRL_INT_MASK27; - - /* Clear the GTS bit so frames can be tranmitted when restarted */ - MCF_FEC_TCR = ( MCF_FEC_TCR & ~MCF_FEC_TCR_GTS ); - - /* Disable I/O pins used by the FEC. */ - MCF_GPIO_PAR_FECI2C &= ~( MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | - MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC ); - ( void )asm_set_ipl( old_ipl ); -} - -err_t -mcf523xfec_init( struct netif *netif ) -{ - err_t res; - - mcf523xfec_if_t *fecif = mem_malloc( sizeof( mcf523xfec_if_t ) ); - - if( fecif != NULL ) - { - /* Global copy used in ISR. */ - fecif_g = fecif; - fecif->self = ( struct eth_addr * )&netif->hwaddr[0]; - fecif->netif = netif; - fecif->tx_sem = NULL; - fecif->rx_sem = NULL; - - if( ( fecif->tx_sem = sys_sem_new( 1 ) ) == NULL ) - { - res = ERR_MEM; - } - else if( ( fecif->rx_sem = sys_sem_new( 0 ) ) == NULL ) - { - res = ERR_MEM; - } - else if( sys_thread_new( mcf523xfec_rx_task, fecif, TASK_PRIORITY ) == NULL ) - { - res = ERR_MEM; - } - else - { - netif->state = fecif; - netif->name[0] = 'C'; - netif->name[1] = 'F'; - netif->hwaddr_len = ETH_ADDR_LEN; - netif->mtu = MCF_FEC_MTU; - netif->flags = NETIF_FLAG_BROADCAST; - netif->output = mcf523xfec_output; - netif->linkoutput = mcf523xfec_output_raw; - - nbuf_init( ); - mcf523xfec_get_mac( fecif, fecif->self ); - mcf523xfec_reset( fecif ); - mcf523xfec_enable( fecif ); - - etharp_init( ); - sys_timeout( ARP_TMR_INTERVAL, arp_timer, NULL ); - - res = ERR_OK; - } - - if( res != ERR_OK ) - { - free( fecif ); - if( fecif->tx_sem != NULL ) - { - mem_free( fecif->tx_sem ); - } - if( fecif->rx_sem != NULL ) - { - mem_free( fecif->rx_sem ); - } - } - } - else - { - res = ERR_MEM; - } - - return res; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.h deleted file mode 100644 index 1495b9ec0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/netif/fec.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2006 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Author: Christian Walter - * - * File: $Id$ - */ - -#ifndef _FEC_H -#define _FEC_H - -/* ------------------------ Defines --------------------------------------- */ - -/* ------------------------ Prototypes ------------------------------------ */ -err_t mcf523xfec_init( struct netif * netif ); - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.c deleted file mode 100644 index 8cea55f2e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright (c) 2006 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Note: Most of the network buffer code is based on the MCF5235 examples from - * Freescale. - * - * File: $Id$ - */ - -/* ------------------------ Platform includes ----------------------------- */ -#include "mcf5xxx.h" -#include "mcf523x.h" - -#include "nbuf.h" - -/* ------------------------ Static variables ------------------------------ */ - -/* Buffer descriptor indexes */ -static uint8 tx_bd_idx; -static uint8 rx_bd_idx; - -/* Buffer Descriptors -- must be aligned on a 4-byte boundary but a - * 16-byte boundary is recommended. */ -static nbuf_t tx_nbuf[sizeof( nbuf_t ) * NUM_TXBDS] ATTR_FECMEM; -static nbuf_t rx_nbuf[sizeof( nbuf_t ) * NUM_RXBDS] ATTR_FECMEM; - -/* Data Buffers -- must be aligned on a 16-byte boundary. */ -static uint8 tx_buf[TX_BUFFER_SIZE * NUM_TXBDS] ATTR_FECMEM; -static uint8 rx_buf[RX_BUFFER_SIZE * NUM_RXBDS] ATTR_FECMEM; - -/* ------------------------ Start implementation -------------------------- */ -void -nbuf_init( ) -{ - - uint8 i; - - /* Initialize receive descriptor ring */ - for( i = 0; i < NUM_RXBDS; i++ ) - { - rx_nbuf[i].status = RX_BD_E; - rx_nbuf[i].length = 0; - rx_nbuf[i].data = &rx_buf[i * RX_BUFFER_SIZE]; - } - - /* Set the Wrap bit on the last one in the ring */ - rx_nbuf[NUM_RXBDS - 1].status |= RX_BD_W; - - /* Initialize transmit descriptor ring */ - for( i = 0; i < NUM_TXBDS; i++ ) - { - tx_nbuf[i].status = TX_BD_L | TX_BD_TC; - tx_nbuf[i].length = 0; - tx_nbuf[i].data = &tx_buf[i * TX_BUFFER_SIZE]; - } - - /* Set the Wrap bit on the last one in the ring */ - tx_nbuf[NUM_TXBDS - 1].status |= TX_BD_W; - - /* Initialize the buffer descriptor indexes */ - tx_bd_idx = rx_bd_idx = 0; - - return; -} - - -/********************************************************************/ -uint32 -nbuf_get_start( uint8 direction ) -{ - /* - * Return the address of the first buffer descriptor in the ring. - * This routine is needed by the FEC of the MPC860T , MCF5282, and MCF523x - * in order to write the Rx/Tx descriptor ring start registers - */ - switch ( direction ) - { - case NBUF_RX: - return ( uint32 ) rx_nbuf; - case NBUF_TX: - default: - return ( uint32 ) tx_nbuf; - } -} - - -/********************************************************************/ -nbuf_t * -nbuf_rx_allocate( ) -{ - /* This routine alters shared data. Disable interrupts! */ - int old_ipl = asm_set_ipl( 6 ); - - /* Return a pointer to the next empty Rx Buffer Descriptor */ - int i = rx_bd_idx; - - - /* Check to see if the ring of BDs is full */ - if( rx_nbuf[i].status & RX_BD_INUSE ) - return NULL; - - /* Mark the buffer as in use */ - rx_nbuf[i].status |= RX_BD_INUSE; - - /* increment the circular index */ - rx_bd_idx = ( uint8 ) ( ( rx_bd_idx + 1 ) % NUM_RXBDS ); - - /* Restore previous IPL */ - asm_set_ipl( old_ipl ); - - return &rx_nbuf[i]; -} - - -/********************************************************************/ -nbuf_t * -nbuf_tx_allocate( ) -{ - /* This routine alters shared data. Disable interrupts! */ - int old_ipl = asm_set_ipl( 6 ); - - /* Return a pointer to the next empty Tx Buffer Descriptor */ - int i = tx_bd_idx; - - /* Check to see if ring of BDs is full */ - if( ( tx_nbuf[i].status & TX_BD_INUSE ) || ( tx_nbuf[i].status & TX_BD_R ) ) - return NULL; - - /* Mark the buffer as Ready (in use) */ - /* FEC must set R bit in transmit routine */ - tx_nbuf[i].status |= TX_BD_INUSE; - - /* increment the circular index */ - tx_bd_idx = ( uint8 ) ( ( tx_bd_idx + 1 ) % NUM_TXBDS ); - - /* Restore previous IPL */ - asm_set_ipl( old_ipl ); - - return &tx_nbuf[i]; -} - - -/********************************************************************/ -void -nbuf_rx_release( nbuf_t * pNbuf ) -{ - /* This routine alters shared data. Disable interrupts! */ - int old_ipl = asm_set_ipl( 6 ); - - /* Mark the buffer as empty and not in use */ - pNbuf->status |= RX_BD_E; - pNbuf->status &= ~RX_BD_INUSE; - - /* Restore previous IPL */ - asm_set_ipl( old_ipl ); -} - -/********************************************************************/ -void -nbuf_tx_release( nbuf_t * pNbuf ) -{ - /* This routine alters shared data. Disable interrupts! */ - int old_ipl = asm_set_ipl( 6 ); - - /* Mark the buffer as not in use */ - pNbuf->status &= ~TX_BD_INUSE; - - /* Restore previous IPL */ - asm_set_ipl( old_ipl ); -} - -/********************************************************************/ -int -nbuf_rx_next_ready( ) -{ - /**************************************************************** - This function checks the EMPTY bit of the next Rx buffer to be - allocated. If the EMPTY bit is cleared, then the next buffer in - the ring has been filled by the FEC and has not already been - allocated and passed up the stack. In this case, the next buffer - in the ring is ready to be allocated. Otherwise, the buffer is - either empty or not empty but still in use by a higher level - protocol. The FEC receive routine uses this function to determine - if multiple buffers where filled by the FEC during a single - interrupt event. - ****************************************************************/ - - return ( !( rx_nbuf[rx_bd_idx].status & RX_BD_E ) ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.h deleted file mode 100644 index fb8c10917..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/netif/nbuf.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2006 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * Note: Most of the network buffer code is based on the MCF5235 examples from - * Freescale. - * - * File: $Id$ - */ - -#ifndef _NBUF_H -#define _NBUF_H - -/* ------------------------ Defines --------------------------------------- */ - -#ifdef __GNUC__ -#define ATTR_FECMEM \ - __attribute__((section(".nbuf"),aligned(16))) -#endif - -#define NBUF_RX ( 1 ) -#define NBUF_TX ( 0 ) - -/* We set the receiver buffers to the maximum size the FEC supports ( See - * MCF5235 reference manual 19.2.5.1.2 - Driver/DMA Operation with Receive - * BDs). This gives us the benefit that any frame fits into one buffer. A - * maximum size of 2047 is guaranteed by the FEC and 2048 is therefore a - * safe value. - * Note: The value MUST be dividable by 16! - */ -#define RX_BUFFER_SIZE ( 2048 ) - -/* Size of the transmit buffers. If you set this value to small all frames - * greater than this size will be dropped. The value 1520 was choosen because - * it is bigger than the FEC MTU (1518) and is dividable by 16. - * Note: The value MUST be dividable by 16! */ -#define TX_BUFFER_SIZE ( 1520 ) - -/* Number of Receive and Transmit Buffers and Buffer Descriptors */ -#define NUM_RXBDS ( 8 ) -#define NUM_TXBDS ( 4 ) - -/* ------------------------ Defines ( Buffer Descriptor Flags )------------ */ - -#define TX_BD_R ( 0x8000 ) -#define TX_BD_INUSE ( 0x4000 ) -#define TX_BD_TO1 ( 0x4000 ) -#define TX_BD_W ( 0x2000 ) -#define TX_BD_TO2 ( 0x1000 ) -#define TX_BD_L ( 0x0800 ) -#define TX_BD_TC ( 0x0400 ) -#define TX_BD_DEF ( 0x0200 ) -#define TX_BD_HB ( 0x0100 ) -#define TX_BD_LC ( 0x0080 ) -#define TX_BD_RL ( 0x0040 ) -#define TX_BD_UN ( 0x0002 ) -#define TX_BD_CSL ( 0x0001 ) - -#define RX_BD_E ( 0x8000 ) -#define RX_BD_INUSE ( 0x4000 ) -#define RX_BD_R01 ( 0x4000 ) -#define RX_BD_W ( 0x2000 ) -#define RX_BD_R02 ( 0x1000 ) -#define RX_BD_L ( 0x0800 ) -#define RX_BD_M ( 0x0100 ) -#define RX_BD_BC ( 0x0080 ) -#define RX_BD_MC ( 0x0040 ) -#define RX_BD_LG ( 0x0020 ) -#define RX_BD_NO ( 0x0010 ) -#define RX_BD_SH ( 0x0008 ) -#define RX_BD_CR ( 0x0004 ) -#define RX_BD_OV ( 0x0002 ) -#define RX_BD_TR ( 0x0001 ) - -/* ------------------------ Type definitions ------------------------------ */ -typedef struct -{ - uint16 status; /* control and status */ - uint16 length; /* transfer length */ - uint8 *data; /* buffer address */ -} nbuf_t; - -/* ------------------------ Prototypes ------------------------------------ */ - -void nbuf_init( void ); -uint32 nbuf_get_start( uint8 ); -nbuf_t *nbuf_rx_allocate( void ); -nbuf_t *nbuf_tx_allocate( void ); -void nbuf_rx_release( nbuf_t * ); -void nbuf_tx_release( nbuf_t * ); -int nbuf_rx_next_ready( void ); - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/sys_arch.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/sys_arch.c deleted file mode 100644 index 9c1abb0d6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/contrib/port/FreeRTOS/MCF5235/sys_arch.c +++ /dev/null @@ -1,562 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * Modifications Copyright (c) 2006 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * Modifcations: Christian Walter - * - * $Id$ - */ - -/* ------------------------ System includes ------------------------------- */ -#include -#include -#include -#include - -/* ------------------------ FreeRTOS includes ----------------------------- */ -#include "FreeRTOS.h" -#include "task.h" -#include "serial.h" -#include "semphr.h" - -/* ------------------------ lwIP includes --------------------------------- */ -#include "lwip/debug.h" -#include "lwip/def.h" -#include "lwip/sys.h" -#include "lwip/mem.h" -#include "lwip/stats.h" - -/* ------------------------ Defines --------------------------------------- */ -/* This is the number of threads that can be started with sys_thead_new() */ -#define SYS_MBOX_SIZE ( 16 ) -#define MS_TO_TICKS( ms ) \ - ( portTickType )( ( portTickType ) ( ms ) / portTICK_RATE_MS ) -#define TICKS_TO_MS( ticks ) \ - ( unsigned portLONG )( ( portTickType ) ( ticks ) * portTICK_RATE_MS ) -#define THREAD_STACK_SIZE ( 1024 ) -#define THREAD_NAME "lwIP" - -/* Must hold the string THREAD_NAME + task number + terminating '\0'. */ -#define THREAD_NAME_LEN_MAX 6 - -#define THREAD_INIT( tcb ) \ - do { \ - tcb->next = NULL; \ - tcb->pid = ( xTaskHandle )0; \ - tcb->timeouts.next = NULL; \ - memset( tcb->name, 0, THREAD_NAME_LEN_MAX ); \ - } while( 0 ) - -/* ------------------------ Type definitions ------------------------------ */ -typedef struct sys_tcb -{ - struct sys_tcb *next; - struct sys_timeouts timeouts; - xTaskHandle pid; - char name[THREAD_NAME_LEN_MAX]; -} sys_tcb_t; - -/* ------------------------ Static functions ------------------------------ */ -sys_tcb_t *sys_thread_current( void ); - -/* ------------------------ Static variables ------------------------------ */ -static sys_tcb_t *tasks = NULL; - -/* ------------------------ Start implementation -------------------------- */ -void -sys_init( void ) -{ - LWIP_ASSERT( "sys_init: not called first\r\n", tasks == NULL ); - tasks = NULL; -} - -/* - * This optional function does a "fast" critical region protection and returns - * the previous protection level. This function is only called during very short - * critical regions. An embedded system which supports ISR-based drivers might - * want to implement this function by disabling interrupts. Task-based systems - * might want to implement this by using a mutex or disabling tasking. This - * function should support recursive calls from the same task or interrupt. In - * other words, sys_arch_protect() could be called while already protected. In - * that case the return value indicates that it is already protected. - * - * sys_arch_protect() is only required if your port is supporting an operating - * system. - */ -sys_prot_t -sys_arch_protect( void ) -{ - vPortEnterCritical( ); - return 1; -} - -/* - * This optional function does a "fast" set of critical region protection to the - * value specified by pval. See the documentation for sys_arch_protect() for - * more information. This function is only required if your port is supporting - * an operating system. - */ -void -sys_arch_unprotect( sys_prot_t pval ) -{ - ( void )pval; - vPortExitCritical( ); -} - -/* - * Prints an assertion messages and aborts execution. - */ -void -sys_assert( const char *msg ) -{ - ( void )fputs( msg, stderr ); - ( void )fputs( "\n\r", stderr ); - exit( EXIT_FAILURE ); -} - -void -sys_debug( const char *const fmt, ... ) -{ - va_list ap; - - va_start( ap, fmt ); - ( void )vprintf( fmt, ap ); - ( void )putc( '\r', stdout ); - fflush( stdout ); - - va_end( ap ); -} - -/* ------------------------ Start implementation ( Threads ) -------------- */ - -sys_thread_t -sys_thread_new( void ( *thread ) ( void *arg ), void *arg, int prio ) -{ - return sys_arch_thread_new( thread, arg, prio, THREAD_STACK_SIZE ); -} - -/* - * Starts a new thread with priority "prio" that will begin its execution in the - * function "thread()". The "arg" argument will be passed as an argument to the - * thread() function. The argument "ssize" is the requested stack size for the - * new thread. The id of the new thread is returned. Both the id and the - * priority are system dependent. - */ -sys_thread_t -sys_arch_thread_new( void ( *thread ) ( void *arg ), void *arg, int prio, size_t ssize ) -{ - sys_thread_t thread_hdl = SYS_THREAD_NULL; - int i; - sys_tcb_t *p; - - /* We disable the FreeRTOS scheduler because it might be the case that the new - * tasks gets scheduled inside the xTaskCreate function. To prevent this we - * disable the scheduling. Note that this can happen although we have interrupts - * disabled because xTaskCreate contains a call to taskYIELD( ). - */ - vPortEnterCritical( ); - - p = tasks; - i = 0; - /* We are called the first time. Initialize it. */ - if( p == NULL ) - { - p = pvPortMalloc( sizeof( sys_tcb_t ) ); - if( p != NULL ) - { - tasks = p; - } - } - else - { - /* First task already counter. */ - i++; - /* Cycle to the end of the list. */ - while( p->next != NULL ) - { - i++; - p = p->next; - } - p->next = pvPortMalloc( sizeof( sys_tcb_t ) ); - p = p->next; - } - - if( p != NULL ) - { - /* Memory allocated. Initialize the data structure. */ - THREAD_INIT( p ); - ( void )snprintf( p->name, THREAD_NAME_LEN_MAX, "lwIP%d", i ); - - /* Now q points to a free element in the list. */ - if( xTaskCreate( thread, p->name, ssize, arg, prio, &p->pid ) == pdPASS ) - { - thread_hdl = p; - } - else - { - vPortFree( p ); - } - } - - vPortExitCritical( ); - return thread_hdl; -} - -void -sys_arch_thread_remove( sys_thread_t hdl ) -{ - sys_tcb_t *current = tasks, *prev; - sys_tcb_t *toremove = hdl; - xTaskHandle pid = ( xTaskHandle ) 0; - - LWIP_ASSERT( "sys_arch_thread_remove: assertion hdl != NULL failed!", hdl != NULL ); - - /* If we have to remove the first task we must update the global "tasks" - * variable. */ - vPortEnterCritical( ); - if( hdl != NULL ) - { - prev = NULL; - while( ( current != NULL ) && ( current != toremove ) ) - { - prev = current; - current = current->next; - } - /* Found it. */ - if( current == toremove ) - { - /* Not the first entry in the list. */ - if( prev != NULL ) - { - prev->next = toremove->next; - } - else - { - tasks = toremove->next; - } - LWIP_ASSERT( "sys_arch_thread_remove: can't remove thread with timeouts!", - toremove->timeouts.next == NULL ); - pid = toremove->pid; - THREAD_INIT( toremove ); - vPortFree( toremove ); - } - } - /* We are done with accessing the shared datastructure. Release the - * resources. - */ - vPortExitCritical( ); - if( pid != ( xTaskHandle ) 0 ) - { - vTaskDelete( pid ); - /* not reached. */ - } -} - -/* - * Returns the thread control block for the currently active task. In case - * of an error the functions returns NULL. - */ -sys_thread_t -sys_arch_thread_current( void ) -{ - sys_tcb_t *p = tasks; - xTaskHandle pid = xTaskGetCurrentTaskHandle( ); - - vPortEnterCritical( ); - while( ( p != NULL ) && ( p->pid != pid ) ) - { - p = p->next; - } - vPortExitCritical( ); - return p; -} - -/* - * Returns a pointer to the per-thread sys_timeouts structure. In lwIP, - * each thread has a list of timeouts which is represented as a linked - * list of sys_timeout structures. The sys_timeouts structure holds a - * pointer to a linked list of timeouts. This function is called by - * the lwIP timeout scheduler and must not return a NULL value. - * - * In a single threaded sys_arch implementation, this function will - * simply return a pointer to a global sys_timeouts variable stored in - * the sys_arch module. - */ -struct sys_timeouts * -sys_arch_timeouts( void ) -{ - sys_tcb_t *ptask; - - ptask = sys_arch_thread_current( ); - LWIP_ASSERT( "sys_arch_timeouts: ptask != NULL", ptask != NULL ); - return ptask != NULL ? &( ptask->timeouts ) : NULL; -} - -/* ------------------------ Start implementation ( Semaphores ) ----------- */ - -/* Creates and returns a new semaphore. The "count" argument specifies - * the initial state of the semaphore. - */ -sys_sem_t -sys_sem_new( u8_t count ) -{ - xSemaphoreHandle xSemaphore; - - vSemaphoreCreateBinary( xSemaphore ); - if( xSemaphore != SYS_SEM_NULL ) - { - if( count == 0 ) - { - xSemaphoreTake( xSemaphore, 1 ); - } -#ifdef SYS_STATS - vPortEnterCritical( ); - lwip_stats.sys.sem.used++; - if( lwip_stats.sys.sem.used > lwip_stats.sys.sem.max ) - { - lwip_stats.sys.sem.max = lwip_stats.sys.sem.used; - } - vPortExitCritical( ); -#endif - } - else - { - LWIP_ASSERT( "sys_sem_new: xSemaphore == SYS_SEM_NULL\n", xSemaphore != SYS_SEM_NULL ); - } - - return xSemaphore; -} - -/* Deallocates a semaphore */ -void -sys_sem_free( sys_sem_t sem ) -{ - LWIP_ASSERT( "sys_sem_free: sem != SYS_SEM_NULL\n", sem != SYS_SEM_NULL ); - if( sem != SYS_SEM_NULL ) - { -#ifdef SYS_STATS - vPortEnterCritical( ); - lwip_stats.sys.sem.used--; - vPortExitCritical( ); -#endif - vQueueDelete( sem ); - } -} - -/* Signals a semaphore */ -void -sys_sem_signal( sys_sem_t sem ) -{ - LWIP_ASSERT( "sys_sem_signal: sem != SYS_SEM_NULL\n", sem != SYS_SEM_NULL ); - xSemaphoreGive( sem ); -} - -/* - * Blocks the thread while waiting for the semaphore to be - * signaled. If the "timeout" argument is non-zero, the thread should - * only be blocked for the specified time (measured in - * milliseconds). - * - * If the timeout argument is non-zero, the return value is the number of - * milliseconds spent waiting for the semaphore to be signaled. If the - * semaphore wasn't signaled within the specified time, the return value is - * SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore - * (i.e., it was already signaled), the function may return zero. - * - * Notice that lwIP implements a function with a similar name, - * sys_sem_wait(), that uses the sys_arch_sem_wait() function. - */ -u32_t -sys_arch_sem_wait( sys_sem_t sem, u32_t timeout ) -{ - portBASE_TYPE xStatus; - portTickType xTicksStart, xTicksEnd, xTicksElapsed; - u32_t timespent; - - LWIP_ASSERT( "sys_arch_sem_wait: sem != SYS_SEM_NULL", sem != SYS_SEM_NULL ); - xTicksStart = xTaskGetTickCount( ); - if( timeout == 0 ) - { - do - { - xStatus = xSemaphoreTake( sem, MS_TO_TICKS( 100 ) ); - } - while( xStatus != pdTRUE ); - } - else - { - xStatus = xSemaphoreTake( sem, MS_TO_TICKS( timeout ) ); - } - - /* Semaphore was signaled. */ - if( xStatus == pdTRUE ) - { - xTicksEnd = xTaskGetTickCount( ); - xTicksElapsed = xTicksEnd - xTicksStart; - timespent = TICKS_TO_MS( xTicksElapsed ); - } - else - { - timespent = SYS_ARCH_TIMEOUT; - } - return timespent; -} - - -/* ------------------------ Start implementation ( Mailboxes ) ------------ */ - -/* Creates an empty mailbox. */ -sys_mbox_t -sys_mbox_new( void ) -{ - xQueueHandle mbox; - - mbox = xQueueCreate( SYS_MBOX_SIZE, sizeof( void * ) ); - if( mbox != SYS_MBOX_NULL ) - { -#ifdef SYS_STATS - vPortEnterCritical( ); - lwip_stats.sys.mbox.used++; - if( lwip_stats.sys.mbox.used > lwip_stats.sys.mbox.max ) - { - lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used; - } - vPortExitCritical( ); -#endif - } - return mbox; -} - -/* - Deallocates a mailbox. If there are messages still present in the - mailbox when the mailbox is deallocated, it is an indication of a - programming error in lwIP and the developer should be notified. -*/ -void -sys_mbox_free( sys_mbox_t mbox ) -{ - void *msg; - - LWIP_ASSERT( "sys_mbox_free: mbox != SYS_MBOX_NULL", mbox != SYS_MBOX_NULL ); - if( mbox != SYS_MBOX_NULL ) - { - while( uxQueueMessagesWaiting( mbox ) != 0 ) - { - if( sys_arch_mbox_fetch( mbox, &msg, 1 ) != SYS_ARCH_TIMEOUT ) - { - LWIP_ASSERT( "sys_mbox_free: memory leak (msg != NULL)", msg == NULL ); - } - } - vQueueDelete( mbox ); -#ifdef SYS_STATS - vPortEnterCritical( ); - lwip_stats.sys.mbox.used--; - vPortExitCritical( ); -#endif - } -} - -/* - * This function sends a message to a mailbox. It is unusual in that no error - * return is made. This is because the caller is responsible for ensuring that - * the mailbox queue will not fail. The caller does this by limiting the number - * of msg structures which exist for a given mailbox. - */ -void -sys_mbox_post( sys_mbox_t mbox, void *data ) -{ - portBASE_TYPE xQueueSent; - - /* Queue must not be full - Otherwise it is an error. */ - xQueueSent = xQueueSend( mbox, &data, 0 ); - LWIP_ASSERT( "sys_mbox_post: xQueueSent == pdPASS", xQueueSent == pdPASS ); -} - -/* - * Blocks the thread until a message arrives in the mailbox, but does - * not block the thread longer than "timeout" milliseconds (similar to - * the sys_arch_sem_wait() function). The "msg" argument is a result - * parameter that is set by the function (i.e., by doing "*msg = - * ptr"). The "msg" parameter maybe NULL to indicate that the message - * should be dropped. - * - * Note that a function with a similar name, sys_mbox_fetch(), is - * implemented by lwIP. - */ -u32_t -sys_arch_mbox_fetch( sys_mbox_t mbox, void **msg, u32_t timeout ) -{ - void *ret_msg; - portBASE_TYPE xStatus; - portTickType xTicksStart, xTicksEnd, xTicksElapsed; - u32_t timespent; - - LWIP_ASSERT( "sys_arch_mbox_fetch: mbox != SYS_MBOX_NULL", mbox != SYS_MBOX_NULL ); - xTicksStart = xTaskGetTickCount( ); - if( timeout == 0 ) - { - do - { - xStatus = xQueueReceive( mbox, &ret_msg, MS_TO_TICKS( 100 ) ); - } - while( xStatus != pdTRUE ); - } - else - { - xStatus = xQueueReceive( mbox, &ret_msg, MS_TO_TICKS( timeout ) ); - } - - if( xStatus == pdTRUE ) - { - if( msg ) - { - *msg = ret_msg; - } - xTicksEnd = xTaskGetTickCount( ); - xTicksElapsed = xTicksEnd - xTicksStart; - timespent = TICKS_TO_MS( xTicksElapsed ); - } - else - { - if( msg ) - { - *msg = NULL; - } - timespent = SYS_ARCH_TIMEOUT; - } - return timespent; -} - -unsigned long -sys_jiffies( void ) -{ - portTickType xTicks = xTaskGetTickCount( ); - - return ( unsigned long )TICKS_TO_MS( xTicks ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/doc/contrib.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/doc/contrib.txt deleted file mode 100644 index 7c99b9be2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/doc/contrib.txt +++ /dev/null @@ -1,62 +0,0 @@ -1 Introduction - -This document describes some guidelines for people participating -in lwIP development. - -2 How to contribute to lwIP - -Here is a short list of suggestions to anybody working with lwIP and -trying to contribute bug reports, fixes, enhancements, platform ports etc. -First of all as you may already know lwIP is a volunteer project so feedback -to fixes or questions might often come late. Hopefully the bug and patch tracking -features of Savannah help us not lose users' input. - -2.1 Source code style: - -1. do not use tabs. -2. indentation is two spaces per level (i.e. per tab). -3. end debug messages with a trailing newline (\n). -4. one space between keyword and opening bracket. -5. no space between function and opening bracket. -6. one space and no newline before opening curly braces of a block. -7. closing curly brace on a single line. -8. spaces surrounding assignment and comparisons. -9. use current source code style as further reference. - -2.2 Source code documentation style: - -1. JavaDoc compliant and Doxygen compatible. -2. Function documentation above functions in .c files, not .h files. - (This forces you to synchronize documentation and implementation.) -3. Use current documentation style as further reference. - -2.3 Bug reports and patches: - -1. Make sure you are reporting bugs or send patches against the latest - sources. (From the latest release and/or the current CVS sources.) -2. If you think you found a bug make sure it's not already filed in the - bugtracker at Savannah. -3. If you have a fix put the patch on Savannah. If it is a patch that affects - both core and arch specific stuff please separate them so that the core can - be applied separately while leaving the other patch 'open'. The prefered way - is to NOT touch archs you can't test and let maintainers take care of them. - This is a good way to see if they are used at all - the same goes for unix - netifs except tapif. -4. Do not file a bug and post a fix to it to the patch area. Either a bug report - or a patch will be enough. - If you correct an existing bug then attach the patch to the bug rather than creating a new entry in the patch area. -5. Trivial patches (compiler warning, indentation and spelling fixes or anything obvious which takes a line or two) - can go to the lwip-users list. This is still the fastest way of interaction and the list is not so crowded - as to allow for loss of fixes. Putting bugs on Savannah and subsequently closing them is too much an overhead - for reporting a compiler warning fix. -6. Patches should be specific to a single change or to related changes.Do not mix bugfixes with spelling and other - trivial fixes unless the bugfix is trivial too.Do not reorganize code and rename identifiers in the same patch you - change behaviour if not necessary.A patch is easier to read and understand if it's to the point and short than - if it's not to the point and long :) so the chances for it to be applied are greater. - -2.4 Platform porters: - -1. If you have ported lwIP to a platform (an OS, a uC/processor or a combination of these) and - you think it could benefit others[1] you might want discuss this on the mailing list. You - can also ask for CVS access to submit and maintain your port in the contrib CVS module. - \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/doc/rawapi.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/doc/rawapi.txt deleted file mode 100644 index f84e0d2eb..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/doc/rawapi.txt +++ /dev/null @@ -1,386 +0,0 @@ -Raw TCP/IP interface for lwIP - -Authors: Adam Dunkels, Leon Woestenberg, Christiaan Simons - -lwIP provides two Application Program's Interfaces (APIs) for programs -to use for communication with the TCP/IP code: -* low-level "core" / "callback" or "raw" API. -* higher-level "sequential" API. - -The sequential API provides a way for ordinary, sequential, programs -to use the lwIP stack. It is quite similar to the BSD socket API. The -model of execution is based on the blocking open-read-write-close -paradigm. Since the TCP/IP stack is event based by nature, the TCP/IP -code and the application program must reside in different execution -contexts (threads). - -** The remainder of this document discusses the "raw" API. ** - -The raw TCP/IP interface allows the application program to integrate -better with the TCP/IP code. Program execution is event based by -having callback functions being called from within the TCP/IP -code. The TCP/IP code and the application program both run in the same -thread. The sequential API has a much higher overhead and is not very -well suited for small systems since it forces a multithreaded paradigm -on the application. - -The raw TCP/IP interface is not only faster in terms of code execution -time but is also less memory intensive. The drawback is that program -development is somewhat harder and application programs written for -the raw TCP/IP interface are more difficult to understand. Still, this -is the preferred way of writing applications that should be small in -code size and memory usage. - -Both APIs can be used simultaneously by different application -programs. In fact, the sequential API is implemented as an application -program using the raw TCP/IP interface. - ---- Callbacks - -Program execution is driven by callbacks. Each callback is an ordinary -C function that is called from within the TCP/IP code. Every callback -function is passed the current TCP or UDP connection state as an -argument. Also, in order to be able to keep program specific state, -the callback functions are called with a program specified argument -that is independent of the TCP/IP state. - -The function for setting the application connection state is: - -- void tcp_arg(struct tcp_pcb *pcb, void *arg) - - Specifies the program specific state that should be passed to all - other callback functions. The "pcb" argument is the current TCP - connection control block, and the "arg" argument is the argument - that will be passed to the callbacks. - - ---- TCP connection setup - -The functions used for setting up connections is similar to that of -the sequential API and of the BSD socket API. A new TCP connection -identifier (i.e., a protocol control block - PCB) is created with the -tcp_new() function. This PCB can then be either set to listen for new -incoming connections or be explicitly connected to another host. - -- struct tcp_pcb *tcp_new(void) - - Creates a new connection identifier (PCB). If memory is not - available for creating the new pcb, NULL is returned. - -- err_t tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port) - - Binds the pcb to a local IP address and port number. The IP address - can be specified as IP_ADDR_ANY in order to bind the connection to - all local IP addresses. - - If another connection is bound to the same port, the function will - return ERR_USE, otherwise ERR_OK is returned. - -- struct tcp_pcb *tcp_listen(struct tcp_pcb *pcb) - - Commands a pcb to start listening for incoming connections. When an - incoming connection is accepted, the function specified with the - tcp_accept() function will be called. The pcb will have to be bound - to a local port with the tcp_bind() function. - - The tcp_listen() function returns a new connection identifier, and - the one passed as an argument to the function will be - deallocated. The reason for this behavior is that less memory is - needed for a connection that is listening, so tcp_listen() will - reclaim the memory needed for the original connection and allocate a - new smaller memory block for the listening connection. - - tcp_listen() may return NULL if no memory was available for the - listening connection. If so, the memory associated with the pcb - passed as an argument to tcp_listen() will not be deallocated. - -- void tcp_accept(struct tcp_pcb *pcb, - err_t (* accept)(void *arg, struct tcp_pcb *newpcb, - err_t err)) - - Specified the callback function that should be called when a new - connection arrives on a listening connection. - -- err_t tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port, err_t (* connected)(void *arg, - struct tcp_pcb *tpcb, - err_t err)); - - Sets up the pcb to connect to the remote host and sends the - initial SYN segment which opens the connection. - - The tcp_connect() function returns immediately; it does not wait for - the connection to be properly setup. Instead, it will call the - function specified as the fourth argument (the "connected" argument) - when the connection is established. If the connection could not be - properly established, either because the other host refused the - connection or because the other host didn't answer, the "connected" - function will be called with an the "err" argument set accordingly. - - The tcp_connect() function can return ERR_MEM if no memory is - available for enqueueing the SYN segment. If the SYN indeed was - enqueued successfully, the tcp_connect() function returns ERR_OK. - - ---- Sending TCP data - -TCP data is sent by enqueueing the data with a call to -tcp_write(). When the data is successfully transmitted to the remote -host, the application will be notified with a call to a specified -callback function. - -- err_t tcp_write(struct tcp_pcb *pcb, void *dataptr, u16_t len, - u8_t copy) - - Enqueues the data pointed to by the argument dataptr. The length of - the data is passed as the len parameter. The copy argument is either - 0 or 1 and indicates whether the new memory should be allocated for - the data to be copied into. If the argument is 0, no new memory - should be allocated and the data should only be referenced by - pointer. - - The tcp_write() function will fail and return ERR_MEM if the length - of the data exceeds the current send buffer size or if the length of - the queue of outgoing segment is larger than the upper limit defined - in lwipopts.h. The number of bytes available in the output queue can - be retrieved with the tcp_sndbuf() function. - - The proper way to use this function is to call the function with at - most tcp_sndbuf() bytes of data. If the function returns ERR_MEM, - the application should wait until some of the currently enqueued - data has been successfully received by the other host and try again. - -- void tcp_sent(struct tcp_pcb *pcb, - err_t (* sent)(void *arg, struct tcp_pcb *tpcb, - u16_t len)) - - Specifies the callback function that should be called when data has - successfully been received (i.e., acknowledged) by the remote - host. The len argument passed to the callback function gives the - amount bytes that was acknowledged by the last acknowledgment. - - ---- Receiving TCP data - -TCP data reception is callback based - an application specified -callback function is called when new data arrives. When the -application has taken the data, it has to call the tcp_recved() -function to indicate that TCP can advertise increase the receive -window. - -- void tcp_recv(struct tcp_pcb *pcb, - err_t (* recv)(void *arg, struct tcp_pcb *tpcb, - struct pbuf *p, err_t err)) - - Sets the callback function that will be called when new data - arrives. The callback function will be passed a NULL pbuf to - indicate that the remote host has closed the connection. - -- void tcp_recved(struct tcp_pcb *pcb, u16_t len) - - Must be called when the application has received the data. The len - argument indicates the length of the received data. - - ---- Application polling - -When a connection is idle (i.e., no data is either transmitted or -received), lwIP will repeatedly poll the application by calling a -specified callback function. This can be used either as a watchdog -timer for killing connections that have stayed idle for too long, or -as a method of waiting for memory to become available. For instance, -if a call to tcp_write() has failed because memory wasn't available, -the application may use the polling functionality to call tcp_write() -again when the connection has been idle for a while. - -- void tcp_poll(struct tcp_pcb *pcb, u8_t interval, - err_t (* poll)(void *arg, struct tcp_pcb *tpcb)) - - Specifies the polling interval and the callback function that should - be called to poll the application. The interval is specified in - number of TCP coarse grained timer shots, which typically occurs - twice a second. An interval of 10 means that the application would - be polled every 5 seconds. - - ---- Closing and aborting connections - -- err_t tcp_close(struct tcp_pcb *pcb) - - Closes the connection. The function may return ERR_MEM if no memory - was available for closing the connection. If so, the application - should wait and try again either by using the acknowledgment - callback or the polling functionality. If the close succeeds, the - function returns ERR_OK. - - The pcb is deallocated by the TCP code after a call to tcp_close(). - -- void tcp_abort(struct tcp_pcb *pcb) - - Aborts the connection by sending a RST (reset) segment to the remote - host. The pcb is deallocated. This function never fails. - -If a connection is aborted because of an error, the application is -alerted of this event by the err callback. Errors that might abort a -connection are when there is a shortage of memory. The callback -function to be called is set using the tcp_err() function. - -- void tcp_err(struct tcp_pcb *pcb, void (* err)(void *arg, - err_t err)) - - The error callback function does not get the pcb passed to it as a - parameter since the pcb may already have been deallocated. - - ---- Lower layer TCP interface - -TCP provides a simple interface to the lower layers of the -system. During system initialization, the function tcp_init() has -to be called before any other TCP function is called. When the system -is running, the two timer functions tcp_fasttmr() and tcp_slowtmr() -must be called with regular intervals. The tcp_fasttmr() should be -called every TCP_FAST_INTERVAL milliseconds (defined in tcp.h) and -tcp_slowtmr() should be called every TCP_SLOW_INTERVAL milliseconds. - - ---- UDP interface - -The UDP interface is similar to that of TCP, but due to the lower -level of complexity of UDP, the interface is significantly simpler. - -- struct udp_pcb *udp_new(void) - - Creates a new UDP pcb which can be used for UDP communication. The - pcb is not active until it has either been bound to a local address - or connected to a remote address. - -- void udp_remove(struct udp_pcb *pcb) - - Removes and deallocates the pcb. - -- err_t udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port) - - Binds the pcb to a local address. The IP-address argument "ipaddr" - can be IP_ADDR_ANY to indicate that it should listen to any local IP - address. The function currently always return ERR_OK. - -- err_t udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port) - - Sets the remote end of the pcb. This function does not generate any - network traffic, but only set the remote address of the pcb. - -- err_t udp_disconnect(struct udp_pcb *pcb) - - Remove the remote end of the pcb. This function does not generate - any network traffic, but only removes the remote address of the pcb. - -- err_t udp_send(struct udp_pcb *pcb, struct pbuf *p) - - Sends the pbuf p. The pbuf is not deallocated. - -- void udp_recv(struct udp_pcb *pcb, - void (* recv)(void *arg, struct udp_pcb *upcb, - struct pbuf *p, - struct ip_addr *addr, - u16_t port), - void *recv_arg) - - Specifies a callback function that should be called when a UDP - datagram is received. - - ---- System initalization - -A truly complete and generic sequence for initializing the lwip stack -cannot be given because it depends on the build configuration (lwipopts.h) -and additional initializations for your runtime environment (e.g. timers). - -We can give you some idea on how to proceed when using the raw API. -We assume a configuration using a single Ethernet netif and the -UDP and TCP transport layers, IPv4 and the DHCP client. - -Call these functions in the order of appearance: - -- stats_init() - - Clears the structure where runtime statistics are gathered. - -- sys_init() - - Not of much use since we set the NO_SYS 1 option in lwipopts.h, - to be called for easy configuration changes. - -- mem_init() - - Initializes the dynamic memory heap defined by MEM_SIZE. - -- memp_init() - - Initializes the memory pools defined by MEMP_NUM_x. - -- pbuf_init() - - Initializes the pbuf memory pool defined by PBUF_POOL_SIZE. - -- etharp_init() - - Initializes the ARP table and queue. - Note: you must call etharp_tmr at a 10 second regular interval - after this initialization. - -- ip_init() - - Doesn't do much, it should be called to handle future changes. - -- udp_init() - - Clears the UDP PCB list. - -- tcp_init() - - Clears the TCP PCB list and clears some internal TCP timers. - Note: you must call tcp_fasttmr() and tcp_slowtmr() at the - predefined regular intervals after this initialization. - -- netif_add(struct netif *netif, struct ip_addr *ipaddr, - struct ip_addr *netmask, struct ip_addr *gw, - void *state, err_t (* init)(struct netif *netif), - err_t (* input)(struct pbuf *p, struct netif *netif)) - - Adds your network interface to the netif_list. Allocate a struct - netif and pass a pointer to this structure as the first argument. - Give pointers to cleared ip_addr structures when using DHCP, - or fill them with sane numbers otherwise. The state pointer may be NULL. - - The init function pointer must point to a initialization function for - your ethernet netif interface. The following code illustrates it's use. - - err_t netif_if_init(struct netif *netif) - { - u8_t i; - - for(i = 0; i < 6; i++) netif->hwaddr[i] = some_eth_addr[i]; - init_my_eth_device(); - return ERR_OK; - } - - The input function pointer must point to the lwip ip_input(). - -- netif_set_default(struct netif *netif) - - Registers the default network interface. - -- netif_set_up(struct netif *netif) - - When the netif is fully configured this function must be called. - -- dhcp_start(struct netif *netif) - - Creates a new DHCP client for this interface on the first call. - Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at - the predefined regular intervals after starting the client. - - You can peek in the netif->dhcp struct for the actual DHCP status. diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/doc/savannah.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/doc/savannah.txt deleted file mode 100644 index 409905b10..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/doc/savannah.txt +++ /dev/null @@ -1,135 +0,0 @@ -Daily Use Guide for using Savannah for lwIP - -Table of Contents: - -1 - Obtaining lwIP from the CVS repository -2 - Committers/developers CVS access using SSH (to be written) -3 - Merging from DEVEL branch to main trunk (stable branch) -4 - How to release lwIP - - - -1 Obtaining lwIP from the CVS repository ----------------------------------------- - -To perform an anonymous CVS checkout of the main trunk (this is where -bug fixes and incremental enhancements occur), do this: - -cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout lwip - -Or, obtain a stable branch (updated with bug fixes only) as follows: -cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \ - -r STABLE-0_7 -d lwip-0.7 lwip - -Or, obtain a specific (fixed) release as follows: -cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \ - -r STABLE-0_7_0 -d lwip-0.7.0 lwip - -3 Committers/developers CVS access using SSH --------------------------------------------- - -The Savannah server uses SSH (Secure Shell) protocol 2 authentication and encryption. -As such, CVS commits to the server occur through a SSH tunnel for project members. -To create a SSH2 key pair in UNIX-like environments, do this: - -ssh-keygen -t dsa - -Under Windows, a recommended SSH client is "PuTTY", freely available with good -documentation and a graphic user interface. Use its key generator. - -Now paste the id_dsa.pub contents into your Savannah account public key list. Wait -a while so that Savannah can update its configuration (This can take minutes). - -Try to login using SSH: - -ssh -v your_login@cvs.sv.gnu.org - -If it tells you: - -Authenticating with public key "your_key_name"... -Server refused to allocate pty - -then you could login; Savannah refuses to give you a shell - which is OK, as we -are allowed to use SSH for CVS only. Now, you should be able to do this: - -export CVS_RSH=ssh -cvs -z3 -d:ext:your_login@cvs.sv.gnu.org:/sources/lwip co lwip - -after which you can edit your local files with bug fixes or new features and -commit them. Make sure you know what you are doing when using CVS to make -changes on the repository. If in doubt, ask on the lwip-members mailing list. - -(If SSH asks about authenticity of the host, you can check the key - fingerprint against http://savannah.nongnu.org/cvs/?group=lwip) - - -3 Merging from DEVEL branch to main trunk (stable) --------------------------------------------------- - -Merging is a delicate process in CVS and requires the -following disciplined steps in order to prevent conflicts -in the future. Conflicts can be hard to solve! - -Merging from branch A to branch B requires that the A branch -has a tag indicating the previous merger. This tag is called -'merged_from_A_to_B'. After merging, the tag is moved in the -A branch to remember this merger for future merge actions. - -IMPORTANT: AFTER COMMITTING A SUCCESFUL MERGE IN THE -REPOSITORY, THE TAG MUST BE SET ON THE SOURCE BRANCH OF THE -MERGE ACTION (REPLACING EXISTING TAGS WITH THE SAME NAME). - -Merge all changes in DEVEL since our last merge to main: - -In the working copy of the main trunk: -cvs update -P -jmerged_from_DEVEL_to_main -jDEVEL - -(This will apply the changes between 'merged_from_DEVEL_to_main' -and 'DEVEL' to your work set of files) - -We can now commit the merge result. -cvs commit -R -m "Merged from DEVEL to main." - -If this worked out OK, we now move the tag in the DEVEL branch -to this merge point, so we can use this point for future merges: - -cvs rtag -F -r DEVEL merged_from_DEVEL_to_main lwip - -4 How to release lwIP ---------------------- - -First, checkout a clean copy of the branch to be released. Tag this set with -tag name "STABLE-0_6_3". (I use release number 0.6.3 throughout this example). - -Login CVS using pserver authentication, then export a clean copy of the -tagged tree. Export is similar to a checkout, except that the CVS metadata -is not created locally. - -export CVS_RSH=ssh -cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \ - -r STABLE-0_6_3 -d lwip-0.6.3 lwip - -Archive this directory using tar, gzip'd, bzip2'd and zip'd. - -tar czvf lwip-0.6.3.tar.gz lwip-0.6.3 -tar cjvf lwip-0.6.3.tar.bz2 lwip-0.6.3 -zip -r lwip-0.6.3.zip lwip-0.6.3 - -Now, sign the archives with a detached GPG binary signature as follows: - -gpg -b lwip-0.6.3.tar.gz -gpg -b lwip-0.6.3.tar.bz2 -gpg -b lwip-0.6.3.zip - -Upload these files using anonymous FTP: -ncftp ftp://savannah.gnu.org/incoming/savannah/lwip - -ncftp>mput *0.6.3.* - -Additionally, you may post a news item on Savannah, like this: - -A new 0.6.3 release is now available here: -http://savannah.nongnu.org/files/?group=lwip&highlight=0.6.3 - -You will have to submit this via the user News interface, then approve -this via the Administrator News interface. \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/doc/sys_arch.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/doc/sys_arch.txt deleted file mode 100644 index 95d0add73..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/doc/sys_arch.txt +++ /dev/null @@ -1,194 +0,0 @@ -sys_arch interface for lwIP 0.6++ - -Author: Adam Dunkels - -The operating system emulation layer provides a common interface -between the lwIP code and the underlying operating system kernel. The -general idea is that porting lwIP to new architectures requires only -small changes to a few header files and a new sys_arch -implementation. It is also possible to do a sys_arch implementation -that does not rely on any underlying operating system. - -The sys_arch provides semaphores and mailboxes to lwIP. For the full -lwIP functionality, multiple threads support can be implemented in the -sys_arch, but this is not required for the basic lwIP -functionality. Previous versions of lwIP required the sys_arch to -implement timer scheduling as well but as of lwIP 0.5 this is -implemented in a higher layer. - -In addition to the source file providing the functionality of sys_arch, -the OS emulation layer must provide several header files defining -macros used throughout lwip. The files required and the macros they -must define are listed below the sys_arch description. - -Semaphores can be either counting or binary - lwIP works with both -kinds. Mailboxes are used for message passing and can be implemented -either as a queue which allows multiple messages to be posted to a -mailbox, or as a rendez-vous point where only one message can be -posted at a time. lwIP works with both kinds, but the former type will -be more efficient. A message in a mailbox is just a pointer, nothing -more. - -Semaphores are represented by the type "sys_sem_t" which is typedef'd -in the sys_arch.h file. Mailboxes are equivalently represented by the -type "sys_mbox_t". lwIP does not place any restrictions on how -sys_sem_t or sys_mbox_t are represented internally. - -The following functions must be implemented by the sys_arch: - -- void sys_init(void) - - Is called to initialize the sys_arch layer. - -- sys_sem_t sys_sem_new(u8_t count) - - Creates and returns a new semaphore. The "count" argument specifies - the initial state of the semaphore. - -- void sys_sem_free(sys_sem_t sem) - - Deallocates a semaphore. - -- void sys_sem_signal(sys_sem_t sem) - - Signals a semaphore. - -- u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout) - - Blocks the thread while waiting for the semaphore to be - signaled. If the "timeout" argument is non-zero, the thread should - only be blocked for the specified time (measured in - milliseconds). - - If the timeout argument is non-zero, the return value is the number of - milliseconds spent waiting for the semaphore to be signaled. If the - semaphore wasn't signaled within the specified time, the return value is - SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore - (i.e., it was already signaled), the function may return zero. - - Notice that lwIP implements a function with a similar name, - sys_sem_wait(), that uses the sys_arch_sem_wait() function. - -- sys_mbox_t sys_mbox_new(void) - - Creates an empty mailbox. - -- void sys_mbox_free(sys_mbox_t mbox) - - Deallocates a mailbox. If there are messages still present in the - mailbox when the mailbox is deallocated, it is an indication of a - programming error in lwIP and the developer should be notified. - -- void sys_mbox_post(sys_mbox_t mbox, void *msg) - - Posts the "msg" to the mailbox. - -- u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout) - - Blocks the thread until a message arrives in the mailbox, but does - not block the thread longer than "timeout" milliseconds (similar to - the sys_arch_sem_wait() function). The "msg" argument is a result - parameter that is set by the function (i.e., by doing "*msg = - ptr"). The "msg" parameter maybe NULL to indicate that the message - should be dropped. - - The return values are the same as for the sys_arch_sem_wait() function: - Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a - timeout. - - Note that a function with a similar name, sys_mbox_fetch(), is - implemented by lwIP. - -- struct sys_timeouts *sys_arch_timeouts(void) - - Returns a pointer to the per-thread sys_timeouts structure. In lwIP, - each thread has a list of timeouts which is repressented as a linked - list of sys_timeout structures. The sys_timeouts structure holds a - pointer to a linked list of timeouts. This function is called by - the lwIP timeout scheduler and must not return a NULL value. - - In a single threadd sys_arch implementation, this function will - simply return a pointer to a global sys_timeouts variable stored in - the sys_arch module. - -If threads are supported by the underlying operating system and if -such functionality is needed in lwIP, the following function will have -to be implemented as well: - -- sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio) - - Starts a new thread with priority "prio" that will begin its execution in the - function "thread()". The "arg" argument will be passed as an argument to the - thread() function. The id of the new thread is returned. Both the id and - the priority are system dependent. - -- sys_prot_t sys_arch_protect(void) - - This optional function does a "fast" critical region protection and returns - the previous protection level. This function is only called during very short - critical regions. An embedded system which supports ISR-based drivers might - want to implement this function by disabling interrupts. Task-based systems - might want to implement this by using a mutex or disabling tasking. This - function should support recursive calls from the same task or interrupt. In - other words, sys_arch_protect() could be called while already protected. In - that case the return value indicates that it is already protected. - - sys_arch_protect() is only required if your port is supporting an operating - system. - -- void sys_arch_unprotect(sys_prot_t pval) - - This optional function does a "fast" set of critical region protection to the - value specified by pval. See the documentation for sys_arch_protect() for - more information. This function is only required if your port is supporting - an operating system. - -------------------------------------------------------------------------------- -Additional files required for the "OS support" emulation layer: -------------------------------------------------------------------------------- - -cc.h - Architecture environment, some compiler specific, some - environment specific (probably should move env stuff - to sys_arch.h.) - - Typedefs for the types used by lwip - - u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t - - Compiler hints for packing lwip's structures - - PACK_STRUCT_FIELD(x) - PACK_STRUCT_STRUCT - PACK_STRUCT_BEGIN - PACK_STRUCT_END - - Platform specific diagnostic output - - LWIP_PLATFORM_DIAG(x) - non-fatal, print a message. - LWIP_PLATFORM_ASSERT(x) - fatal, print message and abandon execution. - - "lightweight" synchronization mechanisms - - SYS_ARCH_DECL_PROTECT(x) - declare a protection state variable. - SYS_ARCH_PROTECT(x) - enter protection mode. - SYS_ARCH_UNPROTECT(x) - leave protection mode. - - If the compiler does not provide memset() this file must include a - definition of it, or include a file which defines it. - - This file must either include a system-local which defines - the standard *nix error codes, or it should #define LWIP_PROVIDE_ERRNO - to make lwip/arch.h define the codes which are used throughout. - - -perf.h - Architecture specific performance measurement. - Measurement calls made throughout lwip, these can be defined to nothing. - PERF_START - start measuring something. - PERF_STOP(x) - stop measuring something, and record the result. - -sys_arch.h - Tied to sys_arch.c - - Arch dependent types for the following objects: - sys_sem_t, sys_mbox_t, sys_thread_t, - And, optionally: - sys_prot_t - - Defines to set vars of sys_mbox_t and sys_sem_t to NULL. - SYS_MBOX_NULL NULL - SYS_SEM_NULL NULL diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/FILES b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/FILES deleted file mode 100644 index 2b6573185..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/FILES +++ /dev/null @@ -1,13 +0,0 @@ -api/ - The code for the high-level wrapper API. Not needed if - you use the lowel-level call-back/raw API. - -core/ - The core of the TPC/IP stack; protocol implementations, - memory and buffer management, and the low-level raw API. - -include/ - lwIP include files. - -netif/ - Generic network interface device drivers are kept here, - as well as the ARP module. - -For more information on the various subdirectories, check the FILES -file in each directory. diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/api/api_lib.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/api/api_lib.c deleted file mode 100644 index 3d83d1ea4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/api/api_lib.c +++ /dev/null @@ -1,729 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* This is the part of the API that is linked with - the application */ - -#include "lwip/opt.h" -#include "lwip/api.h" -#include "lwip/api_msg.h" -#include "lwip/memp.h" - - -struct -netbuf *netbuf_new(void) -{ - struct netbuf *buf; - - buf = memp_malloc(MEMP_NETBUF); - if (buf != NULL) { - buf->p = NULL; - buf->ptr = NULL; - return buf; - } else { - return NULL; - } -} - -void -netbuf_delete(struct netbuf *buf) -{ - if (buf != NULL) { - if (buf->p != NULL) { - pbuf_free(buf->p); - buf->p = buf->ptr = NULL; - } - memp_free(MEMP_NETBUF, buf); - } -} - -void * -netbuf_alloc(struct netbuf *buf, u16_t size) -{ - /* Deallocate any previously allocated memory. */ - if (buf->p != NULL) { - pbuf_free(buf->p); - } - buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM); - if (buf->p == NULL) { - return NULL; - } - buf->ptr = buf->p; - return buf->p->payload; -} - -void -netbuf_free(struct netbuf *buf) -{ - if (buf->p != NULL) { - pbuf_free(buf->p); - } - buf->p = buf->ptr = NULL; -} - -void -netbuf_ref(struct netbuf *buf, void *dataptr, u16_t size) -{ - if (buf->p != NULL) { - pbuf_free(buf->p); - } - buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF); - buf->p->payload = dataptr; - buf->p->len = buf->p->tot_len = size; - buf->ptr = buf->p; -} - -void -netbuf_chain(struct netbuf *head, struct netbuf *tail) -{ - pbuf_chain(head->p, tail->p); - head->ptr = head->p; - memp_free(MEMP_NETBUF, tail); -} - -u16_t -netbuf_len(struct netbuf *buf) -{ - return buf->p->tot_len; -} - -err_t -netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len) -{ - if (buf->ptr == NULL) { - return ERR_BUF; - } - *dataptr = buf->ptr->payload; - *len = buf->ptr->len; - return ERR_OK; -} - -s8_t -netbuf_next(struct netbuf *buf) -{ - if (buf->ptr->next == NULL) { - return -1; - } - buf->ptr = buf->ptr->next; - if (buf->ptr->next == NULL) { - return 1; - } - return 0; -} - -void -netbuf_first(struct netbuf *buf) -{ - buf->ptr = buf->p; -} - -void -netbuf_copy_partial(struct netbuf *buf, void *dataptr, u16_t len, u16_t offset) -{ - struct pbuf *p; - u16_t i, left; - - left = 0; - - if(buf == NULL || dataptr == NULL) { - return; - } - - /* This implementation is bad. It should use bcopy - instead. */ - for(p = buf->p; left < len && p != NULL; p = p->next) { - if (offset != 0 && offset >= p->len) { - offset -= p->len; - } else { - for(i = offset; i < p->len; ++i) { - ((u8_t *)dataptr)[left] = ((u8_t *)p->payload)[i]; - if (++left >= len) { - return; - } - } - offset = 0; - } - } -} - -void -netbuf_copy(struct netbuf *buf, void *dataptr, u16_t len) -{ - netbuf_copy_partial(buf, dataptr, len, 0); -} - -struct ip_addr * -netbuf_fromaddr(struct netbuf *buf) -{ - return buf->fromaddr; -} - -u16_t -netbuf_fromport(struct netbuf *buf) -{ - return buf->fromport; -} - -struct -netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto, - void (*callback)(struct netconn *, enum netconn_evt, u16_t len)) -{ - struct netconn *conn; - struct api_msg *msg; - - conn = memp_malloc(MEMP_NETCONN); - if (conn == NULL) { - return NULL; - } - - conn->err = ERR_OK; - conn->type = t; - conn->pcb.tcp = NULL; - - if ((conn->mbox = sys_mbox_new()) == SYS_MBOX_NULL) { - memp_free(MEMP_NETCONN, conn); - return NULL; - } - conn->recvmbox = SYS_MBOX_NULL; - conn->acceptmbox = SYS_MBOX_NULL; - conn->sem = SYS_SEM_NULL; - conn->state = NETCONN_NONE; - conn->socket = 0; - conn->callback = callback; - conn->recv_avail = 0; - - if((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - memp_free(MEMP_NETCONN, conn); - return NULL; - } - - msg->type = API_MSG_NEWCONN; - msg->msg.msg.bc.port = proto; /* misusing the port field */ - msg->msg.conn = conn; - api_msg_post(msg); - sys_mbox_fetch(conn->mbox, NULL); - memp_free(MEMP_API_MSG, msg); - - if ( conn->err != ERR_OK ) { - memp_free(MEMP_NETCONN, conn); - return NULL; - } - - return conn; -} - - -struct -netconn *netconn_new(enum netconn_type t) -{ - return netconn_new_with_proto_and_callback(t,0,NULL); -} - -struct -netconn *netconn_new_with_callback(enum netconn_type t, - void (*callback)(struct netconn *, enum netconn_evt, u16_t len)) -{ - return netconn_new_with_proto_and_callback(t,0,callback); -} - - -err_t -netconn_delete(struct netconn *conn) -{ - struct api_msg *msg; - void *mem; - - if (conn == NULL) { - return ERR_OK; - } - - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - return ERR_MEM; - } - - msg->type = API_MSG_DELCONN; - msg->msg.conn = conn; - api_msg_post(msg); - sys_mbox_fetch(conn->mbox, NULL); - memp_free(MEMP_API_MSG, msg); - - /* Drain the recvmbox. */ - if (conn->recvmbox != SYS_MBOX_NULL) { - while (sys_arch_mbox_fetch(conn->recvmbox, &mem, 1) != SYS_ARCH_TIMEOUT) { - if (conn->type == NETCONN_TCP) { - if(mem != NULL) - pbuf_free((struct pbuf *)mem); - } else { - netbuf_delete((struct netbuf *)mem); - } - } - sys_mbox_free(conn->recvmbox); - conn->recvmbox = SYS_MBOX_NULL; - } - - - /* Drain the acceptmbox. */ - if (conn->acceptmbox != SYS_MBOX_NULL) { - while (sys_arch_mbox_fetch(conn->acceptmbox, &mem, 1) != SYS_ARCH_TIMEOUT) { - netconn_delete((struct netconn *)mem); - } - - sys_mbox_free(conn->acceptmbox); - conn->acceptmbox = SYS_MBOX_NULL; - } - - sys_mbox_free(conn->mbox); - conn->mbox = SYS_MBOX_NULL; - if (conn->sem != SYS_SEM_NULL) { - sys_sem_free(conn->sem); - } - /* conn->sem = SYS_SEM_NULL;*/ - memp_free(MEMP_NETCONN, conn); - return ERR_OK; -} - -enum netconn_type -netconn_type(struct netconn *conn) -{ - return conn->type; -} - -err_t -netconn_peer(struct netconn *conn, struct ip_addr *addr, - u16_t *port) -{ - switch (conn->type) { - case NETCONN_RAW: - /* return an error as connecting is only a helper for upper layers */ - return ERR_CONN; - case NETCONN_UDPLITE: - case NETCONN_UDPNOCHKSUM: - case NETCONN_UDP: - if (conn->pcb.udp == NULL || - ((conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0)) - return ERR_CONN; - *addr = (conn->pcb.udp->remote_ip); - *port = conn->pcb.udp->remote_port; - break; - case NETCONN_TCP: - if (conn->pcb.tcp == NULL) - return ERR_CONN; - *addr = (conn->pcb.tcp->remote_ip); - *port = conn->pcb.tcp->remote_port; - break; - } - return (conn->err = ERR_OK); -} - -err_t -netconn_addr(struct netconn *conn, struct ip_addr **addr, - u16_t *port) -{ - switch (conn->type) { - case NETCONN_RAW: - *addr = &(conn->pcb.raw->local_ip); - *port = conn->pcb.raw->protocol; - break; - case NETCONN_UDPLITE: - case NETCONN_UDPNOCHKSUM: - case NETCONN_UDP: - *addr = &(conn->pcb.udp->local_ip); - *port = conn->pcb.udp->local_port; - break; - case NETCONN_TCP: - *addr = &(conn->pcb.tcp->local_ip); - *port = conn->pcb.tcp->local_port; - break; - } - return (conn->err = ERR_OK); -} - -err_t -netconn_bind(struct netconn *conn, struct ip_addr *addr, - u16_t port) -{ - struct api_msg *msg; - - if (conn == NULL) { - return ERR_VAL; - } - - if (conn->type != NETCONN_TCP && - conn->recvmbox == SYS_MBOX_NULL) { - if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) { - return ERR_MEM; - } - } - - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - return (conn->err = ERR_MEM); - } - msg->type = API_MSG_BIND; - msg->msg.conn = conn; - msg->msg.msg.bc.ipaddr = addr; - msg->msg.msg.bc.port = port; - api_msg_post(msg); - sys_mbox_fetch(conn->mbox, NULL); - memp_free(MEMP_API_MSG, msg); - return conn->err; -} - - -err_t -netconn_connect(struct netconn *conn, struct ip_addr *addr, - u16_t port) -{ - struct api_msg *msg; - - if (conn == NULL) { - return ERR_VAL; - } - - - if (conn->recvmbox == SYS_MBOX_NULL) { - if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) { - return ERR_MEM; - } - } - - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - return ERR_MEM; - } - msg->type = API_MSG_CONNECT; - msg->msg.conn = conn; - msg->msg.msg.bc.ipaddr = addr; - msg->msg.msg.bc.port = port; - api_msg_post(msg); - sys_mbox_fetch(conn->mbox, NULL); - memp_free(MEMP_API_MSG, msg); - return conn->err; -} - -err_t -netconn_disconnect(struct netconn *conn) -{ - struct api_msg *msg; - - if (conn == NULL) { - return ERR_VAL; - } - - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - return ERR_MEM; - } - msg->type = API_MSG_DISCONNECT; - msg->msg.conn = conn; - api_msg_post(msg); - sys_mbox_fetch(conn->mbox, NULL); - memp_free(MEMP_API_MSG, msg); - return conn->err; - -} - -err_t -netconn_listen(struct netconn *conn) -{ - struct api_msg *msg; - - if (conn == NULL) { - return ERR_VAL; - } - - if (conn->acceptmbox == SYS_MBOX_NULL) { - conn->acceptmbox = sys_mbox_new(); - if (conn->acceptmbox == SYS_MBOX_NULL) { - return ERR_MEM; - } - } - - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - return (conn->err = ERR_MEM); - } - msg->type = API_MSG_LISTEN; - msg->msg.conn = conn; - api_msg_post(msg); - sys_mbox_fetch(conn->mbox, NULL); - memp_free(MEMP_API_MSG, msg); - return conn->err; -} - -struct netconn * -netconn_accept(struct netconn *conn) -{ - struct netconn *newconn; - - if (conn == NULL) { - return NULL; - } - - sys_mbox_fetch(conn->acceptmbox, (void **)&newconn); - /* Register event with callback */ - if (conn->callback) - (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, 0); - - return newconn; -} - -struct netbuf * -netconn_recv(struct netconn *conn) -{ - struct api_msg *msg; - struct netbuf *buf; - struct pbuf *p; - u16_t len; - - if (conn == NULL) { - return NULL; - } - - if (conn->recvmbox == SYS_MBOX_NULL) { - conn->err = ERR_CONN; - return NULL; - } - - if (conn->err != ERR_OK) { - return NULL; - } - - if (conn->type == NETCONN_TCP) { - if (conn->pcb.tcp->state == LISTEN) { - conn->err = ERR_CONN; - return NULL; - } - - - buf = memp_malloc(MEMP_NETBUF); - - if (buf == NULL) { - conn->err = ERR_MEM; - return NULL; - } - - sys_mbox_fetch(conn->recvmbox, (void **)&p); - - if (p != NULL) - { - len = p->tot_len; - conn->recv_avail -= len; - } - else - len = 0; - - /* Register event with callback */ - if (conn->callback) - (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, len); - - /* If we are closed, we indicate that we no longer wish to receive - data by setting conn->recvmbox to SYS_MBOX_NULL. */ - if (p == NULL) { - memp_free(MEMP_NETBUF, buf); - sys_mbox_free(conn->recvmbox); - conn->recvmbox = SYS_MBOX_NULL; - return NULL; - } - - buf->p = p; - buf->ptr = p; - buf->fromport = 0; - buf->fromaddr = NULL; - - /* Let the stack know that we have taken the data. */ - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - conn->err = ERR_MEM; - return buf; - } - msg->type = API_MSG_RECV; - msg->msg.conn = conn; - if (buf != NULL) { - msg->msg.msg.len = buf->p->tot_len; - } else { - msg->msg.msg.len = 1; - } - api_msg_post(msg); - - sys_mbox_fetch(conn->mbox, NULL); - memp_free(MEMP_API_MSG, msg); - } else { - sys_mbox_fetch(conn->recvmbox, (void **)&buf); - conn->recv_avail -= buf->p->tot_len; - /* Register event with callback */ - if (conn->callback) - (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, buf->p->tot_len); - } - - - - - LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv: received %p (err %d)\n", (void *)buf, conn->err)); - - - return buf; -} - -err_t -netconn_send(struct netconn *conn, struct netbuf *buf) -{ - struct api_msg *msg; - - if (conn == NULL) { - return ERR_VAL; - } - - if (conn->err != ERR_OK) { - return conn->err; - } - - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - return (conn->err = ERR_MEM); - } - - LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %d bytes\n", buf->p->tot_len)); - msg->type = API_MSG_SEND; - msg->msg.conn = conn; - msg->msg.msg.p = buf->p; - api_msg_post(msg); - - sys_mbox_fetch(conn->mbox, NULL); - memp_free(MEMP_API_MSG, msg); - return conn->err; -} - -err_t -netconn_write(struct netconn *conn, void *dataptr, u16_t size, u8_t copy) -{ - struct api_msg *msg; - u16_t len; - - if (conn == NULL) { - return ERR_VAL; - } - - if (conn->err != ERR_OK) { - return conn->err; - } - - if (conn->sem == SYS_SEM_NULL) { - conn->sem = sys_sem_new(0); - if (conn->sem == SYS_SEM_NULL) { - return ERR_MEM; - } - } - - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - return (conn->err = ERR_MEM); - } - msg->type = API_MSG_WRITE; - msg->msg.conn = conn; - - - conn->state = NETCONN_WRITE; - while (conn->err == ERR_OK && size > 0) { - msg->msg.msg.w.dataptr = dataptr; - msg->msg.msg.w.copy = copy; - - if (conn->type == NETCONN_TCP) { - if (tcp_sndbuf(conn->pcb.tcp) == 0) { - sys_sem_wait(conn->sem); - if (conn->err != ERR_OK) { - goto ret; - } - } - if (size > tcp_sndbuf(conn->pcb.tcp)) { - /* We cannot send more than one send buffer's worth of data at a - time. */ - len = tcp_sndbuf(conn->pcb.tcp); - } else { - len = size; - } - } else { - len = size; - } - - LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_write: writing %d bytes (%d)\n", len, copy)); - msg->msg.msg.w.len = len; - api_msg_post(msg); - sys_mbox_fetch(conn->mbox, NULL); - if (conn->err == ERR_OK) { - dataptr = (void *)((u8_t *)dataptr + len); - size -= len; - } else if (conn->err == ERR_MEM) { - conn->err = ERR_OK; - sys_sem_wait(conn->sem); - } else { - goto ret; - } - } - ret: - memp_free(MEMP_API_MSG, msg); - conn->state = NETCONN_NONE; - if (conn->sem != SYS_SEM_NULL) { - sys_sem_free(conn->sem); - conn->sem = SYS_SEM_NULL; - } - - return conn->err; -} - -err_t -netconn_close(struct netconn *conn) -{ - struct api_msg *msg; - - if (conn == NULL) { - return ERR_VAL; - } - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - return (conn->err = ERR_MEM); - } - - conn->state = NETCONN_CLOSE; - again: - msg->type = API_MSG_CLOSE; - msg->msg.conn = conn; - api_msg_post(msg); - sys_mbox_fetch(conn->mbox, NULL); - if (conn->err == ERR_MEM && - conn->sem != SYS_SEM_NULL) { - sys_sem_wait(conn->sem); - goto again; - } - conn->state = NETCONN_NONE; - memp_free(MEMP_API_MSG, msg); - return conn->err; -} - -err_t -netconn_err(struct netconn *conn) -{ - return conn->err; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/api/api_msg.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/api/api_msg.c deleted file mode 100644 index 0cbe626fb..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/api/api_msg.c +++ /dev/null @@ -1,800 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" -#include "lwip/arch.h" -#include "lwip/api_msg.h" -#include "lwip/memp.h" -#include "lwip/sys.h" -#include "lwip/tcpip.h" - -#if LWIP_RAW -static u8_t -recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p, - struct ip_addr *addr) -{ - struct netbuf *buf; - struct netconn *conn; - - conn = arg; - if (!conn) return 0; - - if (conn->recvmbox != SYS_MBOX_NULL) { - if (!(buf = memp_malloc(MEMP_NETBUF))) { - return 0; - } - pbuf_ref(p); - buf->p = p; - buf->ptr = p; - buf->fromaddr = addr; - buf->fromport = pcb->protocol; - - conn->recv_avail += p->tot_len; - /* Register event with callback */ - if (conn->callback) - (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len); - sys_mbox_post(conn->recvmbox, buf); - } - - return 0; /* do not eat the packet */ -} -#endif -#if LWIP_UDP -static void -recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p, - struct ip_addr *addr, u16_t port) -{ - struct netbuf *buf; - struct netconn *conn; - - conn = arg; - - if (conn == NULL) { - pbuf_free(p); - return; - } - if (conn->recvmbox != SYS_MBOX_NULL) { - buf = memp_malloc(MEMP_NETBUF); - if (buf == NULL) { - pbuf_free(p); - return; - } else { - buf->p = p; - buf->ptr = p; - buf->fromaddr = addr; - buf->fromport = port; - } - - conn->recv_avail += p->tot_len; - /* Register event with callback */ - if (conn->callback) - (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len); - sys_mbox_post(conn->recvmbox, buf); - } -} -#endif /* LWIP_UDP */ -#if LWIP_TCP - -static err_t -recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) -{ - struct netconn *conn; - u16_t len; - - conn = arg; - - if (conn == NULL) { - pbuf_free(p); - return ERR_VAL; - } - - if (conn->recvmbox != SYS_MBOX_NULL) { - - conn->err = err; - if (p != NULL) { - len = p->tot_len; - conn->recv_avail += len; - } - else - len = 0; - /* Register event with callback */ - if (conn->callback) - (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, len); - sys_mbox_post(conn->recvmbox, p); - } - return ERR_OK; -} - - -static err_t -poll_tcp(void *arg, struct tcp_pcb *pcb) -{ - struct netconn *conn; - - conn = arg; - if (conn != NULL && - (conn->state == NETCONN_WRITE || conn->state == NETCONN_CLOSE) && - conn->sem != SYS_SEM_NULL) { - sys_sem_signal(conn->sem); - } - return ERR_OK; -} - -static err_t -sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len) -{ - struct netconn *conn; - - conn = arg; - if (conn != NULL && conn->sem != SYS_SEM_NULL) { - sys_sem_signal(conn->sem); - } - - if (conn && conn->callback) - if (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) - (*conn->callback)(conn, NETCONN_EVT_SENDPLUS, len); - - return ERR_OK; -} - -static void -err_tcp(void *arg, err_t err) -{ - struct netconn *conn; - - conn = arg; - - conn->pcb.tcp = NULL; - - - conn->err = err; - if (conn->recvmbox != SYS_MBOX_NULL) { - /* Register event with callback */ - if (conn->callback) - (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0); - sys_mbox_post(conn->recvmbox, NULL); - } - if (conn->mbox != SYS_MBOX_NULL) { - sys_mbox_post(conn->mbox, NULL); - } - if (conn->acceptmbox != SYS_MBOX_NULL) { - /* Register event with callback */ - if (conn->callback) - (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0); - sys_mbox_post(conn->acceptmbox, NULL); - } - if (conn->sem != SYS_SEM_NULL) { - sys_sem_signal(conn->sem); - } -} - -static void -setup_tcp(struct netconn *conn) -{ - struct tcp_pcb *pcb; - - pcb = conn->pcb.tcp; - tcp_arg(pcb, conn); - tcp_recv(pcb, recv_tcp); - tcp_sent(pcb, sent_tcp); - tcp_poll(pcb, poll_tcp, 4); - tcp_err(pcb, err_tcp); -} - -static err_t -accept_function(void *arg, struct tcp_pcb *newpcb, err_t err) -{ - sys_mbox_t mbox; - struct netconn *newconn; - struct netconn *conn; - -#if API_MSG_DEBUG -#if TCP_DEBUG - tcp_debug_print_state(newpcb->state); -#endif /* TCP_DEBUG */ -#endif /* API_MSG_DEBUG */ - conn = (struct netconn *)arg; - mbox = conn->acceptmbox; - newconn = memp_malloc(MEMP_NETCONN); - if (newconn == NULL) { - return ERR_MEM; - } - newconn->type = NETCONN_TCP; - newconn->pcb.tcp = newpcb; - setup_tcp(newconn); - newconn->recvmbox = sys_mbox_new(); - if (newconn->recvmbox == SYS_MBOX_NULL) { - memp_free(MEMP_NETCONN, newconn); - return ERR_MEM; - } - newconn->mbox = sys_mbox_new(); - if (newconn->mbox == SYS_MBOX_NULL) { - sys_mbox_free(newconn->recvmbox); - memp_free(MEMP_NETCONN, newconn); - return ERR_MEM; - } - newconn->sem = sys_sem_new(0); - if (newconn->sem == SYS_SEM_NULL) { - sys_mbox_free(newconn->recvmbox); - sys_mbox_free(newconn->mbox); - memp_free(MEMP_NETCONN, newconn); - return ERR_MEM; - } - newconn->acceptmbox = SYS_MBOX_NULL; - newconn->err = err; - /* Register event with callback */ - if (conn->callback) - { - (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0); - /* We have to set the callback here even though - * the new socket is unknown. Mark the socket as -1. */ - newconn->callback = conn->callback; - newconn->socket = -1; - } - - sys_mbox_post(mbox, newconn); - return ERR_OK; -} -#endif /* LWIP_TCP */ - -static void -do_newconn(struct api_msg_msg *msg) -{ - if(msg->conn->pcb.tcp != NULL) { - /* This "new" connection already has a PCB allocated. */ - /* Is this an error condition? Should it be deleted? - We currently just are happy and return. */ - sys_mbox_post(msg->conn->mbox, NULL); - return; - } - - msg->conn->err = ERR_OK; - - /* Allocate a PCB for this connection */ - switch(msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field */ - raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - msg->conn->pcb.udp = udp_new(); - if(msg->conn->pcb.udp == NULL) { - msg->conn->err = ERR_MEM; - break; - } - udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; - case NETCONN_UDPNOCHKSUM: - msg->conn->pcb.udp = udp_new(); - if(msg->conn->pcb.udp == NULL) { - msg->conn->err = ERR_MEM; - break; - } - udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; - case NETCONN_UDP: - msg->conn->pcb.udp = udp_new(); - if(msg->conn->pcb.udp == NULL) { - msg->conn->err = ERR_MEM; - break; - } - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - msg->conn->pcb.tcp = tcp_new(); - if(msg->conn->pcb.tcp == NULL) { - msg->conn->err = ERR_MEM; - break; - } - setup_tcp(msg->conn); - break; -#endif - } - - - sys_mbox_post(msg->conn->mbox, NULL); -} - - -static void -do_delconn(struct api_msg_msg *msg) -{ - if (msg->conn->pcb.tcp != NULL) { - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - raw_remove(msg->conn->pcb.raw); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - msg->conn->pcb.udp->recv_arg = NULL; - udp_remove(msg->conn->pcb.udp); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - if (msg->conn->pcb.tcp->state == LISTEN) { - tcp_arg(msg->conn->pcb.tcp, NULL); - tcp_accept(msg->conn->pcb.tcp, NULL); - tcp_close(msg->conn->pcb.tcp); - } else { - tcp_arg(msg->conn->pcb.tcp, NULL); - tcp_sent(msg->conn->pcb.tcp, NULL); - tcp_recv(msg->conn->pcb.tcp, NULL); - tcp_poll(msg->conn->pcb.tcp, NULL, 0); - tcp_err(msg->conn->pcb.tcp, NULL); - if (tcp_close(msg->conn->pcb.tcp) != ERR_OK) { - tcp_abort(msg->conn->pcb.tcp); - } - } -#endif - default: - break; - } - } - /* Trigger select() in socket layer */ - if (msg->conn->callback) - { - (*msg->conn->callback)(msg->conn, NETCONN_EVT_RCVPLUS, 0); - (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDPLUS, 0); - } - - if (msg->conn->mbox != SYS_MBOX_NULL) { - sys_mbox_post(msg->conn->mbox, NULL); - } -} - -static void -do_bind(struct api_msg_msg *msg) -{ - if (msg->conn->pcb.tcp == NULL) { - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */ - raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - msg->conn->pcb.udp = udp_new(); - udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; - case NETCONN_UDPNOCHKSUM: - msg->conn->pcb.udp = udp_new(); - udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; - case NETCONN_UDP: - msg->conn->pcb.udp = udp_new(); - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - msg->conn->pcb.tcp = tcp_new(); - setup_tcp(msg->conn); -#endif /* LWIP_TCP */ - default: - break; - } - } - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - msg->conn->err = raw_bind(msg->conn->pcb.raw,msg->msg.bc.ipaddr); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - msg->conn->err = udp_bind(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - msg->conn->err = tcp_bind(msg->conn->pcb.tcp, - msg->msg.bc.ipaddr, msg->msg.bc.port); -#endif /* LWIP_TCP */ - default: - break; - } - sys_mbox_post(msg->conn->mbox, NULL); -} -#if LWIP_TCP - -static err_t -do_connected(void *arg, struct tcp_pcb *pcb, err_t err) -{ - struct netconn *conn; - - conn = arg; - - if (conn == NULL) { - return ERR_VAL; - } - - conn->err = err; - if (conn->type == NETCONN_TCP && err == ERR_OK) { - setup_tcp(conn); - } - sys_mbox_post(conn->mbox, NULL); - return ERR_OK; -} -#endif - -static void -do_connect(struct api_msg_msg *msg) -{ - if (msg->conn->pcb.tcp == NULL) { - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */ - raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - msg->conn->pcb.udp = udp_new(); - if (msg->conn->pcb.udp == NULL) { - msg->conn->err = ERR_MEM; - sys_mbox_post(msg->conn->mbox, NULL); - return; - } - udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; - case NETCONN_UDPNOCHKSUM: - msg->conn->pcb.udp = udp_new(); - if (msg->conn->pcb.udp == NULL) { - msg->conn->err = ERR_MEM; - sys_mbox_post(msg->conn->mbox, NULL); - return; - } - udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; - case NETCONN_UDP: - msg->conn->pcb.udp = udp_new(); - if (msg->conn->pcb.udp == NULL) { - msg->conn->err = ERR_MEM; - sys_mbox_post(msg->conn->mbox, NULL); - return; - } - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - msg->conn->pcb.tcp = tcp_new(); - if (msg->conn->pcb.tcp == NULL) { - msg->conn->err = ERR_MEM; - sys_mbox_post(msg->conn->mbox, NULL); - return; - } -#endif - default: - break; - } - } - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - raw_connect(msg->conn->pcb.raw, msg->msg.bc.ipaddr); - sys_mbox_post(msg->conn->mbox, NULL); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - udp_connect(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port); - sys_mbox_post(msg->conn->mbox, NULL); - break; -#endif -#if LWIP_TCP - case NETCONN_TCP: - /* tcp_arg(msg->conn->pcb.tcp, msg->conn);*/ - setup_tcp(msg->conn); - tcp_connect(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port, - do_connected); - /*tcp_output(msg->conn->pcb.tcp);*/ -#endif - - default: - break; - } -} - -static void -do_disconnect(struct api_msg_msg *msg) -{ - - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - /* Do nothing as connecting is only a helper for upper lwip layers */ - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - udp_disconnect(msg->conn->pcb.udp); - break; -#endif - case NETCONN_TCP: - break; - } - sys_mbox_post(msg->conn->mbox, NULL); -} - - -static void -do_listen(struct api_msg_msg *msg) -{ - if (msg->conn->pcb.tcp != NULL) { - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen RAW: cannot listen for RAW.\n")); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen UDP: cannot listen for UDP.\n")); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - msg->conn->pcb.tcp = tcp_listen(msg->conn->pcb.tcp); - if (msg->conn->pcb.tcp == NULL) { - msg->conn->err = ERR_MEM; - } else { - if (msg->conn->acceptmbox == SYS_MBOX_NULL) { - msg->conn->acceptmbox = sys_mbox_new(); - if (msg->conn->acceptmbox == SYS_MBOX_NULL) { - msg->conn->err = ERR_MEM; - break; - } - } - tcp_arg(msg->conn->pcb.tcp, msg->conn); - tcp_accept(msg->conn->pcb.tcp, accept_function); - } -#endif - default: - break; - } - } - sys_mbox_post(msg->conn->mbox, NULL); -} - -static void -do_accept(struct api_msg_msg *msg) -{ - if (msg->conn->pcb.tcp != NULL) { - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept RAW: cannot accept for RAW.\n")); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept UDP: cannot accept for UDP.\n")); - break; -#endif /* LWIP_UDP */ - case NETCONN_TCP: - break; - } - } -} - -static void -do_send(struct api_msg_msg *msg) -{ - if (msg->conn->pcb.tcp != NULL) { - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - raw_send(msg->conn->pcb.raw, msg->msg.p); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - udp_send(msg->conn->pcb.udp, msg->msg.p); - break; -#endif /* LWIP_UDP */ - case NETCONN_TCP: - break; - } - } - sys_mbox_post(msg->conn->mbox, NULL); -} - -static void -do_recv(struct api_msg_msg *msg) -{ -#if LWIP_TCP - if (msg->conn->pcb.tcp != NULL) { - if (msg->conn->type == NETCONN_TCP) { - tcp_recved(msg->conn->pcb.tcp, msg->msg.len); - } - } -#endif - sys_mbox_post(msg->conn->mbox, NULL); -} - -static void -do_write(struct api_msg_msg *msg) -{ -#if LWIP_TCP - err_t err; -#endif - if (msg->conn->pcb.tcp != NULL) { - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - msg->conn->err = ERR_VAL; - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - msg->conn->err = ERR_VAL; - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - err = tcp_write(msg->conn->pcb.tcp, msg->msg.w.dataptr, - msg->msg.w.len, msg->msg.w.copy); - /* This is the Nagle algorithm: inhibit the sending of new TCP - segments when new outgoing data arrives from the user if any - previously transmitted data on the connection remains - unacknowledged. */ - if(err == ERR_OK && (msg->conn->pcb.tcp->unacked == NULL || (msg->conn->pcb.tcp->flags & TF_NODELAY)) ) { - tcp_output(msg->conn->pcb.tcp); - } - msg->conn->err = err; - if (msg->conn->callback) - if (err == ERR_OK) - { - if (tcp_sndbuf(msg->conn->pcb.tcp) <= TCP_SNDLOWAT) - (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDMINUS, msg->msg.w.len); - } -#endif - default: - break; - } - } - sys_mbox_post(msg->conn->mbox, NULL); -} - -static void -do_close(struct api_msg_msg *msg) -{ - err_t err; - - err = ERR_OK; - - if (msg->conn->pcb.tcp != NULL) { - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - if (msg->conn->pcb.tcp->state == LISTEN) { - err = tcp_close(msg->conn->pcb.tcp); - } - msg->conn->err = err; -#endif - default: - break; - } - } - sys_mbox_post(msg->conn->mbox, NULL); -} - -typedef void (* api_msg_decode)(struct api_msg_msg *msg); -static api_msg_decode decode[API_MSG_MAX] = { - do_newconn, - do_delconn, - do_bind, - do_connect, - do_disconnect, - do_listen, - do_accept, - do_send, - do_recv, - do_write, - do_close - }; -void -api_msg_input(struct api_msg *msg) -{ - decode[msg->type](&(msg->msg)); -} - -void -api_msg_post(struct api_msg *msg) -{ - tcpip_apimsg(msg); -} - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/api/err.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/api/err.c deleted file mode 100644 index b582d88a2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/api/err.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/err.h" - -#ifdef LWIP_DEBUG - -static char *err_strerr[] = {"Ok.", - "Out of memory error.", - "Buffer error.", - "Connection aborted.", - "Connection reset.", - "Connection closed.", - "Not connected.", - "Illegal value.", - "Illegal argument.", - "Routing problem.", - "Address in use." -}; - - -char * -lwip_strerr(err_t err) -{ - return err_strerr[-err]; - -} - - -#endif /* LWIP_DEBUG */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/api/sockets.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/api/sockets.c deleted file mode 100644 index 290a7b737..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/api/sockets.c +++ /dev/null @@ -1,1362 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * Improved by Marc Boucher and David Haas - * - */ - -#include -#include - -#include "lwip/opt.h" -#include "lwip/api.h" -#include "lwip/arch.h" -#include "lwip/sys.h" - -#include "lwip/sockets.h" - -#define NUM_SOCKETS MEMP_NUM_NETCONN - -struct lwip_socket { - struct netconn *conn; - struct netbuf *lastdata; - u16_t lastoffset; - u16_t rcvevent; - u16_t sendevent; - u16_t flags; - int err; -}; - -struct lwip_select_cb -{ - struct lwip_select_cb *next; - fd_set *readset; - fd_set *writeset; - fd_set *exceptset; - int sem_signalled; - sys_sem_t sem; -}; - -static struct lwip_socket sockets[NUM_SOCKETS]; -static struct lwip_select_cb *select_cb_list = 0; - -static sys_sem_t socksem = 0; -static sys_sem_t selectsem = 0; - -static void -event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len); - -static int err_to_errno_table[11] = { - 0, /* ERR_OK 0 No error, everything OK. */ - ENOMEM, /* ERR_MEM -1 Out of memory error. */ - ENOBUFS, /* ERR_BUF -2 Buffer error. */ - ECONNABORTED, /* ERR_ABRT -3 Connection aborted. */ - ECONNRESET, /* ERR_RST -4 Connection reset. */ - ESHUTDOWN, /* ERR_CLSD -5 Connection closed. */ - ENOTCONN, /* ERR_CONN -6 Not connected. */ - EINVAL, /* ERR_VAL -7 Illegal value. */ - EIO, /* ERR_ARG -8 Illegal argument. */ - EHOSTUNREACH, /* ERR_RTE -9 Routing problem. */ - EADDRINUSE /* ERR_USE -10 Address in use. */ -}; - -#define ERR_TO_ERRNO_TABLE_SIZE \ - (sizeof(err_to_errno_table)/sizeof(err_to_errno_table[0])) - -#define err_to_errno(err) \ - (-(err) >= 0 && -(err) < ERR_TO_ERRNO_TABLE_SIZE ? \ - err_to_errno_table[-(err)] : EIO) - -#ifdef ERRNO -#define set_errno(err) errno = (err) -#else -#define set_errno(err) -#endif - -#define sock_set_errno(sk, e) do { \ - sk->err = (e); \ - set_errno(sk->err); \ -} while (0) - - -static struct lwip_socket * -get_socket(int s) -{ - struct lwip_socket *sock; - - if ((s < 0) || (s > NUM_SOCKETS)) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s)); - set_errno(EBADF); - return NULL; - } - - sock = &sockets[s]; - - if (!sock->conn) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s)); - set_errno(EBADF); - return NULL; - } - - return sock; -} - -static int -alloc_socket(struct netconn *newconn) -{ - int i; - - if (!socksem) - socksem = sys_sem_new(1); - - /* Protect socket array */ - sys_sem_wait(socksem); - - /* allocate a new socket identifier */ - for(i = 0; i < NUM_SOCKETS; ++i) { - if (!sockets[i].conn) { - sockets[i].conn = newconn; - sockets[i].lastdata = NULL; - sockets[i].lastoffset = 0; - sockets[i].rcvevent = 0; - sockets[i].sendevent = 1; /* TCP send buf is empty */ - sockets[i].flags = 0; - sockets[i].err = 0; - sys_sem_signal(socksem); - return i; - } - } - sys_sem_signal(socksem); - return -1; -} - -int -lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen) -{ - struct lwip_socket *sock; - struct netconn *newconn; - struct ip_addr naddr; - u16_t port; - int newsock; - struct sockaddr_in sin; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s)); - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - newconn = netconn_accept(sock->conn); - - /* get the IP address and port of the remote host */ - netconn_peer(newconn, &naddr, &port); - - memset(&sin, 0, sizeof(sin)); - sin.sin_len = sizeof(sin); - sin.sin_family = AF_INET; - sin.sin_port = htons(port); - sin.sin_addr.s_addr = naddr.addr; - - if (*addrlen > sizeof(sin)) - *addrlen = sizeof(sin); - - memcpy(addr, &sin, *addrlen); - - newsock = alloc_socket(newconn); - if (newsock == -1) { - netconn_delete(newconn); - sock_set_errno(sock, ENOBUFS); - return -1; - } - newconn->callback = event_callback; - sock = get_socket(newsock); - - sys_sem_wait(socksem); - sock->rcvevent += -1 - newconn->socket; - newconn->socket = newsock; - sys_sem_signal(socksem); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock)); - ip_addr_debug_print(SOCKETS_DEBUG, &naddr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", port)); - - sock_set_errno(sock, 0); - return newsock; -} - -int -lwip_bind(int s, struct sockaddr *name, socklen_t namelen) -{ - struct lwip_socket *sock; - struct ip_addr local_addr; - u16_t local_port; - err_t err; - - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - local_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr; - local_port = ((struct sockaddr_in *)name)->sin_port; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s)); - ip_addr_debug_print(SOCKETS_DEBUG, &local_addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(local_port))); - - err = netconn_bind(sock->conn, &local_addr, ntohs(local_port)); - - if (err != ERR_OK) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err)); - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s)); - sock_set_errno(sock, 0); - return 0; -} - -int -lwip_close(int s) -{ - struct lwip_socket *sock; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s)); - if (!socksem) - socksem = sys_sem_new(1); - - /* We cannot allow multiple closes of the same socket. */ - sys_sem_wait(socksem); - - sock = get_socket(s); - if (!sock) { - sys_sem_signal(socksem); - set_errno(EBADF); - return -1; - } - - netconn_delete(sock->conn); - if (sock->lastdata) { - netbuf_delete(sock->lastdata); - } - sock->lastdata = NULL; - sock->lastoffset = 0; - sock->conn = NULL; - sys_sem_signal(socksem); - sock_set_errno(sock, 0); - return 0; -} - -int -lwip_connect(int s, struct sockaddr *name, socklen_t namelen) -{ - struct lwip_socket *sock; - err_t err; - - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - if (((struct sockaddr_in *)name)->sin_family == AF_UNSPEC) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s)); - err = netconn_disconnect(sock->conn); - } else { - struct ip_addr remote_addr; - u16_t remote_port; - - remote_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr; - remote_port = ((struct sockaddr_in *)name)->sin_port; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s)); - ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(remote_port))); - - err = netconn_connect(sock->conn, &remote_addr, ntohs(remote_port)); - } - - if (err != ERR_OK) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err)); - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s)); - sock_set_errno(sock, 0); - return 0; -} - -int -lwip_listen(int s, int backlog) -{ - struct lwip_socket *sock; - err_t err; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog)); - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - err = netconn_listen(sock->conn); - - if (err != ERR_OK) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err)); - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - - sock_set_errno(sock, 0); - return 0; -} - -int -lwip_recvfrom(int s, void *mem, int len, unsigned int flags, - struct sockaddr *from, socklen_t *fromlen) -{ - struct lwip_socket *sock; - struct netbuf *buf; - u16_t buflen, copylen; - struct ip_addr *addr; - u16_t port; - - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %d, 0x%x, ..)\n", s, mem, len, flags)); - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - /* Check if there is data left from the last recv operation. */ - if (sock->lastdata) { - buf = sock->lastdata; - } else { - /* If this is non-blocking call, then check first */ - if (((flags & MSG_DONTWAIT) || (sock->flags & O_NONBLOCK)) - && !sock->rcvevent) - { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s)); - sock_set_errno(sock, EWOULDBLOCK); - return -1; - } - - /* No data was left from the previous operation, so we try to get - some from the network. */ - buf = netconn_recv(sock->conn); - - if (!buf) { - /* We should really do some error checking here. */ - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL!\n", s)); - sock_set_errno(sock, 0); - return 0; - } - } - - buflen = netbuf_len(buf); - - buflen -= sock->lastoffset; - - if (len > buflen) { - copylen = buflen; - } else { - copylen = len; - } - - /* copy the contents of the received buffer into - the supplied memory pointer mem */ - netbuf_copy_partial(buf, mem, copylen, sock->lastoffset); - - /* Check to see from where the data was. */ - if (from && fromlen) { - struct sockaddr_in sin; - - addr = netbuf_fromaddr(buf); - port = netbuf_fromport(buf); - - memset(&sin, 0, sizeof(sin)); - sin.sin_len = sizeof(sin); - sin.sin_family = AF_INET; - sin.sin_port = htons(port); - sin.sin_addr.s_addr = addr->addr; - - if (*fromlen > sizeof(sin)) - *fromlen = sizeof(sin); - - memcpy(from, &sin, *fromlen); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s)); - ip_addr_debug_print(SOCKETS_DEBUG, addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen)); - } else { -#if SOCKETS_DEBUG - addr = netbuf_fromaddr(buf); - port = netbuf_fromport(buf); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s)); - ip_addr_debug_print(SOCKETS_DEBUG, addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen)); -#endif - - } - - /* If this is a TCP socket, check if there is data left in the - buffer. If so, it should be saved in the sock structure for next - time around. */ - if (netconn_type(sock->conn) == NETCONN_TCP && buflen - copylen > 0) { - sock->lastdata = buf; - sock->lastoffset += copylen; - } else { - sock->lastdata = NULL; - sock->lastoffset = 0; - netbuf_delete(buf); - } - - - sock_set_errno(sock, 0); - return copylen; -} - -int -lwip_read(int s, void *mem, int len) -{ - return lwip_recvfrom(s, mem, len, 0, NULL, NULL); -} - -int -lwip_recv(int s, void *mem, int len, unsigned int flags) -{ - return lwip_recvfrom(s, mem, len, flags, NULL, NULL); -} - -int -lwip_send(int s, void *data, int size, unsigned int flags) -{ - struct lwip_socket *sock; - struct netbuf *buf; - err_t err; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%d, flags=0x%x)\n", s, data, size, flags)); - - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - switch (netconn_type(sock->conn)) { - case NETCONN_RAW: - case NETCONN_UDP: - case NETCONN_UDPLITE: - case NETCONN_UDPNOCHKSUM: - /* create a buffer */ - buf = netbuf_new(); - - if (!buf) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ENOBUFS\n", s)); - sock_set_errno(sock, ENOBUFS); - return -1; - } - - /* make the buffer point to the data that should - be sent */ - netbuf_ref(buf, data, size); - - /* send the data */ - err = netconn_send(sock->conn, buf); - - /* deallocated the buffer */ - netbuf_delete(buf); - break; - case NETCONN_TCP: - err = netconn_write(sock->conn, data, size, NETCONN_COPY); - break; - default: - err = ERR_ARG; - break; - } - if (err != ERR_OK) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d\n", s, err)); - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ok size=%d\n", s, size)); - sock_set_errno(sock, 0); - return size; -} - -int -lwip_sendto(int s, void *data, int size, unsigned int flags, - struct sockaddr *to, socklen_t tolen) -{ - struct lwip_socket *sock; - struct ip_addr remote_addr, addr; - u16_t remote_port, port; - int ret,connected; - - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - /* get the peer if currently connected */ - connected = (netconn_peer(sock->conn, &addr, &port) == ERR_OK); - - remote_addr.addr = ((struct sockaddr_in *)to)->sin_addr.s_addr; - remote_port = ((struct sockaddr_in *)to)->sin_port; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, size=%d, flags=0x%x to=", s, data, size, flags)); - ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", ntohs(remote_port))); - - netconn_connect(sock->conn, &remote_addr, ntohs(remote_port)); - - ret = lwip_send(s, data, size, flags); - - /* reset the remote address and port number - of the connection */ - if (connected) - netconn_connect(sock->conn, &addr, port); - else - netconn_disconnect(sock->conn); - return ret; -} - -int -lwip_socket(int domain, int type, int protocol) -{ - struct netconn *conn; - int i; - - /* create a netconn */ - switch (type) { - case SOCK_RAW: - conn = netconn_new_with_proto_and_callback(NETCONN_RAW, protocol, event_callback); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); - break; - case SOCK_DGRAM: - conn = netconn_new_with_callback(NETCONN_UDP, event_callback); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); - break; - case SOCK_STREAM: - conn = netconn_new_with_callback(NETCONN_TCP, event_callback); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); - break; - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", domain, type, protocol)); - set_errno(EINVAL); - return -1; - } - - if (!conn) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n")); - set_errno(ENOBUFS); - return -1; - } - - i = alloc_socket(conn); - - if (i == -1) { - netconn_delete(conn); - set_errno(ENOBUFS); - return -1; - } - conn->socket = i; - LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i)); - set_errno(0); - return i; -} - -int -lwip_write(int s, void *data, int size) -{ - return lwip_send(s, data, size, 0); -} - - -static int -lwip_selscan(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset) -{ - int i, nready = 0; - fd_set lreadset, lwriteset, lexceptset; - struct lwip_socket *p_sock; - - FD_ZERO(&lreadset); - FD_ZERO(&lwriteset); - FD_ZERO(&lexceptset); - - /* Go through each socket in each list to count number of sockets which - currently match */ - for(i = 0; i < maxfdp1; i++) - { - if (FD_ISSET(i, readset)) - { - /* See if netconn of this socket is ready for read */ - p_sock = get_socket(i); - if (p_sock && (p_sock->lastdata || p_sock->rcvevent)) - { - FD_SET(i, &lreadset); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i)); - nready++; - } - } - if (FD_ISSET(i, writeset)) - { - /* See if netconn of this socket is ready for write */ - p_sock = get_socket(i); - if (p_sock && p_sock->sendevent) - { - FD_SET(i, &lwriteset); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i)); - nready++; - } - } - } - *readset = lreadset; - *writeset = lwriteset; - FD_ZERO(exceptset); - - return nready; -} - - - -int -lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, - struct timeval *timeout) -{ - int i; - int nready; - fd_set lreadset, lwriteset, lexceptset; - u32_t msectimeout; - struct lwip_select_cb select_cb; - struct lwip_select_cb *p_selcb; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%ld tvusec=%ld)\n", maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset, timeout ? timeout->tv_sec : -1L, timeout ? timeout->tv_usec : -1L)); - - select_cb.next = 0; - select_cb.readset = readset; - select_cb.writeset = writeset; - select_cb.exceptset = exceptset; - select_cb.sem_signalled = 0; - - /* Protect ourselves searching through the list */ - if (!selectsem) - selectsem = sys_sem_new(1); - sys_sem_wait(selectsem); - - if (readset) - lreadset = *readset; - else - FD_ZERO(&lreadset); - if (writeset) - lwriteset = *writeset; - else - FD_ZERO(&lwriteset); - if (exceptset) - lexceptset = *exceptset; - else - FD_ZERO(&lexceptset); - - /* Go through each socket in each list to count number of sockets which - currently match */ - nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset); - - /* If we don't have any current events, then suspend if we are supposed to */ - if (!nready) - { - if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0) - { - sys_sem_signal(selectsem); - if (readset) - FD_ZERO(readset); - if (writeset) - FD_ZERO(writeset); - if (exceptset) - FD_ZERO(exceptset); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n")); - set_errno(0); - - return 0; - } - - /* add our semaphore to list */ - /* We don't actually need any dynamic memory. Our entry on the - * list is only valid while we are in this function, so it's ok - * to use local variables */ - - select_cb.sem = sys_sem_new(0); - /* Note that we are still protected */ - /* Put this select_cb on top of list */ - select_cb.next = select_cb_list; - select_cb_list = &select_cb; - - /* Now we can safely unprotect */ - sys_sem_signal(selectsem); - - /* Now just wait to be woken */ - if (timeout == 0) - /* Wait forever */ - msectimeout = 0; - else - msectimeout = ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000)); - - i = sys_sem_wait_timeout(select_cb.sem, msectimeout); - - /* Take us off the list */ - sys_sem_wait(selectsem); - if (select_cb_list == &select_cb) - select_cb_list = select_cb.next; - else - for (p_selcb = select_cb_list; p_selcb; p_selcb = p_selcb->next) - if (p_selcb->next == &select_cb) - { - p_selcb->next = select_cb.next; - break; - } - - sys_sem_signal(selectsem); - - sys_sem_free(select_cb.sem); - if (i == 0) /* Timeout */ - { - if (readset) - FD_ZERO(readset); - if (writeset) - FD_ZERO(writeset); - if (exceptset) - FD_ZERO(exceptset); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n")); - set_errno(0); - - return 0; - } - - if (readset) - lreadset = *readset; - else - FD_ZERO(&lreadset); - if (writeset) - lwriteset = *writeset; - else - FD_ZERO(&lwriteset); - if (exceptset) - lexceptset = *exceptset; - else - FD_ZERO(&lexceptset); - - /* See what's set */ - nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset); - } - else - sys_sem_signal(selectsem); - - if (readset) - *readset = lreadset; - if (writeset) - *writeset = lwriteset; - if (exceptset) - *exceptset = lexceptset; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready)); - set_errno(0); - - return nready; -} - - -static void -event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len) -{ - int s; - struct lwip_socket *sock; - struct lwip_select_cb *scb; - - /* Get socket */ - if (conn) - { - s = conn->socket; - if (s < 0) - { - /* Data comes in right away after an accept, even though - * the server task might not have created a new socket yet. - * Just count down (or up) if that's the case and we - * will use the data later. Note that only receive events - * can happen before the new socket is set up. */ - if (evt == NETCONN_EVT_RCVPLUS) - conn->socket--; - return; - } - - sock = get_socket(s); - if (!sock) - return; - } - else - return; - - if (!selectsem) - selectsem = sys_sem_new(1); - - sys_sem_wait(selectsem); - /* Set event as required */ - switch (evt) - { - case NETCONN_EVT_RCVPLUS: - sock->rcvevent++; - break; - case NETCONN_EVT_RCVMINUS: - sock->rcvevent--; - break; - case NETCONN_EVT_SENDPLUS: - sock->sendevent = 1; - break; - case NETCONN_EVT_SENDMINUS: - sock->sendevent = 0; - break; - } - sys_sem_signal(selectsem); - - /* Now decide if anyone is waiting for this socket */ - /* NOTE: This code is written this way to protect the select link list - but to avoid a deadlock situation by releasing socksem before - signalling for the select. This means we need to go through the list - multiple times ONLY IF a select was actually waiting. We go through - the list the number of waiting select calls + 1. This list is - expected to be small. */ - while (1) - { - sys_sem_wait(selectsem); - for (scb = select_cb_list; scb; scb = scb->next) - { - if (scb->sem_signalled == 0) - { - /* Test this select call for our socket */ - if (scb->readset && FD_ISSET(s, scb->readset)) - if (sock->rcvevent) - break; - if (scb->writeset && FD_ISSET(s, scb->writeset)) - if (sock->sendevent) - break; - } - } - if (scb) - { - scb->sem_signalled = 1; - sys_sem_signal(selectsem); - sys_sem_signal(scb->sem); - } else { - sys_sem_signal(selectsem); - break; - } - } - -} - - - - -int lwip_shutdown(int s, int how) -{ - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how)); - return lwip_close(s); /* XXX temporary hack until proper implementation */ -} - -int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen) -{ - struct lwip_socket *sock; - struct sockaddr_in sin; - struct ip_addr naddr; - - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - memset(&sin, 0, sizeof(sin)); - sin.sin_len = sizeof(sin); - sin.sin_family = AF_INET; - - /* get the IP address and port of the remote host */ - netconn_peer(sock->conn, &naddr, &sin.sin_port); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getpeername(%d, addr=", s)); - ip_addr_debug_print(SOCKETS_DEBUG, &naddr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port)); - - sin.sin_port = htons(sin.sin_port); - sin.sin_addr.s_addr = naddr.addr; - - if (*namelen > sizeof(sin)) - *namelen = sizeof(sin); - - memcpy(name, &sin, *namelen); - sock_set_errno(sock, 0); - return 0; -} - -int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen) -{ - struct lwip_socket *sock; - struct sockaddr_in sin; - struct ip_addr *naddr; - - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - memset(&sin, 0, sizeof(sin)); - sin.sin_len = sizeof(sin); - sin.sin_family = AF_INET; - - /* get the IP address and port of the remote host */ - netconn_addr(sock->conn, &naddr, &sin.sin_port); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockname(%d, addr=", s)); - ip_addr_debug_print(SOCKETS_DEBUG, naddr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port)); - - sin.sin_port = htons(sin.sin_port); - sin.sin_addr.s_addr = naddr->addr; - - if (*namelen > sizeof(sin)) - *namelen = sizeof(sin); - - memcpy(name, &sin, *namelen); - sock_set_errno(sock, 0); - return 0; -} - -int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen) -{ - int err = 0; - struct lwip_socket *sock = get_socket(s); - - if(!sock) { - set_errno(EBADF); - return -1; - } - - if( NULL == optval || NULL == optlen ) { - sock_set_errno( sock, EFAULT ); - return -1; - } - - /* Do length and type checks for the various options first, to keep it readable. */ - switch( level ) { - -/* Level: SOL_SOCKET */ - case SOL_SOCKET: - switch(optname) { - - case SO_ACCEPTCONN: - case SO_BROADCAST: - /* UNIMPL case SO_DEBUG: */ - /* UNIMPL case SO_DONTROUTE: */ - case SO_ERROR: - case SO_KEEPALIVE: - /* UNIMPL case SO_OOBINLINE: */ - /* UNIMPL case SO_RCVBUF: */ - /* UNIMPL case SO_SNDBUF: */ - /* UNIMPL case SO_RCVLOWAT: */ - /* UNIMPL case SO_SNDLOWAT: */ -#if SO_REUSE - case SO_REUSEADDR: - case SO_REUSEPORT: -#endif /* SO_REUSE */ - case SO_TYPE: - /* UNIMPL case SO_USELOOPBACK: */ - if( *optlen < sizeof(int) ) { - err = EINVAL; - } - break; - - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname)); - err = ENOPROTOOPT; - } /* switch */ - break; - -/* Level: IPPROTO_IP */ - case IPPROTO_IP: - switch(optname) { - /* UNIMPL case IP_HDRINCL: */ - /* UNIMPL case IP_RCVDSTADDR: */ - /* UNIMPL case IP_RCVIF: */ - case IP_TTL: - case IP_TOS: - if( *optlen < sizeof(int) ) { - err = EINVAL; - } - break; - - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname)); - err = ENOPROTOOPT; - } /* switch */ - break; - -/* Level: IPPROTO_TCP */ - case IPPROTO_TCP: - if( *optlen < sizeof(int) ) { - err = EINVAL; - break; - } - - /* If this is no TCP socket, ignore any options. */ - if ( sock->conn->type != NETCONN_TCP ) return 0; - - switch( optname ) { - case TCP_NODELAY: - case TCP_KEEPALIVE: - break; - - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname)); - err = ENOPROTOOPT; - } /* switch */ - break; - -/* UNDEFINED LEVEL */ - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname)); - err = ENOPROTOOPT; - } /* switch */ - - - if( 0 != err ) { - sock_set_errno(sock, err); - return -1; - } - - - - /* Now do the actual option processing */ - - switch(level) { - -/* Level: SOL_SOCKET */ - case SOL_SOCKET: - switch( optname ) { - - /* The option flags */ - case SO_ACCEPTCONN: - case SO_BROADCAST: - /* UNIMPL case SO_DEBUG: */ - /* UNIMPL case SO_DONTROUTE: */ - case SO_KEEPALIVE: - /* UNIMPL case SO_OOBINCLUDE: */ -#if SO_REUSE - case SO_REUSEADDR: - case SO_REUSEPORT: -#endif /* SO_REUSE */ - /*case SO_USELOOPBACK: UNIMPL */ - *(int*)optval = sock->conn->pcb.tcp->so_options & optname; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", s, optname, (*(int*)optval?"on":"off"))); - break; - - case SO_TYPE: - switch (sock->conn->type) { - case NETCONN_RAW: - *(int*)optval = SOCK_RAW; - break; - case NETCONN_TCP: - *(int*)optval = SOCK_STREAM; - break; - case NETCONN_UDP: - case NETCONN_UDPLITE: - case NETCONN_UDPNOCHKSUM: - *(int*)optval = SOCK_DGRAM; - break; - default: /* unrecognized socket type */ - *(int*)optval = sock->conn->type; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", s, *(int *)optval)); - } /* switch */ - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n", s, *(int *)optval)); - break; - - case SO_ERROR: - *(int *)optval = sock->err; - sock->err = 0; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n", s, *(int *)optval)); - break; - } /* switch */ - break; - -/* Level: IPPROTO_IP */ - case IPPROTO_IP: - switch( optname ) { - case IP_TTL: - *(int*)optval = sock->conn->pcb.tcp->ttl; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n", s, *(int *)optval)); - break; - case IP_TOS: - *(int*)optval = sock->conn->pcb.tcp->tos; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n", s, *(int *)optval)); - break; - } /* switch */ - break; - -/* Level: IPPROTO_TCP */ - case IPPROTO_TCP: - switch( optname ) { - case TCP_NODELAY: - *(int*)optval = (sock->conn->pcb.tcp->flags & TF_NODELAY); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", s, (*(int*)optval)?"on":"off") ); - break; - case TCP_KEEPALIVE: - *(int*)optval = (int)sock->conn->pcb.tcp->keepalive; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPALIVE) = %d\n", s, *(int *)optval)); - break; - } /* switch */ - break; - } - - - sock_set_errno(sock, err); - return err ? -1 : 0; -} - -int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen) -{ - struct lwip_socket *sock = get_socket(s); - int err = 0; - - if(!sock) { - set_errno(EBADF); - return -1; - } - - if( NULL == optval ) { - sock_set_errno( sock, EFAULT ); - return -1; - } - - - /* Do length and type checks for the various options first, to keep it readable. */ - switch( level ) { - -/* Level: SOL_SOCKET */ - case SOL_SOCKET: - switch(optname) { - - case SO_BROADCAST: - /* UNIMPL case SO_DEBUG: */ - /* UNIMPL case SO_DONTROUTE: */ - case SO_KEEPALIVE: - /* UNIMPL case SO_OOBINLINE: */ - /* UNIMPL case SO_RCVBUF: */ - /* UNIMPL case SO_SNDBUF: */ - /* UNIMPL case SO_RCVLOWAT: */ - /* UNIMPL case SO_SNDLOWAT: */ -#if SO_REUSE - case SO_REUSEADDR: - case SO_REUSEPORT: -#endif /* SO_REUSE */ - /* UNIMPL case SO_USELOOPBACK: */ - if( optlen < sizeof(int) ) { - err = EINVAL; - } - break; - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname)); - err = ENOPROTOOPT; - } /* switch */ - break; - -/* Level: IPPROTO_IP */ - case IPPROTO_IP: - switch(optname) { - /* UNIMPL case IP_HDRINCL: */ - /* UNIMPL case IP_RCVDSTADDR: */ - /* UNIMPL case IP_RCVIF: */ - case IP_TTL: - case IP_TOS: - if( optlen < sizeof(int) ) { - err = EINVAL; - } - break; - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname)); - err = ENOPROTOOPT; - } /* switch */ - break; - -/* Level: IPPROTO_TCP */ - case IPPROTO_TCP: - if( optlen < sizeof(int) ) { - err = EINVAL; - break; - } - - /* If this is no TCP socket, ignore any options. */ - if ( sock->conn->type != NETCONN_TCP ) return 0; - - switch( optname ) { - case TCP_NODELAY: - case TCP_KEEPALIVE: - break; - - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname)); - err = ENOPROTOOPT; - } /* switch */ - break; - -/* UNDEFINED LEVEL */ - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname)); - err = ENOPROTOOPT; - } /* switch */ - - - if( 0 != err ) { - sock_set_errno(sock, err); - return -1; - } - - - - /* Now do the actual option processing */ - - switch(level) { - -/* Level: SOL_SOCKET */ - case SOL_SOCKET: - switch(optname) { - - /* The option flags */ - case SO_BROADCAST: - /* UNIMPL case SO_DEBUG: */ - /* UNIMPL case SO_DONTROUTE: */ - case SO_KEEPALIVE: - /* UNIMPL case SO_OOBINCLUDE: */ -#if SO_REUSE - case SO_REUSEADDR: - case SO_REUSEPORT: -#endif /* SO_REUSE */ - /* UNIMPL case SO_USELOOPBACK: */ - if ( *(int*)optval ) { - sock->conn->pcb.tcp->so_options |= optname; - } else { - sock->conn->pcb.tcp->so_options &= ~optname; - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n", s, optname, (*(int*)optval?"on":"off"))); - break; - } /* switch */ - break; - -/* Level: IPPROTO_IP */ - case IPPROTO_IP: - switch( optname ) { - case IP_TTL: - sock->conn->pcb.tcp->ttl = (u8_t)(*(int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %u\n", s, sock->conn->pcb.tcp->ttl)); - break; - case IP_TOS: - sock->conn->pcb.tcp->tos = (u8_t)(*(int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %u\n", s, sock->conn->pcb.tcp->tos)); - break; - } /* switch */ - break; - -/* Level: IPPROTO_TCP */ - case IPPROTO_TCP: - switch( optname ) { - case TCP_NODELAY: - if ( *(int*)optval ) { - sock->conn->pcb.tcp->flags |= TF_NODELAY; - } else { - sock->conn->pcb.tcp->flags &= ~TF_NODELAY; - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n", s, (*(int *)optval)?"on":"off") ); - break; - case TCP_KEEPALIVE: - sock->conn->pcb.tcp->keepalive = (u32_t)(*(int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %lu\n", s, sock->conn->pcb.tcp->keepalive)); - break; - } /* switch */ - break; - } /* switch */ - - sock_set_errno(sock, err); - return err ? -1 : 0; -} - -int lwip_ioctl(int s, long cmd, void *argp) -{ - struct lwip_socket *sock = get_socket(s); - - if(!sock) { - set_errno(EBADF); - return -1; - } - - switch (cmd) { - case FIONREAD: - if (!argp) { - sock_set_errno(sock, EINVAL); - return -1; - } - - *((u16_t*)argp) = sock->conn->recv_avail; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %u\n", s, argp, *((u16_t*)argp))); - sock_set_errno(sock, 0); - return 0; - - case FIONBIO: - if (argp && *(u32_t*)argp) - sock->flags |= O_NONBLOCK; - else - sock->flags &= ~O_NONBLOCK; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, !!(sock->flags & O_NONBLOCK))); - sock_set_errno(sock, 0); - return 0; - - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp)); - sock_set_errno(sock, ENOSYS); /* not yet implemented */ - return -1; - } -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/api/tcpip.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/api/tcpip.c deleted file mode 100644 index ce8a2ca5d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/api/tcpip.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/sys.h" - -#include "lwip/memp.h" -#include "lwip/pbuf.h" - -#include "lwip/ip.h" -#include "lwip/ip_frag.h" -#include "lwip/udp.h" -#include "lwip/tcp.h" - -#include "lwip/tcpip.h" - -static void (* tcpip_init_done)(void *arg) = NULL; -static void *tcpip_init_done_arg; -static sys_mbox_t mbox; - -#if LWIP_TCP -static int tcpip_tcp_timer_active = 0; - -static void -tcpip_tcp_timer(void *arg) -{ - (void)arg; - - /* call TCP timer handler */ - tcp_tmr(); - /* timer still needed? */ - if (tcp_active_pcbs || tcp_tw_pcbs) { - /* restart timer */ - sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); - } else { - /* disable timer */ - tcpip_tcp_timer_active = 0; - } -} - -#if !NO_SYS -void -tcp_timer_needed(void) -{ - /* timer is off but needed again? */ - if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) { - /* enable and start timer */ - tcpip_tcp_timer_active = 1; - sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); - } -} -#endif /* !NO_SYS */ -#endif /* LWIP_TCP */ - -#if IP_REASSEMBLY -static void -ip_timer(void *data) -{ - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: ip_reass_tmr()\n")); - ip_reass_tmr(); - sys_timeout(1000, ip_timer, NULL); -} -#endif - -static void -tcpip_thread(void *arg) -{ - struct tcpip_msg *msg; - - (void)arg; - - ip_init(); -#if LWIP_UDP - udp_init(); -#endif -#if LWIP_TCP - tcp_init(); -#endif -#if IP_REASSEMBLY - sys_timeout(1000, ip_timer, NULL); -#endif - if (tcpip_init_done != NULL) { - tcpip_init_done(tcpip_init_done_arg); - } - - while (1) { /* MAIN Loop */ - sys_mbox_fetch(mbox, (void *)&msg); - switch (msg->type) { - case TCPIP_MSG_API: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg)); - api_msg_input(msg->msg.apimsg); - break; - case TCPIP_MSG_INPUT: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: IP packet %p\n", (void *)msg)); - ip_input(msg->msg.inp.p, msg->msg.inp.netif); - break; - case TCPIP_MSG_CALLBACK: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg)); - msg->msg.cb.f(msg->msg.cb.ctx); - break; - default: - break; - } - memp_free(MEMP_TCPIP_MSG, msg); - } -} - -err_t -tcpip_input(struct pbuf *p, struct netif *inp) -{ - struct tcpip_msg *msg; - - msg = memp_malloc(MEMP_TCPIP_MSG); - if (msg == NULL) { - pbuf_free(p); - return ERR_MEM; - } - - msg->type = TCPIP_MSG_INPUT; - msg->msg.inp.p = p; - msg->msg.inp.netif = inp; - sys_mbox_post(mbox, msg); - return ERR_OK; -} - -err_t -tcpip_callback(void (*f)(void *ctx), void *ctx) -{ - struct tcpip_msg *msg; - - msg = memp_malloc(MEMP_TCPIP_MSG); - if (msg == NULL) { - return ERR_MEM; - } - - msg->type = TCPIP_MSG_CALLBACK; - msg->msg.cb.f = f; - msg->msg.cb.ctx = ctx; - sys_mbox_post(mbox, msg); - return ERR_OK; -} - -void -tcpip_apimsg(struct api_msg *apimsg) -{ - struct tcpip_msg *msg; - msg = memp_malloc(MEMP_TCPIP_MSG); - if (msg == NULL) { - memp_free(MEMP_API_MSG, apimsg); - return; - } - msg->type = TCPIP_MSG_API; - msg->msg.apimsg = apimsg; - sys_mbox_post(mbox, msg); -} - -void -tcpip_init(void (* initfunc)(void *), void *arg) -{ - tcpip_init_done = initfunc; - tcpip_init_done_arg = arg; - mbox = sys_mbox_new(); - sys_thread_new(tcpip_thread, NULL, TCPIP_THREAD_PRIO); -} - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/dhcp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/dhcp.c deleted file mode 100644 index b688afa19..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/dhcp.c +++ /dev/null @@ -1,1455 +0,0 @@ -/** - * @file - * - * Dynamic Host Configuration Protocol client - */ - -/* - * - * Copyright (c) 2001-2004 Leon Woestenberg - * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is a contribution to the lwIP TCP/IP stack. - * The Swedish Institute of Computer Science and Adam Dunkels - * are specifically granted permission to redistribute this - * source code. - * - * Author: Leon Woestenberg - * - * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform - * with RFC 2131 and RFC 2132. - * - * TODO: - * - Proper parsing of DHCP messages exploiting file/sname field overloading. - * - Add JavaDoc style documentation (API, internals). - * - Support for interfaces other than Ethernet (SLIP, PPP, ...) - * - * Please coordinate changes and requests with Leon Woestenberg - * - * - * Integration with your code: - * - * In lwip/dhcp.h - * #define DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute) - * #define DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer) - * - * Then have your application call dhcp_coarse_tmr() and - * dhcp_fine_tmr() on the defined intervals. - * - * dhcp_start(struct netif *netif); - * starts a DHCP client instance which configures the interface by - * obtaining an IP address lease and maintaining it. - * - * Use dhcp_release(netif) to end the lease and use dhcp_stop(netif) - * to remove the DHCP client. - * - */ - -#include - -#include "lwip/stats.h" -#include "lwip/mem.h" -#include "lwip/udp.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/inet.h" -#include "netif/etharp.h" - -#include "lwip/sys.h" -#include "lwip/opt.h" -#include "lwip/dhcp.h" - -#if LWIP_DHCP /* don't build if not configured for use in lwipopt.h */ - -/** global transaction identifier, must be - * unique for each DHCP request. We simply increment, starting - * with this value (easy to match with a packet analyzer) */ -static u32_t xid = 0xABCD0000; - -/** DHCP client state machine functions */ -static void dhcp_handle_ack(struct netif *netif); -static void dhcp_handle_nak(struct netif *netif); -static void dhcp_handle_offer(struct netif *netif); - -static err_t dhcp_discover(struct netif *netif); -static err_t dhcp_select(struct netif *netif); -static void dhcp_check(struct netif *netif); -static void dhcp_bind(struct netif *netif); -static err_t dhcp_decline(struct netif *netif); -static err_t dhcp_rebind(struct netif *netif); -static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state); - -/** receive, unfold, parse and free incoming messages */ -static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port); -static err_t dhcp_unfold_reply(struct dhcp *dhcp); -static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type); -static u8_t dhcp_get_option_byte(u8_t *ptr); -static u16_t dhcp_get_option_short(u8_t *ptr); -static u32_t dhcp_get_option_long(u8_t *ptr); -static void dhcp_free_reply(struct dhcp *dhcp); - -/** set the DHCP timers */ -static void dhcp_timeout(struct netif *netif); -static void dhcp_t1_timeout(struct netif *netif); -static void dhcp_t2_timeout(struct netif *netif); - -/** build outgoing messages */ -/** create a DHCP request, fill in common headers */ -static err_t dhcp_create_request(struct netif *netif); -/** free a DHCP request */ -static void dhcp_delete_request(struct netif *netif); -/** add a DHCP option (type, then length in bytes) */ -static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len); -/** add option values */ -static void dhcp_option_byte(struct dhcp *dhcp, u8_t value); -static void dhcp_option_short(struct dhcp *dhcp, u16_t value); -static void dhcp_option_long(struct dhcp *dhcp, u32_t value); -/** always add the DHCP options trailer to end and pad */ -static void dhcp_option_trailer(struct dhcp *dhcp); - -/** - * Back-off the DHCP client (because of a received NAK response). - * - * Back-off the DHCP client because of a received NAK. Receiving a - * NAK means the client asked for something non-sensible, for - * example when it tries to renew a lease obtained on another network. - * - * We back-off and will end up restarting a fresh DHCP negotiation later. - * - * @param state pointer to DHCP state structure - */ -static void dhcp_handle_nak(struct netif *netif) { - struct dhcp *dhcp = netif->dhcp; - u16_t msecs = 10 * 1000; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n", - (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_handle_nak(): set request timeout %"U16_F" msecs\n", msecs)); - dhcp_set_state(dhcp, DHCP_BACKING_OFF); -} - -/** - * Checks if the offered IP address is already in use. - * - * It does so by sending an ARP request for the offered address and - * entering CHECKING state. If no ARP reply is received within a small - * interval, the address is assumed to be free for use by us. - */ -static void dhcp_check(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0], - (s16_t)netif->name[1])); - /* create an ARP query for the offered IP address, expecting that no host - responds, as the IP address should not be in use. */ - result = etharp_query(netif, &dhcp->offered_ip_addr, NULL); - if (result != ERR_OK) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_check: could not perform ARP query\n")); - } - dhcp->tries++; - msecs = 500; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs)); - dhcp_set_state(dhcp, DHCP_CHECKING); -} - -/** - * Remember the configuration offered by a DHCP server. - * - * @param state pointer to DHCP state structure - */ -static void dhcp_handle_offer(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - /* obtain the server address */ - u8_t *option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SERVER_ID); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n", - (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - if (option_ptr != NULL) - { - dhcp->server_ip_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2])); - LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n", dhcp->server_ip_addr.addr)); - /* remember offered address */ - ip_addr_set(&dhcp->offered_ip_addr, (struct ip_addr *)&dhcp->msg_in->yiaddr); - LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr)); - - dhcp_select(netif); - } -} - -/** - * Select a DHCP server offer out of all offers. - * - * Simply select the first offer received. - * - * @param netif the netif under DHCP control - * @return lwIP specific error (see error.h) - */ -static err_t dhcp_select(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result; - u32_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) - { - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_REQUEST); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, 576); - - /* MUST request the offered IP address */ - dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); - dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); - - dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); - dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); - - dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/); - dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK); - dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER); - dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST); - dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER); - - dhcp_option_trailer(dhcp); - /* shrink the pbuf to the actual content length */ - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - /* TODO: we really should bind to a specific local interface here - but we cannot specify an unconfigured netif as it is addressless */ - udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); - /* send broadcast to any DHCP server */ - udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); - udp_send(dhcp->pcb, dhcp->p_out); - /* reconnect to any (or to server here?!) */ - udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); - dhcp_delete_request(netif); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_select: REQUESTING\n")); - dhcp_set_state(dhcp, DHCP_REQUESTING); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_select: could not allocate DHCP request\n")); - } - dhcp->tries++; - msecs = dhcp->tries < 4 ? dhcp->tries * 1000 : 4 * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_select(): set request timeout %"U32_F" msecs\n", msecs)); - return result; -} - -/** - * The DHCP timer that checks for lease renewal/rebind timeouts. - * - */ -void dhcp_coarse_tmr() -{ - struct netif *netif = netif_list; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_coarse_tmr()\n")); - /* iterate through all network interfaces */ - while (netif != NULL) { - /* only act on DHCP configured interfaces */ - if (netif->dhcp != NULL) { - /* timer is active (non zero), and triggers (zeroes) now? */ - if (netif->dhcp->t2_timeout-- == 1) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n")); - /* this clients' rebind timeout triggered */ - dhcp_t2_timeout(netif); - /* timer is active (non zero), and triggers (zeroes) now */ - } else if (netif->dhcp->t1_timeout-- == 1) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n")); - /* this clients' renewal timeout triggered */ - dhcp_t1_timeout(netif); - } - } - /* proceed to next netif */ - netif = netif->next; - } -} - -/** - * DHCP transaction timeout handling - * - * A DHCP server is expected to respond within a short period of time. - * This timer checks whether an outstanding DHCP request is timed out. - * - */ -void dhcp_fine_tmr() -{ - struct netif *netif = netif_list; - /* loop through netif's */ - while (netif != NULL) { - /* only act on DHCP configured interfaces */ - if (netif->dhcp != NULL) { - /* timer is active (non zero), and is about to trigger now */ - if (netif->dhcp->request_timeout-- == 1) { - /* { netif->dhcp->request_timeout == 0 } */ - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_fine_tmr(): request timeout\n")); - /* this clients' request timeout triggered */ - dhcp_timeout(netif); - } - } - /* proceed to next network interface */ - netif = netif->next; - } -} - -/** - * A DHCP negotiation transaction, or ARP request, has timed out. - * - * The timer that was started with the DHCP or ARP request has - * timed out, indicating no response was received in time. - * - * @param netif the netif under DHCP control - * - */ -static void dhcp_timeout(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_timeout()\n")); - /* back-off period has passed, or server selection timed out */ - if ((dhcp->state == DHCP_BACKING_OFF) || (dhcp->state == DHCP_SELECTING)) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_timeout(): restarting discovery\n")); - dhcp_discover(netif); - /* receiving the requested lease timed out */ - } else if (dhcp->state == DHCP_REQUESTING) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n")); - if (dhcp->tries <= 5) { - dhcp_select(netif); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n")); - dhcp_release(netif); - dhcp_discover(netif); - } - /* received no ARP reply for the offered address (which is good) */ - } else if (dhcp->state == DHCP_CHECKING) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n")); - if (dhcp->tries <= 1) { - dhcp_check(netif); - /* no ARP replies on the offered address, - looks like the IP address is indeed free */ - } else { - /* bind the interface to the offered address */ - dhcp_bind(netif); - } - } - /* did not get response to renew request? */ - else if (dhcp->state == DHCP_RENEWING) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RENEWING, DHCP request timed out\n")); - /* just retry renewal */ - /* note that the rebind timer will eventually time-out if renew does not work */ - dhcp_renew(netif); - /* did not get response to rebind request? */ - } else if (dhcp->state == DHCP_REBINDING) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REBINDING, DHCP request timed out\n")); - if (dhcp->tries <= 8) { - dhcp_rebind(netif); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RELEASING, DISCOVERING\n")); - dhcp_release(netif); - dhcp_discover(netif); - } - } -} - -/** - * The renewal period has timed out. - * - * @param netif the netif under DHCP control - */ -static void dhcp_t1_timeout(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_t1_timeout()\n")); - if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) { - /* just retry to renew - note that the rebind timer (t2) will - * eventually time-out if renew tries fail. */ - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t1_timeout(): must renew\n")); - dhcp_renew(netif); - } -} - -/** - * The rebind period has timed out. - * - */ -static void dhcp_t2_timeout(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout()\n")); - if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) { - /* just retry to rebind */ - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout(): must rebind\n")); - dhcp_rebind(netif); - } -} - -/** - * - * @param netif the netif under DHCP control - */ -static void dhcp_handle_ack(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - u8_t *option_ptr; - /* clear options we might not get from the ACK */ - dhcp->offered_sn_mask.addr = 0; - dhcp->offered_gw_addr.addr = 0; - dhcp->offered_bc_addr.addr = 0; - - /* lease time given? */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_LEASE_TIME); - if (option_ptr != NULL) { - /* remember offered lease time */ - dhcp->offered_t0_lease = dhcp_get_option_long(option_ptr + 2); - } - /* renewal period given? */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T1); - if (option_ptr != NULL) { - /* remember given renewal period */ - dhcp->offered_t1_renew = dhcp_get_option_long(option_ptr + 2); - } else { - /* calculate safe periods for renewal */ - dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2; - } - - /* renewal period given? */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T2); - if (option_ptr != NULL) { - /* remember given rebind period */ - dhcp->offered_t2_rebind = dhcp_get_option_long(option_ptr + 2); - } else { - /* calculate safe periods for rebinding */ - dhcp->offered_t2_rebind = dhcp->offered_t0_lease; - } - - /* (y)our internet address */ - ip_addr_set(&dhcp->offered_ip_addr, &dhcp->msg_in->yiaddr); - -/** - * Patch #1308 - * TODO: we must check if the file field is not overloaded by DHCP options! - */ -#if 0 - /* boot server address */ - ip_addr_set(&dhcp->offered_si_addr, &dhcp->msg_in->siaddr); - /* boot file name */ - if (dhcp->msg_in->file[0]) { - dhcp->boot_file_name = mem_malloc(strlen(dhcp->msg_in->file) + 1); - strcpy(dhcp->boot_file_name, dhcp->msg_in->file); - } -#endif - - /* subnet mask */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SUBNET_MASK); - /* subnet mask given? */ - if (option_ptr != NULL) { - dhcp->offered_sn_mask.addr = htonl(dhcp_get_option_long(&option_ptr[2])); - } - - /* gateway router */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_ROUTER); - if (option_ptr != NULL) { - dhcp->offered_gw_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2])); - } - - /* broadcast address */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_BROADCAST); - if (option_ptr != NULL) { - dhcp->offered_bc_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2])); - } - - /* DNS servers */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_DNS_SERVER); - if (option_ptr != NULL) { - u8_t n; - dhcp->dns_count = dhcp_get_option_byte(&option_ptr[1]); - /* limit to at most DHCP_MAX_DNS DNS servers */ - if (dhcp->dns_count > DHCP_MAX_DNS) dhcp->dns_count = DHCP_MAX_DNS; - for (n = 0; n < dhcp->dns_count; n++) - { - dhcp->offered_dns_addr[n].addr = htonl(dhcp_get_option_long(&option_ptr[2+(n<<2)])); - } - } -} - -/** - * Start DHCP negotiation for a network interface. - * - * If no DHCP client instance was attached to this interface, - * a new client is created first. If a DHCP client instance - * was already present, it restarts negotiation. - * - * @param netif The lwIP network interface - * @return lwIP error code - * - ERR_OK - No error - * - ERR_MEM - Out of memory - * - */ -err_t dhcp_start(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result = ERR_OK; - - LWIP_ASSERT("netif != NULL", netif != NULL); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - netif->flags &= ~NETIF_FLAG_DHCP; - - /* no DHCP client attached yet? */ - if (dhcp == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting new DHCP client\n")); - dhcp = mem_malloc(sizeof(struct dhcp)); - if (dhcp == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n")); - return ERR_MEM; - } - /* store this dhcp client in the netif */ - netif->dhcp = dhcp; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): allocated dhcp")); - /* already has DHCP client attached */ - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 3, ("dhcp_start(): restarting DHCP configuration\n")); - } - - /* clear data structure */ - memset(dhcp, 0, sizeof(struct dhcp)); - /* allocate UDP PCB */ - dhcp->pcb = udp_new(); - if (dhcp->pcb == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not obtain pcb\n")); - mem_free((void *)dhcp); - netif->dhcp = dhcp = NULL; - return ERR_MEM; - } - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n")); - /* (re)start the DHCP negotiation */ - result = dhcp_discover(netif); - if (result != ERR_OK) { - /* free resources allocated above */ - dhcp_stop(netif); - return ERR_MEM; - } - netif->flags |= NETIF_FLAG_DHCP; - return result; -} - -/** - * Inform a DHCP server of our manual configuration. - * - * This informs DHCP servers of our fixed IP address configuration - * by sending an INFORM message. It does not involve DHCP address - * configuration, it is just here to be nice to the network. - * - * @param netif The lwIP network interface - * - */ -void dhcp_inform(struct netif *netif) -{ - struct dhcp *dhcp; - err_t result = ERR_OK; - dhcp = mem_malloc(sizeof(struct dhcp)); - if (dhcp == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not allocate dhcp\n")); - return; - } - netif->dhcp = dhcp; - memset(dhcp, 0, sizeof(struct dhcp)); - - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): allocated dhcp\n")); - dhcp->pcb = udp_new(); - if (dhcp->pcb == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not obtain pcb")); - mem_free((void *)dhcp); - return; - } - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): created new udp pcb\n")); - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) { - - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_INFORM); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - /* TODO: use netif->mtu ?! */ - dhcp_option_short(dhcp, 576); - - dhcp_option_trailer(dhcp); - - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); - udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_inform: INFORMING\n")); - udp_send(dhcp->pcb, dhcp->p_out); - udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); - dhcp_delete_request(netif); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform: could not allocate DHCP request\n")); - } - - if (dhcp != NULL) - { - if (dhcp->pcb != NULL) udp_remove(dhcp->pcb); - dhcp->pcb = NULL; - mem_free((void *)dhcp); - netif->dhcp = NULL; - } -} - -#if DHCP_DOES_ARP_CHECK -/** - * Match an ARP reply with the offered IP address. - * - * @param addr The IP address we received a reply from - * - */ -void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr) -{ - LWIP_ASSERT("netif != NULL", netif != NULL); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_arp_reply()\n")); - /* is a DHCP client doing an ARP check? */ - if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_CHECKING)) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n", addr->addr)); - /* did a host respond with the address we - were offered by the DHCP server? */ - if (ip_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) { - /* we will not accept the offered address */ - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 1, ("dhcp_arp_reply(): arp reply matched with offered address, declining\n")); - dhcp_decline(netif); - } - } -} - -/** - * Decline an offered lease. - * - * Tell the DHCP server we do not accept the offered address. - * One reason to decline the lease is when we find out the address - * is already in use by another host (through ARP). - */ -static err_t dhcp_decline(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result = ERR_OK; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_decline()\n")); - dhcp_set_state(dhcp, DHCP_BACKING_OFF); - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) - { - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_DECLINE); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, 576); - - dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); - dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); - - dhcp_option_trailer(dhcp); - /* resize pbuf to reflect true size of options */ - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); - /* @todo: should we really connect here? we are performing sendto() */ - udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); - /* per section 4.4.4, broadcast DECLINE messages */ - udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); - dhcp_delete_request(netif); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_decline: BACKING OFF\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_decline: could not allocate DHCP request\n")); - } - dhcp->tries++; - msecs = 10*1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} -#endif - - -/** - * Start the DHCP process, discover a DHCP server. - * - */ -static err_t dhcp_discover(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result = ERR_OK; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_discover()\n")); - ip_addr_set(&dhcp->offered_ip_addr, IP_ADDR_ANY); - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) - { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: making request\n")); - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_DISCOVER); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, 576); - - dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/); - dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK); - dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER); - dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST); - dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER); - - dhcp_option_trailer(dhcp); - - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: realloc()ing\n")); - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - /* set receive callback function with netif as user data */ - udp_recv(dhcp->pcb, dhcp_recv, netif); - udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); - udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n")); - udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: deleting()ing\n")); - dhcp_delete_request(netif); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover: SELECTING\n")); - dhcp_set_state(dhcp, DHCP_SELECTING); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_discover: could not allocate DHCP request\n")); - } - dhcp->tries++; - msecs = dhcp->tries < 4 ? (dhcp->tries + 1) * 1000 : 10 * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} - - -/** - * Bind the interface to the offered IP address. - * - * @param netif network interface to bind to the offered address - */ -static void dhcp_bind(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - struct ip_addr sn_mask, gw_addr; - LWIP_ASSERT("dhcp_bind: netif != NULL", netif != NULL); - LWIP_ASSERT("dhcp_bind: dhcp != NULL", dhcp != NULL); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - - /* temporary DHCP lease? */ - if (dhcp->offered_t1_renew != 0xffffffffUL) { - /* set renewal period timer */ - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew)); - dhcp->t1_timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; - if (dhcp->t1_timeout == 0) dhcp->t1_timeout = 1; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew*1000)); - } - /* set renewal period timer */ - if (dhcp->offered_t2_rebind != 0xffffffffUL) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind)); - dhcp->t2_timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; - if (dhcp->t2_timeout == 0) dhcp->t2_timeout = 1; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind*1000)); - } - /* copy offered network mask */ - ip_addr_set(&sn_mask, &dhcp->offered_sn_mask); - - /* subnet mask not given? */ - /* TODO: this is not a valid check. what if the network mask is 0? */ - if (sn_mask.addr == 0) { - /* choose a safe subnet mask given the network class */ - u8_t first_octet = ip4_addr1(&sn_mask); - if (first_octet <= 127) sn_mask.addr = htonl(0xff000000); - else if (first_octet >= 192) sn_mask.addr = htonl(0xffffff00); - else sn_mask.addr = htonl(0xffff0000); - } - - ip_addr_set(&gw_addr, &dhcp->offered_gw_addr); - /* gateway address not given? */ - if (gw_addr.addr == 0) { - /* copy network address */ - gw_addr.addr = (dhcp->offered_ip_addr.addr & sn_mask.addr); - /* use first host address on network as gateway */ - gw_addr.addr |= htonl(0x00000001); - } - - LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr)); - netif_set_ipaddr(netif, &dhcp->offered_ip_addr); - LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): SN: 0x%08"X32_F"\n", sn_mask.addr)); - netif_set_netmask(netif, &sn_mask); - LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): GW: 0x%08"X32_F"\n", gw_addr.addr)); - netif_set_gw(netif, &gw_addr); - /* bring the interface up */ - netif_set_up(netif); - /* netif is now bound to DHCP leased address */ - dhcp_set_state(dhcp, DHCP_BOUND); -} - -/** - * Renew an existing DHCP lease at the involved DHCP server. - * - * @param netif network interface which must renew its lease - */ -err_t dhcp_renew(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_renew()\n")); - dhcp_set_state(dhcp, DHCP_RENEWING); - - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) { - - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_REQUEST); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - /* TODO: use netif->mtu in some way */ - dhcp_option_short(dhcp, 576); - -#if 0 - dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); - dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); -#endif - -#if 0 - dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); - dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); -#endif - /* append DHCP message trailer */ - dhcp_option_trailer(dhcp); - - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); - udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT); - udp_send(dhcp->pcb, dhcp->p_out); - dhcp_delete_request(netif); - - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew: RENEWING\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_renew: could not allocate DHCP request\n")); - } - dhcp->tries++; - /* back-off on retries, but to a maximum of 20 seconds */ - msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} - -/** - * Rebind with a DHCP server for an existing DHCP lease. - * - * @param netif network interface which must rebind with a DHCP server - */ -static err_t dhcp_rebind(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind()\n")); - dhcp_set_state(dhcp, DHCP_REBINDING); - - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) - { - - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_REQUEST); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, 576); - -#if 0 - dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); - dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); - - dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); - dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); -#endif - - dhcp_option_trailer(dhcp); - - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - /* set remote IP association to any DHCP server */ - udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); - udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); - /* broadcast to server */ - udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); - dhcp_delete_request(netif); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind: REBINDING\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_rebind: could not allocate DHCP request\n")); - } - dhcp->tries++; - msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} - -/** - * Release a DHCP lease. - * - * @param netif network interface which must release its lease - */ -err_t dhcp_release(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_release()\n")); - - /* idle DHCP client */ - dhcp_set_state(dhcp, DHCP_OFF); - /* clean old DHCP offer */ - dhcp->server_ip_addr.addr = 0; - dhcp->offered_ip_addr.addr = dhcp->offered_sn_mask.addr = 0; - dhcp->offered_gw_addr.addr = dhcp->offered_bc_addr.addr = 0; - dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0; - dhcp->dns_count = 0; - - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) { - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_RELEASE); - - dhcp_option_trailer(dhcp); - - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); - udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT); - udp_send(dhcp->pcb, dhcp->p_out); - dhcp_delete_request(netif); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release: RELEASED, DHCP_OFF\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_release: could not allocate DHCP request\n")); - } - dhcp->tries++; - msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release(): set request timeout %"U16_F" msecs\n", msecs)); - /* bring the interface down */ - netif_set_down(netif); - /* remove IP address from interface */ - netif_set_ipaddr(netif, IP_ADDR_ANY); - netif_set_gw(netif, IP_ADDR_ANY); - netif_set_netmask(netif, IP_ADDR_ANY); - - /* TODO: netif_down(netif); */ - return result; -} -/** - * Remove the DHCP client from the interface. - * - * @param netif The network interface to stop DHCP on - */ -void dhcp_stop(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - LWIP_ASSERT("dhcp_stop: netif != NULL", netif != NULL); - - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_stop()\n")); - /* netif is DHCP configured? */ - if (dhcp != NULL) - { - if (dhcp->pcb != NULL) - { - udp_remove(dhcp->pcb); - dhcp->pcb = NULL; - } - if (dhcp->p != NULL) - { - pbuf_free(dhcp->p); - dhcp->p = NULL; - } - /* free unfolded reply */ - dhcp_free_reply(dhcp); - mem_free((void *)dhcp); - netif->dhcp = NULL; - } -} - -/* - * Set the DHCP state of a DHCP client. - * - * If the state changed, reset the number of tries. - * - * TODO: we might also want to reset the timeout here? - */ -static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state) -{ - if (new_state != dhcp->state) - { - dhcp->state = new_state; - dhcp->tries = 0; - } -} - -/* - * Concatenate an option type and length field to the outgoing - * DHCP message. - * - */ -static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len) -{ - LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = option_type; - dhcp->msg_out->options[dhcp->options_out_len++] = option_len; -} -/* - * Concatenate a single byte to the outgoing DHCP message. - * - */ -static void dhcp_option_byte(struct dhcp *dhcp, u8_t value) -{ - LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = value; -} -static void dhcp_option_short(struct dhcp *dhcp, u16_t value) -{ - LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff00U) >> 8; - dhcp->msg_out->options[dhcp->options_out_len++] = value & 0x00ffU; -} -static void dhcp_option_long(struct dhcp *dhcp, u32_t value) -{ - LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff000000UL) >> 24; - dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x00ff0000UL) >> 16; - dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x0000ff00UL) >> 8; - dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x000000ffUL); -} - -/** - * Extract the DHCP message and the DHCP options. - * - * Extract the DHCP message and the DHCP options, each into a contiguous - * piece of memory. As a DHCP message is variable sized by its options, - * and also allows overriding some fields for options, the easy approach - * is to first unfold the options into a conitguous piece of memory, and - * use that further on. - * - */ -static err_t dhcp_unfold_reply(struct dhcp *dhcp) -{ - struct pbuf *p = dhcp->p; - u8_t *ptr; - u16_t i; - u16_t j = 0; - LWIP_ASSERT("dhcp->p != NULL", dhcp->p != NULL); - /* free any left-overs from previous unfolds */ - dhcp_free_reply(dhcp); - /* options present? */ - if (dhcp->p->tot_len > (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN)) - { - dhcp->options_in_len = dhcp->p->tot_len - (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN); - dhcp->options_in = mem_malloc(dhcp->options_in_len); - if (dhcp->options_in == NULL) - { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->options\n")); - return ERR_MEM; - } - } - dhcp->msg_in = mem_malloc(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN); - if (dhcp->msg_in == NULL) - { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->msg_in\n")); - mem_free((void *)dhcp->options_in); - dhcp->options_in = NULL; - return ERR_MEM; - } - - ptr = (u8_t *)dhcp->msg_in; - /* proceed through struct dhcp_msg */ - for (i = 0; i < sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN; i++) - { - *ptr++ = ((u8_t *)p->payload)[j++]; - /* reached end of pbuf? */ - if (j == p->len) - { - /* proceed to next pbuf in chain */ - p = p->next; - j = 0; - } - } - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes into dhcp->msg_in[]\n", i)); - if (dhcp->options_in != NULL) { - ptr = (u8_t *)dhcp->options_in; - /* proceed through options */ - for (i = 0; i < dhcp->options_in_len; i++) { - *ptr++ = ((u8_t *)p->payload)[j++]; - /* reached end of pbuf? */ - if (j == p->len) { - /* proceed to next pbuf in chain */ - p = p->next; - j = 0; - } - } - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes to dhcp->options_in[]\n", i)); - } - return ERR_OK; -} - -/** - * Free the incoming DHCP message including contiguous copy of - * its DHCP options. - * - */ -static void dhcp_free_reply(struct dhcp *dhcp) -{ - if (dhcp->msg_in != NULL) { - mem_free((void *)dhcp->msg_in); - dhcp->msg_in = NULL; - } - if (dhcp->options_in) { - mem_free((void *)dhcp->options_in); - dhcp->options_in = NULL; - dhcp->options_in_len = 0; - } - LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_free_reply(): free'd\n")); -} - - -/** - * If an incoming DHCP message is in response to us, then trigger the state machine - */ -static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port) -{ - struct netif *netif = (struct netif *)arg; - struct dhcp *dhcp = netif->dhcp; - struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload; - u8_t *options_ptr; - u8_t msg_type; - u8_t i; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_recv(pbuf = %p) from DHCP server %"U16_F".%"U16_F".%"U16_F".%"U16_F" port %"U16_F"\n", (void*)p, - (u16_t)(ntohl(addr->addr) >> 24 & 0xff), (u16_t)(ntohl(addr->addr) >> 16 & 0xff), - (u16_t)(ntohl(addr->addr) >> 8 & 0xff), (u16_t)(ntohl(addr->addr) & 0xff), port)); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len)); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len)); - /* prevent warnings about unused arguments */ - (void)pcb; (void)addr; (void)port; - dhcp->p = p; - /* TODO: check packet length before reading them */ - if (reply_msg->op != DHCP_BOOTREPLY) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op)); - pbuf_free(p); - dhcp->p = NULL; - return; - } - /* iterate through hardware address and match against DHCP message */ - for (i = 0; i < netif->hwaddr_len; i++) { - if (netif->hwaddr[i] != reply_msg->chaddr[i]) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("netif->hwaddr[%"U16_F"]==%02"X16_F" != reply_msg->chaddr[%"U16_F"]==%02"X16_F"\n", - (u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i])); - pbuf_free(p); - dhcp->p = NULL; - return; - } - } - /* match transaction ID against what we expected */ - if (ntohl(reply_msg->xid) != dhcp->xid) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("transaction id mismatch\n")); - pbuf_free(p); - dhcp->p = NULL; - return; - } - /* option fields could be unfold? */ - if (dhcp_unfold_reply(dhcp) != ERR_OK) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("problem unfolding DHCP message - too short on memory?\n")); - pbuf_free(p); - dhcp->p = NULL; - return; - } - - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n")); - /* obtain pointer to DHCP message type */ - options_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_MESSAGE_TYPE); - if (options_ptr == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OPTION_MESSAGE_TYPE option not found\n")); - pbuf_free(p); - dhcp->p = NULL; - return; - } - - /* read DHCP message type */ - msg_type = dhcp_get_option_byte(options_ptr + 2); - /* message type is DHCP ACK? */ - if (msg_type == DHCP_ACK) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_ACK received\n")); - /* in requesting state? */ - if (dhcp->state == DHCP_REQUESTING) { - dhcp_handle_ack(netif); - dhcp->request_timeout = 0; -#if DHCP_DOES_ARP_CHECK - /* check if the acknowledged lease address is already in use */ - dhcp_check(netif); -#else - /* bind interface to the acknowledged lease address */ - dhcp_bind(netif); -#endif - } - /* already bound to the given lease address? */ - else if ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING)) { - dhcp->request_timeout = 0; - dhcp_bind(netif); - } - } - /* received a DHCP_NAK in appropriate state? */ - else if ((msg_type == DHCP_NAK) && - ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REQUESTING) || - (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING ))) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_NAK received\n")); - dhcp->request_timeout = 0; - dhcp_handle_nak(netif); - } - /* received a DHCP_OFFER in DHCP_SELECTING state? */ - else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_SELECTING)) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OFFER received in DHCP_SELECTING state\n")); - dhcp->request_timeout = 0; - /* remember offered lease */ - dhcp_handle_offer(netif); - } - pbuf_free(p); - dhcp->p = NULL; -} - - -static err_t dhcp_create_request(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - u16_t i; - LWIP_ASSERT("dhcp_create_request: dhcp->p_out == NULL", dhcp->p_out == NULL); - LWIP_ASSERT("dhcp_create_request: dhcp->msg_out == NULL", dhcp->msg_out == NULL); - dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM); - if (dhcp->p_out == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_create_request(): could not allocate pbuf\n")); - return ERR_MEM; - } - /* give unique transaction identifier to this request */ - dhcp->xid = xid++; - - dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload; - - dhcp->msg_out->op = DHCP_BOOTREQUEST; - /* TODO: make link layer independent */ - dhcp->msg_out->htype = DHCP_HTYPE_ETH; - /* TODO: make link layer independent */ - dhcp->msg_out->hlen = DHCP_HLEN_ETH; - dhcp->msg_out->hops = 0; - dhcp->msg_out->xid = htonl(dhcp->xid); - dhcp->msg_out->secs = 0; - dhcp->msg_out->flags = 0; - dhcp->msg_out->ciaddr.addr = netif->ip_addr.addr; - dhcp->msg_out->yiaddr.addr = 0; - dhcp->msg_out->siaddr.addr = 0; - dhcp->msg_out->giaddr.addr = 0; - for (i = 0; i < DHCP_CHADDR_LEN; i++) { - /* copy netif hardware address, pad with zeroes */ - dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len) ? netif->hwaddr[i] : 0/* pad byte*/; - } - for (i = 0; i < DHCP_SNAME_LEN; i++) dhcp->msg_out->sname[i] = 0; - for (i = 0; i < DHCP_FILE_LEN; i++) dhcp->msg_out->file[i] = 0; - dhcp->msg_out->cookie = htonl(0x63825363UL); - dhcp->options_out_len = 0; - /* fill options field with an incrementing array (for debugging purposes) */ - for (i = 0; i < DHCP_OPTIONS_LEN; i++) dhcp->msg_out->options[i] = i; - return ERR_OK; -} - -static void dhcp_delete_request(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - LWIP_ASSERT("dhcp_free_msg: dhcp->p_out != NULL", dhcp->p_out != NULL); - LWIP_ASSERT("dhcp_free_msg: dhcp->msg_out != NULL", dhcp->msg_out != NULL); - pbuf_free(dhcp->p_out); - dhcp->p_out = NULL; - dhcp->msg_out = NULL; -} - -/** - * Add a DHCP message trailer - * - * Adds the END option to the DHCP message, and if - * necessary, up to three padding bytes. - */ - -static void dhcp_option_trailer(struct dhcp *dhcp) -{ - LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL); - LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END; - /* packet is too small, or not 4 byte aligned? */ - while ((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) { - /* LWIP_DEBUGF(DHCP_DEBUG,("dhcp_option_trailer:dhcp->options_out_len=%"U16_F", DHCP_OPTIONS_LEN=%"U16_F, dhcp->options_out_len, DHCP_OPTIONS_LEN)); */ - LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN); - /* add a fill/padding byte */ - dhcp->msg_out->options[dhcp->options_out_len++] = 0; - } -} - -/** - * Find the offset of a DHCP option inside the DHCP message. - * - * @param client DHCP client - * @param option_type - * - * @return a byte offset into the UDP message where the option was found, or - * zero if the given option was not found. - */ -static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type) -{ - u8_t overload = DHCP_OVERLOAD_NONE; - - /* options available? */ - if ((dhcp->options_in != NULL) && (dhcp->options_in_len > 0)) { - /* start with options field */ - u8_t *options = (u8_t *)dhcp->options_in; - u16_t offset = 0; - /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */ - while ((offset < dhcp->options_in_len) && (options[offset] != DHCP_OPTION_END)) { - /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */ - /* are the sname and/or file field overloaded with options? */ - if (options[offset] == DHCP_OPTION_OVERLOAD) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("overloaded message detected\n")); - /* skip option type and length */ - offset += 2; - overload = options[offset++]; - } - /* requested option found */ - else if (options[offset] == option_type) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset %"U16_F" in options\n", offset)); - return &options[offset]; - /* skip option */ - } else { - LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", options[offset])); - /* skip option type */ - offset++; - /* skip option length, and then length bytes */ - offset += 1 + options[offset]; - } - } - /* is this an overloaded message? */ - if (overload != DHCP_OVERLOAD_NONE) { - u16_t field_len; - if (overload == DHCP_OVERLOAD_FILE) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded file field\n")); - options = (u8_t *)&dhcp->msg_in->file; - field_len = DHCP_FILE_LEN; - } else if (overload == DHCP_OVERLOAD_SNAME) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname field\n")); - options = (u8_t *)&dhcp->msg_in->sname; - field_len = DHCP_SNAME_LEN; - /* TODO: check if else if () is necessary */ - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname and file field\n")); - options = (u8_t *)&dhcp->msg_in->sname; - field_len = DHCP_FILE_LEN + DHCP_SNAME_LEN; - } - offset = 0; - - /* at least 1 byte to read and no end marker */ - while ((offset < field_len) && (options[offset] != DHCP_OPTION_END)) { - if (options[offset] == option_type) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset=%"U16_F"\n", offset)); - return &options[offset]; - /* skip option */ - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("skipping option %"U16_F"\n", options[offset])); - /* skip option type */ - offset++; - offset += 1 + options[offset]; - } - } - } - } - return 0; -} - -/** - * Return the byte of DHCP option data. - * - * @param client DHCP client. - * @param ptr pointer obtained by dhcp_get_option_ptr(). - * - * @return byte value at the given address. - */ -static u8_t dhcp_get_option_byte(u8_t *ptr) -{ - LWIP_DEBUGF(DHCP_DEBUG, ("option byte value=%"U16_F"\n", (u16_t)(*ptr))); - return *ptr; -} - -/** - * Return the 16-bit value of DHCP option data. - * - * @param client DHCP client. - * @param ptr pointer obtained by dhcp_get_option_ptr(). - * - * @return byte value at the given address. - */ -static u16_t dhcp_get_option_short(u8_t *ptr) -{ - u16_t value; - value = *ptr++ << 8; - value |= *ptr; - LWIP_DEBUGF(DHCP_DEBUG, ("option short value=%"U16_F"\n", value)); - return value; -} - -/** - * Return the 32-bit value of DHCP option data. - * - * @param client DHCP client. - * @param ptr pointer obtained by dhcp_get_option_ptr(). - * - * @return byte value at the given address. - */ -static u32_t dhcp_get_option_long(u8_t *ptr) -{ - u32_t value; - value = (u32_t)(*ptr++) << 24; - value |= (u32_t)(*ptr++) << 16; - value |= (u32_t)(*ptr++) << 8; - value |= (u32_t)(*ptr++); - LWIP_DEBUGF(DHCP_DEBUG, ("option long value=%"U32_F"\n", value)); - return value; -} - -#endif /* LWIP_DHCP */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/inet.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/inet.c deleted file mode 100644 index 556cbeb5f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/inet.c +++ /dev/null @@ -1,525 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - - -/* inet.c - * - * Functions common to all TCP/IP modules, such as the Internet checksum and the - * byte order functions. - * - */ - - -#include "lwip/opt.h" - -#include "lwip/arch.h" - -#include "lwip/def.h" -#include "lwip/inet.h" - -#include "lwip/sys.h" - -/* This is a reference implementation of the checksum algorithm, with the - * aim of being simple, correct and fully portable. Checksumming is the - * first thing you would want to optimize for your platform. You will - * need to port it to your architecture and in your sys_arch.h: - * - * #define LWIP_CHKSUM -*/ -#ifndef LWIP_CHKSUM -#define LWIP_CHKSUM lwip_standard_chksum - -/** - * lwip checksum - * - * @param dataptr points to start of data to be summed at any boundary - * @param len length of data to be summed - * @return host order (!) lwip checksum (non-inverted Internet sum) - * - * @note accumulator size limits summable lenght to 64k - * @note host endianess is irrelevant (p3 RFC1071) - */ -static u16_t -lwip_standard_chksum(void *dataptr, u16_t len) -{ - u32_t acc; - u16_t src; - u8_t *octetptr; - - acc = 0; - /* dataptr may be at odd or even addresses */ - octetptr = (u8_t*)dataptr; - while (len > 1) - { - /* declare first octet as most significant - thus assume network order, ignoring host order */ - src = (*octetptr) << 8; - octetptr++; - /* declare second octet as least significant */ - src |= (*octetptr); - octetptr++; - acc += src; - len -= 2; - } - if (len > 0) - { - /* accumulate remaining octet */ - src = (*octetptr) << 8; - acc += src; - } - /* add deferred carry bits */ - acc = (acc >> 16) + (acc & 0x0000ffffUL); - if ((acc & 0xffff0000) != 0) { - acc = (acc >> 16) + (acc & 0x0000ffffUL); - } - /* This maybe a little confusing: reorder sum using htons() - instead of ntohs() since it has a little less call overhead. - The caller must invert bits for Internet sum ! */ - return htons((u16_t)acc); -} - -#endif - -#if 0 -/* - * Curt McDowell - * Broadcom Corp. - * csm@broadcom.com - * - * IP checksum two bytes at a time with support for - * unaligned buffer. - * Works for len up to and including 0x20000. - * by Curt McDowell, Broadcom Corp. 12/08/2005 - */ - -static u16_t -lwip_standard_chksum2(void *dataptr, int len) -{ - u8_t *pb = dataptr; - u16_t *ps, t = 0; - u32_t sum = 0; - int odd = ((u32_t)pb & 1); - - /* Get aligned to u16_t */ - if (odd && len > 0) { - ((u8_t *)&t)[1] = *pb++; - len--; - } - - /* Add the bulk of the data */ - ps = (u16_t *)pb; - while (len > 1) { - sum += *ps++; - len -= 2; - } - - /* Consume left-over byte, if any */ - if (len > 0) - ((u8_t *)&t)[0] = *(u8_t *)ps;; - - /* Add end bytes */ - sum += t; - - /* Fold 32-bit sum to 16 bits */ - while (sum >> 16) - sum = (sum & 0xffff) + (sum >> 16); - - /* Swap if alignment was odd */ - if (odd) - sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8); - - return sum; -} - -/** - * An optimized checksum routine. Basically, it uses loop-unrolling on - * the checksum loop, treating the head and tail bytes specially, whereas - * the inner loop acts on 8 bytes at a time. - * - * @arg start of buffer to be checksummed. May be an odd byte address. - * @len number of bytes in the buffer to be checksummed. - * - * @todo First argument type conflicts with generic checksum routine. - * - * by Curt McDowell, Broadcom Corp. December 8th, 2005 - */ - -static u16_t -lwip_standard_chksum4(u8_t *pb, int len) -{ - u16_t *ps, t = 0; - u32_t *pl; - u32_t sum = 0, tmp; - /* starts at odd byte address? */ - int odd = ((u32_t)pb & 1); - - if (odd && len > 0) { - ((u8_t *)&t)[1] = *pb++; - len--; - } - - ps = (u16_t *)pb; - - if (((u32_t)ps & 3) && len > 1) { - sum += *ps++; - len -= 2; - } - - pl = (u32_t *)ps; - - while (len > 7) { - tmp = sum + *pl++; /* ping */ - if (tmp < sum) - tmp++; /* add back carry */ - - sum = tmp + *pl++; /* pong */ - if (sum < tmp) - sum++; /* add back carry */ - - len -= 8; - } - - /* make room in upper bits */ - sum = (sum >> 16) + (sum & 0xffff); - - ps = (u16_t *)pl; - - /* 16-bit aligned word remaining? */ - while (len > 1) { - sum += *ps++; - len -= 2; - } - - /* dangling tail byte remaining? */ - if (len > 0) /* include odd byte */ - ((u8_t *)&t)[0] = *(u8_t *)ps; - - sum += t; /* add end bytes */ - - while (sum >> 16) /* combine halves */ - sum = (sum >> 16) + (sum & 0xffff); - - if (odd) - sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8); - - return sum; -} -#endif - -/* inet_chksum_pseudo: - * - * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain. - */ - -u16_t -inet_chksum_pseudo(struct pbuf *p, - struct ip_addr *src, struct ip_addr *dest, - u8_t proto, u16_t proto_len) -{ - u32_t acc; - struct pbuf *q; - u8_t swapped; - - acc = 0; - swapped = 0; - /* iterate through all pbuf in chain */ - for(q = p; q != NULL; q = q->next) { - LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n", - (void *)q, (void *)q->next)); - acc += LWIP_CHKSUM(q->payload, q->len); - /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/ - while (acc >> 16) { - acc = (acc & 0xffffUL) + (acc >> 16); - } - if (q->len % 2 != 0) { - swapped = 1 - swapped; - acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8); - } - /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/ - } - - if (swapped) { - acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8); - } - acc += (src->addr & 0xffffUL); - acc += ((src->addr >> 16) & 0xffffUL); - acc += (dest->addr & 0xffffUL); - acc += ((dest->addr >> 16) & 0xffffUL); - acc += (u32_t)htons((u16_t)proto); - acc += (u32_t)htons(proto_len); - - while (acc >> 16) { - acc = (acc & 0xffffUL) + (acc >> 16); - } - LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc)); - return (u16_t)~(acc & 0xffffUL); -} - -/* inet_chksum: - * - * Calculates the Internet checksum over a portion of memory. Used primarely for IP - * and ICMP. - */ - -u16_t -inet_chksum(void *dataptr, u16_t len) -{ - u32_t acc; - - acc = LWIP_CHKSUM(dataptr, len); - while (acc >> 16) { - acc = (acc & 0xffff) + (acc >> 16); - } - return (u16_t)~(acc & 0xffff); -} - -u16_t -inet_chksum_pbuf(struct pbuf *p) -{ - u32_t acc; - struct pbuf *q; - u8_t swapped; - - acc = 0; - swapped = 0; - for(q = p; q != NULL; q = q->next) { - acc += LWIP_CHKSUM(q->payload, q->len); - while (acc >> 16) { - acc = (acc & 0xffffUL) + (acc >> 16); - } - if (q->len % 2 != 0) { - swapped = 1 - swapped; - acc = (acc & 0x00ffUL << 8) | (acc & 0xff00UL >> 8); - } - } - - if (swapped) { - acc = ((acc & 0x00ffUL) << 8) | ((acc & 0xff00UL) >> 8); - } - return (u16_t)~(acc & 0xffffUL); -} - -/* Here for now until needed in other places in lwIP */ -#ifndef isascii -#define in_range(c, lo, up) ((u8_t)c >= lo && (u8_t)c <= up) -#define isascii(c) in_range(c, 0x20, 0x7f) -#define isdigit(c) in_range(c, '0', '9') -#define isxdigit(c) (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F')) -#define islower(c) in_range(c, 'a', 'z') -#define isspace(c) (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v') -#endif - - - /* - * Ascii internet address interpretation routine. - * The value returned is in network order. - */ - - /* */ - /* inet_addr */ - u32_t inet_addr(const char *cp) - { - struct in_addr val; - - if (inet_aton(cp, &val)) { - return (val.s_addr); - } - return (INADDR_NONE); - } - - /* - * Check whether "cp" is a valid ascii representation - * of an Internet address and convert to a binary address. - * Returns 1 if the address is valid, 0 if not. - * This replaces inet_addr, the return value from which - * cannot distinguish between failure and a local broadcast address. - */ - /* */ - /* inet_aton */ - s8_t - inet_aton(const char *cp, struct in_addr *addr) - { - u32_t val; - s32_t base, n; - char c; - u32_t parts[4]; - u32_t* pp = parts; - - c = *cp; - for (;;) { - /* - * Collect number up to ``.''. - * Values are specified as for C: - * 0x=hex, 0=octal, isdigit=decimal. - */ - if (!isdigit(c)) - return (0); - val = 0; base = 10; - if (c == '0') { - c = *++cp; - if (c == 'x' || c == 'X') - base = 16, c = *++cp; - else - base = 8; - } - for (;;) { - if (isdigit(c)) { - val = (val * base) + (s16_t)(c - '0'); - c = *++cp; - } else if (base == 16 && isxdigit(c)) { - val = (val << 4) | - (s16_t)(c + 10 - (islower(c) ? 'a' : 'A')); - c = *++cp; - } else - break; - } - if (c == '.') { - /* - * Internet format: - * a.b.c.d - * a.b.c (with c treated as 16 bits) - * a.b (with b treated as 24 bits) - */ - if (pp >= parts + 3) - return (0); - *pp++ = val; - c = *++cp; - } else - break; - } - /* - * Check for trailing characters. - */ - if (c != '\0' && (!isascii(c) || !isspace(c))) - return (0); - /* - * Concoct the address according to - * the number of parts specified. - */ - n = pp - parts + 1; - switch (n) { - - case 0: - return (0); /* initial nondigit */ - - case 1: /* a -- 32 bits */ - break; - - case 2: /* a.b -- 8.24 bits */ - if (val > 0xffffff) - return (0); - val |= parts[0] << 24; - break; - - case 3: /* a.b.c -- 8.8.16 bits */ - if (val > 0xffff) - return (0); - val |= (parts[0] << 24) | (parts[1] << 16); - break; - - case 4: /* a.b.c.d -- 8.8.8.8 bits */ - if (val > 0xff) - return (0); - val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8); - break; - } - if (addr) - addr->s_addr = htonl(val); - return (1); - } - -/* Convert numeric IP address into decimal dotted ASCII representation. - * returns ptr to static buffer; not reentrant! - */ -char *inet_ntoa(struct in_addr addr) -{ - static char str[16]; - u32_t s_addr = addr.s_addr; - char inv[3]; - char *rp; - u8_t *ap; - u8_t rem; - u8_t n; - u8_t i; - - rp = str; - ap = (u8_t *)&s_addr; - for(n = 0; n < 4; n++) { - i = 0; - do { - rem = *ap % (u8_t)10; - *ap /= (u8_t)10; - inv[i++] = '0' + rem; - } while(*ap); - while(i--) - *rp++ = inv[i]; - *rp++ = '.'; - ap++; - } - *--rp = 0; - return str; -} - - -#ifndef BYTE_ORDER -#error BYTE_ORDER is not defined -#endif -#if BYTE_ORDER == LITTLE_ENDIAN - -u16_t -htons(u16_t n) -{ - return ((n & 0xff) << 8) | ((n & 0xff00) >> 8); -} - -u16_t -ntohs(u16_t n) -{ - return htons(n); -} - -u32_t -htonl(u32_t n) -{ - return ((n & 0xff) << 24) | - ((n & 0xff00) << 8) | - ((n & 0xff0000) >> 8) | - ((n & 0xff000000) >> 24); -} - -u32_t -ntohl(u32_t n) -{ - return htonl(n); -} - -#endif /* BYTE_ORDER == LITTLE_ENDIAN */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/inet6.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/inet6.c deleted file mode 100644 index c04915b73..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/inet6.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - - -/* inet6.c - * - * Functions common to all TCP/IP modules, such as the Internet checksum and the - * byte order functions. - * - */ - - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/inet.h" - - - -/* chksum: - * - * Sums up all 16 bit words in a memory portion. Also includes any odd byte. - * This function is used by the other checksum functions. - * - * For now, this is not optimized. Must be optimized for the particular processor - * arcitecture on which it is to run. Preferebly coded in assembler. - */ - -static u32_t -chksum(void *dataptr, u16_t len) -{ - u16_t *sdataptr = dataptr; - u32_t acc; - - - for(acc = 0; len > 1; len -= 2) { - acc += *sdataptr++; - } - - /* add up any odd byte */ - if (len == 1) { - acc += htons((u16_t)(*(u8_t *)dataptr) << 8); - } - - return acc; - -} - -/* inet_chksum_pseudo: - * - * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain. - */ - -u16_t -inet_chksum_pseudo(struct pbuf *p, - struct ip_addr *src, struct ip_addr *dest, - u8_t proto, u32_t proto_len) -{ - u32_t acc; - struct pbuf *q; - u8_t swapped, i; - - acc = 0; - swapped = 0; - for(q = p; q != NULL; q = q->next) { - acc += chksum(q->payload, q->len); - while (acc >> 16) { - acc = (acc & 0xffff) + (acc >> 16); - } - if (q->len % 2 != 0) { - swapped = 1 - swapped; - acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); - } - } - - if (swapped) { - acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); - } - - for(i = 0; i < 8; i++) { - acc += ((u16_t *)src->addr)[i] & 0xffff; - acc += ((u16_t *)dest->addr)[i] & 0xffff; - while (acc >> 16) { - acc = (acc & 0xffff) + (acc >> 16); - } - } - acc += (u16_t)htons((u16_t)proto); - acc += ((u16_t *)&proto_len)[0] & 0xffff; - acc += ((u16_t *)&proto_len)[1] & 0xffff; - - while (acc >> 16) { - acc = (acc & 0xffff) + (acc >> 16); - } - return ~(acc & 0xffff); -} - -/* inet_chksum: - * - * Calculates the Internet checksum over a portion of memory. Used primarely for IP - * and ICMP. - */ - -u16_t -inet_chksum(void *dataptr, u16_t len) -{ - u32_t acc, sum; - - acc = chksum(dataptr, len); - sum = (acc & 0xffff) + (acc >> 16); - sum += (sum >> 16); - return ~(sum & 0xffff); -} - -u16_t -inet_chksum_pbuf(struct pbuf *p) -{ - u32_t acc; - struct pbuf *q; - u8_t swapped; - - acc = 0; - swapped = 0; - for(q = p; q != NULL; q = q->next) { - acc += chksum(q->payload, q->len); - while (acc >> 16) { - acc = (acc & 0xffff) + (acc >> 16); - } - if (q->len % 2 != 0) { - swapped = 1 - swapped; - acc = (acc & 0xff << 8) | (acc & 0xff00 >> 8); - } - } - - if (swapped) { - acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); - } - return ~(acc & 0xffff); -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv4/icmp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv4/icmp.c deleted file mode 100644 index db820148b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv4/icmp.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* Some ICMP messages should be passed to the transport protocols. This - is not implemented. */ - -#include - -#include "lwip/opt.h" -#include "lwip/icmp.h" -#include "lwip/inet.h" -#include "lwip/ip.h" -#include "lwip/def.h" -#include "lwip/stats.h" -#include "lwip/snmp.h" - -void -icmp_input(struct pbuf *p, struct netif *inp) -{ - u8_t type; - u8_t code; - struct icmp_echo_hdr *iecho; - struct ip_hdr *iphdr; - struct ip_addr tmpaddr; - u16_t hlen; - - ICMP_STATS_INC(icmp.recv); - snmp_inc_icmpinmsgs(); - - - iphdr = p->payload; - hlen = IPH_HL(iphdr) * 4; - if (pbuf_header(p, -((s16_t)hlen)) || (p->tot_len < sizeof(u16_t)*2)) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len)); - pbuf_free(p); - ICMP_STATS_INC(icmp.lenerr); - snmp_inc_icmpinerrors(); - return; - } - - type = *((u8_t *)p->payload); - code = *(((u8_t *)p->payload)+1); - switch (type) { - case ICMP_ECHO: - /* broadcast or multicast destination address? */ - if (ip_addr_isbroadcast(&iphdr->dest, inp) || ip_addr_ismulticast(&iphdr->dest)) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n")); - ICMP_STATS_INC(icmp.err); - pbuf_free(p); - return; - } - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n")); - if (p->tot_len < sizeof(struct icmp_echo_hdr)) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n")); - pbuf_free(p); - ICMP_STATS_INC(icmp.lenerr); - snmp_inc_icmpinerrors(); - - return; - } - iecho = p->payload; - if (inet_chksum_pbuf(p) != 0) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n")); - pbuf_free(p); - ICMP_STATS_INC(icmp.chkerr); - snmp_inc_icmpinerrors(); - return; - } - tmpaddr.addr = iphdr->src.addr; - iphdr->src.addr = iphdr->dest.addr; - iphdr->dest.addr = tmpaddr.addr; - ICMPH_TYPE_SET(iecho, ICMP_ER); - /* adjust the checksum */ - if (iecho->chksum >= htons(0xffff - (ICMP_ECHO << 8))) { - iecho->chksum += htons(ICMP_ECHO << 8) + 1; - } else { - iecho->chksum += htons(ICMP_ECHO << 8); - } - ICMP_STATS_INC(icmp.xmit); - /* increase number of messages attempted to send */ - snmp_inc_icmpoutmsgs(); - /* increase number of echo replies attempted to send */ - snmp_inc_icmpoutechoreps(); - - pbuf_header(p, hlen); - ip_output_if(p, &(iphdr->src), IP_HDRINCL, - IPH_TTL(iphdr), 0, IP_PROTO_ICMP, inp); - break; - default: - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", (s16_t)type, (s16_t)code)); - ICMP_STATS_INC(icmp.proterr); - ICMP_STATS_INC(icmp.drop); - } - pbuf_free(p); -} - -void -icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t) -{ - struct pbuf *q; - struct ip_hdr *iphdr; - struct icmp_dur_hdr *idur; - - q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM); - /* ICMP header + IP header + 8 bytes of data */ - - iphdr = p->payload; - - idur = q->payload; - ICMPH_TYPE_SET(idur, ICMP_DUR); - ICMPH_CODE_SET(idur, t); - - memcpy((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8); - - /* calculate checksum */ - idur->chksum = 0; - idur->chksum = inet_chksum(idur, q->len); - ICMP_STATS_INC(icmp.xmit); - /* increase number of messages attempted to send */ - snmp_inc_icmpoutmsgs(); - /* increase number of destination unreachable messages attempted to send */ - snmp_inc_icmpoutdestunreachs(); - - ip_output(q, NULL, &(iphdr->src), - ICMP_TTL, 0, IP_PROTO_ICMP); - pbuf_free(q); -} - -#if IP_FORWARD -void -icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t) -{ - struct pbuf *q; - struct ip_hdr *iphdr; - struct icmp_te_hdr *tehdr; - - q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM); - - iphdr = p->payload; - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from ")); - ip_addr_debug_print(ICMP_DEBUG, &(iphdr->src)); - LWIP_DEBUGF(ICMP_DEBUG, (" to ")); - ip_addr_debug_print(ICMP_DEBUG, &(iphdr->dest)); - LWIP_DEBUGF(ICMP_DEBUG, ("\n")); - - tehdr = q->payload; - ICMPH_TYPE_SET(tehdr, ICMP_TE); - ICMPH_CODE_SET(tehdr, t); - - /* copy fields from original packet */ - memcpy((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8); - - /* calculate checksum */ - tehdr->chksum = 0; - tehdr->chksum = inet_chksum(tehdr, q->len); - ICMP_STATS_INC(icmp.xmit); - /* increase number of messages attempted to send */ - snmp_inc_icmpoutmsgs(); - /* increase number of destination unreachable messages attempted to send */ - snmp_inc_icmpouttimeexcds(); - ip_output(q, NULL, &(iphdr->src), - ICMP_TTL, 0, IP_PROTO_ICMP); - pbuf_free(q); -} - -#endif /* IP_FORWARD */ - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv4/ip.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv4/ip.c deleted file mode 100644 index 4db68c8e8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv4/ip.c +++ /dev/null @@ -1,508 +0,0 @@ -/* @file - * - * This is the IP layer implementation for incoming and outgoing IP traffic. - * - * @see ip_frag.c - * - */ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/ip.h" -#include "lwip/ip_frag.h" -#include "lwip/inet.h" -#include "lwip/netif.h" -#include "lwip/icmp.h" -#include "lwip/raw.h" -#include "lwip/udp.h" -#include "lwip/tcp.h" - -#include "lwip/stats.h" - -#include "arch/perf.h" - -#include "lwip/snmp.h" -#if LWIP_DHCP -# include "lwip/dhcp.h" -#endif /* LWIP_DHCP */ - - -/** - * Initializes the IP layer. - */ - -void -ip_init(void) -{ - /* no initializations as of yet */ -} - -/** - * Finds the appropriate network interface for a given IP address. It - * searches the list of network interfaces linearly. A match is found - * if the masked IP address of the network interface equals the masked - * IP address given to the function. - */ - -struct netif * -ip_route(struct ip_addr *dest) -{ - struct netif *netif; - - /* iterate through netifs */ - for(netif = netif_list; netif != NULL; netif = netif->next) { - /* network mask matches? */ - if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) { - /* return netif on which to forward IP packet */ - return netif; - } - } - /* no matching netif found, use default netif */ - return netif_default; -} -#if IP_FORWARD - -/** - * Forwards an IP packet. It finds an appropriate route for the - * packet, decrements the TTL value of the packet, adjusts the - * checksum and outputs the packet on the appropriate interface. - */ - -static struct netif * -ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp) -{ - struct netif *netif; - - PERF_START; - /* Find network interface where to forward this IP packet to. */ - netif = ip_route((struct ip_addr *)&(iphdr->dest)); - if (netif == NULL) { - LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for 0x%"X32_F" found\n", - iphdr->dest.addr)); - snmp_inc_ipnoroutes(); - return (struct netif *)NULL; - } - /* Do not forward packets onto the same network interface on which - * they arrived. */ - if (netif == inp) { - LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n")); - snmp_inc_ipnoroutes(); - return (struct netif *)NULL; - } - - /* decrement TTL */ - IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1); - /* send ICMP if TTL == 0 */ - if (IPH_TTL(iphdr) == 0) { - /* Don't send ICMP messages in response to ICMP messages */ - if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) { - icmp_time_exceeded(p, ICMP_TE_TTL); - snmp_inc_icmpouttimeexcds(); - } - return (struct netif *)NULL; - } - - /* Incrementally update the IP checksum. */ - if (IPH_CHKSUM(iphdr) >= htons(0xffff - 0x100)) { - IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100) + 1); - } else { - IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100)); - } - - LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to 0x%"X32_F"\n", - iphdr->dest.addr)); - - IP_STATS_INC(ip.fw); - IP_STATS_INC(ip.xmit); - snmp_inc_ipforwdatagrams(); - - PERF_STOP("ip_forward"); - /* transmit pbuf on chosen interface */ - netif->output(netif, p, (struct ip_addr *)&(iphdr->dest)); - return netif; -} -#endif /* IP_FORWARD */ - -/** - * This function is called by the network interface device driver when - * an IP packet is received. The function does the basic checks of the - * IP header such as packet size being at least larger than the header - * size etc. If the packet was not destined for us, the packet is - * forwarded (using ip_forward). The IP checksum is always checked. - * - * Finally, the packet is sent to the upper layer protocol input function. - * - * - * - */ - -err_t -ip_input(struct pbuf *p, struct netif *inp) { - struct ip_hdr *iphdr; - struct netif *netif; - u16_t iphdrlen; - - IP_STATS_INC(ip.recv); - snmp_inc_ipinreceives(); - - /* identify the IP header */ - iphdr = p->payload; - if (IPH_V(iphdr) != 4) { - LWIP_DEBUGF(IP_DEBUG | 1, ("IP packet dropped due to bad version number %"U16_F"\n", IPH_V(iphdr))); - ip_debug_print(p); - pbuf_free(p); - IP_STATS_INC(ip.err); - IP_STATS_INC(ip.drop); - snmp_inc_ipunknownprotos(); - return ERR_OK; - } - /* obtain IP header length in number of 32-bit words */ - iphdrlen = IPH_HL(iphdr); - /* calculate IP header length in bytes */ - iphdrlen *= 4; - - /* header length exceeds first pbuf length? */ - if (iphdrlen > p->len) { - LWIP_DEBUGF(IP_DEBUG | 2, ("IP header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet droppped.\n", - iphdrlen, p->len)); - /* free (drop) packet pbufs */ - pbuf_free(p); - IP_STATS_INC(ip.lenerr); - IP_STATS_INC(ip.drop); - snmp_inc_ipindiscards(); - return ERR_OK; - } - - /* verify checksum */ -#if CHECKSUM_CHECK_IP - if (inet_chksum(iphdr, iphdrlen) != 0) { - - LWIP_DEBUGF(IP_DEBUG | 2, ("Checksum (0x%"X16_F") failed, IP packet dropped.\n", inet_chksum(iphdr, iphdrlen))); - ip_debug_print(p); - pbuf_free(p); - IP_STATS_INC(ip.chkerr); - IP_STATS_INC(ip.drop); - snmp_inc_ipindiscards(); - return ERR_OK; - } -#endif - - /* Trim pbuf. This should have been done at the netif layer, - * but we'll do it anyway just to be sure that its done. */ - pbuf_realloc(p, ntohs(IPH_LEN(iphdr))); - - /* match packet against an interface, i.e. is this packet for us? */ - for (netif = netif_list; netif != NULL; netif = netif->next) { - - LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%"X32_F" netif->ip_addr 0x%"X32_F" (0x%"X32_F", 0x%"X32_F", 0x%"X32_F")\n", - iphdr->dest.addr, netif->ip_addr.addr, - iphdr->dest.addr & netif->netmask.addr, - netif->ip_addr.addr & netif->netmask.addr, - iphdr->dest.addr & ~(netif->netmask.addr))); - - /* interface is up and configured? */ - if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr)))) - { - /* unicast to this interface address? */ - if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr)) || - /* or broadcast on this interface network address? */ - ip_addr_isbroadcast(&(iphdr->dest), netif)) { - LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n", - netif->name[0], netif->name[1])); - /* break out of for loop */ - break; - } - } - } -#if LWIP_DHCP - /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed - * using link layer addressing (such as Ethernet MAC) so we must not filter on IP. - * According to RFC 1542 section 3.1.1, referred by RFC 2131). - */ - if (netif == NULL) { - /* remote port is DHCP server? */ - if (IPH_PROTO(iphdr) == IP_PROTO_UDP) { - LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: UDP packet to DHCP client port %"U16_F"\n", - ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest))); - if (ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest) == DHCP_CLIENT_PORT) { - LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: DHCP packet accepted.\n")); - netif = inp; - } - } - } -#endif /* LWIP_DHCP */ - /* packet not for us? */ - if (netif == NULL) { - /* packet not for us, route or discard */ - LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: packet not for us.\n")); -#if IP_FORWARD - /* non-broadcast packet? */ - if (!ip_addr_isbroadcast(&(iphdr->dest), inp)) { - /* try to forward IP packet on (other) interfaces */ - ip_forward(p, iphdr, inp); - } - else -#endif /* IP_FORWARD */ - { - snmp_inc_ipindiscards(); - } - pbuf_free(p); - return ERR_OK; - } - /* packet consists of multiple fragments? */ - if ((IPH_OFFSET(iphdr) & htons(IP_OFFMASK | IP_MF)) != 0) { -#if IP_REASSEMBLY /* packet fragment reassembly code present? */ - LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip_reass()\n", - ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & htons(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8)); - /* reassemble the packet*/ - p = ip_reass(p); - /* packet not fully reassembled yet? */ - if (p == NULL) { - return ERR_OK; - } - iphdr = p->payload; -#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */ - pbuf_free(p); - LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since it was fragmented (0x%"X16_F") (while IP_REASSEMBLY == 0).\n", - ntohs(IPH_OFFSET(iphdr)))); - IP_STATS_INC(ip.opterr); - IP_STATS_INC(ip.drop); - snmp_inc_ipunknownprotos(); - return ERR_OK; -#endif /* IP_REASSEMBLY */ - } - -#if IP_OPTIONS == 0 /* no support for IP options in the IP header? */ - if (iphdrlen > IP_HLEN) { - LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since there were IP options (while IP_OPTIONS == 0).\n")); - pbuf_free(p); - IP_STATS_INC(ip.opterr); - IP_STATS_INC(ip.drop); - snmp_inc_ipunknownprotos(); - return ERR_OK; - } -#endif /* IP_OPTIONS == 0 */ - - /* send to upper layers */ - LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n")); - ip_debug_print(p); - LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len)); - -#if LWIP_RAW - /* raw input did not eat the packet? */ - if (raw_input(p, inp) == 0) { -#endif /* LWIP_RAW */ - - switch (IPH_PROTO(iphdr)) { -#if LWIP_UDP - case IP_PROTO_UDP: - case IP_PROTO_UDPLITE: - snmp_inc_ipindelivers(); - udp_input(p, inp); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case IP_PROTO_TCP: - snmp_inc_ipindelivers(); - tcp_input(p, inp); - break; -#endif /* LWIP_TCP */ - case IP_PROTO_ICMP: - snmp_inc_ipindelivers(); - icmp_input(p, inp); - break; - default: - /* send ICMP destination protocol unreachable unless is was a broadcast */ - if (!ip_addr_isbroadcast(&(iphdr->dest), inp) && - !ip_addr_ismulticast(&(iphdr->dest))) { - p->payload = iphdr; - icmp_dest_unreach(p, ICMP_DUR_PROTO); - } - pbuf_free(p); - - LWIP_DEBUGF(IP_DEBUG | 2, ("Unsupported transport protocol %"U16_F"\n", IPH_PROTO(iphdr))); - - IP_STATS_INC(ip.proterr); - IP_STATS_INC(ip.drop); - snmp_inc_ipunknownprotos(); - } -#if LWIP_RAW - } /* LWIP_RAW */ -#endif - return ERR_OK; -} - -/** - * Sends an IP packet on a network interface. This function constructs - * the IP header and calculates the IP header checksum. If the source - * IP address is NULL, the IP address of the outgoing network - * interface is filled in as source address. - */ - -err_t -ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t tos, - u8_t proto, struct netif *netif) -{ - struct ip_hdr *iphdr; - u16_t ip_id = 0; - - snmp_inc_ipoutrequests(); - - if (dest != IP_HDRINCL) { - if (pbuf_header(p, IP_HLEN)) { - LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: not enough room for IP header in pbuf\n")); - - IP_STATS_INC(ip.err); - snmp_inc_ipoutdiscards(); - return ERR_BUF; - } - - iphdr = p->payload; - - IPH_TTL_SET(iphdr, ttl); - IPH_PROTO_SET(iphdr, proto); - - ip_addr_set(&(iphdr->dest), dest); - - IPH_VHLTOS_SET(iphdr, 4, IP_HLEN / 4, tos); - IPH_LEN_SET(iphdr, htons(p->tot_len)); - IPH_OFFSET_SET(iphdr, htons(IP_DF)); - IPH_ID_SET(iphdr, htons(ip_id)); - ++ip_id; - - if (ip_addr_isany(src)) { - ip_addr_set(&(iphdr->src), &(netif->ip_addr)); - } else { - ip_addr_set(&(iphdr->src), src); - } - - IPH_CHKSUM_SET(iphdr, 0); -#if CHECKSUM_GEN_IP - IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); -#endif - } else { - iphdr = p->payload; - dest = &(iphdr->dest); - } - -#if IP_FRAG - /* don't fragment if interface has mtu set to 0 [loopif] */ - if (netif->mtu && (p->tot_len > netif->mtu)) - return ip_frag(p,netif,dest); -#endif - - IP_STATS_INC(ip.xmit); - - LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], netif->num)); - ip_debug_print(p); - - LWIP_DEBUGF(IP_DEBUG, ("netif->output()")); - - return netif->output(netif, p, dest); -} - -/** - * Simple interface to ip_output_if. It finds the outgoing network - * interface and calls upon ip_output_if to do the actual work. - */ - -err_t -ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t tos, u8_t proto) -{ - struct netif *netif; - - if ((netif = ip_route(dest)) == NULL) { - LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: No route to 0x%"X32_F"\n", dest->addr)); - - IP_STATS_INC(ip.rterr); - snmp_inc_ipoutdiscards(); - return ERR_RTE; - } - - return ip_output_if(p, src, dest, ttl, tos, proto, netif); -} - -#if IP_DEBUG -void -ip_debug_print(struct pbuf *p) -{ - struct ip_hdr *iphdr = p->payload; - u8_t *payload; - - payload = (u8_t *)iphdr + IP_HLEN; - - LWIP_DEBUGF(IP_DEBUG, ("IP header:\n")); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |%2"S16_F" | 0x%02"X16_F" | %5"U16_F" | (v, hl, tos, len)\n", - IPH_V(iphdr), - IPH_HL(iphdr), - IPH_TOS(iphdr), - ntohs(IPH_LEN(iphdr)))); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %5"U16_F" |%"U16_F"%"U16_F"%"U16_F"| %4"U16_F" | (id, flags, offset)\n", - ntohs(IPH_ID(iphdr)), - ntohs(IPH_OFFSET(iphdr)) >> 15 & 1, - ntohs(IPH_OFFSET(iphdr)) >> 14 & 1, - ntohs(IPH_OFFSET(iphdr)) >> 13 & 1, - ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | 0x%04"X16_F" | (ttl, proto, chksum)\n", - IPH_TTL(iphdr), - IPH_PROTO(iphdr), - ntohs(IPH_CHKSUM(iphdr)))); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (src)\n", - ip4_addr1(&iphdr->src), - ip4_addr2(&iphdr->src), - ip4_addr3(&iphdr->src), - ip4_addr4(&iphdr->src))); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (dest)\n", - ip4_addr1(&iphdr->dest), - ip4_addr2(&iphdr->dest), - ip4_addr3(&iphdr->dest), - ip4_addr4(&iphdr->dest))); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); -} -#endif /* IP_DEBUG */ - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv4/ip_addr.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv4/ip_addr.c deleted file mode 100644 index 2af526e9f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv4/ip_addr.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/ip_addr.h" -#include "lwip/inet.h" -#include "lwip/netif.h" - -/* used by IP_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */ -const struct ip_addr ip_addr_any = { 0x00000000UL }; -const struct ip_addr ip_addr_broadcast = { 0xffffffffUL }; - -/* Determine if an address is a broadcast address on a network interface - * - * @param addr address to be checked - * @param netif the network interface against which the address is checked - * @return returns non-zero if the address is a broadcast address - * - */ - -u8_t ip_addr_isbroadcast(struct ip_addr *addr, struct netif *netif) -{ - /* all ones (broadcast) or all zeroes (old skool broadcast) */ - if ((addr->addr == ip_addr_broadcast.addr) || - (addr->addr == ip_addr_any.addr)) - return 1; - /* no broadcast support on this network interface? */ - else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) - /* the given address cannot be a broadcast address - * nor can we check against any broadcast addresses */ - return 0; - /* address matches network interface address exactly? => no broadcast */ - else if (addr->addr == netif->ip_addr.addr) - return 0; - /* on the same (sub) network... */ - else if (ip_addr_netcmp(addr, &(netif->ip_addr), &(netif->netmask)) - /* ...and host identifier bits are all ones? =>... */ - && ((addr->addr & ~netif->netmask.addr) == - (ip_addr_broadcast.addr & ~netif->netmask.addr))) - /* => network broadcast address */ - return 1; - else - return 0; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv4/ip_frag.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv4/ip_frag.c deleted file mode 100644 index 5a57138ce..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv4/ip_frag.c +++ /dev/null @@ -1,366 +0,0 @@ -/* @file - * - * This is the IP packet segmentation and reassembly implementation. - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Jani Monoses - * original reassembly code by Adam Dunkels - * - */ - -#include - -#include "lwip/opt.h" -/* #include "lwip/sys.h" */ -#include "lwip/ip.h" -#include "lwip/ip_frag.h" -#include "lwip/netif.h" -#include "lwip/stats.h" - - -/* - * Copy len bytes from offset in pbuf to buffer - * - * helper used by both ip_reass and ip_frag - */ -static struct pbuf * -copy_from_pbuf(struct pbuf *p, u16_t * offset, - u8_t * buffer, u16_t len) -{ - u16_t l; - - p->payload = (u8_t *)p->payload + *offset; - p->len -= *offset; - while (len) { - l = len < p->len ? len : p->len; - memcpy(buffer, p->payload, l); - buffer += l; - len -= l; - if (len) - p = p->next; - else - *offset = l; - } - return p; -} - -#define IP_REASS_BUFSIZE 5760 -#define IP_REASS_MAXAGE 30 -#define IP_REASS_TMO 1000 - -static u8_t ip_reassbuf[IP_HLEN + IP_REASS_BUFSIZE]; -static u8_t ip_reassbitmap[IP_REASS_BUFSIZE / (8 * 8) + 1]; -static const u8_t bitmap_bits[8] = { 0xff, 0x7f, 0x3f, 0x1f, - 0x0f, 0x07, 0x03, 0x01 -}; -static u16_t ip_reasslen; -static u8_t ip_reassflags; -#define IP_REASS_FLAG_LASTFRAG 0x01 - -static u8_t ip_reasstmr; - -/** - * Reassembly timer base function - * for both NO_SYS == 0 and 1 (!). - * - * Should be called every 1000 msec. - */ -void -ip_reass_tmr(void) -{ - if (ip_reasstmr > 0) { - ip_reasstmr--; - } -} - -/** - * Reassembles incoming IP fragments into an IP datagram. - * - * @param p points to a pbuf chain of the fragment - * @return NULL if reassembly is incomplete, ? otherwise - */ -struct pbuf * -ip_reass(struct pbuf *p) -{ - struct pbuf *q; - struct ip_hdr *fraghdr, *iphdr; - u16_t offset, len; - u16_t i; - - IPFRAG_STATS_INC(ip_frag.recv); - - iphdr = (struct ip_hdr *) ip_reassbuf; - fraghdr = (struct ip_hdr *) p->payload; - /* If ip_reasstmr is zero, no packet is present in the buffer, so we - write the IP header of the fragment into the reassembly - buffer. The timer is updated with the maximum age. */ - if (ip_reasstmr == 0) { - LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: new packet\n")); - memcpy(iphdr, fraghdr, IP_HLEN); - ip_reasstmr = IP_REASS_MAXAGE; - ip_reassflags = 0; - /* Clear the bitmap. */ - memset(ip_reassbitmap, 0, sizeof(ip_reassbitmap)); - } - - /* Check if the incoming fragment matches the one currently present - in the reasembly buffer. If so, we proceed with copying the - fragment into the buffer. */ - if (ip_addr_cmp(&iphdr->src, &fraghdr->src) && - ip_addr_cmp(&iphdr->dest, &fraghdr->dest) && - IPH_ID(iphdr) == IPH_ID(fraghdr)) { - LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching previous fragment ID=%"X16_F"\n", - ntohs(IPH_ID(fraghdr)))); - IPFRAG_STATS_INC(ip_frag.cachehit); - /* Find out the offset in the reassembly buffer where we should - copy the fragment. */ - len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4; - offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8; - - /* If the offset or the offset + fragment length overflows the - reassembly buffer, we discard the entire packet. */ - if (offset > IP_REASS_BUFSIZE || offset + len > IP_REASS_BUFSIZE) { - LWIP_DEBUGF(IP_REASS_DEBUG, - ("ip_reass: fragment outside of buffer (%"S16_F":%"S16_F"/%"S16_F").\n", offset, - offset + len, IP_REASS_BUFSIZE)); - ip_reasstmr = 0; - goto nullreturn; - } - - /* Copy the fragment into the reassembly buffer, at the right - offset. */ - LWIP_DEBUGF(IP_REASS_DEBUG, - ("ip_reass: copying with offset %"S16_F" into %"S16_F":%"S16_F"\n", offset, - IP_HLEN + offset, IP_HLEN + offset + len)); - i = IPH_HL(fraghdr) * 4; - copy_from_pbuf(p, &i, &ip_reassbuf[IP_HLEN + offset], len); - - /* Update the bitmap. */ - if (offset / (8 * 8) == (offset + len) / (8 * 8)) { - LWIP_DEBUGF(IP_REASS_DEBUG, - ("ip_reass: updating single byte in bitmap.\n")); - /* If the two endpoints are in the same byte, we only update that byte. */ - LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)", - offset / (8 * 8) < sizeof(ip_reassbitmap)); - ip_reassbitmap[offset / (8 * 8)] |= - bitmap_bits[(offset / 8) & 7] & - ~bitmap_bits[((offset + len) / 8) & 7]; - } else { - /* If the two endpoints are in different bytes, we update the - bytes in the endpoints and fill the stuff inbetween with - 0xff. */ - LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)", - offset / (8 * 8) < sizeof(ip_reassbitmap)); - ip_reassbitmap[offset / (8 * 8)] |= bitmap_bits[(offset / 8) & 7]; - LWIP_DEBUGF(IP_REASS_DEBUG, - ("ip_reass: updating many bytes in bitmap (%"S16_F":%"S16_F").\n", - 1 + offset / (8 * 8), (offset + len) / (8 * 8))); - for (i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) { - ip_reassbitmap[i] = 0xff; - } - LWIP_ASSERT("(offset + len) / (8 * 8) < sizeof(ip_reassbitmap)", - (offset + len) / (8 * 8) < sizeof(ip_reassbitmap)); - ip_reassbitmap[(offset + len) / (8 * 8)] |= - ~bitmap_bits[((offset + len) / 8) & 7]; - } - - /* If this fragment has the More Fragments flag set to zero, we - know that this is the last fragment, so we can calculate the - size of the entire packet. We also set the - IP_REASS_FLAG_LASTFRAG flag to indicate that we have received - the final fragment. */ - - if ((ntohs(IPH_OFFSET(fraghdr)) & IP_MF) == 0) { - ip_reassflags |= IP_REASS_FLAG_LASTFRAG; - ip_reasslen = offset + len; - LWIP_DEBUGF(IP_REASS_DEBUG, - ("ip_reass: last fragment seen, total len %"S16_F"\n", - ip_reasslen)); - } - - /* Finally, we check if we have a full packet in the buffer. We do - this by checking if we have the last fragment and if all bits - in the bitmap are set. */ - if (ip_reassflags & IP_REASS_FLAG_LASTFRAG) { - /* Check all bytes up to and including all but the last byte in - the bitmap. */ - LWIP_ASSERT("ip_reasslen / (8 * 8) - 1 < sizeof(ip_reassbitmap)", - ip_reasslen / (8 * 8) - 1 < sizeof(ip_reassbitmap)); - for (i = 0; i < ip_reasslen / (8 * 8) - 1; ++i) { - if (ip_reassbitmap[i] != 0xff) { - LWIP_DEBUGF(IP_REASS_DEBUG, - ("ip_reass: last fragment seen, bitmap %"S16_F"/%"S16_F" failed (%"X16_F")\n", - i, ip_reasslen / (8 * 8) - 1, ip_reassbitmap[i])); - goto nullreturn; - } - } - /* Check the last byte in the bitmap. It should contain just the - right amount of bits. */ - LWIP_ASSERT("ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap)", - ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap)); - if (ip_reassbitmap[ip_reasslen / (8 * 8)] != - (u8_t) ~ bitmap_bits[ip_reasslen / 8 & 7]) { - LWIP_DEBUGF(IP_REASS_DEBUG, - ("ip_reass: last fragment seen, bitmap %"S16_F" didn't contain %"X16_F" (%"X16_F")\n", - ip_reasslen / (8 * 8), ~bitmap_bits[ip_reasslen / 8 & 7], - ip_reassbitmap[ip_reasslen / (8 * 8)])); - goto nullreturn; - } - - /* Pretend to be a "normal" (i.e., not fragmented) IP packet - from now on. */ - ip_reasslen += IP_HLEN; - - IPH_LEN_SET(iphdr, htons(ip_reasslen)); - IPH_OFFSET_SET(iphdr, 0); - IPH_CHKSUM_SET(iphdr, 0); - IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); - - /* If we have come this far, we have a full packet in the - buffer, so we allocate a pbuf and copy the packet into it. We - also reset the timer. */ - ip_reasstmr = 0; - pbuf_free(p); - p = pbuf_alloc(PBUF_LINK, ip_reasslen, PBUF_POOL); - if (p != NULL) { - i = 0; - for (q = p; q != NULL; q = q->next) { - /* Copy enough bytes to fill this pbuf in the chain. The - available data in the pbuf is given by the q->len variable. */ - LWIP_DEBUGF(IP_REASS_DEBUG, - ("ip_reass: memcpy from %p (%"S16_F") to %p, %"S16_F" bytes\n", - (void *)&ip_reassbuf[i], i, q->payload, - q->len > ip_reasslen - i ? ip_reasslen - i : q->len)); - memcpy(q->payload, &ip_reassbuf[i], - q->len > ip_reasslen - i ? ip_reasslen - i : q->len); - i += q->len; - } - IPFRAG_STATS_INC(ip_frag.fw); - } else { - IPFRAG_STATS_INC(ip_frag.memerr); - } - LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: p %p\n", (void*)p)); - return p; - } - } - -nullreturn: - IPFRAG_STATS_INC(ip_frag.drop); - pbuf_free(p); - return NULL; -} - -#define MAX_MTU 1500 -static u8_t buf[MEM_ALIGN_SIZE(MAX_MTU)]; - -/** - * Fragment an IP datagram if too large for the netif. - * - * Chop the datagram in MTU sized chunks and send them in order - * by using a fixed size static memory buffer (PBUF_ROM) - */ -err_t -ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest) -{ - struct pbuf *rambuf; - struct pbuf *header; - struct ip_hdr *iphdr; - u16_t nfb = 0; - u16_t left, cop; - u16_t mtu = netif->mtu; - u16_t ofo, omf; - u16_t last; - u16_t poff = IP_HLEN; - u16_t tmp; - - /* Get a RAM based MTU sized pbuf */ - rambuf = pbuf_alloc(PBUF_LINK, 0, PBUF_REF); - if (rambuf == NULL) { - return ERR_MEM; - } - rambuf->tot_len = rambuf->len = mtu; - rambuf->payload = MEM_ALIGN((void *)buf); - - /* Copy the IP header in it */ - iphdr = rambuf->payload; - memcpy(iphdr, p->payload, IP_HLEN); - - /* Save original offset */ - tmp = ntohs(IPH_OFFSET(iphdr)); - ofo = tmp & IP_OFFMASK; - omf = tmp & IP_MF; - - left = p->tot_len - IP_HLEN; - - while (left) { - last = (left <= mtu - IP_HLEN); - - /* Set new offset and MF flag */ - ofo += nfb; - tmp = omf | (IP_OFFMASK & (ofo)); - if (!last) - tmp = tmp | IP_MF; - IPH_OFFSET_SET(iphdr, htons(tmp)); - - /* Fill this fragment */ - nfb = (mtu - IP_HLEN) / 8; - cop = last ? left : nfb * 8; - - p = copy_from_pbuf(p, &poff, (u8_t *) iphdr + IP_HLEN, cop); - - /* Correct header */ - IPH_LEN_SET(iphdr, htons(cop + IP_HLEN)); - IPH_CHKSUM_SET(iphdr, 0); - IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); - - if (last) - pbuf_realloc(rambuf, left + IP_HLEN); - /* This part is ugly: we alloc a RAM based pbuf for - * the link level header for each chunk and then - * free it.A PBUF_ROM style pbuf for which pbuf_header - * worked would make things simpler. - */ - header = pbuf_alloc(PBUF_LINK, 0, PBUF_RAM); - if (header != NULL) { - pbuf_chain(header, rambuf); - netif->output(netif, header, dest); - IPFRAG_STATS_INC(ip_frag.xmit); - pbuf_free(header); - } else { - pbuf_free(rambuf); - return ERR_MEM; - } - left -= cop; - } - pbuf_free(rambuf); - return ERR_OK; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv6/README b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv6/README deleted file mode 100644 index 362000486..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv6/README +++ /dev/null @@ -1 +0,0 @@ -IPv6 support in lwIP is very experimental. diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv6/icmp6.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv6/icmp6.c deleted file mode 100644 index 10b6903c4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv6/icmp6.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* Some ICMP messages should be passed to the transport protocols. This - is not implemented. */ - -#include "lwip/opt.h" - -#include "lwip/icmp.h" -#include "lwip/inet.h" -#include "lwip/ip.h" -#include "lwip/def.h" - -#include "lwip/stats.h" - - -void -icmp_input(struct pbuf *p, struct netif *inp) -{ - u8_t type; - struct icmp_echo_hdr *iecho; - struct ip_hdr *iphdr; - struct ip_addr tmpaddr; - -#ifdef ICMP_STATS - ++lwip_stats.icmp.recv; -#endif /* ICMP_STATS */ - - /* TODO: check length before accessing payload! */ - - type = ((u8_t *)p->payload)[0]; - - switch (type) { - case ICMP6_ECHO: - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n")); - - if (p->tot_len < sizeof(struct icmp_echo_hdr)) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n")); - - pbuf_free(p); -#ifdef ICMP_STATS - ++lwip_stats.icmp.lenerr; -#endif /* ICMP_STATS */ - - return; - } - iecho = p->payload; - iphdr = (struct ip_hdr *)((u8_t *)p->payload - IP_HLEN); - if (inet_chksum_pbuf(p) != 0) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len))); - -#ifdef ICMP_STATS - ++lwip_stats.icmp.chkerr; -#endif /* ICMP_STATS */ - /* return;*/ - } - LWIP_DEBUGF(ICMP_DEBUG, ("icmp: p->len %"S16_F" p->tot_len %"S16_F"\n", p->len, p->tot_len)); - ip_addr_set(&tmpaddr, &(iphdr->src)); - ip_addr_set(&(iphdr->src), &(iphdr->dest)); - ip_addr_set(&(iphdr->dest), &tmpaddr); - iecho->type = ICMP6_ER; - /* adjust the checksum */ - if (iecho->chksum >= htons(0xffff - (ICMP6_ECHO << 8))) { - iecho->chksum += htons(ICMP6_ECHO << 8) + 1; - } else { - iecho->chksum += htons(ICMP6_ECHO << 8); - } - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len))); -#ifdef ICMP_STATS - ++lwip_stats.icmp.xmit; -#endif /* ICMP_STATS */ - - /* LWIP_DEBUGF("icmp: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/ - ip_output_if (p, &(iphdr->src), IP_HDRINCL, - iphdr->hoplim, IP_PROTO_ICMP, inp); - break; - default: - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" not supported.\n", (s16_t)type)); -#ifdef ICMP_STATS - ++lwip_stats.icmp.proterr; - ++lwip_stats.icmp.drop; -#endif /* ICMP_STATS */ - } - - pbuf_free(p); -} - -void -icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t) -{ - struct pbuf *q; - struct ip_hdr *iphdr; - struct icmp_dur_hdr *idur; - - q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM); - /* ICMP header + IP header + 8 bytes of data */ - - iphdr = p->payload; - - idur = q->payload; - idur->type = (u8_t)ICMP6_DUR; - idur->icode = (u8_t)t; - - memcpy((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8); - - /* calculate checksum */ - idur->chksum = 0; - idur->chksum = inet_chksum(idur, q->len); -#ifdef ICMP_STATS - ++lwip_stats.icmp.xmit; -#endif /* ICMP_STATS */ - - ip_output(q, NULL, - (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP); - pbuf_free(q); -} - -void -icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t) -{ - struct pbuf *q; - struct ip_hdr *iphdr; - struct icmp_te_hdr *tehdr; - - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded\n")); - - q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM); - - iphdr = p->payload; - - tehdr = q->payload; - tehdr->type = (u8_t)ICMP6_TE; - tehdr->icode = (u8_t)t; - - /* copy fields from original packet */ - memcpy((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8); - - /* calculate checksum */ - tehdr->chksum = 0; - tehdr->chksum = inet_chksum(tehdr, q->len); -#ifdef ICMP_STATS - ++lwip_stats.icmp.xmit; -#endif /* ICMP_STATS */ - ip_output(q, NULL, - (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP); - pbuf_free(q); -} - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv6/ip6.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv6/ip6.c deleted file mode 100644 index 03037c818..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv6/ip6.c +++ /dev/null @@ -1,386 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - - - -/* ip.c - * - * This is the code for the IP layer for IPv6. - * - */ - - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/ip.h" -#include "lwip/inet.h" -#include "lwip/netif.h" -#include "lwip/icmp.h" -#include "lwip/udp.h" -#include "lwip/tcp.h" - -#include "lwip/stats.h" - -#include "arch/perf.h" - -/* ip_init: - * - * Initializes the IP layer. - */ - -void -ip_init(void) -{ -} - -/* ip_route: - * - * Finds the appropriate network interface for a given IP address. It searches the - * list of network interfaces linearly. A match is found if the masked IP address of - * the network interface equals the masked IP address given to the function. - */ - -struct netif * -ip_route(struct ip_addr *dest) -{ - struct netif *netif; - - for(netif = netif_list; netif != NULL; netif = netif->next) { - if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) { - return netif; - } - } - - return netif_default; -} - -/* ip_forward: - * - * Forwards an IP packet. It finds an appropriate route for the packet, decrements - * the TTL value of the packet, adjusts the checksum and outputs the packet on the - * appropriate interface. - */ - -static void -ip_forward(struct pbuf *p, struct ip_hdr *iphdr) -{ - struct netif *netif; - - PERF_START; - - if ((netif = ip_route((struct ip_addr *)&(iphdr->dest))) == NULL) { - - LWIP_DEBUGF(IP_DEBUG, ("ip_input: no forwarding route found for ")); -#if IP_DEBUG - ip_addr_debug_print(IP_DEBUG, &(iphdr->dest)); -#endif /* IP_DEBUG */ - LWIP_DEBUGF(IP_DEBUG, ("\n")); - pbuf_free(p); - return; - } - /* Decrement TTL and send ICMP if ttl == 0. */ - if (--iphdr->hoplim == 0) { - /* Don't send ICMP messages in response to ICMP messages */ - if (iphdr->nexthdr != IP_PROTO_ICMP) { - icmp_time_exceeded(p, ICMP_TE_TTL); - } - pbuf_free(p); - return; - } - - /* Incremental update of the IP checksum. */ - /* if (iphdr->chksum >= htons(0xffff - 0x100)) { - iphdr->chksum += htons(0x100) + 1; - } else { - iphdr->chksum += htons(0x100); - }*/ - - - LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to ")); -#if IP_DEBUG - ip_addr_debug_print(IP_DEBUG, &(iphdr->dest)); -#endif /* IP_DEBUG */ - LWIP_DEBUGF(IP_DEBUG, ("\n")); - -#ifdef IP_STATS - ++lwip_stats.ip.fw; - ++lwip_stats.ip.xmit; -#endif /* IP_STATS */ - - PERF_STOP("ip_forward"); - - netif->output(netif, p, (struct ip_addr *)&(iphdr->dest)); -} - -/* ip_input: - * - * This function is called by the network interface device driver when an IP packet is - * received. The function does the basic checks of the IP header such as packet size - * being at least larger than the header size etc. If the packet was not destined for - * us, the packet is forwarded (using ip_forward). The IP checksum is always checked. - * - * Finally, the packet is sent to the upper layer protocol input function. - */ - -void -ip_input(struct pbuf *p, struct netif *inp) { - struct ip_hdr *iphdr; - struct netif *netif; - - - PERF_START; - -#if IP_DEBUG - ip_debug_print(p); -#endif /* IP_DEBUG */ - - -#ifdef IP_STATS - ++lwip_stats.ip.recv; -#endif /* IP_STATS */ - - /* identify the IP header */ - iphdr = p->payload; - - - if (iphdr->v != 6) { - LWIP_DEBUGF(IP_DEBUG, ("IP packet dropped due to bad version number\n")); -#if IP_DEBUG - ip_debug_print(p); -#endif /* IP_DEBUG */ - pbuf_free(p); -#ifdef IP_STATS - ++lwip_stats.ip.err; - ++lwip_stats.ip.drop; -#endif /* IP_STATS */ - return; - } - - /* is this packet for us? */ - for(netif = netif_list; netif != NULL; netif = netif->next) { -#if IP_DEBUG - LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest ")); - ip_addr_debug_print(IP_DEBUG, &(iphdr->dest)); - LWIP_DEBUGF(IP_DEBUG, ("netif->ip_addr ")); - ip_addr_debug_print(IP_DEBUG, &(netif->ip_addr)); - LWIP_DEBUGF(IP_DEBUG, ("\n")); -#endif /* IP_DEBUG */ - if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr))) { - break; - } - } - - - if (netif == NULL) { - /* packet not for us, route or discard */ -#ifdef IP_FORWARD - ip_forward(p, iphdr); -#endif - pbuf_free(p); - return; - } - - pbuf_realloc(p, IP_HLEN + ntohs(iphdr->len)); - - /* send to upper layers */ -#if IP_DEBUG - /* LWIP_DEBUGF("ip_input: \n"); - ip_debug_print(p); - LWIP_DEBUGF("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/ -#endif /* IP_DEBUG */ - - - pbuf_header(p, -IP_HLEN); - - switch (iphdr->nexthdr) { - case IP_PROTO_UDP: - udp_input(p); - break; - case IP_PROTO_TCP: - tcp_input(p); - break; - case IP_PROTO_ICMP: - icmp_input(p, inp); - break; - default: - /* send ICMP destination protocol unreachable */ - icmp_dest_unreach(p, ICMP_DUR_PROTO); - pbuf_free(p); - LWIP_DEBUGF(IP_DEBUG, ("Unsupported transport protocol %"U16_F"\n", - iphdr->nexthdr)); - -#ifdef IP_STATS - ++lwip_stats.ip.proterr; - ++lwip_stats.ip.drop; -#endif /* IP_STATS */ - - } - PERF_STOP("ip_input"); -} - - -/* ip_output_if: - * - * Sends an IP packet on a network interface. This function constructs the IP header - * and calculates the IP header checksum. If the source IP address is NULL, - * the IP address of the outgoing network interface is filled in as source address. - */ - -err_t -ip_output_if (struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, - u8_t proto, struct netif *netif) -{ - struct ip_hdr *iphdr; - - PERF_START; - - printf("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len); - if (pbuf_header(p, IP_HLEN)) { - LWIP_DEBUGF(IP_DEBUG, ("ip_output: not enough room for IP header in pbuf\n")); -#ifdef IP_STATS - ++lwip_stats.ip.err; -#endif /* IP_STATS */ - - return ERR_BUF; - } - printf("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len); - - iphdr = p->payload; - - - if (dest != IP_HDRINCL) { - printf("!IP_HDRLINCL\n"); - iphdr->hoplim = ttl; - iphdr->nexthdr = proto; - iphdr->len = htons(p->tot_len - IP_HLEN); - ip_addr_set(&(iphdr->dest), dest); - - iphdr->v = 6; - - if (ip_addr_isany(src)) { - ip_addr_set(&(iphdr->src), &(netif->ip_addr)); - } else { - ip_addr_set(&(iphdr->src), src); - } - - } else { - dest = &(iphdr->dest); - } - -#ifdef IP_STATS - ++lwip_stats.ip.xmit; -#endif /* IP_STATS */ - - LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c (len %"U16_F")\n", netif->name[0], netif->name[1], p->tot_len)); -#if IP_DEBUG - ip_debug_print(p); -#endif /* IP_DEBUG */ - - PERF_STOP("ip_output_if"); - return netif->output(netif, p, dest); -} - -/* ip_output: - * - * Simple interface to ip_output_if. It finds the outgoing network interface and - * calls upon ip_output_if to do the actual work. - */ - -err_t -ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t proto) -{ - struct netif *netif; - if ((netif = ip_route(dest)) == NULL) { - LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%"X32_F"\n", dest->addr)); -#ifdef IP_STATS - ++lwip_stats.ip.rterr; -#endif /* IP_STATS */ - return ERR_RTE; - } - - return ip_output_if (p, src, dest, ttl, proto, netif); -} - -#if IP_DEBUG -void -ip_debug_print(struct pbuf *p) -{ - struct ip_hdr *iphdr = p->payload; - u8_t *payload; - - payload = (u8_t *)iphdr + IP_HLEN; - - LWIP_DEBUGF(IP_DEBUG, ("IP header:\n")); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" | %"X16_F"%"X16_F" | %"X16_F"%"X16_F" | (v, traffic class, flow label)\n", - iphdr->v, - iphdr->tclass1, iphdr->tclass2, - iphdr->flow1, iphdr->flow2)); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %5"U16_F" | %2"U16_F" | %2"U16_F" | (len, nexthdr, hoplim)\n", - ntohs(iphdr->len), - iphdr->nexthdr, - iphdr->hoplim)); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (src)\n", - ntohl(iphdr->src.addr[0]) >> 16 & 0xffff, - ntohl(iphdr->src.addr[0]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (src)\n", - ntohl(iphdr->src.addr[1]) >> 16 & 0xffff, - ntohl(iphdr->src.addr[1]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (src)\n", - ntohl(iphdr->src.addr[2]) >> 16 & 0xffff, - ntohl(iphdr->src.addr[2]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (src)\n", - ntohl(iphdr->src.addr[3]) >> 16 & 0xffff, - ntohl(iphdr->src.addr[3]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (dest)\n", - ntohl(iphdr->dest.addr[0]) >> 16 & 0xffff, - ntohl(iphdr->dest.addr[0]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (dest)\n", - ntohl(iphdr->dest.addr[1]) >> 16 & 0xffff, - ntohl(iphdr->dest.addr[1]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (dest)\n", - ntohl(iphdr->dest.addr[2]) >> 16 & 0xffff, - ntohl(iphdr->dest.addr[2]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (dest)\n", - ntohl(iphdr->dest.addr[3]) >> 16 & 0xffff, - ntohl(iphdr->dest.addr[3]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); -} -#endif /* IP_DEBUG */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv6/ip6_addr.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv6/ip6_addr.c deleted file mode 100644 index dcb507855..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/ipv6/ip6_addr.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/ip_addr.h" -#include "lwip/inet.h" - - -u8_t -ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2, - struct ip_addr *mask) -{ - return((addr1->addr[0] & mask->addr[0]) == (addr2->addr[0] & mask->addr[0]) && - (addr1->addr[1] & mask->addr[1]) == (addr2->addr[1] & mask->addr[1]) && - (addr1->addr[2] & mask->addr[2]) == (addr2->addr[2] & mask->addr[2]) && - (addr1->addr[3] & mask->addr[3]) == (addr2->addr[3] & mask->addr[3])); - -} - -u8_t -ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2) -{ - return(addr1->addr[0] == addr2->addr[0] && - addr1->addr[1] == addr2->addr[1] && - addr1->addr[2] == addr2->addr[2] && - addr1->addr[3] == addr2->addr[3]); -} - -void -ip_addr_set(struct ip_addr *dest, struct ip_addr *src) -{ - memcpy(dest, src, sizeof(struct ip_addr)); - /* dest->addr[0] = src->addr[0]; - dest->addr[1] = src->addr[1]; - dest->addr[2] = src->addr[2]; - dest->addr[3] = src->addr[3];*/ -} - -u8_t -ip_addr_isany(struct ip_addr *addr) -{ - if (addr == NULL) return 1; - return((addr->addr[0] | addr->addr[1] | addr->addr[2] | addr->addr[3]) == 0); -} - - -/*#if IP_DEBUG*/ -void -ip_addr_debug_print(struct ip_addr *addr) -{ - printf("%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F", - ntohl(addr->addr[0]) >> 16 & 0xffff, - ntohl(addr->addr[0]) & 0xffff, - ntohl(addr->addr[1]) >> 16 & 0xffff, - ntohl(addr->addr[1]) & 0xffff, - ntohl(addr->addr[2]) >> 16 & 0xffff, - ntohl(addr->addr[2]) & 0xffff, - ntohl(addr->addr[3]) >> 16 & 0xffff, - ntohl(addr->addr[3]) & 0xffff); -} -/*#endif*/ /* IP_DEBUG */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/mem.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/mem.c deleted file mode 100644 index b38d8f150..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/mem.c +++ /dev/null @@ -1,310 +0,0 @@ -/** @file - * - * Dynamic memory manager - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include - -#include "lwip/arch.h" -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/mem.h" - -#include "lwip/sys.h" - -#include "lwip/stats.h" - -struct mem { - mem_size_t next, prev; -#if MEM_ALIGNMENT == 1 - u8_t used; -#elif MEM_ALIGNMENT == 2 - u16_t used; -#elif MEM_ALIGNMENT == 4 - u32_t used; -#elif MEM_ALIGNMENT == 8 - u64_t used; -#else -#error "unhandled MEM_ALIGNMENT size" -#endif /* MEM_ALIGNMENT */ -}; - -static struct mem *ram_end; -static u8_t ram[MEM_SIZE + sizeof(struct mem) + MEM_ALIGNMENT]; - -#define MIN_SIZE 12 -#if 0 /* this one does not align correctly for some, resulting in crashes */ -#define SIZEOF_STRUCT_MEM (unsigned int)MEM_ALIGN_SIZE(sizeof(struct mem)) -#else -#define SIZEOF_STRUCT_MEM (sizeof(struct mem) + \ - (((sizeof(struct mem) % MEM_ALIGNMENT) == 0)? 0 : \ - (4 - (sizeof(struct mem) % MEM_ALIGNMENT)))) -#endif - -static struct mem *lfree; /* pointer to the lowest free block */ - -static sys_sem_t mem_sem; - -static void -plug_holes(struct mem *mem) -{ - struct mem *nmem; - struct mem *pmem; - - LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram); - LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end); - LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0); - - /* plug hole forward */ - LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE", mem->next <= MEM_SIZE); - - nmem = (struct mem *)&ram[mem->next]; - if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) { - if (lfree == nmem) { - lfree = mem; - } - mem->next = nmem->next; - ((struct mem *)&ram[nmem->next])->prev = (u8_t *)mem - ram; - } - - /* plug hole backward */ - pmem = (struct mem *)&ram[mem->prev]; - if (pmem != mem && pmem->used == 0) { - if (lfree == mem) { - lfree = pmem; - } - pmem->next = mem->next; - ((struct mem *)&ram[mem->next])->prev = (u8_t *)pmem - ram; - } - -} -void -mem_init(void) -{ - struct mem *mem; - - memset(ram, 0, MEM_SIZE); - mem = (struct mem *)ram; - mem->next = MEM_SIZE; - mem->prev = 0; - mem->used = 0; - ram_end = (struct mem *)&ram[MEM_SIZE]; - ram_end->used = 1; - ram_end->next = MEM_SIZE; - ram_end->prev = MEM_SIZE; - - mem_sem = sys_sem_new(1); - - lfree = (struct mem *)ram; - -#if MEM_STATS - lwip_stats.mem.avail = MEM_SIZE; -#endif /* MEM_STATS */ -} -void -mem_free(void *rmem) -{ - struct mem *mem; - - if (rmem == NULL) { - LWIP_DEBUGF(MEM_DEBUG | DBG_TRACE | 2, ("mem_free(p == NULL) was called.\n")); - return; - } - - sys_sem_wait(mem_sem); - - LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram && - (u8_t *)rmem < (u8_t *)ram_end); - - if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { - LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_free: illegal memory\n")); -#if MEM_STATS - ++lwip_stats.mem.err; -#endif /* MEM_STATS */ - sys_sem_signal(mem_sem); - return; - } - mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM); - - LWIP_ASSERT("mem_free: mem->used", mem->used); - - mem->used = 0; - - if (mem < lfree) { - lfree = mem; - } - -#if MEM_STATS - lwip_stats.mem.used -= mem->next - ((u8_t *)mem - ram); - -#endif /* MEM_STATS */ - plug_holes(mem); - sys_sem_signal(mem_sem); -} -void * -mem_reallocm(void *rmem, mem_size_t newsize) -{ - void *nmem; - nmem = mem_malloc(newsize); - if (nmem == NULL) { - return mem_realloc(rmem, newsize); - } - memcpy(nmem, rmem, newsize); - mem_free(rmem); - return nmem; -} - -void * -mem_realloc(void *rmem, mem_size_t newsize) -{ - mem_size_t size; - mem_size_t ptr, ptr2; - struct mem *mem, *mem2; - - /* Expand the size of the allocated memory region so that we can - adjust for alignment. */ - if ((newsize % MEM_ALIGNMENT) != 0) { - newsize += MEM_ALIGNMENT - ((newsize + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT); - } - - if (newsize > MEM_SIZE) { - return NULL; - } - - sys_sem_wait(mem_sem); - - LWIP_ASSERT("mem_realloc: legal memory", (u8_t *)rmem >= (u8_t *)ram && - (u8_t *)rmem < (u8_t *)ram_end); - - if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { - LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_realloc: illegal memory\n")); - return rmem; - } - mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM); - - ptr = (u8_t *)mem - ram; - - size = mem->next - ptr - SIZEOF_STRUCT_MEM; -#if MEM_STATS - lwip_stats.mem.used -= (size - newsize); -#endif /* MEM_STATS */ - - if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE < size) { - ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize; - mem2 = (struct mem *)&ram[ptr2]; - mem2->used = 0; - mem2->next = mem->next; - mem2->prev = ptr; - mem->next = ptr2; - if (mem2->next != MEM_SIZE) { - ((struct mem *)&ram[mem2->next])->prev = ptr2; - } - - plug_holes(mem2); - } - sys_sem_signal(mem_sem); - return rmem; -} -void * -mem_malloc(mem_size_t size) -{ - mem_size_t ptr, ptr2; - struct mem *mem, *mem2; - - if (size == 0) { - return NULL; - } - - /* Expand the size of the allocated memory region so that we can - adjust for alignment. */ - if ((size % MEM_ALIGNMENT) != 0) { - size += MEM_ALIGNMENT - ((size + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT); - } - - if (size > MEM_SIZE) { - return NULL; - } - - sys_sem_wait(mem_sem); - - for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE; ptr = ((struct mem *)&ram[ptr])->next) { - mem = (struct mem *)&ram[ptr]; - if (!mem->used && - mem->next - (ptr + SIZEOF_STRUCT_MEM) >= size + SIZEOF_STRUCT_MEM) { - ptr2 = ptr + SIZEOF_STRUCT_MEM + size; - mem2 = (struct mem *)&ram[ptr2]; - - mem2->prev = ptr; - mem2->next = mem->next; - mem->next = ptr2; - if (mem2->next != MEM_SIZE) { - ((struct mem *)&ram[mem2->next])->prev = ptr2; - } - - mem2->used = 0; - mem->used = 1; -#if MEM_STATS - lwip_stats.mem.used += (size + SIZEOF_STRUCT_MEM); - /* if (lwip_stats.mem.max < lwip_stats.mem.used) { - lwip_stats.mem.max = lwip_stats.mem.used; - } */ - if (lwip_stats.mem.max < ptr2) { - lwip_stats.mem.max = ptr2; - } -#endif /* MEM_STATS */ - - if (mem == lfree) { - /* Find next free block after mem */ - while (lfree->used && lfree != ram_end) { - lfree = (struct mem *)&ram[lfree->next]; - } - LWIP_ASSERT("mem_malloc: !lfree->used", !lfree->used); - } - sys_sem_signal(mem_sem); - LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.", - (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end); - LWIP_ASSERT("mem_malloc: allocated memory properly aligned.", - (unsigned long)((u8_t *)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0); - return (u8_t *)mem + SIZEOF_STRUCT_MEM; - } - } - LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size)); -#if MEM_STATS - ++lwip_stats.mem.err; -#endif /* MEM_STATS */ - sys_sem_signal(mem_sem); - return NULL; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/memp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/memp.c deleted file mode 100644 index c0cfce29c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/memp.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/memp.h" - -#include "lwip/pbuf.h" -#include "lwip/udp.h" -#include "lwip/raw.h" -#include "lwip/tcp.h" -#include "lwip/api.h" -#include "lwip/api_msg.h" -#include "lwip/tcpip.h" - -#include "lwip/sys.h" -#include "lwip/stats.h" - -struct memp { - struct memp *next; -}; - - - -static struct memp *memp_tab[MEMP_MAX]; - -static const u16_t memp_sizes[MEMP_MAX] = { - sizeof(struct pbuf), - sizeof(struct raw_pcb), - sizeof(struct udp_pcb), - sizeof(struct tcp_pcb), - sizeof(struct tcp_pcb_listen), - sizeof(struct tcp_seg), - sizeof(struct netbuf), - sizeof(struct netconn), - sizeof(struct api_msg), - sizeof(struct tcpip_msg), - sizeof(struct sys_timeout) -}; - -static const u16_t memp_num[MEMP_MAX] = { - MEMP_NUM_PBUF, - MEMP_NUM_RAW_PCB, - MEMP_NUM_UDP_PCB, - MEMP_NUM_TCP_PCB, - MEMP_NUM_TCP_PCB_LISTEN, - MEMP_NUM_TCP_SEG, - MEMP_NUM_NETBUF, - MEMP_NUM_NETCONN, - MEMP_NUM_API_MSG, - MEMP_NUM_TCPIP_MSG, - MEMP_NUM_SYS_TIMEOUT -}; - -static u8_t memp_memory[(MEMP_NUM_PBUF * - MEM_ALIGN_SIZE(sizeof(struct pbuf) + - sizeof(struct memp)) + - MEMP_NUM_RAW_PCB * - MEM_ALIGN_SIZE(sizeof(struct raw_pcb) + - sizeof(struct memp)) + - MEMP_NUM_UDP_PCB * - MEM_ALIGN_SIZE(sizeof(struct udp_pcb) + - sizeof(struct memp)) + - MEMP_NUM_TCP_PCB * - MEM_ALIGN_SIZE(sizeof(struct tcp_pcb) + - sizeof(struct memp)) + - MEMP_NUM_TCP_PCB_LISTEN * - MEM_ALIGN_SIZE(sizeof(struct tcp_pcb_listen) + - sizeof(struct memp)) + - MEMP_NUM_TCP_SEG * - MEM_ALIGN_SIZE(sizeof(struct tcp_seg) + - sizeof(struct memp)) + - MEMP_NUM_NETBUF * - MEM_ALIGN_SIZE(sizeof(struct netbuf) + - sizeof(struct memp)) + - MEMP_NUM_NETCONN * - MEM_ALIGN_SIZE(sizeof(struct netconn) + - sizeof(struct memp)) + - MEMP_NUM_API_MSG * - MEM_ALIGN_SIZE(sizeof(struct api_msg) + - sizeof(struct memp)) + - MEMP_NUM_TCPIP_MSG * - MEM_ALIGN_SIZE(sizeof(struct tcpip_msg) + - sizeof(struct memp)) + - MEMP_NUM_SYS_TIMEOUT * - MEM_ALIGN_SIZE(sizeof(struct sys_timeout) + - sizeof(struct memp)))]; - - -#if !SYS_LIGHTWEIGHT_PROT -static sys_sem_t mutex; -#endif - -#if MEMP_SANITY_CHECK -static int -memp_sanity(void) -{ - s16_t i, c; - struct memp *m, *n; - - for(i = 0; i < MEMP_MAX; i++) { - for(m = memp_tab[i]; m != NULL; m = m->next) { - c = 1; - for(n = memp_tab[i]; n != NULL; n = n->next) { - if (n == m) { - --c; - } - if (c < 0) return 0; /* LW was: abort(); */ - } - } - } - return 1; -} -#endif /* MEMP_SANITY_CHECK*/ - -void -memp_init(void) -{ - struct memp *m, *memp; - u16_t i, j; - u16_t size; - -#if MEMP_STATS - for(i = 0; i < MEMP_MAX; ++i) { - lwip_stats.memp[i].used = lwip_stats.memp[i].max = - lwip_stats.memp[i].err = 0; - lwip_stats.memp[i].avail = memp_num[i]; - } -#endif /* MEMP_STATS */ - - memp = (struct memp *)&memp_memory[0]; - for(i = 0; i < MEMP_MAX; ++i) { - size = MEM_ALIGN_SIZE(memp_sizes[i] + sizeof(struct memp)); - if (memp_num[i] > 0) { - memp_tab[i] = memp; - m = memp; - - for(j = 0; j < memp_num[i]; ++j) { - m->next = (struct memp *)MEM_ALIGN((u8_t *)m + size); - memp = m; - m = m->next; - } - memp->next = NULL; - memp = m; - } else { - memp_tab[i] = NULL; - } - } - -#if !SYS_LIGHTWEIGHT_PROT - mutex = sys_sem_new(1); -#endif - - -} - -void * -memp_malloc(memp_t type) -{ - struct memp *memp; - void *mem; -#if SYS_LIGHTWEIGHT_PROT - SYS_ARCH_DECL_PROTECT(old_level); -#endif - - LWIP_ASSERT("memp_malloc: type < MEMP_MAX", type < MEMP_MAX); - -#if SYS_LIGHTWEIGHT_PROT - SYS_ARCH_PROTECT(old_level); -#else /* SYS_LIGHTWEIGHT_PROT */ - sys_sem_wait(mutex); -#endif /* SYS_LIGHTWEIGHT_PROT */ - - memp = memp_tab[type]; - - if (memp != NULL) { - memp_tab[type] = memp->next; - memp->next = NULL; -#if MEMP_STATS - ++lwip_stats.memp[type].used; - if (lwip_stats.memp[type].used > lwip_stats.memp[type].max) { - lwip_stats.memp[type].max = lwip_stats.memp[type].used; - } -#endif /* MEMP_STATS */ -#if SYS_LIGHTWEIGHT_PROT - SYS_ARCH_UNPROTECT(old_level); -#else /* SYS_LIGHTWEIGHT_PROT */ - sys_sem_signal(mutex); -#endif /* SYS_LIGHTWEIGHT_PROT */ - LWIP_ASSERT("memp_malloc: memp properly aligned", - ((mem_ptr_t)MEM_ALIGN((u8_t *)memp + sizeof(struct memp)) % MEM_ALIGNMENT) == 0); - - mem = MEM_ALIGN((u8_t *)memp + sizeof(struct memp)); - return mem; - } else { - LWIP_DEBUGF(MEMP_DEBUG | 2, ("memp_malloc: out of memory in pool %"S16_F"\n", type)); -#if MEMP_STATS - ++lwip_stats.memp[type].err; -#endif /* MEMP_STATS */ -#if SYS_LIGHTWEIGHT_PROT - SYS_ARCH_UNPROTECT(old_level); -#else /* SYS_LIGHTWEIGHT_PROT */ - sys_sem_signal(mutex); -#endif /* SYS_LIGHTWEIGHT_PROT */ - return NULL; - } -} - -void -memp_free(memp_t type, void *mem) -{ - struct memp *memp; -#if SYS_LIGHTWEIGHT_PROT - SYS_ARCH_DECL_PROTECT(old_level); -#endif /* SYS_LIGHTWEIGHT_PROT */ - - if (mem == NULL) { - return; - } - memp = (struct memp *)((u8_t *)mem - sizeof(struct memp)); - -#if SYS_LIGHTWEIGHT_PROT - SYS_ARCH_PROTECT(old_level); -#else /* SYS_LIGHTWEIGHT_PROT */ - sys_sem_wait(mutex); -#endif /* SYS_LIGHTWEIGHT_PROT */ - -#if MEMP_STATS - lwip_stats.memp[type].used--; -#endif /* MEMP_STATS */ - - memp->next = memp_tab[type]; - memp_tab[type] = memp; - -#if MEMP_SANITY_CHECK - LWIP_ASSERT("memp sanity", memp_sanity()); -#endif - -#if SYS_LIGHTWEIGHT_PROT - SYS_ARCH_UNPROTECT(old_level); -#else /* SYS_LIGHTWEIGHT_PROT */ - sys_sem_signal(mutex); -#endif /* SYS_LIGHTWEIGHT_PROT */ -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/netif.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/netif.c deleted file mode 100644 index 3525089b2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/netif.c +++ /dev/null @@ -1,288 +0,0 @@ -/** - * @file - * - * lwIP network interface abstraction - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/tcp.h" - -struct netif *netif_list = NULL; -struct netif *netif_default = NULL; - -/** - * Add a network interface to the list of lwIP netifs. - * - * @param netif a pre-allocated netif structure - * @param ipaddr IP address for the new netif - * @param netmask network mask for the new netif - * @param gw default gateway IP address for the new netif - * @param state opaque data passed to the new netif - * @param init callback function that initializes the interface - * @param input callback function that is called to pass - * ingress packets up in the protocol layer stack. - * - * @return netif, or NULL if failed. - */ -struct netif * -netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask, - struct ip_addr *gw, - void *state, - err_t (* init)(struct netif *netif), - err_t (* input)(struct pbuf *p, struct netif *netif)) -{ - static s16_t netifnum = 0; - -#if LWIP_DHCP - /* netif not under DHCP control by default */ - netif->dhcp = NULL; -#endif - /* remember netif specific state information data */ - netif->state = state; - netif->num = netifnum++; - netif->input = input; - - netif_set_addr(netif, ipaddr, netmask, gw); - - /* call user specified initialization function for netif */ - if (init(netif) != ERR_OK) { - return NULL; - } - - /* add this netif to the list */ - netif->next = netif_list; - netif_list = netif; - LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP addr ", - netif->name[0], netif->name[1])); - ip_addr_debug_print(NETIF_DEBUG, ipaddr); - LWIP_DEBUGF(NETIF_DEBUG, (" netmask ")); - ip_addr_debug_print(NETIF_DEBUG, netmask); - LWIP_DEBUGF(NETIF_DEBUG, (" gw ")); - ip_addr_debug_print(NETIF_DEBUG, gw); - LWIP_DEBUGF(NETIF_DEBUG, ("\n")); - return netif; -} - -void -netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask, - struct ip_addr *gw) -{ - netif_set_ipaddr(netif, ipaddr); - netif_set_netmask(netif, netmask); - netif_set_gw(netif, gw); -} - -void netif_remove(struct netif * netif) -{ - if ( netif == NULL ) return; - - /* is it the first netif? */ - if (netif_list == netif) { - netif_list = netif->next; - } - else { - /* look for netif further down the list */ - struct netif * tmpNetif; - for (tmpNetif = netif_list; tmpNetif != NULL; tmpNetif = tmpNetif->next) { - if (tmpNetif->next == netif) { - tmpNetif->next = netif->next; - break; - } - } - if (tmpNetif == NULL) - return; /* we didn't find any netif today */ - } - /* this netif is default? */ - if (netif_default == netif) - /* reset default netif */ - netif_default = NULL; - LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") ); -} - -struct netif * -netif_find(char *name) -{ - struct netif *netif; - u8_t num; - - if (name == NULL) { - return NULL; - } - - num = name[2] - '0'; - - for(netif = netif_list; netif != NULL; netif = netif->next) { - if (num == netif->num && - name[0] == netif->name[0] && - name[1] == netif->name[1]) { - LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1])); - return netif; - } - } - LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1])); - return NULL; -} - -void -netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr) -{ - /* TODO: Handling of obsolete pcbs */ - /* See: http://mail.gnu.org/archive/html/lwip-users/2003-03/msg00118.html */ -#if LWIP_TCP - struct tcp_pcb *pcb; - struct tcp_pcb_listen *lpcb; - - /* address is actually being changed? */ - if ((ip_addr_cmp(ipaddr, &(netif->ip_addr))) == 0) - { - /* extern struct tcp_pcb *tcp_active_pcbs; defined by tcp.h */ - LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: netif address being changed\n")); - pcb = tcp_active_pcbs; - while (pcb != NULL) { - /* PCB bound to current local interface address? */ - if (ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) { - /* this connection must be aborted */ - struct tcp_pcb *next = pcb->next; - LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb)); - tcp_abort(pcb); - pcb = next; - } else { - pcb = pcb->next; - } - } - for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { - /* PCB bound to current local interface address? */ - if (ip_addr_cmp(&(lpcb->local_ip), &(netif->ip_addr))) { - /* The PCB is listening to the old ipaddr and - * is set to listen to the new one instead */ - ip_addr_set(&(lpcb->local_ip), ipaddr); - } - } - } -#endif - ip_addr_set(&(netif->ip_addr), ipaddr); -#if 0 /* only allowed for Ethernet interfaces TODO: how can we check? */ - /** For Ethernet network interfaces, we would like to send a - * "gratuitous ARP"; this is an ARP packet sent by a node in order - * to spontaneously cause other nodes to update an entry in their - * ARP cache. From RFC 3220 "IP Mobility Support for IPv4" section 4.6. - */ - etharp_query(netif, ipaddr, NULL); -#endif - LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: IP address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - netif->name[0], netif->name[1], - ip4_addr1(&netif->ip_addr), - ip4_addr2(&netif->ip_addr), - ip4_addr3(&netif->ip_addr), - ip4_addr4(&netif->ip_addr))); -} - -void -netif_set_gw(struct netif *netif, struct ip_addr *gw) -{ - ip_addr_set(&(netif->gw), gw); - LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - netif->name[0], netif->name[1], - ip4_addr1(&netif->gw), - ip4_addr2(&netif->gw), - ip4_addr3(&netif->gw), - ip4_addr4(&netif->gw))); -} - -void -netif_set_netmask(struct netif *netif, struct ip_addr *netmask) -{ - ip_addr_set(&(netif->netmask), netmask); - LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - netif->name[0], netif->name[1], - ip4_addr1(&netif->netmask), - ip4_addr2(&netif->netmask), - ip4_addr3(&netif->netmask), - ip4_addr4(&netif->netmask))); -} - -void -netif_set_default(struct netif *netif) -{ - netif_default = netif; - LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n", - netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\'')); -} - -/** - * Bring an interface up, available for processing - * traffic. - * - * @note: Enabling DHCP on a down interface will make it come - * up once configured. - * - * @see dhcp_start() - */ -void netif_set_up(struct netif *netif) -{ - netif->flags |= NETIF_FLAG_UP; -} - -/** - * Ask if an interface is up - */ -u8_t netif_is_up(struct netif *netif) -{ - return (netif->flags & NETIF_FLAG_UP)?1:0; -} - -/** - * Bring an interface down, disabling any traffic processing. - * - * @note: Enabling DHCP on a down interface will make it come - * up once configured. - * - * @see dhcp_start() - */ -void netif_set_down(struct netif *netif) -{ - netif->flags &= ~NETIF_FLAG_UP; -} - -void -netif_init(void) -{ - netif_list = netif_default = NULL; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/pbuf.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/pbuf.c deleted file mode 100644 index 2ece4b098..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/pbuf.c +++ /dev/null @@ -1,957 +0,0 @@ -/** - * @file - * Packet buffer management - * - * Packets are built from the pbuf data structure. It supports dynamic - * memory allocation for packet contents or can reference externally - * managed packet contents both in RAM and ROM. Quick allocation for - * incoming packets is provided through pools with fixed sized pbufs. - * - * A packet may span over multiple pbufs, chained as a singly linked - * list. This is called a "pbuf chain". - * - * Multiple packets may be queued, also using this singly linked list. - * This is called a "packet queue". - * - * So, a packet queue consists of one or more pbuf chains, each of - * which consist of one or more pbufs. Currently, queues are only - * supported in a limited section of lwIP, this is the etharp queueing - * code. Outside of this section no packet queues are supported yet. - * - * The differences between a pbuf chain and a packet queue are very - * precise but subtle. - * - * The last pbuf of a packet has a ->tot_len field that equals the - * ->len field. It can be found by traversing the list. If the last - * pbuf of a packet has a ->next field other than NULL, more packets - * are on the queue. - * - * Therefore, looping through a pbuf of a single packet, has an - * loop end condition (tot_len == p->len), NOT (next == NULL). - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include - -#include "lwip/opt.h" -#include "lwip/stats.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/memp.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include "arch/perf.h" - -static u8_t pbuf_pool_memory[MEM_ALIGNMENT - 1 + PBUF_POOL_SIZE * MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE + sizeof(struct pbuf))]; - -#if !SYS_LIGHTWEIGHT_PROT -static volatile u8_t pbuf_pool_free_lock, pbuf_pool_alloc_lock; -static sys_sem_t pbuf_pool_free_sem; -#endif - -static struct pbuf *pbuf_pool = NULL; - -/** - * Initializes the pbuf module. - * - * A large part of memory is allocated for holding the pool of pbufs. - * The size of the individual pbufs in the pool is given by the size - * parameter, and the number of pbufs in the pool by the num parameter. - * - * After the memory has been allocated, the pbufs are set up. The - * ->next pointer in each pbuf is set up to point to the next pbuf in - * the pool. - * - */ -void -pbuf_init(void) -{ - struct pbuf *p, *q = NULL; - u16_t i; - - pbuf_pool = (struct pbuf *)MEM_ALIGN(pbuf_pool_memory); - -#if PBUF_STATS - lwip_stats.pbuf.avail = PBUF_POOL_SIZE; -#endif /* PBUF_STATS */ - - /* Set up ->next pointers to link the pbufs of the pool together */ - p = pbuf_pool; - - for(i = 0; i < PBUF_POOL_SIZE; ++i) { - p->next = (struct pbuf *)((u8_t *)p + PBUF_POOL_BUFSIZE + sizeof(struct pbuf)); - p->len = p->tot_len = PBUF_POOL_BUFSIZE; - p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf))); - p->flags = PBUF_FLAG_POOL; - q = p; - p = p->next; - } - - /* The ->next pointer of last pbuf is NULL to indicate that there - are no more pbufs in the pool */ - q->next = NULL; - -#if !SYS_LIGHTWEIGHT_PROT - pbuf_pool_alloc_lock = 0; - pbuf_pool_free_lock = 0; - pbuf_pool_free_sem = sys_sem_new(1); -#endif -} - -/** - * @internal only called from pbuf_alloc() - */ -static struct pbuf * -pbuf_pool_alloc(void) -{ - struct pbuf *p = NULL; - - SYS_ARCH_DECL_PROTECT(old_level); - SYS_ARCH_PROTECT(old_level); - -#if !SYS_LIGHTWEIGHT_PROT - /* Next, check the actual pbuf pool, but if the pool is locked, we - pretend to be out of buffers and return NULL. */ - if (pbuf_pool_free_lock) { -#if PBUF_STATS - ++lwip_stats.pbuf.alloc_locked; -#endif /* PBUF_STATS */ - return NULL; - } - pbuf_pool_alloc_lock = 1; - if (!pbuf_pool_free_lock) { -#endif /* SYS_LIGHTWEIGHT_PROT */ - p = pbuf_pool; - if (p) { - pbuf_pool = p->next; - } -#if !SYS_LIGHTWEIGHT_PROT -#if PBUF_STATS - } else { - ++lwip_stats.pbuf.alloc_locked; -#endif /* PBUF_STATS */ - } - pbuf_pool_alloc_lock = 0; -#endif /* SYS_LIGHTWEIGHT_PROT */ - -#if PBUF_STATS - if (p != NULL) { - ++lwip_stats.pbuf.used; - if (lwip_stats.pbuf.used > lwip_stats.pbuf.max) { - lwip_stats.pbuf.max = lwip_stats.pbuf.used; - } - } -#endif /* PBUF_STATS */ - - SYS_ARCH_UNPROTECT(old_level); - return p; -} - - -/** - * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type). - * - * The actual memory allocated for the pbuf is determined by the - * layer at which the pbuf is allocated and the requested size - * (from the size parameter). - * - * @param flag this parameter decides how and where the pbuf - * should be allocated as follows: - * - * - PBUF_RAM: buffer memory for pbuf is allocated as one large - * chunk. This includes protocol headers as well. - * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for - * protocol headers. Additional headers must be prepended - * by allocating another pbuf and chain in to the front of - * the ROM pbuf. It is assumed that the memory used is really - * similar to ROM in that it is immutable and will not be - * changed. Memory which is dynamic should generally not - * be attached to PBUF_ROM pbufs. Use PBUF_REF instead. - * - PBUF_REF: no buffer memory is allocated for the pbuf, even for - * protocol headers. It is assumed that the pbuf is only - * being used in a single thread. If the pbuf gets queued, - * then pbuf_take should be called to copy the buffer. - * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from - * the pbuf pool that is allocated during pbuf_init(). - * - * @return the allocated pbuf. If multiple pbufs where allocated, this - * is the first pbuf of a pbuf chain. - */ -struct pbuf * -pbuf_alloc(pbuf_layer l, u16_t length, pbuf_flag flag) -{ - struct pbuf *p, *q, *r; - u16_t offset; - s32_t rem_len; /* remaining length */ - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F")\n", length)); - - /* determine header offset */ - offset = 0; - switch (l) { - case PBUF_TRANSPORT: - /* add room for transport (often TCP) layer header */ - offset += PBUF_TRANSPORT_HLEN; - /* FALLTHROUGH */ - case PBUF_IP: - /* add room for IP layer header */ - offset += PBUF_IP_HLEN; - /* FALLTHROUGH */ - case PBUF_LINK: - /* add room for link layer header */ - offset += PBUF_LINK_HLEN; - break; - case PBUF_RAW: - break; - default: - LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0); - return NULL; - } - - switch (flag) { - case PBUF_POOL: - /* allocate head of pbuf chain into p */ - p = pbuf_pool_alloc(); - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc: allocated pbuf %p\n", (void *)p)); - if (p == NULL) { -#if PBUF_STATS - ++lwip_stats.pbuf.err; -#endif /* PBUF_STATS */ - return NULL; - } - p->next = NULL; - - /* make the payload pointer point 'offset' bytes into pbuf data memory */ - p->payload = MEM_ALIGN((void *)((u8_t *)p + (sizeof(struct pbuf) + offset))); - LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned", - ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); - /* the total length of the pbuf chain is the requested size */ - p->tot_len = length; - /* set the length of the first pbuf in the chain */ - p->len = length > PBUF_POOL_BUFSIZE - offset? PBUF_POOL_BUFSIZE - offset: length; - /* set reference count (needed here in case we fail) */ - p->ref = 1; - - /* now allocate the tail of the pbuf chain */ - - /* remember first pbuf for linkage in next iteration */ - r = p; - /* remaining length to be allocated */ - rem_len = length - p->len; - /* any remaining pbufs to be allocated? */ - while (rem_len > 0) { - q = pbuf_pool_alloc(); - if (q == NULL) { - LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_alloc: Out of pbufs in pool.\n")); -#if PBUF_STATS - ++lwip_stats.pbuf.err; -#endif /* PBUF_STATS */ - /* free chain so far allocated */ - pbuf_free(p); - /* bail out unsuccesfully */ - return NULL; - } - q->next = NULL; - /* make previous pbuf point to this pbuf */ - r->next = q; - /* set total length of this pbuf and next in chain */ - q->tot_len = rem_len; - /* this pbuf length is pool size, unless smaller sized tail */ - q->len = rem_len > PBUF_POOL_BUFSIZE? PBUF_POOL_BUFSIZE: rem_len; - q->payload = (void *)((u8_t *)q + sizeof(struct pbuf)); - LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned", - ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0); - q->ref = 1; - /* calculate remaining length to be allocated */ - rem_len -= q->len; - /* remember this pbuf for linkage in next iteration */ - r = q; - } - /* end of chain */ - /*r->next = NULL;*/ - - break; - case PBUF_RAM: - /* If pbuf is to be allocated in RAM, allocate memory for it. */ - p = mem_malloc(MEM_ALIGN_SIZE(sizeof(struct pbuf) + offset) + MEM_ALIGN_SIZE(length)); - if (p == NULL) { - return NULL; - } - /* Set up internal structure of the pbuf. */ - p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf) + offset)); - p->len = p->tot_len = length; - p->next = NULL; - p->flags = PBUF_FLAG_RAM; - - LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned", - ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); - break; - /* pbuf references existing (non-volatile static constant) ROM payload? */ - case PBUF_ROM: - /* pbuf references existing (externally allocated) RAM payload? */ - case PBUF_REF: - /* only allocate memory for the pbuf structure */ - p = memp_malloc(MEMP_PBUF); - if (p == NULL) { - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n", flag == PBUF_ROM?"ROM":"REF")); - return NULL; - } - /* caller must set this field properly, afterwards */ - p->payload = NULL; - p->len = p->tot_len = length; - p->next = NULL; - p->flags = (flag == PBUF_ROM? PBUF_FLAG_ROM: PBUF_FLAG_REF); - break; - default: - LWIP_ASSERT("pbuf_alloc: erroneous flag", 0); - return NULL; - } - /* set reference count */ - p->ref = 1; - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p)); - return p; -} - - -#if PBUF_STATS -#define DEC_PBUF_STATS do { --lwip_stats.pbuf.used; } while (0) -#else /* PBUF_STATS */ -#define DEC_PBUF_STATS -#endif /* PBUF_STATS */ - -#define PBUF_POOL_FAST_FREE(p) do { \ - p->next = pbuf_pool; \ - pbuf_pool = p; \ - DEC_PBUF_STATS; \ - } while (0) - -#if SYS_LIGHTWEIGHT_PROT -#define PBUF_POOL_FREE(p) do { \ - SYS_ARCH_DECL_PROTECT(old_level); \ - SYS_ARCH_PROTECT(old_level); \ - PBUF_POOL_FAST_FREE(p); \ - SYS_ARCH_UNPROTECT(old_level); \ - } while (0) -#else /* SYS_LIGHTWEIGHT_PROT */ -#define PBUF_POOL_FREE(p) do { \ - sys_sem_wait(pbuf_pool_free_sem); \ - PBUF_POOL_FAST_FREE(p); \ - sys_sem_signal(pbuf_pool_free_sem); \ - } while (0) -#endif /* SYS_LIGHTWEIGHT_PROT */ - -/** - * Shrink a pbuf chain to a desired length. - * - * @param p pbuf to shrink. - * @param new_len desired new length of pbuf chain - * - * Depending on the desired length, the first few pbufs in a chain might - * be skipped and left unchanged. The new last pbuf in the chain will be - * resized, and any remaining pbufs will be freed. - * - * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted. - * @note May not be called on a packet queue. - * - * @bug Cannot grow the size of a pbuf (chain) (yet). - */ -void -pbuf_realloc(struct pbuf *p, u16_t new_len) -{ - struct pbuf *q; - u16_t rem_len; /* remaining length */ - s16_t grow; - - LWIP_ASSERT("pbuf_realloc: sane p->flags", p->flags == PBUF_FLAG_POOL || - p->flags == PBUF_FLAG_ROM || - p->flags == PBUF_FLAG_RAM || - p->flags == PBUF_FLAG_REF); - - /* desired length larger than current length? */ - if (new_len >= p->tot_len) { - /* enlarging not yet supported */ - return; - } - - /* the pbuf chain grows by (new_len - p->tot_len) bytes - * (which may be negative in case of shrinking) */ - grow = new_len - p->tot_len; - - /* first, step over any pbufs that should remain in the chain */ - rem_len = new_len; - q = p; - /* should this pbuf be kept? */ - while (rem_len > q->len) { - /* decrease remaining length by pbuf length */ - rem_len -= q->len; - /* decrease total length indicator */ - q->tot_len += grow; - /* proceed to next pbuf in chain */ - q = q->next; - } - /* we have now reached the new last pbuf (in q) */ - /* rem_len == desired length for pbuf q */ - - /* shrink allocated memory for PBUF_RAM */ - /* (other types merely adjust their length fields */ - if ((q->flags == PBUF_FLAG_RAM) && (rem_len != q->len)) { - /* reallocate and adjust the length of the pbuf that will be split */ - mem_realloc(q, (u8_t *)q->payload - (u8_t *)q + rem_len); - } - /* adjust length fields for new last pbuf */ - q->len = rem_len; - q->tot_len = q->len; - - /* any remaining pbufs in chain? */ - if (q->next != NULL) { - /* free remaining pbufs in chain */ - pbuf_free(q->next); - } - /* q is last packet in chain */ - q->next = NULL; - -} - -/** - * Adjusts the payload pointer to hide or reveal headers in the payload. - * - * Adjusts the ->payload pointer so that space for a header - * (dis)appears in the pbuf payload. - * - * The ->payload, ->tot_len and ->len fields are adjusted. - * - * @param hdr_size_inc Number of bytes to increment header size which - * increases the size of the pbuf. New space is on the front. - * (Using a negative value decreases the header size.) - * If hdr_size_inc is 0, this function does nothing and returns succesful. - * - * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so - * the call will fail. A check is made that the increase in header size does - * not move the payload pointer in front of the start of the buffer. - * @return non-zero on failure, zero on success. - * - */ -u8_t -pbuf_header(struct pbuf *p, s16_t header_size_increment) -{ - void *payload; - - LWIP_ASSERT("p != NULL", p != NULL); - if ((header_size_increment == 0) || (p == NULL)) return 0; - - /* remember current payload pointer */ - payload = p->payload; - - /* pbuf types containing payloads? */ - if (p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_POOL) { - /* set new payload pointer */ - p->payload = (u8_t *)p->payload - header_size_increment; - /* boundary check fails? */ - if ((u8_t *)p->payload < (u8_t *)p + sizeof(struct pbuf)) { - LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_header: failed as %p < %p (not enough space for new header size)\n", - (void *)p->payload, - (void *)(p + 1)));\ - /* restore old payload pointer */ - p->payload = payload; - /* bail out unsuccesfully */ - return 1; - } - /* pbuf types refering to external payloads? */ - } else if (p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_ROM) { - /* hide a header in the payload? */ - if ((header_size_increment < 0) && (header_size_increment - p->len <= 0)) { - /* increase payload pointer */ - p->payload = (u8_t *)p->payload - header_size_increment; - } else { - /* cannot expand payload to front (yet!) - * bail out unsuccesfully */ - return 1; - } - } - /* modify pbuf length fields */ - p->len += header_size_increment; - p->tot_len += header_size_increment; - - LWIP_DEBUGF( PBUF_DEBUG, ("pbuf_header: old %p new %p (%"S16_F")\n", - (void *)payload, (void *)p->payload, header_size_increment)); - - return 0; -} - -/** - * Dereference a pbuf chain or queue and deallocate any no-longer-used - * pbufs at the head of this chain or queue. - * - * Decrements the pbuf reference count. If it reaches zero, the pbuf is - * deallocated. - * - * For a pbuf chain, this is repeated for each pbuf in the chain, - * up to the first pbuf which has a non-zero reference count after - * decrementing. So, when all reference counts are one, the whole - * chain is free'd. - * - * @param pbuf The pbuf (chain) to be dereferenced. - * - * @return the number of pbufs that were de-allocated - * from the head of the chain. - * - * @note MUST NOT be called on a packet queue (Not verified to work yet). - * @note the reference counter of a pbuf equals the number of pointers - * that refer to the pbuf (or into the pbuf). - * - * @internal examples: - * - * Assuming existing chains a->b->c with the following reference - * counts, calling pbuf_free(a) results in: - * - * 1->2->3 becomes ...1->3 - * 3->3->3 becomes 2->3->3 - * 1->1->2 becomes ......1 - * 2->1->1 becomes 1->1->1 - * 1->1->1 becomes ....... - * - */ -u8_t -pbuf_free(struct pbuf *p) -{ - struct pbuf *q; - u8_t count; - SYS_ARCH_DECL_PROTECT(old_level); - - LWIP_ASSERT("p != NULL", p != NULL); - /* if assertions are disabled, proceed with debug output */ - if (p == NULL) { - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_free(p == NULL) was called.\n")); - return 0; - } - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_free(%p)\n", (void *)p)); - - PERF_START; - - LWIP_ASSERT("pbuf_free: sane flags", - p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_ROM || - p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_POOL); - - count = 0; - /* Since decrementing ref cannot be guaranteed to be a single machine operation - * we must protect it. Also, the later test of ref must be protected. - */ - SYS_ARCH_PROTECT(old_level); - /* de-allocate all consecutive pbufs from the head of the chain that - * obtain a zero reference count after decrementing*/ - while (p != NULL) { - /* all pbufs in a chain are referenced at least once */ - LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0); - /* decrease reference count (number of pointers to pbuf) */ - p->ref--; - /* this pbuf is no longer referenced to? */ - if (p->ref == 0) { - /* remember next pbuf in chain for next iteration */ - q = p->next; - LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: deallocating %p\n", (void *)p)); - /* is this a pbuf from the pool? */ - if (p->flags == PBUF_FLAG_POOL) { - p->len = p->tot_len = PBUF_POOL_BUFSIZE; - p->payload = (void *)((u8_t *)p + sizeof(struct pbuf)); - PBUF_POOL_FREE(p); - /* is this a ROM or RAM referencing pbuf? */ - } else if (p->flags == PBUF_FLAG_ROM || p->flags == PBUF_FLAG_REF) { - memp_free(MEMP_PBUF, p); - /* p->flags == PBUF_FLAG_RAM */ - } else { - mem_free(p); - } - count++; - /* proceed to next pbuf */ - p = q; - /* p->ref > 0, this pbuf is still referenced to */ - /* (and so the remaining pbufs in chain as well) */ - } else { - LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)p->ref)); - /* stop walking through the chain */ - p = NULL; - } - } - SYS_ARCH_UNPROTECT(old_level); - PERF_STOP("pbuf_free"); - /* return number of de-allocated pbufs */ - return count; -} - -/** - * Count number of pbufs in a chain - * - * @param p first pbuf of chain - * @return the number of pbufs in a chain - */ - -u8_t -pbuf_clen(struct pbuf *p) -{ - u8_t len; - - len = 0; - while (p != NULL) { - ++len; - p = p->next; - } - return len; -} - -/** - * Increment the reference count of the pbuf. - * - * @param p pbuf to increase reference counter of - * - */ -void -pbuf_ref(struct pbuf *p) -{ - SYS_ARCH_DECL_PROTECT(old_level); - /* pbuf given? */ - if (p != NULL) { - SYS_ARCH_PROTECT(old_level); - ++(p->ref); - SYS_ARCH_UNPROTECT(old_level); - } -} - -/** - * Concatenate two pbufs (each may be a pbuf chain) and take over - * the caller's reference of the tail pbuf. - * - * @note The caller MAY NOT reference the tail pbuf afterwards. - * Use pbuf_chain() for that purpose. - * - * @see pbuf_chain() - */ - -void -pbuf_cat(struct pbuf *h, struct pbuf *t) -{ - struct pbuf *p; - - LWIP_ASSERT("h != NULL (programmer violates API)", h != NULL); - LWIP_ASSERT("t != NULL (programmer violates API)", t != NULL); - if ((h == NULL) || (t == NULL)) return; - - /* proceed to last pbuf of chain */ - for (p = h; p->next != NULL; p = p->next) { - /* add total length of second chain to all totals of first chain */ - p->tot_len += t->tot_len; - } - /* { p is last pbuf of first h chain, p->next == NULL } */ - LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len); - LWIP_ASSERT("p->next == NULL", p->next == NULL); - /* add total length of second chain to last pbuf total of first chain */ - p->tot_len += t->tot_len; - /* chain last pbuf of head (p) with first of tail (t) */ - p->next = t; - /* p->next now references t, but the caller will drop its reference to t, - * so netto there is no change to the reference count of t. - */ -} - -/** - * Chain two pbufs (or pbuf chains) together. - * - * The caller MUST call pbuf_free(t) once it has stopped - * using it. Use pbuf_cat() instead if you no longer use t. - * - * @param h head pbuf (chain) - * @param t tail pbuf (chain) - * @note The pbufs MUST belong to the same packet. - * @note MAY NOT be called on a packet queue. - * - * The ->tot_len fields of all pbufs of the head chain are adjusted. - * The ->next field of the last pbuf of the head chain is adjusted. - * The ->ref field of the first pbuf of the tail chain is adjusted. - * - */ -void -pbuf_chain(struct pbuf *h, struct pbuf *t) -{ - pbuf_cat(h, t); - /* t is now referenced by h */ - pbuf_ref(t); - LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t)); -} - -/* For packet queueing. Note that queued packets MUST be dequeued first - * using pbuf_dequeue() before calling other pbuf_() functions. */ -#if ARP_QUEUEING -/** - * Add a packet to the end of a queue. - * - * @param q pointer to first packet on the queue - * @param n packet to be queued - * - * Both packets MUST be given, and must be different. - */ -void -pbuf_queue(struct pbuf *p, struct pbuf *n) -{ -#if PBUF_DEBUG /* remember head of queue */ - struct pbuf *q = p; -#endif - /* programmer stupidity checks */ - LWIP_ASSERT("p == NULL in pbuf_queue: this indicates a programmer error\n", p != NULL); - LWIP_ASSERT("n == NULL in pbuf_queue: this indicates a programmer error\n", n != NULL); - LWIP_ASSERT("p == n in pbuf_queue: this indicates a programmer error\n", p != n); - if ((p == NULL) || (n == NULL) || (p == n)){ - LWIP_DEBUGF(PBUF_DEBUG | DBG_HALT | 3, ("pbuf_queue: programmer argument error\n")); - return; - } - - /* iterate through all packets on queue */ - while (p->next != NULL) { -/* be very picky about pbuf chain correctness */ -#if PBUF_DEBUG - /* iterate through all pbufs in packet */ - while (p->tot_len != p->len) { - /* make sure invariant condition holds */ - LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len); - /* make sure each packet is complete */ - LWIP_ASSERT("p->next != NULL", p->next != NULL); - p = p->next; - /* { p->tot_len == p->len => p is last pbuf of a packet } */ - } - /* { p is last pbuf of a packet } */ - /* proceed to next packet on queue */ -#endif - /* proceed to next pbuf */ - if (p->next != NULL) p = p->next; - } - /* { p->tot_len == p->len and p->next == NULL } ==> - * { p is last pbuf of last packet on queue } */ - /* chain last pbuf of queue with n */ - p->next = n; - /* n is now referenced to by the (packet p in the) queue */ - pbuf_ref(n); -#if PBUF_DEBUG - LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, - ("pbuf_queue: newly queued packet %p sits after packet %p in queue %p\n", - (void *)n, (void *)p, (void *)q)); -#endif -} - -/** - * Remove a packet from the head of a queue. - * - * The caller MUST reference the remainder of the queue (as returned). The - * caller MUST NOT call pbuf_ref() as it implicitly takes over the reference - * from p. - * - * @param p pointer to first packet on the queue which will be dequeued. - * @return first packet on the remaining queue (NULL if no further packets). - * - */ -struct pbuf * -pbuf_dequeue(struct pbuf *p) -{ - struct pbuf *q; - LWIP_ASSERT("p != NULL", p != NULL); - - /* iterate through all pbufs in packet p */ - while (p->tot_len != p->len) { - /* make sure invariant condition holds */ - LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len); - /* make sure each packet is complete */ - LWIP_ASSERT("p->next != NULL", p->next != NULL); - p = p->next; - } - /* { p->tot_len == p->len } => p is the last pbuf of the first packet */ - /* remember next packet on queue in q */ - q = p->next; - /* dequeue packet p from queue */ - p->next = NULL; - /* any next packet on queue? */ - if (q != NULL) { - /* although q is no longer referenced by p, it MUST be referenced by - * the caller, who is maintaining this packet queue. So, we do not call - * pbuf_free(q) here, resulting in an implicit pbuf_ref(q) for the caller. */ - LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: first remaining packet on queue is %p\n", (void *)q)); - } else { - LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: no further packets on queue\n")); - } - return q; -} -#endif - -/** - * - * Create PBUF_POOL (or PBUF_RAM) copies of PBUF_REF pbufs. - * - * Used to queue packets on behalf of the lwIP stack, such as - * ARP based queueing. - * - * Go through a pbuf chain and replace any PBUF_REF buffers - * with PBUF_POOL (or PBUF_RAM) pbufs, each taking a copy of - * the referenced data. - * - * @note You MUST explicitly use p = pbuf_take(p); - * The pbuf you give as argument, may have been replaced - * by a (differently located) copy through pbuf_take()! - * - * @note Any replaced pbufs will be freed through pbuf_free(). - * This may deallocate them if they become no longer referenced. - * - * @param p Head of pbuf chain to process - * - * @return Pointer to head of pbuf chain - */ -struct pbuf * -pbuf_take(struct pbuf *p) -{ - struct pbuf *q , *prev, *head; - LWIP_ASSERT("pbuf_take: p != NULL\n", p != NULL); - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_take(%p)\n", (void*)p)); - - prev = NULL; - head = p; - /* iterate through pbuf chain */ - do - { - /* pbuf is of type PBUF_REF? */ - if (p->flags == PBUF_FLAG_REF) { - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE, ("pbuf_take: encountered PBUF_REF %p\n", (void *)p)); - /* allocate a pbuf (w/ payload) fully in RAM */ - /* PBUF_POOL buffers are faster if we can use them */ - if (p->len <= PBUF_POOL_BUFSIZE) { - q = pbuf_alloc(PBUF_RAW, p->len, PBUF_POOL); - if (q == NULL) { - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_POOL\n")); - } - } else { - /* no replacement pbuf yet */ - q = NULL; - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: PBUF_POOL too small to replace PBUF_REF\n")); - } - /* no (large enough) PBUF_POOL was available? retry with PBUF_RAM */ - if (q == NULL) { - q = pbuf_alloc(PBUF_RAW, p->len, PBUF_RAM); - if (q == NULL) { - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_RAM\n")); - } - } - /* replacement pbuf could be allocated? */ - if (q != NULL) - { - /* copy p to q */ - /* copy successor */ - q->next = p->next; - /* remove linkage from original pbuf */ - p->next = NULL; - /* remove linkage to original pbuf */ - if (prev != NULL) { - /* prev->next == p at this point */ - LWIP_ASSERT("prev->next == p", prev->next == p); - /* break chain and insert new pbuf instead */ - prev->next = q; - /* prev == NULL, so we replaced the head pbuf of the chain */ - } else { - head = q; - } - /* copy pbuf payload */ - memcpy(q->payload, p->payload, p->len); - q->tot_len = p->tot_len; - q->len = p->len; - /* in case p was the first pbuf, it is no longer refered to by - * our caller, as the caller MUST do p = pbuf_take(p); - * in case p was not the first pbuf, it is no longer refered to - * by prev. we can safely free the pbuf here. - * (note that we have set p->next to NULL already so that - * we will not free the rest of the chain by accident.) - */ - pbuf_free(p); - /* do not copy ref, since someone else might be using the old buffer */ - LWIP_DEBUGF(PBUF_DEBUG, ("pbuf_take: replaced PBUF_REF %p with %p\n", (void *)p, (void *)q)); - p = q; - } else { - /* deallocate chain */ - pbuf_free(head); - LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_take: failed to allocate replacement pbuf for %p\n", (void *)p)); - return NULL; - } - /* p->flags != PBUF_FLAG_REF */ - } else { - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: skipping pbuf not of type PBUF_REF\n")); - } - /* remember this pbuf */ - prev = p; - /* proceed to next pbuf in original chain */ - p = p->next; - } while (p); - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: end of chain reached.\n")); - - return head; -} - -/** - * Dechains the first pbuf from its succeeding pbufs in the chain. - * - * Makes p->tot_len field equal to p->len. - * @param p pbuf to dechain - * @return remainder of the pbuf chain, or NULL if it was de-allocated. - * @note May not be called on a packet queue. - */ -struct pbuf * -pbuf_dechain(struct pbuf *p) -{ - struct pbuf *q; - u8_t tail_gone = 1; - /* tail */ - q = p->next; - /* pbuf has successor in chain? */ - if (q != NULL) { - /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ - LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len); - /* enforce invariant if assertion is disabled */ - q->tot_len = p->tot_len - p->len; - /* decouple pbuf from remainder */ - p->next = NULL; - /* total length of pbuf p is its own length only */ - p->tot_len = p->len; - /* q is no longer referenced by p, free it */ - LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, ("pbuf_dechain: unreferencing %p\n", (void *)q)); - tail_gone = pbuf_free(q); - if (tail_gone > 0) { - LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, - ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q)); - } - /* return remaining tail or NULL if deallocated */ - } - /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ - LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len); - return (tail_gone > 0? NULL: q); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/raw.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/raw.c deleted file mode 100644 index 30199804d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/raw.c +++ /dev/null @@ -1,326 +0,0 @@ -/** - * @file - * - * Implementation of raw protocol PCBs for low-level handling of - * different types of protocols besides (or overriding) those - * already available in lwIP. - * - */ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/memp.h" -#include "lwip/inet.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/raw.h" - -#include "lwip/stats.h" - -#include "arch/perf.h" -#include "lwip/snmp.h" - -#if LWIP_RAW - -/** The list of RAW PCBs */ -static struct raw_pcb *raw_pcbs = NULL; - -void -raw_init(void) -{ - raw_pcbs = NULL; -} - -/** - * Determine if in incoming IP packet is covered by a RAW PCB - * and if so, pass it to a user-provided receive callback function. - * - * Given an incoming IP datagram (as a chain of pbufs) this function - * finds a corresponding RAW PCB and calls the corresponding receive - * callback function. - * - * @param pbuf pbuf to be demultiplexed to a RAW PCB. - * @param netif network interface on which the datagram was received. - * @Return - 1 if the packet has been eaten by a RAW PCB receive - * callback function. The caller MAY NOT not reference the - * packet any longer, and MAY NOT call pbuf_free(). - * @return - 0 if packet is not eaten (pbuf is still referenced by the - * caller). - * - */ -u8_t -raw_input(struct pbuf *p, struct netif *inp) -{ - struct raw_pcb *pcb; - struct ip_hdr *iphdr; - s16_t proto; - u8_t eaten = 0; - - iphdr = p->payload; - proto = IPH_PROTO(iphdr); - - pcb = raw_pcbs; - /* loop through all raw pcbs until the packet is eaten by one */ - /* this allows multiple pcbs to match against the packet by design */ - while ((eaten == 0) && (pcb != NULL)) { - if (pcb->protocol == proto) { - /* receive callback function available? */ - if (pcb->recv != NULL) { - /* the receive callback function did not eat the packet? */ - if (pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src)) != 0) - { - /* receive function ate the packet */ - p = NULL; - eaten = 1; - } - } - /* no receive callback function was set for this raw PCB */ - /* drop the packet */ - } - pcb = pcb->next; - } - return eaten; -} - -/** - * Bind a RAW PCB. - * - * @param pcb RAW PCB to be bound with a local address ipaddr. - * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to - * bind to all local interfaces. - * - * @return lwIP error code. - * - ERR_OK. Successful. No error occured. - * - ERR_USE. The specified IP address is already bound to by - * another RAW PCB. - * - * @see raw_disconnect() - */ -err_t -raw_bind(struct raw_pcb *pcb, struct ip_addr *ipaddr) -{ - ip_addr_set(&pcb->local_ip, ipaddr); - return ERR_OK; -} - -/** - * Connect an RAW PCB. This function is required by upper layers - * of lwip. Using the raw api you could use raw_sendto() instead - * - * This will associate the RAW PCB with the remote address. - * - * @param pcb RAW PCB to be connected with remote address ipaddr and port. - * @param ipaddr remote IP address to connect with. - * - * @return lwIP error code - * - * @see raw_disconnect() and raw_sendto() - */ -err_t -raw_connect(struct raw_pcb *pcb, struct ip_addr *ipaddr) -{ - ip_addr_set(&pcb->remote_ip, ipaddr); - return ERR_OK; -} - - -/** - * Set the callback function for received packets that match the - * raw PCB's protocol and binding. - * - * The callback function MUST either - * - eat the packet by calling pbuf_free() and returning non-zero. The - * packet will not be passed to other raw PCBs or other protocol layers. - * - not free the packet, and return zero. The packet will be matched - * against further PCBs and/or forwarded to another protocol layers. - * - * @return non-zero if the packet was free()d, zero if the packet remains - * available for others. - */ -void -raw_recv(struct raw_pcb *pcb, - u8_t (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p, - struct ip_addr *addr), - void *recv_arg) -{ - /* remember recv() callback and user data */ - pcb->recv = recv; - pcb->recv_arg = recv_arg; -} - -/** - * Send the raw IP packet to the given address. Note that actually you cannot - * modify the IP headers (this is inconsistent with the receive callback where - * you actually get the IP headers), you can only specify the IP payload here. - * It requires some more changes in lwIP. (there will be a raw_send() function - * then.) - * - * @param pcb the raw pcb which to send - * @param p the IP payload to send - * @param ipaddr the destination address of the IP packet - * - */ -err_t -raw_sendto(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr) -{ - err_t err; - struct netif *netif; - struct ip_addr *src_ip; - struct pbuf *q; /* q will be sent down the stack */ - - LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_sendto\n")); - - /* not enough space to add an IP header to first pbuf in given p chain? */ - if (pbuf_header(p, IP_HLEN)) { - /* allocate header in new pbuf */ - q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM); - /* new header pbuf could not be allocated? */ - if (q == NULL) { - LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 2, ("raw_sendto: could not allocate header\n")); - return ERR_MEM; - } - /* chain header q in front of given pbuf p */ - pbuf_chain(q, p); - /* { first pbuf q points to header pbuf } */ - LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); - } else { - /* first pbuf q equals given pbuf */ - q = p; - pbuf_header(q, -IP_HLEN); - } - - if ((netif = ip_route(ipaddr)) == NULL) { - LWIP_DEBUGF(RAW_DEBUG | 1, ("raw_sendto: No route to 0x%"X32_F"\n", ipaddr->addr)); -#if RAW_STATS - /* ++lwip_stats.raw.rterr;*/ -#endif /* RAW_STATS */ - /* free any temporary header pbuf allocated by pbuf_header() */ - if (q != p) { - pbuf_free(q); - } - return ERR_RTE; - } - - if (ip_addr_isany(&pcb->local_ip)) { - /* use outgoing network interface IP address as source address */ - src_ip = &(netif->ip_addr); - } else { - /* use RAW PCB local IP address as source address */ - src_ip = &(pcb->local_ip); - } - - err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif); - - /* did we chain a header earlier? */ - if (q != p) { - /* free the header */ - pbuf_free(q); - } - return err; -} - -/** - * Send the raw IP packet to the address given by raw_connect() - * - * @param pcb the raw pcb which to send - * @param p the IP payload to send - * @param ipaddr the destination address of the IP packet - * - */ -err_t -raw_send(struct raw_pcb *pcb, struct pbuf *p) -{ - return raw_sendto(pcb, p, &pcb->remote_ip); -} - -/** - * Remove an RAW PCB. - * - * @param pcb RAW PCB to be removed. The PCB is removed from the list of - * RAW PCB's and the data structure is freed from memory. - * - * @see raw_new() - */ -void -raw_remove(struct raw_pcb *pcb) -{ - struct raw_pcb *pcb2; - /* pcb to be removed is first in list? */ - if (raw_pcbs == pcb) { - /* make list start at 2nd pcb */ - raw_pcbs = raw_pcbs->next; - /* pcb not 1st in list */ - } else for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { - /* find pcb in raw_pcbs list */ - if (pcb2->next != NULL && pcb2->next == pcb) { - /* remove pcb from list */ - pcb2->next = pcb->next; - } - } - memp_free(MEMP_RAW_PCB, pcb); -} - -/** - * Create a RAW PCB. - * - * @return The RAW PCB which was created. NULL if the PCB data structure - * could not be allocated. - * - * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP) - * - * @see raw_remove() - */ -struct raw_pcb * -raw_new(u16_t proto) { - struct raw_pcb *pcb; - - LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_new\n")); - - pcb = memp_malloc(MEMP_RAW_PCB); - /* could allocate RAW PCB? */ - if (pcb != NULL) { - /* initialize PCB to all zeroes */ - memset(pcb, 0, sizeof(struct raw_pcb)); - pcb->protocol = proto; - pcb->ttl = RAW_TTL; - pcb->next = raw_pcbs; - raw_pcbs = pcb; - } - return pcb; -} - -#endif /* LWIP_RAW */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/stats.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/stats.c deleted file mode 100644 index c94623f7a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/stats.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include - -#include "lwip/opt.h" - -#include "lwip/def.h" - -#include "lwip/stats.h" -#include "lwip/mem.h" - - -#if LWIP_STATS -struct stats_ lwip_stats; - -void -stats_init(void) -{ - memset(&lwip_stats, 0, sizeof(struct stats_)); -} -#if LWIP_STATS_DISPLAY -void -stats_display_proto(struct stats_proto *proto, char *name) -{ - LWIP_PLATFORM_DIAG(("\n%s\n\t", name)); - LWIP_PLATFORM_DIAG(("xmit: %"S16_F"\n\t", proto->xmit)); - LWIP_PLATFORM_DIAG(("rexmit: %"S16_F"\n\t", proto->rexmit)); - LWIP_PLATFORM_DIAG(("recv: %"S16_F"\n\t", proto->recv)); - LWIP_PLATFORM_DIAG(("fw: %"S16_F"\n\t", proto->fw)); - LWIP_PLATFORM_DIAG(("drop: %"S16_F"\n\t", proto->drop)); - LWIP_PLATFORM_DIAG(("chkerr: %"S16_F"\n\t", proto->chkerr)); - LWIP_PLATFORM_DIAG(("lenerr: %"S16_F"\n\t", proto->lenerr)); - LWIP_PLATFORM_DIAG(("memerr: %"S16_F"\n\t", proto->memerr)); - LWIP_PLATFORM_DIAG(("rterr: %"S16_F"\n\t", proto->rterr)); - LWIP_PLATFORM_DIAG(("proterr: %"S16_F"\n\t", proto->proterr)); - LWIP_PLATFORM_DIAG(("opterr: %"S16_F"\n\t", proto->opterr)); - LWIP_PLATFORM_DIAG(("err: %"S16_F"\n\t", proto->err)); - LWIP_PLATFORM_DIAG(("cachehit: %"S16_F"\n", proto->cachehit)); -} - -void -stats_display_pbuf(struct stats_pbuf *pbuf) -{ - LWIP_PLATFORM_DIAG(("\nPBUF\n\t")); - LWIP_PLATFORM_DIAG(("avail: %"S16_F"\n\t", pbuf->avail)); - LWIP_PLATFORM_DIAG(("used: %"S16_F"\n\t", pbuf->used)); - LWIP_PLATFORM_DIAG(("max: %"S16_F"\n\t", pbuf->max)); - LWIP_PLATFORM_DIAG(("err: %"S16_F"\n\t", pbuf->err)); - LWIP_PLATFORM_DIAG(("alloc_locked: %"S16_F"\n\t", pbuf->alloc_locked)); - LWIP_PLATFORM_DIAG(("refresh_locked: %"S16_F"\n", pbuf->refresh_locked)); -} - -void -stats_display_mem(struct stats_mem *mem, char *name) -{ - LWIP_PLATFORM_DIAG(("\n MEM %s\n\t", name)); - LWIP_PLATFORM_DIAG(("avail: %"S16_F"\n\t", mem->avail)); - LWIP_PLATFORM_DIAG(("used: %"S16_F"\n\t", mem->used)); - LWIP_PLATFORM_DIAG(("max: %"S16_F"\n\t", mem->max)); - LWIP_PLATFORM_DIAG(("err: %"S16_F"\n", mem->err)); - -} - -void -stats_display(void) -{ - s16_t i; - char * memp_names[] = {"PBUF", "RAW_PCB", "UDP_PCB", "TCP_PCB", "TCP_PCB_LISTEN", - "TCP_SEG", "NETBUF", "NETCONN", "API_MSG", "TCP_MSG", "TIMEOUT"}; - stats_display_proto(&lwip_stats.link, "LINK"); - stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG"); - stats_display_proto(&lwip_stats.ip, "IP"); - stats_display_proto(&lwip_stats.icmp, "ICMP"); - stats_display_proto(&lwip_stats.udp, "UDP"); - stats_display_proto(&lwip_stats.tcp, "TCP"); - stats_display_pbuf(&lwip_stats.pbuf); - stats_display_mem(&lwip_stats.mem, "HEAP"); - for (i = 0; i < MEMP_MAX; i++) { - stats_display_mem(&lwip_stats.memp[i], memp_names[i]); - } - -} -#endif /* LWIP_STATS_DISPLAY */ -#endif /* LWIP_STATS */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/sys.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/sys.c deleted file mode 100644 index a7dbf34da..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/sys.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/sys.h" -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/memp.h" - -#if (NO_SYS == 0) - -struct sswt_cb -{ - s16_t timeflag; - sys_sem_t *psem; -}; - - - -void -sys_mbox_fetch(sys_mbox_t mbox, void **msg) -{ - u32_t time; - struct sys_timeouts *timeouts; - struct sys_timeout *tmptimeout; - sys_timeout_handler h; - void *arg; - - - again: - timeouts = sys_arch_timeouts(); - - if (!timeouts || !timeouts->next) { - sys_arch_mbox_fetch(mbox, msg, 0); - } else { - if (timeouts->next->time > 0) { - time = sys_arch_mbox_fetch(mbox, msg, timeouts->next->time); - } else { - time = SYS_ARCH_TIMEOUT; - } - - if (time == SYS_ARCH_TIMEOUT) { - /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message - could be fetched. We should now call the timeout handler and - deallocate the memory allocated for the timeout. */ - tmptimeout = timeouts->next; - timeouts->next = tmptimeout->next; - h = tmptimeout->h; - arg = tmptimeout->arg; - memp_free(MEMP_SYS_TIMEOUT, tmptimeout); - if (h != NULL) { - LWIP_DEBUGF(SYS_DEBUG, ("smf calling h=%p(%p)\n", (void *)h, (void *)arg)); - h(arg); - } - - /* We try again to fetch a message from the mbox. */ - goto again; - } else { - /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout - occured. The time variable is set to the number of - milliseconds we waited for the message. */ - if (time <= timeouts->next->time) { - timeouts->next->time -= time; - } else { - timeouts->next->time = 0; - } - } - - } -} - -void -sys_sem_wait(sys_sem_t sem) -{ - u32_t time; - struct sys_timeouts *timeouts; - struct sys_timeout *tmptimeout; - sys_timeout_handler h; - void *arg; - - /* while (sys_arch_sem_wait(sem, 1000) == 0); - return;*/ - - again: - - timeouts = sys_arch_timeouts(); - - if (!timeouts || !timeouts->next) { - sys_arch_sem_wait(sem, 0); - } else { - if (timeouts->next->time > 0) { - time = sys_arch_sem_wait(sem, timeouts->next->time); - } else { - time = SYS_ARCH_TIMEOUT; - } - - if (time == SYS_ARCH_TIMEOUT) { - /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message - could be fetched. We should now call the timeout handler and - deallocate the memory allocated for the timeout. */ - tmptimeout = timeouts->next; - timeouts->next = tmptimeout->next; - h = tmptimeout->h; - arg = tmptimeout->arg; - memp_free(MEMP_SYS_TIMEOUT, tmptimeout); - if (h != NULL) { - LWIP_DEBUGF(SYS_DEBUG, ("ssw h=%p(%p)\n", (void *)h, (void *)arg)); - h(arg); - } - - - /* We try again to fetch a message from the mbox. */ - goto again; - } else { - /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout - occured. The time variable is set to the number of - milliseconds we waited for the message. */ - if (time <= timeouts->next->time) { - timeouts->next->time -= time; - } else { - timeouts->next->time = 0; - } - } - - } -} - -void -sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg) -{ - struct sys_timeouts *timeouts; - struct sys_timeout *timeout, *t; - - timeout = memp_malloc(MEMP_SYS_TIMEOUT); - if (timeout == NULL) { - return; - } - timeout->next = NULL; - timeout->h = h; - timeout->arg = arg; - timeout->time = msecs; - - timeouts = sys_arch_timeouts(); - - LWIP_DEBUGF(SYS_DEBUG, ("sys_timeout: %p msecs=%"U32_F" h=%p arg=%p\n", - (void *)timeout, msecs, (void *)h, (void *)arg)); - - LWIP_ASSERT("sys_timeout: timeouts != NULL", timeouts != NULL); - - if (timeouts->next == NULL) { - timeouts->next = timeout; - return; - } - - if (timeouts->next->time > msecs) { - timeouts->next->time -= msecs; - timeout->next = timeouts->next; - timeouts->next = timeout; - } else { - for(t = timeouts->next; t != NULL; t = t->next) { - timeout->time -= t->time; - if (t->next == NULL || t->next->time > timeout->time) { - if (t->next != NULL) { - t->next->time -= timeout->time; - } - timeout->next = t->next; - t->next = timeout; - break; - } - } - } - -} - -/* Go through timeout list (for this task only) and remove the first matching entry, - even though the timeout has not triggered yet. -*/ - -void -sys_untimeout(sys_timeout_handler h, void *arg) -{ - struct sys_timeouts *timeouts; - struct sys_timeout *prev_t, *t; - - timeouts = sys_arch_timeouts(); - - if (timeouts->next == NULL) - return; - - for (t = timeouts->next, prev_t = NULL; t != NULL; prev_t = t, t = t->next) - { - if ((t->h == h) && (t->arg == arg)) - { - /* We have a match */ - /* Unlink from previous in list */ - if (prev_t == NULL) - timeouts->next = t->next; - else - prev_t->next = t->next; - /* If not the last one, add time of this one back to next */ - if (t->next != NULL) - t->next->time += t->time; - memp_free(MEMP_SYS_TIMEOUT, t); - return; - } - } - return; -} - - - - - -static void -sswt_handler(void *arg) -{ - struct sswt_cb *sswt_cb = (struct sswt_cb *) arg; - - /* Timeout. Set flag to TRUE and signal semaphore */ - sswt_cb->timeflag = 1; - sys_sem_signal(*(sswt_cb->psem)); -} - -/* Wait for a semaphore with timeout (specified in ms) */ -/* timeout = 0: wait forever */ -/* Returns 0 on timeout. 1 otherwise */ - -int -sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout) -{ - struct sswt_cb sswt_cb; - - sswt_cb.psem = &sem; - sswt_cb.timeflag = 0; - - /* If timeout is zero, then just wait forever */ - if (timeout > 0) - /* Create a timer and pass it the address of our flag */ - sys_timeout(timeout, sswt_handler, &sswt_cb); - sys_sem_wait(sem); - /* Was it a timeout? */ - if (sswt_cb.timeflag) - { - /* timeout */ - return 0; - } else { - /* Not a timeout. Remove timeout entry */ - sys_untimeout(sswt_handler, &sswt_cb); - return 1; - } - -} - - -void -sys_msleep(u32_t ms) -{ - sys_sem_t delaysem = sys_sem_new(0); - - sys_sem_wait_timeout(delaysem, ms); - - sys_sem_free(delaysem); -} - - -#endif /* NO_SYS */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/tcp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/tcp.c deleted file mode 100644 index 41a9edb4e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/tcp.c +++ /dev/null @@ -1,1171 +0,0 @@ -/** - * @file - * - * Transmission Control Protocol for IP - * - * This file contains common functions for the TCP implementation, such as functinos - * for manipulating the data structures and the TCP timer functions. TCP functions - * related to input and output is found in tcp_in.c and tcp_out.c respectively. - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include - -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/memp.h" - -#include "lwip/tcp.h" -#if LWIP_TCP - -/* Incremented every coarse grained timer shot - (typically every 500 ms, determined by TCP_COARSE_TIMEOUT). */ -u32_t tcp_ticks; -const u8_t tcp_backoff[13] = - { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7}; - -/* The TCP PCB lists. */ - -/** List of all TCP PCBs in LISTEN state */ -union tcp_listen_pcbs_t tcp_listen_pcbs; -/** List of all TCP PCBs that are in a state in which - * they accept or send data. */ -struct tcp_pcb *tcp_active_pcbs; -/** List of all TCP PCBs in TIME-WAIT state */ -struct tcp_pcb *tcp_tw_pcbs; - -struct tcp_pcb *tcp_tmp_pcb; - -static u8_t tcp_timer; -static u16_t tcp_new_port(void); - -/** - * Initializes the TCP layer. - */ -void -tcp_init(void) -{ - /* Clear globals. */ - tcp_listen_pcbs.listen_pcbs = NULL; - tcp_active_pcbs = NULL; - tcp_tw_pcbs = NULL; - tcp_tmp_pcb = NULL; - - /* initialize timer */ - tcp_ticks = 0; - tcp_timer = 0; - -} - -/** - * Called periodically to dispatch TCP timers. - * - */ -void -tcp_tmr(void) -{ - /* Call tcp_fasttmr() every 250 ms */ - tcp_fasttmr(); - - if (++tcp_timer & 1) { - /* Call tcp_tmr() every 500 ms, i.e., every other timer - tcp_tmr() is called. */ - tcp_slowtmr(); - } -} - -/** - * Closes the connection held by the PCB. - * - */ -err_t -tcp_close(struct tcp_pcb *pcb) -{ - err_t err; - -#if TCP_DEBUG - LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in state ")); - tcp_debug_print_state(pcb->state); - LWIP_DEBUGF(TCP_DEBUG, ("\n")); -#endif /* TCP_DEBUG */ - switch (pcb->state) { - case CLOSED: - /* Closing a pcb in the CLOSED state might seem erroneous, - * however, it is in this state once allocated and as yet unused - * and the user needs some way to free it should the need arise. - * Calling tcp_close() with a pcb that has already been closed, (i.e. twice) - * or for a pcb that has been used and then entered the CLOSED state - * is erroneous, but this should never happen as the pcb has in those cases - * been freed, and so any remaining handles are bogus. */ - err = ERR_OK; - memp_free(MEMP_TCP_PCB, pcb); - pcb = NULL; - break; - case LISTEN: - err = ERR_OK; - tcp_pcb_remove((struct tcp_pcb **)&tcp_listen_pcbs.pcbs, pcb); - memp_free(MEMP_TCP_PCB_LISTEN, pcb); - pcb = NULL; - break; - case SYN_SENT: - err = ERR_OK; - tcp_pcb_remove(&tcp_active_pcbs, pcb); - memp_free(MEMP_TCP_PCB, pcb); - pcb = NULL; - break; - case SYN_RCVD: - case ESTABLISHED: - err = tcp_send_ctrl(pcb, TCP_FIN); - if (err == ERR_OK) { - pcb->state = FIN_WAIT_1; - } - break; - case CLOSE_WAIT: - err = tcp_send_ctrl(pcb, TCP_FIN); - if (err == ERR_OK) { - pcb->state = LAST_ACK; - } - break; - default: - /* Has already been closed, do nothing. */ - err = ERR_OK; - pcb = NULL; - break; - } - - if (pcb != NULL && err == ERR_OK) { - err = tcp_output(pcb); - } - return err; -} - -/** - * Aborts a connection by sending a RST to the remote host and deletes - * the local protocol control block. This is done when a connection is - * killed because of shortage of memory. - * - */ -void -tcp_abort(struct tcp_pcb *pcb) -{ - u32_t seqno, ackno; - u16_t remote_port, local_port; - struct ip_addr remote_ip, local_ip; -#if LWIP_CALLBACK_API - void (* errf)(void *arg, err_t err); -#endif /* LWIP_CALLBACK_API */ - void *errf_arg; - - - /* Figure out on which TCP PCB list we are, and remove us. If we - are in an active state, call the receive function associated with - the PCB with a NULL argument, and send an RST to the remote end. */ - if (pcb->state == TIME_WAIT) { - tcp_pcb_remove(&tcp_tw_pcbs, pcb); - memp_free(MEMP_TCP_PCB, pcb); - } else { - seqno = pcb->snd_nxt; - ackno = pcb->rcv_nxt; - ip_addr_set(&local_ip, &(pcb->local_ip)); - ip_addr_set(&remote_ip, &(pcb->remote_ip)); - local_port = pcb->local_port; - remote_port = pcb->remote_port; -#if LWIP_CALLBACK_API - errf = pcb->errf; -#endif /* LWIP_CALLBACK_API */ - errf_arg = pcb->callback_arg; - tcp_pcb_remove(&tcp_active_pcbs, pcb); - if (pcb->unacked != NULL) { - tcp_segs_free(pcb->unacked); - } - if (pcb->unsent != NULL) { - tcp_segs_free(pcb->unsent); - } -#if TCP_QUEUE_OOSEQ - if (pcb->ooseq != NULL) { - tcp_segs_free(pcb->ooseq); - } -#endif /* TCP_QUEUE_OOSEQ */ - memp_free(MEMP_TCP_PCB, pcb); - TCP_EVENT_ERR(errf, errf_arg, ERR_ABRT); - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abort: sending RST\n")); - tcp_rst(seqno, ackno, &local_ip, &remote_ip, local_port, remote_port); - } -} - -/** - * Binds the connection to a local portnumber and IP address. If the - * IP address is not given (i.e., ipaddr == NULL), the IP address of - * the outgoing network interface is used instead. - * - */ - -err_t -tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) -{ - struct tcp_pcb *cpcb; - - if (port == 0) { - port = tcp_new_port(); - } - /* Check if the address already is in use. */ - for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; - cpcb != NULL; cpcb = cpcb->next) { - if (cpcb->local_port == port) { - if (ip_addr_isany(&(cpcb->local_ip)) || - ip_addr_isany(ipaddr) || - ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { - return ERR_USE; - } - } - } - for(cpcb = tcp_active_pcbs; - cpcb != NULL; cpcb = cpcb->next) { - if (cpcb->local_port == port) { - if (ip_addr_isany(&(cpcb->local_ip)) || - ip_addr_isany(ipaddr) || - ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { - return ERR_USE; - } - } - } - - if (!ip_addr_isany(ipaddr)) { - pcb->local_ip = *ipaddr; - } - pcb->local_port = port; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port)); - return ERR_OK; -} -#if LWIP_CALLBACK_API -static err_t -tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err) -{ - (void)arg; - (void)pcb; - (void)err; - - return ERR_ABRT; -} -#endif /* LWIP_CALLBACK_API */ - -/** - * Set the state of the connection to be LISTEN, which means that it - * is able to accept incoming connections. The protocol control block - * is reallocated in order to consume less memory. Setting the - * connection to LISTEN is an irreversible process. - * - */ -struct tcp_pcb * -tcp_listen(struct tcp_pcb *pcb) -{ - struct tcp_pcb_listen *lpcb; - - /* already listening? */ - if (pcb->state == LISTEN) { - return pcb; - } - lpcb = memp_malloc(MEMP_TCP_PCB_LISTEN); - if (lpcb == NULL) { - return NULL; - } - lpcb->callback_arg = pcb->callback_arg; - lpcb->local_port = pcb->local_port; - lpcb->state = LISTEN; - lpcb->so_options = pcb->so_options; - lpcb->so_options |= SOF_ACCEPTCONN; - lpcb->ttl = pcb->ttl; - lpcb->tos = pcb->tos; - ip_addr_set(&lpcb->local_ip, &pcb->local_ip); - memp_free(MEMP_TCP_PCB, pcb); -#if LWIP_CALLBACK_API - lpcb->accept = tcp_accept_null; -#endif /* LWIP_CALLBACK_API */ - TCP_REG(&tcp_listen_pcbs.listen_pcbs, lpcb); - return (struct tcp_pcb *)lpcb; -} - -/** - * This function should be called by the application when it has - * processed the data. The purpose is to advertise a larger window - * when the data has been processed. - * - */ -void -tcp_recved(struct tcp_pcb *pcb, u16_t len) -{ - if ((u32_t)pcb->rcv_wnd + len > TCP_WND) { - pcb->rcv_wnd = TCP_WND; - } else { - pcb->rcv_wnd += len; - } - if (!(pcb->flags & TF_ACK_DELAY) && - !(pcb->flags & TF_ACK_NOW)) { - /* - * We send an ACK here (if one is not already pending, hence - * the above tests) as tcp_recved() implies that the application - * has processed some data, and so we can open the receiver's - * window to allow more to be transmitted. This could result in - * two ACKs being sent for each received packet in some limited cases - * (where the application is only receiving data, and is slow to - * process it) but it is necessary to guarantee that the sender can - * continue to transmit. - */ - tcp_ack(pcb); - } - else if (pcb->flags & TF_ACK_DELAY && pcb->rcv_wnd >= TCP_WND/2) { - /* If we can send a window update such that there is a full - * segment available in the window, do so now. This is sort of - * nagle-like in its goals, and tries to hit a compromise between - * sending acks each time the window is updated, and only sending - * window updates when a timer expires. The "threshold" used - * above (currently TCP_WND/2) can be tuned to be more or less - * aggressive */ - tcp_ack_now(pcb); - } - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %"U16_F" bytes, wnd %"U16_F" (%"U16_F").\n", - len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd)); -} - -/** - * A nastly hack featuring 'goto' statements that allocates a - * new TCP local port. - */ -static u16_t -tcp_new_port(void) -{ - struct tcp_pcb *pcb; -#ifndef TCP_LOCAL_PORT_RANGE_START -#define TCP_LOCAL_PORT_RANGE_START 4096 -#define TCP_LOCAL_PORT_RANGE_END 0x7fff -#endif - static u16_t port = TCP_LOCAL_PORT_RANGE_START; - - again: - if (++port > TCP_LOCAL_PORT_RANGE_END) { - port = TCP_LOCAL_PORT_RANGE_START; - } - - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->local_port == port) { - goto again; - } - } - for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->local_port == port) { - goto again; - } - } - for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->local_port == port) { - goto again; - } - } - return port; -} - -/** - * Connects to another host. The function given as the "connected" - * argument will be called when the connection has been established. - * - */ -err_t -tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port, - err_t (* connected)(void *arg, struct tcp_pcb *tpcb, err_t err)) -{ - u32_t optdata; - err_t ret; - u32_t iss; - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port)); - if (ipaddr != NULL) { - pcb->remote_ip = *ipaddr; - } else { - return ERR_VAL; - } - pcb->remote_port = port; - if (pcb->local_port == 0) { - pcb->local_port = tcp_new_port(); - } - iss = tcp_next_iss(); - pcb->rcv_nxt = 0; - pcb->snd_nxt = iss; - pcb->lastack = iss - 1; - pcb->snd_lbb = iss - 1; - pcb->rcv_wnd = TCP_WND; - pcb->snd_wnd = TCP_WND; - pcb->mss = TCP_MSS; - pcb->cwnd = 1; - pcb->ssthresh = pcb->mss * 10; - pcb->state = SYN_SENT; -#if LWIP_CALLBACK_API - pcb->connected = connected; -#endif /* LWIP_CALLBACK_API */ - TCP_REG(&tcp_active_pcbs, pcb); - - /* Build an MSS option */ - optdata = htonl(((u32_t)2 << 24) | - ((u32_t)4 << 16) | - (((u32_t)pcb->mss / 256) << 8) | - (pcb->mss & 255)); - - ret = tcp_enqueue(pcb, NULL, 0, TCP_SYN, 0, (u8_t *)&optdata, 4); - if (ret == ERR_OK) { - tcp_output(pcb); - } - return ret; -} - -/** - * Called every 500 ms and implements the retransmission timer and the timer that - * removes PCBs that have been in TIME-WAIT for enough time. It also increments - * various timers such as the inactivity timer in each PCB. - */ -void -tcp_slowtmr(void) -{ - struct tcp_pcb *pcb, *pcb2, *prev; - u32_t eff_wnd; - u8_t pcb_remove; /* flag if a PCB should be removed */ - err_t err; - - err = ERR_OK; - - ++tcp_ticks; - - /* Steps through all of the active PCBs. */ - prev = NULL; - pcb = tcp_active_pcbs; - if (pcb == NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n")); - } - while (pcb != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n")); - LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED); - LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN); - LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT); - - pcb_remove = 0; - - if (pcb->state == SYN_SENT && pcb->nrtx == TCP_SYNMAXRTX) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n")); - } - else if (pcb->nrtx == TCP_MAXRTX) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n")); - } else { - ++pcb->rtime; - if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) { - - /* Time for a retransmission. */ - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %"U16_F" pcb->rto %"U16_F"\n", - pcb->rtime, pcb->rto)); - - /* Double retransmission time-out unless we are trying to - * connect to somebody (i.e., we are in SYN_SENT). */ - if (pcb->state != SYN_SENT) { - pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx]; - } - /* Reduce congestion window and ssthresh. */ - eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd); - pcb->ssthresh = eff_wnd >> 1; - if (pcb->ssthresh < pcb->mss) { - pcb->ssthresh = pcb->mss * 2; - } - pcb->cwnd = pcb->mss; - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"U16_F" ssthresh %"U16_F"\n", - pcb->cwnd, pcb->ssthresh)); - - /* The following needs to be called AFTER cwnd is set to one mss - STJ */ - tcp_rexmit_rto(pcb); - } - } - /* Check if this PCB has stayed too long in FIN-WAIT-2 */ - if (pcb->state == FIN_WAIT_2) { - if ((u32_t)(tcp_ticks - pcb->tmr) > - TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n")); - } - } - - /* Check if KEEPALIVE should be sent */ - if((pcb->so_options & SOF_KEEPALIVE) && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) { - if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + TCP_MAXIDLE) / TCP_SLOW_INTERVAL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %"U16_F".%"U16_F".%"U16_F".%"U16_F".\n", - ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), - ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip))); - - tcp_abort(pcb); - } - else if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + pcb->keep_cnt * TCP_KEEPINTVL) / TCP_SLOW_INTERVAL) { - tcp_keepalive(pcb); - pcb->keep_cnt++; - } - } - - /* If this PCB has queued out of sequence data, but has been - inactive for too long, will drop the data (it will eventually - be retransmitted). */ -#if TCP_QUEUE_OOSEQ - if (pcb->ooseq != NULL && - (u32_t)tcp_ticks - pcb->tmr >= - pcb->rto * TCP_OOSEQ_TIMEOUT) { - tcp_segs_free(pcb->ooseq); - pcb->ooseq = NULL; - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n")); - } -#endif /* TCP_QUEUE_OOSEQ */ - - /* Check if this PCB has stayed too long in SYN-RCVD */ - if (pcb->state == SYN_RCVD) { - if ((u32_t)(tcp_ticks - pcb->tmr) > - TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n")); - } - } - - /* Check if this PCB has stayed too long in LAST-ACK */ - if (pcb->state == LAST_ACK) { - if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n")); - } - } - - /* If the PCB should be removed, do it. */ - if (pcb_remove) { - tcp_pcb_purge(pcb); - /* Remove PCB from tcp_active_pcbs list. */ - if (prev != NULL) { - LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs); - prev->next = pcb->next; - } else { - /* This PCB was the first. */ - LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb); - tcp_active_pcbs = pcb->next; - } - - TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_ABRT); - - pcb2 = pcb->next; - memp_free(MEMP_TCP_PCB, pcb); - pcb = pcb2; - } else { - - /* We check if we should poll the connection. */ - ++pcb->polltmr; - if (pcb->polltmr >= pcb->pollinterval) { - pcb->polltmr = 0; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n")); - TCP_EVENT_POLL(pcb, err); - if (err == ERR_OK) { - tcp_output(pcb); - } - } - - prev = pcb; - pcb = pcb->next; - } - } - - - /* Steps through all of the TIME-WAIT PCBs. */ - prev = NULL; - pcb = tcp_tw_pcbs; - while (pcb != NULL) { - LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); - pcb_remove = 0; - - /* Check if this PCB has stayed long enough in TIME-WAIT */ - if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { - ++pcb_remove; - } - - - - /* If the PCB should be removed, do it. */ - if (pcb_remove) { - tcp_pcb_purge(pcb); - /* Remove PCB from tcp_tw_pcbs list. */ - if (prev != NULL) { - LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs); - prev->next = pcb->next; - } else { - /* This PCB was the first. */ - LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb); - tcp_tw_pcbs = pcb->next; - } - pcb2 = pcb->next; - memp_free(MEMP_TCP_PCB, pcb); - pcb = pcb2; - } else { - prev = pcb; - pcb = pcb->next; - } - } -} - -/** - * Is called every TCP_FAST_INTERVAL (250 ms) and sends delayed ACKs. - */ -void -tcp_fasttmr(void) -{ - struct tcp_pcb *pcb; - - /* send delayed ACKs */ - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->flags & TF_ACK_DELAY) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n")); - tcp_ack_now(pcb); - pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); - } - } -} - -/** - * Deallocates a list of TCP segments (tcp_seg structures). - * - */ -u8_t -tcp_segs_free(struct tcp_seg *seg) -{ - u8_t count = 0; - struct tcp_seg *next; - while (seg != NULL) { - next = seg->next; - count += tcp_seg_free(seg); - seg = next; - } - return count; -} - -/** - * Frees a TCP segment. - * - */ -u8_t -tcp_seg_free(struct tcp_seg *seg) -{ - u8_t count = 0; - - if (seg != NULL) { - if (seg->p != NULL) { - count = pbuf_free(seg->p); -#if TCP_DEBUG - seg->p = NULL; -#endif /* TCP_DEBUG */ - } - memp_free(MEMP_TCP_SEG, seg); - } - return count; -} - -/** - * Sets the priority of a connection. - * - */ -void -tcp_setprio(struct tcp_pcb *pcb, u8_t prio) -{ - pcb->prio = prio; -} -#if TCP_QUEUE_OOSEQ - -/** - * Returns a copy of the given TCP segment. - * - */ -struct tcp_seg * -tcp_seg_copy(struct tcp_seg *seg) -{ - struct tcp_seg *cseg; - - cseg = memp_malloc(MEMP_TCP_SEG); - if (cseg == NULL) { - return NULL; - } - memcpy((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); - pbuf_ref(cseg->p); - return cseg; -} -#endif - -#if LWIP_CALLBACK_API -static err_t -tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) -{ - arg = arg; - if (p != NULL) { - pbuf_free(p); - } else if (err == ERR_OK) { - return tcp_close(pcb); - } - return ERR_OK; -} -#endif /* LWIP_CALLBACK_API */ - -static void -tcp_kill_prio(u8_t prio) -{ - struct tcp_pcb *pcb, *inactive; - u32_t inactivity; - u8_t mprio; - - - mprio = TCP_PRIO_MAX; - - /* We kill the oldest active connection that has lower priority than - prio. */ - inactivity = 0; - inactive = NULL; - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->prio <= prio && - pcb->prio <= mprio && - (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { - inactivity = tcp_ticks - pcb->tmr; - inactive = pcb; - mprio = pcb->prio; - } - } - if (inactive != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n", - (void *)inactive, inactivity)); - tcp_abort(inactive); - } -} - - -static void -tcp_kill_timewait(void) -{ - struct tcp_pcb *pcb, *inactive; - u32_t inactivity; - - inactivity = 0; - inactive = NULL; - for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { - inactivity = tcp_ticks - pcb->tmr; - inactive = pcb; - } - } - if (inactive != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n", - (void *)inactive, inactivity)); - tcp_abort(inactive); - } -} - - - -struct tcp_pcb * -tcp_alloc(u8_t prio) -{ - struct tcp_pcb *pcb; - u32_t iss; - - pcb = memp_malloc(MEMP_TCP_PCB); - if (pcb == NULL) { - /* Try killing oldest connection in TIME-WAIT. */ - LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n")); - tcp_kill_timewait(); - pcb = memp_malloc(MEMP_TCP_PCB); - if (pcb == NULL) { - tcp_kill_prio(prio); - pcb = memp_malloc(MEMP_TCP_PCB); - } - } - if (pcb != NULL) { - memset(pcb, 0, sizeof(struct tcp_pcb)); - pcb->prio = TCP_PRIO_NORMAL; - pcb->snd_buf = TCP_SND_BUF; - pcb->snd_queuelen = 0; - pcb->rcv_wnd = TCP_WND; - pcb->tos = 0; - pcb->ttl = TCP_TTL; - pcb->mss = TCP_MSS; - pcb->rto = 3000 / TCP_SLOW_INTERVAL; - pcb->sa = 0; - pcb->sv = 3000 / TCP_SLOW_INTERVAL; - pcb->rtime = 0; - pcb->cwnd = 1; - iss = tcp_next_iss(); - pcb->snd_wl2 = iss; - pcb->snd_nxt = iss; - pcb->snd_max = iss; - pcb->lastack = iss; - pcb->snd_lbb = iss; - pcb->tmr = tcp_ticks; - - pcb->polltmr = 0; - -#if LWIP_CALLBACK_API - pcb->recv = tcp_recv_null; -#endif /* LWIP_CALLBACK_API */ - - /* Init KEEPALIVE timer */ - pcb->keepalive = TCP_KEEPDEFAULT; - pcb->keep_cnt = 0; - } - return pcb; -} - -/** - * Creates a new TCP protocol control block but doesn't place it on - * any of the TCP PCB lists. - * - * @internal: Maybe there should be a idle TCP PCB list where these - * PCBs are put on. We can then implement port reservation using - * tcp_bind(). Currently, we lack this (BSD socket type of) feature. - */ - -struct tcp_pcb * -tcp_new(void) -{ - return tcp_alloc(TCP_PRIO_NORMAL); -} - -/* - * tcp_arg(): - * - * Used to specify the argument that should be passed callback - * functions. - * - */ - -void -tcp_arg(struct tcp_pcb *pcb, void *arg) -{ - pcb->callback_arg = arg; -} -#if LWIP_CALLBACK_API - -/** - * Used to specify the function that should be called when a TCP - * connection receives data. - * - */ -void -tcp_recv(struct tcp_pcb *pcb, - err_t (* recv)(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err)) -{ - pcb->recv = recv; -} - -/** - * Used to specify the function that should be called when TCP data - * has been successfully delivered to the remote host. - * - */ - -void -tcp_sent(struct tcp_pcb *pcb, - err_t (* sent)(void *arg, struct tcp_pcb *tpcb, u16_t len)) -{ - pcb->sent = sent; -} - -/** - * Used to specify the function that should be called when a fatal error - * has occured on the connection. - * - */ -void -tcp_err(struct tcp_pcb *pcb, - void (* errf)(void *arg, err_t err)) -{ - pcb->errf = errf; -} - -/** - * Used for specifying the function that should be called when a - * LISTENing connection has been connected to another host. - * - */ -void -tcp_accept(struct tcp_pcb *pcb, - err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err)) -{ - ((struct tcp_pcb_listen *)pcb)->accept = accept; -} -#endif /* LWIP_CALLBACK_API */ - - -/** - * Used to specify the function that should be called periodically - * from TCP. The interval is specified in terms of the TCP coarse - * timer interval, which is called twice a second. - * - */ -void -tcp_poll(struct tcp_pcb *pcb, - err_t (* poll)(void *arg, struct tcp_pcb *tpcb), u8_t interval) -{ -#if LWIP_CALLBACK_API - pcb->poll = poll; -#endif /* LWIP_CALLBACK_API */ - pcb->pollinterval = interval; -} - -/** - * Purges a TCP PCB. Removes any buffered data and frees the buffer memory. - * - */ -void -tcp_pcb_purge(struct tcp_pcb *pcb) -{ - if (pcb->state != CLOSED && - pcb->state != TIME_WAIT && - pcb->state != LISTEN) { - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n")); - - if (pcb->unsent != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n")); - } - if (pcb->unacked != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n")); - } -#if TCP_QUEUE_OOSEQ /* LW */ - if (pcb->ooseq != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n")); - } - - tcp_segs_free(pcb->ooseq); - pcb->ooseq = NULL; -#endif /* TCP_QUEUE_OOSEQ */ - tcp_segs_free(pcb->unsent); - tcp_segs_free(pcb->unacked); - pcb->unacked = pcb->unsent = NULL; - } -} - -/** - * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first. - * - */ -void -tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb) -{ - TCP_RMV(pcblist, pcb); - - tcp_pcb_purge(pcb); - - /* if there is an outstanding delayed ACKs, send it */ - if (pcb->state != TIME_WAIT && - pcb->state != LISTEN && - pcb->flags & TF_ACK_DELAY) { - pcb->flags |= TF_ACK_NOW; - tcp_output(pcb); - } - pcb->state = CLOSED; - - LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane()); -} - -/** - * Calculates a new initial sequence number for new connections. - * - */ -u32_t -tcp_next_iss(void) -{ - static u32_t iss = 6510; - - iss += tcp_ticks; /* XXX */ - return iss; -} - -#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG -void -tcp_debug_print(struct tcp_hdr *tcphdr) -{ - LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n")); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", - ntohs(tcphdr->src), ntohs(tcphdr->dest))); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (seq no)\n", - ntohl(tcphdr->seqno))); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (ack no)\n", - ntohl(tcphdr->ackno))); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| %2"U16_F" | |%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"| %5"U16_F" | (hdrlen, flags (", - TCPH_HDRLEN(tcphdr), - TCPH_FLAGS(tcphdr) >> 5 & 1, - TCPH_FLAGS(tcphdr) >> 4 & 1, - TCPH_FLAGS(tcphdr) >> 3 & 1, - TCPH_FLAGS(tcphdr) >> 2 & 1, - TCPH_FLAGS(tcphdr) >> 1 & 1, - TCPH_FLAGS(tcphdr) & 1, - ntohs(tcphdr->wnd))); - tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); - LWIP_DEBUGF(TCP_DEBUG, ("), win)\n")); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| 0x%04"X16_F" | %5"U16_F" | (chksum, urgp)\n", - ntohs(tcphdr->chksum), ntohs(tcphdr->urgp))); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); -} - -void -tcp_debug_print_state(enum tcp_state s) -{ - LWIP_DEBUGF(TCP_DEBUG, ("State: ")); - switch (s) { - case CLOSED: - LWIP_DEBUGF(TCP_DEBUG, ("CLOSED\n")); - break; - case LISTEN: - LWIP_DEBUGF(TCP_DEBUG, ("LISTEN\n")); - break; - case SYN_SENT: - LWIP_DEBUGF(TCP_DEBUG, ("SYN_SENT\n")); - break; - case SYN_RCVD: - LWIP_DEBUGF(TCP_DEBUG, ("SYN_RCVD\n")); - break; - case ESTABLISHED: - LWIP_DEBUGF(TCP_DEBUG, ("ESTABLISHED\n")); - break; - case FIN_WAIT_1: - LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_1\n")); - break; - case FIN_WAIT_2: - LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_2\n")); - break; - case CLOSE_WAIT: - LWIP_DEBUGF(TCP_DEBUG, ("CLOSE_WAIT\n")); - break; - case CLOSING: - LWIP_DEBUGF(TCP_DEBUG, ("CLOSING\n")); - break; - case LAST_ACK: - LWIP_DEBUGF(TCP_DEBUG, ("LAST_ACK\n")); - break; - case TIME_WAIT: - LWIP_DEBUGF(TCP_DEBUG, ("TIME_WAIT\n")); - break; - } -} - -void -tcp_debug_print_flags(u8_t flags) -{ - if (flags & TCP_FIN) { - LWIP_DEBUGF(TCP_DEBUG, ("FIN ")); - } - if (flags & TCP_SYN) { - LWIP_DEBUGF(TCP_DEBUG, ("SYN ")); - } - if (flags & TCP_RST) { - LWIP_DEBUGF(TCP_DEBUG, ("RST ")); - } - if (flags & TCP_PSH) { - LWIP_DEBUGF(TCP_DEBUG, ("PSH ")); - } - if (flags & TCP_ACK) { - LWIP_DEBUGF(TCP_DEBUG, ("ACK ")); - } - if (flags & TCP_URG) { - LWIP_DEBUGF(TCP_DEBUG, ("URG ")); - } - if (flags & TCP_ECE) { - LWIP_DEBUGF(TCP_DEBUG, ("ECE ")); - } - if (flags & TCP_CWR) { - LWIP_DEBUGF(TCP_DEBUG, ("CWR ")); - } -} - -void -tcp_debug_print_pcbs(void) -{ - struct tcp_pcb *pcb; - LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n")); - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", - pcb->local_port, pcb->remote_port, - pcb->snd_nxt, pcb->rcv_nxt)); - tcp_debug_print_state(pcb->state); - } - LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n")); - for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", - pcb->local_port, pcb->remote_port, - pcb->snd_nxt, pcb->rcv_nxt)); - tcp_debug_print_state(pcb->state); - } - LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n")); - for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", - pcb->local_port, pcb->remote_port, - pcb->snd_nxt, pcb->rcv_nxt)); - tcp_debug_print_state(pcb->state); - } -} - -s16_t -tcp_pcbs_sane(void) -{ - struct tcp_pcb *pcb; - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED); - LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN); - LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); - } - for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); - } - return 1; -} -#endif /* TCP_DEBUG */ -#endif /* LWIP_TCP */ - - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/tcp_in.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/tcp_in.c deleted file mode 100644 index 212f9c4db..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/tcp_in.c +++ /dev/null @@ -1,1199 +0,0 @@ -/** - * @file - * - * Transmission Control Protocol, incoming traffic - * - * The input processing functions of TCP. - * - * These functions are generally called in the order (ip_input() ->) tcp_input() -> - * tcp_process() -> tcp_receive() (-> application). - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/def.h" -#include "lwip/opt.h" - -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/mem.h" -#include "lwip/memp.h" - -#include "lwip/inet.h" -#include "lwip/tcp.h" - -#include "lwip/stats.h" - -#include "arch/perf.h" -#if LWIP_TCP -/* These variables are global to all functions involved in the input - processing of TCP segments. They are set by the tcp_input() - function. */ -static struct tcp_seg inseg; -static struct tcp_hdr *tcphdr; -static struct ip_hdr *iphdr; -static u32_t seqno, ackno; -static u8_t flags; -static u16_t tcplen; - -static u8_t recv_flags; -static struct pbuf *recv_data; - -struct tcp_pcb *tcp_input_pcb; - -/* Forward declarations. */ -static err_t tcp_process(struct tcp_pcb *pcb); -static void tcp_receive(struct tcp_pcb *pcb); -static void tcp_parseopt(struct tcp_pcb *pcb); - -static err_t tcp_listen_input(struct tcp_pcb_listen *pcb); -static err_t tcp_timewait_input(struct tcp_pcb *pcb); - - -/* tcp_input: - * - * The initial input processing of TCP. It verifies the TCP header, demultiplexes - * the segment between the PCBs and passes it on to tcp_process(), which implements - * the TCP finite state machine. This function is called by the IP layer (in - * ip_input()). - */ - -void -tcp_input(struct pbuf *p, struct netif *inp) -{ - struct tcp_pcb *pcb, *prev; - struct tcp_pcb_listen *lpcb; - u8_t hdrlen; - err_t err; - - PERF_START; - - TCP_STATS_INC(tcp.recv); - - iphdr = p->payload; - tcphdr = (struct tcp_hdr *)((u8_t *)p->payload + IPH_HL(iphdr) * 4); - -#if TCP_INPUT_DEBUG - tcp_debug_print(tcphdr); -#endif - - /* remove header from payload */ - if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) { - /* drop short packets */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%"U16_F" bytes) discarded\n", p->tot_len)); - TCP_STATS_INC(tcp.lenerr); - TCP_STATS_INC(tcp.drop); - pbuf_free(p); - return; - } - - /* Don't even process incoming broadcasts/multicasts. */ - if (ip_addr_isbroadcast(&(iphdr->dest), inp) || - ip_addr_ismulticast(&(iphdr->dest))) { - pbuf_free(p); - return; - } - -#if CHECKSUM_CHECK_TCP - /* Verify TCP checksum. */ - if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), - (struct ip_addr *)&(iphdr->dest), - IP_PROTO_TCP, p->tot_len) != 0) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04"X16_F"\n", - inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), (struct ip_addr *)&(iphdr->dest), - IP_PROTO_TCP, p->tot_len))); -#if TCP_DEBUG - tcp_debug_print(tcphdr); -#endif /* TCP_DEBUG */ - TCP_STATS_INC(tcp.chkerr); - TCP_STATS_INC(tcp.drop); - - pbuf_free(p); - return; - } -#endif - - /* Move the payload pointer in the pbuf so that it points to the - TCP data instead of the TCP header. */ - hdrlen = TCPH_HDRLEN(tcphdr); - pbuf_header(p, -(hdrlen * 4)); - - /* Convert fields in TCP header to host byte order. */ - tcphdr->src = ntohs(tcphdr->src); - tcphdr->dest = ntohs(tcphdr->dest); - seqno = tcphdr->seqno = ntohl(tcphdr->seqno); - ackno = tcphdr->ackno = ntohl(tcphdr->ackno); - tcphdr->wnd = ntohs(tcphdr->wnd); - - flags = TCPH_FLAGS(tcphdr) & TCP_FLAGS; - tcplen = p->tot_len + ((flags & TCP_FIN || flags & TCP_SYN)? 1: 0); - - /* Demultiplex an incoming segment. First, we check if it is destined - for an active connection. */ - prev = NULL; - - - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED); - LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); - LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN); - if (pcb->remote_port == tcphdr->src && - pcb->local_port == tcphdr->dest && - ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) && - ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) { - - /* Move this PCB to the front of the list so that subsequent - lookups will be faster (we exploit locality in TCP segment - arrivals). */ - LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb); - if (prev != NULL) { - prev->next = pcb->next; - pcb->next = tcp_active_pcbs; - tcp_active_pcbs = pcb; - } - LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb); - break; - } - prev = pcb; - } - - if (pcb == NULL) { - /* If it did not go to an active connection, we check the connections - in the TIME-WAIT state. */ - - for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); - if (pcb->remote_port == tcphdr->src && - pcb->local_port == tcphdr->dest && - ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) && - ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) { - /* We don't really care enough to move this PCB to the front - of the list since we are not very likely to receive that - many segments for connections in TIME-WAIT. */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n")); - tcp_timewait_input(pcb); - pbuf_free(p); - return; - } - } - - /* Finally, if we still did not get a match, we check all PCBs that - are LISTENing for incoming connections. */ - prev = NULL; - for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { - if ((ip_addr_isany(&(lpcb->local_ip)) || - ip_addr_cmp(&(lpcb->local_ip), &(iphdr->dest))) && - lpcb->local_port == tcphdr->dest) { - /* Move this PCB to the front of the list so that subsequent - lookups will be faster (we exploit locality in TCP segment - arrivals). */ - if (prev != NULL) { - ((struct tcp_pcb_listen *)prev)->next = lpcb->next; - /* our successor is the remainder of the listening list */ - lpcb->next = tcp_listen_pcbs.listen_pcbs; - /* put this listening pcb at the head of the listening list */ - tcp_listen_pcbs.listen_pcbs = lpcb; - } - - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n")); - tcp_listen_input(lpcb); - pbuf_free(p); - return; - } - prev = (struct tcp_pcb *)lpcb; - } - } - -#if TCP_INPUT_DEBUG - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags ")); - tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n")); -#endif /* TCP_INPUT_DEBUG */ - - - if (pcb != NULL) { - /* The incoming segment belongs to a connection. */ -#if TCP_INPUT_DEBUG -#if TCP_DEBUG - tcp_debug_print_state(pcb->state); -#endif /* TCP_DEBUG */ -#endif /* TCP_INPUT_DEBUG */ - - /* Set up a tcp_seg structure. */ - inseg.next = NULL; - inseg.len = p->tot_len; - inseg.dataptr = p->payload; - inseg.p = p; - inseg.tcphdr = tcphdr; - - recv_data = NULL; - recv_flags = 0; - - tcp_input_pcb = pcb; - err = tcp_process(pcb); - tcp_input_pcb = NULL; - /* A return value of ERR_ABRT means that tcp_abort() was called - and that the pcb has been freed. If so, we don't do anything. */ - if (err != ERR_ABRT) { - if (recv_flags & TF_RESET) { - /* TF_RESET means that the connection was reset by the other - end. We then call the error callback to inform the - application that the connection is dead before we - deallocate the PCB. */ - TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_RST); - tcp_pcb_remove(&tcp_active_pcbs, pcb); - memp_free(MEMP_TCP_PCB, pcb); - } else if (recv_flags & TF_CLOSED) { - /* The connection has been closed and we will deallocate the - PCB. */ - tcp_pcb_remove(&tcp_active_pcbs, pcb); - memp_free(MEMP_TCP_PCB, pcb); - } else { - err = ERR_OK; - /* If the application has registered a "sent" function to be - called when new send buffer space is available, we call it - now. */ - if (pcb->acked > 0) { - TCP_EVENT_SENT(pcb, pcb->acked, err); - } - - if (recv_data != NULL) { - /* Notify application that data has been received. */ - TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err); - } - - /* If a FIN segment was received, we call the callback - function with a NULL buffer to indicate EOF. */ - if (recv_flags & TF_GOT_FIN) { - TCP_EVENT_RECV(pcb, NULL, ERR_OK, err); - } - /* If there were no errors, we try to send something out. */ - if (err == ERR_OK) { - tcp_output(pcb); - } - } - } - - - /* We deallocate the incoming pbuf. If it was buffered by the - application, the application should have called pbuf_ref() to - increase the reference counter in the pbuf. If so, the buffer - isn't actually deallocated by the call to pbuf_free(), only the - reference count is decreased. */ - if (inseg.p != NULL) pbuf_free(inseg.p); -#if TCP_INPUT_DEBUG -#if TCP_DEBUG - tcp_debug_print_state(pcb->state); -#endif /* TCP_DEBUG */ -#endif /* TCP_INPUT_DEBUG */ - - } else { - - /* If no matching PCB was found, send a TCP RST (reset) to the - sender. */ - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n")); - if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) { - TCP_STATS_INC(tcp.proterr); - TCP_STATS_INC(tcp.drop); - tcp_rst(ackno, seqno + tcplen, - &(iphdr->dest), &(iphdr->src), - tcphdr->dest, tcphdr->src); - } - pbuf_free(p); - } - - LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane()); - PERF_STOP("tcp_input"); -} - -/* tcp_listen_input(): - * - * Called by tcp_input() when a segment arrives for a listening - * connection. - */ - -static err_t -tcp_listen_input(struct tcp_pcb_listen *pcb) -{ - struct tcp_pcb *npcb; - u32_t optdata; - - /* In the LISTEN state, we check for incoming SYN segments, - creates a new PCB, and responds with a SYN|ACK. */ - if (flags & TCP_ACK) { - /* For incoming segments with the ACK flag set, respond with a - RST. */ - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n")); - tcp_rst(ackno + 1, seqno + tcplen, - &(iphdr->dest), &(iphdr->src), - tcphdr->dest, tcphdr->src); - } else if (flags & TCP_SYN) { - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %"U16_F" -> %"U16_F".\n", tcphdr->src, tcphdr->dest)); - npcb = tcp_alloc(pcb->prio); - /* If a new PCB could not be created (probably due to lack of memory), - we don't do anything, but rely on the sender will retransmit the - SYN at a time when we have more memory available. */ - if (npcb == NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n")); - TCP_STATS_INC(tcp.memerr); - return ERR_MEM; - } - /* Set up the new PCB. */ - ip_addr_set(&(npcb->local_ip), &(iphdr->dest)); - npcb->local_port = pcb->local_port; - ip_addr_set(&(npcb->remote_ip), &(iphdr->src)); - npcb->remote_port = tcphdr->src; - npcb->state = SYN_RCVD; - npcb->rcv_nxt = seqno + 1; - npcb->snd_wnd = tcphdr->wnd; - npcb->ssthresh = npcb->snd_wnd; - npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */ - npcb->callback_arg = pcb->callback_arg; -#if LWIP_CALLBACK_API - npcb->accept = pcb->accept; -#endif /* LWIP_CALLBACK_API */ - /* inherit socket options */ - npcb->so_options = pcb->so_options & (SOF_DEBUG|SOF_DONTROUTE|SOF_KEEPALIVE|SOF_OOBINLINE|SOF_LINGER); - /* Register the new PCB so that we can begin receiving segments - for it. */ - TCP_REG(&tcp_active_pcbs, npcb); - - /* Parse any options in the SYN. */ - tcp_parseopt(npcb); - - /* Build an MSS option. */ - optdata = htonl(((u32_t)2 << 24) | - ((u32_t)4 << 16) | - (((u32_t)npcb->mss / 256) << 8) | - (npcb->mss & 255)); - /* Send a SYN|ACK together with the MSS option. */ - tcp_enqueue(npcb, NULL, 0, TCP_SYN | TCP_ACK, 0, (u8_t *)&optdata, 4); - return tcp_output(npcb); - } - return ERR_OK; -} - -/* tcp_timewait_input(): - * - * Called by tcp_input() when a segment arrives for a connection in - * TIME_WAIT. - */ - -static err_t -tcp_timewait_input(struct tcp_pcb *pcb) -{ - if (TCP_SEQ_GT(seqno + tcplen, pcb->rcv_nxt)) { - pcb->rcv_nxt = seqno + tcplen; - } - if (tcplen > 0) { - tcp_ack_now(pcb); - } - return tcp_output(pcb); -} - -/* tcp_process - * - * Implements the TCP state machine. Called by tcp_input. In some - * states tcp_receive() is called to receive data. The tcp_seg - * argument will be freed by the caller (tcp_input()) unless the - * recv_data pointer in the pcb is set. - */ - -static err_t -tcp_process(struct tcp_pcb *pcb) -{ - struct tcp_seg *rseg; - u8_t acceptable = 0; - err_t err; - - - err = ERR_OK; - - /* Process incoming RST segments. */ - if (flags & TCP_RST) { - /* First, determine if the reset is acceptable. */ - if (pcb->state == SYN_SENT) { - if (ackno == pcb->snd_nxt) { - acceptable = 1; - } - } else { - /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) && - TCP_SEQ_LEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) { - */ - if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt+pcb->rcv_wnd)) { - acceptable = 1; - } - } - - if (acceptable) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n")); - LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED); - recv_flags = TF_RESET; - pcb->flags &= ~TF_ACK_DELAY; - return ERR_RST; - } else { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", - seqno, pcb->rcv_nxt)); - LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", - seqno, pcb->rcv_nxt)); - return ERR_OK; - } - } - - /* Update the PCB (in)activity timer. */ - pcb->tmr = tcp_ticks; - pcb->keep_cnt = 0; - - /* Do different things depending on the TCP state. */ - switch (pcb->state) { - case SYN_SENT: - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno, - pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno))); - /* received SYN ACK with expected sequence number? */ - if ((flags & TCP_ACK) && (flags & TCP_SYN) - && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) { - pcb->snd_buf++; - pcb->rcv_nxt = seqno + 1; - pcb->lastack = ackno; - pcb->snd_wnd = tcphdr->wnd; - pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */ - pcb->state = ESTABLISHED; - pcb->cwnd = pcb->mss; - --pcb->snd_queuelen; - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"U16_F"\n", (u16_t)pcb->snd_queuelen)); - rseg = pcb->unacked; - pcb->unacked = rseg->next; - tcp_seg_free(rseg); - - /* Parse any options in the SYNACK. */ - tcp_parseopt(pcb); - - /* Call the user specified function to call when sucessfully - * connected. */ - TCP_EVENT_CONNECTED(pcb, ERR_OK, err); - tcp_ack(pcb); - } - /* received ACK? possibly a half-open connection */ - else if (flags & TCP_ACK) { - /* send a RST to bring the other side in a non-synchronized state. */ - tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src), - tcphdr->dest, tcphdr->src); - } - break; - case SYN_RCVD: - if (flags & TCP_ACK && - !(flags & TCP_RST)) { - /* expected ACK number? */ - if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)) { - pcb->state = ESTABLISHED; - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); -#if LWIP_CALLBACK_API - LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL); -#endif - /* Call the accept function. */ - TCP_EVENT_ACCEPT(pcb, ERR_OK, err); - if (err != ERR_OK) { - /* If the accept function returns with an error, we abort - * the connection. */ - tcp_abort(pcb); - return ERR_ABRT; - } - /* If there was any data contained within this ACK, - * we'd better pass it on to the application as well. */ - tcp_receive(pcb); - pcb->cwnd = pcb->mss; - } - /* incorrect ACK number */ - else { - /* send RST */ - tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src), - tcphdr->dest, tcphdr->src); - } - } - break; - case CLOSE_WAIT: - /* FALLTHROUGH */ - case ESTABLISHED: - tcp_receive(pcb); - if (flags & TCP_FIN) { - tcp_ack_now(pcb); - pcb->state = CLOSE_WAIT; - } - break; - case FIN_WAIT_1: - tcp_receive(pcb); - if (flags & TCP_FIN) { - if (flags & TCP_ACK && ackno == pcb->snd_nxt) { - LWIP_DEBUGF(TCP_DEBUG, - ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); - tcp_ack_now(pcb); - tcp_pcb_purge(pcb); - TCP_RMV(&tcp_active_pcbs, pcb); - pcb->state = TIME_WAIT; - TCP_REG(&tcp_tw_pcbs, pcb); - } else { - tcp_ack_now(pcb); - pcb->state = CLOSING; - } - } else if (flags & TCP_ACK && ackno == pcb->snd_nxt) { - pcb->state = FIN_WAIT_2; - } - break; - case FIN_WAIT_2: - tcp_receive(pcb); - if (flags & TCP_FIN) { - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); - tcp_ack_now(pcb); - tcp_pcb_purge(pcb); - TCP_RMV(&tcp_active_pcbs, pcb); - pcb->state = TIME_WAIT; - TCP_REG(&tcp_tw_pcbs, pcb); - } - break; - case CLOSING: - tcp_receive(pcb); - if (flags & TCP_ACK && ackno == pcb->snd_nxt) { - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); - tcp_ack_now(pcb); - tcp_pcb_purge(pcb); - TCP_RMV(&tcp_active_pcbs, pcb); - pcb->state = TIME_WAIT; - TCP_REG(&tcp_tw_pcbs, pcb); - } - break; - case LAST_ACK: - tcp_receive(pcb); - if (flags & TCP_ACK && ackno == pcb->snd_nxt) { - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); - pcb->state = CLOSED; - recv_flags = TF_CLOSED; - } - break; - default: - break; - } - return ERR_OK; -} - -/* tcp_receive: - * - * Called by tcp_process. Checks if the given segment is an ACK for outstanding - * data, and if so frees the memory of the buffered data. Next, is places the - * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment - * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until - * i it has been removed from the buffer. - * - * If the incoming segment constitutes an ACK for a segment that was used for RTT - * estimation, the RTT is estimated here as well. - */ - -static void -tcp_receive(struct tcp_pcb *pcb) -{ - struct tcp_seg *next; -#if TCP_QUEUE_OOSEQ - struct tcp_seg *prev, *cseg; -#endif - struct pbuf *p; - s32_t off; - s16_t m; - u32_t right_wnd_edge; - u16_t new_tot_len; - - - if (flags & TCP_ACK) { - right_wnd_edge = pcb->snd_wnd + pcb->snd_wl1; - - /* Update window. */ - if (TCP_SEQ_LT(pcb->snd_wl1, seqno) || - (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || - (pcb->snd_wl2 == ackno && tcphdr->wnd > pcb->snd_wnd)) { - pcb->snd_wnd = tcphdr->wnd; - pcb->snd_wl1 = seqno; - pcb->snd_wl2 = ackno; - LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %"U32_F"\n", pcb->snd_wnd)); -#if TCP_WND_DEBUG - } else { - if (pcb->snd_wnd != tcphdr->wnd) { - LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: no window update lastack %"U32_F" snd_max %"U32_F" ackno %"U32_F" wl1 %"U32_F" seqno %"U32_F" wl2 %"U32_F"\n", - pcb->lastack, pcb->snd_max, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2)); - } -#endif /* TCP_WND_DEBUG */ - } - - - if (pcb->lastack == ackno) { - pcb->acked = 0; - - if (pcb->snd_wl1 + pcb->snd_wnd == right_wnd_edge){ - ++pcb->dupacks; - if (pcb->dupacks >= 3 && pcb->unacked != NULL) { - if (!(pcb->flags & TF_INFR)) { - /* This is fast retransmit. Retransmit the first unacked segment. */ - LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupacks %"U16_F" (%"U32_F"), fast retransmit %"U32_F"\n", - (u16_t)pcb->dupacks, pcb->lastack, - ntohl(pcb->unacked->tcphdr->seqno))); - tcp_rexmit(pcb); - /* Set ssthresh to max (FlightSize / 2, 2*SMSS) */ - /*pcb->ssthresh = LWIP_MAX((pcb->snd_max - - pcb->lastack) / 2, - 2 * pcb->mss);*/ - /* Set ssthresh to half of the minimum of the currenct cwnd and the advertised window */ - if(pcb->cwnd > pcb->snd_wnd) - pcb->ssthresh = pcb->snd_wnd / 2; - else - pcb->ssthresh = pcb->cwnd / 2; - - pcb->cwnd = pcb->ssthresh + 3 * pcb->mss; - pcb->flags |= TF_INFR; - } else { - /* Inflate the congestion window, but not if it means that - the value overflows. */ - if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { - pcb->cwnd += pcb->mss; - } - } - } - } else { - LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupack averted %"U32_F" %"U32_F"\n", - pcb->snd_wl1 + pcb->snd_wnd, right_wnd_edge)); - } - } else - /*if (TCP_SEQ_LT(pcb->lastack, ackno) && - TCP_SEQ_LEQ(ackno, pcb->snd_max)) { */ - if(TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_max)){ - /* We come here when the ACK acknowledges new data. */ - - /* Reset the "IN Fast Retransmit" flag, since we are no longer - in fast retransmit. Also reset the congestion window to the - slow start threshold. */ - if (pcb->flags & TF_INFR) { - pcb->flags &= ~TF_INFR; - pcb->cwnd = pcb->ssthresh; - } - - /* Reset the number of retransmissions. */ - pcb->nrtx = 0; - - /* Reset the retransmission time-out. */ - pcb->rto = (pcb->sa >> 3) + pcb->sv; - - /* Update the send buffer space. */ - pcb->acked = ackno - pcb->lastack; - - pcb->snd_buf += pcb->acked; - - /* Reset the fast retransmit variables. */ - pcb->dupacks = 0; - pcb->lastack = ackno; - - /* Update the congestion control variables (cwnd and - ssthresh). */ - if (pcb->state >= ESTABLISHED) { - if (pcb->cwnd < pcb->ssthresh) { - if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { - pcb->cwnd += pcb->mss; - } - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"U16_F"\n", pcb->cwnd)); - } else { - u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd); - if (new_cwnd > pcb->cwnd) { - pcb->cwnd = new_cwnd; - } - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %"U16_F"\n", pcb->cwnd)); - } - } - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %"U32_F", unacked->seqno %"U32_F":%"U32_F"\n", - ackno, - pcb->unacked != NULL? - ntohl(pcb->unacked->tcphdr->seqno): 0, - pcb->unacked != NULL? - ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0)); - - /* Remove segment from the unacknowledged list if the incoming - ACK acknowlegdes them. */ - while (pcb->unacked != NULL && - TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) + - TCP_TCPLEN(pcb->unacked), ackno)) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unacked\n", - ntohl(pcb->unacked->tcphdr->seqno), - ntohl(pcb->unacked->tcphdr->seqno) + - TCP_TCPLEN(pcb->unacked))); - - next = pcb->unacked; - pcb->unacked = pcb->unacked->next; - - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen)); - pcb->snd_queuelen -= pbuf_clen(next->p); - tcp_seg_free(next); - - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unacked)\n", (u16_t)pcb->snd_queuelen)); - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL || - pcb->unsent != NULL); - } - } - pcb->polltmr = 0; - } - - /* We go through the ->unsent list to see if any of the segments - on the list are acknowledged by the ACK. This may seem - strange since an "unsent" segment shouldn't be acked. The - rationale is that lwIP puts all outstanding segments on the - ->unsent list after a retransmission, so these segments may - in fact have been sent once. */ - while (pcb->unsent != NULL && - /*TCP_SEQ_LEQ(ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), ackno) && - TCP_SEQ_LEQ(ackno, pcb->snd_max)*/ - TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), pcb->snd_max) - ) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unsent\n", - ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) + - TCP_TCPLEN(pcb->unsent))); - - next = pcb->unsent; - pcb->unsent = pcb->unsent->next; - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen)); - pcb->snd_queuelen -= pbuf_clen(next->p); - tcp_seg_free(next); - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unsent)\n", (u16_t)pcb->snd_queuelen)); - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_receive: valid queue length", - pcb->unacked != NULL || pcb->unsent != NULL); - } - - if (pcb->unsent != NULL) { - pcb->snd_nxt = htonl(pcb->unsent->tcphdr->seqno); - } - } - /* End of ACK for new data processing. */ - - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %"U32_F" rtseq %"U32_F" ackno %"U32_F"\n", - pcb->rttest, pcb->rtseq, ackno)); - - /* RTT estimation calculations. This is done by checking if the - incoming segment acknowledges the segment we use to take a - round-trip time measurement. */ - if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) { - m = tcp_ticks - pcb->rttest; - - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n", - m, m * TCP_SLOW_INTERVAL)); - - /* This is taken directly from VJs original code in his paper */ - m = m - (pcb->sa >> 3); - pcb->sa += m; - if (m < 0) { - m = -m; - } - m = m - (pcb->sv >> 2); - pcb->sv += m; - pcb->rto = (pcb->sa >> 3) + pcb->sv; - - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" miliseconds)\n", - pcb->rto, pcb->rto * TCP_SLOW_INTERVAL)); - - pcb->rttest = 0; - } - } - - /* If the incoming segment contains data, we must process it - further. */ - if (tcplen > 0) { - /* This code basically does three things: - - +) If the incoming segment contains data that is the next - in-sequence data, this data is passed to the application. This - might involve trimming the first edge of the data. The rcv_nxt - variable and the advertised window are adjusted. - - +) If the incoming segment has data that is above the next - sequence number expected (->rcv_nxt), the segment is placed on - the ->ooseq queue. This is done by finding the appropriate - place in the ->ooseq queue (which is ordered by sequence - number) and trim the segment in both ends if needed. An - immediate ACK is sent to indicate that we received an - out-of-sequence segment. - - +) Finally, we check if the first segment on the ->ooseq queue - now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If - rcv_nxt > ooseq->seqno, we must trim the first edge of the - segment on ->ooseq before we adjust rcv_nxt. The data in the - segments that are now on sequence are chained onto the - incoming segment so that we only need to call the application - once. - */ - - /* First, we check if we must trim the first edge. We have to do - this if the sequence number of the incoming segment is less - than rcv_nxt, and the sequence number plus the length of the - segment is larger than rcv_nxt. */ - /* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){ - if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/ - if(TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno+1, seqno+tcplen-1)){ - /* Trimming the first edge is done by pushing the payload - pointer in the pbuf downwards. This is somewhat tricky since - we do not want to discard the full contents of the pbuf up to - the new starting point of the data since we have to keep the - TCP header which is present in the first pbuf in the chain. - - What is done is really quite a nasty hack: the first pbuf in - the pbuf chain is pointed to by inseg.p. Since we need to be - able to deallocate the whole pbuf, we cannot change this - inseg.p pointer to point to any of the later pbufs in the - chain. Instead, we point the ->payload pointer in the first - pbuf to data in one of the later pbufs. We also set the - inseg.data pointer to point to the right place. This way, the - ->p pointer will still point to the first pbuf, but the - ->p->payload pointer will point to data in another pbuf. - - After we are done with adjusting the pbuf pointers we must - adjust the ->data pointer in the seg and the segment - length.*/ - - off = pcb->rcv_nxt - seqno; - p = inseg.p; - if (inseg.p->len < off) { - new_tot_len = inseg.p->tot_len - off; - while (p->len < off) { - off -= p->len; - /* KJM following line changed (with addition of new_tot_len var) - to fix bug #9076 - inseg.p->tot_len -= p->len; */ - p->tot_len = new_tot_len; - p->len = 0; - p = p->next; - } - pbuf_header(p, -off); - } else { - pbuf_header(inseg.p, -off); - } - /* KJM following line changed to use p->payload rather than inseg->p->payload - to fix bug #9076 */ - inseg.dataptr = p->payload; - inseg.len -= pcb->rcv_nxt - seqno; - inseg.tcphdr->seqno = seqno = pcb->rcv_nxt; - } - else{ - if(TCP_SEQ_LT(seqno, pcb->rcv_nxt)){ - /* the whole segment is < rcv_nxt */ - /* must be a duplicate of a packet that has already been correctly handled */ - - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno)); - tcp_ack_now(pcb); - } - } - - /* The sequence number must be within the window (above rcv_nxt - and below rcv_nxt + rcv_wnd) in order to be further - processed. */ - /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) && - TCP_SEQ_LT(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ - if(TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)){ - if (pcb->rcv_nxt == seqno) { - /* The incoming segment is the next in sequence. We check if - we have to trim the end of the segment and update rcv_nxt - and pass the data to the application. */ -#if TCP_QUEUE_OOSEQ - if (pcb->ooseq != NULL && - TCP_SEQ_LEQ(pcb->ooseq->tcphdr->seqno, seqno + inseg.len)) { - /* We have to trim the second edge of the incoming - segment. */ - inseg.len = pcb->ooseq->tcphdr->seqno - seqno; - pbuf_realloc(inseg.p, inseg.len); - } -#endif /* TCP_QUEUE_OOSEQ */ - - tcplen = TCP_TCPLEN(&inseg); - - /* First received FIN will be ACKed +1, on any successive (duplicate) - * FINs we are already in CLOSE_WAIT and have already done +1. - */ - if (pcb->state != CLOSE_WAIT) { - pcb->rcv_nxt += tcplen; - } - - /* Update the receiver's (our) window. */ - if (pcb->rcv_wnd < tcplen) { - pcb->rcv_wnd = 0; - } else { - pcb->rcv_wnd -= tcplen; - } - - /* If there is data in the segment, we make preparations to - pass this up to the application. The ->recv_data variable - is used for holding the pbuf that goes to the - application. The code for reassembling out-of-sequence data - chains its data on this pbuf as well. - - If the segment was a FIN, we set the TF_GOT_FIN flag that will - be used to indicate to the application that the remote side has - closed its end of the connection. */ - if (inseg.p->tot_len > 0) { - recv_data = inseg.p; - /* Since this pbuf now is the responsibility of the - application, we delete our reference to it so that we won't - (mistakingly) deallocate it. */ - inseg.p = NULL; - } - if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n")); - recv_flags = TF_GOT_FIN; - } - -#if TCP_QUEUE_OOSEQ - /* We now check if we have segments on the ->ooseq queue that - is now in sequence. */ - while (pcb->ooseq != NULL && - pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) { - - cseg = pcb->ooseq; - seqno = pcb->ooseq->tcphdr->seqno; - - pcb->rcv_nxt += TCP_TCPLEN(cseg); - if (pcb->rcv_wnd < TCP_TCPLEN(cseg)) { - pcb->rcv_wnd = 0; - } else { - pcb->rcv_wnd -= TCP_TCPLEN(cseg); - } - if (cseg->p->tot_len > 0) { - /* Chain this pbuf onto the pbuf that we will pass to - the application. */ - if (recv_data) { - pbuf_cat(recv_data, cseg->p); - } else { - recv_data = cseg->p; - } - cseg->p = NULL; - } - if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n")); - recv_flags = TF_GOT_FIN; - } - - - pcb->ooseq = cseg->next; - tcp_seg_free(cseg); - } -#endif /* TCP_QUEUE_OOSEQ */ - - - /* Acknowledge the segment(s). */ - tcp_ack(pcb); - - } else { - /* We get here if the incoming segment is out-of-sequence. */ - tcp_ack_now(pcb); -#if TCP_QUEUE_OOSEQ - /* We queue the segment on the ->ooseq queue. */ - if (pcb->ooseq == NULL) { - pcb->ooseq = tcp_seg_copy(&inseg); - } else { - /* If the queue is not empty, we walk through the queue and - try to find a place where the sequence number of the - incoming segment is between the sequence numbers of the - previous and the next segment on the ->ooseq queue. That is - the place where we put the incoming segment. If needed, we - trim the second edges of the previous and the incoming - segment so that it will fit into the sequence. - - If the incoming segment has the same sequence number as a - segment on the ->ooseq queue, we discard the segment that - contains less data. */ - - prev = NULL; - for(next = pcb->ooseq; next != NULL; next = next->next) { - if (seqno == next->tcphdr->seqno) { - /* The sequence number of the incoming segment is the - same as the sequence number of the segment on - ->ooseq. We check the lengths to see which one to - discard. */ - if (inseg.len > next->len) { - /* The incoming segment is larger than the old - segment. We replace the old segment with the new - one. */ - cseg = tcp_seg_copy(&inseg); - if (cseg != NULL) { - cseg->next = next->next; - if (prev != NULL) { - prev->next = cseg; - } else { - pcb->ooseq = cseg; - } - } - break; - } else { - /* Either the lenghts are the same or the incoming - segment was smaller than the old one; in either - case, we ditch the incoming segment. */ - break; - } - } else { - if (prev == NULL) { - if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) { - /* The sequence number of the incoming segment is lower - than the sequence number of the first segment on the - queue. We put the incoming segment first on the - queue. */ - - if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) { - /* We need to trim the incoming segment. */ - inseg.len = next->tcphdr->seqno - seqno; - pbuf_realloc(inseg.p, inseg.len); - } - cseg = tcp_seg_copy(&inseg); - if (cseg != NULL) { - cseg->next = next; - pcb->ooseq = cseg; - } - break; - } - } else - /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) && - TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/ - if(TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)){ - /* The sequence number of the incoming segment is in - between the sequence numbers of the previous and - the next segment on ->ooseq. We trim and insert the - incoming segment and trim the previous segment, if - needed. */ - if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) { - /* We need to trim the incoming segment. */ - inseg.len = next->tcphdr->seqno - seqno; - pbuf_realloc(inseg.p, inseg.len); - } - - cseg = tcp_seg_copy(&inseg); - if (cseg != NULL) { - cseg->next = next; - prev->next = cseg; - if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) { - /* We need to trim the prev segment. */ - prev->len = seqno - prev->tcphdr->seqno; - pbuf_realloc(prev->p, prev->len); - } - } - break; - } - /* If the "next" segment is the last segment on the - ooseq queue, we add the incoming segment to the end - of the list. */ - if (next->next == NULL && - TCP_SEQ_GT(seqno, next->tcphdr->seqno)) { - next->next = tcp_seg_copy(&inseg); - if (next->next != NULL) { - if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) { - /* We need to trim the last segment. */ - next->len = seqno - next->tcphdr->seqno; - pbuf_realloc(next->p, next->len); - } - } - break; - } - } - prev = next; - } - } -#endif /* TCP_QUEUE_OOSEQ */ - - } - } else { - /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) || - TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ - if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){ - tcp_ack_now(pcb); - } - } - } else { - /* Segments with length 0 is taken care of here. Segments that - fall out of the window are ACKed. */ - /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) || - TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ - if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){ - tcp_ack_now(pcb); - } - } -} - -/* - * tcp_parseopt: - * - * Parses the options contained in the incoming segment. (Code taken - * from uIP with only small changes.) - * - */ - -static void -tcp_parseopt(struct tcp_pcb *pcb) -{ - u8_t c; - u8_t *opts, opt; - u16_t mss; - - opts = (u8_t *)tcphdr + TCP_HLEN; - - /* Parse the TCP MSS option, if present. */ - if(TCPH_HDRLEN(tcphdr) > 0x5) { - for(c = 0; c < (TCPH_HDRLEN(tcphdr) - 5) << 2 ;) { - opt = opts[c]; - if (opt == 0x00) { - /* End of options. */ - break; - } else if (opt == 0x01) { - ++c; - /* NOP option. */ - } else if (opt == 0x02 && - opts[c + 1] == 0x04) { - /* An MSS option with the right option length. */ - mss = (opts[c + 2] << 8) | opts[c + 3]; - pcb->mss = mss > TCP_MSS? TCP_MSS: mss; - - /* And we are done processing options. */ - break; - } else { - if (opts[c + 1] == 0) { - /* If the length field is zero, the options are malformed - and we don't process them further. */ - break; - } - /* All other options have a length field, so that we easily - can skip past them. */ - c += opts[c + 1]; - } - } - } -} -#endif /* LWIP_TCP */ - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/tcp_out.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/tcp_out.c deleted file mode 100644 index 62982bd14..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/tcp_out.c +++ /dev/null @@ -1,721 +0,0 @@ -/** - * @file - * - * Transmission Control Protocol, outgoing traffic - * - * The output functions of TCP. - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include - -#include "lwip/def.h" -#include "lwip/opt.h" -#include "lwip/mem.h" -#include "lwip/memp.h" -#include "lwip/sys.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/inet.h" -#include "lwip/tcp.h" -#include "lwip/stats.h" - -#if LWIP_TCP - -/* Forward declarations.*/ -static void tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb); - -err_t -tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags) -{ - /* no data, no length, flags, copy=1, no optdata, no optdatalen */ - return tcp_enqueue(pcb, NULL, 0, flags, 1, NULL, 0); -} - -/** - * Write data for sending (but does not send it immediately). - * - * It waits in the expectation of more data being sent soon (as - * it can send them more efficiently by combining them together). - * To prompt the system to send data now, call tcp_output() after - * calling tcp_write(). - * - * @arg pcb Protocol control block of the TCP connection to enqueue data for. - * - * @see tcp_write() - */ - -err_t -tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t copy) -{ - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, arg=%p, len=%"U16_F", copy=%"U16_F")\n", (void *)pcb, - arg, len, (u16_t)copy)); - /* connection is in valid state for data transmission? */ - if (pcb->state == ESTABLISHED || - pcb->state == CLOSE_WAIT || - pcb->state == SYN_SENT || - pcb->state == SYN_RCVD) { - if (len > 0) { - return tcp_enqueue(pcb, (void *)arg, len, 0, copy, NULL, 0); - } - return ERR_OK; - } else { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_STATE | 3, ("tcp_write() called in invalid state\n")); - return ERR_CONN; - } -} - -/** - * Enqueue either data or TCP options (but not both) for tranmission - * - * - * - * @arg pcb Protocol control block for the TCP connection to enqueue data for. - * @arg arg Pointer to the data to be enqueued for sending. - * @arg len Data length in bytes - * @arg flags - * @arg copy 1 if data must be copied, 0 if data is non-volatile and can be - * referenced. - * @arg optdata - * @arg optlen - */ -err_t -tcp_enqueue(struct tcp_pcb *pcb, void *arg, u16_t len, - u8_t flags, u8_t copy, - u8_t *optdata, u8_t optlen) -{ - struct pbuf *p; - struct tcp_seg *seg, *useg, *queue; - u32_t left, seqno; - u16_t seglen; - void *ptr; - u8_t queuelen; - - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_enqueue(pcb=%p, arg=%p, len=%"U16_F", flags=%"X16_F", copy=%"U16_F")\n", - (void *)pcb, arg, len, (u16_t)flags, (u16_t)copy)); - LWIP_ASSERT("tcp_enqueue: len == 0 || optlen == 0 (programmer violates API)", - len == 0 || optlen == 0); - LWIP_ASSERT("tcp_enqueue: arg == NULL || optdata == NULL (programmer violates API)", - arg == NULL || optdata == NULL); - /* fail on too much data */ - if (len > pcb->snd_buf) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too much data (len=%"U16_F" > snd_buf=%"U16_F")\n", len, pcb->snd_buf)); - return ERR_MEM; - } - left = len; - ptr = arg; - - /* seqno will be the sequence number of the first segment enqueued - * by the call to this function. */ - seqno = pcb->snd_lbb; - - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen)); - - /* If total number of pbufs on the unsent/unacked queues exceeds the - * configured maximum, return an error */ - queuelen = pcb->snd_queuelen; - if (queuelen >= TCP_SND_QUEUELEN) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too long queue %"U16_F" (max %"U16_F")\n", queuelen, TCP_SND_QUEUELEN)); - TCP_STATS_INC(tcp.memerr); - return ERR_MEM; - } - if (queuelen != 0) { - LWIP_ASSERT("tcp_enqueue: pbufs on queue => at least one queue non-empty", - pcb->unacked != NULL || pcb->unsent != NULL); - } else { - LWIP_ASSERT("tcp_enqueue: no pbufs on queue => both queues empty", - pcb->unacked == NULL && pcb->unsent == NULL); - } - - /* First, break up the data into segments and tuck them together in - * the local "queue" variable. */ - useg = queue = seg = NULL; - seglen = 0; - while (queue == NULL || left > 0) { - - /* The segment length should be the MSS if the data to be enqueued - * is larger than the MSS. */ - seglen = left > pcb->mss? pcb->mss: left; - - /* Allocate memory for tcp_seg, and fill in fields. */ - seg = memp_malloc(MEMP_TCP_SEG); - if (seg == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for tcp_seg\n")); - goto memerr; - } - seg->next = NULL; - seg->p = NULL; - - /* first segment of to-be-queued data? */ - if (queue == NULL) { - queue = seg; - } - /* subsequent segments of to-be-queued data */ - else { - /* Attach the segment to the end of the queued segments */ - LWIP_ASSERT("useg != NULL", useg != NULL); - useg->next = seg; - } - /* remember last segment of to-be-queued data for next iteration */ - useg = seg; - - /* If copy is set, memory should be allocated - * and data copied into pbuf, otherwise data comes from - * ROM or other static memory, and need not be copied. If - * optdata is != NULL, we have options instead of data. */ - - /* options? */ - if (optdata != NULL) { - if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { - goto memerr; - } - ++queuelen; - seg->dataptr = seg->p->payload; - } - /* copy from volatile memory? */ - else if (copy) { - if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_RAM)) == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue : could not allocate memory for pbuf copy size %"U16_F"\n", seglen)); - goto memerr; - } - ++queuelen; - if (arg != NULL) { - memcpy(seg->p->payload, ptr, seglen); - } - seg->dataptr = seg->p->payload; - } - /* do not copy data */ - else { - /* First, allocate a pbuf for holding the data. - * since the referenced data is available at least until it is sent out on the - * link (as it has to be ACKed by the remote party) we can safely use PBUF_ROM - * instead of PBUF_REF here. - */ - if ((p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for zero-copy pbuf\n")); - goto memerr; - } - ++queuelen; - /* reference the non-volatile payload data */ - p->payload = ptr; - seg->dataptr = ptr; - - /* Second, allocate a pbuf for the headers. */ - if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_RAM)) == NULL) { - /* If allocation fails, we have to deallocate the data pbuf as - * well. */ - pbuf_free(p); - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for header pbuf\n")); - goto memerr; - } - ++queuelen; - - /* Concatenate the headers and data pbufs together. */ - pbuf_cat(seg->p/*header*/, p/*data*/); - p = NULL; - } - - /* Now that there are more segments queued, we check again if the - length of the queue exceeds the configured maximum. */ - if (queuelen > TCP_SND_QUEUELEN) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: queue too long %"U16_F" (%"U16_F")\n", queuelen, TCP_SND_QUEUELEN)); - goto memerr; - } - - seg->len = seglen; - - /* build TCP header */ - if (pbuf_header(seg->p, TCP_HLEN)) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: no room for TCP header in pbuf.\n")); - TCP_STATS_INC(tcp.err); - goto memerr; - } - seg->tcphdr = seg->p->payload; - seg->tcphdr->src = htons(pcb->local_port); - seg->tcphdr->dest = htons(pcb->remote_port); - seg->tcphdr->seqno = htonl(seqno); - seg->tcphdr->urgp = 0; - TCPH_FLAGS_SET(seg->tcphdr, flags); - /* don't fill in tcphdr->ackno and tcphdr->wnd until later */ - - /* Copy the options into the header, if they are present. */ - if (optdata == NULL) { - TCPH_HDRLEN_SET(seg->tcphdr, 5); - } - else { - TCPH_HDRLEN_SET(seg->tcphdr, (5 + optlen / 4)); - /* Copy options into data portion of segment. - Options can thus only be sent in non data carrying - segments such as SYN|ACK. */ - memcpy(seg->dataptr, optdata, optlen); - } - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE, ("tcp_enqueue: queueing %"U32_F":%"U32_F" (0x%"X16_F")\n", - ntohl(seg->tcphdr->seqno), - ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg), - (u16_t)flags)); - - left -= seglen; - seqno += seglen; - ptr = (void *)((u8_t *)ptr + seglen); - } - - /* Now that the data to be enqueued has been broken up into TCP - segments in the queue variable, we add them to the end of the - pcb->unsent queue. */ - if (pcb->unsent == NULL) { - useg = NULL; - } - else { - for (useg = pcb->unsent; useg->next != NULL; useg = useg->next); - } - /* { useg is last segment on the unsent queue, NULL if list is empty } */ - - /* If there is room in the last pbuf on the unsent queue, - chain the first pbuf on the queue together with that. */ - if (useg != NULL && - TCP_TCPLEN(useg) != 0 && - !(TCPH_FLAGS(useg->tcphdr) & (TCP_SYN | TCP_FIN)) && - !(flags & (TCP_SYN | TCP_FIN)) && - /* fit within max seg size */ - useg->len + queue->len <= pcb->mss) { - /* Remove TCP header from first segment of our to-be-queued list */ - pbuf_header(queue->p, -TCP_HLEN); - pbuf_cat(useg->p, queue->p); - useg->len += queue->len; - useg->next = queue->next; - - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE | DBG_STATE, ("tcp_enqueue: chaining segments, new len %"U16_F"\n", useg->len)); - if (seg == queue) { - seg = NULL; - } - memp_free(MEMP_TCP_SEG, queue); - } - else { - /* empty list */ - if (useg == NULL) { - /* initialize list with this segment */ - pcb->unsent = queue; - } - /* enqueue segment */ - else { - useg->next = queue; - } - } - if ((flags & TCP_SYN) || (flags & TCP_FIN)) { - ++len; - } - pcb->snd_lbb += len; - - pcb->snd_buf -= len; - - /* update number of segments on the queues */ - pcb->snd_queuelen = queuelen; - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: %"S16_F" (after enqueued)\n", pcb->snd_queuelen)); - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_enqueue: valid queue length", - pcb->unacked != NULL || pcb->unsent != NULL); - } - - /* Set the PSH flag in the last segment that we enqueued, but only - if the segment has data (indicated by seglen > 0). */ - if (seg != NULL && seglen > 0 && seg->tcphdr != NULL) { - TCPH_SET_FLAG(seg->tcphdr, TCP_PSH); - } - - return ERR_OK; -memerr: - TCP_STATS_INC(tcp.memerr); - - if (queue != NULL) { - tcp_segs_free(queue); - } - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL || - pcb->unsent != NULL); - } - LWIP_DEBUGF(TCP_QLEN_DEBUG | DBG_STATE, ("tcp_enqueue: %"S16_F" (with mem err)\n", pcb->snd_queuelen)); - return ERR_MEM; -} - -/* find out what we can send and send it */ -err_t -tcp_output(struct tcp_pcb *pcb) -{ - struct pbuf *p; - struct tcp_hdr *tcphdr; - struct tcp_seg *seg, *useg; - u32_t wnd; -#if TCP_CWND_DEBUG - s16_t i = 0; -#endif /* TCP_CWND_DEBUG */ - - /* First, check if we are invoked by the TCP input processing - code. If so, we do not output anything. Instead, we rely on the - input processing code to call us when input processing is done - with. */ - if (tcp_input_pcb == pcb) { - return ERR_OK; - } - - wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd); - - seg = pcb->unsent; - - /* useg should point to last segment on unacked queue */ - useg = pcb->unacked; - if (useg != NULL) { - for (; useg->next != NULL; useg = useg->next); - } - - /* If the TF_ACK_NOW flag is set and no data will be sent (either - * because the ->unsent queue is empty or because the window does - * not allow it), construct an empty ACK segment and send it. - * - * If data is to be sent, we will just piggyback the ACK (see below). - */ - if (pcb->flags & TF_ACK_NOW && - (seg == NULL || - ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) { - p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); - if (p == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n")); - return ERR_BUF; - } - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt)); - /* remove ACK flags from the PCB, as we send an empty ACK now */ - pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); - - tcphdr = p->payload; - tcphdr->src = htons(pcb->local_port); - tcphdr->dest = htons(pcb->remote_port); - tcphdr->seqno = htonl(pcb->snd_nxt); - tcphdr->ackno = htonl(pcb->rcv_nxt); - TCPH_FLAGS_SET(tcphdr, TCP_ACK); - tcphdr->wnd = htons(pcb->rcv_wnd); - tcphdr->urgp = 0; - TCPH_HDRLEN_SET(tcphdr, 5); - - tcphdr->chksum = 0; -#if CHECKSUM_GEN_TCP - tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip), - IP_PROTO_TCP, p->tot_len); -#endif - ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, - IP_PROTO_TCP); - pbuf_free(p); - - return ERR_OK; - } - -#if TCP_OUTPUT_DEBUG - if (seg == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", (void*)pcb->unsent)); - } -#endif /* TCP_OUTPUT_DEBUG */ -#if TCP_CWND_DEBUG - if (seg == NULL) { - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", seg == NULL, ack %"U32_F"\n", - pcb->snd_wnd, pcb->cwnd, wnd, - pcb->lastack)); - } else { - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F"\n", - pcb->snd_wnd, pcb->cwnd, wnd, - ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len, - ntohl(seg->tcphdr->seqno), pcb->lastack)); - } -#endif /* TCP_CWND_DEBUG */ - /* data available and window allows it to be sent? */ - while (seg != NULL && - ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) { -#if TCP_CWND_DEBUG - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F", i %"S16_F"\n", - pcb->snd_wnd, pcb->cwnd, wnd, - ntohl(seg->tcphdr->seqno) + seg->len - - pcb->lastack, - ntohl(seg->tcphdr->seqno), pcb->lastack, i)); - ++i; -#endif /* TCP_CWND_DEBUG */ - - pcb->unsent = seg->next; - - if (pcb->state != SYN_SENT) { - TCPH_SET_FLAG(seg->tcphdr, TCP_ACK); - pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); - } - - tcp_output_segment(seg, pcb); - pcb->snd_nxt = ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg); - if (TCP_SEQ_LT(pcb->snd_max, pcb->snd_nxt)) { - pcb->snd_max = pcb->snd_nxt; - } - /* put segment on unacknowledged list if length > 0 */ - if (TCP_TCPLEN(seg) > 0) { - seg->next = NULL; - /* unacked list is empty? */ - if (pcb->unacked == NULL) { - pcb->unacked = seg; - useg = seg; - /* unacked list is not empty? */ - } else { - /* In the case of fast retransmit, the packet should not go to the tail - * of the unacked queue, but rather at the head. We need to check for - * this case. -STJ Jul 27, 2004 */ - if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))){ - /* add segment to head of unacked list */ - seg->next = pcb->unacked; - pcb->unacked = seg; - } else { - /* add segment to tail of unacked list */ - useg->next = seg; - useg = useg->next; - } - } - /* do not queue empty segments on the unacked list */ - } else { - tcp_seg_free(seg); - } - seg = pcb->unsent; - } - return ERR_OK; -} - -/** - * Actually send a TCP segment over IP - */ -static void -tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb) -{ - u16_t len; - struct netif *netif; - - /* The TCP header has already been constructed, but the ackno and - wnd fields remain. */ - seg->tcphdr->ackno = htonl(pcb->rcv_nxt); - - /* silly window avoidance */ - if (pcb->rcv_wnd < pcb->mss) { - seg->tcphdr->wnd = 0; - } else { - /* advertise our receive window size in this TCP segment */ - seg->tcphdr->wnd = htons(pcb->rcv_wnd); - } - - /* If we don't have a local IP address, we get one by - calling ip_route(). */ - if (ip_addr_isany(&(pcb->local_ip))) { - netif = ip_route(&(pcb->remote_ip)); - if (netif == NULL) { - return; - } - ip_addr_set(&(pcb->local_ip), &(netif->ip_addr)); - } - - pcb->rtime = 0; - - if (pcb->rttest == 0) { - pcb->rttest = tcp_ticks; - pcb->rtseq = ntohl(seg->tcphdr->seqno); - - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %"U32_F"\n", pcb->rtseq)); - } - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n", - htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) + - seg->len)); - - len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload); - - seg->p->len -= len; - seg->p->tot_len -= len; - - seg->p->payload = seg->tcphdr; - - seg->tcphdr->chksum = 0; -#if CHECKSUM_GEN_TCP - seg->tcphdr->chksum = inet_chksum_pseudo(seg->p, - &(pcb->local_ip), - &(pcb->remote_ip), - IP_PROTO_TCP, seg->p->tot_len); -#endif - TCP_STATS_INC(tcp.xmit); - - ip_output(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, - IP_PROTO_TCP); -} - -void -tcp_rst(u32_t seqno, u32_t ackno, - struct ip_addr *local_ip, struct ip_addr *remote_ip, - u16_t local_port, u16_t remote_port) -{ - struct pbuf *p; - struct tcp_hdr *tcphdr; - p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); - if (p == NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n")); - return; - } - - tcphdr = p->payload; - tcphdr->src = htons(local_port); - tcphdr->dest = htons(remote_port); - tcphdr->seqno = htonl(seqno); - tcphdr->ackno = htonl(ackno); - TCPH_FLAGS_SET(tcphdr, TCP_RST | TCP_ACK); - tcphdr->wnd = htons(TCP_WND); - tcphdr->urgp = 0; - TCPH_HDRLEN_SET(tcphdr, 5); - - tcphdr->chksum = 0; -#if CHECKSUM_GEN_TCP - tcphdr->chksum = inet_chksum_pseudo(p, local_ip, remote_ip, - IP_PROTO_TCP, p->tot_len); -#endif - TCP_STATS_INC(tcp.xmit); - /* Send output with hardcoded TTL since we have no access to the pcb */ - ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP); - pbuf_free(p); - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno)); -} - -/* requeue all unacked segments for retransmission */ -void -tcp_rexmit_rto(struct tcp_pcb *pcb) -{ - struct tcp_seg *seg; - - if (pcb->unacked == NULL) { - return; - } - - /* Move all unacked segments to the head of the unsent queue */ - for (seg = pcb->unacked; seg->next != NULL; seg = seg->next); - /* concatenate unsent queue after unacked queue */ - seg->next = pcb->unsent; - /* unsent queue is the concatenated queue (of unacked, unsent) */ - pcb->unsent = pcb->unacked; - /* unacked queue is now empty */ - pcb->unacked = NULL; - - pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno); - /* increment number of retransmissions */ - ++pcb->nrtx; - - /* Don't take any RTT measurements after retransmitting. */ - pcb->rttest = 0; - - /* Do the actual retransmission */ - tcp_output(pcb); -} - -void -tcp_rexmit(struct tcp_pcb *pcb) -{ - struct tcp_seg *seg; - - if (pcb->unacked == NULL) { - return; - } - - /* Move the first unacked segment to the unsent queue */ - seg = pcb->unacked->next; - pcb->unacked->next = pcb->unsent; - pcb->unsent = pcb->unacked; - pcb->unacked = seg; - - pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno); - - ++pcb->nrtx; - - /* Don't take any rtt measurements after retransmitting. */ - pcb->rttest = 0; - - /* Do the actual retransmission. */ - tcp_output(pcb); - -} - - -void -tcp_keepalive(struct tcp_pcb *pcb) -{ - struct pbuf *p; - struct tcp_hdr *tcphdr; - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), - ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip))); - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F" pcb->tmr %"U32_F" pcb->keep_cnt %"U16_F"\n", tcp_ticks, pcb->tmr, pcb->keep_cnt)); - - p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); - - if(p == NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: could not allocate memory for pbuf\n")); - return; - } - - tcphdr = p->payload; - tcphdr->src = htons(pcb->local_port); - tcphdr->dest = htons(pcb->remote_port); - tcphdr->seqno = htonl(pcb->snd_nxt - 1); - tcphdr->ackno = htonl(pcb->rcv_nxt); - tcphdr->wnd = htons(pcb->rcv_wnd); - tcphdr->urgp = 0; - TCPH_HDRLEN_SET(tcphdr, 5); - - tcphdr->chksum = 0; -#if CHECKSUM_GEN_TCP - tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip, IP_PROTO_TCP, p->tot_len); -#endif - TCP_STATS_INC(tcp.xmit); - - /* Send output to IP */ - ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP); - - pbuf_free(p); - - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F".\n", pcb->snd_nxt - 1, pcb->rcv_nxt)); -} - -#endif /* LWIP_TCP */ - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/udp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/udp.c deleted file mode 100644 index d1e0eacac..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/core/udp.c +++ /dev/null @@ -1,655 +0,0 @@ -/** - * @file - * User Datagram Protocol module - * - */ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - - -/* udp.c - * - * The code for the User Datagram Protocol UDP. - * - */ - -#include - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/memp.h" -#include "lwip/inet.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/udp.h" -#include "lwip/icmp.h" - -#include "lwip/stats.h" - -#include "arch/perf.h" -#include "lwip/snmp.h" - -/* The list of UDP PCBs */ -#if LWIP_UDP -/* was static, but we may want to access this from a socket layer */ -struct udp_pcb *udp_pcbs = NULL; - -static struct udp_pcb *pcb_cache = NULL; - -void -udp_init(void) -{ - udp_pcbs = pcb_cache = NULL; -} - -/** - * Process an incoming UDP datagram. - * - * Given an incoming UDP datagram (as a chain of pbufs) this function - * finds a corresponding UDP PCB and - * - * @param pbuf pbuf to be demultiplexed to a UDP PCB. - * @param netif network interface on which the datagram was received. - * - */ -void -udp_input(struct pbuf *p, struct netif *inp) -{ - struct udp_hdr *udphdr; - struct udp_pcb *pcb; - struct udp_pcb *uncon_pcb; - struct ip_hdr *iphdr; - u16_t src, dest; - u8_t local_match; - - PERF_START; - - UDP_STATS_INC(udp.recv); - - iphdr = p->payload; - - if (pbuf_header(p, -((s16_t)(UDP_HLEN + IPH_HL(iphdr) * 4)))) { - /* drop short packets */ - LWIP_DEBUGF(UDP_DEBUG, ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len)); - UDP_STATS_INC(udp.lenerr); - UDP_STATS_INC(udp.drop); - snmp_inc_udpinerrors(); - pbuf_free(p); - goto end; - } - - udphdr = (struct udp_hdr *)((u8_t *)p->payload - UDP_HLEN); - - LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len)); - - src = ntohs(udphdr->src); - dest = ntohs(udphdr->dest); - - udp_debug_print(udphdr); - - /* print the UDP source and destination */ - LWIP_DEBUGF(UDP_DEBUG, ("udp (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") <-- (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n", - ip4_addr1(&iphdr->dest), ip4_addr2(&iphdr->dest), - ip4_addr3(&iphdr->dest), ip4_addr4(&iphdr->dest), ntohs(udphdr->dest), - ip4_addr1(&iphdr->src), ip4_addr2(&iphdr->src), - ip4_addr3(&iphdr->src), ip4_addr4(&iphdr->src), ntohs(udphdr->src))); - - local_match = 0; - uncon_pcb = NULL; - /* Iterate through the UDP pcb list for a matching pcb */ - for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { - /* print the PCB local and remote address */ - LWIP_DEBUGF(UDP_DEBUG, ("pcb (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") --- (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n", - ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip), - ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port, - ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), - ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port)); - - /* compare PCB local addr+port to UDP destination addr+port */ - if ((pcb->local_port == dest) && - (ip_addr_isany(&pcb->local_ip) || - ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)))) { - local_match = 1; - if ((uncon_pcb == NULL) && - ((pcb->flags & UDP_FLAGS_CONNECTED) == 0)) { - /* the first unconnected matching PCB */ - uncon_pcb = pcb; - } - } - /* compare PCB remote addr+port to UDP source addr+port */ - if ((local_match != 0) && - (pcb->remote_port == src) && - (ip_addr_isany(&pcb->remote_ip) || - ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)))) { - /* the first fully matching PCB */ - break; - } - } - /* no fully matching pcb found? then look for an unconnected pcb */ - if (pcb == NULL) { - pcb = uncon_pcb; - } - - /* Check checksum if this is a match or if it was directed at us. */ - if (pcb != NULL || ip_addr_cmp(&inp->ip_addr, &iphdr->dest)) - { - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: calculating checksum\n")); - pbuf_header(p, UDP_HLEN); -#ifdef IPv6 - if (iphdr->nexthdr == IP_PROTO_UDPLITE) { -#else - if (IPH_PROTO(iphdr) == IP_PROTO_UDPLITE) { -#endif /* IPv4 */ - /* Do the UDP Lite checksum */ -#if CHECKSUM_CHECK_UDP - if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), - (struct ip_addr *)&(iphdr->dest), - IP_PROTO_UDPLITE, ntohs(udphdr->len)) != 0) { - LWIP_DEBUGF(UDP_DEBUG | 2, ("udp_input: UDP Lite datagram discarded due to failing checksum\n")); - UDP_STATS_INC(udp.chkerr); - UDP_STATS_INC(udp.drop); - snmp_inc_udpinerrors(); - pbuf_free(p); - goto end; - } -#endif - } else { -#if CHECKSUM_CHECK_UDP - if (udphdr->chksum != 0) { - if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), - (struct ip_addr *)&(iphdr->dest), - IP_PROTO_UDP, p->tot_len) != 0) { - LWIP_DEBUGF(UDP_DEBUG | 2, ("udp_input: UDP datagram discarded due to failing checksum\n")); - - UDP_STATS_INC(udp.chkerr); - UDP_STATS_INC(udp.drop); - snmp_inc_udpinerrors(); - pbuf_free(p); - goto end; - } - } -#endif - } - pbuf_header(p, -UDP_HLEN); - if (pcb != NULL) { - snmp_inc_udpindatagrams(); - /* callback */ - if (pcb->recv != NULL) - { - pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src), src); - } - } else { - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: not for us.\n")); - - /* No match was found, send ICMP destination port unreachable unless - destination address was broadcast/multicast. */ - - if (!ip_addr_isbroadcast(&iphdr->dest, inp) && - !ip_addr_ismulticast(&iphdr->dest)) { - - /* adjust pbuf pointer */ - p->payload = iphdr; - icmp_dest_unreach(p, ICMP_DUR_PORT); - } - UDP_STATS_INC(udp.proterr); - UDP_STATS_INC(udp.drop); - snmp_inc_udpnoports(); - pbuf_free(p); - } - } else { - pbuf_free(p); - } - end: - - PERF_STOP("udp_input"); -} - -/** - * Send data to a specified address using UDP. - * - * @param pcb UDP PCB used to send the data. - * @param pbuf chain of pbuf's to be sent. - * @param dst_ip Destination IP address. - * @param dst_port Destination UDP port. - * - * If the PCB already has a remote address association, it will - * be restored after the data is sent. - * - * @return lwIP error code. - * - ERR_OK. Successful. No error occured. - * - ERR_MEM. Out of memory. - * - ERR_RTE. Could not find route to destination address. - * - * @see udp_disconnect() udp_send() - */ -err_t -udp_sendto(struct udp_pcb *pcb, struct pbuf *p, - struct ip_addr *dst_ip, u16_t dst_port) -{ - err_t err; - /* temporary space for current PCB remote address */ - struct ip_addr pcb_remote_ip; - u16_t pcb_remote_port; - /* remember current remote peer address of PCB */ - pcb_remote_ip.addr = pcb->remote_ip.addr; - pcb_remote_port = pcb->remote_port; - /* copy packet destination address to PCB remote peer address */ - pcb->remote_ip.addr = dst_ip->addr; - pcb->remote_port = dst_port; - /* send to the packet destination address */ - err = udp_send(pcb, p); - /* restore PCB remote peer address */ - pcb->remote_ip.addr = pcb_remote_ip.addr; - pcb->remote_port = pcb_remote_port; - return err; -} - -/** - * Send data using UDP. - * - * @param pcb UDP PCB used to send the data. - * @param pbuf chain of pbuf's to be sent. - * - * @return lwIP error code. - * - ERR_OK. Successful. No error occured. - * - ERR_MEM. Out of memory. - * - ERR_RTE. Could not find route to destination address. - * - * @see udp_disconnect() udp_sendto() - */ -err_t -udp_send(struct udp_pcb *pcb, struct pbuf *p) -{ - struct udp_hdr *udphdr; - struct netif *netif; - struct ip_addr *src_ip; - err_t err; - struct pbuf *q; /* q will be sent down the stack */ - - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_send\n")); - - /* if the PCB is not yet bound to a port, bind it here */ - if (pcb->local_port == 0) { - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: not yet bound to a port, binding now\n")); - err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); - if (err != ERR_OK) { - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: forced port bind failed\n")); - return err; - } - } - /* find the outgoing network interface for this packet */ - netif = ip_route(&(pcb->remote_ip)); - /* no outgoing network interface could be found? */ - if (netif == NULL) { - LWIP_DEBUGF(UDP_DEBUG | 1, ("udp_send: No route to 0x%"X32_F"\n", pcb->remote_ip.addr)); - UDP_STATS_INC(udp.rterr); - return ERR_RTE; - } - - /* not enough space to add an UDP header to first pbuf in given p chain? */ - if (pbuf_header(p, UDP_HLEN)) { - /* allocate header in a seperate new pbuf */ - q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM); - /* new header pbuf could not be allocated? */ - if (q == NULL) { - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: could not allocate header\n")); - return ERR_MEM; - } - /* chain header q in front of given pbuf p */ - pbuf_chain(q, p); - /* { first pbuf q points to header pbuf } */ - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); - /* adding a header within p succeeded */ - } else { - /* first pbuf q equals given pbuf */ - q = p; - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p)); - } - /* { q now represents the packet to be sent } */ - udphdr = q->payload; - udphdr->src = htons(pcb->local_port); - udphdr->dest = htons(pcb->remote_port); - /* in UDP, 0 checksum means 'no checksum' */ - udphdr->chksum = 0x0000; - - /* PCB local address is IP_ANY_ADDR? */ - if (ip_addr_isany(&pcb->local_ip)) { - /* use outgoing network interface IP address as source address */ - src_ip = &(netif->ip_addr); - } else { - /* use UDP PCB local IP address as source address */ - src_ip = &(pcb->local_ip); - } - - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %"U16_F"\n", q->tot_len)); - - /* UDP Lite protocol? */ - if (pcb->flags & UDP_FLAGS_UDPLITE) { - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %"U16_F"\n", q->tot_len)); - /* set UDP message length in UDP header */ - udphdr->len = htons(pcb->chksum_len); - /* calculate checksum */ -#if CHECKSUM_GEN_UDP - udphdr->chksum = inet_chksum_pseudo(q, src_ip, &(pcb->remote_ip), - IP_PROTO_UDP, pcb->chksum_len); - /* chksum zero must become 0xffff, as zero means 'no checksum' */ - if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff; -#else - udphdr->chksum = 0x0000; -#endif - /* output to IP */ - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDPLITE,)\n")); - err = ip_output_if (q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif); - /* UDP */ - } else { - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len)); - udphdr->len = htons(q->tot_len); - /* calculate checksum */ -#if CHECKSUM_GEN_UDP - if ((pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) { - udphdr->chksum = inet_chksum_pseudo(q, src_ip, &pcb->remote_ip, IP_PROTO_UDP, q->tot_len); - /* chksum zero must become 0xffff, as zero means 'no checksum' */ - if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff; - } -#else - udphdr->chksum = 0x0000; -#endif - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum)); - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n")); - /* output to IP */ - err = ip_output_if(q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif); - } - /* TODO: must this be increased even if error occured? */ - snmp_inc_udpoutdatagrams(); - - /* did we chain a seperate header pbuf earlier? */ - if (q != p) { - /* free the header pbuf */ - pbuf_free(q); q = NULL; - /* { p is still referenced by the caller, and will live on } */ - } - - UDP_STATS_INC(udp.xmit); - return err; -} - -/** - * Bind an UDP PCB. - * - * @param pcb UDP PCB to be bound with a local address ipaddr and port. - * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to - * bind to all local interfaces. - * @param port local UDP port to bind with. - * - * @return lwIP error code. - * - ERR_OK. Successful. No error occured. - * - ERR_USE. The specified ipaddr and port are already bound to by - * another UDP PCB. - * - * @see udp_disconnect() - */ -err_t -udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) -{ - struct udp_pcb *ipcb; - u8_t rebind; - - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_bind(ipaddr = ")); - ip_addr_debug_print(UDP_DEBUG, ipaddr); - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, (", port = %"U16_F")\n", port)); - - rebind = 0; - /* Check for double bind and rebind of the same pcb */ - for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { - /* is this UDP PCB already on active list? */ - if (pcb == ipcb) { - /* pcb may occur at most once in active list */ - LWIP_ASSERT("rebind == 0", rebind == 0); - /* pcb already in list, just rebind */ - rebind = 1; - } - -/* this code does not allow upper layer to share a UDP port for - listening to broadcast or multicast traffic (See SO_REUSE_ADDR and - SO_REUSE_PORT under *BSD). TODO: See where it fits instead, OR - combine with implementation of UDP PCB flags. Leon Woestenberg. */ -#ifdef LWIP_UDP_TODO - /* port matches that of PCB in list? */ - else if ((ipcb->local_port == port) && - /* IP address matches, or one is IP_ADDR_ANY? */ - (ip_addr_isany(&(ipcb->local_ip)) || - ip_addr_isany(ipaddr) || - ip_addr_cmp(&(ipcb->local_ip), ipaddr))) { - /* other PCB already binds to this local IP and port */ - LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: local port %"U16_F" already bound by another pcb\n", port)); - return ERR_USE; - } -#endif - - } - - ip_addr_set(&pcb->local_ip, ipaddr); - /* no port specified? */ - if (port == 0) { -#ifndef UDP_LOCAL_PORT_RANGE_START -#define UDP_LOCAL_PORT_RANGE_START 4096 -#define UDP_LOCAL_PORT_RANGE_END 0x7fff -#endif - port = UDP_LOCAL_PORT_RANGE_START; - ipcb = udp_pcbs; - while ((ipcb != NULL) && (port != UDP_LOCAL_PORT_RANGE_END)) { - if (ipcb->local_port == port) { - port++; - ipcb = udp_pcbs; - } else - ipcb = ipcb->next; - } - if (ipcb != NULL) { - /* no more ports available in local range */ - LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n")); - return ERR_USE; - } - } - pcb->local_port = port; - /* pcb not active yet? */ - if (rebind == 0) { - /* place the PCB on the active list if not already there */ - pcb->next = udp_pcbs; - udp_pcbs = pcb; - } - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_bind: bound to %"U16_F".%"U16_F".%"U16_F".%"U16_F", port %"U16_F"\n", - (u16_t)(ntohl(pcb->local_ip.addr) >> 24 & 0xff), - (u16_t)(ntohl(pcb->local_ip.addr) >> 16 & 0xff), - (u16_t)(ntohl(pcb->local_ip.addr) >> 8 & 0xff), - (u16_t)(ntohl(pcb->local_ip.addr) & 0xff), pcb->local_port)); - return ERR_OK; -} -/** - * Connect an UDP PCB. - * - * This will associate the UDP PCB with the remote address. - * - * @param pcb UDP PCB to be connected with remote address ipaddr and port. - * @param ipaddr remote IP address to connect with. - * @param port remote UDP port to connect with. - * - * @return lwIP error code - * - * @see udp_disconnect() - */ -err_t -udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) -{ - struct udp_pcb *ipcb; - - if (pcb->local_port == 0) { - err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); - if (err != ERR_OK) - return err; - } - - ip_addr_set(&pcb->remote_ip, ipaddr); - pcb->remote_port = port; - pcb->flags |= UDP_FLAGS_CONNECTED; -/** TODO: this functionality belongs in upper layers */ -#ifdef LWIP_UDP_TODO - /* Nail down local IP for netconn_addr()/getsockname() */ - if (ip_addr_isany(&pcb->local_ip) && !ip_addr_isany(&pcb->remote_ip)) { - struct netif *netif; - - if ((netif = ip_route(&(pcb->remote_ip))) == NULL) { - LWIP_DEBUGF(UDP_DEBUG, ("udp_connect: No route to 0x%lx\n", pcb->remote_ip.addr)); - UDP_STATS_INC(udp.rterr); - return ERR_RTE; - } - /** TODO: this will bind the udp pcb locally, to the interface which - is used to route output packets to the remote address. However, we - might want to accept incoming packets on any interface! */ - pcb->local_ip = netif->ip_addr; - } else if (ip_addr_isany(&pcb->remote_ip)) { - pcb->local_ip.addr = 0; - } -#endif - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_connect: connected to %"U16_F".%"U16_F".%"U16_F".%"U16_F",port %"U16_F"\n", - (u16_t)(ntohl(pcb->remote_ip.addr) >> 24 & 0xff), - (u16_t)(ntohl(pcb->remote_ip.addr) >> 16 & 0xff), - (u16_t)(ntohl(pcb->remote_ip.addr) >> 8 & 0xff), - (u16_t)(ntohl(pcb->remote_ip.addr) & 0xff), pcb->remote_port)); - - /* Insert UDP PCB into the list of active UDP PCBs. */ - for(ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { - if (pcb == ipcb) { - /* already on the list, just return */ - return ERR_OK; - } - } - /* PCB not yet on the list, add PCB now */ - pcb->next = udp_pcbs; - udp_pcbs = pcb; - return ERR_OK; -} - -void -udp_disconnect(struct udp_pcb *pcb) -{ - /* reset remote address association */ - ip_addr_set(&pcb->remote_ip, IP_ADDR_ANY); - pcb->remote_port = 0; - /* mark PCB as unconnected */ - pcb->flags &= ~UDP_FLAGS_CONNECTED; -} - -void -udp_recv(struct udp_pcb *pcb, - void (* recv)(void *arg, struct udp_pcb *upcb, struct pbuf *p, - struct ip_addr *addr, u16_t port), - void *recv_arg) -{ - /* remember recv() callback and user data */ - pcb->recv = recv; - pcb->recv_arg = recv_arg; -} -/** - * Remove an UDP PCB. - * - * @param pcb UDP PCB to be removed. The PCB is removed from the list of - * UDP PCB's and the data structure is freed from memory. - * - * @see udp_new() - */ -void -udp_remove(struct udp_pcb *pcb) -{ - struct udp_pcb *pcb2; - /* pcb to be removed is first in list? */ - if (udp_pcbs == pcb) { - /* make list start at 2nd pcb */ - udp_pcbs = udp_pcbs->next; - /* pcb not 1st in list */ - } else for(pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { - /* find pcb in udp_pcbs list */ - if (pcb2->next != NULL && pcb2->next == pcb) { - /* remove pcb from list */ - pcb2->next = pcb->next; - } - } - memp_free(MEMP_UDP_PCB, pcb); -} -/** - * Create a UDP PCB. - * - * @return The UDP PCB which was created. NULL if the PCB data structure - * could not be allocated. - * - * @see udp_remove() - */ -struct udp_pcb * -udp_new(void) { - struct udp_pcb *pcb; - pcb = memp_malloc(MEMP_UDP_PCB); - /* could allocate UDP PCB? */ - if (pcb != NULL) { - /* initialize PCB to all zeroes */ - memset(pcb, 0, sizeof(struct udp_pcb)); - pcb->ttl = UDP_TTL; - } - - - return pcb; -} - -#if UDP_DEBUG -void -udp_debug_print(struct udp_hdr *udphdr) -{ - LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n")); - LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", - ntohs(udphdr->src), ntohs(udphdr->dest))); - LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | 0x%04"X16_F" | (len, chksum)\n", - ntohs(udphdr->len), ntohs(udphdr->chksum))); - LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); -} -#endif /* UDP_DEBUG */ - -#endif /* LWIP_UDP */ - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv4/lwip/icmp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv4/lwip/icmp.h deleted file mode 100644 index 634405b71..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv4/lwip/icmp.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_ICMP_H__ -#define __LWIP_ICMP_H__ - -#include "lwip/arch.h" - -#include "lwip/opt.h" -#include "lwip/pbuf.h" - -#include "lwip/ip_addr.h" -#include "lwip/netif.h" - -#define ICMP_ER 0 /* echo reply */ -#define ICMP_DUR 3 /* destination unreachable */ -#define ICMP_SQ 4 /* source quench */ -#define ICMP_RD 5 /* redirect */ -#define ICMP_ECHO 8 /* echo */ -#define ICMP_TE 11 /* time exceeded */ -#define ICMP_PP 12 /* parameter problem */ -#define ICMP_TS 13 /* timestamp */ -#define ICMP_TSR 14 /* timestamp reply */ -#define ICMP_IRQ 15 /* information request */ -#define ICMP_IR 16 /* information reply */ - -enum icmp_dur_type { - ICMP_DUR_NET = 0, /* net unreachable */ - ICMP_DUR_HOST = 1, /* host unreachable */ - ICMP_DUR_PROTO = 2, /* protocol unreachable */ - ICMP_DUR_PORT = 3, /* port unreachable */ - ICMP_DUR_FRAG = 4, /* fragmentation needed and DF set */ - ICMP_DUR_SR = 5 /* source route failed */ -}; - -enum icmp_te_type { - ICMP_TE_TTL = 0, /* time to live exceeded in transit */ - ICMP_TE_FRAG = 1 /* fragment reassembly time exceeded */ -}; - -void icmp_input(struct pbuf *p, struct netif *inp); - -void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t); -void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t); - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct icmp_echo_hdr { - PACK_STRUCT_FIELD(u16_t _type_code); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FIELD(u16_t id); - PACK_STRUCT_FIELD(u16_t seqno); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END - -PACK_STRUCT_BEGIN -struct icmp_dur_hdr { - PACK_STRUCT_FIELD(u16_t _type_code); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FIELD(u32_t unused); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END - -PACK_STRUCT_BEGIN -struct icmp_te_hdr { - PACK_STRUCT_FIELD(u16_t _type_code); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FIELD(u32_t unused); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#define ICMPH_TYPE(hdr) (ntohs((hdr)->_type_code) >> 8) -#define ICMPH_CODE(hdr) (ntohs((hdr)->_type_code) & 0xff) - -#define ICMPH_TYPE_SET(hdr, type) ((hdr)->_type_code = htons(ICMPH_CODE(hdr) | ((type) << 8))) -#define ICMPH_CODE_SET(hdr, code) ((hdr)->_type_code = htons((code) | (ICMPH_TYPE(hdr) << 8))) - -#endif /* __LWIP_ICMP_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv4/lwip/inet.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv4/lwip/inet.h deleted file mode 100644 index 6d79aab7a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv4/lwip/inet.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_INET_H__ -#define __LWIP_INET_H__ - -#include "lwip/arch.h" - -#include "lwip/opt.h" -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" - -u16_t inet_chksum(void *dataptr, u16_t len); -#if 0 /* optimized routine */ -u16_t inet_chksum4(u8_t *dataptr, u16_t len); -#endif -u16_t inet_chksum_pbuf(struct pbuf *p); -u16_t inet_chksum_pseudo(struct pbuf *p, - struct ip_addr *src, struct ip_addr *dest, - u8_t proto, u16_t proto_len); - -u32_t inet_addr(const char *cp); -s8_t inet_aton(const char *cp, struct in_addr *addr); -char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */ - -#ifdef htons -#undef htons -#endif /* htons */ -#ifdef htonl -#undef htonl -#endif /* htonl */ -#ifdef ntohs -#undef ntohs -#endif /* ntohs */ -#ifdef ntohl -#undef ntohl -#endif /* ntohl */ - -#if BYTE_ORDER == BIG_ENDIAN -#define htons(x) (x) -#define ntohs(x) (x) -#define htonl(x) (x) -#define ntohl(x) (x) -#else -#ifdef LWIP_PREFIX_BYTEORDER_FUNCS -/* workaround for naming collisions on some platforms */ -#define htons lwip_htons -#define ntohs lwip_ntohs -#define htonl lwip_htonl -#define ntohl lwip_ntohl -#endif -u16_t htons(u16_t x); -u16_t ntohs(u16_t x); -u32_t htonl(u32_t x); -u32_t ntohl(u32_t x); -#endif - -#endif /* __LWIP_INET_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv4/lwip/ip.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv4/lwip/ip.h deleted file mode 100644 index 4c15e1a0e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv4/lwip/ip.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_IP_H__ -#define __LWIP_IP_H__ - -#include "lwip/arch.h" - -#include "lwip/def.h" -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" - -#include "lwip/err.h" - - -void ip_init(void); -struct netif *ip_route(struct ip_addr *dest); -err_t ip_input(struct pbuf *p, struct netif *inp); -err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t tos, u8_t proto); -err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t tos, u8_t proto, - struct netif *netif); - -#define IP_HLEN 20 - -#define IP_PROTO_ICMP 1 -#define IP_PROTO_UDP 17 -#define IP_PROTO_UDPLITE 170 -#define IP_PROTO_TCP 6 - -/* This is passed as the destination address to ip_output_if (not - to ip_output), meaning that an IP header already is constructed - in the pbuf. This is used when TCP retransmits. */ -#ifdef IP_HDRINCL -#undef IP_HDRINCL -#endif /* IP_HDRINCL */ -#define IP_HDRINCL NULL - - -/* This is the common part of all PCB types. It needs to be at the - beginning of a PCB type definition. It is located here so that - changes to this common part are made in one location instead of - having to change all PCB structs. */ -#define IP_PCB struct ip_addr local_ip; \ - struct ip_addr remote_ip; \ - /* Socket options */ \ - u16_t so_options; \ - /* Type Of Service */ \ - u8_t tos; \ - /* Time To Live */ \ - u8_t ttl - -/* - * Option flags per-socket. These are the same like SO_XXX. - */ -#define SOF_DEBUG (u16_t)0x0001U /* turn on debugging info recording */ -#define SOF_ACCEPTCONN (u16_t)0x0002U /* socket has had listen() */ -#define SOF_REUSEADDR (u16_t)0x0004U /* allow local address reuse */ -#define SOF_KEEPALIVE (u16_t)0x0008U /* keep connections alive */ -#define SOF_DONTROUTE (u16_t)0x0010U /* just use interface addresses */ -#define SOF_BROADCAST (u16_t)0x0020U /* permit sending of broadcast msgs */ -#define SOF_USELOOPBACK (u16_t)0x0040U /* bypass hardware when possible */ -#define SOF_LINGER (u16_t)0x0080U /* linger on close if data present */ -#define SOF_OOBINLINE (u16_t)0x0100U /* leave received OOB data in line */ -#define SOF_REUSEPORT (u16_t)0x0200U /* allow local address & port reuse */ - - - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ip_hdr { - /* version / header length / type of service */ - PACK_STRUCT_FIELD(u16_t _v_hl_tos); - /* total length */ - PACK_STRUCT_FIELD(u16_t _len); - /* identification */ - PACK_STRUCT_FIELD(u16_t _id); - /* fragment offset field */ - PACK_STRUCT_FIELD(u16_t _offset); -#define IP_RF 0x8000 /* reserved fragment flag */ -#define IP_DF 0x4000 /* dont fragment flag */ -#define IP_MF 0x2000 /* more fragments flag */ -#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ - /* time to live / protocol*/ - PACK_STRUCT_FIELD(u16_t _ttl_proto); - /* checksum */ - PACK_STRUCT_FIELD(u16_t _chksum); - /* source and destination IP addresses */ - PACK_STRUCT_FIELD(struct ip_addr src); - PACK_STRUCT_FIELD(struct ip_addr dest); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#define IPH_V(hdr) (ntohs((hdr)->_v_hl_tos) >> 12) -#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f) -#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff) -#define IPH_LEN(hdr) ((hdr)->_len) -#define IPH_ID(hdr) ((hdr)->_id) -#define IPH_OFFSET(hdr) ((hdr)->_offset) -#define IPH_TTL(hdr) (ntohs((hdr)->_ttl_proto) >> 8) -#define IPH_PROTO(hdr) (ntohs((hdr)->_ttl_proto) & 0xff) -#define IPH_CHKSUM(hdr) ((hdr)->_chksum) - -#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos))) -#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len) -#define IPH_ID_SET(hdr, id) (hdr)->_id = (id) -#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off) -#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl_proto = (htons(IPH_PROTO(hdr) | ((ttl) << 8))) -#define IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (IPH_TTL(hdr) << 8))) -#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum) - -#if IP_DEBUG -void ip_debug_print(struct pbuf *p); -#else -#define ip_debug_print(p) -#endif /* IP_DEBUG */ - -#endif /* __LWIP_IP_H__ */ - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv4/lwip/ip_addr.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv4/lwip/ip_addr.h deleted file mode 100644 index 2819b1529..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv4/lwip/ip_addr.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_IP_ADDR_H__ -#define __LWIP_IP_ADDR_H__ - -#include "lwip/arch.h" - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ip_addr { - PACK_STRUCT_FIELD(u32_t addr); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ip_addr2 { - PACK_STRUCT_FIELD(u16_t addrw[2]); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/* For compatibility with BSD code */ -struct in_addr { - u32_t s_addr; -}; - -struct netif; - -extern const struct ip_addr ip_addr_any; -extern const struct ip_addr ip_addr_broadcast; - -/** IP_ADDR_ can be used as a fixed IP address - * for the wildcard and the broadcast address - */ -#define IP_ADDR_ANY ((struct ip_addr *)&ip_addr_any) -#define IP_ADDR_BROADCAST ((struct ip_addr *)&ip_addr_broadcast) - -#define INADDR_NONE ((u32_t) 0xffffffff) /* 255.255.255.255 */ -#define INADDR_LOOPBACK ((u32_t) 0x7f000001) /* 127.0.0.1 */ - -/* Definitions of the bits in an Internet address integer. - - On subnets, host and network parts are found according to - the subnet mask, not these masks. */ - -#define IN_CLASSA(a) ((((u32_t)(a)) & 0x80000000) == 0) -#define IN_CLASSA_NET 0xff000000 -#define IN_CLASSA_NSHIFT 24 -#define IN_CLASSA_HOST (0xffffffff & ~IN_CLASSA_NET) -#define IN_CLASSA_MAX 128 - -#define IN_CLASSB(a) ((((u32_t)(a)) & 0xc0000000) == 0x80000000) -#define IN_CLASSB_NET 0xffff0000 -#define IN_CLASSB_NSHIFT 16 -#define IN_CLASSB_HOST (0xffffffff & ~IN_CLASSB_NET) -#define IN_CLASSB_MAX 65536 - -#define IN_CLASSC(a) ((((u32_t)(a)) & 0xe0000000) == 0xc0000000) -#define IN_CLASSC_NET 0xffffff00 -#define IN_CLASSC_NSHIFT 8 -#define IN_CLASSC_HOST (0xffffffff & ~IN_CLASSC_NET) - -#define IN_CLASSD(a) (((u32_t)(a) & 0xf0000000) == 0xe0000000) -#define IN_CLASSD_NET 0xf0000000 /* These ones aren't really */ -#define IN_CLASSD_NSHIFT 28 /* net and host fields, but */ -#define IN_CLASSD_HOST 0x0fffffff /* routing needn't know. */ -#define IN_MULTICAST(a) IN_CLASSD(a) - -#define IN_EXPERIMENTAL(a) (((u32_t)(a) & 0xf0000000) == 0xf0000000) -#define IN_BADCLASS(a) (((u32_t)(a) & 0xf0000000) == 0xf0000000) - -#define IN_LOOPBACKNET 127 /* official! */ - - -#define IP4_ADDR(ipaddr, a,b,c,d) (ipaddr)->addr = htonl(((u32_t)(a & 0xff) << 24) | ((u32_t)(b & 0xff) << 16) | \ - ((u32_t)(c & 0xff) << 8) | (u32_t)(d & 0xff)) - -#define ip_addr_set(dest, src) (dest)->addr = \ - ((src) == NULL? 0:\ - (src)->addr) -/** - * Determine if two address are on the same network. - * - * @arg addr1 IP address 1 - * @arg addr2 IP address 2 - * @arg mask network identifier mask - * @return !0 if the network identifiers of both address match - */ -#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \ - (mask)->addr) == \ - ((addr2)->addr & \ - (mask)->addr)) -#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr) - -#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == 0) - -u8_t ip_addr_isbroadcast(struct ip_addr *, struct netif *); - -#define ip_addr_ismulticast(addr1) (((addr1)->addr & ntohl(0xf0000000)) == ntohl(0xe0000000)) - - -#define ip_addr_debug_print(debug, ipaddr) LWIP_DEBUGF(debug, ("%"U16_F".%"U16_F".%"U16_F".%"U16_F, \ - ipaddr?(u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff:0, \ - ipaddr?(u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff:0, \ - ipaddr?(u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff:0, \ - ipaddr?(u16_t)ntohl((ipaddr)->addr) & 0xff:0U)) - -/* cast to unsigned int, as it is used as argument to printf functions - * which expect integer arguments. CSi: use cc.h formatters (conversion chars)! */ -#define ip4_addr1(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff) -#define ip4_addr2(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff) -#define ip4_addr3(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff) -#define ip4_addr4(ipaddr) ((u16_t)(ntohl((ipaddr)->addr)) & 0xff) -#endif /* __LWIP_IP_ADDR_H__ */ - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv4/lwip/ip_frag.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv4/lwip/ip_frag.h deleted file mode 100644 index a982c5a63..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv4/lwip/ip_frag.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Jani Monoses - * - */ - -#ifndef __LWIP_IP_FRAG_H__ -#define __LWIP_IP_FRAG_H__ - -#include "lwip/err.h" -#include "lwip/pbuf.h" -#include "lwip/netif.h" -#include "lwip/ip_addr.h" - -void ip_reass_tmr(void); -struct pbuf * ip_reass(struct pbuf *p); -err_t ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest); - -#endif /* __LWIP_IP_FRAG_H__ */ - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv6/lwip/icmp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv6/lwip/icmp.h deleted file mode 100644 index 2b6adb122..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv6/lwip/icmp.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_ICMP_H__ -#define __LWIP_ICMP_H__ - -#include "lwip/arch.h" - -#include "lwip/opt.h" -#include "lwip/pbuf.h" - -#include "lwip/netif.h" - -#define ICMP6_DUR 1 -#define ICMP6_TE 3 -#define ICMP6_ECHO 128 /* echo */ -#define ICMP6_ER 129 /* echo reply */ - - -enum icmp_dur_type { - ICMP_DUR_NET = 0, /* net unreachable */ - ICMP_DUR_HOST = 1, /* host unreachable */ - ICMP_DUR_PROTO = 2, /* protocol unreachable */ - ICMP_DUR_PORT = 3, /* port unreachable */ - ICMP_DUR_FRAG = 4, /* fragmentation needed and DF set */ - ICMP_DUR_SR = 5 /* source route failed */ -}; - -enum icmp_te_type { - ICMP_TE_TTL = 0, /* time to live exceeded in transit */ - ICMP_TE_FRAG = 1 /* fragment reassembly time exceeded */ -}; - -void icmp_input(struct pbuf *p, struct netif *inp); - -void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t); -void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t); - -struct icmp_echo_hdr { - u8_t type; - u8_t icode; - u16_t chksum; - u16_t id; - u16_t seqno; -}; - -struct icmp_dur_hdr { - u8_t type; - u8_t icode; - u16_t chksum; - u32_t unused; -}; - -struct icmp_te_hdr { - u8_t type; - u8_t icode; - u16_t chksum; - u32_t unused; -}; - -#endif /* __LWIP_ICMP_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv6/lwip/inet.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv6/lwip/inet.h deleted file mode 100644 index ae7834364..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv6/lwip/inet.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_INET_H__ -#define __LWIP_INET_H__ - -#include "lwip/arch.h" - -#include "lwip/opt.h" -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" - -u16_t inet_chksum(void *data, u16_t len); -u16_t inet_chksum_pbuf(struct pbuf *p); -u16_t inet_chksum_pseudo(struct pbuf *p, - struct ip_addr *src, struct ip_addr *dest, - u8_t proto, u32_t proto_len); - -u32_t inet_addr(const char *cp); -s8_t inet_aton(const char *cp, struct in_addr *addr); - -#ifndef _MACHINE_ENDIAN_H_ -#ifndef _NETINET_IN_H -#ifndef _LINUX_BYTEORDER_GENERIC_H -u16_t htons(u16_t n); -u16_t ntohs(u16_t n); -u32_t htonl(u32_t n); -u32_t ntohl(u32_t n); -#endif /* _LINUX_BYTEORDER_GENERIC_H */ -#endif /* _NETINET_IN_H */ -#endif /* _MACHINE_ENDIAN_H_ */ - -#endif /* __LWIP_INET_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv6/lwip/ip.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv6/lwip/ip.h deleted file mode 100644 index f46bf9a80..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv6/lwip/ip.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_IP_H__ -#define __LWIP_IP_H__ - -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" - -#include "lwip/err.h" - -#define IP_HLEN 40 - -#define IP_PROTO_ICMP 58 -#define IP_PROTO_UDP 17 -#define IP_PROTO_UDPLITE 170 -#define IP_PROTO_TCP 6 - -/* This is passed as the destination address to ip_output_if (not - to ip_output), meaning that an IP header already is constructed - in the pbuf. This is used when TCP retransmits. */ -#ifdef IP_HDRINCL -#undef IP_HDRINCL -#endif /* IP_HDRINCL */ -#define IP_HDRINCL NULL - - -/* The IPv6 header. */ -struct ip_hdr { -#if BYTE_ORDER == LITTLE_ENDIAN - u8_t tclass1:4, v:4; - u8_t flow1:4, tclass2:4; -#else - u8_t v:4, tclass1:4; - u8_t tclass2:8, flow1:4; -#endif - u16_t flow2; - u16_t len; /* payload length */ - u8_t nexthdr; /* next header */ - u8_t hoplim; /* hop limit (TTL) */ - struct ip_addr src, dest; /* source and destination IP addresses */ -}; - -void ip_init(void); - -#include "lwip/netif.h" - -struct netif *ip_route(struct ip_addr *dest); - -void ip_input(struct pbuf *p, struct netif *inp); - -/* source and destination addresses in network byte order, please */ -err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t proto); - -err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t proto, - struct netif *netif); - -#if IP_DEBUG -void ip_debug_print(struct pbuf *p); -#endif /* IP_DEBUG */ - -#endif /* __LWIP_IP_H__ */ - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv6/lwip/ip_addr.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv6/lwip/ip_addr.h deleted file mode 100644 index db1f09060..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/ipv6/lwip/ip_addr.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_IP_ADDR_H__ -#define __LWIP_IP_ADDR_H__ - -#include "lwip/arch.h" - -#define IP_ADDR_ANY 0 - -struct ip_addr { - u32_t addr[4]; -}; - -#define IP6_ADDR(ipaddr, a,b,c,d,e,f,g,h) do { (ipaddr)->addr[0] = htonl((u32_t)((a & 0xffff) << 16) | (b & 0xffff)); \ - (ipaddr)->addr[1] = htonl(((c & 0xffff) << 16) | (d & 0xffff)); \ - (ipaddr)->addr[2] = htonl(((e & 0xffff) << 16) | (f & 0xffff)); \ - (ipaddr)->addr[3] = htonl(((g & 0xffff) << 16) | (h & 0xffff)); } while(0) - -u8_t ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2, - struct ip_addr *mask); -u8_t ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2); -void ip_addr_set(struct ip_addr *dest, struct ip_addr *src); -u8_t ip_addr_isany(struct ip_addr *addr); - - -#if IP_DEBUG -void ip_addr_debug_print(struct ip_addr *addr); -#endif /* IP_DEBUG */ - -#endif /* __LWIP_IP_ADDR_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/api.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/api.h deleted file mode 100644 index 7f0ad5966..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/api.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_API_H__ -#define __LWIP_API_H__ - -#include "lwip/opt.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" - -#include "lwip/ip.h" - -#include "lwip/raw.h" -#include "lwip/udp.h" -#include "lwip/tcp.h" - -#include "lwip/err.h" - -#define NETCONN_NOCOPY 0x00 -#define NETCONN_COPY 0x01 - -enum netconn_type { - NETCONN_TCP, - NETCONN_UDP, - NETCONN_UDPLITE, - NETCONN_UDPNOCHKSUM, - NETCONN_RAW -}; - -enum netconn_state { - NETCONN_NONE, - NETCONN_WRITE, - NETCONN_ACCEPT, - NETCONN_RECV, - NETCONN_CONNECT, - NETCONN_CLOSE -}; - -enum netconn_evt { - NETCONN_EVT_RCVPLUS, - NETCONN_EVT_RCVMINUS, - NETCONN_EVT_SENDPLUS, - NETCONN_EVT_SENDMINUS -}; - -struct netbuf { - struct pbuf *p, *ptr; - struct ip_addr *fromaddr; - u16_t fromport; - err_t err; -}; - -struct netconn { - enum netconn_type type; - enum netconn_state state; - union { - struct tcp_pcb *tcp; - struct udp_pcb *udp; - struct raw_pcb *raw; - } pcb; - err_t err; - sys_mbox_t mbox; - sys_mbox_t recvmbox; - sys_mbox_t acceptmbox; - sys_sem_t sem; - int socket; - u16_t recv_avail; - void (* callback)(struct netconn *, enum netconn_evt, u16_t len); -}; - -/* Network buffer functions: */ -struct netbuf * netbuf_new (void); -void netbuf_delete (struct netbuf *buf); -void * netbuf_alloc (struct netbuf *buf, u16_t size); -void netbuf_free (struct netbuf *buf); -void netbuf_ref (struct netbuf *buf, - void *dataptr, u16_t size); -void netbuf_chain (struct netbuf *head, - struct netbuf *tail); - -u16_t netbuf_len (struct netbuf *buf); -err_t netbuf_data (struct netbuf *buf, - void **dataptr, u16_t *len); -s8_t netbuf_next (struct netbuf *buf); -void netbuf_first (struct netbuf *buf); - -void netbuf_copy (struct netbuf *buf, - void *dataptr, u16_t len); -void netbuf_copy_partial(struct netbuf *buf, void *dataptr, - u16_t len, u16_t offset); -struct ip_addr * netbuf_fromaddr (struct netbuf *buf); -u16_t netbuf_fromport (struct netbuf *buf); - -/* Network connection functions: */ -struct netconn * netconn_new (enum netconn_type type); -struct -netconn *netconn_new_with_callback(enum netconn_type t, - void (*callback)(struct netconn *, enum netconn_evt, u16_t len)); -struct -netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto, - void (*callback)(struct netconn *, enum netconn_evt, u16_t len)); -err_t netconn_delete (struct netconn *conn); -enum netconn_type netconn_type (struct netconn *conn); -err_t netconn_peer (struct netconn *conn, - struct ip_addr *addr, - u16_t *port); -err_t netconn_addr (struct netconn *conn, - struct ip_addr **addr, - u16_t *port); -err_t netconn_bind (struct netconn *conn, - struct ip_addr *addr, - u16_t port); -err_t netconn_connect (struct netconn *conn, - struct ip_addr *addr, - u16_t port); -err_t netconn_disconnect (struct netconn *conn); -err_t netconn_listen (struct netconn *conn); -struct netconn * netconn_accept (struct netconn *conn); -struct netbuf * netconn_recv (struct netconn *conn); -err_t netconn_send (struct netconn *conn, - struct netbuf *buf); -err_t netconn_write (struct netconn *conn, - void *dataptr, u16_t size, - u8_t copy); -err_t netconn_close (struct netconn *conn); - -err_t netconn_err (struct netconn *conn); - -#endif /* __LWIP_API_H__ */ - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/api_msg.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/api_msg.h deleted file mode 100644 index 3fef3dd0c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/api_msg.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_API_MSG_H__ -#define __LWIP_API_MSG_H__ - -#include "lwip/opt.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" - -#include "lwip/ip.h" - -#include "lwip/udp.h" -#include "lwip/tcp.h" - -#include "lwip/api.h" - -enum api_msg_type { - API_MSG_NEWCONN, - API_MSG_DELCONN, - - API_MSG_BIND, - API_MSG_CONNECT, - API_MSG_DISCONNECT, - - API_MSG_LISTEN, - API_MSG_ACCEPT, - - API_MSG_SEND, - API_MSG_RECV, - API_MSG_WRITE, - - API_MSG_CLOSE, - - API_MSG_MAX -}; - -struct api_msg_msg { - struct netconn *conn; - enum netconn_type conntype; - union { - struct pbuf *p; - struct { - struct ip_addr *ipaddr; - u16_t port; - } bc; - struct { - void *dataptr; - u16_t len; - u8_t copy; - } w; - sys_mbox_t mbox; - u16_t len; - } msg; -}; - -struct api_msg { - enum api_msg_type type; - struct api_msg_msg msg; -}; - -void api_msg_input(struct api_msg *msg); -void api_msg_post(struct api_msg *msg); - -#endif /* __LWIP_API_MSG_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/arch.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/arch.h deleted file mode 100644 index e0d622a4b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/arch.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_ARCH_H__ -#define __LWIP_ARCH_H__ - -#ifndef LITTLE_ENDIAN -#define LITTLE_ENDIAN 1234 -#endif - -#ifndef BIG_ENDIAN -#define BIG_ENDIAN 4321 -#endif - -#include "arch/cc.h" - -#ifndef PACK_STRUCT_BEGIN -#define PACK_STRUCT_BEGIN -#endif /* PACK_STRUCT_BEGIN */ - -#ifndef PACK_STRUCT_END -#define PACK_STRUCT_END -#endif /* PACK_STRUCT_END */ - -#ifndef PACK_STRUCT_FIELD -#define PACK_STRUCT_FIELD(x) x -#endif /* PACK_STRUCT_FIELD */ - - - -#ifdef LWIP_PROVIDE_ERRNO - -#define EPERM 1 /* Operation not permitted */ -#define ENOENT 2 /* No such file or directory */ -#define ESRCH 3 /* No such process */ -#define EINTR 4 /* Interrupted system call */ -#define EIO 5 /* I/O error */ -#define ENXIO 6 /* No such device or address */ -#define E2BIG 7 /* Arg list too long */ -#define ENOEXEC 8 /* Exec format error */ -#define EBADF 9 /* Bad file number */ -#define ECHILD 10 /* No child processes */ -#define EAGAIN 11 /* Try again */ -#define ENOMEM 12 /* Out of memory */ -#define EACCES 13 /* Permission denied */ -#define EFAULT 14 /* Bad address */ -#define ENOTBLK 15 /* Block device required */ -#define EBUSY 16 /* Device or resource busy */ -#define EEXIST 17 /* File exists */ -#define EXDEV 18 /* Cross-device link */ -#define ENODEV 19 /* No such device */ -#define ENOTDIR 20 /* Not a directory */ -#define EISDIR 21 /* Is a directory */ -#define EINVAL 22 /* Invalid argument */ -#define ENFILE 23 /* File table overflow */ -#define EMFILE 24 /* Too many open files */ -#define ENOTTY 25 /* Not a typewriter */ -#define ETXTBSY 26 /* Text file busy */ -#define EFBIG 27 /* File too large */ -#define ENOSPC 28 /* No space left on device */ -#define ESPIPE 29 /* Illegal seek */ -#define EROFS 30 /* Read-only file system */ -#define EMLINK 31 /* Too many links */ -#define EPIPE 32 /* Broken pipe */ -#define EDOM 33 /* Math argument out of domain of func */ -#define ERANGE 34 /* Math result not representable */ -#define EDEADLK 35 /* Resource deadlock would occur */ -#define ENAMETOOLONG 36 /* File name too long */ -#define ENOLCK 37 /* No record locks available */ -#define ENOSYS 38 /* Function not implemented */ -#define ENOTEMPTY 39 /* Directory not empty */ -#define ELOOP 40 /* Too many symbolic links encountered */ -#define EWOULDBLOCK EAGAIN /* Operation would block */ -#define ENOMSG 42 /* No message of desired type */ -#define EIDRM 43 /* Identifier removed */ -#define ECHRNG 44 /* Channel number out of range */ -#define EL2NSYNC 45 /* Level 2 not synchronized */ -#define EL3HLT 46 /* Level 3 halted */ -#define EL3RST 47 /* Level 3 reset */ -#define ELNRNG 48 /* Link number out of range */ -#define EUNATCH 49 /* Protocol driver not attached */ -#define ENOCSI 50 /* No CSI structure available */ -#define EL2HLT 51 /* Level 2 halted */ -#define EBADE 52 /* Invalid exchange */ -#define EBADR 53 /* Invalid request descriptor */ -#define EXFULL 54 /* Exchange full */ -#define ENOANO 55 /* No anode */ -#define EBADRQC 56 /* Invalid request code */ -#define EBADSLT 57 /* Invalid slot */ - -#define EDEADLOCK EDEADLK - -#define EBFONT 59 /* Bad font file format */ -#define ENOSTR 60 /* Device not a stream */ -#define ENODATA 61 /* No data available */ -#define ETIME 62 /* Timer expired */ -#define ENOSR 63 /* Out of streams resources */ -#define ENONET 64 /* Machine is not on the network */ -#define ENOPKG 65 /* Package not installed */ -#define EREMOTE 66 /* Object is remote */ -#define ENOLINK 67 /* Link has been severed */ -#define EADV 68 /* Advertise error */ -#define ESRMNT 69 /* Srmount error */ -#define ECOMM 70 /* Communication error on send */ -#define EPROTO 71 /* Protocol error */ -#define EMULTIHOP 72 /* Multihop attempted */ -#define EDOTDOT 73 /* RFS specific error */ -#define EBADMSG 74 /* Not a data message */ -#define EOVERFLOW 75 /* Value too large for defined data type */ -#define ENOTUNIQ 76 /* Name not unique on network */ -#define EBADFD 77 /* File descriptor in bad state */ -#define EREMCHG 78 /* Remote address changed */ -#define ELIBACC 79 /* Can not access a needed shared library */ -#define ELIBBAD 80 /* Accessing a corrupted shared library */ -#define ELIBSCN 81 /* .lib section in a.out corrupted */ -#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ -#define ELIBEXEC 83 /* Cannot exec a shared library directly */ -#define EILSEQ 84 /* Illegal byte sequence */ -#define ERESTART 85 /* Interrupted system call should be restarted */ -#define ESTRPIPE 86 /* Streams pipe error */ -#define EUSERS 87 /* Too many users */ -#define ENOTSOCK 88 /* Socket operation on non-socket */ -#define EDESTADDRREQ 89 /* Destination address required */ -#define EMSGSIZE 90 /* Message too long */ -#define EPROTOTYPE 91 /* Protocol wrong type for socket */ -#define ENOPROTOOPT 92 /* Protocol not available */ -#define EPROTONOSUPPORT 93 /* Protocol not supported */ -#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ -#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ -#define EPFNOSUPPORT 96 /* Protocol family not supported */ -#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ -#define EADDRINUSE 98 /* Address already in use */ -#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ -#define ENETDOWN 100 /* Network is down */ -#define ENETUNREACH 101 /* Network is unreachable */ -#define ENETRESET 102 /* Network dropped connection because of reset */ -#define ECONNABORTED 103 /* Software caused connection abort */ -#define ECONNRESET 104 /* Connection reset by peer */ -#define ENOBUFS 105 /* No buffer space available */ -#define EISCONN 106 /* Transport endpoint is already connected */ -#define ENOTCONN 107 /* Transport endpoint is not connected */ -#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ -#define ETOOMANYREFS 109 /* Too many references: cannot splice */ -#define ETIMEDOUT 110 /* Connection timed out */ -#define ECONNREFUSED 111 /* Connection refused */ -#define EHOSTDOWN 112 /* Host is down */ -#define EHOSTUNREACH 113 /* No route to host */ -#define EALREADY 114 /* Operation already in progress */ -#define EINPROGRESS 115 /* Operation now in progress */ -#define ESTALE 116 /* Stale NFS file handle */ -#define EUCLEAN 117 /* Structure needs cleaning */ -#define ENOTNAM 118 /* Not a XENIX named type file */ -#define ENAVAIL 119 /* No XENIX semaphores available */ -#define EISNAM 120 /* Is a named type file */ -#define EREMOTEIO 121 /* Remote I/O error */ -#define EDQUOT 122 /* Quota exceeded */ - -#define ENOMEDIUM 123 /* No medium found */ -#define EMEDIUMTYPE 124 /* Wrong medium type */ - - -#define ENSROK 0 /* DNS server returned answer with no data */ -#define ENSRNODATA 160 /* DNS server returned answer with no data */ -#define ENSRFORMERR 161 /* DNS server claims query was misformatted */ -#define ENSRSERVFAIL 162 /* DNS server returned general failure */ -#define ENSRNOTFOUND 163 /* Domain name not found */ -#define ENSRNOTIMP 164 /* DNS server does not implement requested operation */ -#define ENSRREFUSED 165 /* DNS server refused query */ -#define ENSRBADQUERY 166 /* Misformatted DNS query */ -#define ENSRBADNAME 167 /* Misformatted domain name */ -#define ENSRBADFAMILY 168 /* Unsupported address family */ -#define ENSRBADRESP 169 /* Misformatted DNS reply */ -#define ENSRCONNREFUSED 170 /* Could not contact DNS servers */ -#define ENSRTIMEOUT 171 /* Timeout while contacting DNS servers */ -#define ENSROF 172 /* End of file */ -#define ENSRFILE 173 /* Error reading file */ -#define ENSRNOMEM 174 /* Out of memory */ -#define ENSRDESTRUCTION 175 /* Application terminated lookup */ -#define ENSRQUERYDOMAINTOOLONG 176 /* Domain name is too long */ -#define ENSRCNAMELOOP 177 /* Domain name is too long */ - -#ifndef errno -extern int errno; -#endif - -#endif /* LWIP_PROVIDE_ERRNO */ - -#endif /* __LWIP_ARCH_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/debug.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/debug.h deleted file mode 100644 index 8f63a7b62..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/debug.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_DEBUG_H__ -#define __LWIP_DEBUG_H__ - -#include "arch/cc.h" - -/** lower two bits indicate debug level - * - 0 off - * - 1 warning - * - 2 serious - * - 3 severe - */ - -#define DBG_LEVEL_OFF 0 -#define DBG_LEVEL_WARNING 1 /* bad checksums, dropped packets, ... */ -#define DBG_LEVEL_SERIOUS 2 /* memory allocation failures, ... */ -#define DBG_LEVEL_SEVERE 3 /* */ -#define DBG_MASK_LEVEL 3 - -/** flag for LWIP_DEBUGF to enable that debug message */ -#define DBG_ON 0x80U -/** flag for LWIP_DEBUGF to disable that debug message */ -#define DBG_OFF 0x00U - -/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */ -#define DBG_TRACE 0x40U -/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */ -#define DBG_STATE 0x20U -/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */ -#define DBG_FRESH 0x10U -/** flag for LWIP_DEBUGF to halt after printing this debug message */ -#define DBG_HALT 0x08U - -#ifndef LWIP_NOASSERT -# define LWIP_ASSERT(x,y) do { if(!(y)) LWIP_PLATFORM_ASSERT(x); } while(0) -#else -# define LWIP_ASSERT(x,y) -#endif - -#ifdef LWIP_DEBUG -/** print debug message only if debug message type is enabled... - * AND is of correct type AND is at least DBG_LEVEL - */ -# define LWIP_DEBUGF(debug,x) do { if (((debug) & DBG_ON) && ((debug) & DBG_TYPES_ON) && ((s16_t)((debug) & DBG_MASK_LEVEL) >= DBG_MIN_LEVEL)) { LWIP_PLATFORM_DIAG(x); if ((debug) & DBG_HALT) while(1); } } while(0) -# define LWIP_ERROR(x) do { LWIP_PLATFORM_DIAG(x); } while(0) -#else /* LWIP_DEBUG */ -# define LWIP_DEBUGF(debug,x) -# define LWIP_ERROR(x) -#endif /* LWIP_DEBUG */ - -#endif /* __LWIP_DEBUG_H__ */ - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/def.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/def.h deleted file mode 100644 index eba9b8774..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/def.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_DEF_H__ -#define __LWIP_DEF_H__ - -/* this might define NULL already */ -#include "arch/cc.h" - -#define LWIP_MAX(x , y) (x) > (y) ? (x) : (y) -#define LWIP_MIN(x , y) (x) < (y) ? (x) : (y) - -#ifndef NULL -#define NULL ((void *)0) -#endif - - -#endif /* __LWIP_DEF_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/dhcp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/dhcp.h deleted file mode 100644 index bfe753f26..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/dhcp.h +++ /dev/null @@ -1,223 +0,0 @@ -/** @file - */ - -#ifndef __LWIP_DHCP_H__ -#define __LWIP_DHCP_H__ - -#include "lwip/opt.h" -#include "lwip/netif.h" -#include "lwip/udp.h" - -/** period (in seconds) of the application calling dhcp_coarse_tmr() */ -#define DHCP_COARSE_TIMER_SECS 60 -/** period (in milliseconds) of the application calling dhcp_fine_tmr() */ -#define DHCP_FINE_TIMER_MSECS 500 - -struct dhcp -{ - /** current DHCP state machine state */ - u8_t state; - /** retries of current request */ - u8_t tries; - /** transaction identifier of last sent request */ - u32_t xid; - /** our connection to the DHCP server */ - struct udp_pcb *pcb; - /** (first) pbuf of incoming msg */ - struct pbuf *p; - /** incoming msg */ - struct dhcp_msg *msg_in; - /** incoming msg options */ - struct dhcp_msg *options_in; - /** ingoing msg options length */ - u16_t options_in_len; - - struct pbuf *p_out; /* pbuf of outcoming msg */ - struct dhcp_msg *msg_out; /* outgoing msg */ - u16_t options_out_len; /* outgoing msg options length */ - u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */ - u16_t t1_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */ - u16_t t2_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */ - struct ip_addr server_ip_addr; /* dhcp server address that offered this lease */ - struct ip_addr offered_ip_addr; - struct ip_addr offered_sn_mask; - struct ip_addr offered_gw_addr; - struct ip_addr offered_bc_addr; -#define DHCP_MAX_DNS 2 - u32_t dns_count; /* actual number of DNS servers obtained */ - struct ip_addr offered_dns_addr[DHCP_MAX_DNS]; /* DNS server addresses */ - - u32_t offered_t0_lease; /* lease period (in seconds) */ - u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */ - u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period) */ -/** Patch #1308 - * TODO: See dhcp.c "TODO"s - */ -#if 0 - struct ip_addr offered_si_addr; - u8_t *boot_file_name; -#endif -}; - -/* MUST be compiled with "pack structs" or equivalent! */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -/** minimum set of fields of any DHCP message */ -struct dhcp_msg -{ - PACK_STRUCT_FIELD(u8_t op); - PACK_STRUCT_FIELD(u8_t htype); - PACK_STRUCT_FIELD(u8_t hlen); - PACK_STRUCT_FIELD(u8_t hops); - PACK_STRUCT_FIELD(u32_t xid); - PACK_STRUCT_FIELD(u16_t secs); - PACK_STRUCT_FIELD(u16_t flags); - PACK_STRUCT_FIELD(struct ip_addr ciaddr); - PACK_STRUCT_FIELD(struct ip_addr yiaddr); - PACK_STRUCT_FIELD(struct ip_addr siaddr); - PACK_STRUCT_FIELD(struct ip_addr giaddr); -#define DHCP_CHADDR_LEN 16U - PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]); -#define DHCP_SNAME_LEN 64U - PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]); -#define DHCP_FILE_LEN 128U - PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]); - PACK_STRUCT_FIELD(u32_t cookie); -#define DHCP_MIN_OPTIONS_LEN 68U -/** make sure user does not configure this too small */ -#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN)) -# undef DHCP_OPTIONS_LEN -#endif -/** allow this to be configured in lwipopts.h, but not too small */ -#if (!defined(DHCP_OPTIONS_LEN)) -/** set this to be sufficient for your options in outgoing DHCP msgs */ -# define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN -#endif - PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/** start DHCP configuration */ -err_t dhcp_start(struct netif *netif); -/** enforce early lease renewal (not needed normally)*/ -err_t dhcp_renew(struct netif *netif); -/** release the DHCP lease, usually called before dhcp_stop()*/ -err_t dhcp_release(struct netif *netif); -/** stop DHCP configuration */ -void dhcp_stop(struct netif *netif); -/** inform server of our manual IP address */ -void dhcp_inform(struct netif *netif); - -/** if enabled, check whether the offered IP address is not in use, using ARP */ -#if DHCP_DOES_ARP_CHECK -void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr); -#endif - -/** to be called every minute */ -void dhcp_coarse_tmr(void); -/** to be called every half second */ -void dhcp_fine_tmr(void); - -/** DHCP message item offsets and length */ -#define DHCP_MSG_OFS (UDP_DATA_OFS) - #define DHCP_OP_OFS (DHCP_MSG_OFS + 0) - #define DHCP_HTYPE_OFS (DHCP_MSG_OFS + 1) - #define DHCP_HLEN_OFS (DHCP_MSG_OFS + 2) - #define DHCP_HOPS_OFS (DHCP_MSG_OFS + 3) - #define DHCP_XID_OFS (DHCP_MSG_OFS + 4) - #define DHCP_SECS_OFS (DHCP_MSG_OFS + 8) - #define DHCP_FLAGS_OFS (DHCP_MSG_OFS + 10) - #define DHCP_CIADDR_OFS (DHCP_MSG_OFS + 12) - #define DHCP_YIADDR_OFS (DHCP_MSG_OFS + 16) - #define DHCP_SIADDR_OFS (DHCP_MSG_OFS + 20) - #define DHCP_GIADDR_OFS (DHCP_MSG_OFS + 24) - #define DHCP_CHADDR_OFS (DHCP_MSG_OFS + 28) - #define DHCP_SNAME_OFS (DHCP_MSG_OFS + 44) - #define DHCP_FILE_OFS (DHCP_MSG_OFS + 108) -#define DHCP_MSG_LEN 236 - -#define DHCP_COOKIE_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN) -#define DHCP_OPTIONS_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN + 4) - -#define DHCP_CLIENT_PORT 68 -#define DHCP_SERVER_PORT 67 - -/** DHCP client states */ -#define DHCP_REQUESTING 1 -#define DHCP_INIT 2 -#define DHCP_REBOOTING 3 -#define DHCP_REBINDING 4 -#define DHCP_RENEWING 5 -#define DHCP_SELECTING 6 -#define DHCP_INFORMING 7 -#define DHCP_CHECKING 8 -#define DHCP_PERMANENT 9 -#define DHCP_BOUND 10 -/** not yet implemented #define DHCP_RELEASING 11 */ -#define DHCP_BACKING_OFF 12 -#define DHCP_OFF 13 - -#define DHCP_BOOTREQUEST 1 -#define DHCP_BOOTREPLY 2 - -#define DHCP_DISCOVER 1 -#define DHCP_OFFER 2 -#define DHCP_REQUEST 3 -#define DHCP_DECLINE 4 -#define DHCP_ACK 5 -#define DHCP_NAK 6 -#define DHCP_RELEASE 7 -#define DHCP_INFORM 8 - -#define DHCP_HTYPE_ETH 1 - -#define DHCP_HLEN_ETH 6 - -#define DHCP_BROADCAST_FLAG 15 -#define DHCP_BROADCAST_MASK (1 << DHCP_FLAG_BROADCAST) - -/** BootP options */ -#define DHCP_OPTION_PAD 0 -#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */ -#define DHCP_OPTION_ROUTER 3 -#define DHCP_OPTION_DNS_SERVER 6 -#define DHCP_OPTION_HOSTNAME 12 -#define DHCP_OPTION_IP_TTL 23 -#define DHCP_OPTION_MTU 26 -#define DHCP_OPTION_BROADCAST 28 -#define DHCP_OPTION_TCP_TTL 37 -#define DHCP_OPTION_END 255 - -/** DHCP options */ -#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */ -#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */ -#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */ - -#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */ -#define DHCP_OPTION_MESSAGE_TYPE_LEN 1 - - -#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */ -#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */ - -#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */ -#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2 - -#define DHCP_OPTION_T1 58 /* T1 renewal time */ -#define DHCP_OPTION_T2 59 /* T2 rebinding time */ -#define DHCP_OPTION_CLIENT_ID 61 -#define DHCP_OPTION_TFTP_SERVERNAME 66 -#define DHCP_OPTION_BOOTFILE 67 - -/** possible combinations of overloading the file and sname fields with options */ -#define DHCP_OVERLOAD_NONE 0 -#define DHCP_OVERLOAD_FILE 1 -#define DHCP_OVERLOAD_SNAME 2 -#define DHCP_OVERLOAD_SNAME_FILE 3 - -#endif /*__LWIP_DHCP_H__*/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/err.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/err.h deleted file mode 100644 index c92cb26d7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/err.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_ERR_H__ -#define __LWIP_ERR_H__ - -#include "lwip/opt.h" - -#include "arch/cc.h" - -typedef s8_t err_t; - -/* Definitions for error constants. */ - -#define ERR_OK 0 /* No error, everything OK. */ -#define ERR_MEM -1 /* Out of memory error. */ -#define ERR_BUF -2 /* Buffer error. */ - - -#define ERR_ABRT -3 /* Connection aborted. */ -#define ERR_RST -4 /* Connection reset. */ -#define ERR_CLSD -5 /* Connection closed. */ -#define ERR_CONN -6 /* Not connected. */ - -#define ERR_VAL -7 /* Illegal value. */ - -#define ERR_ARG -8 /* Illegal argument. */ - -#define ERR_RTE -9 /* Routing problem. */ - -#define ERR_USE -10 /* Address in use. */ - -#define ERR_IF -11 /* Low-level netif error */ -#define ERR_ISCONN -12 /* Already connected. */ - - -#ifdef LWIP_DEBUG -extern char *lwip_strerr(err_t err); -#else -#define lwip_strerr(x) "" -#endif /* LWIP_DEBUG */ -#endif /* __LWIP_ERR_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/mem.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/mem.h deleted file mode 100644 index ee6fea7d8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/mem.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_MEM_H__ -#define __LWIP_MEM_H__ - -#include "lwip/opt.h" -#include "lwip/arch.h" - -#if MEM_SIZE > 64000l -typedef u32_t mem_size_t; -#else -typedef u16_t mem_size_t; -#endif /* MEM_SIZE > 64000 */ - - -void mem_init(void); - -void *mem_malloc(mem_size_t size); -void mem_free(void *mem); -void *mem_realloc(void *mem, mem_size_t size); -void *mem_reallocm(void *mem, mem_size_t size); - -#ifndef MEM_ALIGN_SIZE -#define MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1)) -#endif - -#ifndef MEM_ALIGN -#define MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1))) -#endif - -#endif /* __LWIP_MEM_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/memp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/memp.h deleted file mode 100644 index 1cd46fa3f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/memp.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef __LWIP_MEMP_H__ -#define __LWIP_MEMP_H__ - -#include "lwip/opt.h" - -typedef enum { - MEMP_PBUF, - MEMP_RAW_PCB, - MEMP_UDP_PCB, - MEMP_TCP_PCB, - MEMP_TCP_PCB_LISTEN, - MEMP_TCP_SEG, - - MEMP_NETBUF, - MEMP_NETCONN, - MEMP_API_MSG, - MEMP_TCPIP_MSG, - - MEMP_SYS_TIMEOUT, - - MEMP_MAX -} memp_t; - -void memp_init(void); - -void *memp_malloc(memp_t type); -void *memp_realloc(memp_t fromtype, memp_t totype, void *mem); -void memp_free(memp_t type, void *mem); - -#endif /* __LWIP_MEMP_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/netif.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/netif.h deleted file mode 100644 index ff50c6f9c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/netif.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_NETIF_H__ -#define __LWIP_NETIF_H__ - -#include "lwip/opt.h" - -#include "lwip/err.h" - -#include "lwip/ip_addr.h" - -#include "lwip/inet.h" -#include "lwip/pbuf.h" -#if LWIP_DHCP -# include "lwip/dhcp.h" -#endif - -/** must be the maximum of all used hardware address lengths - across all types of interfaces in use */ -#define NETIF_MAX_HWADDR_LEN 6U - -/** TODO: define the use (where, when, whom) of netif flags */ - -/** whether the network interface is 'up'. this is - * a software flag used to control whether this network - * interface is enabled and processes traffic. - */ -#define NETIF_FLAG_UP 0x1U -/** if set, the netif has broadcast capability */ -#define NETIF_FLAG_BROADCAST 0x2U -/** if set, the netif is one end of a point-to-point connection */ -#define NETIF_FLAG_POINTTOPOINT 0x4U -/** if set, the interface is configured using DHCP */ -#define NETIF_FLAG_DHCP 0x08U -/** if set, the interface has an active link - * (set by the network interface driver) */ -#define NETIF_FLAG_LINK_UP 0x10U - -/** Generic data structure used for all lwIP network interfaces. - * The following fields should be filled in by the initialization - * function for the device driver: hwaddr_len, hwaddr[], mtu, flags */ - -struct netif { - /** pointer to next in linked list */ - struct netif *next; - - /** IP address configuration in network byte order */ - struct ip_addr ip_addr; - struct ip_addr netmask; - struct ip_addr gw; - - /** This function is called by the network device driver - * to pass a packet up the TCP/IP stack. */ - err_t (* input)(struct pbuf *p, struct netif *inp); - /** This function is called by the IP module when it wants - * to send a packet on the interface. This function typically - * first resolves the hardware address, then sends the packet. */ - err_t (* output)(struct netif *netif, struct pbuf *p, - struct ip_addr *ipaddr); - /** This function is called by the ARP module when it wants - * to send a packet on the interface. This function outputs - * the pbuf as-is on the link medium. */ - err_t (* linkoutput)(struct netif *netif, struct pbuf *p); - /** This field can be set by the device driver and could point - * to state information for the device. */ - void *state; -#if LWIP_DHCP - /** the DHCP client state information for this netif */ - struct dhcp *dhcp; -#endif - /** number of bytes used in hwaddr */ - u8_t hwaddr_len; - /** link level hardware address of this interface */ - u8_t hwaddr[NETIF_MAX_HWADDR_LEN]; - /** maximum transfer unit (in bytes) */ - u16_t mtu; - /** flags (see NETIF_FLAG_ above) */ - u8_t flags; - /** link type */ - u8_t link_type; - /** descriptive abbreviation */ - char name[2]; - /** number of this interface */ - u8_t num; -}; - -/** The list of network interfaces. */ -extern struct netif *netif_list; -/** The default network interface. */ -extern struct netif *netif_default; - -/* netif_init() must be called first. */ -void netif_init(void); - -struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask, - struct ip_addr *gw, - void *state, - err_t (* init)(struct netif *netif), - err_t (* input)(struct pbuf *p, struct netif *netif)); - -void -netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask, - struct ip_addr *gw); -void netif_remove(struct netif * netif); - -/* Returns a network interface given its name. The name is of the form - "et0", where the first two letters are the "name" field in the - netif structure, and the digit is in the num field in the same - structure. */ -struct netif *netif_find(char *name); - -void netif_set_default(struct netif *netif); - -void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr); -void netif_set_netmask(struct netif *netif, struct ip_addr *netmast); -void netif_set_gw(struct netif *netif, struct ip_addr *gw); -void netif_set_up(struct netif *netif); -void netif_set_down(struct netif *netif); -u8_t netif_is_up(struct netif *netif); - -#endif /* __LWIP_NETIF_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/opt.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/opt.h deleted file mode 100644 index 45636cb24..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/opt.h +++ /dev/null @@ -1,671 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_OPT_H__ -#define __LWIP_OPT_H__ - -/* Include user defined options first */ -#include "lwipopts.h" -#include "lwip/debug.h" - -/* Define default values for unconfigured parameters. */ - -/* Platform specific locking */ - -/* - * enable SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection - * for certain critical regions during buffer allocation, deallocation and memory - * allocation and deallocation. - */ -#ifndef SYS_LIGHTWEIGHT_PROT -#define SYS_LIGHTWEIGHT_PROT 0 -#endif - -#ifndef NO_SYS -#define NO_SYS 0 -#endif -/* ---------- Memory options ---------- */ -/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which - lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2 - byte alignment -> define MEM_ALIGNMENT to 2. */ - -#ifndef MEM_ALIGNMENT -#define MEM_ALIGNMENT 1 -#endif - -/* MEM_SIZE: the size of the heap memory. If the application will send -a lot of data that needs to be copied, this should be set high. */ -#ifndef MEM_SIZE -#define MEM_SIZE 1600 -#endif - -#ifndef MEMP_SANITY_CHECK -#define MEMP_SANITY_CHECK 0 -#endif - -/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application - sends a lot of data out of ROM (or other static memory), this - should be set high. */ -#ifndef MEMP_NUM_PBUF -#define MEMP_NUM_PBUF 16 -#endif - -/* Number of raw connection PCBs */ -#ifndef MEMP_NUM_RAW_PCB -#define MEMP_NUM_RAW_PCB 4 -#endif - -/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One - per active UDP "connection". */ -#ifndef MEMP_NUM_UDP_PCB -#define MEMP_NUM_UDP_PCB 4 -#endif -/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP - connections. */ -#ifndef MEMP_NUM_TCP_PCB -#define MEMP_NUM_TCP_PCB 5 -#endif -/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP - connections. */ -#ifndef MEMP_NUM_TCP_PCB_LISTEN -#define MEMP_NUM_TCP_PCB_LISTEN 8 -#endif -/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP - segments. */ -#ifndef MEMP_NUM_TCP_SEG -#define MEMP_NUM_TCP_SEG 16 -#endif -/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active - timeouts. */ -#ifndef MEMP_NUM_SYS_TIMEOUT -#define MEMP_NUM_SYS_TIMEOUT 3 -#endif - -/* The following four are used only with the sequential API and can be - set to 0 if the application only will use the raw API. */ -/* MEMP_NUM_NETBUF: the number of struct netbufs. */ -#ifndef MEMP_NUM_NETBUF -#define MEMP_NUM_NETBUF 2 -#endif -/* MEMP_NUM_NETCONN: the number of struct netconns. */ -#ifndef MEMP_NUM_NETCONN -#define MEMP_NUM_NETCONN 4 -#endif -/* MEMP_NUM_APIMSG: the number of struct api_msg, used for - communication between the TCP/IP stack and the sequential - programs. */ -#ifndef MEMP_NUM_API_MSG -#define MEMP_NUM_API_MSG 8 -#endif -/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used - for sequential API communication and incoming packets. Used in - src/api/tcpip.c. */ -#ifndef MEMP_NUM_TCPIP_MSG -#define MEMP_NUM_TCPIP_MSG 8 -#endif - -/* ---------- Pbuf options ---------- */ -/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ - -#ifndef PBUF_POOL_SIZE -#define PBUF_POOL_SIZE 16 -#endif - -/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */ - -#ifndef PBUF_POOL_BUFSIZE -#define PBUF_POOL_BUFSIZE 128 -#endif - -/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a - link level header. Defaults to 14 for Ethernet. */ - -#ifndef PBUF_LINK_HLEN -#define PBUF_LINK_HLEN 14 -#endif - - - -/* ---------- ARP options ---------- */ - -/** Number of active hardware address, IP address pairs cached */ -#ifndef ARP_TABLE_SIZE -#define ARP_TABLE_SIZE 10 -#endif - -/** - * If enabled, outgoing packets are queued during hardware address - * resolution. - * - * This feature has not stabilized yet. Single-packet queueing is - * believed to be stable, multi-packet queueing is believed to - * clash with the TCP segment queueing. - * - * As multi-packet-queueing is currently disabled, enabling this - * _should_ work, but we need your testing feedback on lwip-users. - * - */ -#ifndef ARP_QUEUEING -#define ARP_QUEUEING 1 -#endif - -/* This option is deprecated */ -#ifdef ETHARP_QUEUE_FIRST -#error ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h. -#endif - -/* This option is removed to comply with the ARP standard */ -#ifdef ETHARP_ALWAYS_INSERT -#error ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h. -#endif - -/* ---------- IP options ---------- */ -/* Define IP_FORWARD to 1 if you wish to have the ability to forward - IP packets across network interfaces. If you are going to run lwIP - on a device with only one network interface, define this to 0. */ -#ifndef IP_FORWARD -#define IP_FORWARD 0 -#endif - -/* If defined to 1, IP options are allowed (but not parsed). If - defined to 0, all packets with IP options are dropped. */ -#ifndef IP_OPTIONS -#define IP_OPTIONS 1 -#endif - -/** IP reassembly and segmentation. Even if they both deal with IP - * fragments, note that these are orthogonal, one dealing with incoming - * packets, the other with outgoing packets - */ - -/** Reassemble incoming fragmented IP packets */ -#ifndef IP_REASSEMBLY -#define IP_REASSEMBLY 1 -#endif - -/** Fragment outgoing IP packets if their size exceeds MTU */ -#ifndef IP_FRAG -#define IP_FRAG 1 -#endif - -/* ---------- ICMP options ---------- */ - -#ifndef ICMP_TTL -#define ICMP_TTL 255 -#endif - -/* ---------- RAW options ---------- */ - -#ifndef LWIP_RAW -#define LWIP_RAW 1 -#endif - -#ifndef RAW_TTL -#define RAW_TTL 255 -#endif - -/* ---------- DHCP options ---------- */ - -#ifndef LWIP_DHCP -#define LWIP_DHCP 0 -#endif - -/* 1 if you want to do an ARP check on the offered address - (recommended). */ -#ifndef DHCP_DOES_ARP_CHECK -#define DHCP_DOES_ARP_CHECK 1 -#endif - -/* ---------- UDP options ---------- */ -#ifndef LWIP_UDP -#define LWIP_UDP 1 -#endif - -#ifndef UDP_TTL -#define UDP_TTL 255 -#endif - -/* ---------- TCP options ---------- */ -#ifndef LWIP_TCP -#define LWIP_TCP 1 -#endif - -#ifndef TCP_TTL -#define TCP_TTL 255 -#endif - -#ifndef TCP_WND -#define TCP_WND 2048 -#endif - -#ifndef TCP_MAXRTX -#define TCP_MAXRTX 12 -#endif - -#ifndef TCP_SYNMAXRTX -#define TCP_SYNMAXRTX 6 -#endif - - -/* Controls if TCP should queue segments that arrive out of - order. Define to 0 if your device is low on memory. */ -#ifndef TCP_QUEUE_OOSEQ -#define TCP_QUEUE_OOSEQ 1 -#endif - -/* TCP Maximum segment size. */ -#ifndef TCP_MSS -#define TCP_MSS 128 /* A *very* conservative default. */ -#endif - -/* TCP sender buffer space (bytes). */ -#ifndef TCP_SND_BUF -#define TCP_SND_BUF 256 -#endif - -/* TCP sender buffer space (pbufs). This must be at least = 2 * - TCP_SND_BUF/TCP_MSS for things to work. */ -#ifndef TCP_SND_QUEUELEN -#define TCP_SND_QUEUELEN 4 * TCP_SND_BUF/TCP_MSS -#endif - - -/* Maximum number of retransmissions of data segments. */ - -/* Maximum number of retransmissions of SYN segments. */ - -/* TCP writable space (bytes). This must be less than or equal - to TCP_SND_BUF. It is the amount of space which must be - available in the tcp snd_buf for select to return writable */ -#ifndef TCP_SNDLOWAT -#define TCP_SNDLOWAT TCP_SND_BUF/2 -#endif - -/* Support loop interface (127.0.0.1) */ -#ifndef LWIP_HAVE_LOOPIF -#define LWIP_HAVE_LOOPIF 0 -#endif - -#ifndef LWIP_EVENT_API -#define LWIP_EVENT_API 0 -#define LWIP_CALLBACK_API 1 -#else -#define LWIP_EVENT_API 1 -#define LWIP_CALLBACK_API 0 -#endif - -#ifndef LWIP_COMPAT_SOCKETS -#define LWIP_COMPAT_SOCKETS 1 -#endif - - -#ifndef TCPIP_THREAD_PRIO -#define TCPIP_THREAD_PRIO 1 -#endif - -#ifndef SLIPIF_THREAD_PRIO -#define SLIPIF_THREAD_PRIO 1 -#endif - -#ifndef PPP_THREAD_PRIO -#define PPP_THREAD_PRIO 1 -#endif - -#ifndef DEFAULT_THREAD_PRIO -#define DEFAULT_THREAD_PRIO 1 -#endif - - -/* ---------- Socket Options ---------- */ -/* Enable SO_REUSEADDR and SO_REUSEPORT options */ -#ifdef SO_REUSE -/* I removed the lot since this was an ugly hack. It broke the raw-API. - It also came with many ugly goto's, Christiaan Simons. */ -#error "SO_REUSE currently unavailable, this was a hack" -#endif - - -/* ---------- Statistics options ---------- */ -#ifndef LWIP_STATS -#define LWIP_STATS 1 -#endif - -#if LWIP_STATS - -#ifndef LWIP_STATS_DISPLAY -#define LWIP_STATS_DISPLAY 0 -#endif - -#ifndef LINK_STATS -#define LINK_STATS 1 -#endif - -#ifndef IP_STATS -#define IP_STATS 1 -#endif - -#ifndef IPFRAG_STATS -#define IPFRAG_STATS 1 -#endif - -#ifndef ICMP_STATS -#define ICMP_STATS 1 -#endif - -#ifndef UDP_STATS -#define UDP_STATS 1 -#endif - -#ifndef TCP_STATS -#define TCP_STATS 1 -#endif - -#ifndef MEM_STATS -#define MEM_STATS 1 -#endif - -#ifndef MEMP_STATS -#define MEMP_STATS 1 -#endif - -#ifndef PBUF_STATS -#define PBUF_STATS 1 -#endif - -#ifndef SYS_STATS -#define SYS_STATS 1 -#endif - -#ifndef RAW_STATS -#define RAW_STATS 0 -#endif - -#else - -#define LINK_STATS 0 -#define IP_STATS 0 -#define IPFRAG_STATS 0 -#define ICMP_STATS 0 -#define UDP_STATS 0 -#define TCP_STATS 0 -#define MEM_STATS 0 -#define MEMP_STATS 0 -#define PBUF_STATS 0 -#define SYS_STATS 0 -#define RAW_STATS 0 -#define LWIP_STATS_DISPLAY 0 - -#endif /* LWIP_STATS */ - -/* ---------- PPP options ---------- */ - -#ifndef PPP_SUPPORT -#define PPP_SUPPORT 0 /* Set for PPP */ -#endif - -#if PPP_SUPPORT - -#define NUM_PPP 1 /* Max PPP sessions. */ - - - -#ifndef PAP_SUPPORT -#define PAP_SUPPORT 0 /* Set for PAP. */ -#endif - -#ifndef CHAP_SUPPORT -#define CHAP_SUPPORT 0 /* Set for CHAP. */ -#endif - -#define MSCHAP_SUPPORT 0 /* Set for MSCHAP (NOT FUNCTIONAL!) */ -#define CBCP_SUPPORT 0 /* Set for CBCP (NOT FUNCTIONAL!) */ -#define CCP_SUPPORT 0 /* Set for CCP (NOT FUNCTIONAL!) */ - -#ifndef VJ_SUPPORT -#define VJ_SUPPORT 0 /* Set for VJ header compression. */ -#endif - -#ifndef MD5_SUPPORT -#define MD5_SUPPORT 0 /* Set for MD5 (see also CHAP) */ -#endif - - -/* - * Timeouts. - */ -#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ -#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ -#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ -#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ - -#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ -#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ - -#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ -#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ - - -/* Interval in seconds between keepalive echo requests, 0 to disable. */ -#if 1 -#define LCP_ECHOINTERVAL 0 -#else -#define LCP_ECHOINTERVAL 10 -#endif - -/* Number of unanswered echo requests before failure. */ -#define LCP_MAXECHOFAILS 3 - -/* Max Xmit idle time (in jiffies) before resend flag char. */ -#define PPP_MAXIDLEFLAG 100 - -/* - * Packet sizes - * - * Note - lcp shouldn't be allowed to negotiate stuff outside these - * limits. See lcp.h in the pppd directory. - * (XXX - these constants should simply be shared by lcp.c instead - * of living in lcp.h) - */ -#define PPP_MTU 1500 /* Default MTU (size of Info field) */ -#if 0 -#define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) -#else -#define PPP_MAXMTU 1500 /* Largest MTU we allow */ -#endif -#define PPP_MINMTU 64 -#define PPP_MRU 1500 /* default MRU = max length of info field */ -#define PPP_MAXMRU 1500 /* Largest MRU we allow */ -#define PPP_DEFMRU 296 /* Try for this */ -#define PPP_MINMRU 128 /* No MRUs below this */ - - -#define MAXNAMELEN 256 /* max length of hostname or name for auth */ -#define MAXSECRETLEN 256 /* max length of password or secret */ - -#endif /* PPP_SUPPORT */ - -/* checksum options - set to zero for hardware checksum support */ - -#ifndef CHECKSUM_GEN_IP -#define CHECKSUM_GEN_IP 1 -#endif - -#ifndef CHECKSUM_GEN_UDP -#define CHECKSUM_GEN_UDP 1 -#endif - -#ifndef CHECKSUM_GEN_TCP -#define CHECKSUM_GEN_TCP 1 -#endif - -#ifndef CHECKSUM_CHECK_IP -#define CHECKSUM_CHECK_IP 1 -#endif - -#ifndef CHECKSUM_CHECK_UDP -#define CHECKSUM_CHECK_UDP 1 -#endif - -#ifndef CHECKSUM_CHECK_TCP -#define CHECKSUM_CHECK_TCP 1 -#endif - -/* Debugging options all default to off */ - -#ifndef DBG_TYPES_ON -#define DBG_TYPES_ON 0 -#endif - -#ifndef ETHARP_DEBUG -#define ETHARP_DEBUG DBG_OFF -#endif - -#ifndef NETIF_DEBUG -#define NETIF_DEBUG DBG_OFF -#endif - -#ifndef PBUF_DEBUG -#define PBUF_DEBUG DBG_OFF -#endif - -#ifndef API_LIB_DEBUG -#define API_LIB_DEBUG DBG_OFF -#endif - -#ifndef API_MSG_DEBUG -#define API_MSG_DEBUG DBG_OFF -#endif - -#ifndef SOCKETS_DEBUG -#define SOCKETS_DEBUG DBG_OFF -#endif - -#ifndef ICMP_DEBUG -#define ICMP_DEBUG DBG_OFF -#endif - -#ifndef INET_DEBUG -#define INET_DEBUG DBG_OFF -#endif - -#ifndef IP_DEBUG -#define IP_DEBUG DBG_OFF -#endif - -#ifndef IP_REASS_DEBUG -#define IP_REASS_DEBUG DBG_OFF -#endif - -#ifndef RAW_DEBUG -#define RAW_DEBUG DBG_OFF -#endif - -#ifndef MEM_DEBUG -#define MEM_DEBUG DBG_OFF -#endif - -#ifndef MEMP_DEBUG -#define MEMP_DEBUG DBG_OFF -#endif - -#ifndef SYS_DEBUG -#define SYS_DEBUG DBG_OFF -#endif - -#ifndef TCP_DEBUG -#define TCP_DEBUG DBG_OFF -#endif - -#ifndef TCP_INPUT_DEBUG -#define TCP_INPUT_DEBUG DBG_OFF -#endif - -#ifndef TCP_FR_DEBUG -#define TCP_FR_DEBUG DBG_OFF -#endif - -#ifndef TCP_RTO_DEBUG -#define TCP_RTO_DEBUG DBG_OFF -#endif - -#ifndef TCP_REXMIT_DEBUG -#define TCP_REXMIT_DEBUG DBG_OFF -#endif - -#ifndef TCP_CWND_DEBUG -#define TCP_CWND_DEBUG DBG_OFF -#endif - -#ifndef TCP_WND_DEBUG -#define TCP_WND_DEBUG DBG_OFF -#endif - -#ifndef TCP_OUTPUT_DEBUG -#define TCP_OUTPUT_DEBUG DBG_OFF -#endif - -#ifndef TCP_RST_DEBUG -#define TCP_RST_DEBUG DBG_OFF -#endif - -#ifndef TCP_QLEN_DEBUG -#define TCP_QLEN_DEBUG DBG_OFF -#endif - -#ifndef UDP_DEBUG -#define UDP_DEBUG DBG_OFF -#endif - -#ifndef TCPIP_DEBUG -#define TCPIP_DEBUG DBG_OFF -#endif - -#ifndef PPP_DEBUG -#define PPP_DEBUG DBG_OFF -#endif - -#ifndef SLIP_DEBUG -#define SLIP_DEBUG DBG_OFF -#endif - -#ifndef DHCP_DEBUG -#define DHCP_DEBUG DBG_OFF -#endif - - -#ifndef DBG_MIN_LEVEL -#define DBG_MIN_LEVEL DBG_LEVEL_OFF -#endif - -#endif /* __LWIP_OPT_H__ */ - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/pbuf.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/pbuf.h deleted file mode 100644 index 546aa3035..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/pbuf.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef __LWIP_PBUF_H__ -#define __LWIP_PBUF_H__ - -#include "arch/cc.h" - - -#define PBUF_TRANSPORT_HLEN 20 -#define PBUF_IP_HLEN 20 - -typedef enum { - PBUF_TRANSPORT, - PBUF_IP, - PBUF_LINK, - PBUF_RAW -} pbuf_layer; - -typedef enum { - PBUF_RAM, - PBUF_ROM, - PBUF_REF, - PBUF_POOL -} pbuf_flag; - -/* Definitions for the pbuf flag field. These are NOT the flags that - * are passed to pbuf_alloc(). */ -#define PBUF_FLAG_RAM 0x00U /* Flags that pbuf data is stored in RAM */ -#define PBUF_FLAG_ROM 0x01U /* Flags that pbuf data is stored in ROM */ -#define PBUF_FLAG_POOL 0x02U /* Flags that the pbuf comes from the pbuf pool */ -#define PBUF_FLAG_REF 0x04U /* Flags thet the pbuf payload refers to RAM */ - -/** indicates this packet was broadcast on the link */ -#define PBUF_FLAG_LINK_BROADCAST 0x80U - -struct pbuf { - /** next pbuf in singly linked pbuf chain */ - struct pbuf *next; - - /** pointer to the actual data in the buffer */ - void *payload; - - /** - * total length of this buffer and all next buffers in chain - * belonging to the same packet. - * - * For non-queue packet chains this is the invariant: - * p->tot_len == p->len + (p->next? p->next->tot_len: 0) - */ - u16_t tot_len; - - /** length of this buffer */ - u16_t len; - - /** flags telling the type of pbuf, see PBUF_FLAG_ */ - u16_t flags; - - /** - * the reference count always equals the number of pointers - * that refer to this pbuf. This can be pointers from an application, - * the stack itself, or pbuf->next pointers from a chain. - */ - u16_t ref; - -}; - -void pbuf_init(void); - -struct pbuf *pbuf_alloc(pbuf_layer l, u16_t size, pbuf_flag flag); -void pbuf_realloc(struct pbuf *p, u16_t size); -u8_t pbuf_header(struct pbuf *p, s16_t header_size); -void pbuf_ref(struct pbuf *p); -void pbuf_ref_chain(struct pbuf *p); -u8_t pbuf_free(struct pbuf *p); -u8_t pbuf_clen(struct pbuf *p); -void pbuf_cat(struct pbuf *h, struct pbuf *t); -void pbuf_chain(struct pbuf *h, struct pbuf *t); -struct pbuf *pbuf_take(struct pbuf *f); -struct pbuf *pbuf_dechain(struct pbuf *p); -void pbuf_queue(struct pbuf *p, struct pbuf *n); -struct pbuf * pbuf_dequeue(struct pbuf *p); - -#endif /* __LWIP_PBUF_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/raw.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/raw.h deleted file mode 100644 index 6f7a98717..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/raw.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_RAW_H__ -#define __LWIP_RAW_H__ - -#include "lwip/arch.h" - -#include "lwip/pbuf.h" -#include "lwip/inet.h" -#include "lwip/ip.h" - -struct raw_pcb { -/* Common members of all PCB types */ - IP_PCB; - - struct raw_pcb *next; - - u16_t protocol; - - u8_t (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p, - struct ip_addr *addr); - void *recv_arg; -}; - -/* The following functions is the application layer interface to the - RAW code. */ -struct raw_pcb * raw_new (u16_t proto); -void raw_remove (struct raw_pcb *pcb); -err_t raw_bind (struct raw_pcb *pcb, struct ip_addr *ipaddr); -err_t raw_connect (struct raw_pcb *pcb, struct ip_addr *ipaddr); - -void raw_recv (struct raw_pcb *pcb, - u8_t (* recv)(void *arg, struct raw_pcb *pcb, - struct pbuf *p, - struct ip_addr *addr), - void *recv_arg); -err_t raw_sendto (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr); -err_t raw_send (struct raw_pcb *pcb, struct pbuf *p); - -/* The following functions are the lower layer interface to RAW. */ -u8_t raw_input (struct pbuf *p, struct netif *inp); -void raw_init (void); - - -#endif /* __LWIP_RAW_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/sio.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/sio.h deleted file mode 100644 index 8a37aa35a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/sio.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - */ - -/* - * This is the interface to the platform specific serial IO module - * It needs to be implemented by those platforms which need SLIP or PPP - */ - -#include "arch/cc.h" - -#ifndef __sio_fd_t_defined -typedef void * sio_fd_t; -#endif - -#ifndef sio_open -sio_fd_t sio_open(u8_t); -#endif - -#ifndef sio_send -void sio_send(u8_t, sio_fd_t); -#endif - -#ifndef sio_recv -u8_t sio_recv(sio_fd_t); -#endif - -#ifndef sio_read -u32_t sio_read(sio_fd_t, u8_t *, u32_t); -#endif - -#ifndef sio_write -u32_t sio_write(sio_fd_t, u8_t *, u32_t); -#endif - -#ifndef sio_read_abort -void sio_read_abort(sio_fd_t); -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/snmp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/snmp.h deleted file mode 100644 index 7d160aaa4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/snmp.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2001, 2002 Leon Woestenberg - * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Leon Woestenberg - * - */ -#ifndef __LWIP_SNMP_H__ -#define __LWIP_SNMP_H__ - -#include "lwip/opt.h" - -/* SNMP support available? */ -#if defined(LWIP_SNMP) && (LWIP_SNMP > 0) - -/* network interface */ -void snmp_add_ifinoctets(unsigned long value); -void snmp_inc_ifinucastpkts(void); -void snmp_inc_ifinnucastpkts(void); -void snmp_inc_ifindiscards(void); -void snmp_add_ifoutoctets(unsigned long value); -void snmp_inc_ifoutucastpkts(void); -void snmp_inc_ifoutnucastpkts(void); -void snmp_inc_ifoutdiscards(void); - -/* IP */ -void snmp_inc_ipinreceives(void); -void snmp_inc_ipindelivers(void); -void snmp_inc_ipindiscards(void); -void snmp_inc_ipoutdiscards(void); -void snmp_inc_ipoutrequests(void); -void snmp_inc_ipunknownprotos(void); -void snmp_inc_ipnoroutes(void); -void snmp_inc_ipforwdatagrams(void); - -/* ICMP */ -void snmp_inc_icmpinmsgs(void); -void snmp_inc_icmpinerrors(void); -void snmp_inc_icmpindestunreachs(void); -void snmp_inc_icmpintimeexcds(void); -void snmp_inc_icmpinparmprobs(void); -void snmp_inc_icmpinsrcquenchs(void); -void snmp_inc_icmpinredirects(void); -void snmp_inc_icmpinechos(void); -void snmp_inc_icmpinechoreps(void); -void snmp_inc_icmpintimestamps(void); -void snmp_inc_icmpintimestampreps(void); -void snmp_inc_icmpinaddrmasks(void); -void snmp_inc_icmpinaddrmaskreps(void); -void snmp_inc_icmpoutmsgs(void); -void snmp_inc_icmpouterrors(void); -void snmp_inc_icmpoutdestunreachs(void); -void snmp_inc_icmpouttimeexcds(void); -void snmp_inc_icmpoutparmprobs(void); -void snmp_inc_icmpoutsrcquenchs(void); -void snmp_inc_icmpoutredirects(void); -void snmp_inc_icmpoutechos(void); -void snmp_inc_icmpoutechoreps(void); -void snmp_inc_icmpouttimestamps(void); -void snmp_inc_icmpouttimestampreps(void); -void snmp_inc_icmpoutaddrmasks(void); -void snmp_inc_icmpoutaddrmaskreps(void); - -/* TCP */ -void snmp_inc_tcpactiveopens(void); -void snmp_inc_tcppassiveopens(void); -void snmp_inc_tcpattemptfails(void); -void snmp_inc_tcpestabresets(void); -void snmp_inc_tcpcurrestab(void); -void snmp_inc_tcpinsegs(void); -void snmp_inc_tcpoutsegs(void); -void snmp_inc_tcpretranssegs(void); -void snmp_inc_tcpinerrs(void); -void snmp_inc_tcpoutrsts(void); - -/* UDP */ -void snmp_inc_udpindatagrams(void); -void snmp_inc_udpnoports(void); -void snmp_inc_udpinerrors(void); -void snmp_inc_udpoutdatagrams(void); - -/* LWIP_SNMP support not available */ -/* define everything to be empty */ -#else - -/* network interface */ -#define snmp_add_ifinoctets(value) -#define snmp_inc_ifinucastpkts() -#define snmp_inc_ifinnucastpkts() -#define snmp_inc_ifindiscards() -#define snmp_add_ifoutoctets(value) -#define snmp_inc_ifoutucastpkts() -#define snmp_inc_ifoutnucastpkts() -#define snmp_inc_ifoutdiscards() - -/* IP */ -#define snmp_inc_ipinreceives() -#define snmp_inc_ipindelivers() -#define snmp_inc_ipindiscards() -#define snmp_inc_ipoutdiscards() -#define snmp_inc_ipoutrequests() -#define snmp_inc_ipunknownprotos() -#define snmp_inc_ipnoroutes() -#define snmp_inc_ipforwdatagrams() - -/* ICMP */ -#define snmp_inc_icmpinmsgs() -#define snmp_inc_icmpinerrors() -#define snmp_inc_icmpindestunreachs() -#define snmp_inc_icmpintimeexcds() -#define snmp_inc_icmpinparmprobs() -#define snmp_inc_icmpinsrcquenchs() -#define snmp_inc_icmpinredirects() -#define snmp_inc_icmpinechos() -#define snmp_inc_icmpinechoreps() -#define snmp_inc_icmpintimestamps() -#define snmp_inc_icmpintimestampreps() -#define snmp_inc_icmpinaddrmasks() -#define snmp_inc_icmpinaddrmaskreps() -#define snmp_inc_icmpoutmsgs() -#define snmp_inc_icmpouterrors() -#define snmp_inc_icmpoutdestunreachs() -#define snmp_inc_icmpouttimeexcds() -#define snmp_inc_icmpoutparmprobs() -#define snmp_inc_icmpoutsrcquenchs() -#define snmp_inc_icmpoutredirects() -#define snmp_inc_icmpoutechos() -#define snmp_inc_icmpoutechoreps() -#define snmp_inc_icmpouttimestamps() -#define snmp_inc_icmpouttimestampreps() -#define snmp_inc_icmpoutaddrmasks() -#define snmp_inc_icmpoutaddrmaskreps() -/* TCP */ -#define snmp_inc_tcpactiveopens() -#define snmp_inc_tcppassiveopens() -#define snmp_inc_tcpattemptfails() -#define snmp_inc_tcpestabresets() -#define snmp_inc_tcpcurrestab() -#define snmp_inc_tcpinsegs() -#define snmp_inc_tcpoutsegs() -#define snmp_inc_tcpretranssegs() -#define snmp_inc_tcpinerrs() -#define snmp_inc_tcpoutrsts() - -/* UDP */ -#define snmp_inc_udpindatagrams() -#define snmp_inc_udpnoports() -#define snmp_inc_udpinerrors() -#define snmp_inc_udpoutdatagrams() - -#endif - -#endif /* __LWIP_SNMP_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/sockets.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/sockets.h deleted file mode 100644 index d5f8ccf74..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/sockets.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - - -#ifndef __LWIP_SOCKETS_H__ -#define __LWIP_SOCKETS_H__ -#include "lwip/ip_addr.h" - -struct sockaddr_in { - u8_t sin_len; - u8_t sin_family; - u16_t sin_port; - struct in_addr sin_addr; - char sin_zero[8]; -}; - -struct sockaddr { - u8_t sa_len; - u8_t sa_family; - char sa_data[14]; -}; - -#ifndef socklen_t -# define socklen_t int -#endif - - -#define SOCK_STREAM 1 -#define SOCK_DGRAM 2 -#define SOCK_RAW 3 - -/* - * Option flags per-socket. - */ -#define SO_DEBUG 0x0001 /* turn on debugging info recording */ -#define SO_ACCEPTCONN 0x0002 /* socket has had listen() */ -#define SO_REUSEADDR 0x0004 /* allow local address reuse */ -#define SO_KEEPALIVE 0x0008 /* keep connections alive */ -#define SO_DONTROUTE 0x0010 /* just use interface addresses */ -#define SO_BROADCAST 0x0020 /* permit sending of broadcast msgs */ -#define SO_USELOOPBACK 0x0040 /* bypass hardware when possible */ -#define SO_LINGER 0x0080 /* linger on close if data present */ -#define SO_OOBINLINE 0x0100 /* leave received OOB data in line */ -#define SO_REUSEPORT 0x0200 /* allow local address & port reuse */ - -#define SO_DONTLINGER (int)(~SO_LINGER) - -/* - * Additional options, not kept in so_options. - */ -#define SO_SNDBUF 0x1001 /* send buffer size */ -#define SO_RCVBUF 0x1002 /* receive buffer size */ -#define SO_SNDLOWAT 0x1003 /* send low-water mark */ -#define SO_RCVLOWAT 0x1004 /* receive low-water mark */ -#define SO_SNDTIMEO 0x1005 /* send timeout */ -#define SO_RCVTIMEO 0x1006 /* receive timeout */ -#define SO_ERROR 0x1007 /* get error status and clear */ -#define SO_TYPE 0x1008 /* get socket type */ - - - -/* - * Structure used for manipulating linger option. - */ -struct linger { - int l_onoff; /* option on/off */ - int l_linger; /* linger time */ -}; - -/* - * Level number for (get/set)sockopt() to apply to socket itself. - */ -#define SOL_SOCKET 0xfff /* options for socket level */ - - -#define AF_UNSPEC 0 -#define AF_INET 2 -#define PF_INET AF_INET -#define PF_UNSPEC AF_UNSPEC - -#define IPPROTO_IP 0 -#define IPPROTO_TCP 6 -#define IPPROTO_UDP 17 - -#define INADDR_ANY 0 -#define INADDR_BROADCAST 0xffffffff - -/* Flags we can use with send and recv. */ -#define MSG_DONTWAIT 0x40 /* Nonblocking i/o for this operation only */ - - -/* - * Options for level IPPROTO_IP - */ -#define IP_TOS 1 -#define IP_TTL 2 - - -#define IPTOS_TOS_MASK 0x1E -#define IPTOS_TOS(tos) ((tos) & IPTOS_TOS_MASK) -#define IPTOS_LOWDELAY 0x10 -#define IPTOS_THROUGHPUT 0x08 -#define IPTOS_RELIABILITY 0x04 -#define IPTOS_LOWCOST 0x02 -#define IPTOS_MINCOST IPTOS_LOWCOST - -/* - * Definitions for IP precedence (also in ip_tos) (hopefully unused) - */ -#define IPTOS_PREC_MASK 0xe0 -#define IPTOS_PREC(tos) ((tos) & IPTOS_PREC_MASK) -#define IPTOS_PREC_NETCONTROL 0xe0 -#define IPTOS_PREC_INTERNETCONTROL 0xc0 -#define IPTOS_PREC_CRITIC_ECP 0xa0 -#define IPTOS_PREC_FLASHOVERRIDE 0x80 -#define IPTOS_PREC_FLASH 0x60 -#define IPTOS_PREC_IMMEDIATE 0x40 -#define IPTOS_PREC_PRIORITY 0x20 -#define IPTOS_PREC_ROUTINE 0x00 - - -/* - * Commands for ioctlsocket(), taken from the BSD file fcntl.h. - * - * - * Ioctl's have the command encoded in the lower word, - * and the size of any in or out parameters in the upper - * word. The high 2 bits of the upper word are used - * to encode the in/out status of the parameter; for now - * we restrict parameters to at most 128 bytes. - */ -#if !defined(FIONREAD) || !defined(FIONBIO) -#define IOCPARM_MASK 0x7f /* parameters must be < 128 bytes */ -#define IOC_VOID 0x20000000 /* no parameters */ -#define IOC_OUT 0x40000000 /* copy out parameters */ -#define IOC_IN 0x80000000 /* copy in parameters */ -#define IOC_INOUT (IOC_IN|IOC_OUT) - /* 0x20000000 distinguishes new & - old ioctl's */ -#define _IO(x,y) (IOC_VOID|((x)<<8)|(y)) - -#define _IOR(x,y,t) (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) - -#define _IOW(x,y,t) (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) -#endif - -#ifndef FIONREAD -#define FIONREAD _IOR('f', 127, unsigned long) /* get # bytes to read */ -#endif -#ifndef FIONBIO -#define FIONBIO _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */ -#endif - -/* Socket I/O Controls */ -#ifndef SIOCSHIWAT -#define SIOCSHIWAT _IOW('s', 0, unsigned long) /* set high watermark */ -#define SIOCGHIWAT _IOR('s', 1, unsigned long) /* get high watermark */ -#define SIOCSLOWAT _IOW('s', 2, unsigned long) /* set low watermark */ -#define SIOCGLOWAT _IOR('s', 3, unsigned long) /* get low watermark */ -#define SIOCATMARK _IOR('s', 7, unsigned long) /* at oob mark? */ -#endif - -#ifndef O_NONBLOCK -#define O_NONBLOCK 04000U -#endif - -#ifndef FD_SET - #undef FD_SETSIZE - #define FD_SETSIZE 16 - #define FD_SET(n, p) ((p)->fd_bits[(n)/8] |= (1 << ((n) & 7))) - #define FD_CLR(n, p) ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7))) - #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] & (1 << ((n) & 7))) - #define FD_ZERO(p) memset((void*)(p),0,sizeof(*(p))) - - typedef struct fd_set { - unsigned char fd_bits [(FD_SETSIZE+7)/8]; - } fd_set; - -/* - * only define this in sockets.c so it does not interfere - * with other projects namespaces where timeval is present - */ -#ifndef LWIP_TIMEVAL_PRIVATE -#define LWIP_TIMEVAL_PRIVATE 1 -#endif - -#if LWIP_TIMEVAL_PRIVATE - struct timeval { - long tv_sec; /* seconds */ - long tv_usec; /* and microseconds */ - }; -#endif - -#endif - -int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen); -int lwip_bind(int s, struct sockaddr *name, socklen_t namelen); -int lwip_shutdown(int s, int how); -int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen); -int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen); -int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen); -int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen); -int lwip_close(int s); -int lwip_connect(int s, struct sockaddr *name, socklen_t namelen); -int lwip_listen(int s, int backlog); -int lwip_recv(int s, void *mem, int len, unsigned int flags); -int lwip_read(int s, void *mem, int len); -int lwip_recvfrom(int s, void *mem, int len, unsigned int flags, - struct sockaddr *from, socklen_t *fromlen); -int lwip_send(int s, void *dataptr, int size, unsigned int flags); -int lwip_sendto(int s, void *dataptr, int size, unsigned int flags, - struct sockaddr *to, socklen_t tolen); -int lwip_socket(int domain, int type, int protocol); -int lwip_write(int s, void *dataptr, int size); -int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, - struct timeval *timeout); -int lwip_ioctl(int s, long cmd, void *argp); - -#if LWIP_COMPAT_SOCKETS -#define accept(a,b,c) lwip_accept(a,b,c) -#define bind(a,b,c) lwip_bind(a,b,c) -#define shutdown(a,b) lwip_shutdown(a,b) -#define close(s) lwip_close(s) -#define connect(a,b,c) lwip_connect(a,b,c) -#define getsockname(a,b,c) lwip_getsockname(a,b,c) -#define getpeername(a,b,c) lwip_getpeername(a,b,c) -#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e) -#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e) -#define listen(a,b) lwip_listen(a,b) -#define recv(a,b,c,d) lwip_recv(a,b,c,d) -#define read(a,b,c) lwip_read(a,b,c) -#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f) -#define send(a,b,c,d) lwip_send(a,b,c,d) -#define sendto(a,b,c,d,e,f) lwip_sendto(a,b,c,d,e,f) -#define socket(a,b,c) lwip_socket(a,b,c) -#define write(a,b,c) lwip_write(a,b,c) -#define select(a,b,c,d,e) lwip_select(a,b,c,d,e) -#define ioctlsocket(a,b,c) lwip_ioctl(a,b,c) -#endif /* LWIP_COMPAT_SOCKETS */ - -#endif /* __LWIP_SOCKETS_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/stats.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/stats.h deleted file mode 100644 index 71acfd068..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/stats.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_STATS_H__ -#define __LWIP_STATS_H__ - -#include "lwip/opt.h" -#include "arch/cc.h" - -#include "lwip/mem.h" -#include "lwip/memp.h" - -#if LWIP_STATS - -struct stats_proto { - u16_t xmit; /* Transmitted packets. */ - u16_t rexmit; /* Retransmitted packets. */ - u16_t recv; /* Received packets. */ - u16_t fw; /* Forwarded packets. */ - u16_t drop; /* Dropped packets. */ - u16_t chkerr; /* Checksum error. */ - u16_t lenerr; /* Invalid length error. */ - u16_t memerr; /* Out of memory error. */ - u16_t rterr; /* Routing error. */ - u16_t proterr; /* Protocol error. */ - u16_t opterr; /* Error in options. */ - u16_t err; /* Misc error. */ - u16_t cachehit; -}; - -struct stats_mem { - mem_size_t avail; - mem_size_t used; - mem_size_t max; - mem_size_t err; -}; - -struct stats_pbuf { - u16_t avail; - u16_t used; - u16_t max; - u16_t err; - - u16_t alloc_locked; - u16_t refresh_locked; -}; - -struct stats_syselem { - u16_t used; - u16_t max; - u16_t err; -}; - -struct stats_sys { - struct stats_syselem sem; - struct stats_syselem mbox; -}; - -struct stats_ { - struct stats_proto link; - struct stats_proto ip_frag; - struct stats_proto ip; - struct stats_proto icmp; - struct stats_proto udp; - struct stats_proto tcp; - struct stats_pbuf pbuf; - struct stats_mem mem; - struct stats_mem memp[MEMP_MAX]; - struct stats_sys sys; -}; - -extern struct stats_ lwip_stats; - - -void stats_init(void); - -#define STATS_INC(x) ++lwip_stats.x -#else -#define stats_init() -#define STATS_INC(x) -#endif /* LWIP_STATS */ - -#if TCP_STATS -#define TCP_STATS_INC(x) STATS_INC(x) -#else -#define TCP_STATS_INC(x) -#endif - -#if UDP_STATS -#define UDP_STATS_INC(x) STATS_INC(x) -#else -#define UDP_STATS_INC(x) -#endif - -#if ICMP_STATS -#define ICMP_STATS_INC(x) STATS_INC(x) -#else -#define ICMP_STATS_INC(x) -#endif - -#if IP_STATS -#define IP_STATS_INC(x) STATS_INC(x) -#else -#define IP_STATS_INC(x) -#endif - -#if IPFRAG_STATS -#define IPFRAG_STATS_INC(x) STATS_INC(x) -#else -#define IPFRAG_STATS_INC(x) -#endif - -#if LINK_STATS -#define LINK_STATS_INC(x) STATS_INC(x) -#else -#define LINK_STATS_INC(x) -#endif - -/* Display of statistics */ -#if LWIP_STATS_DISPLAY -void stats_display(void); -#else -#define stats_display() -#endif - -#endif /* __LWIP_STATS_H__ */ - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/sys.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/sys.h deleted file mode 100644 index 68926e954..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/sys.h +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_SYS_H__ -#define __LWIP_SYS_H__ - -#include "arch/cc.h" - -#include "lwip/opt.h" - - -#if NO_SYS - -/* For a totally minimal and standalone system, we provide null - definitions of the sys_ functions. */ -typedef u8_t sys_sem_t; -typedef u8_t sys_mbox_t; -struct sys_timeout {u8_t dummy;}; - -#define sys_init() -#define sys_timeout(m,h,a) -#define sys_untimeout(m,a) -#define sys_sem_new(c) c -#define sys_sem_signal(s) -#define sys_sem_wait(s) -#define sys_sem_free(s) -#define sys_mbox_new() 0 -#define sys_mbox_fetch(m,d) -#define sys_mbox_post(m,d) -#define sys_mbox_free(m) - -#define sys_thread_new(t,a,p) - -#else /* NO_SYS */ - -#include "arch/sys_arch.h" - -/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */ -#define SYS_ARCH_TIMEOUT 0xffffffff - -typedef void (* sys_timeout_handler)(void *arg); - -struct sys_timeout { - struct sys_timeout *next; - u32_t time; - sys_timeout_handler h; - void *arg; -}; - -struct sys_timeouts { - struct sys_timeout *next; -}; - -/* sys_init() must be called before anthing else. */ -void sys_init(void); - -/* - * sys_timeout(): - * - * Schedule a timeout a specified amount of milliseconds in the - * future. When the timeout occurs, the specified timeout handler will - * be called. The handler will be passed the "arg" argument when - * called. - * - */ -void sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg); -void sys_untimeout(sys_timeout_handler h, void *arg); -struct sys_timeouts *sys_arch_timeouts(void); - -/* Semaphore functions. */ -sys_sem_t sys_sem_new(u8_t count); -void sys_sem_signal(sys_sem_t sem); -u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout); -void sys_sem_free(sys_sem_t sem); -void sys_sem_wait(sys_sem_t sem); -int sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout); - -/* Time functions. */ -#ifndef sys_msleep -void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */ -#endif -#ifndef sys_jiffies -u32_t sys_jiffies(void); /* since power up. */ -#endif - -/* Mailbox functions. */ -sys_mbox_t sys_mbox_new(void); -void sys_mbox_post(sys_mbox_t mbox, void *msg); -u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout); -void sys_mbox_free(sys_mbox_t mbox); -void sys_mbox_fetch(sys_mbox_t mbox, void **msg); - - -/* Thread functions. */ -sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio); - -/* The following functions are used only in Unix code, and - can be omitted when porting the stack. */ -/* Returns the current time in microseconds. */ -unsigned long sys_now(void); - -#endif /* NO_SYS */ - -/* Critical Region Protection */ -/* These functions must be implemented in the sys_arch.c file. - In some implementations they can provide a more light-weight protection - mechanism than using semaphores. Otherwise semaphores can be used for - implementation */ -#ifndef SYS_ARCH_PROTECT -/** SYS_LIGHTWEIGHT_PROT - * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection - * for certain critical regions during buffer allocation, deallocation and memory - * allocation and deallocation. - */ -#if SYS_LIGHTWEIGHT_PROT - -/** SYS_ARCH_DECL_PROTECT - * declare a protection variable. This macro will default to defining a variable of - * type sys_prot_t. If a particular port needs a different implementation, then - * this macro may be defined in sys_arch.h. - */ -#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev -/** SYS_ARCH_PROTECT - * Perform a "fast" protect. This could be implemented by - * disabling interrupts for an embedded system or by using a semaphore or - * mutex. The implementation should allow calling SYS_ARCH_PROTECT when - * already protected. The old protection level is returned in the variable - * "lev". This macro will default to calling the sys_arch_protect() function - * which should be implemented in sys_arch.c. If a particular port needs a - * different implementation, then this macro may be defined in sys_arch.h - */ -#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect() -/** SYS_ARCH_UNPROTECT - * Perform a "fast" set of the protection level to "lev". This could be - * implemented by setting the interrupt level to "lev" within the MACRO or by - * using a semaphore or mutex. This macro will default to calling the - * sys_arch_unprotect() function which should be implemented in - * sys_arch.c. If a particular port needs a different implementation, then - * this macro may be defined in sys_arch.h - */ -#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev) -sys_prot_t sys_arch_protect(void); -void sys_arch_unprotect(sys_prot_t pval); - -#else - -#define SYS_ARCH_DECL_PROTECT(lev) -#define SYS_ARCH_PROTECT(lev) -#define SYS_ARCH_UNPROTECT(lev) - -#endif /* SYS_LIGHTWEIGHT_PROT */ - -#endif /* SYS_ARCH_PROTECT */ - -#endif /* __LWIP_SYS_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/tcp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/tcp.h deleted file mode 100644 index 5f968c684..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/tcp.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_TCP_H__ -#define __LWIP_TCP_H__ - -#include "lwip/sys.h" -#include "lwip/mem.h" - -#include "lwip/pbuf.h" -#include "lwip/opt.h" -#include "lwip/ip.h" -#include "lwip/icmp.h" - -#include "lwip/err.h" - -struct tcp_pcb; - -/* Functions for interfacing with TCP: */ - -/* Lower layer interface to TCP: */ -void tcp_init (void); /* Must be called first to - initialize TCP. */ -void tcp_tmr (void); /* Must be called every - TCP_TMR_INTERVAL - ms. (Typically 250 ms). */ -/* Application program's interface: */ -struct tcp_pcb * tcp_new (void); -struct tcp_pcb * tcp_alloc (u8_t prio); - -void tcp_arg (struct tcp_pcb *pcb, void *arg); -void tcp_accept (struct tcp_pcb *pcb, - err_t (* accept)(void *arg, struct tcp_pcb *newpcb, - err_t err)); -void tcp_recv (struct tcp_pcb *pcb, - err_t (* recv)(void *arg, struct tcp_pcb *tpcb, - struct pbuf *p, err_t err)); -void tcp_sent (struct tcp_pcb *pcb, - err_t (* sent)(void *arg, struct tcp_pcb *tpcb, - u16_t len)); -void tcp_poll (struct tcp_pcb *pcb, - err_t (* poll)(void *arg, struct tcp_pcb *tpcb), - u8_t interval); -void tcp_err (struct tcp_pcb *pcb, - void (* err)(void *arg, err_t err)); - -#define tcp_mss(pcb) ((pcb)->mss) -#define tcp_sndbuf(pcb) ((pcb)->snd_buf) - -void tcp_recved (struct tcp_pcb *pcb, u16_t len); -err_t tcp_bind (struct tcp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port); -err_t tcp_connect (struct tcp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port, err_t (* connected)(void *arg, - struct tcp_pcb *tpcb, - err_t err)); -struct tcp_pcb * tcp_listen (struct tcp_pcb *pcb); -void tcp_abort (struct tcp_pcb *pcb); -err_t tcp_close (struct tcp_pcb *pcb); -err_t tcp_write (struct tcp_pcb *pcb, const void *dataptr, u16_t len, - u8_t copy); - -void tcp_setprio (struct tcp_pcb *pcb, u8_t prio); - -#define TCP_PRIO_MIN 1 -#define TCP_PRIO_NORMAL 64 -#define TCP_PRIO_MAX 127 - -/* It is also possible to call these two functions at the right - intervals (instead of calling tcp_tmr()). */ -void tcp_slowtmr (void); -void tcp_fasttmr (void); - - -/* Only used by IP to pass a TCP segment to TCP: */ -void tcp_input (struct pbuf *p, struct netif *inp); -/* Used within the TCP code only: */ -err_t tcp_output (struct tcp_pcb *pcb); -void tcp_rexmit (struct tcp_pcb *pcb); -void tcp_rexmit_rto (struct tcp_pcb *pcb); - - - -#define TCP_SEQ_LT(a,b) ((s32_t)((a)-(b)) < 0) -#define TCP_SEQ_LEQ(a,b) ((s32_t)((a)-(b)) <= 0) -#define TCP_SEQ_GT(a,b) ((s32_t)((a)-(b)) > 0) -#define TCP_SEQ_GEQ(a,b) ((s32_t)((a)-(b)) >= 0) -/* is b<=a<=c? */ -#if 0 /* see bug #10548 */ -#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b)) -#endif -#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c)) -#define TCP_FIN 0x01U -#define TCP_SYN 0x02U -#define TCP_RST 0x04U -#define TCP_PSH 0x08U -#define TCP_ACK 0x10U -#define TCP_URG 0x20U -#define TCP_ECE 0x40U -#define TCP_CWR 0x80U - -#define TCP_FLAGS 0x3fU - -/* Length of the TCP header, excluding options. */ -#define TCP_HLEN 20 - -#ifndef TCP_TMR_INTERVAL -#define TCP_TMR_INTERVAL 250 /* The TCP timer interval in - milliseconds. */ -#endif /* TCP_TMR_INTERVAL */ - -#ifndef TCP_FAST_INTERVAL -#define TCP_FAST_INTERVAL TCP_TMR_INTERVAL /* the fine grained timeout in - milliseconds */ -#endif /* TCP_FAST_INTERVAL */ - -#ifndef TCP_SLOW_INTERVAL -#define TCP_SLOW_INTERVAL (2*TCP_TMR_INTERVAL) /* the coarse grained timeout in - milliseconds */ -#endif /* TCP_SLOW_INTERVAL */ - -#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */ -#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */ - -#define TCP_OOSEQ_TIMEOUT 6 /* x RTO */ - -#define TCP_MSL 60000 /* The maximum segment lifetime in microseconds */ - -/* - * User-settable options (used with setsockopt). - */ -#define TCP_NODELAY 0x01 /* don't delay send to coalesce packets */ -#define TCP_KEEPALIVE 0x02 /* send KEEPALIVE probes when idle for pcb->keepalive miliseconds */ - -/* Keepalive values */ -#define TCP_KEEPDEFAULT 7200000 /* KEEPALIVE timer in miliseconds */ -#define TCP_KEEPINTVL 75000 /* Time between KEEPALIVE probes in miliseconds */ -#define TCP_KEEPCNT 9 /* Counter for KEEPALIVE probes */ -#define TCP_MAXIDLE TCP_KEEPCNT * TCP_KEEPINTVL /* Maximum KEEPALIVE probe time */ - - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct tcp_hdr { - PACK_STRUCT_FIELD(u16_t src); - PACK_STRUCT_FIELD(u16_t dest); - PACK_STRUCT_FIELD(u32_t seqno); - PACK_STRUCT_FIELD(u32_t ackno); - PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags); - PACK_STRUCT_FIELD(u16_t wnd); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FIELD(u16_t urgp); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8) -#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12) -#define TCPH_FLAGS(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS) - -#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr)) -#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr)) -#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons((ntohs((phdr)->_hdrlen_rsvd_flags) & ~TCP_FLAGS) | (flags)) -#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (flags)) -#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) ) - -#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & TCP_FIN || \ - TCPH_FLAGS((seg)->tcphdr) & TCP_SYN)? 1: 0)) - -enum tcp_state { - CLOSED = 0, - LISTEN = 1, - SYN_SENT = 2, - SYN_RCVD = 3, - ESTABLISHED = 4, - FIN_WAIT_1 = 5, - FIN_WAIT_2 = 6, - CLOSE_WAIT = 7, - CLOSING = 8, - LAST_ACK = 9, - TIME_WAIT = 10 -}; - -/* the TCP protocol control block */ -struct tcp_pcb { -/** common PCB members */ - IP_PCB; -/** protocol specific PCB members */ - struct tcp_pcb *next; /* for the linked list */ - enum tcp_state state; /* TCP state */ - u8_t prio; - void *callback_arg; - - u16_t local_port; - u16_t remote_port; - - u8_t flags; -#define TF_ACK_DELAY (u8_t)0x01U /* Delayed ACK. */ -#define TF_ACK_NOW (u8_t)0x02U /* Immediate ACK. */ -#define TF_INFR (u8_t)0x04U /* In fast recovery. */ -#define TF_RESET (u8_t)0x08U /* Connection was reset. */ -#define TF_CLOSED (u8_t)0x10U /* Connection was sucessfully closed. */ -#define TF_GOT_FIN (u8_t)0x20U /* Connection was closed by the remote end. */ -#define TF_NODELAY (u8_t)0x40U /* Disable Nagle algorithm */ - - /* receiver variables */ - u32_t rcv_nxt; /* next seqno expected */ - u16_t rcv_wnd; /* receiver window */ - - /* Timers */ - u32_t tmr; - u8_t polltmr, pollinterval; - - /* Retransmission timer. */ - u16_t rtime; - - u16_t mss; /* maximum segment size */ - - /* RTT (round trip time) estimation variables */ - u32_t rttest; /* RTT estimate in 500ms ticks */ - u32_t rtseq; /* sequence number being timed */ - s16_t sa, sv; /* @todo document this */ - - u16_t rto; /* retransmission time-out */ - u8_t nrtx; /* number of retransmissions */ - - /* fast retransmit/recovery */ - u32_t lastack; /* Highest acknowledged seqno. */ - u8_t dupacks; - - /* congestion avoidance/control variables */ - u16_t cwnd; - u16_t ssthresh; - - /* sender variables */ - u32_t snd_nxt, /* next seqno to be sent */ - snd_max, /* Highest seqno sent. */ - snd_wnd, /* sender window */ - snd_wl1, snd_wl2, /* Sequence and acknowledgement numbers of last - window update. */ - snd_lbb; /* Sequence number of next byte to be buffered. */ - - u16_t acked; - - u16_t snd_buf; /* Available buffer space for sending (in bytes). */ - u8_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */ - - - /* These are ordered by sequence number: */ - struct tcp_seg *unsent; /* Unsent (queued) segments. */ - struct tcp_seg *unacked; /* Sent but unacknowledged segments. */ -#if TCP_QUEUE_OOSEQ - struct tcp_seg *ooseq; /* Received out of sequence segments. */ -#endif /* TCP_QUEUE_OOSEQ */ - -#if LWIP_CALLBACK_API - /* Function to be called when more send buffer space is available. */ - err_t (* sent)(void *arg, struct tcp_pcb *pcb, u16_t space); - - /* Function to be called when (in-sequence) data has arrived. */ - err_t (* recv)(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err); - - /* Function to be called when a connection has been set up. */ - err_t (* connected)(void *arg, struct tcp_pcb *pcb, err_t err); - - /* Function to call when a listener has been connected. */ - err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err); - - /* Function which is called periodically. */ - err_t (* poll)(void *arg, struct tcp_pcb *pcb); - - /* Function to be called whenever a fatal error occurs. */ - void (* errf)(void *arg, err_t err); -#endif /* LWIP_CALLBACK_API */ - - /* idle time before KEEPALIVE is sent */ - u32_t keepalive; - - /* KEEPALIVE counter */ - u8_t keep_cnt; -}; - -struct tcp_pcb_listen { -/* Common members of all PCB types */ - IP_PCB; - -/* Protocol specific PCB members */ - struct tcp_pcb_listen *next; /* for the linked list */ - - /* Even if state is obviously LISTEN this is here for - * field compatibility with tpc_pcb to which it is cast sometimes - * Until a cleaner solution emerges this is here.FIXME - */ - enum tcp_state state; /* TCP state */ - - u8_t prio; - void *callback_arg; - - u16_t local_port; - -#if LWIP_CALLBACK_API - /* Function to call when a listener has been connected. */ - err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err); -#endif /* LWIP_CALLBACK_API */ -}; - -#if LWIP_EVENT_API - -enum lwip_event { - LWIP_EVENT_ACCEPT, - LWIP_EVENT_SENT, - LWIP_EVENT_RECV, - LWIP_EVENT_CONNECTED, - LWIP_EVENT_POLL, - LWIP_EVENT_ERR -}; - -err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb, - enum lwip_event, - struct pbuf *p, - u16_t size, - err_t err); - -#define TCP_EVENT_ACCEPT(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_ACCEPT, NULL, 0, err) -#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_SENT, NULL, space, ERR_OK) -#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_RECV, (p), 0, (err)) -#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_CONNECTED, NULL, 0, (err)) -#define TCP_EVENT_POLL(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_POLL, NULL, 0, ERR_OK) -#define TCP_EVENT_ERR(errf,arg,err) lwip_tcp_event((arg), NULL, \ - LWIP_EVENT_ERR, NULL, 0, (err)) -#else /* LWIP_EVENT_API */ -#define TCP_EVENT_ACCEPT(pcb,err,ret) \ - if((pcb)->accept != NULL) \ - (ret = (pcb)->accept((pcb)->callback_arg,(pcb),(err))) -#define TCP_EVENT_SENT(pcb,space,ret) \ - if((pcb)->sent != NULL) \ - (ret = (pcb)->sent((pcb)->callback_arg,(pcb),(space))) -#define TCP_EVENT_RECV(pcb,p,err,ret) \ - if((pcb)->recv != NULL) \ - { ret = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err)); } else { \ - if (p) pbuf_free(p); } -#define TCP_EVENT_CONNECTED(pcb,err,ret) \ - if((pcb)->connected != NULL) \ - (ret = (pcb)->connected((pcb)->callback_arg,(pcb),(err))) -#define TCP_EVENT_POLL(pcb,ret) \ - if((pcb)->poll != NULL) \ - (ret = (pcb)->poll((pcb)->callback_arg,(pcb))) -#define TCP_EVENT_ERR(errf,arg,err) \ - if((errf) != NULL) \ - (errf)((arg),(err)) -#endif /* LWIP_EVENT_API */ - -/* This structure represents a TCP segment on the unsent and unacked queues */ -struct tcp_seg { - struct tcp_seg *next; /* used when putting segements on a queue */ - struct pbuf *p; /* buffer containing data + TCP header */ - void *dataptr; /* pointer to the TCP data in the pbuf */ - u16_t len; /* the TCP length of this segment */ - struct tcp_hdr *tcphdr; /* the TCP header */ -}; - -/* Internal functions and global variables: */ -struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb); -void tcp_pcb_purge(struct tcp_pcb *pcb); -void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb); - -u8_t tcp_segs_free(struct tcp_seg *seg); -u8_t tcp_seg_free(struct tcp_seg *seg); -struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg); - -#define tcp_ack(pcb) if((pcb)->flags & TF_ACK_DELAY) { \ - (pcb)->flags &= ~TF_ACK_DELAY; \ - (pcb)->flags |= TF_ACK_NOW; \ - tcp_output(pcb); \ - } else { \ - (pcb)->flags |= TF_ACK_DELAY; \ - } - -#define tcp_ack_now(pcb) (pcb)->flags |= TF_ACK_NOW; \ - tcp_output(pcb) - -err_t tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags); -err_t tcp_enqueue(struct tcp_pcb *pcb, void *dataptr, u16_t len, - u8_t flags, u8_t copy, - u8_t *optdata, u8_t optlen); - -void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg); - -void tcp_rst(u32_t seqno, u32_t ackno, - struct ip_addr *local_ip, struct ip_addr *remote_ip, - u16_t local_port, u16_t remote_port); - -u32_t tcp_next_iss(void); - -void tcp_keepalive(struct tcp_pcb *pcb); - -extern struct tcp_pcb *tcp_input_pcb; -extern u32_t tcp_ticks; - -#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG -void tcp_debug_print(struct tcp_hdr *tcphdr); -void tcp_debug_print_flags(u8_t flags); -void tcp_debug_print_state(enum tcp_state s); -void tcp_debug_print_pcbs(void); -s16_t tcp_pcbs_sane(void); -#else -# define tcp_debug_print(tcphdr) -# define tcp_debug_print_flags(flags) -# define tcp_debug_print_state(s) -# define tcp_debug_print_pcbs() -# define tcp_pcbs_sane() 1 -#endif /* TCP_DEBUG */ - -#if NO_SYS -#define tcp_timer_needed() -#else -void tcp_timer_needed(void); -#endif - -/* The TCP PCB lists. */ -union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */ - struct tcp_pcb_listen *listen_pcbs; - struct tcp_pcb *pcbs; -}; -extern union tcp_listen_pcbs_t tcp_listen_pcbs; -extern struct tcp_pcb *tcp_active_pcbs; /* List of all TCP PCBs that are in a - state in which they accept or send - data. */ -extern struct tcp_pcb *tcp_tw_pcbs; /* List of all TCP PCBs in TIME-WAIT. */ - -extern struct tcp_pcb *tcp_tmp_pcb; /* Only used for temporary storage. */ - -/* Axioms about the above lists: - 1) Every TCP PCB that is not CLOSED is in one of the lists. - 2) A PCB is only in one of the lists. - 3) All PCBs in the tcp_listen_pcbs list is in LISTEN state. - 4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state. -*/ - -/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB - with a PCB list or removes a PCB from a list, respectively. */ -#if 0 -#define TCP_REG(pcbs, npcb) do {\ - LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", npcb, npcb->local_port)); \ - for(tcp_tmp_pcb = *pcbs; \ - tcp_tmp_pcb != NULL; \ - tcp_tmp_pcb = tcp_tmp_pcb->next) { \ - LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != npcb); \ - } \ - LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", npcb->state != CLOSED); \ - npcb->next = *pcbs; \ - LWIP_ASSERT("TCP_REG: npcb->next != npcb", npcb->next != npcb); \ - *(pcbs) = npcb; \ - LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ - tcp_timer_needed(); \ - } while(0) -#define TCP_RMV(pcbs, npcb) do { \ - LWIP_ASSERT("TCP_RMV: pcbs != NULL", *pcbs != NULL); \ - LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", npcb, *pcbs)); \ - if(*pcbs == npcb) { \ - *pcbs = (*pcbs)->next; \ - } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \ - if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \ - tcp_tmp_pcb->next = npcb->next; \ - break; \ - } \ - } \ - npcb->next = NULL; \ - LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ - LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", npcb, *pcbs)); \ - } while(0) - -#else /* LWIP_DEBUG */ -#define TCP_REG(pcbs, npcb) do { \ - npcb->next = *pcbs; \ - *(pcbs) = npcb; \ - tcp_timer_needed(); \ - } while(0) -#define TCP_RMV(pcbs, npcb) do { \ - if(*(pcbs) == npcb) { \ - (*(pcbs)) = (*pcbs)->next; \ - } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \ - if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \ - tcp_tmp_pcb->next = npcb->next; \ - break; \ - } \ - } \ - npcb->next = NULL; \ - } while(0) -#endif /* LWIP_DEBUG */ -#endif /* __LWIP_TCP_H__ */ - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/tcpip.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/tcpip.h deleted file mode 100644 index 316ae4fc5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/tcpip.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_TCPIP_H__ -#define __LWIP_TCPIP_H__ - -#include "lwip/api_msg.h" -#include "lwip/pbuf.h" - -void tcpip_init(void (* tcpip_init_done)(void *), void *arg); -void tcpip_apimsg(struct api_msg *apimsg); -err_t tcpip_input(struct pbuf *p, struct netif *inp); -err_t tcpip_callback(void (*f)(void *ctx), void *ctx); - -void tcpip_tcp_timer_needed(void); - -enum tcpip_msg_type { - TCPIP_MSG_API, - TCPIP_MSG_INPUT, - TCPIP_MSG_CALLBACK -}; - -struct tcpip_msg { - enum tcpip_msg_type type; - sys_sem_t *sem; - union { - struct api_msg *apimsg; - struct { - struct pbuf *p; - struct netif *netif; - } inp; - struct { - void (*f)(void *ctx); - void *ctx; - } cb; - } msg; -}; - - -#endif /* __LWIP_TCPIP_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/udp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/udp.h deleted file mode 100644 index ede04745f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/lwip/udp.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_UDP_H__ -#define __LWIP_UDP_H__ - -#include "lwip/arch.h" - -#include "lwip/pbuf.h" -#include "lwip/inet.h" -#include "lwip/ip.h" - -#define UDP_HLEN 8 - -struct udp_hdr { - PACK_STRUCT_FIELD(u16_t src); - PACK_STRUCT_FIELD(u16_t dest); /* src/dest UDP ports */ - PACK_STRUCT_FIELD(u16_t len); - PACK_STRUCT_FIELD(u16_t chksum); -} PACK_STRUCT_STRUCT; - -#define UDP_FLAGS_NOCHKSUM 0x01U -#define UDP_FLAGS_UDPLITE 0x02U -#define UDP_FLAGS_CONNECTED 0x04U - -struct udp_pcb { -/* Common members of all PCB types */ - IP_PCB; - -/* Protocol specific PCB members */ - - struct udp_pcb *next; - - u8_t flags; - u16_t local_port, remote_port; - - u16_t chksum_len; - - void (* recv)(void *arg, struct udp_pcb *pcb, struct pbuf *p, - struct ip_addr *addr, u16_t port); - void *recv_arg; -}; - -/* The following functions is the application layer interface to the - UDP code. */ -struct udp_pcb * udp_new (void); -void udp_remove (struct udp_pcb *pcb); -err_t udp_bind (struct udp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port); -err_t udp_connect (struct udp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port); -void udp_disconnect (struct udp_pcb *pcb); -void udp_recv (struct udp_pcb *pcb, - void (* recv)(void *arg, struct udp_pcb *upcb, - struct pbuf *p, - struct ip_addr *addr, - u16_t port), - void *recv_arg); -err_t udp_sendto (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port); -err_t udp_send (struct udp_pcb *pcb, struct pbuf *p); - -#define udp_flags(pcb) ((pcb)->flags) -#define udp_setflags(pcb, f) ((pcb)->flags = (f)) - -/* The following functions are the lower layer interface to UDP. */ -void udp_input (struct pbuf *p, struct netif *inp); -void udp_init (void); - -#if UDP_DEBUG -void udp_debug_print(struct udp_hdr *udphdr); -#else -#define udp_debug_print(udphdr) -#endif -#endif /* __LWIP_UDP_H__ */ - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/netif/etharp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/netif/etharp.h deleted file mode 100644 index 08437afe5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/netif/etharp.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * Copyright (c) 2003-2004 Leon Woestenberg - * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef __NETIF_ETHARP_H__ -#define __NETIF_ETHARP_H__ - -#ifndef ETH_PAD_SIZE -#define ETH_PAD_SIZE 0 -#endif - -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/ip.h" - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct eth_addr { - PACK_STRUCT_FIELD(u8_t addr[6]); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct eth_hdr { -#if ETH_PAD_SIZE - PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]); -#endif - PACK_STRUCT_FIELD(struct eth_addr dest); - PACK_STRUCT_FIELD(struct eth_addr src); - PACK_STRUCT_FIELD(u16_t type); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -/** the ARP message */ -struct etharp_hdr { - PACK_STRUCT_FIELD(struct eth_hdr ethhdr); - PACK_STRUCT_FIELD(u16_t hwtype); - PACK_STRUCT_FIELD(u16_t proto); - PACK_STRUCT_FIELD(u16_t _hwlen_protolen); - PACK_STRUCT_FIELD(u16_t opcode); - PACK_STRUCT_FIELD(struct eth_addr shwaddr); - PACK_STRUCT_FIELD(struct ip_addr2 sipaddr); - PACK_STRUCT_FIELD(struct eth_addr dhwaddr); - PACK_STRUCT_FIELD(struct ip_addr2 dipaddr); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ethip_hdr { - PACK_STRUCT_FIELD(struct eth_hdr eth); - PACK_STRUCT_FIELD(struct ip_hdr ip); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/** 5 seconds period */ -#define ARP_TMR_INTERVAL 5000 - -#define ETHTYPE_ARP 0x0806 -#define ETHTYPE_IP 0x0800 - -void etharp_init(void); -void etharp_tmr(void); -void etharp_ip_input(struct netif *netif, struct pbuf *p); -void etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, - struct pbuf *p); -err_t etharp_output(struct netif *netif, struct ip_addr *ipaddr, - struct pbuf *q); -err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q); -err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr); - -#endif /* __NETIF_ARP_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/netif/loopif.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/netif/loopif.h deleted file mode 100644 index 97b3c6764..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/netif/loopif.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __NETIF_LOOPIF_H__ -#define __NETIF_LOOPIF_H__ - -#include "lwip/netif.h" - -err_t loopif_init(struct netif *netif); - -#endif /* __NETIF_LOOPIF_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/netif/slipif.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/netif/slipif.h deleted file mode 100644 index bf70046a9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/include/netif/slipif.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __NETIF_SLIPIF_H__ -#define __NETIF_SLIPIF_H__ - -#include "lwip/netif.h" - -err_t slipif_init(struct netif * netif); - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/FILES b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/FILES deleted file mode 100644 index 825d40715..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/FILES +++ /dev/null @@ -1,27 +0,0 @@ -This directory contains generic network interface device drivers that -do not contain any hardware or architecture specific code. The files -are: - -etharp.c - Implements the ARP (Address Resolution Protocol) over - Ethernet. The code in this file should be used together with - Ethernet device drivers. Note that this module has been - largely made Ethernet independent so you should be able to - adapt this for other link layers (such as Firewire). - -ethernetif.c - An example of how an Ethernet device driver could look. This - file can be used as a "skeleton" for developing new Ethernet - network device drivers. It uses the etharp.c ARP code. - -loopif.c - An example network interface that shows how a "loopback" - interface would work. This is not really intended for actual - use, but as a very basic example of how initialization and - output functions work. - -slipif.c - A generic implementation of the SLIP (Serial Line IP) - protocol. It requires a sio (serial I/O) module to work. - -ppp/ Point-to-Point Protocol stack diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/etharp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/etharp.c deleted file mode 100644 index 7765046d4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/etharp.c +++ /dev/null @@ -1,831 +0,0 @@ -/** - * @file - * Address Resolution Protocol module for IP over Ethernet - * - * Functionally, ARP is divided into two parts. The first maps an IP address - * to a physical address when sending a packet, and the second part answers - * requests from other machines for our physical address. - * - * This implementation complies with RFC 826 (Ethernet ARP). It supports - * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6 - * if an interface calls etharp_query(our_netif, its_ip_addr, NULL) upon - * address change. - */ - -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * Copyright (c) 2003-2004 Leon Woestenberg - * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - */ - -#include "lwip/opt.h" -#include "lwip/inet.h" -#include "netif/etharp.h" -#include "lwip/ip.h" -#include "lwip/stats.h" - -/* ARP needs to inform DHCP of any ARP replies? */ -#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK) -# include "lwip/dhcp.h" -#endif - -/** the time an ARP entry stays valid after its last update, - * (240 * 5) seconds = 20 minutes. - */ -#define ARP_MAXAGE 240 -/** the time an ARP entry stays pending after first request, - * (2 * 5) seconds = 10 seconds. - * - * @internal Keep this number at least 2, otherwise it might - * run out instantly if the timeout occurs directly after a request. - */ -#define ARP_MAXPENDING 2 - -#define HWTYPE_ETHERNET 1 - -/** ARP message types */ -#define ARP_REQUEST 1 -#define ARP_REPLY 2 - -#define ARPH_HWLEN(hdr) (ntohs((hdr)->_hwlen_protolen) >> 8) -#define ARPH_PROTOLEN(hdr) (ntohs((hdr)->_hwlen_protolen) & 0xff) - -#define ARPH_HWLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons(ARPH_PROTOLEN(hdr) | ((len) << 8)) -#define ARPH_PROTOLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons((len) | (ARPH_HWLEN(hdr) << 8)) - -enum etharp_state { - ETHARP_STATE_EMPTY, - ETHARP_STATE_PENDING, - ETHARP_STATE_STABLE, - /** @internal transitional state used in etharp_tmr() for convenience*/ - ETHARP_STATE_EXPIRED -}; - -struct etharp_entry { -#if ARP_QUEUEING - /** - * Pointer to queue of pending outgoing packets on this ARP entry. - */ - struct pbuf *p; -#endif - struct ip_addr ipaddr; - struct eth_addr ethaddr; - enum etharp_state state; - u8_t ctime; -}; - -static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}}; -static struct etharp_entry arp_table[ARP_TABLE_SIZE]; - -/** - * Try hard to create a new entry - we want the IP address to appear in - * the cache (even if this means removing an active entry or so). */ -#define ETHARP_TRY_HARD 1 - -static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags); -static err_t update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags); -/** - * Initializes ARP module. - */ -void -etharp_init(void) -{ - u8_t i; - /* clear ARP entries */ - for(i = 0; i < ARP_TABLE_SIZE; ++i) { - arp_table[i].state = ETHARP_STATE_EMPTY; -#if ARP_QUEUEING - arp_table[i].p = NULL; -#endif - arp_table[i].ctime = 0; - } -} - -/** - * Clears expired entries in the ARP table. - * - * This function should be called every ETHARP_TMR_INTERVAL microseconds (5 seconds), - * in order to expire entries in the ARP table. - */ -void -etharp_tmr(void) -{ - u8_t i; - - LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n")); - /* remove expired entries from the ARP table */ - for (i = 0; i < ARP_TABLE_SIZE; ++i) { - arp_table[i].ctime++; - /* stable entry? */ - if ((arp_table[i].state == ETHARP_STATE_STABLE) && - /* entry has become old? */ - (arp_table[i].ctime >= ARP_MAXAGE)) { - LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired stable entry %"U16_F".\n", (u16_t)i)); - arp_table[i].state = ETHARP_STATE_EXPIRED; - /* pending entry? */ - } else if (arp_table[i].state == ETHARP_STATE_PENDING) { - /* entry unresolved/pending for too long? */ - if (arp_table[i].ctime >= ARP_MAXPENDING) { - LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired pending entry %"U16_F".\n", (u16_t)i)); - arp_table[i].state = ETHARP_STATE_EXPIRED; -#if ARP_QUEUEING - } else if (arp_table[i].p != NULL) { - /* resend an ARP query here */ -#endif - } - } - /* clean up entries that have just been expired */ - if (arp_table[i].state == ETHARP_STATE_EXPIRED) { -#if ARP_QUEUEING - /* and empty packet queue */ - if (arp_table[i].p != NULL) { - /* remove all queued packets */ - LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].p))); - pbuf_free(arp_table[i].p); - arp_table[i].p = NULL; - } -#endif - /* recycle entry for re-use */ - arp_table[i].state = ETHARP_STATE_EMPTY; - } - } -} - -/** - * Search the ARP table for a matching or new entry. - * - * If an IP address is given, return a pending or stable ARP entry that matches - * the address. If no match is found, create a new entry with this address set, - * but in state ETHARP_EMPTY. The caller must check and possibly change the - * state of the returned entry. - * - * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY. - * - * In all cases, attempt to create new entries from an empty entry. If no - * empty entries are available and ETHARP_TRY_HARD flag is set, recycle - * old entries. Heuristic choose the least important entry for recycling. - * - * @param ipaddr IP address to find in ARP cache, or to add if not found. - * @param flags - * - ETHARP_TRY_HARD: Try hard to create a entry by allowing recycling of - * active (stable or pending) entries. - * - * @return The ARP entry index that matched or is created, ERR_MEM if no - * entry is found or could be recycled. - */ -static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags) -{ - s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE; - s8_t empty = ARP_TABLE_SIZE; - u8_t i = 0, age_pending = 0, age_stable = 0; -#if ARP_QUEUEING - /* oldest entry with packets on queue */ - s8_t old_queue = ARP_TABLE_SIZE; - /* its age */ - u8_t age_queue = 0; -#endif - - /** - * a) do a search through the cache, remember candidates - * b) select candidate entry - * c) create new entry - */ - - /* a) in a single search sweep, do all of this - * 1) remember the first empty entry (if any) - * 2) remember the oldest stable entry (if any) - * 3) remember the oldest pending entry without queued packets (if any) - * 4) remember the oldest pending entry with queued packets (if any) - * 5) search for a matching IP entry, either pending or stable - * until 5 matches, or all entries are searched for. - */ - - for (i = 0; i < ARP_TABLE_SIZE; ++i) { - /* no empty entry found yet and now we do find one? */ - if ((empty == ARP_TABLE_SIZE) && (arp_table[i].state == ETHARP_STATE_EMPTY)) { - LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %"U16_F"\n", (u16_t)i)); - /* remember first empty entry */ - empty = i; - } - /* pending entry? */ - else if (arp_table[i].state == ETHARP_STATE_PENDING) { - /* if given, does IP address match IP address in ARP entry? */ - if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) { - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching pending entry %"U16_F"\n", (u16_t)i)); - /* found exact IP address match, simply bail out */ - return i; -#if ARP_QUEUEING - /* pending with queued packets? */ - } else if (arp_table[i].p != NULL) { - if (arp_table[i].ctime >= age_queue) { - old_queue = i; - age_queue = arp_table[i].ctime; - } -#endif - /* pending without queued packets? */ - } else { - if (arp_table[i].ctime >= age_pending) { - old_pending = i; - age_pending = arp_table[i].ctime; - } - } - } - /* stable entry? */ - else if (arp_table[i].state == ETHARP_STATE_STABLE) { - /* if given, does IP address match IP address in ARP entry? */ - if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) { - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching stable entry %"U16_F"\n", (u16_t)i)); - /* found exact IP address match, simply bail out */ - return i; - /* remember entry with oldest stable entry in oldest, its age in maxtime */ - } else if (arp_table[i].ctime >= age_stable) { - old_stable = i; - age_stable = arp_table[i].ctime; - } - } - } - /* { we have no match } => try to create a new entry */ - - /* no empty entry found and not allowed to recycle? */ - if ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_TRY_HARD) == 0)) - { - return (s8_t)ERR_MEM; - } - - /* b) choose the least destructive entry to recycle: - * 1) empty entry - * 2) oldest stable entry - * 3) oldest pending entry without queued packets - * 4) oldest pending entry without queued packets - * - * { ETHARP_TRY_HARD is set at this point } - */ - - /* 1) empty entry available? */ - if (empty < ARP_TABLE_SIZE) { - i = empty; - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting empty entry %"U16_F"\n", (u16_t)i)); - } - /* 2) found recyclable stable entry? */ - else if (old_stable < ARP_TABLE_SIZE) { - /* recycle oldest stable*/ - i = old_stable; - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest stable entry %"U16_F"\n", (u16_t)i)); -#if ARP_QUEUEING - /* no queued packets should exist on stable entries */ - LWIP_ASSERT("arp_table[i].p == NULL", arp_table[i].p == NULL); -#endif - /* 3) found recyclable pending entry without queued packets? */ - } else if (old_pending < ARP_TABLE_SIZE) { - /* recycle oldest pending */ - i = old_pending; - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F" (without queue)\n", (u16_t)i)); -#if ARP_QUEUEING - /* 4) found recyclable pending entry with queued packets? */ - } else if (old_queue < ARP_TABLE_SIZE) { - /* recycle oldest pending */ - i = old_queue; - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F", freeing packet queue %p\n", (u16_t)i, (void *)(arp_table[i].p))); - pbuf_free(arp_table[i].p); - arp_table[i].p = NULL; -#endif - /* no empty or recyclable entries found */ - } else { - return (s8_t)ERR_MEM; - } - - /* { empty or recyclable entry found } */ - LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); - - /* recycle entry (no-op for an already empty entry) */ - arp_table[i].state = ETHARP_STATE_EMPTY; - - /* IP address given? */ - if (ipaddr != NULL) { - /* set IP address */ - ip_addr_set(&arp_table[i].ipaddr, ipaddr); - } - arp_table[i].ctime = 0; - return (err_t)i; -} - -/** - * Update (or insert) a IP/MAC address pair in the ARP cache. - * - * If a pending entry is resolved, any queued packets will be sent - * at this point. - * - * @param ipaddr IP address of the inserted ARP entry. - * @param ethaddr Ethernet address of the inserted ARP entry. - * @param flags Defines behaviour: - * - ETHARP_TRY_HARD Allows ARP to insert this as a new item. If not specified, - * only existing ARP entries will be updated. - * - * @return - * - ERR_OK Succesfully updated ARP cache. - * - ERR_MEM If we could not add a new ARP entry when ETHARP_TRY_HARD was set. - * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. - * - * @see pbuf_free() - */ -static err_t -update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags) -{ - s8_t i, k; - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 3, ("update_arp_entry()\n")); - LWIP_ASSERT("netif->hwaddr_len != 0", netif->hwaddr_len != 0); - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n", - ip4_addr1(ipaddr), ip4_addr2(ipaddr), ip4_addr3(ipaddr), ip4_addr4(ipaddr), - ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2], - ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5])); - /* non-unicast address? */ - if (ip_addr_isany(ipaddr) || - ip_addr_isbroadcast(ipaddr, netif) || - ip_addr_ismulticast(ipaddr)) { - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n")); - return ERR_ARG; - } - /* find or create ARP entry */ - i = find_entry(ipaddr, flags); - /* bail out if no entry could be found */ - if (i < 0) return (err_t)i; - - /* mark it stable */ - arp_table[i].state = ETHARP_STATE_STABLE; - - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: updating stable entry %"S16_F"\n", (s16_t)i)); - /* update address */ - for (k = 0; k < netif->hwaddr_len; ++k) { - arp_table[i].ethaddr.addr[k] = ethaddr->addr[k]; - } - /* reset time stamp */ - arp_table[i].ctime = 0; -/* this is where we will send out queued packets! */ -#if ARP_QUEUEING - while (arp_table[i].p != NULL) { - /* get the first packet on the queue */ - struct pbuf *p = arp_table[i].p; - /* Ethernet header */ - struct eth_hdr *ethhdr = p->payload; - /* remember (and reference) remainder of queue */ - /* note: this will also terminate the p pbuf chain */ - arp_table[i].p = pbuf_dequeue(p); - /* fill-in Ethernet header */ - for (k = 0; k < netif->hwaddr_len; ++k) { - ethhdr->dest.addr[k] = ethaddr->addr[k]; - ethhdr->src.addr[k] = netif->hwaddr[k]; - } - ethhdr->type = htons(ETHTYPE_IP); - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: sending queued IP packet %p.\n", (void *)p)); - /* send the queued IP packet */ - netif->linkoutput(netif, p); - /* free the queued IP packet */ - pbuf_free(p); - } -#endif - return ERR_OK; -} - -/** - * Updates the ARP table using the given IP packet. - * - * Uses the incoming IP packet's source address to update the - * ARP cache for the local network. The function does not alter - * or free the packet. This function must be called before the - * packet p is passed to the IP layer. - * - * @param netif The lwIP network interface on which the IP packet pbuf arrived. - * @param pbuf The IP packet that arrived on netif. - * - * @return NULL - * - * @see pbuf_free() - */ -void -etharp_ip_input(struct netif *netif, struct pbuf *p) -{ - struct ethip_hdr *hdr; - LWIP_ASSERT("netif != NULL", netif != NULL); - /* Only insert an entry if the source IP address of the - incoming IP packet comes from a host on the local network. */ - hdr = p->payload; - /* source is not on the local network? */ - if (!ip_addr_netcmp(&(hdr->ip.src), &(netif->ip_addr), &(netif->netmask))) { - /* do nothing */ - return; - } - - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n")); - /* update ARP table */ - /* @todo We could use ETHARP_TRY_HARD if we think we are going to talk - * back soon (for example, if the destination IP address is ours. */ - update_arp_entry(netif, &(hdr->ip.src), &(hdr->eth.src), 0); -} - - -/** - * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache - * send out queued IP packets. Updates cache with snooped address pairs. - * - * Should be called for incoming ARP packets. The pbuf in the argument - * is freed by this function. - * - * @param netif The lwIP network interface on which the ARP packet pbuf arrived. - * @param pbuf The ARP packet that arrived on netif. Is freed by this function. - * @param ethaddr Ethernet address of netif. - * - * @return NULL - * - * @see pbuf_free() - */ -void -etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p) -{ - struct etharp_hdr *hdr; - /* these are aligned properly, whereas the ARP header fields might not be */ - struct ip_addr sipaddr, dipaddr; - u8_t i; - u8_t for_us; - - LWIP_ASSERT("netif != NULL", netif != NULL); - - /* drop short ARP packets */ - if (p->tot_len < sizeof(struct etharp_hdr)) { - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 1, ("etharp_arp_input: packet dropped, too short (%"S16_F"/%"S16_F")\n", p->tot_len, sizeof(struct etharp_hdr))); - pbuf_free(p); - return; - } - - hdr = p->payload; - - /* get aligned copies of addresses */ - *(struct ip_addr2 *)&sipaddr = hdr->sipaddr; - *(struct ip_addr2 *)&dipaddr = hdr->dipaddr; - - /* this interface is not configured? */ - if (netif->ip_addr.addr == 0) { - for_us = 0; - } else { - /* ARP packet directed to us? */ - for_us = ip_addr_cmp(&dipaddr, &(netif->ip_addr)); - } - - /* ARP message directed to us? */ - if (for_us) { - /* add IP address in ARP cache; assume requester wants to talk to us. - * can result in directly sending the queued packets for this host. */ - update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), ETHARP_TRY_HARD); - /* ARP message not directed to us? */ - } else { - /* update the source IP address in the cache, if present */ - update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), 0); - } - - /* now act on the message itself */ - switch (htons(hdr->opcode)) { - /* ARP request? */ - case ARP_REQUEST: - /* ARP request. If it asked for our address, we send out a - * reply. In any case, we time-stamp any existing ARP entry, - * and possiby send out an IP packet that was queued on it. */ - - LWIP_DEBUGF (ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP request\n")); - /* ARP request for our address? */ - if (for_us) { - - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: replying to ARP request for our IP address\n")); - /* re-use pbuf to send ARP reply */ - hdr->opcode = htons(ARP_REPLY); - - hdr->dipaddr = hdr->sipaddr; - hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr; - - for(i = 0; i < netif->hwaddr_len; ++i) { - hdr->dhwaddr.addr[i] = hdr->shwaddr.addr[i]; - hdr->shwaddr.addr[i] = ethaddr->addr[i]; - hdr->ethhdr.dest.addr[i] = hdr->dhwaddr.addr[i]; - hdr->ethhdr.src.addr[i] = ethaddr->addr[i]; - } - - hdr->hwtype = htons(HWTYPE_ETHERNET); - ARPH_HWLEN_SET(hdr, netif->hwaddr_len); - - hdr->proto = htons(ETHTYPE_IP); - ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr)); - - hdr->ethhdr.type = htons(ETHTYPE_ARP); - /* return ARP reply */ - netif->linkoutput(netif, p); - /* we are not configured? */ - } else if (netif->ip_addr.addr == 0) { - /* { for_us == 0 and netif->ip_addr.addr == 0 } */ - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: we are unconfigured, ARP request ignored.\n")); - /* request was not directed to us */ - } else { - /* { for_us == 0 and netif->ip_addr.addr != 0 } */ - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP request was not for us.\n")); - } - break; - case ARP_REPLY: - /* ARP reply. We already updated the ARP cache earlier. */ - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n")); -#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK) - /* DHCP wants to know about ARP replies from any host with an - * IP address also offered to us by the DHCP server. We do not - * want to take a duplicate IP address on a single network. - * @todo How should we handle redundant (fail-over) interfaces? - * */ - dhcp_arp_reply(netif, &sipaddr); -#endif - break; - default: - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %"S16_F"\n", htons(hdr->opcode))); - break; - } - /* free ARP packet */ - pbuf_free(p); -} - -/** - * Resolve and fill-in Ethernet address header for outgoing packet. - * - * For IP multicast and broadcast, corresponding Ethernet addresses - * are selected and the packet is transmitted on the link. - * - * For unicast addresses, the packet is submitted to etharp_query(). In - * case the IP address is outside the local network, the IP address of - * the gateway is used. - * - * @param netif The lwIP network interface which the IP packet will be sent on. - * @param ipaddr The IP address of the packet destination. - * @param pbuf The pbuf(s) containing the IP packet to be sent. - * - * @return - * - ERR_RTE No route to destination (no gateway to external networks), - * or the return type of either etharp_query() or netif->linkoutput(). - */ -err_t -etharp_output(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q) -{ - struct eth_addr *dest, *srcaddr, mcastaddr; - struct eth_hdr *ethhdr; - u8_t i; - - /* make room for Ethernet header - should not fail */ - if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) { - /* bail out */ - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_output: could not allocate room for header.\n")); - LINK_STATS_INC(link.lenerr); - return ERR_BUF; - } - - /* assume unresolved Ethernet address */ - dest = NULL; - /* Determine on destination hardware address. Broadcasts and multicasts - * are special, other IP addresses are looked up in the ARP table. */ - - /* broadcast destination IP address? */ - if (ip_addr_isbroadcast(ipaddr, netif)) { - /* broadcast on Ethernet also */ - dest = (struct eth_addr *)ðbroadcast; - /* multicast destination IP address? */ - } else if (ip_addr_ismulticast(ipaddr)) { - /* Hash IP multicast address to MAC address.*/ - mcastaddr.addr[0] = 0x01; - mcastaddr.addr[1] = 0x00; - mcastaddr.addr[2] = 0x5e; - mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f; - mcastaddr.addr[4] = ip4_addr3(ipaddr); - mcastaddr.addr[5] = ip4_addr4(ipaddr); - /* destination Ethernet address is multicast */ - dest = &mcastaddr; - /* unicast destination IP address? */ - } else { - /* outside local network? */ - if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) { - /* interface has default gateway? */ - if (netif->gw.addr != 0) { - /* send to hardware address of default gateway IP address */ - ipaddr = &(netif->gw); - /* no default gateway available */ - } else { - /* no route to destination error (default gateway missing) */ - return ERR_RTE; - } - } - /* queue on destination Ethernet address belonging to ipaddr */ - return etharp_query(netif, ipaddr, q); - } - - /* continuation for multicast/broadcast destinations */ - /* obtain source Ethernet address of the given interface */ - srcaddr = (struct eth_addr *)netif->hwaddr; - ethhdr = q->payload; - for (i = 0; i < netif->hwaddr_len; i++) { - ethhdr->dest.addr[i] = dest->addr[i]; - ethhdr->src.addr[i] = srcaddr->addr[i]; - } - ethhdr->type = htons(ETHTYPE_IP); - /* send packet directly on the link */ - return netif->linkoutput(netif, q); -} - -/** - * Send an ARP request for the given IP address and/or queue a packet. - * - * If the IP address was not yet in the cache, a pending ARP cache entry - * is added and an ARP request is sent for the given address. The packet - * is queued on this entry. - * - * If the IP address was already pending in the cache, a new ARP request - * is sent for the given address. The packet is queued on this entry. - * - * If the IP address was already stable in the cache, and a packet is - * given, it is directly sent and no ARP request is sent out. - * - * If the IP address was already stable in the cache, and no packet is - * given, an ARP request is sent out. - * - * @param netif The lwIP network interface on which ipaddr - * must be queried for. - * @param ipaddr The IP address to be resolved. - * @param q If non-NULL, a pbuf that must be delivered to the IP address. - * q is not freed by this function. - * - * @return - * - ERR_BUF Could not make room for Ethernet header. - * - ERR_MEM Hardware address unknown, and no more ARP entries available - * to query for address or queue the packet. - * - ERR_MEM Could not queue packet due to memory shortage. - * - ERR_RTE No route to destination (no gateway to external networks). - * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. - * - */ -err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q) -{ - struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr; - err_t result = ERR_MEM; - s8_t i; /* ARP entry index */ - u8_t k; /* Ethernet address octet index */ - - /* non-unicast address? */ - if (ip_addr_isbroadcast(ipaddr, netif) || - ip_addr_ismulticast(ipaddr) || - ip_addr_isany(ipaddr)) { - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n")); - return ERR_ARG; - } - - /* find entry in ARP cache, ask to create entry if queueing packet */ - i = find_entry(ipaddr, ETHARP_TRY_HARD); - - /* could not find or create entry? */ - if (i < 0) - { - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not create ARP entry\n")); - if (q) LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: packet dropped\n")); - return (err_t)i; - } - - /* mark a fresh entry as pending (we just sent a request) */ - if (arp_table[i].state == ETHARP_STATE_EMPTY) { - arp_table[i].state = ETHARP_STATE_PENDING; - } - - /* { i is either a STABLE or (new or existing) PENDING entry } */ - LWIP_ASSERT("arp_table[i].state == PENDING or STABLE", - ((arp_table[i].state == ETHARP_STATE_PENDING) || - (arp_table[i].state == ETHARP_STATE_STABLE))); - - /* do we have a pending entry? or an implicit query request? */ - if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) { - /* try to resolve it; send out ARP request */ - result = etharp_request(netif, ipaddr); - } - - /* packet given? */ - if (q != NULL) { - /* stable entry? */ - if (arp_table[i].state == ETHARP_STATE_STABLE) { - /* we have a valid IP->Ethernet address mapping, - * fill in the Ethernet header for the outgoing packet */ - struct eth_hdr *ethhdr = q->payload; - for(k = 0; k < netif->hwaddr_len; k++) { - ethhdr->dest.addr[k] = arp_table[i].ethaddr.addr[k]; - ethhdr->src.addr[k] = srcaddr->addr[k]; - } - ethhdr->type = htons(ETHTYPE_IP); - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: sending packet %p\n", (void *)q)); - /* send the packet */ - result = netif->linkoutput(netif, q); - /* pending entry? (either just created or already pending */ - } else if (arp_table[i].state == ETHARP_STATE_PENDING) { -#if ARP_QUEUEING /* queue the given q packet */ - struct pbuf *p; - /* copy any PBUF_REF referenced payloads into PBUF_RAM */ - /* (the caller of lwIP assumes the referenced payload can be - * freed after it returns from the lwIP call that brought us here) */ - p = pbuf_take(q); - /* packet could be taken over? */ - if (p != NULL) { - /* queue packet ... */ - if (arp_table[i].p == NULL) { - /* ... in the empty queue */ - pbuf_ref(p); - arp_table[i].p = p; -#if 0 /* multi-packet-queueing disabled, see bug #11400 */ - } else { - /* ... at tail of non-empty queue */ - pbuf_queue(arp_table[i].p, p); -#endif - } - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i)); - result = ERR_OK; - } else { - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); - /* { result == ERR_MEM } through initialization */ - } -#else /* ARP_QUEUEING == 0 */ - /* q && state == PENDING && ARP_QUEUEING == 0 => result = ERR_MEM */ - /* { result == ERR_MEM } through initialization */ - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: Ethernet destination address unknown, queueing disabled, packet %p dropped\n", (void *)q)); -#endif - } - } - return result; -} - -err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr) -{ - struct pbuf *p; - struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr; - err_t result = ERR_OK; - u8_t k; /* ARP entry index */ - - /* allocate a pbuf for the outgoing ARP request packet */ - p = pbuf_alloc(PBUF_LINK, sizeof(struct etharp_hdr), PBUF_RAM); - /* could allocate a pbuf for an ARP request? */ - if (p != NULL) { - struct etharp_hdr *hdr = p->payload; - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_request: sending ARP request.\n")); - hdr->opcode = htons(ARP_REQUEST); - for (k = 0; k < netif->hwaddr_len; k++) - { - hdr->shwaddr.addr[k] = srcaddr->addr[k]; - /* the hardware address is what we ask for, in - * a request it is a don't-care value, we use zeroes */ - hdr->dhwaddr.addr[k] = 0x00; - } - hdr->dipaddr = *(struct ip_addr2 *)ipaddr; - hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr; - - hdr->hwtype = htons(HWTYPE_ETHERNET); - ARPH_HWLEN_SET(hdr, netif->hwaddr_len); - - hdr->proto = htons(ETHTYPE_IP); - ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr)); - for (k = 0; k < netif->hwaddr_len; ++k) - { - /* broadcast to all network interfaces on the local network */ - hdr->ethhdr.dest.addr[k] = 0xff; - hdr->ethhdr.src.addr[k] = srcaddr->addr[k]; - } - hdr->ethhdr.type = htons(ETHTYPE_ARP); - /* send ARP query */ - result = netif->linkoutput(netif, p); - /* free ARP query packet */ - pbuf_free(p); - p = NULL; - /* could not allocate pbuf for ARP request */ - } else { - result = ERR_MEM; - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_request: could not allocate pbuf for ARP request.\n")); - } - return result; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ethernetif.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ethernetif.c deleted file mode 100644 index 0c14e8de5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ethernetif.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* - * This file is a skeleton for developing Ethernet network interface - * drivers for lwIP. Add code to the low_level functions and do a - * search-and-replace for the word "ethernetif" to replace it with - * something that better describes your network interface. - */ - -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include - -#include "netif/etharp.h" - -/* Define those to better describe your network interface. */ -#define IFNAME0 'e' -#define IFNAME1 'n' - -struct ethernetif { - struct eth_addr *ethaddr; - /* Add whatever per-interface state that is needed here. */ -}; - -static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}}; - -/* Forward declarations. */ -static void ethernetif_input(struct netif *netif); -static err_t ethernetif_output(struct netif *netif, struct pbuf *p, - struct ip_addr *ipaddr); - -static void -low_level_init(struct netif *netif) -{ - struct ethernetif *ethernetif = netif->state; - - /* set MAC hardware address length */ - netif->hwaddr_len = 6; - - /* set MAC hardware address */ - netif->hwaddr[0] = ; - ... - netif->hwaddr[5] = ; - - /* maximum transfer unit */ - netif->mtu = 1500; - - /* broadcast capability */ - netif->flags = NETIF_FLAG_BROADCAST; - - /* Do whatever else is needed to initialize interface. */ -} - -/* - * low_level_output(): - * - * Should do the actual transmission of the packet. The packet is - * contained in the pbuf that is passed to the function. This pbuf - * might be chained. - * - */ - -static err_t -low_level_output(struct netif *netif, struct pbuf *p) -{ - struct ethernetif *ethernetif = netif->state; - struct pbuf *q; - - initiate transfer(); - -#if ETH_PAD_SIZE - pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ -#endif - - for(q = p; q != NULL; q = q->next) { - /* Send the data from the pbuf to the interface, one pbuf at a - time. The size of the data in each pbuf is kept in the ->len - variable. */ - send data from(q->payload, q->len); - } - - signal that packet should be sent(); - -#if ETH_PAD_SIZE - pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ -#endif - -#if LINK_STATS - lwip_stats.link.xmit++; -#endif /* LINK_STATS */ - - return ERR_OK; -} - -/* - * low_level_input(): - * - * Should allocate a pbuf and transfer the bytes of the incoming - * packet from the interface into the pbuf. - * - */ - -static struct pbuf * -low_level_input(struct netif *netif) -{ - struct ethernetif *ethernetif = netif->state; - struct pbuf *p, *q; - u16_t len; - - /* Obtain the size of the packet and put it into the "len" - variable. */ - len = ; - -#if ETH_PAD_SIZE - len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ -#endif - - /* We allocate a pbuf chain of pbufs from the pool. */ - p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); - - if (p != NULL) { - -#if ETH_PAD_SIZE - pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ -#endif - - /* We iterate over the pbuf chain until we have read the entire - * packet into the pbuf. */ - for(q = p; q != NULL; q = q->next) { - /* Read enough bytes to fill this pbuf in the chain. The - * available data in the pbuf is given by the q->len - * variable. */ - read data into(q->payload, q->len); - } - acknowledge that packet has been read(); - -#if ETH_PAD_SIZE - pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ -#endif - -#if LINK_STATS - lwip_stats.link.recv++; -#endif /* LINK_STATS */ - } else { - drop packet(); -#if LINK_STATS - lwip_stats.link.memerr++; - lwip_stats.link.drop++; -#endif /* LINK_STATS */ - } - - return p; -} - -/* - * ethernetif_output(): - * - * This function is called by the TCP/IP stack when an IP packet - * should be sent. It calls the function called low_level_output() to - * do the actual transmission of the packet. - * - */ - -static err_t -ethernetif_output(struct netif *netif, struct pbuf *p, - struct ip_addr *ipaddr) -{ - - /* resolve hardware address, then send (or queue) packet */ - return etharp_output(netif, ipaddr, p); - -} - -/* - * ethernetif_input(): - * - * This function should be called when a packet is ready to be read - * from the interface. It uses the function low_level_input() that - * should handle the actual reception of bytes from the network - * interface. - * - */ - -static void -ethernetif_input(struct netif *netif) -{ - struct ethernetif *ethernetif; - struct eth_hdr *ethhdr; - struct pbuf *p; - - ethernetif = netif->state; - - /* move received packet into a new pbuf */ - p = low_level_input(netif); - /* no packet could be read, silently ignore this */ - if (p == NULL) return; - /* points to packet payload, which starts with an Ethernet header */ - ethhdr = p->payload; - -#if LINK_STATS - lwip_stats.link.recv++; -#endif /* LINK_STATS */ - - ethhdr = p->payload; - - switch (htons(ethhdr->type)) { - /* IP packet? */ - case ETHTYPE_IP: - /* update ARP table */ - etharp_ip_input(netif, p); - /* skip Ethernet header */ - pbuf_header(p, -sizeof(struct eth_hdr)); - /* pass to network layer */ - netif->input(p, netif); - break; - - case ETHTYPE_ARP: - /* pass p to ARP module */ - etharp_arp_input(netif, ethernetif->ethaddr, p); - break; - default: - pbuf_free(p); - p = NULL; - break; - } -} - -static void -arp_timer(void *arg) -{ - etharp_tmr(); - sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL); -} - -/* - * ethernetif_init(): - * - * Should be called at the beginning of the program to set up the - * network interface. It calls the function low_level_init() to do the - * actual setup of the hardware. - * - */ - -err_t -ethernetif_init(struct netif *netif) -{ - struct ethernetif *ethernetif; - - ethernetif = mem_malloc(sizeof(struct ethernetif)); - - if (ethernetif == NULL) - { - LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n")); - return ERR_MEM; - } - - netif->state = ethernetif; - netif->name[0] = IFNAME0; - netif->name[1] = IFNAME1; - netif->output = ethernetif_output; - netif->linkoutput = low_level_output; - - ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]); - - low_level_init(netif); - - etharp_init(); - - sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL); - - return ERR_OK; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/loopif.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/loopif.c deleted file mode 100644 index 0464cb8e8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/loopif.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#include "lwip/opt.h" - -#if LWIP_HAVE_LOOPIF - -#include "netif/loopif.h" -#include "lwip/mem.h" - -#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP) -#include "netif/tcpdump.h" -#endif /* LWIP_DEBUG && LWIP_TCPDUMP */ - -#include "lwip/tcp.h" -#include "lwip/ip.h" - -static void -loopif_input( void * arg ) -{ - struct netif *netif = (struct netif *)( ((void **)arg)[ 0 ] ); - struct pbuf *r = (struct pbuf *)( ((void **)arg)[ 1 ] ); - - mem_free( arg ); - netif -> input( r, netif ); -} - -static err_t -loopif_output(struct netif *netif, struct pbuf *p, - struct ip_addr *ipaddr) -{ - struct pbuf *q, *r; - u8_t *ptr; - void **arg; - -#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP) - tcpdump(p); -#endif /* LWIP_DEBUG && LWIP_TCPDUMP */ - - r = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); - if (r != NULL) { - ptr = r->payload; - - for(q = p; q != NULL; q = q->next) { - memcpy(ptr, q->payload, q->len); - ptr += q->len; - } - - arg = mem_malloc( sizeof( void *[2])); - if( NULL == arg ) { - return ERR_MEM; - } - - arg[0] = netif; - arg[1] = r; - /** - * workaround (patch #1779) to try to prevent bug #2595: - * When connecting to "localhost" with the loopif interface, - * tcp_output doesn't get the opportunity to finnish sending the - * segment before tcp_process gets it, resulting in tcp_process - * referencing pcb->unacked-> which still is NULL. - * - * TODO: Is there still a race condition here? Leon - */ - sys_timeout( 1, loopif_input, arg ); - - return ERR_OK; - } - return ERR_MEM; -} - -err_t -loopif_init(struct netif *netif) -{ - netif->name[0] = 'l'; - netif->name[1] = 'o'; -#if 0 /** TODO: I think this should be enabled, or not? Leon */ - netif->input = loopif_input; -#endif - netif->output = loopif_output; - return ERR_OK; -} - -#endif /* LWIP_HAVE_LOOPIF */ - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/auth.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/auth.c deleted file mode 100644 index 333496402..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/auth.c +++ /dev/null @@ -1,927 +0,0 @@ -/***************************************************************************** -* auth.c - Network Authentication and Phase Control program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* Copyright (c) 1997 by Global Election Systems Inc. All rights reserved. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-08 Guy Lancaster , Global Election Systems Inc. -* Ported from public pppd code. -*****************************************************************************/ -/* - * auth.c - PPP authentication and phase control. - * - * Copyright (c) 1993 The Australian National University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by the Australian National University. The name of the University - * may not be used to endorse or promote products derived from this - * software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include "ppp.h" -#if PPP_SUPPORT > 0 -#include "fsm.h" -#include "lcp.h" -#include "pap.h" -#include "chap.h" -#include "auth.h" -#include "ipcp.h" - -#if CBCP_SUPPORT > 0 -#include "cbcp.h" -#endif - -#include "pppdebug.h" - - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ - -/* Bits in auth_pending[] */ -#define PAP_WITHPEER 1 -#define PAP_PEER 2 -#define CHAP_WITHPEER 4 -#define CHAP_PEER 8 - - - -/************************/ -/*** LOCAL DATA TYPES ***/ -/************************/ -/* Used for storing a sequence of words. Usually malloced. */ -struct wordlist { - struct wordlist *next; - char word[1]; -}; - - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -extern char *crypt (const char *, const char *); - -/* Prototypes for procedures local to this file. */ - -static void network_phase (int); -static void check_idle (void *); -static void connect_time_expired (void *); -#if 0 -static int login (char *, char *, char **, int *); -#endif -static void logout (void); -static int null_login (int); -static int get_pap_passwd (int, char *, char *); -static int have_pap_secret (void); -static int have_chap_secret (char *, char *, u32_t); -static int ip_addr_check (u32_t, struct wordlist *); -#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */ -static void set_allowed_addrs(int unit, struct wordlist *addrs); -static void free_wordlist (struct wordlist *); -#endif -#if CBCP_SUPPORT > 0 -static void callback_phase (int); -#endif - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 -/* The name by which the peer authenticated itself to us. */ -static char peer_authname[MAXNAMELEN]; -#endif - -/* Records which authentication operations haven't completed yet. */ -static int auth_pending[NUM_PPP]; - -/* Set if we have successfully called login() */ -static int logged_in; - -/* Set if we have run the /etc/ppp/auth-up script. */ -static int did_authup; - -/* List of addresses which the peer may use. */ -static struct wordlist *addresses[NUM_PPP]; - -/* Number of network protocols which we have opened. */ -static int num_np_open; - -/* Number of network protocols which have come up. */ -static int num_np_up; - -#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 -/* Set if we got the contents of passwd[] from the pap-secrets file. */ -static int passwd_from_file; -#endif - - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * An Open on LCP has requested a change from Dead to Establish phase. - * Do what's necessary to bring the physical layer up. - */ -void link_required(int unit) -{ - AUTHDEBUG((LOG_INFO, "link_required: %d\n", unit)); -} - -/* - * LCP has terminated the link; go to the Dead phase and take the - * physical layer down. - */ -void link_terminated(int unit) -{ - AUTHDEBUG((LOG_INFO, "link_terminated: %d\n", unit)); - - if (lcp_phase[unit] == PHASE_DEAD) - return; - if (logged_in) - logout(); - lcp_phase[unit] = PHASE_DEAD; - AUTHDEBUG((LOG_NOTICE, "Connection terminated.\n")); - pppMainWakeup(unit); -} - -/* - * LCP has gone down; it will either die or try to re-establish. - */ -void link_down(int unit) -{ - int i; - struct protent *protp; - - AUTHDEBUG((LOG_INFO, "link_down: %d\n", unit)); - if (did_authup) { - /* XXX Do link down processing. */ - did_authup = 0; - } - for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { - if (!protp->enabled_flag) - continue; - if (protp->protocol != PPP_LCP && protp->lowerdown != NULL) - (*protp->lowerdown)(unit); - if (protp->protocol < 0xC000 && protp->close != NULL) - (*protp->close)(unit, "LCP down"); - } - num_np_open = 0; - num_np_up = 0; - if (lcp_phase[unit] != PHASE_DEAD) - lcp_phase[unit] = PHASE_TERMINATE; - pppMainWakeup(unit); -} - -/* - * The link is established. - * Proceed to the Dead, Authenticate or Network phase as appropriate. - */ -void link_established(int unit) -{ - int auth; - int i; - struct protent *protp; - lcp_options *wo = &lcp_wantoptions[unit]; - lcp_options *go = &lcp_gotoptions[unit]; -#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 - lcp_options *ho = &lcp_hisoptions[unit]; -#endif - - AUTHDEBUG((LOG_INFO, "link_established: %d\n", unit)); - /* - * Tell higher-level protocols that LCP is up. - */ - for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) - if (protp->protocol != PPP_LCP && protp->enabled_flag - && protp->lowerup != NULL) - (*protp->lowerup)(unit); - - if (ppp_settings.auth_required && !(go->neg_chap || go->neg_upap)) { - /* - * We wanted the peer to authenticate itself, and it refused: - * treat it as though it authenticated with PAP using a username - * of "" and a password of "". If that's not OK, boot it out. - */ - if (!wo->neg_upap || !null_login(unit)) { - AUTHDEBUG((LOG_WARNING, "peer refused to authenticate\n")); - lcp_close(unit, "peer refused to authenticate"); - return; - } - } - - lcp_phase[unit] = PHASE_AUTHENTICATE; - auth = 0; -#if CHAP_SUPPORT > 0 - if (go->neg_chap) { - ChapAuthPeer(unit, ppp_settings.our_name, go->chap_mdtype); - auth |= CHAP_PEER; - } -#endif -#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0 - else -#endif -#if PAP_SUPPORT > 0 - if (go->neg_upap) { - upap_authpeer(unit); - auth |= PAP_PEER; - } -#endif -#if CHAP_SUPPORT > 0 - if (ho->neg_chap) { - ChapAuthWithPeer(unit, ppp_settings.user, ho->chap_mdtype); - auth |= CHAP_WITHPEER; - } -#endif -#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0 - else -#endif -#if PAP_SUPPORT > 0 - if (ho->neg_upap) { - if (ppp_settings.passwd[0] == 0) { - passwd_from_file = 1; - if (!get_pap_passwd(unit, ppp_settings.user, ppp_settings.passwd)) - AUTHDEBUG((LOG_ERR, "No secret found for PAP login\n")); - } - upap_authwithpeer(unit, ppp_settings.user, ppp_settings.passwd); - auth |= PAP_WITHPEER; - } -#endif - auth_pending[unit] = auth; - - if (!auth) - network_phase(unit); -} - - -/* - * The peer has failed to authenticate himself using `protocol'. - */ -void auth_peer_fail(int unit, u16_t protocol) -{ - AUTHDEBUG((LOG_INFO, "auth_peer_fail: %d proto=%X\n", unit, protocol)); - /* - * Authentication failure: take the link down - */ - lcp_close(unit, "Authentication failed"); -} - - -#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 -/* - * The peer has been successfully authenticated using `protocol'. - */ -void auth_peer_success(int unit, u16_t protocol, char *name, int namelen) -{ - int pbit; - - AUTHDEBUG((LOG_INFO, "auth_peer_success: %d proto=%X\n", unit, protocol)); - switch (protocol) { - case PPP_CHAP: - pbit = CHAP_PEER; - break; - case PPP_PAP: - pbit = PAP_PEER; - break; - default: - AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n", - protocol)); - return; - } - - /* - * Save the authenticated name of the peer for later. - */ - if (namelen > sizeof(peer_authname) - 1) - namelen = sizeof(peer_authname) - 1; - BCOPY(name, peer_authname, namelen); - peer_authname[namelen] = 0; - - /* - * If there is no more authentication still to be done, - * proceed to the network (or callback) phase. - */ - if ((auth_pending[unit] &= ~pbit) == 0) - network_phase(unit); -} - -/* - * We have failed to authenticate ourselves to the peer using `protocol'. - */ -void auth_withpeer_fail(int unit, u16_t protocol) -{ - int errCode = PPPERR_AUTHFAIL; - - AUTHDEBUG((LOG_INFO, "auth_withpeer_fail: %d proto=%X\n", unit, protocol)); - if (passwd_from_file) - BZERO(ppp_settings.passwd, MAXSECRETLEN); - /* - * XXX Warning: the unit number indicates the interface which is - * not necessarily the PPP connection. It works here as long - * as we are only supporting PPP interfaces. - */ - pppIOCtl(unit, PPPCTLS_ERRCODE, &errCode); - - /* - * We've failed to authenticate ourselves to our peer. - * He'll probably take the link down, and there's not much - * we can do except wait for that. - */ -} - -/* - * We have successfully authenticated ourselves with the peer using `protocol'. - */ -void auth_withpeer_success(int unit, u16_t protocol) -{ - int pbit; - - AUTHDEBUG((LOG_INFO, "auth_withpeer_success: %d proto=%X\n", unit, protocol)); - switch (protocol) { - case PPP_CHAP: - pbit = CHAP_WITHPEER; - break; - case PPP_PAP: - if (passwd_from_file) - BZERO(ppp_settings.passwd, MAXSECRETLEN); - pbit = PAP_WITHPEER; - break; - default: - AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n", - protocol)); - pbit = 0; - } - - /* - * If there is no more authentication still being done, - * proceed to the network (or callback) phase. - */ - if ((auth_pending[unit] &= ~pbit) == 0) - network_phase(unit); -} -#endif - - -/* - * np_up - a network protocol has come up. - */ -void np_up(int unit, u16_t proto) -{ - AUTHDEBUG((LOG_INFO, "np_up: %d proto=%X\n", unit, proto)); - if (num_np_up == 0) { - AUTHDEBUG((LOG_INFO, "np_up: maxconnect=%d idle_time_limit=%d\n",ppp_settings.maxconnect,ppp_settings.idle_time_limit)); - /* - * At this point we consider that the link has come up successfully. - */ - if (ppp_settings.idle_time_limit > 0) - TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit); - - /* - * Set a timeout to close the connection once the maximum - * connect time has expired. - */ - if (ppp_settings.maxconnect > 0) - TIMEOUT(connect_time_expired, 0, ppp_settings.maxconnect); - } - ++num_np_up; -} - -/* - * np_down - a network protocol has gone down. - */ -void np_down(int unit, u16_t proto) -{ - AUTHDEBUG((LOG_INFO, "np_down: %d proto=%X\n", unit, proto)); - if (--num_np_up == 0 && ppp_settings.idle_time_limit > 0) { - UNTIMEOUT(check_idle, NULL); - } -} - -/* - * np_finished - a network protocol has finished using the link. - */ -void np_finished(int unit, u16_t proto) -{ - AUTHDEBUG((LOG_INFO, "np_finished: %d proto=%X\n", unit, proto)); - if (--num_np_open <= 0) { - /* no further use for the link: shut up shop. */ - lcp_close(0, "No network protocols running"); - } -} - -/* - * auth_reset - called when LCP is starting negotiations to recheck - * authentication options, i.e. whether we have appropriate secrets - * to use for authenticating ourselves and/or the peer. - */ -void auth_reset(int unit) -{ - lcp_options *go = &lcp_gotoptions[unit]; - lcp_options *ao = &lcp_allowoptions[0]; - ipcp_options *ipwo = &ipcp_wantoptions[0]; - u32_t remote; - - AUTHDEBUG((LOG_INFO, "auth_reset: %d\n", unit)); - ao->neg_upap = !ppp_settings.refuse_pap && (ppp_settings.passwd[0] != 0 || get_pap_passwd(unit, NULL, NULL)); - ao->neg_chap = !ppp_settings.refuse_chap && ppp_settings.passwd[0] != 0 /*have_chap_secret(ppp_settings.user, ppp_settings.remote_name, (u32_t)0)*/; - - if (go->neg_upap && !have_pap_secret()) - go->neg_upap = 0; - if (go->neg_chap) { - remote = ipwo->accept_remote? 0: ipwo->hisaddr; - if (!have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote)) - go->neg_chap = 0; - } -} - - -#if PAP_SUPPORT > 0 -/* - * check_passwd - Check the user name and passwd against the PAP secrets - * file. If requested, also check against the system password database, - * and login the user if OK. - * - * returns: - * UPAP_AUTHNAK: Authentication failed. - * UPAP_AUTHACK: Authentication succeeded. - * In either case, msg points to an appropriate message. - */ -int check_passwd( - int unit, - char *auser, - int userlen, - char *apasswd, - int passwdlen, - char **msg, - int *msglen -) -{ -#if 1 - *msg = (char *) 0; - return UPAP_AUTHACK; /* XXX Assume all entries OK. */ -#else - int ret = 0; - struct wordlist *addrs = NULL; - char passwd[256], user[256]; - char secret[MAXWORDLEN]; - static u_short attempts = 0; - - /* - * Make copies of apasswd and auser, then null-terminate them. - */ - BCOPY(apasswd, passwd, passwdlen); - passwd[passwdlen] = '\0'; - BCOPY(auser, user, userlen); - user[userlen] = '\0'; - *msg = (char *) 0; - - /* XXX Validate user name and password. */ - ret = UPAP_AUTHACK; /* XXX Assume all entries OK. */ - - if (ret == UPAP_AUTHNAK) { - if (*msg == (char *) 0) - *msg = "Login incorrect"; - *msglen = strlen(*msg); - /* - * Frustrate passwd stealer programs. - * Allow 10 tries, but start backing off after 3 (stolen from login). - * On 10'th, drop the connection. - */ - if (attempts++ >= 10) { - AUTHDEBUG((LOG_WARNING, "%d LOGIN FAILURES BY %s\n", attempts, user)); - /*ppp_panic("Excess Bad Logins");*/ - } - if (attempts > 3) { - sys_msleep((attempts - 3) * 5); - } - if (addrs != NULL) { - free_wordlist(addrs); - } - } else { - attempts = 0; /* Reset count */ - if (*msg == (char *) 0) - *msg = "Login ok"; - *msglen = strlen(*msg); - set_allowed_addrs(unit, addrs); - } - - BZERO(passwd, sizeof(passwd)); - BZERO(secret, sizeof(secret)); - - return ret; -#endif -} -#endif - - -/* - * auth_ip_addr - check whether the peer is authorized to use - * a given IP address. Returns 1 if authorized, 0 otherwise. - */ -int auth_ip_addr(int unit, u32_t addr) -{ - return ip_addr_check(addr, addresses[unit]); -} - -/* - * bad_ip_adrs - return 1 if the IP address is one we don't want - * to use, such as an address in the loopback net or a multicast address. - * addr is in network byte order. - */ -int bad_ip_adrs(u32_t addr) -{ - addr = ntohl(addr); - return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET - || IN_MULTICAST(addr) || IN_BADCLASS(addr); -} - - -#if CHAP_SUPPORT > 0 -/* - * get_secret - open the CHAP secret file and return the secret - * for authenticating the given client on the given server. - * (We could be either client or server). - */ -int get_secret( - int unit, - char *client, - char *server, - char *secret, - int *secret_len, - int save_addrs -) -{ -#if 1 - int len; - struct wordlist *addrs; - - addrs = NULL; - - if(!client || !client[0] || strcmp(client, ppp_settings.user)) { - return 0; - } - - len = strlen(ppp_settings.passwd); - if (len > MAXSECRETLEN) { - AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server)); - len = MAXSECRETLEN; - } - BCOPY(ppp_settings.passwd, secret, len); - *secret_len = len; - - return 1; -#else - int ret = 0, len; - struct wordlist *addrs; - char secbuf[MAXWORDLEN]; - - addrs = NULL; - secbuf[0] = 0; - - /* XXX Find secret. */ - if (ret < 0) - return 0; - - if (save_addrs) - set_allowed_addrs(unit, addrs); - - len = strlen(secbuf); - if (len > MAXSECRETLEN) { - AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server)); - len = MAXSECRETLEN; - } - BCOPY(secbuf, secret, len); - BZERO(secbuf, sizeof(secbuf)); - *secret_len = len; - - return 1; -#endif -} -#endif - - -#if 0 /* UNUSED */ -/* - * auth_check_options - called to check authentication options. - */ -void auth_check_options(void) -{ - lcp_options *wo = &lcp_wantoptions[0]; - int can_auth; - ipcp_options *ipwo = &ipcp_wantoptions[0]; - u32_t remote; - - /* Default our_name to hostname, and user to our_name */ - if (ppp_settings.our_name[0] == 0 || ppp_settings.usehostname) - strcpy(ppp_settings.our_name, ppp_settings.hostname); - if (ppp_settings.user[0] == 0) - strcpy(ppp_settings.user, ppp_settings.our_name); - - /* If authentication is required, ask peer for CHAP or PAP. */ - if (ppp_settings.auth_required && !wo->neg_chap && !wo->neg_upap) { - wo->neg_chap = 1; - wo->neg_upap = 1; - } - - /* - * Check whether we have appropriate secrets to use - * to authenticate the peer. - */ - can_auth = wo->neg_upap && have_pap_secret(); - if (!can_auth && wo->neg_chap) { - remote = ipwo->accept_remote? 0: ipwo->hisaddr; - can_auth = have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote); - } - - if (ppp_settings.auth_required && !can_auth) { - ppp_panic("No auth secret"); - } -} -#endif - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ -/* - * Proceed to the network phase. - */ -static void network_phase(int unit) -{ - int i; - struct protent *protp; - lcp_options *go = &lcp_gotoptions[unit]; - - /* - * If the peer had to authenticate, run the auth-up script now. - */ - if ((go->neg_chap || go->neg_upap) && !did_authup) { - /* XXX Do setup for peer authentication. */ - did_authup = 1; - } - -#if CBCP_SUPPORT > 0 - /* - * If we negotiated callback, do it now. - */ - if (go->neg_cbcp) { - lcp_phase[unit] = PHASE_CALLBACK; - (*cbcp_protent.open)(unit); - return; - } -#endif - - lcp_phase[unit] = PHASE_NETWORK; - for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) - if (protp->protocol < 0xC000 && protp->enabled_flag - && protp->open != NULL) { - (*protp->open)(unit); - if (protp->protocol != PPP_CCP) - ++num_np_open; - } - - if (num_np_open == 0) - /* nothing to do */ - lcp_close(0, "No network protocols running"); -} - -/* - * check_idle - check whether the link has been idle for long - * enough that we can shut it down. - */ -static void check_idle(void *arg) -{ - struct ppp_idle idle; - u_short itime; - - (void)arg; - if (!get_idle_time(0, &idle)) - return; - itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle); - if (itime >= ppp_settings.idle_time_limit) { - /* link is idle: shut it down. */ - AUTHDEBUG((LOG_INFO, "Terminating connection due to lack of activity.\n")); - lcp_close(0, "Link inactive"); - } else { - TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit - itime); - } -} - -/* - * connect_time_expired - log a message and close the connection. - */ -static void connect_time_expired(void *arg) -{ - (void)arg; - - AUTHDEBUG((LOG_INFO, "Connect time expired\n")); - lcp_close(0, "Connect time expired"); /* Close connection */ -} - -#if 0 -/* - * login - Check the user name and password against the system - * password database, and login the user if OK. - * - * returns: - * UPAP_AUTHNAK: Login failed. - * UPAP_AUTHACK: Login succeeded. - * In either case, msg points to an appropriate message. - */ -static int login(char *user, char *passwd, char **msg, int *msglen) -{ - /* XXX Fail until we decide that we want to support logins. */ - return (UPAP_AUTHNAK); -} -#endif - -/* - * logout - Logout the user. - */ -static void logout(void) -{ - logged_in = 0; -} - - -/* - * null_login - Check if a username of "" and a password of "" are - * acceptable, and iff so, set the list of acceptable IP addresses - * and return 1. - */ -static int null_login(int unit) -{ - (void)unit; - /* XXX Fail until we decide that we want to support logins. */ - return 0; -} - - -/* - * get_pap_passwd - get a password for authenticating ourselves with - * our peer using PAP. Returns 1 on success, 0 if no suitable password - * could be found. - */ -static int get_pap_passwd(int unit, char *user, char *passwd) -{ -/* normally we would reject PAP if no password is provided, - but this causes problems with some providers (like CHT in Taiwan) - who incorrectly request PAP and expect a bogus/empty password, so - always provide a default user/passwd of "none"/"none" -*/ - if(user) - strcpy(user, "none"); - if(passwd) - strcpy(passwd, "none"); - - return 1; -} - - -/* - * have_pap_secret - check whether we have a PAP file with any - * secrets that we could possibly use for authenticating the peer. - */ -static int have_pap_secret(void) -{ - /* XXX Fail until we set up our passwords. */ - return 0; -} - - -/* - * have_chap_secret - check whether we have a CHAP file with a - * secret that we could possibly use for authenticating `client' - * on `server'. Either can be the null string, meaning we don't - * know the identity yet. - */ -static int have_chap_secret(char *client, char *server, u32_t remote) -{ - (void)client; - (void)server; - (void)remote; - /* XXX Fail until we set up our passwords. */ - return 0; -} - - -#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */ -/* - * set_allowed_addrs() - set the list of allowed addresses. - */ -static void set_allowed_addrs(int unit, struct wordlist *addrs) -{ - if (addresses[unit] != NULL) - free_wordlist(addresses[unit]); - addresses[unit] = addrs; - -#if 0 - /* - * If there's only one authorized address we might as well - * ask our peer for that one right away - */ - if (addrs != NULL && addrs->next == NULL) { - char *p = addrs->word; - struct ipcp_options *wo = &ipcp_wantoptions[unit]; - u32_t a; - struct hostent *hp; - - if (wo->hisaddr == 0 && *p != '!' && *p != '-' - && strchr(p, '/') == NULL) { - hp = gethostbyname(p); - if (hp != NULL && hp->h_addrtype == AF_INET) - a = *(u32_t *)hp->h_addr; - else - a = inet_addr(p); - if (a != (u32_t) -1) - wo->hisaddr = a; - } - } -#endif -} -#endif - -static int ip_addr_check(u32_t addr, struct wordlist *addrs) -{ - - /* don't allow loopback or multicast address */ - if (bad_ip_adrs(addr)) - return 0; - - if (addrs == NULL) - return !ppp_settings.auth_required; /* no addresses authorized */ - - /* XXX All other addresses allowed. */ - return 1; -} - -#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT */ -/* - * free_wordlist - release memory allocated for a wordlist. - */ -static void free_wordlist(struct wordlist *wp) -{ - struct wordlist *next; - - while (wp != NULL) { - next = wp->next; - free(wp); - wp = next; - } -} -#endif - -#endif /* PPP_SUPPORT */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/auth.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/auth.h deleted file mode 100644 index d6a5de5b7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/auth.h +++ /dev/null @@ -1,94 +0,0 @@ -/***************************************************************************** -* auth.h - PPP Authentication and phase control header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1998 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD pppd.h. -*****************************************************************************/ -/* - * pppd.h - PPP daemon global declarations. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - */ - -#ifndef AUTH_H -#define AUTH_H - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ -void link_required (int); /* we are starting to use the link */ -void link_terminated (int); /* we are finished with the link */ -void link_down (int); /* the LCP layer has left the Opened state */ -void link_established (int); /* the link is up; authenticate now */ -void np_up (int, u16_t); /* a network protocol has come up */ -void np_down (int, u16_t); /* a network protocol has gone down */ -void np_finished (int, u16_t); /* a network protocol no longer needs link */ -void auth_peer_fail (int, u16_t);/* peer failed to authenticate itself */ - -/* peer successfully authenticated itself */ -void auth_peer_success (int, u16_t, char *, int); - -/* we failed to authenticate ourselves */ -void auth_withpeer_fail (int, u16_t); - -/* we successfully authenticated ourselves */ -void auth_withpeer_success (int, u16_t); - -/* check authentication options supplied */ -void auth_check_options (void); -void auth_reset (int); /* check what secrets we have */ - -/* Check peer-supplied username/password */ -int check_passwd (int, char *, int, char *, int, char **, int *); - -/* get "secret" for chap */ -int get_secret (int, char *, char *, char *, int *, int); - -/* check if IP address is authorized */ -int auth_ip_addr (int, u32_t); - -/* check if IP address is unreasonable */ -int bad_ip_adrs (u32_t); - - -#endif /* AUTH_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/chap.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/chap.c deleted file mode 100644 index 4d1dc0d24..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/chap.c +++ /dev/null @@ -1,872 +0,0 @@ -/*** WARNING - THIS HAS NEVER BEEN FINISHED ***/ -/***************************************************************************** -* chap.c - Network Challenge Handshake Authentication Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original based on BSD chap.c. -*****************************************************************************/ -/* - * chap.c - Challenge Handshake Authentication Protocol. - * - * Copyright (c) 1993 The Australian National University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by the Australian National University. The name of the University - * may not be used to endorse or promote products derived from this - * software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * Copyright (c) 1991 Gregory M. Christy. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Gregory M. Christy. The name of the author may not be used to - * endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include "ppp.h" -#if PPP_SUPPORT > 0 -#include "magic.h" - -#if CHAP_SUPPORT > 0 - -#include "randm.h" -#include "auth.h" -#include "md5.h" -#include "chap.h" -#include "chpms.h" -#include "pppdebug.h" - - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ - - -/************************/ -/*** LOCAL DATA TYPES ***/ -/************************/ - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -/* - * Protocol entry points. - */ -static void ChapInit (int); -static void ChapLowerUp (int); -static void ChapLowerDown (int); -static void ChapInput (int, u_char *, int); -static void ChapProtocolReject (int); -static int ChapPrintPkt (u_char *, int, - void (*) (void *, char *, ...), void *); - -static void ChapChallengeTimeout (void *); -static void ChapResponseTimeout (void *); -static void ChapReceiveChallenge (chap_state *, u_char *, int, int); -static void ChapRechallenge (void *); -static void ChapReceiveResponse (chap_state *, u_char *, int, int); -static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len); -static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len); -static void ChapSendStatus (chap_state *, int); -static void ChapSendChallenge (chap_state *); -static void ChapSendResponse (chap_state *); -static void ChapGenChallenge (chap_state *); - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ -chap_state chap[NUM_PPP]; /* CHAP state; one for each unit */ - -struct protent chap_protent = { - PPP_CHAP, - ChapInit, - ChapInput, - ChapProtocolReject, - ChapLowerUp, - ChapLowerDown, - NULL, - NULL, -#if 0 - ChapPrintPkt, - NULL, -#endif - 1, - "CHAP", -#if 0 - NULL, - NULL, - NULL -#endif -}; - - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -static char *ChapCodenames[] = { - "Challenge", "Response", "Success", "Failure" -}; - - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * ChapAuthWithPeer - Authenticate us with our peer (start client). - * - */ -void ChapAuthWithPeer(int unit, char *our_name, int digest) -{ - chap_state *cstate = &chap[unit]; - - cstate->resp_name = our_name; - cstate->resp_type = digest; - - if (cstate->clientstate == CHAPCS_INITIAL || - cstate->clientstate == CHAPCS_PENDING) { - /* lower layer isn't up - wait until later */ - cstate->clientstate = CHAPCS_PENDING; - return; - } - - /* - * We get here as a result of LCP coming up. - * So even if CHAP was open before, we will - * have to re-authenticate ourselves. - */ - cstate->clientstate = CHAPCS_LISTEN; -} - - -/* - * ChapAuthPeer - Authenticate our peer (start server). - */ -void ChapAuthPeer(int unit, char *our_name, int digest) -{ - chap_state *cstate = &chap[unit]; - - cstate->chal_name = our_name; - cstate->chal_type = digest; - - if (cstate->serverstate == CHAPSS_INITIAL || - cstate->serverstate == CHAPSS_PENDING) { - /* lower layer isn't up - wait until later */ - cstate->serverstate = CHAPSS_PENDING; - return; - } - - ChapGenChallenge(cstate); - ChapSendChallenge(cstate); /* crank it up dude! */ - cstate->serverstate = CHAPSS_INITIAL_CHAL; -} - - - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ -/* - * ChapInit - Initialize a CHAP unit. - */ -static void ChapInit(int unit) -{ - chap_state *cstate = &chap[unit]; - - BZERO(cstate, sizeof(*cstate)); - cstate->unit = unit; - cstate->clientstate = CHAPCS_INITIAL; - cstate->serverstate = CHAPSS_INITIAL; - cstate->timeouttime = CHAP_DEFTIMEOUT; - cstate->max_transmits = CHAP_DEFTRANSMITS; - /* random number generator is initialized in magic_init */ -} - - -/* - * ChapChallengeTimeout - Timeout expired on sending challenge. - */ -static void ChapChallengeTimeout(void *arg) -{ - chap_state *cstate = (chap_state *) arg; - - /* if we aren't sending challenges, don't worry. then again we */ - /* probably shouldn't be here either */ - if (cstate->serverstate != CHAPSS_INITIAL_CHAL && - cstate->serverstate != CHAPSS_RECHALLENGE) - return; - - if (cstate->chal_transmits >= cstate->max_transmits) { - /* give up on peer */ - CHAPDEBUG((LOG_ERR, "Peer failed to respond to CHAP challenge\n")); - cstate->serverstate = CHAPSS_BADAUTH; - auth_peer_fail(cstate->unit, PPP_CHAP); - return; - } - - ChapSendChallenge(cstate); /* Re-send challenge */ -} - - -/* - * ChapResponseTimeout - Timeout expired on sending response. - */ -static void ChapResponseTimeout(void *arg) -{ - chap_state *cstate = (chap_state *) arg; - - /* if we aren't sending a response, don't worry. */ - if (cstate->clientstate != CHAPCS_RESPONSE) - return; - - ChapSendResponse(cstate); /* re-send response */ -} - - -/* - * ChapRechallenge - Time to challenge the peer again. - */ -static void ChapRechallenge(void *arg) -{ - chap_state *cstate = (chap_state *) arg; - - /* if we aren't sending a response, don't worry. */ - if (cstate->serverstate != CHAPSS_OPEN) - return; - - ChapGenChallenge(cstate); - ChapSendChallenge(cstate); - cstate->serverstate = CHAPSS_RECHALLENGE; -} - - -/* - * ChapLowerUp - The lower layer is up. - * - * Start up if we have pending requests. - */ -static void ChapLowerUp(int unit) -{ - chap_state *cstate = &chap[unit]; - - if (cstate->clientstate == CHAPCS_INITIAL) - cstate->clientstate = CHAPCS_CLOSED; - else if (cstate->clientstate == CHAPCS_PENDING) - cstate->clientstate = CHAPCS_LISTEN; - - if (cstate->serverstate == CHAPSS_INITIAL) - cstate->serverstate = CHAPSS_CLOSED; - else if (cstate->serverstate == CHAPSS_PENDING) { - ChapGenChallenge(cstate); - ChapSendChallenge(cstate); - cstate->serverstate = CHAPSS_INITIAL_CHAL; - } -} - - -/* - * ChapLowerDown - The lower layer is down. - * - * Cancel all timeouts. - */ -static void ChapLowerDown(int unit) -{ - chap_state *cstate = &chap[unit]; - - /* Timeout(s) pending? Cancel if so. */ - if (cstate->serverstate == CHAPSS_INITIAL_CHAL || - cstate->serverstate == CHAPSS_RECHALLENGE) - UNTIMEOUT(ChapChallengeTimeout, cstate); - else if (cstate->serverstate == CHAPSS_OPEN - && cstate->chal_interval != 0) - UNTIMEOUT(ChapRechallenge, cstate); - if (cstate->clientstate == CHAPCS_RESPONSE) - UNTIMEOUT(ChapResponseTimeout, cstate); - - cstate->clientstate = CHAPCS_INITIAL; - cstate->serverstate = CHAPSS_INITIAL; -} - - -/* - * ChapProtocolReject - Peer doesn't grok CHAP. - */ -static void ChapProtocolReject(int unit) -{ - chap_state *cstate = &chap[unit]; - - if (cstate->serverstate != CHAPSS_INITIAL && - cstate->serverstate != CHAPSS_CLOSED) - auth_peer_fail(unit, PPP_CHAP); - if (cstate->clientstate != CHAPCS_INITIAL && - cstate->clientstate != CHAPCS_CLOSED) - auth_withpeer_fail(unit, PPP_CHAP); - ChapLowerDown(unit); /* shutdown chap */ -} - - -/* - * ChapInput - Input CHAP packet. - */ -static void ChapInput(int unit, u_char *inpacket, int packet_len) -{ - chap_state *cstate = &chap[unit]; - u_char *inp; - u_char code, id; - int len; - - /* - * Parse header (code, id and length). - * If packet too short, drop it. - */ - inp = inpacket; - if (packet_len < CHAP_HEADERLEN) { - CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short header.\n")); - return; - } - GETCHAR(code, inp); - GETCHAR(id, inp); - GETSHORT(len, inp); - if (len < CHAP_HEADERLEN) { - CHAPDEBUG((LOG_INFO, "ChapInput: rcvd illegal length.\n")); - return; - } - if (len > packet_len) { - CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short packet.\n")); - return; - } - len -= CHAP_HEADERLEN; - - /* - * Action depends on code (as in fact it usually does :-). - */ - switch (code) { - case CHAP_CHALLENGE: - ChapReceiveChallenge(cstate, inp, id, len); - break; - - case CHAP_RESPONSE: - ChapReceiveResponse(cstate, inp, id, len); - break; - - case CHAP_FAILURE: - ChapReceiveFailure(cstate, inp, id, len); - break; - - case CHAP_SUCCESS: - ChapReceiveSuccess(cstate, inp, id, len); - break; - - default: /* Need code reject? */ - CHAPDEBUG((LOG_WARNING, "Unknown CHAP code (%d) received.\n", code)); - break; - } -} - - -/* - * ChapReceiveChallenge - Receive Challenge and send Response. - */ -static void ChapReceiveChallenge(chap_state *cstate, u_char *inp, int id, int len) -{ - int rchallenge_len; - u_char *rchallenge; - int secret_len; - char secret[MAXSECRETLEN]; - char rhostname[256]; - MD5_CTX mdContext; - u_char hash[MD5_SIGNATURE_SIZE]; - - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: Rcvd id %d.\n", id)); - if (cstate->clientstate == CHAPCS_CLOSED || - cstate->clientstate == CHAPCS_PENDING) { - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: in state %d\n", - cstate->clientstate)); - return; - } - - if (len < 2) { - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n")); - return; - } - - GETCHAR(rchallenge_len, inp); - len -= sizeof (u_char) + rchallenge_len; /* now name field length */ - if (len < 0) { - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n")); - return; - } - rchallenge = inp; - INCPTR(rchallenge_len, inp); - - if (len >= sizeof(rhostname)) - len = sizeof(rhostname) - 1; - BCOPY(inp, rhostname, len); - rhostname[len] = '\000'; - - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: received name field '%s'\n", - rhostname)); - - /* Microsoft doesn't send their name back in the PPP packet */ - if (ppp_settings.remote_name[0] != 0 && (ppp_settings.explicit_remote || rhostname[0] == 0)) { - strncpy(rhostname, ppp_settings.remote_name, sizeof(rhostname)); - rhostname[sizeof(rhostname) - 1] = 0; - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: using '%s' as remote name\n", - rhostname)); - } - - /* get secret for authenticating ourselves with the specified host */ - if (!get_secret(cstate->unit, cstate->resp_name, rhostname, - secret, &secret_len, 0)) { - secret_len = 0; /* assume null secret if can't find one */ - CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating us to %s\n", rhostname)); - } - - /* cancel response send timeout if necessary */ - if (cstate->clientstate == CHAPCS_RESPONSE) - UNTIMEOUT(ChapResponseTimeout, cstate); - - cstate->resp_id = id; - cstate->resp_transmits = 0; - - /* generate MD based on negotiated type */ - switch (cstate->resp_type) { - - case CHAP_DIGEST_MD5: - MD5Init(&mdContext); - MD5Update(&mdContext, &cstate->resp_id, 1); - MD5Update(&mdContext, (u_char*)secret, secret_len); - MD5Update(&mdContext, rchallenge, rchallenge_len); - MD5Final(hash, &mdContext); - BCOPY(hash, cstate->response, MD5_SIGNATURE_SIZE); - cstate->resp_length = MD5_SIGNATURE_SIZE; - break; - -#ifdef CHAPMS - case CHAP_MICROSOFT: - ChapMS(cstate, rchallenge, rchallenge_len, secret, secret_len); - break; -#endif - - default: - CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->resp_type)); - return; - } - - BZERO(secret, sizeof(secret)); - ChapSendResponse(cstate); -} - - -/* - * ChapReceiveResponse - Receive and process response. - */ -static void ChapReceiveResponse(chap_state *cstate, u_char *inp, int id, int len) -{ - u_char *remmd, remmd_len; - int secret_len, old_state; - int code; - char rhostname[256]; - MD5_CTX mdContext; - char secret[MAXSECRETLEN]; - u_char hash[MD5_SIGNATURE_SIZE]; - - CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: Rcvd id %d.\n", id)); - - if (cstate->serverstate == CHAPSS_CLOSED || - cstate->serverstate == CHAPSS_PENDING) { - CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: in state %d\n", - cstate->serverstate)); - return; - } - - if (id != cstate->chal_id) - return; /* doesn't match ID of last challenge */ - - /* - * If we have received a duplicate or bogus Response, - * we have to send the same answer (Success/Failure) - * as we did for the first Response we saw. - */ - if (cstate->serverstate == CHAPSS_OPEN) { - ChapSendStatus(cstate, CHAP_SUCCESS); - return; - } - if (cstate->serverstate == CHAPSS_BADAUTH) { - ChapSendStatus(cstate, CHAP_FAILURE); - return; - } - - if (len < 2) { - CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n")); - return; - } - GETCHAR(remmd_len, inp); /* get length of MD */ - remmd = inp; /* get pointer to MD */ - INCPTR(remmd_len, inp); - - len -= sizeof (u_char) + remmd_len; - if (len < 0) { - CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n")); - return; - } - - UNTIMEOUT(ChapChallengeTimeout, cstate); - - if (len >= sizeof(rhostname)) - len = sizeof(rhostname) - 1; - BCOPY(inp, rhostname, len); - rhostname[len] = '\000'; - - CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: received name field: %s\n", - rhostname)); - - /* - * Get secret for authenticating them with us, - * do the hash ourselves, and compare the result. - */ - code = CHAP_FAILURE; - if (!get_secret(cstate->unit, rhostname, cstate->chal_name, - secret, &secret_len, 1)) { -/* CHAPDEBUG((LOG_WARNING, TL_CHAP, "No CHAP secret found for authenticating %s\n", rhostname)); */ - CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating %s\n", - rhostname)); - } else { - - /* generate MD based on negotiated type */ - switch (cstate->chal_type) { - - case CHAP_DIGEST_MD5: /* only MD5 is defined for now */ - if (remmd_len != MD5_SIGNATURE_SIZE) - break; /* it's not even the right length */ - MD5Init(&mdContext); - MD5Update(&mdContext, &cstate->chal_id, 1); - MD5Update(&mdContext, (u_char*)secret, secret_len); - MD5Update(&mdContext, cstate->challenge, cstate->chal_len); - MD5Final(hash, &mdContext); - - /* compare local and remote MDs and send the appropriate status */ - if (memcmp (hash, remmd, MD5_SIGNATURE_SIZE) == 0) - code = CHAP_SUCCESS; /* they are the same! */ - break; - - default: - CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->chal_type)); - } - } - - BZERO(secret, sizeof(secret)); - ChapSendStatus(cstate, code); - - if (code == CHAP_SUCCESS) { - old_state = cstate->serverstate; - cstate->serverstate = CHAPSS_OPEN; - if (old_state == CHAPSS_INITIAL_CHAL) { - auth_peer_success(cstate->unit, PPP_CHAP, rhostname, len); - } - if (cstate->chal_interval != 0) - TIMEOUT(ChapRechallenge, cstate, cstate->chal_interval); - } else { - CHAPDEBUG((LOG_ERR, "CHAP peer authentication failed\n")); - cstate->serverstate = CHAPSS_BADAUTH; - auth_peer_fail(cstate->unit, PPP_CHAP); - } -} - -/* - * ChapReceiveSuccess - Receive Success - */ -static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len) -{ - - CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: Rcvd id %d.\n", id)); - - if (cstate->clientstate == CHAPCS_OPEN) - /* presumably an answer to a duplicate response */ - return; - - if (cstate->clientstate != CHAPCS_RESPONSE) { - /* don't know what this is */ - CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: in state %d\n", - cstate->clientstate)); - return; - } - - UNTIMEOUT(ChapResponseTimeout, cstate); - - /* - * Print message. - */ - if (len > 0) - PRINTMSG(inp, len); - - cstate->clientstate = CHAPCS_OPEN; - - auth_withpeer_success(cstate->unit, PPP_CHAP); -} - - -/* - * ChapReceiveFailure - Receive failure. - */ -static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len) -{ - CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: Rcvd id %d.\n", id)); - - if (cstate->clientstate != CHAPCS_RESPONSE) { - /* don't know what this is */ - CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: in state %d\n", - cstate->clientstate)); - return; - } - - UNTIMEOUT(ChapResponseTimeout, cstate); - - /* - * Print message. - */ - if (len > 0) - PRINTMSG(inp, len); - - CHAPDEBUG((LOG_ERR, "CHAP authentication failed\n")); - auth_withpeer_fail(cstate->unit, PPP_CHAP); -} - - -/* - * ChapSendChallenge - Send an Authenticate challenge. - */ -static void ChapSendChallenge(chap_state *cstate) -{ - u_char *outp; - int chal_len, name_len; - int outlen; - - chal_len = cstate->chal_len; - name_len = strlen(cstate->chal_name); - outlen = CHAP_HEADERLEN + sizeof (u_char) + chal_len + name_len; - outp = outpacket_buf[cstate->unit]; - - MAKEHEADER(outp, PPP_CHAP); /* paste in a CHAP header */ - - PUTCHAR(CHAP_CHALLENGE, outp); - PUTCHAR(cstate->chal_id, outp); - PUTSHORT(outlen, outp); - - PUTCHAR(chal_len, outp); /* put length of challenge */ - BCOPY(cstate->challenge, outp, chal_len); - INCPTR(chal_len, outp); - - BCOPY(cstate->chal_name, outp, name_len); /* append hostname */ - - pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); - - CHAPDEBUG((LOG_INFO, "ChapSendChallenge: Sent id %d.\n", cstate->chal_id)); - - TIMEOUT(ChapChallengeTimeout, cstate, cstate->timeouttime); - ++cstate->chal_transmits; -} - - -/* - * ChapSendStatus - Send a status response (ack or nak). - */ -static void ChapSendStatus(chap_state *cstate, int code) -{ - u_char *outp; - int outlen, msglen; - char msg[256]; - - if (code == CHAP_SUCCESS) - strcpy(msg, "Welcome!"); - else - strcpy(msg, "I don't like you. Go 'way."); - msglen = strlen(msg); - - outlen = CHAP_HEADERLEN + msglen; - outp = outpacket_buf[cstate->unit]; - - MAKEHEADER(outp, PPP_CHAP); /* paste in a header */ - - PUTCHAR(code, outp); - PUTCHAR(cstate->chal_id, outp); - PUTSHORT(outlen, outp); - BCOPY(msg, outp, msglen); - pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); - - CHAPDEBUG((LOG_INFO, "ChapSendStatus: Sent code %d, id %d.\n", code, - cstate->chal_id)); -} - -/* - * ChapGenChallenge is used to generate a pseudo-random challenge string of - * a pseudo-random length between min_len and max_len. The challenge - * string and its length are stored in *cstate, and various other fields of - * *cstate are initialized. - */ - -static void ChapGenChallenge(chap_state *cstate) -{ - int chal_len; - u_char *ptr = cstate->challenge; - int i; - - /* pick a random challenge length between MIN_CHALLENGE_LENGTH and - MAX_CHALLENGE_LENGTH */ - chal_len = (unsigned) - ((((magic() >> 16) * - (MAX_CHALLENGE_LENGTH - MIN_CHALLENGE_LENGTH)) >> 16) - + MIN_CHALLENGE_LENGTH); - cstate->chal_len = chal_len; - cstate->chal_id = ++cstate->id; - cstate->chal_transmits = 0; - - /* generate a random string */ - for (i = 0; i < chal_len; i++ ) - *ptr++ = (char) (magic() & 0xff); -} - -/* - * ChapSendResponse - send a response packet with values as specified - * in *cstate. - */ -/* ARGSUSED */ -static void ChapSendResponse(chap_state *cstate) -{ - u_char *outp; - int outlen, md_len, name_len; - - md_len = cstate->resp_length; - name_len = strlen(cstate->resp_name); - outlen = CHAP_HEADERLEN + sizeof (u_char) + md_len + name_len; - outp = outpacket_buf[cstate->unit]; - - MAKEHEADER(outp, PPP_CHAP); - - PUTCHAR(CHAP_RESPONSE, outp); /* we are a response */ - PUTCHAR(cstate->resp_id, outp); /* copy id from challenge packet */ - PUTSHORT(outlen, outp); /* packet length */ - - PUTCHAR(md_len, outp); /* length of MD */ - BCOPY(cstate->response, outp, md_len); /* copy MD to buffer */ - INCPTR(md_len, outp); - - BCOPY(cstate->resp_name, outp, name_len); /* append our name */ - - /* send the packet */ - pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); - - cstate->clientstate = CHAPCS_RESPONSE; - TIMEOUT(ChapResponseTimeout, cstate, cstate->timeouttime); - ++cstate->resp_transmits; -} - -/* - * ChapPrintPkt - print the contents of a CHAP packet. - */ -static int ChapPrintPkt( - u_char *p, - int plen, - void (*printer) (void *, char *, ...), - void *arg -) -{ - int code, id, len; - int clen, nlen; - u_char x; - - if (plen < CHAP_HEADERLEN) - return 0; - GETCHAR(code, p); - GETCHAR(id, p); - GETSHORT(len, p); - if (len < CHAP_HEADERLEN || len > plen) - return 0; - - if (code >= 1 && code <= sizeof(ChapCodenames) / sizeof(char *)) - printer(arg, " %s", ChapCodenames[code-1]); - else - printer(arg, " code=0x%x", code); - printer(arg, " id=0x%x", id); - len -= CHAP_HEADERLEN; - switch (code) { - case CHAP_CHALLENGE: - case CHAP_RESPONSE: - if (len < 1) - break; - clen = p[0]; - if (len < clen + 1) - break; - ++p; - nlen = len - clen - 1; - printer(arg, " <"); - for (; clen > 0; --clen) { - GETCHAR(x, p); - printer(arg, "%.2x", x); - } - printer(arg, ">, name = %.*Z", nlen, p); - break; - case CHAP_FAILURE: - case CHAP_SUCCESS: - printer(arg, " %.*Z", len, p); - break; - default: - for (clen = len; clen > 0; --clen) { - GETCHAR(x, p); - printer(arg, " %.2x", x); - } - } - - return len + CHAP_HEADERLEN; -} - -#endif - -#endif /* PPP_SUPPORT */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/chap.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/chap.h deleted file mode 100644 index 9a4ea4fc0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/chap.h +++ /dev/null @@ -1,167 +0,0 @@ -/***************************************************************************** -* chap.h - Network Challenge Handshake Authentication Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1998 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-03 Guy Lancaster , Global Election Systems Inc. -* Original built from BSD network code. -******************************************************************************/ -/* - * chap.h - Challenge Handshake Authentication Protocol definitions. - * - * Copyright (c) 1993 The Australian National University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by the Australian National University. The name of the University - * may not be used to endorse or promote products derived from this - * software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * Copyright (c) 1991 Gregory M. Christy - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by the author. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id$ - */ - -#ifndef CHAP_H -#define CHAP_H - -/************************* -*** PUBLIC DEFINITIONS *** -*************************/ - -/* Code + ID + length */ -#define CHAP_HEADERLEN 4 - -/* - * CHAP codes. - */ - -#define CHAP_DIGEST_MD5 5 /* use MD5 algorithm */ -#define MD5_SIGNATURE_SIZE 16 /* 16 bytes in a MD5 message digest */ -#define CHAP_MICROSOFT 0x80 /* use Microsoft-compatible alg. */ -#define MS_CHAP_RESPONSE_LEN 49 /* Response length for MS-CHAP */ - -#define CHAP_CHALLENGE 1 -#define CHAP_RESPONSE 2 -#define CHAP_SUCCESS 3 -#define CHAP_FAILURE 4 - -/* - * Challenge lengths (for challenges we send) and other limits. - */ -#define MIN_CHALLENGE_LENGTH 32 -#define MAX_CHALLENGE_LENGTH 64 -#define MAX_RESPONSE_LENGTH 64 /* sufficient for MD5 or MS-CHAP */ - -/* - * Client (peer) states. - */ -#define CHAPCS_INITIAL 0 /* Lower layer down, not opened */ -#define CHAPCS_CLOSED 1 /* Lower layer up, not opened */ -#define CHAPCS_PENDING 2 /* Auth us to peer when lower up */ -#define CHAPCS_LISTEN 3 /* Listening for a challenge */ -#define CHAPCS_RESPONSE 4 /* Sent response, waiting for status */ -#define CHAPCS_OPEN 5 /* We've received Success */ - -/* - * Server (authenticator) states. - */ -#define CHAPSS_INITIAL 0 /* Lower layer down, not opened */ -#define CHAPSS_CLOSED 1 /* Lower layer up, not opened */ -#define CHAPSS_PENDING 2 /* Auth peer when lower up */ -#define CHAPSS_INITIAL_CHAL 3 /* We've sent the first challenge */ -#define CHAPSS_OPEN 4 /* We've sent a Success msg */ -#define CHAPSS_RECHALLENGE 5 /* We've sent another challenge */ -#define CHAPSS_BADAUTH 6 /* We've sent a Failure msg */ - -/************************ -*** PUBLIC DATA TYPES *** -************************/ - -/* - * Each interface is described by a chap structure. - */ - -typedef struct chap_state { - int unit; /* Interface unit number */ - int clientstate; /* Client state */ - int serverstate; /* Server state */ - u_char challenge[MAX_CHALLENGE_LENGTH]; /* last challenge string sent */ - u_char chal_len; /* challenge length */ - u_char chal_id; /* ID of last challenge */ - u_char chal_type; /* hash algorithm for challenges */ - u_char id; /* Current id */ - char *chal_name; /* Our name to use with challenge */ - int chal_interval; /* Time until we challenge peer again */ - int timeouttime; /* Timeout time in seconds */ - int max_transmits; /* Maximum # of challenge transmissions */ - int chal_transmits; /* Number of transmissions of challenge */ - int resp_transmits; /* Number of transmissions of response */ - u_char response[MAX_RESPONSE_LENGTH]; /* Response to send */ - u_char resp_length; /* length of response */ - u_char resp_id; /* ID for response messages */ - u_char resp_type; /* hash algorithm for responses */ - char *resp_name; /* Our name to send with response */ -} chap_state; - - -/****************** -*** PUBLIC DATA *** -******************/ -extern chap_state chap[]; - -extern struct protent chap_protent; - - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ - -void ChapAuthWithPeer (int, char *, int); -void ChapAuthPeer (int, char *, int); - -#endif /* CHAP_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/chpms.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/chpms.c deleted file mode 100644 index 01755ba39..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/chpms.c +++ /dev/null @@ -1,398 +0,0 @@ -/*** WARNING - THIS CODE HAS NOT BEEN FINISHED! ***/ -/***************************************************************************** -* chpms.c - Network MicroSoft Challenge Handshake Authentication Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* Copyright (c) 1997 by Global Election Systems Inc. All rights reserved. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-08 Guy Lancaster , Global Election Systems Inc. -* Original based on BSD chap_ms.c. -*****************************************************************************/ -/* - * chap_ms.c - Microsoft MS-CHAP compatible implementation. - * - * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited. - * http://www.strataware.com/ - * - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Eric Rosenquist. The name of the author may not be used to - * endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -/* - * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997 - * - * Implemented LANManager type password response to MS-CHAP challenges. - * Now pppd provides both NT style and LANMan style blocks, and the - * prefered is set by option "ms-lanman". Default is to use NT. - * The hash text (StdText) was taken from Win95 RASAPI32.DLL. - * - * You should also use DOMAIN\\USERNAME as described in README.MSCHAP80 - */ - -#define USE_CRYPT - - -#include "ppp.h" - -#if MSCHAP_SUPPORT > 0 - -#include "md4.h" -#ifndef USE_CRYPT -#include "des.h" -#endif -#include "chap.h" -#include "chpms.h" -#include "pppdebug.h" - - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ - - -/************************/ -/*** LOCAL DATA TYPES ***/ -/************************/ -typedef struct { - u_char LANManResp[24]; - u_char NTResp[24]; - u_char UseNT; /* If 1, ignore the LANMan response field */ -} MS_ChapResponse; -/* We use MS_CHAP_RESPONSE_LEN, rather than sizeof(MS_ChapResponse), - in case this struct gets padded. */ - - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ - -/* XXX Don't know what to do with these. */ -extern void setkey(const char *); -extern void encrypt(char *, int); - -static void DesEncrypt (u_char *, u_char *, u_char *); -static void MakeKey (u_char *, u_char *); - -#ifdef USE_CRYPT -static void Expand (u_char *, u_char *); -static void Collapse (u_char *, u_char *); -#endif - -static void ChallengeResponse( - u_char *challenge, /* IN 8 octets */ - u_char *pwHash, /* IN 16 octets */ - u_char *response /* OUT 24 octets */ -); -static void ChapMS_NT( - char *rchallenge, - int rchallenge_len, - char *secret, - int secret_len, - MS_ChapResponse *response -); -static u_char Get7Bits( - u_char *input, - int startBit -); - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -void ChapMS( - chap_state *cstate, - char *rchallenge, - int rchallenge_len, - char *secret, - int secret_len -) -{ - MS_ChapResponse response; -#ifdef MSLANMAN - extern int ms_lanman; -#endif - -#if 0 - CHAPDEBUG((LOG_INFO, "ChapMS: secret is '%.*s'\n", secret_len, secret)); -#endif - BZERO(&response, sizeof(response)); - - /* Calculate both always */ - ChapMS_NT(rchallenge, rchallenge_len, secret, secret_len, &response); - -#ifdef MSLANMAN - ChapMS_LANMan(rchallenge, rchallenge_len, secret, secret_len, &response); - - /* prefered method is set by option */ - response.UseNT = !ms_lanman; -#else - response.UseNT = 1; -#endif - - BCOPY(&response, cstate->response, MS_CHAP_RESPONSE_LEN); - cstate->resp_length = MS_CHAP_RESPONSE_LEN; -} - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ -static void ChallengeResponse( - u_char *challenge, /* IN 8 octets */ - u_char *pwHash, /* IN 16 octets */ - u_char *response /* OUT 24 octets */ -) -{ - char ZPasswordHash[21]; - - BZERO(ZPasswordHash, sizeof(ZPasswordHash)); - BCOPY(pwHash, ZPasswordHash, 16); - -#if 0 - log_packet(ZPasswordHash, sizeof(ZPasswordHash), "ChallengeResponse - ZPasswordHash", LOG_DEBUG); -#endif - - DesEncrypt(challenge, ZPasswordHash + 0, response + 0); - DesEncrypt(challenge, ZPasswordHash + 7, response + 8); - DesEncrypt(challenge, ZPasswordHash + 14, response + 16); - -#if 0 - log_packet(response, 24, "ChallengeResponse - response", LOG_DEBUG); -#endif -} - - -#ifdef USE_CRYPT -static void DesEncrypt( - u_char *clear, /* IN 8 octets */ - u_char *key, /* IN 7 octets */ - u_char *cipher /* OUT 8 octets */ -) -{ - u_char des_key[8]; - u_char crypt_key[66]; - u_char des_input[66]; - - MakeKey(key, des_key); - - Expand(des_key, crypt_key); - setkey(crypt_key); - -#if 0 - CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n", - clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7])); -#endif - - Expand(clear, des_input); - encrypt(des_input, 0); - Collapse(des_input, cipher); - -#if 0 - CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n", - cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7])); -#endif -} - -#else /* USE_CRYPT */ - -static void DesEncrypt( - u_char *clear, /* IN 8 octets */ - u_char *key, /* IN 7 octets */ - u_char *cipher /* OUT 8 octets */ -) -{ - des_cblock des_key; - des_key_schedule key_schedule; - - MakeKey(key, des_key); - - des_set_key(&des_key, key_schedule); - -#if 0 - CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n", - clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7])); -#endif - - des_ecb_encrypt((des_cblock *)clear, (des_cblock *)cipher, key_schedule, 1); - -#if 0 - CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n", - cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7])); -#endif -} - -#endif /* USE_CRYPT */ - - -static u_char Get7Bits( - u_char *input, - int startBit -) -{ - register unsigned int word; - - word = (unsigned)input[startBit / 8] << 8; - word |= (unsigned)input[startBit / 8 + 1]; - - word >>= 15 - (startBit % 8 + 7); - - return word & 0xFE; -} - -#ifdef USE_CRYPT - -/* in == 8-byte string (expanded version of the 56-bit key) - * out == 64-byte string where each byte is either 1 or 0 - * Note that the low-order "bit" is always ignored by by setkey() - */ -static void Expand(u_char *in, u_char *out) -{ - int j, c; - int i; - - for(i = 0; i < 64; in++){ - c = *in; - for(j = 7; j >= 0; j--) - *out++ = (c >> j) & 01; - i += 8; - } -} - -/* The inverse of Expand - */ -static void Collapse(u_char *in, u_char *out) -{ - int j; - int i; - unsigned int c; - - for (i = 0; i < 64; i += 8, out++) { - c = 0; - for (j = 7; j >= 0; j--, in++) - c |= *in << j; - *out = c & 0xff; - } -} -#endif - -static void MakeKey( - u_char *key, /* IN 56 bit DES key missing parity bits */ - u_char *des_key /* OUT 64 bit DES key with parity bits added */ -) -{ - des_key[0] = Get7Bits(key, 0); - des_key[1] = Get7Bits(key, 7); - des_key[2] = Get7Bits(key, 14); - des_key[3] = Get7Bits(key, 21); - des_key[4] = Get7Bits(key, 28); - des_key[5] = Get7Bits(key, 35); - des_key[6] = Get7Bits(key, 42); - des_key[7] = Get7Bits(key, 49); - -#ifndef USE_CRYPT - des_set_odd_parity((des_cblock *)des_key); -#endif - -#if 0 - CHAPDEBUG((LOG_INFO, "MakeKey: 56-bit input : %02X%02X%02X%02X%02X%02X%02X\n", - key[0], key[1], key[2], key[3], key[4], key[5], key[6])); - CHAPDEBUG((LOG_INFO, "MakeKey: 64-bit output: %02X%02X%02X%02X%02X%02X%02X%02X\n", - des_key[0], des_key[1], des_key[2], des_key[3], des_key[4], des_key[5], des_key[6], des_key[7])); -#endif -} - -static void ChapMS_NT( - char *rchallenge, - int rchallenge_len, - char *secret, - int secret_len, - MS_ChapResponse *response -) -{ - int i; - MDstruct md4Context; - u_char unicodePassword[MAX_NT_PASSWORD * 2]; - static int low_byte_first = -1; - - /* Initialize the Unicode version of the secret (== password). */ - /* This implicitly supports 8-bit ISO8859/1 characters. */ - BZERO(unicodePassword, sizeof(unicodePassword)); - for (i = 0; i < secret_len; i++) - unicodePassword[i * 2] = (u_char)secret[i]; - - MDbegin(&md4Context); - MDupdate(&md4Context, unicodePassword, secret_len * 2 * 8); /* Unicode is 2 bytes/char, *8 for bit count */ - - if (low_byte_first == -1) - low_byte_first = (htons((unsigned short int)1) != 1); - if (low_byte_first == 0) - MDreverse((u_long *)&md4Context); /* sfb 961105 */ - - MDupdate(&md4Context, NULL, 0); /* Tell MD4 we're done */ - - ChallengeResponse(rchallenge, (char *)md4Context.buffer, response->NTResp); -} - -#ifdef MSLANMAN -static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */ - -static ChapMS_LANMan( - char *rchallenge, - int rchallenge_len, - char *secret, - int secret_len, - MS_ChapResponse *response -) -{ - int i; - u_char UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */ - u_char PasswordHash[16]; - - /* LANMan password is case insensitive */ - BZERO(UcasePassword, sizeof(UcasePassword)); - for (i = 0; i < secret_len; i++) - UcasePassword[i] = (u_char)toupper(secret[i]); - DesEncrypt( StdText, UcasePassword + 0, PasswordHash + 0 ); - DesEncrypt( StdText, UcasePassword + 7, PasswordHash + 8 ); - ChallengeResponse(rchallenge, PasswordHash, response->LANManResp); -} -#endif - -#endif /* MSCHAP_SUPPORT */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/chpms.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/chpms.h deleted file mode 100644 index 1a2bd41d1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/chpms.h +++ /dev/null @@ -1,64 +0,0 @@ -/***************************************************************************** -* chpms.h - Network Microsoft Challenge Handshake Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1998 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 98-01-30 Guy Lancaster , Global Election Systems Inc. -* Original built from BSD network code. -******************************************************************************/ -/* - * chap.h - Challenge Handshake Authentication Protocol definitions. - * - * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited. - * http://www.strataware.com/ - * - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Eric Rosenquist. The name of the author may not be used to - * endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id$ - */ - -#ifndef CHPMS_H -#define CHPMS_H - -#define MAX_NT_PASSWORD 256 /* Maximum number of (Unicode) chars in an NT password */ - -void ChapMS (chap_state *, char *, int, char *, int); - -#endif /* CHPMS_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/fsm.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/fsm.c deleted file mode 100644 index fe8b38a93..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/fsm.c +++ /dev/null @@ -1,838 +0,0 @@ -/***************************************************************************** -* fsm.c - Network Control Protocol Finite State Machine program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-01 Guy Lancaster , Global Election Systems Inc. -* Original based on BSD fsm.c. -*****************************************************************************/ -/* - * fsm.c - {Link, IP} Control Protocol Finite State Machine. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - - -/* - * TODO: - * Randomize fsm id on link/init. - * Deal with variable outgoing MTU. - */ - -#include "ppp.h" -#if PPP_SUPPORT > 0 -#include "fsm.h" -#include "pppdebug.h" - - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ - - -/************************/ -/*** LOCAL DATA TYPES ***/ -/************************/ - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -static void fsm_timeout (void *); -static void fsm_rconfreq (fsm *, u_char, u_char *, int); -static void fsm_rconfack (fsm *, int, u_char *, int); -static void fsm_rconfnakrej (fsm *, int, int, u_char *, int); -static void fsm_rtermreq (fsm *, int, u_char *, int); -static void fsm_rtermack (fsm *); -static void fsm_rcoderej (fsm *, u_char *, int); -static void fsm_sconfreq (fsm *, int); - -#define PROTO_NAME(f) ((f)->callbacks->proto_name) - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -int peer_mru[NUM_PPP]; - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ - -/* - * fsm_init - Initialize fsm. - * - * Initialize fsm state. - */ -void fsm_init(fsm *f) -{ - f->state = INITIAL; - f->flags = 0; - f->id = 0; /* XXX Start with random id? */ - f->timeouttime = FSM_DEFTIMEOUT; - f->maxconfreqtransmits = FSM_DEFMAXCONFREQS; - f->maxtermtransmits = FSM_DEFMAXTERMREQS; - f->maxnakloops = FSM_DEFMAXNAKLOOPS; - f->term_reason_len = 0; -} - - -/* - * fsm_lowerup - The lower layer is up. - */ -void fsm_lowerup(fsm *f) -{ - int oldState = f->state; - - switch( f->state ){ - case INITIAL: - f->state = CLOSED; - break; - - case STARTING: - if( f->flags & OPT_SILENT ) - f->state = STOPPED; - else { - /* Send an initial configure-request */ - fsm_sconfreq(f, 0); - f->state = REQSENT; - } - break; - - default: - FSMDEBUG((LOG_INFO, "%s: Up event in state %d!\n", - PROTO_NAME(f), f->state)); - } - - FSMDEBUG((LOG_INFO, "%s: lowerup state %d -> %d\n", - PROTO_NAME(f), oldState, f->state)); -} - - -/* - * fsm_lowerdown - The lower layer is down. - * - * Cancel all timeouts and inform upper layers. - */ -void fsm_lowerdown(fsm *f) -{ - int oldState = f->state; - - switch( f->state ){ - case CLOSED: - f->state = INITIAL; - break; - - case STOPPED: - f->state = STARTING; - if( f->callbacks->starting ) - (*f->callbacks->starting)(f); - break; - - case CLOSING: - f->state = INITIAL; - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - break; - - case STOPPING: - case REQSENT: - case ACKRCVD: - case ACKSENT: - f->state = STARTING; - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - break; - - case OPENED: - if( f->callbacks->down ) - (*f->callbacks->down)(f); - f->state = STARTING; - break; - - default: - FSMDEBUG((LOG_INFO, "%s: Down event in state %d!\n", - PROTO_NAME(f), f->state)); - } - - FSMDEBUG((LOG_INFO, "%s: lowerdown state %d -> %d\n", - PROTO_NAME(f), oldState, f->state)); -} - - -/* - * fsm_open - Link is allowed to come up. - */ -void fsm_open(fsm *f) -{ - int oldState = f->state; - - switch( f->state ){ - case INITIAL: - f->state = STARTING; - if( f->callbacks->starting ) - (*f->callbacks->starting)(f); - break; - - case CLOSED: - if( f->flags & OPT_SILENT ) - f->state = STOPPED; - else { - /* Send an initial configure-request */ - fsm_sconfreq(f, 0); - f->state = REQSENT; - } - break; - - case CLOSING: - f->state = STOPPING; - /* fall through */ - case STOPPED: - case OPENED: - if( f->flags & OPT_RESTART ){ - fsm_lowerdown(f); - fsm_lowerup(f); - } - break; - } - - FSMDEBUG((LOG_INFO, "%s: open state %d -> %d\n", - PROTO_NAME(f), oldState, f->state)); -} - - -/* - * fsm_close - Start closing connection. - * - * Cancel timeouts and either initiate close or possibly go directly to - * the CLOSED state. - */ -void fsm_close(fsm *f, char *reason) -{ - int oldState = f->state; - - f->term_reason = reason; - f->term_reason_len = (reason == NULL? 0: strlen(reason)); - switch( f->state ){ - case STARTING: - f->state = INITIAL; - break; - case STOPPED: - f->state = CLOSED; - break; - case STOPPING: - f->state = CLOSING; - break; - - case REQSENT: - case ACKRCVD: - case ACKSENT: - case OPENED: - if( f->state != OPENED ) - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - else if( f->callbacks->down ) - (*f->callbacks->down)(f); /* Inform upper layers we're down */ - - /* Init restart counter, send Terminate-Request */ - f->retransmits = f->maxtermtransmits; - fsm_sdata(f, TERMREQ, f->reqid = ++f->id, - (u_char *) f->term_reason, f->term_reason_len); - TIMEOUT(fsm_timeout, f, f->timeouttime); - --f->retransmits; - - f->state = CLOSING; - break; - } - - FSMDEBUG((LOG_INFO, "%s: close reason=%s state %d -> %d\n", - PROTO_NAME(f), reason, oldState, f->state)); -} - - -/* - * fsm_sdata - Send some data. - * - * Used for all packets sent to our peer by this module. - */ -void fsm_sdata( - fsm *f, - u_char code, - u_char id, - u_char *data, - int datalen -) -{ - u_char *outp; - int outlen; - - /* Adjust length to be smaller than MTU */ - outp = outpacket_buf[f->unit]; - if (datalen > peer_mru[f->unit] - (int)HEADERLEN) - datalen = peer_mru[f->unit] - HEADERLEN; - if (datalen && data != outp + PPP_HDRLEN + HEADERLEN) - BCOPY(data, outp + PPP_HDRLEN + HEADERLEN, datalen); - outlen = datalen + HEADERLEN; - MAKEHEADER(outp, f->protocol); - PUTCHAR(code, outp); - PUTCHAR(id, outp); - PUTSHORT(outlen, outp); - pppWrite(f->unit, outpacket_buf[f->unit], outlen + PPP_HDRLEN); - FSMDEBUG((LOG_INFO, "fsm_sdata(%s): Sent code %d,%d,%d.\n", - PROTO_NAME(f), code, id, outlen)); -} - - -/* - * fsm_input - Input packet. - */ -void fsm_input(fsm *f, u_char *inpacket, int l) -{ - u_char *inp = inpacket; - u_char code, id; - int len; - - /* - * Parse header (code, id and length). - * If packet too short, drop it. - */ - if (l < HEADERLEN) { - FSMDEBUG((LOG_WARNING, "fsm_input(%x): Rcvd short header.\n", - f->protocol)); - return; - } - GETCHAR(code, inp); - GETCHAR(id, inp); - GETSHORT(len, inp); - if (len < HEADERLEN) { - FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd illegal length.\n", - f->protocol)); - return; - } - if (len > l) { - FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd short packet.\n", - f->protocol)); - return; - } - len -= HEADERLEN; /* subtract header length */ - - if( f->state == INITIAL || f->state == STARTING ){ - FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd packet in state %d.\n", - f->protocol, f->state)); - return; - } - FSMDEBUG((LOG_INFO, "fsm_input(%s):%d,%d,%d\n", PROTO_NAME(f), code, id, l)); - /* - * Action depends on code. - */ - switch (code) { - case CONFREQ: - fsm_rconfreq(f, id, inp, len); - break; - - case CONFACK: - fsm_rconfack(f, id, inp, len); - break; - - case CONFNAK: - case CONFREJ: - fsm_rconfnakrej(f, code, id, inp, len); - break; - - case TERMREQ: - fsm_rtermreq(f, id, inp, len); - break; - - case TERMACK: - fsm_rtermack(f); - break; - - case CODEREJ: - fsm_rcoderej(f, inp, len); - break; - - default: - if( !f->callbacks->extcode - || !(*f->callbacks->extcode)(f, code, id, inp, len) ) - fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN); - break; - } -} - - -/* - * fsm_protreject - Peer doesn't speak this protocol. - * - * Treat this as a catastrophic error (RXJ-). - */ -void fsm_protreject(fsm *f) -{ - switch( f->state ){ - case CLOSING: - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - /* fall through */ - case CLOSED: - f->state = CLOSED; - if( f->callbacks->finished ) - (*f->callbacks->finished)(f); - break; - - case STOPPING: - case REQSENT: - case ACKRCVD: - case ACKSENT: - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - /* fall through */ - case STOPPED: - f->state = STOPPED; - if( f->callbacks->finished ) - (*f->callbacks->finished)(f); - break; - - case OPENED: - if( f->callbacks->down ) - (*f->callbacks->down)(f); - - /* Init restart counter, send Terminate-Request */ - f->retransmits = f->maxtermtransmits; - fsm_sdata(f, TERMREQ, f->reqid = ++f->id, - (u_char *) f->term_reason, f->term_reason_len); - TIMEOUT(fsm_timeout, f, f->timeouttime); - --f->retransmits; - - f->state = STOPPING; - break; - - default: - FSMDEBUG((LOG_INFO, "%s: Protocol-reject event in state %d!\n", - PROTO_NAME(f), f->state)); - } -} - - - - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ - -/* - * fsm_timeout - Timeout expired. - */ -static void fsm_timeout(void *arg) -{ - fsm *f = (fsm *) arg; - - switch (f->state) { - case CLOSING: - case STOPPING: - if( f->retransmits <= 0 ){ - FSMDEBUG((LOG_WARNING, "%s: timeout sending Terminate-Request state=%d\n", - PROTO_NAME(f), f->state)); - /* - * We've waited for an ack long enough. Peer probably heard us. - */ - f->state = (f->state == CLOSING)? CLOSED: STOPPED; - if( f->callbacks->finished ) - (*f->callbacks->finished)(f); - } else { - FSMDEBUG((LOG_WARNING, "%s: timeout resending Terminate-Requests state=%d\n", - PROTO_NAME(f), f->state)); - /* Send Terminate-Request */ - fsm_sdata(f, TERMREQ, f->reqid = ++f->id, - (u_char *) f->term_reason, f->term_reason_len); - TIMEOUT(fsm_timeout, f, f->timeouttime); - --f->retransmits; - } - break; - - case REQSENT: - case ACKRCVD: - case ACKSENT: - if (f->retransmits <= 0) { - FSMDEBUG((LOG_WARNING, "%s: timeout sending Config-Requests state=%d\n", - PROTO_NAME(f), f->state)); - f->state = STOPPED; - if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished ) - (*f->callbacks->finished)(f); - - } else { - FSMDEBUG((LOG_WARNING, "%s: timeout resending Config-Request state=%d\n", - PROTO_NAME(f), f->state)); - /* Retransmit the configure-request */ - if (f->callbacks->retransmit) - (*f->callbacks->retransmit)(f); - fsm_sconfreq(f, 1); /* Re-send Configure-Request */ - if( f->state == ACKRCVD ) - f->state = REQSENT; - } - break; - - default: - FSMDEBUG((LOG_INFO, "%s: Timeout event in state %d!\n", - PROTO_NAME(f), f->state)); - } -} - - -/* - * fsm_rconfreq - Receive Configure-Request. - */ -static void fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len) -{ - int code, reject_if_disagree; - - FSMDEBUG((LOG_INFO, "fsm_rconfreq(%s): Rcvd id %d state=%d\n", - PROTO_NAME(f), id, f->state)); - switch( f->state ){ - case CLOSED: - /* Go away, we're closed */ - fsm_sdata(f, TERMACK, id, NULL, 0); - return; - case CLOSING: - case STOPPING: - return; - - case OPENED: - /* Go down and restart negotiation */ - if( f->callbacks->down ) - (*f->callbacks->down)(f); /* Inform upper layers */ - fsm_sconfreq(f, 0); /* Send initial Configure-Request */ - break; - - case STOPPED: - /* Negotiation started by our peer */ - fsm_sconfreq(f, 0); /* Send initial Configure-Request */ - f->state = REQSENT; - break; - } - - /* - * Pass the requested configuration options - * to protocol-specific code for checking. - */ - if (f->callbacks->reqci){ /* Check CI */ - reject_if_disagree = (f->nakloops >= f->maxnakloops); - code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree); - } - else if (len) - code = CONFREJ; /* Reject all CI */ - else - code = CONFACK; - - /* send the Ack, Nak or Rej to the peer */ - fsm_sdata(f, (u_char)code, id, inp, len); - - if (code == CONFACK) { - if (f->state == ACKRCVD) { - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - f->state = OPENED; - if (f->callbacks->up) - (*f->callbacks->up)(f); /* Inform upper layers */ - } - else - f->state = ACKSENT; - f->nakloops = 0; - } - else { - /* we sent CONFACK or CONFREJ */ - if (f->state != ACKRCVD) - f->state = REQSENT; - if( code == CONFNAK ) - ++f->nakloops; - } -} - - -/* - * fsm_rconfack - Receive Configure-Ack. - */ -static void fsm_rconfack(fsm *f, int id, u_char *inp, int len) -{ - FSMDEBUG((LOG_INFO, "fsm_rconfack(%s): Rcvd id %d state=%d\n", - PROTO_NAME(f), id, f->state)); - - if (id != f->reqid || f->seen_ack) /* Expected id? */ - return; /* Nope, toss... */ - if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len): - (len == 0)) ){ - /* Ack is bad - ignore it */ - FSMDEBUG((LOG_INFO, "%s: received bad Ack (length %d)\n", - PROTO_NAME(f), len)); - return; - } - f->seen_ack = 1; - - switch (f->state) { - case CLOSED: - case STOPPED: - fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); - break; - - case REQSENT: - f->state = ACKRCVD; - f->retransmits = f->maxconfreqtransmits; - break; - - case ACKRCVD: - /* Huh? an extra valid Ack? oh well... */ - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - fsm_sconfreq(f, 0); - f->state = REQSENT; - break; - - case ACKSENT: - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - f->state = OPENED; - f->retransmits = f->maxconfreqtransmits; - if (f->callbacks->up) - (*f->callbacks->up)(f); /* Inform upper layers */ - break; - - case OPENED: - /* Go down and restart negotiation */ - if (f->callbacks->down) - (*f->callbacks->down)(f); /* Inform upper layers */ - fsm_sconfreq(f, 0); /* Send initial Configure-Request */ - f->state = REQSENT; - break; - } -} - - -/* - * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject. - */ -static void fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len) -{ - int (*proc) (fsm *, u_char *, int); - int ret; - - FSMDEBUG((LOG_INFO, "fsm_rconfnakrej(%s): Rcvd id %d state=%d\n", - PROTO_NAME(f), id, f->state)); - - if (id != f->reqid || f->seen_ack) /* Expected id? */ - return; /* Nope, toss... */ - proc = (code == CONFNAK)? f->callbacks->nakci: f->callbacks->rejci; - if (!proc || !(ret = proc(f, inp, len))) { - /* Nak/reject is bad - ignore it */ - FSMDEBUG((LOG_INFO, "%s: received bad %s (length %d)\n", - PROTO_NAME(f), (code==CONFNAK? "Nak": "reject"), len)); - return; - } - f->seen_ack = 1; - - switch (f->state) { - case CLOSED: - case STOPPED: - fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); - break; - - case REQSENT: - case ACKSENT: - /* They didn't agree to what we wanted - try another request */ - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - if (ret < 0) - f->state = STOPPED; /* kludge for stopping CCP */ - else - fsm_sconfreq(f, 0); /* Send Configure-Request */ - break; - - case ACKRCVD: - /* Got a Nak/reject when we had already had an Ack?? oh well... */ - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - fsm_sconfreq(f, 0); - f->state = REQSENT; - break; - - case OPENED: - /* Go down and restart negotiation */ - if (f->callbacks->down) - (*f->callbacks->down)(f); /* Inform upper layers */ - fsm_sconfreq(f, 0); /* Send initial Configure-Request */ - f->state = REQSENT; - break; - } -} - - -/* - * fsm_rtermreq - Receive Terminate-Req. - */ -static void fsm_rtermreq(fsm *f, int id, u_char *p, int len) -{ - FSMDEBUG((LOG_INFO, "fsm_rtermreq(%s): Rcvd id %d state=%d\n", - PROTO_NAME(f), id, f->state)); - - switch (f->state) { - case ACKRCVD: - case ACKSENT: - f->state = REQSENT; /* Start over but keep trying */ - break; - - case OPENED: - if (len > 0) { - FSMDEBUG((LOG_INFO, "%s terminated by peer (%x)\n", PROTO_NAME(f), p)); - } else { - FSMDEBUG((LOG_INFO, "%s terminated by peer\n", PROTO_NAME(f))); - } - if (f->callbacks->down) - (*f->callbacks->down)(f); /* Inform upper layers */ - f->retransmits = 0; - f->state = STOPPING; - TIMEOUT(fsm_timeout, f, f->timeouttime); - break; - } - - fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); -} - - -/* - * fsm_rtermack - Receive Terminate-Ack. - */ -static void fsm_rtermack(fsm *f) -{ - FSMDEBUG((LOG_INFO, "fsm_rtermack(%s): state=%d\n", - PROTO_NAME(f), f->state)); - - switch (f->state) { - case CLOSING: - UNTIMEOUT(fsm_timeout, f); - f->state = CLOSED; - if( f->callbacks->finished ) - (*f->callbacks->finished)(f); - break; - case STOPPING: - UNTIMEOUT(fsm_timeout, f); - f->state = STOPPED; - if( f->callbacks->finished ) - (*f->callbacks->finished)(f); - break; - - case ACKRCVD: - f->state = REQSENT; - break; - - case OPENED: - if (f->callbacks->down) - (*f->callbacks->down)(f); /* Inform upper layers */ - fsm_sconfreq(f, 0); - break; - } -} - - -/* - * fsm_rcoderej - Receive an Code-Reject. - */ -static void fsm_rcoderej(fsm *f, u_char *inp, int len) -{ - u_char code, id; - - FSMDEBUG((LOG_INFO, "fsm_rcoderej(%s): state=%d\n", - PROTO_NAME(f), f->state)); - - if (len < HEADERLEN) { - FSMDEBUG((LOG_INFO, "fsm_rcoderej: Rcvd short Code-Reject packet!\n")); - return; - } - GETCHAR(code, inp); - GETCHAR(id, inp); - FSMDEBUG((LOG_WARNING, "%s: Rcvd Code-Reject for code %d, id %d\n", - PROTO_NAME(f), code, id)); - - if( f->state == ACKRCVD ) - f->state = REQSENT; -} - - -/* - * fsm_sconfreq - Send a Configure-Request. - */ -static void fsm_sconfreq(fsm *f, int retransmit) -{ - u_char *outp; - int cilen; - - if( f->state != REQSENT && f->state != ACKRCVD && f->state != ACKSENT ){ - /* Not currently negotiating - reset options */ - if( f->callbacks->resetci ) - (*f->callbacks->resetci)(f); - f->nakloops = 0; - } - - if( !retransmit ){ - /* New request - reset retransmission counter, use new ID */ - f->retransmits = f->maxconfreqtransmits; - f->reqid = ++f->id; - } - - f->seen_ack = 0; - - /* - * Make up the request packet - */ - outp = outpacket_buf[f->unit] + PPP_HDRLEN + HEADERLEN; - if( f->callbacks->cilen && f->callbacks->addci ){ - cilen = (*f->callbacks->cilen)(f); - if( cilen > peer_mru[f->unit] - (int)HEADERLEN ) - cilen = peer_mru[f->unit] - HEADERLEN; - if (f->callbacks->addci) - (*f->callbacks->addci)(f, outp, &cilen); - } else - cilen = 0; - - /* send the request to our peer */ - fsm_sdata(f, CONFREQ, f->reqid, outp, cilen); - - /* start the retransmit timer */ - --f->retransmits; - TIMEOUT(fsm_timeout, f, f->timeouttime); - - FSMDEBUG((LOG_INFO, "%s: sending Configure-Request, id %d\n", - PROTO_NAME(f), f->reqid)); -} - -#endif /* PPP_SUPPORT */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/fsm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/fsm.h deleted file mode 100644 index b2da3e3e2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/fsm.h +++ /dev/null @@ -1,187 +0,0 @@ -/***************************************************************************** -* fsm.h - Network Control Protocol Finite State Machine header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-11-05 Guy Lancaster , Global Election Systems Inc. -* Original based on BSD code. -*****************************************************************************/ -/* - * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id$ - */ - -#ifndef FSM_H -#define FSM_H - - -/***************************************************************************** -************************* PUBLIC DEFINITIONS ********************************* -*****************************************************************************/ -/* - * LCP Packet header = Code, id, length. - */ -#define HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short)) - - -/* - * CP (LCP, IPCP, etc.) codes. - */ -#define CONFREQ 1 /* Configuration Request */ -#define CONFACK 2 /* Configuration Ack */ -#define CONFNAK 3 /* Configuration Nak */ -#define CONFREJ 4 /* Configuration Reject */ -#define TERMREQ 5 /* Termination Request */ -#define TERMACK 6 /* Termination Ack */ -#define CODEREJ 7 /* Code Reject */ - -/* - * Link states. - */ -#define INITIAL 0 /* Down, hasn't been opened */ -#define STARTING 1 /* Down, been opened */ -#define CLOSED 2 /* Up, hasn't been opened */ -#define STOPPED 3 /* Open, waiting for down event */ -#define CLOSING 4 /* Terminating the connection, not open */ -#define STOPPING 5 /* Terminating, but open */ -#define REQSENT 6 /* We've sent a Config Request */ -#define ACKRCVD 7 /* We've received a Config Ack */ -#define ACKSENT 8 /* We've sent a Config Ack */ -#define OPENED 9 /* Connection available */ - - -/* - * Flags - indicate options controlling FSM operation - */ -#define OPT_PASSIVE 1 /* Don't die if we don't get a response */ -#define OPT_RESTART 2 /* Treat 2nd OPEN as DOWN, UP */ -#define OPT_SILENT 4 /* Wait for peer to speak first */ - - -/***************************************************************************** -************************* PUBLIC DATA TYPES ********************************** -*****************************************************************************/ -/* - * Each FSM is described by an fsm structure and fsm callbacks. - */ -typedef struct fsm { - int unit; /* Interface unit number */ - u_short protocol; /* Data Link Layer Protocol field value */ - int state; /* State */ - int flags; /* Contains option bits */ - u_char id; /* Current id */ - u_char reqid; /* Current request id */ - u_char seen_ack; /* Have received valid Ack/Nak/Rej to Req */ - int timeouttime; /* Timeout time in milliseconds */ - int maxconfreqtransmits;/* Maximum Configure-Request transmissions */ - int retransmits; /* Number of retransmissions left */ - int maxtermtransmits; /* Maximum Terminate-Request transmissions */ - int nakloops; /* Number of nak loops since last ack */ - int maxnakloops; /* Maximum number of nak loops tolerated */ - struct fsm_callbacks* callbacks;/* Callback routines */ - char* term_reason; /* Reason for closing protocol */ - int term_reason_len; /* Length of term_reason */ -} fsm; - - -typedef struct fsm_callbacks { - void (*resetci) /* Reset our Configuration Information */ - (fsm*); - int (*cilen) /* Length of our Configuration Information */ - (fsm*); - void (*addci) /* Add our Configuration Information */ - (fsm*, u_char*, int*); - int (*ackci) /* ACK our Configuration Information */ - (fsm*, u_char*, int); - int (*nakci) /* NAK our Configuration Information */ - (fsm*, u_char*, int); - int (*rejci) /* Reject our Configuration Information */ - (fsm*, u_char*, int); - int (*reqci) /* Request peer's Configuration Information */ - (fsm*, u_char*, int*, int); - void (*up) /* Called when fsm reaches OPENED state */ - (fsm*); - void (*down) /* Called when fsm leaves OPENED state */ - (fsm*); - void (*starting) /* Called when we want the lower layer */ - (fsm*); - void (*finished) /* Called when we don't want the lower layer */ - (fsm*); - void (*protreject) /* Called when Protocol-Reject received */ - (int); - void (*retransmit) /* Retransmission is necessary */ - (fsm*); - int (*extcode) /* Called when unknown code received */ - (fsm*, int, u_char, u_char*, int); - char *proto_name; /* String name for protocol (for messages) */ -} fsm_callbacks; - - -/***************************************************************************** -*********************** PUBLIC DATA STRUCTURES ******************************* -*****************************************************************************/ -/* - * Variables - */ -extern int peer_mru[]; /* currently negotiated peer MRU (per unit) */ - - -/***************************************************************************** -************************** PUBLIC FUNCTIONS ********************************** -*****************************************************************************/ - -/* - * Prototypes - */ -void fsm_init (fsm*); -void fsm_lowerup (fsm*); -void fsm_lowerdown (fsm*); -void fsm_open (fsm*); -void fsm_close (fsm*, char*); -void fsm_input (fsm*, u_char*, int); -void fsm_protreject (fsm*); -void fsm_sdata (fsm*, u_char, u_char, u_char*, int); - - -#endif /* FSM_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/ipcp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/ipcp.c deleted file mode 100644 index d5b251880..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/ipcp.c +++ /dev/null @@ -1,1377 +0,0 @@ -/***************************************************************************** -* ipcp.c - Network PPP IP Control Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-08 Guy Lancaster , Global Election Systems Inc. -* Original. -*****************************************************************************/ -/* - * ipcp.c - PPP IP Control Protocol. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include - -#include "ppp.h" -#if PPP_SUPPORT > 0 -#include "auth.h" -#include "fsm.h" -#include "vj.h" -#include "ipcp.h" -#include "pppdebug.h" - - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ -/* #define OLD_CI_ADDRS 1 */ /* Support deprecated address negotiation. */ - -/* - * Lengths of configuration options. - */ -#define CILEN_VOID 2 -#define CILEN_COMPRESS 4 /* min length for compression protocol opt. */ -#define CILEN_VJ 6 /* length for RFC1332 Van-Jacobson opt. */ -#define CILEN_ADDR 6 /* new-style single address option */ -#define CILEN_ADDRS 10 /* old-style dual address option */ - - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -/* - * Callbacks for fsm code. (CI = Configuration Information) - */ -static void ipcp_resetci (fsm *); /* Reset our CI */ -static int ipcp_cilen (fsm *); /* Return length of our CI */ -static void ipcp_addci (fsm *, u_char *, int *); /* Add our CI */ -static int ipcp_ackci (fsm *, u_char *, int); /* Peer ack'd our CI */ -static int ipcp_nakci (fsm *, u_char *, int); /* Peer nak'd our CI */ -static int ipcp_rejci (fsm *, u_char *, int); /* Peer rej'd our CI */ -static int ipcp_reqci (fsm *, u_char *, int *, int); /* Rcv CI */ -static void ipcp_up (fsm *); /* We're UP */ -static void ipcp_down (fsm *); /* We're DOWN */ -#if 0 -static void ipcp_script (fsm *, char *); /* Run an up/down script */ -#endif -static void ipcp_finished (fsm *); /* Don't need lower layer */ - -/* - * Protocol entry points from main code. - */ -static void ipcp_init (int); -static void ipcp_open (int); -static void ipcp_close (int, char *); -static void ipcp_lowerup (int); -static void ipcp_lowerdown (int); -static void ipcp_input (int, u_char *, int); -static void ipcp_protrej (int); - -static void ipcp_clear_addrs (int); - -#define CODENAME(x) ((x) == CONFACK ? "ACK" : \ - (x) == CONFNAK ? "NAK" : "REJ") - - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ -/* global vars */ -ipcp_options ipcp_wantoptions[NUM_PPP]; /* Options that we want to request */ -ipcp_options ipcp_gotoptions[NUM_PPP]; /* Options that peer ack'd */ -ipcp_options ipcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */ -ipcp_options ipcp_hisoptions[NUM_PPP]; /* Options that we ack'd */ - -fsm ipcp_fsm[NUM_PPP]; /* IPCP fsm structure */ - -struct protent ipcp_protent = { - PPP_IPCP, - ipcp_init, - ipcp_input, - ipcp_protrej, - ipcp_lowerup, - ipcp_lowerdown, - ipcp_open, - ipcp_close, -#if 0 - ipcp_printpkt, - NULL, -#endif - 1, - "IPCP", -#if 0 - ip_check_options, - NULL, - ip_active_pkt -#endif -}; - - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -/* local vars */ -static int cis_received[NUM_PPP]; /* # Conf-Reqs received */ -static int default_route_set[NUM_PPP]; /* Have set up a default route */ - -static fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */ - ipcp_resetci, /* Reset our Configuration Information */ - ipcp_cilen, /* Length of our Configuration Information */ - ipcp_addci, /* Add our Configuration Information */ - ipcp_ackci, /* ACK our Configuration Information */ - ipcp_nakci, /* NAK our Configuration Information */ - ipcp_rejci, /* Reject our Configuration Information */ - ipcp_reqci, /* Request peer's Configuration Information */ - ipcp_up, /* Called when fsm reaches OPENED state */ - ipcp_down, /* Called when fsm leaves OPENED state */ - NULL, /* Called when we want the lower layer up */ - ipcp_finished, /* Called when we want the lower layer down */ - NULL, /* Called when Protocol-Reject received */ - NULL, /* Retransmission is necessary */ - NULL, /* Called to handle protocol-specific codes */ - "IPCP" /* String name of protocol */ -}; - - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ - -/* - * Non-standard inet_ntoa left here for compat with original ppp - * sources. Assumes u32_t instead of struct in_addr. - */ - -char * _inet_ntoa(u32_t n) -{ - struct in_addr ia; - ia.s_addr = n; - return inet_ntoa(ia); -} - -#define inet_ntoa _inet_ntoa - -/* - * ipcp_init - Initialize IPCP. - */ -static void ipcp_init(int unit) -{ - fsm *f = &ipcp_fsm[unit]; - ipcp_options *wo = &ipcp_wantoptions[unit]; - ipcp_options *ao = &ipcp_allowoptions[unit]; - - f->unit = unit; - f->protocol = PPP_IPCP; - f->callbacks = &ipcp_callbacks; - fsm_init(&ipcp_fsm[unit]); - - memset(wo, 0, sizeof(*wo)); - memset(ao, 0, sizeof(*ao)); - - wo->neg_addr = 1; - wo->ouraddr = 0; -#if VJ_SUPPORT > 0 - wo->neg_vj = 1; -#else - wo->neg_vj = 0; -#endif - wo->vj_protocol = IPCP_VJ_COMP; - wo->maxslotindex = MAX_SLOTS - 1; - wo->cflag = 0; - - wo->default_route = 1; - - ao->neg_addr = 1; -#if VJ_SUPPORT > 0 - ao->neg_vj = 1; -#else - ao->neg_vj = 0; -#endif - ao->maxslotindex = MAX_SLOTS - 1; - ao->cflag = 1; - - ao->default_route = 1; -} - - -/* - * ipcp_open - IPCP is allowed to come up. - */ -static void ipcp_open(int unit) -{ - fsm_open(&ipcp_fsm[unit]); -} - - -/* - * ipcp_close - Take IPCP down. - */ -static void ipcp_close(int unit, char *reason) -{ - fsm_close(&ipcp_fsm[unit], reason); -} - - -/* - * ipcp_lowerup - The lower layer is up. - */ -static void ipcp_lowerup(int unit) -{ - fsm_lowerup(&ipcp_fsm[unit]); -} - - -/* - * ipcp_lowerdown - The lower layer is down. - */ -static void ipcp_lowerdown(int unit) -{ - fsm_lowerdown(&ipcp_fsm[unit]); -} - - -/* - * ipcp_input - Input IPCP packet. - */ -static void ipcp_input(int unit, u_char *p, int len) -{ - fsm_input(&ipcp_fsm[unit], p, len); -} - - -/* - * ipcp_protrej - A Protocol-Reject was received for IPCP. - * - * Pretend the lower layer went down, so we shut up. - */ -static void ipcp_protrej(int unit) -{ - fsm_lowerdown(&ipcp_fsm[unit]); -} - - -/* - * ipcp_resetci - Reset our CI. - */ -static void ipcp_resetci(fsm *f) -{ - ipcp_options *wo = &ipcp_wantoptions[f->unit]; - - wo->req_addr = wo->neg_addr && ipcp_allowoptions[f->unit].neg_addr; - if (wo->ouraddr == 0) - wo->accept_local = 1; - if (wo->hisaddr == 0) - wo->accept_remote = 1; - /* Request DNS addresses from the peer */ - wo->req_dns1 = ppp_settings.usepeerdns; - wo->req_dns2 = ppp_settings.usepeerdns; - ipcp_gotoptions[f->unit] = *wo; - cis_received[f->unit] = 0; -} - - -/* - * ipcp_cilen - Return length of our CI. - */ -static int ipcp_cilen(fsm *f) -{ - ipcp_options *go = &ipcp_gotoptions[f->unit]; - ipcp_options *wo = &ipcp_wantoptions[f->unit]; - ipcp_options *ho = &ipcp_hisoptions[f->unit]; - -#define LENCIVJ(neg, old) (neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0) -#define LENCIADDR(neg, old) (neg ? (old? CILEN_ADDRS : CILEN_ADDR) : 0) -#define LENCIDNS(neg) (neg ? (CILEN_ADDR) : 0) - - /* - * First see if we want to change our options to the old - * forms because we have received old forms from the peer. - */ - if (wo->neg_addr && !go->neg_addr && !go->old_addrs) { - /* use the old style of address negotiation */ - go->neg_addr = 1; - go->old_addrs = 1; - } - if (wo->neg_vj && !go->neg_vj && !go->old_vj) { - /* try an older style of VJ negotiation */ - if (cis_received[f->unit] == 0) { - /* keep trying the new style until we see some CI from the peer */ - go->neg_vj = 1; - } else { - /* use the old style only if the peer did */ - if (ho->neg_vj && ho->old_vj) { - go->neg_vj = 1; - go->old_vj = 1; - go->vj_protocol = ho->vj_protocol; - } - } - } - - return (LENCIADDR(go->neg_addr, go->old_addrs) - + LENCIVJ(go->neg_vj, go->old_vj) + - LENCIDNS(go->req_dns1) + - LENCIDNS(go->req_dns2)); -} - - -/* - * ipcp_addci - Add our desired CIs to a packet. - */ -static void ipcp_addci(fsm *f, u_char *ucp, int *lenp) -{ - ipcp_options *go = &ipcp_gotoptions[f->unit]; - int len = *lenp; - -#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \ - if (neg) { \ - int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \ - if (len >= vjlen) { \ - PUTCHAR(opt, ucp); \ - PUTCHAR(vjlen, ucp); \ - PUTSHORT(val, ucp); \ - if (!old) { \ - PUTCHAR(maxslotindex, ucp); \ - PUTCHAR(cflag, ucp); \ - } \ - len -= vjlen; \ - } else \ - neg = 0; \ - } - -#define ADDCIADDR(opt, neg, old, val1, val2) \ - if (neg) { \ - int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \ - if (len >= addrlen) { \ - u32_t l; \ - PUTCHAR(opt, ucp); \ - PUTCHAR(addrlen, ucp); \ - l = ntohl(val1); \ - PUTLONG(l, ucp); \ - if (old) { \ - l = ntohl(val2); \ - PUTLONG(l, ucp); \ - } \ - len -= addrlen; \ - } else \ - neg = 0; \ - } - -#define ADDCIDNS(opt, neg, addr) \ - if (neg) { \ - if (len >= CILEN_ADDR) { \ - u32_t l; \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_ADDR, ucp); \ - l = ntohl(addr); \ - PUTLONG(l, ucp); \ - len -= CILEN_ADDR; \ - } else \ - neg = 0; \ - } - - ADDCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr, - go->old_addrs, go->ouraddr, go->hisaddr); - - ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj, - go->maxslotindex, go->cflag); - - ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]); - - ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]); - - *lenp -= len; -} - - -/* - * ipcp_ackci - Ack our CIs. - * - * Returns: - * 0 - Ack was bad. - * 1 - Ack was good. - */ -static int ipcp_ackci(fsm *f, u_char *p, int len) -{ - ipcp_options *go = &ipcp_gotoptions[f->unit]; - u_short cilen, citype, cishort; - u32_t cilong; - u_char cimaxslotindex, cicflag; - - /* - * CIs must be in exactly the same order that we sent... - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ - -#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \ - if (neg) { \ - int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \ - if ((len -= vjlen) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != vjlen || \ - citype != opt) \ - goto bad; \ - GETSHORT(cishort, p); \ - if (cishort != val) \ - goto bad; \ - if (!old) { \ - GETCHAR(cimaxslotindex, p); \ - if (cimaxslotindex != maxslotindex) \ - goto bad; \ - GETCHAR(cicflag, p); \ - if (cicflag != cflag) \ - goto bad; \ - } \ - } - -#define ACKCIADDR(opt, neg, old, val1, val2) \ - if (neg) { \ - int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \ - u32_t l; \ - if ((len -= addrlen) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != addrlen || \ - citype != opt) \ - goto bad; \ - GETLONG(l, p); \ - cilong = htonl(l); \ - if (val1 != cilong) \ - goto bad; \ - if (old) { \ - GETLONG(l, p); \ - cilong = htonl(l); \ - if (val2 != cilong) \ - goto bad; \ - } \ - } - -#define ACKCIDNS(opt, neg, addr) \ - if (neg) { \ - u32_t l; \ - if ((len -= CILEN_ADDR) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_ADDR || \ - citype != opt) \ - goto bad; \ - GETLONG(l, p); \ - cilong = htonl(l); \ - if (addr != cilong) \ - goto bad; \ - } - - ACKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr, - go->old_addrs, go->ouraddr, go->hisaddr); - - ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj, - go->maxslotindex, go->cflag); - - ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]); - - ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]); - - /* - * If there are any remaining CIs, then this packet is bad. - */ - if (len != 0) - goto bad; - return (1); - -bad: - IPCPDEBUG((LOG_INFO, "ipcp_ackci: received bad Ack!\n")); - return (0); -} - -/* - * ipcp_nakci - Peer has sent a NAK for some of our CIs. - * This should not modify any state if the Nak is bad - * or if IPCP is in the OPENED state. - * - * Returns: - * 0 - Nak was bad. - * 1 - Nak was good. - */ -static int ipcp_nakci(fsm *f, u_char *p, int len) -{ - ipcp_options *go = &ipcp_gotoptions[f->unit]; - u_char cimaxslotindex, cicflag; - u_char citype, cilen, *next; - u_short cishort; - u32_t ciaddr1, ciaddr2, l, cidnsaddr; - ipcp_options no; /* options we've seen Naks for */ - ipcp_options try; /* options to request next time */ - - BZERO(&no, sizeof(no)); - try = *go; - - /* - * Any Nak'd CIs must be in exactly the same order that we sent. - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ -#define NAKCIADDR(opt, neg, old, code) \ - if (go->neg && \ - len >= (cilen = (old? CILEN_ADDRS: CILEN_ADDR)) && \ - p[1] == cilen && \ - p[0] == opt) { \ - len -= cilen; \ - INCPTR(2, p); \ - GETLONG(l, p); \ - ciaddr1 = htonl(l); \ - if (old) { \ - GETLONG(l, p); \ - ciaddr2 = htonl(l); \ - no.old_addrs = 1; \ - } else \ - ciaddr2 = 0; \ - no.neg = 1; \ - code \ - } - -#define NAKCIVJ(opt, neg, code) \ - if (go->neg && \ - ((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \ - len >= cilen && \ - p[0] == opt) { \ - len -= cilen; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - no.neg = 1; \ - code \ - } - -#define NAKCIDNS(opt, neg, code) \ - if (go->neg && \ - ((cilen = p[1]) == CILEN_ADDR) && \ - len >= cilen && \ - p[0] == opt) { \ - len -= cilen; \ - INCPTR(2, p); \ - GETLONG(l, p); \ - cidnsaddr = htonl(l); \ - no.neg = 1; \ - code \ - } - - /* - * Accept the peer's idea of {our,his} address, if different - * from our idea, only if the accept_{local,remote} flag is set. - */ - NAKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, go->old_addrs, - if (go->accept_local && ciaddr1) { /* Do we know our address? */ - try.ouraddr = ciaddr1; - IPCPDEBUG((LOG_INFO, "local IP address %s\n", - inet_ntoa(ciaddr1))); - } - if (go->accept_remote && ciaddr2) { /* Does he know his? */ - try.hisaddr = ciaddr2; - IPCPDEBUG((LOG_INFO, "remote IP address %s\n", - inet_ntoa(ciaddr2))); - } - ); - - /* - * Accept the peer's value of maxslotindex provided that it - * is less than what we asked for. Turn off slot-ID compression - * if the peer wants. Send old-style compress-type option if - * the peer wants. - */ - NAKCIVJ(CI_COMPRESSTYPE, neg_vj, - if (cilen == CILEN_VJ) { - GETCHAR(cimaxslotindex, p); - GETCHAR(cicflag, p); - if (cishort == IPCP_VJ_COMP) { - try.old_vj = 0; - if (cimaxslotindex < go->maxslotindex) - try.maxslotindex = cimaxslotindex; - if (!cicflag) - try.cflag = 0; - } else { - try.neg_vj = 0; - } - } else { - if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) { - try.old_vj = 1; - try.vj_protocol = cishort; - } else { - try.neg_vj = 0; - } - } - ); - - NAKCIDNS(CI_MS_DNS1, req_dns1, - try.dnsaddr[0] = cidnsaddr; - IPCPDEBUG((LOG_INFO, "primary DNS address %s\n", inet_ntoa(cidnsaddr))); - ); - - NAKCIDNS(CI_MS_DNS2, req_dns2, - try.dnsaddr[1] = cidnsaddr; - IPCPDEBUG((LOG_INFO, "secondary DNS address %s\n", inet_ntoa(cidnsaddr))); - ); - - /* - * There may be remaining CIs, if the peer is requesting negotiation - * on an option that we didn't include in our request packet. - * If they want to negotiate about IP addresses, we comply. - * If they want us to ask for compression, we refuse. - */ - while (len > CILEN_VOID) { - GETCHAR(citype, p); - GETCHAR(cilen, p); - if( (len -= cilen) < 0 ) - goto bad; - next = p + cilen - 2; - - switch (citype) { - case CI_COMPRESSTYPE: - if (go->neg_vj || no.neg_vj || - (cilen != CILEN_VJ && cilen != CILEN_COMPRESS)) - goto bad; - no.neg_vj = 1; - break; - case CI_ADDRS: - if ((go->neg_addr && go->old_addrs) || no.old_addrs - || cilen != CILEN_ADDRS) - goto bad; - try.neg_addr = 1; - try.old_addrs = 1; - GETLONG(l, p); - ciaddr1 = htonl(l); - if (ciaddr1 && go->accept_local) - try.ouraddr = ciaddr1; - GETLONG(l, p); - ciaddr2 = htonl(l); - if (ciaddr2 && go->accept_remote) - try.hisaddr = ciaddr2; - no.old_addrs = 1; - break; - case CI_ADDR: - if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR) - goto bad; - try.old_addrs = 0; - GETLONG(l, p); - ciaddr1 = htonl(l); - if (ciaddr1 && go->accept_local) - try.ouraddr = ciaddr1; - if (try.ouraddr != 0) - try.neg_addr = 1; - no.neg_addr = 1; - break; - } - p = next; - } - - /* If there is still anything left, this packet is bad. */ - if (len != 0) - goto bad; - - /* - * OK, the Nak is good. Now we can update state. - */ - if (f->state != OPENED) - *go = try; - - return 1; - -bad: - IPCPDEBUG((LOG_INFO, "ipcp_nakci: received bad Nak!\n")); - return 0; -} - - -/* - * ipcp_rejci - Reject some of our CIs. - */ -static int ipcp_rejci(fsm *f, u_char *p, int len) -{ - ipcp_options *go = &ipcp_gotoptions[f->unit]; - u_char cimaxslotindex, ciflag, cilen; - u_short cishort; - u32_t cilong; - ipcp_options try; /* options to request next time */ - - try = *go; - /* - * Any Rejected CIs must be in exactly the same order that we sent. - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ -#define REJCIADDR(opt, neg, old, val1, val2) \ - if (go->neg && \ - len >= (cilen = old? CILEN_ADDRS: CILEN_ADDR) && \ - p[1] == cilen && \ - p[0] == opt) { \ - u32_t l; \ - len -= cilen; \ - INCPTR(2, p); \ - GETLONG(l, p); \ - cilong = htonl(l); \ - /* Check rejected value. */ \ - if (cilong != val1) \ - goto bad; \ - if (old) { \ - GETLONG(l, p); \ - cilong = htonl(l); \ - /* Check rejected value. */ \ - if (cilong != val2) \ - goto bad; \ - } \ - try.neg = 0; \ - } - -#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \ - if (go->neg && \ - p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \ - len >= p[1] && \ - p[0] == opt) { \ - len -= p[1]; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - /* Check rejected value. */ \ - if (cishort != val) \ - goto bad; \ - if (!old) { \ - GETCHAR(cimaxslotindex, p); \ - if (cimaxslotindex != maxslot) \ - goto bad; \ - GETCHAR(ciflag, p); \ - if (ciflag != cflag) \ - goto bad; \ - } \ - try.neg = 0; \ - } - -#define REJCIDNS(opt, neg, dnsaddr) \ - if (go->neg && \ - ((cilen = p[1]) == CILEN_ADDR) && \ - len >= cilen && \ - p[0] == opt) { \ - u32_t l; \ - len -= cilen; \ - INCPTR(2, p); \ - GETLONG(l, p); \ - cilong = htonl(l); \ - /* Check rejected value. */ \ - if (cilong != dnsaddr) \ - goto bad; \ - try.neg = 0; \ - } - - REJCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, - go->old_addrs, go->ouraddr, go->hisaddr); - - REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj, - go->maxslotindex, go->cflag); - - REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]); - - REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]); - - /* - * If there are any remaining CIs, then this packet is bad. - */ - if (len != 0) - goto bad; - /* - * Now we can update state. - */ - if (f->state != OPENED) - *go = try; - return 1; - -bad: - IPCPDEBUG((LOG_INFO, "ipcp_rejci: received bad Reject!\n")); - return 0; -} - - -/* - * ipcp_reqci - Check the peer's requested CIs and send appropriate response. - * - * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified - * appropriately. If reject_if_disagree is non-zero, doesn't return - * CONFNAK; returns CONFREJ if it can't return CONFACK. - */ -static int ipcp_reqci( - fsm *f, - u_char *inp, /* Requested CIs */ - int *len, /* Length of requested CIs */ - int reject_if_disagree -) -{ - ipcp_options *wo = &ipcp_wantoptions[f->unit]; - ipcp_options *ho = &ipcp_hisoptions[f->unit]; - ipcp_options *ao = &ipcp_allowoptions[f->unit]; -#ifdef OLD_CI_ADDRS - ipcp_options *go = &ipcp_gotoptions[f->unit]; -#endif - u_char *cip, *next; /* Pointer to current and next CIs */ - u_short cilen, citype; /* Parsed len, type */ - u_short cishort; /* Parsed short value */ - u32_t tl, ciaddr1; /* Parsed address values */ -#ifdef OLD_CI_ADDRS - u32_t ciaddr2; /* Parsed address values */ -#endif - int rc = CONFACK; /* Final packet return code */ - int orc; /* Individual option return code */ - u_char *p; /* Pointer to next char to parse */ - u_char *ucp = inp; /* Pointer to current output char */ - int l = *len; /* Length left */ - u_char maxslotindex, cflag; - int d; - - cis_received[f->unit] = 1; - - /* - * Reset all his options. - */ - BZERO(ho, sizeof(*ho)); - - /* - * Process all his options. - */ - next = inp; - while (l) { - orc = CONFACK; /* Assume success */ - cip = p = next; /* Remember begining of CI */ - if (l < 2 || /* Not enough data for CI header or */ - p[1] < 2 || /* CI length too small or */ - p[1] > l) { /* CI length too big? */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: bad CI length!\n")); - orc = CONFREJ; /* Reject bad CI */ - cilen = l; /* Reject till end of packet */ - l = 0; /* Don't loop again */ - goto endswitch; - } - GETCHAR(citype, p); /* Parse CI type */ - GETCHAR(cilen, p); /* Parse CI length */ - l -= cilen; /* Adjust remaining length */ - next += cilen; /* Step to next CI */ - - switch (citype) { /* Check CI type */ -#ifdef OLD_CI_ADDRS /* Need to save space... */ - case CI_ADDRS: - IPCPDEBUG((LOG_INFO, "ipcp_reqci: received ADDRS\n")); - if (!ao->neg_addr || - cilen != CILEN_ADDRS) { /* Check CI length */ - orc = CONFREJ; /* Reject CI */ - break; - } - - /* - * If he has no address, or if we both have his address but - * disagree about it, then NAK it with our idea. - * In particular, if we don't know his address, but he does, - * then accept it. - */ - GETLONG(tl, p); /* Parse source address (his) */ - ciaddr1 = htonl(tl); - IPCPDEBUG((LOG_INFO, "his addr %s\n", inet_ntoa(ciaddr1))); - if (ciaddr1 != wo->hisaddr - && (ciaddr1 == 0 || !wo->accept_remote)) { - orc = CONFNAK; - if (!reject_if_disagree) { - DECPTR(sizeof(u32_t), p); - tl = ntohl(wo->hisaddr); - PUTLONG(tl, p); - } - } else if (ciaddr1 == 0 && wo->hisaddr == 0) { - /* - * If neither we nor he knows his address, reject the option. - */ - orc = CONFREJ; - wo->req_addr = 0; /* don't NAK with 0.0.0.0 later */ - break; - } - - /* - * If he doesn't know our address, or if we both have our address - * but disagree about it, then NAK it with our idea. - */ - GETLONG(tl, p); /* Parse desination address (ours) */ - ciaddr2 = htonl(tl); - IPCPDEBUG((LOG_INFO, "our addr %s\n", inet_ntoa(ciaddr2))); - if (ciaddr2 != wo->ouraddr) { - if (ciaddr2 == 0 || !wo->accept_local) { - orc = CONFNAK; - if (!reject_if_disagree) { - DECPTR(sizeof(u32_t), p); - tl = ntohl(wo->ouraddr); - PUTLONG(tl, p); - } - } else { - go->ouraddr = ciaddr2; /* accept peer's idea */ - } - } - - ho->neg_addr = 1; - ho->old_addrs = 1; - ho->hisaddr = ciaddr1; - ho->ouraddr = ciaddr2; - break; -#endif - - case CI_ADDR: - if (!ao->neg_addr) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR not allowed\n")); - orc = CONFREJ; /* Reject CI */ - break; - } else if (cilen != CILEN_ADDR) { /* Check CI length */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR bad len\n")); - orc = CONFREJ; /* Reject CI */ - break; - } - - /* - * If he has no address, or if we both have his address but - * disagree about it, then NAK it with our idea. - * In particular, if we don't know his address, but he does, - * then accept it. - */ - GETLONG(tl, p); /* Parse source address (his) */ - ciaddr1 = htonl(tl); - if (ciaddr1 != wo->hisaddr - && (ciaddr1 == 0 || !wo->accept_remote)) { - orc = CONFNAK; - if (!reject_if_disagree) { - DECPTR(sizeof(u32_t), p); - tl = ntohl(wo->hisaddr); - PUTLONG(tl, p); - } - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Nak ADDR %s\n", inet_ntoa(ciaddr1))); - } else if (ciaddr1 == 0 && wo->hisaddr == 0) { - /* - * Don't ACK an address of 0.0.0.0 - reject it instead. - */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR %s\n", inet_ntoa(ciaddr1))); - orc = CONFREJ; - wo->req_addr = 0; /* don't NAK with 0.0.0.0 later */ - break; - } - - ho->neg_addr = 1; - ho->hisaddr = ciaddr1; - IPCPDEBUG((LOG_INFO, "ipcp_reqci: ADDR %s\n", inet_ntoa(ciaddr1))); - break; - - case CI_MS_DNS1: - case CI_MS_DNS2: - /* Microsoft primary or secondary DNS request */ - d = citype == CI_MS_DNS2; - - /* If we do not have a DNS address then we cannot send it */ - if (ao->dnsaddr[d] == 0 || - cilen != CILEN_ADDR) { /* Check CI length */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting DNS%d Request\n", d+1)); - orc = CONFREJ; /* Reject CI */ - break; - } - GETLONG(tl, p); - if (htonl(tl) != ao->dnsaddr[d]) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking DNS%d Request %d\n", - d+1, inet_ntoa(tl))); - DECPTR(sizeof(u32_t), p); - tl = ntohl(ao->dnsaddr[d]); - PUTLONG(tl, p); - orc = CONFNAK; - } - IPCPDEBUG((LOG_INFO, "ipcp_reqci: received DNS%d Request\n", d+1)); - break; - - case CI_MS_WINS1: - case CI_MS_WINS2: - /* Microsoft primary or secondary WINS request */ - d = citype == CI_MS_WINS2; - IPCPDEBUG((LOG_INFO, "ipcp_reqci: received WINS%d Request\n", d+1)); - - /* If we do not have a DNS address then we cannot send it */ - if (ao->winsaddr[d] == 0 || - cilen != CILEN_ADDR) { /* Check CI length */ - orc = CONFREJ; /* Reject CI */ - break; - } - GETLONG(tl, p); - if (htonl(tl) != ao->winsaddr[d]) { - DECPTR(sizeof(u32_t), p); - tl = ntohl(ao->winsaddr[d]); - PUTLONG(tl, p); - orc = CONFNAK; - } - break; - - case CI_COMPRESSTYPE: - if (!ao->neg_vj) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE not allowed\n")); - orc = CONFREJ; - break; - } else if (cilen != CILEN_VJ && cilen != CILEN_COMPRESS) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE len=%d\n", cilen)); - orc = CONFREJ; - break; - } - GETSHORT(cishort, p); - - if (!(cishort == IPCP_VJ_COMP || - (cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE %d\n", cishort)); - orc = CONFREJ; - break; - } - - ho->neg_vj = 1; - ho->vj_protocol = cishort; - if (cilen == CILEN_VJ) { - GETCHAR(maxslotindex, p); - if (maxslotindex > ao->maxslotindex) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ max slot %d\n", maxslotindex)); - orc = CONFNAK; - if (!reject_if_disagree){ - DECPTR(1, p); - PUTCHAR(ao->maxslotindex, p); - } - } - GETCHAR(cflag, p); - if (cflag && !ao->cflag) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ cflag %d\n", cflag)); - orc = CONFNAK; - if (!reject_if_disagree){ - DECPTR(1, p); - PUTCHAR(wo->cflag, p); - } - } - ho->maxslotindex = maxslotindex; - ho->cflag = cflag; - } else { - ho->old_vj = 1; - ho->maxslotindex = MAX_SLOTS - 1; - ho->cflag = 1; - } - IPCPDEBUG((LOG_INFO, - "ipcp_reqci: received COMPRESSTYPE p=%d old=%d maxslot=%d cflag=%d\n", - ho->vj_protocol, ho->old_vj, ho->maxslotindex, ho->cflag)); - break; - - default: - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting unknown CI type %d\n", citype)); - orc = CONFREJ; - break; - } - -endswitch: - if (orc == CONFACK && /* Good CI */ - rc != CONFACK) /* but prior CI wasnt? */ - continue; /* Don't send this one */ - - if (orc == CONFNAK) { /* Nak this CI? */ - if (reject_if_disagree) { /* Getting fed up with sending NAKs? */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting too many naks\n")); - orc = CONFREJ; /* Get tough if so */ - } else { - if (rc == CONFREJ) /* Rejecting prior CI? */ - continue; /* Don't send this one */ - if (rc == CONFACK) { /* Ack'd all prior CIs? */ - rc = CONFNAK; /* Not anymore... */ - ucp = inp; /* Backup */ - } - } - } - - if (orc == CONFREJ && /* Reject this CI */ - rc != CONFREJ) { /* but no prior ones? */ - rc = CONFREJ; - ucp = inp; /* Backup */ - } - - /* Need to move CI? */ - if (ucp != cip) - BCOPY(cip, ucp, cilen); /* Move it */ - - /* Update output pointer */ - INCPTR(cilen, ucp); - } - - /* - * If we aren't rejecting this packet, and we want to negotiate - * their address, and they didn't send their address, then we - * send a NAK with a CI_ADDR option appended. We assume the - * input buffer is long enough that we can append the extra - * option safely. - */ - if (rc != CONFREJ && !ho->neg_addr && - wo->req_addr && !reject_if_disagree) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Requesting peer address\n")); - if (rc == CONFACK) { - rc = CONFNAK; - ucp = inp; /* reset pointer */ - wo->req_addr = 0; /* don't ask again */ - } - PUTCHAR(CI_ADDR, ucp); - PUTCHAR(CILEN_ADDR, ucp); - tl = ntohl(wo->hisaddr); - PUTLONG(tl, ucp); - } - - *len = (int)(ucp - inp); /* Compute output length */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: returning Configure-%s\n", CODENAME(rc))); - return (rc); /* Return final code */ -} - - -#if 0 -/* - * ip_check_options - check that any IP-related options are OK, - * and assign appropriate defaults. - */ -static void ip_check_options(u_long localAddr) -{ - ipcp_options *wo = &ipcp_wantoptions[0]; - - /* - * Load our default IP address but allow the remote host to give us - * a new address. - */ - if (wo->ouraddr == 0 && !ppp_settings.disable_defaultip) { - wo->accept_local = 1; /* don't insist on this default value */ - wo->ouraddr = htonl(localAddr); - } -} -#endif - - -/* - * ipcp_up - IPCP has come UP. - * - * Configure the IP network interface appropriately and bring it up. - */ -static void ipcp_up(fsm *f) -{ - u32_t mask; - ipcp_options *ho = &ipcp_hisoptions[f->unit]; - ipcp_options *go = &ipcp_gotoptions[f->unit]; - ipcp_options *wo = &ipcp_wantoptions[f->unit]; - - np_up(f->unit, PPP_IP); - IPCPDEBUG((LOG_INFO, "ipcp: up\n")); - - /* - * We must have a non-zero IP address for both ends of the link. - */ - if (!ho->neg_addr) - ho->hisaddr = wo->hisaddr; - - if (ho->hisaddr == 0) { - IPCPDEBUG((LOG_ERR, "Could not determine remote IP address\n")); - ipcp_close(f->unit, "Could not determine remote IP address"); - return; - } - if (go->ouraddr == 0) { - IPCPDEBUG((LOG_ERR, "Could not determine local IP address\n")); - ipcp_close(f->unit, "Could not determine local IP address"); - return; - } - - if (ppp_settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) { - /*pppGotDNSAddrs(go->dnsaddr[0], go->dnsaddr[1]);*/ - } - - /* - * Check that the peer is allowed to use the IP address it wants. - */ - if (!auth_ip_addr(f->unit, ho->hisaddr)) { - IPCPDEBUG((LOG_ERR, "Peer is not authorized to use remote address %s\n", - inet_ntoa(ho->hisaddr))); - ipcp_close(f->unit, "Unauthorized remote IP address"); - return; - } - - /* set tcp compression */ - sifvjcomp(f->unit, ho->neg_vj, ho->cflag, ho->maxslotindex); - - /* - * Set IP addresses and (if specified) netmask. - */ - mask = GetMask(go->ouraddr); - - if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask, go->dnsaddr[0], go->dnsaddr[1])) { - IPCPDEBUG((LOG_WARNING, "sifaddr failed\n")); - ipcp_close(f->unit, "Interface configuration failed"); - return; - } - - /* bring the interface up for IP */ - if (!sifup(f->unit)) { - IPCPDEBUG((LOG_WARNING, "sifup failed\n")); - ipcp_close(f->unit, "Interface configuration failed"); - return; - } - - sifnpmode(f->unit, PPP_IP, NPMODE_PASS); - - /* assign a default route through the interface if required */ - if (ipcp_wantoptions[f->unit].default_route) - if (sifdefaultroute(f->unit, go->ouraddr, ho->hisaddr)) - default_route_set[f->unit] = 1; - - IPCPDEBUG((LOG_NOTICE, "local IP address %s\n", inet_ntoa(go->ouraddr))); - IPCPDEBUG((LOG_NOTICE, "remote IP address %s\n", inet_ntoa(ho->hisaddr))); - if (go->dnsaddr[0]) { - IPCPDEBUG((LOG_NOTICE, "primary DNS address %s\n", inet_ntoa(go->dnsaddr[0]))); - } - if (go->dnsaddr[1]) { - IPCPDEBUG((LOG_NOTICE, "secondary DNS address %s\n", inet_ntoa(go->dnsaddr[1]))); - } -} - - -/* - * ipcp_down - IPCP has gone DOWN. - * - * Take the IP network interface down, clear its addresses - * and delete routes through it. - */ -static void ipcp_down(fsm *f) -{ - IPCPDEBUG((LOG_INFO, "ipcp: down\n")); - np_down(f->unit, PPP_IP); - sifvjcomp(f->unit, 0, 0, 0); - - sifdown(f->unit); - ipcp_clear_addrs(f->unit); -} - - -/* - * ipcp_clear_addrs() - clear the interface addresses, routes, etc. - */ -static void ipcp_clear_addrs(int unit) -{ - u32_t ouraddr, hisaddr; - - ouraddr = ipcp_gotoptions[unit].ouraddr; - hisaddr = ipcp_hisoptions[unit].hisaddr; - if (default_route_set[unit]) { - cifdefaultroute(unit, ouraddr, hisaddr); - default_route_set[unit] = 0; - } - cifaddr(unit, ouraddr, hisaddr); -} - - -/* - * ipcp_finished - possibly shut down the lower layers. - */ -static void ipcp_finished(fsm *f) -{ - np_finished(f->unit, PPP_IP); -} - -#if 0 -static int ipcp_printpkt( - u_char *p, - int plen, - void (*printer) (void *, char *, ...), - void *arg -) -{ - (void)p; - (void)plen; - (void)printer; - (void)arg; - return 0; -} - -/* - * ip_active_pkt - see if this IP packet is worth bringing the link up for. - * We don't bring the link up for IP fragments or for TCP FIN packets - * with no data. - */ -#define IP_HDRLEN 20 /* bytes */ -#define IP_OFFMASK 0x1fff -#define IPPROTO_TCP 6 -#define TCP_HDRLEN 20 -#define TH_FIN 0x01 - -/* - * We use these macros because the IP header may be at an odd address, - * and some compilers might use word loads to get th_off or ip_hl. - */ - -#define net_short(x) (((x)[0] << 8) + (x)[1]) -#define get_iphl(x) (((unsigned char *)(x))[0] & 0xF) -#define get_ipoff(x) net_short((unsigned char *)(x) + 6) -#define get_ipproto(x) (((unsigned char *)(x))[9]) -#define get_tcpoff(x) (((unsigned char *)(x))[12] >> 4) -#define get_tcpflags(x) (((unsigned char *)(x))[13]) - -static int ip_active_pkt(u_char *pkt, int len) -{ - u_char *tcp; - int hlen; - - len -= PPP_HDRLEN; - pkt += PPP_HDRLEN; - if (len < IP_HDRLEN) - return 0; - if ((get_ipoff(pkt) & IP_OFFMASK) != 0) - return 0; - if (get_ipproto(pkt) != IPPROTO_TCP) - return 1; - hlen = get_iphl(pkt) * 4; - if (len < hlen + TCP_HDRLEN) - return 0; - tcp = pkt + hlen; - if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4) - return 0; - return 1; -} -#endif - -#endif /* PPP_SUPPORT */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/ipcp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/ipcp.h deleted file mode 100644 index 040a7cf4f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/ipcp.h +++ /dev/null @@ -1,126 +0,0 @@ -/***************************************************************************** -* ipcp.h - PPP IP NCP: Internet Protocol Network Control Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD codes. -*****************************************************************************/ -/* - * ipcp.h - IP Control Protocol definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id$ - */ - -#ifndef IPCP_H -#define IPCP_H - -/************************* -*** PUBLIC DEFINITIONS *** -*************************/ -/* - * Options. - */ -#define CI_ADDRS 1 /* IP Addresses */ -#define CI_COMPRESSTYPE 2 /* Compression Type */ -#define CI_ADDR 3 - -#define CI_MS_WINS1 128 /* Primary WINS value */ -#define CI_MS_DNS1 129 /* Primary DNS value */ -#define CI_MS_WINS2 130 /* Secondary WINS value */ -#define CI_MS_DNS2 131 /* Secondary DNS value */ - -#define IPCP_VJMODE_OLD 1 /* "old" mode (option # = 0x0037) */ -#define IPCP_VJMODE_RFC1172 2 /* "old-rfc"mode (option # = 0x002d) */ -#define IPCP_VJMODE_RFC1332 3 /* "new-rfc"mode (option # = 0x002d, */ - /* maxslot and slot number compression) */ - -#define IPCP_VJ_COMP 0x002d /* current value for VJ compression option*/ -#define IPCP_VJ_COMP_OLD 0x0037 /* "old" (i.e, broken) value for VJ */ - /* compression option*/ - - -/************************ -*** PUBLIC DATA TYPES *** -************************/ - -typedef struct ipcp_options { - u_int neg_addr : 1; /* Negotiate IP Address? */ - u_int old_addrs : 1; /* Use old (IP-Addresses) option? */ - u_int req_addr : 1; /* Ask peer to send IP address? */ - u_int default_route : 1; /* Assign default route through interface? */ - u_int proxy_arp : 1; /* Make proxy ARP entry for peer? */ - u_int neg_vj : 1; /* Van Jacobson Compression? */ - u_int old_vj : 1; /* use old (short) form of VJ option? */ - u_int accept_local : 1; /* accept peer's value for ouraddr */ - u_int accept_remote : 1; /* accept peer's value for hisaddr */ - u_int req_dns1 : 1; /* Ask peer to send primary DNS address? */ - u_int req_dns2 : 1; /* Ask peer to send secondary DNS address? */ - u_short vj_protocol; /* protocol value to use in VJ option */ - u_char maxslotindex; /* VJ slots - 1. */ - u_char cflag; /* VJ slot compression flag. */ - u32_t ouraddr, hisaddr; /* Addresses in NETWORK BYTE ORDER */ - u32_t dnsaddr[2]; /* Primary and secondary MS DNS entries */ - u32_t winsaddr[2]; /* Primary and secondary MS WINS entries */ -} ipcp_options; - - -/***************************** -*** PUBLIC DATA STRUCTURES *** -*****************************/ - -extern fsm ipcp_fsm[]; -extern ipcp_options ipcp_wantoptions[]; -extern ipcp_options ipcp_gotoptions[]; -extern ipcp_options ipcp_allowoptions[]; -extern ipcp_options ipcp_hisoptions[]; - -extern struct protent ipcp_protent; - - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ - - -#endif /* IPCP_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/lcp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/lcp.c deleted file mode 100644 index 6a988d6df..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/lcp.c +++ /dev/null @@ -1,1991 +0,0 @@ -/***************************************************************************** -* lcp.c - Network Link Control Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-01 Guy Lancaster , Global Election Systems Inc. -* Original. -*****************************************************************************/ - -/* - * lcp.c - PPP Link Control Protocol. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include - -#include "ppp.h" -#if PPP_SUPPORT > 0 -#include "fsm.h" -#include "chap.h" -#include "magic.h" -#include "auth.h" -#include "lcp.h" -#include "pppdebug.h" - - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ -/* - * Length of each type of configuration option (in octets) - */ -#define CILEN_VOID 2 -#define CILEN_CHAR 3 -#define CILEN_SHORT 4 /* CILEN_VOID + sizeof(short) */ -#define CILEN_CHAP 5 /* CILEN_VOID + sizeof(short) + 1 */ -#define CILEN_LONG 6 /* CILEN_VOID + sizeof(long) */ -#define CILEN_LQR 8 /* CILEN_VOID + sizeof(short) + sizeof(long) */ -#define CILEN_CBCP 3 - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -/* - * Callbacks for fsm code. (CI = Configuration Information) - */ -static void lcp_resetci (fsm*); /* Reset our CI */ -static int lcp_cilen (fsm*); /* Return length of our CI */ -static void lcp_addci (fsm*, u_char*, int*); /* Add our CI to pkt */ -static int lcp_ackci (fsm*, u_char*, int);/* Peer ack'd our CI */ -static int lcp_nakci (fsm*, u_char*, int);/* Peer nak'd our CI */ -static int lcp_rejci (fsm*, u_char*, int);/* Peer rej'd our CI */ -static int lcp_reqci (fsm*, u_char*, int*, int); /* Rcv peer CI */ -static void lcp_up (fsm*); /* We're UP */ -static void lcp_down (fsm*); /* We're DOWN */ -static void lcp_starting (fsm*); /* We need lower layer up */ -static void lcp_finished (fsm*); /* We need lower layer down */ -static int lcp_extcode (fsm*, int, u_char, u_char*, int); - -static void lcp_rprotrej (fsm*, u_char*, int); - -/* - * routines to send LCP echos to peer - */ -static void lcp_echo_lowerup (int); -static void lcp_echo_lowerdown (int); -static void LcpEchoTimeout (void*); -static void lcp_received_echo_reply (fsm*, int, u_char*, int); -static void LcpSendEchoRequest (fsm*); -static void LcpLinkFailure (fsm*); -static void LcpEchoCheck (fsm*); - -/* - * Protocol entry points. - * Some of these are called directly. - */ -static void lcp_input (int, u_char *, int); -static void lcp_protrej (int); - -#define CODENAME(x) ((x) == CONFACK ? "ACK" : \ - (x) == CONFNAK ? "NAK" : "REJ") - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ -/* global vars */ -LinkPhase lcp_phase[NUM_PPP]; /* Phase of link session (RFC 1661) */ -lcp_options lcp_wantoptions[NUM_PPP]; /* Options that we want to request */ -lcp_options lcp_gotoptions[NUM_PPP]; /* Options that peer ack'd */ -lcp_options lcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */ -lcp_options lcp_hisoptions[NUM_PPP]; /* Options that we ack'd */ -ext_accm xmit_accm[NUM_PPP]; /* extended transmit ACCM */ - - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -static fsm lcp_fsm[NUM_PPP]; /* LCP fsm structure (global)*/ -static u_int lcp_echo_interval = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */ -static u_int lcp_echo_fails = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */ -static u32_t lcp_echos_pending = 0; /* Number of outstanding echo msgs */ -static u32_t lcp_echo_number = 0; /* ID number of next echo frame */ -static u32_t lcp_echo_timer_running = 0; /* TRUE if a timer is running */ - -static u_char nak_buffer[PPP_MRU]; /* where we construct a nak packet */ - -static fsm_callbacks lcp_callbacks = { /* LCP callback routines */ - lcp_resetci, /* Reset our Configuration Information */ - lcp_cilen, /* Length of our Configuration Information */ - lcp_addci, /* Add our Configuration Information */ - lcp_ackci, /* ACK our Configuration Information */ - lcp_nakci, /* NAK our Configuration Information */ - lcp_rejci, /* Reject our Configuration Information */ - lcp_reqci, /* Request peer's Configuration Information */ - lcp_up, /* Called when fsm reaches OPENED state */ - lcp_down, /* Called when fsm leaves OPENED state */ - lcp_starting, /* Called when we want the lower layer up */ - lcp_finished, /* Called when we want the lower layer down */ - NULL, /* Called when Protocol-Reject received */ - NULL, /* Retransmission is necessary */ - lcp_extcode, /* Called to handle LCP-specific codes */ - "LCP" /* String name of protocol */ -}; - -struct protent lcp_protent = { - PPP_LCP, - lcp_init, - lcp_input, - lcp_protrej, - lcp_lowerup, - lcp_lowerdown, - lcp_open, - lcp_close, -#if 0 - lcp_printpkt, - NULL, -#endif - 1, - "LCP", -#if 0 - NULL, - NULL, - NULL -#endif -}; - -int lcp_loopbackfail = DEFLOOPBACKFAIL; - - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * lcp_init - Initialize LCP. - */ -void lcp_init(int unit) -{ - fsm *f = &lcp_fsm[unit]; - lcp_options *wo = &lcp_wantoptions[unit]; - lcp_options *ao = &lcp_allowoptions[unit]; - - f->unit = unit; - f->protocol = PPP_LCP; - f->callbacks = &lcp_callbacks; - - fsm_init(f); - - wo->passive = 0; - wo->silent = 0; - wo->restart = 0; /* Set to 1 in kernels or multi-line - * implementations */ - wo->neg_mru = 1; - wo->mru = PPP_DEFMRU; - wo->neg_asyncmap = 1; - wo->asyncmap = 0x00000000l; /* Assume don't need to escape any ctl chars. */ - wo->neg_chap = 0; /* Set to 1 on server */ - wo->neg_upap = 0; /* Set to 1 on server */ - wo->chap_mdtype = CHAP_DIGEST_MD5; - wo->neg_magicnumber = 1; - wo->neg_pcompression = 1; - wo->neg_accompression = 1; - wo->neg_lqr = 0; /* no LQR implementation yet */ - wo->neg_cbcp = 0; - - ao->neg_mru = 1; - ao->mru = PPP_MAXMRU; - ao->neg_asyncmap = 1; - ao->asyncmap = 0x00000000l; /* Assume don't need to escape any ctl chars. */ - ao->neg_chap = (CHAP_SUPPORT != 0); - ao->chap_mdtype = CHAP_DIGEST_MD5; - ao->neg_upap = (PAP_SUPPORT != 0); - ao->neg_magicnumber = 1; - ao->neg_pcompression = 1; - ao->neg_accompression = 1; - ao->neg_lqr = 0; /* no LQR implementation yet */ - ao->neg_cbcp = (CBCP_SUPPORT != 0); - - /* - * Set transmit escape for the flag and escape characters plus anything - * set for the allowable options. - */ - memset(xmit_accm[unit], 0, sizeof(xmit_accm[0])); - xmit_accm[unit][15] = 0x60; - xmit_accm[unit][0] = (u_char)(ao->asyncmap & 0xFF); - xmit_accm[unit][1] = (u_char)((ao->asyncmap >> 8) & 0xFF); - xmit_accm[unit][2] = (u_char)((ao->asyncmap >> 16) & 0xFF); - xmit_accm[unit][3] = (u_char)((ao->asyncmap >> 24) & 0xFF); - LCPDEBUG((LOG_INFO, "lcp_init: xmit_accm=%X %X %X %X\n", - xmit_accm[unit][0], - xmit_accm[unit][1], - xmit_accm[unit][2], - xmit_accm[unit][3])); - - lcp_phase[unit] = PHASE_INITIALIZE; -} - - -/* - * lcp_open - LCP is allowed to come up. - */ -void lcp_open(int unit) -{ - fsm *f = &lcp_fsm[unit]; - lcp_options *wo = &lcp_wantoptions[unit]; - - f->flags = 0; - if (wo->passive) - f->flags |= OPT_PASSIVE; - if (wo->silent) - f->flags |= OPT_SILENT; - fsm_open(f); - - lcp_phase[unit] = PHASE_ESTABLISH; -} - - -/* - * lcp_close - Take LCP down. - */ -void lcp_close(int unit, char *reason) -{ - fsm *f = &lcp_fsm[unit]; - - if (lcp_phase[unit] != PHASE_DEAD) - lcp_phase[unit] = PHASE_TERMINATE; - if (f->state == STOPPED && f->flags & (OPT_PASSIVE|OPT_SILENT)) { - /* - * This action is not strictly according to the FSM in RFC1548, - * but it does mean that the program terminates if you do an - * lcp_close() in passive/silent mode when a connection hasn't - * been established. - */ - f->state = CLOSED; - lcp_finished(f); - } - else - fsm_close(&lcp_fsm[unit], reason); -} - - -/* - * lcp_lowerup - The lower layer is up. - */ -void lcp_lowerup(int unit) -{ - lcp_options *wo = &lcp_wantoptions[unit]; - - /* - * Don't use A/C or protocol compression on transmission, - * but accept A/C and protocol compressed packets - * if we are going to ask for A/C and protocol compression. - */ - ppp_set_xaccm(unit, &xmit_accm[unit]); - ppp_send_config(unit, PPP_MRU, 0xffffffffl, 0, 0); - ppp_recv_config(unit, PPP_MRU, 0x00000000l, - wo->neg_pcompression, wo->neg_accompression); - peer_mru[unit] = PPP_MRU; - lcp_allowoptions[unit].asyncmap - = (u_long)xmit_accm[unit][0] - | ((u_long)xmit_accm[unit][1] << 8) - | ((u_long)xmit_accm[unit][2] << 16) - | ((u_long)xmit_accm[unit][3] << 24); - LCPDEBUG((LOG_INFO, "lcp_lowerup: asyncmap=%X %X %X %X\n", - xmit_accm[unit][3], - xmit_accm[unit][2], - xmit_accm[unit][1], - xmit_accm[unit][0])); - - fsm_lowerup(&lcp_fsm[unit]); -} - - -/* - * lcp_lowerdown - The lower layer is down. - */ -void lcp_lowerdown(int unit) -{ - fsm_lowerdown(&lcp_fsm[unit]); -} - -/* - * lcp_sprotrej - Send a Protocol-Reject for some protocol. - */ -void lcp_sprotrej(int unit, u_char *p, int len) -{ - /* - * Send back the protocol and the information field of the - * rejected packet. We only get here if LCP is in the OPENED state. - */ - - fsm_sdata(&lcp_fsm[unit], PROTREJ, ++lcp_fsm[unit].id, - p, len); -} - - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ -/* - * lcp_input - Input LCP packet. - */ -static void lcp_input(int unit, u_char *p, int len) -{ - fsm *f = &lcp_fsm[unit]; - - fsm_input(f, p, len); -} - - -/* - * lcp_extcode - Handle a LCP-specific code. - */ -static int lcp_extcode(fsm *f, int code, u_char id, u_char *inp, int len) -{ - u_char *magp; - - switch( code ){ - case PROTREJ: - lcp_rprotrej(f, inp, len); - break; - - case ECHOREQ: - if (f->state != OPENED) - break; - LCPDEBUG((LOG_INFO, "lcp: Echo-Request, Rcvd id %d\n", id)); - magp = inp; - PUTLONG(lcp_gotoptions[f->unit].magicnumber, magp); - fsm_sdata(f, ECHOREP, id, inp, len); - break; - - case ECHOREP: - lcp_received_echo_reply(f, id, inp, len); - break; - - case DISCREQ: - break; - - default: - return 0; - } - return 1; -} - - -/* - * lcp_rprotrej - Receive an Protocol-Reject. - * - * Figure out which protocol is rejected and inform it. - */ -static void lcp_rprotrej(fsm *f, u_char *inp, int len) -{ - int i; - struct protent *protp; - u_short prot; - - if (len < sizeof (u_short)) { - LCPDEBUG((LOG_INFO, - "lcp_rprotrej: Rcvd short Protocol-Reject packet!\n")); - return; - } - - GETSHORT(prot, inp); - - LCPDEBUG((LOG_INFO, - "lcp_rprotrej: Rcvd Protocol-Reject packet for %x!\n", - prot)); - - /* - * Protocol-Reject packets received in any state other than the LCP - * OPENED state SHOULD be silently discarded. - */ - if( f->state != OPENED ){ - LCPDEBUG((LOG_INFO, "Protocol-Reject discarded: LCP in state %d\n", - f->state)); - return; - } - - /* - * Upcall the proper Protocol-Reject routine. - */ - for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) - if (protp->protocol == prot && protp->enabled_flag) { - (*protp->protrej)(f->unit); - return; - } - - LCPDEBUG((LOG_WARNING, "Protocol-Reject for unsupported protocol 0x%x\n", - prot)); -} - - -/* - * lcp_protrej - A Protocol-Reject was received. - */ -static void lcp_protrej(int unit) -{ - (void)unit; - /* - * Can't reject LCP! - */ - LCPDEBUG((LOG_WARNING, - "lcp_protrej: Received Protocol-Reject for LCP!\n")); - fsm_protreject(&lcp_fsm[unit]); -} - - -/* - * lcp_resetci - Reset our CI. - */ -static void lcp_resetci(fsm *f) -{ - lcp_wantoptions[f->unit].magicnumber = magic(); - lcp_wantoptions[f->unit].numloops = 0; - lcp_gotoptions[f->unit] = lcp_wantoptions[f->unit]; - peer_mru[f->unit] = PPP_MRU; - auth_reset(f->unit); -} - - -/* - * lcp_cilen - Return length of our CI. - */ -static int lcp_cilen(fsm *f) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - -#define LENCIVOID(neg) ((neg) ? CILEN_VOID : 0) -#define LENCICHAP(neg) ((neg) ? CILEN_CHAP : 0) -#define LENCISHORT(neg) ((neg) ? CILEN_SHORT : 0) -#define LENCILONG(neg) ((neg) ? CILEN_LONG : 0) -#define LENCILQR(neg) ((neg) ? CILEN_LQR: 0) -#define LENCICBCP(neg) ((neg) ? CILEN_CBCP: 0) - /* - * NB: we only ask for one of CHAP and UPAP, even if we will - * accept either. - */ - return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) + - LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) + - LENCICHAP(go->neg_chap) + - LENCISHORT(!go->neg_chap && go->neg_upap) + - LENCILQR(go->neg_lqr) + - LENCICBCP(go->neg_cbcp) + - LENCILONG(go->neg_magicnumber) + - LENCIVOID(go->neg_pcompression) + - LENCIVOID(go->neg_accompression)); -} - - -/* - * lcp_addci - Add our desired CIs to a packet. - */ -static void lcp_addci(fsm *f, u_char *ucp, int *lenp) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - u_char *start_ucp = ucp; - -#define ADDCIVOID(opt, neg) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: opt=%d\n", opt)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_VOID, ucp); \ - } -#define ADDCISHORT(opt, neg, val) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: INT opt=%d %X\n", opt, val)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_SHORT, ucp); \ - PUTSHORT(val, ucp); \ - } -#define ADDCICHAP(opt, neg, val, digest) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: CHAP opt=%d %X\n", opt, val)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_CHAP, ucp); \ - PUTSHORT(val, ucp); \ - PUTCHAR(digest, ucp); \ - } -#define ADDCILONG(opt, neg, val) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: L opt=%d %lX\n", opt, val)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_LONG, ucp); \ - PUTLONG(val, ucp); \ - } -#define ADDCILQR(opt, neg, val) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: LQR opt=%d %lX\n", opt, val)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_LQR, ucp); \ - PUTSHORT(PPP_LQR, ucp); \ - PUTLONG(val, ucp); \ - } -#define ADDCICHAR(opt, neg, val) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: CHAR opt=%d %X '%z'\n", opt, val, val)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_CHAR, ucp); \ - PUTCHAR(val, ucp); \ - } - - ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru); - ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, - go->asyncmap); - ADDCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype); - ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP); - ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period); - ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT); - ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber); - ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression); - ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression); - - if (ucp - start_ucp != *lenp) { - /* this should never happen, because peer_mtu should be 1500 */ - LCPDEBUG((LOG_ERR, "Bug in lcp_addci: wrong length\n")); - } -} - - -/* - * lcp_ackci - Ack our CIs. - * This should not modify any state if the Ack is bad. - * - * Returns: - * 0 - Ack was bad. - * 1 - Ack was good. - */ -static int lcp_ackci(fsm *f, u_char *p, int len) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - u_char cilen, citype, cichar; - u_short cishort; - u32_t cilong; - - /* - * CIs must be in exactly the same order that we sent. - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ -#define ACKCIVOID(opt, neg) \ - if (neg) { \ - if ((len -= CILEN_VOID) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_VOID || \ - citype != opt) \ - goto bad; \ - } -#define ACKCISHORT(opt, neg, val) \ - if (neg) { \ - if ((len -= CILEN_SHORT) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_SHORT || \ - citype != opt) \ - goto bad; \ - GETSHORT(cishort, p); \ - if (cishort != val) \ - goto bad; \ - } -#define ACKCICHAR(opt, neg, val) \ - if (neg) { \ - if ((len -= CILEN_CHAR) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_CHAR || \ - citype != opt) \ - goto bad; \ - GETCHAR(cichar, p); \ - if (cichar != val) \ - goto bad; \ - } -#define ACKCICHAP(opt, neg, val, digest) \ - if (neg) { \ - if ((len -= CILEN_CHAP) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_CHAP || \ - citype != opt) \ - goto bad; \ - GETSHORT(cishort, p); \ - if (cishort != val) \ - goto bad; \ - GETCHAR(cichar, p); \ - if (cichar != digest) \ - goto bad; \ - } -#define ACKCILONG(opt, neg, val) \ - if (neg) { \ - if ((len -= CILEN_LONG) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_LONG || \ - citype != opt) \ - goto bad; \ - GETLONG(cilong, p); \ - if (cilong != val) \ - goto bad; \ - } -#define ACKCILQR(opt, neg, val) \ - if (neg) { \ - if ((len -= CILEN_LQR) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_LQR || \ - citype != opt) \ - goto bad; \ - GETSHORT(cishort, p); \ - if (cishort != PPP_LQR) \ - goto bad; \ - GETLONG(cilong, p); \ - if (cilong != val) \ - goto bad; \ - } - - ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru); - ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, - go->asyncmap); - ACKCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype); - ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP); - ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period); - ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT); - ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber); - ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression); - ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression); - - /* - * If there are any remaining CIs, then this packet is bad. - */ - if (len != 0) - goto bad; - LCPDEBUG((LOG_INFO, "lcp_acki: Ack\n")); - return (1); -bad: - LCPDEBUG((LOG_WARNING, "lcp_acki: received bad Ack!\n")); - return (0); -} - - -/* - * lcp_nakci - Peer has sent a NAK for some of our CIs. - * This should not modify any state if the Nak is bad - * or if LCP is in the OPENED state. - * - * Returns: - * 0 - Nak was bad. - * 1 - Nak was good. - */ -static int lcp_nakci(fsm *f, u_char *p, int len) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - lcp_options *wo = &lcp_wantoptions[f->unit]; - u_char citype, cichar, *next; - u_short cishort; - u32_t cilong; - lcp_options no; /* options we've seen Naks for */ - lcp_options try; /* options to request next time */ - int looped_back = 0; - int cilen; - - BZERO(&no, sizeof(no)); - try = *go; - - /* - * Any Nak'd CIs must be in exactly the same order that we sent. - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ -#define NAKCIVOID(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_VOID && \ - p[1] == CILEN_VOID && \ - p[0] == opt) { \ - len -= CILEN_VOID; \ - INCPTR(CILEN_VOID, p); \ - no.neg = 1; \ - code \ - } -#define NAKCICHAP(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_CHAP && \ - p[1] == CILEN_CHAP && \ - p[0] == opt) { \ - len -= CILEN_CHAP; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - GETCHAR(cichar, p); \ - no.neg = 1; \ - code \ - } -#define NAKCICHAR(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_CHAR && \ - p[1] == CILEN_CHAR && \ - p[0] == opt) { \ - len -= CILEN_CHAR; \ - INCPTR(2, p); \ - GETCHAR(cichar, p); \ - no.neg = 1; \ - code \ - } -#define NAKCISHORT(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_SHORT && \ - p[1] == CILEN_SHORT && \ - p[0] == opt) { \ - len -= CILEN_SHORT; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - no.neg = 1; \ - code \ - } -#define NAKCILONG(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_LONG && \ - p[1] == CILEN_LONG && \ - p[0] == opt) { \ - len -= CILEN_LONG; \ - INCPTR(2, p); \ - GETLONG(cilong, p); \ - no.neg = 1; \ - code \ - } -#define NAKCILQR(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_LQR && \ - p[1] == CILEN_LQR && \ - p[0] == opt) { \ - len -= CILEN_LQR; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - GETLONG(cilong, p); \ - no.neg = 1; \ - code \ - } - - /* - * We don't care if they want to send us smaller packets than - * we want. Therefore, accept any MRU less than what we asked for, - * but then ignore the new value when setting the MRU in the kernel. - * If they send us a bigger MRU than what we asked, accept it, up to - * the limit of the default MRU we'd get if we didn't negotiate. - */ - if (go->neg_mru && go->mru != PPP_DEFMRU) { - NAKCISHORT(CI_MRU, neg_mru, - if (cishort <= wo->mru || cishort < PPP_DEFMRU) - try.mru = cishort; - ); - } - - /* - * Add any characters they want to our (receive-side) asyncmap. - */ - if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) { - NAKCILONG(CI_ASYNCMAP, neg_asyncmap, - try.asyncmap = go->asyncmap | cilong; - ); - } - - /* - * If they've nak'd our authentication-protocol, check whether - * they are proposing a different protocol, or a different - * hash algorithm for CHAP. - */ - if ((go->neg_chap || go->neg_upap) - && len >= CILEN_SHORT - && p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) { - cilen = p[1]; - len -= cilen; - no.neg_chap = go->neg_chap; - no.neg_upap = go->neg_upap; - INCPTR(2, p); - GETSHORT(cishort, p); - if (cishort == PPP_PAP && cilen == CILEN_SHORT) { - /* - * If we were asking for CHAP, they obviously don't want to do it. - * If we weren't asking for CHAP, then we were asking for PAP, - * in which case this Nak is bad. - */ - if (!go->neg_chap) - goto bad; - try.neg_chap = 0; - - } else if (cishort == PPP_CHAP && cilen == CILEN_CHAP) { - GETCHAR(cichar, p); - if (go->neg_chap) { - /* - * We were asking for CHAP/MD5; they must want a different - * algorithm. If they can't do MD5, we'll have to stop - * asking for CHAP. - */ - if (cichar != go->chap_mdtype) - try.neg_chap = 0; - } else { - /* - * Stop asking for PAP if we were asking for it. - */ - try.neg_upap = 0; - } - - } else { - /* - * We don't recognize what they're suggesting. - * Stop asking for what we were asking for. - */ - if (go->neg_chap) - try.neg_chap = 0; - else - try.neg_upap = 0; - p += cilen - CILEN_SHORT; - } - } - - /* - * If they can't cope with our link quality protocol, we'll have - * to stop asking for LQR. We haven't got any other protocol. - * If they Nak the reporting period, take their value XXX ? - */ - NAKCILQR(CI_QUALITY, neg_lqr, - if (cishort != PPP_LQR) - try.neg_lqr = 0; - else - try.lqr_period = cilong; - ); - - /* - * Only implementing CBCP...not the rest of the callback options - */ - NAKCICHAR(CI_CALLBACK, neg_cbcp, - try.neg_cbcp = 0; - ); - - /* - * Check for a looped-back line. - */ - NAKCILONG(CI_MAGICNUMBER, neg_magicnumber, - try.magicnumber = magic(); - looped_back = 1; - ); - - /* - * Peer shouldn't send Nak for protocol compression or - * address/control compression requests; they should send - * a Reject instead. If they send a Nak, treat it as a Reject. - */ - NAKCIVOID(CI_PCOMPRESSION, neg_pcompression, - try.neg_pcompression = 0; - ); - NAKCIVOID(CI_ACCOMPRESSION, neg_accompression, - try.neg_accompression = 0; - ); - - /* - * There may be remaining CIs, if the peer is requesting negotiation - * on an option that we didn't include in our request packet. - * If we see an option that we requested, or one we've already seen - * in this packet, then this packet is bad. - * If we wanted to respond by starting to negotiate on the requested - * option(s), we could, but we don't, because except for the - * authentication type and quality protocol, if we are not negotiating - * an option, it is because we were told not to. - * For the authentication type, the Nak from the peer means - * `let me authenticate myself with you' which is a bit pointless. - * For the quality protocol, the Nak means `ask me to send you quality - * reports', but if we didn't ask for them, we don't want them. - * An option we don't recognize represents the peer asking to - * negotiate some option we don't support, so ignore it. - */ - while (len > CILEN_VOID) { - GETCHAR(citype, p); - GETCHAR(cilen, p); - if (cilen < CILEN_VOID || (len -= cilen) < 0) - goto bad; - next = p + cilen - 2; - - switch (citype) { - case CI_MRU: - if ((go->neg_mru && go->mru != PPP_DEFMRU) - || no.neg_mru || cilen != CILEN_SHORT) - goto bad; - GETSHORT(cishort, p); - if (cishort < PPP_DEFMRU) - try.mru = cishort; - break; - case CI_ASYNCMAP: - if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) - || no.neg_asyncmap || cilen != CILEN_LONG) - goto bad; - break; - case CI_AUTHTYPE: - if (go->neg_chap || no.neg_chap || go->neg_upap || no.neg_upap) - goto bad; - break; - case CI_MAGICNUMBER: - if (go->neg_magicnumber || no.neg_magicnumber || - cilen != CILEN_LONG) - goto bad; - break; - case CI_PCOMPRESSION: - if (go->neg_pcompression || no.neg_pcompression - || cilen != CILEN_VOID) - goto bad; - break; - case CI_ACCOMPRESSION: - if (go->neg_accompression || no.neg_accompression - || cilen != CILEN_VOID) - goto bad; - break; - case CI_QUALITY: - if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR) - goto bad; - break; - } - p = next; - } - - /* If there is still anything left, this packet is bad. */ - if (len != 0) - goto bad; - - /* - * OK, the Nak is good. Now we can update state. - */ - if (f->state != OPENED) { - if (looped_back) { - if (++try.numloops >= lcp_loopbackfail) { - LCPDEBUG((LOG_NOTICE, "Serial line is looped back.\n")); - lcp_close(f->unit, "Loopback detected"); - } - } - else - try.numloops = 0; - *go = try; - } - - return 1; - -bad: - LCPDEBUG((LOG_WARNING, "lcp_nakci: received bad Nak!\n")); - return 0; -} - - -/* - * lcp_rejci - Peer has Rejected some of our CIs. - * This should not modify any state if the Reject is bad - * or if LCP is in the OPENED state. - * - * Returns: - * 0 - Reject was bad. - * 1 - Reject was good. - */ -static int lcp_rejci(fsm *f, u_char *p, int len) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - u_char cichar; - u_short cishort; - u32_t cilong; - lcp_options try; /* options to request next time */ - - try = *go; - - /* - * Any Rejected CIs must be in exactly the same order that we sent. - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ -#define REJCIVOID(opt, neg) \ - if (go->neg && \ - len >= CILEN_VOID && \ - p[1] == CILEN_VOID && \ - p[0] == opt) { \ - len -= CILEN_VOID; \ - INCPTR(CILEN_VOID, p); \ - try.neg = 0; \ - LCPDEBUG((LOG_INFO, "lcp_rejci: void opt %d rejected\n", opt)); \ - } -#define REJCISHORT(opt, neg, val) \ - if (go->neg && \ - len >= CILEN_SHORT && \ - p[1] == CILEN_SHORT && \ - p[0] == opt) { \ - len -= CILEN_SHORT; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - /* Check rejected value. */ \ - if (cishort != val) \ - goto bad; \ - try.neg = 0; \ - LCPDEBUG((LOG_INFO,"lcp_rejci: short opt %d rejected\n", opt)); \ - } -#define REJCICHAP(opt, neg, val, digest) \ - if (go->neg && \ - len >= CILEN_CHAP && \ - p[1] == CILEN_CHAP && \ - p[0] == opt) { \ - len -= CILEN_CHAP; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - GETCHAR(cichar, p); \ - /* Check rejected value. */ \ - if (cishort != val || cichar != digest) \ - goto bad; \ - try.neg = 0; \ - try.neg_upap = 0; \ - LCPDEBUG((LOG_INFO,"lcp_rejci: chap opt %d rejected\n", opt)); \ - } -#define REJCILONG(opt, neg, val) \ - if (go->neg && \ - len >= CILEN_LONG && \ - p[1] == CILEN_LONG && \ - p[0] == opt) { \ - len -= CILEN_LONG; \ - INCPTR(2, p); \ - GETLONG(cilong, p); \ - /* Check rejected value. */ \ - if (cilong != val) \ - goto bad; \ - try.neg = 0; \ - LCPDEBUG((LOG_INFO,"lcp_rejci: long opt %d rejected\n", opt)); \ - } -#define REJCILQR(opt, neg, val) \ - if (go->neg && \ - len >= CILEN_LQR && \ - p[1] == CILEN_LQR && \ - p[0] == opt) { \ - len -= CILEN_LQR; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - GETLONG(cilong, p); \ - /* Check rejected value. */ \ - if (cishort != PPP_LQR || cilong != val) \ - goto bad; \ - try.neg = 0; \ - LCPDEBUG((LOG_INFO,"lcp_rejci: LQR opt %d rejected\n", opt)); \ - } -#define REJCICBCP(opt, neg, val) \ - if (go->neg && \ - len >= CILEN_CBCP && \ - p[1] == CILEN_CBCP && \ - p[0] == opt) { \ - len -= CILEN_CBCP; \ - INCPTR(2, p); \ - GETCHAR(cichar, p); \ - /* Check rejected value. */ \ - if (cichar != val) \ - goto bad; \ - try.neg = 0; \ - LCPDEBUG((LOG_INFO,"lcp_rejci: Callback opt %d rejected\n", opt)); \ - } - - REJCISHORT(CI_MRU, neg_mru, go->mru); - REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap); - REJCICHAP(CI_AUTHTYPE, neg_chap, PPP_CHAP, go->chap_mdtype); - if (!go->neg_chap) { - REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP); - } - REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period); - REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT); - REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber); - REJCIVOID(CI_PCOMPRESSION, neg_pcompression); - REJCIVOID(CI_ACCOMPRESSION, neg_accompression); - - /* - * If there are any remaining CIs, then this packet is bad. - */ - if (len != 0) - goto bad; - /* - * Now we can update state. - */ - if (f->state != OPENED) - *go = try; - return 1; - -bad: - LCPDEBUG((LOG_WARNING, "lcp_rejci: received bad Reject!\n")); - return 0; -} - - -/* - * lcp_reqci - Check the peer's requested CIs and send appropriate response. - * - * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified - * appropriately. If reject_if_disagree is non-zero, doesn't return - * CONFNAK; returns CONFREJ if it can't return CONFACK. - */ -static int lcp_reqci(fsm *f, - u_char *inp, /* Requested CIs */ - int *lenp, /* Length of requested CIs */ - int reject_if_disagree) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - lcp_options *ho = &lcp_hisoptions[f->unit]; - lcp_options *ao = &lcp_allowoptions[f->unit]; - u_char *cip, *next; /* Pointer to current and next CIs */ - int cilen, citype, cichar; /* Parsed len, type, char value */ - u_short cishort; /* Parsed short value */ - u32_t cilong; /* Parse long value */ - int rc = CONFACK; /* Final packet return code */ - int orc; /* Individual option return code */ - u_char *p; /* Pointer to next char to parse */ - u_char *rejp; /* Pointer to next char in reject frame */ - u_char *nakp; /* Pointer to next char in Nak frame */ - int l = *lenp; /* Length left */ -#if TRACELCP > 0 - char traceBuf[80]; - int traceNdx = 0; -#endif - - /* - * Reset all his options. - */ - BZERO(ho, sizeof(*ho)); - - /* - * Process all his options. - */ - next = inp; - nakp = nak_buffer; - rejp = inp; - while (l) { - orc = CONFACK; /* Assume success */ - cip = p = next; /* Remember begining of CI */ - if (l < 2 || /* Not enough data for CI header or */ - p[1] < 2 || /* CI length too small or */ - p[1] > l) { /* CI length too big? */ - LCPDEBUG((LOG_WARNING, "lcp_reqci: bad CI length!\n")); - orc = CONFREJ; /* Reject bad CI */ - cilen = l; /* Reject till end of packet */ - l = 0; /* Don't loop again */ - citype = 0; - goto endswitch; - } - GETCHAR(citype, p); /* Parse CI type */ - GETCHAR(cilen, p); /* Parse CI length */ - l -= cilen; /* Adjust remaining length */ - next += cilen; /* Step to next CI */ - - switch (citype) { /* Check CI type */ - case CI_MRU: - if (!ao->neg_mru) { /* Allow option? */ - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - not allowed\n")); - orc = CONFREJ; /* Reject CI */ - break; - } else if (cilen != CILEN_SHORT) { /* Check CI length */ - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - bad length\n")); - orc = CONFREJ; /* Reject CI */ - break; - } - GETSHORT(cishort, p); /* Parse MRU */ - - /* - * He must be able to receive at least our minimum. - * No need to check a maximum. If he sends a large number, - * we'll just ignore it. - */ - if (cishort < PPP_MINMRU) { - LCPDEBUG((LOG_INFO, "lcp_reqci: Nak - MRU too small\n")); - orc = CONFNAK; /* Nak CI */ - PUTCHAR(CI_MRU, nakp); - PUTCHAR(CILEN_SHORT, nakp); - PUTSHORT(PPP_MINMRU, nakp); /* Give him a hint */ - break; - } - ho->neg_mru = 1; /* Remember he sent MRU */ - ho->mru = cishort; /* And remember value */ -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MRU %d", cishort); - traceNdx = strlen(traceBuf); -#endif - break; - - case CI_ASYNCMAP: - if (!ao->neg_asyncmap) { - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP not allowed\n")); - orc = CONFREJ; - break; - } else if (cilen != CILEN_LONG) { - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP bad length\n")); - orc = CONFREJ; - break; - } - GETLONG(cilong, p); - - /* - * Asyncmap must have set at least the bits - * which are set in lcp_allowoptions[unit].asyncmap. - */ - if ((ao->asyncmap & ~cilong) != 0) { - LCPDEBUG((LOG_INFO, "lcp_reqci: Nak ASYNCMAP %lX missing %lX\n", - cilong, ao->asyncmap)); - orc = CONFNAK; - PUTCHAR(CI_ASYNCMAP, nakp); - PUTCHAR(CILEN_LONG, nakp); - PUTLONG(ao->asyncmap | cilong, nakp); - break; - } - ho->neg_asyncmap = 1; - ho->asyncmap = cilong; -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ASYNCMAP=%lX", cilong); - traceNdx = strlen(traceBuf); -#endif - break; - - case CI_AUTHTYPE: - if (cilen < CILEN_SHORT) { - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE missing arg\n")); - orc = CONFREJ; - break; - } else if (!(ao->neg_upap || ao->neg_chap)) { - /* - * Reject the option if we're not willing to authenticate. - */ - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE not allowed\n")); - orc = CONFREJ; - break; - } - GETSHORT(cishort, p); - - /* - * Authtype must be UPAP or CHAP. - * - * Note: if both ao->neg_upap and ao->neg_chap are set, - * and the peer sends a Configure-Request with two - * authenticate-protocol requests, one for CHAP and one - * for UPAP, then we will reject the second request. - * Whether we end up doing CHAP or UPAP depends then on - * the ordering of the CIs in the peer's Configure-Request. - */ - - if (cishort == PPP_PAP) { - if (ho->neg_chap) { /* we've already accepted CHAP */ - LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP already accepted\n")); - orc = CONFREJ; - break; - } else if (cilen != CILEN_SHORT) { - LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP bad len\n")); - orc = CONFREJ; - break; - } - if (!ao->neg_upap) { /* we don't want to do PAP */ - LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE PAP not allowed\n")); - orc = CONFNAK; /* NAK it and suggest CHAP */ - PUTCHAR(CI_AUTHTYPE, nakp); - PUTCHAR(CILEN_CHAP, nakp); - PUTSHORT(PPP_CHAP, nakp); - PUTCHAR(ao->chap_mdtype, nakp); - break; - } - ho->neg_upap = 1; -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PAP (%X)", cishort); - traceNdx = strlen(traceBuf); -#endif - break; - } - if (cishort == PPP_CHAP) { - if (ho->neg_upap) { /* we've already accepted PAP */ - LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP accepted PAP\n")); - orc = CONFREJ; - break; - } else if (cilen != CILEN_CHAP) { - LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP bad len\n")); - orc = CONFREJ; - break; - } - if (!ao->neg_chap) { /* we don't want to do CHAP */ - LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP not allowed\n")); - orc = CONFNAK; /* NAK it and suggest PAP */ - PUTCHAR(CI_AUTHTYPE, nakp); - PUTCHAR(CILEN_SHORT, nakp); - PUTSHORT(PPP_PAP, nakp); - break; - } - GETCHAR(cichar, p); /* get digest type*/ - if (cichar != CHAP_DIGEST_MD5 -#ifdef CHAPMS - && cichar != CHAP_MICROSOFT -#endif - ) { - LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP digest=%d\n", cichar)); - orc = CONFNAK; - PUTCHAR(CI_AUTHTYPE, nakp); - PUTCHAR(CILEN_CHAP, nakp); - PUTSHORT(PPP_CHAP, nakp); - PUTCHAR(ao->chap_mdtype, nakp); - break; - } -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CHAP %X,%d", cishort, cichar); - traceNdx = strlen(traceBuf); -#endif - ho->chap_mdtype = cichar; /* save md type */ - ho->neg_chap = 1; - break; - } - - /* - * We don't recognize the protocol they're asking for. - * Nak it with something we're willing to do. - * (At this point we know ao->neg_upap || ao->neg_chap.) - */ - orc = CONFNAK; - PUTCHAR(CI_AUTHTYPE, nakp); - if (ao->neg_chap) { - LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req CHAP\n", cishort)); - PUTCHAR(CILEN_CHAP, nakp); - PUTSHORT(PPP_CHAP, nakp); - PUTCHAR(ao->chap_mdtype, nakp); - } - else { - LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req PAP\n", cishort)); - PUTCHAR(CILEN_SHORT, nakp); - PUTSHORT(PPP_PAP, nakp); - } - break; - - case CI_QUALITY: - GETSHORT(cishort, p); - GETLONG(cilong, p); -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " QUALITY (%x %x)", cishort, (unsigned int) cilong); - traceNdx = strlen(traceBuf); -#endif - - if (!ao->neg_lqr || - cilen != CILEN_LQR) { - orc = CONFREJ; - break; - } - - /* - * Check the protocol and the reporting period. - * XXX When should we Nak this, and what with? - */ - if (cishort != PPP_LQR) { - orc = CONFNAK; - PUTCHAR(CI_QUALITY, nakp); - PUTCHAR(CILEN_LQR, nakp); - PUTSHORT(PPP_LQR, nakp); - PUTLONG(ao->lqr_period, nakp); - break; - } - break; - - case CI_MAGICNUMBER: - if (!(ao->neg_magicnumber || go->neg_magicnumber) || - cilen != CILEN_LONG) { - orc = CONFREJ; - break; - } - GETLONG(cilong, p); -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MAGICNUMBER (%lX)", cilong); - traceNdx = strlen(traceBuf); -#endif - - /* - * He must have a different magic number. - */ - if (go->neg_magicnumber && - cilong == go->magicnumber) { - cilong = magic(); /* Don't put magic() inside macro! */ - orc = CONFNAK; - PUTCHAR(CI_MAGICNUMBER, nakp); - PUTCHAR(CILEN_LONG, nakp); - PUTLONG(cilong, nakp); - break; - } - ho->neg_magicnumber = 1; - ho->magicnumber = cilong; - break; - - - case CI_PCOMPRESSION: -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PCOMPRESSION"); - traceNdx = strlen(traceBuf); -#endif - if (!ao->neg_pcompression || - cilen != CILEN_VOID) { - orc = CONFREJ; - break; - } - ho->neg_pcompression = 1; - break; - - case CI_ACCOMPRESSION: -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ACCOMPRESSION"); - traceNdx = strlen(traceBuf); -#endif - if (!ao->neg_accompression || - cilen != CILEN_VOID) { - orc = CONFREJ; - break; - } - ho->neg_accompression = 1; - break; - - case CI_MRRU: -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_MRRU"); - traceNdx = strlen(traceBuf); -#endif - orc = CONFREJ; - break; - - case CI_SSNHF: -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_SSNHF"); - traceNdx = strlen(traceBuf); -#endif - orc = CONFREJ; - break; - - case CI_EPDISC: -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_EPDISC"); - traceNdx = strlen(traceBuf); -#endif - orc = CONFREJ; - break; - - default: -#if TRACELCP - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " unknown %d", citype); - traceNdx = strlen(traceBuf); -#endif - orc = CONFREJ; - break; - } - - endswitch: -#if TRACELCP - if (traceNdx >= 80 - 32) { - LCPDEBUG((LOG_INFO, "lcp_reqci: rcvd%s\n", traceBuf)); - traceNdx = 0; - } -#endif - if (orc == CONFACK && /* Good CI */ - rc != CONFACK) /* but prior CI wasnt? */ - continue; /* Don't send this one */ - - if (orc == CONFNAK) { /* Nak this CI? */ - if (reject_if_disagree /* Getting fed up with sending NAKs? */ - && citype != CI_MAGICNUMBER) { - orc = CONFREJ; /* Get tough if so */ - } - else { - if (rc == CONFREJ) /* Rejecting prior CI? */ - continue; /* Don't send this one */ - rc = CONFNAK; - } - } - if (orc == CONFREJ) { /* Reject this CI */ - rc = CONFREJ; - if (cip != rejp) /* Need to move rejected CI? */ - BCOPY(cip, rejp, cilen); /* Move it */ - INCPTR(cilen, rejp); /* Update output pointer */ - } - } - - /* - * If we wanted to send additional NAKs (for unsent CIs), the - * code would go here. The extra NAKs would go at *nakp. - * At present there are no cases where we want to ask the - * peer to negotiate an option. - */ - - switch (rc) { - case CONFACK: - *lenp = (int)(next - inp); - break; - case CONFNAK: - /* - * Copy the Nak'd options from the nak_buffer to the caller's buffer. - */ - *lenp = (int)(nakp - nak_buffer); - BCOPY(nak_buffer, inp, *lenp); - break; - case CONFREJ: - *lenp = (int)(rejp - inp); - break; - } - -#if TRACELCP > 0 - if (traceNdx > 0) { - LCPDEBUG((LOG_INFO, "lcp_reqci: %s\n", traceBuf)); - } -#endif - LCPDEBUG((LOG_INFO, "lcp_reqci: returning CONF%s.\n", CODENAME(rc))); - return (rc); /* Return final code */ -} - - -/* - * lcp_up - LCP has come UP. - */ -static void lcp_up(fsm *f) -{ - lcp_options *wo = &lcp_wantoptions[f->unit]; - lcp_options *ho = &lcp_hisoptions[f->unit]; - lcp_options *go = &lcp_gotoptions[f->unit]; - lcp_options *ao = &lcp_allowoptions[f->unit]; - - if (!go->neg_magicnumber) - go->magicnumber = 0; - if (!ho->neg_magicnumber) - ho->magicnumber = 0; - - /* - * Set our MTU to the smaller of the MTU we wanted and - * the MRU our peer wanted. If we negotiated an MRU, - * set our MRU to the larger of value we wanted and - * the value we got in the negotiation. - */ - ppp_send_config(f->unit, LWIP_MIN(ao->mru, (ho->neg_mru? ho->mru: PPP_MRU)), - (ho->neg_asyncmap? ho->asyncmap: 0xffffffffl), - ho->neg_pcompression, ho->neg_accompression); - /* - * If the asyncmap hasn't been negotiated, we really should - * set the receive asyncmap to ffffffff, but we set it to 0 - * for backwards contemptibility. - */ - ppp_recv_config(f->unit, (go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU), - (go->neg_asyncmap? go->asyncmap: 0x00000000), - go->neg_pcompression, go->neg_accompression); - - if (ho->neg_mru) - peer_mru[f->unit] = ho->mru; - - lcp_echo_lowerup(f->unit); /* Enable echo messages */ - - link_established(f->unit); -} - - -/* - * lcp_down - LCP has gone DOWN. - * - * Alert other protocols. - */ -static void lcp_down(fsm *f) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - - lcp_echo_lowerdown(f->unit); - - link_down(f->unit); - - ppp_send_config(f->unit, PPP_MRU, 0xffffffffl, 0, 0); - ppp_recv_config(f->unit, PPP_MRU, - (go->neg_asyncmap? go->asyncmap: 0x00000000), - go->neg_pcompression, go->neg_accompression); - peer_mru[f->unit] = PPP_MRU; -} - - -/* - * lcp_starting - LCP needs the lower layer up. - */ -static void lcp_starting(fsm *f) -{ - link_required(f->unit); -} - - -/* - * lcp_finished - LCP has finished with the lower layer. - */ -static void lcp_finished(fsm *f) -{ - link_terminated(f->unit); -} - - -#if 0 -/* - * print_string - print a readable representation of a string using - * printer. - */ -static void print_string( - char *p, - int len, - void (*printer) (void *, char *, ...), - void *arg -) -{ - int c; - - printer(arg, "\""); - for (; len > 0; --len) { - c = *p++; - if (' ' <= c && c <= '~') { - if (c == '\\' || c == '"') - printer(arg, "\\"); - printer(arg, "%c", c); - } else { - switch (c) { - case '\n': - printer(arg, "\\n"); - break; - case '\r': - printer(arg, "\\r"); - break; - case '\t': - printer(arg, "\\t"); - break; - default: - printer(arg, "\\%.3o", c); - } - } - } - printer(arg, "\""); -} - - -/* - * lcp_printpkt - print the contents of an LCP packet. - */ -static char *lcp_codenames[] = { - "ConfReq", "ConfAck", "ConfNak", "ConfRej", - "TermReq", "TermAck", "CodeRej", "ProtRej", - "EchoReq", "EchoRep", "DiscReq" -}; - -static int lcp_printpkt( - u_char *p, - int plen, - void (*printer) (void *, char *, ...), - void *arg -) -{ - int code, id, len, olen; - u_char *pstart, *optend; - u_short cishort; - u32_t cilong; - - if (plen < HEADERLEN) - return 0; - pstart = p; - GETCHAR(code, p); - GETCHAR(id, p); - GETSHORT(len, p); - if (len < HEADERLEN || len > plen) - return 0; - - if (code >= 1 && code <= sizeof(lcp_codenames) / sizeof(char *)) - printer(arg, " %s", lcp_codenames[code-1]); - else - printer(arg, " code=0x%x", code); - printer(arg, " id=0x%x", id); - len -= HEADERLEN; - switch (code) { - case CONFREQ: - case CONFACK: - case CONFNAK: - case CONFREJ: - /* print option list */ - while (len >= 2) { - GETCHAR(code, p); - GETCHAR(olen, p); - p -= 2; - if (olen < 2 || olen > len) { - break; - } - printer(arg, " <"); - len -= olen; - optend = p + olen; - switch (code) { - case CI_MRU: - if (olen == CILEN_SHORT) { - p += 2; - GETSHORT(cishort, p); - printer(arg, "mru %d", cishort); - } - break; - case CI_ASYNCMAP: - if (olen == CILEN_LONG) { - p += 2; - GETLONG(cilong, p); - printer(arg, "asyncmap 0x%lx", cilong); - } - break; - case CI_AUTHTYPE: - if (olen >= CILEN_SHORT) { - p += 2; - printer(arg, "auth "); - GETSHORT(cishort, p); - switch (cishort) { - case PPP_PAP: - printer(arg, "pap"); - break; - case PPP_CHAP: - printer(arg, "chap"); - break; - default: - printer(arg, "0x%x", cishort); - } - } - break; - case CI_QUALITY: - if (olen >= CILEN_SHORT) { - p += 2; - printer(arg, "quality "); - GETSHORT(cishort, p); - switch (cishort) { - case PPP_LQR: - printer(arg, "lqr"); - break; - default: - printer(arg, "0x%x", cishort); - } - } - break; - case CI_CALLBACK: - if (olen >= CILEN_CHAR) { - p += 2; - printer(arg, "callback "); - GETSHORT(cishort, p); - switch (cishort) { - case CBCP_OPT: - printer(arg, "CBCP"); - break; - default: - printer(arg, "0x%x", cishort); - } - } - break; - case CI_MAGICNUMBER: - if (olen == CILEN_LONG) { - p += 2; - GETLONG(cilong, p); - printer(arg, "magic 0x%x", cilong); - } - break; - case CI_PCOMPRESSION: - if (olen == CILEN_VOID) { - p += 2; - printer(arg, "pcomp"); - } - break; - case CI_ACCOMPRESSION: - if (olen == CILEN_VOID) { - p += 2; - printer(arg, "accomp"); - } - break; - } - while (p < optend) { - GETCHAR(code, p); - printer(arg, " %.2x", code); - } - printer(arg, ">"); - } - break; - - case TERMACK: - case TERMREQ: - if (len > 0 && *p >= ' ' && *p < 0x7f) { - printer(arg, " "); - print_string((char*)p, len, printer, arg); - p += len; - len = 0; - } - break; - - case ECHOREQ: - case ECHOREP: - case DISCREQ: - if (len >= 4) { - GETLONG(cilong, p); - printer(arg, " magic=0x%x", cilong); - p += 4; - len -= 4; - } - break; - } - - /* print the rest of the bytes in the packet */ - for (; len > 0; --len) { - GETCHAR(code, p); - printer(arg, " %.2x", code); - } - - return (int)(p - pstart); -} -#endif - -/* - * Time to shut down the link because there is nothing out there. - */ - -static void LcpLinkFailure (fsm *f) -{ - if (f->state == OPENED) { - LCPDEBUG((LOG_INFO, "No response to %d echo-requests\n", lcp_echos_pending)); - LCPDEBUG((LOG_NOTICE, "Serial link appears to be disconnected.\n")); - lcp_close(f->unit, "Peer not responding"); - } -} - -/* - * Timer expired for the LCP echo requests from this process. - */ - -static void LcpEchoCheck (fsm *f) -{ - LcpSendEchoRequest (f); - - /* - * Start the timer for the next interval. - */ - LWIP_ASSERT("lcp_echo_timer_running == 0", lcp_echo_timer_running == 0); - - TIMEOUT (LcpEchoTimeout, f, lcp_echo_interval); - lcp_echo_timer_running = 1; -} - -/* - * LcpEchoTimeout - Timer expired on the LCP echo - */ - -static void LcpEchoTimeout (void *arg) -{ - if (lcp_echo_timer_running != 0) { - lcp_echo_timer_running = 0; - LcpEchoCheck ((fsm *) arg); - } -} - -/* - * LcpEchoReply - LCP has received a reply to the echo - */ -static void lcp_received_echo_reply (fsm *f, int id, u_char *inp, int len) -{ - u32_t magic; - - (void)id; - - /* Check the magic number - don't count replies from ourselves. */ - if (len < 4) { - LCPDEBUG((LOG_WARNING, "lcp: received short Echo-Reply, length %d\n", len)); - return; - } - GETLONG(magic, inp); - if (lcp_gotoptions[f->unit].neg_magicnumber - && magic == lcp_gotoptions[f->unit].magicnumber) { - LCPDEBUG((LOG_WARNING, "appear to have received our own echo-reply!\n")); - return; - } - - /* Reset the number of outstanding echo frames */ - lcp_echos_pending = 0; -} - -/* - * LcpSendEchoRequest - Send an echo request frame to the peer - */ - -static void LcpSendEchoRequest (fsm *f) -{ - u32_t lcp_magic; - u_char pkt[4], *pktp; - - /* - * Detect the failure of the peer at this point. - */ - if (lcp_echo_fails != 0) { - if (lcp_echos_pending++ >= lcp_echo_fails) { - LcpLinkFailure(f); - lcp_echos_pending = 0; - } - } - - /* - * Make and send the echo request frame. - */ - if (f->state == OPENED) { - lcp_magic = lcp_gotoptions[f->unit].magicnumber; - pktp = pkt; - PUTLONG(lcp_magic, pktp); - fsm_sdata(f, ECHOREQ, (u_char)(lcp_echo_number++ & 0xFF), pkt, (int)(pktp - pkt)); - } -} - -/* - * lcp_echo_lowerup - Start the timer for the LCP frame - */ - -static void lcp_echo_lowerup (int unit) -{ - fsm *f = &lcp_fsm[unit]; - - /* Clear the parameters for generating echo frames */ - lcp_echos_pending = 0; - lcp_echo_number = 0; - lcp_echo_timer_running = 0; - - /* If a timeout interval is specified then start the timer */ - if (lcp_echo_interval != 0) - LcpEchoCheck (f); -} - -/* - * lcp_echo_lowerdown - Stop the timer for the LCP frame - */ - -static void lcp_echo_lowerdown (int unit) -{ - fsm *f = &lcp_fsm[unit]; - - if (lcp_echo_timer_running != 0) { - UNTIMEOUT (LcpEchoTimeout, f); - lcp_echo_timer_running = 0; - } -} - -#endif /* PPP_SUPPORT */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/lcp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/lcp.h deleted file mode 100644 index 3bf2edd50..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/lcp.h +++ /dev/null @@ -1,169 +0,0 @@ -/***************************************************************************** -* lcp.h - Network Link Control Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-11-05 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD codes. -*****************************************************************************/ -/* - * lcp.h - Link Control Protocol definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id$ - */ - -#ifndef LCP_H -#define LCP_H - - -/************************* -*** PUBLIC DEFINITIONS *** -*************************/ -/* - * Options. - */ -#define CI_MRU 1 /* Maximum Receive Unit */ -#define CI_ASYNCMAP 2 /* Async Control Character Map */ -#define CI_AUTHTYPE 3 /* Authentication Type */ -#define CI_QUALITY 4 /* Quality Protocol */ -#define CI_MAGICNUMBER 5 /* Magic Number */ -#define CI_PCOMPRESSION 7 /* Protocol Field Compression */ -#define CI_ACCOMPRESSION 8 /* Address/Control Field Compression */ -#define CI_CALLBACK 13 /* callback */ -#define CI_MRRU 17 /* max reconstructed receive unit; multilink */ -#define CI_SSNHF 18 /* short sequence numbers for multilink */ -#define CI_EPDISC 19 /* endpoint discriminator */ - -/* - * LCP-specific packet types. - */ -#define PROTREJ 8 /* Protocol Reject */ -#define ECHOREQ 9 /* Echo Request */ -#define ECHOREP 10 /* Echo Reply */ -#define DISCREQ 11 /* Discard Request */ -#define CBCP_OPT 6 /* Use callback control protocol */ - - -/************************ -*** PUBLIC DATA TYPES *** -************************/ - -/* - * The state of options is described by an lcp_options structure. - */ -typedef struct lcp_options { - u_int passive : 1; /* Don't die if we don't get a response */ - u_int silent : 1; /* Wait for the other end to start first */ - u_int restart : 1; /* Restart vs. exit after close */ - u_int neg_mru : 1; /* Negotiate the MRU? */ - u_int neg_asyncmap : 1; /* Negotiate the async map? */ - u_int neg_upap : 1; /* Ask for UPAP authentication? */ - u_int neg_chap : 1; /* Ask for CHAP authentication? */ - u_int neg_magicnumber : 1; /* Ask for magic number? */ - u_int neg_pcompression : 1; /* HDLC Protocol Field Compression? */ - u_int neg_accompression : 1; /* HDLC Address/Control Field Compression? */ - u_int neg_lqr : 1; /* Negotiate use of Link Quality Reports */ - u_int neg_cbcp : 1; /* Negotiate use of CBCP */ -#ifdef PPP_MULTILINK - u_int neg_mrru : 1; /* Negotiate multilink MRRU */ - u_int neg_ssnhf : 1; /* Negotiate short sequence numbers */ - u_int neg_endpoint : 1; /* Negotiate endpoint discriminator */ -#endif - u_short mru; /* Value of MRU */ -#ifdef PPP_MULTILINK - u_short mrru; /* Value of MRRU, and multilink enable */ -#endif - u_char chap_mdtype; /* which MD type (hashing algorithm) */ - u32_t asyncmap; /* Value of async map */ - u32_t magicnumber; - int numloops; /* Number of loops during magic number neg. */ - u32_t lqr_period; /* Reporting period for LQR 1/100ths second */ -#ifdef PPP_MULTILINK - struct epdisc endpoint; /* endpoint discriminator */ -#endif -} lcp_options; - -/* - * Values for phase from BSD pppd.h based on RFC 1661. - */ -typedef enum { - PHASE_DEAD = 0, - PHASE_INITIALIZE, - PHASE_ESTABLISH, - PHASE_AUTHENTICATE, - PHASE_CALLBACK, - PHASE_NETWORK, - PHASE_TERMINATE -} LinkPhase; - - -/***************************** -*** PUBLIC DATA STRUCTURES *** -*****************************/ - -extern LinkPhase lcp_phase[NUM_PPP]; /* Phase of link session (RFC 1661) */ -extern lcp_options lcp_wantoptions[]; -extern lcp_options lcp_gotoptions[]; -extern lcp_options lcp_allowoptions[]; -extern lcp_options lcp_hisoptions[]; -extern ext_accm xmit_accm[]; - - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ - -void lcp_init (int); -void lcp_open (int); -void lcp_close (int, char *); -void lcp_lowerup (int); -void lcp_lowerdown (int); -void lcp_sprotrej (int, u_char *, int); /* send protocol reject */ - -extern struct protent lcp_protent; - -/* Default number of times we receive our magic number from the peer - before deciding the link is looped-back. */ -#define DEFLOOPBACKFAIL 10 - -#endif /* LCP_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/magic.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/magic.c deleted file mode 100644 index 427401691..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/magic.c +++ /dev/null @@ -1,79 +0,0 @@ -/***************************************************************************** -* magic.c - Network Random Number Generator program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original based on BSD magic.c. -*****************************************************************************/ -/* - * magic.c - PPP Magic Number routines. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include "ppp.h" -#include "randm.h" -#include "magic.h" - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * magicInit - Initialize the magic number generator. - * - * Since we use another random number generator that has its own - * initialization, we do nothing here. - */ -void magicInit() -{ - return; -} - -/* - * magic - Returns the next magic number. - */ -u32_t magic() -{ - return avRandom(); -} - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/magic.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/magic.h deleted file mode 100644 index ef776d8ad..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/magic.h +++ /dev/null @@ -1,64 +0,0 @@ -/***************************************************************************** -* magic.h - Network Random Number Generator header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD codes. -*****************************************************************************/ -/* - * magic.h - PPP Magic Number definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id$ - */ - -#ifndef MAGIC_H -#define MAGIC_H - -/***************************************************************************** -************************** PUBLIC FUNCTIONS ********************************** -*****************************************************************************/ - -void magicInit(void); /* Initialize the magic number generator */ -u32_t magic(void); /* Returns the next magic number */ - -#endif /* MAGIC_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/md5.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/md5.c deleted file mode 100644 index e077cdea5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/md5.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - *********************************************************************** - ** md5.c -- the source code for MD5 routines ** - ** RSA Data Security, Inc. MD5 Message-Digest Algorithm ** - ** Created: 2/17/90 RLR ** - ** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. ** - *********************************************************************** - */ - -/* - *********************************************************************** - ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved. ** - ** ** - ** License to copy and use this software is granted provided that ** - ** it is identified as the "RSA Data Security, Inc. MD5 Message- ** - ** Digest Algorithm" in all material mentioning or referencing this ** - ** software or this function. ** - ** ** - ** License is also granted to make and use derivative works ** - ** provided that such works are identified as "derived from the RSA ** - ** Data Security, Inc. MD5 Message-Digest Algorithm" in all ** - ** material mentioning or referencing the derived work. ** - ** ** - ** RSA Data Security, Inc. makes no representations concerning ** - ** either the merchantability of this software or the suitability ** - ** of this software for any particular purpose. It is provided "as ** - ** is" without express or implied warranty of any kind. ** - ** ** - ** These notices must be retained in any copies of any part of this ** - ** documentation and/or software. ** - *********************************************************************** - */ - -#include "ppp.h" -#include "md5.h" -#include "pppdebug.h" - -#if CHAP_SUPPORT > 0 || MD5_SUPPORT > 0 - -/* - *********************************************************************** - ** Message-digest routines: ** - ** To form the message digest for a message M ** - ** (1) Initialize a context buffer mdContext using MD5Init ** - ** (2) Call MD5Update on mdContext and M ** - ** (3) Call MD5Final on mdContext ** - ** The message digest is now in mdContext->digest[0...15] ** - *********************************************************************** - */ - -/* forward declaration */ -static void Transform (u32_t *buf, u32_t *in); - -static unsigned char PADDING[64] = { - 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - -/* F, G, H and I are basic MD5 functions */ -#define F(x, y, z) (((x) & (y)) | ((~x) & (z))) -#define G(x, y, z) (((x) & (z)) | ((y) & (~z))) -#define H(x, y, z) ((x) ^ (y) ^ (z)) -#define I(x, y, z) ((y) ^ ((x) | (~z))) - -/* ROTATE_LEFT rotates x left n bits */ -#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n)))) - -/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */ -/* Rotation is separate from addition to prevent recomputation */ -#define FF(a, b, c, d, x, s, ac) \ - {(a) += F ((b), (c), (d)) + (x) + (u32_t)(ac); \ - (a) = ROTATE_LEFT ((a), (s)); \ - (a) += (b); \ - } -#define GG(a, b, c, d, x, s, ac) \ - {(a) += G ((b), (c), (d)) + (x) + (u32_t)(ac); \ - (a) = ROTATE_LEFT ((a), (s)); \ - (a) += (b); \ - } -#define HH(a, b, c, d, x, s, ac) \ - {(a) += H ((b), (c), (d)) + (x) + (u32_t)(ac); \ - (a) = ROTATE_LEFT ((a), (s)); \ - (a) += (b); \ - } -#define II(a, b, c, d, x, s, ac) \ - {(a) += I ((b), (c), (d)) + (x) + (u32_t)(ac); \ - (a) = ROTATE_LEFT ((a), (s)); \ - (a) += (b); \ - } - -#ifdef __STDC__ -#define UL(x) x##UL -#else -#ifdef WIN32 -#define UL(x) x##UL -#else -#define UL(x) x -#endif -#endif - -/* The routine MD5Init initializes the message-digest context - mdContext. All fields are set to zero. - */ -void MD5Init (MD5_CTX *mdContext) -{ - mdContext->i[0] = mdContext->i[1] = (u32_t)0; - - /* Load magic initialization constants. - */ - mdContext->buf[0] = (u32_t)0x67452301UL; - mdContext->buf[1] = (u32_t)0xefcdab89UL; - mdContext->buf[2] = (u32_t)0x98badcfeUL; - mdContext->buf[3] = (u32_t)0x10325476UL; -} - -/* The routine MD5Update updates the message-digest context to - account for the presence of each of the characters inBuf[0..inLen-1] - in the message whose digest is being computed. - */ -void MD5Update(MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen) -{ - u32_t in[16]; - int mdi; - unsigned int i, ii; - -#if 0 - ppp_trace(LOG_INFO, "MD5Update: %u:%.*H\n", inLen, MIN(inLen, 20) * 2, inBuf); - ppp_trace(LOG_INFO, "MD5Update: %u:%s\n", inLen, inBuf); -#endif - - /* compute number of bytes mod 64 */ - mdi = (int)((mdContext->i[0] >> 3) & 0x3F); - - /* update number of bits */ - if ((mdContext->i[0] + ((u32_t)inLen << 3)) < mdContext->i[0]) - mdContext->i[1]++; - mdContext->i[0] += ((u32_t)inLen << 3); - mdContext->i[1] += ((u32_t)inLen >> 29); - - while (inLen--) { - /* add new character to buffer, increment mdi */ - mdContext->in[mdi++] = *inBuf++; - - /* transform if necessary */ - if (mdi == 0x40) { - for (i = 0, ii = 0; i < 16; i++, ii += 4) - in[i] = (((u32_t)mdContext->in[ii+3]) << 24) | - (((u32_t)mdContext->in[ii+2]) << 16) | - (((u32_t)mdContext->in[ii+1]) << 8) | - ((u32_t)mdContext->in[ii]); - Transform (mdContext->buf, in); - mdi = 0; - } - } -} - -/* The routine MD5Final terminates the message-digest computation and - ends with the desired message digest in mdContext->digest[0...15]. - */ -void MD5Final (unsigned char hash[], MD5_CTX *mdContext) -{ - u32_t in[16]; - int mdi; - unsigned int i, ii; - unsigned int padLen; - - /* save number of bits */ - in[14] = mdContext->i[0]; - in[15] = mdContext->i[1]; - - /* compute number of bytes mod 64 */ - mdi = (int)((mdContext->i[0] >> 3) & 0x3F); - - /* pad out to 56 mod 64 */ - padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi); - MD5Update (mdContext, PADDING, padLen); - - /* append length in bits and transform */ - for (i = 0, ii = 0; i < 14; i++, ii += 4) - in[i] = (((u32_t)mdContext->in[ii+3]) << 24) | - (((u32_t)mdContext->in[ii+2]) << 16) | - (((u32_t)mdContext->in[ii+1]) << 8) | - ((u32_t)mdContext->in[ii]); - Transform (mdContext->buf, in); - - /* store buffer in digest */ - for (i = 0, ii = 0; i < 4; i++, ii += 4) { - mdContext->digest[ii] = (unsigned char)(mdContext->buf[i] & 0xFF); - mdContext->digest[ii+1] = - (unsigned char)((mdContext->buf[i] >> 8) & 0xFF); - mdContext->digest[ii+2] = - (unsigned char)((mdContext->buf[i] >> 16) & 0xFF); - mdContext->digest[ii+3] = - (unsigned char)((mdContext->buf[i] >> 24) & 0xFF); - } - memcpy(hash, mdContext->digest, 16); -} - -/* Basic MD5 step. Transforms buf based on in. - */ -static void Transform (u32_t *buf, u32_t *in) -{ - u32_t a = buf[0], b = buf[1], c = buf[2], d = buf[3]; - - /* Round 1 */ -#define S11 7 -#define S12 12 -#define S13 17 -#define S14 22 - FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */ - FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */ - FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */ - FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */ - FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */ - FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */ - FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */ - FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */ - FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */ - FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */ - FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */ - FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */ - FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */ - FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */ - FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */ - FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */ - - /* Round 2 */ -#define S21 5 -#define S22 9 -#define S23 14 -#define S24 20 - GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */ - GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */ - GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */ - GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */ - GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */ - GG ( d, a, b, c, in[10], S22, UL( 38016083)); /* 22 */ - GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */ - GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */ - GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */ - GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */ - GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */ - GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */ - GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */ - GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */ - GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */ - GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */ - - /* Round 3 */ -#define S31 4 -#define S32 11 -#define S33 16 -#define S34 23 - HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */ - HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */ - HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */ - HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */ - HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */ - HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */ - HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */ - HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */ - HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */ - HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */ - HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */ - HH ( b, c, d, a, in[ 6], S34, UL( 76029189)); /* 44 */ - HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */ - HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */ - HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */ - HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */ - - /* Round 4 */ -#define S41 6 -#define S42 10 -#define S43 15 -#define S44 21 - II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */ - II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */ - II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */ - II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */ - II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */ - II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */ - II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */ - II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */ - II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */ - II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */ - II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */ - II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */ - II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */ - II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */ - II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */ - II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */ - - buf[0] += a; - buf[1] += b; - buf[2] += c; - buf[3] += d; -} - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/md5.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/md5.h deleted file mode 100644 index 0e81cdc34..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/md5.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - *********************************************************************** - ** md5.h -- header file for implementation of MD5 ** - ** RSA Data Security, Inc. MD5 Message-Digest Algorithm ** - ** Created: 2/17/90 RLR ** - ** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version ** - ** Revised (for MD5): RLR 4/27/91 ** - ** -- G modified to have y&~z instead of y&z ** - ** -- FF, GG, HH modified to add in last register done ** - ** -- Access pattern: round 2 works mod 5, round 3 works mod 3 ** - ** -- distinct additive constant for each step ** - ** -- round 4 added, working mod 7 ** - *********************************************************************** - */ - -/* - *********************************************************************** - ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved. ** - ** ** - ** License to copy and use this software is granted provided that ** - ** it is identified as the "RSA Data Security, Inc. MD5 Message- ** - ** Digest Algorithm" in all material mentioning or referencing this ** - ** software or this function. ** - ** ** - ** License is also granted to make and use derivative works ** - ** provided that such works are identified as "derived from the RSA ** - ** Data Security, Inc. MD5 Message-Digest Algorithm" in all ** - ** material mentioning or referencing the derived work. ** - ** ** - ** RSA Data Security, Inc. makes no representations concerning ** - ** either the merchantability of this software or the suitability ** - ** of this software for any particular purpose. It is provided "as ** - ** is" without express or implied warranty of any kind. ** - ** ** - ** These notices must be retained in any copies of any part of this ** - ** documentation and/or software. ** - *********************************************************************** - */ - -#ifndef MD5_H -#define MD5_H - -/* Data structure for MD5 (Message-Digest) computation */ -typedef struct { - u32_t i[2]; /* number of _bits_ handled mod 2^64 */ - u32_t buf[4]; /* scratch buffer */ - unsigned char in[64]; /* input buffer */ - unsigned char digest[16]; /* actual digest after MD5Final call */ -} MD5_CTX; - -void MD5Init (MD5_CTX *mdContext); -void MD5Update (MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen); -void MD5Final (unsigned char hash[], MD5_CTX *mdContext); - -#endif /* MD5_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/pap.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/pap.c deleted file mode 100644 index 23e438ff2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/pap.c +++ /dev/null @@ -1,608 +0,0 @@ -/***************************************************************************** -* pap.c - Network Password Authentication Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-12 Guy Lancaster , Global Election Systems Inc. -* Original. -*****************************************************************************/ -/* - * upap.c - User/Password Authentication Protocol. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include "ppp.h" -#include "auth.h" -#include "pap.h" -#include "pppdebug.h" - - -#if PAP_SUPPORT > 0 - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -/* - * Protocol entry points. - */ -static void upap_init (int); -static void upap_lowerup (int); -static void upap_lowerdown (int); -static void upap_input (int, u_char *, int); -static void upap_protrej (int); - -static void upap_timeout (void *); -static void upap_reqtimeout (void *); -static void upap_rauthreq (upap_state *, u_char *, int, int); -static void upap_rauthack (upap_state *, u_char *, int, int); -static void upap_rauthnak (upap_state *, u_char *, int, int); -static void upap_sauthreq (upap_state *); -static void upap_sresp (upap_state *, u_char, u_char, char *, int); - - - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ -struct protent pap_protent = { - PPP_PAP, - upap_init, - upap_input, - upap_protrej, - upap_lowerup, - upap_lowerdown, - NULL, - NULL, -#if 0 - upap_printpkt, - NULL, -#endif - 1, - "PAP", -#if 0 - NULL, - NULL, - NULL -#endif -}; - -upap_state upap[NUM_PPP]; /* UPAP state; one for each unit */ - - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * Set the default login name and password for the pap sessions - */ -void upap_setloginpasswd(int unit, const char *luser, const char *lpassword) -{ - upap_state *u = &upap[unit]; - - /* Save the username and password we're given */ - u->us_user = luser; - u->us_userlen = strlen(luser); - u->us_passwd = lpassword; - u->us_passwdlen = strlen(lpassword); -} - - -/* - * upap_authwithpeer - Authenticate us with our peer (start client). - * - * Set new state and send authenticate's. - */ -void upap_authwithpeer(int unit, char *user, char *password) -{ - upap_state *u = &upap[unit]; - - UPAPDEBUG((LOG_INFO, "upap_authwithpeer: %d user=%s password=%s s=%d\n", - unit, user, password, u->us_clientstate)); - - upap_setloginpasswd(unit, user, password); - - u->us_transmits = 0; - - /* Lower layer up yet? */ - if (u->us_clientstate == UPAPCS_INITIAL || - u->us_clientstate == UPAPCS_PENDING) { - u->us_clientstate = UPAPCS_PENDING; - return; - } - - upap_sauthreq(u); /* Start protocol */ -} - - -/* - * upap_authpeer - Authenticate our peer (start server). - * - * Set new state. - */ -void upap_authpeer(int unit) -{ - upap_state *u = &upap[unit]; - - /* Lower layer up yet? */ - if (u->us_serverstate == UPAPSS_INITIAL || - u->us_serverstate == UPAPSS_PENDING) { - u->us_serverstate = UPAPSS_PENDING; - return; - } - - u->us_serverstate = UPAPSS_LISTEN; - if (u->us_reqtimeout > 0) - TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout); -} - - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ -/* - * upap_init - Initialize a UPAP unit. - */ -static void upap_init(int unit) -{ - upap_state *u = &upap[unit]; - - UPAPDEBUG((LOG_INFO, "upap_init: %d\n", unit)); - u->us_unit = unit; - u->us_user = NULL; - u->us_userlen = 0; - u->us_passwd = NULL; - u->us_passwdlen = 0; - u->us_clientstate = UPAPCS_INITIAL; - u->us_serverstate = UPAPSS_INITIAL; - u->us_id = 0; - u->us_timeouttime = UPAP_DEFTIMEOUT; - u->us_maxtransmits = 10; - u->us_reqtimeout = UPAP_DEFREQTIME; -} - -/* - * upap_timeout - Retransmission timer for sending auth-reqs expired. - */ -static void upap_timeout(void *arg) -{ - upap_state *u = (upap_state *) arg; - - UPAPDEBUG((LOG_INFO, "upap_timeout: %d timeout %d expired s=%d\n", - u->us_unit, u->us_timeouttime, u->us_clientstate)); - - if (u->us_clientstate != UPAPCS_AUTHREQ) - return; - - if (u->us_transmits >= u->us_maxtransmits) { - /* give up in disgust */ - UPAPDEBUG((LOG_ERR, "No response to PAP authenticate-requests\n")); - u->us_clientstate = UPAPCS_BADAUTH; - auth_withpeer_fail(u->us_unit, PPP_PAP); - return; - } - - upap_sauthreq(u); /* Send Authenticate-Request */ -} - - -/* - * upap_reqtimeout - Give up waiting for the peer to send an auth-req. - */ -static void upap_reqtimeout(void *arg) -{ - upap_state *u = (upap_state *) arg; - - if (u->us_serverstate != UPAPSS_LISTEN) - return; /* huh?? */ - - auth_peer_fail(u->us_unit, PPP_PAP); - u->us_serverstate = UPAPSS_BADAUTH; -} - - -/* - * upap_lowerup - The lower layer is up. - * - * Start authenticating if pending. - */ -static void upap_lowerup(int unit) -{ - upap_state *u = &upap[unit]; - - UPAPDEBUG((LOG_INFO, "upap_lowerup: %d s=%d\n", unit, u->us_clientstate)); - - if (u->us_clientstate == UPAPCS_INITIAL) - u->us_clientstate = UPAPCS_CLOSED; - else if (u->us_clientstate == UPAPCS_PENDING) { - upap_sauthreq(u); /* send an auth-request */ - } - - if (u->us_serverstate == UPAPSS_INITIAL) - u->us_serverstate = UPAPSS_CLOSED; - else if (u->us_serverstate == UPAPSS_PENDING) { - u->us_serverstate = UPAPSS_LISTEN; - if (u->us_reqtimeout > 0) - TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout); - } -} - - -/* - * upap_lowerdown - The lower layer is down. - * - * Cancel all timeouts. - */ -static void upap_lowerdown(int unit) -{ - upap_state *u = &upap[unit]; - - UPAPDEBUG((LOG_INFO, "upap_lowerdown: %d s=%d\n", unit, u->us_clientstate)); - - if (u->us_clientstate == UPAPCS_AUTHREQ) /* Timeout pending? */ - UNTIMEOUT(upap_timeout, u); /* Cancel timeout */ - if (u->us_serverstate == UPAPSS_LISTEN && u->us_reqtimeout > 0) - UNTIMEOUT(upap_reqtimeout, u); - - u->us_clientstate = UPAPCS_INITIAL; - u->us_serverstate = UPAPSS_INITIAL; -} - - -/* - * upap_protrej - Peer doesn't speak this protocol. - * - * This shouldn't happen. In any case, pretend lower layer went down. - */ -static void upap_protrej(int unit) -{ - upap_state *u = &upap[unit]; - - if (u->us_clientstate == UPAPCS_AUTHREQ) { - UPAPDEBUG((LOG_ERR, "PAP authentication failed due to protocol-reject\n")); - auth_withpeer_fail(unit, PPP_PAP); - } - if (u->us_serverstate == UPAPSS_LISTEN) { - UPAPDEBUG((LOG_ERR, "PAP authentication of peer failed (protocol-reject)\n")); - auth_peer_fail(unit, PPP_PAP); - } - upap_lowerdown(unit); -} - - -/* - * upap_input - Input UPAP packet. - */ -static void upap_input(int unit, u_char *inpacket, int l) -{ - upap_state *u = &upap[unit]; - u_char *inp; - u_char code, id; - int len; - - /* - * Parse header (code, id and length). - * If packet too short, drop it. - */ - inp = inpacket; - if (l < UPAP_HEADERLEN) { - UPAPDEBUG((LOG_INFO, "pap_input: rcvd short header.\n")); - return; - } - GETCHAR(code, inp); - GETCHAR(id, inp); - GETSHORT(len, inp); - if (len < UPAP_HEADERLEN) { - UPAPDEBUG((LOG_INFO, "pap_input: rcvd illegal length.\n")); - return; - } - if (len > l) { - UPAPDEBUG((LOG_INFO, "pap_input: rcvd short packet.\n")); - return; - } - len -= UPAP_HEADERLEN; - - /* - * Action depends on code. - */ - switch (code) { - case UPAP_AUTHREQ: - upap_rauthreq(u, inp, id, len); - break; - - case UPAP_AUTHACK: - upap_rauthack(u, inp, id, len); - break; - - case UPAP_AUTHNAK: - upap_rauthnak(u, inp, id, len); - break; - - default: /* XXX Need code reject */ - break; - } -} - - -/* - * upap_rauth - Receive Authenticate. - */ -static void upap_rauthreq( - upap_state *u, - u_char *inp, - int id, - int len -) -{ - u_char ruserlen, rpasswdlen; - char *ruser, *rpasswd; - int retcode; - char *msg; - int msglen; - - UPAPDEBUG((LOG_INFO, "pap_rauth: Rcvd id %d.\n", id)); - - if (u->us_serverstate < UPAPSS_LISTEN) - return; - - /* - * If we receive a duplicate authenticate-request, we are - * supposed to return the same status as for the first request. - */ - if (u->us_serverstate == UPAPSS_OPEN) { - upap_sresp(u, UPAP_AUTHACK, id, "", 0); /* return auth-ack */ - return; - } - if (u->us_serverstate == UPAPSS_BADAUTH) { - upap_sresp(u, UPAP_AUTHNAK, id, "", 0); /* return auth-nak */ - return; - } - - /* - * Parse user/passwd. - */ - if (len < sizeof (u_char)) { - UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n")); - return; - } - GETCHAR(ruserlen, inp); - len -= sizeof (u_char) + ruserlen + sizeof (u_char); - if (len < 0) { - UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n")); - return; - } - ruser = (char *) inp; - INCPTR(ruserlen, inp); - GETCHAR(rpasswdlen, inp); - if (len < rpasswdlen) { - UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n")); - return; - } - rpasswd = (char *) inp; - - /* - * Check the username and password given. - */ - retcode = check_passwd(u->us_unit, ruser, ruserlen, rpasswd, - rpasswdlen, &msg, &msglen); - BZERO(rpasswd, rpasswdlen); - - upap_sresp(u, retcode, id, msg, msglen); - - if (retcode == UPAP_AUTHACK) { - u->us_serverstate = UPAPSS_OPEN; - auth_peer_success(u->us_unit, PPP_PAP, ruser, ruserlen); - } else { - u->us_serverstate = UPAPSS_BADAUTH; - auth_peer_fail(u->us_unit, PPP_PAP); - } - - if (u->us_reqtimeout > 0) - UNTIMEOUT(upap_reqtimeout, u); -} - - -/* - * upap_rauthack - Receive Authenticate-Ack. - */ -static void upap_rauthack( - upap_state *u, - u_char *inp, - int id, - int len -) -{ - u_char msglen; - char *msg; - - UPAPDEBUG((LOG_INFO, "pap_rauthack: Rcvd id %d s=%d\n", id, u->us_clientstate)); - - if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */ - return; - - /* - * Parse message. - */ - if (len < sizeof (u_char)) { - UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n")); - return; - } - GETCHAR(msglen, inp); - len -= sizeof (u_char); - if (len < msglen) { - UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n")); - return; - } - msg = (char *) inp; - PRINTMSG(msg, msglen); - - u->us_clientstate = UPAPCS_OPEN; - - auth_withpeer_success(u->us_unit, PPP_PAP); -} - - -/* - * upap_rauthnak - Receive Authenticate-Nakk. - */ -static void upap_rauthnak( - upap_state *u, - u_char *inp, - int id, - int len -) -{ - u_char msglen; - char *msg; - - UPAPDEBUG((LOG_INFO, "pap_rauthnak: Rcvd id %d s=%d\n", id, u->us_clientstate)); - - if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */ - return; - - /* - * Parse message. - */ - if (len < sizeof (u_char)) { - UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n")); - return; - } - GETCHAR(msglen, inp); - len -= sizeof (u_char); - if (len < msglen) { - UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n")); - return; - } - msg = (char *) inp; - PRINTMSG(msg, msglen); - - u->us_clientstate = UPAPCS_BADAUTH; - - UPAPDEBUG((LOG_ERR, "PAP authentication failed\n")); - auth_withpeer_fail(u->us_unit, PPP_PAP); -} - - -/* - * upap_sauthreq - Send an Authenticate-Request. - */ -static void upap_sauthreq(upap_state *u) -{ - u_char *outp; - int outlen; - - outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) - + u->us_userlen + u->us_passwdlen; - outp = outpacket_buf[u->us_unit]; - - MAKEHEADER(outp, PPP_PAP); - - PUTCHAR(UPAP_AUTHREQ, outp); - PUTCHAR(++u->us_id, outp); - PUTSHORT(outlen, outp); - PUTCHAR(u->us_userlen, outp); - BCOPY(u->us_user, outp, u->us_userlen); - INCPTR(u->us_userlen, outp); - PUTCHAR(u->us_passwdlen, outp); - BCOPY(u->us_passwd, outp, u->us_passwdlen); - - pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN); - - UPAPDEBUG((LOG_INFO, "pap_sauth: Sent id %d\n", u->us_id)); - - TIMEOUT(upap_timeout, u, u->us_timeouttime); - ++u->us_transmits; - u->us_clientstate = UPAPCS_AUTHREQ; -} - - -/* - * upap_sresp - Send a response (ack or nak). - */ -static void upap_sresp( - upap_state *u, - u_char code, - u_char id, - char *msg, - int msglen -) -{ - u_char *outp; - int outlen; - - outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen; - outp = outpacket_buf[u->us_unit]; - MAKEHEADER(outp, PPP_PAP); - - PUTCHAR(code, outp); - PUTCHAR(id, outp); - PUTSHORT(outlen, outp); - PUTCHAR(msglen, outp); - BCOPY(msg, outp, msglen); - pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN); - - UPAPDEBUG((LOG_INFO, "pap_sresp: Sent code %d, id %d s=%d\n", - code, id, u->us_clientstate)); -} - -#if 0 -/* - * upap_printpkt - print the contents of a PAP packet. - */ -static int upap_printpkt( - u_char *p, - int plen, - void (*printer) (void *, char *, ...), - void *arg -) -{ - (void)p; - (void)plen; - (void)printer; - (void)arg; - return 0; -} -#endif - -#endif /* PAP_SUPPORT */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/pap.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/pap.h deleted file mode 100644 index 215c8a4f2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/pap.h +++ /dev/null @@ -1,129 +0,0 @@ -/***************************************************************************** -* pap.h - PPP Password Authentication Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD codes. -*****************************************************************************/ -/* - * upap.h - User/Password Authentication Protocol definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - - -#ifndef PAP_H -#define PAP_H - -/************************* -*** PUBLIC DEFINITIONS *** -*************************/ -/* - * Packet header = Code, id, length. - */ -#define UPAP_HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short)) - - -/* - * UPAP codes. - */ -#define UPAP_AUTHREQ 1 /* Authenticate-Request */ -#define UPAP_AUTHACK 2 /* Authenticate-Ack */ -#define UPAP_AUTHNAK 3 /* Authenticate-Nak */ - -/* - * Client states. - */ -#define UPAPCS_INITIAL 0 /* Connection down */ -#define UPAPCS_CLOSED 1 /* Connection up, haven't requested auth */ -#define UPAPCS_PENDING 2 /* Connection down, have requested auth */ -#define UPAPCS_AUTHREQ 3 /* We've sent an Authenticate-Request */ -#define UPAPCS_OPEN 4 /* We've received an Ack */ -#define UPAPCS_BADAUTH 5 /* We've received a Nak */ - -/* - * Server states. - */ -#define UPAPSS_INITIAL 0 /* Connection down */ -#define UPAPSS_CLOSED 1 /* Connection up, haven't requested auth */ -#define UPAPSS_PENDING 2 /* Connection down, have requested auth */ -#define UPAPSS_LISTEN 3 /* Listening for an Authenticate */ -#define UPAPSS_OPEN 4 /* We've sent an Ack */ -#define UPAPSS_BADAUTH 5 /* We've sent a Nak */ - - -/************************ -*** PUBLIC DATA TYPES *** -************************/ - -/* - * Each interface is described by upap structure. - */ -typedef struct upap_state { - int us_unit; /* Interface unit number */ - const char *us_user; /* User */ - int us_userlen; /* User length */ - const char *us_passwd; /* Password */ - int us_passwdlen; /* Password length */ - int us_clientstate; /* Client state */ - int us_serverstate; /* Server state */ - u_char us_id; /* Current id */ - int us_timeouttime; /* Timeout (seconds) for auth-req retrans. */ - int us_transmits; /* Number of auth-reqs sent */ - int us_maxtransmits; /* Maximum number of auth-reqs to send */ - int us_reqtimeout; /* Time to wait for auth-req from peer */ -} upap_state; - - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ - -extern upap_state upap[]; - -void upap_setloginpasswd(int unit, const char *luser, const char *lpassword); -void upap_authwithpeer (int, char *, char *); -void upap_authpeer (int); - -extern struct protent pap_protent; - -#endif /* PAP_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/ppp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/ppp.c deleted file mode 100644 index df402189e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/ppp.c +++ /dev/null @@ -1,1623 +0,0 @@ -/***************************************************************************** -* ppp.c - Network Point to Point Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-11-05 Guy Lancaster , Global Election Systems Inc. -* Original. -*****************************************************************************/ - -/* - * ppp_defs.h - PPP definitions. - * - * if_pppvar.h - private structures and declarations for PPP. - * - * Copyright (c) 1994 The Australian National University. - * All rights reserved. - * - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, provided that the above copyright - * notice appears in all copies. This software is provided without any - * warranty, express or implied. The Australian National University - * makes no representations about the suitability of this software for - * any purpose. - * - * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY - * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES - * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF - * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS - * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO - * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, - * OR MODIFICATIONS. - */ - -/* - * if_ppp.h - Point-to-Point Protocol definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include - -#include "ppp.h" -#if PPP_SUPPORT > 0 -#include "randm.h" -#include "fsm.h" -#if PAP_SUPPORT > 0 -#include "pap.h" -#endif -#if CHAP_SUPPORT > 0 -#include "chap.h" -#endif -#include "ipcp.h" -#include "lcp.h" -#include "magic.h" -#include "auth.h" -#if VJ_SUPPORT > 0 -#include "vj.h" -#endif - -#include "pppdebug.h" - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ - -/* - * The basic PPP frame. - */ -#define PPP_ADDRESS(p) (((u_char *)(p))[0]) -#define PPP_CONTROL(p) (((u_char *)(p))[1]) -#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3]) - -/* PPP packet parser states. Current state indicates operation yet to be - * completed. */ -typedef enum { - PDIDLE = 0, /* Idle state - waiting. */ - PDSTART, /* Process start flag. */ - PDADDRESS, /* Process address field. */ - PDCONTROL, /* Process control field. */ - PDPROTOCOL1, /* Process protocol field 1. */ - PDPROTOCOL2, /* Process protocol field 2. */ - PDDATA /* Process data byte. */ -} PPPDevStates; - -#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & pppACCMMask[c & 0x07]) - -/************************/ -/*** LOCAL DATA TYPES ***/ -/************************/ -/* - * PPP interface control block. - */ -typedef struct PPPControl_s { - char openFlag; /* True when in use. */ - char oldFrame; /* Old framing character for fd. */ - sio_fd_t fd; /* File device ID of port. */ - int kill_link; /* Shut the link down. */ - int sig_hup; /* Carrier lost. */ - int if_up; /* True when the interface is up. */ - int errCode; /* Code indicating why interface is down. */ - struct pbuf *inHead, *inTail; /* The input packet. */ - PPPDevStates inState; /* The input process state. */ - char inEscaped; /* Escape next character. */ - u16_t inProtocol; /* The input protocol code. */ - u16_t inFCS; /* Input Frame Check Sequence value. */ - int mtu; /* Peer's mru */ - int pcomp; /* Does peer accept protocol compression? */ - int accomp; /* Does peer accept addr/ctl compression? */ - u_long lastXMit; /* Time of last transmission. */ - ext_accm inACCM; /* Async-Ctl-Char-Map for input. */ - ext_accm outACCM; /* Async-Ctl-Char-Map for output. */ -#if VJ_SUPPORT > 0 - int vjEnabled; /* Flag indicating VJ compression enabled. */ - struct vjcompress vjComp; /* Van Jabobsen compression header. */ -#endif - - struct netif netif; - - struct ppp_addrs addrs; - - void (*linkStatusCB)(void *ctx, int errCode, void *arg); - void *linkStatusCtx; - -} PPPControl; - - -/* - * Ioctl definitions. - */ - -struct npioctl { - int protocol; /* PPP procotol, e.g. PPP_IP */ - enum NPmode mode; -}; - - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -static void pppMain(void *pd); -static void pppDrop(PPPControl *pc); -static void pppInProc(int pd, u_char *s, int l); - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ -u_long subnetMask; - -static PPPControl pppControl[NUM_PPP]; /* The PPP interface control blocks. */ - -/* - * PPP Data Link Layer "protocol" table. - * One entry per supported protocol. - * The last entry must be NULL. - */ -struct protent *ppp_protocols[] = { - &lcp_protent, -#if PAP_SUPPORT > 0 - &pap_protent, -#endif -#if CHAP_SUPPORT > 0 - &chap_protent, -#endif -#if CBCP_SUPPORT > 0 - &cbcp_protent, -#endif - &ipcp_protent, -#if CCP_SUPPORT > 0 - &ccp_protent, -#endif - NULL -}; - - -/* - * Buffers for outgoing packets. This must be accessed only from the appropriate - * PPP task so that it doesn't need to be protected to avoid collisions. - */ -u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN]; - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ - -/* - * FCS lookup table as calculated by genfcstab. - */ -static const u_short fcstab[256] = { - 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, - 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, - 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, - 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, - 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd, - 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5, - 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c, - 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974, - 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb, - 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, - 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, - 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72, - 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9, - 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1, - 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738, - 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70, - 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7, - 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff, - 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036, - 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e, - 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5, - 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd, - 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134, - 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c, - 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3, - 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb, - 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232, - 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a, - 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1, - 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9, - 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330, - 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78 -}; - -/* PPP's Asynchronous-Control-Character-Map. The mask array is used - * to select the specific bit for a character. */ -static u_char pppACCMMask[] = { - 0x01, - 0x02, - 0x04, - 0x08, - 0x10, - 0x20, - 0x40, - 0x80 -}; - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* Initialize the PPP subsystem. */ - -struct ppp_settings ppp_settings; - -void pppInit(void) -{ - struct protent *protp; - int i, j; - - memset(&ppp_settings, 0, sizeof(ppp_settings)); - ppp_settings.usepeerdns = 1; - pppSetAuth(PPPAUTHTYPE_NONE, NULL, NULL); - - magicInit(); - - for (i = 0; i < NUM_PPP; i++) { - pppControl[i].openFlag = 0; - - subnetMask = htonl(0xffffff00); - - /* - * Initialize to the standard option set. - */ - for (j = 0; (protp = ppp_protocols[j]) != NULL; ++j) - (*protp->init)(i); - } - -#if LINK_STATS - /* Clear the statistics. */ - memset(&lwip_stats.link, 0, sizeof(lwip_stats.link)); -#endif -} - -void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd) -{ - switch(authType) { - case PPPAUTHTYPE_NONE: - default: -#ifdef LWIP_PPP_STRICT_PAP_REJECT - ppp_settings.refuse_pap = 1; -#else - /* some providers request pap and accept an empty login/pw */ - ppp_settings.refuse_pap = 0; -#endif - ppp_settings.refuse_chap = 1; - break; - case PPPAUTHTYPE_ANY: -/* Warning: Using PPPAUTHTYPE_ANY might have security consequences. - * RFC 1994 says: - * - * In practice, within or associated with each PPP server, there is a - * database which associates "user" names with authentication - * information ("secrets"). It is not anticipated that a particular - * named user would be authenticated by multiple methods. This would - * make the user vulnerable to attacks which negotiate the least secure - * method from among a set (such as PAP rather than CHAP). If the same - * secret was used, PAP would reveal the secret to be used later with - * CHAP. - * - * Instead, for each user name there should be an indication of exactly - * one method used to authenticate that user name. If a user needs to - * make use of different authentication methods under different - * circumstances, then distinct user names SHOULD be employed, each of - * which identifies exactly one authentication method. - * - */ - ppp_settings.refuse_pap = 0; - ppp_settings.refuse_chap = 0; - break; - case PPPAUTHTYPE_PAP: - ppp_settings.refuse_pap = 0; - ppp_settings.refuse_chap = 1; - break; - case PPPAUTHTYPE_CHAP: - ppp_settings.refuse_pap = 1; - ppp_settings.refuse_chap = 0; - break; - } - - if(user) { - strncpy(ppp_settings.user, user, sizeof(ppp_settings.user)-1); - ppp_settings.user[sizeof(ppp_settings.user)-1] = '\0'; - } else - ppp_settings.user[0] = '\0'; - - if(passwd) { - strncpy(ppp_settings.passwd, passwd, sizeof(ppp_settings.passwd)-1); - ppp_settings.passwd[sizeof(ppp_settings.passwd)-1] = '\0'; - } else - ppp_settings.passwd[0] = '\0'; -} - -/* Open a new PPP connection using the given I/O device. - * This initializes the PPP control block but does not - * attempt to negotiate the LCP session. If this port - * connects to a modem, the modem connection must be - * established before calling this. - * Return a new PPP connection descriptor on success or - * an error code (negative) on failure. */ -int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx) -{ - PPPControl *pc; - int pd; - - /* Find a free PPP session descriptor. Critical region? */ - for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++); - if (pd >= NUM_PPP) - pd = PPPERR_OPEN; - else - pppControl[pd].openFlag = !0; - - /* Launch a deamon thread. */ - if (pd >= 0) { - - pppControl[pd].openFlag = 1; - - lcp_init(pd); - pc = &pppControl[pd]; - pc->fd = fd; - pc->kill_link = 0; - pc->sig_hup = 0; - pc->if_up = 0; - pc->errCode = 0; - pc->inState = PDIDLE; - pc->inHead = NULL; - pc->inTail = NULL; - pc->inEscaped = 0; - pc->lastXMit = 0; - -#if VJ_SUPPORT > 0 - pc->vjEnabled = 0; - vj_compress_init(&pc->vjComp); -#endif - - /* - * Default the in and out accm so that escape and flag characters - * are always escaped. - */ - memset(pc->inACCM, 0, sizeof(ext_accm)); - pc->inACCM[15] = 0x60; - memset(pc->outACCM, 0, sizeof(ext_accm)); - pc->outACCM[15] = 0x60; - - pc->linkStatusCB = linkStatusCB; - pc->linkStatusCtx = linkStatusCtx; - - sys_thread_new(pppMain, (void*)pd, PPP_THREAD_PRIO); - if(!linkStatusCB) { - while(pd >= 0 && !pc->if_up) { - sys_msleep(500); - if (lcp_phase[pd] == PHASE_DEAD) { - pppClose(pd); - if (pc->errCode) - pd = pc->errCode; - else - pd = PPPERR_CONNECT; - } - } - } - } - return pd; -} - -/* Close a PPP connection and release the descriptor. - * Any outstanding packets in the queues are dropped. - * Return 0 on success, an error code on failure. */ -int pppClose(int pd) -{ - PPPControl *pc = &pppControl[pd]; - int st = 0; - - /* Disconnect */ - pc->kill_link = !0; - pppMainWakeup(pd); - - if(!pc->linkStatusCB) { - while(st >= 0 && lcp_phase[pd] != PHASE_DEAD) { - sys_msleep(500); - break; - } - } - return st; -} - -/* This function is called when carrier is lost on the PPP channel. */ -void pppSigHUP(int pd) -{ - PPPControl *pc = &pppControl[pd]; - - pc->sig_hup = 1; - pppMainWakeup(pd); -} - -static void nPut(PPPControl *pc, struct pbuf *nb) -{ - struct pbuf *b; - int c; - - for(b = nb; b != NULL; b = b->next) { - if((c = sio_write(pc->fd, b->payload, b->len)) != b->len) { - PPPDEBUG((LOG_WARNING, - "PPP nPut: incomplete sio_write(%d,, %u) = %d\n", pc->fd, b->len, c)); -#if LINK_STATS - lwip_stats.link.err++; -#endif /* LINK_STATS */ - pc->lastXMit = 0; /* prepend PPP_FLAG to next packet */ - break; - } - } - pbuf_free(nb); - -#if LINK_STATS - lwip_stats.link.xmit++; -#endif /* LINK_STATS */ -} - -/* - * pppAppend - append given character to end of given pbuf. If outACCM - * is not NULL and the character needs to be escaped, do so. - * If pbuf is full, append another. - * Return the current pbuf. - */ -static struct pbuf *pppAppend(u_char c, struct pbuf *nb, ext_accm *outACCM) -{ - struct pbuf *tb = nb; - - /* Make sure there is room for the character and an escape code. - * Sure we don't quite fill the buffer if the character doesn't - * get escaped but is one character worth complicating this? */ - /* Note: We assume no packet header. */ - if (nb && (PBUF_POOL_BUFSIZE - nb->len) < 2) { - tb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); - if (tb) { - nb->next = tb; - } -#if LINK_STATS - else { - lwip_stats.link.memerr++; - } -#endif /* LINK_STATS */ - nb = tb; - } - if (nb) { - if (outACCM && ESCAPE_P(*outACCM, c)) { - *((u_char*)nb->payload + nb->len++) = PPP_ESCAPE; - *((u_char*)nb->payload + nb->len++) = c ^ PPP_TRANS; - } - else - *((u_char*)nb->payload + nb->len++) = c; - } - - return tb; -} - -/* Send a packet on the given connection. */ -static err_t pppifOutput(struct netif *netif, struct pbuf *pb, struct ip_addr *ipaddr) -{ - int pd = (int)netif->state; - u_short protocol = PPP_IP; - PPPControl *pc = &pppControl[pd]; - u_int fcsOut = PPP_INITFCS; - struct pbuf *headMB = NULL, *tailMB = NULL, *p; - u_char c; - - (void)ipaddr; - - /* Validate parameters. */ - /* We let any protocol value go through - it can't hurt us - * and the peer will just drop it if it's not accepting it. */ - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag || !pb) { - PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad parms prot=%d pb=%p\n", - pd, protocol, pb)); -#if LINK_STATS - lwip_stats.link.opterr++; - lwip_stats.link.drop++; -#endif - return ERR_ARG; - } - - /* Check that the link is up. */ - if (lcp_phase[pd] == PHASE_DEAD) { - PPPDEBUG((LOG_ERR, "pppifOutput[%d]: link not up\n", pd)); -#if LINK_STATS - lwip_stats.link.rterr++; - lwip_stats.link.drop++; -#endif - return ERR_RTE; - } - - /* Grab an output buffer. */ - headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); - if (headMB == NULL) { - PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: first alloc fail\n", pd)); -#if LINK_STATS - lwip_stats.link.memerr++; - lwip_stats.link.drop++; -#endif /* LINK_STATS */ - return ERR_MEM; - } - -#if VJ_SUPPORT > 0 - /* - * Attempt Van Jacobson header compression if VJ is configured and - * this is an IP packet. - */ - if (protocol == PPP_IP && pc->vjEnabled) { - switch (vj_compress_tcp(&pc->vjComp, pb)) { - case TYPE_IP: - /* No change... - protocol = PPP_IP_PROTOCOL; - */ - break; - case TYPE_COMPRESSED_TCP: - protocol = PPP_VJC_COMP; - break; - case TYPE_UNCOMPRESSED_TCP: - protocol = PPP_VJC_UNCOMP; - break; - default: - PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad IP packet\n", pd)); -#if LINK_STATS - lwip_stats.link.proterr++; - lwip_stats.link.drop++; -#endif - pbuf_free(headMB); - return ERR_VAL; - } - } -#endif - - tailMB = headMB; - - /* Build the PPP header. */ - if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) - tailMB = pppAppend(PPP_FLAG, tailMB, NULL); - pc->lastXMit = sys_jiffies(); - if (!pc->accomp) { - fcsOut = PPP_FCS(fcsOut, PPP_ALLSTATIONS); - tailMB = pppAppend(PPP_ALLSTATIONS, tailMB, &pc->outACCM); - fcsOut = PPP_FCS(fcsOut, PPP_UI); - tailMB = pppAppend(PPP_UI, tailMB, &pc->outACCM); - } - if (!pc->pcomp || protocol > 0xFF) { - c = (protocol >> 8) & 0xFF; - fcsOut = PPP_FCS(fcsOut, c); - tailMB = pppAppend(c, tailMB, &pc->outACCM); - } - c = protocol & 0xFF; - fcsOut = PPP_FCS(fcsOut, c); - tailMB = pppAppend(c, tailMB, &pc->outACCM); - - /* Load packet. */ - for(p = pb; p; p = p->next) { - int n; - u_char *sPtr; - - sPtr = (u_char*)p->payload; - n = p->len; - while (n-- > 0) { - c = *sPtr++; - - /* Update FCS before checking for special characters. */ - fcsOut = PPP_FCS(fcsOut, c); - - /* Copy to output buffer escaping special characters. */ - tailMB = pppAppend(c, tailMB, &pc->outACCM); - } - } - - /* Add FCS and trailing flag. */ - c = ~fcsOut & 0xFF; - tailMB = pppAppend(c, tailMB, &pc->outACCM); - c = (~fcsOut >> 8) & 0xFF; - tailMB = pppAppend(c, tailMB, &pc->outACCM); - tailMB = pppAppend(PPP_FLAG, tailMB, NULL); - - /* If we failed to complete the packet, throw it away. */ - if (!tailMB) { - PPPDEBUG((LOG_WARNING, - "pppifOutput[%d]: Alloc err - dropping proto=%d\n", - pd, protocol)); - pbuf_free(headMB); -#if LINK_STATS - lwip_stats.link.memerr++; - lwip_stats.link.drop++; -#endif - return ERR_MEM; - } - - /* Send it. */ - PPPDEBUG((LOG_INFO, "pppifOutput[%d]: proto=0x%04X\n", pd, protocol)); - - nPut(pc, headMB); - - return ERR_OK; -} - -/* Get and set parameters for the given connection. - * Return 0 on success, an error code on failure. */ -int pppIOCtl(int pd, int cmd, void *arg) -{ - PPPControl *pc = &pppControl[pd]; - int st = 0; - - if (pd < 0 || pd >= NUM_PPP) - st = PPPERR_PARAM; - else { - switch(cmd) { - case PPPCTLG_UPSTATUS: /* Get the PPP up status. */ - if (arg) - *(int *)arg = (int)(pc->if_up); - else - st = PPPERR_PARAM; - break; - case PPPCTLS_ERRCODE: /* Set the PPP error code. */ - if (arg) - pc->errCode = *(int *)arg; - else - st = PPPERR_PARAM; - break; - case PPPCTLG_ERRCODE: /* Get the PPP error code. */ - if (arg) - *(int *)arg = (int)(pc->errCode); - else - st = PPPERR_PARAM; - break; - case PPPCTLG_FD: - if (arg) - *(sio_fd_t *)arg = pc->fd; - else - st = PPPERR_PARAM; - break; - default: - st = PPPERR_PARAM; - break; - } - } - - return st; -} - -/* - * Return the Maximum Transmission Unit for the given PPP connection. - */ -u_int pppMTU(int pd) -{ - PPPControl *pc = &pppControl[pd]; - u_int st; - - /* Validate parameters. */ - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) - st = 0; - else - st = pc->mtu; - - return st; -} - -/* - * Write n characters to a ppp link. - * RETURN: >= 0 Number of characters written - * -1 Failed to write to device - */ -int pppWrite(int pd, const u_char *s, int n) -{ - PPPControl *pc = &pppControl[pd]; - u_char c; - u_int fcsOut = PPP_INITFCS; - struct pbuf *headMB = NULL, *tailMB; - headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); - if (headMB == NULL) { -#if LINK_STATS - lwip_stats.link.memerr++; - lwip_stats.link.proterr++; -#endif /* LINK_STATS */ - return PPPERR_ALLOC; - } - - tailMB = headMB; - - /* If the link has been idle, we'll send a fresh flag character to - * flush any noise. */ - if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) - tailMB = pppAppend(PPP_FLAG, tailMB, NULL); - pc->lastXMit = sys_jiffies(); - - /* Load output buffer. */ - while (n-- > 0) { - c = *s++; - - /* Update FCS before checking for special characters. */ - fcsOut = PPP_FCS(fcsOut, c); - - /* Copy to output buffer escaping special characters. */ - tailMB = pppAppend(c, tailMB, &pc->outACCM); - } - - /* Add FCS and trailing flag. */ - c = ~fcsOut & 0xFF; - tailMB = pppAppend(c, tailMB, &pc->outACCM); - c = (~fcsOut >> 8) & 0xFF; - tailMB = pppAppend(c, tailMB, &pc->outACCM); - tailMB = pppAppend(PPP_FLAG, tailMB, NULL); - - /* If we failed to complete the packet, throw it away. - * Otherwise send it. */ - if (!tailMB) { - PPPDEBUG((LOG_WARNING, - "pppWrite[%d]: Alloc err - dropping pbuf len=%d\n", pd, headMB->len)); -/* "pppWrite[%d]: Alloc err - dropping %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */ - pbuf_free(headMB); -#if LINK_STATS - lwip_stats.link.memerr++; - lwip_stats.link.proterr++; -#endif /* LINK_STATS */ - return PPPERR_ALLOC; - } - - PPPDEBUG((LOG_INFO, "pppWrite[%d]: len=%d\n", pd, headMB->len)); -/* "pppWrite[%d]: %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */ - nPut(pc, headMB); - - return PPPERR_NONE; -} - -/* - * ppp_send_config - configure the transmit characteristics of - * the ppp interface. - */ -void ppp_send_config( - int unit, - int mtu, - u32_t asyncmap, - int pcomp, - int accomp -) -{ - PPPControl *pc = &pppControl[unit]; - int i; - - pc->mtu = mtu; - pc->pcomp = pcomp; - pc->accomp = accomp; - - /* Load the ACCM bits for the 32 control codes. */ - for (i = 0; i < 32/8; i++) - pc->outACCM[i] = (u_char)((asyncmap >> (8 * i)) & 0xFF); - PPPDEBUG((LOG_INFO, "ppp_send_config[%d]: outACCM=%X %X %X %X\n", - unit, - pc->outACCM[0], pc->outACCM[1], pc->outACCM[2], pc->outACCM[3])); -} - - -/* - * ppp_set_xaccm - set the extended transmit ACCM for the interface. - */ -void ppp_set_xaccm(int unit, ext_accm *accm) -{ - memcpy(pppControl[unit].outACCM, accm, sizeof(ext_accm)); - PPPDEBUG((LOG_INFO, "ppp_set_xaccm[%d]: outACCM=%X %X %X %X\n", - unit, - pppControl[unit].outACCM[0], - pppControl[unit].outACCM[1], - pppControl[unit].outACCM[2], - pppControl[unit].outACCM[3])); -} - - -/* - * ppp_recv_config - configure the receive-side characteristics of - * the ppp interface. - */ -void ppp_recv_config( - int unit, - int mru, - u32_t asyncmap, - int pcomp, - int accomp -) -{ - PPPControl *pc = &pppControl[unit]; - int i; - - (void)accomp; - (void)pcomp; - (void)mru; - - /* Load the ACCM bits for the 32 control codes. */ - for (i = 0; i < 32 / 8; i++) - pc->inACCM[i] = (u_char)(asyncmap >> (i * 8)); - PPPDEBUG((LOG_INFO, "ppp_recv_config[%d]: inACCM=%X %X %X %X\n", - unit, - pc->inACCM[0], pc->inACCM[1], pc->inACCM[2], pc->inACCM[3])); -} - -#if 0 -/* - * ccp_test - ask kernel whether a given compression method - * is acceptable for use. Returns 1 if the method and parameters - * are OK, 0 if the method is known but the parameters are not OK - * (e.g. code size should be reduced), or -1 if the method is unknown. - */ -int ccp_test( - int unit, - int opt_len, - int for_transmit, - u_char *opt_ptr -) -{ - return 0; /* XXX Currently no compression. */ -} - -/* - * ccp_flags_set - inform kernel about the current state of CCP. - */ -void ccp_flags_set(int unit, int isopen, int isup) -{ - /* XXX */ -} - -/* - * ccp_fatal_error - returns 1 if decompression was disabled as a - * result of an error detected after decompression of a packet, - * 0 otherwise. This is necessary because of patent nonsense. - */ -int ccp_fatal_error(int unit) -{ - /* XXX */ - return 0; -} -#endif - -/* - * get_idle_time - return how long the link has been idle. - */ -int get_idle_time(int u, struct ppp_idle *ip) -{ - /* XXX */ - (void)u; - (void)ip; - - return 0; -} - - -/* - * Return user specified netmask, modified by any mask we might determine - * for address `addr' (in network byte order). - * Here we scan through the system's list of interfaces, looking for - * any non-point-to-point interfaces which might appear to be on the same - * network as `addr'. If we find any, we OR in their netmask to the - * user-specified netmask. - */ -u32_t GetMask(u32_t addr) -{ - u32_t mask, nmask; - - htonl(addr); - if (IN_CLASSA(addr)) /* determine network mask for address class */ - nmask = IN_CLASSA_NET; - else if (IN_CLASSB(addr)) - nmask = IN_CLASSB_NET; - else - nmask = IN_CLASSC_NET; - /* class D nets are disallowed by bad_ip_adrs */ - mask = subnetMask | htonl(nmask); - - /* XXX - * Scan through the system's network interfaces. - * Get each netmask and OR them into our mask. - */ - - return mask; -} - -/* - * sifvjcomp - config tcp header compression - */ -int sifvjcomp( - int pd, - int vjcomp, - int cidcomp, - int maxcid -) -{ -#if VJ_SUPPORT > 0 - PPPControl *pc = &pppControl[pd]; - - pc->vjEnabled = vjcomp; - pc->vjComp.compressSlot = cidcomp; - pc->vjComp.maxSlotIndex = maxcid; - PPPDEBUG((LOG_INFO, "sifvjcomp: VJ compress enable=%d slot=%d max slot=%d\n", - vjcomp, cidcomp, maxcid)); -#endif - - return 0; -} - -/* - * pppifNetifInit - netif init callback - */ -static err_t pppifNetifInit(struct netif *netif) -{ - netif->name[0] = 'p'; - netif->name[1] = 'p'; - netif->output = pppifOutput; - netif->mtu = pppMTU((int)netif->state); - return ERR_OK; -} - - -/* - * sifup - Config the interface up and enable IP packets to pass. - */ -int sifup(int pd) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); - } else { - netif_remove(&pc->netif); - if (netif_add(&pc->netif, &pc->addrs.our_ipaddr, &pc->addrs.netmask, &pc->addrs.his_ipaddr, (void *)pd, pppifNetifInit, ip_input)) { - pc->if_up = 1; - pc->errCode = PPPERR_NONE; - - PPPDEBUG((LOG_DEBUG, "sifup: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); - if(pc->linkStatusCB) - pc->linkStatusCB(pc->linkStatusCtx, pc->errCode, &pc->addrs); - } else { - st = 0; - PPPDEBUG((LOG_ERR, "sifup[%d]: netif_add failed\n", pd)); - } - } - - return st; -} - -/* - * sifnpmode - Set the mode for handling packets for a given NP. - */ -int sifnpmode(int u, int proto, enum NPmode mode) -{ - (void)u; - (void)proto; - (void)mode; - return 0; -} - -/* - * sifdown - Config the interface down and disable IP. - */ -int sifdown(int pd) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifdown[%d]: bad parms\n", pd)); - } else { - pc->if_up = 0; - netif_remove(&pc->netif); - PPPDEBUG((LOG_DEBUG, "sifdown: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); - if(pc->linkStatusCB) - pc->linkStatusCB(pc->linkStatusCtx, PPPERR_CONNECT, NULL); - } - return st; -} - -/* - * sifaddr - Config the interface IP addresses and netmask. - */ -int sifaddr( - int pd, /* Interface unit ??? */ - u32_t o, /* Our IP address ??? */ - u32_t h, /* His IP address ??? */ - u32_t m, /* IP subnet mask ??? */ - u32_t ns1, /* Primary DNS */ - u32_t ns2 /* Secondary DNS */ -) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); - } else { - memcpy(&pc->addrs.our_ipaddr, &o, sizeof(o)); - memcpy(&pc->addrs.his_ipaddr, &h, sizeof(h)); - memcpy(&pc->addrs.netmask, &m, sizeof(m)); - memcpy(&pc->addrs.dns1, &ns1, sizeof(ns1)); - memcpy(&pc->addrs.dns2, &ns2, sizeof(ns2)); - } - return st; -} - -/* - * cifaddr - Clear the interface IP addresses, and delete routes - * through the interface if possible. - */ -int cifaddr( - int pd, /* Interface unit ??? */ - u32_t o, /* Our IP address ??? */ - u32_t h /* IP broadcast address ??? */ -) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - (void)o; - (void)h; - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); - } else { - IP4_ADDR(&pc->addrs.our_ipaddr, 0,0,0,0); - IP4_ADDR(&pc->addrs.his_ipaddr, 0,0,0,0); - IP4_ADDR(&pc->addrs.netmask, 255,255,255,0); - IP4_ADDR(&pc->addrs.dns1, 0,0,0,0); - IP4_ADDR(&pc->addrs.dns2, 0,0,0,0); - } - return st; -} - -/* - * sifdefaultroute - assign a default route through the address given. - */ -int sifdefaultroute(int pd, u32_t l, u32_t g) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - (void)l; - (void)g; - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); - } else { - netif_set_default(&pc->netif); - } - - /* TODO: check how PPP handled the netMask, previously not set by ipSetDefault */ - - return st; -} - -/* - * cifdefaultroute - delete a default route through the address given. - */ -int cifdefaultroute(int pd, u32_t l, u32_t g) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - (void)l; - (void)g; - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); - } else { - netif_set_default(NULL); - } - - return st; -} - -void -pppMainWakeup(int pd) -{ - PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d\n", pd)); - sio_read_abort(pppControl[pd].fd); -} - -/* these callbacks are necessary because lcp_* functions - must be called in the same context as pppInput(), - namely the tcpip_thread(), essentially because - they manipulate timeouts which are thread-private -*/ - -static void -pppStartCB(void *arg) -{ - int pd = (int)arg; - - PPPDEBUG((LOG_DEBUG, "pppStartCB: unit %d\n", pd)); - lcp_lowerup(pd); - lcp_open(pd); /* Start protocol */ -} - -static void -pppStopCB(void *arg) -{ - int pd = (int)arg; - - PPPDEBUG((LOG_DEBUG, "pppStopCB: unit %d\n", pd)); - lcp_close(pd, "User request"); -} - -static void -pppHupCB(void *arg) -{ - int pd = (int)arg; - - PPPDEBUG((LOG_DEBUG, "pppHupCB: unit %d\n", pd)); - lcp_lowerdown(pd); - link_terminated(pd); -} -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ -/* The main PPP process function. This implements the state machine according - * to section 4 of RFC 1661: The Point-To-Point Protocol. */ -static void pppMain(void *arg) -{ - int pd = (int)arg; - struct pbuf *p; - PPPControl* pc; - - pc = &pppControl[pd]; - - p = pbuf_alloc(PBUF_RAW, PPP_MRU+PPP_HDRLEN, PBUF_RAM); - if(!p) { - LWIP_ASSERT("p != NULL", p); - pc->errCode = PPPERR_ALLOC; - goto out; - } - - /* - * Start the connection and handle incoming events (packet or timeout). - */ - PPPDEBUG((LOG_INFO, "pppMain: unit %d: Connecting\n", pd)); - tcpip_callback(pppStartCB, arg); - while (lcp_phase[pd] != PHASE_DEAD) { - if (pc->kill_link) { - PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d kill_link -> pppStopCB\n", pd)); - pc->errCode = PPPERR_USER; - /* This will leave us at PHASE_DEAD. */ - tcpip_callback(pppStopCB, arg); - pc->kill_link = 0; - } - else if (pc->sig_hup) { - PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sig_hup -> pppHupCB\n", pd)); - pc->sig_hup = 0; - tcpip_callback(pppHupCB, arg); - } else { - int c = sio_read(pc->fd, p->payload, p->len); - if(c > 0) { - pppInProc(pd, p->payload, c); - } else { - PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sio_read len=%d returned %d\n", pd, p->len, c)); - sys_msleep(1); /* give other tasks a chance to run */ - } - } - } - PPPDEBUG((LOG_INFO, "pppMain: unit %d: PHASE_DEAD\n", pd)); - pbuf_free(p); - -out: - PPPDEBUG((LOG_DEBUG, "pppMain: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); - if(pc->linkStatusCB) - pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL); - - pc->openFlag = 0; -} - -static struct pbuf *pppSingleBuf(struct pbuf *p) -{ - struct pbuf *q, *b; - u_char *pl; - - if(p->tot_len == p->len) - return p; - - q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); - if(!q) { - PPPDEBUG((LOG_ERR, - "pppSingleBuf: unable to alloc new buf (%d)\n", p->tot_len)); - return p; /* live dangerously */ - } - - for(b = p, pl = q->payload; b != NULL; b = b->next) { - memcpy(pl, b->payload, b->len); - pl += b->len; - } - - pbuf_free(p); - - return q; -} - -struct pppInputHeader { - int unit; - u16_t proto; -}; - -/* - * Pass the processed input packet to the appropriate handler. - * This function and all handlers run in the context of the tcpip_thread - */ -static void pppInput(void *arg) -{ - struct pbuf *nb = (struct pbuf *)arg; - u16_t protocol; - int pd; - - pd = ((struct pppInputHeader *)nb->payload)->unit; - protocol = ((struct pppInputHeader *)nb->payload)->proto; - - pbuf_header(nb, -(int)sizeof(struct pppInputHeader)); - -#if LINK_STATS - lwip_stats.link.recv++; -#endif /* LINK_STATS */ - - /* - * Toss all non-LCP packets unless LCP is OPEN. - * Until we get past the authentication phase, toss all packets - * except LCP, LQR and authentication packets. - */ - if((lcp_phase[pd] <= PHASE_AUTHENTICATE) && (protocol != PPP_LCP)) { - if(!((protocol == PPP_LQR) || (protocol == PPP_PAP) || (protocol == PPP_CHAP)) || - (lcp_phase[pd] != PHASE_AUTHENTICATE)) { - PPPDEBUG((LOG_INFO, "pppInput: discarding proto 0x%04X in phase %d\n", protocol, lcp_phase[pd])); - goto drop; - } - } - - switch(protocol) { - case PPP_VJC_COMP: /* VJ compressed TCP */ -#if VJ_SUPPORT > 0 - PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_comp in pbuf len=%d\n", pd, nb->len)); - /* - * Clip off the VJ header and prepend the rebuilt TCP/IP header and - * pass the result to IP. - */ - if (vj_uncompress_tcp(&nb, &pppControl[pd].vjComp) >= 0) { - pppControl[pd].netif.input(nb, &pppControl[pd].netif); - return; - } - /* Something's wrong so drop it. */ - PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ compressed\n", pd)); -#else - /* No handler for this protocol so drop the packet. */ - PPPDEBUG((LOG_INFO, "pppInput[%d]: drop VJ Comp in %d:%s\n", pd, nb->len, nb->payload)); -#endif /* VJ_SUPPORT > 0 */ - break; - case PPP_VJC_UNCOMP: /* VJ uncompressed TCP */ -#if VJ_SUPPORT > 0 - PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_un in pbuf len=%d\n", pd, nb->len)); - /* - * Process the TCP/IP header for VJ header compression and then pass - * the packet to IP. - */ - if (vj_uncompress_uncomp(nb, &pppControl[pd].vjComp) >= 0) { - pppControl[pd].netif.input(nb, &pppControl[pd].netif); - return; - } - /* Something's wrong so drop it. */ - PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ uncompressed\n", pd)); -#else - /* No handler for this protocol so drop the packet. */ - PPPDEBUG((LOG_INFO, - "pppInput[%d]: drop VJ UnComp in %d:.*H\n", - pd, nb->len, LWIP_MIN(nb->len * 2, 40), nb->payload)); -#endif /* VJ_SUPPORT > 0 */ - break; - case PPP_IP: /* Internet Protocol */ - PPPDEBUG((LOG_INFO, "pppInput[%d]: ip in pbuf len=%d\n", pd, nb->len)); - pppControl[pd].netif.input(nb, &pppControl[pd].netif); - return; - default: - { - struct protent *protp; - int i; - - /* - * Upcall the proper protocol input routine. - */ - for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { - if (protp->protocol == protocol && protp->enabled_flag) { - PPPDEBUG((LOG_INFO, "pppInput[%d]: %s len=%d\n", pd, protp->name, nb->len)); - nb = pppSingleBuf(nb); - (*protp->input)(pd, nb->payload, nb->len); - goto out; - } - } - - /* No handler for this protocol so reject the packet. */ - PPPDEBUG((LOG_INFO, "pppInput[%d]: rejecting unsupported proto 0x%04X len=%d\n", pd, protocol, nb->len)); - pbuf_header(nb, sizeof(protocol)); -#if BYTE_ORDER == LITTLE_ENDIAN - protocol = htons(protocol); - memcpy(nb->payload, &protocol, sizeof(protocol)); -#endif - lcp_sprotrej(pd, nb->payload, nb->len); - } - break; - } - -drop: -#if LINK_STATS - lwip_stats.link.drop++; -#endif - -out: - pbuf_free(nb); - return; -} - - -/* - * Drop the input packet. - */ -static void pppDrop(PPPControl *pc) -{ - if (pc->inHead != NULL) { -#if 0 - PPPDEBUG((LOG_INFO, "pppDrop: %d:%.*H\n", pc->inHead->len, min(60, pc->inHead->len * 2), pc->inHead->payload)); -#endif - PPPDEBUG((LOG_INFO, "pppDrop: pbuf len=%d\n", pc->inHead->len)); - if (pc->inTail && (pc->inTail != pc->inHead)) - pbuf_free(pc->inTail); - pbuf_free(pc->inHead); - pc->inHead = NULL; - pc->inTail = NULL; - } -#if VJ_SUPPORT > 0 - vj_uncompress_err(&pc->vjComp); -#endif - -#if LINK_STATS - lwip_stats.link.drop++; -#endif /* LINK_STATS */ -} - - -/* - * Process a received octet string. - */ -static void pppInProc(int pd, u_char *s, int l) -{ - PPPControl *pc = &pppControl[pd]; - struct pbuf *nextNBuf; - u_char curChar; - - PPPDEBUG((LOG_DEBUG, "pppInProc[%d]: got %d bytes\n", pd, l)); - while (l-- > 0) { - curChar = *s++; - - /* Handle special characters. */ - if (ESCAPE_P(pc->inACCM, curChar)) { - /* Check for escape sequences. */ - /* XXX Note that this does not handle an escaped 0x5d character which - * would appear as an escape character. Since this is an ASCII ']' - * and there is no reason that I know of to escape it, I won't complicate - * the code to handle this case. GLL */ - if (curChar == PPP_ESCAPE) - pc->inEscaped = 1; - /* Check for the flag character. */ - else if (curChar == PPP_FLAG) { - /* If this is just an extra flag character, ignore it. */ - if (pc->inState <= PDADDRESS) - ; - /* If we haven't received the packet header, drop what has come in. */ - else if (pc->inState < PDDATA) { - PPPDEBUG((LOG_WARNING, - "pppInProc[%d]: Dropping incomplete packet %d\n", - pd, pc->inState)); -#if LINK_STATS - lwip_stats.link.lenerr++; -#endif - pppDrop(pc); - } - /* If the fcs is invalid, drop the packet. */ - else if (pc->inFCS != PPP_GOODFCS) { - PPPDEBUG((LOG_INFO, - "pppInProc[%d]: Dropping bad fcs 0x%04X proto=0x%04X\n", - pd, pc->inFCS, pc->inProtocol)); -#if LINK_STATS - lwip_stats.link.chkerr++; -#endif - pppDrop(pc); - } - /* Otherwise it's a good packet so pass it on. */ - else { - - /* Trim off the checksum. */ - if(pc->inTail->len >= 2) { - pc->inTail->len -= 2; - - pc->inTail->tot_len = pc->inTail->len; - if (pc->inTail != pc->inHead) { - pbuf_cat(pc->inHead, pc->inTail); - } - } else { - pc->inTail->tot_len = pc->inTail->len; - if (pc->inTail != pc->inHead) { - pbuf_cat(pc->inHead, pc->inTail); - } - - pbuf_realloc(pc->inHead, pc->inHead->tot_len - 2); - } - - /* Dispatch the packet thereby consuming it. */ - if(tcpip_callback(pppInput, pc->inHead) != ERR_OK) { - PPPDEBUG((LOG_ERR, - "pppInProc[%d]: tcpip_callback() failed, dropping packet\n", pd)); - pbuf_free(pc->inHead); -#if LINK_STATS - lwip_stats.link.drop++; -#endif - } - pc->inHead = NULL; - pc->inTail = NULL; - } - - /* Prepare for a new packet. */ - pc->inFCS = PPP_INITFCS; - pc->inState = PDADDRESS; - pc->inEscaped = 0; - } - /* Other characters are usually control characters that may have - * been inserted by the physical layer so here we just drop them. */ - else { - PPPDEBUG((LOG_WARNING, - "pppInProc[%d]: Dropping ACCM char <%d>\n", pd, curChar)); - } - } - /* Process other characters. */ - else { - /* Unencode escaped characters. */ - if (pc->inEscaped) { - pc->inEscaped = 0; - curChar ^= PPP_TRANS; - } - - /* Process character relative to current state. */ - switch(pc->inState) { - case PDIDLE: /* Idle state - waiting. */ - /* Drop the character if it's not 0xff - * we would have processed a flag character above. */ - if (curChar != PPP_ALLSTATIONS) { - break; - } - - /* Fall through */ - case PDSTART: /* Process start flag. */ - /* Prepare for a new packet. */ - pc->inFCS = PPP_INITFCS; - - /* Fall through */ - case PDADDRESS: /* Process address field. */ - if (curChar == PPP_ALLSTATIONS) { - pc->inState = PDCONTROL; - break; - } - /* Else assume compressed address and control fields so - * fall through to get the protocol... */ - case PDCONTROL: /* Process control field. */ - /* If we don't get a valid control code, restart. */ - if (curChar == PPP_UI) { - pc->inState = PDPROTOCOL1; - break; - } -#if 0 - else { - PPPDEBUG((LOG_WARNING, - "pppInProc[%d]: Invalid control <%d>\n", pd, curChar)); - pc->inState = PDSTART; - } -#endif - case PDPROTOCOL1: /* Process protocol field 1. */ - /* If the lower bit is set, this is the end of the protocol - * field. */ - if (curChar & 1) { - pc->inProtocol = curChar; - pc->inState = PDDATA; - } - else { - pc->inProtocol = (u_int)curChar << 8; - pc->inState = PDPROTOCOL2; - } - break; - case PDPROTOCOL2: /* Process protocol field 2. */ - pc->inProtocol |= curChar; - pc->inState = PDDATA; - break; - case PDDATA: /* Process data byte. */ - /* Make space to receive processed data. */ - if (pc->inTail == NULL || pc->inTail->len == PBUF_POOL_BUFSIZE) { - if(pc->inTail) { - pc->inTail->tot_len = pc->inTail->len; - if (pc->inTail != pc->inHead) { - pbuf_cat(pc->inHead, pc->inTail); - } - } - /* If we haven't started a packet, we need a packet header. */ - nextNBuf = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); - if (nextNBuf == NULL) { - /* No free buffers. Drop the input packet and let the - * higher layers deal with it. Continue processing - * the received pbuf chain in case a new packet starts. */ - PPPDEBUG((LOG_ERR, "pppInProc[%d]: NO FREE MBUFS!\n", pd)); -#if LINK_STATS - lwip_stats.link.memerr++; -#endif /* LINK_STATS */ - pppDrop(pc); - pc->inState = PDSTART; /* Wait for flag sequence. */ - break; - } - if (pc->inHead == NULL) { - struct pppInputHeader *pih = nextNBuf->payload; - - pih->unit = pd; - pih->proto = pc->inProtocol; - - nextNBuf->len += sizeof(*pih); - - pc->inHead = nextNBuf; - } - pc->inTail = nextNBuf; - } - /* Load character into buffer. */ - ((u_char*)pc->inTail->payload)[pc->inTail->len++] = curChar; - break; - } - - /* update the frame check sequence number. */ - pc->inFCS = PPP_FCS(pc->inFCS, curChar); - } - } - avRandomize(); -} - -#endif /* PPP_SUPPORT */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/ppp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/ppp.h deleted file mode 100644 index dbe12171e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/ppp.h +++ /dev/null @@ -1,446 +0,0 @@ -/***************************************************************************** -* ppp.h - Network Point to Point Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-11-05 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD codes. -*****************************************************************************/ - -#ifndef PPP_H -#define PPP_H - -#include "lwip/opt.h" - -#if PPP_SUPPORT > 0 -#include "lwip/sio.h" -#include "lwip/api.h" -#include "lwip/sockets.h" -#include "lwip/stats.h" -#include "lwip/mem.h" -#include "lwip/tcpip.h" -#include "lwip/netif.h" - -/* - * pppd.h - PPP daemon global declarations. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - */ -/* - * ppp_defs.h - PPP definitions. - * - * Copyright (c) 1994 The Australian National University. - * All rights reserved. - * - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, provided that the above copyright - * notice appears in all copies. This software is provided without any - * warranty, express or implied. The Australian National University - * makes no representations about the suitability of this software for - * any purpose. - * - * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY - * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES - * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF - * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS - * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO - * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, - * OR MODIFICATIONS. - */ - -#define TIMEOUT(f, a, t) sys_untimeout((f), (a)), sys_timeout((t)*1000, (f), (a)) -#define UNTIMEOUT(f, a) sys_untimeout((f), (a)) - - -# ifndef __u_char_defined - -/* Type definitions for BSD code. */ -typedef unsigned long u_long; -typedef unsigned int u_int; -typedef unsigned short u_short; -typedef unsigned char u_char; - -#endif - -/* - * Constants and structures defined by the internet system, - * Per RFC 790, September 1981, and numerous additions. - */ - -/* - * The basic PPP frame. - */ -#define PPP_HDRLEN 4 /* octets for standard ppp header */ -#define PPP_FCSLEN 2 /* octets for FCS */ - - -/* - * Significant octet values. - */ -#define PPP_ALLSTATIONS 0xff /* All-Stations broadcast address */ -#define PPP_UI 0x03 /* Unnumbered Information */ -#define PPP_FLAG 0x7e /* Flag Sequence */ -#define PPP_ESCAPE 0x7d /* Asynchronous Control Escape */ -#define PPP_TRANS 0x20 /* Asynchronous transparency modifier */ - -/* - * Protocol field values. - */ -#define PPP_IP 0x21 /* Internet Protocol */ -#define PPP_AT 0x29 /* AppleTalk Protocol */ -#define PPP_VJC_COMP 0x2d /* VJ compressed TCP */ -#define PPP_VJC_UNCOMP 0x2f /* VJ uncompressed TCP */ -#define PPP_COMP 0xfd /* compressed packet */ -#define PPP_IPCP 0x8021 /* IP Control Protocol */ -#define PPP_ATCP 0x8029 /* AppleTalk Control Protocol */ -#define PPP_CCP 0x80fd /* Compression Control Protocol */ -#define PPP_LCP 0xc021 /* Link Control Protocol */ -#define PPP_PAP 0xc023 /* Password Authentication Protocol */ -#define PPP_LQR 0xc025 /* Link Quality Report protocol */ -#define PPP_CHAP 0xc223 /* Cryptographic Handshake Auth. Protocol */ -#define PPP_CBCP 0xc029 /* Callback Control Protocol */ - -/* - * Values for FCS calculations. - */ -#define PPP_INITFCS 0xffff /* Initial FCS value */ -#define PPP_GOODFCS 0xf0b8 /* Good final FCS value */ -#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff]) - -/* - * Extended asyncmap - allows any character to be escaped. - */ -typedef u_char ext_accm[32]; - -/* - * What to do with network protocol (NP) packets. - */ -enum NPmode { - NPMODE_PASS, /* pass the packet through */ - NPMODE_DROP, /* silently drop the packet */ - NPMODE_ERROR, /* return an error */ - NPMODE_QUEUE /* save it up for later. */ -}; - -/* - * Inline versions of get/put char/short/long. - * Pointer is advanced; we assume that both arguments - * are lvalues and will already be in registers. - * cp MUST be u_char *. - */ -#define GETCHAR(c, cp) { \ - (c) = *(cp)++; \ -} -#define PUTCHAR(c, cp) { \ - *(cp)++ = (u_char) (c); \ -} - - -#define GETSHORT(s, cp) { \ - (s) = *(cp)++ << 8; \ - (s) |= *(cp)++; \ -} -#define PUTSHORT(s, cp) { \ - *(cp)++ = (u_char) ((s) >> 8); \ - *(cp)++ = (u_char) (s); \ -} - -#define GETLONG(l, cp) { \ - (l) = *(cp)++ << 8; \ - (l) |= *(cp)++; (l) <<= 8; \ - (l) |= *(cp)++; (l) <<= 8; \ - (l) |= *(cp)++; \ -} -#define PUTLONG(l, cp) { \ - *(cp)++ = (u_char) ((l) >> 24); \ - *(cp)++ = (u_char) ((l) >> 16); \ - *(cp)++ = (u_char) ((l) >> 8); \ - *(cp)++ = (u_char) (l); \ -} - - -#define INCPTR(n, cp) ((cp) += (n)) -#define DECPTR(n, cp) ((cp) -= (n)) - -#define BCMP(s0, s1, l) memcmp((u_char *)(s0), (u_char *)(s1), (l)) -#define BCOPY(s, d, l) memcpy((d), (s), (l)) -#define BZERO(s, n) memset(s, 0, n) -#if PPP_DEBUG -#define PRINTMSG(m, l) { m[l] = '\0'; ppp_trace(LOG_INFO, "Remote message: %s\n", m); } -#else -#define PRINTMSG(m, l) -#endif - -/* - * MAKEHEADER - Add PPP Header fields to a packet. - */ -#define MAKEHEADER(p, t) { \ - PUTCHAR(PPP_ALLSTATIONS, p); \ - PUTCHAR(PPP_UI, p); \ - PUTSHORT(t, p); } - -/************************* -*** PUBLIC DEFINITIONS *** -*************************/ - -/* Error codes. */ -#define PPPERR_NONE 0 /* No error. */ -#define PPPERR_PARAM -1 /* Invalid parameter. */ -#define PPPERR_OPEN -2 /* Unable to open PPP session. */ -#define PPPERR_DEVICE -3 /* Invalid I/O device for PPP. */ -#define PPPERR_ALLOC -4 /* Unable to allocate resources. */ -#define PPPERR_USER -5 /* User interrupt. */ -#define PPPERR_CONNECT -6 /* Connection lost. */ -#define PPPERR_AUTHFAIL -7 /* Failed authentication challenge. */ -#define PPPERR_PROTOCOL -8 /* Failed to meet protocol. */ - -/* - * PPP IOCTL commands. - */ -/* - * Get the up status - 0 for down, non-zero for up. The argument must - * point to an int. - */ -#define PPPCTLG_UPSTATUS 100 /* Get the up status - 0 down else up */ -#define PPPCTLS_ERRCODE 101 /* Set the error code */ -#define PPPCTLG_ERRCODE 102 /* Get the error code */ -#define PPPCTLG_FD 103 /* Get the fd associated with the ppp */ - -/************************ -*** PUBLIC DATA TYPES *** -************************/ - -/* - * The following struct gives the addresses of procedures to call - * for a particular protocol. - */ -struct protent { - u_short protocol; /* PPP protocol number */ - /* Initialization procedure */ - void (*init) (int unit); - /* Process a received packet */ - void (*input) (int unit, u_char *pkt, int len); - /* Process a received protocol-reject */ - void (*protrej) (int unit); - /* Lower layer has come up */ - void (*lowerup) (int unit); - /* Lower layer has gone down */ - void (*lowerdown) (int unit); - /* Open the protocol */ - void (*open) (int unit); - /* Close the protocol */ - void (*close) (int unit, char *reason); -#if 0 - /* Print a packet in readable form */ - int (*printpkt) (u_char *pkt, int len, - void (*printer) (void *, char *, ...), - void *arg); - /* Process a received data packet */ - void (*datainput) (int unit, u_char *pkt, int len); -#endif - int enabled_flag; /* 0 iff protocol is disabled */ - char *name; /* Text name of protocol */ -#if 0 - /* Check requested options, assign defaults */ - void (*check_options) (u_long); - /* Configure interface for demand-dial */ - int (*demand_conf) (int unit); - /* Say whether to bring up link for this pkt */ - int (*active_pkt) (u_char *pkt, int len); -#endif -}; - -/* - * The following structure records the time in seconds since - * the last NP packet was sent or received. - */ -struct ppp_idle { - u_short xmit_idle; /* seconds since last NP packet sent */ - u_short recv_idle; /* seconds since last NP packet received */ -}; - -struct ppp_settings { - - u_int disable_defaultip : 1; /* Don't use hostname for default IP addrs */ - u_int auth_required : 1; /* Peer is required to authenticate */ - u_int explicit_remote : 1; /* remote_name specified with remotename opt */ - u_int refuse_pap : 1; /* Don't wanna auth. ourselves with PAP */ - u_int refuse_chap : 1; /* Don't wanna auth. ourselves with CHAP */ - u_int usehostname : 1; /* Use hostname for our_name */ - u_int usepeerdns : 1; /* Ask peer for DNS adds */ - - u_short idle_time_limit; /* Shut down link if idle for this long */ - int maxconnect; /* Maximum connect time (seconds) */ - - char user[MAXNAMELEN + 1];/* Username for PAP */ - char passwd[MAXSECRETLEN + 1]; /* Password for PAP, secret for CHAP */ - char our_name[MAXNAMELEN + 1]; /* Our name for authentication purposes */ - char remote_name[MAXNAMELEN + 1]; /* Peer's name for authentication */ -}; - -struct ppp_addrs { - struct ip_addr our_ipaddr, his_ipaddr, netmask, dns1, dns2; -}; - -/***************************** -*** PUBLIC DATA STRUCTURES *** -*****************************/ -/* Buffers for outgoing packets. */ -extern u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN]; - -extern struct ppp_settings ppp_settings; - -extern struct protent *ppp_protocols[];/* Table of pointers to supported protocols */ - - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ - -/* Initialize the PPP subsystem. */ -void pppInit(void); - -/* Warning: Using PPPAUTHTYPE_ANY might have security consequences. - * RFC 1994 says: - * - * In practice, within or associated with each PPP server, there is a - * database which associates "user" names with authentication - * information ("secrets"). It is not anticipated that a particular - * named user would be authenticated by multiple methods. This would - * make the user vulnerable to attacks which negotiate the least secure - * method from among a set (such as PAP rather than CHAP). If the same - * secret was used, PAP would reveal the secret to be used later with - * CHAP. - * - * Instead, for each user name there should be an indication of exactly - * one method used to authenticate that user name. If a user needs to - * make use of different authentication methods under different - * circumstances, then distinct user names SHOULD be employed, each of - * which identifies exactly one authentication method. - * - */ -enum pppAuthType { - PPPAUTHTYPE_NONE, - PPPAUTHTYPE_ANY, - PPPAUTHTYPE_PAP, - PPPAUTHTYPE_CHAP -}; - -void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd); - -/* - * Open a new PPP connection using the given I/O device. - * This initializes the PPP control block but does not - * attempt to negotiate the LCP session. - * Return a new PPP connection descriptor on success or - * an error code (negative) on failure. - */ -int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx); - -/* - * Close a PPP connection and release the descriptor. - * Any outstanding packets in the queues are dropped. - * Return 0 on success, an error code on failure. - */ -int pppClose(int pd); - -/* - * Indicate to the PPP process that the line has disconnected. - */ -void pppSigHUP(int pd); - -/* - * Get and set parameters for the given connection. - * Return 0 on success, an error code on failure. - */ -int pppIOCtl(int pd, int cmd, void *arg); - -/* - * Return the Maximum Transmission Unit for the given PPP connection. - */ -u_int pppMTU(int pd); - -/* - * Write n characters to a ppp link. - * RETURN: >= 0 Number of characters written - * -1 Failed to write to device - */ -int pppWrite(int pd, const u_char *s, int n); - -void pppMainWakeup(int pd); - -/* Configure i/f transmit parameters */ -void ppp_send_config (int, int, u32_t, int, int); -/* Set extended transmit ACCM */ -void ppp_set_xaccm (int, ext_accm *); -/* Configure i/f receive parameters */ -void ppp_recv_config (int, int, u32_t, int, int); -/* Find out how long link has been idle */ -int get_idle_time (int, struct ppp_idle *); - -/* Configure VJ TCP header compression */ -int sifvjcomp (int, int, int, int); -/* Configure i/f down (for IP) */ -int sifup (int); -/* Set mode for handling packets for proto */ -int sifnpmode (int u, int proto, enum NPmode mode); -/* Configure i/f down (for IP) */ -int sifdown (int); -/* Configure IP addresses for i/f */ -int sifaddr (int, u32_t, u32_t, u32_t, u32_t, u32_t); -/* Reset i/f IP addresses */ -int cifaddr (int, u32_t, u32_t); -/* Create default route through i/f */ -int sifdefaultroute (int, u32_t, u32_t); -/* Delete default route through i/f */ -int cifdefaultroute (int, u32_t, u32_t); - -/* Get appropriate netmask for address */ -u32_t GetMask (u32_t); - -#endif /* PPP_SUPPORT */ - -#endif /* PPP_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/pppdebug.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/pppdebug.h deleted file mode 100644 index de1478cee..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/pppdebug.h +++ /dev/null @@ -1,89 +0,0 @@ -/***************************************************************************** -* pppdebug.h - System debugging utilities. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1998 Global Election Systems Inc. -* portions Copyright (c) 2001 by Cognizant Pty Ltd. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY (please don't use tabs!) -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 98-07-29 Guy Lancaster , Global Election Systems Inc. -* Original. -* -***************************************************************************** -*/ -#ifndef PPPDEBUG_H -#define PPPDEBUG_H - -/************************ -*** PUBLIC DATA TYPES *** -************************/ -/* Trace levels. */ -typedef enum { - LOG_CRITICAL = 0, - LOG_ERR = 1, - LOG_NOTICE = 2, - LOG_WARNING = 3, - LOG_INFO = 5, - LOG_DETAIL = 6, - LOG_DEBUG = 7 -} LogCodes; - - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ -/* - * ppp_trace - a form of printf to send tracing information to stderr - */ -void ppp_trace(int level, const char *format,...); - -#if PPP_DEBUG > 0 - -#define AUTHDEBUG(a) ppp_trace a -#define IPCPDEBUG(a) ppp_trace a -#define UPAPDEBUG(a) ppp_trace a -#define LCPDEBUG(a) ppp_trace a -#define FSMDEBUG(a) ppp_trace a -#define CHAPDEBUG(a) ppp_trace a -#define PPPDEBUG(a) ppp_trace a - -#define TRACELCP 1 - -#else - -#define AUTHDEBUG(a) -#define IPCPDEBUG(a) -#define UPAPDEBUG(a) -#define LCPDEBUG(a) -#define FSMDEBUG(a) -#define CHAPDEBUG(a) - -#define PPPDEBUG(a) - -#define TRACELCP 0 - -#endif - -#endif /* PPPDEBUG_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/randm.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/randm.c deleted file mode 100644 index 05eeb4410..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/randm.c +++ /dev/null @@ -1,242 +0,0 @@ -/***************************************************************************** -* randm.c - Random number generator program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* Copyright (c) 1998 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 98-06-03 Guy Lancaster , Global Election Systems Inc. -* Extracted from avos. -*****************************************************************************/ - -#include "ppp.h" -#if PPP_SUPPORT > 0 -#include "md5.h" -#include "randm.h" - -#include "pppdebug.h" - - -#if MD5_SUPPORT>0 /* this module depends on MD5 */ -#define RANDPOOLSZ 16 /* Bytes stored in the pool of randomness. */ - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -static char randPool[RANDPOOLSZ]; /* Pool of randomness. */ -static long randCount = 0; /* Pseudo-random incrementer */ - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * Initialize the random number generator. - * - * Since this is to be called on power up, we don't have much - * system randomess to work with. Here all we use is the - * real-time clock. We'll accumulate more randomness as soon - * as things start happening. - */ -void avRandomInit() -{ - avChurnRand(NULL, 0); -} - -/* - * Churn the randomness pool on a random event. Call this early and often - * on random and semi-random system events to build randomness in time for - * usage. For randomly timed events, pass a null pointer and a zero length - * and this will use the system timer and other sources to add randomness. - * If new random data is available, pass a pointer to that and it will be - * included. - * - * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427 - */ -void avChurnRand(char *randData, u32_t randLen) -{ - MD5_CTX md5; - -/* ppp_trace(LOG_INFO, "churnRand: %u@%P\n", randLen, randData); */ - MD5Init(&md5); - MD5Update(&md5, (u_char *)randPool, sizeof(randPool)); - if (randData) - MD5Update(&md5, (u_char *)randData, randLen); - else { - struct { - /* INCLUDE fields for any system sources of randomness */ - char foobar; - } sysData; - - /* Load sysData fields here. */ - ; - MD5Update(&md5, (u_char *)&sysData, sizeof(sysData)); - } - MD5Final((u_char *)randPool, &md5); -/* ppp_trace(LOG_INFO, "churnRand: -> 0\n"); */ -} - -/* - * Use the random pool to generate random data. This degrades to pseudo - * random when used faster than randomness is supplied using churnRand(). - * Note: It's important that there be sufficient randomness in randPool - * before this is called for otherwise the range of the result may be - * narrow enough to make a search feasible. - * - * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427 - * - * XXX Why does he not just call churnRand() for each block? Probably - * so that you don't ever publish the seed which could possibly help - * predict future values. - * XXX Why don't we preserve md5 between blocks and just update it with - * randCount each time? Probably there is a weakness but I wish that - * it was documented. - */ -void avGenRand(char *buf, u32_t bufLen) -{ - MD5_CTX md5; - u_char tmp[16]; - u32_t n; - - while (bufLen > 0) { - n = LWIP_MIN(bufLen, RANDPOOLSZ); - MD5Init(&md5); - MD5Update(&md5, (u_char *)randPool, sizeof(randPool)); - MD5Update(&md5, (u_char *)&randCount, sizeof(randCount)); - MD5Final(tmp, &md5); - randCount++; - memcpy(buf, tmp, n); - buf += n; - bufLen -= n; - } -} - -/* - * Return a new random number. - */ -u32_t avRandom() -{ - u32_t newRand; - - avGenRand((char *)&newRand, sizeof(newRand)); - - return newRand; -} - -#else /* MD5_SUPPORT */ - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -static int avRandomized = 0; /* Set when truely randomized. */ -static u32_t avRandomSeed = 0; /* Seed used for random number generation. */ - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * Initialize the random number generator. - * - * Here we attempt to compute a random number seed but even if - * it isn't random, we'll randomize it later. - * - * The current method uses the fields from the real time clock, - * the idle process counter, the millisecond counter, and the - * hardware timer tick counter. When this is invoked - * in startup(), then the idle counter and timer values may - * repeat after each boot and the real time clock may not be - * operational. Thus we call it again on the first random - * event. - */ -void avRandomInit() -{ -#if 0 - /* Get a pointer into the last 4 bytes of clockBuf. */ - u32_t *lptr1 = (u32_t *)((char *)&clockBuf[3]); - - /* - * Initialize our seed using the real-time clock, the idle - * counter, the millisecond timer, and the hardware timer - * tick counter. The real-time clock and the hardware - * tick counter are the best sources of randomness but - * since the tick counter is only 16 bit (and truncated - * at that), the idle counter and millisecond timer - * (which may be small values) are added to help - * randomize the lower 16 bits of the seed. - */ - readClk(); - avRandomSeed += *(u32_t *)clockBuf + *lptr1 + OSIdleCtr - + ppp_mtime() + ((u32_t)TM1 << 16) + TM1; -#else - avRandomSeed += sys_jiffies(); /* XXX */ -#endif - - /* Initialize the Borland random number generator. */ - srand((unsigned)avRandomSeed); -} - -/* - * Randomize our random seed value. Here we use the fact that - * this function is called at *truely random* times by the polling - * and network functions. Here we only get 16 bits of new random - * value but we use the previous value to randomize the other 16 - * bits. - */ -void avRandomize(void) -{ - static u32_t last_jiffies; - - if (!avRandomized) { - avRandomized = !0; - avRandomInit(); - /* The initialization function also updates the seed. */ - } else { -/* avRandomSeed += (avRandomSeed << 16) + TM1; */ - avRandomSeed += (sys_jiffies() - last_jiffies); /* XXX */ - } - last_jiffies = sys_jiffies(); -} - -/* - * Return a new random number. - * Here we use the Borland rand() function to supply a pseudo random - * number which we make truely random by combining it with our own - * seed which is randomized by truely random events. - * Thus the numbers will be truely random unless there have been no - * operator or network events in which case it will be pseudo random - * seeded by the real time clock. - */ -u32_t avRandom() -{ - return ((((u32_t)rand() << 16) + rand()) + avRandomSeed); -} - - - -#endif /* MD5_SUPPORT */ -#endif /* PPP_SUPPORT */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/randm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/randm.h deleted file mode 100644 index baa42f0c2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/randm.h +++ /dev/null @@ -1,81 +0,0 @@ -/***************************************************************************** -* randm.h - Random number generator header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* Copyright (c) 1998 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 98-05-29 Guy Lancaster , Global Election Systems Inc. -* Extracted from avos. -*****************************************************************************/ - -#ifndef RANDM_H -#define RANDM_H - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ -/* - * Initialize the random number generator. - */ -void avRandomInit(void); - -/* - * Churn the randomness pool on a random event. Call this early and often - * on random and semi-random system events to build randomness in time for - * usage. For randomly timed events, pass a null pointer and a zero length - * and this will use the system timer and other sources to add randomness. - * If new random data is available, pass a pointer to that and it will be - * included. - */ -void avChurnRand(char *randData, u32_t randLen); - -/* - * Randomize our random seed value. To be called for truely random events - * such as user operations and network traffic. - */ -#if MD5_SUPPORT -#define avRandomize() avChurnRand(NULL, 0) -#else -void avRandomize(void); -#endif - -/* - * Use the random pool to generate random data. This degrades to pseudo - * random when used faster than randomness is supplied using churnRand(). - * Thus it's important to make sure that the results of this are not - * published directly because one could predict the next result to at - * least some degree. Also, it's important to get a good seed before - * the first use. - */ -void avGenRand(char *buf, u32_t bufLen); - -/* - * Return a new random number. - */ -u32_t avRandom(void); - - -#endif /* RANDM_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/vj.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/vj.c deleted file mode 100644 index 0636ee11b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/vj.c +++ /dev/null @@ -1,633 +0,0 @@ -/* - * Routines to compress and uncompess tcp packets (for transmission - * over low speed serial lines. - * - * Copyright (c) 1989 Regents of the University of California. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by the University of California, Berkeley. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989: - * - Initial distribution. - * - * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au, - * so that the entire packet being decompressed doesn't have - * to be in contiguous memory (just the compressed header). - * - * Modified March 1998 by Guy Lancaster, glanca@gesn.com, - * for a 16 bit processor. - */ - -#include - -#include "ppp.h" -#include "vj.h" -#include "pppdebug.h" - -#if VJ_SUPPORT > 0 - -#if LINK_STATS -#define INCR(counter) ++comp->stats.counter -#else -#define INCR(counter) -#endif - -#if defined(NO_CHAR_BITFIELDS) -#define getip_hl(base) ((base).ip_hl_v&0xf) -#define getth_off(base) (((base).th_x2_off&0xf0)>>4) -#else -#define getip_hl(base) ((base).ip_hl) -#define getth_off(base) ((base).th_off) -#endif - -void vj_compress_init(struct vjcompress *comp) -{ - register u_int i; - register struct cstate *tstate = comp->tstate; - -#if MAX_SLOTS == 0 - memset((char *)comp, 0, sizeof(*comp)); -#endif - comp->maxSlotIndex = MAX_SLOTS - 1; - comp->compressSlot = 0; /* Disable slot ID compression by default. */ - for (i = MAX_SLOTS - 1; i > 0; --i) { - tstate[i].cs_id = i; - tstate[i].cs_next = &tstate[i - 1]; - } - tstate[0].cs_next = &tstate[MAX_SLOTS - 1]; - tstate[0].cs_id = 0; - comp->last_cs = &tstate[0]; - comp->last_recv = 255; - comp->last_xmit = 255; - comp->flags = VJF_TOSS; -} - - -/* ENCODE encodes a number that is known to be non-zero. ENCODEZ - * checks for zero (since zero has to be encoded in the long, 3 byte - * form). - */ -#define ENCODE(n) { \ - if ((u_short)(n) >= 256) { \ - *cp++ = 0; \ - cp[1] = (n); \ - cp[0] = (n) >> 8; \ - cp += 2; \ - } else { \ - *cp++ = (n); \ - } \ -} -#define ENCODEZ(n) { \ - if ((u_short)(n) >= 256 || (u_short)(n) == 0) { \ - *cp++ = 0; \ - cp[1] = (n); \ - cp[0] = (n) >> 8; \ - cp += 2; \ - } else { \ - *cp++ = (n); \ - } \ -} - -#define DECODEL(f) { \ - if (*cp == 0) {\ - u32_t tmp = ntohl(f) + ((cp[1] << 8) | cp[2]); \ - (f) = htonl(tmp); \ - cp += 3; \ - } else { \ - u32_t tmp = ntohl(f) + (u32_t)*cp++; \ - (f) = htonl(tmp); \ - } \ -} - -#define DECODES(f) { \ - if (*cp == 0) {\ - u_short tmp = ntohs(f) + (((u_short)cp[1] << 8) | cp[2]); \ - (f) = htons(tmp); \ - cp += 3; \ - } else { \ - u_short tmp = ntohs(f) + (u_short)*cp++; \ - (f) = htons(tmp); \ - } \ -} - -#define DECODEU(f) { \ - if (*cp == 0) {\ - (f) = htons(((u_short)cp[1] << 8) | cp[2]); \ - cp += 3; \ - } else { \ - (f) = htons((u_short)*cp++); \ - } \ -} - -/* - * vj_compress_tcp - Attempt to do Van Jacobsen header compression on a - * packet. This assumes that nb and comp are not null and that the first - * buffer of the chain contains a valid IP header. - * Return the VJ type code indicating whether or not the packet was - * compressed. - */ -u_int vj_compress_tcp( - struct vjcompress *comp, - struct pbuf *pb -) -{ - register struct ip *ip = (struct ip *)pb->payload; - register struct cstate *cs = comp->last_cs->cs_next; - register u_short hlen = getip_hl(*ip); - register struct tcphdr *oth; - register struct tcphdr *th; - register u_short deltaS, deltaA; - register u_long deltaL; - register u_int changes = 0; - u_char new_seq[16]; - register u_char *cp = new_seq; - - /* - * Check that the packet is IP proto TCP. - */ - if (ip->ip_p != IPPROTO_TCP) - return (TYPE_IP); - - /* - * Bail if this is an IP fragment or if the TCP packet isn't - * `compressible' (i.e., ACK isn't set or some other control bit is - * set). - */ - if ((ip->ip_off & htons(0x3fff)) || pb->tot_len < 40) - return (TYPE_IP); - th = (struct tcphdr *)&((long *)ip)[hlen]; - if ((th->th_flags & (TCP_SYN|TCP_FIN|TCP_RST|TCP_ACK)) != TCP_ACK) - return (TYPE_IP); - - /* - * Packet is compressible -- we're going to send either a - * COMPRESSED_TCP or UNCOMPRESSED_TCP packet. Either way we need - * to locate (or create) the connection state. Special case the - * most recently used connection since it's most likely to be used - * again & we don't have to do any reordering if it's used. - */ - INCR(vjs_packets); - if (ip->ip_src.s_addr != cs->cs_ip.ip_src.s_addr - || ip->ip_dst.s_addr != cs->cs_ip.ip_dst.s_addr - || *(long *)th != ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) { - /* - * Wasn't the first -- search for it. - * - * States are kept in a circularly linked list with - * last_cs pointing to the end of the list. The - * list is kept in lru order by moving a state to the - * head of the list whenever it is referenced. Since - * the list is short and, empirically, the connection - * we want is almost always near the front, we locate - * states via linear search. If we don't find a state - * for the datagram, the oldest state is (re-)used. - */ - register struct cstate *lcs; - register struct cstate *lastcs = comp->last_cs; - - do { - lcs = cs; cs = cs->cs_next; - INCR(vjs_searches); - if (ip->ip_src.s_addr == cs->cs_ip.ip_src.s_addr - && ip->ip_dst.s_addr == cs->cs_ip.ip_dst.s_addr - && *(long *)th == ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) - goto found; - } while (cs != lastcs); - - /* - * Didn't find it -- re-use oldest cstate. Send an - * uncompressed packet that tells the other side what - * connection number we're using for this conversation. - * Note that since the state list is circular, the oldest - * state points to the newest and we only need to set - * last_cs to update the lru linkage. - */ - INCR(vjs_misses); - comp->last_cs = lcs; - hlen += getth_off(*th); - hlen <<= 2; - /* Check that the IP/TCP headers are contained in the first buffer. */ - if (hlen > pb->len) - return (TYPE_IP); - goto uncompressed; - - found: - /* - * Found it -- move to the front on the connection list. - */ - if (cs == lastcs) - comp->last_cs = lcs; - else { - lcs->cs_next = cs->cs_next; - cs->cs_next = lastcs->cs_next; - lastcs->cs_next = cs; - } - } - - oth = (struct tcphdr *)&((long *)&cs->cs_ip)[hlen]; - deltaS = hlen; - hlen += getth_off(*th); - hlen <<= 2; - /* Check that the IP/TCP headers are contained in the first buffer. */ - if (hlen > pb->len) { - PPPDEBUG((LOG_INFO, "vj_compress_tcp: header len %d spans buffers\n", - hlen)); - return (TYPE_IP); - } - - /* - * Make sure that only what we expect to change changed. The first - * line of the `if' checks the IP protocol version, header length & - * type of service. The 2nd line checks the "Don't fragment" bit. - * The 3rd line checks the time-to-live and protocol (the protocol - * check is unnecessary but costless). The 4th line checks the TCP - * header length. The 5th line checks IP options, if any. The 6th - * line checks TCP options, if any. If any of these things are - * different between the previous & current datagram, we send the - * current datagram `uncompressed'. - */ - if (((u_short *)ip)[0] != ((u_short *)&cs->cs_ip)[0] - || ((u_short *)ip)[3] != ((u_short *)&cs->cs_ip)[3] - || ((u_short *)ip)[4] != ((u_short *)&cs->cs_ip)[4] - || getth_off(*th) != getth_off(*oth) - || (deltaS > 5 && BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2)) - || (getth_off(*th) > 5 && BCMP(th + 1, oth + 1, (getth_off(*th) - 5) << 2))) - goto uncompressed; - - /* - * Figure out which of the changing fields changed. The - * receiver expects changes in the order: urgent, window, - * ack, seq (the order minimizes the number of temporaries - * needed in this section of code). - */ - if (th->th_flags & TCP_URG) { - deltaS = ntohs(th->th_urp); - ENCODEZ(deltaS); - changes |= NEW_U; - } else if (th->th_urp != oth->th_urp) - /* argh! URG not set but urp changed -- a sensible - * implementation should never do this but RFC793 - * doesn't prohibit the change so we have to deal - * with it. */ - goto uncompressed; - - if ((deltaS = (u_short)(ntohs(th->th_win) - ntohs(oth->th_win))) != 0) { - ENCODE(deltaS); - changes |= NEW_W; - } - - if ((deltaL = ntohl(th->th_ack) - ntohl(oth->th_ack)) != 0) { - if (deltaL > 0xffff) - goto uncompressed; - deltaA = (u_short)deltaL; - ENCODE(deltaA); - changes |= NEW_A; - } - - if ((deltaL = ntohl(th->th_seq) - ntohl(oth->th_seq)) != 0) { - if (deltaL > 0xffff) - goto uncompressed; - deltaS = (u_short)deltaL; - ENCODE(deltaS); - changes |= NEW_S; - } - - switch(changes) { - - case 0: - /* - * Nothing changed. If this packet contains data and the - * last one didn't, this is probably a data packet following - * an ack (normal on an interactive connection) and we send - * it compressed. Otherwise it's probably a retransmit, - * retransmitted ack or window probe. Send it uncompressed - * in case the other side missed the compressed version. - */ - if (ip->ip_len != cs->cs_ip.ip_len && - ntohs(cs->cs_ip.ip_len) == hlen) - break; - - /* (fall through) */ - - case SPECIAL_I: - case SPECIAL_D: - /* - * actual changes match one of our special case encodings -- - * send packet uncompressed. - */ - goto uncompressed; - - case NEW_S|NEW_A: - if (deltaS == deltaA && deltaS == ntohs(cs->cs_ip.ip_len) - hlen) { - /* special case for echoed terminal traffic */ - changes = SPECIAL_I; - cp = new_seq; - } - break; - - case NEW_S: - if (deltaS == ntohs(cs->cs_ip.ip_len) - hlen) { - /* special case for data xfer */ - changes = SPECIAL_D; - cp = new_seq; - } - break; - } - - deltaS = (u_short)(ntohs(ip->ip_id) - ntohs(cs->cs_ip.ip_id)); - if (deltaS != 1) { - ENCODEZ(deltaS); - changes |= NEW_I; - } - if (th->th_flags & TCP_PSH) - changes |= TCP_PUSH_BIT; - /* - * Grab the cksum before we overwrite it below. Then update our - * state with this packet's header. - */ - deltaA = ntohs(th->th_sum); - BCOPY(ip, &cs->cs_ip, hlen); - - /* - * We want to use the original packet as our compressed packet. - * (cp - new_seq) is the number of bytes we need for compressed - * sequence numbers. In addition we need one byte for the change - * mask, one for the connection id and two for the tcp checksum. - * So, (cp - new_seq) + 4 bytes of header are needed. hlen is how - * many bytes of the original packet to toss so subtract the two to - * get the new packet size. - */ - deltaS = (u_short)(cp - new_seq); - if (!comp->compressSlot || comp->last_xmit != cs->cs_id) { - comp->last_xmit = cs->cs_id; - hlen -= deltaS + 4; - pbuf_header(pb, -hlen); - cp = (u_char *)pb->payload; - *cp++ = changes | NEW_C; - *cp++ = cs->cs_id; - } else { - hlen -= deltaS + 3; - pbuf_header(pb, -hlen); - cp = (u_char *)pb->payload; - *cp++ = changes; - } - *cp++ = deltaA >> 8; - *cp++ = deltaA; - BCOPY(new_seq, cp, deltaS); - INCR(vjs_compressed); - return (TYPE_COMPRESSED_TCP); - - /* - * Update connection state cs & send uncompressed packet (that is, - * a regular ip/tcp packet but with the 'conversation id' we hope - * to use on future compressed packets in the protocol field). - */ -uncompressed: - BCOPY(ip, &cs->cs_ip, hlen); - ip->ip_p = cs->cs_id; - comp->last_xmit = cs->cs_id; - return (TYPE_UNCOMPRESSED_TCP); -} - -/* - * Called when we may have missed a packet. - */ -void vj_uncompress_err(struct vjcompress *comp) -{ - comp->flags |= VJF_TOSS; - INCR(vjs_errorin); -} - -/* - * "Uncompress" a packet of type TYPE_UNCOMPRESSED_TCP. - * Return 0 on success, -1 on failure. - */ -int vj_uncompress_uncomp( - struct pbuf *nb, - struct vjcompress *comp -) -{ - register u_int hlen; - register struct cstate *cs; - register struct ip *ip; - - ip = (struct ip *)nb->payload; - hlen = getip_hl(*ip) << 2; - if (ip->ip_p >= MAX_SLOTS - || hlen + sizeof(struct tcphdr) > nb->len - || (hlen += getth_off(*((struct tcphdr *)&((char *)ip)[hlen])) << 2) - > nb->len - || hlen > MAX_HDR) { - PPPDEBUG((LOG_INFO, "vj_uncompress_uncomp: bad cid=%d, hlen=%d buflen=%d\n", - ip->ip_p, hlen, nb->len)); - comp->flags |= VJF_TOSS; - INCR(vjs_errorin); - return -1; - } - cs = &comp->rstate[comp->last_recv = ip->ip_p]; - comp->flags &=~ VJF_TOSS; - ip->ip_p = IPPROTO_TCP; - BCOPY(ip, &cs->cs_ip, hlen); - cs->cs_hlen = hlen; - INCR(vjs_uncompressedin); - return 0; -} - -/* - * Uncompress a packet of type TYPE_COMPRESSED_TCP. - * The packet is composed of a buffer chain and the first buffer - * must contain an accurate chain length. - * The first buffer must include the entire compressed TCP/IP header. - * This procedure replaces the compressed header with the uncompressed - * header and returns the length of the VJ header. - */ -int vj_uncompress_tcp( - struct pbuf **nb, - struct vjcompress *comp -) -{ - u_char *cp; - struct tcphdr *th; - struct cstate *cs; - u_short *bp; - struct pbuf *n0 = *nb; - u32_t tmp; - u_int vjlen, hlen, changes; - - INCR(vjs_compressedin); - cp = (u_char *)n0->payload; - changes = *cp++; - if (changes & NEW_C) { - /* - * Make sure the state index is in range, then grab the state. - * If we have a good state index, clear the 'discard' flag. - */ - if (*cp >= MAX_SLOTS) { - PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: bad cid=%d\n", *cp)); - goto bad; - } - - comp->flags &=~ VJF_TOSS; - comp->last_recv = *cp++; - } else { - /* - * this packet has an implicit state index. If we've - * had a line error since the last time we got an - * explicit state index, we have to toss the packet. - */ - if (comp->flags & VJF_TOSS) { - PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: tossing\n")); - INCR(vjs_tossed); - return (-1); - } - } - cs = &comp->rstate[comp->last_recv]; - hlen = getip_hl(cs->cs_ip) << 2; - th = (struct tcphdr *)&((u_char *)&cs->cs_ip)[hlen]; - th->th_sum = htons((*cp << 8) | cp[1]); - cp += 2; - if (changes & TCP_PUSH_BIT) - th->th_flags |= TCP_PSH; - else - th->th_flags &=~ TCP_PSH; - - switch (changes & SPECIALS_MASK) { - case SPECIAL_I: - { - register u32_t i = ntohs(cs->cs_ip.ip_len) - cs->cs_hlen; - /* some compilers can't nest inline assembler.. */ - tmp = ntohl(th->th_ack) + i; - th->th_ack = htonl(tmp); - tmp = ntohl(th->th_seq) + i; - th->th_seq = htonl(tmp); - } - break; - - case SPECIAL_D: - /* some compilers can't nest inline assembler.. */ - tmp = ntohl(th->th_seq) + ntohs(cs->cs_ip.ip_len) - cs->cs_hlen; - th->th_seq = htonl(tmp); - break; - - default: - if (changes & NEW_U) { - th->th_flags |= TCP_URG; - DECODEU(th->th_urp); - } else - th->th_flags &=~ TCP_URG; - if (changes & NEW_W) - DECODES(th->th_win); - if (changes & NEW_A) - DECODEL(th->th_ack); - if (changes & NEW_S) - DECODEL(th->th_seq); - break; - } - if (changes & NEW_I) { - DECODES(cs->cs_ip.ip_id); - } else { - cs->cs_ip.ip_id = ntohs(cs->cs_ip.ip_id) + 1; - cs->cs_ip.ip_id = htons(cs->cs_ip.ip_id); - } - - /* - * At this point, cp points to the first byte of data in the - * packet. Fill in the IP total length and update the IP - * header checksum. - */ - vjlen = (u_short)(cp - (u_char*)n0->payload); - if (n0->len < vjlen) { - /* - * We must have dropped some characters (crc should detect - * this but the old slip framing won't) - */ - PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: head buffer %d too short %d\n", - n0->len, vjlen)); - goto bad; - } - -#if BYTE_ORDER == LITTLE_ENDIAN - tmp = n0->tot_len - vjlen + cs->cs_hlen; - cs->cs_ip.ip_len = htons(tmp); -#else - cs->cs_ip.ip_len = htons(n0->tot_len - vjlen + cs->cs_hlen); -#endif - - /* recompute the ip header checksum */ - bp = (u_short *) &cs->cs_ip; - cs->cs_ip.ip_sum = 0; - for (tmp = 0; hlen > 0; hlen -= 2) - tmp += *bp++; - tmp = (tmp & 0xffff) + (tmp >> 16); - tmp = (tmp & 0xffff) + (tmp >> 16); - cs->cs_ip.ip_sum = (u_short)(~tmp); - - /* Remove the compressed header and prepend the uncompressed header. */ - pbuf_header(n0, -vjlen); - - if(MEM_ALIGN(n0->payload) != n0->payload) { - struct pbuf *np, *q; - u8_t *bufptr; - - np = pbuf_alloc(PBUF_RAW, n0->len + cs->cs_hlen, PBUF_POOL); - if(!np) { - PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: realign failed\n")); - *nb = NULL; - goto bad; - } - - pbuf_header(np, -cs->cs_hlen); - - bufptr = n0->payload; - for(q = np; q != NULL; q = q->next) { - memcpy(q->payload, bufptr, q->len); - bufptr += q->len; - } - - if(n0->next) { - pbuf_chain(np, n0->next); - pbuf_dechain(n0); - } - pbuf_free(n0); - n0 = np; - } - - if(pbuf_header(n0, cs->cs_hlen)) { - struct pbuf *np; - - LWIP_ASSERT("vj_uncompress_tcp: cs->cs_hlen <= PBUF_POOL_BUFSIZE", cs->cs_hlen <= PBUF_POOL_BUFSIZE); - np = pbuf_alloc(PBUF_RAW, cs->cs_hlen, PBUF_POOL); - if(!np) { - PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: prepend failed\n")); - *nb = NULL; - goto bad; - } - pbuf_cat(np, n0); - n0 = np; - } - LWIP_ASSERT("n0->len >= cs->cs_hlen", n0->len >= cs->cs_hlen); - memcpy(n0->payload, &cs->cs_ip, cs->cs_hlen); - - *nb = n0; - - return vjlen; - -bad: - comp->flags |= VJF_TOSS; - INCR(vjs_errorin); - return (-1); -} - -#endif - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/vj.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/vj.h deleted file mode 100644 index 252d0f5aa..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/vj.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Definitions for tcp compression routines. - * - * $Id$ - * - * Copyright (c) 1989 Regents of the University of California. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by the University of California, Berkeley. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989: - * - Initial distribution. - */ - -#ifndef VJ_H -#define VJ_H - -#include "vjbsdhdr.h" - -#define MAX_SLOTS 16 /* must be > 2 and < 256 */ -#define MAX_HDR 128 - -/* - * Compressed packet format: - * - * The first octet contains the packet type (top 3 bits), TCP - * 'push' bit, and flags that indicate which of the 4 TCP sequence - * numbers have changed (bottom 5 bits). The next octet is a - * conversation number that associates a saved IP/TCP header with - * the compressed packet. The next two octets are the TCP checksum - * from the original datagram. The next 0 to 15 octets are - * sequence number changes, one change per bit set in the header - * (there may be no changes and there are two special cases where - * the receiver implicitly knows what changed -- see below). - * - * There are 5 numbers which can change (they are always inserted - * in the following order): TCP urgent pointer, window, - * acknowlegement, sequence number and IP ID. (The urgent pointer - * is different from the others in that its value is sent, not the - * change in value.) Since typical use of SLIP links is biased - * toward small packets (see comments on MTU/MSS below), changes - * use a variable length coding with one octet for numbers in the - * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the - * range 256 - 65535 or 0. (If the change in sequence number or - * ack is more than 65535, an uncompressed packet is sent.) - */ - -/* - * Packet types (must not conflict with IP protocol version) - * - * The top nibble of the first octet is the packet type. There are - * three possible types: IP (not proto TCP or tcp with one of the - * control flags set); uncompressed TCP (a normal IP/TCP packet but - * with the 8-bit protocol field replaced by an 8-bit connection id -- - * this type of packet syncs the sender & receiver); and compressed - * TCP (described above). - * - * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and - * is logically part of the 4-bit "changes" field that follows. Top - * three bits are actual packet type. For backward compatibility - * and in the interest of conserving bits, numbers are chosen so the - * IP protocol version number (4) which normally appears in this nibble - * means "IP packet". - */ - -/* packet types */ -#define TYPE_IP 0x40 -#define TYPE_UNCOMPRESSED_TCP 0x70 -#define TYPE_COMPRESSED_TCP 0x80 -#define TYPE_ERROR 0x00 - -/* Bits in first octet of compressed packet */ -#define NEW_C 0x40 /* flag bits for what changed in a packet */ -#define NEW_I 0x20 -#define NEW_S 0x08 -#define NEW_A 0x04 -#define NEW_W 0x02 -#define NEW_U 0x01 - -/* reserved, special-case values of above */ -#define SPECIAL_I (NEW_S|NEW_W|NEW_U) /* echoed interactive traffic */ -#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U) /* unidirectional data */ -#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U) - -#define TCP_PUSH_BIT 0x10 - - -/* - * "state" data for each active tcp conversation on the wire. This is - * basically a copy of the entire IP/TCP header from the last packet - * we saw from the conversation together with a small identifier - * the transmit & receive ends of the line use to locate saved header. - */ -struct cstate { - struct cstate *cs_next; /* next most recently used state (xmit only) */ - u_short cs_hlen; /* size of hdr (receive only) */ - u_char cs_id; /* connection # associated with this state */ - u_char cs_filler; - union { - char csu_hdr[MAX_HDR]; - struct ip csu_ip; /* ip/tcp hdr from most recent packet */ - } vjcs_u; -}; -#define cs_ip vjcs_u.csu_ip -#define cs_hdr vjcs_u.csu_hdr - - -struct vjstat { - unsigned long vjs_packets; /* outbound packets */ - unsigned long vjs_compressed; /* outbound compressed packets */ - unsigned long vjs_searches; /* searches for connection state */ - unsigned long vjs_misses; /* times couldn't find conn. state */ - unsigned long vjs_uncompressedin; /* inbound uncompressed packets */ - unsigned long vjs_compressedin; /* inbound compressed packets */ - unsigned long vjs_errorin; /* inbound unknown type packets */ - unsigned long vjs_tossed; /* inbound packets tossed because of error */ -}; - -/* - * all the state data for one serial line (we need one of these per line). - */ -struct vjcompress { - struct cstate *last_cs; /* most recently used tstate */ - u_char last_recv; /* last rcvd conn. id */ - u_char last_xmit; /* last sent conn. id */ - u_short flags; - u_char maxSlotIndex; - u_char compressSlot; /* Flag indicating OK to compress slot ID. */ -#if LINK_STATS - struct vjstat stats; -#endif - struct cstate tstate[MAX_SLOTS]; /* xmit connection states */ - struct cstate rstate[MAX_SLOTS]; /* receive connection states */ -}; - -/* flag values */ -#define VJF_TOSS 1U /* tossing rcvd frames because of input err */ - -extern void vj_compress_init (struct vjcompress *comp); -extern u_int vj_compress_tcp (struct vjcompress *comp, struct pbuf *pb); -extern void vj_uncompress_err (struct vjcompress *comp); -extern int vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp); -extern int vj_uncompress_tcp(struct pbuf **nb, struct vjcompress *comp); - -#endif /* VJ_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/vjbsdhdr.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/vjbsdhdr.h deleted file mode 100644 index a089352ad..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/ppp/vjbsdhdr.h +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef VJBSDHDR_H -#define VJBSDHDR_H - -#include "lwip/tcp.h" - - -/* - * Structure of an internet header, naked of options. - * - * We declare ip_len and ip_off to be short, rather than u_short - * pragmatically since otherwise unsigned comparisons can result - * against negative integers quite easily, and fail in subtle ways. - */ -PACK_STRUCT_BEGIN -struct ip -{ -#if defined(NO_CHAR_BITFIELDS) - u_char ip_hl_v; /* bug in GCC for mips means the bitfield stuff will sometimes break - so we use a char for both and get round it with macro's instead... */ -#else -#if BYTE_ORDER == LITTLE_ENDIAN - unsigned ip_hl:4, /* header length */ - ip_v:4; /* version */ -#elif BYTE_ORDER == BIG_ENDIAN - unsigned ip_v:4, /* version */ - ip_hl:4; /* header length */ -#else - COMPLAIN - NO BYTE ORDER SELECTED! -#endif -#endif - u_char ip_tos; /* type of service */ - u_short ip_len; /* total length */ - u_short ip_id; /* identification */ - u_short ip_off; /* fragment offset field */ -#define IP_DF 0x4000 /* dont fragment flag */ -#define IP_MF 0x2000 /* more fragments flag */ -#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ - u_char ip_ttl; /* time to live */ - u_char ip_p; /* protocol */ - u_short ip_sum; /* checksum */ - struct in_addr ip_src,ip_dst; /* source and dest address */ -}; -PACK_STRUCT_END - -typedef u32_t tcp_seq; - -/* - * TCP header. - * Per RFC 793, September, 1981. - */ -PACK_STRUCT_BEGIN -struct tcphdr -{ - u_short th_sport; /* source port */ - u_short th_dport; /* destination port */ - tcp_seq th_seq; /* sequence number */ - tcp_seq th_ack; /* acknowledgement number */ -#if defined(NO_CHAR_BITFIELDS) - u_char th_x2_off; -#else -#if BYTE_ORDER == LITTLE_ENDIAN - unsigned th_x2:4, /* (unused) */ - th_off:4; /* data offset */ -#endif -#if BYTE_ORDER == BIG_ENDIAN - unsigned th_off:4, /* data offset */ - th_x2:4; /* (unused) */ -#endif -#endif - u_char th_flags; - u_short th_win; /* window */ - u_short th_sum; /* checksum */ - u_short th_urp; /* urgent pointer */ -}; -PACK_STRUCT_END - -#endif /* VJBSDHDR_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/slipif.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/slipif.c deleted file mode 100644 index dd8db208c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwip/src/netif/slipif.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is built upon the file: src/arch/rtxc/netif/sioslip.c - * - * Author: Magnus Ivarsson - */ - -/* - * This is an arch independent SLIP netif. The specific serial hooks must be - * provided by another file. They are sio_open, sio_recv and sio_send - */ - -#include "netif/slipif.h" -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include "lwip/stats.h" -#include "lwip/sio.h" - -#define SLIP_END 0300 -#define SLIP_ESC 0333 -#define SLIP_ESC_END 0334 -#define SLIP_ESC_ESC 0335 - -#define MAX_SIZE 1500 - -/** - * Send a pbuf doing the necessary SLIP encapsulation - * - * Uses the serial layer's sio_send() - */ -err_t -slipif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr) -{ - struct pbuf *q; - u16_t i; - u8_t c; - - /* Send pbuf out on the serial I/O device. */ - sio_send(SLIP_END, netif->state); - - for (q = p; q != NULL; q = q->next) { - for (i = 0; i < q->len; i++) { - c = ((u8_t *)q->payload)[i]; - switch (c) { - case SLIP_END: - sio_send(SLIP_ESC, netif->state); - sio_send(SLIP_ESC_END, netif->state); - break; - case SLIP_ESC: - sio_send(SLIP_ESC, netif->state); - sio_send(SLIP_ESC_ESC, netif->state); - break; - default: - sio_send(c, netif->state); - break; - } - } - } - sio_send(SLIP_END, netif->state); - return 0; -} - -/** - * Handle the incoming SLIP stream character by character - * - * Poll the serial layer by calling sio_recv() - * - * @return The IP packet when SLIP_END is received - */ -static struct pbuf * -slipif_input(struct netif *netif) -{ - u8_t c; - struct pbuf *p, *q; - u16_t recved; - u16_t i; - - q = p = NULL; - recved = i = 0; - c = 0; - - while (1) { - c = sio_recv(netif->state); - switch (c) { - case SLIP_END: - if (recved > 0) { - /* Received whole packet. */ - pbuf_realloc(q, recved); - - LINK_STATS_INC(link.recv); - - LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n")); - return q; - } - break; - - case SLIP_ESC: - c = sio_recv(netif->state); - switch (c) { - case SLIP_ESC_END: - c = SLIP_END; - break; - case SLIP_ESC_ESC: - c = SLIP_ESC; - break; - } - /* FALLTHROUGH */ - - default: - if (p == NULL) { - LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n")); - p = pbuf_alloc(PBUF_LINK, PBUF_POOL_BUFSIZE, PBUF_POOL); - - if (p == NULL) { - LINK_STATS_INC(link.drop); - LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n")); - } - - if (q != NULL) { - pbuf_cat(q, p); - } else { - q = p; - } - } - if (p != NULL && recved < MAX_SIZE) { - ((u8_t *)p->payload)[i] = c; - recved++; - i++; - if (i >= p->len) { - i = 0; - if (p->next != NULL && p->next->len > 0) - p = p->next; - else - p = NULL; - } - } - break; - } - - } - return NULL; -} - -/** - * The SLIP input thread. - * - * Feed the IP layer with incoming packets - */ -static void -slipif_loop(void *nf) -{ - struct pbuf *p; - struct netif *netif = (struct netif *)nf; - - while (1) { - p = slipif_input(netif); - netif->input(p, netif); - } -} - -/** - * SLIP netif initialization - * - * Call the arch specific sio_open and remember - * the opened device in the state field of the netif. - */ -err_t -slipif_init(struct netif *netif) -{ - - LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%"U16_F"\n", (u16_t)netif->num)); - - netif->name[0] = 's'; - netif->name[1] = 'l'; - netif->output = slipif_output; - netif->mtu = 1500; - netif->flags = NETIF_FLAG_POINTTOPOINT; - - netif->state = sio_open(netif->num); - if (!netif->state) - return ERR_IF; - - sys_thread_new(slipif_loop, netif, SLIPIF_THREAD_PRIO); - return ERR_OK; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwipopts.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwipopts.h deleted file mode 100644 index 13fd21bee..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/lwipopts.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * Modifications: Christian Walter - */ -#ifndef __LWIPOPTS_H__ -#define __LWIPOPTS_H__ - -/* ------------------------ Generic options ------------------------------- */ -#undef LWIP_NOASSERT - -#define SYS_LIGHTWEIGHT_PROT 1 -#define TCPIP_THREAD_PRIO 3 - -#define LWIP_DEBUG 1 -#define DBG_TYPES_ON ( DBG_LEVEL_WARNING | DBG_LEVEL_SEVERE | DBG_LEVEL_SERIOUS ) -#define FEC_DEBUG ( DBG_LEVEL_WARNING | DBG_ON ) - -/* ------------------------ Memory options -------------------------------- */ -/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which - lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2 - byte alignment -> define MEM_ALIGNMENT to 2. */ -#define MEM_ALIGNMENT 4 - -/* MEM_SIZE: the size of the heap memory. If the application will send -a lot of data that needs to be copied, this should be set high. */ -#define MEM_SIZE 2048 - -/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application - sends a lot of data out of ROM (or other static memory), this - should be set high. */ -#define MEMP_NUM_PBUF 16 -/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One - per active UDP "connection". */ -#define MEMP_NUM_UDP_PCB 4 -/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP - connections. */ -#define MEMP_NUM_TCP_PCB 8 -/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP - connections. */ -#define MEMP_NUM_TCP_PCB_LISTEN 8 -/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP - segments. */ -#define MEMP_NUM_TCP_SEG 16 -/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active - timeouts. */ -#define MEMP_NUM_SYS_TIMEOUT 4 - -/* The following four are used only with the sequential API and can be - set to 0 if the application only will use the raw API. */ -/* MEMP_NUM_NETBUF: the number of struct netbufs. */ -#define MEMP_NUM_NETBUF 4 -/* MEMP_NUM_NETCONN: the number of struct netconns. */ -#define MEMP_NUM_NETCONN 4 -/* MEMP_NUM_APIMSG: the number of struct api_msg, used for - communication between the TCP/IP stack and the sequential - programs. */ -#define MEMP_NUM_API_MSG 8 -/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used - for sequential API communication and incoming packets. Used in - src/api/tcpip.c. */ -#define MEMP_NUM_TCPIP_MSG 8 - -/* ---------- Pbuf options ---------- */ -/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ -#define PBUF_POOL_SIZE 64 - -/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */ -#define PBUF_POOL_BUFSIZE 512 - -/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a - link level header. */ -#define PBUF_LINK_HLEN 14 - -/* ------------------------ TCP options ----------------------------------- */ -#define LWIP_TCP 1 -#define TCP_TTL 255 - -/* Controls if TCP should queue segments that arrive out of - order. Define to 0 if your device is low on memory. */ -#define TCP_QUEUE_OOSEQ 1 - -/* TCP Maximum segment size. */ -#define TCP_MSS 512 - -/* TCP sender buffer space (bytes). */ -#define TCP_SND_BUF 512 - -/* TCP sender buffer space (pbufs). This must be at least = 2 * - TCP_SND_BUF/TCP_MSS for things to work. */ -#define TCP_SND_QUEUELEN ( 6 * TCP_SND_BUF/TCP_MSS ) - -/* TCP receive window. */ -#define TCP_WND 512 - -/* Maximum number of retransmissions of data segments. */ -#define TCP_MAXRTX 12 - -/* Maximum number of retransmissions of SYN segments. */ -#define TCP_SYNMAXRTX 4 - -/* ------------------------ ARP options ----------------------------------- */ -#define ARP_TABLE_SIZE 10 -#define ARP_QUEUEING 1 - -/* ------------------------ IP options ------------------------------------ */ -/* Define IP_FORWARD to 1 if you wish to have the ability to forward - IP packets across network interfaces. If you are going to run lwIP - on a device with only one network interface, define this to 0. */ -#define IP_FORWARD 0 - -/* If defined to 1, IP options are allowed (but not parsed). If - defined to 0, all packets with IP options are dropped. */ -#define IP_OPTIONS 1 - -/* ------------------------ ICMP options ---------------------------------- */ -#define ICMP_TTL 255 - - -/* ------------------------ DHCP options ---------------------------------- */ -/* Define LWIP_DHCP to 1 if you want DHCP configuration of - interfaces. DHCP is not implemented in lwIP 0.5.1, however, so - turning this on does currently not work. */ -#define LWIP_DHCP 0 - -/* 1 if you want to do an ARP check on the offered address - (recommended). */ -#define DHCP_DOES_ARP_CHECK 1 - -/* ------------------------ UDP options ----------------------------------- */ -#define LWIP_UDP 1 -#define UDP_TTL 255 - -/* ------------------------ Statistics options ---------------------------- */ -#define STATS - -#ifdef STATS -#define LINK_STATS 1 -#define IP_STATS 1 -#define ICMP_STATS 1 -#define UDP_STATS 1 -#define TCP_STATS 1 -#define MEM_STATS 1 -#define MEMP_STATS 1 -#define PBUF_STATS 1 -#define SYS_STATS 1 -#endif /* STATS */ - -#define LWIP_PROVIDE_ERRNO 1 - -#endif /* __LWIPOPTS_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/m5235-ram.ld b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/m5235-ram.ld deleted file mode 100644 index a5c359416..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/m5235-ram.ld +++ /dev/null @@ -1,119 +0,0 @@ -STARTUP(system/crt0.o) -INPUT(system/vector.o) -OUTPUT_ARCH(m68k) -SEARCH_DIR(.) -GROUP(-lc -lgcc) - -__DYNAMIC = 0; - -MEMORY -{ - sdram (rwx) : ORIGIN = 0x00000000, LENGTH = 0x01000000 - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 - ipsbar (rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000 - flash (rwx) : ORIGIN = 0x80000000, LENGTH = 0x00080000 -} - -PROVIDE (__stack = 0x2000FFFC); - -SECTIONS -{ - .sdram : {} > sdram - .ipsbar : {} > ipsbar - .sram (NOLOAD) : { *(.vector_ram); *(.nbuf) } > sram - .flash : {} > flash - - .text : - { - __text_start = . ; - *(.vector_rom) - . = ALIGN (0x100); - *(.text) - . = ALIGN (16); - - *(.eh_frame) - . = ALIGN (16); - - *(.gnu.linkonce.t.*) - - . = ALIGN(0x4); - __CTOR_LIST__ = .; - ___CTOR_LIST__ = .; - LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) - *(.ctors) - LONG(0) - __CTOR_END__ = .; - __DTOR_LIST__ = .; - ___DTOR_LIST__ = .; - LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) - *(.dtors) - LONG(0) - __DTOR_END__ = .; - *(.rodata) - *(.rodata.*) - *(.gcc_except_table) - - . = ALIGN(0x2); - __INIT_SECTION__ = . ; - LONG (0x4e560000) /* linkw %fp,#0 */ - *(.init) - SHORT (0x4e5e) /* unlk %fp */ - SHORT (0x4e75) /* rts */ - - __FINI_SECTION__ = . ; - LONG (0x4e560000) /* linkw %fp,#0 */ - *(.fini) - SHORT (0x4e5e) /* unlk %fp */ - SHORT (0x4e75) /* rts */ - - *(.lit) - . = ALIGN(16); - _etext = .; - etext = .; - } > sdram - - .data : - { - copy_start = .; - *(.shdata) - *(.data) - *(.gnu.linkonce.d.*) - . = ALIGN (16); - _edata = .; - copy_end = .; - } > sdram - __data_load_start = LOADADDR(.data); - __data_load_end = __data_load_start + SIZEOF(.data); - - .bss : - { - . = ALIGN(0x4); - __bss_start = . ; - *(.shbss) - *(.bss) - *(COMMON) - _end = ALIGN (0x8); - __end = _end; - } > sdram - - .stab 0 (NOLOAD) : - { - *(.stab) - } - - .stabstr 0 (NOLOAD) : - { - *(.stabstr) - } -} - -__IPSBAR = ADDR(.ipsbar); - -__SDRAM = ADDR(.sdram); -__SDRAM_SIZE = SIZEOF(.sdram); - -__SRAM = ADDR(.sram); -__SRAM_SIZE = SIZEOF(.sram); - -__FLASH = ADDR(.flash); -__FLASH_SIZE = SIZEOF(.flash); diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/m5235-rom.ld b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/m5235-rom.ld deleted file mode 100644 index 9ad0186ce..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/m5235-rom.ld +++ /dev/null @@ -1,121 +0,0 @@ -STARTUP(system/crt0.o) -INPUT(system/vector.o) -OUTPUT_ARCH(m68k) -SEARCH_DIR(.) -GROUP(-lc -lgcc) - -__DYNAMIC = 0; - -MEMORY -{ - flash (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00200000 - sdram (rwx) : ORIGIN = 0x01000000, LENGTH = 0x01000000 - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 - ipsbar (rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000 -} - -PROVIDE (__stack = 0x2000FFFC); - -SECTIONS -{ - .sdram : {} > sdram - .ipsbar : {} > ipsbar - .sram (NOLOAD) : { *(.vector_ram); *(.nbuf) } > sram - .flash : {} > flash - - .text : - { - __text_start = . ; - *(.vector_rom) - . = ALIGN (0x100); - *(.text) - . = ALIGN (16); - - *(.eh_frame) - . = ALIGN (16); - - *(.gnu.linkonce.t.*) - - . = ALIGN(0x4); - __CTOR_LIST__ = .; - ___CTOR_LIST__ = .; - LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) - *(.ctors) - LONG(0) - __CTOR_END__ = .; - __DTOR_LIST__ = .; - ___DTOR_LIST__ = .; - LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) - *(.dtors) - LONG(0) - __DTOR_END__ = .; - *(.rodata) - *(.rodata.*) - *(.gcc_except_table) - - . = ALIGN(0x2); - __INIT_SECTION__ = . ; - LONG (0x4e560000) /* linkw %fp,#0 */ - *(.init) - SHORT (0x4e5e) /* unlk %fp */ - SHORT (0x4e75) /* rts */ - - __FINI_SECTION__ = . ; - LONG (0x4e560000) /* linkw %fp,#0 */ - *(.fini) - SHORT (0x4e5e) /* unlk %fp */ - SHORT (0x4e75) /* rts */ - - *(.lit) - . = ALIGN(16); - _etext = .; - etext = .; - - } > flash - . = ALIGN(2); - - .data : AT (ADDR (.text) + SIZEOF (.text)) - { - copy_start = .; - *(.shdata) - *(.data) - *(.gnu.linkonce.d.*) - . = ALIGN (16); - _edata = .; - copy_end = .; - } > sdram - __data_load_start = LOADADDR(.data); - __data_load_end = __data_load_start + SIZEOF(.data); - - .bss : - { - . = ALIGN(0x4); - __bss_start = . ; - *(.shbss) - *(.bss) - *(COMMON) - _end = ALIGN (0x8); - __end = _end; - } > sdram - - .stab 0 (NOLOAD) : - { - *(.stab) - } - - .stabstr 0 (NOLOAD) : - { - *(.stabstr) - } -} - -__IPSBAR = ADDR(.ipsbar); - -__SDRAM = ADDR(.sdram); -__SDRAM_SIZE = SIZEOF(.sdram); - -__SRAM = ADDR(.sram); -__SRAM_SIZE = SIZEOF(.sram); - -__FLASH = ADDR(.flash); -__FLASH_SIZE = SIZEOF(.flash); diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/m5235.gdb b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/m5235.gdb deleted file mode 100644 index 545fbea31..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/m5235.gdb +++ /dev/null @@ -1,134 +0,0 @@ -set $IPSBAR = 0x40000000 - -set $DCR = $IPSBAR + 0x000040 -set $DACR0 = $IPSBAR + 0x000048 -set $DMR0 = $IPSBAR + 0x00004C - -set $CSAR0 = $IPSBAR + 0x000080 -set $CSMR0 = $IPSBAR + 0x000084 -set $CSCR0 = $IPSBAR + 0x00008A - -set $PAR_SDRAM = $IPSBAR + 0x100046 -set $PAR_AD = $IPSBAR + 0x100040 - -set $WCR = $IPSBAR + 0x140000 - -define delay - set $delay = 0 - while ($delay < 20000) - set $delay += 1 - end -end - -define delay_memsync - set $delay = 0 - while ($delay < 10000) - set $delay += 1 - end -end - -define setup-cs - # 2MB FLASH on CS0 at 0x80000000 - set *(unsigned short *)$CSAR0 = 0x00008000 - set *(unsigned long *)$CSMR0 = 0x001F0101 - set *(unsigned short *)$CSCR0 = 0x00001980 -end - -define setup-sdram - # Set PAR_SDRAM to allow SDRAM signals to be enable - set *(unsigned char *)$PAR_SDRAM = 0x3F - # Set PAR_AD to allow 32-bit SDRAM if the external boot device is 16-bit - set *(unsigned char *)$PAR_AD = 0xE1 - - # SDRAM - set *(unsigned short *)$DCR = 0x0446 - set *(unsigned long *)$DACR0 = 0x00001300 - set *(unsigned long *)$DMR0 = 0x00FC0001 - - # Set IP in DACR and init precharge. - set *(unsigned long *)$DACR0 |= 0x00000008 - set *(0x00000000) = 0xAA55AA55 - delay - - # Set RE in DACR - set *(unsigned long *)$DACR0 |= 0x00008000 - # Issue IMRS - set *(unsigned long *)$DACR0 |= 0x00000040 - set *(0x00000400) = 0xAA55AA55 - delay -end - -define setup-other - # Turn Off WCR - set *(unsigned char *)$WCR = 0x00 -end - -define setup-and-load - bdm-reset - - # Set VBR to the vector table. - set $vbr = 0x00000000 - # Set internal SRAM to start at 0x20000000 - set $rambar = 0x20000001 - - setup-other - setup-cs - setup-sdram -end - -define debug-sramtest - set $srambase = 0x20000000 - set $sramsize = 0x00010000 - set $j = 0 - printf "Testing SRAM : 0x%08X - 0x%08X\n", $srambase, ($srambase + $sramsize) - set $i = $srambase - while $i < ($srambase + $sramsize) - set *(unsigned long *)($i) = 0xAA55AA55 - delay_memsync - if 0xAA55AA55 != *(unsigned long *)$i - printf " 0x%08X = FAIL\n", $i - else - printf " 0x%08X = OK", $i - if $j % 4 == 3 - printf "\n" - end - set $j = $j + 1 - end - set $i = $i + 0x400 - end -en - -define debug-ramtest - set $sdrambase = 0x00000000 - set $sdramsize = 0x01000000 - set $j = 0 - printf "Testing SDRAM : 0x%08X - 0x%08X\n", $sdrambase, ($sdrambase + $sdramsize) - set $i = $sdrambase - while $i < ($sdrambase + $sdramsize) - set *(unsigned long *)($i) = 0xAA55AA55 - delay_memsync - if 0xAA55AA55 != *(unsigned long *)$i - printf " 0x%08X = FAIL\n", $i - else - printf " 0x%08X = OK", $i - if $j % 4 == 3 - printf "\n" - end - set $j = $j + 1 - end - set $i = $i + 0x10000 - end - printf "\n" -end - -define execute - set $pc = *(long *)0x00000004 - tbreak main - tk gdbtk_update -end - -define debug-printexception - printf "vector: %d", *(unsigned short *)$sp >> 2 &0x1F - printf "old pc: 0x%08x", *(unsigned long *)($sp + 4) - printf "old sr: 0x%02x", *(unsigned short *)($sp + 2) -end diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/port/mbconfig.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/port/mbconfig.h deleted file mode 100644 index 490edda8c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/port/mbconfig.h +++ /dev/null @@ -1,92 +0,0 @@ - /* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _MB_CONFIG_H -#define _MB_CONFIG_H - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif -/* ----------------------- Defines ------------------------------------------*/ -/*! \defgroup modbus_cfg Modbus Configuration - * - * Most modules in the protocol stack are completly optional and can be - * excluded. This is specially important if target resources are very small - * and program memory space should be saved.
- * - * All of these settings are available in the file mbconfig.h - */ -/*! \addtogroup modbus_cfg - * @{ - */ -/*! \brief If Modbus ASCII support is enabled. */ -#define MB_ASCII_ENABLED ( 0 ) -/*! \brief If Modbus RTU support is enabled. */ -#define MB_RTU_ENABLED ( 0 ) -/*! \brief If Modbus TCP support is enabled. */ -#define MB_TCP_ENABLED ( 1 ) -/*! \brief The character timeout value for Modbus ASCII. - * - * The character timeout value is not fixed for Modbus ASCII and is therefore - * a configuration option. It should be set to the maximum expected delay - * time of the network. - */ -#define MB_ASCII_TIMEOUT_SEC ( 1 ) -/*! \brief Maximum number of Modbus functions codes the protocol stack - * should support. - * - * The maximum number of supported Modbus functions must be greater than - * the sum of all enabled functions in this file and custom function - * handlers. If set to small adding more functions will fail. - */ -#define MB_FUNC_HANDLERS_MAX ( 16 ) -/*! \brief Number of bytes which should be allocated for the Report Slave ID - * command. - * - * This number limits the maximum size of the additional segment in the - * report slave id function. See eMBSetSlaveID( ) for more information on - * how to set this value. It is only used if MB_FUNC_OTHER_REP_SLAVEID_ENABLED - * is set to 1. - */ -#define MB_FUNC_OTHER_REP_SLAVEID_BUF ( 32 ) -/*! \brief If the Report Slave ID function should be enabled. */ -#define MB_FUNC_OTHER_REP_SLAVEID_ENABLED ( 1 ) -/*! \brief If the Read Input Registers function should be enabled. */ -#define MB_FUNC_READ_INPUT_ENABLED ( 1 ) -/*! \brief If the Read Holding Registers function should be enabled. */ -#define MB_FUNC_READ_HOLDING_ENABLED ( 1 ) -/*! \brief If the Write Single Register function should be enabled. */ -#define MB_FUNC_WRITE_HOLDING_ENABLED ( 1 ) -/*! \brief If the Write Multiple registers function should be enabled. */ -#define MB_FUNC_WRITE_MULTIPLE_HOLDING_ENABLED ( 1 ) -/*! \brief If the Read Coils function should be enabled. */ -#define MB_FUNC_READ_COILS_ENABLED ( 1 ) -/*! \brief If the Write Coils function should be enabled. */ -#define MB_FUNC_WRITE_COIL_ENABLED ( 1 ) -/*! \brief If the Write Multiple Coils function should be enabled. */ -#define MB_FUNC_WRITE_MULTIPLE_COILS_ENABLED ( 1 ) -/*! \brief If the Read Discrete Inputs function should be enabled. */ -#define MB_FUNC_READ_DISCRETE_INPUTS_ENABLED ( 1 ) -/*! @} */ -#ifdef __cplusplus - PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/port/port.h deleted file mode 100644 index c8594080f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/port/port.h +++ /dev/null @@ -1,77 +0,0 @@ - /* - * FreeModbus Libary: MCF5235 Port - * Copyright (C) 2006 Christian Walter - * Parts of crt0.S Copyright (c) 1995, 1996, 1998 Cygnus Support - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -#include - -/* ----------------------- Defines ------------------------------------------*/ - -#define INLINE inline -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif -#define MB_TCP_DEBUG 1 /* Debug output in TCP module. */ -/* ----------------------- Type definitions ---------------------------------*/ -typedef char BOOL; - -typedef unsigned char UCHAR; -typedef char CHAR; - -typedef unsigned short USHORT; -typedef short SHORT; - -typedef unsigned long ULONG; -typedef long LONG; - -#ifdef MB_TCP_DEBUG -typedef enum -{ - MB_LOG_DEBUG, - MB_LOG_INFO, - MB_LOG_WARN, - MB_LOG_ERROR -} eMBPortLogLevel; -#endif - -/* ----------------------- Function prototypes ------------------------------*/ -#ifdef MB_TCP_DEBUG -void vMBPortLog( eMBPortLogLevel eLevel, const CHAR * szModule, - const CHAR * szFmt, ... ); -#endif - -#ifdef __cplusplus -PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/port/portevent.c deleted file mode 100644 index c1e8a5bab..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/port/portevent.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * FreeModbus Libary: lwIP Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "assert.h" - -/* ----------------------- lwIP ---------------------------------------------*/ -#include "lwip/api.h" -#include "lwip/sys.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_POLL_CYCLETIME 100 /* Poll cycle time is 100ms */ -/* ----------------------- Static variables ---------------------------------*/ -static sys_mbox_t xMailBox = SYS_MBOX_NULL; -static eMBEventType eMailBoxEvent; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - eMailBoxEvent = EV_READY; - xMailBox = sys_mbox_new( ); - return xMailBox != SYS_MBOX_NULL ? TRUE : FALSE; -} - -void -vMBPortEventClose( void ) -{ - if( xMailBox != SYS_MBOX_NULL ) - { - sys_mbox_free( xMailBox ); - } -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - eMailBoxEvent = eEvent; - sys_mbox_post( xMailBox, &eMailBoxEvent ); - return TRUE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - void *peMailBoxEvent; - BOOL xEventHappend = FALSE; - u32_t uiTimeSpent; - - uiTimeSpent = sys_arch_mbox_fetch( xMailBox, &peMailBoxEvent, MB_POLL_CYCLETIME ); - if( uiTimeSpent != SYS_ARCH_TIMEOUT ) - { - *eEvent = *( eMBEventType * ) peMailBoxEvent; - eMailBoxEvent = EV_READY; - xEventHappend = TRUE; - } - return xEventHappend; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/port/portother.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/port/portother.c deleted file mode 100644 index de38ae944..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/port/portother.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * FreeModbus Libary: lwIP Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include -#include -#include -#include -#include -#include - -#include "port.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_FRAME_LOG_BUFSIZE 512 - -/* ----------------------- Start implementation -----------------------------*/ - -#ifdef MB_TCP_DEBUG -void -prvvMBTCPLogFrame( UCHAR * pucMsg, UCHAR * pucFrame, USHORT usFrameLen ) -{ - int i; - int res; - int iBufPos = 0; - size_t iBufLeft = MB_FRAME_LOG_BUFSIZE; - static CHAR arcBuffer[MB_FRAME_LOG_BUFSIZE]; - - assert( pucFrame != NULL ); - - for( i = 0; i < usFrameLen; i++ ) - { - /* Print some additional frame information. */ - switch ( i ) - { - case 0: - /* TID = Transaction Identifier. */ - res = snprintf( &arcBuffer[iBufPos], iBufLeft, "| TID = " ); - break; - case 2: - /* PID = Protocol Identifier. */ - res = snprintf( &arcBuffer[iBufPos], iBufLeft, " | PID = " ); - break; - case 4: - /* Length */ - res = snprintf( &arcBuffer[iBufPos], iBufLeft, " | LEN = " ); - break; - case 6: - /* UID = Unit Identifier. */ - res = snprintf( &arcBuffer[iBufPos], iBufLeft, " | UID = " ); - break; - case 7: - /* MB Function Code. */ - res = snprintf( &arcBuffer[iBufPos], iBufLeft, "|| FUNC = " ); - break; - case 8: - /* MB PDU rest. */ - res = snprintf( &arcBuffer[iBufPos], iBufLeft, " | DATA = " ); - break; - default: - res = 0; - break; - } - if( res == -1 ) - { - break; - } - else - { - iBufPos += res; - iBufLeft -= res; - } - - /* Print the data. */ - res = snprintf( &arcBuffer[iBufPos], iBufLeft, "%02X", pucFrame[i] ); - if( res == -1 ) - { - break; - } - else - { - iBufPos += res; - iBufLeft -= res; - } - } - - if( res != -1 ) - { - /* Append an end of frame string. */ - res = snprintf( &arcBuffer[iBufPos], iBufLeft, " |\r\n" ); - if( res != -1 ) - { - vMBPortLog( MB_LOG_DEBUG, pucMsg, "%s", arcBuffer ); - } - } -} -#endif - -#ifdef MB_TCP_DEBUG -void -vMBPortLog( eMBPortLogLevel eLevel, const CHAR * szModule, const CHAR * szFmt, ... ) -{ - va_list args; - static const char *arszLevel2Str[] = { "DEBUG", "INFO", "WARN", "ERROR" }; - - ( void )printf( "%s: %s: ", arszLevel2Str[eLevel], szModule ); - va_start( args, szFmt ); - vprintf( szFmt, args ); - va_end( args ); -} -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/port/porttcp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/port/porttcp.c deleted file mode 100644 index b6d8a86ad..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/port/porttcp.c +++ /dev/null @@ -1,328 +0,0 @@ -/* - * FreeModbus Libary: lwIP Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include - -#include "port.h" - -/* ----------------------- lwIP includes ------------------------------------*/ -#include "lwip/api.h" -#include "lwip/tcp.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- MBAP Header --------------------------------------*/ -#define MB_TCP_UID 6 -#define MB_TCP_LEN 4 -#define MB_TCP_FUNC 7 - -/* ----------------------- Defines -----------------------------------------*/ -#define MB_TCP_DEFAULT_PORT 502 /* TCP listening port. */ -#define MB_TCP_BUF_SIZE ( 256 + 7 ) /* Must hold a complete Modbus TCP frame. */ - -/* ----------------------- Prototypes ---------------------------------------*/ -void vMBPortEventClose( void ); -void vMBPortLog( eMBPortLogLevel eLevel, const CHAR * szModule, - const CHAR * szFmt, ... ); - -/* ----------------------- Static variables ---------------------------------*/ -static struct tcp_pcb *pxPCBListen; -static struct tcp_pcb *pxPCBClient; - -static UCHAR aucTCPBuf[MB_TCP_BUF_SIZE]; -static USHORT usTCPBufPos; - -/* ----------------------- Static functions ---------------------------------*/ -static err_t prvxMBTCPPortAccept( void *pvArg, struct tcp_pcb *pxPCB, err_t xErr ); -static err_t prvxMBTCPPortReceive( void *pvArg, struct tcp_pcb *pxPCB, struct pbuf *p, - err_t xErr ); -static void prvvMBTCPPortError( void *pvArg, err_t xErr ); - -/* ----------------------- Begin implementation -----------------------------*/ -BOOL -xMBTCPPortInit( USHORT usTCPPort ) -{ - struct tcp_pcb *pxPCBListenNew, *pxPCBListenOld; - BOOL bOkay = FALSE; - USHORT usPort; - - if( usTCPPort == 0 ) - { - usPort = MB_TCP_DEFAULT_PORT; - } - else - { - usPort = ( USHORT ) usTCPPort; - } - - if( ( pxPCBListenNew = pxPCBListenOld = tcp_new( ) ) == NULL ) - { - /* Can't create TCP socket. */ - bOkay = FALSE; - } - else if( tcp_bind( pxPCBListenNew, IP_ADDR_ANY, ( u16_t ) usPort ) != ERR_OK ) - { - /* Bind failed - Maybe illegal port value or in use. */ - ( void )tcp_close( pxPCBListenOld ); - bOkay = FALSE; - } - else if( ( pxPCBListenNew = tcp_listen( pxPCBListenNew ) ) == NULL ) - { - ( void )tcp_close( pxPCBListenOld ); - bOkay = FALSE; - } - else - { - /* Register callback function for new clients. */ - tcp_accept( pxPCBListenNew, prvxMBTCPPortAccept ); - - /* Everything okay. Set global variable. */ - pxPCBListen = pxPCBListenNew; - -#ifdef MB_TCP_DEBUG - vMBPortLog( MB_LOG_DEBUG, "MBTCP-ACCEPT", "Protocol stack ready.\r\n" ); -#endif - } - bOkay = TRUE; - return bOkay; -} - -void -prvvMBPortReleaseClient( struct tcp_pcb *pxPCB ) -{ - if( pxPCB != NULL ) - { - if( tcp_close( pxPCB ) != ERR_OK ) - { - tcp_abort( pxPCB ); - } - if( pxPCB == pxPCBClient ) - { -#ifdef MB_TCP_DEBUG - vMBPortLog( MB_LOG_DEBUG, "MBTCP-CLOSE", "Closed connection to %d.%d.%d.%d.\r\n", - ip4_addr1( &( pxPCB->remote_ip ) ), - ip4_addr2( &( pxPCB->remote_ip ) ), - ip4_addr3( &( pxPCB->remote_ip ) ), ip4_addr4( &( pxPCB->remote_ip ) ) ); -#endif - pxPCBClient = NULL; - } - if( pxPCB == pxPCBListen ) - { - pxPCBListen = NULL; - } - } -} -void -vMBTCPPortClose( ) -{ - /* Shutdown any open client sockets. */ - prvvMBPortReleaseClient( pxPCBClient ); - - /* Shutdown or listening socket. */ - prvvMBPortReleaseClient( pxPCBListen ); - - /* Release resources for the event queue. */ - vMBPortEventClose( ); -} - -void -vMBTCPPortDisable( void ) -{ - prvvMBPortReleaseClient( pxPCBClient ); -} - -err_t -prvxMBTCPPortAccept( void *pvArg, struct tcp_pcb *pxPCB, err_t xErr ) -{ - err_t error; - - if( xErr != ERR_OK ) - { - return xErr; - } - - /* We can handle only one client. */ - if( pxPCBClient == NULL ) - { - /* Register the client. */ - pxPCBClient = pxPCB; - - /* Set up the receive function prvxMBTCPPortReceive( ) to be called when data - * arrives. - */ - tcp_recv( pxPCB, prvxMBTCPPortReceive ); - - /* Register error handler. */ - tcp_err( pxPCB, prvvMBTCPPortError ); - - /* Set callback argument later used in the error handler. */ - tcp_arg( pxPCB, pxPCB ); - - /* Reset the buffers and state variables. */ - usTCPBufPos = 0; - -#ifdef MB_TCP_DEBUG - vMBPortLog( MB_LOG_DEBUG, "MBTCP-ACCEPT", "Accepted new client %d.%d.%d.%d\r\n", - ip4_addr1( &( pxPCB->remote_ip ) ), - ip4_addr2( &( pxPCB->remote_ip ) ), - ip4_addr3( &( pxPCB->remote_ip ) ), ip4_addr4( &( pxPCB->remote_ip ) ) ); -#endif - - error = ERR_OK; - } - else - { - prvvMBPortReleaseClient( pxPCB ); - error = ERR_OK; - } - return error; -} - -/* Called in case of an unrecoverable error. In any case we drop the client - * connection. */ -void -prvvMBTCPPortError( void *pvArg, err_t xErr ) -{ - struct tcp_pcb *pxPCB = pvArg; - - if( pxPCB != NULL ) - { -#ifdef MB_TCP_DEBUG - vMBPortLog( MB_LOG_DEBUG, "MBTCP-ERROR", "Error with client connection! Droping it.\r\n" ); -#endif - prvvMBPortReleaseClient( pxPCB ); - } -} - -err_t -prvxMBTCPPortReceive( void *pvArg, struct tcp_pcb *pxPCB, struct pbuf *p, err_t xErr ) -{ - USHORT usLength; - - err_t error; - - if( xErr != ERR_OK ) - { - return xErr; - } - - /* If pbuf is NULL then remote end has closed connection. */ - if( p == NULL ) - { - prvvMBPortReleaseClient( pxPCB ); - return ERR_OK; - } - - /* Acknowledge that we have received the data bytes. */ - tcp_recved( pxPCB, p->len ); - - /* Check for internal buffer overflow. In case of an error drop the - * client. */ - if( ( usTCPBufPos + p->len ) >= MB_TCP_BUF_SIZE ) - { - prvvMBPortReleaseClient( pxPCB ); - error = ERR_OK; - } - else - { - memcpy( &aucTCPBuf[usTCPBufPos], p->payload, p->len ); - usTCPBufPos += p->len; - - /* If we have received the MBAP header we can analyze it and calculate - * the number of bytes left to complete the current request. If complete - * notify the protocol stack. - */ - if( usTCPBufPos >= MB_TCP_FUNC ) - { - /* Length is a byte count of Modbus PDU (function code + data) and the - * unit identifier. */ - usLength = aucTCPBuf[MB_TCP_LEN] << 8U; - usLength |= aucTCPBuf[MB_TCP_LEN + 1]; - - /* Is the frame already complete. */ - if( usTCPBufPos < ( MB_TCP_UID + usLength ) ) - { - } - else if( usTCPBufPos == ( MB_TCP_UID + usLength ) ) - { -#ifdef MB_TCP_DEBUG - prvvMBTCPLogFrame( "MBTCP-RECV", &aucTCPBuf[0], usTCPBufPos ); -#endif - ( void )xMBPortEventPost( EV_FRAME_RECEIVED ); - } - else - { -#ifdef MB_TCP_DEBUG - vMBPortLog( MB_LOG_DEBUG, "MBTCP-ERROR", - "Received to many bytes! Droping client.\r\n" ); -#endif - /* This should not happen. We can't deal with such a client and - * drop the connection for security reasons. - */ - prvvMBPortReleaseClient( pxPCB ); - } - } - } - pbuf_free( p ); - return error; -} - -BOOL -xMBTCPPortGetRequest( UCHAR ** ppucMBTCPFrame, USHORT * usTCPLength ) -{ - *ppucMBTCPFrame = &aucTCPBuf[0]; - *usTCPLength = usTCPBufPos; - - /* Reset the buffer. */ - usTCPBufPos = 0; - return TRUE; -} - -BOOL -xMBTCPPortSendResponse( const UCHAR * pucMBTCPFrame, USHORT usTCPLength ) -{ - BOOL bFrameSent = FALSE; - - if( pxPCBClient ) - { - /* Make sure we can send the packet. */ - assert( tcp_sndbuf( pxPCBClient ) >= usTCPLength ); - - if( tcp_write( pxPCBClient, pucMBTCPFrame, ( u16_t ) usTCPLength, NETCONN_COPY ) == ERR_OK ) - { -#ifdef MB_TCP_DEBUG - prvvMBTCPLogFrame( "MBTCP-SENT", &aucTCPBuf[0], usTCPLength ); -#endif - /* Make sure data gets sent immediately. */ - ( void )tcp_output( pxPCBClient ); - bFrameSent = TRUE; - } - else - { - /* Drop the connection in case of an write error. */ - prvvMBPortReleaseClient( pxPCBClient ); - } - } - return bFrameSent; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/simple.bat b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/simple.bat deleted file mode 100644 index c4d53d227..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/simple.bat +++ /dev/null @@ -1 +0,0 @@ -..\..\tools\modpoll.exe -m tcp 10.0.10.2 -r 1000 -t 3:int diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/simple.sh b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/simple.sh deleted file mode 100644 index 1af9b7a19..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/simple.sh +++ /dev/null @@ -1 +0,0 @@ -../../tools/modpoll -m tcp 10.0.10.2 -r 1000 -t 3:int diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/crt0.S b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/crt0.S deleted file mode 100644 index 21954bcb1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/crt0.S +++ /dev/null @@ -1,115 +0,0 @@ -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - .title "crt0.S" - - .extern main - .extern __stack - .extern __bss_start - .extern __text_start - .extern init_main - - .equ MCF5XXX_RAMBAR_SPV, 0x00000200 - .equ MCF5XXX_RAMBAR_V, 0x00000001 - .global start - - .align 4 -debug: - .word 0x2C80 /* write to CSR */ - .word 0x0010 - .word 0x0400 - .word 0x0000 - -start: - /* disable all interrupts on startup. */ - move.w #0x2700, sr - - /* prepare internal SRAM. */ - move.l #__SRAM, d0 - ori.l #( MCF5XXX_RAMBAR_SPV | MCF5XXX_RAMBAR_V ), d0 - movec d0, rambar - - /* prepare stack and frame pointer. */ - move.l #__stack, sp - link a6, #-8 - - /* initialize hardware. */ - jsr init_main - - /* zero out the bss section. */ - move.l #__bss_start, d1 - move.l #_end, d0 - cmp.l d0, d1 - jbeq 3f - move.l d1, a0 - sub.l d1, d0 - subq.l #1, d0 -2: - clr.b (a0)+ - subq.l #1, d0 - jbpl 2b -3: - - /* Relocate the data section. */ - move.l #__data_load_start, %a0 /* .data in ROM */ - move.l #copy_start, %a1 /* .data in RAM */ - - /* Test if the two sections overlap. This is the case when we are working - * with the debugger and the debugger loads the .data section. - */ - cmpa.l %a0, %a1 - beq 2f -1: - /* Have we already copied everything. */ - cmpa.l #__data_load_end, %a0 - beq 2f - move.b (%a0)+, (%a1)+ - bra 1b - -2: - - /* C library */ - move.l #__FINI_SECTION__, -(%sp) - jsr atexit - jsr __INIT_SECTION__ - - /* call main(int argc, char *argv[] */ - move.l #0, -(sp) - move.l #0, -(sp) - move.l #0, -(sp) - jsr main - lea (sp, 12), %sp - - /* stop on exit from main. */ -1: - halt - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/init.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/init.c deleted file mode 100644 index 74957f35e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/init.c +++ /dev/null @@ -1,743 +0,0 @@ -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include "mcf5xxx.h" -#include "mcf523x.h" - -/* Function prototypes */ -void init_main( void ); -static void disable_interrupts( void ); -static void disable_watchdog_timer( void ); -static void disable_cache( void ); -static void init_ipsbar( void ); -static void init_basics( void ); -static void init_clock_config( void ); -static void init_chip_selects( void ); -static void init_bus_config( void ); -static void init_cache( void ); -static void init_eport( void ); -static void init_flexcan( void ); -static void init_power_management( void ); -static void init_dma_timers( void ); -static void init_interrupt_timers( void ); -static void init_watchdog_timers( void ); -static void init_pin_assignments( void ); -static void init_sdram_controller( void ); -static void init_interrupt_controller( void ); - - -/********************************************************************* -* init_main - Main entry point for initialisation code * -**********************************************************************/ -void -init_main( void ) -{ - - /* Initialise base address of peripherals, VBR, etc */ - init_ipsbar( ); - init_basics( ); - init_clock_config( ); - - /* Disable interrupts, watchdog timer, cache */ - disable_interrupts( ); - disable_watchdog_timer( ); - disable_cache( ); - - /* Initialise individual modules */ - init_chip_selects( ); - init_bus_config( ); - init_cache( ); - init_eport( ); - init_flexcan( ); - init_power_management( ); - init_dma_timers( ); - init_interrupt_timers( ); - init_watchdog_timers( ); - init_pin_assignments( ); - init_sdram_controller( ); - - /* Initialise interrupt controller */ - init_interrupt_controller( ); -} - -/********************************************************************* -* disable_interrupts - Disable all interrupt sources * -**********************************************************************/ -static void -disable_interrupts( void ) -{ - vuint8 *p; - int i; - - - /* Set ICR008-ICR063 to 0x0 */ - p = ( vuint8 * ) & MCF_INTC0_ICR8; - for( i = 8; i <= 63; i++ ) - *p++ = 0x0; - - /* Set ICR108-ICR163 to 0x0 */ - p = ( vuint8 * ) & MCF_INTC1_ICR8; - for( i = 108; i <= 163; i++ ) - *p++ = 0x0; -} - - -/********************************************************************* -* disable_watchdog_timer - Disable system watchdog timer * -**********************************************************************/ -static void -disable_watchdog_timer( void ) -{ - - /* Disable Core Watchdog Timer */ - MCF_SCM_CWCR = 0; -} - -/********************************************************************* -* disable_cache - Disable and invalidate cache * -**********************************************************************/ -static void -disable_cache( void ) -{ - asm ( "move.l #0x01000000, %d0" ); - asm ( "movec %d0, %CACR" ); -} - -/********************************************************************* -* init_basics - Configuration Information & VBR * -**********************************************************************/ -static void -init_basics( void ) -{ - int i; - extern uint32 __RAMVEC[]; - extern uint32 __ROMVEC[]; - - /* Transfer size not driven on SIZ[1:0] pins during external cycles - Processor Status (PST) and Debug Data (DDATA) functions disabled - Bus monitor disabled - Output pads configured for full strength - */ - MCF_CCM_CCR = ( 0x1 << 15 ) | MCF_CCM_CCR_BME; - - /* Set up RAM vectors */ - for( i = 0; i < 256; i++ ) - - { - __RAMVEC[i] = __ROMVEC[i]; - } - asm( "move.l %0,%%d0": :"i"( __RAMVEC ) ); - asm( "movec %d0,%vbr" ); -} - - -/********************************************************************* -* init_clock_config - Clock Module * -**********************************************************************/ -static void -init_clock_config( void ) -{ - /* Clock module uses normal PLL mode with 25.0000 MHz external reference (Fref) - MFD = 0, RFD = 1 - Bus clock frequency = 25.00 MHz - Processor clock frequency = 2 x bus clock = 50.00 MHz - Frequency Modulation disabled - Loss of clock detection disabled - Reset/Interrupt on loss of lock disabled - */ - MCF_FMPLL_SYNCR = 0x00100000; /* Set RFD=RFD+1 to avoid frequency overshoot */ - while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */ - ; - MCF_FMPLL_SYNCR = 0x00080000; /* Set desired RFD */ - while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 ) /* Wait for PLL to lock */ - ; -} - - -/********************************************************************* -* init_ipsbar - Internal Peripheral System Base Address (IPSBAR) * -**********************************************************************/ -static void -init_ipsbar( void ) -{ - extern int __SRAM; - - /* Base address of internal peripherals (IPSBAR) = 0x40000000 - - Note: Processor powers up with IPS base address = 0x40000000 - Write to IPS base + 0x00000000 to set new value - */ - *( vuint32 * ) 0x40000000 = ( vuint32 ) __IPSBAR + 1; - - /* Configure RAMBAR in SCM module and allow dual-ported access. */ - MCF_SCM_RAMBAR = ( uint32 ) &__SRAM | MCF_SCM_RAMBAR_BDE; -} - -/********************************************************************* -* init_chip_selects - Chip Select Module * -**********************************************************************/ -static void -init_chip_selects( void ) -{ - extern void __FLASH; - uint32 FLASH_ADDR = (uint32)&__FLASH; - - /* Chip Select 0 - External Flash */ - MCF_CS_CSAR0 = MCF_CS_CSAR_BA( FLASH_ADDR ); - MCF_CS_CSCR0 = ( 0 - | MCF_CS_CSCR_IWS( 6 ) - | MCF_CS_CSCR_AA | MCF_CS_CSCR_PS_16 ); - MCF_CS_CSMR0 = MCF_CS_CSMR_BAM_2M | MCF_CS_CSMR_V; - - /* Chip Select 1 disabled (CSMR1[V] = 0) */ - MCF_CS_CSAR1 = 0; - MCF_CS_CSMR1 = 0; - MCF_CS_CSCR1 = 0; - - /* Chip Select 2 disabled (CSMR2[V] = 0) */ - MCF_CS_CSAR2 = 0; - MCF_CS_CSMR2 = 0; - MCF_CS_CSCR2 = 0; - - /* Chip Select 3 disabled (CSMR3[V] = 0) */ - MCF_CS_CSAR3 = 0; - MCF_CS_CSMR3 = 0; - MCF_CS_CSCR3 = 0; - - /* Chip Select 4 disabled (CSMR4[V] = 0) */ - MCF_CS_CSAR4 = 0; - MCF_CS_CSMR4 = 0; - MCF_CS_CSCR4 = 0; - - /* Chip Select 5 disabled (CSMR5[V] = 0) */ - MCF_CS_CSAR5 = 0; - MCF_CS_CSMR5 = 0; - MCF_CS_CSCR5 = 0; - - /* Chip Select 6 disabled (CSMR6[V] = 0) */ - MCF_CS_CSAR6 = 0; - MCF_CS_CSMR6 = 0; - MCF_CS_CSCR6 = 0; - - /* Chip Select 7 disabled (CSMR7[V] = 0) */ - MCF_CS_CSAR7 = 0; - MCF_CS_CSMR7 = 0; - MCF_CS_CSCR7 = 0; -} - -/********************************************************************* -* init_bus_config - Internal Bus Arbitration * -**********************************************************************/ -static void -init_bus_config( void ) -{ - - /* Use round robin arbitration scheme - Assigned priorities (highest first): - Ethernet - DMA Controller - ColdFire Core - DMA bandwidth control disabled - Park on last active bus master - */ - MCF_SCM_MPARK = - MCF_SCM_MPARK_M3_PRTY( 0x3 ) | MCF_SCM_MPARK_M2_PRTY( 0x2 ) | - MCF_SCM_MPARK_M1_PRTY( 0x1 ); -} - -/********************************************************************* -* init_cache - Instruction/Data Cache * -**********************************************************************/ -static void -init_cache( void ) -{ - /* Configured as split cache: 4 KByte instruction cache and 4 Kbyte data cache - ACR0: Don't cache accesses to 16 MB memory region at address $20000000 - ACR1: Don't cache accesses to 1 GB memory region at address $40000000 - CACR: Cache accesses to the rest of memory - */ - asm("move.l #0x80000000,%d0"); - asm("movec %d0,%CACR"); - asm("move.l #0x2000c040,%d0"); - asm("movec %d0,%ACR0"); - asm("move.l #0x403fc040,%d0"); - asm("movec %d0,%ACR1"); - - /* Instruction/Data cache disabled. */ - //asm( "move.l #0x00000000, %d0" ); - //asm( "movec %d0,%cacr" ); -} - -/********************************************************************* -* init_eport - Edge Port Module (EPORT) * -**********************************************************************/ -static void -init_eport( void ) -{ - - /* Pins 1-7 configured as GPIO inputs */ - MCF_EPORT_EPPAR = 0; - MCF_EPORT_EPDDR = 0; - MCF_EPORT_EPIER = 0; -} - -/********************************************************************* -* init_flexcan - FlexCAN Module * -**********************************************************************/ -static void -init_flexcan( void ) -{ - - /* FlexCAN controller 0 disabled (CANMCR0[MDIS]=1) */ - MCF_CAN_IMASK0 = 0; - MCF_CAN_RXGMASK0 = MCF_CAN_RXGMASK_MI( 0x1fffffff ); - MCF_CAN_RX14MASK0 = MCF_CAN_RX14MASK_MI( 0x1fffffff ); - MCF_CAN_RX15MASK0 = MCF_CAN_RX15MASK_MI( 0x1fffffff ); - MCF_CAN_CANCTRL0 = 0; - MCF_CAN_CANMCR0 = - MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT | - MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf ); - - /* FlexCAN controller 1 disabled (CANMCR1[MDIS]=1) */ - MCF_CAN_IMASK1 = 0; - MCF_CAN_RXGMASK1 = MCF_CAN_RXGMASK_MI( 0x1fffffff ); - MCF_CAN_RX14MASK1 = MCF_CAN_RX14MASK_MI( 0x1fffffff ); - MCF_CAN_RX15MASK1 = MCF_CAN_RX15MASK_MI( 0x1fffffff ); - MCF_CAN_CANCTRL1 = 0; - MCF_CAN_CANMCR1 = - MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT | - MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf ); -} - -/********************************************************************* -* init_power_management - Power Management * -**********************************************************************/ -static void -init_power_management( void ) -{ - - /* On executing STOP instruction, processor enters RUN mode - Mode is exited when an interrupt of level 1 or higher is received - */ - MCF_SCM_LPICR = MCF_SCM_LPICR_ENBSTOP; - MCF_CCM_LPCR = 0; -} - -/********************************************************************* -* init_sdram_controller - SDRAM Controller * -**********************************************************************/ -static void -init_sdram_controller( void ) -{ - extern void __SDRAM; - uint32 SDRAM_ADDR = (uint32)&__SDRAM; - int i; - - - /* - * Check to see if the SDRAM has already been initialized - * by a run control tool - */ - if( !( MCF_SDRAMC_DACR0 & MCF_SDRAMC_DACR0_RE ) ) - { - /* Initialize DRAM Control Register: DCR */ - MCF_SDRAMC_DCR = ( MCF_SDRAMC_DCR_RTIM( 1 ) | - MCF_SDRAMC_DCR_RC( ( 15 * FSYS_2 ) >> 4 ) ); - - /* Initialize DACR0 */ - MCF_SDRAMC_DACR0 = ( MCF_SDRAMC_DACR0_BA( SDRAM_ADDR >> 18UL ) | - MCF_SDRAMC_DACR0_CASL( 1 ) | - MCF_SDRAMC_DACR0_CBM( 3 ) | - MCF_SDRAMC_DACR0_PS( 0 ) ); - - /* Initialize DMR0 */ - MCF_SDRAMC_DMR0 = ( MCF_SDRAMC_DMR_BAM_16M | MCF_SDRAMC_DMR0_V ); - - /* Set IP (bit 3) in DACR */ - MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_IP; - - /* Wait 30ns to allow banks to precharge */ - for( i = 0; i < 5; i++ ) - { - asm volatile ( " nop" ); - } - /* Write to this block to initiate precharge */ - *( uint32 * ) ( SDRAM_ADDR ) = 0xA5A59696; - - /* Set RE (bit 15) in DACR */ - MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_RE; - - /* Wait for at least 8 auto refresh cycles to occur */ - for( i = 0; i < 2000; i++ ) - { - asm volatile ( "nop" ); - } - /* Finish the configuration by issuing the IMRS. */ - MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_MRS; - - /* Write to the SDRAM Mode Register */ - *( uint32 * ) ( SDRAM_ADDR + 0x400 ) = 0xA5A59696; - } -} - -/********************************************************************* -* init_dma_timers - DMA Timer Modules * -**********************************************************************/ -static void -init_dma_timers( void ) -{ - - /* DMA Timer 0 disabled (DTMR0[RST] = 0) */ - MCF_TIMER_DTMR0 = 0; - MCF_TIMER_DTXMR0 = 0; - MCF_TIMER_DTRR0 = 0xffffffff; - - /* DMA Timer 1 disabled (DTMR1[RST] = 0) */ - MCF_TIMER_DTMR1 = 0; - MCF_TIMER_DTXMR1 = 0; - MCF_TIMER_DTRR1 = 0xffffffff; - - /* DMA Timer 2 disabled (DTMR2[RST] = 0) */ - MCF_TIMER_DTMR2 = 0; - MCF_TIMER_DTXMR2 = 0; - MCF_TIMER_DTRR2 = 0xffffffff; - - /* DMA Timer 3 disabled (DTMR3[RST] = 0) */ - MCF_TIMER_DTMR3 = 0; - MCF_TIMER_DTXMR3 = 0; - MCF_TIMER_DTRR3 = 0xffffffff; -} - -/********************************************************************** -* init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules * -***********************************************************************/ -static void -init_interrupt_timers( void ) -{ - - /* PIT0 disabled (PCSR0[EN]=0) */ - MCF_PIT_PCSR0 = 0; - - /* PIT1 disabled (PCSR1[EN]=0) */ - MCF_PIT_PCSR1 = 0; - - /* PIT2 disabled (PCSR2[EN]=0) */ - MCF_PIT_PCSR2 = 0; - - /* PIT3 disabled (PCSR3[EN]=0) */ - MCF_PIT_PCSR3 = 0; -} - -/********************************************************************* -* init_watchdog_timers - Watchdog Timer Modules * -**********************************************************************/ -static void -init_watchdog_timers( void ) -{ - - /* Watchdog Timer disabled (WCR[EN]=0) - NOTE: WCR and WMR cannot be written again until after the - processor is reset. - */ - MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED; - MCF_WTM_WMR = 0xffff; - - /* Core Watchdog Timer disabled (CWCR[CWE]=0) */ - MCF_SCM_CWCR = 0; -} - -/********************************************************************* -* init_interrupt_controller - Interrupt Controller * -**********************************************************************/ -static void -init_interrupt_controller( void ) -{ - - /* Configured interrupt sources in order of priority... - Level 7: External interrupt /IRQ7, (initially masked) - Level 6: External interrupt /IRQ6, (initially masked) - Level 5: External interrupt /IRQ5, (initially masked) - Level 4: External interrupt /IRQ4, (initially masked) - Level 3: External interrupt /IRQ3, (initially masked) - Level 2: External interrupt /IRQ2, (initially masked) - Level 1: External interrupt /IRQ1, (initially masked) - */ - MCF_INTC0_ICR1 = 0; - MCF_INTC0_ICR2 = 0; - MCF_INTC0_ICR3 = 0; - MCF_INTC0_ICR4 = 0; - MCF_INTC0_ICR5 = 0; - MCF_INTC0_ICR6 = 0; - MCF_INTC0_ICR7 = 0; - MCF_INTC0_ICR8 = 0; - MCF_INTC0_ICR9 = 0; - MCF_INTC0_ICR10 = 0; - MCF_INTC0_ICR11 = 0; - MCF_INTC0_ICR12 = 0; - MCF_INTC0_ICR13 = 0; - MCF_INTC0_ICR14 = 0; - MCF_INTC0_ICR15 = 0; - MCF_INTC0_ICR17 = 0; - MCF_INTC0_ICR18 = 0; - MCF_INTC0_ICR19 = 0; - MCF_INTC0_ICR20 = 0; - MCF_INTC0_ICR21 = 0; - MCF_INTC0_ICR22 = 0; - MCF_INTC0_ICR23 = 0; - MCF_INTC0_ICR24 = 0; - MCF_INTC0_ICR25 = 0; - MCF_INTC0_ICR26 = 0; - MCF_INTC0_ICR27 = 0; - MCF_INTC0_ICR28 = 0; - MCF_INTC0_ICR29 = 0; - MCF_INTC0_ICR30 = 0; - MCF_INTC0_ICR31 = 0; - MCF_INTC0_ICR32 = 0; - MCF_INTC0_ICR33 = 0; - MCF_INTC0_ICR34 = 0; - MCF_INTC0_ICR35 = 0; - MCF_INTC0_ICR36 = 0; - MCF_INTC0_ICR37 = 0; - MCF_INTC0_ICR38 = 0; - MCF_INTC0_ICR39 = 0; - MCF_INTC0_ICR40 = 0; - MCF_INTC0_ICR41 = 0; - MCF_INTC0_ICR42 = 0; - MCF_INTC0_ICR43 = 0; - MCF_INTC0_ICR44 = 0; - MCF_INTC0_ICR45 = 0; - MCF_INTC0_ICR46 = 0; - MCF_INTC0_ICR47 = 0; - MCF_INTC0_ICR48 = 0; - MCF_INTC0_ICR49 = 0; - MCF_INTC0_ICR50 = 0; - MCF_INTC0_ICR51 = 0; - MCF_INTC0_ICR52 = 0; - MCF_INTC0_ICR53 = 0; - MCF_INTC0_ICR54 = 0; - MCF_INTC0_ICR55 = 0; - MCF_INTC0_ICR56 = 0; - MCF_INTC0_ICR57 = 0; - MCF_INTC0_ICR58 = 0; - MCF_INTC0_ICR59 = 0; - MCF_INTC0_ICR60 = 0; - MCF_INTC1_ICR8 = 0; - MCF_INTC1_ICR9 = 0; - MCF_INTC1_ICR10 = 0; - MCF_INTC1_ICR11 = 0; - MCF_INTC1_ICR12 = 0; - MCF_INTC1_ICR13 = 0; - MCF_INTC1_ICR14 = 0; - MCF_INTC1_ICR15 = 0; - MCF_INTC1_ICR16 = 0; - MCF_INTC1_ICR17 = 0; - MCF_INTC1_ICR18 = 0; - MCF_INTC1_ICR19 = 0; - MCF_INTC1_ICR20 = 0; - MCF_INTC1_ICR21 = 0; - MCF_INTC1_ICR22 = 0; - MCF_INTC1_ICR23 = 0; - MCF_INTC1_ICR24 = 0; - MCF_INTC1_ICR25 = 0; - MCF_INTC1_ICR27 = 0; - MCF_INTC1_ICR28 = 0; - MCF_INTC1_ICR29 = 0; - MCF_INTC1_ICR30 = 0; - MCF_INTC1_ICR31 = 0; - MCF_INTC1_ICR32 = 0; - MCF_INTC1_ICR33 = 0; - MCF_INTC1_ICR34 = 0; - MCF_INTC1_ICR35 = 0; - MCF_INTC1_ICR36 = 0; - MCF_INTC1_ICR37 = 0; - MCF_INTC1_ICR38 = 0; - MCF_INTC1_ICR39 = 0; - MCF_INTC1_ICR40 = 0; - MCF_INTC1_ICR41 = 0; - MCF_INTC1_ICR42 = 0; - MCF_INTC1_ICR59 = 0; - MCF_INTC0_IMRH = 0xffffffff; - MCF_INTC0_IMRL = - MCF_INTC0_IMRL_INT_MASK31 | MCF_INTC0_IMRL_INT_MASK30 | - MCF_INTC0_IMRL_INT_MASK29 | MCF_INTC0_IMRL_INT_MASK28 | - MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_INT_MASK26 | - MCF_INTC0_IMRL_INT_MASK25 | MCF_INTC0_IMRL_INT_MASK24 | - MCF_INTC0_IMRL_INT_MASK23 | MCF_INTC0_IMRL_INT_MASK22 | - MCF_INTC0_IMRL_INT_MASK21 | MCF_INTC0_IMRL_INT_MASK20 | - MCF_INTC0_IMRL_INT_MASK19 | MCF_INTC0_IMRL_INT_MASK18 | - MCF_INTC0_IMRL_INT_MASK17 | MCF_INTC0_IMRL_INT_MASK16 | - MCF_INTC0_IMRL_INT_MASK15 | MCF_INTC0_IMRL_INT_MASK14 | - MCF_INTC0_IMRL_INT_MASK13 | MCF_INTC0_IMRL_INT_MASK12 | - MCF_INTC0_IMRL_INT_MASK11 | MCF_INTC0_IMRL_INT_MASK10 | - MCF_INTC0_IMRL_INT_MASK9 | MCF_INTC0_IMRL_INT_MASK8 | - MCF_INTC0_IMRL_INT_MASK7 | MCF_INTC0_IMRL_INT_MASK6 | - MCF_INTC0_IMRL_INT_MASK5 | MCF_INTC0_IMRL_INT_MASK4 | - MCF_INTC0_IMRL_INT_MASK3 | MCF_INTC0_IMRL_INT_MASK2 | - MCF_INTC0_IMRL_INT_MASK1; - MCF_INTC1_IMRH = 0xffffffff; - MCF_INTC1_IMRL = - MCF_INTC1_IMRL_INT_MASK31 | MCF_INTC1_IMRL_INT_MASK30 | - MCF_INTC1_IMRL_INT_MASK29 | MCF_INTC1_IMRL_INT_MASK28 | - MCF_INTC1_IMRL_INT_MASK27 | MCF_INTC1_IMRL_INT_MASK26 | - MCF_INTC1_IMRL_INT_MASK25 | MCF_INTC1_IMRL_INT_MASK24 | - MCF_INTC1_IMRL_INT_MASK23 | MCF_INTC1_IMRL_INT_MASK22 | - MCF_INTC1_IMRL_INT_MASK21 | MCF_INTC1_IMRL_INT_MASK20 | - MCF_INTC1_IMRL_INT_MASK19 | MCF_INTC1_IMRL_INT_MASK18 | - MCF_INTC1_IMRL_INT_MASK17 | MCF_INTC1_IMRL_INT_MASK16 | - MCF_INTC1_IMRL_INT_MASK15 | MCF_INTC1_IMRL_INT_MASK14 | - MCF_INTC1_IMRL_INT_MASK13 | MCF_INTC1_IMRL_INT_MASK12 | - MCF_INTC1_IMRL_INT_MASK11 | MCF_INTC1_IMRL_INT_MASK10 | - MCF_INTC1_IMRL_INT_MASK9 | MCF_INTC1_IMRL_INT_MASK8 | - MCF_INTC1_IMRL_INT_MASK7 | MCF_INTC1_IMRL_INT_MASK6 | - MCF_INTC1_IMRL_INT_MASK5 | MCF_INTC1_IMRL_INT_MASK4 | - MCF_INTC1_IMRL_INT_MASK3 | MCF_INTC1_IMRL_INT_MASK2 | - MCF_INTC1_IMRL_INT_MASK1; -} - -/********************************************************************* -* init_pin_assignments - Pin Assignment and General Purpose I/O * -**********************************************************************/ -static void -init_pin_assignments( void ) -{ - - /* Pin assignments for port ADDR - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_APDDR = 0; - MCF_GPIO_PAR_AD = MCF_GPIO_PAR_AD_PAR_ADDR23 - | MCF_GPIO_PAR_AD_PAR_ADDR22 - | MCF_GPIO_PAR_AD_PAR_ADDR21 | MCF_GPIO_PAR_AD_PAR_DATAL; - - /* Pin assignments for ports DATAH and DATAL - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_DATAH = 0; - MCF_GPIO_PDDR_DATAL = 0; - - /* Pin assignments for port BUSCTL - Pin /OE : External bus output enable, /OE - Pin /TA : External bus transfer acknowledge, /TA - Pin /TEA : External bus transfer error acknowledge, /TEA - Pin R/W : External bus read/write indication, R/W - Pin TSIZ1 : External bus transfer size TSIZ1 or DMA acknowledge /DACK1 - Pin TSIZ0 : External bus transfer size TSIZ0 or DMA acknowledge /DACK0 - Pin /TS : External bus transfer start, /TS - Pin /TIP : External bus transfer in progess, /TIP - */ - MCF_GPIO_PDDR_BUSCTL = 0; - MCF_GPIO_PAR_BUSCTL = - MCF_GPIO_PAR_BUSCTL_PAR_OE | MCF_GPIO_PAR_BUSCTL_PAR_TA | - MCF_GPIO_PAR_BUSCTL_PAR_TEA( 0x3 ) | MCF_GPIO_PAR_BUSCTL_PAR_RWB | - MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 | MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 | - MCF_GPIO_PAR_BUSCTL_PAR_TS( 0x3 ) | - MCF_GPIO_PAR_BUSCTL_PAR_TIP( 0x3 ); - - /* Pin assignments for port BS - Pin /BS3 : External byte strobe /BS3 - Pin /BS2 : External byte strobe /BS2 - Pin /BS1 : External byte strobe /BS1 - Pin /BS0 : External byte strobe /BS0 - */ - MCF_GPIO_PDDR_BS = 0; - MCF_GPIO_PAR_BS = - MCF_GPIO_PAR_BS_PAR_BS3 | MCF_GPIO_PAR_BS_PAR_BS2 | - MCF_GPIO_PAR_BS_PAR_BS1 | MCF_GPIO_PAR_BS_PAR_BS0; - - /* Pin assignments for port CS - Pin /CS7 : Chip select /CS7 - Pin /CS6 : Chip select /CS6 - Pin /CS5 : Chip select /CS5 - Pin /CS4 : Chip select /CS4 - Pin /CS3 : Chip select /CS3 - Pin /CS2 : Chip select /CS2 - Pin /CS1 : Chip select /CS1 - */ - MCF_GPIO_PDDR_CS = 0; - MCF_GPIO_PAR_CS = - MCF_GPIO_PAR_CS_PAR_CS7 | MCF_GPIO_PAR_CS_PAR_CS6 | - MCF_GPIO_PAR_CS_PAR_CS5 | MCF_GPIO_PAR_CS_PAR_CS4 | - MCF_GPIO_PAR_CS_PAR_CS3 | MCF_GPIO_PAR_CS_PAR_CS2 | - MCF_GPIO_PAR_CS_PAR_CS1; - - /* Pin assignments for port SDRAM - Pin /SD_WE : SDRAM controller /SD_WE - Pin /SD_SCAS : SDRAM controller /SD_SCAS - Pin /SD_SRAS : SDRAM controller /SD_SRAS - Pin /SD_SCKE : SDRAM controller /SD_SCKE - Pin /SD_CS1 : SDRAM controller /SD_CS1 - Pin /SD_CS0 : SDRAM controller /SD_CS0 - */ - MCF_GPIO_PDDR_SDRAM = 0; - MCF_GPIO_PAR_SDRAM = - MCF_GPIO_PAR_SDRAM_PAR_SDWE | MCF_GPIO_PAR_SDRAM_PAR_SCAS | - MCF_GPIO_PAR_SDRAM_PAR_SRAS | MCF_GPIO_PAR_SDRAM_PAR_SCKE | - MCF_GPIO_PAR_SDRAM_PAR_SDCS1 | MCF_GPIO_PAR_SDRAM_PAR_SDCS0; - - /* Pin assignments for port FECI2C - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_FECI2C = 0; - MCF_GPIO_PAR_FECI2C = - MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC; - - /* Pin assignments for port UARTL - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_UARTL = 0; - MCF_GPIO_PAR_UART = 0; - - /* Pin assignments for port UARTH - Pin U2TXD : GPIO input - Pin U2RXD : GPIO input - Pin /IRQ2 : Interrupt request /IRQ2 or GPIO - */ - MCF_GPIO_PDDR_UARTH = 0; - - /* Pin assignments for port QSPI - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_QSPI = 0; - MCF_GPIO_PAR_QSPI = 0; - - /* Pin assignments for port TIMER - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_TIMER = 0; - MCF_GPIO_PAR_TIMER = 0; - - /* Pin assignments for port ETPU - Pins are all GPIO inputs - */ - MCF_GPIO_PDDR_ETPU = 0; - MCF_GPIO_PAR_ETPU = 0; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/mcf5xxx.S b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/mcf5xxx.S deleted file mode 100644 index 5902ababa..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/mcf5xxx.S +++ /dev/null @@ -1,271 +0,0 @@ -/* - * File: mcf5xxx.s - * Purpose: Lowest level routines for all ColdFire processors. -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - .global asm_set_ipl - .global _asm_set_ipl - .global mcf5xxx_wr_cacr - .global _mcf5xxx_wr_cacr - .global mcf5xxx_wr_acr0 - .global _mcf5xxx_wr_acr0 - .global mcf5xxx_wr_acr1 - .global _mcf5xxx_wr_acr1 - .global mcf5xxx_wr_acr2 - .global _mcf5xxx_wr_acr2 - .global mcf5xxx_wr_acr3 - .global _mcf5xxx_wr_acr3 - .global mcf5xxx_wr_other_sp - .global _mcf5xxx_wr_other_sp - .global mcf5xxx_wr_other_a7 - .global _mcf5xxx_wr_other_a7 - .global mcf5xxx_wr_vbr - .global _mcf5xxx_wr_vbr - .global mcf5xxx_wr_macsr - .global _mcf5xxx_wr_macsr - .global mcf5xxx_wr_mask - .global _mcf5xxx_wr_mask - .global mcf5xxx_wr_acc0 - .global _mcf5xxx_wr_acc0 - .global mcf5xxx_wr_accext01 - .global _mcf5xxx_wr_accext01 - .global mcf5xxx_wr_accext23 - .global _mcf5xxx_wr_accext23 - .global mcf5xxx_wr_acc1 - .global _mcf5xxx_wr_acc1 - .global mcf5xxx_wr_acc2 - .global _mcf5xxx_wr_acc2 - .global mcf5xxx_wr_acc3 - .global _mcf5xxx_wr_acc3 - .global mcf5xxx_wr_sr - .global _mcf5xxx_wr_sr - .global mcf5xxx_wr_rambar0 - .global _mcf5xxx_wr_rambar0 - .global mcf5xxx_wr_rambar1 - .global _mcf5xxx_wr_rambar1 - .global mcf5xxx_wr_mbar - .global _mcf5xxx_wr_mbar - .global mcf5xxx_wr_mbar0 - .global _mcf5xxx_wr_mbar0 - .global mcf5xxx_wr_mbar1 - .global _mcf5xxx_wr_mbar1 - - .text - -/********************************************************************/ -/* - * This routines changes the IPL to the value passed into the routine. - * It also returns the old IPL value back. - * Calling convention from C: - * old_ipl = asm_set_ipl(new_ipl); - * For the Diab Data C compiler, it passes return value thru D0. - * Note that only the least significant three bits of the passed - * value are used. - */ - -asm_set_ipl: -_asm_set_ipl: - link a6,#-8 - movem.l d6-d7,(sp) - - move.w sr,d7 /* current sr */ - - move.l d7,d0 /* prepare return value */ - andi.l #0x0700,d0 /* mask out IPL */ - lsr.l #8,d0 /* IPL */ - - move.l 8(a6),d6 /* get argument */ - andi.l #0x07,d6 /* least significant three bits */ - lsl.l #8,d6 /* move over to make mask */ - - andi.l #0x0000F8FF,d7 /* zero out current IPL */ - or.l d6,d7 /* place new IPL in sr */ - move.w d7,sr - - movem.l (sp),d6-d7 - lea 8(sp),sp - unlk a6 - rts - -/********************************************************************/ -/* - * These routines write to the special purpose registers in the ColdFire - * core. Since these registers are write-only in the supervisor model, - * no corresponding read routines exist. - */ - -mcf5xxx_wr_cacr: -_mcf5xxx_wr_cacr: - move.l 4(sp),d0 - .long 0x4e7b0002 /* movec d0,cacr */ - nop - rts - -mcf5xxx_wr_acr0: -_mcf5xxx_wr_acr0: - move.l 4(sp),d0 - .long 0x4e7b0004 /* movec d0,ACR0 */ - nop - rts - -mcf5xxx_wr_acr1: -_mcf5xxx_wr_acr1: - move.l 4(sp),d0 - .long 0x4e7b0005 /* movec d0,ACR1 */ - nop - rts - -mcf5xxx_wr_acr2: -_mcf5xxx_wr_acr2: - move.l 4(sp),d0 - .long 0x4e7b0006 /* movec d0,ACR2 */ - nop - rts - -mcf5xxx_wr_acr3: -_mcf5xxx_wr_acr3: - move.l 4(sp),d0 - .long 0x4e7b0007 /* movec d0,ACR3 */ - nop - rts - -mcf5xxx_wr_other_sp: -_mcf5xxx_wr_other_sp: -mcf5xxx_wr_other_a7: -_mcf5xxx_wr_other_a7: - move.l 4(sp),d0 - .long 0x4e7b0800 /* movec d0,OTHER_A7 */ - nop - rts - -mcf5xxx_wr_vbr: -_mcf5xxx_wr_vbr: - move.l 4(sp),d0 - .long 0x4e7b0801 /* movec d0,VBR */ - nop - rts - -mcf5xxx_wr_macsr: -_mcf5xxx_wr_macsr: - move.l 4(sp),d0 - .long 0x4e7b0804 /* movec d0,MACSR */ - nop - rts - -mcf5xxx_wr_mask: -_mcf5xxx_wr_mask: - move.l 4(sp),d0 - .long 0x4e7b0805 /* movec d0,MASK */ - nop - rts - -mcf5xxx_wr_acc0: -_mcf5xxx_wr_acc0: - move.l 4(sp),d0 - .long 0x4e7b0806 /* movec d0,ACC0 */ - nop - rts - -mcf5xxx_wr_accext01: -_mcf5xxx_wr_accext01: - move.l 4(sp),d0 - .long 0x4e7b0807 /* movec d0,ACCEXT01 */ - nop - rts - -mcf5xxx_wr_accext23: -_mcf5xxx_wr_accext23: - move.l 4(sp),d0 - .long 0x4e7b0808 /* movec d0,ACCEXT23 */ - nop - rts - -mcf5xxx_wr_acc1: -_mcf5xxx_wr_acc1: - move.l 4(sp),d0 - .long 0x4e7b0809 /* movec d0,ACC1 */ - nop - rts - -mcf5xxx_wr_acc2: -_mcf5xxx_wr_acc2: - move.l 4(sp),d0 - .long 0x4e7b080A /* movec d0,ACC2 */ - nop - rts - -mcf5xxx_wr_acc3: -_mcf5xxx_wr_acc3: - move.l 4(sp),d0 - .long 0x4e7b080B /* movec d0,ACC3 */ - nop - rts - -mcf5xxx_wr_sr: -_mcf5xxx_wr_sr: - move.l 4(sp),d0 - move.w d0,SR - rts - -mcf5xxx_wr_rambar0: -_mcf5xxx_wr_rambar0: - move.l 4(sp),d0 - .long 0x4e7b0C04 /* movec d0,RAMBAR0 */ - nop - rts - -mcf5xxx_wr_rambar1: -_mcf5xxx_wr_rambar1: - move.l 4(sp),d0 - .long 0x4e7b0C05 /* movec d0,RAMBAR1 */ - nop - rts - -mcf5xxx_wr_mbar: -_mcf5xxx_wr_mbar: -mcf5xxx_wr_mbar0: -_mcf5xxx_wr_mbar0: - move.l 4(sp),d0 - .long 0x4e7b0C0F /* movec d0,MBAR0 */ - nop - rts - -mcf5xxx_wr_mbar1: -_mcf5xxx_wr_mbar1: - move.l 4(sp),d0 - .long 0x4e7b0C0E /* movec d0,MBAR1 */ - nop - rts - - .end -/********************************************************************/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/newlib.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/newlib.c deleted file mode 100644 index 82ffbb0aa..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/newlib.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* ------------------------ System includes ------------------------------- */ -#include -#include -#include -#include - -/* ------------------------ FreeRTOS includes ----------------------------- */ -#include -#include - -/* ------------------------ Prototypes ------------------------------------ */ -void vSerialPutStringNOISR( xComPortHandle pxPort, - const signed portCHAR * const pcString, - unsigned portSHORT usStringLength ); - -/* ------------------------ Start implementation -------------------------- */ -void -_exit( int status ) -{ - asm volatile ( "halt" ); - - for( ;; ); -} - -pid_t -getpid( void ) -{ - return 0; -} - -int -kill( pid_t pid, int sig ) -{ - _exit( 0 ); -} - -int -close( int fd ) -{ - return 0; -} - -int -fstat( int fd, struct stat *buf ) -{ - buf->st_mode = S_IFCHR; - buf->st_blksize = 0; - return 0; -} - -ssize_t -write( int fd, const void *buf, size_t nbytes ) -{ - ssize_t res = nbytes; - extern xComPortHandle xSTDComPort; - switch ( fd ) - { - case STDERR_FILENO: - vSerialPutStringNOISR( xSTDComPort, - ( const signed portCHAR * const )buf, - ( unsigned portSHORT )nbytes ); - break; - case STDOUT_FILENO: - vSerialPutString( xSTDComPort, - ( const signed portCHAR * const)buf, - ( unsigned portSHORT )nbytes ); - break; - default: - errno = EIO; - res = -1; - break; - } - return res; -} - -int -read( int fd, void *buf, size_t nbytes ) -{ - switch ( fd ) - { - default: - errno = EIO; - return -1; - } -} - -int -isatty( int fd ) -{ - return 0; -} - -off_t -lseek( int fd, off_t offset, int whence ) -{ - errno = EIO; - return ( off_t ) - 1; -} - -extern char _end[]; -char *heap_ptr; - -void * -sbrk( ptrdiff_t nbytes ) -{ - char *base; - - if( !heap_ptr ) - heap_ptr = ( char * )&_end; - base = heap_ptr; - heap_ptr += nbytes; - - return base; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/serial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/serial.c deleted file mode 100644 index bc22a70f6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/serial.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* ------------------------ MCF523x includes ------------------------------ */ -#include "mcf5xxx.h" -#include "mcf523x.h" - -/* ------------------------ FreeRTOS includes ----------------------------- */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -#include "serial.h" - -/* ----------------------- Defines ----------------------------------------- */ -#define BAUDRATE_VALUE(fsys, baud) ( ( fsys )/(32UL * baud) ) -#define MCF_UART_VECTOR ( 64 + 13 ) -#define COM_NIFACE 1 -#define COM_BLOCK_RETRYTIME 10 - -/* ------------------------ Static functions ------------------------------ */ -static void prvSerialISR( void ); - -/* ------------------------ Static variables ------------------------------ */ -typedef struct -{ - portBASE_TYPE xInitialized; - xQueueHandle xRXChars; - xQueueHandle xTXChars; -} xComPortIF_t; - -static xComPortIF_t xComPortIF[COM_NIFACE]; - -/* ------------------------ Begin implementation -------------------------- */ -xComPortHandle -xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ - extern void ( *__RAMVEC[] ) ( ); - xComPortHandle xReturn; - portBASE_TYPE xOldIPL; - - /* Create the queues used to hold Rx and Tx characters. */ - xComPortIF[0].xRXChars = - xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE )sizeof( signed portCHAR ) ); - xComPortIF[0].xTXChars = - xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE )sizeof( signed portCHAR ) ); - - /* If the queues were created correctly then setup the serial port hardware. */ - if( ( xComPortIF[0].xRXChars != 0 ) && ( xComPortIF[0].xTXChars != 0 ) ) - { - xOldIPL = portSET_IPL( portIPL_MAX ); - - /* UART 0: Reset transmitter, receiver and mode register pointer */ - MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x3 ); - MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x2 ); - MCF_UART_UCR0 = MCF_UART_UCR_MISC( 0x1 ); - - /* Enable receive interrupts. */ - MCF_UART_UIMR0 = MCF_UART_UIMR_RXRDY_FU; - - /* 8 Databits, 1 Stopbit and no parity */ - MCF_UART_UMR0 = MCF_UART_UMR_PM( 0x3 ) | MCF_UART_UMR_SB( 0x7 ) | MCF_UART_UMR_BC( 0x3 ); - - /* UART 0 Clocking */ - MCF_UART_UCSR0 = MCF_UART_UCSR_RCS( 0xd ) | MCF_UART_UCSR_TCS( 0xd ); - MCF_UART_UBG10 = BAUDRATE_VALUE( FSYS_2, ulWantedBaud ) >> 8U; - MCF_UART_UBG20 = BAUDRATE_VALUE( FSYS_2, ulWantedBaud ) & 0xFFU; - - /* UART 0: Enable interrupts */ - __RAMVEC[MCF_UART_VECTOR] = prvSerialISR; - MCF_INTC0_ICR13 = MCF_INTC0_ICRn_IL( 0x2 ) | MCF_INTC0_ICRn_IP( 0x1 ); - MCF_INTC0_IMRL &= ~MCF_INTC0_IMRL_INT_MASK13; - - /* UART 0 Miscellaneous */ - MCF_UART_UACR0 = 0; - - /* UART 0: Enable pins */ - MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_U0RXD | MCF_GPIO_PAR_UART_PAR_U0TXD; - - /* Enable the UART. */ - MCF_UART_UCR0 = MCF_UART_UCR_RXC( 0x1 ) | MCF_UART_UCR_TXC( 0x1 ); - - xComPortIF[0].xInitialized = TRUE; - xReturn = ( xComPortHandle ) & xComPortIF[0]; - - ( void )portSET_IPL( xOldIPL ); - } - else - { - xReturn = ( xComPortHandle ) 0; - } - - return xReturn; -} - -signed portBASE_TYPE -xSerialGetChar( xComPortHandle pxPort, signed portCHAR * pcRxedChar, portTickType xBlockTime ) -{ - int i; - portBASE_TYPE xResult = pdFALSE; - - /* Lookup the correct interface. */ - for( i = 0; i < COM_NIFACE; i++ ) - { - if( pxPort == ( xComPortHandle ) & xComPortIF[i] ) - { - break; - } - } - /* This COM port is available. */ - if( ( i != COM_NIFACE ) && xComPortIF[i].xInitialized ) - { - /* Get the next character from the buffer. Return false if no characters - * are available, or arrive before xBlockTime expires. - */ - if( xQueueReceive( xComPortIF[i].xRXChars, pcRxedChar, xBlockTime ) ) - { - xResult = pdTRUE; - } - } - return xResult; -} - -void -vSerialPutString( xComPortHandle pxPort, const signed portCHAR * - const pcString, unsigned portSHORT usStringLength ) -{ - int i; - signed portCHAR *pChNext; - - /* Send each character in the string, one at a time. */ - pChNext = ( signed portCHAR * )pcString; - for( i = 0; i < usStringLength; i++ ) - { - /* Block until character has been transmitted. */ - while( xSerialPutChar( pxPort, *pChNext, COM_BLOCK_RETRYTIME ) != pdTRUE ); - pChNext++; - } -} - -signed portBASE_TYPE -xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ - int i; - portBASE_TYPE xResult = pdFALSE; - portBASE_TYPE xOldIPL; - - /* Lookup the correct interface. */ - for( i = 0; i < COM_NIFACE; i++ ) - { - if( pxPort == ( xComPortHandle ) & xComPortIF[i] ) - { - break; - } - } - /* This COM port is available. */ - if( ( i != COM_NIFACE ) && xComPortIF[i].xInitialized ) - { - /* Place the character in the queue of characters to be transmitted. */ - if( xQueueSend( xComPortIF[i].xTXChars, &cOutChar, xBlockTime ) == pdPASS ) - { - MCF_UART_UIMR0 = MCF_UART_UIMR_TXRDY | MCF_UART_UIMR_RXRDY_FU; - /* Turn on the Tx interrupt so the ISR will remove the character from the - * queue and send it. */ - xResult = pdTRUE; - } - } - return xResult; -} - -signed portBASE_TYPE -xSerialPutCharNOISR( xComPortHandle pxPort, signed portCHAR cOutChar ) -{ - int i; - portBASE_TYPE xResult = pdFALSE; - portBASE_TYPE xOldIPL = portSET_IPL( portIPL_MAX ); - - /* Lookup the correct interface. */ - for( i = 0; i < COM_NIFACE; i++ ) - { - if( pxPort == ( xComPortHandle ) & xComPortIF[i] ) - { - break; - } - } - /* This COM port is available. Support for this only available for COM1 right now. */ - if( ( i != COM_NIFACE ) && ( i == 0 ) ) - { - /* Wait until the transmit buffer is ready. */ - while( !( MCF_UART_USR0 & MCF_UART_USR_TXRDY ) ); - /* Place the character in the transmit buffer. */ - MCF_UART_UTB0 = cOutChar; - xResult = pdTRUE; - } - ( void )portSET_IPL( xOldIPL ); - return xResult; -} - -void -vSerialPutStringNOISR( xComPortHandle pxPort, const signed portCHAR * - const pcString, unsigned portSHORT usStringLength ) -{ - int i; - signed portCHAR *pChNext; - portBASE_TYPE xOldIPL = portSET_IPL( portIPL_MAX ); - - /* Send each character in the string, one at a time. */ - pChNext = ( signed portCHAR * )pcString; - for( i = 0; i < usStringLength; i++ ) - { - /* Block until character has been transmitted. */ - while( xSerialPutCharNOISR( pxPort, *pChNext ) != pdTRUE ); - pChNext++; - } - ( void )portSET_IPL( xOldIPL ); -} - -void -vSerialClose( xComPortHandle xPort ) -{ - /* Not supported as not required by the demo application. */ -} - -void -prvSerialISR( void ) -{ - static signed portCHAR cChar; - static portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE; - - /* We have to remvoe the effect of the GCC. Please note that the - * __attribute__ ((interrupt_handler)) does not work here because we - * have to do the storing of the registers ourself. Another problem - * is the usage of a frame pointer which is unlinked on entry. - */ -#if _GCC_USES_FP == 1 - asm volatile ( "unlk %fp\n\t" ); -#endif - /* This ISR can cause a context switch, so the first statement must be - * a call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any - * variable declarations. - */ - portENTER_SWITCHING_ISR( ); - - /* Ready to send a character from the buffer. */ - if( MCF_UART_USR0 & MCF_UART_USR_TXRDY ) - { - /* Transmit buffer is ready. Test if there are characters available. */ - if( xQueueReceiveFromISR( xComPortIF[0].xTXChars, &cChar, &xTaskWokenByTx ) == pdTRUE ) - { - /* A character was retrieved from the queue so can be sent. */ - MCF_UART_UTB0 = cChar; - } - else - { - /* Leave only receiver enabled. */ - MCF_UART_UIMR0 = MCF_UART_UIMR_RXRDY_FU; - } - } - if( MCF_UART_USR0 & MCF_UART_USR_RXRDY ) - { - cChar = MCF_UART_URB0; - xTaskWokenByRx = xQueueSendFromISR( xComPortIF[0].xRXChars, &cChar, xTaskWokenByRx ); - } - /* Exit the ISR. If a task was woken by either a character being - * or transmitted then a context switch will occur. - */ - portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/vector.S b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/vector.S deleted file mode 100644 index 4c278a64c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MCF5235TCP/system/vector.S +++ /dev/null @@ -1,302 +0,0 @@ -/* - FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - .extern __stack - .extern start - .extern fec_handler - .extern fec_if - .extern decrement_timers - .global __RAMVEC - .global __ROMVEC - - .equ MCF_PIT_PCSR0, IPSBAR + 0x150000 - .equ MCF_PIT_PCSR_PIF, 0x0004 - - .section .vector_rom, "x" -__ROMVEC: - .long __stack /* Reset: Initial Stack Pointer */ - .long start /* Reset: Initial Program Counter */ - .long VecDefault /* Bus Error */ - .long VecDefault /* Address Error */ - .long VecDefault /* Illegal Instruction */ - .long VecDefault /* Zero Divison */ - .space 4 /* reserved */ - .space 4 /* reserved */ - .long VecDefault /* Privilege Violation */ - .long VecDefault /* Trace */ - .long VecDefault /* Unimplemented line-a opcode */ - .long VecDefault /* Unimplemented line-b opcode */ - .long VecDefault /* Non-PC breakpoint debug interrupt */ - .long VecDefault /* PC breakpoint debug interrupt */ - .long VecDefault /* Format Error */ - .long VecDefault /* Uninitialized Interrupt */ - .org 0x60 - .long IRQSpurious /* Spurious Interrupt */ - .long IRQDefault /* Level 1 Interrupt */ - .long IRQDefault /* Level 2 Interrupt */ - .long IRQDefault /* Level 3 Interrupt */ - .long IRQDefault /* Level 4 Interrupt */ - .long IRQDefault /* Level 5 Interrupt */ - .long IRQDefault /* Level 6 Interrupt */ - .long IRQDefault /* Level 7 Interrupt */ - .org 0x80 - .long TrapDefault /* TRAP 0 */ - .long TrapDefault /* TRAP 1 */ - .long TrapDefault /* TRAP 2 */ - .long TrapDefault /* TRAP 3 */ - .long TrapDefault /* TRAP 4 */ - .long TrapDefault /* TRAP 5 */ - .long TrapDefault /* TRAP 6 */ - .long TrapDefault /* TRAP 7 */ - .long TrapDefault /* TRAP 8 */ - .long TrapDefault /* TRAP 9 */ - .long TrapDefault /* TRAP 10 */ - .long TrapDefault /* TRAP 11 */ - .long TrapDefault /* TRAP 12 */ - .long TrapDefault /* TRAP 13 */ - .long TrapDefault /* TRAP 14 */ - .long TrapDefault /* TRAP 15 */ - .org 0x100 - .long IRQDefault /* User-Defined Interrupt 0 */ - .long IRQDefault /* User-Defined Interrupt 1 */ - .long IRQDefault /* User-Defined Interrupt 2 */ - .long IRQDefault /* User-Defined Interrupt 3 */ - .long IRQDefault /* User-Defined Interrupt 4 */ - .long IRQDefault /* User-Defined Interrupt 5 */ - .long IRQDefault /* User-Defined Interrupt 6 */ - .long IRQDefault /* User-Defined Interrupt 7 */ - .long IRQDefault /* User-Defined Interrupt 8 */ - .long IRQDefault /* User-Defined Interrupt 9 */ - .long IRQDefault /* User-Defined Interrupt 10 */ - .long IRQDefault /* User-Defined Interrupt 11 */ - .long IRQDefault /* User-Defined Interrupt 12 */ - .long IRQDefault /* User-Defined Interrupt 13 */ - .long IRQDefault /* User-Defined Interrupt 14 */ - .long IRQDefault /* User-Defined Interrupt 15 */ - .long IRQDefault /* User-Defined Interrupt 16 */ - .long IRQDefault /* User-Defined Interrupt 17 */ - .long IRQDefault /* User-Defined Interrupt 18 */ - .long IRQDefault /* User-Defined Interrupt 19 */ - .long IRQDefault /* User-Defined Interrupt 20 */ - .long IRQDefault /* User-Defined Interrupt 21 */ - .long IRQDefault /* User-Defined Interrupt 22 */ - .long IRQDefault /* Transmit frame interrupt */ - .long IRQDefault /* Transmit buffer interrupt */ - .long IRQDefault /* Transmit FIFO underrun */ - .long IRQDefault /* Collision retry limit */ - .long IRQDefault /* Receive frame interrupt */ - .long IRQDefault /* Receive buffer interrupt */ - .long IRQDefault /* MII interrupt */ - .long IRQDefault /* Late collision */ - .long IRQDefault /* Heartbeat error */ - .long IRQDefault /* Graceful stop complete */ - .long IRQDefault /* Ethernet bus error */ - .long IRQDefault /* Babbling transmit error */ - .long IRQDefault /* Babbling receive error */ - .long IRQDefault /* Timer interrupt */ - .long IRQDefault /* User-Defined Interrupt 37 */ - .long IRQDefault /* User-Defined Interrupt 38 */ - .long IRQDefault /* User-Defined Interrupt 39 */ - .long IRQDefault /* User-Defined Interrupt 40 */ - .long IRQDefault /* User-Defined Interrupt 41 */ - .long IRQDefault /* User-Defined Interrupt 42 */ - .long IRQDefault /* User-Defined Interrupt 43 */ - .long IRQDefault /* User-Defined Interrupt 44 */ - .long IRQDefault /* User-Defined Interrupt 45 */ - .long IRQDefault /* User-Defined Interrupt 46 */ - .long IRQDefault /* User-Defined Interrupt 47 */ - .long IRQDefault /* User-Defined Interrupt 48 */ - .long IRQDefault /* User-Defined Interrupt 49 */ - .long IRQDefault /* User-Defined Interrupt 50 */ - .long IRQDefault /* User-Defined Interrupt 51 */ - .long IRQDefault /* User-Defined Interrupt 52 */ - .long IRQDefault /* User-Defined Interrupt 53 */ - .long IRQDefault /* User-Defined Interrupt 54 */ - .long IRQDefault /* User-Defined Interrupt 55 */ - .long IRQDefault /* User-Defined Interrupt 56 */ - .long IRQDefault /* User-Defined Interrupt 57 */ - .long IRQDefault /* User-Defined Interrupt 58 */ - .long IRQDefault /* User-Defined Interrupt 59 */ - .long IRQDefault /* User-Defined Interrupt 60 */ - .long IRQDefault /* User-Defined Interrupt 61 */ - .long IRQDefault /* User-Defined Interrupt 62 */ - .long IRQDefault /* User-Defined Interrupt 63 */ - .long IRQDefault /* User-Defined Interrupt 64 */ - .long IRQDefault /* User-Defined Interrupt 65 */ - .long IRQDefault /* User-Defined Interrupt 66 */ - .long IRQDefault /* User-Defined Interrupt 67 */ - .long IRQDefault /* User-Defined Interrupt 68 */ - .long IRQDefault /* User-Defined Interrupt 69 */ - .long IRQDefault /* User-Defined Interrupt 70 */ - .long IRQDefault /* User-Defined Interrupt 71 */ - .long IRQDefault /* User-Defined Interrupt 72 */ - .long IRQDefault /* User-Defined Interrupt 73 */ - .long IRQDefault /* User-Defined Interrupt 74 */ - .long IRQDefault /* User-Defined Interrupt 75 */ - .long IRQDefault /* User-Defined Interrupt 76 */ - .long IRQDefault /* User-Defined Interrupt 77 */ - .long IRQDefault /* User-Defined Interrupt 78 */ - .long IRQDefault /* User-Defined Interrupt 79 */ - .long IRQDefault /* User-Defined Interrupt 80 */ - .long IRQDefault /* User-Defined Interrupt 81 */ - .long IRQDefault /* User-Defined Interrupt 82 */ - .long IRQDefault /* User-Defined Interrupt 83 */ - .long IRQDefault /* User-Defined Interrupt 84 */ - .long IRQDefault /* User-Defined Interrupt 85 */ - .long IRQDefault /* User-Defined Interrupt 86 */ - .long IRQDefault /* User-Defined Interrupt 87 */ - .long IRQDefault /* User-Defined Interrupt 88 */ - .long IRQDefault /* User-Defined Interrupt 89 */ - .long IRQDefault /* User-Defined Interrupt 90 */ - .long IRQDefault /* User-Defined Interrupt 91 */ - .long IRQDefault /* User-Defined Interrupt 92 */ - .long IRQDefault /* User-Defined Interrupt 93 */ - .long IRQDefault /* User-Defined Interrupt 94 */ - .long IRQDefault /* User-Defined Interrupt 95 */ - .long IRQDefault /* User-Defined Interrupt 96 */ - .long IRQDefault /* User-Defined Interrupt 97 */ - .long IRQDefault /* User-Defined Interrupt 98 */ - .long IRQDefault /* User-Defined Interrupt 99 */ - .long IRQDefault /* User-Defined Interrupt 100 */ - .long IRQDefault /* User-Defined Interrupt 101 */ - .long IRQDefault /* User-Defined Interrupt 102 */ - .long IRQDefault /* User-Defined Interrupt 103 */ - .long IRQDefault /* User-Defined Interrupt 104 */ - .long IRQDefault /* User-Defined Interrupt 105 */ - .long IRQDefault /* User-Defined Interrupt 106 */ - .long IRQDefault /* User-Defined Interrupt 107 */ - .long IRQDefault /* User-Defined Interrupt 108 */ - .long IRQDefault /* User-Defined Interrupt 109 */ - .long IRQDefault /* User-Defined Interrupt 110 */ - .long IRQDefault /* User-Defined Interrupt 111 */ - .long IRQDefault /* User-Defined Interrupt 112 */ - .long IRQDefault /* User-Defined Interrupt 113 */ - .long IRQDefault /* User-Defined Interrupt 114 */ - .long IRQDefault /* User-Defined Interrupt 115 */ - .long IRQDefault /* User-Defined Interrupt 116 */ - .long IRQDefault /* User-Defined Interrupt 117 */ - .long IRQDefault /* User-Defined Interrupt 118 */ - .long IRQDefault /* User-Defined Interrupt 119 */ - .long IRQDefault /* User-Defined Interrupt 120 */ - .long IRQDefault /* User-Defined Interrupt 121 */ - .long IRQDefault /* User-Defined Interrupt 122 */ - .long IRQDefault /* User-Defined Interrupt 123 */ - .long IRQDefault /* User-Defined Interrupt 124 */ - .long IRQDefault /* User-Defined Interrupt 125 */ - .long IRQDefault /* User-Defined Interrupt 126 */ - .long IRQDefault /* User-Defined Interrupt 127 */ - .long IRQDefault /* User-Defined Interrupt 128 */ - .long IRQDefault /* User-Defined Interrupt 129 */ - .long IRQDefault /* User-Defined Interrupt 130 */ - .long IRQDefault /* User-Defined Interrupt 131 */ - .long IRQDefault /* User-Defined Interrupt 132 */ - .long IRQDefault /* User-Defined Interrupt 133 */ - .long IRQDefault /* User-Defined Interrupt 134 */ - .long IRQDefault /* User-Defined Interrupt 135 */ - .long IRQDefault /* User-Defined Interrupt 136 */ - .long IRQDefault /* User-Defined Interrupt 137 */ - .long IRQDefault /* User-Defined Interrupt 138 */ - .long IRQDefault /* User-Defined Interrupt 139 */ - .long IRQDefault /* User-Defined Interrupt 140 */ - .long IRQDefault /* User-Defined Interrupt 141 */ - .long IRQDefault /* User-Defined Interrupt 142 */ - .long IRQDefault /* User-Defined Interrupt 143 */ - .long IRQDefault /* User-Defined Interrupt 144 */ - .long IRQDefault /* User-Defined Interrupt 145 */ - .long IRQDefault /* User-Defined Interrupt 146 */ - .long IRQDefault /* User-Defined Interrupt 147 */ - .long IRQDefault /* User-Defined Interrupt 148 */ - .long IRQDefault /* User-Defined Interrupt 149 */ - .long IRQDefault /* User-Defined Interrupt 150 */ - .long IRQDefault /* User-Defined Interrupt 151 */ - .long IRQDefault /* User-Defined Interrupt 152 */ - .long IRQDefault /* User-Defined Interrupt 153 */ - .long IRQDefault /* User-Defined Interrupt 154 */ - .long IRQDefault /* User-Defined Interrupt 155 */ - .long IRQDefault /* User-Defined Interrupt 156 */ - .long IRQDefault /* User-Defined Interrupt 157 */ - .long IRQDefault /* User-Defined Interrupt 158 */ - .long IRQDefault /* User-Defined Interrupt 159 */ - .long IRQDefault /* User-Defined Interrupt 160 */ - .long IRQDefault /* User-Defined Interrupt 161 */ - .long IRQDefault /* User-Defined Interrupt 162 */ - .long IRQDefault /* User-Defined Interrupt 163 */ - .long IRQDefault /* User-Defined Interrupt 164 */ - .long IRQDefault /* User-Defined Interrupt 165 */ - .long IRQDefault /* User-Defined Interrupt 166 */ - .long IRQDefault /* User-Defined Interrupt 167 */ - .long IRQDefault /* User-Defined Interrupt 168 */ - .long IRQDefault /* User-Defined Interrupt 169 */ - .long IRQDefault /* User-Defined Interrupt 170 */ - .long IRQDefault /* User-Defined Interrupt 171 */ - .long IRQDefault /* User-Defined Interrupt 172 */ - .long IRQDefault /* User-Defined Interrupt 173 */ - .long IRQDefault /* User-Defined Interrupt 174 */ - .long IRQDefault /* User-Defined Interrupt 175 */ - .long IRQDefault /* User-Defined Interrupt 176 */ - .long IRQDefault /* User-Defined Interrupt 177 */ - .long IRQDefault /* User-Defined Interrupt 178 */ - .long IRQDefault /* User-Defined Interrupt 179 */ - .long IRQDefault /* User-Defined Interrupt 180 */ - .long IRQDefault /* User-Defined Interrupt 181 */ - .long IRQDefault /* User-Defined Interrupt 182 */ - .long IRQDefault /* User-Defined Interrupt 183 */ - .long IRQDefault /* User-Defined Interrupt 184 */ - .long IRQDefault /* User-Defined Interrupt 185 */ - .long IRQDefault /* User-Defined Interrupt 186 */ - .long IRQDefault /* User-Defined Interrupt 187 */ - .long IRQDefault /* User-Defined Interrupt 188 */ - .long IRQDefault /* User-Defined Interrupt 189 */ - .long IRQDefault /* User-Defined Interrupt 190 */ - .long IRQDefault /* User-Defined Interrupt 191 */ - .org 0x00000400 - - .section .vector_ram -__RAMVEC: - .space 0x400 - - .section .text -VecDefault: - halt - bra VecDefault - -IRQDefault: - halt - bra IRQDefault - -IRQSpurious: - halt - bra IRQSpurious - -TrapDefault: - halt - bra TrapDefault diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/Makefile b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/Makefile deleted file mode 100644 index 8ccec1afb..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/Makefile +++ /dev/null @@ -1,80 +0,0 @@ -# -# FreeModbus MSP430 port Makefile -# -# Copyright (c) 2006 Christian Walter, Vienna 2006. -# -# $Id: Makefile,v 1.3 2007/06/12 06:42:01 wolti Exp $ -# -# --------------------------------------------------------------------------- - -BASE = /cygdrive/c/mspgcc -CC = $(BASE)/bin/msp430-gcc -LD = $(BASE)/bin/msp430-ld -CXX = $(BASE)/bin/msp430-g++ -OBJCOPY = $(BASE)/bin/msp430-objcopy -SIZE = $(BASE)/bin/msp430-size -INSIGHT = $(BASE)/bin/msp430-insight -GDBPROXY = $(BASE)/bin/msp430-gdbproxy - -MCU = msp430x149 -MB_INC = -Iport -I../../modbus/rtu -I../../modbus/ascii \ - -I../../modbus/include -CFLAGS = -MD -g -mmcu=$(MCU) -Wall -D'FSYS_2=25000000UL' -CFLAGS += -I. -Isystem $(MB_INC) -ASFLAGS = -MD -g -mmcu=$(MCU) -LDFLAGS = -g -mmcu=$(MCU) -TGT = demo - -MB_SRC = $(addprefix ../../modbus/, mb.c ) -MB_RTU_SRC = $(addprefix ../../modbus/rtu/, mbrtu.c mbcrc.c ) -MB_ASCII_SRC= $(addprefix ../../modbus/ascii/, mbascii.c ) -MB_FUNC_SRC = $(addprefix ../../modbus/functions/, mbfunccoils.c \ - mbfuncdiag.c mbfuncholding.c mbfuncinput.c mbfuncother.c \ - mbfuncdisc.c mbutils.c) -PORT_SRC = $(addprefix port/, portserial.c porttimer.c portevent.c ) -CSRC = demo.c \ - $(MB_SRC) $(MB_RTU_SRC) $(MB_ASCII_SRC) $(MB_FUNC_SRC) \ - $(PORT_SRC) -ASRC = system/dco-gcc.S - -OBJS = $(CSRC:.c=.o) $(ASRC:.S=.o) -DEPS = $(OBJS:.o=.d) -BIN = $(TGT).elf - -.PHONY: clean all - -all: $(BIN) - -flash-programm: $(TGT).elf - -flash-verify: - -flash-erase: - -proxy: - $(GDBPROXY) --port=2000 msp430 -debug: - $(INSIGHT) --command=msp430.gdb --se=$(TGT).elf - -$(BIN): $(OBJS) - $(CC) $(LDFLAGS) $(OBJS) $(LDLIBS) -o $@ - -clean: - rm -f $(DEPS) - rm -f $(OBJS) - rm -f $(BIN) $(TGT).map - -# --------------------------------------------------------------------------- -# rules for code generation -# --------------------------------------------------------------------------- -%.o: %.c - $(CC) $(CFLAGS) -o $@ -c $< - -%.o: %.S - $(CC) $(ASFLAGS) -o $@ -c $< - -# --------------------------------------------------------------------------- -# # compiler generated dependencies -# --------------------------------------------------------------------------- --include $(DEPS) - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/README.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/README.txt deleted file mode 100644 index c9f2d93d9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/README.txt +++ /dev/null @@ -1,51 +0,0 @@ - - FREEMODBUS 1.1 MSP430 PORT - ========================== - -REQUIREMENTS -============ - -This demo application provides a port for the MSP430 series of processors -from Text Instruments. The port was done using the MSP430-P169 from -Olimex[1] which features a MSP430F169 MCU. -It requires a wired serial port to a host processor and a Modbus Master -Software on the PC side to be useful. Demo versions of Modbus Masters -can be found in [2] and [3]. - -INSTALLATION -============ - -SOURCE -====== - -TESTING -======= - -Start the Modbus Sample Application and test if the input registers starting -at protocol address 1000 can be read. There are four registers value available -and the output should look like: - -Polling slave (Ctrl-C to stop) ... -[1000]: 6474 -[1001]: 0 -[1002]: 0 -[1003]: 0 -Polling slave (Ctrl-C to stop) ... -[1000]: -8831 -[1001]: 0 -[1002]: 0 -[1003]: 0 -Polling slave (Ctrl-C to stop) ... - -The simple testing utility used in the 'demo_rtu.bat' script can be found -at [4]. - -PROBLEMS -======== - -[1] Olimex MSP430-P169 kit: http://www.olimex.com/dev/msp-p169.html -[2] WinTech ModScan32: http://www.win-tech.com/html/modscan32.htm -[3] Modus Poll: http://www.modbustools.com/modbus_poll.asp -[4] FieldTalk Modpoll: http://www.focus-sw.com/fieldtalk/modpoll.html - -Version: $Id: README.txt,v 1.1 2006/11/19 03:00:33 wolti Exp $ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/demo.c deleted file mode 100644 index 334814fed..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/demo.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * FreeModbus Libary: MSP430 Demo Application - * Copyright (C) 2006 Christian Walter - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Platform includes --------------------------------*/ -#include "port.h" -#include "dco.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define REG_INPUT_START 1000 -#define REG_INPUT_NREGS 4 -#define REG_HOLDING_START 1000 -#define REG_HOLDING_NREGS 130 - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegInputStart = REG_INPUT_START; -static USHORT usRegInputBuf[REG_INPUT_NREGS]; -static USHORT usRegHoldingStart = REG_HOLDING_START; -static USHORT usRegHoldingBuf[REG_HOLDING_NREGS]; - -/* ----------------------- Start implementation -----------------------------*/ -int -main( void ) -{ - eMBErrorCode eStatus; - volatile USHORT usACLKCnt; - - /* Stop Watchdog Timer. */ - WDTCTL = WDTPW + WDTHOLD; - - /* Delay for ACLK startup. */ - for( usACLKCnt = 0xFFFF; usACLKCnt != 0; usACLKCnt-- ); - if( cTISetDCO( TI_DCO_4MHZ ) == TI_DCO_NO_ERROR ) - { - _EINT( ); - - /* Initialize Protocol Stack. */ - if( ( eStatus = eMBInit( MB_RTU, 0x0A, 0, 38400, MB_PAR_EVEN ) ) != MB_ENOERR ) - { - } - /* Enable the Modbus Protocol Stack. */ - else if( ( eStatus = eMBEnable( ) ) != MB_ENOERR ) - { - } - else - { - for( ;; ) - { - ( void )eMBPoll( ); - - /* Here we simply count the number of poll cycles. */ - usRegInputBuf[0]++; - } - } - } - for( ;; ); -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_HOLDING_START ) && - ( usAddress + usNRegs <= REG_HOLDING_START + REG_HOLDING_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegHoldingStart ); - switch ( eMode ) - { - /* Pass current register values to the protocol stack. */ - case MB_REG_READ: - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegHoldingBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegHoldingBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - break; - - /* Update current register values with new values from the - * protocol stack. */ - case MB_REG_WRITE: - while( usNRegs > 0 ) - { - usRegHoldingBuf[iRegIndex] = *pucRegBuffer++ << 8; - usRegHoldingBuf[iRegIndex] |= *pucRegBuffer++; - iRegIndex++; - usNRegs--; - } - } - } - else - { - eStatus = MB_ENOREG; - } - return eStatus; -} - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/demo.hzp b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/demo.hzp deleted file mode 100644 index 765c305ad..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/demo.hzp +++ /dev/null @@ -1,56 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/demo.hzs b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/demo.hzs deleted file mode 100644 index 40b433efd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/demo.hzs +++ /dev/null @@ -1,82 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/demo_rtu.sh b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/demo_rtu.sh deleted file mode 100644 index 76076a9c2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/demo_rtu.sh +++ /dev/null @@ -1 +0,0 @@ -../../tools/modpoll -m rtu -a 10 -r 1000 -c 4 -t 3 -b 38400 -d 8 -p even /dev/ttyUSB0 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/doc/timing-snd-rcv.png b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/doc/timing-snd-rcv.png deleted file mode 100644 index e22efd70a..000000000 Binary files a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/doc/timing-snd-rcv.png and /dev/null differ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/msp430.gdb b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/msp430.gdb deleted file mode 100644 index be6c29d37..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/msp430.gdb +++ /dev/null @@ -1,9 +0,0 @@ -define setup-and-load - set remoteaddresssize 16 - set remotetimeout 999999 - set download-write-size 512 - set remote memory-write-packet-size 512 - set remote memory-write-packet-size fixed - set remote memory-read-packet-size 512 - set remote memory-read-packet-size fixed -end diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/port/port.h deleted file mode 100644 index 6b05edcc5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/port/port.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * FreeModbus Libary: MSP430 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -/* ----------------------- Platform includes --------------------------------*/ - -#include -#if defined (__GNUC__) -#include -#endif -#undef CHAR - -/* ----------------------- Defines ------------------------------------------*/ -#define INLINE -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#define ENTER_CRITICAL_SECTION( ) EnterCriticalSection( ) -#define EXIT_CRITICAL_SECTION( ) ExitCriticalSection( ) -#define assert( expr ) - -#define SMCLK ( 4000000UL ) -#define ACLK ( 32768UL ) - -typedef char BOOL; - -typedef unsigned char UCHAR; - -typedef char CHAR; - -typedef unsigned short USHORT; -typedef short SHORT; - -typedef unsigned long ULONG; -typedef long LONG; - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -void EnterCriticalSection( void ); -void ExitCriticalSection( void ); - - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/port/portevent.c deleted file mode 100644 index b55df1928..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/port/portevent.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * FreeModbus Libary: MSP430 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static eMBEventType eQueuedEvent; -static BOOL xEventInQueue; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - xEventInQueue = FALSE; - return TRUE; -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - xEventInQueue = TRUE; - eQueuedEvent = eEvent; - return TRUE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - BOOL xEventHappened = FALSE; - - if( xEventInQueue ) - { - *eEvent = eQueuedEvent; - xEventInQueue = FALSE; - xEventHappened = TRUE; - } - return xEventHappened; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/port/portserial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/port/portserial.c deleted file mode 100644 index 8171b4844..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/port/portserial.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * FreeModbus Libary: MSP430 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Platform includes --------------------------------*/ -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define U0_CHAR ( 0x10 ) /* Data 0:7-bits / 1:8-bits */ - -#define DEBUG_PERFORMANCE ( 1 ) - -#if DEBUG_PERFORMANCE == 1 -#define DEBUG_PIN_RX ( 0 ) -#define DEBUG_PIN_TX ( 1 ) -#define DEBUG_PORT_DIR ( P1DIR ) -#define DEBUG_PORT_OUT ( P1OUT ) -#define DEBUG_INIT( ) \ - do \ - { \ - DEBUG_PORT_DIR |= ( 1 << DEBUG_PIN_RX ) | ( 1 << DEBUG_PIN_TX ); \ - DEBUG_PORT_OUT &= ~( ( 1 << DEBUG_PIN_RX ) | ( 1 << DEBUG_PIN_TX ) ); \ - } while( 0 ); -#define DEBUG_TOGGLE_RX( ) DEBUG_PORT_OUT ^= ( 1 << DEBUG_PIN_RX ) -#define DEBUG_TOGGLE_TX( ) DEBUG_PORT_OUT ^= ( 1 << DEBUG_PIN_TX ) - -#else - -#define DEBUG_INIT( ) -#define DEBUG_TOGGLE_RX( ) -#define DEBUG_TOGGLE_TX( ) -#endif - -/* ----------------------- Static variables ---------------------------------*/ -UCHAR ucGIEWasEnabled = FALSE; -UCHAR ucCriticalNesting = 0x00; - -/* ----------------------- Start implementation -----------------------------*/ -void -vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable ) -{ - ENTER_CRITICAL_SECTION( ); - if( xRxEnable ) - { - IE1 |= URXIE0; - } - else - { - IE1 &= ~URXIE0; - } - if( xTxEnable ) - { - IE1 |= UTXIE0; - IFG1 |= UTXIFG0; - } - else - { - IE1 &= ~UTXIE0; - } - EXIT_CRITICAL_SECTION( ); -} - -BOOL -xMBPortSerialInit( UCHAR ucPort, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity ) -{ - BOOL bInitialized = TRUE; - USHORT UxCTL = 0; - USHORT UxBR = ( USHORT ) ( SMCLK / ulBaudRate ); - - switch ( eParity ) - { - case MB_PAR_NONE: - break; - case MB_PAR_ODD: - UxCTL |= PENA; - break; - case MB_PAR_EVEN: - UxCTL |= PENA | PEV; - break; - } - switch ( ucDataBits ) - { - case 8: - UxCTL |= U0_CHAR; - break; - case 7: - break; - default: - bInitialized = FALSE; - } - if( bInitialized ) - { - ENTER_CRITICAL_SECTION( ); - /* Reset USART */ - U0CTL |= SWRST; - /* Initialize all UART registers */ - U0CTL = UxCTL | SWRST; - /* SSELx = 11 = SMCLK. Use only if PLL is synchronized ! */ - U0TCTL = SSEL1 | SSEL0; - U0RCTL = URXEIE; - /* Configure USART0 Baudrate Registers. */ - U0BR0 = ( UxBR & 0xFF ); - U0BR1 = ( UxBR >> 8 ); - U0MCTL = 0; - /* Enable UART */ - ME1 |= UTXE0 | URXE0; - /* Clear reset flag. */ - U0CTL &= ~SWRST; - - /* USART0 TXD/RXD */ - P3SEL |= 0x30; - P3DIR |= 0x10; - - EXIT_CRITICAL_SECTION( ); - - DEBUG_INIT( ); - } - return bInitialized; -} - -BOOL -xMBPortSerialPutByte( CHAR ucByte ) -{ - TXBUF0 = ucByte; - return TRUE; -} - -BOOL -xMBPortSerialGetByte( CHAR * pucByte ) -{ - *pucByte = RXBUF0; - return TRUE; -} - -#if defined (__GNUC__) -interrupt (USART0RX_VECTOR) prvvMBSerialRXIRQHandler( void ) -#else -void -prvvMBSerialRXIRQHandler( void ) __interrupt[USART0RX_VECTOR] -#endif -{ - DEBUG_TOGGLE_RX( ); - pxMBFrameCBByteReceived( ); -} - -#if defined (__GNUC__) -interrupt (USART0TX_VECTOR) prvvMBSerialTXIRQHandler( void ) -#else -void -prvvMBSerialTXIRQHandler( void ) __interrupt[USART0TX_VECTOR] -#endif -{ - DEBUG_TOGGLE_TX( ); - pxMBFrameCBTransmitterEmpty( ); -} - -void -EnterCriticalSection( void ) -{ - USHORT usOldSR; - if( ucCriticalNesting == 0 ) - { -#if defined (__GNUC__) - usOldSR = READ_SR; - _DINT( ); -#else - usOldSR = _DINT( ); -#endif - ucGIEWasEnabled = usOldSR & GIE ? TRUE : FALSE; - } - ucCriticalNesting++; -} - -void -ExitCriticalSection( void ) -{ - ucCriticalNesting--; - if( ucCriticalNesting == 0 ) - { - if( ucGIEWasEnabled ) - { - _EINT( ); - } - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/port/porttimer.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/port/porttimer.c deleted file mode 100644 index bb361f903..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/port/porttimer.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * FreeModbus Libary: MSP430 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Platform includes --------------------------------*/ -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -/* Timer ticks are counted in multiples of 50us. Therefore 20000 ticks are - * one second. - */ -#define MB_TIMER_TICKS ( 20000L ) - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usTimerOCRADelta; -static USHORT usTimerOCRBDelta; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortTimersInit( USHORT usTim1Timeout50us ) -{ - BOOL bInitialized = FALSE; - ULONG ulReloadValue = ( ACLK * ( ULONG )usTim1Timeout50us ) / MB_TIMER_TICKS; - - if( ulReloadValue <= 1 ) - { - ulReloadValue = 1; - } - else - { - ulReloadValue -= 1; - } - - if( ulReloadValue < 0xFFFE ) - { - /* Timer A clock source is ACLK, Start disabled. */ - TACTL = TASSEL0; - TACCR0 = ( USHORT ) ulReloadValue; - /* Enable Timer A caputer compare interrupt. */ - TACCTL0 = CCIE; - - bInitialized = TRUE; - } - return bInitialized; -} - -void -vMBPortTimersEnable( void ) -{ - /* Reset timer counter and set compare interrupt. */ - TAR = 0; - TACCTL0 |= CCIE; - TACTL |= MC0; -} - -void -vMBPortTimersDisable( void ) -{ - TACCTL0 &= ~CCIE; - TACTL &= ~( MC0 | MC1 ); -} - -#if defined (__GNUC__) -interrupt (TIMERA0_VECTOR) prvvMBTimerIRQHandler( void ) -#else -void -prvvMBTimerIRQHandler( void ) __interrupt[TIMERA0_VECTOR] -#endif -{ - ( void )pxMBPortCBTimerExpired( ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/system/dco-gcc.S b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/system/dco-gcc.S deleted file mode 100644 index c894f48f5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/system/dco-gcc.S +++ /dev/null @@ -1,171 +0,0 @@ -/* - * THIS PROGRAM IS PROVIDED "AS IS". TI MAKES NO WARRANTIES OR - * REPRESENTATIONS, EITHER EXPRESS, IMPLIED OR STATUTORY, - * INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR - * - * COMPLETENESS OF RESPONSES, RESULTS AND LACK OF NEGLIGENCE. - * TI DISCLAIMS ANY WARRANTY OF TITLE, QUIET ENJOYMENT, QUIET - * POSSESSION, AND NON-INFRINGEMENT OF ANY THIRD PARTY - * INTELLECTUAL PROPERTY RIGHTS WITH REGARD TO THE PROGRAM OR - * YOUR USE OF THE PROGRAM. - * - * IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, INCIDENTAL, - * CONSEQUENTIAL OR INDIRECT DAMAGES, HOWEVER CAUSED, ON ANY - * THEORY OF LIABILITY AND WHETHER OR NOT TI HAS BEEN ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGES, ARISING IN ANY WAY OUT - * OF THIS AGREEMENT, THE PROGRAM, OR YOUR USE OF THE PROGRAM. - * EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF - * REMOVAL OR REINSTALLATION, COMPUTER TIME, LABOR COSTS, LOSS - * OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, OR LOSS OF - * USE OR INTERRUPTION OF BUSINESS. IN NO EVENT WILL TI'S - * AGGREGATE LIABILITY UNDER THIS AGREEMENT OR ARISING OUT OF - * YOUR USE OF THE PROGRAM EXCEED FIVE HUNDRED DOLLARS - * (U.S.$500). - * - * Unless otherwise stated, the Program written and copyrighted - * by Texas Instruments is distributed as "freeware". You may, - * only under TI's copyright in the Program, use and modify the - * Program without any charge or restriction. You may - * distribute to third parties, provided that you transfer a - * copy of this license to the third party and the third party - * agrees to these terms by its first use of the Program. You - * must reproduce the copyright notice and any other legend of - * ownership on each copy or partial copy, of the Program. - * - * You acknowledge and agree that the Program contains - * copyrighted material, trade secrets and other TI proprietary - * information and is protected by copyright laws, - * international copyright treaties, and trade secret laws, as - * well as other intellectual property laws. To protect TI's - * rights in the Program, you agree not to decompile, reverse - * engineer, disassemble or otherwise translate any object code - * versions of the Program to a human-readable form. You agree - * that in no event will you alter, remove or destroy any - * copyright notice included in the Program. TI reserves all - * rights not specifically granted under this license. Except - * as specifically provided herein, nothing in this agreement - * shall be construed as conferring by implication, estoppel, - * or otherwise, upon you, any license or other right under any - * TI patents, copyrights or trade secrets. - * - * You may not use the Program in non-TI devices. - */ - -/* ----------------------- MSP430 registers ---------------------------------*/ -.equ DCOCTL, 0x0056 /* DCO Clock Frequency Control */ -.equ TACTL, 0x0160 /* Timer A 0 Control */ -.equ TACCTL2, 0x0166 /* Timer A 0 Capture/Compare Control 2 */ -.equ TACCR2, 0x0176 /* Timer A 0 Capture/Compare 2 */ -.equ BCSCTL1, 0x0057 /* Basic Clock Module Register */ - -.equ XT2OFF, 0x80 -.equ DIVA_3, 0x30 -.equ CCIFG, 0x0001 /* Capture/compare interrupt flag */ -.equ TACLR, 0x0004 /* Timer A counter clear */ - -.equ CM_1, (1*0x4000) /* Capture mode: 1 - pos. edge */ -.equ CCIS_1, (1*0x1000) /* Capture input select : 1 - CCIxB */ -.equ CAP, 0x0100 /* Capture mode: 1, Compare mode: 0 */ - -.equ TASSEL_2, (2*0x100) /* Timer A clock source select */ -.equ MC_2, (2*0x10) /* Timer A mode control: 2 - Continous up */ - -/* ----------------------- MSP430 registers ---------------------------------*/ - -/* - * Subroutine: Sets DCO to selected frequency based on Delta. - * R14 and R15 are used, ACLK = 32768/8 Timer_A clocked by DCOCLK - * R13 used to hold old BCSCTL1 value - * R15 is the parameter specifying the delta value, MCLK = delta * 4096 - * returns in R15: - * 0 - DCO Set Correctly - * 1 - DCO running at slowest setting - * 2 - DCO running at fastest setting - * 0xff - Timeout Occured while setting DCO - */ - .text - .align 2 - .globl cTISetDCO - -cTISetDCO: - push.w r10 - push.w r11 - push.w &TACTL - push.w &TACCTL2 - mov.w #10000, r11 /* max number of times to loop */ - mov.w r15, r12 - clr.w r15 - mov.b &BCSCTL1, r13 /* Copy BC settings to preserve */ - and.w #0xF8, r13 /* Mask out bits which will change (0-2) 1xx */ -SetupBC: - /* ACLK=LFXT1CLK/8, XT2OFF to make a known state */ - bis.b #(XT2OFF + DIVA_3),&BCSCTL1 -SetupCC2: - /* CAP, ACLK */ - mov.w #(CM_1 + CCIS_1 + CAP), &TACCTL2 - /* SMCLK, cont-mode, clear */ - mov.w #(TASSEL_2 + MC_2 + TACLR), &TACTL -firstTest: - bit.w #CCIFG, &TACCTL2 /* Test capture flag, skip first short ACLK to avoid error */ - jz firstTest - bic.w #CCIFG, &TACCTL2 /* Clear capture flag */ -TestDCO: - dec.w r11 - jz ExitTimeOutError -TestDCO2: - bit.w #CCIFG, &TACCTL2 /* Test capture flag */ - jz TestDCO2 - bic.w #CCIFG, &TACCTL2 /* Clear capture flag */ - -AdjDCO: - mov.w &TACCR2, r14 /* R14 = captured SMCLK */ - sub.w r15, r14 /* R14 = capture difference */ - mov.w &TACCR2, r15 /* R15 = captured SMCLK */ - mov.w r14, r10 /* R10 = capture difference */ - sub.w r12, r10 /* R10 = difference between desired and actual */ - jz ExitNoError /* if R12 = R10, DCO set exactly */ - cmp.w #0xFFFF, r10 /* DCO can be off by 1 for a tolerance */ - jeq ExitNoError - cmp.w r12, r14 /* Delta = SMCLK/(32768/8) */ - jlo IncDCO -DecDCO: - dec.b &DCOCTL /* Slow DCO with DCO and MOD */ - jc TestDCO /* Slower? */ - bit.b #0x7, &BCSCTL1 /* Can RSEL.x be decremented? 1xx */ - jz ExitSlowestSetting /* jmp>DCO at slowest setting */ - dec.b &BCSCTL1 /* Decrement RSEL.x */ - jmp TestDCO -IncDCO: - inc.b &DCOCTL /* Speed DCO with DCO and MOD */ - jnc TestDCO /* Faster? */ - /* Can RSEL.x be increased? 1xx */ - cmp.b #(XT2OFF + DIVA_3 + 0x7), &BCSCTL1 - jeq ExitFastestSetting /* jmp> DCO at fastest setting */ - inc.b &BCSCTL1 /* Increment RSEL.x */ - jmp TestDCO -ExitSlowestSetting: - clr.b &DCOCTL - mov.w #0x01, r15 - jmp SetDCO_Exit -ExitFastestSetting: - mov.b #0xFF, &DCOCTL /* since the DCO previously rolled over */ -ExitFastestSetting2xx: - mov.w #0x02, r15 - jmp SetDCO_Exit -ExitTimeOutError: - mov.w #0xff, r15 - jmp SetDCO_Exit -ExitNoError: - clr.w r15 -SetDCO_Exit: - clr.w TACCTL2 /* Stop CCR2 */ - bic.b #0xF8, &BCSCTL1 /* Mask out bits which will change (0-2) 1xx */ - bis.b r13, &BCSCTL1 /* Copy in old non-DCO BC settings */ - pop.w &TACTL - pop.w &TACCTL2 - pop.w r11 - pop.w r10 - ret /* Return from subroutine */ - - .end diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/system/dco-rowley.S b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/system/dco-rowley.S deleted file mode 100644 index fb80733d7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/system/dco-rowley.S +++ /dev/null @@ -1,172 +0,0 @@ -/* - * THIS PROGRAM IS PROVIDED "AS IS". TI MAKES NO WARRANTIES OR - * REPRESENTATIONS, EITHER EXPRESS, IMPLIED OR STATUTORY, - * INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR - * - * COMPLETENESS OF RESPONSES, RESULTS AND LACK OF NEGLIGENCE. - * TI DISCLAIMS ANY WARRANTY OF TITLE, QUIET ENJOYMENT, QUIET - * POSSESSION, AND NON-INFRINGEMENT OF ANY THIRD PARTY - * INTELLECTUAL PROPERTY RIGHTS WITH REGARD TO THE PROGRAM OR - * YOUR USE OF THE PROGRAM. - * - * IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, INCIDENTAL, - * CONSEQUENTIAL OR INDIRECT DAMAGES, HOWEVER CAUSED, ON ANY - * THEORY OF LIABILITY AND WHETHER OR NOT TI HAS BEEN ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGES, ARISING IN ANY WAY OUT - * OF THIS AGREEMENT, THE PROGRAM, OR YOUR USE OF THE PROGRAM. - * EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF - * REMOVAL OR REINSTALLATION, COMPUTER TIME, LABOR COSTS, LOSS - * OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, OR LOSS OF - * USE OR INTERRUPTION OF BUSINESS. IN NO EVENT WILL TI'S - * AGGREGATE LIABILITY UNDER THIS AGREEMENT OR ARISING OUT OF - * YOUR USE OF THE PROGRAM EXCEED FIVE HUNDRED DOLLARS - * (U.S.$500). - * - * Unless otherwise stated, the Program written and copyrighted - * by Texas Instruments is distributed as "freeware". You may, - * only under TI's copyright in the Program, use and modify the - * Program without any charge or restriction. You may - * distribute to third parties, provided that you transfer a - * copy of this license to the third party and the third party - * agrees to these terms by its first use of the Program. You - * must reproduce the copyright notice and any other legend of - * ownership on each copy or partial copy, of the Program. - * - * You acknowledge and agree that the Program contains - * copyrighted material, trade secrets and other TI proprietary - * information and is protected by copyright laws, - * international copyright treaties, and trade secret laws, as - * well as other intellectual property laws. To protect TI's - * rights in the Program, you agree not to decompile, reverse - * engineer, disassemble or otherwise translate any object code - * versions of the Program to a human-readable form. You agree - * that in no event will you alter, remove or destroy any - * copyright notice included in the Program. TI reserves all - * rights not specifically granted under this license. Except - * as specifically provided herein, nothing in this agreement - * shall be construed as conferring by implication, estoppel, - * or otherwise, upon you, any license or other right under any - * TI patents, copyrights or trade secrets. - * - * You may not use the Program in non-TI devices. - */ - -/* ----------------------- MSP430 registers ---------------------------------*/ -DCOCTL .equ 0x0056 /* DCO Clock Frequency Control */ -TACTL .equ 0x0160 /* Timer A 0 Control */ -TACCTL2 .equ 0x0166 /* Timer A 0 Capture/Compare Control 2 */ -TACCR2 .equ 0x0176 /* Timer A 0 Capture/Compare 2 */ -BCSCTL1 .equ 0x0057 /* Basic Clock Module Register */ - -XT2OFF .equ 0x80 -DIVA_3 .equ 0x30 -CCIFG .equ 0x0001 /* Capture/compare interrupt flag */ -TACLR .equ 0x0004 /* Timer A counter clear */ - -CM_1 .equ (1*0x4000) /* Capture mode: 1 - pos. edge */ -CCIS_1 .equ (1*0x1000) /* Capture input select : 1 - CCIxB */ -CAP .equ 0x0100 /* Capture mode: 1, Compare mode: 0 */ - -TASSEL_2 .equ (2*0x100) /* Timer A clock source select */ -MC_2 .equ (2*0x10) /* Timer A mode control: 2 - Continous up */ - -/* ----------------------- MSP430 registers ---------------------------------*/ - -/* - * Subroutine: Sets DCO to selected frequency based on Delta. - * R14 and R15 are used, ACLK = 32768/8 Timer_A clocked by DCOCLK - * R13 used to hold old BCSCTL1 value - * R15 is the parameter specifying the delta value, MCLK = delta * 4096 - * returns in R15: - * 0 - DCO Set Correctly - * 1 - DCO running at slowest setting - * 2 - DCO running at fastest setting - * 0xff - Timeout Occured while setting DCO - */ - - CODE - ALIGN 2 - EXPORT _cTISetDCO - -_cTISetDCO: - push.w r10 - push.w r11 - push.w &TACTL - push.w &TACCTL2 - mov.w #10000, r11 /* max number of times to loop */ - mov.w r15, r12 - clr.w r15 - mov.b &BCSCTL1, r13 /* Copy BC settings to preserve */ - and.w #0xF8, r13 /* Mask out bits which will change (0-2) 1xx */ -SetupBC: - /* ACLK=LFXT1CLK/8, XT2OFF to make a known state */ - bis.b #(XT2OFF + DIVA_3),&BCSCTL1 -SetupCC2: - /* CAP, ACLK */ - mov.w #(CM_1 + CCIS_1 + CAP), &TACCTL2 - /* SMCLK, cont-mode, clear */ - mov.w #(TASSEL_2 + MC_2 + TACLR), &TACTL -firstTest: - bit.w #CCIFG, &TACCTL2 /* Test capture flag, skip first short ACLK to avoid error */ - jz firstTest - bic.w #CCIFG, &TACCTL2 /* Clear capture flag */ -TestDCO: - dec.w r11 - jz ExitTimeOutError -TestDCO2: - bit.w #CCIFG, &TACCTL2 /* Test capture flag */ - jz TestDCO2 - bic.w #CCIFG, &TACCTL2 /* Clear capture flag */ - -AdjDCO: - mov.w &TACCR2, r14 /* R14 = captured SMCLK */ - sub.w r15, r14 /* R14 = capture difference */ - mov.w &TACCR2, r15 /* R15 = captured SMCLK */ - mov.w r14, r10 /* R10 = capture difference */ - sub.w r12, r10 /* R10 = difference between desired and actual */ - jz ExitNoError /* if R12 = R10, DCO set exactly */ - cmp.w #0xFFFF, r10 /* DCO can be off by 1 for a tolerance */ - jeq ExitNoError - cmp.w r12, r14 /* Delta = SMCLK/(32768/8) */ - jlo IncDCO -DecDCO: - dec.b &DCOCTL /* Slow DCO with DCO and MOD */ - jc TestDCO /* Slower? */ - bit.b #0x7, &BCSCTL1 /* Can RSEL.x be decremented? 1xx */ - jz ExitSlowestSetting /* jmp>DCO at slowest setting */ - dec.b &BCSCTL1 /* Decrement RSEL.x */ - jmp TestDCO -IncDCO: - inc.b &DCOCTL /* Speed DCO with DCO and MOD */ - jnc TestDCO /* Faster? */ - /* Can RSEL.x be increased? 1xx */ - cmp.b #(XT2OFF + DIVA_3 + 0x7), &BCSCTL1 - jeq ExitFastestSetting /* jmp> DCO at fastest setting */ - inc.b &BCSCTL1 /* Increment RSEL.x */ - jmp TestDCO -ExitSlowestSetting: - clr.b &DCOCTL - mov.w #0x01, r15 - jmp SetDCO_Exit -ExitFastestSetting: - mov.b #0xFF, &DCOCTL /* since the DCO previously rolled over */ -ExitFastestSetting2xx: - mov.w #0x02, r15 - jmp SetDCO_Exit -ExitTimeOutError: - mov.w #0xff, r15 - jmp SetDCO_Exit -ExitNoError: - clr.w r15 -SetDCO_Exit: - clr.w TACCTL2 /* Stop CCR2 */ - bic.b #0xF8, &BCSCTL1 /* Mask out bits which will change (0-2) 1xx */ - bis.b r13, &BCSCTL1 /* Copy in old non-DCO BC settings */ - pop.w &TACTL - pop.w &TACCTL2 - pop.w r11 - pop.w r10 - ret /* Return from subroutine */ - - .end diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/system/dco.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/system/dco.h deleted file mode 100644 index a1f30bbc1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/MSP430/system/dco.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - * - */ -#ifndef DCO_H -#define DCO_H - -/* ----------------------- Defines ------------------------------------------*/ -#define TI_DCO_NO_ERROR ( 0 ) -#define TI_DCO_SET_TO_SLOWEST ( 1 ) -#define TI_DCO_SET_TO_FASTEST ( 2 ) -#define TI_DCO_TIMEOUT_ERROR ( 0xFF ) - -#define TI_DCO_1MHZ ( 244 ) /* Target DCO = DELTA*(4096) ~1MHz */ -#define TI_DCO_2MHZ ( 488 ) /* Target DCO = DELTA*(4096) ~2MHz */ -#define TI_DCO_3MHZ ( 732 ) /* Target DCO = DELTA*(4096) ~3MHz */ -#define TI_DCO_4MHZ ( 977 ) /* Target DCO = DELTA*(4096) ~4MHz */ -#define TI_DCO_5MHZ ( 1221 ) /* Target DCO = DELTA*(4096) ~5MHz */ -#define TI_DCO_6MHZ ( 1465 ) /* Target DCO = DELTA*(4096) ~6MHz */ -#define TI_DCO_7MHZ ( 1709 ) /* Target DCO = DELTA*(4096) ~7MHz */ -#define TI_DCO_8MHZ ( 1953 ) /* Target DCO = DELTA*(4096) ~8MHz */ -#define TI_DCO_9MHZ ( 2197 ) /* Target DCO = DELTA*(4096) ~9MHz */ -#define TI_DCO_10MHZ ( 2441 ) /* Target DCO = DELTA*(4096) ~10MHz */ -#define TI_DCO_11MHZ ( 2686 ) /* Target DCO = DELTA*(4096) ~11MHz */ -#define TI_DCO_12MHZ ( 2930 ) /* Target DCO = DELTA*(4096) ~12MHz */ -#define TI_DCO_13MHZ ( 3174 ) /* Target DCO = DELTA*(4096) ~13MHz */ -#define TI_DCO_14MHZ ( 3418 ) /* Target DCO = DELTA*(4096) ~14MHz */ -#define TI_DCO_15MHZ ( 3662 ) /* Target DCO = DELTA*(4096) ~15MHz */ -#define TI_DCO_16MHZ ( 3906 ) /* Target DCO = DELTA*(4096) ~16MHz */ - -/* ----------------------- Function prototypes ------------------------------*/ -extern char cTISetDCO( int delta ); - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/FreeRTOSConfig.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/FreeRTOSConfig.h deleted file mode 100644 index 95a104295..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/FreeRTOSConfig.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - FreeRTOS V3.2.4 - Copyright (C) 2003-2005 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 - -/* 160000000Mhz is frequency of PCLK2 not CPU frequency because this - * value is used for calculating the timer reload value */ -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 16000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - - -/* Set the following definitions to 1 to include the API function, or zero - * to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - - -#endif /* FREERTOS_CONFIG_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/crt0.s b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/crt0.s deleted file mode 100644 index 7ab4eec43..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/crt0.s +++ /dev/null @@ -1,177 +0,0 @@ -/***************************************************************************** - * Copyright (c) 2001, 2002 Rowley Associates Limited. * - * * - * This file may be distributed under the terms of the License Agreement * - * provided with this software. * - * * - * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * - * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - *****************************************************************************/ - .section .init, "ax" - .code 32 - .align 0 - - .weak _start - .global __start - .global __gccmain - .extern main - .extern exit - -/***************************************************************************** - * Function : _start * - * Description : Main entry point and startup code for C system. * - *****************************************************************************/ -_start: -__start: - mrs r0, cpsr - bic r0, r0, #0x1F - - /* Setup stacks */ - orr r1, r0, #0x1B /* Undefined mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_und_end__ - - orr r1, r0, #0x17 /* Abort mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_abt_end__ - - orr r1, r0, #0x12 /* IRQ mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_irq_end__ - - orr r1, r0, #0x11 /* FIQ mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_fiq_end__ - - orr r1, r0, #0x13 /* Supervisor mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_svc_end__ -#ifdef SUPERVISOR_START - /* Start application in supervisor mode */ - ldr r1, =__stack_end__ /* Setup user/system mode stack */ - mov r2, sp - stmfd r2!, {r1} - ldmfd r2, {sp}^ -#else - /* Start application in system mode */ - orr r1, r0, #0x1F /* System mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_end__ -#endif - - /* Copy from initialised data section to data section (if necessary). */ - ldr r0, =__data_load_start__ - ldr r1, =__data_start__ - cmp r0, r1 - beq copy_data_end - - ldr r2, =__data_end__ - subs r2, r2, r1 - beq copy_data_end - -copy_data_loop: - ldrb r3, [r0], #+1 - strb r3, [r1], #+1 - subs r2, r2, #1 - bne copy_data_loop -copy_data_end: - - /* Copy from initialised text section to text section (if necessary). */ - ldr r0, =__text_load_start__ - ldr r1, =__text_start__ - cmp r0, r1 - beq copy_text_end - - ldr r2, =__text_end__ - subs r2, r2, r1 - beq copy_text_end - -copy_text_loop: - ldrb r3, [r0], #+1 - strb r3, [r1], #+1 - subs r2, r2, #1 - bne copy_text_loop -copy_text_end: - - /* Copy from initialised fast_text section to fast_text section (if necessary). */ - ldr r0, =__fast_load_start__ - ldr r1, =__fast_start__ - cmp r0, r1 - beq copy_fast_end - - ldr r2, =__fast_end__ - subs r2, r2, r1 - beq copy_fast_end - -copy_fast_loop: - ldrb r3, [r0], #+1 - strb r3, [r1], #+1 - subs r2, r2, #1 - bne copy_fast_loop -copy_fast_end: - - /* Zero the bss. */ - ldr r0, =__bss_start__ - ldr r1, =__bss_end__ - mov r2, #0 -zero_bss_loop: - cmp r0, r1 - beq zero_bss_end - strb r2, [r0], #+1 - b zero_bss_loop -zero_bss_end: - - /* Initialise the heap */ - ldr r0, = __heap_start__ - ldr r1, = __heap_end__ - sub r1, r1, r0 /* r1 = r1-r0 */ - mov r2, #0 - str r2, [r0], #+4 /* *r0++ = 0 */ - str r1, [r0] /* *r0 = __heap_end__ - __heap_start__ */ - - /* Call constructors */ - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ -ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #+4 - stmfd sp!, {r0-r1} - mov lr, pc - mov pc, r2 - ldmfd sp!, {r0-r1} - b ctor_loop -ctor_end: - - /* Setup initial call frame */ - mov lr, #4 - mov r12, sp - stmfd sp!, {r11-r12, lr-pc} - sub r11, r12, #0x00000004 - -start: - /* Jump to main entry point */ - mov r0, #0 - mov r1, #0 - ldr r2, =main - bx r2 - - /* Call destructors */ - ldr r0, =__dtors_start__ - ldr r1, =__dtors_end__ - -dtor_loop: - cmp r0, r1 - beq dtor_end - ldr r2, [r0], #+4 - stmfd sp!, {r0-r1} - mov lr, pc - mov pc, r2 - ldmfd sp!, {r0-r1} - b dtor_loop -dtor_end: - - /* Return from main, loop forever. */ -exit_loop: - b exit_loop - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/demo.hzp b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/demo.hzp deleted file mode 100644 index d0ba296b9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/demo.hzp +++ /dev/null @@ -1,110 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/excoils.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/excoils.c deleted file mode 100644 index 26c67e164..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/excoils.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * FreeModbus Libary: STR71x Demo Application - * Copyright (C) 2006 Christian Walter - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "assert.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* ----------------------- STR71X includes ----------------------------------*/ -#include "eic.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbutils.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define REG_COILS_START 1000 -#define REG_COILS_SIZE 16 - -/* ----------------------- Static variables ---------------------------------*/ -static unsigned char ucRegCoilsBuf[REG_COILS_SIZE / 8]; - -/* ----------------------- Static functions ---------------------------------*/ -static void vModbusTask( void *pvParameters ); - -/* ----------------------- Start implementation -----------------------------*/ -int -main( void ) -{ - EIC_Init( ); - EIC_IRQConfig( ENABLE ); - - ( void )xTaskCreate( vModbusTask, NULL, configMINIMAL_STACK_SIZE, NULL, - tskIDLE_PRIORITY, NULL ); - - vTaskStartScheduler( ); - return 0; -} - -static void -vModbusTask( void *pvParameters ) -{ - /* Select either ASCII or RTU Mode. */ - ( void )eMBInit( MB_RTU, 0x0A, 0, 38400, MB_PAR_EVEN ); - - /* Enable the Modbus Protocol Stack. */ - ( void )eMBEnable( ); - - /* Enter main loop. */ - for( ;; ) - { - /* Call the main polling loop of the Modbus protocol stack. */ - ( void )eMBPoll( ); - } -} - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, - eMBRegisterMode eMode ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iNCoils = ( int )usNCoils; - unsigned short usBitOffset; - - /* Check if we have registers mapped at this block. */ - if( ( usAddress >= REG_COILS_START ) && - ( usAddress + usNCoils <= REG_COILS_START + REG_COILS_SIZE ) ) - { - usBitOffset = ( unsigned short )( usAddress - REG_COILS_START ); - switch ( eMode ) - { - /* Read current values and pass to protocol stack. */ - case MB_REG_READ: - while( iNCoils > 0 ) - { - *pucRegBuffer++ = - xMBUtilGetBits( ucRegCoilsBuf, usBitOffset, - ( unsigned char )( iNCoils > - 8 ? 8 : - iNCoils ) ); - iNCoils -= 8; - usBitOffset += 8; - } - break; - - /* Update current register values. */ - case MB_REG_WRITE: - while( iNCoils > 0 ) - { - xMBUtilSetBits( ucRegCoilsBuf, usBitOffset, - ( unsigned char )( iNCoils > 8 ? 8 : iNCoils ), - *pucRegBuffer++ ); - iNCoils -= 8; - usBitOffset += 8; - } - break; - } - - } - else - { - eStatus = MB_ENOREG; - } - return eStatus; -} - - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, - eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} - -void -__assert( const char *pcFile, const char *pcLine, int iLineNumber ) -{ - portENTER_CRITICAL( ); - for( ;; ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/exdisc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/exdisc.c deleted file mode 100644 index 11f844584..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/exdisc.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * FreeModbus Libary: STR71x Demo Application - * Copyright (C) 2006 Christian Walter - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "assert.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* ----------------------- STR71X includes ----------------------------------*/ -#include "eic.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbutils.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define REG_DISC_START 1000 -#define REG_DISC_SIZE 16 - -/* ----------------------- Static variables ---------------------------------*/ -static unsigned char ucRegDiscBuf[REG_DISC_SIZE / 8] = { 0, 0 }; - -/* ----------------------- Static functions ---------------------------------*/ -static void vModbusTask( void *pvParameters ); - -/* ----------------------- Start implementation -----------------------------*/ -int -main( void ) -{ - EIC_Init( ); - EIC_IRQConfig( ENABLE ); - - ( void )xTaskCreate( vModbusTask, NULL, configMINIMAL_STACK_SIZE, NULL, - tskIDLE_PRIORITY, NULL ); - - vTaskStartScheduler( ); - return 0; -} - -static void -vModbusTask( void *pvParameters ) -{ - /* Select either ASCII or RTU Mode. */ - ( void )eMBInit( MB_RTU, 0x0A, 0, 38400, MB_PAR_EVEN ); - - /* Initialise the discrete input registers. */ - xMBUtilSetBits( ucRegDiscBuf, 2, 2, 3 ); /* Set bit 2:3 to 11b. */ - xMBUtilSetBits( ucRegDiscBuf, 8, 1, 1 ); /* Set bit 8 to 1b. */ - - /* Enable the Modbus Protocol Stack. */ - ( void )eMBEnable( ); - for( ;; ) - { - /* Call the main polling loop of the Modbus protocol stack. */ - ( void )eMBPoll( ); - } -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - eMBErrorCode eStatus = MB_ENOERR; - short iNDiscrete = ( short )usNDiscrete; - unsigned short usBitOffset; - - /* Check if we have registers mapped at this block. */ - if( ( usAddress >= REG_DISC_START ) && - ( usAddress + usNDiscrete <= REG_DISC_START + REG_DISC_SIZE ) ) - { - usBitOffset = ( unsigned short )( usAddress - REG_DISC_START ); - while( iNDiscrete > 0 ) - { - *pucRegBuffer++ = - xMBUtilGetBits( ucRegDiscBuf, usBitOffset, - ( unsigned char )( iNDiscrete > - 8 ? 8 : iNDiscrete ) ); - iNDiscrete -= 8; - usBitOffset += 8; - } - } - else - { - eStatus = MB_ENOREG; - } - return eStatus; -} - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, - eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, - eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -void -__assert( const char *pcFile, const char *pcLine, int iLineNumber ) -{ - portENTER_CRITICAL( ); - while( 1 ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/exholding.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/exholding.c deleted file mode 100644 index 82c63adb9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/exholding.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * FreeModbus Libary: STR71x Demo Application - * Copyright (C) 2006 Christian Walter - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "assert.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* ----------------------- STR71X includes ----------------------------------*/ -#include "eic.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define REG_HOLDING_START 1000 -#define REG_HOLDING_NREGS 130 - -/* ----------------------- Static variables ---------------------------------*/ -static unsigned short usRegHoldingStart = REG_HOLDING_START; -static unsigned short usRegHoldingBuf[REG_HOLDING_NREGS]; - -/* ----------------------- Static functions ---------------------------------*/ -static void vModbusTask( void *pvParameters ); - -/* ----------------------- Start implementation -----------------------------*/ -int -main( void ) -{ - EIC_Init( ); - EIC_IRQConfig( ENABLE ); - - ( void )xTaskCreate( vModbusTask, NULL, configMINIMAL_STACK_SIZE, NULL, - tskIDLE_PRIORITY, NULL ); - - vTaskStartScheduler( ); - return 0; -} - -static void -vModbusTask( void *pvParameters ) -{ - int i; - - /* Select either ASCII or RTU Mode. */ - ( void )eMBInit( MB_RTU, 0x0A, 0, 38400, MB_PAR_EVEN ); - - /* Initialize the holding register values before starting the - * Modbus stack. */ - for( i = 0; i < REG_HOLDING_NREGS; i++ ) - { - usRegHoldingBuf[i] = ( unsigned short )i; - } - - /* Enable the Modbus Protocol Stack. */ - ( void )eMBEnable( ); - for( ;; ) - { - /* Call the main polling loop of the Modbus protocol stack. */ - ( void )eMBPoll( ); - } -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, - eMBRegisterMode eMode ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_HOLDING_START ) && - ( usAddress + usNRegs <= REG_HOLDING_START + REG_HOLDING_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegHoldingStart ); - switch ( eMode ) - { - /* Pass current register values to the protocol stack. */ - case MB_REG_READ: - while( usNRegs > 0 ) - { - *pucRegBuffer++ = - ( unsigned char )( usRegHoldingBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = - ( unsigned char )( usRegHoldingBuf[iRegIndex] & - 0xFF ); - iRegIndex++; - usNRegs--; - } - break; - - /* Update current register values with new values from the - * protocol stack. */ - case MB_REG_WRITE: - while( usNRegs > 0 ) - { - usRegHoldingBuf[iRegIndex] = *pucRegBuffer++ << 8; - usRegHoldingBuf[iRegIndex] |= *pucRegBuffer++; - iRegIndex++; - usNRegs--; - } - } - } - else - { - eStatus = MB_ENOREG; - } - return eStatus; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, - eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} - -void -__assert( const char *pcFile, const char *pcLine, int iLineNumber ) -{ - portENTER_CRITICAL( ); - for( ;; ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/FreeRTOS.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/FreeRTOS.h deleted file mode 100644 index 8079a680a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/FreeRTOS.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - FreeRTOS V3.2.4 - Copyright (C) 2003-2005 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef INC_FREERTOS_H -#define INC_FREERTOS_H - - -/* - * Include the generic headers required for the FreeRTOS port being used. - */ -#include - -/* Basic FreeRTOS definitions. */ -#include "projdefs.h" - -/* Application specific configuration options. */ -#include "FreeRTOSConfig.h" - -/* Definitions specific to the port being used. */ -#include "portable.h" - - - - - - - -/* - * Check all the required application specific macros have been defined. - * These macros are application specific and (as downloaded) are defined - * within FreeRTOSConfig.h. - */ - -#ifndef configUSE_PREEMPTION - #error Missing definition: configUSE_PREEMPTION should be defined as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_IDLE_HOOK - #error Missing definition: configUSE_IDLE_HOOK should be defined as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskPrioritySet - #error Missing definition: INCLUDE_vTaskPrioritySet should be defined as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_uxTaskPriorityGet - #error Missing definition: INCLUDE_uxTaskPriorityGet should be defined as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelete - #error Missing definition: INCLUDE_vTaskDelete should be defined as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskCleanUpResources - #error Missing definition: INCLUDE_vTaskCleanUpResources should be defined as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskSuspend - #error Missing definition: INCLUDE_vTaskSuspend should be defined as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelayUntil - #error Missing definition: INCLUDE_vTaskDelayUntil should be defined as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelay - #error Missing definition: INCLUDE_vTaskDelay should be defined as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_16_BIT_TICKS - #error Missing definition: configUSE_16_BIT_TICKS should be defined as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - - - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/list.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/list.h deleted file mode 100644 index b8d185652..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/list.h +++ /dev/null @@ -1,265 +0,0 @@ -/* - FreeRTOS V3.2.4 - Copyright (C) 2003-2005 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This is the list implementation used by the scheduler. While it is tailored - * heavily for the schedulers needs, it is also available for use by - * application code. - * - * xLists can only store pointers to xListItems. Each xListItem contains a - * numeric value (xItemValue). Most of the time the lists are sorted in - * descending item value order. - * - * Lists are created already containing one list item. The value of this - * item is the maximum possible that can be stored, it is therefore always at - * the end of the list and acts as a marker. The list member pxHead always - * points to this marker - even though it is at the tail of the list. This - * is because the tail contains a wrap back pointer to the true head of - * the list. - * - * In addition to it's value, each list item contains a pointer to the next - * item in the list (pxNext), a pointer to the list it is in (pxContainer) - * and a pointer to back to the object that contains it. These later two - * pointers are included for efficiency of list manipulation. There is - * effectively a two way link between the object containing the list item and - * the list item itself. - * - * - * \page ListIntroduction List Implementation - * \ingroup FreeRTOSIntro - */ - - -#ifndef LIST_H -#define LIST_H - -/* - * Definition of the only type of object that a list can contain. - */ -struct xLIST_ITEM -{ - portTickType xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ - volatile struct xLIST_ITEM * pxNext; /*< Pointer to the next xListItem in the list. */ - volatile struct xLIST_ITEM * pxPrevious;/*< Pointer to the previous xListItem in the list. */ - void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ - void * pvContainer; /*< Pointer to the list in which this list item is placed (if any). */ -}; -typedef struct xLIST_ITEM xListItem; /* For some reason lint wants this as two separate definitions. */ - -/* - * Definition of the type of queue used by the scheduler. - */ -typedef struct xLIST -{ - unsigned portBASE_TYPE uxNumberOfItems; - volatile xListItem * pxHead; /*< Pointer to the xListEnd item. xListEnd contains a wrap back pointer to true list head. */ - volatile xListItem * pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to pvListGetOwnerOfNextEntry (). */ - volatile xListItem xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ -} xList; - -/* - * Access macro to set the owner of a list item. The owner of a list item - * is the object (usually a TCB) that contains the list item. - * - * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) { ( pxListItem )->pvOwner = ( void * ) pxOwner; } - -/* - * Access macro to set the value of the list item. In most cases the value is - * used to sort the list in descending order. - * - * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) { ( pxListItem )->xItemValue = xValue; } - -/* - * Access macro the retrieve the value of the list item. The value can - * represent anything - for example a the priority of a task, or the time at - * which a task should be unblocked. - * - * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) - -/* - * Access macro to determine if a list contains any items. The macro will - * only have the value true if the list is empty. - * - * \page listLIST_IS_EMPTY listLIST_IS_EMPTY - * \ingroup LinkedList - */ -#define listLIST_IS_EMPTY( pxList ) ( ( pxList )->uxNumberOfItems == ( unsigned portBASE_TYPE ) 0 ) - -/* - * Access macro to return the number of items in the list. - */ -#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) - -/* - * Access function to obtain the owner of the next entry in a list. - * - * The list member pxIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list - * and returns that entries pxOwner parameter. Using multiple calls to this - * function it is therefore possible to move through every item contained in - * a list. - * - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the next item owner is to be returned. - * - * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ -{ \ - /* Increment the index to the next item and return the item, ensuring */ \ - /* we don't return the marker used at the end of the list. */ \ - \ - ( pxList )->pxIndex = ( pxList )->pxIndex->pxNext; \ - if( ( pxList )->pxIndex == ( pxList )->pxHead ) \ - { \ - ( pxList )->pxIndex = ( pxList )->pxIndex->pxNext; \ - } \ - pxTCB = ( volatile tskTCB * ) ( pxList )->pxIndex->pvOwner; \ -} - -/* - * Access function to obtain the owner of the first entry in a list. Lists - * are normally sorted in ascending item value order. - * - * This function returns the pxOwner member of the first item in the list. - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the owner of the head item is to be - * returned. - * - * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( pxList->uxNumberOfItems != ( unsigned portBASE_TYPE ) 0 ) ? ( pxList->pxHead->pxNext->pvOwner ) : ( NULL ) ) - -/* - * Check to see if a list item is within a list. The list item maintains a - * "container" pointer that points to the list it is in. All this macro does - * is check to see if the container and the list match. - * - * @param pxList The list we want to know if the list item is within. - * @param pxListItem The list item we want to know if is in the list. - * @return pdTRUE is the list item is in the list, otherwise pdFALSE. - * pointer against - */ -#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( pxListItem )->pvContainer == ( void * ) pxList ) - -/* - * Must be called before a list is used! This initialises all the members - * of the list structure and inserts the xListEnd item into the list as a - * marker to the back of the list. - * - * @param pxList Pointer to the list being initialised. - * - * \page vListInitialise vListInitialise - * \ingroup LinkedList - */ -void vListInitialise( xList *pxList ); - -/* - * Must be called before a list item is used. This sets the list container to - * null so the item does not think that it is already contained in a list. - * - * @param pxItem Pointer to the list item being initialised. - * - * \page vListInitialiseItem vListInitialiseItem - * \ingroup LinkedList - */ -void vListInitialiseItem( xListItem *pxItem ); - -/* - * Insert a list item into a list. The item will be inserted into the list in - * a position determined by its item value (descending item value order). - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The item to that is to be placed in the list. - * - * \page vListInsert vListInsert - * \ingroup LinkedList - */ -void vListInsert( xList *pxList, xListItem *pxNewListItem ); - -/* - * Insert a list item into a list. The item will be inserted in a position - * such that it will be the last item within the list returned by multiple - * calls to listGET_OWNER_OF_NEXT_ENTRY. - * - * The list member pvIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list. - * Placing an item in a list using vListInsertEnd effectively places the item - * in the list position pointed to by pvIndex. This means that every other - * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before - * the pvIndex parameter again points to the item being inserted. - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The list item to be inserted into the list. - * - * \page vListInsertEnd vListInsertEnd - * \ingroup LinkedList - */ -void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ); - -/* - * Remove an item from a list. The list item has a pointer to the list that - * it is in, so only the list item need be passed into the function. - * - * @param vListRemove The item to be removed. The item will remove itself from - * the list pointed to by it's pxContainer parameter. - * - * \page vListRemove vListRemove - * \ingroup LinkedList - */ -void vListRemove( xListItem *pxItemToRemove ); - - - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/portable.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/portable.h deleted file mode 100644 index ee63220c7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/portable.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - FreeRTOS V3.2.4 - Copyright (C) 2003-2005 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http:www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http:www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Portable layer API. Each function must be defined for each port. - *----------------------------------------------------------*/ - -#ifndef PORTABLE_H -#define PORTABLE_H - -/* Include the macro file relevant to the port being used. */ - -#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT - #include "..\..\source\portable\owatcom\16bitdos\pc\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT - #include "..\..\source\portable\owatcom\16bitdos\flsh186\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef GCC_MEGA_AVR - #include "../portable/GCC/ATMega323/portmacro.h" -#endif - -#ifdef IAR_MEGA_AVR - #include "../portable/IAR/ATMega323/portmacro.h" -#endif - -#ifdef MPLAB_PIC18F_PORT - #include "..\..\source\portable\MPLAB\PIC18F\portmacro.h" -#endif - -#ifdef _FEDPICC - #include "libFreeRTOS/Include/portmacro.h" -#endif - -#ifdef SDCC_CYGNAL - #include "../../Source/portable/SDCC/Cygnal/portmacro.h" -#endif - -#ifdef GCC_ARM7 - #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" -#endif - -#ifdef GCC_MSP430 - #include "../../Source/portable/GCC/MSP430F449/portmacro.h" -#endif - -#ifdef ROWLEY_MSP430 - #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" -#endif - -#ifdef KEIL_ARM7 - #include "..\..\Source\portable\Keil\ARM7\portmacro.h" -#endif - -#ifdef SAM7_GCC - #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" -#endif - -#ifdef SAM7_IAR - #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" -#endif - -#ifdef LPC2000_IAR - #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" -#endif - -#ifdef STR71X_IAR - #include "..\..\Source\portable\IAR\STR71x\portmacro.h" -#endif - -#ifdef STR71X_GCC - #include "portmacro.h" -#endif - -#ifdef GCC_H8S - #include "../../Source/portable/GCC/H8S2329/portmacro.h" -#endif - -#ifdef GCC_AT91FR40008 - #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" -#endif - -#ifdef HCS12_CODE_WARRIOR - #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" -#endif - -#ifdef MICROBLAZE_GCC - #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" -#endif - -#ifdef BCC_INDUSTRIAL_PC_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef BCC_FLASH_LITE_186_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif -/* - * Setup the stack of a new task so it is ready to be placed under the - * scheduler control. The registers have to be placed on the stack in - * the order that the port expects to find them. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ); - -/* - * Map to the memory management routines required for the port. - */ -void *pvPortMalloc( size_t xSize ); -void vPortFree( void *pv ); -void vPortInitialiseBlocks( void ); - -/* - * Setup the hardware ready for the scheduler to take control. This generally - * sets up a tick interrupt and sets timers for the correct tick frequency. - */ -portBASE_TYPE xPortStartScheduler( void ); - -/* - * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so - * the hardware is left in its original condition after the scheduler stops - * executing. - */ -void vPortEndScheduler( void ); - - -#endif /* PORTABLE_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/projdefs.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/projdefs.h deleted file mode 100644 index 07e54c3ef..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/projdefs.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - FreeRTOS V3.2.4 - Copyright (C) 2003-2005 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PROJDEFS_H -#define PROJDEFS_H - -typedef void (*pdTASK_CODE)( void * ); - -#define pdTRUE ( 1 ) -#define pdFALSE ( 0 ) - -#define pdPASS ( 1 ) -#define pdFAIL ( 0 ) - -/* Error definitions. */ -#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 ) -#define errNO_TASK_TO_RUN ( -2 ) -#define errQUEUE_FULL ( -3 ) - - -#endif - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/queue.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/queue.h deleted file mode 100644 index 93e0bdfb4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/queue.h +++ /dev/null @@ -1,457 +0,0 @@ -/* - FreeRTOS V3.2.4 - Copyright (C) 2003-2005 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef QUEUE_H -#define QUEUE_H - -typedef void * xQueueHandle; - -/** - * queue. h - *
- xQueueHandle xQueueCreate( 
-                              unsigned portBASE_TYPE uxQueueLength, 
-                              unsigned portBASE_TYPE uxItemSize 
-                          );
- * 
- * - * Creates a new queue instance. This allocates the storage required by the - * new queue and returns a handle for the queue. - * - * @param uxQueueLength The maximum number of items that the queue can contain. - * - * @param uxItemSize The number of bytes each item in the queue will require. - * Items are queued by copy, not by reference, so this is the number of bytes - * that will be copied for each posted item. Each item on the queue must be - * the same size. - * - * @return If the queue is successfully create then a handle to the newly - * created queue is returned. If the queue cannot be created then 0 is - * returned. - * - * Example usage: -
- struct AMessage
- {
-    portCHAR ucMessageID;
-    portCHAR ucData[ 20 ];
- };
-
- void vATask( void *pvParameters )
- {
- xQueueHandle xQueue1, xQueue2;
-
-    // Create a queue capable of containing 10 unsigned long values.
-    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );
-    if( xQueue1 == 0 )
-    {
-        // Queue was not created and must not be used.
-    }
-
-    // Create a queue capable of containing 10 pointers to AMessage structures.
-    // These should be passed by pointer as they contain a lot of data.
-    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-    if( xQueue2 == 0 )
-    {
-        // Queue was not created and must not be used.
-    }
-
-    // ... Rest of task code.
- }
- 
- * \defgroup xQueueCreate xQueueCreate - * \ingroup QueueManagement - */ -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); - -/** - * queue. h - *
- portBASE_TYPE xQueueSend( 
-                             xQueueHandle xQueue, 
-                             const void * pvItemToQueue, 
-                             portTickType xTicksToWait 
-                         );
- * 
- * - * Post an item on a queue. The item is queued by copy, not by reference. - * This function must not be called from an interrupt service routine. - * See xQueueSendFromISR () for an alternative which may be used in an ISR. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for space to become available on the queue, should it already - * be full. The call will return immediately if this is set to 0. The - * time is defined in tick periods so the constant portTICK_RATE_MS - * should be used to convert to real time if this is required. - * - * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. - * - * Example usage: -
- struct AMessage
- {
-    portCHAR ucMessageID;
-    portCHAR ucData[ 20 ];
- } xMessage;
-
- unsigned portLONG ulVar = 10UL;
-
- void vATask( void *pvParameters )
- {
- xQueueHandle xQueue1, xQueue2;
- struct AMessage *pxMessage;
-
-    // Create a queue capable of containing 10 unsigned long values.
-    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );
-
-    // Create a queue capable of containing 10 pointers to AMessage structures.
-    // These should be passed by pointer as they contain a lot of data.
-    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-
-    // ...
-
-    if( xQueue1 != 0 )
-    {
-        // Send an unsigned long.  Wait for 10 ticks for space to become 
-        // available if necessary.
-        if( xQueueSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )
-        {
-            // Failed to post the message, even after 10 ticks.
-        }
-    }
-
-    if( xQueue2 != 0 )
-    {
-        // Send a pointer to a struct AMessage object.  Don't block if the
-        // queue is already full.
-        pxMessage = & xMessage;
-        xQueueSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );
-    }
-
-	// ... Rest of task code.
- }
- 
- * \defgroup xQueueSend xQueueSend - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); - -/** - * queue. h - *
- portBASE_TYPE xQueueReceive( 
-                                xQueueHandle xQueue, 
-                                void *pcBuffer, 
-                                portTickType xTicksToWait 
-                            );
- * - * Receive an item from a queue. The item is received by copy so a buffer of - * adequate size must be provided. The number of bytes copied into the buffer - * was defined when the queue was created. - * - * This function must not be used in an interrupt service routine. See - * xQueueReceiveFromISR for an alternative that can. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pcBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for an item to receive should the queue be empty at the time - * of the call. The time is defined in tick periods so the constant - * portTICK_RATE_MS should be used to convert to real time if this is required. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: -
- struct AMessage
- {
-    portCHAR ucMessageID;
-    portCHAR ucData[ 20 ];
- } xMessage;
-
- xQueueHandle xQueue;
- 
- // Task to create a queue and post a value.
- void vATask( void *pvParameters )
- {
- struct AMessage *pxMessage;
-
-    // Create a queue capable of containing 10 pointers to AMessage structures.
-    // These should be passed by pointer as they contain a lot of data.
-    xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
-    if( xQueue == 0 )
-    {
-        // Failed to create the queue.
-    }
-
-    // ...
-
-    // Send a pointer to a struct AMessage object.  Don't block if the
-    // queue is already full.
-    pxMessage = & xMessage;
-    xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );
-
-	// ... Rest of task code.
- }
-
- // Task to receive from the queue.
- void vADifferentTask( void *pvParameters )
- {
- struct AMessage *pxRxedMessage;
-
-    if( xQueue != 0 )
-    {
-        // Receive a message on the created queue.  Block for 10 ticks if a
-        // message is not immediately available.
-        if( xQueueReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )
-        {
-            // pcRxedMessage now points to the struct AMessage variable posted
-            // by vATask.
-        }
-    }
-
-	// ... Rest of task code.
- }
- 
- * \defgroup xQueueReceive xQueueReceive - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueReceive( xQueueHandle xQueue, void *pcBuffer, portTickType xTicksToWait ); - -/** - * queue. h - *
unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue );
- * - * Return the number of messages stored in a queue. - * - * @param xQueue A handle to the queue being queried. - * - * @return The number of messages available in the queue. - * - * \page uxQueueMessagesWaiting uxQueueMessagesWaiting - * \ingroup QueueManagement - */ -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue ); - -/** - * queue. h - *
void vQueueDelete( xQueueHandle xQueue );
- * - * Delete a queue - freeing all the memory allocated for storing of items - * placed on the queue. - * - * @param xQueue A handle to the queue to be deleted. - * - * \page vQueueDelete vQueueDelete - * \ingroup QueueManagement - */ -void vQueueDelete( xQueueHandle xQueue ); - -/** - * queue. h - *
- portBASE_TYPE xQueueSendFromISR( 
-                                    xQueueHandle pxQueue, 
-                                    const void *pvItemToQueue, 
-                                    portBASE_TYPE xTaskPreviouslyWoken 
-                                );
- 
- * - * Post an item on a queue. It is safe to use this function from within an - * interrupt service routine. - * - * Items are queued by copy not reference so it is preferable to only - * queue small items, especially when called from an ISR. In most cases - * it would be preferable to store a pointer to the item being queued. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param cTaskPreviouslyWoken This is included so an ISR can post onto - * the same queue multiple times from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. See the file serial .c in the - * PC port for a good example of this mechanism. - * - * @return pdTRUE if a task was woken by posting onto the queue. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage for buffered IO (where the ISR can obtain more than one value - * per call): -
- void vBufferISR( void )
- {
- portCHAR cIn;
- portBASE_TYPE xTaskWokenByPost;
-
-    // We have not woken a task at the start of the ISR.
-    cTaskWokenByPost = pdFALSE;
-
-    // Loop until the buffer is empty.
-    do
-    {
-        // Obtain a byte from the buffer.
-        cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );						
-
-        // Post the byte.  The first time round the loop cTaskWokenByPost
-        // will be pdFALSE.  If the queue send causes a task to wake we do
-        // not want the task to run until we have finished the ISR, so
-        // xQueueSendFromISR does not cause a context switch.  Also we 
-        // don't want subsequent posts to wake any other tasks, so we store
-        // the return value back into cTaskWokenByPost so xQueueSendFromISR
-        // knows not to wake any task the next iteration of the loop.
-        xTaskWokenByPost = xQueueSendFromISR( xRxQueue, &cIn, cTaskWokenByPost );
-
-    } while( portINPUT_BYTE( BUFFER_COUNT ) );
-
-    // Now the buffer is empty we can switch context if necessary.
-    if( cTaskWokenByPost )
-    {
-        taskYIELD ();
-    }
- }
- 
- * - * \defgroup xQueueSendFromISR xQueueSendFromISR - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ); - -/** - * queue. h - *
- portBASE_TYPE xQueueReceiveFromISR( 
-                                       xQueueHandle pxQueue, 
-                                       void *pcBuffer, 
-                                       portBASE_TYPE *pxTaskWoken 
-                                   ); 
- * 
- * - * Receive an item from a queue. It is safe to use this function from within an - * interrupt service routine. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pcBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param pcTaskWoken A task may be blocked waiting for space to become - * available on the queue. If xQueueReceiveFromISR causes such a task to - * unblock *pcTaskWoken will get set to pdTRUE, otherwise *pcTaskWoken will - * remain unchanged. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: -
- 
- xQueueHandle xQueue;
- 
- // Function to create a queue and post some values.
- void vAFunction( void *pvParameters )
- {
- portCHAR cValueToPost;
- const portTickType xBlockTime = ( portTickType )0xff;
-
-    // Create a queue capable of containing 10 characters.
-    xQueue = xQueueCreate( 10, sizeof( portCHAR ) );
-    if( xQueue == 0 )
-    {
-        // Failed to create the queue.
-    }
-
-    // ...
-
-    // Post some characters that will be used within an ISR.  If the queue
-    // is full then this task will block for xBlockTime ticks.
-    cValueToPost = 'a';
-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
-    cValueToPost = 'b';
-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
-
-    // ... keep posting characters ... this task may block when the queue
-    // becomes full.
-
-    cValueToPost = 'c';
-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );
- }
-
- // ISR that outputs all the characters received on the queue. 
- void vISR_Routine( void )
- {
- portBASE_TYPE xTaskWokenByReceive = pdFALSE;
- portCHAR cRxedChar;
-
-    while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
-    {
-        // A character was received.  Output the character now.
-        vOutputCharacter( cRxedChar );
-
-        // If removing the character from the queue woke the task that was 
-        // posting onto the queue cTaskWokenByReceive will have been set to
-        // pdTRUE.  No matter how many times this loop iterates only one
-        // task will be woken.
-    }
-
-    if( cTaskWokenByPost != ( portCHAR ) pdFALSE;
-    {
-        taskYIELD ();
-    }
- }
- 
- * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pcBuffer, signed portBASE_TYPE *pxTaskWoken ); - - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/semphr.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/semphr.h deleted file mode 100644 index e9e0159fb..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/semphr.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - FreeRTOS V3.2.4 - Copyright (C) 2003-2005 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include "queue.h" - -#ifndef SEMAPHORE_H -#define SEMAPHORE_H - -typedef xQueueHandle xSemaphoreHandle; - -#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( unsigned portCHAR ) 1 ) -#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( unsigned portCHAR ) 0 ) -#define semGIVE_BLOCK_TIME ( ( portTickType ) 0 ) - - -/** - * semphr. h - *
vSemaphoreCreateBinary( xSemaphoreHandle xSemaphore )
- * - * Macro that implements a semaphore by using the existing queue mechanism. - * The queue length is 1 as this is a binary semaphore. The data size is 0 - * as we don't want to actually store any data - we just want to know if the - * queue is empty or full. - * - * @param xSemaphore Handle to the created semaphore. Should be of type xSemaphoreHandle. - * - * Example usage: -
- xSemaphoreHandle xSemaphore;
-
- void vATask( void * pvParameters )
- {
-    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
-    // This is a macro so pass the variable in directly.
-    vSemaphoreCreateBinary( xSemaphore );
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.  
-    }
- }
- 
- * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary - * \ingroup Semaphores - */ -#define vSemaphoreCreateBinary( xSemaphore ) { \ - xSemaphore = xQueueCreate( ( unsigned portCHAR ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH ); \ - if( xSemaphore != NULL ) \ - { \ - xSemaphoreGive( xSemaphore ); \ - } \ - } - -/** - * semphr. h - * xSemaphoreTake( - * xSemaphoreHandle xSemaphore, - * portTickType xBlockTime - * ) - * - * Macro to obtain a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (). - * - * @param xSemaphore A handle to the semaphore being obtained. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @param xBlockTime The time in ticks to wait for the semaphore to become - * available. The macro portTICK_RATE_MS can be used to convert this to a - * real time. A block time of zero can be used to poll the semaphore. - * - * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime - * expired without the semaphore becoming available. - * - * Example usage: -
- xSemaphoreHandle xSemaphore = NULL;
-
- // A task that creates a semaphore.
- void vATask( void * pvParameters )
- {
-    // Create the semaphore to guard a shared resource.
-    vSemaphoreCreateBinary( xSemaphore );
- }
-
- // A task that uses the semaphore.
- void vAnotherTask( void * pvParameters )
- {
-    // ... Do other things.
-
-    if( xSemaphore != NULL )
-    {
-        // See if we can obtain the semaphore.  If the semaphore is not available
-        // wait 10 ticks to see if it becomes free.	
-        if( xSemaphoreTake( xSemaphore, ( portTickType ) 10 ) == pdTRUE )
-        {
-            // We were able to obtain the semaphore and can now access the
-            // shared resource.
-
-            // ...
-
-            // We have finished accessing the shared resource.  Release the 
-            // semaphore.
-            xSemaphoreGive( xSemaphore );
-        }
-        else
-        {
-            // We could not obtain the semaphore and can therefore not access
-            // the shared resource safely.
-        }
-    }
- }
- 
- * \defgroup xSemaphoreTake xSemaphoreTake - * \ingroup Semaphores - */ -#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueReceive( ( xQueueHandle ) xSemaphore, NULL, xBlockTime ) - -/** - * semphr. h - *
xSemaphoreGive( xSemaphoreHandle xSemaphore )
- * - * Macro to release a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (), and obtained using sSemaphoreTake (). - * - * This must not be used from an ISR. See xSemaphoreGiveFromISR () for - * an alternative which can be used from an ISR. - * - * @param xSemaphore A handle to the semaphore being released. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. - * Semaphores are implemented using queues. An error can occur if there is - * no space on the queue to post a message - indicating that the - * semaphore was not first obtained correctly. - * - * Example usage: -
- xSemaphoreHandle xSemaphore = NULL;
-
- void vATask( void * pvParameters )
- {
-    // Create the semaphore to guard a shared resource.
-    vSemaphoreCreateBinary( xSemaphore );
-
-    if( xSemaphore != NULL )
-    {
-        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
-        {
-            // We would expect this call to fail because we cannot give
-            // a semaphore without first "taking" it!
-        }
-
-        // Obtain the semaphore - don't block if the semaphore is not
-        // immediately available.
-        if( xSemaphoreTake( xSemaphore, ( portTickType ) 0 ) )
-        {
-            // We now have the semaphore and can access the shared resource.
-
-            // ...
-
-            // We have finished accessing the shared resource so can free the
-            // semaphore.
-            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
-            {
-                // We would not expect this call to fail because we must have
-                // obtained the semaphore to get here.
-            }
-        }
-    }
- }
- 
- * \defgroup xSemaphoreGive xSemaphoreGive - * \ingroup Semaphores - */ -#define xSemaphoreGive( xSemaphore ) xQueueSend( ( xQueueHandle ) xSemaphore, NULL, semGIVE_BLOCK_TIME ) - -/** - * semphr. h - *
- xSemaphoreGiveFromISR( 
-                          xSemaphoreHandle xSemaphore, 
-                          portSHORT sTaskPreviouslyWoken 
-                      )
- * - * Macro to release a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (), and obtained using xSemaphoreTake (). - * - * This macro can be used from an ISR. - * - * @param xSemaphore A handle to the semaphore being released. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @param sTaskPreviouslyWoken This is included so an ISR can make multiple calls - * to xSemaphoreGiveFromISR () from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. See the file serial .c in the - * PC port for a good example of using xSemaphoreGiveFromISR (). - * - * @return pdTRUE if a task was woken by releasing the semaphore. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage: -
- #define LONG_TIME 0xffff
- #define TICKS_TO_WAIT	10
- xSemaphoreHandle xSemaphore = NULL;
-
- // Repetitive task.
- void vATask( void * pvParameters )
- {
-    for( ;; )
-    {
-        // We want this task to run every 10 ticks or a timer.  The semaphore 
-        // was created before this task was started
-
-        // Block waiting for the semaphore to become available.
-        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
-        {
-            // It is time to execute.
-
-            // ...
-
-            // We have finished our task.  Return to the top of the loop where
-            // we will block on the semaphore until it is time to execute 
-            // again.
-        }
-    }
- }
-
- // Timer ISR
- void vTimerISR( void * pvParameters )
- {
- static unsigned portCHAR ucLocalTickCount = 0;
-
-    // A timer tick has occurred.
-
-    // ... Do other time functions.
-
-    // Is it time for vATask () to run?
-    ucLocalTickCount++;
-    if( ucLocalTickCount >= TICKS_TO_WAIT )
-    {
-        // Unblock the task by releasing the semaphore.
-        xSemaphoreGive( xSemaphore );
-
-        // Reset the count so we release the semaphore again in 10 ticks time.
-        ucLocalTickCount = 0;
-    }
- }
- 
- * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR - * \ingroup Semaphores - */ -#define xSemaphoreGiveFromISR( xSemaphore, xTaskPreviouslyWoken ) xQueueSendFromISR( ( xQueueHandle ) xSemaphore, NULL, xTaskPreviouslyWoken ) - - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/task.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/task.h deleted file mode 100644 index 811f499f1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/include/task.h +++ /dev/null @@ -1,906 +0,0 @@ -/* - FreeRTOS V3.2.4 - Copyright (C) 2003-2005 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef TASK_H -#define TASK_H - -#include "portable.h" -#include "list.h" - -/*----------------------------------------------------------- - * MACROS AND DEFINITIONS - *----------------------------------------------------------*/ - -#define tskKERNEL_VERSION_NUMBER "V3.2.4" - -/** - * task. h - * - * Type by which tasks are referenced. For example, a call to xTaskCreate - * returns (via a pointer parameter) an xTaskHandle variable that can then - * be used as a parameter to vTaskDelete to delete the task. - * - * \page xTaskHandle xTaskHandle - * \ingroup Tasks - */ -typedef void * xTaskHandle; - -/* - * Defines the priority used by the idle task. This must not be modified. - * - * \ingroup TaskUtils - */ -#define tskIDLE_PRIORITY ( ( unsigned portBASE_TYPE ) 0 ) - -/** - * task. h - * - * Macro for forcing a context switch. - * - * \page taskYIELD taskYIELD - * \ingroup SchedulerControl - */ -#define taskYIELD() portYIELD() - -/** - * task. h - * - * Macro to mark the start of a critical code region. Preemptive context - * switches cannot occur when in a critical region. - * - * NOTE: This may alter the stack (depending on the portable implementation) - * so must be used with care! - * - * \page taskENTER_CRITICAL taskENTER_CRITICAL - * \ingroup SchedulerControl - */ -#define taskENTER_CRITICAL() portENTER_CRITICAL() - -/** - * task. h - * - * Macro to mark the end of a critical code region. Preemptive context - * switches cannot occur when in a critical region. - * - * NOTE: This may alter the stack (depending on the portable implementation) - * so must be used with care! - * - * \page taskEXIT_CRITICAL taskEXIT_CRITICAL - * \ingroup SchedulerControl - */ -#define taskEXIT_CRITICAL() portEXIT_CRITICAL() - -/** - * task. h - * - * Macro to disable all maskable interrupts. - * - * \page taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS - * \ingroup SchedulerControl - */ -#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() - -/** - * task. h - * - * Macro to enable microcontroller interrupts. - * - * \page taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS - * \ingroup SchedulerControl - */ -#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() - - -/*----------------------------------------------------------- - * TASK CREATION API - *----------------------------------------------------------*/ - -/** - * task. h - *
- portBASE_TYPE xTaskCreate(
-                              pdTASK_CODE pvTaskCode,
-                              const portCHAR * const pcName,
-                              unsigned portSHORT usStackDepth,
-                              void *pvParameters,
-                              unsigned portBASE_TYPE uxPriority,
-                              xTaskHandle *pvCreatedTask
-                          );
- * - * Create a new task and add it to the list of tasks that are ready to run. - * - * @param pvTaskCode Pointer to the task entry function. Tasks - * must be implemented to never return (i.e. continuous loop). - * - * @param pcName A descriptive name for the task. This is mainly used to - * facilitate debugging. Max length defined by tskMAX_TASK_NAME_LEN - default - * is 16. - * - * @param usStackDepth The size of the task stack specified as the number of - * variables the stack can hold - not the number of bytes. For example, if - * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes - * will be allocated for stack storage. - * - * @param pvParameters Pointer that will be used as the parameter for the task - * being created. - * - * @param uxPriority The priority at which the task should run. - * - * @param pvCreatedTask Used to pass back a handle by which the created task - * can be referenced. - * - * @return pdPASS if the task was successfully created and added to a ready - * list, otherwise an error code defined in the file errors. h - * - * Example usage: -
- // Task to be created.
- void vTaskCode( void * pvParameters )
- {
-     for( ;; )
-     {
-         // Task code goes here.
-     }
- }
-
- // Function that creates a task.
- void vOtherFunction( void )
- {
- unsigned char ucParameterToPass;
- xTaskHandle xHandle;
-		
-     // Create the task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
-		
-     // Use the handle to delete the task.
-     vTaskDelete( xHandle );
- }
-   
- * \defgroup xTaskCreate xTaskCreate - * \ingroup Tasks - */ -signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pvCreatedTask ); - -/** - * task. h - *
void vTaskDelete( xTaskHandle pxTask );
- * - * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Remove a task from the RTOS real time kernels management. The task being - * deleted will be removed from all ready, blocked, suspended and event lists. - * - * NOTE: The idle task is responsible for freeing the kernel allocated - * memory from tasks that have been deleted. It is therefore important that - * the idle task is not starved of microcontroller processing time if your - * application makes any calls to vTaskDelete (). Memory allocated by the - * task code is not automatically freed, and should be freed before the task - * is deleted. - * - * See the demo application file death.c for sample code that utilises - * vTaskDelete (). - * - * @param pxTask The handle of the task to be deleted. Passing NULL will - * cause the calling task to be deleted. - * - * Example usage: -
- void vOtherFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create the task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-		
-     // Use the handle to delete the task.
-     vTaskDelete( xHandle );
- }
-   
- * \defgroup vTaskDelete vTaskDelete - * \ingroup Tasks - */ -void vTaskDelete( xTaskHandle pxTask ); - - -/*----------------------------------------------------------- - * TASK CONTROL API - *----------------------------------------------------------*/ - -/** - * task. h - *
void vTaskDelay( portTickType xTicksToDelay );
- * - * Delay a task for a given number of ticks. The actual time that the - * task remains blocked depends on the tick rate. The constant - * portTICK_RATE_MS can be used to calculate real time from the tick - * rate - with the resolution of one tick period. - * - * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * @param xTicksToDelay The amount of time, in tick periods, that - * the calling task should block. - * - * Example usage: -
- // Wait 10 ticks before performing an action.
- // NOTE:
- // This is for demonstration only and would be better achieved
- // using vTaskDelayUntil ().
- void vTaskFunction( void * pvParameters )
- {
- portTickType xDelay, xNextTime;
-
-     // Calc the time at which we want to perform the action
-     // next.
-     xNextTime = xTaskGetTickCount () + ( portTickType ) 10;
-
-     for( ;; )
-     {
-         xDelay = xNextTime - xTaskGetTickCount ();
-         xNextTime += ( portTickType ) 10;
-
-         // Guard against overflow
-         if( xDelay <= ( portTickType ) 10 )
-         {
-             vTaskDelay( xDelay );
-         }
-
-         // Perform action here.
-     }
- }
-   
- * \defgroup vTaskDelay vTaskDelay - * \ingroup TaskCtrl - */ -void vTaskDelay( portTickType xTicksToDelay ); - -/** - * task. h - *
void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement );
- * - * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Delay a task until a specified time. This function can be used by cyclical - * tasks to ensure a constant execution frequency. - * - * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will - * cause a task to block for the specified number of ticks from the time vTaskDelay () is - * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed - * execution frequency as the time between a task starting to execute and that task - * calling vTaskDelay () may not be fixed [the task may take a different path though the - * code between calls, or may get interrupted or preempted a different number of times - * each time it executes]. - * - * Whereas vTaskDelay () specifies a wake time relative to the time at which the function - * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to - * unblock. - * - * The constant portTICK_RATE_MS can be used to calculate real time from the tick - * rate - with the resolution of one tick period. - * - * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the - * task was last unblocked. The variable must be initialised with the current time - * prior to its first use (see the example below). Following this the variable is - * automatically updated within vTaskDelayUntil (). - * - * @param xTimeIncrement The cycle time period. The task will be unblocked at - * time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the - * same xTimeIncrement parameter value will cause the task to execute with - * a fixed interface period. - * - * Example usage: -
- // Perform an action every 10 ticks.
- void vTaskFunction( void * pvParameters )
- {
- portTickType xLastWakeTime;
- const portTickType xFrequency = 10;
-
-     // Initialise the xLastWakeTime variable with the current time.
-     xLastWakeTime = xTaskGetTickCount ();
-     for( ;; )
-     {
-         // Wait for the next cycle.
-         vTaskDelayUntil( &xLastWakeTime, xFrequency );
-
-         // Perform action here.
-     }
- }
-   
- * \defgroup vTaskDelayUntil vTaskDelayUntil - * \ingroup TaskCtrl - */ -void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement ); - -/** - * task. h - *
unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask );
- * - * INCLUDE_xTaskPriorityGet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Obtain the priority of any task. - * - * @param pxTask Handle of the task to be queried. Passing a NULL - * handle results in the priority of the calling task being returned. - * - * @return The priority of pxTask. - * - * Example usage: -
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create a task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-		
-     // ...
-
-     // Use the handle to obtain the priority of the created task.
-     // It was created with tskIDLE_PRIORITY, but may have changed
-     // it itself.
-     if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
-     {
-         // The task has changed it's priority.
-     }
-
-     // ...
-
-     // Is our priority higher than the created task?
-     if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
-     {
-         // Our priority (obtained using NULL handle) is higher.
-     }
- }
-   
- * \defgroup uxTaskPriorityGet uxTaskPriorityGet - * \ingroup TaskCtrl - */ -unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ); - -/** - * task. h - *
void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );
- * - * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Set the priority of any task. - * - * A context switch will occur before the function returns if the priority - * being set is higher than the currently executing task. - * - * @param pxTask Handle to the task for which the priority is being set. - * Passing a NULL handle results in the priority of the calling task being set. - * - * @param uxNewPriority The priority to which the task will be set. - * - * Example usage: -
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create a task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-     // ...
-
-     // Use the handle to raise the priority of the created task.
-     vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
-
-     // ...
-
-     // Use a NULL handle to raise our priority to the same value.
-     vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
- }
-   
- * \defgroup vTaskPrioritySet vTaskPrioritySet - * \ingroup TaskCtrl - */ -void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ); - -/** - * task. h - *
void vTaskSuspend( xTaskHandle pxTaskToSuspend );
- * - * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Suspend any task. When suspended a task will never get any microcontroller - * processing time, no matter what its priority. - * - * Calls to vTaskSuspend are not accumulative - - * i.e. calling vTaskSuspend () twice on the same task still only requires one - * call to vTaskResume () to ready the suspended task. - * - * @param pxTaskToSuspend Handle to the task being suspended. Passing a NULL - * handle will cause the calling task to be suspended. - * - * Example usage: -
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create a task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-		
-     // ...
-
-     // Use the handle to suspend the created task.
-     vTaskSuspend( xHandle );
-
-     // ...
-		
-     // The created task will not run during this period, unless
-     // another task calls vTaskResume( xHandle ).
-		
-     //...
-		
-
-     // Suspend ourselves.
-     vTaskSuspend( NULL );
-
-     // We cannot get here unless another task calls vTaskResume
-     // with our handle as the parameter.
- }
-   
- * \defgroup vTaskSuspend vTaskSuspend - * \ingroup TaskCtrl - */ -void vTaskSuspend( xTaskHandle pxTaskToSuspend ); - -/** - * task. h - *
void vTaskResume( xTaskHandle pxTaskToResume );
- * - * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Resumes a suspended task. - * - * A task that has been suspended by one of more calls to vTaskSuspend () - * will be made available for running again by a single call to - * vTaskResume (). - * - * @param pxTaskToResume Handle to the task being readied. - * - * Example usage: -
- void vAFunction( void )
- {
- xTaskHandle xHandle;
-		
-     // Create a task, storing the handle.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-		
-     // ...
-
-     // Use the handle to suspend the created task.
-     vTaskSuspend( xHandle );
-
-     // ...
-	
-     // The created task will not run during this period, unless
-     // another task calls vTaskResume( xHandle ).
-		
-     //...
-		
-
-     // Resume the suspended task ourselves.
-     vTaskResume( xHandle );
-
-     // The created task will once again get microcontroller processing
-     // time in accordance with it priority within the system.
- }
-   
- * \defgroup vTaskResume vTaskResume - * \ingroup TaskCtrl - */ -void vTaskResume( xTaskHandle pxTaskToResume ); - -/*----------------------------------------------------------- - * SCHEDULER CONTROL - *----------------------------------------------------------*/ - -/** - * task. h - *
void vTaskStartScheduler( void );
- * - * Starts the real time kernel tick processing. After calling the kernel - * has control over which tasks are executed and when. This function - * does not return until an executing task calls vTaskEndScheduler (). - * - * At least one task should be created via a call to xTaskCreate () - * before calling vTaskStartScheduler (). The idle task is created - * automatically when the first application task is created. - * - * See the demo application file main.c for an example of creating - * tasks and starting the kernel. - * - * Example usage: -
- void vAFunction( void )
- {
-     // Create at least one task before starting the kernel.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
-     // Start the real time kernel with preemption.
-     vTaskStartScheduler ();
-
-     // Will not get here unless a task calls vTaskEndScheduler ()
- }
-   
- * - * \defgroup vTaskStartScheduler vTaskStartScheduler - * \ingroup SchedulerControl - */ -void vTaskStartScheduler( void ); - -/** - * task. h - *
void vTaskEndScheduler( void );
- * - * Stops the real time kernel tick. All created tasks will be automatically - * deleted and multitasking (either preemptive or cooperative) will - * stop. Execution then resumes from the point where vTaskStartScheduler () - * was called, as if vTaskStartScheduler () had just returned. - * - * See the demo application file main. c in the demo/PC directory for an - * example that uses vTaskEndScheduler (). - * - * vTaskEndScheduler () requires an exit function to be defined within the - * portable layer (see vPortEndScheduler () in port. c for the PC port). This - * performs hardware specific operations such as stopping the kernel tick. - * - * vTaskEndScheduler () will cause all of the resources allocated by the - * kernel to be freed - but will not free resources allocated by application - * tasks. - * - * Example usage: -
- void vTaskCode( void * pvParameters )
- {
-     for( ;; )
-     {
-         // Task code goes here.
-
-         // At some point we want to end the real time kernel processing
-         // so call ...
-         vTaskEndScheduler ();
-     }
- }
-
- void vAFunction( void )
- {
-     // Create at least one task before starting the kernel.
-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
-     // Start the real time kernel with preemption.
-     vTaskStartScheduler ();
-
-     // Will only get here when the vTaskCode () task has called
-     // vTaskEndScheduler ().  When we get here we are back to single task
-     // execution.
- }
-   
- * - * \defgroup vTaskEndScheduler vTaskEndScheduler - * \ingroup SchedulerControl - */ -void vTaskEndScheduler( void ); - -/** - * task. h - *
void vTaskSuspendAll( void );
- * - * Suspends all real time kernel activity while keeping interrupts (including the - * kernel tick) enabled. - * - * After calling vTaskSuspendAll () the calling task will continue to execute - * without risk of being swapped out until a call to xTaskResumeAll () has been - * made. - * - * Example usage: -
- void vTask1( void * pvParameters )
- {
-     for( ;; )
-     {
-         // Task code goes here.
-
-         // ...
-
-         // At some point the task wants to perform a long operation during
-         // which it does not want to get swapped out.  It cannot use
-         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
-         // operation may cause interrupts to be missed - including the
-         // ticks.
-
-         // Prevent the real time kernel swapping out the task.
-         vTaskSuspendAll ();
-
-         // Perform the operation here.  There is no need to use critical
-         // sections as we have all the microcontroller processing time.
-         // During this time interrupts will still operate and the kernel
-         // tick count will be maintained.
-
-         // ...
-
-         // The operation is complete.  Restart the kernel.
-         xTaskResumeAll ();
-     }
- }
-   
- * \defgroup vTaskSuspendAll vTaskSuspendAll - * \ingroup SchedulerControl - */ -void vTaskSuspendAll( void ); - -/** - * task. h - *
portCHAR xTaskResumeAll( void );
- * - * Resumes real time kernel activity following a call to vTaskSuspendAll (). - * After a call to vTaskSuspendAll () the kernel will take control of which - * task is executing at any time. - * - * @return If resuming the scheduler caused a context switch then pdTRUE is - * returned, otherwise pdFALSE is returned. - * - * Example usage: -
- void vTask1( void * pvParameters )
- {
-     for( ;; )
-     {
-         // Task code goes here.
-
-         // ...
-
-         // At some point the task wants to perform a long operation during
-         // which it does not want to get swapped out.  It cannot use
-         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
-         // operation may cause interrupts to be missed - including the
-         // ticks.
-
-         // Prevent the real time kernel swapping out the task.
-         vTaskSuspendAll ();
-
-         // Perform the operation here.  There is no need to use critical
-         // sections as we have all the microcontroller processing time.
-         // During this time interrupts will still operate and the real
-         // time kernel tick count will be maintained.
-
-         // ...
-
-         // The operation is complete.  Restart the kernel.  We want to force
-         // a context switch - but there is no point if resuming the scheduler
-         // caused a context switch already.
-         if( !xTaskResumeAll () )
-         {
-              taskYIELD ();
-         }
-     }
- }
-   
- * \defgroup xTaskResumeAll xTaskResumeAll - * \ingroup SchedulerControl - */ -signed portBASE_TYPE xTaskResumeAll( void ); - - -/*----------------------------------------------------------- - * TASK UTILITIES - *----------------------------------------------------------*/ - -/** - * task. h - *
volatile portTickType xTaskGetTickCount( void );
- * - * @return The count of ticks since vTaskStartScheduler was called. - * - * \page xTaskGetTickCount xTaskGetTickCount - * \ingroup TaskUtils - */ -portTickType xTaskGetTickCount( void ); - -/** - * task. h - *
unsigned portSHORT uxTaskGetNumberOfTasks( void );
- * - * @return The number of tasks that the real time kernel is currently managing. - * This includes all ready, blocked and suspended tasks. A task that - * has been deleted but not yet freed by the idle task will also be - * included in the count. - * - * \page uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks - * \ingroup TaskUtils - */ -unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ); - -/** - * task. h - *
void vTaskList( portCHAR *pcWriteBuffer );
- * - * configUSE_TRACE_FACILITY, INCLUDE_vTaskDelete and INCLUDE_vTaskSuspend - * must all be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * NOTE: This function will disable interrupts for its duration. It is - * not intended for normal application runtime use but as a debug aid. - * - * Lists all the current tasks, along with their current state and stack - * usage high water mark. - * - * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or - * suspended ('S'). - * - * @param pcWriteBuffer A buffer into which the above mentioned details - * will be written, in ascii form. This buffer is assumed to be large - * enough to contain the generated report. Approximately 40 bytes per - * task should be sufficient. - * - * \page vTaskList vTaskList - * \ingroup TaskUtils - */ -void vTaskList( signed portCHAR *pcWriteBuffer ); - -/** - * task. h - *
void vTaskStartTrace( portCHAR * pcBuffer, unsigned portBASE_TYPE uxBufferSize );
- * - * Starts a real time kernel activity trace. The trace logs the identity of - * which task is running when. - * - * The trace file is stored in binary format. A separate DOS utility called - * convtrce.exe is used to convert this into a tab delimited text file which - * can be viewed and plotted in a spread sheet. - * - * @param pcBuffer The buffer into which the trace will be written. - * - * @param ulBufferSize The size of pcBuffer in bytes. The trace will continue - * until either the buffer in full, or ulTaskEndTrace () is called. - * - * \page vTaskStartTrace vTaskStartTrace - * \ingroup TaskUtils - */ -void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ); - -/** - * task. h - *
unsigned portLONG ulTaskEndTrace( void );
- * - * Stops a kernel activity trace. See vTaskStartTrace (). - * - * @return The number of bytes that have been written into the trace buffer. - * - * \page usTaskEndTrace usTaskEndTrace - * \ingroup TaskUtils - */ -unsigned portLONG ulTaskEndTrace( void ); - - -/*----------------------------------------------------------- - * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES - *----------------------------------------------------------*/ - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY - * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS - * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * Called from the real time kernel tick (either preemptive or cooperative), - * this increments the tick count and checks if any tasks that are blocked - * for a finite period required removing from a blocked list and placing on - * a ready list. - */ -inline void vTaskIncrementTick( void ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. - * - * Removes the calling task from the ready list and places it both - * on the list of tasks waiting for a particular event, and the - * list of delayed tasks. The task will be removed from both lists - * and replaced on the ready list should either the event occur (and - * there be no higher priority tasks waiting on the same event) or - * the delay period expires. - * - * @param pxEventList The list containing tasks that are blocked waiting - * for the event to occur. - * - * @param xTicksToWait The maximum amount of time that the task should wait - * for the event to occur. This is specified in kernel ticks,the constant - * portTICK_RATE_MS can be used to convert kernel ticks into a real time - * period. - */ -void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. - * - * Removes a task from both the specified event list and the list of blocked - * tasks, and places it on a ready queue. - * - * xTaskRemoveFromEventList () will be called if either an event occurs to - * unblock a task, or the block timeout period expires. - * - * @return pdTRUE if the task being removed has a higher priority than the task - * making the call, otherwise pdFALSE. - */ -signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * INCLUDE_vTaskCleanUpResources and INCLUDE_vTaskSuspend must be defined as 1 - * for this function to be available. - * See the configuration section for more information. - * - * Empties the ready and delayed queues of task control blocks, freeing the - * memory allocated for the task control block and task stacks as it goes. - */ -void vTaskCleanUpResources( void ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY - * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS - * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * Sets the pointer to the current TCB to the TCB of the highest priority task - * that is ready to run. - */ -inline void vTaskSwitchContext( void ); - -/* - * Return the handle of the calling task. - */ -xTaskHandle xTaskGetCurrentTaskHandle( void ); - - -#endif /* TASK_H */ - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/list.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/list.c deleted file mode 100644 index 2ffcc2250..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/list.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - FreeRTOS V3.2.4 - Copyright (C) 2003-2005 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.2.0 - - + Removed the volatile modifier from the function parameters. This was - only ever included to prevent compiler warnings. Now warnings are - removed by casting parameters where the calls are made. - - + prvListGetOwnerOfNextEntry() and prvListGetOwnerOfHeadEntry() have been - removed from the c file and added as macros to the h file. - - + uxNumberOfItems has been added to the list structure. This removes the - need for a pointer comparison when checking if a list is empty, and so - is slightly faster. - - + Removed the NULL check in vListRemove(). This makes the call faster but - necessitates any application code utilising the list implementation to - ensure NULL pointers are not passed. - -Changes from V2.0.0 - - + Double linked the lists to allow faster removal item removal. - -Changes from V2.6.1 - - + Make use of the new portBASE_TYPE definition where ever appropriate. - -Changes from V3.0.0 - - + API changes as described on the FreeRTOS.org WEB site. -*/ - -#include -#include "FreeRTOS.h" -#include "list.h" - -/*----------------------------------------------------------- - * PUBLIC LIST API documented in list.h - *----------------------------------------------------------*/ - -void vListInitialise( xList *pxList ) -{ - /* The list structure contains a list item which is used to mark the - end of the list. To initialise the list the list end is inserted - as the only list entry. */ - pxList->pxHead = &( pxList->xListEnd ); - pxList->pxIndex = pxList->pxHead; - - /* The list end value is the highest possible value in the list to - ensure it remains at the end of the list. */ - pxList->xListEnd.xItemValue = portMAX_DELAY; - - /* The list end next and previous pointers point to itself so we know - when the list is empty. */ - pxList->xListEnd.pxNext = &( pxList->xListEnd ); - pxList->xListEnd.pxPrevious = &( pxList->xListEnd ); - - /* The list head will never get used and has no owner. */ - pxList->xListEnd.pvOwner = NULL; - - /* Make sure the marker items are not mistaken for being on a list. */ - vListInitialiseItem( ( xListItem * ) &( pxList->xListEnd ) ); - - pxList->uxNumberOfItems = 0; -} -/*-----------------------------------------------------------*/ - -void vListInitialiseItem( xListItem *pxItem ) -{ - /* Make sure the list item is not recorded as being on a list. */ - pxItem->pvContainer = NULL; -} -/*-----------------------------------------------------------*/ - -void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ) -{ -volatile xListItem * pxIndex; - - /* Insert a new list item into pxList, but rather than sort the list, - makes the new list item the last item to be removed by a call to - pvListGetOwnerOfNextEntry. This means it has to be the item pointed to by - the pxIndex member. */ - pxIndex = pxList->pxIndex; - - pxNewListItem->pxNext = pxIndex->pxNext; - pxNewListItem->pxPrevious = pxList->pxIndex; - pxIndex->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; - pxIndex->pxNext = ( volatile xListItem * ) pxNewListItem; - pxList->pxIndex = ( volatile xListItem * ) pxNewListItem; - - /* Remember which list the item is in. */ - pxNewListItem->pvContainer = ( void * ) pxList; - - ( pxList->uxNumberOfItems )++; -} -/*-----------------------------------------------------------*/ - -void vListInsert( xList *pxList, xListItem *pxNewListItem ) -{ -volatile xListItem *pxIterator; -register portTickType xValueOfInsertion; - - /* Insert the new list item into the list, sorted in ulListItem order. */ - xValueOfInsertion = pxNewListItem->xItemValue; - - /* If the list already contains a list item with the same item value then - the new list item should be placed after it. This ensures that TCB's which - are stored in ready lists (all of which have the same ulListItem value) - get an equal share of the CPU. However, if the xItemValue is the same as - the back marker the iteration loop below will not end. This means we need - to guard against this by checking the value first and modifying the - algorithm slightly if necessary. */ - if( xValueOfInsertion == portMAX_DELAY ) - { - for( pxIterator = pxList->pxHead; pxIterator->pxNext->xItemValue < xValueOfInsertion; pxIterator = pxIterator->pxNext ) - { - /* There is nothing to do here, we are just iterating to the - wanted insertion position. */ - } - } - else - { - for( pxIterator = pxList->pxHead; pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) - { - /* There is nothing to do here, we are just iterating to the - wanted insertion position. */ - } - } - - pxNewListItem->pxNext = pxIterator->pxNext; - pxNewListItem->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; - pxNewListItem->pxPrevious = pxIterator; - pxIterator->pxNext = ( volatile xListItem * ) pxNewListItem; - - /* Remember which list the item is in. This allows fast removal of the - item later. */ - pxNewListItem->pvContainer = ( void * ) pxList; - - ( pxList->uxNumberOfItems )++; -} -/*-----------------------------------------------------------*/ - -void vListRemove( xListItem *pxItemToRemove ) -{ -xList * pxList; - - pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; - pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; - - /* The list item knows which list it is in. Obtain the list from the list - item. */ - pxList = ( xList * ) pxItemToRemove->pvContainer; - - /* Make sure the index is left pointing to a valid item. */ - if( pxList->pxIndex == pxItemToRemove ) - { - pxList->pxIndex = pxItemToRemove->pxPrevious; - } - - pxItemToRemove->pvContainer = NULL; - ( pxList->uxNumberOfItems )--; -} -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/GCC/ARM7_STR71X/port.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/GCC/ARM7_STR71X/port.c deleted file mode 100644 index cd512764d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/GCC/ARM7_STR71X/port.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - FreeRTOS V3.2.4 - Copyright (C) 2003-2005 Richard Barry. - Modification for STR71X/GCC - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/*----------------------------------------------------------- - * Implementation of functions defined in portable.h for the ARM7 port. - * - * Components that can be compiled to either ARM or THUMB mode are - * contained in this file. The ISR routines, which can only be compiled - * to ARM mode are contained in portISR.c. - *----------------------------------------------------------*/ - -/* - Changes from V2.5.2 - - + ulCriticalNesting is now saved as part of the task context, as is - therefore added to the initial task stack during pxPortInitialiseStack. - - Changes from V3.2.2 - - + Bug fix - The prescale value for the timer setup is now written to T0_PR - instead of T0_PC. This bug would have had no effect unless a prescale - value was actually used. -*/ - - -/* Standard includes. */ -#include - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Port specific includes */ -#include "eic.h" -#include "wdg.h" - -/* Constants required to setup the task context. */ -#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) -#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) - -/*-----------------------------------------------------------*/ - -/* Setup the timer to generate the tick interrupts. */ -static void prvSetupTimerInterrupt( void ); - -/* - * The scheduler can only be started from ARM mode, so - * vPortISRStartFirstSTask() is defined in portISR.c. - */ -extern void vPortISRStartFirstTask( void ); - -/*-----------------------------------------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - * - * See header file for description. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ -portSTACK_TYPE *pxOriginalTOS; - - pxOriginalTOS = pxTopOfStack; - - /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ - - /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - R0. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack--; - - /* The last thing onto the stack is the status register, which is set for - system mode, with interrupts enabled. */ - *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; - - #ifdef THUMB_INTERWORK - { - /* We want the task to start in thumb mode. */ - *pxTopOfStack |= portTHUMB_MODE_BIT; - } - #endif - - pxTopOfStack--; - - /* Some optimisation levels use the stack differently to others. This - means the interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ - *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; - - return pxTopOfStack; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xPortStartScheduler( void ) -{ - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt(); - - /* Start the first task. */ - vPortISRStartFirstTask(); - - /* Should not get here! */ - return 0; -} -/*-----------------------------------------------------------*/ - -void vPortEndScheduler( void ) -{ - /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ -} -/*-----------------------------------------------------------*/ - -/*! - * Setup timer 3 to generate ticks at the required frequency. - */ -static void prvSetupTimerInterrupt( void ) -{ - /* Set the watchdog up to generate a periodic tick. */ - WDG_ECITConfig( DISABLE ); - WDG_CntOnOffConfig( DISABLE ); - WDG_PeriodValueConfig( configTICK_RATE_HZ ); - - /* Setup the tick interrupt in the EIC. */ - EIC_IRQChannelPriorityConfig( WDG_IRQChannel, 1 ); - EIC_IRQChannelConfig( WDG_IRQChannel, ENABLE ); - EIC_IRQConfig( ENABLE ); - WDG_ECITConfig( ENABLE ); - - /* Start the timer - interrupts are actually disabled at this point so - it is safe to do this here. */ - WDG_CntOnOffConfig( ENABLE ); -} -/*-----------------------------------------------------------*/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/GCC/ARM7_STR71X/portISR.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/GCC/ARM7_STR71X/portISR.c deleted file mode 100644 index 7265186ed..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/GCC/ARM7_STR71X/portISR.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - FreeRTOS V3.2.4 - Copyright (C) 2003-2005 Richard Barry. - Modification for STR71X/GCC - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Port specific includes */ -#include "eic.h" -#include "wdg.h" - -/* Constants required to handle critical sections. */ -#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) - -/* Import global variables declared in the port file. */ -extern const portSHORT portTimerOCRDeltaValue; - -volatile unsigned portLONG ulCriticalNesting = 9999UL; - -/*-----------------------------------------------------------*/ - -/* ISR to handle manual context switches (from a call to taskYIELD()). */ -void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked)); - -/* - * The scheduler can only be started from ARM mode, hence the inclusion of this - * function here. - */ -void vPortISRStartFirstTask( void ); -/*-----------------------------------------------------------*/ - -void vPortISRStartFirstTask( void ) -{ - /* Simply start the scheduler. This is included here as it can only be - called from ARM mode. */ - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * Called by portYIELD() or taskYIELD() to manually force a context switch. - * - * When a context switch is performed from the task level the saved task - * context is made to look as if it occurred from within the tick ISR. This - * way the same restore context function can be used when restoring the context - * saved from the ISR or that saved from a call to vPortYieldProcessor. - */ -void vPortYieldProcessor( void ) -{ - /* Within an IRQ ISR the link register has an offset from the true return - address, but an SWI ISR does not. Add the offset manually so the same - ISR return code can be used in both cases. */ - asm volatile ( "ADD LR, LR, #4" ); - - /* Perform the context switch. First save the context of the current task. */ - portSAVE_CONTEXT(); - - /* Find the highest priority task that is ready to run. */ - vTaskSwitchContext(); - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT(); -} -/*-----------------------------------------------------------*/ - -/* - * The ISR used for the scheduler tick depends on whether the cooperative or - * the preemptive scheduler is being used. - */ -#if configUSE_PREEMPTION == 0 - -/* The cooperative scheduler requires a normal IRQ service routine to - * simply increment the system tick. - */ -void vPortNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ"))); -void vPortNonPreemptiveTick( void ) -{ - vTaskIncrementTick(); - - /* Clear the interrupt in the watchdog and EIC. */ - WDG->SR = 0x0000; - /* clear current interrupt pending flag for interupt source. */ - EIC->IPR |= 1 << EIC_CurrentIRQChannelValue(); -} - -#else - -/* The preemptive scheduler is defined as "naked" as the full context is - * saved on entry as part of the context switch. - */ -void vPortPreemptiveTick( void ) __attribute__((naked)); -void vPortPreemptiveTick( void ) -{ - /* Save the context of the interrupted task. */ - portSAVE_CONTEXT(); - - /* Increment the RTOS tick count, then look for the highest priority - * task that is ready to run. - */ - vTaskIncrementTick(); - vTaskSwitchContext(); - - /* Clear the interrupt in the watchdog and EIC. */ - WDG->SR = 0x0000; - /* clear current interrupt pending flag for interupt source. */ - EIC->IPR |= 1 << EIC_CurrentIRQChannelValue(); - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT(); -} - -#endif -/*-----------------------------------------------------------*/ - -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions here to - * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then - * the utilities are defined as macros in portmacro.h - as per other ports. - */ -#ifdef THUMB_INTERWORK - - void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); - - void vPortDisableInterruptsFromThumb( void ) - { - asm volatile ( "STMDB SP!, {R0}" ); /* Push R0. */ - asm volatile ( "MRS R0, CPSR" ); /* Get CPSR. */ - asm volatile ( "ORR R0, R0, #0xC0" ); /* Disable IRQ, FIQ. */ - asm volatile ( "MSR CPSR, R0" ); /* Write back modified value. */ - asm volatile ( "LDMIA SP!, {R0}" ); /* Pop R0. */ - asm volatile ( "BX R14" ); /* Return back to thumb. */ - } - - void vPortEnableInterruptsFromThumb( void ) - { - asm volatile ( "STMDB SP!, {R0}" ); /* Push R0. */ - asm volatile ( "MRS R0, CPSR" ); /* Get CPSR. */ - asm volatile ( "BIC R0, R0, #0xC0" ); /* Enable IRQ, FIQ. */ - asm volatile ( "MSR CPSR, R0" ); /* Write back modified value. */ - asm volatile ( "LDMIA SP!, {R0}" ); /* Pop R0. */ - asm volatile ( "BX R14" ); /* Return back to thumb. */ - } - -#endif /* THUMB_INTERWORK */ - -/* The code generated by the GCC compiler uses the stack in different ways at -different optimisation levels. The interrupt flags can therefore not always -be saved to the stack. Instead the critical section nesting level is stored -in a variable, which is then saved as part of the stack context. */ -void vPortEnterCritical( void ) -{ - /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ - asm volatile ( "STMDB SP!, {R0}" ); /* Push R0. */ - asm volatile ( "MRS R0, CPSR" ); /* Get CPSR. */ - asm volatile ( "ORR R0, R0, #0xC0" ); /* Disable IRQ, FIQ. */ - asm volatile ( "MSR CPSR, R0" ); /* Write back modified value. */ - asm volatile ( "LDMIA SP!, {R0}" ); /* Pop R0. */ - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ - ulCriticalNesting++; -} - -void vPortExitCritical( void ) -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - /* Enable interrupts as per portEXIT_CRITICAL(). */ - asm volatile ( "STMDB SP!, {R0}" ); /* Push R0. */ - asm volatile ( "MRS R0, CPSR" ); /* Get CPSR. */ - asm volatile ( "BIC R0, R0, #0xC0" ); /* Enable IRQ, FIQ. */ - asm volatile ( "MSR CPSR, R0" ); /* Write back modified value. */ - asm volatile ( "LDMIA SP!, {R0}" ); /* Pop R0. */ - } - } -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/GCC/ARM7_STR71X/portmacro.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/GCC/ARM7_STR71X/portmacro.h deleted file mode 100644 index 500a9eebb..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/GCC/ARM7_STR71X/portmacro.h +++ /dev/null @@ -1,241 +0,0 @@ -/* - FreeRTOS V3.2.4 - Copyright (C) 2003-2005 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - Changes from V3.2.3 - - + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE portLONG - -#if( configUSE_16_BIT_TICKS == 1 ) - typedef unsigned portSHORT portTickType; - #define portMAX_DELAY ( portTickType ) 0xffff -#else - typedef unsigned portLONG portTickType; - #define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -/*-----------------------------------------------------------*/ - - -/* Scheduler utilities. */ - -/* - * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR - * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but - * are included here for efficiency. An attempt to call one from - * THUMB mode code will result in a compile time error. - */ - -#define portRESTORE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile unsigned portLONG ulCriticalNesting; \ - \ - /* Set the LR to the task stack. */ \ - asm volatile ( "LDR R0, %0" : : "m" (pxCurrentTCB) ); \ - asm volatile ( "LDR LR, [R0]" ); \ - \ - /* The critical nesting depth is the first item on the stack. */ \ - /* Load it into the ulCriticalNesting variable. */ \ - asm volatile ( "LDR R0, =ulCriticalNesting" ); \ - asm volatile ( "LDMFD LR!, {R1}" ); \ - asm volatile ( "STR R1, [R0]" ); \ - \ - /* Get the SPSR from the stack. */ \ - asm volatile ( "LDMFD LR!, {R0}" ); \ - asm volatile ( "MSR SPSR, R0" ); \ - \ - /* Restore all system mode registers for the task. */ \ - asm volatile ( "LDMFD LR, {R0-R14}^" ); \ - asm volatile ( "NOP" ); \ - \ - /* Restore the return address. */ \ - asm volatile ( "LDR LR, [LR, #+60]" ); \ - \ - /* And return - correcting the offset in the LR to obtain the */ \ - /* correct address. */ \ - asm volatile ( "SUBS PC, LR, #4" ); \ - ( void ) ulCriticalNesting; \ -} -/*-----------------------------------------------------------*/ - -#define portSAVE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile unsigned portLONG ulCriticalNesting; \ - \ - /* Push R0 as we are going to use the register. */ \ - asm volatile ( "STMDB SP!, {R0}" ); \ - \ - /* Set R0 to point to the task stack pointer. */ \ - asm volatile ( "STMDB SP,{SP}^" ); \ - asm volatile ( "SUB SP, SP, #4" ); \ - asm volatile ( "LDMIA SP!,{R0}" ); \ - \ - /* Push the return address onto the stack. */ \ - asm volatile ( "STMDB R0!, {LR}" ); \ - \ - /* Now we have saved LR we can use it instead of R0. */ \ - asm volatile ( "MOV LR, R0" ); \ - \ - /* Pop R0 so we can save it onto the system mode stack. */ \ - asm volatile ( "LDMIA SP!, {R0}" ); \ - \ - /* Push all the system mode registers onto the task stack. */ \ - asm volatile ( "STMDB LR,{R0-LR}^"); \ - asm volatile ( "SUB LR, LR, #60" ); \ - \ - /* Push the SPSR onto the task stack. */ \ - asm volatile ( "MRS R0, SPSR" ); \ - asm volatile ( "STMDB LR!, {R0}" ); \ - \ - asm volatile ( "LDR R0, =ulCriticalNesting " ); \ - asm volatile ( "LDR R0, [R0]" ); \ - asm volatile ( "STMDB LR!, {R0}" ); \ - \ - /* Store the new top of stack for the task. */ \ - asm volatile ( "LDR R0, %0" : : "m" (pxCurrentTCB) ); \ - asm volatile ( "STR LR, [R0]" ); \ - ( void ) ulCriticalNesting; \ -} - - -/*----------------------------------------------------------- - * ISR entry and exit macros. These are only required if a task switch - * is required from the ISR. - *----------------------------------------------------------*/ - - -#define portENTER_SWITCHING_ISR() \ - /* Save the context of the interrupted task. */ \ - portSAVE_CONTEXT(); \ - \ - /* We don't know the stack requirements for the ISR, so the frame */\ - /* pointer will be set to the top of the task stack, and the stack*/\ - /* pointer left where it is. The IRQ stack will get used for any */\ - /* functions calls made by this ISR. */ \ - asm volatile ( "SUB R11, LR, #4" ); \ - { - -#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ - /* If a switch is required then we just need to call */ \ - /* vTaskSwitchContext() as the context has already been */ \ - /* saved. */ \ - if( SwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ - } \ - /* Restore the context of which ever task is now the highest */ \ - /* priority that is ready to run. */ \ - portRESTORE_CONTEXT(); - -#define portYIELD() asm volatile ( "SWI" ); -/*-----------------------------------------------------------*/ - - -/* Critical section management. */ - -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions in - * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not - * defined then the utilities are defined as macros here - as per other ports. - */ - -#ifdef THUMB_INTERWORK - - extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked)); - extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked)); - - #define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() - #define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() - -#else - - #define portDISABLE_INTERRUPTS() \ - asm volatile ( "STMDB SP!, {R0}" ); /* Push R0. */ \ - asm volatile ( "MRS R0, CPSR" ); /* Get CPSR. */ \ - asm volatile ( "ORR R0, R0, #0xC0" ); /* Disable IRQ, FIQ. */ \ - asm volatile ( "MSR CPSR, R0" ); /* Write back modified value. */ \ - asm volatile ( "LDMIA SP!, {R0}" ) /* Pop R0. */ - - #define portENABLE_INTERRUPTS() \ - asm volatile ( "STMDB SP!, {R0}" ); /* Push R0. */ \ - asm volatile ( "MRS R0, CPSR" ); /* Get CPSR. */ \ - asm volatile ( "BIC R0, R0, #0xC0" ); /* Enable IRQ, FIQ. */ \ - asm volatile ( "MSR CPSR, R0" ); /* Write back modified value. */ \ - asm volatile ( "LDMIA SP!, {R0}" ) /* Pop R0. */ - -#endif /* THUMB_INTERWORK */ - -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#endif /* PORTMACRO_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/MemMang/heap_1.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/MemMang/heap_1.c deleted file mode 100644 index 7be8a31b6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/MemMang/heap_1.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - FreeRTOS V3.2.4 - Copyright (C) 2003-2005 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - -Changes between V2.5.1 and V2.5.1 - - + The memory pool has been defined within a struct to ensure correct memory - alignment on 32bit systems. - -Changes between V2.6.1 and V3.0.0 - - + An overflow check has been added to ensure the next free byte variable - does not wrap around. -*/ - - -/* - * The simplest possible implementation of pvPortMalloc(). Note that this - * implementation does NOT allow allocated memory to be freed again. - * - * See heap_2.c and heap_3.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ -#include -#include "FreeRTOS.h" -#include "task.h" - -/* Setup the correct byte alignment mask for the defined byte alignment. */ -#if portBYTE_ALIGNMENT == 4 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) -#endif - -#if portBYTE_ALIGNMENT == 2 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) -#endif - -#if portBYTE_ALIGNMENT == 1 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) -#endif - -#ifndef heapBYTE_ALIGNMENT_MASK - #error "Invalid portBYTE_ALIGNMENT definition" -#endif - -/* Allocate the memory for the heap. The struct is used to force byte -alignment without using any non-portable code. */ -static struct xRTOS_HEAP -{ - unsigned portLONG ulDummy; - unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; -} xHeap; - -static size_t xNextFreeByte = ( size_t ) 0; -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -void *pvReturn = NULL; - - /* Ensure that blocks are always aligned to the required number of bytes. */ - #if portBYTE_ALIGNMENT != 1 - if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) - { - /* Byte alignment required. */ - xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); - } - #endif - - vTaskSuspendAll(); - { - /* Check there is enough room left for the allocation. */ - if( ( ( xNextFreeByte + xWantedSize ) < configTOTAL_HEAP_SIZE ) && - ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) )/* Check for overflow. */ - { - /* Return the next free byte then increment the index past this - block. */ - pvReturn = &( xHeap.ucHeap[ xNextFreeByte ] ); - xNextFreeByte += xWantedSize; - } - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ - /* Memory cannot be freed using this scheme. See heap_2.c and heap_3.c - for alternative implementations, and the memory management pages of - http://www.FreeRTOS.org for more information. */ - ( void ) pv; -} -/*-----------------------------------------------------------*/ - -void vPortInitialiseBlocks( void ) -{ - /* Only required when static memory is not cleared. */ - xNextFreeByte = ( size_t ) 0; -} - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/MemMang/heap_2.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/MemMang/heap_2.c deleted file mode 100644 index eb581cdd5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/MemMang/heap_2.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - FreeRTOS V3.2.4 - Copyright (C) 2003-2005 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * A sample implementation of pvPortMalloc() and vPortFree() that permits - * allocated blocks to be freed, but does not combine adjacent free blocks - * into a single larger block. - * - * See heap_1.c and heap_3.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ -#include - -#include "FreeRTOS.h" -#include "task.h" - -/* Setup the correct byte alignment mask for the defined byte alignment. */ -#if portBYTE_ALIGNMENT == 4 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) -#endif - -#if portBYTE_ALIGNMENT == 2 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) -#endif - -#if portBYTE_ALIGNMENT == 1 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) -#endif - -#ifndef heapBYTE_ALIGNMENT_MASK - #error "Invalid portBYTE_ALIGNMENT definition" -#endif - -/* Allocate the memory for the heap. The struct is used to force byte -alignment without using any non-portable code. */ -static struct xRTOS_HEAP -{ - unsigned portLONG ulDummy; - unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; -} xHeap; - -/* Define the linked list structure. This is used to link free blocks in order -of their size. */ -typedef struct A_BLOCK_LINK -{ - struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */ - size_t xBlockSize; /*<< The size of the free block. */ -} xBlockLink; - - -static const unsigned portSHORT heapSTRUCT_SIZE = ( sizeof( xBlockLink ) + ( sizeof( xBlockLink ) % portBYTE_ALIGNMENT ) ); -#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) ) - -/* Create a couple of list links to mark the start and end of the list. */ -static xBlockLink xStart, xEnd; - -/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */ - -/* - * Insert a block into the list of free blocks - which is ordered by size of - * the block. Small blocks at the start of the list and large blocks at the end - * of the list. - */ -#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \ -{ \ -xBlockLink *pxIterator; \ -size_t xBlockSize; \ - \ - xBlockSize = pxBlockToInsert->xBlockSize; \ - \ - /* Iterate through the list until a block is found that has a larger size */ \ - /* than the block we are inserting. */ \ - for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \ - { \ - /* There is nothing to do here - just iterate to the correct position. */ \ - } \ - \ - /* Update the list to include the block being inserted in the correct */ \ - /* position. */ \ - pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \ - pxIterator->pxNextFreeBlock = pxBlockToInsert; \ -} -/*-----------------------------------------------------------*/ - -#define prvHeapInit() \ -{ \ -xBlockLink *pxFirstFreeBlock; \ - \ - /* xStart is used to hold a pointer to the first item in the list of free */ \ - /* blocks. The void cast is used to prevent compiler warnings. */ \ - xStart.pxNextFreeBlock = ( void * ) xHeap.ucHeap; \ - xStart.xBlockSize = ( size_t ) 0; \ - \ - /* xEnd is used to mark the end of the list of free blocks. */ \ - xEnd.xBlockSize = configTOTAL_HEAP_SIZE; \ - xEnd.pxNextFreeBlock = NULL; \ - \ - /* To start with there is a single free block that is sized to take up the \ - entire heap space. */ \ - pxFirstFreeBlock = ( void * ) xHeap.ucHeap; \ - pxFirstFreeBlock->xBlockSize = configTOTAL_HEAP_SIZE; \ - pxFirstFreeBlock->pxNextFreeBlock = &xEnd; \ -} -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -xBlockLink *pxBlock, *pxPreviousBlock, *pxNewBlockLink; -static portBASE_TYPE xHeapHasBeenInitialised = pdFALSE; -void *pvReturn = NULL; - - vTaskSuspendAll(); - { - /* If this is the first call to malloc then the heap will require - initialisation to setup the list of free blocks. */ - if( xHeapHasBeenInitialised == pdFALSE ) - { - prvHeapInit(); - xHeapHasBeenInitialised = pdTRUE; - } - - /* The wanted size is increased so it can contain a xBlockLink - structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) - { - xWantedSize += heapSTRUCT_SIZE; - - /* Ensure that blocks are always aligned to the required number of bytes. */ - if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) - { - /* Byte alignment required. */ - xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); - } - } - - if( ( xWantedSize > 0 ) && ( xWantedSize < configTOTAL_HEAP_SIZE ) ) - { - /* Blocks are stored in byte order - traverse the list from the start - (smallest) block until one of adequate size is found. */ - pxPreviousBlock = &xStart; - pxBlock = xStart.pxNextFreeBlock; - while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock ) ) - { - pxPreviousBlock = pxBlock; - pxBlock = pxBlock->pxNextFreeBlock; - } - - /* If we found the end marker then a block of adequate size was not found. */ - if( pxBlock != &xEnd ) - { - /* Return the memory space - jumping over the xBlockLink structure - at its start. */ - pvReturn = ( void * ) ( ( ( unsigned portCHAR * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE ); - - /* This block is being returned for use so must be taken our of the - list of free blocks. */ - pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; - - /* If the block is larger than required it can be split into two. */ - if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) - { - /* This block is to be split into two. Create a new block - following the number of bytes requested. The void cast is - used to prevent byte alignment warnings from the compiler. */ - pxNewBlockLink = ( void * ) ( ( ( unsigned portCHAR * ) pxBlock ) + xWantedSize ); - - /* Calculate the sizes of two blocks split from the single - block. */ - pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; - pxBlock->xBlockSize = xWantedSize; - - /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); - } - } - } - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ -unsigned portCHAR *puc = ( unsigned portCHAR * ) pv; -xBlockLink *pxLink; - - if( pv ) - { - /* The memory being freed will have an xBlockLink structure immediately - before it. */ - puc -= heapSTRUCT_SIZE; - - /* This casting is to keep the compiler from issuing warnings. */ - pxLink = ( void * ) puc; - - vTaskSuspendAll(); - { - /* Add this block to the list of free blocks. */ - prvInsertBlockIntoFreeList( ( ( xBlockLink * ) pxLink ) ); - } - xTaskResumeAll(); - } -} -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/MemMang/heap_3.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/MemMang/heap_3.c deleted file mode 100644 index cca99ed35..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/portable/MemMang/heap_3.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - FreeRTOS V3.2.4 - Copyright (C) 2003-2005 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * Implementation of pvPortMalloc() and vPortFree() that relies on the - * compilers own malloc() and free() implementations. - * - * This file can only be used if the linker is configured to to generate - * a heap memory area. - * - * See heap_2.c and heap_1.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ - -#include - -#include "FreeRTOS.h" -#include "task.h" - -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -void *pvReturn; - - vTaskSuspendAll(); - { - pvReturn = malloc( xWantedSize ); - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ - if( pv ) - { - vTaskSuspendAll(); - { - free( pv ); - } - xTaskResumeAll(); - } -} - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/queue.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/queue.c deleted file mode 100644 index cd9fa7063..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/queue.c +++ /dev/null @@ -1,645 +0,0 @@ -/* - FreeRTOS V3.2.4 - Copyright (C) 2003-2005 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.01 - - + More use of 8bit data types. - + Function name prefixes changed where the data type returned has changed. - -Changed from V2.0.0 - - + Added the queue locking mechanism and make more use of the scheduler - suspension feature to minimise the time interrupts have to be disabled - when accessing a queue. - -Changed from V2.2.0 - - + Explicit use of 'signed' qualifier on portCHAR types added. - -Changes from V3.0.0 - - + API changes as described on the FreeRTOS.org WEB site. - -*/ - -#include -#include -#include "FreeRTOS.h" -#include "task.h" -#include "list.h" - -/*----------------------------------------------------------- - * PUBLIC LIST API documented in list.h - *----------------------------------------------------------*/ - -/* Constants used with the cRxLock and cTxLock structure members. */ -#define queueUNLOCKED ( ( signed portBASE_TYPE ) -1 ) - -/* - * Definition of the queue used by the scheduler. - * Items are queued by copy, not reference. - */ -typedef struct QueueDefinition -{ - signed portCHAR *pcHead; /*< Points to the beginning of the queue storage area. */ - signed portCHAR *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */ - - signed portCHAR *pcWriteTo; /*< Points to the free next place in the storage area. */ - signed portCHAR *pcReadFrom; /*< Points to the last place that a queued item was read from. */ - - xList xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */ - xList xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */ - - unsigned portBASE_TYPE uxMessagesWaiting;/*< The number of items currently in the queue. */ - unsigned portBASE_TYPE uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */ - unsigned portBASE_TYPE uxItemSize; /*< The size of each items that the queue will hold. */ - - signed portBASE_TYPE xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ - signed portBASE_TYPE xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ -} xQUEUE; -/*-----------------------------------------------------------*/ - -/* - * Inside this file xQueueHandle is a pointer to a xQUEUE structure. - * To keep the definition private the API header file defines it as a - * pointer to void. - */ -typedef xQUEUE * xQueueHandle; - -/* - * Prototypes for public functions are included here so we don't have to - * include the API header file (as it defines xQueueHandle differently). These - * functions are documented in the API header file. - */ -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); -signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue ); -void vQueueDelete( xQueueHandle xQueue ); -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ); -signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pcBuffer, portTickType xTicksToWait ); -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pcBuffer, signed portBASE_TYPE *pxTaskWoken ); - -/* - * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not - * prevent an ISR from adding or removing items to the queue, but does prevent - * an ISR from removing tasks from the queue event lists. If an ISR finds a - * queue is locked it will instead increment the appropriate queue lock count - * to indicate that a task may require unblocking. When the queue in unlocked - * these lock counts are inspected, and the appropriate action taken. - */ -static signed portBASE_TYPE prvUnlockQueue( xQueueHandle pxQueue ); - -/* - * Uses a critical section to determine if there is any data in a queue. - * - * @return pdTRUE if the queue contains no items, otherwise pdFALSE. - */ -static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ); - -/* - * Uses a critical section to determine if there is any space in a queue. - * - * @return pdTRUE if there is no space, otherwise pdFALSE; - */ -static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ); - -/* - * Macro that copies an item into the queue. This is done by copying the item - * byte for byte, not by reference. Updates the queue state to ensure it's - * integrity after the copy. - */ -#define prvCopyQueueData( pxQueue, pvItemToQueue ) \ -{ \ - memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize ); \ - ++( pxQueue->uxMessagesWaiting ); \ - pxQueue->pcWriteTo += pxQueue->uxItemSize; \ - if( pxQueue->pcWriteTo >= pxQueue->pcTail ) \ - { \ - pxQueue->pcWriteTo = pxQueue->pcHead; \ - } \ -} -/*-----------------------------------------------------------*/ - -/* - * Macro to mark a queue as locked. Locking a queue prevents an ISR from - * accessing the queue event lists. - */ -#define prvLockQueue( pxQueue ) \ -{ \ - taskENTER_CRITICAL(); \ - ++( pxQueue->xRxLock ); \ - ++( pxQueue->xTxLock ); \ - taskEXIT_CRITICAL(); \ -} -/*-----------------------------------------------------------*/ - - -/*----------------------------------------------------------- - * PUBLIC QUEUE MANAGEMENT API documented in queue.h - *----------------------------------------------------------*/ - -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ) -{ -xQUEUE *pxNewQueue; -size_t xQueueSizeInBytes; - - /* Allocate the new queue structure. */ - if( uxQueueLength > ( unsigned portBASE_TYPE ) 0 ) - { - pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) ); - if( pxNewQueue != NULL ) - { - /* Create the list of pointers to queue items. The queue is one byte - longer than asked for to make wrap checking easier/faster. */ - xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1; - - pxNewQueue->pcHead = ( signed portCHAR * ) pvPortMalloc( xQueueSizeInBytes ); - if( pxNewQueue->pcHead != NULL ) - { - /* Initialise the queue members as described above where the - queue type is defined. */ - pxNewQueue->pcTail = pxNewQueue->pcHead + ( uxQueueLength * uxItemSize ); - pxNewQueue->uxMessagesWaiting = 0; - pxNewQueue->pcWriteTo = pxNewQueue->pcHead; - pxNewQueue->pcReadFrom = pxNewQueue->pcHead + ( ( uxQueueLength - 1 ) * uxItemSize ); - pxNewQueue->uxLength = uxQueueLength; - pxNewQueue->uxItemSize = uxItemSize; - pxNewQueue->xRxLock = queueUNLOCKED; - pxNewQueue->xTxLock = queueUNLOCKED; - - /* Likewise ensure the event queues start with the correct state. */ - vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) ); - vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) ); - - return pxNewQueue; - } - else - { - vPortFree( pxNewQueue ); - } - } - } - - /* Will only reach here if we could not allocate enough memory or no memory - was required. */ - return NULL; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* Make sure other tasks do not access the queue. */ - vTaskSuspendAll(); - - /* It is important that this is the only thread/ISR that modifies the - ready or delayed lists until xTaskResumeAll() is called. Places where - the ready/delayed lists are modified include: - - + vTaskDelay() - Nothing can call vTaskDelay as the scheduler is - suspended, vTaskDelay() cannot be called from an ISR. - + vTaskPrioritySet() - Has a critical section around the access. - + vTaskSwitchContext() - This will not get executed while the scheduler - is suspended. - + prvCheckDelayedTasks() - This will not get executed while the - scheduler is suspended. - + xTaskCreate() - Has a critical section around the access. - + vTaskResume() - Has a critical section around the access. - + xTaskResumeAll() - Has a critical section around the access. - + xTaskRemoveFromEventList - Checks to see if the scheduler is - suspended. If so then the TCB being removed from the event is - removed from the event and added to the xPendingReadyList. - */ - - /* Make sure interrupts do not access the queue event list. */ - prvLockQueue( pxQueue ); - - /* It is important that interrupts to not access the event list of the - queue being modified here. Places where the event list is modified - include: - - + xQueueSendFromISR(). This checks the lock on the queue to see if - it has access. If the queue is locked then the Tx lock count is - incremented to signify that a task waiting for data can be made ready - once the queue lock is removed. If the queue is not locked then - a task can be moved from the event list, but will not be removed - from the delayed list or placed in the ready list until the scheduler - is unlocked. - - + xQueueReceiveFromISR(). As per xQueueSendFromISR(). - */ - - /* If the queue is already full we may have to block. */ - if( prvIsQueueFull( pxQueue ) ) - { - /* The queue is full - do we want to block or just leave without - posting? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* We are going to place ourselves on the xTasksWaitingToSend event - list, and will get woken should the delay expire, or space become - available on the queue. - - As detailed above we do not require mutual exclusion on the event - list as nothing else can modify it or the ready lists while we - have the scheduler suspended and queue locked. - - It is possible that an ISR has removed data from the queue since we - checked if any was available. If this is the case then the data - will have been copied from the queue, and the queue variables - updated, but the event list will not yet have been checked to see if - anything is waiting as the queue is locked. */ - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); - - /* Force a context switch now as we are blocked. We can do - this from within a critical section as the task we are - switching to has its own context. When we return here (i.e. we - unblock) we will leave the critical section as normal. - - It is possible that an ISR has caused an event on an unrelated and - unlocked queue. If this was the case then the event list for that - queue will have been updated but the ready lists left unchanged - - instead the readied task will have been added to the pending ready - list. */ - taskENTER_CRITICAL(); - { - /* We can safely unlock the queue and scheduler here as - interrupts are disabled. We must not yield with anything - locked, but we can yield from within a critical section. - - Tasks that have been placed on the pending ready list cannot - be tasks that are waiting for events on this queue. See - in comment xTaskRemoveFromEventList(). */ - prvUnlockQueue( pxQueue ); - - /* Resuming the scheduler may cause a yield. If so then there - is no point yielding again here. */ - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - - /* Before leaving the critical section we have to ensure - exclusive access again. */ - vTaskSuspendAll(); - prvLockQueue( pxQueue ); - } - taskEXIT_CRITICAL(); - } - } - - /* When we are here it is possible that we unblocked as space became - available on the queue. It is also possible that an ISR posted to the - queue since we left the critical section, so it may be that again there - is no space. This would only happen if a task and ISR post onto the - same queue. */ - taskENTER_CRITICAL(); - { - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - /* There is room in the queue, copy the data into the queue. */ - prvCopyQueueData( pxQueue, pvItemToQueue ); - xReturn = pdPASS; - - /* Update the TxLock count so prvUnlockQueue knows to check for - tasks waiting for data to become available in the queue. */ - ++( pxQueue->xTxLock ); - } - else - { - xReturn = errQUEUE_FULL; - } - } - taskEXIT_CRITICAL(); - - /* We no longer require exclusive access to the queue. prvUnlockQueue - will remove any tasks suspended on a receive if either this function - or an ISR has posted onto the queue. */ - if( prvUnlockQueue( pxQueue ) ) - { - /* Resume the scheduler - making ready any tasks that were woken - by an event while the scheduler was locked. Resuming the - scheduler may cause a yield, in which case there is no point - yielding again here. */ - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - } - else - { - /* Resume the scheduler - making ready any tasks that were woken - by an event while the scheduler was locked. */ - xTaskResumeAll(); - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ) -{ - /* Similar to xQueueSend, except we don't block if there is no room in the - queue. Also we don't directly wake a task that was blocked on a queue - read, instead we return a flag to say whether a context switch is required - or not (i.e. has a task with a higher priority than us been woken by this - post). */ - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - prvCopyQueueData( pxQueue, pvItemToQueue ); - - /* If the queue is locked we do not alter the event list. This will - be done when the queue is unlocked later. */ - if( pxQueue->xTxLock == queueUNLOCKED ) - { - /* We only want to wake one task per ISR, so check that a task has - not already been woken. */ - if( !xTaskPreviouslyWoken ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority so record that a - context switch is required. */ - return pdTRUE; - } - } - } - } - else - { - /* Increment the lock count so the task that unlocks the queue - knows that data was posted while it was locked. */ - ++( pxQueue->xTxLock ); - } - } - - return xTaskPreviouslyWoken; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pcBuffer, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* This function is very similar to xQueueSend(). See comments within - xQueueSend() for a more detailed explanation. - - Make sure other tasks do not access the queue. */ - vTaskSuspendAll(); - - /* Make sure interrupts do not access the queue. */ - prvLockQueue( pxQueue ); - - /* If there are no messages in the queue we may have to block. */ - if( prvIsQueueEmpty( pxQueue ) ) - { - /* There are no messages in the queue, do we want to block or just - leave with nothing? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); - taskENTER_CRITICAL(); - { - prvUnlockQueue( pxQueue ); - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - - vTaskSuspendAll(); - prvLockQueue( pxQueue ); - } - taskEXIT_CRITICAL(); - } - } - - taskENTER_CRITICAL(); - { - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pcBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - /* Increment the lock count so prvUnlockQueue knows to check for - tasks waiting for space to become available on the queue. */ - ++( pxQueue->xRxLock ); - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - } - taskEXIT_CRITICAL(); - - /* We no longer require exclusive access to the queue. */ - if( prvUnlockQueue( pxQueue ) ) - { - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - } - else - { - xTaskResumeAll(); - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pcBuffer, signed portBASE_TYPE *pxTaskWoken ) -{ -signed portBASE_TYPE xReturn; - - /* We cannot block from an ISR, so check there is data available. */ - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Copy the data from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pcBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - /* If the queue is locked we will not modify the event list. Instead - we update the lock count so the task that unlocks the queue will know - that an ISR has removed data while the queue was locked. */ - if( pxQueue->xRxLock == queueUNLOCKED ) - { - /* We only want to wake one task per ISR, so check that a task has - not already been woken. */ - if( !( *pxTaskWoken ) ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - /* The task waiting has a higher priority than us so - force a context switch. */ - *pxTaskWoken = pdTRUE; - } - } - } - } - else - { - /* Increment the lock count so the task that unlocks the queue - knows that data was removed while it was locked. */ - ++( pxQueue->xRxLock ); - } - - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue ) -{ -unsigned portBASE_TYPE uxReturn; - - taskENTER_CRITICAL(); - uxReturn = pxQueue->uxMessagesWaiting; - taskEXIT_CRITICAL(); - - return uxReturn; -} -/*-----------------------------------------------------------*/ - -void vQueueDelete( xQueueHandle pxQueue ) -{ - vPortFree( pxQueue->pcHead ); - vPortFree( pxQueue ); -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvUnlockQueue( xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xYieldRequired = pdFALSE; - - /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */ - - /* The lock counts contains the number of extra data items placed or - removed from the queue while the queue was locked. When a queue is - locked items can be added or removed, but the event lists cannot be - updated. */ - taskENTER_CRITICAL(); - { - --( pxQueue->xTxLock ); - - /* See if data was added to the queue while it was locked. */ - if( pxQueue->xTxLock > queueUNLOCKED ) - { - pxQueue->xTxLock = queueUNLOCKED; - - /* Data was posted while the queue was locked. Are any tasks - blocked waiting for data to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - /* Tasks that are removed from the event list will get added to - the pending ready list as the scheduler is still suspended. */ - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority so record that a - context switch is required. */ - xYieldRequired = pdTRUE; - } - } - } - } - taskEXIT_CRITICAL(); - - /* Do the same for the Rx lock. */ - taskENTER_CRITICAL(); - { - --( pxQueue->xRxLock ); - - if( pxQueue->xRxLock > queueUNLOCKED ) - { - pxQueue->xRxLock = queueUNLOCKED; - - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - xYieldRequired = pdTRUE; - } - } - } - } - taskEXIT_CRITICAL(); - - return xYieldRequired; -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - taskENTER_CRITICAL(); - xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ); - taskEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - taskENTER_CRITICAL(); - xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength ); - taskEXIT_CRITICAL(); - - return xReturn; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/readme.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/readme.txt deleted file mode 100644 index 18da584b7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/readme.txt +++ /dev/null @@ -1,15 +0,0 @@ -Each real time kernel port consists of three files that contain the core kernel -components and are common to every port, and one or more files that are -specific to a particular microcontroller and or compiler. - -+ The FreeRTOS/Source directory contains the three files that are common to -every port. The kernel is contained within these three files. - -+ The FreeRTOS/Source/Portable directory contains the files that are specific to -a particular microcontroller and or compiler. - -+ The FreeRTOS/Source/include directory contains the real time kernel header -files. - -See the readme file in the FreeRTOS/Source/Portable directory for more -information. \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/tasks.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/tasks.c deleted file mode 100644 index 27cb7b011..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/freertos/tasks.c +++ /dev/null @@ -1,1632 +0,0 @@ -/* - FreeRTOS V3.2.4 - Copyright (C) 2003-2005 Richard Barry. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.00: - - + Call to portRESTORE_CONTEXT has been removed. The first context - switch is now performed within sPortStartScheduler(). - -Changes from V1.01: - - + More use of 8bit data types. - + Function name prefixes changed where the data type returned has changed. - + configUSE_TRACE_FACILITY is no longer defined by default. - -Changes from V1.2.0 - - + Introduced ucTopReadyPriority. This tracks the highest priority ready - queue that contains a valid TCB and thus makes the context switch - slightly faster. - - + prvAddTaskToReadyQueue() has been made a macro. - -Changes from V1.2.6 - - + Added conditional compilation directives. - + Extended API. - + Rearranged function order. - + Creating a task now causes a context switch if the task being created - has a higher priority than the calling task - assuming the kernel is - running. - + vTaskDelete() now only causes a context switch if the calling task is - the task being deleted. - -Changes from V2.0.0 - - + Allow the type of the tick count to be 16 or 32 bits. - + Introduce xPendingReadyList feature to allow the time interrupts have to - be disabled to be minimised. - + Remove the #if( INCLUDE_vTaskSuspendAll ) statements. vTaskSuspendAll() - is now always included as it is used by the scheduler itself. - -Changes from V2.1.0 - - + Bug fix - pxCurrentTCB is now initialised before the call to - prvInitializeTaskLists(). Previously pxCurrentTCB could be accessed - while null. - -Changed from V2.1.1 - - + Change to where lStackSize is declared within sTaskCreate() to prevent - compiler warnings with 8051 port. - -Changes from V2.2.0 - - + Explicit use of 'signed' qualifier on portCHAR types added. - + Changed odd calculation of initial pxTopOfStack value when - portSTACK_GROWTH < 0. - + Removed pcVersionNumber definition. - -Changes from V2.5.3 - - + cTaskResumeAll() modified to ensure it can be called prior to the task - lists being initialised. - -Changes from V2.5.5 - - + Added API function vTaskDelayUntil(). - + Added INCLUDE_vTaskDelay conditional compilation. - -Changes from V2.6.0 - - + Updated the vWriteTraceToBuffer macro to always be 4 byte aligned so it - can be used on ARM architectures. - + tskMAX_TASK_NAME_LEN definition replaced with the port specific - configMAX_TASK_NAME_LEN definition. - + Removed the call to strcpy when copying across the task name into the - TCB. - + Added ucTasksDeleted variable to prevent vTaskSuspendAll() being called - too often in the idle task. - -Changes between V3.0.0 and V2.6.1 - - + When resuming the scheduler a yield is performed if either a tick has - been missed, or a task is moved from the pending ready list into a ready - list. Previously a yield was not performed on this second condition. - + Introduced the type portBASE_TYPE. This necessitates several API - changes. - + Removed the sUsingPreemption variable. The constant defined in - portmacro.h is now used directly. - + The idle task can now include an optional hook function - and no longer - completes its time slice if other tasks with equal priority to it are - ready to run. - + See the FreeRTOS.org documentation for more information on V2.x.x to - V3.x.x modifications. - -Changes from V3.1.1 - - + Modified vTaskPrioritySet() and vTaskResume() to allow these functions to - be called while the scheduler is suspended. - + Corrected the task ordering within event lists. - -Changes from V3.2.0 - - + Added function xTaskGetCurrentTaskHandle(). -*/ - -#include -#include -#include - -#include "FreeRTOS.h" -#include "task.h" - -/* - * Macro to define the amount of stack available to the idle task. - */ -#define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE - - -/* - * Default a definitions for backwards compatibility with old - * portmacro.h files. - */ -#ifndef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 16 -#endif - -#ifndef INCLUDE_xTaskGetCurrentTaskHandle - #define INCLUDE_xTaskGetCurrentTaskHandle 0 -#endif - -#ifndef configIDLE_SHOULD_YIELD - #define configIDLE_SHOULD_YIELD 1 -#endif - -#if configMAX_TASK_NAME_LEN < 1 - #undef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 1 -#endif - - -/* - * Task control block. A task control block (TCB) is allocated to each task, - * and stores the context of the task. - */ -typedef struct tskTaskControlBlock -{ - portSTACK_TYPE *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE STRUCT. */ - portSTACK_TYPE *pxStack; /*< Points to the start of the stack. */ - unsigned portBASE_TYPE uxTCBNumber; /*< This is used for tracing the scheduler and making debugging easier only. */ - unsigned portBASE_TYPE uxPriority; /*< The priority of the task where 0 is the lowest priority. */ - xListItem xGenericListItem; /*< List item used to place the TCB in ready and blocked queues. */ - xListItem xEventListItem; /*< List item used to place the TCB in event lists. */ - signed portCHAR pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */ - unsigned portSHORT usStackDepth; /*< Total depth of the stack (when empty). This is defined as the number of variables the stack can hold, not the number of bytes. */ -} tskTCB; - -/*lint -e956 */ - -volatile tskTCB * volatile pxCurrentTCB = NULL; - -/* Lists for ready and blocked tasks. --------------------*/ - -static volatile xList pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */ -static volatile xList xDelayedTaskList1; /*< Delayed tasks. */ -static volatile xList xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */ -static volatile xList *pxDelayedTaskList; /*< Points to the delayed task list currently being used. */ -static volatile xList *pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */ -static volatile xList xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready queue when the scheduler is resumed. */ - -#if ( INCLUDE_vTaskDelete == 1 ) - - static volatile xList xTasksWaitingTermination; /*< Tasks that have been deleted - but the their memory not yet freed. */ - static volatile unsigned portBASE_TYPE uxTasksDeleted = ( unsigned portBASE_TYPE ) 0; - -#endif - -#if ( INCLUDE_vTaskSuspend == 1 ) - - static volatile xList xSuspendedTaskList; /*< Tasks that are currently suspended. */ - -#endif - -/* File private variables. --------------------------------*/ -static unsigned portBASE_TYPE uxCurrentNumberOfTasks = ( unsigned portBASE_TYPE ) 0; -static volatile portTickType xTickCount = ( portTickType ) 0; -static unsigned portBASE_TYPE uxTopUsedPriority = tskIDLE_PRIORITY; -static volatile unsigned portBASE_TYPE uxTopReadyPriority = tskIDLE_PRIORITY; -static signed portBASE_TYPE xSchedulerRunning = pdFALSE; -static volatile unsigned portBASE_TYPE uxSchedulerSuspended = ( unsigned portBASE_TYPE ) pdFALSE; -static volatile unsigned portBASE_TYPE uxMissedTicks = ( unsigned portBASE_TYPE ) 0; - -/* Debugging and trace facilities private variables and macros. ------------*/ - -/* - * The value used to fill the stack of a task when the task is created. This - * is used purely for checking the high water mark for tasks. - */ -#define tskSTACK_FILL_BYTE ( 0xa5 ) - -/* - * Macros used by vListTask to indicate which state a task is in. - */ -#define tskBLOCKED_CHAR ( ( signed portCHAR ) 'B' ) -#define tskREADY_CHAR ( ( signed portCHAR ) 'R' ) -#define tskDELETED_CHAR ( ( signed portCHAR ) 'D' ) -#define tskSUSPENDED_CHAR ( ( signed portCHAR ) 'S' ) - -/* - * Macros and private variables used by the trace facility. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - #define tskSIZE_OF_EACH_TRACE_LINE ( ( unsigned portLONG ) ( sizeof( unsigned portLONG ) + sizeof( unsigned portLONG ) ) ) - static volatile signed portCHAR * volatile pcTraceBuffer; - static signed portCHAR *pcTraceBufferStart; - static signed portCHAR *pcTraceBufferEnd; - static signed portBASE_TYPE xTracing = pdFALSE; - -#endif - -/* - * Macro that writes a trace of scheduler activity to a buffer. This trace - * shows which task is running when and is very useful as a debugging tool. - * As this macro is called each context switch it is a good idea to undefine - * it if not using the facility. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - #define vWriteTraceToBuffer() \ - { \ - if( xTracing ) \ - { \ - static unsigned portBASE_TYPE uxPreviousTask = 255; \ - \ - if( uxPreviousTask != pxCurrentTCB->uxTCBNumber ) \ - { \ - if( ( pcTraceBuffer + tskSIZE_OF_EACH_TRACE_LINE ) < pcTraceBufferEnd ) \ - { \ - uxPreviousTask = pxCurrentTCB->uxTCBNumber; \ - *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) xTickCount; \ - pcTraceBuffer += sizeof( unsigned portLONG ); \ - *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) uxPreviousTask; \ - pcTraceBuffer += sizeof( unsigned portLONG ); \ - } \ - else \ - { \ - xTracing = pdFALSE; \ - } \ - } \ - } \ - } - -#else - - #define vWriteTraceToBuffer() - -#endif - - -/* - * Place the task represented by pxTCB into the appropriate ready queue for - * the task. It is inserted at the end of the list. One quirk of this is - * that if the task being inserted is at the same priority as the currently - * executing task, then it will only be rescheduled after the currently - * executing task has been rescheduled. - */ -#define prvAddTaskToReadyQueue( pxTCB ) \ -{ \ - listSET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ), 0 ); \ - if( pxTCB->uxPriority > uxTopReadyPriority ) \ - { \ - uxTopReadyPriority = pxTCB->uxPriority; \ - } \ - vListInsertEnd( ( xList * ) &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ); \ -} - - -/* - * Macro that looks at the list of tasks that are currently delayed to see if - * any require waking. - * - * Tasks are stored in the queue in the order of their wake time - meaning - * once one tasks has been found whose timer has not expired we need not look - * any further down the list. - */ -#define prvCheckDelayedTasks() \ -{ \ -register tskTCB *pxTCB; \ - \ - while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ) ) != NULL ) \ - { \ - if( xTickCount < listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) ) ) \ - { \ - break; \ - } \ - vListRemove( &( pxTCB->xGenericListItem ) ); \ - /* Is the task waiting on an event also? */ \ - if( pxTCB->xEventListItem.pvContainer ) \ - { \ - vListRemove( &( pxTCB->xEventListItem ) ); \ - } \ - prvAddTaskToReadyQueue( pxTCB ); \ - } \ -} - -/* - * Several functions take an xTaskHandle parameter that can optionally be NULL, - * where NULL is used to indicate that the handle of the currently executing - * task should be used in place of the parameter. This macro simply checks to - * see if the parameter is NULL and returns a pointer to the appropriate TCB. - */ -#define prvGetTCBFromHandle( pxHandle ) ( ( pxHandle == NULL ) ? ( tskTCB * ) pxCurrentTCB : ( tskTCB * ) pxHandle ) - - -/* File private functions. --------------------------------*/ - -/* - * Utility to ready a TCB for a given task. Mainly just copies the parameters - * into the TCB structure. - */ -static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ); - -/* - * Utility to ready all the lists used by the scheduler. This is called - * automatically upon the creation of the first task. - */ -static void prvInitialiseTaskLists( void ); - -/* - * The idle task, which as all tasks is implemented as a never ending loop. - * The idle task is automatically created and added to the ready lists upon - * creation of the first user task. - * - * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific - * language extensions. The equivalent prototype for this function is: - * - * void prvIdleTask( void *pvParameters ); - * - */ -static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ); - -/* - * Utility to free all memory allocated by the scheduler to hold a TCB, - * including the stack pointed to by the TCB. - * - * This does not free memory allocated by the task itself (i.e. memory - * allocated by calls to pvPortMalloc from within the tasks application code). - */ -#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) - static void prvDeleteTCB( tskTCB *pxTCB ); -#endif - -/* - * Used only by the idle task. This checks to see if anything has been placed - * in the list of tasks waiting to be deleted. If so the task is cleaned up - * and its TCB deleted. - */ -static void prvCheckTasksWaitingTermination( void ); - -/* - * Allocates memory from the heap for a TCB and associated stack. Checks the - * allocation was successful. - */ -static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ); - -/* - * Called from vTaskList. vListTasks details all the tasks currently under - * control of the scheduler. The tasks may be in one of a number of lists. - * prvListTaskWithinSingleList accepts a list and details the tasks from - * within just that list. - * - * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM - * NORMAL APPLICATION CODE. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ); - -#endif - -/* - * When a task is created, the stack of the task is filled with a known value. - * This function determines the 'high water mark' of the task stack by - * determining how much of the stack remains at the original preset value. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte ); - -#endif - -/*lint +e956 */ - - - - - -/*----------------------------------------------------------- - * TASK CREATION API documented in task.h - *----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask ) -{ -signed portBASE_TYPE xReturn; -tskTCB * pxNewTCB; -static unsigned portBASE_TYPE uxTaskNumber = 0; /*lint !e956 Static is deliberate - this is guarded before use. */ - - /* Allocate the memory required by the TCB and stack for the new task. - checking that the allocation was successful. */ - pxNewTCB = prvAllocateTCBAndStack( usStackDepth ); - - if( pxNewTCB != NULL ) - { - portSTACK_TYPE *pxTopOfStack; - - /* Setup the newly allocated TCB with the initial state of the task. */ - prvInitialiseTCBVariables( pxNewTCB, usStackDepth, pcName, uxPriority ); - - /* Calculate the top of stack address. This depends on whether the - stack grows from high memory to low (as per the 80x86) or visa versa. - portSTACK_GROWTH is used to make the result positive or negative as - required by the port. */ - #if portSTACK_GROWTH < 0 - { - pxTopOfStack = pxNewTCB->pxStack + ( pxNewTCB->usStackDepth - 1 ); - } - #else - { - pxTopOfStack = pxNewTCB->pxStack; - } - #endif - - /* Initialize the TCB stack to look as if the task was already running, - but had been interrupted by the scheduler. The return address is set - to the start of the task function. Once the stack has been initialised - the top of stack variable is updated. */ - pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pvTaskCode, pvParameters ); - - /* We are going to manipulate the task queues to add this task to a - ready list, so must make sure no interrupts occur. */ - portENTER_CRITICAL(); - { - uxCurrentNumberOfTasks++; - if( uxCurrentNumberOfTasks == ( unsigned portBASE_TYPE ) 1 ) - { - /* As this is the first task it must also be the current task. */ - pxCurrentTCB = ( volatile tskTCB * volatile ) pxNewTCB; - - /* This is the first task to be created so do the preliminary - initialisation required. We will not recover if this call - fails, but we will report the failure. */ - prvInitialiseTaskLists(); - } - else - { - /* If the scheduler is not already running, make this task the - current task if it is the highest priority task to be created - so far. */ - if( xSchedulerRunning == pdFALSE ) - { - if( pxCurrentTCB->uxPriority <= uxPriority ) - { - pxCurrentTCB = ( volatile tskTCB * volatile ) pxNewTCB; - } - } - } - - /* Remember the top priority to make context switching faster. Use - the priority in pxNewTCB as this has been capped to a valid value. */ - if( pxNewTCB->uxPriority > uxTopUsedPriority ) - { - uxTopUsedPriority = pxNewTCB->uxPriority; - } - - /* Add a counter into the TCB for tracing only. */ - pxNewTCB->uxTCBNumber = uxTaskNumber; - uxTaskNumber++; - - prvAddTaskToReadyQueue( pxNewTCB ); - - xReturn = pdPASS; - } - portEXIT_CRITICAL(); - } - else - { - xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - } - - if( xReturn == pdPASS ) - { - if( ( void * ) pxCreatedTask != NULL ) - { - /* Pass the TCB out - in an anonymous way. The calling function/ - task can use this as a handle to delete the task later if - required.*/ - *pxCreatedTask = ( xTaskHandle ) pxNewTCB; - } - - if( xSchedulerRunning != pdFALSE ) - { - /* If the created task is of a higher priority than the current task - then it should run now. */ - if( pxCurrentTCB->uxPriority < uxPriority ) - { - taskYIELD(); - } - } - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelete == 1 ) - - void vTaskDelete( xTaskHandle pxTaskToDelete ) - { - tskTCB *pxTCB; - - taskENTER_CRITICAL(); - { - /* If null is passed in here then we are deleting ourselves. */ - pxTCB = prvGetTCBFromHandle( pxTaskToDelete ); - - /* Remove task from the ready list and place in the termination list. - This will stop the task from be scheduled. The idle task will check - the termination list and free up any memory allocated by the - scheduler for the TCB and stack. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Is the task waiting on an event also? */ - if( pxTCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - } - - vListInsertEnd( ( xList * ) &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) ); - - /* Increment the ucTasksDeleted variable so the idle task knows - there is a task that has been deleted and that it should therefore - check the xTasksWaitingTermination list. */ - ++uxTasksDeleted; - } - taskEXIT_CRITICAL(); - - /* Force a reschedule if we have just deleted the current task. */ - if( ( void * ) pxTaskToDelete == NULL ) - { - taskYIELD(); - } - } - -#endif - - - - - - -/*----------------------------------------------------------- - * TASK CONTROL API documented in task.h - *----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelayUntil == 1 ) - void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement ) - { - portTickType xTimeToWake; - portBASE_TYPE xAlreadyYielded, xShouldDelay = pdFALSE; - - vTaskSuspendAll(); - { - /* Generate the tick time at which the task wants to wake. */ - xTimeToWake = *pxPreviousWakeTime + xTimeIncrement; - - if( xTickCount < *pxPreviousWakeTime ) - { - /* The tick count has overflowed since this function was - lasted called. In this case the only time we should ever - actually delay is if the wake time has also overflowed, - and the wake time is greater than the tick time. When this - is the case it is as if neither time had overflowed. */ - if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xTickCount ) ) - { - xShouldDelay = pdTRUE; - } - } - else - { - /* The tick time has not overflowed. In this case we will - delay if either the wake time has overflowed, and/or the - tick time is less than the wake time. */ - if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xTickCount ) ) - { - xShouldDelay = pdTRUE; - } - } - - /* Update the wake time ready for the next call. */ - *pxPreviousWakeTime = xTimeToWake; - - if( xShouldDelay ) - { - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - } - xAlreadyYielded = xTaskResumeAll(); - - /* Force a reschedule if xTaskResumeAll has not already done so, we may - have put ourselves to sleep. */ - if( !xAlreadyYielded ) - { - taskYIELD(); - } - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelay == 1 ) - void vTaskDelay( portTickType xTicksToDelay ) - { - portTickType xTimeToWake; - signed portBASE_TYPE xAlreadyYielded = pdFALSE; - - /* A delay time of zero just forces a reschedule. */ - if( xTicksToDelay > ( portTickType ) 0 ) - { - vTaskSuspendAll(); - { - /* A task that is removed from the event list while the - scheduler is suspended will not get placed in the ready - list or removed from the blocked list until the scheduler - is resumed. - - This task cannot be in an event list as it is the currently - executing task. */ - - /* Calculate the time to wake - this may overflow but this is - not a problem. */ - xTimeToWake = xTickCount + xTicksToDelay; - - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - xAlreadyYielded = xTaskResumeAll(); - } - - /* Force a reschedule if xTaskResumeAll has not already done so, we may - have put ourselves to sleep. */ - if( !xAlreadyYielded ) - { - taskYIELD(); - } - } -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_uxTaskPriorityGet == 1 ) - - unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ) - { - tskTCB *pxTCB; - unsigned portBASE_TYPE uxReturn; - - taskENTER_CRITICAL(); - { - /* If null is passed in here then we are changing the - priority of the calling function. */ - pxTCB = prvGetTCBFromHandle( pxTask ); - uxReturn = pxTCB->uxPriority; - } - taskEXIT_CRITICAL(); - - return uxReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskPrioritySet == 1 ) - - void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ) - { - tskTCB *pxTCB; - unsigned portBASE_TYPE uxCurrentPriority; - - /* Ensure the new priority is valid. */ - if( uxNewPriority >= configMAX_PRIORITIES ) - { - uxNewPriority = configMAX_PRIORITIES - 1; - } - - taskENTER_CRITICAL(); - { - /* If null is passed in here then we are changing the - priority of the calling function. */ - pxTCB = prvGetTCBFromHandle( pxTask ); - uxCurrentPriority = pxTCB->uxPriority; - - if( uxCurrentPriority != uxNewPriority ) - { - pxTCB->uxPriority = uxNewPriority; - - /* If the task is in the blocked or suspended list we need do - nothing more than change it's priority variable. However, if - the task is in a ready list it needs to be removed and placed - in the queue appropriate to its new priority. */ - if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxCurrentPriority ] ), &( pxTCB->xGenericListItem ) ) ) - { - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - /* The task is currently in its ready list - remove before adding - it to it's new ready list. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - } - else - { - /* We cannot access the delayed or ready lists, so will hold this - task pending until the scheduler is resumed. */ - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); - } - } - } - } - taskEXIT_CRITICAL(); - - /* The priority change may have readied a task of higher - priority than the calling task. */ - taskYIELD(); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - void vTaskSuspend( xTaskHandle pxTaskToSuspend ) - { - tskTCB *pxTCB; - - taskENTER_CRITICAL(); - { - /* If null is passed in here then we are suspending ourselves. */ - pxTCB = prvGetTCBFromHandle( pxTaskToSuspend ); - - /* Remove task from the ready/delayed list and place in the suspended list. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Is the task waiting on an event also? */ - if( pxTCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - } - - vListInsertEnd( ( xList * ) &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ); - } - taskEXIT_CRITICAL(); - - /* We may have just suspended the current task. */ - if( ( void * ) pxTaskToSuspend == NULL ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - void vTaskResume( xTaskHandle pxTaskToResume ) - { - tskTCB *pxTCB; - portBASE_TYPE xYieldRequired; - - /* Remove the task from whichever list it is currently in, and place - it in the ready list. */ - pxTCB = ( tskTCB * ) pxTaskToResume; - - /* The parameter cannot be NULL as it is impossible to resume the - currently executing task. */ - if( pxTCB != NULL ) - { - taskENTER_CRITICAL(); - { - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - xYieldRequired = ( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ); - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - } - else - { - /* We cannot access the delayed or ready lists, so will hold this - task pending until the scheduler is resumed. */ - xYieldRequired = pdFALSE; - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); - } - } - taskEXIT_CRITICAL(); - - /* We may have just resumed a higher priority task. */ - if( xYieldRequired ) - { - /* This yield may not cause the task just resumed to run, but - will leave the lists in the correct state for the next yield. */ - taskYIELD(); - } - } - } - -#endif - - - - - -/*----------------------------------------------------------- - * PUBLIC SCHEDULER CONTROL documented in task.h - *----------------------------------------------------------*/ - - -void vTaskStartScheduler( void ) -{ -portBASE_TYPE xReturn; - - /* Check a task has been created. */ - if( pxCurrentTCB != NULL ) - { - /* Add the idle task at the lowest priority. */ - xReturn = xTaskCreate( prvIdleTask, ( const signed portCHAR * const ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); - - if( xReturn == pdPASS ) - { - /* Interrupts are turned off here, to ensure a tick does not occur - before or during the call to xPortStartScheduler(). The stacks of - the created tasks contain a status word with interrupts switched on - so interrupts will automatically get re-enabled when the first task - starts to run. - - STEPPING THROUGH HERE USING A DEBUGGER CAN CAUSE BIG PROBLEMS IF THE - DEBUGGER ALLOWS INTERRUPTS TO BE PROCESSED. */ - portDISABLE_INTERRUPTS(); - - xSchedulerRunning = pdTRUE; - xTickCount = ( portTickType ) 0; - - /* Setting up the timer tick is hardware specific and thus in the - portable interface. */ - if( xPortStartScheduler() ) - { - /* Should not reach here as if the scheduler is running the - function will not return. */ - } - else - { - /* Should only reach here if a task calls xTaskEndScheduler(). */ - } - } - } -} -/*-----------------------------------------------------------*/ - -void vTaskEndScheduler( void ) -{ - /* Stop the scheduler interrupts and call the portable scheduler end - routine so the original ISRs can be restored if necessary. The port - layer must ensure interrupts enable bit is left in the correct state. */ - portDISABLE_INTERRUPTS(); - xSchedulerRunning = pdFALSE; - vPortEndScheduler(); -} -/*----------------------------------------------------------*/ - -void vTaskSuspendAll( void ) -{ - portENTER_CRITICAL(); - ++uxSchedulerSuspended; - portEXIT_CRITICAL(); -} -/*----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskResumeAll( void ) -{ -register tskTCB *pxTCB; -signed portBASE_TYPE xAlreadyYielded = pdFALSE; - - /* It is possible that an ISR caused a task to be removed from an event - list while the scheduler was suspended. If this was the case then the - removed task will have been added to the xPendingReadyList. Once the - scheduler has been resumed it is safe to move all the pending ready - tasks from this list into their appropriate ready list. */ - portENTER_CRITICAL(); - { - --uxSchedulerSuspended; - - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - if( uxCurrentNumberOfTasks > ( unsigned portBASE_TYPE ) 0 ) - { - portBASE_TYPE xYieldRequired = pdFALSE; - - /* Move any readied tasks from the pending list into the - appropriate ready list. */ - while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xPendingReadyList ) ) ) != NULL ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - - /* If we have moved a task that has a priority higher than - the current task then we should yield. */ - if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) - { - xYieldRequired = pdTRUE; - } - } - - /* If any ticks occurred while the scheduler was suspended then - they should be processed now. This ensures the tick count does not - slip, and that any delayed tasks are resumed at the correct time. */ - if( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) - { - while( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) - { - vTaskIncrementTick(); - --uxMissedTicks; - } - - /* As we have processed some ticks it is appropriate to yield - to ensure the highest priority task that is ready to run is - the task actually running. */ - xYieldRequired = pdTRUE; - } - - if( xYieldRequired == pdTRUE ) - { - xAlreadyYielded = pdTRUE; - taskYIELD(); - } - } - } - } - portEXIT_CRITICAL(); - - return xAlreadyYielded; -} - - - - - - -/*----------------------------------------------------------- - * PUBLIC TASK UTILITIES documented in task.h - *----------------------------------------------------------*/ - - - -portTickType xTaskGetTickCount( void ) -{ -portTickType xTicks; - - /* Critical section required if running on a 16 bit processor. */ - taskENTER_CRITICAL(); - { - xTicks = xTickCount; - } - taskEXIT_CRITICAL(); - - return xTicks; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ) -{ -unsigned portBASE_TYPE uxNumberOfTasks; - - taskENTER_CRITICAL(); - uxNumberOfTasks = uxCurrentNumberOfTasks; - taskEXIT_CRITICAL(); - - return uxNumberOfTasks; -} -/*-----------------------------------------------------------*/ - -#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_vTaskDelete == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - void vTaskList( signed portCHAR *pcWriteBuffer ) - { - unsigned portBASE_TYPE uxQueue; - - /* This is a VERY costly function that should be used for debug only. - It leaves interrupts disabled for a LONG time. */ - - taskENTER_CRITICAL(); - { - /* Run through all the lists that could potentially contain a TCB and - report the task name, state and stack high water mark. */ - - pcWriteBuffer[ 0 ] = ( signed portCHAR ) 0x00; - strcat( ( portCHAR * ) pcWriteBuffer, ( const portCHAR * ) "\r\n" ); - - uxQueue = uxTopUsedPriority + 1; - - do - { - uxQueue--; - - if( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), tskREADY_CHAR ); - } - }while( uxQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); - - if( !listLIST_IS_EMPTY( pxDelayedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, tskBLOCKED_CHAR ); - } - - if( !listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, tskBLOCKED_CHAR ); - } - - if( !listLIST_IS_EMPTY( &xTasksWaitingTermination ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xTasksWaitingTermination, tskDELETED_CHAR ); - } - - if( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xSuspendedTaskList, tskSUSPENDED_CHAR ); - } - } - taskEXIT_CRITICAL(); - } - -#endif -/*----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ) - { - portENTER_CRITICAL(); - { - pcTraceBuffer = ( volatile signed portCHAR * volatile )pcBuffer; - pcTraceBufferStart = pcBuffer; - pcTraceBufferEnd = pcBuffer + ( ulBufferSize - tskSIZE_OF_EACH_TRACE_LINE ); - xTracing = pdTRUE; - } - portEXIT_CRITICAL(); - } - -#endif -/*----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - unsigned portLONG ulTaskEndTrace( void ) - { - unsigned portLONG ulBufferLength; - - portENTER_CRITICAL(); - xTracing = pdFALSE; - portEXIT_CRITICAL(); - - ulBufferLength = ( unsigned portLONG ) ( pcTraceBuffer - pcTraceBufferStart ); - - return ulBufferLength; - } - -#endif - - - -/*----------------------------------------------------------- - * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES - * documented in task.h - *----------------------------------------------------------*/ - - -inline void vTaskIncrementTick( void ) -{ - /* Called by the portable layer each time a tick interrupt occurs. - Increments the tick then checks to see if the new tick value will cause any - tasks to be unblocked. */ - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - ++xTickCount; - if( xTickCount == ( portTickType ) 0 ) - { - volatile xList *pxTemp; - - /* Tick count has overflowed so we need to swap the delay lists. If there are - any items in pxDelayedTaskList here then there is an error! */ - pxTemp = pxDelayedTaskList; - pxDelayedTaskList = pxOverflowDelayedTaskList; - pxOverflowDelayedTaskList = pxTemp; - } - - /* See if this tick has made a timeout expire. */ - prvCheckDelayedTasks(); - } - else - { - ++uxMissedTicks; - } -} -/*-----------------------------------------------------------*/ - -#if ( ( INCLUDE_vTaskCleanUpResources == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - void vTaskCleanUpResources( void ) - { - unsigned portSHORT usQueue; - volatile tskTCB *pxTCB; - - usQueue = ( unsigned portSHORT ) uxTopUsedPriority + ( unsigned portSHORT ) 1; - - /* Remove any TCB's from the ready queues. */ - do - { - usQueue--; - - while( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ usQueue ] ) ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &( pxReadyTasksLists[ usQueue ] ) ) - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - }while( usQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); - - /* Remove any TCB's from the delayed queue. */ - while( !listLIST_IS_EMPTY( &xDelayedTaskList1 ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList1 ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - /* Remove any TCB's from the overflow delayed queue. */ - while( !listLIST_IS_EMPTY( &xDelayedTaskList2 ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList2 ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - while( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xSuspendedTaskList ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - while( !listLIST_IS_EMPTY( &xPendingReadyList ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xPendingReadyList ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - } - -#endif -/*-----------------------------------------------------------*/ - -inline void vTaskSwitchContext( void ) -{ - if( uxSchedulerSuspended != ( unsigned portBASE_TYPE ) pdFALSE ) - { - /* The scheduler is currently suspended - do not allow a context - switch. */ - return; - } - - /* Find the highest priority queue that contains ready tasks. */ - while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) ) - { - --uxTopReadyPriority; - } - - /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the tasks of the - same priority get an equal share of the processor time. */ - listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) ); - vWriteTraceToBuffer(); -} -/*-----------------------------------------------------------*/ - -void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait ) -{ -portTickType xTimeToWake; - - /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE - SCHEDULER SUSPENDED. */ - - /* Place the event list item of the TCB in the appropriate event list. - This is placed in the list in priority order so the highest priority task - is the first to be woken by the event. */ - vListInsert( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) ); - - /* Calculate the time at which the task should be woken if the event does - not occur. This may overflow but this doesn't matter. */ - xTimeToWake = xTickCount + xTicksToWait; - - /* We must remove ourselves from the ready list before adding ourselves - to the blocked list as the same list item is used for both lists. We have - exclusive access to the ready lists as the scheduler is locked. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList ) -{ -tskTCB *pxUnblockedTCB; -portBASE_TYPE xReturn; - - /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE - SCHEDULER SUSPENDED. It can also be called from within an ISR. */ - - /* The event list is sorted in priority order, so we can remove the - first in the list, remove the TCB from the delayed list, and add - it to the ready list. - - If an event is for a queue that is locked then this function will never - get called - the lock count on the queue will get modified instead. This - means we can always expect exclusive access to the event list here. */ - pxUnblockedTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); - vListRemove( &( pxUnblockedTCB->xEventListItem ) ); - - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - vListRemove( &( pxUnblockedTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxUnblockedTCB ); - } - else - { - /* We cannot access the delayed or ready lists, so will hold this - task pending until the scheduler is resumed. */ - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); - } - - if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) - { - /* Return true if the task removed from the event list has - a higher priority than the calling task. This allows - the calling task to know if it should force a context - switch now. */ - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} - - - - - -/* - * ----------------------------------------------------------- - * The Idle task. - * ---------------------------------------------------------- - * - * The portTASK_FUNCTION() macro is used to allow port/compiler specific - * language extensions. The equivalent prototype for this function is: - * - * void prvIdleTask( void *pvParameters ); - * - */ -static portTASK_FUNCTION( prvIdleTask, pvParameters ) -{ - /* Stop warnings. */ - ( void ) pvParameters; - - for( ;; ) - { - /* See if any tasks have been deleted. */ - prvCheckTasksWaitingTermination(); - - #if ( configUSE_PREEMPTION == 0 ) - { - /* If we are not using preemption we keep forcing a task switch to - see if any other task has become available. If we are using - preemption we don't need to do this as any task becoming available - will automatically get the processor anyway. */ - taskYIELD(); - } - #endif - - #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) - { - /* When using preemption tasks of equal priority will be - timesliced. If a task that is sharing the idle priority is ready - to run then the idle task should yield before the end of the - timeslice. - - A critical region is not required here as we are just reading from - the list, and an occasional incorrect value will not matter. If - the ready list at the idle priority contains more than one task - then a task other than the idle task is ready to execute. */ - if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( unsigned portBASE_TYPE ) 1 ) - { - taskYIELD(); - } - } - #endif - - #if ( configUSE_IDLE_HOOK == 1 ) - { - extern void vApplicationIdleHook( void ); - - /* Call the user defined function from within the idle task. This - allows the application designer to add background functionality - without the overhead of a separate task. - NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, - CALL A FUNCTION THAT MIGHT BLOCK. */ - vApplicationIdleHook(); - } - #endif - } -} /*lint !e715 pvParameters is not accessed but all task functions require the same prototype. */ - - - - - - - -/*----------------------------------------------------------- - * File private functions documented at the top of the file. - *----------------------------------------------------------*/ - - - -static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ) -{ - pxTCB->usStackDepth = usStackDepth; - - /* Store the function name in the TCB. */ - strncpy( ( char * ) pxTCB->pcTaskName, ( const char * ) pcName, ( unsigned portSHORT ) configMAX_TASK_NAME_LEN ); - pxTCB->pcTaskName[ ( unsigned portSHORT ) configMAX_TASK_NAME_LEN - ( unsigned portSHORT ) 1 ] = '\0'; - - /* This is used as an array index so must ensure it's not too large. */ - if( uxPriority >= configMAX_PRIORITIES ) - { - uxPriority = configMAX_PRIORITIES - 1; - } - pxTCB->uxPriority = uxPriority; - - vListInitialiseItem( &( pxTCB->xGenericListItem ) ); - vListInitialiseItem( &( pxTCB->xEventListItem ) ); - - /* Set the pxTCB as a link back from the xListItem. This is so we can get - back to the containing TCB from a generic item in a list. */ - listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB ); - - /* Event lists are always in priority order. */ - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); - listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB ); -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseTaskLists( void ) -{ -unsigned portBASE_TYPE uxPriority; - - for( uxPriority = 0; uxPriority < configMAX_PRIORITIES; uxPriority++ ) - { - vListInitialise( ( xList * ) &( pxReadyTasksLists[ uxPriority ] ) ); - } - - vListInitialise( ( xList * ) &xDelayedTaskList1 ); - vListInitialise( ( xList * ) &xDelayedTaskList2 ); - vListInitialise( ( xList * ) &xPendingReadyList ); - - #if ( INCLUDE_vTaskDelete == 1 ) - { - vListInitialise( ( xList * ) &xTasksWaitingTermination ); - } - #endif - - #if ( INCLUDE_vTaskSuspend == 1 ) - { - vListInitialise( ( xList * ) &xSuspendedTaskList ); - } - #endif - - /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList - using list2. */ - pxDelayedTaskList = &xDelayedTaskList1; - pxOverflowDelayedTaskList = &xDelayedTaskList2; -} -/*-----------------------------------------------------------*/ - -static void prvCheckTasksWaitingTermination( void ) -{ - #if ( INCLUDE_vTaskDelete == 1 ) - { - portBASE_TYPE xListIsEmpty; - - /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called - too often in the idle task. */ - if( uxTasksDeleted > ( unsigned portBASE_TYPE ) 0 ) - { - vTaskSuspendAll(); - xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination ); - xTaskResumeAll(); - - if( !xListIsEmpty ) - { - tskTCB *pxTCB; - - portENTER_CRITICAL(); - { - pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xTasksWaitingTermination ) ); - vListRemove( &( pxTCB->xGenericListItem ) ); - --uxCurrentNumberOfTasks; - --uxTasksDeleted; - } - portEXIT_CRITICAL(); - - prvDeleteTCB( pxTCB ); - } - } - } - #endif -} -/*-----------------------------------------------------------*/ - -static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ) -{ -tskTCB *pxNewTCB; - - /* Allocate space for the TCB. Where the memory comes from depends on - the implementation of the port malloc function. */ - pxNewTCB = ( tskTCB * ) pvPortMalloc( sizeof( tskTCB ) ); - - if( pxNewTCB != NULL ) - { - /* Allocate space for the stack used by the task being created. - The base of the stack memory stored in the TCB so the task can - be deleted later if required. */ - pxNewTCB->pxStack = ( portSTACK_TYPE * ) pvPortMalloc( ( ( size_t )usStackDepth ) * sizeof( portSTACK_TYPE ) ); - - if( pxNewTCB->pxStack == NULL ) - { - /* Could not allocate the stack. Delete the allocated TCB. */ - vPortFree( pxNewTCB ); - pxNewTCB = NULL; - } - else - { - /* Just to help debugging. */ - memset( pxNewTCB->pxStack, tskSTACK_FILL_BYTE, usStackDepth * sizeof( portSTACK_TYPE ) ); - } - } - - return pxNewTCB; -} -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ) - { - volatile tskTCB *pxNextTCB, *pxFirstTCB; - static portCHAR pcStatusString[ 50 ]; - unsigned portSHORT usStackRemaining; - - /* Write the details of all the TCB's in pxList into the buffer. */ - listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); - do - { - listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); - usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned portCHAR * ) pxNextTCB->pxStack ); - sprintf( pcStatusString, ( portCHAR * ) "%s\t\t%c\t%u\t%u\t%u\r\n", pxNextTCB->pcTaskName, cStatus, ( unsigned int ) pxNextTCB->uxPriority, usStackRemaining, ( unsigned int ) pxNextTCB->uxTCBNumber ); - strcat( ( portCHAR * ) pcWriteBuffer, ( portCHAR * ) pcStatusString ); - - } while( pxNextTCB != pxFirstTCB ); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte ) - { - register unsigned portSHORT usCount = 0; - - while( *pucStackByte == tskSTACK_FILL_BYTE ) - { - pucStackByte -= portSTACK_GROWTH; - usCount++; - } - - usCount /= sizeof( portSTACK_TYPE ); - - return usCount; - } -#endif -/*-----------------------------------------------------------*/ - - - -#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) - - static void prvDeleteTCB( tskTCB *pxTCB ) - { - /* Free up the memory allocated by the scheduler for the task. It is up to - the task to free any memory allocated at the application level. */ - vPortFree( pxTCB->pxStack ); - vPortFree( pxTCB ); - } - -#endif - - -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) - - xTaskHandle xTaskGetCurrentTaskHandle( void ) - { - xTaskHandle xReturn; - - portENTER_CRITICAL(); - { - xReturn = ( xTaskHandle ) pxCurrentTCB; - } - portEXIT_CRITICAL(); - - return xReturn; - } - -#endif - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/71x_lib.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/71x_lib.c deleted file mode 100644 index a161fc2d6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/71x_lib.c +++ /dev/null @@ -1,158 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_lib.c -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Peripherals pointers initialization -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#define EXT - -#include "71x_map.h" - -#ifdef LIBDEBUG - -extern u32 T0TIMI_Addr; - -/******************************************************************************* -* Function Name : debug -* Description : Initialize the pointers to peripherals -* Input : none -* Output : none -* Return : none -*******************************************************************************/ -void libdebug(void) -{ - #ifdef _ADC12 - ADC12 = (ADC12_TypeDef *)ADC12_BASE; - #endif - - #ifdef _APB - #ifdef _APB1 - APB1 = (APB_TypeDef *)(APB1_BASE+0x10); - #endif - #ifdef _APB2 - APB2 = (APB_TypeDef *)(APB2_BASE+0x10); - #endif - #endif - - #ifdef _BSPI - #ifdef _BSPI0 - BSPI0 = (BSPI_TypeDef *)BSPI0_BASE; - #endif - #ifdef _BSPI1 - BSPI1 = (BSPI_TypeDef *)BSPI1_BASE; - #endif - #endif - - #ifdef _CAN - CAN = (CAN_TypeDef *)CAN_BASE; - #endif - - #ifdef _EIC - EIC = (EIC_TypeDef *)EIC_BASE; - #endif - - #ifdef _EMI - EMI = (EMI_TypeDef *)EMI_BASE; - #endif - - #ifdef _FLASH - FLASHR = (FLASHR_TypeDef *)FLASHR_BASE; - FLASHPR = (FLASHPR_TypeDef *)FLASHPR_BASE; - #endif - - #ifdef _GPIO - #ifdef _GPIO0 - GPIO0 = (GPIO_TypeDef *)GPIO0_BASE; - #endif - #ifdef _GPIO1 - GPIO1 = (GPIO_TypeDef *)GPIO1_BASE; - #endif - #ifdef _GPIO2 - GPIO2 = (GPIO_TypeDef *)GPIO2_BASE; - #endif - #endif - - #ifdef _I2C - #ifdef _I2C0 - I2C0 = (I2C_TypeDef *)I2C0_BASE; - #endif - #ifdef _I2C1 - I2C1 = (I2C_TypeDef *)I2C1_BASE; - #endif - #endif - - #ifdef _PCU - PCU = (PCU_TypeDef *)PCU_BASE; - #endif - - #ifdef _RCCU - RCCU = (RCCU_TypeDef *)RCCU_BASE; - #endif - - #ifdef _RTC - RTC = (RTC_TypeDef *)RTC_BASE; - #endif - - #ifdef _TIM - #ifdef _TIM0 - TIM0 = (TIM_TypeDef *)TIM0_BASE; - #endif - #ifdef _TIM1 - TIM1 = (TIM_TypeDef *)TIM1_BASE; - #endif - #ifdef _TIM2 - TIM2 = (TIM_TypeDef *)TIM2_BASE; - #endif - #ifdef _TIM3 - TIM3 = (TIM_TypeDef *)TIM3_BASE; - #endif - #endif - - #ifdef _UART - #ifdef _UART0 - UART0 = (UART_TypeDef *)UART0_BASE; - #endif - #ifdef _UART1 - UART1 = (UART_TypeDef *)UART1_BASE; - #endif - #ifdef _UART2 - UART2 = (UART_TypeDef *)UART2_BASE; - #endif - #ifdef _UART3 - UART3 = (UART_TypeDef *)UART3_BASE; - #endif - #endif - - #ifdef _USB - USB = (USB_TypeDef *)USB_BASE; - #endif - - #ifdef _WDG - WDG = (WDG_TypeDef *)WDG_BASE; - #endif - - #ifdef _XTI - XTI = (XTI_TypeDef *)XTI_BASE; - #endif - - #ifdef _IRQVectors - IRQVectors = (IRQVectors_TypeDef *)&T0TIMI_Addr; - #endif -} - -#endif /* LIBDEBUG */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/adc12.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/adc12.c deleted file mode 100644 index a300fa35a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/adc12.c +++ /dev/null @@ -1,79 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : adc12.c -* Author : MCD Application Team -* Date First Issued : 07/31/2003 -* Description : Code sources of ADC12 functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#include "adc12.h" - -/******************************************************************************* -* Function Name : ADC12_Init -* Description : Initialize the ADC -* Input : None. -* Return : None. -*******************************************************************************/ -void ADC12_Init(void) -{ - //Initiate ADC12 registers to their reset values - ADC12->CSR = 0x00; - ADC12->CPR = 0x01; -} - -/******************************************************************************* -* Function Name : ADC12_PrescalerConfig -* Description : Configure the prescaler -* Input : None. -* Return : None. -*******************************************************************************/ -void ADC12_PrescalerConfig(u32 Adc12_clk) -{ - //Update the Prescaler Register - ADC12->CPR = (vu16) (RCCU_FrequencyValue(RCCU_PCLK)/(Adc12_clk*512*8)); -} - -/******************************************************************************* -* Function Name : ADC12_ITConfig -* Description : enable or disable the interrupt -* Input : status=ENABLE=>enable interrupt -* status=DISABLE=>disable interrupt -* Return : None -*******************************************************************************/ -void ADC12_ITConfig(FunctionalState NewState) -{ - if (NewState == ENABLE) - { - // Test the conversion mode - if (ADC12->CSR & 0x0040) - { - // Set interrupt bit equivalent to the channel selected - switch (ADC12->CSR & 0x30) - { - case 0x00 : ADC12->CSR |= ADC12_IT0_Mask; break; - case 0x10 : ADC12->CSR |= ADC12_IT1_Mask; break; - case 0x20 : ADC12->CSR |= ADC12_IT2_Mask; break; - case 0x30 : ADC12->CSR |= ADC12_IT3_Mask; break; - } - } - else - // Set all interrupt bits in case of round robin mode - ADC12->CSR |= ADC12_IT_Mask; - } - else - // Clear all interrupt bits - ADC12->CSR &= ~ADC12_IT_Mask; -} -/*********************(c) 2003 STMicroelectronics********************* END OF FILE **/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/apb.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/apb.c deleted file mode 100644 index ec171401c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/apb.c +++ /dev/null @@ -1,24 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : apb.c -* Author : MCD Application Team -* Date First Issued : 05/30/2003 -* Description : This file provides all the APB software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "apb.h" - - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/bspi.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/bspi.c deleted file mode 100644 index acbe34181..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/bspi.c +++ /dev/null @@ -1,171 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : bspi.c -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : This file provides all the BSPI software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "bspi.h" - -/******************************************************************************* -* Function Name : BSPI_Init -* Description : Initializes BSPI peripheral control and registers to their default reset values. -* Input : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Output : BSPI peripheral registers and BSPI global variables are initialized. -* Return : None. -*******************************************************************************/ -void BSPI_Init(BSPI_TypeDef *BSPIx) -{ - BSPIx->CSR2 = 0x41; - BSPIx->CSR1 = 0x00; - BSPIx->CLK = 0x06; -} - -/******************************************************************************* -* Function Name : BSPI_TrItSrc. -* Description : Configures the transmit interrupt source. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : TrItSrc: specifies the transmit interrupt source. -* : Refer to the section Transmit Interrupt Sources for more details on the -* : allowed values of this parameter. -* Output : TIE bit in BSPCSR2 register. -* Return : None. -*******************************************************************************/ -void BSPI_TrItSrc(BSPI_TypeDef *BSPIx, BSPI_TR_IT_SRCS TrItSrc) -{ - switch (TrItSrc) - { - case BSPI_TR_DIS: - BSPIx->CSR2 &= ~0xC000; - break; - case BSPI_TR_FE: - BSPIx->CSR2 &= ~0x8000; - BSPIx->CSR2 |= 0x4000; - break; - case BSPI_TR_UFL: - BSPIx->CSR2 &= ~0x4000; - BSPIx->CSR2 |= 0x8000; - break; - case BSPI_TR_FF: - BSPIx->CSR2 |= 0xC000; - break; - } -} - -/******************************************************************************* -* Function Name : BSPI_RcItSrc. -* Description : Configures the receive interrupt source. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : RcItSrc: specifies the source for the receive interrupt. -* : Refer to the section Receive Interrupt Sources for more details on the -* : allowed values of this parameter. -* Output : RIE bit in BSPCSR1 is register. -* Return : None. -*******************************************************************************/ -void BSPI_RcItSrc(BSPI_TypeDef *BSPIx, BSPI_RC_IR_SRCS RcItSrc) -{ - switch (RcItSrc) - { - case BSPI_RC_DIS: - BSPIx->CSR1 &= ~0x000C; - break; - case BSPI_RC_FNE: - BSPIx->CSR1 &= ~0x0008; - BSPIx->CSR1 |= 0x0004; - break; - case BSPI_RC_FF: - BSPIx->CSR1 |= 0x000C; - break; - } -} - -/******************************************************************************* -* Function Name : BSPI_TrFifoDepth -* Description : Configures BSPI transmission FIFO number of words. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI. -* Input 2 : TDepth:specifies the depth of the transmit FIFO. -* Output : TFE bit in BSPCSR2 register. -* Return : None. -*******************************************************************************/ -void BSPI_TrFifoDepth(BSPI_TypeDef *BSPIx, u8 TDepth) -{ - if (TDepth > 0 && TDepth < 11) - { - TDepth--; - BSPIx->CSR2 &= (TDepth*0x400) | ~0x3C00; - BSPIx->CSR2 |= TDepth*0x400; - } - else BSPIx->CSR2 &= ~0x3C00; -} - -/******************************************************************************* -* Function Name : BSPI_RcFifoDepth -* Description : Configures BSPI reception FIFO number of words. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : RDepth:specifies the depth of the receive FIFO. -* Output : RFE bits [3:0] in BSPCSR1 register. -* Return : None. -*******************************************************************************/ -void BSPI_RcFifoDepth(BSPI_TypeDef *BSPIx, u8 RDepth) -{ - if (RDepth > 0 && RDepth < 11) - { - RDepth--; - BSPIx->CSR1 &= (RDepth*0x1000) | ~0xF000; - BSPIx->CSR1 |= RDepth*0x1000; - } - else BSPIx->CSR1 &= ~0xF000; -} - -/******************************************************************************* -* Function Name : BSPI_BufferSend. -* Description : Transmits data from a buffer. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : PtrToBuffer is an u8 pointer to the first word of the buffer to be transmitted. -* Input 3 : NbOfWords parameter indicates the number of words saved in the buffer to be sent. -* Output : None. -* Return : None. -*******************************************************************************/ -void BSPI_BufferSend(BSPI_TypeDef *BSPIx, u8 *PtrToBuffer, u8 NbOfWords) -{ - vu8 SendWord = 0; - while (SendWord < NbOfWords) - { - BSPI_WordSend(BSPIx, *(PtrToBuffer+SendWord)); - SendWord++; - } -} - -/******************************************************************************* -* Function Name : BSPI_BufferReceive. -* Description : Receives number of data words and stores them in user defined area. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : PtrToBuffer is an u8 pointer to the first word of the defined area to save the received buffer. -* Input 3 : NbOfWords parameter indicates the number of words to be received in the buffer. -* Output : None. -* Return : None. -*******************************************************************************/ -void BSPI_BufferReceive(BSPI_TypeDef *BSPIx, u8 *PtrToBuffer, u8 NbOfWords) -{ - vu16 ReceiveWord = 0; - while (ReceiveWord < NbOfWords) - { - *(PtrToBuffer+ReceiveWord) = BSPI_WordReceive(BSPIx); - ReceiveWord++; - } -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/can.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/can.c deleted file mode 100644 index 48d491c83..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/can.c +++ /dev/null @@ -1,541 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : can.c -* Author : MCD Application Team -* Date First Issued : 10/27/2003 -* Description : This file contains all the functions prototypes for the -* CAN bus software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "can.h" -#include "xti.h" -#include "pcu.h" - -// macro to format the timing register value from the timing parameters -#define CAN_TIMING(tseg1, tseg2, sjw, brp) (((tseg2-1) & 0x07) << 12) | (((tseg1-1) & 0x0F) << 8) | (((sjw-1) & 0x03) << 6) | ((brp-1) & 0x3F) - -// array of pre-defined timing parameters for standard bitrates -u16 CanTimings[] = { // value bitrate NTQ TSEG1 TSEG2 SJW BRP - CAN_TIMING(11, 4, 4, 5), // 0x3AC4 100 kbit/s 16 11 4 4 5 - CAN_TIMING(11, 4, 4, 4), // 0x3AC3 125 kbit/s 16 11 4 4 4 - CAN_TIMING( 4, 3, 3, 4), // 0x2383 250 kbit/s 8 4 3 3 4 - CAN_TIMING(13, 2, 1, 1), // 0x1C00 500 kbit/s 16 13 2 1 1 - CAN_TIMING( 4, 3, 1, 1), // 0x2300 1 Mbit/s 8 4 3 1 1 -}; - -/******************************************************************************* -* Function Name : CAN_SetBitrate -* Description : Setup a standard CAN bitrate -* Input 1 : one of the CAN_BITRATE_xxx defines -* Output : None -* Return : None -* Note : CAN must be in initialization mode -*******************************************************************************/ -void CAN_SetBitrate(u32 bitrate) -{ - CAN->BTR = CanTimings[bitrate]; // write the predefined timing value - CAN->BRPR = 0; // clear the Extended Baud Rate Prescaler -} - -/******************************************************************************* -* Function Name : CAN_SetTiming -* Description : Setup the CAN timing with specific parameters -* Input 1 : Time Segment before the sample point position, from 1 to 16 -* Input 2 : Time Segment after the sample point position, from 1 to 8 -* Input 3 : Synchronisation Jump Width, from 1 to 4 -* Input 4 : Baud Rate Prescaler, from 1 to 1024 -* Output : None -* Return : None -* Note : CAN must be in initialization mode -*******************************************************************************/ -void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp) -{ - CAN->BTR = CAN_TIMING(tseg1, tseg2, sjw, brp); - CAN->BRPR = ((brp-1) >> 6) & 0x0F; -} - -/******************************************************************************* -* Function Name : CAN_SleepRequest -* Description : Request the CAN cell to enter sleep mode -* Input 1 : CAN_WAKEUP_ON_EXT or CAN_WAKEUP_ON_CAN -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SleepRequest(u32 WakeupMode) -{ - // Wakeup Line 6 is linked to CAN RX pin (port 1.11) - // Wakeup Line 2 is linked to external pin (port 2.8) - u32 WakeupLine = (WakeupMode == CAN_WAKEUP_ON_CAN ? XTI_Line6 : XTI_Line2); - - CAN_WaitEndOfTx(); - - XTI_Init(); - - // Configure the Wakeup Line mode, select Falling edge (transition to dominant state) - XTI_LineModeConfig(WakeupLine, XTI_FallingEdge); - - // Enable Wake-Up interrupt - XTI_LineConfig(WakeupLine, ENABLE); - - // Enable Wake-Up mode with interrupt - XTI_ModeConfig(XTI_WakeUpInterrupt, ENABLE); - - XTI_PendingBitClear(XTI_InterruptLineValue()); - - // Enter STOP mode (resume execution from here) - PCU_LPMEnter(PCU_STOP); -} - -/******************************************************************************* -* Function Name : CAN_GetFreeIF -* Description : Search the first free message interface, starting from 0 -* Input : None -* Output : None -* Return : A free message interface number (0 or 1) if found, else 2 -*******************************************************************************/ -static u32 CAN_GetFreeIF(void) -{ - if ((CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) == 0) - return 0; - else if ((CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) == 0) - return 1; - else return 2; -} - -/******************************************************************************* -* Macro Name : xxx_ID_MSK, xxx_ID_ARB -* Description : Form the Mask and Arbitration registers value to filter a range -* of identifiers or a fixed identifier, for standard and extended IDs -*******************************************************************************/ -#define RANGE_ID_MSK(range_start, range_end) (~((range_end) - (range_start))) -#define RANGE_ID_ARB(range_start, range_end) ((range_start) & (range_end)) - -#define FIXED_ID_MSK(id) RANGE_ID_MSK((id), (id)) -#define FIXED_ID_ARB(id) RANGE_ID_ARB((id), (id)) - -#define STD_RANGE_ID_MSK(range_start, range_end) ((u16)((RANGE_ID_MSK((range_start), (range_end)) & 0x7FF) << 2)) -#define STD_RANGE_ID_ARB(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) << 2)) - -#define STD_FIXED_ID_MSK(id) ((u16)((FIXED_ID_MSK(id) & 0x7FF) << 2)) -#define STD_FIXED_ID_ARB(id) ((u16)(FIXED_ID_ARB(id) << 2)) - -#define EXT_RANGE_ID_MSK_L(range_start, range_end) ((u16)(RANGE_ID_MSK((range_start), (range_end)) >> 11)) -#define EXT_RANGE_ID_MSK_H(range_start, range_end) ((u16)(STD_RANGE_ID_MSK((range_start), (range_end)) | ((RANGE_ID_MSK((range_start), (range_end)) >> 27) & 0x03))) -#define EXT_RANGE_ID_ARB_L(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) >> 11)) -#define EXT_RANGE_ID_ARB_H(range_start, range_end) ((u16)(STD_RANGE_ID_ARB((range_start), (range_end)) | ((RANGE_ID_ARB((range_start), (range_end)) >> 27) & 0x03))) - -#define EXT_FIXED_ID_MSK_L(id) ((u16)(FIXED_ID_MSK(id) >> 11)) -#define EXT_FIXED_ID_MSK_H(id) ((u16)(STD_FIXED_ID_MSK(id) | ((FIXED_ID_MSK(id) >> 27) & 0x03))) -#define EXT_FIXED_ID_ARB_L(id) ((u16)(FIXED_ID_ARB(id) >> 11)) -#define EXT_FIXED_ID_ARB_H(id) ((u16)(STD_FIXED_ID_ARB(id) | ((FIXED_ID_ARB(id) >> 27) & 0x03))) - -/******************************************************************************* -* Function Name : CAN_SetUnusedMsgObj -* Description : Configure the message object as unused -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetUnusedMsgObj(u32 msgobj) -{ - u32 msg_if; - while ((msg_if = CAN_GetFreeIF()) == 2); - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].M2R = 0; - - CAN->sMsgObj[msg_if].A1R = 0; - CAN->sMsgObj[msg_if].A2R = 0; - - CAN->sMsgObj[msg_if].MCR = 0; - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_SetTxMsgObj -* Description : Configure the message object as TX -* Input 1 : message object number, from 0 to 31 -* Input 2 : CAN_STD_ID or CAN_EXT_ID -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetTxMsgObj(u32 msgobj, u32 idType) -{ - u32 msg_if; - while ((msg_if = CAN_GetFreeIF()) == 2); - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].A1R = 0; - - if (idType == CAN_STD_ID) - { - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR; - } - else - { - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR | CAN_M2R_MXTD; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR | CAN_A2R_XTD; - } - - CAN->sMsgObj[msg_if].MCR = CAN_MCR_TXIE | CAN_MCR_EOB; - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_SetRxMsgObj -* Description : Configure the message object as RX -* Input 1 : message object number, from 0 to 31 -* Input 2 : CAN_STD_ID or CAN_EXT_ID -* Input 3 : low part of the identifier range used for acceptance filtering -* Input 4 : high part of the identifier range used for acceptance filtering -* Input 5 : TRUE for a single receive object or a FIFO receive object that -* is the last one of the FIFO -* FALSE for a FIFO receive object that is not the last one -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast) -{ - u32 msg_if; - while ((msg_if = CAN_GetFreeIF()) == 2); - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if (idType == CAN_STD_ID) - { - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].M2R = STD_RANGE_ID_MSK(idLow, idHigh); - - CAN->sMsgObj[msg_if].A1R = 0; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | STD_RANGE_ID_ARB(idLow, idHigh); - } - else - { - CAN->sMsgObj[msg_if].M1R = EXT_RANGE_ID_MSK_L(idLow, idHigh); - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MXTD | EXT_RANGE_ID_MSK_H(idLow, idHigh); - - CAN->sMsgObj[msg_if].A1R = EXT_RANGE_ID_ARB_L(idLow, idHigh); - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_XTD | EXT_RANGE_ID_ARB_H(idLow, idHigh); - } - - CAN->sMsgObj[msg_if].MCR = CAN_MCR_RXIE | CAN_MCR_UMASK | (singleOrFifoLast ? CAN_MCR_EOB : 0); - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_InvalidateAllMsgObj -* Description : Configure all the message objects as unused -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_InvalidateAllMsgObj(void) -{ - u32 i; - for (i = 0; i < 32; i++) - CAN_SetUnusedMsgObj(i); -} - -/******************************************************************************* -* Function Name : CAN_Init -* Description : Initialize the CAN cell and set the bitrate -* Input 1 : any binary value formed from the CAN_CTL_xxx defines -* Input 2 : one of the CAN_BITRATE_xxx defines -* Output : None -* Return : None -*******************************************************************************/ -void CAN_Init(u8 mask, u32 bitrate) -{ - CAN_EnterInitMode(CAN_CR_CCE | mask); - CAN_SetBitrate(bitrate); - CAN_LeaveInitMode(); - CAN_LeaveTestMode(); -} - -/******************************************************************************* -* Function Name : CAN_ReleaseMessage -* Description : Release the message object -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -*******************************************************************************/ -void CAN_ReleaseMessage(u32 msgobj) -{ - u32 i; - while ((i = CAN_GetFreeIF()) == 2); - - CAN->sMsgObj[i].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQST; - CAN->sMsgObj[i].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_SendMessage -* Description : Start transmission of a message -* Input 1 : message object number, from 0 to 31 -* Input 2 : pointer to the message structure containing data to transmit -* Output : None -* Return : 1 if transmission was OK, else 0 -*******************************************************************************/ -u32 CAN_SendMessage(u32 msgobj, canmsg* pCanMsg) -{ - while (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY); - -// if (CAN->sMsgObj[0].COMR & CAN_CRQ_BUSY) -// return 0; // message interface 0 not free - - CAN->SR &= ~CAN_SR_TXOK; - - // read the Arbitration and Message Control - CAN->sMsgObj[0].CMR = CAN_CMR_ARB | CAN_CMR_CONTROL; - - CAN->sMsgObj[0].CRR = 1 + msgobj; - - while (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY); - - // update the contents needed for transmission - CAN->sMsgObj[0].CMR = CAN_CMR_WRRD - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if ((CAN->sMsgObj[0].A2R & CAN_A2R_XTD) == 0) - { - // standard ID - CAN->sMsgObj[0].A1R = 0; - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); - } - else - { - // extended ID - CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); - } - - CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFEF0) | CAN_MCR_NEWDAT | CAN_MCR_TXRQST | pCanMsg->Dlc; - - CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; - CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; - CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; - CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; - - CAN->sMsgObj[0].CRR = 1 + msgobj; - - return 1; -} - -/******************************************************************************* -* Function Name : CAN_ReceiveMessage -* Description : Get the message, if received -* Input 1 : message object number, from 0 to 31 -* Input 2 : if TRUE, the message object is released when getting the data -* if FALSE, the message object is not released -* Input 3 : pointer to the message structure where received data is stored -* Output : None -* Return : 1 if reception was OK, else 0 (no message pending) -*******************************************************************************/ -u32 CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg) -{ - if (!CAN_IsMessageWaiting(msgobj)) - return 0; - - CAN->SR &= ~CAN_SR_RXOK; - - // read the message contents - CAN->sMsgObj[1].CMR = CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_CLRINTPND - | (release ? CAN_CMR_TXRQST : 0) - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[1].CRR = 1 + msgobj; - - while (CAN->sMsgObj[1].CRR & CAN_CRR_BUSY); - - if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) - { - // standard ID - pCanMsg->IdType = CAN_STD_ID; - pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; - } - else - { - // extended ID - pCanMsg->IdType = CAN_EXT_ID; - pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF) | ((u32)CAN->sMsgObj[1].A1R << 11) | (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); - } - - pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; - - pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; - pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); - pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; - pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); - pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; - pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); - pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; - pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); - - return 1; -} - -/******************************************************************************* -* Function Name : CAN_WaitEndOfTx -* Description : Wait until current transmission is finished -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_WaitEndOfTx(void) -{ - while ((CAN->SR & CAN_SR_TXOK) == 0); - CAN->SR &= ~CAN_SR_TXOK; -} - -/******************************************************************************* -* Function Name : CAN_BasicSendMessage -* Description : Start transmission of a message in BASIC mode -* Input 1 : pointer to the message structure containing data to transmit -* Output : None -* Return : 1 if transmission was OK, else 0 -* Note : CAN must be in BASIC mode -*******************************************************************************/ -u32 CAN_BasicSendMessage(canmsg* pCanMsg) -{ - // clear NewDat bit in IF2 to detect next reception - CAN->sMsgObj[1].MCR &= ~CAN_MCR_NEWDAT; - - CAN->SR &= ~CAN_SR_TXOK; - - CAN->sMsgObj[0].CMR = CAN_CMR_WRRD - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if (pCanMsg->IdType == CAN_STD_ID) - { - // standard ID - CAN->sMsgObj[0].A1R = 0; - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); - } - else - { - // extended ID - CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); - } - - CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFCF0) | pCanMsg->Dlc; - - CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; - CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; - CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; - CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; - - // request transmission - CAN->sMsgObj[0].CRR = CAN_CRR_BUSY | (1 + 0); - - return 1; -} - -/******************************************************************************* -* Function Name : CAN_BasicReceiveMessage -* Description : Get the message in BASIC mode, if received -* Input 1 : pointer to the message structure where received data is stored -* Output : None -* Return : 1 if reception was OK, else 0 (no message pending) -* Note : CAN must be in BASIC mode -*******************************************************************************/ -u32 CAN_BasicReceiveMessage(canmsg* pCanMsg) -{ - if ((CAN->sMsgObj[1].MCR & CAN_MCR_NEWDAT) == 0) - return 0; - - CAN->SR &= ~CAN_SR_RXOK; - - CAN->sMsgObj[1].CMR = CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) - { - // standard ID - pCanMsg->IdType = CAN_STD_ID; - pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; - } - else - { - // extended ID - pCanMsg->IdType = CAN_EXT_ID; - pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF) | ((u32)CAN->sMsgObj[1].A1R << 11) | (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); - } - - pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; - - pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; - pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); - pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; - pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); - pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; - pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); - pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; - pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); - - return 1; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/eic.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/eic.c deleted file mode 100644 index 8bc053dfd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/eic.c +++ /dev/null @@ -1,67 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : eic.c -* Author : MCD Application Team -* Date First Issued : 06/25/2003 -* Description : This file provides all the EIC software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "eic.h" - -/******************************************************************************* -* Function Name : EIC_Init -* Description : Initialise the EIC using the load PC instruction -* (PC = PC +offset) -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void EIC_Init(void) -{ - extern u32 T0TIMI_Addr; - u8 bCounter; - u32 dOffset=((u32)&T0TIMI_Addr); - EIC->ICR = 0x00000000; // Disable FIQ and IRQ interrupts - EIC->IER = 0x00000000; // Disable all channels interrupts - EIC->IPR = 0xFFFFFFFF; // Clear all pending bits - EIC->FIR = 0x0000000C; // Disable all FIQ channels interrupts and clear FIQ - // channels pending bits - EIC->CIPR = 0x00000000; // Ste the current priority level to zero - EIC->IVR = 0xE59F0000; // IVR = high half of load PC instruction - dOffset = (dOffset+0x00007E0)<<16; - for(bCounter=0; bCounter<32; bCounter++) // Initialize SIRn registers - { - EIC->SIR[bCounter] = dOffset|0xF0000000; - dOffset += 0x00000004 << 16; - } -} - -/******************************************************************************* -* Function Name : EIC_CurrentPriorityLevelConfig -* Description : Change the current priority level of the srved IRQ routine -* Input 1 : New priority -* Output : None -* Return : None -*******************************************************************************/ -void EIC_CurrentPriorityLevelConfig(u8 NewPriorityLevel) -{ - u32 dVal; - dVal = EIC->ICR; // Save ICR content - EIC->ICR &= ~0x0001; // Disable IRQ interrupts. - EIC->CIPR = NewPriorityLevel; // Change the current priority - EIC->ICR = dVal; // Restore ICR content -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/emi.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/emi.c deleted file mode 100644 index caf2a73e1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/emi.c +++ /dev/null @@ -1,24 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : emi.c -* Author : MCD Application Team -* Date First Issued : 08/08/2003 -* Description : This file provides all the EMI software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "emi.h" - - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/flash.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/flash.c deleted file mode 100644 index 9e28cf3ae..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/flash.c +++ /dev/null @@ -1,354 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : flash.c -* Author : MCD Application Team -* Date First Issued : 07/28/2003 -* Description : This file provides all the Flash software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "flash.h" - - u32 D0_temp; - - -/******************************************************************************* -* Function Name : FLASH_Init -* Description : Initialise the Flash -* Input : None -* Return : None -*******************************************************************************/ -void FLASH_Init(void) -{ -// Reset Flash Control Registers - FLASHR->CR0 = 0x00000000; - FLASHR->CR1 = 0x00000000; -// Reset Flash Data Registers - FLASHR->DR0 = 0xFFFFFFFF; - FLASHR->DR1 = 0xFFFFFFFF; -// Reset Flash Error Register - FLASHR->ER = 0x00000000; -} - -/******************************************************************************* -* Function Name : FLASH_WordWrite -* Description : Writes a Word to the Flash -* Input 1 : Address of the Destination -* Input 2 : Word To program -* Return : None -*******************************************************************************/ -void FLASH_WordWrite(u32 XtargetAdd, u32 Xdata) -{ - FLASH_WaitForLastTask(); - // set the Word Programming bit 'WPG' in the CR0 Reg - FLASHR->CR0 |= FLASH_WPG_Mask; - // Load the destination address in AR - FLASHR->AR = XtargetAdd; - // Load DATA to be programmed in DR0 - FLASHR->DR0 = Xdata; - // Set the Write Mode Start bit 'WMS' in the CR0 Reg to Start Write Operation - FLASHR->CR0 |= FLASH_WMS_Mask; - // Wait until the write operation is completed - FLASH_WaitForLastTask(); -} - -/******************************************************************************* -* Function Name : FLASH_DWordWrite -* Description : Writes Double Word to the Flash -* Input 1 : Address of the Destination -* Input 2 : Word 1 To program -* Input 3 : Word 2 To program -* Return : None -*******************************************************************************/ -void FLASH_DWordWrite(u32 XtargetAdd, u32 Xdata0, u32 Xdata1) -{ - - FLASH_WaitForLastTask(); - // set the Double Word Programming bit 'DWPG' in the CR0 Reg - FLASHR->CR0 |= FLASH_DWPG_Mask; - // Load the destination address in AR - FLASHR->AR = XtargetAdd; - // Load DATA0 in DR0 Reg - FLASHR->DR0 = Xdata0; - // Load DATA1 in DR1 Reg - FLASHR->DR1 = Xdata1; - // Set the Write Mode Start bit 'WMS' in the CR0 Reg to Start Write Operation - FLASHR->CR0 |= FLASH_WMS_Mask; - // Wait until the write operation is completed - FLASH_WaitForLastTask(); -} - - -/******************************************************************************* -* Function Name : FLASH_SectorErase -* Description : Erases a Flash sector -* Input 1 : Sectors to be Erased -* Return : None -*******************************************************************************/ -void FLASH_SectorErase(u32 Xsectors) -{ - FLASH_WaitForLastTask(); - // Set the Sector Erase flag 'SER' in the FCRO reg - FLASHR->CR0 |= FLASH_SER_Mask; - // Select the Sectors to be erased in the CR1 register - FLASHR->CR1 |= Xsectors; - // Set the Write Mode Start bit 'WMS' in the CR0 Reg to Start Erase Operation - FLASHR->CR0 |= FLASH_WMS_Mask; - // Wait until the erase operation is completed - FLASH_WaitForLastTask(); -} -/******************************************************************************* -* Function Name : FLASH_Suspend -* Description : Suspends the current program or erase operation -* Input 1 : None -* Return : Flash CR0 register -*******************************************************************************/ -u32 FLASH_Suspend(void) -{ - u32 temp; - /* Save the CR0 Contetnt */ - temp = FLASHR->CR0; - /* Set The suspend Bit 'SUSP' in the CR0 register */ - FLASHR->CR0 |= FLASH_SUSP_Mask; - /* Wait until the flash controller acknowlegs the suspend of the current - operation */ - FLASH_WaitForLastTask(); - return temp; -} -/******************************************************************************* -* Function Name : FLASH_Resume -* Description : Resume a Suspended program or erase operation -* Input 1 : The operation to be resumed -* Return : None -*******************************************************************************/ -void FLASH_Resume(u32 FLASH_LastOperation) -{ - // Clear The suspend Bit 'SUSP' in the FRC0 register - FLASHR->CR0 &= ~FLASH_SUSP_Mask; - // Resume last operation - FLASHR->CR0 = FLASH_LastOperation & 0x7FFFFFFF; - // Set write mode bit - FLASHR->CR0 |= FLASH_WMS_Mask; -} - -/******************************************************************************* -* Function Name : FLASH_WordRead -* Description : Read a single word of the flash -* Input 1 : Source Address -* Return : Word -*******************************************************************************/ -u32 FLASH_WordRead(u32 FLASH_SourceAdd) -{ - FLASH_WaitForLastTask(); - // Reads the data from the specified Address - return *(u32 *)(FLASH_SourceAdd + 0x40000000); -} -/******************************************************************************* -* Function Name : FLASH_WritePrConfig -* Description : Configures The Write Protection Bits -* Input 1 : Flash Bank -* Input 2 : Enable or disable Protection -* Return : None -*******************************************************************************/ -void FLASH_WritePrConfig(u32 Xsectors, FunctionalState NewState) -{ - FLASH_WaitForLastTask(); - - if (NewState == ENABLE) - { - // Set the Set protection Bit - FLASHR->CR0 |= FLASH_SPR_Mask; - // Set the Register Address - FLASHR->AR = 0x4010DFB0; - // Data To be Programmed to the Protection Register - FLASHR->DR0 = ~Xsectors; - // Set the WMS bit to Start the Sequence - FLASHR->CR0 |= FLASH_WMS_Mask; - } - else - { - // Set the Set protection Bit - FLASHR->CR0 |= FLASH_SPR_Mask; - // Set the Register Address - FLASHR->AR = 0x4010DFB0; - // Data To be Programmed to the Protection Register - FLASHR->DR0 = FLASHPR->NVWPAR|Xsectors; - // Set the WMS bit to Start the Sequence - FLASHR->CR0 |= FLASH_WMS_Mask; - } -} - -/******************************************************************************* -* Function Name : FLASH_PermanantDebugPrConfig -* Description : Configures The Debug Protection Bits -* Input 1 : ENABLE or DISABLE -* Return : Word -*******************************************************************************/ -void FLASH_PermanantDebugPrConfig(FunctionalState NewState) -{ - u16 ProtectionLevel = FLASH_ProtectionLevel(); - - - if (NewState == ENABLE) - { - // If the First Protection Reset the DBGP bit - if(!ProtectionLevel) - { - // Set the Set protection Bit - FLASHR->CR0 |= FLASH_SPR_Mask; - // Set the Register Address - FLASHR->AR = 0x4010DFB8; - // Data To be Programmed to the Protection Register - FLASHR->DR0 = ~2; - // Set the WMS bit to Start the Sequence - FLASHR->CR0 |= FLASH_WMS_Mask; - } - else - { - // Set the Set protection Bit - FLASHR->CR0 |= FLASH_SPR_Mask; - // Set the Register Address - FLASHR->AR = 0x4010DFBC; - // Data To be Programmed to the Protection Register - D0_temp=~(1<<(15+ProtectionLevel)); - FLASHR->DR0 =D0_temp; - // Set the WMS bit to Start the Sequence - FLASHR->CR0 |= FLASH_WMS_Mask; - } - - } - else if(ProtectionLevel) - { - // Set the Set protection Bit - FLASHR->CR0 |= FLASH_SPR_Mask; - // Set the Register Address - FLASHR->AR = 0x4010DFBC; - // Data To be Programmed to the Protection Register - FLASHR->DR0 =~(1<<(ProtectionLevel-1)); - // Set the WMS bit to Start the Sequence - FLASHR->CR0 |= FLASH_WMS_Mask; - } - -} - -/******************************************************************************* -* Function Name : FLASH_FlagStatus -* Description : Returns the NewState of Flash flags -* Input 1 : Flash Flag -* Return : flagstate -*******************************************************************************/ -FlagStatus FLASH_FlagStatus(flashflags Xflag) -{ - FlagStatus TmpResult; - u8 TmpReg; - u8 TmpPos; - // get the Register Index - TmpReg = (Xflag & FLASH_Reg_Mask) >> 5; - // get the Flag Index - TmpPos = (Xflag & FLASH_Flag_Mask); - - switch(TmpReg) - { - case 0 : // CR0 - { - // Returns the status of the CR0[TmpPos] flag - TmpResult = (FLASHR->CR0 & (1<CR1 & (1<ER & (1<> 5; - TmpPos = (Xflag & FLASH_Flag_Mask); - - switch(TmpReg) - { - case 0 : // CR0 - { - // Clears the status of the CR0[TmpPos] flag - FLASHR->CR0 &= ~(1<CR1 &= ~(1<ER &= ~(1<NVAPR0&2) - TmpBitIndex=0; - else - TmpBitIndex=1; - - ProtectionRegs=~(FLASHPR->NVAPR1>>16); - while (((ProtectionRegs) != 0) && (TmpBitIndex < 16)) - { - ProtectionRegs = ProtectionRegs >> 1 ; - TmpBitIndex++; - } - return TmpBitIndex; -} -/******************************************************************************* -* Function Name : Wait For Last Task -* Description : Waits for the end of last task on a Flash Bank -* Input 1 : None. -* Return : None -*******************************************************************************/ -void FLASH_WaitForLastTask(void) -{ - while (FLASHR->CR0&0x16); -} - -/*******************(C)COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/gpio.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/gpio.c deleted file mode 100644 index 588d1f285..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/gpio.c +++ /dev/null @@ -1,115 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : gpio.c -* Author : MCD Application Team -* Date First Issued : 06/08/2003 -* Description : This file provides all the GPIO software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "gpio.h" - -/******************************************************************************* -* Function Name : GPIO_Config -* Description : Configure the GPIO port pins -* Input 1 : GPIOx (x can be 0,1 or 2) the desired port -* Input 2 : Port_Pins : pins placements -* Input 3 : Pins Mode -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_Config (GPIO_TypeDef *GPIOx, u16 Port_Pins, GpioPinMode_TypeDef GPIO_Mode) -{ - switch (GPIO_Mode) - { - case GPIO_HI_AIN_TRI: - GPIOx->PC0&=~Port_Pins; - GPIOx->PC1&=~Port_Pins; - GPIOx->PC2&=~Port_Pins; - break; - - case GPIO_IN_TRI_TTL: - GPIOx->PC0|=Port_Pins; - GPIOx->PC1&=~Port_Pins; - GPIOx->PC2&=~Port_Pins; - break; - - case GPIO_IN_TRI_CMOS: - GPIOx->PC0&=~Port_Pins; - GPIOx->PC1|=Port_Pins; - GPIOx->PC2&=~Port_Pins; - break; - - case GPIO_IPUPD_WP: - GPIOx->PC0|=Port_Pins; - GPIOx->PC1|=Port_Pins; - GPIOx->PC2&=~Port_Pins; - break; - - case GPIO_OUT_OD: - GPIOx->PC0&=~Port_Pins; - GPIOx->PC1&=~Port_Pins; - GPIOx->PC2|=Port_Pins; - break; - - case GPIO_OUT_PP: - GPIOx->PC0|=Port_Pins; - GPIOx->PC1&=~Port_Pins; - GPIOx->PC2|=Port_Pins; - break; - - case GPIO_AF_OD: - GPIOx->PC0&=~Port_Pins; - GPIOx->PC1|=Port_Pins; - GPIOx->PC2|=Port_Pins; - break; - - case GPIO_AF_PP: - GPIOx->PC0|=Port_Pins; - GPIOx->PC1|=Port_Pins; - GPIOx->PC2|=Port_Pins; - break; - } -} - -/******************************************************************************* -* Function Name : GPIO_BitWrite -* Description : Set or reset the selected port pin -* Input 1 : Selected GPIO port -* Input 2 : Pin number -* Input 3 : bit value -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_BitWrite(GPIO_TypeDef *GPIOx, u8 Port_Pin, u8 Port_Val) -{ - if (Port_Val&0x01) GPIOx->PD |= 1<PD &= ~(1<PD = Port_Byte ? (GPIOx->PD&0x00FF) | ((u16)Port_Val<<8) - : (GPIOx->PD&0xFF00) | Port_Val; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/i2c.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/i2c.c deleted file mode 100644 index 70c7f68ad..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/i2c.c +++ /dev/null @@ -1,504 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : i2c.c -* Author : MCD Application Team -* Date First Issued : 09/05/2003 -* Description : This file provides Code sources I2C functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "i2c.h" -#include "rccu.h" -#include - -/******************************************************************************* -* Function Name : I2C_Init -* Description : Initializes I2C peripheral control and registers to their -* default reset values. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : None. -*******************************************************************************/ -void I2C_Init (I2C_TypeDef *I2Cx) -{ - //Initialize all the register of the specified I2C passed as parameter - I2Cx->CR=0x0; - I2Cx->CCR=0x0; - I2Cx->ECCR=0x0; - I2Cx->OAR1=0x0; - I2Cx->OAR2=0x0; - (void)I2Cx->SR1; - (void)I2Cx->SR2; - I2Cx->DR=0x0; -} - -/******************************************************************************* -* Function Name : I2C_OnOffConfig -* Description : Enables or disables I2C peripheral. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -void I2C_OnOffConfig (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - // Enable the I2C selected by setting twice the PE bit on the CR register - I2Cx->CR |= I2C_PESET_Mask; - I2Cx->CR |= I2C_PESET_Mask; - } - else - // Disable the I2C selected - I2Cx->CR &= ~I2C_PESET_Mask; -} - -/******************************************************************************* -* Function Name : I2C_FlagStatus -* Description : Checks whether any I2C Flag is set or not. -* Input : I2Cx ( I2C0 or I2C1 ) -* Access(DIRECT or INDIRECT) -* Flag : the flag to be read -* input 4: an (u8) variable needed in the case -* of the INDIRECT access -* Return : the NewState of the Flag (SET or RESET). -*******************************************************************************/ -FlagStatus I2C_FlagStatus (I2C_TypeDef *I2Cx, RegisterAccess Access, I2C_Flags Flag, ...) -{ - u32 Tmp; - - if (Access == DIRECT) - // Store in Tmp variable the register where is located the flag - Tmp = I2C_GetStatus(I2Cx)&Flag; - else - { - va_list list; - //Get the fourth register - va_start(list,Flag); - Tmp = va_arg(list,u32); - Tmp&=Flag; - } - //Return the Flag NewState - return Tmp != 0 ? SET : RESET; -} - -/******************************************************************************* -* Function Name : I2C_FlagClear -* Description : Clears the I2C Flag passed as a parameter -* Input : I2Cx ( I2C0 or I2C1 ) -* Flag : the flag to be read -* input3: an (u8) parameter needed in the case that the flag -* to be cleared need a write in one register -* Return : None. -*******************************************************************************/ -void I2C_FlagClear (I2C_TypeDef *I2Cx, I2C_Flags Flag, ...) -{ - u8 Tmp = (u8)*((u32 *)&Flag + sizeof(Flag)); - - if (Flag==I2C_ADD10 || Flag==I2C_EVF || Flag==I2C_BERR || Flag==I2C_ARLO || - Flag==I2C_STOPF || Flag==I2C_AF || Flag==I2C_ENDAD) - //flags that need a read of the SR2 register to be cleared - { - // Read the SR2 register - (void)I2Cx->SR2; - // Two flags need a second step to be cleared - switch (Flag) - { - case I2C_ADD10: I2Cx->DR = Tmp; break; - case I2C_ENDAD: I2Cx->CR|=0x20; break; - } - } - else if (Flag==I2C_SB || Flag==I2C_ADSL || Flag==I2C_BTF || Flag==I2C_TRA) - //flags that need a read of the SR1 register to be cleared - { - // Read the SR1 register - (void)I2Cx->SR1; - if (Flag==I2C_SB) I2Cx->DR=Tmp; - else if (Flag==I2C_BTF || Flag==I2C_TRA) (void)I2Cx->DR; - } - else if ( Flag==I2C_M_SL || Flag==I2C_GCAL) - //flags that need the PE bit to be cleared - { - I2C_OnOffConfig (I2Cx, DISABLE); - I2C_OnOffConfig (I2Cx, ENABLE); - } -} - -/******************************************************************************* -* Function Name : I2C_SpeedConfig -* Description : Selects I2C clock speed and configures its corresponding mode. -* Input : I2Cx ( I2C0 or I2C1 ) -* Clock: I2C expected clock in Hertz. -* Return : None. -*******************************************************************************/ -void I2C_SpeedConfig (I2C_TypeDef *I2Cx, u32 Clock) -{ - u32 FCLK; - u16 result; - // Get the FCLK frequency using the RCCU library - FCLK = RCCU_FrequencyValue ( RCCU_FCLK ); - // Test on speed mode - // Update the CCR and ECCR are updated - if (Clock <=100000) - // Standard mode selected - { - result = ((FCLK / Clock) - 7)/2; - //Clear FM/SM bit - I2Cx->CCR=result &0x7f; - } - else if (Clock <=400000) - { - // Fast mode selected - result = ((FCLK/Clock)-9)/3; - //set FM/SM bit - I2Cx->CCR=result |0x80; - } - I2Cx->ECCR= result >>7; -} -/******************************************************************************* -* Function Name : I2C_AddressConfig -* Description : Defines the I2C bus address of the interface. -* Input : I2Cx ( I2C0 or I2C1 ). -* Address: an u16 parameter indicating the address -* of the interface. -* Mode (I2C_Mode10,I2C_Mode7). -* Return : None. -*******************************************************************************/ -void I2C_AddressConfig (I2C_TypeDef *I2Cx, u16 Address, I2C_Addressing Mode) -{ - //Update OAR1 bit[7:1] by the lowest byte of address - I2Cx->OAR1 = (u8)Address; - - if (Mode == I2C_Mode10) - //Update Add8 and add9 bits in OAR2 - I2Cx->OAR2 |= (Address & 0x0300)>>7; -} - -/******************************************************************************* -* Function Name : I2C_FCLKConfig -* Description : Configures frequency bits according to RCLK frequency. -* the selected I2C must be disabled -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : None. -*******************************************************************************/ -void I2C_FCLKConfig (I2C_TypeDef *I2Cx) -{ - u32 FCLK; - // Get the FCLK frequency using the RCCU library - FCLK = RCCU_FrequencyValue ( RCCU_FCLK ); - // Test the value of the FCLK and affect FR0,FR1&FR2 of the OAR2 register - if (FCLK > 5000000) - { - if (FCLK <10000000) - I2Cx->OAR2 |= 0x00; - else if (FCLK <16670000) - I2Cx->OAR2 |= 0x20; - else if (FCLK < 26670000) - I2Cx->OAR2 |= 0x40; - else if (FCLK <40000000) - I2Cx->OAR2 |= 0x60; - else if (FCLK < 53330000) - I2Cx->OAR2 |= 0x80; - else if (FCLK < 66000000) - I2Cx->OAR2 |= 0xA0; - else if (FCLK <80000000) - I2Cx->OAR2 |= 0xC0; - else if (FCLK <100000000) - I2Cx->OAR2 |= 0xE0; - } -} - -/******************************************************************************* -* Function Name : I2C_AddressSend -* Description : Transmits the address byte to select the slave device. -* Input : I2Cx ( I2C0 or I2C1 ) -* Address: an u16 parameter indicating the slave address -* Mode (I2C_Mode10,I2C_Mode7). -* Direction (I2C_RX,I2C_TX). -* Return : None. -********************************************************************************/ -void I2C_AddressSend (I2C_TypeDef *I2Cx, u16 Address, I2C_Addressing Mode, I2C_Direction Direction) -{ - if (Mode == I2C_Mode10 ) - //10 bit addressing mode - { - // Update the DR register by generated header - I2Cx->DR = ((Address>>7)|0xf0)&0xfe; - //Wait till I2C_ADD10 flag is set - while ((I2Cx->SR1&0x40)==0); - //clear I2C_ADD10 flag - (void)I2Cx->SR2; - I2Cx->DR=(u8)Address; - //Test on the direction to define the read/write bit - if (Direction == I2C_RX) - { - //Wait till I2C_ENDAD flag is set - while ((I2Cx->SR2&0x20)==0); - I2Cx->CR|=0x20; - //Repeated START Generate - I2C_STARTGenerate (I2Cx, ENABLE); - //Test on SB flag status - while ((I2Cx->SR1&0x01)==0); - I2Cx->DR = ((Address>>7)|0xf1); - } - } - else - // 7 bit addressing mode - { - if (Direction == I2C_RX) Address|=0x01; else Address&=~0x01; - I2Cx->DR=(u8)Address; - } -} - -/******************************************************************************* -* Function Name : I2C_ByteSend -* Description : Send a single byte of data. -* Input : I2Cx ( I2C0 or I2C1 ) -* Data : the byte to be sent to the slave -* Return : None. -*******************************************************************************/ -void I2C_ByteSend (I2C_TypeDef *I2Cx, u8 Data) -{ - //Write in the DR register the byte to be sent - I2Cx->DR = Data; -} - -/******************************************************************************* -* Function Name : I2C_BufferSend -* Description : Send data from a buffer whose number of bytes is known -* Input : I2Cx ( I2C0 or I2C1 ) -* PtrToBuffer :pointer to the byte of buffer to be transmitted. -* NbOfBytes:Number of byte of the buffer -* Return : I2C_Tx_Status :transmission status (I2C_TX_AF, I2C_TX_ARLO, -* I2C_TX_BERR,I2C_TX_DATA_OK) -*******************************************************************************/ -I2C_Tx_Status I2C_BufferSend (I2C_TypeDef *I2Cx, u8 *PtrToBuffer, u8 NbOfBytes) -{ - u8 Interruption_Status; - u8 SentBytes; - u8 error; - I2C_Tx_Status I2C_TXTMP; - - //Test of the interrupt status - Interruption_Status=0; - Interruption_Status=I2Cx->CR & 0x01; - I2C_ITConfig (I2Cx, DISABLE); - //Wait till I2C_BTF bit is set - while ((I2Cx->SR1 & 0x08 )==0); - SentBytes=0; - while (SentBytesDR= *(PtrToBuffer+SentBytes); - //Wait till I2C_BTF bit is set or error detected - do - error = I2Cx->SR2 & 0x16; - while ((I2Cx->SR1 & 0x08)==0 && error==0); - // In case of error exit - if (error) break; - // increment SentBytes counter - SentBytes++; - } - if (error) - { - if (error & 0x10) - // I2C_TX_AF if Acknowledge failure is detected - I2C_TXTMP = I2C_TX_AF; - if (error & 0x02) - //I2C_TX_ARLO if the ARLO bit is set in the SR2 register - I2C_TXTMP = I2C_TX_ARLO; - if (error & 0x04) - // I2C_TX_BERR if the BERR bit is set in the SR2 register - I2C_TXTMP= I2C_TX_BERR; - } - else - //I2C_TX_DATA_OK to show that the buffer is well sent - I2C_TXTMP= I2C_TX_DATA_OK; - - //Restore the interrupt status - if (Interruption_Status==1) - I2C_ITConfig (I2Cx, ENABLE); - - return I2C_TXTMP; -} - -/******************************************************************************* -* Function Name : I2C_StringSend -* Description : Send data from a buffer -* Input : I2Cx ( I2C0 or I2C1 ) -* PtrToBuffer :pointer to the byte of string to be transmitted. -* Return : I2C_Tx_Status :transmission status (I2C_TX_AF, I2C_TX_ARLO, -* I2C_TX_BERR,I2C_TX_DATA_OK) -*******************************************************************************/ -I2C_Tx_Status I2C_StringSend (I2C_TypeDef *I2Cx, char *PtrToString) -{ - u8 NbOfBytes=0; - // count the number of byte composing the string passed as parameter. - while (*(PtrToString+NbOfBytes)!= '\0') - NbOfBytes++; - // call I2C_BufferSend function to execute the send part - return I2C_BufferSend (I2Cx,(u8 *)PtrToString,NbOfBytes); -} - -/******************************************************************************* -* Function Name : I2C_TransmissionStatus -* Description : Report the NewState of the transmission -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : I2C_Tx_Status :transmission status (I2C_TX_NO, I2C_TX_SB, -* I2C_TX_AF, I2C_TX_ARLO, I2C_TX_BERR,I2C_TX_ADD_OK, -* I2C_TX_DATA_OK,I2C_TX_ONGOING) -*******************************************************************************/ -I2C_Tx_Status I2C_TransmissionStatus (I2C_TypeDef *I2Cx) -{ - u8 SR1value; - u8 SR2value; - I2C_Tx_Status NewState; - - SR1value = I2Cx->SR1; - SR2value = I2Cx->SR2; - if ((I2Cx->SR1&0x10)==0) - NewState=I2C_TX_NO; - else if (I2Cx->SR1&0x01) - //I2C_SB bit is set - NewState=I2C_TX_SB; - else if ((SR2value & 0x10)&&(I2Cx->CR&0x04)) - //I2C_ACK &I2C_AF are both set - NewState=I2C_TX_AF; - else if (SR2value & 0x04) - //I2C_ARLO is set in multimaster mode - NewState=I2C_TX_ARLO; - else if (SR2value & 0x02) - //I2C_BERR bit is set - NewState=I2C_TX_BERR; - else if ((SR1value & 0x80)&& (I2Cx->SR2&0x20)) - //I2C_EVF and I2C_ENDAD are both set - NewState=I2C_TX_ADD_OK; - else if ((I2Cx->SR1&0x20)&& (I2Cx->SR1&0x08)) - //I2C_TRA and I2C_BTF are both set - NewState=I2C_TX_DATA_OK; - else - NewState=I2C_TX_ONGOING; - - return NewState; -} - -/******************************************************************************* -* Function Name : I2C_ByteReceive -* Description : Returns the received byte. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : the byte received -*******************************************************************************/ -u8 I2C_ByteReceive (I2C_TypeDef *I2Cx) -{ - //Wait till I2C_BTF bit is set - while ((I2Cx->SR1 & 0x08)==0); - return I2Cx->DR; -} - -/******************************************************************************* -* Function Name : I2C_BufferReceive -* Description : received a buffer. and return the status of error. -* Input : I2Cx ( I2C0 or I2C1 ) -* PtrToBuffer :pointer to the byte of buffer received. -* NbOfBytes:Number of byte to be received -* Return : I2C_Rx_Status:the NewState of the reception (,I2C_RX_AF, -* I2C_RX_ARLO,I2C_RX_BERR, I2C_RX_DATA_OK) -*******************************************************************************/ -I2C_Rx_Status I2C_BufferReceive (I2C_TypeDef *I2Cx, u8 *PtrToBuffer, u8 NbOfBytes) -{ - u8 Interruption_Status; - u8 ReceivedBytes; - u8 error; - I2C_Rx_Status I2C_RXTMP; - - //Test of the interrupt status - Interruption_Status=0; - Interruption_Status=I2Cx->CR & 0x01; - I2C_ITConfig (I2Cx, DISABLE); - ReceivedBytes=0; - while (ReceivedBytesSR2 & 0x16; - while ((I2Cx->SR1 & 0x08)==0 && !error); - if (error==0) - // No error detected - { - *(PtrToBuffer+ReceivedBytes) = I2Cx->DR; - ReceivedBytes++; - } - else break; - } - if (error) - { - if (error & 0x10) - // I2C_RX_AF if Acknowledge failure is detected - I2C_RXTMP= I2C_RX_AF; - else if (error & 0x02) - // I2C_RX_ARLO if the ARLO bit is set in the SR2 register - I2C_RXTMP= I2C_RX_ARLO; - else if (error & 0x04) - // I2C_RX_BERR if the BERR bit is set in the SR2 register - I2C_RXTMP= I2C_RX_BERR; - } - else - //I2C_RX_DATA_OK to show that the buffer is well sent - I2C_RXTMP= I2C_RX_DATA_OK; - - //Restore the interrupt status - if (Interruption_Status==1) - I2C_ITConfig (I2Cx, ENABLE); - - return I2C_RXTMP; -} - -/******************************************************************************* -* Function Name :I2C_ReceptionStatus -* Description : Report the reception NewState. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : I2C_Rx_Status:the NewState of the reception ( I2C_RX_NO, -* I2C_RX_SB,I2C_RX_AF,I2C_RX_ARLO,I2C_RX_BERR,I2C_RX_ADD_OK, -* I2C_RX_DATA_OK, I2C_RX_ONGOING) -*******************************************************************************/ -I2C_Rx_Status I2C_ReceptionStatus (I2C_TypeDef *I2Cx) -{ - u8 SR1value; - u8 SR2value; - I2C_Rx_Status NewState; - SR1value= I2Cx->SR1; - SR2value= I2Cx->SR2; - - if ((I2Cx->SR1&0x10) == 0) - NewState=I2C_RX_NO; - else if (I2Cx->SR1&0x01) - //I2C_SB bit is set - NewState=I2C_RX_SB; - else if ((SR2value & 0x10) && (I2Cx->CR&0x04)) - //I2C_ACK &I2C_AF are both set - NewState=I2C_RX_AF; - else if (SR2value & 0x04) - //I2C_ARLO is set - NewState=I2C_RX_ARLO; - else if (SR2value & 0x02) - //I2C_BERR bit is set - NewState=I2C_RX_BERR; - else if ((SR1value & 0x80) && (I2Cx->SR1&0x08)==0) - //2C_EVF is set & I2C_BTF is not set - NewState=I2C_RX_ADD_OK; - else if ((I2Cx->SR1&0x20)==0 && (I2Cx->SR1&0x08)) - //II2C_TRA is cleared & I2C_BTF is set - NewState=I2C_RX_DATA_OK; - else - NewState=I2C_RX_ONGOING; - return NewState; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/71x_conf.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/71x_conf.h deleted file mode 100644 index 6e416c8e3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/71x_conf.h +++ /dev/null @@ -1,73 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_conf.h -* Author : MCD Application Team -* Date First Issued : 16/05/2003 -* Description : Library configuration for the WDG example -******************************************************************************** -* History: -* 24/05/05 : V3.0 -* 30/11/04 : V2.0 -* 16/05/03 : Created -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __71x_CONF_H -#define __71x_CONF_H - -/* Comment the line below to put the library in release mode */ -//#define DEBUG - -#define INLINE static inline - -//#define USE_SERIAL_PORT -//#define USE_UART0 - -/* Main Oscillator Frequency value = 4 Mhz */ -#define RCCU_Main_Osc 4000000 - -/* Comment the lines below corresponding to unwanted peripherals */ -#define _ADC12 -#define _APB -#define _APB1 -#define _APB2 -#define _BSPI -#define _BSPI0 -#define _BSPI1 -#define _CAN -#define _EIC -#define _EMI -#define _FLASH -#define _GPIO -#define _GPIO0 -#define _GPIO1 -#define _GPIO2 -#define _I2C -#define _I2C0 -#define _I2C1 -#define _PCU -#define _RCCU -#define _RTC -#define _TIM -#define _TIM0 -#define _TIM1 -#define _TIM2 -#define _TIM3 -#define _UART -#define _UART0 -#define _UART1 -#define _UART2 -#define _UART3 -#define _USB -#define _WDG -#define _XTI -#define _IRQVectors - -#endif /* __71x_CONF_H */ - - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/71x_it.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/71x_it.h deleted file mode 100644 index 5b99928e1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/71x_it.h +++ /dev/null @@ -1,62 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_it.h -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Interrupt handlers -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef _71x_IT_H -#define _71x_IT_H - -#include "71x_lib.h" - - -void Undefined_Handler (void); -void FIQ_Handler (void); -void SWI_Handler (void); -void Prefetch_Handler (void); -void Abort_Handler (void); -void T0TIMI_IRQHandler (void); -void FLASH_IRQHandler (void); -void RCCU_IRQHandler (void); -void RTC_IRQHandler (void); -void WDG_IRQHandler (void); -void XTI_IRQHandler (void); -void USBHP_IRQHandler (void); -void I2C0ITERR_IRQHandler(void); -void I2C1ITERR_IRQHandler(void); -void UART0_IRQHandler (void); -void UART1_IRQHandler (void); -void UART2_IRQHandler (void); -void UART3_IRQHandler (void); -void BSPI0_IRQHandler (void); -void BSPI1_IRQHandler (void); -void I2C0_IRQHandler (void); -void I2C1_IRQHandler (void); -void CAN_IRQHandler (void); -void ADC12_IRQHandler (void); -void T1TIMI_IRQHandler (void); -void T2TIMI_IRQHandler (void); -void T3TIMI_IRQHandler (void); -void HDLC_IRQHandler (void); -void USBLP_IRQHandler (void); -void T0TOI_IRQHandler (void); -void T0OC1_IRQHandler (void); -void T0OC2_IRQHandler (void); - -#endif /* _71x_IT_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/71x_lib.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/71x_lib.h deleted file mode 100644 index 5532ca472..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/71x_lib.h +++ /dev/null @@ -1,101 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_lib.h -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Global include for all peripherals -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __71x_LIB_H -#define __71x_LIB_H - -#include "71x_map.h" -#include "71x_conf.h" - - -#ifdef _ADC12 - #include "adc12.h" -#endif - -#ifdef _APB - #include "apb.h" -#endif - -#ifdef _BSPI - #include "bspi.h" -#endif - -#ifdef _CAN - #include "can.h" -#endif - -#ifdef _EIC - #include "eic.h" -#endif - -#ifdef _EMI - #include "emi.h" -#endif - -#ifdef _FLASH - #include "flash.h" -#endif - -#ifdef _GPIO - #include "gpio.h" -#endif - -#ifdef _I2C - #include "i2c.h" -#endif - -#ifdef _PCU - #include "pcu.h" -#endif - -#ifdef _RCCU - #include "rccu.h" -#endif - -#ifdef _RTC - #include "rtc.h" -#endif - -#ifdef _TIM - #include "tim.h" -#endif - -#ifdef _UART - #include "uart.h" -#endif - -#ifdef _USB -#endif - -#ifdef _WDG - #include "wdg.h" -#endif - -#ifdef _XTI - #include "xti.h" -#endif - - -#ifdef LIBDEBUG - void libdebug(void); -#endif - -#endif /* __71x_LIB_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/71x_map.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/71x_map.h deleted file mode 100644 index 0f49a1549..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/71x_map.h +++ /dev/null @@ -1,611 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_map.h -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Peripherals memory mapping and registers structures -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __71x_map_H -#define __71x_map_H - -#ifndef EXT - #define EXT extern -#endif - -#include "71x_conf.h" -#include "71x_type.h" - - -/* IP registers structures */ - -typedef volatile struct -{ - vu16 DATA0; - vu16 EMPTY1[3]; - vu16 DATA1; - vu16 EMPTY2[3]; - vu16 DATA2; - vu16 EMPTY3[3]; - vu16 DATA3; - vu16 EMPTY4[3]; - vu16 CSR; - vu16 EMPTY5[7]; - vu16 CPR; -} ADC12_TypeDef; - -typedef volatile struct -{ - vu32 CKDIS; - vu32 SWRES; -} APB_TypeDef; - -typedef volatile struct -{ - vu16 RXR; - vu16 EMPTY1; - vu16 TXR; - vu16 EMPTY2; - vu16 CSR1; - vu16 EMPTY3; - vu16 CSR2; - vu16 EMPTY4; - vu16 CLK; -} BSPI_TypeDef; - -typedef volatile struct -{ - vu16 CRR; - vu16 EMPTY1; - vu16 CMR; - vu16 EMPTY2; - vu16 M1R; - vu16 EMPTY3; - vu16 M2R; - vu16 EMPTY4; - vu16 A1R; - vu16 EMPTY5; - vu16 A2R; - vu16 EMPTY6; - vu16 MCR; - vu16 EMPTY7; - vu16 DA1R; - vu16 EMPTY8; - vu16 DA2R; - vu16 EMPTY9; - vu16 DB1R; - vu16 EMPTY10; - vu16 DB2R; - vu16 EMPTY11[27]; -} CAN_MsgObj_TypeDef; - -typedef volatile struct -{ - vu16 CR; - vu16 EMPTY1; - vu16 SR; - vu16 EMPTY2; - vu16 ERR; - vu16 EMPTY3; - vu16 BTR; - vu16 EMPTY4; - vu16 IDR; - vu16 EMPTY5; - vu16 TESTR; - vu16 EMPTY6; - vu16 BRPR; - vu16 EMPTY7[3]; - CAN_MsgObj_TypeDef sMsgObj[2]; - vu16 EMPTY8[16]; - vu16 TR1R; - vu16 EMPTY9; - vu16 TR2R; - vu16 EMPTY10[13]; - vu16 ND1R; - vu16 EMPTY11; - vu16 ND2R; - vu16 EMPTY12[13]; - vu16 IP1R; - vu16 EMPTY13; - vu16 IP2R; - vu16 EMPTY14[13]; - vu16 MV1R; - vu16 EMPTY15; - vu16 MV2R; - vu16 EMPTY16; -} CAN_TypeDef; - -typedef volatile struct -{ - vu32 ICR; - vu32 CICR; - vu32 CIPR; - vu32 EMPTY1[3]; - vu32 IVR; - vu32 FIR; - vu32 IER; - vu32 EMPTY2[7]; - vu32 IPR; - vu32 EMPTY3[7]; - vu32 SIR[32]; -} EIC_TypeDef; - -typedef volatile struct -{ - vu16 BCON0; - vu16 EMPTY1; - vu16 BCON1; - vu16 EMPTY2; - vu16 BCON2; - vu16 EMPTY3; - vu16 BCON3; - vu16 EMPTY4; -} EMI_TypeDef; - -typedef volatile struct -{ - vu32 CR0; - vu32 CR1; - vu32 DR0; - vu32 DR1; - vu32 AR; - vu32 ER; -} FLASHR_TypeDef; - -typedef volatile struct -{ - vu32 NVWPAR; - vu32 EMPTY; - vu32 NVAPR0; - vu32 NVAPR1; -} FLASHPR_TypeDef; - -typedef volatile struct -{ - vu16 PC0; - vu16 EMPTY1; - vu16 PC1; - vu16 EMPTY2; - vu16 PC2; - vu16 EMPTY3; - vu16 PD; - vu16 EMPTY4; -} GPIO_TypeDef; - -typedef volatile struct -{ - vu8 CR; - vu8 EMPTY1[3]; - vu8 SR1; - vu8 EMPTY2[3]; - vu8 SR2; - vu8 EMPTY3[3]; - vu8 CCR; - vu8 EMPTY4[3]; - vu8 OAR1; - vu8 EMPTY5[3]; - vu8 OAR2; - vu8 EMPTY6[3]; - vu8 DR; - vu8 EMPTY7[3]; - vu8 ECCR; -} I2C_TypeDef; - -typedef volatile struct -{ - vu32 CCR; - vu32 EMPTY1; - vu32 CFR; - vu32 EMPTY2[3]; - vu32 PLL1CR; - vu32 PER; - vu32 SMR; -} RCCU_TypeDef; - -typedef volatile struct -{ - vu16 MDIVR; - vu16 EMPTY1; - vu16 PDIVR; - vu16 EMPTY2; - vu16 RSTR; - vu16 EMPTY3; - vu16 PLL2CR; - vu16 EMPTY4; - vu16 BOOTCR; - vu16 EMPTY5; - vu16 PWRCR; -} PCU_TypeDef; - -typedef volatile struct -{ - vu16 CRH; - vu16 EMPTY1; - vu16 CRL; - vu16 EMPTY2; - vu16 PRLH; - vu16 EMPTY3; - vu16 PRLL; - vu16 EMPTY4; - vu16 DIVH; - vu16 EMPTY5; - vu16 DIVL; - vu16 EMPTY6; - vu16 CNTH; - vu16 EMPTY7; - vu16 CNTL; - vu16 EMPTY8; - vu16 ALRH; - vu16 EMPTY9; - vu16 ALRL; -} RTC_TypeDef; - -typedef volatile struct -{ - vu16 ICAR; - vu16 EMPTY1; - vu16 ICBR; - vu16 EMPTY2; - vu16 OCAR; - vu16 EMPTY3; - vu16 OCBR; - vu16 EMPTY4; - vu16 CNTR; - vu16 EMPTY5; - vu16 CR1; - vu16 EMPTY6; - vu16 CR2; - vu16 EMPTY7; - vu16 SR; -} TIM_TypeDef; - -typedef volatile struct -{ - vu16 BR; - vu16 EMPTY1; - vu16 TxBUFR; - vu16 EMPTY2; - vu16 RxBUFR; - vu16 EMPTY3; - vu16 CR; - vu16 EMPTY4; - vu16 IER; - vu16 EMPTY5; - vu16 SR; - vu16 EMPTY6; - vu16 GTR; - vu16 EMPTY7; - vu16 TOR; - vu16 EMPTY8; - vu16 TxRSTR; - vu16 EMPTY9; - vu16 RxRSTR; -} UART_TypeDef; - -typedef volatile struct -{ - vu32 EP0R; - vu32 EP1R; - vu32 EP2R; - vu32 EP3R; - vu32 EP4R; - vu32 EP5R; - vu32 EP6R; - vu32 EP7R; - vu32 EP8R; - vu32 EP9R; - vu32 EP10R; - vu32 EP11R; - vu32 EP12R; - vu32 EP13R; - vu32 EP14R; - vu32 EP15R; - vu32 CNTR; - vu32 ISTR; - vu32 FNR; - vu32 DADDR; - vu32 BTABLE; -} USB_TypeDef; - -typedef volatile struct -{ - vu16 CR; - vu16 EMPTY1; - vu16 PR; - vu16 EMPTY2; - vu16 VR; - vu16 EMPTY3; - vu16 CNT; - vu16 EMPTY4; - vu16 SR; - vu16 EMPTY5; - vu16 MR; - vu16 EMPTY6; - vu16 KR; -} WDG_TypeDef; - -typedef volatile struct -{ - vu8 SR; - vu8 EMPTY1[7]; - vu8 CTRL; - vu8 EMPTY2[3]; - vu8 MRH; - vu8 EMPTY3[3]; - vu8 MRL; - vu8 EMPTY4[3]; - vu8 TRH; - vu8 EMPTY5[3]; - vu8 TRL; - vu8 EMPTY6[3]; - vu8 PRH; - vu8 EMPTY7[3]; - vu8 PRL; -} XTI_TypeDef; - - -/* IRQ vectors */ -typedef volatile struct -{ - vu32 T0TIMI_IRQHandler; - vu32 FLASH_IRQHandler; - vu32 RCCU_IRQHandler; - vu32 RTC_IRQHandler; - vu32 WDG_IRQHandler; - vu32 XTI_IRQHandler; - vu32 USBHP_IRQHandler; - vu32 I2C0ITERR_IRQHandler; - vu32 I2C1ITERR_IRQHandler; - vu32 UART0_IRQHandler; - vu32 UART1_IRQHandler; - vu32 UART2_IRQHandler; - vu32 UART3_IRQHandler; - vu32 BSPI0_IRQHandler; - vu32 BSPI1_IRQHandler; - vu32 I2C0_IRQHandler; - vu32 I2C1_IRQHandler; - vu32 CAN_IRQHandler; - vu32 ADC12_IRQHandler; - vu32 T1TIMI_IRQHandler; - vu32 T2TIMI_IRQHandler; - vu32 T3TIMI_IRQHandler; - vu32 EMPTY1[3]; - vu32 HDLC_IRQHandler; - vu32 USBLP_IRQHandler; - vu32 EMPTY2[2]; - vu32 T0TOI_IRQHandler; - vu32 T0OC1_IRQHandler; - vu32 T0OC2_IRQHandler; -} IRQVectors_TypeDef; - -/*===================================================================*/ - -/* Memory mapping */ - -#define RAM_BASE 0x20000000 - -#define FLASHR_BASE 0x40100000 -#define FLASHPR_BASE 0x4010DFB0 - -#define EXTMEM_BASE 0x60000000 -#define RCCU_BASE 0xA0000000 -#define PCU_BASE 0xA0000040 -#define APB1_BASE 0xC0000000 -#define APB2_BASE 0xE0000000 -#define EIC_BASE 0xFFFFF800 - -#define I2C0_BASE (APB1_BASE + 0x1000) -#define I2C1_BASE (APB1_BASE + 0x2000) -#define UART0_BASE (APB1_BASE + 0x4000) -#define UART1_BASE (APB1_BASE + 0x5000) -#define UART2_BASE (APB1_BASE + 0x6000) -#define UART3_BASE (APB1_BASE + 0x7000) -#define CAN_BASE (APB1_BASE + 0x9000) -#define BSPI0_BASE (APB1_BASE + 0xA000) -#define BSPI1_BASE (APB1_BASE + 0xB000) -#define USB_BASE (APB1_BASE + 0x8800) - -#define XTI_BASE (APB2_BASE + 0x101C) -#define GPIO0_BASE (APB2_BASE + 0x3000) -#define GPIO1_BASE (APB2_BASE + 0x4000) -#define GPIO2_BASE (APB2_BASE + 0x5000) -#define ADC12_BASE (APB2_BASE + 0x7000) -#define TIM0_BASE (APB2_BASE + 0x9000) -#define TIM1_BASE (APB2_BASE + 0xA000) -#define TIM2_BASE (APB2_BASE + 0xB000) -#define TIM3_BASE (APB2_BASE + 0xC000) -#define RTC_BASE (APB2_BASE + 0xD000) -#define WDG_BASE (APB2_BASE + 0xE000) - -#define EMI_BASE (EXTMEM_BASE + 0x0C000000) - -/*===================================================================*/ - -/* IP data access */ - -#ifndef LIBDEBUG - #define ADC12 ((ADC12_TypeDef *)ADC12_BASE) - - #define APB1 ((APB_TypeDef *)(APB1_BASE+0x10)) - #define APB2 ((APB_TypeDef *)(APB2_BASE+0x10)) - - #define BSPI0 ((BSPI_TypeDef *)BSPI0_BASE) - #define BSPI1 ((BSPI_TypeDef *)BSPI1_BASE) - - #define CAN ((CAN_TypeDef *)CAN_BASE) - - #define EIC ((EIC_TypeDef *)EIC_BASE) - - #define EMI ((EMI_TypeDef *)EMI_BASE) - - #define FLASHR ((FLASHR_TypeDef *)FLASHR_BASE) - #define FLASHPR ((FLASHPR_TypeDef *)FLASHPR_BASE) - - #define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE) - #define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE) - #define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE) - - #define I2C0 ((I2C_TypeDef *)I2C0_BASE) - #define I2C1 ((I2C_TypeDef *)I2C1_BASE) - - #define PCU ((PCU_TypeDef *)PCU_BASE) - - #define RCCU ((RCCU_TypeDef *)RCCU_BASE) - - #define RTC ((RTC_TypeDef *)RTC_BASE) - - #define TIM0 ((TIM_TypeDef *)TIM0_BASE) - #define TIM1 ((TIM_TypeDef *)TIM1_BASE) - #define TIM2 ((TIM_TypeDef *)TIM2_BASE) - #define TIM3 ((TIM_TypeDef *)TIM3_BASE) - - #define UART0 ((UART_TypeDef *)UART0_BASE) - #define UART1 ((UART_TypeDef *)UART1_BASE) - #define UART2 ((UART_TypeDef *)UART2_BASE) - #define UART3 ((UART_TypeDef *)UART3_BASE) - - #define USB ((USB_TypeDef *)USB_BASE) - - #define WDG ((WDG_TypeDef *)WDG_BASE) - - #define XTI ((XTI_TypeDef *)XTI_BASE) - - #define IRQVectors ((IRQVectors_TypeDef *)&T0TIMI_Addr) - -#else /* LIBDEBUG */ - - #ifdef _ADC12 - EXT ADC12_TypeDef *ADC12; - #endif - - #ifdef _APB - #ifdef _APB1 - EXT APB_TypeDef *APB1; - #endif - #ifdef _APB2 - EXT APB_TypeDef *APB2; - #endif - #endif - - #ifdef _BSPI - #ifdef _BSPI0 - EXT BSPI_TypeDef *BSPI0; - #endif - #ifdef _BSPI1 - EXT BSPI_TypeDef *BSPI1; - #endif - #endif - - #ifdef _CAN - EXT CAN_TypeDef *CAN; - #endif - - #ifdef _EIC - EXT EIC_TypeDef *EIC; - #endif - - #ifdef _EMI - EXT EMI_TypeDef *EMI; - #endif - - #ifdef _FLASH - EXT FLASHR_TypeDef *FLASHR; - EXT FLASHPR_TypeDef *FLASHPR; - #endif - - #ifdef _GPIO - #ifdef _GPIO0 - EXT GPIO_TypeDef *GPIO0; - #endif - #ifdef _GPIO1 - EXT GPIO_TypeDef *GPIO1; - #endif - #ifdef _GPIO2 - EXT GPIO_TypeDef *GPIO2; - #endif - #endif - - #ifdef _I2C - #ifdef _I2C0 - EXT I2C_TypeDef *I2C0; - #endif - #ifdef _I2C1 - EXT I2C_TypeDef *I2C1; - #endif - #endif - - #ifdef _PCU - EXT PCU_TypeDef *PCU; - #endif - - #ifdef _RCCU - EXT RCCU_TypeDef *RCCU; - #endif - - #ifdef _RTC - EXT RTC_TypeDef *RTC; - #endif - - #ifdef _TIM - #ifdef _TIM0 - EXT TIM_TypeDef *TIM0; - #endif - #ifdef _TIM1 - EXT TIM_TypeDef *TIM1; - #endif - #ifdef _TIM2 - EXT TIM_TypeDef *TIM2; - #endif - #ifdef _TIM3 - EXT TIM_TypeDef *TIM3; - #endif - #endif - - #ifdef _UART - #ifdef _UART0 - EXT UART_TypeDef *UART0; - #endif - #ifdef _UART1 - EXT UART_TypeDef *UART1; - #endif - #ifdef _UART2 - EXT UART_TypeDef *UART2; - #endif - #ifdef _UART3 - EXT UART_TypeDef *UART3; - #endif - #endif - - #ifdef _USB - EXT USB_TypeDef *USB; - #endif - - #ifdef _WDG - EXT WDG_TypeDef *WDG; - #endif - - #ifdef _XTI - EXT XTI_TypeDef *XTI; - #endif - - #ifdef _IRQVectors - EXT IRQVectors_TypeDef *IRQVectors; - #endif - -#endif /* LIBDEBUG */ - -#endif /* __71x_map_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/71x_type.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/71x_type.h deleted file mode 100644 index ccf60ae1d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/71x_type.h +++ /dev/null @@ -1,51 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_type.h -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Common data types -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef _71x_type_H -#define _71x_type_H - -typedef unsigned long u32; -typedef unsigned short u16; -typedef unsigned char u8; - -typedef signed long s32; -typedef signed short s16; -typedef signed char s8; - -typedef volatile unsigned long vu32; -typedef volatile unsigned short vu16; -typedef volatile unsigned char vu8; - -typedef volatile signed long vs32; -typedef volatile signed short vs16; -typedef volatile signed char vs8; - -/*===================================================================*/ -typedef enum { FALSE = 0, TRUE = !FALSE } bool; -/*===================================================================*/ -typedef enum { RESET = 0, SET = !RESET } FlagStatus; -/*===================================================================*/ -typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -/*===================================================================*/ -typedef enum { INDIRECT = 0, DIRECT = !INDIRECT} RegisterAccess; -/*===================================================================*/ - -#endif /* _71x_type_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/adc12.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/adc12.h deleted file mode 100644 index a3c0581fd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/adc12.h +++ /dev/null @@ -1,181 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : adc12.h -* Author : MCD Application Team -* Date First Issued : 07/31/2003 -* Description : ADC12 functions prototypes -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef _ADC12_H -#define _ADC12_H - -#include "71x_map.h" -#include "rccu.h" - -//--------------------ADC12 Conversion modes----------------------------------- -typedef enum -{ - ADC12_SINGLE, - ADC12_ROUND -} ADC12_Modes; - -//--------------------ADC12 Channels------------------------------------------- -typedef enum -{ - ADC12_CHANNEL0 = 0x00, - ADC12_CHANNEL1 = 0x10, - ADC12_CHANNEL2 = 0x20, - ADC12_CHANNEL3 = 0x30 -} ADC12_Channels; - -//--------------------ADC12 control status register flag----------------------- -typedef enum -{ - ADC12_DA0 = 0x01, - ADC12_DA1 = 0x02, - ADC12_DA2 = 0x04, - ADC12_DA3 = 0x08, - ADC12_OR = 0x2000 -} ADC12_Flags; - -// Masks for the update of interrupt bit for channel n -#define ADC12_IT0_Mask 0x0100 -#define ADC12_IT1_Mask 0x0200 -#define ADC12_IT2_Mask 0x0400 -#define ADC12_IT3_Mask 0x0800 - -//Mask for the update of all the interrupt bit in the CSR -#define ADC12_IT_Mask 0x0F00 - -//Mask for Selecting mode -#define ADC12_Mode_Mask 0x0040 - -//Mask for configuring the converter -#define ADC12_Start_Mask 0x0020 - -/******************************************************************************* -* Function Name : ADC12_Init -* Description : Intialize the ADC -* Input : None. -* Return : None. -*******************************************************************************/ -void ADC12_Init(void); - -/******************************************************************************* -* Function Name : ADC12_ConversionStart -* Description : start the Conversion. -* Input : None -* Return : None -*******************************************************************************/ -INLINE void ADC12_ConversionStart (void) -{ - // Set the ADCen bit of the bootconf register - PCU->BOOTCR |= ADC12_Start_Mask; -} - -/******************************************************************************* -* Function Name : ADC12_ConversionStop -* Description : Disable the ADC -* Input : None. -* Return : None. -*******************************************************************************/ -INLINE void ADC12_ConversionStop(void) -{ - // Clear the ADCen bit of the bootconf register - PCU->BOOTCR &= ~ADC12_Start_Mask; -} - -/******************************************************************************* -* Function Name : ADC12_ModeConfig -* Description : Configure the mode of conversion -* Input : ADC12_SINGLE: single channel mode -* ADC12_ROUND : round robin mode -* Return : None -*******************************************************************************/ -INLINE void ADC12_ModeConfig (ADC12_Modes ConversionMode) -{ - // Select the mode of conversion and update the CSR[6] - ADC12->CSR= ConversionMode == ADC12_SINGLE ? ADC12->CSR | ADC12_Mode_Mask :\ - ADC12->CSR & ~ADC12_Mode_Mask; -} - -/******************************************************************************* -* Function Name : ADC12_PrescalerConfig -* Description : Configure the prescaler -* Input : Adc12_clk: Sampling frequency. -* Return : None. -*******************************************************************************/ -void ADC12_PrescalerConfig(u32 Adc12_clk); - -/******************************************************************************* -* Function Name : ADC12_ChannelSelect -* Description : select the channel passed as parameter to be converted. -* Input : ADC12_Channel: channel selected to be converted it may be -* ADC12_CHANNEL0 : select channel 0 -* ADC12_CHANNEL1 : select channel 1 -* ADC12_CHANNEL2 : select channel 2 -* ADC12_CHANNEL3 : select channel 3 -* Return : None -*******************************************************************************/ -INLINE void ADC12_ChannelSelect(ADC12_Channels ADC12_Channel) -{ - // Update the CSR by the value of the selected channel - ADC12->CSR |= ADC12_Channel; -} - -/******************************************************************************* -* Function Name : ADC12_FlagStatus -* Description : test if the flag passed in parameter is set or not -* Input : ADC12_DA0 :Data Available on Channel 0 -* ADC12_DA1 :Data Available on Channel 1 -* ADC12_DA2 :Data Available on Channel 2 -* ADC12_DA3 :Data Available on Channel 3 -* ADC12_OR :Overrun -* Return : SET: if the flag is set -* RESET: if the flag is clear -*******************************************************************************/ -INLINE FlagStatus ADC12_FlagStatus (ADC12_Flags flag) -{ - // Test on the flag status and return set or RESET - return ADC12->CSR & flag ? SET : RESET; -} - -/******************************************************************************* -* Function Name : ADC12_ConversionValue -* Description : Read the conversion result from the data register. -* Input : ADC12_Channel :number of the register to read -* ADC12_CHANNEL0 : read the DATA0 register -* ADC12_CHANNEL1 : read the DATA1 register -* ADC12_CHANNEL2 : read the DATA2 register -* ADC12_CHANNEL3 : read the DATA3 register -* Return : the register value of the channel converted -*******************************************************************************/ -INLINE u16 ADC12_ConversionValue( ADC12_Channels ADC12_Channel) -{ - // Clear the corespondent DA bit - ADC12->CSR &= ~(1<<(ADC12_Channel >> 4)); - // Only the 12 MSB of the DATAn Register are taken - return *(u16 *)(ADC12_BASE + (ADC12_Channel >> 1)) >> 4; -} - -/******************************************************************************* -* Function Name : ADC12_ITConfig -* Description : enable or disable the interruption -* Input : status=ENABLE=>enable interrupt -* status=DISABLE=>disable interrupt -* Return : None -*******************************************************************************/ -void ADC12_ITConfig (FunctionalState NewState); - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/apb.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/apb.h deleted file mode 100644 index 2e512d97d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/apb.h +++ /dev/null @@ -1,89 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : apb.h -* Author : MCD Application Team -* Date First Issued : 05/30/2003 -* Description : This file contains all the functions prototypes for the -* APB bridge software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __APB_H -#define __APB_H - -#include "71x_map.h" - -/* APB1 Peripherals */ -#define I2C0_Periph 0x0000 -#define I2C1_Periph 0x0002 -#define UART0_Periph 0x0008 -#define UART1_Periph 0x0010 -#define UART2_Periph 0x0020 -#define UART3_Periph 0x0080 -#define USB_Periph 0x0100 -#define CAN_Periph 0x0200 -#define BSPI0_Periph 0x0400 -#define BSPI1_Periph 0x0800 -#define HDLC_Periph 0x2000 - -/* APB2 Peripherals */ -#define XTI_Periph 0x0000 -#define GPIO0_Periph 0x0002 -#define GPIO1_Periph 0x0004 -#define GPIO2_Periph 0x0008 -#define ADC12_Periph 0x0010 -#define TIM0_Periph 0x0080 -#define TIM1_Periph 0x0200 -#define TIM2_Periph 0x0400 -#define TIM3_Periph 0x0800 -#define RTC_Periph 0x1000 -#define WDG_Periph 0x2000 -#define EIC_Periph 0x4000 - -/******************************************************************************* -* Function Name : APB_ClockConfig -* Description : Enables/Disables the Clock gating for peripherals on the APB -* bridge passed in parameters. -* Input : APBx ( APB1 or APB2 ) -* NewState ENABLE or DISABLE -* NewValue (u16) -* Return : None -*******************************************************************************/ -INLINE void APB_ClockConfig ( APB_TypeDef *APBx, - FunctionalState NewState, - u16 NewValue ) -{ - if (NewState == ENABLE) APBx->CKDIS &= ~NewValue; - else APBx->CKDIS |= NewValue; -} - -/******************************************************************************* -* Function Name : APB_SwResetConfig -* Description : Enables/Disables the software Reset for peripherals on the APB -* bridge passed in parameters. -* Input : APBx ( APB1 or APB2 ) -* NewState ENABLE or DISABLE -* NewValue (u16) -* Return : None -*******************************************************************************/ -INLINE void APB_SwResetConfig ( APB_TypeDef *APBx, - FunctionalState NewState, - u16 NewValue ) -{ - if (NewState == ENABLE) APBx->SWRES |= NewValue; - else APBx->SWRES &= ~NewValue; -} - -#endif // __APB_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/bspi.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/bspi.h deleted file mode 100644 index 0761c500b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/bspi.h +++ /dev/null @@ -1,324 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : bspi.h -* Author : MCD Application Team -* Date First Issued : 16/05/2003 -* Description : This file contains all the functions prototypes for the -* BSPI software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __bspi_H -#define __bspi_H - -#include "71x_map.h" - -typedef enum { - BSPI_BERIT = 0x80, - BSPI_RCIT = 0x10, - BSPI_ALL = 0x90 -} BSPI_ITS; - -typedef enum { - BSPI_BERR = 0x004, - BSPI_RFNE = 0x008, - BSPI_RFF = 0x010, - BSPI_ROFL = 0x020, - BSPI_TFE = 0x040, - BSPI_TUFL = 0x080, - BSPI_TFF = 0x100, - BSPI_TFNE = 0x200 -} BSPI_Flags; - -typedef enum { - BSPI_TR_FE, - BSPI_TR_UFL, - BSPI_TR_FF, - BSPI_TR_DIS -} BSPI_TR_IT_SRCS; - -typedef enum { - BSPI_RC_FNE, - BSPI_RC_FF, - BSPI_RC_DIS -} BSPI_RC_IR_SRCS; - -#define BSPI_PESET_Mask 0x01 -#define BSPI_DFIFO_Mask 0xFFFE -#define BSPI_CPHA_Mask 0x200 -#define BSPI_CPOL_Mask 0x100 -#define BSPI_BSPI0_Base 0xA000 -#define BSPI_BSPI1_Base 0xB000 - - -/******************************************************************************* -* Function Name : BSPI_BSPI0Conf -* Description : configure STARM71x on BSPI0 mode. -* Input 2 : NewState: specifies the status of the BSPI -* : NewState value must be either ENABLE or DISABLE: -* : ENABLE: the specified BSPI0 peripheral will be enabled. -* : DISABLE: the specified BSPI0 peripheral will be disabled.. -* Output : SPI0 EN bit in BOOTCR. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_BSPI0Conf(FunctionalState NewState) -{ - if (NewState == ENABLE) PCU->BOOTCR |= 0x04; else PCU->BOOTCR &= ~0x04; -} - -/******************************************************************************* -* Function Name : BSPI_Init -* Description : Initializes BSPI peripheral control and registers to their default reset values. -* Input : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Output : BSPI peripheral registers and BSPI global variables are initialized. -* Return : None. -*******************************************************************************/ -void BSPI_Init( BSPI_TypeDef *BSPIx); - -/******************************************************************************* -* Function Name : BSPI_Enable -* Description : Enables/disables the specified BSPI peripheral. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral to be enabled or disabled. -* Input 2 : NewState: specifies the status of the BSPI -* : NewState value must be either ENABLE or DISABLE: -* : ENABLE: the specified BSPI peripheral will be enabled. -* : DISABLE: the specified BSPI peripheral will be disabled. -* Output : BSPE bit in BSPCSR1. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_Enable( BSPI_TypeDef *BSPIx, FunctionalState NewState) -{ - if (NewState == ENABLE) BSPIx->CSR1 |= BSPI_PESET_Mask; - else BSPIx->CSR1 &= ~BSPI_PESET_Mask; -} - -/******************************************************************************* -* Function Name : BSPI_MasterEnable -* Description : Configures the BSPI as a Master or a Slave. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : NewState: specifies whether configuring BSPI as master is enabled or disabled. -* : ENABLE: the specified BSPI will be configured as a master. -* : DISABLE: the specified BSPI will be configured as a slave. -* Output : MSTR bit in BSPCSR1 is modified register. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_MasterEnable(BSPI_TypeDef *BSPIx, FunctionalState NewState) -{ - if (NewState == ENABLE) BSPIx->CSR1 |= 0x02; else BSPIx->CSR1 &= ~0x02; -} - -/******************************************************************************* -* Function Name : BSPI_TrItSrc. -* Description : Configures the transmit interrupt source. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : TrItSrc: specifies the transmit interrupt source. -* : Refer to the section Transmit Interrupt Sources for more details on the -* : allowed values of this parameter. -* Output : TIE bit in BSPCSR2 register. -* Return : None. -*******************************************************************************/ -void BSPI_TrItSrc(BSPI_TypeDef *BSPIx, BSPI_TR_IT_SRCS TrItSrc); - -/******************************************************************************* -* Function Name : BSPI_RcItSrc. -* Description : Configures the receive interrupt source. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : RcItSrc: specifies the source for the receive interrupt. -* : Refer to the section Receive Interrupt Sources for more details on the -* : allowed values of this parameter. -* Output : RIE bit in BSPCSR1 is register. -* Return : None. -*******************************************************************************/ -void BSPI_RcItSrc(BSPI_TypeDef *BSPIx, BSPI_RC_IR_SRCS RcItSrc); - -/******************************************************************************* -* Function Name : BSPI_TrFifoDepth -* Description : Configures BSPI transmission FIFO number of words. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI. -* Input 2 : TDepth:specifies the depth of the transmit FIFO. -* Output : TFE bit in BSPCSR2 register. -* Return : None. -*******************************************************************************/ -void BSPI_TrFifoDepth(BSPI_TypeDef *BSPIx, u8 TDepth); - -/******************************************************************************* -* Function Name : BSPI_RcFifoDepth -* Description : Configures BSPI reception FIFO number of words. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : RDepth:specifies the depth of the receive FIFO. -* Output : RFE bits [3:0] in BSPCSR1 register. -* Return : None. -*******************************************************************************/ -void BSPI_RcFifoDepth(BSPI_TypeDef *BSPIx, u8 RDepth); - -/******************************************************************************* -* Function Name : BSPI_8bLEn -* Description : Sets the word length of the receive FIFO and transmit data registers to either 8 or 16 bits. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI. -* Input 2 : status: specifies if the word length is 8 or 16 bits. -* : status value must be either ENABLE or DISABLE: -* : ENABLE: to enable setting the word length to 8 bits. -* : DISABLE: disables setting the word length to 8 bits: the wordlength will be configured to 16 bits. -* Output : WL bits in BSPCSR1 register. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_8bLEn(BSPI_TypeDef *BSPIx, FunctionalState NewState) -{ - if (NewState == DISABLE) BSPIx->CSR1 |= 0x0400; else BSPIx->CSR1 &= ~0x0C00; -} - -/******************************************************************************* -* Function Name : BSPI_ClkFEdge -* Description : Enables capturing the first data sample on the first edge of SCK or on the second edge. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : NewState: specifies whether capturing the first data sample on the first edge of SCK is enabled or disabled. -* : status value must be either ENABLE or DISABLE. -* :DISABLE: to enable capturing the first data sample on the first edge of SCK. -* : ENABLE: to enable capturing the first data sample on the second edge of SCK. -* Output : CPHA bits in BSPCSR1 register. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_ClkFEdge(BSPI_TypeDef *BSPIx, FunctionalState NewState) -{ - if (NewState == ENABLE) BSPIx->CSR1 |= BSPI_CPHA_Mask; - else BSPIx->CSR1&=~BSPI_CPHA_Mask; -} - -/******************************************************************************* -* Function Name : BSPI_ClkActiveHigh -* Description : Configures the clock to be active high or low. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : NewState: specifies whether the clock is active high or low. -* : status value must be ENABLE or DISABLE. -* : ENABLE: configures the clock to be active high. -* : DISABLE: confgures the clock to be active low. -* Output : CPOL bits in BSPCSR1 register. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_ClkActiveHigh(BSPI_TypeDef *BSPIx, FunctionalState NewState) -{ - if (NewState == ENABLE) BSPIx->CSR1 |= BSPI_CPOL_Mask; - else BSPIx->CSR1 &= ~BSPI_CPOL_Mask; -} - -/******************************************************************************* -* Function Name : BSPI_FifoDisable -* Description : Configure the BSPI FIFO. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Output : DFIFO bit in BSPCSR2 register. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_FifoDisable(BSPI_TypeDef *BSPIx) -{ - BSPIx->CSR2 |= 0x0001; -} - -/******************************************************************************* -* Function Name : BSPI_ClockDividerConfig -* Description : Configure BSPI clock divider -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI. -* Input 2 : Div: holds the value of the clock divider. -* Output : Div [7:0] bits in BSPCLK register. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_ClockDividerConfig(BSPI_TypeDef *BSPIx, u8 Div) -{ - BSPIx->CLK = Div; -} - -/******************************************************************************* -* Function Name : BSPI_FlagStatus. -* Description : Check whether the specified BSPI Flag is set or not. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : flag: specifies the flag to see the status. -* : Refer to the section BSPI Flags for more details on the allowed values of this parameter. -* Output : None. -* Return : FlagStatus type -* : SET: if the tested flag is set. -* : RESET: if the corresponding flag is reset. -*******************************************************************************/ -INLINE FlagStatus BSPI_FlagStatus(BSPI_TypeDef *BSPIx, BSPI_Flags flag) -{ - return (BSPIx->CSR2 & flag) != 0 ? SET : RESET; -} - -/******************************************************************************* -* Function Name : BSPI_WordSend. -* Description : Transmit a single Word. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : holds the word which will be transmitted. -* Output : BSPTXR register. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_WordSend(BSPI_TypeDef *BSPIx, u16 Data) -{ - if ((BSPIx->CSR1 & 0x0400) == 0) Data <<= 8; - BSPIx->TXR = Data; -} - -/******************************************************************************* -* Function Name : BSPI_BufferSend. -* Description : Transmits data from a buffer. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : PtrToBuffer is an u8 pointer to the first word of the buffer to be transmitted. -* Input 3 : NbOfWords parameter indicates the number of words saved in the buffer to be sent. -* Output : None. -* Return : None. -*******************************************************************************/ -void BSPI_BufferSend(BSPI_TypeDef *BSPIx, u8 *PtrToBuffer, u8 NbOfWords); - -/******************************************************************************* -* Function Name : BSPI_WordReceive. -* Description : Returns the recent received word. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Output : None. -* Return : The value of the received word. -*******************************************************************************/ -INLINE u16 BSPI_WordReceive(BSPI_TypeDef *BSPIx) -{ - return (BSPIx->CSR1 & 0x0400) == 0 ? BSPIx->RXR >> 8 : BSPIx->RXR; -} - -/******************************************************************************* -* Function Name : BSPI_BufferReceive. -* Description : Receives number of data words and stores them in user defined area. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : PtrToBuffer is an u8 pointer to the first word of the defined area to save the received buffer. -* Input 3 : NbOfWords parameter indicates the number of words to be received in the buffer. -* Output : None. -* Return : None. -*******************************************************************************/ -void BSPI_BufferReceive(BSPI_TypeDef *BSPIx, u8 *PtrToBuffer, u8 NbOfWords); - -/******************************************************************************* -* Function Name : BSPI_ItEnable. -* Description : Enable the specified interrupt. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : BSPI_IT: specifies the BSPI interrupt. -* : Refer to the section Interrupt Enable for more details on the allowed values of this parameter.. -* Input 3 : NewState: specified whether the BSPI interrupt is enabled or disabled. -* : status value must be either ENABLE or DISABLE. -* : ENABLE: to enable interrupt -* : DISABLE: to disable interrupt. -* Output : BSPCSR1 register. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_ItEnable(BSPI_TypeDef *BSPIx, BSPI_ITS BSPI_IE, FunctionalState NewState) -{ - if (NewState == ENABLE) BSPIx->CSR1 |= BSPI_IE; else BSPIx->CSR1 &= ~BSPI_IE; -} - -#endif /* __bspi_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/can.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/can.h deleted file mode 100644 index 7a97e2125..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/can.h +++ /dev/null @@ -1,404 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : can.h -* Author : MCD Application Team -* Date First Issued : 27/10/2003 -* Description : This file contains all the functions prototypes for the -* CAN bus software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __can_H -#define __can_H - -#include "71x_map.h" - -// Standard bitrates available -enum -{ - CAN_BITRATE_100K, - CAN_BITRATE_125K, - CAN_BITRATE_250K, - CAN_BITRATE_500K, - CAN_BITRATE_1M -}; - -// Control register -#define CAN_CR_TEST 0x0080 -#define CAN_CR_CCE 0x0040 -#define CAN_CR_DAR 0x0020 -#define CAN_CR_EIE 0x0008 -#define CAN_CR_SIE 0x0004 -#define CAN_CR_IE 0x0002 -#define CAN_CR_INIT 0x0001 - -// Status register -#define CAN_SR_LEC 0x0007 -#define CAN_SR_TXOK 0x0008 -#define CAN_SR_RXOK 0x0010 -#define CAN_SR_EPASS 0x0020 -#define CAN_SR_EWARN 0x0040 -#define CAN_SR_BOFF 0x0080 - -// Test register -#define CAN_TESTR_RX 0x0080 -#define CAN_TESTR_TX1 0x0040 -#define CAN_TESTR_TX0 0x0020 -#define CAN_TESTR_LBACK 0x0010 -#define CAN_TESTR_SILENT 0x0008 -#define CAN_TESTR_BASIC 0x0004 - -// IFn / Command Request register -#define CAN_CRR_BUSY 0x8000 - -// IFn / Command Mask register -#define CAN_CMR_WRRD 0x0080 -#define CAN_CMR_MASK 0x0040 -#define CAN_CMR_ARB 0x0020 -#define CAN_CMR_CONTROL 0x0010 -#define CAN_CMR_CLRINTPND 0x0008 -#define CAN_CMR_TXRQST 0x0004 -#define CAN_CMR_DATAA 0x0002 -#define CAN_CMR_DATAB 0x0001 - -// IFn / Mask 2 register -#define CAN_M2R_MXTD 0x8000 -#define CAN_M2R_MDIR 0x4000 - -// IFn / Arbitration 2 register -#define CAN_A2R_MSGVAL 0x8000 -#define CAN_A2R_XTD 0x4000 -#define CAN_A2R_DIR 0x2000 - -// IFn / Message Control register -#define CAN_MCR_NEWDAT 0x8000 -#define CAN_MCR_MSGLST 0x4000 -#define CAN_MCR_INTPND 0x2000 -#define CAN_MCR_UMASK 0x1000 -#define CAN_MCR_TXIE 0x0800 -#define CAN_MCR_RXIE 0x0400 -#define CAN_MCR_RMTEN 0x0200 -#define CAN_MCR_TXRQST 0x0100 -#define CAN_MCR_EOB 0x0080 - - -// Wake-up modes -enum -{ - CAN_WAKEUP_ON_EXT, - CAN_WAKEUP_ON_CAN -}; - - -// CAN message structure -typedef struct -{ - u32 IdType; - vu32 Id; - vu8 Dlc; - vu8 Data[8]; -} canmsg; - -// message ID types -enum -{ - CAN_STD_ID, - CAN_EXT_ID -}; - -// message ID limits -#define CAN_LAST_STD_ID ((1<<11) - 1) -#define CAN_LAST_EXT_ID ((1L<<29) - 1) - -/******************************************************************************* -* Function Name : CAN_EnterInitMode -* Description : Switch the CAN into initialization mode -* Input 1 : any binary value formed from the CAN_CR_xxx defines -* Output : None -* Return : None -* Note : CAN_LeaveInitMode must be called when all is done -*******************************************************************************/ -INLINE void CAN_EnterInitMode(u8 mask) -{ - CAN->CR = mask | CAN_CR_INIT; - CAN->SR = 0; // reset the status -} - -/******************************************************************************* -* Function Name : CAN_LeaveInitMode -* Description : Leave the initialization mode (switch into normal mode) -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -INLINE void CAN_LeaveInitMode(void) -{ - CAN->CR &= ~(CAN_CR_INIT | CAN_CR_CCE); -} - -/******************************************************************************* -* Function Name : CAN_EnterTestMode -* Description : Switch the CAN into test mode -* Input 1 : any binary value formed from the CAN_TESTR_xxx defines -* Output : None -* Return : None -* Note : CAN_LeaveTestMode must be called when all is done -*******************************************************************************/ -INLINE void CAN_EnterTestMode(u8 mask) -{ - CAN->CR |= CAN_CR_TEST; - CAN->TESTR |= mask; -} - -/******************************************************************************* -* Function Name : CAN_LeaveTestMode -* Description : Leave the current test mode (switch into normal mode) -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -INLINE void CAN_LeaveTestMode(void) -{ - CAN->CR |= CAN_CR_TEST; - CAN->TESTR &= ~(CAN_TESTR_LBACK | CAN_TESTR_SILENT | CAN_TESTR_BASIC); - CAN->CR &= ~CAN_CR_TEST; -} - -/******************************************************************************* -* Function Name : CAN_SetBitrate -* Description : Setup a standard CAN bitrate -* Input 1 : one of the CAN_BITRATE_xxx defines -* Output : None -* Return : None -* Note : CAN must be in initialization mode -*******************************************************************************/ -void CAN_SetBitrate(u32 bitrate); - -/******************************************************************************* -* Function Name : CAN_SetTiming -* Description : Setup the CAN timing with specific parameters -* Input 1 : Time Segment before the sample point position, from 1 to 16 -* Input 2 : Time Segment after the sample point position, from 1 to 8 -* Input 3 : Synchronisation Jump Width, from 1 to 4 -* Input 4 : Baud Rate Prescaler, from 1 to 1024 -* Output : None -* Return : None -* Note : CAN must be in initialization mode -*******************************************************************************/ -void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp); - -/******************************************************************************* -* Function Name : CAN_SleepRequest -* Description : Request the CAN cell to enter sleep mode -* Input 1 : CAN_WAKEUP_ON_EXT or CAN_WAKEUP_ON_CAN -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SleepRequest(u32 WakeupMode); - -/******************************************************************************* -* Function Name : CAN_SetUnusedMsgObj -* Description : Configure the message object as unused -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetUnusedMsgObj(u32 msgobj); - -/******************************************************************************* -* Function Name : CAN_SetTxMsgObj -* Description : Configure the message object as TX -* Input 1 : message object number, from 0 to 31 -* Input 2 : CAN_STD_ID or CAN_EXT_ID -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetTxMsgObj(u32 msgobj, u32 idType); - -/******************************************************************************* -* Function Name : CAN_SetRxMsgObj -* Description : Configure the message object as RX -* Input 1 : message object number, from 0 to 31 -* Input 2 : CAN_STD_ID or CAN_EXT_ID -* Input 3 : low part of the identifier range used for acceptance filtering -* Input 4 : high part of the identifier range used for acceptance filtering -* Input 5 : TRUE for a single receive object or a FIFO receive object that -* is the last one of the FIFO -* FALSE for a FIFO receive object that is not the last one -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast); - -/******************************************************************************* -* Function Name : CAN_InvalidateAllMsgObj -* Description : Configure all the message objects as unused -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_InvalidateAllMsgObj(void); - -/******************************************************************************* -* Function Name : CAN_Init -* Description : Initialize the CAN cell and set the bitrate -* Input 1 : any binary value formed from the CAN_CTL_xxx defines -* Input 2 : one of the CAN_BITRATE_xxx defines -* Output : None -* Return : None -*******************************************************************************/ -void CAN_Init(u8 mask, u32 bitrate); - -/******************************************************************************* -* Function Name : CAN_ReleaseMessage -* Description : Release the message object -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -*******************************************************************************/ -void CAN_ReleaseMessage(u32 msgobj); - -/******************************************************************************* -* Function Name : CAN_ReleaseTxMessage -* Description : Release the transmit message object -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -* Note : assume that message interface 0 is free -*******************************************************************************/ -INLINE void CAN_ReleaseTxMessage(u32 msgobj) -{ - CAN->sMsgObj[0].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQST; - CAN->sMsgObj[0].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_ReleaseRxMessage -* Description : Release the receive message object -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -* Note : assume that message interface 1 is free -*******************************************************************************/ -INLINE void CAN_ReleaseRxMessage(u32 msgobj) -{ - CAN->sMsgObj[1].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQST; - CAN->sMsgObj[1].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_SendMessage -* Description : Start transmission of a message -* Input 1 : message object number, from 0 to 31 -* Input 2 : pointer to the message structure containing data to transmit -* Output : None -* Return : 1 if transmission was OK, else 0 -*******************************************************************************/ -u32 CAN_SendMessage(u32 msgobj, canmsg* pCanMsg); - -/******************************************************************************* -* Function Name : CAN_ReceiveMessage -* Description : Get the message, if received -* Input 1 : message object number, from 0 to 31 -* Input 2 : if TRUE, the message object is released when getting the data -* if FALSE, the message object is not released -* Input 3 : pointer to the message structure where received data is stored -* Output : None -* Return : 1 if reception was OK, else 0 (no message pending) -*******************************************************************************/ -u32 CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg); - -/******************************************************************************* -* Function Name : CAN_WaitEndOfTx -* Description : Wait until current transmission is finished -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_WaitEndOfTx(void); - -/******************************************************************************* -* Function Name : CAN_BasicSendMessage -* Description : Start transmission of a message in BASIC mode -* Input 1 : pointer to the message structure containing data to transmit -* Output : None -* Return : 1 if transmission was OK, else 0 -* Note : CAN must be in BASIC mode -*******************************************************************************/ -u32 CAN_BasicSendMessage(canmsg* pCanMsg); - -/******************************************************************************* -* Function Name : CAN_BasicReceiveMessage -* Description : Get the message in BASIC mode, if received -* Input 1 : pointer to the message structure where received data is stored -* Output : None -* Return : 1 if reception was OK, else 0 (no message pending) -* Note : CAN must be in BASIC mode -*******************************************************************************/ -u32 CAN_BasicReceiveMessage(canmsg* pCanMsg); - -/******************************************************************************* -* Function Name : CAN_IsMessageWaiting -* Description : Test the waiting status of a received message -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : A non-zero value if the corresponding message object has -* received a message waiting to be copied, else 0 -*******************************************************************************/ -INLINE u32 CAN_IsMessageWaiting(u32 msgobj) -{ - return (msgobj < 16 ? CAN->ND1R & (1 << msgobj) : CAN->ND2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsTransmitRequested -* Description : Test the request status of a transmitted message -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : A non-zero value if the corresponding message is requested -* to transmit, else 0 -*******************************************************************************/ -INLINE u32 CAN_IsTransmitRequested(u32 msgobj) -{ - return (msgobj < 16 ? CAN->TR1R & (1 << msgobj) : CAN->TR2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsInterruptPending -* Description : Test the interrupt status of a message object -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : A non-zero value if the corresponding message has an interrupt -* pending, else 0 -*******************************************************************************/ -INLINE u32 CAN_IsInterruptPending(u32 msgobj) -{ - return (msgobj < 16 ? CAN->IP1R & (1 << msgobj) : CAN->IP2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsObjectValid -* Description : Test the validity of a message object (ready to use) -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : A non-zero value if the corresponding message object is valid, -* else 0 -*******************************************************************************/ -INLINE u32 CAN_IsObjectValid(u32 msgobj) -{ - return (msgobj < 16 ? CAN->MV1R & (1 << msgobj) : CAN->MV2R & (1 << (msgobj-16))); -} - -#endif /* __can_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/eic.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/eic.h deleted file mode 100644 index ee691d95a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/eic.h +++ /dev/null @@ -1,200 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : eic.h -* Author : MCD Application Team -* Date First Issued : 25/06/2003 -* Description : This file contains all the functions prototypes for the -* EIC software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __eic_H -#define __eic_H - -#include "71x_map.h" - -typedef enum -{ - T0TIMI_IRQChannel = 0, - FLASH_IRQChannel = 1, - RCCU_IRQChannel = 2, - RTC_IRQChannel = 3, - WDG_IRQChannel = 4, - XTI_IRQChannel = 5, - USBHP_IRQChannel = 6, - I2C0ITERR_IRQChannel = 7, - I2C1ITERR_IRQChannel = 8, - UART0_IRQChannel = 9, - UART1_IRQChannel = 10, - UART2_IRQChannel = 11, - UART3_IRQChannel = 12, - SPI0_IRQChannel = 13, - SPI1_IRQChannel = 14, - I2C0_IRQChannel = 15, - I2C1_IRQChannel = 16, - CAN_IRQChannel = 17, - ADC_IRQChannel = 18, - T1TIMI_IRQChannel = 19, - T2TIMI_IRQChannel = 20, - T3TIMI_IRQChannel = 21, - HDLC_IRQChannel = 25, - USBLP_IRQChannel = 26, - T0TOI_IRQChannel = 29, - T0OC1_IRQChannel = 30, - T0OC2_IRQChannel = 31 -} IRQChannel_TypeDef; - -typedef enum -{ - T0TIMI_FIQChannel = 0x00000001, - WDG_FIQChannel = 0x00000002, - WDGT0TIMI_FIQChannels = 0x00000003 -} FIQChannel_TypeDef; - -/******************************************************************************* -* Function Name : EIC_Init -* Description : Initialise the EIC using the load PC instruction -* (PC = PC +offset) -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void EIC_Init(void); - -/******************************************************************************* -* Function Name : EIC_IRQConfig -* Description : Enable or Disable IRQ interrupts -* Input 1 : New status : can be ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -INLINE void EIC_IRQConfig(FunctionalState NewState) -{ - if (NewState==ENABLE) EIC->ICR |= 0x0001; else EIC->ICR &= ~0x0001; -} - -/******************************************************************************* -* Function Name : EIC_FIQConfig -* Description : Enable or Disable FIQ interrupts -* Input 1 : New status : can be ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -INLINE void EIC_FIQConfig(FunctionalState NewState) -{ - if (NewState==ENABLE) EIC->ICR |= 0x0002; else EIC->ICR &= ~0x0002; -} - -/******************************************************************************* -* Function Name : EIC_IRQChannelConfig -* Description : Configure the IRQ Channel -* Input 1 : IRQ channel name -* Input 2 : Channel New status : can be ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -INLINE void EIC_IRQChannelConfig(IRQChannel_TypeDef IRQChannel, FunctionalState NewState) -{ - if (NewState==ENABLE) EIC->IER |= 0x0001 << IRQChannel; - else EIC->IER &= ~(0x0001 << IRQChannel); -} - -/******************************************************************************* -* Function Name : EIC_FIQChannelConfig -* Description : Configure the FIQ Channel -* Input 1 : FIQ channel name -* Input 2 : Channel New status : can be ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -INLINE void EIC_FIQChannelConfig(FIQChannel_TypeDef FIQChannel, - FunctionalState NewState) -{ - if (NewState==ENABLE) EIC->FIR |= FIQChannel; - else EIC->FIR &= ~FIQChannel; -} - -/******************************************************************************* -* Function Name : EIC_IRQChannelPriorityConfig -* Description : Configure the selected IRQ channel priority -* Input 1 : IRQ channel name -* Input 2 : IRQ channel priority -* Output : None -* Return : None -*******************************************************************************/ -INLINE void EIC_IRQChannelPriorityConfig(IRQChannel_TypeDef IRQChannel, u8 Priority) -{ - EIC->SIR[IRQChannel] = (EIC->SIR[IRQChannel]&0xFFFF0000) | (u16)Priority & 0x000F; -} - -/******************************************************************************* -* Function Name : EIC_CurrentPriorityLevelConfig -* Description : Change the current priority level of the srved IRQ routine -* Input 1 : New priority -* Output : None -* Return : None -*******************************************************************************/ -void EIC_CurrentPriorityLevelConfig(u8 NewPriorityLevel); - -/******************************************************************************* -* Function Name : EIC_CurrentPriorityLevelValue -* Description : Return the current priority level of the current served IRQ -* routine -* Input : None -* Output : None -* Return : The current priority level -*******************************************************************************/ -INLINE u8 EIC_CurrentPriorityLevelValue(void) -{ - return EIC->CIPR & 0xF; -} - -/******************************************************************************* -* Function Name : EIC_CurrentIRQChannelValue -* Description : Return the current served IRQ channel number -* Input 0 : None -* Output : None -* Return : The current served IRQ channel number -*******************************************************************************/ -INLINE IRQChannel_TypeDef EIC_CurrentIRQChannelValue(void) -{ - return (IRQChannel_TypeDef)(EIC->CICR & 0x1F); -} - -/******************************************************************************* -* Function Name : EIC_CurrentFIQChannelValue -* Description : Return the current served FIQ channel number -* Input : None -* Output : None -* Return : The current served FIQ channel number -*******************************************************************************/ -INLINE FIQChannel_TypeDef EIC_CurrentFIQChannelValue(void) -{ - return (FIQChannel_TypeDef)((EIC->FIR >> 2) & 0x0003); -} - -/******************************************************************************* -* Function Name : EIC_FIPendingBitClear -* Description : Clear the FIQ pending bit -* Input 1 : FIQ channel -* Output : None -* Return : None -*******************************************************************************/ -INLINE void EIC_FIQPendingBitClear(FIQChannel_TypeDef FIQChannel) -{ - EIC->FIR = (EIC->FIR & 0x0003) | (FIQChannel << 2); -} - -#endif /* __eic_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/emi.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/emi.h deleted file mode 100644 index 97c5115c9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/emi.h +++ /dev/null @@ -1,52 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : emi.h -* Author : MCD Application Team -* Date First Issued : 08/08/2003 -* Description : This file contains all the functions prototypes for the -* EMI software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef _EMI_H -#define _EMI_H - -#include "71x_map.h" - -#define EMI_ENABLE 0x8000 -#define EMI_DISABLE 0x0000 -#define EMI_WAITSTATE(n) ((n) << 2) -#define EMI_SIZE_8 0x0000 -#define EMI_SIZE_16 0x0001 - -#define EMI_BANK0 EXTMEM_BASE -#define EMI_BANK1 (EXTMEM_BASE + 0x2000000) -#define EMI_BANK2 (EXTMEM_BASE + 0x4000000) - -/******************************************************************************* -* Function Name : EMI_Config -* Description : This routine is used, for each bank, to configure enabling, -* : cycle length and bus size. -* Input : Bank (u8) -* : Config (u16) -* Return : None -*******************************************************************************/ -INLINE void EMI_Config(u8 Bank, u16 Config) -{ - *(u16 *)(EMI_BASE + (4*Bank)) = Config; -} - -#endif // _EMI_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/flash.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/flash.h deleted file mode 100644 index 6d6bb09d6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/flash.h +++ /dev/null @@ -1,253 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : flash.h -* Author : MCD Application Team -* Date First Issued : 28/07/2003 -* Description : This file contains all the functions prototypes for the -* Embedded Flash software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __FLASH_H -#define __FLASH_H - -#include "71x_map.h" - -#define FLASH_B0F0 0x00000001 -#define FLASH_B0F1 0x00000002 -#define FLASH_B0F2 0x00000004 -#define FLASH_B0F3 0x00000008 -#define FLASH_B0F4 0x00000010 -#define FLASH_B0F5 0x00000020 -#define FLASH_B0F6 0x00000040 -#define FLASH_B0F7 0x00000080 - -#define FLASH_B1F0 0x00010000 -#define FLASH_B1F1 0x00020000 - -#define FLASH_B0 (FLASH_B0F0 | FLASH_B0F1 | FLASH_B0F2 | FLASH_B0F3 | FLASH_B0F4 | FLASH_B0F5 | FLASH_B0F6 | FLASH_B0F7) -#define FLASH_B1 (FLASH_B1F0 | FLASH_B1F1) - -typedef enum -{ - FLASH_FINISHED, - FLASH_ONGOING -} flashwriteoperation; - -typedef enum -{ - FLASH_BANK0 = 0x1000000, - FLASH_BANK1 = 0x2000000 -} flashbanks; - -typedef enum -{ - FLASH_BSYA0 = 0x01, /* 000-00001 = 0000 0001 = 0x01 */ /* FLASH_CR0.1 */ - FLASH_BSYA1 = 0x02, /* 000-00010 = 0000 0010 = 0x02 */ /* FLASH_CR0.2 */ - FLASH_LOCK = 0x04, /* 000-00100 = 0000 0100 = 0x04 */ /* FLASH_CR0.4*/ - FLASH_INTP = 0x14, /* 000-10100 = 0001 0100 = 0x14 */ /* FLASH_CR0.20 */ - FLASH_B0S = 0x38, /* 001-11000 = 0011 1000 = 0x38 */ /* FLASH_CR1.24*/ - FLASH_B1S = 0x39, /* 001-11001 = 0011 1001 = 0x39 */ /* FLASH_CR1.25*/ - FLASH_ERR = 0xA0, /* 101-00000 = 1010 0000 = 0xA0 */ /* FLASH_ER.0*/ - FLASH_ERER = 0xA1, /* 101-00001 = 1010 0001 = 0xA1 */ /* FLASH_ER.1*/ - FLASH_PGER = 0xA2, /* 101-00010 = 1010 0010 = 0xA2 */ /* FLASH_ER.2*/ - FLASH_10ER = 0xA3, /* 101-00011 = 1010 0011 = 0xA3 */ /* FLASH_ER.3*/ - FLASH_SEQER = 0xA6, /* 101-00110 = 1010 0110 = 0xA6 */ /* FLASH_ER.6*/ - FLASH_RESER = 0xA7, /* 101-00111 = 1010 0111 = 0xA7 */ /* FLASH_ER.7*/ - FLASH_WPF = 0xA8 /* 101-01000 = 1010 1000 = 0xA8 */ /* FLASH_ER.8*/ -} flashflags; - -#define FLASH_WMS_Mask 0x80000000 -#define FLASH_SUSP_Mask 0x40000000 -#define FLASH_WPG_Mask 0x20000000 -#define FLASH_DWPG_Mask 0x10000000 -#define FLASH_SER_Mask 0x08000000 -#define FLASH_SPR_Mask 0x01000000 -#define FLASH_BER_Mask 0x04000000 -#define FLASH_MER_Mask 0x02000000 -#define FLASH_BSYA1_Mask 0x00000002 -#define FLASH_BSYA2_Mask 0x00000004 - -#define FLASH_DBGP_Mask 0x00000002 -#define FLASH_ACCP_Mask 0x00000001 - -#define FLASH_Reg_Mask 0xE0 -#define FLASH_Flag_Mask 0x1F - -#define FLASH_INTM_Mask 0x00200000 -#define FLASH_INTP_Mask 0x00100000 - -/******************************************************************************* -* Function Name : FLASH_Init -* Description : Initialise the Flash -* Input : None -* Return : None -*******************************************************************************/ -void FLASH_Init(void); - -/******************************************************************************* -* Function Name : FLASH_FlagStatus -* Description : Returns the NewState of Flash flags -* Input 1 : Flash Flag -* Return : flagstate -*******************************************************************************/ -FlagStatus FLASH_FlagStatus(flashflags Xflag); - -/******************************************************************************* -* Function Name : FLASH_WriteOpStatus -* Description : Checks the write operation status -* Input 1 : flash banck -* Return : write operation status -*******************************************************************************/ -INLINE FlagStatus FLASH_WriteOpStatus(flashbanks Xbank) -{ - return Xbank == FLASH_BANK0 ? FLASH_FlagStatus(FLASH_BSYA0) : FLASH_FlagStatus(FLASH_BSYA1); -} - -/******************************************************************************* -* Function Name : FLASH_WordWrite -* Description : Writes a Word to the Flash -* Input 1 : Address of the Destination -* Input 2 : Word to program -* Return : None -*******************************************************************************/ -void FLASH_WordWrite(u32 TargetAdd, u32 Data); - -/******************************************************************************* -* Function Name : FLASH_DWordWrite -* Description : Writes Double Word to the Flash -* Input 1 : Address of the Destination -* Input 2 : Word 1 To program -* Input 3 : Word 2 To program -* Return : None -*******************************************************************************/ -void FLASH_DWordWrite(u32 TargetAdd, u32 Data0, u32 Data1); - -/******************************************************************************* -* Function Name : FLASH_EraseSector -* Description : Erases a Flash sector -* Input 1 : Sectors to be Erased -* Return : None -*******************************************************************************/ -void FLASH_SectorErase(u32 Xsectors); - -/******************************************************************************* -* Function Name : FLASH_BankErase -* Description : Erases a Bank of the Flash -* Input 1 : Bank to be Erased -* Return : None -*******************************************************************************/ -INLINE void FLASH_BankErase(flashbanks Xbank) -{ - FLASH_SectorErase(Xbank == FLASH_BANK0 ? FLASH_B0 : FLASH_B1); -} -/******************************************************************************* -* Function Name : FLASH_Suspend -* Description : Suspends the current program or erase operation -* Input 1 : None -* Return : Flash CR0 register -*******************************************************************************/ -u32 FLASH_Suspend(void); - -/******************************************************************************* -* Function Name : FLASH_Resume -* Description : Resume a Suspended program or erase operation -* Input 1 : The operation to be resumed -* Return : None -*******************************************************************************/ -void FLASH_Resume(u32 FLASH_LastOperation); - -/******************************************************************************* -* Function Name : FLASH_WordRead -* Description : Read a single word of the flash -* Input 1 : Source Address -* Return : Word -*******************************************************************************/ -u32 FLASH_WordRead(u32 FLASH_SourceAdd); -/******************************************************************************* -* Function Name : FLASH_WritePrConfig -* Description : Configures The Write Protection Bits -* Input 1 : Flash Bank -* Input 2 : Enable or disable Protection -* Return : None -*******************************************************************************/ -void FLASH_WritePrConfig(u32 Xsectors, FunctionalState NewState); -/******************************************************************************* -* Function Name : FLASH_PermanantDebugPrConfig -* Description : Configures The Debug Protection Bits -* Input 1 : ENABLE or DISABLE -* Return : None -*******************************************************************************/ -void FLASH_PermanantDebugPrConfig(FunctionalState NewState); - -/******************************************************************************* -* Function Name : FLASH_FlagClear -* Description : Clears a flash flag -* Input 1 : Flash Flag -* Return : None -*******************************************************************************/ -void FLASH_FlagClear(flashflags Xflag); - -/******************************************************************************* -* Function Name : FLASH_ITConfig -* Description : Enables Or Disables the write-end interrupt -* Input 1 : FunctionalState(Enable, Disable) -* Return : None -*******************************************************************************/ -INLINE void FLASH_ITConfig(FunctionalState NewState) -{ - if (NewState == ENABLE) FLASHR->CR0 |= FLASH_INTM_Mask; - else FLASHR->CR0 &= ~FLASH_INTM_Mask; -} - -/******************************************************************************* -* Function Name : FLASH_ITStatus -* Description : Checks if the write-end interrupt is enabled or not -* Input 1 : None -* Return : Enable, Disable -*******************************************************************************/ -INLINE FunctionalState FLASH_ITStatus(void) -{ - return (FLASHR->CR0 & FLASH_INTM_Mask)==0 ? DISABLE : ENABLE; -} - -/******************************************************************************* -* Function Name : FLASH_ITClear -* Description : Clears an interrupt pending flag -* Input 1 : None -* Return : None -*******************************************************************************/ -INLINE void FLASH_ITClear(void) -{ - FLASHR->CR0 &= ~FLASH_INTM_Mask; -} - -/******************************************************************************* -* Function Name : FLASH_ProtectionLevel -* Description : Gives the level of protection in the PDS PEN registers -* Input 1 : None -* Return : The last bit not yet reset -*******************************************************************************/ -u16 FLASH_ProtectionLevel(void); - -/******************************************************************************* -* Function Name : FLASH_WaitForLastTask -* Description : Waits for the end of last task on a Flash Bank -* Input 1 : None -* Return : Nones -*******************************************************************************/ -void FLASH_WaitForLastTask(void); - -#endif // __FLASH_H - -/*******************(C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/gpio.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/gpio.h deleted file mode 100644 index 8b3f9d38d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/gpio.h +++ /dev/null @@ -1,127 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : gpio.h -* Author : MCD Application Team -* Date First Issued : 08/06/2003 -* Description : This file contains all the functions prototypes for the -* GPIO software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __gpio_H -#define __gpio_H - -#include "71x_map.h" - -typedef enum -{ - GPIO_HI_AIN_TRI, - GPIO_IN_TRI_TTL, - GPIO_IN_TRI_CMOS, - GPIO_IPUPD_WP, - GPIO_OUT_OD, - GPIO_OUT_PP, - GPIO_AF_OD, - GPIO_AF_PP -} GpioPinMode_TypeDef; - -#define GPIO_LSB 0x00 -#define GPIO_MSB 0x08 - -/******************************************************************************* -* Function Name : GPIO_Config -* Description : Configure the GPIO port pins -* Input 1 : GPIOx (x can be 0,1 or 2) the desired port -* Input 2 : Port_Pins : pins placements -* Input 3 : Pins Mode -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_Config (GPIO_TypeDef *GPIOx, u16 Port_Pins, GpioPinMode_TypeDef GPIO_Mode); - -/******************************************************************************* -* Function Name : GPIO_BitRead -* Description : Read the desired port pin value -* Input 1 : Selected GPIO port -* Input 2 : Pin number -* Output : None -* Return : The selected pin value -*******************************************************************************/ -INLINE u8 GPIO_BitRead(GPIO_TypeDef *GPIOx, u8 Port_Pin) -{ - return (GPIOx->PD >> Port_Pin) & 0x0001; -} - -/******************************************************************************* -* Function Name : GPIO_ByteRead -* Description : Read the desired port Byte value -* Input 1 : Selected GPIO port -* Input 2 : GPIO_MSB or GPIO_LSB -* Output : None -* Return : The GPIO_MSB or GPIO_LSB of the selected PD register -*******************************************************************************/ -INLINE u8 GPIO_ByteRead(GPIO_TypeDef *GPIOx, u8 Port_Byte) -{ - return (u8)(GPIOx->PD >> Port_Byte); -} - -/******************************************************************************* -* Function Name : GPIO_WordRead -* Description : Read the desired port word value -* Input 1 : Selected GPIO port -* Output : None -* Return : The selected PD register value -*******************************************************************************/ -INLINE u16 GPIO_WordRead(GPIO_TypeDef *GPIOx) -{ - return GPIOx->PD; -} - -/******************************************************************************* -* Function Name : GPIO_BitWrite -* Description : Set or reset the selected port pin -* Input 1 : Selected GPIO port -* Input 2 : Pin number -* Input 3 : bit value -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_BitWrite(GPIO_TypeDef *GPIOx, u8 Port_Pin, u8 Port_Val); - -/******************************************************************************* -* Function Name : GPIO_ByteWrite -* Description : Write byte value to the selected PD register -* Input 1 : Selected GPIO port -* Input 2 : GPIO_MSB or GPIO_LSB -* Input 3 : Byte value -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_ByteWrite(GPIO_TypeDef *GPIOx, u8 Port_Byte, u8 Port_Val); - -/******************************************************************************* -* Function Name : GPIO_WordWrite -* Description : Write word value to the selected PD register -* Input 1 : Selected GPIO port -* Input 2 : Value -* Output : None -* Return : None -*******************************************************************************/ -INLINE void GPIO_WordWrite(GPIO_TypeDef *GPIOx, u16 Port_Val) -{ - GPIOx->PD = Port_Val; -} - -#endif /* __gpio_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/i2c.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/i2c.h deleted file mode 100644 index a4f98fbd8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/i2c.h +++ /dev/null @@ -1,357 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : i2c.h -* Author : MCD Application Team -* Date First Issued : 05/09/2003 -* Description : This file provides prototypes of I2C functions -* and variable used in code sources -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __i2c_H -#define __i2c_H - -#include "71x_map.h" - -typedef enum -{ - I2C_CR = 0x00, - I2C_SR1 = 0x04, - I2C_SR2 = 0x08, - I2C_CCR = 0x0C, - I2C_OAR1 = 0x10, - I2C_OAR2 = 0x14, - I2C_DR = 0x18, - I2C_ECCR = 0x1C -} I2C_Registers; - -typedef enum -{ - I2C_Mode10, - I2C_Mode7 -} I2C_Addressing; - -typedef enum -{ - I2C_RX, - I2C_TX -} I2C_Direction; - -typedef enum -{ - I2C_SB = 0x00001, - I2C_M_SL = 0x00002, - I2C_ADSL = 0x00004, - I2C_BTF = 0x00008, - I2C_BUSY = 0x00010, - I2C_TRA = 0x00020, - I2C_ADD10 = 0x00040, - I2C_EVF = 0x00080, - I2C_GCAL = 0x00100, - I2C_BERR = 0x00200, - I2C_ARLO = 0x00400, - I2C_STOPF = 0x00800, - I2C_AF = 0x01000, - I2C_ENDAD = 0x02000, - I2C_STOP = 0x08000, - I2C_ACK = 0x10000, - I2C_START = 0x20000 -} I2C_Flags; - -typedef enum -{ - I2C_TX_NO, - I2C_TX_SB, - I2C_TX_AF, - I2C_TX_ARLO, - I2C_TX_BERR, - I2C_TX_ADD_OK, - I2C_TX_DATA_OK, - I2C_TX_ONGOING -} I2C_Tx_Status; - -typedef enum -{ - I2C_RX_NO, - I2C_RX_SB, - I2C_RX_AF, - I2C_RX_ARLO, - I2C_RX_BERR, - I2C_RX_ADD_OK, - I2C_RX_DATA_OK, - I2C_RX_ONGOING -} I2C_Rx_Status; - -#define I2C_PESET_Mask 0x20 -#define I2C_PERESET 0xDF -#define I2C_ENGC_Mask 0x10 -#define I2C_START_Mask 0x08 -#define I2C_STOP_Mask 0x02 -#define I2C_ACK_Mask 0x04 -#define I2C_ITE_Mask 0x01 - -/******************************************************************************* -* Function Name : I2C_Init -* Description : Initializes I2C peripheral control and registers to their -* default reset values. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : None. -*******************************************************************************/ -void I2C_Init (I2C_TypeDef *I2Cx); - -/******************************************************************************* -* Function Name : I2C_OnOffConfig -* Description : Enables or disables I2C peripheral. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -void I2C_OnOffConfig (I2C_TypeDef *I2Cx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : I2C_GeneralCallConfig -* Description : Enables or disables I2C general call option. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -INLINE void I2C_GeneralCallConfig (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) I2Cx->CR |= I2C_ENGC_Mask; - else I2Cx->CR &= ~I2C_ENGC_Mask; -} - -/******************************************************************************* -* Function Name : I2C_STARTGenerate -* Description : Generates I2C communication START condition. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -INLINE void I2C_STARTGenerate (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) I2Cx->CR |= I2C_START_Mask; - else I2Cx->CR &= ~I2C_START_Mask; -} - -/******************************************************************************* -* Function Name : I2C_STOPGenerate -* Description : Generates I2C communication STOP condition. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -INLINE void I2C_STOPGenerate (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) I2Cx->CR |= I2C_STOP_Mask; - else I2Cx->CR &= ~I2C_STOP_Mask; -} - -/******************************************************************************* -* Function Name : I2C_AcknowledgeConfig -* Description : Enables or disables I2C acknowledge feature. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -INLINE void I2C_AcknowledgeConfig (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) I2Cx->CR |= I2C_ACK_Mask; - else I2Cx->CR &= ~I2C_ACK_Mask; -} - -/******************************************************************************* -* Function Name : I2C_ITConfig -* Description : Enables or disables I2C interrupt feature. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -INLINE void I2C_ITConfig (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) I2Cx->CR |= I2C_ITE_Mask; - else I2Cx->CR &= ~I2C_ITE_Mask; -} - -/******************************************************************************* -* Function Name : I2C_RegisterRead -* Description : Reads any I2C register and returns its value. -* Input : I2Cx ( I2C0 or I2C1 ) -* Reg :the register to be read (I2CCR,I2CSR1,I2CSR2,I2CCCR, -* I2COAR1,I2COAR2,I2CDR,I2CECCR) -* Return : the value of the register passed as parameter(u8) -*******************************************************************************/ -INLINE u8 I2C_RegisterRead (I2C_TypeDef *I2Cx, I2C_Registers reg) -{ - return (*(u8 *)(*((u32 *)&I2Cx) + reg)); -} - -/******************************************************************************* -* Function Name : I2C_FlagStatus -* Description : Checks whether any I2C Flag is set or not. -* Input : I2Cx ( I2C0 or I2C1 ) -* Access(DIRECT or INDIRECT) -* Flag : the flag to be read -* input 4: an (u8) variable needed in the case -* of the INDIRECT access -* Return : the NewState of the Flag (SET or RESET). -*******************************************************************************/ -FlagStatus I2C_FlagStatus (I2C_TypeDef *I2Cx, RegisterAccess Access, I2C_Flags Flag,...); - -/******************************************************************************* -* Function Name : I2C_FlagClear -* Description : Clears the I2C Flag passed as a parameter -* Input : I2Cx ( I2C0 or I2C1 ) -* Flag : the flag to be read -* input3: an (u8) parameter needed in the case that the flag -* to be cleared need a write in one register -* Return : None. -*******************************************************************************/ -void I2C_FlagClear (I2C_TypeDef *I2Cx, I2C_Flags Flag,...); - -/******************************************************************************* -* Function Name : I2C_SpeedConfig -* Description : Selects I2C clock speed and configures its corresponding mode. -* Input : I2Cx ( I2C0 or I2C1 ) -* Clock: I2C expected clock in Hertz. -* Return : None. -*******************************************************************************/ -void I2C_SpeedConfig (I2C_TypeDef *I2Cx, u32 Clock); - -/******************************************************************************* -* Function Name : I2C_AddressConfig -* Description : Defines the I2C bus address of the interface. -* Input : I2Cx ( I2C0 or I2C1 ). -* Address: an u16 parameter indicating the address -* of the interface. -* Mode (I2C_Mode10,I2C_Mode7). -* Return : None. -*******************************************************************************/ -void I2C_AddressConfig (I2C_TypeDef *I2Cx, u16 Address, I2C_Addressing Mode); - -/******************************************************************************* -* Function Name : I2C_FCLKConfig -* Description : Configures frequency bits according to RCLK frequency. -* the I2C selected must be disabled -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : None. -*******************************************************************************/ -void I2C_FCLKConfig (I2C_TypeDef *I2Cx); - -/******************************************************************************* -* Function Name : I2C_AddressSend -* Description : Transmits the address byte to select the slave device. -* Input : I2Cx ( I2C0 or I2C1 ) -* Address: an u16 parameter indicating the slave address -* Mode (I2C_Mode10,I2C_Mode7). -* Direction (I2C_RX,I2C_TX). -* Return : None. -********************************************************************************/ -void I2C_AddressSend (I2C_TypeDef *I2Cx, u16 Address, I2C_Addressing Mode, I2C_Direction Direction); - -/******************************************************************************* -* Function Name : I2C_ByteSend -* Description : Send a single byte of data. -* Input : I2Cx ( I2C0 or I2C1 ) -* Data : the byte to be sent to the slave -* Return : None. -*******************************************************************************/ -void I2C_ByteSend (I2C_TypeDef *I2Cx, u8 Data); - -/******************************************************************************* -* Function Name : I2C_BufferSend -* Description : Send data from a buffer whose number of bytes is known -* Input : I2Cx ( I2C0 or I2C1 ) -* PtrToBuffer :pointer to the byte of buffer to be transmitted. -* NbOfBytes:Number of byte of the buffer -* Return : I2C_Tx_Status :transmission status (I2C_TX_AF, I2C_TX_ARLO, -* I2C_TX_BERR,I2C_TX_DATA_OK) -*******************************************************************************/ -I2C_Tx_Status I2C_BufferSend (I2C_TypeDef *I2Cx, u8 *PtrToBuffer, u8 NbOfBytes); - -/******************************************************************************* -* Function Name : I2C_StringSend -* Description : Send data from a buffer -* Input : I2Cx ( I2C0 or I2C1 ) -* PtrToString :pointer to the string to be transmitted. -* Return : I2C_Tx_Status :transmission status (I2C_TX_AF, I2C_TX_ARLO, -* I2C_TX_BERR,I2C_TX_DATA_OK) -*******************************************************************************/ -I2C_Tx_Status I2C_StringSend (I2C_TypeDef *I2Cx, char *PtrToString); - -/******************************************************************************* -* Function Name : I2C_TransmissionStatus -* Description : Report the NewState of the transmission -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : I2C_Tx_Status :transmission status (I2C_TX_NO, I2C_TX_SB, -* I2C_TX_AF, I2C_TX_ARLO, I2C_TX_BERR,I2C_TX_ADD_OK, -* I2C_TX_DATA_OK,I2C_TX_ONGOING) -*******************************************************************************/ -I2C_Tx_Status I2C_TransmissionStatus (I2C_TypeDef *I2Cx); - -/******************************************************************************* -* Function Name : I2C_ByteReceive -* Description : Returns the received byte. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : the byte received -*******************************************************************************/ -u8 I2C_ByteReceive (I2C_TypeDef *I2Cx); - -/******************************************************************************* -* Function Name : I2C_BufferReceive -* Description : received a buffer. and return the status of error. -* Input : I2Cx ( I2C0 or I2C1 ) -* PtrToBuffer :pointer to the byte of buffer received. -* NbOfBytes:Number of byte to be received -* Return : I2C_Rx_Status:the NewState of the reception (,I2C_RX_AF, -* I2C_RX_ARLO,I2C_RX_BERR, I2C_RX_DATA_OK) -*******************************************************************************/ -I2C_Rx_Status I2C_BufferReceive (I2C_TypeDef *I2Cx, u8 *PtrToBuffer, u8 NbOfBytes); - -/******************************************************************************* -* Function Name :I2C_ReceptionStatus -* Description : Report the reception NewState. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : I2C_Rx_Status:the NewState of the reception ( I2C_RX_NO, -* I2C_RX_SB,I2C_RX_AF,I2C_RX_ARLO,I2C_RX_BERR,I2C_RX_ADD_OK, -* I2C_RX_DATA_OK, I2C_RX_ONGOING) -*******************************************************************************/ -I2C_Rx_Status I2C_ReceptionStatus (I2C_TypeDef *I2Cx); - -/******************************************************************************* -* Function Name : I2C_ErrorClear -* Description : Clears any error flags. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : None. -*******************************************************************************/ -INLINE void I2C_ErrorClear (I2C_TypeDef *I2Cx) -{ - // Clear all error flags by reading the SR2 register - (void)I2Cx->SR2; -} - -/******************************************************************************* -* Function Name : I2C_GetStatus -* Description : Reads the I2C status registers. -* Input : None -* Return : I2C status registers. -*******************************************************************************/ -INLINE u32 I2C_GetStatus(I2C_TypeDef *I2Cx) -{ - return (((I2Cx->CR&0x04)<<14)|(I2Cx->SR1|(I2Cx->SR2<<8))&0x3FFF); -} - -#endif /* __i2c_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/pcu.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/pcu.h deleted file mode 100644 index 30d3fdda6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/pcu.h +++ /dev/null @@ -1,194 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : pcu.h -* Author : MCD Application Team -* Date First Issued : 30/05/2003 -* Description : This file contains all the functions prototypes for the -* PCU software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __PCU_H -#define __PCU_H - -#include "71x_map.h" - -typedef enum -{ - PCU_WREN = 0x8000, - PCU_VROK = 0x1000 -} PCU_Flags; - -typedef enum -{ - PCU_STABLE, - PCU_UNSTABLE -} PCU_VR_Status; - -typedef enum -{ - PCU_MVR = 0x0008, - PCU_LPR = 0x0020 -} PCU_VR; - -typedef enum -{ - WFI_CLOCK2_16, - WFI_EXTERNAL -} WFI_CLOCKS; - -typedef enum -{ - PCU_SLOW, - PCU_STOP, - PCU_STANDBY -} LPM_MODES; - - -// VR_OK : Voltage Regulator OK -#define PCU_VROK_Mask 0x1000 - -// Main Voltage Regulator -#define PCU_MVR_Mask 0x0008 - -// Low Power Voltage Regulator -#define PCU_LPR_Mask 0x0020 - -// PCU register Write Enable Bit -#define PCU_WREN_Mask 0x8000 - -// Low Voltage Detector -#define PCU_LVD_Mask 0x0100 - -// Power Down Flag -#define PCU_PWRDWN_Mask 0x0040 - -// WFI Mode Clock Selection Bit -#define PCU_WFI_CKSEL_Mask 0x00000002 - -// Halt Mode Enable Bit -#define PCU_EN_HALT_Mask 0x00000800 - -// Halt Mode Flag -#define PCU_HALT_Mask 0x0002 - -// Stop Mode Enable Bit -#define PCU_STOP_EN_Mask 0x00000400 - -// Low Power Regulator in Wait For interrupt Mode -#define PCU_LPRWFI_Mask 0x0020 - -// Low Power Mode in Wait For interrupt Mode -#define PCU_LPOWFI_Mask 0x00000001 - -// Software Reset Enable -#define PCU_SRESEN_Mask 0x00000001 - - -/******************************************************************************* -* Function Name : PCU_MVRStatus -* Description : This routine is used to check the Main Voltage Regulator -* : NewState. -* Input : None -* Return : STABLE, UNSTABLE -*******************************************************************************/ -INLINE PCU_VR_Status PCU_MVRStatus ( void ) -{ - return (PCU->PWRCR & PCU_VROK_Mask) == 0x00 ? PCU_UNSTABLE : PCU_STABLE; -} - -/******************************************************************************* -* Function Name : PCU_FlagStatus -* Description : This routine is used to return the PCU register flag -* Input 1 : The flag to get -* Return : RESET, SET -*******************************************************************************/ -INLINE FlagStatus PCU_FlagStatus ( PCU_Flags Xflag ) -{ - return ( PCU->PWRCR & Xflag ) == 0x00 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : PCU_VRConfig -* Description : This routine is used to configure PCU voltage regultors -* Input 1 : MVR : Main voltage Regulator - LPR : Low Power Regulator -* Input 2 : ENABLE : Enable the Voltage Regulator - DISABLE: Disable ( ByPass ) the VR -* Return : None -*******************************************************************************/ -void PCU_VRConfig ( PCU_VR xVR, FunctionalState NewState ); - -/******************************************************************************* -* Function Name : PCU_VRStatus -* Description : This routine is used to get the PCU voltage regultors status -* Input : MVR : Main voltage Regulator - LPR : Low Power Regulator -* Return : ENABLE : Enable the Voltage Regulator - DISABLE: Disable ( ByPass ) the VR -*******************************************************************************/ -INLINE FunctionalState PCU_VRStatus ( PCU_VR xVR ) -{ - return ( PCU->PWRCR & xVR ) == 0 ? ENABLE : DISABLE; -} - -/******************************************************************************* -* Function Name : PCU_LVDDisable -* Description : This routine is used to disable the Low Voltage Detector. -* Input : None -* Return : None -*******************************************************************************/ -INLINE void PCU_LVDDisable ( void ) -{ - PCU->PWRCR |= PCU_WREN_Mask; // Unlock Power Control Register - PCU->PWRCR |= PCU_LVD_Mask; // Set the LVD DIS Flag -} - -/******************************************************************************* -* Function Name : PCU_LVDStatus -* Description : This routine is used to get the LVD NewState. -* Input : None -* Return : ENABLE, DISABLE -*******************************************************************************/ -INLINE FunctionalState PCU_LVDStatus ( void ) -{ - return ( PCU->PWRCR & PCU_LVD_Mask ) == 0 ? ENABLE : DISABLE; -} - -/******************************************************************************* -* Function Name : PCU_WFIEnter -* Description : This routine is used to force the Device to enter in WFI mode -* Input 1 : CLOCK2_16 : Clock2_16 as system clock for WFI mode -* EXTERNAL : external clock as system clock for WFI mode -* Input 2 : ENABLE : Enable Low Power Regulator during Wait For Interrupt Mode -* DISABLE: Disable Low Power Regulator during Wait For Interrupt Mode -* Input 3 : ENABLE : Enable Low Power Mode during Wait For Interrupt Mode -* DISABLE: Disable Low Power Mode during Wait For Interrupt Mode -* Return : None -*******************************************************************************/ -void PCU_WFIEnter ( WFI_CLOCKS Xclock, FunctionalState Xlpr, FunctionalState Xlpm ); - -/******************************************************************************* -* Function Name : PCU_LPMEnter -* Description : This routine is used to force the Device to enter low -* power mode -* Input : SLOW : Slow Mode - STOP : Stop Mode - HALT : Halt Mode -* Return : None -*******************************************************************************/ -void PCU_LPMEnter ( LPM_MODES Xmode); - -#endif // __PCU_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/rccu.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/rccu.h deleted file mode 100644 index 775efc6d0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/rccu.h +++ /dev/null @@ -1,319 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : rccu.h -* Author : MCD Application Team -* Date First Issued : 28/07/2003 -* Description : This file contains all the functions prototypes for the -* RCCU software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __RCCU_H -#define __RCCU_H - -#include "71x_map.h" - -typedef enum { - RCCU_DEFAULT=0x00, - RCCU_RCLK_2 =0x01, - RCCU_RCLK_4 =0x02, - RCCU_RCLK_8 =0x03 - } RCCU_Clock_Div; - -typedef enum { - RCCU_PLL1_Output, - RCCU_CLOCK2_16, - RCCU_CLOCK2, - RCCU_RTC_CLOCK - } RCCU_RCLK_Clocks; - - - typedef enum { - RCCU_PLL1_Mul_12=0x01, - RCCU_PLL1_Mul_16=0x03, - RCCU_PLL1_Mul_20=0x00, - RCCU_PLL1_Mul_24=0x02 - } RCCU_PLL1_Mul; - -typedef enum { - RCCU_PLL2_Mul_12=0x01, - RCCU_PLL2_Mul_16=0x03, - RCCU_PLL2_Mul_20=0x00, - RCCU_PLL2_Mul_28=0x02 - } RCCU_PLL2_Mul; - -typedef enum { - RCCU_Div_1=0x00, - RCCU_Div_2=0x01, - RCCU_Div_3=0x02, - RCCU_Div_4=0x03, - RCCU_Div_5=0x04, - RCCU_Div_6=0x05, - RCCU_Div_7=0x06 - } RCCU_PLL_Div; - -typedef enum { - RCCU_PLL2_Output = 0x01, - RCCU_USBCK = 0x00 - } RCCU_USB_Clocks; - -typedef enum { - RCCU_CLK2, - RCCU_RCLK, - RCCU_MCLK, - RCCU_PCLK, - RCCU_FCLK - } RCCU_Clocks; - -typedef enum { - RCCU_PLL1_LOCK_IT = 0x0080, - RCCU_CKAF_IT = 0x0100, - RCCU_CK2_16_IT = 0x0200, - RCCU_STOP_IT = 0x0400 - } RCCU_Interrupts; - -typedef enum { - RCCU_PLL1_LOCK = 0x0002, - RCCU_CKAF_ST = 0x0004, - RCCU_PLL1_LOCK_I = 0x0800, - RCCU_CKAF_I = 0x1000, - RCCU_CK2_16_I = 0x2000, - RCCU_STOP_I = 0x4000 - } RCCU_Flags; - -typedef enum { - RCCU_ExternalReset = 0x00000000, - RCCU_SoftwareReset = 0x00000020, - RCCU_WDGReset = 0x00000040, - RCCU_RTCAlarmReset = 0x00000080, - RCCU_LVDReset = 0x00000200, - RCCU_WKPReset = 0x00000400 - }RCCU_ResetSources; - - -#define RCCU_Div2_Mask 0x00008000 -#define RCCU_Div2_Index 0x0F -#define RCCU_FACT_Mask 0x0003 - -#define RCCU_FACT1_Mask 0x0003 - -#define RCCU_FACT2_Mask 0x0300 -#define RCCU_FACT2_Index 0x08 - -#define RCCU_MX_Mask 0x00000030 -#define RCCU_MX_Index 0x04 - -#define RCCU_DX_Mask 0x00000007 - -#define RCCU_FREEN_Mask 0x00000080 - -#define RCCU_CSU_CKSEL_Mask 0x00000001 - -#define RCCU_CK2_16_Mask 0x00000008 - -#define RCCU_CKAF_SEL_Mask 0x00000004 - -#define RCCU_LOCK_Mask 0x00000002 - -#define RCCU_USBEN_Mask 0x0100 -#define RCCU_USBEN_Index 0x08 -#define RCCU_ResetSources_Mask 0x000006E0 - -// RTC Oscillator Frequency value = 32 768 Hz -#define RCCU_RTC_Osc 32768 - -/******************************************************************************* -* Function Name : RCCU_Div2Config -* Description : Enables/Disables the clock division by two -* Input : NewState : ENABLE or DISABLE -* Return : None -*******************************************************************************/ -INLINE void RCCU_Div2Config ( FunctionalState NewState ) -{ - if (NewState == ENABLE) RCCU->CFR |= RCCU_Div2_Mask; - else RCCU->CFR &= ~RCCU_Div2_Mask; -} - -/******************************************************************************* -* Function Name : RCCU_Div2Status -* Description : Gets the Div2 Flag status -* Input : None -* Input : FlagStatus -* Return : None -*******************************************************************************/ -INLINE FlagStatus RCCU_Div2Status ( void ) -{ - return (RCCU->CFR & RCCU_Div2_Mask) == 0 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : RCCU_MCLKConfig -* Description : Selects the division factor for RCLK to obtain the -* MCLK clock for the CPU -* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, RCCU_RCLK_4, RCCU_RCLK_8 -* Return : None -*******************************************************************************/ -INLINE void RCCU_MCLKConfig ( RCCU_Clock_Div New_Clock ) -{ - PCU->MDIVR = ( PCU->MDIVR & ~RCCU_FACT_Mask ) | New_Clock; -} - -/******************************************************************************* -* Function Name : RCCU_FCLKConfig -* Description : Selects the division factor for RCLK to obtain the -* FCLK clock for the APB1 fast peripherals (PCLK1). -* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, -* RCCU_RCLK_4, RCCU_RCLK_8 -* Return : None -*******************************************************************************/ -INLINE void RCCU_FCLKConfig ( RCCU_Clock_Div New_Clock ) -{ - PCU->PDIVR = ( PCU->PDIVR & ~RCCU_FACT1_Mask ) | New_Clock; -} - -/******************************************************************************* -* Function Name : RCCU_PCLKConfig -* Description : Selects the division factor for RCLK to obtain the -* PCLK clock for the APB2 peripherals (PCLK2). -* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, -* RCCU_RCLK_4, RCCU_RCLK_8 -* Return : None -*******************************************************************************/ -INLINE void RCCU_PCLKConfig ( RCCU_Clock_Div New_Clock ) -{ - PCU->PDIVR =(PCU->PDIVR & ~RCCU_FACT2_Mask)|(New_Clock << RCCU_FACT2_Index); -} - -/******************************************************************************* -* Function Name : RCCU_PLL1Config -* Description : Configures the PLL1 div & mul factors. -* Input : New_Mul : RCCU_Mul_12, RCCU_Mul_16, RCCU_Mul_20, RCCU_Mul_28 -* : New_Div : RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, -* RCCU_Div_4, RCCU_Div_5, RCCU_Div_6, RCCU_Div_7 -* Return : None -*******************************************************************************/ -void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div ); - -/******************************************************************************* -* Function Name : RCCU_PLL2Config -* Description : Configures the PLL2 div & mul factors. -* Input : New_Mul : RCCU_Mul_12, RCCU_Mul_16, RCCU_Mul_20, RCCU_Mul_28 -* : New_Div : RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, -* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7 -* Return : None -*******************************************************************************/ -void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div ); - -/******************************************************************************* -* Function Name : RCCU_RCLKSourceConfig -* Description : Selects the RCLK source clock -* Input : New_Clock : RCCU_PLL1_OutPut, RCCU_CLOCK2_16, RCCU_CLOCK2 -* Return : None -*******************************************************************************/ -void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock ); - -/******************************************************************************* -* Function Name : RCCU_RCLKClockSource -* Description : Returns the current RCLK source clock -* Input : None -* Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 -*******************************************************************************/ -RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void ); - -/******************************************************************************* -* Function Name : RCCU_USBCLKConfig -* Description : Selects the USB source clock -* Input : New_Clock : RCCU_PLL2_Output, RCCU_USBCK -* Return : None -*******************************************************************************/ -INLINE void RCCU_USBCLKConfig ( RCCU_USB_Clocks New_Clock ) -{ - PCU->PLL2CR = (PCU->PLL2CR & ~RCCU_USBEN_Mask)|(New_Clock << RCCU_USBEN_Index); -} - -/******************************************************************************* -* Function Name : RCCU_USBClockSource -* Description : Gets the USB source clock -* Input : None -* Return : RCCU_USB_Clocks -*******************************************************************************/ -RCCU_USB_Clocks RCCU_USBClockSource ( void ); - -/******************************************************************************* -* Function Name : RCCU_FrequencyValue -* Description : Calculates & Returns any internal RCCU clock freuqency -* passed in parametres -* Input : RCCU_Clocks : RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, -* RCCU_PCLK, RCCU_FCLK -* Return : u32 -*******************************************************************************/ -u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk ); - -/******************************************************************************* -* Function Name : RCCU_ITConfig -* Description : Configures the RCCU interrupts -* Input : RCCU interrupts : RCCU_CK2_16_IT, RCCU_CKAF_IT, -* RCCU_PLL1_LOCK_IT -* Return : None -*******************************************************************************/ -INLINE void RCCU_ITConfig ( RCCU_Interrupts RCCU_IT, FunctionalState NewState) -{ - if (NewState == ENABLE) RCCU->CCR |= RCCU_IT; else RCCU->CCR &= ~RCCU_IT; -} - -/******************************************************************************* -* Function Name : RCCU_FlagStatus -* Description : Checks the RCCU clock flag register status -* Input : RCCU Flags : RCCU_CK2_16, RCCU_CKAF, RCCU_PLL1_LOCK -* Return : FlagStatus : SET or RESET -*******************************************************************************/ -INLINE FlagStatus RCCU_FlagStatus ( RCCU_Flags RCCU_flag ) -{ - return (RCCU->CFR & RCCU_flag) == 0 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : RCCU_FlagClear -* Description : Clears a specified flag in the RCCU registers -* Input : RCCU Flags : RCCU_CK2_16, RCCU_CKAF, RCCU_PLL1_LOCK -* Return : None -*******************************************************************************/ -INLINE void RCCU_FlagClear ( RCCU_Interrupts RCCU_IT ) -{ - RCCU->CFR |= RCCU_IT; -} - -/******************************************************************************* -* Function Name : RCCU_ResetSources -* Description : Return the source of the system reset -* Input : None -* Return : The reset source -*******************************************************************************/ -INLINE RCCU_ResetSources RCCU_ResetSource () -{ - - switch(RCCU->CFR & RCCU_ResetSources_Mask) - { - case 0x00000020: return RCCU_SoftwareReset; - case 0x00000040: return RCCU_WDGReset; - case 0x00000080: return RCCU_RTCAlarmReset; - case 0x00000200: return RCCU_LVDReset; - case 0x00000400: return RCCU_WKPReset; - default : return RCCU_ExternalReset; - } -} - -#endif // __RCCU_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/rtc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/rtc.h deleted file mode 100644 index 6d449196e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/rtc.h +++ /dev/null @@ -1,190 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : rtc.h -* Author : MCD Application Team -* Date First Issued : 20/05/2003 -* Description : This file contains all the functions prototypes for the -* RTC software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __RTC_H -#define __RTC_H - -#include "71x_map.h" - -typedef enum -{ - RTC_GIR = 0x08, - RTC_OWIR = 0x04, - RTC_AIR = 0x02, - RTC_SIR = 0x01 -} RTC_FLAGS; - -typedef enum -{ - RTC_GIT = 0x08, - RTC_OWIT = 0x04, - RTC_AIT = 0x02, - RTC_SIT = 0x01, - RTC_NONE = 0x00 -} RTC_IT; - -/******************************************************************************* -* Function Name : RTC_Delay -* Description : This routine is used to insert a delay -* Input : None -* Return : None -*******************************************************************************/ -void RTC_Delay( void ); - -/******************************************************************************* -* Function Name : RTC_CounterClear -* Description : This routine is used to clear the RTC counter -* Input : None -* Return : None -*******************************************************************************/ -void RTC_CounterClear (void); -/******************************************************************************* -* Function Name : RTC_CounterValue -* Description : This routine is used to get the RTC counter value -* Input : None -* Return : The current counter value. -*******************************************************************************/ -INLINE u32 RTC_CounterValue (void) -{ - return ( (u32)RTC->CNTH << 16 ) | RTC->CNTL; -} -/******************************************************************************* -* Function Name : RTC_CounterConfig -* Description : This routine is used to update the RTC counter value -* Input : The new counter value. -* Return : None -*******************************************************************************/ -void RTC_CounterConfig (u32 CounterValue); - -/******************************************************************************* -* Function Name : RTC_PrescalerValue -* Description : This routine is used to get the RTC prescaler Value -* Input : None -* Return : an u32 value that holds the prescaler Value. -*******************************************************************************/ -INLINE u32 RTC_PrescalerValue (void) -{ - return ( (u32)(RTC->PRLH & 0x000F) << 16 ) | RTC->PRLL; -} - -/******************************************************************************* -* Function Name : RTC_PrescalerConfig -* Description : This routine is used to set the Prescaler Value -* Input : The New prescaler Value -* Return : None -*******************************************************************************/ -void RTC_PrescalerConfig (u32 Xprescaler); - -/******************************************************************************* -* Function Name : RTC_AlarmValue -* Description : This routine is used to get the RTC alarm Value -* Input : None -* Return : an u32 value that holds the Real Time clock alarm time . -*******************************************************************************/ -INLINE u32 RTC_AlarmValue (void) -{ - return ( (u32)RTC->ALRH << 16 ) | RTC->ALRL; -} - -/******************************************************************************* -* Function Name : RTC_AlarmConfig -* Description : This routine is used to set the RTC alarm Value -* Input : an u32 value that holds the Real Time clock alarm time . -* Return : None -*******************************************************************************/ -void RTC_AlarmConfig (u32 Xalarm); - -/******************************************************************************* -* Function Name : RTC_FlagStatus -* Description : This routine is used to chek the RTC flag status -* Input : an RTC flag -* Return : Set or RESET -*******************************************************************************/ -INLINE FlagStatus RTC_FlagStatus (RTC_FLAGS Xflag) -{ - return ( RTC->CRL & Xflag ) == 0 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : RTC_FlagClear -* Description : This routine is used to clear the RTC flags -* Input : an RTC flag -* Return : None -*******************************************************************************/ -void RTC_FlagClear (RTC_FLAGS Xflag); - -/******************************************************************************* -* Function Name : RTC_ITConfig -* Description : This routine is used to configure the RTC interrupts -* Input 1 : an RTC interrupt -* Input 2 : Enable or Disable -* Return : None -*******************************************************************************/ -INLINE void RTC_ITConfig (RTC_IT Xrtcit, FunctionalState NewState) -{ - if (NewState == ENABLE) RTC->CRH |= Xrtcit; else RTC->CRH &= ~Xrtcit; -} - -/******************************************************************************* -* Function Name : RTC_ITStatus -* Description : This routine is used to get the RTC interrupts status -* Input : an RTC interrupt -* Return : Enable or Disable -*******************************************************************************/ -INLINE FunctionalState RTC_ITStatus (RTC_IT Xrtcit) -{ - return ( RTC->CRH & Xrtcit ) == 0 ? DISABLE : ENABLE; -} - -/******************************************************************************* -* Function Name : RTC_ITClear -* Description : This routine is used to clear the RTC interrupts -* Input : an RTC interrupt -* Return : None -*******************************************************************************/ -void RTC_ITClear (RTC_IT Xrtcit); - -/******************************************************************************* -* Function Name : RTC_EnterCfgMode -* Description : This routine is used to enter in the Configuration Mode -* Input : None -* Return : None -*******************************************************************************/ -void RTC_EnterCfgMode(void); - -/******************************************************************************* -* Function Name : RTC_ExitCfgMode -* Description : This routine is used to exit from the Configuration Mode -* Input : None -* Return : None -*******************************************************************************/ -void RTC_ExitCfgMode(void); - -/******************************************************************************* -* Function Name : RTC_WaitForLastTask -* Description : This routine is waits for the last task completetion -* Input : None -* Return : None -*******************************************************************************/ -void RTC_WaitForLastTask(void); - -#endif // __RTC_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/tim.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/tim.h deleted file mode 100644 index 15c009468..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/tim.h +++ /dev/null @@ -1,346 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : tim.h -* Author : MCD Application Team -* Date First Issued : 08/09/2003 -* Description : This file contains all the functions prototypes for the -* TIM software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __TIM_H -#define __TIM_H - -#include "71x_map.h" - -typedef enum { TIM_EXTERNAL, - TIM_INTERNAL - } TIM_Clocks; - -typedef enum { TIM_RISING, - TIM_FALLING - } TIM_Clock_Edges; - -typedef enum { TIM_CHANNEL_A, - TIM_CHANNEL_B - } TIM_Channels; - -typedef enum { TIM_WITH_IT, - TIM_WITHOUT_IT - } TIM_IT_Mode; - -typedef enum { TIM_TIMING, - TIM_WAVE - } TIM_OC_Modes; - -typedef enum { TIM_HIGH, - TIM_LOW - } TIM_Logic_Levels; - -typedef enum { TIM_START, - TIM_STOP, - TIM_CLEAR - } TIM_CounterOperations; - -typedef enum { TIM_ICFA = 0x8000, - TIM_OCFA = 0x4000, - TIM_TOF = 0x2000, - TIM_ICFB = 0x1000, - TIM_OCFB = 0x0800 - } TIM_Flags; - -typedef struct { u16 Pulse; - u16 Period; - } PWMI_parameters; - -#define TIM_ECKEN_Mask 0x0001 -#define TIM_EXEDG_Mask 0x0002 - -#define TIM_IEDGA_Mask 0x0004 -#define TIM_IEDGB_Mask 0x0008 - -#define TIM_PWM_Mask 0x0010 - -#define TIM_OMP_Mask 0x0020 - -#define TIM_OCAE_Mask 0x0040 -#define TIM_OCBE_Mask 0x0080 - -#define TIM_OLVLA_Mask 0x0100 -#define TIM_OLVLB_Mask 0x0200 - -#define TIM_FOLVA_Mask 0x0400 -#define TIM_FOLVB_Mask 0x0800 - -#define TIM_PWMI_Mask 0x4000 - -#define TIM_EN_Mask 0x8000 - -#define TIM_OCBIE_mask 0x0800 -#define TIM_ICBIE_Mask 0x1000 -#define TIM_TOE_Mask 0x2000 -#define TIM_ICAIE_Mask 0x8000 -#define TIM_OCAIE_mask 0x4000 - -#define TIM_ICA_IT 0x8000 // Input Capture Channel A -#define TIM_OCA_IT 0x4000 // Output Compare Channel A -#define TIM_TO_IT 0x2000 // Timer OverFlow -#define TIM_ICB_IT 0x1000 // Input Capture Channel B -#define TIM_OCB_IT 0x0800 // Input Capture Channel A - - -/******************************************************************************* -* Function Name : TIM_Init -* Description : This routine is used to Initialize the TIM peripheral -* Input : TIM Timer to Initialize -* Return : None -*******************************************************************************/ -void TIM_Init( TIM_TypeDef *TIMx ); - -/******************************************************************************* -* Function Name : TIM_ClockSourceConfig -* Description : This routine is used to configure the TIM clock source -* Input : (1) TIM Timer -* : (2) TIM_Clocks : Specifies the TIM source clock -* - TIM_INTERNAL : The TIM is clocked by the APB2 frequency -* divided by the prescaler value. -* - TIM_EXTERNAL : The TIM is clocked by an external Clock -* Return : None -*******************************************************************************/ -INLINE void TIM_ClockSourceConfig ( TIM_TypeDef *TIMx, TIM_Clocks Xclock ) -{ - if (Xclock==TIM_EXTERNAL) TIMx->CR1|=TIM_ECKEN_Mask; else TIMx->CR1&=~TIM_ECKEN_Mask; -} - -/******************************************************************************* -* Function Name : TIM_ClockSourceValue -* Description : This routine is used to get the TIM clock source -* Input : TIM Timer -* Return : TIM_Clocks : Specifies the TIM source clock -* - TIM_INTERNAL : The TIM is clocked by the APB2 frequency -* divided by the prescaler value. -* - TIM_EXTERNAL : The TIM is clocked by an external Clock -*******************************************************************************/ -INLINE TIM_Clocks TIM_ClockSourceValue ( TIM_TypeDef *TIMx ) -{ - return ( TIMx->CR1 & TIM_ECKEN_Mask) == 0 ? TIM_INTERNAL : TIM_EXTERNAL; -} - -/******************************************************************************* -* Function Name : TIM_PrescalerConfig -* Description : This routine is used to configure the TIM prescaler value -* ( using an internal clock ) -* Input : (1) TIM Timer -* : (2) Prescaler ( u8 ) -* Return : None -*******************************************************************************/ -INLINE void TIM_PrescalerConfig ( TIM_TypeDef *TIMx, u8 Xprescaler ) -{ - TIMx->CR2 = ( TIMx->CR2 & 0xFF00 ) | Xprescaler; -} - -/******************************************************************************* -* Function Name : TIM_PrescalerValue -* Description : This routine is used to get the TIM prescaler value -* ( when using using an internal clock ) -* Input : TIM Timer -* Return : Prescaler ( u8 ) -*******************************************************************************/ -INLINE u8 TIM_PrescalerValue ( TIM_TypeDef *TIMx ) -{ - return TIMx->CR2 & 0x00FF; -} - -/******************************************************************************* -* Function Name : TIM_ClockLevelConfig -* Description : This routine is used to configure the TIM clock level -* ( using an external clock ) -* Input : TIM Timer -* : TIM_Clock_Edges : Specifies the active adge of the external clock -* - TIM_RISING : The rising edge -* - TIM_FALLING : The falling edge -* Return : None -*******************************************************************************/ -INLINE void TIM_ClockLevelConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge ) -{ - if (Xedge == TIM_RISING) TIMx->CR1 |= TIM_EXEDG_Mask; else TIMx->CR1 &= ~TIM_EXEDG_Mask; -} - -/******************************************************************************* -* Function Name : TIM_ClockLevelValue -* Description : This routine is used to get the TIM clock level -* Input : TIM Timer -* Output : TIM_Clock_Edges : Specifies the active adge of the external clock -* - TIM_RISING : The rising edge -* - TIM_FALLING : The falling edge -*******************************************************************************/ -INLINE TIM_Clock_Edges TIM_ClockLevelValue ( TIM_TypeDef *TIMx ) -{ - return ( TIMx->CR1 & TIM_EXEDG_Mask ) == 0 ? TIM_FALLING : TIM_RISING; -} - -/******************************************************************************* -* Function Name : TIM_ICAPModeConfig -* Description : This routine is used to configure the input capture feature -* Input : (1) TIM Timer -* : (2) Input Capture Channel ( Channel_A or Channel_B ) -* : (3) Active Edge : Rising edge or Falling edge. -* Output : None -*******************************************************************************/ -void TIM_ICAPModeConfig ( TIM_TypeDef *TIMx, - TIM_Channels Xchannel, - TIM_Clock_Edges Xedge ); - -/******************************************************************************* -* Function Name : TIM_ICAPValue -* Description : This routine is used to get the Input Capture value -* Input : (1) TIM Timer -* : (2) Input Capture Channel ( Channel_A or Channel_B ) -* Output : None -*******************************************************************************/ -INLINE u16 TIM_ICAPValue ( TIM_TypeDef *TIMx, TIM_Channels Xchannel ) -{ - return Xchannel == TIM_CHANNEL_A ? TIMx->ICAR : TIMx->ICBR; -} - -/******************************************************************************* -* Function Name : TIM_OCMPModeConfig -* Description : This routine is used to configure the output compare feature -* Input : (1) TIM Timer -* : (2) OCMP Channel ( Channel_A or Channel_B ) -* : (3) Pulse Length -* : (4) OC_Mode : output wave, or only timing. -* : (5) Level : Rising edge or Falling edge after the == -* Output : None -*******************************************************************************/ -void TIM_OCMPModeConfig ( TIM_TypeDef *TIMx, - TIM_Channels Xchannel, - u16 XpulseLength, - TIM_OC_Modes Xmode, - TIM_Logic_Levels Xlevel ); - -/******************************************************************************* -* Function Name : TIM_OPModeConfig -* Description : This routine is used to configure the one pulse mode -* Input : (1) TIM Timer -* : (3) XpulseLength : Length of the pulse -* : (4) Level1 : Level during the pulse -* : (5) Level2 : Level after the pulse -* : (6) Activation Edge : High or Low on ICAP A -* Output : None -*******************************************************************************/ -void TIM_OPModeConfig ( TIM_TypeDef *TIMx, - u16 XpulseLength, - TIM_Logic_Levels XLevel1, - TIM_Logic_Levels XLevel2, - TIM_Clock_Edges Xedge ); - -/******************************************************************************* -* Function Name : TIM_PWMOModeConfig -* Description : This routine is used to configure the PWM in output mode -* Input : (1) TIM Timer -* : (2) DutyCycle : u16 -* : (3) Level 1 : During the Duty Cycle -* : (4) Level 2 : During the after the pulse -* : (5) Full period : u16 -* Output : None -*******************************************************************************/ -void TIM_PWMOModeConfig ( TIM_TypeDef *TIMx, - u16 XDutyCycle, - TIM_Logic_Levels XLevel1, - u16 XFullperiod, - TIM_Logic_Levels XLevel2 - ); - -/******************************************************************************* -* Function Name : TIM_PWMInputConfig -* Description : This routine is used to configure the PWM in input mode -* Input : (1) TIM Timer -* : (2) First Activation Edge -* Output : None -*******************************************************************************/ -void TIM_PWMIModeConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge ); - -/******************************************************************************* -* Function Name : TIM_PWMIValue -* Description : This routine is used to get the PWMI values -* Input : (1) TIM Timer -* Output : PWMI_parameters : - u16 Dyty cycle - - u16 Full period -*******************************************************************************/ -PWMI_parameters TIM_PWMIValue (TIM_TypeDef *TIMx ); - -/******************************************************************************* -* Function Name : TIM_CounterConfig -* Description : This routine is used to start/stop and clear the selected -* timer counter -* Input : (1) TIM Timer -* : (2) TIM_CounterOperations - TIM_START Enables or resumes the counter -* TIM_STOP Stops the TIM counter -* TIM_CLEAR Set the TIM counter value to FFFCh -* Output : None -*******************************************************************************/ -void TIM_CounterConfig ( TIM_TypeDef *TIMx, TIM_CounterOperations Xoperation ); - -/******************************************************************************* -* Function Name : TIM_ITConfig -* Description : This routine is used to configure the TIM IT -* Input : (1) TIM Timer -* : (2) TIM interrupt -* : (2) ENABLE / DISABLE -* Output : None -*******************************************************************************/ -INLINE void TIM_ITConfig ( TIM_TypeDef *TIMx, u16 New_IT, FunctionalState NewState ) -{ - if (NewState == ENABLE) TIMx->CR2 |= New_IT; else TIMx->CR2 &= ~New_IT; -} - -/******************************************************************************* -* Function Name : TIM_FlagStatus -* Description : This routine is used to check whether a Flag is Set. -* Input : (1) TIM Timer -* : (2) The TIM FLag -* Output : Flag NewState -*******************************************************************************/ -INLINE FlagStatus TIM_FlagStatus ( TIM_TypeDef *TIMx, TIM_Flags Xflag ) -{ - return (TIMx->SR & Xflag) == 0 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : TIM_FlagClear -* Description : This routine is used to clear Flags. -* Input : (1) TIM Timer -* : (2) The TIM FLag -* Output : None -*******************************************************************************/ -INLINE void TIM_FlagClear ( TIM_TypeDef *TIMx, TIM_Flags Xflag ) -{ - TIMx->SR &= ~Xflag; -} - -/******************************************************************************* -* Function Name : TIM_CounterValue -* Description : This routine returns the timer counter value. -* Input : TIM Timer -* Output : The counter value -*******************************************************************************/ -INLINE u16 TIM_CounterValue(TIM_TypeDef *TIMx) -{ - return TIMx->CNTR; -} -#endif // __TIM_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/uart.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/uart.h deleted file mode 100644 index 248c8da71..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/uart.h +++ /dev/null @@ -1,391 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : uart.h -* Author : MCD Application Team -* Date First Issued : 16/05/2003 -* Description : This file contains all the functions prototypes for the -* UART software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef _UART_H -#define _UART_H - -#include "71x_map.h" -#include "rccu.h" - -typedef enum -{ - UART_RxFIFO, - UART_TxFIFO -} UARTFIFO_TypeDef; - -typedef enum -{ - UART_EVEN_PARITY = 0x0000, - UART_ODD_PARITY = 0x0020, - UART_NO_PARITY -} UARTParity_TypeDef; - -typedef enum -{ - UART_0_5_StopBits = 0x00, - UART_1_StopBits = 0x08, - UART_1_5_StopBits = 0x10, - UART_2_StopBits = 0x18 -} UARTStopBits_TypeDef; - -typedef enum -{ - UARTM_8D = 0x01, - UARTM_7D_P = 0x03, - UARTM_9D = 0x04, - UARTM_8D_W = 0x05, - UARTM_8D_P = 0x07 -} UARTMode_TypeDef; - - -#define DUMMY 0 - -// UART flags definition -#define UART_TxFull 0x0200 -#define UART_RxHalfFull 0x0100 -#define UART_TimeOutIdle 0x0080 -#define UART_TimeOutNotEmpty 0x0040 -#define UART_OverrunError 0x0020 -#define UART_FrameError 0x0010 -#define UART_ParityError 0x0008 -#define UART_TxHalfEmpty 0x0004 -#define UART_TxEmpty 0x0002 -#define UART_RxBufFull 0x0001 - -// CR regiter bit definition -#define UART_FIFOEnableBit 10 -#define UART_RxEnableBit 8 -#define UART_RunBit 7 -#define UART_LoopBackBit 6 -#define UART_ParityOddBit 5 -#define UART_StopBits 3 - -// Stop bits definition -#define UART_05StopBits 0x00 -#define UART_1StopBit (0x01<<3) -#define UART_15StopBits (0x02<<3) -#define UART_2StopBits (0x03<<3) - -// Modes definition -#define UART_8BitsData 0x01 -#define UART_7BitsData 0x03 -#define UART_9BitsData 0x04 -#define UART_8BitsDataWakeUp 0x05 -#define UART_8BitsDataParity 0x07 - -/******************************************************************************* -* Function Name : UART_Init -* Description : This function initializes the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Output : None -* Return : None -*******************************************************************************/ -void UART_Init(UART_TypeDef *UARTx); - -/******************************************************************************* -* Function Name : UART_ModeConfig -* Description : This function configures the mode of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The UART mode -* Output : None -* Return : None -*******************************************************************************/ -INLINE void UART_ModeConfig(UART_TypeDef *UARTx, UARTMode_TypeDef UART_Mode) -{ - UARTx->CR = (UARTx->CR&0xFFF8)|(u16)UART_Mode; -} - -/******************************************************************************* -* Function Name : UART_BaudRateConfig -* Description : This function configures the baud rate of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The baudrate value -* Output : None -* Return : None -*******************************************************************************/ -void UART_BaudRateConfig(UART_TypeDef *UARTx, u32 BaudRate); - -/******************************************************************************* -* Function Name : UART_ParityConfig -* Description : This function configures the data parity of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The parity type -* Output : None -* Return : None -*******************************************************************************/ -INLINE void UART_ParityConfig(UART_TypeDef *UARTx, UARTParity_TypeDef Parity) -{ - UARTx->CR = (UARTx->CR&0xFFDF)|(u16)Parity; -} - -/******************************************************************************* -* Function Name : UART_StopBitsConfig -* Description : This function configures the number of stop bits of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The number of stop bits -* Output : None -* Return : None -*******************************************************************************/ -INLINE void UART_StopBitsConfig(UART_TypeDef *UARTx, UARTStopBits_TypeDef StopBits) -{ - UARTx->CR = (UARTx->CR&0xFFE7)|(u16)StopBits; -} - -/******************************************************************************* -* Function Name : UART_Config -* Description : This function configures the baudrate, the mode, the data -* parity and the number of stop bits of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The baudrate value -* Input 3 : The parity type -* Input 4 : The number of stop bits -* Input 5 : The UART mode -* Output : None -* Return : None -*******************************************************************************/ -void UART_Config(UART_TypeDef *UARTx, u32 BaudRate, UARTParity_TypeDef Parity, - UARTStopBits_TypeDef StopBits, UARTMode_TypeDef Mode); - -/******************************************************************************* -* Function Name : UART_ItConfig -* Description : This function enables or disables the interrupts of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The new interrupt flag -* Input 3 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_ItConfig(UART_TypeDef *UARTx, u16 UART_Flag, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_FifoConfig -* Description : This function enables or disables the Rx and Tx FIFOs of -* the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_FifoConfig(UART_TypeDef *UARTx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_FifoReset -* Description : This function resets the Rx and the Tx FIFOs of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : RxFIFO or TxFIFO -* Output : None -* Return : None -*******************************************************************************/ -void UART_FifoReset(UART_TypeDef *UARTx, UARTFIFO_TypeDef FIFO); - -/******************************************************************************* -* Function Name : UART_LoopBackConfig -* Description : This function enables or disables the loop back mode of -* the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_LoopBackConfig(UART_TypeDef *UARTx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_TimeOutPeriodConfig -* Description : This function configure the Time Out Period. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The time-out period value -* Output : None -* Return : None -*******************************************************************************/ -INLINE void UART_TimeOutPeriodConfig(UART_TypeDef *UARTx, u16 TimeOutPeriod) -{ - UARTx->TOR = TimeOutPeriod; -} - -/******************************************************************************* -* Function Name : UART_GuardTimeConfig -* Description : This function configure the Guard Time. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The guard time value -* Output : None -* Return : None -*******************************************************************************/ -INLINE void UART_GuardTimeConfig(UART_TypeDef *UARTx, u16 GuardTime) -{ - UARTx->GTR = GuardTime; -} - -/******************************************************************************* -* Function Name : UART_RxConfig -* Description : This function enable and disable the UART data reception. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_RxConfig(UART_TypeDef *UARTx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_OnOffConfig -* Description : This function sets On/Off the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_OnOffConfig(UART_TypeDef *UARTx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_ByteSend -* Description : This function sends a data byte to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data byte to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_ByteSend(UART_TypeDef *UARTx, u8 *Data); - -/******************************************************************************* -* Function Name : UART_9BitByteSend -* Description : This function sends a 9 bits data byte to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_9BitByteSend(UART_TypeDef *UARTx, u16 *Data); - -/******************************************************************************* -* Function Name : UART_DataSend -* Description : This function sends several data bytes to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Input 3 : The data length in bytes -* Output : None -* Return : None -*******************************************************************************/ -void UART_DataSend(UART_TypeDef *UARTx, u8 *Data, u8 DataLength); - -/******************************************************************************* -* Function Name : UART_9BitDataSend -* Description : This function sends several 9 bits data bytes to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Input 3 : The data length -* Output : None -* Return : None -*******************************************************************************/ -void UART_9BitDataSend(UART_TypeDef *UARTx, u16 *Data, u8 DataLength); - -/******************************************************************************* -* Function Name : UART_StringSend -* Description : This function sends a string to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the string to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_StringSend(UART_TypeDef *UARTx, u8 *String); - -/******************************************************************************* -* Function Name : UART_ByteReceive -* Description : This function gets a data byte from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The time-out period -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_ByteReceive(UART_TypeDef *UARTx, u8 *Data, u8 TimeOut); - -/******************************************************************************* -* Function Name : UART_9BitByteReceive -* Description : This function gets a 9 bits data byte from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The time-out period value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_9BitByteReceive(UART_TypeDef *UARTx, u16 *Data, u8 TimeOut); - -/******************************************************************************* -* Function Name : UART_DataReceive -* Description : This function gets 8 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The data length -* Input 4 : The time-out period value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_DataReceive(UART_TypeDef *UARTx, u8 *Data, u8 DataLength, u8 TimeOut); - -/******************************************************************************* -* Function Name : UART_9BitDataReceive -* Description : This function gets 9 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The data length -* Input 4 : The time-out value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_9BitDataReceive(UART_TypeDef *UARTx, u16 *Data, u8 DataLength, u8 TimeOut); - -/******************************************************************************* -* Function Name : UART_StringReceive -* Description : This function gets 8 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the string will be stored -* Output : None -* Return : None -*******************************************************************************/ -u16 UART_StringReceive(UART_TypeDef *UARTx, u8 *Data); - -/******************************************************************************* -* Function Name : UART_FlagStatus -* Description : This function gets the flags status of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Output : None -* Return : None -*******************************************************************************/ -INLINE u16 UART_FlagStatus(UART_TypeDef *UARTx) -{ - return UARTx->SR; -} - -#ifdef USE_SERIAL_PORT -/******************************************************************************* -* Function Name : sendchar -* Description : This function sends a character to the selected UART. -* Input 1 : A pointer to the character to send. -* Output : None -* Return : None -*******************************************************************************/ -void sendchar( char *ch ); -#endif /* USE_SERIAL_PORT */ - -#endif /* _UART_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/wdg.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/wdg.h deleted file mode 100644 index 58858824a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/wdg.h +++ /dev/null @@ -1,130 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : wdg.h -* Author : MCD Application Team -* Date First Issued : 25/08/2003 -* Description : This file contains all the functions prototypes for the -* WDG software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __WDG_H -#define __WDG_H - -#include "71x_map.h" -#include "rccu.h" - -/******************************************************************************* -* Function Name : WDG_Enable -* Description : Enable the Watchdog Mode -* Input : None -* Return : None -*******************************************************************************/ -INLINE void WDG_Enable ( void ) -{ - WDG->CR |= 0x01; -} - -/******************************************************************************* -* Function Name : WDG_CntRefresh -* Description : Refresh and update the WDG counter to avoid a system reset. -* Input : None -* Return : None -*******************************************************************************/ -INLINE void WDG_CntRefresh ( void ) -{ - //write the first value in the key register - WDG->KR = 0xA55A; - //write the consecutive value - WDG->KR = 0x5AA5; -} - -/******************************************************************************* -* Function Name : WDG_PrescalerConfig -* Description : Set the counter prescaler value. -* Divide the counter clock by (Prescaler + 1) -* Input : Prescaler data value (8 bit) -* Return : None -*******************************************************************************/ -INLINE void WDG_PrescalerConfig ( u8 Prescaler ) -{ - WDG->PR = Prescaler; -} - -/******************************************************************************* -* Function Name : WDG_CntReloadUpdate -* Description : Update the counter pre-load value. -* Input : Pre-load data value (16 bit) -* Return : None -*******************************************************************************/ -INLINE void WDG_CntReloadUpdate ( u16 PreLoadValue ) -{ - WDG->VR = PreLoadValue; -} - -/******************************************************************************* -* Function Name : WDG_PeriodValueConfig -* Description : Set the prescaler and counter reload value based on the -* time needed -* Input : Amount of time (us) needed, peripheral clock2 value -* Return : None -*******************************************************************************/ -void WDG_PeriodValueConfig ( u32 Time ); - -/******************************************************************************* -* Function Name : WDG_CntOnOffConfig -* Description : Start or stop the free auto-reload timer to countdown. -* Input : ENABLE or DISABLE -* Return : None -*******************************************************************************/ -INLINE void WDG_CntOnOffConfig ( FunctionalState NewState ) -{ - if (NewState == ENABLE) WDG->CR |= 0x0002; else WDG->CR &= ~0x0002; -} - -/******************************************************************************* -* Function Name : WDG_ECITConfig -* Description : Enable or Disable the end of count interrupt -* Input : ENABLE or DISABLE -* Return : None -*******************************************************************************/ -INLINE void WDG_ECITConfig (FunctionalState NewState) -{ - if (NewState == ENABLE) WDG->MR |= 0x0001; else WDG->MR &= ~0x0001; -} - -/******************************************************************************* -* Function Name : WDG_ECFlagClear -* Description : Clear the end of count flag -* Input : None -* Return : None -*******************************************************************************/ -INLINE void WDG_ECFlagClear ( void ) -{ - WDG->SR = 0x0000; -} - -/******************************************************************************* -* Function Name : WDG_ECStatus -* Description : Return the end of count status -* Input : None -* Return : NewState value -*******************************************************************************/ -INLINE u16 WDG_ECStatus ( void ) -{ - return WDG->SR; -} - -#endif // __WDG_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/xti.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/xti.h deleted file mode 100644 index a8a2476a9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/include/xti.h +++ /dev/null @@ -1,138 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : xti.h -* Author : MCD Application Team -* Date First Issued : 08/06/2003 -* Description : This file contains all the functions prototypes for the -* XTI software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __XTI_H -#define __XTI_H - -#include "71x_map.h" - -typedef enum -{ - XTI_WakeUp = 1, - XTI_Interrupt = 2, - XTI_WakeUpInterrupt = 3 -} XTIMode_TypeDef; - -typedef enum -{ - XTI_FallingEdge, - XTI_RisingEdge -} XTITriggerEdge_TypeDef; - -#define XTI_Line0 0x0001 -#define XTI_Line1 (XTI_Line0<<1) -#define XTI_Line2 (XTI_Line1<<1) -#define XTI_Line3 (XTI_Line2<<1) -#define XTI_Line4 (XTI_Line3<<1) -#define XTI_Line5 (XTI_Line4<<1) -#define XTI_Line6 (XTI_Line5<<1) -#define XTI_Line7 (XTI_Line6<<1) -#define XTI_Line8 (XTI_Line7<<1) -#define XTI_Line9 (XTI_Line8<<1) -#define XTI_Line10 (XTI_Line9<<1) -#define XTI_Line11 (XTI_Line10<<1) -#define XTI_Line12 (XTI_Line11<<1) -#define XTI_Line13 (XTI_Line12<<1) -#define XTI_Line14 (XTI_Line13<<1) -#define XTI_Line15 (XTI_Line14<<1) - -/******************************************************************************* -* Function Name : XTI_Init -* Description : Initialize the XIT peripheral to reset state. -* Input 1 : None -* Output : None -* Return : None -*******************************************************************************/ -void XTI_Init(void); - -/******************************************************************************* -* Function Name : XTI_ModeConfig -* Description : Configure the XTI Mede -* Input 1 : Mode can be WakeUp, Interrupt or WakeUpInterrupt. -* Input 2 : NewState can be ENABLE ro DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -INLINE void XTI_ModeConfig(XTIMode_TypeDef Mode,FunctionalState NewState) -{ - if (NewState==ENABLE) XTI->CTRL|=Mode; else XTI->CTRL&=~Mode; -} - -/******************************************************************************* -* Function Name : XTI_LineModeConfig -* Description : Configure the trigger edge. -* Input 1 : Lines to be configured. -* Input 2 : The trigger edge can be FallingEdge or RisingEdge. -* Output : None -* Return : None -*******************************************************************************/ -void XTI_LineModeConfig(u16 Lines, XTITriggerEdge_TypeDef TriggerEdge); - -/******************************************************************************* -* Function Name : XTI_LineConfig -* Description : Enable and disable lines interrupts -* Input 1 : Lines to be configured. -* Input 2 : NewState can be ENABLE ro DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void XTI_LineConfig(u16 Lines, FunctionalState NewState); - -/******************************************************************************* -* Function Name : XTI_InterruptLineValue -* Description : Get the interrupt lines -* Input 1 : None. -* Output : The interrupts lines numbers -* Return : None -*******************************************************************************/ -INLINE u16 XTI_InterruptLineValue(void) -{ - return XTI->PRL | ((u16)XTI->PRH<<8); -} - -/******************************************************************************* -* Function Name : XTI_PendingBitClear -* Description : Clear the pending bits -* Input 1 : Bits to be cleared. -* Output : None -* Return : None -*******************************************************************************/ -INLINE void XTI_PendingBitClear(u16 Lines) -{ - XTI->PRL &= ~Lines; - XTI->PRH &= ~((Lines>>8)&0x00FF); -} - -/******************************************************************************* -* Function Name : XTI_SoftwareIRQInterruprGenerate -* Description : Generate a software IRQ interrupt. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -INLINE void XTI_SWIRQGenerate(void) -{ - XTI->SR = 0x01; - XTI->SR = 0x00; -} - -#endif /* __XTI_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/pcu.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/pcu.c deleted file mode 100644 index 9b943a893..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/pcu.c +++ /dev/null @@ -1,139 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : pcu.c -* Author : MCD Application Team -* Date First Issued : 09/09/03 -* Description : This file provides all the Power Control Unit functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "pcu.h" -#include "rccu.h" - -/******************************************************************************* -* Function Name : PCU_VRConfig -* Description : This routine is used to configure PCU voltage regultors -* Input 1 : MVR : Main voltage Regulator - LPR : Low Power Regulator -* Input 2 : ENABLE : Enable the Voltage Regulator - DISABLE: Disable ( ByPass ) the VR -* Return : None -*******************************************************************************/ -void PCU_VRConfig ( PCU_VR Xvr, FunctionalState NewState ) -{ - u16 Tmp = PCU->PWRCR; - switch ( Xvr ) - { - case PCU_MVR : - // Configure the Main Voltage Regulator - if (NewState == DISABLE) Tmp |= PCU_MVR_Mask; else Tmp &= ~PCU_MVR_Mask; - break; - case PCU_LPR : - // Configure the Low power Voltage Regulator - if (NewState == DISABLE) Tmp |= PCU_LPR_Mask; else Tmp &= ~PCU_LPR_Mask; - break; - } - // Unlock Power Control Register - PCU->PWRCR |= PCU_WREN_Mask; - PCU->PWRCR = Tmp | PCU_WREN_Mask; -} - -/******************************************************************************* -* Function Name : PCU_WFIEnter -* Description : This routine is used to force the Device to enter in WFI mode -* Input 1 : CLOCK2_16 : Clock2_16 as system clock for WFI mode -* EXTERNAL : external clock as system clock for WFI mode -* Input 2 : ENABLE : Enable Low Power Regulator during Wait For Interrupt Mode -* DISABLE: Disable Low Power Regulator during Wait For Interrupt Mode -* Input 3 : ENABLE : Enable Low Power Mode during Wait For Interrupt Mode -* DISABLE: Disable Low Power Mode during Wait For Interrupt Mode -* Return : None -*******************************************************************************/ -void PCU_WFIEnter ( WFI_CLOCKS Xclock, FunctionalState Xlpr, FunctionalState Xlpm ) -{ - u32 Tmp; - // Enable Low Power Regulator in WFI mode - Tmp = PCU->PWRCR; - // Unlock Power Control Register - PCU->PWRCR |= PCU_WREN_Mask; - PCU->PWRCR = Xlpr == ENABLE ? Tmp & ~PCU_LPRWFI_Mask : Tmp | PCU_LPRWFI_Mask; - // WFI Clock Selection - Tmp = RCCU->CCR; - RCCU->CCR = Xclock == WFI_CLOCK2_16 ? Tmp & ~PCU_WFI_CKSEL_Mask : Tmp | PCU_WFI_CKSEL_Mask; - // Low Power Mode during WFI mode - Tmp = RCCU->CCR; - RCCU->CCR = Xlpm == DISABLE ? Tmp & ~PCU_LPOWFI_Mask : Tmp | PCU_LPOWFI_Mask; - // Enter WFI Mode - RCCU->SMR &= ~0x0001; -} - -/******************************************************************************* -* Function Name : PCU_LPMEnter -* Description : This routine is used to force the device to enter in low -* power modes -* Input : PCU_SLOW : Slow Mode - PCU_STOP : Stop Mode - PCU_STANDBY : StandBy Mode -* Return : None -*******************************************************************************/ -void PCU_LPMEnter ( LPM_MODES Xmode ) -{ - u32 temp; - switch ( Xmode ) - { - // Slow Mode - case PCU_SLOW: - { - RCCU->PLL1CR |= 0x87; - RCCU_RCLKSourceConfig ( RCCU_PLL1_Output ); - break; - } - - // Stop Mode - case PCU_STOP: - { - // Enable Stop EN bit - RCCU->CCR |= PCU_STOP_EN_Mask; - - // Write '1' to Stop Bit - XTI->CTRL |= 0x04; - // Write '0' to Stop Bit - XTI->CTRL &= 0x03; - // Write '1' to Stop Bit - XTI->CTRL |= 0x04; - // add Delay - - temp = 0; - temp = 1; - temp = 2; - temp = 3; - temp = 4; - temp = 5; - temp = 6; - temp = 7; - temp = 8; - - break; - - } - // PCU_STANDBY Mode - case PCU_STANDBY: - { - PCU->PWRCR |= PCU_WREN_Mask; // Unlock Power Control Register - PCU->PWRCR |= PCU_PWRDWN_Mask; // Set the Power Down flag - } - } -} -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/rccu.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/rccu.c deleted file mode 100644 index 7de93580b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/rccu.c +++ /dev/null @@ -1,185 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : rccu.c -* Author : MCD Application Team -* Date First Issued : 07/28/2003 -* Description : This file provides all the RCCU software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#include "rccu.h" - -/******************************************************************************* -* Function Name : RCCU_PLL1Config -* Description : Configures the PLL1 div & mul factors. -* Input : New_Mul ( RCCU_PLL1_Mul_12, RCCU_PLL1_Mul_16, RCCU_PLL1_Mul_20, -* RCCU_PLL1_Mul_24 ) -* : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, -* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7) -* Return : None -*******************************************************************************/ -void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div ) -{ - u32 Tmp = ( RCCU->PLL1CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index ); - RCCU->PLL1CR = ( Tmp & ~RCCU_DX_Mask ) | New_Div | 0x40; -} - -/******************************************************************************* -* Function Name : RCCU_PLL2Config -* Description : Configures the PLL2 div & mul factors. -* Input : New_Mul ( RCCU_PLL2_Mul_12, RCCU_PLL2_Mul_16, RCCU_PLL2_Mul_20, -* RCCU_Mul_PLL2_28 ) -* : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, -* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7) -* Return : None -*******************************************************************************/ -void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div ) -{ - u32 Tmp = ( PCU->PLL2CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index ); - PCU->PLL2CR = ( Tmp & ~RCCU_DX_Mask ) | ( New_Div | RCCU_FREEN_Mask ); -} - -/******************************************************************************* -* Function Name : RCCU_RCLKSourceConfig -* Description : Selects the RCLK source clock -* Input : New_Clock ( RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 ) -* Return : None -*******************************************************************************/ -void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock ) -{ - switch ( New_Clock ) - { - case RCCU_CLOCK2 :{// Resets the CSU_Cksel bit in clk_flag - RCCU->CFR &= ~RCCU_CSU_CKSEL_Mask; - // Set the CK2_16 Bit in the CFR - RCCU->CFR |= RCCU_CK2_16_Mask; - // Deselect The CKAF - RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; - // switch off the PLL1 - RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\ - |0x00000003) & ~RCCU_FREEN_Mask; - break;} - case RCCU_CLOCK2_16 :{// ReSet the CK2_16 Bit in the CFR - RCCU->CFR &= ~RCCU_CK2_16_Mask; - // Deselect The CKAF - RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; - // switch off the PLL1 - RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\ - |0x00000003) & ~RCCU_FREEN_Mask; - break;} - case RCCU_PLL1_Output:{// Set the CK2_16 Bit in the CFR - RCCU->CFR = RCCU->CFR | RCCU_CK2_16_Mask; - // Waits the PLL1 to lock if DX bits are different from '111' - // If all DX bit are set the PLL lock flag in meaningless - if (( RCCU->PLL1CR & 0x0007 ) != 7) - while(!(RCCU->CFR & RCCU_LOCK_Mask)); - // Deselect The CKAF - RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; - // Select The CSU_CKSEL - RCCU->CFR |= RCCU_CSU_CKSEL_Mask; - break;} - case RCCU_RTC_CLOCK : {RCCU->CCR |= 0x04; - break;} - } -} - -/******************************************************************************* -* Function Name : RCCU_RCLKClockSource -* Description : Returns the current RCLK source clock -* Input : None -* Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2, RCCU_RTC_CLOCK -*******************************************************************************/ -RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void ) -{ - if ((RCCU->CCR & 0x04)==0x04) - return RCCU_RTC_CLOCK; - - else if ((RCCU->CFR & RCCU_CK2_16_Mask)==0) - return RCCU_CLOCK2_16; - - else if (RCCU->CFR & RCCU_CSU_CKSEL_Mask) - return RCCU_PLL1_Output; - - else - return RCCU_CLOCK2; -} - -/******************************************************************************* -* Function Name : RCCU_USBClockSource -* Description : Gets the RCLK source clock -* Input : None -* Return : RCCU_USB_Clocks ( RCCU_PLL2_Output, RCCU_USBCK ) -*******************************************************************************/ -RCCU_USB_Clocks RCCU_USBClockSource ( void ) -{ - if ((PCU->PLL2CR & RCCU_USBEN_Mask ) >> RCCU_USBEN_Index == 1 ) - return RCCU_PLL2_Output; - else return RCCU_USBCK; -} - -/******************************************************************************* -* Function Name : RCCU_FrequencyValue -* Description : Calculates & Returns any internal RCCU clock frequency -* passed in parametres -* Input : RCCU_Clocks ( RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, RCCU_PCLK, RCCU_FCLK ) -* Return : u32 -*******************************************************************************/ -u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk ) -{ - u32 Tmp; - u8 Div = 0; - u8 Mul = 0; - RCCU_RCLK_Clocks CurrentRCLK; - - Tmp = ( RCCU_Div2Status() == SET )? RCCU_Main_Osc / 2 : RCCU_Main_Osc; - - if ( Internal_Clk == RCCU_CLK2 ) - { - Div = 1; - Mul = 1; - } - else - { CurrentRCLK = RCCU_RCLKClockSource (); - switch ( CurrentRCLK ){ - case RCCU_CLOCK2_16 : Div = 16; - Mul = 1; - break; - case RCCU_CLOCK2 : Div = 1; - Mul = 1; - break; - case RCCU_PLL1_Output :{Mul=(RCCU->PLL1CR & RCCU_MX_Mask ) >> RCCU_MX_Index; - switch ( Mul ) - {case 0: Mul = 20; break; - case 1: Mul = 12; break; - case 2: Mul = 24; break; - case 3: Mul = 16; break; - } - Div = ( RCCU->PLL1CR & RCCU_DX_Mask ) + 1; - break;} - case RCCU_RTC_CLOCK : Mul = 1; - Div = 1; - Tmp = RCCU_RTC_Osc; - break;}} - - switch ( Internal_Clk ){ - case RCCU_MCLK :{Div <<= PCU->MDIVR & RCCU_FACT_Mask; - break;} - case RCCU_PCLK :{Div <<=(PCU->PDIVR & RCCU_FACT2_Mask ) >> RCCU_FACT2_Index; - break;} - case RCCU_FCLK :{Div <<= PCU->PDIVR & 0x3; - break;}} - - return (Tmp * Mul) / Div; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/rtc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/rtc.c deleted file mode 100644 index 8adab4f46..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/rtc.c +++ /dev/null @@ -1,232 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : rtc.c -* Author : MCD Application Team -* Date First Issued : 09/30/2003 -* Description : This file provides all the RTC software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "rtc.h" - -// Global interrupt -#define RTC_GI_Mask 0x0008 -#define RTC_GI_Index 3 - -// OverFlow interrupt -#define RTC_OWI_Mask 0x0004 -#define RTC_OWI_Index 2 - -// Alarm interrupt -#define RTC_AI_Mask 0x0002 -#define RTC_AI_Index 1 - -// Second interrupt -#define RTC_SI_Mask 0x0001 - -// Configuration Flag Mask -#define RTC_CNF_Mask 0x0010 - -// Operation OFF flag -#define RTC_RTOFF_Mask 0x0020 - -/******************************************************************************* -* Function Name : RTC_Delay -* Description : This routine is used to insert a delay -* Input : None -* Return : None -*******************************************************************************/ -void RTC_Delay( void ) -{ - u16 _Tmp; - for (_Tmp = 0x0; _Tmp < 0x7F; _Tmp ++); -} - -/******************************************************************************* -* Function Name : RTC_CounterConfig -* Description : This routine is used to update the RTC counter value -* Input : The new counter value. -* Return : None -*******************************************************************************/ -void RTC_CounterConfig (u32 CounterValue) -{ - /* Wait For Last Task Completition */ - RTC_WaitForLastTask(); - - /* Enter to configuration mode */ - RTC_EnterCfgMode(); - - /* Wait For Last Task Completition */ - RTC_WaitForLastTask(); - -/* Update the RTC counter register with the new time and date */ - /* Update the CNTL register */ - RTC->CNTL = (u16)CounterValue; - - /* Wait For Last Task Completition */ - RTC_WaitForLastTask(); - - /* Update the CNTH register */ - RTC->CNTH = (u16)(CounterValue >> 16); - - /* Wait For Last Task Completition */ - RTC_WaitForLastTask(); - - /* Exit From Configuration Mode */ - RTC_ExitCfgMode (); -} - -/******************************************************************************* -* Function Name : RTC_PrescalerConfig -* Description : This routine is used to set the Prescaler Value -* Input : The New prescaler Value -* Return : None -*******************************************************************************/ -void RTC_PrescalerConfig (u32 Xprescaler) -{ - if ( RTC_PrescalerValue () != Xprescaler ) - { - // Wait For Last Task Completion - RTC_WaitForLastTask (); - // Enter In Configuration Mode - RTC_EnterCfgMode (); - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Set the prescaler MSB part - RTC->PRLH = (Xprescaler & 0x000F0000) >> 16; - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Set the prescaler LSB part - RTC->PRLL = (Xprescaler & 0x0000FFFF); - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Exit From Configuration Mode - RTC_ExitCfgMode (); - // Wait For Last Task Completion - RTC_WaitForLastTask (); - } -} - -/******************************************************************************* -* Function Name : RTC_AlarmConfig -* Description : This routine is used to set the RTC alarm Value -* Input : an u32 value that holds the Real Time clock alarm time. -* Return : None -*******************************************************************************/ -void RTC_AlarmConfig (u32 Xalarm) -{ - // Wait For Last Task Completion - RTC_WaitForLastTask (); - // Enter In Configuration Mode - RTC_EnterCfgMode (); - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Set The MSB part of the Alarm Time - RTC->ALRH = (Xalarm & 0xFFFF0000) >> 16; - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Set The LSB part of the Alarm Time - RTC->ALRL = (Xalarm & 0x0000FFFF); - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Exit From Configuration Mode - RTC_ExitCfgMode (); - // Wait For Last Task Completion - RTC_WaitForLastTask (); -} - -/******************************************************************************* -* Function Name : RTC_FlagClear -* Description : This routine is used to clear the RTC flags -* Input : an RTC flag -* Return : None -*******************************************************************************/ -void RTC_FlagClear (RTC_FLAGS Xflag) -{ - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Enter In Configuration Mode - RTC_EnterCfgMode(); - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Clear an RTC flag - RTC->CRL &= ~Xflag; - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Exit From Configuration Mode - RTC_ExitCfgMode (); - // Wait For Last Task Completion - RTC_WaitForLastTask(); -} - -/******************************************************************************* -* Function Name : RTC_ITClear -* Description : This routine is used to clear the RTC interrupts -* Input : an RTC interrupt -* Return : None -*******************************************************************************/ -void RTC_ITClear (RTC_IT Xrtcit) -{ - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Enter In Configuration Mode - RTC_EnterCfgMode(); - // Clears an RTC interrupt - RTC->CRL &= ~Xrtcit; - // Exit From Configuration Mode - RTC_ExitCfgMode (); - // Wait For Last Task Completion - RTC_WaitForLastTask (); -} - -/******************************************************************************* -* Function Name : RTC_EnterCfgMode -* Description : This routine is used to enter in the Configuration Mode -* Input : None -* Return : None -*******************************************************************************/ -void RTC_EnterCfgMode(void) -{ - // Set the CNF flag to enter in the Configuration Mode - RTC->CRL |= RTC_CNF_Mask; - // Wait For Last Task Completion - RTC_WaitForLastTask (); -} - -/******************************************************************************* -* Function Name : RTC_ExitCfgMode -* Description : This routine is used to exit from the Configuration Mode -* Input : None -* Return : None -*******************************************************************************/ -void RTC_ExitCfgMode(void) -{ - // Reset the CNF flag to exit from the Configuration Mode - RTC->CRL &= ~RTC_CNF_Mask; - // Wait For Last Task Completion - RTC_WaitForLastTask (); -} - -/******************************************************************************* -* Function Name : RTC_WaitForLastTask -* Description : This routine waits for the last task completion -* Input : None -* Return : None -*******************************************************************************/ -void RTC_WaitForLastTask(void) -{ - // Loop until the Last operation Completion - while (!(RTC->CRL & RTC_RTOFF_Mask)); -} -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/tim.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/tim.c deleted file mode 100644 index f6d2ab195..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/tim.c +++ /dev/null @@ -1,233 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : tim.c -* Author : MCD Application Team -* Date First Issued : 09/08/2003 -* Description : This file provides all the TIM software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "tim.h" - -/******************************************************************************* -* Function Name : TIM_Init -* Description : This routine is used to Initialize the TIM peripheral -* Input : TIM Timer to Initialize -* Return : None -*******************************************************************************/ -void TIM_Init( TIM_TypeDef *TIMx ) -{ - TIMx->CR1 = 0x0000; - TIMx->CR2 = 0x0000; - TIMx->SR = 0x0000; -} - -/******************************************************************************* -* Function Name : TIM_ICAPModeConfig -* Description : This routine is used to configure the input capture feature -* Input : (1) TIM Timer -* : (2) Input Capture Channel ( Channel_A or Channel_B ) -* : (3) Active Edge : Rising edge or Falling edge. -* Output : None -*******************************************************************************/ -void TIM_ICAPModeConfig ( TIM_TypeDef *TIMx, - TIM_Channels Xchannel, - TIM_Clock_Edges Xedge ) -{ - switch (Xchannel) - { - case TIM_CHANNEL_A : - if (Xedge == TIM_RISING) TIMx->CR1 |= TIM_IEDGA_Mask; else TIMx->CR1 &= ~TIM_IEDGA_Mask; - break; - case TIM_CHANNEL_B : - if (Xedge == TIM_RISING) TIMx->CR1 |= TIM_IEDGB_Mask; else TIMx->CR1 &= ~TIM_IEDGB_Mask; - break; - } -} - -/******************************************************************************* -* Function Name : TIM_OCMPModeConfig -* Description : This routine is used to configure the output compare feature -* Input : (1) TIM Timer -* : (2) OCMP Channel ( Channel_A or Channel_B ) -* : (3) Pulse Length -* : (4) OC_Mode : output wave, or only timing. -* : (5) Level : Rising edge or Falling edge after the == -* Output : None -*******************************************************************************/ -void TIM_OCMPModeConfig ( TIM_TypeDef *TIMx, - TIM_Channels Xchannel, - u16 XpulseLength, - TIM_OC_Modes Xmode, - TIM_Logic_Levels Xlevel ) -{ - u16 Tmp1 = 0x0000; - u16 Tmp2 = TIMx->CR2; - - TIMx->CR2 = 0x0000; - // Start The TIM Counter - TIMx->CR1 = TIM_EN_Mask; - // Update the CR2 Register - TIMx->CR2 = Tmp2; - switch ( Xmode ) - { - case TIM_TIMING : - // Output Compare Used only for Internal Timing Operation - Tmp1 = Xchannel == TIM_CHANNEL_A ? Tmp1 & ~TIM_OCAE_Mask : Tmp1 & ~TIM_OCBE_Mask; - break; - case TIM_WAVE : - // Output Compare Used for external wave generation - Tmp1 = Xchannel == TIM_CHANNEL_A ? TIM_OCAE_Mask : TIM_OCBE_Mask; - if ( Xlevel == TIM_HIGH ) - Tmp1 = Xchannel == TIM_CHANNEL_A ? Tmp1 | TIM_OLVLA_Mask : Tmp1 | TIM_OLVLB_Mask; - else - Tmp1 = Xchannel == TIM_CHANNEL_A ? Tmp1 & ~TIM_OLVLA_Mask : Tmp1 & ~TIM_OLVLB_Mask; - break; - } - if ( Xchannel == TIM_CHANNEL_A ) - TIMx->OCAR = ( XpulseLength); - else - TIMx->OCBR = ( XpulseLength); - TIMx->CNTR = 0x0000; - TIMx->CR1 |= Tmp1; -} - -/******************************************************************************* -* Function Name : TIM_OPModeConfig -* Description : This routine is used to configure the one pulse mode -* Input : (1) TIM Timer -* : (3) XpulseLength : Length of the pulse -* : (4) Level1 : Level during the pulse -* : (5) Level2 : Level after the pulse -* : (6) Activation Edge : High or Low on ICAP A -* Output : None -*******************************************************************************/ -void TIM_OPModeConfig ( TIM_TypeDef *TIMx, - u16 XpulseLength, - TIM_Logic_Levels XLevel1, - TIM_Logic_Levels XLevel2, - TIM_Clock_Edges Xedge ) -{ - u16 Tmp = 0; - - // Set the Level During the pulse - if (XLevel1 == TIM_HIGH) Tmp |= TIM_OLVLB_Mask; - // Set the Level after After the pulse - if (XLevel2 == TIM_HIGH) Tmp |= TIM_OLVLA_Mask; - // Set the Activation Edge on the INCAP 1 - if (Xedge == TIM_RISING) Tmp |= TIM_IEDGA_Mask; - // Set the Output Compare Function - Tmp |= TIM_OCAE_Mask; - // Set the One pulse mode - Tmp |= TIM_OMP_Mask; - // Update the CR1 register Value - TIMx->CR1 = Tmp; - // Set the Pulse length - TIMx->OCAR = XpulseLength; -} - -/******************************************************************************* -* Function Name : TIM_PWMOModeConfig -* Description : This routine is used to configure the PWM in output mode -* Input : (1) TIM Timer -* : (2) DutyCycle : u16 -* : (3) Level 1 : During the Duty Cycle -* : (4) Level 2 : During the after the pulse -* : (5) Full period : u16 -* Output : None -*******************************************************************************/ -void TIM_PWMOModeConfig ( TIM_TypeDef *TIMx, - u16 XDutyCycle, - TIM_Logic_Levels XLevel1, - u16 XFullperiod, - TIM_Logic_Levels XLevel2 - ) -{ - u16 Tmp = TIMx->CR1; - // Set the Level During the pulse - Tmp = XLevel1 == TIM_HIGH ? Tmp | TIM_OLVLB_Mask : Tmp & ~TIM_OLVLB_Mask; - // Set the Level after After the pulse - Tmp = XLevel2 == TIM_HIGH ? Tmp | TIM_OLVLA_Mask : Tmp & ~TIM_OLVLA_Mask; - // Set the OCAE - Tmp |= TIM_OCAE_Mask; - // Set the PWM Bit - Tmp |= TIM_PWM_Mask; - // Update the CR1 - TIMx->CR1 = Tmp; - // Set the Duty Cycle value - if ( XDutyCycle < 5 ) XDutyCycle = 5; - TIMx->OCAR = XDutyCycle - 5; - // Set the Full Period - TIMx->OCBR = XFullperiod - 5; -} - -/******************************************************************************* -* Function Name : TIM_PWMInputConfig -* Description : This routine is used to configure the PWM in input mode -* Input : (1) TIM Timer -* : (2) First Activation Edge -* Output : None -*******************************************************************************/ -void TIM_PWMIModeConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge ) -{ - u16 Tmp = TIMx->CR1; - // Set the first edge Level - Tmp = Xedge == TIM_RISING ? Tmp | TIM_IEDGA_Mask : Tmp & ~TIM_IEDGA_Mask; - // Set the Second edge Level ( Opposit of the first level ) - Tmp = Xedge == TIM_FALLING ? Tmp | TIM_IEDGB_Mask : Tmp & ~TIM_IEDGB_Mask; - // Set the PWM I Bit - Tmp |= TIM_PWMI_Mask; - // Update the CR1 - TIMx->CR1 = Tmp; -} - -/******************************************************************************* -* Function Name : TIM_PWMIValue -* Description : This routine is used to get the PWMI values -* Input : (1) TIM Timer -* Output : PWMI_parameters : - u16 Dyty cycle - - u16 Full period -*******************************************************************************/ -PWMI_parameters TIM_PWMIValue ( TIM_TypeDef *TIMx ) -{ - PWMI_parameters Tmp; - Tmp.Pulse = TIMx->ICBR; - Tmp.Period = TIMx->ICAR; - return Tmp; -} - -/******************************************************************************* -* Function Name : TIM_PWMInputConfig -* Description : This routine is used to configure the PWM in input mode -* Input : (1) TIM Timer -* : (2) First Activation Edge -* Output : None -*******************************************************************************/ -void TIM_CounterConfig ( TIM_TypeDef *TIMx, TIM_CounterOperations Xoperation ) -{ - switch ( Xoperation ) - { - case TIM_START : - TIMx->CR1 |= TIM_EN_Mask; - break; - case TIM_STOP : - TIMx->CR1 &= ~TIM_EN_Mask; - break; - case TIM_CLEAR : - TIMx->CNTR = 0x1234; - break; - } -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/uart.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/uart.c deleted file mode 100644 index 0a74681ff..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/uart.c +++ /dev/null @@ -1,366 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : uart.c -* Author : MCD Application Team -* Date First Issued : 06/08/2003 -* Description : This file provides all the UART software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "uart.h" - -/******************************************************************************* -* Function Name : UART_Init -* Description : This function initializes the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Output : None -* Return : None -*******************************************************************************/ -void UART_Init(UART_TypeDef *UARTx) -{ - UARTx->IER = 0x00; - UARTx->CR = 0x00; - (void)UARTx->RxBUFR; - UARTx->RxRSTR = 0xFFFF; - UARTx->TxRSTR = 0xFFFF; -} - -/******************************************************************************* -* Function Name : UART_BaudRateConfig -* Description : This function configures the baud rate of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The baudrate value -* Output : None -* Return : None -*******************************************************************************/ -void UART_BaudRateConfig(UART_TypeDef *UARTx, u32 BaudRate) -{ - UARTx->BR = (u16)(RCCU_FrequencyValue(RCCU_FCLK)/(16*BaudRate)); -} - -/******************************************************************************* -* Function Name : UART_Config -* Description : This function configures the baudrate, the mode, the data -* parity and the number of stop bits of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The baudrate value -* Input 3 : The parity type -* Input 4 : The number of stop bits -* Input 5 : The UART mode -* Output : None -* Return : None -*******************************************************************************/ -void UART_Config(UART_TypeDef *UARTx, u32 BaudRate, UARTParity_TypeDef Parity, - UARTStopBits_TypeDef StopBits, UARTMode_TypeDef Mode) -{ - UART_ModeConfig(UARTx, Mode); - UART_BaudRateConfig(UARTx, BaudRate); - UART_ParityConfig(UARTx, Parity); - UART_StopBitsConfig(UARTx, StopBits); -} - -/******************************************************************************* -* Function Name : UART_ItConfig -* Description : This function enables or disables the interrupts of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The new interrupt flag -* Input 3 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_ItConfig(UART_TypeDef *UARTx, u16 UART_Flag, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->IER|=UART_Flag; else UARTx->IER&=~UART_Flag; -} - -/******************************************************************************* -* Function Name : UART_FifoConfig -* Description : This function enables or disables the Rx and Tx FIFOs of -* the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_FifoConfig(UART_TypeDef *UARTx, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->CR|=0x0400; else UARTx->CR&=~0x0400; -} - -/******************************************************************************* -* Function Name : UART_FifoReset -* Description : This function resets the Rx and the Tx FIFOs of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : UART_RxFIFO or UART_TxFIFO -* Output : None -* Return : None -*******************************************************************************/ -void UART_FifoReset(UART_TypeDef *UARTx, UARTFIFO_TypeDef FIFO) -{ - if (FIFO==UART_RxFIFO) UARTx->RxRSTR=0xFFFF; else UARTx->TxRSTR=0xFFFF; -} - -/******************************************************************************* -* Function Name : UART_LoopBackConfig -* Description : This function enables or disables the loop back mode of -* the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_LoopBackConfig(UART_TypeDef *UARTx, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->CR|=0x0040; else UARTx->CR&=~0x0040; -} - -/******************************************************************************* -* Function Name : UART_RxConfig -* Description : This function enables or disables the UART data reception. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_RxConfig(UART_TypeDef *UARTx, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->CR|=0x0100; else UARTx->CR&=~0x0100; -} - -/******************************************************************************* -* Function Name : UART_OnOffConfig -* Description : This function sets On/Off the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_OnOffConfig(UART_TypeDef *UARTx, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->CR|=0x0080; else UARTx->CR&=~0x0080; -} - -/******************************************************************************* -* Function Name : UART_ByteSend -* Description : This function sends a data byte to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data byte to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_ByteSend(UART_TypeDef *UARTx, u8 *Data) -{ - if (UARTx->CR & (0x0001<SR & UART_TxFull)); // while the UART_TxFIFO contain 16 characters. - else // if FIFO DISABLED - while (!(UARTx->SR & UART_TxEmpty)); // while the transmit shift register not empty - UARTx->TxBUFR = *Data; -} - -/******************************************************************************* -* Function Name : UART_9BitByteSend -* Description : This function sends a 9 bits data byte to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_9BitByteSend(UART_TypeDef *UARTx, u16 *Data) -{ - if(UARTx->CR & (0x0001<SR & UART_TxFull)); // while the UART_TxFIFO contain 16 characters. - else // if FIFO DISABLED - while (!(UARTx->SR & UART_TxEmpty)); // while the transmit shift register not empty - UARTx->TxBUFR = *Data; -} - -/******************************************************************************* -* Function Name : UART_DataSend -* Description : This function sends several data bytes to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Input 3 : The data length in bytes -* Output : None -* Return : None -*******************************************************************************/ -void UART_DataSend(UART_TypeDef *UARTx, u8 *Data, u8 DataLength) -{ - while(DataLength--) - { - UART_ByteSend(UARTx,Data); - Data++; - } -} - -/******************************************************************************* -* Function Name : UART_9BitDataSend -* Description : This function sends several 9 bits data bytes to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Input 3 : The data length -* Output : None -* Return : None -*******************************************************************************/ -void UART_9BitDataSend(UART_TypeDef *UARTx, u16 *Data, u8 DataLength) -{ - while(DataLength--) - { - UART_9BitByteSend(UARTx,Data); - Data++; - } -} - -/******************************************************************************* -* Function Name : UART_StringSend -* Description : This function sends a string to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the string to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_StringSend(UART_TypeDef *UARTx, u8 *String) -{ - u8 *Data=String; - while(*Data != '\0') - UART_ByteSend(UARTx, Data++); - *Data='\0'; - UART_ByteSend(UARTx, Data); -} - -/******************************************************************************* -* Function Name : UART_ByteReceive -* Description : This function gets a data byte from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The time-out period -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_ByteReceive(UART_TypeDef *UARTx, u8 *Data, u8 TimeOut) -{ - u16 wStatus; - UARTx->TOR=TimeOut;// reload the Timeout counter - while (!((wStatus=UARTx->SR) & (UART_TimeOutIdle|UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle - *Data = (u8)UARTx->RxBUFR; // then read the Receive Buffer Register - return wStatus; -} - -/******************************************************************************* -* Function Name : UART_9BitByteReceive -* Description : This function gets a 9 bits data byte from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The time-out period value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_9BitByteReceive(UART_TypeDef *UARTx, u16 *Data, u8 TimeOut) -{ - u16 wStatus; - UARTx->TOR=TimeOut;// reload the Timeout counter - while (!((wStatus=UARTx->SR) & (UART_TimeOutIdle|UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle - *Data = (u16)UARTx->RxBUFR; // then read the RxBUFR - return wStatus; -} - -/******************************************************************************* -* Function Name : UART_DataReceive -* Description : This function gets 8 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The data length -* Input 4 : The time-out period value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_DataReceive(UART_TypeDef *UARTx, u8 *Data, u8 DataLength, u8 TimeOut) -{ - u16 wStatus; - while(DataLength--) - wStatus=UART_ByteReceive(UARTx,Data++,TimeOut); - return wStatus; -} - -/******************************************************************************* -* Function Name : UART_9BitDataReceive -* Description : This function gets 9 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The data length -* Input 4 : The time-out value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_9BitDataReceive(UART_TypeDef *UARTx, u16 *Data, u8 DataLength, u8 TimeOut) -{ - u16 wStatus; - while(DataLength--) - wStatus=UART_9BitByteReceive(UARTx,Data++,TimeOut); - return wStatus; -} - -/******************************************************************************* -* Function Name : UART_StringReceive -* Description : This function gets 8 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the string will be stored -* Output : The received string -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_StringReceive(UART_TypeDef *UARTx, u8 *Data) -{ - u8 *pSTRING=Data; - u16 wStatus; - do - { - while (!((wStatus=UARTx->SR) & (UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle - *(pSTRING++) = (u8)UARTx->RxBUFR; // then read the RxBUFR - } while((*(pSTRING - 1)!=0x0D)&(*(pSTRING - 1)!='\0')); - *(pSTRING - 1)='\0'; - return wStatus; -} - -#ifdef USE_SERIAL_PORT -/******************************************************************************* -* Function Name : sendchar -* Description : This function sends a character to the selected UART. -* Input 1 : A pointer to the character to send. -* Output : None -* Return : None -*******************************************************************************/ -void sendchar( char *ch ) -{ - #ifdef USE_UART0 - #define UARTx UART0 - #endif /* Use_UART0 */ - - #ifdef USE_UART1 - #define UARTx UART1 - #endif /* Use_UART1 */ - - #ifdef USE_UART2 - #define UARTx UART2 - #endif /* Use_UART2 */ - - #ifdef USE_UART3 - #define UARTx UART3 - #endif /* Use_UART3 */ - - UART_ByteSend(UARTx,(u8 *)ch); -} -#endif /* USE_SERIAL_PORT */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/wdg.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/wdg.c deleted file mode 100644 index 1ae16cf54..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/wdg.c +++ /dev/null @@ -1,84 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : WDG.c -* Author : MCD Application Team -* Date First Issued : 10/24/2003 -* Description : This file provides all the WDG software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "wdg.h" - -#ifndef abs - #define abs(x) ((x)>0 ? (x) : -(x)) -#endif - -/******************************************************************************* -* Function Name : FindFactors -* Description : Search for the best (a,b) values that fit n = a*b -* with the following constraints: 1<=a<=256, 1<=b<=65536 -* Input 1 : n: the number to decompose -* Input/Output 2 : a: a pointer to the first factor -* Input/Output 3 : b: a pointer to the second factor -* Return : None -*******************************************************************************/ -static void FindFactors(unsigned long n, unsigned int *a, unsigned long *b) -{ - unsigned long b0; - unsigned int a0; - long err, err_min=n; - - *a = a0 = ((n-1)/65536ul) + 1; - *b = b0 = n / *a; - - for (; *a <= 256; (*a)++) - { - *b = n / *a; - err = (long)*a * (long)*b - (long)n; - if (abs(err) > (*a / 2)) - { - (*b)++; - err = (long)*a * (long)*b - (long)n; - } - if (abs(err) < abs(err_min)) - { - err_min = err; - a0 = *a; - b0 = *b; - if (err == 0) break; - } - } - - *a = a0; - *b = b0; -} - -/******************************************************************************* -* Function Name : WDG_PeriodValueConfig -* Description : Set the prescaler and counter reload value -* Input : Amount of time (us) needed -* Return : None -*******************************************************************************/ -void WDG_PeriodValueConfig ( u32 Time ) -{ - unsigned int a; - unsigned long n, b; - - n = Time * (RCCU_FrequencyValue(RCCU_PCLK) / 1000000); - FindFactors(n, &a, &b); - WDG->PR = a - 1; - WDG->VR = b - 1; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/xti.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/xti.c deleted file mode 100644 index 3e23dbfb0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/library/xti.c +++ /dev/null @@ -1,87 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : xti.c -* Author : MCD Application Team -* Date First Issued : 06/08/2003 -* Description : This file provides all the XTI software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "xti.h" - -/******************************************************************************* -* Function Name : XTI_Init -* Description : Initialize the XTI -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -void XTI_Init(void) -{ - XTI->SR=0x00; - XTI->MRH=0x00; - XTI->MRL=0x00; - XTI->TRH=0x00; - XTI->TRL=0x00; - XTI->PRH=0x00; - XTI->PRL=0x00; - XTI->CTRL=0x00; /* Write the STOP bit twice to reset the STOP state machine */ - XTI->CTRL=0x00; -} - -/******************************************************************************* -* Function Name : XTI_LineModeConfig -* Description : Configure the trigger edge. -* Input 1 : Lines to be configured. -* Input 2 : The trigger edge can be FallingEdge or RisingEdge. -* Output : None -* Return : None -*******************************************************************************/ -void XTI_LineModeConfig(u16 Lines, XTITriggerEdge_TypeDef TriggerEdge) -{ - if(TriggerEdge == XTI_FallingEdge) - { - XTI->TRL &= ~Lines; - XTI->TRH &= ~(Lines>>8)&0x00FF; - } - else - { - XTI->TRL |= Lines; - XTI->TRH |= (Lines>>8)&0x00FF; - } -} - -/******************************************************************************* -* Function Name : XTI_LineConfig -* Description : Enable and disable lines interrupts -* Input 1 : Lines to be configured. -* Input 2 : NewState can be ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void XTI_LineConfig(u16 Lines, FunctionalState NewState) -{ - if(NewState) - { - XTI->MRL |= Lines; - XTI->MRH |= (Lines>>8)&0x00FF; - } - else - { - XTI->MRL &= ~Lines; - XTI->MRH &= ~(Lines>>8)&0x00FF; - } -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/port/port.h deleted file mode 100644 index d764bea0d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/port/port.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * FreeModbus Libary: STR71x Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -#include "assert.h" -#include "FreeRTOS.h" - -/* work aroung a problem when inline is also defined in 71x_conf.h */ -#ifdef INLINE -#undef INLINE -#endif - -#define INLINE inline - -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#define ENTER_CRITICAL_SECTION( ) portENTER_CRITICAL( ) -#define EXIT_CRITICAL_SECTION( ) portEXIT_CRITICAL( ) - -typedef char BOOL; - -typedef unsigned char UCHAR; -typedef char CHAR; - -typedef unsigned short USHORT; -typedef short SHORT; - -typedef unsigned long ULONG; -typedef long LONG; - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/port/portevent.c deleted file mode 100644 index d01d7e745..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/port/portevent.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * FreeModbus Libary: STR71x Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "assert.h" - -/* ----------------------- FreeRTOS -----------------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static xQueueHandle xMBPortQueueHdl; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - xMBPortQueueHdl = xQueueCreate( 1, sizeof( eMBEventType ) ); - return xMBPortQueueHdl != NULL ? TRUE : FALSE; -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - portBASE_TYPE xEventSent = pdFALSE; - - xEventSent = xQueueSendFromISR( xMBPortQueueHdl, &eEvent, xEventSent ); - return xEventSent == pdTRUE ? TRUE : FALSE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - BOOL xEventHappened = FALSE; - - if( xQueueReceive( xMBPortQueueHdl, eEvent, portMAX_DELAY ) == pdTRUE ) - { - xEventHappened = TRUE; - } - return xEventHappened; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/port/portserial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/port/portserial.c deleted file mode 100644 index 50315fbc1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/port/portserial.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - * FreeModbus Libary: STR71x Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "assert.h" - -/* ----------------------- FreeRTOS includes --------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" - -/* ----------------------- STR71X includes ----------------------------------*/ -#include "gpio.h" -#include "eic.h" -#include "uart.h" -#include "tim.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_UART_DEV ( UART0 ) -#define MB_UART_RX_PORT ( GPIO0 ) -#define MB_UART_RX_PIN ( 8 ) -#define MB_UART_TX_PORT ( GPIO0 ) -#define MB_UART_TX_PIN ( 9 ) -#define MB_UART_IRQ_CH ( UART0_IRQChannel ) -#define MB_UART_TX_QUEUE_LEN ( 8 ) -#define MB_IRQ_PRIORITY ( 1 ) - -/* ----------------------- Static functions ---------------------------------*/ -void prvvMBSerialIRQHandler( void ) __attribute__ ( ( naked ) ); - -static inline BOOL prvMBPortTXIsEnabled( ); - -static inline BOOL prvMBPortRXIsEnabled( ); - -/* ----------------------- Start implementation -----------------------------*/ - -BOOL -xMBPortSerialInit( UCHAR ucPort, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity ) -{ - BOOL xResult = TRUE; - UARTParity_TypeDef eUARTParity; - UARTMode_TypeDef eUARTMode; - - (void)ucPort; - - switch ( eParity ) - { - case MB_PAR_EVEN: - eUARTParity = UART_EVEN_PARITY; - break; - case MB_PAR_ODD: - eUARTParity = UART_ODD_PARITY; - break; - case MB_PAR_NONE: - eUARTParity = UART_NO_PARITY; - break; - } - - switch ( ucDataBits ) - { - case 7: - if( eParity == MB_PAR_NONE ) - { - /* not supported by our hardware. */ - xResult = FALSE; - } - else - { - eUARTMode = UARTM_7D_P; - } - break; - case 8: - if( eParity == MB_PAR_NONE ) - { - eUARTMode = UARTM_8D; - } - else - { - eUARTMode = UARTM_8D_P; - } - break; - default: - xResult = FALSE; - } - - if( xResult != FALSE ) - { - /* Setup the UART port pins. */ - GPIO_Config( MB_UART_TX_PORT, 1 << MB_UART_TX_PIN, GPIO_AF_PP ); - GPIO_Config( MB_UART_RX_PORT, 1 << MB_UART_RX_PIN, GPIO_IN_TRI_CMOS ); - - /* Configure the UART. */ - UART_OnOffConfig( MB_UART_DEV, ENABLE ); - UART_FifoConfig( MB_UART_DEV, DISABLE ); - UART_FifoReset( MB_UART_DEV, UART_RxFIFO ); - UART_FifoReset( MB_UART_DEV, UART_TxFIFO ); - UART_LoopBackConfig( MB_UART_DEV, DISABLE ); - UART_Config( MB_UART_DEV, ulBaudRate, eUARTParity, UART_1_StopBits, - eUARTMode ); - UART_RxConfig( UART0, ENABLE ); - vMBPortSerialEnable( FALSE, FALSE ); - - /* Configure the IEC for the UART interrupts. */ - EIC_IRQChannelPriorityConfig( MB_UART_IRQ_CH, MB_IRQ_PRIORITY ); - EIC_IRQChannelConfig( MB_UART_IRQ_CH, ENABLE ); - } - return xResult; -} - -void -vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable ) -{ - if( xRxEnable ) - UART_ItConfig( MB_UART_DEV, UART_RxBufFull, ENABLE ); - else - UART_ItConfig( MB_UART_DEV, UART_RxBufFull, DISABLE ); - - if( xTxEnable ) - UART_ItConfig( MB_UART_DEV, UART_TxHalfEmpty, ENABLE ); - else - UART_ItConfig( MB_UART_DEV, UART_TxHalfEmpty, DISABLE ); -} - -BOOL -xMBPortSerialPutByte( CHAR ucByte ) -{ - MB_UART_DEV->TxBUFR = ucByte; - return TRUE; -} - -BOOL -xMBPortSerialGetByte( CHAR * pucByte ) -{ - *pucByte = MB_UART_DEV->RxBUFR; - return TRUE; -} - -BOOL -prvMBPortTXIsEnabled( ) -{ - return ( MB_UART_DEV->IER & UART_TxHalfEmpty ) == UART_TxHalfEmpty; -} - -BOOL -prvMBPortRXIsEnabled( ) -{ - return ( MB_UART_DEV->IER & UART_RxBufFull ) == UART_RxBufFull; -} - - -void -prvvMBSerialIRQHandler( void ) -{ - portENTER_SWITCHING_ISR( ); - - static BOOL xTaskWokenReceive = FALSE; - static BOOL xTaskWokenTransmit = FALSE; - static USHORT usStatus; - - usStatus = UART_FlagStatus( MB_UART_DEV ); - - if( prvMBPortTXIsEnabled( ) && ( usStatus & UART_TxHalfEmpty ) ) - { - xTaskWokenReceive = pxMBFrameCBTransmitterEmpty( ); - } - if( prvMBPortRXIsEnabled( ) && ( usStatus & UART_RxBufFull ) ) - { - xTaskWokenReceive = pxMBFrameCBByteReceived( ); - } - - /* End the interrupt in the EIC. */ - EIC->IPR |= 1 << EIC_CurrentIRQChannelValue( ); - - portEXIT_SWITCHING_ISR( ( xTaskWokenReceive - || xTaskWokenTransmit ) ? pdTRUE : pdFALSE ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/port/porttimer.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/port/porttimer.c deleted file mode 100644 index 9bf341566..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/port/porttimer.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * FreeModbus Libary: STR71x Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "assert.h" - -/* ----------------------- FreeRTOS includes --------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" - -/* ----------------------- STR71X includes ----------------------------------*/ -#include "gpio.h" -#include "eic.h" -#include "uart.h" -#include "tim.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_TIMER_DEV ( TIM0 ) -#define MB_TIMER_PRESCALER ( 255UL ) -#define MB_TIMER_IRQ_CH ( T0TIMI_IRQChannel ) -#define MB_IRQ_PRIORITY ( 1 ) - -/* Timer ticks are counted in multiples of 50us. Therefore 20000 ticks are - * one second. - */ -#define MB_TIMER_TICKS ( 20000UL ) - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usTimerDeltaOCRA; - -/* ----------------------- Static functions ---------------------------------*/ -void prvvMBTimerIRQHandler( void ) __attribute__ ( ( naked ) ); - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortTimersInit( USHORT usTim1Timerout50us ) -{ - /* Calculate output compare value for timer1. */ - usTimerDeltaOCRA = - ( ( configCPU_CLOCK_HZ / ( MB_TIMER_PRESCALER + 1 ) ) * - usTim1Timerout50us ) / ( MB_TIMER_TICKS ); - - TIM_Init( MB_TIMER_DEV ); - TIM_PrescalerConfig( MB_TIMER_DEV, MB_TIMER_PRESCALER ); - if( usTimerDeltaOCRA > 0 ) - { - TIM_OCMPModeConfig( MB_TIMER_DEV, TIM_CHANNEL_A, usTimerDeltaOCRA, - TIM_TIMING, TIM_LOW ); - } - - vMBPortTimersDisable( ); - EIC_IRQChannelConfig( MB_TIMER_IRQ_CH, ENABLE ); - EIC_IRQChannelPriorityConfig( MB_TIMER_IRQ_CH, MB_IRQ_PRIORITY ); - - return TRUE; -} - -void -prvvMBTimerIRQHandler( void ) -{ - portENTER_SWITCHING_ISR( ); - - static portBASE_TYPE xTaskSwitch = pdFALSE; - - if( ( usTimerDeltaOCRA > 0 ) - && ( TIM_FlagStatus( MB_TIMER_DEV, TIM_OCFA ) ) ) - { - xTaskSwitch |= pxMBPortCBTimerExpired( ); - TIM_FlagClear( MB_TIMER_DEV, TIM_OCFA ); - } - - /* End the interrupt in the EIC. */ - EIC->IPR |= 1 << EIC_CurrentIRQChannelValue( ); - portEXIT_SWITCHING_ISR( xTaskSwitch ); -} - -inline void -vMBPortTimersEnable( ) -{ - unsigned portSHORT maskTimFlags = 0; - unsigned portSHORT maskTimIT = 0; - - MB_TIMER_DEV->CNTR = 0; - if( usTimerDeltaOCRA > 0 ) - { - MB_TIMER_DEV->OCAR = usTimerDeltaOCRA; - maskTimFlags |= TIM_OCFA; - maskTimIT |= TIM_OCA_IT; - } - - TIM_FlagClear( MB_TIMER_DEV, maskTimFlags ); - TIM_ITConfig( MB_TIMER_DEV, maskTimIT, ENABLE ); - TIM_CounterConfig( MB_TIMER_DEV, TIM_START ); -} - -inline void -vMBPortTimersDisable( ) -{ - /* We can always clear both flags. This improves performance. */ - TIM_FlagClear( MB_TIMER_DEV, TIM_OCFA | TIM_OCFB ); - TIM_ITConfig( MB_TIMER_DEV, TIM_OCA_IT | TIM_OCB_IT, DISABLE ); - TIM_CounterConfig( MB_TIMER_DEV, TIM_STOP ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/simple.bat b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/simple.bat deleted file mode 100644 index beb9247d5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/simple.bat +++ /dev/null @@ -1 +0,0 @@ -..\..\tools\modpoll.exe -m ascii -a 10 -r 1000 -c 4 -t 3 -b 9600 -d 7 -p even COM4 \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/simple.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/simple.c deleted file mode 100644 index 111c48ba1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/simple.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * FreeModbus Libary: STR71x Demo Application - * Copyright (C) 2006 Christian Walter - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "assert.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* ----------------------- STR71X includes ----------------------------------*/ -#include "eic.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define REG_INPUT_START 1000 -#define REG_INPUT_NREGS 4 - -/* ----------------------- Static variables ---------------------------------*/ -static unsigned short usRegInputStart = REG_INPUT_START; -static unsigned short usRegInputBuf[REG_INPUT_NREGS]; - -/* ----------------------- Static functions ---------------------------------*/ -static void vInitTask( void *pvParameters ); -static void vMeasureTask( void *pvParameters ); - -/* ----------------------- Start implementation -----------------------------*/ -int -main( void ) -{ - EIC_Init( ); - EIC_IRQConfig( ENABLE ); - - ( void )xTaskCreate( vInitTask, NULL, configMINIMAL_STACK_SIZE, NULL, - tskIDLE_PRIORITY, NULL ); - vTaskStartScheduler( ); - - return 0; -} - -static void -vInitTask( void *pvParameters ) -{ - const unsigned char ucSlaveIDAdditonal[] = { 0xAA, 0xBB, 0xCC }; - eMBErrorCode eStatus; - - /* Select either ASCII or RTU Mode. */ - eStatus = eMBInit( MB_RTU, 0x0A, 0, 38400, MB_PAR_EVEN ); - assert( eStatus == MB_ENOERR ); - - /* Configure the slave id of the device. */ - eStatus = eMBSetSlaveID( 44, TRUE, ucSlaveIDAdditonal, 3 ); - assert( eStatus == MB_ENOERR ); - - /* Enable the Modbus Protocol Stack. */ - eStatus = eMBEnable( ); - - for( ;; ) - { - /* Call the main polling loop of the Modbus protocol stack. Internally - * the polling loop waits for a new event by calling the port - * dependent function xMBPortEventGet( ). In the FreeRTOS port the - * event layer is built with queues. - */ - ( void )eMBPoll( ); - - /* Here we simply count the number of poll cycles. */ - usRegInputBuf[0]++; - } -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = - ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = - ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, - eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, - eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} - -void -__assert( const char *pcFile, const char *pcLine, int iLineNumber ) -{ - portENTER_CRITICAL( ); - for( ;; ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/simple2.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/simple2.c deleted file mode 100644 index 41701dbde..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/simple2.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * FreeModbus Libary: STR71x Demo Application - * Copyright (C) 2006 Christian Walter - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "assert.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* ----------------------- STR71X includes ----------------------------------*/ -#include "eic.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define REG_INPUT_START 1000 -#define REG_INPUT_NREGS 4 - -/* ----------------------- Static variables ---------------------------------*/ -static unsigned short usRegInputStart = REG_INPUT_START; -static unsigned short usRegInputBuf[REG_INPUT_NREGS]; - -/* ----------------------- Static functions ---------------------------------*/ -static void vModbusTask( void *pvParameters ); - -/* ----------------------- Start implementation -----------------------------*/ -int -main( void ) -{ - EIC_Init( ); - EIC_IRQConfig( ENABLE ); - - ( void )xTaskCreate( vModbusTask, NULL, configMINIMAL_STACK_SIZE, NULL, - tskIDLE_PRIORITY, NULL ); - - vTaskStartScheduler( ); - return 0; -} - -static void -vModbusTask( void *pvParameters ) -{ - portTickType xLastWakeTime; - - /* Select either ASCII or RTU Mode. */ - ( void )eMBInit( MB_RTU, 0x0A, 38400, MB_PAR_EVEN ); - - /* Enable the Modbus Protocol Stack. */ - ( void )eMBEnable( ); - for( ;; ) - { - /* Call the main polling loop of the Modbus protocol stack. */ - ( void )eMBPoll( ); - /* Application specific actions. Count the number of poll cycles. */ - usRegInputBuf[0]++; - /* Hold the current FreeRTOS ticks. */ - xLastWakeTime = xTaskGetTickCount( ); - usRegInputBuf[1] = ( unsigned portSHORT )( xLastWakeTime >> 16UL ); - usRegInputBuf[2] = ( unsigned portSHORT )( xLastWakeTime & 0xFFFFUL ); - /* The constant value. */ - usRegInputBuf[3] = 33; - } -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = - ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = - ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, - eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, - eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} - -void -__assert( const char *pcFile, const char *pcLine, int iLineNumber ) -{ - portENTER_CRITICAL( ); - for( ;; ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/startup.s b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/startup.s deleted file mode 100644 index d18b35b46..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71X/startup.s +++ /dev/null @@ -1,196 +0,0 @@ -/***************************************************************************** - * Copyright (c) 2001, 2002 Rowley Associates Limited. * - * * - * This file may be distributed under the terms of the License Agreement * - * provided with this software. * - * * - * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * - * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - ***************************************************************************** - * WARNING * - ***************************************************************************** - * There have been a lot of modifications to this file for the FreeRTOS port * - * for the following reason: * - * * - * - We need support for the interrupt vectors from the EIC. * - * - The default file did only make a copy of the standard vectors when in * - * FLASH mode. Because in the used EIC configuration the new programm * - * counter value is loaded with a relative offset to the current pc the * - * interrupt vectors must also be available in the RAM. * - * - The clock source configuration did not fit for the specific * - * needs of the author. * - * * - * All modifications copyright (c) 2006, Christian Walter * - *****************************************************************************/ - -#include "FreeRTOSConfig.h" /* import configUSE_PREEMPTION */ - - .equ EIC_BASE, 0xFFFFF800 /* EIC base address. */ - .equ EIC_IVR_OFF, 0x18 /* EIC interrupt vector register. */ - - .section .vectors, "ax" - .code 32 - .align 0 - -/***************************************************************************** - * Exception vectors * - *****************************************************************************/ -_vectors_start: - ldr pc, [pc, #reset_handler_address - . - 8] /* reset */ - ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */ - ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */ - ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */ - ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */ - nop - ldr pc, [pc, #irq_handler_address - . - 8] - ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq */ - -reset_handler_address: .word _reset_handler -undef_handler_address: .word _undef_handler -swi_handler_address: .word vPortYieldProcessor -pabort_handler_address: .word _pabort_handler -dabort_handler_address: .word _dabort_handler -irq_handler_address: .word _irq_handler -fiq_handler_address: .word _fiq_handler - -/******************************************************************************* - * EIC interrupt vectors - ******************************************************************************/ -.global T0TIMI_address -.global T0TIMI_Addr -T0TIMI_Addr: /* for compatibility with STR71X library. */ -T0TIMI_address: .word prvvMBTimerIRQHandler -FLASH_address: .word _undef_IRQhandler -RCCU_address: .word _undef_IRQhandler -RTC_Addr: .word _undef_IRQhandler -#if configUSE_PREEMPTION == 0 -WDG_Addr: .word vPortNonPreemptiveTick -#else -WDG_Addr: .word vPortPreemptiveTick -#endif -XTI_Addr: .word _undef_IRQhandler -USBHP_Addr: .word _undef_IRQhandler -I2C0ITERR_Addr: .word _undef_IRQhandler -I2C1ITERR_ADDR: .word _undef_IRQhandler -UART0_address: .word prvvMBSerialIRQHandler -UART1_Addr: .word _undef_IRQhandler -UART2_ADDR: .word _undef_IRQhandler -UART3_ADDR: .word _undef_IRQhandler -BSPI0_ADDR: .word _undef_IRQhandler -BSPI1_Addr: .word _undef_IRQhandler -I2C0_Addr: .word _undef_IRQhandler -I2C1_Addr: .word _undef_IRQhandler -CAN_Addr: .word _undef_IRQhandler -ADC12_Addr: .word _undef_IRQhandler -T1TIMI_Addr: .word _undef_IRQhandler -T2TIMI_Addr: .word _undef_IRQhandler -T3TIMI_Addr: .word _undef_IRQhandler - .word 0 /* reserved */ - .word 0 /* reserved */ - .word 0 /* reserved */ -HDLC_Addr: .word _undef_IRQhandler -USBLP_Addr: .word _undef_IRQhandler - .word 0 /* reserved */ - .word 0 /* reserved */ -T0TOI_Addr: .word _undef_IRQhandler -T0OC1_Addr: .word _undef_IRQhandler -T0OC2_Addr: .word _undef_IRQhandler -_vectors_end: - -/******************************************************************************* - * If flash execution is used and the RAM is mapped at address 0 we also need - * to place a copy of the interrupt vector address table in the RAM. - ******************************************************************************/ - #ifdef __FLASH_BUILD - .section .vectors_ram, "ax" - .code 32 - .align 0 -_vectors_ram: - .fill _vectors_end - _vectors_start -#endif - -/****************************************************************************** - * Default exception handlers * - ******************************************************************************/ - .section .init, "ax" - .code 32 - .global _reset_handler - .align 0 - -_reset_handler: -#ifdef __FLASH_BUILD - ldr r0, =_vectors_start - ldr r1, =_vectors_end - sub r1, r1, r0 /* r2 = number of bytes to copy */ - ldr r2, =0x20000000 /* r0 = start address to place copy */ -_vector_copy: - ldr r3, [r0], #4 /* read a word from the source */ - str r3, [r2], #4 /* copy the word to destination */ - subs r1, r1, #4 /* decrement number of words to copy */ - bne _vector_copy -#endif - - /* Configure system and jump to the _start entry point. */ - ldr r0, =0x6C000000 - ldr r1, =0x801D - str r1, [r0, #4] /* set up the emi to 1 wait state */ - - ldr r0, =0xA0000000 - ldr r1, =0x1c2 - str r1, [r0, #0x50] /* set up the internal RAM at 0x0 */ - - /* After setup the folling clock configuration will be active. Note - * that the value of CK is dependent on the target oscillator. - * - * CK = 4Mhz - * CLK2 = 2Mhz (with DIV2 = 1) - * RCLK = 16 * CLK2 / 1 = 32Mhz - * MCLK = RCLK - * PCLK1 = RCLK/2 - * PCLK2 = RCLK/2 - */ - - /* set RCLK to 16 * CLK2 / 1 = 32Mhz - * (0x0071 = FREEN=1, FREF_RANGE=1, MX1:0=11b, DX2:0=000b) */ - ldr r1, =0x00F0 - str r1, [r0, #0x18] - - /* (0x8009 = DIV2=1, CK2_16=1, CKU_CKSEL=1) */ - ldr r1, =0x8009 - str r1, [r0, #0x8] - - /* cpu and memory clock div = 1 */ - ldr r1, =0x0 - str r1, [r0, #0x40] - - /* pclk1 = rclk/2 and pclk2 = rclk/2 = 16Mhz - * (0x0101 = FACT2_9:8=01b, FACT1_1:0=01b) */ - ldr r1, =0x0101 - str r1, [r0, #0x44] - - /* Jump to the default C runtime startup code. */ - B _start - -_undef_handler: - b _undef_handler - -_swi_handler: - b vPortYieldProcessor - -_pabort_handler: - b _pabort_handler - -_dabort_handler: - b _dabort_handler - -_irq_handler: - ldr pc, =(EIC_BASE + EIC_IVR_OFF) - -_fiq_handler: - b _fiq_handler - -/****************************************************************************** - * Default IRQ handlers * - ******************************************************************************/ -_undef_IRQhandler: - b _undef_IRQhandler diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/FreeRTOSConfig.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/FreeRTOSConfig.h deleted file mode 100644 index 3a3502171..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/FreeRTOSConfig.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - FreeRTOS.org V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) 4096 ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 0 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 0 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - -#endif /* FREERTOS_CONFIG_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/Makefile b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/Makefile deleted file mode 100644 index 7775aba19..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/Makefile +++ /dev/null @@ -1,187 +0,0 @@ -# -# FreeModbus STR71X GCC Makefile -# -# Copyright (C) 2006 Christian Walter -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# -# $Id: Makefile,v 1.1 2006/11/02 23:14:43 wolti Exp $ -# - -# MCU name and submodel -MCU = arm7tdmi -SUBMDL = STR711 -#THUMB = -mthumb -#THUMB_IW = -mthumb-interwork - -## Create ROM-Image (final) -#RUN_MODE=ROM_RUN -## Create RAM-Image (debugging) -RUN_MODE=RAM_RUN - -# --------------------------------------------------------------------------- # -# TARGET ... name of the target executable to generate -# SRC ... C source files ( either THUMB or ARM ) -# SRCARM ... C source files which are always compiled in ARM mode -# CPPSRC ... C++ source files ( either THUMB or ARM ) -# CPPSRCARM ... C++ source files which are always compiled in ARM mode -# --------------------------------------------------------------------------- # - -TARGET = demo -INC = -I. -Iport \ - -Ifreertos/include \ - -Ilibstr71x/include \ - -I../../modbus/include \ - -I../../modbus/rtu \ - -I../../modbus/ascii -SRC = demo.c \ - $(addprefix freertos/, list.c queue.c tasks.c ) \ - $(addprefix freertos/portable/MemMang/, heap_2.c ) \ - $(addprefix freertos/portable/GCC/ARM7_STR71X/, port.c ) \ - $(addprefix libstr71x/, wdg.c rccu.c eic.c tim.c uart.c gpio.c ) \ - $(addprefix ../../modbus/, mb.c ) \ - $(addprefix ../../modbus/rtu/, mbrtu.c mbcrc.c ) \ - $(addprefix ../../modbus/ascii/, mbascii.c ) \ - $(addprefix ../../modbus/functions/, mbfunccoils.c mbfuncdiag.c mbfuncholding.c mbfuncinput.c mbfuncother.c mbfuncdisc.c mbutils.c ) -SRCARM = $(addprefix freertos/portable/GCC/ARM7_STR71X/, portISR.c ) \ - $(addprefix port/, portevent.c portserial.c porttimer.c ) -CPPSRC = -CPPSRCARM = - -AINC = -I. -ASRC = -ASRCARM = $(addprefix system/, startup.S vector.S ) - -# --------------------------------------------------------------------------- # -# This section includes compiler and linker settings. -# --------------------------------------------------------------------------- # -# Flags for C and C++ (arm-elf-gcc/arm-elf-g++) -CPPFLAGS = -gdwarf-2 -O0 -fno-strict-aliasing -CPPFLAGS += -Wall -Wcast-align -Wimplicit -Wpointer-arith -Wswitch -CPPFLAGS += -Wredundant-decls -Wreturn-type -Wshadow -Wunused -CPPFLAGS += -D$(RUN_MODE) -DGCC_ARM7_STR71X=1 -# Flags for C -CFLAGS = $(CPPFLAGS) $(INC) -# Flags for C++ -CCXXFLAGS = $(CFLAGS) - -# Assembler flags. -#ASFLAGS = --defsym $(RUN_MODE)=1 --defsym REMAP=2 --gdwarf-2 -ASFLAGS = -gdwarf-2 -D$(RUN_MODE)=1 -DREMAP=0 $(AINC) - -# Linker flags. -LDFLAGS = -nostartfiles -Wl,-Map=$(TARGET).map,--cref -lc -lgcc -ifeq ($(RUN_MODE),RAM_RUN) -LDFLAGS +=-Tsupport/ram71x.ld -else -LDFLAGS +=-Tsupport/rom71x.ld -endif - -# --------------------------------------------------------------------------- # -# Toolchain setup -# --------------------------------------------------------------------------- # -PREFIX = /opt/gcc-arm/bin -AS = $(PREFIX)/arm-elf-as -CC = $(PREFIX)/arm-elf-gcc -CPP = $(PREFIX)/arm-elf-g++ -OBJCOPY = $(PREFIX)/arm-elf-objcopy -OBJDUMP = $(PREFIX)/arm-elf-objdump -SIZE = $(PREFIX)/arm-elf-size -NM = $(PREFIX)/arm-elf-nm -INSIGHT = $(PREFIX)/arm-elf-insight - -# --------------------------------------------------------------------------- # -# Define all output files and dependencies based upon the specified -# source files. -# --------------------------------------------------------------------------- # -COBJ = $(SRC:.c=.o) -AOBJ = $(ASRC:.S=.o) -COBJARM = $(SRCARM:.c=.o) -AOBJARM = $(ASRCARM:.S=.o) -CPPOBJ = $(CPPSRC:.cpp=.o) -CPPOBJARM = $(CPPSRCARM:.cpp=.o) - -# Flags need to generate dependencies -GENDEPFLAGS = -MD -MP -MF .dep/$(@F).d - -# Combine all necessary flags and optional flags. -ALL_CFLAGS = -mcpu=$(MCU) $(THUMB_IW) $(CFLAGS) $(GENDEPFLAGS) -ALL_ASFLAGS = -mcpu=$(MCU) $(THUMB_IW) $(ASFLAGS) - -# --------------------------------------------------------------------------- # -# Make targets -# --------------------------------------------------------------------------- # - -all: $(TARGET).elf $(TARGET).sym $(TARGET).hex $(TARGET).bin - -# Debug target which invokes the debugger -debug: $(TARGET).hex - $(INSIGHT) --se=$(TARGET).elf --command=support/target-71.gdb - -# Flasg target which downloads the code. -flash: $(TARGET).hex $(TARGET).bin - -%.hex: %.elf - $(OBJCOPY) -O ihex $< $@ - -%.bin: %.elf - $(OBJCOPY) -O binary $< $@ - -%.sym: %.elf - $(NM) -n $< > $@ - -$(TARGET).elf: $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) - $(CC) $(THUMB) $(THUMB_IW) $(AOBJARM) $(AOBJ) $(COBJARM) $(COBJ) $(CPPOBJ) $(CPPOBJARM) --output $@ $(LDFLAGS) - -# Compile: create object files from C source files. ARM/Thumb -$(COBJ) : %.o : %.c - $(CC) -c $(THUMB) $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@ - -# Compile: create object files from C source files. ARM-only -$(COBJARM) : %.o : %.c - $(CC) -c $(ALL_CFLAGS) $(CONLYFLAGS) $< -o $@ - -# Compile: create object files from C++ source files. ARM/Thumb -$(CPPOBJ) : %.o : %.cpp - $(CPP) -c $(THUMB) $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@ - -# Compile: create object files from C++ source files. ARM-only -$(CPPOBJARM) : %.o : %.cpp - $(CPP) -c $(ALL_CFLAGS) $(CPPFLAGS) $< -o $@ - -# Assemble: create object files from assembler source files. ARM/Thumb -$(AOBJ) : %.o : %.S - $(CC) -c $(THUMB) $(ALL_ASFLAGS) $< -o $@ -# $(AS) $(THUMB) $(ALL_ASFLAGS) -o $@ $< - -# Assemble: create object files from assembler source files. ARM-only -$(AOBJARM) : %.o : %.S - $(CC) -c $(ALL_ASFLAGS) $< -o $@ -# $(AS) $(ALL_ASFLAGS) -o $@ $< - -# Target: clean project. -clean: - rm -f $(TARGET).hex $(TARGET).bin $(TARGET).obj $(TARGET).elf $(TARGET).map - rm -f $(TARGET).obj $(TARGET).sym $(TARGET).lss $(TARGET).lst - rm -f $(COBJ) $(CPPOBJ) $(AOBJ) $(COBJARM) $(CPPOBJARM) $(AOBJARM) - rm -f $(SRC:.c=.d) $(SRCARM:.c=.d) $(CPPSRC:.cpp=.d) $(CPPSRCARM:.cpp=.d) - rm -f .dep/* - -# Include the dependency files. --include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*) - -# Listing of phony targets. -.PHONY : all clean - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/README.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/README.txt deleted file mode 100644 index 198ff1d61..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/README.txt +++ /dev/null @@ -1,120 +0,0 @@ - - FreeModbus STR71X/FreeRTOS/GCC Port - -REQUIREMENTS -============ - -This port is the same as the STR71X port but contains complete startup -scripts, makefiles and debugger scripts to work without the Rowley -Crossworks tools. -On the software side a GCC [1] installation (tested with 4.1.1) is required -together with a working C-Library [2]. If debugging is desired -a Wiggler interface must be present. OpenOCD [3] binaries for Windows -and Linux are provided in the tools directory together with a suitable -configuration. - - [1] ... GNU ARM Homepage http://www.gnuarm.org/ - [2] ... The Newlib Homepage http://sources.redhat.com/newlib - [3] ... OpenOCD homepage http://openocd.berlios.de/web/ - -USAGE -===== - -A makefile is supplied with the demo application and a binary can be -produced by calling 'make all'. A special target 'debug' is provided -which executes the insight debugger. Command line debugging with GDB is -also possible and is described here. After you have compiled the binary -start the OpenOCD daemon in a shell. - -$ ./tools/openocd -f tools/str71x_wig.cfg -Info: openocd.c:82 main(): Open On-Chip Debugger (2006-08-01 12:00 CEST) - -Then start the GDB debugger and continue till you have reached the main -entry point. - -$ arm-elf-gdb -se=demo.elf --command=support/target-71.gdb -GNU gdb 6.5.0.20060626-cvs -... -(gdb) target remote localhost:3333 -Remote debugging using localhost:3333 -0x00000004 in ?? () -(gdb) setup-and-load-ram -requesting target halt and executing a soft reset -software breakpoints enabled -Breakpoint 1 at 0x400011e4: file demo.c, line 53. -Mapped internal SRAM at address 0x00000000 -(gdb) load demo.elf -Loading section .text, size 0x945c lma 0x20000000 -Loading section .rodata, size 0x40c lma 0x2000945c -Loading section .data, size 0x90 lma 0x20009868 -Start address 0x20000000, load size 39160 -Transfer rate: 99170 bits/sec, 495 bytes/write. -(gdb) stepi -_start () at system/startup.S:97 -97 ldr pc, =NextInst -Current language: auto; currently asm -(gdb) c -Continuing. -main () at demo.c:53 -53 RCCU_Div2Config( ENABLE ); -Current language: auto; currently c -(gdb) - -Now you are ready to start or debug the application. If you want to test -your system simply enter 'continue' at the prompt. Now start the Modbus -test application [1] from the 'demo.sh' or 'demo.bat' shell script. You -should see the following output. - -$ ./demo.sh -modpoll - FieldTalk(tm) Modbus(R) Polling Utility -... -Protocol opened successfully. -Polling slave (Ctrl-C to stop) ... -[1000]: 5 -[1001]: 0 -[1002]: 0 -[1003]: 0 - -If this is working then congratulations. The Modbus Stack and the Target -Hardware is ready. - - [1] ... You need the FieldTalk Modpoll Modbus® Polling Tool which you - can get at http://www.focus-sw.com/fieldtalk/modpoll.html. - -FLASH DOWNLOAD -============== - -Flash download is possible with OpenOCD. First edit the Makefile and set -the variable RAM_RUN to ROM_RUN and execute 'make clean' and 'make all'. -Open a telnet connection to your OpenOCD daemon and enter the following -commands at the telnet prompt: - -$ telnet localhost 4444 -Trying 127.0.0.1... -Connected to localhost.localdomain (127.0.0.1). -Escape character is '^]'. -Open On-Chip Debugger -> flash probe 0 -flash 'str7x' found at 0x40000000 -> flash erase 0 0 9 -> flash erase 1 0 3 -> flash write 0 demo.bin 0x0 -wrote file ../demo.bin to flash bank 0 at offset 0x00000000 in 82s 783us - -Now restart the target system and the it with the demo application. It -is also possible to attach a debugger but you are limited to two hardware -breakpoints. Use the same procedure as above but leave out the load step -and replace 'setup-and-load-ram' by 'setup-and-load-rom'. - -COMMON PROBLEMS -=============== -The following list should serve as a checklist where each point must -be satisfied for the port to work. - - - If you have changed the execution mode make sure you have called - 'make clean' - -$Id: README.txt,v 1.2 2006/11/02 23:29:47 wolti Exp $ - -STR71X FreeModbus Port Copyright (c) 2006 Christian Walter. - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/demo.c deleted file mode 100644 index 79f74ef4b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/demo.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * FreeModbus Libary: STR71x Demo Application - * Copyright (C) 2006 Christian Walter - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include - -/* ----------------------- Platform includes --------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* ----------------------- STR71X includes ----------------------------------*/ -#include "rccu.h" -#include "eic.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define REG_INPUT_START 1000 -#define REG_INPUT_NREGS 4 - -/* ----------------------- Static variables ---------------------------------*/ -static unsigned short usRegInputStart = REG_INPUT_START; -static unsigned short usRegInputBuf[REG_INPUT_NREGS]; - -/* ----------------------- Static functions ---------------------------------*/ -static void vInitTask( void *pvParameters ); -static void vMeasureTask( void *pvParameters ); - -/* ----------------------- Start implementation -----------------------------*/ -int -main( void ) -{ - RCCU_Div2Config( ENABLE ); - RCCU_PLL1Config( RCCU_PLL1_Mul_16, RCCU_Div_1 ); - RCCU_RCLKSourceConfig( RCCU_PLL1_Output ); - RCCU_MCLKConfig( RCCU_DEFAULT ); - RCCU_PCLKConfig( RCCU_RCLK_2 ); - RCCU_FCLKConfig( RCCU_RCLK_2 ); - - EIC_Init( ); - EIC_IRQConfig( ENABLE ); - - ( void )xTaskCreate( vInitTask, NULL, configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); - vTaskStartScheduler( ); - - return 0; -} - -static void -vInitTask( void *pvParameters ) -{ - const unsigned char ucSlaveIDAdditonal[] = { 0xAA, 0xBB, 0xCC }; - eMBErrorCode eStatus; - - /* Select either ASCII or RTU Mode. */ - eStatus = eMBInit( MB_RTU, 0x0A, 0, 38400, MB_PAR_EVEN ); - assert( eStatus == MB_ENOERR ); - - /* Configure the slave id of the device. */ - eStatus = eMBSetSlaveID( 44, TRUE, ucSlaveIDAdditonal, 3 ); - assert( eStatus == MB_ENOERR ); - - /* Enable the Modbus Protocol Stack. */ - eStatus = eMBEnable( ); - - for( ;; ) - { - /* Call the main polling loop of the Modbus protocol stack. Internally - * the polling loop waits for a new event by calling the port - * dependent function xMBPortEventGet( ). In the FreeRTOS port the - * event layer is built with queues. - */ - ( void )eMBPoll( ); - - /* Here we simply count the number of poll cycles. */ - usRegInputBuf[0]++; - } -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} - -void -__assert( const char *pcFile, int iLineNumber, const char *pcLine ) -{ - portENTER_CRITICAL( ); - for( ;; ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/demo.sh b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/demo.sh deleted file mode 100644 index 76076a9c2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/demo.sh +++ /dev/null @@ -1 +0,0 @@ -../../tools/modpoll -m rtu -a 10 -r 1000 -c 4 -t 3 -b 38400 -d 8 -p even /dev/ttyUSB0 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/croutine.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/croutine.c deleted file mode 100644 index dba4bc386..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/croutine.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - FreeRTOS.org V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/* Lists for ready and blocked co-routines. --------------------*/ -static xList pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ -static xList xDelayedCoRoutineList1; /*< Delayed co-routines. */ -static xList xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ -static xList * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */ -static xList * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ -static xList xPendingReadyList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ - -/* Other file private variables. --------------------------------*/ -corCRCB * pxCurrentCoRoutine = NULL; -static unsigned portBASE_TYPE uxTopCoRoutineReadyPriority = 0; -static portTickType xCoRoutineTickCount = 0; - -/* The initial state of the co-routine when it is created. */ -#define corINITIAL_STATE ( 0 ) - -/* - * Place the co-routine represented by pxCRCB into the appropriate ready queue - * for the priority. It is inserted at the end of the list. - * - * This macro accesses the co-routine ready lists and therefore must not be - * used from within an ISR. - */ -#define prvAddCoRoutineToReadyQueue( pxCRCB ) \ -{ \ - if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ - { \ - uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ - } \ - vListInsertEnd( ( xList * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ -} - -/* - * Utility to ready all the lists used by the scheduler. This is called - * automatically upon the creation of the first co-routine. - */ -static void prvInitialiseCoRoutineLists( void ); - -/* - * Co-routines that are readied by an interrupt cannot be placed directly into - * the ready lists (there is no mutual exclusion). Instead they are placed in - * in the pending ready list in order that they can later be moved to the ready - * list by the co-routine scheduler. - */ -static inline void prvCheckPendingReadyList( void ); - -/* - * Macro that looks at the list of co-routines that are currently delayed to - * see if any require waking. - * - * Co-routines are stored in the queue in the order of their wake time - - * meaning once one co-routine has been found whose timer has not expired - * we need not look any further down the list. - */ -static inline void prvCheckDelayedList( void ); - -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ) -{ -signed portBASE_TYPE xReturn; -corCRCB *pxCoRoutine; - - /* Allocate the memory that will store the co-routine control block. */ - pxCoRoutine = ( corCRCB * ) pvPortMalloc( sizeof( corCRCB ) ); - if( pxCoRoutine ) - { - /* If pxCurrentCoRoutine is NULL then this is the first co-routine to - be created and the co-routine data structures need initialising. */ - if( pxCurrentCoRoutine == NULL ) - { - pxCurrentCoRoutine = pxCoRoutine; - prvInitialiseCoRoutineLists(); - } - - /* Check the priority is within limits. */ - if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) - { - uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; - } - - /* Fill out the co-routine control block from the function parameters. */ - pxCoRoutine->uxState = corINITIAL_STATE; - pxCoRoutine->uxPriority = uxPriority; - pxCoRoutine->uxIndex = uxIndex; - pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; - - /* Initialise all the other co-routine control block parameters. */ - vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); - vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); - - /* Set the co-routine control block as a link back from the xListItem. - This is so we can get back to the containing CRCB from a generic item - in a list. */ - listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); - listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); - - /* Event lists are always in priority order. */ - listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); - - /* Now the co-routine has been initialised it can be added to the ready - list at the correct priority. */ - prvAddCoRoutineToReadyQueue( pxCoRoutine ); - - xReturn = pdPASS; - } - else - { - xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList ) -{ -portTickType xTimeToWake; - - /* Calculate the time to wake - this may overflow but this is - not a problem. */ - xTimeToWake = xCoRoutineTickCount + xTicksToDelay; - - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xCoRoutineTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - } - - if( pxEventList ) - { - /* Also add the co-routine to an event list. If this is done then the - function must be called with interrupts disabled. */ - vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); - } -} -/*-----------------------------------------------------------*/ - -static inline void prvCheckPendingReadyList( void ) -{ - /* Are there any co-routines waiting to get moved to the ready list? These - are co-routines that have been readied by an ISR. The ISR cannot access - the ready lists itself. */ - while( !listLIST_IS_EMPTY( &xPendingReadyList ) ) - { - corCRCB *pxUnblockedCRCB; - - /* The pending ready list can be accessed by an ISR. */ - portDISABLE_INTERRUPTS(); - { - pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyList) ); - vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); - } - portENABLE_INTERRUPTS(); - - vListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); - prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); - } -} -/*-----------------------------------------------------------*/ - -static inline void prvCheckDelayedList( void ) -{ -static portTickType xLastTickCount, xPassedTicks; -corCRCB *pxCRCB; - - xPassedTicks = xTaskGetTickCount() - xLastTickCount; - while( xPassedTicks ) - { - xCoRoutineTickCount++; - xPassedTicks--; - - /* If the tick count has overflowed we need to swap the ready lists. */ - if( xCoRoutineTickCount == 0 ) - { - xList * pxTemp; - - /* Tick count has overflowed so we need to swap the delay lists. If there are - any items in pxDelayedCoRoutineList here then there is an error! */ - pxTemp = pxDelayedCoRoutineList; - pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; - pxOverflowDelayedCoRoutineList = pxTemp; - } - - /* See if this tick has made a timeout expire. */ - while( ( pxCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ) ) != NULL ) - { - if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) - { - /* Timeout not yet expired. */ - break; - } - - portDISABLE_INTERRUPTS(); - { - /* The event could have occurred just before this critical - section. If this is the case then the generic list item will - have been moved to the pending ready list and the following - line is still valid. Also the pvContainer parameter will have - been set to NULL so the following lines are also valid. */ - vListRemove( &( pxCRCB->xGenericListItem ) ); - - /* Is the co-routine waiting on an event also? */ - if( pxCRCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxCRCB->xEventListItem ) ); - } - } - portENABLE_INTERRUPTS(); - - prvAddCoRoutineToReadyQueue( pxCRCB ); - } - } - - xLastTickCount = xCoRoutineTickCount; -} -/*-----------------------------------------------------------*/ - -void vCoRoutineSchedule( void ) -{ - /* See if any co-routines readied by events need moving to the ready lists. */ - prvCheckPendingReadyList(); - - /* See if any delayed co-routines have timed out. */ - prvCheckDelayedList(); - - /* Find the highest priority queue that contains ready co-routines. */ - while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) - { - if( uxTopCoRoutineReadyPriority == 0 ) - { - /* No more co-routines to check. */ - return; - } - --uxTopCoRoutineReadyPriority; - } - - /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines - of the same priority get an equal share of the processor time. */ - listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); - - /* Call the co-routine. */ - ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); - - return; -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseCoRoutineLists( void ) -{ -unsigned portBASE_TYPE uxPriority; - - for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) - { - vListInitialise( ( xList * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); - } - - vListInitialise( ( xList * ) &xDelayedCoRoutineList1 ); - vListInitialise( ( xList * ) &xDelayedCoRoutineList2 ); - vListInitialise( ( xList * ) &xPendingReadyList ); - - /* Start with pxDelayedCoRoutineList using list1 and the - pxOverflowDelayedCoRoutineList using list2. */ - pxDelayedCoRoutineList = &xDelayedCoRoutineList1; - pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList ) -{ -corCRCB *pxUnblockedCRCB; -signed portBASE_TYPE xReturn; - - /* This function is called from within an interrupt. It can only access - event lists and the pending ready list. */ - pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); - vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedCRCB->xEventListItem ) ); - - if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) - { - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/FreeRTOS.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/FreeRTOS.h deleted file mode 100644 index affc7065e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/FreeRTOS.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - FreeRTOS.org V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef INC_FREERTOS_H -#define INC_FREERTOS_H - - -/* - * Include the generic headers required for the FreeRTOS port being used. - */ -#include - -/* Basic FreeRTOS definitions. */ -#include "projdefs.h" - -/* Application specific configuration options. */ -#include "FreeRTOSConfig.h" - -/* Definitions specific to the port being used. */ -#include "portable.h" - - - - - - - -/* - * Check all the required application specific macros have been defined. - * These macros are application specific and (as downloaded) are defined - * within FreeRTOSConfig.h. - */ - -#ifndef configUSE_PREEMPTION - #error Missing definition: configUSE_PREEMPTION should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_IDLE_HOOK - #error Missing definition: configUSE_IDLE_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_TICK_HOOK - #error Missing definition: configUSE_TICK_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_CO_ROUTINES - #error Missing definition: configUSE_CO_ROUTINES should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskPrioritySet - #error Missing definition: INCLUDE_vTaskPrioritySet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_uxTaskPriorityGet - #error Missing definition: INCLUDE_uxTaskPriorityGet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelete - #error Missing definition: INCLUDE_vTaskDelete should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskCleanUpResources - #error Missing definition: INCLUDE_vTaskCleanUpResources should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskSuspend - #error Missing definition: INCLUDE_vTaskSuspend should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelayUntil - #error Missing definition: INCLUDE_vTaskDelayUntil should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelay - #error Missing definition: INCLUDE_vTaskDelay should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_16_BIT_TICKS - #error Missing definition: configUSE_16_BIT_TICKS should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/croutine.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/croutine.h deleted file mode 100644 index f49adc148..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/croutine.h +++ /dev/null @@ -1,713 +0,0 @@ -/* - FreeRTOS.org V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ -#ifndef CO_ROUTINE_H -#define CO_ROUTINE_H - -#include "list.h" - -/* Used to hide the implementation of the co-routine control block. The -control block structure however has to be included in the header due to -the macro implementation of the co-routine functionality. */ -typedef void * xCoRoutineHandle; - -/* Defines the prototype to which co-routine functions must conform. */ -typedef void (*crCOROUTINE_CODE)( xCoRoutineHandle, unsigned portBASE_TYPE ); - -typedef struct corCoRoutineControlBlock -{ - crCOROUTINE_CODE pxCoRoutineFunction; - xListItem xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ - xListItem xEventListItem; /*< List item used to place the CRCB in event lists. */ - unsigned portBASE_TYPE uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ - unsigned portBASE_TYPE uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ - unsigned portSHORT uxState; /*< Used internally by the co-routine implementation. */ -} corCRCB; /* Co-routine control block. Note must be identical in size down to uxPriority with tskTCB. */ - -/** - * croutine. h - *

- portBASE_TYPE xCoRoutineCreate(

-                                 crCOROUTINE_CODE pxCoRoutineCode,

-                                 unsigned portBASE_TYPE uxPriority,

-                                 unsigned portBASE_TYPE uxIndex

-                               );
- * - * Create a new co-routine and add it to the list of co-routines that are - * ready to run. - * - * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine - * functions require special syntax - see the co-routine section of the WEB - * documentation for more information. - * - * @param uxPriority The priority with respect to other co-routines at which - * the co-routine will run. - * - * @param uxIndex Used to distinguish between different co-routines that - * execute the same function. See the example below and the co-routine section - * of the WEB documentation for further information. - * - * @return pdPASS if the co-routine was successfully created and added to a ready - * list, otherwise an error code defined with ProjDefs.h. - * - * Example usage: -

- // Co-routine to be created.

- void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- // This may not be necessary for const variables.

- static const char cLedToFlash[ 2 ] = { 5, 6 };

- static const portTickType xTimeToDelay[ 2 ] = { 200, 400 };

-

-     // Must start every co-routine with a call to crSTART();

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-         // This co-routine just delays for a fixed period, then toggles

-         // an LED.  Two co-routines are created using this function, so

-         // the uxIndex parameter is used to tell the co-routine which

-         // LED to flash and how long to delay.  This assumes xQueue has

-         // already been created.

-         vParTestToggleLED( cLedToFlash[ uxIndex ] );

-         crDELAY( xHandle, uxFlashRates[ uxIndex ] );

-     }

-

-     // Must end every co-routine with a call to crEND();

-     crEND();

- }

-

- // Function that creates two co-routines.

- void vOtherFunction( void )

- {

- unsigned char ucParameterToPass;

- xTaskHandle xHandle;

-		

-     // Create two co-routines at priority 0.  The first is given index 0

-     // so (from the code above) toggles LED 5 every 200 ticks.  The second

-     // is given index 1 so toggles LED 6 every 400 ticks.

-     for( uxIndex = 0; uxIndex < 2; uxIndex++ )

-     {

-         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );

-     }

- }

-   
- * \defgroup xCoRoutineCreate xCoRoutineCreate - * \ingroup Tasks - */ -signed portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ); - - -/** - * croutine. h - *

- void vCoRoutineSchedule( void );
- * - * Run a co-routine. - * - * vCoRoutineSchedule() executes the highest priority co-routine that is able - * to run. The co-routine will execute until it either blocks, yields or is - * preempted by a task. Co-routines execute cooperatively so one - * co-routine cannot be preempted by another, but can be preempted by a task. - * - * If an application comprises of both tasks and co-routines then - * vCoRoutineSchedule should be called from the idle task (in an idle task - * hook). - * - * Example usage: -

- // This idle task hook will schedule a co-routine each time it is called.

- // The rest of the idle task will execute between co-routine calls.

- void vApplicationIdleHook( void )

- {

-	vCoRoutineSchedule();

- }

-

- // Alternatively, if you do not require any other part of the idle task to

- // execute, the idle task hook can call vCoRoutineScheduler() within an

- // infinite loop.

- void vApplicationIdleHook( void )

- {

-    for( ;; )

-    {

-        vCoRoutineSchedule();

-    }

- }

- 
- * \defgroup vCoRoutineSchedule vCoRoutineSchedule - * \ingroup Tasks - */ -void vCoRoutineSchedule( void ); - -/** - * croutine. h - *

- crSTART( xCoRoutineHandle xHandle );
- * - * This macro MUST always be called at the start of a co-routine function. - * - * Example usage: -

- // Co-routine to be created.

- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- static portLONG ulAVariable;

-

-     // Must start every co-routine with a call to crSTART();

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-          // Co-routine functionality goes here.

-     }

-

-     // Must end every co-routine with a call to crEND();

-     crEND();

- }
- * \defgroup crSTART crSTART - * \ingroup Tasks - */ -#define crSTART( pxCRCB ) switch( ( ( corCRCB * )pxCRCB )->uxState ) { case 0: - -/** - * croutine. h - *

- crEND();
- * - * This macro MUST always be called at the end of a co-routine function. - * - * Example usage: -

- // Co-routine to be created.

- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- static portLONG ulAVariable;

-

-     // Must start every co-routine with a call to crSTART();

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-          // Co-routine functionality goes here.

-     }

-

-     // Must end every co-routine with a call to crEND();

-     crEND();

- }
- * \defgroup crSTART crSTART - * \ingroup Tasks - */ -#define crEND() } - -/* - * These macros are intended for internal use by the co-routine implementation - * only. The macros should not be used directly by application writers. - */ -#define crSET_STATE0( xHandle ) ( ( corCRCB * )xHandle)->uxState = (__LINE__ * 2); return; case (__LINE__ * 2): -#define crSET_STATE1( xHandle ) ( ( corCRCB * )xHandle)->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1): - -/** - * croutine. h - *

- crDELAY( xCoRoutineHandle xHandle, portTickType xTicksToDelay );
- * - * Delay a co-routine for a fixed period of time. - * - * crDELAY can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * @param xHandle The handle of the co-routine to delay. This is the xHandle - * parameter of the co-routine function. - * - * @param xTickToDelay The number of ticks that the co-routine should delay - * for. The actual amount of time this equates to is defined by - * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_RATE_MS - * can be used to convert ticks to milliseconds. - * - * Example usage: -

- // Co-routine to be created.

- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- // This may not be necessary for const variables.

- // We are to delay for 200ms.

- static const xTickType xDelayTime = 200 / portTICK_RATE_MS;

-

-     // Must start every co-routine with a call to crSTART();

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-        // Delay for 200ms.

-        crDELAY( xHandle, xDelayTime );

-

-        // Do something here.

-     }

-

-     // Must end every co-routine with a call to crEND();

-     crEND();

- }
- * \defgroup crDELAY crDELAY - * \ingroup Tasks - */ -#define crDELAY( xHandle, xTicksToDelay ) \ - if( xTicksToDelay > 0 ) \ - { \ - vCoRoutineAddToDelayedList( xTicksToDelay, NULL ); \ - } \ - crSET_STATE0( xHandle ); - -/** - *

- crQUEUE_SEND(

-                  xCoRoutineHandle xHandle,

-                  xQueueHandle pxQueue,

-                  void *pvItemToQueue,

-                  portTickType xTicksToWait,

-                  portBASE_TYPE *pxResult

-             )
- * - * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine - * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. - * - * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas - * xQueueSend() and xQueueReceive() can only be used from tasks. - * - * crQUEUE_SEND can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xHandle The handle of the calling co-routine. This is the xHandle - * parameter of the co-routine function. - * - * @param pxQueue The handle of the queue on which the data will be posted. - * The handle is obtained as the return value when the queue is created using - * the xQueueCreate() API function. - * - * @param pvItemToQueue A pointer to the data being posted onto the queue. - * The number of bytes of each queued item is specified when the queue is - * created. This number of bytes is copied from pvItemToQueue into the queue - * itself. - * - * @param xTickToDelay The number of ticks that the co-routine should block - * to wait for space to become available on the queue, should space not be - * available immediately. The actual amount of time this equates to is defined - * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant - * portTICK_RATE_MS can be used to convert ticks to milliseconds (see example - * below). - * - * @param pxResult The variable pointed to by pxResult will be set to pdPASS if - * data was successfully posted onto the queue, otherwise it will be set to an - * error defined within ProjDefs.h. - * - * Example usage: -

- // Co-routine function that blocks for a fixed period then posts a number onto

- // a queue.

- static void prvCoRoutineFlashTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- static portBASE_TYPE xNumberToPost = 0;

- static portBASE_TYPE xResult;

-

-    // Co-routines must begin with a call to crSTART().

-    crSTART( xHandle );

-

-    for( ;; )

-    {

-        // This assumes the queue has already been created.

-        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );

-

-        if( xResult != pdPASS )

-        {

-            // The message was not posted!

-        }

-

-        // Increment the number to be posted onto the queue.

-        xNumberToPost++;

-

-        // Delay for 100 ticks.

-        crDELAY( xHandle, 100 );

-    }

-

-    // Co-routines must end with a call to crEND().

-    crEND();

- }
- * \defgroup crQUEUE_SEND crQUEUE_SEND - * \ingroup Tasks - */ -#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ -{ \ - *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, xTicksToWait ); \ - if( *pxResult == errQUEUE_BLOCKED ) \ - { \ - crSET_STATE0( xHandle ); \ - *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, 0 ); \ - } \ - if( *pxResult == errQUEUE_YIELD ) \ - { \ - crSET_STATE1( xHandle ); \ - *pxResult = pdPASS; \ - } \ -} - -/** - * croutine. h - *

-  crQUEUE_RECEIVE(

-                     xCoRoutineHandle xHandle,

-                     xQueueHandle pxQueue,

-                     void *pvBuffer,

-                     portTickType xTicksToWait,

-                     portBASE_TYPE *pxResult

-                 )
- * - * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine - * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. - * - * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas - * xQueueSend() and xQueueReceive() can only be used from tasks. - * - * crQUEUE_RECEIVE can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xHandle The handle of the calling co-routine. This is the xHandle - * parameter of the co-routine function. - * - * @param pxQueue The handle of the queue from which the data will be received. - * The handle is obtained as the return value when the queue is created using - * the xQueueCreate() API function. - * - * @param pvBuffer The buffer into which the received item is to be copied. - * The number of bytes of each queued item is specified when the queue is - * created. This number of bytes is copied into pvBuffer. - * - * @param xTickToDelay The number of ticks that the co-routine should block - * to wait for data to become available from the queue, should data not be - * available immediately. The actual amount of time this equates to is defined - * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant - * portTICK_RATE_MS can be used to convert ticks to milliseconds (see the - * crQUEUE_SEND example). - * - * @param pxResult The variable pointed to by pxResult will be set to pdPASS if - * data was successfully retrieved from the queue, otherwise it will be set to - * an error code as defined within ProjDefs.h. - * - * Example usage: -

- // A co-routine receives the number of an LED to flash from a queue.  It

- // blocks on the queue until the number is received.

- static void prvCoRoutineFlashWorkTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- static portBASE_TYPE xResult;

- static unsigned portBASE_TYPE uxLEDToFlash;

-

-    // All co-routines must start with a call to crSTART().

-    crSTART( xHandle );

-

-    for( ;; )

-    {

-        // Wait for data to become available on the queue.

-        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );

-

-        if( xResult == pdPASS )

-        {

-            // We received the LED to flash - flash it!

-            vParTestToggleLED( uxLEDToFlash );

-        }

-    }

-

-    crEND();

- }
- * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE - * \ingroup Tasks - */ -#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ -{ \ - *pxResult = xQueueCRReceive( pxQueue, pvBuffer, xTicksToWait ); \ - if( *pxResult == errQUEUE_BLOCKED ) \ - { \ - crSET_STATE0( xHandle ); \ - *pxResult = xQueueCRReceive( pxQueue, pvBuffer, 0 ); \ - } \ - if( *pxResult == errQUEUE_YIELD ) \ - { \ - crSET_STATE1( xHandle ); \ - *pxResult = pdPASS; \ - } \ -} - -/** - * croutine. h - *

-  crQUEUE_SEND_FROM_ISR(

-                            xQueueHandle pxQueue,

-                            void *pvItemToQueue,

-                            portBASE_TYPE xCoRoutinePreviouslyWoken

-                       )
- * - * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the - * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() - * functions used by tasks. - * - * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to - * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and - * xQueueReceiveFromISR() can only be used to pass data between a task and and - * ISR. - * - * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue - * that is being used from within a co-routine. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto - * the same queue multiple times from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. - * - * @return pdTRUE if a co-routine was woken by posting onto the queue. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage: -

- // A co-routine that blocks on a queue waiting for characters to be received.

- static void vReceivingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- portCHAR cRxedChar;

- portBASE_TYPE xResult;

-

-     // All co-routines must start with a call to crSTART().

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-         // Wait for data to become available on the queue.  This assumes the

-         // queue xCommsRxQueue has already been created!

-         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );

-

-         // Was a character received?

-         if( xResult == pdPASS )

-         {

-             // Process the character here.

-         }

-     }

-

-     // All co-routines must end with a call to crEND().

-     crEND();

- }

-

- // An ISR that uses a queue to send characters received on a serial port to

- // a co-routine.

- void vUART_ISR( void )

- {

- portCHAR cRxedChar;

- portBASE_TYPE xCRWokenByPost = pdFALSE;

-

-     // We loop around reading characters until there are none left in the UART.

-     while( UART_RX_REG_NOT_EMPTY() )

-     {

-         // Obtain the character from the UART.

-         cRxedChar = UART_RX_REG;

-

-         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE

-         // the first time around the loop.  If the post causes a co-routine

-         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.

-         // In this manner we can ensure that if more than one co-routine is

-         // blocked on the queue only one is woken by this ISR no matter how

-         // many characters are posted to the queue.

-         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );

-     }

- }
- * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR - * \ingroup Tasks - */ -#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) - - -/** - * croutine. h - *

-  crQUEUE_SEND_FROM_ISR(

-                            xQueueHandle pxQueue,

-                            void *pvBuffer,

-                            portBASE_TYPE * pxCoRoutineWoken

-                       )
- * - * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the - * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() - * functions used by tasks. - * - * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to - * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and - * xQueueReceiveFromISR() can only be used to pass data between a task and and - * ISR. - * - * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data - * from a queue that is being used from within a co-routine (a co-routine - * posted to the queue). - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvBuffer A pointer to a buffer into which the received item will be - * placed. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from the queue into - * pvBuffer. - * - * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become - * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a - * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise - * *pxCoRoutineWoken will remain unchanged. - * - * @return pdTRUE an item was successfully received from the queue, otherwise - * pdFALSE. - * - * Example usage: -

- // A co-routine that posts a character to a queue then blocks for a fixed

- // period.  The character is incremented each time.

- static void vSendingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // cChar holds its value while this co-routine is blocked and must therefore

- // be declared static.

- static portCHAR cCharToTx = 'a';

- portBASE_TYPE xResult;

-

-     // All co-routines must start with a call to crSTART().

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-         // Send the next character to the queue.

-         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );

-

-         if( xResult == pdPASS )

-         {

-             // The character was successfully posted to the queue.

-         }

-		 else

-		 {

-			// Could not post the character to the queue.

-		 }

-

-         // Enable the UART Tx interrupt to cause an interrupt in this

-		 // hypothetical UART.  The interrupt will obtain the character

-		 // from the queue and send it.

-		 ENABLE_RX_INTERRUPT();

-

-		 // Increment to the next character then block for a fixed period.

-		 // cCharToTx will maintain its value across the delay as it is

-		 // declared static.

-		 cCharToTx++;

-		 if( cCharToTx > 'x' )

-		 {

-			cCharToTx = 'a';

-		 }

-		 crDELAY( 100 );

-     }

-

-     // All co-routines must end with a call to crEND().

-     crEND();

- }

-

- // An ISR that uses a queue to receive characters to send on a UART.

- void vUART_ISR( void )

- {

- portCHAR cCharToTx;

- portBASE_TYPE xCRWokenByPost = pdFALSE;

-

-     while( UART_TX_REG_EMPTY() )

-     {

-         // Are there any characters in the queue waiting to be sent?

-		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine

-		 // is woken by the post - ensuring that only a single co-routine is

-		 // woken no matter how many times we go around this loop.

-         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )

-		 {

-			 SEND_CHARACTER( cCharToTx );

-		 }

-     }

- }
- * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR - * \ingroup Tasks - */ -#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( pxQueue, pvBuffer, pxCoRoutineWoken ) - -/* - * This function is intended for internal use by the co-routine macros only. - * The macro nature of the co-routine implementation requires that the - * prototype appears here. The function should not be used by application - * writers. - * - * Removes the current co-routine from its ready list and places it in the - * appropriate delayed list. - */ -void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList ); - -/* - * This function is intended for internal use by the queue implementation only. - * The function should not be used by application writers. - * - * Removes the highest priority co-routine from the event list and places it in - * the pending ready list. - */ -signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList ); - - -#endif /* CO_ROUTINE_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/list.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/list.h deleted file mode 100644 index 8a5b6d042..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/list.h +++ /dev/null @@ -1,270 +0,0 @@ -/* - FreeRTOS.org V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This is the list implementation used by the scheduler. While it is tailored - * heavily for the schedulers needs, it is also available for use by - * application code. - * - * xLists can only store pointers to xListItems. Each xListItem contains a - * numeric value (xItemValue). Most of the time the lists are sorted in - * descending item value order. - * - * Lists are created already containing one list item. The value of this - * item is the maximum possible that can be stored, it is therefore always at - * the end of the list and acts as a marker. The list member pxHead always - * points to this marker - even though it is at the tail of the list. This - * is because the tail contains a wrap back pointer to the true head of - * the list. - * - * In addition to it's value, each list item contains a pointer to the next - * item in the list (pxNext), a pointer to the list it is in (pxContainer) - * and a pointer to back to the object that contains it. These later two - * pointers are included for efficiency of list manipulation. There is - * effectively a two way link between the object containing the list item and - * the list item itself. - * - * - * \page ListIntroduction List Implementation - * \ingroup FreeRTOSIntro - */ - - -#ifndef LIST_H -#define LIST_H - -/* - * Definition of the only type of object that a list can contain. - */ -struct xLIST_ITEM -{ - portTickType xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ - volatile struct xLIST_ITEM * pxNext; /*< Pointer to the next xListItem in the list. */ - volatile struct xLIST_ITEM * pxPrevious;/*< Pointer to the previous xListItem in the list. */ - void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ - void * pvContainer; /*< Pointer to the list in which this list item is placed (if any). */ -}; -typedef struct xLIST_ITEM xListItem; /* For some reason lint wants this as two separate definitions. */ - -struct xMINI_LIST_ITEM -{ - portTickType xItemValue; - volatile struct xLIST_ITEM *pxNext; - volatile struct xLIST_ITEM *pxPrevious; -}; -typedef struct xMINI_LIST_ITEM xMiniListItem; - -/* - * Definition of the type of queue used by the scheduler. - */ -typedef struct xLIST -{ - volatile unsigned portBASE_TYPE uxNumberOfItems; - volatile xListItem * pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to pvListGetOwnerOfNextEntry (). */ - volatile xMiniListItem xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ -} xList; - -/* - * Access macro to set the owner of a list item. The owner of a list item - * is the object (usually a TCB) that contains the list item. - * - * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( pxListItem )->pvOwner = ( void * ) pxOwner - -/* - * Access macro to set the value of the list item. In most cases the value is - * used to sort the list in descending order. - * - * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( pxListItem )->xItemValue = xValue - -/* - * Access macro the retrieve the value of the list item. The value can - * represent anything - for example a the priority of a task, or the time at - * which a task should be unblocked. - * - * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) - -/* - * Access macro to determine if a list contains any items. The macro will - * only have the value true if the list is empty. - * - * \page listLIST_IS_EMPTY listLIST_IS_EMPTY - * \ingroup LinkedList - */ -#define listLIST_IS_EMPTY( pxList ) ( ( pxList )->uxNumberOfItems == ( unsigned portBASE_TYPE ) 0 ) - -/* - * Access macro to return the number of items in the list. - */ -#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) - -/* - * Access function to obtain the owner of the next entry in a list. - * - * The list member pxIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list - * and returns that entries pxOwner parameter. Using multiple calls to this - * function it is therefore possible to move through every item contained in - * a list. - * - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the next item owner is to be returned. - * - * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ - /* Increment the index to the next item and return the item, ensuring */ \ - /* we don't return the marker used at the end of the list. */ \ - ( pxList )->pxIndex = ( pxList )->pxIndex->pxNext; \ - if( ( pxList )->pxIndex == ( xListItem * ) &( ( pxList )->xListEnd ) ) \ - { \ - ( pxList )->pxIndex = ( pxList )->pxIndex->pxNext; \ - } \ - pxTCB = ( pxList )->pxIndex->pvOwner - - -/* - * Access function to obtain the owner of the first entry in a list. Lists - * are normally sorted in ascending item value order. - * - * This function returns the pxOwner member of the first item in the list. - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the owner of the head item is to be - * returned. - * - * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( pxList->uxNumberOfItems != ( unsigned portBASE_TYPE ) 0 ) ? ( (&( pxList->xListEnd ))->pxNext->pvOwner ) : ( NULL ) ) - -/* - * Check to see if a list item is within a list. The list item maintains a - * "container" pointer that points to the list it is in. All this macro does - * is check to see if the container and the list match. - * - * @param pxList The list we want to know if the list item is within. - * @param pxListItem The list item we want to know if is in the list. - * @return pdTRUE is the list item is in the list, otherwise pdFALSE. - * pointer against - */ -#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( pxListItem )->pvContainer == ( void * ) pxList ) - -/* - * Must be called before a list is used! This initialises all the members - * of the list structure and inserts the xListEnd item into the list as a - * marker to the back of the list. - * - * @param pxList Pointer to the list being initialised. - * - * \page vListInitialise vListInitialise - * \ingroup LinkedList - */ -void vListInitialise( xList *pxList ); - -/* - * Must be called before a list item is used. This sets the list container to - * null so the item does not think that it is already contained in a list. - * - * @param pxItem Pointer to the list item being initialised. - * - * \page vListInitialiseItem vListInitialiseItem - * \ingroup LinkedList - */ -void vListInitialiseItem( xListItem *pxItem ); - -/* - * Insert a list item into a list. The item will be inserted into the list in - * a position determined by its item value (descending item value order). - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The item to that is to be placed in the list. - * - * \page vListInsert vListInsert - * \ingroup LinkedList - */ -void vListInsert( xList *pxList, xListItem *pxNewListItem ); - -/* - * Insert a list item into a list. The item will be inserted in a position - * such that it will be the last item within the list returned by multiple - * calls to listGET_OWNER_OF_NEXT_ENTRY. - * - * The list member pvIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list. - * Placing an item in a list using vListInsertEnd effectively places the item - * in the list position pointed to by pvIndex. This means that every other - * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before - * the pvIndex parameter again points to the item being inserted. - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The list item to be inserted into the list. - * - * \page vListInsertEnd vListInsertEnd - * \ingroup LinkedList - */ -void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ); - -/* - * Remove an item from a list. The list item has a pointer to the list that - * it is in, so only the list item need be passed into the function. - * - * @param vListRemove The item to be removed. The item will remove itself from - * the list pointed to by it's pxContainer parameter. - * - * \page vListRemove vListRemove - * \ingroup LinkedList - */ -void vListRemove( xListItem *pxItemToRemove ); - - - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/portable.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/portable.h deleted file mode 100644 index 92d42e2f9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/portable.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - FreeRTOS.org V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http:www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http:www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Portable layer API. Each function must be defined for each port. - *----------------------------------------------------------*/ - -#ifndef PORTABLE_H -#define PORTABLE_H - -/* Include the macro file relevant to the port being used. */ - -#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT - #include "..\..\source\portable\owatcom\16bitdos\pc\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT - #include "..\..\source\portable\owatcom\16bitdos\flsh186\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef GCC_MEGA_AVR - #include "../portable/GCC/ATMega323/portmacro.h" -#endif - -#ifdef IAR_MEGA_AVR - #include "../portable/IAR/ATMega323/portmacro.h" -#endif - -#ifdef MPLAB_PIC18F_PORT - #include "..\..\source\portable\MPLAB\PIC18F\portmacro.h" -#endif - -#ifdef _FEDPICC - #include "libFreeRTOS/Include/portmacro.h" -#endif - -#ifdef SDCC_CYGNAL - #include "../../Source/portable/SDCC/Cygnal/portmacro.h" -#endif - -#ifdef GCC_ARM7 - #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" -#endif - -#ifdef GCC_ARM7_STR71X - #include "freertos/portable/GCC/ARM7_STR71X/portmacro.h" -#endif - -#ifdef GCC_MSP430 - #include "../../Source/portable/GCC/MSP430F449/portmacro.h" -#endif - -#ifdef ROWLEY_MSP430 - #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" -#endif - -#ifdef KEIL_ARM7 - #include "..\..\Source\portable\Keil\ARM7\portmacro.h" -#endif - -#ifdef SAM7_GCC - #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" -#endif - -#ifdef SAM7_IAR - #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" -#endif - -#ifdef LPC2000_IAR - #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" -#endif - -#ifdef STR71X_IAR - #include "..\..\Source\portable\IAR\STR71x\portmacro.h" -#endif - -#ifdef STR91X_IAR - #include "..\..\Source\portable\IAR\STR91x\portmacro.h" -#endif - -#ifdef GCC_H8S - #include "../../Source/portable/GCC/H8S2329/portmacro.h" -#endif - -#ifdef GCC_AT91FR40008 - #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" -#endif - -#ifdef RVDS_ARMCM3_LM3S102 - #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" -#endif - -#ifdef GCC_ARMCM3_LM3S102 - #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" -#endif - -#ifdef IAR_ARMCM3_LM - #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" -#endif - -#ifdef HCS12_CODE_WARRIOR - #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" -#endif - -#ifdef MICROBLAZE_GCC - #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" -#endif - -#ifdef TERN_EE - #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" -#endif - -#ifdef GCC_HCS12 - #include "../../Source/portable/GCC/HCS12/portmacro.h" -#endif - - -#ifdef BCC_INDUSTRIAL_PC_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef BCC_FLASH_LITE_186_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif -/* - * Setup the stack of a new task so it is ready to be placed under the - * scheduler control. The registers have to be placed on the stack in - * the order that the port expects to find them. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ); - -/* - * Map to the memory management routines required for the port. - */ -void *pvPortMalloc( size_t xSize ); -void vPortFree( void *pv ); -void vPortInitialiseBlocks( void ); - -/* - * Setup the hardware ready for the scheduler to take control. This generally - * sets up a tick interrupt and sets timers for the correct tick frequency. - */ -portBASE_TYPE xPortStartScheduler( void ); - -/* - * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so - * the hardware is left in its original condition after the scheduler stops - * executing. - */ -void vPortEndScheduler( void ); - - -#endif /* PORTABLE_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/projdefs.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/projdefs.h deleted file mode 100644 index 052e8f0cc..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/projdefs.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - FreeRTOS.org V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PROJDEFS_H -#define PROJDEFS_H - -/* Defines to prototype to which task functions must conform. */ -typedef void (*pdTASK_CODE)( void * ); - -#define pdTRUE ( 1 ) -#define pdFALSE ( 0 ) - -#define pdPASS ( 1 ) -#define pdFAIL ( 0 ) -#define errQUEUE_EMPTY ( 0 ) -#define errQUEUE_FULL ( 0 ) - -/* Error definitions. */ -#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 ) -#define errNO_TASK_TO_RUN ( -2 ) -#define errQUEUE_BLOCKED ( -4 ) -#define errQUEUE_YIELD ( -5 ) - -#endif /* PROJDEFS_H */ - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/queue.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/queue.h deleted file mode 100644 index 41db1b8d4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/queue.h +++ /dev/null @@ -1,471 +0,0 @@ -/* - FreeRTOS.org V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef QUEUE_H -#define QUEUE_H - -typedef void * xQueueHandle; - -/** - * queue. h - *

- xQueueHandle xQueueCreate( 

-                              unsigned portBASE_TYPE uxQueueLength, 

-                              unsigned portBASE_TYPE uxItemSize 

-                          );

- * 
- * - * Creates a new queue instance. This allocates the storage required by the - * new queue and returns a handle for the queue. - * - * @param uxQueueLength The maximum number of items that the queue can contain. - * - * @param uxItemSize The number of bytes each item in the queue will require. - * Items are queued by copy, not by reference, so this is the number of bytes - * that will be copied for each posted item. Each item on the queue must be - * the same size. - * - * @return If the queue is successfully create then a handle to the newly - * created queue is returned. If the queue cannot be created then 0 is - * returned. - * - * Example usage: -

- struct AMessage

- {

-    portCHAR ucMessageID;

-    portCHAR ucData[ 20 ];

- };

-

- void vATask( void *pvParameters )

- {

- xQueueHandle xQueue1, xQueue2;

-

-    // Create a queue capable of containing 10 unsigned long values.

-    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );

-    if( xQueue1 == 0 )

-    {

-        // Queue was not created and must not be used.

-    }

-

-    // Create a queue capable of containing 10 pointers to AMessage structures.

-    // These should be passed by pointer as they contain a lot of data.

-    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );

-    if( xQueue2 == 0 )

-    {

-        // Queue was not created and must not be used.

-    }

-

-    // ... Rest of task code.

- }

- 
- * \defgroup xQueueCreate xQueueCreate - * \ingroup QueueManagement - */ -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); - -/** - * queue. h - *

- portBASE_TYPE xQueueSend( 

-                             xQueueHandle xQueue, 

-                             const void * pvItemToQueue, 

-                             portTickType xTicksToWait 

-                         );

- * 
- * - * Post an item on a queue. The item is queued by copy, not by reference. - * This function must not be called from an interrupt service routine. - * See xQueueSendFromISR () for an alternative which may be used in an ISR. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for space to become available on the queue, should it already - * be full. The call will return immediately if this is set to 0. The - * time is defined in tick periods so the constant portTICK_RATE_MS - * should be used to convert to real time if this is required. - * - * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. - * - * Example usage: -

- struct AMessage

- {

-    portCHAR ucMessageID;

-    portCHAR ucData[ 20 ];

- } xMessage;

-

- unsigned portLONG ulVar = 10UL;

-

- void vATask( void *pvParameters )

- {

- xQueueHandle xQueue1, xQueue2;

- struct AMessage *pxMessage;

-

-    // Create a queue capable of containing 10 unsigned long values.

-    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );

-

-    // Create a queue capable of containing 10 pointers to AMessage structures.

-    // These should be passed by pointer as they contain a lot of data.

-    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );

-

-    // ...

-

-    if( xQueue1 != 0 )

-    {

-        // Send an unsigned long.  Wait for 10 ticks for space to become 

-        // available if necessary.

-        if( xQueueSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )

-        {

-            // Failed to post the message, even after 10 ticks.

-        }

-    }

-

-    if( xQueue2 != 0 )

-    {

-        // Send a pointer to a struct AMessage object.  Don't block if the

-        // queue is already full.

-        pxMessage = & xMessage;

-        xQueueSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );

-    }

-

-	// ... Rest of task code.

- }

- 
- * \defgroup xQueueSend xQueueSend - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); - -/** - * queue. h - *

- portBASE_TYPE xQueueReceive( 

-                                xQueueHandle xQueue, 

-                                void *pvBuffer, 

-                                portTickType xTicksToWait 

-                            );
- * - * Receive an item from a queue. The item is received by copy so a buffer of - * adequate size must be provided. The number of bytes copied into the buffer - * was defined when the queue was created. - * - * This function must not be used in an interrupt service routine. See - * xQueueReceiveFromISR for an alternative that can. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pvBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for an item to receive should the queue be empty at the time - * of the call. The time is defined in tick periods so the constant - * portTICK_RATE_MS should be used to convert to real time if this is required. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: -

- struct AMessage

- {

-    portCHAR ucMessageID;

-    portCHAR ucData[ 20 ];

- } xMessage;

-

- xQueueHandle xQueue;

- 

- // Task to create a queue and post a value.

- void vATask( void *pvParameters )

- {

- struct AMessage *pxMessage;

-

-    // Create a queue capable of containing 10 pointers to AMessage structures.

-    // These should be passed by pointer as they contain a lot of data.

-    xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );

-    if( xQueue == 0 )

-    {

-        // Failed to create the queue.

-    }

-

-    // ...

-

-    // Send a pointer to a struct AMessage object.  Don't block if the

-    // queue is already full.

-    pxMessage = & xMessage;

-    xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );

-

-	// ... Rest of task code.

- }

-

- // Task to receive from the queue.

- void vADifferentTask( void *pvParameters )

- {

- struct AMessage *pxRxedMessage;

-

-    if( xQueue != 0 )

-    {

-        // Receive a message on the created queue.  Block for 10 ticks if a

-        // message is not immediately available.

-        if( xQueueReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )

-        {

-            // pcRxedMessage now points to the struct AMessage variable posted

-            // by vATask.

-        }

-    }

-

-	// ... Rest of task code.

- }

- 
- * \defgroup xQueueReceive xQueueReceive - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueReceive( xQueueHandle xQueue, void *pvBuffer, portTickType xTicksToWait ); - -/** - * queue. h - *
unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue );
- * - * Return the number of messages stored in a queue. - * - * @param xQueue A handle to the queue being queried. - * - * @return The number of messages available in the queue. - * - * \page uxQueueMessagesWaiting uxQueueMessagesWaiting - * \ingroup QueueManagement - */ -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue ); - -/** - * queue. h - *
void vQueueDelete( xQueueHandle xQueue );
- * - * Delete a queue - freeing all the memory allocated for storing of items - * placed on the queue. - * - * @param xQueue A handle to the queue to be deleted. - * - * \page vQueueDelete vQueueDelete - * \ingroup QueueManagement - */ -void vQueueDelete( xQueueHandle xQueue ); - -/** - * queue. h - *

- portBASE_TYPE xQueueSendFromISR( 

-                                    xQueueHandle pxQueue, 

-                                    const void *pvItemToQueue, 

-                                    portBASE_TYPE xTaskPreviouslyWoken 

-                                );

- 
- * - * Post an item on a queue. It is safe to use this function from within an - * interrupt service routine. - * - * Items are queued by copy not reference so it is preferable to only - * queue small items, especially when called from an ISR. In most cases - * it would be preferable to store a pointer to the item being queued. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param cTaskPreviouslyWoken This is included so an ISR can post onto - * the same queue multiple times from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. See the file serial .c in the - * PC port for a good example of this mechanism. - * - * @return pdTRUE if a task was woken by posting onto the queue. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage for buffered IO (where the ISR can obtain more than one value - * per call): -

- void vBufferISR( void )

- {

- portCHAR cIn;

- portBASE_TYPE xTaskWokenByPost;

-

-    // We have not woken a task at the start of the ISR.

-    cTaskWokenByPost = pdFALSE;

-

-    // Loop until the buffer is empty.

-    do

-    {

-        // Obtain a byte from the buffer.

-        cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );						

-

-        // Post the byte.  The first time round the loop cTaskWokenByPost

-        // will be pdFALSE.  If the queue send causes a task to wake we do

-        // not want the task to run until we have finished the ISR, so

-        // xQueueSendFromISR does not cause a context switch.  Also we 

-        // don't want subsequent posts to wake any other tasks, so we store

-        // the return value back into cTaskWokenByPost so xQueueSendFromISR

-        // knows not to wake any task the next iteration of the loop.

-        xTaskWokenByPost = xQueueSendFromISR( xRxQueue, &cIn, cTaskWokenByPost );

-

-    } while( portINPUT_BYTE( BUFFER_COUNT ) );

-

-    // Now the buffer is empty we can switch context if necessary.

-    if( cTaskWokenByPost )

-    {

-        taskYIELD ();

-    }

- }

- 
- * - * \defgroup xQueueSendFromISR xQueueSendFromISR - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ); - -/** - * queue. h - *

- portBASE_TYPE xQueueReceiveFromISR( 

-                                       xQueueHandle pxQueue, 

-                                       void *pvBuffer, 

-                                       portBASE_TYPE *pxTaskWoken 

-                                   ); 

- * 
- * - * Receive an item from a queue. It is safe to use this function from within an - * interrupt service routine. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pvBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param pxTaskWoken A task may be blocked waiting for space to become - * available on the queue. If xQueueReceiveFromISR causes such a task to - * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will - * remain unchanged. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: -

- 

- xQueueHandle xQueue;

- 

- // Function to create a queue and post some values.

- void vAFunction( void *pvParameters )

- {

- portCHAR cValueToPost;

- const portTickType xBlockTime = ( portTickType )0xff;

-

-    // Create a queue capable of containing 10 characters.

-    xQueue = xQueueCreate( 10, sizeof( portCHAR ) );

-    if( xQueue == 0 )

-    {

-        // Failed to create the queue.

-    }

-

-    // ...

-

-    // Post some characters that will be used within an ISR.  If the queue

-    // is full then this task will block for xBlockTime ticks.

-    cValueToPost = 'a';

-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );

-    cValueToPost = 'b';

-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );

-

-    // ... keep posting characters ... this task may block when the queue

-    // becomes full.

-

-    cValueToPost = 'c';

-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );

- }

-

- // ISR that outputs all the characters received on the queue. 

- void vISR_Routine( void )

- {

- portBASE_TYPE xTaskWokenByReceive = pdFALSE;

- portCHAR cRxedChar;

-

-    while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )

-    {

-        // A character was received.  Output the character now.

-        vOutputCharacter( cRxedChar );

-

-        // If removing the character from the queue woke the task that was 

-        // posting onto the queue cTaskWokenByReceive will have been set to

-        // pdTRUE.  No matter how many times this loop iterates only one

-        // task will be woken.

-    }

-

-    if( cTaskWokenByPost != ( portCHAR ) pdFALSE;

-    {

-        taskYIELD ();

-    }

- }

- 
- * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - - -/* - * The functions defined above are for passing data to and from tasks. The - * functions below are the equivalents for passing data to and from - * co-rtoutines. - * - * These functions are called from the co-routine macro implementation and - * should not be called directly from application code. Instead use the macro - * wrappers defined within croutine.h. - */ -signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ); -signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); -signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ); -signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/semphr.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/semphr.h deleted file mode 100644 index be2864755..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/semphr.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - FreeRTOS.org V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include "queue.h" - -#ifndef SEMAPHORE_H -#define SEMAPHORE_H - -typedef xQueueHandle xSemaphoreHandle; - -#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( unsigned portCHAR ) 1 ) -#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( unsigned portCHAR ) 0 ) -#define semGIVE_BLOCK_TIME ( ( portTickType ) 0 ) - - -/** - * semphr. h - *
vSemaphoreCreateBinary( xSemaphoreHandle xSemaphore )
- * - * Macro that implements a semaphore by using the existing queue mechanism. - * The queue length is 1 as this is a binary semaphore. The data size is 0 - * as we don't want to actually store any data - we just want to know if the - * queue is empty or full. - * - * @param xSemaphore Handle to the created semaphore. Should be of type xSemaphoreHandle. - * - * Example usage: -

- xSemaphoreHandle xSemaphore;

-

- void vATask( void * pvParameters )

- {

-    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().

-    // This is a macro so pass the variable in directly.

-    vSemaphoreCreateBinary( xSemaphore );

-

-    if( xSemaphore != NULL )

-    {

-        // The semaphore was created successfully.

-        // The semaphore can now be used.  

-    }

- }

- 
- * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary - * \ingroup Semaphores - */ -#define vSemaphoreCreateBinary( xSemaphore ) { \ - xSemaphore = xQueueCreate( ( unsigned portCHAR ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH ); \ - if( xSemaphore != NULL ) \ - { \ - xSemaphoreGive( xSemaphore ); \ - } \ - } - -/** - * semphr. h - * xSemaphoreTake( - * xSemaphoreHandle xSemaphore, - * portTickType xBlockTime - * ) - * - * Macro to obtain a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (). - * - * @param xSemaphore A handle to the semaphore being obtained. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @param xBlockTime The time in ticks to wait for the semaphore to become - * available. The macro portTICK_RATE_MS can be used to convert this to a - * real time. A block time of zero can be used to poll the semaphore. - * - * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime - * expired without the semaphore becoming available. - * - * Example usage: -

- xSemaphoreHandle xSemaphore = NULL;

-

- // A task that creates a semaphore.

- void vATask( void * pvParameters )

- {

-    // Create the semaphore to guard a shared resource.

-    vSemaphoreCreateBinary( xSemaphore );

- }

-

- // A task that uses the semaphore.

- void vAnotherTask( void * pvParameters )

- {

-    // ... Do other things.

-

-    if( xSemaphore != NULL )

-    {

-        // See if we can obtain the semaphore.  If the semaphore is not available

-        // wait 10 ticks to see if it becomes free.	

-        if( xSemaphoreTake( xSemaphore, ( portTickType ) 10 ) == pdTRUE )

-        {

-            // We were able to obtain the semaphore and can now access the

-            // shared resource.

-

-            // ...

-

-            // We have finished accessing the shared resource.  Release the 

-            // semaphore.

-            xSemaphoreGive( xSemaphore );

-        }

-        else

-        {

-            // We could not obtain the semaphore and can therefore not access

-            // the shared resource safely.

-        }

-    }

- }

- 
- * \defgroup xSemaphoreTake xSemaphoreTake - * \ingroup Semaphores - */ -#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueReceive( ( xQueueHandle ) xSemaphore, NULL, xBlockTime ) - -/** - * semphr. h - *
xSemaphoreGive( xSemaphoreHandle xSemaphore )
- * - * Macro to release a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (), and obtained using sSemaphoreTake (). - * - * This must not be used from an ISR. See xSemaphoreGiveFromISR () for - * an alternative which can be used from an ISR. - * - * @param xSemaphore A handle to the semaphore being released. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. - * Semaphores are implemented using queues. An error can occur if there is - * no space on the queue to post a message - indicating that the - * semaphore was not first obtained correctly. - * - * Example usage: -

- xSemaphoreHandle xSemaphore = NULL;

-

- void vATask( void * pvParameters )

- {

-    // Create the semaphore to guard a shared resource.

-    vSemaphoreCreateBinary( xSemaphore );

-

-    if( xSemaphore != NULL )

-    {

-        if( xSemaphoreGive( xSemaphore ) != pdTRUE )

-        {

-            // We would expect this call to fail because we cannot give

-            // a semaphore without first "taking" it!

-        }

-

-        // Obtain the semaphore - don't block if the semaphore is not

-        // immediately available.

-        if( xSemaphoreTake( xSemaphore, ( portTickType ) 0 ) )

-        {

-            // We now have the semaphore and can access the shared resource.

-

-            // ...

-

-            // We have finished accessing the shared resource so can free the

-            // semaphore.

-            if( xSemaphoreGive( xSemaphore ) != pdTRUE )

-            {

-                // We would not expect this call to fail because we must have

-                // obtained the semaphore to get here.

-            }

-        }

-    }

- }

- 
- * \defgroup xSemaphoreGive xSemaphoreGive - * \ingroup Semaphores - */ -#define xSemaphoreGive( xSemaphore ) xQueueSend( ( xQueueHandle ) xSemaphore, NULL, semGIVE_BLOCK_TIME ) - -/** - * semphr. h - *

- xSemaphoreGiveFromISR( 

-                          xSemaphoreHandle xSemaphore, 

-                          portSHORT sTaskPreviouslyWoken 

-                      )
- * - * Macro to release a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (), and obtained using xSemaphoreTake (). - * - * This macro can be used from an ISR. - * - * @param xSemaphore A handle to the semaphore being released. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @param sTaskPreviouslyWoken This is included so an ISR can make multiple calls - * to xSemaphoreGiveFromISR () from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. See the file serial .c in the - * PC port for a good example of using xSemaphoreGiveFromISR (). - * - * @return pdTRUE if a task was woken by releasing the semaphore. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage: -

- #define LONG_TIME 0xffff

- #define TICKS_TO_WAIT	10

- xSemaphoreHandle xSemaphore = NULL;

-

- // Repetitive task.

- void vATask( void * pvParameters )

- {

-    for( ;; )

-    {

-        // We want this task to run every 10 ticks or a timer.  The semaphore 

-        // was created before this task was started

-

-        // Block waiting for the semaphore to become available.

-        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )

-        {

-            // It is time to execute.

-

-            // ...

-

-            // We have finished our task.  Return to the top of the loop where

-            // we will block on the semaphore until it is time to execute 

-            // again.

-        }

-    }

- }

-

- // Timer ISR

- void vTimerISR( void * pvParameters )

- {

- static unsigned portCHAR ucLocalTickCount = 0;

-

-    // A timer tick has occurred.

-

-    // ... Do other time functions.

-

-    // Is it time for vATask () to run?

-    ucLocalTickCount++;

-    if( ucLocalTickCount >= TICKS_TO_WAIT )

-    {

-        // Unblock the task by releasing the semaphore.

-        xSemaphoreGive( xSemaphore );

-

-        // Reset the count so we release the semaphore again in 10 ticks time.

-        ucLocalTickCount = 0;

-    }

- }

- 
- * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR - * \ingroup Semaphores - */ -#define xSemaphoreGiveFromISR( xSemaphore, xTaskPreviouslyWoken ) xQueueSendFromISR( ( xQueueHandle ) xSemaphore, NULL, xTaskPreviouslyWoken ) - - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/task.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/task.h deleted file mode 100644 index ca0085349..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/include/task.h +++ /dev/null @@ -1,951 +0,0 @@ -/* - FreeRTOS.org V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef TASK_H -#define TASK_H - -#include "portable.h" -#include "list.h" - -/*----------------------------------------------------------- - * MACROS AND DEFINITIONS - *----------------------------------------------------------*/ - -#define tskKERNEL_VERSION_NUMBER "V4.1.1" - -/** - * task. h - * - * Type by which tasks are referenced. For example, a call to xTaskCreate - * returns (via a pointer parameter) an xTaskHandle variable that can then - * be used as a parameter to vTaskDelete to delete the task. - * - * \page xTaskHandle xTaskHandle - * \ingroup Tasks - */ -typedef void * xTaskHandle; - -/* - * Used internally only. - */ -typedef struct xTIME_OUT -{ - portBASE_TYPE xOverflowCount; - portTickType xTimeOnEntering; -} xTimeOutType; - -/* - * Defines the priority used by the idle task. This must not be modified. - * - * \ingroup TaskUtils - */ -#define tskIDLE_PRIORITY ( ( unsigned portBASE_TYPE ) 0 ) - -/** - * task. h - * - * Macro for forcing a context switch. - * - * \page taskYIELD taskYIELD - * \ingroup SchedulerControl - */ -#define taskYIELD() portYIELD() - -/** - * task. h - * - * Macro to mark the start of a critical code region. Preemptive context - * switches cannot occur when in a critical region. - * - * NOTE: This may alter the stack (depending on the portable implementation) - * so must be used with care! - * - * \page taskENTER_CRITICAL taskENTER_CRITICAL - * \ingroup SchedulerControl - */ -#define taskENTER_CRITICAL() portENTER_CRITICAL() - -/** - * task. h - * - * Macro to mark the end of a critical code region. Preemptive context - * switches cannot occur when in a critical region. - * - * NOTE: This may alter the stack (depending on the portable implementation) - * so must be used with care! - * - * \page taskEXIT_CRITICAL taskEXIT_CRITICAL - * \ingroup SchedulerControl - */ -#define taskEXIT_CRITICAL() portEXIT_CRITICAL() - -/** - * task. h - * - * Macro to disable all maskable interrupts. - * - * \page taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS - * \ingroup SchedulerControl - */ -#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() - -/** - * task. h - * - * Macro to enable microcontroller interrupts. - * - * \page taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS - * \ingroup SchedulerControl - */ -#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() - - -/*----------------------------------------------------------- - * TASK CREATION API - *----------------------------------------------------------*/ - -/** - * task. h - *

- portBASE_TYPE xTaskCreate(

-                              pdTASK_CODE pvTaskCode,

-                              const portCHAR * const pcName,

-                              unsigned portSHORT usStackDepth,

-                              void *pvParameters,

-                              unsigned portBASE_TYPE uxPriority,

-                              xTaskHandle *pvCreatedTask

-                          );
- * - * Create a new task and add it to the list of tasks that are ready to run. - * - * @param pvTaskCode Pointer to the task entry function. Tasks - * must be implemented to never return (i.e. continuous loop). - * - * @param pcName A descriptive name for the task. This is mainly used to - * facilitate debugging. Max length defined by tskMAX_TASK_NAME_LEN - default - * is 16. - * - * @param usStackDepth The size of the task stack specified as the number of - * variables the stack can hold - not the number of bytes. For example, if - * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes - * will be allocated for stack storage. - * - * @param pvParameters Pointer that will be used as the parameter for the task - * being created. - * - * @param uxPriority The priority at which the task should run. - * - * @param pvCreatedTask Used to pass back a handle by which the created task - * can be referenced. - * - * @return pdPASS if the task was successfully created and added to a ready - * list, otherwise an error code defined in the file errors. h - * - * Example usage: -

- // Task to be created.

- void vTaskCode( void * pvParameters )

- {

-     for( ;; )

-     {

-         // Task code goes here.

-     }

- }

-

- // Function that creates a task.

- void vOtherFunction( void )

- {

- unsigned char ucParameterToPass;

- xTaskHandle xHandle;

-		

-     // Create the task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );

-		

-     // Use the handle to delete the task.

-     vTaskDelete( xHandle );

- }

-   
- * \defgroup xTaskCreate xTaskCreate - * \ingroup Tasks - */ -signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pvCreatedTask ); - -/** - * task. h - *
void vTaskDelete( xTaskHandle pxTask );
- * - * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Remove a task from the RTOS real time kernels management. The task being - * deleted will be removed from all ready, blocked, suspended and event lists. - * - * NOTE: The idle task is responsible for freeing the kernel allocated - * memory from tasks that have been deleted. It is therefore important that - * the idle task is not starved of microcontroller processing time if your - * application makes any calls to vTaskDelete (). Memory allocated by the - * task code is not automatically freed, and should be freed before the task - * is deleted. - * - * See the demo application file death.c for sample code that utilises - * vTaskDelete (). - * - * @param pxTask The handle of the task to be deleted. Passing NULL will - * cause the calling task to be deleted. - * - * Example usage: -

- void vOtherFunction( void )

- {

- xTaskHandle xHandle;

-		

-     // Create the task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

-		

-     // Use the handle to delete the task.

-     vTaskDelete( xHandle );

- }

-   
- * \defgroup vTaskDelete vTaskDelete - * \ingroup Tasks - */ -void vTaskDelete( xTaskHandle pxTask ); - - -/*----------------------------------------------------------- - * TASK CONTROL API - *----------------------------------------------------------*/ - -/** - * task. h - *
void vTaskDelay( portTickType xTicksToDelay );
- * - * Delay a task for a given number of ticks. The actual time that the - * task remains blocked depends on the tick rate. The constant - * portTICK_RATE_MS can be used to calculate real time from the tick - * rate - with the resolution of one tick period. - * - * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * @param xTicksToDelay The amount of time, in tick periods, that - * the calling task should block. - * - * Example usage: -

- // Wait 10 ticks before performing an action.

- // NOTE:

- // This is for demonstration only and would be better achieved

- // using vTaskDelayUntil ().

- void vTaskFunction( void * pvParameters )

- {

- portTickType xDelay, xNextTime;

-

-     // Calc the time at which we want to perform the action

-     // next.

-     xNextTime = xTaskGetTickCount () + ( portTickType ) 10;

-

-     for( ;; )

-     {

-         xDelay = xNextTime - xTaskGetTickCount ();

-         xNextTime += ( portTickType ) 10;

-

-         // Guard against overflow

-         if( xDelay <= ( portTickType ) 10 )

-         {

-             vTaskDelay( xDelay );

-         }

-

-         // Perform action here.

-     }

- }

-   
- * \defgroup vTaskDelay vTaskDelay - * \ingroup TaskCtrl - */ -void vTaskDelay( portTickType xTicksToDelay ); - -/** - * task. h - *
void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement );
- * - * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Delay a task until a specified time. This function can be used by cyclical - * tasks to ensure a constant execution frequency. - * - * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will - * cause a task to block for the specified number of ticks from the time vTaskDelay () is - * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed - * execution frequency as the time between a task starting to execute and that task - * calling vTaskDelay () may not be fixed [the task may take a different path though the - * code between calls, or may get interrupted or preempted a different number of times - * each time it executes]. - * - * Whereas vTaskDelay () specifies a wake time relative to the time at which the function - * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to - * unblock. - * - * The constant portTICK_RATE_MS can be used to calculate real time from the tick - * rate - with the resolution of one tick period. - * - * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the - * task was last unblocked. The variable must be initialised with the current time - * prior to its first use (see the example below). Following this the variable is - * automatically updated within vTaskDelayUntil (). - * - * @param xTimeIncrement The cycle time period. The task will be unblocked at - * time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the - * same xTimeIncrement parameter value will cause the task to execute with - * a fixed interface period. - * - * Example usage: -

- // Perform an action every 10 ticks.

- void vTaskFunction( void * pvParameters )

- {

- portTickType xLastWakeTime;

- const portTickType xFrequency = 10;

-

-     // Initialise the xLastWakeTime variable with the current time.

-     xLastWakeTime = xTaskGetTickCount ();

-     for( ;; )

-     {

-         // Wait for the next cycle.

-         vTaskDelayUntil( &xLastWakeTime, xFrequency );

-

-         // Perform action here.

-     }

- }

-   
- * \defgroup vTaskDelayUntil vTaskDelayUntil - * \ingroup TaskCtrl - */ -void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement ); - -/** - * task. h - *
unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask );
- * - * INCLUDE_xTaskPriorityGet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Obtain the priority of any task. - * - * @param pxTask Handle of the task to be queried. Passing a NULL - * handle results in the priority of the calling task being returned. - * - * @return The priority of pxTask. - * - * Example usage: -

- void vAFunction( void )

- {

- xTaskHandle xHandle;

-		

-     // Create a task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

-		

-     // ...

-

-     // Use the handle to obtain the priority of the created task.

-     // It was created with tskIDLE_PRIORITY, but may have changed

-     // it itself.

-     if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )

-     {

-         // The task has changed it's priority.

-     }

-

-     // ...

-

-     // Is our priority higher than the created task?

-     if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )

-     {

-         // Our priority (obtained using NULL handle) is higher.

-     }

- }

-   
- * \defgroup uxTaskPriorityGet uxTaskPriorityGet - * \ingroup TaskCtrl - */ -unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ); - -/** - * task. h - *
void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );
- * - * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Set the priority of any task. - * - * A context switch will occur before the function returns if the priority - * being set is higher than the currently executing task. - * - * @param pxTask Handle to the task for which the priority is being set. - * Passing a NULL handle results in the priority of the calling task being set. - * - * @param uxNewPriority The priority to which the task will be set. - * - * Example usage: -

- void vAFunction( void )

- {

- xTaskHandle xHandle;

-		

-     // Create a task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

-

-     // ...

-

-     // Use the handle to raise the priority of the created task.

-     vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );

-

-     // ...

-

-     // Use a NULL handle to raise our priority to the same value.

-     vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );

- }

-   
- * \defgroup vTaskPrioritySet vTaskPrioritySet - * \ingroup TaskCtrl - */ -void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ); - -/** - * task. h - *
void vTaskSuspend( xTaskHandle pxTaskToSuspend );
- * - * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Suspend any task. When suspended a task will never get any microcontroller - * processing time, no matter what its priority. - * - * Calls to vTaskSuspend are not accumulative - - * i.e. calling vTaskSuspend () twice on the same task still only requires one - * call to vTaskResume () to ready the suspended task. - * - * @param pxTaskToSuspend Handle to the task being suspended. Passing a NULL - * handle will cause the calling task to be suspended. - * - * Example usage: -

- void vAFunction( void )

- {

- xTaskHandle xHandle;

-		

-     // Create a task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

-		

-     // ...

-

-     // Use the handle to suspend the created task.

-     vTaskSuspend( xHandle );

-

-     // ...

-		

-     // The created task will not run during this period, unless

-     // another task calls vTaskResume( xHandle ).

-		

-     //...

-		

-

-     // Suspend ourselves.

-     vTaskSuspend( NULL );

-

-     // We cannot get here unless another task calls vTaskResume

-     // with our handle as the parameter.

- }

-   
- * \defgroup vTaskSuspend vTaskSuspend - * \ingroup TaskCtrl - */ -void vTaskSuspend( xTaskHandle pxTaskToSuspend ); - -/** - * task. h - *
void vTaskResume( xTaskHandle pxTaskToResume );
- * - * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Resumes a suspended task. - * - * A task that has been suspended by one of more calls to vTaskSuspend () - * will be made available for running again by a single call to - * vTaskResume (). - * - * @param pxTaskToResume Handle to the task being readied. - * - * Example usage: -

- void vAFunction( void )

- {

- xTaskHandle xHandle;

-		

-     // Create a task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

-		

-     // ...

-

-     // Use the handle to suspend the created task.

-     vTaskSuspend( xHandle );

-

-     // ...

-	

-     // The created task will not run during this period, unless

-     // another task calls vTaskResume( xHandle ).

-		

-     //...

-		

-

-     // Resume the suspended task ourselves.

-     vTaskResume( xHandle );

-

-     // The created task will once again get microcontroller processing

-     // time in accordance with it priority within the system.

- }

-   
- * \defgroup vTaskResume vTaskResume - * \ingroup TaskCtrl - */ -void vTaskResume( xTaskHandle pxTaskToResume ); - -/** - * task. h - *
void xTaskResumeFromISR( xTaskHandle pxTaskToResume );
- * - * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be - * available. See the configuration section for more information. - * - * An implementation of vTaskResume() that can be called from within an ISR. - * - * A task that has been suspended by one of more calls to vTaskSuspend () - * will be made available for running again by a single call to - * xTaskResumeFromISR (). - * - * @param pxTaskToResume Handle to the task being readied. - * - * \defgroup vTaskResumeFromISR vTaskResumeFromISR - * \ingroup TaskCtrl - */ -portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ); - -/*----------------------------------------------------------- - * SCHEDULER CONTROL - *----------------------------------------------------------*/ - -/** - * task. h - *
void vTaskStartScheduler( void );
- * - * Starts the real time kernel tick processing. After calling the kernel - * has control over which tasks are executed and when. This function - * does not return until an executing task calls vTaskEndScheduler (). - * - * At least one task should be created via a call to xTaskCreate () - * before calling vTaskStartScheduler (). The idle task is created - * automatically when the first application task is created. - * - * See the demo application file main.c for an example of creating - * tasks and starting the kernel. - * - * Example usage: -

- void vAFunction( void )

- {

-     // Create at least one task before starting the kernel.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );

-

-     // Start the real time kernel with preemption.

-     vTaskStartScheduler ();

-

-     // Will not get here unless a task calls vTaskEndScheduler ()

- }

-   
- * - * \defgroup vTaskStartScheduler vTaskStartScheduler - * \ingroup SchedulerControl - */ -void vTaskStartScheduler( void ); - -/** - * task. h - *
void vTaskEndScheduler( void );
- * - * Stops the real time kernel tick. All created tasks will be automatically - * deleted and multitasking (either preemptive or cooperative) will - * stop. Execution then resumes from the point where vTaskStartScheduler () - * was called, as if vTaskStartScheduler () had just returned. - * - * See the demo application file main. c in the demo/PC directory for an - * example that uses vTaskEndScheduler (). - * - * vTaskEndScheduler () requires an exit function to be defined within the - * portable layer (see vPortEndScheduler () in port. c for the PC port). This - * performs hardware specific operations such as stopping the kernel tick. - * - * vTaskEndScheduler () will cause all of the resources allocated by the - * kernel to be freed - but will not free resources allocated by application - * tasks. - * - * Example usage: -

- void vTaskCode( void * pvParameters )

- {

-     for( ;; )

-     {

-         // Task code goes here.

-

-         // At some point we want to end the real time kernel processing

-         // so call ...

-         vTaskEndScheduler ();

-     }

- }

-

- void vAFunction( void )

- {

-     // Create at least one task before starting the kernel.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );

-

-     // Start the real time kernel with preemption.

-     vTaskStartScheduler ();

-

-     // Will only get here when the vTaskCode () task has called

-     // vTaskEndScheduler ().  When we get here we are back to single task

-     // execution.

- }

-   
- * - * \defgroup vTaskEndScheduler vTaskEndScheduler - * \ingroup SchedulerControl - */ -void vTaskEndScheduler( void ); - -/** - * task. h - *
void vTaskSuspendAll( void );
- * - * Suspends all real time kernel activity while keeping interrupts (including the - * kernel tick) enabled. - * - * After calling vTaskSuspendAll () the calling task will continue to execute - * without risk of being swapped out until a call to xTaskResumeAll () has been - * made. - * - * Example usage: -

- void vTask1( void * pvParameters )

- {

-     for( ;; )

-     {

-         // Task code goes here.

-

-         // ...

-

-         // At some point the task wants to perform a long operation during

-         // which it does not want to get swapped out.  It cannot use

-         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the

-         // operation may cause interrupts to be missed - including the

-         // ticks.

-

-         // Prevent the real time kernel swapping out the task.

-         vTaskSuspendAll ();

-

-         // Perform the operation here.  There is no need to use critical

-         // sections as we have all the microcontroller processing time.

-         // During this time interrupts will still operate and the kernel

-         // tick count will be maintained.

-

-         // ...

-

-         // The operation is complete.  Restart the kernel.

-         xTaskResumeAll ();

-     }

- }

-   
- * \defgroup vTaskSuspendAll vTaskSuspendAll - * \ingroup SchedulerControl - */ -void vTaskSuspendAll( void ); - -/** - * task. h - *
portCHAR xTaskResumeAll( void );
- * - * Resumes real time kernel activity following a call to vTaskSuspendAll (). - * After a call to vTaskSuspendAll () the kernel will take control of which - * task is executing at any time. - * - * @return If resuming the scheduler caused a context switch then pdTRUE is - * returned, otherwise pdFALSE is returned. - * - * Example usage: -

- void vTask1( void * pvParameters )

- {

-     for( ;; )

-     {

-         // Task code goes here.

-

-         // ...

-

-         // At some point the task wants to perform a long operation during

-         // which it does not want to get swapped out.  It cannot use

-         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the

-         // operation may cause interrupts to be missed - including the

-         // ticks.

-

-         // Prevent the real time kernel swapping out the task.

-         vTaskSuspendAll ();

-

-         // Perform the operation here.  There is no need to use critical

-         // sections as we have all the microcontroller processing time.

-         // During this time interrupts will still operate and the real

-         // time kernel tick count will be maintained.

-

-         // ...

-

-         // The operation is complete.  Restart the kernel.  We want to force

-         // a context switch - but there is no point if resuming the scheduler

-         // caused a context switch already.

-         if( !xTaskResumeAll () )

-         {

-              taskYIELD ();

-         }

-     }

- }

-   
- * \defgroup xTaskResumeAll xTaskResumeAll - * \ingroup SchedulerControl - */ -signed portBASE_TYPE xTaskResumeAll( void ); - - -/*----------------------------------------------------------- - * TASK UTILITIES - *----------------------------------------------------------*/ - -/** - * task. h - *
volatile portTickType xTaskGetTickCount( void );
- * - * @return The count of ticks since vTaskStartScheduler was called. - * - * \page xTaskGetTickCount xTaskGetTickCount - * \ingroup TaskUtils - */ -portTickType xTaskGetTickCount( void ); - -/** - * task. h - *
unsigned portSHORT uxTaskGetNumberOfTasks( void );
- * - * @return The number of tasks that the real time kernel is currently managing. - * This includes all ready, blocked and suspended tasks. A task that - * has been deleted but not yet freed by the idle task will also be - * included in the count. - * - * \page uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks - * \ingroup TaskUtils - */ -unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ); - -/** - * task. h - *
void vTaskList( portCHAR *pcWriteBuffer );
- * - * configUSE_TRACE_FACILITY, INCLUDE_vTaskDelete and INCLUDE_vTaskSuspend - * must all be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * NOTE: This function will disable interrupts for its duration. It is - * not intended for normal application runtime use but as a debug aid. - * - * Lists all the current tasks, along with their current state and stack - * usage high water mark. - * - * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or - * suspended ('S'). - * - * @param pcWriteBuffer A buffer into which the above mentioned details - * will be written, in ascii form. This buffer is assumed to be large - * enough to contain the generated report. Approximately 40 bytes per - * task should be sufficient. - * - * \page vTaskList vTaskList - * \ingroup TaskUtils - */ -void vTaskList( signed portCHAR *pcWriteBuffer ); - -/** - * task. h - *
void vTaskStartTrace( portCHAR * pcBuffer, unsigned portBASE_TYPE uxBufferSize );
- * - * Starts a real time kernel activity trace. The trace logs the identity of - * which task is running when. - * - * The trace file is stored in binary format. A separate DOS utility called - * convtrce.exe is used to convert this into a tab delimited text file which - * can be viewed and plotted in a spread sheet. - * - * @param pcBuffer The buffer into which the trace will be written. - * - * @param ulBufferSize The size of pcBuffer in bytes. The trace will continue - * until either the buffer in full, or ulTaskEndTrace () is called. - * - * \page vTaskStartTrace vTaskStartTrace - * \ingroup TaskUtils - */ -void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ); - -/** - * task. h - *
unsigned portLONG ulTaskEndTrace( void );
- * - * Stops a kernel activity trace. See vTaskStartTrace (). - * - * @return The number of bytes that have been written into the trace buffer. - * - * \page usTaskEndTrace usTaskEndTrace - * \ingroup TaskUtils - */ -unsigned portLONG ulTaskEndTrace( void ); - - -/*----------------------------------------------------------- - * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES - *----------------------------------------------------------*/ - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY - * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS - * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * Called from the real time kernel tick (either preemptive or cooperative), - * this increments the tick count and checks if any tasks that are blocked - * for a finite period required removing from a blocked list and placing on - * a ready list. - */ -inline void vTaskIncrementTick( void ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. - * - * Removes the calling task from the ready list and places it both - * on the list of tasks waiting for a particular event, and the - * list of delayed tasks. The task will be removed from both lists - * and replaced on the ready list should either the event occur (and - * there be no higher priority tasks waiting on the same event) or - * the delay period expires. - * - * @param pxEventList The list containing tasks that are blocked waiting - * for the event to occur. - * - * @param xTicksToWait The maximum amount of time that the task should wait - * for the event to occur. This is specified in kernel ticks,the constant - * portTICK_RATE_MS can be used to convert kernel ticks into a real time - * period. - */ -void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. - * - * Removes a task from both the specified event list and the list of blocked - * tasks, and places it on a ready queue. - * - * xTaskRemoveFromEventList () will be called if either an event occurs to - * unblock a task, or the block timeout period expires. - * - * @return pdTRUE if the task being removed has a higher priority than the task - * making the call, otherwise pdFALSE. - */ -signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * INCLUDE_vTaskCleanUpResources and INCLUDE_vTaskSuspend must be defined as 1 - * for this function to be available. - * See the configuration section for more information. - * - * Empties the ready and delayed queues of task control blocks, freeing the - * memory allocated for the task control block and task stacks as it goes. - */ -void vTaskCleanUpResources( void ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY - * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS - * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * Sets the pointer to the current TCB to the TCB of the highest priority task - * that is ready to run. - */ -inline void vTaskSwitchContext( void ); - -/* - * Return the handle of the calling task. - */ -xTaskHandle xTaskGetCurrentTaskHandle( void ); - -/* - * Capture the current time status for future reference. - */ -void vTaskSetTimeOutState( xTimeOutType *pxTimeOut ); - -/* - * Compare the time status now with that previously captured to see if the - * timeout has expired. - */ -portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType *pxTimeOut, portTickType *pxTicksToWait ); - -/* - * Shortcut used by the queue implementation to prevent unnecessary call to - * taskYIELD(); - */ -void vTaskMissedYield( void ); - -#endif /* TASK_H */ - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/list.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/list.c deleted file mode 100644 index 8efc2e33b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/list.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - FreeRTOS.org V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.2.0 - - + Removed the volatile modifier from the function parameters. This was - only ever included to prevent compiler warnings. Now warnings are - removed by casting parameters where the calls are made. - - + prvListGetOwnerOfNextEntry() and prvListGetOwnerOfHeadEntry() have been - removed from the c file and added as macros to the h file. - - + uxNumberOfItems has been added to the list structure. This removes the - need for a pointer comparison when checking if a list is empty, and so - is slightly faster. - - + Removed the NULL check in vListRemove(). This makes the call faster but - necessitates any application code utilising the list implementation to - ensure NULL pointers are not passed. - -Changes from V2.0.0 - - + Double linked the lists to allow faster removal item removal. - -Changes from V2.6.1 - - + Make use of the new portBASE_TYPE definition where ever appropriate. - -Changes from V3.0.0 - - + API changes as described on the FreeRTOS.org WEB site. - -Changes from V3.2.4 - - + Removed the pxHead member of the xList structure. This always pointed - to the same place so has been removed to free a few bytes of RAM. - - + Introduced the xMiniListItem structure that does not include the - xListItem members that are not required by the xListEnd member of a list. - Again this was done to reduce RAM usage. - - + Changed the volatile definitions of some structure members to clean up - the code where the list structures are used. - -Changes from V4.0.4 - - + Optimised vListInsert() in the case when the wake time is the maximum - tick count value. -*/ - -#include -#include "FreeRTOS.h" -#include "list.h" - -/*----------------------------------------------------------- - * PUBLIC LIST API documented in list.h - *----------------------------------------------------------*/ - -void vListInitialise( xList *pxList ) -{ - /* The list structure contains a list item which is used to mark the - end of the list. To initialise the list the list end is inserted - as the only list entry. */ - pxList->pxIndex = ( xListItem * ) &( pxList->xListEnd ); - - /* The list end value is the highest possible value in the list to - ensure it remains at the end of the list. */ - pxList->xListEnd.xItemValue = portMAX_DELAY; - - /* The list end next and previous pointers point to itself so we know - when the list is empty. */ - pxList->xListEnd.pxNext = ( xListItem * ) &( pxList->xListEnd ); - pxList->xListEnd.pxPrevious = ( xListItem * ) &( pxList->xListEnd ); - - pxList->uxNumberOfItems = 0; -} -/*-----------------------------------------------------------*/ - -void vListInitialiseItem( xListItem *pxItem ) -{ - /* Make sure the list item is not recorded as being on a list. */ - pxItem->pvContainer = NULL; -} -/*-----------------------------------------------------------*/ - -void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ) -{ -volatile xListItem * pxIndex; - - /* Insert a new list item into pxList, but rather than sort the list, - makes the new list item the last item to be removed by a call to - pvListGetOwnerOfNextEntry. This means it has to be the item pointed to by - the pxIndex member. */ - pxIndex = pxList->pxIndex; - - pxNewListItem->pxNext = pxIndex->pxNext; - pxNewListItem->pxPrevious = pxList->pxIndex; - pxIndex->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; - pxIndex->pxNext = ( volatile xListItem * ) pxNewListItem; - pxList->pxIndex = ( volatile xListItem * ) pxNewListItem; - - /* Remember which list the item is in. */ - pxNewListItem->pvContainer = ( void * ) pxList; - - ( pxList->uxNumberOfItems )++; -} -/*-----------------------------------------------------------*/ - -void vListInsert( xList *pxList, xListItem *pxNewListItem ) -{ -volatile xListItem *pxIterator; -portTickType xValueOfInsertion; - - /* Insert the new list item into the list, sorted in ulListItem order. */ - xValueOfInsertion = pxNewListItem->xItemValue; - - /* If the list already contains a list item with the same item value then - the new list item should be placed after it. This ensures that TCB's which - are stored in ready lists (all of which have the same ulListItem value) - get an equal share of the CPU. However, if the xItemValue is the same as - the back marker the iteration loop below will not end. This means we need - to guard against this by checking the value first and modifying the - algorithm slightly if necessary. */ - if( xValueOfInsertion == portMAX_DELAY ) - { - pxIterator = pxList->xListEnd.pxPrevious; - } - else - { - for( pxIterator = ( xListItem * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) - { - /* There is nothing to do here, we are just iterating to the - wanted insertion position. */ - } - } - - pxNewListItem->pxNext = pxIterator->pxNext; - pxNewListItem->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; - pxNewListItem->pxPrevious = pxIterator; - pxIterator->pxNext = ( volatile xListItem * ) pxNewListItem; - - /* Remember which list the item is in. This allows fast removal of the - item later. */ - pxNewListItem->pvContainer = ( void * ) pxList; - - ( pxList->uxNumberOfItems )++; -} -/*-----------------------------------------------------------*/ - -void vListRemove( xListItem *pxItemToRemove ) -{ -xList * pxList; - - pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; - pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; - - /* The list item knows which list it is in. Obtain the list from the list - item. */ - pxList = ( xList * ) pxItemToRemove->pvContainer; - - /* Make sure the index is left pointing to a valid item. */ - if( pxList->pxIndex == pxItemToRemove ) - { - pxList->pxIndex = pxItemToRemove->pxPrevious; - } - - pxItemToRemove->pvContainer = NULL; - ( pxList->uxNumberOfItems )--; -} -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/GCC/ARM7_STR71X/port.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/GCC/ARM7_STR71X/port.c deleted file mode 100644 index 5fd7a657a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/GCC/ARM7_STR71X/port.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - FreeRTOS V4.1.1 - Copyright (C) 2003-2005 Richard Barry. - Modification for STR71X/GCC - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* ----------------------- Standard includes --------------------------------*/ -#include - -/* ----------------------- FreeRTOS includes --------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" - -/* ----------------------- System includes ----------------------------------*/ -#include "eic.h" -#include "wdg.h" - -#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */ -#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) -#define portNO_CRITICAL_SECTION_NESTING \ - ( ( portSTACK_TYPE ) 0 ) - -/* ----------------------- Prototypes ---------------------------------------*/ - -/* Setup the timer to generate the tick interrupts. */ -static void prvSetupTimerInterrupt( void ); - -/* The scheduler can only be started from ARM mode, so - * vPortISRStartFirstSTask() is defined in portISR.c. - */ -extern void vPortISRStartFirstTask( void ); - -/* ----------------------- Start Implementation -----------------------------*/ -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - * - * See header file for description. - */ -portSTACK_TYPE * -pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ - portSTACK_TYPE *pxOriginalTOS; - - pxOriginalTOS = pxTopOfStack; - - /* Setup the initial stack of the task. The stack is set exactly as - * expected by the portRESTORE_CONTEXT() macro. - */ - - /* First on the stack is the return address - which in this case is the - * start of the task. The offset is added to make the return address appear - * as it would within an IRQ ISR. - */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - * R0. - */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack--; - - /* The last thing onto the stack is the status register, which is set for - * system mode, with interrupts enabled. - */ - *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; - -#ifdef THUMB_INTERWORK - { - /* We want the task to start in thumb mode. */ - *pxTopOfStack |= portTHUMB_MODE_BIT; - } -#endif - - pxTopOfStack--; - - /* Some optimisation levels use the stack differently to others. This - * means the interrupt flags cannot always be stored on the stack and will - * instead be stored in a variable, which is then saved as part of the - * tasks context. - */ - *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; - - return pxTopOfStack; -} - -portBASE_TYPE -xPortStartScheduler( void ) -{ - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt( ); - - /* Start the first task. */ - vPortISRStartFirstTask( ); - - /* Should not get here! */ - return 0; -} - -void -vPortEndScheduler( void ) -{ - /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ -} - -/* - * Setup timer 3 to generate ticks at the required frequency. - */ -static void -prvSetupTimerInterrupt( void ) -{ - /* Set the watchdog up to generate a periodic tick. */ - WDG_ECITConfig( DISABLE ); - WDG_CntOnOffConfig( DISABLE ); - WDG_PeriodValueConfig( configTICK_RATE_HZ ); - - /* Setup the tick interrupt in the EIC. */ - EIC_IRQChannelPriorityConfig( WDG_IRQChannel, 1 ); - EIC_IRQChannelConfig( WDG_IRQChannel, ENABLE ); - EIC_IRQConfig( ENABLE ); - WDG_ECITConfig( ENABLE ); - - /* Start the timer - interrupts are actually disabled at this point so - it is safe to do this here. */ - WDG_CntOnOffConfig( ENABLE ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/GCC/ARM7_STR71X/portISR.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/GCC/ARM7_STR71X/portISR.c deleted file mode 100644 index c86ee488e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/GCC/ARM7_STR71X/portISR.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - FreeRTOS V4.1.1 - Copyright (C) 2003-2005 Richard Barry. - Modification for STR71X/GCC - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* ----------------------- FreeRTOS includes --------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" - -/* ----------------------- System includes ----------------------------------*/ -#include "eic.h" -#include "wdg.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define portNO_CRITICAL_NESTING \ - ( ( unsigned portLONG ) 0 ) - -/* ----------------------- Prototypes ---------------------------------------*/ - -/* ISR to handle manual context switches (from a call to taskYIELD()). */ -void vPortYieldProcessor( void ) __attribute__ ( ( interrupt( "SWI" ), naked ) ); - -/* The scheduler can only be started from ARM mode, hence the inclusion of this - * function here. - */ -void vPortISRStartFirstTask( void ); - -/* ----------------------- Global variables ---------------------------------*/ -extern const portSHORT portTimerOCRDeltaValue; -volatile unsigned portLONG ulCriticalNesting = 9999UL; - -/* ----------------------- Start implementation -----------------------------*/ - -void -vPortISRStartFirstTask( void ) -{ - /* Simply start the scheduler. This is included here as it can only be - * called from ARM mode. - */ - portRESTORE_CONTEXT( ); -} - -/* - * Called by portYIELD() or taskYIELD() to manually force a context switch. - * - * When a context switch is performed from the task level the saved task - * context is made to look as if it occurred from within the tick ISR. This - * way the same restore context function can be used when restoring the context - * saved from the ISR or that saved from a call to vPortYieldProcessor. - */ -void -vPortYieldProcessor( void ) -{ - /* Within an IRQ ISR the link register has an offset from the true return - address, but an SWI ISR does not. Add the offset manually so the same - ISR return code can be used in both cases. */ - asm volatile ( "ADD LR, LR, #4" ); - - /* Perform the context switch. First save the context of the current task. */ - portSAVE_CONTEXT( ); - - /* Find the highest priority task that is ready to run. */ - vTaskSwitchContext( ); - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT( ); -} - -/* - * The ISR used for the scheduler tick depends on whether the cooperative or - * the preemptive scheduler is being used. - */ -#if configUSE_PREEMPTION == 0 - -/* The cooperative scheduler requires a normal IRQ service routine to - * simply increment the system tick. - */ -void vPortNonPreemptiveTick( void ) __attribute__ ( ( interrupt( "IRQ" ) ) ); -void -vPortNonPreemptiveTick( void ) -{ - vTaskIncrementTick( ); - - /* Clear the interrupt in the watchdog and EIC. */ - WDG->SR = 0x0000; - /* clear current interrupt pending flag for interupt source. */ - EIC->IPR |= 1 << EIC_CurrentIRQChannelValue( ); -} - -#else - -/* The preemptive scheduler is defined as "naked" as the full context is - * saved on entry as part of the context switch. - */ -void vPortPreemptiveTick( void ) __attribute__ ( ( naked ) ); -void -vPortPreemptiveTick( void ) -{ - /* Save the context of the interrupted task. */ - portSAVE_CONTEXT( ); - - /* Increment the RTOS tick count, then look for the highest priority - * task that is ready to run. - */ - vTaskIncrementTick( ); - vTaskSwitchContext( ); - - /* Clear the interrupt in the watchdog and EIC. */ - WDG->SR = 0x0000; - /* clear current interrupt pending flag for interupt source. */ - EIC->IPR |= 1 << EIC_CurrentIRQChannelValue( ); - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT( ); -} - -#endif - - -void -vPortDisableInterrupts( void ) -{ - asm volatile ( "STMDB SP!, {R0}" ); /* Push R0. */ - asm volatile ( "MRS R0, CPSR" ); /* Get CPSR. */ - asm volatile ( "ORR R0, R0, #0xC0" ); /* Disable IRQ, FIQ. */ - asm volatile ( "MSR CPSR, R0" ); /* Write back modified value. */ - asm volatile ( "LDMIA SP!, {R0}" ); /* Pop R0. */ - asm volatile ( "BX R14" ); /* Return back to thumb. */ -} - -void -vPortEnableInterrupts( void ) -{ - asm volatile ( "STMDB SP!, {R0}" ); /* Push R0. */ - asm volatile ( "MRS R0, CPSR" ); /* Get CPSR. */ - asm volatile ( "BIC R0, R0, #0xC0" ); /* Enable IRQ, FIQ. */ - asm volatile ( "MSR CPSR, R0" ); /* Write back modified value. */ - asm volatile ( "LDMIA SP!, {R0}" ); /* Pop R0. */ - asm volatile ( "BX R14" ); /* Return back to thumb. */ -} - -/* The code generated by the GCC compiler uses the stack in different ways at - * different optimisation levels. The interrupt flags can therefore not always - * be saved to the stack. Instead the critical section nesting level is stored - * in a variable, which is then saved as part of the stack context. - */ -void -vPortEnterCritical( void ) -{ - /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ - asm volatile ( "STMDB SP!, {R0}" ); /* Push R0. */ - asm volatile ( "MRS R0, CPSR" ); /* Get CPSR. */ - asm volatile ( "ORR R0, R0, #0xC0" ); /* Disable IRQ, FIQ. */ - asm volatile ( "MSR CPSR, R0" ); /* Write back modified value. */ - asm volatile ( "LDMIA SP!, {R0}" ); /* Pop R0. */ - - /* Now interrupts are disabled ulCriticalNesting can be accessed - * directly. Increment ulCriticalNesting to keep a count of how many times - * portENTER_CRITICAL() has been called. - */ - ulCriticalNesting++; -} - -void -vPortExitCritical( void ) -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - * re-enabled. - */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - /* Enable interrupts as per portEXIT_CRITICAL(). */ - asm volatile ( "STMDB SP!, {R0}" ); /* Push R0. */ - asm volatile ( "MRS R0, CPSR" ); /* Get CPSR. */ - asm volatile ( "BIC R0, R0, #0xC0" ); /* Enable IRQ, FIQ. */ - asm volatile ( "MSR CPSR, R0" ); /* Write back modified value. */ - asm volatile ( "LDMIA SP!, {R0}" ); /* Pop R0. */ - } - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/GCC/ARM7_STR71X/portmacro.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/GCC/ARM7_STR71X/portmacro.h deleted file mode 100644 index 9b0afc32c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/GCC/ARM7_STR71X/portmacro.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - FreeRTOS V4.1.1 - Copyright (C) 2003-2005 Richard Barry. - Modification for STR71X/GCC - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/* ----------------------- Defines ------------------------------------------*/ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE portLONG - -#if( configUSE_16_BIT_TICKS == 1 ) -typedef unsigned portSHORT portTickType; - -#define portMAX_DELAY ( portTickType ) 0xffff -#else -typedef unsigned portLONG portTickType; - -#define portMAX_DELAY ( portTickType ) 0xffffffff -#endif - -/* ----------------------- Defines (Architecture) ---------------------------*/ - -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 - -/* ----------------------- Global variables ---------------------------------*/ -extern volatile unsigned portLONG ulCriticalNesting; - -/*------------------------ Defines (Scheduler) ------------------------------*/ -/* - * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR - * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but - * are included here for efficiency. An attempt to call one from - * THUMB mode code will result in a compile time error. - */ - -#define portRESTORE_CONTEXT() \ -do { \ - extern void * volatile pxCurrentTCB; \ - /* Set the LR to the task stack. */ \ - asm volatile ( "LDR R0, %0" : : "m" (pxCurrentTCB) ); \ - asm volatile ( "LDR LR, [R0]" ); \ - \ - /* The critical nesting depth is the first item on the stack. */ \ - /* Load it into the ulCriticalNesting variable. */ \ - asm volatile ( "LDR R0, =ulCriticalNesting" ); \ - asm volatile ( "LDMFD LR!, {R1}" ); \ - asm volatile ( "STR R1, [R0]" ); \ - \ - /* Get the SPSR from the stack. */ \ - asm volatile ( "LDMFD LR!, {R0}" ); \ - asm volatile ( "MSR SPSR, R0" ); \ - \ - /* Restore all system mode registers for the task. */ \ - asm volatile ( "LDMFD LR, {R0-R14}^" ); \ - asm volatile ( "NOP" ); \ - \ - /* Restore the return address. */ \ - asm volatile ( "LDR LR, [LR, #+60]" ); \ - \ - /* And return - correcting the offset in the LR to obtain the */ \ - /* correct address. */ \ - asm volatile ( "SUBS PC, LR, #4" ); \ -} while( 0 ); - -/*-----------------------------------------------------------*/ - -#define portSAVE_CONTEXT() \ -do { \ - extern void * volatile pxCurrentTCB; \ - /* Push R0 as we are going to use the register. */ \ - asm volatile ( "STMDB SP!, {R0}" ); \ - \ - /* Set R0 to point to the task stack pointer. */ \ - asm volatile ( "STMDB SP,{SP}^" ); \ - asm volatile ( "SUB SP, SP, #4" ); \ - asm volatile ( "LDMIA SP!,{R0}" ); \ - \ - /* Push the return address onto the stack. */ \ - asm volatile ( "STMDB R0!, {LR}" ); \ - \ - /* Now we have saved LR we can use it instead of R0. */ \ - asm volatile ( "MOV LR, R0" ); \ - \ - /* Pop R0 so we can save it onto the system mode stack. */ \ - asm volatile ( "LDMIA SP!, {R0}" ); \ - \ - /* Push all the system mode registers onto the task stack. */ \ - asm volatile ( "STMDB LR,{R0-LR}^"); \ - asm volatile ( "SUB LR, LR, #60" ); \ - \ - /* Push the SPSR onto the task stack. */ \ - asm volatile ( "MRS R0, SPSR" ); \ - asm volatile ( "STMDB LR!, {R0}" ); \ - \ - asm volatile ( "LDR R0, =ulCriticalNesting " ); \ - asm volatile ( "LDR R0, [R0]" ); \ - asm volatile ( "STMDB LR!, {R0}" ); \ - \ - /* Store the new top of stack for the task. */ \ - asm volatile ( "LDR R0, %0" : : "m" (pxCurrentTCB) ); \ - asm volatile ( "STR LR, [R0]" ); \ -} while( 0 ); - - -/*----------------------------------------------------------- - * ISR entry and exit macros. These are only required if a task switch - * is required from the ISR. - *----------------------------------------------------------*/ - - -#define portENTER_SWITCHING_ISR() \ - /* Save the context of the interrupted task. */ \ - portSAVE_CONTEXT(); \ - \ - /* We don't know the stack requirements for the ISR, so the frame */\ - /* pointer will be set to the top of the task stack, and the stack*/\ - /* pointer left where it is. The IRQ stack will get used for any */\ - /* functions calls made by this ISR. */ \ - asm volatile ( "SUB R11, LR, #4" ); \ - do { - -#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ - /* If a switch is required then we just need to call */ \ - /* vTaskSwitchContext() as the context has already been */ \ - /* saved. */ \ - if( SwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ - } while( 0 ); \ - /* Restore the context of which ever task is now the highest */ \ - /* priority that is ready to run. */ \ - portRESTORE_CONTEXT(); - -#define portYIELD() asm volatile ( "SWI" ); - -/* ----------------------- Prototypes ---------------------------------------*/ - -#define portDISABLE_INTERRUPTS( ) vPortDisableInterrupts() -#define portENABLE_INTERRUPTS( ) vPortEnableInterrupts() - -extern void vPortDisableInterrupts( void ) __attribute__ ( ( naked ) ); -extern void vPortEnableInterrupts( void ) __attribute__ ( ( naked ) ); -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); - -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) \ - void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) \ - void vFunction( void *pvParameters ) - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/MemMang/heap_1.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/MemMang/heap_1.c deleted file mode 100644 index bfbc063ef..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/MemMang/heap_1.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - FreeRTOS.org V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - -Changes between V2.5.1 and V2.5.1 - - + The memory pool has been defined within a struct to ensure correct memory - alignment on 32bit systems. - -Changes between V2.6.1 and V3.0.0 - - + An overflow check has been added to ensure the next free byte variable - does not wrap around. -*/ - - -/* - * The simplest possible implementation of pvPortMalloc(). Note that this - * implementation does NOT allow allocated memory to be freed again. - * - * See heap_2.c and heap_3.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ -#include -#include "FreeRTOS.h" -#include "task.h" - -/* Setup the correct byte alignment mask for the defined byte alignment. */ -#if portBYTE_ALIGNMENT == 4 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) -#endif - -#if portBYTE_ALIGNMENT == 2 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) -#endif - -#if portBYTE_ALIGNMENT == 1 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) -#endif - -#ifndef heapBYTE_ALIGNMENT_MASK - #error "Invalid portBYTE_ALIGNMENT definition" -#endif - -/* Allocate the memory for the heap. The struct is used to force byte -alignment without using any non-portable code. */ -static struct xRTOS_HEAP -{ - unsigned portLONG ulDummy; - unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; -} xHeap; - -static size_t xNextFreeByte = ( size_t ) 0; -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -void *pvReturn = NULL; - - /* Ensure that blocks are always aligned to the required number of bytes. */ - #if portBYTE_ALIGNMENT != 1 - if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) - { - /* Byte alignment required. */ - xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); - } - #endif - - vTaskSuspendAll(); - { - /* Check there is enough room left for the allocation. */ - if( ( ( xNextFreeByte + xWantedSize ) < configTOTAL_HEAP_SIZE ) && - ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) )/* Check for overflow. */ - { - /* Return the next free byte then increment the index past this - block. */ - pvReturn = &( xHeap.ucHeap[ xNextFreeByte ] ); - xNextFreeByte += xWantedSize; - } - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ - /* Memory cannot be freed using this scheme. See heap_2.c and heap_3.c - for alternative implementations, and the memory management pages of - http://www.FreeRTOS.org for more information. */ - ( void ) pv; -} -/*-----------------------------------------------------------*/ - -void vPortInitialiseBlocks( void ) -{ - /* Only required when static memory is not cleared. */ - xNextFreeByte = ( size_t ) 0; -} - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/MemMang/heap_2.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/MemMang/heap_2.c deleted file mode 100644 index 2b258b127..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/MemMang/heap_2.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - FreeRTOS.org V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * A sample implementation of pvPortMalloc() and vPortFree() that permits - * allocated blocks to be freed, but does not combine adjacent free blocks - * into a single larger block. - * - * See heap_1.c and heap_3.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ -#include - -#include "FreeRTOS.h" -#include "task.h" - -/* Setup the correct byte alignment mask for the defined byte alignment. */ -#if portBYTE_ALIGNMENT == 4 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) -#endif - -#if portBYTE_ALIGNMENT == 2 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) -#endif - -#if portBYTE_ALIGNMENT == 1 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) -#endif - -#ifndef heapBYTE_ALIGNMENT_MASK - #error "Invalid portBYTE_ALIGNMENT definition" -#endif - -/* Allocate the memory for the heap. The struct is used to force byte -alignment without using any non-portable code. */ -static struct xRTOS_HEAP -{ - unsigned portLONG ulDummy; - unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; -} xHeap; - -/* Define the linked list structure. This is used to link free blocks in order -of their size. */ -typedef struct A_BLOCK_LINK -{ - struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */ - size_t xBlockSize; /*<< The size of the free block. */ -} xBlockLink; - - -static const unsigned portSHORT heapSTRUCT_SIZE = ( sizeof( xBlockLink ) + ( sizeof( xBlockLink ) % portBYTE_ALIGNMENT ) ); -#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) ) - -/* Create a couple of list links to mark the start and end of the list. */ -static xBlockLink xStart, xEnd; - -/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */ - -/* - * Insert a block into the list of free blocks - which is ordered by size of - * the block. Small blocks at the start of the list and large blocks at the end - * of the list. - */ -#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \ -{ \ -xBlockLink *pxIterator; \ -size_t xBlockSize; \ - \ - xBlockSize = pxBlockToInsert->xBlockSize; \ - \ - /* Iterate through the list until a block is found that has a larger size */ \ - /* than the block we are inserting. */ \ - for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \ - { \ - /* There is nothing to do here - just iterate to the correct position. */ \ - } \ - \ - /* Update the list to include the block being inserted in the correct */ \ - /* position. */ \ - pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \ - pxIterator->pxNextFreeBlock = pxBlockToInsert; \ -} -/*-----------------------------------------------------------*/ - -#define prvHeapInit() \ -{ \ -xBlockLink *pxFirstFreeBlock; \ - \ - /* xStart is used to hold a pointer to the first item in the list of free */ \ - /* blocks. The void cast is used to prevent compiler warnings. */ \ - xStart.pxNextFreeBlock = ( void * ) xHeap.ucHeap; \ - xStart.xBlockSize = ( size_t ) 0; \ - \ - /* xEnd is used to mark the end of the list of free blocks. */ \ - xEnd.xBlockSize = configTOTAL_HEAP_SIZE; \ - xEnd.pxNextFreeBlock = NULL; \ - \ - /* To start with there is a single free block that is sized to take up the \ - entire heap space. */ \ - pxFirstFreeBlock = ( void * ) xHeap.ucHeap; \ - pxFirstFreeBlock->xBlockSize = configTOTAL_HEAP_SIZE; \ - pxFirstFreeBlock->pxNextFreeBlock = &xEnd; \ -} -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -xBlockLink *pxBlock, *pxPreviousBlock, *pxNewBlockLink; -static portBASE_TYPE xHeapHasBeenInitialised = pdFALSE; -void *pvReturn = NULL; - - vTaskSuspendAll(); - { - /* If this is the first call to malloc then the heap will require - initialisation to setup the list of free blocks. */ - if( xHeapHasBeenInitialised == pdFALSE ) - { - prvHeapInit(); - xHeapHasBeenInitialised = pdTRUE; - } - - /* The wanted size is increased so it can contain a xBlockLink - structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) - { - xWantedSize += heapSTRUCT_SIZE; - - /* Ensure that blocks are always aligned to the required number of bytes. */ - if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) - { - /* Byte alignment required. */ - xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); - } - } - - if( ( xWantedSize > 0 ) && ( xWantedSize < configTOTAL_HEAP_SIZE ) ) - { - /* Blocks are stored in byte order - traverse the list from the start - (smallest) block until one of adequate size is found. */ - pxPreviousBlock = &xStart; - pxBlock = xStart.pxNextFreeBlock; - while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock ) ) - { - pxPreviousBlock = pxBlock; - pxBlock = pxBlock->pxNextFreeBlock; - } - - /* If we found the end marker then a block of adequate size was not found. */ - if( pxBlock != &xEnd ) - { - /* Return the memory space - jumping over the xBlockLink structure - at its start. */ - pvReturn = ( void * ) ( ( ( unsigned portCHAR * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE ); - - /* This block is being returned for use so must be taken our of the - list of free blocks. */ - pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; - - /* If the block is larger than required it can be split into two. */ - if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) - { - /* This block is to be split into two. Create a new block - following the number of bytes requested. The void cast is - used to prevent byte alignment warnings from the compiler. */ - pxNewBlockLink = ( void * ) ( ( ( unsigned portCHAR * ) pxBlock ) + xWantedSize ); - - /* Calculate the sizes of two blocks split from the single - block. */ - pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; - pxBlock->xBlockSize = xWantedSize; - - /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); - } - } - } - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ -unsigned portCHAR *puc = ( unsigned portCHAR * ) pv; -xBlockLink *pxLink; - - if( pv ) - { - /* The memory being freed will have an xBlockLink structure immediately - before it. */ - puc -= heapSTRUCT_SIZE; - - /* This casting is to keep the compiler from issuing warnings. */ - pxLink = ( void * ) puc; - - vTaskSuspendAll(); - { - /* Add this block to the list of free blocks. */ - prvInsertBlockIntoFreeList( ( ( xBlockLink * ) pxLink ) ); - } - xTaskResumeAll(); - } -} -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/MemMang/heap_3.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/MemMang/heap_3.c deleted file mode 100644 index 180c3e626..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/portable/MemMang/heap_3.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - FreeRTOS.org V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * Implementation of pvPortMalloc() and vPortFree() that relies on the - * compilers own malloc() and free() implementations. - * - * This file can only be used if the linker is configured to to generate - * a heap memory area. - * - * See heap_2.c and heap_1.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ - -#include - -#include "FreeRTOS.h" -#include "task.h" - -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -void *pvReturn; - - vTaskSuspendAll(); - { - pvReturn = malloc( xWantedSize ); - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ - if( pv ) - { - vTaskSuspendAll(); - { - free( pv ); - } - xTaskResumeAll(); - } -} - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/queue.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/queue.c deleted file mode 100644 index 7ed6363d8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/queue.c +++ /dev/null @@ -1,882 +0,0 @@ -/* - FreeRTOS.org V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.01 - - + More use of 8bit data types. - + Function name prefixes changed where the data type returned has changed. - -Changed from V2.0.0 - - + Added the queue locking mechanism and make more use of the scheduler - suspension feature to minimise the time interrupts have to be disabled - when accessing a queue. - -Changed from V2.2.0 - - + Explicit use of 'signed' qualifier on portCHAR types added. - -Changes from V3.0.0 - - + API changes as described on the FreeRTOS.org WEB site. - -Changes from V3.2.3 - - + Added the queue functions that can be used from co-routines. - -Changes from V4.0.5 - - + Added a loop within xQueueSend() and xQueueReceive() to prevent the - functions exiting when a block time remains and the function has - not completed. - -*/ - -#include -#include -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/*----------------------------------------------------------- - * PUBLIC LIST API documented in list.h - *----------------------------------------------------------*/ - -/* Constants used with the cRxLock and cTxLock structure members. */ -#define queueUNLOCKED ( ( signed portBASE_TYPE ) -1 ) -#define queueERRONEOUS_UNBLOCK ( -1 ) - -/* - * Definition of the queue used by the scheduler. - * Items are queued by copy, not reference. - */ -typedef struct QueueDefinition -{ - signed portCHAR *pcHead; /*< Points to the beginning of the queue storage area. */ - signed portCHAR *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */ - - signed portCHAR *pcWriteTo; /*< Points to the free next place in the storage area. */ - signed portCHAR *pcReadFrom; /*< Points to the last place that a queued item was read from. */ - - xList xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */ - xList xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */ - - unsigned portBASE_TYPE uxMessagesWaiting;/*< The number of items currently in the queue. */ - unsigned portBASE_TYPE uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */ - unsigned portBASE_TYPE uxItemSize; /*< The size of each items that the queue will hold. */ - - signed portBASE_TYPE xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ - signed portBASE_TYPE xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ -} xQUEUE; -/*-----------------------------------------------------------*/ - -/* - * Inside this file xQueueHandle is a pointer to a xQUEUE structure. - * To keep the definition private the API header file defines it as a - * pointer to void. - */ -typedef xQUEUE * xQueueHandle; - -/* - * Prototypes for public functions are included here so we don't have to - * include the API header file (as it defines xQueueHandle differently). These - * functions are documented in the API header file. - */ -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); -signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue ); -void vQueueDelete( xQueueHandle xQueue ); -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ); -signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - -#if configUSE_CO_ROUTINES == 1 - signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ); - signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ); - signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); -#endif - -/* - * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not - * prevent an ISR from adding or removing items to the queue, but does prevent - * an ISR from removing tasks from the queue event lists. If an ISR finds a - * queue is locked it will instead increment the appropriate queue lock count - * to indicate that a task may require unblocking. When the queue in unlocked - * these lock counts are inspected, and the appropriate action taken. - */ -static void prvUnlockQueue( xQueueHandle pxQueue ); - -/* - * Uses a critical section to determine if there is any data in a queue. - * - * @return pdTRUE if the queue contains no items, otherwise pdFALSE. - */ -static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ); - -/* - * Uses a critical section to determine if there is any space in a queue. - * - * @return pdTRUE if there is no space, otherwise pdFALSE; - */ -static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ); - -/* - * Macro that copies an item into the queue. This is done by copying the item - * byte for byte, not by reference. Updates the queue state to ensure it's - * integrity after the copy. - */ -#define prvCopyQueueData( pxQueue, pvItemToQueue ) \ -{ \ - memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize ); \ - ++( pxQueue->uxMessagesWaiting ); \ - pxQueue->pcWriteTo += pxQueue->uxItemSize; \ - if( pxQueue->pcWriteTo >= pxQueue->pcTail ) \ - { \ - pxQueue->pcWriteTo = pxQueue->pcHead; \ - } \ -} -/*-----------------------------------------------------------*/ - -/* - * Macro to mark a queue as locked. Locking a queue prevents an ISR from - * accessing the queue event lists. - */ -#define prvLockQueue( pxQueue ) \ -{ \ - taskENTER_CRITICAL(); \ - ++( pxQueue->xRxLock ); \ - ++( pxQueue->xTxLock ); \ - taskEXIT_CRITICAL(); \ -} -/*-----------------------------------------------------------*/ - - -/*----------------------------------------------------------- - * PUBLIC QUEUE MANAGEMENT API documented in queue.h - *----------------------------------------------------------*/ - -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ) -{ -xQUEUE *pxNewQueue; -size_t xQueueSizeInBytes; - - /* Allocate the new queue structure. */ - if( uxQueueLength > ( unsigned portBASE_TYPE ) 0 ) - { - pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) ); - if( pxNewQueue != NULL ) - { - /* Create the list of pointers to queue items. The queue is one byte - longer than asked for to make wrap checking easier/faster. */ - xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1; - - pxNewQueue->pcHead = ( signed portCHAR * ) pvPortMalloc( xQueueSizeInBytes ); - if( pxNewQueue->pcHead != NULL ) - { - /* Initialise the queue members as described above where the - queue type is defined. */ - pxNewQueue->pcTail = pxNewQueue->pcHead + ( uxQueueLength * uxItemSize ); - pxNewQueue->uxMessagesWaiting = 0; - pxNewQueue->pcWriteTo = pxNewQueue->pcHead; - pxNewQueue->pcReadFrom = pxNewQueue->pcHead + ( ( uxQueueLength - 1 ) * uxItemSize ); - pxNewQueue->uxLength = uxQueueLength; - pxNewQueue->uxItemSize = uxItemSize; - pxNewQueue->xRxLock = queueUNLOCKED; - pxNewQueue->xTxLock = queueUNLOCKED; - - /* Likewise ensure the event queues start with the correct state. */ - vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) ); - vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) ); - - return pxNewQueue; - } - else - { - vPortFree( pxNewQueue ); - } - } - } - - /* Will only reach here if we could not allocate enough memory or no memory - was required. */ - return NULL; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; -xTimeOutType xTimeOut; - - /* Make sure other tasks do not access the queue. */ - vTaskSuspendAll(); - - /* Capture the current time status for future reference. */ - vTaskSetTimeOutState( &xTimeOut ); - - /* It is important that this is the only thread/ISR that modifies the - ready or delayed lists until xTaskResumeAll() is called. Places where - the ready/delayed lists are modified include: - - + vTaskDelay() - Nothing can call vTaskDelay as the scheduler is - suspended, vTaskDelay() cannot be called from an ISR. - + vTaskPrioritySet() - Has a critical section around the access. - + vTaskSwitchContext() - This will not get executed while the scheduler - is suspended. - + prvCheckDelayedTasks() - This will not get executed while the - scheduler is suspended. - + xTaskCreate() - Has a critical section around the access. - + vTaskResume() - Has a critical section around the access. - + xTaskResumeAll() - Has a critical section around the access. - + xTaskRemoveFromEventList - Checks to see if the scheduler is - suspended. If so then the TCB being removed from the event is - removed from the event and added to the xPendingReadyList. - */ - - /* Make sure interrupts do not access the queue event list. */ - prvLockQueue( pxQueue ); - - /* It is important that interrupts to not access the event list of the - queue being modified here. Places where the event list is modified - include: - - + xQueueSendFromISR(). This checks the lock on the queue to see if - it has access. If the queue is locked then the Tx lock count is - incremented to signify that a task waiting for data can be made ready - once the queue lock is removed. If the queue is not locked then - a task can be moved from the event list, but will not be removed - from the delayed list or placed in the ready list until the scheduler - is unlocked. - - + xQueueReceiveFromISR(). As per xQueueSendFromISR(). - */ - - /* If the queue is already full we may have to block. */ - do - { - if( prvIsQueueFull( pxQueue ) ) - { - /* The queue is full - do we want to block or just leave without - posting? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* We are going to place ourselves on the xTasksWaitingToSend event - list, and will get woken should the delay expire, or space become - available on the queue. - - As detailed above we do not require mutual exclusion on the event - list as nothing else can modify it or the ready lists while we - have the scheduler suspended and queue locked. - - It is possible that an ISR has removed data from the queue since we - checked if any was available. If this is the case then the data - will have been copied from the queue, and the queue variables - updated, but the event list will not yet have been checked to see if - anything is waiting as the queue is locked. */ - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); - - /* Force a context switch now as we are blocked. We can do - this from within a critical section as the task we are - switching to has its own context. When we return here (i.e. we - unblock) we will leave the critical section as normal. - - It is possible that an ISR has caused an event on an unrelated and - unlocked queue. If this was the case then the event list for that - queue will have been updated but the ready lists left unchanged - - instead the readied task will have been added to the pending ready - list. */ - taskENTER_CRITICAL(); - { - /* We can safely unlock the queue and scheduler here as - interrupts are disabled. We must not yield with anything - locked, but we can yield from within a critical section. - - Tasks that have been placed on the pending ready list cannot - be tasks that are waiting for events on this queue. See - in comment xTaskRemoveFromEventList(). */ - prvUnlockQueue( pxQueue ); - - /* Resuming the scheduler may cause a yield. If so then there - is no point yielding again here. */ - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - - /* Before leaving the critical section we have to ensure - exclusive access again. */ - vTaskSuspendAll(); - prvLockQueue( pxQueue ); - } - taskEXIT_CRITICAL(); - } - } - - /* When we are here it is possible that we unblocked as space became - available on the queue. It is also possible that an ISR posted to the - queue since we left the critical section, so it may be that again there - is no space. This would only happen if a task and ISR post onto the - same queue. */ - taskENTER_CRITICAL(); - { - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - /* There is room in the queue, copy the data into the queue. */ - prvCopyQueueData( pxQueue, pvItemToQueue ); - xReturn = pdPASS; - - /* Update the TxLock count so prvUnlockQueue knows to check for - tasks waiting for data to become available in the queue. */ - ++( pxQueue->xTxLock ); - } - else - { - xReturn = errQUEUE_FULL; - } - } - taskEXIT_CRITICAL(); - - if( xReturn == errQUEUE_FULL ) - { - if( xTicksToWait > 0 ) - { - if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) - { - xReturn = queueERRONEOUS_UNBLOCK; - } - } - } - } - while( xReturn == queueERRONEOUS_UNBLOCK ); - - prvUnlockQueue( pxQueue ); - xTaskResumeAll(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ) -{ - /* Similar to xQueueSend, except we don't block if there is no room in the - queue. Also we don't directly wake a task that was blocked on a queue - read, instead we return a flag to say whether a context switch is required - or not (i.e. has a task with a higher priority than us been woken by this - post). */ - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - prvCopyQueueData( pxQueue, pvItemToQueue ); - - /* If the queue is locked we do not alter the event list. This will - be done when the queue is unlocked later. */ - if( pxQueue->xTxLock == queueUNLOCKED ) - { - /* We only want to wake one task per ISR, so check that a task has - not already been woken. */ - if( !xTaskPreviouslyWoken ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority so record that a - context switch is required. */ - return pdTRUE; - } - } - } - } - else - { - /* Increment the lock count so the task that unlocks the queue - knows that data was posted while it was locked. */ - ++( pxQueue->xTxLock ); - } - } - - return xTaskPreviouslyWoken; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; -xTimeOutType xTimeOut; - - /* This function is very similar to xQueueSend(). See comments within - xQueueSend() for a more detailed explanation. - - Make sure other tasks do not access the queue. */ - vTaskSuspendAll(); - - /* Capture the current time status for future reference. */ - vTaskSetTimeOutState( &xTimeOut ); - - /* Make sure interrupts do not access the queue. */ - prvLockQueue( pxQueue ); - - do - { - /* If there are no messages in the queue we may have to block. */ - if( prvIsQueueEmpty( pxQueue ) ) - { - /* There are no messages in the queue, do we want to block or just - leave with nothing? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); - taskENTER_CRITICAL(); - { - prvUnlockQueue( pxQueue ); - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - - vTaskSuspendAll(); - prvLockQueue( pxQueue ); - } - taskEXIT_CRITICAL(); - } - } - - taskENTER_CRITICAL(); - { - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - /* Increment the lock count so prvUnlockQueue knows to check for - tasks waiting for space to become available on the queue. */ - ++( pxQueue->xRxLock ); - xReturn = pdPASS; - } - else - { - xReturn = errQUEUE_EMPTY; - } - } - taskEXIT_CRITICAL(); - - if( xReturn == errQUEUE_EMPTY ) - { - if( xTicksToWait > 0 ) - { - if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) - { - xReturn = queueERRONEOUS_UNBLOCK; - } - } - } - } while( xReturn == queueERRONEOUS_UNBLOCK ); - - /* We no longer require exclusive access to the queue. */ - prvUnlockQueue( pxQueue ); - xTaskResumeAll(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ) -{ -signed portBASE_TYPE xReturn; - - /* We cannot block from an ISR, so check there is data available. */ - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Copy the data from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - /* If the queue is locked we will not modify the event list. Instead - we update the lock count so the task that unlocks the queue will know - that an ISR has removed data while the queue was locked. */ - if( pxQueue->xRxLock == queueUNLOCKED ) - { - /* We only want to wake one task per ISR, so check that a task has - not already been woken. */ - if( !( *pxTaskWoken ) ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - /* The task waiting has a higher priority than us so - force a context switch. */ - *pxTaskWoken = pdTRUE; - } - } - } - } - else - { - /* Increment the lock count so the task that unlocks the queue - knows that data was removed while it was locked. */ - ++( pxQueue->xRxLock ); - } - - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue ) -{ -unsigned portBASE_TYPE uxReturn; - - taskENTER_CRITICAL(); - uxReturn = pxQueue->uxMessagesWaiting; - taskEXIT_CRITICAL(); - - return uxReturn; -} -/*-----------------------------------------------------------*/ - -void vQueueDelete( xQueueHandle pxQueue ) -{ - vPortFree( pxQueue->pcHead ); - vPortFree( pxQueue ); -} -/*-----------------------------------------------------------*/ - -static void prvUnlockQueue( xQueueHandle pxQueue ) -{ - /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */ - - /* The lock counts contains the number of extra data items placed or - removed from the queue while the queue was locked. When a queue is - locked items can be added or removed, but the event lists cannot be - updated. */ - taskENTER_CRITICAL(); - { - --( pxQueue->xTxLock ); - - /* See if data was added to the queue while it was locked. */ - if( pxQueue->xTxLock > queueUNLOCKED ) - { - pxQueue->xTxLock = queueUNLOCKED; - - /* Data was posted while the queue was locked. Are any tasks - blocked waiting for data to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - /* Tasks that are removed from the event list will get added to - the pending ready list as the scheduler is still suspended. */ - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority so record that a - context switch is required. */ - vTaskMissedYield(); - } - } - } - } - taskEXIT_CRITICAL(); - - /* Do the same for the Rx lock. */ - taskENTER_CRITICAL(); - { - --( pxQueue->xRxLock ); - - if( pxQueue->xRxLock > queueUNLOCKED ) - { - pxQueue->xRxLock = queueUNLOCKED; - - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - vTaskMissedYield(); - } - } - } - } - taskEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - taskENTER_CRITICAL(); - xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ); - taskEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - taskENTER_CRITICAL(); - xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength ); - taskEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* If the queue is already full we may have to block. A critical section - is required to prevent an interrupt removing something from the queue - between the check to see if the queue is full and blocking on the queue. */ - portDISABLE_INTERRUPTS(); - { - if( prvIsQueueFull( pxQueue ) ) - { - /* The queue is full - do we want to block or just leave without - posting? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* As this is called from a coroutine we cannot block directly, but - return indicating that we need to block. */ - vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) ); - portENABLE_INTERRUPTS(); - return errQUEUE_BLOCKED; - } - else - { - portENABLE_INTERRUPTS(); - return errQUEUE_FULL; - } - } - } - portENABLE_INTERRUPTS(); - - portNOP(); - - portDISABLE_INTERRUPTS(); - { - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - /* There is room in the queue, copy the data into the queue. */ - prvCopyQueueData( pxQueue, pvItemToQueue ); - xReturn = pdPASS; - - /* Were any co-routines waiting for data to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - /* In this instance the co-routine could be placed directly - into the ready list as we are within a critical section. - Instead the same pending ready list mechansim is used as if - the event were caused from within an interrupt. */ - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The co-routine waiting has a higher priority so record - that a yield might be appropriate. */ - xReturn = errQUEUE_YIELD; - } - } - } - else - { - xReturn = errQUEUE_FULL; - } - } - portENABLE_INTERRUPTS(); - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* If the queue is already empty we may have to block. A critical section - is required to prevent an interrupt adding something to the queue - between the check to see if the queue is empty and blocking on the queue. */ - portDISABLE_INTERRUPTS(); - { - if( prvIsQueueEmpty( pxQueue ) ) - { - /* There are no messages in the queue, do we want to block or just - leave with nothing? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* As this is a co-routine we cannot block directly, but return - indicating that we need to block. */ - vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) ); - portENABLE_INTERRUPTS(); - return errQUEUE_BLOCKED; - } - else - { - portENABLE_INTERRUPTS(); - return errQUEUE_FULL; - } - } - } - portENABLE_INTERRUPTS(); - - portNOP(); - - portDISABLE_INTERRUPTS(); - { - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Data is available from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - xReturn = pdPASS; - - /* Were any co-routines waiting for space to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - /* In this instance the co-routine could be placed directly - into the ready list as we are within a critical section. - Instead the same pending ready list mechansim is used as if - the event were caused from within an interrupt. */ - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - xReturn = errQUEUE_YIELD; - } - } - } - else - { - xReturn = pdFAIL; - } - } - portENABLE_INTERRUPTS(); - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - - - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ) -{ - /* Cannot block within an ISR so if there is no space on the queue then - exit without doing anything. */ - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - prvCopyQueueData( pxQueue, pvItemToQueue ); - - /* We only want to wake one co-routine per ISR, so check that a - co-routine has not already been woken. */ - if( !xCoRoutinePreviouslyWoken ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - return pdTRUE; - } - } - } - } - - return xCoRoutinePreviouslyWoken; -} -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxCoRoutineWoken ) -{ -signed portBASE_TYPE xReturn; - - /* We cannot block from an ISR, so check there is data available. If - not then just leave without doing anything. */ - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Copy the data from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - if( !( *pxCoRoutineWoken ) ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - *pxCoRoutineWoken = pdTRUE; - } - } - } - - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/tasks.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/tasks.c deleted file mode 100644 index 31a39eaf5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/freertos/tasks.c +++ /dev/null @@ -1,1814 +0,0 @@ -/* - FreeRTOS.org V4.1.1 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.00: - - + Call to portRESTORE_CONTEXT has been removed. The first context - switch is now performed within sPortStartScheduler(). - -Changes from V1.01: - - + More use of 8bit data types. - + Function name prefixes changed where the data type returned has changed. - + configUSE_TRACE_FACILITY is no longer defined by default. - -Changes from V1.2.0 - - + Introduced ucTopReadyPriority. This tracks the highest priority ready - queue that contains a valid TCB and thus makes the context switch - slightly faster. - - + prvAddTaskToReadyQueue() has been made a macro. - -Changes from V1.2.6 - - + Added conditional compilation directives. - + Extended API. - + Rearranged function order. - + Creating a task now causes a context switch if the task being created - has a higher priority than the calling task - assuming the kernel is - running. - + vTaskDelete() now only causes a context switch if the calling task is - the task being deleted. - -Changes from V2.0.0 - - + Allow the type of the tick count to be 16 or 32 bits. - + Introduce xPendingReadyList feature to allow the time interrupts have to - be disabled to be minimised. - + Remove the #if( INCLUDE_vTaskSuspendAll ) statements. vTaskSuspendAll() - is now always included as it is used by the scheduler itself. - -Changes from V2.1.0 - - + Bug fix - pxCurrentTCB is now initialised before the call to - prvInitializeTaskLists(). Previously pxCurrentTCB could be accessed - while null. - -Changed from V2.1.1 - - + Change to where lStackSize is declared within sTaskCreate() to prevent - compiler warnings with 8051 port. - -Changes from V2.2.0 - - + Explicit use of 'signed' qualifier on portCHAR types added. - + Changed odd calculation of initial pxTopOfStack value when - portSTACK_GROWTH < 0. - + Removed pcVersionNumber definition. - -Changes from V2.5.3 - - + cTaskResumeAll() modified to ensure it can be called prior to the task - lists being initialised. - -Changes from V2.5.5 - - + Added API function vTaskDelayUntil(). - + Added INCLUDE_vTaskDelay conditional compilation. - -Changes from V2.6.0 - - + Updated the vWriteTraceToBuffer macro to always be 4 byte aligned so it - can be used on ARM architectures. - + tskMAX_TASK_NAME_LEN definition replaced with the port specific - configMAX_TASK_NAME_LEN definition. - + Removed the call to strcpy when copying across the task name into the - TCB. - + Added ucTasksDeleted variable to prevent vTaskSuspendAll() being called - too often in the idle task. - -Changes between V3.0.0 and V2.6.1 - - + When resuming the scheduler a yield is performed if either a tick has - been missed, or a task is moved from the pending ready list into a ready - list. Previously a yield was not performed on this second condition. - + Introduced the type portBASE_TYPE. This necessitates several API - changes. - + Removed the sUsingPreemption variable. The constant defined in - portmacro.h is now used directly. - + The idle task can now include an optional hook function - and no longer - completes its time slice if other tasks with equal priority to it are - ready to run. - + See the FreeRTOS.org documentation for more information on V2.x.x to - V3.x.x modifications. - -Changes from V3.1.1 - - + Modified vTaskPrioritySet() and vTaskResume() to allow these functions to - be called while the scheduler is suspended. - + Corrected the task ordering within event lists. - -Changes from V3.2.0 - - + Added function xTaskGetCurrentTaskHandle(). - -Changes from V3.2.4 - - + Changed the volatile declarations on some variables to reflect the - changes to the list definitions. - + Changed the order of the TCB definition so there is commonality between - the task control block and a co-routine control block. - + Allow the scheduler to be started even if no tasks other than the idle - task has been created. This allows co-routines to run even when no tasks - have been created. - + The need for a context switch is now signalled if a task woken by an - event has a priority greater or equal to the currently running task. - Previously this was only greater than. - -Changes from V4.0.0 - - + Added the xMissedYield handling. - -Changes from V4.0.1 - - + The function vTaskList() now suspends the scheduler rather than disabling - interrupts during the creation of the task list. - + Allow a task to delete itself by passing in its own handle. Previously - this could only be done by passing in NULL. - + The tick hook function is now called only within a tick isr. Previously - it was also called when the tick function was called during the scheduler - unlocking process. - -Changes from V4.0.3 - - + Extra checks have been placed in vTaskPrioritySet() to avoid unnecessary - yields. - -Changed from V4.0.4 - - + Bug fix: The 'value' of the event list item is updated when the priority - of a task is changed. Previously only the priority of the TCB itself was - changed. - + When resuming a task a check is first made to see if the task is actually - suspended. - + vTaskPrioritySet() and vTaskResume() no longer use the event list item. - This has not been necessary since V4.0.1 when the xMissedYield handling - was added. - + Implement xTaskResumeFromISR(). - -Changes from V4.0.5 - - + Added utility functions and xOverflowCount variable to facilitate the - queue.c changes. -*/ - -#include -#include -#include - -#include "FreeRTOS.h" -#include "task.h" - -/* - * Macro to define the amount of stack available to the idle task. - */ -#define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE - - -/* - * Default a definitions for backwards compatibility with old - * portmacro.h files. - */ -#ifndef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 16 -#endif - -#ifndef INCLUDE_xTaskGetCurrentTaskHandle - #define INCLUDE_xTaskGetCurrentTaskHandle 0 -#endif - -#ifndef configIDLE_SHOULD_YIELD - #define configIDLE_SHOULD_YIELD 1 -#endif - -#if configMAX_TASK_NAME_LEN < 1 - #undef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 1 -#endif - -#ifndef INCLUDE_xTaskResumeFromISR - #define INCLUDE_xTaskResumeFromISR 1 -#endif - -/* - * Task control block. A task control block (TCB) is allocated to each task, - * and stores the context of the task. - */ -typedef struct tskTaskControlBlock -{ - volatile portSTACK_TYPE *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE STRUCT. */ - xListItem xGenericListItem; /*< List item used to place the TCB in ready and blocked queues. */ - xListItem xEventListItem; /*< List item used to place the TCB in event lists. */ - unsigned portBASE_TYPE uxPriority; /*< The priority of the task where 0 is the lowest priority. */ - portSTACK_TYPE *pxStack; /*< Points to the start of the stack. */ - unsigned portBASE_TYPE uxTCBNumber; /*< This is used for tracing the scheduler and making debugging easier only. */ - signed portCHAR pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */ - unsigned portSHORT usStackDepth; /*< Total depth of the stack (when empty). This is defined as the number of variables the stack can hold, not the number of bytes. */ -} tskTCB; - -/*lint -e956 */ - -tskTCB * volatile pxCurrentTCB = NULL; - -/* Lists for ready and blocked tasks. --------------------*/ - -static xList pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */ -static xList xDelayedTaskList1; /*< Delayed tasks. */ -static xList xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */ -static xList * volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */ -static xList * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */ -static xList xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready queue when the scheduler is resumed. */ - -#if ( INCLUDE_vTaskDelete == 1 ) - - static volatile xList xTasksWaitingTermination; /*< Tasks that have been deleted - but the their memory not yet freed. */ - static volatile unsigned portBASE_TYPE uxTasksDeleted = ( unsigned portBASE_TYPE ) 0; - -#endif - -#if ( INCLUDE_vTaskSuspend == 1 ) - - static xList xSuspendedTaskList; /*< Tasks that are currently suspended. */ - -#endif - -/* File private variables. --------------------------------*/ -static volatile unsigned portBASE_TYPE uxCurrentNumberOfTasks = ( unsigned portBASE_TYPE ) 0; -static volatile portTickType xTickCount = ( portTickType ) 0; -static unsigned portBASE_TYPE uxTopUsedPriority = tskIDLE_PRIORITY; -static volatile unsigned portBASE_TYPE uxTopReadyPriority = tskIDLE_PRIORITY; -static volatile signed portBASE_TYPE xSchedulerRunning = pdFALSE; -static volatile unsigned portBASE_TYPE uxSchedulerSuspended = ( unsigned portBASE_TYPE ) pdFALSE; -static volatile unsigned portBASE_TYPE uxMissedTicks = ( unsigned portBASE_TYPE ) 0; -static volatile portBASE_TYPE xMissedYield = ( portBASE_TYPE ) pdFALSE; -static volatile portBASE_TYPE xNumOfOverflows = ( portBASE_TYPE ) 0; -/* Debugging and trace facilities private variables and macros. ------------*/ - -/* - * The value used to fill the stack of a task when the task is created. This - * is used purely for checking the high water mark for tasks. - */ -#define tskSTACK_FILL_BYTE ( 0xa5 ) - -/* - * Macros used by vListTask to indicate which state a task is in. - */ -#define tskBLOCKED_CHAR ( ( signed portCHAR ) 'B' ) -#define tskREADY_CHAR ( ( signed portCHAR ) 'R' ) -#define tskDELETED_CHAR ( ( signed portCHAR ) 'D' ) -#define tskSUSPENDED_CHAR ( ( signed portCHAR ) 'S' ) - -/* - * Macros and private variables used by the trace facility. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - #define tskSIZE_OF_EACH_TRACE_LINE ( ( unsigned portLONG ) ( sizeof( unsigned portLONG ) + sizeof( unsigned portLONG ) ) ) - static volatile signed portCHAR * volatile pcTraceBuffer; - static signed portCHAR *pcTraceBufferStart; - static signed portCHAR *pcTraceBufferEnd; - static signed portBASE_TYPE xTracing = pdFALSE; - -#endif - -/* - * Macro that writes a trace of scheduler activity to a buffer. This trace - * shows which task is running when and is very useful as a debugging tool. - * As this macro is called each context switch it is a good idea to undefine - * it if not using the facility. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - #define vWriteTraceToBuffer() \ - { \ - if( xTracing ) \ - { \ - static unsigned portBASE_TYPE uxPreviousTask = 255; \ - \ - if( uxPreviousTask != pxCurrentTCB->uxTCBNumber ) \ - { \ - if( ( pcTraceBuffer + tskSIZE_OF_EACH_TRACE_LINE ) < pcTraceBufferEnd ) \ - { \ - uxPreviousTask = pxCurrentTCB->uxTCBNumber; \ - *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) xTickCount; \ - pcTraceBuffer += sizeof( unsigned portLONG ); \ - *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) uxPreviousTask; \ - pcTraceBuffer += sizeof( unsigned portLONG ); \ - } \ - else \ - { \ - xTracing = pdFALSE; \ - } \ - } \ - } \ - } - -#else - - #define vWriteTraceToBuffer() - -#endif - - -/* - * Place the task represented by pxTCB into the appropriate ready queue for - * the task. It is inserted at the end of the list. One quirk of this is - * that if the task being inserted is at the same priority as the currently - * executing task, then it will only be rescheduled after the currently - * executing task has been rescheduled. - */ -#define prvAddTaskToReadyQueue( pxTCB ) \ -{ \ - if( pxTCB->uxPriority > uxTopReadyPriority ) \ - { \ - uxTopReadyPriority = pxTCB->uxPriority; \ - } \ - vListInsertEnd( ( xList * ) &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ); \ -} - -/* - * Macro that looks at the list of tasks that are currently delayed to see if - * any require waking. - * - * Tasks are stored in the queue in the order of their wake time - meaning - * once one tasks has been found whose timer has not expired we need not look - * any further down the list. - */ -#define prvCheckDelayedTasks() \ -{ \ -register tskTCB *pxTCB; \ - \ - while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ) ) != NULL ) \ - { \ - if( xTickCount < listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) ) ) \ - { \ - break; \ - } \ - vListRemove( &( pxTCB->xGenericListItem ) ); \ - /* Is the task waiting on an event also? */ \ - if( pxTCB->xEventListItem.pvContainer ) \ - { \ - vListRemove( &( pxTCB->xEventListItem ) ); \ - } \ - prvAddTaskToReadyQueue( pxTCB ); \ - } \ -} - -/* - * Several functions take an xTaskHandle parameter that can optionally be NULL, - * where NULL is used to indicate that the handle of the currently executing - * task should be used in place of the parameter. This macro simply checks to - * see if the parameter is NULL and returns a pointer to the appropriate TCB. - */ -#define prvGetTCBFromHandle( pxHandle ) ( ( pxHandle == NULL ) ? ( tskTCB * ) pxCurrentTCB : ( tskTCB * ) pxHandle ) - - -/* File private functions. --------------------------------*/ - -/* - * Utility to ready a TCB for a given task. Mainly just copies the parameters - * into the TCB structure. - */ -static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ); - -/* - * Utility to ready all the lists used by the scheduler. This is called - * automatically upon the creation of the first task. - */ -static void prvInitialiseTaskLists( void ); - -/* - * The idle task, which as all tasks is implemented as a never ending loop. - * The idle task is automatically created and added to the ready lists upon - * creation of the first user task. - * - * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific - * language extensions. The equivalent prototype for this function is: - * - * void prvIdleTask( void *pvParameters ); - * - */ -static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ); - -/* - * Utility to free all memory allocated by the scheduler to hold a TCB, - * including the stack pointed to by the TCB. - * - * This does not free memory allocated by the task itself (i.e. memory - * allocated by calls to pvPortMalloc from within the tasks application code). - */ -#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) - static void prvDeleteTCB( tskTCB *pxTCB ); -#endif - -/* - * Used only by the idle task. This checks to see if anything has been placed - * in the list of tasks waiting to be deleted. If so the task is cleaned up - * and its TCB deleted. - */ -static void prvCheckTasksWaitingTermination( void ); - -/* - * Allocates memory from the heap for a TCB and associated stack. Checks the - * allocation was successful. - */ -static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ); - -/* - * Called from vTaskList. vListTasks details all the tasks currently under - * control of the scheduler. The tasks may be in one of a number of lists. - * prvListTaskWithinSingleList accepts a list and details the tasks from - * within just that list. - * - * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM - * NORMAL APPLICATION CODE. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ); - -#endif - -/* - * When a task is created, the stack of the task is filled with a known value. - * This function determines the 'high water mark' of the task stack by - * determining how much of the stack remains at the original preset value. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte ); - -#endif - -/*lint +e956 */ - - - - - -/*----------------------------------------------------------- - * TASK CREATION API documented in task.h - *----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask ) -{ -signed portBASE_TYPE xReturn; -tskTCB * pxNewTCB; -static unsigned portBASE_TYPE uxTaskNumber = 0; /*lint !e956 Static is deliberate - this is guarded before use. */ - - /* Allocate the memory required by the TCB and stack for the new task. - checking that the allocation was successful. */ - pxNewTCB = prvAllocateTCBAndStack( usStackDepth ); - - if( pxNewTCB != NULL ) - { - portSTACK_TYPE *pxTopOfStack; - - /* Setup the newly allocated TCB with the initial state of the task. */ - prvInitialiseTCBVariables( pxNewTCB, usStackDepth, pcName, uxPriority ); - - /* Calculate the top of stack address. This depends on whether the - stack grows from high memory to low (as per the 80x86) or visa versa. - portSTACK_GROWTH is used to make the result positive or negative as - required by the port. */ - #if portSTACK_GROWTH < 0 - { - pxTopOfStack = pxNewTCB->pxStack + ( pxNewTCB->usStackDepth - 1 ); - } - #else - { - pxTopOfStack = pxNewTCB->pxStack; - } - #endif - - /* Initialize the TCB stack to look as if the task was already running, - but had been interrupted by the scheduler. The return address is set - to the start of the task function. Once the stack has been initialised - the top of stack variable is updated. */ - pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pvTaskCode, pvParameters ); - - /* We are going to manipulate the task queues to add this task to a - ready list, so must make sure no interrupts occur. */ - portENTER_CRITICAL(); - { - uxCurrentNumberOfTasks++; - if( uxCurrentNumberOfTasks == ( unsigned portBASE_TYPE ) 1 ) - { - /* As this is the first task it must also be the current task. */ - pxCurrentTCB = pxNewTCB; - - /* This is the first task to be created so do the preliminary - initialisation required. We will not recover if this call - fails, but we will report the failure. */ - prvInitialiseTaskLists(); - } - else - { - /* If the scheduler is not already running, make this task the - current task if it is the highest priority task to be created - so far. */ - if( xSchedulerRunning == pdFALSE ) - { - if( pxCurrentTCB->uxPriority <= uxPriority ) - { - pxCurrentTCB = pxNewTCB; - } - } - } - - /* Remember the top priority to make context switching faster. Use - the priority in pxNewTCB as this has been capped to a valid value. */ - if( pxNewTCB->uxPriority > uxTopUsedPriority ) - { - uxTopUsedPriority = pxNewTCB->uxPriority; - } - - /* Add a counter into the TCB for tracing only. */ - pxNewTCB->uxTCBNumber = uxTaskNumber; - uxTaskNumber++; - - prvAddTaskToReadyQueue( pxNewTCB ); - - xReturn = pdPASS; - } - portEXIT_CRITICAL(); - } - else - { - xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - } - - if( xReturn == pdPASS ) - { - if( ( void * ) pxCreatedTask != NULL ) - { - /* Pass the TCB out - in an anonymous way. The calling function/ - task can use this as a handle to delete the task later if - required.*/ - *pxCreatedTask = ( xTaskHandle ) pxNewTCB; - } - - if( xSchedulerRunning != pdFALSE ) - { - /* If the created task is of a higher priority than the current task - then it should run now. */ - if( pxCurrentTCB->uxPriority < uxPriority ) - { - taskYIELD(); - } - } - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelete == 1 ) - - void vTaskDelete( xTaskHandle pxTaskToDelete ) - { - tskTCB *pxTCB; - - taskENTER_CRITICAL(); - { - /* Ensure a yield is performed if the current task is being - deleted. */ - if( pxTaskToDelete == pxCurrentTCB ) - { - pxTaskToDelete = NULL; - } - - /* If null is passed in here then we are deleting ourselves. */ - pxTCB = prvGetTCBFromHandle( pxTaskToDelete ); - - /* Remove task from the ready list and place in the termination list. - This will stop the task from be scheduled. The idle task will check - the termination list and free up any memory allocated by the - scheduler for the TCB and stack. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Is the task waiting on an event also? */ - if( pxTCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - } - - vListInsertEnd( ( xList * ) &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) ); - - /* Increment the ucTasksDeleted variable so the idle task knows - there is a task that has been deleted and that it should therefore - check the xTasksWaitingTermination list. */ - ++uxTasksDeleted; - } - taskEXIT_CRITICAL(); - - /* Force a reschedule if we have just deleted the current task. */ - if( xSchedulerRunning != pdFALSE ) - { - if( ( void * ) pxTaskToDelete == NULL ) - { - taskYIELD(); - } - } - } - -#endif - - - - - - -/*----------------------------------------------------------- - * TASK CONTROL API documented in task.h - *----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelayUntil == 1 ) - - void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement ) - { - portTickType xTimeToWake; - portBASE_TYPE xAlreadyYielded, xShouldDelay = pdFALSE; - - vTaskSuspendAll(); - { - /* Generate the tick time at which the task wants to wake. */ - xTimeToWake = *pxPreviousWakeTime + xTimeIncrement; - - if( xTickCount < *pxPreviousWakeTime ) - { - /* The tick count has overflowed since this function was - lasted called. In this case the only time we should ever - actually delay is if the wake time has also overflowed, - and the wake time is greater than the tick time. When this - is the case it is as if neither time had overflowed. */ - if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xTickCount ) ) - { - xShouldDelay = pdTRUE; - } - } - else - { - /* The tick time has not overflowed. In this case we will - delay if either the wake time has overflowed, and/or the - tick time is less than the wake time. */ - if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xTickCount ) ) - { - xShouldDelay = pdTRUE; - } - } - - /* Update the wake time ready for the next call. */ - *pxPreviousWakeTime = xTimeToWake; - - if( xShouldDelay ) - { - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - } - xAlreadyYielded = xTaskResumeAll(); - - /* Force a reschedule if xTaskResumeAll has not already done so, we may - have put ourselves to sleep. */ - if( !xAlreadyYielded ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelay == 1 ) - - void vTaskDelay( portTickType xTicksToDelay ) - { - portTickType xTimeToWake; - signed portBASE_TYPE xAlreadyYielded = pdFALSE; - - /* A delay time of zero just forces a reschedule. */ - if( xTicksToDelay > ( portTickType ) 0 ) - { - vTaskSuspendAll(); - { - /* A task that is removed from the event list while the - scheduler is suspended will not get placed in the ready - list or removed from the blocked list until the scheduler - is resumed. - - This task cannot be in an event list as it is the currently - executing task. */ - - /* Calculate the time to wake - this may overflow but this is - not a problem. */ - xTimeToWake = xTickCount + xTicksToDelay; - - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - xAlreadyYielded = xTaskResumeAll(); - } - - /* Force a reschedule if xTaskResumeAll has not already done so, we may - have put ourselves to sleep. */ - if( !xAlreadyYielded ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_uxTaskPriorityGet == 1 ) - - unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ) - { - tskTCB *pxTCB; - unsigned portBASE_TYPE uxReturn; - - taskENTER_CRITICAL(); - { - /* If null is passed in here then we are changing the - priority of the calling function. */ - pxTCB = prvGetTCBFromHandle( pxTask ); - uxReturn = pxTCB->uxPriority; - } - taskEXIT_CRITICAL(); - - return uxReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskPrioritySet == 1 ) - - void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ) - { - tskTCB *pxTCB; - unsigned portBASE_TYPE uxCurrentPriority, xYieldRequired = pdFALSE; - - /* Ensure the new priority is valid. */ - if( uxNewPriority >= configMAX_PRIORITIES ) - { - uxNewPriority = configMAX_PRIORITIES - 1; - } - - taskENTER_CRITICAL(); - { - /* If null is passed in here then we are changing the - priority of the calling function. */ - pxTCB = prvGetTCBFromHandle( pxTask ); - uxCurrentPriority = pxTCB->uxPriority; - - if( uxCurrentPriority != uxNewPriority ) - { - /* The priority change may have readied a task of higher - priority than the calling task. */ - if( uxNewPriority > pxCurrentTCB->uxPriority ) - { - if( pxTask != NULL ) - { - /* The priority of another task is being raised. If we - were raising the priority of the currently running task - there would be no need to switch as it must have already - been the highest priority task. */ - xYieldRequired = pdTRUE; - } - } - else if( pxTask == NULL ) - { - /* Setting our own priority down means there may now be another - task of higher priority that is ready to execute. */ - xYieldRequired = pdTRUE; - } - - pxTCB->uxPriority = uxNewPriority; - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxNewPriority ); - - /* If the task is in the blocked or suspended list we need do - nothing more than change it's priority variable. However, if - the task is in a ready list it needs to be removed and placed - in the queue appropriate to its new priority. */ - if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxCurrentPriority ] ), &( pxTCB->xGenericListItem ) ) ) - { - /* The task is currently in its ready list - remove before adding - it to it's new ready list. As we are in a critical section we - can do this even if the scheduler is suspended. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - } - - if( xYieldRequired == pdTRUE ) - { - taskYIELD(); - } - } - } - taskEXIT_CRITICAL(); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - void vTaskSuspend( xTaskHandle pxTaskToSuspend ) - { - tskTCB *pxTCB; - - taskENTER_CRITICAL(); - { - /* Ensure a yield is performed if the current task is being - suspended. */ - if( pxTaskToSuspend == pxCurrentTCB ) - { - pxTaskToSuspend = NULL; - } - - /* If null is passed in here then we are suspending ourselves. */ - pxTCB = prvGetTCBFromHandle( pxTaskToSuspend ); - - /* Remove task from the ready/delayed list and place in the suspended list. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Is the task waiting on an event also? */ - if( pxTCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - } - - vListInsertEnd( ( xList * ) &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ); - } - taskEXIT_CRITICAL(); - - /* We may have just suspended the current task. */ - if( ( void * ) pxTaskToSuspend == NULL ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - void vTaskResume( xTaskHandle pxTaskToResume ) - { - tskTCB *pxTCB; - - /* Remove the task from whichever list it is currently in, and place - it in the ready list. */ - pxTCB = ( tskTCB * ) pxTaskToResume; - - /* The parameter cannot be NULL as it is impossible to resume the - currently executing task. */ - if( pxTCB != NULL ) - { - taskENTER_CRITICAL(); - { - /* Is the task we are attempting to resume actually suspended? */ - if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE ) - { - /* Has the task already been resumed from within an ISR? */ - if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdTRUE ) - { - /* As we are in a critical section we can access the ready - lists even if the scheduler is suspended. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - - /* We may have just resumed a higher priority task. */ - if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - /* This yield may not cause the task just resumed to run, but - will leave the lists in the correct state for the next yield. */ - taskYIELD(); - } - } - } - } - taskEXIT_CRITICAL(); - } - } - -#endif - -/*-----------------------------------------------------------*/ - -#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ) - { - portBASE_TYPE xYieldRequired = pdFALSE; - tskTCB *pxTCB; - - pxTCB = ( tskTCB * ) pxTaskToResume; - - /* Is the task we are attempting to resume actually suspended? */ - if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE ) - { - /* Has the task already been resumed from within an ISR? */ - if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdTRUE ) - { - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - xYieldRequired = ( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ); - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - } - else - { - /* We cannot access the delayed or ready lists, so will hold this - task pending until the scheduler is resumed, at which point a - yield will be preformed if necessary. */ - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); - } - } - } - - return xYieldRequired; - } - -#endif - - - - -/*----------------------------------------------------------- - * PUBLIC SCHEDULER CONTROL documented in task.h - *----------------------------------------------------------*/ - - -void vTaskStartScheduler( void ) -{ -portBASE_TYPE xReturn; - - /* Add the idle task at the lowest priority. */ - xReturn = xTaskCreate( prvIdleTask, ( signed portCHAR * ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); - - if( xReturn == pdPASS ) - { - /* Interrupts are turned off here, to ensure a tick does not occur - before or during the call to xPortStartScheduler(). The stacks of - the created tasks contain a status word with interrupts switched on - so interrupts will automatically get re-enabled when the first task - starts to run. - - STEPPING THROUGH HERE USING A DEBUGGER CAN CAUSE BIG PROBLEMS IF THE - DEBUGGER ALLOWS INTERRUPTS TO BE PROCESSED. */ - portDISABLE_INTERRUPTS(); - - xSchedulerRunning = pdTRUE; - xTickCount = ( portTickType ) 0; - - /* Setting up the timer tick is hardware specific and thus in the - portable interface. */ - if( xPortStartScheduler() ) - { - /* Should not reach here as if the scheduler is running the - function will not return. */ - } - else - { - /* Should only reach here if a task calls xTaskEndScheduler(). */ - } - } -} -/*-----------------------------------------------------------*/ - -void vTaskEndScheduler( void ) -{ - /* Stop the scheduler interrupts and call the portable scheduler end - routine so the original ISRs can be restored if necessary. The port - layer must ensure interrupts enable bit is left in the correct state. */ - portDISABLE_INTERRUPTS(); - xSchedulerRunning = pdFALSE; - vPortEndScheduler(); -} -/*----------------------------------------------------------*/ - -void vTaskSuspendAll( void ) -{ - portENTER_CRITICAL(); - ++uxSchedulerSuspended; - portEXIT_CRITICAL(); -} -/*----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskResumeAll( void ) -{ -register tskTCB *pxTCB; -signed portBASE_TYPE xAlreadyYielded = pdFALSE; - - /* It is possible that an ISR caused a task to be removed from an event - list while the scheduler was suspended. If this was the case then the - removed task will have been added to the xPendingReadyList. Once the - scheduler has been resumed it is safe to move all the pending ready - tasks from this list into their appropriate ready list. */ - portENTER_CRITICAL(); - { - --uxSchedulerSuspended; - - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - if( uxCurrentNumberOfTasks > ( unsigned portBASE_TYPE ) 0 ) - { - portBASE_TYPE xYieldRequired = pdFALSE; - - /* Move any readied tasks from the pending list into the - appropriate ready list. */ - while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xPendingReadyList ) ) ) != NULL ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - - /* If we have moved a task that has a priority higher than - the current task then we should yield. */ - if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - xYieldRequired = pdTRUE; - } - } - - /* If any ticks occurred while the scheduler was suspended then - they should be processed now. This ensures the tick count does not - slip, and that any delayed tasks are resumed at the correct time. */ - if( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) - { - while( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) - { - vTaskIncrementTick(); - --uxMissedTicks; - } - - /* As we have processed some ticks it is appropriate to yield - to ensure the highest priority task that is ready to run is - the task actually running. */ - xYieldRequired = pdTRUE; - } - - if( ( xYieldRequired == pdTRUE ) || ( xMissedYield == pdTRUE ) ) - { - xAlreadyYielded = pdTRUE; - xMissedYield = pdFALSE; - taskYIELD(); - } - } - } - } - portEXIT_CRITICAL(); - - return xAlreadyYielded; -} - - - - - - -/*----------------------------------------------------------- - * PUBLIC TASK UTILITIES documented in task.h - *----------------------------------------------------------*/ - - - -portTickType xTaskGetTickCount( void ) -{ -portTickType xTicks; - - /* Critical section required if running on a 16 bit processor. */ - taskENTER_CRITICAL(); - { - xTicks = xTickCount; - } - taskEXIT_CRITICAL(); - - return xTicks; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ) -{ -unsigned portBASE_TYPE uxNumberOfTasks; - - taskENTER_CRITICAL(); - uxNumberOfTasks = uxCurrentNumberOfTasks; - taskEXIT_CRITICAL(); - - return uxNumberOfTasks; -} -/*-----------------------------------------------------------*/ - -#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_vTaskDelete == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - void vTaskList( signed portCHAR *pcWriteBuffer ) - { - unsigned portBASE_TYPE uxQueue; - - /* This is a VERY costly function that should be used for debug only. - It leaves interrupts disabled for a LONG time. */ - - vTaskSuspendAll(); - { - /* Run through all the lists that could potentially contain a TCB and - report the task name, state and stack high water mark. */ - - pcWriteBuffer[ 0 ] = ( signed portCHAR ) 0x00; - strcat( ( portCHAR * ) pcWriteBuffer, ( const portCHAR * ) "\r\n" ); - - uxQueue = uxTopUsedPriority + 1; - - do - { - uxQueue--; - - if( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), tskREADY_CHAR ); - } - }while( uxQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); - - if( !listLIST_IS_EMPTY( pxDelayedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, tskBLOCKED_CHAR ); - } - - if( !listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, tskBLOCKED_CHAR ); - } - - if( !listLIST_IS_EMPTY( &xTasksWaitingTermination ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xTasksWaitingTermination, tskDELETED_CHAR ); - } - - if( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xSuspendedTaskList, tskSUSPENDED_CHAR ); - } - } - xTaskResumeAll(); - } - -#endif -/*----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ) - { - portENTER_CRITICAL(); - { - pcTraceBuffer = ( volatile signed portCHAR * volatile )pcBuffer; - pcTraceBufferStart = pcBuffer; - pcTraceBufferEnd = pcBuffer + ( ulBufferSize - tskSIZE_OF_EACH_TRACE_LINE ); - xTracing = pdTRUE; - } - portEXIT_CRITICAL(); - } - -#endif -/*----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - unsigned portLONG ulTaskEndTrace( void ) - { - unsigned portLONG ulBufferLength; - - portENTER_CRITICAL(); - xTracing = pdFALSE; - portEXIT_CRITICAL(); - - ulBufferLength = ( unsigned portLONG ) ( pcTraceBuffer - pcTraceBufferStart ); - - return ulBufferLength; - } - -#endif - - - -/*----------------------------------------------------------- - * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES - * documented in task.h - *----------------------------------------------------------*/ - - -inline void vTaskIncrementTick( void ) -{ - /* Called by the portable layer each time a tick interrupt occurs. - Increments the tick then checks to see if the new tick value will cause any - tasks to be unblocked. */ - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - ++xTickCount; - if( xTickCount == ( portTickType ) 0 ) - { - xList *pxTemp; - - /* Tick count has overflowed so we need to swap the delay lists. - If there are any items in pxDelayedTaskList here then there is - an error! */ - pxTemp = pxDelayedTaskList; - pxDelayedTaskList = pxOverflowDelayedTaskList; - pxOverflowDelayedTaskList = pxTemp; - xNumOfOverflows++; - } - - /* See if this tick has made a timeout expire. */ - prvCheckDelayedTasks(); - } - else - { - ++uxMissedTicks; - - /* The tick hook gets called at regular intervals, even if the - scheduler is locked. */ - #if ( configUSE_TICK_HOOK == 1 ) - { - extern void vApplicationTickHook( void ); - - vApplicationTickHook(); - } - #endif - } - - #if ( configUSE_TICK_HOOK == 1 ) - { - extern void vApplicationTickHook( void ); - - /* Guard against the tick hook being called when the missed tick - count is being unwound (when the scheduler is being unlocked. */ - if( uxMissedTicks == 0 ) - { - vApplicationTickHook(); - } - } - #endif -} -/*-----------------------------------------------------------*/ - -#if ( ( INCLUDE_vTaskCleanUpResources == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - void vTaskCleanUpResources( void ) - { - unsigned portSHORT usQueue; - volatile tskTCB *pxTCB; - - usQueue = ( unsigned portSHORT ) uxTopUsedPriority + ( unsigned portSHORT ) 1; - - /* Remove any TCB's from the ready queues. */ - do - { - usQueue--; - - while( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ usQueue ] ) ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &( pxReadyTasksLists[ usQueue ] ) ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - }while( usQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); - - /* Remove any TCB's from the delayed queue. */ - while( !listLIST_IS_EMPTY( &xDelayedTaskList1 ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList1 ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - /* Remove any TCB's from the overflow delayed queue. */ - while( !listLIST_IS_EMPTY( &xDelayedTaskList2 ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList2 ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - while( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xSuspendedTaskList ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - while( !listLIST_IS_EMPTY( &xPendingReadyList ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xPendingReadyList ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - } - -#endif -/*-----------------------------------------------------------*/ - -void vTaskSwitchContext( void ) -{ - if( uxSchedulerSuspended != ( unsigned portBASE_TYPE ) pdFALSE ) - { - /* The scheduler is currently suspended - do not allow a context - switch. */ - xMissedYield = pdTRUE; - return; - } - - /* Find the highest priority queue that contains ready tasks. */ - while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) ) - { - --uxTopReadyPriority; - } - - /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the tasks of the - same priority get an equal share of the processor time. */ - listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) ); - vWriteTraceToBuffer(); -} -/*-----------------------------------------------------------*/ - -void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait ) -{ -portTickType xTimeToWake; - - /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE - SCHEDULER SUSPENDED. */ - - /* Place the event list item of the TCB in the appropriate event list. - This is placed in the list in priority order so the highest priority task - is the first to be woken by the event. */ - vListInsert( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) ); - - /* Calculate the time at which the task should be woken if the event does - not occur. This may overflow but this doesn't matter. */ - xTimeToWake = xTickCount + xTicksToWait; - - /* We must remove ourselves from the ready list before adding ourselves - to the blocked list as the same list item is used for both lists. We have - exclusive access to the ready lists as the scheduler is locked. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList ) -{ -tskTCB *pxUnblockedTCB; -portBASE_TYPE xReturn; - - /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE - SCHEDULER SUSPENDED. It can also be called from within an ISR. */ - - /* The event list is sorted in priority order, so we can remove the - first in the list, remove the TCB from the delayed list, and add - it to the ready list. - - If an event is for a queue that is locked then this function will never - get called - the lock count on the queue will get modified instead. This - means we can always expect exclusive access to the event list here. */ - pxUnblockedTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); - vListRemove( &( pxUnblockedTCB->xEventListItem ) ); - - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - vListRemove( &( pxUnblockedTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxUnblockedTCB ); - } - else - { - /* We cannot access the delayed or ready lists, so will hold this - task pending until the scheduler is resumed. */ - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); - } - - if( pxUnblockedTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - /* Return true if the task removed from the event list has - a higher priority than the calling task. This allows - the calling task to know if it should force a context - switch now. */ - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vTaskSetTimeOutState( xTimeOutType *pxTimeOut ) -{ - pxTimeOut->xOverflowCount = xNumOfOverflows; - pxTimeOut->xTimeOnEntering = xTickCount; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType *pxTimeOut, portTickType *pxTicksToWait ) -{ -portBASE_TYPE xReturn; - - if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xTickCount > pxTimeOut->xTimeOnEntering ) ) - { - /* The tick count is greater than the time at which vTaskSetTimeout() - was called, but has also overflowed since vTaskSetTimeOut() was called. - It must have wrapped all the way around and gone past us again. This - passed since vTaskSetTimeout() was called. */ - xReturn = pdTRUE; - } - else if( ( xTickCount - pxTimeOut->xTimeOnEntering ) < *pxTicksToWait ) - { - /* Not a genuine timeout. Adjust parameters for time remaining. */ - *pxTicksToWait -= ( xTickCount - pxTimeOut->xTimeOnEntering ); - vTaskSetTimeOutState( pxTimeOut ); - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vTaskMissedYield( void ) -{ - xMissedYield = pdTRUE; -} - -/* - * ----------------------------------------------------------- - * The Idle task. - * ---------------------------------------------------------- - * - * The portTASK_FUNCTION() macro is used to allow port/compiler specific - * language extensions. The equivalent prototype for this function is: - * - * void prvIdleTask( void *pvParameters ); - * - */ -static portTASK_FUNCTION( prvIdleTask, pvParameters ) -{ - /* Stop warnings. */ - ( void ) pvParameters; - - for( ;; ) - { - /* See if any tasks have been deleted. */ - prvCheckTasksWaitingTermination(); - - #if ( configUSE_PREEMPTION == 0 ) - { - /* If we are not using preemption we keep forcing a task switch to - see if any other task has become available. If we are using - preemption we don't need to do this as any task becoming available - will automatically get the processor anyway. */ - taskYIELD(); - } - #endif - - #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) - { - /* When using preemption tasks of equal priority will be - timesliced. If a task that is sharing the idle priority is ready - to run then the idle task should yield before the end of the - timeslice. - - A critical region is not required here as we are just reading from - the list, and an occasional incorrect value will not matter. If - the ready list at the idle priority contains more than one task - then a task other than the idle task is ready to execute. */ - if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( unsigned portBASE_TYPE ) 1 ) - { - taskYIELD(); - } - } - #endif - - #if ( configUSE_IDLE_HOOK == 1 ) - { - extern void vApplicationIdleHook( void ); - - /* Call the user defined function from within the idle task. This - allows the application designer to add background functionality - without the overhead of a separate task. - NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, - CALL A FUNCTION THAT MIGHT BLOCK. */ - vApplicationIdleHook(); - } - #endif - } -} /*lint !e715 pvParameters is not accessed but all task functions require the same prototype. */ - - - - - - - -/*----------------------------------------------------------- - * File private functions documented at the top of the file. - *----------------------------------------------------------*/ - - - -static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ) -{ - pxTCB->usStackDepth = usStackDepth; - - /* Store the function name in the TCB. */ - strncpy( ( char * ) pxTCB->pcTaskName, ( const char * ) pcName, ( unsigned portSHORT ) configMAX_TASK_NAME_LEN ); - pxTCB->pcTaskName[ ( unsigned portSHORT ) configMAX_TASK_NAME_LEN - ( unsigned portSHORT ) 1 ] = '\0'; - - /* This is used as an array index so must ensure it's not too large. */ - if( uxPriority >= configMAX_PRIORITIES ) - { - uxPriority = configMAX_PRIORITIES - 1; - } - - pxTCB->uxPriority = uxPriority; - - vListInitialiseItem( &( pxTCB->xGenericListItem ) ); - vListInitialiseItem( &( pxTCB->xEventListItem ) ); - - /* Set the pxTCB as a link back from the xListItem. This is so we can get - back to the containing TCB from a generic item in a list. */ - listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB ); - - /* Event lists are always in priority order. */ - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); - listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB ); -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseTaskLists( void ) -{ -unsigned portBASE_TYPE uxPriority; - - for( uxPriority = 0; uxPriority < configMAX_PRIORITIES; uxPriority++ ) - { - vListInitialise( ( xList * ) &( pxReadyTasksLists[ uxPriority ] ) ); - } - - vListInitialise( ( xList * ) &xDelayedTaskList1 ); - vListInitialise( ( xList * ) &xDelayedTaskList2 ); - vListInitialise( ( xList * ) &xPendingReadyList ); - - #if ( INCLUDE_vTaskDelete == 1 ) - { - vListInitialise( ( xList * ) &xTasksWaitingTermination ); - } - #endif - - #if ( INCLUDE_vTaskSuspend == 1 ) - { - vListInitialise( ( xList * ) &xSuspendedTaskList ); - } - #endif - - /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList - using list2. */ - pxDelayedTaskList = &xDelayedTaskList1; - pxOverflowDelayedTaskList = &xDelayedTaskList2; -} -/*-----------------------------------------------------------*/ - -static void prvCheckTasksWaitingTermination( void ) -{ - #if ( INCLUDE_vTaskDelete == 1 ) - { - portBASE_TYPE xListIsEmpty; - - /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called - too often in the idle task. */ - if( uxTasksDeleted > ( unsigned portBASE_TYPE ) 0 ) - { - vTaskSuspendAll(); - xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination ); - xTaskResumeAll(); - - if( !xListIsEmpty ) - { - tskTCB *pxTCB; - - portENTER_CRITICAL(); - { - pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xTasksWaitingTermination ) ); - vListRemove( &( pxTCB->xGenericListItem ) ); - --uxCurrentNumberOfTasks; - --uxTasksDeleted; - } - portEXIT_CRITICAL(); - - prvDeleteTCB( pxTCB ); - } - } - } - #endif -} -/*-----------------------------------------------------------*/ - -static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ) -{ -tskTCB *pxNewTCB; - - /* Allocate space for the TCB. Where the memory comes from depends on - the implementation of the port malloc function. */ - pxNewTCB = ( tskTCB * ) pvPortMalloc( sizeof( tskTCB ) ); - - if( pxNewTCB != NULL ) - { - /* Allocate space for the stack used by the task being created. - The base of the stack memory stored in the TCB so the task can - be deleted later if required. */ - pxNewTCB->pxStack = ( portSTACK_TYPE * ) pvPortMalloc( ( ( size_t )usStackDepth ) * sizeof( portSTACK_TYPE ) ); - - if( pxNewTCB->pxStack == NULL ) - { - /* Could not allocate the stack. Delete the allocated TCB. */ - vPortFree( pxNewTCB ); - pxNewTCB = NULL; - } - else - { - /* Just to help debugging. */ - memset( pxNewTCB->pxStack, tskSTACK_FILL_BYTE, usStackDepth * sizeof( portSTACK_TYPE ) ); - } - } - - return pxNewTCB; -} -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ) - { - volatile tskTCB *pxNextTCB, *pxFirstTCB; - static portCHAR pcStatusString[ 50 ]; - unsigned portSHORT usStackRemaining; - - /* Write the details of all the TCB's in pxList into the buffer. */ - listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); - do - { - listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); - usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned portCHAR * ) pxNextTCB->pxStack ); - sprintf( pcStatusString, ( portCHAR * ) "%s\t\t%c\t%u\t%u\t%u\r\n", pxNextTCB->pcTaskName, cStatus, ( unsigned int ) pxNextTCB->uxPriority, usStackRemaining, ( unsigned int ) pxNextTCB->uxTCBNumber ); - strcat( ( portCHAR * ) pcWriteBuffer, ( portCHAR * ) pcStatusString ); - - } while( pxNextTCB != pxFirstTCB ); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte ) - { - register unsigned portSHORT usCount = 0; - - while( *pucStackByte == tskSTACK_FILL_BYTE ) - { - pucStackByte -= portSTACK_GROWTH; - usCount++; - } - - usCount /= sizeof( portSTACK_TYPE ); - - return usCount; - } -#endif -/*-----------------------------------------------------------*/ - - - -#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) - - static void prvDeleteTCB( tskTCB *pxTCB ) - { - /* Free up the memory allocated by the scheduler for the task. It is up to - the task to free any memory allocated at the application level. */ - vPortFree( pxTCB->pxStack ); - vPortFree( pxTCB ); - } - -#endif - - -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) - - xTaskHandle xTaskGetCurrentTaskHandle( void ) - { - xTaskHandle xReturn; - - portENTER_CRITICAL(); - { - xReturn = ( xTaskHandle ) pxCurrentTCB; - } - portEXIT_CRITICAL(); - - return xReturn; - } - -#endif - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/71x_lib.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/71x_lib.c deleted file mode 100644 index fcc5896a4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/71x_lib.c +++ /dev/null @@ -1,159 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_lib.c -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Peripherals pointers initialization -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#define EXT - -#include "71x_map.h" - -#ifdef LIBDEBUG - -extern u32 T0TIMI_Addr; - -/******************************************************************************* -* Function Name : debug -* Description : Initialize the pointers to peripherals -* Input : none -* Output : none -* Return : none -*******************************************************************************/ -void libdebug(void) -{ - #ifdef _ADC12 - ADC12 = (ADC12_TypeDef *)ADC12_BASE; - #endif - - #ifdef _APB - #ifdef _APB1 - APB1 = (APB_TypeDef *)(APB1_BASE+0x10); - #endif - #ifdef _APB2 - APB2 = (APB_TypeDef *)(APB2_BASE+0x10); - #endif - #endif - - #ifdef _BSPI - #ifdef _BSPI0 - BSPI0 = (BSPI_TypeDef *)BSPI0_BASE; - #endif - #ifdef _BSPI1 - BSPI1 = (BSPI_TypeDef *)BSPI1_BASE; - #endif - #endif - - #ifdef _CAN - CAN = (CAN_TypeDef *)CAN_BASE; - #endif - - #ifdef _EIC - EIC = (EIC_TypeDef *)EIC_BASE; - #endif - - #ifdef _EMI - EMI = (EMI_TypeDef *)EMI_BASE; - #endif - - #ifdef _FLASH - FLASHR = (FLASHR_TypeDef *)FLASHR_BASE; - FLASHPR = (FLASHPR_TypeDef *)FLASHPR_BASE; - #endif - - #ifdef _GPIO - #ifdef _GPIO0 - GPIO0 = (GPIO_TypeDef *)GPIO0_BASE; - #endif - #ifdef _GPIO1 - GPIO1 = (GPIO_TypeDef *)GPIO1_BASE; - #endif - #ifdef _GPIO2 - GPIO2 = (GPIO_TypeDef *)GPIO2_BASE; - #endif - #endif - - #ifdef _I2C - #ifdef _I2C0 - I2C0 = (I2C_TypeDef *)I2C0_BASE; - #endif - #ifdef _I2C1 - I2C1 = (I2C_TypeDef *)I2C1_BASE; - #endif - #endif - - #ifdef _PCU - PCU = (PCU_TypeDef *)PCU_BASE; - #endif - - #ifdef _RCCU - RCCU = (RCCU_TypeDef *)RCCU_BASE; - #endif - - #ifdef _RTC - RTC = (RTC_TypeDef *)RTC_BASE; - #endif - - #ifdef _TIM - #ifdef _TIM0 - TIM0 = (TIM_TypeDef *)TIM0_BASE; - #endif - #ifdef _TIM1 - TIM1 = (TIM_TypeDef *)TIM1_BASE; - #endif - #ifdef _TIM2 - TIM2 = (TIM_TypeDef *)TIM2_BASE; - #endif - #ifdef _TIM3 - TIM3 = (TIM_TypeDef *)TIM3_BASE; - #endif - #endif - - #ifdef _UART - #ifdef _UART0 - UART0 = (UART_TypeDef *)UART0_BASE; - #endif - #ifdef _UART1 - UART1 = (UART_TypeDef *)UART1_BASE; - #endif - #ifdef _UART2 - UART2 = (UART_TypeDef *)UART2_BASE; - #endif - #ifdef _UART3 - UART3 = (UART_TypeDef *)UART3_BASE; - #endif - #endif - - #ifdef _USB - USB = (USB_TypeDef *)USB_BASE; - #endif - - #ifdef _WDG - WDG = (WDG_TypeDef *)WDG_BASE; - #endif - - #ifdef _XTI - XTI = (XTI_TypeDef *)XTI_BASE; - #endif - - #ifdef _IRQVectors - IRQVectors = (IRQVectors_TypeDef *)&T0TIMI_Addr; - #endif -} - -#endif /* LIBDEBUG */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/adc12.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/adc12.c deleted file mode 100644 index da23919df..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/adc12.c +++ /dev/null @@ -1,84 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : adc12.c -* Author : MCD Application Team -* Date First Issued : 07/31/2003 -* Description : This file provides all the ADC12 software functions. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#include "adc12.h" - - -/******************************************************************************* -* Function Name : ADC12_Init -* Description : This routine is used to initialize the ADC12 registers to -* their reset values -* Input : None. -* Return : None. -*******************************************************************************/ -void ADC12_Init(void) -{ - /* Initiate ADC12 registers to their reset values */ - ADC12->CSR = 0x0000; - ADC12->CPR = 0x0005; -} - -/******************************************************************************* -* Function Name : ADC12_PrescalerConfig -* Description : This routine is used to configure the prescaler register -* Input : Adc12_clk: Sampling frequency in Hz. -* Return : None. -*******************************************************************************/ -void ADC12_PrescalerConfig(u32 Adc12_clk) -{ - /* Update the Prescaler Register */ - ADC12->CPR = (vu16) (RCCU_FrequencyValue(RCCU_PCLK)/(Adc12_clk*512*8)); -} - -/******************************************************************************* -* Function Name : ADC12_ITConfig -* Description : This routine is used to enable or disable the interrupt - routine. -* Input : NewState = ENABLE => Enable the interrupt routine. -* NewState = DISABLE => Disable the interrupt routine. -* Return : None -*******************************************************************************/ -void ADC12_ITConfig(FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* If the single mode is selected */ - if (ADC12->CSR & 0x0040) - { - /* Set the corresponding interrupt bit according to the selected channel */ - switch (ADC12->CSR & 0x30) - { - case 0x00 : ADC12->CSR |= ADC12_IT0_Mask; break; - case 0x10 : ADC12->CSR |= ADC12_IT1_Mask; break; - case 0x20 : ADC12->CSR |= ADC12_IT2_Mask; break; - case 0x30 : ADC12->CSR |= ADC12_IT3_Mask; break; - } - } - - else - /* Set all interrupt bits in case of round robin mode is selected */ - ADC12->CSR |= ADC12_IT_Mask; - } - else - /* Clear all interrupt bits */ - ADC12->CSR &= ~ADC12_IT_Mask; -} -/*********************(c) 2003 STMicroelectronics********************* END OF FILE **/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/apb.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/apb.c deleted file mode 100644 index 3e9d270d7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/apb.c +++ /dev/null @@ -1,25 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : apb.c -* Author : MCD Application Team -* Date First Issued : 05/30/2003 -* Description : This file provides all the APB software functions -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "apb.h" - - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/bspi.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/bspi.c deleted file mode 100644 index 4c581ce0d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/bspi.c +++ /dev/null @@ -1,172 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : bspi.c -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : This file provides all the BSPI software functions -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "bspi.h" - -/******************************************************************************* -* Function Name : BSPI_Init -* Description : Initializes BSPI peripheral control and registers to their default reset values. -* Input : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Output : BSPI peripheral registers and BSPI global variables are initialized. -* Return : None. -*******************************************************************************/ -void BSPI_Init(BSPI_TypeDef *BSPIx) -{ - BSPIx->CSR2 = 0x41; - BSPIx->CSR1 = 0x00; - BSPIx->CLK = 0x06; -} - -/******************************************************************************* -* Function Name : BSPI_TrItSrc. -* Description : Configures the transmit interrupt source. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : TrItSrc: specifies the transmit interrupt source. -* : Refer to the section Transmit Interrupt Sources for more details on the -* : allowed values of this parameter. -* Output : TIE bit in BSPCSR2 register. -* Return : None. -*******************************************************************************/ -void BSPI_TrItSrc(BSPI_TypeDef *BSPIx, BSPI_TR_IT_SRCS TrItSrc) -{ - switch (TrItSrc) - { - case BSPI_TR_DIS: - BSPIx->CSR2 &= ~0xC000; - break; - case BSPI_TR_FE: - BSPIx->CSR2 &= ~0x8000; - BSPIx->CSR2 |= 0x4000; - break; - case BSPI_TR_UFL: - BSPIx->CSR2 &= ~0x4000; - BSPIx->CSR2 |= 0x8000; - break; - case BSPI_TR_FF: - BSPIx->CSR2 |= 0xC000; - break; - } -} - -/******************************************************************************* -* Function Name : BSPI_RcItSrc. -* Description : Configures the receive interrupt source. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : RcItSrc: specifies the source for the receive interrupt. -* : Refer to the section Receive Interrupt Sources for more details on the -* : allowed values of this parameter. -* Output : RIE bit in BSPCSR1 is register. -* Return : None. -*******************************************************************************/ -void BSPI_RcItSrc(BSPI_TypeDef *BSPIx, BSPI_RC_IR_SRCS RcItSrc) -{ - switch (RcItSrc) - { - case BSPI_RC_DIS: - BSPIx->CSR1 &= ~0x000C; - break; - case BSPI_RC_FNE: - BSPIx->CSR1 &= ~0x0008; - BSPIx->CSR1 |= 0x0004; - break; - case BSPI_RC_FF: - BSPIx->CSR1 |= 0x000C; - break; - } -} - -/******************************************************************************* -* Function Name : BSPI_TrFifoDepth -* Description : Configures BSPI transmission FIFO number of words. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI. -* Input 2 : TDepth:specifies the depth of the transmit FIFO. -* Output : TFE bit in BSPCSR2 register. -* Return : None. -*******************************************************************************/ -void BSPI_TrFifoDepth(BSPI_TypeDef *BSPIx, u8 TDepth) -{ - if (TDepth > 0 && TDepth < 11) - { - TDepth--; - BSPIx->CSR2 &= (TDepth*0x400) | ~0x3C00; - BSPIx->CSR2 |= TDepth*0x400; - } - else BSPIx->CSR2 &= ~0x3C00; -} - -/******************************************************************************* -* Function Name : BSPI_RcFifoDepth -* Description : Configures BSPI reception FIFO number of words. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : RDepth:specifies the depth of the receive FIFO. -* Output : RFE bits [3:0] in BSPCSR1 register. -* Return : None. -*******************************************************************************/ -void BSPI_RcFifoDepth(BSPI_TypeDef *BSPIx, u8 RDepth) -{ - if (RDepth > 0 && RDepth < 11) - { - RDepth--; - BSPIx->CSR1 &= (RDepth*0x1000) | ~0xF000; - BSPIx->CSR1 |= RDepth*0x1000; - } - else BSPIx->CSR1 &= ~0xF000; -} - -/******************************************************************************* -* Function Name : BSPI_BufferSend. -* Description : Transmits data from a buffer. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : PtrToBuffer is an u8 pointer to the first word of the buffer to be transmitted. -* Input 3 : NbOfWords parameter indicates the number of words saved in the buffer to be sent. -* Output : None. -* Return : None. -*******************************************************************************/ -void BSPI_BufferSend(BSPI_TypeDef *BSPIx, u8 *PtrToBuffer, u8 NbOfWords) -{ - vu8 SendWord = 0; - while (SendWord < NbOfWords) - { - BSPI_WordSend(BSPIx, *(PtrToBuffer+SendWord)); - SendWord++; - } -} - -/******************************************************************************* -* Function Name : BSPI_BufferReceive. -* Description : Receives number of data words and stores them in user defined area. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : PtrToBuffer is an u8 pointer to the first word of the defined area to save the received buffer. -* Input 3 : NbOfWords parameter indicates the number of words to be received in the buffer. -* Output : None. -* Return : None. -*******************************************************************************/ -void BSPI_BufferReceive(BSPI_TypeDef *BSPIx, u8 *PtrToBuffer, u8 NbOfWords) -{ - vu16 ReceiveWord = 0; - while (ReceiveWord < NbOfWords) - { - *(PtrToBuffer+ReceiveWord) = BSPI_WordReceive(BSPIx); - ReceiveWord++; - } -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/can.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/can.c deleted file mode 100644 index ae3ccc906..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/can.c +++ /dev/null @@ -1,546 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : can.c -* Author : MCD Application Team -* Date First Issued : 10/27/2003 -* Description : This file contains all the functions prototypes for the -* CAN bus software library. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "can.h" -#include "xti.h" -#include "pcu.h" - -// macro to format the timing register value from the timing parameters -#define CAN_TIMING(tseg1, tseg2, sjw, brp) (((tseg2-1) & 0x07) << 12) | (((tseg1-1) & 0x0F) << 8) | (((sjw-1) & 0x03) << 6) | ((brp-1) & 0x3F) - -// array of pre-defined timing parameters for standard bitrates -u16 CanTimings[] = { /* value bitrate NTQ TSEG1 TSEG2 SJW BRP */ - CAN_TIMING(11, 4, 4, 5), /* 0x3AC4 100 kbit/s 16 11 4 4 5 */ - CAN_TIMING(11, 4, 4, 4), /* 0x3AC3 125 kbit/s 16 11 4 4 4 */ - CAN_TIMING( 4, 3, 3, 4), /* 0x2383 250 kbit/s 8 4 3 3 4 */ - CAN_TIMING(13, 2, 1, 1), /* 0x1C00 500 kbit/s 16 13 2 1 1 */ - CAN_TIMING( 4, 3, 1, 1), /* 0x2300 1 Mbit/s 8 4 3 1 1 */ -}; - -/******************************************************************************* -* Function Name : CAN_SetBitrate -* Description : Setup a standard CAN bitrate -* Input 1 : one of the CAN_BITRATE_xxx defines -* Output : None -* Return : None -* Note : CAN must be in initialization mode -*******************************************************************************/ -void CAN_SetBitrate(u32 bitrate) -{ - /* write the predefined timing value */ - CAN->BTR = CanTimings[bitrate]; - - /* clear the Extended Baud Rate Prescaler */ - CAN->BRPR = 0; -} - -/******************************************************************************* -* Function Name : CAN_SetTiming -* Description : Setup the CAN timing with specific parameters -* Input 1 : Time Segment before the sample point position, from 2 to 16 -* Input 2 : Time Segment after the sample point position, from 1 to 8 -* Input 3 : Synchronisation Jump Width, from 1 to 4 -* Input 4 : Baud Rate Prescaler, from 1 to 1024 -* Output : None -* Return : None -* Note : CAN must be in initialization mode -*******************************************************************************/ -void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp) -{ - CAN->BTR = CAN_TIMING(tseg1, tseg2, sjw, brp); - CAN->BRPR = ((brp-1) >> 6) & 0x0F; -} - -/******************************************************************************* -* Function Name : CAN_SleepRequest -* Description : Request the CAN cell to enter sleep mode -* Input 1 : CAN_WAKEUP_ON_EXT or CAN_WAKEUP_ON_CAN -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SleepRequest(u32 WakeupMode) -{ - /* Wakeup Line 6 is linked to CAN RX pin (port 1.11) */ - /* Wakeup Line 2 is linked to external pin (port 2.8) */ - u32 WakeupLine = (WakeupMode == CAN_WAKEUP_ON_CAN ? XTI_Line6 : XTI_Line2); - - CAN_WaitEndOfTx(); - - XTI_Init(); - - /* Configure the Wakeup Line mode, select Falling edge (transition to dominant state) */ - XTI_LineModeConfig(WakeupLine, XTI_FallingEdge); - - /* Enable Wake-Up interrupt */ - XTI_LineConfig(WakeupLine, ENABLE); - - /* Enable Wake-Up mode with interrupt */ - XTI_ModeConfig(XTI_WakeUpInterrupt, ENABLE); - - XTI_PendingBitClear(XTI_InterruptLineValue()); - - /* Enter STOP mode (resume execution from here) */ - PCU_LPMEnter(PCU_STOP); -} - -/******************************************************************************* -* Function Name : CAN_GetFreeIF -* Description : Search the first free message interface, starting from 0 -* Input : None -* Output : None -* Return : A free message interface number (0 or 1) if found, else 2 -*******************************************************************************/ -static u32 CAN_GetFreeIF(void) -{ - if ((CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) == 0) - return 0; - else if ((CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) == 0) - return 1; - else return 2; -} - -/******************************************************************************* -* Macro Name : xxx_ID_MSK, xxx_ID_ARB -* Description : Form the Mask and Arbitration registers value to filter a -* range of identifiers or a fixed identifier, for standard -* and extended IDs -*******************************************************************************/ -#define RANGE_ID_MSK(range_start, range_end) (~((range_end) - (range_start))) -#define RANGE_ID_ARB(range_start, range_end) ((range_start) & (range_end)) - -#define FIXED_ID_MSK(id) RANGE_ID_MSK((id), (id)) -#define FIXED_ID_ARB(id) RANGE_ID_ARB((id), (id)) - -#define STD_RANGE_ID_MSK(range_start, range_end) ((u16)((RANGE_ID_MSK((range_start), (range_end)) & 0x7FF) << 2)) -#define STD_RANGE_ID_ARB(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) << 2)) - -#define STD_FIXED_ID_MSK(id) ((u16)((FIXED_ID_MSK(id) & 0x7FF) << 2)) -#define STD_FIXED_ID_ARB(id) ((u16)(FIXED_ID_ARB(id) << 2)) - -#define EXT_RANGE_ID_MSK_L(range_start, range_end) ((u16)(RANGE_ID_MSK((range_start), (range_end)) >> 11)) -#define EXT_RANGE_ID_MSK_H(range_start, range_end) ((u16)(STD_RANGE_ID_MSK((range_start), (range_end)) | ((RANGE_ID_MSK((range_start), (range_end)) >> 27) & 0x03))) -#define EXT_RANGE_ID_ARB_L(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) >> 11)) -#define EXT_RANGE_ID_ARB_H(range_start, range_end) ((u16)(STD_RANGE_ID_ARB((range_start), (range_end)) | ((RANGE_ID_ARB((range_start), (range_end)) >> 27) & 0x03))) - -#define EXT_FIXED_ID_MSK_L(id) ((u16)(FIXED_ID_MSK(id) >> 11)) -#define EXT_FIXED_ID_MSK_H(id) ((u16)(STD_FIXED_ID_MSK(id) | ((FIXED_ID_MSK(id) >> 27) & 0x03))) -#define EXT_FIXED_ID_ARB_L(id) ((u16)(FIXED_ID_ARB(id) >> 11)) -#define EXT_FIXED_ID_ARB_H(id) ((u16)(STD_FIXED_ID_ARB(id) | ((FIXED_ID_ARB(id) >> 27) & 0x03))) - -/******************************************************************************* -* Function Name : CAN_SetUnusedMsgObj -* Description : Configure the message object as unused -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetUnusedMsgObj(u32 msgobj) -{ - u32 msg_if; - while ((msg_if = CAN_GetFreeIF()) == 2); - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].M2R = 0; - - CAN->sMsgObj[msg_if].A1R = 0; - CAN->sMsgObj[msg_if].A2R = 0; - - CAN->sMsgObj[msg_if].MCR = 0; - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_SetTxMsgObj -* Description : Configure the message object as TX -* Input 1 : message object number, from 0 to 31 -* Input 2 : CAN_STD_ID or CAN_EXT_ID -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetTxMsgObj(u32 msgobj, u32 idType) -{ - u32 msg_if; - while ((msg_if = CAN_GetFreeIF()) == 2); - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].A1R = 0; - - if (idType == CAN_STD_ID) - { - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR; - } - else - { - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR | CAN_M2R_MXTD; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR | CAN_A2R_XTD; - } - - CAN->sMsgObj[msg_if].MCR = CAN_MCR_TXIE | CAN_MCR_EOB; - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_SetRxMsgObj -* Description : Configure the message object as RX -* Input 1 : message object number, from 0 to 31 -* Input 2 : CAN_STD_ID or CAN_EXT_ID -* Input 3 : low part of the identifier range used for acceptance filtering -* Input 4 : high part of the identifier range used for acceptance filtering -* Input 5 : TRUE for a single receive object or a FIFO receive object that -* is the last one of the FIFO -* FALSE for a FIFO receive object that is not the last one -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast) -{ - u32 msg_if; - while ((msg_if = CAN_GetFreeIF()) == 2); - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if (idType == CAN_STD_ID) - { - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].M2R = STD_RANGE_ID_MSK(idLow, idHigh); - - CAN->sMsgObj[msg_if].A1R = 0; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | STD_RANGE_ID_ARB(idLow, idHigh); - } - else - { - CAN->sMsgObj[msg_if].M1R = EXT_RANGE_ID_MSK_L(idLow, idHigh); - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MXTD | EXT_RANGE_ID_MSK_H(idLow, idHigh); - - CAN->sMsgObj[msg_if].A1R = EXT_RANGE_ID_ARB_L(idLow, idHigh); - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_XTD | EXT_RANGE_ID_ARB_H(idLow, idHigh); - } - - CAN->sMsgObj[msg_if].MCR = CAN_MCR_RXIE | CAN_MCR_UMASK | (singleOrFifoLast ? CAN_MCR_EOB : 0); - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_InvalidateAllMsgObj -* Description : Configure all the message objects as unused -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_InvalidateAllMsgObj(void) -{ - u32 i; - for (i = 0; i < 32; i++) - CAN_SetUnusedMsgObj(i); -} - -/******************************************************************************* -* Function Name : CAN_Init -* Description : Initialize the CAN cell and set the bitrate -* Input 1 : any binary value formed from the CAN_CTL_xxx defines -* Input 2 : one of the CAN_BITRATE_xxx defines -* Output : None -* Return : None -*******************************************************************************/ -void CAN_Init(u8 mask, u32 bitrate) -{ - CAN_EnterInitMode(CAN_CR_CCE | mask); - CAN_SetBitrate(bitrate); - CAN_LeaveInitMode(); - CAN_LeaveTestMode(); -} - -/******************************************************************************* -* Function Name : CAN_ReleaseMessage -* Description : Release the message object -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -*******************************************************************************/ -void CAN_ReleaseMessage(u32 msgobj) -{ - u32 i; - while ((i = CAN_GetFreeIF()) == 2); - - CAN->sMsgObj[i].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQST; - CAN->sMsgObj[i].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_SendMessage -* Description : Start transmission of a message -* Input 1 : message object number, from 0 to 31 -* Input 2 : pointer to the message structure containing data to transmit -* Output : None -* Return : 1 if transmission was OK, else 0 -*******************************************************************************/ -u32 CAN_SendMessage(u32 msgobj, canmsg* pCanMsg) -{ - while (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY); - -/* if (CAN->sMsgObj[0].COMR & CAN_CRQ_BUSY) */ -/* return 0; // message interface 0 not free */ - - CAN->SR &= ~CAN_SR_TXOK; - - /* read the Arbitration and Message Control */ - CAN->sMsgObj[0].CMR = CAN_CMR_ARB | CAN_CMR_CONTROL; - - CAN->sMsgObj[0].CRR = 1 + msgobj; - - while (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY); - - /* update the contents needed for transmission */ - CAN->sMsgObj[0].CMR = CAN_CMR_WRRD - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if ((CAN->sMsgObj[0].A2R & CAN_A2R_XTD) == 0) - { - /* standard ID */ - CAN->sMsgObj[0].A1R = 0; - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); - } - else - { - // extended ID - CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); - } - - CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFEF0) | CAN_MCR_NEWDAT | CAN_MCR_TXRQST | pCanMsg->Dlc; - - CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; - CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; - CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; - CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; - - CAN->sMsgObj[0].CRR = 1 + msgobj; - - return 1; -} - -/******************************************************************************* -* Function Name : CAN_ReceiveMessage -* Description : Get the message, if received -* Input 1 : message object number, from 0 to 31 -* Input 2 : if TRUE, the message object is released when getting the data -* if FALSE, the message object is not released -* Input 3 : pointer to the message structure where received data is stored -* Output : None -* Return : 1 if reception was OK, else 0 (no message pending) -*******************************************************************************/ -u32 CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg) -{ - if (!CAN_IsMessageWaiting(msgobj)) - return 0; - - CAN->SR &= ~CAN_SR_RXOK; - - /* read the message contents */ - CAN->sMsgObj[1].CMR = CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_CLRINTPND - | (release ? CAN_CMR_TXRQST : 0) - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[1].CRR = 1 + msgobj; - - while (CAN->sMsgObj[1].CRR & CAN_CRR_BUSY); - - if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) - { - /* standard ID */ - pCanMsg->IdType = CAN_STD_ID; - pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; - } - else - { - /* extended ID */ - pCanMsg->IdType = CAN_EXT_ID; - pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF) | ((u32)CAN->sMsgObj[1].A1R << 11) | (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); - } - - pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; - - pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; - pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); - pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; - pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); - pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; - pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); - pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; - pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); - - return 1; -} - -/******************************************************************************* -* Function Name : CAN_WaitEndOfTx -* Description : Wait until current transmission is finished -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_WaitEndOfTx(void) -{ - while ((CAN->SR & CAN_SR_TXOK) == 0); - CAN->SR &= ~CAN_SR_TXOK; -} - -/******************************************************************************* -* Function Name : CAN_BasicSendMessage -* Description : Start transmission of a message in BASIC mode -* Input 1 : pointer to the message structure containing data to transmit -* Output : None -* Return : 1 if transmission was OK, else 0 -* Note : CAN must be in BASIC mode -*******************************************************************************/ -u32 CAN_BasicSendMessage(canmsg* pCanMsg) -{ - /* clear NewDat bit in IF2 to detect next reception */ - CAN->sMsgObj[1].MCR &= ~CAN_MCR_NEWDAT; - - CAN->SR &= ~CAN_SR_TXOK; - - CAN->sMsgObj[0].CMR = CAN_CMR_WRRD - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if (pCanMsg->IdType == CAN_STD_ID) - { - /* standard ID */ - CAN->sMsgObj[0].A1R = 0; - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); - } - else - { - /* extended ID */ - CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); - } - - CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFCF0) | pCanMsg->Dlc; - - CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; - CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; - CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; - CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; - - /* request transmission */ - CAN->sMsgObj[0].CRR = CAN_CRR_BUSY | (1 + 0); - - return 1; -} - -/******************************************************************************* -* Function Name : CAN_BasicReceiveMessage -* Description : Get the message in BASIC mode, if received -* Input 1 : pointer to the message structure where received data is stored -* Output : None -* Return : 1 if reception was OK, else 0 (no message pending) -* Note : CAN must be in BASIC mode -*******************************************************************************/ -u32 CAN_BasicReceiveMessage(canmsg* pCanMsg) -{ - if ((CAN->sMsgObj[1].MCR & CAN_MCR_NEWDAT) == 0) - return 0; - - CAN->SR &= ~CAN_SR_RXOK; - - CAN->sMsgObj[1].CMR = CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) - { - /* standard ID */ - pCanMsg->IdType = CAN_STD_ID; - pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; - } - else - { - /* extended ID */ - pCanMsg->IdType = CAN_EXT_ID; - pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF) | ((u32)CAN->sMsgObj[1].A1R << 11) | (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); - } - - pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; - - pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; - pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); - pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; - pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); - pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; - pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); - pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; - pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); - - return 1; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/eic.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/eic.c deleted file mode 100644 index 42a2be7cf..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/eic.c +++ /dev/null @@ -1,91 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : eic.c -* Author : MCD Application Team -* Date First Issued : 06/25/2003 -* Description : This file provides all the EIC software functions -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "eic.h" - -/******************************************************************************* -* Function Name : EIC_Init -* Description : Initialise the EIC using the load PC instruction -* (PC = PC +offset) -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void EIC_Init(void) -{ - extern u32 T0TIMI_Addr; - u8 bCounter; - u32 dOffset=((u32)&T0TIMI_Addr); - - /* Disable FIQ and IRQ interrupts */ - EIC->ICR = 0x00000000; - - /* Disable all channels interrupts */ - EIC->IER = 0x00000000; - - /* Clear all pending bits */ - EIC->IPR = 0xFFFFFFFF; - - /* Disable all FIQ channels interrupts and clear FIQ */ - EIC->FIR = 0x0000000C; - - /* channels pending bits */ - /* Ste the current priority level to zero */ - EIC->CIPR = 0x00000000; - - /* IVR = high half of load PC instruction */ - EIC->IVR = 0xE59F0000; - - dOffset = (dOffset+0x00007E0)<<16; - - /* Initialize SIRn registers */ - for(bCounter=0; bCounter<32; bCounter++) - { - EIC->SIR[bCounter] = dOffset|0xF0000000; - dOffset += 0x00000004 << 16; - } -} - -/******************************************************************************* -* Function Name : EIC_CurrentPriorityLevelConfig -* Description : Change the current priority level of the srved IRQ routine -* Input 1 : New priority -* Output : None -* Return : None -*******************************************************************************/ -void EIC_CurrentPriorityLevelConfig(u8 NewPriorityLevel) -{ - u32 dVal; - - /* Save ICR content */ - dVal = EIC->ICR; - - /* Disable IRQ interrupts. */ - EIC->ICR &= ~0x0001; - - /* Change the current priority */ - EIC->CIPR = NewPriorityLevel; - - /* Restore ICR content */ - EIC->ICR = dVal; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/emi.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/emi.c deleted file mode 100644 index f82f588c7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/emi.c +++ /dev/null @@ -1,25 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : emi.c -* Author : MCD Application Team -* Date First Issued : 08/08/2003 -* Description : This file provides all the EMI software functions -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "emi.h" - - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/flash.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/flash.c deleted file mode 100644 index a916f4ba4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/flash.c +++ /dev/null @@ -1,374 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : flash.c -* Author : MCD Application Team -* Date First Issued : 07/28/2003 -* Description : This file provides all the Flash software functions -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "flash.h" - -/******************************************************************************* -* Function Name : FLASH_Init -* Description : Initialise the Flash registers to their default values. -* Input : None. -* Return : None. -*******************************************************************************/ -void FLASH_Init(void) -{ -/* Reset Flash Control Registers */ - FLASHR->CR0 = 0x00000000; - FLASHR->CR1 = 0x00000000; -/* Reset Flash Data Registers */ - FLASHR->DR0 = 0xFFFFFFFF; - FLASHR->DR1 = 0xFFFFFFFF; -/* Reset Flash Error Register */ - FLASHR->ER = 0x00000000; -} - -/******************************************************************************* -* Function Name : FLASH_WordWrite -* Description : Writes a Word in the Flash. -* Input 1 : Address of the Destination. -* Input 2 : Word to program at Address. -* Return : None. -*******************************************************************************/ -void FLASH_WordWrite(u32 XtargetAdd, u32 Xdata) -{ - /* Wait until another operation going on is completed */ - FLASH_WaitForLastTask(); - /* Set the Word Programming bit 'WPG' in the CR0 Reg */ - FLASHR->CR0 |= FLASH_WPG_Mask; - /* Load the destination address in AR */ - FLASHR->AR = XtargetAdd; - /* Load DATA to be programmed in DR0 */ - FLASHR->DR0 = Xdata; - /* Set the Write Mode Start bit 'WMS' in the CR0 Reg to Start Write Operation */ - FLASHR->CR0 |= FLASH_WMS_Mask; - /* Wait until the write operation is completed */ - FLASH_WaitForLastTask(); -} - -/******************************************************************************* -* Function Name : FLASH_DWordWrite -* Description : Writes Double Word to the Flash. -* Input 1 : Address of the Destination. -* Input 2 : Word 1 to program. -* Input 3 : Word 2 to program. -* Return : None. -*******************************************************************************/ -void FLASH_DWordWrite(u32 XtargetAdd, u32 Xdata0, u32 Xdata1) -{ - /* Wait until another operation going on is completed */ - FLASH_WaitForLastTask(); - /* set the Double Word Programming bit 'DWPG' in the CR0 Reg */ - FLASHR->CR0 |= FLASH_DWPG_Mask; - /* Load the destination address in AR */ - FLASHR->AR = XtargetAdd; - /* Load DATA0 in DR0 Reg */ - FLASHR->DR0 = Xdata0; - /* Load DATA1 in DR1 Reg */ - FLASHR->DR1 = Xdata1; - /* Set the Write Mode Start bit 'WMS' in the CR0 Reg to Start Write Operation */ - FLASHR->CR0 |= FLASH_WMS_Mask; - /* Wait until the write operation is completed */ - FLASH_WaitForLastTask(); -} - -/******************************************************************************* -* Function Name : FLASH_SectorErase -* Description : Erases a Flash sector. -* Input 1 : Sectors to be Erased. -* Return : None. -*******************************************************************************/ -void FLASH_SectorErase(u32 Xsectors) -{ - /* Wait until another operation going on is completed */ - FLASH_WaitForLastTask(); - /* Set the Sector Erase flag 'SER' in the CRO reg */ - FLASHR->CR0 |= FLASH_SER_Mask; - /* Select in the CR1 register the Sectors to be erased */ - FLASHR->CR1 |= Xsectors; - /* Set the Write Mode Start bit 'WMS' in the CR0 Reg to Start Erase Operation */ - FLASHR->CR0 |= FLASH_WMS_Mask; - /* Wait until the erase operation is completed */ - FLASH_WaitForLastTask(); -} -/******************************************************************************* -* Function Name : FLASH_Suspend -* Description : Suspends the current program or erase operation. -* Input 1 : None. -* Return : Flash CR0 register content. -*******************************************************************************/ -u32 FLASH_Suspend(void) -{ - u32 temp; - /* Save the CR0 Content */ - temp = FLASHR->CR0; - /* Set The suspend Bit 'SUSP' in the CR0 register */ - FLASHR->CR0 |= FLASH_SUSP_Mask; - /* Wait until the flash controller acknowledges the suspend of the current - operation */ - FLASH_WaitForLastTask(); - return temp; -} - -/******************************************************************************* -* Function Name : FLASH_Resume -* Description : Resume a Suspended program or erase operation. -* Input 1 : The operation to be resumed. -* Return : None. -*******************************************************************************/ -void FLASH_Resume(u32 FLASH_LastOperation) -{ - /* Clear The suspend Bit 'SUSP' in the FRC0 register */ - FLASHR->CR0 &= ~FLASH_SUSP_Mask; - /* Resume last operation */ - FLASHR->CR0 = FLASH_LastOperation & 0x7FFFFFFF; - /* Set write mode bit */ - FLASHR->CR0 |= FLASH_WMS_Mask; -} - -/******************************************************************************* -* Function Name : FLASH_WordRead -* Description : Read a single word from the flash -* Input 1 : Source Address -* Return : Word -*******************************************************************************/ -u32 FLASH_WordRead(u32 FLASH_SourceAdd) -{ - FLASH_WaitForLastTask(); - /* Reads the data from the specified Address */ - return *(u32 *)(FLASH_SourceAdd + 0x40000000); -} - -/******************************************************************************* -* Function Name : FLASH_FlagStatus -* Description : Returns the NewState of Flash flags -* Input : Xflag(FLASH_BSYA0, FLASH_BSYA1, FLASH_LOCK, FLASH_INTP -* FLASH_B0S, FLASH_B1S, FLASH_ERR, FLASH_ERER, FLASH_PGER, -* FLASH_10ER, FLASH_SEQER, FLASH_RESER, FLASH_WPF) -* Return : FlagStatus (SET or RESET). -*******************************************************************************/ -FlagStatus FLASH_FlagStatus(flashflags Xflag) -{ - FlagStatus TmpResult = RESET; - u8 TmpReg; - u8 TmpPos; - /* Get the Register Index */ - TmpReg = (Xflag & FLASH_Reg_Mask) >> 5; - /* Get the Flag Index */ - TmpPos = (Xflag & FLASH_Flag_Mask); - - switch(TmpReg) - { - case 0 : /* CR0 */ - { - /* Returns the status of the CR0[TmpPos] flag */ - TmpResult = (FLASHR->CR0 & (1<CR1 & (1<ER & (1<> 5; - TmpPos = (Xflag & FLASH_Flag_Mask); - - switch(TmpReg) - { - case 0 : /* CR0 */ - { - /* Clears the status of the CR0[TmpPos] flag */ - FLASHR->CR0 &= ~(1<CR1 &= ~(1<ER &= ~(1<CR0 |= FLASH_SPR_Mask; - /* Set the Register Address */ - FLASHR->AR = 0x4010DFB0; - /* Data to be programmed to the Protection Register */ - FLASHR->DR0 = ~Xsectors; - /* Set the WMS bit to Start the Sequence */ - FLASHR->CR0 |= FLASH_WMS_Mask; - } - /* Unprotect temporarily Flash sector */ - else - { - /* Set the Set protection Bit */ - FLASHR->CR0 |= FLASH_SPR_Mask; - /* Set the Register Address */ - FLASHR->AR = 0x4010DFB0; - /* Data to be programmed to the Protection Register */ - FLASHR->DR0 = FLASHPR->NVWPAR|Xsectors; - /* Set the WMS bit to Start the Sequence */ - FLASHR->CR0 |= FLASH_WMS_Mask; - } -} - -/******************************************************************************* -* Function Name : FLASH_PermanentDebugPrConfig -* Description : Configures the Debug Protection Bits -* Input 1 : NewState: ENABLE or DISABLE. -* Return : None. -*******************************************************************************/ -void FLASH_PermanentDebugPrConfig(FunctionalState NewState) -{ - u16 ProtectionLevel = FLASH_ProtectionLevel(); - - /* Enable permanent Debug protection */ - if (NewState == ENABLE) - { - /* If this is the first time that the debug protection is enabled:Reset - the DBGP bit in the NVAPR0 register */ - if(!ProtectionLevel) - { - /* Set the Set protection Bit */ - FLASHR->CR0 |= FLASH_SPR_Mask; - /* Set the Register Address */ - FLASHR->AR = 0x4010DFB8; - /* Data to be programmed to the Protection Register NVAPR0 */ - FLASHR->DR0 = ~2; - /* Set the WMS bit to start the sequence */ - FLASHR->CR0 |= FLASH_WMS_Mask; - } - /* If this is not the first time that the debug protection is enabled: - use of NVAPR1 register */ - else - { - /* Set the Set protection Bit */ - FLASHR->CR0 |= FLASH_SPR_Mask; - /* Set the Register Address */ - FLASHR->AR = 0x4010DFBC; - /* Data to be programmed to the Protection Register NVAPR1(PEN bits) */ - FLASHR->DR0 =~(1<<(15+ProtectionLevel)); - /* Set the WMS bit to Start the Sequence */ - FLASHR->CR0 |= FLASH_WMS_Mask; - } - - } - /* Permanent debug unprotection: use of NVAPR1 register */ - else if(ProtectionLevel) - { - /* Set the Set protection Bit */ - FLASHR->CR0 |= FLASH_SPR_Mask; - /* Set the Register Address */ - FLASHR->AR = 0x4010DFBC; - /* Data to be programmed to the Protection Register NVAPR1(PDS bits)*/ - FLASHR->DR0 =~(1<<(ProtectionLevel-1)); - /* Set the WMS bit to Start the Sequence */ - FLASHR->CR0 |= FLASH_WMS_Mask; - } - -} - -/******************************************************************************* -* Function Name : FLASH_ProtectionLevel -* Description : If the flash is Debug protected, up to 16 unprotection/ -* protection cycles are possible using the NVAPR1 register. -* This routine returns the number of times of Debug unprotection. -* Input : None. -* Return : Number of times of Debug Protection/Unprotection(0..15) -* Example: if 5 is returned, this means that the flash was debug -* unprotected 5 times(using PDS bits)and debug protected 5 times -* (1 time:using DBGP bit & 4 times: using PEN bits. -*******************************************************************************/ -u16 FLASH_ProtectionLevel(void) -{ - u16 TmpBitIndex =0; - u16 ProtectionRegs; - - /* If DBGP = 1(Flash is Debug protected */ - if(FLASHPR->NVAPR0&2) - TmpBitIndex=0; - - /*If DBGP = 0 (Flash is not Debug protected */ - else - TmpBitIndex=1; - ProtectionRegs=~(FLASHPR->NVAPR1>>16); - - while (((ProtectionRegs) != 0) && (TmpBitIndex < 16)) - { - ProtectionRegs = ProtectionRegs >> 1 ; - TmpBitIndex++; - } - return TmpBitIndex; -} -/******************************************************************************* -* Function Name : FLASH_WaitForLastTask -* Description : Waits for the end of last task on a Flash Bank. -* Input 1 : None. -* Return : None. -*******************************************************************************/ -void FLASH_WaitForLastTask(void) -{ - while (FLASHR->CR0&0x16); -} - -/*******************(C)COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/gpio.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/gpio.c deleted file mode 100644 index ec3ac5c5b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/gpio.c +++ /dev/null @@ -1,117 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : gpio.c -* Author : MCD Application Team -* Date First Issued : 06/08/2003 -* Description : This file provides all the GPIO software functions -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "gpio.h" - -/******************************************************************************* -* Function Name : GPIO_Config -* Description : Configure the GPIO port pins. -* Input 1 : GPIOx (x can be 0,1 or 2) the desired port. -* Input 2 : Port_Pins : pins placements. -* Input 3 : Pins Mode(GPIO_HI_AIN_TRI,GPIO_IN_TRI_TTL,GPIO_IN_TRI_CMOS, -* GPIO_IPUPD_WP,GPIO_OUT_OD,GPIO_OUT_PP,GPIO_AF_OD,GPIO_AF_PP). -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_Config (GPIO_TypeDef *GPIOx, u16 Port_Pins, GpioPinMode_TypeDef GPIO_Mode) -{ - switch (GPIO_Mode) - { - case GPIO_HI_AIN_TRI: - GPIOx->PC0&=~Port_Pins; - GPIOx->PC1&=~Port_Pins; - GPIOx->PC2&=~Port_Pins; - break; - - case GPIO_IN_TRI_TTL: - GPIOx->PC0|=Port_Pins; - GPIOx->PC1&=~Port_Pins; - GPIOx->PC2&=~Port_Pins; - break; - - case GPIO_IN_TRI_CMOS: - GPIOx->PC0&=~Port_Pins; - GPIOx->PC1|=Port_Pins; - GPIOx->PC2&=~Port_Pins; - break; - - case GPIO_IPUPD_WP: - GPIOx->PC0|=Port_Pins; - GPIOx->PC1|=Port_Pins; - GPIOx->PC2&=~Port_Pins; - break; - - case GPIO_OUT_OD: - GPIOx->PC0&=~Port_Pins; - GPIOx->PC1&=~Port_Pins; - GPIOx->PC2|=Port_Pins; - break; - - case GPIO_OUT_PP: - GPIOx->PC0|=Port_Pins; - GPIOx->PC1&=~Port_Pins; - GPIOx->PC2|=Port_Pins; - break; - - case GPIO_AF_OD: - GPIOx->PC0&=~Port_Pins; - GPIOx->PC1|=Port_Pins; - GPIOx->PC2|=Port_Pins; - break; - - case GPIO_AF_PP: - GPIOx->PC0|=Port_Pins; - GPIOx->PC1|=Port_Pins; - GPIOx->PC2|=Port_Pins; - break; - } -} - -/******************************************************************************* -* Function Name : GPIO_BitWrite -* Description : Set or reset the selected port pin. -* Input 1 : Selected GPIO port(GPIO1, GPIO1, GPIO2). -* Input 2 : Pin number. -* Input 3 : bit value. -* Output : None -* Return : None. -*******************************************************************************/ -void GPIO_BitWrite(GPIO_TypeDef *GPIOx, u8 Port_Pin, u8 Port_Val) -{ - if (Port_Val&0x01) GPIOx->PD |= 1<PD &= ~(1<PD = Port_Byte ? (GPIOx->PD&0x00FF) | ((u16)Port_Val<<8) - : (GPIOx->PD&0xFF00) | Port_Val; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/i2c.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/i2c.c deleted file mode 100644 index be67a2420..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/i2c.c +++ /dev/null @@ -1,375 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : i2c.c -* Author : MCD Application Team -* Date First Issued : 09/05/2003 -* Description : This file provides Code sources I2C functions -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "i2c.h" -#include "rccu.h" -#include - -/******************************************************************************* -* Function Name : I2C_Init -* Description : Initializes I2C peripheral control and registers to their -* default reset values. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : None. -*******************************************************************************/ -void I2C_Init (I2C_TypeDef *I2Cx) -{ - /* Initialize all the register of the specified I2C passed as parameter */ - I2Cx->CR=0x0; - I2Cx->CCR=0x0; - I2Cx->ECCR=0x0; - I2Cx->OAR1=0x0; - I2Cx->OAR2=0x0; - (void)I2Cx->SR1; - (void)I2Cx->SR2; - I2Cx->DR=0x0; -} - -/******************************************************************************* -* Function Name : I2C_OnOffConfig -* Description : Enables or disables I2C peripheral. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -void I2C_OnOffConfig (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - /* Enable the I2C selected by setting twice the PE bit on the CR register */ - I2Cx->CR |= I2C_PESET_Mask; - I2Cx->CR |= I2C_PESET_Mask; - } - else - /* Disable the I2C selected */ - I2Cx->CR &= ~I2C_PESET_Mask; -} - -/******************************************************************************* -* Function Name : I2C_FlagStatus -* Description : Checks whether any I2C Flag is set or not. -* Input : I2Cx ( I2C0 or I2C1 ) -* Access(DIRECT or INDIRECT) -* Flag : the flag to be read -* input 4: an (u8) variable needed in the case -* of the INDIRECT access -* Return : the NewState of the Flag (SET or RESET). -*******************************************************************************/ -FlagStatus I2C_FlagStatus (I2C_TypeDef *I2Cx, RegisterAccess Access, I2C_Flags Flag, ...) -{ - u32 Tmp=0; - - if (Access == DIRECT) - /* Store in Tmp variable the register where is located the flag */ - Tmp = I2C_GetStatus(I2Cx)&Flag; - else - { - va_list list; - /* Get the fourth register */ - va_start(list,Flag); - Tmp = va_arg(list,u32); - Tmp&=Flag; - } - /* Return the Flag NewState */ - return Tmp != 0 ? SET : RESET; -} - -/******************************************************************************* -* Function Name : I2C_FlagClear -* Description : Clears the I2C Flag passed as a parameter -* Input : I2Cx ( I2C0 or I2C1 ) -* Flag : the flag to be read -* input3: an (u8) parameter needed in the case that the flag -* to be cleared need a write in one register -* Return : None. -*******************************************************************************/ -void I2C_FlagClear (I2C_TypeDef *I2Cx, I2C_Flags Flag, ...) -{ - u8 Tmp = (u8)*((u32 *)&Flag + sizeof(Flag)); - - if (Flag==I2C_ADD10 || Flag==I2C_EVF || Flag==I2C_BERR || Flag==I2C_ARLO || - Flag==I2C_STOPF || Flag==I2C_AF || Flag==I2C_ENDAD) - - /* flags that need a read of the SR2 register to be cleared */ - { - /* Read the SR2 register */ - (void)I2Cx->SR2; - /* Two flags need a second step to be cleared */ - switch (Flag) - { - case I2C_ADD10: I2Cx->DR = Tmp; break; - case I2C_ENDAD: I2Cx->CR|=0x20; break; - } - } - else if (Flag==I2C_SB || Flag==I2C_ADSL || Flag==I2C_BTF || Flag==I2C_TRA) - /* flags that need a read of the SR1 register to be cleared */ - { - /* Read the SR1 register */ - (void)I2Cx->SR1; - if (Flag==I2C_SB) I2Cx->DR=Tmp; - else if (Flag==I2C_BTF || Flag==I2C_TRA) (void)I2Cx->DR; - } - else if ( Flag==I2C_M_SL || Flag==I2C_GCAL) - /*flags that need the PE bit to be cleared */ - { - I2C_OnOffConfig (I2Cx, DISABLE); - I2C_OnOffConfig (I2Cx, ENABLE); - } -} - -/******************************************************************************* -* Function Name : I2C_SpeedConfig -* Description : Selects I2C clock speed and configures its corresponding mode. -* Input : I2Cx ( I2C0 or I2C1 ) -* Clock: I2C expected clock in Hertz. -* Return : None. -*******************************************************************************/ -void I2C_SpeedConfig (I2C_TypeDef *I2Cx, u32 Clock) -{ - u32 FCLK=0; - u16 result=0; - /* Get the FCLK frequency using the RCCU library */ - FCLK = RCCU_FrequencyValue ( RCCU_FCLK ); - /* Test on speed mode */ - /* Update the CCR and ECCR are updated */ - if (Clock <=100000) - /* Standard mode selected */ - { - result = ((FCLK / Clock) - 7)/2; - /* Clear FM/SM bit */ - I2Cx->CCR=result &0x7f; - } - else if (Clock <=400000) - { - /* Fast mode selected */ - result = ((FCLK/Clock)-9)/3; - /* set FM/SM bit */ - I2Cx->CCR=result |0x80; - } - I2Cx->ECCR= result >>7; -} -/******************************************************************************* -* Function Name : I2C_AddressConfig -* Description : Defines the I2C bus address of the interface. -* Input : I2Cx ( I2C0 or I2C1 ). -* Address: an u16 parameter indicating the address -* of the interface. -* Mode (I2C_Mode10,I2C_Mode7). -* Return : None. -*******************************************************************************/ -void I2C_AddressConfig (I2C_TypeDef *I2Cx, u16 Address, I2C_Addressing Mode) -{ - /* Update OAR1 bit[7:1] by the lowest byte of address */ - I2Cx->OAR1 = (u8)Address; - - if (Mode == I2C_Mode10) - /* Update Add8 and add9 bits in OAR2 */ - I2Cx->OAR2 |= (Address & 0x0300)>>7; -} - -/******************************************************************************* -* Function Name : I2C_FCLKConfig -* Description : Configures frequency bits according to RCLK frequency. -* the selected I2C must be disabled -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : None. -*******************************************************************************/ -void I2C_FCLKConfig (I2C_TypeDef *I2Cx) -{ - u32 FCLK=0; - /* Get the FCLK frequency using the RCCU library */ - FCLK = RCCU_FrequencyValue ( RCCU_FCLK ); - /* Test the value of the FCLK and affect FR0,FR1&FR2 of the OAR2 register */ - if (FCLK > 5000000) - { - if (FCLK <10000000) - I2Cx->OAR2 |= 0x00; - else if (FCLK <16670000) - I2Cx->OAR2 |= 0x20; - else if (FCLK < 26670000) - I2Cx->OAR2 |= 0x40; - else if (FCLK <40000000) - I2Cx->OAR2 |= 0x60; - else if (FCLK < 53330000) - I2Cx->OAR2 |= 0x80; - else if (FCLK < 66000000) - I2Cx->OAR2 |= 0xA0; - else if (FCLK <80000000) - I2Cx->OAR2 |= 0xC0; - else if (FCLK <100000000) - I2Cx->OAR2 |= 0xE0; - } -} - -/******************************************************************************* -* Function Name : I2C_AddressSend -* Description : Transmits the address byte to select the slave device. -* Input : I2Cx ( I2C0 or I2C1 ) -* Address: an u16 parameter indicating the slave address -* Mode (I2C_Mode10,I2C_Mode7). -* Direction (I2C_RX,I2C_TX). -* Return : None. -********************************************************************************/ -void I2C_AddressSend (I2C_TypeDef *I2Cx, u16 Address, I2C_Addressing Mode, I2C_Direction Direction) -{ - if (Mode == I2C_Mode10 ) - /*10 bit addressing mode */ - { - /* Update the DR register by generated header */ - I2Cx->DR = ((Address>>7)|0xf0)&0xfe; - /* Wait till I2C_ADD10 flag is set */ - while ((I2Cx->SR1&0x40)==0); - /* clear I2C_ADD10 flag */ - (void)I2Cx->SR2; - I2Cx->DR=(u8)Address; - /* Test on the direction to define the read/write bit */ - if (Direction == I2C_RX) - { - /* Wait till I2C_ENDAD flag is set */ - while ((I2Cx->SR2&0x20)==0); - I2Cx->CR|=0x20; - /* Repeated START Generate */ - I2C_STARTGenerate (I2Cx, ENABLE); - /* Test on SB flag status */ - while ((I2Cx->SR1&0x01)==0); - I2Cx->DR = ((Address>>7)|0xf1); - } - } - else - /* 7 bit addressing mode */ - { - if (Direction == I2C_RX) Address|=0x01; else Address&=~0x01; - I2Cx->DR=(u8)Address; - } -} - -/******************************************************************************* -* Function Name : I2C_ByteSend -* Description : Send a single byte of data. -* Input : I2Cx ( I2C0 or I2C1 ) -* Data : the byte to be sent to the slave -* Return : None. -*******************************************************************************/ -void I2C_ByteSend (I2C_TypeDef *I2Cx, u8 Data) -{ - /* Write in the DR register the byte to be sent */ - I2Cx->DR = Data; -} - - -/******************************************************************************* -* Function Name : I2C_TransmissionStatus -* Description : Report the NewState of the transmission -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : I2C_Tx_Status :transmission status (I2C_TX_NO, I2C_TX_SB, -* I2C_TX_AF, I2C_TX_ARLO, I2C_TX_BERR,I2C_TX_ADD_OK, -* I2C_TX_DATA_OK,I2C_TX_ONGOING) -*******************************************************************************/ -I2C_Tx_Status I2C_TransmissionStatus (I2C_TypeDef *I2Cx) -{ - u8 SR1value=0; - u8 SR2value=0; - I2C_Tx_Status NewState = I2C_TX_NO; - - SR1value = I2Cx->SR1; - SR2value = I2Cx->SR2; - if ((I2Cx->SR1&0x10)==0) - NewState=I2C_TX_NO; - else if (I2Cx->SR1&0x01) - /* I2C_SB bit is set */ - NewState=I2C_TX_SB; - else if ((SR2value & 0x10)&&(I2Cx->CR&0x04)) - /* I2C_ACK &I2C_AF are both set */ - NewState=I2C_TX_AF; - else if (SR2value & 0x04) - /* I2C_ARLO is set in multimaster mode */ - NewState=I2C_TX_ARLO; - else if (SR2value & 0x02) - /* I2C_BERR bit is set */ - NewState=I2C_TX_BERR; - else if ((SR1value & 0x80)&& (I2Cx->SR2&0x20)) - /* I2C_EVF and I2C_ENDAD are both set */ - NewState=I2C_TX_ADD_OK; - else if ((I2Cx->SR1&0x20)&& (I2Cx->SR1&0x08)) - /* I2C_TRA and I2C_BTF are both set */ - NewState=I2C_TX_DATA_OK; - else - NewState=I2C_TX_ONGOING; - - return NewState; -} - -/******************************************************************************* -* Function Name : I2C_ByteReceive -* Description : Returns the received byte. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : the byte received -*******************************************************************************/ -u8 I2C_ByteReceive (I2C_TypeDef *I2Cx) -{ - /* Wait till I2C_BTF bit is set */ - while ((I2Cx->SR1 & 0x08)==0); - return I2Cx->DR; -} - - -/******************************************************************************* -* Function Name :I2C_ReceptionStatus -* Description : Report the reception NewState. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : I2C_Rx_Status:the NewState of the reception ( I2C_RX_NO, -* I2C_RX_SB,I2C_RX_AF,I2C_RX_ARLO,I2C_RX_BERR,I2C_RX_ADD_OK, -* I2C_RX_DATA_OK, I2C_RX_ONGOING) -*******************************************************************************/ -I2C_Rx_Status I2C_ReceptionStatus (I2C_TypeDef *I2Cx) -{ - u8 SR1value=0; - u8 SR2value=0; - I2C_Rx_Status NewState = I2C_RX_NO; - SR1value= I2Cx->SR1; - SR2value= I2Cx->SR2; - - if ((I2Cx->SR1&0x10) == 0) - NewState=I2C_RX_NO; - else if (I2Cx->SR1&0x01) - /* I2C_SB bit is set */ - NewState=I2C_RX_SB; - else if ((SR2value & 0x10) && (I2Cx->CR&0x04)) - /* I2C_ACK &I2C_AF are both set */ - NewState=I2C_RX_AF; - else if (SR2value & 0x04) - /* I2C_ARLO is set */ - NewState=I2C_RX_ARLO; - else if (SR2value & 0x02) - /* I2C_BERR bit is set */ - NewState=I2C_RX_BERR; - else if ((SR1value & 0x80) && (I2Cx->SR1&0x08)==0) - /* I2C_EVF is set & I2C_BTF is not set */ - NewState=I2C_RX_ADD_OK; - else if ((I2Cx->SR1&0x20)==0 && (I2Cx->SR1&0x08)) - /* I2C_TRA is cleared & I2C_BTF is set */ - NewState=I2C_RX_DATA_OK; - else - NewState=I2C_RX_ONGOING; - return NewState; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/71x_conf.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/71x_conf.h deleted file mode 100644 index 40bd033c5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/71x_conf.h +++ /dev/null @@ -1,73 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_conf.h -* Author : MCD Application Team -* Date First Issued : 16/05/2003 -* Description : Library configuration for the WDG example -******************************************************************************** -* History: -* 24/05/05 : V3.0 -* 30/11/04 : V2.0 -* 16/05/03 : Created -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __71x_CONF_H -#define __71x_CONF_H - -/* Comment the line below to put the library in release mode */ -//#define DEBUG - -#define inline static __inline - -//#define USE_SERIAL_PORT -//#define USE_UART0 - -/* Main Oscillator Frequency value = 16 Mhz */ -//#define RCCU_Main_Osc 16000000 - -/* Comment the lines below corresponding to unwanted peripherals */ -#define _ADC12 -#define _APB -#define _APB1 -#define _APB2 -#define _BSPI -#define _BSPI0 -#define _BSPI1 -#define _CAN -#define _EIC -#define _EMI -#define _FLASH -#define _GPIO -#define _GPIO0 -#define _GPIO1 -#define _GPIO2 -#define _I2C -#define _I2C0 -#define _I2C1 -#define _PCU -#define _RCCU -#define _RTC -#define _TIM -#define _TIM0 -#define _TIM1 -#define _TIM2 -#define _TIM3 -#define _UART -#define _UART0 -#define _UART1 -#define _UART2 -#define _UART3 -#define _USB -#define _WDG -#define _XTI -#define _IRQVectors - -#endif /* __71x_CONF_H */ - - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/71x_it.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/71x_it.h deleted file mode 100644 index ac0c76d52..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/71x_it.h +++ /dev/null @@ -1,63 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_it.h -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Interrupt handlers -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef _71x_IT_H -#define _71x_IT_H - -#include "71x_lib.h" - - -void Undefined_Handler (void); -void FIQ_Handler (void); -void SWI_Handler (void); -void Prefetch_Handler (void); -void Abort_Handler (void); -void T0TIMI_IRQHandler (void); -void FLASH_IRQHandler (void); -void RCCU_IRQHandler (void); -void RTC_IRQHandler (void); -void WDG_IRQHandler (void); -void XTI_IRQHandler (void); -void USBHP_IRQHandler (void); -void I2C0ITERR_IRQHandler(void); -void I2C1ITERR_IRQHandler(void); -void UART0_IRQHandler (void); -void UART1_IRQHandler (void); -void UART2_IRQHandler (void); -void UART3_IRQHandler (void); -void BSPI0_IRQHandler (void); -void BSPI1_IRQHandler (void); -void I2C0_IRQHandler (void); -void I2C1_IRQHandler (void); -void CAN_IRQHandler (void); -void ADC12_IRQHandler (void); -void T1TIMI_IRQHandler (void); -void T2TIMI_IRQHandler (void); -void T3TIMI_IRQHandler (void); -void HDLC_IRQHandler (void); -void USBLP_IRQHandler (void); -void T0TOI_IRQHandler (void); -void T0OC1_IRQHandler (void); -void T0OC2_IRQHandler (void); - -#endif /* _71x_IT_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/71x_lib.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/71x_lib.h deleted file mode 100644 index 2007a6625..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/71x_lib.h +++ /dev/null @@ -1,102 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_lib.h -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Global include for all peripherals -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __71x_LIB_H -#define __71x_LIB_H - -#include "71x_map.h" -#include "71x_conf.h" - - -#ifdef _ADC12 - #include "adc12.h" -#endif - -#ifdef _APB - #include "apb.h" -#endif - -#ifdef _BSPI - #include "bspi.h" -#endif - -#ifdef _CAN - #include "can.h" -#endif - -#ifdef _EIC - #include "eic.h" -#endif - -#ifdef _EMI - #include "emi.h" -#endif - -#ifdef _FLASH - #include "flash.h" -#endif - -#ifdef _GPIO - #include "gpio.h" -#endif - -#ifdef _I2C - #include "i2c.h" -#endif - -#ifdef _PCU - #include "pcu.h" -#endif - -#ifdef _RCCU - #include "rccu.h" -#endif - -#ifdef _RTC - #include "rtc.h" -#endif - -#ifdef _TIM - #include "tim.h" -#endif - -#ifdef _UART - #include "uart.h" -#endif - -#ifdef _USB -#endif - -#ifdef _WDG - #include "wdg.h" -#endif - -#ifdef _XTI - #include "xti.h" -#endif - - -#ifdef LIBDEBUG - void libdebug(void); -#endif - -#endif /* __71x_LIB_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/71x_map.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/71x_map.h deleted file mode 100644 index be35840e2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/71x_map.h +++ /dev/null @@ -1,612 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_map.h -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Peripherals memory mapping and registers structures -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __71x_MAP_H -#define __71x_MAP_H - -#ifndef EXT - #define EXT extern -#endif - -#include "71x_conf.h" -#include "71x_type.h" - - -/* IP registers structures */ - -typedef volatile struct -{ - vu16 DATA0; - vu16 EMPTY1[3]; - vu16 DATA1; - vu16 EMPTY2[3]; - vu16 DATA2; - vu16 EMPTY3[3]; - vu16 DATA3; - vu16 EMPTY4[3]; - vu16 CSR; - vu16 EMPTY5[7]; - vu16 CPR; -} ADC12_TypeDef; - -typedef volatile struct -{ - vu32 CKDIS; - vu32 SWRES; -} APB_TypeDef; - -typedef volatile struct -{ - vu16 RXR; - vu16 EMPTY1; - vu16 TXR; - vu16 EMPTY2; - vu16 CSR1; - vu16 EMPTY3; - vu16 CSR2; - vu16 EMPTY4; - vu16 CLK; -} BSPI_TypeDef; - -typedef volatile struct -{ - vu16 CRR; - vu16 EMPTY1; - vu16 CMR; - vu16 EMPTY2; - vu16 M1R; - vu16 EMPTY3; - vu16 M2R; - vu16 EMPTY4; - vu16 A1R; - vu16 EMPTY5; - vu16 A2R; - vu16 EMPTY6; - vu16 MCR; - vu16 EMPTY7; - vu16 DA1R; - vu16 EMPTY8; - vu16 DA2R; - vu16 EMPTY9; - vu16 DB1R; - vu16 EMPTY10; - vu16 DB2R; - vu16 EMPTY11[27]; -} CAN_MsgObj_TypeDef; - -typedef volatile struct -{ - vu16 CR; - vu16 EMPTY1; - vu16 SR; - vu16 EMPTY2; - vu16 ERR; - vu16 EMPTY3; - vu16 BTR; - vu16 EMPTY4; - vu16 IDR; - vu16 EMPTY5; - vu16 TESTR; - vu16 EMPTY6; - vu16 BRPR; - vu16 EMPTY7[3]; - CAN_MsgObj_TypeDef sMsgObj[2]; - vu16 EMPTY8[16]; - vu16 TR1R; - vu16 EMPTY9; - vu16 TR2R; - vu16 EMPTY10[13]; - vu16 ND1R; - vu16 EMPTY11; - vu16 ND2R; - vu16 EMPTY12[13]; - vu16 IP1R; - vu16 EMPTY13; - vu16 IP2R; - vu16 EMPTY14[13]; - vu16 MV1R; - vu16 EMPTY15; - vu16 MV2R; - vu16 EMPTY16; -} CAN_TypeDef; - -typedef volatile struct -{ - vu32 ICR; - vu32 CICR; - vu32 CIPR; - vu32 EMPTY1[3]; - vu32 IVR; - vu32 FIR; - vu32 IER; - vu32 EMPTY2[7]; - vu32 IPR; - vu32 EMPTY3[7]; - vu32 SIR[32]; -} EIC_TypeDef; - -typedef volatile struct -{ - vu16 BCON0; - vu16 EMPTY1; - vu16 BCON1; - vu16 EMPTY2; - vu16 BCON2; - vu16 EMPTY3; - vu16 BCON3; - vu16 EMPTY4; -} EMI_TypeDef; - -typedef volatile struct -{ - vu32 CR0; - vu32 CR1; - vu32 DR0; - vu32 DR1; - vu32 AR; - vu32 ER; -} FLASHR_TypeDef; - -typedef volatile struct -{ - vu32 NVWPAR; - vu32 EMPTY; - vu32 NVAPR0; - vu32 NVAPR1; -} FLASHPR_TypeDef; - -typedef volatile struct -{ - vu16 PC0; - vu16 EMPTY1; - vu16 PC1; - vu16 EMPTY2; - vu16 PC2; - vu16 EMPTY3; - vu16 PD; - vu16 EMPTY4; -} GPIO_TypeDef; - -typedef volatile struct -{ - vu8 CR; - vu8 EMPTY1[3]; - vu8 SR1; - vu8 EMPTY2[3]; - vu8 SR2; - vu8 EMPTY3[3]; - vu8 CCR; - vu8 EMPTY4[3]; - vu8 OAR1; - vu8 EMPTY5[3]; - vu8 OAR2; - vu8 EMPTY6[3]; - vu8 DR; - vu8 EMPTY7[3]; - vu8 ECCR; -} I2C_TypeDef; - -typedef volatile struct -{ - vu32 CCR; - vu32 EMPTY1; - vu32 CFR; - vu32 EMPTY2[3]; - vu32 PLL1CR; - vu32 PER; - vu32 SMR; -} RCCU_TypeDef; - -typedef volatile struct -{ - vu16 MDIVR; - vu16 EMPTY1; - vu16 PDIVR; - vu16 EMPTY2; - vu16 RSTR; - vu16 EMPTY3; - vu16 PLL2CR; - vu16 EMPTY4; - vu16 BOOTCR; - vu16 EMPTY5; - vu16 PWRCR; -} PCU_TypeDef; - -typedef volatile struct -{ - vu16 CRH; - vu16 EMPTY1; - vu16 CRL; - vu16 EMPTY2; - vu16 PRLH; - vu16 EMPTY3; - vu16 PRLL; - vu16 EMPTY4; - vu16 DIVH; - vu16 EMPTY5; - vu16 DIVL; - vu16 EMPTY6; - vu16 CNTH; - vu16 EMPTY7; - vu16 CNTL; - vu16 EMPTY8; - vu16 ALRH; - vu16 EMPTY9; - vu16 ALRL; -} RTC_TypeDef; - -typedef volatile struct -{ - vu16 ICAR; - vu16 EMPTY1; - vu16 ICBR; - vu16 EMPTY2; - vu16 OCAR; - vu16 EMPTY3; - vu16 OCBR; - vu16 EMPTY4; - vu16 CNTR; - vu16 EMPTY5; - vu16 CR1; - vu16 EMPTY6; - vu16 CR2; - vu16 EMPTY7; - vu16 SR; -} TIM_TypeDef; - -typedef volatile struct -{ - vu16 BR; - vu16 EMPTY1; - vu16 TxBUFR; - vu16 EMPTY2; - vu16 RxBUFR; - vu16 EMPTY3; - vu16 CR; - vu16 EMPTY4; - vu16 IER; - vu16 EMPTY5; - vu16 SR; - vu16 EMPTY6; - vu16 GTR; - vu16 EMPTY7; - vu16 TOR; - vu16 EMPTY8; - vu16 TxRSTR; - vu16 EMPTY9; - vu16 RxRSTR; -} UART_TypeDef; - -typedef volatile struct -{ - vu32 EP0R; - vu32 EP1R; - vu32 EP2R; - vu32 EP3R; - vu32 EP4R; - vu32 EP5R; - vu32 EP6R; - vu32 EP7R; - vu32 EP8R; - vu32 EP9R; - vu32 EP10R; - vu32 EP11R; - vu32 EP12R; - vu32 EP13R; - vu32 EP14R; - vu32 EP15R; - vu32 CNTR; - vu32 ISTR; - vu32 FNR; - vu32 DADDR; - vu32 BTABLE; -} USB_TypeDef; - -typedef volatile struct -{ - vu16 CR; - vu16 EMPTY1; - vu16 PR; - vu16 EMPTY2; - vu16 VR; - vu16 EMPTY3; - vu16 CNT; - vu16 EMPTY4; - vu16 SR; - vu16 EMPTY5; - vu16 MR; - vu16 EMPTY6; - vu16 KR; -} WDG_TypeDef; - -typedef volatile struct -{ - vu8 SR; - vu8 EMPTY1[7]; - vu8 CTRL; - vu8 EMPTY2[3]; - vu8 MRH; - vu8 EMPTY3[3]; - vu8 MRL; - vu8 EMPTY4[3]; - vu8 TRH; - vu8 EMPTY5[3]; - vu8 TRL; - vu8 EMPTY6[3]; - vu8 PRH; - vu8 EMPTY7[3]; - vu8 PRL; -} XTI_TypeDef; - - -/* IRQ vectors */ -typedef volatile struct -{ - vu32 T0TIMI_IRQHandler; - vu32 FLASH_IRQHandler; - vu32 RCCU_IRQHandler; - vu32 RTC_IRQHandler; - vu32 WDG_IRQHandler; - vu32 XTI_IRQHandler; - vu32 USBHP_IRQHandler; - vu32 I2C0ITERR_IRQHandler; - vu32 I2C1ITERR_IRQHandler; - vu32 UART0_IRQHandler; - vu32 UART1_IRQHandler; - vu32 UART2_IRQHandler; - vu32 UART3_IRQHandler; - vu32 BSPI0_IRQHandler; - vu32 BSPI1_IRQHandler; - vu32 I2C0_IRQHandler; - vu32 I2C1_IRQHandler; - vu32 CAN_IRQHandler; - vu32 ADC12_IRQHandler; - vu32 T1TIMI_IRQHandler; - vu32 T2TIMI_IRQHandler; - vu32 T3TIMI_IRQHandler; - vu32 EMPTY1[3]; - vu32 HDLC_IRQHandler; - vu32 USBLP_IRQHandler; - vu32 EMPTY2[2]; - vu32 T0TOI_IRQHandler; - vu32 T0OC1_IRQHandler; - vu32 T0OC2_IRQHandler; -} IRQVectors_TypeDef; - -/*===================================================================*/ - -/* Memory mapping */ - -#define RAM_BASE 0x20000000 - -#define FLASHR_BASE 0x40100000 -#define FLASHPR_BASE 0x4010DFB0 - -#define EXTMEM_BASE 0x60000000 -#define RCCU_BASE 0xA0000000 -#define PCU_BASE 0xA0000040 -#define APB1_BASE 0xC0000000 -#define APB2_BASE 0xE0000000 -#define EIC_BASE 0xFFFFF800 - -#define I2C0_BASE (APB1_BASE + 0x1000) -#define I2C1_BASE (APB1_BASE + 0x2000) -#define UART0_BASE (APB1_BASE + 0x4000) -#define UART1_BASE (APB1_BASE + 0x5000) -#define UART2_BASE (APB1_BASE + 0x6000) -#define UART3_BASE (APB1_BASE + 0x7000) -#define CAN_BASE (APB1_BASE + 0x9000) -#define BSPI0_BASE (APB1_BASE + 0xA000) -#define BSPI1_BASE (APB1_BASE + 0xB000) -#define USB_BASE (APB1_BASE + 0x8800) - -#define XTI_BASE (APB2_BASE + 0x101C) -#define GPIO0_BASE (APB2_BASE + 0x3000) -#define GPIO1_BASE (APB2_BASE + 0x4000) -#define GPIO2_BASE (APB2_BASE + 0x5000) -#define ADC12_BASE (APB2_BASE + 0x7000) -#define TIM0_BASE (APB2_BASE + 0x9000) -#define TIM1_BASE (APB2_BASE + 0xA000) -#define TIM2_BASE (APB2_BASE + 0xB000) -#define TIM3_BASE (APB2_BASE + 0xC000) -#define RTC_BASE (APB2_BASE + 0xD000) -#define WDG_BASE (APB2_BASE + 0xE000) - -#define EMI_BASE (EXTMEM_BASE + 0x0C000000) - -/*===================================================================*/ - -/* IP data access */ - -#ifndef LIBDEBUG - #define ADC12 ((ADC12_TypeDef *)ADC12_BASE) - - #define APB1 ((APB_TypeDef *)(APB1_BASE+0x10)) - #define APB2 ((APB_TypeDef *)(APB2_BASE+0x10)) - - #define BSPI0 ((BSPI_TypeDef *)BSPI0_BASE) - #define BSPI1 ((BSPI_TypeDef *)BSPI1_BASE) - - #define CAN ((CAN_TypeDef *)CAN_BASE) - - #define EIC ((EIC_TypeDef *)EIC_BASE) - - #define EMI ((EMI_TypeDef *)EMI_BASE) - - #define FLASHR ((FLASHR_TypeDef *)FLASHR_BASE) - #define FLASHPR ((FLASHPR_TypeDef *)FLASHPR_BASE) - - #define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE) - #define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE) - #define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE) - - #define I2C0 ((I2C_TypeDef *)I2C0_BASE) - #define I2C1 ((I2C_TypeDef *)I2C1_BASE) - - #define PCU ((PCU_TypeDef *)PCU_BASE) - - #define RCCU ((RCCU_TypeDef *)RCCU_BASE) - - #define RTC ((RTC_TypeDef *)RTC_BASE) - - #define TIM0 ((TIM_TypeDef *)TIM0_BASE) - #define TIM1 ((TIM_TypeDef *)TIM1_BASE) - #define TIM2 ((TIM_TypeDef *)TIM2_BASE) - #define TIM3 ((TIM_TypeDef *)TIM3_BASE) - - #define UART0 ((UART_TypeDef *)UART0_BASE) - #define UART1 ((UART_TypeDef *)UART1_BASE) - #define UART2 ((UART_TypeDef *)UART2_BASE) - #define UART3 ((UART_TypeDef *)UART3_BASE) - - #define USB ((USB_TypeDef *)USB_BASE) - - #define WDG ((WDG_TypeDef *)WDG_BASE) - - #define XTI ((XTI_TypeDef *)XTI_BASE) - - #define IRQVectors ((IRQVectors_TypeDef *)&T0TIMI_Addr) - -#else /* LIBDEBUG */ - - #ifdef _ADC12 - EXT ADC12_TypeDef *ADC12; - #endif - - #ifdef _APB - #ifdef _APB1 - EXT APB_TypeDef *APB1; - #endif - #ifdef _APB2 - EXT APB_TypeDef *APB2; - #endif - #endif - - #ifdef _BSPI - #ifdef _BSPI0 - EXT BSPI_TypeDef *BSPI0; - #endif - #ifdef _BSPI1 - EXT BSPI_TypeDef *BSPI1; - #endif - #endif - - #ifdef _CAN - EXT CAN_TypeDef *CAN; - #endif - - #ifdef _EIC - EXT EIC_TypeDef *EIC; - #endif - - #ifdef _EMI - EXT EMI_TypeDef *EMI; - #endif - - #ifdef _FLASH - EXT FLASHR_TypeDef *FLASHR; - EXT FLASHPR_TypeDef *FLASHPR; - #endif - - #ifdef _GPIO - #ifdef _GPIO0 - EXT GPIO_TypeDef *GPIO0; - #endif - #ifdef _GPIO1 - EXT GPIO_TypeDef *GPIO1; - #endif - #ifdef _GPIO2 - EXT GPIO_TypeDef *GPIO2; - #endif - #endif - - #ifdef _I2C - #ifdef _I2C0 - EXT I2C_TypeDef *I2C0; - #endif - #ifdef _I2C1 - EXT I2C_TypeDef *I2C1; - #endif - #endif - - #ifdef _PCU - EXT PCU_TypeDef *PCU; - #endif - - #ifdef _RCCU - EXT RCCU_TypeDef *RCCU; - #endif - - #ifdef _RTC - EXT RTC_TypeDef *RTC; - #endif - - #ifdef _TIM - #ifdef _TIM0 - EXT TIM_TypeDef *TIM0; - #endif - #ifdef _TIM1 - EXT TIM_TypeDef *TIM1; - #endif - #ifdef _TIM2 - EXT TIM_TypeDef *TIM2; - #endif - #ifdef _TIM3 - EXT TIM_TypeDef *TIM3; - #endif - #endif - - #ifdef _UART - #ifdef _UART0 - EXT UART_TypeDef *UART0; - #endif - #ifdef _UART1 - EXT UART_TypeDef *UART1; - #endif - #ifdef _UART2 - EXT UART_TypeDef *UART2; - #endif - #ifdef _UART3 - EXT UART_TypeDef *UART3; - #endif - #endif - - #ifdef _USB - EXT USB_TypeDef *USB; - #endif - - #ifdef _WDG - EXT WDG_TypeDef *WDG; - #endif - - #ifdef _XTI - EXT XTI_TypeDef *XTI; - #endif - - #ifdef _IRQVectors - EXT IRQVectors_TypeDef *IRQVectors; - #endif - -#endif /* LIBDEBUG */ - -#endif /* __71x_MAP_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/71x_type.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/71x_type.h deleted file mode 100644 index 7fcfb2a45..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/71x_type.h +++ /dev/null @@ -1,52 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_type.h -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Common data types -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef _71x_type_H -#define _71x_type_H - -typedef unsigned long u32; -typedef unsigned short u16; -typedef unsigned char u8; - -typedef signed long s32; -typedef signed short s16; -typedef signed char s8; - -typedef volatile unsigned long vu32; -typedef volatile unsigned short vu16; -typedef volatile unsigned char vu8; - -typedef volatile signed long vs32; -typedef volatile signed short vs16; -typedef volatile signed char vs8; - -/*===================================================================*/ -typedef enum { FALSE = 0, TRUE = !FALSE } bool; -/*===================================================================*/ -typedef enum { RESET = 0, SET = !RESET } FlagStatus; -/*===================================================================*/ -typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -/*===================================================================*/ -typedef enum { INDIRECT = 0, DIRECT = !INDIRECT} RegisterAccess; -/*===================================================================*/ - -#endif /* _71x_type_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/adc12.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/adc12.h deleted file mode 100644 index 741397a1d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/adc12.h +++ /dev/null @@ -1,186 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : adc12.h -* Author : MCD Application Team -* Date First Issued : 07/31/2003 -* Description : This file contains all the functions prototypes for the -* ADC12 software library. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef _ADC12_H -#define _ADC12_H - -#include "71x_map.h" -#include "rccu.h" - -/* --------------------ADC12 Conversion modes----------------------------------- */ -typedef enum -{ - ADC12_SINGLE, - ADC12_ROUND -} ADC12_Modes; - -/* --------------------ADC12 Channels------------------------------------------- */ -typedef enum -{ - ADC12_CHANNEL0 = 0x00, - ADC12_CHANNEL1 = 0x10, - ADC12_CHANNEL2 = 0x20, - ADC12_CHANNEL3 = 0x30 -} ADC12_Channels; - -/* --------------------ADC12 control status register flag----------------------- */ -typedef enum -{ - ADC12_DA0 = 0x0001, - ADC12_DA1 = 0x0002, - ADC12_DA2 = 0x0004, - ADC12_DA3 = 0x0008, - ADC12_OR = 0x2000 -} ADC12_Flags; - -/* Masks for the update of interrupt bit for channel n */ -#define ADC12_IT0_Mask 0x0100 -#define ADC12_IT1_Mask 0x0200 -#define ADC12_IT2_Mask 0x0400 -#define ADC12_IT3_Mask 0x0800 - -/* Mask for the update of all the interrupt bit in the CSR */ -#define ADC12_IT_Mask 0x0F00 - -/* Mask for Selecting mode */ -#define ADC12_Mode_Mask 0x0040 - -/* Mask for configuring the converter */ -#define ADC12_Start_Mask 0x0020 - -/******************************************************************************* -* Function Name : ADC12_Init -* Description : This routine is used to intialize the ADC12 registers to -* their reset values -* Input : None. -* Return : None. -*******************************************************************************/ -void ADC12_Init(void); - -/******************************************************************************* -* Function Name : ADC12_ConversionStart -* Description : This routine is used to launch the Conversion. -* Input : None -* Return : None -*******************************************************************************/ -inline void ADC12_ConversionStart (void) -{ - /* Set the ADCen bit of the BOOTCR register */ - PCU->BOOTCR |= ADC12_Start_Mask; -} - -/******************************************************************************* -* Function Name : ADC12_ConversionStop -* Description : This routine is used to disable the ADC12 cell. -* Input : None. -* Return : None. -*******************************************************************************/ -inline void ADC12_ConversionStop(void) -{ - /* Clear the ADCen bit of the BOOTCR register */ - PCU->BOOTCR &= ~ADC12_Start_Mask; -} - -/******************************************************************************* -* Function Name : ADC12_ModeConfig -* Description : This routine is used to select the mode of conversion. -* Input : ADC12_SINGLE: Single channel mode -* ADC12_ROUND : Round robin mode -* Return : None -*******************************************************************************/ -inline void ADC12_ModeConfig (ADC12_Modes ConversionMode) -{ - /* Select the mode of conversion and update the CSR */ - ADC12->CSR= ConversionMode == ADC12_SINGLE ? ADC12->CSR | ADC12_Mode_Mask :\ - ADC12->CSR & ~ADC12_Mode_Mask; -} - -/******************************************************************************* -* Function Name : ADC12_PrescalerConfig -* Description : This routine is used to configure the prescaler register. -* Input : Adc12_clk: Sampling frequency in Hz. -* Return : None. -*******************************************************************************/ -void ADC12_PrescalerConfig(u32 Adc12_clk); - -/******************************************************************************* -* Function Name : ADC12_ChannelSelect -* Description : This routine is used to select the channel passed as -* parameter to be converted. -* Input : ADC12_Channel: channel selected to be converted it may be -* ADC12_CHANNEL0 : select channel 0 -* ADC12_CHANNEL1 : select channel 1 -* ADC12_CHANNEL2 : select channel 2 -* ADC12_CHANNEL3 : select channel 3 -* Return : None -*******************************************************************************/ -inline void ADC12_ChannelSelect(ADC12_Channels ADC12_Channel) -{ - /* Update the CSR by the value of the selected channel */ - ADC12->CSR |= ADC12_Channel; -} - -/******************************************************************************* -* Function Name : ADC12_FlagStatus -* Description : This routine is used to test if the flag passed in parameter is set or not -* Input : ADC12_DA0 :Data Available on Channel 0 -* ADC12_DA1 :Data Available on Channel 1 -* ADC12_DA2 :Data Available on Channel 2 -* ADC12_DA3 :Data Available on Channel 3 -* ADC12_OR :Overrun -* Return : SET: if the flag is set -* RESET: if the flag is cleared -*******************************************************************************/ -inline FlagStatus ADC12_FlagStatus (ADC12_Flags flag) -{ - /* Test on the flag status and return set or RESET */ - return ADC12->CSR & flag ? SET : RESET; -} - -/******************************************************************************* -* Function Name : ADC12_ConversionValue -* Description : Read the conversion result from the data register. -* Input : ADC12_Channel :number of the register to read -* ADC12_CHANNEL0 : read the DATA0 register -* ADC12_CHANNEL1 : read the DATA1 register -* ADC12_CHANNEL2 : read the DATA2 register -* ADC12_CHANNEL3 : read the DATA3 register -* Return : the register value of the channel converted -*******************************************************************************/ -inline u16 ADC12_ConversionValue( ADC12_Channels ADC12_Channel) -{ - /* Clear the corespondent DA bit */ - ADC12->CSR &= ~(1<<(ADC12_Channel >> 4)); - - /* Only the 12 MSB of the DATAn Register are taken */ - return *(u16 *)(ADC12_BASE + (ADC12_Channel >> 1)) >> 4; -} - -/******************************************************************************* -* Function Name : ADC12_ITConfig -* Description : enable or disable the interruption -* Input : status=ENABLE=>enable interrupt -* status=DISABLE=>disable interrupt -* Return : None -*******************************************************************************/ -void ADC12_ITConfig (FunctionalState NewState); - -#endif /* _ADC12_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/apb.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/apb.h deleted file mode 100644 index 568f89914..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/apb.h +++ /dev/null @@ -1,90 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : apb.h -* Author : MCD Application Team -* Date First Issued : 05/30/2003 -* Description : This file contains all the functions prototypes for the -* APB bridge software library. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __APB_H -#define __APB_H - -#include "71x_map.h" - -/* APB1 Peripherals */ -#define I2C0_Periph 0x0000 -#define I2C1_Periph 0x0002 -#define UART0_Periph 0x0008 -#define UART1_Periph 0x0010 -#define UART2_Periph 0x0020 -#define UART3_Periph 0x0040 -#define USB_Periph 0x0080 -#define CAN_Periph 0x0100 -#define BSPI0_Periph 0x0200 -#define BSPI1_Periph 0x0400 -#define HDLC_Periph 0x2000 - -/* APB2 Peripherals */ -#define XTI_Periph 0x0000 -#define GPIO0_Periph 0x0004 -#define GPIO1_Periph 0x0008 -#define GPIO2_Periph 0x0010 -#define ADC12_Periph 0x0040 -#define CKOUT_Periph 0x0080 -#define TIM0_Periph 0x0100 -#define TIM1_Periph 0x0200 -#define TIM2_Periph 0x0400 -#define TIM3_Periph 0x0800 -#define RTC_Periph 0x1000 -#define EIC_Periph 0x4000 - -/******************************************************************************* -* Function Name : APB_ClockConfig -* Description : Enables/Disables the Clock gating for peripherals on the APB -* bridge passed in parameters. -* Input : APBx ( APB1 or APB2 ) -* NewState ENABLE or DISABLE -* NewValue (u16) -* Return : None -*******************************************************************************/ -inline void APB_ClockConfig ( APB_TypeDef *APBx, - FunctionalState NewState, - u16 NewValue ) -{ - if (NewState == ENABLE) APBx->CKDIS &= ~NewValue; - else APBx->CKDIS |= NewValue; -} - -/******************************************************************************* -* Function Name : APB_SwResetConfig -* Description : Enables/Disables the software Reset for peripherals on the APB -* bridge passed in parameters. -* Input : APBx ( APB1 or APB2 ) -* NewState ENABLE or DISABLE -* NewValue (u16) -* Return : None -*******************************************************************************/ -inline void APB_SwResetConfig ( APB_TypeDef *APBx, - FunctionalState NewState, - u16 NewValue ) -{ - if (NewState == ENABLE) APBx->SWRES |= NewValue; - else APBx->SWRES &= ~NewValue; -} - -#endif /* __APB_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/bspi.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/bspi.h deleted file mode 100644 index ede8552c9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/bspi.h +++ /dev/null @@ -1,325 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : bspi.h -* Author : MCD Application Team -* Date First Issued : 16/05/2003 -* Description : This file contains all the functions prototypes for the -* BSPI software library. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __BSPI_H -#define __BSPI_H - -#include "71x_map.h" - -typedef enum { - BSPI_BERIT = 0x80, - BSPI_RCIT = 0x10, - BSPI_ALL = 0x90 -} BSPI_ITS; - -typedef enum { - BSPI_BERR = 0x004, - BSPI_RFNE = 0x008, - BSPI_RFF = 0x010, - BSPI_ROFL = 0x020, - BSPI_TFE = 0x040, - BSPI_TUFL = 0x080, - BSPI_TFF = 0x100, - BSPI_TFNE = 0x200 -} BSPI_Flags; - -typedef enum { - BSPI_TR_FE, - BSPI_TR_UFL, - BSPI_TR_FF, - BSPI_TR_DIS -} BSPI_TR_IT_SRCS; - -typedef enum { - BSPI_RC_FNE, - BSPI_RC_FF, - BSPI_RC_DIS -} BSPI_RC_IR_SRCS; - -#define BSPI_PESET_Mask 0x01 -#define BSPI_DFIFO_Mask 0xFFFE -#define BSPI_CPHA_Mask 0x200 -#define BSPI_CPOL_Mask 0x100 -#define BSPI_BSPI0_Base 0xA000 -#define BSPI_BSPI1_Base 0xB000 - - -/******************************************************************************* -* Function Name : BSPI_BSPI0Conf -* Description : configure STR71x on BSPI0 mode. -* Input 2 : NewState: specifies the status of the BSPI -* : NewState value must be either ENABLE or DISABLE: -* : ENABLE: the specified BSPI0 peripheral will be enabled. -* : DISABLE: the specified BSPI0 peripheral will be disabled.. -* Output : SPI0 EN bit in BOOTCR. -* Return : None. -*******************************************************************************/ -inline void BSPI_BSPI0Conf(FunctionalState NewState) -{ - if (NewState == ENABLE) PCU->BOOTCR |= 0x04; else PCU->BOOTCR &= ~0x04; -} - -/******************************************************************************* -* Function Name : BSPI_Init -* Description : Initializes BSPI peripheral control and registers to their default reset values. -* Input : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Output : BSPI peripheral registers and BSPI global variables are initialized. -* Return : None. -*******************************************************************************/ -void BSPI_Init( BSPI_TypeDef *BSPIx); - -/******************************************************************************* -* Function Name : BSPI_Enable -* Description : Enables/disables the specified BSPI peripheral. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral to be enabled or disabled. -* Input 2 : NewState: specifies the status of the BSPI -* : NewState value must be either ENABLE or DISABLE: -* : ENABLE: the specified BSPI peripheral will be enabled. -* : DISABLE: the specified BSPI peripheral will be disabled. -* Output : BSPE bit in BSPCSR1. -* Return : None. -*******************************************************************************/ -inline void BSPI_Enable( BSPI_TypeDef *BSPIx, FunctionalState NewState) -{ - if (NewState == ENABLE) BSPIx->CSR1 |= BSPI_PESET_Mask; - else BSPIx->CSR1 &= ~BSPI_PESET_Mask; -} - -/******************************************************************************* -* Function Name : BSPI_MasterEnable -* Description : Configures the BSPI as a Master or a Slave. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : NewState: specifies whether configuring BSPI as master is enabled or disabled. -* : ENABLE: the specified BSPI will be configured as a master. -* : DISABLE: the specified BSPI will be configured as a slave. -* Output : MSTR bit in BSPCSR1 is modified register. -* Return : None. -*******************************************************************************/ -inline void BSPI_MasterEnable(BSPI_TypeDef *BSPIx, FunctionalState NewState) -{ - if (NewState == ENABLE) BSPIx->CSR1 |= 0x02; else BSPIx->CSR1 &= ~0x02; -} - -/******************************************************************************* -* Function Name : BSPI_TrItSrc. -* Description : Configures the transmit interrupt source. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : TrItSrc: specifies the transmit interrupt source. -* : Refer to the section Transmit Interrupt Sources for more details on the -* : allowed values of this parameter. -* Output : TIE bit in BSPCSR2 register. -* Return : None. -*******************************************************************************/ -void BSPI_TrItSrc(BSPI_TypeDef *BSPIx, BSPI_TR_IT_SRCS TrItSrc); - -/******************************************************************************* -* Function Name : BSPI_RcItSrc. -* Description : Configures the receive interrupt source. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : RcItSrc: specifies the source for the receive interrupt. -* : Refer to the section Receive Interrupt Sources for more details on the -* : allowed values of this parameter. -* Output : RIE bit in BSPCSR1 is register. -* Return : None. -*******************************************************************************/ -void BSPI_RcItSrc(BSPI_TypeDef *BSPIx, BSPI_RC_IR_SRCS RcItSrc); - -/******************************************************************************* -* Function Name : BSPI_TrFifoDepth -* Description : Configures BSPI transmission FIFO number of words. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI. -* Input 2 : TDepth:specifies the depth of the transmit FIFO. -* Output : TFE bit in BSPCSR2 register. -* Return : None. -*******************************************************************************/ -void BSPI_TrFifoDepth(BSPI_TypeDef *BSPIx, u8 TDepth); - -/******************************************************************************* -* Function Name : BSPI_RcFifoDepth -* Description : Configures BSPI reception FIFO number of words. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : RDepth:specifies the depth of the receive FIFO. -* Output : RFE bits [3:0] in BSPCSR1 register. -* Return : None. -*******************************************************************************/ -void BSPI_RcFifoDepth(BSPI_TypeDef *BSPIx, u8 RDepth); - -/******************************************************************************* -* Function Name : BSPI_8bLEn -* Description : Sets the word length of the receive FIFO and transmit data registers to either 8 or 16 bits. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI. -* Input 2 : status: specifies if the word length is 8 or 16 bits. -* : status value must be either ENABLE or DISABLE: -* : ENABLE: to enable setting the word length to 8 bits. -* : DISABLE: disables setting the word length to 8 bits: the wordlength will be configured to 16 bits. -* Output : WL bits in BSPCSR1 register. -* Return : None. -*******************************************************************************/ -inline void BSPI_8bLEn(BSPI_TypeDef *BSPIx, FunctionalState NewState) -{ - if (NewState == DISABLE) BSPIx->CSR1 |= 0x0400; else BSPIx->CSR1 &= ~0x0C00; -} - -/******************************************************************************* -* Function Name : BSPI_ClkFEdge -* Description : Enables capturing the first data sample on the first edge of SCK or on the second edge. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : NewState: specifies whether capturing the first data sample on the first edge of SCK is enabled or disabled. -* : status value must be either ENABLE or DISABLE. -* :DISABLE: to enable capturing the first data sample on the first edge of SCK. -* : ENABLE: to enable capturing the first data sample on the second edge of SCK. -* Output : CPHA bits in BSPCSR1 register. -* Return : None. -*******************************************************************************/ -inline void BSPI_ClkFEdge(BSPI_TypeDef *BSPIx, FunctionalState NewState) -{ - if (NewState == ENABLE) BSPIx->CSR1 |= BSPI_CPHA_Mask; - else BSPIx->CSR1&=~BSPI_CPHA_Mask; -} - -/******************************************************************************* -* Function Name : BSPI_ClkActiveHigh -* Description : Configures the clock to be active high or low. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : NewState: specifies whether the clock is active high or low. -* : status value must be ENABLE or DISABLE. -* : ENABLE: configures the clock to be active high. -* : DISABLE: confgures the clock to be active low. -* Output : CPOL bits in BSPCSR1 register. -* Return : None. -*******************************************************************************/ -inline void BSPI_ClkActiveHigh(BSPI_TypeDef *BSPIx, FunctionalState NewState) -{ - if (NewState == ENABLE) BSPIx->CSR1 |= BSPI_CPOL_Mask; - else BSPIx->CSR1 &= ~BSPI_CPOL_Mask; -} - -/******************************************************************************* -* Function Name : BSPI_FifoDisable -* Description : Configure the BSPI FIFO. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Output : DFIFO bit in BSPCSR2 register. -* Return : None. -*******************************************************************************/ -inline void BSPI_FifoDisable(BSPI_TypeDef *BSPIx) -{ - BSPIx->CSR2 |= 0x0001; -} - -/******************************************************************************* -* Function Name : BSPI_ClockDividerConfig -* Description : Configure BSPI clock divider -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI. -* Input 2 : Div: holds the value of the clock divider. -* Output : Div [7:0] bits in BSPCLK register. -* Return : None. -*******************************************************************************/ -inline void BSPI_ClockDividerConfig(BSPI_TypeDef *BSPIx, u8 Div) -{ - BSPIx->CLK = Div; -} - -/******************************************************************************* -* Function Name : BSPI_FlagStatus. -* Description : Check whether the specified BSPI Flag is set or not. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : flag: specifies the flag to see the status. -* : Refer to the section BSPI Flags for more details on the allowed values of this parameter. -* Output : None. -* Return : FlagStatus type -* : SET: if the tested flag is set. -* : RESET: if the corresponding flag is reset. -*******************************************************************************/ -inline FlagStatus BSPI_FlagStatus(BSPI_TypeDef *BSPIx, BSPI_Flags flag) -{ - return (BSPIx->CSR2 & flag) != 0 ? SET : RESET; -} - -/******************************************************************************* -* Function Name : BSPI_WordSend. -* Description : Transmit a single Word. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : holds the word which will be transmitted. -* Output : BSPTXR register. -* Return : None. -*******************************************************************************/ -inline void BSPI_WordSend(BSPI_TypeDef *BSPIx, u16 Data) -{ - if ((BSPIx->CSR1 & 0x0400) == 0) Data <<= 8; - BSPIx->TXR = Data; -} - -/******************************************************************************* -* Function Name : BSPI_BufferSend. -* Description : Transmits data from a buffer. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : PtrToBuffer is an u8 pointer to the first word of the buffer to be transmitted. -* Input 3 : NbOfWords parameter indicates the number of words saved in the buffer to be sent. -* Output : None. -* Return : None. -*******************************************************************************/ -void BSPI_BufferSend(BSPI_TypeDef *BSPIx, u8 *PtrToBuffer, u8 NbOfWords); - -/******************************************************************************* -* Function Name : BSPI_WordReceive. -* Description : Returns the recent received word. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Output : None. -* Return : The value of the received word. -*******************************************************************************/ -inline u16 BSPI_WordReceive(BSPI_TypeDef *BSPIx) -{ - return (BSPIx->CSR1 & 0x0400) == 0 ? BSPIx->RXR >> 8 : BSPIx->RXR; -} - -/******************************************************************************* -* Function Name : BSPI_BufferReceive. -* Description : Receives number of data words and stores them in user defined area. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : PtrToBuffer is an u8 pointer to the first word of the defined area to save the received buffer. -* Input 3 : NbOfWords parameter indicates the number of words to be received in the buffer. -* Output : None. -* Return : None. -*******************************************************************************/ -void BSPI_BufferReceive(BSPI_TypeDef *BSPIx, u8 *PtrToBuffer, u8 NbOfWords); - -/******************************************************************************* -* Function Name : BSPI_ItEnable. -* Description : Enable the specified interrupt. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : BSPI_IT: specifies the BSPI interrupt. -* : Refer to the section Interrupt Enable for more details on the allowed values of this parameter.. -* Input 3 : NewState: specified whether the BSPI interrupt is enabled or disabled. -* : status value must be either ENABLE or DISABLE. -* : ENABLE: to enable interrupt -* : DISABLE: to disable interrupt. -* Output : BSPCSR1 register. -* Return : None. -*******************************************************************************/ -inline void BSPI_ItEnable(BSPI_TypeDef *BSPIx, BSPI_ITS BSPI_IE, FunctionalState NewState) -{ - if (NewState == ENABLE) BSPIx->CSR1 |= BSPI_IE; else BSPIx->CSR1 &= ~BSPI_IE; -} - -#endif /* __BSPI_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/can.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/can.h deleted file mode 100644 index 3e8ab646c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/can.h +++ /dev/null @@ -1,407 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : can.h -* Author : MCD Application Team -* Date First Issued : 27/10/2003 -* Description : This file contains all the functions prototypes for the -* CAN bus software library. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __CAN_H -#define __CAN_H - -#include "71x_map.h" - -/* Standard bitrates available */ -enum -{ - CAN_BITRATE_100K, - CAN_BITRATE_125K, - CAN_BITRATE_250K, - CAN_BITRATE_500K, - CAN_BITRATE_1M -}; - -/* Control register */ -#define CAN_CR_TEST 0x0080 -#define CAN_CR_CCE 0x0040 -#define CAN_CR_DAR 0x0020 -#define CAN_CR_EIE 0x0008 -#define CAN_CR_SIE 0x0004 -#define CAN_CR_IE 0x0002 -#define CAN_CR_INIT 0x0001 - -/* Status register */ -#define CAN_SR_LEC 0x0007 -#define CAN_SR_TXOK 0x0008 -#define CAN_SR_RXOK 0x0010 -#define CAN_SR_EPASS 0x0020 -#define CAN_SR_EWARN 0x0040 -#define CAN_SR_BOFF 0x0080 - -/* Test register */ -#define CAN_TESTR_RX 0x0080 -#define CAN_TESTR_TX1 0x0040 -#define CAN_TESTR_TX0 0x0020 -#define CAN_TESTR_LBACK 0x0010 -#define CAN_TESTR_SILENT 0x0008 -#define CAN_TESTR_BASIC 0x0004 - -/* IFn / Command Request register */ -#define CAN_CRR_BUSY 0x8000 - -/* IFn / Command Mask register */ -#define CAN_CMR_WRRD 0x0080 -#define CAN_CMR_MASK 0x0040 -#define CAN_CMR_ARB 0x0020 -#define CAN_CMR_CONTROL 0x0010 -#define CAN_CMR_CLRINTPND 0x0008 -#define CAN_CMR_TXRQST 0x0004 -#define CAN_CMR_DATAA 0x0002 -#define CAN_CMR_DATAB 0x0001 - -/* IFn / Mask 2 register */ -#define CAN_M2R_MXTD 0x8000 -#define CAN_M2R_MDIR 0x4000 - -/* IFn / Arbitration 2 register */ -#define CAN_A2R_MSGVAL 0x8000 -#define CAN_A2R_XTD 0x4000 -#define CAN_A2R_DIR 0x2000 - -/* IFn / Message Control register */ -#define CAN_MCR_NEWDAT 0x8000 -#define CAN_MCR_MSGLST 0x4000 -#define CAN_MCR_INTPND 0x2000 -#define CAN_MCR_UMASK 0x1000 -#define CAN_MCR_TXIE 0x0800 -#define CAN_MCR_RXIE 0x0400 -#define CAN_MCR_RMTEN 0x0200 -#define CAN_MCR_TXRQST 0x0100 -#define CAN_MCR_EOB 0x0080 - - -/* Wake-up modes */ -enum -{ - CAN_WAKEUP_ON_EXT, - CAN_WAKEUP_ON_CAN -}; - - -/* CAN message structure */ -typedef struct -{ - u32 IdType; - vu32 Id; - vu8 Dlc; - vu8 Data[8]; -} canmsg; - -/* message ID types */ -enum -{ - CAN_STD_ID, - CAN_EXT_ID -}; - -/* message ID limits */ -#define CAN_LAST_STD_ID ((1<<11) - 1) -#define CAN_LAST_EXT_ID ((1L<<29) - 1) - -/******************************************************************************* -* Function Name : CAN_EnterInitMode -* Description : Switch the CAN into initialization mode -* Input 1 : any binary value formed from the CAN_CR_xxx defines -* Output : None -* Return : None -* Note : CAN_LeaveInitMode must be called when all is done -*******************************************************************************/ -inline void CAN_EnterInitMode(u8 mask) -{ - CAN->CR = mask | CAN_CR_INIT; - - /* reset the status */ - CAN->SR = 0; -} - -/******************************************************************************* -* Function Name : CAN_LeaveInitMode -* Description : Leave the initialization mode (switch into normal mode) -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -inline void CAN_LeaveInitMode(void) -{ - CAN->CR &= ~(CAN_CR_INIT | CAN_CR_CCE); -} - -/******************************************************************************* -* Function Name : CAN_EnterTestMode -* Description : Switch the CAN into test mode -* Input 1 : any binary value formed from the CAN_TESTR_xxx defines -* Output : None -* Return : None -* Note : CAN_LeaveTestMode must be called when all is done -*******************************************************************************/ -inline void CAN_EnterTestMode(u8 mask) -{ - CAN->CR |= CAN_CR_TEST; - CAN->TESTR |= mask; -} - -/******************************************************************************* -* Function Name : CAN_LeaveTestMode -* Description : Leave the current test mode (switch into normal mode) -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -inline void CAN_LeaveTestMode(void) -{ - CAN->CR |= CAN_CR_TEST; - CAN->TESTR &= ~(CAN_TESTR_LBACK | CAN_TESTR_SILENT | CAN_TESTR_BASIC); - CAN->CR &= ~CAN_CR_TEST; -} - -/******************************************************************************* -* Function Name : CAN_SetBitrate -* Description : Setup a standard CAN bitrate -* Input 1 : one of the CAN_BITRATE_xxx defines -* Output : None -* Return : None -* Note : CAN must be in initialization mode -*******************************************************************************/ -void CAN_SetBitrate(u32 bitrate); - -/******************************************************************************* -* Function Name : CAN_SetTiming -* Description : Setup the CAN timing with specific parameters -* Input 1 : Time Segment before the sample point position, from 1 to 16 -* Input 2 : Time Segment after the sample point position, from 1 to 8 -* Input 3 : Synchronisation Jump Width, from 1 to 4 -* Input 4 : Baud Rate Prescaler, from 1 to 1024 -* Output : None -* Return : None -* Note : CAN must be in initialization mode -*******************************************************************************/ -void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp); - -/******************************************************************************* -* Function Name : CAN_SleepRequest -* Description : Request the CAN cell to enter sleep mode -* Input 1 : CAN_WAKEUP_ON_EXT or CAN_WAKEUP_ON_CAN -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SleepRequest(u32 WakeupMode); - -/******************************************************************************* -* Function Name : CAN_SetUnusedMsgObj -* Description : Configure the message object as unused -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetUnusedMsgObj(u32 msgobj); - -/******************************************************************************* -* Function Name : CAN_SetTxMsgObj -* Description : Configure the message object as TX -* Input 1 : message object number, from 0 to 31 -* Input 2 : CAN_STD_ID or CAN_EXT_ID -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetTxMsgObj(u32 msgobj, u32 idType); - -/******************************************************************************* -* Function Name : CAN_SetRxMsgObj -* Description : Configure the message object as RX -* Input 1 : message object number, from 0 to 31 -* Input 2 : CAN_STD_ID or CAN_EXT_ID -* Input 3 : low part of the identifier range used for acceptance filtering -* Input 4 : high part of the identifier range used for acceptance filtering -* Input 5 : TRUE for a single receive object or a FIFO receive object that -* is the last one of the FIFO -* FALSE for a FIFO receive object that is not the last one -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast); - -/******************************************************************************* -* Function Name : CAN_InvalidateAllMsgObj -* Description : Configure all the message objects as unused -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_InvalidateAllMsgObj(void); - -/******************************************************************************* -* Function Name : CAN_Init -* Description : Initialize the CAN cell and set the bitrate -* Input 1 : any binary value formed from the CAN_CTL_xxx defines -* Input 2 : one of the CAN_BITRATE_xxx defines -* Output : None -* Return : None -*******************************************************************************/ -void CAN_Init(u8 mask, u32 bitrate); - -/******************************************************************************* -* Function Name : CAN_ReleaseMessage -* Description : Release the message object -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -*******************************************************************************/ -void CAN_ReleaseMessage(u32 msgobj); - -/******************************************************************************* -* Function Name : CAN_ReleaseTxMessage -* Description : Release the transmit message object -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -* Note : assume that message interface 0 is free -*******************************************************************************/ -inline void CAN_ReleaseTxMessage(u32 msgobj) -{ - CAN->sMsgObj[0].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQST; - CAN->sMsgObj[0].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_ReleaseRxMessage -* Description : Release the receive message object -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -* Note : assume that message interface 1 is free -*******************************************************************************/ -inline void CAN_ReleaseRxMessage(u32 msgobj) -{ - CAN->sMsgObj[1].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQST; - CAN->sMsgObj[1].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_SendMessage -* Description : Start transmission of a message -* Input 1 : message object number, from 0 to 31 -* Input 2 : pointer to the message structure containing data to transmit -* Output : None -* Return : 1 if transmission was OK, else 0 -*******************************************************************************/ -u32 CAN_SendMessage(u32 msgobj, canmsg* pCanMsg); - -/******************************************************************************* -* Function Name : CAN_ReceiveMessage -* Description : Get the message, if received -* Input 1 : message object number, from 0 to 31 -* Input 2 : if TRUE, the message object is released when getting the data -* if FALSE, the message object is not released -* Input 3 : pointer to the message structure where received data is stored -* Output : None -* Return : 1 if reception was OK, else 0 (no message pending) -*******************************************************************************/ -u32 CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg); - -/******************************************************************************* -* Function Name : CAN_WaitEndOfTx -* Description : Wait until current transmission is finished -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_WaitEndOfTx(void); - -/******************************************************************************* -* Function Name : CAN_BasicSendMessage -* Description : Start transmission of a message in BASIC mode -* Input 1 : pointer to the message structure containing data to transmit -* Output : None -* Return : 1 if transmission was OK, else 0 -* Note : CAN must be in BASIC mode -*******************************************************************************/ -u32 CAN_BasicSendMessage(canmsg* pCanMsg); - -/******************************************************************************* -* Function Name : CAN_BasicReceiveMessage -* Description : Get the message in BASIC mode, if received -* Input 1 : pointer to the message structure where received data is stored -* Output : None -* Return : 1 if reception was OK, else 0 (no message pending) -* Note : CAN must be in BASIC mode -*******************************************************************************/ -u32 CAN_BasicReceiveMessage(canmsg* pCanMsg); - -/******************************************************************************* -* Function Name : CAN_IsMessageWaiting -* Description : Test the waiting status of a received message -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : A non-zero value if the corresponding message object has -* received a message waiting to be copied, else 0 -*******************************************************************************/ -inline u32 CAN_IsMessageWaiting(u32 msgobj) -{ - return (msgobj < 16 ? CAN->ND1R & (1 << msgobj) : CAN->ND2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsTransmitRequested -* Description : Test the request status of a transmitted message -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : A non-zero value if the corresponding message is requested -* to transmit, else 0 -*******************************************************************************/ -inline u32 CAN_IsTransmitRequested(u32 msgobj) -{ - return (msgobj < 16 ? CAN->TR1R & (1 << msgobj) : CAN->TR2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsInterruptPending -* Description : Test the interrupt status of a message object -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : A non-zero value if the corresponding message has an interrupt -* pending, else 0 -*******************************************************************************/ -inline u32 CAN_IsInterruptPending(u32 msgobj) -{ - return (msgobj < 16 ? CAN->IP1R & (1 << msgobj) : CAN->IP2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsObjectValid -* Description : Test the validity of a message object (ready to use) -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : A non-zero value if the corresponding message object is valid, -* else 0 -*******************************************************************************/ -inline u32 CAN_IsObjectValid(u32 msgobj) -{ - return (msgobj < 16 ? CAN->MV1R & (1 << msgobj) : CAN->MV2R & (1 << (msgobj-16))); -} - -#endif /* __CAN_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/eic.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/eic.h deleted file mode 100644 index c39f119bc..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/eic.h +++ /dev/null @@ -1,201 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : eic.h -* Author : MCD Application Team -* Date First Issued : 25/06/2003 -* Description : This file contains all the functions prototypes for the -* EIC software library. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __EIC_H -#define __EIC_H - -#include "71x_map.h" - -typedef enum -{ - T0TIMI_IRQChannel = 0, - FLASH_IRQChannel = 1, - RCCU_IRQChannel = 2, - RTC_IRQChannel = 3, - WDG_IRQChannel = 4, - XTI_IRQChannel = 5, - USBHP_IRQChannel = 6, - I2C0ITERR_IRQChannel = 7, - I2C1ITERR_IRQChannel = 8, - UART0_IRQChannel = 9, - UART1_IRQChannel = 10, - UART2_IRQChannel = 11, - UART3_IRQChannel = 12, - SPI0_IRQChannel = 13, - SPI1_IRQChannel = 14, - I2C0_IRQChannel = 15, - I2C1_IRQChannel = 16, - CAN_IRQChannel = 17, - ADC_IRQChannel = 18, - T1TIMI_IRQChannel = 19, - T2TIMI_IRQChannel = 20, - T3TIMI_IRQChannel = 21, - HDLC_IRQChannel = 25, - USBLP_IRQChannel = 26, - T0TOI_IRQChannel = 29, - T0OC1_IRQChannel = 30, - T0OC2_IRQChannel = 31 -} IRQChannel_TypeDef; - -typedef enum -{ - T0TIMI_FIQChannel = 0x00000001, - WDG_FIQChannel = 0x00000002, - WDGT0TIMI_FIQChannels = 0x00000003 -} FIQChannel_TypeDef; - -/******************************************************************************* -* Function Name : EIC_Init -* Description : Initialise the EIC using the load PC instruction -* (PC = PC +offset) -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void EIC_Init(void); - -/******************************************************************************* -* Function Name : EIC_IRQConfig -* Description : Enable or Disable IRQ interrupts -* Input 1 : New status : can be ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -inline void EIC_IRQConfig(FunctionalState NewState) -{ - if (NewState==ENABLE) EIC->ICR |= 0x0001; else EIC->ICR &= ~0x0001; -} - -/******************************************************************************* -* Function Name : EIC_FIQConfig -* Description : Enable or Disable FIQ interrupts -* Input 1 : New status : can be ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -inline void EIC_FIQConfig(FunctionalState NewState) -{ - if (NewState==ENABLE) EIC->ICR |= 0x0002; else EIC->ICR &= ~0x0002; -} - -/******************************************************************************* -* Function Name : EIC_IRQChannelConfig -* Description : Configure the IRQ Channel -* Input 1 : IRQ channel name -* Input 2 : Channel New status : can be ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -inline void EIC_IRQChannelConfig(IRQChannel_TypeDef IRQChannel, FunctionalState NewState) -{ - if (NewState==ENABLE) EIC->IER |= 0x0001 << IRQChannel; - else EIC->IER &= ~(0x0001 << IRQChannel); -} - -/******************************************************************************* -* Function Name : EIC_FIQChannelConfig -* Description : Configure the FIQ Channel -* Input 1 : FIQ channel name -* Input 2 : Channel New status : can be ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -inline void EIC_FIQChannelConfig(FIQChannel_TypeDef FIQChannel, - FunctionalState NewState) -{ - if (NewState==ENABLE) EIC->FIR |= FIQChannel; - else EIC->FIR &= ~FIQChannel; -} - -/******************************************************************************* -* Function Name : EIC_IRQChannelPriorityConfig -* Description : Configure the selected IRQ channel priority -* Input 1 : IRQ channel name -* Input 2 : IRQ channel priority -* Output : None -* Return : None -*******************************************************************************/ -inline void EIC_IRQChannelPriorityConfig(IRQChannel_TypeDef IRQChannel, u8 Priority) -{ - EIC->SIR[IRQChannel] = (EIC->SIR[IRQChannel]&0xFFFF0000) | (u16)Priority & 0x000F; -} - -/******************************************************************************* -* Function Name : EIC_CurrentPriorityLevelConfig -* Description : Change the current priority level of the srved IRQ routine -* Input 1 : New priority -* Output : None -* Return : None -*******************************************************************************/ -void EIC_CurrentPriorityLevelConfig(u8 NewPriorityLevel); - -/******************************************************************************* -* Function Name : EIC_CurrentPriorityLevelValue -* Description : Return the current priority level of the current served IRQ -* routine -* Input : None -* Output : None -* Return : The current priority level -*******************************************************************************/ -inline u8 EIC_CurrentPriorityLevelValue(void) -{ - return EIC->CIPR & 0xF; -} - -/******************************************************************************* -* Function Name : EIC_CurrentIRQChannelValue -* Description : Return the current served IRQ channel number -* Input 0 : None -* Output : None -* Return : The current served IRQ channel number -*******************************************************************************/ -inline IRQChannel_TypeDef EIC_CurrentIRQChannelValue(void) -{ - return (IRQChannel_TypeDef)(EIC->CICR & 0x1F); -} - -/******************************************************************************* -* Function Name : EIC_CurrentFIQChannelValue -* Description : Return the current served FIQ channel number -* Input : None -* Output : None -* Return : The current served FIQ channel number -*******************************************************************************/ -inline FIQChannel_TypeDef EIC_CurrentFIQChannelValue(void) -{ - return (FIQChannel_TypeDef)((EIC->FIR >> 2) & 0x0003); -} - -/******************************************************************************* -* Function Name : EIC_FIPendingBitClear -* Description : Clear the FIQ pending bit -* Input 1 : FIQ channel -* Output : None -* Return : None -*******************************************************************************/ -inline void EIC_FIQPendingBitClear(FIQChannel_TypeDef FIQChannel) -{ - EIC->FIR = (EIC->FIR & 0x0003) | (FIQChannel << 2); -} - -#endif /* __EIC_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/emi.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/emi.h deleted file mode 100644 index 2f9c2aac1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/emi.h +++ /dev/null @@ -1,53 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : emi.h -* Author : MCD Application Team -* Date First Issued : 08/08/2003 -* Description : This file contains all the functions prototypes for the -* EMI software library. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef _EMI_H -#define _EMI_H - -#include "71x_map.h" - -#define EMI_ENABLE 0x8000 -#define EMI_DISABLE 0x0000 -#define EMI_WAITSTATE(n) ((n) << 2) -#define EMI_SIZE_8 0x0000 -#define EMI_SIZE_16 0x0001 - -#define EMI_BANK0 EXTMEM_BASE -#define EMI_BANK1 (EXTMEM_BASE + 0x2000000) -#define EMI_BANK2 (EXTMEM_BASE + 0x4000000) -#define EMI_BANK3 (EXTMEM_BASE + 0x6000000) -/******************************************************************************* -* Function Name : EMI_Config -* Description : This routine is used, for each bank, to configure enabling, -* : cycle length and bus size. -* Input : Bank (u8) -* : Config (u16) -* Return : None -*******************************************************************************/ -inline void EMI_Config(u8 Bank, u16 Config) -{ - *(u16 *)(EMI_BASE + (4*Bank)) = Config; -} - -#endif /* _EMI_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/flash.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/flash.h deleted file mode 100644 index 8b5e383ee..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/flash.h +++ /dev/null @@ -1,256 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : flash.h -* Author : MCD Application Team -* Date First Issued : 28/07/2003 -* Description : This file contains all the functions prototypes for the -* Embedded Flash software library. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __FLASH_H -#define __FLASH_H - -#include "71x_map.h" - -#define FLASH_B0F0 0x00000001 -#define FLASH_B0F1 0x00000002 -#define FLASH_B0F2 0x00000004 -#define FLASH_B0F3 0x00000008 -#define FLASH_B0F4 0x00000010 -#define FLASH_B0F5 0x00000020 -#define FLASH_B0F6 0x00000040 -#define FLASH_B0F7 0x00000080 - -#define FLASH_B1F0 0x00010000 -#define FLASH_B1F1 0x00020000 - -#define FLASH_B0 (FLASH_B0F0 | FLASH_B0F1 | FLASH_B0F2 | FLASH_B0F3 | FLASH_B0F4 | FLASH_B0F5 | FLASH_B0F6 | FLASH_B0F7) -#define FLASH_B1 (FLASH_B1F0 | FLASH_B1F1) - -typedef enum -{ - FLASH_BANK0 = 0x1000000, - FLASH_BANK1 = 0x2000000 -} flashbanks; - -typedef enum -{ - FLASH_BSYA0 = 0x01, /* 000-00001 = 0000 0001 = 0x01 */ /* FLASH_CR0.1 */ - FLASH_BSYA1 = 0x02, /* 000-00010 = 0000 0010 = 0x02 */ /* FLASH_CR0.2 */ - FLASH_LOCK = 0x04, /* 000-00100 = 0000 0100 = 0x04 */ /* FLASH_CR0.4*/ - FLASH_INTP = 0x14, /* 000-10100 = 0001 0100 = 0x14 */ /* FLASH_CR0.20 */ - FLASH_B0S = 0x38, /* 001-11000 = 0011 1000 = 0x38 */ /* FLASH_CR1.24*/ - FLASH_B1S = 0x39, /* 001-11001 = 0011 1001 = 0x39 */ /* FLASH_CR1.25*/ - FLASH_ERR = 0xA0, /* 101-00000 = 1010 0000 = 0xA0 */ /* FLASH_ER.0*/ - FLASH_ERER = 0xA1, /* 101-00001 = 1010 0001 = 0xA1 */ /* FLASH_ER.1*/ - FLASH_PGER = 0xA2, /* 101-00010 = 1010 0010 = 0xA2 */ /* FLASH_ER.2*/ - FLASH_10ER = 0xA3, /* 101-00011 = 1010 0011 = 0xA3 */ /* FLASH_ER.3*/ - FLASH_SEQER = 0xA6, /* 101-00110 = 1010 0110 = 0xA6 */ /* FLASH_ER.6*/ - FLASH_RESER = 0xA7, /* 101-00111 = 1010 0111 = 0xA7 */ /* FLASH_ER.7*/ - FLASH_WPF = 0xA8 /* 101-01000 = 1010 1000 = 0xA8 */ /* FLASH_ER.8*/ -} flashflags; - -#define FLASH_WMS_Mask 0x80000000 -#define FLASH_SUSP_Mask 0x40000000 -#define FLASH_WPG_Mask 0x20000000 -#define FLASH_DWPG_Mask 0x10000000 -#define FLASH_SER_Mask 0x08000000 -#define FLASH_SPR_Mask 0x01000000 -#define FLASH_DBGP_Mask 0x00000002 -#define FLASH_ACCP_Mask 0x00000001 - -#define FLASH_Reg_Mask 0xE0 -#define FLASH_Flag_Mask 0x1F - -#define FLASH_INTM_Mask 0x00200000 - - -/******************************************************************************* -* Function Name : FLASH_Init -* Description : Initialise the Flash -* Input : None -* Return : None -*******************************************************************************/ -void FLASH_Init(void); - -/******************************************************************************* -* Function Name : FLASH_FlagStatus -* Description : Returns the NewState of Flash flags -* Input 1 : Flash Flag (FLASH_BSYA0, FLASH_BSYA1, FLASH_LOCK, FLASH_INTP -* FLASH_B0S, FLASH_B1S, FLASH_ERR, FLASH_ERER, FLASH_PGER, -* FLASH_10ER, FLASH_SEQER, FLASH_RESER, FLASH_WPF) -* Return : flagstatus (SET or RESET) -*******************************************************************************/ -FlagStatus FLASH_FlagStatus(flashflags Xflag); - -/******************************************************************************* -* Function Name : FLASH_WriteOpStatus -* Description : Checks the write operation status -* Input 1 : Flash bank (FLASH_BANK0 or FLASH_BANK1) -* Return : write operation status (Write operation is going on if -* FlagStatus is SET and write operation is completed if -* FlagStatus is RESET) -*******************************************************************************/ -inline FlagStatus FLASH_WriteOpStatus(flashbanks Xbank) -{ - return Xbank == FLASH_BANK0 ? FLASH_FlagStatus(FLASH_BSYA0) : FLASH_FlagStatus(FLASH_BSYA1); -} - -/******************************************************************************* -* Function Name : FLASH_WordWrite -* Description : Writes a Word to the Flash -* Input 1 : Destination Address -* Input 2 : Word to program -* Return : None -*******************************************************************************/ -void FLASH_WordWrite(u32 TargetAdd, u32 Data); - -/******************************************************************************* -* Function Name : FLASH_DWordWrite -* Description : Writes Double Word to the Flash -* Input 1 : Destination Address -* Input 2 : Word 1 To program -* Input 3 : Word 2 To program -* Return : None -*******************************************************************************/ -void FLASH_DWordWrite(u32 TargetAdd, u32 Data0, u32 Data1); - -/******************************************************************************* -* Function Name : FLASH_SectorErase -* Description : Erases a Flash sector -* Input 1 : Sectors to be Erased -* Return : None -*******************************************************************************/ -void FLASH_SectorErase(u32 Xsectors); - -/******************************************************************************* -* Function Name : FLASH_BankErase -* Description : Erases a Bank of the Flash -* Input 1 : Bank to be Erased -* Return : None -*******************************************************************************/ -inline void FLASH_BankErase(flashbanks Xbank) -{ - FLASH_SectorErase(Xbank == FLASH_BANK0 ? FLASH_B0 : FLASH_B1); -} - -/******************************************************************************* -* Function Name : FLASH_Suspend -* Description : Suspends the current program or erase operation -* Input 1 : None -* Return : Flash CR0 register -*******************************************************************************/ -u32 FLASH_Suspend(void); - -/******************************************************************************* -* Function Name : FLASH_Resume -* Description : Resume a Suspended program or erase operation -* Input 1 : The operation to be resumed -* Return : None -*******************************************************************************/ -void FLASH_Resume(u32 FLASH_LastOperation); - -/******************************************************************************* -* Function Name : FLASH_WordRead -* Description : Read a single word of the flash -* Input 1 : Source Address -* Return : Word -*******************************************************************************/ -u32 FLASH_WordRead(u32 FLASH_SourceAdd); - -/******************************************************************************* -* Function Name : FLASH_FlagClear -* Description : Clears a flash flag -* Input 1 : Flash Flag -* Return : None -*******************************************************************************/ -void FLASH_FlagClear(flashflags Xflag); - -/******************************************************************************* -* Function Name : FLASH_ITConfig -* Description : Enables or Disables the write-end interrupt -* Input 1 : FunctionalState(Enable, Disable) -* Return : None -*******************************************************************************/ -inline void FLASH_ITConfig(FunctionalState NewState) -{ - if (NewState == ENABLE) FLASHR->CR0 |= FLASH_INTM_Mask; - else FLASHR->CR0 &= ~FLASH_INTM_Mask; -} - -/******************************************************************************* -* Function Name : FLASH_ITStatus -* Description : Checks if the write-end interrupt is enabled or not -* Input 1 : None -* Return : Enable, Disable -*******************************************************************************/ -inline FunctionalState FLASH_ITStatus(void) -{ - return (FLASHR->CR0 & FLASH_INTM_Mask)==0 ? DISABLE : ENABLE; -} - -/******************************************************************************* -* Function Name : FLASH_ITClear -* Description : Clears an interrupt pending flag -* Input 1 : None -* Return : None -*******************************************************************************/ -inline void FLASH_ITClear(void) -{ - FLASHR->CR0 &= ~FLASH_INTM_Mask; -} - -/******************************************************************************* -* Function Name : FLASH_WritePrConfig -* Description : Enable Write protection or Disable temporarily Write -* protection of a flash sector. -* Input 1 : Flash Sector. -* Input 2 : Enable or disable Flash sector Write Protection. -* Return : None. -*******************************************************************************/ -void FLASH_WritePrConfig(u32 Xsectors, FunctionalState NewState); - -/******************************************************************************* -* Function Name : FLASH_PermanentDebugPrConfig -* Description : Configures the Debug Protection Bits -* Input 1 : NewState: ENABLE or DISABLE. -* Return : None. -*******************************************************************************/ -void FLASH_PermanentDebugPrConfig(FunctionalState NewState); - -/******************************************************************************* -* Function Name : FLASH_ProtectionLevel -* Description : If the flash is Debug protected, up to 16 unprotection/ -* protection cycles are possible using the NVAPR1 register. -* This routine returns the number of times of Debug unprotection. -* Input : None. -* Return : Number of times of Debug Protection/Unprotection(0..15) -* Example: if 5 is returned, this means that the flash was debug -* unprotected 5 times(using PDS bits)and debug protected 5 times -* (1 time:using DBGP bit & 4 times: using PEN bits). -*******************************************************************************/ -u16 FLASH_ProtectionLevel(void); - -/******************************************************************************* -* Function Name : FLASH_WaitForLastTask -* Description : Waits for the end of last task on a Flash Bank -* Input 1 : None -* Return : Nones -*******************************************************************************/ -void FLASH_WaitForLastTask(void); - -#endif /* __FLASH_H */ - -/*******************(C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/gpio.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/gpio.h deleted file mode 100644 index 4f6c13425..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/gpio.h +++ /dev/null @@ -1,129 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : gpio.h -* Author : MCD Application Team -* Date First Issued : 08/06/2003 -* Description : This file contains all the functions prototypes for the -* GPIO software library. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __GPIO_H -#define __GPIO_H - -#include "71x_map.h" - -typedef enum -{ - GPIO_HI_AIN_TRI, /*HIGH IMPEDANCE ANALOG INPUT TRISTATE*/ - GPIO_IN_TRI_TTL, /* INPUT TRISTATE TTL*/ - GPIO_IN_TRI_CMOS,/*INPUT TRSISTATE CMOS*/ - GPIO_IPUPD_WP, /*INPUT PULL UP/PULL DOWN WEAK PUSH PULL*/ - GPIO_OUT_OD, /* OUTPUT OPEN DRAIN*/ - GPIO_OUT_PP, /* OUTPUT PUSH PULL*/ - GPIO_AF_OD, /*ALTERNATE FUNCTION OPEN DRAIN */ - GPIO_AF_PP /* ALTERNATE FUNCTION PUSH PULL*/ -} GpioPinMode_TypeDef; - -#define GPIO_LSB 0x00 -#define GPIO_MSB 0x08 - -/******************************************************************************* -* Function Name : GPIO_Config -* Description : Configure the GPIO port pins. -* Input 1 : GPIOx (x can be 0,1 or 2) the desired port. -* Input 2 : Port_Pins : pins placements. -* Input 3 : Pins Mode(GPIO_HI_AIN_TRI,GPIO_IN_TRI_TTL,GPIO_IN_TRI_CMOS, -* GPIO_IPUPD_WP,GPIO_OUT_OD,GPIO_OUT_PP,GPIO_AF_OD,GPIO_AF_PP). -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_Config (GPIO_TypeDef *GPIOx, u16 Port_Pins, GpioPinMode_TypeDef GPIO_Mode); - -/******************************************************************************* -* Function Name : GPIO_BitRead -* Description : Read the desired port pin value. -* Input 1 : Selected GPIO port(GPIO1, GPIO1, GPIO2). -* Input 2 : Pin number. -* Output : None -* Return : The selected port pin value. -*******************************************************************************/ -inline u8 GPIO_BitRead(GPIO_TypeDef *GPIOx, u8 Port_Pin) -{ - return (GPIOx->PD >> Port_Pin) & 0x0001; -} - -/******************************************************************************* -* Function Name : GPIO_ByteRead -* Description : Read the desired port Byte value. -* Input 1 : Selected GPIO port(GPIO1, GPIO1, GPIO2). -* Input 2 : Port_Byte(GPIO_MSB or GPIO_LSB). -* Output : None -* Return : The GPIO_MSB or GPIO_LSB of the selected PD register. -*******************************************************************************/ -inline u8 GPIO_ByteRead(GPIO_TypeDef *GPIOx, u8 Port_Byte) -{ - return (u8)(GPIOx->PD >> Port_Byte); -} - -/******************************************************************************* -* Function Name : GPIO_WordRead -* Description : Read the desired port word value. -* Input 1 : Selected GPIO port(GPIO1, GPIO1, GPIO2). -* Output : None -* Return : The selected PD register value. -*******************************************************************************/ -inline u16 GPIO_WordRead(GPIO_TypeDef *GPIOx) -{ - return GPIOx->PD; -} - -/******************************************************************************* -* Function Name : GPIO_BitWrite -* Description : Set or reset the selected port pin. -* Input 1 : Selected GPIO port(GPIO1, GPIO1, GPIO2). -* Input 2 : Pin number. -* Input 3 : bit value. -* Output : None -* Return : None. -*******************************************************************************/ -void GPIO_BitWrite(GPIO_TypeDef *GPIOx, u8 Port_Pin, u8 Port_Val); - -/******************************************************************************* -* Function Name : GPIO_ByteWrite -* Description : Write byte value to the selected PD register. -* Input 1 : Selected GPIO port(GPIO1, GPIO1, GPIO2). -* Input 2 : Port_Byte (GPIO_MSB or GPIO_LSB). -* Input 3 : Byte value. -* Output : None -* Return : None. -*******************************************************************************/ -void GPIO_ByteWrite(GPIO_TypeDef *GPIOx, u8 Port_Byte, u8 Port_Val); - -/******************************************************************************* -* Function Name : GPIO_WordWrite -* Description : Write word value to the selected PD register. -* Input 1 : Selected GPIO port(GPIO1, GPIO1, GPIO2). -* Input 2 : Value. -* Output : None -* Return : None. -*******************************************************************************/ -inline void GPIO_WordWrite(GPIO_TypeDef *GPIOx, u16 Port_Val) -{ - GPIOx->PD = Port_Val; -} - -#endif /* __GPIO_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/i2c.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/i2c.h deleted file mode 100644 index 0cab7a369..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/i2c.h +++ /dev/null @@ -1,323 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : i2c.h -* Author : MCD Application Team -* Date First Issued : 05/09/2003 -* Description : This file provides prototypes of I2C functions -* and variable used in code sources -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __i2c_H -#define __i2c_H - -#include "71x_map.h" - -typedef enum -{ - I2C_CR = 0x00, - I2C_SR1 = 0x04, - I2C_SR2 = 0x08, - I2C_CCR = 0x0C, - I2C_OAR1 = 0x10, - I2C_OAR2 = 0x14, - I2C_DR = 0x18, - I2C_ECCR = 0x1C -} I2C_Registers; - -typedef enum -{ - I2C_Mode10, - I2C_Mode7 -} I2C_Addressing; - -typedef enum -{ - I2C_RX, - I2C_TX -} I2C_Direction; - -typedef enum -{ - I2C_SB = 0x00001, - I2C_M_SL = 0x00002, - I2C_ADSL = 0x00004, - I2C_BTF = 0x00008, - I2C_BUSY = 0x00010, - I2C_TRA = 0x00020, - I2C_ADD10 = 0x00040, - I2C_EVF = 0x00080, - I2C_GCAL = 0x00100, - I2C_BERR = 0x00200, - I2C_ARLO = 0x00400, - I2C_STOPF = 0x00800, - I2C_AF = 0x01000, - I2C_ENDAD = 0x02000, - I2C_STOP = 0x08000, - I2C_ACK = 0x10000, - I2C_START = 0x20000 -} I2C_Flags; - -typedef enum -{ - I2C_TX_NO, - I2C_TX_SB, - I2C_TX_AF, - I2C_TX_ARLO, - I2C_TX_BERR, - I2C_TX_ADD_OK, - I2C_TX_DATA_OK, - I2C_TX_ONGOING -} I2C_Tx_Status; - -typedef enum -{ - I2C_RX_NO, - I2C_RX_SB, - I2C_RX_AF, - I2C_RX_ARLO, - I2C_RX_BERR, - I2C_RX_ADD_OK, - I2C_RX_DATA_OK, - I2C_RX_ONGOING -} I2C_Rx_Status; - -#define I2C_PESET_Mask 0x20 -#define I2C_PERESET 0xDF -#define I2C_ENGC_Mask 0x10 -#define I2C_START_Mask 0x08 -#define I2C_STOP_Mask 0x02 -#define I2C_ACK_Mask 0x04 -#define I2C_ITE_Mask 0x01 - -/******************************************************************************* -* Function Name : I2C_Init -* Description : Initializes I2C peripheral control and registers to their -* default reset values. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : None. -*******************************************************************************/ -void I2C_Init (I2C_TypeDef *I2Cx); - -/******************************************************************************* -* Function Name : I2C_OnOffConfig -* Description : Enables or disables I2C peripheral. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -void I2C_OnOffConfig (I2C_TypeDef *I2Cx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : I2C_GeneralCallConfig -* Description : Enables or disables I2C general call option. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -inline void I2C_GeneralCallConfig (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) I2Cx->CR |= I2C_ENGC_Mask; - else I2Cx->CR &= ~I2C_ENGC_Mask; -} - -/******************************************************************************* -* Function Name : I2C_STARTGenerate -* Description : Generates I2C communication START condition. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -inline void I2C_STARTGenerate (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) I2Cx->CR |= I2C_START_Mask; - else I2Cx->CR &= ~I2C_START_Mask; -} - -/******************************************************************************* -* Function Name : I2C_STOPGenerate -* Description : Generates I2C communication STOP condition. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -inline void I2C_STOPGenerate (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) I2Cx->CR |= I2C_STOP_Mask; - else I2Cx->CR &= ~I2C_STOP_Mask; -} - -/******************************************************************************* -* Function Name : I2C_AcknowledgeConfig -* Description : Enables or disables I2C acknowledge feature. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -inline void I2C_AcknowledgeConfig (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) I2Cx->CR |= I2C_ACK_Mask; - else I2Cx->CR &= ~I2C_ACK_Mask; -} - -/******************************************************************************* -* Function Name : I2C_ITConfig -* Description : Enables or disables I2C interrupt feature. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -inline void I2C_ITConfig (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) I2Cx->CR |= I2C_ITE_Mask; - else I2Cx->CR &= ~I2C_ITE_Mask; -} - -/******************************************************************************* -* Function Name : I2C_RegisterRead -* Description : Reads any I2C register and returns its value. -* Input : I2Cx ( I2C0 or I2C1 ) -* Reg :the register to be read (I2CCR,I2CSR1,I2CSR2,I2CCCR, -* I2COAR1,I2COAR2,I2CDR,I2CECCR) -* Return : the value of the register passed as parameter(u8) -*******************************************************************************/ -inline u8 I2C_RegisterRead (I2C_TypeDef *I2Cx, I2C_Registers reg) -{ - return (*(u8 *)(*((u32 *)&I2Cx) + reg)); -} - -/******************************************************************************* -* Function Name : I2C_FlagStatus -* Description : Checks whether any I2C Flag is set or not. -* Input : I2Cx ( I2C0 or I2C1 ) -* Access(DIRECT or INDIRECT) -* Flag : the flag to be read -* input 4: an (u8) variable needed in the case -* of the INDIRECT access. -* Return : The NewState of the Flag (SET or RESET). -*******************************************************************************/ -FlagStatus I2C_FlagStatus (I2C_TypeDef *I2Cx, RegisterAccess Access, I2C_Flags Flag,...); -/******************************************************************************* -* Function Name : I2C_FlagClear -* Description : Clears the I2C Flag passed as a parameter -* Input : I2Cx ( I2C0 or I2C1 ) -* Flag : the flag to be cleared. -* input3: an (u8) parameter needed if the flag -* to be cleared needs a write in one register. -* Return : None. -*******************************************************************************/ -void I2C_FlagClear (I2C_TypeDef *I2Cx, I2C_Flags Flag,...); -/******************************************************************************* -* Function Name : I2C_SpeedConfig -* Description : Selects I2C clock speed and configures its corresponding mode. -* Input : I2Cx ( I2C0 or I2C1 ) -* Clock: I2C expected clock in Hertz. -* Return : None. -*******************************************************************************/ -void I2C_SpeedConfig (I2C_TypeDef *I2Cx, u32 Clock); -/******************************************************************************* -* Function Name : I2C_AddressConfig -* Description : Defines the I2C bus address of the interface. -* Input : I2Cx ( I2C0 or I2C1 ). -* Address: an u16 parameter indicating the address -* of the interface. -* Mode (I2C_Mode10,I2C_Mode7). -* Return : None. -*******************************************************************************/ -void I2C_AddressConfig (I2C_TypeDef *I2Cx, u16 Address, I2C_Addressing Mode); - -/******************************************************************************* -* Function Name : I2C_FCLKConfig -* Description : Configures frequency bits according to RCLK frequency. -* The I2C selected MUST be disabled. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : None. -*******************************************************************************/ -void I2C_FCLKConfig (I2C_TypeDef *I2Cx); -/******************************************************************************* -* Function Name : I2C_AddressSend -* Description : Transmits the address byte to select the slave device. -* Input : I2Cx ( I2C0 or I2C1 ) -* Address: an u16 parameter indicating the slave address -* Mode (I2C_Mode10,I2C_Mode7). -* Direction (I2C_RX,I2C_TX). -* Return : None. -********************************************************************************/ -void I2C_AddressSend (I2C_TypeDef *I2Cx, u16 Address, I2C_Addressing Mode, I2C_Direction Direction); -/******************************************************************************* -* Function Name : I2C_ByteSend -* Description : Send a single byte of data. -* Input : I2Cx ( I2C0 or I2C1 ) -* Data : the byte to be sent to the slave -* Return : None. -*******************************************************************************/ -void I2C_ByteSend (I2C_TypeDef *I2Cx, u8 Data); -/******************************************************************************* -* Function Name : I2C_TransmissionStatus -* Description : Report the NewState of the transmission -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : I2C_Tx_Status :transmission status (I2C_TX_NO, I2C_TX_SB, -* I2C_TX_AF, I2C_TX_ARLO, I2C_TX_BERR,I2C_TX_ADD_OK, -* I2C_TX_DATA_OK,I2C_TX_ONGOING) -*******************************************************************************/ -I2C_Tx_Status I2C_TransmissionStatus (I2C_TypeDef *I2Cx); -/******************************************************************************* -* Function Name : I2C_ByteReceive -* Description : Returns the received byte. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : The received byte. -*******************************************************************************/ -u8 I2C_ByteReceive (I2C_TypeDef *I2Cx); -/******************************************************************************* -* Function Name :I2C_ReceptionStatus -* Description : Report the reception NewState. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : I2C_Rx_Status:the NewState of the reception ( I2C_RX_NO, -* I2C_RX_SB,I2C_RX_AF,I2C_RX_ARLO,I2C_RX_BERR,I2C_RX_ADD_OK, -* I2C_RX_DATA_OK, I2C_RX_ONGOING) -*******************************************************************************/ -I2C_Rx_Status I2C_ReceptionStatus (I2C_TypeDef *I2Cx); -/******************************************************************************* -* Function Name : I2C_ErrorClear -* Description : Clears any error flags. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : None. -*******************************************************************************/ -inline void I2C_ErrorClear (I2C_TypeDef *I2Cx) -{ - /* Clear all error flags by reading the SR2 register */ - (void)I2Cx->SR2; -} - -/******************************************************************************* -* Function Name : I2C_GetStatus -* Description : Reads the I2C status registers. -* Input : None -* Return : I2C status registers. -*******************************************************************************/ -inline u32 I2C_GetStatus(I2C_TypeDef *I2Cx) -{ - u8 i2c_cr, i2c_sr1,i2c_sr2; - - i2c_cr = I2Cx->CR; - i2c_sr1 = I2Cx->SR1; - i2c_sr2 = I2Cx->SR2; - - return (((i2c_cr)<<14)|(i2c_sr1|(i2c_sr2<<8))&0x3FFF); -} - -#endif /* __i2c_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/pcu.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/pcu.h deleted file mode 100644 index 65ad1746c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/pcu.h +++ /dev/null @@ -1,204 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : pcu.h -* Author : MCD Application Team -* Date First Issued : 30/05/2003 -* Description : This file contains all the functions prototypes for the -* PCU software library. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __PCU_H -#define __PCU_H - -#include "71x_map.h" - -typedef enum -{ - PCU_WREN = 0x8000, - PCU_VROK = 0x1000 -} PCU_Flags; - -typedef enum -{ - PCU_STABLE, - PCU_UNSTABLE -} PCU_VR_Status; - -typedef enum -{ - PCU_MVR = 0x0008, - PCU_LPR = 0x0010 -} PCU_VR; - -typedef enum -{ - WFI_CLOCK2_16, - WFI_EXTERNAL -} WFI_CLOCKS; - -typedef enum -{ - PCU_SLOW, - PCU_STOP, - PCU_STANDBY -} LPM_MODES; - - -/* VR_OK : Voltage Regulator OK */ -#define PCU_VROK_Mask 0x1000 - -/* Main Voltage Regulator */ -#define PCU_MVR_Mask 0x0008 - -/* Low Power Voltage Regulator */ -#define PCU_LPR_Mask 0x0010 - -/* PCU register Write Enable Bit */ -#define PCU_WREN_Mask 0x8000 - -/* PCU register Backup logic Busy ( programming ongoing) Bit */ -#define PCU_BUSY_Mask 0x4000 - -/* Low Voltage Detector */ -#define PCU_LVD_Mask 0x0100 - -/* Power Down Flag */ -#define PCU_PWRDWN_Mask 0x0040 - -/* WFI Mode Clock Selection Bit */ -#define PCU_WFI_CKSEL_Mask 0x00000002 - -/* Halt Mode Enable Bit */ -#define PCU_EN_HALT_Mask 0x00000800 - -/* Halt Mode Flag */ -#define PCU_HALT_Mask 0x0002 - -/* Stop Mode Enable Bit */ -#define PCU_STOP_EN_Mask 0x00000400 - -/* Low Power Regulator in Wait For interrupt Mode */ -#define PCU_LPRWFI_Mask 0x0020 - -/* Low Power Mode in Wait For interrupt Mode */ -#define PCU_LPOWFI_Mask 0x00000001 - -/* Software Reset Enable */ -#define PCU_SRESEN_Mask 0x00000001 - - -/******************************************************************************* -* Function Name : PCU_MVRStatus -* Description : This routine is used to check the Main Voltage Regulator -* : NewState. -* Input : None -* Return : STABLE, UNSTABLE -*******************************************************************************/ -inline PCU_VR_Status PCU_MVRStatus ( void ) -{ - return (PCU->PWRCR & PCU_VROK_Mask) == 0x00 ? PCU_UNSTABLE : PCU_STABLE; -} - -/******************************************************************************* -* Function Name : PCU_FlagStatus -* Description : This routine is used to return the PCU register flag -* Input 1 : The flag to get -* Return : RESET, SET -*******************************************************************************/ -inline FlagStatus PCU_FlagStatus ( PCU_Flags Xflag ) -{ - return ( PCU->PWRCR & Xflag ) == 0x00 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : PCU_VRConfig -* Description : This routine is used to configure PCU voltage regultors -* Input 1 : MVR : Main voltage Regulator - LPR : Low Power Regulator -* Input 2 : ENABLE : Enable the Voltage Regulator - DISABLE: Disable ( ByPass ) the VR -* Return : None -*******************************************************************************/ -void PCU_VRConfig ( PCU_VR xVR, FunctionalState NewState ); - -/******************************************************************************* -* Function Name : PCU_VRStatus -* Description : This routine is used to get the PCU voltage regultors status -* Input : MVR : Main voltage Regulator - LPR : Low Power Regulator -* Return : ENABLE : Enable the Voltage Regulator - DISABLE: Disable ( ByPass ) the VR -*******************************************************************************/ -inline FunctionalState PCU_VRStatus ( PCU_VR xVR ) -{ - return ( PCU->PWRCR & xVR ) == 0 ? ENABLE : DISABLE; -} - -/******************************************************************************* -* Function Name : PCU_LVDDisable -* Description : This routine is used to disable the Low Voltage Detector. -* Input : None -* Return : None -*******************************************************************************/ -inline void PCU_LVDDisable ( void ) -{ - /* Wait until the previous write operation will be completed */ - while (( PCU->PWRCR & PCU_BUSY_Mask ) == 1); - - /* Unlock Power Control Register */ - PCU->PWRCR |= PCU_WREN_Mask; - - /* Set the LVD DIS Flag */ - PCU->PWRCR |= PCU_LVD_Mask; -} - -/******************************************************************************* -* Function Name : PCU_LVDStatus -* Description : This routine is used to get the LVD NewState. -* Input : None -* Return : ENABLE, DISABLE -*******************************************************************************/ -inline FunctionalState PCU_LVDStatus ( void ) -{ - return ( PCU->PWRCR & PCU_LVD_Mask ) == 0 ? ENABLE : DISABLE; -} - -/******************************************************************************* -* Function Name : PCU_WFIEnter -* Description : This routine is used to force the Device to enter in WFI mode -* Input 1 : CLOCK2_16 : Clock2_16 as system clock for WFI mode -* EXTERNAL : external clock as system clock for WFI mode -* Input 2 : ENABLE : Enable Low Power Regulator during Wait For Interrupt Mode -* DISABLE: Disable Low Power Regulator during Wait For Interrupt Mode -* Input 3 : ENABLE : Enable Low Power Mode during Wait For Interrupt Mode -* DISABLE: Disable Low Power Mode during Wait For Interrupt Mode -* Return : None -*******************************************************************************/ -void PCU_WFIEnter ( WFI_CLOCKS Xclock, FunctionalState Xlpr, FunctionalState Xlpm ); - -/******************************************************************************* -* Function Name : PCU_LPMEnter -* Description : This routine is used to force the Device to enter low -* power mode -* Input : SLOW : Slow Mode - STOP : Stop Mode - HALT : Halt Mode -* Return : None -*******************************************************************************/ -void PCU_LPMEnter ( LPM_MODES Xmode); - -#endif /* __PCU_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/rccu.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/rccu.h deleted file mode 100644 index 3cedadb80..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/rccu.h +++ /dev/null @@ -1,323 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : rccu.h -* Author : MCD Application Team -* Date First Issued : 28/07/2003 -* Description : This file contains all the functions prototypes for the -* RCCU software library. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __RCCU_H -#define __RCCU_H - -#include "71x_map.h" - -typedef enum { - RCCU_DEFAULT=0x00, - RCCU_RCLK_2 =0x01, - RCCU_RCLK_4 =0x02, - RCCU_RCLK_8 =0x03 - } RCCU_Clock_Div; - -typedef enum { - RCCU_PLL1_Output, - RCCU_CLOCK2_16, - RCCU_CLOCK2, - RCCU_RTC_CLOCK - } RCCU_RCLK_Clocks; - - - typedef enum { - RCCU_PLL1_Mul_12=0x01, - RCCU_PLL1_Mul_16=0x03, - RCCU_PLL1_Mul_20=0x00, - RCCU_PLL1_Mul_24=0x02 - } RCCU_PLL1_Mul; - -typedef enum { - RCCU_PLL2_Mul_12=0x01, - RCCU_PLL2_Mul_16=0x03, - RCCU_PLL2_Mul_20=0x00, - RCCU_PLL2_Mul_28=0x02 - } RCCU_PLL2_Mul; - -typedef enum { - RCCU_Div_1=0x00, - RCCU_Div_2=0x01, - RCCU_Div_3=0x02, - RCCU_Div_4=0x03, - RCCU_Div_5=0x04, - RCCU_Div_6=0x05, - RCCU_Div_7=0x06 - } RCCU_PLL_Div; - -typedef enum { - RCCU_PLL2_Output = 0x01, - RCCU_USBCK = 0x00 - } RCCU_USB_Clocks; - -typedef enum { - RCCU_CLK2, - RCCU_RCLK, - RCCU_MCLK, - RCCU_PCLK, - RCCU_FCLK - } RCCU_Clocks; - -typedef enum { - RCCU_PLL1_LOCK_IT = 0x0080, - RCCU_CKAF_IT = 0x0100, - RCCU_CK2_16_IT = 0x0200, - RCCU_STOP_IT = 0x0400 - } RCCU_Interrupts; - -typedef enum { - RCCU_PLL1_LOCK = 0x0002, - RCCU_CKAF_ST = 0x0004, - RCCU_PLL1_LOCK_I = 0x0800, - RCCU_CKAF_I = 0x1000, - RCCU_CK2_16_I = 0x2000, - RCCU_STOP_I = 0x4000 - } RCCU_Flags; - -typedef enum { - RCCU_ExternalReset = 0x00000000, - RCCU_SoftwareReset = 0x00000020, - RCCU_WDGReset = 0x00000040, - RCCU_RTCAlarmReset = 0x00000080, - RCCU_LVDReset = 0x00000200, - RCCU_WKPReset = 0x00000400 - }RCCU_ResetSources; - - -#define RCCU_Div2_Mask 0x00008000 -#define RCCU_Div2_Index 0x0F -#define RCCU_FACT_Mask 0x0003 - -#define RCCU_FACT1_Mask 0x0003 - -#define RCCU_FACT2_Mask 0x0300 -#define RCCU_FACT2_Index 0x08 - -#define RCCU_MX_Mask 0x00000030 -#define RCCU_MX_Index 0x04 - -#define RCCU_DX_Mask 0x00000007 - -#define RCCU_FREEN_Mask 0x00000080 - -#define RCCU_CSU_CKSEL_Mask 0x00000001 - -#define RCCU_CK2_16_Mask 0x00000008 - -#define RCCU_CKAF_SEL_Mask 0x00000004 - -#define RCCU_LOCK_Mask 0x00000002 - -#define RCCU_USBEN_Mask 0x0100 -#define RCCU_USBEN_Index 0x08 -#define RCCU_ResetSources_Mask 0x000006E0 - -// RTC Oscillator Frequency value = 32 768 Hz -//#define RCCU_RTC_Osc 32768 - -extern const u32 RCCU_Main_Osc; -extern const u32 RCCU_RTC_Osc; - -/******************************************************************************* -* Function Name : RCCU_Div2Config -* Description : Enables/Disables the clock division by two -* Input : NewState : ENABLE or DISABLE -* Return : None -*******************************************************************************/ -inline void RCCU_Div2Config ( FunctionalState NewState ) -{ - if (NewState == ENABLE) RCCU->CFR |= RCCU_Div2_Mask; - else RCCU->CFR &= ~RCCU_Div2_Mask; -} - -/******************************************************************************* -* Function Name : RCCU_Div2Status -* Description : Gets the Div2 Flag status -* Input : None -* Input : FlagStatus -* Return : None -*******************************************************************************/ -inline FlagStatus RCCU_Div2Status ( void ) -{ - return (RCCU->CFR & RCCU_Div2_Mask) == 0 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : RCCU_MCLKConfig -* Description : Selects the division factor for RCLK to obtain the -* MCLK clock for the CPU -* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, RCCU_RCLK_4, RCCU_RCLK_8 -* Return : None -*******************************************************************************/ -inline void RCCU_MCLKConfig ( RCCU_Clock_Div New_Clock ) -{ - PCU->MDIVR = ( PCU->MDIVR & ~RCCU_FACT_Mask ) | New_Clock; -} - -/******************************************************************************* -* Function Name : RCCU_FCLKConfig -* Description : Selects the division factor for RCLK to obtain the -* FCLK clock for the APB1 fast peripherals (PCLK1). -* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, -* RCCU_RCLK_4, RCCU_RCLK_8 -* Return : None -*******************************************************************************/ -inline void RCCU_FCLKConfig ( RCCU_Clock_Div New_Clock ) -{ - PCU->PDIVR = ( PCU->PDIVR & ~RCCU_FACT1_Mask ) | New_Clock; -} - -/******************************************************************************* -* Function Name : RCCU_PCLKConfig -* Description : Selects the division factor for RCLK to obtain the -* PCLK clock for the APB2 peripherals (PCLK2). -* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, -* RCCU_RCLK_4, RCCU_RCLK_8 -* Return : None -*******************************************************************************/ -inline void RCCU_PCLKConfig ( RCCU_Clock_Div New_Clock ) -{ - PCU->PDIVR =(PCU->PDIVR & ~RCCU_FACT2_Mask)|(New_Clock << RCCU_FACT2_Index); -} - -/******************************************************************************* -* Function Name : RCCU_PLL1Config -* Description : Configures the PLL1 div & mul factors. -* Input : New_Mul : RCCU_Mul_12, RCCU_Mul_16, RCCU_Mul_20, RCCU_Mul_28 -* : New_Div : RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, -* RCCU_Div_4, RCCU_Div_5, RCCU_Div_6, RCCU_Div_7 -* Return : None -*******************************************************************************/ -void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div ); - -/******************************************************************************* -* Function Name : RCCU_PLL2Config -* Description : Configures the PLL2 div & mul factors. -* Input : New_Mul : RCCU_Mul_12, RCCU_Mul_16, RCCU_Mul_20, RCCU_Mul_28 -* : New_Div : RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, -* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7 -* Return : None -*******************************************************************************/ -void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div ); - -/******************************************************************************* -* Function Name : RCCU_RCLKSourceConfig -* Description : Selects the RCLK source clock -* Input : New_Clock : RCCU_PLL1_OutPut, RCCU_CLOCK2_16, RCCU_CLOCK2 -* Return : None -*******************************************************************************/ -void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock ); - -/******************************************************************************* -* Function Name : RCCU_RCLKClockSource -* Description : Returns the current RCLK source clock -* Input : None -* Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 -*******************************************************************************/ -RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void ); - -/******************************************************************************* -* Function Name : RCCU_USBCLKConfig -* Description : Selects the USB source clock -* Input : New_Clock : RCCU_PLL2_Output, RCCU_USBCK -* Return : None -*******************************************************************************/ -inline void RCCU_USBCLKConfig ( RCCU_USB_Clocks New_Clock ) -{ - PCU->PLL2CR = (PCU->PLL2CR & ~RCCU_USBEN_Mask)|(New_Clock << RCCU_USBEN_Index); -} - -/******************************************************************************* -* Function Name : RCCU_USBClockSource -* Description : Gets the USB source clock -* Input : None -* Return : RCCU_USB_Clocks -*******************************************************************************/ -RCCU_USB_Clocks RCCU_USBClockSource ( void ); - -/******************************************************************************* -* Function Name : RCCU_FrequencyValue -* Description : Calculates & Returns any internal RCCU clock freuqency -* passed in parametres -* Input : RCCU_Clocks : RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, -* RCCU_PCLK, RCCU_FCLK -* Return : u32 -*******************************************************************************/ -u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk ); - -/******************************************************************************* -* Function Name : RCCU_ITConfig -* Description : Configures the RCCU interrupts -* Input : RCCU interrupts : RCCU_CK2_16_IT, RCCU_CKAF_IT, -* RCCU_PLL1_LOCK_IT -* Return : None -*******************************************************************************/ -inline void RCCU_ITConfig ( RCCU_Interrupts RCCU_IT, FunctionalState NewState) -{ - if (NewState == ENABLE) RCCU->CCR |= RCCU_IT; else RCCU->CCR &= ~RCCU_IT; -} - -/******************************************************************************* -* Function Name : RCCU_FlagStatus -* Description : Checks the RCCU clock flag register status -* Input : RCCU Flags : RCCU_CK2_16, RCCU_CKAF, RCCU_PLL1_LOCK -* Return : FlagStatus : SET or RESET -*******************************************************************************/ -inline FlagStatus RCCU_FlagStatus ( RCCU_Flags RCCU_flag ) -{ - return (RCCU->CFR & RCCU_flag) == 0 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : RCCU_FlagClear -* Description : Clears a specified flag in the RCCU registers -* Input : RCCU Flags : RCCU_CK2_16, RCCU_CKAF, RCCU_PLL1_LOCK -* Return : None -*******************************************************************************/ -inline void RCCU_FlagClear ( RCCU_Interrupts RCCU_IT ) -{ - RCCU->CFR |= RCCU_IT; -} - -/******************************************************************************* -* Function Name : RCCU_ResetSources -* Description : Return the source of the system reset -* Input : None -* Return : The reset source -*******************************************************************************/ -inline RCCU_ResetSources RCCU_ResetSource () -{ - - switch(RCCU->CFR & RCCU_ResetSources_Mask) - { - case 0x00000020: return RCCU_SoftwareReset; - case 0x00000040: return RCCU_WDGReset; - case 0x00000080: return RCCU_RTCAlarmReset; - case 0x00000200: return RCCU_LVDReset; - case 0x00000400: return RCCU_WKPReset; - default : return RCCU_ExternalReset; - } -} - -#endif /* __RCCU_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/rtc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/rtc.h deleted file mode 100644 index 90e3b2370..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/rtc.h +++ /dev/null @@ -1,185 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : rtc.h -* Author : MCD Application Team -* Date First Issued : 20/05/2003 -* Description : This file contains all the functions prototypes for the -* RTC software library. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __RTC_H -#define __RTC_H - -#include "71x_map.h" - -typedef enum -{ - RTC_GIR = 0x0008, - RTC_OWIR = 0x0004, - RTC_AIR = 0x0002, - RTC_SIR = 0x0001 -} RTC_FLAGS; - -typedef enum -{ - RTC_GIT = 0x0008, - RTC_OWIT = 0x0004, - RTC_AIT = 0x0002, - RTC_SIT = 0x0001 -} RTC_IT; - - -/******************************************************************************* -* Function Name : RTC_CounterClear -* Description : This routine is used to clear the RTC counter -* Input : None -* Return : None -*******************************************************************************/ -void RTC_CounterClear (void); - -/******************************************************************************* -* Function Name : RTC_CounterValue -* Description : This routine is used to get the RTC counter value -* Input : None -* Return : The current counter value. -*******************************************************************************/ -inline u32 RTC_CounterValue (void) -{ - return ( (u32)RTC->CNTH << 16 ) | RTC->CNTL; -} - -/******************************************************************************* -* Function Name : RTC_CounterConfig -* Description : This routine is used to update the RTC counter value -* Input : The new counter value. -* Return : None -*******************************************************************************/ -void RTC_CounterConfig (u32 CounterValue); - -/******************************************************************************* -* Function Name : RTC_PrescalerValue -* Description : This routine is used to get the RTC prescaler Value -* Input : None -* Return : an u32 value that holds the prescaler Value. -*******************************************************************************/ -inline u32 RTC_PrescalerValue (void) -{ - return ( (u32)(RTC->PRLH & 0x000F) << 16 ) | RTC->PRLL; -} - -/******************************************************************************* -* Function Name : RTC_PrescalerConfig -* Description : This routine is used to set the Prescaler Value -* Input : The New prescaler Value -* Return : None -*******************************************************************************/ -void RTC_PrescalerConfig (u32 Xprescaler); - -/******************************************************************************* -* Function Name : RTC_AlarmValue -* Description : This routine is used to get the RTC alarm Value -* Input : None -* Return : an u32 value that holds the Real Time clock alarm time . -*******************************************************************************/ -inline u32 RTC_AlarmValue (void) -{ - return ( (u32)RTC->ALRH << 16 ) | RTC->ALRL; -} - -/******************************************************************************* -* Function Name : RTC_AlarmConfig -* Description : This routine is used to set the RTC alarm Value -* Input : an u32 value that holds the Real Time clock alarm time . -* Return : None -*******************************************************************************/ -void RTC_AlarmConfig (u32 Xalarm); - -/******************************************************************************* -* Function Name : RTC_FlagStatus -* Description : This routine is used to get the RTC flag status -* Input : an RTC flag RTC_GIR, RTC_OWIR, RTC_AIR or RTC_SIR -* Return : SET or RESET -*******************************************************************************/ -inline FlagStatus RTC_FlagStatus (RTC_FLAGS Xflag) -{ - return ( RTC->CRL & Xflag ) == 0 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : RTC_FlagClear -* Description : This routine is used to clear the RTC flags -* Input : an RTC flag RTC_GIR, RTC_OWIR, RTC_AIR or RTC_SIR -* Return : None -*******************************************************************************/ -void RTC_FlagClear (RTC_FLAGS Xflag); - -/******************************************************************************* -* Function Name : RTC_ITConfig -* Description : This routine is used to configure the RTC interrupts -* Input 1 : a RTC interrupt RTC_GIT, RTC_OWIT, RTC_AIT or RTC_SIT -* Input 2 : ENABLE or DISABLE -* Return : None -*******************************************************************************/ -inline void RTC_ITConfig (RTC_IT Xrtcit, FunctionalState NewState) -{ - if (NewState == ENABLE) RTC->CRH |= Xrtcit; else RTC->CRH &= ~Xrtcit; -} - -/******************************************************************************* -* Function Name : RTC_ITStatus -* Description : This routine is used to get the RTC interrupts status -* Input : an RTC interrupt RTC_GIT, RTC_OWIT, RTC_AIT or RTC_SIT -* Return : ENABLE or DISABLE -*******************************************************************************/ -inline FunctionalState RTC_ITStatus (RTC_IT Xrtcit) -{ - return ( RTC->CRH & Xrtcit ) == 0 ? DISABLE : ENABLE; -} - -/******************************************************************************* -* Function Name : RTC_ITClear -* Description : This routine is used to clear the RTC interrupts -* Input : an RTC interrupt RTC_GIT, RTC_OWIT, RTC_AIT or RTC_SIT -* Return : None -*******************************************************************************/ -void RTC_ITClear (RTC_IT Xrtcit); - -/******************************************************************************* -* Function Name : RTC_EnterCfgMode -* Description : This routine is used to enter in the Configuration Mode -* Input : None -* Return : None -*******************************************************************************/ -void RTC_EnterCfgMode(void); - -/******************************************************************************* -* Function Name : RTC_ExitCfgMode -* Description : This routine is used to exit from the Configuration Mode -* Input : None -* Return : None -*******************************************************************************/ -void RTC_ExitCfgMode(void); - -/******************************************************************************* -* Function Name : RTC_WaitForLastTask -* Description : This routine waits for the last task completetion -* Input : None -* Return : None -*******************************************************************************/ -void RTC_WaitForLastTask(void); - -#endif /* __RTC_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/tim.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/tim.h deleted file mode 100644 index f5ad88322..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/tim.h +++ /dev/null @@ -1,348 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : tim.h -* Author : MCD Application Team -* Date First Issued : 08/09/2003 -* Description : This file contains all the functions prototypes for the -* TIM software library. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __TIM_H -#define __TIM_H - -#include "71x_map.h" - -typedef enum { TIM_EXTERNAL, - TIM_INTERNAL - } TIM_Clocks; - -typedef enum { TIM_RISING, - TIM_FALLING - } TIM_Clock_Edges; - -typedef enum { TIM_CHANNEL_A, - TIM_CHANNEL_B - } TIM_Channels; - -typedef enum { TIM_WITH_IT, - TIM_WITHOUT_IT - } TIM_IT_Mode; - -typedef enum { TIM_TIMING, - TIM_WAVE - } TIM_OC_Modes; - -typedef enum { TIM_HIGH, - TIM_LOW - } TIM_Logic_Levels; - -typedef enum { TIM_START, - TIM_STOP, - TIM_CLEAR - } TIM_CounterOperations; - -typedef enum { TIM_ICFA = 0x8000, - TIM_OCFA = 0x4000, - TIM_TOF = 0x2000, - TIM_ICFB = 0x1000, - TIM_OCFB = 0x0800 - } TIM_Flags; - -typedef struct { u16 Pulse; - u16 Period; - } PWMI_parameters; - -#define TIM_ECKEN_Mask 0x0001 -#define TIM_EXEDG_Mask 0x0002 - -#define TIM_IEDGA_Mask 0x0004 -#define TIM_IEDGB_Mask 0x0008 - -#define TIM_PWM_Mask 0x0010 - -#define TIM_OPM_Mask 0x0020 - -#define TIM_OCAE_Mask 0x0040 -#define TIM_OCBE_Mask 0x0080 - -#define TIM_OLVLA_Mask 0x0100 -#define TIM_OLVLB_Mask 0x0200 - -#define TIM_FOLVA_Mask 0x0400 -#define TIM_FOLVB_Mask 0x0800 - -#define TIM_PWMI_Mask 0x4000 - -#define TIM_EN_Mask 0x8000 - -#define TIM_OCBIE_mask 0x0800 -#define TIM_ICBIE_Mask 0x1000 -#define TIM_TOE_Mask 0x2000 -#define TIM_OCAIE_mask 0x4000 - -#define TIM_ICAIE_Mask 0x8000 - -#define TIM_ICA_IT 0x8000 /* Input Capture Channel A */ -#define TIM_OCA_IT 0x4000 /* Output Compare Channel A */ -#define TIM_TO_IT 0x2000 /* Timer OverFlow */ -#define TIM_ICB_IT 0x1000 /* Input Capture Channel B */ -#define TIM_OCB_IT 0x0800 /* Input Capture Channel A */ - - -/******************************************************************************* -* Function Name : TIM_Init -* Description : This routine is used to Initialize the TIM peripheral -* Input : TIM Timer to Initialize -* Return : None -*******************************************************************************/ -void TIM_Init( TIM_TypeDef *TIMx ); - -/******************************************************************************* -* Function Name : TIM_ClockSourceConfig -* Description : This routine is used to configure the TIM clock source -* Input : (1) TIM Timer -* : (2) TIM_Clocks : Specifies the TIM source clock -* - TIM_INTERNAL : The TIM is clocked by the APB2 frequency -* divided by the prescaler value. -* - TIM_EXTERNAL : The TIM is clocked by an external Clock -* Return : None -*******************************************************************************/ -inline void TIM_ClockSourceConfig ( TIM_TypeDef *TIMx, TIM_Clocks Xclock ) -{ - if (Xclock==TIM_EXTERNAL) TIMx->CR1|=TIM_ECKEN_Mask; else TIMx->CR1&=~TIM_ECKEN_Mask; -} - -/******************************************************************************* -* Function Name : TIM_ClockSourceValue -* Description : This routine is used to get the TIM clock source -* Input : TIM Timer -* Return : TIM_Clocks : Specifies the TIM source clock -* - TIM_INTERNAL : The TIM is clocked by the APB2 frequency -* divided by the prescaler value. -* - TIM_EXTERNAL : The TIM is clocked by an external Clock -*******************************************************************************/ -inline TIM_Clocks TIM_ClockSourceValue ( TIM_TypeDef *TIMx ) -{ - return ( TIMx->CR1 & TIM_ECKEN_Mask) == 0 ? TIM_INTERNAL : TIM_EXTERNAL; -} - -/******************************************************************************* -* Function Name : TIM_PrescalerConfig -* Description : This routine is used to configure the TIM prescaler value -* ( using an internal clock ) -* Input : (1) TIM Timer -* : (2) Prescaler ( u8 ) -* Return : None -*******************************************************************************/ -inline void TIM_PrescalerConfig ( TIM_TypeDef *TIMx, u8 Xprescaler ) -{ - TIMx->CR2 = ( TIMx->CR2 & 0xFF00 ) | Xprescaler; -} - -/******************************************************************************* -* Function Name : TIM_PrescalerValue -* Description : This routine is used to get the TIM prescaler value -* ( when using using an internal clock ) -* Input : TIM Timer -* Return : Prescaler ( u8 ) -*******************************************************************************/ -inline u8 TIM_PrescalerValue ( TIM_TypeDef *TIMx ) -{ - return TIMx->CR2 & 0x00FF; -} - -/******************************************************************************* -* Function Name : TIM_ClockLevelConfig -* Description : This routine is used to configure the TIM clock level -* ( using an external clock ) -* Input : TIM Timer -* : TIM_Clock_Edges : Specifies the active adge of the external clock -* - TIM_RISING : The rising edge -* - TIM_FALLING : The falling edge -* Return : None -*******************************************************************************/ -inline void TIM_ClockLevelConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge ) -{ - if (Xedge == TIM_RISING) TIMx->CR1 |= TIM_EXEDG_Mask; else TIMx->CR1 &= ~TIM_EXEDG_Mask; -} - -/******************************************************************************* -* Function Name : TIM_ClockLevelValue -* Description : This routine is used to get the TIM clock level -* Input : TIM Timer -* Output : TIM_Clock_Edges : Specifies the active adge of the external clock -* - TIM_RISING : The rising edge -* - TIM_FALLING : The falling edge -*******************************************************************************/ -inline TIM_Clock_Edges TIM_ClockLevelValue ( TIM_TypeDef *TIMx ) -{ - return ( TIMx->CR1 & TIM_EXEDG_Mask ) == 0 ? TIM_FALLING : TIM_RISING; -} - -/******************************************************************************* -* Function Name : TIM_ICAPModeConfig -* Description : This routine is used to configure the input capture feature -* Input : (1) TIM Timer -* : (2) Input Capture Channel ( Channel_A or Channel_B ) -* : (3) Active Edge : Rising edge or Falling edge. -* Output : None -*******************************************************************************/ -void TIM_ICAPModeConfig ( TIM_TypeDef *TIMx, - TIM_Channels Xchannel, - TIM_Clock_Edges Xedge ); - -/******************************************************************************* -* Function Name : TIM_ICAPValue -* Description : This routine is used to get the Input Capture value -* Input : (1) TIM Timer -* : (2) Input Capture Channel ( Channel_A or Channel_B ) -* Output : None -*******************************************************************************/ -inline u16 TIM_ICAPValue ( TIM_TypeDef *TIMx, TIM_Channels Xchannel ) -{ - return Xchannel == TIM_CHANNEL_A ? TIMx->ICAR : TIMx->ICBR; -} - -/******************************************************************************* -* Function Name : TIM_OCMPModeConfig -* Description : This routine is used to configure the output compare feature -* Input : (1) TIM Timer -* : (2) OCMP Channel ( Channel_A or Channel_B ) -* : (3) Pulse Length -* : (4) OC_Mode : output wave, or only timing. -* : (5) Level : Rising edge or Falling edge after the == -* Output : None -*******************************************************************************/ -void TIM_OCMPModeConfig ( TIM_TypeDef *TIMx, - TIM_Channels Xchannel, - u16 XpulseLength, - TIM_OC_Modes Xmode, - TIM_Logic_Levels Xlevel ); - -/******************************************************************************* -* Function Name : TIM_OPModeConfig -* Description : This routine is used to configure the one pulse mode -* Input : (1) TIM Timer -* : (3) XpulseLength : Length of the pulse -* : (4) Level1 : Level during the pulse -* : (5) Level2 : Level after the pulse -* : (6) Activation Edge : High or Low on ICAP A -* Output : None -*******************************************************************************/ -void TIM_OPModeConfig ( TIM_TypeDef *TIMx, - u16 XpulseLength, - TIM_Logic_Levels XLevel1, - TIM_Logic_Levels XLevel2, - TIM_Clock_Edges Xedge ); - -/******************************************************************************* -* Function Name : TIM_PWMOModeConfig -* Description : This routine is used to configure the PWM in output mode -* Input : (1) TIM Timer -* : (2) DutyCycle : u16 -* : (3) Level 1 : During the Duty Cycle -* : (4) Level 2 : During the after the pulse -* : (5) Full period : u16 -* Output : None -*******************************************************************************/ -void TIM_PWMOModeConfig ( TIM_TypeDef *TIMx, - u16 XDutyCycle, - TIM_Logic_Levels XLevel1, - u16 XFullperiod, - TIM_Logic_Levels XLevel2 - ); - -/******************************************************************************* -* Function Name : TIM_PWMInputConfig -* Description : This routine is used to configure the PWM in input mode -* Input : (1) TIM Timer -* : (2) First Activation Edge -* Output : None -*******************************************************************************/ -void TIM_PWMIModeConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge ); - -/******************************************************************************* -* Function Name : TIM_PWMIValue -* Description : This routine is used to get the PWMI values -* Input : (1) TIM Timer -* Output : PWMI_parameters : - u16 Dyty cycle - - u16 Full period -*******************************************************************************/ -PWMI_parameters TIM_PWMIValue (TIM_TypeDef *TIMx ); - -/******************************************************************************* -* Function Name : TIM_CounterConfig -* Description : This routine is used to start/stop and clear the selected -* timer counter -* Input : (1) TIM Timer -* : (2) TIM_CounterOperations - TIM_START Enables or resumes the counter -* TIM_STOP Stops the TIM counter -* TIM_CLEAR Set the TIM counter value to FFFCh -* Output : None -*******************************************************************************/ -void TIM_CounterConfig ( TIM_TypeDef *TIMx, TIM_CounterOperations Xoperation ); - -/******************************************************************************* -* Function Name : TIM_ITConfig -* Description : This routine is used to configure the TIM IT -* Input : (1) TIM Timer -* : (2) TIM interrupt (input capture A or input capture B or timer overflow or out compA or outpu com B -* : (2) ENABLE / DISABLE -* Output : None -*******************************************************************************/ -inline void TIM_ITConfig ( TIM_TypeDef *TIMx, u16 New_IT, FunctionalState NewState ) -{ - if (NewState == ENABLE) TIMx->CR2 |= New_IT; else TIMx->CR2 &= ~New_IT; -} - -/******************************************************************************* -* Function Name : TIM_FlagStatus -* Description : This routine is used to check whether a Flag is Set. -* Input : (1) TIM Timer -* : (2) The TIM FLag -* Output : Flag NewState -*******************************************************************************/ -inline FlagStatus TIM_FlagStatus ( TIM_TypeDef *TIMx, TIM_Flags Xflag ) -{ - return (TIMx->SR & Xflag) == 0 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : TIM_FlagClear -* Description : This routine is used to clear Flags. -* Input : (1) TIM Timer -* : (2) The TIM FLag -* Output : None -*******************************************************************************/ -inline void TIM_FlagClear ( TIM_TypeDef *TIMx, TIM_Flags Xflag ) -{ - TIMx->SR &= ~Xflag; -} - -/******************************************************************************* -* Function Name : TIM_CounterValue -* Description : This routine returns the timer counter value. -* Input : TIM Timer -* Output : The counter value -*******************************************************************************/ -inline u16 TIM_CounterValue(TIM_TypeDef *TIMx) -{ - return TIMx->CNTR; -} -#endif /* __TIM_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/uart.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/uart.h deleted file mode 100644 index 21b60705d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/uart.h +++ /dev/null @@ -1,389 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : uart.h -* Author : MCD Application Team -* Date First Issued : 16/05/2003 -* Description : This file contains all the functions prototypes for the -* UART software library. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef _UART_H -#define _UART_H - -#include "71x_map.h" -#include "rccu.h" - -typedef enum -{ - UART_RxFIFO, - UART_TxFIFO -} UARTFIFO_TypeDef; - -typedef enum -{ - UART_EVEN_PARITY = 0x0000, - UART_ODD_PARITY = 0x0020, - UART_NO_PARITY = 0x0000 -} UARTParity_TypeDef; - -typedef enum -{ - UART_0_5_StopBits = 0x00, - UART_1_StopBits = 0x08, - UART_1_5_StopBits = 0x10, - UART_2_StopBits = 0x18 -} UARTStopBits_TypeDef; - -typedef enum -{ - UARTM_8D = 0x01, - UARTM_7D_P = 0x03, - UARTM_9D = 0x04, - UARTM_8D_W = 0x05, - UARTM_8D_P = 0x07 -} UARTMode_TypeDef; - - -/* UART flags definition */ -#define UART_TxFull 0x0200 -#define UART_RxHalfFull 0x0100 -#define UART_TimeOutIdle 0x0080 -#define UART_TimeOutNotEmpty 0x0040 -#define UART_OverrunError 0x0020 -#define UART_FrameError 0x0010 -#define UART_ParityError 0x0008 -#define UART_TxHalfEmpty 0x0004 -#define UART_TxEmpty 0x0002 -#define UART_RxBufFull 0x0001 - - -/******************************************************************************* -* Function Name : UART_Init -* Description : This function initializes the selected UART registers to -* their reset values -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Output : None -* Return : None -*******************************************************************************/ -void UART_Init(UART_TypeDef *UARTx); - -/******************************************************************************* -* Function Name : UART_ModeConfig -* Description : This function configures the mode of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : The UART mode, it can be -* UARTM_8D for 8-bit data format -* UARTM_7D_P for 7-bit data + parity format -* UART_9D for 9-bit data format -* UART_8D_W for 8-bit data + wake-up bit format -* UART_8D_P for 8-bit data + parity bit format -* Output : None -* Return : None -*******************************************************************************/ -inline void UART_ModeConfig(UART_TypeDef *UARTx, UARTMode_TypeDef UART_Mode) -{ - UARTx->CR = (UARTx->CR&0xFFF8)|(u16)UART_Mode; -} - -/******************************************************************************* -* Function Name : UART_BaudRateConfig -* Description : This function configures the baud rate of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : The baudrate value -* Output : None -* Return : None -*******************************************************************************/ -void UART_BaudRateConfig(UART_TypeDef *UARTx, u32 BaudRate); - -/******************************************************************************* -* Function Name : UART_ParityConfig -* Description : This function configures the data parity of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The parity type, it can be UART_EVEN_PARITY, UART_ODD_PARITY -* or UART_NO_PARITY -* Output : None -* Return : None -*******************************************************************************/ -inline void UART_ParityConfig(UART_TypeDef *UARTx, UARTParity_TypeDef Parity) -{ - UARTx->CR = (UARTx->CR&0xFFDF)|(u16)Parity; -} - -/******************************************************************************* -* Function Name : UART_StopBitsConfig -* Description : This function configures the number of stop bits of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : The number of stop bits, it can be -* UART_0_5_StopBits for 0.5 stop bit -* UART_1_StopBits for 1 stop bit, -* UART_1_5_StopBits for 1.5 stop bits -* UART_2_StopBits for 2 stop bits -* Output : None -* Return : None -*******************************************************************************/ -inline void UART_StopBitsConfig(UART_TypeDef *UARTx, UARTStopBits_TypeDef StopBits) -{ - UARTx->CR = (UARTx->CR&0xFFE7)|(u16)StopBits; -} - -/******************************************************************************* -* Function Name : UART_Config -* Description : This function configures the baudrate, the mode, the data -* parity and the number of stop bits of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : u32 The baudrate value -* Input 3 : The parity type, it can be UART_EVEN_PARITY, UART_ODD_PARITY -* or UART_NO_PARITY -* Input 4 : The number of stop bits UART_0_5_StopBits, UART_1_StopBits, -* UART_1_5_StopBits or UART_2_StopBits -* Input 5 : The UART mode, it can be -* UARTM_8D for 8-bit data format -* UARTM_7D_P for 7-bit data + parity format -* UART_9D for 9-bit data format -* UART_8D_W for 8-bit data + wake-up bit format -* UART_8D_P for 8-bit data + parity bit format -* Output : None -* Return : None -*******************************************************************************/ -void UART_Config(UART_TypeDef *UARTx, u32 BaudRate, UARTParity_TypeDef Parity, - UARTStopBits_TypeDef StopBits, UARTMode_TypeDef Mode); - -/******************************************************************************* -* Function Name : UART_ItConfig -* Description : This function enables or disables one or several interrupt -* sources of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : The new interrupt flag or flags -* Input 3 : ENABLE or DISABLE -* Output : None -* Return : None -* Note : The UART interrupt flags are listed in the file uart.h -*******************************************************************************/ -void UART_ItConfig(UART_TypeDef *UARTx, u16 UART_Flag, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_FifoConfig -* Description : This function enables or disables the Rx and Tx FIFOs of -* the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_FifoConfig(UART_TypeDef *UARTx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_FifoReset -* Description : This function resets the Rx and the Tx FIFOs of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : RxFIFO or TxFIFO -* Output : None -* Return : None -*******************************************************************************/ -void UART_FifoReset(UART_TypeDef *UARTx, UARTFIFO_TypeDef FIFO); - -/******************************************************************************* -* Function Name : UART_LoopBackConfig -* Description : This function enables or disables the loop back mode of -* the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_LoopBackConfig(UART_TypeDef *UARTx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_TimeOutPeriodConfig -* Description : This function configures the UART Time Out Period. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : The time-out period value -* Output : None -* Return : None -*******************************************************************************/ -inline void UART_TimeOutPeriodConfig(UART_TypeDef *UARTx, u16 TimeOutPeriod) -{ - UARTx->TOR = TimeOutPeriod; -} - -/******************************************************************************* -* Function Name : UART_GuardTimeConfig -* Description : This function configures the UART Guard Time. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : The guard time value -* Output : None -* Return : None -*******************************************************************************/ -inline void UART_GuardTimeConfig(UART_TypeDef *UARTx, u16 GuardTime) -{ - UARTx->GTR = GuardTime; -} - -/******************************************************************************* -* Function Name : UART_RxConfig -* Description : This function enable and disable the UART data reception. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_RxConfig(UART_TypeDef *UARTx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_OnOffConfig -* Description : This function sets On/Off the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_OnOffConfig(UART_TypeDef *UARTx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_ByteSend -* Description : This function sends a byte to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer on the data byte to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_ByteSend(UART_TypeDef *UARTx, u8 *Data); - -/******************************************************************************* -* Function Name : UART_9BitByteSend -* Description : This function sends a 9-bit data to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer on the data to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_9BitByteSend(UART_TypeDef *UARTx, u16 *Data); - -/******************************************************************************* -* Function Name : UART_DataSend -* Description : This function sends several data bytes to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer on the data to send -* Input 3 : The data length in bytes -* Output : None -* Return : None -*******************************************************************************/ -void UART_DataSend(UART_TypeDef *UARTx, u8 *Data, u8 DataLength); - -/******************************************************************************* -* Function Name : UART_9BitDataSend -* Description : This function sends several 9-bits data to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer on the data to send -* Input 3 : The data length -* Output : None -* Return : None -*******************************************************************************/ -void UART_9BitDataSend(UART_TypeDef *UARTx, u16 *Data, u8 DataLength); - -/******************************************************************************* -* Function Name : UART_StringSend -* Description : This function sends a string to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer on the string to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_StringSend(UART_TypeDef *UARTx, u8 *String); - -/******************************************************************************* -* Function Name : UART_ByteReceive -* Description : This function gets a data byte from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer on the buffer where the data will be stored -* Input 3 : The time-out period -* Output : The received 8-bit data -* Return : The UARTx.SR register content -*******************************************************************************/ -u16 UART_ByteReceive(UART_TypeDef *UARTx, u8 *Data, u8 TimeOut); - -/******************************************************************************* -* Function Name : UART_9BitByteReceive -* Description : This function gets a 9-bit data byte from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer on the buffer where the data will be stored -* Input 3 : The time-out period value -* Output : The received 9-bit data -* Return : The UARTx.SR register content -*******************************************************************************/ -u16 UART_9BitByteReceive(UART_TypeDef *UARTx, u16 *Data, u8 TimeOut); - -/******************************************************************************* -* Function Name : UART_DataReceive -* Description : This function gets 8 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The data length -* Input 4 : The time-out period value -* Output : The received 8-bit data buffer -* Return : The UARTx.SR register content -*******************************************************************************/ -u16 UART_DataReceive(UART_TypeDef *UARTx, u8 *Data, u8 DataLength, u8 TimeOut); - -/******************************************************************************* -* Function Name : UART_9BitDataReceive -* Description : This function gets 9 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The data length -* Input 4 : The time-out value -* Output : The received 9-bit data buffer -* Return : The UARTx.SR register content -*******************************************************************************/ -u16 UART_9BitDataReceive(UART_TypeDef *UARTx, u16 *Data, u8 DataLength, u8 TimeOut); - -/******************************************************************************* -* Function Name : UART_StringReceive -* Description : This function gets 8-bit data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer on the buffer where the string will be stored -* Output : None -* Return : None -*******************************************************************************/ -u16 UART_StringReceive(UART_TypeDef *UARTx, u8 *Data); - -/******************************************************************************* -* Function Name : UART_FlagStatus -* Description : This function gets the flags status of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Output : None -* Return : None -*******************************************************************************/ -inline u16 UART_FlagStatus(UART_TypeDef *UARTx) -{ - return UARTx->SR; -} - -#ifdef USE_SERIAL_PORT -/******************************************************************************* -* Function Name : sendchar -* Description : This function sends a character to the selected UART. -* Input 1 : A pointer on the character to send. -* Output : None -* Return : None -*******************************************************************************/ -void sendchar( char *ch ); -#endif /* USE_SERIAL_PORT */ - -#endif /* _UART_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/wdg.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/wdg.h deleted file mode 100644 index 8ba8f442b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/wdg.h +++ /dev/null @@ -1,132 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : wdg.h -* Author : MCD Application Team -* Date First Issued : 25/08/2003 -* Description : This file contains all the functions prototypes for the -* WDG software library. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __WDG_H -#define __WDG_H - -#include "71x_map.h" -#include "rccu.h" - -/******************************************************************************* -* Function Name : WDG_Enable -* Description : Enable the Watchdog Mode -* Input : None -* Return : None -*******************************************************************************/ -inline void WDG_Enable ( void ) -{ - WDG->CR |= 0x01; -} - -/******************************************************************************* -* Function Name : WDG_CntRefresh -* Description : Refresh and update the WDG counter to avoid a system reset. -* Input : None -* Return : None -*******************************************************************************/ -inline void WDG_CntRefresh ( void ) -{ - /* Write the first value in the key register */ - WDG->KR = 0xA55A; - - /* Write the second value in the key register */ - WDG->KR = 0x5AA5; -} - -/******************************************************************************* -* Function Name : WDG_PrescalerConfig -* Description : Set the counter prescaler value. -* The clock to Timer Counter is divided by (Prescaler + 1) -* Input : Prescaler data value (8 bit) -* Return : None -*******************************************************************************/ -inline void WDG_PrescalerConfig ( u8 Prescaler ) -{ - WDG->PR = Prescaler; -} - -/******************************************************************************* -* Function Name : WDG_CntReloadUpdate -* Description : Update the counter pre-load value. -* Input : Pre-load data value (16 bit) -* Return : None -*******************************************************************************/ -inline void WDG_CntReloadUpdate ( u16 PreLoadValue ) -{ - WDG->VR = PreLoadValue; -} - -/******************************************************************************* -* Function Name : WDG_PeriodValueConfig -* Description : Set the prescaler and counter reload value based on the -* needed time. -* Input : Amount of time (s) needed, peripheral clock2 value -* Return : None -*******************************************************************************/ -void WDG_PeriodValueConfig ( u32 Time ); - -/******************************************************************************* -* Function Name : WDG_CntOnOffConfig -* Description : Start or stop the free auto-reload timer to count down. -* Input : ENABLE or DISABLE -* Return : None -*******************************************************************************/ -inline void WDG_CntOnOffConfig ( FunctionalState NewState ) -{ - if (NewState == ENABLE) WDG->CR |= 0x0002; else WDG->CR &= ~0x0002; -} - -/******************************************************************************* -* Function Name : WDG_ECITConfig -* Description : Enable or Disable the end of count interrupt. -* Input : ENABLE or DISABLE -* Return : None -*******************************************************************************/ -inline void WDG_ECITConfig (FunctionalState NewState) -{ - if (NewState == ENABLE) WDG->MR |= 0x0001; else WDG->MR &= ~0x0001; -} - -/******************************************************************************* -* Function Name : WDG_ECFlagClear -* Description : Clear the end of count flag. -* Input : None -* Return : None -*******************************************************************************/ -inline void WDG_ECFlagClear ( void ) -{ - WDG->SR = 0x0000; -} - -/******************************************************************************* -* Function Name : WDG_ECStatus -* Description : Return the end of count status -* Input : None -* Return : NewState value -*******************************************************************************/ -inline u16 WDG_ECStatus ( void ) -{ - return WDG->SR; -} - -#endif /* __WDG_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/xti.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/xti.h deleted file mode 100644 index 38f90af7c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/include/xti.h +++ /dev/null @@ -1,140 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : xti.h -* Author : MCD Application Team -* Date First Issued : 08/06/2003 -* Description : This file contains all the functions prototypes for the -* XTI software library. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __XTI_H -#define __XTI_H - -#include "71x_map.h" - -typedef enum -{ - XTI_WakeUp = 1, - XTI_Interrupt = 2, - XTI_WakeUpInterrupt = 3 -} XTIMode_TypeDef; - -typedef enum -{ - XTI_FallingEdge, - XTI_RisingEdge -} XTITriggerEdge_TypeDef; - -#define XTI_Line0 0x0001 -#define XTI_Line1 (XTI_Line0<<1) -#define XTI_Line2 (XTI_Line1<<1) -#define XTI_Line3 (XTI_Line2<<1) -#define XTI_Line4 (XTI_Line3<<1) -#define XTI_Line5 (XTI_Line4<<1) -#define XTI_Line6 (XTI_Line5<<1) -#define XTI_Line7 (XTI_Line6<<1) -#define XTI_Line8 (XTI_Line7<<1) -#define XTI_Line9 (XTI_Line8<<1) -#define XTI_Line10 (XTI_Line9<<1) -#define XTI_Line11 (XTI_Line10<<1) -#define XTI_Line12 (XTI_Line11<<1) -#define XTI_Line13 (XTI_Line12<<1) -#define XTI_Line14 (XTI_Line13<<1) -#define XTI_Line15 (XTI_Line14<<1) - -/******************************************************************************* -* Function Name : XTI_Init -* Description : This routine is used to initialize the XIT peripheral - to reset state. -* Input 1 : None -* Output : None -* Return : None -*******************************************************************************/ -void XTI_Init(void); - -/******************************************************************************* -* Function Name : XTI_ModeConfig -* Description : This routine is used to configure the XTI Mode. -* Input 1 : Mode can be WakeUp, Interrupt or WakeUpInterrupt. -* Input 2 : NewState can be ENABLE ro DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -inline void XTI_ModeConfig(XTIMode_TypeDef Mode,FunctionalState NewState) -{ - if (NewState==ENABLE) XTI->CTRL|=Mode; else XTI->CTRL&=~Mode; -} - -/******************************************************************************* -* Function Name : XTI_LineModeConfig -* Description : This routine is used to configure the trigger edge. -* Input 1 : Lines to be configured. -* Input 2 : The trigger edge can be FallingEdge or RisingEdge. -* Output : None -* Return : None -*******************************************************************************/ -void XTI_LineModeConfig(u16 Lines, XTITriggerEdge_TypeDef TriggerEdge); - -/******************************************************************************* -* Function Name : XTI_LineConfig -* Description : This routine is used to enable and disable lines interrupts. -* Input 1 : Lines to be configured. -* Input 2 : NewState can be ENABLE ro DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void XTI_LineConfig(u16 Lines, FunctionalState NewState); - -/******************************************************************************* -* Function Name : XTI_InterruptLineValue -* Description : This routine is used to get the interrupt lines status. -* Input 1 : None. -* Output : The interrupts lines numbers -* Return : None -*******************************************************************************/ -inline u16 XTI_InterruptLineValue(void) -{ - return XTI->PRL | ((u16)XTI->PRH<<8); -} - -/******************************************************************************* -* Function Name : XTI_PendingBitClear -* Description : This routine is used to clear the pending bits. -* Input 1 : Bits to be cleared. -* Output : None -* Return : None -*******************************************************************************/ -inline void XTI_PendingBitClear(u16 Lines) -{ - XTI->PRL &= ~Lines; - XTI->PRH &= ~((Lines>>8)&0x00FF); -} - -/******************************************************************************* -* Function Name : XTI_SoftwareIRQInterruprGenerate -* Description : This routine is used to generate a software IRQ interrupt. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -inline void XTI_SWIRQGenerate(void) -{ - XTI->SR = 0x01; - XTI->SR = 0x00; -} - -#endif /* __XTI_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/pcu.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/pcu.c deleted file mode 100644 index 7e0bf9017..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/pcu.c +++ /dev/null @@ -1,173 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : pcu.c -* Author : MCD Application Team -* Date First Issued : 09/09/03 -* Description : This file provides all the Power Control Unit functions -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "pcu.h" -#include "rccu.h" - -/******************************************************************************* -* Function Name : PCU_VRConfig -* Description : This routine is used to configure PCU voltage regultors -* Input 1 : MVR : Main voltage Regulator - LPR : Low Power Regulator -* Input 2 : ENABLE : Enable the Voltage Regulator - DISABLE: Disable ( ByPass ) the VR -* Return : None -*******************************************************************************/ -void PCU_VRConfig ( PCU_VR Xvr, FunctionalState NewState ) -{ - u16 Tmp = PCU->PWRCR; - switch ( Xvr ) - { - case PCU_MVR : - /* Configure the Main Voltage Regulator */ - if (NewState == DISABLE) Tmp |= PCU_MVR_Mask; else Tmp &= ~PCU_MVR_Mask; - break; - case PCU_LPR : - /* Configure the Low power Voltage Regulator */ - if (NewState == DISABLE) Tmp |= PCU_LPR_Mask; else Tmp &= ~PCU_LPR_Mask; - break; - } - - /* Wait until the previous write operation will be completed */ - while (( PCU->PWRCR & PCU_BUSY_Mask ) == 1); - - /* Unlock Power Control Register */ - PCU->PWRCR |= PCU_WREN_Mask; - PCU->PWRCR = Tmp | PCU_WREN_Mask; -} - -/******************************************************************************* -* Function Name : PCU_WFIEnter -* Description : This routine is used to force the Device to enter in WFI mode -* Input 1 : CLOCK2_16 : Clock2_16 as system clock for WFI mode -* EXTERNAL : external clock as system clock for WFI mode -* Input 2 : ENABLE : Enable Low Power Regulator during Wait For Interrupt Mode -* DISABLE: Disable Low Power Regulator during Wait For Interrupt Mode -* Input 3 : ENABLE : Enable Low Power Mode during Wait For Interrupt Mode -* DISABLE: Disable Low Power Mode during Wait For Interrupt Mode -* Return : None -*******************************************************************************/ -void PCU_WFIEnter ( WFI_CLOCKS Xclock, FunctionalState Xlpr, FunctionalState Xlpm ) -{ - /* Select the WFI mode */ - /* Clear WFI bit in the RCCU_SMR register to enter in WFI mode */ - RCCU->SMR &=0xFE ; - - if (Xlpr == DISABLE ) - - /* Wait until the previous write operation will be completed */ - while (( PCU->PWRCR & PCU_BUSY_Mask ) == 1); - - /* Unlock Power Control Register */ - PCU->PWRCR |= PCU_WREN_Mask; - - /* switched off the main Voltage Regulator in WFI mode */ - PCU->PWRCR |=0x0010;; - - /* Select the LPWFI mode */ - if (Xlpm == ENABLE ) - - /* Disable the flash during the LPWFI */ - FLASHR->CR0|=0x8000; - - if (Xclock == WFI_CLOCK2_16) - /* Select the 32KHz as peripherl clock during LPWFI */ - RCCU->CCR |=0x2; - else - /* Select CLK2/15 as peripherals clock during LPWFI */ - RCCU->CCR &=~0x2; - - /* Set bit LOPWFI for selecting LPWFI mode */ - RCCU->CCR |=0x1; - - /* Enter the LPWFI mode */ - RCCU->SMR &=0xFE; -} - -/******************************************************************************* -* Function Name : PCU_LPMEnter -* Description : This routine is used to force the device to enter in low -* power modes -* Input : PCU_SLOW : Slow Mode - PCU_STOP : Stop Mode - PCU_STANDBY : StandBy Mode -* Return : None -*******************************************************************************/ -void PCU_LPMEnter ( LPM_MODES Xmode ) -{ - u32 temp; - switch ( Xmode ) - { - /* Slow Mode */ - case PCU_SLOW: - { - RCCU->PLL1CR |= 0x87; - RCCU_RCLKSourceConfig ( RCCU_PLL1_Output ); - break; - } - - /* Stop Mode */ - case PCU_STOP: - { - /* Enable Stop EN bit */ - RCCU->CCR |= PCU_STOP_EN_Mask; - - /* Write '1' to Stop Bit */ - XTI->CTRL |= 0x04; - - /* Write '0' to Stop Bit */ - XTI->CTRL &= 0x03; - - /* Write '1' to Stop Bit */ - XTI->CTRL |= 0x04; - - /* Aadd Delay */ - - temp = 0; - temp = 1; - temp = 2; - temp = 3; - temp = 4; - temp = 5; - temp = 6; - temp = 7; - temp = 8; - - break; - - } - - /* PCU_STANDBY Mode */ - case PCU_STANDBY: - { - /* Wait until the previous write operation will be completed */ - while (( PCU->PWRCR & PCU_BUSY_Mask ) == 1); - - /* Unlock Power Control Register */ - PCU->PWRCR |= PCU_WREN_Mask; - - /* Set the Power Down flag */ - PCU->PWRCR |= PCU_PWRDWN_Mask; - } - } -} -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/rccu.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/rccu.c deleted file mode 100644 index 2b7c65a3a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/rccu.c +++ /dev/null @@ -1,193 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : rccu.c -* Author : MCD Application Team -* Date First Issued : 07/28/2003 -* Description : This file provides all the RCCU software functions -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#include "rccu.h" - -/******************************************************************************* -* Function Name : RCCU_PLL1Config -* Description : Configures the PLL1 div & mul factors. -* Input : New_Mul ( RCCU_PLL1_Mul_12, RCCU_PLL1_Mul_16, RCCU_PLL1_Mul_20, -* RCCU_PLL1_Mul_24 ) -* : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, -* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7) -* Return : None -*******************************************************************************/ -void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div ) -{ - u32 Tmp = 0; - - if (RCCU_FrequencyValue(RCCU_CLK2)>3000000) - RCCU->PLL1CR|=RCCU_FREEN_Mask; - else - RCCU->PLL1CR&=~RCCU_FREEN_Mask; - - Tmp = ( RCCU->PLL1CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index ); - RCCU->PLL1CR = ( Tmp & ~RCCU_DX_Mask ) | New_Div | 0x40; -} - -/******************************************************************************* -* Function Name : RCCU_PLL2Config -* Description : Configures the PLL2 div & mul factors. -* Input : New_Mul ( RCCU_PLL2_Mul_12, RCCU_PLL2_Mul_16, RCCU_PLL2_Mul_20, -* RCCU_Mul_PLL2_28 ) -* : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, -* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7) -* Return : None -*******************************************************************************/ -void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div ) -{ - u32 Tmp = ( PCU->PLL2CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index ); - PCU->PLL2CR = ( Tmp & ~RCCU_DX_Mask ) | ( New_Div | RCCU_FREEN_Mask ); -} - -/******************************************************************************* -* Function Name : RCCU_RCLKSourceConfig -* Description : Selects the RCLK source clock -* Input : New_Clock ( RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 ) -* Return : None -*******************************************************************************/ -void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock ) -{ - switch ( New_Clock ) - { - case RCCU_CLOCK2 :{ /* Resets the CSU_Cksel bit in clk_flag */ - RCCU->CFR &= ~RCCU_CSU_CKSEL_Mask; - /* Set the CK2_16 Bit in the CFR */ - RCCU->CFR |= RCCU_CK2_16_Mask; - /* Deselect The CKAF */ - RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; - /* switch off the PLL1 */ - RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\ - |0x00000003) & ~RCCU_FREEN_Mask; - break;} - case RCCU_CLOCK2_16 :{ /* ReSet the CK2_16 Bit in the CFR */ - RCCU->CFR &= ~RCCU_CK2_16_Mask; - /* Deselect The CKAF */ - RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; - /* switch off the PLL1 */ - RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\ - |0x00000003) & ~RCCU_FREEN_Mask; - break;} - case RCCU_PLL1_Output:{ /* Set the CK2_16 Bit in the CFR */ - RCCU->CFR = RCCU->CFR | RCCU_CK2_16_Mask; - /* Waits the PLL1 to lock if DX bits are different from '111' */ - /* If all DX bit are set the PLL lock flag in meaningless */ - if (( RCCU->PLL1CR & 0x0007 ) != 7) - while(!(RCCU->CFR & RCCU_LOCK_Mask)); - /* Deselect The CKAF */ - RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; - /* Select The CSU_CKSEL */ - RCCU->CFR |= RCCU_CSU_CKSEL_Mask; - break;} - case RCCU_RTC_CLOCK : {RCCU->CCR |= 0x04; - break;} - } -} - -/******************************************************************************* -* Function Name : RCCU_RCLKClockSource -* Description : Returns the current RCLK source clock -* Input : None -* Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2, RCCU_RTC_CLOCK -*******************************************************************************/ -RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void ) -{ - if ((RCCU->CCR & 0x04)==0x04) - return RCCU_RTC_CLOCK; - - else if ((RCCU->CFR & RCCU_CK2_16_Mask)==0) - return RCCU_CLOCK2_16; - - else if (RCCU->CFR & RCCU_CSU_CKSEL_Mask) - return RCCU_PLL1_Output; - - else - return RCCU_CLOCK2; -} - -/******************************************************************************* -* Function Name : RCCU_USBClockSource -* Description : Gets the RCLK source clock -* Input : None -* Return : RCCU_USB_Clocks ( RCCU_PLL2_Output, RCCU_USBCK ) -*******************************************************************************/ -RCCU_USB_Clocks RCCU_USBClockSource ( void ) -{ - if ((PCU->PLL2CR & RCCU_USBEN_Mask ) >> RCCU_USBEN_Index == 1 ) - return RCCU_PLL2_Output; - else return RCCU_USBCK; -} - -/******************************************************************************* -* Function Name : RCCU_FrequencyValue -* Description : Calculates & Returns any internal RCCU clock frequency -* passed in parametres -* Input : RCCU_Clocks ( RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, RCCU_PCLK, RCCU_FCLK ) -* Return : u32 -*******************************************************************************/ -u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk ) -{ - u32 Tmp; - u8 Div = 0; - u8 Mul = 0; - RCCU_RCLK_Clocks CurrentRCLK; - - Tmp = ( RCCU_Div2Status() == SET )? RCCU_Main_Osc / 2 : RCCU_Main_Osc; - - if ( Internal_Clk == RCCU_CLK2 ) - { - Div = 1; - Mul = 1; - } - else - { CurrentRCLK = RCCU_RCLKClockSource (); - switch ( CurrentRCLK ){ - case RCCU_CLOCK2_16 : Div = 16; - Mul = 1; - break; - case RCCU_CLOCK2 : Div = 1; - Mul = 1; - break; - case RCCU_PLL1_Output :{Mul=(RCCU->PLL1CR & RCCU_MX_Mask ) >> RCCU_MX_Index; - switch ( Mul ) - {case 0: Mul = 20; break; - case 1: Mul = 12; break; - case 2: Mul = 24; break; - case 3: Mul = 16; break; - } - Div = ( RCCU->PLL1CR & RCCU_DX_Mask ) + 1; - break;} - case RCCU_RTC_CLOCK : Mul = 1; - Div = 1; - Tmp = RCCU_RTC_Osc; - break;}} - - switch ( Internal_Clk ){ - case RCCU_MCLK :{Div <<= PCU->MDIVR & RCCU_FACT_Mask; - break;} - case RCCU_PCLK :{Div <<=(PCU->PDIVR & RCCU_FACT2_Mask ) >> RCCU_FACT2_Index; - break;} - case RCCU_FCLK :{Div <<= PCU->PDIVR & 0x3; - break;}} - - return (Tmp * Mul) / Div; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/rtc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/rtc.c deleted file mode 100644 index 7f705ef94..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/rtc.c +++ /dev/null @@ -1,225 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : rtc.c -* Author : MCD Application Team -* Date First Issued : 09/30/2003 -* Description : This file provides all the RTC software functions -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "rtc.h" - -/* Second interrupt */ -#define RTC_SI_Mask 0x0001 - -/* Alarm interrupt */ -#define RTC_AI_Mask 0x0002 - -/* OverFlow interrupt */ -#define RTC_OWI_Mask 0x0004 - -/* Global interrupt */ -#define RTC_GI_Mask 0x0008 - -/* Configuration Flag Mask */ -#define RTC_CNF_Mask 0x0010 - -/* Operation OFF flag */ -#define RTC_RTOFF_Mask 0x0020 - -/******************************************************************************* -* Function Name : RTC_CounterConfig -* Description : This routine is used to update the RTC counter value -* Input : The new counter value. -* Return : None -*******************************************************************************/ -void RTC_CounterConfig (u32 CounterValue) -{ - /* Wait For Last Task Completition */ - RTC_WaitForLastTask(); - - /* Enter to configuration mode */ - RTC_EnterCfgMode(); - - /* Update the RTC counter register with the new time and date */ - /* Update the CNTL register */ - RTC->CNTL = (u16)CounterValue; - - /* Wait For Last Task Completition */ - RTC_WaitForLastTask(); - - /* Update the CNTH register */ - RTC->CNTH = (u16)(CounterValue >> 16); - - /* Wait For Last Task Completition */ - RTC_WaitForLastTask(); - - /* Exit From Configuration Mode */ - RTC_ExitCfgMode (); -} - -/******************************************************************************* -* Function Name : RTC_PrescalerConfig -* Description : This routine is used to set the RTC 20-bit Prescaler Value -* Input : The New prescaler Value -* Return : None -*******************************************************************************/ -void RTC_PrescalerConfig (u32 Xprescaler) -{ - if ( RTC_PrescalerValue () != Xprescaler ) - { - /* Wait For Last Task Completion */ - RTC_WaitForLastTask (); - - /* Enter In Configuration Mode */ - RTC_EnterCfgMode (); - - /* Set the prescaler MSB part */ - RTC->PRLH = (Xprescaler & 0x000F0000) >> 16; - - /* Wait For Last Task Completion */ - RTC_WaitForLastTask(); - - /* Set the prescaler LSB part */ - RTC->PRLL = (Xprescaler & 0x0000FFFF); - - /* Wait For Last Task Completion */ - RTC_WaitForLastTask(); - - /* Exit From Configuration Mode */ - RTC_ExitCfgMode (); - } -} - -/******************************************************************************* -* Function Name : RTC_AlarmConfig -* Description : This routine is used to set the RTC alarm Value -* Input : an u32 value that holds the Real Time clock alarm time. -* Return : None -*******************************************************************************/ -void RTC_AlarmConfig (u32 Xalarm) -{ - /* Wait For Last Task Completion */ - RTC_WaitForLastTask (); - - /* Enter In Configuration Mode */ - RTC_EnterCfgMode (); - - /* Set The MSB part of the Alarm Time */ - RTC->ALRH = (Xalarm & 0xFFFF0000) >> 16; - - /* Wait For Last Task Completion */ - RTC_WaitForLastTask(); - - /* Set The LSB part of the Alarm Time */ - RTC->ALRL = (Xalarm & 0x0000FFFF); - - /* Wait For Last Task Completion */ - RTC_WaitForLastTask(); - - /* Exit From Configuration Mode */ - RTC_ExitCfgMode (); -} - -/******************************************************************************* -* Function Name : RTC_FlagClear -* Description : This routine is used to clear the RTC flags -* Input : an RTC flag RTC_GIR, RTC_OWIR, RTC_AIR or RTC_SIR -* Return : None -*******************************************************************************/ -void RTC_FlagClear (RTC_FLAGS Xflag) -{ - /* Wait For Last Task Completion */ - RTC_WaitForLastTask(); - - /* Enter In Configuration Mode */ - RTC_EnterCfgMode(); - - /* Clear an RTC flag */ - RTC->CRL &= ~Xflag; - - /* Wait For Last Task Completion */ - RTC_WaitForLastTask(); - - /* Exit From Configuration Mode */ - RTC_ExitCfgMode (); - } - -/******************************************************************************* -* Function Name : RTC_ITClear -* Description : This routine is used to clear a RTC interrupt pending bit -* Input : a RTC interrupt: RTC_GIT, RTC_OWIT, RTC_AIT or RTC_SIT -* Return : None -*******************************************************************************/ -void RTC_ITClear (RTC_IT Xrtcit) -{ - /* Wait For Last Task Completion */ - RTC_WaitForLastTask(); - - /* Enter In Configuration Mode */ - RTC_EnterCfgMode(); - - /* Clears an RTC interrupt */ - RTC->CRL &= ~Xrtcit; - - /* Wait For Last Task Completion */ - RTC_WaitForLastTask (); - - /* Exit From Configuration Mode */ - RTC_ExitCfgMode (); -} - -/******************************************************************************* -* Function Name : RTC_EnterCfgMode -* Description : This routine is used to enter in the Configuration Mode -* Input : None -* Return : None -*******************************************************************************/ -void RTC_EnterCfgMode(void) -{ - /* Set the CNF flag to enter in the Configuration Mode */ - RTC->CRL |= RTC_CNF_Mask; - - /* Wait For Last Task Completion */ - RTC_WaitForLastTask (); -} - -/******************************************************************************* -* Function Name : RTC_ExitCfgMode -* Description : This routine is used to exit from the Configuration Mode -* Input : None -* Return : None -*******************************************************************************/ -void RTC_ExitCfgMode(void) -{ - /* Reset the CNF flag to exit from the Configuration Mode */ - RTC->CRL &= ~RTC_CNF_Mask; - - /* Wait For Last Task Completion */ - RTC_WaitForLastTask (); -} - -/******************************************************************************* -* Function Name : RTC_WaitForLastTask -* Description : This routine waits for the last task completion -* Input : None -* Return : None -*******************************************************************************/ -void RTC_WaitForLastTask(void) -{ - /* Loop until the Last operation Completion */ - while (!(RTC->CRL & RTC_RTOFF_Mask)); -} -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/tim.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/tim.c deleted file mode 100644 index 6f59a6269..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/tim.c +++ /dev/null @@ -1,234 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : tim.c -* Author : MCD Application Team -* Date First Issued : 09/08/2003 -* Description : This file provides all the TIM software functions -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "tim.h" - -/******************************************************************************* -* Function Name : TIM_Init -* Description : This routine is used to Initialize the TIM peripheral -* registers to their default values. -* Input : TIM Timer to Initialize(TIM0, TIM1, TIM2, TIM3). -* Return : None. -*******************************************************************************/ -void TIM_Init( TIM_TypeDef *TIMx ) -{ - TIMx->CR1 = 0x0000; - TIMx->CR2 = 0x0000; - TIMx->SR = 0x0000; -} - -/******************************************************************************* -* Function Name : TIM_ICAPModeConfig -* Description : This routine is used to configure the input capture feature -* Input : (1) TIM Timer (TIM0, TIM1, TIM2, TIM3). -* : (2) Input Capture Channel (TIM_CHANNEL_A, TIM_CHANNEL_B). -* : (3) Active Edge :(TIM_RISING,TIM_FALLING). -* Return : None. -*******************************************************************************/ -void TIM_ICAPModeConfig ( TIM_TypeDef *TIMx, - TIM_Channels Xchannel, - TIM_Clock_Edges Xedge ) -{ - switch (Xchannel) - { - case TIM_CHANNEL_A : - if (Xedge == TIM_RISING) TIMx->CR1 |= TIM_IEDGA_Mask; else TIMx->CR1 &= ~TIM_IEDGA_Mask; - break; - case TIM_CHANNEL_B : - if (Xedge == TIM_RISING) TIMx->CR1 |= TIM_IEDGB_Mask; else TIMx->CR1 &= ~TIM_IEDGB_Mask; - break; - } -} - -/******************************************************************************* -* Function Name : TIM_OCMPModeConfig -* Description : This routine is used to configure the output compare feature. -* Input : (1) TIM Timer(TIM0, TIM1, TIM2, TIM3). -* : (2) OCMP Channel (TIM_CHANNEL_A, TIM_CHANNEL_B). -* : (3) Pulse Length. -* : (4) OC_Mode (TIM_TIMING,TIM_WAVE). -* : (5) Level (TIM_HIGH,TIM_LOW). -* Return : None. -*******************************************************************************/ -void TIM_OCMPModeConfig ( TIM_TypeDef *TIMx, - TIM_Channels Xchannel, - u16 XpulseLength, - TIM_OC_Modes Xmode, - TIM_Logic_Levels Xlevel ) -{ - u16 Tmp1 = 0x0000; - u16 Tmp2 = TIMx->CR2; - - TIMx->CR2 = 0x0000; - /* Start The TIM Counter */ - TIMx->CR1 = TIM_EN_Mask; - /* Update the CR2 Register */ - TIMx->CR2 = Tmp2; - switch ( Xmode ) - { - case TIM_TIMING : - /* Output Compare Used only for Internal Timing Operation */ - Tmp1 = Xchannel == TIM_CHANNEL_A ? Tmp1 & ~TIM_OCAE_Mask : Tmp1 & ~TIM_OCBE_Mask; - break; - case TIM_WAVE : - /* Output Compare Used for external wave generation */ - Tmp1 = Xchannel == TIM_CHANNEL_A ? TIM_OCAE_Mask : TIM_OCBE_Mask; - if ( Xlevel == TIM_HIGH ) - Tmp1 = Xchannel == TIM_CHANNEL_A ? Tmp1 | TIM_OLVLA_Mask : Tmp1 | TIM_OLVLB_Mask; - else - Tmp1 = Xchannel == TIM_CHANNEL_A ? Tmp1 & ~TIM_OLVLA_Mask : Tmp1 & ~TIM_OLVLB_Mask; - break; - } - if ( Xchannel == TIM_CHANNEL_A ) - TIMx->OCAR = (XpulseLength); - else - TIMx->OCBR = ( XpulseLength); - TIMx->CNTR = 0x0000; - TIMx->CR1 |= Tmp1; -} - -/******************************************************************************* -* Function Name : TIM_OPModeConfig -* Description : This routine is used to configure the one pulse mode. -* Input : (1) TIM Timer(TIM0, TIM1, TIM2, TIM3). -* : (2) XpulseLength : Length of the pulse. -* : (3) Level1 :Level during the pulse (TIM_HIGH,TIM_LOW). -* : (4) Level2 :Level after the pulse (TIM_HIGH,TIM_LOW). -* : (5) Activation Edge :High or Low on ICAP A (TIM_RISING, -* TIM_FALLING). -* Return : None. -*******************************************************************************/ -void TIM_OPModeConfig ( TIM_TypeDef *TIMx, - u16 XpulseLength, - TIM_Logic_Levels XLevel1, - TIM_Logic_Levels XLevel2, - TIM_Clock_Edges Xedge ) -{ - u16 Tmp = 0; - - /* Set the Level During the pulse */ - if (XLevel1 == TIM_HIGH) Tmp |= TIM_OLVLB_Mask; - /* Set the Level after After the pulse */ - if (XLevel2 == TIM_HIGH) Tmp |= TIM_OLVLA_Mask; - /* Set the Activation Edge on the INCAP 1 */ /* to be verified*/ - if (Xedge == TIM_RISING) Tmp |= TIM_IEDGA_Mask; - /* Set the Output Compare Function */ - Tmp |= TIM_OCAE_Mask; - /* Set the One pulse mode */ - Tmp |= TIM_OPM_Mask; - /* Update the CR1 register Value */ - TIMx->CR1 = Tmp; - /* Set the Pulse length */ - TIMx->OCAR = XpulseLength; -} - -/******************************************************************************* -* Function Name : TIM_PWMOModeConfig -* Description : This routine is used to configure the PWM in output mode. -* Input : (1) TIM Timer(TIM0, TIM1, TIM2, TIM3). -* : (2) DutyCycle. -* : (3) Level 1 : During the Duty Cycle(TIM_HIGH,TIM_LOW). -* : (4) Full period -* : (5) Level 2 : After the pulse(TIM_HIGH,TIM_LOW). -* Return : None. -*******************************************************************************/ -void TIM_PWMOModeConfig ( TIM_TypeDef *TIMx, - u16 XDutyCycle, - TIM_Logic_Levels XLevel1, - u16 XFullperiod, - TIM_Logic_Levels XLevel2) -{ - u16 Tmp = TIMx->CR1; - /* Set the level during the pulse */ - Tmp = XLevel1 == TIM_HIGH ? Tmp | TIM_OLVLB_Mask : Tmp & ~TIM_OLVLB_Mask; - /* Set the level after After the pulse */ - Tmp = XLevel2 == TIM_HIGH ? Tmp | TIM_OLVLA_Mask : Tmp & ~TIM_OLVLA_Mask; - /* Set the OCAE */ - Tmp |= TIM_OCAE_Mask; - /* Set the PWM Bit */ - Tmp |= TIM_PWM_Mask; - /* Update the CR1 */ - TIMx->CR1 = Tmp; - /* Set the Duty Cycle value */ - if ( XDutyCycle < 5 ) XDutyCycle = 5; - TIMx->OCAR = XDutyCycle - 5; - /* Set the Full Period */ - TIMx->OCBR = XFullperiod - 5; -} - -/******************************************************************************* -* Function Name : TIM_PWMIModeConfig -* Description : This routine is used to configure the PWM in input mode. -* Input : (1) TIM Timer(TIM0, TIM1, TIM2, TIM3). -* : (2) First Activation Edge(TIM_RISING,TIM_FALLING). -* Output : None. -*******************************************************************************/ -void TIM_PWMIModeConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge ) -{ - u16 Tmp = TIMx->CR1; - /* Set the first edge Level */ - Tmp = Xedge == TIM_RISING ? Tmp | TIM_IEDGA_Mask : Tmp & ~TIM_IEDGA_Mask; - /* Set the Second edge Level ( Opposit of the first level )*/ - Tmp = Xedge == TIM_FALLING ? Tmp | TIM_IEDGB_Mask : Tmp & ~TIM_IEDGB_Mask; - /* Set the PWM I Bit */ - Tmp |= TIM_PWMI_Mask; - /* Update the CR1 */ - TIMx->CR1 = Tmp; -} - -/******************************************************************************* -* Function Name : TIM_PWMIValue -* Description : This routine is used to get the PWMI values. -* Input : TIM Timer(TIM0, TIM1, TIM2, TIM3). -* Return : PWMI_parameters(Pulse, Period). -*******************************************************************************/ -PWMI_parameters TIM_PWMIValue ( TIM_TypeDef *TIMx ) -{ - PWMI_parameters Tmp; - Tmp.Pulse = TIMx->ICBR; - Tmp.Period = TIMx->ICAR; - return Tmp; -} - -/******************************************************************************* -* Function Name : TIM_CounterConfig -* Description : This routine is used to configure the Timer conuter. -* Input : (1) TIM Timer(TIM0, TIM1, TIM2, TIM3). -* : (2) Xoperation(TIM_START, TIM_STOP, TIM_CLEAR). -* Return : None. -*******************************************************************************/ -void TIM_CounterConfig ( TIM_TypeDef *TIMx, TIM_CounterOperations Xoperation) -{ - switch ( Xoperation ) - { - case TIM_START : - TIMx->CR1 |= TIM_EN_Mask; - break; - case TIM_STOP : - TIMx->CR1 &= ~TIM_EN_Mask; - break; - case TIM_CLEAR : - TIMx->CNTR = 0x1234; - break; - } -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/uart.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/uart.c deleted file mode 100644 index b7e48c0c5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/uart.c +++ /dev/null @@ -1,416 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : uart.c -* Author : MCD Application Team -* Date First Issued : 06/08/2003 -* Description : This file provides all the UART software functions -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "uart.h" - -/******************************************************************************* -* Function Name : UART_Init -* Description : This function initializes the selected UART registers to -* their reset values -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Output : None -* Return : None -*******************************************************************************/ -void UART_Init(UART_TypeDef *UARTx) -{ - UARTx->CR = 0x0000; - UARTx->IER = 0x0000; - (void)UARTx->RxBUFR; - UARTx->RxRSTR = 0xFFFF; - UARTx->TxRSTR = 0xFFFF; - UARTx->TOR = 0x0000; - UARTx->GTR = 0x0000; -} - -/******************************************************************************* -* Function Name : UART_BaudRateConfig -* Description : This function configures the baud rate of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : u32 The baudrate value -* Output : None -* Return : None -*******************************************************************************/ -void UART_BaudRateConfig(UART_TypeDef *UARTx, u32 BaudRate) -{ - UARTx->BR = (u16)(RCCU_FrequencyValue(RCCU_FCLK)/(16*BaudRate)); -} - -/******************************************************************************* -* Function Name : UART_Config -* Description : This function configures the baudrate, the mode, the data -* parity and the number of stop bits of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : u32 The baudrate value -* Input 3 : The parity type, it can be UART_EVEN_PARITY, UART_ODD_PARITY -* or UART_NO_PARITY -* Input 4 : The number of stop bits UART_0_5_StopBits, UART_1_StopBits, -* UART_1_5_StopBits or UART_2_StopBits -* Input 5 : The UART mode, it can be -* UARTM_8D for 8-bit data format -* UARTM_7D_P for 7-bit data + parity format -* UART_9D for 9-bit data format -* UART_8D_W for 8-bit data + wake-up bit format -* UART_8D_P for 8-bit data + parity bit format -* Output : None -* Return : None -*******************************************************************************/ -void UART_Config(UART_TypeDef *UARTx, u32 BaudRate, UARTParity_TypeDef Parity, - UARTStopBits_TypeDef StopBits, UARTMode_TypeDef Mode) -{ - UART_ModeConfig(UARTx, Mode); - UART_BaudRateConfig(UARTx, BaudRate); - UART_ParityConfig(UARTx, Parity); - UART_StopBitsConfig(UARTx, StopBits); -} - -/******************************************************************************* -* Function Name : UART_ItConfig -* Description : This function enables or disables one or several interrupt -* sources of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : The new interrupt flag or flags -* Input 3 : ENABLE or DISABLE -* Output : None -* Return : None -* Note : The UART interrupt flags are listed in the file uart.h -*******************************************************************************/ -void UART_ItConfig(UART_TypeDef *UARTx, u16 UART_Flag, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->IER|=UART_Flag; else UARTx->IER&=~UART_Flag; -} - -/******************************************************************************* -* Function Name : UART_FifoConfig -* Description : This function enables or disables the Rx and Tx FIFOs of -* the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_FifoConfig(UART_TypeDef *UARTx, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->CR|=0x0400; else UARTx->CR&=~0x0400; -} - -/******************************************************************************* -* Function Name : UART_FifoReset -* Description : This function resets the Rx and the Tx FIFOs of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : UART_RxFIFO or UART_TxFIFO -* Output : None -* Return : None -*******************************************************************************/ -void UART_FifoReset(UART_TypeDef *UARTx, UARTFIFO_TypeDef FIFO) -{ - if (FIFO==UART_RxFIFO) UARTx->RxRSTR=0xFFFF; else UARTx->TxRSTR=0xFFFF; -} - -/******************************************************************************* -* Function Name : UART_LoopBackConfig -* Description : This function enables or disables the loop back mode of -* the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_LoopBackConfig(UART_TypeDef *UARTx, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->CR|=0x0040; else UARTx->CR&=~0x0040; -} - -/******************************************************************************* -* Function Name : UART_RxConfig -* Description : This function enables or disables the UART data reception. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_RxConfig(UART_TypeDef *UARTx, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->CR|=0x0100; else UARTx->CR&=~0x0100; -} - -/******************************************************************************* -* Function Name : UART_OnOffConfig -* Description : This function sets On/Off the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_OnOffConfig(UART_TypeDef *UARTx, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->CR|=0x0080; else UARTx->CR&=~0x0080; -} - -/******************************************************************************* -* Function Name : UART_ByteSend -* Description : This function sends a data byte to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer on the data byte to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_ByteSend(UART_TypeDef *UARTx, u8 *Data) -{ - /* if FIFO ENABLED */ - if (UARTx->CR & 0x0400) - - /* Wait until the TxFIFO contains at least 1 free place */ - while((UARTx->SR & UART_TxFull)); - - /* if FIFO DISABLED */ - else - - /* Wait until the transmit shift register is empty */ - while (!(UARTx->SR & UART_TxEmpty)); - - UARTx->TxBUFR = *Data; -} - -/******************************************************************************* -* Function Name : UART_9BitByteSend -* Description : This function sends a 9-bit data to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer on the 9-bit data to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_9BitByteSend(UART_TypeDef *UARTx, u16 *Data) -{ - /* if FIFO ENABLED */ - if(UARTx->CR & 0x0400) - - /* Wait until the TxFIFO contains at least 1 free place */ - while((UARTx->SR & UART_TxFull)); - - /* if FIFO DISABLED */ - else - - /* Wait until the transmit shift register is empty */ - while (!(UARTx->SR & UART_TxEmpty)); - - UARTx->TxBUFR = ((*Data) & 0x01FF); -} - -/******************************************************************************* -* Function Name : UART_DataSend -* Description : This function sends several data bytes to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer on the data to send -* Input 3 : The data length in bytes -* Output : None -* Return : None -*******************************************************************************/ -void UART_DataSend(UART_TypeDef *UARTx, u8 *Data, u8 DataLength) -{ - - while(DataLength--) - { - UART_ByteSend(UARTx,Data); - Data++; - } -} - -/******************************************************************************* -* Function Name : UART_9BitDataSend -* Description : This function sends several 9-bit data to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer to the data to send -* Input 3 : The data length -* Output : None -* Return : None -*******************************************************************************/ -void UART_9BitDataSend(UART_TypeDef *UARTx, u16 *Data, u8 DataLength) -{ - while(DataLength--) - { - UART_9BitByteSend(UARTx,Data); - Data++; - } -} - -/******************************************************************************* -* Function Name : UART_StringSend -* Description : This function sends a string to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer on the string to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_StringSend(UART_TypeDef *UARTx, u8 *String) -{ - u8 *Data=String; - while(*Data != '\0') - UART_ByteSend(UARTx, Data++); - *Data='\0'; - UART_ByteSend(UARTx, Data); -} - -/******************************************************************************* -* Function Name : UART_ByteReceive -* Description : This function gets a data byte from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer on the data where the data will be stored -* Input 3 : The time-out period -* Output : The received 8-bit data -* Return : The UARTx.SR register content -*******************************************************************************/ -u16 UART_ByteReceive(UART_TypeDef *UARTx, u8 *Data, u8 TimeOut) -{ - u16 wStatus = 0; - -/* reload the Timeout counter */ - UARTx->TOR=TimeOut; - -/* while the UART_RxFIFO is empty and no Timeoutidle */ - while (!((wStatus=UARTx->SR) & (UART_TimeOutIdle|UART_RxHalfFull|UART_RxBufFull))); - -/* then read the Receive Buffer Register */ - *Data = (u8)UARTx->RxBUFR; - - return wStatus; -} - -/******************************************************************************* -* Function Name : UART_9BitByteReceive -* Description : This function gets a 9-bit data from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer on the buffer where the data will be stored -* Input 3 : The time-out period value -* Output : The received 9-bit data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_9BitByteReceive(UART_TypeDef *UARTx, u16 *Data, u8 TimeOut) -{ - u16 wStatus = 0; - -/* reload the Timeout counter */ - UARTx->TOR=TimeOut; - -/* while the UART_RxFIFO is empty and no Timeoutidle */ - while (!((wStatus=UARTx->SR) & (UART_TimeOutIdle|UART_RxHalfFull|UART_RxBufFull))); - -/* then read the RxBUFR*/ - *Data = (u16)UARTx->RxBUFR; - return wStatus; -} - -/******************************************************************************* -* Function Name : UART_DataReceive -* Description : This function gets 8 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer on the buffer where the data will be stored -* Input 3 : The data length -* Input 4 : The time-out period value -* Output : The received 8-bit data buffer -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_DataReceive(UART_TypeDef *UARTx, u8 *Data, u8 DataLength, u8 TimeOut) -{ - u16 wStatus = 0; - while(DataLength--) - wStatus=UART_ByteReceive(UARTx,Data++,TimeOut); - return wStatus; -} - -/******************************************************************************* -* Function Name : UART_9BitDataReceive -* Description : This function gets several 9-bits data from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer on the buffer where the data will be stored -* Input 3 : The data length -* Input 4 : The time-out value -* Output : The received 9-bit data buffer -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_9BitDataReceive(UART_TypeDef *UARTx, u16 *Data, u8 DataLength, u8 TimeOut) -{ - u16 wStatus = 0; - - while(DataLength--) - wStatus=UART_9BitByteReceive(UARTx,Data++,TimeOut); - return wStatus; -} - -/******************************************************************************* -* Function Name : UART_StringReceive -* Description : This function gets 8-bit data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the selected UART -* Input 2 : A pointer on the buffer where the string will be stored -* Output : The received string -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_StringReceive(UART_TypeDef *UARTx, u8 *Data) -{ - u8 *pSTRING=Data; - u16 wStatus = 0; - - do - { - /* while the UART_RxFIFO is empty */ - while (!((wStatus=UARTx->SR) & (UART_RxHalfFull|UART_RxBufFull))); - - /* then read the RxBUFR */ - *(pSTRING++) = (u8)UARTx->RxBUFR; - - } while((*(pSTRING - 1)!=0x0D)&(*(pSTRING - 1)!='\0')); - - *(pSTRING - 1)='\0'; - - return wStatus; -} - -#ifdef USE_SERIAL_PORT -/******************************************************************************* -* Function Name : sendchar -* Description : This function sends a character to the selected UART. -* Input 1 : A pointer on the character to send. -* Output : None -* Return : None -*******************************************************************************/ -void sendchar( char *ch ) -{ - #ifdef USE_UART0 - #define UARTx UART0 - #endif /* Use_UART0 */ - - #ifdef USE_UART1 - #define UARTx UART1 - #endif /* Use_UART1 */ - - #ifdef USE_UART2 - #define UARTx UART2 - #endif /* Use_UART2 */ - - #ifdef USE_UART3 - #define UARTx UART3 - #endif /* Use_UART3 */ - - UART_ByteSend(UARTx,(u8 *)ch); -} -#endif /* USE_SERIAL_PORT */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/wdg.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/wdg.c deleted file mode 100644 index 14711765f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/wdg.c +++ /dev/null @@ -1,85 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : WDG.c -* Author : MCD Application Team -* Date First Issued : 10/24/2003 -* Description : This file provides all the WDG software functions -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "wdg.h" - -#ifndef abs - #define abs(x) ((x)>0 ? (x) : -(x)) -#endif - -/******************************************************************************* -* Function Name : FindFactors -* Description : Search for the best (a,b) values that fit n = a*b -* with the following constraints: 1<=a<=256, 1<=b<=65536 -* Input 1 : n: the number to decompose -* Input/Output 2 : a: a pointer to the first factor -* Input/Output 3 : b: a pointer to the second factor -* Return : None -*******************************************************************************/ -static void FindFactors(u32 n, u16 *a, u32 *b) -{ - u32 b0; - u16 a0; - long err, err_min=n; - - *a = a0 = ((n-1)/65536ul) + 1; - *b = b0 = n / *a; - - for (; *a <= 256; (*a)++) - { - *b = n / *a; - err = (long)*a * (long)*b - (long)n; - if (abs(err) > (*a / 2)) - { - (*b)++; - err = (long)*a * (long)*b - (long)n; - } - if (abs(err) < abs(err_min)) - { - err_min = err; - a0 = *a; - b0 = *b; - if (err == 0) break; - } - } - - *a = a0; - *b = b0; -} - -/******************************************************************************* -* Function Name : WDG_PeriodValueConfig -* Description : Set the prescaler and counter reload value -* Input : Amount of time (us) needed -* Return : None -*******************************************************************************/ -void WDG_PeriodValueConfig ( u32 Time ) -{ - u16 a; - u32 n, b; - - n = Time * (RCCU_FrequencyValue(RCCU_PCLK) / 1000000); - FindFactors(n, &a, &b); - WDG->PR = a - 1; - WDG->VR = b - 1; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/xti.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/xti.c deleted file mode 100644 index 7755fba40..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/libstr71x/xti.c +++ /dev/null @@ -1,88 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : xti.c -* Author : MCD Application Team -* Date First Issued : 06/08/2003 -* Description : This file provides all the XTI software functions. -******************************************************************************** -* History: -* 13/01/2006 : V3.1 -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "xti.h" - -/******************************************************************************* -* Function Name : XTI_Init -* Description : This routine is used to initialize the XTI cell -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -void XTI_Init(void) -{ - XTI->SR=0x00; - XTI->MRH=0x00; - XTI->MRL=0x00; - XTI->TRH=0x00; - XTI->TRL=0x00; - XTI->PRH=0x00; - XTI->PRL=0x00; - XTI->CTRL=0x00; /* Write the STOP bit twice to reset the STOP state machine */ - XTI->CTRL=0x00; -} - -/******************************************************************************* -* Function Name : XTI_LineModeConfig -* Description : This routine is used to configure the trigger edge. -* Input 1 : Lines to be configured. -* Input 2 : The trigger edge can be FallingEdge or RisingEdge. -* Output : None -* Return : None -*******************************************************************************/ -void XTI_LineModeConfig(u16 Lines, XTITriggerEdge_TypeDef TriggerEdge) -{ - if(TriggerEdge == XTI_FallingEdge) - { - XTI->TRL &= ~Lines; - XTI->TRH &= ~(Lines>>8)&0x00FF; - } - else - { - XTI->TRL |= Lines; - XTI->TRH |= (Lines>>8)&0x00FF; - } -} - -/******************************************************************************* -* Function Name : XTI_LineConfig -* Description : This routine is used to enable and disable lines interrupts -* Input 1 : Lines to be configured. -* Input 2 : NewState can be ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void XTI_LineConfig(u16 Lines, FunctionalState NewState) -{ - if(NewState) - { - XTI->MRL |= Lines; - XTI->MRH |= (Lines>>8)&0x00FF; - } - else - { - XTI->MRL &= ~Lines; - XTI->MRH &= ~(Lines>>8)&0x00FF; - } -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/port/port.h deleted file mode 100644 index d78d6e567..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/port/port.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * FreeModbus Libary: STR71x Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -#include "assert.h" -#include "FreeRTOS.h" - -/* work aroung a problem when inline is also defined in 71x_conf.h */ -#ifdef INLINE -#undef INLINE -#endif - -#define INLINE - -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#define ENTER_CRITICAL_SECTION( ) portENTER_CRITICAL( ) -#define EXIT_CRITICAL_SECTION( ) portEXIT_CRITICAL( ) - -typedef char BOOL; - -typedef unsigned char UCHAR; -typedef char CHAR; - -typedef unsigned short USHORT; -typedef short SHORT; - -typedef unsigned long ULONG; -typedef long LONG; - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/port/portevent.c deleted file mode 100644 index d01d7e745..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/port/portevent.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * FreeModbus Libary: STR71x Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "assert.h" - -/* ----------------------- FreeRTOS -----------------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static xQueueHandle xMBPortQueueHdl; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - xMBPortQueueHdl = xQueueCreate( 1, sizeof( eMBEventType ) ); - return xMBPortQueueHdl != NULL ? TRUE : FALSE; -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - portBASE_TYPE xEventSent = pdFALSE; - - xEventSent = xQueueSendFromISR( xMBPortQueueHdl, &eEvent, xEventSent ); - return xEventSent == pdTRUE ? TRUE : FALSE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - BOOL xEventHappened = FALSE; - - if( xQueueReceive( xMBPortQueueHdl, eEvent, portMAX_DELAY ) == pdTRUE ) - { - xEventHappened = TRUE; - } - return xEventHappened; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/port/portserial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/port/portserial.c deleted file mode 100644 index e99c5393a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/port/portserial.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * FreeModbus Libary: STR71x Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "assert.h" - -/* ----------------------- FreeRTOS includes --------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" - -/* ----------------------- STR71X includes ----------------------------------*/ -#include "gpio.h" -#include "eic.h" -#include "uart.h" -#include "tim.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_UART_DEV ( UART0 ) -#define MB_UART_RX_PORT ( GPIO0 ) -#define MB_UART_RX_PIN ( 8 ) -#define MB_UART_TX_PORT ( GPIO0 ) -#define MB_UART_TX_PIN ( 9 ) -#define MB_UART_IRQ_CH ( UART0_IRQChannel ) -#define MB_UART_TX_QUEUE_LEN ( 8 ) -#define MB_IRQ_PRIORITY ( 1 ) - -/* ----------------------- Static functions ---------------------------------*/ -void prvvMBSerialIRQHandler( void ) __attribute__ ( ( naked ) ); - -static BOOL prvMBPortTXIsEnabled( ); - -static BOOL prvMBPortRXIsEnabled( ); - -/* ----------------------- Start implementation -----------------------------*/ - -BOOL -xMBPortSerialInit( UCHAR ucPort, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity ) -{ - BOOL xResult = TRUE; - UARTParity_TypeDef eUARTParity; - UARTMode_TypeDef eUARTMode; - - ( void )ucPort; - - switch ( eParity ) - { - case MB_PAR_EVEN: - eUARTParity = UART_EVEN_PARITY; - break; - case MB_PAR_ODD: - eUARTParity = UART_ODD_PARITY; - break; - case MB_PAR_NONE: - eUARTParity = UART_NO_PARITY; - break; - } - - switch ( ucDataBits ) - { - case 7: - if( eParity == MB_PAR_NONE ) - { - /* not supported by our hardware. */ - xResult = FALSE; - } - else - { - eUARTMode = UARTM_7D_P; - } - break; - case 8: - if( eParity == MB_PAR_NONE ) - { - eUARTMode = UARTM_8D; - } - else - { - eUARTMode = UARTM_8D_P; - } - break; - default: - xResult = FALSE; - } - - if( xResult != FALSE ) - { - u32 test = RCCU_FrequencyValue( RCCU_CLK2 ); - - test = RCCU_FrequencyValue( RCCU_RCLK ); - test = RCCU_FrequencyValue( RCCU_PCLK ); - test = RCCU_FrequencyValue( RCCU_FCLK ); - - /* Setup the UART port pins. */ - GPIO_Config( MB_UART_TX_PORT, 1 << MB_UART_TX_PIN, GPIO_AF_PP ); - GPIO_Config( MB_UART_RX_PORT, 1 << MB_UART_RX_PIN, GPIO_IN_TRI_CMOS ); - - /* Configure the UART. */ - UART_OnOffConfig( MB_UART_DEV, ENABLE ); - UART_FifoConfig( MB_UART_DEV, DISABLE ); - UART_FifoReset( MB_UART_DEV, UART_RxFIFO ); - UART_FifoReset( MB_UART_DEV, UART_TxFIFO ); - UART_LoopBackConfig( MB_UART_DEV, DISABLE ); - UART_Config( MB_UART_DEV, ulBaudRate, eUARTParity, UART_1_StopBits, eUARTMode ); - UART_RxConfig( UART0, ENABLE ); - vMBPortSerialEnable( FALSE, FALSE ); - - /* Configure the IEC for the UART interrupts. */ - EIC_IRQChannelPriorityConfig( MB_UART_IRQ_CH, MB_IRQ_PRIORITY ); - EIC_IRQChannelConfig( MB_UART_IRQ_CH, ENABLE ); - } - return xResult; -} - -void -vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable ) -{ - if( xRxEnable ) - UART_ItConfig( MB_UART_DEV, UART_RxBufFull, ENABLE ); - else - UART_ItConfig( MB_UART_DEV, UART_RxBufFull, DISABLE ); - - if( xTxEnable ) - UART_ItConfig( MB_UART_DEV, UART_TxHalfEmpty, ENABLE ); - else - UART_ItConfig( MB_UART_DEV, UART_TxHalfEmpty, DISABLE ); -} - -BOOL -xMBPortSerialPutByte( CHAR ucByte ) -{ - MB_UART_DEV->TxBUFR = ucByte; - return TRUE; -} - -BOOL -xMBPortSerialGetByte( CHAR * pucByte ) -{ - *pucByte = MB_UART_DEV->RxBUFR; - return TRUE; -} - -BOOL -prvMBPortTXIsEnabled( ) -{ - return ( MB_UART_DEV->IER & UART_TxHalfEmpty ) == UART_TxHalfEmpty; -} - -BOOL -prvMBPortRXIsEnabled( ) -{ - return ( MB_UART_DEV->IER & UART_RxBufFull ) == UART_RxBufFull; -} - - -void -prvvMBSerialIRQHandler( void ) -{ - portENTER_SWITCHING_ISR( ); - - static BOOL xTaskWokenReceive = FALSE; - static BOOL xTaskWokenTransmit = FALSE; - static USHORT usStatus; - - usStatus = UART_FlagStatus( MB_UART_DEV ); - - if( prvMBPortTXIsEnabled( ) && ( usStatus & UART_TxHalfEmpty ) ) - { - xTaskWokenReceive = pxMBFrameCBTransmitterEmpty( ); - } - if( prvMBPortRXIsEnabled( ) && ( usStatus & UART_RxBufFull ) ) - { - xTaskWokenReceive = pxMBFrameCBByteReceived( ); - } - - /* End the interrupt in the EIC. */ - EIC->IPR |= 1 << EIC_CurrentIRQChannelValue( ); - - portEXIT_SWITCHING_ISR( ( xTaskWokenReceive || xTaskWokenTransmit ) ? pdTRUE : pdFALSE ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/port/porttimer.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/port/porttimer.c deleted file mode 100644 index f7315bb94..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/port/porttimer.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * FreeModbus Libary: STR71x Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "assert.h" - -/* ----------------------- FreeRTOS includes --------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" - -/* ----------------------- STR71X includes ----------------------------------*/ -#include "gpio.h" -#include "eic.h" -#include "uart.h" -#include "tim.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_TIMER_DEV ( TIM0 ) -#define MB_TIMER_PRESCALER ( 255UL ) -#define MB_TIMER_IRQ_CH ( T0TIMI_IRQChannel ) -#define MB_IRQ_PRIORITY ( 1 ) - -/* Timer ticks are counted in multiples of 50us. Therefore 20000 ticks are - * one second. - */ -#define MB_TIMER_TICKS ( 20000UL ) - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usTimerDeltaOCRA; - -/* ----------------------- Static functions ---------------------------------*/ -void prvvMBTimerIRQHandler( void ) __attribute__ ( ( naked ) ); - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortTimersInit( USHORT usTim1Timerout50us ) -{ - /* Calculate output compare value for timer1. */ - usTimerDeltaOCRA = - ( ( RCCU_FrequencyValue( RCCU_PCLK ) / ( MB_TIMER_PRESCALER + 1 ) ) * - usTim1Timerout50us ) / ( MB_TIMER_TICKS ); - - TIM_Init( MB_TIMER_DEV ); - TIM_PrescalerConfig( MB_TIMER_DEV, MB_TIMER_PRESCALER ); - if( usTimerDeltaOCRA > 0 ) - { - TIM_OCMPModeConfig( MB_TIMER_DEV, TIM_CHANNEL_A, usTimerDeltaOCRA, TIM_TIMING, TIM_LOW ); - } - - vMBPortTimersDisable( ); - EIC_IRQChannelConfig( MB_TIMER_IRQ_CH, ENABLE ); - EIC_IRQChannelPriorityConfig( MB_TIMER_IRQ_CH, MB_IRQ_PRIORITY ); - - return TRUE; -} - -void -prvvMBTimerIRQHandler( void ) -{ - portENTER_SWITCHING_ISR( ); - - static portBASE_TYPE xTaskSwitch = pdFALSE; - - if( ( usTimerDeltaOCRA > 0 ) && ( TIM_FlagStatus( MB_TIMER_DEV, TIM_OCFA ) ) ) - { - xTaskSwitch |= pxMBPortCBTimerExpired( ); - TIM_FlagClear( MB_TIMER_DEV, TIM_OCFA ); - } - - /* End the interrupt in the EIC. */ - EIC->IPR |= 1 << EIC_CurrentIRQChannelValue( ); - portEXIT_SWITCHING_ISR( xTaskSwitch ); -} - -void -vMBPortTimersEnable( ) -{ - unsigned portSHORT maskTimFlags = 0; - unsigned portSHORT maskTimIT = 0; - - MB_TIMER_DEV->CNTR = 0; - if( usTimerDeltaOCRA > 0 ) - { - MB_TIMER_DEV->OCAR = usTimerDeltaOCRA; - maskTimFlags |= TIM_OCFA; - maskTimIT |= TIM_OCA_IT; - } - - TIM_FlagClear( MB_TIMER_DEV, maskTimFlags ); - TIM_ITConfig( MB_TIMER_DEV, maskTimIT, ENABLE ); - TIM_CounterConfig( MB_TIMER_DEV, TIM_START ); -} - -void -vMBPortTimersDisable( ) -{ - /* We can always clear both flags. This improves performance. */ - TIM_FlagClear( MB_TIMER_DEV, TIM_OCFA | TIM_OCFB ); - TIM_ITConfig( MB_TIMER_DEV, TIM_OCA_IT | TIM_OCB_IT, DISABLE ); - TIM_CounterConfig( MB_TIMER_DEV, TIM_STOP ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/support/ram71x.ld b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/support/ram71x.ld deleted file mode 100644 index ed0076c27..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/support/ram71x.ld +++ /dev/null @@ -1,201 +0,0 @@ -/* - * STR71X Linker Scripts for FreeModbus (RAM) - * Copyright 2005 Anglia Design, Spencer Oliver - * Modifications Copyright (C) 2006 Christian Walter - * - * This demo code and associated components are provided as is and has no - * warranty, implied or otherwise. You are free to use/modify any of the - * provided code at your own risk in your applications with the expressed - * limitation of liability (see below) - * - * LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE - * FOR ANY LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF - * BUSINESS, NOR FOR INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES - * OF ANY KIND WHETHER UNDER THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - * - * $Id: ram71x.ld,v 1.1 2006/11/02 23:14:44 wolti Exp $ - */ - -_STACKSIZE = 256; -_STACKSIZE_IRQ = 256; -_STACKSIZE_FIQ = 256; -_STACKSIZE_SVC = 0; -_STACKSIZE_ABT = 0; -_STACKSIZE_UND = 0; - -MEMORY -{ - DATA (rw) : ORIGIN = 0x20000000, LENGTH = 0x00010000 -} - -SECTIONS -{ - /* first section is .text which is used for code */ - .text : - { - KEEP(*(.vectrom)) - KEEP(*(.init)) - *(.text .text.*) - *(.gnu.linkonce.t.*) - *(.glue_7t .glue_7) - KEEP(*(.fini)) - *(.gcc_except_table) - } >DATA =0 - . = ALIGN(4); - - /* .ctors .dtors are used for c++ constructors/destructors */ - .ctors : - { - PROVIDE(__ctors_start__ = .); - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - } >DATA - - .dtors : - { - PROVIDE(__dtors_start__ = .); - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - PROVIDE(__dtors_end__ = .); - } >DATA - - /* .rodata section which is used for read-only data (constants) */ - .rodata : - { - *(.rodata .rodata.*) - *(.gnu.linkonce.r.*) - } >DATA - . = ALIGN(4); - - _vectext = .; - PROVIDE (vectext = .); - - .vect : AT (_vectext) - { - _vecstart = .; - KEEP(*(.vectram)) - _vecend = .; - } >DATA - - _etext = _vectext + SIZEOF(.vect); - PROVIDE (etext = .); - - /* .data section which is used for initialized data */ - .data : AT (_etext) - { - _data = .; - *(.data .data.*) - *(.gnu.linkonce.d.*) - SORT(CONSTRUCTORS) - } >DATA - . = ALIGN(4); - - _edata = .; - PROVIDE (edata = .); - - /* .bss section which is used for uninitialized data */ - .bss : - { - __bss_start = .; - __bss_start__ = .; - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - } >DATA - . = ALIGN(4); - __bss_end__ = .; - - _end = .; - PROVIDE(end = .); - - /* .stack section - user mode stack */ - .stack (NOLOAD) : - { - __stack_start__ = .; - *(.stack) - . = MAX(__stack_start__ + _STACKSIZE , .); - } >DATA - __stack_end__ = __stack_start__ + SIZEOF(.stack); - - /* .stack_irq section */ - .stack_irq (__stack_end__ + 3) / 4 * 4 (NOLOAD) : - { - __stack_irq_start__ = .; - *(.stack_irq) - . = MAX(__stack_irq_start__ + _STACKSIZE_IRQ , .); - } >DATA - __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq); - - /* .stack_fiq section */ - .stack_fiq (__stack_irq_end__ + 3) / 4 * 4 (NOLOAD) : - { - __stack_fiq_start__ = .; - *(.stack_fiq) - . = MAX(__stack_fiq_start__ + _STACKSIZE_FIQ , .); - } >DATA - __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq); - - /* .stack_svc section */ - .stack_svc (__stack_fiq_end__ + 3) / 4 * 4 (NOLOAD) : - { - __stack_svc_start__ = .; - *(.stack_svc) - . = MAX(__stack_svc_start__ + _STACKSIZE_SVC , .); - } >DATA - __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc); - - /* .stack_abt section */ - .stack_abt (__stack_svc_end__ + 3) / 4 * 4 (NOLOAD) : - { - __stack_abt_start__ = .; - *(.stack_abt) - . = MAX(__stack_abt_start__ + _STACKSIZE_ABT , .); - } >DATA - __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt); - - /* .stack_und section */ - .stack_und (__stack_abt_end__ + 3) / 4 * 4 (NOLOAD) : - { - __stack_und_start__ = .; - *(.stack_und) - . = MAX(__stack_und_start__ + _STACKSIZE_UND , .); - } >DATA - __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und); - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/support/rom71x.ld b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/support/rom71x.ld deleted file mode 100644 index 068eb1dbd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/support/rom71x.ld +++ /dev/null @@ -1,208 +0,0 @@ -/* - * STR71X Linker Scripts for FreeModbus (ROM) - * Copyright 2005 Anglia Design, Spencer Oliver - * Modifications Copyright (C) 2006 Christian Walter - * - * This demo code and associated components are provided as is and has no - * warranty, implied or otherwise. You are free to use/modify any of the - * provided code at your own risk in your applications with the expressed - * limitation of liability (see below) - * - * LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE - * FOR ANY LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF - * BUSINESS, NOR FOR INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES - * OF ANY KIND WHETHER UNDER THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - * - * $Id: rom71x.ld,v 1.1 2006/11/02 23:14:44 wolti Exp $ - */ - -/* Stack Sizes */ -_STACKSIZE = 256; -_STACKSIZE_IRQ = 256; -_STACKSIZE_FIQ = 256; -_STACKSIZE_SVC = 0; -_STACKSIZE_ABT = 0; -_STACKSIZE_UND = 0; - -/* Memory Definitions */ -MEMORY -{ - CODE (rx) : ORIGIN = 0x40000000, LENGTH = 0x00040000 - DATA (rw) : ORIGIN = 0x20000000, LENGTH = 0x00010000 -} - -/* Section Definitions */ -SECTIONS -{ - /* first section is .text which is used for code */ - .text : - { - KEEP(*(.vectrom)) - KEEP(*(.init)) - *(.text .text.*) - *(.gnu.linkonce.t.*) - *(.glue_7t .glue_7) - KEEP(*(.fini)) - *(.gcc_except_table) - } >CODE =0 - . = ALIGN(4); - - /* .ctors .dtors are used for c++ constructors/destructors */ - .ctors : - { - PROVIDE(__ctors_start__ = .); - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - PROVIDE(__ctors_end__ = .); - } >CODE - - .dtors : - { - PROVIDE(__dtors_start__ = .); - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - PROVIDE(__dtors_end__ = .); - } >CODE - - /* .rodata section which is used for read-only data (constants) */ - .rodata : - { - *(.rodata .rodata.*) - *(.gnu.linkonce.r.*) - } >CODE - . = ALIGN(4); - - _vectext = .; - PROVIDE (vectext = .); - - .vect : AT (_vectext) - { - _vecstart = .; - KEEP(*(.vectram)) - _vecend = .; - } >DATA - - _etext = _vectext + SIZEOF(.vect); - PROVIDE (etext = .); - - /* .data section which is used for initialized data */ - .data : AT (_etext) - { - _data = .; - *(.data .data.*) - *(.gnu.linkonce.d.*) - SORT(CONSTRUCTORS) - . = ALIGN(4); - *(.fastrun .fastrun.*) - } >DATA - . = ALIGN(4); - - _edata = .; - PROVIDE (edata = .); - - /* .bss section which is used for uninitialized data */ - .bss : - { - __bss_start = .; - __bss_start__ = .; - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - } >DATA - . = ALIGN(4); - __bss_end__ = .; - - _end = .; - PROVIDE(end = .); - - /* .stack section - user mode stack */ - .stack (NOLOAD) : - { - __stack_start__ = .; - *(.stack) - . = MAX(__stack_start__ + _STACKSIZE , .); - } >DATA - __stack_end__ = __stack_start__ + SIZEOF(.stack); - - /* .stack_irq section */ - .stack_irq (__stack_end__ + 3) / 4 * 4 (NOLOAD) : - { - __stack_irq_start__ = .; - *(.stack_irq) - . = MAX(__stack_irq_start__ + _STACKSIZE_IRQ , .); - } >DATA - __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq); - - /* .stack_fiq section */ - .stack_fiq (__stack_irq_end__ + 3) / 4 * 4 (NOLOAD) : - { - __stack_fiq_start__ = .; - *(.stack_fiq) - . = MAX(__stack_fiq_start__ + _STACKSIZE_FIQ , .); - } >DATA - __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq); - - /* .stack_svc section */ - .stack_svc (__stack_fiq_end__ + 3) / 4 * 4 (NOLOAD) : - { - __stack_svc_start__ = .; - *(.stack_svc) - . = MAX(__stack_svc_start__ + _STACKSIZE_SVC , .); - } >DATA - __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc); - - /* .stack_abt section */ - .stack_abt (__stack_svc_end__ + 3) / 4 * 4 (NOLOAD) : - { - __stack_abt_start__ = .; - *(.stack_abt) - . = MAX(__stack_abt_start__ + _STACKSIZE_ABT , .); - } >DATA - __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt); - - /* .stack_und section */ - .stack_und (__stack_abt_end__ + 3) / 4 * 4 (NOLOAD) : - { - __stack_und_start__ = .; - *(.stack_und) - . = MAX(__stack_und_start__ + _STACKSIZE_UND , .); - } >DATA - __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und); - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/support/target-71.gdb b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/support/target-71.gdb deleted file mode 100644 index e4e8a15ee..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/support/target-71.gdb +++ /dev/null @@ -1,59 +0,0 @@ -# -# STR71X GDB Target Scripts for FreeModbus -# Copyright 2005 Anglia Design, Spencer Oliver -# Modifications Copyright (C) 2006 Christian Walter -# -# This demo code and associated components are provided as is and has no -# warranty, implied or otherwise. You are free to use/modify any of the -# provided code at your own risk in your applications with the expressed -# limitation of liability (see below) -# -# LIMITATION OF LIABILITY: ANGLIA OR ANGLIA DESIGNS SHALL NOT BE LIABLE -# FOR ANY LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA, INTERRUPTION OF -# BUSINESS, NOR FOR INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES -# OF ANY KIND WHETHER UNDER THIS AGREEMENT OR OTHERWISE, EVEN IF ADVISED OF -# THE POSSIBILITY OF SUCH DAMAGES. -# -# $Id: target-71.gdb,v 1.1 2006/11/02 23:14:44 wolti Exp $ -# - -set remote memory-write-packet-size 1024 -set remote memory-write-packet-size fixed - -set remote memory-read-packet-size 1024 -set remote memory-read-packet-size fixed -set remote hardware-watchpoint-limit 2 -set remote hardware-breakpoint-limit 2 - -# reset and map 0 to internal ram -define ramreset - set *(int*)0xA0000050 = 0x800A - monitor arm7_9 sw_bkpts enable - tb main - echo Mapped internal SRAM at address 0x00000000\n -end - -# reset and map 0 to flash -define romreset - set *(int*)0xA0000050 = 0x8008 - monitor arm7_9 force_hw_bkpts enable - thb main - echo Mapped internal FLASH at address 0x00000000\n -end - -define setup-and-load-rom - reset - romreset -end - -define setup-and-load-ram - reset - ramreset -end - -define reset - monitor reset - monitor sleep 50 - monitor soft_reset_halt -end - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/system/startup.S b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/system/startup.S deleted file mode 100644 index aae5ab429..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/system/startup.S +++ /dev/null @@ -1,251 +0,0 @@ -/* - * STR71X/GCC Startup Scripts for FreeModbus - - * Copyright C) 2005 Anglia Design, Spencer Oliver - * Copyright (C) 2006 Christian Walter - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id: startup.S,v 1.1 2006/11/02 23:14:44 wolti Exp $ - */ - -/* ----------------------- Target settings ----------------------------------*/ - .equ FOSC, 4000000 - .equ FRTC, 32768 - -/* ----------------------- ARM7 CPU modes -----------------------------------*/ - .equ MODE_USR, 0x10 - .equ MODE_FIQ, 0x11 - .equ MODE_IRQ, 0x12 - .equ MODE_SVC, 0x13 - .equ MODE_ABT, 0x17 - .equ MODE_UND, 0x1B - .equ MODE_SYS, 0x1F /* available on ARM Arch 4 and later */ - - .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */ - .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */ - -/* ----------------------- System memory locations --------------------------*/ - .equ EIC_ADDR, 0xFFFFF800 /* EIC base address */ - .equ EIC_ICF_OFF, 0x00 /* Interrupt Control register offset */ - .equ EIC_CIPR_OFF, 0x08 /* Current Interrupt Priority Register offset */ - .equ EIC_IVR_OFF, 0x18 /* Interrupt Vector Register offset */ - .equ EIC_FIR_OFF, 0x1C /* Fast Interrupt Register offset */ - .equ EIC_IER_OFF, 0x20 /* Interrupt Enable Register offset */ - .equ EIC_IPR_OFF, 0x40 /* Interrupt Pending Bit Register offset */ - .equ EIC_SIR0_OFF, 0x60 /* Source Interrupt Register 0 */ - - .equ CPM_ADDR, 0xA0000040 /* CPM Base Address */ - .equ CPM_BC_OFF, 0x10 /* CPM - Boot Configuration Register */ - .equ CPM_BC_FLASH, 0x0000 /* to remap FLASH at 0x0 */ - .equ CPM_BC_RAM, 0x0002 /* to remap RAM at 0x0 */ - .equ CPM_BC_EXTMEM, 0x0003 /* to remap EXTMEM at 0x0 */ - -/* ----------------------- Startup code -------------------------------------*/ - .text - .arm - .section .init, "ax" - - .global _start - .global RCCU_Main_Osc - .global RCCU_RTC_Osc - -/* ----------------------- Exception vectors ( ROM mode with remap ) --------*/ -.if ROM_RUN == 1 -_vector_reset_rom: - ldr pc, =_start_rom - nop - nop - nop - nop - nop - nop - nop - - /* Copy the final vectors from ROM into RAM and map RAM at address - * 0x00000000 */ -_start_rom: - ldr r1, =_vecstart /* r1 = start address from which to copy */ - ldr r3, =_vecend - sub r3, r3, r1 /* r3 = number of bytes to copy */ - ldr r0, =_vectext /* r0 = start address where to copy */ -copy_ram: - ldr r2, [r0], #4 /* Read a word from the source */ - str r2, [r1], #4 /* copy the word to destination */ - subs r3, r3, #4 /* Decrement number of words to copy */ - bne copy_ram - - ldr r1, =CPM_ADDR - ldrh r2, [r1, #CPM_BC_OFF] /* Read BOOTCONF Register */ - bic r2, r2, #0x03 /* Reset the two LSB bits of BOOTCONF Register */ - orr r2, r2, #CPM_BC_RAM /* change the two LSB bits of BOOTCONF Register */ - strh r2, [r1, #CPM_BC_OFF] /* Write BOOTCONF Register */ -.endif - -/* ----------------------- Default reset handler (After remap ) -------------*/ -_start: - ldr pc, =NextInst -NextInst: - nop /* Wait for OSC stabilization */ - nop - nop - nop - nop - nop - nop - nop - nop - - /* Enter Undefined Instruction Mode and set its Stack Pointer */ - msr cpsr_c, #MODE_UND|I_Bit|F_Bit - ldr sp, =__stack_und_end__ - - /* Enter Abort Mode and set its Stack Pointer */ - msr cpsr_c, #MODE_ABT|I_Bit|F_Bit - ldr sp, =__stack_abt_end__ - - /* Enter IRQ Mode and set its Stack Pointer */ - msr cpsr_c, #MODE_IRQ|I_Bit|F_Bit - ldr sp, =__stack_irq_end__ - - /* Enter FIQ Mode and set its Stack Pointer */ - msr cpsr_c, #MODE_FIQ|I_Bit|F_Bit - ldr sp, =__stack_fiq_end__ - - /* Enter Supervisor Mode and set its Stack Pointer */ - msr cpsr_c, #MODE_SVC|I_Bit|F_Bit - ldr sp, =__stack_svc_end__ - - /* Set User Mode Stack pointer but remain in Supervisor Mode */ - ldr r1, =__stack_end__ - mov r2, sp - stmfd r2!, {r1} - ldmfd r2, {sp}^ - - /* Setup a default Stack Limit (when compiled with "-mapcs-stack-check") */ - ldr sl, =__bss_end__ - -/* ----------------------- EIC initialization ------------------------------- -/* - * EIC is initialized with: - * - IRQ disabled - * - FIQ disabled - * - IVR contain the load PC opcode (0xF59FF00) - * - Current priority level equal to 0 - * - All channels are disabled - * - All channels priority equal to 0 - * - All SIR registers contain offset to the related IRQ table entry - */ - -eic_init: - ldr r3, =EIC_ADDR - ldr r4, =0x00000000 - str r4, [r3, #EIC_ICF_OFF] /* Disable FIQ and IRQ */ - str r4, [r3, #EIC_IER_OFF] /* Disable all channels interrupts */ - ldr r4, =0xFFFFFFFF - str r4, [r3, #EIC_IPR_OFF] /* Clear all IRQ pending bits */ - ldr r4, =0x0C - str r4, [r3, #EIC_FIR_OFF] /* Disable FIQ channels and clear FIQ pending bits */ - ldr r4, =0x00000000 - str r4, [r3, #EIC_CIPR_OFF] /* Reset the current priority register */ - ldr r4, =0xE59F0000 - str r4, [r3, #EIC_IVR_OFF] /* Write the LDR pc,pc,#offset instruction code in IVR[31:16] */ - ldr r2, =32 /* 32 Channel to initialize */ - ldr r0, =T0TIMI_Addr /* Read the address of the IRQs address table */ - ldr r1, =0x00000FFF - and r0, r0, r1 - ldr r5, =EIC_SIR0_OFF /* Read SIR0 address */ - sub r4, r0, #8 /* subtract 8 for prefetch */ - ldr r1, =0xF7E8 /* add the offset to the 0x00000000 address(IVR address + 7E8 = 0x00000000) */ - /* 0xF7E8 used to complete the LDR pc,pc,#offset opcode */ - add r1, r4, r1 /* compute the jump offset */ -eic_ini: - mov r4, r1, LSL #16 /* Left shift the result */ - str r4, [r3, r5] /* Store the result in SIRx register */ - add r1, r1, #4 /* Next IRQ address */ - add r5, r5, #4 /* Next SIR */ - subs r2, r2, #1 /* Decrement the number of SIR registers to initialize */ - bne eic_ini /* If more then continue */ - - /* Relocate .data section (Copy from ROM to RAM) */ -.if ROM_RUN == 1 - ldr r1, =_etext - ldr r2, =_data - ldr r3, =_edata -_loop_relocate: - cmp r2, r3 - ldrlo r0, [r1], #4 - strlo r0, [r2], #4 - blo _loop_relocate -.endif - - /* Clear .bss section (Zero init) */ - mov r0, #0 - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ -_loop_clear_bss: - cmp r1, r2 - strlo r0, [r1], #4 - blo _loop_clear_bss - - /* Call C++ constructors */ - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ -ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #4 - stmfd sp!, {r0-r1} - mov lr, pc - mov pc, r2 - ldmfd sp!, {r0-r1} - b ctor_loop -ctor_end: - - /* Need to set up standard file handles */ - - /* if we use debug version of str7lib this will call the init function */ - bl libdebug -libdebug: - - /* Call main */ - bl main - - /* Call destructors */ - ldr r0, =__dtors_start__ - ldr r1, =__dtors_end__ -dtor_loop: - cmp r0, r1 - beq dtor_end - ldr r2, [r0], #4 - stmfd sp!, {r0-r1} - mov lr, pc - mov pc, r2 - ldmfd sp!, {r0-r1} - b dtor_loop -dtor_end: - -/* Return from main, loop forever. */ -exit_loop: - b exit_loop - -/* Fosc values, used by libstr7 */ - -RCCU_Main_Osc: .long FOSC -RCCU_RTC_Osc: .long FRTC - - .weak libdebug - - .end diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/system/vector.S b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/system/vector.S deleted file mode 100644 index 8ea5297ca..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/system/vector.S +++ /dev/null @@ -1,125 +0,0 @@ -/* - * STR71X vectors for FreeModbus - * Copyright C) 2005 Anglia Design, Spencer Oliver - * Modifications (C) 2006 Christian Walter - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id: vector.S,v 1.1 2006/11/02 23:14:44 wolti Exp $ - */ - -/* ----------------------- System memory locations --------------------------*/ -#include "FreeRTOSConfig.h" - -/* ----------------------- System memory locations --------------------------*/ - .equ EIC_ADDR, 0xFFFFF800 /* EIC base address */ - .equ EIC_IVR_OFF, 0x18 /* Interrupt Vector Register offset */ - -/* ----------------------- Start implementation -----------------------------*/ - .global _vector_reset - .global T0TIMI_Addr - -/* ----------------------- Exception vectors --------------------------------*/ - .text - .arm -.if ROM_RUN == 1 - .section .vectram, "ax" -.else - .section .vectrom, "ax" -.endif - -_vector_reset: - ldr pc, reset_handler_address /* Reset Handler */ - ldr pc, undef_handler_address - ldr pc, swi_handler_address - ldr pc, pabort_handler_address - ldr pc, dabort_handler_address - nop - ldr pc, irq_handler_address - ldr pc, fiq_handler_address - -/* ----------------------- Exception handlers address table -----------------*/ - -reset_handler_address: .word _start -undef_handler_address: .word _undef_handler -swi_handler_address: .word vPortYieldProcessor -pabort_handler_address: .word _pabort_handler -dabort_handler_address: .word _dabort_handler -irq_handler_address: .word _irq_handler -fiq_handler_address: .word _fiq_handler - -/* ----------------------- EIC IRQ handlers address table -------------------*/ - -T0TIMI_Addr: .word prvvMBTimerIRQHandler -FLASH_Addr: .word _undef_IRQhandler -RCCU_Addr: .word _undef_IRQhandler -RTC_Addr: .word _undef_IRQhandler -#if configUSE_PREEMPTION == 0 -WDG_Addr: .word vPortNonPreemptiveTick -#else -WDG_Addr: .word vPortPreemptiveTick -#endif -XTI_Addr: .word _undef_IRQhandler -USBHP_Addr: .word _undef_IRQhandler -I2C0ITERR_Addr: .word _undef_IRQhandler -I2C1ITERR_Addr: .word _undef_IRQhandler -UART0_Addr: .word prvvMBSerialIRQHandler -UART1_Addr: .word _undef_IRQhandler -UART2_Aadd: .word _undef_IRQhandler -UART3_Addr: .word _undef_IRQhandler -BSPI0_Addr: .word _undef_IRQhandler -BSPI1_Addr: .word _undef_IRQhandler -I2C0_Addr: .word _undef_IRQhandler -I2C1_Addr: .word _undef_IRQhandler -CAN_Addr: .word _undef_IRQhandler -ADC12_Addr: .word _undef_IRQhandler -T1TIMI_Addr: .word _undef_IRQhandler -T2TIMI_Addr: .word _undef_IRQhandler -T3TIMI_Addr: .word _undef_IRQhandler - .word 0 - .word 0 - .word 0 -HDLC_Addr: .word _undef_IRQhandler -USBLP_Addr: .word _undef_IRQhandler - .word 0 - .word 0 -T0TOI_Addr: .word _undef_IRQhandler -T0OC1_Addr: .word _undef_IRQhandler -T0OC2_Addr: .word _undef_IRQhandler - -/* ----------------------- Default IRQ handlers -----------------------------*/ - -_undef_handler: - b _undef_handler - -_swi_handler: - b _swi_handler - -_pabort_handler: - b _pabort_handler - -_dabort_handler: - b _dabort_handler - -_irq_handler: - ldr pc, =(EIC_ADDR + EIC_IVR_OFF) - -_fiq_handler: - b _fiq_handler - -/* ----------------------- Default EIC IRQ handlers -------------------------*/ -_undef_IRQhandler: - b _undef_IRQhandler - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/tools/openocd b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/tools/openocd deleted file mode 100644 index 0c3795ddf..000000000 Binary files a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/tools/openocd and /dev/null differ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/tools/openocd.exe b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/tools/openocd.exe deleted file mode 100644 index b00a66f0f..000000000 Binary files a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/tools/openocd.exe and /dev/null differ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/tools/str71x_wig.cfg b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/tools/str71x_wig.cfg deleted file mode 100644 index 6cfdc81b0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XGCC/tools/str71x_wig.cfg +++ /dev/null @@ -1,48 +0,0 @@ -# STR71X OpenOCD configuration for FreeModbus -# -# Copyright (C) 2006 Christian Walter -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# -# $Id: str71x_wig.cfg,v 1.1 2006/11/02 23:14:44 wolti Exp $ -# - -#daemon configuration -telnet_port 4444 -gdb_port 3333 - -#interface -interface parport -parport_port 0 -parport_cable wiggler -jtag_speed 0 -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config trst_and_srst - -#jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe - -#target configuration -daemon_startup reset -#target -#target arm7tdmi -target arm7tdmi little run_and_halt 0 arm7tdmi -run_and_halt_time 0 30 - -working_area str71x 0x2000F000 0x00001000 nobackup -#flash configuration -flash bank str7x 0x40000000 0x00040000 0 0 STR71x 0 -flash bank str7x 0x400C0000 0x00004000 0 0 STR71x 0 diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/FreeRTOSConfig.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/FreeRTOSConfig.h deleted file mode 100644 index a50109cee..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/FreeRTOSConfig.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry. - MCF5235 Port - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - *----------------------------------------------------------*/ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 25000000 ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 ) -#define configMAX_TASK_NAME_LEN ( 16 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ - -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetCurrentTaskHandle 1 - -#endif /* FREERTOS_CONFIG_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/README.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/README.txt deleted file mode 100644 index cb4612e8d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/README.txt +++ /dev/null @@ -1,69 +0,0 @@ - - STR71X PORT with lwIP/PPP - -REQUIREMENTS -============ - -The FreeModbus/lwIP port requires are port of the lwIP TCP/IP stack for -the target platform. This port includes a PPP driver for lwIP together -with suitable drivers for the serial interfaces of the STR71x device. - -The development environment used is Rowley Crossworks 1.5 for ARM but as - they use the GNU compilers any other environment should work too. The - hardware used is STR-P711 [1] development board from Olimex. - - [1] ... STR-P711: http://www.olimex.com/dev/str-p711.html - -USAGE -===== - -Simply compile the software with the Rowley compilers and download it to -the target. The provided configuration "Flash Debug" and "Flash Release" -should work out of the box. The first UART of the STR711 device is used -as stdout where debug messages are sent to. You should connect this one -to a simple terminal program. The second UART is used for the PPP conn- -ection. You must setup a PPP server on this line. Example for Linux can -be found in the utils directory together with a startup script to start -the server. Remember to replace ttyS0 with the line you have connected -the second UART to. - -By default the port using the following settings: - - IP Address (STR71X) : 10.0.10.2 - IP Address (HOST) : 10.0.10.1 - Modbus TCP Port : 502 - -If you have configured everything correctly you should see the following -output from your local PPP daemon. - ------------------------ start /var/log/messages output ---------------------- -Sep 4 21:12:40 pcno-4 pppd[22597]: pppd 2.4.2 started by root, uid 0 -Sep 4 21:12:40 pcno-4 pppd[22597]: Using interface ppp0 -Sep 4 21:12:40 pcno-4 pppd[22597]: Connect: ppp0 <--> /dev/ttyS0 -Sep 4 21:12:44 pcno-4 pppd[22597]: found interface eth0 for proxy arp -Sep 4 21:12:44 pcno-4 pppd[22597]: local IP address 10.0.10.1 -Sep 4 21:12:44 pcno-4 pppd[22597]: remote IP address 10.0.10.2 ------------------------ end /var/log/messages output ------------------------ - -The output from the debug console received by the target should match: - ------------------------ start console output -------------------------------- -ERROR: PPP: new PPP connection established -ERROR: PPP: our IP address = 10.0.10.2 -ERROR: PPP: his IP address = 10.0.10.1 -ERROR: PPP: netmask = 255.255.255.0 -DEBUG: MBTCP-ACCEPT: Accepted new client 10.0.10.1 -DEBUG: MBTCP-RECV: | TID = 0000 | PID = 0000 | LEN = 0006 | UID = 01|| - FUNC = 04 | DATA = 03E70002 | -DEBUG: MBTCP-SENT: | TID = 0000 | PID = 0000 | LEN = 0007 | UID = 01|| - FUNC = 04 | DATA = 04AC610001 | -DEBUG: MBTCP-RECV: | TID = 0000 | PID = 0000 | LEN = 0006 | UID = 01|| - FUNC = 04 | DATA = 03E70002 | -DEBUG: MBTCP-SENT: | TID = 0000 | PID = 0000 | LEN = 0007 | UID = 01|| - FUNC = 04 | DATA = 04B0420001 | ------------------------ end console output ---------------------------------- - -$Id: README.txt,v 1.1 2006/09/04 19:33:58 wolti Exp $ - -STR71X + lwIP/PPP port - Copyright (c) 2006 Christian Walter. - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/crt0.s b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/crt0.s deleted file mode 100644 index 7ab4eec43..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/crt0.s +++ /dev/null @@ -1,177 +0,0 @@ -/***************************************************************************** - * Copyright (c) 2001, 2002 Rowley Associates Limited. * - * * - * This file may be distributed under the terms of the License Agreement * - * provided with this software. * - * * - * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * - * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - *****************************************************************************/ - .section .init, "ax" - .code 32 - .align 0 - - .weak _start - .global __start - .global __gccmain - .extern main - .extern exit - -/***************************************************************************** - * Function : _start * - * Description : Main entry point and startup code for C system. * - *****************************************************************************/ -_start: -__start: - mrs r0, cpsr - bic r0, r0, #0x1F - - /* Setup stacks */ - orr r1, r0, #0x1B /* Undefined mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_und_end__ - - orr r1, r0, #0x17 /* Abort mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_abt_end__ - - orr r1, r0, #0x12 /* IRQ mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_irq_end__ - - orr r1, r0, #0x11 /* FIQ mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_fiq_end__ - - orr r1, r0, #0x13 /* Supervisor mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_svc_end__ -#ifdef SUPERVISOR_START - /* Start application in supervisor mode */ - ldr r1, =__stack_end__ /* Setup user/system mode stack */ - mov r2, sp - stmfd r2!, {r1} - ldmfd r2, {sp}^ -#else - /* Start application in system mode */ - orr r1, r0, #0x1F /* System mode */ - msr cpsr_cxsf, r1 - ldr sp, =__stack_end__ -#endif - - /* Copy from initialised data section to data section (if necessary). */ - ldr r0, =__data_load_start__ - ldr r1, =__data_start__ - cmp r0, r1 - beq copy_data_end - - ldr r2, =__data_end__ - subs r2, r2, r1 - beq copy_data_end - -copy_data_loop: - ldrb r3, [r0], #+1 - strb r3, [r1], #+1 - subs r2, r2, #1 - bne copy_data_loop -copy_data_end: - - /* Copy from initialised text section to text section (if necessary). */ - ldr r0, =__text_load_start__ - ldr r1, =__text_start__ - cmp r0, r1 - beq copy_text_end - - ldr r2, =__text_end__ - subs r2, r2, r1 - beq copy_text_end - -copy_text_loop: - ldrb r3, [r0], #+1 - strb r3, [r1], #+1 - subs r2, r2, #1 - bne copy_text_loop -copy_text_end: - - /* Copy from initialised fast_text section to fast_text section (if necessary). */ - ldr r0, =__fast_load_start__ - ldr r1, =__fast_start__ - cmp r0, r1 - beq copy_fast_end - - ldr r2, =__fast_end__ - subs r2, r2, r1 - beq copy_fast_end - -copy_fast_loop: - ldrb r3, [r0], #+1 - strb r3, [r1], #+1 - subs r2, r2, #1 - bne copy_fast_loop -copy_fast_end: - - /* Zero the bss. */ - ldr r0, =__bss_start__ - ldr r1, =__bss_end__ - mov r2, #0 -zero_bss_loop: - cmp r0, r1 - beq zero_bss_end - strb r2, [r0], #+1 - b zero_bss_loop -zero_bss_end: - - /* Initialise the heap */ - ldr r0, = __heap_start__ - ldr r1, = __heap_end__ - sub r1, r1, r0 /* r1 = r1-r0 */ - mov r2, #0 - str r2, [r0], #+4 /* *r0++ = 0 */ - str r1, [r0] /* *r0 = __heap_end__ - __heap_start__ */ - - /* Call constructors */ - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ -ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #+4 - stmfd sp!, {r0-r1} - mov lr, pc - mov pc, r2 - ldmfd sp!, {r0-r1} - b ctor_loop -ctor_end: - - /* Setup initial call frame */ - mov lr, #4 - mov r12, sp - stmfd sp!, {r11-r12, lr-pc} - sub r11, r12, #0x00000004 - -start: - /* Jump to main entry point */ - mov r0, #0 - mov r1, #0 - ldr r2, =main - bx r2 - - /* Call destructors */ - ldr r0, =__dtors_start__ - ldr r1, =__dtors_end__ - -dtor_loop: - cmp r0, r1 - beq dtor_end - ldr r2, [r0], #+4 - stmfd sp!, {r0-r1} - mov lr, pc - mov pc, r2 - ldmfd sp!, {r0-r1} - b dtor_loop -dtor_end: - - /* Return from main, loop forever. */ -exit_loop: - b exit_loop - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/demo.c deleted file mode 100644 index ad5d9ce61..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/demo.c +++ /dev/null @@ -1,320 +0,0 @@ -/* - * FreeModbus Libary: STR71XTCP Demo Application - * Copyright (C) 2006 Christian Walter - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include - -/* ----------------------- lwIP includes ------------------------------------*/ -#include "lwip/opt.h" -#include "lwip/sio.h" -#include "lwip/sys.h" -#include "lwip/inet.h" -#include "ppp/ppp.h" -#include "arch/cc.h" - -/* ----------------------- FreeRTOS includes --------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "eic.h" -#include "netif/serial.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define mainMB_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 ) -#define REG_INPUT_START 1000 -#define REG_INPUT_NREGS 4 -#define REG_HOLDING_START 2000 -#define REG_HOLDING_NREGS 130 - -#define PPP_AUTH_ENABLED 1 -#define PPP_USER "freemodbus" -#define PPP_PASS "insecure" - -/* ----------------------- Type definitions ---------------------------------*/ -typedef enum -{ - CONNECTING, CONNECTED, DISCONNECT -} ePPPThreadControl; - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegInputStart = REG_INPUT_START; -static USHORT usRegInputBuf[REG_INPUT_NREGS]; -static USHORT usRegHoldingStart = REG_HOLDING_START; -static USHORT usRegHoldingBuf[REG_HOLDING_NREGS]; -static ePPPThreadControl ePPPThrCtl; - - -/* ----------------------- Static functions ---------------------------------*/ -static void vlwIPInit( void ); -static void vMBServerTask( void *arg ); -static void vPPPStatusCB( void *ctx, int errCode, void *arg ); - -sio_fd_t stdio_fd; -sio_fd_t ppp_fd; - -/* ----------------------- Start implementation -----------------------------*/ -int -main( void ) -{ - EIC_Init( ); - EIC_IRQConfig( ENABLE ); - - /* Use UART0 as stdin/stdout for debug purposes. */ - if( ( stdio_fd = sio_open_new( 0, 115200, 8, SIO_STOP_1, SIO_PAR_NONE ) ) == SIO_FD_NULL ) - { - /* nothing we can do here - no stdout means no logging. */ - } - else - { - /* Initialize lwIP and its interface layer. */ - vlwIPInit( ); - - /* Use UART1 as PPP device. */ - if( ( ppp_fd = sio_open_new( 1, 115200, 8, SIO_STOP_1, SIO_PAR_NONE ) ) == SIO_FD_NULL ) - { - vMBPortLog( MB_LOG_ERROR, "PPP", "can't open PPP device!\r\n" ); - } - else if( sys_thread_new( vMBServerTask, NULL, mainMB_TASK_PRIORITY ) == SYS_THREAD_NULL ) - { - vMBPortLog( MB_LOG_ERROR, "MB-INIT", "can't start modbus task!\r\n" ); - } - else - { - vMBPortLog( MB_LOG_INFO, "MB-INIT", "FreeModbus demo application starting...\r\n" ); - /* Everything ready. Start the scheduler. */ - vTaskStartScheduler( ); - } - } - - for( ;; ); -} - -void -vlwIPInit( void ) -{ - sys_init( ); - mem_init( ); - memp_init( ); - pbuf_init( ); - netif_init( ); - ip_init( ); - tcpip_init( NULL, NULL ); -} - -void -vMBServerTask( void *arg ) -{ - eMBErrorCode xStatus; - ePPPThreadControl ePPPThrCtlCur; - int ppp_con_fd; - portTickType xTicks; - - pppInit( ); - if( PPP_AUTH_ENABLED ) - { - pppSetAuth( PPPAUTHTYPE_PAP, PPP_USER, PPP_PASS ); - } - else - { - pppSetAuth( PPPAUTHTYPE_NONE, NULL, NULL ); - } - do - { - vPortEnterCritical( ); - ePPPThrCtl = CONNECTING; - vPortExitCritical( ); - if( ( ppp_con_fd = pppOpen( ppp_fd, vPPPStatusCB, NULL ) ) == PPPERR_NONE ) - { - /* Check every 50ms if the state of the connecton has changed. - * This could either mean it was aborted or successful. - */ - do - { - vTaskDelay( ( portTickType ) ( 50UL / portTICK_RATE_MS ) ); - vPortEnterCritical( ); - ePPPThrCtlCur = ePPPThrCtl; - vPortExitCritical( ); - } - while( ePPPThrCtlCur == CONNECTING ); - - if( ePPPThrCtlCur == CONNECTED ) - { - if( eMBTCPInit( MB_TCP_PORT_USE_DEFAULT ) != MB_ENOERR ) - { - vMBPortLog( MB_LOG_ERROR, "PPP", "can't initalize modbus stack!\r\n" ); - } - else if( eMBEnable( ) != MB_ENOERR ) - { - vMBPortLog( MB_LOG_ERROR, "PPP", "can't enable modbus stack!\r\n" ); - } - else - { - do - { - vPortEnterCritical( ); - ePPPThrCtlCur = ePPPThrCtl; - vPortExitCritical( ); - - /* Application code here. */ - xStatus = eMBPoll( ); - - /* Update input registers with the current system tick. */ - xTicks = xTaskGetTickCount( ); - - /* Note: little endian stuff */ - usRegInputBuf[0] = ( USHORT ) ( xTicks ); - usRegInputBuf[1] = ( USHORT ) ( xTicks >> 16UL ); - - } - while( ( xStatus == MB_ENOERR ) && ( ePPPThrCtlCur == CONNECTED ) ); - - ( void )eMBDisable( ); - ( void )eMBClose( ); - } - } - /* FIXME: pppClose bugs because thread is not stopped. */ - /* Connection has been closed. */ - pppClose( ppp_con_fd ); - } - - /* Wait 1s until reopening the connection. */ - vTaskDelay( ( portTickType ) ( 1000UL / portTICK_RATE_MS ) ); - } - while( pdTRUE ); -} - -void -vPPPStatusCB( void *ctx, int err, void *arg ) -{ - /* Imported from ipcp.c */ - extern char *_inet_ntoa( u32_t n ); - - ePPPThreadControl ePPPThrCtlNew; - struct ppp_addrs *ppp_addrs; - - switch ( err ) - { - /* No error. */ - case PPPERR_NONE: - ePPPThrCtlNew = CONNECTED; - ppp_addrs = arg; - vMBPortLog( MB_LOG_INFO, "PPP", "new PPP connection established\r\n" ); - vMBPortLog( MB_LOG_INFO, "PPP", " our IP address = %s\r\n", - _inet_ntoa( ppp_addrs->our_ipaddr.addr ) ); - vMBPortLog( MB_LOG_INFO, "PPP", " his IP address = %s\r\n", - _inet_ntoa( ppp_addrs->his_ipaddr.addr ) ); - vMBPortLog( MB_LOG_INFO, "PPP", " netmask = %s\r\n", - _inet_ntoa( ppp_addrs->netmask.addr ) ); - break; - default: - ePPPThrCtlNew = DISCONNECT; - vMBPortLog( MB_LOG_ERROR, "PPP", "PPP connection died ( err = %d )\r\n", err ); - break; - } - vPortEnterCritical( ); - ePPPThrCtl = ePPPThrCtlNew; - vPortExitCritical( ); -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_HOLDING_START ) && - ( usAddress + usNRegs <= REG_HOLDING_START + REG_HOLDING_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegHoldingStart ); - switch ( eMode ) - { - /* Pass current register values to the protocol stack. */ - case MB_REG_READ: - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( UCHAR ) ( usRegHoldingBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( UCHAR ) ( usRegHoldingBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - break; - - /* Update current register values with new values from the - * protocol stack. */ - case MB_REG_WRITE: - while( usNRegs > 0 ) - { - usRegHoldingBuf[iRegIndex] = *pucRegBuffer++ << 8; - usRegHoldingBuf[iRegIndex] |= *pucRegBuffer++; - iRegIndex++; - usNRegs--; - } - } - } - else - { - eStatus = MB_ENOREG; - } - return eStatus; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/demo.hzp b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/demo.hzp deleted file mode 100644 index e0e7599de..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/demo.hzp +++ /dev/null @@ -1,225 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/demo.hzs b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/demo.hzs deleted file mode 100644 index 05e924218..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/demo.hzs +++ /dev/null @@ -1,74 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/croutine.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/croutine.c deleted file mode 100644 index 5906f1535..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/croutine.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/* Lists for ready and blocked co-routines. --------------------*/ -static xList pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ -static xList xDelayedCoRoutineList1; /*< Delayed co-routines. */ -static xList xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ -static xList * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */ -static xList * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ -static xList xPendingReadyList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ - -/* Other file private variables. --------------------------------*/ -corCRCB * pxCurrentCoRoutine = NULL; -static unsigned portBASE_TYPE uxTopCoRoutineReadyPriority = 0; -static portTickType xCoRoutineTickCount = 0; - -/* The initial state of the co-routine when it is created. */ -#define corINITIAL_STATE ( 0 ) - -/* - * Place the co-routine represented by pxCRCB into the appropriate ready queue - * for the priority. It is inserted at the end of the list. - * - * This macro accesses the co-routine ready lists and therefore must not be - * used from within an ISR. - */ -#define prvAddCoRoutineToReadyQueue( pxCRCB ) \ -{ \ - if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ - { \ - uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ - } \ - vListInsertEnd( ( xList * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ -} - -/* - * Utility to ready all the lists used by the scheduler. This is called - * automatically upon the creation of the first co-routine. - */ -static void prvInitialiseCoRoutineLists( void ); - -/* - * Co-routines that are readied by an interrupt cannot be placed directly into - * the ready lists (there is no mutual exclusion). Instead they are placed in - * in the pending ready list in order that they can later be moved to the ready - * list by the co-routine scheduler. - */ -static inline void prvCheckPendingReadyList( void ); - -/* - * Macro that looks at the list of co-routines that are currently delayed to - * see if any require waking. - * - * Co-routines are stored in the queue in the order of their wake time - - * meaning once one co-routine has been found whose timer has not expired - * we need not look any further down the list. - */ -static inline void prvCheckDelayedList( void ); - -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ) -{ -signed portBASE_TYPE xReturn; -corCRCB *pxCoRoutine; - - /* Allocate the memory that will store the co-routine control block. */ - pxCoRoutine = ( corCRCB * ) pvPortMalloc( sizeof( corCRCB ) ); - if( pxCoRoutine ) - { - /* If pxCurrentCoRoutine is NULL then this is the first co-routine to - be created and the co-routine data structures need initialising. */ - if( pxCurrentCoRoutine == NULL ) - { - pxCurrentCoRoutine = pxCoRoutine; - prvInitialiseCoRoutineLists(); - } - - /* Check the priority is within limits. */ - if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) - { - uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; - } - - /* Fill out the co-routine control block from the function parameters. */ - pxCoRoutine->uxState = corINITIAL_STATE; - pxCoRoutine->uxPriority = uxPriority; - pxCoRoutine->uxIndex = uxIndex; - pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; - - /* Initialise all the other co-routine control block parameters. */ - vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); - vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); - - /* Set the co-routine control block as a link back from the xListItem. - This is so we can get back to the containing CRCB from a generic item - in a list. */ - listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); - listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); - - /* Event lists are always in priority order. */ - listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); - - /* Now the co-routine has been initialised it can be added to the ready - list at the correct priority. */ - prvAddCoRoutineToReadyQueue( pxCoRoutine ); - - xReturn = pdPASS; - } - else - { - xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList ) -{ -portTickType xTimeToWake; - - /* Calculate the time to wake - this may overflow but this is - not a problem. */ - xTimeToWake = xCoRoutineTickCount + xTicksToDelay; - - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xCoRoutineTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedCoRoutineList, ( xListItem * ) &( pxCurrentCoRoutine->xGenericListItem ) ); - } - - if( pxEventList ) - { - /* Also add the co-routine to an event list. If this is done then the - function must be called with interrupts disabled. */ - vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); - } -} -/*-----------------------------------------------------------*/ - -static inline void prvCheckPendingReadyList( void ) -{ - /* Are there any co-routines waiting to get moved to the ready list? These - are co-routines that have been readied by an ISR. The ISR cannot access - the ready lists itself. */ - while( !listLIST_IS_EMPTY( &xPendingReadyList ) ) - { - corCRCB *pxUnblockedCRCB; - - /* The pending ready list can be accessed by an ISR. */ - portDISABLE_INTERRUPTS(); - { - pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyList) ); - vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); - } - portENABLE_INTERRUPTS(); - - vListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); - prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); - } -} -/*-----------------------------------------------------------*/ - -static inline void prvCheckDelayedList( void ) -{ -static portTickType xLastTickCount, xPassedTicks; -corCRCB *pxCRCB; - - xPassedTicks = xTaskGetTickCount() - xLastTickCount; - while( xPassedTicks ) - { - xCoRoutineTickCount++; - xPassedTicks--; - - /* If the tick count has overflowed we need to swap the ready lists. */ - if( xCoRoutineTickCount == 0 ) - { - xList * pxTemp; - - /* Tick count has overflowed so we need to swap the delay lists. If there are - any items in pxDelayedCoRoutineList here then there is an error! */ - pxTemp = pxDelayedCoRoutineList; - pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; - pxOverflowDelayedCoRoutineList = pxTemp; - } - - /* See if this tick has made a timeout expire. */ - while( ( pxCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ) ) != NULL ) - { - if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) - { - /* Timeout not yet expired. */ - break; - } - - portDISABLE_INTERRUPTS(); - { - /* The event could have occurred just before this critical - section. If this is the case then the generic list item will - have been moved to the pending ready list and the following - line is still valid. Also the pvContainer parameter will have - been set to NULL so the following lines are also valid. */ - vListRemove( &( pxCRCB->xGenericListItem ) ); - - /* Is the co-routine waiting on an event also? */ - if( pxCRCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxCRCB->xEventListItem ) ); - } - } - portENABLE_INTERRUPTS(); - - prvAddCoRoutineToReadyQueue( pxCRCB ); - } - } - - xLastTickCount = xCoRoutineTickCount; -} -/*-----------------------------------------------------------*/ - -void vCoRoutineSchedule( void ) -{ - /* See if any co-routines readied by events need moving to the ready lists. */ - prvCheckPendingReadyList(); - - /* See if any delayed co-routines have timed out. */ - prvCheckDelayedList(); - - /* Find the highest priority queue that contains ready co-routines. */ - while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) - { - if( uxTopCoRoutineReadyPriority == 0 ) - { - /* No more co-routines to check. */ - return; - } - --uxTopCoRoutineReadyPriority; - } - - /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines - of the same priority get an equal share of the processor time. */ - listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); - - /* Call the co-routine. */ - ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); - - return; -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseCoRoutineLists( void ) -{ -unsigned portBASE_TYPE uxPriority; - - for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) - { - vListInitialise( ( xList * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); - } - - vListInitialise( ( xList * ) &xDelayedCoRoutineList1 ); - vListInitialise( ( xList * ) &xDelayedCoRoutineList2 ); - vListInitialise( ( xList * ) &xPendingReadyList ); - - /* Start with pxDelayedCoRoutineList using list1 and the - pxOverflowDelayedCoRoutineList using list2. */ - pxDelayedCoRoutineList = &xDelayedCoRoutineList1; - pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList ) -{ -corCRCB *pxUnblockedCRCB; -signed portBASE_TYPE xReturn; - - /* This function is called from within an interrupt. It can only access - event lists and the pending ready list. */ - pxUnblockedCRCB = ( corCRCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); - vListRemove( &( pxUnblockedCRCB->xEventListItem ) ); - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedCRCB->xEventListItem ) ); - - if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) - { - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/FreeRTOS.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/FreeRTOS.h deleted file mode 100644 index 0d0f7d289..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/FreeRTOS.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef INC_FREERTOS_H -#define INC_FREERTOS_H - - -/* - * Include the generic headers required for the FreeRTOS port being used. - */ -#include - -/* Basic FreeRTOS definitions. */ -#include "projdefs.h" - -/* Application specific configuration options. */ -#include "FreeRTOSConfig.h" - -/* Definitions specific to the port being used. */ -#include "portable.h" - - - - - - - -/* - * Check all the required application specific macros have been defined. - * These macros are application specific and (as downloaded) are defined - * within FreeRTOSConfig.h. - */ - -#ifndef configUSE_PREEMPTION - #error Missing definition: configUSE_PREEMPTION should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_IDLE_HOOK - #error Missing definition: configUSE_IDLE_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_TICK_HOOK - #error Missing definition: configUSE_TICK_HOOK should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_CO_ROUTINES - #error Missing definition: configUSE_CO_ROUTINES should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskPrioritySet - #error Missing definition: INCLUDE_vTaskPrioritySet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_uxTaskPriorityGet - #error Missing definition: INCLUDE_uxTaskPriorityGet should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelete - #error Missing definition: INCLUDE_vTaskDelete should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskCleanUpResources - #error Missing definition: INCLUDE_vTaskCleanUpResources should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskSuspend - #error Missing definition: INCLUDE_vTaskSuspend should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelayUntil - #error Missing definition: INCLUDE_vTaskDelayUntil should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef INCLUDE_vTaskDelay - #error Missing definition: INCLUDE_vTaskDelay should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_16_BIT_TICKS - #error Missing definition: configUSE_16_BIT_TICKS should be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/croutine.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/croutine.h deleted file mode 100644 index 1e85c807f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/croutine.h +++ /dev/null @@ -1,713 +0,0 @@ -/* - FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ -#ifndef CO_ROUTINE_H -#define CO_ROUTINE_H - -#include "list.h" - -/* Used to hide the implementation of the co-routine control block. The -control block structure however has to be included in the header due to -the macro implementation of the co-routine functionality. */ -typedef void * xCoRoutineHandle; - -/* Defines the prototype to which co-routine functions must conform. */ -typedef void (*crCOROUTINE_CODE)( xCoRoutineHandle, unsigned portBASE_TYPE ); - -typedef struct corCoRoutineControlBlock -{ - crCOROUTINE_CODE pxCoRoutineFunction; - xListItem xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ - xListItem xEventListItem; /*< List item used to place the CRCB in event lists. */ - unsigned portBASE_TYPE uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ - unsigned portBASE_TYPE uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ - unsigned portSHORT uxState; /*< Used internally by the co-routine implementation. */ -} corCRCB; /* Co-routine control block. Note must be identical in size down to uxPriority with tskTCB. */ - -/** - * croutine. h - *

- portBASE_TYPE xCoRoutineCreate(

-                                 crCOROUTINE_CODE pxCoRoutineCode,

-                                 unsigned portBASE_TYPE uxPriority,

-                                 unsigned portBASE_TYPE uxIndex

-                               );
- * - * Create a new co-routine and add it to the list of co-routines that are - * ready to run. - * - * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine - * functions require special syntax - see the co-routine section of the WEB - * documentation for more information. - * - * @param uxPriority The priority with respect to other co-routines at which - * the co-routine will run. - * - * @param uxIndex Used to distinguish between different co-routines that - * execute the same function. See the example below and the co-routine section - * of the WEB documentation for further information. - * - * @return pdPASS if the co-routine was successfully created and added to a ready - * list, otherwise an error code defined with ProjDefs.h. - * - * Example usage: -

- // Co-routine to be created.

- void vFlashCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- // This may not be necessary for const variables.

- static const char cLedToFlash[ 2 ] = { 5, 6 };

- static const portTickType xTimeToDelay[ 2 ] = { 200, 400 };

-

-     // Must start every co-routine with a call to crSTART();

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-         // This co-routine just delays for a fixed period, then toggles

-         // an LED.  Two co-routines are created using this function, so

-         // the uxIndex parameter is used to tell the co-routine which

-         // LED to flash and how long to delay.  This assumes xQueue has

-         // already been created.

-         vParTestToggleLED( cLedToFlash[ uxIndex ] );

-         crDELAY( xHandle, uxFlashRates[ uxIndex ] );

-     }

-

-     // Must end every co-routine with a call to crEND();

-     crEND();

- }

-

- // Function that creates two co-routines.

- void vOtherFunction( void )

- {

- unsigned char ucParameterToPass;

- xTaskHandle xHandle;

-		

-     // Create two co-routines at priority 0.  The first is given index 0

-     // so (from the code above) toggles LED 5 every 200 ticks.  The second

-     // is given index 1 so toggles LED 6 every 400 ticks.

-     for( uxIndex = 0; uxIndex < 2; uxIndex++ )

-     {

-         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );

-     }

- }

-   
- * \defgroup xCoRoutineCreate xCoRoutineCreate - * \ingroup Tasks - */ -signed portBASE_TYPE xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, unsigned portBASE_TYPE uxPriority, unsigned portBASE_TYPE uxIndex ); - - -/** - * croutine. h - *

- void vCoRoutineSchedule( void );
- * - * Run a co-routine. - * - * vCoRoutineSchedule() executes the highest priority co-routine that is able - * to run. The co-routine will execute until it either blocks, yields or is - * preempted by a task. Co-routines execute cooperatively so one - * co-routine cannot be preempted by another, but can be preempted by a task. - * - * If an application comprises of both tasks and co-routines then - * vCoRoutineSchedule should be called from the idle task (in an idle task - * hook). - * - * Example usage: -

- // This idle task hook will schedule a co-routine each time it is called.

- // The rest of the idle task will execute between co-routine calls.

- void vApplicationIdleHook( void )

- {

-	vCoRoutineSchedule();

- }

-

- // Alternatively, if you do not require any other part of the idle task to

- // execute, the idle task hook can call vCoRoutineScheduler() within an

- // infinite loop.

- void vApplicationIdleHook( void )

- {

-    for( ;; )

-    {

-        vCoRoutineSchedule();

-    }

- }

- 
- * \defgroup vCoRoutineSchedule vCoRoutineSchedule - * \ingroup Tasks - */ -void vCoRoutineSchedule( void ); - -/** - * croutine. h - *

- crSTART( xCoRoutineHandle xHandle );
- * - * This macro MUST always be called at the start of a co-routine function. - * - * Example usage: -

- // Co-routine to be created.

- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- static portLONG ulAVariable;

-

-     // Must start every co-routine with a call to crSTART();

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-          // Co-routine functionality goes here.

-     }

-

-     // Must end every co-routine with a call to crEND();

-     crEND();

- }
- * \defgroup crSTART crSTART - * \ingroup Tasks - */ -#define crSTART( pxCRCB ) switch( ( ( corCRCB * )pxCRCB )->uxState ) { case 0: - -/** - * croutine. h - *

- crEND();
- * - * This macro MUST always be called at the end of a co-routine function. - * - * Example usage: -

- // Co-routine to be created.

- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- static portLONG ulAVariable;

-

-     // Must start every co-routine with a call to crSTART();

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-          // Co-routine functionality goes here.

-     }

-

-     // Must end every co-routine with a call to crEND();

-     crEND();

- }
- * \defgroup crSTART crSTART - * \ingroup Tasks - */ -#define crEND() } - -/* - * These macros are intended for internal use by the co-routine implementation - * only. The macros should not be used directly by application writers. - */ -#define crSET_STATE0( xHandle ) ( ( corCRCB * )xHandle)->uxState = (__LINE__ * 2); return; case (__LINE__ * 2): -#define crSET_STATE1( xHandle ) ( ( corCRCB * )xHandle)->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1): - -/** - * croutine. h - *

- crDELAY( xCoRoutineHandle xHandle, portTickType xTicksToDelay );
- * - * Delay a co-routine for a fixed period of time. - * - * crDELAY can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * @param xHandle The handle of the co-routine to delay. This is the xHandle - * parameter of the co-routine function. - * - * @param xTickToDelay The number of ticks that the co-routine should delay - * for. The actual amount of time this equates to is defined by - * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_RATE_MS - * can be used to convert ticks to milliseconds. - * - * Example usage: -

- // Co-routine to be created.

- void vACoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- // This may not be necessary for const variables.

- // We are to delay for 200ms.

- static const xTickType xDelayTime = 200 / portTICK_RATE_MS;

-

-     // Must start every co-routine with a call to crSTART();

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-        // Delay for 200ms.

-        crDELAY( xHandle, xDelayTime );

-

-        // Do something here.

-     }

-

-     // Must end every co-routine with a call to crEND();

-     crEND();

- }
- * \defgroup crDELAY crDELAY - * \ingroup Tasks - */ -#define crDELAY( xHandle, xTicksToDelay ) \ - if( xTicksToDelay > 0 ) \ - { \ - vCoRoutineAddToDelayedList( xTicksToDelay, NULL ); \ - } \ - crSET_STATE0( xHandle ); - -/** - *

- crQUEUE_SEND(

-                  xCoRoutineHandle xHandle,

-                  xQueueHandle pxQueue,

-                  void *pvItemToQueue,

-                  portTickType xTicksToWait,

-                  portBASE_TYPE *pxResult

-             )
- * - * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine - * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. - * - * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas - * xQueueSend() and xQueueReceive() can only be used from tasks. - * - * crQUEUE_SEND can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xHandle The handle of the calling co-routine. This is the xHandle - * parameter of the co-routine function. - * - * @param pxQueue The handle of the queue on which the data will be posted. - * The handle is obtained as the return value when the queue is created using - * the xQueueCreate() API function. - * - * @param pvItemToQueue A pointer to the data being posted onto the queue. - * The number of bytes of each queued item is specified when the queue is - * created. This number of bytes is copied from pvItemToQueue into the queue - * itself. - * - * @param xTickToDelay The number of ticks that the co-routine should block - * to wait for space to become available on the queue, should space not be - * available immediately. The actual amount of time this equates to is defined - * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant - * portTICK_RATE_MS can be used to convert ticks to milliseconds (see example - * below). - * - * @param pxResult The variable pointed to by pxResult will be set to pdPASS if - * data was successfully posted onto the queue, otherwise it will be set to an - * error defined within ProjDefs.h. - * - * Example usage: -

- // Co-routine function that blocks for a fixed period then posts a number onto

- // a queue.

- static void prvCoRoutineFlashTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- static portBASE_TYPE xNumberToPost = 0;

- static portBASE_TYPE xResult;

-

-    // Co-routines must begin with a call to crSTART().

-    crSTART( xHandle );

-

-    for( ;; )

-    {

-        // This assumes the queue has already been created.

-        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );

-

-        if( xResult != pdPASS )

-        {

-            // The message was not posted!

-        }

-

-        // Increment the number to be posted onto the queue.

-        xNumberToPost++;

-

-        // Delay for 100 ticks.

-        crDELAY( xHandle, 100 );

-    }

-

-    // Co-routines must end with a call to crEND().

-    crEND();

- }
- * \defgroup crQUEUE_SEND crQUEUE_SEND - * \ingroup Tasks - */ -#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ -{ \ - *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, xTicksToWait ); \ - if( *pxResult == errQUEUE_BLOCKED ) \ - { \ - crSET_STATE0( xHandle ); \ - *pxResult = xQueueCRSend( pxQueue, pvItemToQueue, 0 ); \ - } \ - if( *pxResult == errQUEUE_YIELD ) \ - { \ - crSET_STATE1( xHandle ); \ - *pxResult = pdPASS; \ - } \ -} - -/** - * croutine. h - *

-  crQUEUE_RECEIVE(

-                     xCoRoutineHandle xHandle,

-                     xQueueHandle pxQueue,

-                     void *pvBuffer,

-                     portTickType xTicksToWait,

-                     portBASE_TYPE *pxResult

-                 )
- * - * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine - * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. - * - * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas - * xQueueSend() and xQueueReceive() can only be used from tasks. - * - * crQUEUE_RECEIVE can only be called from the co-routine function itself - not - * from within a function called by the co-routine function. This is because - * co-routines do not maintain their own stack. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xHandle The handle of the calling co-routine. This is the xHandle - * parameter of the co-routine function. - * - * @param pxQueue The handle of the queue from which the data will be received. - * The handle is obtained as the return value when the queue is created using - * the xQueueCreate() API function. - * - * @param pvBuffer The buffer into which the received item is to be copied. - * The number of bytes of each queued item is specified when the queue is - * created. This number of bytes is copied into pvBuffer. - * - * @param xTickToDelay The number of ticks that the co-routine should block - * to wait for data to become available from the queue, should data not be - * available immediately. The actual amount of time this equates to is defined - * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant - * portTICK_RATE_MS can be used to convert ticks to milliseconds (see the - * crQUEUE_SEND example). - * - * @param pxResult The variable pointed to by pxResult will be set to pdPASS if - * data was successfully retrieved from the queue, otherwise it will be set to - * an error code as defined within ProjDefs.h. - * - * Example usage: -

- // A co-routine receives the number of an LED to flash from a queue.  It

- // blocks on the queue until the number is received.

- static void prvCoRoutineFlashWorkTask( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // Variables in co-routines must be declared static if they must maintain value across a blocking call.

- static portBASE_TYPE xResult;

- static unsigned portBASE_TYPE uxLEDToFlash;

-

-    // All co-routines must start with a call to crSTART().

-    crSTART( xHandle );

-

-    for( ;; )

-    {

-        // Wait for data to become available on the queue.

-        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );

-

-        if( xResult == pdPASS )

-        {

-            // We received the LED to flash - flash it!

-            vParTestToggleLED( uxLEDToFlash );

-        }

-    }

-

-    crEND();

- }
- * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE - * \ingroup Tasks - */ -#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ -{ \ - *pxResult = xQueueCRReceive( pxQueue, pvBuffer, xTicksToWait ); \ - if( *pxResult == errQUEUE_BLOCKED ) \ - { \ - crSET_STATE0( xHandle ); \ - *pxResult = xQueueCRReceive( pxQueue, pvBuffer, 0 ); \ - } \ - if( *pxResult == errQUEUE_YIELD ) \ - { \ - crSET_STATE1( xHandle ); \ - *pxResult = pdPASS; \ - } \ -} - -/** - * croutine. h - *

-  crQUEUE_SEND_FROM_ISR(

-                            xQueueHandle pxQueue,

-                            void *pvItemToQueue,

-                            portBASE_TYPE xCoRoutinePreviouslyWoken

-                       )
- * - * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the - * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() - * functions used by tasks. - * - * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to - * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and - * xQueueReceiveFromISR() can only be used to pass data between a task and and - * ISR. - * - * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue - * that is being used from within a co-routine. - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto - * the same queue multiple times from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. - * - * @return pdTRUE if a co-routine was woken by posting onto the queue. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage: -

- // A co-routine that blocks on a queue waiting for characters to be received.

- static void vReceivingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- portCHAR cRxedChar;

- portBASE_TYPE xResult;

-

-     // All co-routines must start with a call to crSTART().

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-         // Wait for data to become available on the queue.  This assumes the

-         // queue xCommsRxQueue has already been created!

-         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );

-

-         // Was a character received?

-         if( xResult == pdPASS )

-         {

-             // Process the character here.

-         }

-     }

-

-     // All co-routines must end with a call to crEND().

-     crEND();

- }

-

- // An ISR that uses a queue to send characters received on a serial port to

- // a co-routine.

- void vUART_ISR( void )

- {

- portCHAR cRxedChar;

- portBASE_TYPE xCRWokenByPost = pdFALSE;

-

-     // We loop around reading characters until there are none left in the UART.

-     while( UART_RX_REG_NOT_EMPTY() )

-     {

-         // Obtain the character from the UART.

-         cRxedChar = UART_RX_REG;

-

-         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE

-         // the first time around the loop.  If the post causes a co-routine

-         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.

-         // In this manner we can ensure that if more than one co-routine is

-         // blocked on the queue only one is woken by this ISR no matter how

-         // many characters are posted to the queue.

-         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );

-     }

- }
- * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR - * \ingroup Tasks - */ -#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) - - -/** - * croutine. h - *

-  crQUEUE_SEND_FROM_ISR(

-                            xQueueHandle pxQueue,

-                            void *pvBuffer,

-                            portBASE_TYPE * pxCoRoutineWoken

-                       )
- * - * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the - * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() - * functions used by tasks. - * - * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to - * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and - * xQueueReceiveFromISR() can only be used to pass data between a task and and - * ISR. - * - * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data - * from a queue that is being used from within a co-routine (a co-routine - * posted to the queue). - * - * See the co-routine section of the WEB documentation for information on - * passing data between tasks and co-routines and between ISR's and - * co-routines. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvBuffer A pointer to a buffer into which the received item will be - * placed. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from the queue into - * pvBuffer. - * - * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become - * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a - * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise - * *pxCoRoutineWoken will remain unchanged. - * - * @return pdTRUE an item was successfully received from the queue, otherwise - * pdFALSE. - * - * Example usage: -

- // A co-routine that posts a character to a queue then blocks for a fixed

- // period.  The character is incremented each time.

- static void vSendingCoRoutine( xCoRoutineHandle xHandle, unsigned portBASE_TYPE uxIndex )

- {

- // cChar holds its value while this co-routine is blocked and must therefore

- // be declared static.

- static portCHAR cCharToTx = 'a';

- portBASE_TYPE xResult;

-

-     // All co-routines must start with a call to crSTART().

-     crSTART( xHandle );

-

-     for( ;; )

-     {

-         // Send the next character to the queue.

-         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );

-

-         if( xResult == pdPASS )

-         {

-             // The character was successfully posted to the queue.

-         }

-		 else

-		 {

-			// Could not post the character to the queue.

-		 }

-

-         // Enable the UART Tx interrupt to cause an interrupt in this

-		 // hypothetical UART.  The interrupt will obtain the character

-		 // from the queue and send it.

-		 ENABLE_RX_INTERRUPT();

-

-		 // Increment to the next character then block for a fixed period.

-		 // cCharToTx will maintain its value across the delay as it is

-		 // declared static.

-		 cCharToTx++;

-		 if( cCharToTx > 'x' )

-		 {

-			cCharToTx = 'a';

-		 }

-		 crDELAY( 100 );

-     }

-

-     // All co-routines must end with a call to crEND().

-     crEND();

- }

-

- // An ISR that uses a queue to receive characters to send on a UART.

- void vUART_ISR( void )

- {

- portCHAR cCharToTx;

- portBASE_TYPE xCRWokenByPost = pdFALSE;

-

-     while( UART_TX_REG_EMPTY() )

-     {

-         // Are there any characters in the queue waiting to be sent?

-		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine

-		 // is woken by the post - ensuring that only a single co-routine is

-		 // woken no matter how many times we go around this loop.

-         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )

-		 {

-			 SEND_CHARACTER( cCharToTx );

-		 }

-     }

- }
- * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR - * \ingroup Tasks - */ -#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( pxQueue, pvBuffer, pxCoRoutineWoken ) - -/* - * This function is intended for internal use by the co-routine macros only. - * The macro nature of the co-routine implementation requires that the - * prototype appears here. The function should not be used by application - * writers. - * - * Removes the current co-routine from its ready list and places it in the - * appropriate delayed list. - */ -void vCoRoutineAddToDelayedList( portTickType xTicksToDelay, xList *pxEventList ); - -/* - * This function is intended for internal use by the queue implementation only. - * The function should not be used by application writers. - * - * Removes the highest priority co-routine from the event list and places it in - * the pending ready list. - */ -signed portBASE_TYPE xCoRoutineRemoveFromEventList( const xList *pxEventList ); - - -#endif /* CO_ROUTINE_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/list.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/list.h deleted file mode 100644 index bd144c9aa..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/list.h +++ /dev/null @@ -1,270 +0,0 @@ -/* - FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * This is the list implementation used by the scheduler. While it is tailored - * heavily for the schedulers needs, it is also available for use by - * application code. - * - * xLists can only store pointers to xListItems. Each xListItem contains a - * numeric value (xItemValue). Most of the time the lists are sorted in - * descending item value order. - * - * Lists are created already containing one list item. The value of this - * item is the maximum possible that can be stored, it is therefore always at - * the end of the list and acts as a marker. The list member pxHead always - * points to this marker - even though it is at the tail of the list. This - * is because the tail contains a wrap back pointer to the true head of - * the list. - * - * In addition to it's value, each list item contains a pointer to the next - * item in the list (pxNext), a pointer to the list it is in (pxContainer) - * and a pointer to back to the object that contains it. These later two - * pointers are included for efficiency of list manipulation. There is - * effectively a two way link between the object containing the list item and - * the list item itself. - * - * - * \page ListIntroduction List Implementation - * \ingroup FreeRTOSIntro - */ - - -#ifndef LIST_H -#define LIST_H - -/* - * Definition of the only type of object that a list can contain. - */ -struct xLIST_ITEM -{ - portTickType xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ - volatile struct xLIST_ITEM * pxNext; /*< Pointer to the next xListItem in the list. */ - volatile struct xLIST_ITEM * pxPrevious;/*< Pointer to the previous xListItem in the list. */ - void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ - void * pvContainer; /*< Pointer to the list in which this list item is placed (if any). */ -}; -typedef struct xLIST_ITEM xListItem; /* For some reason lint wants this as two separate definitions. */ - -struct xMINI_LIST_ITEM -{ - portTickType xItemValue; - volatile struct xLIST_ITEM *pxNext; - volatile struct xLIST_ITEM *pxPrevious; -}; -typedef struct xMINI_LIST_ITEM xMiniListItem; - -/* - * Definition of the type of queue used by the scheduler. - */ -typedef struct xLIST -{ - volatile unsigned portBASE_TYPE uxNumberOfItems; - volatile xListItem * pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to pvListGetOwnerOfNextEntry (). */ - volatile xMiniListItem xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ -} xList; - -/* - * Access macro to set the owner of a list item. The owner of a list item - * is the object (usually a TCB) that contains the list item. - * - * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( pxListItem )->pvOwner = ( void * ) pxOwner - -/* - * Access macro to set the value of the list item. In most cases the value is - * used to sort the list in descending order. - * - * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( pxListItem )->xItemValue = xValue - -/* - * Access macro the retrieve the value of the list item. The value can - * represent anything - for example a the priority of a task, or the time at - * which a task should be unblocked. - * - * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) - -/* - * Access macro to determine if a list contains any items. The macro will - * only have the value true if the list is empty. - * - * \page listLIST_IS_EMPTY listLIST_IS_EMPTY - * \ingroup LinkedList - */ -#define listLIST_IS_EMPTY( pxList ) ( ( pxList )->uxNumberOfItems == ( unsigned portBASE_TYPE ) 0 ) - -/* - * Access macro to return the number of items in the list. - */ -#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) - -/* - * Access function to obtain the owner of the next entry in a list. - * - * The list member pxIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list - * and returns that entries pxOwner parameter. Using multiple calls to this - * function it is therefore possible to move through every item contained in - * a list. - * - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the next item owner is to be returned. - * - * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ - /* Increment the index to the next item and return the item, ensuring */ \ - /* we don't return the marker used at the end of the list. */ \ - ( pxList )->pxIndex = ( pxList )->pxIndex->pxNext; \ - if( ( pxList )->pxIndex == ( xListItem * ) &( ( pxList )->xListEnd ) ) \ - { \ - ( pxList )->pxIndex = ( pxList )->pxIndex->pxNext; \ - } \ - pxTCB = ( pxList )->pxIndex->pvOwner - - -/* - * Access function to obtain the owner of the first entry in a list. Lists - * are normally sorted in ascending item value order. - * - * This function returns the pxOwner member of the first item in the list. - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the owner of the head item is to be - * returned. - * - * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( pxList->uxNumberOfItems != ( unsigned portBASE_TYPE ) 0 ) ? ( (&( pxList->xListEnd ))->pxNext->pvOwner ) : ( NULL ) ) - -/* - * Check to see if a list item is within a list. The list item maintains a - * "container" pointer that points to the list it is in. All this macro does - * is check to see if the container and the list match. - * - * @param pxList The list we want to know if the list item is within. - * @param pxListItem The list item we want to know if is in the list. - * @return pdTRUE is the list item is in the list, otherwise pdFALSE. - * pointer against - */ -#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( pxListItem )->pvContainer == ( void * ) pxList ) - -/* - * Must be called before a list is used! This initialises all the members - * of the list structure and inserts the xListEnd item into the list as a - * marker to the back of the list. - * - * @param pxList Pointer to the list being initialised. - * - * \page vListInitialise vListInitialise - * \ingroup LinkedList - */ -void vListInitialise( xList *pxList ); - -/* - * Must be called before a list item is used. This sets the list container to - * null so the item does not think that it is already contained in a list. - * - * @param pxItem Pointer to the list item being initialised. - * - * \page vListInitialiseItem vListInitialiseItem - * \ingroup LinkedList - */ -void vListInitialiseItem( xListItem *pxItem ); - -/* - * Insert a list item into a list. The item will be inserted into the list in - * a position determined by its item value (descending item value order). - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The item to that is to be placed in the list. - * - * \page vListInsert vListInsert - * \ingroup LinkedList - */ -void vListInsert( xList *pxList, xListItem *pxNewListItem ); - -/* - * Insert a list item into a list. The item will be inserted in a position - * such that it will be the last item within the list returned by multiple - * calls to listGET_OWNER_OF_NEXT_ENTRY. - * - * The list member pvIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list. - * Placing an item in a list using vListInsertEnd effectively places the item - * in the list position pointed to by pvIndex. This means that every other - * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before - * the pvIndex parameter again points to the item being inserted. - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The list item to be inserted into the list. - * - * \page vListInsertEnd vListInsertEnd - * \ingroup LinkedList - */ -void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ); - -/* - * Remove an item from a list. The list item has a pointer to the list that - * it is in, so only the list item need be passed into the function. - * - * @param vListRemove The item to be removed. The item will remove itself from - * the list pointed to by it's pxContainer parameter. - * - * \page vListRemove vListRemove - * \ingroup LinkedList - */ -void vListRemove( xListItem *pxItemToRemove ); - - - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/portable.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/portable.h deleted file mode 100644 index 3ab6fa726..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/portable.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http:www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http:www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/*----------------------------------------------------------- - * Portable layer API. Each function must be defined for each port. - *----------------------------------------------------------*/ - -#ifndef PORTABLE_H -#define PORTABLE_H - -/* Include the macro file relevant to the port being used. */ - -#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT - #include "..\..\source\portable\owatcom\16bitdos\pc\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT - #include "..\..\source\portable\owatcom\16bitdos\flsh186\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef GCC_MEGA_AVR - #include "../portable/GCC/ATMega323/portmacro.h" -#endif - -#ifdef IAR_MEGA_AVR - #include "../portable/IAR/ATMega323/portmacro.h" -#endif - -#ifdef MPLAB_PIC18F_PORT - #include "..\..\source\portable\MPLAB\PIC18F\portmacro.h" -#endif - -#ifdef _FEDPICC - #include "libFreeRTOS/Include/portmacro.h" -#endif - -#ifdef SDCC_CYGNAL - #include "../../Source/portable/SDCC/Cygnal/portmacro.h" -#endif - -#ifdef GCC_ARM7 - #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" -#endif - -#ifdef GCC_MSP430 - #include "../../Source/portable/GCC/MSP430F449/portmacro.h" -#endif - -#ifdef ROWLEY_MSP430 - #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" -#endif - -#ifdef KEIL_ARM7 - #include "..\..\Source\portable\Keil\ARM7\portmacro.h" -#endif - -#ifdef SAM7_GCC - #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" -#endif - -#ifdef SAM7_IAR - #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" -#endif - -#ifdef LPC2000_IAR - #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" -#endif - -#ifdef STR71X_IAR - #include "..\..\Source\portable\IAR\STR71x\portmacro.h" -#endif - -#ifdef STR91X_IAR - #include "..\..\Source\portable\IAR\STR91x\portmacro.h" -#endif - -#ifdef GCC_H8S - #include "../../Source/portable/GCC/H8S2329/portmacro.h" -#endif - -#ifdef GCC_AT91FR40008 - #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" -#endif - -#ifdef RVDS_ARMCM3_LM3S102 - #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" -#endif - -#ifdef GCC_ARMCM3_LM3S102 - #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" -#endif - -#ifdef IAR_ARMCM3_LM - #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" -#endif - -#ifdef HCS12_CODE_WARRIOR - #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" -#endif - -#ifdef MICROBLAZE_GCC - #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" -#endif - -#ifdef TERN_EE - #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" -#endif - -#ifdef GCC_HCS12 - #include "../../Source/portable/GCC/HCS12/portmacro.h" -#endif - -#ifdef GCC_STR71X - #include "../portable/GCC/ARM7_STR71X/portmacro.h" -#endif - - -#ifdef BCC_INDUSTRIAL_PC_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef BCC_FLASH_LITE_186_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif -/* - * Setup the stack of a new task so it is ready to be placed under the - * scheduler control. The registers have to be placed on the stack in - * the order that the port expects to find them. - */ -portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ); - -/* - * Map to the memory management routines required for the port. - */ -void *pvPortMalloc( size_t xSize ); -void vPortFree( void *pv ); -void vPortInitialiseBlocks( void ); - -/* - * Setup the hardware ready for the scheduler to take control. This generally - * sets up a tick interrupt and sets timers for the correct tick frequency. - */ -portBASE_TYPE xPortStartScheduler( void ); - -/* - * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so - * the hardware is left in its original condition after the scheduler stops - * executing. - */ -void vPortEndScheduler( void ); - - -#endif /* PORTABLE_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/projdefs.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/projdefs.h deleted file mode 100644 index 739ee1e14..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/projdefs.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef PROJDEFS_H -#define PROJDEFS_H - -/* Defines to prototype to which task functions must conform. */ -typedef void (*pdTASK_CODE)( void * ); - -#define pdTRUE ( 1 ) -#define pdFALSE ( 0 ) - -#define pdPASS ( 1 ) -#define pdFAIL ( 0 ) -#define errQUEUE_EMPTY ( 0 ) -#define errQUEUE_FULL ( 0 ) - -/* Error definitions. */ -#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 ) -#define errNO_TASK_TO_RUN ( -2 ) -#define errQUEUE_BLOCKED ( -4 ) -#define errQUEUE_YIELD ( -5 ) - -#endif /* PROJDEFS_H */ - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/queue.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/queue.h deleted file mode 100644 index 4b25c8efa..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/queue.h +++ /dev/null @@ -1,471 +0,0 @@ -/* - FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef QUEUE_H -#define QUEUE_H - -typedef void * xQueueHandle; - -/** - * queue. h - *

- xQueueHandle xQueueCreate( 

-                              unsigned portBASE_TYPE uxQueueLength, 

-                              unsigned portBASE_TYPE uxItemSize 

-                          );

- * 
- * - * Creates a new queue instance. This allocates the storage required by the - * new queue and returns a handle for the queue. - * - * @param uxQueueLength The maximum number of items that the queue can contain. - * - * @param uxItemSize The number of bytes each item in the queue will require. - * Items are queued by copy, not by reference, so this is the number of bytes - * that will be copied for each posted item. Each item on the queue must be - * the same size. - * - * @return If the queue is successfully create then a handle to the newly - * created queue is returned. If the queue cannot be created then 0 is - * returned. - * - * Example usage: -

- struct AMessage

- {

-    portCHAR ucMessageID;

-    portCHAR ucData[ 20 ];

- };

-

- void vATask( void *pvParameters )

- {

- xQueueHandle xQueue1, xQueue2;

-

-    // Create a queue capable of containing 10 unsigned long values.

-    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );

-    if( xQueue1 == 0 )

-    {

-        // Queue was not created and must not be used.

-    }

-

-    // Create a queue capable of containing 10 pointers to AMessage structures.

-    // These should be passed by pointer as they contain a lot of data.

-    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );

-    if( xQueue2 == 0 )

-    {

-        // Queue was not created and must not be used.

-    }

-

-    // ... Rest of task code.

- }

- 
- * \defgroup xQueueCreate xQueueCreate - * \ingroup QueueManagement - */ -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); - -/** - * queue. h - *

- portBASE_TYPE xQueueSend( 

-                             xQueueHandle xQueue, 

-                             const void * pvItemToQueue, 

-                             portTickType xTicksToWait 

-                         );

- * 
- * - * Post an item on a queue. The item is queued by copy, not by reference. - * This function must not be called from an interrupt service routine. - * See xQueueSendFromISR () for an alternative which may be used in an ISR. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for space to become available on the queue, should it already - * be full. The call will return immediately if this is set to 0. The - * time is defined in tick periods so the constant portTICK_RATE_MS - * should be used to convert to real time if this is required. - * - * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. - * - * Example usage: -

- struct AMessage

- {

-    portCHAR ucMessageID;

-    portCHAR ucData[ 20 ];

- } xMessage;

-

- unsigned portLONG ulVar = 10UL;

-

- void vATask( void *pvParameters )

- {

- xQueueHandle xQueue1, xQueue2;

- struct AMessage *pxMessage;

-

-    // Create a queue capable of containing 10 unsigned long values.

-    xQueue1 = xQueueCreate( 10, sizeof( unsigned portLONG ) );

-

-    // Create a queue capable of containing 10 pointers to AMessage structures.

-    // These should be passed by pointer as they contain a lot of data.

-    xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );

-

-    // ...

-

-    if( xQueue1 != 0 )

-    {

-        // Send an unsigned long.  Wait for 10 ticks for space to become 

-        // available if necessary.

-        if( xQueueSend( xQueue1, ( void * ) &ulVar, ( portTickType ) 10 ) != pdPASS )

-        {

-            // Failed to post the message, even after 10 ticks.

-        }

-    }

-

-    if( xQueue2 != 0 )

-    {

-        // Send a pointer to a struct AMessage object.  Don't block if the

-        // queue is already full.

-        pxMessage = & xMessage;

-        xQueueSend( xQueue2, ( void * ) &pxMessage, ( portTickType ) 0 );

-    }

-

-	// ... Rest of task code.

- }

- 
- * \defgroup xQueueSend xQueueSend - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); - -/** - * queue. h - *

- portBASE_TYPE xQueueReceive( 

-                                xQueueHandle xQueue, 

-                                void *pvBuffer, 

-                                portTickType xTicksToWait 

-                            );
- * - * Receive an item from a queue. The item is received by copy so a buffer of - * adequate size must be provided. The number of bytes copied into the buffer - * was defined when the queue was created. - * - * This function must not be used in an interrupt service routine. See - * xQueueReceiveFromISR for an alternative that can. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pvBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param xTicksToWait The maximum amount of time the task should block - * waiting for an item to receive should the queue be empty at the time - * of the call. The time is defined in tick periods so the constant - * portTICK_RATE_MS should be used to convert to real time if this is required. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: -

- struct AMessage

- {

-    portCHAR ucMessageID;

-    portCHAR ucData[ 20 ];

- } xMessage;

-

- xQueueHandle xQueue;

- 

- // Task to create a queue and post a value.

- void vATask( void *pvParameters )

- {

- struct AMessage *pxMessage;

-

-    // Create a queue capable of containing 10 pointers to AMessage structures.

-    // These should be passed by pointer as they contain a lot of data.

-    xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );

-    if( xQueue == 0 )

-    {

-        // Failed to create the queue.

-    }

-

-    // ...

-

-    // Send a pointer to a struct AMessage object.  Don't block if the

-    // queue is already full.

-    pxMessage = & xMessage;

-    xQueueSend( xQueue, ( void * ) &pxMessage, ( portTickType ) 0 );

-

-	// ... Rest of task code.

- }

-

- // Task to receive from the queue.

- void vADifferentTask( void *pvParameters )

- {

- struct AMessage *pxRxedMessage;

-

-    if( xQueue != 0 )

-    {

-        // Receive a message on the created queue.  Block for 10 ticks if a

-        // message is not immediately available.

-        if( xQueueReceive( xQueue, &( pxRxedMessage ), ( portTickType ) 10 ) )

-        {

-            // pcRxedMessage now points to the struct AMessage variable posted

-            // by vATask.

-        }

-    }

-

-	// ... Rest of task code.

- }

- 
- * \defgroup xQueueReceive xQueueReceive - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueReceive( xQueueHandle xQueue, void *pvBuffer, portTickType xTicksToWait ); - -/** - * queue. h - *
unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue );
- * - * Return the number of messages stored in a queue. - * - * @param xQueue A handle to the queue being queried. - * - * @return The number of messages available in the queue. - * - * \page uxQueueMessagesWaiting uxQueueMessagesWaiting - * \ingroup QueueManagement - */ -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle xQueue ); - -/** - * queue. h - *
void vQueueDelete( xQueueHandle xQueue );
- * - * Delete a queue - freeing all the memory allocated for storing of items - * placed on the queue. - * - * @param xQueue A handle to the queue to be deleted. - * - * \page vQueueDelete vQueueDelete - * \ingroup QueueManagement - */ -void vQueueDelete( xQueueHandle xQueue ); - -/** - * queue. h - *

- portBASE_TYPE xQueueSendFromISR( 

-                                    xQueueHandle pxQueue, 

-                                    const void *pvItemToQueue, 

-                                    portBASE_TYPE xTaskPreviouslyWoken 

-                                );

- 
- * - * Post an item on a queue. It is safe to use this function from within an - * interrupt service routine. - * - * Items are queued by copy not reference so it is preferable to only - * queue small items, especially when called from an ISR. In most cases - * it would be preferable to store a pointer to the item being queued. - * - * @param xQueue The handle to the queue on which the item is to be posted. - * - * @param pvItemToQueue A pointer to the item that is to be placed on the - * queue. The size of the items the queue will hold was defined when the - * queue was created, so this many bytes will be copied from pvItemToQueue - * into the queue storage area. - * - * @param cTaskPreviouslyWoken This is included so an ISR can post onto - * the same queue multiple times from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. See the file serial .c in the - * PC port for a good example of this mechanism. - * - * @return pdTRUE if a task was woken by posting onto the queue. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage for buffered IO (where the ISR can obtain more than one value - * per call): -

- void vBufferISR( void )

- {

- portCHAR cIn;

- portBASE_TYPE xTaskWokenByPost;

-

-    // We have not woken a task at the start of the ISR.

-    cTaskWokenByPost = pdFALSE;

-

-    // Loop until the buffer is empty.

-    do

-    {

-        // Obtain a byte from the buffer.

-        cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );						

-

-        // Post the byte.  The first time round the loop cTaskWokenByPost

-        // will be pdFALSE.  If the queue send causes a task to wake we do

-        // not want the task to run until we have finished the ISR, so

-        // xQueueSendFromISR does not cause a context switch.  Also we 

-        // don't want subsequent posts to wake any other tasks, so we store

-        // the return value back into cTaskWokenByPost so xQueueSendFromISR

-        // knows not to wake any task the next iteration of the loop.

-        xTaskWokenByPost = xQueueSendFromISR( xRxQueue, &cIn, cTaskWokenByPost );

-

-    } while( portINPUT_BYTE( BUFFER_COUNT ) );

-

-    // Now the buffer is empty we can switch context if necessary.

-    if( cTaskWokenByPost )

-    {

-        taskYIELD ();

-    }

- }

- 
- * - * \defgroup xQueueSendFromISR xQueueSendFromISR - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ); - -/** - * queue. h - *

- portBASE_TYPE xQueueReceiveFromISR( 

-                                       xQueueHandle pxQueue, 

-                                       void *pvBuffer, 

-                                       portBASE_TYPE *pxTaskWoken 

-                                   ); 

- * 
- * - * Receive an item from a queue. It is safe to use this function from within an - * interrupt service routine. - * - * @param pxQueue The handle to the queue from which the item is to be - * received. - * - * @param pvBuffer Pointer to the buffer into which the received item will - * be copied. - * - * @param pxTaskWoken A task may be blocked waiting for space to become - * available on the queue. If xQueueReceiveFromISR causes such a task to - * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will - * remain unchanged. - * - * @return pdTRUE if an item was successfully received from the queue, - * otherwise pdFALSE. - * - * Example usage: -

- 

- xQueueHandle xQueue;

- 

- // Function to create a queue and post some values.

- void vAFunction( void *pvParameters )

- {

- portCHAR cValueToPost;

- const portTickType xBlockTime = ( portTickType )0xff;

-

-    // Create a queue capable of containing 10 characters.

-    xQueue = xQueueCreate( 10, sizeof( portCHAR ) );

-    if( xQueue == 0 )

-    {

-        // Failed to create the queue.

-    }

-

-    // ...

-

-    // Post some characters that will be used within an ISR.  If the queue

-    // is full then this task will block for xBlockTime ticks.

-    cValueToPost = 'a';

-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );

-    cValueToPost = 'b';

-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );

-

-    // ... keep posting characters ... this task may block when the queue

-    // becomes full.

-

-    cValueToPost = 'c';

-    xQueueSend( xQueue, ( void * ) &cValueToPost, xBlockTime );

- }

-

- // ISR that outputs all the characters received on the queue. 

- void vISR_Routine( void )

- {

- portBASE_TYPE xTaskWokenByReceive = pdFALSE;

- portCHAR cRxedChar;

-

-    while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )

-    {

-        // A character was received.  Output the character now.

-        vOutputCharacter( cRxedChar );

-

-        // If removing the character from the queue woke the task that was 

-        // posting onto the queue cTaskWokenByReceive will have been set to

-        // pdTRUE.  No matter how many times this loop iterates only one

-        // task will be woken.

-    }

-

-    if( cTaskWokenByPost != ( portCHAR ) pdFALSE;

-    {

-        taskYIELD ();

-    }

- }

- 
- * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR - * \ingroup QueueManagement - */ -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - - -/* - * The functions defined above are for passing data to and from tasks. The - * functions below are the equivalents for passing data to and from - * co-rtoutines. - * - * These functions are called from the co-routine macro implementation and - * should not be called directly from application code. Instead use the macro - * wrappers defined within croutine.h. - */ -signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ); -signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); -signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ); -signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/semphr.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/semphr.h deleted file mode 100644 index 050e4d667..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/semphr.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#include "queue.h" - -#ifndef SEMAPHORE_H -#define SEMAPHORE_H - -typedef xQueueHandle xSemaphoreHandle; - -#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( unsigned portCHAR ) 1 ) -#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( unsigned portCHAR ) 0 ) -#define semGIVE_BLOCK_TIME ( ( portTickType ) 0 ) - - -/** - * semphr. h - *
vSemaphoreCreateBinary( xSemaphoreHandle xSemaphore )
- * - * Macro that implements a semaphore by using the existing queue mechanism. - * The queue length is 1 as this is a binary semaphore. The data size is 0 - * as we don't want to actually store any data - we just want to know if the - * queue is empty or full. - * - * @param xSemaphore Handle to the created semaphore. Should be of type xSemaphoreHandle. - * - * Example usage: -

- xSemaphoreHandle xSemaphore;

-

- void vATask( void * pvParameters )

- {

-    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().

-    // This is a macro so pass the variable in directly.

-    vSemaphoreCreateBinary( xSemaphore );

-

-    if( xSemaphore != NULL )

-    {

-        // The semaphore was created successfully.

-        // The semaphore can now be used.  

-    }

- }

- 
- * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary - * \ingroup Semaphores - */ -#define vSemaphoreCreateBinary( xSemaphore ) { \ - xSemaphore = xQueueCreate( ( unsigned portCHAR ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH ); \ - if( xSemaphore != NULL ) \ - { \ - xSemaphoreGive( xSemaphore ); \ - } \ - } - -/** - * semphr. h - * xSemaphoreTake( - * xSemaphoreHandle xSemaphore, - * portTickType xBlockTime - * ) - * - * Macro to obtain a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (). - * - * @param xSemaphore A handle to the semaphore being obtained. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @param xBlockTime The time in ticks to wait for the semaphore to become - * available. The macro portTICK_RATE_MS can be used to convert this to a - * real time. A block time of zero can be used to poll the semaphore. - * - * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime - * expired without the semaphore becoming available. - * - * Example usage: -

- xSemaphoreHandle xSemaphore = NULL;

-

- // A task that creates a semaphore.

- void vATask( void * pvParameters )

- {

-    // Create the semaphore to guard a shared resource.

-    vSemaphoreCreateBinary( xSemaphore );

- }

-

- // A task that uses the semaphore.

- void vAnotherTask( void * pvParameters )

- {

-    // ... Do other things.

-

-    if( xSemaphore != NULL )

-    {

-        // See if we can obtain the semaphore.  If the semaphore is not available

-        // wait 10 ticks to see if it becomes free.	

-        if( xSemaphoreTake( xSemaphore, ( portTickType ) 10 ) == pdTRUE )

-        {

-            // We were able to obtain the semaphore and can now access the

-            // shared resource.

-

-            // ...

-

-            // We have finished accessing the shared resource.  Release the 

-            // semaphore.

-            xSemaphoreGive( xSemaphore );

-        }

-        else

-        {

-            // We could not obtain the semaphore and can therefore not access

-            // the shared resource safely.

-        }

-    }

- }

- 
- * \defgroup xSemaphoreTake xSemaphoreTake - * \ingroup Semaphores - */ -#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueReceive( ( xQueueHandle ) xSemaphore, NULL, xBlockTime ) - -/** - * semphr. h - *
xSemaphoreGive( xSemaphoreHandle xSemaphore )
- * - * Macro to release a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (), and obtained using sSemaphoreTake (). - * - * This must not be used from an ISR. See xSemaphoreGiveFromISR () for - * an alternative which can be used from an ISR. - * - * @param xSemaphore A handle to the semaphore being released. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. - * Semaphores are implemented using queues. An error can occur if there is - * no space on the queue to post a message - indicating that the - * semaphore was not first obtained correctly. - * - * Example usage: -

- xSemaphoreHandle xSemaphore = NULL;

-

- void vATask( void * pvParameters )

- {

-    // Create the semaphore to guard a shared resource.

-    vSemaphoreCreateBinary( xSemaphore );

-

-    if( xSemaphore != NULL )

-    {

-        if( xSemaphoreGive( xSemaphore ) != pdTRUE )

-        {

-            // We would expect this call to fail because we cannot give

-            // a semaphore without first "taking" it!

-        }

-

-        // Obtain the semaphore - don't block if the semaphore is not

-        // immediately available.

-        if( xSemaphoreTake( xSemaphore, ( portTickType ) 0 ) )

-        {

-            // We now have the semaphore and can access the shared resource.

-

-            // ...

-

-            // We have finished accessing the shared resource so can free the

-            // semaphore.

-            if( xSemaphoreGive( xSemaphore ) != pdTRUE )

-            {

-                // We would not expect this call to fail because we must have

-                // obtained the semaphore to get here.

-            }

-        }

-    }

- }

- 
- * \defgroup xSemaphoreGive xSemaphoreGive - * \ingroup Semaphores - */ -#define xSemaphoreGive( xSemaphore ) xQueueSend( ( xQueueHandle ) xSemaphore, NULL, semGIVE_BLOCK_TIME ) - -/** - * semphr. h - *

- xSemaphoreGiveFromISR( 

-                          xSemaphoreHandle xSemaphore, 

-                          portSHORT sTaskPreviouslyWoken 

-                      )
- * - * Macro to release a semaphore. The semaphore must of been created using - * vSemaphoreCreateBinary (), and obtained using xSemaphoreTake (). - * - * This macro can be used from an ISR. - * - * @param xSemaphore A handle to the semaphore being released. This is the - * handle returned by vSemaphoreCreateBinary (); - * - * @param sTaskPreviouslyWoken This is included so an ISR can make multiple calls - * to xSemaphoreGiveFromISR () from a single interrupt. The first call - * should always pass in pdFALSE. Subsequent calls should pass in - * the value returned from the previous call. See the file serial .c in the - * PC port for a good example of using xSemaphoreGiveFromISR (). - * - * @return pdTRUE if a task was woken by releasing the semaphore. This is - * used by the ISR to determine if a context switch may be required following - * the ISR. - * - * Example usage: -

- #define LONG_TIME 0xffff

- #define TICKS_TO_WAIT	10

- xSemaphoreHandle xSemaphore = NULL;

-

- // Repetitive task.

- void vATask( void * pvParameters )

- {

-    for( ;; )

-    {

-        // We want this task to run every 10 ticks or a timer.  The semaphore 

-        // was created before this task was started

-

-        // Block waiting for the semaphore to become available.

-        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )

-        {

-            // It is time to execute.

-

-            // ...

-

-            // We have finished our task.  Return to the top of the loop where

-            // we will block on the semaphore until it is time to execute 

-            // again.

-        }

-    }

- }

-

- // Timer ISR

- void vTimerISR( void * pvParameters )

- {

- static unsigned portCHAR ucLocalTickCount = 0;

-

-    // A timer tick has occurred.

-

-    // ... Do other time functions.

-

-    // Is it time for vATask () to run?

-    ucLocalTickCount++;

-    if( ucLocalTickCount >= TICKS_TO_WAIT )

-    {

-        // Unblock the task by releasing the semaphore.

-        xSemaphoreGive( xSemaphore );

-

-        // Reset the count so we release the semaphore again in 10 ticks time.

-        ucLocalTickCount = 0;

-    }

- }

- 
- * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR - * \ingroup Semaphores - */ -#define xSemaphoreGiveFromISR( xSemaphore, xTaskPreviouslyWoken ) xQueueSendFromISR( ( xQueueHandle ) xSemaphore, NULL, xTaskPreviouslyWoken ) - - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/task.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/task.h deleted file mode 100644 index 62b9a018a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/include/task.h +++ /dev/null @@ -1,951 +0,0 @@ -/* - FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -#ifndef TASK_H -#define TASK_H - -#include "portable.h" -#include "list.h" - -/*----------------------------------------------------------- - * MACROS AND DEFINITIONS - *----------------------------------------------------------*/ - -#define tskKERNEL_VERSION_NUMBER "V4.1.0" - -/** - * task. h - * - * Type by which tasks are referenced. For example, a call to xTaskCreate - * returns (via a pointer parameter) an xTaskHandle variable that can then - * be used as a parameter to vTaskDelete to delete the task. - * - * \page xTaskHandle xTaskHandle - * \ingroup Tasks - */ -typedef void * xTaskHandle; - -/* - * Used internally only. - */ -typedef struct xTIME_OUT -{ - portBASE_TYPE xOverflowCount; - portTickType xTimeOnEntering; -} xTimeOutType; - -/* - * Defines the priority used by the idle task. This must not be modified. - * - * \ingroup TaskUtils - */ -#define tskIDLE_PRIORITY ( ( unsigned portBASE_TYPE ) 0 ) - -/** - * task. h - * - * Macro for forcing a context switch. - * - * \page taskYIELD taskYIELD - * \ingroup SchedulerControl - */ -#define taskYIELD() portYIELD() - -/** - * task. h - * - * Macro to mark the start of a critical code region. Preemptive context - * switches cannot occur when in a critical region. - * - * NOTE: This may alter the stack (depending on the portable implementation) - * so must be used with care! - * - * \page taskENTER_CRITICAL taskENTER_CRITICAL - * \ingroup SchedulerControl - */ -#define taskENTER_CRITICAL() portENTER_CRITICAL() - -/** - * task. h - * - * Macro to mark the end of a critical code region. Preemptive context - * switches cannot occur when in a critical region. - * - * NOTE: This may alter the stack (depending on the portable implementation) - * so must be used with care! - * - * \page taskEXIT_CRITICAL taskEXIT_CRITICAL - * \ingroup SchedulerControl - */ -#define taskEXIT_CRITICAL() portEXIT_CRITICAL() - -/** - * task. h - * - * Macro to disable all maskable interrupts. - * - * \page taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS - * \ingroup SchedulerControl - */ -#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() - -/** - * task. h - * - * Macro to enable microcontroller interrupts. - * - * \page taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS - * \ingroup SchedulerControl - */ -#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() - - -/*----------------------------------------------------------- - * TASK CREATION API - *----------------------------------------------------------*/ - -/** - * task. h - *

- portBASE_TYPE xTaskCreate(

-                              pdTASK_CODE pvTaskCode,

-                              const portCHAR * const pcName,

-                              unsigned portSHORT usStackDepth,

-                              void *pvParameters,

-                              unsigned portBASE_TYPE uxPriority,

-                              xTaskHandle *pvCreatedTask

-                          );
- * - * Create a new task and add it to the list of tasks that are ready to run. - * - * @param pvTaskCode Pointer to the task entry function. Tasks - * must be implemented to never return (i.e. continuous loop). - * - * @param pcName A descriptive name for the task. This is mainly used to - * facilitate debugging. Max length defined by tskMAX_TASK_NAME_LEN - default - * is 16. - * - * @param usStackDepth The size of the task stack specified as the number of - * variables the stack can hold - not the number of bytes. For example, if - * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes - * will be allocated for stack storage. - * - * @param pvParameters Pointer that will be used as the parameter for the task - * being created. - * - * @param uxPriority The priority at which the task should run. - * - * @param pvCreatedTask Used to pass back a handle by which the created task - * can be referenced. - * - * @return pdPASS if the task was successfully created and added to a ready - * list, otherwise an error code defined in the file errors. h - * - * Example usage: -

- // Task to be created.

- void vTaskCode( void * pvParameters )

- {

-     for( ;; )

-     {

-         // Task code goes here.

-     }

- }

-

- // Function that creates a task.

- void vOtherFunction( void )

- {

- unsigned char ucParameterToPass;

- xTaskHandle xHandle;

-		

-     // Create the task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );

-		

-     // Use the handle to delete the task.

-     vTaskDelete( xHandle );

- }

-   
- * \defgroup xTaskCreate xTaskCreate - * \ingroup Tasks - */ -signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pvCreatedTask ); - -/** - * task. h - *
void vTaskDelete( xTaskHandle pxTask );
- * - * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Remove a task from the RTOS real time kernels management. The task being - * deleted will be removed from all ready, blocked, suspended and event lists. - * - * NOTE: The idle task is responsible for freeing the kernel allocated - * memory from tasks that have been deleted. It is therefore important that - * the idle task is not starved of microcontroller processing time if your - * application makes any calls to vTaskDelete (). Memory allocated by the - * task code is not automatically freed, and should be freed before the task - * is deleted. - * - * See the demo application file death.c for sample code that utilises - * vTaskDelete (). - * - * @param pxTask The handle of the task to be deleted. Passing NULL will - * cause the calling task to be deleted. - * - * Example usage: -

- void vOtherFunction( void )

- {

- xTaskHandle xHandle;

-		

-     // Create the task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

-		

-     // Use the handle to delete the task.

-     vTaskDelete( xHandle );

- }

-   
- * \defgroup vTaskDelete vTaskDelete - * \ingroup Tasks - */ -void vTaskDelete( xTaskHandle pxTask ); - - -/*----------------------------------------------------------- - * TASK CONTROL API - *----------------------------------------------------------*/ - -/** - * task. h - *
void vTaskDelay( portTickType xTicksToDelay );
- * - * Delay a task for a given number of ticks. The actual time that the - * task remains blocked depends on the tick rate. The constant - * portTICK_RATE_MS can be used to calculate real time from the tick - * rate - with the resolution of one tick period. - * - * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * @param xTicksToDelay The amount of time, in tick periods, that - * the calling task should block. - * - * Example usage: -

- // Wait 10 ticks before performing an action.

- // NOTE:

- // This is for demonstration only and would be better achieved

- // using vTaskDelayUntil ().

- void vTaskFunction( void * pvParameters )

- {

- portTickType xDelay, xNextTime;

-

-     // Calc the time at which we want to perform the action

-     // next.

-     xNextTime = xTaskGetTickCount () + ( portTickType ) 10;

-

-     for( ;; )

-     {

-         xDelay = xNextTime - xTaskGetTickCount ();

-         xNextTime += ( portTickType ) 10;

-

-         // Guard against overflow

-         if( xDelay <= ( portTickType ) 10 )

-         {

-             vTaskDelay( xDelay );

-         }

-

-         // Perform action here.

-     }

- }

-   
- * \defgroup vTaskDelay vTaskDelay - * \ingroup TaskCtrl - */ -void vTaskDelay( portTickType xTicksToDelay ); - -/** - * task. h - *
void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement );
- * - * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Delay a task until a specified time. This function can be used by cyclical - * tasks to ensure a constant execution frequency. - * - * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will - * cause a task to block for the specified number of ticks from the time vTaskDelay () is - * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed - * execution frequency as the time between a task starting to execute and that task - * calling vTaskDelay () may not be fixed [the task may take a different path though the - * code between calls, or may get interrupted or preempted a different number of times - * each time it executes]. - * - * Whereas vTaskDelay () specifies a wake time relative to the time at which the function - * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to - * unblock. - * - * The constant portTICK_RATE_MS can be used to calculate real time from the tick - * rate - with the resolution of one tick period. - * - * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the - * task was last unblocked. The variable must be initialised with the current time - * prior to its first use (see the example below). Following this the variable is - * automatically updated within vTaskDelayUntil (). - * - * @param xTimeIncrement The cycle time period. The task will be unblocked at - * time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the - * same xTimeIncrement parameter value will cause the task to execute with - * a fixed interface period. - * - * Example usage: -

- // Perform an action every 10 ticks.

- void vTaskFunction( void * pvParameters )

- {

- portTickType xLastWakeTime;

- const portTickType xFrequency = 10;

-

-     // Initialise the xLastWakeTime variable with the current time.

-     xLastWakeTime = xTaskGetTickCount ();

-     for( ;; )

-     {

-         // Wait for the next cycle.

-         vTaskDelayUntil( &xLastWakeTime, xFrequency );

-

-         // Perform action here.

-     }

- }

-   
- * \defgroup vTaskDelayUntil vTaskDelayUntil - * \ingroup TaskCtrl - */ -void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement ); - -/** - * task. h - *
unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask );
- * - * INCLUDE_xTaskPriorityGet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Obtain the priority of any task. - * - * @param pxTask Handle of the task to be queried. Passing a NULL - * handle results in the priority of the calling task being returned. - * - * @return The priority of pxTask. - * - * Example usage: -

- void vAFunction( void )

- {

- xTaskHandle xHandle;

-		

-     // Create a task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

-		

-     // ...

-

-     // Use the handle to obtain the priority of the created task.

-     // It was created with tskIDLE_PRIORITY, but may have changed

-     // it itself.

-     if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )

-     {

-         // The task has changed it's priority.

-     }

-

-     // ...

-

-     // Is our priority higher than the created task?

-     if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )

-     {

-         // Our priority (obtained using NULL handle) is higher.

-     }

- }

-   
- * \defgroup uxTaskPriorityGet uxTaskPriorityGet - * \ingroup TaskCtrl - */ -unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ); - -/** - * task. h - *
void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );
- * - * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Set the priority of any task. - * - * A context switch will occur before the function returns if the priority - * being set is higher than the currently executing task. - * - * @param pxTask Handle to the task for which the priority is being set. - * Passing a NULL handle results in the priority of the calling task being set. - * - * @param uxNewPriority The priority to which the task will be set. - * - * Example usage: -

- void vAFunction( void )

- {

- xTaskHandle xHandle;

-		

-     // Create a task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

-

-     // ...

-

-     // Use the handle to raise the priority of the created task.

-     vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );

-

-     // ...

-

-     // Use a NULL handle to raise our priority to the same value.

-     vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );

- }

-   
- * \defgroup vTaskPrioritySet vTaskPrioritySet - * \ingroup TaskCtrl - */ -void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ); - -/** - * task. h - *
void vTaskSuspend( xTaskHandle pxTaskToSuspend );
- * - * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Suspend any task. When suspended a task will never get any microcontroller - * processing time, no matter what its priority. - * - * Calls to vTaskSuspend are not accumulative - - * i.e. calling vTaskSuspend () twice on the same task still only requires one - * call to vTaskResume () to ready the suspended task. - * - * @param pxTaskToSuspend Handle to the task being suspended. Passing a NULL - * handle will cause the calling task to be suspended. - * - * Example usage: -

- void vAFunction( void )

- {

- xTaskHandle xHandle;

-		

-     // Create a task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

-		

-     // ...

-

-     // Use the handle to suspend the created task.

-     vTaskSuspend( xHandle );

-

-     // ...

-		

-     // The created task will not run during this period, unless

-     // another task calls vTaskResume( xHandle ).

-		

-     //...

-		

-

-     // Suspend ourselves.

-     vTaskSuspend( NULL );

-

-     // We cannot get here unless another task calls vTaskResume

-     // with our handle as the parameter.

- }

-   
- * \defgroup vTaskSuspend vTaskSuspend - * \ingroup TaskCtrl - */ -void vTaskSuspend( xTaskHandle pxTaskToSuspend ); - -/** - * task. h - *
void vTaskResume( xTaskHandle pxTaskToResume );
- * - * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * Resumes a suspended task. - * - * A task that has been suspended by one of more calls to vTaskSuspend () - * will be made available for running again by a single call to - * vTaskResume (). - * - * @param pxTaskToResume Handle to the task being readied. - * - * Example usage: -

- void vAFunction( void )

- {

- xTaskHandle xHandle;

-		

-     // Create a task, storing the handle.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );

-		

-     // ...

-

-     // Use the handle to suspend the created task.

-     vTaskSuspend( xHandle );

-

-     // ...

-	

-     // The created task will not run during this period, unless

-     // another task calls vTaskResume( xHandle ).

-		

-     //...

-		

-

-     // Resume the suspended task ourselves.

-     vTaskResume( xHandle );

-

-     // The created task will once again get microcontroller processing

-     // time in accordance with it priority within the system.

- }

-   
- * \defgroup vTaskResume vTaskResume - * \ingroup TaskCtrl - */ -void vTaskResume( xTaskHandle pxTaskToResume ); - -/** - * task. h - *
void xTaskResumeFromISR( xTaskHandle pxTaskToResume );
- * - * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be - * available. See the configuration section for more information. - * - * An implementation of vTaskResume() that can be called from within an ISR. - * - * A task that has been suspended by one of more calls to vTaskSuspend () - * will be made available for running again by a single call to - * xTaskResumeFromISR (). - * - * @param pxTaskToResume Handle to the task being readied. - * - * \defgroup vTaskResumeFromISR vTaskResumeFromISR - * \ingroup TaskCtrl - */ -portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ); - -/*----------------------------------------------------------- - * SCHEDULER CONTROL - *----------------------------------------------------------*/ - -/** - * task. h - *
void vTaskStartScheduler( void );
- * - * Starts the real time kernel tick processing. After calling the kernel - * has control over which tasks are executed and when. This function - * does not return until an executing task calls vTaskEndScheduler (). - * - * At least one task should be created via a call to xTaskCreate () - * before calling vTaskStartScheduler (). The idle task is created - * automatically when the first application task is created. - * - * See the demo application file main.c for an example of creating - * tasks and starting the kernel. - * - * Example usage: -

- void vAFunction( void )

- {

-     // Create at least one task before starting the kernel.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );

-

-     // Start the real time kernel with preemption.

-     vTaskStartScheduler ();

-

-     // Will not get here unless a task calls vTaskEndScheduler ()

- }

-   
- * - * \defgroup vTaskStartScheduler vTaskStartScheduler - * \ingroup SchedulerControl - */ -void vTaskStartScheduler( void ); - -/** - * task. h - *
void vTaskEndScheduler( void );
- * - * Stops the real time kernel tick. All created tasks will be automatically - * deleted and multitasking (either preemptive or cooperative) will - * stop. Execution then resumes from the point where vTaskStartScheduler () - * was called, as if vTaskStartScheduler () had just returned. - * - * See the demo application file main. c in the demo/PC directory for an - * example that uses vTaskEndScheduler (). - * - * vTaskEndScheduler () requires an exit function to be defined within the - * portable layer (see vPortEndScheduler () in port. c for the PC port). This - * performs hardware specific operations such as stopping the kernel tick. - * - * vTaskEndScheduler () will cause all of the resources allocated by the - * kernel to be freed - but will not free resources allocated by application - * tasks. - * - * Example usage: -

- void vTaskCode( void * pvParameters )

- {

-     for( ;; )

-     {

-         // Task code goes here.

-

-         // At some point we want to end the real time kernel processing

-         // so call ...

-         vTaskEndScheduler ();

-     }

- }

-

- void vAFunction( void )

- {

-     // Create at least one task before starting the kernel.

-     xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );

-

-     // Start the real time kernel with preemption.

-     vTaskStartScheduler ();

-

-     // Will only get here when the vTaskCode () task has called

-     // vTaskEndScheduler ().  When we get here we are back to single task

-     // execution.

- }

-   
- * - * \defgroup vTaskEndScheduler vTaskEndScheduler - * \ingroup SchedulerControl - */ -void vTaskEndScheduler( void ); - -/** - * task. h - *
void vTaskSuspendAll( void );
- * - * Suspends all real time kernel activity while keeping interrupts (including the - * kernel tick) enabled. - * - * After calling vTaskSuspendAll () the calling task will continue to execute - * without risk of being swapped out until a call to xTaskResumeAll () has been - * made. - * - * Example usage: -

- void vTask1( void * pvParameters )

- {

-     for( ;; )

-     {

-         // Task code goes here.

-

-         // ...

-

-         // At some point the task wants to perform a long operation during

-         // which it does not want to get swapped out.  It cannot use

-         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the

-         // operation may cause interrupts to be missed - including the

-         // ticks.

-

-         // Prevent the real time kernel swapping out the task.

-         vTaskSuspendAll ();

-

-         // Perform the operation here.  There is no need to use critical

-         // sections as we have all the microcontroller processing time.

-         // During this time interrupts will still operate and the kernel

-         // tick count will be maintained.

-

-         // ...

-

-         // The operation is complete.  Restart the kernel.

-         xTaskResumeAll ();

-     }

- }

-   
- * \defgroup vTaskSuspendAll vTaskSuspendAll - * \ingroup SchedulerControl - */ -void vTaskSuspendAll( void ); - -/** - * task. h - *
portCHAR xTaskResumeAll( void );
- * - * Resumes real time kernel activity following a call to vTaskSuspendAll (). - * After a call to vTaskSuspendAll () the kernel will take control of which - * task is executing at any time. - * - * @return If resuming the scheduler caused a context switch then pdTRUE is - * returned, otherwise pdFALSE is returned. - * - * Example usage: -

- void vTask1( void * pvParameters )

- {

-     for( ;; )

-     {

-         // Task code goes here.

-

-         // ...

-

-         // At some point the task wants to perform a long operation during

-         // which it does not want to get swapped out.  It cannot use

-         // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the

-         // operation may cause interrupts to be missed - including the

-         // ticks.

-

-         // Prevent the real time kernel swapping out the task.

-         vTaskSuspendAll ();

-

-         // Perform the operation here.  There is no need to use critical

-         // sections as we have all the microcontroller processing time.

-         // During this time interrupts will still operate and the real

-         // time kernel tick count will be maintained.

-

-         // ...

-

-         // The operation is complete.  Restart the kernel.  We want to force

-         // a context switch - but there is no point if resuming the scheduler

-         // caused a context switch already.

-         if( !xTaskResumeAll () )

-         {

-              taskYIELD ();

-         }

-     }

- }

-   
- * \defgroup xTaskResumeAll xTaskResumeAll - * \ingroup SchedulerControl - */ -signed portBASE_TYPE xTaskResumeAll( void ); - - -/*----------------------------------------------------------- - * TASK UTILITIES - *----------------------------------------------------------*/ - -/** - * task. h - *
volatile portTickType xTaskGetTickCount( void );
- * - * @return The count of ticks since vTaskStartScheduler was called. - * - * \page xTaskGetTickCount xTaskGetTickCount - * \ingroup TaskUtils - */ -portTickType xTaskGetTickCount( void ); - -/** - * task. h - *
unsigned portSHORT uxTaskGetNumberOfTasks( void );
- * - * @return The number of tasks that the real time kernel is currently managing. - * This includes all ready, blocked and suspended tasks. A task that - * has been deleted but not yet freed by the idle task will also be - * included in the count. - * - * \page uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks - * \ingroup TaskUtils - */ -unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ); - -/** - * task. h - *
void vTaskList( portCHAR *pcWriteBuffer );
- * - * configUSE_TRACE_FACILITY, INCLUDE_vTaskDelete and INCLUDE_vTaskSuspend - * must all be defined as 1 for this function to be available. - * See the configuration section for more information. - * - * NOTE: This function will disable interrupts for its duration. It is - * not intended for normal application runtime use but as a debug aid. - * - * Lists all the current tasks, along with their current state and stack - * usage high water mark. - * - * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or - * suspended ('S'). - * - * @param pcWriteBuffer A buffer into which the above mentioned details - * will be written, in ascii form. This buffer is assumed to be large - * enough to contain the generated report. Approximately 40 bytes per - * task should be sufficient. - * - * \page vTaskList vTaskList - * \ingroup TaskUtils - */ -void vTaskList( signed portCHAR *pcWriteBuffer ); - -/** - * task. h - *
void vTaskStartTrace( portCHAR * pcBuffer, unsigned portBASE_TYPE uxBufferSize );
- * - * Starts a real time kernel activity trace. The trace logs the identity of - * which task is running when. - * - * The trace file is stored in binary format. A separate DOS utility called - * convtrce.exe is used to convert this into a tab delimited text file which - * can be viewed and plotted in a spread sheet. - * - * @param pcBuffer The buffer into which the trace will be written. - * - * @param ulBufferSize The size of pcBuffer in bytes. The trace will continue - * until either the buffer in full, or ulTaskEndTrace () is called. - * - * \page vTaskStartTrace vTaskStartTrace - * \ingroup TaskUtils - */ -void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ); - -/** - * task. h - *
unsigned portLONG ulTaskEndTrace( void );
- * - * Stops a kernel activity trace. See vTaskStartTrace (). - * - * @return The number of bytes that have been written into the trace buffer. - * - * \page usTaskEndTrace usTaskEndTrace - * \ingroup TaskUtils - */ -unsigned portLONG ulTaskEndTrace( void ); - - -/*----------------------------------------------------------- - * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES - *----------------------------------------------------------*/ - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY - * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS - * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * Called from the real time kernel tick (either preemptive or cooperative), - * this increments the tick count and checks if any tasks that are blocked - * for a finite period required removing from a blocked list and placing on - * a ready list. - */ -inline void vTaskIncrementTick( void ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. - * - * Removes the calling task from the ready list and places it both - * on the list of tasks waiting for a particular event, and the - * list of delayed tasks. The task will be removed from both lists - * and replaced on the ready list should either the event occur (and - * there be no higher priority tasks waiting on the same event) or - * the delay period expires. - * - * @param pxEventList The list containing tasks that are blocked waiting - * for the event to occur. - * - * @param xTicksToWait The maximum amount of time that the task should wait - * for the event to occur. This is specified in kernel ticks,the constant - * portTICK_RATE_MS can be used to convert kernel ticks into a real time - * period. - */ -void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. - * - * Removes a task from both the specified event list and the list of blocked - * tasks, and places it on a ready queue. - * - * xTaskRemoveFromEventList () will be called if either an event occurs to - * unblock a task, or the block timeout period expires. - * - * @return pdTRUE if the task being removed has a higher priority than the task - * making the call, otherwise pdFALSE. - */ -signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN - * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * INCLUDE_vTaskCleanUpResources and INCLUDE_vTaskSuspend must be defined as 1 - * for this function to be available. - * See the configuration section for more information. - * - * Empties the ready and delayed queues of task control blocks, freeing the - * memory allocated for the task control block and task stacks as it goes. - */ -void vTaskCleanUpResources( void ); - -/* - * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY - * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS - * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. - * - * Sets the pointer to the current TCB to the TCB of the highest priority task - * that is ready to run. - */ -inline void vTaskSwitchContext( void ); - -/* - * Return the handle of the calling task. - */ -xTaskHandle xTaskGetCurrentTaskHandle( void ); - -/* - * Capture the current time status for future reference. - */ -void vTaskSetTimeOutState( xTimeOutType *pxTimeOut ); - -/* - * Compare the time status now with that previously captured to see if the - * timeout has expired. - */ -portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType *pxTimeOut, portTickType *pxTicksToWait ); - -/* - * Shortcut used by the queue implementation to prevent unnecessary call to - * taskYIELD(); - */ -void vTaskMissedYield( void ); - -#endif /* TASK_H */ - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/list.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/list.c deleted file mode 100644 index 297297071..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/list.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.2.0 - - + Removed the volatile modifier from the function parameters. This was - only ever included to prevent compiler warnings. Now warnings are - removed by casting parameters where the calls are made. - - + prvListGetOwnerOfNextEntry() and prvListGetOwnerOfHeadEntry() have been - removed from the c file and added as macros to the h file. - - + uxNumberOfItems has been added to the list structure. This removes the - need for a pointer comparison when checking if a list is empty, and so - is slightly faster. - - + Removed the NULL check in vListRemove(). This makes the call faster but - necessitates any application code utilising the list implementation to - ensure NULL pointers are not passed. - -Changes from V2.0.0 - - + Double linked the lists to allow faster removal item removal. - -Changes from V2.6.1 - - + Make use of the new portBASE_TYPE definition where ever appropriate. - -Changes from V3.0.0 - - + API changes as described on the FreeRTOS.org WEB site. - -Changes from V3.2.4 - - + Removed the pxHead member of the xList structure. This always pointed - to the same place so has been removed to free a few bytes of RAM. - - + Introduced the xMiniListItem structure that does not include the - xListItem members that are not required by the xListEnd member of a list. - Again this was done to reduce RAM usage. - - + Changed the volatile definitions of some structure members to clean up - the code where the list structures are used. - -Changes from V4.0.4 - - + Optimised vListInsert() in the case when the wake time is the maximum - tick count value. -*/ - -#include -#include "FreeRTOS.h" -#include "list.h" - -/*----------------------------------------------------------- - * PUBLIC LIST API documented in list.h - *----------------------------------------------------------*/ - -void vListInitialise( xList *pxList ) -{ - /* The list structure contains a list item which is used to mark the - end of the list. To initialise the list the list end is inserted - as the only list entry. */ - pxList->pxIndex = ( xListItem * ) &( pxList->xListEnd ); - - /* The list end value is the highest possible value in the list to - ensure it remains at the end of the list. */ - pxList->xListEnd.xItemValue = portMAX_DELAY; - - /* The list end next and previous pointers point to itself so we know - when the list is empty. */ - pxList->xListEnd.pxNext = ( xListItem * ) &( pxList->xListEnd ); - pxList->xListEnd.pxPrevious = ( xListItem * ) &( pxList->xListEnd ); - - pxList->uxNumberOfItems = 0; -} -/*-----------------------------------------------------------*/ - -void vListInitialiseItem( xListItem *pxItem ) -{ - /* Make sure the list item is not recorded as being on a list. */ - pxItem->pvContainer = NULL; -} -/*-----------------------------------------------------------*/ - -void vListInsertEnd( xList *pxList, xListItem *pxNewListItem ) -{ -volatile xListItem * pxIndex; - - /* Insert a new list item into pxList, but rather than sort the list, - makes the new list item the last item to be removed by a call to - pvListGetOwnerOfNextEntry. This means it has to be the item pointed to by - the pxIndex member. */ - pxIndex = pxList->pxIndex; - - pxNewListItem->pxNext = pxIndex->pxNext; - pxNewListItem->pxPrevious = pxList->pxIndex; - pxIndex->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; - pxIndex->pxNext = ( volatile xListItem * ) pxNewListItem; - pxList->pxIndex = ( volatile xListItem * ) pxNewListItem; - - /* Remember which list the item is in. */ - pxNewListItem->pvContainer = ( void * ) pxList; - - ( pxList->uxNumberOfItems )++; -} -/*-----------------------------------------------------------*/ - -void vListInsert( xList *pxList, xListItem *pxNewListItem ) -{ -volatile xListItem *pxIterator; -portTickType xValueOfInsertion; - - /* Insert the new list item into the list, sorted in ulListItem order. */ - xValueOfInsertion = pxNewListItem->xItemValue; - - /* If the list already contains a list item with the same item value then - the new list item should be placed after it. This ensures that TCB's which - are stored in ready lists (all of which have the same ulListItem value) - get an equal share of the CPU. However, if the xItemValue is the same as - the back marker the iteration loop below will not end. This means we need - to guard against this by checking the value first and modifying the - algorithm slightly if necessary. */ - if( xValueOfInsertion == portMAX_DELAY ) - { - pxIterator = pxList->xListEnd.pxPrevious; - } - else - { - for( pxIterator = ( xListItem * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) - { - /* There is nothing to do here, we are just iterating to the - wanted insertion position. */ - } - } - - pxNewListItem->pxNext = pxIterator->pxNext; - pxNewListItem->pxNext->pxPrevious = ( volatile xListItem * ) pxNewListItem; - pxNewListItem->pxPrevious = pxIterator; - pxIterator->pxNext = ( volatile xListItem * ) pxNewListItem; - - /* Remember which list the item is in. This allows fast removal of the - item later. */ - pxNewListItem->pvContainer = ( void * ) pxList; - - ( pxList->uxNumberOfItems )++; -} -/*-----------------------------------------------------------*/ - -void vListRemove( xListItem *pxItemToRemove ) -{ -xList * pxList; - - pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; - pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; - - /* The list item knows which list it is in. Obtain the list from the list - item. */ - pxList = ( xList * ) pxItemToRemove->pvContainer; - - /* Make sure the index is left pointing to a valid item. */ - if( pxList->pxIndex == pxItemToRemove ) - { - pxList->pxIndex = pxItemToRemove->pxPrevious; - } - - pxItemToRemove->pvContainer = NULL; - ( pxList->uxNumberOfItems )--; -} -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/GCC/ARM7_STR71X/port.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/GCC/ARM7_STR71X/port.c deleted file mode 100644 index e131ccbd2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/GCC/ARM7_STR71X/port.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - FreeRTOS V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - Modification for STR71X/GCC - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* ----------------------- System incldues ----------------------------------*/ -#include - -/* ----------------------- FreeRTOS -----------------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" - -/* ----------------------- STR71X includes ----------------------------------*/ -#include "eic.h" -#include "wdg.h" - -/* ----------------------- Defines ------------------------------------------*/ - -/* System mode, ARM mode, interrupts enabled. */ -#define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1F ) -#define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 ) -#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 ) -#define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 ) - -/* ----------------------- Static functions ---------------------------------*/ - -/* Setup the timer to generate the tick interrupts. */ -static void prvSetupTimerInterrupt( void ); - -/* Scheduler can only be started from ARM mode, so vPortISRStartFirstSTask() - * is defined in portISR.c. - */ -extern void vPortISRStartFirstTask( void ); - -/* ----------------------- Start implementation -----------------------------*/ - -/* - * Initialise the stack of a task to look exactly as if a call to - * portSAVE_CONTEXT had been called. - */ -portSTACK_TYPE * -pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters ) -{ - portSTACK_TYPE *pxOriginalTOS; - - pxOriginalTOS = pxTopOfStack; - - /* Setup the initial stack of the task. The stack is set exactly as - expected by the portRESTORE_CONTEXT() macro. */ - - /* First on the stack is the return address - which in this case is the - start of the task. The offset is added to make the return address appear - as it would within an IRQ ISR. */ - *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; - pxTopOfStack--; - - *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */ - pxTopOfStack--; - *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */ - pxTopOfStack--; - - /* When the task starts is will expect to find the function parameter in - R0. */ - *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */ - pxTopOfStack--; - - /* The last thing onto the stack is the status register, which is set for - system mode, with interrupts enabled. */ - *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR; - -#ifdef THUMB_INTERWORK - { - /* We want the task to start in thumb mode. */ - *pxTopOfStack |= portTHUMB_MODE_BIT; - } -#endif - - pxTopOfStack--; - - /* Some optimisation levels use the stack differently to others. This - means the interrupt flags cannot always be stored on the stack and will - instead be stored in a variable, which is then saved as part of the - tasks context. */ - *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING; - - return pxTopOfStack; -} - -portBASE_TYPE -xPortStartScheduler( void ) -{ - /* Start the timer that generates the tick ISR. Interrupts are disabled - here already. */ - prvSetupTimerInterrupt( ); - - /* Start the first task. */ - vPortISRStartFirstTask( ); - - /* Should not get here! */ - return 0; -} - -void -vPortEndScheduler( void ) -{ - /* It is unlikely that the ARM port will require this function as there - is nothing to return to. */ -} - -/* We use the interal watchdog timer to generate a periodic clock tick. */ -static void -prvSetupTimerInterrupt( void ) -{ - /* Set the watchdog up to generate a periodic tick. */ - WDG_ECITConfig( DISABLE ); - WDG_CntOnOffConfig( DISABLE ); - WDG_PeriodValueConfig( configTICK_RATE_HZ ); - - /* Setup the tick interrupt in the EIC. */ - EIC_IRQChannelPriorityConfig( WDG_IRQChannel, 1 ); - EIC_IRQChannelConfig( WDG_IRQChannel, ENABLE ); - EIC_IRQConfig( ENABLE ); - WDG_ECITConfig( ENABLE ); - - /* Start the timer - interrupts are actually disabled at this point so - it is safe to do this here. */ - WDG_CntOnOffConfig( ENABLE ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/GCC/ARM7_STR71X/portISR.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/GCC/ARM7_STR71X/portISR.c deleted file mode 100644 index 7888d6e07..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/GCC/ARM7_STR71X/portISR.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - FreeRTOS V4.1.0 - Copyright (C) 2003-2005 Richard Barry. - Modification for STR71X/GCC - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* ----------------------- System incldues ----------------------------------*/ - -/* ----------------------- FreeRTOS -----------------------------------------*/ -#include "FreeRTOS.h" -#include "task.h" - -/* ----------------------- STR71X includes ----------------------------------*/ -#include "eic.h" -#include "wdg.h" - -/* ----------------------- Defines ------------------------------------------*/ - -#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 ) - -/* ----------------------- Variables ----------------------------------------*/ -volatile unsigned portLONG ulCriticalNesting = 9999UL; - -/* ----------------------- Prototypes ---------------------------------------*/ - -/* ISR to handle manual context switches (from a call to taskYIELD()). */ -void vPortYieldProcessor( void ) __attribute__ ( ( interrupt( "SWI" ), naked ) ); -void vPortISRStartFirstTask( void ); -void vPortPreemptiveTick( void ) __attribute__ ( ( naked ) ); -void vPortNonPreemptiveTick( void ) __attribute__ ( ( interrupt( "IRQ" ) ) ); - -/* ----------------------- Start implementation -----------------------------*/ - -/* The scheduler can only be started from ARM mode, hence the inclusion of this - * function here. - */ -void -vPortISRStartFirstTask( void ) -{ - /* Simply start the scheduler. This is included here as it can only be - called from ARM mode. */ - portRESTORE_CONTEXT( ); -} - -/* - * Called by portYIELD() or taskYIELD() to manually force a context switch. - * - * When a context switch is performed from the task level the saved task - * context is made to look as if it occurred from within the tick ISR. This - * way the same restore context function can be used when restoring the context - * saved from the ISR or that saved from a call to vPortYieldProcessor. - */ -void -vPortYieldProcessor( void ) -{ - /* Within an IRQ ISR the link register has an offset from the true return - address, but an SWI ISR does not. Add the offset manually so the same - ISR return code can be used in both cases. */ - asm volatile ( "ADD LR, LR, #4" ); - - /* Perform the context switch. First save the context of the current task. */ - portSAVE_CONTEXT( ); - - /* Find the highest priority task that is ready to run. */ - vTaskSwitchContext( ); - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT( ); -} - -/* - * The ISR used for the scheduler tick depends on whether the cooperative or - * the preemptive scheduler is being used. - */ -#if configUSE_PREEMPTION == 0 - -/* The cooperative scheduler requires a normal IRQ service routine to - * simply increment the system tick. - */ -void -vPortNonPreemptiveTick( void ) -{ - vTaskIncrementTick( ); - - /* Clear the interrupt in the watchdog and EIC. */ - WDG->SR = 0x0000; - /* clear current interrupt pending flag for interupt source. */ - EIC->IPR |= 1 << EIC_CurrentIRQChannelValue( ); -} - -#else - -/* The preemptive scheduler is defined as "naked" as the full context is - * saved on entry as part of the context switch. - */ -void -vPortPreemptiveTick( void ) -{ - /* Save the context of the interrupted task. */ - portSAVE_CONTEXT( ); - - /* Increment the RTOS tick count, then look for the highest priority - * task that is ready to run. - */ - vTaskIncrementTick( ); - vTaskSwitchContext( ); - - /* Clear the interrupt in the watchdog and EIC. */ - WDG->SR = 0x0000; - /* clear current interrupt pending flag for interupt source. */ - EIC->IPR |= 1 << EIC_CurrentIRQChannelValue( ); - - /* Restore the context of the new task. */ - portRESTORE_CONTEXT( ); -} - -#endif - -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions here to - * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then - * the utilities are defined as macros in portmacro.h - as per other ports. - */ -#ifdef THUMB_INTERWORK - -void vPortDisableInterruptsFromThumb( void ) __attribute__ ( ( naked ) ); -void vPortEnableInterruptsFromThumb( void ) __attribute__ ( ( naked ) ); - -void -vPortDisableInterruptsFromThumb( void ) -{ - asm volatile ( "STMDB SP!, {R0}" ); /* Push R0. */ - asm volatile ( "MRS R0, CPSR" ); /* Get CPSR. */ - asm volatile ( "ORR R0, R0, #0xC0" ); /* Disable IRQ, FIQ. */ - asm volatile ( "MSR CPSR, R0" ); /* Write back modified value. */ - asm volatile ( "LDMIA SP!, {R0}" ); /* Pop R0. */ - asm volatile ( "BX R14" ); /* Return back to thumb. */ -} - -void -vPortEnableInterruptsFromThumb( void ) -{ - asm volatile ( "STMDB SP!, {R0}" ); /* Push R0. */ - asm volatile ( "MRS R0, CPSR" ); /* Get CPSR. */ - asm volatile ( "BIC R0, R0, #0xC0" ); /* Enable IRQ, FIQ. */ - asm volatile ( "MSR CPSR, R0" ); /* Write back modified value. */ - asm volatile ( "LDMIA SP!, {R0}" ); /* Pop R0. */ - asm volatile ( "BX R14" ); /* Return back to thumb. */ -} - -#endif - -/* The code generated by the GCC compiler uses the stack in different ways at -different optimisation levels. The interrupt flags can therefore not always -be saved to the stack. Instead the critical section nesting level is stored -in a variable, which is then saved as part of the stack context. */ -void -vPortEnterCritical( void ) -{ - /* Disable interrupts as per portDISABLE_INTERRUPTS(); */ - asm volatile ( "STMDB SP!, {R0}" ); /* Push R0. */ - asm volatile ( "MRS R0, CPSR" ); /* Get CPSR. */ - asm volatile ( "ORR R0, R0, #0xC0" ); /* Disable IRQ, FIQ. */ - asm volatile ( "MSR CPSR, R0" ); /* Write back modified value. */ - asm volatile ( "LDMIA SP!, {R0}" ); /* Pop R0. */ - - /* Now interrupts are disabled ulCriticalNesting can be accessed - directly. Increment ulCriticalNesting to keep a count of how many times - portENTER_CRITICAL() has been called. */ - ulCriticalNesting++; -} - -void -vPortExitCritical( void ) -{ - if( ulCriticalNesting > portNO_CRITICAL_NESTING ) - { - /* Decrement the nesting count as we are leaving a critical section. */ - ulCriticalNesting--; - - /* If the nesting level has reached zero then interrupts should be - re-enabled. */ - if( ulCriticalNesting == portNO_CRITICAL_NESTING ) - { - /* Enable interrupts as per portEXIT_CRITICAL(). */ - asm volatile ( "STMDB SP!, {R0}" ); /* Push R0. */ - asm volatile ( "MRS R0, CPSR" ); /* Get CPSR. */ - asm volatile ( "BIC R0, R0, #0xC0" ); /* Enable IRQ, FIQ. */ - asm volatile ( "MSR CPSR, R0" ); /* Write back modified value. */ - asm volatile ( "LDMIA SP!, {R0}" ); /* Pop R0. */ - } - } -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/GCC/ARM7_STR71X/portmacro.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/GCC/ARM7_STR71X/portmacro.h deleted file mode 100644 index 466321529..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/GCC/ARM7_STR71X/portmacro.h +++ /dev/null @@ -1,243 +0,0 @@ -/* - FreeRTOS V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - Modification for STR71X/GCC - Copyright (C) 2006 Christian Walter. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - Changes from V3.2.3 - - + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1. -*/ - -#ifndef PORTMACRO_H -#define PORTMACRO_H - -/*----------------------------------------------------------- - * Port specific definitions. - * - * The settings in this file configure FreeRTOS correctly for the - * given hardware and compiler. - * - * These settings should not be altered. - *----------------------------------------------------------- - */ - -/* Type definitions. */ -#define portCHAR char -#define portFLOAT float -#define portDOUBLE double -#define portLONG long -#define portSHORT short -#define portSTACK_TYPE unsigned portLONG -#define portBASE_TYPE portLONG - -#if( configUSE_16_BIT_TICKS == 1 ) -typedef unsigned portSHORT portTickType; - -#define portMAX_DELAY ( portTickType ) 0xffff -#else -typedef unsigned portLONG portTickType; - -#define portMAX_DELAY ( portTickType ) 0xffffffff -#endif -/*-----------------------------------------------------------*/ - -/* Architecture specifics. */ -#define portSTACK_GROWTH ( -1 ) -#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ ) -#define portBYTE_ALIGNMENT 4 -/*-----------------------------------------------------------*/ - - -/* Scheduler utilities. */ - -/* - * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR - * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but - * are included here for efficiency. An attempt to call one from - * THUMB mode code will result in a compile time error. - */ - -#define portRESTORE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile unsigned portLONG ulCriticalNesting; \ - \ - /* Set the LR to the task stack. */ \ - asm volatile ( "LDR R0, %0" : : "m" (pxCurrentTCB) ); \ - asm volatile ( "LDR LR, [R0]" ); \ - \ - /* The critical nesting depth is the first item on the stack. */ \ - /* Load it into the ulCriticalNesting variable. */ \ - asm volatile ( "LDR R0, =ulCriticalNesting" ); \ - asm volatile ( "LDMFD LR!, {R1}" ); \ - asm volatile ( "STR R1, [R0]" ); \ - \ - /* Get the SPSR from the stack. */ \ - asm volatile ( "LDMFD LR!, {R0}" ); \ - asm volatile ( "MSR SPSR, R0" ); \ - \ - /* Restore all system mode registers for the task. */ \ - asm volatile ( "LDMFD LR, {R0-R14}^" ); \ - asm volatile ( "NOP" ); \ - \ - /* Restore the return address. */ \ - asm volatile ( "LDR LR, [LR, #+60]" ); \ - \ - /* And return - correcting the offset in the LR to obtain the */ \ - /* correct address. */ \ - asm volatile ( "SUBS PC, LR, #4" ); \ - ( void ) ulCriticalNesting; \ -} -/*-----------------------------------------------------------*/ - -#define portSAVE_CONTEXT() \ -{ \ -extern volatile void * volatile pxCurrentTCB; \ -extern volatile unsigned portLONG ulCriticalNesting; \ - \ - /* Push R0 as we are going to use the register. */ \ - asm volatile ( "STMDB SP!, {R0}" ); \ - \ - /* Set R0 to point to the task stack pointer. */ \ - asm volatile ( "STMDB SP,{SP}^" ); \ - asm volatile ( "SUB SP, SP, #4" ); \ - asm volatile ( "LDMIA SP!,{R0}" ); \ - \ - /* Push the return address onto the stack. */ \ - asm volatile ( "STMDB R0!, {LR}" ); \ - \ - /* Now we have saved LR we can use it instead of R0. */ \ - asm volatile ( "MOV LR, R0" ); \ - \ - /* Pop R0 so we can save it onto the system mode stack. */ \ - asm volatile ( "LDMIA SP!, {R0}" ); \ - \ - /* Push all the system mode registers onto the task stack. */ \ - asm volatile ( "STMDB LR,{R0-LR}^"); \ - asm volatile ( "SUB LR, LR, #60" ); \ - \ - /* Push the SPSR onto the task stack. */ \ - asm volatile ( "MRS R0, SPSR" ); \ - asm volatile ( "STMDB LR!, {R0}" ); \ - \ - asm volatile ( "LDR R0, =ulCriticalNesting " ); \ - asm volatile ( "LDR R0, [R0]" ); \ - asm volatile ( "STMDB LR!, {R0}" ); \ - \ - /* Store the new top of stack for the task. */ \ - asm volatile ( "LDR R0, %0" : : "m" (pxCurrentTCB) ); \ - asm volatile ( "STR LR, [R0]" ); \ - ( void ) ulCriticalNesting; \ -} - - -/*----------------------------------------------------------- - * ISR entry and exit macros. These are only required if a task switch - * is required from the ISR. - *----------------------------------------------------------*/ - - -#define portENTER_SWITCHING_ISR() \ - /* Save the context of the interrupted task. */ \ - portSAVE_CONTEXT(); \ - \ - /* We don't know the stack requirements for the ISR, so the frame */\ - /* pointer will be set to the top of the task stack, and the stack*/\ - /* pointer left where it is. The IRQ stack will get used for any */\ - /* functions calls made by this ISR. */ \ - asm volatile ( "SUB R11, LR, #4" ); \ - { - -#define portEXIT_SWITCHING_ISR( SwitchRequired ) \ - /* If a switch is required then we just need to call */ \ - /* vTaskSwitchContext() as the context has already been */ \ - /* saved. */ \ - if( SwitchRequired ) \ - { \ - vTaskSwitchContext(); \ - } \ - } \ - /* Restore the context of which ever task is now the highest */ \ - /* priority that is ready to run. */ \ - portRESTORE_CONTEXT(); - -#define portYIELD() asm volatile ( "SWI" ); -/*-----------------------------------------------------------*/ - - -/* Critical section management. */ - -/* - * The interrupt management utilities can only be called from ARM mode. When - * THUMB_INTERWORK is defined the utilities are defined as functions in - * portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not - * defined then the utilities are defined as macros here - as per other ports. - */ - -#ifdef THUMB_INTERWORK - -extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ( ( naked ) ); -extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ( ( naked ) ); - -#define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb() -#define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb() - -#else - -#define portDISABLE_INTERRUPTS() \ - asm volatile ( "STMDB SP!, {R0}" ); /* Push R0. */ \ - asm volatile ( "MRS R0, CPSR" ); /* Get CPSR. */ \ - asm volatile ( "ORR R0, R0, #0xC0" ); /* Disable IRQ, FIQ. */ \ - asm volatile ( "MSR CPSR, R0" ); /* Write back modified value. */ \ - asm volatile ( "LDMIA SP!, {R0}" ) /* Pop R0. */ - -#define portENABLE_INTERRUPTS() \ - asm volatile ( "STMDB SP!, {R0}" ); /* Push R0. */ \ - asm volatile ( "MRS R0, CPSR" ); /* Get CPSR. */ \ - asm volatile ( "BIC R0, R0, #0xC0" ); /* Enable IRQ, FIQ. */ \ - asm volatile ( "MSR CPSR, R0" ); /* Write back modified value. */ \ - asm volatile ( "LDMIA SP!, {R0}" ) /* Pop R0. */ - -#endif /* THUMB_INTERWORK */ - -extern void vPortEnterCritical( void ); -extern void vPortExitCritical( void ); - -#define portENTER_CRITICAL() vPortEnterCritical(); -#define portEXIT_CRITICAL() vPortExitCritical(); -/*-----------------------------------------------------------*/ - -/* Task function macros as described on the FreeRTOS.org WEB site. */ -#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) -#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) - -#endif /* PORTMACRO_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/MemMang/heap_1.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/MemMang/heap_1.c deleted file mode 100644 index fef991bff..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/MemMang/heap_1.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - -Changes between V2.5.1 and V2.5.1 - - + The memory pool has been defined within a struct to ensure correct memory - alignment on 32bit systems. - -Changes between V2.6.1 and V3.0.0 - - + An overflow check has been added to ensure the next free byte variable - does not wrap around. -*/ - - -/* - * The simplest possible implementation of pvPortMalloc(). Note that this - * implementation does NOT allow allocated memory to be freed again. - * - * See heap_2.c and heap_3.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ -#include -#include "FreeRTOS.h" -#include "task.h" - -/* Setup the correct byte alignment mask for the defined byte alignment. */ -#if portBYTE_ALIGNMENT == 4 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) -#endif - -#if portBYTE_ALIGNMENT == 2 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) -#endif - -#if portBYTE_ALIGNMENT == 1 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) -#endif - -#ifndef heapBYTE_ALIGNMENT_MASK - #error "Invalid portBYTE_ALIGNMENT definition" -#endif - -/* Allocate the memory for the heap. The struct is used to force byte -alignment without using any non-portable code. */ -static struct xRTOS_HEAP -{ - unsigned portLONG ulDummy; - unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; -} xHeap; - -static size_t xNextFreeByte = ( size_t ) 0; -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -void *pvReturn = NULL; - - /* Ensure that blocks are always aligned to the required number of bytes. */ - #if portBYTE_ALIGNMENT != 1 - if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) - { - /* Byte alignment required. */ - xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); - } - #endif - - vTaskSuspendAll(); - { - /* Check there is enough room left for the allocation. */ - if( ( ( xNextFreeByte + xWantedSize ) < configTOTAL_HEAP_SIZE ) && - ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) )/* Check for overflow. */ - { - /* Return the next free byte then increment the index past this - block. */ - pvReturn = &( xHeap.ucHeap[ xNextFreeByte ] ); - xNextFreeByte += xWantedSize; - } - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ - /* Memory cannot be freed using this scheme. See heap_2.c and heap_3.c - for alternative implementations, and the memory management pages of - http://www.FreeRTOS.org for more information. */ - ( void ) pv; -} -/*-----------------------------------------------------------*/ - -void vPortInitialiseBlocks( void ) -{ - /* Only required when static memory is not cleared. */ - xNextFreeByte = ( size_t ) 0; -} - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/MemMang/heap_2.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/MemMang/heap_2.c deleted file mode 100644 index f9896cfe3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/MemMang/heap_2.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* - * A sample implementation of pvPortMalloc() and vPortFree() that permits - * allocated blocks to be freed, but does not combine adjacent free blocks - * into a single larger block. - * - * See heap_1.c and heap_3.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ -#include - -#include "FreeRTOS.h" -#include "task.h" - -/* Setup the correct byte alignment mask for the defined byte alignment. */ -#if portBYTE_ALIGNMENT == 4 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0003 ) -#endif - -#if portBYTE_ALIGNMENT == 2 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0001 ) -#endif - -#if portBYTE_ALIGNMENT == 1 - #define heapBYTE_ALIGNMENT_MASK ( ( size_t ) 0x0000 ) -#endif - -#ifndef heapBYTE_ALIGNMENT_MASK - #error "Invalid portBYTE_ALIGNMENT definition" -#endif - -/* Allocate the memory for the heap. The struct is used to force byte -alignment without using any non-portable code. */ -static struct xRTOS_HEAP -{ - unsigned portLONG ulDummy; - unsigned portCHAR ucHeap[ configTOTAL_HEAP_SIZE ]; -} xHeap; - -/* Define the linked list structure. This is used to link free blocks in order -of their size. */ -typedef struct A_BLOCK_LINK -{ - struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */ - size_t xBlockSize; /*<< The size of the free block. */ -} xBlockLink; - - -static const unsigned portSHORT heapSTRUCT_SIZE = ( sizeof( xBlockLink ) + ( sizeof( xBlockLink ) % portBYTE_ALIGNMENT ) ); -#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) ) - -/* Create a couple of list links to mark the start and end of the list. */ -static xBlockLink xStart, xEnd; - -/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */ - -/* - * Insert a block into the list of free blocks - which is ordered by size of - * the block. Small blocks at the start of the list and large blocks at the end - * of the list. - */ -#define prvInsertBlockIntoFreeList( pxBlockToInsert ) \ -{ \ -xBlockLink *pxIterator; \ -size_t xBlockSize; \ - \ - xBlockSize = pxBlockToInsert->xBlockSize; \ - \ - /* Iterate through the list until a block is found that has a larger size */ \ - /* than the block we are inserting. */ \ - for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \ - { \ - /* There is nothing to do here - just iterate to the correct position. */ \ - } \ - \ - /* Update the list to include the block being inserted in the correct */ \ - /* position. */ \ - pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; \ - pxIterator->pxNextFreeBlock = pxBlockToInsert; \ -} -/*-----------------------------------------------------------*/ - -#define prvHeapInit() \ -{ \ -xBlockLink *pxFirstFreeBlock; \ - \ - /* xStart is used to hold a pointer to the first item in the list of free */ \ - /* blocks. The void cast is used to prevent compiler warnings. */ \ - xStart.pxNextFreeBlock = ( void * ) xHeap.ucHeap; \ - xStart.xBlockSize = ( size_t ) 0; \ - \ - /* xEnd is used to mark the end of the list of free blocks. */ \ - xEnd.xBlockSize = configTOTAL_HEAP_SIZE; \ - xEnd.pxNextFreeBlock = NULL; \ - \ - /* To start with there is a single free block that is sized to take up the \ - entire heap space. */ \ - pxFirstFreeBlock = ( void * ) xHeap.ucHeap; \ - pxFirstFreeBlock->xBlockSize = configTOTAL_HEAP_SIZE; \ - pxFirstFreeBlock->pxNextFreeBlock = &xEnd; \ -} -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -xBlockLink *pxBlock, *pxPreviousBlock, *pxNewBlockLink; -static portBASE_TYPE xHeapHasBeenInitialised = pdFALSE; -void *pvReturn = NULL; - - vTaskSuspendAll(); - { - /* If this is the first call to malloc then the heap will require - initialisation to setup the list of free blocks. */ - if( xHeapHasBeenInitialised == pdFALSE ) - { - prvHeapInit(); - xHeapHasBeenInitialised = pdTRUE; - } - - /* The wanted size is increased so it can contain a xBlockLink - structure in addition to the requested amount of bytes. */ - if( xWantedSize > 0 ) - { - xWantedSize += heapSTRUCT_SIZE; - - /* Ensure that blocks are always aligned to the required number of bytes. */ - if( xWantedSize & heapBYTE_ALIGNMENT_MASK ) - { - /* Byte alignment required. */ - xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & heapBYTE_ALIGNMENT_MASK ) ); - } - } - - if( ( xWantedSize > 0 ) && ( xWantedSize < configTOTAL_HEAP_SIZE ) ) - { - /* Blocks are stored in byte order - traverse the list from the start - (smallest) block until one of adequate size is found. */ - pxPreviousBlock = &xStart; - pxBlock = xStart.pxNextFreeBlock; - while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock ) ) - { - pxPreviousBlock = pxBlock; - pxBlock = pxBlock->pxNextFreeBlock; - } - - /* If we found the end marker then a block of adequate size was not found. */ - if( pxBlock != &xEnd ) - { - /* Return the memory space - jumping over the xBlockLink structure - at its start. */ - pvReturn = ( void * ) ( ( ( unsigned portCHAR * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE ); - - /* This block is being returned for use so must be taken our of the - list of free blocks. */ - pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; - - /* If the block is larger than required it can be split into two. */ - if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) - { - /* This block is to be split into two. Create a new block - following the number of bytes requested. The void cast is - used to prevent byte alignment warnings from the compiler. */ - pxNewBlockLink = ( void * ) ( ( ( unsigned portCHAR * ) pxBlock ) + xWantedSize ); - - /* Calculate the sizes of two blocks split from the single - block. */ - pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; - pxBlock->xBlockSize = xWantedSize; - - /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); - } - } - } - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ -unsigned portCHAR *puc = ( unsigned portCHAR * ) pv; -xBlockLink *pxLink; - - if( pv ) - { - /* The memory being freed will have an xBlockLink structure immediately - before it. */ - puc -= heapSTRUCT_SIZE; - - /* This casting is to keep the compiler from issuing warnings. */ - pxLink = ( void * ) puc; - - vTaskSuspendAll(); - { - /* Add this block to the list of free blocks. */ - prvInsertBlockIntoFreeList( ( ( xBlockLink * ) pxLink ) ); - } - xTaskResumeAll(); - } -} -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/MemMang/heap_3.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/MemMang/heap_3.c deleted file mode 100644 index 4b3ce0b72..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/portable/MemMang/heap_3.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - - -/* - * Implementation of pvPortMalloc() and vPortFree() that relies on the - * compilers own malloc() and free() implementations. - * - * This file can only be used if the linker is configured to to generate - * a heap memory area. - * - * See heap_2.c and heap_1.c for alternative implementations, and the memory - * management pages of http://www.FreeRTOS.org for more information. - */ - -#include - -#include "FreeRTOS.h" -#include "task.h" - -/*-----------------------------------------------------------*/ - -void *pvPortMalloc( size_t xWantedSize ) -{ -void *pvReturn; - - vTaskSuspendAll(); - { - pvReturn = malloc( xWantedSize ); - } - xTaskResumeAll(); - - return pvReturn; -} -/*-----------------------------------------------------------*/ - -void vPortFree( void *pv ) -{ - if( pv ) - { - vTaskSuspendAll(); - { - free( pv ); - } - xTaskResumeAll(); - } -} - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/queue.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/queue.c deleted file mode 100644 index 0791ad55a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/queue.c +++ /dev/null @@ -1,882 +0,0 @@ -/* - FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.01 - - + More use of 8bit data types. - + Function name prefixes changed where the data type returned has changed. - -Changed from V2.0.0 - - + Added the queue locking mechanism and make more use of the scheduler - suspension feature to minimise the time interrupts have to be disabled - when accessing a queue. - -Changed from V2.2.0 - - + Explicit use of 'signed' qualifier on portCHAR types added. - -Changes from V3.0.0 - - + API changes as described on the FreeRTOS.org WEB site. - -Changes from V3.2.3 - - + Added the queue functions that can be used from co-routines. - -Changes from V4.0.5 - - + Added a loop within xQueueSend() and xQueueReceive() to prevent the - functions exiting when a block time remains and the function has - not completed. - -*/ - -#include -#include -#include "FreeRTOS.h" -#include "task.h" -#include "croutine.h" - -/*----------------------------------------------------------- - * PUBLIC LIST API documented in list.h - *----------------------------------------------------------*/ - -/* Constants used with the cRxLock and cTxLock structure members. */ -#define queueUNLOCKED ( ( signed portBASE_TYPE ) -1 ) -#define queueERRONEOUS_UNBLOCK ( -1 ) - -/* - * Definition of the queue used by the scheduler. - * Items are queued by copy, not reference. - */ -typedef struct QueueDefinition -{ - signed portCHAR *pcHead; /*< Points to the beginning of the queue storage area. */ - signed portCHAR *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */ - - signed portCHAR *pcWriteTo; /*< Points to the free next place in the storage area. */ - signed portCHAR *pcReadFrom; /*< Points to the last place that a queued item was read from. */ - - xList xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */ - xList xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */ - - unsigned portBASE_TYPE uxMessagesWaiting;/*< The number of items currently in the queue. */ - unsigned portBASE_TYPE uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */ - unsigned portBASE_TYPE uxItemSize; /*< The size of each items that the queue will hold. */ - - signed portBASE_TYPE xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ - signed portBASE_TYPE xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ -} xQUEUE; -/*-----------------------------------------------------------*/ - -/* - * Inside this file xQueueHandle is a pointer to a xQUEUE structure. - * To keep the definition private the API header file defines it as a - * pointer to void. - */ -typedef xQUEUE * xQueueHandle; - -/* - * Prototypes for public functions are included here so we don't have to - * include the API header file (as it defines xQueueHandle differently). These - * functions are documented in the API header file. - */ -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ); -signed portBASE_TYPE xQueueSend( xQueueHandle xQueue, const void * pvItemToQueue, portTickType xTicksToWait ); -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue ); -void vQueueDelete( xQueueHandle xQueue ); -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ); -signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - -#if configUSE_CO_ROUTINES == 1 - signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ); - signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ); - signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ); - signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ); -#endif - -/* - * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not - * prevent an ISR from adding or removing items to the queue, but does prevent - * an ISR from removing tasks from the queue event lists. If an ISR finds a - * queue is locked it will instead increment the appropriate queue lock count - * to indicate that a task may require unblocking. When the queue in unlocked - * these lock counts are inspected, and the appropriate action taken. - */ -static void prvUnlockQueue( xQueueHandle pxQueue ); - -/* - * Uses a critical section to determine if there is any data in a queue. - * - * @return pdTRUE if the queue contains no items, otherwise pdFALSE. - */ -static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ); - -/* - * Uses a critical section to determine if there is any space in a queue. - * - * @return pdTRUE if there is no space, otherwise pdFALSE; - */ -static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ); - -/* - * Macro that copies an item into the queue. This is done by copying the item - * byte for byte, not by reference. Updates the queue state to ensure it's - * integrity after the copy. - */ -#define prvCopyQueueData( pxQueue, pvItemToQueue ) \ -{ \ - memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( unsigned ) pxQueue->uxItemSize ); \ - ++( pxQueue->uxMessagesWaiting ); \ - pxQueue->pcWriteTo += pxQueue->uxItemSize; \ - if( pxQueue->pcWriteTo >= pxQueue->pcTail ) \ - { \ - pxQueue->pcWriteTo = pxQueue->pcHead; \ - } \ -} -/*-----------------------------------------------------------*/ - -/* - * Macro to mark a queue as locked. Locking a queue prevents an ISR from - * accessing the queue event lists. - */ -#define prvLockQueue( pxQueue ) \ -{ \ - taskENTER_CRITICAL(); \ - ++( pxQueue->xRxLock ); \ - ++( pxQueue->xTxLock ); \ - taskEXIT_CRITICAL(); \ -} -/*-----------------------------------------------------------*/ - - -/*----------------------------------------------------------- - * PUBLIC QUEUE MANAGEMENT API documented in queue.h - *----------------------------------------------------------*/ - -xQueueHandle xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize ) -{ -xQUEUE *pxNewQueue; -size_t xQueueSizeInBytes; - - /* Allocate the new queue structure. */ - if( uxQueueLength > ( unsigned portBASE_TYPE ) 0 ) - { - pxNewQueue = ( xQUEUE * ) pvPortMalloc( sizeof( xQUEUE ) ); - if( pxNewQueue != NULL ) - { - /* Create the list of pointers to queue items. The queue is one byte - longer than asked for to make wrap checking easier/faster. */ - xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1; - - pxNewQueue->pcHead = ( signed portCHAR * ) pvPortMalloc( xQueueSizeInBytes ); - if( pxNewQueue->pcHead != NULL ) - { - /* Initialise the queue members as described above where the - queue type is defined. */ - pxNewQueue->pcTail = pxNewQueue->pcHead + ( uxQueueLength * uxItemSize ); - pxNewQueue->uxMessagesWaiting = 0; - pxNewQueue->pcWriteTo = pxNewQueue->pcHead; - pxNewQueue->pcReadFrom = pxNewQueue->pcHead + ( ( uxQueueLength - 1 ) * uxItemSize ); - pxNewQueue->uxLength = uxQueueLength; - pxNewQueue->uxItemSize = uxItemSize; - pxNewQueue->xRxLock = queueUNLOCKED; - pxNewQueue->xTxLock = queueUNLOCKED; - - /* Likewise ensure the event queues start with the correct state. */ - vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) ); - vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) ); - - return pxNewQueue; - } - else - { - vPortFree( pxNewQueue ); - } - } - } - - /* Will only reach here if we could not allocate enough memory or no memory - was required. */ - return NULL; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; -xTimeOutType xTimeOut; - - /* Make sure other tasks do not access the queue. */ - vTaskSuspendAll(); - - /* Capture the current time status for future reference. */ - vTaskSetTimeOutState( &xTimeOut ); - - /* It is important that this is the only thread/ISR that modifies the - ready or delayed lists until xTaskResumeAll() is called. Places where - the ready/delayed lists are modified include: - - + vTaskDelay() - Nothing can call vTaskDelay as the scheduler is - suspended, vTaskDelay() cannot be called from an ISR. - + vTaskPrioritySet() - Has a critical section around the access. - + vTaskSwitchContext() - This will not get executed while the scheduler - is suspended. - + prvCheckDelayedTasks() - This will not get executed while the - scheduler is suspended. - + xTaskCreate() - Has a critical section around the access. - + vTaskResume() - Has a critical section around the access. - + xTaskResumeAll() - Has a critical section around the access. - + xTaskRemoveFromEventList - Checks to see if the scheduler is - suspended. If so then the TCB being removed from the event is - removed from the event and added to the xPendingReadyList. - */ - - /* Make sure interrupts do not access the queue event list. */ - prvLockQueue( pxQueue ); - - /* It is important that interrupts to not access the event list of the - queue being modified here. Places where the event list is modified - include: - - + xQueueSendFromISR(). This checks the lock on the queue to see if - it has access. If the queue is locked then the Tx lock count is - incremented to signify that a task waiting for data can be made ready - once the queue lock is removed. If the queue is not locked then - a task can be moved from the event list, but will not be removed - from the delayed list or placed in the ready list until the scheduler - is unlocked. - - + xQueueReceiveFromISR(). As per xQueueSendFromISR(). - */ - - /* If the queue is already full we may have to block. */ - do - { - if( prvIsQueueFull( pxQueue ) ) - { - /* The queue is full - do we want to block or just leave without - posting? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* We are going to place ourselves on the xTasksWaitingToSend event - list, and will get woken should the delay expire, or space become - available on the queue. - - As detailed above we do not require mutual exclusion on the event - list as nothing else can modify it or the ready lists while we - have the scheduler suspended and queue locked. - - It is possible that an ISR has removed data from the queue since we - checked if any was available. If this is the case then the data - will have been copied from the queue, and the queue variables - updated, but the event list will not yet have been checked to see if - anything is waiting as the queue is locked. */ - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); - - /* Force a context switch now as we are blocked. We can do - this from within a critical section as the task we are - switching to has its own context. When we return here (i.e. we - unblock) we will leave the critical section as normal. - - It is possible that an ISR has caused an event on an unrelated and - unlocked queue. If this was the case then the event list for that - queue will have been updated but the ready lists left unchanged - - instead the readied task will have been added to the pending ready - list. */ - taskENTER_CRITICAL(); - { - /* We can safely unlock the queue and scheduler here as - interrupts are disabled. We must not yield with anything - locked, but we can yield from within a critical section. - - Tasks that have been placed on the pending ready list cannot - be tasks that are waiting for events on this queue. See - in comment xTaskRemoveFromEventList(). */ - prvUnlockQueue( pxQueue ); - - /* Resuming the scheduler may cause a yield. If so then there - is no point yielding again here. */ - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - - /* Before leaving the critical section we have to ensure - exclusive access again. */ - vTaskSuspendAll(); - prvLockQueue( pxQueue ); - } - taskEXIT_CRITICAL(); - } - } - - /* When we are here it is possible that we unblocked as space became - available on the queue. It is also possible that an ISR posted to the - queue since we left the critical section, so it may be that again there - is no space. This would only happen if a task and ISR post onto the - same queue. */ - taskENTER_CRITICAL(); - { - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - /* There is room in the queue, copy the data into the queue. */ - prvCopyQueueData( pxQueue, pvItemToQueue ); - xReturn = pdPASS; - - /* Update the TxLock count so prvUnlockQueue knows to check for - tasks waiting for data to become available in the queue. */ - ++( pxQueue->xTxLock ); - } - else - { - xReturn = errQUEUE_FULL; - } - } - taskEXIT_CRITICAL(); - - if( xReturn == errQUEUE_FULL ) - { - if( xTicksToWait > 0 ) - { - if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) - { - xReturn = queueERRONEOUS_UNBLOCK; - } - } - } - } - while( xReturn == queueERRONEOUS_UNBLOCK ); - - prvUnlockQueue( pxQueue ); - xTaskResumeAll(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xTaskPreviouslyWoken ) -{ - /* Similar to xQueueSend, except we don't block if there is no room in the - queue. Also we don't directly wake a task that was blocked on a queue - read, instead we return a flag to say whether a context switch is required - or not (i.e. has a task with a higher priority than us been woken by this - post). */ - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - prvCopyQueueData( pxQueue, pvItemToQueue ); - - /* If the queue is locked we do not alter the event list. This will - be done when the queue is unlocked later. */ - if( pxQueue->xTxLock == queueUNLOCKED ) - { - /* We only want to wake one task per ISR, so check that a task has - not already been woken. */ - if( !xTaskPreviouslyWoken ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority so record that a - context switch is required. */ - return pdTRUE; - } - } - } - } - else - { - /* Increment the lock count so the task that unlocks the queue - knows that data was posted while it was locked. */ - ++( pxQueue->xTxLock ); - } - } - - return xTaskPreviouslyWoken; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; -xTimeOutType xTimeOut; - - /* This function is very similar to xQueueSend(). See comments within - xQueueSend() for a more detailed explanation. - - Make sure other tasks do not access the queue. */ - vTaskSuspendAll(); - - /* Capture the current time status for future reference. */ - vTaskSetTimeOutState( &xTimeOut ); - - /* Make sure interrupts do not access the queue. */ - prvLockQueue( pxQueue ); - - do - { - /* If there are no messages in the queue we may have to block. */ - if( prvIsQueueEmpty( pxQueue ) ) - { - /* There are no messages in the queue, do we want to block or just - leave with nothing? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); - taskENTER_CRITICAL(); - { - prvUnlockQueue( pxQueue ); - if( !xTaskResumeAll() ) - { - taskYIELD(); - } - - vTaskSuspendAll(); - prvLockQueue( pxQueue ); - } - taskEXIT_CRITICAL(); - } - } - - taskENTER_CRITICAL(); - { - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - /* Increment the lock count so prvUnlockQueue knows to check for - tasks waiting for space to become available on the queue. */ - ++( pxQueue->xRxLock ); - xReturn = pdPASS; - } - else - { - xReturn = errQUEUE_EMPTY; - } - } - taskEXIT_CRITICAL(); - - if( xReturn == errQUEUE_EMPTY ) - { - if( xTicksToWait > 0 ) - { - if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) - { - xReturn = queueERRONEOUS_UNBLOCK; - } - } - } - } while( xReturn == queueERRONEOUS_UNBLOCK ); - - /* We no longer require exclusive access to the queue. */ - prvUnlockQueue( pxQueue ); - xTaskResumeAll(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xQueueReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxTaskWoken ) -{ -signed portBASE_TYPE xReturn; - - /* We cannot block from an ISR, so check there is data available. */ - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Copy the data from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - /* If the queue is locked we will not modify the event list. Instead - we update the lock count so the task that unlocks the queue will know - that an ISR has removed data while the queue was locked. */ - if( pxQueue->xRxLock == queueUNLOCKED ) - { - /* We only want to wake one task per ISR, so check that a task has - not already been woken. */ - if( !( *pxTaskWoken ) ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - /* The task waiting has a higher priority than us so - force a context switch. */ - *pxTaskWoken = pdTRUE; - } - } - } - } - else - { - /* Increment the lock count so the task that unlocks the queue - knows that data was removed while it was locked. */ - ++( pxQueue->xRxLock ); - } - - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxQueueMessagesWaiting( xQueueHandle pxQueue ) -{ -unsigned portBASE_TYPE uxReturn; - - taskENTER_CRITICAL(); - uxReturn = pxQueue->uxMessagesWaiting; - taskEXIT_CRITICAL(); - - return uxReturn; -} -/*-----------------------------------------------------------*/ - -void vQueueDelete( xQueueHandle pxQueue ) -{ - vPortFree( pxQueue->pcHead ); - vPortFree( pxQueue ); -} -/*-----------------------------------------------------------*/ - -static void prvUnlockQueue( xQueueHandle pxQueue ) -{ - /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */ - - /* The lock counts contains the number of extra data items placed or - removed from the queue while the queue was locked. When a queue is - locked items can be added or removed, but the event lists cannot be - updated. */ - taskENTER_CRITICAL(); - { - --( pxQueue->xTxLock ); - - /* See if data was added to the queue while it was locked. */ - if( pxQueue->xTxLock > queueUNLOCKED ) - { - pxQueue->xTxLock = queueUNLOCKED; - - /* Data was posted while the queue was locked. Are any tasks - blocked waiting for data to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - /* Tasks that are removed from the event list will get added to - the pending ready list as the scheduler is still suspended. */ - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The task waiting has a higher priority so record that a - context switch is required. */ - vTaskMissedYield(); - } - } - } - } - taskEXIT_CRITICAL(); - - /* Do the same for the Rx lock. */ - taskENTER_CRITICAL(); - { - --( pxQueue->xRxLock ); - - if( pxQueue->xRxLock > queueUNLOCKED ) - { - pxQueue->xRxLock = queueUNLOCKED; - - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - vTaskMissedYield(); - } - } - } - } - taskEXIT_CRITICAL(); -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvIsQueueEmpty( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - taskENTER_CRITICAL(); - xReturn = ( pxQueue->uxMessagesWaiting == ( unsigned portBASE_TYPE ) 0 ); - taskEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -static signed portBASE_TYPE prvIsQueueFull( const xQueueHandle pxQueue ) -{ -signed portBASE_TYPE xReturn; - - taskENTER_CRITICAL(); - xReturn = ( pxQueue->uxMessagesWaiting == pxQueue->uxLength ); - taskEXIT_CRITICAL(); - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRSend( xQueueHandle pxQueue, const void *pvItemToQueue, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* If the queue is already full we may have to block. A critical section - is required to prevent an interrupt removing something from the queue - between the check to see if the queue is full and blocking on the queue. */ - portDISABLE_INTERRUPTS(); - { - if( prvIsQueueFull( pxQueue ) ) - { - /* The queue is full - do we want to block or just leave without - posting? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* As this is called from a coroutine we cannot block directly, but - return indicating that we need to block. */ - vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) ); - portENABLE_INTERRUPTS(); - return errQUEUE_BLOCKED; - } - else - { - portENABLE_INTERRUPTS(); - return errQUEUE_FULL; - } - } - } - portENABLE_INTERRUPTS(); - - portNOP(); - - portDISABLE_INTERRUPTS(); - { - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - /* There is room in the queue, copy the data into the queue. */ - prvCopyQueueData( pxQueue, pvItemToQueue ); - xReturn = pdPASS; - - /* Were any co-routines waiting for data to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - /* In this instance the co-routine could be placed directly - into the ready list as we are within a critical section. - Instead the same pending ready list mechansim is used as if - the event were caused from within an interrupt. */ - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - /* The co-routine waiting has a higher priority so record - that a yield might be appropriate. */ - xReturn = errQUEUE_YIELD; - } - } - } - else - { - xReturn = errQUEUE_FULL; - } - } - portENABLE_INTERRUPTS(); - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRReceive( xQueueHandle pxQueue, void *pvBuffer, portTickType xTicksToWait ) -{ -signed portBASE_TYPE xReturn; - - /* If the queue is already empty we may have to block. A critical section - is required to prevent an interrupt adding something to the queue - between the check to see if the queue is empty and blocking on the queue. */ - portDISABLE_INTERRUPTS(); - { - if( prvIsQueueEmpty( pxQueue ) ) - { - /* There are no messages in the queue, do we want to block or just - leave with nothing? */ - if( xTicksToWait > ( portTickType ) 0 ) - { - /* As this is a co-routine we cannot block directly, but return - indicating that we need to block. */ - vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) ); - portENABLE_INTERRUPTS(); - return errQUEUE_BLOCKED; - } - else - { - portENABLE_INTERRUPTS(); - return errQUEUE_FULL; - } - } - } - portENABLE_INTERRUPTS(); - - portNOP(); - - portDISABLE_INTERRUPTS(); - { - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Data is available from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - xReturn = pdPASS; - - /* Were any co-routines waiting for space to become available? */ - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - /* In this instance the co-routine could be placed directly - into the ready list as we are within a critical section. - Instead the same pending ready list mechansim is used as if - the event were caused from within an interrupt. */ - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - xReturn = errQUEUE_YIELD; - } - } - } - else - { - xReturn = pdFAIL; - } - } - portENABLE_INTERRUPTS(); - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - - - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRSendFromISR( xQueueHandle pxQueue, const void *pvItemToQueue, signed portBASE_TYPE xCoRoutinePreviouslyWoken ) -{ - /* Cannot block within an ISR so if there is no space on the queue then - exit without doing anything. */ - if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) - { - prvCopyQueueData( pxQueue, pvItemToQueue ); - - /* We only want to wake one co-routine per ISR, so check that a - co-routine has not already been woken. */ - if( !xCoRoutinePreviouslyWoken ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) ) - { - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - { - return pdTRUE; - } - } - } - } - - return xCoRoutinePreviouslyWoken; -} -#endif -/*-----------------------------------------------------------*/ - -#if configUSE_CO_ROUTINES == 1 -signed portBASE_TYPE xQueueCRReceiveFromISR( xQueueHandle pxQueue, void *pvBuffer, signed portBASE_TYPE *pxCoRoutineWoken ) -{ -signed portBASE_TYPE xReturn; - - /* We cannot block from an ISR, so check there is data available. If - not then just leave without doing anything. */ - if( pxQueue->uxMessagesWaiting > ( unsigned portBASE_TYPE ) 0 ) - { - /* Copy the data from the queue. */ - pxQueue->pcReadFrom += pxQueue->uxItemSize; - if( pxQueue->pcReadFrom >= pxQueue->pcTail ) - { - pxQueue->pcReadFrom = pxQueue->pcHead; - } - --( pxQueue->uxMessagesWaiting ); - memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); - - if( !( *pxCoRoutineWoken ) ) - { - if( !listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) ) - { - if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - { - *pxCoRoutineWoken = pdTRUE; - } - } - } - - xReturn = pdPASS; - } - else - { - xReturn = pdFAIL; - } - - return xReturn; -} -#endif -/*-----------------------------------------------------------*/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/tasks.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/tasks.c deleted file mode 100644 index 20d5a6b94..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/freertos/tasks.c +++ /dev/null @@ -1,1814 +0,0 @@ -/* - FreeRTOS.org V4.1.0 - Copyright (C) 2003-2006 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant - port sections of the online documentation. - *************************************************************************** -*/ - -/* -Changes from V1.00: - - + Call to portRESTORE_CONTEXT has been removed. The first context - switch is now performed within sPortStartScheduler(). - -Changes from V1.01: - - + More use of 8bit data types. - + Function name prefixes changed where the data type returned has changed. - + configUSE_TRACE_FACILITY is no longer defined by default. - -Changes from V1.2.0 - - + Introduced ucTopReadyPriority. This tracks the highest priority ready - queue that contains a valid TCB and thus makes the context switch - slightly faster. - - + prvAddTaskToReadyQueue() has been made a macro. - -Changes from V1.2.6 - - + Added conditional compilation directives. - + Extended API. - + Rearranged function order. - + Creating a task now causes a context switch if the task being created - has a higher priority than the calling task - assuming the kernel is - running. - + vTaskDelete() now only causes a context switch if the calling task is - the task being deleted. - -Changes from V2.0.0 - - + Allow the type of the tick count to be 16 or 32 bits. - + Introduce xPendingReadyList feature to allow the time interrupts have to - be disabled to be minimised. - + Remove the #if( INCLUDE_vTaskSuspendAll ) statements. vTaskSuspendAll() - is now always included as it is used by the scheduler itself. - -Changes from V2.1.0 - - + Bug fix - pxCurrentTCB is now initialised before the call to - prvInitializeTaskLists(). Previously pxCurrentTCB could be accessed - while null. - -Changed from V2.1.1 - - + Change to where lStackSize is declared within sTaskCreate() to prevent - compiler warnings with 8051 port. - -Changes from V2.2.0 - - + Explicit use of 'signed' qualifier on portCHAR types added. - + Changed odd calculation of initial pxTopOfStack value when - portSTACK_GROWTH < 0. - + Removed pcVersionNumber definition. - -Changes from V2.5.3 - - + cTaskResumeAll() modified to ensure it can be called prior to the task - lists being initialised. - -Changes from V2.5.5 - - + Added API function vTaskDelayUntil(). - + Added INCLUDE_vTaskDelay conditional compilation. - -Changes from V2.6.0 - - + Updated the vWriteTraceToBuffer macro to always be 4 byte aligned so it - can be used on ARM architectures. - + tskMAX_TASK_NAME_LEN definition replaced with the port specific - configMAX_TASK_NAME_LEN definition. - + Removed the call to strcpy when copying across the task name into the - TCB. - + Added ucTasksDeleted variable to prevent vTaskSuspendAll() being called - too often in the idle task. - -Changes between V3.0.0 and V2.6.1 - - + When resuming the scheduler a yield is performed if either a tick has - been missed, or a task is moved from the pending ready list into a ready - list. Previously a yield was not performed on this second condition. - + Introduced the type portBASE_TYPE. This necessitates several API - changes. - + Removed the sUsingPreemption variable. The constant defined in - portmacro.h is now used directly. - + The idle task can now include an optional hook function - and no longer - completes its time slice if other tasks with equal priority to it are - ready to run. - + See the FreeRTOS.org documentation for more information on V2.x.x to - V3.x.x modifications. - -Changes from V3.1.1 - - + Modified vTaskPrioritySet() and vTaskResume() to allow these functions to - be called while the scheduler is suspended. - + Corrected the task ordering within event lists. - -Changes from V3.2.0 - - + Added function xTaskGetCurrentTaskHandle(). - -Changes from V3.2.4 - - + Changed the volatile declarations on some variables to reflect the - changes to the list definitions. - + Changed the order of the TCB definition so there is commonality between - the task control block and a co-routine control block. - + Allow the scheduler to be started even if no tasks other than the idle - task has been created. This allows co-routines to run even when no tasks - have been created. - + The need for a context switch is now signalled if a task woken by an - event has a priority greater or equal to the currently running task. - Previously this was only greater than. - -Changes from V4.0.0 - - + Added the xMissedYield handling. - -Changes from V4.0.1 - - + The function vTaskList() now suspends the scheduler rather than disabling - interrupts during the creation of the task list. - + Allow a task to delete itself by passing in its own handle. Previously - this could only be done by passing in NULL. - + The tick hook function is now called only within a tick isr. Previously - it was also called when the tick function was called during the scheduler - unlocking process. - -Changes from V4.0.3 - - + Extra checks have been placed in vTaskPrioritySet() to avoid unnecessary - yields. - -Changed from V4.0.4 - - + Bug fix: The 'value' of the event list item is updated when the priority - of a task is changed. Previously only the priority of the TCB itself was - changed. - + When resuming a task a check is first made to see if the task is actually - suspended. - + vTaskPrioritySet() and vTaskResume() no longer use the event list item. - This has not been necessary since V4.0.1 when the xMissedYield handling - was added. - + Implement xTaskResumeFromISR(). - -Changes from V4.0.5 - - + Added utility functions and xOverflowCount variable to facilitate the - queue.c changes. -*/ - -#include -#include -#include - -#include "FreeRTOS.h" -#include "task.h" - -/* - * Macro to define the amount of stack available to the idle task. - */ -#define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE - - -/* - * Default a definitions for backwards compatibility with old - * portmacro.h files. - */ -#ifndef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 16 -#endif - -#ifndef INCLUDE_xTaskGetCurrentTaskHandle - #define INCLUDE_xTaskGetCurrentTaskHandle 0 -#endif - -#ifndef configIDLE_SHOULD_YIELD - #define configIDLE_SHOULD_YIELD 1 -#endif - -#if configMAX_TASK_NAME_LEN < 1 - #undef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 1 -#endif - -#ifndef INCLUDE_xTaskResumeFromISR - #define INCLUDE_xTaskResumeFromISR 1 -#endif - -/* - * Task control block. A task control block (TCB) is allocated to each task, - * and stores the context of the task. - */ -typedef struct tskTaskControlBlock -{ - volatile portSTACK_TYPE *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE STRUCT. */ - xListItem xGenericListItem; /*< List item used to place the TCB in ready and blocked queues. */ - xListItem xEventListItem; /*< List item used to place the TCB in event lists. */ - unsigned portBASE_TYPE uxPriority; /*< The priority of the task where 0 is the lowest priority. */ - portSTACK_TYPE *pxStack; /*< Points to the start of the stack. */ - unsigned portBASE_TYPE uxTCBNumber; /*< This is used for tracing the scheduler and making debugging easier only. */ - signed portCHAR pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */ - unsigned portSHORT usStackDepth; /*< Total depth of the stack (when empty). This is defined as the number of variables the stack can hold, not the number of bytes. */ -} tskTCB; - -/*lint -e956 */ - -tskTCB * volatile pxCurrentTCB = NULL; - -/* Lists for ready and blocked tasks. --------------------*/ - -static xList pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */ -static xList xDelayedTaskList1; /*< Delayed tasks. */ -static xList xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */ -static xList * volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */ -static xList * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */ -static xList xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready queue when the scheduler is resumed. */ - -#if ( INCLUDE_vTaskDelete == 1 ) - - static volatile xList xTasksWaitingTermination; /*< Tasks that have been deleted - but the their memory not yet freed. */ - static volatile unsigned portBASE_TYPE uxTasksDeleted = ( unsigned portBASE_TYPE ) 0; - -#endif - -#if ( INCLUDE_vTaskSuspend == 1 ) - - static xList xSuspendedTaskList; /*< Tasks that are currently suspended. */ - -#endif - -/* File private variables. --------------------------------*/ -static volatile unsigned portBASE_TYPE uxCurrentNumberOfTasks = ( unsigned portBASE_TYPE ) 0; -static volatile portTickType xTickCount = ( portTickType ) 0; -static unsigned portBASE_TYPE uxTopUsedPriority = tskIDLE_PRIORITY; -static volatile unsigned portBASE_TYPE uxTopReadyPriority = tskIDLE_PRIORITY; -static volatile signed portBASE_TYPE xSchedulerRunning = pdFALSE; -static volatile unsigned portBASE_TYPE uxSchedulerSuspended = ( unsigned portBASE_TYPE ) pdFALSE; -static volatile unsigned portBASE_TYPE uxMissedTicks = ( unsigned portBASE_TYPE ) 0; -static volatile portBASE_TYPE xMissedYield = ( portBASE_TYPE ) pdFALSE; -static volatile portBASE_TYPE xNumOfOverflows = ( portBASE_TYPE ) 0; -/* Debugging and trace facilities private variables and macros. ------------*/ - -/* - * The value used to fill the stack of a task when the task is created. This - * is used purely for checking the high water mark for tasks. - */ -#define tskSTACK_FILL_BYTE ( 0xa5 ) - -/* - * Macros used by vListTask to indicate which state a task is in. - */ -#define tskBLOCKED_CHAR ( ( signed portCHAR ) 'B' ) -#define tskREADY_CHAR ( ( signed portCHAR ) 'R' ) -#define tskDELETED_CHAR ( ( signed portCHAR ) 'D' ) -#define tskSUSPENDED_CHAR ( ( signed portCHAR ) 'S' ) - -/* - * Macros and private variables used by the trace facility. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - #define tskSIZE_OF_EACH_TRACE_LINE ( ( unsigned portLONG ) ( sizeof( unsigned portLONG ) + sizeof( unsigned portLONG ) ) ) - static volatile signed portCHAR * volatile pcTraceBuffer; - static signed portCHAR *pcTraceBufferStart; - static signed portCHAR *pcTraceBufferEnd; - static signed portBASE_TYPE xTracing = pdFALSE; - -#endif - -/* - * Macro that writes a trace of scheduler activity to a buffer. This trace - * shows which task is running when and is very useful as a debugging tool. - * As this macro is called each context switch it is a good idea to undefine - * it if not using the facility. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - #define vWriteTraceToBuffer() \ - { \ - if( xTracing ) \ - { \ - static unsigned portBASE_TYPE uxPreviousTask = 255; \ - \ - if( uxPreviousTask != pxCurrentTCB->uxTCBNumber ) \ - { \ - if( ( pcTraceBuffer + tskSIZE_OF_EACH_TRACE_LINE ) < pcTraceBufferEnd ) \ - { \ - uxPreviousTask = pxCurrentTCB->uxTCBNumber; \ - *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) xTickCount; \ - pcTraceBuffer += sizeof( unsigned portLONG ); \ - *( unsigned portLONG * ) pcTraceBuffer = ( unsigned portLONG ) uxPreviousTask; \ - pcTraceBuffer += sizeof( unsigned portLONG ); \ - } \ - else \ - { \ - xTracing = pdFALSE; \ - } \ - } \ - } \ - } - -#else - - #define vWriteTraceToBuffer() - -#endif - - -/* - * Place the task represented by pxTCB into the appropriate ready queue for - * the task. It is inserted at the end of the list. One quirk of this is - * that if the task being inserted is at the same priority as the currently - * executing task, then it will only be rescheduled after the currently - * executing task has been rescheduled. - */ -#define prvAddTaskToReadyQueue( pxTCB ) \ -{ \ - if( pxTCB->uxPriority > uxTopReadyPriority ) \ - { \ - uxTopReadyPriority = pxTCB->uxPriority; \ - } \ - vListInsertEnd( ( xList * ) &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ); \ -} - -/* - * Macro that looks at the list of tasks that are currently delayed to see if - * any require waking. - * - * Tasks are stored in the queue in the order of their wake time - meaning - * once one tasks has been found whose timer has not expired we need not look - * any further down the list. - */ -#define prvCheckDelayedTasks() \ -{ \ -register tskTCB *pxTCB; \ - \ - while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ) ) != NULL ) \ - { \ - if( xTickCount < listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) ) ) \ - { \ - break; \ - } \ - vListRemove( &( pxTCB->xGenericListItem ) ); \ - /* Is the task waiting on an event also? */ \ - if( pxTCB->xEventListItem.pvContainer ) \ - { \ - vListRemove( &( pxTCB->xEventListItem ) ); \ - } \ - prvAddTaskToReadyQueue( pxTCB ); \ - } \ -} - -/* - * Several functions take an xTaskHandle parameter that can optionally be NULL, - * where NULL is used to indicate that the handle of the currently executing - * task should be used in place of the parameter. This macro simply checks to - * see if the parameter is NULL and returns a pointer to the appropriate TCB. - */ -#define prvGetTCBFromHandle( pxHandle ) ( ( pxHandle == NULL ) ? ( tskTCB * ) pxCurrentTCB : ( tskTCB * ) pxHandle ) - - -/* File private functions. --------------------------------*/ - -/* - * Utility to ready a TCB for a given task. Mainly just copies the parameters - * into the TCB structure. - */ -static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ); - -/* - * Utility to ready all the lists used by the scheduler. This is called - * automatically upon the creation of the first task. - */ -static void prvInitialiseTaskLists( void ); - -/* - * The idle task, which as all tasks is implemented as a never ending loop. - * The idle task is automatically created and added to the ready lists upon - * creation of the first user task. - * - * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific - * language extensions. The equivalent prototype for this function is: - * - * void prvIdleTask( void *pvParameters ); - * - */ -static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ); - -/* - * Utility to free all memory allocated by the scheduler to hold a TCB, - * including the stack pointed to by the TCB. - * - * This does not free memory allocated by the task itself (i.e. memory - * allocated by calls to pvPortMalloc from within the tasks application code). - */ -#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) - static void prvDeleteTCB( tskTCB *pxTCB ); -#endif - -/* - * Used only by the idle task. This checks to see if anything has been placed - * in the list of tasks waiting to be deleted. If so the task is cleaned up - * and its TCB deleted. - */ -static void prvCheckTasksWaitingTermination( void ); - -/* - * Allocates memory from the heap for a TCB and associated stack. Checks the - * allocation was successful. - */ -static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ); - -/* - * Called from vTaskList. vListTasks details all the tasks currently under - * control of the scheduler. The tasks may be in one of a number of lists. - * prvListTaskWithinSingleList accepts a list and details the tasks from - * within just that list. - * - * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM - * NORMAL APPLICATION CODE. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ); - -#endif - -/* - * When a task is created, the stack of the task is filled with a known value. - * This function determines the 'high water mark' of the task stack by - * determining how much of the stack remains at the original preset value. - */ -#if ( configUSE_TRACE_FACILITY == 1 ) - - unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte ); - -#endif - -/*lint +e956 */ - - - - - -/*----------------------------------------------------------- - * TASK CREATION API documented in task.h - *----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskCreate( pdTASK_CODE pvTaskCode, const signed portCHAR * const pcName, unsigned portSHORT usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask ) -{ -signed portBASE_TYPE xReturn; -tskTCB * pxNewTCB; -static unsigned portBASE_TYPE uxTaskNumber = 0; /*lint !e956 Static is deliberate - this is guarded before use. */ - - /* Allocate the memory required by the TCB and stack for the new task. - checking that the allocation was successful. */ - pxNewTCB = prvAllocateTCBAndStack( usStackDepth ); - - if( pxNewTCB != NULL ) - { - portSTACK_TYPE *pxTopOfStack; - - /* Setup the newly allocated TCB with the initial state of the task. */ - prvInitialiseTCBVariables( pxNewTCB, usStackDepth, pcName, uxPriority ); - - /* Calculate the top of stack address. This depends on whether the - stack grows from high memory to low (as per the 80x86) or visa versa. - portSTACK_GROWTH is used to make the result positive or negative as - required by the port. */ - #if portSTACK_GROWTH < 0 - { - pxTopOfStack = pxNewTCB->pxStack + ( pxNewTCB->usStackDepth - 1 ); - } - #else - { - pxTopOfStack = pxNewTCB->pxStack; - } - #endif - - /* Initialize the TCB stack to look as if the task was already running, - but had been interrupted by the scheduler. The return address is set - to the start of the task function. Once the stack has been initialised - the top of stack variable is updated. */ - pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pvTaskCode, pvParameters ); - - /* We are going to manipulate the task queues to add this task to a - ready list, so must make sure no interrupts occur. */ - portENTER_CRITICAL(); - { - uxCurrentNumberOfTasks++; - if( uxCurrentNumberOfTasks == ( unsigned portBASE_TYPE ) 1 ) - { - /* As this is the first task it must also be the current task. */ - pxCurrentTCB = pxNewTCB; - - /* This is the first task to be created so do the preliminary - initialisation required. We will not recover if this call - fails, but we will report the failure. */ - prvInitialiseTaskLists(); - } - else - { - /* If the scheduler is not already running, make this task the - current task if it is the highest priority task to be created - so far. */ - if( xSchedulerRunning == pdFALSE ) - { - if( pxCurrentTCB->uxPriority <= uxPriority ) - { - pxCurrentTCB = pxNewTCB; - } - } - } - - /* Remember the top priority to make context switching faster. Use - the priority in pxNewTCB as this has been capped to a valid value. */ - if( pxNewTCB->uxPriority > uxTopUsedPriority ) - { - uxTopUsedPriority = pxNewTCB->uxPriority; - } - - /* Add a counter into the TCB for tracing only. */ - pxNewTCB->uxTCBNumber = uxTaskNumber; - uxTaskNumber++; - - prvAddTaskToReadyQueue( pxNewTCB ); - - xReturn = pdPASS; - } - portEXIT_CRITICAL(); - } - else - { - xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - } - - if( xReturn == pdPASS ) - { - if( ( void * ) pxCreatedTask != NULL ) - { - /* Pass the TCB out - in an anonymous way. The calling function/ - task can use this as a handle to delete the task later if - required.*/ - *pxCreatedTask = ( xTaskHandle ) pxNewTCB; - } - - if( xSchedulerRunning != pdFALSE ) - { - /* If the created task is of a higher priority than the current task - then it should run now. */ - if( pxCurrentTCB->uxPriority < uxPriority ) - { - taskYIELD(); - } - } - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelete == 1 ) - - void vTaskDelete( xTaskHandle pxTaskToDelete ) - { - tskTCB *pxTCB; - - taskENTER_CRITICAL(); - { - /* Ensure a yield is performed if the current task is being - deleted. */ - if( pxTaskToDelete == pxCurrentTCB ) - { - pxTaskToDelete = NULL; - } - - /* If null is passed in here then we are deleting ourselves. */ - pxTCB = prvGetTCBFromHandle( pxTaskToDelete ); - - /* Remove task from the ready list and place in the termination list. - This will stop the task from be scheduled. The idle task will check - the termination list and free up any memory allocated by the - scheduler for the TCB and stack. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Is the task waiting on an event also? */ - if( pxTCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - } - - vListInsertEnd( ( xList * ) &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) ); - - /* Increment the ucTasksDeleted variable so the idle task knows - there is a task that has been deleted and that it should therefore - check the xTasksWaitingTermination list. */ - ++uxTasksDeleted; - } - taskEXIT_CRITICAL(); - - /* Force a reschedule if we have just deleted the current task. */ - if( xSchedulerRunning != pdFALSE ) - { - if( ( void * ) pxTaskToDelete == NULL ) - { - taskYIELD(); - } - } - } - -#endif - - - - - - -/*----------------------------------------------------------- - * TASK CONTROL API documented in task.h - *----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelayUntil == 1 ) - - void vTaskDelayUntil( portTickType *pxPreviousWakeTime, portTickType xTimeIncrement ) - { - portTickType xTimeToWake; - portBASE_TYPE xAlreadyYielded, xShouldDelay = pdFALSE; - - vTaskSuspendAll(); - { - /* Generate the tick time at which the task wants to wake. */ - xTimeToWake = *pxPreviousWakeTime + xTimeIncrement; - - if( xTickCount < *pxPreviousWakeTime ) - { - /* The tick count has overflowed since this function was - lasted called. In this case the only time we should ever - actually delay is if the wake time has also overflowed, - and the wake time is greater than the tick time. When this - is the case it is as if neither time had overflowed. */ - if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xTickCount ) ) - { - xShouldDelay = pdTRUE; - } - } - else - { - /* The tick time has not overflowed. In this case we will - delay if either the wake time has overflowed, and/or the - tick time is less than the wake time. */ - if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xTickCount ) ) - { - xShouldDelay = pdTRUE; - } - } - - /* Update the wake time ready for the next call. */ - *pxPreviousWakeTime = xTimeToWake; - - if( xShouldDelay ) - { - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - } - xAlreadyYielded = xTaskResumeAll(); - - /* Force a reschedule if xTaskResumeAll has not already done so, we may - have put ourselves to sleep. */ - if( !xAlreadyYielded ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskDelay == 1 ) - - void vTaskDelay( portTickType xTicksToDelay ) - { - portTickType xTimeToWake; - signed portBASE_TYPE xAlreadyYielded = pdFALSE; - - /* A delay time of zero just forces a reschedule. */ - if( xTicksToDelay > ( portTickType ) 0 ) - { - vTaskSuspendAll(); - { - /* A task that is removed from the event list while the - scheduler is suspended will not get placed in the ready - list or removed from the blocked list until the scheduler - is resumed. - - This task cannot be in an event list as it is the currently - executing task. */ - - /* Calculate the time to wake - this may overflow but this is - not a problem. */ - xTimeToWake = xTickCount + xTicksToDelay; - - /* We must remove ourselves from the ready list before adding - ourselves to the blocked list as the same list item is used for - both lists. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - /* The list item will be inserted in wake time order. */ - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the - overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the - current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - } - xAlreadyYielded = xTaskResumeAll(); - } - - /* Force a reschedule if xTaskResumeAll has not already done so, we may - have put ourselves to sleep. */ - if( !xAlreadyYielded ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_uxTaskPriorityGet == 1 ) - - unsigned portBASE_TYPE uxTaskPriorityGet( xTaskHandle pxTask ) - { - tskTCB *pxTCB; - unsigned portBASE_TYPE uxReturn; - - taskENTER_CRITICAL(); - { - /* If null is passed in here then we are changing the - priority of the calling function. */ - pxTCB = prvGetTCBFromHandle( pxTask ); - uxReturn = pxTCB->uxPriority; - } - taskEXIT_CRITICAL(); - - return uxReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskPrioritySet == 1 ) - - void vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority ) - { - tskTCB *pxTCB; - unsigned portBASE_TYPE uxCurrentPriority, xYieldRequired = pdFALSE; - - /* Ensure the new priority is valid. */ - if( uxNewPriority >= configMAX_PRIORITIES ) - { - uxNewPriority = configMAX_PRIORITIES - 1; - } - - taskENTER_CRITICAL(); - { - /* If null is passed in here then we are changing the - priority of the calling function. */ - pxTCB = prvGetTCBFromHandle( pxTask ); - uxCurrentPriority = pxTCB->uxPriority; - - if( uxCurrentPriority != uxNewPriority ) - { - /* The priority change may have readied a task of higher - priority than the calling task. */ - if( uxNewPriority > pxCurrentTCB->uxPriority ) - { - if( pxTask != NULL ) - { - /* The priority of another task is being raised. If we - were raising the priority of the currently running task - there would be no need to switch as it must have already - been the highest priority task. */ - xYieldRequired = pdTRUE; - } - } - else if( pxTask == NULL ) - { - /* Setting our own priority down means there may now be another - task of higher priority that is ready to execute. */ - xYieldRequired = pdTRUE; - } - - pxTCB->uxPriority = uxNewPriority; - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxNewPriority ); - - /* If the task is in the blocked or suspended list we need do - nothing more than change it's priority variable. However, if - the task is in a ready list it needs to be removed and placed - in the queue appropriate to its new priority. */ - if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxCurrentPriority ] ), &( pxTCB->xGenericListItem ) ) ) - { - /* The task is currently in its ready list - remove before adding - it to it's new ready list. As we are in a critical section we - can do this even if the scheduler is suspended. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - } - - if( xYieldRequired == pdTRUE ) - { - taskYIELD(); - } - } - } - taskEXIT_CRITICAL(); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - void vTaskSuspend( xTaskHandle pxTaskToSuspend ) - { - tskTCB *pxTCB; - - taskENTER_CRITICAL(); - { - /* Ensure a yield is performed if the current task is being - suspended. */ - if( pxTaskToSuspend == pxCurrentTCB ) - { - pxTaskToSuspend = NULL; - } - - /* If null is passed in here then we are suspending ourselves. */ - pxTCB = prvGetTCBFromHandle( pxTaskToSuspend ); - - /* Remove task from the ready/delayed list and place in the suspended list. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - - /* Is the task waiting on an event also? */ - if( pxTCB->xEventListItem.pvContainer ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - } - - vListInsertEnd( ( xList * ) &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ); - } - taskEXIT_CRITICAL(); - - /* We may have just suspended the current task. */ - if( ( void * ) pxTaskToSuspend == NULL ) - { - taskYIELD(); - } - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_vTaskSuspend == 1 ) - - void vTaskResume( xTaskHandle pxTaskToResume ) - { - tskTCB *pxTCB; - - /* Remove the task from whichever list it is currently in, and place - it in the ready list. */ - pxTCB = ( tskTCB * ) pxTaskToResume; - - /* The parameter cannot be NULL as it is impossible to resume the - currently executing task. */ - if( pxTCB != NULL ) - { - taskENTER_CRITICAL(); - { - /* Is the task we are attempting to resume actually suspended? */ - if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE ) - { - /* Has the task already been resumed from within an ISR? */ - if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdTRUE ) - { - /* As we are in a critical section we can access the ready - lists even if the scheduler is suspended. */ - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - - /* We may have just resumed a higher priority task. */ - if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - /* This yield may not cause the task just resumed to run, but - will leave the lists in the correct state for the next yield. */ - taskYIELD(); - } - } - } - } - taskEXIT_CRITICAL(); - } - } - -#endif - -/*-----------------------------------------------------------*/ - -#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - portBASE_TYPE xTaskResumeFromISR( xTaskHandle pxTaskToResume ) - { - portBASE_TYPE xYieldRequired = pdFALSE; - tskTCB *pxTCB; - - pxTCB = ( tskTCB * ) pxTaskToResume; - - /* Is the task we are attempting to resume actually suspended? */ - if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE ) - { - /* Has the task already been resumed from within an ISR? */ - if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) != pdTRUE ) - { - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - xYieldRequired = ( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ); - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - } - else - { - /* We cannot access the delayed or ready lists, so will hold this - task pending until the scheduler is resumed, at which point a - yield will be preformed if necessary. */ - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); - } - } - } - - return xYieldRequired; - } - -#endif - - - - -/*----------------------------------------------------------- - * PUBLIC SCHEDULER CONTROL documented in task.h - *----------------------------------------------------------*/ - - -void vTaskStartScheduler( void ) -{ -portBASE_TYPE xReturn; - - /* Add the idle task at the lowest priority. */ - xReturn = xTaskCreate( prvIdleTask, ( signed portCHAR * ) "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, ( xTaskHandle * ) NULL ); - - if( xReturn == pdPASS ) - { - /* Interrupts are turned off here, to ensure a tick does not occur - before or during the call to xPortStartScheduler(). The stacks of - the created tasks contain a status word with interrupts switched on - so interrupts will automatically get re-enabled when the first task - starts to run. - - STEPPING THROUGH HERE USING A DEBUGGER CAN CAUSE BIG PROBLEMS IF THE - DEBUGGER ALLOWS INTERRUPTS TO BE PROCESSED. */ - portDISABLE_INTERRUPTS(); - - xSchedulerRunning = pdTRUE; - xTickCount = ( portTickType ) 0; - - /* Setting up the timer tick is hardware specific and thus in the - portable interface. */ - if( xPortStartScheduler() ) - { - /* Should not reach here as if the scheduler is running the - function will not return. */ - } - else - { - /* Should only reach here if a task calls xTaskEndScheduler(). */ - } - } -} -/*-----------------------------------------------------------*/ - -void vTaskEndScheduler( void ) -{ - /* Stop the scheduler interrupts and call the portable scheduler end - routine so the original ISRs can be restored if necessary. The port - layer must ensure interrupts enable bit is left in the correct state. */ - portDISABLE_INTERRUPTS(); - xSchedulerRunning = pdFALSE; - vPortEndScheduler(); -} -/*----------------------------------------------------------*/ - -void vTaskSuspendAll( void ) -{ - portENTER_CRITICAL(); - ++uxSchedulerSuspended; - portEXIT_CRITICAL(); -} -/*----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskResumeAll( void ) -{ -register tskTCB *pxTCB; -signed portBASE_TYPE xAlreadyYielded = pdFALSE; - - /* It is possible that an ISR caused a task to be removed from an event - list while the scheduler was suspended. If this was the case then the - removed task will have been added to the xPendingReadyList. Once the - scheduler has been resumed it is safe to move all the pending ready - tasks from this list into their appropriate ready list. */ - portENTER_CRITICAL(); - { - --uxSchedulerSuspended; - - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - if( uxCurrentNumberOfTasks > ( unsigned portBASE_TYPE ) 0 ) - { - portBASE_TYPE xYieldRequired = pdFALSE; - - /* Move any readied tasks from the pending list into the - appropriate ready list. */ - while( ( pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xPendingReadyList ) ) ) != NULL ) - { - vListRemove( &( pxTCB->xEventListItem ) ); - vListRemove( &( pxTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxTCB ); - - /* If we have moved a task that has a priority higher than - the current task then we should yield. */ - if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - xYieldRequired = pdTRUE; - } - } - - /* If any ticks occurred while the scheduler was suspended then - they should be processed now. This ensures the tick count does not - slip, and that any delayed tasks are resumed at the correct time. */ - if( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) - { - while( uxMissedTicks > ( unsigned portBASE_TYPE ) 0 ) - { - vTaskIncrementTick(); - --uxMissedTicks; - } - - /* As we have processed some ticks it is appropriate to yield - to ensure the highest priority task that is ready to run is - the task actually running. */ - xYieldRequired = pdTRUE; - } - - if( ( xYieldRequired == pdTRUE ) || ( xMissedYield == pdTRUE ) ) - { - xAlreadyYielded = pdTRUE; - xMissedYield = pdFALSE; - taskYIELD(); - } - } - } - } - portEXIT_CRITICAL(); - - return xAlreadyYielded; -} - - - - - - -/*----------------------------------------------------------- - * PUBLIC TASK UTILITIES documented in task.h - *----------------------------------------------------------*/ - - - -portTickType xTaskGetTickCount( void ) -{ -portTickType xTicks; - - /* Critical section required if running on a 16 bit processor. */ - taskENTER_CRITICAL(); - { - xTicks = xTickCount; - } - taskEXIT_CRITICAL(); - - return xTicks; -} -/*-----------------------------------------------------------*/ - -unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ) -{ -unsigned portBASE_TYPE uxNumberOfTasks; - - taskENTER_CRITICAL(); - uxNumberOfTasks = uxCurrentNumberOfTasks; - taskEXIT_CRITICAL(); - - return uxNumberOfTasks; -} -/*-----------------------------------------------------------*/ - -#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_vTaskDelete == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - void vTaskList( signed portCHAR *pcWriteBuffer ) - { - unsigned portBASE_TYPE uxQueue; - - /* This is a VERY costly function that should be used for debug only. - It leaves interrupts disabled for a LONG time. */ - - vTaskSuspendAll(); - { - /* Run through all the lists that could potentially contain a TCB and - report the task name, state and stack high water mark. */ - - pcWriteBuffer[ 0 ] = ( signed portCHAR ) 0x00; - strcat( ( portCHAR * ) pcWriteBuffer, ( const portCHAR * ) "\r\n" ); - - uxQueue = uxTopUsedPriority + 1; - - do - { - uxQueue--; - - if( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxQueue ] ) ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &( pxReadyTasksLists[ uxQueue ] ), tskREADY_CHAR ); - } - }while( uxQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); - - if( !listLIST_IS_EMPTY( pxDelayedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxDelayedTaskList, tskBLOCKED_CHAR ); - } - - if( !listLIST_IS_EMPTY( pxOverflowDelayedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) pxOverflowDelayedTaskList, tskBLOCKED_CHAR ); - } - - if( !listLIST_IS_EMPTY( &xTasksWaitingTermination ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xTasksWaitingTermination, tskDELETED_CHAR ); - } - - if( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) - { - prvListTaskWithinSingleList( pcWriteBuffer, ( xList * ) &xSuspendedTaskList, tskSUSPENDED_CHAR ); - } - } - xTaskResumeAll(); - } - -#endif -/*----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - void vTaskStartTrace( signed portCHAR * pcBuffer, unsigned portLONG ulBufferSize ) - { - portENTER_CRITICAL(); - { - pcTraceBuffer = ( volatile signed portCHAR * volatile )pcBuffer; - pcTraceBufferStart = pcBuffer; - pcTraceBufferEnd = pcBuffer + ( ulBufferSize - tskSIZE_OF_EACH_TRACE_LINE ); - xTracing = pdTRUE; - } - portEXIT_CRITICAL(); - } - -#endif -/*----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - unsigned portLONG ulTaskEndTrace( void ) - { - unsigned portLONG ulBufferLength; - - portENTER_CRITICAL(); - xTracing = pdFALSE; - portEXIT_CRITICAL(); - - ulBufferLength = ( unsigned portLONG ) ( pcTraceBuffer - pcTraceBufferStart ); - - return ulBufferLength; - } - -#endif - - - -/*----------------------------------------------------------- - * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES - * documented in task.h - *----------------------------------------------------------*/ - - -inline void vTaskIncrementTick( void ) -{ - /* Called by the portable layer each time a tick interrupt occurs. - Increments the tick then checks to see if the new tick value will cause any - tasks to be unblocked. */ - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - ++xTickCount; - if( xTickCount == ( portTickType ) 0 ) - { - xList *pxTemp; - - /* Tick count has overflowed so we need to swap the delay lists. - If there are any items in pxDelayedTaskList here then there is - an error! */ - pxTemp = pxDelayedTaskList; - pxDelayedTaskList = pxOverflowDelayedTaskList; - pxOverflowDelayedTaskList = pxTemp; - xNumOfOverflows++; - } - - /* See if this tick has made a timeout expire. */ - prvCheckDelayedTasks(); - } - else - { - ++uxMissedTicks; - - /* The tick hook gets called at regular intervals, even if the - scheduler is locked. */ - #if ( configUSE_TICK_HOOK == 1 ) - { - extern void vApplicationTickHook( void ); - - vApplicationTickHook(); - } - #endif - } - - #if ( configUSE_TICK_HOOK == 1 ) - { - extern void vApplicationTickHook( void ); - - /* Guard against the tick hook being called when the missed tick - count is being unwound (when the scheduler is being unlocked. */ - if( uxMissedTicks == 0 ) - { - vApplicationTickHook(); - } - } - #endif -} -/*-----------------------------------------------------------*/ - -#if ( ( INCLUDE_vTaskCleanUpResources == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) - - void vTaskCleanUpResources( void ) - { - unsigned portSHORT usQueue; - volatile tskTCB *pxTCB; - - usQueue = ( unsigned portSHORT ) uxTopUsedPriority + ( unsigned portSHORT ) 1; - - /* Remove any TCB's from the ready queues. */ - do - { - usQueue--; - - while( !listLIST_IS_EMPTY( &( pxReadyTasksLists[ usQueue ] ) ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &( pxReadyTasksLists[ usQueue ] ) ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - }while( usQueue > ( unsigned portSHORT ) tskIDLE_PRIORITY ); - - /* Remove any TCB's from the delayed queue. */ - while( !listLIST_IS_EMPTY( &xDelayedTaskList1 ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList1 ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - /* Remove any TCB's from the overflow delayed queue. */ - while( !listLIST_IS_EMPTY( &xDelayedTaskList2 ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xDelayedTaskList2 ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - while( !listLIST_IS_EMPTY( &xSuspendedTaskList ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xSuspendedTaskList ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - - while( !listLIST_IS_EMPTY( &xPendingReadyList ) ) - { - listGET_OWNER_OF_NEXT_ENTRY( pxTCB, &xPendingReadyList ); - vListRemove( ( xListItem * ) &( pxTCB->xGenericListItem ) ); - - prvDeleteTCB( ( tskTCB * ) pxTCB ); - } - } - -#endif -/*-----------------------------------------------------------*/ - -void vTaskSwitchContext( void ) -{ - if( uxSchedulerSuspended != ( unsigned portBASE_TYPE ) pdFALSE ) - { - /* The scheduler is currently suspended - do not allow a context - switch. */ - xMissedYield = pdTRUE; - return; - } - - /* Find the highest priority queue that contains ready tasks. */ - while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) ) - { - --uxTopReadyPriority; - } - - /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the tasks of the - same priority get an equal share of the processor time. */ - listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) ); - vWriteTraceToBuffer(); -} -/*-----------------------------------------------------------*/ - -void vTaskPlaceOnEventList( xList *pxEventList, portTickType xTicksToWait ) -{ -portTickType xTimeToWake; - - /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE - SCHEDULER SUSPENDED. */ - - /* Place the event list item of the TCB in the appropriate event list. - This is placed in the list in priority order so the highest priority task - is the first to be woken by the event. */ - vListInsert( ( xList * ) pxEventList, ( xListItem * ) &( pxCurrentTCB->xEventListItem ) ); - - /* Calculate the time at which the task should be woken if the event does - not occur. This may overflow but this doesn't matter. */ - xTimeToWake = xTickCount + xTicksToWait; - - /* We must remove ourselves from the ready list before adding ourselves - to the blocked list as the same list item is used for both lists. We have - exclusive access to the ready lists as the scheduler is locked. */ - vListRemove( ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - - listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake ); - - if( xTimeToWake < xTickCount ) - { - /* Wake time has overflowed. Place this item in the overflow list. */ - vListInsert( ( xList * ) pxOverflowDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } - else - { - /* The wake time has not overflowed, so we can use the current block list. */ - vListInsert( ( xList * ) pxDelayedTaskList, ( xListItem * ) &( pxCurrentTCB->xGenericListItem ) ); - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xTaskRemoveFromEventList( const xList *pxEventList ) -{ -tskTCB *pxUnblockedTCB; -portBASE_TYPE xReturn; - - /* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED OR THE - SCHEDULER SUSPENDED. It can also be called from within an ISR. */ - - /* The event list is sorted in priority order, so we can remove the - first in the list, remove the TCB from the delayed list, and add - it to the ready list. - - If an event is for a queue that is locked then this function will never - get called - the lock count on the queue will get modified instead. This - means we can always expect exclusive access to the event list here. */ - pxUnblockedTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); - vListRemove( &( pxUnblockedTCB->xEventListItem ) ); - - if( uxSchedulerSuspended == ( unsigned portBASE_TYPE ) pdFALSE ) - { - vListRemove( &( pxUnblockedTCB->xGenericListItem ) ); - prvAddTaskToReadyQueue( pxUnblockedTCB ); - } - else - { - /* We cannot access the delayed or ready lists, so will hold this - task pending until the scheduler is resumed. */ - vListInsertEnd( ( xList * ) &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); - } - - if( pxUnblockedTCB->uxPriority >= pxCurrentTCB->uxPriority ) - { - /* Return true if the task removed from the event list has - a higher priority than the calling task. This allows - the calling task to know if it should force a context - switch now. */ - xReturn = pdTRUE; - } - else - { - xReturn = pdFALSE; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vTaskSetTimeOutState( xTimeOutType *pxTimeOut ) -{ - pxTimeOut->xOverflowCount = xNumOfOverflows; - pxTimeOut->xTimeOnEntering = xTickCount; -} -/*-----------------------------------------------------------*/ - -portBASE_TYPE xTaskCheckForTimeOut( xTimeOutType *pxTimeOut, portTickType *pxTicksToWait ) -{ -portBASE_TYPE xReturn; - - if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xTickCount > pxTimeOut->xTimeOnEntering ) ) - { - /* The tick count is greater than the time at which vTaskSetTimeout() - was called, but has also overflowed since vTaskSetTimeOut() was called. - It must have wrapped all the way around and gone past us again. This - passed since vTaskSetTimeout() was called. */ - xReturn = pdTRUE; - } - else if( ( xTickCount - pxTimeOut->xTimeOnEntering ) < *pxTicksToWait ) - { - /* Not a genuine timeout. Adjust parameters for time remaining. */ - *pxTicksToWait -= ( xTickCount - pxTimeOut->xTimeOnEntering ); - vTaskSetTimeOutState( pxTimeOut ); - xReturn = pdFALSE; - } - else - { - xReturn = pdTRUE; - } - - return xReturn; -} -/*-----------------------------------------------------------*/ - -void vTaskMissedYield( void ) -{ - xMissedYield = pdTRUE; -} - -/* - * ----------------------------------------------------------- - * The Idle task. - * ---------------------------------------------------------- - * - * The portTASK_FUNCTION() macro is used to allow port/compiler specific - * language extensions. The equivalent prototype for this function is: - * - * void prvIdleTask( void *pvParameters ); - * - */ -static portTASK_FUNCTION( prvIdleTask, pvParameters ) -{ - /* Stop warnings. */ - ( void ) pvParameters; - - for( ;; ) - { - /* See if any tasks have been deleted. */ - prvCheckTasksWaitingTermination(); - - #if ( configUSE_PREEMPTION == 0 ) - { - /* If we are not using preemption we keep forcing a task switch to - see if any other task has become available. If we are using - preemption we don't need to do this as any task becoming available - will automatically get the processor anyway. */ - taskYIELD(); - } - #endif - - #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) - { - /* When using preemption tasks of equal priority will be - timesliced. If a task that is sharing the idle priority is ready - to run then the idle task should yield before the end of the - timeslice. - - A critical region is not required here as we are just reading from - the list, and an occasional incorrect value will not matter. If - the ready list at the idle priority contains more than one task - then a task other than the idle task is ready to execute. */ - if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( unsigned portBASE_TYPE ) 1 ) - { - taskYIELD(); - } - } - #endif - - #if ( configUSE_IDLE_HOOK == 1 ) - { - extern void vApplicationIdleHook( void ); - - /* Call the user defined function from within the idle task. This - allows the application designer to add background functionality - without the overhead of a separate task. - NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, - CALL A FUNCTION THAT MIGHT BLOCK. */ - vApplicationIdleHook(); - } - #endif - } -} /*lint !e715 pvParameters is not accessed but all task functions require the same prototype. */ - - - - - - - -/*----------------------------------------------------------- - * File private functions documented at the top of the file. - *----------------------------------------------------------*/ - - - -static void prvInitialiseTCBVariables( tskTCB *pxTCB, unsigned portSHORT usStackDepth, const signed portCHAR * const pcName, unsigned portBASE_TYPE uxPriority ) -{ - pxTCB->usStackDepth = usStackDepth; - - /* Store the function name in the TCB. */ - strncpy( ( char * ) pxTCB->pcTaskName, ( const char * ) pcName, ( unsigned portSHORT ) configMAX_TASK_NAME_LEN ); - pxTCB->pcTaskName[ ( unsigned portSHORT ) configMAX_TASK_NAME_LEN - ( unsigned portSHORT ) 1 ] = '\0'; - - /* This is used as an array index so must ensure it's not too large. */ - if( uxPriority >= configMAX_PRIORITIES ) - { - uxPriority = configMAX_PRIORITIES - 1; - } - - pxTCB->uxPriority = uxPriority; - - vListInitialiseItem( &( pxTCB->xGenericListItem ) ); - vListInitialiseItem( &( pxTCB->xEventListItem ) ); - - /* Set the pxTCB as a link back from the xListItem. This is so we can get - back to the containing TCB from a generic item in a list. */ - listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB ); - - /* Event lists are always in priority order. */ - listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), configMAX_PRIORITIES - ( portTickType ) uxPriority ); - listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB ); -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseTaskLists( void ) -{ -unsigned portBASE_TYPE uxPriority; - - for( uxPriority = 0; uxPriority < configMAX_PRIORITIES; uxPriority++ ) - { - vListInitialise( ( xList * ) &( pxReadyTasksLists[ uxPriority ] ) ); - } - - vListInitialise( ( xList * ) &xDelayedTaskList1 ); - vListInitialise( ( xList * ) &xDelayedTaskList2 ); - vListInitialise( ( xList * ) &xPendingReadyList ); - - #if ( INCLUDE_vTaskDelete == 1 ) - { - vListInitialise( ( xList * ) &xTasksWaitingTermination ); - } - #endif - - #if ( INCLUDE_vTaskSuspend == 1 ) - { - vListInitialise( ( xList * ) &xSuspendedTaskList ); - } - #endif - - /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList - using list2. */ - pxDelayedTaskList = &xDelayedTaskList1; - pxOverflowDelayedTaskList = &xDelayedTaskList2; -} -/*-----------------------------------------------------------*/ - -static void prvCheckTasksWaitingTermination( void ) -{ - #if ( INCLUDE_vTaskDelete == 1 ) - { - portBASE_TYPE xListIsEmpty; - - /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called - too often in the idle task. */ - if( uxTasksDeleted > ( unsigned portBASE_TYPE ) 0 ) - { - vTaskSuspendAll(); - xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination ); - xTaskResumeAll(); - - if( !xListIsEmpty ) - { - tskTCB *pxTCB; - - portENTER_CRITICAL(); - { - pxTCB = ( tskTCB * ) listGET_OWNER_OF_HEAD_ENTRY( ( ( xList * ) &xTasksWaitingTermination ) ); - vListRemove( &( pxTCB->xGenericListItem ) ); - --uxCurrentNumberOfTasks; - --uxTasksDeleted; - } - portEXIT_CRITICAL(); - - prvDeleteTCB( pxTCB ); - } - } - } - #endif -} -/*-----------------------------------------------------------*/ - -static tskTCB *prvAllocateTCBAndStack( unsigned portSHORT usStackDepth ) -{ -tskTCB *pxNewTCB; - - /* Allocate space for the TCB. Where the memory comes from depends on - the implementation of the port malloc function. */ - pxNewTCB = ( tskTCB * ) pvPortMalloc( sizeof( tskTCB ) ); - - if( pxNewTCB != NULL ) - { - /* Allocate space for the stack used by the task being created. - The base of the stack memory stored in the TCB so the task can - be deleted later if required. */ - pxNewTCB->pxStack = ( portSTACK_TYPE * ) pvPortMalloc( ( ( size_t )usStackDepth ) * sizeof( portSTACK_TYPE ) ); - - if( pxNewTCB->pxStack == NULL ) - { - /* Could not allocate the stack. Delete the allocated TCB. */ - vPortFree( pxNewTCB ); - pxNewTCB = NULL; - } - else - { - /* Just to help debugging. */ - memset( pxNewTCB->pxStack, tskSTACK_FILL_BYTE, usStackDepth * sizeof( portSTACK_TYPE ) ); - } - } - - return pxNewTCB; -} -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - static void prvListTaskWithinSingleList( signed portCHAR *pcWriteBuffer, xList *pxList, signed portCHAR cStatus ) - { - volatile tskTCB *pxNextTCB, *pxFirstTCB; - static portCHAR pcStatusString[ 50 ]; - unsigned portSHORT usStackRemaining; - - /* Write the details of all the TCB's in pxList into the buffer. */ - listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); - do - { - listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); - usStackRemaining = usTaskCheckFreeStackSpace( ( unsigned portCHAR * ) pxNextTCB->pxStack ); - sprintf( pcStatusString, ( portCHAR * ) "%s\t\t%c\t%u\t%u\t%u\r\n", pxNextTCB->pcTaskName, cStatus, ( unsigned int ) pxNextTCB->uxPriority, usStackRemaining, ( unsigned int ) pxNextTCB->uxTCBNumber ); - strcat( ( portCHAR * ) pcWriteBuffer, ( portCHAR * ) pcStatusString ); - - } while( pxNextTCB != pxFirstTCB ); - } - -#endif -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - unsigned portSHORT usTaskCheckFreeStackSpace( const unsigned portCHAR *pucStackByte ) - { - register unsigned portSHORT usCount = 0; - - while( *pucStackByte == tskSTACK_FILL_BYTE ) - { - pucStackByte -= portSTACK_GROWTH; - usCount++; - } - - usCount /= sizeof( portSTACK_TYPE ); - - return usCount; - } -#endif -/*-----------------------------------------------------------*/ - - - -#if ( ( INCLUDE_vTaskDelete == 1 ) || ( INCLUDE_vTaskCleanUpResources == 1 ) ) - - static void prvDeleteTCB( tskTCB *pxTCB ) - { - /* Free up the memory allocated by the scheduler for the task. It is up to - the task to free any memory allocated at the application level. */ - vPortFree( pxTCB->pxStack ); - vPortFree( pxTCB ); - } - -#endif - - -/*-----------------------------------------------------------*/ - -#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) - - xTaskHandle xTaskGetCurrentTaskHandle( void ) - { - xTaskHandle xReturn; - - portENTER_CRITICAL(); - { - xReturn = ( xTaskHandle ) pxCurrentTCB; - } - portEXIT_CRITICAL(); - - return xReturn; - } - -#endif - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/71x_lib.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/71x_lib.c deleted file mode 100644 index a161fc2d6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/71x_lib.c +++ /dev/null @@ -1,158 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_lib.c -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Peripherals pointers initialization -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#define EXT - -#include "71x_map.h" - -#ifdef LIBDEBUG - -extern u32 T0TIMI_Addr; - -/******************************************************************************* -* Function Name : debug -* Description : Initialize the pointers to peripherals -* Input : none -* Output : none -* Return : none -*******************************************************************************/ -void libdebug(void) -{ - #ifdef _ADC12 - ADC12 = (ADC12_TypeDef *)ADC12_BASE; - #endif - - #ifdef _APB - #ifdef _APB1 - APB1 = (APB_TypeDef *)(APB1_BASE+0x10); - #endif - #ifdef _APB2 - APB2 = (APB_TypeDef *)(APB2_BASE+0x10); - #endif - #endif - - #ifdef _BSPI - #ifdef _BSPI0 - BSPI0 = (BSPI_TypeDef *)BSPI0_BASE; - #endif - #ifdef _BSPI1 - BSPI1 = (BSPI_TypeDef *)BSPI1_BASE; - #endif - #endif - - #ifdef _CAN - CAN = (CAN_TypeDef *)CAN_BASE; - #endif - - #ifdef _EIC - EIC = (EIC_TypeDef *)EIC_BASE; - #endif - - #ifdef _EMI - EMI = (EMI_TypeDef *)EMI_BASE; - #endif - - #ifdef _FLASH - FLASHR = (FLASHR_TypeDef *)FLASHR_BASE; - FLASHPR = (FLASHPR_TypeDef *)FLASHPR_BASE; - #endif - - #ifdef _GPIO - #ifdef _GPIO0 - GPIO0 = (GPIO_TypeDef *)GPIO0_BASE; - #endif - #ifdef _GPIO1 - GPIO1 = (GPIO_TypeDef *)GPIO1_BASE; - #endif - #ifdef _GPIO2 - GPIO2 = (GPIO_TypeDef *)GPIO2_BASE; - #endif - #endif - - #ifdef _I2C - #ifdef _I2C0 - I2C0 = (I2C_TypeDef *)I2C0_BASE; - #endif - #ifdef _I2C1 - I2C1 = (I2C_TypeDef *)I2C1_BASE; - #endif - #endif - - #ifdef _PCU - PCU = (PCU_TypeDef *)PCU_BASE; - #endif - - #ifdef _RCCU - RCCU = (RCCU_TypeDef *)RCCU_BASE; - #endif - - #ifdef _RTC - RTC = (RTC_TypeDef *)RTC_BASE; - #endif - - #ifdef _TIM - #ifdef _TIM0 - TIM0 = (TIM_TypeDef *)TIM0_BASE; - #endif - #ifdef _TIM1 - TIM1 = (TIM_TypeDef *)TIM1_BASE; - #endif - #ifdef _TIM2 - TIM2 = (TIM_TypeDef *)TIM2_BASE; - #endif - #ifdef _TIM3 - TIM3 = (TIM_TypeDef *)TIM3_BASE; - #endif - #endif - - #ifdef _UART - #ifdef _UART0 - UART0 = (UART_TypeDef *)UART0_BASE; - #endif - #ifdef _UART1 - UART1 = (UART_TypeDef *)UART1_BASE; - #endif - #ifdef _UART2 - UART2 = (UART_TypeDef *)UART2_BASE; - #endif - #ifdef _UART3 - UART3 = (UART_TypeDef *)UART3_BASE; - #endif - #endif - - #ifdef _USB - USB = (USB_TypeDef *)USB_BASE; - #endif - - #ifdef _WDG - WDG = (WDG_TypeDef *)WDG_BASE; - #endif - - #ifdef _XTI - XTI = (XTI_TypeDef *)XTI_BASE; - #endif - - #ifdef _IRQVectors - IRQVectors = (IRQVectors_TypeDef *)&T0TIMI_Addr; - #endif -} - -#endif /* LIBDEBUG */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/adc12.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/adc12.c deleted file mode 100644 index a300fa35a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/adc12.c +++ /dev/null @@ -1,79 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : adc12.c -* Author : MCD Application Team -* Date First Issued : 07/31/2003 -* Description : Code sources of ADC12 functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#include "adc12.h" - -/******************************************************************************* -* Function Name : ADC12_Init -* Description : Initialize the ADC -* Input : None. -* Return : None. -*******************************************************************************/ -void ADC12_Init(void) -{ - //Initiate ADC12 registers to their reset values - ADC12->CSR = 0x00; - ADC12->CPR = 0x01; -} - -/******************************************************************************* -* Function Name : ADC12_PrescalerConfig -* Description : Configure the prescaler -* Input : None. -* Return : None. -*******************************************************************************/ -void ADC12_PrescalerConfig(u32 Adc12_clk) -{ - //Update the Prescaler Register - ADC12->CPR = (vu16) (RCCU_FrequencyValue(RCCU_PCLK)/(Adc12_clk*512*8)); -} - -/******************************************************************************* -* Function Name : ADC12_ITConfig -* Description : enable or disable the interrupt -* Input : status=ENABLE=>enable interrupt -* status=DISABLE=>disable interrupt -* Return : None -*******************************************************************************/ -void ADC12_ITConfig(FunctionalState NewState) -{ - if (NewState == ENABLE) - { - // Test the conversion mode - if (ADC12->CSR & 0x0040) - { - // Set interrupt bit equivalent to the channel selected - switch (ADC12->CSR & 0x30) - { - case 0x00 : ADC12->CSR |= ADC12_IT0_Mask; break; - case 0x10 : ADC12->CSR |= ADC12_IT1_Mask; break; - case 0x20 : ADC12->CSR |= ADC12_IT2_Mask; break; - case 0x30 : ADC12->CSR |= ADC12_IT3_Mask; break; - } - } - else - // Set all interrupt bits in case of round robin mode - ADC12->CSR |= ADC12_IT_Mask; - } - else - // Clear all interrupt bits - ADC12->CSR &= ~ADC12_IT_Mask; -} -/*********************(c) 2003 STMicroelectronics********************* END OF FILE **/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/apb.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/apb.c deleted file mode 100644 index ec171401c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/apb.c +++ /dev/null @@ -1,24 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : apb.c -* Author : MCD Application Team -* Date First Issued : 05/30/2003 -* Description : This file provides all the APB software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "apb.h" - - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/bspi.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/bspi.c deleted file mode 100644 index acbe34181..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/bspi.c +++ /dev/null @@ -1,171 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : bspi.c -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : This file provides all the BSPI software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "bspi.h" - -/******************************************************************************* -* Function Name : BSPI_Init -* Description : Initializes BSPI peripheral control and registers to their default reset values. -* Input : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Output : BSPI peripheral registers and BSPI global variables are initialized. -* Return : None. -*******************************************************************************/ -void BSPI_Init(BSPI_TypeDef *BSPIx) -{ - BSPIx->CSR2 = 0x41; - BSPIx->CSR1 = 0x00; - BSPIx->CLK = 0x06; -} - -/******************************************************************************* -* Function Name : BSPI_TrItSrc. -* Description : Configures the transmit interrupt source. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : TrItSrc: specifies the transmit interrupt source. -* : Refer to the section Transmit Interrupt Sources for more details on the -* : allowed values of this parameter. -* Output : TIE bit in BSPCSR2 register. -* Return : None. -*******************************************************************************/ -void BSPI_TrItSrc(BSPI_TypeDef *BSPIx, BSPI_TR_IT_SRCS TrItSrc) -{ - switch (TrItSrc) - { - case BSPI_TR_DIS: - BSPIx->CSR2 &= ~0xC000; - break; - case BSPI_TR_FE: - BSPIx->CSR2 &= ~0x8000; - BSPIx->CSR2 |= 0x4000; - break; - case BSPI_TR_UFL: - BSPIx->CSR2 &= ~0x4000; - BSPIx->CSR2 |= 0x8000; - break; - case BSPI_TR_FF: - BSPIx->CSR2 |= 0xC000; - break; - } -} - -/******************************************************************************* -* Function Name : BSPI_RcItSrc. -* Description : Configures the receive interrupt source. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : RcItSrc: specifies the source for the receive interrupt. -* : Refer to the section Receive Interrupt Sources for more details on the -* : allowed values of this parameter. -* Output : RIE bit in BSPCSR1 is register. -* Return : None. -*******************************************************************************/ -void BSPI_RcItSrc(BSPI_TypeDef *BSPIx, BSPI_RC_IR_SRCS RcItSrc) -{ - switch (RcItSrc) - { - case BSPI_RC_DIS: - BSPIx->CSR1 &= ~0x000C; - break; - case BSPI_RC_FNE: - BSPIx->CSR1 &= ~0x0008; - BSPIx->CSR1 |= 0x0004; - break; - case BSPI_RC_FF: - BSPIx->CSR1 |= 0x000C; - break; - } -} - -/******************************************************************************* -* Function Name : BSPI_TrFifoDepth -* Description : Configures BSPI transmission FIFO number of words. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI. -* Input 2 : TDepth:specifies the depth of the transmit FIFO. -* Output : TFE bit in BSPCSR2 register. -* Return : None. -*******************************************************************************/ -void BSPI_TrFifoDepth(BSPI_TypeDef *BSPIx, u8 TDepth) -{ - if (TDepth > 0 && TDepth < 11) - { - TDepth--; - BSPIx->CSR2 &= (TDepth*0x400) | ~0x3C00; - BSPIx->CSR2 |= TDepth*0x400; - } - else BSPIx->CSR2 &= ~0x3C00; -} - -/******************************************************************************* -* Function Name : BSPI_RcFifoDepth -* Description : Configures BSPI reception FIFO number of words. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : RDepth:specifies the depth of the receive FIFO. -* Output : RFE bits [3:0] in BSPCSR1 register. -* Return : None. -*******************************************************************************/ -void BSPI_RcFifoDepth(BSPI_TypeDef *BSPIx, u8 RDepth) -{ - if (RDepth > 0 && RDepth < 11) - { - RDepth--; - BSPIx->CSR1 &= (RDepth*0x1000) | ~0xF000; - BSPIx->CSR1 |= RDepth*0x1000; - } - else BSPIx->CSR1 &= ~0xF000; -} - -/******************************************************************************* -* Function Name : BSPI_BufferSend. -* Description : Transmits data from a buffer. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : PtrToBuffer is an u8 pointer to the first word of the buffer to be transmitted. -* Input 3 : NbOfWords parameter indicates the number of words saved in the buffer to be sent. -* Output : None. -* Return : None. -*******************************************************************************/ -void BSPI_BufferSend(BSPI_TypeDef *BSPIx, u8 *PtrToBuffer, u8 NbOfWords) -{ - vu8 SendWord = 0; - while (SendWord < NbOfWords) - { - BSPI_WordSend(BSPIx, *(PtrToBuffer+SendWord)); - SendWord++; - } -} - -/******************************************************************************* -* Function Name : BSPI_BufferReceive. -* Description : Receives number of data words and stores them in user defined area. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : PtrToBuffer is an u8 pointer to the first word of the defined area to save the received buffer. -* Input 3 : NbOfWords parameter indicates the number of words to be received in the buffer. -* Output : None. -* Return : None. -*******************************************************************************/ -void BSPI_BufferReceive(BSPI_TypeDef *BSPIx, u8 *PtrToBuffer, u8 NbOfWords) -{ - vu16 ReceiveWord = 0; - while (ReceiveWord < NbOfWords) - { - *(PtrToBuffer+ReceiveWord) = BSPI_WordReceive(BSPIx); - ReceiveWord++; - } -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/can.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/can.c deleted file mode 100644 index 48d491c83..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/can.c +++ /dev/null @@ -1,541 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : can.c -* Author : MCD Application Team -* Date First Issued : 10/27/2003 -* Description : This file contains all the functions prototypes for the -* CAN bus software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "can.h" -#include "xti.h" -#include "pcu.h" - -// macro to format the timing register value from the timing parameters -#define CAN_TIMING(tseg1, tseg2, sjw, brp) (((tseg2-1) & 0x07) << 12) | (((tseg1-1) & 0x0F) << 8) | (((sjw-1) & 0x03) << 6) | ((brp-1) & 0x3F) - -// array of pre-defined timing parameters for standard bitrates -u16 CanTimings[] = { // value bitrate NTQ TSEG1 TSEG2 SJW BRP - CAN_TIMING(11, 4, 4, 5), // 0x3AC4 100 kbit/s 16 11 4 4 5 - CAN_TIMING(11, 4, 4, 4), // 0x3AC3 125 kbit/s 16 11 4 4 4 - CAN_TIMING( 4, 3, 3, 4), // 0x2383 250 kbit/s 8 4 3 3 4 - CAN_TIMING(13, 2, 1, 1), // 0x1C00 500 kbit/s 16 13 2 1 1 - CAN_TIMING( 4, 3, 1, 1), // 0x2300 1 Mbit/s 8 4 3 1 1 -}; - -/******************************************************************************* -* Function Name : CAN_SetBitrate -* Description : Setup a standard CAN bitrate -* Input 1 : one of the CAN_BITRATE_xxx defines -* Output : None -* Return : None -* Note : CAN must be in initialization mode -*******************************************************************************/ -void CAN_SetBitrate(u32 bitrate) -{ - CAN->BTR = CanTimings[bitrate]; // write the predefined timing value - CAN->BRPR = 0; // clear the Extended Baud Rate Prescaler -} - -/******************************************************************************* -* Function Name : CAN_SetTiming -* Description : Setup the CAN timing with specific parameters -* Input 1 : Time Segment before the sample point position, from 1 to 16 -* Input 2 : Time Segment after the sample point position, from 1 to 8 -* Input 3 : Synchronisation Jump Width, from 1 to 4 -* Input 4 : Baud Rate Prescaler, from 1 to 1024 -* Output : None -* Return : None -* Note : CAN must be in initialization mode -*******************************************************************************/ -void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp) -{ - CAN->BTR = CAN_TIMING(tseg1, tseg2, sjw, brp); - CAN->BRPR = ((brp-1) >> 6) & 0x0F; -} - -/******************************************************************************* -* Function Name : CAN_SleepRequest -* Description : Request the CAN cell to enter sleep mode -* Input 1 : CAN_WAKEUP_ON_EXT or CAN_WAKEUP_ON_CAN -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SleepRequest(u32 WakeupMode) -{ - // Wakeup Line 6 is linked to CAN RX pin (port 1.11) - // Wakeup Line 2 is linked to external pin (port 2.8) - u32 WakeupLine = (WakeupMode == CAN_WAKEUP_ON_CAN ? XTI_Line6 : XTI_Line2); - - CAN_WaitEndOfTx(); - - XTI_Init(); - - // Configure the Wakeup Line mode, select Falling edge (transition to dominant state) - XTI_LineModeConfig(WakeupLine, XTI_FallingEdge); - - // Enable Wake-Up interrupt - XTI_LineConfig(WakeupLine, ENABLE); - - // Enable Wake-Up mode with interrupt - XTI_ModeConfig(XTI_WakeUpInterrupt, ENABLE); - - XTI_PendingBitClear(XTI_InterruptLineValue()); - - // Enter STOP mode (resume execution from here) - PCU_LPMEnter(PCU_STOP); -} - -/******************************************************************************* -* Function Name : CAN_GetFreeIF -* Description : Search the first free message interface, starting from 0 -* Input : None -* Output : None -* Return : A free message interface number (0 or 1) if found, else 2 -*******************************************************************************/ -static u32 CAN_GetFreeIF(void) -{ - if ((CAN->sMsgObj[0].CRR & CAN_CRR_BUSY) == 0) - return 0; - else if ((CAN->sMsgObj[1].CRR & CAN_CRR_BUSY) == 0) - return 1; - else return 2; -} - -/******************************************************************************* -* Macro Name : xxx_ID_MSK, xxx_ID_ARB -* Description : Form the Mask and Arbitration registers value to filter a range -* of identifiers or a fixed identifier, for standard and extended IDs -*******************************************************************************/ -#define RANGE_ID_MSK(range_start, range_end) (~((range_end) - (range_start))) -#define RANGE_ID_ARB(range_start, range_end) ((range_start) & (range_end)) - -#define FIXED_ID_MSK(id) RANGE_ID_MSK((id), (id)) -#define FIXED_ID_ARB(id) RANGE_ID_ARB((id), (id)) - -#define STD_RANGE_ID_MSK(range_start, range_end) ((u16)((RANGE_ID_MSK((range_start), (range_end)) & 0x7FF) << 2)) -#define STD_RANGE_ID_ARB(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) << 2)) - -#define STD_FIXED_ID_MSK(id) ((u16)((FIXED_ID_MSK(id) & 0x7FF) << 2)) -#define STD_FIXED_ID_ARB(id) ((u16)(FIXED_ID_ARB(id) << 2)) - -#define EXT_RANGE_ID_MSK_L(range_start, range_end) ((u16)(RANGE_ID_MSK((range_start), (range_end)) >> 11)) -#define EXT_RANGE_ID_MSK_H(range_start, range_end) ((u16)(STD_RANGE_ID_MSK((range_start), (range_end)) | ((RANGE_ID_MSK((range_start), (range_end)) >> 27) & 0x03))) -#define EXT_RANGE_ID_ARB_L(range_start, range_end) ((u16)(RANGE_ID_ARB((range_start), (range_end)) >> 11)) -#define EXT_RANGE_ID_ARB_H(range_start, range_end) ((u16)(STD_RANGE_ID_ARB((range_start), (range_end)) | ((RANGE_ID_ARB((range_start), (range_end)) >> 27) & 0x03))) - -#define EXT_FIXED_ID_MSK_L(id) ((u16)(FIXED_ID_MSK(id) >> 11)) -#define EXT_FIXED_ID_MSK_H(id) ((u16)(STD_FIXED_ID_MSK(id) | ((FIXED_ID_MSK(id) >> 27) & 0x03))) -#define EXT_FIXED_ID_ARB_L(id) ((u16)(FIXED_ID_ARB(id) >> 11)) -#define EXT_FIXED_ID_ARB_H(id) ((u16)(STD_FIXED_ID_ARB(id) | ((FIXED_ID_ARB(id) >> 27) & 0x03))) - -/******************************************************************************* -* Function Name : CAN_SetUnusedMsgObj -* Description : Configure the message object as unused -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetUnusedMsgObj(u32 msgobj) -{ - u32 msg_if; - while ((msg_if = CAN_GetFreeIF()) == 2); - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].M2R = 0; - - CAN->sMsgObj[msg_if].A1R = 0; - CAN->sMsgObj[msg_if].A2R = 0; - - CAN->sMsgObj[msg_if].MCR = 0; - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_SetTxMsgObj -* Description : Configure the message object as TX -* Input 1 : message object number, from 0 to 31 -* Input 2 : CAN_STD_ID or CAN_EXT_ID -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetTxMsgObj(u32 msgobj, u32 idType) -{ - u32 msg_if; - while ((msg_if = CAN_GetFreeIF()) == 2); - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].A1R = 0; - - if (idType == CAN_STD_ID) - { - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR; - } - else - { - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MDIR | CAN_M2R_MXTD; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_DIR | CAN_A2R_XTD; - } - - CAN->sMsgObj[msg_if].MCR = CAN_MCR_TXIE | CAN_MCR_EOB; - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_SetRxMsgObj -* Description : Configure the message object as RX -* Input 1 : message object number, from 0 to 31 -* Input 2 : CAN_STD_ID or CAN_EXT_ID -* Input 3 : low part of the identifier range used for acceptance filtering -* Input 4 : high part of the identifier range used for acceptance filtering -* Input 5 : TRUE for a single receive object or a FIFO receive object that -* is the last one of the FIFO -* FALSE for a FIFO receive object that is not the last one -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast) -{ - u32 msg_if; - while ((msg_if = CAN_GetFreeIF()) == 2); - - CAN->sMsgObj[msg_if].CMR = CAN_CMR_WRRD - | CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if (idType == CAN_STD_ID) - { - CAN->sMsgObj[msg_if].M1R = 0; - CAN->sMsgObj[msg_if].M2R = STD_RANGE_ID_MSK(idLow, idHigh); - - CAN->sMsgObj[msg_if].A1R = 0; - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | STD_RANGE_ID_ARB(idLow, idHigh); - } - else - { - CAN->sMsgObj[msg_if].M1R = EXT_RANGE_ID_MSK_L(idLow, idHigh); - CAN->sMsgObj[msg_if].M2R = CAN_M2R_MXTD | EXT_RANGE_ID_MSK_H(idLow, idHigh); - - CAN->sMsgObj[msg_if].A1R = EXT_RANGE_ID_ARB_L(idLow, idHigh); - CAN->sMsgObj[msg_if].A2R = CAN_A2R_MSGVAL | CAN_A2R_XTD | EXT_RANGE_ID_ARB_H(idLow, idHigh); - } - - CAN->sMsgObj[msg_if].MCR = CAN_MCR_RXIE | CAN_MCR_UMASK | (singleOrFifoLast ? CAN_MCR_EOB : 0); - - CAN->sMsgObj[msg_if].DA1R = 0; - CAN->sMsgObj[msg_if].DA2R = 0; - CAN->sMsgObj[msg_if].DB1R = 0; - CAN->sMsgObj[msg_if].DB2R = 0; - - CAN->sMsgObj[msg_if].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_InvalidateAllMsgObj -* Description : Configure all the message objects as unused -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_InvalidateAllMsgObj(void) -{ - u32 i; - for (i = 0; i < 32; i++) - CAN_SetUnusedMsgObj(i); -} - -/******************************************************************************* -* Function Name : CAN_Init -* Description : Initialize the CAN cell and set the bitrate -* Input 1 : any binary value formed from the CAN_CTL_xxx defines -* Input 2 : one of the CAN_BITRATE_xxx defines -* Output : None -* Return : None -*******************************************************************************/ -void CAN_Init(u8 mask, u32 bitrate) -{ - CAN_EnterInitMode(CAN_CR_CCE | mask); - CAN_SetBitrate(bitrate); - CAN_LeaveInitMode(); - CAN_LeaveTestMode(); -} - -/******************************************************************************* -* Function Name : CAN_ReleaseMessage -* Description : Release the message object -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -*******************************************************************************/ -void CAN_ReleaseMessage(u32 msgobj) -{ - u32 i; - while ((i = CAN_GetFreeIF()) == 2); - - CAN->sMsgObj[i].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQST; - CAN->sMsgObj[i].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_SendMessage -* Description : Start transmission of a message -* Input 1 : message object number, from 0 to 31 -* Input 2 : pointer to the message structure containing data to transmit -* Output : None -* Return : 1 if transmission was OK, else 0 -*******************************************************************************/ -u32 CAN_SendMessage(u32 msgobj, canmsg* pCanMsg) -{ - while (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY); - -// if (CAN->sMsgObj[0].COMR & CAN_CRQ_BUSY) -// return 0; // message interface 0 not free - - CAN->SR &= ~CAN_SR_TXOK; - - // read the Arbitration and Message Control - CAN->sMsgObj[0].CMR = CAN_CMR_ARB | CAN_CMR_CONTROL; - - CAN->sMsgObj[0].CRR = 1 + msgobj; - - while (CAN->sMsgObj[0].CRR & CAN_CRR_BUSY); - - // update the contents needed for transmission - CAN->sMsgObj[0].CMR = CAN_CMR_WRRD - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if ((CAN->sMsgObj[0].A2R & CAN_A2R_XTD) == 0) - { - // standard ID - CAN->sMsgObj[0].A1R = 0; - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); - } - else - { - // extended ID - CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); - } - - CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFEF0) | CAN_MCR_NEWDAT | CAN_MCR_TXRQST | pCanMsg->Dlc; - - CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; - CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; - CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; - CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; - - CAN->sMsgObj[0].CRR = 1 + msgobj; - - return 1; -} - -/******************************************************************************* -* Function Name : CAN_ReceiveMessage -* Description : Get the message, if received -* Input 1 : message object number, from 0 to 31 -* Input 2 : if TRUE, the message object is released when getting the data -* if FALSE, the message object is not released -* Input 3 : pointer to the message structure where received data is stored -* Output : None -* Return : 1 if reception was OK, else 0 (no message pending) -*******************************************************************************/ -u32 CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg) -{ - if (!CAN_IsMessageWaiting(msgobj)) - return 0; - - CAN->SR &= ~CAN_SR_RXOK; - - // read the message contents - CAN->sMsgObj[1].CMR = CAN_CMR_MASK - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_CLRINTPND - | (release ? CAN_CMR_TXRQST : 0) - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - CAN->sMsgObj[1].CRR = 1 + msgobj; - - while (CAN->sMsgObj[1].CRR & CAN_CRR_BUSY); - - if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) - { - // standard ID - pCanMsg->IdType = CAN_STD_ID; - pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; - } - else - { - // extended ID - pCanMsg->IdType = CAN_EXT_ID; - pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF) | ((u32)CAN->sMsgObj[1].A1R << 11) | (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); - } - - pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; - - pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; - pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); - pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; - pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); - pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; - pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); - pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; - pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); - - return 1; -} - -/******************************************************************************* -* Function Name : CAN_WaitEndOfTx -* Description : Wait until current transmission is finished -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_WaitEndOfTx(void) -{ - while ((CAN->SR & CAN_SR_TXOK) == 0); - CAN->SR &= ~CAN_SR_TXOK; -} - -/******************************************************************************* -* Function Name : CAN_BasicSendMessage -* Description : Start transmission of a message in BASIC mode -* Input 1 : pointer to the message structure containing data to transmit -* Output : None -* Return : 1 if transmission was OK, else 0 -* Note : CAN must be in BASIC mode -*******************************************************************************/ -u32 CAN_BasicSendMessage(canmsg* pCanMsg) -{ - // clear NewDat bit in IF2 to detect next reception - CAN->sMsgObj[1].MCR &= ~CAN_MCR_NEWDAT; - - CAN->SR &= ~CAN_SR_TXOK; - - CAN->sMsgObj[0].CMR = CAN_CMR_WRRD - | CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if (pCanMsg->IdType == CAN_STD_ID) - { - // standard ID - CAN->sMsgObj[0].A1R = 0; - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | STD_FIXED_ID_ARB(pCanMsg->Id); - } - else - { - // extended ID - CAN->sMsgObj[0].A1R = EXT_FIXED_ID_ARB_L(pCanMsg->Id); - CAN->sMsgObj[0].A2R = (CAN->sMsgObj[0].A2R & 0xE000) | EXT_FIXED_ID_ARB_H(pCanMsg->Id); - } - - CAN->sMsgObj[0].MCR = (CAN->sMsgObj[0].MCR & 0xFCF0) | pCanMsg->Dlc; - - CAN->sMsgObj[0].DA1R = ((u16)pCanMsg->Data[1]<<8) | pCanMsg->Data[0]; - CAN->sMsgObj[0].DA2R = ((u16)pCanMsg->Data[3]<<8) | pCanMsg->Data[2]; - CAN->sMsgObj[0].DB1R = ((u16)pCanMsg->Data[5]<<8) | pCanMsg->Data[4]; - CAN->sMsgObj[0].DB2R = ((u16)pCanMsg->Data[7]<<8) | pCanMsg->Data[6]; - - // request transmission - CAN->sMsgObj[0].CRR = CAN_CRR_BUSY | (1 + 0); - - return 1; -} - -/******************************************************************************* -* Function Name : CAN_BasicReceiveMessage -* Description : Get the message in BASIC mode, if received -* Input 1 : pointer to the message structure where received data is stored -* Output : None -* Return : 1 if reception was OK, else 0 (no message pending) -* Note : CAN must be in BASIC mode -*******************************************************************************/ -u32 CAN_BasicReceiveMessage(canmsg* pCanMsg) -{ - if ((CAN->sMsgObj[1].MCR & CAN_MCR_NEWDAT) == 0) - return 0; - - CAN->SR &= ~CAN_SR_RXOK; - - CAN->sMsgObj[1].CMR = CAN_CMR_ARB - | CAN_CMR_CONTROL - | CAN_CMR_DATAA - | CAN_CMR_DATAB; - - if ((CAN->sMsgObj[1].A2R & CAN_A2R_XTD) == 0) - { - // standard ID - pCanMsg->IdType = CAN_STD_ID; - pCanMsg->Id = (CAN->sMsgObj[1].A2R >> 2) & 0x07FF; - } - else - { - // extended ID - pCanMsg->IdType = CAN_EXT_ID; - pCanMsg->Id = ((CAN->sMsgObj[1].A2R >> 2) & 0x07FF) | ((u32)CAN->sMsgObj[1].A1R << 11) | (((u32)CAN->sMsgObj[1].A2R & 0x0003) << 27); - } - - pCanMsg->Dlc = CAN->sMsgObj[1].MCR & 0x0F; - - pCanMsg->Data[0] = (u8) CAN->sMsgObj[1].DA1R; - pCanMsg->Data[1] = (u8)(CAN->sMsgObj[1].DA1R >> 8); - pCanMsg->Data[2] = (u8) CAN->sMsgObj[1].DA2R; - pCanMsg->Data[3] = (u8)(CAN->sMsgObj[1].DA2R >> 8); - pCanMsg->Data[4] = (u8) CAN->sMsgObj[1].DB1R; - pCanMsg->Data[5] = (u8)(CAN->sMsgObj[1].DB1R >> 8); - pCanMsg->Data[6] = (u8) CAN->sMsgObj[1].DB2R; - pCanMsg->Data[7] = (u8)(CAN->sMsgObj[1].DB2R >> 8); - - return 1; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/eic.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/eic.c deleted file mode 100644 index 8bc053dfd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/eic.c +++ /dev/null @@ -1,67 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : eic.c -* Author : MCD Application Team -* Date First Issued : 06/25/2003 -* Description : This file provides all the EIC software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "eic.h" - -/******************************************************************************* -* Function Name : EIC_Init -* Description : Initialise the EIC using the load PC instruction -* (PC = PC +offset) -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void EIC_Init(void) -{ - extern u32 T0TIMI_Addr; - u8 bCounter; - u32 dOffset=((u32)&T0TIMI_Addr); - EIC->ICR = 0x00000000; // Disable FIQ and IRQ interrupts - EIC->IER = 0x00000000; // Disable all channels interrupts - EIC->IPR = 0xFFFFFFFF; // Clear all pending bits - EIC->FIR = 0x0000000C; // Disable all FIQ channels interrupts and clear FIQ - // channels pending bits - EIC->CIPR = 0x00000000; // Ste the current priority level to zero - EIC->IVR = 0xE59F0000; // IVR = high half of load PC instruction - dOffset = (dOffset+0x00007E0)<<16; - for(bCounter=0; bCounter<32; bCounter++) // Initialize SIRn registers - { - EIC->SIR[bCounter] = dOffset|0xF0000000; - dOffset += 0x00000004 << 16; - } -} - -/******************************************************************************* -* Function Name : EIC_CurrentPriorityLevelConfig -* Description : Change the current priority level of the srved IRQ routine -* Input 1 : New priority -* Output : None -* Return : None -*******************************************************************************/ -void EIC_CurrentPriorityLevelConfig(u8 NewPriorityLevel) -{ - u32 dVal; - dVal = EIC->ICR; // Save ICR content - EIC->ICR &= ~0x0001; // Disable IRQ interrupts. - EIC->CIPR = NewPriorityLevel; // Change the current priority - EIC->ICR = dVal; // Restore ICR content -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/emi.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/emi.c deleted file mode 100644 index caf2a73e1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/emi.c +++ /dev/null @@ -1,24 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : emi.c -* Author : MCD Application Team -* Date First Issued : 08/08/2003 -* Description : This file provides all the EMI software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "emi.h" - - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/flash.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/flash.c deleted file mode 100644 index 9e28cf3ae..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/flash.c +++ /dev/null @@ -1,354 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : flash.c -* Author : MCD Application Team -* Date First Issued : 07/28/2003 -* Description : This file provides all the Flash software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "flash.h" - - u32 D0_temp; - - -/******************************************************************************* -* Function Name : FLASH_Init -* Description : Initialise the Flash -* Input : None -* Return : None -*******************************************************************************/ -void FLASH_Init(void) -{ -// Reset Flash Control Registers - FLASHR->CR0 = 0x00000000; - FLASHR->CR1 = 0x00000000; -// Reset Flash Data Registers - FLASHR->DR0 = 0xFFFFFFFF; - FLASHR->DR1 = 0xFFFFFFFF; -// Reset Flash Error Register - FLASHR->ER = 0x00000000; -} - -/******************************************************************************* -* Function Name : FLASH_WordWrite -* Description : Writes a Word to the Flash -* Input 1 : Address of the Destination -* Input 2 : Word To program -* Return : None -*******************************************************************************/ -void FLASH_WordWrite(u32 XtargetAdd, u32 Xdata) -{ - FLASH_WaitForLastTask(); - // set the Word Programming bit 'WPG' in the CR0 Reg - FLASHR->CR0 |= FLASH_WPG_Mask; - // Load the destination address in AR - FLASHR->AR = XtargetAdd; - // Load DATA to be programmed in DR0 - FLASHR->DR0 = Xdata; - // Set the Write Mode Start bit 'WMS' in the CR0 Reg to Start Write Operation - FLASHR->CR0 |= FLASH_WMS_Mask; - // Wait until the write operation is completed - FLASH_WaitForLastTask(); -} - -/******************************************************************************* -* Function Name : FLASH_DWordWrite -* Description : Writes Double Word to the Flash -* Input 1 : Address of the Destination -* Input 2 : Word 1 To program -* Input 3 : Word 2 To program -* Return : None -*******************************************************************************/ -void FLASH_DWordWrite(u32 XtargetAdd, u32 Xdata0, u32 Xdata1) -{ - - FLASH_WaitForLastTask(); - // set the Double Word Programming bit 'DWPG' in the CR0 Reg - FLASHR->CR0 |= FLASH_DWPG_Mask; - // Load the destination address in AR - FLASHR->AR = XtargetAdd; - // Load DATA0 in DR0 Reg - FLASHR->DR0 = Xdata0; - // Load DATA1 in DR1 Reg - FLASHR->DR1 = Xdata1; - // Set the Write Mode Start bit 'WMS' in the CR0 Reg to Start Write Operation - FLASHR->CR0 |= FLASH_WMS_Mask; - // Wait until the write operation is completed - FLASH_WaitForLastTask(); -} - - -/******************************************************************************* -* Function Name : FLASH_SectorErase -* Description : Erases a Flash sector -* Input 1 : Sectors to be Erased -* Return : None -*******************************************************************************/ -void FLASH_SectorErase(u32 Xsectors) -{ - FLASH_WaitForLastTask(); - // Set the Sector Erase flag 'SER' in the FCRO reg - FLASHR->CR0 |= FLASH_SER_Mask; - // Select the Sectors to be erased in the CR1 register - FLASHR->CR1 |= Xsectors; - // Set the Write Mode Start bit 'WMS' in the CR0 Reg to Start Erase Operation - FLASHR->CR0 |= FLASH_WMS_Mask; - // Wait until the erase operation is completed - FLASH_WaitForLastTask(); -} -/******************************************************************************* -* Function Name : FLASH_Suspend -* Description : Suspends the current program or erase operation -* Input 1 : None -* Return : Flash CR0 register -*******************************************************************************/ -u32 FLASH_Suspend(void) -{ - u32 temp; - /* Save the CR0 Contetnt */ - temp = FLASHR->CR0; - /* Set The suspend Bit 'SUSP' in the CR0 register */ - FLASHR->CR0 |= FLASH_SUSP_Mask; - /* Wait until the flash controller acknowlegs the suspend of the current - operation */ - FLASH_WaitForLastTask(); - return temp; -} -/******************************************************************************* -* Function Name : FLASH_Resume -* Description : Resume a Suspended program or erase operation -* Input 1 : The operation to be resumed -* Return : None -*******************************************************************************/ -void FLASH_Resume(u32 FLASH_LastOperation) -{ - // Clear The suspend Bit 'SUSP' in the FRC0 register - FLASHR->CR0 &= ~FLASH_SUSP_Mask; - // Resume last operation - FLASHR->CR0 = FLASH_LastOperation & 0x7FFFFFFF; - // Set write mode bit - FLASHR->CR0 |= FLASH_WMS_Mask; -} - -/******************************************************************************* -* Function Name : FLASH_WordRead -* Description : Read a single word of the flash -* Input 1 : Source Address -* Return : Word -*******************************************************************************/ -u32 FLASH_WordRead(u32 FLASH_SourceAdd) -{ - FLASH_WaitForLastTask(); - // Reads the data from the specified Address - return *(u32 *)(FLASH_SourceAdd + 0x40000000); -} -/******************************************************************************* -* Function Name : FLASH_WritePrConfig -* Description : Configures The Write Protection Bits -* Input 1 : Flash Bank -* Input 2 : Enable or disable Protection -* Return : None -*******************************************************************************/ -void FLASH_WritePrConfig(u32 Xsectors, FunctionalState NewState) -{ - FLASH_WaitForLastTask(); - - if (NewState == ENABLE) - { - // Set the Set protection Bit - FLASHR->CR0 |= FLASH_SPR_Mask; - // Set the Register Address - FLASHR->AR = 0x4010DFB0; - // Data To be Programmed to the Protection Register - FLASHR->DR0 = ~Xsectors; - // Set the WMS bit to Start the Sequence - FLASHR->CR0 |= FLASH_WMS_Mask; - } - else - { - // Set the Set protection Bit - FLASHR->CR0 |= FLASH_SPR_Mask; - // Set the Register Address - FLASHR->AR = 0x4010DFB0; - // Data To be Programmed to the Protection Register - FLASHR->DR0 = FLASHPR->NVWPAR|Xsectors; - // Set the WMS bit to Start the Sequence - FLASHR->CR0 |= FLASH_WMS_Mask; - } -} - -/******************************************************************************* -* Function Name : FLASH_PermanantDebugPrConfig -* Description : Configures The Debug Protection Bits -* Input 1 : ENABLE or DISABLE -* Return : Word -*******************************************************************************/ -void FLASH_PermanantDebugPrConfig(FunctionalState NewState) -{ - u16 ProtectionLevel = FLASH_ProtectionLevel(); - - - if (NewState == ENABLE) - { - // If the First Protection Reset the DBGP bit - if(!ProtectionLevel) - { - // Set the Set protection Bit - FLASHR->CR0 |= FLASH_SPR_Mask; - // Set the Register Address - FLASHR->AR = 0x4010DFB8; - // Data To be Programmed to the Protection Register - FLASHR->DR0 = ~2; - // Set the WMS bit to Start the Sequence - FLASHR->CR0 |= FLASH_WMS_Mask; - } - else - { - // Set the Set protection Bit - FLASHR->CR0 |= FLASH_SPR_Mask; - // Set the Register Address - FLASHR->AR = 0x4010DFBC; - // Data To be Programmed to the Protection Register - D0_temp=~(1<<(15+ProtectionLevel)); - FLASHR->DR0 =D0_temp; - // Set the WMS bit to Start the Sequence - FLASHR->CR0 |= FLASH_WMS_Mask; - } - - } - else if(ProtectionLevel) - { - // Set the Set protection Bit - FLASHR->CR0 |= FLASH_SPR_Mask; - // Set the Register Address - FLASHR->AR = 0x4010DFBC; - // Data To be Programmed to the Protection Register - FLASHR->DR0 =~(1<<(ProtectionLevel-1)); - // Set the WMS bit to Start the Sequence - FLASHR->CR0 |= FLASH_WMS_Mask; - } - -} - -/******************************************************************************* -* Function Name : FLASH_FlagStatus -* Description : Returns the NewState of Flash flags -* Input 1 : Flash Flag -* Return : flagstate -*******************************************************************************/ -FlagStatus FLASH_FlagStatus(flashflags Xflag) -{ - FlagStatus TmpResult; - u8 TmpReg; - u8 TmpPos; - // get the Register Index - TmpReg = (Xflag & FLASH_Reg_Mask) >> 5; - // get the Flag Index - TmpPos = (Xflag & FLASH_Flag_Mask); - - switch(TmpReg) - { - case 0 : // CR0 - { - // Returns the status of the CR0[TmpPos] flag - TmpResult = (FLASHR->CR0 & (1<CR1 & (1<ER & (1<> 5; - TmpPos = (Xflag & FLASH_Flag_Mask); - - switch(TmpReg) - { - case 0 : // CR0 - { - // Clears the status of the CR0[TmpPos] flag - FLASHR->CR0 &= ~(1<CR1 &= ~(1<ER &= ~(1<NVAPR0&2) - TmpBitIndex=0; - else - TmpBitIndex=1; - - ProtectionRegs=~(FLASHPR->NVAPR1>>16); - while (((ProtectionRegs) != 0) && (TmpBitIndex < 16)) - { - ProtectionRegs = ProtectionRegs >> 1 ; - TmpBitIndex++; - } - return TmpBitIndex; -} -/******************************************************************************* -* Function Name : Wait For Last Task -* Description : Waits for the end of last task on a Flash Bank -* Input 1 : None. -* Return : None -*******************************************************************************/ -void FLASH_WaitForLastTask(void) -{ - while (FLASHR->CR0&0x16); -} - -/*******************(C)COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/gpio.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/gpio.c deleted file mode 100644 index 588d1f285..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/gpio.c +++ /dev/null @@ -1,115 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : gpio.c -* Author : MCD Application Team -* Date First Issued : 06/08/2003 -* Description : This file provides all the GPIO software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "gpio.h" - -/******************************************************************************* -* Function Name : GPIO_Config -* Description : Configure the GPIO port pins -* Input 1 : GPIOx (x can be 0,1 or 2) the desired port -* Input 2 : Port_Pins : pins placements -* Input 3 : Pins Mode -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_Config (GPIO_TypeDef *GPIOx, u16 Port_Pins, GpioPinMode_TypeDef GPIO_Mode) -{ - switch (GPIO_Mode) - { - case GPIO_HI_AIN_TRI: - GPIOx->PC0&=~Port_Pins; - GPIOx->PC1&=~Port_Pins; - GPIOx->PC2&=~Port_Pins; - break; - - case GPIO_IN_TRI_TTL: - GPIOx->PC0|=Port_Pins; - GPIOx->PC1&=~Port_Pins; - GPIOx->PC2&=~Port_Pins; - break; - - case GPIO_IN_TRI_CMOS: - GPIOx->PC0&=~Port_Pins; - GPIOx->PC1|=Port_Pins; - GPIOx->PC2&=~Port_Pins; - break; - - case GPIO_IPUPD_WP: - GPIOx->PC0|=Port_Pins; - GPIOx->PC1|=Port_Pins; - GPIOx->PC2&=~Port_Pins; - break; - - case GPIO_OUT_OD: - GPIOx->PC0&=~Port_Pins; - GPIOx->PC1&=~Port_Pins; - GPIOx->PC2|=Port_Pins; - break; - - case GPIO_OUT_PP: - GPIOx->PC0|=Port_Pins; - GPIOx->PC1&=~Port_Pins; - GPIOx->PC2|=Port_Pins; - break; - - case GPIO_AF_OD: - GPIOx->PC0&=~Port_Pins; - GPIOx->PC1|=Port_Pins; - GPIOx->PC2|=Port_Pins; - break; - - case GPIO_AF_PP: - GPIOx->PC0|=Port_Pins; - GPIOx->PC1|=Port_Pins; - GPIOx->PC2|=Port_Pins; - break; - } -} - -/******************************************************************************* -* Function Name : GPIO_BitWrite -* Description : Set or reset the selected port pin -* Input 1 : Selected GPIO port -* Input 2 : Pin number -* Input 3 : bit value -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_BitWrite(GPIO_TypeDef *GPIOx, u8 Port_Pin, u8 Port_Val) -{ - if (Port_Val&0x01) GPIOx->PD |= 1<PD &= ~(1<PD = Port_Byte ? (GPIOx->PD&0x00FF) | ((u16)Port_Val<<8) - : (GPIOx->PD&0xFF00) | Port_Val; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/i2c.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/i2c.c deleted file mode 100644 index 70c7f68ad..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/i2c.c +++ /dev/null @@ -1,504 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : i2c.c -* Author : MCD Application Team -* Date First Issued : 09/05/2003 -* Description : This file provides Code sources I2C functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "i2c.h" -#include "rccu.h" -#include - -/******************************************************************************* -* Function Name : I2C_Init -* Description : Initializes I2C peripheral control and registers to their -* default reset values. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : None. -*******************************************************************************/ -void I2C_Init (I2C_TypeDef *I2Cx) -{ - //Initialize all the register of the specified I2C passed as parameter - I2Cx->CR=0x0; - I2Cx->CCR=0x0; - I2Cx->ECCR=0x0; - I2Cx->OAR1=0x0; - I2Cx->OAR2=0x0; - (void)I2Cx->SR1; - (void)I2Cx->SR2; - I2Cx->DR=0x0; -} - -/******************************************************************************* -* Function Name : I2C_OnOffConfig -* Description : Enables or disables I2C peripheral. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -void I2C_OnOffConfig (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) - { - // Enable the I2C selected by setting twice the PE bit on the CR register - I2Cx->CR |= I2C_PESET_Mask; - I2Cx->CR |= I2C_PESET_Mask; - } - else - // Disable the I2C selected - I2Cx->CR &= ~I2C_PESET_Mask; -} - -/******************************************************************************* -* Function Name : I2C_FlagStatus -* Description : Checks whether any I2C Flag is set or not. -* Input : I2Cx ( I2C0 or I2C1 ) -* Access(DIRECT or INDIRECT) -* Flag : the flag to be read -* input 4: an (u8) variable needed in the case -* of the INDIRECT access -* Return : the NewState of the Flag (SET or RESET). -*******************************************************************************/ -FlagStatus I2C_FlagStatus (I2C_TypeDef *I2Cx, RegisterAccess Access, I2C_Flags Flag, ...) -{ - u32 Tmp; - - if (Access == DIRECT) - // Store in Tmp variable the register where is located the flag - Tmp = I2C_GetStatus(I2Cx)&Flag; - else - { - va_list list; - //Get the fourth register - va_start(list,Flag); - Tmp = va_arg(list,u32); - Tmp&=Flag; - } - //Return the Flag NewState - return Tmp != 0 ? SET : RESET; -} - -/******************************************************************************* -* Function Name : I2C_FlagClear -* Description : Clears the I2C Flag passed as a parameter -* Input : I2Cx ( I2C0 or I2C1 ) -* Flag : the flag to be read -* input3: an (u8) parameter needed in the case that the flag -* to be cleared need a write in one register -* Return : None. -*******************************************************************************/ -void I2C_FlagClear (I2C_TypeDef *I2Cx, I2C_Flags Flag, ...) -{ - u8 Tmp = (u8)*((u32 *)&Flag + sizeof(Flag)); - - if (Flag==I2C_ADD10 || Flag==I2C_EVF || Flag==I2C_BERR || Flag==I2C_ARLO || - Flag==I2C_STOPF || Flag==I2C_AF || Flag==I2C_ENDAD) - //flags that need a read of the SR2 register to be cleared - { - // Read the SR2 register - (void)I2Cx->SR2; - // Two flags need a second step to be cleared - switch (Flag) - { - case I2C_ADD10: I2Cx->DR = Tmp; break; - case I2C_ENDAD: I2Cx->CR|=0x20; break; - } - } - else if (Flag==I2C_SB || Flag==I2C_ADSL || Flag==I2C_BTF || Flag==I2C_TRA) - //flags that need a read of the SR1 register to be cleared - { - // Read the SR1 register - (void)I2Cx->SR1; - if (Flag==I2C_SB) I2Cx->DR=Tmp; - else if (Flag==I2C_BTF || Flag==I2C_TRA) (void)I2Cx->DR; - } - else if ( Flag==I2C_M_SL || Flag==I2C_GCAL) - //flags that need the PE bit to be cleared - { - I2C_OnOffConfig (I2Cx, DISABLE); - I2C_OnOffConfig (I2Cx, ENABLE); - } -} - -/******************************************************************************* -* Function Name : I2C_SpeedConfig -* Description : Selects I2C clock speed and configures its corresponding mode. -* Input : I2Cx ( I2C0 or I2C1 ) -* Clock: I2C expected clock in Hertz. -* Return : None. -*******************************************************************************/ -void I2C_SpeedConfig (I2C_TypeDef *I2Cx, u32 Clock) -{ - u32 FCLK; - u16 result; - // Get the FCLK frequency using the RCCU library - FCLK = RCCU_FrequencyValue ( RCCU_FCLK ); - // Test on speed mode - // Update the CCR and ECCR are updated - if (Clock <=100000) - // Standard mode selected - { - result = ((FCLK / Clock) - 7)/2; - //Clear FM/SM bit - I2Cx->CCR=result &0x7f; - } - else if (Clock <=400000) - { - // Fast mode selected - result = ((FCLK/Clock)-9)/3; - //set FM/SM bit - I2Cx->CCR=result |0x80; - } - I2Cx->ECCR= result >>7; -} -/******************************************************************************* -* Function Name : I2C_AddressConfig -* Description : Defines the I2C bus address of the interface. -* Input : I2Cx ( I2C0 or I2C1 ). -* Address: an u16 parameter indicating the address -* of the interface. -* Mode (I2C_Mode10,I2C_Mode7). -* Return : None. -*******************************************************************************/ -void I2C_AddressConfig (I2C_TypeDef *I2Cx, u16 Address, I2C_Addressing Mode) -{ - //Update OAR1 bit[7:1] by the lowest byte of address - I2Cx->OAR1 = (u8)Address; - - if (Mode == I2C_Mode10) - //Update Add8 and add9 bits in OAR2 - I2Cx->OAR2 |= (Address & 0x0300)>>7; -} - -/******************************************************************************* -* Function Name : I2C_FCLKConfig -* Description : Configures frequency bits according to RCLK frequency. -* the selected I2C must be disabled -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : None. -*******************************************************************************/ -void I2C_FCLKConfig (I2C_TypeDef *I2Cx) -{ - u32 FCLK; - // Get the FCLK frequency using the RCCU library - FCLK = RCCU_FrequencyValue ( RCCU_FCLK ); - // Test the value of the FCLK and affect FR0,FR1&FR2 of the OAR2 register - if (FCLK > 5000000) - { - if (FCLK <10000000) - I2Cx->OAR2 |= 0x00; - else if (FCLK <16670000) - I2Cx->OAR2 |= 0x20; - else if (FCLK < 26670000) - I2Cx->OAR2 |= 0x40; - else if (FCLK <40000000) - I2Cx->OAR2 |= 0x60; - else if (FCLK < 53330000) - I2Cx->OAR2 |= 0x80; - else if (FCLK < 66000000) - I2Cx->OAR2 |= 0xA0; - else if (FCLK <80000000) - I2Cx->OAR2 |= 0xC0; - else if (FCLK <100000000) - I2Cx->OAR2 |= 0xE0; - } -} - -/******************************************************************************* -* Function Name : I2C_AddressSend -* Description : Transmits the address byte to select the slave device. -* Input : I2Cx ( I2C0 or I2C1 ) -* Address: an u16 parameter indicating the slave address -* Mode (I2C_Mode10,I2C_Mode7). -* Direction (I2C_RX,I2C_TX). -* Return : None. -********************************************************************************/ -void I2C_AddressSend (I2C_TypeDef *I2Cx, u16 Address, I2C_Addressing Mode, I2C_Direction Direction) -{ - if (Mode == I2C_Mode10 ) - //10 bit addressing mode - { - // Update the DR register by generated header - I2Cx->DR = ((Address>>7)|0xf0)&0xfe; - //Wait till I2C_ADD10 flag is set - while ((I2Cx->SR1&0x40)==0); - //clear I2C_ADD10 flag - (void)I2Cx->SR2; - I2Cx->DR=(u8)Address; - //Test on the direction to define the read/write bit - if (Direction == I2C_RX) - { - //Wait till I2C_ENDAD flag is set - while ((I2Cx->SR2&0x20)==0); - I2Cx->CR|=0x20; - //Repeated START Generate - I2C_STARTGenerate (I2Cx, ENABLE); - //Test on SB flag status - while ((I2Cx->SR1&0x01)==0); - I2Cx->DR = ((Address>>7)|0xf1); - } - } - else - // 7 bit addressing mode - { - if (Direction == I2C_RX) Address|=0x01; else Address&=~0x01; - I2Cx->DR=(u8)Address; - } -} - -/******************************************************************************* -* Function Name : I2C_ByteSend -* Description : Send a single byte of data. -* Input : I2Cx ( I2C0 or I2C1 ) -* Data : the byte to be sent to the slave -* Return : None. -*******************************************************************************/ -void I2C_ByteSend (I2C_TypeDef *I2Cx, u8 Data) -{ - //Write in the DR register the byte to be sent - I2Cx->DR = Data; -} - -/******************************************************************************* -* Function Name : I2C_BufferSend -* Description : Send data from a buffer whose number of bytes is known -* Input : I2Cx ( I2C0 or I2C1 ) -* PtrToBuffer :pointer to the byte of buffer to be transmitted. -* NbOfBytes:Number of byte of the buffer -* Return : I2C_Tx_Status :transmission status (I2C_TX_AF, I2C_TX_ARLO, -* I2C_TX_BERR,I2C_TX_DATA_OK) -*******************************************************************************/ -I2C_Tx_Status I2C_BufferSend (I2C_TypeDef *I2Cx, u8 *PtrToBuffer, u8 NbOfBytes) -{ - u8 Interruption_Status; - u8 SentBytes; - u8 error; - I2C_Tx_Status I2C_TXTMP; - - //Test of the interrupt status - Interruption_Status=0; - Interruption_Status=I2Cx->CR & 0x01; - I2C_ITConfig (I2Cx, DISABLE); - //Wait till I2C_BTF bit is set - while ((I2Cx->SR1 & 0x08 )==0); - SentBytes=0; - while (SentBytesDR= *(PtrToBuffer+SentBytes); - //Wait till I2C_BTF bit is set or error detected - do - error = I2Cx->SR2 & 0x16; - while ((I2Cx->SR1 & 0x08)==0 && error==0); - // In case of error exit - if (error) break; - // increment SentBytes counter - SentBytes++; - } - if (error) - { - if (error & 0x10) - // I2C_TX_AF if Acknowledge failure is detected - I2C_TXTMP = I2C_TX_AF; - if (error & 0x02) - //I2C_TX_ARLO if the ARLO bit is set in the SR2 register - I2C_TXTMP = I2C_TX_ARLO; - if (error & 0x04) - // I2C_TX_BERR if the BERR bit is set in the SR2 register - I2C_TXTMP= I2C_TX_BERR; - } - else - //I2C_TX_DATA_OK to show that the buffer is well sent - I2C_TXTMP= I2C_TX_DATA_OK; - - //Restore the interrupt status - if (Interruption_Status==1) - I2C_ITConfig (I2Cx, ENABLE); - - return I2C_TXTMP; -} - -/******************************************************************************* -* Function Name : I2C_StringSend -* Description : Send data from a buffer -* Input : I2Cx ( I2C0 or I2C1 ) -* PtrToBuffer :pointer to the byte of string to be transmitted. -* Return : I2C_Tx_Status :transmission status (I2C_TX_AF, I2C_TX_ARLO, -* I2C_TX_BERR,I2C_TX_DATA_OK) -*******************************************************************************/ -I2C_Tx_Status I2C_StringSend (I2C_TypeDef *I2Cx, char *PtrToString) -{ - u8 NbOfBytes=0; - // count the number of byte composing the string passed as parameter. - while (*(PtrToString+NbOfBytes)!= '\0') - NbOfBytes++; - // call I2C_BufferSend function to execute the send part - return I2C_BufferSend (I2Cx,(u8 *)PtrToString,NbOfBytes); -} - -/******************************************************************************* -* Function Name : I2C_TransmissionStatus -* Description : Report the NewState of the transmission -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : I2C_Tx_Status :transmission status (I2C_TX_NO, I2C_TX_SB, -* I2C_TX_AF, I2C_TX_ARLO, I2C_TX_BERR,I2C_TX_ADD_OK, -* I2C_TX_DATA_OK,I2C_TX_ONGOING) -*******************************************************************************/ -I2C_Tx_Status I2C_TransmissionStatus (I2C_TypeDef *I2Cx) -{ - u8 SR1value; - u8 SR2value; - I2C_Tx_Status NewState; - - SR1value = I2Cx->SR1; - SR2value = I2Cx->SR2; - if ((I2Cx->SR1&0x10)==0) - NewState=I2C_TX_NO; - else if (I2Cx->SR1&0x01) - //I2C_SB bit is set - NewState=I2C_TX_SB; - else if ((SR2value & 0x10)&&(I2Cx->CR&0x04)) - //I2C_ACK &I2C_AF are both set - NewState=I2C_TX_AF; - else if (SR2value & 0x04) - //I2C_ARLO is set in multimaster mode - NewState=I2C_TX_ARLO; - else if (SR2value & 0x02) - //I2C_BERR bit is set - NewState=I2C_TX_BERR; - else if ((SR1value & 0x80)&& (I2Cx->SR2&0x20)) - //I2C_EVF and I2C_ENDAD are both set - NewState=I2C_TX_ADD_OK; - else if ((I2Cx->SR1&0x20)&& (I2Cx->SR1&0x08)) - //I2C_TRA and I2C_BTF are both set - NewState=I2C_TX_DATA_OK; - else - NewState=I2C_TX_ONGOING; - - return NewState; -} - -/******************************************************************************* -* Function Name : I2C_ByteReceive -* Description : Returns the received byte. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : the byte received -*******************************************************************************/ -u8 I2C_ByteReceive (I2C_TypeDef *I2Cx) -{ - //Wait till I2C_BTF bit is set - while ((I2Cx->SR1 & 0x08)==0); - return I2Cx->DR; -} - -/******************************************************************************* -* Function Name : I2C_BufferReceive -* Description : received a buffer. and return the status of error. -* Input : I2Cx ( I2C0 or I2C1 ) -* PtrToBuffer :pointer to the byte of buffer received. -* NbOfBytes:Number of byte to be received -* Return : I2C_Rx_Status:the NewState of the reception (,I2C_RX_AF, -* I2C_RX_ARLO,I2C_RX_BERR, I2C_RX_DATA_OK) -*******************************************************************************/ -I2C_Rx_Status I2C_BufferReceive (I2C_TypeDef *I2Cx, u8 *PtrToBuffer, u8 NbOfBytes) -{ - u8 Interruption_Status; - u8 ReceivedBytes; - u8 error; - I2C_Rx_Status I2C_RXTMP; - - //Test of the interrupt status - Interruption_Status=0; - Interruption_Status=I2Cx->CR & 0x01; - I2C_ITConfig (I2Cx, DISABLE); - ReceivedBytes=0; - while (ReceivedBytesSR2 & 0x16; - while ((I2Cx->SR1 & 0x08)==0 && !error); - if (error==0) - // No error detected - { - *(PtrToBuffer+ReceivedBytes) = I2Cx->DR; - ReceivedBytes++; - } - else break; - } - if (error) - { - if (error & 0x10) - // I2C_RX_AF if Acknowledge failure is detected - I2C_RXTMP= I2C_RX_AF; - else if (error & 0x02) - // I2C_RX_ARLO if the ARLO bit is set in the SR2 register - I2C_RXTMP= I2C_RX_ARLO; - else if (error & 0x04) - // I2C_RX_BERR if the BERR bit is set in the SR2 register - I2C_RXTMP= I2C_RX_BERR; - } - else - //I2C_RX_DATA_OK to show that the buffer is well sent - I2C_RXTMP= I2C_RX_DATA_OK; - - //Restore the interrupt status - if (Interruption_Status==1) - I2C_ITConfig (I2Cx, ENABLE); - - return I2C_RXTMP; -} - -/******************************************************************************* -* Function Name :I2C_ReceptionStatus -* Description : Report the reception NewState. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : I2C_Rx_Status:the NewState of the reception ( I2C_RX_NO, -* I2C_RX_SB,I2C_RX_AF,I2C_RX_ARLO,I2C_RX_BERR,I2C_RX_ADD_OK, -* I2C_RX_DATA_OK, I2C_RX_ONGOING) -*******************************************************************************/ -I2C_Rx_Status I2C_ReceptionStatus (I2C_TypeDef *I2Cx) -{ - u8 SR1value; - u8 SR2value; - I2C_Rx_Status NewState; - SR1value= I2Cx->SR1; - SR2value= I2Cx->SR2; - - if ((I2Cx->SR1&0x10) == 0) - NewState=I2C_RX_NO; - else if (I2Cx->SR1&0x01) - //I2C_SB bit is set - NewState=I2C_RX_SB; - else if ((SR2value & 0x10) && (I2Cx->CR&0x04)) - //I2C_ACK &I2C_AF are both set - NewState=I2C_RX_AF; - else if (SR2value & 0x04) - //I2C_ARLO is set - NewState=I2C_RX_ARLO; - else if (SR2value & 0x02) - //I2C_BERR bit is set - NewState=I2C_RX_BERR; - else if ((SR1value & 0x80) && (I2Cx->SR1&0x08)==0) - //2C_EVF is set & I2C_BTF is not set - NewState=I2C_RX_ADD_OK; - else if ((I2Cx->SR1&0x20)==0 && (I2Cx->SR1&0x08)) - //II2C_TRA is cleared & I2C_BTF is set - NewState=I2C_RX_DATA_OK; - else - NewState=I2C_RX_ONGOING; - return NewState; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/71x_conf.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/71x_conf.h deleted file mode 100644 index db268a565..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/71x_conf.h +++ /dev/null @@ -1,75 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_conf.h -* Author : MCD Application Team -* Date First Issued : 16/05/2003 -* Description : Library configuration for the WDG example -******************************************************************************** -* History: -* 24/05/05 : V3.0 -* 30/11/04 : V2.0 -* 16/05/03 : Created -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __71x_CONF_H -#define __71x_CONF_H - -/* Comment the line below to put the library in release mode */ -//#define DEBUG - -#ifndef INLINE -#define INLINE static inline -#endif - -//#define USE_SERIAL_PORT -//#define USE_UART0 - -/* Main Oscillator Frequency value = 4 Mhz */ -#define RCCU_Main_Osc 4000000 - -/* Comment the lines below corresponding to unwanted peripherals */ -#define _ADC12 -#define _APB -#define _APB1 -#define _APB2 -#define _BSPI -#define _BSPI0 -#define _BSPI1 -#define _CAN -#define _EIC -#define _EMI -#define _FLASH -#define _GPIO -#define _GPIO0 -#define _GPIO1 -#define _GPIO2 -#define _I2C -#define _I2C0 -#define _I2C1 -#define _PCU -#define _RCCU -#define _RTC -#define _TIM -#define _TIM0 -#define _TIM1 -#define _TIM2 -#define _TIM3 -#define _UART -#define _UART0 -#define _UART1 -#define _UART2 -#define _UART3 -#define _USB -#define _WDG -#define _XTI -#define _IRQVectors - -#endif /* __71x_CONF_H */ - - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/71x_it.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/71x_it.h deleted file mode 100644 index 5b99928e1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/71x_it.h +++ /dev/null @@ -1,62 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_it.h -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Interrupt handlers -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef _71x_IT_H -#define _71x_IT_H - -#include "71x_lib.h" - - -void Undefined_Handler (void); -void FIQ_Handler (void); -void SWI_Handler (void); -void Prefetch_Handler (void); -void Abort_Handler (void); -void T0TIMI_IRQHandler (void); -void FLASH_IRQHandler (void); -void RCCU_IRQHandler (void); -void RTC_IRQHandler (void); -void WDG_IRQHandler (void); -void XTI_IRQHandler (void); -void USBHP_IRQHandler (void); -void I2C0ITERR_IRQHandler(void); -void I2C1ITERR_IRQHandler(void); -void UART0_IRQHandler (void); -void UART1_IRQHandler (void); -void UART2_IRQHandler (void); -void UART3_IRQHandler (void); -void BSPI0_IRQHandler (void); -void BSPI1_IRQHandler (void); -void I2C0_IRQHandler (void); -void I2C1_IRQHandler (void); -void CAN_IRQHandler (void); -void ADC12_IRQHandler (void); -void T1TIMI_IRQHandler (void); -void T2TIMI_IRQHandler (void); -void T3TIMI_IRQHandler (void); -void HDLC_IRQHandler (void); -void USBLP_IRQHandler (void); -void T0TOI_IRQHandler (void); -void T0OC1_IRQHandler (void); -void T0OC2_IRQHandler (void); - -#endif /* _71x_IT_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/71x_lib.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/71x_lib.h deleted file mode 100644 index 5532ca472..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/71x_lib.h +++ /dev/null @@ -1,101 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_lib.h -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Global include for all peripherals -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __71x_LIB_H -#define __71x_LIB_H - -#include "71x_map.h" -#include "71x_conf.h" - - -#ifdef _ADC12 - #include "adc12.h" -#endif - -#ifdef _APB - #include "apb.h" -#endif - -#ifdef _BSPI - #include "bspi.h" -#endif - -#ifdef _CAN - #include "can.h" -#endif - -#ifdef _EIC - #include "eic.h" -#endif - -#ifdef _EMI - #include "emi.h" -#endif - -#ifdef _FLASH - #include "flash.h" -#endif - -#ifdef _GPIO - #include "gpio.h" -#endif - -#ifdef _I2C - #include "i2c.h" -#endif - -#ifdef _PCU - #include "pcu.h" -#endif - -#ifdef _RCCU - #include "rccu.h" -#endif - -#ifdef _RTC - #include "rtc.h" -#endif - -#ifdef _TIM - #include "tim.h" -#endif - -#ifdef _UART - #include "uart.h" -#endif - -#ifdef _USB -#endif - -#ifdef _WDG - #include "wdg.h" -#endif - -#ifdef _XTI - #include "xti.h" -#endif - - -#ifdef LIBDEBUG - void libdebug(void); -#endif - -#endif /* __71x_LIB_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/71x_map.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/71x_map.h deleted file mode 100644 index 0f49a1549..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/71x_map.h +++ /dev/null @@ -1,611 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_map.h -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Peripherals memory mapping and registers structures -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __71x_map_H -#define __71x_map_H - -#ifndef EXT - #define EXT extern -#endif - -#include "71x_conf.h" -#include "71x_type.h" - - -/* IP registers structures */ - -typedef volatile struct -{ - vu16 DATA0; - vu16 EMPTY1[3]; - vu16 DATA1; - vu16 EMPTY2[3]; - vu16 DATA2; - vu16 EMPTY3[3]; - vu16 DATA3; - vu16 EMPTY4[3]; - vu16 CSR; - vu16 EMPTY5[7]; - vu16 CPR; -} ADC12_TypeDef; - -typedef volatile struct -{ - vu32 CKDIS; - vu32 SWRES; -} APB_TypeDef; - -typedef volatile struct -{ - vu16 RXR; - vu16 EMPTY1; - vu16 TXR; - vu16 EMPTY2; - vu16 CSR1; - vu16 EMPTY3; - vu16 CSR2; - vu16 EMPTY4; - vu16 CLK; -} BSPI_TypeDef; - -typedef volatile struct -{ - vu16 CRR; - vu16 EMPTY1; - vu16 CMR; - vu16 EMPTY2; - vu16 M1R; - vu16 EMPTY3; - vu16 M2R; - vu16 EMPTY4; - vu16 A1R; - vu16 EMPTY5; - vu16 A2R; - vu16 EMPTY6; - vu16 MCR; - vu16 EMPTY7; - vu16 DA1R; - vu16 EMPTY8; - vu16 DA2R; - vu16 EMPTY9; - vu16 DB1R; - vu16 EMPTY10; - vu16 DB2R; - vu16 EMPTY11[27]; -} CAN_MsgObj_TypeDef; - -typedef volatile struct -{ - vu16 CR; - vu16 EMPTY1; - vu16 SR; - vu16 EMPTY2; - vu16 ERR; - vu16 EMPTY3; - vu16 BTR; - vu16 EMPTY4; - vu16 IDR; - vu16 EMPTY5; - vu16 TESTR; - vu16 EMPTY6; - vu16 BRPR; - vu16 EMPTY7[3]; - CAN_MsgObj_TypeDef sMsgObj[2]; - vu16 EMPTY8[16]; - vu16 TR1R; - vu16 EMPTY9; - vu16 TR2R; - vu16 EMPTY10[13]; - vu16 ND1R; - vu16 EMPTY11; - vu16 ND2R; - vu16 EMPTY12[13]; - vu16 IP1R; - vu16 EMPTY13; - vu16 IP2R; - vu16 EMPTY14[13]; - vu16 MV1R; - vu16 EMPTY15; - vu16 MV2R; - vu16 EMPTY16; -} CAN_TypeDef; - -typedef volatile struct -{ - vu32 ICR; - vu32 CICR; - vu32 CIPR; - vu32 EMPTY1[3]; - vu32 IVR; - vu32 FIR; - vu32 IER; - vu32 EMPTY2[7]; - vu32 IPR; - vu32 EMPTY3[7]; - vu32 SIR[32]; -} EIC_TypeDef; - -typedef volatile struct -{ - vu16 BCON0; - vu16 EMPTY1; - vu16 BCON1; - vu16 EMPTY2; - vu16 BCON2; - vu16 EMPTY3; - vu16 BCON3; - vu16 EMPTY4; -} EMI_TypeDef; - -typedef volatile struct -{ - vu32 CR0; - vu32 CR1; - vu32 DR0; - vu32 DR1; - vu32 AR; - vu32 ER; -} FLASHR_TypeDef; - -typedef volatile struct -{ - vu32 NVWPAR; - vu32 EMPTY; - vu32 NVAPR0; - vu32 NVAPR1; -} FLASHPR_TypeDef; - -typedef volatile struct -{ - vu16 PC0; - vu16 EMPTY1; - vu16 PC1; - vu16 EMPTY2; - vu16 PC2; - vu16 EMPTY3; - vu16 PD; - vu16 EMPTY4; -} GPIO_TypeDef; - -typedef volatile struct -{ - vu8 CR; - vu8 EMPTY1[3]; - vu8 SR1; - vu8 EMPTY2[3]; - vu8 SR2; - vu8 EMPTY3[3]; - vu8 CCR; - vu8 EMPTY4[3]; - vu8 OAR1; - vu8 EMPTY5[3]; - vu8 OAR2; - vu8 EMPTY6[3]; - vu8 DR; - vu8 EMPTY7[3]; - vu8 ECCR; -} I2C_TypeDef; - -typedef volatile struct -{ - vu32 CCR; - vu32 EMPTY1; - vu32 CFR; - vu32 EMPTY2[3]; - vu32 PLL1CR; - vu32 PER; - vu32 SMR; -} RCCU_TypeDef; - -typedef volatile struct -{ - vu16 MDIVR; - vu16 EMPTY1; - vu16 PDIVR; - vu16 EMPTY2; - vu16 RSTR; - vu16 EMPTY3; - vu16 PLL2CR; - vu16 EMPTY4; - vu16 BOOTCR; - vu16 EMPTY5; - vu16 PWRCR; -} PCU_TypeDef; - -typedef volatile struct -{ - vu16 CRH; - vu16 EMPTY1; - vu16 CRL; - vu16 EMPTY2; - vu16 PRLH; - vu16 EMPTY3; - vu16 PRLL; - vu16 EMPTY4; - vu16 DIVH; - vu16 EMPTY5; - vu16 DIVL; - vu16 EMPTY6; - vu16 CNTH; - vu16 EMPTY7; - vu16 CNTL; - vu16 EMPTY8; - vu16 ALRH; - vu16 EMPTY9; - vu16 ALRL; -} RTC_TypeDef; - -typedef volatile struct -{ - vu16 ICAR; - vu16 EMPTY1; - vu16 ICBR; - vu16 EMPTY2; - vu16 OCAR; - vu16 EMPTY3; - vu16 OCBR; - vu16 EMPTY4; - vu16 CNTR; - vu16 EMPTY5; - vu16 CR1; - vu16 EMPTY6; - vu16 CR2; - vu16 EMPTY7; - vu16 SR; -} TIM_TypeDef; - -typedef volatile struct -{ - vu16 BR; - vu16 EMPTY1; - vu16 TxBUFR; - vu16 EMPTY2; - vu16 RxBUFR; - vu16 EMPTY3; - vu16 CR; - vu16 EMPTY4; - vu16 IER; - vu16 EMPTY5; - vu16 SR; - vu16 EMPTY6; - vu16 GTR; - vu16 EMPTY7; - vu16 TOR; - vu16 EMPTY8; - vu16 TxRSTR; - vu16 EMPTY9; - vu16 RxRSTR; -} UART_TypeDef; - -typedef volatile struct -{ - vu32 EP0R; - vu32 EP1R; - vu32 EP2R; - vu32 EP3R; - vu32 EP4R; - vu32 EP5R; - vu32 EP6R; - vu32 EP7R; - vu32 EP8R; - vu32 EP9R; - vu32 EP10R; - vu32 EP11R; - vu32 EP12R; - vu32 EP13R; - vu32 EP14R; - vu32 EP15R; - vu32 CNTR; - vu32 ISTR; - vu32 FNR; - vu32 DADDR; - vu32 BTABLE; -} USB_TypeDef; - -typedef volatile struct -{ - vu16 CR; - vu16 EMPTY1; - vu16 PR; - vu16 EMPTY2; - vu16 VR; - vu16 EMPTY3; - vu16 CNT; - vu16 EMPTY4; - vu16 SR; - vu16 EMPTY5; - vu16 MR; - vu16 EMPTY6; - vu16 KR; -} WDG_TypeDef; - -typedef volatile struct -{ - vu8 SR; - vu8 EMPTY1[7]; - vu8 CTRL; - vu8 EMPTY2[3]; - vu8 MRH; - vu8 EMPTY3[3]; - vu8 MRL; - vu8 EMPTY4[3]; - vu8 TRH; - vu8 EMPTY5[3]; - vu8 TRL; - vu8 EMPTY6[3]; - vu8 PRH; - vu8 EMPTY7[3]; - vu8 PRL; -} XTI_TypeDef; - - -/* IRQ vectors */ -typedef volatile struct -{ - vu32 T0TIMI_IRQHandler; - vu32 FLASH_IRQHandler; - vu32 RCCU_IRQHandler; - vu32 RTC_IRQHandler; - vu32 WDG_IRQHandler; - vu32 XTI_IRQHandler; - vu32 USBHP_IRQHandler; - vu32 I2C0ITERR_IRQHandler; - vu32 I2C1ITERR_IRQHandler; - vu32 UART0_IRQHandler; - vu32 UART1_IRQHandler; - vu32 UART2_IRQHandler; - vu32 UART3_IRQHandler; - vu32 BSPI0_IRQHandler; - vu32 BSPI1_IRQHandler; - vu32 I2C0_IRQHandler; - vu32 I2C1_IRQHandler; - vu32 CAN_IRQHandler; - vu32 ADC12_IRQHandler; - vu32 T1TIMI_IRQHandler; - vu32 T2TIMI_IRQHandler; - vu32 T3TIMI_IRQHandler; - vu32 EMPTY1[3]; - vu32 HDLC_IRQHandler; - vu32 USBLP_IRQHandler; - vu32 EMPTY2[2]; - vu32 T0TOI_IRQHandler; - vu32 T0OC1_IRQHandler; - vu32 T0OC2_IRQHandler; -} IRQVectors_TypeDef; - -/*===================================================================*/ - -/* Memory mapping */ - -#define RAM_BASE 0x20000000 - -#define FLASHR_BASE 0x40100000 -#define FLASHPR_BASE 0x4010DFB0 - -#define EXTMEM_BASE 0x60000000 -#define RCCU_BASE 0xA0000000 -#define PCU_BASE 0xA0000040 -#define APB1_BASE 0xC0000000 -#define APB2_BASE 0xE0000000 -#define EIC_BASE 0xFFFFF800 - -#define I2C0_BASE (APB1_BASE + 0x1000) -#define I2C1_BASE (APB1_BASE + 0x2000) -#define UART0_BASE (APB1_BASE + 0x4000) -#define UART1_BASE (APB1_BASE + 0x5000) -#define UART2_BASE (APB1_BASE + 0x6000) -#define UART3_BASE (APB1_BASE + 0x7000) -#define CAN_BASE (APB1_BASE + 0x9000) -#define BSPI0_BASE (APB1_BASE + 0xA000) -#define BSPI1_BASE (APB1_BASE + 0xB000) -#define USB_BASE (APB1_BASE + 0x8800) - -#define XTI_BASE (APB2_BASE + 0x101C) -#define GPIO0_BASE (APB2_BASE + 0x3000) -#define GPIO1_BASE (APB2_BASE + 0x4000) -#define GPIO2_BASE (APB2_BASE + 0x5000) -#define ADC12_BASE (APB2_BASE + 0x7000) -#define TIM0_BASE (APB2_BASE + 0x9000) -#define TIM1_BASE (APB2_BASE + 0xA000) -#define TIM2_BASE (APB2_BASE + 0xB000) -#define TIM3_BASE (APB2_BASE + 0xC000) -#define RTC_BASE (APB2_BASE + 0xD000) -#define WDG_BASE (APB2_BASE + 0xE000) - -#define EMI_BASE (EXTMEM_BASE + 0x0C000000) - -/*===================================================================*/ - -/* IP data access */ - -#ifndef LIBDEBUG - #define ADC12 ((ADC12_TypeDef *)ADC12_BASE) - - #define APB1 ((APB_TypeDef *)(APB1_BASE+0x10)) - #define APB2 ((APB_TypeDef *)(APB2_BASE+0x10)) - - #define BSPI0 ((BSPI_TypeDef *)BSPI0_BASE) - #define BSPI1 ((BSPI_TypeDef *)BSPI1_BASE) - - #define CAN ((CAN_TypeDef *)CAN_BASE) - - #define EIC ((EIC_TypeDef *)EIC_BASE) - - #define EMI ((EMI_TypeDef *)EMI_BASE) - - #define FLASHR ((FLASHR_TypeDef *)FLASHR_BASE) - #define FLASHPR ((FLASHPR_TypeDef *)FLASHPR_BASE) - - #define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE) - #define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE) - #define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE) - - #define I2C0 ((I2C_TypeDef *)I2C0_BASE) - #define I2C1 ((I2C_TypeDef *)I2C1_BASE) - - #define PCU ((PCU_TypeDef *)PCU_BASE) - - #define RCCU ((RCCU_TypeDef *)RCCU_BASE) - - #define RTC ((RTC_TypeDef *)RTC_BASE) - - #define TIM0 ((TIM_TypeDef *)TIM0_BASE) - #define TIM1 ((TIM_TypeDef *)TIM1_BASE) - #define TIM2 ((TIM_TypeDef *)TIM2_BASE) - #define TIM3 ((TIM_TypeDef *)TIM3_BASE) - - #define UART0 ((UART_TypeDef *)UART0_BASE) - #define UART1 ((UART_TypeDef *)UART1_BASE) - #define UART2 ((UART_TypeDef *)UART2_BASE) - #define UART3 ((UART_TypeDef *)UART3_BASE) - - #define USB ((USB_TypeDef *)USB_BASE) - - #define WDG ((WDG_TypeDef *)WDG_BASE) - - #define XTI ((XTI_TypeDef *)XTI_BASE) - - #define IRQVectors ((IRQVectors_TypeDef *)&T0TIMI_Addr) - -#else /* LIBDEBUG */ - - #ifdef _ADC12 - EXT ADC12_TypeDef *ADC12; - #endif - - #ifdef _APB - #ifdef _APB1 - EXT APB_TypeDef *APB1; - #endif - #ifdef _APB2 - EXT APB_TypeDef *APB2; - #endif - #endif - - #ifdef _BSPI - #ifdef _BSPI0 - EXT BSPI_TypeDef *BSPI0; - #endif - #ifdef _BSPI1 - EXT BSPI_TypeDef *BSPI1; - #endif - #endif - - #ifdef _CAN - EXT CAN_TypeDef *CAN; - #endif - - #ifdef _EIC - EXT EIC_TypeDef *EIC; - #endif - - #ifdef _EMI - EXT EMI_TypeDef *EMI; - #endif - - #ifdef _FLASH - EXT FLASHR_TypeDef *FLASHR; - EXT FLASHPR_TypeDef *FLASHPR; - #endif - - #ifdef _GPIO - #ifdef _GPIO0 - EXT GPIO_TypeDef *GPIO0; - #endif - #ifdef _GPIO1 - EXT GPIO_TypeDef *GPIO1; - #endif - #ifdef _GPIO2 - EXT GPIO_TypeDef *GPIO2; - #endif - #endif - - #ifdef _I2C - #ifdef _I2C0 - EXT I2C_TypeDef *I2C0; - #endif - #ifdef _I2C1 - EXT I2C_TypeDef *I2C1; - #endif - #endif - - #ifdef _PCU - EXT PCU_TypeDef *PCU; - #endif - - #ifdef _RCCU - EXT RCCU_TypeDef *RCCU; - #endif - - #ifdef _RTC - EXT RTC_TypeDef *RTC; - #endif - - #ifdef _TIM - #ifdef _TIM0 - EXT TIM_TypeDef *TIM0; - #endif - #ifdef _TIM1 - EXT TIM_TypeDef *TIM1; - #endif - #ifdef _TIM2 - EXT TIM_TypeDef *TIM2; - #endif - #ifdef _TIM3 - EXT TIM_TypeDef *TIM3; - #endif - #endif - - #ifdef _UART - #ifdef _UART0 - EXT UART_TypeDef *UART0; - #endif - #ifdef _UART1 - EXT UART_TypeDef *UART1; - #endif - #ifdef _UART2 - EXT UART_TypeDef *UART2; - #endif - #ifdef _UART3 - EXT UART_TypeDef *UART3; - #endif - #endif - - #ifdef _USB - EXT USB_TypeDef *USB; - #endif - - #ifdef _WDG - EXT WDG_TypeDef *WDG; - #endif - - #ifdef _XTI - EXT XTI_TypeDef *XTI; - #endif - - #ifdef _IRQVectors - EXT IRQVectors_TypeDef *IRQVectors; - #endif - -#endif /* LIBDEBUG */ - -#endif /* __71x_map_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/71x_type.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/71x_type.h deleted file mode 100644 index ccf60ae1d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/71x_type.h +++ /dev/null @@ -1,51 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : 71x_type.h -* Author : MCD Application Team -* Date First Issued : 05/16/2003 -* Description : Common data types -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef _71x_type_H -#define _71x_type_H - -typedef unsigned long u32; -typedef unsigned short u16; -typedef unsigned char u8; - -typedef signed long s32; -typedef signed short s16; -typedef signed char s8; - -typedef volatile unsigned long vu32; -typedef volatile unsigned short vu16; -typedef volatile unsigned char vu8; - -typedef volatile signed long vs32; -typedef volatile signed short vs16; -typedef volatile signed char vs8; - -/*===================================================================*/ -typedef enum { FALSE = 0, TRUE = !FALSE } bool; -/*===================================================================*/ -typedef enum { RESET = 0, SET = !RESET } FlagStatus; -/*===================================================================*/ -typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -/*===================================================================*/ -typedef enum { INDIRECT = 0, DIRECT = !INDIRECT} RegisterAccess; -/*===================================================================*/ - -#endif /* _71x_type_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/adc12.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/adc12.h deleted file mode 100644 index a3c0581fd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/adc12.h +++ /dev/null @@ -1,181 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : adc12.h -* Author : MCD Application Team -* Date First Issued : 07/31/2003 -* Description : ADC12 functions prototypes -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef _ADC12_H -#define _ADC12_H - -#include "71x_map.h" -#include "rccu.h" - -//--------------------ADC12 Conversion modes----------------------------------- -typedef enum -{ - ADC12_SINGLE, - ADC12_ROUND -} ADC12_Modes; - -//--------------------ADC12 Channels------------------------------------------- -typedef enum -{ - ADC12_CHANNEL0 = 0x00, - ADC12_CHANNEL1 = 0x10, - ADC12_CHANNEL2 = 0x20, - ADC12_CHANNEL3 = 0x30 -} ADC12_Channels; - -//--------------------ADC12 control status register flag----------------------- -typedef enum -{ - ADC12_DA0 = 0x01, - ADC12_DA1 = 0x02, - ADC12_DA2 = 0x04, - ADC12_DA3 = 0x08, - ADC12_OR = 0x2000 -} ADC12_Flags; - -// Masks for the update of interrupt bit for channel n -#define ADC12_IT0_Mask 0x0100 -#define ADC12_IT1_Mask 0x0200 -#define ADC12_IT2_Mask 0x0400 -#define ADC12_IT3_Mask 0x0800 - -//Mask for the update of all the interrupt bit in the CSR -#define ADC12_IT_Mask 0x0F00 - -//Mask for Selecting mode -#define ADC12_Mode_Mask 0x0040 - -//Mask for configuring the converter -#define ADC12_Start_Mask 0x0020 - -/******************************************************************************* -* Function Name : ADC12_Init -* Description : Intialize the ADC -* Input : None. -* Return : None. -*******************************************************************************/ -void ADC12_Init(void); - -/******************************************************************************* -* Function Name : ADC12_ConversionStart -* Description : start the Conversion. -* Input : None -* Return : None -*******************************************************************************/ -INLINE void ADC12_ConversionStart (void) -{ - // Set the ADCen bit of the bootconf register - PCU->BOOTCR |= ADC12_Start_Mask; -} - -/******************************************************************************* -* Function Name : ADC12_ConversionStop -* Description : Disable the ADC -* Input : None. -* Return : None. -*******************************************************************************/ -INLINE void ADC12_ConversionStop(void) -{ - // Clear the ADCen bit of the bootconf register - PCU->BOOTCR &= ~ADC12_Start_Mask; -} - -/******************************************************************************* -* Function Name : ADC12_ModeConfig -* Description : Configure the mode of conversion -* Input : ADC12_SINGLE: single channel mode -* ADC12_ROUND : round robin mode -* Return : None -*******************************************************************************/ -INLINE void ADC12_ModeConfig (ADC12_Modes ConversionMode) -{ - // Select the mode of conversion and update the CSR[6] - ADC12->CSR= ConversionMode == ADC12_SINGLE ? ADC12->CSR | ADC12_Mode_Mask :\ - ADC12->CSR & ~ADC12_Mode_Mask; -} - -/******************************************************************************* -* Function Name : ADC12_PrescalerConfig -* Description : Configure the prescaler -* Input : Adc12_clk: Sampling frequency. -* Return : None. -*******************************************************************************/ -void ADC12_PrescalerConfig(u32 Adc12_clk); - -/******************************************************************************* -* Function Name : ADC12_ChannelSelect -* Description : select the channel passed as parameter to be converted. -* Input : ADC12_Channel: channel selected to be converted it may be -* ADC12_CHANNEL0 : select channel 0 -* ADC12_CHANNEL1 : select channel 1 -* ADC12_CHANNEL2 : select channel 2 -* ADC12_CHANNEL3 : select channel 3 -* Return : None -*******************************************************************************/ -INLINE void ADC12_ChannelSelect(ADC12_Channels ADC12_Channel) -{ - // Update the CSR by the value of the selected channel - ADC12->CSR |= ADC12_Channel; -} - -/******************************************************************************* -* Function Name : ADC12_FlagStatus -* Description : test if the flag passed in parameter is set or not -* Input : ADC12_DA0 :Data Available on Channel 0 -* ADC12_DA1 :Data Available on Channel 1 -* ADC12_DA2 :Data Available on Channel 2 -* ADC12_DA3 :Data Available on Channel 3 -* ADC12_OR :Overrun -* Return : SET: if the flag is set -* RESET: if the flag is clear -*******************************************************************************/ -INLINE FlagStatus ADC12_FlagStatus (ADC12_Flags flag) -{ - // Test on the flag status and return set or RESET - return ADC12->CSR & flag ? SET : RESET; -} - -/******************************************************************************* -* Function Name : ADC12_ConversionValue -* Description : Read the conversion result from the data register. -* Input : ADC12_Channel :number of the register to read -* ADC12_CHANNEL0 : read the DATA0 register -* ADC12_CHANNEL1 : read the DATA1 register -* ADC12_CHANNEL2 : read the DATA2 register -* ADC12_CHANNEL3 : read the DATA3 register -* Return : the register value of the channel converted -*******************************************************************************/ -INLINE u16 ADC12_ConversionValue( ADC12_Channels ADC12_Channel) -{ - // Clear the corespondent DA bit - ADC12->CSR &= ~(1<<(ADC12_Channel >> 4)); - // Only the 12 MSB of the DATAn Register are taken - return *(u16 *)(ADC12_BASE + (ADC12_Channel >> 1)) >> 4; -} - -/******************************************************************************* -* Function Name : ADC12_ITConfig -* Description : enable or disable the interruption -* Input : status=ENABLE=>enable interrupt -* status=DISABLE=>disable interrupt -* Return : None -*******************************************************************************/ -void ADC12_ITConfig (FunctionalState NewState); - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/apb.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/apb.h deleted file mode 100644 index 2e512d97d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/apb.h +++ /dev/null @@ -1,89 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : apb.h -* Author : MCD Application Team -* Date First Issued : 05/30/2003 -* Description : This file contains all the functions prototypes for the -* APB bridge software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __APB_H -#define __APB_H - -#include "71x_map.h" - -/* APB1 Peripherals */ -#define I2C0_Periph 0x0000 -#define I2C1_Periph 0x0002 -#define UART0_Periph 0x0008 -#define UART1_Periph 0x0010 -#define UART2_Periph 0x0020 -#define UART3_Periph 0x0080 -#define USB_Periph 0x0100 -#define CAN_Periph 0x0200 -#define BSPI0_Periph 0x0400 -#define BSPI1_Periph 0x0800 -#define HDLC_Periph 0x2000 - -/* APB2 Peripherals */ -#define XTI_Periph 0x0000 -#define GPIO0_Periph 0x0002 -#define GPIO1_Periph 0x0004 -#define GPIO2_Periph 0x0008 -#define ADC12_Periph 0x0010 -#define TIM0_Periph 0x0080 -#define TIM1_Periph 0x0200 -#define TIM2_Periph 0x0400 -#define TIM3_Periph 0x0800 -#define RTC_Periph 0x1000 -#define WDG_Periph 0x2000 -#define EIC_Periph 0x4000 - -/******************************************************************************* -* Function Name : APB_ClockConfig -* Description : Enables/Disables the Clock gating for peripherals on the APB -* bridge passed in parameters. -* Input : APBx ( APB1 or APB2 ) -* NewState ENABLE or DISABLE -* NewValue (u16) -* Return : None -*******************************************************************************/ -INLINE void APB_ClockConfig ( APB_TypeDef *APBx, - FunctionalState NewState, - u16 NewValue ) -{ - if (NewState == ENABLE) APBx->CKDIS &= ~NewValue; - else APBx->CKDIS |= NewValue; -} - -/******************************************************************************* -* Function Name : APB_SwResetConfig -* Description : Enables/Disables the software Reset for peripherals on the APB -* bridge passed in parameters. -* Input : APBx ( APB1 or APB2 ) -* NewState ENABLE or DISABLE -* NewValue (u16) -* Return : None -*******************************************************************************/ -INLINE void APB_SwResetConfig ( APB_TypeDef *APBx, - FunctionalState NewState, - u16 NewValue ) -{ - if (NewState == ENABLE) APBx->SWRES |= NewValue; - else APBx->SWRES &= ~NewValue; -} - -#endif // __APB_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/bspi.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/bspi.h deleted file mode 100644 index 0761c500b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/bspi.h +++ /dev/null @@ -1,324 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : bspi.h -* Author : MCD Application Team -* Date First Issued : 16/05/2003 -* Description : This file contains all the functions prototypes for the -* BSPI software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __bspi_H -#define __bspi_H - -#include "71x_map.h" - -typedef enum { - BSPI_BERIT = 0x80, - BSPI_RCIT = 0x10, - BSPI_ALL = 0x90 -} BSPI_ITS; - -typedef enum { - BSPI_BERR = 0x004, - BSPI_RFNE = 0x008, - BSPI_RFF = 0x010, - BSPI_ROFL = 0x020, - BSPI_TFE = 0x040, - BSPI_TUFL = 0x080, - BSPI_TFF = 0x100, - BSPI_TFNE = 0x200 -} BSPI_Flags; - -typedef enum { - BSPI_TR_FE, - BSPI_TR_UFL, - BSPI_TR_FF, - BSPI_TR_DIS -} BSPI_TR_IT_SRCS; - -typedef enum { - BSPI_RC_FNE, - BSPI_RC_FF, - BSPI_RC_DIS -} BSPI_RC_IR_SRCS; - -#define BSPI_PESET_Mask 0x01 -#define BSPI_DFIFO_Mask 0xFFFE -#define BSPI_CPHA_Mask 0x200 -#define BSPI_CPOL_Mask 0x100 -#define BSPI_BSPI0_Base 0xA000 -#define BSPI_BSPI1_Base 0xB000 - - -/******************************************************************************* -* Function Name : BSPI_BSPI0Conf -* Description : configure STARM71x on BSPI0 mode. -* Input 2 : NewState: specifies the status of the BSPI -* : NewState value must be either ENABLE or DISABLE: -* : ENABLE: the specified BSPI0 peripheral will be enabled. -* : DISABLE: the specified BSPI0 peripheral will be disabled.. -* Output : SPI0 EN bit in BOOTCR. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_BSPI0Conf(FunctionalState NewState) -{ - if (NewState == ENABLE) PCU->BOOTCR |= 0x04; else PCU->BOOTCR &= ~0x04; -} - -/******************************************************************************* -* Function Name : BSPI_Init -* Description : Initializes BSPI peripheral control and registers to their default reset values. -* Input : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Output : BSPI peripheral registers and BSPI global variables are initialized. -* Return : None. -*******************************************************************************/ -void BSPI_Init( BSPI_TypeDef *BSPIx); - -/******************************************************************************* -* Function Name : BSPI_Enable -* Description : Enables/disables the specified BSPI peripheral. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral to be enabled or disabled. -* Input 2 : NewState: specifies the status of the BSPI -* : NewState value must be either ENABLE or DISABLE: -* : ENABLE: the specified BSPI peripheral will be enabled. -* : DISABLE: the specified BSPI peripheral will be disabled. -* Output : BSPE bit in BSPCSR1. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_Enable( BSPI_TypeDef *BSPIx, FunctionalState NewState) -{ - if (NewState == ENABLE) BSPIx->CSR1 |= BSPI_PESET_Mask; - else BSPIx->CSR1 &= ~BSPI_PESET_Mask; -} - -/******************************************************************************* -* Function Name : BSPI_MasterEnable -* Description : Configures the BSPI as a Master or a Slave. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : NewState: specifies whether configuring BSPI as master is enabled or disabled. -* : ENABLE: the specified BSPI will be configured as a master. -* : DISABLE: the specified BSPI will be configured as a slave. -* Output : MSTR bit in BSPCSR1 is modified register. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_MasterEnable(BSPI_TypeDef *BSPIx, FunctionalState NewState) -{ - if (NewState == ENABLE) BSPIx->CSR1 |= 0x02; else BSPIx->CSR1 &= ~0x02; -} - -/******************************************************************************* -* Function Name : BSPI_TrItSrc. -* Description : Configures the transmit interrupt source. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : TrItSrc: specifies the transmit interrupt source. -* : Refer to the section Transmit Interrupt Sources for more details on the -* : allowed values of this parameter. -* Output : TIE bit in BSPCSR2 register. -* Return : None. -*******************************************************************************/ -void BSPI_TrItSrc(BSPI_TypeDef *BSPIx, BSPI_TR_IT_SRCS TrItSrc); - -/******************************************************************************* -* Function Name : BSPI_RcItSrc. -* Description : Configures the receive interrupt source. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : RcItSrc: specifies the source for the receive interrupt. -* : Refer to the section Receive Interrupt Sources for more details on the -* : allowed values of this parameter. -* Output : RIE bit in BSPCSR1 is register. -* Return : None. -*******************************************************************************/ -void BSPI_RcItSrc(BSPI_TypeDef *BSPIx, BSPI_RC_IR_SRCS RcItSrc); - -/******************************************************************************* -* Function Name : BSPI_TrFifoDepth -* Description : Configures BSPI transmission FIFO number of words. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI. -* Input 2 : TDepth:specifies the depth of the transmit FIFO. -* Output : TFE bit in BSPCSR2 register. -* Return : None. -*******************************************************************************/ -void BSPI_TrFifoDepth(BSPI_TypeDef *BSPIx, u8 TDepth); - -/******************************************************************************* -* Function Name : BSPI_RcFifoDepth -* Description : Configures BSPI reception FIFO number of words. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : RDepth:specifies the depth of the receive FIFO. -* Output : RFE bits [3:0] in BSPCSR1 register. -* Return : None. -*******************************************************************************/ -void BSPI_RcFifoDepth(BSPI_TypeDef *BSPIx, u8 RDepth); - -/******************************************************************************* -* Function Name : BSPI_8bLEn -* Description : Sets the word length of the receive FIFO and transmit data registers to either 8 or 16 bits. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI. -* Input 2 : status: specifies if the word length is 8 or 16 bits. -* : status value must be either ENABLE or DISABLE: -* : ENABLE: to enable setting the word length to 8 bits. -* : DISABLE: disables setting the word length to 8 bits: the wordlength will be configured to 16 bits. -* Output : WL bits in BSPCSR1 register. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_8bLEn(BSPI_TypeDef *BSPIx, FunctionalState NewState) -{ - if (NewState == DISABLE) BSPIx->CSR1 |= 0x0400; else BSPIx->CSR1 &= ~0x0C00; -} - -/******************************************************************************* -* Function Name : BSPI_ClkFEdge -* Description : Enables capturing the first data sample on the first edge of SCK or on the second edge. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : NewState: specifies whether capturing the first data sample on the first edge of SCK is enabled or disabled. -* : status value must be either ENABLE or DISABLE. -* :DISABLE: to enable capturing the first data sample on the first edge of SCK. -* : ENABLE: to enable capturing the first data sample on the second edge of SCK. -* Output : CPHA bits in BSPCSR1 register. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_ClkFEdge(BSPI_TypeDef *BSPIx, FunctionalState NewState) -{ - if (NewState == ENABLE) BSPIx->CSR1 |= BSPI_CPHA_Mask; - else BSPIx->CSR1&=~BSPI_CPHA_Mask; -} - -/******************************************************************************* -* Function Name : BSPI_ClkActiveHigh -* Description : Configures the clock to be active high or low. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : NewState: specifies whether the clock is active high or low. -* : status value must be ENABLE or DISABLE. -* : ENABLE: configures the clock to be active high. -* : DISABLE: confgures the clock to be active low. -* Output : CPOL bits in BSPCSR1 register. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_ClkActiveHigh(BSPI_TypeDef *BSPIx, FunctionalState NewState) -{ - if (NewState == ENABLE) BSPIx->CSR1 |= BSPI_CPOL_Mask; - else BSPIx->CSR1 &= ~BSPI_CPOL_Mask; -} - -/******************************************************************************* -* Function Name : BSPI_FifoDisable -* Description : Configure the BSPI FIFO. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Output : DFIFO bit in BSPCSR2 register. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_FifoDisable(BSPI_TypeDef *BSPIx) -{ - BSPIx->CSR2 |= 0x0001; -} - -/******************************************************************************* -* Function Name : BSPI_ClockDividerConfig -* Description : Configure BSPI clock divider -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI. -* Input 2 : Div: holds the value of the clock divider. -* Output : Div [7:0] bits in BSPCLK register. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_ClockDividerConfig(BSPI_TypeDef *BSPIx, u8 Div) -{ - BSPIx->CLK = Div; -} - -/******************************************************************************* -* Function Name : BSPI_FlagStatus. -* Description : Check whether the specified BSPI Flag is set or not. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : flag: specifies the flag to see the status. -* : Refer to the section BSPI Flags for more details on the allowed values of this parameter. -* Output : None. -* Return : FlagStatus type -* : SET: if the tested flag is set. -* : RESET: if the corresponding flag is reset. -*******************************************************************************/ -INLINE FlagStatus BSPI_FlagStatus(BSPI_TypeDef *BSPIx, BSPI_Flags flag) -{ - return (BSPIx->CSR2 & flag) != 0 ? SET : RESET; -} - -/******************************************************************************* -* Function Name : BSPI_WordSend. -* Description : Transmit a single Word. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : holds the word which will be transmitted. -* Output : BSPTXR register. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_WordSend(BSPI_TypeDef *BSPIx, u16 Data) -{ - if ((BSPIx->CSR1 & 0x0400) == 0) Data <<= 8; - BSPIx->TXR = Data; -} - -/******************************************************************************* -* Function Name : BSPI_BufferSend. -* Description : Transmits data from a buffer. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : PtrToBuffer is an u8 pointer to the first word of the buffer to be transmitted. -* Input 3 : NbOfWords parameter indicates the number of words saved in the buffer to be sent. -* Output : None. -* Return : None. -*******************************************************************************/ -void BSPI_BufferSend(BSPI_TypeDef *BSPIx, u8 *PtrToBuffer, u8 NbOfWords); - -/******************************************************************************* -* Function Name : BSPI_WordReceive. -* Description : Returns the recent received word. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Output : None. -* Return : The value of the received word. -*******************************************************************************/ -INLINE u16 BSPI_WordReceive(BSPI_TypeDef *BSPIx) -{ - return (BSPIx->CSR1 & 0x0400) == 0 ? BSPIx->RXR >> 8 : BSPIx->RXR; -} - -/******************************************************************************* -* Function Name : BSPI_BufferReceive. -* Description : Receives number of data words and stores them in user defined area. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : PtrToBuffer is an u8 pointer to the first word of the defined area to save the received buffer. -* Input 3 : NbOfWords parameter indicates the number of words to be received in the buffer. -* Output : None. -* Return : None. -*******************************************************************************/ -void BSPI_BufferReceive(BSPI_TypeDef *BSPIx, u8 *PtrToBuffer, u8 NbOfWords); - -/******************************************************************************* -* Function Name : BSPI_ItEnable. -* Description : Enable the specified interrupt. -* Input 1 : BSPIx where x can be 0 or 1 to select the BSPI peripheral. -* Input 2 : BSPI_IT: specifies the BSPI interrupt. -* : Refer to the section Interrupt Enable for more details on the allowed values of this parameter.. -* Input 3 : NewState: specified whether the BSPI interrupt is enabled or disabled. -* : status value must be either ENABLE or DISABLE. -* : ENABLE: to enable interrupt -* : DISABLE: to disable interrupt. -* Output : BSPCSR1 register. -* Return : None. -*******************************************************************************/ -INLINE void BSPI_ItEnable(BSPI_TypeDef *BSPIx, BSPI_ITS BSPI_IE, FunctionalState NewState) -{ - if (NewState == ENABLE) BSPIx->CSR1 |= BSPI_IE; else BSPIx->CSR1 &= ~BSPI_IE; -} - -#endif /* __bspi_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/can.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/can.h deleted file mode 100644 index 7a97e2125..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/can.h +++ /dev/null @@ -1,404 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : can.h -* Author : MCD Application Team -* Date First Issued : 27/10/2003 -* Description : This file contains all the functions prototypes for the -* CAN bus software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __can_H -#define __can_H - -#include "71x_map.h" - -// Standard bitrates available -enum -{ - CAN_BITRATE_100K, - CAN_BITRATE_125K, - CAN_BITRATE_250K, - CAN_BITRATE_500K, - CAN_BITRATE_1M -}; - -// Control register -#define CAN_CR_TEST 0x0080 -#define CAN_CR_CCE 0x0040 -#define CAN_CR_DAR 0x0020 -#define CAN_CR_EIE 0x0008 -#define CAN_CR_SIE 0x0004 -#define CAN_CR_IE 0x0002 -#define CAN_CR_INIT 0x0001 - -// Status register -#define CAN_SR_LEC 0x0007 -#define CAN_SR_TXOK 0x0008 -#define CAN_SR_RXOK 0x0010 -#define CAN_SR_EPASS 0x0020 -#define CAN_SR_EWARN 0x0040 -#define CAN_SR_BOFF 0x0080 - -// Test register -#define CAN_TESTR_RX 0x0080 -#define CAN_TESTR_TX1 0x0040 -#define CAN_TESTR_TX0 0x0020 -#define CAN_TESTR_LBACK 0x0010 -#define CAN_TESTR_SILENT 0x0008 -#define CAN_TESTR_BASIC 0x0004 - -// IFn / Command Request register -#define CAN_CRR_BUSY 0x8000 - -// IFn / Command Mask register -#define CAN_CMR_WRRD 0x0080 -#define CAN_CMR_MASK 0x0040 -#define CAN_CMR_ARB 0x0020 -#define CAN_CMR_CONTROL 0x0010 -#define CAN_CMR_CLRINTPND 0x0008 -#define CAN_CMR_TXRQST 0x0004 -#define CAN_CMR_DATAA 0x0002 -#define CAN_CMR_DATAB 0x0001 - -// IFn / Mask 2 register -#define CAN_M2R_MXTD 0x8000 -#define CAN_M2R_MDIR 0x4000 - -// IFn / Arbitration 2 register -#define CAN_A2R_MSGVAL 0x8000 -#define CAN_A2R_XTD 0x4000 -#define CAN_A2R_DIR 0x2000 - -// IFn / Message Control register -#define CAN_MCR_NEWDAT 0x8000 -#define CAN_MCR_MSGLST 0x4000 -#define CAN_MCR_INTPND 0x2000 -#define CAN_MCR_UMASK 0x1000 -#define CAN_MCR_TXIE 0x0800 -#define CAN_MCR_RXIE 0x0400 -#define CAN_MCR_RMTEN 0x0200 -#define CAN_MCR_TXRQST 0x0100 -#define CAN_MCR_EOB 0x0080 - - -// Wake-up modes -enum -{ - CAN_WAKEUP_ON_EXT, - CAN_WAKEUP_ON_CAN -}; - - -// CAN message structure -typedef struct -{ - u32 IdType; - vu32 Id; - vu8 Dlc; - vu8 Data[8]; -} canmsg; - -// message ID types -enum -{ - CAN_STD_ID, - CAN_EXT_ID -}; - -// message ID limits -#define CAN_LAST_STD_ID ((1<<11) - 1) -#define CAN_LAST_EXT_ID ((1L<<29) - 1) - -/******************************************************************************* -* Function Name : CAN_EnterInitMode -* Description : Switch the CAN into initialization mode -* Input 1 : any binary value formed from the CAN_CR_xxx defines -* Output : None -* Return : None -* Note : CAN_LeaveInitMode must be called when all is done -*******************************************************************************/ -INLINE void CAN_EnterInitMode(u8 mask) -{ - CAN->CR = mask | CAN_CR_INIT; - CAN->SR = 0; // reset the status -} - -/******************************************************************************* -* Function Name : CAN_LeaveInitMode -* Description : Leave the initialization mode (switch into normal mode) -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -INLINE void CAN_LeaveInitMode(void) -{ - CAN->CR &= ~(CAN_CR_INIT | CAN_CR_CCE); -} - -/******************************************************************************* -* Function Name : CAN_EnterTestMode -* Description : Switch the CAN into test mode -* Input 1 : any binary value formed from the CAN_TESTR_xxx defines -* Output : None -* Return : None -* Note : CAN_LeaveTestMode must be called when all is done -*******************************************************************************/ -INLINE void CAN_EnterTestMode(u8 mask) -{ - CAN->CR |= CAN_CR_TEST; - CAN->TESTR |= mask; -} - -/******************************************************************************* -* Function Name : CAN_LeaveTestMode -* Description : Leave the current test mode (switch into normal mode) -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -INLINE void CAN_LeaveTestMode(void) -{ - CAN->CR |= CAN_CR_TEST; - CAN->TESTR &= ~(CAN_TESTR_LBACK | CAN_TESTR_SILENT | CAN_TESTR_BASIC); - CAN->CR &= ~CAN_CR_TEST; -} - -/******************************************************************************* -* Function Name : CAN_SetBitrate -* Description : Setup a standard CAN bitrate -* Input 1 : one of the CAN_BITRATE_xxx defines -* Output : None -* Return : None -* Note : CAN must be in initialization mode -*******************************************************************************/ -void CAN_SetBitrate(u32 bitrate); - -/******************************************************************************* -* Function Name : CAN_SetTiming -* Description : Setup the CAN timing with specific parameters -* Input 1 : Time Segment before the sample point position, from 1 to 16 -* Input 2 : Time Segment after the sample point position, from 1 to 8 -* Input 3 : Synchronisation Jump Width, from 1 to 4 -* Input 4 : Baud Rate Prescaler, from 1 to 1024 -* Output : None -* Return : None -* Note : CAN must be in initialization mode -*******************************************************************************/ -void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp); - -/******************************************************************************* -* Function Name : CAN_SleepRequest -* Description : Request the CAN cell to enter sleep mode -* Input 1 : CAN_WAKEUP_ON_EXT or CAN_WAKEUP_ON_CAN -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SleepRequest(u32 WakeupMode); - -/******************************************************************************* -* Function Name : CAN_SetUnusedMsgObj -* Description : Configure the message object as unused -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetUnusedMsgObj(u32 msgobj); - -/******************************************************************************* -* Function Name : CAN_SetTxMsgObj -* Description : Configure the message object as TX -* Input 1 : message object number, from 0 to 31 -* Input 2 : CAN_STD_ID or CAN_EXT_ID -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetTxMsgObj(u32 msgobj, u32 idType); - -/******************************************************************************* -* Function Name : CAN_SetRxMsgObj -* Description : Configure the message object as RX -* Input 1 : message object number, from 0 to 31 -* Input 2 : CAN_STD_ID or CAN_EXT_ID -* Input 3 : low part of the identifier range used for acceptance filtering -* Input 4 : high part of the identifier range used for acceptance filtering -* Input 5 : TRUE for a single receive object or a FIFO receive object that -* is the last one of the FIFO -* FALSE for a FIFO receive object that is not the last one -* Output : None -* Return : None -*******************************************************************************/ -void CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast); - -/******************************************************************************* -* Function Name : CAN_InvalidateAllMsgObj -* Description : Configure all the message objects as unused -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_InvalidateAllMsgObj(void); - -/******************************************************************************* -* Function Name : CAN_Init -* Description : Initialize the CAN cell and set the bitrate -* Input 1 : any binary value formed from the CAN_CTL_xxx defines -* Input 2 : one of the CAN_BITRATE_xxx defines -* Output : None -* Return : None -*******************************************************************************/ -void CAN_Init(u8 mask, u32 bitrate); - -/******************************************************************************* -* Function Name : CAN_ReleaseMessage -* Description : Release the message object -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -*******************************************************************************/ -void CAN_ReleaseMessage(u32 msgobj); - -/******************************************************************************* -* Function Name : CAN_ReleaseTxMessage -* Description : Release the transmit message object -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -* Note : assume that message interface 0 is free -*******************************************************************************/ -INLINE void CAN_ReleaseTxMessage(u32 msgobj) -{ - CAN->sMsgObj[0].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQST; - CAN->sMsgObj[0].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_ReleaseRxMessage -* Description : Release the receive message object -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : None -* Note : assume that message interface 1 is free -*******************************************************************************/ -INLINE void CAN_ReleaseRxMessage(u32 msgobj) -{ - CAN->sMsgObj[1].CMR = CAN_CMR_CLRINTPND | CAN_CMR_TXRQST; - CAN->sMsgObj[1].CRR = 1 + msgobj; -} - -/******************************************************************************* -* Function Name : CAN_SendMessage -* Description : Start transmission of a message -* Input 1 : message object number, from 0 to 31 -* Input 2 : pointer to the message structure containing data to transmit -* Output : None -* Return : 1 if transmission was OK, else 0 -*******************************************************************************/ -u32 CAN_SendMessage(u32 msgobj, canmsg* pCanMsg); - -/******************************************************************************* -* Function Name : CAN_ReceiveMessage -* Description : Get the message, if received -* Input 1 : message object number, from 0 to 31 -* Input 2 : if TRUE, the message object is released when getting the data -* if FALSE, the message object is not released -* Input 3 : pointer to the message structure where received data is stored -* Output : None -* Return : 1 if reception was OK, else 0 (no message pending) -*******************************************************************************/ -u32 CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg); - -/******************************************************************************* -* Function Name : CAN_WaitEndOfTx -* Description : Wait until current transmission is finished -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void CAN_WaitEndOfTx(void); - -/******************************************************************************* -* Function Name : CAN_BasicSendMessage -* Description : Start transmission of a message in BASIC mode -* Input 1 : pointer to the message structure containing data to transmit -* Output : None -* Return : 1 if transmission was OK, else 0 -* Note : CAN must be in BASIC mode -*******************************************************************************/ -u32 CAN_BasicSendMessage(canmsg* pCanMsg); - -/******************************************************************************* -* Function Name : CAN_BasicReceiveMessage -* Description : Get the message in BASIC mode, if received -* Input 1 : pointer to the message structure where received data is stored -* Output : None -* Return : 1 if reception was OK, else 0 (no message pending) -* Note : CAN must be in BASIC mode -*******************************************************************************/ -u32 CAN_BasicReceiveMessage(canmsg* pCanMsg); - -/******************************************************************************* -* Function Name : CAN_IsMessageWaiting -* Description : Test the waiting status of a received message -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : A non-zero value if the corresponding message object has -* received a message waiting to be copied, else 0 -*******************************************************************************/ -INLINE u32 CAN_IsMessageWaiting(u32 msgobj) -{ - return (msgobj < 16 ? CAN->ND1R & (1 << msgobj) : CAN->ND2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsTransmitRequested -* Description : Test the request status of a transmitted message -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : A non-zero value if the corresponding message is requested -* to transmit, else 0 -*******************************************************************************/ -INLINE u32 CAN_IsTransmitRequested(u32 msgobj) -{ - return (msgobj < 16 ? CAN->TR1R & (1 << msgobj) : CAN->TR2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsInterruptPending -* Description : Test the interrupt status of a message object -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : A non-zero value if the corresponding message has an interrupt -* pending, else 0 -*******************************************************************************/ -INLINE u32 CAN_IsInterruptPending(u32 msgobj) -{ - return (msgobj < 16 ? CAN->IP1R & (1 << msgobj) : CAN->IP2R & (1 << (msgobj-16))); -} - -/******************************************************************************* -* Function Name : CAN_IsObjectValid -* Description : Test the validity of a message object (ready to use) -* Input 1 : message object number, from 0 to 31 -* Output : None -* Return : A non-zero value if the corresponding message object is valid, -* else 0 -*******************************************************************************/ -INLINE u32 CAN_IsObjectValid(u32 msgobj) -{ - return (msgobj < 16 ? CAN->MV1R & (1 << msgobj) : CAN->MV2R & (1 << (msgobj-16))); -} - -#endif /* __can_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/eic.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/eic.h deleted file mode 100644 index ee691d95a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/eic.h +++ /dev/null @@ -1,200 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : eic.h -* Author : MCD Application Team -* Date First Issued : 25/06/2003 -* Description : This file contains all the functions prototypes for the -* EIC software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __eic_H -#define __eic_H - -#include "71x_map.h" - -typedef enum -{ - T0TIMI_IRQChannel = 0, - FLASH_IRQChannel = 1, - RCCU_IRQChannel = 2, - RTC_IRQChannel = 3, - WDG_IRQChannel = 4, - XTI_IRQChannel = 5, - USBHP_IRQChannel = 6, - I2C0ITERR_IRQChannel = 7, - I2C1ITERR_IRQChannel = 8, - UART0_IRQChannel = 9, - UART1_IRQChannel = 10, - UART2_IRQChannel = 11, - UART3_IRQChannel = 12, - SPI0_IRQChannel = 13, - SPI1_IRQChannel = 14, - I2C0_IRQChannel = 15, - I2C1_IRQChannel = 16, - CAN_IRQChannel = 17, - ADC_IRQChannel = 18, - T1TIMI_IRQChannel = 19, - T2TIMI_IRQChannel = 20, - T3TIMI_IRQChannel = 21, - HDLC_IRQChannel = 25, - USBLP_IRQChannel = 26, - T0TOI_IRQChannel = 29, - T0OC1_IRQChannel = 30, - T0OC2_IRQChannel = 31 -} IRQChannel_TypeDef; - -typedef enum -{ - T0TIMI_FIQChannel = 0x00000001, - WDG_FIQChannel = 0x00000002, - WDGT0TIMI_FIQChannels = 0x00000003 -} FIQChannel_TypeDef; - -/******************************************************************************* -* Function Name : EIC_Init -* Description : Initialise the EIC using the load PC instruction -* (PC = PC +offset) -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void EIC_Init(void); - -/******************************************************************************* -* Function Name : EIC_IRQConfig -* Description : Enable or Disable IRQ interrupts -* Input 1 : New status : can be ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -INLINE void EIC_IRQConfig(FunctionalState NewState) -{ - if (NewState==ENABLE) EIC->ICR |= 0x0001; else EIC->ICR &= ~0x0001; -} - -/******************************************************************************* -* Function Name : EIC_FIQConfig -* Description : Enable or Disable FIQ interrupts -* Input 1 : New status : can be ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -INLINE void EIC_FIQConfig(FunctionalState NewState) -{ - if (NewState==ENABLE) EIC->ICR |= 0x0002; else EIC->ICR &= ~0x0002; -} - -/******************************************************************************* -* Function Name : EIC_IRQChannelConfig -* Description : Configure the IRQ Channel -* Input 1 : IRQ channel name -* Input 2 : Channel New status : can be ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -INLINE void EIC_IRQChannelConfig(IRQChannel_TypeDef IRQChannel, FunctionalState NewState) -{ - if (NewState==ENABLE) EIC->IER |= 0x0001 << IRQChannel; - else EIC->IER &= ~(0x0001 << IRQChannel); -} - -/******************************************************************************* -* Function Name : EIC_FIQChannelConfig -* Description : Configure the FIQ Channel -* Input 1 : FIQ channel name -* Input 2 : Channel New status : can be ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -INLINE void EIC_FIQChannelConfig(FIQChannel_TypeDef FIQChannel, - FunctionalState NewState) -{ - if (NewState==ENABLE) EIC->FIR |= FIQChannel; - else EIC->FIR &= ~FIQChannel; -} - -/******************************************************************************* -* Function Name : EIC_IRQChannelPriorityConfig -* Description : Configure the selected IRQ channel priority -* Input 1 : IRQ channel name -* Input 2 : IRQ channel priority -* Output : None -* Return : None -*******************************************************************************/ -INLINE void EIC_IRQChannelPriorityConfig(IRQChannel_TypeDef IRQChannel, u8 Priority) -{ - EIC->SIR[IRQChannel] = (EIC->SIR[IRQChannel]&0xFFFF0000) | (u16)Priority & 0x000F; -} - -/******************************************************************************* -* Function Name : EIC_CurrentPriorityLevelConfig -* Description : Change the current priority level of the srved IRQ routine -* Input 1 : New priority -* Output : None -* Return : None -*******************************************************************************/ -void EIC_CurrentPriorityLevelConfig(u8 NewPriorityLevel); - -/******************************************************************************* -* Function Name : EIC_CurrentPriorityLevelValue -* Description : Return the current priority level of the current served IRQ -* routine -* Input : None -* Output : None -* Return : The current priority level -*******************************************************************************/ -INLINE u8 EIC_CurrentPriorityLevelValue(void) -{ - return EIC->CIPR & 0xF; -} - -/******************************************************************************* -* Function Name : EIC_CurrentIRQChannelValue -* Description : Return the current served IRQ channel number -* Input 0 : None -* Output : None -* Return : The current served IRQ channel number -*******************************************************************************/ -INLINE IRQChannel_TypeDef EIC_CurrentIRQChannelValue(void) -{ - return (IRQChannel_TypeDef)(EIC->CICR & 0x1F); -} - -/******************************************************************************* -* Function Name : EIC_CurrentFIQChannelValue -* Description : Return the current served FIQ channel number -* Input : None -* Output : None -* Return : The current served FIQ channel number -*******************************************************************************/ -INLINE FIQChannel_TypeDef EIC_CurrentFIQChannelValue(void) -{ - return (FIQChannel_TypeDef)((EIC->FIR >> 2) & 0x0003); -} - -/******************************************************************************* -* Function Name : EIC_FIPendingBitClear -* Description : Clear the FIQ pending bit -* Input 1 : FIQ channel -* Output : None -* Return : None -*******************************************************************************/ -INLINE void EIC_FIQPendingBitClear(FIQChannel_TypeDef FIQChannel) -{ - EIC->FIR = (EIC->FIR & 0x0003) | (FIQChannel << 2); -} - -#endif /* __eic_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/emi.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/emi.h deleted file mode 100644 index 97c5115c9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/emi.h +++ /dev/null @@ -1,52 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : emi.h -* Author : MCD Application Team -* Date First Issued : 08/08/2003 -* Description : This file contains all the functions prototypes for the -* EMI software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef _EMI_H -#define _EMI_H - -#include "71x_map.h" - -#define EMI_ENABLE 0x8000 -#define EMI_DISABLE 0x0000 -#define EMI_WAITSTATE(n) ((n) << 2) -#define EMI_SIZE_8 0x0000 -#define EMI_SIZE_16 0x0001 - -#define EMI_BANK0 EXTMEM_BASE -#define EMI_BANK1 (EXTMEM_BASE + 0x2000000) -#define EMI_BANK2 (EXTMEM_BASE + 0x4000000) - -/******************************************************************************* -* Function Name : EMI_Config -* Description : This routine is used, for each bank, to configure enabling, -* : cycle length and bus size. -* Input : Bank (u8) -* : Config (u16) -* Return : None -*******************************************************************************/ -INLINE void EMI_Config(u8 Bank, u16 Config) -{ - *(u16 *)(EMI_BASE + (4*Bank)) = Config; -} - -#endif // _EMI_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/flash.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/flash.h deleted file mode 100644 index 6d6bb09d6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/flash.h +++ /dev/null @@ -1,253 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : flash.h -* Author : MCD Application Team -* Date First Issued : 28/07/2003 -* Description : This file contains all the functions prototypes for the -* Embedded Flash software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __FLASH_H -#define __FLASH_H - -#include "71x_map.h" - -#define FLASH_B0F0 0x00000001 -#define FLASH_B0F1 0x00000002 -#define FLASH_B0F2 0x00000004 -#define FLASH_B0F3 0x00000008 -#define FLASH_B0F4 0x00000010 -#define FLASH_B0F5 0x00000020 -#define FLASH_B0F6 0x00000040 -#define FLASH_B0F7 0x00000080 - -#define FLASH_B1F0 0x00010000 -#define FLASH_B1F1 0x00020000 - -#define FLASH_B0 (FLASH_B0F0 | FLASH_B0F1 | FLASH_B0F2 | FLASH_B0F3 | FLASH_B0F4 | FLASH_B0F5 | FLASH_B0F6 | FLASH_B0F7) -#define FLASH_B1 (FLASH_B1F0 | FLASH_B1F1) - -typedef enum -{ - FLASH_FINISHED, - FLASH_ONGOING -} flashwriteoperation; - -typedef enum -{ - FLASH_BANK0 = 0x1000000, - FLASH_BANK1 = 0x2000000 -} flashbanks; - -typedef enum -{ - FLASH_BSYA0 = 0x01, /* 000-00001 = 0000 0001 = 0x01 */ /* FLASH_CR0.1 */ - FLASH_BSYA1 = 0x02, /* 000-00010 = 0000 0010 = 0x02 */ /* FLASH_CR0.2 */ - FLASH_LOCK = 0x04, /* 000-00100 = 0000 0100 = 0x04 */ /* FLASH_CR0.4*/ - FLASH_INTP = 0x14, /* 000-10100 = 0001 0100 = 0x14 */ /* FLASH_CR0.20 */ - FLASH_B0S = 0x38, /* 001-11000 = 0011 1000 = 0x38 */ /* FLASH_CR1.24*/ - FLASH_B1S = 0x39, /* 001-11001 = 0011 1001 = 0x39 */ /* FLASH_CR1.25*/ - FLASH_ERR = 0xA0, /* 101-00000 = 1010 0000 = 0xA0 */ /* FLASH_ER.0*/ - FLASH_ERER = 0xA1, /* 101-00001 = 1010 0001 = 0xA1 */ /* FLASH_ER.1*/ - FLASH_PGER = 0xA2, /* 101-00010 = 1010 0010 = 0xA2 */ /* FLASH_ER.2*/ - FLASH_10ER = 0xA3, /* 101-00011 = 1010 0011 = 0xA3 */ /* FLASH_ER.3*/ - FLASH_SEQER = 0xA6, /* 101-00110 = 1010 0110 = 0xA6 */ /* FLASH_ER.6*/ - FLASH_RESER = 0xA7, /* 101-00111 = 1010 0111 = 0xA7 */ /* FLASH_ER.7*/ - FLASH_WPF = 0xA8 /* 101-01000 = 1010 1000 = 0xA8 */ /* FLASH_ER.8*/ -} flashflags; - -#define FLASH_WMS_Mask 0x80000000 -#define FLASH_SUSP_Mask 0x40000000 -#define FLASH_WPG_Mask 0x20000000 -#define FLASH_DWPG_Mask 0x10000000 -#define FLASH_SER_Mask 0x08000000 -#define FLASH_SPR_Mask 0x01000000 -#define FLASH_BER_Mask 0x04000000 -#define FLASH_MER_Mask 0x02000000 -#define FLASH_BSYA1_Mask 0x00000002 -#define FLASH_BSYA2_Mask 0x00000004 - -#define FLASH_DBGP_Mask 0x00000002 -#define FLASH_ACCP_Mask 0x00000001 - -#define FLASH_Reg_Mask 0xE0 -#define FLASH_Flag_Mask 0x1F - -#define FLASH_INTM_Mask 0x00200000 -#define FLASH_INTP_Mask 0x00100000 - -/******************************************************************************* -* Function Name : FLASH_Init -* Description : Initialise the Flash -* Input : None -* Return : None -*******************************************************************************/ -void FLASH_Init(void); - -/******************************************************************************* -* Function Name : FLASH_FlagStatus -* Description : Returns the NewState of Flash flags -* Input 1 : Flash Flag -* Return : flagstate -*******************************************************************************/ -FlagStatus FLASH_FlagStatus(flashflags Xflag); - -/******************************************************************************* -* Function Name : FLASH_WriteOpStatus -* Description : Checks the write operation status -* Input 1 : flash banck -* Return : write operation status -*******************************************************************************/ -INLINE FlagStatus FLASH_WriteOpStatus(flashbanks Xbank) -{ - return Xbank == FLASH_BANK0 ? FLASH_FlagStatus(FLASH_BSYA0) : FLASH_FlagStatus(FLASH_BSYA1); -} - -/******************************************************************************* -* Function Name : FLASH_WordWrite -* Description : Writes a Word to the Flash -* Input 1 : Address of the Destination -* Input 2 : Word to program -* Return : None -*******************************************************************************/ -void FLASH_WordWrite(u32 TargetAdd, u32 Data); - -/******************************************************************************* -* Function Name : FLASH_DWordWrite -* Description : Writes Double Word to the Flash -* Input 1 : Address of the Destination -* Input 2 : Word 1 To program -* Input 3 : Word 2 To program -* Return : None -*******************************************************************************/ -void FLASH_DWordWrite(u32 TargetAdd, u32 Data0, u32 Data1); - -/******************************************************************************* -* Function Name : FLASH_EraseSector -* Description : Erases a Flash sector -* Input 1 : Sectors to be Erased -* Return : None -*******************************************************************************/ -void FLASH_SectorErase(u32 Xsectors); - -/******************************************************************************* -* Function Name : FLASH_BankErase -* Description : Erases a Bank of the Flash -* Input 1 : Bank to be Erased -* Return : None -*******************************************************************************/ -INLINE void FLASH_BankErase(flashbanks Xbank) -{ - FLASH_SectorErase(Xbank == FLASH_BANK0 ? FLASH_B0 : FLASH_B1); -} -/******************************************************************************* -* Function Name : FLASH_Suspend -* Description : Suspends the current program or erase operation -* Input 1 : None -* Return : Flash CR0 register -*******************************************************************************/ -u32 FLASH_Suspend(void); - -/******************************************************************************* -* Function Name : FLASH_Resume -* Description : Resume a Suspended program or erase operation -* Input 1 : The operation to be resumed -* Return : None -*******************************************************************************/ -void FLASH_Resume(u32 FLASH_LastOperation); - -/******************************************************************************* -* Function Name : FLASH_WordRead -* Description : Read a single word of the flash -* Input 1 : Source Address -* Return : Word -*******************************************************************************/ -u32 FLASH_WordRead(u32 FLASH_SourceAdd); -/******************************************************************************* -* Function Name : FLASH_WritePrConfig -* Description : Configures The Write Protection Bits -* Input 1 : Flash Bank -* Input 2 : Enable or disable Protection -* Return : None -*******************************************************************************/ -void FLASH_WritePrConfig(u32 Xsectors, FunctionalState NewState); -/******************************************************************************* -* Function Name : FLASH_PermanantDebugPrConfig -* Description : Configures The Debug Protection Bits -* Input 1 : ENABLE or DISABLE -* Return : None -*******************************************************************************/ -void FLASH_PermanantDebugPrConfig(FunctionalState NewState); - -/******************************************************************************* -* Function Name : FLASH_FlagClear -* Description : Clears a flash flag -* Input 1 : Flash Flag -* Return : None -*******************************************************************************/ -void FLASH_FlagClear(flashflags Xflag); - -/******************************************************************************* -* Function Name : FLASH_ITConfig -* Description : Enables Or Disables the write-end interrupt -* Input 1 : FunctionalState(Enable, Disable) -* Return : None -*******************************************************************************/ -INLINE void FLASH_ITConfig(FunctionalState NewState) -{ - if (NewState == ENABLE) FLASHR->CR0 |= FLASH_INTM_Mask; - else FLASHR->CR0 &= ~FLASH_INTM_Mask; -} - -/******************************************************************************* -* Function Name : FLASH_ITStatus -* Description : Checks if the write-end interrupt is enabled or not -* Input 1 : None -* Return : Enable, Disable -*******************************************************************************/ -INLINE FunctionalState FLASH_ITStatus(void) -{ - return (FLASHR->CR0 & FLASH_INTM_Mask)==0 ? DISABLE : ENABLE; -} - -/******************************************************************************* -* Function Name : FLASH_ITClear -* Description : Clears an interrupt pending flag -* Input 1 : None -* Return : None -*******************************************************************************/ -INLINE void FLASH_ITClear(void) -{ - FLASHR->CR0 &= ~FLASH_INTM_Mask; -} - -/******************************************************************************* -* Function Name : FLASH_ProtectionLevel -* Description : Gives the level of protection in the PDS PEN registers -* Input 1 : None -* Return : The last bit not yet reset -*******************************************************************************/ -u16 FLASH_ProtectionLevel(void); - -/******************************************************************************* -* Function Name : FLASH_WaitForLastTask -* Description : Waits for the end of last task on a Flash Bank -* Input 1 : None -* Return : Nones -*******************************************************************************/ -void FLASH_WaitForLastTask(void); - -#endif // __FLASH_H - -/*******************(C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/gpio.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/gpio.h deleted file mode 100644 index 8b3f9d38d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/gpio.h +++ /dev/null @@ -1,127 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : gpio.h -* Author : MCD Application Team -* Date First Issued : 08/06/2003 -* Description : This file contains all the functions prototypes for the -* GPIO software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __gpio_H -#define __gpio_H - -#include "71x_map.h" - -typedef enum -{ - GPIO_HI_AIN_TRI, - GPIO_IN_TRI_TTL, - GPIO_IN_TRI_CMOS, - GPIO_IPUPD_WP, - GPIO_OUT_OD, - GPIO_OUT_PP, - GPIO_AF_OD, - GPIO_AF_PP -} GpioPinMode_TypeDef; - -#define GPIO_LSB 0x00 -#define GPIO_MSB 0x08 - -/******************************************************************************* -* Function Name : GPIO_Config -* Description : Configure the GPIO port pins -* Input 1 : GPIOx (x can be 0,1 or 2) the desired port -* Input 2 : Port_Pins : pins placements -* Input 3 : Pins Mode -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_Config (GPIO_TypeDef *GPIOx, u16 Port_Pins, GpioPinMode_TypeDef GPIO_Mode); - -/******************************************************************************* -* Function Name : GPIO_BitRead -* Description : Read the desired port pin value -* Input 1 : Selected GPIO port -* Input 2 : Pin number -* Output : None -* Return : The selected pin value -*******************************************************************************/ -INLINE u8 GPIO_BitRead(GPIO_TypeDef *GPIOx, u8 Port_Pin) -{ - return (GPIOx->PD >> Port_Pin) & 0x0001; -} - -/******************************************************************************* -* Function Name : GPIO_ByteRead -* Description : Read the desired port Byte value -* Input 1 : Selected GPIO port -* Input 2 : GPIO_MSB or GPIO_LSB -* Output : None -* Return : The GPIO_MSB or GPIO_LSB of the selected PD register -*******************************************************************************/ -INLINE u8 GPIO_ByteRead(GPIO_TypeDef *GPIOx, u8 Port_Byte) -{ - return (u8)(GPIOx->PD >> Port_Byte); -} - -/******************************************************************************* -* Function Name : GPIO_WordRead -* Description : Read the desired port word value -* Input 1 : Selected GPIO port -* Output : None -* Return : The selected PD register value -*******************************************************************************/ -INLINE u16 GPIO_WordRead(GPIO_TypeDef *GPIOx) -{ - return GPIOx->PD; -} - -/******************************************************************************* -* Function Name : GPIO_BitWrite -* Description : Set or reset the selected port pin -* Input 1 : Selected GPIO port -* Input 2 : Pin number -* Input 3 : bit value -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_BitWrite(GPIO_TypeDef *GPIOx, u8 Port_Pin, u8 Port_Val); - -/******************************************************************************* -* Function Name : GPIO_ByteWrite -* Description : Write byte value to the selected PD register -* Input 1 : Selected GPIO port -* Input 2 : GPIO_MSB or GPIO_LSB -* Input 3 : Byte value -* Output : None -* Return : None -*******************************************************************************/ -void GPIO_ByteWrite(GPIO_TypeDef *GPIOx, u8 Port_Byte, u8 Port_Val); - -/******************************************************************************* -* Function Name : GPIO_WordWrite -* Description : Write word value to the selected PD register -* Input 1 : Selected GPIO port -* Input 2 : Value -* Output : None -* Return : None -*******************************************************************************/ -INLINE void GPIO_WordWrite(GPIO_TypeDef *GPIOx, u16 Port_Val) -{ - GPIOx->PD = Port_Val; -} - -#endif /* __gpio_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/i2c.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/i2c.h deleted file mode 100644 index a4f98fbd8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/i2c.h +++ /dev/null @@ -1,357 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : i2c.h -* Author : MCD Application Team -* Date First Issued : 05/09/2003 -* Description : This file provides prototypes of I2C functions -* and variable used in code sources -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __i2c_H -#define __i2c_H - -#include "71x_map.h" - -typedef enum -{ - I2C_CR = 0x00, - I2C_SR1 = 0x04, - I2C_SR2 = 0x08, - I2C_CCR = 0x0C, - I2C_OAR1 = 0x10, - I2C_OAR2 = 0x14, - I2C_DR = 0x18, - I2C_ECCR = 0x1C -} I2C_Registers; - -typedef enum -{ - I2C_Mode10, - I2C_Mode7 -} I2C_Addressing; - -typedef enum -{ - I2C_RX, - I2C_TX -} I2C_Direction; - -typedef enum -{ - I2C_SB = 0x00001, - I2C_M_SL = 0x00002, - I2C_ADSL = 0x00004, - I2C_BTF = 0x00008, - I2C_BUSY = 0x00010, - I2C_TRA = 0x00020, - I2C_ADD10 = 0x00040, - I2C_EVF = 0x00080, - I2C_GCAL = 0x00100, - I2C_BERR = 0x00200, - I2C_ARLO = 0x00400, - I2C_STOPF = 0x00800, - I2C_AF = 0x01000, - I2C_ENDAD = 0x02000, - I2C_STOP = 0x08000, - I2C_ACK = 0x10000, - I2C_START = 0x20000 -} I2C_Flags; - -typedef enum -{ - I2C_TX_NO, - I2C_TX_SB, - I2C_TX_AF, - I2C_TX_ARLO, - I2C_TX_BERR, - I2C_TX_ADD_OK, - I2C_TX_DATA_OK, - I2C_TX_ONGOING -} I2C_Tx_Status; - -typedef enum -{ - I2C_RX_NO, - I2C_RX_SB, - I2C_RX_AF, - I2C_RX_ARLO, - I2C_RX_BERR, - I2C_RX_ADD_OK, - I2C_RX_DATA_OK, - I2C_RX_ONGOING -} I2C_Rx_Status; - -#define I2C_PESET_Mask 0x20 -#define I2C_PERESET 0xDF -#define I2C_ENGC_Mask 0x10 -#define I2C_START_Mask 0x08 -#define I2C_STOP_Mask 0x02 -#define I2C_ACK_Mask 0x04 -#define I2C_ITE_Mask 0x01 - -/******************************************************************************* -* Function Name : I2C_Init -* Description : Initializes I2C peripheral control and registers to their -* default reset values. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : None. -*******************************************************************************/ -void I2C_Init (I2C_TypeDef *I2Cx); - -/******************************************************************************* -* Function Name : I2C_OnOffConfig -* Description : Enables or disables I2C peripheral. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -void I2C_OnOffConfig (I2C_TypeDef *I2Cx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : I2C_GeneralCallConfig -* Description : Enables or disables I2C general call option. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -INLINE void I2C_GeneralCallConfig (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) I2Cx->CR |= I2C_ENGC_Mask; - else I2Cx->CR &= ~I2C_ENGC_Mask; -} - -/******************************************************************************* -* Function Name : I2C_STARTGenerate -* Description : Generates I2C communication START condition. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -INLINE void I2C_STARTGenerate (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) I2Cx->CR |= I2C_START_Mask; - else I2Cx->CR &= ~I2C_START_Mask; -} - -/******************************************************************************* -* Function Name : I2C_STOPGenerate -* Description : Generates I2C communication STOP condition. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -INLINE void I2C_STOPGenerate (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) I2Cx->CR |= I2C_STOP_Mask; - else I2Cx->CR &= ~I2C_STOP_Mask; -} - -/******************************************************************************* -* Function Name : I2C_AcknowledgeConfig -* Description : Enables or disables I2C acknowledge feature. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -INLINE void I2C_AcknowledgeConfig (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) I2Cx->CR |= I2C_ACK_Mask; - else I2Cx->CR &= ~I2C_ACK_Mask; -} - -/******************************************************************************* -* Function Name : I2C_ITConfig -* Description : Enables or disables I2C interrupt feature. -* Input : I2Cx ( I2C0 or I2C1 ) -* condition(ENABLE or DISABLE). -* Return : None. -*******************************************************************************/ -INLINE void I2C_ITConfig (I2C_TypeDef *I2Cx, FunctionalState NewState) -{ - if (NewState == ENABLE) I2Cx->CR |= I2C_ITE_Mask; - else I2Cx->CR &= ~I2C_ITE_Mask; -} - -/******************************************************************************* -* Function Name : I2C_RegisterRead -* Description : Reads any I2C register and returns its value. -* Input : I2Cx ( I2C0 or I2C1 ) -* Reg :the register to be read (I2CCR,I2CSR1,I2CSR2,I2CCCR, -* I2COAR1,I2COAR2,I2CDR,I2CECCR) -* Return : the value of the register passed as parameter(u8) -*******************************************************************************/ -INLINE u8 I2C_RegisterRead (I2C_TypeDef *I2Cx, I2C_Registers reg) -{ - return (*(u8 *)(*((u32 *)&I2Cx) + reg)); -} - -/******************************************************************************* -* Function Name : I2C_FlagStatus -* Description : Checks whether any I2C Flag is set or not. -* Input : I2Cx ( I2C0 or I2C1 ) -* Access(DIRECT or INDIRECT) -* Flag : the flag to be read -* input 4: an (u8) variable needed in the case -* of the INDIRECT access -* Return : the NewState of the Flag (SET or RESET). -*******************************************************************************/ -FlagStatus I2C_FlagStatus (I2C_TypeDef *I2Cx, RegisterAccess Access, I2C_Flags Flag,...); - -/******************************************************************************* -* Function Name : I2C_FlagClear -* Description : Clears the I2C Flag passed as a parameter -* Input : I2Cx ( I2C0 or I2C1 ) -* Flag : the flag to be read -* input3: an (u8) parameter needed in the case that the flag -* to be cleared need a write in one register -* Return : None. -*******************************************************************************/ -void I2C_FlagClear (I2C_TypeDef *I2Cx, I2C_Flags Flag,...); - -/******************************************************************************* -* Function Name : I2C_SpeedConfig -* Description : Selects I2C clock speed and configures its corresponding mode. -* Input : I2Cx ( I2C0 or I2C1 ) -* Clock: I2C expected clock in Hertz. -* Return : None. -*******************************************************************************/ -void I2C_SpeedConfig (I2C_TypeDef *I2Cx, u32 Clock); - -/******************************************************************************* -* Function Name : I2C_AddressConfig -* Description : Defines the I2C bus address of the interface. -* Input : I2Cx ( I2C0 or I2C1 ). -* Address: an u16 parameter indicating the address -* of the interface. -* Mode (I2C_Mode10,I2C_Mode7). -* Return : None. -*******************************************************************************/ -void I2C_AddressConfig (I2C_TypeDef *I2Cx, u16 Address, I2C_Addressing Mode); - -/******************************************************************************* -* Function Name : I2C_FCLKConfig -* Description : Configures frequency bits according to RCLK frequency. -* the I2C selected must be disabled -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : None. -*******************************************************************************/ -void I2C_FCLKConfig (I2C_TypeDef *I2Cx); - -/******************************************************************************* -* Function Name : I2C_AddressSend -* Description : Transmits the address byte to select the slave device. -* Input : I2Cx ( I2C0 or I2C1 ) -* Address: an u16 parameter indicating the slave address -* Mode (I2C_Mode10,I2C_Mode7). -* Direction (I2C_RX,I2C_TX). -* Return : None. -********************************************************************************/ -void I2C_AddressSend (I2C_TypeDef *I2Cx, u16 Address, I2C_Addressing Mode, I2C_Direction Direction); - -/******************************************************************************* -* Function Name : I2C_ByteSend -* Description : Send a single byte of data. -* Input : I2Cx ( I2C0 or I2C1 ) -* Data : the byte to be sent to the slave -* Return : None. -*******************************************************************************/ -void I2C_ByteSend (I2C_TypeDef *I2Cx, u8 Data); - -/******************************************************************************* -* Function Name : I2C_BufferSend -* Description : Send data from a buffer whose number of bytes is known -* Input : I2Cx ( I2C0 or I2C1 ) -* PtrToBuffer :pointer to the byte of buffer to be transmitted. -* NbOfBytes:Number of byte of the buffer -* Return : I2C_Tx_Status :transmission status (I2C_TX_AF, I2C_TX_ARLO, -* I2C_TX_BERR,I2C_TX_DATA_OK) -*******************************************************************************/ -I2C_Tx_Status I2C_BufferSend (I2C_TypeDef *I2Cx, u8 *PtrToBuffer, u8 NbOfBytes); - -/******************************************************************************* -* Function Name : I2C_StringSend -* Description : Send data from a buffer -* Input : I2Cx ( I2C0 or I2C1 ) -* PtrToString :pointer to the string to be transmitted. -* Return : I2C_Tx_Status :transmission status (I2C_TX_AF, I2C_TX_ARLO, -* I2C_TX_BERR,I2C_TX_DATA_OK) -*******************************************************************************/ -I2C_Tx_Status I2C_StringSend (I2C_TypeDef *I2Cx, char *PtrToString); - -/******************************************************************************* -* Function Name : I2C_TransmissionStatus -* Description : Report the NewState of the transmission -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : I2C_Tx_Status :transmission status (I2C_TX_NO, I2C_TX_SB, -* I2C_TX_AF, I2C_TX_ARLO, I2C_TX_BERR,I2C_TX_ADD_OK, -* I2C_TX_DATA_OK,I2C_TX_ONGOING) -*******************************************************************************/ -I2C_Tx_Status I2C_TransmissionStatus (I2C_TypeDef *I2Cx); - -/******************************************************************************* -* Function Name : I2C_ByteReceive -* Description : Returns the received byte. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : the byte received -*******************************************************************************/ -u8 I2C_ByteReceive (I2C_TypeDef *I2Cx); - -/******************************************************************************* -* Function Name : I2C_BufferReceive -* Description : received a buffer. and return the status of error. -* Input : I2Cx ( I2C0 or I2C1 ) -* PtrToBuffer :pointer to the byte of buffer received. -* NbOfBytes:Number of byte to be received -* Return : I2C_Rx_Status:the NewState of the reception (,I2C_RX_AF, -* I2C_RX_ARLO,I2C_RX_BERR, I2C_RX_DATA_OK) -*******************************************************************************/ -I2C_Rx_Status I2C_BufferReceive (I2C_TypeDef *I2Cx, u8 *PtrToBuffer, u8 NbOfBytes); - -/******************************************************************************* -* Function Name :I2C_ReceptionStatus -* Description : Report the reception NewState. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : I2C_Rx_Status:the NewState of the reception ( I2C_RX_NO, -* I2C_RX_SB,I2C_RX_AF,I2C_RX_ARLO,I2C_RX_BERR,I2C_RX_ADD_OK, -* I2C_RX_DATA_OK, I2C_RX_ONGOING) -*******************************************************************************/ -I2C_Rx_Status I2C_ReceptionStatus (I2C_TypeDef *I2Cx); - -/******************************************************************************* -* Function Name : I2C_ErrorClear -* Description : Clears any error flags. -* Input : I2Cx ( I2C0 or I2C1 ) -* Return : None. -*******************************************************************************/ -INLINE void I2C_ErrorClear (I2C_TypeDef *I2Cx) -{ - // Clear all error flags by reading the SR2 register - (void)I2Cx->SR2; -} - -/******************************************************************************* -* Function Name : I2C_GetStatus -* Description : Reads the I2C status registers. -* Input : None -* Return : I2C status registers. -*******************************************************************************/ -INLINE u32 I2C_GetStatus(I2C_TypeDef *I2Cx) -{ - return (((I2Cx->CR&0x04)<<14)|(I2Cx->SR1|(I2Cx->SR2<<8))&0x3FFF); -} - -#endif /* __i2c_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/pcu.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/pcu.h deleted file mode 100644 index 30d3fdda6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/pcu.h +++ /dev/null @@ -1,194 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : pcu.h -* Author : MCD Application Team -* Date First Issued : 30/05/2003 -* Description : This file contains all the functions prototypes for the -* PCU software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __PCU_H -#define __PCU_H - -#include "71x_map.h" - -typedef enum -{ - PCU_WREN = 0x8000, - PCU_VROK = 0x1000 -} PCU_Flags; - -typedef enum -{ - PCU_STABLE, - PCU_UNSTABLE -} PCU_VR_Status; - -typedef enum -{ - PCU_MVR = 0x0008, - PCU_LPR = 0x0020 -} PCU_VR; - -typedef enum -{ - WFI_CLOCK2_16, - WFI_EXTERNAL -} WFI_CLOCKS; - -typedef enum -{ - PCU_SLOW, - PCU_STOP, - PCU_STANDBY -} LPM_MODES; - - -// VR_OK : Voltage Regulator OK -#define PCU_VROK_Mask 0x1000 - -// Main Voltage Regulator -#define PCU_MVR_Mask 0x0008 - -// Low Power Voltage Regulator -#define PCU_LPR_Mask 0x0020 - -// PCU register Write Enable Bit -#define PCU_WREN_Mask 0x8000 - -// Low Voltage Detector -#define PCU_LVD_Mask 0x0100 - -// Power Down Flag -#define PCU_PWRDWN_Mask 0x0040 - -// WFI Mode Clock Selection Bit -#define PCU_WFI_CKSEL_Mask 0x00000002 - -// Halt Mode Enable Bit -#define PCU_EN_HALT_Mask 0x00000800 - -// Halt Mode Flag -#define PCU_HALT_Mask 0x0002 - -// Stop Mode Enable Bit -#define PCU_STOP_EN_Mask 0x00000400 - -// Low Power Regulator in Wait For interrupt Mode -#define PCU_LPRWFI_Mask 0x0020 - -// Low Power Mode in Wait For interrupt Mode -#define PCU_LPOWFI_Mask 0x00000001 - -// Software Reset Enable -#define PCU_SRESEN_Mask 0x00000001 - - -/******************************************************************************* -* Function Name : PCU_MVRStatus -* Description : This routine is used to check the Main Voltage Regulator -* : NewState. -* Input : None -* Return : STABLE, UNSTABLE -*******************************************************************************/ -INLINE PCU_VR_Status PCU_MVRStatus ( void ) -{ - return (PCU->PWRCR & PCU_VROK_Mask) == 0x00 ? PCU_UNSTABLE : PCU_STABLE; -} - -/******************************************************************************* -* Function Name : PCU_FlagStatus -* Description : This routine is used to return the PCU register flag -* Input 1 : The flag to get -* Return : RESET, SET -*******************************************************************************/ -INLINE FlagStatus PCU_FlagStatus ( PCU_Flags Xflag ) -{ - return ( PCU->PWRCR & Xflag ) == 0x00 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : PCU_VRConfig -* Description : This routine is used to configure PCU voltage regultors -* Input 1 : MVR : Main voltage Regulator - LPR : Low Power Regulator -* Input 2 : ENABLE : Enable the Voltage Regulator - DISABLE: Disable ( ByPass ) the VR -* Return : None -*******************************************************************************/ -void PCU_VRConfig ( PCU_VR xVR, FunctionalState NewState ); - -/******************************************************************************* -* Function Name : PCU_VRStatus -* Description : This routine is used to get the PCU voltage regultors status -* Input : MVR : Main voltage Regulator - LPR : Low Power Regulator -* Return : ENABLE : Enable the Voltage Regulator - DISABLE: Disable ( ByPass ) the VR -*******************************************************************************/ -INLINE FunctionalState PCU_VRStatus ( PCU_VR xVR ) -{ - return ( PCU->PWRCR & xVR ) == 0 ? ENABLE : DISABLE; -} - -/******************************************************************************* -* Function Name : PCU_LVDDisable -* Description : This routine is used to disable the Low Voltage Detector. -* Input : None -* Return : None -*******************************************************************************/ -INLINE void PCU_LVDDisable ( void ) -{ - PCU->PWRCR |= PCU_WREN_Mask; // Unlock Power Control Register - PCU->PWRCR |= PCU_LVD_Mask; // Set the LVD DIS Flag -} - -/******************************************************************************* -* Function Name : PCU_LVDStatus -* Description : This routine is used to get the LVD NewState. -* Input : None -* Return : ENABLE, DISABLE -*******************************************************************************/ -INLINE FunctionalState PCU_LVDStatus ( void ) -{ - return ( PCU->PWRCR & PCU_LVD_Mask ) == 0 ? ENABLE : DISABLE; -} - -/******************************************************************************* -* Function Name : PCU_WFIEnter -* Description : This routine is used to force the Device to enter in WFI mode -* Input 1 : CLOCK2_16 : Clock2_16 as system clock for WFI mode -* EXTERNAL : external clock as system clock for WFI mode -* Input 2 : ENABLE : Enable Low Power Regulator during Wait For Interrupt Mode -* DISABLE: Disable Low Power Regulator during Wait For Interrupt Mode -* Input 3 : ENABLE : Enable Low Power Mode during Wait For Interrupt Mode -* DISABLE: Disable Low Power Mode during Wait For Interrupt Mode -* Return : None -*******************************************************************************/ -void PCU_WFIEnter ( WFI_CLOCKS Xclock, FunctionalState Xlpr, FunctionalState Xlpm ); - -/******************************************************************************* -* Function Name : PCU_LPMEnter -* Description : This routine is used to force the Device to enter low -* power mode -* Input : SLOW : Slow Mode - STOP : Stop Mode - HALT : Halt Mode -* Return : None -*******************************************************************************/ -void PCU_LPMEnter ( LPM_MODES Xmode); - -#endif // __PCU_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/rccu.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/rccu.h deleted file mode 100644 index 775efc6d0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/rccu.h +++ /dev/null @@ -1,319 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : rccu.h -* Author : MCD Application Team -* Date First Issued : 28/07/2003 -* Description : This file contains all the functions prototypes for the -* RCCU software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __RCCU_H -#define __RCCU_H - -#include "71x_map.h" - -typedef enum { - RCCU_DEFAULT=0x00, - RCCU_RCLK_2 =0x01, - RCCU_RCLK_4 =0x02, - RCCU_RCLK_8 =0x03 - } RCCU_Clock_Div; - -typedef enum { - RCCU_PLL1_Output, - RCCU_CLOCK2_16, - RCCU_CLOCK2, - RCCU_RTC_CLOCK - } RCCU_RCLK_Clocks; - - - typedef enum { - RCCU_PLL1_Mul_12=0x01, - RCCU_PLL1_Mul_16=0x03, - RCCU_PLL1_Mul_20=0x00, - RCCU_PLL1_Mul_24=0x02 - } RCCU_PLL1_Mul; - -typedef enum { - RCCU_PLL2_Mul_12=0x01, - RCCU_PLL2_Mul_16=0x03, - RCCU_PLL2_Mul_20=0x00, - RCCU_PLL2_Mul_28=0x02 - } RCCU_PLL2_Mul; - -typedef enum { - RCCU_Div_1=0x00, - RCCU_Div_2=0x01, - RCCU_Div_3=0x02, - RCCU_Div_4=0x03, - RCCU_Div_5=0x04, - RCCU_Div_6=0x05, - RCCU_Div_7=0x06 - } RCCU_PLL_Div; - -typedef enum { - RCCU_PLL2_Output = 0x01, - RCCU_USBCK = 0x00 - } RCCU_USB_Clocks; - -typedef enum { - RCCU_CLK2, - RCCU_RCLK, - RCCU_MCLK, - RCCU_PCLK, - RCCU_FCLK - } RCCU_Clocks; - -typedef enum { - RCCU_PLL1_LOCK_IT = 0x0080, - RCCU_CKAF_IT = 0x0100, - RCCU_CK2_16_IT = 0x0200, - RCCU_STOP_IT = 0x0400 - } RCCU_Interrupts; - -typedef enum { - RCCU_PLL1_LOCK = 0x0002, - RCCU_CKAF_ST = 0x0004, - RCCU_PLL1_LOCK_I = 0x0800, - RCCU_CKAF_I = 0x1000, - RCCU_CK2_16_I = 0x2000, - RCCU_STOP_I = 0x4000 - } RCCU_Flags; - -typedef enum { - RCCU_ExternalReset = 0x00000000, - RCCU_SoftwareReset = 0x00000020, - RCCU_WDGReset = 0x00000040, - RCCU_RTCAlarmReset = 0x00000080, - RCCU_LVDReset = 0x00000200, - RCCU_WKPReset = 0x00000400 - }RCCU_ResetSources; - - -#define RCCU_Div2_Mask 0x00008000 -#define RCCU_Div2_Index 0x0F -#define RCCU_FACT_Mask 0x0003 - -#define RCCU_FACT1_Mask 0x0003 - -#define RCCU_FACT2_Mask 0x0300 -#define RCCU_FACT2_Index 0x08 - -#define RCCU_MX_Mask 0x00000030 -#define RCCU_MX_Index 0x04 - -#define RCCU_DX_Mask 0x00000007 - -#define RCCU_FREEN_Mask 0x00000080 - -#define RCCU_CSU_CKSEL_Mask 0x00000001 - -#define RCCU_CK2_16_Mask 0x00000008 - -#define RCCU_CKAF_SEL_Mask 0x00000004 - -#define RCCU_LOCK_Mask 0x00000002 - -#define RCCU_USBEN_Mask 0x0100 -#define RCCU_USBEN_Index 0x08 -#define RCCU_ResetSources_Mask 0x000006E0 - -// RTC Oscillator Frequency value = 32 768 Hz -#define RCCU_RTC_Osc 32768 - -/******************************************************************************* -* Function Name : RCCU_Div2Config -* Description : Enables/Disables the clock division by two -* Input : NewState : ENABLE or DISABLE -* Return : None -*******************************************************************************/ -INLINE void RCCU_Div2Config ( FunctionalState NewState ) -{ - if (NewState == ENABLE) RCCU->CFR |= RCCU_Div2_Mask; - else RCCU->CFR &= ~RCCU_Div2_Mask; -} - -/******************************************************************************* -* Function Name : RCCU_Div2Status -* Description : Gets the Div2 Flag status -* Input : None -* Input : FlagStatus -* Return : None -*******************************************************************************/ -INLINE FlagStatus RCCU_Div2Status ( void ) -{ - return (RCCU->CFR & RCCU_Div2_Mask) == 0 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : RCCU_MCLKConfig -* Description : Selects the division factor for RCLK to obtain the -* MCLK clock for the CPU -* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, RCCU_RCLK_4, RCCU_RCLK_8 -* Return : None -*******************************************************************************/ -INLINE void RCCU_MCLKConfig ( RCCU_Clock_Div New_Clock ) -{ - PCU->MDIVR = ( PCU->MDIVR & ~RCCU_FACT_Mask ) | New_Clock; -} - -/******************************************************************************* -* Function Name : RCCU_FCLKConfig -* Description : Selects the division factor for RCLK to obtain the -* FCLK clock for the APB1 fast peripherals (PCLK1). -* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, -* RCCU_RCLK_4, RCCU_RCLK_8 -* Return : None -*******************************************************************************/ -INLINE void RCCU_FCLKConfig ( RCCU_Clock_Div New_Clock ) -{ - PCU->PDIVR = ( PCU->PDIVR & ~RCCU_FACT1_Mask ) | New_Clock; -} - -/******************************************************************************* -* Function Name : RCCU_PCLKConfig -* Description : Selects the division factor for RCLK to obtain the -* PCLK clock for the APB2 peripherals (PCLK2). -* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, -* RCCU_RCLK_4, RCCU_RCLK_8 -* Return : None -*******************************************************************************/ -INLINE void RCCU_PCLKConfig ( RCCU_Clock_Div New_Clock ) -{ - PCU->PDIVR =(PCU->PDIVR & ~RCCU_FACT2_Mask)|(New_Clock << RCCU_FACT2_Index); -} - -/******************************************************************************* -* Function Name : RCCU_PLL1Config -* Description : Configures the PLL1 div & mul factors. -* Input : New_Mul : RCCU_Mul_12, RCCU_Mul_16, RCCU_Mul_20, RCCU_Mul_28 -* : New_Div : RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, -* RCCU_Div_4, RCCU_Div_5, RCCU_Div_6, RCCU_Div_7 -* Return : None -*******************************************************************************/ -void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div ); - -/******************************************************************************* -* Function Name : RCCU_PLL2Config -* Description : Configures the PLL2 div & mul factors. -* Input : New_Mul : RCCU_Mul_12, RCCU_Mul_16, RCCU_Mul_20, RCCU_Mul_28 -* : New_Div : RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, -* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7 -* Return : None -*******************************************************************************/ -void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div ); - -/******************************************************************************* -* Function Name : RCCU_RCLKSourceConfig -* Description : Selects the RCLK source clock -* Input : New_Clock : RCCU_PLL1_OutPut, RCCU_CLOCK2_16, RCCU_CLOCK2 -* Return : None -*******************************************************************************/ -void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock ); - -/******************************************************************************* -* Function Name : RCCU_RCLKClockSource -* Description : Returns the current RCLK source clock -* Input : None -* Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 -*******************************************************************************/ -RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void ); - -/******************************************************************************* -* Function Name : RCCU_USBCLKConfig -* Description : Selects the USB source clock -* Input : New_Clock : RCCU_PLL2_Output, RCCU_USBCK -* Return : None -*******************************************************************************/ -INLINE void RCCU_USBCLKConfig ( RCCU_USB_Clocks New_Clock ) -{ - PCU->PLL2CR = (PCU->PLL2CR & ~RCCU_USBEN_Mask)|(New_Clock << RCCU_USBEN_Index); -} - -/******************************************************************************* -* Function Name : RCCU_USBClockSource -* Description : Gets the USB source clock -* Input : None -* Return : RCCU_USB_Clocks -*******************************************************************************/ -RCCU_USB_Clocks RCCU_USBClockSource ( void ); - -/******************************************************************************* -* Function Name : RCCU_FrequencyValue -* Description : Calculates & Returns any internal RCCU clock freuqency -* passed in parametres -* Input : RCCU_Clocks : RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, -* RCCU_PCLK, RCCU_FCLK -* Return : u32 -*******************************************************************************/ -u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk ); - -/******************************************************************************* -* Function Name : RCCU_ITConfig -* Description : Configures the RCCU interrupts -* Input : RCCU interrupts : RCCU_CK2_16_IT, RCCU_CKAF_IT, -* RCCU_PLL1_LOCK_IT -* Return : None -*******************************************************************************/ -INLINE void RCCU_ITConfig ( RCCU_Interrupts RCCU_IT, FunctionalState NewState) -{ - if (NewState == ENABLE) RCCU->CCR |= RCCU_IT; else RCCU->CCR &= ~RCCU_IT; -} - -/******************************************************************************* -* Function Name : RCCU_FlagStatus -* Description : Checks the RCCU clock flag register status -* Input : RCCU Flags : RCCU_CK2_16, RCCU_CKAF, RCCU_PLL1_LOCK -* Return : FlagStatus : SET or RESET -*******************************************************************************/ -INLINE FlagStatus RCCU_FlagStatus ( RCCU_Flags RCCU_flag ) -{ - return (RCCU->CFR & RCCU_flag) == 0 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : RCCU_FlagClear -* Description : Clears a specified flag in the RCCU registers -* Input : RCCU Flags : RCCU_CK2_16, RCCU_CKAF, RCCU_PLL1_LOCK -* Return : None -*******************************************************************************/ -INLINE void RCCU_FlagClear ( RCCU_Interrupts RCCU_IT ) -{ - RCCU->CFR |= RCCU_IT; -} - -/******************************************************************************* -* Function Name : RCCU_ResetSources -* Description : Return the source of the system reset -* Input : None -* Return : The reset source -*******************************************************************************/ -INLINE RCCU_ResetSources RCCU_ResetSource () -{ - - switch(RCCU->CFR & RCCU_ResetSources_Mask) - { - case 0x00000020: return RCCU_SoftwareReset; - case 0x00000040: return RCCU_WDGReset; - case 0x00000080: return RCCU_RTCAlarmReset; - case 0x00000200: return RCCU_LVDReset; - case 0x00000400: return RCCU_WKPReset; - default : return RCCU_ExternalReset; - } -} - -#endif // __RCCU_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/rtc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/rtc.h deleted file mode 100644 index 6d449196e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/rtc.h +++ /dev/null @@ -1,190 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : rtc.h -* Author : MCD Application Team -* Date First Issued : 20/05/2003 -* Description : This file contains all the functions prototypes for the -* RTC software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __RTC_H -#define __RTC_H - -#include "71x_map.h" - -typedef enum -{ - RTC_GIR = 0x08, - RTC_OWIR = 0x04, - RTC_AIR = 0x02, - RTC_SIR = 0x01 -} RTC_FLAGS; - -typedef enum -{ - RTC_GIT = 0x08, - RTC_OWIT = 0x04, - RTC_AIT = 0x02, - RTC_SIT = 0x01, - RTC_NONE = 0x00 -} RTC_IT; - -/******************************************************************************* -* Function Name : RTC_Delay -* Description : This routine is used to insert a delay -* Input : None -* Return : None -*******************************************************************************/ -void RTC_Delay( void ); - -/******************************************************************************* -* Function Name : RTC_CounterClear -* Description : This routine is used to clear the RTC counter -* Input : None -* Return : None -*******************************************************************************/ -void RTC_CounterClear (void); -/******************************************************************************* -* Function Name : RTC_CounterValue -* Description : This routine is used to get the RTC counter value -* Input : None -* Return : The current counter value. -*******************************************************************************/ -INLINE u32 RTC_CounterValue (void) -{ - return ( (u32)RTC->CNTH << 16 ) | RTC->CNTL; -} -/******************************************************************************* -* Function Name : RTC_CounterConfig -* Description : This routine is used to update the RTC counter value -* Input : The new counter value. -* Return : None -*******************************************************************************/ -void RTC_CounterConfig (u32 CounterValue); - -/******************************************************************************* -* Function Name : RTC_PrescalerValue -* Description : This routine is used to get the RTC prescaler Value -* Input : None -* Return : an u32 value that holds the prescaler Value. -*******************************************************************************/ -INLINE u32 RTC_PrescalerValue (void) -{ - return ( (u32)(RTC->PRLH & 0x000F) << 16 ) | RTC->PRLL; -} - -/******************************************************************************* -* Function Name : RTC_PrescalerConfig -* Description : This routine is used to set the Prescaler Value -* Input : The New prescaler Value -* Return : None -*******************************************************************************/ -void RTC_PrescalerConfig (u32 Xprescaler); - -/******************************************************************************* -* Function Name : RTC_AlarmValue -* Description : This routine is used to get the RTC alarm Value -* Input : None -* Return : an u32 value that holds the Real Time clock alarm time . -*******************************************************************************/ -INLINE u32 RTC_AlarmValue (void) -{ - return ( (u32)RTC->ALRH << 16 ) | RTC->ALRL; -} - -/******************************************************************************* -* Function Name : RTC_AlarmConfig -* Description : This routine is used to set the RTC alarm Value -* Input : an u32 value that holds the Real Time clock alarm time . -* Return : None -*******************************************************************************/ -void RTC_AlarmConfig (u32 Xalarm); - -/******************************************************************************* -* Function Name : RTC_FlagStatus -* Description : This routine is used to chek the RTC flag status -* Input : an RTC flag -* Return : Set or RESET -*******************************************************************************/ -INLINE FlagStatus RTC_FlagStatus (RTC_FLAGS Xflag) -{ - return ( RTC->CRL & Xflag ) == 0 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : RTC_FlagClear -* Description : This routine is used to clear the RTC flags -* Input : an RTC flag -* Return : None -*******************************************************************************/ -void RTC_FlagClear (RTC_FLAGS Xflag); - -/******************************************************************************* -* Function Name : RTC_ITConfig -* Description : This routine is used to configure the RTC interrupts -* Input 1 : an RTC interrupt -* Input 2 : Enable or Disable -* Return : None -*******************************************************************************/ -INLINE void RTC_ITConfig (RTC_IT Xrtcit, FunctionalState NewState) -{ - if (NewState == ENABLE) RTC->CRH |= Xrtcit; else RTC->CRH &= ~Xrtcit; -} - -/******************************************************************************* -* Function Name : RTC_ITStatus -* Description : This routine is used to get the RTC interrupts status -* Input : an RTC interrupt -* Return : Enable or Disable -*******************************************************************************/ -INLINE FunctionalState RTC_ITStatus (RTC_IT Xrtcit) -{ - return ( RTC->CRH & Xrtcit ) == 0 ? DISABLE : ENABLE; -} - -/******************************************************************************* -* Function Name : RTC_ITClear -* Description : This routine is used to clear the RTC interrupts -* Input : an RTC interrupt -* Return : None -*******************************************************************************/ -void RTC_ITClear (RTC_IT Xrtcit); - -/******************************************************************************* -* Function Name : RTC_EnterCfgMode -* Description : This routine is used to enter in the Configuration Mode -* Input : None -* Return : None -*******************************************************************************/ -void RTC_EnterCfgMode(void); - -/******************************************************************************* -* Function Name : RTC_ExitCfgMode -* Description : This routine is used to exit from the Configuration Mode -* Input : None -* Return : None -*******************************************************************************/ -void RTC_ExitCfgMode(void); - -/******************************************************************************* -* Function Name : RTC_WaitForLastTask -* Description : This routine is waits for the last task completetion -* Input : None -* Return : None -*******************************************************************************/ -void RTC_WaitForLastTask(void); - -#endif // __RTC_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/tim.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/tim.h deleted file mode 100644 index 15c009468..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/tim.h +++ /dev/null @@ -1,346 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : tim.h -* Author : MCD Application Team -* Date First Issued : 08/09/2003 -* Description : This file contains all the functions prototypes for the -* TIM software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef __TIM_H -#define __TIM_H - -#include "71x_map.h" - -typedef enum { TIM_EXTERNAL, - TIM_INTERNAL - } TIM_Clocks; - -typedef enum { TIM_RISING, - TIM_FALLING - } TIM_Clock_Edges; - -typedef enum { TIM_CHANNEL_A, - TIM_CHANNEL_B - } TIM_Channels; - -typedef enum { TIM_WITH_IT, - TIM_WITHOUT_IT - } TIM_IT_Mode; - -typedef enum { TIM_TIMING, - TIM_WAVE - } TIM_OC_Modes; - -typedef enum { TIM_HIGH, - TIM_LOW - } TIM_Logic_Levels; - -typedef enum { TIM_START, - TIM_STOP, - TIM_CLEAR - } TIM_CounterOperations; - -typedef enum { TIM_ICFA = 0x8000, - TIM_OCFA = 0x4000, - TIM_TOF = 0x2000, - TIM_ICFB = 0x1000, - TIM_OCFB = 0x0800 - } TIM_Flags; - -typedef struct { u16 Pulse; - u16 Period; - } PWMI_parameters; - -#define TIM_ECKEN_Mask 0x0001 -#define TIM_EXEDG_Mask 0x0002 - -#define TIM_IEDGA_Mask 0x0004 -#define TIM_IEDGB_Mask 0x0008 - -#define TIM_PWM_Mask 0x0010 - -#define TIM_OMP_Mask 0x0020 - -#define TIM_OCAE_Mask 0x0040 -#define TIM_OCBE_Mask 0x0080 - -#define TIM_OLVLA_Mask 0x0100 -#define TIM_OLVLB_Mask 0x0200 - -#define TIM_FOLVA_Mask 0x0400 -#define TIM_FOLVB_Mask 0x0800 - -#define TIM_PWMI_Mask 0x4000 - -#define TIM_EN_Mask 0x8000 - -#define TIM_OCBIE_mask 0x0800 -#define TIM_ICBIE_Mask 0x1000 -#define TIM_TOE_Mask 0x2000 -#define TIM_ICAIE_Mask 0x8000 -#define TIM_OCAIE_mask 0x4000 - -#define TIM_ICA_IT 0x8000 // Input Capture Channel A -#define TIM_OCA_IT 0x4000 // Output Compare Channel A -#define TIM_TO_IT 0x2000 // Timer OverFlow -#define TIM_ICB_IT 0x1000 // Input Capture Channel B -#define TIM_OCB_IT 0x0800 // Input Capture Channel A - - -/******************************************************************************* -* Function Name : TIM_Init -* Description : This routine is used to Initialize the TIM peripheral -* Input : TIM Timer to Initialize -* Return : None -*******************************************************************************/ -void TIM_Init( TIM_TypeDef *TIMx ); - -/******************************************************************************* -* Function Name : TIM_ClockSourceConfig -* Description : This routine is used to configure the TIM clock source -* Input : (1) TIM Timer -* : (2) TIM_Clocks : Specifies the TIM source clock -* - TIM_INTERNAL : The TIM is clocked by the APB2 frequency -* divided by the prescaler value. -* - TIM_EXTERNAL : The TIM is clocked by an external Clock -* Return : None -*******************************************************************************/ -INLINE void TIM_ClockSourceConfig ( TIM_TypeDef *TIMx, TIM_Clocks Xclock ) -{ - if (Xclock==TIM_EXTERNAL) TIMx->CR1|=TIM_ECKEN_Mask; else TIMx->CR1&=~TIM_ECKEN_Mask; -} - -/******************************************************************************* -* Function Name : TIM_ClockSourceValue -* Description : This routine is used to get the TIM clock source -* Input : TIM Timer -* Return : TIM_Clocks : Specifies the TIM source clock -* - TIM_INTERNAL : The TIM is clocked by the APB2 frequency -* divided by the prescaler value. -* - TIM_EXTERNAL : The TIM is clocked by an external Clock -*******************************************************************************/ -INLINE TIM_Clocks TIM_ClockSourceValue ( TIM_TypeDef *TIMx ) -{ - return ( TIMx->CR1 & TIM_ECKEN_Mask) == 0 ? TIM_INTERNAL : TIM_EXTERNAL; -} - -/******************************************************************************* -* Function Name : TIM_PrescalerConfig -* Description : This routine is used to configure the TIM prescaler value -* ( using an internal clock ) -* Input : (1) TIM Timer -* : (2) Prescaler ( u8 ) -* Return : None -*******************************************************************************/ -INLINE void TIM_PrescalerConfig ( TIM_TypeDef *TIMx, u8 Xprescaler ) -{ - TIMx->CR2 = ( TIMx->CR2 & 0xFF00 ) | Xprescaler; -} - -/******************************************************************************* -* Function Name : TIM_PrescalerValue -* Description : This routine is used to get the TIM prescaler value -* ( when using using an internal clock ) -* Input : TIM Timer -* Return : Prescaler ( u8 ) -*******************************************************************************/ -INLINE u8 TIM_PrescalerValue ( TIM_TypeDef *TIMx ) -{ - return TIMx->CR2 & 0x00FF; -} - -/******************************************************************************* -* Function Name : TIM_ClockLevelConfig -* Description : This routine is used to configure the TIM clock level -* ( using an external clock ) -* Input : TIM Timer -* : TIM_Clock_Edges : Specifies the active adge of the external clock -* - TIM_RISING : The rising edge -* - TIM_FALLING : The falling edge -* Return : None -*******************************************************************************/ -INLINE void TIM_ClockLevelConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge ) -{ - if (Xedge == TIM_RISING) TIMx->CR1 |= TIM_EXEDG_Mask; else TIMx->CR1 &= ~TIM_EXEDG_Mask; -} - -/******************************************************************************* -* Function Name : TIM_ClockLevelValue -* Description : This routine is used to get the TIM clock level -* Input : TIM Timer -* Output : TIM_Clock_Edges : Specifies the active adge of the external clock -* - TIM_RISING : The rising edge -* - TIM_FALLING : The falling edge -*******************************************************************************/ -INLINE TIM_Clock_Edges TIM_ClockLevelValue ( TIM_TypeDef *TIMx ) -{ - return ( TIMx->CR1 & TIM_EXEDG_Mask ) == 0 ? TIM_FALLING : TIM_RISING; -} - -/******************************************************************************* -* Function Name : TIM_ICAPModeConfig -* Description : This routine is used to configure the input capture feature -* Input : (1) TIM Timer -* : (2) Input Capture Channel ( Channel_A or Channel_B ) -* : (3) Active Edge : Rising edge or Falling edge. -* Output : None -*******************************************************************************/ -void TIM_ICAPModeConfig ( TIM_TypeDef *TIMx, - TIM_Channels Xchannel, - TIM_Clock_Edges Xedge ); - -/******************************************************************************* -* Function Name : TIM_ICAPValue -* Description : This routine is used to get the Input Capture value -* Input : (1) TIM Timer -* : (2) Input Capture Channel ( Channel_A or Channel_B ) -* Output : None -*******************************************************************************/ -INLINE u16 TIM_ICAPValue ( TIM_TypeDef *TIMx, TIM_Channels Xchannel ) -{ - return Xchannel == TIM_CHANNEL_A ? TIMx->ICAR : TIMx->ICBR; -} - -/******************************************************************************* -* Function Name : TIM_OCMPModeConfig -* Description : This routine is used to configure the output compare feature -* Input : (1) TIM Timer -* : (2) OCMP Channel ( Channel_A or Channel_B ) -* : (3) Pulse Length -* : (4) OC_Mode : output wave, or only timing. -* : (5) Level : Rising edge or Falling edge after the == -* Output : None -*******************************************************************************/ -void TIM_OCMPModeConfig ( TIM_TypeDef *TIMx, - TIM_Channels Xchannel, - u16 XpulseLength, - TIM_OC_Modes Xmode, - TIM_Logic_Levels Xlevel ); - -/******************************************************************************* -* Function Name : TIM_OPModeConfig -* Description : This routine is used to configure the one pulse mode -* Input : (1) TIM Timer -* : (3) XpulseLength : Length of the pulse -* : (4) Level1 : Level during the pulse -* : (5) Level2 : Level after the pulse -* : (6) Activation Edge : High or Low on ICAP A -* Output : None -*******************************************************************************/ -void TIM_OPModeConfig ( TIM_TypeDef *TIMx, - u16 XpulseLength, - TIM_Logic_Levels XLevel1, - TIM_Logic_Levels XLevel2, - TIM_Clock_Edges Xedge ); - -/******************************************************************************* -* Function Name : TIM_PWMOModeConfig -* Description : This routine is used to configure the PWM in output mode -* Input : (1) TIM Timer -* : (2) DutyCycle : u16 -* : (3) Level 1 : During the Duty Cycle -* : (4) Level 2 : During the after the pulse -* : (5) Full period : u16 -* Output : None -*******************************************************************************/ -void TIM_PWMOModeConfig ( TIM_TypeDef *TIMx, - u16 XDutyCycle, - TIM_Logic_Levels XLevel1, - u16 XFullperiod, - TIM_Logic_Levels XLevel2 - ); - -/******************************************************************************* -* Function Name : TIM_PWMInputConfig -* Description : This routine is used to configure the PWM in input mode -* Input : (1) TIM Timer -* : (2) First Activation Edge -* Output : None -*******************************************************************************/ -void TIM_PWMIModeConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge ); - -/******************************************************************************* -* Function Name : TIM_PWMIValue -* Description : This routine is used to get the PWMI values -* Input : (1) TIM Timer -* Output : PWMI_parameters : - u16 Dyty cycle - - u16 Full period -*******************************************************************************/ -PWMI_parameters TIM_PWMIValue (TIM_TypeDef *TIMx ); - -/******************************************************************************* -* Function Name : TIM_CounterConfig -* Description : This routine is used to start/stop and clear the selected -* timer counter -* Input : (1) TIM Timer -* : (2) TIM_CounterOperations - TIM_START Enables or resumes the counter -* TIM_STOP Stops the TIM counter -* TIM_CLEAR Set the TIM counter value to FFFCh -* Output : None -*******************************************************************************/ -void TIM_CounterConfig ( TIM_TypeDef *TIMx, TIM_CounterOperations Xoperation ); - -/******************************************************************************* -* Function Name : TIM_ITConfig -* Description : This routine is used to configure the TIM IT -* Input : (1) TIM Timer -* : (2) TIM interrupt -* : (2) ENABLE / DISABLE -* Output : None -*******************************************************************************/ -INLINE void TIM_ITConfig ( TIM_TypeDef *TIMx, u16 New_IT, FunctionalState NewState ) -{ - if (NewState == ENABLE) TIMx->CR2 |= New_IT; else TIMx->CR2 &= ~New_IT; -} - -/******************************************************************************* -* Function Name : TIM_FlagStatus -* Description : This routine is used to check whether a Flag is Set. -* Input : (1) TIM Timer -* : (2) The TIM FLag -* Output : Flag NewState -*******************************************************************************/ -INLINE FlagStatus TIM_FlagStatus ( TIM_TypeDef *TIMx, TIM_Flags Xflag ) -{ - return (TIMx->SR & Xflag) == 0 ? RESET : SET; -} - -/******************************************************************************* -* Function Name : TIM_FlagClear -* Description : This routine is used to clear Flags. -* Input : (1) TIM Timer -* : (2) The TIM FLag -* Output : None -*******************************************************************************/ -INLINE void TIM_FlagClear ( TIM_TypeDef *TIMx, TIM_Flags Xflag ) -{ - TIMx->SR &= ~Xflag; -} - -/******************************************************************************* -* Function Name : TIM_CounterValue -* Description : This routine returns the timer counter value. -* Input : TIM Timer -* Output : The counter value -*******************************************************************************/ -INLINE u16 TIM_CounterValue(TIM_TypeDef *TIMx) -{ - return TIMx->CNTR; -} -#endif // __TIM_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/uart.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/uart.h deleted file mode 100644 index 248c8da71..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/uart.h +++ /dev/null @@ -1,391 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : uart.h -* Author : MCD Application Team -* Date First Issued : 16/05/2003 -* Description : This file contains all the functions prototypes for the -* UART software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef _UART_H -#define _UART_H - -#include "71x_map.h" -#include "rccu.h" - -typedef enum -{ - UART_RxFIFO, - UART_TxFIFO -} UARTFIFO_TypeDef; - -typedef enum -{ - UART_EVEN_PARITY = 0x0000, - UART_ODD_PARITY = 0x0020, - UART_NO_PARITY -} UARTParity_TypeDef; - -typedef enum -{ - UART_0_5_StopBits = 0x00, - UART_1_StopBits = 0x08, - UART_1_5_StopBits = 0x10, - UART_2_StopBits = 0x18 -} UARTStopBits_TypeDef; - -typedef enum -{ - UARTM_8D = 0x01, - UARTM_7D_P = 0x03, - UARTM_9D = 0x04, - UARTM_8D_W = 0x05, - UARTM_8D_P = 0x07 -} UARTMode_TypeDef; - - -#define DUMMY 0 - -// UART flags definition -#define UART_TxFull 0x0200 -#define UART_RxHalfFull 0x0100 -#define UART_TimeOutIdle 0x0080 -#define UART_TimeOutNotEmpty 0x0040 -#define UART_OverrunError 0x0020 -#define UART_FrameError 0x0010 -#define UART_ParityError 0x0008 -#define UART_TxHalfEmpty 0x0004 -#define UART_TxEmpty 0x0002 -#define UART_RxBufFull 0x0001 - -// CR regiter bit definition -#define UART_FIFOEnableBit 10 -#define UART_RxEnableBit 8 -#define UART_RunBit 7 -#define UART_LoopBackBit 6 -#define UART_ParityOddBit 5 -#define UART_StopBits 3 - -// Stop bits definition -#define UART_05StopBits 0x00 -#define UART_1StopBit (0x01<<3) -#define UART_15StopBits (0x02<<3) -#define UART_2StopBits (0x03<<3) - -// Modes definition -#define UART_8BitsData 0x01 -#define UART_7BitsData 0x03 -#define UART_9BitsData 0x04 -#define UART_8BitsDataWakeUp 0x05 -#define UART_8BitsDataParity 0x07 - -/******************************************************************************* -* Function Name : UART_Init -* Description : This function initializes the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Output : None -* Return : None -*******************************************************************************/ -void UART_Init(UART_TypeDef *UARTx); - -/******************************************************************************* -* Function Name : UART_ModeConfig -* Description : This function configures the mode of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The UART mode -* Output : None -* Return : None -*******************************************************************************/ -INLINE void UART_ModeConfig(UART_TypeDef *UARTx, UARTMode_TypeDef UART_Mode) -{ - UARTx->CR = (UARTx->CR&0xFFF8)|(u16)UART_Mode; -} - -/******************************************************************************* -* Function Name : UART_BaudRateConfig -* Description : This function configures the baud rate of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The baudrate value -* Output : None -* Return : None -*******************************************************************************/ -void UART_BaudRateConfig(UART_TypeDef *UARTx, u32 BaudRate); - -/******************************************************************************* -* Function Name : UART_ParityConfig -* Description : This function configures the data parity of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The parity type -* Output : None -* Return : None -*******************************************************************************/ -INLINE void UART_ParityConfig(UART_TypeDef *UARTx, UARTParity_TypeDef Parity) -{ - UARTx->CR = (UARTx->CR&0xFFDF)|(u16)Parity; -} - -/******************************************************************************* -* Function Name : UART_StopBitsConfig -* Description : This function configures the number of stop bits of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The number of stop bits -* Output : None -* Return : None -*******************************************************************************/ -INLINE void UART_StopBitsConfig(UART_TypeDef *UARTx, UARTStopBits_TypeDef StopBits) -{ - UARTx->CR = (UARTx->CR&0xFFE7)|(u16)StopBits; -} - -/******************************************************************************* -* Function Name : UART_Config -* Description : This function configures the baudrate, the mode, the data -* parity and the number of stop bits of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The baudrate value -* Input 3 : The parity type -* Input 4 : The number of stop bits -* Input 5 : The UART mode -* Output : None -* Return : None -*******************************************************************************/ -void UART_Config(UART_TypeDef *UARTx, u32 BaudRate, UARTParity_TypeDef Parity, - UARTStopBits_TypeDef StopBits, UARTMode_TypeDef Mode); - -/******************************************************************************* -* Function Name : UART_ItConfig -* Description : This function enables or disables the interrupts of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The new interrupt flag -* Input 3 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_ItConfig(UART_TypeDef *UARTx, u16 UART_Flag, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_FifoConfig -* Description : This function enables or disables the Rx and Tx FIFOs of -* the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_FifoConfig(UART_TypeDef *UARTx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_FifoReset -* Description : This function resets the Rx and the Tx FIFOs of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : RxFIFO or TxFIFO -* Output : None -* Return : None -*******************************************************************************/ -void UART_FifoReset(UART_TypeDef *UARTx, UARTFIFO_TypeDef FIFO); - -/******************************************************************************* -* Function Name : UART_LoopBackConfig -* Description : This function enables or disables the loop back mode of -* the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_LoopBackConfig(UART_TypeDef *UARTx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_TimeOutPeriodConfig -* Description : This function configure the Time Out Period. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The time-out period value -* Output : None -* Return : None -*******************************************************************************/ -INLINE void UART_TimeOutPeriodConfig(UART_TypeDef *UARTx, u16 TimeOutPeriod) -{ - UARTx->TOR = TimeOutPeriod; -} - -/******************************************************************************* -* Function Name : UART_GuardTimeConfig -* Description : This function configure the Guard Time. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The guard time value -* Output : None -* Return : None -*******************************************************************************/ -INLINE void UART_GuardTimeConfig(UART_TypeDef *UARTx, u16 GuardTime) -{ - UARTx->GTR = GuardTime; -} - -/******************************************************************************* -* Function Name : UART_RxConfig -* Description : This function enable and disable the UART data reception. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_RxConfig(UART_TypeDef *UARTx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_OnOffConfig -* Description : This function sets On/Off the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_OnOffConfig(UART_TypeDef *UARTx, FunctionalState NewState); - -/******************************************************************************* -* Function Name : UART_ByteSend -* Description : This function sends a data byte to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data byte to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_ByteSend(UART_TypeDef *UARTx, u8 *Data); - -/******************************************************************************* -* Function Name : UART_9BitByteSend -* Description : This function sends a 9 bits data byte to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_9BitByteSend(UART_TypeDef *UARTx, u16 *Data); - -/******************************************************************************* -* Function Name : UART_DataSend -* Description : This function sends several data bytes to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Input 3 : The data length in bytes -* Output : None -* Return : None -*******************************************************************************/ -void UART_DataSend(UART_TypeDef *UARTx, u8 *Data, u8 DataLength); - -/******************************************************************************* -* Function Name : UART_9BitDataSend -* Description : This function sends several 9 bits data bytes to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Input 3 : The data length -* Output : None -* Return : None -*******************************************************************************/ -void UART_9BitDataSend(UART_TypeDef *UARTx, u16 *Data, u8 DataLength); - -/******************************************************************************* -* Function Name : UART_StringSend -* Description : This function sends a string to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the string to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_StringSend(UART_TypeDef *UARTx, u8 *String); - -/******************************************************************************* -* Function Name : UART_ByteReceive -* Description : This function gets a data byte from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The time-out period -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_ByteReceive(UART_TypeDef *UARTx, u8 *Data, u8 TimeOut); - -/******************************************************************************* -* Function Name : UART_9BitByteReceive -* Description : This function gets a 9 bits data byte from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The time-out period value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_9BitByteReceive(UART_TypeDef *UARTx, u16 *Data, u8 TimeOut); - -/******************************************************************************* -* Function Name : UART_DataReceive -* Description : This function gets 8 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The data length -* Input 4 : The time-out period value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_DataReceive(UART_TypeDef *UARTx, u8 *Data, u8 DataLength, u8 TimeOut); - -/******************************************************************************* -* Function Name : UART_9BitDataReceive -* Description : This function gets 9 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The data length -* Input 4 : The time-out value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_9BitDataReceive(UART_TypeDef *UARTx, u16 *Data, u8 DataLength, u8 TimeOut); - -/******************************************************************************* -* Function Name : UART_StringReceive -* Description : This function gets 8 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the string will be stored -* Output : None -* Return : None -*******************************************************************************/ -u16 UART_StringReceive(UART_TypeDef *UARTx, u8 *Data); - -/******************************************************************************* -* Function Name : UART_FlagStatus -* Description : This function gets the flags status of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Output : None -* Return : None -*******************************************************************************/ -INLINE u16 UART_FlagStatus(UART_TypeDef *UARTx) -{ - return UARTx->SR; -} - -#ifdef USE_SERIAL_PORT -/******************************************************************************* -* Function Name : sendchar -* Description : This function sends a character to the selected UART. -* Input 1 : A pointer to the character to send. -* Output : None -* Return : None -*******************************************************************************/ -void sendchar( char *ch ); -#endif /* USE_SERIAL_PORT */ - -#endif /* _UART_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/wdg.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/wdg.h deleted file mode 100644 index 58858824a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/wdg.h +++ /dev/null @@ -1,130 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : wdg.h -* Author : MCD Application Team -* Date First Issued : 25/08/2003 -* Description : This file contains all the functions prototypes for the -* WDG software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __WDG_H -#define __WDG_H - -#include "71x_map.h" -#include "rccu.h" - -/******************************************************************************* -* Function Name : WDG_Enable -* Description : Enable the Watchdog Mode -* Input : None -* Return : None -*******************************************************************************/ -INLINE void WDG_Enable ( void ) -{ - WDG->CR |= 0x01; -} - -/******************************************************************************* -* Function Name : WDG_CntRefresh -* Description : Refresh and update the WDG counter to avoid a system reset. -* Input : None -* Return : None -*******************************************************************************/ -INLINE void WDG_CntRefresh ( void ) -{ - //write the first value in the key register - WDG->KR = 0xA55A; - //write the consecutive value - WDG->KR = 0x5AA5; -} - -/******************************************************************************* -* Function Name : WDG_PrescalerConfig -* Description : Set the counter prescaler value. -* Divide the counter clock by (Prescaler + 1) -* Input : Prescaler data value (8 bit) -* Return : None -*******************************************************************************/ -INLINE void WDG_PrescalerConfig ( u8 Prescaler ) -{ - WDG->PR = Prescaler; -} - -/******************************************************************************* -* Function Name : WDG_CntReloadUpdate -* Description : Update the counter pre-load value. -* Input : Pre-load data value (16 bit) -* Return : None -*******************************************************************************/ -INLINE void WDG_CntReloadUpdate ( u16 PreLoadValue ) -{ - WDG->VR = PreLoadValue; -} - -/******************************************************************************* -* Function Name : WDG_PeriodValueConfig -* Description : Set the prescaler and counter reload value based on the -* time needed -* Input : Amount of time (us) needed, peripheral clock2 value -* Return : None -*******************************************************************************/ -void WDG_PeriodValueConfig ( u32 Time ); - -/******************************************************************************* -* Function Name : WDG_CntOnOffConfig -* Description : Start or stop the free auto-reload timer to countdown. -* Input : ENABLE or DISABLE -* Return : None -*******************************************************************************/ -INLINE void WDG_CntOnOffConfig ( FunctionalState NewState ) -{ - if (NewState == ENABLE) WDG->CR |= 0x0002; else WDG->CR &= ~0x0002; -} - -/******************************************************************************* -* Function Name : WDG_ECITConfig -* Description : Enable or Disable the end of count interrupt -* Input : ENABLE or DISABLE -* Return : None -*******************************************************************************/ -INLINE void WDG_ECITConfig (FunctionalState NewState) -{ - if (NewState == ENABLE) WDG->MR |= 0x0001; else WDG->MR &= ~0x0001; -} - -/******************************************************************************* -* Function Name : WDG_ECFlagClear -* Description : Clear the end of count flag -* Input : None -* Return : None -*******************************************************************************/ -INLINE void WDG_ECFlagClear ( void ) -{ - WDG->SR = 0x0000; -} - -/******************************************************************************* -* Function Name : WDG_ECStatus -* Description : Return the end of count status -* Input : None -* Return : NewState value -*******************************************************************************/ -INLINE u16 WDG_ECStatus ( void ) -{ - return WDG->SR; -} - -#endif // __WDG_H - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/xti.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/xti.h deleted file mode 100644 index a8a2476a9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/include/xti.h +++ /dev/null @@ -1,138 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : xti.h -* Author : MCD Application Team -* Date First Issued : 08/06/2003 -* Description : This file contains all the functions prototypes for the -* XTI software library. -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#ifndef __XTI_H -#define __XTI_H - -#include "71x_map.h" - -typedef enum -{ - XTI_WakeUp = 1, - XTI_Interrupt = 2, - XTI_WakeUpInterrupt = 3 -} XTIMode_TypeDef; - -typedef enum -{ - XTI_FallingEdge, - XTI_RisingEdge -} XTITriggerEdge_TypeDef; - -#define XTI_Line0 0x0001 -#define XTI_Line1 (XTI_Line0<<1) -#define XTI_Line2 (XTI_Line1<<1) -#define XTI_Line3 (XTI_Line2<<1) -#define XTI_Line4 (XTI_Line3<<1) -#define XTI_Line5 (XTI_Line4<<1) -#define XTI_Line6 (XTI_Line5<<1) -#define XTI_Line7 (XTI_Line6<<1) -#define XTI_Line8 (XTI_Line7<<1) -#define XTI_Line9 (XTI_Line8<<1) -#define XTI_Line10 (XTI_Line9<<1) -#define XTI_Line11 (XTI_Line10<<1) -#define XTI_Line12 (XTI_Line11<<1) -#define XTI_Line13 (XTI_Line12<<1) -#define XTI_Line14 (XTI_Line13<<1) -#define XTI_Line15 (XTI_Line14<<1) - -/******************************************************************************* -* Function Name : XTI_Init -* Description : Initialize the XIT peripheral to reset state. -* Input 1 : None -* Output : None -* Return : None -*******************************************************************************/ -void XTI_Init(void); - -/******************************************************************************* -* Function Name : XTI_ModeConfig -* Description : Configure the XTI Mede -* Input 1 : Mode can be WakeUp, Interrupt or WakeUpInterrupt. -* Input 2 : NewState can be ENABLE ro DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -INLINE void XTI_ModeConfig(XTIMode_TypeDef Mode,FunctionalState NewState) -{ - if (NewState==ENABLE) XTI->CTRL|=Mode; else XTI->CTRL&=~Mode; -} - -/******************************************************************************* -* Function Name : XTI_LineModeConfig -* Description : Configure the trigger edge. -* Input 1 : Lines to be configured. -* Input 2 : The trigger edge can be FallingEdge or RisingEdge. -* Output : None -* Return : None -*******************************************************************************/ -void XTI_LineModeConfig(u16 Lines, XTITriggerEdge_TypeDef TriggerEdge); - -/******************************************************************************* -* Function Name : XTI_LineConfig -* Description : Enable and disable lines interrupts -* Input 1 : Lines to be configured. -* Input 2 : NewState can be ENABLE ro DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void XTI_LineConfig(u16 Lines, FunctionalState NewState); - -/******************************************************************************* -* Function Name : XTI_InterruptLineValue -* Description : Get the interrupt lines -* Input 1 : None. -* Output : The interrupts lines numbers -* Return : None -*******************************************************************************/ -INLINE u16 XTI_InterruptLineValue(void) -{ - return XTI->PRL | ((u16)XTI->PRH<<8); -} - -/******************************************************************************* -* Function Name : XTI_PendingBitClear -* Description : Clear the pending bits -* Input 1 : Bits to be cleared. -* Output : None -* Return : None -*******************************************************************************/ -INLINE void XTI_PendingBitClear(u16 Lines) -{ - XTI->PRL &= ~Lines; - XTI->PRH &= ~((Lines>>8)&0x00FF); -} - -/******************************************************************************* -* Function Name : XTI_SoftwareIRQInterruprGenerate -* Description : Generate a software IRQ interrupt. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -INLINE void XTI_SWIRQGenerate(void) -{ - XTI->SR = 0x01; - XTI->SR = 0x00; -} - -#endif /* __XTI_H */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/pcu.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/pcu.c deleted file mode 100644 index 9b943a893..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/pcu.c +++ /dev/null @@ -1,139 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : pcu.c -* Author : MCD Application Team -* Date First Issued : 09/09/03 -* Description : This file provides all the Power Control Unit functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "pcu.h" -#include "rccu.h" - -/******************************************************************************* -* Function Name : PCU_VRConfig -* Description : This routine is used to configure PCU voltage regultors -* Input 1 : MVR : Main voltage Regulator - LPR : Low Power Regulator -* Input 2 : ENABLE : Enable the Voltage Regulator - DISABLE: Disable ( ByPass ) the VR -* Return : None -*******************************************************************************/ -void PCU_VRConfig ( PCU_VR Xvr, FunctionalState NewState ) -{ - u16 Tmp = PCU->PWRCR; - switch ( Xvr ) - { - case PCU_MVR : - // Configure the Main Voltage Regulator - if (NewState == DISABLE) Tmp |= PCU_MVR_Mask; else Tmp &= ~PCU_MVR_Mask; - break; - case PCU_LPR : - // Configure the Low power Voltage Regulator - if (NewState == DISABLE) Tmp |= PCU_LPR_Mask; else Tmp &= ~PCU_LPR_Mask; - break; - } - // Unlock Power Control Register - PCU->PWRCR |= PCU_WREN_Mask; - PCU->PWRCR = Tmp | PCU_WREN_Mask; -} - -/******************************************************************************* -* Function Name : PCU_WFIEnter -* Description : This routine is used to force the Device to enter in WFI mode -* Input 1 : CLOCK2_16 : Clock2_16 as system clock for WFI mode -* EXTERNAL : external clock as system clock for WFI mode -* Input 2 : ENABLE : Enable Low Power Regulator during Wait For Interrupt Mode -* DISABLE: Disable Low Power Regulator during Wait For Interrupt Mode -* Input 3 : ENABLE : Enable Low Power Mode during Wait For Interrupt Mode -* DISABLE: Disable Low Power Mode during Wait For Interrupt Mode -* Return : None -*******************************************************************************/ -void PCU_WFIEnter ( WFI_CLOCKS Xclock, FunctionalState Xlpr, FunctionalState Xlpm ) -{ - u32 Tmp; - // Enable Low Power Regulator in WFI mode - Tmp = PCU->PWRCR; - // Unlock Power Control Register - PCU->PWRCR |= PCU_WREN_Mask; - PCU->PWRCR = Xlpr == ENABLE ? Tmp & ~PCU_LPRWFI_Mask : Tmp | PCU_LPRWFI_Mask; - // WFI Clock Selection - Tmp = RCCU->CCR; - RCCU->CCR = Xclock == WFI_CLOCK2_16 ? Tmp & ~PCU_WFI_CKSEL_Mask : Tmp | PCU_WFI_CKSEL_Mask; - // Low Power Mode during WFI mode - Tmp = RCCU->CCR; - RCCU->CCR = Xlpm == DISABLE ? Tmp & ~PCU_LPOWFI_Mask : Tmp | PCU_LPOWFI_Mask; - // Enter WFI Mode - RCCU->SMR &= ~0x0001; -} - -/******************************************************************************* -* Function Name : PCU_LPMEnter -* Description : This routine is used to force the device to enter in low -* power modes -* Input : PCU_SLOW : Slow Mode - PCU_STOP : Stop Mode - PCU_STANDBY : StandBy Mode -* Return : None -*******************************************************************************/ -void PCU_LPMEnter ( LPM_MODES Xmode ) -{ - u32 temp; - switch ( Xmode ) - { - // Slow Mode - case PCU_SLOW: - { - RCCU->PLL1CR |= 0x87; - RCCU_RCLKSourceConfig ( RCCU_PLL1_Output ); - break; - } - - // Stop Mode - case PCU_STOP: - { - // Enable Stop EN bit - RCCU->CCR |= PCU_STOP_EN_Mask; - - // Write '1' to Stop Bit - XTI->CTRL |= 0x04; - // Write '0' to Stop Bit - XTI->CTRL &= 0x03; - // Write '1' to Stop Bit - XTI->CTRL |= 0x04; - // add Delay - - temp = 0; - temp = 1; - temp = 2; - temp = 3; - temp = 4; - temp = 5; - temp = 6; - temp = 7; - temp = 8; - - break; - - } - // PCU_STANDBY Mode - case PCU_STANDBY: - { - PCU->PWRCR |= PCU_WREN_Mask; // Unlock Power Control Register - PCU->PWRCR |= PCU_PWRDWN_Mask; // Set the Power Down flag - } - } -} -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/rccu.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/rccu.c deleted file mode 100644 index 7de93580b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/rccu.c +++ /dev/null @@ -1,185 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : rccu.c -* Author : MCD Application Team -* Date First Issued : 07/28/2003 -* Description : This file provides all the RCCU software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ -#include "rccu.h" - -/******************************************************************************* -* Function Name : RCCU_PLL1Config -* Description : Configures the PLL1 div & mul factors. -* Input : New_Mul ( RCCU_PLL1_Mul_12, RCCU_PLL1_Mul_16, RCCU_PLL1_Mul_20, -* RCCU_PLL1_Mul_24 ) -* : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, -* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7) -* Return : None -*******************************************************************************/ -void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div ) -{ - u32 Tmp = ( RCCU->PLL1CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index ); - RCCU->PLL1CR = ( Tmp & ~RCCU_DX_Mask ) | New_Div | 0x40; -} - -/******************************************************************************* -* Function Name : RCCU_PLL2Config -* Description : Configures the PLL2 div & mul factors. -* Input : New_Mul ( RCCU_PLL2_Mul_12, RCCU_PLL2_Mul_16, RCCU_PLL2_Mul_20, -* RCCU_Mul_PLL2_28 ) -* : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4, -* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7) -* Return : None -*******************************************************************************/ -void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div ) -{ - u32 Tmp = ( PCU->PLL2CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index ); - PCU->PLL2CR = ( Tmp & ~RCCU_DX_Mask ) | ( New_Div | RCCU_FREEN_Mask ); -} - -/******************************************************************************* -* Function Name : RCCU_RCLKSourceConfig -* Description : Selects the RCLK source clock -* Input : New_Clock ( RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 ) -* Return : None -*******************************************************************************/ -void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock ) -{ - switch ( New_Clock ) - { - case RCCU_CLOCK2 :{// Resets the CSU_Cksel bit in clk_flag - RCCU->CFR &= ~RCCU_CSU_CKSEL_Mask; - // Set the CK2_16 Bit in the CFR - RCCU->CFR |= RCCU_CK2_16_Mask; - // Deselect The CKAF - RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; - // switch off the PLL1 - RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\ - |0x00000003) & ~RCCU_FREEN_Mask; - break;} - case RCCU_CLOCK2_16 :{// ReSet the CK2_16 Bit in the CFR - RCCU->CFR &= ~RCCU_CK2_16_Mask; - // Deselect The CKAF - RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; - // switch off the PLL1 - RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\ - |0x00000003) & ~RCCU_FREEN_Mask; - break;} - case RCCU_PLL1_Output:{// Set the CK2_16 Bit in the CFR - RCCU->CFR = RCCU->CFR | RCCU_CK2_16_Mask; - // Waits the PLL1 to lock if DX bits are different from '111' - // If all DX bit are set the PLL lock flag in meaningless - if (( RCCU->PLL1CR & 0x0007 ) != 7) - while(!(RCCU->CFR & RCCU_LOCK_Mask)); - // Deselect The CKAF - RCCU->CCR &= ~RCCU_CKAF_SEL_Mask; - // Select The CSU_CKSEL - RCCU->CFR |= RCCU_CSU_CKSEL_Mask; - break;} - case RCCU_RTC_CLOCK : {RCCU->CCR |= 0x04; - break;} - } -} - -/******************************************************************************* -* Function Name : RCCU_RCLKClockSource -* Description : Returns the current RCLK source clock -* Input : None -* Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2, RCCU_RTC_CLOCK -*******************************************************************************/ -RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void ) -{ - if ((RCCU->CCR & 0x04)==0x04) - return RCCU_RTC_CLOCK; - - else if ((RCCU->CFR & RCCU_CK2_16_Mask)==0) - return RCCU_CLOCK2_16; - - else if (RCCU->CFR & RCCU_CSU_CKSEL_Mask) - return RCCU_PLL1_Output; - - else - return RCCU_CLOCK2; -} - -/******************************************************************************* -* Function Name : RCCU_USBClockSource -* Description : Gets the RCLK source clock -* Input : None -* Return : RCCU_USB_Clocks ( RCCU_PLL2_Output, RCCU_USBCK ) -*******************************************************************************/ -RCCU_USB_Clocks RCCU_USBClockSource ( void ) -{ - if ((PCU->PLL2CR & RCCU_USBEN_Mask ) >> RCCU_USBEN_Index == 1 ) - return RCCU_PLL2_Output; - else return RCCU_USBCK; -} - -/******************************************************************************* -* Function Name : RCCU_FrequencyValue -* Description : Calculates & Returns any internal RCCU clock frequency -* passed in parametres -* Input : RCCU_Clocks ( RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, RCCU_PCLK, RCCU_FCLK ) -* Return : u32 -*******************************************************************************/ -u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk ) -{ - u32 Tmp; - u8 Div = 0; - u8 Mul = 0; - RCCU_RCLK_Clocks CurrentRCLK; - - Tmp = ( RCCU_Div2Status() == SET )? RCCU_Main_Osc / 2 : RCCU_Main_Osc; - - if ( Internal_Clk == RCCU_CLK2 ) - { - Div = 1; - Mul = 1; - } - else - { CurrentRCLK = RCCU_RCLKClockSource (); - switch ( CurrentRCLK ){ - case RCCU_CLOCK2_16 : Div = 16; - Mul = 1; - break; - case RCCU_CLOCK2 : Div = 1; - Mul = 1; - break; - case RCCU_PLL1_Output :{Mul=(RCCU->PLL1CR & RCCU_MX_Mask ) >> RCCU_MX_Index; - switch ( Mul ) - {case 0: Mul = 20; break; - case 1: Mul = 12; break; - case 2: Mul = 24; break; - case 3: Mul = 16; break; - } - Div = ( RCCU->PLL1CR & RCCU_DX_Mask ) + 1; - break;} - case RCCU_RTC_CLOCK : Mul = 1; - Div = 1; - Tmp = RCCU_RTC_Osc; - break;}} - - switch ( Internal_Clk ){ - case RCCU_MCLK :{Div <<= PCU->MDIVR & RCCU_FACT_Mask; - break;} - case RCCU_PCLK :{Div <<=(PCU->PDIVR & RCCU_FACT2_Mask ) >> RCCU_FACT2_Index; - break;} - case RCCU_FCLK :{Div <<= PCU->PDIVR & 0x3; - break;}} - - return (Tmp * Mul) / Div; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/rtc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/rtc.c deleted file mode 100644 index 8adab4f46..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/rtc.c +++ /dev/null @@ -1,232 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : rtc.c -* Author : MCD Application Team -* Date First Issued : 09/30/2003 -* Description : This file provides all the RTC software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "rtc.h" - -// Global interrupt -#define RTC_GI_Mask 0x0008 -#define RTC_GI_Index 3 - -// OverFlow interrupt -#define RTC_OWI_Mask 0x0004 -#define RTC_OWI_Index 2 - -// Alarm interrupt -#define RTC_AI_Mask 0x0002 -#define RTC_AI_Index 1 - -// Second interrupt -#define RTC_SI_Mask 0x0001 - -// Configuration Flag Mask -#define RTC_CNF_Mask 0x0010 - -// Operation OFF flag -#define RTC_RTOFF_Mask 0x0020 - -/******************************************************************************* -* Function Name : RTC_Delay -* Description : This routine is used to insert a delay -* Input : None -* Return : None -*******************************************************************************/ -void RTC_Delay( void ) -{ - u16 _Tmp; - for (_Tmp = 0x0; _Tmp < 0x7F; _Tmp ++); -} - -/******************************************************************************* -* Function Name : RTC_CounterConfig -* Description : This routine is used to update the RTC counter value -* Input : The new counter value. -* Return : None -*******************************************************************************/ -void RTC_CounterConfig (u32 CounterValue) -{ - /* Wait For Last Task Completition */ - RTC_WaitForLastTask(); - - /* Enter to configuration mode */ - RTC_EnterCfgMode(); - - /* Wait For Last Task Completition */ - RTC_WaitForLastTask(); - -/* Update the RTC counter register with the new time and date */ - /* Update the CNTL register */ - RTC->CNTL = (u16)CounterValue; - - /* Wait For Last Task Completition */ - RTC_WaitForLastTask(); - - /* Update the CNTH register */ - RTC->CNTH = (u16)(CounterValue >> 16); - - /* Wait For Last Task Completition */ - RTC_WaitForLastTask(); - - /* Exit From Configuration Mode */ - RTC_ExitCfgMode (); -} - -/******************************************************************************* -* Function Name : RTC_PrescalerConfig -* Description : This routine is used to set the Prescaler Value -* Input : The New prescaler Value -* Return : None -*******************************************************************************/ -void RTC_PrescalerConfig (u32 Xprescaler) -{ - if ( RTC_PrescalerValue () != Xprescaler ) - { - // Wait For Last Task Completion - RTC_WaitForLastTask (); - // Enter In Configuration Mode - RTC_EnterCfgMode (); - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Set the prescaler MSB part - RTC->PRLH = (Xprescaler & 0x000F0000) >> 16; - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Set the prescaler LSB part - RTC->PRLL = (Xprescaler & 0x0000FFFF); - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Exit From Configuration Mode - RTC_ExitCfgMode (); - // Wait For Last Task Completion - RTC_WaitForLastTask (); - } -} - -/******************************************************************************* -* Function Name : RTC_AlarmConfig -* Description : This routine is used to set the RTC alarm Value -* Input : an u32 value that holds the Real Time clock alarm time. -* Return : None -*******************************************************************************/ -void RTC_AlarmConfig (u32 Xalarm) -{ - // Wait For Last Task Completion - RTC_WaitForLastTask (); - // Enter In Configuration Mode - RTC_EnterCfgMode (); - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Set The MSB part of the Alarm Time - RTC->ALRH = (Xalarm & 0xFFFF0000) >> 16; - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Set The LSB part of the Alarm Time - RTC->ALRL = (Xalarm & 0x0000FFFF); - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Exit From Configuration Mode - RTC_ExitCfgMode (); - // Wait For Last Task Completion - RTC_WaitForLastTask (); -} - -/******************************************************************************* -* Function Name : RTC_FlagClear -* Description : This routine is used to clear the RTC flags -* Input : an RTC flag -* Return : None -*******************************************************************************/ -void RTC_FlagClear (RTC_FLAGS Xflag) -{ - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Enter In Configuration Mode - RTC_EnterCfgMode(); - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Clear an RTC flag - RTC->CRL &= ~Xflag; - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Exit From Configuration Mode - RTC_ExitCfgMode (); - // Wait For Last Task Completion - RTC_WaitForLastTask(); -} - -/******************************************************************************* -* Function Name : RTC_ITClear -* Description : This routine is used to clear the RTC interrupts -* Input : an RTC interrupt -* Return : None -*******************************************************************************/ -void RTC_ITClear (RTC_IT Xrtcit) -{ - // Wait For Last Task Completion - RTC_WaitForLastTask(); - // Enter In Configuration Mode - RTC_EnterCfgMode(); - // Clears an RTC interrupt - RTC->CRL &= ~Xrtcit; - // Exit From Configuration Mode - RTC_ExitCfgMode (); - // Wait For Last Task Completion - RTC_WaitForLastTask (); -} - -/******************************************************************************* -* Function Name : RTC_EnterCfgMode -* Description : This routine is used to enter in the Configuration Mode -* Input : None -* Return : None -*******************************************************************************/ -void RTC_EnterCfgMode(void) -{ - // Set the CNF flag to enter in the Configuration Mode - RTC->CRL |= RTC_CNF_Mask; - // Wait For Last Task Completion - RTC_WaitForLastTask (); -} - -/******************************************************************************* -* Function Name : RTC_ExitCfgMode -* Description : This routine is used to exit from the Configuration Mode -* Input : None -* Return : None -*******************************************************************************/ -void RTC_ExitCfgMode(void) -{ - // Reset the CNF flag to exit from the Configuration Mode - RTC->CRL &= ~RTC_CNF_Mask; - // Wait For Last Task Completion - RTC_WaitForLastTask (); -} - -/******************************************************************************* -* Function Name : RTC_WaitForLastTask -* Description : This routine waits for the last task completion -* Input : None -* Return : None -*******************************************************************************/ -void RTC_WaitForLastTask(void) -{ - // Loop until the Last operation Completion - while (!(RTC->CRL & RTC_RTOFF_Mask)); -} -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/tim.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/tim.c deleted file mode 100644 index f6d2ab195..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/tim.c +++ /dev/null @@ -1,233 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : tim.c -* Author : MCD Application Team -* Date First Issued : 09/08/2003 -* Description : This file provides all the TIM software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "tim.h" - -/******************************************************************************* -* Function Name : TIM_Init -* Description : This routine is used to Initialize the TIM peripheral -* Input : TIM Timer to Initialize -* Return : None -*******************************************************************************/ -void TIM_Init( TIM_TypeDef *TIMx ) -{ - TIMx->CR1 = 0x0000; - TIMx->CR2 = 0x0000; - TIMx->SR = 0x0000; -} - -/******************************************************************************* -* Function Name : TIM_ICAPModeConfig -* Description : This routine is used to configure the input capture feature -* Input : (1) TIM Timer -* : (2) Input Capture Channel ( Channel_A or Channel_B ) -* : (3) Active Edge : Rising edge or Falling edge. -* Output : None -*******************************************************************************/ -void TIM_ICAPModeConfig ( TIM_TypeDef *TIMx, - TIM_Channels Xchannel, - TIM_Clock_Edges Xedge ) -{ - switch (Xchannel) - { - case TIM_CHANNEL_A : - if (Xedge == TIM_RISING) TIMx->CR1 |= TIM_IEDGA_Mask; else TIMx->CR1 &= ~TIM_IEDGA_Mask; - break; - case TIM_CHANNEL_B : - if (Xedge == TIM_RISING) TIMx->CR1 |= TIM_IEDGB_Mask; else TIMx->CR1 &= ~TIM_IEDGB_Mask; - break; - } -} - -/******************************************************************************* -* Function Name : TIM_OCMPModeConfig -* Description : This routine is used to configure the output compare feature -* Input : (1) TIM Timer -* : (2) OCMP Channel ( Channel_A or Channel_B ) -* : (3) Pulse Length -* : (4) OC_Mode : output wave, or only timing. -* : (5) Level : Rising edge or Falling edge after the == -* Output : None -*******************************************************************************/ -void TIM_OCMPModeConfig ( TIM_TypeDef *TIMx, - TIM_Channels Xchannel, - u16 XpulseLength, - TIM_OC_Modes Xmode, - TIM_Logic_Levels Xlevel ) -{ - u16 Tmp1 = 0x0000; - u16 Tmp2 = TIMx->CR2; - - TIMx->CR2 = 0x0000; - // Start The TIM Counter - TIMx->CR1 = TIM_EN_Mask; - // Update the CR2 Register - TIMx->CR2 = Tmp2; - switch ( Xmode ) - { - case TIM_TIMING : - // Output Compare Used only for Internal Timing Operation - Tmp1 = Xchannel == TIM_CHANNEL_A ? Tmp1 & ~TIM_OCAE_Mask : Tmp1 & ~TIM_OCBE_Mask; - break; - case TIM_WAVE : - // Output Compare Used for external wave generation - Tmp1 = Xchannel == TIM_CHANNEL_A ? TIM_OCAE_Mask : TIM_OCBE_Mask; - if ( Xlevel == TIM_HIGH ) - Tmp1 = Xchannel == TIM_CHANNEL_A ? Tmp1 | TIM_OLVLA_Mask : Tmp1 | TIM_OLVLB_Mask; - else - Tmp1 = Xchannel == TIM_CHANNEL_A ? Tmp1 & ~TIM_OLVLA_Mask : Tmp1 & ~TIM_OLVLB_Mask; - break; - } - if ( Xchannel == TIM_CHANNEL_A ) - TIMx->OCAR = ( XpulseLength); - else - TIMx->OCBR = ( XpulseLength); - TIMx->CNTR = 0x0000; - TIMx->CR1 |= Tmp1; -} - -/******************************************************************************* -* Function Name : TIM_OPModeConfig -* Description : This routine is used to configure the one pulse mode -* Input : (1) TIM Timer -* : (3) XpulseLength : Length of the pulse -* : (4) Level1 : Level during the pulse -* : (5) Level2 : Level after the pulse -* : (6) Activation Edge : High or Low on ICAP A -* Output : None -*******************************************************************************/ -void TIM_OPModeConfig ( TIM_TypeDef *TIMx, - u16 XpulseLength, - TIM_Logic_Levels XLevel1, - TIM_Logic_Levels XLevel2, - TIM_Clock_Edges Xedge ) -{ - u16 Tmp = 0; - - // Set the Level During the pulse - if (XLevel1 == TIM_HIGH) Tmp |= TIM_OLVLB_Mask; - // Set the Level after After the pulse - if (XLevel2 == TIM_HIGH) Tmp |= TIM_OLVLA_Mask; - // Set the Activation Edge on the INCAP 1 - if (Xedge == TIM_RISING) Tmp |= TIM_IEDGA_Mask; - // Set the Output Compare Function - Tmp |= TIM_OCAE_Mask; - // Set the One pulse mode - Tmp |= TIM_OMP_Mask; - // Update the CR1 register Value - TIMx->CR1 = Tmp; - // Set the Pulse length - TIMx->OCAR = XpulseLength; -} - -/******************************************************************************* -* Function Name : TIM_PWMOModeConfig -* Description : This routine is used to configure the PWM in output mode -* Input : (1) TIM Timer -* : (2) DutyCycle : u16 -* : (3) Level 1 : During the Duty Cycle -* : (4) Level 2 : During the after the pulse -* : (5) Full period : u16 -* Output : None -*******************************************************************************/ -void TIM_PWMOModeConfig ( TIM_TypeDef *TIMx, - u16 XDutyCycle, - TIM_Logic_Levels XLevel1, - u16 XFullperiod, - TIM_Logic_Levels XLevel2 - ) -{ - u16 Tmp = TIMx->CR1; - // Set the Level During the pulse - Tmp = XLevel1 == TIM_HIGH ? Tmp | TIM_OLVLB_Mask : Tmp & ~TIM_OLVLB_Mask; - // Set the Level after After the pulse - Tmp = XLevel2 == TIM_HIGH ? Tmp | TIM_OLVLA_Mask : Tmp & ~TIM_OLVLA_Mask; - // Set the OCAE - Tmp |= TIM_OCAE_Mask; - // Set the PWM Bit - Tmp |= TIM_PWM_Mask; - // Update the CR1 - TIMx->CR1 = Tmp; - // Set the Duty Cycle value - if ( XDutyCycle < 5 ) XDutyCycle = 5; - TIMx->OCAR = XDutyCycle - 5; - // Set the Full Period - TIMx->OCBR = XFullperiod - 5; -} - -/******************************************************************************* -* Function Name : TIM_PWMInputConfig -* Description : This routine is used to configure the PWM in input mode -* Input : (1) TIM Timer -* : (2) First Activation Edge -* Output : None -*******************************************************************************/ -void TIM_PWMIModeConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge ) -{ - u16 Tmp = TIMx->CR1; - // Set the first edge Level - Tmp = Xedge == TIM_RISING ? Tmp | TIM_IEDGA_Mask : Tmp & ~TIM_IEDGA_Mask; - // Set the Second edge Level ( Opposit of the first level ) - Tmp = Xedge == TIM_FALLING ? Tmp | TIM_IEDGB_Mask : Tmp & ~TIM_IEDGB_Mask; - // Set the PWM I Bit - Tmp |= TIM_PWMI_Mask; - // Update the CR1 - TIMx->CR1 = Tmp; -} - -/******************************************************************************* -* Function Name : TIM_PWMIValue -* Description : This routine is used to get the PWMI values -* Input : (1) TIM Timer -* Output : PWMI_parameters : - u16 Dyty cycle - - u16 Full period -*******************************************************************************/ -PWMI_parameters TIM_PWMIValue ( TIM_TypeDef *TIMx ) -{ - PWMI_parameters Tmp; - Tmp.Pulse = TIMx->ICBR; - Tmp.Period = TIMx->ICAR; - return Tmp; -} - -/******************************************************************************* -* Function Name : TIM_PWMInputConfig -* Description : This routine is used to configure the PWM in input mode -* Input : (1) TIM Timer -* : (2) First Activation Edge -* Output : None -*******************************************************************************/ -void TIM_CounterConfig ( TIM_TypeDef *TIMx, TIM_CounterOperations Xoperation ) -{ - switch ( Xoperation ) - { - case TIM_START : - TIMx->CR1 |= TIM_EN_Mask; - break; - case TIM_STOP : - TIMx->CR1 &= ~TIM_EN_Mask; - break; - case TIM_CLEAR : - TIMx->CNTR = 0x1234; - break; - } -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/uart.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/uart.c deleted file mode 100644 index db4c94e10..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/uart.c +++ /dev/null @@ -1,366 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : uart.c -* Author : MCD Application Team -* Date First Issued : 06/08/2003 -* Description : This file provides all the UART software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "uart.h" - -/******************************************************************************* -* Function Name : UART_Init -* Description : This function initializes the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Output : None -* Return : None -*******************************************************************************/ -void UART_Init(UART_TypeDef *UARTx) -{ - UARTx->IER = 0x00; - UARTx->CR = 0x00; - (void)UARTx->RxBUFR; - UARTx->RxRSTR = 0xFFFF; - UARTx->TxRSTR = 0xFFFF; -} - -/******************************************************************************* -* Function Name : UART_BaudRateConfig -* Description : This function configures the baud rate of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The baudrate value -* Output : None -* Return : None -*******************************************************************************/ -void UART_BaudRateConfig(UART_TypeDef *UARTx, u32 BaudRate) -{ - UARTx->BR = (u16)(RCCU_FrequencyValue(RCCU_FCLK)/(16UL * BaudRate)); -} - -/******************************************************************************* -* Function Name : UART_Config -* Description : This function configures the baudrate, the mode, the data -* parity and the number of stop bits of the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The baudrate value -* Input 3 : The parity type -* Input 4 : The number of stop bits -* Input 5 : The UART mode -* Output : None -* Return : None -*******************************************************************************/ -void UART_Config(UART_TypeDef *UARTx, u32 BaudRate, UARTParity_TypeDef Parity, - UARTStopBits_TypeDef StopBits, UARTMode_TypeDef Mode) -{ - UART_ModeConfig(UARTx, Mode); - UART_BaudRateConfig(UARTx, BaudRate); - UART_ParityConfig(UARTx, Parity); - UART_StopBitsConfig(UARTx, StopBits); -} - -/******************************************************************************* -* Function Name : UART_ItConfig -* Description : This function enables or disables the interrupts of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : The new interrupt flag -* Input 3 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_ItConfig(UART_TypeDef *UARTx, u16 UART_Flag, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->IER|=UART_Flag; else UARTx->IER&=~UART_Flag; -} - -/******************************************************************************* -* Function Name : UART_FifoConfig -* Description : This function enables or disables the Rx and Tx FIFOs of -* the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_FifoConfig(UART_TypeDef *UARTx, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->CR|=0x0400; else UARTx->CR&=~0x0400; -} - -/******************************************************************************* -* Function Name : UART_FifoReset -* Description : This function resets the Rx and the Tx FIFOs of the -* selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : UART_RxFIFO or UART_TxFIFO -* Output : None -* Return : None -*******************************************************************************/ -void UART_FifoReset(UART_TypeDef *UARTx, UARTFIFO_TypeDef FIFO) -{ - if (FIFO==UART_RxFIFO) UARTx->RxRSTR=0xFFFF; else UARTx->TxRSTR=0xFFFF; -} - -/******************************************************************************* -* Function Name : UART_LoopBackConfig -* Description : This function enables or disables the loop back mode of -* the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_LoopBackConfig(UART_TypeDef *UARTx, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->CR|=0x0040; else UARTx->CR&=~0x0040; -} - -/******************************************************************************* -* Function Name : UART_RxConfig -* Description : This function enables or disables the UART data reception. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_RxConfig(UART_TypeDef *UARTx, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->CR|=0x0100; else UARTx->CR&=~0x0100; -} - -/******************************************************************************* -* Function Name : UART_OnOffConfig -* Description : This function sets On/Off the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : ENABLE or DISABLE -* Output : None -* Return : None -*******************************************************************************/ -void UART_OnOffConfig(UART_TypeDef *UARTx, FunctionalState NewState) -{ - if (NewState==ENABLE) UARTx->CR|=0x0080; else UARTx->CR&=~0x0080; -} - -/******************************************************************************* -* Function Name : UART_ByteSend -* Description : This function sends a data byte to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data byte to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_ByteSend(UART_TypeDef *UARTx, u8 *Data) -{ - if (UARTx->CR & (0x0001<SR & UART_TxFull)); // while the UART_TxFIFO contain 16 characters. - else // if FIFO DISABLED - while (!(UARTx->SR & UART_TxEmpty)); // while the transmit shift register not empty - UARTx->TxBUFR = *Data; -} - -/******************************************************************************* -* Function Name : UART_9BitByteSend -* Description : This function sends a 9 bits data byte to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_9BitByteSend(UART_TypeDef *UARTx, u16 *Data) -{ - if(UARTx->CR & (0x0001<SR & UART_TxFull)); // while the UART_TxFIFO contain 16 characters. - else // if FIFO DISABLED - while (!(UARTx->SR & UART_TxEmpty)); // while the transmit shift register not empty - UARTx->TxBUFR = *Data; -} - -/******************************************************************************* -* Function Name : UART_DataSend -* Description : This function sends several data bytes to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Input 3 : The data length in bytes -* Output : None -* Return : None -*******************************************************************************/ -void UART_DataSend(UART_TypeDef *UARTx, u8 *Data, u8 DataLength) -{ - while(DataLength--) - { - UART_ByteSend(UARTx,Data); - Data++; - } -} - -/******************************************************************************* -* Function Name : UART_9BitDataSend -* Description : This function sends several 9 bits data bytes to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the data to send -* Input 3 : The data length -* Output : None -* Return : None -*******************************************************************************/ -void UART_9BitDataSend(UART_TypeDef *UARTx, u16 *Data, u8 DataLength) -{ - while(DataLength--) - { - UART_9BitByteSend(UARTx,Data); - Data++; - } -} - -/******************************************************************************* -* Function Name : UART_StringSend -* Description : This function sends a string to the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the string to send -* Output : None -* Return : None -*******************************************************************************/ -void UART_StringSend(UART_TypeDef *UARTx, u8 *String) -{ - u8 *Data=String; - while(*Data != '\0') - UART_ByteSend(UARTx, Data++); - *Data='\0'; - UART_ByteSend(UARTx, Data); -} - -/******************************************************************************* -* Function Name : UART_ByteReceive -* Description : This function gets a data byte from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The time-out period -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_ByteReceive(UART_TypeDef *UARTx, u8 *Data, u8 TimeOut) -{ - u16 wStatus; - UARTx->TOR=TimeOut;// reload the Timeout counter - while (!((wStatus=UARTx->SR) & (UART_TimeOutIdle|UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle - *Data = (u8)UARTx->RxBUFR; // then read the Receive Buffer Register - return wStatus; -} - -/******************************************************************************* -* Function Name : UART_9BitByteReceive -* Description : This function gets a 9 bits data byte from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The time-out period value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_9BitByteReceive(UART_TypeDef *UARTx, u16 *Data, u8 TimeOut) -{ - u16 wStatus; - UARTx->TOR=TimeOut;// reload the Timeout counter - while (!((wStatus=UARTx->SR) & (UART_TimeOutIdle|UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle - *Data = (u16)UARTx->RxBUFR; // then read the RxBUFR - return wStatus; -} - -/******************************************************************************* -* Function Name : UART_DataReceive -* Description : This function gets 8 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The data length -* Input 4 : The time-out period value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_DataReceive(UART_TypeDef *UARTx, u8 *Data, u8 DataLength, u8 TimeOut) -{ - u16 wStatus = 0; - while(DataLength--) - wStatus=UART_ByteReceive(UARTx,Data++,TimeOut); - return wStatus; -} - -/******************************************************************************* -* Function Name : UART_9BitDataReceive -* Description : This function gets 9 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the data will be stored -* Input 3 : The data length -* Input 4 : The time-out value -* Output : The received data -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_9BitDataReceive(UART_TypeDef *UARTx, u16 *Data, u8 DataLength, u8 TimeOut) -{ - u16 wStatus = 0; - while(DataLength--) - wStatus=UART_9BitByteReceive(UARTx,Data++,TimeOut); - return wStatus; -} - -/******************************************************************************* -* Function Name : UART_StringReceive -* Description : This function gets 8 bits data bytes from the selected UART. -* Input 1 : UARTx (x can be 0,1, 2 or 3) the desired UART -* Input 2 : A pointer to the buffer where the string will be stored -* Output : The received string -* Return : The UARTx.SR register contents -*******************************************************************************/ -u16 UART_StringReceive(UART_TypeDef *UARTx, u8 *Data) -{ - u8 *pSTRING=Data; - u16 wStatus; - do - { - while (!((wStatus=UARTx->SR) & (UART_RxHalfFull|UART_RxBufFull)));// while the UART_RxFIFO is empty and no Timeoutidle - *(pSTRING++) = (u8)UARTx->RxBUFR; // then read the RxBUFR - } while((*(pSTRING - 1)!=0x0D)&(*(pSTRING - 1)!='\0')); - *(pSTRING - 1)='\0'; - return wStatus; -} - -#ifdef USE_SERIAL_PORT -/******************************************************************************* -* Function Name : sendchar -* Description : This function sends a character to the selected UART. -* Input 1 : A pointer to the character to send. -* Output : None -* Return : None -*******************************************************************************/ -void sendchar( char *ch ) -{ - #ifdef USE_UART0 - #define UARTx UART0 - #endif /* Use_UART0 */ - - #ifdef USE_UART1 - #define UARTx UART1 - #endif /* Use_UART1 */ - - #ifdef USE_UART2 - #define UARTx UART2 - #endif /* Use_UART2 */ - - #ifdef USE_UART3 - #define UARTx UART3 - #endif /* Use_UART3 */ - - UART_ByteSend(UARTx,(u8 *)ch); -} -#endif /* USE_SERIAL_PORT */ - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/wdg.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/wdg.c deleted file mode 100644 index 1ae16cf54..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/wdg.c +++ /dev/null @@ -1,84 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : WDG.c -* Author : MCD Application Team -* Date First Issued : 10/24/2003 -* Description : This file provides all the WDG software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "wdg.h" - -#ifndef abs - #define abs(x) ((x)>0 ? (x) : -(x)) -#endif - -/******************************************************************************* -* Function Name : FindFactors -* Description : Search for the best (a,b) values that fit n = a*b -* with the following constraints: 1<=a<=256, 1<=b<=65536 -* Input 1 : n: the number to decompose -* Input/Output 2 : a: a pointer to the first factor -* Input/Output 3 : b: a pointer to the second factor -* Return : None -*******************************************************************************/ -static void FindFactors(unsigned long n, unsigned int *a, unsigned long *b) -{ - unsigned long b0; - unsigned int a0; - long err, err_min=n; - - *a = a0 = ((n-1)/65536ul) + 1; - *b = b0 = n / *a; - - for (; *a <= 256; (*a)++) - { - *b = n / *a; - err = (long)*a * (long)*b - (long)n; - if (abs(err) > (*a / 2)) - { - (*b)++; - err = (long)*a * (long)*b - (long)n; - } - if (abs(err) < abs(err_min)) - { - err_min = err; - a0 = *a; - b0 = *b; - if (err == 0) break; - } - } - - *a = a0; - *b = b0; -} - -/******************************************************************************* -* Function Name : WDG_PeriodValueConfig -* Description : Set the prescaler and counter reload value -* Input : Amount of time (us) needed -* Return : None -*******************************************************************************/ -void WDG_PeriodValueConfig ( u32 Time ) -{ - unsigned int a; - unsigned long n, b; - - n = Time * (RCCU_FrequencyValue(RCCU_PCLK) / 1000000); - FindFactors(n, &a, &b); - WDG->PR = a - 1; - WDG->VR = b - 1; -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/xti.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/xti.c deleted file mode 100644 index 3e23dbfb0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/library/xti.c +++ /dev/null @@ -1,87 +0,0 @@ -/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** -* File Name : xti.c -* Author : MCD Application Team -* Date First Issued : 06/08/2003 -* Description : This file provides all the XTI software functions -******************************************************************************** -* History: -* 24/05/2005 : V3.0 -* 30/11/2004 : V2.0 -* 14/07/2004 : V1.3 -* 01/01/2004 : V1.2 -******************************************************************************* - THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH - CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. - AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT - OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT - OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION - CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#include "xti.h" - -/******************************************************************************* -* Function Name : XTI_Init -* Description : Initialize the XTI -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -void XTI_Init(void) -{ - XTI->SR=0x00; - XTI->MRH=0x00; - XTI->MRL=0x00; - XTI->TRH=0x00; - XTI->TRL=0x00; - XTI->PRH=0x00; - XTI->PRL=0x00; - XTI->CTRL=0x00; /* Write the STOP bit twice to reset the STOP state machine */ - XTI->CTRL=0x00; -} - -/******************************************************************************* -* Function Name : XTI_LineModeConfig -* Description : Configure the trigger edge. -* Input 1 : Lines to be configured. -* Input 2 : The trigger edge can be FallingEdge or RisingEdge. -* Output : None -* Return : None -*******************************************************************************/ -void XTI_LineModeConfig(u16 Lines, XTITriggerEdge_TypeDef TriggerEdge) -{ - if(TriggerEdge == XTI_FallingEdge) - { - XTI->TRL &= ~Lines; - XTI->TRH &= ~(Lines>>8)&0x00FF; - } - else - { - XTI->TRL |= Lines; - XTI->TRH |= (Lines>>8)&0x00FF; - } -} - -/******************************************************************************* -* Function Name : XTI_LineConfig -* Description : Enable and disable lines interrupts -* Input 1 : Lines to be configured. -* Input 2 : NewState can be ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void XTI_LineConfig(u16 Lines, FunctionalState NewState) -{ - if(NewState) - { - XTI->MRL |= Lines; - XTI->MRH |= (Lines>>8)&0x00FF; - } - else - { - XTI->MRL &= ~Lines; - XTI->MRH &= ~(Lines>>8)&0x00FF; - } -} - -/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/CHANGELOG b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/CHANGELOG deleted file mode 100644 index 0bf28ac56..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/CHANGELOG +++ /dev/null @@ -1,596 +0,0 @@ -FUTURE - - * TODO: The lwIP source code makes some invalid assumptions on processor - word-length, storage sizes and alignment. See the mailing lists for - problems with exoteric (/DSP) architectures showing these problems. - We still have to fix some of these issues neatly. - - * TODO: the ARP layer is not protected against concurrent access. If - you run from a multitasking OS, serialize access to ARP (called from - your network device driver and from a timeout thread.) - - * TODO: the PPP code is broken in a few ways. There are namespace - collisions on BSD systems and many assumptions on word-length - (sizeof(int)). In ppp.c an assumption is made on the availability of - a thread subsystem. Either PPP needs to be moved to contrib/ports/??? - or rearranged to be more generic. - -HISTORY - -(CVS HEAD) - - * [New changes go here] - -(STABLE-1_1_1) - - 2006-03-03 Christiaan Simons - * ipv4/ip_frag.c: Added bound-checking assertions on ip_reassbitmap - access and added pbuf_alloc() return value checks. - - 2006-01-01 Leon Woestenberg - * tcp_{in,out}.c, tcp_out.c: Removed 'even sndbuf' fix in TCP, which is - now handled by the checksum routine properly. - - 2006-02-27 Leon Woestenberg - * pbuf.c: Fix alignment; pbuf_init() would not work unless - pbuf_pool_memory[] was properly aligned. (Patch by Curt McDowell.) - - 2005-12-20 Leon Woestenberg - * tcp.c: Remove PCBs which stay in LAST_ACK state too long. Patch - submitted by Mitrani Hiroshi. - - 2005-12-15 Christiaan Simons - * inet.c: Disabled the added summing routine to preserve code space. - - 2005-12-14 Leon Woestenberg - * tcp_in.c: Duplicate FIN ACK race condition fix by Kelvin Lawson. - Added Curt McDowell's optimized checksumming routine for future - inclusion. Need to create test case for unaliged, aligned, odd, - even length combination of cases on various endianess machines. - - 2005-12-09 Christiaan Simons - * inet.c: Rewrote standard checksum routine in proper portable C. - - 2005-11-25 Christiaan Simons - * udp.c tcp.c: Removed SO_REUSE hack. Should reside in socket code only. - * *.c: introduced cc.h LWIP_DEBUG formatters matching the u16_t, s16_t, - u32_t, s32_t typedefs. This solves most debug word-length assumes. - - 2005-07-17 Leon Woestenberg - * inet.c: Fixed unaligned 16-bit access in the standard checksum - routine by Peter Jolasson. - * slipif.c: Fixed implementation assumption of single-pbuf datagrams. - - 2005-02-04 Leon Woestenberg - * tcp_out.c: Fixed uninitialized 'queue' referenced in memerr branch. - * tcp_{out|in}.c: Applied patch fixing unaligned access. - - 2005-01-04 Leon Woestenberg - * pbuf.c: Fixed missing semicolon after LWIP_DEBUG statement. - - 2005-01-03 Leon Woestenberg - * udp.c: UDP pcb->recv() was called even when it was NULL. - -(STABLE-1_1_0) - - 2004-12-28 Leon Woestenberg - * etharp.*: Disabled multiple packets on the ARP queue. - This clashes with TCP queueing. - - 2004-11-28 Leon Woestenberg - * etharp.*: Fixed race condition from ARP request to ARP timeout. - Halved the ARP period, doubled the period counts. - ETHARP_MAX_PENDING now should be at least 2. This prevents - the counter from reaching 0 right away (which would allow - too little time for ARP responses to be received). - - 2004-11-25 Leon Woestenberg - * dhcp.c: Decline messages were not multicast but unicast. - * etharp.c: ETHARP_CREATE is renamed to ETHARP_TRY_HARD. - Do not try hard to insert arbitrary packet's source address, - etharp_ip_input() now calls etharp_update() without ETHARP_TRY_HARD. - etharp_query() now always DOES call ETHARP_TRY_HARD so that users - querying an address will see it appear in the cache (DHCP could - suffer from this when a server invalidly gave an in-use address.) - * ipv4/ip_addr.h: Renamed ip_addr_maskcmp() to _netcmp() as we are - comparing network addresses (identifiers), not the network masks - themselves. - * ipv4/ip_addr.c: ip_addr_isbroadcast() now checks that the given - IP address actually belongs to the network of the given interface. - - 2004-11-24 Kieran Mansley - * tcp.c: Increment pcb->snd_buf when ACK is received in SYN_SENT state. - -(STABLE-1_1_0-RC1) - - 2004-10-16 Kieran Mansley - * tcp.c: Add code to tcp_recved() to send an ACK (window update) immediately, - even if one is already pending, if the rcv_wnd is above a threshold - (currently TCP_WND/2). This avoids waiting for a timer to expire to send a - delayed ACK in order to open the window if the stack is only receiving data. - - 2004-09-12 Kieran Mansley - * tcp*.*: Retransmit time-out handling improvement by Sam Jansen. - - 2004-08-20 Tony Mountifield - * etharp.c: Make sure the first pbuf queued on an ARP entry - is properly ref counted. - - 2004-07-27 Tony Mountifield - * debug.h: Added (int) cast in LWIP_DEBUGF() to avoid compiler - warnings about comparison. - * pbuf.c: Stopped compiler complaining of empty if statement - when LWIP_DEBUGF() empty. Closed an unclosed comment. - * tcp.c: Stopped compiler complaining of empty if statement - when LWIP_DEBUGF() empty. - * ip.h Corrected IPH_TOS() macro: returns a byte, so doesn't need htons(). - * inet.c: Added a couple of casts to quiet the compiler. - No need to test isascii(c) before isdigit(c) or isxdigit(c). - - 2004-07-22 Tony Mountifield - * inet.c: Made data types consistent in inet_ntoa(). - Added casts for return values of checksum routines, to pacify compiler. - * ip_frag.c, tcp_out.c, sockets.c, pbuf.c - Small corrections to some debugging statements, to pacify compiler. - - 2004-07-21 Tony Mountifield - * etharp.c: Removed spurious semicolon and added missing end-of-comment. - * ethernetif.c Updated low_level_output() to match prototype for - netif->linkoutput and changed low_level_input() similarly for consistency. - * api_msg.c: Changed recv_raw() from int to u8_t, to match prototype - of raw_recv() in raw.h and so avoid compiler error. - * sockets.c: Added trivial (int) cast to keep compiler happier. - * ip.c, netif.c Changed debug statements to use the tidier ip4_addrN() macros. - -(STABLE-1_0_0) - - ++ Changes: - - 2004-07-05 Leon Woestenberg - * sockets.*: Restructured LWIP_PRIVATE_TIMEVAL. Make sure - your cc.h file defines this either 1 or 0. If non-defined, - defaults to 1. - * .c: Added and includes where used. - * etharp.c: Made some array indices unsigned. - - 2004-06-27 Leon Woestenberg - * netif.*: Added netif_set_up()/down(). - * dhcp.c: Changes to restart program flow. - - 2004-05-07 Leon Woestenberg - * etharp.c: In find_entry(), instead of a list traversal per candidate, do a - single-pass lookup for different candidates. Should exploit locality. - - 2004-04-29 Leon Woestenberg - * tcp*.c: Cleaned up source comment documentation for Doxygen processing. - * opt.h: ETHARP_ALWAYS_INSERT option removed to comply with ARP RFC. - * etharp.c: update_arp_entry() only adds new ARP entries when adviced to by - the caller. This deprecates the ETHARP_ALWAYS_INSERT overrule option. - - ++ Bug fixes: - - 2004-04-27 Leon Woestenberg - * etharp.c: Applied patch of bug #8708 by Toni Mountifield with a solution - suggested by Timmy Brolin. Fix for 32-bit processors that cannot access - non-aligned 32-bit words, such as soms 32-bit TCP/IP header fields. Fix - is to prefix the 14-bit Ethernet headers with two padding bytes. - - 2004-04-23 Leon Woestenberg - * ip_addr.c: Fix in the ip_addr_isbroadcast() check. - * etharp.c: Fixed the case where the packet that initiates the ARP request - is not queued, and gets lost. Fixed the case where the packets destination - address is already known; we now always queue the packet and perform an ARP - request. - -(STABLE-0_7_0) - - ++ Bug fixes: - - * Fixed TCP bug for SYN_SENT to ESTABLISHED state transition. - * Fixed TCP bug in dequeueing of FIN from out of order segment queue. - * Fixed two possible NULL references in rare cases. - -(STABLE-0_6_6) - - ++ Bug fixes: - - * Fixed DHCP which did not include the IP address in DECLINE messages. - - ++ Changes: - - * etharp.c has been hauled over a bit. - -(STABLE-0_6_5) - - ++ Bug fixes: - - * Fixed TCP bug induced by bad window resizing with unidirectional TCP traffic. - * Packets sent from ARP queue had invalid source hardware address. - - ++ Changes: - - * Pass-by ARP requests do now update the cache. - - ++ New features: - - * No longer dependent on ctype.h. - * New socket options. - * Raw IP pcb support. - -(STABLE-0_6_4) - - ++ Bug fixes: - - * Some debug formatters and casts fixed. - * Numereous fixes in PPP. - - ++ Changes: - - * DEBUGF now is LWIP_DEBUGF - * pbuf_dechain() has been re-enabled. - * Mentioned the changed use of CVS branches in README. - -(STABLE-0_6_3) - - ++ Bug fixes: - - * Fixed pool pbuf memory leak in pbuf_alloc(). - Occured if not enough PBUF_POOL pbufs for a packet pbuf chain. - Reported by Savin Zlobec. - - * PBUF_POOL chains had their tot_len field not set for non-first - pbufs. Fixed in pbuf_alloc(). - - ++ New features: - - * Added PPP stack contributed by Marc Boucher - - ++ Changes: - - * Now drops short packets for ICMP/UDP/TCP protocols. More robust. - - * ARP queueuing now queues the latest packet instead of the first. - This is the RFC recommended behaviour, but can be overridden in - lwipopts.h. - -(0.6.2) - - ++ Bugfixes: - - * TCP has been fixed to deal with the new use of the pbuf->ref - counter. - - * DHCP dhcp_inform() crash bug fixed. - - ++ Changes: - - * Removed pbuf_pool_free_cache and pbuf_pool_alloc_cache. Also removed - pbuf_refresh(). This has sped up pbuf pool operations considerably. - Implemented by David Haas. - -(0.6.1) - - ++ New features: - - * The packet buffer implementation has been enhanced to support - zero-copy and copy-on-demand for packet buffers which have their - payloads in application-managed memory. - Implemented by David Haas. - - Use PBUF_REF to make a pbuf refer to RAM. lwIP will use zero-copy - if an outgoing packet can be directly sent on the link, or perform - a copy-on-demand when necessary. - - The application can safely assume the packet is sent, and the RAM - is available to the application directly after calling udp_send() - or similar function. - - ++ Bugfixes: - - * ARP_QUEUEING should now correctly work for all cases, including - PBUF_REF. - Implemented by Leon Woestenberg. - - ++ Changes: - - * IP_ADDR_ANY is no longer a NULL pointer. Instead, it is a pointer - to a '0.0.0.0' IP address. - - * The packet buffer implementation is changed. The pbuf->ref counter - meaning has changed, and several pbuf functions have been - adapted accordingly. - - * netif drivers have to be changed to set the hardware address length field - that must be initialized correctly by the driver (hint: 6 for Ethernet MAC). - See the contrib/ports/c16x cs8900 driver as a driver example. - - * netif's have a dhcp field that must be initialized to NULL by the driver. - See the contrib/ports/c16x cs8900 driver as a driver example. - -(0.5.x) This file has been unmaintained up to 0.6.1. All changes are - logged in CVS but have not been explained here. - -(0.5.3) Changes since version 0.5.2 - - ++ Bugfixes: - - * memp_malloc(MEMP_API_MSG) could fail with multiple application - threads because it wasn't protected by semaphores. - - ++ Other changes: - - * struct ip_addr now packed. - - * The name of the time variable in arp.c has been changed to ctime - to avoid conflicts with the time() function. - -(0.5.2) Changes since version 0.5.1 - - ++ New features: - - * A new TCP function, tcp_tmr(), now handles both TCP timers. - - ++ Bugfixes: - - * A bug in tcp_parseopt() could cause the stack to hang because of a - malformed TCP option. - - * The address of new connections in the accept() function in the BSD - socket library was not handled correctly. - - * pbuf_dechain() did not update the ->tot_len field of the tail. - - * Aborted TCP connections were not handled correctly in all - situations. - - ++ Other changes: - - * All protocol header structs are now packed. - - * The ->len field in the tcp_seg structure now counts the actual - amount of data, and does not add one for SYN and FIN segments. - -(0.5.1) Changes since version 0.5.0 - - ++ New features: - - * Possible to run as a user process under Linux. - - * Preliminary support for cross platform packed structs. - - * ARP timer now implemented. - - ++ Bugfixes: - - * TCP output queue length was badly initialized when opening - connections. - - * TCP delayed ACKs were not sent correctly. - - * Explicit initialization of BSS segment variables. - - * read() in BSD socket library could drop data. - - * Problems with memory alignment. - - * Situations when all TCP buffers were used could lead to - starvation. - - * TCP MSS option wasn't parsed correctly. - - * Problems with UDP checksum calculation. - - * IP multicast address tests had endianess problems. - - * ARP requests had wrong destination hardware address. - - ++ Other changes: - - * struct eth_addr changed from u16_t[3] array to u8_t[6]. - - * A ->linkoutput() member was added to struct netif. - - * TCP and UDP ->dest_* struct members where changed to ->remote_*. - - * ntoh* macros are now null definitions for big endian CPUs. - -(0.5.0) Changes since version 0.4.2 - - ++ New features: - - * Redesigned operating system emulation layer to make porting easier. - - * Better control over TCP output buffers. - - * Documenation added. - - ++ Bugfixes: - - * Locking issues in buffer management. - - * Bugfixes in the sequential API. - - * IP forwarding could cause memory leakage. This has been fixed. - - ++ Other changes: - - * Directory structure somewhat changed; the core/ tree has been - collapsed. - -(0.4.2) Changes since version 0.4.1 - - ++ New features: - - * Experimental ARP implementation added. - - * Skeleton Ethernet driver added. - - * Experimental BSD socket API library added. - - ++ Bugfixes: - - * In very intense situations, memory leakage could occur. This has - been fixed. - - ++ Other changes: - - * Variables named "data" and "code" have been renamed in order to - avoid name conflicts in certain compilers. - - * Variable++ have in appliciable cases been translated to ++variable - since some compilers generate better code in the latter case. - -(0.4.1) Changes since version 0.4 - - ++ New features: - - * TCP: Connection attempts time out earlier than data - transmissions. Nagle algorithm implemented. Push flag set on the - last segment in a burst. - - * UDP: experimental support for UDP-Lite extensions. - - ++ Bugfixes: - - * TCP: out of order segments were in some cases handled incorrectly, - and this has now been fixed. Delayed acknowledgements was broken - in 0.4, has now been fixed. Binding to an address that is in use - now results in an error. Reset connections sometimes hung an - application; this has been fixed. - - * Checksum calculation sometimes failed for chained pbufs with odd - lengths. This has been fixed. - - * API: a lot of bug fixes in the API. The UDP API has been improved - and tested. Error reporting and handling has been - improved. Logical flaws and race conditions for incoming TCP - connections has been found and removed. - - * Memory manager: alignment issues. Reallocating memory sometimes - failed, this has been fixed. - - * Generic library: bcopy was flawed and has been fixed. - - ++ Other changes: - - * API: all datatypes has been changed from generic ones such as - ints, to specified ones such as u16_t. Functions that return - errors now have the correct type (err_t). - - * General: A lot of code cleaned up and debugging code removed. Many - portability issues have been fixed. - - * The license was changed; the advertising clause was removed. - - * C64 port added. - - * Thanks: Huge thanks go to Dagan Galarneau, Horst Garnetzke, Petri - Kosunen, Mikael Caleres, and Frits Wilmink for reporting and - fixing bugs! - -(0.4) Changes since version 0.3.1 - - * Memory management has been radically changed; instead of - allocating memory from a shared heap, memory for objects that are - rapidly allocated and deallocated is now kept in pools. Allocation - and deallocation from those memory pools is very fast. The shared - heap is still present but is used less frequently. - - * The memory, memory pool, and packet buffer subsystems now support - 4-, 2-, or 1-byte alignment. - - * "Out of memory" situations are handled in a more robust way. - - * Stack usage has been reduced. - - * Easier configuration of lwIP parameters such as memory usage, - TTLs, statistics gathering, etc. All configuration parameters are - now kept in a single header file "lwipopts.h". - - * The directory structure has been changed slightly so that all - architecture specific files are kept under the src/arch - hierarchy. - - * Error propagation has been improved, both in the protocol modules - and in the API. - - * The code for the RTXC architecture has been implemented, tested - and put to use. - - * Bugs have been found and corrected in the TCP, UDP, IP, API, and - the Internet checksum modules. - - * Bugs related to porting between a 32-bit and a 16-bit architecture - have been found and corrected. - - * The license has been changed slightly to conform more with the - original BSD license, including the advertisement clause. - -(0.3.1) Changes since version 0.3 - - * Fix of a fatal bug in the buffer management. Pbufs with allocated - RAM never returned the RAM when the pbuf was deallocated. - - * TCP congestion control, window updates and retransmissions did not - work correctly. This has now been fixed. - - * Bugfixes in the API. - -(0.3) Changes since version 0.2 - - * New and improved directory structure. All include files are now - kept in a dedicated include/ directory. - - * The API now has proper error handling. A new function, - netconn_err(), now returns an error code for the connection in - case of errors. - - * Improvements in the memory management subsystem. The system now - keeps a pointer to the lowest free memory block. A new function, - mem_malloc2() tries to allocate memory once, and if it fails tries - to free some memory and retry the allocation. - - * Much testing has been done with limited memory - configurations. lwIP now does a better job when overloaded. - - * Some bugfixes and improvements to the buffer (pbuf) subsystem. - - * Many bugfixes in the TCP code: - - - Fixed a bug in tcp_close(). - - - The TCP receive window was incorrectly closed when out of - sequence segments was received. This has been fixed. - - - Connections are now timed-out of the FIN-WAIT-2 state. - - - The initial congestion window could in some cases be too - large. This has been fixed. - - - The retransmission queue could in some cases be screwed up. This - has been fixed. - - - TCP RST flag now handled correctly. - - - Out of sequence data was in some cases never delivered to the - application. This has been fixed. - - - Retransmitted segments now contain the correct acknowledgment - number and advertised window. - - - TCP retransmission timeout backoffs are not correctly computed - (ala BSD). After a number of retransmissions, TCP now gives up - the connection. - - * TCP connections now are kept on three lists, one for active - connections, one for listening connections, and one for - connections that are in TIME-WAIT. This greatly speeds up the fast - timeout processing for sending delayed ACKs. - - * TCP now provides proper feedback to the application when a - connection has been successfully set up. - - * More comments have been added to the code. The code has also been - somewhat cleaned up. - -(0.2) Initial public release. diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/COPYING b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/COPYING deleted file mode 100644 index e23898b5e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/COPYING +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2001, 2002 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/FILES b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/FILES deleted file mode 100644 index 66253196f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/FILES +++ /dev/null @@ -1,4 +0,0 @@ -src/ - The source code for the lwIP TCP/IP stack. -doc/ - The documentation for lwIP. - -See also the FILES file in each subdirectory. diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/README b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/README deleted file mode 100644 index d9102826f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/README +++ /dev/null @@ -1,74 +0,0 @@ -INTRODUCTION - -lwIP is a small independent implementation of the TCP/IP protocol -suite that has been developed by Adam Dunkels at the Computer and -Networks Architectures (CNA) lab at the Swedish Institute of Computer -Science (SICS). - -The focus of the lwIP TCP/IP implementation is to reduce the RAM usage -while still having a full scale TCP. This making lwIP suitable for use -in embedded systems with tens of kilobytes of free RAM and room for -around 40 kilobytes of code ROM. - -FEATURES - - * IP (Internet Protocol) including packet forwarding over multiple - network interfaces - * ICMP (Internet Control Message Protocol) for network maintenance - and debugging - * UDP (User Datagram Protocol) including experimental UDP-lite - extensions - * TCP (Transmission Control Protocol) with congestion control, RTT - estimation and fast recovery/fast retransmit - * Specialized API for enhanced performance - * Optional Berkeley socket API - -LICENSE - -lwIP is freely available under a BSD license. - -DEVELOPMENT - -lwIP has grown into an excellent TCP/IP stack for embedded devices, -and developers using the stack often submit bug fixes, improvements, -and additions to the stack to further increase its usefulness. - -Development of lwIP is hosted on Savannah, a central point for -software development, maintenance and distribution. Everyone can -help improve lwIP by use of Savannah's interface, CVS and the -mailing list. A core team of developers will commit changes to the -CVS source tree. - -The lwIP TCP/IP stack is maintained in the 'lwip' CVS module and -contributions (such as platform ports) are in the 'contrib' module. - -See doc/savannah.txt for details on CVS server access for users and -developers. - -Last night's CVS tar ball can be downloaded from: - http://savannah.gnu.org/cvs.backups/lwip.tar.gz [CHANGED - NEEDS FIXING] - -The current CVS trees are web-browsable: - http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/lwip/ - http://savannah.nongnu.org/cgi-bin/viewcvs/lwip/contrib/ - -Submit patches and bugs via the lwIP project page: - http://savannah.nongnu.org/projects/lwip/ - - -DOCUMENTATION - -The original out-dated homepage of lwIP and Adam Dunkels' papers on -lwIP are at the official lwIP home page: - http://www.sics.se/~adam/lwip/ - -Self documentation of the source code is regularly extracted from the -current CVS sources and is available from this web page: - http://www.nongnu.org/lwip/ - -Reading Adam's papers, the files in docs/, browsing the source code -documentation and browsing the mailing list archives is a good way to -become familiar with the design of lwIP. - -Adam Dunkels -Leon Woestenberg diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/arch/cc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/arch/cc.h deleted file mode 100644 index 377f219f8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/arch/cc.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * Modifcations: Christian Walter - */ -#ifndef __CC_H__ -#define __CC_H__ - -/* ------------------------ System includes ------------------------------- */ -#include - -/* ------------------------ Project includes ------------------------------ */ -#include "cpu.h" -#include "sys_arch.h" - -/* ------------------------ Defines --------------------------------------- */ - -#define PACK_STRUCT_BEGIN -#define PACK_STRUCT_STRUCT __attribute__ ((__packed__)) -#define PACK_STRUCT_END - -#define PACK_STRUCT_FIELD( x ) x - -#define ALIGN_STRUCT_8_BEGIN -#define ALIGN_STRUCT_8 __attribute__ ((aligned (8))) -#define ALIGN_STRUCT_8_END - -#define LWIP_PLATFORM_ASSERT( x ) sys_assert( x ) -#define LWIP_PLATFORM_DIAG( x, ... ) do{ sys_debug x; } while( 0 ); - -/* Define (sn)printf formatters for these lwIP types */ -#define U16_F "hu" -#define S16_F "hd" -#define X16_F "hx" -#define U32_F "lu" -#define S32_F "ld" -#define X32_F "lx" - -/* ------------------------ Type definitions (lwIP) ----------------------- */ -typedef unsigned char u8_t; -typedef signed char s8_t; -typedef unsigned short u16_t; -typedef signed short s16_t; -typedef unsigned long u32_t; -typedef signed long s32_t; -typedef u32_t mem_ptr_t; -typedef int sys_prot_t; - -/* ------------------------ Prototypes ------------------------------------ */ - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/arch/cpu.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/arch/cpu.h deleted file mode 100644 index 12b4f212c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/arch/cpu.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __CPU_H__ -#define __CPU_H__ - -/* ------------------------ Defines --------------------------------------- */ -#define BYTE_ORDER LITTLE_ENDIAN - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/arch/perf.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/arch/perf.h deleted file mode 100644 index f94640e9f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/arch/perf.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __PERF_H__ -#define __PERF_H__ - -/* ------------------------ Defines --------------------------------------- */ -#define PERF_START /* null definition */ -#define PERF_STOP(x) /* null definition */ - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/arch/sys_arch.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/arch/sys_arch.h deleted file mode 100644 index 9e47406ca..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/arch/sys_arch.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __SYS_ARCH_H__ -#define __SYS_ARCH_H__ - -/* ------------------------ Project includes ------------------------------ */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "semphr.h" - -/* ------------------------ Defines --------------------------------------- */ -#define SYS_MBOX_NULL ( xQueueHandle )0 -#define SYS_THREAD_NULL NULL -#define SYS_SEM_NULL ( xSemaphoreHandle )0 -#define SIO_FD_NULL ( sio_fd_t )NULL - -/* ------------------------ Type definitions ------------------------------ */ - - -typedef xSemaphoreHandle sys_sem_t; -typedef xQueueHandle sys_mbox_t; -typedef void *sys_thread_t; - -/* ------------------------ Prototypes ------------------------------------ */ -sys_thread_t sys_arch_thread_new( void ( *thread ) ( void *arg ), void *arg, - int prio, size_t ssize ); -sys_thread_t sys_arch_thread_current( void ); -void sys_arch_thread_remove( sys_thread_t hdl ); -void sys_assert( const char *const msg ); -void sys_debug( const char *const fmt, ... ); - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/netif/serial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/netif/serial.c deleted file mode 100644 index 842816934..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/netif/serial.c +++ /dev/null @@ -1,627 +0,0 @@ -/* - * FreeModbus Libary: STR71/lwIP Port serial driver. - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - - -/* ----------------------- Platform includes --------------------------------*/ -#include "uart.h" -#include "eic.h" -#include "gpio.h" - -/* ----------------------- lwIP includes ------------------------------------*/ -#include "lwip/opt.h" -#include "lwip/sys.h" -#include "lwip/sio.h" -#include "lwip/err.h" - -/* ----------------------- FreeRTOS includes --------------------------------*/ -#include "task.h" -#include "semphr.h" - -/* ----------------------- Project includes ---------------------------------*/ -#include "serial.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define UART0_DEV ( UART0 ) -#define UART0_RX_PORT ( GPIO0 ) -#define UART0_RX_PIN ( 8 ) -#define UART0_TX_PORT ( GPIO0 ) -#define UART0_TX_PIN ( 9 ) -#define UART0_IRQ_CH ( UART0_IRQChannel ) -#define UART0_IRQ_PRIORITY ( 1 ) - -#define UART1_DEV ( UART1 ) -#define UART1_RX_PORT ( GPIO0 ) -#define UART1_RX_PIN ( 10 ) -#define UART1_TX_PORT ( GPIO0 ) -#define UART1_TX_PIN ( 11 ) -#define UART1_IRQ_CH ( UART1_IRQChannel ) -#define UART1_IRQ_PRIORITY ( 1 ) - -#define UART_DEVICES_MAX ( 2 ) - -#define DEFAULT_BAUDRATE ( 38400 ) -#define DEFAULT_DATABITS ( 8 ) -#define DEFAULT_STOPBITS ( 1 ) -#define DEFAULT_PARITY ( SIO_PAR_NONE ) - -#define DEFAULT_TX_BUFSIZE ( 64 ) -#define DEFAULT_RX_BUFSIZE ( 64 ) - -#define DEFAULT_READTIMEOUT_MS ( 10 ) - -#define SIO_RESET_STATE( dev ) do { \ - ( dev )->ready = 0; \ - ( dev )->abort = 0; \ - ( dev )->UARTx = NULL; \ - ( dev )->rx_buf_rdpos = ( dev )->rx_buf_wrpos = 0; \ - ( dev )->rx_sem = SYS_SEM_NULL; \ - ( dev )->tx_buf_rdpos = ( dev )->tx_buf_wrpos = 0; \ - ( dev )->tx_sem = SYS_SEM_NULL; \ - } while( 0 ) - -#define MS_TO_TICKS( ms ) \ - ( portTickType )( ( portTickType ) ( ms ) / portTICK_RATE_MS ) - -/* ----------------------- Type definitions ---------------------------------*/ -typedef struct -{ - u8_t ready; - u8_t abort; - - u8_t rx_buf[DEFAULT_RX_BUFSIZE]; - u8_t rx_buf_rdpos; - u8_t rx_buf_wrpos; - u8_t rx_buf_cnt; - xSemaphoreHandle rx_sem; - - u8_t tx_buf[DEFAULT_TX_BUFSIZE]; - u8_t tx_buf_rdpos; - u8_t tx_buf_wrpos; - u8_t tx_buf_cnt; - xSemaphoreHandle tx_sem; - UART_TypeDef *UARTx; -} serdev_t; - -/* ----------------------- Prototypes ---------------------------------------*/ -void sio_uart0_irq( void ) __attribute__ ( ( naked ) ); -void sio_uart1_irq( void ) __attribute__ ( ( naked ) ); - -/* ----------------------- Static functions ---------------------------------*/ - -static err_t sio_open_low_level( u8_t devnr, serdev_t * dev ); -static err_t sio_close_low_level( u8_t devnr, serdev_t * dev ); - -/* ----------------------- Static variables ---------------------------------*/ -static u8_t initialized = FALSE; -static volatile serdev_t devices[UART_DEVICES_MAX]; - -/* ----------------------- Start implementation -----------------------------*/ - -err_t -sio_open_low_level( u8_t devnr, serdev_t * dev ) -{ - err_t error = ERR_OK; - - if( devnr == 0 ) - { - /* Return value. */ - dev->UARTx = UART0; - - /* Reset the UART. */ - UART_Init( dev->UARTx ); - - /* Configure the GPIO pints for the UART device. */ - GPIO_Config( UART0_TX_PORT, 1 << UART0_TX_PIN, GPIO_AF_PP ); - GPIO_Config( UART0_RX_PORT, 1 << UART0_RX_PIN, GPIO_IN_TRI_CMOS ); - - /* Configure the IEC for the UART interrupts. */ - EIC_IRQChannelPriorityConfig( UART0_IRQ_CH, UART0_IRQ_PRIORITY ); - EIC_IRQChannelConfig( UART0_IRQ_CH, ENABLE ); - } - else if( devnr == 1 ) - { - /* Return value. */ - dev->UARTx = UART1; - - /* Reset the UART. */ - UART_Init( dev->UARTx ); - - /* Configure the GPIO pints for the UART device. */ - GPIO_Config( UART1_TX_PORT, 1 << UART1_TX_PIN, GPIO_AF_PP ); - GPIO_Config( UART1_RX_PORT, 1 << UART1_RX_PIN, GPIO_IN_TRI_TTL ); - - /* Configure the EIC for the UART interrupts. */ - EIC_IRQChannelPriorityConfig( UART1_IRQ_CH, UART1_IRQ_PRIORITY ); - EIC_IRQChannelConfig( UART1_IRQ_CH, ENABLE ); - } - else - { - error = ERR_IF; - } - return error; -} - -err_t -sio_close_low_level( u8_t devnr, serdev_t * dev ) -{ - err_t error = ERR_OK; - - if( devnr == 0 ) - { - UART_Init( dev->UARTx ); - - /* Disable the GPIO pints for the UART device. */ - GPIO_Config( UART0_TX_PORT, 1 << UART1_TX_PIN, GPIO_IN_TRI_TTL ); - GPIO_Config( UART0_RX_PORT, 1 << UART1_RX_PIN, GPIO_IN_TRI_TTL ); - - /* Disable the UART interrupts in the EIC. */ - EIC_IRQChannelConfig( UART0_IRQ_CH, DISABLE ); - } - else if( devnr == 1 ) - { - UART_Init( dev->UARTx ); - - /* Disable the GPIO pints for the UART device. */ - GPIO_Config( UART1_TX_PORT, 1 << UART1_TX_PIN, GPIO_IN_TRI_TTL ); - GPIO_Config( UART1_RX_PORT, 1 << UART1_RX_PIN, GPIO_IN_TRI_TTL ); - - /* Disable the UART interrupts in the EIC. */ - EIC_IRQChannelConfig( UART1_IRQ_CH, DISABLE ); - } - else - { - error = ERR_IF; - } - return error; -} - -err_t -sio_close( serdev_t * dev ) -{ - int i; - err_t error = ERR_VAL; - - for( i = 0; i < UART_DEVICES_MAX; i++ ) - { - if( &devices[i] == dev ) - { - break; - } - } - if( i < UART_DEVICES_MAX ) - { - vPortEnterCritical( ); - error = sio_close_low_level( i, dev ); - vPortExitCritical( ); - - if( dev->tx_sem != ( xSemaphoreHandle ) 0 ) - { - vQueueDelete( dev->tx_sem ); - } - if( dev->rx_sem != ( xSemaphoreHandle ) 0 ) - { - vQueueDelete( dev->tx_sem ); - } - SIO_RESET_STATE( dev ); - } - - return error; -} - -sio_fd_t -sio_open_new( u8_t devnr, u32_t baudrate, u8_t databits, sio_stop_t stopbits, sio_parity_t parity ) -{ - int i; - err_t error = ERR_OK; - serdev_t *dev; - UARTParity_TypeDef eUARTParity = UART_NO_PARITY; - UARTMode_TypeDef eUARTMode = UARTM_8D; - UARTStopBits_TypeDef eUARTStopBits; - - if( !initialized ) - { - for( i = 0; i < UART_DEVICES_MAX; i++ ) - { - SIO_RESET_STATE( &devices[i] ); - } - initialized = 1; - } - - /* Check if devicename is valid and not in use. */ - if( ( devnr < UART_DEVICES_MAX ) && ( devices[devnr].ready == 0 ) ) - { - dev = ( serdev_t * ) & devices[devnr]; - - switch ( parity ) - { - case SIO_PAR_EVEN: - eUARTParity = UART_EVEN_PARITY; - break; - case SIO_PAR_ODD: - eUARTParity = UART_ODD_PARITY; - break; - case SIO_PAR_NONE: - eUARTParity = UART_NO_PARITY; - break; - default: - error = ERR_VAL; - } - - switch ( databits ) - { - case 7: - if( parity != SIO_PAR_NONE ) - { - eUARTMode = UARTM_7D_P; - } - break; - case 8: - eUARTMode = parity == SIO_PAR_NONE ? UARTM_8D : UARTM_8D_P; - break; - default: - error = ERR_VAL; - } - - switch ( stopbits ) - { - case SIO_STOP_0_5: - eUARTStopBits = UART_0_5_StopBits; - break; - case SIO_STOP_1: - eUARTStopBits = UART_1_StopBits; - break; - case SIO_STOP_1_5: - eUARTStopBits = UART_1_5_StopBits; - break; - case SIO_STOP_2: - eUARTStopBits = UART_2_StopBits; - break; - default: - error = ERR_VAL; - } - - if( error == ERR_OK ) - { - SIO_RESET_STATE( dev ); - - vSemaphoreCreateBinary( dev->rx_sem ); - vSemaphoreCreateBinary( dev->tx_sem ); - - vPortEnterCritical( ); - if( ( error = sio_open_low_level( devnr, dev ) ) != ERR_OK ) - { - /* Hardware interface does not exist. */ - } - else if( dev->tx_sem == ( xSemaphoreHandle ) 0 ) - { - error = ERR_MEM; - } - else if( dev->rx_sem == ( xSemaphoreHandle ) 0 ) - { - error = ERR_MEM; - } - else - { - /* UART parameter correct and hardware device available. */ - UART_OnOffConfig( dev->UARTx, ENABLE ); - UART_FifoConfig( dev->UARTx, ENABLE ); - UART_FifoReset( dev->UARTx, UART_RxFIFO ); - UART_FifoReset( dev->UARTx, UART_TxFIFO ); - UART_LoopBackConfig( dev->UARTx, DISABLE ); - UART_Config( dev->UARTx, baudrate, eUARTParity, eUARTStopBits, eUARTMode ); - UART_TimeOutPeriodConfig( dev->UARTx, 0xFF ); - UART_ItConfig( dev->UARTx, UART_RxBufFull, ENABLE ); - UART_RxConfig( dev->UARTx, ENABLE ); - - /* Device is now ready for use. */ - dev->ready = 1; - } - - if( error != ERR_OK ) - { - sio_close( dev ); - } - vPortExitCritical( ); - } - } - else - { - error = ERR_VAL; - } - return error == ERR_OK ? ( void * )dev : SIO_FD_NULL; -} - -sio_fd_t -sio_open( u8_t devnr ) -{ - return sio_open_new( devnr, DEFAULT_BAUDRATE, DEFAULT_DATABITS, - DEFAULT_STOPBITS, DEFAULT_PARITY ); -} - -void -sio_send_noisr( u8_t data, sio_fd_t fd ) -{ - serdev_t *dev = fd; - - if( dev->ready ) - { - UART_ByteSend( dev->UARTx, &data ); - } -} - -u32_t -sio_write_noisr( sio_fd_t fd, u8_t * buf, u32_t size ) -{ - u32_t left = size; - u8_t send; - serdev_t *dev = fd; - - if( dev->ready ) - { - left = size; - while( left > 0 ) - { - send = size % 256; - UART_DataSend( dev->UARTx, ( u8 * ) buf, ( u8 ) send ); - left -= send; - } - } - return size - left; -} - -void -sio_send( u8_t data, sio_fd_t fd ) -{ - while( sio_write( fd, &data, 1 ) != 1 ); -} - -u8_t -sio_recv( sio_fd_t fd ) -{ - u8_t data; - serdev_t *dev = fd; - - if( dev->ready ) - { - while( sio_read( fd, &data, 1 ) != 1 ); - } - else - { - LWIP_ASSERT( "sio_recv: dev->ready != 0 ", dev->ready != 0 ); - data = '\0'; - } - return data; -} - -u32_t -sio_read( sio_fd_t fd, u8_t * buf, u32_t size ) -{ - u32_t ch_left = size; - u32_t ch_received = 0; - volatile serdev_t *dev = fd; - - if( dev->ready ) - { - dev->abort = 0; - while( ch_left && !dev->abort ) - { - vPortEnterCritical( ); - while( ( dev->rx_buf_cnt > 0 ) && ( ch_left > 0 ) ) - { - /* Fetch character from the ring buffer. */ - *buf++ = dev->rx_buf[dev->rx_buf_rdpos]; - dev->rx_buf_rdpos = ( dev->rx_buf_rdpos + 1 ) % DEFAULT_RX_BUFSIZE; - dev->rx_buf_cnt--; - /* Count character received and left for read. */ - ch_left--; - ch_received++; - } - vPortExitCritical( ); - /* If we want more data block on the semaphore and wait until - * something happens. - */ - if( ch_left ) - { - if( xSemaphoreTake( dev->rx_sem, MS_TO_TICKS( DEFAULT_READTIMEOUT_MS ) ) == - pdFALSE ) - { - /* A timeout. Abort the read and return the characters - * received so far. - */ - dev->abort = 1; - } - } - } - } - return ch_received; -} - -u32_t -sio_write( sio_fd_t fd, u8_t * buf, u32_t size ) -{ - u32_t ch_left; - - volatile serdev_t *dev = fd; - - if( dev->ready ) - { - ch_left = size; - while( ch_left > 0 ) - { - vPortEnterCritical( ); - while( ( dev->tx_buf_cnt < DEFAULT_TX_BUFSIZE ) && ( ch_left > 0 ) ) - { - dev->tx_buf[dev->tx_buf_wrpos] = *buf++; - dev->tx_buf_wrpos = ( dev->tx_buf_wrpos + 1 ) % DEFAULT_TX_BUFSIZE; - dev->tx_buf_cnt++; - ch_left--; - } - /* Enable transmit FIFO empty interrupts and block. */ - UART_ItConfig( dev->UARTx, UART_TxHalfEmpty, ENABLE ); - vPortExitCritical( ); - - /* Not all characters sent within one write. Block on a semaphore - * which is triggered when the buffer is empty again. - */ - if( ch_left != 0 ) - { - while( xSemaphoreTake( dev->tx_sem, portMAX_DELAY ) != pdTRUE ); - } - } - } - return size; -} - -void -sio_read_abort( sio_fd_t fd ) -{ - volatile serdev_t *dev = fd; - - dev->abort = 1; -} - -void -sio_serial_isr( UART_TypeDef * UARTx, u8_t * need_ctx_switch ) -{ - int i; - u16 status; - volatile serdev_t *dev = SIO_FD_NULL; - - portBASE_TYPE rx_woken = pdFALSE; - portBASE_TYPE tx_woken = pdFALSE; - - for( i = 0; i < UART_DEVICES_MAX; i++ ) - { - if( devices[i].ready && ( devices[i].UARTx == UARTx ) ) - { - dev = &devices[i]; - break; - } - } - if( dev != SIO_FD_NULL ) - { - status = UART_FlagStatus( dev->UARTx ); - - /* If there are characters in the UART fifo place them into the - * ring buffer. In case the buffer is filled half or the requested - * number of bytes has been read wakeup the receiver. - */ - if( status & UART_RxBufFull ) - { - do - { - /* Store the character in the ring buffer and advance write - * position. */ - dev->rx_buf[dev->rx_buf_wrpos] = dev->UARTx->RxBUFR; - dev->rx_buf_wrpos = ( dev->rx_buf_wrpos + 1 ) % DEFAULT_RX_BUFSIZE; - - /* Increment the receiver buffer counter. Check for a buffer - * overrun. In that case we have overwritten a old character. - * Therefore we have to advance the read position. Note that - * in this error case we must not increment the read counter - * because an old character was lost. - */ - if( dev->rx_buf_cnt >= DEFAULT_RX_BUFSIZE ) - { - /* LWIP_ASSERT( "sio_serial_isr: receiver buffer overflow", 0 ); */ - dev->rx_buf_rdpos = ( dev->rx_buf_rdpos + 1 ) % DEFAULT_RX_BUFSIZE; - } - else - { - dev->rx_buf_cnt++; - } - - /* Get the new status from the UART. */ - status = UART_FlagStatus( dev->UARTx ); - } - while( status & UART_RxBufFull ); - - /* Wakeup receiver if buffer is starting to fill. */ - if( dev->rx_buf_cnt > ( DEFAULT_RX_BUFSIZE / 2 ) ) - { - rx_woken = xSemaphoreGiveFromISR( dev->rx_sem, rx_woken ); - } - } - - /* Check if we must send characters. */ - if( ( dev->tx_buf_cnt > 0 ) && ( status & UART_TxHalfEmpty ) ) - { - do - { - /* Fetch character from the ring buffer and place them into - * the FIFO. */ - dev->UARTx->TxBUFR = dev->tx_buf[dev->tx_buf_rdpos]; - dev->tx_buf_rdpos = ( dev->tx_buf_rdpos + 1 ) % DEFAULT_TX_BUFSIZE; - dev->tx_buf_cnt--; - - /* Get the new status from the UART. */ - status = UART_FlagStatus( dev->UARTx ); - } - while( ( dev->tx_buf_cnt > 0 ) && ( status & UART_TxHalfEmpty ) ); - - if( dev->tx_buf_cnt == 0 ) - { - tx_woken = xSemaphoreGiveFromISR( dev->tx_sem, tx_woken ); - UART_ItConfig( dev->UARTx, UART_TxHalfEmpty, DISABLE ); - } - } - - if( tx_woken || rx_woken ) - { - *need_ctx_switch = 1; - } - } -} - - -void -sio_uart0_irq( void ) -{ - /* Save context to stack. */ - portENTER_SWITCHING_ISR( ); - - static u8_t need_ctx_switch; - - sio_serial_isr( UART0, &need_ctx_switch ); - - /* End the interrupt in the EIC. */ - EIC->IPR |= 1 << EIC_CurrentIRQChannelValue( ); - - /* End the ISR. */ - portEXIT_SWITCHING_ISR( need_ctx_switch ? pdTRUE : pdFALSE ); -} - -void -sio_uart1_irq( void ) -{ - /* Save context to stack. */ - portENTER_SWITCHING_ISR( ); - - static u8_t need_ctx_switch; - - sio_serial_isr( UART1, &need_ctx_switch ); - - /* End the interrupt in the EIC. */ - EIC->IPR |= 1 << EIC_CurrentIRQChannelValue( ); - - /* End the ISR. */ - portEXIT_SWITCHING_ISR( need_ctx_switch ? pdTRUE : pdFALSE ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/netif/serial.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/netif/serial.h deleted file mode 100644 index 1ddba1f47..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/netif/serial.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * FreeModbus Libary: STR71/lwIP Port serial driver. - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _SERIAL_H -#define _SERIAL_H - -/* ------------------------ Platform includes ----------------------------- */ - -#include "uart.h" - -/* ------------------------ Defines --------------------------------------- */ - -/* ------------------------ Type definitions ----------------------------- */ - -typedef enum -{ - SIO_PAR_NONE, - SIO_PAR_ODD, - SIO_PAR_EVEN -} sio_parity_t; - -typedef enum -{ - SIO_STOP_0_5, - SIO_STOP_1, - SIO_STOP_1_5, - SIO_STOP_2 -} sio_stop_t; - -/* ------------------------ Prototypes ------------------------------------ */ -sio_fd_t sio_open_new( u8_t devnr, u32_t baudrate, u8_t databits, - sio_stop_t stopbits, sio_parity_t parity ); -u32_t sio_write_noisr( sio_fd_t fd, u8_t * buf, u32_t size ); -void sio_send_noisr( u8_t data, sio_fd_t fd ); -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/sys_arch.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/sys_arch.c deleted file mode 100644 index e4d104aec..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/contrib/port/FreeRTOS/STR71X/sys_arch.c +++ /dev/null @@ -1,585 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * Modifications Copyright (c) 2006 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * Modifcations: Christian Walter - * - * $Id$ - */ - -/* ------------------------ System includes ------------------------------- */ -#include -#include -#include -#include - -/* ------------------------ FreeRTOS includes ----------------------------- */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -/* ------------------------ lwIP includes --------------------------------- */ -#include "lwip/debug.h" -#include "lwip/def.h" -#include "lwip/sys.h" -#include "lwip/mem.h" -#include "lwip/sio.h" -#include "lwip/stats.h" - -/* ------------------------ Project includes ------------------------------ */ -#include "netif/serial.h" - -/* ------------------------ Defines --------------------------------------- */ -/* This is the number of threads that can be started with sys_thead_new() */ -#define SYS_MBOX_SIZE ( 16 ) -#define MS_TO_TICKS( ms ) \ - ( portTickType )( ( portTickType ) ( ms ) / portTICK_RATE_MS ) -#define TICKS_TO_MS( ticks ) \ - ( unsigned portLONG )( ( portTickType ) ( ticks ) * portTICK_RATE_MS ) -#define THREAD_STACK_SIZE ( 512 ) -#define THREAD_NAME "lwIP" - -#define THREAD_INIT( tcb ) \ - do { \ - tcb->next = NULL; \ - tcb->pid = ( xTaskHandle )0; \ - tcb->timeouts.next = NULL; \ - } while( 0 ) - -/* ------------------------ Type definitions ------------------------------ */ -typedef struct sys_tcb -{ - struct sys_tcb *next; - struct sys_timeouts timeouts; - xTaskHandle pid; -} sys_tcb_t; - -/* ------------------------ Prototypes ------------------------------------ */ -int putchar( int c ); - -/* ------------------------ Static functions ------------------------------ */ -sys_tcb_t *sys_thread_current( void ); - -/* ------------------------ Static variables ------------------------------ */ -static sys_tcb_t *tasks = NULL; - -/* ------------------------ Start implementation -------------------------- */ -void -sys_init( void ) -{ - LWIP_ASSERT( "sys_init: not called first", tasks == NULL ); - tasks = NULL; -} - -/* - * This optional function does a "fast" critical region protection and returns - * the previous protection level. This function is only called during very short - * critical regions. An embedded system which supports ISR-based drivers might - * want to implement this function by disabling interrupts. Task-based systems - * might want to implement this by using a mutex or disabling tasking. This - * function should support recursive calls from the same task or interrupt. In - * other words, sys_arch_protect() could be called while already protected. In - * that case the return value indicates that it is already protected. - * - * sys_arch_protect() is only required if your port is supporting an operating - * system. - */ -sys_prot_t -sys_arch_protect( void ) -{ - vPortEnterCritical( ); - return 1; -} - -/* - * This optional function does a "fast" set of critical region protection to the - * value specified by pval. See the documentation for sys_arch_protect() for - * more information. This function is only required if your port is supporting - * an operating system. - */ -void -sys_arch_unprotect( sys_prot_t pval ) -{ - ( void )pval; - vPortExitCritical( ); -} - -/* - * Prints an assertion messages and aborts execution. - */ -void -sys_assert( const char *msg ) -{ - extern sio_fd_t stdio_fd; - - ( void )sio_write_noisr( stdio_fd, ( u8_t * ) msg, ( u32_t ) strlen( msg ) ); - ( void )sio_write_noisr( stdio_fd, "\n\r", 2 ); - vPortEnterCritical( ); - for( ;; ); -} - -void -sys_debug( const char *const fmt, ... ) -{ - va_list ap; - - va_start( ap, fmt ); - ( void )vprintf( fmt, ap ); - ( void )putchar( '\r' ); - va_end( ap ); -} - -void -ppp_trace( int level, const char *fmt, ... ) -{ - va_list ap; - - va_start( ap, fmt ); - ( void )vprintf( fmt, ap ); - ( void )putchar( '\r' ); - va_end( ap ); -} - -int -putchar( int c ) -{ - extern sio_fd_t stdio_fd; - - sio_send_noisr( ( u8_t ) c, stdio_fd ); - return c; -} - -/* ------------------------ Start implementation ( Threads ) -------------- */ - -sys_thread_t -sys_thread_new( void ( *thread ) ( void *arg ), void *arg, int prio ) -{ - return sys_arch_thread_new( thread, arg, prio, THREAD_STACK_SIZE ); -} - -/* - * Starts a new thread with priority "prio" that will begin its execution in the - * function "thread()". The "arg" argument will be passed as an argument to the - * thread() function. The argument "ssize" is the requested stack size for the - * new thread. The id of the new thread is returned. Both the id and the - * priority are system dependent. - */ -sys_thread_t -sys_arch_thread_new( void ( *thread ) ( void *arg ), void *arg, int prio, size_t ssize ) -{ - sys_thread_t thread_hdl = SYS_THREAD_NULL; - int i; - sys_tcb_t *p; - char thread_name[ configMAX_TASK_NAME_LEN ]; - - /* We disable the FreeRTOS scheduler because it might be the case that the new - * tasks gets scheduled inside the xTaskCreate function. To prevent this we - * disable the scheduling. Note that this can happen although we have interrupts - * disabled because xTaskCreate contains a call to taskYIELD( ). - */ - vPortEnterCritical( ); - - p = tasks; - i = 0; - /* We are called the first time. Initialize it. */ - if( p == NULL ) - { - p = pvPortMalloc( sizeof( sys_tcb_t ) ); - if( p != NULL ) - { - tasks = p; - } - } - else - { - /* First task already counter. */ - i++; - /* Cycle to the end of the list. */ - while( p->next != NULL ) - { - i++; - p = p->next; - } - p->next = pvPortMalloc( sizeof( sys_tcb_t ) ); - p = p->next; - } - - if( p != NULL ) - { - /* Memory allocated. Initialize the data structure. */ - THREAD_INIT( p ); - ( void )snprintf( thread_name, configMAX_TASK_NAME_LEN, "lwIP%d", i ); - - /* Now q points to a free element in the list. */ - if( xTaskCreate( thread, thread_name, ssize, arg, prio, &p->pid ) == pdPASS ) - { - thread_hdl = p; - } - else - { - vPortFree( p ); - } - } - - vPortExitCritical( ); - return thread_hdl; -} - -void -sys_arch_thread_remove( sys_thread_t hdl ) -{ - sys_tcb_t *current = tasks, *prev; - sys_tcb_t *toremove = hdl; - xTaskHandle pid = ( xTaskHandle ) 0; - - LWIP_ASSERT( "sys_arch_thread_remove: assertion hdl != NULL failed!", hdl != NULL ); - - /* If we have to remove the first task we must update the global "tasks" - * variable. */ - vPortEnterCritical( ); - if( hdl != NULL ) - { - prev = NULL; - while( ( current != NULL ) && ( current != toremove ) ) - { - prev = current; - current = current->next; - } - /* Found it. */ - if( current == toremove ) - { - /* Not the first entry in the list. */ - if( prev != NULL ) - { - prev->next = toremove->next; - } - else - { - tasks = toremove->next; - } - LWIP_ASSERT( "sys_arch_thread_remove: can't remove thread with timeouts!", - toremove->timeouts.next == NULL ); - pid = toremove->pid; - THREAD_INIT( toremove ); - vPortFree( toremove ); - } - } - /* We are done with accessing the shared datastructure. Release the - * resources. - */ - vPortExitCritical( ); - if( pid != ( xTaskHandle ) 0 ) - { - vTaskDelete( pid ); - /* not reached. */ - } -} - -/* - * Returns the thread control block for the currently active task. In case - * of an error the functions returns NULL. - */ -sys_thread_t -sys_arch_thread_current( void ) -{ - sys_tcb_t *p = tasks; - xTaskHandle pid = xTaskGetCurrentTaskHandle( ); - - vPortEnterCritical( ); - while( ( p != NULL ) && ( p->pid != pid ) ) - { - p = p->next; - } - vPortExitCritical( ); - return p; -} - -/* - * Returns a pointer to the per-thread sys_timeouts structure. In lwIP, - * each thread has a list of timeouts which is represented as a linked - * list of sys_timeout structures. The sys_timeouts structure holds a - * pointer to a linked list of timeouts. This function is called by - * the lwIP timeout scheduler and must not return a NULL value. - * - * In a single threaded sys_arch implementation, this function will - * simply return a pointer to a global sys_timeouts variable stored in - * the sys_arch module. - */ -struct sys_timeouts * -sys_arch_timeouts( void ) -{ - sys_tcb_t *ptask; - - ptask = sys_arch_thread_current( ); - LWIP_ASSERT( "sys_arch_timeouts: ptask != NULL", ptask != NULL ); - return ptask != NULL ? &( ptask->timeouts ) : NULL; -} - -/* ------------------------ Start implementation ( Semaphores ) ----------- */ - -/* Creates and returns a new semaphore. The "count" argument specifies - * the initial state of the semaphore. - */ -sys_sem_t -sys_sem_new( u8_t count ) -{ - xSemaphoreHandle xSemaphore; - - vSemaphoreCreateBinary( xSemaphore ); - if( xSemaphore != SYS_SEM_NULL ) - { - if( count == 0 ) - { - xSemaphoreTake( xSemaphore, 1 ); - } -#ifdef SYS_STATS - vPortEnterCritical( ); - lwip_stats.sys.sem.used++; - if( lwip_stats.sys.sem.used > lwip_stats.sys.sem.max ) - { - lwip_stats.sys.sem.max = lwip_stats.sys.sem.used; - } - vPortExitCritical( ); -#endif - } - else - { - LWIP_ASSERT( "sys_sem_new: xSemaphore == SYS_SEM_NULL", xSemaphore != SYS_SEM_NULL ); - } - - return xSemaphore; -} - -/* Deallocates a semaphore */ -void -sys_sem_free( sys_sem_t sem ) -{ - LWIP_ASSERT( "sys_sem_free: sem != SYS_SEM_NULL", sem != SYS_SEM_NULL ); - if( sem != SYS_SEM_NULL ) - { -#ifdef SYS_STATS - vPortEnterCritical( ); - lwip_stats.sys.sem.used--; - vPortExitCritical( ); -#endif - vQueueDelete( sem ); - } -} - -/* Signals a semaphore */ -void -sys_sem_signal( sys_sem_t sem ) -{ - LWIP_ASSERT( "sys_sem_signal: sem != SYS_SEM_NULL", sem != SYS_SEM_NULL ); - xSemaphoreGive( sem ); -} - -/* - * Blocks the thread while waiting for the semaphore to be - * signaled. If the "timeout" argument is non-zero, the thread should - * only be blocked for the specified time (measured in - * milliseconds). - * - * If the timeout argument is non-zero, the return value is the number of - * milliseconds spent waiting for the semaphore to be signaled. If the - * semaphore wasn't signaled within the specified time, the return value is - * SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore - * (i.e., it was already signaled), the function may return zero. - * - * Notice that lwIP implements a function with a similar name, - * sys_sem_wait(), that uses the sys_arch_sem_wait() function. - */ -u32_t -sys_arch_sem_wait( sys_sem_t sem, u32_t timeout ) -{ - portBASE_TYPE xStatus; - portTickType xTicksStart, xTicksEnd, xTicksElapsed; - u32_t timespent; - - LWIP_ASSERT( "sys_arch_sem_wait: sem != SYS_SEM_NULL", sem != SYS_SEM_NULL ); - xTicksStart = xTaskGetTickCount( ); - if( timeout == 0 ) - { - do - { - xStatus = xSemaphoreTake( sem, MS_TO_TICKS( 100 ) ); - } - while( xStatus != pdTRUE ); - } - else - { - xStatus = xSemaphoreTake( sem, MS_TO_TICKS( timeout ) ); - } - - /* Semaphore was signaled. */ - if( xStatus == pdTRUE ) - { - xTicksEnd = xTaskGetTickCount( ); - xTicksElapsed = xTicksEnd - xTicksStart; - timespent = TICKS_TO_MS( xTicksElapsed ); - } - else - { - timespent = SYS_ARCH_TIMEOUT; - } - return timespent; -} - - -/* ------------------------ Start implementation ( Mailboxes ) ------------ */ - -/* Creates an empty mailbox. */ -sys_mbox_t -sys_mbox_new( void ) -{ - xQueueHandle mbox; - - mbox = xQueueCreate( SYS_MBOX_SIZE, sizeof( void * ) ); - if( mbox != SYS_MBOX_NULL ) - { -#ifdef SYS_STATS - vPortEnterCritical( ); - lwip_stats.sys.mbox.used++; - if( lwip_stats.sys.mbox.used > lwip_stats.sys.mbox.max ) - { - lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used; - } - vPortExitCritical( ); -#endif - } - return mbox; -} - -/* - Deallocates a mailbox. If there are messages still present in the - mailbox when the mailbox is deallocated, it is an indication of a - programming error in lwIP and the developer should be notified. -*/ -void -sys_mbox_free( sys_mbox_t mbox ) -{ - void *msg; - - LWIP_ASSERT( "sys_mbox_free: mbox != SYS_MBOX_NULL", mbox != SYS_MBOX_NULL ); - if( mbox != SYS_MBOX_NULL ) - { - while( uxQueueMessagesWaiting( mbox ) != 0 ) - { - if( sys_arch_mbox_fetch( mbox, &msg, 1 ) != SYS_ARCH_TIMEOUT ) - { - LWIP_ASSERT( "sys_mbox_free: memory leak (msg != NULL)", msg == NULL ); - } - } - vQueueDelete( mbox ); -#ifdef SYS_STATS - vPortEnterCritical( ); - lwip_stats.sys.mbox.used--; - vPortExitCritical( ); -#endif - } -} - -/* - * This function sends a message to a mailbox. It is unusual in that no error - * return is made. This is because the caller is responsible for ensuring that - * the mailbox queue will not fail. The caller does this by limiting the number - * of msg structures which exist for a given mailbox. - */ -void -sys_mbox_post( sys_mbox_t mbox, void *data ) -{ - portBASE_TYPE xQueueSent; - - /* Queue must not be full - Otherwise it is an error. */ - xQueueSent = xQueueSend( mbox, &data, 0 ); - LWIP_ASSERT( "sys_mbox_post: xQueueSent == pdPASS", xQueueSent == pdPASS ); -} - -/* - * Blocks the thread until a message arrives in the mailbox, but does - * not block the thread longer than "timeout" milliseconds (similar to - * the sys_arch_sem_wait() function). The "msg" argument is a result - * parameter that is set by the function (i.e., by doing "*msg = - * ptr"). The "msg" parameter maybe NULL to indicate that the message - * should be dropped. - * - * Note that a function with a similar name, sys_mbox_fetch(), is - * implemented by lwIP. - */ -u32_t -sys_arch_mbox_fetch( sys_mbox_t mbox, void **msg, u32_t timeout ) -{ - void *ret_msg; - portBASE_TYPE xStatus; - portTickType xTicksStart, xTicksEnd, xTicksElapsed; - u32_t timespent; - - LWIP_ASSERT( "sys_arch_mbox_fetch: mbox != SYS_MBOX_NULL", mbox != SYS_MBOX_NULL ); - xTicksStart = xTaskGetTickCount( ); - if( timeout == 0 ) - { - do - { - xStatus = xQueueReceive( mbox, &ret_msg, MS_TO_TICKS( 100 ) ); - } - while( xStatus != pdTRUE ); - } - else - { - xStatus = xQueueReceive( mbox, &ret_msg, MS_TO_TICKS( timeout ) ); - } - - if( xStatus == pdTRUE ) - { - if( msg ) - { - *msg = ret_msg; - } - xTicksEnd = xTaskGetTickCount( ); - xTicksElapsed = xTicksEnd - xTicksStart; - timespent = TICKS_TO_MS( xTicksElapsed ); - } - else - { - if( msg ) - { - *msg = NULL; - } - timespent = SYS_ARCH_TIMEOUT; - } - return timespent; -} - -u32_t -sys_jiffies( void ) -{ - portTickType xTicks = xTaskGetTickCount( ); - - return ( u32_t )TICKS_TO_MS( xTicks ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/doc/contrib.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/doc/contrib.txt deleted file mode 100644 index 7c99b9be2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/doc/contrib.txt +++ /dev/null @@ -1,62 +0,0 @@ -1 Introduction - -This document describes some guidelines for people participating -in lwIP development. - -2 How to contribute to lwIP - -Here is a short list of suggestions to anybody working with lwIP and -trying to contribute bug reports, fixes, enhancements, platform ports etc. -First of all as you may already know lwIP is a volunteer project so feedback -to fixes or questions might often come late. Hopefully the bug and patch tracking -features of Savannah help us not lose users' input. - -2.1 Source code style: - -1. do not use tabs. -2. indentation is two spaces per level (i.e. per tab). -3. end debug messages with a trailing newline (\n). -4. one space between keyword and opening bracket. -5. no space between function and opening bracket. -6. one space and no newline before opening curly braces of a block. -7. closing curly brace on a single line. -8. spaces surrounding assignment and comparisons. -9. use current source code style as further reference. - -2.2 Source code documentation style: - -1. JavaDoc compliant and Doxygen compatible. -2. Function documentation above functions in .c files, not .h files. - (This forces you to synchronize documentation and implementation.) -3. Use current documentation style as further reference. - -2.3 Bug reports and patches: - -1. Make sure you are reporting bugs or send patches against the latest - sources. (From the latest release and/or the current CVS sources.) -2. If you think you found a bug make sure it's not already filed in the - bugtracker at Savannah. -3. If you have a fix put the patch on Savannah. If it is a patch that affects - both core and arch specific stuff please separate them so that the core can - be applied separately while leaving the other patch 'open'. The prefered way - is to NOT touch archs you can't test and let maintainers take care of them. - This is a good way to see if they are used at all - the same goes for unix - netifs except tapif. -4. Do not file a bug and post a fix to it to the patch area. Either a bug report - or a patch will be enough. - If you correct an existing bug then attach the patch to the bug rather than creating a new entry in the patch area. -5. Trivial patches (compiler warning, indentation and spelling fixes or anything obvious which takes a line or two) - can go to the lwip-users list. This is still the fastest way of interaction and the list is not so crowded - as to allow for loss of fixes. Putting bugs on Savannah and subsequently closing them is too much an overhead - for reporting a compiler warning fix. -6. Patches should be specific to a single change or to related changes.Do not mix bugfixes with spelling and other - trivial fixes unless the bugfix is trivial too.Do not reorganize code and rename identifiers in the same patch you - change behaviour if not necessary.A patch is easier to read and understand if it's to the point and short than - if it's not to the point and long :) so the chances for it to be applied are greater. - -2.4 Platform porters: - -1. If you have ported lwIP to a platform (an OS, a uC/processor or a combination of these) and - you think it could benefit others[1] you might want discuss this on the mailing list. You - can also ask for CVS access to submit and maintain your port in the contrib CVS module. - \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/doc/rawapi.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/doc/rawapi.txt deleted file mode 100644 index f84e0d2eb..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/doc/rawapi.txt +++ /dev/null @@ -1,386 +0,0 @@ -Raw TCP/IP interface for lwIP - -Authors: Adam Dunkels, Leon Woestenberg, Christiaan Simons - -lwIP provides two Application Program's Interfaces (APIs) for programs -to use for communication with the TCP/IP code: -* low-level "core" / "callback" or "raw" API. -* higher-level "sequential" API. - -The sequential API provides a way for ordinary, sequential, programs -to use the lwIP stack. It is quite similar to the BSD socket API. The -model of execution is based on the blocking open-read-write-close -paradigm. Since the TCP/IP stack is event based by nature, the TCP/IP -code and the application program must reside in different execution -contexts (threads). - -** The remainder of this document discusses the "raw" API. ** - -The raw TCP/IP interface allows the application program to integrate -better with the TCP/IP code. Program execution is event based by -having callback functions being called from within the TCP/IP -code. The TCP/IP code and the application program both run in the same -thread. The sequential API has a much higher overhead and is not very -well suited for small systems since it forces a multithreaded paradigm -on the application. - -The raw TCP/IP interface is not only faster in terms of code execution -time but is also less memory intensive. The drawback is that program -development is somewhat harder and application programs written for -the raw TCP/IP interface are more difficult to understand. Still, this -is the preferred way of writing applications that should be small in -code size and memory usage. - -Both APIs can be used simultaneously by different application -programs. In fact, the sequential API is implemented as an application -program using the raw TCP/IP interface. - ---- Callbacks - -Program execution is driven by callbacks. Each callback is an ordinary -C function that is called from within the TCP/IP code. Every callback -function is passed the current TCP or UDP connection state as an -argument. Also, in order to be able to keep program specific state, -the callback functions are called with a program specified argument -that is independent of the TCP/IP state. - -The function for setting the application connection state is: - -- void tcp_arg(struct tcp_pcb *pcb, void *arg) - - Specifies the program specific state that should be passed to all - other callback functions. The "pcb" argument is the current TCP - connection control block, and the "arg" argument is the argument - that will be passed to the callbacks. - - ---- TCP connection setup - -The functions used for setting up connections is similar to that of -the sequential API and of the BSD socket API. A new TCP connection -identifier (i.e., a protocol control block - PCB) is created with the -tcp_new() function. This PCB can then be either set to listen for new -incoming connections or be explicitly connected to another host. - -- struct tcp_pcb *tcp_new(void) - - Creates a new connection identifier (PCB). If memory is not - available for creating the new pcb, NULL is returned. - -- err_t tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port) - - Binds the pcb to a local IP address and port number. The IP address - can be specified as IP_ADDR_ANY in order to bind the connection to - all local IP addresses. - - If another connection is bound to the same port, the function will - return ERR_USE, otherwise ERR_OK is returned. - -- struct tcp_pcb *tcp_listen(struct tcp_pcb *pcb) - - Commands a pcb to start listening for incoming connections. When an - incoming connection is accepted, the function specified with the - tcp_accept() function will be called. The pcb will have to be bound - to a local port with the tcp_bind() function. - - The tcp_listen() function returns a new connection identifier, and - the one passed as an argument to the function will be - deallocated. The reason for this behavior is that less memory is - needed for a connection that is listening, so tcp_listen() will - reclaim the memory needed for the original connection and allocate a - new smaller memory block for the listening connection. - - tcp_listen() may return NULL if no memory was available for the - listening connection. If so, the memory associated with the pcb - passed as an argument to tcp_listen() will not be deallocated. - -- void tcp_accept(struct tcp_pcb *pcb, - err_t (* accept)(void *arg, struct tcp_pcb *newpcb, - err_t err)) - - Specified the callback function that should be called when a new - connection arrives on a listening connection. - -- err_t tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port, err_t (* connected)(void *arg, - struct tcp_pcb *tpcb, - err_t err)); - - Sets up the pcb to connect to the remote host and sends the - initial SYN segment which opens the connection. - - The tcp_connect() function returns immediately; it does not wait for - the connection to be properly setup. Instead, it will call the - function specified as the fourth argument (the "connected" argument) - when the connection is established. If the connection could not be - properly established, either because the other host refused the - connection or because the other host didn't answer, the "connected" - function will be called with an the "err" argument set accordingly. - - The tcp_connect() function can return ERR_MEM if no memory is - available for enqueueing the SYN segment. If the SYN indeed was - enqueued successfully, the tcp_connect() function returns ERR_OK. - - ---- Sending TCP data - -TCP data is sent by enqueueing the data with a call to -tcp_write(). When the data is successfully transmitted to the remote -host, the application will be notified with a call to a specified -callback function. - -- err_t tcp_write(struct tcp_pcb *pcb, void *dataptr, u16_t len, - u8_t copy) - - Enqueues the data pointed to by the argument dataptr. The length of - the data is passed as the len parameter. The copy argument is either - 0 or 1 and indicates whether the new memory should be allocated for - the data to be copied into. If the argument is 0, no new memory - should be allocated and the data should only be referenced by - pointer. - - The tcp_write() function will fail and return ERR_MEM if the length - of the data exceeds the current send buffer size or if the length of - the queue of outgoing segment is larger than the upper limit defined - in lwipopts.h. The number of bytes available in the output queue can - be retrieved with the tcp_sndbuf() function. - - The proper way to use this function is to call the function with at - most tcp_sndbuf() bytes of data. If the function returns ERR_MEM, - the application should wait until some of the currently enqueued - data has been successfully received by the other host and try again. - -- void tcp_sent(struct tcp_pcb *pcb, - err_t (* sent)(void *arg, struct tcp_pcb *tpcb, - u16_t len)) - - Specifies the callback function that should be called when data has - successfully been received (i.e., acknowledged) by the remote - host. The len argument passed to the callback function gives the - amount bytes that was acknowledged by the last acknowledgment. - - ---- Receiving TCP data - -TCP data reception is callback based - an application specified -callback function is called when new data arrives. When the -application has taken the data, it has to call the tcp_recved() -function to indicate that TCP can advertise increase the receive -window. - -- void tcp_recv(struct tcp_pcb *pcb, - err_t (* recv)(void *arg, struct tcp_pcb *tpcb, - struct pbuf *p, err_t err)) - - Sets the callback function that will be called when new data - arrives. The callback function will be passed a NULL pbuf to - indicate that the remote host has closed the connection. - -- void tcp_recved(struct tcp_pcb *pcb, u16_t len) - - Must be called when the application has received the data. The len - argument indicates the length of the received data. - - ---- Application polling - -When a connection is idle (i.e., no data is either transmitted or -received), lwIP will repeatedly poll the application by calling a -specified callback function. This can be used either as a watchdog -timer for killing connections that have stayed idle for too long, or -as a method of waiting for memory to become available. For instance, -if a call to tcp_write() has failed because memory wasn't available, -the application may use the polling functionality to call tcp_write() -again when the connection has been idle for a while. - -- void tcp_poll(struct tcp_pcb *pcb, u8_t interval, - err_t (* poll)(void *arg, struct tcp_pcb *tpcb)) - - Specifies the polling interval and the callback function that should - be called to poll the application. The interval is specified in - number of TCP coarse grained timer shots, which typically occurs - twice a second. An interval of 10 means that the application would - be polled every 5 seconds. - - ---- Closing and aborting connections - -- err_t tcp_close(struct tcp_pcb *pcb) - - Closes the connection. The function may return ERR_MEM if no memory - was available for closing the connection. If so, the application - should wait and try again either by using the acknowledgment - callback or the polling functionality. If the close succeeds, the - function returns ERR_OK. - - The pcb is deallocated by the TCP code after a call to tcp_close(). - -- void tcp_abort(struct tcp_pcb *pcb) - - Aborts the connection by sending a RST (reset) segment to the remote - host. The pcb is deallocated. This function never fails. - -If a connection is aborted because of an error, the application is -alerted of this event by the err callback. Errors that might abort a -connection are when there is a shortage of memory. The callback -function to be called is set using the tcp_err() function. - -- void tcp_err(struct tcp_pcb *pcb, void (* err)(void *arg, - err_t err)) - - The error callback function does not get the pcb passed to it as a - parameter since the pcb may already have been deallocated. - - ---- Lower layer TCP interface - -TCP provides a simple interface to the lower layers of the -system. During system initialization, the function tcp_init() has -to be called before any other TCP function is called. When the system -is running, the two timer functions tcp_fasttmr() and tcp_slowtmr() -must be called with regular intervals. The tcp_fasttmr() should be -called every TCP_FAST_INTERVAL milliseconds (defined in tcp.h) and -tcp_slowtmr() should be called every TCP_SLOW_INTERVAL milliseconds. - - ---- UDP interface - -The UDP interface is similar to that of TCP, but due to the lower -level of complexity of UDP, the interface is significantly simpler. - -- struct udp_pcb *udp_new(void) - - Creates a new UDP pcb which can be used for UDP communication. The - pcb is not active until it has either been bound to a local address - or connected to a remote address. - -- void udp_remove(struct udp_pcb *pcb) - - Removes and deallocates the pcb. - -- err_t udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port) - - Binds the pcb to a local address. The IP-address argument "ipaddr" - can be IP_ADDR_ANY to indicate that it should listen to any local IP - address. The function currently always return ERR_OK. - -- err_t udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port) - - Sets the remote end of the pcb. This function does not generate any - network traffic, but only set the remote address of the pcb. - -- err_t udp_disconnect(struct udp_pcb *pcb) - - Remove the remote end of the pcb. This function does not generate - any network traffic, but only removes the remote address of the pcb. - -- err_t udp_send(struct udp_pcb *pcb, struct pbuf *p) - - Sends the pbuf p. The pbuf is not deallocated. - -- void udp_recv(struct udp_pcb *pcb, - void (* recv)(void *arg, struct udp_pcb *upcb, - struct pbuf *p, - struct ip_addr *addr, - u16_t port), - void *recv_arg) - - Specifies a callback function that should be called when a UDP - datagram is received. - - ---- System initalization - -A truly complete and generic sequence for initializing the lwip stack -cannot be given because it depends on the build configuration (lwipopts.h) -and additional initializations for your runtime environment (e.g. timers). - -We can give you some idea on how to proceed when using the raw API. -We assume a configuration using a single Ethernet netif and the -UDP and TCP transport layers, IPv4 and the DHCP client. - -Call these functions in the order of appearance: - -- stats_init() - - Clears the structure where runtime statistics are gathered. - -- sys_init() - - Not of much use since we set the NO_SYS 1 option in lwipopts.h, - to be called for easy configuration changes. - -- mem_init() - - Initializes the dynamic memory heap defined by MEM_SIZE. - -- memp_init() - - Initializes the memory pools defined by MEMP_NUM_x. - -- pbuf_init() - - Initializes the pbuf memory pool defined by PBUF_POOL_SIZE. - -- etharp_init() - - Initializes the ARP table and queue. - Note: you must call etharp_tmr at a 10 second regular interval - after this initialization. - -- ip_init() - - Doesn't do much, it should be called to handle future changes. - -- udp_init() - - Clears the UDP PCB list. - -- tcp_init() - - Clears the TCP PCB list and clears some internal TCP timers. - Note: you must call tcp_fasttmr() and tcp_slowtmr() at the - predefined regular intervals after this initialization. - -- netif_add(struct netif *netif, struct ip_addr *ipaddr, - struct ip_addr *netmask, struct ip_addr *gw, - void *state, err_t (* init)(struct netif *netif), - err_t (* input)(struct pbuf *p, struct netif *netif)) - - Adds your network interface to the netif_list. Allocate a struct - netif and pass a pointer to this structure as the first argument. - Give pointers to cleared ip_addr structures when using DHCP, - or fill them with sane numbers otherwise. The state pointer may be NULL. - - The init function pointer must point to a initialization function for - your ethernet netif interface. The following code illustrates it's use. - - err_t netif_if_init(struct netif *netif) - { - u8_t i; - - for(i = 0; i < 6; i++) netif->hwaddr[i] = some_eth_addr[i]; - init_my_eth_device(); - return ERR_OK; - } - - The input function pointer must point to the lwip ip_input(). - -- netif_set_default(struct netif *netif) - - Registers the default network interface. - -- netif_set_up(struct netif *netif) - - When the netif is fully configured this function must be called. - -- dhcp_start(struct netif *netif) - - Creates a new DHCP client for this interface on the first call. - Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at - the predefined regular intervals after starting the client. - - You can peek in the netif->dhcp struct for the actual DHCP status. diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/doc/savannah.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/doc/savannah.txt deleted file mode 100644 index 409905b10..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/doc/savannah.txt +++ /dev/null @@ -1,135 +0,0 @@ -Daily Use Guide for using Savannah for lwIP - -Table of Contents: - -1 - Obtaining lwIP from the CVS repository -2 - Committers/developers CVS access using SSH (to be written) -3 - Merging from DEVEL branch to main trunk (stable branch) -4 - How to release lwIP - - - -1 Obtaining lwIP from the CVS repository ----------------------------------------- - -To perform an anonymous CVS checkout of the main trunk (this is where -bug fixes and incremental enhancements occur), do this: - -cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout lwip - -Or, obtain a stable branch (updated with bug fixes only) as follows: -cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \ - -r STABLE-0_7 -d lwip-0.7 lwip - -Or, obtain a specific (fixed) release as follows: -cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \ - -r STABLE-0_7_0 -d lwip-0.7.0 lwip - -3 Committers/developers CVS access using SSH --------------------------------------------- - -The Savannah server uses SSH (Secure Shell) protocol 2 authentication and encryption. -As such, CVS commits to the server occur through a SSH tunnel for project members. -To create a SSH2 key pair in UNIX-like environments, do this: - -ssh-keygen -t dsa - -Under Windows, a recommended SSH client is "PuTTY", freely available with good -documentation and a graphic user interface. Use its key generator. - -Now paste the id_dsa.pub contents into your Savannah account public key list. Wait -a while so that Savannah can update its configuration (This can take minutes). - -Try to login using SSH: - -ssh -v your_login@cvs.sv.gnu.org - -If it tells you: - -Authenticating with public key "your_key_name"... -Server refused to allocate pty - -then you could login; Savannah refuses to give you a shell - which is OK, as we -are allowed to use SSH for CVS only. Now, you should be able to do this: - -export CVS_RSH=ssh -cvs -z3 -d:ext:your_login@cvs.sv.gnu.org:/sources/lwip co lwip - -after which you can edit your local files with bug fixes or new features and -commit them. Make sure you know what you are doing when using CVS to make -changes on the repository. If in doubt, ask on the lwip-members mailing list. - -(If SSH asks about authenticity of the host, you can check the key - fingerprint against http://savannah.nongnu.org/cvs/?group=lwip) - - -3 Merging from DEVEL branch to main trunk (stable) --------------------------------------------------- - -Merging is a delicate process in CVS and requires the -following disciplined steps in order to prevent conflicts -in the future. Conflicts can be hard to solve! - -Merging from branch A to branch B requires that the A branch -has a tag indicating the previous merger. This tag is called -'merged_from_A_to_B'. After merging, the tag is moved in the -A branch to remember this merger for future merge actions. - -IMPORTANT: AFTER COMMITTING A SUCCESFUL MERGE IN THE -REPOSITORY, THE TAG MUST BE SET ON THE SOURCE BRANCH OF THE -MERGE ACTION (REPLACING EXISTING TAGS WITH THE SAME NAME). - -Merge all changes in DEVEL since our last merge to main: - -In the working copy of the main trunk: -cvs update -P -jmerged_from_DEVEL_to_main -jDEVEL - -(This will apply the changes between 'merged_from_DEVEL_to_main' -and 'DEVEL' to your work set of files) - -We can now commit the merge result. -cvs commit -R -m "Merged from DEVEL to main." - -If this worked out OK, we now move the tag in the DEVEL branch -to this merge point, so we can use this point for future merges: - -cvs rtag -F -r DEVEL merged_from_DEVEL_to_main lwip - -4 How to release lwIP ---------------------- - -First, checkout a clean copy of the branch to be released. Tag this set with -tag name "STABLE-0_6_3". (I use release number 0.6.3 throughout this example). - -Login CVS using pserver authentication, then export a clean copy of the -tagged tree. Export is similar to a checkout, except that the CVS metadata -is not created locally. - -export CVS_RSH=ssh -cvs -z3 -d:pserver:anonymous@cvs.sv.gnu.org:/sources/lwip checkout \ - -r STABLE-0_6_3 -d lwip-0.6.3 lwip - -Archive this directory using tar, gzip'd, bzip2'd and zip'd. - -tar czvf lwip-0.6.3.tar.gz lwip-0.6.3 -tar cjvf lwip-0.6.3.tar.bz2 lwip-0.6.3 -zip -r lwip-0.6.3.zip lwip-0.6.3 - -Now, sign the archives with a detached GPG binary signature as follows: - -gpg -b lwip-0.6.3.tar.gz -gpg -b lwip-0.6.3.tar.bz2 -gpg -b lwip-0.6.3.zip - -Upload these files using anonymous FTP: -ncftp ftp://savannah.gnu.org/incoming/savannah/lwip - -ncftp>mput *0.6.3.* - -Additionally, you may post a news item on Savannah, like this: - -A new 0.6.3 release is now available here: -http://savannah.nongnu.org/files/?group=lwip&highlight=0.6.3 - -You will have to submit this via the user News interface, then approve -this via the Administrator News interface. \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/doc/sys_arch.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/doc/sys_arch.txt deleted file mode 100644 index 95d0add73..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/doc/sys_arch.txt +++ /dev/null @@ -1,194 +0,0 @@ -sys_arch interface for lwIP 0.6++ - -Author: Adam Dunkels - -The operating system emulation layer provides a common interface -between the lwIP code and the underlying operating system kernel. The -general idea is that porting lwIP to new architectures requires only -small changes to a few header files and a new sys_arch -implementation. It is also possible to do a sys_arch implementation -that does not rely on any underlying operating system. - -The sys_arch provides semaphores and mailboxes to lwIP. For the full -lwIP functionality, multiple threads support can be implemented in the -sys_arch, but this is not required for the basic lwIP -functionality. Previous versions of lwIP required the sys_arch to -implement timer scheduling as well but as of lwIP 0.5 this is -implemented in a higher layer. - -In addition to the source file providing the functionality of sys_arch, -the OS emulation layer must provide several header files defining -macros used throughout lwip. The files required and the macros they -must define are listed below the sys_arch description. - -Semaphores can be either counting or binary - lwIP works with both -kinds. Mailboxes are used for message passing and can be implemented -either as a queue which allows multiple messages to be posted to a -mailbox, or as a rendez-vous point where only one message can be -posted at a time. lwIP works with both kinds, but the former type will -be more efficient. A message in a mailbox is just a pointer, nothing -more. - -Semaphores are represented by the type "sys_sem_t" which is typedef'd -in the sys_arch.h file. Mailboxes are equivalently represented by the -type "sys_mbox_t". lwIP does not place any restrictions on how -sys_sem_t or sys_mbox_t are represented internally. - -The following functions must be implemented by the sys_arch: - -- void sys_init(void) - - Is called to initialize the sys_arch layer. - -- sys_sem_t sys_sem_new(u8_t count) - - Creates and returns a new semaphore. The "count" argument specifies - the initial state of the semaphore. - -- void sys_sem_free(sys_sem_t sem) - - Deallocates a semaphore. - -- void sys_sem_signal(sys_sem_t sem) - - Signals a semaphore. - -- u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout) - - Blocks the thread while waiting for the semaphore to be - signaled. If the "timeout" argument is non-zero, the thread should - only be blocked for the specified time (measured in - milliseconds). - - If the timeout argument is non-zero, the return value is the number of - milliseconds spent waiting for the semaphore to be signaled. If the - semaphore wasn't signaled within the specified time, the return value is - SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore - (i.e., it was already signaled), the function may return zero. - - Notice that lwIP implements a function with a similar name, - sys_sem_wait(), that uses the sys_arch_sem_wait() function. - -- sys_mbox_t sys_mbox_new(void) - - Creates an empty mailbox. - -- void sys_mbox_free(sys_mbox_t mbox) - - Deallocates a mailbox. If there are messages still present in the - mailbox when the mailbox is deallocated, it is an indication of a - programming error in lwIP and the developer should be notified. - -- void sys_mbox_post(sys_mbox_t mbox, void *msg) - - Posts the "msg" to the mailbox. - -- u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout) - - Blocks the thread until a message arrives in the mailbox, but does - not block the thread longer than "timeout" milliseconds (similar to - the sys_arch_sem_wait() function). The "msg" argument is a result - parameter that is set by the function (i.e., by doing "*msg = - ptr"). The "msg" parameter maybe NULL to indicate that the message - should be dropped. - - The return values are the same as for the sys_arch_sem_wait() function: - Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a - timeout. - - Note that a function with a similar name, sys_mbox_fetch(), is - implemented by lwIP. - -- struct sys_timeouts *sys_arch_timeouts(void) - - Returns a pointer to the per-thread sys_timeouts structure. In lwIP, - each thread has a list of timeouts which is repressented as a linked - list of sys_timeout structures. The sys_timeouts structure holds a - pointer to a linked list of timeouts. This function is called by - the lwIP timeout scheduler and must not return a NULL value. - - In a single threadd sys_arch implementation, this function will - simply return a pointer to a global sys_timeouts variable stored in - the sys_arch module. - -If threads are supported by the underlying operating system and if -such functionality is needed in lwIP, the following function will have -to be implemented as well: - -- sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio) - - Starts a new thread with priority "prio" that will begin its execution in the - function "thread()". The "arg" argument will be passed as an argument to the - thread() function. The id of the new thread is returned. Both the id and - the priority are system dependent. - -- sys_prot_t sys_arch_protect(void) - - This optional function does a "fast" critical region protection and returns - the previous protection level. This function is only called during very short - critical regions. An embedded system which supports ISR-based drivers might - want to implement this function by disabling interrupts. Task-based systems - might want to implement this by using a mutex or disabling tasking. This - function should support recursive calls from the same task or interrupt. In - other words, sys_arch_protect() could be called while already protected. In - that case the return value indicates that it is already protected. - - sys_arch_protect() is only required if your port is supporting an operating - system. - -- void sys_arch_unprotect(sys_prot_t pval) - - This optional function does a "fast" set of critical region protection to the - value specified by pval. See the documentation for sys_arch_protect() for - more information. This function is only required if your port is supporting - an operating system. - -------------------------------------------------------------------------------- -Additional files required for the "OS support" emulation layer: -------------------------------------------------------------------------------- - -cc.h - Architecture environment, some compiler specific, some - environment specific (probably should move env stuff - to sys_arch.h.) - - Typedefs for the types used by lwip - - u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t - - Compiler hints for packing lwip's structures - - PACK_STRUCT_FIELD(x) - PACK_STRUCT_STRUCT - PACK_STRUCT_BEGIN - PACK_STRUCT_END - - Platform specific diagnostic output - - LWIP_PLATFORM_DIAG(x) - non-fatal, print a message. - LWIP_PLATFORM_ASSERT(x) - fatal, print message and abandon execution. - - "lightweight" synchronization mechanisms - - SYS_ARCH_DECL_PROTECT(x) - declare a protection state variable. - SYS_ARCH_PROTECT(x) - enter protection mode. - SYS_ARCH_UNPROTECT(x) - leave protection mode. - - If the compiler does not provide memset() this file must include a - definition of it, or include a file which defines it. - - This file must either include a system-local which defines - the standard *nix error codes, or it should #define LWIP_PROVIDE_ERRNO - to make lwip/arch.h define the codes which are used throughout. - - -perf.h - Architecture specific performance measurement. - Measurement calls made throughout lwip, these can be defined to nothing. - PERF_START - start measuring something. - PERF_STOP(x) - stop measuring something, and record the result. - -sys_arch.h - Tied to sys_arch.c - - Arch dependent types for the following objects: - sys_sem_t, sys_mbox_t, sys_thread_t, - And, optionally: - sys_prot_t - - Defines to set vars of sys_mbox_t and sys_sem_t to NULL. - SYS_MBOX_NULL NULL - SYS_SEM_NULL NULL diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/FILES b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/FILES deleted file mode 100644 index 2b6573185..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/FILES +++ /dev/null @@ -1,13 +0,0 @@ -api/ - The code for the high-level wrapper API. Not needed if - you use the lowel-level call-back/raw API. - -core/ - The core of the TPC/IP stack; protocol implementations, - memory and buffer management, and the low-level raw API. - -include/ - lwIP include files. - -netif/ - Generic network interface device drivers are kept here, - as well as the ARP module. - -For more information on the various subdirectories, check the FILES -file in each directory. diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/api/api_lib.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/api/api_lib.c deleted file mode 100644 index 3d83d1ea4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/api/api_lib.c +++ /dev/null @@ -1,729 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* This is the part of the API that is linked with - the application */ - -#include "lwip/opt.h" -#include "lwip/api.h" -#include "lwip/api_msg.h" -#include "lwip/memp.h" - - -struct -netbuf *netbuf_new(void) -{ - struct netbuf *buf; - - buf = memp_malloc(MEMP_NETBUF); - if (buf != NULL) { - buf->p = NULL; - buf->ptr = NULL; - return buf; - } else { - return NULL; - } -} - -void -netbuf_delete(struct netbuf *buf) -{ - if (buf != NULL) { - if (buf->p != NULL) { - pbuf_free(buf->p); - buf->p = buf->ptr = NULL; - } - memp_free(MEMP_NETBUF, buf); - } -} - -void * -netbuf_alloc(struct netbuf *buf, u16_t size) -{ - /* Deallocate any previously allocated memory. */ - if (buf->p != NULL) { - pbuf_free(buf->p); - } - buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM); - if (buf->p == NULL) { - return NULL; - } - buf->ptr = buf->p; - return buf->p->payload; -} - -void -netbuf_free(struct netbuf *buf) -{ - if (buf->p != NULL) { - pbuf_free(buf->p); - } - buf->p = buf->ptr = NULL; -} - -void -netbuf_ref(struct netbuf *buf, void *dataptr, u16_t size) -{ - if (buf->p != NULL) { - pbuf_free(buf->p); - } - buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF); - buf->p->payload = dataptr; - buf->p->len = buf->p->tot_len = size; - buf->ptr = buf->p; -} - -void -netbuf_chain(struct netbuf *head, struct netbuf *tail) -{ - pbuf_chain(head->p, tail->p); - head->ptr = head->p; - memp_free(MEMP_NETBUF, tail); -} - -u16_t -netbuf_len(struct netbuf *buf) -{ - return buf->p->tot_len; -} - -err_t -netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len) -{ - if (buf->ptr == NULL) { - return ERR_BUF; - } - *dataptr = buf->ptr->payload; - *len = buf->ptr->len; - return ERR_OK; -} - -s8_t -netbuf_next(struct netbuf *buf) -{ - if (buf->ptr->next == NULL) { - return -1; - } - buf->ptr = buf->ptr->next; - if (buf->ptr->next == NULL) { - return 1; - } - return 0; -} - -void -netbuf_first(struct netbuf *buf) -{ - buf->ptr = buf->p; -} - -void -netbuf_copy_partial(struct netbuf *buf, void *dataptr, u16_t len, u16_t offset) -{ - struct pbuf *p; - u16_t i, left; - - left = 0; - - if(buf == NULL || dataptr == NULL) { - return; - } - - /* This implementation is bad. It should use bcopy - instead. */ - for(p = buf->p; left < len && p != NULL; p = p->next) { - if (offset != 0 && offset >= p->len) { - offset -= p->len; - } else { - for(i = offset; i < p->len; ++i) { - ((u8_t *)dataptr)[left] = ((u8_t *)p->payload)[i]; - if (++left >= len) { - return; - } - } - offset = 0; - } - } -} - -void -netbuf_copy(struct netbuf *buf, void *dataptr, u16_t len) -{ - netbuf_copy_partial(buf, dataptr, len, 0); -} - -struct ip_addr * -netbuf_fromaddr(struct netbuf *buf) -{ - return buf->fromaddr; -} - -u16_t -netbuf_fromport(struct netbuf *buf) -{ - return buf->fromport; -} - -struct -netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto, - void (*callback)(struct netconn *, enum netconn_evt, u16_t len)) -{ - struct netconn *conn; - struct api_msg *msg; - - conn = memp_malloc(MEMP_NETCONN); - if (conn == NULL) { - return NULL; - } - - conn->err = ERR_OK; - conn->type = t; - conn->pcb.tcp = NULL; - - if ((conn->mbox = sys_mbox_new()) == SYS_MBOX_NULL) { - memp_free(MEMP_NETCONN, conn); - return NULL; - } - conn->recvmbox = SYS_MBOX_NULL; - conn->acceptmbox = SYS_MBOX_NULL; - conn->sem = SYS_SEM_NULL; - conn->state = NETCONN_NONE; - conn->socket = 0; - conn->callback = callback; - conn->recv_avail = 0; - - if((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - memp_free(MEMP_NETCONN, conn); - return NULL; - } - - msg->type = API_MSG_NEWCONN; - msg->msg.msg.bc.port = proto; /* misusing the port field */ - msg->msg.conn = conn; - api_msg_post(msg); - sys_mbox_fetch(conn->mbox, NULL); - memp_free(MEMP_API_MSG, msg); - - if ( conn->err != ERR_OK ) { - memp_free(MEMP_NETCONN, conn); - return NULL; - } - - return conn; -} - - -struct -netconn *netconn_new(enum netconn_type t) -{ - return netconn_new_with_proto_and_callback(t,0,NULL); -} - -struct -netconn *netconn_new_with_callback(enum netconn_type t, - void (*callback)(struct netconn *, enum netconn_evt, u16_t len)) -{ - return netconn_new_with_proto_and_callback(t,0,callback); -} - - -err_t -netconn_delete(struct netconn *conn) -{ - struct api_msg *msg; - void *mem; - - if (conn == NULL) { - return ERR_OK; - } - - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - return ERR_MEM; - } - - msg->type = API_MSG_DELCONN; - msg->msg.conn = conn; - api_msg_post(msg); - sys_mbox_fetch(conn->mbox, NULL); - memp_free(MEMP_API_MSG, msg); - - /* Drain the recvmbox. */ - if (conn->recvmbox != SYS_MBOX_NULL) { - while (sys_arch_mbox_fetch(conn->recvmbox, &mem, 1) != SYS_ARCH_TIMEOUT) { - if (conn->type == NETCONN_TCP) { - if(mem != NULL) - pbuf_free((struct pbuf *)mem); - } else { - netbuf_delete((struct netbuf *)mem); - } - } - sys_mbox_free(conn->recvmbox); - conn->recvmbox = SYS_MBOX_NULL; - } - - - /* Drain the acceptmbox. */ - if (conn->acceptmbox != SYS_MBOX_NULL) { - while (sys_arch_mbox_fetch(conn->acceptmbox, &mem, 1) != SYS_ARCH_TIMEOUT) { - netconn_delete((struct netconn *)mem); - } - - sys_mbox_free(conn->acceptmbox); - conn->acceptmbox = SYS_MBOX_NULL; - } - - sys_mbox_free(conn->mbox); - conn->mbox = SYS_MBOX_NULL; - if (conn->sem != SYS_SEM_NULL) { - sys_sem_free(conn->sem); - } - /* conn->sem = SYS_SEM_NULL;*/ - memp_free(MEMP_NETCONN, conn); - return ERR_OK; -} - -enum netconn_type -netconn_type(struct netconn *conn) -{ - return conn->type; -} - -err_t -netconn_peer(struct netconn *conn, struct ip_addr *addr, - u16_t *port) -{ - switch (conn->type) { - case NETCONN_RAW: - /* return an error as connecting is only a helper for upper layers */ - return ERR_CONN; - case NETCONN_UDPLITE: - case NETCONN_UDPNOCHKSUM: - case NETCONN_UDP: - if (conn->pcb.udp == NULL || - ((conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0)) - return ERR_CONN; - *addr = (conn->pcb.udp->remote_ip); - *port = conn->pcb.udp->remote_port; - break; - case NETCONN_TCP: - if (conn->pcb.tcp == NULL) - return ERR_CONN; - *addr = (conn->pcb.tcp->remote_ip); - *port = conn->pcb.tcp->remote_port; - break; - } - return (conn->err = ERR_OK); -} - -err_t -netconn_addr(struct netconn *conn, struct ip_addr **addr, - u16_t *port) -{ - switch (conn->type) { - case NETCONN_RAW: - *addr = &(conn->pcb.raw->local_ip); - *port = conn->pcb.raw->protocol; - break; - case NETCONN_UDPLITE: - case NETCONN_UDPNOCHKSUM: - case NETCONN_UDP: - *addr = &(conn->pcb.udp->local_ip); - *port = conn->pcb.udp->local_port; - break; - case NETCONN_TCP: - *addr = &(conn->pcb.tcp->local_ip); - *port = conn->pcb.tcp->local_port; - break; - } - return (conn->err = ERR_OK); -} - -err_t -netconn_bind(struct netconn *conn, struct ip_addr *addr, - u16_t port) -{ - struct api_msg *msg; - - if (conn == NULL) { - return ERR_VAL; - } - - if (conn->type != NETCONN_TCP && - conn->recvmbox == SYS_MBOX_NULL) { - if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) { - return ERR_MEM; - } - } - - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - return (conn->err = ERR_MEM); - } - msg->type = API_MSG_BIND; - msg->msg.conn = conn; - msg->msg.msg.bc.ipaddr = addr; - msg->msg.msg.bc.port = port; - api_msg_post(msg); - sys_mbox_fetch(conn->mbox, NULL); - memp_free(MEMP_API_MSG, msg); - return conn->err; -} - - -err_t -netconn_connect(struct netconn *conn, struct ip_addr *addr, - u16_t port) -{ - struct api_msg *msg; - - if (conn == NULL) { - return ERR_VAL; - } - - - if (conn->recvmbox == SYS_MBOX_NULL) { - if ((conn->recvmbox = sys_mbox_new()) == SYS_MBOX_NULL) { - return ERR_MEM; - } - } - - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - return ERR_MEM; - } - msg->type = API_MSG_CONNECT; - msg->msg.conn = conn; - msg->msg.msg.bc.ipaddr = addr; - msg->msg.msg.bc.port = port; - api_msg_post(msg); - sys_mbox_fetch(conn->mbox, NULL); - memp_free(MEMP_API_MSG, msg); - return conn->err; -} - -err_t -netconn_disconnect(struct netconn *conn) -{ - struct api_msg *msg; - - if (conn == NULL) { - return ERR_VAL; - } - - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - return ERR_MEM; - } - msg->type = API_MSG_DISCONNECT; - msg->msg.conn = conn; - api_msg_post(msg); - sys_mbox_fetch(conn->mbox, NULL); - memp_free(MEMP_API_MSG, msg); - return conn->err; - -} - -err_t -netconn_listen(struct netconn *conn) -{ - struct api_msg *msg; - - if (conn == NULL) { - return ERR_VAL; - } - - if (conn->acceptmbox == SYS_MBOX_NULL) { - conn->acceptmbox = sys_mbox_new(); - if (conn->acceptmbox == SYS_MBOX_NULL) { - return ERR_MEM; - } - } - - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - return (conn->err = ERR_MEM); - } - msg->type = API_MSG_LISTEN; - msg->msg.conn = conn; - api_msg_post(msg); - sys_mbox_fetch(conn->mbox, NULL); - memp_free(MEMP_API_MSG, msg); - return conn->err; -} - -struct netconn * -netconn_accept(struct netconn *conn) -{ - struct netconn *newconn; - - if (conn == NULL) { - return NULL; - } - - sys_mbox_fetch(conn->acceptmbox, (void **)&newconn); - /* Register event with callback */ - if (conn->callback) - (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, 0); - - return newconn; -} - -struct netbuf * -netconn_recv(struct netconn *conn) -{ - struct api_msg *msg; - struct netbuf *buf; - struct pbuf *p; - u16_t len; - - if (conn == NULL) { - return NULL; - } - - if (conn->recvmbox == SYS_MBOX_NULL) { - conn->err = ERR_CONN; - return NULL; - } - - if (conn->err != ERR_OK) { - return NULL; - } - - if (conn->type == NETCONN_TCP) { - if (conn->pcb.tcp->state == LISTEN) { - conn->err = ERR_CONN; - return NULL; - } - - - buf = memp_malloc(MEMP_NETBUF); - - if (buf == NULL) { - conn->err = ERR_MEM; - return NULL; - } - - sys_mbox_fetch(conn->recvmbox, (void **)&p); - - if (p != NULL) - { - len = p->tot_len; - conn->recv_avail -= len; - } - else - len = 0; - - /* Register event with callback */ - if (conn->callback) - (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, len); - - /* If we are closed, we indicate that we no longer wish to receive - data by setting conn->recvmbox to SYS_MBOX_NULL. */ - if (p == NULL) { - memp_free(MEMP_NETBUF, buf); - sys_mbox_free(conn->recvmbox); - conn->recvmbox = SYS_MBOX_NULL; - return NULL; - } - - buf->p = p; - buf->ptr = p; - buf->fromport = 0; - buf->fromaddr = NULL; - - /* Let the stack know that we have taken the data. */ - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - conn->err = ERR_MEM; - return buf; - } - msg->type = API_MSG_RECV; - msg->msg.conn = conn; - if (buf != NULL) { - msg->msg.msg.len = buf->p->tot_len; - } else { - msg->msg.msg.len = 1; - } - api_msg_post(msg); - - sys_mbox_fetch(conn->mbox, NULL); - memp_free(MEMP_API_MSG, msg); - } else { - sys_mbox_fetch(conn->recvmbox, (void **)&buf); - conn->recv_avail -= buf->p->tot_len; - /* Register event with callback */ - if (conn->callback) - (*conn->callback)(conn, NETCONN_EVT_RCVMINUS, buf->p->tot_len); - } - - - - - LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv: received %p (err %d)\n", (void *)buf, conn->err)); - - - return buf; -} - -err_t -netconn_send(struct netconn *conn, struct netbuf *buf) -{ - struct api_msg *msg; - - if (conn == NULL) { - return ERR_VAL; - } - - if (conn->err != ERR_OK) { - return conn->err; - } - - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - return (conn->err = ERR_MEM); - } - - LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %d bytes\n", buf->p->tot_len)); - msg->type = API_MSG_SEND; - msg->msg.conn = conn; - msg->msg.msg.p = buf->p; - api_msg_post(msg); - - sys_mbox_fetch(conn->mbox, NULL); - memp_free(MEMP_API_MSG, msg); - return conn->err; -} - -err_t -netconn_write(struct netconn *conn, void *dataptr, u16_t size, u8_t copy) -{ - struct api_msg *msg; - u16_t len; - - if (conn == NULL) { - return ERR_VAL; - } - - if (conn->err != ERR_OK) { - return conn->err; - } - - if (conn->sem == SYS_SEM_NULL) { - conn->sem = sys_sem_new(0); - if (conn->sem == SYS_SEM_NULL) { - return ERR_MEM; - } - } - - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - return (conn->err = ERR_MEM); - } - msg->type = API_MSG_WRITE; - msg->msg.conn = conn; - - - conn->state = NETCONN_WRITE; - while (conn->err == ERR_OK && size > 0) { - msg->msg.msg.w.dataptr = dataptr; - msg->msg.msg.w.copy = copy; - - if (conn->type == NETCONN_TCP) { - if (tcp_sndbuf(conn->pcb.tcp) == 0) { - sys_sem_wait(conn->sem); - if (conn->err != ERR_OK) { - goto ret; - } - } - if (size > tcp_sndbuf(conn->pcb.tcp)) { - /* We cannot send more than one send buffer's worth of data at a - time. */ - len = tcp_sndbuf(conn->pcb.tcp); - } else { - len = size; - } - } else { - len = size; - } - - LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_write: writing %d bytes (%d)\n", len, copy)); - msg->msg.msg.w.len = len; - api_msg_post(msg); - sys_mbox_fetch(conn->mbox, NULL); - if (conn->err == ERR_OK) { - dataptr = (void *)((u8_t *)dataptr + len); - size -= len; - } else if (conn->err == ERR_MEM) { - conn->err = ERR_OK; - sys_sem_wait(conn->sem); - } else { - goto ret; - } - } - ret: - memp_free(MEMP_API_MSG, msg); - conn->state = NETCONN_NONE; - if (conn->sem != SYS_SEM_NULL) { - sys_sem_free(conn->sem); - conn->sem = SYS_SEM_NULL; - } - - return conn->err; -} - -err_t -netconn_close(struct netconn *conn) -{ - struct api_msg *msg; - - if (conn == NULL) { - return ERR_VAL; - } - if ((msg = memp_malloc(MEMP_API_MSG)) == NULL) { - return (conn->err = ERR_MEM); - } - - conn->state = NETCONN_CLOSE; - again: - msg->type = API_MSG_CLOSE; - msg->msg.conn = conn; - api_msg_post(msg); - sys_mbox_fetch(conn->mbox, NULL); - if (conn->err == ERR_MEM && - conn->sem != SYS_SEM_NULL) { - sys_sem_wait(conn->sem); - goto again; - } - conn->state = NETCONN_NONE; - memp_free(MEMP_API_MSG, msg); - return conn->err; -} - -err_t -netconn_err(struct netconn *conn) -{ - return conn->err; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/api/api_msg.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/api/api_msg.c deleted file mode 100644 index 762a7060a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/api/api_msg.c +++ /dev/null @@ -1,808 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" -#include "lwip/arch.h" -#include "lwip/api_msg.h" -#include "lwip/memp.h" -#include "lwip/sys.h" -#include "lwip/tcpip.h" - -#if LWIP_RAW -static u8_t -recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p, - struct ip_addr *addr) -{ - struct netbuf *buf; - struct netconn *conn; - - conn = arg; - if (!conn) return 0; - - if (conn->recvmbox != SYS_MBOX_NULL) { - if (!(buf = memp_malloc(MEMP_NETBUF))) { - return 0; - } - pbuf_ref(p); - buf->p = p; - buf->ptr = p; - buf->fromaddr = addr; - buf->fromport = pcb->protocol; - - conn->recv_avail += p->tot_len; - /* Register event with callback */ - if (conn->callback) - (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len); - sys_mbox_post(conn->recvmbox, buf); - } - - return 0; /* do not eat the packet */ -} -#endif -#if LWIP_UDP -static void -recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p, - struct ip_addr *addr, u16_t port) -{ - struct netbuf *buf; - struct netconn *conn; - - conn = arg; - - if (conn == NULL) { - pbuf_free(p); - return; - } - if (conn->recvmbox != SYS_MBOX_NULL) { - buf = memp_malloc(MEMP_NETBUF); - if (buf == NULL) { - pbuf_free(p); - return; - } else { - buf->p = p; - buf->ptr = p; - buf->fromaddr = addr; - buf->fromport = port; - } - - conn->recv_avail += p->tot_len; - /* Register event with callback */ - if (conn->callback) - (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, p->tot_len); - sys_mbox_post(conn->recvmbox, buf); - } -} -#endif /* LWIP_UDP */ -#if LWIP_TCP - -static err_t -recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) -{ - struct netconn *conn; - u16_t len; - - conn = arg; - - if (conn == NULL) { - pbuf_free(p); - return ERR_VAL; - } - - if (conn->recvmbox != SYS_MBOX_NULL) { - - conn->err = err; - if (p != NULL) { - len = p->tot_len; - conn->recv_avail += len; - } - else - len = 0; - /* Register event with callback */ - if (conn->callback) - (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, len); - sys_mbox_post(conn->recvmbox, p); - } - return ERR_OK; -} - - -static err_t -poll_tcp(void *arg, struct tcp_pcb *pcb) -{ - struct netconn *conn; - - conn = arg; - if (conn != NULL && - (conn->state == NETCONN_WRITE || conn->state == NETCONN_CLOSE) && - conn->sem != SYS_SEM_NULL) { - sys_sem_signal(conn->sem); - } - return ERR_OK; -} - -static err_t -sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len) -{ - struct netconn *conn; - - conn = arg; - if (conn != NULL && conn->sem != SYS_SEM_NULL) { - sys_sem_signal(conn->sem); - } - - if (conn && conn->callback) - if (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) - (*conn->callback)(conn, NETCONN_EVT_SENDPLUS, len); - - return ERR_OK; -} - -static void -err_tcp(void *arg, err_t err) -{ - struct netconn *conn; - - conn = arg; - - conn->pcb.tcp = NULL; - - - conn->err = err; - if (conn->recvmbox != SYS_MBOX_NULL) { - /* Register event with callback */ - if (conn->callback) - (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0); - sys_mbox_post(conn->recvmbox, NULL); - } - if (conn->mbox != SYS_MBOX_NULL) { - sys_mbox_post(conn->mbox, NULL); - } - if (conn->acceptmbox != SYS_MBOX_NULL) { - /* Register event with callback */ - if (conn->callback) - (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0); - sys_mbox_post(conn->acceptmbox, NULL); - } - if (conn->sem != SYS_SEM_NULL) { - sys_sem_signal(conn->sem); - } -} - -static void -setup_tcp(struct netconn *conn) -{ - struct tcp_pcb *pcb; - - pcb = conn->pcb.tcp; - tcp_arg(pcb, conn); - tcp_recv(pcb, recv_tcp); - tcp_sent(pcb, sent_tcp); - tcp_poll(pcb, poll_tcp, 4); - tcp_err(pcb, err_tcp); -} - -static err_t -accept_function(void *arg, struct tcp_pcb *newpcb, err_t err) -{ - sys_mbox_t mbox; - struct netconn *newconn; - struct netconn *conn; - -#if API_MSG_DEBUG -#if TCP_DEBUG - tcp_debug_print_state(newpcb->state); -#endif /* TCP_DEBUG */ -#endif /* API_MSG_DEBUG */ - conn = (struct netconn *)arg; - mbox = conn->acceptmbox; - newconn = memp_malloc(MEMP_NETCONN); - if (newconn == NULL) { - return ERR_MEM; - } - newconn->type = NETCONN_TCP; - newconn->pcb.tcp = newpcb; - setup_tcp(newconn); - newconn->recvmbox = sys_mbox_new(); - if (newconn->recvmbox == SYS_MBOX_NULL) { - memp_free(MEMP_NETCONN, newconn); - return ERR_MEM; - } - newconn->mbox = sys_mbox_new(); - if (newconn->mbox == SYS_MBOX_NULL) { - sys_mbox_free(newconn->recvmbox); - memp_free(MEMP_NETCONN, newconn); - return ERR_MEM; - } - newconn->sem = sys_sem_new(0); - if (newconn->sem == SYS_SEM_NULL) { - sys_mbox_free(newconn->recvmbox); - sys_mbox_free(newconn->mbox); - memp_free(MEMP_NETCONN, newconn); - return ERR_MEM; - } - newconn->acceptmbox = SYS_MBOX_NULL; - newconn->err = err; - /* Register event with callback */ - if (conn->callback) - { - (*conn->callback)(conn, NETCONN_EVT_RCVPLUS, 0); - /* We have to set the callback here even though - * the new socket is unknown. Mark the socket as -1. */ - newconn->callback = conn->callback; - newconn->socket = -1; - } - - sys_mbox_post(mbox, newconn); - return ERR_OK; -} -#endif /* LWIP_TCP */ - -static void -do_newconn(struct api_msg_msg *msg) -{ - if(msg->conn->pcb.tcp != NULL) { - /* This "new" connection already has a PCB allocated. */ - /* Is this an error condition? Should it be deleted? - We currently just are happy and return. */ - sys_mbox_post(msg->conn->mbox, NULL); - return; - } - - msg->conn->err = ERR_OK; - - /* Allocate a PCB for this connection */ - switch(msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field */ - raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - msg->conn->pcb.udp = udp_new(); - if(msg->conn->pcb.udp == NULL) { - msg->conn->err = ERR_MEM; - break; - } - udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; - case NETCONN_UDPNOCHKSUM: - msg->conn->pcb.udp = udp_new(); - if(msg->conn->pcb.udp == NULL) { - msg->conn->err = ERR_MEM; - break; - } - udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; - case NETCONN_UDP: - msg->conn->pcb.udp = udp_new(); - if(msg->conn->pcb.udp == NULL) { - msg->conn->err = ERR_MEM; - break; - } - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - msg->conn->pcb.tcp = tcp_new(); - if(msg->conn->pcb.tcp == NULL) { - msg->conn->err = ERR_MEM; - break; - } - setup_tcp(msg->conn); - break; -#endif - default: - LWIP_ASSERT( "do_newconn: msg->conn->type unknown\n", 0 ); - } - - - sys_mbox_post(msg->conn->mbox, NULL); -} - - -static void -do_delconn(struct api_msg_msg *msg) -{ - if (msg->conn->pcb.tcp != NULL) { - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - raw_remove(msg->conn->pcb.raw); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - msg->conn->pcb.udp->recv_arg = NULL; - udp_remove(msg->conn->pcb.udp); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - if (msg->conn->pcb.tcp->state == LISTEN) { - tcp_arg(msg->conn->pcb.tcp, NULL); - tcp_accept(msg->conn->pcb.tcp, NULL); - tcp_close(msg->conn->pcb.tcp); - } else { - tcp_arg(msg->conn->pcb.tcp, NULL); - tcp_sent(msg->conn->pcb.tcp, NULL); - tcp_recv(msg->conn->pcb.tcp, NULL); - tcp_poll(msg->conn->pcb.tcp, NULL, 0); - tcp_err(msg->conn->pcb.tcp, NULL); - if (tcp_close(msg->conn->pcb.tcp) != ERR_OK) { - tcp_abort(msg->conn->pcb.tcp); - } - } -#endif - default: - break; - } - } - /* Trigger select() in socket layer */ - if (msg->conn->callback) - { - (*msg->conn->callback)(msg->conn, NETCONN_EVT_RCVPLUS, 0); - (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDPLUS, 0); - } - - if (msg->conn->mbox != SYS_MBOX_NULL) { - sys_mbox_post(msg->conn->mbox, NULL); - } -} - -static void -do_bind(struct api_msg_msg *msg) -{ - if (msg->conn->pcb.tcp == NULL) { - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */ - raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - msg->conn->pcb.udp = udp_new(); - udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; - case NETCONN_UDPNOCHKSUM: - msg->conn->pcb.udp = udp_new(); - udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; - case NETCONN_UDP: - msg->conn->pcb.udp = udp_new(); - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - msg->conn->pcb.tcp = tcp_new(); - setup_tcp(msg->conn); -#endif /* LWIP_TCP */ - default: - break; - } - } - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - msg->conn->err = raw_bind(msg->conn->pcb.raw,msg->msg.bc.ipaddr); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - msg->conn->err = udp_bind(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - msg->conn->err = tcp_bind(msg->conn->pcb.tcp, - msg->msg.bc.ipaddr, msg->msg.bc.port); -#endif /* LWIP_TCP */ - default: - break; - } - sys_mbox_post(msg->conn->mbox, NULL); -} -#if LWIP_TCP - -static err_t -do_connected(void *arg, struct tcp_pcb *pcb, err_t err) -{ - struct netconn *conn; - - conn = arg; - - if (conn == NULL) { - return ERR_VAL; - } - - conn->err = err; - if (conn->type == NETCONN_TCP && err == ERR_OK) { - setup_tcp(conn); - } - sys_mbox_post(conn->mbox, NULL); - return ERR_OK; -} -#endif - -static void -do_connect(struct api_msg_msg *msg) -{ - if (msg->conn->pcb.tcp == NULL) { - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - msg->conn->pcb.raw = raw_new(msg->msg.bc.port); /* misusing the port field as protocol */ - raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - msg->conn->pcb.udp = udp_new(); - if (msg->conn->pcb.udp == NULL) { - msg->conn->err = ERR_MEM; - sys_mbox_post(msg->conn->mbox, NULL); - return; - } - udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; - case NETCONN_UDPNOCHKSUM: - msg->conn->pcb.udp = udp_new(); - if (msg->conn->pcb.udp == NULL) { - msg->conn->err = ERR_MEM; - sys_mbox_post(msg->conn->mbox, NULL); - return; - } - udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; - case NETCONN_UDP: - msg->conn->pcb.udp = udp_new(); - if (msg->conn->pcb.udp == NULL) { - msg->conn->err = ERR_MEM; - sys_mbox_post(msg->conn->mbox, NULL); - return; - } - udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - msg->conn->pcb.tcp = tcp_new(); - if (msg->conn->pcb.tcp == NULL) { - msg->conn->err = ERR_MEM; - sys_mbox_post(msg->conn->mbox, NULL); - return; - } -#endif - default: - break; - } - } - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - raw_connect(msg->conn->pcb.raw, msg->msg.bc.ipaddr); - sys_mbox_post(msg->conn->mbox, NULL); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - udp_connect(msg->conn->pcb.udp, msg->msg.bc.ipaddr, msg->msg.bc.port); - sys_mbox_post(msg->conn->mbox, NULL); - break; -#endif -#if LWIP_TCP - case NETCONN_TCP: - /* tcp_arg(msg->conn->pcb.tcp, msg->conn);*/ - setup_tcp(msg->conn); - tcp_connect(msg->conn->pcb.tcp, msg->msg.bc.ipaddr, msg->msg.bc.port, - do_connected); - /*tcp_output(msg->conn->pcb.tcp);*/ -#endif - - default: - break; - } -} - -static void -do_disconnect(struct api_msg_msg *msg) -{ - - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - /* Do nothing as connecting is only a helper for upper lwip layers */ - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - udp_disconnect(msg->conn->pcb.udp); - break; -#endif - case NETCONN_TCP: - break; - default: - LWIP_ASSERT( "do_newconn: msg->conn->type unknown\n", 0 ); - } - sys_mbox_post(msg->conn->mbox, NULL); -} - - -static void -do_listen(struct api_msg_msg *msg) -{ - if (msg->conn->pcb.tcp != NULL) { - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen RAW: cannot listen for RAW.\n")); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: listen UDP: cannot listen for UDP.\n")); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - msg->conn->pcb.tcp = tcp_listen(msg->conn->pcb.tcp); - if (msg->conn->pcb.tcp == NULL) { - msg->conn->err = ERR_MEM; - } else { - if (msg->conn->acceptmbox == SYS_MBOX_NULL) { - msg->conn->acceptmbox = sys_mbox_new(); - if (msg->conn->acceptmbox == SYS_MBOX_NULL) { - msg->conn->err = ERR_MEM; - break; - } - } - tcp_arg(msg->conn->pcb.tcp, msg->conn); - tcp_accept(msg->conn->pcb.tcp, accept_function); - } -#endif - default: - break; - } - } - sys_mbox_post(msg->conn->mbox, NULL); -} - -static void -do_accept(struct api_msg_msg *msg) -{ - if (msg->conn->pcb.tcp != NULL) { - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept RAW: cannot accept for RAW.\n")); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - LWIP_DEBUGF(API_MSG_DEBUG, ("api_msg: accept UDP: cannot accept for UDP.\n")); - break; -#endif /* LWIP_UDP */ - case NETCONN_TCP: - break; - default: - LWIP_ASSERT( "do_newconn: msg->conn->type unknown\n", 0 ); - } - } -} - -static void -do_send(struct api_msg_msg *msg) -{ - if (msg->conn->pcb.tcp != NULL) { - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - raw_send(msg->conn->pcb.raw, msg->msg.p); - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - udp_send(msg->conn->pcb.udp, msg->msg.p); - break; -#endif /* LWIP_UDP */ - case NETCONN_TCP: - break; - default: - LWIP_ASSERT( "do_newconn: msg->conn->type unknown\n", 0 ); - } - } - sys_mbox_post(msg->conn->mbox, NULL); -} - -static void -do_recv(struct api_msg_msg *msg) -{ -#if LWIP_TCP - if (msg->conn->pcb.tcp != NULL) { - if (msg->conn->type == NETCONN_TCP) { - tcp_recved(msg->conn->pcb.tcp, msg->msg.len); - } - } -#endif - sys_mbox_post(msg->conn->mbox, NULL); -} - -static void -do_write(struct api_msg_msg *msg) -{ -#if LWIP_TCP - err_t err; -#endif - if (msg->conn->pcb.tcp != NULL) { - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - msg->conn->err = ERR_VAL; - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - msg->conn->err = ERR_VAL; - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - err = tcp_write(msg->conn->pcb.tcp, msg->msg.w.dataptr, - msg->msg.w.len, msg->msg.w.copy); - /* This is the Nagle algorithm: inhibit the sending of new TCP - segments when new outgoing data arrives from the user if any - previously transmitted data on the connection remains - unacknowledged. */ - if(err == ERR_OK && (msg->conn->pcb.tcp->unacked == NULL || (msg->conn->pcb.tcp->flags & TF_NODELAY)) ) { - tcp_output(msg->conn->pcb.tcp); - } - msg->conn->err = err; - if (msg->conn->callback) - if (err == ERR_OK) - { - if (tcp_sndbuf(msg->conn->pcb.tcp) <= TCP_SNDLOWAT) - (*msg->conn->callback)(msg->conn, NETCONN_EVT_SENDMINUS, msg->msg.w.len); - } -#endif - default: - break; - } - } - sys_mbox_post(msg->conn->mbox, NULL); -} - -static void -do_close(struct api_msg_msg *msg) -{ - err_t err; - - err = ERR_OK; - - if (msg->conn->pcb.tcp != NULL) { - switch (msg->conn->type) { -#if LWIP_RAW - case NETCONN_RAW: - break; -#endif -#if LWIP_UDP - case NETCONN_UDPLITE: - /* FALLTHROUGH */ - case NETCONN_UDPNOCHKSUM: - /* FALLTHROUGH */ - case NETCONN_UDP: - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case NETCONN_TCP: - if (msg->conn->pcb.tcp->state == LISTEN) { - err = tcp_close(msg->conn->pcb.tcp); - } - msg->conn->err = err; -#endif - default: - break; - } - } - sys_mbox_post(msg->conn->mbox, NULL); -} - -typedef void (* api_msg_decode)(struct api_msg_msg *msg); -static api_msg_decode decode[API_MSG_MAX] = { - do_newconn, - do_delconn, - do_bind, - do_connect, - do_disconnect, - do_listen, - do_accept, - do_send, - do_recv, - do_write, - do_close - }; -void -api_msg_input(struct api_msg *msg) -{ - decode[msg->type](&(msg->msg)); -} - -void -api_msg_post(struct api_msg *msg) -{ - tcpip_apimsg(msg); -} - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/api/err.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/api/err.c deleted file mode 100644 index b582d88a2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/api/err.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/err.h" - -#ifdef LWIP_DEBUG - -static char *err_strerr[] = {"Ok.", - "Out of memory error.", - "Buffer error.", - "Connection aborted.", - "Connection reset.", - "Connection closed.", - "Not connected.", - "Illegal value.", - "Illegal argument.", - "Routing problem.", - "Address in use." -}; - - -char * -lwip_strerr(err_t err) -{ - return err_strerr[-err]; - -} - - -#endif /* LWIP_DEBUG */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/api/sockets.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/api/sockets.c deleted file mode 100644 index c6c4f8285..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/api/sockets.c +++ /dev/null @@ -1,1362 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - * Improved by Marc Boucher and David Haas - * - */ - -#include -/* #include */ - -#include "lwip/opt.h" -#include "lwip/api.h" -#include "lwip/arch.h" -#include "lwip/sys.h" - -#include "lwip/sockets.h" - -#define NUM_SOCKETS MEMP_NUM_NETCONN - -struct lwip_socket { - struct netconn *conn; - struct netbuf *lastdata; - u16_t lastoffset; - u16_t rcvevent; - u16_t sendevent; - u16_t flags; - int err; -}; - -struct lwip_select_cb -{ - struct lwip_select_cb *next; - fd_set *readset; - fd_set *writeset; - fd_set *exceptset; - int sem_signalled; - sys_sem_t sem; -}; - -static struct lwip_socket sockets[NUM_SOCKETS]; -static struct lwip_select_cb *select_cb_list = 0; - -static sys_sem_t socksem = 0; -static sys_sem_t selectsem = 0; - -static void -event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len); - -static int err_to_errno_table[11] = { - 0, /* ERR_OK 0 No error, everything OK. */ - ENOMEM, /* ERR_MEM -1 Out of memory error. */ - ENOBUFS, /* ERR_BUF -2 Buffer error. */ - ECONNABORTED, /* ERR_ABRT -3 Connection aborted. */ - ECONNRESET, /* ERR_RST -4 Connection reset. */ - ESHUTDOWN, /* ERR_CLSD -5 Connection closed. */ - ENOTCONN, /* ERR_CONN -6 Not connected. */ - EINVAL, /* ERR_VAL -7 Illegal value. */ - EIO, /* ERR_ARG -8 Illegal argument. */ - EHOSTUNREACH, /* ERR_RTE -9 Routing problem. */ - EADDRINUSE /* ERR_USE -10 Address in use. */ -}; - -#define ERR_TO_ERRNO_TABLE_SIZE \ - (sizeof(err_to_errno_table)/sizeof(err_to_errno_table[0])) - -#define err_to_errno(err) \ - (-(err) >= 0 && -(err) < ERR_TO_ERRNO_TABLE_SIZE ? \ - err_to_errno_table[-(err)] : EIO) - -#ifdef ERRNO -#define set_errno(err) errno = (err) -#else -#define set_errno(err) -#endif - -#define sock_set_errno(sk, e) do { \ - sk->err = (e); \ - set_errno(sk->err); \ -} while (0) - - -static struct lwip_socket * -get_socket(int s) -{ - struct lwip_socket *sock; - - if ((s < 0) || (s > NUM_SOCKETS)) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s)); - set_errno(EBADF); - return NULL; - } - - sock = &sockets[s]; - - if (!sock->conn) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s)); - set_errno(EBADF); - return NULL; - } - - return sock; -} - -static int -alloc_socket(struct netconn *newconn) -{ - int i; - - if (!socksem) - socksem = sys_sem_new(1); - - /* Protect socket array */ - sys_sem_wait(socksem); - - /* allocate a new socket identifier */ - for(i = 0; i < NUM_SOCKETS; ++i) { - if (!sockets[i].conn) { - sockets[i].conn = newconn; - sockets[i].lastdata = NULL; - sockets[i].lastoffset = 0; - sockets[i].rcvevent = 0; - sockets[i].sendevent = 1; /* TCP send buf is empty */ - sockets[i].flags = 0; - sockets[i].err = 0; - sys_sem_signal(socksem); - return i; - } - } - sys_sem_signal(socksem); - return -1; -} - -int -lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen) -{ - struct lwip_socket *sock; - struct netconn *newconn; - struct ip_addr naddr; - u16_t port; - int newsock; - struct sockaddr_in sin; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s)); - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - newconn = netconn_accept(sock->conn); - - /* get the IP address and port of the remote host */ - netconn_peer(newconn, &naddr, &port); - - memset(&sin, 0, sizeof(sin)); - sin.sin_len = sizeof(sin); - sin.sin_family = AF_INET; - sin.sin_port = htons(port); - sin.sin_addr.s_addr = naddr.addr; - - if (*addrlen > sizeof(sin)) - *addrlen = sizeof(sin); - - memcpy(addr, &sin, *addrlen); - - newsock = alloc_socket(newconn); - if (newsock == -1) { - netconn_delete(newconn); - sock_set_errno(sock, ENOBUFS); - return -1; - } - newconn->callback = event_callback; - sock = get_socket(newsock); - - sys_sem_wait(socksem); - sock->rcvevent += -1 - newconn->socket; - newconn->socket = newsock; - sys_sem_signal(socksem); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock)); - ip_addr_debug_print(SOCKETS_DEBUG, &naddr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", port)); - - sock_set_errno(sock, 0); - return newsock; -} - -int -lwip_bind(int s, struct sockaddr *name, socklen_t namelen) -{ - struct lwip_socket *sock; - struct ip_addr local_addr; - u16_t local_port; - err_t err; - - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - local_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr; - local_port = ((struct sockaddr_in *)name)->sin_port; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s)); - ip_addr_debug_print(SOCKETS_DEBUG, &local_addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(local_port))); - - err = netconn_bind(sock->conn, &local_addr, ntohs(local_port)); - - if (err != ERR_OK) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err)); - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s)); - sock_set_errno(sock, 0); - return 0; -} - -int -lwip_close(int s) -{ - struct lwip_socket *sock; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s)); - if (!socksem) - socksem = sys_sem_new(1); - - /* We cannot allow multiple closes of the same socket. */ - sys_sem_wait(socksem); - - sock = get_socket(s); - if (!sock) { - sys_sem_signal(socksem); - set_errno(EBADF); - return -1; - } - - netconn_delete(sock->conn); - if (sock->lastdata) { - netbuf_delete(sock->lastdata); - } - sock->lastdata = NULL; - sock->lastoffset = 0; - sock->conn = NULL; - sys_sem_signal(socksem); - sock_set_errno(sock, 0); - return 0; -} - -int -lwip_connect(int s, struct sockaddr *name, socklen_t namelen) -{ - struct lwip_socket *sock; - err_t err; - - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - if (((struct sockaddr_in *)name)->sin_family == AF_UNSPEC) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s)); - err = netconn_disconnect(sock->conn); - } else { - struct ip_addr remote_addr; - u16_t remote_port; - - remote_addr.addr = ((struct sockaddr_in *)name)->sin_addr.s_addr; - remote_port = ((struct sockaddr_in *)name)->sin_port; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s)); - ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u)\n", ntohs(remote_port))); - - err = netconn_connect(sock->conn, &remote_addr, ntohs(remote_port)); - } - - if (err != ERR_OK) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err)); - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s)); - sock_set_errno(sock, 0); - return 0; -} - -int -lwip_listen(int s, int backlog) -{ - struct lwip_socket *sock; - err_t err; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog)); - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - err = netconn_listen(sock->conn); - - if (err != ERR_OK) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err)); - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - - sock_set_errno(sock, 0); - return 0; -} - -int -lwip_recvfrom(int s, void *mem, int len, unsigned int flags, - struct sockaddr *from, socklen_t *fromlen) -{ - struct lwip_socket *sock; - struct netbuf *buf; - u16_t buflen, copylen; - struct ip_addr *addr; - u16_t port; - - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %d, 0x%x, ..)\n", s, mem, len, flags)); - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - /* Check if there is data left from the last recv operation. */ - if (sock->lastdata) { - buf = sock->lastdata; - } else { - /* If this is non-blocking call, then check first */ - if (((flags & MSG_DONTWAIT) || (sock->flags & O_NONBLOCK)) - && !sock->rcvevent) - { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s)); - sock_set_errno(sock, EWOULDBLOCK); - return -1; - } - - /* No data was left from the previous operation, so we try to get - some from the network. */ - buf = netconn_recv(sock->conn); - - if (!buf) { - /* We should really do some error checking here. */ - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL!\n", s)); - sock_set_errno(sock, 0); - return 0; - } - } - - buflen = netbuf_len(buf); - - buflen -= sock->lastoffset; - - if (len > buflen) { - copylen = buflen; - } else { - copylen = len; - } - - /* copy the contents of the received buffer into - the supplied memory pointer mem */ - netbuf_copy_partial(buf, mem, copylen, sock->lastoffset); - - /* Check to see from where the data was. */ - if (from && fromlen) { - struct sockaddr_in sin; - - addr = netbuf_fromaddr(buf); - port = netbuf_fromport(buf); - - memset(&sin, 0, sizeof(sin)); - sin.sin_len = sizeof(sin); - sin.sin_family = AF_INET; - sin.sin_port = htons(port); - sin.sin_addr.s_addr = addr->addr; - - if (*fromlen > sizeof(sin)) - *fromlen = sizeof(sin); - - memcpy(from, &sin, *fromlen); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s)); - ip_addr_debug_print(SOCKETS_DEBUG, addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen)); - } else { -#if SOCKETS_DEBUG - addr = netbuf_fromaddr(buf); - port = netbuf_fromport(buf); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s)); - ip_addr_debug_print(SOCKETS_DEBUG, addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u len=%u\n", port, copylen)); -#endif - - } - - /* If this is a TCP socket, check if there is data left in the - buffer. If so, it should be saved in the sock structure for next - time around. */ - if (netconn_type(sock->conn) == NETCONN_TCP && buflen - copylen > 0) { - sock->lastdata = buf; - sock->lastoffset += copylen; - } else { - sock->lastdata = NULL; - sock->lastoffset = 0; - netbuf_delete(buf); - } - - - sock_set_errno(sock, 0); - return copylen; -} - -int -lwip_read(int s, void *mem, int len) -{ - return lwip_recvfrom(s, mem, len, 0, NULL, NULL); -} - -int -lwip_recv(int s, void *mem, int len, unsigned int flags) -{ - return lwip_recvfrom(s, mem, len, flags, NULL, NULL); -} - -int -lwip_send(int s, void *data, int size, unsigned int flags) -{ - struct lwip_socket *sock; - struct netbuf *buf; - err_t err; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%d, flags=0x%x)\n", s, data, size, flags)); - - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - switch (netconn_type(sock->conn)) { - case NETCONN_RAW: - case NETCONN_UDP: - case NETCONN_UDPLITE: - case NETCONN_UDPNOCHKSUM: - /* create a buffer */ - buf = netbuf_new(); - - if (!buf) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ENOBUFS\n", s)); - sock_set_errno(sock, ENOBUFS); - return -1; - } - - /* make the buffer point to the data that should - be sent */ - netbuf_ref(buf, data, size); - - /* send the data */ - err = netconn_send(sock->conn, buf); - - /* deallocated the buffer */ - netbuf_delete(buf); - break; - case NETCONN_TCP: - err = netconn_write(sock->conn, data, size, NETCONN_COPY); - break; - default: - err = ERR_ARG; - break; - } - if (err != ERR_OK) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d\n", s, err)); - sock_set_errno(sock, err_to_errno(err)); - return -1; - } - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) ok size=%d\n", s, size)); - sock_set_errno(sock, 0); - return size; -} - -int -lwip_sendto(int s, void *data, int size, unsigned int flags, - struct sockaddr *to, socklen_t tolen) -{ - struct lwip_socket *sock; - struct ip_addr remote_addr, addr; - u16_t remote_port, port; - int ret,connected; - - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - /* get the peer if currently connected */ - connected = (netconn_peer(sock->conn, &addr, &port) == ERR_OK); - - remote_addr.addr = ((struct sockaddr_in *)to)->sin_addr.s_addr; - remote_port = ((struct sockaddr_in *)to)->sin_port; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, size=%d, flags=0x%x to=", s, data, size, flags)); - ip_addr_debug_print(SOCKETS_DEBUG, &remote_addr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%u\n", ntohs(remote_port))); - - netconn_connect(sock->conn, &remote_addr, ntohs(remote_port)); - - ret = lwip_send(s, data, size, flags); - - /* reset the remote address and port number - of the connection */ - if (connected) - netconn_connect(sock->conn, &addr, port); - else - netconn_disconnect(sock->conn); - return ret; -} - -int -lwip_socket(int domain, int type, int protocol) -{ - struct netconn *conn; - int i; - - /* create a netconn */ - switch (type) { - case SOCK_RAW: - conn = netconn_new_with_proto_and_callback(NETCONN_RAW, protocol, event_callback); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); - break; - case SOCK_DGRAM: - conn = netconn_new_with_callback(NETCONN_UDP, event_callback); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); - break; - case SOCK_STREAM: - conn = netconn_new_with_callback(NETCONN_TCP, event_callback); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); - break; - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", domain, type, protocol)); - set_errno(EINVAL); - return -1; - } - - if (!conn) { - LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n")); - set_errno(ENOBUFS); - return -1; - } - - i = alloc_socket(conn); - - if (i == -1) { - netconn_delete(conn); - set_errno(ENOBUFS); - return -1; - } - conn->socket = i; - LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i)); - set_errno(0); - return i; -} - -int -lwip_write(int s, void *data, int size) -{ - return lwip_send(s, data, size, 0); -} - - -static int -lwip_selscan(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset) -{ - int i, nready = 0; - fd_set lreadset, lwriteset, lexceptset; - struct lwip_socket *p_sock; - - FD_ZERO(&lreadset); - FD_ZERO(&lwriteset); - FD_ZERO(&lexceptset); - - /* Go through each socket in each list to count number of sockets which - currently match */ - for(i = 0; i < maxfdp1; i++) - { - if (FD_ISSET(i, readset)) - { - /* See if netconn of this socket is ready for read */ - p_sock = get_socket(i); - if (p_sock && (p_sock->lastdata || p_sock->rcvevent)) - { - FD_SET(i, &lreadset); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i)); - nready++; - } - } - if (FD_ISSET(i, writeset)) - { - /* See if netconn of this socket is ready for write */ - p_sock = get_socket(i); - if (p_sock && p_sock->sendevent) - { - FD_SET(i, &lwriteset); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i)); - nready++; - } - } - } - *readset = lreadset; - *writeset = lwriteset; - FD_ZERO(exceptset); - - return nready; -} - - - -int -lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, - struct timeval *timeout) -{ - int i; - int nready; - fd_set lreadset, lwriteset, lexceptset; - u32_t msectimeout; - struct lwip_select_cb select_cb; - struct lwip_select_cb *p_selcb; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%ld tvusec=%ld)\n", maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset, timeout ? timeout->tv_sec : -1L, timeout ? timeout->tv_usec : -1L)); - - select_cb.next = 0; - select_cb.readset = readset; - select_cb.writeset = writeset; - select_cb.exceptset = exceptset; - select_cb.sem_signalled = 0; - - /* Protect ourselves searching through the list */ - if (!selectsem) - selectsem = sys_sem_new(1); - sys_sem_wait(selectsem); - - if (readset) - lreadset = *readset; - else - FD_ZERO(&lreadset); - if (writeset) - lwriteset = *writeset; - else - FD_ZERO(&lwriteset); - if (exceptset) - lexceptset = *exceptset; - else - FD_ZERO(&lexceptset); - - /* Go through each socket in each list to count number of sockets which - currently match */ - nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset); - - /* If we don't have any current events, then suspend if we are supposed to */ - if (!nready) - { - if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0) - { - sys_sem_signal(selectsem); - if (readset) - FD_ZERO(readset); - if (writeset) - FD_ZERO(writeset); - if (exceptset) - FD_ZERO(exceptset); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n")); - set_errno(0); - - return 0; - } - - /* add our semaphore to list */ - /* We don't actually need any dynamic memory. Our entry on the - * list is only valid while we are in this function, so it's ok - * to use local variables */ - - select_cb.sem = sys_sem_new(0); - /* Note that we are still protected */ - /* Put this select_cb on top of list */ - select_cb.next = select_cb_list; - select_cb_list = &select_cb; - - /* Now we can safely unprotect */ - sys_sem_signal(selectsem); - - /* Now just wait to be woken */ - if (timeout == 0) - /* Wait forever */ - msectimeout = 0; - else - msectimeout = ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000)); - - i = sys_sem_wait_timeout(select_cb.sem, msectimeout); - - /* Take us off the list */ - sys_sem_wait(selectsem); - if (select_cb_list == &select_cb) - select_cb_list = select_cb.next; - else - for (p_selcb = select_cb_list; p_selcb; p_selcb = p_selcb->next) - if (p_selcb->next == &select_cb) - { - p_selcb->next = select_cb.next; - break; - } - - sys_sem_signal(selectsem); - - sys_sem_free(select_cb.sem); - if (i == 0) /* Timeout */ - { - if (readset) - FD_ZERO(readset); - if (writeset) - FD_ZERO(writeset); - if (exceptset) - FD_ZERO(exceptset); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n")); - set_errno(0); - - return 0; - } - - if (readset) - lreadset = *readset; - else - FD_ZERO(&lreadset); - if (writeset) - lwriteset = *writeset; - else - FD_ZERO(&lwriteset); - if (exceptset) - lexceptset = *exceptset; - else - FD_ZERO(&lexceptset); - - /* See what's set */ - nready = lwip_selscan(maxfdp1, &lreadset, &lwriteset, &lexceptset); - } - else - sys_sem_signal(selectsem); - - if (readset) - *readset = lreadset; - if (writeset) - *writeset = lwriteset; - if (exceptset) - *exceptset = lexceptset; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready)); - set_errno(0); - - return nready; -} - - -static void -event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len) -{ - int s; - struct lwip_socket *sock; - struct lwip_select_cb *scb; - - /* Get socket */ - if (conn) - { - s = conn->socket; - if (s < 0) - { - /* Data comes in right away after an accept, even though - * the server task might not have created a new socket yet. - * Just count down (or up) if that's the case and we - * will use the data later. Note that only receive events - * can happen before the new socket is set up. */ - if (evt == NETCONN_EVT_RCVPLUS) - conn->socket--; - return; - } - - sock = get_socket(s); - if (!sock) - return; - } - else - return; - - if (!selectsem) - selectsem = sys_sem_new(1); - - sys_sem_wait(selectsem); - /* Set event as required */ - switch (evt) - { - case NETCONN_EVT_RCVPLUS: - sock->rcvevent++; - break; - case NETCONN_EVT_RCVMINUS: - sock->rcvevent--; - break; - case NETCONN_EVT_SENDPLUS: - sock->sendevent = 1; - break; - case NETCONN_EVT_SENDMINUS: - sock->sendevent = 0; - break; - } - sys_sem_signal(selectsem); - - /* Now decide if anyone is waiting for this socket */ - /* NOTE: This code is written this way to protect the select link list - but to avoid a deadlock situation by releasing socksem before - signalling for the select. This means we need to go through the list - multiple times ONLY IF a select was actually waiting. We go through - the list the number of waiting select calls + 1. This list is - expected to be small. */ - while (1) - { - sys_sem_wait(selectsem); - for (scb = select_cb_list; scb; scb = scb->next) - { - if (scb->sem_signalled == 0) - { - /* Test this select call for our socket */ - if (scb->readset && FD_ISSET(s, scb->readset)) - if (sock->rcvevent) - break; - if (scb->writeset && FD_ISSET(s, scb->writeset)) - if (sock->sendevent) - break; - } - } - if (scb) - { - scb->sem_signalled = 1; - sys_sem_signal(selectsem); - sys_sem_signal(scb->sem); - } else { - sys_sem_signal(selectsem); - break; - } - } - -} - - - - -int lwip_shutdown(int s, int how) -{ - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how)); - return lwip_close(s); /* XXX temporary hack until proper implementation */ -} - -int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen) -{ - struct lwip_socket *sock; - struct sockaddr_in sin; - struct ip_addr naddr; - - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - memset(&sin, 0, sizeof(sin)); - sin.sin_len = sizeof(sin); - sin.sin_family = AF_INET; - - /* get the IP address and port of the remote host */ - netconn_peer(sock->conn, &naddr, &sin.sin_port); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getpeername(%d, addr=", s)); - ip_addr_debug_print(SOCKETS_DEBUG, &naddr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port)); - - sin.sin_port = htons(sin.sin_port); - sin.sin_addr.s_addr = naddr.addr; - - if (*namelen > sizeof(sin)) - *namelen = sizeof(sin); - - memcpy(name, &sin, *namelen); - sock_set_errno(sock, 0); - return 0; -} - -int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen) -{ - struct lwip_socket *sock; - struct sockaddr_in sin; - struct ip_addr *naddr; - - sock = get_socket(s); - if (!sock) { - set_errno(EBADF); - return -1; - } - - memset(&sin, 0, sizeof(sin)); - sin.sin_len = sizeof(sin); - sin.sin_family = AF_INET; - - /* get the IP address and port of the remote host */ - netconn_addr(sock->conn, &naddr, &sin.sin_port); - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockname(%d, addr=", s)); - ip_addr_debug_print(SOCKETS_DEBUG, naddr); - LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%d)\n", sin.sin_port)); - - sin.sin_port = htons(sin.sin_port); - sin.sin_addr.s_addr = naddr->addr; - - if (*namelen > sizeof(sin)) - *namelen = sizeof(sin); - - memcpy(name, &sin, *namelen); - sock_set_errno(sock, 0); - return 0; -} - -int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen) -{ - int err = 0; - struct lwip_socket *sock = get_socket(s); - - if(!sock) { - set_errno(EBADF); - return -1; - } - - if( NULL == optval || NULL == optlen ) { - sock_set_errno( sock, EFAULT ); - return -1; - } - - /* Do length and type checks for the various options first, to keep it readable. */ - switch( level ) { - -/* Level: SOL_SOCKET */ - case SOL_SOCKET: - switch(optname) { - - case SO_ACCEPTCONN: - case SO_BROADCAST: - /* UNIMPL case SO_DEBUG: */ - /* UNIMPL case SO_DONTROUTE: */ - case SO_ERROR: - case SO_KEEPALIVE: - /* UNIMPL case SO_OOBINLINE: */ - /* UNIMPL case SO_RCVBUF: */ - /* UNIMPL case SO_SNDBUF: */ - /* UNIMPL case SO_RCVLOWAT: */ - /* UNIMPL case SO_SNDLOWAT: */ -#if SO_REUSE - case SO_REUSEADDR: - case SO_REUSEPORT: -#endif /* SO_REUSE */ - case SO_TYPE: - /* UNIMPL case SO_USELOOPBACK: */ - if( *optlen < sizeof(int) ) { - err = EINVAL; - } - break; - - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname)); - err = ENOPROTOOPT; - } /* switch */ - break; - -/* Level: IPPROTO_IP */ - case IPPROTO_IP: - switch(optname) { - /* UNIMPL case IP_HDRINCL: */ - /* UNIMPL case IP_RCVDSTADDR: */ - /* UNIMPL case IP_RCVIF: */ - case IP_TTL: - case IP_TOS: - if( *optlen < sizeof(int) ) { - err = EINVAL; - } - break; - - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname)); - err = ENOPROTOOPT; - } /* switch */ - break; - -/* Level: IPPROTO_TCP */ - case IPPROTO_TCP: - if( *optlen < sizeof(int) ) { - err = EINVAL; - break; - } - - /* If this is no TCP socket, ignore any options. */ - if ( sock->conn->type != NETCONN_TCP ) return 0; - - switch( optname ) { - case TCP_NODELAY: - case TCP_KEEPALIVE: - break; - - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname)); - err = ENOPROTOOPT; - } /* switch */ - break; - -/* UNDEFINED LEVEL */ - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname)); - err = ENOPROTOOPT; - } /* switch */ - - - if( 0 != err ) { - sock_set_errno(sock, err); - return -1; - } - - - - /* Now do the actual option processing */ - - switch(level) { - -/* Level: SOL_SOCKET */ - case SOL_SOCKET: - switch( optname ) { - - /* The option flags */ - case SO_ACCEPTCONN: - case SO_BROADCAST: - /* UNIMPL case SO_DEBUG: */ - /* UNIMPL case SO_DONTROUTE: */ - case SO_KEEPALIVE: - /* UNIMPL case SO_OOBINCLUDE: */ -#if SO_REUSE - case SO_REUSEADDR: - case SO_REUSEPORT: -#endif /* SO_REUSE */ - /*case SO_USELOOPBACK: UNIMPL */ - *(int*)optval = sock->conn->pcb.tcp->so_options & optname; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", s, optname, (*(int*)optval?"on":"off"))); - break; - - case SO_TYPE: - switch (sock->conn->type) { - case NETCONN_RAW: - *(int*)optval = SOCK_RAW; - break; - case NETCONN_TCP: - *(int*)optval = SOCK_STREAM; - break; - case NETCONN_UDP: - case NETCONN_UDPLITE: - case NETCONN_UDPNOCHKSUM: - *(int*)optval = SOCK_DGRAM; - break; - default: /* unrecognized socket type */ - *(int*)optval = sock->conn->type; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", s, *(int *)optval)); - } /* switch */ - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n", s, *(int *)optval)); - break; - - case SO_ERROR: - *(int *)optval = sock->err; - sock->err = 0; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n", s, *(int *)optval)); - break; - } /* switch */ - break; - -/* Level: IPPROTO_IP */ - case IPPROTO_IP: - switch( optname ) { - case IP_TTL: - *(int*)optval = sock->conn->pcb.tcp->ttl; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n", s, *(int *)optval)); - break; - case IP_TOS: - *(int*)optval = sock->conn->pcb.tcp->tos; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n", s, *(int *)optval)); - break; - } /* switch */ - break; - -/* Level: IPPROTO_TCP */ - case IPPROTO_TCP: - switch( optname ) { - case TCP_NODELAY: - *(int*)optval = (sock->conn->pcb.tcp->flags & TF_NODELAY); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", s, (*(int*)optval)?"on":"off") ); - break; - case TCP_KEEPALIVE: - *(int*)optval = (int)sock->conn->pcb.tcp->keepalive; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, TCP_KEEPALIVE) = %d\n", s, *(int *)optval)); - break; - } /* switch */ - break; - } - - - sock_set_errno(sock, err); - return err ? -1 : 0; -} - -int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen) -{ - struct lwip_socket *sock = get_socket(s); - int err = 0; - - if(!sock) { - set_errno(EBADF); - return -1; - } - - if( NULL == optval ) { - sock_set_errno( sock, EFAULT ); - return -1; - } - - - /* Do length and type checks for the various options first, to keep it readable. */ - switch( level ) { - -/* Level: SOL_SOCKET */ - case SOL_SOCKET: - switch(optname) { - - case SO_BROADCAST: - /* UNIMPL case SO_DEBUG: */ - /* UNIMPL case SO_DONTROUTE: */ - case SO_KEEPALIVE: - /* UNIMPL case SO_OOBINLINE: */ - /* UNIMPL case SO_RCVBUF: */ - /* UNIMPL case SO_SNDBUF: */ - /* UNIMPL case SO_RCVLOWAT: */ - /* UNIMPL case SO_SNDLOWAT: */ -#if SO_REUSE - case SO_REUSEADDR: - case SO_REUSEPORT: -#endif /* SO_REUSE */ - /* UNIMPL case SO_USELOOPBACK: */ - if( optlen < sizeof(int) ) { - err = EINVAL; - } - break; - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", s, optname)); - err = ENOPROTOOPT; - } /* switch */ - break; - -/* Level: IPPROTO_IP */ - case IPPROTO_IP: - switch(optname) { - /* UNIMPL case IP_HDRINCL: */ - /* UNIMPL case IP_RCVDSTADDR: */ - /* UNIMPL case IP_RCVIF: */ - case IP_TTL: - case IP_TOS: - if( optlen < sizeof(int) ) { - err = EINVAL; - } - break; - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", s, optname)); - err = ENOPROTOOPT; - } /* switch */ - break; - -/* Level: IPPROTO_TCP */ - case IPPROTO_TCP: - if( optlen < sizeof(int) ) { - err = EINVAL; - break; - } - - /* If this is no TCP socket, ignore any options. */ - if ( sock->conn->type != NETCONN_TCP ) return 0; - - switch( optname ) { - case TCP_NODELAY: - case TCP_KEEPALIVE: - break; - - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", s, optname)); - err = ENOPROTOOPT; - } /* switch */ - break; - -/* UNDEFINED LEVEL */ - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", s, level, optname)); - err = ENOPROTOOPT; - } /* switch */ - - - if( 0 != err ) { - sock_set_errno(sock, err); - return -1; - } - - - - /* Now do the actual option processing */ - - switch(level) { - -/* Level: SOL_SOCKET */ - case SOL_SOCKET: - switch(optname) { - - /* The option flags */ - case SO_BROADCAST: - /* UNIMPL case SO_DEBUG: */ - /* UNIMPL case SO_DONTROUTE: */ - case SO_KEEPALIVE: - /* UNIMPL case SO_OOBINCLUDE: */ -#if SO_REUSE - case SO_REUSEADDR: - case SO_REUSEPORT: -#endif /* SO_REUSE */ - /* UNIMPL case SO_USELOOPBACK: */ - if ( *(int*)optval ) { - sock->conn->pcb.tcp->so_options |= optname; - } else { - sock->conn->pcb.tcp->so_options &= ~optname; - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n", s, optname, (*(int*)optval?"on":"off"))); - break; - } /* switch */ - break; - -/* Level: IPPROTO_IP */ - case IPPROTO_IP: - switch( optname ) { - case IP_TTL: - sock->conn->pcb.tcp->ttl = (u8_t)(*(int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %u\n", s, sock->conn->pcb.tcp->ttl)); - break; - case IP_TOS: - sock->conn->pcb.tcp->tos = (u8_t)(*(int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %u\n", s, sock->conn->pcb.tcp->tos)); - break; - } /* switch */ - break; - -/* Level: IPPROTO_TCP */ - case IPPROTO_TCP: - switch( optname ) { - case TCP_NODELAY: - if ( *(int*)optval ) { - sock->conn->pcb.tcp->flags |= TF_NODELAY; - } else { - sock->conn->pcb.tcp->flags &= ~TF_NODELAY; - } - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n", s, (*(int *)optval)?"on":"off") ); - break; - case TCP_KEEPALIVE: - sock->conn->pcb.tcp->keepalive = (u32_t)(*(int*)optval); - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %lu\n", s, sock->conn->pcb.tcp->keepalive)); - break; - } /* switch */ - break; - } /* switch */ - - sock_set_errno(sock, err); - return err ? -1 : 0; -} - -int lwip_ioctl(int s, long cmd, void *argp) -{ - struct lwip_socket *sock = get_socket(s); - - if(!sock) { - set_errno(EBADF); - return -1; - } - - switch (cmd) { - case FIONREAD: - if (!argp) { - sock_set_errno(sock, EINVAL); - return -1; - } - - *((u16_t*)argp) = sock->conn->recv_avail; - - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %u\n", s, argp, *((u16_t*)argp))); - sock_set_errno(sock, 0); - return 0; - - case FIONBIO: - if (argp && *(u32_t*)argp) - sock->flags |= O_NONBLOCK; - else - sock->flags &= ~O_NONBLOCK; - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, !!(sock->flags & O_NONBLOCK))); - sock_set_errno(sock, 0); - return 0; - - default: - LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp)); - sock_set_errno(sock, ENOSYS); /* not yet implemented */ - return -1; - } -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/api/tcpip.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/api/tcpip.c deleted file mode 100644 index ce8a2ca5d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/api/tcpip.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/sys.h" - -#include "lwip/memp.h" -#include "lwip/pbuf.h" - -#include "lwip/ip.h" -#include "lwip/ip_frag.h" -#include "lwip/udp.h" -#include "lwip/tcp.h" - -#include "lwip/tcpip.h" - -static void (* tcpip_init_done)(void *arg) = NULL; -static void *tcpip_init_done_arg; -static sys_mbox_t mbox; - -#if LWIP_TCP -static int tcpip_tcp_timer_active = 0; - -static void -tcpip_tcp_timer(void *arg) -{ - (void)arg; - - /* call TCP timer handler */ - tcp_tmr(); - /* timer still needed? */ - if (tcp_active_pcbs || tcp_tw_pcbs) { - /* restart timer */ - sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); - } else { - /* disable timer */ - tcpip_tcp_timer_active = 0; - } -} - -#if !NO_SYS -void -tcp_timer_needed(void) -{ - /* timer is off but needed again? */ - if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) { - /* enable and start timer */ - tcpip_tcp_timer_active = 1; - sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); - } -} -#endif /* !NO_SYS */ -#endif /* LWIP_TCP */ - -#if IP_REASSEMBLY -static void -ip_timer(void *data) -{ - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip: ip_reass_tmr()\n")); - ip_reass_tmr(); - sys_timeout(1000, ip_timer, NULL); -} -#endif - -static void -tcpip_thread(void *arg) -{ - struct tcpip_msg *msg; - - (void)arg; - - ip_init(); -#if LWIP_UDP - udp_init(); -#endif -#if LWIP_TCP - tcp_init(); -#endif -#if IP_REASSEMBLY - sys_timeout(1000, ip_timer, NULL); -#endif - if (tcpip_init_done != NULL) { - tcpip_init_done(tcpip_init_done_arg); - } - - while (1) { /* MAIN Loop */ - sys_mbox_fetch(mbox, (void *)&msg); - switch (msg->type) { - case TCPIP_MSG_API: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg)); - api_msg_input(msg->msg.apimsg); - break; - case TCPIP_MSG_INPUT: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: IP packet %p\n", (void *)msg)); - ip_input(msg->msg.inp.p, msg->msg.inp.netif); - break; - case TCPIP_MSG_CALLBACK: - LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg)); - msg->msg.cb.f(msg->msg.cb.ctx); - break; - default: - break; - } - memp_free(MEMP_TCPIP_MSG, msg); - } -} - -err_t -tcpip_input(struct pbuf *p, struct netif *inp) -{ - struct tcpip_msg *msg; - - msg = memp_malloc(MEMP_TCPIP_MSG); - if (msg == NULL) { - pbuf_free(p); - return ERR_MEM; - } - - msg->type = TCPIP_MSG_INPUT; - msg->msg.inp.p = p; - msg->msg.inp.netif = inp; - sys_mbox_post(mbox, msg); - return ERR_OK; -} - -err_t -tcpip_callback(void (*f)(void *ctx), void *ctx) -{ - struct tcpip_msg *msg; - - msg = memp_malloc(MEMP_TCPIP_MSG); - if (msg == NULL) { - return ERR_MEM; - } - - msg->type = TCPIP_MSG_CALLBACK; - msg->msg.cb.f = f; - msg->msg.cb.ctx = ctx; - sys_mbox_post(mbox, msg); - return ERR_OK; -} - -void -tcpip_apimsg(struct api_msg *apimsg) -{ - struct tcpip_msg *msg; - msg = memp_malloc(MEMP_TCPIP_MSG); - if (msg == NULL) { - memp_free(MEMP_API_MSG, apimsg); - return; - } - msg->type = TCPIP_MSG_API; - msg->msg.apimsg = apimsg; - sys_mbox_post(mbox, msg); -} - -void -tcpip_init(void (* initfunc)(void *), void *arg) -{ - tcpip_init_done = initfunc; - tcpip_init_done_arg = arg; - mbox = sys_mbox_new(); - sys_thread_new(tcpip_thread, NULL, TCPIP_THREAD_PRIO); -} - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/dhcp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/dhcp.c deleted file mode 100644 index b688afa19..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/dhcp.c +++ /dev/null @@ -1,1455 +0,0 @@ -/** - * @file - * - * Dynamic Host Configuration Protocol client - */ - -/* - * - * Copyright (c) 2001-2004 Leon Woestenberg - * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is a contribution to the lwIP TCP/IP stack. - * The Swedish Institute of Computer Science and Adam Dunkels - * are specifically granted permission to redistribute this - * source code. - * - * Author: Leon Woestenberg - * - * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform - * with RFC 2131 and RFC 2132. - * - * TODO: - * - Proper parsing of DHCP messages exploiting file/sname field overloading. - * - Add JavaDoc style documentation (API, internals). - * - Support for interfaces other than Ethernet (SLIP, PPP, ...) - * - * Please coordinate changes and requests with Leon Woestenberg - * - * - * Integration with your code: - * - * In lwip/dhcp.h - * #define DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute) - * #define DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer) - * - * Then have your application call dhcp_coarse_tmr() and - * dhcp_fine_tmr() on the defined intervals. - * - * dhcp_start(struct netif *netif); - * starts a DHCP client instance which configures the interface by - * obtaining an IP address lease and maintaining it. - * - * Use dhcp_release(netif) to end the lease and use dhcp_stop(netif) - * to remove the DHCP client. - * - */ - -#include - -#include "lwip/stats.h" -#include "lwip/mem.h" -#include "lwip/udp.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/inet.h" -#include "netif/etharp.h" - -#include "lwip/sys.h" -#include "lwip/opt.h" -#include "lwip/dhcp.h" - -#if LWIP_DHCP /* don't build if not configured for use in lwipopt.h */ - -/** global transaction identifier, must be - * unique for each DHCP request. We simply increment, starting - * with this value (easy to match with a packet analyzer) */ -static u32_t xid = 0xABCD0000; - -/** DHCP client state machine functions */ -static void dhcp_handle_ack(struct netif *netif); -static void dhcp_handle_nak(struct netif *netif); -static void dhcp_handle_offer(struct netif *netif); - -static err_t dhcp_discover(struct netif *netif); -static err_t dhcp_select(struct netif *netif); -static void dhcp_check(struct netif *netif); -static void dhcp_bind(struct netif *netif); -static err_t dhcp_decline(struct netif *netif); -static err_t dhcp_rebind(struct netif *netif); -static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state); - -/** receive, unfold, parse and free incoming messages */ -static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port); -static err_t dhcp_unfold_reply(struct dhcp *dhcp); -static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type); -static u8_t dhcp_get_option_byte(u8_t *ptr); -static u16_t dhcp_get_option_short(u8_t *ptr); -static u32_t dhcp_get_option_long(u8_t *ptr); -static void dhcp_free_reply(struct dhcp *dhcp); - -/** set the DHCP timers */ -static void dhcp_timeout(struct netif *netif); -static void dhcp_t1_timeout(struct netif *netif); -static void dhcp_t2_timeout(struct netif *netif); - -/** build outgoing messages */ -/** create a DHCP request, fill in common headers */ -static err_t dhcp_create_request(struct netif *netif); -/** free a DHCP request */ -static void dhcp_delete_request(struct netif *netif); -/** add a DHCP option (type, then length in bytes) */ -static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len); -/** add option values */ -static void dhcp_option_byte(struct dhcp *dhcp, u8_t value); -static void dhcp_option_short(struct dhcp *dhcp, u16_t value); -static void dhcp_option_long(struct dhcp *dhcp, u32_t value); -/** always add the DHCP options trailer to end and pad */ -static void dhcp_option_trailer(struct dhcp *dhcp); - -/** - * Back-off the DHCP client (because of a received NAK response). - * - * Back-off the DHCP client because of a received NAK. Receiving a - * NAK means the client asked for something non-sensible, for - * example when it tries to renew a lease obtained on another network. - * - * We back-off and will end up restarting a fresh DHCP negotiation later. - * - * @param state pointer to DHCP state structure - */ -static void dhcp_handle_nak(struct netif *netif) { - struct dhcp *dhcp = netif->dhcp; - u16_t msecs = 10 * 1000; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n", - (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_handle_nak(): set request timeout %"U16_F" msecs\n", msecs)); - dhcp_set_state(dhcp, DHCP_BACKING_OFF); -} - -/** - * Checks if the offered IP address is already in use. - * - * It does so by sending an ARP request for the offered address and - * entering CHECKING state. If no ARP reply is received within a small - * interval, the address is assumed to be free for use by us. - */ -static void dhcp_check(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0], - (s16_t)netif->name[1])); - /* create an ARP query for the offered IP address, expecting that no host - responds, as the IP address should not be in use. */ - result = etharp_query(netif, &dhcp->offered_ip_addr, NULL); - if (result != ERR_OK) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_check: could not perform ARP query\n")); - } - dhcp->tries++; - msecs = 500; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs)); - dhcp_set_state(dhcp, DHCP_CHECKING); -} - -/** - * Remember the configuration offered by a DHCP server. - * - * @param state pointer to DHCP state structure - */ -static void dhcp_handle_offer(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - /* obtain the server address */ - u8_t *option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SERVER_ID); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n", - (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - if (option_ptr != NULL) - { - dhcp->server_ip_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2])); - LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n", dhcp->server_ip_addr.addr)); - /* remember offered address */ - ip_addr_set(&dhcp->offered_ip_addr, (struct ip_addr *)&dhcp->msg_in->yiaddr); - LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr)); - - dhcp_select(netif); - } -} - -/** - * Select a DHCP server offer out of all offers. - * - * Simply select the first offer received. - * - * @param netif the netif under DHCP control - * @return lwIP specific error (see error.h) - */ -static err_t dhcp_select(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result; - u32_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) - { - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_REQUEST); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, 576); - - /* MUST request the offered IP address */ - dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); - dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); - - dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); - dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); - - dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/); - dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK); - dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER); - dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST); - dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER); - - dhcp_option_trailer(dhcp); - /* shrink the pbuf to the actual content length */ - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - /* TODO: we really should bind to a specific local interface here - but we cannot specify an unconfigured netif as it is addressless */ - udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); - /* send broadcast to any DHCP server */ - udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); - udp_send(dhcp->pcb, dhcp->p_out); - /* reconnect to any (or to server here?!) */ - udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); - dhcp_delete_request(netif); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_select: REQUESTING\n")); - dhcp_set_state(dhcp, DHCP_REQUESTING); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_select: could not allocate DHCP request\n")); - } - dhcp->tries++; - msecs = dhcp->tries < 4 ? dhcp->tries * 1000 : 4 * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_select(): set request timeout %"U32_F" msecs\n", msecs)); - return result; -} - -/** - * The DHCP timer that checks for lease renewal/rebind timeouts. - * - */ -void dhcp_coarse_tmr() -{ - struct netif *netif = netif_list; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_coarse_tmr()\n")); - /* iterate through all network interfaces */ - while (netif != NULL) { - /* only act on DHCP configured interfaces */ - if (netif->dhcp != NULL) { - /* timer is active (non zero), and triggers (zeroes) now? */ - if (netif->dhcp->t2_timeout-- == 1) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n")); - /* this clients' rebind timeout triggered */ - dhcp_t2_timeout(netif); - /* timer is active (non zero), and triggers (zeroes) now */ - } else if (netif->dhcp->t1_timeout-- == 1) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n")); - /* this clients' renewal timeout triggered */ - dhcp_t1_timeout(netif); - } - } - /* proceed to next netif */ - netif = netif->next; - } -} - -/** - * DHCP transaction timeout handling - * - * A DHCP server is expected to respond within a short period of time. - * This timer checks whether an outstanding DHCP request is timed out. - * - */ -void dhcp_fine_tmr() -{ - struct netif *netif = netif_list; - /* loop through netif's */ - while (netif != NULL) { - /* only act on DHCP configured interfaces */ - if (netif->dhcp != NULL) { - /* timer is active (non zero), and is about to trigger now */ - if (netif->dhcp->request_timeout-- == 1) { - /* { netif->dhcp->request_timeout == 0 } */ - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_fine_tmr(): request timeout\n")); - /* this clients' request timeout triggered */ - dhcp_timeout(netif); - } - } - /* proceed to next network interface */ - netif = netif->next; - } -} - -/** - * A DHCP negotiation transaction, or ARP request, has timed out. - * - * The timer that was started with the DHCP or ARP request has - * timed out, indicating no response was received in time. - * - * @param netif the netif under DHCP control - * - */ -static void dhcp_timeout(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_timeout()\n")); - /* back-off period has passed, or server selection timed out */ - if ((dhcp->state == DHCP_BACKING_OFF) || (dhcp->state == DHCP_SELECTING)) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_timeout(): restarting discovery\n")); - dhcp_discover(netif); - /* receiving the requested lease timed out */ - } else if (dhcp->state == DHCP_REQUESTING) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n")); - if (dhcp->tries <= 5) { - dhcp_select(netif); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n")); - dhcp_release(netif); - dhcp_discover(netif); - } - /* received no ARP reply for the offered address (which is good) */ - } else if (dhcp->state == DHCP_CHECKING) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n")); - if (dhcp->tries <= 1) { - dhcp_check(netif); - /* no ARP replies on the offered address, - looks like the IP address is indeed free */ - } else { - /* bind the interface to the offered address */ - dhcp_bind(netif); - } - } - /* did not get response to renew request? */ - else if (dhcp->state == DHCP_RENEWING) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RENEWING, DHCP request timed out\n")); - /* just retry renewal */ - /* note that the rebind timer will eventually time-out if renew does not work */ - dhcp_renew(netif); - /* did not get response to rebind request? */ - } else if (dhcp->state == DHCP_REBINDING) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): REBINDING, DHCP request timed out\n")); - if (dhcp->tries <= 8) { - dhcp_rebind(netif); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_timeout(): RELEASING, DISCOVERING\n")); - dhcp_release(netif); - dhcp_discover(netif); - } - } -} - -/** - * The renewal period has timed out. - * - * @param netif the netif under DHCP control - */ -static void dhcp_t1_timeout(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_t1_timeout()\n")); - if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) { - /* just retry to renew - note that the rebind timer (t2) will - * eventually time-out if renew tries fail. */ - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t1_timeout(): must renew\n")); - dhcp_renew(netif); - } -} - -/** - * The rebind period has timed out. - * - */ -static void dhcp_t2_timeout(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout()\n")); - if ((dhcp->state == DHCP_REQUESTING) || (dhcp->state == DHCP_BOUND) || (dhcp->state == DHCP_RENEWING)) { - /* just retry to rebind */ - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_t2_timeout(): must rebind\n")); - dhcp_rebind(netif); - } -} - -/** - * - * @param netif the netif under DHCP control - */ -static void dhcp_handle_ack(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - u8_t *option_ptr; - /* clear options we might not get from the ACK */ - dhcp->offered_sn_mask.addr = 0; - dhcp->offered_gw_addr.addr = 0; - dhcp->offered_bc_addr.addr = 0; - - /* lease time given? */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_LEASE_TIME); - if (option_ptr != NULL) { - /* remember offered lease time */ - dhcp->offered_t0_lease = dhcp_get_option_long(option_ptr + 2); - } - /* renewal period given? */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T1); - if (option_ptr != NULL) { - /* remember given renewal period */ - dhcp->offered_t1_renew = dhcp_get_option_long(option_ptr + 2); - } else { - /* calculate safe periods for renewal */ - dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2; - } - - /* renewal period given? */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_T2); - if (option_ptr != NULL) { - /* remember given rebind period */ - dhcp->offered_t2_rebind = dhcp_get_option_long(option_ptr + 2); - } else { - /* calculate safe periods for rebinding */ - dhcp->offered_t2_rebind = dhcp->offered_t0_lease; - } - - /* (y)our internet address */ - ip_addr_set(&dhcp->offered_ip_addr, &dhcp->msg_in->yiaddr); - -/** - * Patch #1308 - * TODO: we must check if the file field is not overloaded by DHCP options! - */ -#if 0 - /* boot server address */ - ip_addr_set(&dhcp->offered_si_addr, &dhcp->msg_in->siaddr); - /* boot file name */ - if (dhcp->msg_in->file[0]) { - dhcp->boot_file_name = mem_malloc(strlen(dhcp->msg_in->file) + 1); - strcpy(dhcp->boot_file_name, dhcp->msg_in->file); - } -#endif - - /* subnet mask */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_SUBNET_MASK); - /* subnet mask given? */ - if (option_ptr != NULL) { - dhcp->offered_sn_mask.addr = htonl(dhcp_get_option_long(&option_ptr[2])); - } - - /* gateway router */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_ROUTER); - if (option_ptr != NULL) { - dhcp->offered_gw_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2])); - } - - /* broadcast address */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_BROADCAST); - if (option_ptr != NULL) { - dhcp->offered_bc_addr.addr = htonl(dhcp_get_option_long(&option_ptr[2])); - } - - /* DNS servers */ - option_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_DNS_SERVER); - if (option_ptr != NULL) { - u8_t n; - dhcp->dns_count = dhcp_get_option_byte(&option_ptr[1]); - /* limit to at most DHCP_MAX_DNS DNS servers */ - if (dhcp->dns_count > DHCP_MAX_DNS) dhcp->dns_count = DHCP_MAX_DNS; - for (n = 0; n < dhcp->dns_count; n++) - { - dhcp->offered_dns_addr[n].addr = htonl(dhcp_get_option_long(&option_ptr[2+(n<<2)])); - } - } -} - -/** - * Start DHCP negotiation for a network interface. - * - * If no DHCP client instance was attached to this interface, - * a new client is created first. If a DHCP client instance - * was already present, it restarts negotiation. - * - * @param netif The lwIP network interface - * @return lwIP error code - * - ERR_OK - No error - * - ERR_MEM - Out of memory - * - */ -err_t dhcp_start(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result = ERR_OK; - - LWIP_ASSERT("netif != NULL", netif != NULL); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - netif->flags &= ~NETIF_FLAG_DHCP; - - /* no DHCP client attached yet? */ - if (dhcp == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting new DHCP client\n")); - dhcp = mem_malloc(sizeof(struct dhcp)); - if (dhcp == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n")); - return ERR_MEM; - } - /* store this dhcp client in the netif */ - netif->dhcp = dhcp; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): allocated dhcp")); - /* already has DHCP client attached */ - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 3, ("dhcp_start(): restarting DHCP configuration\n")); - } - - /* clear data structure */ - memset(dhcp, 0, sizeof(struct dhcp)); - /* allocate UDP PCB */ - dhcp->pcb = udp_new(); - if (dhcp->pcb == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): could not obtain pcb\n")); - mem_free((void *)dhcp); - netif->dhcp = dhcp = NULL; - return ERR_MEM; - } - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n")); - /* (re)start the DHCP negotiation */ - result = dhcp_discover(netif); - if (result != ERR_OK) { - /* free resources allocated above */ - dhcp_stop(netif); - return ERR_MEM; - } - netif->flags |= NETIF_FLAG_DHCP; - return result; -} - -/** - * Inform a DHCP server of our manual configuration. - * - * This informs DHCP servers of our fixed IP address configuration - * by sending an INFORM message. It does not involve DHCP address - * configuration, it is just here to be nice to the network. - * - * @param netif The lwIP network interface - * - */ -void dhcp_inform(struct netif *netif) -{ - struct dhcp *dhcp; - err_t result = ERR_OK; - dhcp = mem_malloc(sizeof(struct dhcp)); - if (dhcp == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not allocate dhcp\n")); - return; - } - netif->dhcp = dhcp; - memset(dhcp, 0, sizeof(struct dhcp)); - - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): allocated dhcp\n")); - dhcp->pcb = udp_new(); - if (dhcp->pcb == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform(): could not obtain pcb")); - mem_free((void *)dhcp); - return; - } - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_inform(): created new udp pcb\n")); - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) { - - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_INFORM); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - /* TODO: use netif->mtu ?! */ - dhcp_option_short(dhcp, 576); - - dhcp_option_trailer(dhcp); - - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); - udp_connect(dhcp->pcb, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_inform: INFORMING\n")); - udp_send(dhcp->pcb, dhcp->p_out); - udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); - dhcp_delete_request(netif); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_inform: could not allocate DHCP request\n")); - } - - if (dhcp != NULL) - { - if (dhcp->pcb != NULL) udp_remove(dhcp->pcb); - dhcp->pcb = NULL; - mem_free((void *)dhcp); - netif->dhcp = NULL; - } -} - -#if DHCP_DOES_ARP_CHECK -/** - * Match an ARP reply with the offered IP address. - * - * @param addr The IP address we received a reply from - * - */ -void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr) -{ - LWIP_ASSERT("netif != NULL", netif != NULL); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_arp_reply()\n")); - /* is a DHCP client doing an ARP check? */ - if ((netif->dhcp != NULL) && (netif->dhcp->state == DHCP_CHECKING)) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n", addr->addr)); - /* did a host respond with the address we - were offered by the DHCP server? */ - if (ip_addr_cmp(addr, &netif->dhcp->offered_ip_addr)) { - /* we will not accept the offered address */ - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE | 1, ("dhcp_arp_reply(): arp reply matched with offered address, declining\n")); - dhcp_decline(netif); - } - } -} - -/** - * Decline an offered lease. - * - * Tell the DHCP server we do not accept the offered address. - * One reason to decline the lease is when we find out the address - * is already in use by another host (through ARP). - */ -static err_t dhcp_decline(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result = ERR_OK; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_decline()\n")); - dhcp_set_state(dhcp, DHCP_BACKING_OFF); - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) - { - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_DECLINE); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, 576); - - dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); - dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); - - dhcp_option_trailer(dhcp); - /* resize pbuf to reflect true size of options */ - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); - /* @todo: should we really connect here? we are performing sendto() */ - udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); - /* per section 4.4.4, broadcast DECLINE messages */ - udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); - dhcp_delete_request(netif); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_decline: BACKING OFF\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_decline: could not allocate DHCP request\n")); - } - dhcp->tries++; - msecs = 10*1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} -#endif - - -/** - * Start the DHCP process, discover a DHCP server. - * - */ -static err_t dhcp_discover(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result = ERR_OK; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_discover()\n")); - ip_addr_set(&dhcp->offered_ip_addr, IP_ADDR_ANY); - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) - { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: making request\n")); - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_DISCOVER); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, 576); - - dhcp_option(dhcp, DHCP_OPTION_PARAMETER_REQUEST_LIST, 4/*num options*/); - dhcp_option_byte(dhcp, DHCP_OPTION_SUBNET_MASK); - dhcp_option_byte(dhcp, DHCP_OPTION_ROUTER); - dhcp_option_byte(dhcp, DHCP_OPTION_BROADCAST); - dhcp_option_byte(dhcp, DHCP_OPTION_DNS_SERVER); - - dhcp_option_trailer(dhcp); - - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: realloc()ing\n")); - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - /* set receive callback function with netif as user data */ - udp_recv(dhcp->pcb, dhcp_recv, netif); - udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); - udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, DHCP_SERVER_PORT)\n")); - udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_discover: deleting()ing\n")); - dhcp_delete_request(netif); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover: SELECTING\n")); - dhcp_set_state(dhcp, DHCP_SELECTING); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_discover: could not allocate DHCP request\n")); - } - dhcp->tries++; - msecs = dhcp->tries < 4 ? (dhcp->tries + 1) * 1000 : 10 * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} - - -/** - * Bind the interface to the offered IP address. - * - * @param netif network interface to bind to the offered address - */ -static void dhcp_bind(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - struct ip_addr sn_mask, gw_addr; - LWIP_ASSERT("dhcp_bind: netif != NULL", netif != NULL); - LWIP_ASSERT("dhcp_bind: dhcp != NULL", dhcp != NULL); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void*)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); - - /* temporary DHCP lease? */ - if (dhcp->offered_t1_renew != 0xffffffffUL) { - /* set renewal period timer */ - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew)); - dhcp->t1_timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; - if (dhcp->t1_timeout == 0) dhcp->t1_timeout = 1; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew*1000)); - } - /* set renewal period timer */ - if (dhcp->offered_t2_rebind != 0xffffffffUL) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind)); - dhcp->t2_timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; - if (dhcp->t2_timeout == 0) dhcp->t2_timeout = 1; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind*1000)); - } - /* copy offered network mask */ - ip_addr_set(&sn_mask, &dhcp->offered_sn_mask); - - /* subnet mask not given? */ - /* TODO: this is not a valid check. what if the network mask is 0? */ - if (sn_mask.addr == 0) { - /* choose a safe subnet mask given the network class */ - u8_t first_octet = ip4_addr1(&sn_mask); - if (first_octet <= 127) sn_mask.addr = htonl(0xff000000); - else if (first_octet >= 192) sn_mask.addr = htonl(0xffffff00); - else sn_mask.addr = htonl(0xffff0000); - } - - ip_addr_set(&gw_addr, &dhcp->offered_gw_addr); - /* gateway address not given? */ - if (gw_addr.addr == 0) { - /* copy network address */ - gw_addr.addr = (dhcp->offered_ip_addr.addr & sn_mask.addr); - /* use first host address on network as gateway */ - gw_addr.addr |= htonl(0x00000001); - } - - LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F"\n", dhcp->offered_ip_addr.addr)); - netif_set_ipaddr(netif, &dhcp->offered_ip_addr); - LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): SN: 0x%08"X32_F"\n", sn_mask.addr)); - netif_set_netmask(netif, &sn_mask); - LWIP_DEBUGF(DHCP_DEBUG | DBG_STATE, ("dhcp_bind(): GW: 0x%08"X32_F"\n", gw_addr.addr)); - netif_set_gw(netif, &gw_addr); - /* bring the interface up */ - netif_set_up(netif); - /* netif is now bound to DHCP leased address */ - dhcp_set_state(dhcp, DHCP_BOUND); -} - -/** - * Renew an existing DHCP lease at the involved DHCP server. - * - * @param netif network interface which must renew its lease - */ -err_t dhcp_renew(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_renew()\n")); - dhcp_set_state(dhcp, DHCP_RENEWING); - - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) { - - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_REQUEST); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - /* TODO: use netif->mtu in some way */ - dhcp_option_short(dhcp, 576); - -#if 0 - dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); - dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); -#endif - -#if 0 - dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); - dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); -#endif - /* append DHCP message trailer */ - dhcp_option_trailer(dhcp); - - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); - udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT); - udp_send(dhcp->pcb, dhcp->p_out); - dhcp_delete_request(netif); - - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew: RENEWING\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_renew: could not allocate DHCP request\n")); - } - dhcp->tries++; - /* back-off on retries, but to a maximum of 20 seconds */ - msecs = dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} - -/** - * Rebind with a DHCP server for an existing DHCP lease. - * - * @param netif network interface which must rebind with a DHCP server - */ -static err_t dhcp_rebind(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind()\n")); - dhcp_set_state(dhcp, DHCP_REBINDING); - - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) - { - - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_REQUEST); - - dhcp_option(dhcp, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); - dhcp_option_short(dhcp, 576); - -#if 0 - dhcp_option(dhcp, DHCP_OPTION_REQUESTED_IP, 4); - dhcp_option_long(dhcp, ntohl(dhcp->offered_ip_addr.addr)); - - dhcp_option(dhcp, DHCP_OPTION_SERVER_ID, 4); - dhcp_option_long(dhcp, ntohl(dhcp->server_ip_addr.addr)); -#endif - - dhcp_option_trailer(dhcp); - - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - /* set remote IP association to any DHCP server */ - udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); - udp_connect(dhcp->pcb, IP_ADDR_ANY, DHCP_SERVER_PORT); - /* broadcast to server */ - udp_sendto(dhcp->pcb, dhcp->p_out, IP_ADDR_BROADCAST, DHCP_SERVER_PORT); - dhcp_delete_request(netif); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind: REBINDING\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_rebind: could not allocate DHCP request\n")); - } - dhcp->tries++; - msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs)); - return result; -} - -/** - * Release a DHCP lease. - * - * @param netif network interface which must release its lease - */ -err_t dhcp_release(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - err_t result; - u16_t msecs; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_release()\n")); - - /* idle DHCP client */ - dhcp_set_state(dhcp, DHCP_OFF); - /* clean old DHCP offer */ - dhcp->server_ip_addr.addr = 0; - dhcp->offered_ip_addr.addr = dhcp->offered_sn_mask.addr = 0; - dhcp->offered_gw_addr.addr = dhcp->offered_bc_addr.addr = 0; - dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0; - dhcp->dns_count = 0; - - /* create and initialize the DHCP message header */ - result = dhcp_create_request(netif); - if (result == ERR_OK) { - dhcp_option(dhcp, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); - dhcp_option_byte(dhcp, DHCP_RELEASE); - - dhcp_option_trailer(dhcp); - - pbuf_realloc(dhcp->p_out, sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + dhcp->options_out_len); - - udp_bind(dhcp->pcb, IP_ADDR_ANY, DHCP_CLIENT_PORT); - udp_connect(dhcp->pcb, &dhcp->server_ip_addr, DHCP_SERVER_PORT); - udp_send(dhcp->pcb, dhcp->p_out); - dhcp_delete_request(netif); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release: RELEASED, DHCP_OFF\n")); - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_release: could not allocate DHCP request\n")); - } - dhcp->tries++; - msecs = dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000; - dhcp->request_timeout = (msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | DBG_STATE, ("dhcp_release(): set request timeout %"U16_F" msecs\n", msecs)); - /* bring the interface down */ - netif_set_down(netif); - /* remove IP address from interface */ - netif_set_ipaddr(netif, IP_ADDR_ANY); - netif_set_gw(netif, IP_ADDR_ANY); - netif_set_netmask(netif, IP_ADDR_ANY); - - /* TODO: netif_down(netif); */ - return result; -} -/** - * Remove the DHCP client from the interface. - * - * @param netif The network interface to stop DHCP on - */ -void dhcp_stop(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - LWIP_ASSERT("dhcp_stop: netif != NULL", netif != NULL); - - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_stop()\n")); - /* netif is DHCP configured? */ - if (dhcp != NULL) - { - if (dhcp->pcb != NULL) - { - udp_remove(dhcp->pcb); - dhcp->pcb = NULL; - } - if (dhcp->p != NULL) - { - pbuf_free(dhcp->p); - dhcp->p = NULL; - } - /* free unfolded reply */ - dhcp_free_reply(dhcp); - mem_free((void *)dhcp); - netif->dhcp = NULL; - } -} - -/* - * Set the DHCP state of a DHCP client. - * - * If the state changed, reset the number of tries. - * - * TODO: we might also want to reset the timeout here? - */ -static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state) -{ - if (new_state != dhcp->state) - { - dhcp->state = new_state; - dhcp->tries = 0; - } -} - -/* - * Concatenate an option type and length field to the outgoing - * DHCP message. - * - */ -static void dhcp_option(struct dhcp *dhcp, u8_t option_type, u8_t option_len) -{ - LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = option_type; - dhcp->msg_out->options[dhcp->options_out_len++] = option_len; -} -/* - * Concatenate a single byte to the outgoing DHCP message. - * - */ -static void dhcp_option_byte(struct dhcp *dhcp, u8_t value) -{ - LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len < DHCP_OPTIONS_LEN", dhcp->options_out_len < DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = value; -} -static void dhcp_option_short(struct dhcp *dhcp, u16_t value) -{ - LWIP_ASSERT("dhcp_option_short: dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 2 <= DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff00U) >> 8; - dhcp->msg_out->options[dhcp->options_out_len++] = value & 0x00ffU; -} -static void dhcp_option_long(struct dhcp *dhcp, u32_t value) -{ - LWIP_ASSERT("dhcp_option_long: dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN", dhcp->options_out_len + 4 <= DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0xff000000UL) >> 24; - dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x00ff0000UL) >> 16; - dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x0000ff00UL) >> 8; - dhcp->msg_out->options[dhcp->options_out_len++] = (value & 0x000000ffUL); -} - -/** - * Extract the DHCP message and the DHCP options. - * - * Extract the DHCP message and the DHCP options, each into a contiguous - * piece of memory. As a DHCP message is variable sized by its options, - * and also allows overriding some fields for options, the easy approach - * is to first unfold the options into a conitguous piece of memory, and - * use that further on. - * - */ -static err_t dhcp_unfold_reply(struct dhcp *dhcp) -{ - struct pbuf *p = dhcp->p; - u8_t *ptr; - u16_t i; - u16_t j = 0; - LWIP_ASSERT("dhcp->p != NULL", dhcp->p != NULL); - /* free any left-overs from previous unfolds */ - dhcp_free_reply(dhcp); - /* options present? */ - if (dhcp->p->tot_len > (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN)) - { - dhcp->options_in_len = dhcp->p->tot_len - (sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN); - dhcp->options_in = mem_malloc(dhcp->options_in_len); - if (dhcp->options_in == NULL) - { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->options\n")); - return ERR_MEM; - } - } - dhcp->msg_in = mem_malloc(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN); - if (dhcp->msg_in == NULL) - { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_unfold_reply(): could not allocate dhcp->msg_in\n")); - mem_free((void *)dhcp->options_in); - dhcp->options_in = NULL; - return ERR_MEM; - } - - ptr = (u8_t *)dhcp->msg_in; - /* proceed through struct dhcp_msg */ - for (i = 0; i < sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN; i++) - { - *ptr++ = ((u8_t *)p->payload)[j++]; - /* reached end of pbuf? */ - if (j == p->len) - { - /* proceed to next pbuf in chain */ - p = p->next; - j = 0; - } - } - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes into dhcp->msg_in[]\n", i)); - if (dhcp->options_in != NULL) { - ptr = (u8_t *)dhcp->options_in; - /* proceed through options */ - for (i = 0; i < dhcp->options_in_len; i++) { - *ptr++ = ((u8_t *)p->payload)[j++]; - /* reached end of pbuf? */ - if (j == p->len) { - /* proceed to next pbuf in chain */ - p = p->next; - j = 0; - } - } - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("dhcp_unfold_reply(): copied %"U16_F" bytes to dhcp->options_in[]\n", i)); - } - return ERR_OK; -} - -/** - * Free the incoming DHCP message including contiguous copy of - * its DHCP options. - * - */ -static void dhcp_free_reply(struct dhcp *dhcp) -{ - if (dhcp->msg_in != NULL) { - mem_free((void *)dhcp->msg_in); - dhcp->msg_in = NULL; - } - if (dhcp->options_in) { - mem_free((void *)dhcp->options_in); - dhcp->options_in = NULL; - dhcp->options_in_len = 0; - } - LWIP_DEBUGF(DHCP_DEBUG, ("dhcp_free_reply(): free'd\n")); -} - - -/** - * If an incoming DHCP message is in response to us, then trigger the state machine - */ -static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *addr, u16_t port) -{ - struct netif *netif = (struct netif *)arg; - struct dhcp *dhcp = netif->dhcp; - struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload; - u8_t *options_ptr; - u8_t msg_type; - u8_t i; - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 3, ("dhcp_recv(pbuf = %p) from DHCP server %"U16_F".%"U16_F".%"U16_F".%"U16_F" port %"U16_F"\n", (void*)p, - (u16_t)(ntohl(addr->addr) >> 24 & 0xff), (u16_t)(ntohl(addr->addr) >> 16 & 0xff), - (u16_t)(ntohl(addr->addr) >> 8 & 0xff), (u16_t)(ntohl(addr->addr) & 0xff), port)); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len)); - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len)); - /* prevent warnings about unused arguments */ - (void)pcb; (void)addr; (void)port; - dhcp->p = p; - /* TODO: check packet length before reading them */ - if (reply_msg->op != DHCP_BOOTREPLY) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op)); - pbuf_free(p); - dhcp->p = NULL; - return; - } - /* iterate through hardware address and match against DHCP message */ - for (i = 0; i < netif->hwaddr_len; i++) { - if (netif->hwaddr[i] != reply_msg->chaddr[i]) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("netif->hwaddr[%"U16_F"]==%02"X16_F" != reply_msg->chaddr[%"U16_F"]==%02"X16_F"\n", - (u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i])); - pbuf_free(p); - dhcp->p = NULL; - return; - } - } - /* match transaction ID against what we expected */ - if (ntohl(reply_msg->xid) != dhcp->xid) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("transaction id mismatch\n")); - pbuf_free(p); - dhcp->p = NULL; - return; - } - /* option fields could be unfold? */ - if (dhcp_unfold_reply(dhcp) != ERR_OK) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("problem unfolding DHCP message - too short on memory?\n")); - pbuf_free(p); - dhcp->p = NULL; - return; - } - - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n")); - /* obtain pointer to DHCP message type */ - options_ptr = dhcp_get_option_ptr(dhcp, DHCP_OPTION_MESSAGE_TYPE); - if (options_ptr == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OPTION_MESSAGE_TYPE option not found\n")); - pbuf_free(p); - dhcp->p = NULL; - return; - } - - /* read DHCP message type */ - msg_type = dhcp_get_option_byte(options_ptr + 2); - /* message type is DHCP ACK? */ - if (msg_type == DHCP_ACK) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_ACK received\n")); - /* in requesting state? */ - if (dhcp->state == DHCP_REQUESTING) { - dhcp_handle_ack(netif); - dhcp->request_timeout = 0; -#if DHCP_DOES_ARP_CHECK - /* check if the acknowledged lease address is already in use */ - dhcp_check(netif); -#else - /* bind interface to the acknowledged lease address */ - dhcp_bind(netif); -#endif - } - /* already bound to the given lease address? */ - else if ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING)) { - dhcp->request_timeout = 0; - dhcp_bind(netif); - } - } - /* received a DHCP_NAK in appropriate state? */ - else if ((msg_type == DHCP_NAK) && - ((dhcp->state == DHCP_REBOOTING) || (dhcp->state == DHCP_REQUESTING) || - (dhcp->state == DHCP_REBINDING) || (dhcp->state == DHCP_RENEWING ))) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_NAK received\n")); - dhcp->request_timeout = 0; - dhcp_handle_nak(netif); - } - /* received a DHCP_OFFER in DHCP_SELECTING state? */ - else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_SELECTING)) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("DHCP_OFFER received in DHCP_SELECTING state\n")); - dhcp->request_timeout = 0; - /* remember offered lease */ - dhcp_handle_offer(netif); - } - pbuf_free(p); - dhcp->p = NULL; -} - - -static err_t dhcp_create_request(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - u16_t i; - LWIP_ASSERT("dhcp_create_request: dhcp->p_out == NULL", dhcp->p_out == NULL); - LWIP_ASSERT("dhcp_create_request: dhcp->msg_out == NULL", dhcp->msg_out == NULL); - dhcp->p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM); - if (dhcp->p_out == NULL) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("dhcp_create_request(): could not allocate pbuf\n")); - return ERR_MEM; - } - /* give unique transaction identifier to this request */ - dhcp->xid = xid++; - - dhcp->msg_out = (struct dhcp_msg *)dhcp->p_out->payload; - - dhcp->msg_out->op = DHCP_BOOTREQUEST; - /* TODO: make link layer independent */ - dhcp->msg_out->htype = DHCP_HTYPE_ETH; - /* TODO: make link layer independent */ - dhcp->msg_out->hlen = DHCP_HLEN_ETH; - dhcp->msg_out->hops = 0; - dhcp->msg_out->xid = htonl(dhcp->xid); - dhcp->msg_out->secs = 0; - dhcp->msg_out->flags = 0; - dhcp->msg_out->ciaddr.addr = netif->ip_addr.addr; - dhcp->msg_out->yiaddr.addr = 0; - dhcp->msg_out->siaddr.addr = 0; - dhcp->msg_out->giaddr.addr = 0; - for (i = 0; i < DHCP_CHADDR_LEN; i++) { - /* copy netif hardware address, pad with zeroes */ - dhcp->msg_out->chaddr[i] = (i < netif->hwaddr_len) ? netif->hwaddr[i] : 0/* pad byte*/; - } - for (i = 0; i < DHCP_SNAME_LEN; i++) dhcp->msg_out->sname[i] = 0; - for (i = 0; i < DHCP_FILE_LEN; i++) dhcp->msg_out->file[i] = 0; - dhcp->msg_out->cookie = htonl(0x63825363UL); - dhcp->options_out_len = 0; - /* fill options field with an incrementing array (for debugging purposes) */ - for (i = 0; i < DHCP_OPTIONS_LEN; i++) dhcp->msg_out->options[i] = i; - return ERR_OK; -} - -static void dhcp_delete_request(struct netif *netif) -{ - struct dhcp *dhcp = netif->dhcp; - LWIP_ASSERT("dhcp_free_msg: dhcp->p_out != NULL", dhcp->p_out != NULL); - LWIP_ASSERT("dhcp_free_msg: dhcp->msg_out != NULL", dhcp->msg_out != NULL); - pbuf_free(dhcp->p_out); - dhcp->p_out = NULL; - dhcp->msg_out = NULL; -} - -/** - * Add a DHCP message trailer - * - * Adds the END option to the DHCP message, and if - * necessary, up to three padding bytes. - */ - -static void dhcp_option_trailer(struct dhcp *dhcp) -{ - LWIP_ASSERT("dhcp_option_trailer: dhcp->msg_out != NULL\n", dhcp->msg_out != NULL); - LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN); - dhcp->msg_out->options[dhcp->options_out_len++] = DHCP_OPTION_END; - /* packet is too small, or not 4 byte aligned? */ - while ((dhcp->options_out_len < DHCP_MIN_OPTIONS_LEN) || (dhcp->options_out_len & 3)) { - /* LWIP_DEBUGF(DHCP_DEBUG,("dhcp_option_trailer:dhcp->options_out_len=%"U16_F", DHCP_OPTIONS_LEN=%"U16_F, dhcp->options_out_len, DHCP_OPTIONS_LEN)); */ - LWIP_ASSERT("dhcp_option_trailer: dhcp->options_out_len < DHCP_OPTIONS_LEN\n", dhcp->options_out_len < DHCP_OPTIONS_LEN); - /* add a fill/padding byte */ - dhcp->msg_out->options[dhcp->options_out_len++] = 0; - } -} - -/** - * Find the offset of a DHCP option inside the DHCP message. - * - * @param client DHCP client - * @param option_type - * - * @return a byte offset into the UDP message where the option was found, or - * zero if the given option was not found. - */ -static u8_t *dhcp_get_option_ptr(struct dhcp *dhcp, u8_t option_type) -{ - u8_t overload = DHCP_OVERLOAD_NONE; - - /* options available? */ - if ((dhcp->options_in != NULL) && (dhcp->options_in_len > 0)) { - /* start with options field */ - u8_t *options = (u8_t *)dhcp->options_in; - u16_t offset = 0; - /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */ - while ((offset < dhcp->options_in_len) && (options[offset] != DHCP_OPTION_END)) { - /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */ - /* are the sname and/or file field overloaded with options? */ - if (options[offset] == DHCP_OPTION_OVERLOAD) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 2, ("overloaded message detected\n")); - /* skip option type and length */ - offset += 2; - overload = options[offset++]; - } - /* requested option found */ - else if (options[offset] == option_type) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset %"U16_F" in options\n", offset)); - return &options[offset]; - /* skip option */ - } else { - LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", options[offset])); - /* skip option type */ - offset++; - /* skip option length, and then length bytes */ - offset += 1 + options[offset]; - } - } - /* is this an overloaded message? */ - if (overload != DHCP_OVERLOAD_NONE) { - u16_t field_len; - if (overload == DHCP_OVERLOAD_FILE) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded file field\n")); - options = (u8_t *)&dhcp->msg_in->file; - field_len = DHCP_FILE_LEN; - } else if (overload == DHCP_OVERLOAD_SNAME) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname field\n")); - options = (u8_t *)&dhcp->msg_in->sname; - field_len = DHCP_SNAME_LEN; - /* TODO: check if else if () is necessary */ - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE | 1, ("overloaded sname and file field\n")); - options = (u8_t *)&dhcp->msg_in->sname; - field_len = DHCP_FILE_LEN + DHCP_SNAME_LEN; - } - offset = 0; - - /* at least 1 byte to read and no end marker */ - while ((offset < field_len) && (options[offset] != DHCP_OPTION_END)) { - if (options[offset] == option_type) { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("option found at offset=%"U16_F"\n", offset)); - return &options[offset]; - /* skip option */ - } else { - LWIP_DEBUGF(DHCP_DEBUG | DBG_TRACE, ("skipping option %"U16_F"\n", options[offset])); - /* skip option type */ - offset++; - offset += 1 + options[offset]; - } - } - } - } - return 0; -} - -/** - * Return the byte of DHCP option data. - * - * @param client DHCP client. - * @param ptr pointer obtained by dhcp_get_option_ptr(). - * - * @return byte value at the given address. - */ -static u8_t dhcp_get_option_byte(u8_t *ptr) -{ - LWIP_DEBUGF(DHCP_DEBUG, ("option byte value=%"U16_F"\n", (u16_t)(*ptr))); - return *ptr; -} - -/** - * Return the 16-bit value of DHCP option data. - * - * @param client DHCP client. - * @param ptr pointer obtained by dhcp_get_option_ptr(). - * - * @return byte value at the given address. - */ -static u16_t dhcp_get_option_short(u8_t *ptr) -{ - u16_t value; - value = *ptr++ << 8; - value |= *ptr; - LWIP_DEBUGF(DHCP_DEBUG, ("option short value=%"U16_F"\n", value)); - return value; -} - -/** - * Return the 32-bit value of DHCP option data. - * - * @param client DHCP client. - * @param ptr pointer obtained by dhcp_get_option_ptr(). - * - * @return byte value at the given address. - */ -static u32_t dhcp_get_option_long(u8_t *ptr) -{ - u32_t value; - value = (u32_t)(*ptr++) << 24; - value |= (u32_t)(*ptr++) << 16; - value |= (u32_t)(*ptr++) << 8; - value |= (u32_t)(*ptr++); - LWIP_DEBUGF(DHCP_DEBUG, ("option long value=%"U32_F"\n", value)); - return value; -} - -#endif /* LWIP_DHCP */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/inet.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/inet.c deleted file mode 100644 index 556cbeb5f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/inet.c +++ /dev/null @@ -1,525 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - - -/* inet.c - * - * Functions common to all TCP/IP modules, such as the Internet checksum and the - * byte order functions. - * - */ - - -#include "lwip/opt.h" - -#include "lwip/arch.h" - -#include "lwip/def.h" -#include "lwip/inet.h" - -#include "lwip/sys.h" - -/* This is a reference implementation of the checksum algorithm, with the - * aim of being simple, correct and fully portable. Checksumming is the - * first thing you would want to optimize for your platform. You will - * need to port it to your architecture and in your sys_arch.h: - * - * #define LWIP_CHKSUM -*/ -#ifndef LWIP_CHKSUM -#define LWIP_CHKSUM lwip_standard_chksum - -/** - * lwip checksum - * - * @param dataptr points to start of data to be summed at any boundary - * @param len length of data to be summed - * @return host order (!) lwip checksum (non-inverted Internet sum) - * - * @note accumulator size limits summable lenght to 64k - * @note host endianess is irrelevant (p3 RFC1071) - */ -static u16_t -lwip_standard_chksum(void *dataptr, u16_t len) -{ - u32_t acc; - u16_t src; - u8_t *octetptr; - - acc = 0; - /* dataptr may be at odd or even addresses */ - octetptr = (u8_t*)dataptr; - while (len > 1) - { - /* declare first octet as most significant - thus assume network order, ignoring host order */ - src = (*octetptr) << 8; - octetptr++; - /* declare second octet as least significant */ - src |= (*octetptr); - octetptr++; - acc += src; - len -= 2; - } - if (len > 0) - { - /* accumulate remaining octet */ - src = (*octetptr) << 8; - acc += src; - } - /* add deferred carry bits */ - acc = (acc >> 16) + (acc & 0x0000ffffUL); - if ((acc & 0xffff0000) != 0) { - acc = (acc >> 16) + (acc & 0x0000ffffUL); - } - /* This maybe a little confusing: reorder sum using htons() - instead of ntohs() since it has a little less call overhead. - The caller must invert bits for Internet sum ! */ - return htons((u16_t)acc); -} - -#endif - -#if 0 -/* - * Curt McDowell - * Broadcom Corp. - * csm@broadcom.com - * - * IP checksum two bytes at a time with support for - * unaligned buffer. - * Works for len up to and including 0x20000. - * by Curt McDowell, Broadcom Corp. 12/08/2005 - */ - -static u16_t -lwip_standard_chksum2(void *dataptr, int len) -{ - u8_t *pb = dataptr; - u16_t *ps, t = 0; - u32_t sum = 0; - int odd = ((u32_t)pb & 1); - - /* Get aligned to u16_t */ - if (odd && len > 0) { - ((u8_t *)&t)[1] = *pb++; - len--; - } - - /* Add the bulk of the data */ - ps = (u16_t *)pb; - while (len > 1) { - sum += *ps++; - len -= 2; - } - - /* Consume left-over byte, if any */ - if (len > 0) - ((u8_t *)&t)[0] = *(u8_t *)ps;; - - /* Add end bytes */ - sum += t; - - /* Fold 32-bit sum to 16 bits */ - while (sum >> 16) - sum = (sum & 0xffff) + (sum >> 16); - - /* Swap if alignment was odd */ - if (odd) - sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8); - - return sum; -} - -/** - * An optimized checksum routine. Basically, it uses loop-unrolling on - * the checksum loop, treating the head and tail bytes specially, whereas - * the inner loop acts on 8 bytes at a time. - * - * @arg start of buffer to be checksummed. May be an odd byte address. - * @len number of bytes in the buffer to be checksummed. - * - * @todo First argument type conflicts with generic checksum routine. - * - * by Curt McDowell, Broadcom Corp. December 8th, 2005 - */ - -static u16_t -lwip_standard_chksum4(u8_t *pb, int len) -{ - u16_t *ps, t = 0; - u32_t *pl; - u32_t sum = 0, tmp; - /* starts at odd byte address? */ - int odd = ((u32_t)pb & 1); - - if (odd && len > 0) { - ((u8_t *)&t)[1] = *pb++; - len--; - } - - ps = (u16_t *)pb; - - if (((u32_t)ps & 3) && len > 1) { - sum += *ps++; - len -= 2; - } - - pl = (u32_t *)ps; - - while (len > 7) { - tmp = sum + *pl++; /* ping */ - if (tmp < sum) - tmp++; /* add back carry */ - - sum = tmp + *pl++; /* pong */ - if (sum < tmp) - sum++; /* add back carry */ - - len -= 8; - } - - /* make room in upper bits */ - sum = (sum >> 16) + (sum & 0xffff); - - ps = (u16_t *)pl; - - /* 16-bit aligned word remaining? */ - while (len > 1) { - sum += *ps++; - len -= 2; - } - - /* dangling tail byte remaining? */ - if (len > 0) /* include odd byte */ - ((u8_t *)&t)[0] = *(u8_t *)ps; - - sum += t; /* add end bytes */ - - while (sum >> 16) /* combine halves */ - sum = (sum >> 16) + (sum & 0xffff); - - if (odd) - sum = ((sum & 0xff) << 8) | ((sum & 0xff00) >> 8); - - return sum; -} -#endif - -/* inet_chksum_pseudo: - * - * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain. - */ - -u16_t -inet_chksum_pseudo(struct pbuf *p, - struct ip_addr *src, struct ip_addr *dest, - u8_t proto, u16_t proto_len) -{ - u32_t acc; - struct pbuf *q; - u8_t swapped; - - acc = 0; - swapped = 0; - /* iterate through all pbuf in chain */ - for(q = p; q != NULL; q = q->next) { - LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n", - (void *)q, (void *)q->next)); - acc += LWIP_CHKSUM(q->payload, q->len); - /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/ - while (acc >> 16) { - acc = (acc & 0xffffUL) + (acc >> 16); - } - if (q->len % 2 != 0) { - swapped = 1 - swapped; - acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8); - } - /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/ - } - - if (swapped) { - acc = ((acc & 0xff) << 8) | ((acc & 0xff00UL) >> 8); - } - acc += (src->addr & 0xffffUL); - acc += ((src->addr >> 16) & 0xffffUL); - acc += (dest->addr & 0xffffUL); - acc += ((dest->addr >> 16) & 0xffffUL); - acc += (u32_t)htons((u16_t)proto); - acc += (u32_t)htons(proto_len); - - while (acc >> 16) { - acc = (acc & 0xffffUL) + (acc >> 16); - } - LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc)); - return (u16_t)~(acc & 0xffffUL); -} - -/* inet_chksum: - * - * Calculates the Internet checksum over a portion of memory. Used primarely for IP - * and ICMP. - */ - -u16_t -inet_chksum(void *dataptr, u16_t len) -{ - u32_t acc; - - acc = LWIP_CHKSUM(dataptr, len); - while (acc >> 16) { - acc = (acc & 0xffff) + (acc >> 16); - } - return (u16_t)~(acc & 0xffff); -} - -u16_t -inet_chksum_pbuf(struct pbuf *p) -{ - u32_t acc; - struct pbuf *q; - u8_t swapped; - - acc = 0; - swapped = 0; - for(q = p; q != NULL; q = q->next) { - acc += LWIP_CHKSUM(q->payload, q->len); - while (acc >> 16) { - acc = (acc & 0xffffUL) + (acc >> 16); - } - if (q->len % 2 != 0) { - swapped = 1 - swapped; - acc = (acc & 0x00ffUL << 8) | (acc & 0xff00UL >> 8); - } - } - - if (swapped) { - acc = ((acc & 0x00ffUL) << 8) | ((acc & 0xff00UL) >> 8); - } - return (u16_t)~(acc & 0xffffUL); -} - -/* Here for now until needed in other places in lwIP */ -#ifndef isascii -#define in_range(c, lo, up) ((u8_t)c >= lo && (u8_t)c <= up) -#define isascii(c) in_range(c, 0x20, 0x7f) -#define isdigit(c) in_range(c, '0', '9') -#define isxdigit(c) (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F')) -#define islower(c) in_range(c, 'a', 'z') -#define isspace(c) (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v') -#endif - - - /* - * Ascii internet address interpretation routine. - * The value returned is in network order. - */ - - /* */ - /* inet_addr */ - u32_t inet_addr(const char *cp) - { - struct in_addr val; - - if (inet_aton(cp, &val)) { - return (val.s_addr); - } - return (INADDR_NONE); - } - - /* - * Check whether "cp" is a valid ascii representation - * of an Internet address and convert to a binary address. - * Returns 1 if the address is valid, 0 if not. - * This replaces inet_addr, the return value from which - * cannot distinguish between failure and a local broadcast address. - */ - /* */ - /* inet_aton */ - s8_t - inet_aton(const char *cp, struct in_addr *addr) - { - u32_t val; - s32_t base, n; - char c; - u32_t parts[4]; - u32_t* pp = parts; - - c = *cp; - for (;;) { - /* - * Collect number up to ``.''. - * Values are specified as for C: - * 0x=hex, 0=octal, isdigit=decimal. - */ - if (!isdigit(c)) - return (0); - val = 0; base = 10; - if (c == '0') { - c = *++cp; - if (c == 'x' || c == 'X') - base = 16, c = *++cp; - else - base = 8; - } - for (;;) { - if (isdigit(c)) { - val = (val * base) + (s16_t)(c - '0'); - c = *++cp; - } else if (base == 16 && isxdigit(c)) { - val = (val << 4) | - (s16_t)(c + 10 - (islower(c) ? 'a' : 'A')); - c = *++cp; - } else - break; - } - if (c == '.') { - /* - * Internet format: - * a.b.c.d - * a.b.c (with c treated as 16 bits) - * a.b (with b treated as 24 bits) - */ - if (pp >= parts + 3) - return (0); - *pp++ = val; - c = *++cp; - } else - break; - } - /* - * Check for trailing characters. - */ - if (c != '\0' && (!isascii(c) || !isspace(c))) - return (0); - /* - * Concoct the address according to - * the number of parts specified. - */ - n = pp - parts + 1; - switch (n) { - - case 0: - return (0); /* initial nondigit */ - - case 1: /* a -- 32 bits */ - break; - - case 2: /* a.b -- 8.24 bits */ - if (val > 0xffffff) - return (0); - val |= parts[0] << 24; - break; - - case 3: /* a.b.c -- 8.8.16 bits */ - if (val > 0xffff) - return (0); - val |= (parts[0] << 24) | (parts[1] << 16); - break; - - case 4: /* a.b.c.d -- 8.8.8.8 bits */ - if (val > 0xff) - return (0); - val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8); - break; - } - if (addr) - addr->s_addr = htonl(val); - return (1); - } - -/* Convert numeric IP address into decimal dotted ASCII representation. - * returns ptr to static buffer; not reentrant! - */ -char *inet_ntoa(struct in_addr addr) -{ - static char str[16]; - u32_t s_addr = addr.s_addr; - char inv[3]; - char *rp; - u8_t *ap; - u8_t rem; - u8_t n; - u8_t i; - - rp = str; - ap = (u8_t *)&s_addr; - for(n = 0; n < 4; n++) { - i = 0; - do { - rem = *ap % (u8_t)10; - *ap /= (u8_t)10; - inv[i++] = '0' + rem; - } while(*ap); - while(i--) - *rp++ = inv[i]; - *rp++ = '.'; - ap++; - } - *--rp = 0; - return str; -} - - -#ifndef BYTE_ORDER -#error BYTE_ORDER is not defined -#endif -#if BYTE_ORDER == LITTLE_ENDIAN - -u16_t -htons(u16_t n) -{ - return ((n & 0xff) << 8) | ((n & 0xff00) >> 8); -} - -u16_t -ntohs(u16_t n) -{ - return htons(n); -} - -u32_t -htonl(u32_t n) -{ - return ((n & 0xff) << 24) | - ((n & 0xff00) << 8) | - ((n & 0xff0000) >> 8) | - ((n & 0xff000000) >> 24); -} - -u32_t -ntohl(u32_t n) -{ - return htonl(n); -} - -#endif /* BYTE_ORDER == LITTLE_ENDIAN */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/inet6.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/inet6.c deleted file mode 100644 index f34e2902d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/inet6.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - - -/* inet6.c - * - * Functions common to all TCP/IP modules, such as the Internet checksum and the - * byte order functions. - * - */ - - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/inet.h" - - - -/* chksum: - * - * Sums up all 16 bit words in a memory portion. Also includes any odd byte. - * This function is used by the other checksum functions. - * - * For now, this is not optimized. Must be optimized for the particular processor - * arcitecture on which it is to run. Preferebly coded in assembler. - */ - -static u32_t -chksum(void *dataptr, u16_t len) -{ - u16_t *sdataptr = dataptr; - u32_t acc; - - - for(acc = 0; len > 1; len -= 2) { - acc += *sdataptr++; - } - - /* add up any odd byte */ - if (len == 1) { - acc += htons((u16_t)(*(u8_t *)dataptr) << 8); - } - - return acc; -} - -/* inet_chksum_pseudo: - * - * Calculates the pseudo Internet checksum used by TCP and UDP for a pbuf chain. - */ - -u16_t -inet_chksum_pseudo(struct pbuf *p, - struct ip_addr *src, struct ip_addr *dest, - u8_t proto, u32_t proto_len) -{ - u32_t acc; - struct pbuf *q; - u8_t swapped, i; - - acc = 0; - swapped = 0; - for(q = p; q != NULL; q = q->next) { - acc += chksum(q->payload, q->len); - while (acc >> 16) { - acc = (acc & 0xffff) + (acc >> 16); - } - if (q->len % 2 != 0) { - swapped = 1 - swapped; - acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); - } - } - - if (swapped) { - acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); - } - - for(i = 0; i < 8; i++) { - acc += ((u16_t *)src->addr)[i] & 0xffff; - acc += ((u16_t *)dest->addr)[i] & 0xffff; - while (acc >> 16) { - acc = (acc & 0xffff) + (acc >> 16); - } - } - acc += (u16_t)htons((u16_t)proto); - acc += ((u16_t *)&proto_len)[0] & 0xffff; - acc += ((u16_t *)&proto_len)[1] & 0xffff; - - while (acc >> 16) { - acc = (acc & 0xffff) + (acc >> 16); - } - return ~(acc & 0xffff); -} - -/* inet_chksum: - * - * Calculates the Internet checksum over a portion of memory. Used primarely for IP - * and ICMP. - */ - -u16_t -inet_chksum(void *dataptr, u16_t len) -{ - u32_t acc, sum; - - acc = chksum(dataptr, len); - sum = (acc & 0xffff) + (acc >> 16); - sum += (sum >> 16); - return ~(sum & 0xffff); -} - -u16_t -inet_chksum_pbuf(struct pbuf *p) -{ - u32_t acc; - struct pbuf *q; - u8_t swapped; - - acc = 0; - swapped = 0; - for(q = p; q != NULL; q = q->next) { - acc += chksum(q->payload, q->len); - while (acc >> 16) { - acc = (acc & 0xffff) + (acc >> 16); - } - if (q->len % 2 != 0) { - swapped = 1 - swapped; - acc = (acc & 0xff << 8) | (acc & 0xff00 >> 8); - } - } - - if (swapped) { - acc = ((acc & 0xff) << 8) | ((acc & 0xff00) >> 8); - } - return ~(acc & 0xffff); -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv4/icmp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv4/icmp.c deleted file mode 100644 index db820148b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv4/icmp.c +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* Some ICMP messages should be passed to the transport protocols. This - is not implemented. */ - -#include - -#include "lwip/opt.h" -#include "lwip/icmp.h" -#include "lwip/inet.h" -#include "lwip/ip.h" -#include "lwip/def.h" -#include "lwip/stats.h" -#include "lwip/snmp.h" - -void -icmp_input(struct pbuf *p, struct netif *inp) -{ - u8_t type; - u8_t code; - struct icmp_echo_hdr *iecho; - struct ip_hdr *iphdr; - struct ip_addr tmpaddr; - u16_t hlen; - - ICMP_STATS_INC(icmp.recv); - snmp_inc_icmpinmsgs(); - - - iphdr = p->payload; - hlen = IPH_HL(iphdr) * 4; - if (pbuf_header(p, -((s16_t)hlen)) || (p->tot_len < sizeof(u16_t)*2)) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len)); - pbuf_free(p); - ICMP_STATS_INC(icmp.lenerr); - snmp_inc_icmpinerrors(); - return; - } - - type = *((u8_t *)p->payload); - code = *(((u8_t *)p->payload)+1); - switch (type) { - case ICMP_ECHO: - /* broadcast or multicast destination address? */ - if (ip_addr_isbroadcast(&iphdr->dest, inp) || ip_addr_ismulticast(&iphdr->dest)) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast or broadcast pings\n")); - ICMP_STATS_INC(icmp.err); - pbuf_free(p); - return; - } - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n")); - if (p->tot_len < sizeof(struct icmp_echo_hdr)) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n")); - pbuf_free(p); - ICMP_STATS_INC(icmp.lenerr); - snmp_inc_icmpinerrors(); - - return; - } - iecho = p->payload; - if (inet_chksum_pbuf(p) != 0) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n")); - pbuf_free(p); - ICMP_STATS_INC(icmp.chkerr); - snmp_inc_icmpinerrors(); - return; - } - tmpaddr.addr = iphdr->src.addr; - iphdr->src.addr = iphdr->dest.addr; - iphdr->dest.addr = tmpaddr.addr; - ICMPH_TYPE_SET(iecho, ICMP_ER); - /* adjust the checksum */ - if (iecho->chksum >= htons(0xffff - (ICMP_ECHO << 8))) { - iecho->chksum += htons(ICMP_ECHO << 8) + 1; - } else { - iecho->chksum += htons(ICMP_ECHO << 8); - } - ICMP_STATS_INC(icmp.xmit); - /* increase number of messages attempted to send */ - snmp_inc_icmpoutmsgs(); - /* increase number of echo replies attempted to send */ - snmp_inc_icmpoutechoreps(); - - pbuf_header(p, hlen); - ip_output_if(p, &(iphdr->src), IP_HDRINCL, - IPH_TTL(iphdr), 0, IP_PROTO_ICMP, inp); - break; - default: - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", (s16_t)type, (s16_t)code)); - ICMP_STATS_INC(icmp.proterr); - ICMP_STATS_INC(icmp.drop); - } - pbuf_free(p); -} - -void -icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t) -{ - struct pbuf *q; - struct ip_hdr *iphdr; - struct icmp_dur_hdr *idur; - - q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM); - /* ICMP header + IP header + 8 bytes of data */ - - iphdr = p->payload; - - idur = q->payload; - ICMPH_TYPE_SET(idur, ICMP_DUR); - ICMPH_CODE_SET(idur, t); - - memcpy((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8); - - /* calculate checksum */ - idur->chksum = 0; - idur->chksum = inet_chksum(idur, q->len); - ICMP_STATS_INC(icmp.xmit); - /* increase number of messages attempted to send */ - snmp_inc_icmpoutmsgs(); - /* increase number of destination unreachable messages attempted to send */ - snmp_inc_icmpoutdestunreachs(); - - ip_output(q, NULL, &(iphdr->src), - ICMP_TTL, 0, IP_PROTO_ICMP); - pbuf_free(q); -} - -#if IP_FORWARD -void -icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t) -{ - struct pbuf *q; - struct ip_hdr *iphdr; - struct icmp_te_hdr *tehdr; - - q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM); - - iphdr = p->payload; - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from ")); - ip_addr_debug_print(ICMP_DEBUG, &(iphdr->src)); - LWIP_DEBUGF(ICMP_DEBUG, (" to ")); - ip_addr_debug_print(ICMP_DEBUG, &(iphdr->dest)); - LWIP_DEBUGF(ICMP_DEBUG, ("\n")); - - tehdr = q->payload; - ICMPH_TYPE_SET(tehdr, ICMP_TE); - ICMPH_CODE_SET(tehdr, t); - - /* copy fields from original packet */ - memcpy((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8); - - /* calculate checksum */ - tehdr->chksum = 0; - tehdr->chksum = inet_chksum(tehdr, q->len); - ICMP_STATS_INC(icmp.xmit); - /* increase number of messages attempted to send */ - snmp_inc_icmpoutmsgs(); - /* increase number of destination unreachable messages attempted to send */ - snmp_inc_icmpouttimeexcds(); - ip_output(q, NULL, &(iphdr->src), - ICMP_TTL, 0, IP_PROTO_ICMP); - pbuf_free(q); -} - -#endif /* IP_FORWARD */ - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv4/ip.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv4/ip.c deleted file mode 100644 index 4db68c8e8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv4/ip.c +++ /dev/null @@ -1,508 +0,0 @@ -/* @file - * - * This is the IP layer implementation for incoming and outgoing IP traffic. - * - * @see ip_frag.c - * - */ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/ip.h" -#include "lwip/ip_frag.h" -#include "lwip/inet.h" -#include "lwip/netif.h" -#include "lwip/icmp.h" -#include "lwip/raw.h" -#include "lwip/udp.h" -#include "lwip/tcp.h" - -#include "lwip/stats.h" - -#include "arch/perf.h" - -#include "lwip/snmp.h" -#if LWIP_DHCP -# include "lwip/dhcp.h" -#endif /* LWIP_DHCP */ - - -/** - * Initializes the IP layer. - */ - -void -ip_init(void) -{ - /* no initializations as of yet */ -} - -/** - * Finds the appropriate network interface for a given IP address. It - * searches the list of network interfaces linearly. A match is found - * if the masked IP address of the network interface equals the masked - * IP address given to the function. - */ - -struct netif * -ip_route(struct ip_addr *dest) -{ - struct netif *netif; - - /* iterate through netifs */ - for(netif = netif_list; netif != NULL; netif = netif->next) { - /* network mask matches? */ - if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) { - /* return netif on which to forward IP packet */ - return netif; - } - } - /* no matching netif found, use default netif */ - return netif_default; -} -#if IP_FORWARD - -/** - * Forwards an IP packet. It finds an appropriate route for the - * packet, decrements the TTL value of the packet, adjusts the - * checksum and outputs the packet on the appropriate interface. - */ - -static struct netif * -ip_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp) -{ - struct netif *netif; - - PERF_START; - /* Find network interface where to forward this IP packet to. */ - netif = ip_route((struct ip_addr *)&(iphdr->dest)); - if (netif == NULL) { - LWIP_DEBUGF(IP_DEBUG, ("ip_forward: no forwarding route for 0x%"X32_F" found\n", - iphdr->dest.addr)); - snmp_inc_ipnoroutes(); - return (struct netif *)NULL; - } - /* Do not forward packets onto the same network interface on which - * they arrived. */ - if (netif == inp) { - LWIP_DEBUGF(IP_DEBUG, ("ip_forward: not bouncing packets back on incoming interface.\n")); - snmp_inc_ipnoroutes(); - return (struct netif *)NULL; - } - - /* decrement TTL */ - IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1); - /* send ICMP if TTL == 0 */ - if (IPH_TTL(iphdr) == 0) { - /* Don't send ICMP messages in response to ICMP messages */ - if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) { - icmp_time_exceeded(p, ICMP_TE_TTL); - snmp_inc_icmpouttimeexcds(); - } - return (struct netif *)NULL; - } - - /* Incrementally update the IP checksum. */ - if (IPH_CHKSUM(iphdr) >= htons(0xffff - 0x100)) { - IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100) + 1); - } else { - IPH_CHKSUM_SET(iphdr, IPH_CHKSUM(iphdr) + htons(0x100)); - } - - LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to 0x%"X32_F"\n", - iphdr->dest.addr)); - - IP_STATS_INC(ip.fw); - IP_STATS_INC(ip.xmit); - snmp_inc_ipforwdatagrams(); - - PERF_STOP("ip_forward"); - /* transmit pbuf on chosen interface */ - netif->output(netif, p, (struct ip_addr *)&(iphdr->dest)); - return netif; -} -#endif /* IP_FORWARD */ - -/** - * This function is called by the network interface device driver when - * an IP packet is received. The function does the basic checks of the - * IP header such as packet size being at least larger than the header - * size etc. If the packet was not destined for us, the packet is - * forwarded (using ip_forward). The IP checksum is always checked. - * - * Finally, the packet is sent to the upper layer protocol input function. - * - * - * - */ - -err_t -ip_input(struct pbuf *p, struct netif *inp) { - struct ip_hdr *iphdr; - struct netif *netif; - u16_t iphdrlen; - - IP_STATS_INC(ip.recv); - snmp_inc_ipinreceives(); - - /* identify the IP header */ - iphdr = p->payload; - if (IPH_V(iphdr) != 4) { - LWIP_DEBUGF(IP_DEBUG | 1, ("IP packet dropped due to bad version number %"U16_F"\n", IPH_V(iphdr))); - ip_debug_print(p); - pbuf_free(p); - IP_STATS_INC(ip.err); - IP_STATS_INC(ip.drop); - snmp_inc_ipunknownprotos(); - return ERR_OK; - } - /* obtain IP header length in number of 32-bit words */ - iphdrlen = IPH_HL(iphdr); - /* calculate IP header length in bytes */ - iphdrlen *= 4; - - /* header length exceeds first pbuf length? */ - if (iphdrlen > p->len) { - LWIP_DEBUGF(IP_DEBUG | 2, ("IP header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet droppped.\n", - iphdrlen, p->len)); - /* free (drop) packet pbufs */ - pbuf_free(p); - IP_STATS_INC(ip.lenerr); - IP_STATS_INC(ip.drop); - snmp_inc_ipindiscards(); - return ERR_OK; - } - - /* verify checksum */ -#if CHECKSUM_CHECK_IP - if (inet_chksum(iphdr, iphdrlen) != 0) { - - LWIP_DEBUGF(IP_DEBUG | 2, ("Checksum (0x%"X16_F") failed, IP packet dropped.\n", inet_chksum(iphdr, iphdrlen))); - ip_debug_print(p); - pbuf_free(p); - IP_STATS_INC(ip.chkerr); - IP_STATS_INC(ip.drop); - snmp_inc_ipindiscards(); - return ERR_OK; - } -#endif - - /* Trim pbuf. This should have been done at the netif layer, - * but we'll do it anyway just to be sure that its done. */ - pbuf_realloc(p, ntohs(IPH_LEN(iphdr))); - - /* match packet against an interface, i.e. is this packet for us? */ - for (netif = netif_list; netif != NULL; netif = netif->next) { - - LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%"X32_F" netif->ip_addr 0x%"X32_F" (0x%"X32_F", 0x%"X32_F", 0x%"X32_F")\n", - iphdr->dest.addr, netif->ip_addr.addr, - iphdr->dest.addr & netif->netmask.addr, - netif->ip_addr.addr & netif->netmask.addr, - iphdr->dest.addr & ~(netif->netmask.addr))); - - /* interface is up and configured? */ - if ((netif_is_up(netif)) && (!ip_addr_isany(&(netif->ip_addr)))) - { - /* unicast to this interface address? */ - if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr)) || - /* or broadcast on this interface network address? */ - ip_addr_isbroadcast(&(iphdr->dest), netif)) { - LWIP_DEBUGF(IP_DEBUG, ("ip_input: packet accepted on interface %c%c\n", - netif->name[0], netif->name[1])); - /* break out of for loop */ - break; - } - } - } -#if LWIP_DHCP - /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed - * using link layer addressing (such as Ethernet MAC) so we must not filter on IP. - * According to RFC 1542 section 3.1.1, referred by RFC 2131). - */ - if (netif == NULL) { - /* remote port is DHCP server? */ - if (IPH_PROTO(iphdr) == IP_PROTO_UDP) { - LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: UDP packet to DHCP client port %"U16_F"\n", - ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest))); - if (ntohs(((struct udp_hdr *)((u8_t *)iphdr + iphdrlen))->dest) == DHCP_CLIENT_PORT) { - LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: DHCP packet accepted.\n")); - netif = inp; - } - } - } -#endif /* LWIP_DHCP */ - /* packet not for us? */ - if (netif == NULL) { - /* packet not for us, route or discard */ - LWIP_DEBUGF(IP_DEBUG | DBG_TRACE | 1, ("ip_input: packet not for us.\n")); -#if IP_FORWARD - /* non-broadcast packet? */ - if (!ip_addr_isbroadcast(&(iphdr->dest), inp)) { - /* try to forward IP packet on (other) interfaces */ - ip_forward(p, iphdr, inp); - } - else -#endif /* IP_FORWARD */ - { - snmp_inc_ipindiscards(); - } - pbuf_free(p); - return ERR_OK; - } - /* packet consists of multiple fragments? */ - if ((IPH_OFFSET(iphdr) & htons(IP_OFFMASK | IP_MF)) != 0) { -#if IP_REASSEMBLY /* packet fragment reassembly code present? */ - LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip_reass()\n", - ntohs(IPH_ID(iphdr)), p->tot_len, ntohs(IPH_LEN(iphdr)), !!(IPH_OFFSET(iphdr) & htons(IP_MF)), (ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)*8)); - /* reassemble the packet*/ - p = ip_reass(p); - /* packet not fully reassembled yet? */ - if (p == NULL) { - return ERR_OK; - } - iphdr = p->payload; -#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */ - pbuf_free(p); - LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since it was fragmented (0x%"X16_F") (while IP_REASSEMBLY == 0).\n", - ntohs(IPH_OFFSET(iphdr)))); - IP_STATS_INC(ip.opterr); - IP_STATS_INC(ip.drop); - snmp_inc_ipunknownprotos(); - return ERR_OK; -#endif /* IP_REASSEMBLY */ - } - -#if IP_OPTIONS == 0 /* no support for IP options in the IP header? */ - if (iphdrlen > IP_HLEN) { - LWIP_DEBUGF(IP_DEBUG | 2, ("IP packet dropped since there were IP options (while IP_OPTIONS == 0).\n")); - pbuf_free(p); - IP_STATS_INC(ip.opterr); - IP_STATS_INC(ip.drop); - snmp_inc_ipunknownprotos(); - return ERR_OK; - } -#endif /* IP_OPTIONS == 0 */ - - /* send to upper layers */ - LWIP_DEBUGF(IP_DEBUG, ("ip_input: \n")); - ip_debug_print(p); - LWIP_DEBUGF(IP_DEBUG, ("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len)); - -#if LWIP_RAW - /* raw input did not eat the packet? */ - if (raw_input(p, inp) == 0) { -#endif /* LWIP_RAW */ - - switch (IPH_PROTO(iphdr)) { -#if LWIP_UDP - case IP_PROTO_UDP: - case IP_PROTO_UDPLITE: - snmp_inc_ipindelivers(); - udp_input(p, inp); - break; -#endif /* LWIP_UDP */ -#if LWIP_TCP - case IP_PROTO_TCP: - snmp_inc_ipindelivers(); - tcp_input(p, inp); - break; -#endif /* LWIP_TCP */ - case IP_PROTO_ICMP: - snmp_inc_ipindelivers(); - icmp_input(p, inp); - break; - default: - /* send ICMP destination protocol unreachable unless is was a broadcast */ - if (!ip_addr_isbroadcast(&(iphdr->dest), inp) && - !ip_addr_ismulticast(&(iphdr->dest))) { - p->payload = iphdr; - icmp_dest_unreach(p, ICMP_DUR_PROTO); - } - pbuf_free(p); - - LWIP_DEBUGF(IP_DEBUG | 2, ("Unsupported transport protocol %"U16_F"\n", IPH_PROTO(iphdr))); - - IP_STATS_INC(ip.proterr); - IP_STATS_INC(ip.drop); - snmp_inc_ipunknownprotos(); - } -#if LWIP_RAW - } /* LWIP_RAW */ -#endif - return ERR_OK; -} - -/** - * Sends an IP packet on a network interface. This function constructs - * the IP header and calculates the IP header checksum. If the source - * IP address is NULL, the IP address of the outgoing network - * interface is filled in as source address. - */ - -err_t -ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t tos, - u8_t proto, struct netif *netif) -{ - struct ip_hdr *iphdr; - u16_t ip_id = 0; - - snmp_inc_ipoutrequests(); - - if (dest != IP_HDRINCL) { - if (pbuf_header(p, IP_HLEN)) { - LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: not enough room for IP header in pbuf\n")); - - IP_STATS_INC(ip.err); - snmp_inc_ipoutdiscards(); - return ERR_BUF; - } - - iphdr = p->payload; - - IPH_TTL_SET(iphdr, ttl); - IPH_PROTO_SET(iphdr, proto); - - ip_addr_set(&(iphdr->dest), dest); - - IPH_VHLTOS_SET(iphdr, 4, IP_HLEN / 4, tos); - IPH_LEN_SET(iphdr, htons(p->tot_len)); - IPH_OFFSET_SET(iphdr, htons(IP_DF)); - IPH_ID_SET(iphdr, htons(ip_id)); - ++ip_id; - - if (ip_addr_isany(src)) { - ip_addr_set(&(iphdr->src), &(netif->ip_addr)); - } else { - ip_addr_set(&(iphdr->src), src); - } - - IPH_CHKSUM_SET(iphdr, 0); -#if CHECKSUM_GEN_IP - IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); -#endif - } else { - iphdr = p->payload; - dest = &(iphdr->dest); - } - -#if IP_FRAG - /* don't fragment if interface has mtu set to 0 [loopif] */ - if (netif->mtu && (p->tot_len > netif->mtu)) - return ip_frag(p,netif,dest); -#endif - - IP_STATS_INC(ip.xmit); - - LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], netif->num)); - ip_debug_print(p); - - LWIP_DEBUGF(IP_DEBUG, ("netif->output()")); - - return netif->output(netif, p, dest); -} - -/** - * Simple interface to ip_output_if. It finds the outgoing network - * interface and calls upon ip_output_if to do the actual work. - */ - -err_t -ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t tos, u8_t proto) -{ - struct netif *netif; - - if ((netif = ip_route(dest)) == NULL) { - LWIP_DEBUGF(IP_DEBUG | 2, ("ip_output: No route to 0x%"X32_F"\n", dest->addr)); - - IP_STATS_INC(ip.rterr); - snmp_inc_ipoutdiscards(); - return ERR_RTE; - } - - return ip_output_if(p, src, dest, ttl, tos, proto, netif); -} - -#if IP_DEBUG -void -ip_debug_print(struct pbuf *p) -{ - struct ip_hdr *iphdr = p->payload; - u8_t *payload; - - payload = (u8_t *)iphdr + IP_HLEN; - - LWIP_DEBUGF(IP_DEBUG, ("IP header:\n")); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |%2"S16_F" | 0x%02"X16_F" | %5"U16_F" | (v, hl, tos, len)\n", - IPH_V(iphdr), - IPH_HL(iphdr), - IPH_TOS(iphdr), - ntohs(IPH_LEN(iphdr)))); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %5"U16_F" |%"U16_F"%"U16_F"%"U16_F"| %4"U16_F" | (id, flags, offset)\n", - ntohs(IPH_ID(iphdr)), - ntohs(IPH_OFFSET(iphdr)) >> 15 & 1, - ntohs(IPH_OFFSET(iphdr)) >> 14 & 1, - ntohs(IPH_OFFSET(iphdr)) >> 13 & 1, - ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK)); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | 0x%04"X16_F" | (ttl, proto, chksum)\n", - IPH_TTL(iphdr), - IPH_PROTO(iphdr), - ntohs(IPH_CHKSUM(iphdr)))); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (src)\n", - ip4_addr1(&iphdr->src), - ip4_addr2(&iphdr->src), - ip4_addr3(&iphdr->src), - ip4_addr4(&iphdr->src))); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (dest)\n", - ip4_addr1(&iphdr->dest), - ip4_addr2(&iphdr->dest), - ip4_addr3(&iphdr->dest), - ip4_addr4(&iphdr->dest))); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); -} -#endif /* IP_DEBUG */ - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv4/ip_addr.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv4/ip_addr.c deleted file mode 100644 index 2af526e9f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv4/ip_addr.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/ip_addr.h" -#include "lwip/inet.h" -#include "lwip/netif.h" - -/* used by IP_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */ -const struct ip_addr ip_addr_any = { 0x00000000UL }; -const struct ip_addr ip_addr_broadcast = { 0xffffffffUL }; - -/* Determine if an address is a broadcast address on a network interface - * - * @param addr address to be checked - * @param netif the network interface against which the address is checked - * @return returns non-zero if the address is a broadcast address - * - */ - -u8_t ip_addr_isbroadcast(struct ip_addr *addr, struct netif *netif) -{ - /* all ones (broadcast) or all zeroes (old skool broadcast) */ - if ((addr->addr == ip_addr_broadcast.addr) || - (addr->addr == ip_addr_any.addr)) - return 1; - /* no broadcast support on this network interface? */ - else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) - /* the given address cannot be a broadcast address - * nor can we check against any broadcast addresses */ - return 0; - /* address matches network interface address exactly? => no broadcast */ - else if (addr->addr == netif->ip_addr.addr) - return 0; - /* on the same (sub) network... */ - else if (ip_addr_netcmp(addr, &(netif->ip_addr), &(netif->netmask)) - /* ...and host identifier bits are all ones? =>... */ - && ((addr->addr & ~netif->netmask.addr) == - (ip_addr_broadcast.addr & ~netif->netmask.addr))) - /* => network broadcast address */ - return 1; - else - return 0; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv4/ip_frag.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv4/ip_frag.c deleted file mode 100644 index 5a57138ce..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv4/ip_frag.c +++ /dev/null @@ -1,366 +0,0 @@ -/* @file - * - * This is the IP packet segmentation and reassembly implementation. - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Jani Monoses - * original reassembly code by Adam Dunkels - * - */ - -#include - -#include "lwip/opt.h" -/* #include "lwip/sys.h" */ -#include "lwip/ip.h" -#include "lwip/ip_frag.h" -#include "lwip/netif.h" -#include "lwip/stats.h" - - -/* - * Copy len bytes from offset in pbuf to buffer - * - * helper used by both ip_reass and ip_frag - */ -static struct pbuf * -copy_from_pbuf(struct pbuf *p, u16_t * offset, - u8_t * buffer, u16_t len) -{ - u16_t l; - - p->payload = (u8_t *)p->payload + *offset; - p->len -= *offset; - while (len) { - l = len < p->len ? len : p->len; - memcpy(buffer, p->payload, l); - buffer += l; - len -= l; - if (len) - p = p->next; - else - *offset = l; - } - return p; -} - -#define IP_REASS_BUFSIZE 5760 -#define IP_REASS_MAXAGE 30 -#define IP_REASS_TMO 1000 - -static u8_t ip_reassbuf[IP_HLEN + IP_REASS_BUFSIZE]; -static u8_t ip_reassbitmap[IP_REASS_BUFSIZE / (8 * 8) + 1]; -static const u8_t bitmap_bits[8] = { 0xff, 0x7f, 0x3f, 0x1f, - 0x0f, 0x07, 0x03, 0x01 -}; -static u16_t ip_reasslen; -static u8_t ip_reassflags; -#define IP_REASS_FLAG_LASTFRAG 0x01 - -static u8_t ip_reasstmr; - -/** - * Reassembly timer base function - * for both NO_SYS == 0 and 1 (!). - * - * Should be called every 1000 msec. - */ -void -ip_reass_tmr(void) -{ - if (ip_reasstmr > 0) { - ip_reasstmr--; - } -} - -/** - * Reassembles incoming IP fragments into an IP datagram. - * - * @param p points to a pbuf chain of the fragment - * @return NULL if reassembly is incomplete, ? otherwise - */ -struct pbuf * -ip_reass(struct pbuf *p) -{ - struct pbuf *q; - struct ip_hdr *fraghdr, *iphdr; - u16_t offset, len; - u16_t i; - - IPFRAG_STATS_INC(ip_frag.recv); - - iphdr = (struct ip_hdr *) ip_reassbuf; - fraghdr = (struct ip_hdr *) p->payload; - /* If ip_reasstmr is zero, no packet is present in the buffer, so we - write the IP header of the fragment into the reassembly - buffer. The timer is updated with the maximum age. */ - if (ip_reasstmr == 0) { - LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: new packet\n")); - memcpy(iphdr, fraghdr, IP_HLEN); - ip_reasstmr = IP_REASS_MAXAGE; - ip_reassflags = 0; - /* Clear the bitmap. */ - memset(ip_reassbitmap, 0, sizeof(ip_reassbitmap)); - } - - /* Check if the incoming fragment matches the one currently present - in the reasembly buffer. If so, we proceed with copying the - fragment into the buffer. */ - if (ip_addr_cmp(&iphdr->src, &fraghdr->src) && - ip_addr_cmp(&iphdr->dest, &fraghdr->dest) && - IPH_ID(iphdr) == IPH_ID(fraghdr)) { - LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: matching previous fragment ID=%"X16_F"\n", - ntohs(IPH_ID(fraghdr)))); - IPFRAG_STATS_INC(ip_frag.cachehit); - /* Find out the offset in the reassembly buffer where we should - copy the fragment. */ - len = ntohs(IPH_LEN(fraghdr)) - IPH_HL(fraghdr) * 4; - offset = (ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) * 8; - - /* If the offset or the offset + fragment length overflows the - reassembly buffer, we discard the entire packet. */ - if (offset > IP_REASS_BUFSIZE || offset + len > IP_REASS_BUFSIZE) { - LWIP_DEBUGF(IP_REASS_DEBUG, - ("ip_reass: fragment outside of buffer (%"S16_F":%"S16_F"/%"S16_F").\n", offset, - offset + len, IP_REASS_BUFSIZE)); - ip_reasstmr = 0; - goto nullreturn; - } - - /* Copy the fragment into the reassembly buffer, at the right - offset. */ - LWIP_DEBUGF(IP_REASS_DEBUG, - ("ip_reass: copying with offset %"S16_F" into %"S16_F":%"S16_F"\n", offset, - IP_HLEN + offset, IP_HLEN + offset + len)); - i = IPH_HL(fraghdr) * 4; - copy_from_pbuf(p, &i, &ip_reassbuf[IP_HLEN + offset], len); - - /* Update the bitmap. */ - if (offset / (8 * 8) == (offset + len) / (8 * 8)) { - LWIP_DEBUGF(IP_REASS_DEBUG, - ("ip_reass: updating single byte in bitmap.\n")); - /* If the two endpoints are in the same byte, we only update that byte. */ - LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)", - offset / (8 * 8) < sizeof(ip_reassbitmap)); - ip_reassbitmap[offset / (8 * 8)] |= - bitmap_bits[(offset / 8) & 7] & - ~bitmap_bits[((offset + len) / 8) & 7]; - } else { - /* If the two endpoints are in different bytes, we update the - bytes in the endpoints and fill the stuff inbetween with - 0xff. */ - LWIP_ASSERT("offset / (8 * 8) < sizeof(ip_reassbitmap)", - offset / (8 * 8) < sizeof(ip_reassbitmap)); - ip_reassbitmap[offset / (8 * 8)] |= bitmap_bits[(offset / 8) & 7]; - LWIP_DEBUGF(IP_REASS_DEBUG, - ("ip_reass: updating many bytes in bitmap (%"S16_F":%"S16_F").\n", - 1 + offset / (8 * 8), (offset + len) / (8 * 8))); - for (i = 1 + offset / (8 * 8); i < (offset + len) / (8 * 8); ++i) { - ip_reassbitmap[i] = 0xff; - } - LWIP_ASSERT("(offset + len) / (8 * 8) < sizeof(ip_reassbitmap)", - (offset + len) / (8 * 8) < sizeof(ip_reassbitmap)); - ip_reassbitmap[(offset + len) / (8 * 8)] |= - ~bitmap_bits[((offset + len) / 8) & 7]; - } - - /* If this fragment has the More Fragments flag set to zero, we - know that this is the last fragment, so we can calculate the - size of the entire packet. We also set the - IP_REASS_FLAG_LASTFRAG flag to indicate that we have received - the final fragment. */ - - if ((ntohs(IPH_OFFSET(fraghdr)) & IP_MF) == 0) { - ip_reassflags |= IP_REASS_FLAG_LASTFRAG; - ip_reasslen = offset + len; - LWIP_DEBUGF(IP_REASS_DEBUG, - ("ip_reass: last fragment seen, total len %"S16_F"\n", - ip_reasslen)); - } - - /* Finally, we check if we have a full packet in the buffer. We do - this by checking if we have the last fragment and if all bits - in the bitmap are set. */ - if (ip_reassflags & IP_REASS_FLAG_LASTFRAG) { - /* Check all bytes up to and including all but the last byte in - the bitmap. */ - LWIP_ASSERT("ip_reasslen / (8 * 8) - 1 < sizeof(ip_reassbitmap)", - ip_reasslen / (8 * 8) - 1 < sizeof(ip_reassbitmap)); - for (i = 0; i < ip_reasslen / (8 * 8) - 1; ++i) { - if (ip_reassbitmap[i] != 0xff) { - LWIP_DEBUGF(IP_REASS_DEBUG, - ("ip_reass: last fragment seen, bitmap %"S16_F"/%"S16_F" failed (%"X16_F")\n", - i, ip_reasslen / (8 * 8) - 1, ip_reassbitmap[i])); - goto nullreturn; - } - } - /* Check the last byte in the bitmap. It should contain just the - right amount of bits. */ - LWIP_ASSERT("ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap)", - ip_reasslen / (8 * 8) < sizeof(ip_reassbitmap)); - if (ip_reassbitmap[ip_reasslen / (8 * 8)] != - (u8_t) ~ bitmap_bits[ip_reasslen / 8 & 7]) { - LWIP_DEBUGF(IP_REASS_DEBUG, - ("ip_reass: last fragment seen, bitmap %"S16_F" didn't contain %"X16_F" (%"X16_F")\n", - ip_reasslen / (8 * 8), ~bitmap_bits[ip_reasslen / 8 & 7], - ip_reassbitmap[ip_reasslen / (8 * 8)])); - goto nullreturn; - } - - /* Pretend to be a "normal" (i.e., not fragmented) IP packet - from now on. */ - ip_reasslen += IP_HLEN; - - IPH_LEN_SET(iphdr, htons(ip_reasslen)); - IPH_OFFSET_SET(iphdr, 0); - IPH_CHKSUM_SET(iphdr, 0); - IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); - - /* If we have come this far, we have a full packet in the - buffer, so we allocate a pbuf and copy the packet into it. We - also reset the timer. */ - ip_reasstmr = 0; - pbuf_free(p); - p = pbuf_alloc(PBUF_LINK, ip_reasslen, PBUF_POOL); - if (p != NULL) { - i = 0; - for (q = p; q != NULL; q = q->next) { - /* Copy enough bytes to fill this pbuf in the chain. The - available data in the pbuf is given by the q->len variable. */ - LWIP_DEBUGF(IP_REASS_DEBUG, - ("ip_reass: memcpy from %p (%"S16_F") to %p, %"S16_F" bytes\n", - (void *)&ip_reassbuf[i], i, q->payload, - q->len > ip_reasslen - i ? ip_reasslen - i : q->len)); - memcpy(q->payload, &ip_reassbuf[i], - q->len > ip_reasslen - i ? ip_reasslen - i : q->len); - i += q->len; - } - IPFRAG_STATS_INC(ip_frag.fw); - } else { - IPFRAG_STATS_INC(ip_frag.memerr); - } - LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass: p %p\n", (void*)p)); - return p; - } - } - -nullreturn: - IPFRAG_STATS_INC(ip_frag.drop); - pbuf_free(p); - return NULL; -} - -#define MAX_MTU 1500 -static u8_t buf[MEM_ALIGN_SIZE(MAX_MTU)]; - -/** - * Fragment an IP datagram if too large for the netif. - * - * Chop the datagram in MTU sized chunks and send them in order - * by using a fixed size static memory buffer (PBUF_ROM) - */ -err_t -ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest) -{ - struct pbuf *rambuf; - struct pbuf *header; - struct ip_hdr *iphdr; - u16_t nfb = 0; - u16_t left, cop; - u16_t mtu = netif->mtu; - u16_t ofo, omf; - u16_t last; - u16_t poff = IP_HLEN; - u16_t tmp; - - /* Get a RAM based MTU sized pbuf */ - rambuf = pbuf_alloc(PBUF_LINK, 0, PBUF_REF); - if (rambuf == NULL) { - return ERR_MEM; - } - rambuf->tot_len = rambuf->len = mtu; - rambuf->payload = MEM_ALIGN((void *)buf); - - /* Copy the IP header in it */ - iphdr = rambuf->payload; - memcpy(iphdr, p->payload, IP_HLEN); - - /* Save original offset */ - tmp = ntohs(IPH_OFFSET(iphdr)); - ofo = tmp & IP_OFFMASK; - omf = tmp & IP_MF; - - left = p->tot_len - IP_HLEN; - - while (left) { - last = (left <= mtu - IP_HLEN); - - /* Set new offset and MF flag */ - ofo += nfb; - tmp = omf | (IP_OFFMASK & (ofo)); - if (!last) - tmp = tmp | IP_MF; - IPH_OFFSET_SET(iphdr, htons(tmp)); - - /* Fill this fragment */ - nfb = (mtu - IP_HLEN) / 8; - cop = last ? left : nfb * 8; - - p = copy_from_pbuf(p, &poff, (u8_t *) iphdr + IP_HLEN, cop); - - /* Correct header */ - IPH_LEN_SET(iphdr, htons(cop + IP_HLEN)); - IPH_CHKSUM_SET(iphdr, 0); - IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); - - if (last) - pbuf_realloc(rambuf, left + IP_HLEN); - /* This part is ugly: we alloc a RAM based pbuf for - * the link level header for each chunk and then - * free it.A PBUF_ROM style pbuf for which pbuf_header - * worked would make things simpler. - */ - header = pbuf_alloc(PBUF_LINK, 0, PBUF_RAM); - if (header != NULL) { - pbuf_chain(header, rambuf); - netif->output(netif, header, dest); - IPFRAG_STATS_INC(ip_frag.xmit); - pbuf_free(header); - } else { - pbuf_free(rambuf); - return ERR_MEM; - } - left -= cop; - } - pbuf_free(rambuf); - return ERR_OK; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv6/README b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv6/README deleted file mode 100644 index 362000486..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv6/README +++ /dev/null @@ -1 +0,0 @@ -IPv6 support in lwIP is very experimental. diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv6/icmp6.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv6/icmp6.c deleted file mode 100644 index 10b6903c4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv6/icmp6.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* Some ICMP messages should be passed to the transport protocols. This - is not implemented. */ - -#include "lwip/opt.h" - -#include "lwip/icmp.h" -#include "lwip/inet.h" -#include "lwip/ip.h" -#include "lwip/def.h" - -#include "lwip/stats.h" - - -void -icmp_input(struct pbuf *p, struct netif *inp) -{ - u8_t type; - struct icmp_echo_hdr *iecho; - struct ip_hdr *iphdr; - struct ip_addr tmpaddr; - -#ifdef ICMP_STATS - ++lwip_stats.icmp.recv; -#endif /* ICMP_STATS */ - - /* TODO: check length before accessing payload! */ - - type = ((u8_t *)p->payload)[0]; - - switch (type) { - case ICMP6_ECHO: - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n")); - - if (p->tot_len < sizeof(struct icmp_echo_hdr)) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n")); - - pbuf_free(p); -#ifdef ICMP_STATS - ++lwip_stats.icmp.lenerr; -#endif /* ICMP_STATS */ - - return; - } - iecho = p->payload; - iphdr = (struct ip_hdr *)((u8_t *)p->payload - IP_HLEN); - if (inet_chksum_pbuf(p) != 0) { - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len))); - -#ifdef ICMP_STATS - ++lwip_stats.icmp.chkerr; -#endif /* ICMP_STATS */ - /* return;*/ - } - LWIP_DEBUGF(ICMP_DEBUG, ("icmp: p->len %"S16_F" p->tot_len %"S16_F"\n", p->len, p->tot_len)); - ip_addr_set(&tmpaddr, &(iphdr->src)); - ip_addr_set(&(iphdr->src), &(iphdr->dest)); - ip_addr_set(&(iphdr->dest), &tmpaddr); - iecho->type = ICMP6_ER; - /* adjust the checksum */ - if (iecho->chksum >= htons(0xffff - (ICMP6_ECHO << 8))) { - iecho->chksum += htons(ICMP6_ECHO << 8) + 1; - } else { - iecho->chksum += htons(ICMP6_ECHO << 8); - } - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo (%"X16_F")\n", inet_chksum_pseudo(p, &(iphdr->src), &(iphdr->dest), IP_PROTO_ICMP, p->tot_len))); -#ifdef ICMP_STATS - ++lwip_stats.icmp.xmit; -#endif /* ICMP_STATS */ - - /* LWIP_DEBUGF("icmp: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/ - ip_output_if (p, &(iphdr->src), IP_HDRINCL, - iphdr->hoplim, IP_PROTO_ICMP, inp); - break; - default: - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" not supported.\n", (s16_t)type)); -#ifdef ICMP_STATS - ++lwip_stats.icmp.proterr; - ++lwip_stats.icmp.drop; -#endif /* ICMP_STATS */ - } - - pbuf_free(p); -} - -void -icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t) -{ - struct pbuf *q; - struct ip_hdr *iphdr; - struct icmp_dur_hdr *idur; - - q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM); - /* ICMP header + IP header + 8 bytes of data */ - - iphdr = p->payload; - - idur = q->payload; - idur->type = (u8_t)ICMP6_DUR; - idur->icode = (u8_t)t; - - memcpy((u8_t *)q->payload + 8, p->payload, IP_HLEN + 8); - - /* calculate checksum */ - idur->chksum = 0; - idur->chksum = inet_chksum(idur, q->len); -#ifdef ICMP_STATS - ++lwip_stats.icmp.xmit; -#endif /* ICMP_STATS */ - - ip_output(q, NULL, - (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP); - pbuf_free(q); -} - -void -icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t) -{ - struct pbuf *q; - struct ip_hdr *iphdr; - struct icmp_te_hdr *tehdr; - - LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded\n")); - - q = pbuf_alloc(PBUF_IP, 8 + IP_HLEN + 8, PBUF_RAM); - - iphdr = p->payload; - - tehdr = q->payload; - tehdr->type = (u8_t)ICMP6_TE; - tehdr->icode = (u8_t)t; - - /* copy fields from original packet */ - memcpy((u8_t *)q->payload + 8, (u8_t *)p->payload, IP_HLEN + 8); - - /* calculate checksum */ - tehdr->chksum = 0; - tehdr->chksum = inet_chksum(tehdr, q->len); -#ifdef ICMP_STATS - ++lwip_stats.icmp.xmit; -#endif /* ICMP_STATS */ - ip_output(q, NULL, - (struct ip_addr *)&(iphdr->src), ICMP_TTL, IP_PROTO_ICMP); - pbuf_free(q); -} - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv6/ip6.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv6/ip6.c deleted file mode 100644 index 03037c818..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv6/ip6.c +++ /dev/null @@ -1,386 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - - - -/* ip.c - * - * This is the code for the IP layer for IPv6. - * - */ - - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/ip.h" -#include "lwip/inet.h" -#include "lwip/netif.h" -#include "lwip/icmp.h" -#include "lwip/udp.h" -#include "lwip/tcp.h" - -#include "lwip/stats.h" - -#include "arch/perf.h" - -/* ip_init: - * - * Initializes the IP layer. - */ - -void -ip_init(void) -{ -} - -/* ip_route: - * - * Finds the appropriate network interface for a given IP address. It searches the - * list of network interfaces linearly. A match is found if the masked IP address of - * the network interface equals the masked IP address given to the function. - */ - -struct netif * -ip_route(struct ip_addr *dest) -{ - struct netif *netif; - - for(netif = netif_list; netif != NULL; netif = netif->next) { - if (ip_addr_netcmp(dest, &(netif->ip_addr), &(netif->netmask))) { - return netif; - } - } - - return netif_default; -} - -/* ip_forward: - * - * Forwards an IP packet. It finds an appropriate route for the packet, decrements - * the TTL value of the packet, adjusts the checksum and outputs the packet on the - * appropriate interface. - */ - -static void -ip_forward(struct pbuf *p, struct ip_hdr *iphdr) -{ - struct netif *netif; - - PERF_START; - - if ((netif = ip_route((struct ip_addr *)&(iphdr->dest))) == NULL) { - - LWIP_DEBUGF(IP_DEBUG, ("ip_input: no forwarding route found for ")); -#if IP_DEBUG - ip_addr_debug_print(IP_DEBUG, &(iphdr->dest)); -#endif /* IP_DEBUG */ - LWIP_DEBUGF(IP_DEBUG, ("\n")); - pbuf_free(p); - return; - } - /* Decrement TTL and send ICMP if ttl == 0. */ - if (--iphdr->hoplim == 0) { - /* Don't send ICMP messages in response to ICMP messages */ - if (iphdr->nexthdr != IP_PROTO_ICMP) { - icmp_time_exceeded(p, ICMP_TE_TTL); - } - pbuf_free(p); - return; - } - - /* Incremental update of the IP checksum. */ - /* if (iphdr->chksum >= htons(0xffff - 0x100)) { - iphdr->chksum += htons(0x100) + 1; - } else { - iphdr->chksum += htons(0x100); - }*/ - - - LWIP_DEBUGF(IP_DEBUG, ("ip_forward: forwarding packet to ")); -#if IP_DEBUG - ip_addr_debug_print(IP_DEBUG, &(iphdr->dest)); -#endif /* IP_DEBUG */ - LWIP_DEBUGF(IP_DEBUG, ("\n")); - -#ifdef IP_STATS - ++lwip_stats.ip.fw; - ++lwip_stats.ip.xmit; -#endif /* IP_STATS */ - - PERF_STOP("ip_forward"); - - netif->output(netif, p, (struct ip_addr *)&(iphdr->dest)); -} - -/* ip_input: - * - * This function is called by the network interface device driver when an IP packet is - * received. The function does the basic checks of the IP header such as packet size - * being at least larger than the header size etc. If the packet was not destined for - * us, the packet is forwarded (using ip_forward). The IP checksum is always checked. - * - * Finally, the packet is sent to the upper layer protocol input function. - */ - -void -ip_input(struct pbuf *p, struct netif *inp) { - struct ip_hdr *iphdr; - struct netif *netif; - - - PERF_START; - -#if IP_DEBUG - ip_debug_print(p); -#endif /* IP_DEBUG */ - - -#ifdef IP_STATS - ++lwip_stats.ip.recv; -#endif /* IP_STATS */ - - /* identify the IP header */ - iphdr = p->payload; - - - if (iphdr->v != 6) { - LWIP_DEBUGF(IP_DEBUG, ("IP packet dropped due to bad version number\n")); -#if IP_DEBUG - ip_debug_print(p); -#endif /* IP_DEBUG */ - pbuf_free(p); -#ifdef IP_STATS - ++lwip_stats.ip.err; - ++lwip_stats.ip.drop; -#endif /* IP_STATS */ - return; - } - - /* is this packet for us? */ - for(netif = netif_list; netif != NULL; netif = netif->next) { -#if IP_DEBUG - LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest ")); - ip_addr_debug_print(IP_DEBUG, &(iphdr->dest)); - LWIP_DEBUGF(IP_DEBUG, ("netif->ip_addr ")); - ip_addr_debug_print(IP_DEBUG, &(netif->ip_addr)); - LWIP_DEBUGF(IP_DEBUG, ("\n")); -#endif /* IP_DEBUG */ - if (ip_addr_cmp(&(iphdr->dest), &(netif->ip_addr))) { - break; - } - } - - - if (netif == NULL) { - /* packet not for us, route or discard */ -#ifdef IP_FORWARD - ip_forward(p, iphdr); -#endif - pbuf_free(p); - return; - } - - pbuf_realloc(p, IP_HLEN + ntohs(iphdr->len)); - - /* send to upper layers */ -#if IP_DEBUG - /* LWIP_DEBUGF("ip_input: \n"); - ip_debug_print(p); - LWIP_DEBUGF("ip_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len);*/ -#endif /* IP_DEBUG */ - - - pbuf_header(p, -IP_HLEN); - - switch (iphdr->nexthdr) { - case IP_PROTO_UDP: - udp_input(p); - break; - case IP_PROTO_TCP: - tcp_input(p); - break; - case IP_PROTO_ICMP: - icmp_input(p, inp); - break; - default: - /* send ICMP destination protocol unreachable */ - icmp_dest_unreach(p, ICMP_DUR_PROTO); - pbuf_free(p); - LWIP_DEBUGF(IP_DEBUG, ("Unsupported transport protocol %"U16_F"\n", - iphdr->nexthdr)); - -#ifdef IP_STATS - ++lwip_stats.ip.proterr; - ++lwip_stats.ip.drop; -#endif /* IP_STATS */ - - } - PERF_STOP("ip_input"); -} - - -/* ip_output_if: - * - * Sends an IP packet on a network interface. This function constructs the IP header - * and calculates the IP header checksum. If the source IP address is NULL, - * the IP address of the outgoing network interface is filled in as source address. - */ - -err_t -ip_output_if (struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, - u8_t proto, struct netif *netif) -{ - struct ip_hdr *iphdr; - - PERF_START; - - printf("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len); - if (pbuf_header(p, IP_HLEN)) { - LWIP_DEBUGF(IP_DEBUG, ("ip_output: not enough room for IP header in pbuf\n")); -#ifdef IP_STATS - ++lwip_stats.ip.err; -#endif /* IP_STATS */ - - return ERR_BUF; - } - printf("len %"U16_F" tot_len %"U16_F"\n", p->len, p->tot_len); - - iphdr = p->payload; - - - if (dest != IP_HDRINCL) { - printf("!IP_HDRLINCL\n"); - iphdr->hoplim = ttl; - iphdr->nexthdr = proto; - iphdr->len = htons(p->tot_len - IP_HLEN); - ip_addr_set(&(iphdr->dest), dest); - - iphdr->v = 6; - - if (ip_addr_isany(src)) { - ip_addr_set(&(iphdr->src), &(netif->ip_addr)); - } else { - ip_addr_set(&(iphdr->src), src); - } - - } else { - dest = &(iphdr->dest); - } - -#ifdef IP_STATS - ++lwip_stats.ip.xmit; -#endif /* IP_STATS */ - - LWIP_DEBUGF(IP_DEBUG, ("ip_output_if: %c%c (len %"U16_F")\n", netif->name[0], netif->name[1], p->tot_len)); -#if IP_DEBUG - ip_debug_print(p); -#endif /* IP_DEBUG */ - - PERF_STOP("ip_output_if"); - return netif->output(netif, p, dest); -} - -/* ip_output: - * - * Simple interface to ip_output_if. It finds the outgoing network interface and - * calls upon ip_output_if to do the actual work. - */ - -err_t -ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t proto) -{ - struct netif *netif; - if ((netif = ip_route(dest)) == NULL) { - LWIP_DEBUGF(IP_DEBUG, ("ip_output: No route to 0x%"X32_F"\n", dest->addr)); -#ifdef IP_STATS - ++lwip_stats.ip.rterr; -#endif /* IP_STATS */ - return ERR_RTE; - } - - return ip_output_if (p, src, dest, ttl, proto, netif); -} - -#if IP_DEBUG -void -ip_debug_print(struct pbuf *p) -{ - struct ip_hdr *iphdr = p->payload; - u8_t *payload; - - payload = (u8_t *)iphdr + IP_HLEN; - - LWIP_DEBUGF(IP_DEBUG, ("IP header:\n")); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" | %"X16_F"%"X16_F" | %"X16_F"%"X16_F" | (v, traffic class, flow label)\n", - iphdr->v, - iphdr->tclass1, iphdr->tclass2, - iphdr->flow1, iphdr->flow2)); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %5"U16_F" | %2"U16_F" | %2"U16_F" | (len, nexthdr, hoplim)\n", - ntohs(iphdr->len), - iphdr->nexthdr, - iphdr->hoplim)); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (src)\n", - ntohl(iphdr->src.addr[0]) >> 16 & 0xffff, - ntohl(iphdr->src.addr[0]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (src)\n", - ntohl(iphdr->src.addr[1]) >> 16 & 0xffff, - ntohl(iphdr->src.addr[1]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (src)\n", - ntohl(iphdr->src.addr[2]) >> 16 & 0xffff, - ntohl(iphdr->src.addr[2]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (src)\n", - ntohl(iphdr->src.addr[3]) >> 16 & 0xffff, - ntohl(iphdr->src.addr[3]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (dest)\n", - ntohl(iphdr->dest.addr[0]) >> 16 & 0xffff, - ntohl(iphdr->dest.addr[0]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (dest)\n", - ntohl(iphdr->dest.addr[1]) >> 16 & 0xffff, - ntohl(iphdr->dest.addr[1]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (dest)\n", - ntohl(iphdr->dest.addr[2]) >> 16 & 0xffff, - ntohl(iphdr->dest.addr[2]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("| %4"X32_F" | %4"X32_F" | (dest)\n", - ntohl(iphdr->dest.addr[3]) >> 16 & 0xffff, - ntohl(iphdr->dest.addr[3]) & 0xffff)); - LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); -} -#endif /* IP_DEBUG */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv6/ip6_addr.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv6/ip6_addr.c deleted file mode 100644 index dcb507855..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/ipv6/ip6_addr.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/ip_addr.h" -#include "lwip/inet.h" - - -u8_t -ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2, - struct ip_addr *mask) -{ - return((addr1->addr[0] & mask->addr[0]) == (addr2->addr[0] & mask->addr[0]) && - (addr1->addr[1] & mask->addr[1]) == (addr2->addr[1] & mask->addr[1]) && - (addr1->addr[2] & mask->addr[2]) == (addr2->addr[2] & mask->addr[2]) && - (addr1->addr[3] & mask->addr[3]) == (addr2->addr[3] & mask->addr[3])); - -} - -u8_t -ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2) -{ - return(addr1->addr[0] == addr2->addr[0] && - addr1->addr[1] == addr2->addr[1] && - addr1->addr[2] == addr2->addr[2] && - addr1->addr[3] == addr2->addr[3]); -} - -void -ip_addr_set(struct ip_addr *dest, struct ip_addr *src) -{ - memcpy(dest, src, sizeof(struct ip_addr)); - /* dest->addr[0] = src->addr[0]; - dest->addr[1] = src->addr[1]; - dest->addr[2] = src->addr[2]; - dest->addr[3] = src->addr[3];*/ -} - -u8_t -ip_addr_isany(struct ip_addr *addr) -{ - if (addr == NULL) return 1; - return((addr->addr[0] | addr->addr[1] | addr->addr[2] | addr->addr[3]) == 0); -} - - -/*#if IP_DEBUG*/ -void -ip_addr_debug_print(struct ip_addr *addr) -{ - printf("%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F":%"X32_F", - ntohl(addr->addr[0]) >> 16 & 0xffff, - ntohl(addr->addr[0]) & 0xffff, - ntohl(addr->addr[1]) >> 16 & 0xffff, - ntohl(addr->addr[1]) & 0xffff, - ntohl(addr->addr[2]) >> 16 & 0xffff, - ntohl(addr->addr[2]) & 0xffff, - ntohl(addr->addr[3]) >> 16 & 0xffff, - ntohl(addr->addr[3]) & 0xffff); -} -/*#endif*/ /* IP_DEBUG */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/mem.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/mem.c deleted file mode 100644 index b38d8f150..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/mem.c +++ /dev/null @@ -1,310 +0,0 @@ -/** @file - * - * Dynamic memory manager - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include - -#include "lwip/arch.h" -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/mem.h" - -#include "lwip/sys.h" - -#include "lwip/stats.h" - -struct mem { - mem_size_t next, prev; -#if MEM_ALIGNMENT == 1 - u8_t used; -#elif MEM_ALIGNMENT == 2 - u16_t used; -#elif MEM_ALIGNMENT == 4 - u32_t used; -#elif MEM_ALIGNMENT == 8 - u64_t used; -#else -#error "unhandled MEM_ALIGNMENT size" -#endif /* MEM_ALIGNMENT */ -}; - -static struct mem *ram_end; -static u8_t ram[MEM_SIZE + sizeof(struct mem) + MEM_ALIGNMENT]; - -#define MIN_SIZE 12 -#if 0 /* this one does not align correctly for some, resulting in crashes */ -#define SIZEOF_STRUCT_MEM (unsigned int)MEM_ALIGN_SIZE(sizeof(struct mem)) -#else -#define SIZEOF_STRUCT_MEM (sizeof(struct mem) + \ - (((sizeof(struct mem) % MEM_ALIGNMENT) == 0)? 0 : \ - (4 - (sizeof(struct mem) % MEM_ALIGNMENT)))) -#endif - -static struct mem *lfree; /* pointer to the lowest free block */ - -static sys_sem_t mem_sem; - -static void -plug_holes(struct mem *mem) -{ - struct mem *nmem; - struct mem *pmem; - - LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram); - LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end); - LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0); - - /* plug hole forward */ - LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE", mem->next <= MEM_SIZE); - - nmem = (struct mem *)&ram[mem->next]; - if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) { - if (lfree == nmem) { - lfree = mem; - } - mem->next = nmem->next; - ((struct mem *)&ram[nmem->next])->prev = (u8_t *)mem - ram; - } - - /* plug hole backward */ - pmem = (struct mem *)&ram[mem->prev]; - if (pmem != mem && pmem->used == 0) { - if (lfree == mem) { - lfree = pmem; - } - pmem->next = mem->next; - ((struct mem *)&ram[mem->next])->prev = (u8_t *)pmem - ram; - } - -} -void -mem_init(void) -{ - struct mem *mem; - - memset(ram, 0, MEM_SIZE); - mem = (struct mem *)ram; - mem->next = MEM_SIZE; - mem->prev = 0; - mem->used = 0; - ram_end = (struct mem *)&ram[MEM_SIZE]; - ram_end->used = 1; - ram_end->next = MEM_SIZE; - ram_end->prev = MEM_SIZE; - - mem_sem = sys_sem_new(1); - - lfree = (struct mem *)ram; - -#if MEM_STATS - lwip_stats.mem.avail = MEM_SIZE; -#endif /* MEM_STATS */ -} -void -mem_free(void *rmem) -{ - struct mem *mem; - - if (rmem == NULL) { - LWIP_DEBUGF(MEM_DEBUG | DBG_TRACE | 2, ("mem_free(p == NULL) was called.\n")); - return; - } - - sys_sem_wait(mem_sem); - - LWIP_ASSERT("mem_free: legal memory", (u8_t *)rmem >= (u8_t *)ram && - (u8_t *)rmem < (u8_t *)ram_end); - - if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { - LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_free: illegal memory\n")); -#if MEM_STATS - ++lwip_stats.mem.err; -#endif /* MEM_STATS */ - sys_sem_signal(mem_sem); - return; - } - mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM); - - LWIP_ASSERT("mem_free: mem->used", mem->used); - - mem->used = 0; - - if (mem < lfree) { - lfree = mem; - } - -#if MEM_STATS - lwip_stats.mem.used -= mem->next - ((u8_t *)mem - ram); - -#endif /* MEM_STATS */ - plug_holes(mem); - sys_sem_signal(mem_sem); -} -void * -mem_reallocm(void *rmem, mem_size_t newsize) -{ - void *nmem; - nmem = mem_malloc(newsize); - if (nmem == NULL) { - return mem_realloc(rmem, newsize); - } - memcpy(nmem, rmem, newsize); - mem_free(rmem); - return nmem; -} - -void * -mem_realloc(void *rmem, mem_size_t newsize) -{ - mem_size_t size; - mem_size_t ptr, ptr2; - struct mem *mem, *mem2; - - /* Expand the size of the allocated memory region so that we can - adjust for alignment. */ - if ((newsize % MEM_ALIGNMENT) != 0) { - newsize += MEM_ALIGNMENT - ((newsize + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT); - } - - if (newsize > MEM_SIZE) { - return NULL; - } - - sys_sem_wait(mem_sem); - - LWIP_ASSERT("mem_realloc: legal memory", (u8_t *)rmem >= (u8_t *)ram && - (u8_t *)rmem < (u8_t *)ram_end); - - if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { - LWIP_DEBUGF(MEM_DEBUG | 3, ("mem_realloc: illegal memory\n")); - return rmem; - } - mem = (struct mem *)((u8_t *)rmem - SIZEOF_STRUCT_MEM); - - ptr = (u8_t *)mem - ram; - - size = mem->next - ptr - SIZEOF_STRUCT_MEM; -#if MEM_STATS - lwip_stats.mem.used -= (size - newsize); -#endif /* MEM_STATS */ - - if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE < size) { - ptr2 = ptr + SIZEOF_STRUCT_MEM + newsize; - mem2 = (struct mem *)&ram[ptr2]; - mem2->used = 0; - mem2->next = mem->next; - mem2->prev = ptr; - mem->next = ptr2; - if (mem2->next != MEM_SIZE) { - ((struct mem *)&ram[mem2->next])->prev = ptr2; - } - - plug_holes(mem2); - } - sys_sem_signal(mem_sem); - return rmem; -} -void * -mem_malloc(mem_size_t size) -{ - mem_size_t ptr, ptr2; - struct mem *mem, *mem2; - - if (size == 0) { - return NULL; - } - - /* Expand the size of the allocated memory region so that we can - adjust for alignment. */ - if ((size % MEM_ALIGNMENT) != 0) { - size += MEM_ALIGNMENT - ((size + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT); - } - - if (size > MEM_SIZE) { - return NULL; - } - - sys_sem_wait(mem_sem); - - for (ptr = (u8_t *)lfree - ram; ptr < MEM_SIZE; ptr = ((struct mem *)&ram[ptr])->next) { - mem = (struct mem *)&ram[ptr]; - if (!mem->used && - mem->next - (ptr + SIZEOF_STRUCT_MEM) >= size + SIZEOF_STRUCT_MEM) { - ptr2 = ptr + SIZEOF_STRUCT_MEM + size; - mem2 = (struct mem *)&ram[ptr2]; - - mem2->prev = ptr; - mem2->next = mem->next; - mem->next = ptr2; - if (mem2->next != MEM_SIZE) { - ((struct mem *)&ram[mem2->next])->prev = ptr2; - } - - mem2->used = 0; - mem->used = 1; -#if MEM_STATS - lwip_stats.mem.used += (size + SIZEOF_STRUCT_MEM); - /* if (lwip_stats.mem.max < lwip_stats.mem.used) { - lwip_stats.mem.max = lwip_stats.mem.used; - } */ - if (lwip_stats.mem.max < ptr2) { - lwip_stats.mem.max = ptr2; - } -#endif /* MEM_STATS */ - - if (mem == lfree) { - /* Find next free block after mem */ - while (lfree->used && lfree != ram_end) { - lfree = (struct mem *)&ram[lfree->next]; - } - LWIP_ASSERT("mem_malloc: !lfree->used", !lfree->used); - } - sys_sem_signal(mem_sem); - LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.", - (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end); - LWIP_ASSERT("mem_malloc: allocated memory properly aligned.", - (unsigned long)((u8_t *)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0); - return (u8_t *)mem + SIZEOF_STRUCT_MEM; - } - } - LWIP_DEBUGF(MEM_DEBUG | 2, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size)); -#if MEM_STATS - ++lwip_stats.mem.err; -#endif /* MEM_STATS */ - sys_sem_signal(mem_sem); - return NULL; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/memp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/memp.c deleted file mode 100644 index c0cfce29c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/memp.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/memp.h" - -#include "lwip/pbuf.h" -#include "lwip/udp.h" -#include "lwip/raw.h" -#include "lwip/tcp.h" -#include "lwip/api.h" -#include "lwip/api_msg.h" -#include "lwip/tcpip.h" - -#include "lwip/sys.h" -#include "lwip/stats.h" - -struct memp { - struct memp *next; -}; - - - -static struct memp *memp_tab[MEMP_MAX]; - -static const u16_t memp_sizes[MEMP_MAX] = { - sizeof(struct pbuf), - sizeof(struct raw_pcb), - sizeof(struct udp_pcb), - sizeof(struct tcp_pcb), - sizeof(struct tcp_pcb_listen), - sizeof(struct tcp_seg), - sizeof(struct netbuf), - sizeof(struct netconn), - sizeof(struct api_msg), - sizeof(struct tcpip_msg), - sizeof(struct sys_timeout) -}; - -static const u16_t memp_num[MEMP_MAX] = { - MEMP_NUM_PBUF, - MEMP_NUM_RAW_PCB, - MEMP_NUM_UDP_PCB, - MEMP_NUM_TCP_PCB, - MEMP_NUM_TCP_PCB_LISTEN, - MEMP_NUM_TCP_SEG, - MEMP_NUM_NETBUF, - MEMP_NUM_NETCONN, - MEMP_NUM_API_MSG, - MEMP_NUM_TCPIP_MSG, - MEMP_NUM_SYS_TIMEOUT -}; - -static u8_t memp_memory[(MEMP_NUM_PBUF * - MEM_ALIGN_SIZE(sizeof(struct pbuf) + - sizeof(struct memp)) + - MEMP_NUM_RAW_PCB * - MEM_ALIGN_SIZE(sizeof(struct raw_pcb) + - sizeof(struct memp)) + - MEMP_NUM_UDP_PCB * - MEM_ALIGN_SIZE(sizeof(struct udp_pcb) + - sizeof(struct memp)) + - MEMP_NUM_TCP_PCB * - MEM_ALIGN_SIZE(sizeof(struct tcp_pcb) + - sizeof(struct memp)) + - MEMP_NUM_TCP_PCB_LISTEN * - MEM_ALIGN_SIZE(sizeof(struct tcp_pcb_listen) + - sizeof(struct memp)) + - MEMP_NUM_TCP_SEG * - MEM_ALIGN_SIZE(sizeof(struct tcp_seg) + - sizeof(struct memp)) + - MEMP_NUM_NETBUF * - MEM_ALIGN_SIZE(sizeof(struct netbuf) + - sizeof(struct memp)) + - MEMP_NUM_NETCONN * - MEM_ALIGN_SIZE(sizeof(struct netconn) + - sizeof(struct memp)) + - MEMP_NUM_API_MSG * - MEM_ALIGN_SIZE(sizeof(struct api_msg) + - sizeof(struct memp)) + - MEMP_NUM_TCPIP_MSG * - MEM_ALIGN_SIZE(sizeof(struct tcpip_msg) + - sizeof(struct memp)) + - MEMP_NUM_SYS_TIMEOUT * - MEM_ALIGN_SIZE(sizeof(struct sys_timeout) + - sizeof(struct memp)))]; - - -#if !SYS_LIGHTWEIGHT_PROT -static sys_sem_t mutex; -#endif - -#if MEMP_SANITY_CHECK -static int -memp_sanity(void) -{ - s16_t i, c; - struct memp *m, *n; - - for(i = 0; i < MEMP_MAX; i++) { - for(m = memp_tab[i]; m != NULL; m = m->next) { - c = 1; - for(n = memp_tab[i]; n != NULL; n = n->next) { - if (n == m) { - --c; - } - if (c < 0) return 0; /* LW was: abort(); */ - } - } - } - return 1; -} -#endif /* MEMP_SANITY_CHECK*/ - -void -memp_init(void) -{ - struct memp *m, *memp; - u16_t i, j; - u16_t size; - -#if MEMP_STATS - for(i = 0; i < MEMP_MAX; ++i) { - lwip_stats.memp[i].used = lwip_stats.memp[i].max = - lwip_stats.memp[i].err = 0; - lwip_stats.memp[i].avail = memp_num[i]; - } -#endif /* MEMP_STATS */ - - memp = (struct memp *)&memp_memory[0]; - for(i = 0; i < MEMP_MAX; ++i) { - size = MEM_ALIGN_SIZE(memp_sizes[i] + sizeof(struct memp)); - if (memp_num[i] > 0) { - memp_tab[i] = memp; - m = memp; - - for(j = 0; j < memp_num[i]; ++j) { - m->next = (struct memp *)MEM_ALIGN((u8_t *)m + size); - memp = m; - m = m->next; - } - memp->next = NULL; - memp = m; - } else { - memp_tab[i] = NULL; - } - } - -#if !SYS_LIGHTWEIGHT_PROT - mutex = sys_sem_new(1); -#endif - - -} - -void * -memp_malloc(memp_t type) -{ - struct memp *memp; - void *mem; -#if SYS_LIGHTWEIGHT_PROT - SYS_ARCH_DECL_PROTECT(old_level); -#endif - - LWIP_ASSERT("memp_malloc: type < MEMP_MAX", type < MEMP_MAX); - -#if SYS_LIGHTWEIGHT_PROT - SYS_ARCH_PROTECT(old_level); -#else /* SYS_LIGHTWEIGHT_PROT */ - sys_sem_wait(mutex); -#endif /* SYS_LIGHTWEIGHT_PROT */ - - memp = memp_tab[type]; - - if (memp != NULL) { - memp_tab[type] = memp->next; - memp->next = NULL; -#if MEMP_STATS - ++lwip_stats.memp[type].used; - if (lwip_stats.memp[type].used > lwip_stats.memp[type].max) { - lwip_stats.memp[type].max = lwip_stats.memp[type].used; - } -#endif /* MEMP_STATS */ -#if SYS_LIGHTWEIGHT_PROT - SYS_ARCH_UNPROTECT(old_level); -#else /* SYS_LIGHTWEIGHT_PROT */ - sys_sem_signal(mutex); -#endif /* SYS_LIGHTWEIGHT_PROT */ - LWIP_ASSERT("memp_malloc: memp properly aligned", - ((mem_ptr_t)MEM_ALIGN((u8_t *)memp + sizeof(struct memp)) % MEM_ALIGNMENT) == 0); - - mem = MEM_ALIGN((u8_t *)memp + sizeof(struct memp)); - return mem; - } else { - LWIP_DEBUGF(MEMP_DEBUG | 2, ("memp_malloc: out of memory in pool %"S16_F"\n", type)); -#if MEMP_STATS - ++lwip_stats.memp[type].err; -#endif /* MEMP_STATS */ -#if SYS_LIGHTWEIGHT_PROT - SYS_ARCH_UNPROTECT(old_level); -#else /* SYS_LIGHTWEIGHT_PROT */ - sys_sem_signal(mutex); -#endif /* SYS_LIGHTWEIGHT_PROT */ - return NULL; - } -} - -void -memp_free(memp_t type, void *mem) -{ - struct memp *memp; -#if SYS_LIGHTWEIGHT_PROT - SYS_ARCH_DECL_PROTECT(old_level); -#endif /* SYS_LIGHTWEIGHT_PROT */ - - if (mem == NULL) { - return; - } - memp = (struct memp *)((u8_t *)mem - sizeof(struct memp)); - -#if SYS_LIGHTWEIGHT_PROT - SYS_ARCH_PROTECT(old_level); -#else /* SYS_LIGHTWEIGHT_PROT */ - sys_sem_wait(mutex); -#endif /* SYS_LIGHTWEIGHT_PROT */ - -#if MEMP_STATS - lwip_stats.memp[type].used--; -#endif /* MEMP_STATS */ - - memp->next = memp_tab[type]; - memp_tab[type] = memp; - -#if MEMP_SANITY_CHECK - LWIP_ASSERT("memp sanity", memp_sanity()); -#endif - -#if SYS_LIGHTWEIGHT_PROT - SYS_ARCH_UNPROTECT(old_level); -#else /* SYS_LIGHTWEIGHT_PROT */ - sys_sem_signal(mutex); -#endif /* SYS_LIGHTWEIGHT_PROT */ -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/netif.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/netif.c deleted file mode 100644 index 3525089b2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/netif.c +++ /dev/null @@ -1,288 +0,0 @@ -/** - * @file - * - * lwIP network interface abstraction - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/tcp.h" - -struct netif *netif_list = NULL; -struct netif *netif_default = NULL; - -/** - * Add a network interface to the list of lwIP netifs. - * - * @param netif a pre-allocated netif structure - * @param ipaddr IP address for the new netif - * @param netmask network mask for the new netif - * @param gw default gateway IP address for the new netif - * @param state opaque data passed to the new netif - * @param init callback function that initializes the interface - * @param input callback function that is called to pass - * ingress packets up in the protocol layer stack. - * - * @return netif, or NULL if failed. - */ -struct netif * -netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask, - struct ip_addr *gw, - void *state, - err_t (* init)(struct netif *netif), - err_t (* input)(struct pbuf *p, struct netif *netif)) -{ - static s16_t netifnum = 0; - -#if LWIP_DHCP - /* netif not under DHCP control by default */ - netif->dhcp = NULL; -#endif - /* remember netif specific state information data */ - netif->state = state; - netif->num = netifnum++; - netif->input = input; - - netif_set_addr(netif, ipaddr, netmask, gw); - - /* call user specified initialization function for netif */ - if (init(netif) != ERR_OK) { - return NULL; - } - - /* add this netif to the list */ - netif->next = netif_list; - netif_list = netif; - LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP addr ", - netif->name[0], netif->name[1])); - ip_addr_debug_print(NETIF_DEBUG, ipaddr); - LWIP_DEBUGF(NETIF_DEBUG, (" netmask ")); - ip_addr_debug_print(NETIF_DEBUG, netmask); - LWIP_DEBUGF(NETIF_DEBUG, (" gw ")); - ip_addr_debug_print(NETIF_DEBUG, gw); - LWIP_DEBUGF(NETIF_DEBUG, ("\n")); - return netif; -} - -void -netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask, - struct ip_addr *gw) -{ - netif_set_ipaddr(netif, ipaddr); - netif_set_netmask(netif, netmask); - netif_set_gw(netif, gw); -} - -void netif_remove(struct netif * netif) -{ - if ( netif == NULL ) return; - - /* is it the first netif? */ - if (netif_list == netif) { - netif_list = netif->next; - } - else { - /* look for netif further down the list */ - struct netif * tmpNetif; - for (tmpNetif = netif_list; tmpNetif != NULL; tmpNetif = tmpNetif->next) { - if (tmpNetif->next == netif) { - tmpNetif->next = netif->next; - break; - } - } - if (tmpNetif == NULL) - return; /* we didn't find any netif today */ - } - /* this netif is default? */ - if (netif_default == netif) - /* reset default netif */ - netif_default = NULL; - LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") ); -} - -struct netif * -netif_find(char *name) -{ - struct netif *netif; - u8_t num; - - if (name == NULL) { - return NULL; - } - - num = name[2] - '0'; - - for(netif = netif_list; netif != NULL; netif = netif->next) { - if (num == netif->num && - name[0] == netif->name[0] && - name[1] == netif->name[1]) { - LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1])); - return netif; - } - } - LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1])); - return NULL; -} - -void -netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr) -{ - /* TODO: Handling of obsolete pcbs */ - /* See: http://mail.gnu.org/archive/html/lwip-users/2003-03/msg00118.html */ -#if LWIP_TCP - struct tcp_pcb *pcb; - struct tcp_pcb_listen *lpcb; - - /* address is actually being changed? */ - if ((ip_addr_cmp(ipaddr, &(netif->ip_addr))) == 0) - { - /* extern struct tcp_pcb *tcp_active_pcbs; defined by tcp.h */ - LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: netif address being changed\n")); - pcb = tcp_active_pcbs; - while (pcb != NULL) { - /* PCB bound to current local interface address? */ - if (ip_addr_cmp(&(pcb->local_ip), &(netif->ip_addr))) { - /* this connection must be aborted */ - struct tcp_pcb *next = pcb->next; - LWIP_DEBUGF(NETIF_DEBUG | 1, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb)); - tcp_abort(pcb); - pcb = next; - } else { - pcb = pcb->next; - } - } - for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { - /* PCB bound to current local interface address? */ - if (ip_addr_cmp(&(lpcb->local_ip), &(netif->ip_addr))) { - /* The PCB is listening to the old ipaddr and - * is set to listen to the new one instead */ - ip_addr_set(&(lpcb->local_ip), ipaddr); - } - } - } -#endif - ip_addr_set(&(netif->ip_addr), ipaddr); -#if 0 /* only allowed for Ethernet interfaces TODO: how can we check? */ - /** For Ethernet network interfaces, we would like to send a - * "gratuitous ARP"; this is an ARP packet sent by a node in order - * to spontaneously cause other nodes to update an entry in their - * ARP cache. From RFC 3220 "IP Mobility Support for IPv4" section 4.6. - */ - etharp_query(netif, ipaddr, NULL); -#endif - LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: IP address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - netif->name[0], netif->name[1], - ip4_addr1(&netif->ip_addr), - ip4_addr2(&netif->ip_addr), - ip4_addr3(&netif->ip_addr), - ip4_addr4(&netif->ip_addr))); -} - -void -netif_set_gw(struct netif *netif, struct ip_addr *gw) -{ - ip_addr_set(&(netif->gw), gw); - LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - netif->name[0], netif->name[1], - ip4_addr1(&netif->gw), - ip4_addr2(&netif->gw), - ip4_addr3(&netif->gw), - ip4_addr4(&netif->gw))); -} - -void -netif_set_netmask(struct netif *netif, struct ip_addr *netmask) -{ - ip_addr_set(&(netif->netmask), netmask); - LWIP_DEBUGF(NETIF_DEBUG | DBG_TRACE | DBG_STATE | 3, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - netif->name[0], netif->name[1], - ip4_addr1(&netif->netmask), - ip4_addr2(&netif->netmask), - ip4_addr3(&netif->netmask), - ip4_addr4(&netif->netmask))); -} - -void -netif_set_default(struct netif *netif) -{ - netif_default = netif; - LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n", - netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\'')); -} - -/** - * Bring an interface up, available for processing - * traffic. - * - * @note: Enabling DHCP on a down interface will make it come - * up once configured. - * - * @see dhcp_start() - */ -void netif_set_up(struct netif *netif) -{ - netif->flags |= NETIF_FLAG_UP; -} - -/** - * Ask if an interface is up - */ -u8_t netif_is_up(struct netif *netif) -{ - return (netif->flags & NETIF_FLAG_UP)?1:0; -} - -/** - * Bring an interface down, disabling any traffic processing. - * - * @note: Enabling DHCP on a down interface will make it come - * up once configured. - * - * @see dhcp_start() - */ -void netif_set_down(struct netif *netif) -{ - netif->flags &= ~NETIF_FLAG_UP; -} - -void -netif_init(void) -{ - netif_list = netif_default = NULL; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/pbuf.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/pbuf.c deleted file mode 100644 index 2ece4b098..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/pbuf.c +++ /dev/null @@ -1,957 +0,0 @@ -/** - * @file - * Packet buffer management - * - * Packets are built from the pbuf data structure. It supports dynamic - * memory allocation for packet contents or can reference externally - * managed packet contents both in RAM and ROM. Quick allocation for - * incoming packets is provided through pools with fixed sized pbufs. - * - * A packet may span over multiple pbufs, chained as a singly linked - * list. This is called a "pbuf chain". - * - * Multiple packets may be queued, also using this singly linked list. - * This is called a "packet queue". - * - * So, a packet queue consists of one or more pbuf chains, each of - * which consist of one or more pbufs. Currently, queues are only - * supported in a limited section of lwIP, this is the etharp queueing - * code. Outside of this section no packet queues are supported yet. - * - * The differences between a pbuf chain and a packet queue are very - * precise but subtle. - * - * The last pbuf of a packet has a ->tot_len field that equals the - * ->len field. It can be found by traversing the list. If the last - * pbuf of a packet has a ->next field other than NULL, more packets - * are on the queue. - * - * Therefore, looping through a pbuf of a single packet, has an - * loop end condition (tot_len == p->len), NOT (next == NULL). - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include - -#include "lwip/opt.h" -#include "lwip/stats.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/memp.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include "arch/perf.h" - -static u8_t pbuf_pool_memory[MEM_ALIGNMENT - 1 + PBUF_POOL_SIZE * MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE + sizeof(struct pbuf))]; - -#if !SYS_LIGHTWEIGHT_PROT -static volatile u8_t pbuf_pool_free_lock, pbuf_pool_alloc_lock; -static sys_sem_t pbuf_pool_free_sem; -#endif - -static struct pbuf *pbuf_pool = NULL; - -/** - * Initializes the pbuf module. - * - * A large part of memory is allocated for holding the pool of pbufs. - * The size of the individual pbufs in the pool is given by the size - * parameter, and the number of pbufs in the pool by the num parameter. - * - * After the memory has been allocated, the pbufs are set up. The - * ->next pointer in each pbuf is set up to point to the next pbuf in - * the pool. - * - */ -void -pbuf_init(void) -{ - struct pbuf *p, *q = NULL; - u16_t i; - - pbuf_pool = (struct pbuf *)MEM_ALIGN(pbuf_pool_memory); - -#if PBUF_STATS - lwip_stats.pbuf.avail = PBUF_POOL_SIZE; -#endif /* PBUF_STATS */ - - /* Set up ->next pointers to link the pbufs of the pool together */ - p = pbuf_pool; - - for(i = 0; i < PBUF_POOL_SIZE; ++i) { - p->next = (struct pbuf *)((u8_t *)p + PBUF_POOL_BUFSIZE + sizeof(struct pbuf)); - p->len = p->tot_len = PBUF_POOL_BUFSIZE; - p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf))); - p->flags = PBUF_FLAG_POOL; - q = p; - p = p->next; - } - - /* The ->next pointer of last pbuf is NULL to indicate that there - are no more pbufs in the pool */ - q->next = NULL; - -#if !SYS_LIGHTWEIGHT_PROT - pbuf_pool_alloc_lock = 0; - pbuf_pool_free_lock = 0; - pbuf_pool_free_sem = sys_sem_new(1); -#endif -} - -/** - * @internal only called from pbuf_alloc() - */ -static struct pbuf * -pbuf_pool_alloc(void) -{ - struct pbuf *p = NULL; - - SYS_ARCH_DECL_PROTECT(old_level); - SYS_ARCH_PROTECT(old_level); - -#if !SYS_LIGHTWEIGHT_PROT - /* Next, check the actual pbuf pool, but if the pool is locked, we - pretend to be out of buffers and return NULL. */ - if (pbuf_pool_free_lock) { -#if PBUF_STATS - ++lwip_stats.pbuf.alloc_locked; -#endif /* PBUF_STATS */ - return NULL; - } - pbuf_pool_alloc_lock = 1; - if (!pbuf_pool_free_lock) { -#endif /* SYS_LIGHTWEIGHT_PROT */ - p = pbuf_pool; - if (p) { - pbuf_pool = p->next; - } -#if !SYS_LIGHTWEIGHT_PROT -#if PBUF_STATS - } else { - ++lwip_stats.pbuf.alloc_locked; -#endif /* PBUF_STATS */ - } - pbuf_pool_alloc_lock = 0; -#endif /* SYS_LIGHTWEIGHT_PROT */ - -#if PBUF_STATS - if (p != NULL) { - ++lwip_stats.pbuf.used; - if (lwip_stats.pbuf.used > lwip_stats.pbuf.max) { - lwip_stats.pbuf.max = lwip_stats.pbuf.used; - } - } -#endif /* PBUF_STATS */ - - SYS_ARCH_UNPROTECT(old_level); - return p; -} - - -/** - * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type). - * - * The actual memory allocated for the pbuf is determined by the - * layer at which the pbuf is allocated and the requested size - * (from the size parameter). - * - * @param flag this parameter decides how and where the pbuf - * should be allocated as follows: - * - * - PBUF_RAM: buffer memory for pbuf is allocated as one large - * chunk. This includes protocol headers as well. - * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for - * protocol headers. Additional headers must be prepended - * by allocating another pbuf and chain in to the front of - * the ROM pbuf. It is assumed that the memory used is really - * similar to ROM in that it is immutable and will not be - * changed. Memory which is dynamic should generally not - * be attached to PBUF_ROM pbufs. Use PBUF_REF instead. - * - PBUF_REF: no buffer memory is allocated for the pbuf, even for - * protocol headers. It is assumed that the pbuf is only - * being used in a single thread. If the pbuf gets queued, - * then pbuf_take should be called to copy the buffer. - * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from - * the pbuf pool that is allocated during pbuf_init(). - * - * @return the allocated pbuf. If multiple pbufs where allocated, this - * is the first pbuf of a pbuf chain. - */ -struct pbuf * -pbuf_alloc(pbuf_layer l, u16_t length, pbuf_flag flag) -{ - struct pbuf *p, *q, *r; - u16_t offset; - s32_t rem_len; /* remaining length */ - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F")\n", length)); - - /* determine header offset */ - offset = 0; - switch (l) { - case PBUF_TRANSPORT: - /* add room for transport (often TCP) layer header */ - offset += PBUF_TRANSPORT_HLEN; - /* FALLTHROUGH */ - case PBUF_IP: - /* add room for IP layer header */ - offset += PBUF_IP_HLEN; - /* FALLTHROUGH */ - case PBUF_LINK: - /* add room for link layer header */ - offset += PBUF_LINK_HLEN; - break; - case PBUF_RAW: - break; - default: - LWIP_ASSERT("pbuf_alloc: bad pbuf layer", 0); - return NULL; - } - - switch (flag) { - case PBUF_POOL: - /* allocate head of pbuf chain into p */ - p = pbuf_pool_alloc(); - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc: allocated pbuf %p\n", (void *)p)); - if (p == NULL) { -#if PBUF_STATS - ++lwip_stats.pbuf.err; -#endif /* PBUF_STATS */ - return NULL; - } - p->next = NULL; - - /* make the payload pointer point 'offset' bytes into pbuf data memory */ - p->payload = MEM_ALIGN((void *)((u8_t *)p + (sizeof(struct pbuf) + offset))); - LWIP_ASSERT("pbuf_alloc: pbuf p->payload properly aligned", - ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); - /* the total length of the pbuf chain is the requested size */ - p->tot_len = length; - /* set the length of the first pbuf in the chain */ - p->len = length > PBUF_POOL_BUFSIZE - offset? PBUF_POOL_BUFSIZE - offset: length; - /* set reference count (needed here in case we fail) */ - p->ref = 1; - - /* now allocate the tail of the pbuf chain */ - - /* remember first pbuf for linkage in next iteration */ - r = p; - /* remaining length to be allocated */ - rem_len = length - p->len; - /* any remaining pbufs to be allocated? */ - while (rem_len > 0) { - q = pbuf_pool_alloc(); - if (q == NULL) { - LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_alloc: Out of pbufs in pool.\n")); -#if PBUF_STATS - ++lwip_stats.pbuf.err; -#endif /* PBUF_STATS */ - /* free chain so far allocated */ - pbuf_free(p); - /* bail out unsuccesfully */ - return NULL; - } - q->next = NULL; - /* make previous pbuf point to this pbuf */ - r->next = q; - /* set total length of this pbuf and next in chain */ - q->tot_len = rem_len; - /* this pbuf length is pool size, unless smaller sized tail */ - q->len = rem_len > PBUF_POOL_BUFSIZE? PBUF_POOL_BUFSIZE: rem_len; - q->payload = (void *)((u8_t *)q + sizeof(struct pbuf)); - LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned", - ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0); - q->ref = 1; - /* calculate remaining length to be allocated */ - rem_len -= q->len; - /* remember this pbuf for linkage in next iteration */ - r = q; - } - /* end of chain */ - /*r->next = NULL;*/ - - break; - case PBUF_RAM: - /* If pbuf is to be allocated in RAM, allocate memory for it. */ - p = mem_malloc(MEM_ALIGN_SIZE(sizeof(struct pbuf) + offset) + MEM_ALIGN_SIZE(length)); - if (p == NULL) { - return NULL; - } - /* Set up internal structure of the pbuf. */ - p->payload = MEM_ALIGN((void *)((u8_t *)p + sizeof(struct pbuf) + offset)); - p->len = p->tot_len = length; - p->next = NULL; - p->flags = PBUF_FLAG_RAM; - - LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned", - ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); - break; - /* pbuf references existing (non-volatile static constant) ROM payload? */ - case PBUF_ROM: - /* pbuf references existing (externally allocated) RAM payload? */ - case PBUF_REF: - /* only allocate memory for the pbuf structure */ - p = memp_malloc(MEMP_PBUF); - if (p == NULL) { - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_alloc: Could not allocate MEMP_PBUF for PBUF_%s.\n", flag == PBUF_ROM?"ROM":"REF")); - return NULL; - } - /* caller must set this field properly, afterwards */ - p->payload = NULL; - p->len = p->tot_len = length; - p->next = NULL; - p->flags = (flag == PBUF_ROM? PBUF_FLAG_ROM: PBUF_FLAG_REF); - break; - default: - LWIP_ASSERT("pbuf_alloc: erroneous flag", 0); - return NULL; - } - /* set reference count */ - p->ref = 1; - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p)); - return p; -} - - -#if PBUF_STATS -#define DEC_PBUF_STATS do { --lwip_stats.pbuf.used; } while (0) -#else /* PBUF_STATS */ -#define DEC_PBUF_STATS -#endif /* PBUF_STATS */ - -#define PBUF_POOL_FAST_FREE(p) do { \ - p->next = pbuf_pool; \ - pbuf_pool = p; \ - DEC_PBUF_STATS; \ - } while (0) - -#if SYS_LIGHTWEIGHT_PROT -#define PBUF_POOL_FREE(p) do { \ - SYS_ARCH_DECL_PROTECT(old_level); \ - SYS_ARCH_PROTECT(old_level); \ - PBUF_POOL_FAST_FREE(p); \ - SYS_ARCH_UNPROTECT(old_level); \ - } while (0) -#else /* SYS_LIGHTWEIGHT_PROT */ -#define PBUF_POOL_FREE(p) do { \ - sys_sem_wait(pbuf_pool_free_sem); \ - PBUF_POOL_FAST_FREE(p); \ - sys_sem_signal(pbuf_pool_free_sem); \ - } while (0) -#endif /* SYS_LIGHTWEIGHT_PROT */ - -/** - * Shrink a pbuf chain to a desired length. - * - * @param p pbuf to shrink. - * @param new_len desired new length of pbuf chain - * - * Depending on the desired length, the first few pbufs in a chain might - * be skipped and left unchanged. The new last pbuf in the chain will be - * resized, and any remaining pbufs will be freed. - * - * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted. - * @note May not be called on a packet queue. - * - * @bug Cannot grow the size of a pbuf (chain) (yet). - */ -void -pbuf_realloc(struct pbuf *p, u16_t new_len) -{ - struct pbuf *q; - u16_t rem_len; /* remaining length */ - s16_t grow; - - LWIP_ASSERT("pbuf_realloc: sane p->flags", p->flags == PBUF_FLAG_POOL || - p->flags == PBUF_FLAG_ROM || - p->flags == PBUF_FLAG_RAM || - p->flags == PBUF_FLAG_REF); - - /* desired length larger than current length? */ - if (new_len >= p->tot_len) { - /* enlarging not yet supported */ - return; - } - - /* the pbuf chain grows by (new_len - p->tot_len) bytes - * (which may be negative in case of shrinking) */ - grow = new_len - p->tot_len; - - /* first, step over any pbufs that should remain in the chain */ - rem_len = new_len; - q = p; - /* should this pbuf be kept? */ - while (rem_len > q->len) { - /* decrease remaining length by pbuf length */ - rem_len -= q->len; - /* decrease total length indicator */ - q->tot_len += grow; - /* proceed to next pbuf in chain */ - q = q->next; - } - /* we have now reached the new last pbuf (in q) */ - /* rem_len == desired length for pbuf q */ - - /* shrink allocated memory for PBUF_RAM */ - /* (other types merely adjust their length fields */ - if ((q->flags == PBUF_FLAG_RAM) && (rem_len != q->len)) { - /* reallocate and adjust the length of the pbuf that will be split */ - mem_realloc(q, (u8_t *)q->payload - (u8_t *)q + rem_len); - } - /* adjust length fields for new last pbuf */ - q->len = rem_len; - q->tot_len = q->len; - - /* any remaining pbufs in chain? */ - if (q->next != NULL) { - /* free remaining pbufs in chain */ - pbuf_free(q->next); - } - /* q is last packet in chain */ - q->next = NULL; - -} - -/** - * Adjusts the payload pointer to hide or reveal headers in the payload. - * - * Adjusts the ->payload pointer so that space for a header - * (dis)appears in the pbuf payload. - * - * The ->payload, ->tot_len and ->len fields are adjusted. - * - * @param hdr_size_inc Number of bytes to increment header size which - * increases the size of the pbuf. New space is on the front. - * (Using a negative value decreases the header size.) - * If hdr_size_inc is 0, this function does nothing and returns succesful. - * - * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so - * the call will fail. A check is made that the increase in header size does - * not move the payload pointer in front of the start of the buffer. - * @return non-zero on failure, zero on success. - * - */ -u8_t -pbuf_header(struct pbuf *p, s16_t header_size_increment) -{ - void *payload; - - LWIP_ASSERT("p != NULL", p != NULL); - if ((header_size_increment == 0) || (p == NULL)) return 0; - - /* remember current payload pointer */ - payload = p->payload; - - /* pbuf types containing payloads? */ - if (p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_POOL) { - /* set new payload pointer */ - p->payload = (u8_t *)p->payload - header_size_increment; - /* boundary check fails? */ - if ((u8_t *)p->payload < (u8_t *)p + sizeof(struct pbuf)) { - LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_header: failed as %p < %p (not enough space for new header size)\n", - (void *)p->payload, - (void *)(p + 1)));\ - /* restore old payload pointer */ - p->payload = payload; - /* bail out unsuccesfully */ - return 1; - } - /* pbuf types refering to external payloads? */ - } else if (p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_ROM) { - /* hide a header in the payload? */ - if ((header_size_increment < 0) && (header_size_increment - p->len <= 0)) { - /* increase payload pointer */ - p->payload = (u8_t *)p->payload - header_size_increment; - } else { - /* cannot expand payload to front (yet!) - * bail out unsuccesfully */ - return 1; - } - } - /* modify pbuf length fields */ - p->len += header_size_increment; - p->tot_len += header_size_increment; - - LWIP_DEBUGF( PBUF_DEBUG, ("pbuf_header: old %p new %p (%"S16_F")\n", - (void *)payload, (void *)p->payload, header_size_increment)); - - return 0; -} - -/** - * Dereference a pbuf chain or queue and deallocate any no-longer-used - * pbufs at the head of this chain or queue. - * - * Decrements the pbuf reference count. If it reaches zero, the pbuf is - * deallocated. - * - * For a pbuf chain, this is repeated for each pbuf in the chain, - * up to the first pbuf which has a non-zero reference count after - * decrementing. So, when all reference counts are one, the whole - * chain is free'd. - * - * @param pbuf The pbuf (chain) to be dereferenced. - * - * @return the number of pbufs that were de-allocated - * from the head of the chain. - * - * @note MUST NOT be called on a packet queue (Not verified to work yet). - * @note the reference counter of a pbuf equals the number of pointers - * that refer to the pbuf (or into the pbuf). - * - * @internal examples: - * - * Assuming existing chains a->b->c with the following reference - * counts, calling pbuf_free(a) results in: - * - * 1->2->3 becomes ...1->3 - * 3->3->3 becomes 2->3->3 - * 1->1->2 becomes ......1 - * 2->1->1 becomes 1->1->1 - * 1->1->1 becomes ....... - * - */ -u8_t -pbuf_free(struct pbuf *p) -{ - struct pbuf *q; - u8_t count; - SYS_ARCH_DECL_PROTECT(old_level); - - LWIP_ASSERT("p != NULL", p != NULL); - /* if assertions are disabled, proceed with debug output */ - if (p == NULL) { - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_free(p == NULL) was called.\n")); - return 0; - } - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_free(%p)\n", (void *)p)); - - PERF_START; - - LWIP_ASSERT("pbuf_free: sane flags", - p->flags == PBUF_FLAG_RAM || p->flags == PBUF_FLAG_ROM || - p->flags == PBUF_FLAG_REF || p->flags == PBUF_FLAG_POOL); - - count = 0; - /* Since decrementing ref cannot be guaranteed to be a single machine operation - * we must protect it. Also, the later test of ref must be protected. - */ - SYS_ARCH_PROTECT(old_level); - /* de-allocate all consecutive pbufs from the head of the chain that - * obtain a zero reference count after decrementing*/ - while (p != NULL) { - /* all pbufs in a chain are referenced at least once */ - LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0); - /* decrease reference count (number of pointers to pbuf) */ - p->ref--; - /* this pbuf is no longer referenced to? */ - if (p->ref == 0) { - /* remember next pbuf in chain for next iteration */ - q = p->next; - LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: deallocating %p\n", (void *)p)); - /* is this a pbuf from the pool? */ - if (p->flags == PBUF_FLAG_POOL) { - p->len = p->tot_len = PBUF_POOL_BUFSIZE; - p->payload = (void *)((u8_t *)p + sizeof(struct pbuf)); - PBUF_POOL_FREE(p); - /* is this a ROM or RAM referencing pbuf? */ - } else if (p->flags == PBUF_FLAG_ROM || p->flags == PBUF_FLAG_REF) { - memp_free(MEMP_PBUF, p); - /* p->flags == PBUF_FLAG_RAM */ - } else { - mem_free(p); - } - count++; - /* proceed to next pbuf */ - p = q; - /* p->ref > 0, this pbuf is still referenced to */ - /* (and so the remaining pbufs in chain as well) */ - } else { - LWIP_DEBUGF( PBUF_DEBUG | 2, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)p->ref)); - /* stop walking through the chain */ - p = NULL; - } - } - SYS_ARCH_UNPROTECT(old_level); - PERF_STOP("pbuf_free"); - /* return number of de-allocated pbufs */ - return count; -} - -/** - * Count number of pbufs in a chain - * - * @param p first pbuf of chain - * @return the number of pbufs in a chain - */ - -u8_t -pbuf_clen(struct pbuf *p) -{ - u8_t len; - - len = 0; - while (p != NULL) { - ++len; - p = p->next; - } - return len; -} - -/** - * Increment the reference count of the pbuf. - * - * @param p pbuf to increase reference counter of - * - */ -void -pbuf_ref(struct pbuf *p) -{ - SYS_ARCH_DECL_PROTECT(old_level); - /* pbuf given? */ - if (p != NULL) { - SYS_ARCH_PROTECT(old_level); - ++(p->ref); - SYS_ARCH_UNPROTECT(old_level); - } -} - -/** - * Concatenate two pbufs (each may be a pbuf chain) and take over - * the caller's reference of the tail pbuf. - * - * @note The caller MAY NOT reference the tail pbuf afterwards. - * Use pbuf_chain() for that purpose. - * - * @see pbuf_chain() - */ - -void -pbuf_cat(struct pbuf *h, struct pbuf *t) -{ - struct pbuf *p; - - LWIP_ASSERT("h != NULL (programmer violates API)", h != NULL); - LWIP_ASSERT("t != NULL (programmer violates API)", t != NULL); - if ((h == NULL) || (t == NULL)) return; - - /* proceed to last pbuf of chain */ - for (p = h; p->next != NULL; p = p->next) { - /* add total length of second chain to all totals of first chain */ - p->tot_len += t->tot_len; - } - /* { p is last pbuf of first h chain, p->next == NULL } */ - LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len); - LWIP_ASSERT("p->next == NULL", p->next == NULL); - /* add total length of second chain to last pbuf total of first chain */ - p->tot_len += t->tot_len; - /* chain last pbuf of head (p) with first of tail (t) */ - p->next = t; - /* p->next now references t, but the caller will drop its reference to t, - * so netto there is no change to the reference count of t. - */ -} - -/** - * Chain two pbufs (or pbuf chains) together. - * - * The caller MUST call pbuf_free(t) once it has stopped - * using it. Use pbuf_cat() instead if you no longer use t. - * - * @param h head pbuf (chain) - * @param t tail pbuf (chain) - * @note The pbufs MUST belong to the same packet. - * @note MAY NOT be called on a packet queue. - * - * The ->tot_len fields of all pbufs of the head chain are adjusted. - * The ->next field of the last pbuf of the head chain is adjusted. - * The ->ref field of the first pbuf of the tail chain is adjusted. - * - */ -void -pbuf_chain(struct pbuf *h, struct pbuf *t) -{ - pbuf_cat(h, t); - /* t is now referenced by h */ - pbuf_ref(t); - LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t)); -} - -/* For packet queueing. Note that queued packets MUST be dequeued first - * using pbuf_dequeue() before calling other pbuf_() functions. */ -#if ARP_QUEUEING -/** - * Add a packet to the end of a queue. - * - * @param q pointer to first packet on the queue - * @param n packet to be queued - * - * Both packets MUST be given, and must be different. - */ -void -pbuf_queue(struct pbuf *p, struct pbuf *n) -{ -#if PBUF_DEBUG /* remember head of queue */ - struct pbuf *q = p; -#endif - /* programmer stupidity checks */ - LWIP_ASSERT("p == NULL in pbuf_queue: this indicates a programmer error\n", p != NULL); - LWIP_ASSERT("n == NULL in pbuf_queue: this indicates a programmer error\n", n != NULL); - LWIP_ASSERT("p == n in pbuf_queue: this indicates a programmer error\n", p != n); - if ((p == NULL) || (n == NULL) || (p == n)){ - LWIP_DEBUGF(PBUF_DEBUG | DBG_HALT | 3, ("pbuf_queue: programmer argument error\n")); - return; - } - - /* iterate through all packets on queue */ - while (p->next != NULL) { -/* be very picky about pbuf chain correctness */ -#if PBUF_DEBUG - /* iterate through all pbufs in packet */ - while (p->tot_len != p->len) { - /* make sure invariant condition holds */ - LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len); - /* make sure each packet is complete */ - LWIP_ASSERT("p->next != NULL", p->next != NULL); - p = p->next; - /* { p->tot_len == p->len => p is last pbuf of a packet } */ - } - /* { p is last pbuf of a packet } */ - /* proceed to next packet on queue */ -#endif - /* proceed to next pbuf */ - if (p->next != NULL) p = p->next; - } - /* { p->tot_len == p->len and p->next == NULL } ==> - * { p is last pbuf of last packet on queue } */ - /* chain last pbuf of queue with n */ - p->next = n; - /* n is now referenced to by the (packet p in the) queue */ - pbuf_ref(n); -#if PBUF_DEBUG - LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, - ("pbuf_queue: newly queued packet %p sits after packet %p in queue %p\n", - (void *)n, (void *)p, (void *)q)); -#endif -} - -/** - * Remove a packet from the head of a queue. - * - * The caller MUST reference the remainder of the queue (as returned). The - * caller MUST NOT call pbuf_ref() as it implicitly takes over the reference - * from p. - * - * @param p pointer to first packet on the queue which will be dequeued. - * @return first packet on the remaining queue (NULL if no further packets). - * - */ -struct pbuf * -pbuf_dequeue(struct pbuf *p) -{ - struct pbuf *q; - LWIP_ASSERT("p != NULL", p != NULL); - - /* iterate through all pbufs in packet p */ - while (p->tot_len != p->len) { - /* make sure invariant condition holds */ - LWIP_ASSERT("p->len < p->tot_len", p->len < p->tot_len); - /* make sure each packet is complete */ - LWIP_ASSERT("p->next != NULL", p->next != NULL); - p = p->next; - } - /* { p->tot_len == p->len } => p is the last pbuf of the first packet */ - /* remember next packet on queue in q */ - q = p->next; - /* dequeue packet p from queue */ - p->next = NULL; - /* any next packet on queue? */ - if (q != NULL) { - /* although q is no longer referenced by p, it MUST be referenced by - * the caller, who is maintaining this packet queue. So, we do not call - * pbuf_free(q) here, resulting in an implicit pbuf_ref(q) for the caller. */ - LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: first remaining packet on queue is %p\n", (void *)q)); - } else { - LWIP_DEBUGF(PBUF_DEBUG | DBG_FRESH | 2, ("pbuf_dequeue: no further packets on queue\n")); - } - return q; -} -#endif - -/** - * - * Create PBUF_POOL (or PBUF_RAM) copies of PBUF_REF pbufs. - * - * Used to queue packets on behalf of the lwIP stack, such as - * ARP based queueing. - * - * Go through a pbuf chain and replace any PBUF_REF buffers - * with PBUF_POOL (or PBUF_RAM) pbufs, each taking a copy of - * the referenced data. - * - * @note You MUST explicitly use p = pbuf_take(p); - * The pbuf you give as argument, may have been replaced - * by a (differently located) copy through pbuf_take()! - * - * @note Any replaced pbufs will be freed through pbuf_free(). - * This may deallocate them if they become no longer referenced. - * - * @param p Head of pbuf chain to process - * - * @return Pointer to head of pbuf chain - */ -struct pbuf * -pbuf_take(struct pbuf *p) -{ - struct pbuf *q , *prev, *head; - LWIP_ASSERT("pbuf_take: p != NULL\n", p != NULL); - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 3, ("pbuf_take(%p)\n", (void*)p)); - - prev = NULL; - head = p; - /* iterate through pbuf chain */ - do - { - /* pbuf is of type PBUF_REF? */ - if (p->flags == PBUF_FLAG_REF) { - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE, ("pbuf_take: encountered PBUF_REF %p\n", (void *)p)); - /* allocate a pbuf (w/ payload) fully in RAM */ - /* PBUF_POOL buffers are faster if we can use them */ - if (p->len <= PBUF_POOL_BUFSIZE) { - q = pbuf_alloc(PBUF_RAW, p->len, PBUF_POOL); - if (q == NULL) { - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_POOL\n")); - } - } else { - /* no replacement pbuf yet */ - q = NULL; - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: PBUF_POOL too small to replace PBUF_REF\n")); - } - /* no (large enough) PBUF_POOL was available? retry with PBUF_RAM */ - if (q == NULL) { - q = pbuf_alloc(PBUF_RAW, p->len, PBUF_RAM); - if (q == NULL) { - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 2, ("pbuf_take: Could not allocate PBUF_RAM\n")); - } - } - /* replacement pbuf could be allocated? */ - if (q != NULL) - { - /* copy p to q */ - /* copy successor */ - q->next = p->next; - /* remove linkage from original pbuf */ - p->next = NULL; - /* remove linkage to original pbuf */ - if (prev != NULL) { - /* prev->next == p at this point */ - LWIP_ASSERT("prev->next == p", prev->next == p); - /* break chain and insert new pbuf instead */ - prev->next = q; - /* prev == NULL, so we replaced the head pbuf of the chain */ - } else { - head = q; - } - /* copy pbuf payload */ - memcpy(q->payload, p->payload, p->len); - q->tot_len = p->tot_len; - q->len = p->len; - /* in case p was the first pbuf, it is no longer refered to by - * our caller, as the caller MUST do p = pbuf_take(p); - * in case p was not the first pbuf, it is no longer refered to - * by prev. we can safely free the pbuf here. - * (note that we have set p->next to NULL already so that - * we will not free the rest of the chain by accident.) - */ - pbuf_free(p); - /* do not copy ref, since someone else might be using the old buffer */ - LWIP_DEBUGF(PBUF_DEBUG, ("pbuf_take: replaced PBUF_REF %p with %p\n", (void *)p, (void *)q)); - p = q; - } else { - /* deallocate chain */ - pbuf_free(head); - LWIP_DEBUGF(PBUF_DEBUG | 2, ("pbuf_take: failed to allocate replacement pbuf for %p\n", (void *)p)); - return NULL; - } - /* p->flags != PBUF_FLAG_REF */ - } else { - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: skipping pbuf not of type PBUF_REF\n")); - } - /* remember this pbuf */ - prev = p; - /* proceed to next pbuf in original chain */ - p = p->next; - } while (p); - LWIP_DEBUGF(PBUF_DEBUG | DBG_TRACE | 1, ("pbuf_take: end of chain reached.\n")); - - return head; -} - -/** - * Dechains the first pbuf from its succeeding pbufs in the chain. - * - * Makes p->tot_len field equal to p->len. - * @param p pbuf to dechain - * @return remainder of the pbuf chain, or NULL if it was de-allocated. - * @note May not be called on a packet queue. - */ -struct pbuf * -pbuf_dechain(struct pbuf *p) -{ - struct pbuf *q; - u8_t tail_gone = 1; - /* tail */ - q = p->next; - /* pbuf has successor in chain? */ - if (q != NULL) { - /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ - LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len); - /* enforce invariant if assertion is disabled */ - q->tot_len = p->tot_len - p->len; - /* decouple pbuf from remainder */ - p->next = NULL; - /* total length of pbuf p is its own length only */ - p->tot_len = p->len; - /* q is no longer referenced by p, free it */ - LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, ("pbuf_dechain: unreferencing %p\n", (void *)q)); - tail_gone = pbuf_free(q); - if (tail_gone > 0) { - LWIP_DEBUGF(PBUF_DEBUG | DBG_STATE, - ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q)); - } - /* return remaining tail or NULL if deallocated */ - } - /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ - LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len); - return (tail_gone > 0? NULL: q); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/raw.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/raw.c deleted file mode 100644 index 30199804d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/raw.c +++ /dev/null @@ -1,326 +0,0 @@ -/** - * @file - * - * Implementation of raw protocol PCBs for low-level handling of - * different types of protocols besides (or overriding) those - * already available in lwIP. - * - */ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/memp.h" -#include "lwip/inet.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/raw.h" - -#include "lwip/stats.h" - -#include "arch/perf.h" -#include "lwip/snmp.h" - -#if LWIP_RAW - -/** The list of RAW PCBs */ -static struct raw_pcb *raw_pcbs = NULL; - -void -raw_init(void) -{ - raw_pcbs = NULL; -} - -/** - * Determine if in incoming IP packet is covered by a RAW PCB - * and if so, pass it to a user-provided receive callback function. - * - * Given an incoming IP datagram (as a chain of pbufs) this function - * finds a corresponding RAW PCB and calls the corresponding receive - * callback function. - * - * @param pbuf pbuf to be demultiplexed to a RAW PCB. - * @param netif network interface on which the datagram was received. - * @Return - 1 if the packet has been eaten by a RAW PCB receive - * callback function. The caller MAY NOT not reference the - * packet any longer, and MAY NOT call pbuf_free(). - * @return - 0 if packet is not eaten (pbuf is still referenced by the - * caller). - * - */ -u8_t -raw_input(struct pbuf *p, struct netif *inp) -{ - struct raw_pcb *pcb; - struct ip_hdr *iphdr; - s16_t proto; - u8_t eaten = 0; - - iphdr = p->payload; - proto = IPH_PROTO(iphdr); - - pcb = raw_pcbs; - /* loop through all raw pcbs until the packet is eaten by one */ - /* this allows multiple pcbs to match against the packet by design */ - while ((eaten == 0) && (pcb != NULL)) { - if (pcb->protocol == proto) { - /* receive callback function available? */ - if (pcb->recv != NULL) { - /* the receive callback function did not eat the packet? */ - if (pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src)) != 0) - { - /* receive function ate the packet */ - p = NULL; - eaten = 1; - } - } - /* no receive callback function was set for this raw PCB */ - /* drop the packet */ - } - pcb = pcb->next; - } - return eaten; -} - -/** - * Bind a RAW PCB. - * - * @param pcb RAW PCB to be bound with a local address ipaddr. - * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to - * bind to all local interfaces. - * - * @return lwIP error code. - * - ERR_OK. Successful. No error occured. - * - ERR_USE. The specified IP address is already bound to by - * another RAW PCB. - * - * @see raw_disconnect() - */ -err_t -raw_bind(struct raw_pcb *pcb, struct ip_addr *ipaddr) -{ - ip_addr_set(&pcb->local_ip, ipaddr); - return ERR_OK; -} - -/** - * Connect an RAW PCB. This function is required by upper layers - * of lwip. Using the raw api you could use raw_sendto() instead - * - * This will associate the RAW PCB with the remote address. - * - * @param pcb RAW PCB to be connected with remote address ipaddr and port. - * @param ipaddr remote IP address to connect with. - * - * @return lwIP error code - * - * @see raw_disconnect() and raw_sendto() - */ -err_t -raw_connect(struct raw_pcb *pcb, struct ip_addr *ipaddr) -{ - ip_addr_set(&pcb->remote_ip, ipaddr); - return ERR_OK; -} - - -/** - * Set the callback function for received packets that match the - * raw PCB's protocol and binding. - * - * The callback function MUST either - * - eat the packet by calling pbuf_free() and returning non-zero. The - * packet will not be passed to other raw PCBs or other protocol layers. - * - not free the packet, and return zero. The packet will be matched - * against further PCBs and/or forwarded to another protocol layers. - * - * @return non-zero if the packet was free()d, zero if the packet remains - * available for others. - */ -void -raw_recv(struct raw_pcb *pcb, - u8_t (* recv)(void *arg, struct raw_pcb *upcb, struct pbuf *p, - struct ip_addr *addr), - void *recv_arg) -{ - /* remember recv() callback and user data */ - pcb->recv = recv; - pcb->recv_arg = recv_arg; -} - -/** - * Send the raw IP packet to the given address. Note that actually you cannot - * modify the IP headers (this is inconsistent with the receive callback where - * you actually get the IP headers), you can only specify the IP payload here. - * It requires some more changes in lwIP. (there will be a raw_send() function - * then.) - * - * @param pcb the raw pcb which to send - * @param p the IP payload to send - * @param ipaddr the destination address of the IP packet - * - */ -err_t -raw_sendto(struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr) -{ - err_t err; - struct netif *netif; - struct ip_addr *src_ip; - struct pbuf *q; /* q will be sent down the stack */ - - LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_sendto\n")); - - /* not enough space to add an IP header to first pbuf in given p chain? */ - if (pbuf_header(p, IP_HLEN)) { - /* allocate header in new pbuf */ - q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM); - /* new header pbuf could not be allocated? */ - if (q == NULL) { - LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 2, ("raw_sendto: could not allocate header\n")); - return ERR_MEM; - } - /* chain header q in front of given pbuf p */ - pbuf_chain(q, p); - /* { first pbuf q points to header pbuf } */ - LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); - } else { - /* first pbuf q equals given pbuf */ - q = p; - pbuf_header(q, -IP_HLEN); - } - - if ((netif = ip_route(ipaddr)) == NULL) { - LWIP_DEBUGF(RAW_DEBUG | 1, ("raw_sendto: No route to 0x%"X32_F"\n", ipaddr->addr)); -#if RAW_STATS - /* ++lwip_stats.raw.rterr;*/ -#endif /* RAW_STATS */ - /* free any temporary header pbuf allocated by pbuf_header() */ - if (q != p) { - pbuf_free(q); - } - return ERR_RTE; - } - - if (ip_addr_isany(&pcb->local_ip)) { - /* use outgoing network interface IP address as source address */ - src_ip = &(netif->ip_addr); - } else { - /* use RAW PCB local IP address as source address */ - src_ip = &(pcb->local_ip); - } - - err = ip_output_if (q, src_ip, ipaddr, pcb->ttl, pcb->tos, pcb->protocol, netif); - - /* did we chain a header earlier? */ - if (q != p) { - /* free the header */ - pbuf_free(q); - } - return err; -} - -/** - * Send the raw IP packet to the address given by raw_connect() - * - * @param pcb the raw pcb which to send - * @param p the IP payload to send - * @param ipaddr the destination address of the IP packet - * - */ -err_t -raw_send(struct raw_pcb *pcb, struct pbuf *p) -{ - return raw_sendto(pcb, p, &pcb->remote_ip); -} - -/** - * Remove an RAW PCB. - * - * @param pcb RAW PCB to be removed. The PCB is removed from the list of - * RAW PCB's and the data structure is freed from memory. - * - * @see raw_new() - */ -void -raw_remove(struct raw_pcb *pcb) -{ - struct raw_pcb *pcb2; - /* pcb to be removed is first in list? */ - if (raw_pcbs == pcb) { - /* make list start at 2nd pcb */ - raw_pcbs = raw_pcbs->next; - /* pcb not 1st in list */ - } else for(pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { - /* find pcb in raw_pcbs list */ - if (pcb2->next != NULL && pcb2->next == pcb) { - /* remove pcb from list */ - pcb2->next = pcb->next; - } - } - memp_free(MEMP_RAW_PCB, pcb); -} - -/** - * Create a RAW PCB. - * - * @return The RAW PCB which was created. NULL if the PCB data structure - * could not be allocated. - * - * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP) - * - * @see raw_remove() - */ -struct raw_pcb * -raw_new(u16_t proto) { - struct raw_pcb *pcb; - - LWIP_DEBUGF(RAW_DEBUG | DBG_TRACE | 3, ("raw_new\n")); - - pcb = memp_malloc(MEMP_RAW_PCB); - /* could allocate RAW PCB? */ - if (pcb != NULL) { - /* initialize PCB to all zeroes */ - memset(pcb, 0, sizeof(struct raw_pcb)); - pcb->protocol = proto; - pcb->ttl = RAW_TTL; - pcb->next = raw_pcbs; - raw_pcbs = pcb; - } - return pcb; -} - -#endif /* LWIP_RAW */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/stats.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/stats.c deleted file mode 100644 index c94623f7a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/stats.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include - -#include "lwip/opt.h" - -#include "lwip/def.h" - -#include "lwip/stats.h" -#include "lwip/mem.h" - - -#if LWIP_STATS -struct stats_ lwip_stats; - -void -stats_init(void) -{ - memset(&lwip_stats, 0, sizeof(struct stats_)); -} -#if LWIP_STATS_DISPLAY -void -stats_display_proto(struct stats_proto *proto, char *name) -{ - LWIP_PLATFORM_DIAG(("\n%s\n\t", name)); - LWIP_PLATFORM_DIAG(("xmit: %"S16_F"\n\t", proto->xmit)); - LWIP_PLATFORM_DIAG(("rexmit: %"S16_F"\n\t", proto->rexmit)); - LWIP_PLATFORM_DIAG(("recv: %"S16_F"\n\t", proto->recv)); - LWIP_PLATFORM_DIAG(("fw: %"S16_F"\n\t", proto->fw)); - LWIP_PLATFORM_DIAG(("drop: %"S16_F"\n\t", proto->drop)); - LWIP_PLATFORM_DIAG(("chkerr: %"S16_F"\n\t", proto->chkerr)); - LWIP_PLATFORM_DIAG(("lenerr: %"S16_F"\n\t", proto->lenerr)); - LWIP_PLATFORM_DIAG(("memerr: %"S16_F"\n\t", proto->memerr)); - LWIP_PLATFORM_DIAG(("rterr: %"S16_F"\n\t", proto->rterr)); - LWIP_PLATFORM_DIAG(("proterr: %"S16_F"\n\t", proto->proterr)); - LWIP_PLATFORM_DIAG(("opterr: %"S16_F"\n\t", proto->opterr)); - LWIP_PLATFORM_DIAG(("err: %"S16_F"\n\t", proto->err)); - LWIP_PLATFORM_DIAG(("cachehit: %"S16_F"\n", proto->cachehit)); -} - -void -stats_display_pbuf(struct stats_pbuf *pbuf) -{ - LWIP_PLATFORM_DIAG(("\nPBUF\n\t")); - LWIP_PLATFORM_DIAG(("avail: %"S16_F"\n\t", pbuf->avail)); - LWIP_PLATFORM_DIAG(("used: %"S16_F"\n\t", pbuf->used)); - LWIP_PLATFORM_DIAG(("max: %"S16_F"\n\t", pbuf->max)); - LWIP_PLATFORM_DIAG(("err: %"S16_F"\n\t", pbuf->err)); - LWIP_PLATFORM_DIAG(("alloc_locked: %"S16_F"\n\t", pbuf->alloc_locked)); - LWIP_PLATFORM_DIAG(("refresh_locked: %"S16_F"\n", pbuf->refresh_locked)); -} - -void -stats_display_mem(struct stats_mem *mem, char *name) -{ - LWIP_PLATFORM_DIAG(("\n MEM %s\n\t", name)); - LWIP_PLATFORM_DIAG(("avail: %"S16_F"\n\t", mem->avail)); - LWIP_PLATFORM_DIAG(("used: %"S16_F"\n\t", mem->used)); - LWIP_PLATFORM_DIAG(("max: %"S16_F"\n\t", mem->max)); - LWIP_PLATFORM_DIAG(("err: %"S16_F"\n", mem->err)); - -} - -void -stats_display(void) -{ - s16_t i; - char * memp_names[] = {"PBUF", "RAW_PCB", "UDP_PCB", "TCP_PCB", "TCP_PCB_LISTEN", - "TCP_SEG", "NETBUF", "NETCONN", "API_MSG", "TCP_MSG", "TIMEOUT"}; - stats_display_proto(&lwip_stats.link, "LINK"); - stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG"); - stats_display_proto(&lwip_stats.ip, "IP"); - stats_display_proto(&lwip_stats.icmp, "ICMP"); - stats_display_proto(&lwip_stats.udp, "UDP"); - stats_display_proto(&lwip_stats.tcp, "TCP"); - stats_display_pbuf(&lwip_stats.pbuf); - stats_display_mem(&lwip_stats.mem, "HEAP"); - for (i = 0; i < MEMP_MAX; i++) { - stats_display_mem(&lwip_stats.memp[i], memp_names[i]); - } - -} -#endif /* LWIP_STATS_DISPLAY */ -#endif /* LWIP_STATS */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/sys.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/sys.c deleted file mode 100644 index a7dbf34da..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/sys.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/sys.h" -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/memp.h" - -#if (NO_SYS == 0) - -struct sswt_cb -{ - s16_t timeflag; - sys_sem_t *psem; -}; - - - -void -sys_mbox_fetch(sys_mbox_t mbox, void **msg) -{ - u32_t time; - struct sys_timeouts *timeouts; - struct sys_timeout *tmptimeout; - sys_timeout_handler h; - void *arg; - - - again: - timeouts = sys_arch_timeouts(); - - if (!timeouts || !timeouts->next) { - sys_arch_mbox_fetch(mbox, msg, 0); - } else { - if (timeouts->next->time > 0) { - time = sys_arch_mbox_fetch(mbox, msg, timeouts->next->time); - } else { - time = SYS_ARCH_TIMEOUT; - } - - if (time == SYS_ARCH_TIMEOUT) { - /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message - could be fetched. We should now call the timeout handler and - deallocate the memory allocated for the timeout. */ - tmptimeout = timeouts->next; - timeouts->next = tmptimeout->next; - h = tmptimeout->h; - arg = tmptimeout->arg; - memp_free(MEMP_SYS_TIMEOUT, tmptimeout); - if (h != NULL) { - LWIP_DEBUGF(SYS_DEBUG, ("smf calling h=%p(%p)\n", (void *)h, (void *)arg)); - h(arg); - } - - /* We try again to fetch a message from the mbox. */ - goto again; - } else { - /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout - occured. The time variable is set to the number of - milliseconds we waited for the message. */ - if (time <= timeouts->next->time) { - timeouts->next->time -= time; - } else { - timeouts->next->time = 0; - } - } - - } -} - -void -sys_sem_wait(sys_sem_t sem) -{ - u32_t time; - struct sys_timeouts *timeouts; - struct sys_timeout *tmptimeout; - sys_timeout_handler h; - void *arg; - - /* while (sys_arch_sem_wait(sem, 1000) == 0); - return;*/ - - again: - - timeouts = sys_arch_timeouts(); - - if (!timeouts || !timeouts->next) { - sys_arch_sem_wait(sem, 0); - } else { - if (timeouts->next->time > 0) { - time = sys_arch_sem_wait(sem, timeouts->next->time); - } else { - time = SYS_ARCH_TIMEOUT; - } - - if (time == SYS_ARCH_TIMEOUT) { - /* If time == SYS_ARCH_TIMEOUT, a timeout occured before a message - could be fetched. We should now call the timeout handler and - deallocate the memory allocated for the timeout. */ - tmptimeout = timeouts->next; - timeouts->next = tmptimeout->next; - h = tmptimeout->h; - arg = tmptimeout->arg; - memp_free(MEMP_SYS_TIMEOUT, tmptimeout); - if (h != NULL) { - LWIP_DEBUGF(SYS_DEBUG, ("ssw h=%p(%p)\n", (void *)h, (void *)arg)); - h(arg); - } - - - /* We try again to fetch a message from the mbox. */ - goto again; - } else { - /* If time != SYS_ARCH_TIMEOUT, a message was received before the timeout - occured. The time variable is set to the number of - milliseconds we waited for the message. */ - if (time <= timeouts->next->time) { - timeouts->next->time -= time; - } else { - timeouts->next->time = 0; - } - } - - } -} - -void -sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg) -{ - struct sys_timeouts *timeouts; - struct sys_timeout *timeout, *t; - - timeout = memp_malloc(MEMP_SYS_TIMEOUT); - if (timeout == NULL) { - return; - } - timeout->next = NULL; - timeout->h = h; - timeout->arg = arg; - timeout->time = msecs; - - timeouts = sys_arch_timeouts(); - - LWIP_DEBUGF(SYS_DEBUG, ("sys_timeout: %p msecs=%"U32_F" h=%p arg=%p\n", - (void *)timeout, msecs, (void *)h, (void *)arg)); - - LWIP_ASSERT("sys_timeout: timeouts != NULL", timeouts != NULL); - - if (timeouts->next == NULL) { - timeouts->next = timeout; - return; - } - - if (timeouts->next->time > msecs) { - timeouts->next->time -= msecs; - timeout->next = timeouts->next; - timeouts->next = timeout; - } else { - for(t = timeouts->next; t != NULL; t = t->next) { - timeout->time -= t->time; - if (t->next == NULL || t->next->time > timeout->time) { - if (t->next != NULL) { - t->next->time -= timeout->time; - } - timeout->next = t->next; - t->next = timeout; - break; - } - } - } - -} - -/* Go through timeout list (for this task only) and remove the first matching entry, - even though the timeout has not triggered yet. -*/ - -void -sys_untimeout(sys_timeout_handler h, void *arg) -{ - struct sys_timeouts *timeouts; - struct sys_timeout *prev_t, *t; - - timeouts = sys_arch_timeouts(); - - if (timeouts->next == NULL) - return; - - for (t = timeouts->next, prev_t = NULL; t != NULL; prev_t = t, t = t->next) - { - if ((t->h == h) && (t->arg == arg)) - { - /* We have a match */ - /* Unlink from previous in list */ - if (prev_t == NULL) - timeouts->next = t->next; - else - prev_t->next = t->next; - /* If not the last one, add time of this one back to next */ - if (t->next != NULL) - t->next->time += t->time; - memp_free(MEMP_SYS_TIMEOUT, t); - return; - } - } - return; -} - - - - - -static void -sswt_handler(void *arg) -{ - struct sswt_cb *sswt_cb = (struct sswt_cb *) arg; - - /* Timeout. Set flag to TRUE and signal semaphore */ - sswt_cb->timeflag = 1; - sys_sem_signal(*(sswt_cb->psem)); -} - -/* Wait for a semaphore with timeout (specified in ms) */ -/* timeout = 0: wait forever */ -/* Returns 0 on timeout. 1 otherwise */ - -int -sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout) -{ - struct sswt_cb sswt_cb; - - sswt_cb.psem = &sem; - sswt_cb.timeflag = 0; - - /* If timeout is zero, then just wait forever */ - if (timeout > 0) - /* Create a timer and pass it the address of our flag */ - sys_timeout(timeout, sswt_handler, &sswt_cb); - sys_sem_wait(sem); - /* Was it a timeout? */ - if (sswt_cb.timeflag) - { - /* timeout */ - return 0; - } else { - /* Not a timeout. Remove timeout entry */ - sys_untimeout(sswt_handler, &sswt_cb); - return 1; - } - -} - - -void -sys_msleep(u32_t ms) -{ - sys_sem_t delaysem = sys_sem_new(0); - - sys_sem_wait_timeout(delaysem, ms); - - sys_sem_free(delaysem); -} - - -#endif /* NO_SYS */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/tcp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/tcp.c deleted file mode 100644 index 41a9edb4e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/tcp.c +++ /dev/null @@ -1,1171 +0,0 @@ -/** - * @file - * - * Transmission Control Protocol for IP - * - * This file contains common functions for the TCP implementation, such as functinos - * for manipulating the data structures and the TCP timer functions. TCP functions - * related to input and output is found in tcp_in.c and tcp_out.c respectively. - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include - -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/memp.h" - -#include "lwip/tcp.h" -#if LWIP_TCP - -/* Incremented every coarse grained timer shot - (typically every 500 ms, determined by TCP_COARSE_TIMEOUT). */ -u32_t tcp_ticks; -const u8_t tcp_backoff[13] = - { 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7}; - -/* The TCP PCB lists. */ - -/** List of all TCP PCBs in LISTEN state */ -union tcp_listen_pcbs_t tcp_listen_pcbs; -/** List of all TCP PCBs that are in a state in which - * they accept or send data. */ -struct tcp_pcb *tcp_active_pcbs; -/** List of all TCP PCBs in TIME-WAIT state */ -struct tcp_pcb *tcp_tw_pcbs; - -struct tcp_pcb *tcp_tmp_pcb; - -static u8_t tcp_timer; -static u16_t tcp_new_port(void); - -/** - * Initializes the TCP layer. - */ -void -tcp_init(void) -{ - /* Clear globals. */ - tcp_listen_pcbs.listen_pcbs = NULL; - tcp_active_pcbs = NULL; - tcp_tw_pcbs = NULL; - tcp_tmp_pcb = NULL; - - /* initialize timer */ - tcp_ticks = 0; - tcp_timer = 0; - -} - -/** - * Called periodically to dispatch TCP timers. - * - */ -void -tcp_tmr(void) -{ - /* Call tcp_fasttmr() every 250 ms */ - tcp_fasttmr(); - - if (++tcp_timer & 1) { - /* Call tcp_tmr() every 500 ms, i.e., every other timer - tcp_tmr() is called. */ - tcp_slowtmr(); - } -} - -/** - * Closes the connection held by the PCB. - * - */ -err_t -tcp_close(struct tcp_pcb *pcb) -{ - err_t err; - -#if TCP_DEBUG - LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in state ")); - tcp_debug_print_state(pcb->state); - LWIP_DEBUGF(TCP_DEBUG, ("\n")); -#endif /* TCP_DEBUG */ - switch (pcb->state) { - case CLOSED: - /* Closing a pcb in the CLOSED state might seem erroneous, - * however, it is in this state once allocated and as yet unused - * and the user needs some way to free it should the need arise. - * Calling tcp_close() with a pcb that has already been closed, (i.e. twice) - * or for a pcb that has been used and then entered the CLOSED state - * is erroneous, but this should never happen as the pcb has in those cases - * been freed, and so any remaining handles are bogus. */ - err = ERR_OK; - memp_free(MEMP_TCP_PCB, pcb); - pcb = NULL; - break; - case LISTEN: - err = ERR_OK; - tcp_pcb_remove((struct tcp_pcb **)&tcp_listen_pcbs.pcbs, pcb); - memp_free(MEMP_TCP_PCB_LISTEN, pcb); - pcb = NULL; - break; - case SYN_SENT: - err = ERR_OK; - tcp_pcb_remove(&tcp_active_pcbs, pcb); - memp_free(MEMP_TCP_PCB, pcb); - pcb = NULL; - break; - case SYN_RCVD: - case ESTABLISHED: - err = tcp_send_ctrl(pcb, TCP_FIN); - if (err == ERR_OK) { - pcb->state = FIN_WAIT_1; - } - break; - case CLOSE_WAIT: - err = tcp_send_ctrl(pcb, TCP_FIN); - if (err == ERR_OK) { - pcb->state = LAST_ACK; - } - break; - default: - /* Has already been closed, do nothing. */ - err = ERR_OK; - pcb = NULL; - break; - } - - if (pcb != NULL && err == ERR_OK) { - err = tcp_output(pcb); - } - return err; -} - -/** - * Aborts a connection by sending a RST to the remote host and deletes - * the local protocol control block. This is done when a connection is - * killed because of shortage of memory. - * - */ -void -tcp_abort(struct tcp_pcb *pcb) -{ - u32_t seqno, ackno; - u16_t remote_port, local_port; - struct ip_addr remote_ip, local_ip; -#if LWIP_CALLBACK_API - void (* errf)(void *arg, err_t err); -#endif /* LWIP_CALLBACK_API */ - void *errf_arg; - - - /* Figure out on which TCP PCB list we are, and remove us. If we - are in an active state, call the receive function associated with - the PCB with a NULL argument, and send an RST to the remote end. */ - if (pcb->state == TIME_WAIT) { - tcp_pcb_remove(&tcp_tw_pcbs, pcb); - memp_free(MEMP_TCP_PCB, pcb); - } else { - seqno = pcb->snd_nxt; - ackno = pcb->rcv_nxt; - ip_addr_set(&local_ip, &(pcb->local_ip)); - ip_addr_set(&remote_ip, &(pcb->remote_ip)); - local_port = pcb->local_port; - remote_port = pcb->remote_port; -#if LWIP_CALLBACK_API - errf = pcb->errf; -#endif /* LWIP_CALLBACK_API */ - errf_arg = pcb->callback_arg; - tcp_pcb_remove(&tcp_active_pcbs, pcb); - if (pcb->unacked != NULL) { - tcp_segs_free(pcb->unacked); - } - if (pcb->unsent != NULL) { - tcp_segs_free(pcb->unsent); - } -#if TCP_QUEUE_OOSEQ - if (pcb->ooseq != NULL) { - tcp_segs_free(pcb->ooseq); - } -#endif /* TCP_QUEUE_OOSEQ */ - memp_free(MEMP_TCP_PCB, pcb); - TCP_EVENT_ERR(errf, errf_arg, ERR_ABRT); - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abort: sending RST\n")); - tcp_rst(seqno, ackno, &local_ip, &remote_ip, local_port, remote_port); - } -} - -/** - * Binds the connection to a local portnumber and IP address. If the - * IP address is not given (i.e., ipaddr == NULL), the IP address of - * the outgoing network interface is used instead. - * - */ - -err_t -tcp_bind(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) -{ - struct tcp_pcb *cpcb; - - if (port == 0) { - port = tcp_new_port(); - } - /* Check if the address already is in use. */ - for(cpcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; - cpcb != NULL; cpcb = cpcb->next) { - if (cpcb->local_port == port) { - if (ip_addr_isany(&(cpcb->local_ip)) || - ip_addr_isany(ipaddr) || - ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { - return ERR_USE; - } - } - } - for(cpcb = tcp_active_pcbs; - cpcb != NULL; cpcb = cpcb->next) { - if (cpcb->local_port == port) { - if (ip_addr_isany(&(cpcb->local_ip)) || - ip_addr_isany(ipaddr) || - ip_addr_cmp(&(cpcb->local_ip), ipaddr)) { - return ERR_USE; - } - } - } - - if (!ip_addr_isany(ipaddr)) { - pcb->local_ip = *ipaddr; - } - pcb->local_port = port; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port)); - return ERR_OK; -} -#if LWIP_CALLBACK_API -static err_t -tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err) -{ - (void)arg; - (void)pcb; - (void)err; - - return ERR_ABRT; -} -#endif /* LWIP_CALLBACK_API */ - -/** - * Set the state of the connection to be LISTEN, which means that it - * is able to accept incoming connections. The protocol control block - * is reallocated in order to consume less memory. Setting the - * connection to LISTEN is an irreversible process. - * - */ -struct tcp_pcb * -tcp_listen(struct tcp_pcb *pcb) -{ - struct tcp_pcb_listen *lpcb; - - /* already listening? */ - if (pcb->state == LISTEN) { - return pcb; - } - lpcb = memp_malloc(MEMP_TCP_PCB_LISTEN); - if (lpcb == NULL) { - return NULL; - } - lpcb->callback_arg = pcb->callback_arg; - lpcb->local_port = pcb->local_port; - lpcb->state = LISTEN; - lpcb->so_options = pcb->so_options; - lpcb->so_options |= SOF_ACCEPTCONN; - lpcb->ttl = pcb->ttl; - lpcb->tos = pcb->tos; - ip_addr_set(&lpcb->local_ip, &pcb->local_ip); - memp_free(MEMP_TCP_PCB, pcb); -#if LWIP_CALLBACK_API - lpcb->accept = tcp_accept_null; -#endif /* LWIP_CALLBACK_API */ - TCP_REG(&tcp_listen_pcbs.listen_pcbs, lpcb); - return (struct tcp_pcb *)lpcb; -} - -/** - * This function should be called by the application when it has - * processed the data. The purpose is to advertise a larger window - * when the data has been processed. - * - */ -void -tcp_recved(struct tcp_pcb *pcb, u16_t len) -{ - if ((u32_t)pcb->rcv_wnd + len > TCP_WND) { - pcb->rcv_wnd = TCP_WND; - } else { - pcb->rcv_wnd += len; - } - if (!(pcb->flags & TF_ACK_DELAY) && - !(pcb->flags & TF_ACK_NOW)) { - /* - * We send an ACK here (if one is not already pending, hence - * the above tests) as tcp_recved() implies that the application - * has processed some data, and so we can open the receiver's - * window to allow more to be transmitted. This could result in - * two ACKs being sent for each received packet in some limited cases - * (where the application is only receiving data, and is slow to - * process it) but it is necessary to guarantee that the sender can - * continue to transmit. - */ - tcp_ack(pcb); - } - else if (pcb->flags & TF_ACK_DELAY && pcb->rcv_wnd >= TCP_WND/2) { - /* If we can send a window update such that there is a full - * segment available in the window, do so now. This is sort of - * nagle-like in its goals, and tries to hit a compromise between - * sending acks each time the window is updated, and only sending - * window updates when a timer expires. The "threshold" used - * above (currently TCP_WND/2) can be tuned to be more or less - * aggressive */ - tcp_ack_now(pcb); - } - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: recveived %"U16_F" bytes, wnd %"U16_F" (%"U16_F").\n", - len, pcb->rcv_wnd, TCP_WND - pcb->rcv_wnd)); -} - -/** - * A nastly hack featuring 'goto' statements that allocates a - * new TCP local port. - */ -static u16_t -tcp_new_port(void) -{ - struct tcp_pcb *pcb; -#ifndef TCP_LOCAL_PORT_RANGE_START -#define TCP_LOCAL_PORT_RANGE_START 4096 -#define TCP_LOCAL_PORT_RANGE_END 0x7fff -#endif - static u16_t port = TCP_LOCAL_PORT_RANGE_START; - - again: - if (++port > TCP_LOCAL_PORT_RANGE_END) { - port = TCP_LOCAL_PORT_RANGE_START; - } - - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->local_port == port) { - goto again; - } - } - for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->local_port == port) { - goto again; - } - } - for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->local_port == port) { - goto again; - } - } - return port; -} - -/** - * Connects to another host. The function given as the "connected" - * argument will be called when the connection has been established. - * - */ -err_t -tcp_connect(struct tcp_pcb *pcb, struct ip_addr *ipaddr, u16_t port, - err_t (* connected)(void *arg, struct tcp_pcb *tpcb, err_t err)) -{ - u32_t optdata; - err_t ret; - u32_t iss; - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port)); - if (ipaddr != NULL) { - pcb->remote_ip = *ipaddr; - } else { - return ERR_VAL; - } - pcb->remote_port = port; - if (pcb->local_port == 0) { - pcb->local_port = tcp_new_port(); - } - iss = tcp_next_iss(); - pcb->rcv_nxt = 0; - pcb->snd_nxt = iss; - pcb->lastack = iss - 1; - pcb->snd_lbb = iss - 1; - pcb->rcv_wnd = TCP_WND; - pcb->snd_wnd = TCP_WND; - pcb->mss = TCP_MSS; - pcb->cwnd = 1; - pcb->ssthresh = pcb->mss * 10; - pcb->state = SYN_SENT; -#if LWIP_CALLBACK_API - pcb->connected = connected; -#endif /* LWIP_CALLBACK_API */ - TCP_REG(&tcp_active_pcbs, pcb); - - /* Build an MSS option */ - optdata = htonl(((u32_t)2 << 24) | - ((u32_t)4 << 16) | - (((u32_t)pcb->mss / 256) << 8) | - (pcb->mss & 255)); - - ret = tcp_enqueue(pcb, NULL, 0, TCP_SYN, 0, (u8_t *)&optdata, 4); - if (ret == ERR_OK) { - tcp_output(pcb); - } - return ret; -} - -/** - * Called every 500 ms and implements the retransmission timer and the timer that - * removes PCBs that have been in TIME-WAIT for enough time. It also increments - * various timers such as the inactivity timer in each PCB. - */ -void -tcp_slowtmr(void) -{ - struct tcp_pcb *pcb, *pcb2, *prev; - u32_t eff_wnd; - u8_t pcb_remove; /* flag if a PCB should be removed */ - err_t err; - - err = ERR_OK; - - ++tcp_ticks; - - /* Steps through all of the active PCBs. */ - prev = NULL; - pcb = tcp_active_pcbs; - if (pcb == NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n")); - } - while (pcb != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n")); - LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED); - LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN); - LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT); - - pcb_remove = 0; - - if (pcb->state == SYN_SENT && pcb->nrtx == TCP_SYNMAXRTX) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n")); - } - else if (pcb->nrtx == TCP_MAXRTX) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n")); - } else { - ++pcb->rtime; - if (pcb->unacked != NULL && pcb->rtime >= pcb->rto) { - - /* Time for a retransmission. */ - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %"U16_F" pcb->rto %"U16_F"\n", - pcb->rtime, pcb->rto)); - - /* Double retransmission time-out unless we are trying to - * connect to somebody (i.e., we are in SYN_SENT). */ - if (pcb->state != SYN_SENT) { - pcb->rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[pcb->nrtx]; - } - /* Reduce congestion window and ssthresh. */ - eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd); - pcb->ssthresh = eff_wnd >> 1; - if (pcb->ssthresh < pcb->mss) { - pcb->ssthresh = pcb->mss * 2; - } - pcb->cwnd = pcb->mss; - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"U16_F" ssthresh %"U16_F"\n", - pcb->cwnd, pcb->ssthresh)); - - /* The following needs to be called AFTER cwnd is set to one mss - STJ */ - tcp_rexmit_rto(pcb); - } - } - /* Check if this PCB has stayed too long in FIN-WAIT-2 */ - if (pcb->state == FIN_WAIT_2) { - if ((u32_t)(tcp_ticks - pcb->tmr) > - TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n")); - } - } - - /* Check if KEEPALIVE should be sent */ - if((pcb->so_options & SOF_KEEPALIVE) && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) { - if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + TCP_MAXIDLE) / TCP_SLOW_INTERVAL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to %"U16_F".%"U16_F".%"U16_F".%"U16_F".\n", - ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), - ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip))); - - tcp_abort(pcb); - } - else if((u32_t)(tcp_ticks - pcb->tmr) > (pcb->keepalive + pcb->keep_cnt * TCP_KEEPINTVL) / TCP_SLOW_INTERVAL) { - tcp_keepalive(pcb); - pcb->keep_cnt++; - } - } - - /* If this PCB has queued out of sequence data, but has been - inactive for too long, will drop the data (it will eventually - be retransmitted). */ -#if TCP_QUEUE_OOSEQ - if (pcb->ooseq != NULL && - (u32_t)tcp_ticks - pcb->tmr >= - pcb->rto * TCP_OOSEQ_TIMEOUT) { - tcp_segs_free(pcb->ooseq); - pcb->ooseq = NULL; - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n")); - } -#endif /* TCP_QUEUE_OOSEQ */ - - /* Check if this PCB has stayed too long in SYN-RCVD */ - if (pcb->state == SYN_RCVD) { - if ((u32_t)(tcp_ticks - pcb->tmr) > - TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n")); - } - } - - /* Check if this PCB has stayed too long in LAST-ACK */ - if (pcb->state == LAST_ACK) { - if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { - ++pcb_remove; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n")); - } - } - - /* If the PCB should be removed, do it. */ - if (pcb_remove) { - tcp_pcb_purge(pcb); - /* Remove PCB from tcp_active_pcbs list. */ - if (prev != NULL) { - LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs); - prev->next = pcb->next; - } else { - /* This PCB was the first. */ - LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb); - tcp_active_pcbs = pcb->next; - } - - TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_ABRT); - - pcb2 = pcb->next; - memp_free(MEMP_TCP_PCB, pcb); - pcb = pcb2; - } else { - - /* We check if we should poll the connection. */ - ++pcb->polltmr; - if (pcb->polltmr >= pcb->pollinterval) { - pcb->polltmr = 0; - LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n")); - TCP_EVENT_POLL(pcb, err); - if (err == ERR_OK) { - tcp_output(pcb); - } - } - - prev = pcb; - pcb = pcb->next; - } - } - - - /* Steps through all of the TIME-WAIT PCBs. */ - prev = NULL; - pcb = tcp_tw_pcbs; - while (pcb != NULL) { - LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); - pcb_remove = 0; - - /* Check if this PCB has stayed long enough in TIME-WAIT */ - if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { - ++pcb_remove; - } - - - - /* If the PCB should be removed, do it. */ - if (pcb_remove) { - tcp_pcb_purge(pcb); - /* Remove PCB from tcp_tw_pcbs list. */ - if (prev != NULL) { - LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs); - prev->next = pcb->next; - } else { - /* This PCB was the first. */ - LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb); - tcp_tw_pcbs = pcb->next; - } - pcb2 = pcb->next; - memp_free(MEMP_TCP_PCB, pcb); - pcb = pcb2; - } else { - prev = pcb; - pcb = pcb->next; - } - } -} - -/** - * Is called every TCP_FAST_INTERVAL (250 ms) and sends delayed ACKs. - */ -void -tcp_fasttmr(void) -{ - struct tcp_pcb *pcb; - - /* send delayed ACKs */ - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->flags & TF_ACK_DELAY) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n")); - tcp_ack_now(pcb); - pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); - } - } -} - -/** - * Deallocates a list of TCP segments (tcp_seg structures). - * - */ -u8_t -tcp_segs_free(struct tcp_seg *seg) -{ - u8_t count = 0; - struct tcp_seg *next; - while (seg != NULL) { - next = seg->next; - count += tcp_seg_free(seg); - seg = next; - } - return count; -} - -/** - * Frees a TCP segment. - * - */ -u8_t -tcp_seg_free(struct tcp_seg *seg) -{ - u8_t count = 0; - - if (seg != NULL) { - if (seg->p != NULL) { - count = pbuf_free(seg->p); -#if TCP_DEBUG - seg->p = NULL; -#endif /* TCP_DEBUG */ - } - memp_free(MEMP_TCP_SEG, seg); - } - return count; -} - -/** - * Sets the priority of a connection. - * - */ -void -tcp_setprio(struct tcp_pcb *pcb, u8_t prio) -{ - pcb->prio = prio; -} -#if TCP_QUEUE_OOSEQ - -/** - * Returns a copy of the given TCP segment. - * - */ -struct tcp_seg * -tcp_seg_copy(struct tcp_seg *seg) -{ - struct tcp_seg *cseg; - - cseg = memp_malloc(MEMP_TCP_SEG); - if (cseg == NULL) { - return NULL; - } - memcpy((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); - pbuf_ref(cseg->p); - return cseg; -} -#endif - -#if LWIP_CALLBACK_API -static err_t -tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) -{ - arg = arg; - if (p != NULL) { - pbuf_free(p); - } else if (err == ERR_OK) { - return tcp_close(pcb); - } - return ERR_OK; -} -#endif /* LWIP_CALLBACK_API */ - -static void -tcp_kill_prio(u8_t prio) -{ - struct tcp_pcb *pcb, *inactive; - u32_t inactivity; - u8_t mprio; - - - mprio = TCP_PRIO_MAX; - - /* We kill the oldest active connection that has lower priority than - prio. */ - inactivity = 0; - inactive = NULL; - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - if (pcb->prio <= prio && - pcb->prio <= mprio && - (u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { - inactivity = tcp_ticks - pcb->tmr; - inactive = pcb; - mprio = pcb->prio; - } - } - if (inactive != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n", - (void *)inactive, inactivity)); - tcp_abort(inactive); - } -} - - -static void -tcp_kill_timewait(void) -{ - struct tcp_pcb *pcb, *inactive; - u32_t inactivity; - - inactivity = 0; - inactive = NULL; - for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { - inactivity = tcp_ticks - pcb->tmr; - inactive = pcb; - } - } - if (inactive != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n", - (void *)inactive, inactivity)); - tcp_abort(inactive); - } -} - - - -struct tcp_pcb * -tcp_alloc(u8_t prio) -{ - struct tcp_pcb *pcb; - u32_t iss; - - pcb = memp_malloc(MEMP_TCP_PCB); - if (pcb == NULL) { - /* Try killing oldest connection in TIME-WAIT. */ - LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n")); - tcp_kill_timewait(); - pcb = memp_malloc(MEMP_TCP_PCB); - if (pcb == NULL) { - tcp_kill_prio(prio); - pcb = memp_malloc(MEMP_TCP_PCB); - } - } - if (pcb != NULL) { - memset(pcb, 0, sizeof(struct tcp_pcb)); - pcb->prio = TCP_PRIO_NORMAL; - pcb->snd_buf = TCP_SND_BUF; - pcb->snd_queuelen = 0; - pcb->rcv_wnd = TCP_WND; - pcb->tos = 0; - pcb->ttl = TCP_TTL; - pcb->mss = TCP_MSS; - pcb->rto = 3000 / TCP_SLOW_INTERVAL; - pcb->sa = 0; - pcb->sv = 3000 / TCP_SLOW_INTERVAL; - pcb->rtime = 0; - pcb->cwnd = 1; - iss = tcp_next_iss(); - pcb->snd_wl2 = iss; - pcb->snd_nxt = iss; - pcb->snd_max = iss; - pcb->lastack = iss; - pcb->snd_lbb = iss; - pcb->tmr = tcp_ticks; - - pcb->polltmr = 0; - -#if LWIP_CALLBACK_API - pcb->recv = tcp_recv_null; -#endif /* LWIP_CALLBACK_API */ - - /* Init KEEPALIVE timer */ - pcb->keepalive = TCP_KEEPDEFAULT; - pcb->keep_cnt = 0; - } - return pcb; -} - -/** - * Creates a new TCP protocol control block but doesn't place it on - * any of the TCP PCB lists. - * - * @internal: Maybe there should be a idle TCP PCB list where these - * PCBs are put on. We can then implement port reservation using - * tcp_bind(). Currently, we lack this (BSD socket type of) feature. - */ - -struct tcp_pcb * -tcp_new(void) -{ - return tcp_alloc(TCP_PRIO_NORMAL); -} - -/* - * tcp_arg(): - * - * Used to specify the argument that should be passed callback - * functions. - * - */ - -void -tcp_arg(struct tcp_pcb *pcb, void *arg) -{ - pcb->callback_arg = arg; -} -#if LWIP_CALLBACK_API - -/** - * Used to specify the function that should be called when a TCP - * connection receives data. - * - */ -void -tcp_recv(struct tcp_pcb *pcb, - err_t (* recv)(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err)) -{ - pcb->recv = recv; -} - -/** - * Used to specify the function that should be called when TCP data - * has been successfully delivered to the remote host. - * - */ - -void -tcp_sent(struct tcp_pcb *pcb, - err_t (* sent)(void *arg, struct tcp_pcb *tpcb, u16_t len)) -{ - pcb->sent = sent; -} - -/** - * Used to specify the function that should be called when a fatal error - * has occured on the connection. - * - */ -void -tcp_err(struct tcp_pcb *pcb, - void (* errf)(void *arg, err_t err)) -{ - pcb->errf = errf; -} - -/** - * Used for specifying the function that should be called when a - * LISTENing connection has been connected to another host. - * - */ -void -tcp_accept(struct tcp_pcb *pcb, - err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err)) -{ - ((struct tcp_pcb_listen *)pcb)->accept = accept; -} -#endif /* LWIP_CALLBACK_API */ - - -/** - * Used to specify the function that should be called periodically - * from TCP. The interval is specified in terms of the TCP coarse - * timer interval, which is called twice a second. - * - */ -void -tcp_poll(struct tcp_pcb *pcb, - err_t (* poll)(void *arg, struct tcp_pcb *tpcb), u8_t interval) -{ -#if LWIP_CALLBACK_API - pcb->poll = poll; -#endif /* LWIP_CALLBACK_API */ - pcb->pollinterval = interval; -} - -/** - * Purges a TCP PCB. Removes any buffered data and frees the buffer memory. - * - */ -void -tcp_pcb_purge(struct tcp_pcb *pcb) -{ - if (pcb->state != CLOSED && - pcb->state != TIME_WAIT && - pcb->state != LISTEN) { - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n")); - - if (pcb->unsent != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n")); - } - if (pcb->unacked != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n")); - } -#if TCP_QUEUE_OOSEQ /* LW */ - if (pcb->ooseq != NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n")); - } - - tcp_segs_free(pcb->ooseq); - pcb->ooseq = NULL; -#endif /* TCP_QUEUE_OOSEQ */ - tcp_segs_free(pcb->unsent); - tcp_segs_free(pcb->unacked); - pcb->unacked = pcb->unsent = NULL; - } -} - -/** - * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first. - * - */ -void -tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb) -{ - TCP_RMV(pcblist, pcb); - - tcp_pcb_purge(pcb); - - /* if there is an outstanding delayed ACKs, send it */ - if (pcb->state != TIME_WAIT && - pcb->state != LISTEN && - pcb->flags & TF_ACK_DELAY) { - pcb->flags |= TF_ACK_NOW; - tcp_output(pcb); - } - pcb->state = CLOSED; - - LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane()); -} - -/** - * Calculates a new initial sequence number for new connections. - * - */ -u32_t -tcp_next_iss(void) -{ - static u32_t iss = 6510; - - iss += tcp_ticks; /* XXX */ - return iss; -} - -#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG -void -tcp_debug_print(struct tcp_hdr *tcphdr) -{ - LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n")); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", - ntohs(tcphdr->src), ntohs(tcphdr->dest))); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (seq no)\n", - ntohl(tcphdr->seqno))); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (ack no)\n", - ntohl(tcphdr->ackno))); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| %2"U16_F" | |%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"| %5"U16_F" | (hdrlen, flags (", - TCPH_HDRLEN(tcphdr), - TCPH_FLAGS(tcphdr) >> 5 & 1, - TCPH_FLAGS(tcphdr) >> 4 & 1, - TCPH_FLAGS(tcphdr) >> 3 & 1, - TCPH_FLAGS(tcphdr) >> 2 & 1, - TCPH_FLAGS(tcphdr) >> 1 & 1, - TCPH_FLAGS(tcphdr) & 1, - ntohs(tcphdr->wnd))); - tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); - LWIP_DEBUGF(TCP_DEBUG, ("), win)\n")); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(TCP_DEBUG, ("| 0x%04"X16_F" | %5"U16_F" | (chksum, urgp)\n", - ntohs(tcphdr->chksum), ntohs(tcphdr->urgp))); - LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); -} - -void -tcp_debug_print_state(enum tcp_state s) -{ - LWIP_DEBUGF(TCP_DEBUG, ("State: ")); - switch (s) { - case CLOSED: - LWIP_DEBUGF(TCP_DEBUG, ("CLOSED\n")); - break; - case LISTEN: - LWIP_DEBUGF(TCP_DEBUG, ("LISTEN\n")); - break; - case SYN_SENT: - LWIP_DEBUGF(TCP_DEBUG, ("SYN_SENT\n")); - break; - case SYN_RCVD: - LWIP_DEBUGF(TCP_DEBUG, ("SYN_RCVD\n")); - break; - case ESTABLISHED: - LWIP_DEBUGF(TCP_DEBUG, ("ESTABLISHED\n")); - break; - case FIN_WAIT_1: - LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_1\n")); - break; - case FIN_WAIT_2: - LWIP_DEBUGF(TCP_DEBUG, ("FIN_WAIT_2\n")); - break; - case CLOSE_WAIT: - LWIP_DEBUGF(TCP_DEBUG, ("CLOSE_WAIT\n")); - break; - case CLOSING: - LWIP_DEBUGF(TCP_DEBUG, ("CLOSING\n")); - break; - case LAST_ACK: - LWIP_DEBUGF(TCP_DEBUG, ("LAST_ACK\n")); - break; - case TIME_WAIT: - LWIP_DEBUGF(TCP_DEBUG, ("TIME_WAIT\n")); - break; - } -} - -void -tcp_debug_print_flags(u8_t flags) -{ - if (flags & TCP_FIN) { - LWIP_DEBUGF(TCP_DEBUG, ("FIN ")); - } - if (flags & TCP_SYN) { - LWIP_DEBUGF(TCP_DEBUG, ("SYN ")); - } - if (flags & TCP_RST) { - LWIP_DEBUGF(TCP_DEBUG, ("RST ")); - } - if (flags & TCP_PSH) { - LWIP_DEBUGF(TCP_DEBUG, ("PSH ")); - } - if (flags & TCP_ACK) { - LWIP_DEBUGF(TCP_DEBUG, ("ACK ")); - } - if (flags & TCP_URG) { - LWIP_DEBUGF(TCP_DEBUG, ("URG ")); - } - if (flags & TCP_ECE) { - LWIP_DEBUGF(TCP_DEBUG, ("ECE ")); - } - if (flags & TCP_CWR) { - LWIP_DEBUGF(TCP_DEBUG, ("CWR ")); - } -} - -void -tcp_debug_print_pcbs(void) -{ - struct tcp_pcb *pcb; - LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n")); - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", - pcb->local_port, pcb->remote_port, - pcb->snd_nxt, pcb->rcv_nxt)); - tcp_debug_print_state(pcb->state); - } - LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n")); - for(pcb = (struct tcp_pcb *)tcp_listen_pcbs.pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", - pcb->local_port, pcb->remote_port, - pcb->snd_nxt, pcb->rcv_nxt)); - tcp_debug_print_state(pcb->state); - } - LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n")); - for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", - pcb->local_port, pcb->remote_port, - pcb->snd_nxt, pcb->rcv_nxt)); - tcp_debug_print_state(pcb->state); - } -} - -s16_t -tcp_pcbs_sane(void) -{ - struct tcp_pcb *pcb; - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED); - LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN); - LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); - } - for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); - } - return 1; -} -#endif /* TCP_DEBUG */ -#endif /* LWIP_TCP */ - - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/tcp_in.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/tcp_in.c deleted file mode 100644 index 212f9c4db..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/tcp_in.c +++ /dev/null @@ -1,1199 +0,0 @@ -/** - * @file - * - * Transmission Control Protocol, incoming traffic - * - * The input processing functions of TCP. - * - * These functions are generally called in the order (ip_input() ->) tcp_input() -> - * tcp_process() -> tcp_receive() (-> application). - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include "lwip/def.h" -#include "lwip/opt.h" - -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/mem.h" -#include "lwip/memp.h" - -#include "lwip/inet.h" -#include "lwip/tcp.h" - -#include "lwip/stats.h" - -#include "arch/perf.h" -#if LWIP_TCP -/* These variables are global to all functions involved in the input - processing of TCP segments. They are set by the tcp_input() - function. */ -static struct tcp_seg inseg; -static struct tcp_hdr *tcphdr; -static struct ip_hdr *iphdr; -static u32_t seqno, ackno; -static u8_t flags; -static u16_t tcplen; - -static u8_t recv_flags; -static struct pbuf *recv_data; - -struct tcp_pcb *tcp_input_pcb; - -/* Forward declarations. */ -static err_t tcp_process(struct tcp_pcb *pcb); -static void tcp_receive(struct tcp_pcb *pcb); -static void tcp_parseopt(struct tcp_pcb *pcb); - -static err_t tcp_listen_input(struct tcp_pcb_listen *pcb); -static err_t tcp_timewait_input(struct tcp_pcb *pcb); - - -/* tcp_input: - * - * The initial input processing of TCP. It verifies the TCP header, demultiplexes - * the segment between the PCBs and passes it on to tcp_process(), which implements - * the TCP finite state machine. This function is called by the IP layer (in - * ip_input()). - */ - -void -tcp_input(struct pbuf *p, struct netif *inp) -{ - struct tcp_pcb *pcb, *prev; - struct tcp_pcb_listen *lpcb; - u8_t hdrlen; - err_t err; - - PERF_START; - - TCP_STATS_INC(tcp.recv); - - iphdr = p->payload; - tcphdr = (struct tcp_hdr *)((u8_t *)p->payload + IPH_HL(iphdr) * 4); - -#if TCP_INPUT_DEBUG - tcp_debug_print(tcphdr); -#endif - - /* remove header from payload */ - if (pbuf_header(p, -((s16_t)(IPH_HL(iphdr) * 4))) || (p->tot_len < sizeof(struct tcp_hdr))) { - /* drop short packets */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%"U16_F" bytes) discarded\n", p->tot_len)); - TCP_STATS_INC(tcp.lenerr); - TCP_STATS_INC(tcp.drop); - pbuf_free(p); - return; - } - - /* Don't even process incoming broadcasts/multicasts. */ - if (ip_addr_isbroadcast(&(iphdr->dest), inp) || - ip_addr_ismulticast(&(iphdr->dest))) { - pbuf_free(p); - return; - } - -#if CHECKSUM_CHECK_TCP - /* Verify TCP checksum. */ - if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), - (struct ip_addr *)&(iphdr->dest), - IP_PROTO_TCP, p->tot_len) != 0) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04"X16_F"\n", - inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), (struct ip_addr *)&(iphdr->dest), - IP_PROTO_TCP, p->tot_len))); -#if TCP_DEBUG - tcp_debug_print(tcphdr); -#endif /* TCP_DEBUG */ - TCP_STATS_INC(tcp.chkerr); - TCP_STATS_INC(tcp.drop); - - pbuf_free(p); - return; - } -#endif - - /* Move the payload pointer in the pbuf so that it points to the - TCP data instead of the TCP header. */ - hdrlen = TCPH_HDRLEN(tcphdr); - pbuf_header(p, -(hdrlen * 4)); - - /* Convert fields in TCP header to host byte order. */ - tcphdr->src = ntohs(tcphdr->src); - tcphdr->dest = ntohs(tcphdr->dest); - seqno = tcphdr->seqno = ntohl(tcphdr->seqno); - ackno = tcphdr->ackno = ntohl(tcphdr->ackno); - tcphdr->wnd = ntohs(tcphdr->wnd); - - flags = TCPH_FLAGS(tcphdr) & TCP_FLAGS; - tcplen = p->tot_len + ((flags & TCP_FIN || flags & TCP_SYN)? 1: 0); - - /* Demultiplex an incoming segment. First, we check if it is destined - for an active connection. */ - prev = NULL; - - - for(pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED); - LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); - LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN); - if (pcb->remote_port == tcphdr->src && - pcb->local_port == tcphdr->dest && - ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) && - ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) { - - /* Move this PCB to the front of the list so that subsequent - lookups will be faster (we exploit locality in TCP segment - arrivals). */ - LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb); - if (prev != NULL) { - prev->next = pcb->next; - pcb->next = tcp_active_pcbs; - tcp_active_pcbs = pcb; - } - LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb); - break; - } - prev = pcb; - } - - if (pcb == NULL) { - /* If it did not go to an active connection, we check the connections - in the TIME-WAIT state. */ - - for(pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { - LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); - if (pcb->remote_port == tcphdr->src && - pcb->local_port == tcphdr->dest && - ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)) && - ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest))) { - /* We don't really care enough to move this PCB to the front - of the list since we are not very likely to receive that - many segments for connections in TIME-WAIT. */ - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n")); - tcp_timewait_input(pcb); - pbuf_free(p); - return; - } - } - - /* Finally, if we still did not get a match, we check all PCBs that - are LISTENing for incoming connections. */ - prev = NULL; - for(lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { - if ((ip_addr_isany(&(lpcb->local_ip)) || - ip_addr_cmp(&(lpcb->local_ip), &(iphdr->dest))) && - lpcb->local_port == tcphdr->dest) { - /* Move this PCB to the front of the list so that subsequent - lookups will be faster (we exploit locality in TCP segment - arrivals). */ - if (prev != NULL) { - ((struct tcp_pcb_listen *)prev)->next = lpcb->next; - /* our successor is the remainder of the listening list */ - lpcb->next = tcp_listen_pcbs.listen_pcbs; - /* put this listening pcb at the head of the listening list */ - tcp_listen_pcbs.listen_pcbs = lpcb; - } - - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n")); - tcp_listen_input(lpcb); - pbuf_free(p); - return; - } - prev = (struct tcp_pcb *)lpcb; - } - } - -#if TCP_INPUT_DEBUG - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags ")); - tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n")); -#endif /* TCP_INPUT_DEBUG */ - - - if (pcb != NULL) { - /* The incoming segment belongs to a connection. */ -#if TCP_INPUT_DEBUG -#if TCP_DEBUG - tcp_debug_print_state(pcb->state); -#endif /* TCP_DEBUG */ -#endif /* TCP_INPUT_DEBUG */ - - /* Set up a tcp_seg structure. */ - inseg.next = NULL; - inseg.len = p->tot_len; - inseg.dataptr = p->payload; - inseg.p = p; - inseg.tcphdr = tcphdr; - - recv_data = NULL; - recv_flags = 0; - - tcp_input_pcb = pcb; - err = tcp_process(pcb); - tcp_input_pcb = NULL; - /* A return value of ERR_ABRT means that tcp_abort() was called - and that the pcb has been freed. If so, we don't do anything. */ - if (err != ERR_ABRT) { - if (recv_flags & TF_RESET) { - /* TF_RESET means that the connection was reset by the other - end. We then call the error callback to inform the - application that the connection is dead before we - deallocate the PCB. */ - TCP_EVENT_ERR(pcb->errf, pcb->callback_arg, ERR_RST); - tcp_pcb_remove(&tcp_active_pcbs, pcb); - memp_free(MEMP_TCP_PCB, pcb); - } else if (recv_flags & TF_CLOSED) { - /* The connection has been closed and we will deallocate the - PCB. */ - tcp_pcb_remove(&tcp_active_pcbs, pcb); - memp_free(MEMP_TCP_PCB, pcb); - } else { - err = ERR_OK; - /* If the application has registered a "sent" function to be - called when new send buffer space is available, we call it - now. */ - if (pcb->acked > 0) { - TCP_EVENT_SENT(pcb, pcb->acked, err); - } - - if (recv_data != NULL) { - /* Notify application that data has been received. */ - TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err); - } - - /* If a FIN segment was received, we call the callback - function with a NULL buffer to indicate EOF. */ - if (recv_flags & TF_GOT_FIN) { - TCP_EVENT_RECV(pcb, NULL, ERR_OK, err); - } - /* If there were no errors, we try to send something out. */ - if (err == ERR_OK) { - tcp_output(pcb); - } - } - } - - - /* We deallocate the incoming pbuf. If it was buffered by the - application, the application should have called pbuf_ref() to - increase the reference counter in the pbuf. If so, the buffer - isn't actually deallocated by the call to pbuf_free(), only the - reference count is decreased. */ - if (inseg.p != NULL) pbuf_free(inseg.p); -#if TCP_INPUT_DEBUG -#if TCP_DEBUG - tcp_debug_print_state(pcb->state); -#endif /* TCP_DEBUG */ -#endif /* TCP_INPUT_DEBUG */ - - } else { - - /* If no matching PCB was found, send a TCP RST (reset) to the - sender. */ - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n")); - if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) { - TCP_STATS_INC(tcp.proterr); - TCP_STATS_INC(tcp.drop); - tcp_rst(ackno, seqno + tcplen, - &(iphdr->dest), &(iphdr->src), - tcphdr->dest, tcphdr->src); - } - pbuf_free(p); - } - - LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane()); - PERF_STOP("tcp_input"); -} - -/* tcp_listen_input(): - * - * Called by tcp_input() when a segment arrives for a listening - * connection. - */ - -static err_t -tcp_listen_input(struct tcp_pcb_listen *pcb) -{ - struct tcp_pcb *npcb; - u32_t optdata; - - /* In the LISTEN state, we check for incoming SYN segments, - creates a new PCB, and responds with a SYN|ACK. */ - if (flags & TCP_ACK) { - /* For incoming segments with the ACK flag set, respond with a - RST. */ - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n")); - tcp_rst(ackno + 1, seqno + tcplen, - &(iphdr->dest), &(iphdr->src), - tcphdr->dest, tcphdr->src); - } else if (flags & TCP_SYN) { - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %"U16_F" -> %"U16_F".\n", tcphdr->src, tcphdr->dest)); - npcb = tcp_alloc(pcb->prio); - /* If a new PCB could not be created (probably due to lack of memory), - we don't do anything, but rely on the sender will retransmit the - SYN at a time when we have more memory available. */ - if (npcb == NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n")); - TCP_STATS_INC(tcp.memerr); - return ERR_MEM; - } - /* Set up the new PCB. */ - ip_addr_set(&(npcb->local_ip), &(iphdr->dest)); - npcb->local_port = pcb->local_port; - ip_addr_set(&(npcb->remote_ip), &(iphdr->src)); - npcb->remote_port = tcphdr->src; - npcb->state = SYN_RCVD; - npcb->rcv_nxt = seqno + 1; - npcb->snd_wnd = tcphdr->wnd; - npcb->ssthresh = npcb->snd_wnd; - npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */ - npcb->callback_arg = pcb->callback_arg; -#if LWIP_CALLBACK_API - npcb->accept = pcb->accept; -#endif /* LWIP_CALLBACK_API */ - /* inherit socket options */ - npcb->so_options = pcb->so_options & (SOF_DEBUG|SOF_DONTROUTE|SOF_KEEPALIVE|SOF_OOBINLINE|SOF_LINGER); - /* Register the new PCB so that we can begin receiving segments - for it. */ - TCP_REG(&tcp_active_pcbs, npcb); - - /* Parse any options in the SYN. */ - tcp_parseopt(npcb); - - /* Build an MSS option. */ - optdata = htonl(((u32_t)2 << 24) | - ((u32_t)4 << 16) | - (((u32_t)npcb->mss / 256) << 8) | - (npcb->mss & 255)); - /* Send a SYN|ACK together with the MSS option. */ - tcp_enqueue(npcb, NULL, 0, TCP_SYN | TCP_ACK, 0, (u8_t *)&optdata, 4); - return tcp_output(npcb); - } - return ERR_OK; -} - -/* tcp_timewait_input(): - * - * Called by tcp_input() when a segment arrives for a connection in - * TIME_WAIT. - */ - -static err_t -tcp_timewait_input(struct tcp_pcb *pcb) -{ - if (TCP_SEQ_GT(seqno + tcplen, pcb->rcv_nxt)) { - pcb->rcv_nxt = seqno + tcplen; - } - if (tcplen > 0) { - tcp_ack_now(pcb); - } - return tcp_output(pcb); -} - -/* tcp_process - * - * Implements the TCP state machine. Called by tcp_input. In some - * states tcp_receive() is called to receive data. The tcp_seg - * argument will be freed by the caller (tcp_input()) unless the - * recv_data pointer in the pcb is set. - */ - -static err_t -tcp_process(struct tcp_pcb *pcb) -{ - struct tcp_seg *rseg; - u8_t acceptable = 0; - err_t err; - - - err = ERR_OK; - - /* Process incoming RST segments. */ - if (flags & TCP_RST) { - /* First, determine if the reset is acceptable. */ - if (pcb->state == SYN_SENT) { - if (ackno == pcb->snd_nxt) { - acceptable = 1; - } - } else { - /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) && - TCP_SEQ_LEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) { - */ - if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt+pcb->rcv_wnd)) { - acceptable = 1; - } - } - - if (acceptable) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n")); - LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED); - recv_flags = TF_RESET; - pcb->flags &= ~TF_ACK_DELAY; - return ERR_RST; - } else { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", - seqno, pcb->rcv_nxt)); - LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", - seqno, pcb->rcv_nxt)); - return ERR_OK; - } - } - - /* Update the PCB (in)activity timer. */ - pcb->tmr = tcp_ticks; - pcb->keep_cnt = 0; - - /* Do different things depending on the TCP state. */ - switch (pcb->state) { - case SYN_SENT: - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno, - pcb->snd_nxt, ntohl(pcb->unacked->tcphdr->seqno))); - /* received SYN ACK with expected sequence number? */ - if ((flags & TCP_ACK) && (flags & TCP_SYN) - && ackno == ntohl(pcb->unacked->tcphdr->seqno) + 1) { - pcb->snd_buf++; - pcb->rcv_nxt = seqno + 1; - pcb->lastack = ackno; - pcb->snd_wnd = tcphdr->wnd; - pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */ - pcb->state = ESTABLISHED; - pcb->cwnd = pcb->mss; - --pcb->snd_queuelen; - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"U16_F"\n", (u16_t)pcb->snd_queuelen)); - rseg = pcb->unacked; - pcb->unacked = rseg->next; - tcp_seg_free(rseg); - - /* Parse any options in the SYNACK. */ - tcp_parseopt(pcb); - - /* Call the user specified function to call when sucessfully - * connected. */ - TCP_EVENT_CONNECTED(pcb, ERR_OK, err); - tcp_ack(pcb); - } - /* received ACK? possibly a half-open connection */ - else if (flags & TCP_ACK) { - /* send a RST to bring the other side in a non-synchronized state. */ - tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src), - tcphdr->dest, tcphdr->src); - } - break; - case SYN_RCVD: - if (flags & TCP_ACK && - !(flags & TCP_RST)) { - /* expected ACK number? */ - if (TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_nxt)) { - pcb->state = ESTABLISHED; - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); -#if LWIP_CALLBACK_API - LWIP_ASSERT("pcb->accept != NULL", pcb->accept != NULL); -#endif - /* Call the accept function. */ - TCP_EVENT_ACCEPT(pcb, ERR_OK, err); - if (err != ERR_OK) { - /* If the accept function returns with an error, we abort - * the connection. */ - tcp_abort(pcb); - return ERR_ABRT; - } - /* If there was any data contained within this ACK, - * we'd better pass it on to the application as well. */ - tcp_receive(pcb); - pcb->cwnd = pcb->mss; - } - /* incorrect ACK number */ - else { - /* send RST */ - tcp_rst(ackno, seqno + tcplen, &(iphdr->dest), &(iphdr->src), - tcphdr->dest, tcphdr->src); - } - } - break; - case CLOSE_WAIT: - /* FALLTHROUGH */ - case ESTABLISHED: - tcp_receive(pcb); - if (flags & TCP_FIN) { - tcp_ack_now(pcb); - pcb->state = CLOSE_WAIT; - } - break; - case FIN_WAIT_1: - tcp_receive(pcb); - if (flags & TCP_FIN) { - if (flags & TCP_ACK && ackno == pcb->snd_nxt) { - LWIP_DEBUGF(TCP_DEBUG, - ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); - tcp_ack_now(pcb); - tcp_pcb_purge(pcb); - TCP_RMV(&tcp_active_pcbs, pcb); - pcb->state = TIME_WAIT; - TCP_REG(&tcp_tw_pcbs, pcb); - } else { - tcp_ack_now(pcb); - pcb->state = CLOSING; - } - } else if (flags & TCP_ACK && ackno == pcb->snd_nxt) { - pcb->state = FIN_WAIT_2; - } - break; - case FIN_WAIT_2: - tcp_receive(pcb); - if (flags & TCP_FIN) { - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); - tcp_ack_now(pcb); - tcp_pcb_purge(pcb); - TCP_RMV(&tcp_active_pcbs, pcb); - pcb->state = TIME_WAIT; - TCP_REG(&tcp_tw_pcbs, pcb); - } - break; - case CLOSING: - tcp_receive(pcb); - if (flags & TCP_ACK && ackno == pcb->snd_nxt) { - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); - tcp_ack_now(pcb); - tcp_pcb_purge(pcb); - TCP_RMV(&tcp_active_pcbs, pcb); - pcb->state = TIME_WAIT; - TCP_REG(&tcp_tw_pcbs, pcb); - } - break; - case LAST_ACK: - tcp_receive(pcb); - if (flags & TCP_ACK && ackno == pcb->snd_nxt) { - LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); - pcb->state = CLOSED; - recv_flags = TF_CLOSED; - } - break; - default: - break; - } - return ERR_OK; -} - -/* tcp_receive: - * - * Called by tcp_process. Checks if the given segment is an ACK for outstanding - * data, and if so frees the memory of the buffered data. Next, is places the - * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment - * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until - * i it has been removed from the buffer. - * - * If the incoming segment constitutes an ACK for a segment that was used for RTT - * estimation, the RTT is estimated here as well. - */ - -static void -tcp_receive(struct tcp_pcb *pcb) -{ - struct tcp_seg *next; -#if TCP_QUEUE_OOSEQ - struct tcp_seg *prev, *cseg; -#endif - struct pbuf *p; - s32_t off; - s16_t m; - u32_t right_wnd_edge; - u16_t new_tot_len; - - - if (flags & TCP_ACK) { - right_wnd_edge = pcb->snd_wnd + pcb->snd_wl1; - - /* Update window. */ - if (TCP_SEQ_LT(pcb->snd_wl1, seqno) || - (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || - (pcb->snd_wl2 == ackno && tcphdr->wnd > pcb->snd_wnd)) { - pcb->snd_wnd = tcphdr->wnd; - pcb->snd_wl1 = seqno; - pcb->snd_wl2 = ackno; - LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %"U32_F"\n", pcb->snd_wnd)); -#if TCP_WND_DEBUG - } else { - if (pcb->snd_wnd != tcphdr->wnd) { - LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: no window update lastack %"U32_F" snd_max %"U32_F" ackno %"U32_F" wl1 %"U32_F" seqno %"U32_F" wl2 %"U32_F"\n", - pcb->lastack, pcb->snd_max, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2)); - } -#endif /* TCP_WND_DEBUG */ - } - - - if (pcb->lastack == ackno) { - pcb->acked = 0; - - if (pcb->snd_wl1 + pcb->snd_wnd == right_wnd_edge){ - ++pcb->dupacks; - if (pcb->dupacks >= 3 && pcb->unacked != NULL) { - if (!(pcb->flags & TF_INFR)) { - /* This is fast retransmit. Retransmit the first unacked segment. */ - LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupacks %"U16_F" (%"U32_F"), fast retransmit %"U32_F"\n", - (u16_t)pcb->dupacks, pcb->lastack, - ntohl(pcb->unacked->tcphdr->seqno))); - tcp_rexmit(pcb); - /* Set ssthresh to max (FlightSize / 2, 2*SMSS) */ - /*pcb->ssthresh = LWIP_MAX((pcb->snd_max - - pcb->lastack) / 2, - 2 * pcb->mss);*/ - /* Set ssthresh to half of the minimum of the currenct cwnd and the advertised window */ - if(pcb->cwnd > pcb->snd_wnd) - pcb->ssthresh = pcb->snd_wnd / 2; - else - pcb->ssthresh = pcb->cwnd / 2; - - pcb->cwnd = pcb->ssthresh + 3 * pcb->mss; - pcb->flags |= TF_INFR; - } else { - /* Inflate the congestion window, but not if it means that - the value overflows. */ - if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { - pcb->cwnd += pcb->mss; - } - } - } - } else { - LWIP_DEBUGF(TCP_FR_DEBUG, ("tcp_receive: dupack averted %"U32_F" %"U32_F"\n", - pcb->snd_wl1 + pcb->snd_wnd, right_wnd_edge)); - } - } else - /*if (TCP_SEQ_LT(pcb->lastack, ackno) && - TCP_SEQ_LEQ(ackno, pcb->snd_max)) { */ - if(TCP_SEQ_BETWEEN(ackno, pcb->lastack+1, pcb->snd_max)){ - /* We come here when the ACK acknowledges new data. */ - - /* Reset the "IN Fast Retransmit" flag, since we are no longer - in fast retransmit. Also reset the congestion window to the - slow start threshold. */ - if (pcb->flags & TF_INFR) { - pcb->flags &= ~TF_INFR; - pcb->cwnd = pcb->ssthresh; - } - - /* Reset the number of retransmissions. */ - pcb->nrtx = 0; - - /* Reset the retransmission time-out. */ - pcb->rto = (pcb->sa >> 3) + pcb->sv; - - /* Update the send buffer space. */ - pcb->acked = ackno - pcb->lastack; - - pcb->snd_buf += pcb->acked; - - /* Reset the fast retransmit variables. */ - pcb->dupacks = 0; - pcb->lastack = ackno; - - /* Update the congestion control variables (cwnd and - ssthresh). */ - if (pcb->state >= ESTABLISHED) { - if (pcb->cwnd < pcb->ssthresh) { - if ((u16_t)(pcb->cwnd + pcb->mss) > pcb->cwnd) { - pcb->cwnd += pcb->mss; - } - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"U16_F"\n", pcb->cwnd)); - } else { - u16_t new_cwnd = (pcb->cwnd + pcb->mss * pcb->mss / pcb->cwnd); - if (new_cwnd > pcb->cwnd) { - pcb->cwnd = new_cwnd; - } - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %"U16_F"\n", pcb->cwnd)); - } - } - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %"U32_F", unacked->seqno %"U32_F":%"U32_F"\n", - ackno, - pcb->unacked != NULL? - ntohl(pcb->unacked->tcphdr->seqno): 0, - pcb->unacked != NULL? - ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked): 0)); - - /* Remove segment from the unacknowledged list if the incoming - ACK acknowlegdes them. */ - while (pcb->unacked != NULL && - TCP_SEQ_LEQ(ntohl(pcb->unacked->tcphdr->seqno) + - TCP_TCPLEN(pcb->unacked), ackno)) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unacked\n", - ntohl(pcb->unacked->tcphdr->seqno), - ntohl(pcb->unacked->tcphdr->seqno) + - TCP_TCPLEN(pcb->unacked))); - - next = pcb->unacked; - pcb->unacked = pcb->unacked->next; - - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen)); - pcb->snd_queuelen -= pbuf_clen(next->p); - tcp_seg_free(next); - - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unacked)\n", (u16_t)pcb->snd_queuelen)); - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_receive: valid queue length", pcb->unacked != NULL || - pcb->unsent != NULL); - } - } - pcb->polltmr = 0; - } - - /* We go through the ->unsent list to see if any of the segments - on the list are acknowledged by the ACK. This may seem - strange since an "unsent" segment shouldn't be acked. The - rationale is that lwIP puts all outstanding segments on the - ->unsent list after a retransmission, so these segments may - in fact have been sent once. */ - while (pcb->unsent != NULL && - /*TCP_SEQ_LEQ(ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), ackno) && - TCP_SEQ_LEQ(ackno, pcb->snd_max)*/ - TCP_SEQ_BETWEEN(ackno, ntohl(pcb->unsent->tcphdr->seqno) + TCP_TCPLEN(pcb->unsent), pcb->snd_max) - ) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->unsent\n", - ntohl(pcb->unsent->tcphdr->seqno), ntohl(pcb->unsent->tcphdr->seqno) + - TCP_TCPLEN(pcb->unsent))); - - next = pcb->unsent; - pcb->unsent = pcb->unsent->next; - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"U16_F" ... ", (u16_t)pcb->snd_queuelen)); - pcb->snd_queuelen -= pbuf_clen(next->p); - tcp_seg_free(next); - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"U16_F" (after freeing unsent)\n", (u16_t)pcb->snd_queuelen)); - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_receive: valid queue length", - pcb->unacked != NULL || pcb->unsent != NULL); - } - - if (pcb->unsent != NULL) { - pcb->snd_nxt = htonl(pcb->unsent->tcphdr->seqno); - } - } - /* End of ACK for new data processing. */ - - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %"U32_F" rtseq %"U32_F" ackno %"U32_F"\n", - pcb->rttest, pcb->rtseq, ackno)); - - /* RTT estimation calculations. This is done by checking if the - incoming segment acknowledges the segment we use to take a - round-trip time measurement. */ - if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) { - m = tcp_ticks - pcb->rttest; - - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n", - m, m * TCP_SLOW_INTERVAL)); - - /* This is taken directly from VJs original code in his paper */ - m = m - (pcb->sa >> 3); - pcb->sa += m; - if (m < 0) { - m = -m; - } - m = m - (pcb->sv >> 2); - pcb->sv += m; - pcb->rto = (pcb->sa >> 3) + pcb->sv; - - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" miliseconds)\n", - pcb->rto, pcb->rto * TCP_SLOW_INTERVAL)); - - pcb->rttest = 0; - } - } - - /* If the incoming segment contains data, we must process it - further. */ - if (tcplen > 0) { - /* This code basically does three things: - - +) If the incoming segment contains data that is the next - in-sequence data, this data is passed to the application. This - might involve trimming the first edge of the data. The rcv_nxt - variable and the advertised window are adjusted. - - +) If the incoming segment has data that is above the next - sequence number expected (->rcv_nxt), the segment is placed on - the ->ooseq queue. This is done by finding the appropriate - place in the ->ooseq queue (which is ordered by sequence - number) and trim the segment in both ends if needed. An - immediate ACK is sent to indicate that we received an - out-of-sequence segment. - - +) Finally, we check if the first segment on the ->ooseq queue - now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If - rcv_nxt > ooseq->seqno, we must trim the first edge of the - segment on ->ooseq before we adjust rcv_nxt. The data in the - segments that are now on sequence are chained onto the - incoming segment so that we only need to call the application - once. - */ - - /* First, we check if we must trim the first edge. We have to do - this if the sequence number of the incoming segment is less - than rcv_nxt, and the sequence number plus the length of the - segment is larger than rcv_nxt. */ - /* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)){ - if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/ - if(TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno+1, seqno+tcplen-1)){ - /* Trimming the first edge is done by pushing the payload - pointer in the pbuf downwards. This is somewhat tricky since - we do not want to discard the full contents of the pbuf up to - the new starting point of the data since we have to keep the - TCP header which is present in the first pbuf in the chain. - - What is done is really quite a nasty hack: the first pbuf in - the pbuf chain is pointed to by inseg.p. Since we need to be - able to deallocate the whole pbuf, we cannot change this - inseg.p pointer to point to any of the later pbufs in the - chain. Instead, we point the ->payload pointer in the first - pbuf to data in one of the later pbufs. We also set the - inseg.data pointer to point to the right place. This way, the - ->p pointer will still point to the first pbuf, but the - ->p->payload pointer will point to data in another pbuf. - - After we are done with adjusting the pbuf pointers we must - adjust the ->data pointer in the seg and the segment - length.*/ - - off = pcb->rcv_nxt - seqno; - p = inseg.p; - if (inseg.p->len < off) { - new_tot_len = inseg.p->tot_len - off; - while (p->len < off) { - off -= p->len; - /* KJM following line changed (with addition of new_tot_len var) - to fix bug #9076 - inseg.p->tot_len -= p->len; */ - p->tot_len = new_tot_len; - p->len = 0; - p = p->next; - } - pbuf_header(p, -off); - } else { - pbuf_header(inseg.p, -off); - } - /* KJM following line changed to use p->payload rather than inseg->p->payload - to fix bug #9076 */ - inseg.dataptr = p->payload; - inseg.len -= pcb->rcv_nxt - seqno; - inseg.tcphdr->seqno = seqno = pcb->rcv_nxt; - } - else{ - if(TCP_SEQ_LT(seqno, pcb->rcv_nxt)){ - /* the whole segment is < rcv_nxt */ - /* must be a duplicate of a packet that has already been correctly handled */ - - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno)); - tcp_ack_now(pcb); - } - } - - /* The sequence number must be within the window (above rcv_nxt - and below rcv_nxt + rcv_wnd) in order to be further - processed. */ - /*if (TCP_SEQ_GEQ(seqno, pcb->rcv_nxt) && - TCP_SEQ_LT(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ - if(TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)){ - if (pcb->rcv_nxt == seqno) { - /* The incoming segment is the next in sequence. We check if - we have to trim the end of the segment and update rcv_nxt - and pass the data to the application. */ -#if TCP_QUEUE_OOSEQ - if (pcb->ooseq != NULL && - TCP_SEQ_LEQ(pcb->ooseq->tcphdr->seqno, seqno + inseg.len)) { - /* We have to trim the second edge of the incoming - segment. */ - inseg.len = pcb->ooseq->tcphdr->seqno - seqno; - pbuf_realloc(inseg.p, inseg.len); - } -#endif /* TCP_QUEUE_OOSEQ */ - - tcplen = TCP_TCPLEN(&inseg); - - /* First received FIN will be ACKed +1, on any successive (duplicate) - * FINs we are already in CLOSE_WAIT and have already done +1. - */ - if (pcb->state != CLOSE_WAIT) { - pcb->rcv_nxt += tcplen; - } - - /* Update the receiver's (our) window. */ - if (pcb->rcv_wnd < tcplen) { - pcb->rcv_wnd = 0; - } else { - pcb->rcv_wnd -= tcplen; - } - - /* If there is data in the segment, we make preparations to - pass this up to the application. The ->recv_data variable - is used for holding the pbuf that goes to the - application. The code for reassembling out-of-sequence data - chains its data on this pbuf as well. - - If the segment was a FIN, we set the TF_GOT_FIN flag that will - be used to indicate to the application that the remote side has - closed its end of the connection. */ - if (inseg.p->tot_len > 0) { - recv_data = inseg.p; - /* Since this pbuf now is the responsibility of the - application, we delete our reference to it so that we won't - (mistakingly) deallocate it. */ - inseg.p = NULL; - } - if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n")); - recv_flags = TF_GOT_FIN; - } - -#if TCP_QUEUE_OOSEQ - /* We now check if we have segments on the ->ooseq queue that - is now in sequence. */ - while (pcb->ooseq != NULL && - pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) { - - cseg = pcb->ooseq; - seqno = pcb->ooseq->tcphdr->seqno; - - pcb->rcv_nxt += TCP_TCPLEN(cseg); - if (pcb->rcv_wnd < TCP_TCPLEN(cseg)) { - pcb->rcv_wnd = 0; - } else { - pcb->rcv_wnd -= TCP_TCPLEN(cseg); - } - if (cseg->p->tot_len > 0) { - /* Chain this pbuf onto the pbuf that we will pass to - the application. */ - if (recv_data) { - pbuf_cat(recv_data, cseg->p); - } else { - recv_data = cseg->p; - } - cseg->p = NULL; - } - if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { - LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n")); - recv_flags = TF_GOT_FIN; - } - - - pcb->ooseq = cseg->next; - tcp_seg_free(cseg); - } -#endif /* TCP_QUEUE_OOSEQ */ - - - /* Acknowledge the segment(s). */ - tcp_ack(pcb); - - } else { - /* We get here if the incoming segment is out-of-sequence. */ - tcp_ack_now(pcb); -#if TCP_QUEUE_OOSEQ - /* We queue the segment on the ->ooseq queue. */ - if (pcb->ooseq == NULL) { - pcb->ooseq = tcp_seg_copy(&inseg); - } else { - /* If the queue is not empty, we walk through the queue and - try to find a place where the sequence number of the - incoming segment is between the sequence numbers of the - previous and the next segment on the ->ooseq queue. That is - the place where we put the incoming segment. If needed, we - trim the second edges of the previous and the incoming - segment so that it will fit into the sequence. - - If the incoming segment has the same sequence number as a - segment on the ->ooseq queue, we discard the segment that - contains less data. */ - - prev = NULL; - for(next = pcb->ooseq; next != NULL; next = next->next) { - if (seqno == next->tcphdr->seqno) { - /* The sequence number of the incoming segment is the - same as the sequence number of the segment on - ->ooseq. We check the lengths to see which one to - discard. */ - if (inseg.len > next->len) { - /* The incoming segment is larger than the old - segment. We replace the old segment with the new - one. */ - cseg = tcp_seg_copy(&inseg); - if (cseg != NULL) { - cseg->next = next->next; - if (prev != NULL) { - prev->next = cseg; - } else { - pcb->ooseq = cseg; - } - } - break; - } else { - /* Either the lenghts are the same or the incoming - segment was smaller than the old one; in either - case, we ditch the incoming segment. */ - break; - } - } else { - if (prev == NULL) { - if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) { - /* The sequence number of the incoming segment is lower - than the sequence number of the first segment on the - queue. We put the incoming segment first on the - queue. */ - - if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) { - /* We need to trim the incoming segment. */ - inseg.len = next->tcphdr->seqno - seqno; - pbuf_realloc(inseg.p, inseg.len); - } - cseg = tcp_seg_copy(&inseg); - if (cseg != NULL) { - cseg->next = next; - pcb->ooseq = cseg; - } - break; - } - } else - /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) && - TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/ - if(TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno+1, next->tcphdr->seqno-1)){ - /* The sequence number of the incoming segment is in - between the sequence numbers of the previous and - the next segment on ->ooseq. We trim and insert the - incoming segment and trim the previous segment, if - needed. */ - if (TCP_SEQ_GT(seqno + inseg.len, next->tcphdr->seqno)) { - /* We need to trim the incoming segment. */ - inseg.len = next->tcphdr->seqno - seqno; - pbuf_realloc(inseg.p, inseg.len); - } - - cseg = tcp_seg_copy(&inseg); - if (cseg != NULL) { - cseg->next = next; - prev->next = cseg; - if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) { - /* We need to trim the prev segment. */ - prev->len = seqno - prev->tcphdr->seqno; - pbuf_realloc(prev->p, prev->len); - } - } - break; - } - /* If the "next" segment is the last segment on the - ooseq queue, we add the incoming segment to the end - of the list. */ - if (next->next == NULL && - TCP_SEQ_GT(seqno, next->tcphdr->seqno)) { - next->next = tcp_seg_copy(&inseg); - if (next->next != NULL) { - if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) { - /* We need to trim the last segment. */ - next->len = seqno - next->tcphdr->seqno; - pbuf_realloc(next->p, next->len); - } - } - break; - } - } - prev = next; - } - } -#endif /* TCP_QUEUE_OOSEQ */ - - } - } else { - /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) || - TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ - if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){ - tcp_ack_now(pcb); - } - } - } else { - /* Segments with length 0 is taken care of here. Segments that - fall out of the window are ACKed. */ - /*if (TCP_SEQ_GT(pcb->rcv_nxt, seqno) || - TCP_SEQ_GEQ(seqno, pcb->rcv_nxt + pcb->rcv_wnd)) {*/ - if(!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd-1)){ - tcp_ack_now(pcb); - } - } -} - -/* - * tcp_parseopt: - * - * Parses the options contained in the incoming segment. (Code taken - * from uIP with only small changes.) - * - */ - -static void -tcp_parseopt(struct tcp_pcb *pcb) -{ - u8_t c; - u8_t *opts, opt; - u16_t mss; - - opts = (u8_t *)tcphdr + TCP_HLEN; - - /* Parse the TCP MSS option, if present. */ - if(TCPH_HDRLEN(tcphdr) > 0x5) { - for(c = 0; c < (TCPH_HDRLEN(tcphdr) - 5) << 2 ;) { - opt = opts[c]; - if (opt == 0x00) { - /* End of options. */ - break; - } else if (opt == 0x01) { - ++c; - /* NOP option. */ - } else if (opt == 0x02 && - opts[c + 1] == 0x04) { - /* An MSS option with the right option length. */ - mss = (opts[c + 2] << 8) | opts[c + 3]; - pcb->mss = mss > TCP_MSS? TCP_MSS: mss; - - /* And we are done processing options. */ - break; - } else { - if (opts[c + 1] == 0) { - /* If the length field is zero, the options are malformed - and we don't process them further. */ - break; - } - /* All other options have a length field, so that we easily - can skip past them. */ - c += opts[c + 1]; - } - } - } -} -#endif /* LWIP_TCP */ - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/tcp_out.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/tcp_out.c deleted file mode 100644 index 62982bd14..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/tcp_out.c +++ /dev/null @@ -1,721 +0,0 @@ -/** - * @file - * - * Transmission Control Protocol, outgoing traffic - * - * The output functions of TCP. - * - */ - -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#include - -#include "lwip/def.h" -#include "lwip/opt.h" -#include "lwip/mem.h" -#include "lwip/memp.h" -#include "lwip/sys.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/inet.h" -#include "lwip/tcp.h" -#include "lwip/stats.h" - -#if LWIP_TCP - -/* Forward declarations.*/ -static void tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb); - -err_t -tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags) -{ - /* no data, no length, flags, copy=1, no optdata, no optdatalen */ - return tcp_enqueue(pcb, NULL, 0, flags, 1, NULL, 0); -} - -/** - * Write data for sending (but does not send it immediately). - * - * It waits in the expectation of more data being sent soon (as - * it can send them more efficiently by combining them together). - * To prompt the system to send data now, call tcp_output() after - * calling tcp_write(). - * - * @arg pcb Protocol control block of the TCP connection to enqueue data for. - * - * @see tcp_write() - */ - -err_t -tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t copy) -{ - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, arg=%p, len=%"U16_F", copy=%"U16_F")\n", (void *)pcb, - arg, len, (u16_t)copy)); - /* connection is in valid state for data transmission? */ - if (pcb->state == ESTABLISHED || - pcb->state == CLOSE_WAIT || - pcb->state == SYN_SENT || - pcb->state == SYN_RCVD) { - if (len > 0) { - return tcp_enqueue(pcb, (void *)arg, len, 0, copy, NULL, 0); - } - return ERR_OK; - } else { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_STATE | 3, ("tcp_write() called in invalid state\n")); - return ERR_CONN; - } -} - -/** - * Enqueue either data or TCP options (but not both) for tranmission - * - * - * - * @arg pcb Protocol control block for the TCP connection to enqueue data for. - * @arg arg Pointer to the data to be enqueued for sending. - * @arg len Data length in bytes - * @arg flags - * @arg copy 1 if data must be copied, 0 if data is non-volatile and can be - * referenced. - * @arg optdata - * @arg optlen - */ -err_t -tcp_enqueue(struct tcp_pcb *pcb, void *arg, u16_t len, - u8_t flags, u8_t copy, - u8_t *optdata, u8_t optlen) -{ - struct pbuf *p; - struct tcp_seg *seg, *useg, *queue; - u32_t left, seqno; - u16_t seglen; - void *ptr; - u8_t queuelen; - - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_enqueue(pcb=%p, arg=%p, len=%"U16_F", flags=%"X16_F", copy=%"U16_F")\n", - (void *)pcb, arg, len, (u16_t)flags, (u16_t)copy)); - LWIP_ASSERT("tcp_enqueue: len == 0 || optlen == 0 (programmer violates API)", - len == 0 || optlen == 0); - LWIP_ASSERT("tcp_enqueue: arg == NULL || optdata == NULL (programmer violates API)", - arg == NULL || optdata == NULL); - /* fail on too much data */ - if (len > pcb->snd_buf) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too much data (len=%"U16_F" > snd_buf=%"U16_F")\n", len, pcb->snd_buf)); - return ERR_MEM; - } - left = len; - ptr = arg; - - /* seqno will be the sequence number of the first segment enqueued - * by the call to this function. */ - seqno = pcb->snd_lbb; - - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen)); - - /* If total number of pbufs on the unsent/unacked queues exceeds the - * configured maximum, return an error */ - queuelen = pcb->snd_queuelen; - if (queuelen >= TCP_SND_QUEUELEN) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 3, ("tcp_enqueue: too long queue %"U16_F" (max %"U16_F")\n", queuelen, TCP_SND_QUEUELEN)); - TCP_STATS_INC(tcp.memerr); - return ERR_MEM; - } - if (queuelen != 0) { - LWIP_ASSERT("tcp_enqueue: pbufs on queue => at least one queue non-empty", - pcb->unacked != NULL || pcb->unsent != NULL); - } else { - LWIP_ASSERT("tcp_enqueue: no pbufs on queue => both queues empty", - pcb->unacked == NULL && pcb->unsent == NULL); - } - - /* First, break up the data into segments and tuck them together in - * the local "queue" variable. */ - useg = queue = seg = NULL; - seglen = 0; - while (queue == NULL || left > 0) { - - /* The segment length should be the MSS if the data to be enqueued - * is larger than the MSS. */ - seglen = left > pcb->mss? pcb->mss: left; - - /* Allocate memory for tcp_seg, and fill in fields. */ - seg = memp_malloc(MEMP_TCP_SEG); - if (seg == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for tcp_seg\n")); - goto memerr; - } - seg->next = NULL; - seg->p = NULL; - - /* first segment of to-be-queued data? */ - if (queue == NULL) { - queue = seg; - } - /* subsequent segments of to-be-queued data */ - else { - /* Attach the segment to the end of the queued segments */ - LWIP_ASSERT("useg != NULL", useg != NULL); - useg->next = seg; - } - /* remember last segment of to-be-queued data for next iteration */ - useg = seg; - - /* If copy is set, memory should be allocated - * and data copied into pbuf, otherwise data comes from - * ROM or other static memory, and need not be copied. If - * optdata is != NULL, we have options instead of data. */ - - /* options? */ - if (optdata != NULL) { - if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { - goto memerr; - } - ++queuelen; - seg->dataptr = seg->p->payload; - } - /* copy from volatile memory? */ - else if (copy) { - if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_RAM)) == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue : could not allocate memory for pbuf copy size %"U16_F"\n", seglen)); - goto memerr; - } - ++queuelen; - if (arg != NULL) { - memcpy(seg->p->payload, ptr, seglen); - } - seg->dataptr = seg->p->payload; - } - /* do not copy data */ - else { - /* First, allocate a pbuf for holding the data. - * since the referenced data is available at least until it is sent out on the - * link (as it has to be ACKed by the remote party) we can safely use PBUF_ROM - * instead of PBUF_REF here. - */ - if ((p = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for zero-copy pbuf\n")); - goto memerr; - } - ++queuelen; - /* reference the non-volatile payload data */ - p->payload = ptr; - seg->dataptr = ptr; - - /* Second, allocate a pbuf for the headers. */ - if ((seg->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_RAM)) == NULL) { - /* If allocation fails, we have to deallocate the data pbuf as - * well. */ - pbuf_free(p); - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: could not allocate memory for header pbuf\n")); - goto memerr; - } - ++queuelen; - - /* Concatenate the headers and data pbufs together. */ - pbuf_cat(seg->p/*header*/, p/*data*/); - p = NULL; - } - - /* Now that there are more segments queued, we check again if the - length of the queue exceeds the configured maximum. */ - if (queuelen > TCP_SND_QUEUELEN) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: queue too long %"U16_F" (%"U16_F")\n", queuelen, TCP_SND_QUEUELEN)); - goto memerr; - } - - seg->len = seglen; - - /* build TCP header */ - if (pbuf_header(seg->p, TCP_HLEN)) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | 2, ("tcp_enqueue: no room for TCP header in pbuf.\n")); - TCP_STATS_INC(tcp.err); - goto memerr; - } - seg->tcphdr = seg->p->payload; - seg->tcphdr->src = htons(pcb->local_port); - seg->tcphdr->dest = htons(pcb->remote_port); - seg->tcphdr->seqno = htonl(seqno); - seg->tcphdr->urgp = 0; - TCPH_FLAGS_SET(seg->tcphdr, flags); - /* don't fill in tcphdr->ackno and tcphdr->wnd until later */ - - /* Copy the options into the header, if they are present. */ - if (optdata == NULL) { - TCPH_HDRLEN_SET(seg->tcphdr, 5); - } - else { - TCPH_HDRLEN_SET(seg->tcphdr, (5 + optlen / 4)); - /* Copy options into data portion of segment. - Options can thus only be sent in non data carrying - segments such as SYN|ACK. */ - memcpy(seg->dataptr, optdata, optlen); - } - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE, ("tcp_enqueue: queueing %"U32_F":%"U32_F" (0x%"X16_F")\n", - ntohl(seg->tcphdr->seqno), - ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg), - (u16_t)flags)); - - left -= seglen; - seqno += seglen; - ptr = (void *)((u8_t *)ptr + seglen); - } - - /* Now that the data to be enqueued has been broken up into TCP - segments in the queue variable, we add them to the end of the - pcb->unsent queue. */ - if (pcb->unsent == NULL) { - useg = NULL; - } - else { - for (useg = pcb->unsent; useg->next != NULL; useg = useg->next); - } - /* { useg is last segment on the unsent queue, NULL if list is empty } */ - - /* If there is room in the last pbuf on the unsent queue, - chain the first pbuf on the queue together with that. */ - if (useg != NULL && - TCP_TCPLEN(useg) != 0 && - !(TCPH_FLAGS(useg->tcphdr) & (TCP_SYN | TCP_FIN)) && - !(flags & (TCP_SYN | TCP_FIN)) && - /* fit within max seg size */ - useg->len + queue->len <= pcb->mss) { - /* Remove TCP header from first segment of our to-be-queued list */ - pbuf_header(queue->p, -TCP_HLEN); - pbuf_cat(useg->p, queue->p); - useg->len += queue->len; - useg->next = queue->next; - - LWIP_DEBUGF(TCP_OUTPUT_DEBUG | DBG_TRACE | DBG_STATE, ("tcp_enqueue: chaining segments, new len %"U16_F"\n", useg->len)); - if (seg == queue) { - seg = NULL; - } - memp_free(MEMP_TCP_SEG, queue); - } - else { - /* empty list */ - if (useg == NULL) { - /* initialize list with this segment */ - pcb->unsent = queue; - } - /* enqueue segment */ - else { - useg->next = queue; - } - } - if ((flags & TCP_SYN) || (flags & TCP_FIN)) { - ++len; - } - pcb->snd_lbb += len; - - pcb->snd_buf -= len; - - /* update number of segments on the queues */ - pcb->snd_queuelen = queuelen; - LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: %"S16_F" (after enqueued)\n", pcb->snd_queuelen)); - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_enqueue: valid queue length", - pcb->unacked != NULL || pcb->unsent != NULL); - } - - /* Set the PSH flag in the last segment that we enqueued, but only - if the segment has data (indicated by seglen > 0). */ - if (seg != NULL && seglen > 0 && seg->tcphdr != NULL) { - TCPH_SET_FLAG(seg->tcphdr, TCP_PSH); - } - - return ERR_OK; -memerr: - TCP_STATS_INC(tcp.memerr); - - if (queue != NULL) { - tcp_segs_free(queue); - } - if (pcb->snd_queuelen != 0) { - LWIP_ASSERT("tcp_enqueue: valid queue length", pcb->unacked != NULL || - pcb->unsent != NULL); - } - LWIP_DEBUGF(TCP_QLEN_DEBUG | DBG_STATE, ("tcp_enqueue: %"S16_F" (with mem err)\n", pcb->snd_queuelen)); - return ERR_MEM; -} - -/* find out what we can send and send it */ -err_t -tcp_output(struct tcp_pcb *pcb) -{ - struct pbuf *p; - struct tcp_hdr *tcphdr; - struct tcp_seg *seg, *useg; - u32_t wnd; -#if TCP_CWND_DEBUG - s16_t i = 0; -#endif /* TCP_CWND_DEBUG */ - - /* First, check if we are invoked by the TCP input processing - code. If so, we do not output anything. Instead, we rely on the - input processing code to call us when input processing is done - with. */ - if (tcp_input_pcb == pcb) { - return ERR_OK; - } - - wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd); - - seg = pcb->unsent; - - /* useg should point to last segment on unacked queue */ - useg = pcb->unacked; - if (useg != NULL) { - for (; useg->next != NULL; useg = useg->next); - } - - /* If the TF_ACK_NOW flag is set and no data will be sent (either - * because the ->unsent queue is empty or because the window does - * not allow it), construct an empty ACK segment and send it. - * - * If data is to be sent, we will just piggyback the ACK (see below). - */ - if (pcb->flags & TF_ACK_NOW && - (seg == NULL || - ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd)) { - p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); - if (p == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n")); - return ERR_BUF; - } - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt)); - /* remove ACK flags from the PCB, as we send an empty ACK now */ - pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); - - tcphdr = p->payload; - tcphdr->src = htons(pcb->local_port); - tcphdr->dest = htons(pcb->remote_port); - tcphdr->seqno = htonl(pcb->snd_nxt); - tcphdr->ackno = htonl(pcb->rcv_nxt); - TCPH_FLAGS_SET(tcphdr, TCP_ACK); - tcphdr->wnd = htons(pcb->rcv_wnd); - tcphdr->urgp = 0; - TCPH_HDRLEN_SET(tcphdr, 5); - - tcphdr->chksum = 0; -#if CHECKSUM_GEN_TCP - tcphdr->chksum = inet_chksum_pseudo(p, &(pcb->local_ip), &(pcb->remote_ip), - IP_PROTO_TCP, p->tot_len); -#endif - ip_output(p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, - IP_PROTO_TCP); - pbuf_free(p); - - return ERR_OK; - } - -#if TCP_OUTPUT_DEBUG - if (seg == NULL) { - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", (void*)pcb->unsent)); - } -#endif /* TCP_OUTPUT_DEBUG */ -#if TCP_CWND_DEBUG - if (seg == NULL) { - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", seg == NULL, ack %"U32_F"\n", - pcb->snd_wnd, pcb->cwnd, wnd, - pcb->lastack)); - } else { - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F"\n", - pcb->snd_wnd, pcb->cwnd, wnd, - ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len, - ntohl(seg->tcphdr->seqno), pcb->lastack)); - } -#endif /* TCP_CWND_DEBUG */ - /* data available and window allows it to be sent? */ - while (seg != NULL && - ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) { -#if TCP_CWND_DEBUG - LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"U32_F", cwnd %"U16_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F", i %"S16_F"\n", - pcb->snd_wnd, pcb->cwnd, wnd, - ntohl(seg->tcphdr->seqno) + seg->len - - pcb->lastack, - ntohl(seg->tcphdr->seqno), pcb->lastack, i)); - ++i; -#endif /* TCP_CWND_DEBUG */ - - pcb->unsent = seg->next; - - if (pcb->state != SYN_SENT) { - TCPH_SET_FLAG(seg->tcphdr, TCP_ACK); - pcb->flags &= ~(TF_ACK_DELAY | TF_ACK_NOW); - } - - tcp_output_segment(seg, pcb); - pcb->snd_nxt = ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg); - if (TCP_SEQ_LT(pcb->snd_max, pcb->snd_nxt)) { - pcb->snd_max = pcb->snd_nxt; - } - /* put segment on unacknowledged list if length > 0 */ - if (TCP_TCPLEN(seg) > 0) { - seg->next = NULL; - /* unacked list is empty? */ - if (pcb->unacked == NULL) { - pcb->unacked = seg; - useg = seg; - /* unacked list is not empty? */ - } else { - /* In the case of fast retransmit, the packet should not go to the tail - * of the unacked queue, but rather at the head. We need to check for - * this case. -STJ Jul 27, 2004 */ - if (TCP_SEQ_LT(ntohl(seg->tcphdr->seqno), ntohl(useg->tcphdr->seqno))){ - /* add segment to head of unacked list */ - seg->next = pcb->unacked; - pcb->unacked = seg; - } else { - /* add segment to tail of unacked list */ - useg->next = seg; - useg = useg->next; - } - } - /* do not queue empty segments on the unacked list */ - } else { - tcp_seg_free(seg); - } - seg = pcb->unsent; - } - return ERR_OK; -} - -/** - * Actually send a TCP segment over IP - */ -static void -tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb) -{ - u16_t len; - struct netif *netif; - - /* The TCP header has already been constructed, but the ackno and - wnd fields remain. */ - seg->tcphdr->ackno = htonl(pcb->rcv_nxt); - - /* silly window avoidance */ - if (pcb->rcv_wnd < pcb->mss) { - seg->tcphdr->wnd = 0; - } else { - /* advertise our receive window size in this TCP segment */ - seg->tcphdr->wnd = htons(pcb->rcv_wnd); - } - - /* If we don't have a local IP address, we get one by - calling ip_route(). */ - if (ip_addr_isany(&(pcb->local_ip))) { - netif = ip_route(&(pcb->remote_ip)); - if (netif == NULL) { - return; - } - ip_addr_set(&(pcb->local_ip), &(netif->ip_addr)); - } - - pcb->rtime = 0; - - if (pcb->rttest == 0) { - pcb->rttest = tcp_ticks; - pcb->rtseq = ntohl(seg->tcphdr->seqno); - - LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %"U32_F"\n", pcb->rtseq)); - } - LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n", - htonl(seg->tcphdr->seqno), htonl(seg->tcphdr->seqno) + - seg->len)); - - len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload); - - seg->p->len -= len; - seg->p->tot_len -= len; - - seg->p->payload = seg->tcphdr; - - seg->tcphdr->chksum = 0; -#if CHECKSUM_GEN_TCP - seg->tcphdr->chksum = inet_chksum_pseudo(seg->p, - &(pcb->local_ip), - &(pcb->remote_ip), - IP_PROTO_TCP, seg->p->tot_len); -#endif - TCP_STATS_INC(tcp.xmit); - - ip_output(seg->p, &(pcb->local_ip), &(pcb->remote_ip), pcb->ttl, pcb->tos, - IP_PROTO_TCP); -} - -void -tcp_rst(u32_t seqno, u32_t ackno, - struct ip_addr *local_ip, struct ip_addr *remote_ip, - u16_t local_port, u16_t remote_port) -{ - struct pbuf *p; - struct tcp_hdr *tcphdr; - p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); - if (p == NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n")); - return; - } - - tcphdr = p->payload; - tcphdr->src = htons(local_port); - tcphdr->dest = htons(remote_port); - tcphdr->seqno = htonl(seqno); - tcphdr->ackno = htonl(ackno); - TCPH_FLAGS_SET(tcphdr, TCP_RST | TCP_ACK); - tcphdr->wnd = htons(TCP_WND); - tcphdr->urgp = 0; - TCPH_HDRLEN_SET(tcphdr, 5); - - tcphdr->chksum = 0; -#if CHECKSUM_GEN_TCP - tcphdr->chksum = inet_chksum_pseudo(p, local_ip, remote_ip, - IP_PROTO_TCP, p->tot_len); -#endif - TCP_STATS_INC(tcp.xmit); - /* Send output with hardcoded TTL since we have no access to the pcb */ - ip_output(p, local_ip, remote_ip, TCP_TTL, 0, IP_PROTO_TCP); - pbuf_free(p); - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno)); -} - -/* requeue all unacked segments for retransmission */ -void -tcp_rexmit_rto(struct tcp_pcb *pcb) -{ - struct tcp_seg *seg; - - if (pcb->unacked == NULL) { - return; - } - - /* Move all unacked segments to the head of the unsent queue */ - for (seg = pcb->unacked; seg->next != NULL; seg = seg->next); - /* concatenate unsent queue after unacked queue */ - seg->next = pcb->unsent; - /* unsent queue is the concatenated queue (of unacked, unsent) */ - pcb->unsent = pcb->unacked; - /* unacked queue is now empty */ - pcb->unacked = NULL; - - pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno); - /* increment number of retransmissions */ - ++pcb->nrtx; - - /* Don't take any RTT measurements after retransmitting. */ - pcb->rttest = 0; - - /* Do the actual retransmission */ - tcp_output(pcb); -} - -void -tcp_rexmit(struct tcp_pcb *pcb) -{ - struct tcp_seg *seg; - - if (pcb->unacked == NULL) { - return; - } - - /* Move the first unacked segment to the unsent queue */ - seg = pcb->unacked->next; - pcb->unacked->next = pcb->unsent; - pcb->unsent = pcb->unacked; - pcb->unacked = seg; - - pcb->snd_nxt = ntohl(pcb->unsent->tcphdr->seqno); - - ++pcb->nrtx; - - /* Don't take any rtt measurements after retransmitting. */ - pcb->rttest = 0; - - /* Do the actual retransmission. */ - tcp_output(pcb); - -} - - -void -tcp_keepalive(struct tcp_pcb *pcb) -{ - struct pbuf *p; - struct tcp_hdr *tcphdr; - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", - ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), - ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip))); - - LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F" pcb->tmr %"U32_F" pcb->keep_cnt %"U16_F"\n", tcp_ticks, pcb->tmr, pcb->keep_cnt)); - - p = pbuf_alloc(PBUF_IP, TCP_HLEN, PBUF_RAM); - - if(p == NULL) { - LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: could not allocate memory for pbuf\n")); - return; - } - - tcphdr = p->payload; - tcphdr->src = htons(pcb->local_port); - tcphdr->dest = htons(pcb->remote_port); - tcphdr->seqno = htonl(pcb->snd_nxt - 1); - tcphdr->ackno = htonl(pcb->rcv_nxt); - tcphdr->wnd = htons(pcb->rcv_wnd); - tcphdr->urgp = 0; - TCPH_HDRLEN_SET(tcphdr, 5); - - tcphdr->chksum = 0; -#if CHECKSUM_GEN_TCP - tcphdr->chksum = inet_chksum_pseudo(p, &pcb->local_ip, &pcb->remote_ip, IP_PROTO_TCP, p->tot_len); -#endif - TCP_STATS_INC(tcp.xmit); - - /* Send output to IP */ - ip_output(p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, 0, IP_PROTO_TCP); - - pbuf_free(p); - - LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F".\n", pcb->snd_nxt - 1, pcb->rcv_nxt)); -} - -#endif /* LWIP_TCP */ - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/udp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/udp.c deleted file mode 100644 index d1e0eacac..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/core/udp.c +++ /dev/null @@ -1,655 +0,0 @@ -/** - * @file - * User Datagram Protocol module - * - */ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - - -/* udp.c - * - * The code for the User Datagram Protocol UDP. - * - */ - -#include - -#include "lwip/opt.h" - -#include "lwip/def.h" -#include "lwip/memp.h" -#include "lwip/inet.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/udp.h" -#include "lwip/icmp.h" - -#include "lwip/stats.h" - -#include "arch/perf.h" -#include "lwip/snmp.h" - -/* The list of UDP PCBs */ -#if LWIP_UDP -/* was static, but we may want to access this from a socket layer */ -struct udp_pcb *udp_pcbs = NULL; - -static struct udp_pcb *pcb_cache = NULL; - -void -udp_init(void) -{ - udp_pcbs = pcb_cache = NULL; -} - -/** - * Process an incoming UDP datagram. - * - * Given an incoming UDP datagram (as a chain of pbufs) this function - * finds a corresponding UDP PCB and - * - * @param pbuf pbuf to be demultiplexed to a UDP PCB. - * @param netif network interface on which the datagram was received. - * - */ -void -udp_input(struct pbuf *p, struct netif *inp) -{ - struct udp_hdr *udphdr; - struct udp_pcb *pcb; - struct udp_pcb *uncon_pcb; - struct ip_hdr *iphdr; - u16_t src, dest; - u8_t local_match; - - PERF_START; - - UDP_STATS_INC(udp.recv); - - iphdr = p->payload; - - if (pbuf_header(p, -((s16_t)(UDP_HLEN + IPH_HL(iphdr) * 4)))) { - /* drop short packets */ - LWIP_DEBUGF(UDP_DEBUG, ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len)); - UDP_STATS_INC(udp.lenerr); - UDP_STATS_INC(udp.drop); - snmp_inc_udpinerrors(); - pbuf_free(p); - goto end; - } - - udphdr = (struct udp_hdr *)((u8_t *)p->payload - UDP_HLEN); - - LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len)); - - src = ntohs(udphdr->src); - dest = ntohs(udphdr->dest); - - udp_debug_print(udphdr); - - /* print the UDP source and destination */ - LWIP_DEBUGF(UDP_DEBUG, ("udp (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") <-- (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n", - ip4_addr1(&iphdr->dest), ip4_addr2(&iphdr->dest), - ip4_addr3(&iphdr->dest), ip4_addr4(&iphdr->dest), ntohs(udphdr->dest), - ip4_addr1(&iphdr->src), ip4_addr2(&iphdr->src), - ip4_addr3(&iphdr->src), ip4_addr4(&iphdr->src), ntohs(udphdr->src))); - - local_match = 0; - uncon_pcb = NULL; - /* Iterate through the UDP pcb list for a matching pcb */ - for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { - /* print the PCB local and remote address */ - LWIP_DEBUGF(UDP_DEBUG, ("pcb (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F") --- (%"U16_F".%"U16_F".%"U16_F".%"U16_F", %"U16_F")\n", - ip4_addr1(&pcb->local_ip), ip4_addr2(&pcb->local_ip), - ip4_addr3(&pcb->local_ip), ip4_addr4(&pcb->local_ip), pcb->local_port, - ip4_addr1(&pcb->remote_ip), ip4_addr2(&pcb->remote_ip), - ip4_addr3(&pcb->remote_ip), ip4_addr4(&pcb->remote_ip), pcb->remote_port)); - - /* compare PCB local addr+port to UDP destination addr+port */ - if ((pcb->local_port == dest) && - (ip_addr_isany(&pcb->local_ip) || - ip_addr_cmp(&(pcb->local_ip), &(iphdr->dest)))) { - local_match = 1; - if ((uncon_pcb == NULL) && - ((pcb->flags & UDP_FLAGS_CONNECTED) == 0)) { - /* the first unconnected matching PCB */ - uncon_pcb = pcb; - } - } - /* compare PCB remote addr+port to UDP source addr+port */ - if ((local_match != 0) && - (pcb->remote_port == src) && - (ip_addr_isany(&pcb->remote_ip) || - ip_addr_cmp(&(pcb->remote_ip), &(iphdr->src)))) { - /* the first fully matching PCB */ - break; - } - } - /* no fully matching pcb found? then look for an unconnected pcb */ - if (pcb == NULL) { - pcb = uncon_pcb; - } - - /* Check checksum if this is a match or if it was directed at us. */ - if (pcb != NULL || ip_addr_cmp(&inp->ip_addr, &iphdr->dest)) - { - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: calculating checksum\n")); - pbuf_header(p, UDP_HLEN); -#ifdef IPv6 - if (iphdr->nexthdr == IP_PROTO_UDPLITE) { -#else - if (IPH_PROTO(iphdr) == IP_PROTO_UDPLITE) { -#endif /* IPv4 */ - /* Do the UDP Lite checksum */ -#if CHECKSUM_CHECK_UDP - if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), - (struct ip_addr *)&(iphdr->dest), - IP_PROTO_UDPLITE, ntohs(udphdr->len)) != 0) { - LWIP_DEBUGF(UDP_DEBUG | 2, ("udp_input: UDP Lite datagram discarded due to failing checksum\n")); - UDP_STATS_INC(udp.chkerr); - UDP_STATS_INC(udp.drop); - snmp_inc_udpinerrors(); - pbuf_free(p); - goto end; - } -#endif - } else { -#if CHECKSUM_CHECK_UDP - if (udphdr->chksum != 0) { - if (inet_chksum_pseudo(p, (struct ip_addr *)&(iphdr->src), - (struct ip_addr *)&(iphdr->dest), - IP_PROTO_UDP, p->tot_len) != 0) { - LWIP_DEBUGF(UDP_DEBUG | 2, ("udp_input: UDP datagram discarded due to failing checksum\n")); - - UDP_STATS_INC(udp.chkerr); - UDP_STATS_INC(udp.drop); - snmp_inc_udpinerrors(); - pbuf_free(p); - goto end; - } - } -#endif - } - pbuf_header(p, -UDP_HLEN); - if (pcb != NULL) { - snmp_inc_udpindatagrams(); - /* callback */ - if (pcb->recv != NULL) - { - pcb->recv(pcb->recv_arg, pcb, p, &(iphdr->src), src); - } - } else { - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE, ("udp_input: not for us.\n")); - - /* No match was found, send ICMP destination port unreachable unless - destination address was broadcast/multicast. */ - - if (!ip_addr_isbroadcast(&iphdr->dest, inp) && - !ip_addr_ismulticast(&iphdr->dest)) { - - /* adjust pbuf pointer */ - p->payload = iphdr; - icmp_dest_unreach(p, ICMP_DUR_PORT); - } - UDP_STATS_INC(udp.proterr); - UDP_STATS_INC(udp.drop); - snmp_inc_udpnoports(); - pbuf_free(p); - } - } else { - pbuf_free(p); - } - end: - - PERF_STOP("udp_input"); -} - -/** - * Send data to a specified address using UDP. - * - * @param pcb UDP PCB used to send the data. - * @param pbuf chain of pbuf's to be sent. - * @param dst_ip Destination IP address. - * @param dst_port Destination UDP port. - * - * If the PCB already has a remote address association, it will - * be restored after the data is sent. - * - * @return lwIP error code. - * - ERR_OK. Successful. No error occured. - * - ERR_MEM. Out of memory. - * - ERR_RTE. Could not find route to destination address. - * - * @see udp_disconnect() udp_send() - */ -err_t -udp_sendto(struct udp_pcb *pcb, struct pbuf *p, - struct ip_addr *dst_ip, u16_t dst_port) -{ - err_t err; - /* temporary space for current PCB remote address */ - struct ip_addr pcb_remote_ip; - u16_t pcb_remote_port; - /* remember current remote peer address of PCB */ - pcb_remote_ip.addr = pcb->remote_ip.addr; - pcb_remote_port = pcb->remote_port; - /* copy packet destination address to PCB remote peer address */ - pcb->remote_ip.addr = dst_ip->addr; - pcb->remote_port = dst_port; - /* send to the packet destination address */ - err = udp_send(pcb, p); - /* restore PCB remote peer address */ - pcb->remote_ip.addr = pcb_remote_ip.addr; - pcb->remote_port = pcb_remote_port; - return err; -} - -/** - * Send data using UDP. - * - * @param pcb UDP PCB used to send the data. - * @param pbuf chain of pbuf's to be sent. - * - * @return lwIP error code. - * - ERR_OK. Successful. No error occured. - * - ERR_MEM. Out of memory. - * - ERR_RTE. Could not find route to destination address. - * - * @see udp_disconnect() udp_sendto() - */ -err_t -udp_send(struct udp_pcb *pcb, struct pbuf *p) -{ - struct udp_hdr *udphdr; - struct netif *netif; - struct ip_addr *src_ip; - err_t err; - struct pbuf *q; /* q will be sent down the stack */ - - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_send\n")); - - /* if the PCB is not yet bound to a port, bind it here */ - if (pcb->local_port == 0) { - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: not yet bound to a port, binding now\n")); - err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); - if (err != ERR_OK) { - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: forced port bind failed\n")); - return err; - } - } - /* find the outgoing network interface for this packet */ - netif = ip_route(&(pcb->remote_ip)); - /* no outgoing network interface could be found? */ - if (netif == NULL) { - LWIP_DEBUGF(UDP_DEBUG | 1, ("udp_send: No route to 0x%"X32_F"\n", pcb->remote_ip.addr)); - UDP_STATS_INC(udp.rterr); - return ERR_RTE; - } - - /* not enough space to add an UDP header to first pbuf in given p chain? */ - if (pbuf_header(p, UDP_HLEN)) { - /* allocate header in a seperate new pbuf */ - q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM); - /* new header pbuf could not be allocated? */ - if (q == NULL) { - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 2, ("udp_send: could not allocate header\n")); - return ERR_MEM; - } - /* chain header q in front of given pbuf p */ - pbuf_chain(q, p); - /* { first pbuf q points to header pbuf } */ - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); - /* adding a header within p succeeded */ - } else { - /* first pbuf q equals given pbuf */ - q = p; - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p)); - } - /* { q now represents the packet to be sent } */ - udphdr = q->payload; - udphdr->src = htons(pcb->local_port); - udphdr->dest = htons(pcb->remote_port); - /* in UDP, 0 checksum means 'no checksum' */ - udphdr->chksum = 0x0000; - - /* PCB local address is IP_ANY_ADDR? */ - if (ip_addr_isany(&pcb->local_ip)) { - /* use outgoing network interface IP address as source address */ - src_ip = &(netif->ip_addr); - } else { - /* use UDP PCB local IP address as source address */ - src_ip = &(pcb->local_ip); - } - - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %"U16_F"\n", q->tot_len)); - - /* UDP Lite protocol? */ - if (pcb->flags & UDP_FLAGS_UDPLITE) { - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %"U16_F"\n", q->tot_len)); - /* set UDP message length in UDP header */ - udphdr->len = htons(pcb->chksum_len); - /* calculate checksum */ -#if CHECKSUM_GEN_UDP - udphdr->chksum = inet_chksum_pseudo(q, src_ip, &(pcb->remote_ip), - IP_PROTO_UDP, pcb->chksum_len); - /* chksum zero must become 0xffff, as zero means 'no checksum' */ - if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff; -#else - udphdr->chksum = 0x0000; -#endif - /* output to IP */ - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDPLITE,)\n")); - err = ip_output_if (q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDPLITE, netif); - /* UDP */ - } else { - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len)); - udphdr->len = htons(q->tot_len); - /* calculate checksum */ -#if CHECKSUM_GEN_UDP - if ((pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) { - udphdr->chksum = inet_chksum_pseudo(q, src_ip, &pcb->remote_ip, IP_PROTO_UDP, q->tot_len); - /* chksum zero must become 0xffff, as zero means 'no checksum' */ - if (udphdr->chksum == 0x0000) udphdr->chksum = 0xffff; - } -#else - udphdr->chksum = 0x0000; -#endif - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum)); - LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,IP_PROTO_UDP,)\n")); - /* output to IP */ - err = ip_output_if(q, src_ip, &pcb->remote_ip, pcb->ttl, pcb->tos, IP_PROTO_UDP, netif); - } - /* TODO: must this be increased even if error occured? */ - snmp_inc_udpoutdatagrams(); - - /* did we chain a seperate header pbuf earlier? */ - if (q != p) { - /* free the header pbuf */ - pbuf_free(q); q = NULL; - /* { p is still referenced by the caller, and will live on } */ - } - - UDP_STATS_INC(udp.xmit); - return err; -} - -/** - * Bind an UDP PCB. - * - * @param pcb UDP PCB to be bound with a local address ipaddr and port. - * @param ipaddr local IP address to bind with. Use IP_ADDR_ANY to - * bind to all local interfaces. - * @param port local UDP port to bind with. - * - * @return lwIP error code. - * - ERR_OK. Successful. No error occured. - * - ERR_USE. The specified ipaddr and port are already bound to by - * another UDP PCB. - * - * @see udp_disconnect() - */ -err_t -udp_bind(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) -{ - struct udp_pcb *ipcb; - u8_t rebind; - - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, ("udp_bind(ipaddr = ")); - ip_addr_debug_print(UDP_DEBUG, ipaddr); - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | 3, (", port = %"U16_F")\n", port)); - - rebind = 0; - /* Check for double bind and rebind of the same pcb */ - for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { - /* is this UDP PCB already on active list? */ - if (pcb == ipcb) { - /* pcb may occur at most once in active list */ - LWIP_ASSERT("rebind == 0", rebind == 0); - /* pcb already in list, just rebind */ - rebind = 1; - } - -/* this code does not allow upper layer to share a UDP port for - listening to broadcast or multicast traffic (See SO_REUSE_ADDR and - SO_REUSE_PORT under *BSD). TODO: See where it fits instead, OR - combine with implementation of UDP PCB flags. Leon Woestenberg. */ -#ifdef LWIP_UDP_TODO - /* port matches that of PCB in list? */ - else if ((ipcb->local_port == port) && - /* IP address matches, or one is IP_ADDR_ANY? */ - (ip_addr_isany(&(ipcb->local_ip)) || - ip_addr_isany(ipaddr) || - ip_addr_cmp(&(ipcb->local_ip), ipaddr))) { - /* other PCB already binds to this local IP and port */ - LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: local port %"U16_F" already bound by another pcb\n", port)); - return ERR_USE; - } -#endif - - } - - ip_addr_set(&pcb->local_ip, ipaddr); - /* no port specified? */ - if (port == 0) { -#ifndef UDP_LOCAL_PORT_RANGE_START -#define UDP_LOCAL_PORT_RANGE_START 4096 -#define UDP_LOCAL_PORT_RANGE_END 0x7fff -#endif - port = UDP_LOCAL_PORT_RANGE_START; - ipcb = udp_pcbs; - while ((ipcb != NULL) && (port != UDP_LOCAL_PORT_RANGE_END)) { - if (ipcb->local_port == port) { - port++; - ipcb = udp_pcbs; - } else - ipcb = ipcb->next; - } - if (ipcb != NULL) { - /* no more ports available in local range */ - LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n")); - return ERR_USE; - } - } - pcb->local_port = port; - /* pcb not active yet? */ - if (rebind == 0) { - /* place the PCB on the active list if not already there */ - pcb->next = udp_pcbs; - udp_pcbs = pcb; - } - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_bind: bound to %"U16_F".%"U16_F".%"U16_F".%"U16_F", port %"U16_F"\n", - (u16_t)(ntohl(pcb->local_ip.addr) >> 24 & 0xff), - (u16_t)(ntohl(pcb->local_ip.addr) >> 16 & 0xff), - (u16_t)(ntohl(pcb->local_ip.addr) >> 8 & 0xff), - (u16_t)(ntohl(pcb->local_ip.addr) & 0xff), pcb->local_port)); - return ERR_OK; -} -/** - * Connect an UDP PCB. - * - * This will associate the UDP PCB with the remote address. - * - * @param pcb UDP PCB to be connected with remote address ipaddr and port. - * @param ipaddr remote IP address to connect with. - * @param port remote UDP port to connect with. - * - * @return lwIP error code - * - * @see udp_disconnect() - */ -err_t -udp_connect(struct udp_pcb *pcb, struct ip_addr *ipaddr, u16_t port) -{ - struct udp_pcb *ipcb; - - if (pcb->local_port == 0) { - err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); - if (err != ERR_OK) - return err; - } - - ip_addr_set(&pcb->remote_ip, ipaddr); - pcb->remote_port = port; - pcb->flags |= UDP_FLAGS_CONNECTED; -/** TODO: this functionality belongs in upper layers */ -#ifdef LWIP_UDP_TODO - /* Nail down local IP for netconn_addr()/getsockname() */ - if (ip_addr_isany(&pcb->local_ip) && !ip_addr_isany(&pcb->remote_ip)) { - struct netif *netif; - - if ((netif = ip_route(&(pcb->remote_ip))) == NULL) { - LWIP_DEBUGF(UDP_DEBUG, ("udp_connect: No route to 0x%lx\n", pcb->remote_ip.addr)); - UDP_STATS_INC(udp.rterr); - return ERR_RTE; - } - /** TODO: this will bind the udp pcb locally, to the interface which - is used to route output packets to the remote address. However, we - might want to accept incoming packets on any interface! */ - pcb->local_ip = netif->ip_addr; - } else if (ip_addr_isany(&pcb->remote_ip)) { - pcb->local_ip.addr = 0; - } -#endif - LWIP_DEBUGF(UDP_DEBUG | DBG_TRACE | DBG_STATE, ("udp_connect: connected to %"U16_F".%"U16_F".%"U16_F".%"U16_F",port %"U16_F"\n", - (u16_t)(ntohl(pcb->remote_ip.addr) >> 24 & 0xff), - (u16_t)(ntohl(pcb->remote_ip.addr) >> 16 & 0xff), - (u16_t)(ntohl(pcb->remote_ip.addr) >> 8 & 0xff), - (u16_t)(ntohl(pcb->remote_ip.addr) & 0xff), pcb->remote_port)); - - /* Insert UDP PCB into the list of active UDP PCBs. */ - for(ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { - if (pcb == ipcb) { - /* already on the list, just return */ - return ERR_OK; - } - } - /* PCB not yet on the list, add PCB now */ - pcb->next = udp_pcbs; - udp_pcbs = pcb; - return ERR_OK; -} - -void -udp_disconnect(struct udp_pcb *pcb) -{ - /* reset remote address association */ - ip_addr_set(&pcb->remote_ip, IP_ADDR_ANY); - pcb->remote_port = 0; - /* mark PCB as unconnected */ - pcb->flags &= ~UDP_FLAGS_CONNECTED; -} - -void -udp_recv(struct udp_pcb *pcb, - void (* recv)(void *arg, struct udp_pcb *upcb, struct pbuf *p, - struct ip_addr *addr, u16_t port), - void *recv_arg) -{ - /* remember recv() callback and user data */ - pcb->recv = recv; - pcb->recv_arg = recv_arg; -} -/** - * Remove an UDP PCB. - * - * @param pcb UDP PCB to be removed. The PCB is removed from the list of - * UDP PCB's and the data structure is freed from memory. - * - * @see udp_new() - */ -void -udp_remove(struct udp_pcb *pcb) -{ - struct udp_pcb *pcb2; - /* pcb to be removed is first in list? */ - if (udp_pcbs == pcb) { - /* make list start at 2nd pcb */ - udp_pcbs = udp_pcbs->next; - /* pcb not 1st in list */ - } else for(pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { - /* find pcb in udp_pcbs list */ - if (pcb2->next != NULL && pcb2->next == pcb) { - /* remove pcb from list */ - pcb2->next = pcb->next; - } - } - memp_free(MEMP_UDP_PCB, pcb); -} -/** - * Create a UDP PCB. - * - * @return The UDP PCB which was created. NULL if the PCB data structure - * could not be allocated. - * - * @see udp_remove() - */ -struct udp_pcb * -udp_new(void) { - struct udp_pcb *pcb; - pcb = memp_malloc(MEMP_UDP_PCB); - /* could allocate UDP PCB? */ - if (pcb != NULL) { - /* initialize PCB to all zeroes */ - memset(pcb, 0, sizeof(struct udp_pcb)); - pcb->ttl = UDP_TTL; - } - - - return pcb; -} - -#if UDP_DEBUG -void -udp_debug_print(struct udp_hdr *udphdr) -{ - LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n")); - LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", - ntohs(udphdr->src), ntohs(udphdr->dest))); - LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); - LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | 0x%04"X16_F" | (len, chksum)\n", - ntohs(udphdr->len), ntohs(udphdr->chksum))); - LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); -} -#endif /* UDP_DEBUG */ - -#endif /* LWIP_UDP */ - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv4/lwip/icmp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv4/lwip/icmp.h deleted file mode 100644 index 634405b71..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv4/lwip/icmp.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_ICMP_H__ -#define __LWIP_ICMP_H__ - -#include "lwip/arch.h" - -#include "lwip/opt.h" -#include "lwip/pbuf.h" - -#include "lwip/ip_addr.h" -#include "lwip/netif.h" - -#define ICMP_ER 0 /* echo reply */ -#define ICMP_DUR 3 /* destination unreachable */ -#define ICMP_SQ 4 /* source quench */ -#define ICMP_RD 5 /* redirect */ -#define ICMP_ECHO 8 /* echo */ -#define ICMP_TE 11 /* time exceeded */ -#define ICMP_PP 12 /* parameter problem */ -#define ICMP_TS 13 /* timestamp */ -#define ICMP_TSR 14 /* timestamp reply */ -#define ICMP_IRQ 15 /* information request */ -#define ICMP_IR 16 /* information reply */ - -enum icmp_dur_type { - ICMP_DUR_NET = 0, /* net unreachable */ - ICMP_DUR_HOST = 1, /* host unreachable */ - ICMP_DUR_PROTO = 2, /* protocol unreachable */ - ICMP_DUR_PORT = 3, /* port unreachable */ - ICMP_DUR_FRAG = 4, /* fragmentation needed and DF set */ - ICMP_DUR_SR = 5 /* source route failed */ -}; - -enum icmp_te_type { - ICMP_TE_TTL = 0, /* time to live exceeded in transit */ - ICMP_TE_FRAG = 1 /* fragment reassembly time exceeded */ -}; - -void icmp_input(struct pbuf *p, struct netif *inp); - -void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t); -void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t); - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct icmp_echo_hdr { - PACK_STRUCT_FIELD(u16_t _type_code); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FIELD(u16_t id); - PACK_STRUCT_FIELD(u16_t seqno); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END - -PACK_STRUCT_BEGIN -struct icmp_dur_hdr { - PACK_STRUCT_FIELD(u16_t _type_code); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FIELD(u32_t unused); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END - -PACK_STRUCT_BEGIN -struct icmp_te_hdr { - PACK_STRUCT_FIELD(u16_t _type_code); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FIELD(u32_t unused); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#define ICMPH_TYPE(hdr) (ntohs((hdr)->_type_code) >> 8) -#define ICMPH_CODE(hdr) (ntohs((hdr)->_type_code) & 0xff) - -#define ICMPH_TYPE_SET(hdr, type) ((hdr)->_type_code = htons(ICMPH_CODE(hdr) | ((type) << 8))) -#define ICMPH_CODE_SET(hdr, code) ((hdr)->_type_code = htons((code) | (ICMPH_TYPE(hdr) << 8))) - -#endif /* __LWIP_ICMP_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv4/lwip/inet.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv4/lwip/inet.h deleted file mode 100644 index 6d79aab7a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv4/lwip/inet.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_INET_H__ -#define __LWIP_INET_H__ - -#include "lwip/arch.h" - -#include "lwip/opt.h" -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" - -u16_t inet_chksum(void *dataptr, u16_t len); -#if 0 /* optimized routine */ -u16_t inet_chksum4(u8_t *dataptr, u16_t len); -#endif -u16_t inet_chksum_pbuf(struct pbuf *p); -u16_t inet_chksum_pseudo(struct pbuf *p, - struct ip_addr *src, struct ip_addr *dest, - u8_t proto, u16_t proto_len); - -u32_t inet_addr(const char *cp); -s8_t inet_aton(const char *cp, struct in_addr *addr); -char *inet_ntoa(struct in_addr addr); /* returns ptr to static buffer; not reentrant! */ - -#ifdef htons -#undef htons -#endif /* htons */ -#ifdef htonl -#undef htonl -#endif /* htonl */ -#ifdef ntohs -#undef ntohs -#endif /* ntohs */ -#ifdef ntohl -#undef ntohl -#endif /* ntohl */ - -#if BYTE_ORDER == BIG_ENDIAN -#define htons(x) (x) -#define ntohs(x) (x) -#define htonl(x) (x) -#define ntohl(x) (x) -#else -#ifdef LWIP_PREFIX_BYTEORDER_FUNCS -/* workaround for naming collisions on some platforms */ -#define htons lwip_htons -#define ntohs lwip_ntohs -#define htonl lwip_htonl -#define ntohl lwip_ntohl -#endif -u16_t htons(u16_t x); -u16_t ntohs(u16_t x); -u32_t htonl(u32_t x); -u32_t ntohl(u32_t x); -#endif - -#endif /* __LWIP_INET_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv4/lwip/ip.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv4/lwip/ip.h deleted file mode 100644 index 4c15e1a0e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv4/lwip/ip.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_IP_H__ -#define __LWIP_IP_H__ - -#include "lwip/arch.h" - -#include "lwip/def.h" -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" - -#include "lwip/err.h" - - -void ip_init(void); -struct netif *ip_route(struct ip_addr *dest); -err_t ip_input(struct pbuf *p, struct netif *inp); -err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t tos, u8_t proto); -err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t tos, u8_t proto, - struct netif *netif); - -#define IP_HLEN 20 - -#define IP_PROTO_ICMP 1 -#define IP_PROTO_UDP 17 -#define IP_PROTO_UDPLITE 170 -#define IP_PROTO_TCP 6 - -/* This is passed as the destination address to ip_output_if (not - to ip_output), meaning that an IP header already is constructed - in the pbuf. This is used when TCP retransmits. */ -#ifdef IP_HDRINCL -#undef IP_HDRINCL -#endif /* IP_HDRINCL */ -#define IP_HDRINCL NULL - - -/* This is the common part of all PCB types. It needs to be at the - beginning of a PCB type definition. It is located here so that - changes to this common part are made in one location instead of - having to change all PCB structs. */ -#define IP_PCB struct ip_addr local_ip; \ - struct ip_addr remote_ip; \ - /* Socket options */ \ - u16_t so_options; \ - /* Type Of Service */ \ - u8_t tos; \ - /* Time To Live */ \ - u8_t ttl - -/* - * Option flags per-socket. These are the same like SO_XXX. - */ -#define SOF_DEBUG (u16_t)0x0001U /* turn on debugging info recording */ -#define SOF_ACCEPTCONN (u16_t)0x0002U /* socket has had listen() */ -#define SOF_REUSEADDR (u16_t)0x0004U /* allow local address reuse */ -#define SOF_KEEPALIVE (u16_t)0x0008U /* keep connections alive */ -#define SOF_DONTROUTE (u16_t)0x0010U /* just use interface addresses */ -#define SOF_BROADCAST (u16_t)0x0020U /* permit sending of broadcast msgs */ -#define SOF_USELOOPBACK (u16_t)0x0040U /* bypass hardware when possible */ -#define SOF_LINGER (u16_t)0x0080U /* linger on close if data present */ -#define SOF_OOBINLINE (u16_t)0x0100U /* leave received OOB data in line */ -#define SOF_REUSEPORT (u16_t)0x0200U /* allow local address & port reuse */ - - - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ip_hdr { - /* version / header length / type of service */ - PACK_STRUCT_FIELD(u16_t _v_hl_tos); - /* total length */ - PACK_STRUCT_FIELD(u16_t _len); - /* identification */ - PACK_STRUCT_FIELD(u16_t _id); - /* fragment offset field */ - PACK_STRUCT_FIELD(u16_t _offset); -#define IP_RF 0x8000 /* reserved fragment flag */ -#define IP_DF 0x4000 /* dont fragment flag */ -#define IP_MF 0x2000 /* more fragments flag */ -#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ - /* time to live / protocol*/ - PACK_STRUCT_FIELD(u16_t _ttl_proto); - /* checksum */ - PACK_STRUCT_FIELD(u16_t _chksum); - /* source and destination IP addresses */ - PACK_STRUCT_FIELD(struct ip_addr src); - PACK_STRUCT_FIELD(struct ip_addr dest); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#define IPH_V(hdr) (ntohs((hdr)->_v_hl_tos) >> 12) -#define IPH_HL(hdr) ((ntohs((hdr)->_v_hl_tos) >> 8) & 0x0f) -#define IPH_TOS(hdr) (ntohs((hdr)->_v_hl_tos) & 0xff) -#define IPH_LEN(hdr) ((hdr)->_len) -#define IPH_ID(hdr) ((hdr)->_id) -#define IPH_OFFSET(hdr) ((hdr)->_offset) -#define IPH_TTL(hdr) (ntohs((hdr)->_ttl_proto) >> 8) -#define IPH_PROTO(hdr) (ntohs((hdr)->_ttl_proto) & 0xff) -#define IPH_CHKSUM(hdr) ((hdr)->_chksum) - -#define IPH_VHLTOS_SET(hdr, v, hl, tos) (hdr)->_v_hl_tos = (htons(((v) << 12) | ((hl) << 8) | (tos))) -#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len) -#define IPH_ID_SET(hdr, id) (hdr)->_id = (id) -#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off) -#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl_proto = (htons(IPH_PROTO(hdr) | ((ttl) << 8))) -#define IPH_PROTO_SET(hdr, proto) (hdr)->_ttl_proto = (htons((proto) | (IPH_TTL(hdr) << 8))) -#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum) - -#if IP_DEBUG -void ip_debug_print(struct pbuf *p); -#else -#define ip_debug_print(p) -#endif /* IP_DEBUG */ - -#endif /* __LWIP_IP_H__ */ - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv4/lwip/ip_addr.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv4/lwip/ip_addr.h deleted file mode 100644 index 2819b1529..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv4/lwip/ip_addr.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_IP_ADDR_H__ -#define __LWIP_IP_ADDR_H__ - -#include "lwip/arch.h" - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ip_addr { - PACK_STRUCT_FIELD(u32_t addr); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ip_addr2 { - PACK_STRUCT_FIELD(u16_t addrw[2]); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/* For compatibility with BSD code */ -struct in_addr { - u32_t s_addr; -}; - -struct netif; - -extern const struct ip_addr ip_addr_any; -extern const struct ip_addr ip_addr_broadcast; - -/** IP_ADDR_ can be used as a fixed IP address - * for the wildcard and the broadcast address - */ -#define IP_ADDR_ANY ((struct ip_addr *)&ip_addr_any) -#define IP_ADDR_BROADCAST ((struct ip_addr *)&ip_addr_broadcast) - -#define INADDR_NONE ((u32_t) 0xffffffff) /* 255.255.255.255 */ -#define INADDR_LOOPBACK ((u32_t) 0x7f000001) /* 127.0.0.1 */ - -/* Definitions of the bits in an Internet address integer. - - On subnets, host and network parts are found according to - the subnet mask, not these masks. */ - -#define IN_CLASSA(a) ((((u32_t)(a)) & 0x80000000) == 0) -#define IN_CLASSA_NET 0xff000000 -#define IN_CLASSA_NSHIFT 24 -#define IN_CLASSA_HOST (0xffffffff & ~IN_CLASSA_NET) -#define IN_CLASSA_MAX 128 - -#define IN_CLASSB(a) ((((u32_t)(a)) & 0xc0000000) == 0x80000000) -#define IN_CLASSB_NET 0xffff0000 -#define IN_CLASSB_NSHIFT 16 -#define IN_CLASSB_HOST (0xffffffff & ~IN_CLASSB_NET) -#define IN_CLASSB_MAX 65536 - -#define IN_CLASSC(a) ((((u32_t)(a)) & 0xe0000000) == 0xc0000000) -#define IN_CLASSC_NET 0xffffff00 -#define IN_CLASSC_NSHIFT 8 -#define IN_CLASSC_HOST (0xffffffff & ~IN_CLASSC_NET) - -#define IN_CLASSD(a) (((u32_t)(a) & 0xf0000000) == 0xe0000000) -#define IN_CLASSD_NET 0xf0000000 /* These ones aren't really */ -#define IN_CLASSD_NSHIFT 28 /* net and host fields, but */ -#define IN_CLASSD_HOST 0x0fffffff /* routing needn't know. */ -#define IN_MULTICAST(a) IN_CLASSD(a) - -#define IN_EXPERIMENTAL(a) (((u32_t)(a) & 0xf0000000) == 0xf0000000) -#define IN_BADCLASS(a) (((u32_t)(a) & 0xf0000000) == 0xf0000000) - -#define IN_LOOPBACKNET 127 /* official! */ - - -#define IP4_ADDR(ipaddr, a,b,c,d) (ipaddr)->addr = htonl(((u32_t)(a & 0xff) << 24) | ((u32_t)(b & 0xff) << 16) | \ - ((u32_t)(c & 0xff) << 8) | (u32_t)(d & 0xff)) - -#define ip_addr_set(dest, src) (dest)->addr = \ - ((src) == NULL? 0:\ - (src)->addr) -/** - * Determine if two address are on the same network. - * - * @arg addr1 IP address 1 - * @arg addr2 IP address 2 - * @arg mask network identifier mask - * @return !0 if the network identifiers of both address match - */ -#define ip_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \ - (mask)->addr) == \ - ((addr2)->addr & \ - (mask)->addr)) -#define ip_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr) - -#define ip_addr_isany(addr1) ((addr1) == NULL || (addr1)->addr == 0) - -u8_t ip_addr_isbroadcast(struct ip_addr *, struct netif *); - -#define ip_addr_ismulticast(addr1) (((addr1)->addr & ntohl(0xf0000000)) == ntohl(0xe0000000)) - - -#define ip_addr_debug_print(debug, ipaddr) LWIP_DEBUGF(debug, ("%"U16_F".%"U16_F".%"U16_F".%"U16_F, \ - ipaddr?(u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff:0, \ - ipaddr?(u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff:0, \ - ipaddr?(u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff:0, \ - ipaddr?(u16_t)ntohl((ipaddr)->addr) & 0xff:0U)) - -/* cast to unsigned int, as it is used as argument to printf functions - * which expect integer arguments. CSi: use cc.h formatters (conversion chars)! */ -#define ip4_addr1(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 24) & 0xff) -#define ip4_addr2(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 16) & 0xff) -#define ip4_addr3(ipaddr) ((u16_t)(ntohl((ipaddr)->addr) >> 8) & 0xff) -#define ip4_addr4(ipaddr) ((u16_t)(ntohl((ipaddr)->addr)) & 0xff) -#endif /* __LWIP_IP_ADDR_H__ */ - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv4/lwip/ip_frag.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv4/lwip/ip_frag.h deleted file mode 100644 index a982c5a63..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv4/lwip/ip_frag.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Jani Monoses - * - */ - -#ifndef __LWIP_IP_FRAG_H__ -#define __LWIP_IP_FRAG_H__ - -#include "lwip/err.h" -#include "lwip/pbuf.h" -#include "lwip/netif.h" -#include "lwip/ip_addr.h" - -void ip_reass_tmr(void); -struct pbuf * ip_reass(struct pbuf *p); -err_t ip_frag(struct pbuf *p, struct netif *netif, struct ip_addr *dest); - -#endif /* __LWIP_IP_FRAG_H__ */ - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv6/lwip/icmp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv6/lwip/icmp.h deleted file mode 100644 index 2b6adb122..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv6/lwip/icmp.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_ICMP_H__ -#define __LWIP_ICMP_H__ - -#include "lwip/arch.h" - -#include "lwip/opt.h" -#include "lwip/pbuf.h" - -#include "lwip/netif.h" - -#define ICMP6_DUR 1 -#define ICMP6_TE 3 -#define ICMP6_ECHO 128 /* echo */ -#define ICMP6_ER 129 /* echo reply */ - - -enum icmp_dur_type { - ICMP_DUR_NET = 0, /* net unreachable */ - ICMP_DUR_HOST = 1, /* host unreachable */ - ICMP_DUR_PROTO = 2, /* protocol unreachable */ - ICMP_DUR_PORT = 3, /* port unreachable */ - ICMP_DUR_FRAG = 4, /* fragmentation needed and DF set */ - ICMP_DUR_SR = 5 /* source route failed */ -}; - -enum icmp_te_type { - ICMP_TE_TTL = 0, /* time to live exceeded in transit */ - ICMP_TE_FRAG = 1 /* fragment reassembly time exceeded */ -}; - -void icmp_input(struct pbuf *p, struct netif *inp); - -void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t); -void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t); - -struct icmp_echo_hdr { - u8_t type; - u8_t icode; - u16_t chksum; - u16_t id; - u16_t seqno; -}; - -struct icmp_dur_hdr { - u8_t type; - u8_t icode; - u16_t chksum; - u32_t unused; -}; - -struct icmp_te_hdr { - u8_t type; - u8_t icode; - u16_t chksum; - u32_t unused; -}; - -#endif /* __LWIP_ICMP_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv6/lwip/inet.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv6/lwip/inet.h deleted file mode 100644 index ae7834364..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv6/lwip/inet.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_INET_H__ -#define __LWIP_INET_H__ - -#include "lwip/arch.h" - -#include "lwip/opt.h" -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" - -u16_t inet_chksum(void *data, u16_t len); -u16_t inet_chksum_pbuf(struct pbuf *p); -u16_t inet_chksum_pseudo(struct pbuf *p, - struct ip_addr *src, struct ip_addr *dest, - u8_t proto, u32_t proto_len); - -u32_t inet_addr(const char *cp); -s8_t inet_aton(const char *cp, struct in_addr *addr); - -#ifndef _MACHINE_ENDIAN_H_ -#ifndef _NETINET_IN_H -#ifndef _LINUX_BYTEORDER_GENERIC_H -u16_t htons(u16_t n); -u16_t ntohs(u16_t n); -u32_t htonl(u32_t n); -u32_t ntohl(u32_t n); -#endif /* _LINUX_BYTEORDER_GENERIC_H */ -#endif /* _NETINET_IN_H */ -#endif /* _MACHINE_ENDIAN_H_ */ - -#endif /* __LWIP_INET_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv6/lwip/ip.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv6/lwip/ip.h deleted file mode 100644 index f46bf9a80..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv6/lwip/ip.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_IP_H__ -#define __LWIP_IP_H__ - -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" - -#include "lwip/err.h" - -#define IP_HLEN 40 - -#define IP_PROTO_ICMP 58 -#define IP_PROTO_UDP 17 -#define IP_PROTO_UDPLITE 170 -#define IP_PROTO_TCP 6 - -/* This is passed as the destination address to ip_output_if (not - to ip_output), meaning that an IP header already is constructed - in the pbuf. This is used when TCP retransmits. */ -#ifdef IP_HDRINCL -#undef IP_HDRINCL -#endif /* IP_HDRINCL */ -#define IP_HDRINCL NULL - - -/* The IPv6 header. */ -struct ip_hdr { -#if BYTE_ORDER == LITTLE_ENDIAN - u8_t tclass1:4, v:4; - u8_t flow1:4, tclass2:4; -#else - u8_t v:4, tclass1:4; - u8_t tclass2:8, flow1:4; -#endif - u16_t flow2; - u16_t len; /* payload length */ - u8_t nexthdr; /* next header */ - u8_t hoplim; /* hop limit (TTL) */ - struct ip_addr src, dest; /* source and destination IP addresses */ -}; - -void ip_init(void); - -#include "lwip/netif.h" - -struct netif *ip_route(struct ip_addr *dest); - -void ip_input(struct pbuf *p, struct netif *inp); - -/* source and destination addresses in network byte order, please */ -err_t ip_output(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t proto); - -err_t ip_output_if(struct pbuf *p, struct ip_addr *src, struct ip_addr *dest, - u8_t ttl, u8_t proto, - struct netif *netif); - -#if IP_DEBUG -void ip_debug_print(struct pbuf *p); -#endif /* IP_DEBUG */ - -#endif /* __LWIP_IP_H__ */ - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv6/lwip/ip_addr.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv6/lwip/ip_addr.h deleted file mode 100644 index db1f09060..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/ipv6/lwip/ip_addr.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_IP_ADDR_H__ -#define __LWIP_IP_ADDR_H__ - -#include "lwip/arch.h" - -#define IP_ADDR_ANY 0 - -struct ip_addr { - u32_t addr[4]; -}; - -#define IP6_ADDR(ipaddr, a,b,c,d,e,f,g,h) do { (ipaddr)->addr[0] = htonl((u32_t)((a & 0xffff) << 16) | (b & 0xffff)); \ - (ipaddr)->addr[1] = htonl(((c & 0xffff) << 16) | (d & 0xffff)); \ - (ipaddr)->addr[2] = htonl(((e & 0xffff) << 16) | (f & 0xffff)); \ - (ipaddr)->addr[3] = htonl(((g & 0xffff) << 16) | (h & 0xffff)); } while(0) - -u8_t ip_addr_netcmp(struct ip_addr *addr1, struct ip_addr *addr2, - struct ip_addr *mask); -u8_t ip_addr_cmp(struct ip_addr *addr1, struct ip_addr *addr2); -void ip_addr_set(struct ip_addr *dest, struct ip_addr *src); -u8_t ip_addr_isany(struct ip_addr *addr); - - -#if IP_DEBUG -void ip_addr_debug_print(struct ip_addr *addr); -#endif /* IP_DEBUG */ - -#endif /* __LWIP_IP_ADDR_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/api.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/api.h deleted file mode 100644 index 7f0ad5966..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/api.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_API_H__ -#define __LWIP_API_H__ - -#include "lwip/opt.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" - -#include "lwip/ip.h" - -#include "lwip/raw.h" -#include "lwip/udp.h" -#include "lwip/tcp.h" - -#include "lwip/err.h" - -#define NETCONN_NOCOPY 0x00 -#define NETCONN_COPY 0x01 - -enum netconn_type { - NETCONN_TCP, - NETCONN_UDP, - NETCONN_UDPLITE, - NETCONN_UDPNOCHKSUM, - NETCONN_RAW -}; - -enum netconn_state { - NETCONN_NONE, - NETCONN_WRITE, - NETCONN_ACCEPT, - NETCONN_RECV, - NETCONN_CONNECT, - NETCONN_CLOSE -}; - -enum netconn_evt { - NETCONN_EVT_RCVPLUS, - NETCONN_EVT_RCVMINUS, - NETCONN_EVT_SENDPLUS, - NETCONN_EVT_SENDMINUS -}; - -struct netbuf { - struct pbuf *p, *ptr; - struct ip_addr *fromaddr; - u16_t fromport; - err_t err; -}; - -struct netconn { - enum netconn_type type; - enum netconn_state state; - union { - struct tcp_pcb *tcp; - struct udp_pcb *udp; - struct raw_pcb *raw; - } pcb; - err_t err; - sys_mbox_t mbox; - sys_mbox_t recvmbox; - sys_mbox_t acceptmbox; - sys_sem_t sem; - int socket; - u16_t recv_avail; - void (* callback)(struct netconn *, enum netconn_evt, u16_t len); -}; - -/* Network buffer functions: */ -struct netbuf * netbuf_new (void); -void netbuf_delete (struct netbuf *buf); -void * netbuf_alloc (struct netbuf *buf, u16_t size); -void netbuf_free (struct netbuf *buf); -void netbuf_ref (struct netbuf *buf, - void *dataptr, u16_t size); -void netbuf_chain (struct netbuf *head, - struct netbuf *tail); - -u16_t netbuf_len (struct netbuf *buf); -err_t netbuf_data (struct netbuf *buf, - void **dataptr, u16_t *len); -s8_t netbuf_next (struct netbuf *buf); -void netbuf_first (struct netbuf *buf); - -void netbuf_copy (struct netbuf *buf, - void *dataptr, u16_t len); -void netbuf_copy_partial(struct netbuf *buf, void *dataptr, - u16_t len, u16_t offset); -struct ip_addr * netbuf_fromaddr (struct netbuf *buf); -u16_t netbuf_fromport (struct netbuf *buf); - -/* Network connection functions: */ -struct netconn * netconn_new (enum netconn_type type); -struct -netconn *netconn_new_with_callback(enum netconn_type t, - void (*callback)(struct netconn *, enum netconn_evt, u16_t len)); -struct -netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u16_t proto, - void (*callback)(struct netconn *, enum netconn_evt, u16_t len)); -err_t netconn_delete (struct netconn *conn); -enum netconn_type netconn_type (struct netconn *conn); -err_t netconn_peer (struct netconn *conn, - struct ip_addr *addr, - u16_t *port); -err_t netconn_addr (struct netconn *conn, - struct ip_addr **addr, - u16_t *port); -err_t netconn_bind (struct netconn *conn, - struct ip_addr *addr, - u16_t port); -err_t netconn_connect (struct netconn *conn, - struct ip_addr *addr, - u16_t port); -err_t netconn_disconnect (struct netconn *conn); -err_t netconn_listen (struct netconn *conn); -struct netconn * netconn_accept (struct netconn *conn); -struct netbuf * netconn_recv (struct netconn *conn); -err_t netconn_send (struct netconn *conn, - struct netbuf *buf); -err_t netconn_write (struct netconn *conn, - void *dataptr, u16_t size, - u8_t copy); -err_t netconn_close (struct netconn *conn); - -err_t netconn_err (struct netconn *conn); - -#endif /* __LWIP_API_H__ */ - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/api_msg.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/api_msg.h deleted file mode 100644 index 3fef3dd0c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/api_msg.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_API_MSG_H__ -#define __LWIP_API_MSG_H__ - -#include "lwip/opt.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" - -#include "lwip/ip.h" - -#include "lwip/udp.h" -#include "lwip/tcp.h" - -#include "lwip/api.h" - -enum api_msg_type { - API_MSG_NEWCONN, - API_MSG_DELCONN, - - API_MSG_BIND, - API_MSG_CONNECT, - API_MSG_DISCONNECT, - - API_MSG_LISTEN, - API_MSG_ACCEPT, - - API_MSG_SEND, - API_MSG_RECV, - API_MSG_WRITE, - - API_MSG_CLOSE, - - API_MSG_MAX -}; - -struct api_msg_msg { - struct netconn *conn; - enum netconn_type conntype; - union { - struct pbuf *p; - struct { - struct ip_addr *ipaddr; - u16_t port; - } bc; - struct { - void *dataptr; - u16_t len; - u8_t copy; - } w; - sys_mbox_t mbox; - u16_t len; - } msg; -}; - -struct api_msg { - enum api_msg_type type; - struct api_msg_msg msg; -}; - -void api_msg_input(struct api_msg *msg); -void api_msg_post(struct api_msg *msg); - -#endif /* __LWIP_API_MSG_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/arch.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/arch.h deleted file mode 100644 index e0d622a4b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/arch.h +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_ARCH_H__ -#define __LWIP_ARCH_H__ - -#ifndef LITTLE_ENDIAN -#define LITTLE_ENDIAN 1234 -#endif - -#ifndef BIG_ENDIAN -#define BIG_ENDIAN 4321 -#endif - -#include "arch/cc.h" - -#ifndef PACK_STRUCT_BEGIN -#define PACK_STRUCT_BEGIN -#endif /* PACK_STRUCT_BEGIN */ - -#ifndef PACK_STRUCT_END -#define PACK_STRUCT_END -#endif /* PACK_STRUCT_END */ - -#ifndef PACK_STRUCT_FIELD -#define PACK_STRUCT_FIELD(x) x -#endif /* PACK_STRUCT_FIELD */ - - - -#ifdef LWIP_PROVIDE_ERRNO - -#define EPERM 1 /* Operation not permitted */ -#define ENOENT 2 /* No such file or directory */ -#define ESRCH 3 /* No such process */ -#define EINTR 4 /* Interrupted system call */ -#define EIO 5 /* I/O error */ -#define ENXIO 6 /* No such device or address */ -#define E2BIG 7 /* Arg list too long */ -#define ENOEXEC 8 /* Exec format error */ -#define EBADF 9 /* Bad file number */ -#define ECHILD 10 /* No child processes */ -#define EAGAIN 11 /* Try again */ -#define ENOMEM 12 /* Out of memory */ -#define EACCES 13 /* Permission denied */ -#define EFAULT 14 /* Bad address */ -#define ENOTBLK 15 /* Block device required */ -#define EBUSY 16 /* Device or resource busy */ -#define EEXIST 17 /* File exists */ -#define EXDEV 18 /* Cross-device link */ -#define ENODEV 19 /* No such device */ -#define ENOTDIR 20 /* Not a directory */ -#define EISDIR 21 /* Is a directory */ -#define EINVAL 22 /* Invalid argument */ -#define ENFILE 23 /* File table overflow */ -#define EMFILE 24 /* Too many open files */ -#define ENOTTY 25 /* Not a typewriter */ -#define ETXTBSY 26 /* Text file busy */ -#define EFBIG 27 /* File too large */ -#define ENOSPC 28 /* No space left on device */ -#define ESPIPE 29 /* Illegal seek */ -#define EROFS 30 /* Read-only file system */ -#define EMLINK 31 /* Too many links */ -#define EPIPE 32 /* Broken pipe */ -#define EDOM 33 /* Math argument out of domain of func */ -#define ERANGE 34 /* Math result not representable */ -#define EDEADLK 35 /* Resource deadlock would occur */ -#define ENAMETOOLONG 36 /* File name too long */ -#define ENOLCK 37 /* No record locks available */ -#define ENOSYS 38 /* Function not implemented */ -#define ENOTEMPTY 39 /* Directory not empty */ -#define ELOOP 40 /* Too many symbolic links encountered */ -#define EWOULDBLOCK EAGAIN /* Operation would block */ -#define ENOMSG 42 /* No message of desired type */ -#define EIDRM 43 /* Identifier removed */ -#define ECHRNG 44 /* Channel number out of range */ -#define EL2NSYNC 45 /* Level 2 not synchronized */ -#define EL3HLT 46 /* Level 3 halted */ -#define EL3RST 47 /* Level 3 reset */ -#define ELNRNG 48 /* Link number out of range */ -#define EUNATCH 49 /* Protocol driver not attached */ -#define ENOCSI 50 /* No CSI structure available */ -#define EL2HLT 51 /* Level 2 halted */ -#define EBADE 52 /* Invalid exchange */ -#define EBADR 53 /* Invalid request descriptor */ -#define EXFULL 54 /* Exchange full */ -#define ENOANO 55 /* No anode */ -#define EBADRQC 56 /* Invalid request code */ -#define EBADSLT 57 /* Invalid slot */ - -#define EDEADLOCK EDEADLK - -#define EBFONT 59 /* Bad font file format */ -#define ENOSTR 60 /* Device not a stream */ -#define ENODATA 61 /* No data available */ -#define ETIME 62 /* Timer expired */ -#define ENOSR 63 /* Out of streams resources */ -#define ENONET 64 /* Machine is not on the network */ -#define ENOPKG 65 /* Package not installed */ -#define EREMOTE 66 /* Object is remote */ -#define ENOLINK 67 /* Link has been severed */ -#define EADV 68 /* Advertise error */ -#define ESRMNT 69 /* Srmount error */ -#define ECOMM 70 /* Communication error on send */ -#define EPROTO 71 /* Protocol error */ -#define EMULTIHOP 72 /* Multihop attempted */ -#define EDOTDOT 73 /* RFS specific error */ -#define EBADMSG 74 /* Not a data message */ -#define EOVERFLOW 75 /* Value too large for defined data type */ -#define ENOTUNIQ 76 /* Name not unique on network */ -#define EBADFD 77 /* File descriptor in bad state */ -#define EREMCHG 78 /* Remote address changed */ -#define ELIBACC 79 /* Can not access a needed shared library */ -#define ELIBBAD 80 /* Accessing a corrupted shared library */ -#define ELIBSCN 81 /* .lib section in a.out corrupted */ -#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ -#define ELIBEXEC 83 /* Cannot exec a shared library directly */ -#define EILSEQ 84 /* Illegal byte sequence */ -#define ERESTART 85 /* Interrupted system call should be restarted */ -#define ESTRPIPE 86 /* Streams pipe error */ -#define EUSERS 87 /* Too many users */ -#define ENOTSOCK 88 /* Socket operation on non-socket */ -#define EDESTADDRREQ 89 /* Destination address required */ -#define EMSGSIZE 90 /* Message too long */ -#define EPROTOTYPE 91 /* Protocol wrong type for socket */ -#define ENOPROTOOPT 92 /* Protocol not available */ -#define EPROTONOSUPPORT 93 /* Protocol not supported */ -#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ -#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ -#define EPFNOSUPPORT 96 /* Protocol family not supported */ -#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ -#define EADDRINUSE 98 /* Address already in use */ -#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ -#define ENETDOWN 100 /* Network is down */ -#define ENETUNREACH 101 /* Network is unreachable */ -#define ENETRESET 102 /* Network dropped connection because of reset */ -#define ECONNABORTED 103 /* Software caused connection abort */ -#define ECONNRESET 104 /* Connection reset by peer */ -#define ENOBUFS 105 /* No buffer space available */ -#define EISCONN 106 /* Transport endpoint is already connected */ -#define ENOTCONN 107 /* Transport endpoint is not connected */ -#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ -#define ETOOMANYREFS 109 /* Too many references: cannot splice */ -#define ETIMEDOUT 110 /* Connection timed out */ -#define ECONNREFUSED 111 /* Connection refused */ -#define EHOSTDOWN 112 /* Host is down */ -#define EHOSTUNREACH 113 /* No route to host */ -#define EALREADY 114 /* Operation already in progress */ -#define EINPROGRESS 115 /* Operation now in progress */ -#define ESTALE 116 /* Stale NFS file handle */ -#define EUCLEAN 117 /* Structure needs cleaning */ -#define ENOTNAM 118 /* Not a XENIX named type file */ -#define ENAVAIL 119 /* No XENIX semaphores available */ -#define EISNAM 120 /* Is a named type file */ -#define EREMOTEIO 121 /* Remote I/O error */ -#define EDQUOT 122 /* Quota exceeded */ - -#define ENOMEDIUM 123 /* No medium found */ -#define EMEDIUMTYPE 124 /* Wrong medium type */ - - -#define ENSROK 0 /* DNS server returned answer with no data */ -#define ENSRNODATA 160 /* DNS server returned answer with no data */ -#define ENSRFORMERR 161 /* DNS server claims query was misformatted */ -#define ENSRSERVFAIL 162 /* DNS server returned general failure */ -#define ENSRNOTFOUND 163 /* Domain name not found */ -#define ENSRNOTIMP 164 /* DNS server does not implement requested operation */ -#define ENSRREFUSED 165 /* DNS server refused query */ -#define ENSRBADQUERY 166 /* Misformatted DNS query */ -#define ENSRBADNAME 167 /* Misformatted domain name */ -#define ENSRBADFAMILY 168 /* Unsupported address family */ -#define ENSRBADRESP 169 /* Misformatted DNS reply */ -#define ENSRCONNREFUSED 170 /* Could not contact DNS servers */ -#define ENSRTIMEOUT 171 /* Timeout while contacting DNS servers */ -#define ENSROF 172 /* End of file */ -#define ENSRFILE 173 /* Error reading file */ -#define ENSRNOMEM 174 /* Out of memory */ -#define ENSRDESTRUCTION 175 /* Application terminated lookup */ -#define ENSRQUERYDOMAINTOOLONG 176 /* Domain name is too long */ -#define ENSRCNAMELOOP 177 /* Domain name is too long */ - -#ifndef errno -extern int errno; -#endif - -#endif /* LWIP_PROVIDE_ERRNO */ - -#endif /* __LWIP_ARCH_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/debug.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/debug.h deleted file mode 100644 index 8f63a7b62..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/debug.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_DEBUG_H__ -#define __LWIP_DEBUG_H__ - -#include "arch/cc.h" - -/** lower two bits indicate debug level - * - 0 off - * - 1 warning - * - 2 serious - * - 3 severe - */ - -#define DBG_LEVEL_OFF 0 -#define DBG_LEVEL_WARNING 1 /* bad checksums, dropped packets, ... */ -#define DBG_LEVEL_SERIOUS 2 /* memory allocation failures, ... */ -#define DBG_LEVEL_SEVERE 3 /* */ -#define DBG_MASK_LEVEL 3 - -/** flag for LWIP_DEBUGF to enable that debug message */ -#define DBG_ON 0x80U -/** flag for LWIP_DEBUGF to disable that debug message */ -#define DBG_OFF 0x00U - -/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */ -#define DBG_TRACE 0x40U -/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */ -#define DBG_STATE 0x20U -/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */ -#define DBG_FRESH 0x10U -/** flag for LWIP_DEBUGF to halt after printing this debug message */ -#define DBG_HALT 0x08U - -#ifndef LWIP_NOASSERT -# define LWIP_ASSERT(x,y) do { if(!(y)) LWIP_PLATFORM_ASSERT(x); } while(0) -#else -# define LWIP_ASSERT(x,y) -#endif - -#ifdef LWIP_DEBUG -/** print debug message only if debug message type is enabled... - * AND is of correct type AND is at least DBG_LEVEL - */ -# define LWIP_DEBUGF(debug,x) do { if (((debug) & DBG_ON) && ((debug) & DBG_TYPES_ON) && ((s16_t)((debug) & DBG_MASK_LEVEL) >= DBG_MIN_LEVEL)) { LWIP_PLATFORM_DIAG(x); if ((debug) & DBG_HALT) while(1); } } while(0) -# define LWIP_ERROR(x) do { LWIP_PLATFORM_DIAG(x); } while(0) -#else /* LWIP_DEBUG */ -# define LWIP_DEBUGF(debug,x) -# define LWIP_ERROR(x) -#endif /* LWIP_DEBUG */ - -#endif /* __LWIP_DEBUG_H__ */ - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/def.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/def.h deleted file mode 100644 index eba9b8774..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/def.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_DEF_H__ -#define __LWIP_DEF_H__ - -/* this might define NULL already */ -#include "arch/cc.h" - -#define LWIP_MAX(x , y) (x) > (y) ? (x) : (y) -#define LWIP_MIN(x , y) (x) < (y) ? (x) : (y) - -#ifndef NULL -#define NULL ((void *)0) -#endif - - -#endif /* __LWIP_DEF_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/dhcp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/dhcp.h deleted file mode 100644 index bfe753f26..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/dhcp.h +++ /dev/null @@ -1,223 +0,0 @@ -/** @file - */ - -#ifndef __LWIP_DHCP_H__ -#define __LWIP_DHCP_H__ - -#include "lwip/opt.h" -#include "lwip/netif.h" -#include "lwip/udp.h" - -/** period (in seconds) of the application calling dhcp_coarse_tmr() */ -#define DHCP_COARSE_TIMER_SECS 60 -/** period (in milliseconds) of the application calling dhcp_fine_tmr() */ -#define DHCP_FINE_TIMER_MSECS 500 - -struct dhcp -{ - /** current DHCP state machine state */ - u8_t state; - /** retries of current request */ - u8_t tries; - /** transaction identifier of last sent request */ - u32_t xid; - /** our connection to the DHCP server */ - struct udp_pcb *pcb; - /** (first) pbuf of incoming msg */ - struct pbuf *p; - /** incoming msg */ - struct dhcp_msg *msg_in; - /** incoming msg options */ - struct dhcp_msg *options_in; - /** ingoing msg options length */ - u16_t options_in_len; - - struct pbuf *p_out; /* pbuf of outcoming msg */ - struct dhcp_msg *msg_out; /* outgoing msg */ - u16_t options_out_len; /* outgoing msg options length */ - u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */ - u16_t t1_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */ - u16_t t2_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */ - struct ip_addr server_ip_addr; /* dhcp server address that offered this lease */ - struct ip_addr offered_ip_addr; - struct ip_addr offered_sn_mask; - struct ip_addr offered_gw_addr; - struct ip_addr offered_bc_addr; -#define DHCP_MAX_DNS 2 - u32_t dns_count; /* actual number of DNS servers obtained */ - struct ip_addr offered_dns_addr[DHCP_MAX_DNS]; /* DNS server addresses */ - - u32_t offered_t0_lease; /* lease period (in seconds) */ - u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */ - u32_t offered_t2_rebind; /* recommended rebind time (usually 66% of lease period) */ -/** Patch #1308 - * TODO: See dhcp.c "TODO"s - */ -#if 0 - struct ip_addr offered_si_addr; - u8_t *boot_file_name; -#endif -}; - -/* MUST be compiled with "pack structs" or equivalent! */ -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -/** minimum set of fields of any DHCP message */ -struct dhcp_msg -{ - PACK_STRUCT_FIELD(u8_t op); - PACK_STRUCT_FIELD(u8_t htype); - PACK_STRUCT_FIELD(u8_t hlen); - PACK_STRUCT_FIELD(u8_t hops); - PACK_STRUCT_FIELD(u32_t xid); - PACK_STRUCT_FIELD(u16_t secs); - PACK_STRUCT_FIELD(u16_t flags); - PACK_STRUCT_FIELD(struct ip_addr ciaddr); - PACK_STRUCT_FIELD(struct ip_addr yiaddr); - PACK_STRUCT_FIELD(struct ip_addr siaddr); - PACK_STRUCT_FIELD(struct ip_addr giaddr); -#define DHCP_CHADDR_LEN 16U - PACK_STRUCT_FIELD(u8_t chaddr[DHCP_CHADDR_LEN]); -#define DHCP_SNAME_LEN 64U - PACK_STRUCT_FIELD(u8_t sname[DHCP_SNAME_LEN]); -#define DHCP_FILE_LEN 128U - PACK_STRUCT_FIELD(u8_t file[DHCP_FILE_LEN]); - PACK_STRUCT_FIELD(u32_t cookie); -#define DHCP_MIN_OPTIONS_LEN 68U -/** make sure user does not configure this too small */ -#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN)) -# undef DHCP_OPTIONS_LEN -#endif -/** allow this to be configured in lwipopts.h, but not too small */ -#if (!defined(DHCP_OPTIONS_LEN)) -/** set this to be sufficient for your options in outgoing DHCP msgs */ -# define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN -#endif - PACK_STRUCT_FIELD(u8_t options[DHCP_OPTIONS_LEN]); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/** start DHCP configuration */ -err_t dhcp_start(struct netif *netif); -/** enforce early lease renewal (not needed normally)*/ -err_t dhcp_renew(struct netif *netif); -/** release the DHCP lease, usually called before dhcp_stop()*/ -err_t dhcp_release(struct netif *netif); -/** stop DHCP configuration */ -void dhcp_stop(struct netif *netif); -/** inform server of our manual IP address */ -void dhcp_inform(struct netif *netif); - -/** if enabled, check whether the offered IP address is not in use, using ARP */ -#if DHCP_DOES_ARP_CHECK -void dhcp_arp_reply(struct netif *netif, struct ip_addr *addr); -#endif - -/** to be called every minute */ -void dhcp_coarse_tmr(void); -/** to be called every half second */ -void dhcp_fine_tmr(void); - -/** DHCP message item offsets and length */ -#define DHCP_MSG_OFS (UDP_DATA_OFS) - #define DHCP_OP_OFS (DHCP_MSG_OFS + 0) - #define DHCP_HTYPE_OFS (DHCP_MSG_OFS + 1) - #define DHCP_HLEN_OFS (DHCP_MSG_OFS + 2) - #define DHCP_HOPS_OFS (DHCP_MSG_OFS + 3) - #define DHCP_XID_OFS (DHCP_MSG_OFS + 4) - #define DHCP_SECS_OFS (DHCP_MSG_OFS + 8) - #define DHCP_FLAGS_OFS (DHCP_MSG_OFS + 10) - #define DHCP_CIADDR_OFS (DHCP_MSG_OFS + 12) - #define DHCP_YIADDR_OFS (DHCP_MSG_OFS + 16) - #define DHCP_SIADDR_OFS (DHCP_MSG_OFS + 20) - #define DHCP_GIADDR_OFS (DHCP_MSG_OFS + 24) - #define DHCP_CHADDR_OFS (DHCP_MSG_OFS + 28) - #define DHCP_SNAME_OFS (DHCP_MSG_OFS + 44) - #define DHCP_FILE_OFS (DHCP_MSG_OFS + 108) -#define DHCP_MSG_LEN 236 - -#define DHCP_COOKIE_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN) -#define DHCP_OPTIONS_OFS (DHCP_MSG_OFS + DHCP_MSG_LEN + 4) - -#define DHCP_CLIENT_PORT 68 -#define DHCP_SERVER_PORT 67 - -/** DHCP client states */ -#define DHCP_REQUESTING 1 -#define DHCP_INIT 2 -#define DHCP_REBOOTING 3 -#define DHCP_REBINDING 4 -#define DHCP_RENEWING 5 -#define DHCP_SELECTING 6 -#define DHCP_INFORMING 7 -#define DHCP_CHECKING 8 -#define DHCP_PERMANENT 9 -#define DHCP_BOUND 10 -/** not yet implemented #define DHCP_RELEASING 11 */ -#define DHCP_BACKING_OFF 12 -#define DHCP_OFF 13 - -#define DHCP_BOOTREQUEST 1 -#define DHCP_BOOTREPLY 2 - -#define DHCP_DISCOVER 1 -#define DHCP_OFFER 2 -#define DHCP_REQUEST 3 -#define DHCP_DECLINE 4 -#define DHCP_ACK 5 -#define DHCP_NAK 6 -#define DHCP_RELEASE 7 -#define DHCP_INFORM 8 - -#define DHCP_HTYPE_ETH 1 - -#define DHCP_HLEN_ETH 6 - -#define DHCP_BROADCAST_FLAG 15 -#define DHCP_BROADCAST_MASK (1 << DHCP_FLAG_BROADCAST) - -/** BootP options */ -#define DHCP_OPTION_PAD 0 -#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */ -#define DHCP_OPTION_ROUTER 3 -#define DHCP_OPTION_DNS_SERVER 6 -#define DHCP_OPTION_HOSTNAME 12 -#define DHCP_OPTION_IP_TTL 23 -#define DHCP_OPTION_MTU 26 -#define DHCP_OPTION_BROADCAST 28 -#define DHCP_OPTION_TCP_TTL 37 -#define DHCP_OPTION_END 255 - -/** DHCP options */ -#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */ -#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */ -#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */ - -#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */ -#define DHCP_OPTION_MESSAGE_TYPE_LEN 1 - - -#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */ -#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */ - -#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */ -#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2 - -#define DHCP_OPTION_T1 58 /* T1 renewal time */ -#define DHCP_OPTION_T2 59 /* T2 rebinding time */ -#define DHCP_OPTION_CLIENT_ID 61 -#define DHCP_OPTION_TFTP_SERVERNAME 66 -#define DHCP_OPTION_BOOTFILE 67 - -/** possible combinations of overloading the file and sname fields with options */ -#define DHCP_OVERLOAD_NONE 0 -#define DHCP_OVERLOAD_FILE 1 -#define DHCP_OVERLOAD_SNAME 2 -#define DHCP_OVERLOAD_SNAME_FILE 3 - -#endif /*__LWIP_DHCP_H__*/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/err.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/err.h deleted file mode 100644 index c92cb26d7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/err.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_ERR_H__ -#define __LWIP_ERR_H__ - -#include "lwip/opt.h" - -#include "arch/cc.h" - -typedef s8_t err_t; - -/* Definitions for error constants. */ - -#define ERR_OK 0 /* No error, everything OK. */ -#define ERR_MEM -1 /* Out of memory error. */ -#define ERR_BUF -2 /* Buffer error. */ - - -#define ERR_ABRT -3 /* Connection aborted. */ -#define ERR_RST -4 /* Connection reset. */ -#define ERR_CLSD -5 /* Connection closed. */ -#define ERR_CONN -6 /* Not connected. */ - -#define ERR_VAL -7 /* Illegal value. */ - -#define ERR_ARG -8 /* Illegal argument. */ - -#define ERR_RTE -9 /* Routing problem. */ - -#define ERR_USE -10 /* Address in use. */ - -#define ERR_IF -11 /* Low-level netif error */ -#define ERR_ISCONN -12 /* Already connected. */ - - -#ifdef LWIP_DEBUG -extern char *lwip_strerr(err_t err); -#else -#define lwip_strerr(x) "" -#endif /* LWIP_DEBUG */ -#endif /* __LWIP_ERR_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/mem.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/mem.h deleted file mode 100644 index ee6fea7d8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/mem.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_MEM_H__ -#define __LWIP_MEM_H__ - -#include "lwip/opt.h" -#include "lwip/arch.h" - -#if MEM_SIZE > 64000l -typedef u32_t mem_size_t; -#else -typedef u16_t mem_size_t; -#endif /* MEM_SIZE > 64000 */ - - -void mem_init(void); - -void *mem_malloc(mem_size_t size); -void mem_free(void *mem); -void *mem_realloc(void *mem, mem_size_t size); -void *mem_reallocm(void *mem, mem_size_t size); - -#ifndef MEM_ALIGN_SIZE -#define MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1) & ~(MEM_ALIGNMENT-1)) -#endif - -#ifndef MEM_ALIGN -#define MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1))) -#endif - -#endif /* __LWIP_MEM_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/memp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/memp.h deleted file mode 100644 index 1cd46fa3f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/memp.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef __LWIP_MEMP_H__ -#define __LWIP_MEMP_H__ - -#include "lwip/opt.h" - -typedef enum { - MEMP_PBUF, - MEMP_RAW_PCB, - MEMP_UDP_PCB, - MEMP_TCP_PCB, - MEMP_TCP_PCB_LISTEN, - MEMP_TCP_SEG, - - MEMP_NETBUF, - MEMP_NETCONN, - MEMP_API_MSG, - MEMP_TCPIP_MSG, - - MEMP_SYS_TIMEOUT, - - MEMP_MAX -} memp_t; - -void memp_init(void); - -void *memp_malloc(memp_t type); -void *memp_realloc(memp_t fromtype, memp_t totype, void *mem); -void memp_free(memp_t type, void *mem); - -#endif /* __LWIP_MEMP_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/netif.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/netif.h deleted file mode 100644 index ff50c6f9c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/netif.h +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_NETIF_H__ -#define __LWIP_NETIF_H__ - -#include "lwip/opt.h" - -#include "lwip/err.h" - -#include "lwip/ip_addr.h" - -#include "lwip/inet.h" -#include "lwip/pbuf.h" -#if LWIP_DHCP -# include "lwip/dhcp.h" -#endif - -/** must be the maximum of all used hardware address lengths - across all types of interfaces in use */ -#define NETIF_MAX_HWADDR_LEN 6U - -/** TODO: define the use (where, when, whom) of netif flags */ - -/** whether the network interface is 'up'. this is - * a software flag used to control whether this network - * interface is enabled and processes traffic. - */ -#define NETIF_FLAG_UP 0x1U -/** if set, the netif has broadcast capability */ -#define NETIF_FLAG_BROADCAST 0x2U -/** if set, the netif is one end of a point-to-point connection */ -#define NETIF_FLAG_POINTTOPOINT 0x4U -/** if set, the interface is configured using DHCP */ -#define NETIF_FLAG_DHCP 0x08U -/** if set, the interface has an active link - * (set by the network interface driver) */ -#define NETIF_FLAG_LINK_UP 0x10U - -/** Generic data structure used for all lwIP network interfaces. - * The following fields should be filled in by the initialization - * function for the device driver: hwaddr_len, hwaddr[], mtu, flags */ - -struct netif { - /** pointer to next in linked list */ - struct netif *next; - - /** IP address configuration in network byte order */ - struct ip_addr ip_addr; - struct ip_addr netmask; - struct ip_addr gw; - - /** This function is called by the network device driver - * to pass a packet up the TCP/IP stack. */ - err_t (* input)(struct pbuf *p, struct netif *inp); - /** This function is called by the IP module when it wants - * to send a packet on the interface. This function typically - * first resolves the hardware address, then sends the packet. */ - err_t (* output)(struct netif *netif, struct pbuf *p, - struct ip_addr *ipaddr); - /** This function is called by the ARP module when it wants - * to send a packet on the interface. This function outputs - * the pbuf as-is on the link medium. */ - err_t (* linkoutput)(struct netif *netif, struct pbuf *p); - /** This field can be set by the device driver and could point - * to state information for the device. */ - void *state; -#if LWIP_DHCP - /** the DHCP client state information for this netif */ - struct dhcp *dhcp; -#endif - /** number of bytes used in hwaddr */ - u8_t hwaddr_len; - /** link level hardware address of this interface */ - u8_t hwaddr[NETIF_MAX_HWADDR_LEN]; - /** maximum transfer unit (in bytes) */ - u16_t mtu; - /** flags (see NETIF_FLAG_ above) */ - u8_t flags; - /** link type */ - u8_t link_type; - /** descriptive abbreviation */ - char name[2]; - /** number of this interface */ - u8_t num; -}; - -/** The list of network interfaces. */ -extern struct netif *netif_list; -/** The default network interface. */ -extern struct netif *netif_default; - -/* netif_init() must be called first. */ -void netif_init(void); - -struct netif *netif_add(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask, - struct ip_addr *gw, - void *state, - err_t (* init)(struct netif *netif), - err_t (* input)(struct pbuf *p, struct netif *netif)); - -void -netif_set_addr(struct netif *netif,struct ip_addr *ipaddr, struct ip_addr *netmask, - struct ip_addr *gw); -void netif_remove(struct netif * netif); - -/* Returns a network interface given its name. The name is of the form - "et0", where the first two letters are the "name" field in the - netif structure, and the digit is in the num field in the same - structure. */ -struct netif *netif_find(char *name); - -void netif_set_default(struct netif *netif); - -void netif_set_ipaddr(struct netif *netif, struct ip_addr *ipaddr); -void netif_set_netmask(struct netif *netif, struct ip_addr *netmast); -void netif_set_gw(struct netif *netif, struct ip_addr *gw); -void netif_set_up(struct netif *netif); -void netif_set_down(struct netif *netif); -u8_t netif_is_up(struct netif *netif); - -#endif /* __LWIP_NETIF_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/opt.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/opt.h deleted file mode 100644 index 45636cb24..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/opt.h +++ /dev/null @@ -1,671 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_OPT_H__ -#define __LWIP_OPT_H__ - -/* Include user defined options first */ -#include "lwipopts.h" -#include "lwip/debug.h" - -/* Define default values for unconfigured parameters. */ - -/* Platform specific locking */ - -/* - * enable SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection - * for certain critical regions during buffer allocation, deallocation and memory - * allocation and deallocation. - */ -#ifndef SYS_LIGHTWEIGHT_PROT -#define SYS_LIGHTWEIGHT_PROT 0 -#endif - -#ifndef NO_SYS -#define NO_SYS 0 -#endif -/* ---------- Memory options ---------- */ -/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which - lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2 - byte alignment -> define MEM_ALIGNMENT to 2. */ - -#ifndef MEM_ALIGNMENT -#define MEM_ALIGNMENT 1 -#endif - -/* MEM_SIZE: the size of the heap memory. If the application will send -a lot of data that needs to be copied, this should be set high. */ -#ifndef MEM_SIZE -#define MEM_SIZE 1600 -#endif - -#ifndef MEMP_SANITY_CHECK -#define MEMP_SANITY_CHECK 0 -#endif - -/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application - sends a lot of data out of ROM (or other static memory), this - should be set high. */ -#ifndef MEMP_NUM_PBUF -#define MEMP_NUM_PBUF 16 -#endif - -/* Number of raw connection PCBs */ -#ifndef MEMP_NUM_RAW_PCB -#define MEMP_NUM_RAW_PCB 4 -#endif - -/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One - per active UDP "connection". */ -#ifndef MEMP_NUM_UDP_PCB -#define MEMP_NUM_UDP_PCB 4 -#endif -/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP - connections. */ -#ifndef MEMP_NUM_TCP_PCB -#define MEMP_NUM_TCP_PCB 5 -#endif -/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP - connections. */ -#ifndef MEMP_NUM_TCP_PCB_LISTEN -#define MEMP_NUM_TCP_PCB_LISTEN 8 -#endif -/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP - segments. */ -#ifndef MEMP_NUM_TCP_SEG -#define MEMP_NUM_TCP_SEG 16 -#endif -/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active - timeouts. */ -#ifndef MEMP_NUM_SYS_TIMEOUT -#define MEMP_NUM_SYS_TIMEOUT 3 -#endif - -/* The following four are used only with the sequential API and can be - set to 0 if the application only will use the raw API. */ -/* MEMP_NUM_NETBUF: the number of struct netbufs. */ -#ifndef MEMP_NUM_NETBUF -#define MEMP_NUM_NETBUF 2 -#endif -/* MEMP_NUM_NETCONN: the number of struct netconns. */ -#ifndef MEMP_NUM_NETCONN -#define MEMP_NUM_NETCONN 4 -#endif -/* MEMP_NUM_APIMSG: the number of struct api_msg, used for - communication between the TCP/IP stack and the sequential - programs. */ -#ifndef MEMP_NUM_API_MSG -#define MEMP_NUM_API_MSG 8 -#endif -/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used - for sequential API communication and incoming packets. Used in - src/api/tcpip.c. */ -#ifndef MEMP_NUM_TCPIP_MSG -#define MEMP_NUM_TCPIP_MSG 8 -#endif - -/* ---------- Pbuf options ---------- */ -/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ - -#ifndef PBUF_POOL_SIZE -#define PBUF_POOL_SIZE 16 -#endif - -/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */ - -#ifndef PBUF_POOL_BUFSIZE -#define PBUF_POOL_BUFSIZE 128 -#endif - -/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a - link level header. Defaults to 14 for Ethernet. */ - -#ifndef PBUF_LINK_HLEN -#define PBUF_LINK_HLEN 14 -#endif - - - -/* ---------- ARP options ---------- */ - -/** Number of active hardware address, IP address pairs cached */ -#ifndef ARP_TABLE_SIZE -#define ARP_TABLE_SIZE 10 -#endif - -/** - * If enabled, outgoing packets are queued during hardware address - * resolution. - * - * This feature has not stabilized yet. Single-packet queueing is - * believed to be stable, multi-packet queueing is believed to - * clash with the TCP segment queueing. - * - * As multi-packet-queueing is currently disabled, enabling this - * _should_ work, but we need your testing feedback on lwip-users. - * - */ -#ifndef ARP_QUEUEING -#define ARP_QUEUEING 1 -#endif - -/* This option is deprecated */ -#ifdef ETHARP_QUEUE_FIRST -#error ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h. -#endif - -/* This option is removed to comply with the ARP standard */ -#ifdef ETHARP_ALWAYS_INSERT -#error ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h. -#endif - -/* ---------- IP options ---------- */ -/* Define IP_FORWARD to 1 if you wish to have the ability to forward - IP packets across network interfaces. If you are going to run lwIP - on a device with only one network interface, define this to 0. */ -#ifndef IP_FORWARD -#define IP_FORWARD 0 -#endif - -/* If defined to 1, IP options are allowed (but not parsed). If - defined to 0, all packets with IP options are dropped. */ -#ifndef IP_OPTIONS -#define IP_OPTIONS 1 -#endif - -/** IP reassembly and segmentation. Even if they both deal with IP - * fragments, note that these are orthogonal, one dealing with incoming - * packets, the other with outgoing packets - */ - -/** Reassemble incoming fragmented IP packets */ -#ifndef IP_REASSEMBLY -#define IP_REASSEMBLY 1 -#endif - -/** Fragment outgoing IP packets if their size exceeds MTU */ -#ifndef IP_FRAG -#define IP_FRAG 1 -#endif - -/* ---------- ICMP options ---------- */ - -#ifndef ICMP_TTL -#define ICMP_TTL 255 -#endif - -/* ---------- RAW options ---------- */ - -#ifndef LWIP_RAW -#define LWIP_RAW 1 -#endif - -#ifndef RAW_TTL -#define RAW_TTL 255 -#endif - -/* ---------- DHCP options ---------- */ - -#ifndef LWIP_DHCP -#define LWIP_DHCP 0 -#endif - -/* 1 if you want to do an ARP check on the offered address - (recommended). */ -#ifndef DHCP_DOES_ARP_CHECK -#define DHCP_DOES_ARP_CHECK 1 -#endif - -/* ---------- UDP options ---------- */ -#ifndef LWIP_UDP -#define LWIP_UDP 1 -#endif - -#ifndef UDP_TTL -#define UDP_TTL 255 -#endif - -/* ---------- TCP options ---------- */ -#ifndef LWIP_TCP -#define LWIP_TCP 1 -#endif - -#ifndef TCP_TTL -#define TCP_TTL 255 -#endif - -#ifndef TCP_WND -#define TCP_WND 2048 -#endif - -#ifndef TCP_MAXRTX -#define TCP_MAXRTX 12 -#endif - -#ifndef TCP_SYNMAXRTX -#define TCP_SYNMAXRTX 6 -#endif - - -/* Controls if TCP should queue segments that arrive out of - order. Define to 0 if your device is low on memory. */ -#ifndef TCP_QUEUE_OOSEQ -#define TCP_QUEUE_OOSEQ 1 -#endif - -/* TCP Maximum segment size. */ -#ifndef TCP_MSS -#define TCP_MSS 128 /* A *very* conservative default. */ -#endif - -/* TCP sender buffer space (bytes). */ -#ifndef TCP_SND_BUF -#define TCP_SND_BUF 256 -#endif - -/* TCP sender buffer space (pbufs). This must be at least = 2 * - TCP_SND_BUF/TCP_MSS for things to work. */ -#ifndef TCP_SND_QUEUELEN -#define TCP_SND_QUEUELEN 4 * TCP_SND_BUF/TCP_MSS -#endif - - -/* Maximum number of retransmissions of data segments. */ - -/* Maximum number of retransmissions of SYN segments. */ - -/* TCP writable space (bytes). This must be less than or equal - to TCP_SND_BUF. It is the amount of space which must be - available in the tcp snd_buf for select to return writable */ -#ifndef TCP_SNDLOWAT -#define TCP_SNDLOWAT TCP_SND_BUF/2 -#endif - -/* Support loop interface (127.0.0.1) */ -#ifndef LWIP_HAVE_LOOPIF -#define LWIP_HAVE_LOOPIF 0 -#endif - -#ifndef LWIP_EVENT_API -#define LWIP_EVENT_API 0 -#define LWIP_CALLBACK_API 1 -#else -#define LWIP_EVENT_API 1 -#define LWIP_CALLBACK_API 0 -#endif - -#ifndef LWIP_COMPAT_SOCKETS -#define LWIP_COMPAT_SOCKETS 1 -#endif - - -#ifndef TCPIP_THREAD_PRIO -#define TCPIP_THREAD_PRIO 1 -#endif - -#ifndef SLIPIF_THREAD_PRIO -#define SLIPIF_THREAD_PRIO 1 -#endif - -#ifndef PPP_THREAD_PRIO -#define PPP_THREAD_PRIO 1 -#endif - -#ifndef DEFAULT_THREAD_PRIO -#define DEFAULT_THREAD_PRIO 1 -#endif - - -/* ---------- Socket Options ---------- */ -/* Enable SO_REUSEADDR and SO_REUSEPORT options */ -#ifdef SO_REUSE -/* I removed the lot since this was an ugly hack. It broke the raw-API. - It also came with many ugly goto's, Christiaan Simons. */ -#error "SO_REUSE currently unavailable, this was a hack" -#endif - - -/* ---------- Statistics options ---------- */ -#ifndef LWIP_STATS -#define LWIP_STATS 1 -#endif - -#if LWIP_STATS - -#ifndef LWIP_STATS_DISPLAY -#define LWIP_STATS_DISPLAY 0 -#endif - -#ifndef LINK_STATS -#define LINK_STATS 1 -#endif - -#ifndef IP_STATS -#define IP_STATS 1 -#endif - -#ifndef IPFRAG_STATS -#define IPFRAG_STATS 1 -#endif - -#ifndef ICMP_STATS -#define ICMP_STATS 1 -#endif - -#ifndef UDP_STATS -#define UDP_STATS 1 -#endif - -#ifndef TCP_STATS -#define TCP_STATS 1 -#endif - -#ifndef MEM_STATS -#define MEM_STATS 1 -#endif - -#ifndef MEMP_STATS -#define MEMP_STATS 1 -#endif - -#ifndef PBUF_STATS -#define PBUF_STATS 1 -#endif - -#ifndef SYS_STATS -#define SYS_STATS 1 -#endif - -#ifndef RAW_STATS -#define RAW_STATS 0 -#endif - -#else - -#define LINK_STATS 0 -#define IP_STATS 0 -#define IPFRAG_STATS 0 -#define ICMP_STATS 0 -#define UDP_STATS 0 -#define TCP_STATS 0 -#define MEM_STATS 0 -#define MEMP_STATS 0 -#define PBUF_STATS 0 -#define SYS_STATS 0 -#define RAW_STATS 0 -#define LWIP_STATS_DISPLAY 0 - -#endif /* LWIP_STATS */ - -/* ---------- PPP options ---------- */ - -#ifndef PPP_SUPPORT -#define PPP_SUPPORT 0 /* Set for PPP */ -#endif - -#if PPP_SUPPORT - -#define NUM_PPP 1 /* Max PPP sessions. */ - - - -#ifndef PAP_SUPPORT -#define PAP_SUPPORT 0 /* Set for PAP. */ -#endif - -#ifndef CHAP_SUPPORT -#define CHAP_SUPPORT 0 /* Set for CHAP. */ -#endif - -#define MSCHAP_SUPPORT 0 /* Set for MSCHAP (NOT FUNCTIONAL!) */ -#define CBCP_SUPPORT 0 /* Set for CBCP (NOT FUNCTIONAL!) */ -#define CCP_SUPPORT 0 /* Set for CCP (NOT FUNCTIONAL!) */ - -#ifndef VJ_SUPPORT -#define VJ_SUPPORT 0 /* Set for VJ header compression. */ -#endif - -#ifndef MD5_SUPPORT -#define MD5_SUPPORT 0 /* Set for MD5 (see also CHAP) */ -#endif - - -/* - * Timeouts. - */ -#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ -#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ -#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ -#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ - -#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ -#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ - -#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ -#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ - - -/* Interval in seconds between keepalive echo requests, 0 to disable. */ -#if 1 -#define LCP_ECHOINTERVAL 0 -#else -#define LCP_ECHOINTERVAL 10 -#endif - -/* Number of unanswered echo requests before failure. */ -#define LCP_MAXECHOFAILS 3 - -/* Max Xmit idle time (in jiffies) before resend flag char. */ -#define PPP_MAXIDLEFLAG 100 - -/* - * Packet sizes - * - * Note - lcp shouldn't be allowed to negotiate stuff outside these - * limits. See lcp.h in the pppd directory. - * (XXX - these constants should simply be shared by lcp.c instead - * of living in lcp.h) - */ -#define PPP_MTU 1500 /* Default MTU (size of Info field) */ -#if 0 -#define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) -#else -#define PPP_MAXMTU 1500 /* Largest MTU we allow */ -#endif -#define PPP_MINMTU 64 -#define PPP_MRU 1500 /* default MRU = max length of info field */ -#define PPP_MAXMRU 1500 /* Largest MRU we allow */ -#define PPP_DEFMRU 296 /* Try for this */ -#define PPP_MINMRU 128 /* No MRUs below this */ - - -#define MAXNAMELEN 256 /* max length of hostname or name for auth */ -#define MAXSECRETLEN 256 /* max length of password or secret */ - -#endif /* PPP_SUPPORT */ - -/* checksum options - set to zero for hardware checksum support */ - -#ifndef CHECKSUM_GEN_IP -#define CHECKSUM_GEN_IP 1 -#endif - -#ifndef CHECKSUM_GEN_UDP -#define CHECKSUM_GEN_UDP 1 -#endif - -#ifndef CHECKSUM_GEN_TCP -#define CHECKSUM_GEN_TCP 1 -#endif - -#ifndef CHECKSUM_CHECK_IP -#define CHECKSUM_CHECK_IP 1 -#endif - -#ifndef CHECKSUM_CHECK_UDP -#define CHECKSUM_CHECK_UDP 1 -#endif - -#ifndef CHECKSUM_CHECK_TCP -#define CHECKSUM_CHECK_TCP 1 -#endif - -/* Debugging options all default to off */ - -#ifndef DBG_TYPES_ON -#define DBG_TYPES_ON 0 -#endif - -#ifndef ETHARP_DEBUG -#define ETHARP_DEBUG DBG_OFF -#endif - -#ifndef NETIF_DEBUG -#define NETIF_DEBUG DBG_OFF -#endif - -#ifndef PBUF_DEBUG -#define PBUF_DEBUG DBG_OFF -#endif - -#ifndef API_LIB_DEBUG -#define API_LIB_DEBUG DBG_OFF -#endif - -#ifndef API_MSG_DEBUG -#define API_MSG_DEBUG DBG_OFF -#endif - -#ifndef SOCKETS_DEBUG -#define SOCKETS_DEBUG DBG_OFF -#endif - -#ifndef ICMP_DEBUG -#define ICMP_DEBUG DBG_OFF -#endif - -#ifndef INET_DEBUG -#define INET_DEBUG DBG_OFF -#endif - -#ifndef IP_DEBUG -#define IP_DEBUG DBG_OFF -#endif - -#ifndef IP_REASS_DEBUG -#define IP_REASS_DEBUG DBG_OFF -#endif - -#ifndef RAW_DEBUG -#define RAW_DEBUG DBG_OFF -#endif - -#ifndef MEM_DEBUG -#define MEM_DEBUG DBG_OFF -#endif - -#ifndef MEMP_DEBUG -#define MEMP_DEBUG DBG_OFF -#endif - -#ifndef SYS_DEBUG -#define SYS_DEBUG DBG_OFF -#endif - -#ifndef TCP_DEBUG -#define TCP_DEBUG DBG_OFF -#endif - -#ifndef TCP_INPUT_DEBUG -#define TCP_INPUT_DEBUG DBG_OFF -#endif - -#ifndef TCP_FR_DEBUG -#define TCP_FR_DEBUG DBG_OFF -#endif - -#ifndef TCP_RTO_DEBUG -#define TCP_RTO_DEBUG DBG_OFF -#endif - -#ifndef TCP_REXMIT_DEBUG -#define TCP_REXMIT_DEBUG DBG_OFF -#endif - -#ifndef TCP_CWND_DEBUG -#define TCP_CWND_DEBUG DBG_OFF -#endif - -#ifndef TCP_WND_DEBUG -#define TCP_WND_DEBUG DBG_OFF -#endif - -#ifndef TCP_OUTPUT_DEBUG -#define TCP_OUTPUT_DEBUG DBG_OFF -#endif - -#ifndef TCP_RST_DEBUG -#define TCP_RST_DEBUG DBG_OFF -#endif - -#ifndef TCP_QLEN_DEBUG -#define TCP_QLEN_DEBUG DBG_OFF -#endif - -#ifndef UDP_DEBUG -#define UDP_DEBUG DBG_OFF -#endif - -#ifndef TCPIP_DEBUG -#define TCPIP_DEBUG DBG_OFF -#endif - -#ifndef PPP_DEBUG -#define PPP_DEBUG DBG_OFF -#endif - -#ifndef SLIP_DEBUG -#define SLIP_DEBUG DBG_OFF -#endif - -#ifndef DHCP_DEBUG -#define DHCP_DEBUG DBG_OFF -#endif - - -#ifndef DBG_MIN_LEVEL -#define DBG_MIN_LEVEL DBG_LEVEL_OFF -#endif - -#endif /* __LWIP_OPT_H__ */ - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/pbuf.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/pbuf.h deleted file mode 100644 index 546aa3035..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/pbuf.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef __LWIP_PBUF_H__ -#define __LWIP_PBUF_H__ - -#include "arch/cc.h" - - -#define PBUF_TRANSPORT_HLEN 20 -#define PBUF_IP_HLEN 20 - -typedef enum { - PBUF_TRANSPORT, - PBUF_IP, - PBUF_LINK, - PBUF_RAW -} pbuf_layer; - -typedef enum { - PBUF_RAM, - PBUF_ROM, - PBUF_REF, - PBUF_POOL -} pbuf_flag; - -/* Definitions for the pbuf flag field. These are NOT the flags that - * are passed to pbuf_alloc(). */ -#define PBUF_FLAG_RAM 0x00U /* Flags that pbuf data is stored in RAM */ -#define PBUF_FLAG_ROM 0x01U /* Flags that pbuf data is stored in ROM */ -#define PBUF_FLAG_POOL 0x02U /* Flags that the pbuf comes from the pbuf pool */ -#define PBUF_FLAG_REF 0x04U /* Flags thet the pbuf payload refers to RAM */ - -/** indicates this packet was broadcast on the link */ -#define PBUF_FLAG_LINK_BROADCAST 0x80U - -struct pbuf { - /** next pbuf in singly linked pbuf chain */ - struct pbuf *next; - - /** pointer to the actual data in the buffer */ - void *payload; - - /** - * total length of this buffer and all next buffers in chain - * belonging to the same packet. - * - * For non-queue packet chains this is the invariant: - * p->tot_len == p->len + (p->next? p->next->tot_len: 0) - */ - u16_t tot_len; - - /** length of this buffer */ - u16_t len; - - /** flags telling the type of pbuf, see PBUF_FLAG_ */ - u16_t flags; - - /** - * the reference count always equals the number of pointers - * that refer to this pbuf. This can be pointers from an application, - * the stack itself, or pbuf->next pointers from a chain. - */ - u16_t ref; - -}; - -void pbuf_init(void); - -struct pbuf *pbuf_alloc(pbuf_layer l, u16_t size, pbuf_flag flag); -void pbuf_realloc(struct pbuf *p, u16_t size); -u8_t pbuf_header(struct pbuf *p, s16_t header_size); -void pbuf_ref(struct pbuf *p); -void pbuf_ref_chain(struct pbuf *p); -u8_t pbuf_free(struct pbuf *p); -u8_t pbuf_clen(struct pbuf *p); -void pbuf_cat(struct pbuf *h, struct pbuf *t); -void pbuf_chain(struct pbuf *h, struct pbuf *t); -struct pbuf *pbuf_take(struct pbuf *f); -struct pbuf *pbuf_dechain(struct pbuf *p); -void pbuf_queue(struct pbuf *p, struct pbuf *n); -struct pbuf * pbuf_dequeue(struct pbuf *p); - -#endif /* __LWIP_PBUF_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/raw.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/raw.h deleted file mode 100644 index 6f7a98717..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/raw.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_RAW_H__ -#define __LWIP_RAW_H__ - -#include "lwip/arch.h" - -#include "lwip/pbuf.h" -#include "lwip/inet.h" -#include "lwip/ip.h" - -struct raw_pcb { -/* Common members of all PCB types */ - IP_PCB; - - struct raw_pcb *next; - - u16_t protocol; - - u8_t (* recv)(void *arg, struct raw_pcb *pcb, struct pbuf *p, - struct ip_addr *addr); - void *recv_arg; -}; - -/* The following functions is the application layer interface to the - RAW code. */ -struct raw_pcb * raw_new (u16_t proto); -void raw_remove (struct raw_pcb *pcb); -err_t raw_bind (struct raw_pcb *pcb, struct ip_addr *ipaddr); -err_t raw_connect (struct raw_pcb *pcb, struct ip_addr *ipaddr); - -void raw_recv (struct raw_pcb *pcb, - u8_t (* recv)(void *arg, struct raw_pcb *pcb, - struct pbuf *p, - struct ip_addr *addr), - void *recv_arg); -err_t raw_sendto (struct raw_pcb *pcb, struct pbuf *p, struct ip_addr *ipaddr); -err_t raw_send (struct raw_pcb *pcb, struct pbuf *p); - -/* The following functions are the lower layer interface to RAW. */ -u8_t raw_input (struct pbuf *p, struct netif *inp); -void raw_init (void); - - -#endif /* __LWIP_RAW_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/sio.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/sio.h deleted file mode 100644 index e357b1053..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/sio.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - */ - -/* - * This is the interface to the platform specific serial IO module - * It needs to be implemented by those platforms which need SLIP or PPP - */ -#ifndef __SIO_H -#define __SIO_H - -#include "arch/cc.h" - -#ifndef __sio_fd_t_defined -typedef void * sio_fd_t; -#endif - -#ifndef sio_open -sio_fd_t sio_open(u8_t); -#endif - -#ifndef sio_send -void sio_send(u8_t, sio_fd_t); -#endif - -#ifndef sio_recv -u8_t sio_recv(sio_fd_t); -#endif - -#ifndef sio_read -u32_t sio_read(sio_fd_t, u8_t *, u32_t); -#endif - -#ifndef sio_write -u32_t sio_write(sio_fd_t, u8_t *, u32_t); -#endif - -#ifndef sio_read_abort -void sio_read_abort(sio_fd_t); -#endif - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/snmp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/snmp.h deleted file mode 100644 index 7d160aaa4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/snmp.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2001, 2002 Leon Woestenberg - * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Leon Woestenberg - * - */ -#ifndef __LWIP_SNMP_H__ -#define __LWIP_SNMP_H__ - -#include "lwip/opt.h" - -/* SNMP support available? */ -#if defined(LWIP_SNMP) && (LWIP_SNMP > 0) - -/* network interface */ -void snmp_add_ifinoctets(unsigned long value); -void snmp_inc_ifinucastpkts(void); -void snmp_inc_ifinnucastpkts(void); -void snmp_inc_ifindiscards(void); -void snmp_add_ifoutoctets(unsigned long value); -void snmp_inc_ifoutucastpkts(void); -void snmp_inc_ifoutnucastpkts(void); -void snmp_inc_ifoutdiscards(void); - -/* IP */ -void snmp_inc_ipinreceives(void); -void snmp_inc_ipindelivers(void); -void snmp_inc_ipindiscards(void); -void snmp_inc_ipoutdiscards(void); -void snmp_inc_ipoutrequests(void); -void snmp_inc_ipunknownprotos(void); -void snmp_inc_ipnoroutes(void); -void snmp_inc_ipforwdatagrams(void); - -/* ICMP */ -void snmp_inc_icmpinmsgs(void); -void snmp_inc_icmpinerrors(void); -void snmp_inc_icmpindestunreachs(void); -void snmp_inc_icmpintimeexcds(void); -void snmp_inc_icmpinparmprobs(void); -void snmp_inc_icmpinsrcquenchs(void); -void snmp_inc_icmpinredirects(void); -void snmp_inc_icmpinechos(void); -void snmp_inc_icmpinechoreps(void); -void snmp_inc_icmpintimestamps(void); -void snmp_inc_icmpintimestampreps(void); -void snmp_inc_icmpinaddrmasks(void); -void snmp_inc_icmpinaddrmaskreps(void); -void snmp_inc_icmpoutmsgs(void); -void snmp_inc_icmpouterrors(void); -void snmp_inc_icmpoutdestunreachs(void); -void snmp_inc_icmpouttimeexcds(void); -void snmp_inc_icmpoutparmprobs(void); -void snmp_inc_icmpoutsrcquenchs(void); -void snmp_inc_icmpoutredirects(void); -void snmp_inc_icmpoutechos(void); -void snmp_inc_icmpoutechoreps(void); -void snmp_inc_icmpouttimestamps(void); -void snmp_inc_icmpouttimestampreps(void); -void snmp_inc_icmpoutaddrmasks(void); -void snmp_inc_icmpoutaddrmaskreps(void); - -/* TCP */ -void snmp_inc_tcpactiveopens(void); -void snmp_inc_tcppassiveopens(void); -void snmp_inc_tcpattemptfails(void); -void snmp_inc_tcpestabresets(void); -void snmp_inc_tcpcurrestab(void); -void snmp_inc_tcpinsegs(void); -void snmp_inc_tcpoutsegs(void); -void snmp_inc_tcpretranssegs(void); -void snmp_inc_tcpinerrs(void); -void snmp_inc_tcpoutrsts(void); - -/* UDP */ -void snmp_inc_udpindatagrams(void); -void snmp_inc_udpnoports(void); -void snmp_inc_udpinerrors(void); -void snmp_inc_udpoutdatagrams(void); - -/* LWIP_SNMP support not available */ -/* define everything to be empty */ -#else - -/* network interface */ -#define snmp_add_ifinoctets(value) -#define snmp_inc_ifinucastpkts() -#define snmp_inc_ifinnucastpkts() -#define snmp_inc_ifindiscards() -#define snmp_add_ifoutoctets(value) -#define snmp_inc_ifoutucastpkts() -#define snmp_inc_ifoutnucastpkts() -#define snmp_inc_ifoutdiscards() - -/* IP */ -#define snmp_inc_ipinreceives() -#define snmp_inc_ipindelivers() -#define snmp_inc_ipindiscards() -#define snmp_inc_ipoutdiscards() -#define snmp_inc_ipoutrequests() -#define snmp_inc_ipunknownprotos() -#define snmp_inc_ipnoroutes() -#define snmp_inc_ipforwdatagrams() - -/* ICMP */ -#define snmp_inc_icmpinmsgs() -#define snmp_inc_icmpinerrors() -#define snmp_inc_icmpindestunreachs() -#define snmp_inc_icmpintimeexcds() -#define snmp_inc_icmpinparmprobs() -#define snmp_inc_icmpinsrcquenchs() -#define snmp_inc_icmpinredirects() -#define snmp_inc_icmpinechos() -#define snmp_inc_icmpinechoreps() -#define snmp_inc_icmpintimestamps() -#define snmp_inc_icmpintimestampreps() -#define snmp_inc_icmpinaddrmasks() -#define snmp_inc_icmpinaddrmaskreps() -#define snmp_inc_icmpoutmsgs() -#define snmp_inc_icmpouterrors() -#define snmp_inc_icmpoutdestunreachs() -#define snmp_inc_icmpouttimeexcds() -#define snmp_inc_icmpoutparmprobs() -#define snmp_inc_icmpoutsrcquenchs() -#define snmp_inc_icmpoutredirects() -#define snmp_inc_icmpoutechos() -#define snmp_inc_icmpoutechoreps() -#define snmp_inc_icmpouttimestamps() -#define snmp_inc_icmpouttimestampreps() -#define snmp_inc_icmpoutaddrmasks() -#define snmp_inc_icmpoutaddrmaskreps() -/* TCP */ -#define snmp_inc_tcpactiveopens() -#define snmp_inc_tcppassiveopens() -#define snmp_inc_tcpattemptfails() -#define snmp_inc_tcpestabresets() -#define snmp_inc_tcpcurrestab() -#define snmp_inc_tcpinsegs() -#define snmp_inc_tcpoutsegs() -#define snmp_inc_tcpretranssegs() -#define snmp_inc_tcpinerrs() -#define snmp_inc_tcpoutrsts() - -/* UDP */ -#define snmp_inc_udpindatagrams() -#define snmp_inc_udpnoports() -#define snmp_inc_udpinerrors() -#define snmp_inc_udpoutdatagrams() - -#endif - -#endif /* __LWIP_SNMP_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/sockets.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/sockets.h deleted file mode 100644 index d5f8ccf74..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/sockets.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - - -#ifndef __LWIP_SOCKETS_H__ -#define __LWIP_SOCKETS_H__ -#include "lwip/ip_addr.h" - -struct sockaddr_in { - u8_t sin_len; - u8_t sin_family; - u16_t sin_port; - struct in_addr sin_addr; - char sin_zero[8]; -}; - -struct sockaddr { - u8_t sa_len; - u8_t sa_family; - char sa_data[14]; -}; - -#ifndef socklen_t -# define socklen_t int -#endif - - -#define SOCK_STREAM 1 -#define SOCK_DGRAM 2 -#define SOCK_RAW 3 - -/* - * Option flags per-socket. - */ -#define SO_DEBUG 0x0001 /* turn on debugging info recording */ -#define SO_ACCEPTCONN 0x0002 /* socket has had listen() */ -#define SO_REUSEADDR 0x0004 /* allow local address reuse */ -#define SO_KEEPALIVE 0x0008 /* keep connections alive */ -#define SO_DONTROUTE 0x0010 /* just use interface addresses */ -#define SO_BROADCAST 0x0020 /* permit sending of broadcast msgs */ -#define SO_USELOOPBACK 0x0040 /* bypass hardware when possible */ -#define SO_LINGER 0x0080 /* linger on close if data present */ -#define SO_OOBINLINE 0x0100 /* leave received OOB data in line */ -#define SO_REUSEPORT 0x0200 /* allow local address & port reuse */ - -#define SO_DONTLINGER (int)(~SO_LINGER) - -/* - * Additional options, not kept in so_options. - */ -#define SO_SNDBUF 0x1001 /* send buffer size */ -#define SO_RCVBUF 0x1002 /* receive buffer size */ -#define SO_SNDLOWAT 0x1003 /* send low-water mark */ -#define SO_RCVLOWAT 0x1004 /* receive low-water mark */ -#define SO_SNDTIMEO 0x1005 /* send timeout */ -#define SO_RCVTIMEO 0x1006 /* receive timeout */ -#define SO_ERROR 0x1007 /* get error status and clear */ -#define SO_TYPE 0x1008 /* get socket type */ - - - -/* - * Structure used for manipulating linger option. - */ -struct linger { - int l_onoff; /* option on/off */ - int l_linger; /* linger time */ -}; - -/* - * Level number for (get/set)sockopt() to apply to socket itself. - */ -#define SOL_SOCKET 0xfff /* options for socket level */ - - -#define AF_UNSPEC 0 -#define AF_INET 2 -#define PF_INET AF_INET -#define PF_UNSPEC AF_UNSPEC - -#define IPPROTO_IP 0 -#define IPPROTO_TCP 6 -#define IPPROTO_UDP 17 - -#define INADDR_ANY 0 -#define INADDR_BROADCAST 0xffffffff - -/* Flags we can use with send and recv. */ -#define MSG_DONTWAIT 0x40 /* Nonblocking i/o for this operation only */ - - -/* - * Options for level IPPROTO_IP - */ -#define IP_TOS 1 -#define IP_TTL 2 - - -#define IPTOS_TOS_MASK 0x1E -#define IPTOS_TOS(tos) ((tos) & IPTOS_TOS_MASK) -#define IPTOS_LOWDELAY 0x10 -#define IPTOS_THROUGHPUT 0x08 -#define IPTOS_RELIABILITY 0x04 -#define IPTOS_LOWCOST 0x02 -#define IPTOS_MINCOST IPTOS_LOWCOST - -/* - * Definitions for IP precedence (also in ip_tos) (hopefully unused) - */ -#define IPTOS_PREC_MASK 0xe0 -#define IPTOS_PREC(tos) ((tos) & IPTOS_PREC_MASK) -#define IPTOS_PREC_NETCONTROL 0xe0 -#define IPTOS_PREC_INTERNETCONTROL 0xc0 -#define IPTOS_PREC_CRITIC_ECP 0xa0 -#define IPTOS_PREC_FLASHOVERRIDE 0x80 -#define IPTOS_PREC_FLASH 0x60 -#define IPTOS_PREC_IMMEDIATE 0x40 -#define IPTOS_PREC_PRIORITY 0x20 -#define IPTOS_PREC_ROUTINE 0x00 - - -/* - * Commands for ioctlsocket(), taken from the BSD file fcntl.h. - * - * - * Ioctl's have the command encoded in the lower word, - * and the size of any in or out parameters in the upper - * word. The high 2 bits of the upper word are used - * to encode the in/out status of the parameter; for now - * we restrict parameters to at most 128 bytes. - */ -#if !defined(FIONREAD) || !defined(FIONBIO) -#define IOCPARM_MASK 0x7f /* parameters must be < 128 bytes */ -#define IOC_VOID 0x20000000 /* no parameters */ -#define IOC_OUT 0x40000000 /* copy out parameters */ -#define IOC_IN 0x80000000 /* copy in parameters */ -#define IOC_INOUT (IOC_IN|IOC_OUT) - /* 0x20000000 distinguishes new & - old ioctl's */ -#define _IO(x,y) (IOC_VOID|((x)<<8)|(y)) - -#define _IOR(x,y,t) (IOC_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) - -#define _IOW(x,y,t) (IOC_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) -#endif - -#ifndef FIONREAD -#define FIONREAD _IOR('f', 127, unsigned long) /* get # bytes to read */ -#endif -#ifndef FIONBIO -#define FIONBIO _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */ -#endif - -/* Socket I/O Controls */ -#ifndef SIOCSHIWAT -#define SIOCSHIWAT _IOW('s', 0, unsigned long) /* set high watermark */ -#define SIOCGHIWAT _IOR('s', 1, unsigned long) /* get high watermark */ -#define SIOCSLOWAT _IOW('s', 2, unsigned long) /* set low watermark */ -#define SIOCGLOWAT _IOR('s', 3, unsigned long) /* get low watermark */ -#define SIOCATMARK _IOR('s', 7, unsigned long) /* at oob mark? */ -#endif - -#ifndef O_NONBLOCK -#define O_NONBLOCK 04000U -#endif - -#ifndef FD_SET - #undef FD_SETSIZE - #define FD_SETSIZE 16 - #define FD_SET(n, p) ((p)->fd_bits[(n)/8] |= (1 << ((n) & 7))) - #define FD_CLR(n, p) ((p)->fd_bits[(n)/8] &= ~(1 << ((n) & 7))) - #define FD_ISSET(n,p) ((p)->fd_bits[(n)/8] & (1 << ((n) & 7))) - #define FD_ZERO(p) memset((void*)(p),0,sizeof(*(p))) - - typedef struct fd_set { - unsigned char fd_bits [(FD_SETSIZE+7)/8]; - } fd_set; - -/* - * only define this in sockets.c so it does not interfere - * with other projects namespaces where timeval is present - */ -#ifndef LWIP_TIMEVAL_PRIVATE -#define LWIP_TIMEVAL_PRIVATE 1 -#endif - -#if LWIP_TIMEVAL_PRIVATE - struct timeval { - long tv_sec; /* seconds */ - long tv_usec; /* and microseconds */ - }; -#endif - -#endif - -int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen); -int lwip_bind(int s, struct sockaddr *name, socklen_t namelen); -int lwip_shutdown(int s, int how); -int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen); -int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen); -int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen); -int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen); -int lwip_close(int s); -int lwip_connect(int s, struct sockaddr *name, socklen_t namelen); -int lwip_listen(int s, int backlog); -int lwip_recv(int s, void *mem, int len, unsigned int flags); -int lwip_read(int s, void *mem, int len); -int lwip_recvfrom(int s, void *mem, int len, unsigned int flags, - struct sockaddr *from, socklen_t *fromlen); -int lwip_send(int s, void *dataptr, int size, unsigned int flags); -int lwip_sendto(int s, void *dataptr, int size, unsigned int flags, - struct sockaddr *to, socklen_t tolen); -int lwip_socket(int domain, int type, int protocol); -int lwip_write(int s, void *dataptr, int size); -int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, - struct timeval *timeout); -int lwip_ioctl(int s, long cmd, void *argp); - -#if LWIP_COMPAT_SOCKETS -#define accept(a,b,c) lwip_accept(a,b,c) -#define bind(a,b,c) lwip_bind(a,b,c) -#define shutdown(a,b) lwip_shutdown(a,b) -#define close(s) lwip_close(s) -#define connect(a,b,c) lwip_connect(a,b,c) -#define getsockname(a,b,c) lwip_getsockname(a,b,c) -#define getpeername(a,b,c) lwip_getpeername(a,b,c) -#define setsockopt(a,b,c,d,e) lwip_setsockopt(a,b,c,d,e) -#define getsockopt(a,b,c,d,e) lwip_getsockopt(a,b,c,d,e) -#define listen(a,b) lwip_listen(a,b) -#define recv(a,b,c,d) lwip_recv(a,b,c,d) -#define read(a,b,c) lwip_read(a,b,c) -#define recvfrom(a,b,c,d,e,f) lwip_recvfrom(a,b,c,d,e,f) -#define send(a,b,c,d) lwip_send(a,b,c,d) -#define sendto(a,b,c,d,e,f) lwip_sendto(a,b,c,d,e,f) -#define socket(a,b,c) lwip_socket(a,b,c) -#define write(a,b,c) lwip_write(a,b,c) -#define select(a,b,c,d,e) lwip_select(a,b,c,d,e) -#define ioctlsocket(a,b,c) lwip_ioctl(a,b,c) -#endif /* LWIP_COMPAT_SOCKETS */ - -#endif /* __LWIP_SOCKETS_H__ */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/stats.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/stats.h deleted file mode 100644 index 71acfd068..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/stats.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_STATS_H__ -#define __LWIP_STATS_H__ - -#include "lwip/opt.h" -#include "arch/cc.h" - -#include "lwip/mem.h" -#include "lwip/memp.h" - -#if LWIP_STATS - -struct stats_proto { - u16_t xmit; /* Transmitted packets. */ - u16_t rexmit; /* Retransmitted packets. */ - u16_t recv; /* Received packets. */ - u16_t fw; /* Forwarded packets. */ - u16_t drop; /* Dropped packets. */ - u16_t chkerr; /* Checksum error. */ - u16_t lenerr; /* Invalid length error. */ - u16_t memerr; /* Out of memory error. */ - u16_t rterr; /* Routing error. */ - u16_t proterr; /* Protocol error. */ - u16_t opterr; /* Error in options. */ - u16_t err; /* Misc error. */ - u16_t cachehit; -}; - -struct stats_mem { - mem_size_t avail; - mem_size_t used; - mem_size_t max; - mem_size_t err; -}; - -struct stats_pbuf { - u16_t avail; - u16_t used; - u16_t max; - u16_t err; - - u16_t alloc_locked; - u16_t refresh_locked; -}; - -struct stats_syselem { - u16_t used; - u16_t max; - u16_t err; -}; - -struct stats_sys { - struct stats_syselem sem; - struct stats_syselem mbox; -}; - -struct stats_ { - struct stats_proto link; - struct stats_proto ip_frag; - struct stats_proto ip; - struct stats_proto icmp; - struct stats_proto udp; - struct stats_proto tcp; - struct stats_pbuf pbuf; - struct stats_mem mem; - struct stats_mem memp[MEMP_MAX]; - struct stats_sys sys; -}; - -extern struct stats_ lwip_stats; - - -void stats_init(void); - -#define STATS_INC(x) ++lwip_stats.x -#else -#define stats_init() -#define STATS_INC(x) -#endif /* LWIP_STATS */ - -#if TCP_STATS -#define TCP_STATS_INC(x) STATS_INC(x) -#else -#define TCP_STATS_INC(x) -#endif - -#if UDP_STATS -#define UDP_STATS_INC(x) STATS_INC(x) -#else -#define UDP_STATS_INC(x) -#endif - -#if ICMP_STATS -#define ICMP_STATS_INC(x) STATS_INC(x) -#else -#define ICMP_STATS_INC(x) -#endif - -#if IP_STATS -#define IP_STATS_INC(x) STATS_INC(x) -#else -#define IP_STATS_INC(x) -#endif - -#if IPFRAG_STATS -#define IPFRAG_STATS_INC(x) STATS_INC(x) -#else -#define IPFRAG_STATS_INC(x) -#endif - -#if LINK_STATS -#define LINK_STATS_INC(x) STATS_INC(x) -#else -#define LINK_STATS_INC(x) -#endif - -/* Display of statistics */ -#if LWIP_STATS_DISPLAY -void stats_display(void); -#else -#define stats_display() -#endif - -#endif /* __LWIP_STATS_H__ */ - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/sys.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/sys.h deleted file mode 100644 index 68926e954..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/sys.h +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_SYS_H__ -#define __LWIP_SYS_H__ - -#include "arch/cc.h" - -#include "lwip/opt.h" - - -#if NO_SYS - -/* For a totally minimal and standalone system, we provide null - definitions of the sys_ functions. */ -typedef u8_t sys_sem_t; -typedef u8_t sys_mbox_t; -struct sys_timeout {u8_t dummy;}; - -#define sys_init() -#define sys_timeout(m,h,a) -#define sys_untimeout(m,a) -#define sys_sem_new(c) c -#define sys_sem_signal(s) -#define sys_sem_wait(s) -#define sys_sem_free(s) -#define sys_mbox_new() 0 -#define sys_mbox_fetch(m,d) -#define sys_mbox_post(m,d) -#define sys_mbox_free(m) - -#define sys_thread_new(t,a,p) - -#else /* NO_SYS */ - -#include "arch/sys_arch.h" - -/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */ -#define SYS_ARCH_TIMEOUT 0xffffffff - -typedef void (* sys_timeout_handler)(void *arg); - -struct sys_timeout { - struct sys_timeout *next; - u32_t time; - sys_timeout_handler h; - void *arg; -}; - -struct sys_timeouts { - struct sys_timeout *next; -}; - -/* sys_init() must be called before anthing else. */ -void sys_init(void); - -/* - * sys_timeout(): - * - * Schedule a timeout a specified amount of milliseconds in the - * future. When the timeout occurs, the specified timeout handler will - * be called. The handler will be passed the "arg" argument when - * called. - * - */ -void sys_timeout(u32_t msecs, sys_timeout_handler h, void *arg); -void sys_untimeout(sys_timeout_handler h, void *arg); -struct sys_timeouts *sys_arch_timeouts(void); - -/* Semaphore functions. */ -sys_sem_t sys_sem_new(u8_t count); -void sys_sem_signal(sys_sem_t sem); -u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout); -void sys_sem_free(sys_sem_t sem); -void sys_sem_wait(sys_sem_t sem); -int sys_sem_wait_timeout(sys_sem_t sem, u32_t timeout); - -/* Time functions. */ -#ifndef sys_msleep -void sys_msleep(u32_t ms); /* only has a (close to) 1 jiffy resolution. */ -#endif -#ifndef sys_jiffies -u32_t sys_jiffies(void); /* since power up. */ -#endif - -/* Mailbox functions. */ -sys_mbox_t sys_mbox_new(void); -void sys_mbox_post(sys_mbox_t mbox, void *msg); -u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout); -void sys_mbox_free(sys_mbox_t mbox); -void sys_mbox_fetch(sys_mbox_t mbox, void **msg); - - -/* Thread functions. */ -sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio); - -/* The following functions are used only in Unix code, and - can be omitted when porting the stack. */ -/* Returns the current time in microseconds. */ -unsigned long sys_now(void); - -#endif /* NO_SYS */ - -/* Critical Region Protection */ -/* These functions must be implemented in the sys_arch.c file. - In some implementations they can provide a more light-weight protection - mechanism than using semaphores. Otherwise semaphores can be used for - implementation */ -#ifndef SYS_ARCH_PROTECT -/** SYS_LIGHTWEIGHT_PROT - * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection - * for certain critical regions during buffer allocation, deallocation and memory - * allocation and deallocation. - */ -#if SYS_LIGHTWEIGHT_PROT - -/** SYS_ARCH_DECL_PROTECT - * declare a protection variable. This macro will default to defining a variable of - * type sys_prot_t. If a particular port needs a different implementation, then - * this macro may be defined in sys_arch.h. - */ -#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev -/** SYS_ARCH_PROTECT - * Perform a "fast" protect. This could be implemented by - * disabling interrupts for an embedded system or by using a semaphore or - * mutex. The implementation should allow calling SYS_ARCH_PROTECT when - * already protected. The old protection level is returned in the variable - * "lev". This macro will default to calling the sys_arch_protect() function - * which should be implemented in sys_arch.c. If a particular port needs a - * different implementation, then this macro may be defined in sys_arch.h - */ -#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect() -/** SYS_ARCH_UNPROTECT - * Perform a "fast" set of the protection level to "lev". This could be - * implemented by setting the interrupt level to "lev" within the MACRO or by - * using a semaphore or mutex. This macro will default to calling the - * sys_arch_unprotect() function which should be implemented in - * sys_arch.c. If a particular port needs a different implementation, then - * this macro may be defined in sys_arch.h - */ -#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev) -sys_prot_t sys_arch_protect(void); -void sys_arch_unprotect(sys_prot_t pval); - -#else - -#define SYS_ARCH_DECL_PROTECT(lev) -#define SYS_ARCH_PROTECT(lev) -#define SYS_ARCH_UNPROTECT(lev) - -#endif /* SYS_LIGHTWEIGHT_PROT */ - -#endif /* SYS_ARCH_PROTECT */ - -#endif /* __LWIP_SYS_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/tcp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/tcp.h deleted file mode 100644 index 5f968c684..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/tcp.h +++ /dev/null @@ -1,531 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_TCP_H__ -#define __LWIP_TCP_H__ - -#include "lwip/sys.h" -#include "lwip/mem.h" - -#include "lwip/pbuf.h" -#include "lwip/opt.h" -#include "lwip/ip.h" -#include "lwip/icmp.h" - -#include "lwip/err.h" - -struct tcp_pcb; - -/* Functions for interfacing with TCP: */ - -/* Lower layer interface to TCP: */ -void tcp_init (void); /* Must be called first to - initialize TCP. */ -void tcp_tmr (void); /* Must be called every - TCP_TMR_INTERVAL - ms. (Typically 250 ms). */ -/* Application program's interface: */ -struct tcp_pcb * tcp_new (void); -struct tcp_pcb * tcp_alloc (u8_t prio); - -void tcp_arg (struct tcp_pcb *pcb, void *arg); -void tcp_accept (struct tcp_pcb *pcb, - err_t (* accept)(void *arg, struct tcp_pcb *newpcb, - err_t err)); -void tcp_recv (struct tcp_pcb *pcb, - err_t (* recv)(void *arg, struct tcp_pcb *tpcb, - struct pbuf *p, err_t err)); -void tcp_sent (struct tcp_pcb *pcb, - err_t (* sent)(void *arg, struct tcp_pcb *tpcb, - u16_t len)); -void tcp_poll (struct tcp_pcb *pcb, - err_t (* poll)(void *arg, struct tcp_pcb *tpcb), - u8_t interval); -void tcp_err (struct tcp_pcb *pcb, - void (* err)(void *arg, err_t err)); - -#define tcp_mss(pcb) ((pcb)->mss) -#define tcp_sndbuf(pcb) ((pcb)->snd_buf) - -void tcp_recved (struct tcp_pcb *pcb, u16_t len); -err_t tcp_bind (struct tcp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port); -err_t tcp_connect (struct tcp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port, err_t (* connected)(void *arg, - struct tcp_pcb *tpcb, - err_t err)); -struct tcp_pcb * tcp_listen (struct tcp_pcb *pcb); -void tcp_abort (struct tcp_pcb *pcb); -err_t tcp_close (struct tcp_pcb *pcb); -err_t tcp_write (struct tcp_pcb *pcb, const void *dataptr, u16_t len, - u8_t copy); - -void tcp_setprio (struct tcp_pcb *pcb, u8_t prio); - -#define TCP_PRIO_MIN 1 -#define TCP_PRIO_NORMAL 64 -#define TCP_PRIO_MAX 127 - -/* It is also possible to call these two functions at the right - intervals (instead of calling tcp_tmr()). */ -void tcp_slowtmr (void); -void tcp_fasttmr (void); - - -/* Only used by IP to pass a TCP segment to TCP: */ -void tcp_input (struct pbuf *p, struct netif *inp); -/* Used within the TCP code only: */ -err_t tcp_output (struct tcp_pcb *pcb); -void tcp_rexmit (struct tcp_pcb *pcb); -void tcp_rexmit_rto (struct tcp_pcb *pcb); - - - -#define TCP_SEQ_LT(a,b) ((s32_t)((a)-(b)) < 0) -#define TCP_SEQ_LEQ(a,b) ((s32_t)((a)-(b)) <= 0) -#define TCP_SEQ_GT(a,b) ((s32_t)((a)-(b)) > 0) -#define TCP_SEQ_GEQ(a,b) ((s32_t)((a)-(b)) >= 0) -/* is b<=a<=c? */ -#if 0 /* see bug #10548 */ -#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b)) -#endif -#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c)) -#define TCP_FIN 0x01U -#define TCP_SYN 0x02U -#define TCP_RST 0x04U -#define TCP_PSH 0x08U -#define TCP_ACK 0x10U -#define TCP_URG 0x20U -#define TCP_ECE 0x40U -#define TCP_CWR 0x80U - -#define TCP_FLAGS 0x3fU - -/* Length of the TCP header, excluding options. */ -#define TCP_HLEN 20 - -#ifndef TCP_TMR_INTERVAL -#define TCP_TMR_INTERVAL 250 /* The TCP timer interval in - milliseconds. */ -#endif /* TCP_TMR_INTERVAL */ - -#ifndef TCP_FAST_INTERVAL -#define TCP_FAST_INTERVAL TCP_TMR_INTERVAL /* the fine grained timeout in - milliseconds */ -#endif /* TCP_FAST_INTERVAL */ - -#ifndef TCP_SLOW_INTERVAL -#define TCP_SLOW_INTERVAL (2*TCP_TMR_INTERVAL) /* the coarse grained timeout in - milliseconds */ -#endif /* TCP_SLOW_INTERVAL */ - -#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */ -#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */ - -#define TCP_OOSEQ_TIMEOUT 6 /* x RTO */ - -#define TCP_MSL 60000 /* The maximum segment lifetime in microseconds */ - -/* - * User-settable options (used with setsockopt). - */ -#define TCP_NODELAY 0x01 /* don't delay send to coalesce packets */ -#define TCP_KEEPALIVE 0x02 /* send KEEPALIVE probes when idle for pcb->keepalive miliseconds */ - -/* Keepalive values */ -#define TCP_KEEPDEFAULT 7200000 /* KEEPALIVE timer in miliseconds */ -#define TCP_KEEPINTVL 75000 /* Time between KEEPALIVE probes in miliseconds */ -#define TCP_KEEPCNT 9 /* Counter for KEEPALIVE probes */ -#define TCP_MAXIDLE TCP_KEEPCNT * TCP_KEEPINTVL /* Maximum KEEPALIVE probe time */ - - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct tcp_hdr { - PACK_STRUCT_FIELD(u16_t src); - PACK_STRUCT_FIELD(u16_t dest); - PACK_STRUCT_FIELD(u32_t seqno); - PACK_STRUCT_FIELD(u32_t ackno); - PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags); - PACK_STRUCT_FIELD(u16_t wnd); - PACK_STRUCT_FIELD(u16_t chksum); - PACK_STRUCT_FIELD(u16_t urgp); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#define TCPH_OFFSET(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 8) -#define TCPH_HDRLEN(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) >> 12) -#define TCPH_FLAGS(phdr) (ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS) - -#define TCPH_OFFSET_SET(phdr, offset) (phdr)->_hdrlen_rsvd_flags = htons(((offset) << 8) | TCPH_FLAGS(phdr)) -#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = htons(((len) << 12) | TCPH_FLAGS(phdr)) -#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons((ntohs((phdr)->_hdrlen_rsvd_flags) & ~TCP_FLAGS) | (flags)) -#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (flags)) -#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = htons(ntohs((phdr)->_hdrlen_rsvd_flags) | (TCPH_FLAGS(phdr) & ~(flags)) ) - -#define TCP_TCPLEN(seg) ((seg)->len + ((TCPH_FLAGS((seg)->tcphdr) & TCP_FIN || \ - TCPH_FLAGS((seg)->tcphdr) & TCP_SYN)? 1: 0)) - -enum tcp_state { - CLOSED = 0, - LISTEN = 1, - SYN_SENT = 2, - SYN_RCVD = 3, - ESTABLISHED = 4, - FIN_WAIT_1 = 5, - FIN_WAIT_2 = 6, - CLOSE_WAIT = 7, - CLOSING = 8, - LAST_ACK = 9, - TIME_WAIT = 10 -}; - -/* the TCP protocol control block */ -struct tcp_pcb { -/** common PCB members */ - IP_PCB; -/** protocol specific PCB members */ - struct tcp_pcb *next; /* for the linked list */ - enum tcp_state state; /* TCP state */ - u8_t prio; - void *callback_arg; - - u16_t local_port; - u16_t remote_port; - - u8_t flags; -#define TF_ACK_DELAY (u8_t)0x01U /* Delayed ACK. */ -#define TF_ACK_NOW (u8_t)0x02U /* Immediate ACK. */ -#define TF_INFR (u8_t)0x04U /* In fast recovery. */ -#define TF_RESET (u8_t)0x08U /* Connection was reset. */ -#define TF_CLOSED (u8_t)0x10U /* Connection was sucessfully closed. */ -#define TF_GOT_FIN (u8_t)0x20U /* Connection was closed by the remote end. */ -#define TF_NODELAY (u8_t)0x40U /* Disable Nagle algorithm */ - - /* receiver variables */ - u32_t rcv_nxt; /* next seqno expected */ - u16_t rcv_wnd; /* receiver window */ - - /* Timers */ - u32_t tmr; - u8_t polltmr, pollinterval; - - /* Retransmission timer. */ - u16_t rtime; - - u16_t mss; /* maximum segment size */ - - /* RTT (round trip time) estimation variables */ - u32_t rttest; /* RTT estimate in 500ms ticks */ - u32_t rtseq; /* sequence number being timed */ - s16_t sa, sv; /* @todo document this */ - - u16_t rto; /* retransmission time-out */ - u8_t nrtx; /* number of retransmissions */ - - /* fast retransmit/recovery */ - u32_t lastack; /* Highest acknowledged seqno. */ - u8_t dupacks; - - /* congestion avoidance/control variables */ - u16_t cwnd; - u16_t ssthresh; - - /* sender variables */ - u32_t snd_nxt, /* next seqno to be sent */ - snd_max, /* Highest seqno sent. */ - snd_wnd, /* sender window */ - snd_wl1, snd_wl2, /* Sequence and acknowledgement numbers of last - window update. */ - snd_lbb; /* Sequence number of next byte to be buffered. */ - - u16_t acked; - - u16_t snd_buf; /* Available buffer space for sending (in bytes). */ - u8_t snd_queuelen; /* Available buffer space for sending (in tcp_segs). */ - - - /* These are ordered by sequence number: */ - struct tcp_seg *unsent; /* Unsent (queued) segments. */ - struct tcp_seg *unacked; /* Sent but unacknowledged segments. */ -#if TCP_QUEUE_OOSEQ - struct tcp_seg *ooseq; /* Received out of sequence segments. */ -#endif /* TCP_QUEUE_OOSEQ */ - -#if LWIP_CALLBACK_API - /* Function to be called when more send buffer space is available. */ - err_t (* sent)(void *arg, struct tcp_pcb *pcb, u16_t space); - - /* Function to be called when (in-sequence) data has arrived. */ - err_t (* recv)(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err); - - /* Function to be called when a connection has been set up. */ - err_t (* connected)(void *arg, struct tcp_pcb *pcb, err_t err); - - /* Function to call when a listener has been connected. */ - err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err); - - /* Function which is called periodically. */ - err_t (* poll)(void *arg, struct tcp_pcb *pcb); - - /* Function to be called whenever a fatal error occurs. */ - void (* errf)(void *arg, err_t err); -#endif /* LWIP_CALLBACK_API */ - - /* idle time before KEEPALIVE is sent */ - u32_t keepalive; - - /* KEEPALIVE counter */ - u8_t keep_cnt; -}; - -struct tcp_pcb_listen { -/* Common members of all PCB types */ - IP_PCB; - -/* Protocol specific PCB members */ - struct tcp_pcb_listen *next; /* for the linked list */ - - /* Even if state is obviously LISTEN this is here for - * field compatibility with tpc_pcb to which it is cast sometimes - * Until a cleaner solution emerges this is here.FIXME - */ - enum tcp_state state; /* TCP state */ - - u8_t prio; - void *callback_arg; - - u16_t local_port; - -#if LWIP_CALLBACK_API - /* Function to call when a listener has been connected. */ - err_t (* accept)(void *arg, struct tcp_pcb *newpcb, err_t err); -#endif /* LWIP_CALLBACK_API */ -}; - -#if LWIP_EVENT_API - -enum lwip_event { - LWIP_EVENT_ACCEPT, - LWIP_EVENT_SENT, - LWIP_EVENT_RECV, - LWIP_EVENT_CONNECTED, - LWIP_EVENT_POLL, - LWIP_EVENT_ERR -}; - -err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb, - enum lwip_event, - struct pbuf *p, - u16_t size, - err_t err); - -#define TCP_EVENT_ACCEPT(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_ACCEPT, NULL, 0, err) -#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_SENT, NULL, space, ERR_OK) -#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_RECV, (p), 0, (err)) -#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_CONNECTED, NULL, 0, (err)) -#define TCP_EVENT_POLL(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ - LWIP_EVENT_POLL, NULL, 0, ERR_OK) -#define TCP_EVENT_ERR(errf,arg,err) lwip_tcp_event((arg), NULL, \ - LWIP_EVENT_ERR, NULL, 0, (err)) -#else /* LWIP_EVENT_API */ -#define TCP_EVENT_ACCEPT(pcb,err,ret) \ - if((pcb)->accept != NULL) \ - (ret = (pcb)->accept((pcb)->callback_arg,(pcb),(err))) -#define TCP_EVENT_SENT(pcb,space,ret) \ - if((pcb)->sent != NULL) \ - (ret = (pcb)->sent((pcb)->callback_arg,(pcb),(space))) -#define TCP_EVENT_RECV(pcb,p,err,ret) \ - if((pcb)->recv != NULL) \ - { ret = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err)); } else { \ - if (p) pbuf_free(p); } -#define TCP_EVENT_CONNECTED(pcb,err,ret) \ - if((pcb)->connected != NULL) \ - (ret = (pcb)->connected((pcb)->callback_arg,(pcb),(err))) -#define TCP_EVENT_POLL(pcb,ret) \ - if((pcb)->poll != NULL) \ - (ret = (pcb)->poll((pcb)->callback_arg,(pcb))) -#define TCP_EVENT_ERR(errf,arg,err) \ - if((errf) != NULL) \ - (errf)((arg),(err)) -#endif /* LWIP_EVENT_API */ - -/* This structure represents a TCP segment on the unsent and unacked queues */ -struct tcp_seg { - struct tcp_seg *next; /* used when putting segements on a queue */ - struct pbuf *p; /* buffer containing data + TCP header */ - void *dataptr; /* pointer to the TCP data in the pbuf */ - u16_t len; /* the TCP length of this segment */ - struct tcp_hdr *tcphdr; /* the TCP header */ -}; - -/* Internal functions and global variables: */ -struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb); -void tcp_pcb_purge(struct tcp_pcb *pcb); -void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb); - -u8_t tcp_segs_free(struct tcp_seg *seg); -u8_t tcp_seg_free(struct tcp_seg *seg); -struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg); - -#define tcp_ack(pcb) if((pcb)->flags & TF_ACK_DELAY) { \ - (pcb)->flags &= ~TF_ACK_DELAY; \ - (pcb)->flags |= TF_ACK_NOW; \ - tcp_output(pcb); \ - } else { \ - (pcb)->flags |= TF_ACK_DELAY; \ - } - -#define tcp_ack_now(pcb) (pcb)->flags |= TF_ACK_NOW; \ - tcp_output(pcb) - -err_t tcp_send_ctrl(struct tcp_pcb *pcb, u8_t flags); -err_t tcp_enqueue(struct tcp_pcb *pcb, void *dataptr, u16_t len, - u8_t flags, u8_t copy, - u8_t *optdata, u8_t optlen); - -void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg); - -void tcp_rst(u32_t seqno, u32_t ackno, - struct ip_addr *local_ip, struct ip_addr *remote_ip, - u16_t local_port, u16_t remote_port); - -u32_t tcp_next_iss(void); - -void tcp_keepalive(struct tcp_pcb *pcb); - -extern struct tcp_pcb *tcp_input_pcb; -extern u32_t tcp_ticks; - -#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG -void tcp_debug_print(struct tcp_hdr *tcphdr); -void tcp_debug_print_flags(u8_t flags); -void tcp_debug_print_state(enum tcp_state s); -void tcp_debug_print_pcbs(void); -s16_t tcp_pcbs_sane(void); -#else -# define tcp_debug_print(tcphdr) -# define tcp_debug_print_flags(flags) -# define tcp_debug_print_state(s) -# define tcp_debug_print_pcbs() -# define tcp_pcbs_sane() 1 -#endif /* TCP_DEBUG */ - -#if NO_SYS -#define tcp_timer_needed() -#else -void tcp_timer_needed(void); -#endif - -/* The TCP PCB lists. */ -union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */ - struct tcp_pcb_listen *listen_pcbs; - struct tcp_pcb *pcbs; -}; -extern union tcp_listen_pcbs_t tcp_listen_pcbs; -extern struct tcp_pcb *tcp_active_pcbs; /* List of all TCP PCBs that are in a - state in which they accept or send - data. */ -extern struct tcp_pcb *tcp_tw_pcbs; /* List of all TCP PCBs in TIME-WAIT. */ - -extern struct tcp_pcb *tcp_tmp_pcb; /* Only used for temporary storage. */ - -/* Axioms about the above lists: - 1) Every TCP PCB that is not CLOSED is in one of the lists. - 2) A PCB is only in one of the lists. - 3) All PCBs in the tcp_listen_pcbs list is in LISTEN state. - 4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state. -*/ - -/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB - with a PCB list or removes a PCB from a list, respectively. */ -#if 0 -#define TCP_REG(pcbs, npcb) do {\ - LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %d\n", npcb, npcb->local_port)); \ - for(tcp_tmp_pcb = *pcbs; \ - tcp_tmp_pcb != NULL; \ - tcp_tmp_pcb = tcp_tmp_pcb->next) { \ - LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != npcb); \ - } \ - LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", npcb->state != CLOSED); \ - npcb->next = *pcbs; \ - LWIP_ASSERT("TCP_REG: npcb->next != npcb", npcb->next != npcb); \ - *(pcbs) = npcb; \ - LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ - tcp_timer_needed(); \ - } while(0) -#define TCP_RMV(pcbs, npcb) do { \ - LWIP_ASSERT("TCP_RMV: pcbs != NULL", *pcbs != NULL); \ - LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", npcb, *pcbs)); \ - if(*pcbs == npcb) { \ - *pcbs = (*pcbs)->next; \ - } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \ - if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \ - tcp_tmp_pcb->next = npcb->next; \ - break; \ - } \ - } \ - npcb->next = NULL; \ - LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ - LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", npcb, *pcbs)); \ - } while(0) - -#else /* LWIP_DEBUG */ -#define TCP_REG(pcbs, npcb) do { \ - npcb->next = *pcbs; \ - *(pcbs) = npcb; \ - tcp_timer_needed(); \ - } while(0) -#define TCP_RMV(pcbs, npcb) do { \ - if(*(pcbs) == npcb) { \ - (*(pcbs)) = (*pcbs)->next; \ - } else for(tcp_tmp_pcb = *pcbs; tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \ - if(tcp_tmp_pcb->next != NULL && tcp_tmp_pcb->next == npcb) { \ - tcp_tmp_pcb->next = npcb->next; \ - break; \ - } \ - } \ - npcb->next = NULL; \ - } while(0) -#endif /* LWIP_DEBUG */ -#endif /* __LWIP_TCP_H__ */ - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/tcpip.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/tcpip.h deleted file mode 100644 index 316ae4fc5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/tcpip.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_TCPIP_H__ -#define __LWIP_TCPIP_H__ - -#include "lwip/api_msg.h" -#include "lwip/pbuf.h" - -void tcpip_init(void (* tcpip_init_done)(void *), void *arg); -void tcpip_apimsg(struct api_msg *apimsg); -err_t tcpip_input(struct pbuf *p, struct netif *inp); -err_t tcpip_callback(void (*f)(void *ctx), void *ctx); - -void tcpip_tcp_timer_needed(void); - -enum tcpip_msg_type { - TCPIP_MSG_API, - TCPIP_MSG_INPUT, - TCPIP_MSG_CALLBACK -}; - -struct tcpip_msg { - enum tcpip_msg_type type; - sys_sem_t *sem; - union { - struct api_msg *apimsg; - struct { - struct pbuf *p; - struct netif *netif; - } inp; - struct { - void (*f)(void *ctx); - void *ctx; - } cb; - } msg; -}; - - -#endif /* __LWIP_TCPIP_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/udp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/udp.h deleted file mode 100644 index ede04745f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/lwip/udp.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __LWIP_UDP_H__ -#define __LWIP_UDP_H__ - -#include "lwip/arch.h" - -#include "lwip/pbuf.h" -#include "lwip/inet.h" -#include "lwip/ip.h" - -#define UDP_HLEN 8 - -struct udp_hdr { - PACK_STRUCT_FIELD(u16_t src); - PACK_STRUCT_FIELD(u16_t dest); /* src/dest UDP ports */ - PACK_STRUCT_FIELD(u16_t len); - PACK_STRUCT_FIELD(u16_t chksum); -} PACK_STRUCT_STRUCT; - -#define UDP_FLAGS_NOCHKSUM 0x01U -#define UDP_FLAGS_UDPLITE 0x02U -#define UDP_FLAGS_CONNECTED 0x04U - -struct udp_pcb { -/* Common members of all PCB types */ - IP_PCB; - -/* Protocol specific PCB members */ - - struct udp_pcb *next; - - u8_t flags; - u16_t local_port, remote_port; - - u16_t chksum_len; - - void (* recv)(void *arg, struct udp_pcb *pcb, struct pbuf *p, - struct ip_addr *addr, u16_t port); - void *recv_arg; -}; - -/* The following functions is the application layer interface to the - UDP code. */ -struct udp_pcb * udp_new (void); -void udp_remove (struct udp_pcb *pcb); -err_t udp_bind (struct udp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port); -err_t udp_connect (struct udp_pcb *pcb, struct ip_addr *ipaddr, - u16_t port); -void udp_disconnect (struct udp_pcb *pcb); -void udp_recv (struct udp_pcb *pcb, - void (* recv)(void *arg, struct udp_pcb *upcb, - struct pbuf *p, - struct ip_addr *addr, - u16_t port), - void *recv_arg); -err_t udp_sendto (struct udp_pcb *pcb, struct pbuf *p, struct ip_addr *dst_ip, u16_t dst_port); -err_t udp_send (struct udp_pcb *pcb, struct pbuf *p); - -#define udp_flags(pcb) ((pcb)->flags) -#define udp_setflags(pcb, f) ((pcb)->flags = (f)) - -/* The following functions are the lower layer interface to UDP. */ -void udp_input (struct pbuf *p, struct netif *inp); -void udp_init (void); - -#if UDP_DEBUG -void udp_debug_print(struct udp_hdr *udphdr); -#else -#define udp_debug_print(udphdr) -#endif -#endif /* __LWIP_UDP_H__ */ - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/netif/etharp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/netif/etharp.h deleted file mode 100644 index 08437afe5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/netif/etharp.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * Copyright (c) 2003-2004 Leon Woestenberg - * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -#ifndef __NETIF_ETHARP_H__ -#define __NETIF_ETHARP_H__ - -#ifndef ETH_PAD_SIZE -#define ETH_PAD_SIZE 0 -#endif - -#include "lwip/pbuf.h" -#include "lwip/ip_addr.h" -#include "lwip/netif.h" -#include "lwip/ip.h" - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct eth_addr { - PACK_STRUCT_FIELD(u8_t addr[6]); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct eth_hdr { -#if ETH_PAD_SIZE - PACK_STRUCT_FIELD(u8_t padding[ETH_PAD_SIZE]); -#endif - PACK_STRUCT_FIELD(struct eth_addr dest); - PACK_STRUCT_FIELD(struct eth_addr src); - PACK_STRUCT_FIELD(u16_t type); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -/** the ARP message */ -struct etharp_hdr { - PACK_STRUCT_FIELD(struct eth_hdr ethhdr); - PACK_STRUCT_FIELD(u16_t hwtype); - PACK_STRUCT_FIELD(u16_t proto); - PACK_STRUCT_FIELD(u16_t _hwlen_protolen); - PACK_STRUCT_FIELD(u16_t opcode); - PACK_STRUCT_FIELD(struct eth_addr shwaddr); - PACK_STRUCT_FIELD(struct ip_addr2 sipaddr); - PACK_STRUCT_FIELD(struct eth_addr dhwaddr); - PACK_STRUCT_FIELD(struct ip_addr2 dipaddr); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/bpstruct.h" -#endif -PACK_STRUCT_BEGIN -struct ethip_hdr { - PACK_STRUCT_FIELD(struct eth_hdr eth); - PACK_STRUCT_FIELD(struct ip_hdr ip); -} PACK_STRUCT_STRUCT; -PACK_STRUCT_END -#ifdef PACK_STRUCT_USE_INCLUDES -# include "arch/epstruct.h" -#endif - -/** 5 seconds period */ -#define ARP_TMR_INTERVAL 5000 - -#define ETHTYPE_ARP 0x0806 -#define ETHTYPE_IP 0x0800 - -void etharp_init(void); -void etharp_tmr(void); -void etharp_ip_input(struct netif *netif, struct pbuf *p); -void etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, - struct pbuf *p); -err_t etharp_output(struct netif *netif, struct ip_addr *ipaddr, - struct pbuf *q); -err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q); -err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr); - -#endif /* __NETIF_ARP_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/netif/loopif.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/netif/loopif.h deleted file mode 100644 index 97b3c6764..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/netif/loopif.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __NETIF_LOOPIF_H__ -#define __NETIF_LOOPIF_H__ - -#include "lwip/netif.h" - -err_t loopif_init(struct netif *netif); - -#endif /* __NETIF_LOOPIF_H__ */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/netif/slipif.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/netif/slipif.h deleted file mode 100644 index bf70046a9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/include/netif/slipif.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2001, Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#ifndef __NETIF_SLIPIF_H__ -#define __NETIF_SLIPIF_H__ - -#include "lwip/netif.h" - -err_t slipif_init(struct netif * netif); - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/FILES b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/FILES deleted file mode 100644 index 825d40715..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/FILES +++ /dev/null @@ -1,27 +0,0 @@ -This directory contains generic network interface device drivers that -do not contain any hardware or architecture specific code. The files -are: - -etharp.c - Implements the ARP (Address Resolution Protocol) over - Ethernet. The code in this file should be used together with - Ethernet device drivers. Note that this module has been - largely made Ethernet independent so you should be able to - adapt this for other link layers (such as Firewire). - -ethernetif.c - An example of how an Ethernet device driver could look. This - file can be used as a "skeleton" for developing new Ethernet - network device drivers. It uses the etharp.c ARP code. - -loopif.c - An example network interface that shows how a "loopback" - interface would work. This is not really intended for actual - use, but as a very basic example of how initialization and - output functions work. - -slipif.c - A generic implementation of the SLIP (Serial Line IP) - protocol. It requires a sio (serial I/O) module to work. - -ppp/ Point-to-Point Protocol stack diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/etharp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/etharp.c deleted file mode 100644 index 7765046d4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/etharp.c +++ /dev/null @@ -1,831 +0,0 @@ -/** - * @file - * Address Resolution Protocol module for IP over Ethernet - * - * Functionally, ARP is divided into two parts. The first maps an IP address - * to a physical address when sending a packet, and the second part answers - * requests from other machines for our physical address. - * - * This implementation complies with RFC 826 (Ethernet ARP). It supports - * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6 - * if an interface calls etharp_query(our_netif, its_ip_addr, NULL) upon - * address change. - */ - -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * Copyright (c) 2003-2004 Leon Woestenberg - * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - */ - -#include "lwip/opt.h" -#include "lwip/inet.h" -#include "netif/etharp.h" -#include "lwip/ip.h" -#include "lwip/stats.h" - -/* ARP needs to inform DHCP of any ARP replies? */ -#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK) -# include "lwip/dhcp.h" -#endif - -/** the time an ARP entry stays valid after its last update, - * (240 * 5) seconds = 20 minutes. - */ -#define ARP_MAXAGE 240 -/** the time an ARP entry stays pending after first request, - * (2 * 5) seconds = 10 seconds. - * - * @internal Keep this number at least 2, otherwise it might - * run out instantly if the timeout occurs directly after a request. - */ -#define ARP_MAXPENDING 2 - -#define HWTYPE_ETHERNET 1 - -/** ARP message types */ -#define ARP_REQUEST 1 -#define ARP_REPLY 2 - -#define ARPH_HWLEN(hdr) (ntohs((hdr)->_hwlen_protolen) >> 8) -#define ARPH_PROTOLEN(hdr) (ntohs((hdr)->_hwlen_protolen) & 0xff) - -#define ARPH_HWLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons(ARPH_PROTOLEN(hdr) | ((len) << 8)) -#define ARPH_PROTOLEN_SET(hdr, len) (hdr)->_hwlen_protolen = htons((len) | (ARPH_HWLEN(hdr) << 8)) - -enum etharp_state { - ETHARP_STATE_EMPTY, - ETHARP_STATE_PENDING, - ETHARP_STATE_STABLE, - /** @internal transitional state used in etharp_tmr() for convenience*/ - ETHARP_STATE_EXPIRED -}; - -struct etharp_entry { -#if ARP_QUEUEING - /** - * Pointer to queue of pending outgoing packets on this ARP entry. - */ - struct pbuf *p; -#endif - struct ip_addr ipaddr; - struct eth_addr ethaddr; - enum etharp_state state; - u8_t ctime; -}; - -static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}}; -static struct etharp_entry arp_table[ARP_TABLE_SIZE]; - -/** - * Try hard to create a new entry - we want the IP address to appear in - * the cache (even if this means removing an active entry or so). */ -#define ETHARP_TRY_HARD 1 - -static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags); -static err_t update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags); -/** - * Initializes ARP module. - */ -void -etharp_init(void) -{ - u8_t i; - /* clear ARP entries */ - for(i = 0; i < ARP_TABLE_SIZE; ++i) { - arp_table[i].state = ETHARP_STATE_EMPTY; -#if ARP_QUEUEING - arp_table[i].p = NULL; -#endif - arp_table[i].ctime = 0; - } -} - -/** - * Clears expired entries in the ARP table. - * - * This function should be called every ETHARP_TMR_INTERVAL microseconds (5 seconds), - * in order to expire entries in the ARP table. - */ -void -etharp_tmr(void) -{ - u8_t i; - - LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n")); - /* remove expired entries from the ARP table */ - for (i = 0; i < ARP_TABLE_SIZE; ++i) { - arp_table[i].ctime++; - /* stable entry? */ - if ((arp_table[i].state == ETHARP_STATE_STABLE) && - /* entry has become old? */ - (arp_table[i].ctime >= ARP_MAXAGE)) { - LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired stable entry %"U16_F".\n", (u16_t)i)); - arp_table[i].state = ETHARP_STATE_EXPIRED; - /* pending entry? */ - } else if (arp_table[i].state == ETHARP_STATE_PENDING) { - /* entry unresolved/pending for too long? */ - if (arp_table[i].ctime >= ARP_MAXPENDING) { - LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired pending entry %"U16_F".\n", (u16_t)i)); - arp_table[i].state = ETHARP_STATE_EXPIRED; -#if ARP_QUEUEING - } else if (arp_table[i].p != NULL) { - /* resend an ARP query here */ -#endif - } - } - /* clean up entries that have just been expired */ - if (arp_table[i].state == ETHARP_STATE_EXPIRED) { -#if ARP_QUEUEING - /* and empty packet queue */ - if (arp_table[i].p != NULL) { - /* remove all queued packets */ - LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].p))); - pbuf_free(arp_table[i].p); - arp_table[i].p = NULL; - } -#endif - /* recycle entry for re-use */ - arp_table[i].state = ETHARP_STATE_EMPTY; - } - } -} - -/** - * Search the ARP table for a matching or new entry. - * - * If an IP address is given, return a pending or stable ARP entry that matches - * the address. If no match is found, create a new entry with this address set, - * but in state ETHARP_EMPTY. The caller must check and possibly change the - * state of the returned entry. - * - * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY. - * - * In all cases, attempt to create new entries from an empty entry. If no - * empty entries are available and ETHARP_TRY_HARD flag is set, recycle - * old entries. Heuristic choose the least important entry for recycling. - * - * @param ipaddr IP address to find in ARP cache, or to add if not found. - * @param flags - * - ETHARP_TRY_HARD: Try hard to create a entry by allowing recycling of - * active (stable or pending) entries. - * - * @return The ARP entry index that matched or is created, ERR_MEM if no - * entry is found or could be recycled. - */ -static s8_t find_entry(struct ip_addr *ipaddr, u8_t flags) -{ - s8_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE; - s8_t empty = ARP_TABLE_SIZE; - u8_t i = 0, age_pending = 0, age_stable = 0; -#if ARP_QUEUEING - /* oldest entry with packets on queue */ - s8_t old_queue = ARP_TABLE_SIZE; - /* its age */ - u8_t age_queue = 0; -#endif - - /** - * a) do a search through the cache, remember candidates - * b) select candidate entry - * c) create new entry - */ - - /* a) in a single search sweep, do all of this - * 1) remember the first empty entry (if any) - * 2) remember the oldest stable entry (if any) - * 3) remember the oldest pending entry without queued packets (if any) - * 4) remember the oldest pending entry with queued packets (if any) - * 5) search for a matching IP entry, either pending or stable - * until 5 matches, or all entries are searched for. - */ - - for (i = 0; i < ARP_TABLE_SIZE; ++i) { - /* no empty entry found yet and now we do find one? */ - if ((empty == ARP_TABLE_SIZE) && (arp_table[i].state == ETHARP_STATE_EMPTY)) { - LWIP_DEBUGF(ETHARP_DEBUG, ("find_entry: found empty entry %"U16_F"\n", (u16_t)i)); - /* remember first empty entry */ - empty = i; - } - /* pending entry? */ - else if (arp_table[i].state == ETHARP_STATE_PENDING) { - /* if given, does IP address match IP address in ARP entry? */ - if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) { - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching pending entry %"U16_F"\n", (u16_t)i)); - /* found exact IP address match, simply bail out */ - return i; -#if ARP_QUEUEING - /* pending with queued packets? */ - } else if (arp_table[i].p != NULL) { - if (arp_table[i].ctime >= age_queue) { - old_queue = i; - age_queue = arp_table[i].ctime; - } -#endif - /* pending without queued packets? */ - } else { - if (arp_table[i].ctime >= age_pending) { - old_pending = i; - age_pending = arp_table[i].ctime; - } - } - } - /* stable entry? */ - else if (arp_table[i].state == ETHARP_STATE_STABLE) { - /* if given, does IP address match IP address in ARP entry? */ - if (ipaddr && ip_addr_cmp(ipaddr, &arp_table[i].ipaddr)) { - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: found matching stable entry %"U16_F"\n", (u16_t)i)); - /* found exact IP address match, simply bail out */ - return i; - /* remember entry with oldest stable entry in oldest, its age in maxtime */ - } else if (arp_table[i].ctime >= age_stable) { - old_stable = i; - age_stable = arp_table[i].ctime; - } - } - } - /* { we have no match } => try to create a new entry */ - - /* no empty entry found and not allowed to recycle? */ - if ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_TRY_HARD) == 0)) - { - return (s8_t)ERR_MEM; - } - - /* b) choose the least destructive entry to recycle: - * 1) empty entry - * 2) oldest stable entry - * 3) oldest pending entry without queued packets - * 4) oldest pending entry without queued packets - * - * { ETHARP_TRY_HARD is set at this point } - */ - - /* 1) empty entry available? */ - if (empty < ARP_TABLE_SIZE) { - i = empty; - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting empty entry %"U16_F"\n", (u16_t)i)); - } - /* 2) found recyclable stable entry? */ - else if (old_stable < ARP_TABLE_SIZE) { - /* recycle oldest stable*/ - i = old_stable; - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest stable entry %"U16_F"\n", (u16_t)i)); -#if ARP_QUEUEING - /* no queued packets should exist on stable entries */ - LWIP_ASSERT("arp_table[i].p == NULL", arp_table[i].p == NULL); -#endif - /* 3) found recyclable pending entry without queued packets? */ - } else if (old_pending < ARP_TABLE_SIZE) { - /* recycle oldest pending */ - i = old_pending; - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F" (without queue)\n", (u16_t)i)); -#if ARP_QUEUEING - /* 4) found recyclable pending entry with queued packets? */ - } else if (old_queue < ARP_TABLE_SIZE) { - /* recycle oldest pending */ - i = old_queue; - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("find_entry: selecting oldest pending entry %"U16_F", freeing packet queue %p\n", (u16_t)i, (void *)(arp_table[i].p))); - pbuf_free(arp_table[i].p); - arp_table[i].p = NULL; -#endif - /* no empty or recyclable entries found */ - } else { - return (s8_t)ERR_MEM; - } - - /* { empty or recyclable entry found } */ - LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); - - /* recycle entry (no-op for an already empty entry) */ - arp_table[i].state = ETHARP_STATE_EMPTY; - - /* IP address given? */ - if (ipaddr != NULL) { - /* set IP address */ - ip_addr_set(&arp_table[i].ipaddr, ipaddr); - } - arp_table[i].ctime = 0; - return (err_t)i; -} - -/** - * Update (or insert) a IP/MAC address pair in the ARP cache. - * - * If a pending entry is resolved, any queued packets will be sent - * at this point. - * - * @param ipaddr IP address of the inserted ARP entry. - * @param ethaddr Ethernet address of the inserted ARP entry. - * @param flags Defines behaviour: - * - ETHARP_TRY_HARD Allows ARP to insert this as a new item. If not specified, - * only existing ARP entries will be updated. - * - * @return - * - ERR_OK Succesfully updated ARP cache. - * - ERR_MEM If we could not add a new ARP entry when ETHARP_TRY_HARD was set. - * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. - * - * @see pbuf_free() - */ -static err_t -update_arp_entry(struct netif *netif, struct ip_addr *ipaddr, struct eth_addr *ethaddr, u8_t flags) -{ - s8_t i, k; - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 3, ("update_arp_entry()\n")); - LWIP_ASSERT("netif->hwaddr_len != 0", netif->hwaddr_len != 0); - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n", - ip4_addr1(ipaddr), ip4_addr2(ipaddr), ip4_addr3(ipaddr), ip4_addr4(ipaddr), - ethaddr->addr[0], ethaddr->addr[1], ethaddr->addr[2], - ethaddr->addr[3], ethaddr->addr[4], ethaddr->addr[5])); - /* non-unicast address? */ - if (ip_addr_isany(ipaddr) || - ip_addr_isbroadcast(ipaddr, netif) || - ip_addr_ismulticast(ipaddr)) { - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: will not add non-unicast IP address to ARP cache\n")); - return ERR_ARG; - } - /* find or create ARP entry */ - i = find_entry(ipaddr, flags); - /* bail out if no entry could be found */ - if (i < 0) return (err_t)i; - - /* mark it stable */ - arp_table[i].state = ETHARP_STATE_STABLE; - - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: updating stable entry %"S16_F"\n", (s16_t)i)); - /* update address */ - for (k = 0; k < netif->hwaddr_len; ++k) { - arp_table[i].ethaddr.addr[k] = ethaddr->addr[k]; - } - /* reset time stamp */ - arp_table[i].ctime = 0; -/* this is where we will send out queued packets! */ -#if ARP_QUEUEING - while (arp_table[i].p != NULL) { - /* get the first packet on the queue */ - struct pbuf *p = arp_table[i].p; - /* Ethernet header */ - struct eth_hdr *ethhdr = p->payload; - /* remember (and reference) remainder of queue */ - /* note: this will also terminate the p pbuf chain */ - arp_table[i].p = pbuf_dequeue(p); - /* fill-in Ethernet header */ - for (k = 0; k < netif->hwaddr_len; ++k) { - ethhdr->dest.addr[k] = ethaddr->addr[k]; - ethhdr->src.addr[k] = netif->hwaddr[k]; - } - ethhdr->type = htons(ETHTYPE_IP); - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("update_arp_entry: sending queued IP packet %p.\n", (void *)p)); - /* send the queued IP packet */ - netif->linkoutput(netif, p); - /* free the queued IP packet */ - pbuf_free(p); - } -#endif - return ERR_OK; -} - -/** - * Updates the ARP table using the given IP packet. - * - * Uses the incoming IP packet's source address to update the - * ARP cache for the local network. The function does not alter - * or free the packet. This function must be called before the - * packet p is passed to the IP layer. - * - * @param netif The lwIP network interface on which the IP packet pbuf arrived. - * @param pbuf The IP packet that arrived on netif. - * - * @return NULL - * - * @see pbuf_free() - */ -void -etharp_ip_input(struct netif *netif, struct pbuf *p) -{ - struct ethip_hdr *hdr; - LWIP_ASSERT("netif != NULL", netif != NULL); - /* Only insert an entry if the source IP address of the - incoming IP packet comes from a host on the local network. */ - hdr = p->payload; - /* source is not on the local network? */ - if (!ip_addr_netcmp(&(hdr->ip.src), &(netif->ip_addr), &(netif->netmask))) { - /* do nothing */ - return; - } - - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_ip_input: updating ETHARP table.\n")); - /* update ARP table */ - /* @todo We could use ETHARP_TRY_HARD if we think we are going to talk - * back soon (for example, if the destination IP address is ours. */ - update_arp_entry(netif, &(hdr->ip.src), &(hdr->eth.src), 0); -} - - -/** - * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache - * send out queued IP packets. Updates cache with snooped address pairs. - * - * Should be called for incoming ARP packets. The pbuf in the argument - * is freed by this function. - * - * @param netif The lwIP network interface on which the ARP packet pbuf arrived. - * @param pbuf The ARP packet that arrived on netif. Is freed by this function. - * @param ethaddr Ethernet address of netif. - * - * @return NULL - * - * @see pbuf_free() - */ -void -etharp_arp_input(struct netif *netif, struct eth_addr *ethaddr, struct pbuf *p) -{ - struct etharp_hdr *hdr; - /* these are aligned properly, whereas the ARP header fields might not be */ - struct ip_addr sipaddr, dipaddr; - u8_t i; - u8_t for_us; - - LWIP_ASSERT("netif != NULL", netif != NULL); - - /* drop short ARP packets */ - if (p->tot_len < sizeof(struct etharp_hdr)) { - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 1, ("etharp_arp_input: packet dropped, too short (%"S16_F"/%"S16_F")\n", p->tot_len, sizeof(struct etharp_hdr))); - pbuf_free(p); - return; - } - - hdr = p->payload; - - /* get aligned copies of addresses */ - *(struct ip_addr2 *)&sipaddr = hdr->sipaddr; - *(struct ip_addr2 *)&dipaddr = hdr->dipaddr; - - /* this interface is not configured? */ - if (netif->ip_addr.addr == 0) { - for_us = 0; - } else { - /* ARP packet directed to us? */ - for_us = ip_addr_cmp(&dipaddr, &(netif->ip_addr)); - } - - /* ARP message directed to us? */ - if (for_us) { - /* add IP address in ARP cache; assume requester wants to talk to us. - * can result in directly sending the queued packets for this host. */ - update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), ETHARP_TRY_HARD); - /* ARP message not directed to us? */ - } else { - /* update the source IP address in the cache, if present */ - update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), 0); - } - - /* now act on the message itself */ - switch (htons(hdr->opcode)) { - /* ARP request? */ - case ARP_REQUEST: - /* ARP request. If it asked for our address, we send out a - * reply. In any case, we time-stamp any existing ARP entry, - * and possiby send out an IP packet that was queued on it. */ - - LWIP_DEBUGF (ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP request\n")); - /* ARP request for our address? */ - if (for_us) { - - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: replying to ARP request for our IP address\n")); - /* re-use pbuf to send ARP reply */ - hdr->opcode = htons(ARP_REPLY); - - hdr->dipaddr = hdr->sipaddr; - hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr; - - for(i = 0; i < netif->hwaddr_len; ++i) { - hdr->dhwaddr.addr[i] = hdr->shwaddr.addr[i]; - hdr->shwaddr.addr[i] = ethaddr->addr[i]; - hdr->ethhdr.dest.addr[i] = hdr->dhwaddr.addr[i]; - hdr->ethhdr.src.addr[i] = ethaddr->addr[i]; - } - - hdr->hwtype = htons(HWTYPE_ETHERNET); - ARPH_HWLEN_SET(hdr, netif->hwaddr_len); - - hdr->proto = htons(ETHTYPE_IP); - ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr)); - - hdr->ethhdr.type = htons(ETHTYPE_ARP); - /* return ARP reply */ - netif->linkoutput(netif, p); - /* we are not configured? */ - } else if (netif->ip_addr.addr == 0) { - /* { for_us == 0 and netif->ip_addr.addr == 0 } */ - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: we are unconfigured, ARP request ignored.\n")); - /* request was not directed to us */ - } else { - /* { for_us == 0 and netif->ip_addr.addr != 0 } */ - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP request was not for us.\n")); - } - break; - case ARP_REPLY: - /* ARP reply. We already updated the ARP cache earlier. */ - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: incoming ARP reply\n")); -#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK) - /* DHCP wants to know about ARP replies from any host with an - * IP address also offered to us by the DHCP server. We do not - * want to take a duplicate IP address on a single network. - * @todo How should we handle redundant (fail-over) interfaces? - * */ - dhcp_arp_reply(netif, &sipaddr); -#endif - break; - default: - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_arp_input: ARP unknown opcode type %"S16_F"\n", htons(hdr->opcode))); - break; - } - /* free ARP packet */ - pbuf_free(p); -} - -/** - * Resolve and fill-in Ethernet address header for outgoing packet. - * - * For IP multicast and broadcast, corresponding Ethernet addresses - * are selected and the packet is transmitted on the link. - * - * For unicast addresses, the packet is submitted to etharp_query(). In - * case the IP address is outside the local network, the IP address of - * the gateway is used. - * - * @param netif The lwIP network interface which the IP packet will be sent on. - * @param ipaddr The IP address of the packet destination. - * @param pbuf The pbuf(s) containing the IP packet to be sent. - * - * @return - * - ERR_RTE No route to destination (no gateway to external networks), - * or the return type of either etharp_query() or netif->linkoutput(). - */ -err_t -etharp_output(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q) -{ - struct eth_addr *dest, *srcaddr, mcastaddr; - struct eth_hdr *ethhdr; - u8_t i; - - /* make room for Ethernet header - should not fail */ - if (pbuf_header(q, sizeof(struct eth_hdr)) != 0) { - /* bail out */ - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_output: could not allocate room for header.\n")); - LINK_STATS_INC(link.lenerr); - return ERR_BUF; - } - - /* assume unresolved Ethernet address */ - dest = NULL; - /* Determine on destination hardware address. Broadcasts and multicasts - * are special, other IP addresses are looked up in the ARP table. */ - - /* broadcast destination IP address? */ - if (ip_addr_isbroadcast(ipaddr, netif)) { - /* broadcast on Ethernet also */ - dest = (struct eth_addr *)ðbroadcast; - /* multicast destination IP address? */ - } else if (ip_addr_ismulticast(ipaddr)) { - /* Hash IP multicast address to MAC address.*/ - mcastaddr.addr[0] = 0x01; - mcastaddr.addr[1] = 0x00; - mcastaddr.addr[2] = 0x5e; - mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f; - mcastaddr.addr[4] = ip4_addr3(ipaddr); - mcastaddr.addr[5] = ip4_addr4(ipaddr); - /* destination Ethernet address is multicast */ - dest = &mcastaddr; - /* unicast destination IP address? */ - } else { - /* outside local network? */ - if (!ip_addr_netcmp(ipaddr, &(netif->ip_addr), &(netif->netmask))) { - /* interface has default gateway? */ - if (netif->gw.addr != 0) { - /* send to hardware address of default gateway IP address */ - ipaddr = &(netif->gw); - /* no default gateway available */ - } else { - /* no route to destination error (default gateway missing) */ - return ERR_RTE; - } - } - /* queue on destination Ethernet address belonging to ipaddr */ - return etharp_query(netif, ipaddr, q); - } - - /* continuation for multicast/broadcast destinations */ - /* obtain source Ethernet address of the given interface */ - srcaddr = (struct eth_addr *)netif->hwaddr; - ethhdr = q->payload; - for (i = 0; i < netif->hwaddr_len; i++) { - ethhdr->dest.addr[i] = dest->addr[i]; - ethhdr->src.addr[i] = srcaddr->addr[i]; - } - ethhdr->type = htons(ETHTYPE_IP); - /* send packet directly on the link */ - return netif->linkoutput(netif, q); -} - -/** - * Send an ARP request for the given IP address and/or queue a packet. - * - * If the IP address was not yet in the cache, a pending ARP cache entry - * is added and an ARP request is sent for the given address. The packet - * is queued on this entry. - * - * If the IP address was already pending in the cache, a new ARP request - * is sent for the given address. The packet is queued on this entry. - * - * If the IP address was already stable in the cache, and a packet is - * given, it is directly sent and no ARP request is sent out. - * - * If the IP address was already stable in the cache, and no packet is - * given, an ARP request is sent out. - * - * @param netif The lwIP network interface on which ipaddr - * must be queried for. - * @param ipaddr The IP address to be resolved. - * @param q If non-NULL, a pbuf that must be delivered to the IP address. - * q is not freed by this function. - * - * @return - * - ERR_BUF Could not make room for Ethernet header. - * - ERR_MEM Hardware address unknown, and no more ARP entries available - * to query for address or queue the packet. - * - ERR_MEM Could not queue packet due to memory shortage. - * - ERR_RTE No route to destination (no gateway to external networks). - * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. - * - */ -err_t etharp_query(struct netif *netif, struct ip_addr *ipaddr, struct pbuf *q) -{ - struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr; - err_t result = ERR_MEM; - s8_t i; /* ARP entry index */ - u8_t k; /* Ethernet address octet index */ - - /* non-unicast address? */ - if (ip_addr_isbroadcast(ipaddr, netif) || - ip_addr_ismulticast(ipaddr) || - ip_addr_isany(ipaddr)) { - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n")); - return ERR_ARG; - } - - /* find entry in ARP cache, ask to create entry if queueing packet */ - i = find_entry(ipaddr, ETHARP_TRY_HARD); - - /* could not find or create entry? */ - if (i < 0) - { - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not create ARP entry\n")); - if (q) LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: packet dropped\n")); - return (err_t)i; - } - - /* mark a fresh entry as pending (we just sent a request) */ - if (arp_table[i].state == ETHARP_STATE_EMPTY) { - arp_table[i].state = ETHARP_STATE_PENDING; - } - - /* { i is either a STABLE or (new or existing) PENDING entry } */ - LWIP_ASSERT("arp_table[i].state == PENDING or STABLE", - ((arp_table[i].state == ETHARP_STATE_PENDING) || - (arp_table[i].state == ETHARP_STATE_STABLE))); - - /* do we have a pending entry? or an implicit query request? */ - if ((arp_table[i].state == ETHARP_STATE_PENDING) || (q == NULL)) { - /* try to resolve it; send out ARP request */ - result = etharp_request(netif, ipaddr); - } - - /* packet given? */ - if (q != NULL) { - /* stable entry? */ - if (arp_table[i].state == ETHARP_STATE_STABLE) { - /* we have a valid IP->Ethernet address mapping, - * fill in the Ethernet header for the outgoing packet */ - struct eth_hdr *ethhdr = q->payload; - for(k = 0; k < netif->hwaddr_len; k++) { - ethhdr->dest.addr[k] = arp_table[i].ethaddr.addr[k]; - ethhdr->src.addr[k] = srcaddr->addr[k]; - } - ethhdr->type = htons(ETHTYPE_IP); - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: sending packet %p\n", (void *)q)); - /* send the packet */ - result = netif->linkoutput(netif, q); - /* pending entry? (either just created or already pending */ - } else if (arp_table[i].state == ETHARP_STATE_PENDING) { -#if ARP_QUEUEING /* queue the given q packet */ - struct pbuf *p; - /* copy any PBUF_REF referenced payloads into PBUF_RAM */ - /* (the caller of lwIP assumes the referenced payload can be - * freed after it returns from the lwIP call that brought us here) */ - p = pbuf_take(q); - /* packet could be taken over? */ - if (p != NULL) { - /* queue packet ... */ - if (arp_table[i].p == NULL) { - /* ... in the empty queue */ - pbuf_ref(p); - arp_table[i].p = p; -#if 0 /* multi-packet-queueing disabled, see bug #11400 */ - } else { - /* ... at tail of non-empty queue */ - pbuf_queue(arp_table[i].p, p); -#endif - } - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"S16_F"\n", (void *)q, (s16_t)i)); - result = ERR_OK; - } else { - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); - /* { result == ERR_MEM } through initialization */ - } -#else /* ARP_QUEUEING == 0 */ - /* q && state == PENDING && ARP_QUEUEING == 0 => result = ERR_MEM */ - /* { result == ERR_MEM } through initialization */ - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_query: Ethernet destination address unknown, queueing disabled, packet %p dropped\n", (void *)q)); -#endif - } - } - return result; -} - -err_t etharp_request(struct netif *netif, struct ip_addr *ipaddr) -{ - struct pbuf *p; - struct eth_addr * srcaddr = (struct eth_addr *)netif->hwaddr; - err_t result = ERR_OK; - u8_t k; /* ARP entry index */ - - /* allocate a pbuf for the outgoing ARP request packet */ - p = pbuf_alloc(PBUF_LINK, sizeof(struct etharp_hdr), PBUF_RAM); - /* could allocate a pbuf for an ARP request? */ - if (p != NULL) { - struct etharp_hdr *hdr = p->payload; - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE, ("etharp_request: sending ARP request.\n")); - hdr->opcode = htons(ARP_REQUEST); - for (k = 0; k < netif->hwaddr_len; k++) - { - hdr->shwaddr.addr[k] = srcaddr->addr[k]; - /* the hardware address is what we ask for, in - * a request it is a don't-care value, we use zeroes */ - hdr->dhwaddr.addr[k] = 0x00; - } - hdr->dipaddr = *(struct ip_addr2 *)ipaddr; - hdr->sipaddr = *(struct ip_addr2 *)&netif->ip_addr; - - hdr->hwtype = htons(HWTYPE_ETHERNET); - ARPH_HWLEN_SET(hdr, netif->hwaddr_len); - - hdr->proto = htons(ETHTYPE_IP); - ARPH_PROTOLEN_SET(hdr, sizeof(struct ip_addr)); - for (k = 0; k < netif->hwaddr_len; ++k) - { - /* broadcast to all network interfaces on the local network */ - hdr->ethhdr.dest.addr[k] = 0xff; - hdr->ethhdr.src.addr[k] = srcaddr->addr[k]; - } - hdr->ethhdr.type = htons(ETHTYPE_ARP); - /* send ARP query */ - result = netif->linkoutput(netif, p); - /* free ARP query packet */ - pbuf_free(p); - p = NULL; - /* could not allocate pbuf for ARP request */ - } else { - result = ERR_MEM; - LWIP_DEBUGF(ETHARP_DEBUG | DBG_TRACE | 2, ("etharp_request: could not allocate pbuf for ARP request.\n")); - } - return result; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ethernetif.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ethernetif.c deleted file mode 100644 index 0c14e8de5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ethernetif.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* - * This file is a skeleton for developing Ethernet network interface - * drivers for lwIP. Add code to the low_level functions and do a - * search-and-replace for the word "ethernetif" to replace it with - * something that better describes your network interface. - */ - -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include - -#include "netif/etharp.h" - -/* Define those to better describe your network interface. */ -#define IFNAME0 'e' -#define IFNAME1 'n' - -struct ethernetif { - struct eth_addr *ethaddr; - /* Add whatever per-interface state that is needed here. */ -}; - -static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}}; - -/* Forward declarations. */ -static void ethernetif_input(struct netif *netif); -static err_t ethernetif_output(struct netif *netif, struct pbuf *p, - struct ip_addr *ipaddr); - -static void -low_level_init(struct netif *netif) -{ - struct ethernetif *ethernetif = netif->state; - - /* set MAC hardware address length */ - netif->hwaddr_len = 6; - - /* set MAC hardware address */ - netif->hwaddr[0] = ; - ... - netif->hwaddr[5] = ; - - /* maximum transfer unit */ - netif->mtu = 1500; - - /* broadcast capability */ - netif->flags = NETIF_FLAG_BROADCAST; - - /* Do whatever else is needed to initialize interface. */ -} - -/* - * low_level_output(): - * - * Should do the actual transmission of the packet. The packet is - * contained in the pbuf that is passed to the function. This pbuf - * might be chained. - * - */ - -static err_t -low_level_output(struct netif *netif, struct pbuf *p) -{ - struct ethernetif *ethernetif = netif->state; - struct pbuf *q; - - initiate transfer(); - -#if ETH_PAD_SIZE - pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ -#endif - - for(q = p; q != NULL; q = q->next) { - /* Send the data from the pbuf to the interface, one pbuf at a - time. The size of the data in each pbuf is kept in the ->len - variable. */ - send data from(q->payload, q->len); - } - - signal that packet should be sent(); - -#if ETH_PAD_SIZE - pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ -#endif - -#if LINK_STATS - lwip_stats.link.xmit++; -#endif /* LINK_STATS */ - - return ERR_OK; -} - -/* - * low_level_input(): - * - * Should allocate a pbuf and transfer the bytes of the incoming - * packet from the interface into the pbuf. - * - */ - -static struct pbuf * -low_level_input(struct netif *netif) -{ - struct ethernetif *ethernetif = netif->state; - struct pbuf *p, *q; - u16_t len; - - /* Obtain the size of the packet and put it into the "len" - variable. */ - len = ; - -#if ETH_PAD_SIZE - len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ -#endif - - /* We allocate a pbuf chain of pbufs from the pool. */ - p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); - - if (p != NULL) { - -#if ETH_PAD_SIZE - pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ -#endif - - /* We iterate over the pbuf chain until we have read the entire - * packet into the pbuf. */ - for(q = p; q != NULL; q = q->next) { - /* Read enough bytes to fill this pbuf in the chain. The - * available data in the pbuf is given by the q->len - * variable. */ - read data into(q->payload, q->len); - } - acknowledge that packet has been read(); - -#if ETH_PAD_SIZE - pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ -#endif - -#if LINK_STATS - lwip_stats.link.recv++; -#endif /* LINK_STATS */ - } else { - drop packet(); -#if LINK_STATS - lwip_stats.link.memerr++; - lwip_stats.link.drop++; -#endif /* LINK_STATS */ - } - - return p; -} - -/* - * ethernetif_output(): - * - * This function is called by the TCP/IP stack when an IP packet - * should be sent. It calls the function called low_level_output() to - * do the actual transmission of the packet. - * - */ - -static err_t -ethernetif_output(struct netif *netif, struct pbuf *p, - struct ip_addr *ipaddr) -{ - - /* resolve hardware address, then send (or queue) packet */ - return etharp_output(netif, ipaddr, p); - -} - -/* - * ethernetif_input(): - * - * This function should be called when a packet is ready to be read - * from the interface. It uses the function low_level_input() that - * should handle the actual reception of bytes from the network - * interface. - * - */ - -static void -ethernetif_input(struct netif *netif) -{ - struct ethernetif *ethernetif; - struct eth_hdr *ethhdr; - struct pbuf *p; - - ethernetif = netif->state; - - /* move received packet into a new pbuf */ - p = low_level_input(netif); - /* no packet could be read, silently ignore this */ - if (p == NULL) return; - /* points to packet payload, which starts with an Ethernet header */ - ethhdr = p->payload; - -#if LINK_STATS - lwip_stats.link.recv++; -#endif /* LINK_STATS */ - - ethhdr = p->payload; - - switch (htons(ethhdr->type)) { - /* IP packet? */ - case ETHTYPE_IP: - /* update ARP table */ - etharp_ip_input(netif, p); - /* skip Ethernet header */ - pbuf_header(p, -sizeof(struct eth_hdr)); - /* pass to network layer */ - netif->input(p, netif); - break; - - case ETHTYPE_ARP: - /* pass p to ARP module */ - etharp_arp_input(netif, ethernetif->ethaddr, p); - break; - default: - pbuf_free(p); - p = NULL; - break; - } -} - -static void -arp_timer(void *arg) -{ - etharp_tmr(); - sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL); -} - -/* - * ethernetif_init(): - * - * Should be called at the beginning of the program to set up the - * network interface. It calls the function low_level_init() to do the - * actual setup of the hardware. - * - */ - -err_t -ethernetif_init(struct netif *netif) -{ - struct ethernetif *ethernetif; - - ethernetif = mem_malloc(sizeof(struct ethernetif)); - - if (ethernetif == NULL) - { - LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n")); - return ERR_MEM; - } - - netif->state = ethernetif; - netif->name[0] = IFNAME0; - netif->name[1] = IFNAME1; - netif->output = ethernetif_output; - netif->linkoutput = low_level_output; - - ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]); - - low_level_init(netif); - - etharp_init(); - - sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL); - - return ERR_OK; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/loopif.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/loopif.c deleted file mode 100644 index 0464cb8e8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/loopif.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ -#include "lwip/opt.h" - -#if LWIP_HAVE_LOOPIF - -#include "netif/loopif.h" -#include "lwip/mem.h" - -#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP) -#include "netif/tcpdump.h" -#endif /* LWIP_DEBUG && LWIP_TCPDUMP */ - -#include "lwip/tcp.h" -#include "lwip/ip.h" - -static void -loopif_input( void * arg ) -{ - struct netif *netif = (struct netif *)( ((void **)arg)[ 0 ] ); - struct pbuf *r = (struct pbuf *)( ((void **)arg)[ 1 ] ); - - mem_free( arg ); - netif -> input( r, netif ); -} - -static err_t -loopif_output(struct netif *netif, struct pbuf *p, - struct ip_addr *ipaddr) -{ - struct pbuf *q, *r; - u8_t *ptr; - void **arg; - -#if defined(LWIP_DEBUG) && defined(LWIP_TCPDUMP) - tcpdump(p); -#endif /* LWIP_DEBUG && LWIP_TCPDUMP */ - - r = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); - if (r != NULL) { - ptr = r->payload; - - for(q = p; q != NULL; q = q->next) { - memcpy(ptr, q->payload, q->len); - ptr += q->len; - } - - arg = mem_malloc( sizeof( void *[2])); - if( NULL == arg ) { - return ERR_MEM; - } - - arg[0] = netif; - arg[1] = r; - /** - * workaround (patch #1779) to try to prevent bug #2595: - * When connecting to "localhost" with the loopif interface, - * tcp_output doesn't get the opportunity to finnish sending the - * segment before tcp_process gets it, resulting in tcp_process - * referencing pcb->unacked-> which still is NULL. - * - * TODO: Is there still a race condition here? Leon - */ - sys_timeout( 1, loopif_input, arg ); - - return ERR_OK; - } - return ERR_MEM; -} - -err_t -loopif_init(struct netif *netif) -{ - netif->name[0] = 'l'; - netif->name[1] = 'o'; -#if 0 /** TODO: I think this should be enabled, or not? Leon */ - netif->input = loopif_input; -#endif - netif->output = loopif_output; - return ERR_OK; -} - -#endif /* LWIP_HAVE_LOOPIF */ - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/auth.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/auth.c deleted file mode 100644 index 333496402..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/auth.c +++ /dev/null @@ -1,927 +0,0 @@ -/***************************************************************************** -* auth.c - Network Authentication and Phase Control program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* Copyright (c) 1997 by Global Election Systems Inc. All rights reserved. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-08 Guy Lancaster , Global Election Systems Inc. -* Ported from public pppd code. -*****************************************************************************/ -/* - * auth.c - PPP authentication and phase control. - * - * Copyright (c) 1993 The Australian National University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by the Australian National University. The name of the University - * may not be used to endorse or promote products derived from this - * software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include "ppp.h" -#if PPP_SUPPORT > 0 -#include "fsm.h" -#include "lcp.h" -#include "pap.h" -#include "chap.h" -#include "auth.h" -#include "ipcp.h" - -#if CBCP_SUPPORT > 0 -#include "cbcp.h" -#endif - -#include "pppdebug.h" - - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ - -/* Bits in auth_pending[] */ -#define PAP_WITHPEER 1 -#define PAP_PEER 2 -#define CHAP_WITHPEER 4 -#define CHAP_PEER 8 - - - -/************************/ -/*** LOCAL DATA TYPES ***/ -/************************/ -/* Used for storing a sequence of words. Usually malloced. */ -struct wordlist { - struct wordlist *next; - char word[1]; -}; - - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -extern char *crypt (const char *, const char *); - -/* Prototypes for procedures local to this file. */ - -static void network_phase (int); -static void check_idle (void *); -static void connect_time_expired (void *); -#if 0 -static int login (char *, char *, char **, int *); -#endif -static void logout (void); -static int null_login (int); -static int get_pap_passwd (int, char *, char *); -static int have_pap_secret (void); -static int have_chap_secret (char *, char *, u32_t); -static int ip_addr_check (u32_t, struct wordlist *); -#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */ -static void set_allowed_addrs(int unit, struct wordlist *addrs); -static void free_wordlist (struct wordlist *); -#endif -#if CBCP_SUPPORT > 0 -static void callback_phase (int); -#endif - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 -/* The name by which the peer authenticated itself to us. */ -static char peer_authname[MAXNAMELEN]; -#endif - -/* Records which authentication operations haven't completed yet. */ -static int auth_pending[NUM_PPP]; - -/* Set if we have successfully called login() */ -static int logged_in; - -/* Set if we have run the /etc/ppp/auth-up script. */ -static int did_authup; - -/* List of addresses which the peer may use. */ -static struct wordlist *addresses[NUM_PPP]; - -/* Number of network protocols which we have opened. */ -static int num_np_open; - -/* Number of network protocols which have come up. */ -static int num_np_up; - -#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 -/* Set if we got the contents of passwd[] from the pap-secrets file. */ -static int passwd_from_file; -#endif - - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * An Open on LCP has requested a change from Dead to Establish phase. - * Do what's necessary to bring the physical layer up. - */ -void link_required(int unit) -{ - AUTHDEBUG((LOG_INFO, "link_required: %d\n", unit)); -} - -/* - * LCP has terminated the link; go to the Dead phase and take the - * physical layer down. - */ -void link_terminated(int unit) -{ - AUTHDEBUG((LOG_INFO, "link_terminated: %d\n", unit)); - - if (lcp_phase[unit] == PHASE_DEAD) - return; - if (logged_in) - logout(); - lcp_phase[unit] = PHASE_DEAD; - AUTHDEBUG((LOG_NOTICE, "Connection terminated.\n")); - pppMainWakeup(unit); -} - -/* - * LCP has gone down; it will either die or try to re-establish. - */ -void link_down(int unit) -{ - int i; - struct protent *protp; - - AUTHDEBUG((LOG_INFO, "link_down: %d\n", unit)); - if (did_authup) { - /* XXX Do link down processing. */ - did_authup = 0; - } - for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { - if (!protp->enabled_flag) - continue; - if (protp->protocol != PPP_LCP && protp->lowerdown != NULL) - (*protp->lowerdown)(unit); - if (protp->protocol < 0xC000 && protp->close != NULL) - (*protp->close)(unit, "LCP down"); - } - num_np_open = 0; - num_np_up = 0; - if (lcp_phase[unit] != PHASE_DEAD) - lcp_phase[unit] = PHASE_TERMINATE; - pppMainWakeup(unit); -} - -/* - * The link is established. - * Proceed to the Dead, Authenticate or Network phase as appropriate. - */ -void link_established(int unit) -{ - int auth; - int i; - struct protent *protp; - lcp_options *wo = &lcp_wantoptions[unit]; - lcp_options *go = &lcp_gotoptions[unit]; -#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 - lcp_options *ho = &lcp_hisoptions[unit]; -#endif - - AUTHDEBUG((LOG_INFO, "link_established: %d\n", unit)); - /* - * Tell higher-level protocols that LCP is up. - */ - for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) - if (protp->protocol != PPP_LCP && protp->enabled_flag - && protp->lowerup != NULL) - (*protp->lowerup)(unit); - - if (ppp_settings.auth_required && !(go->neg_chap || go->neg_upap)) { - /* - * We wanted the peer to authenticate itself, and it refused: - * treat it as though it authenticated with PAP using a username - * of "" and a password of "". If that's not OK, boot it out. - */ - if (!wo->neg_upap || !null_login(unit)) { - AUTHDEBUG((LOG_WARNING, "peer refused to authenticate\n")); - lcp_close(unit, "peer refused to authenticate"); - return; - } - } - - lcp_phase[unit] = PHASE_AUTHENTICATE; - auth = 0; -#if CHAP_SUPPORT > 0 - if (go->neg_chap) { - ChapAuthPeer(unit, ppp_settings.our_name, go->chap_mdtype); - auth |= CHAP_PEER; - } -#endif -#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0 - else -#endif -#if PAP_SUPPORT > 0 - if (go->neg_upap) { - upap_authpeer(unit); - auth |= PAP_PEER; - } -#endif -#if CHAP_SUPPORT > 0 - if (ho->neg_chap) { - ChapAuthWithPeer(unit, ppp_settings.user, ho->chap_mdtype); - auth |= CHAP_WITHPEER; - } -#endif -#if PAP_SUPPORT > 0 && CHAP_SUPPORT > 0 - else -#endif -#if PAP_SUPPORT > 0 - if (ho->neg_upap) { - if (ppp_settings.passwd[0] == 0) { - passwd_from_file = 1; - if (!get_pap_passwd(unit, ppp_settings.user, ppp_settings.passwd)) - AUTHDEBUG((LOG_ERR, "No secret found for PAP login\n")); - } - upap_authwithpeer(unit, ppp_settings.user, ppp_settings.passwd); - auth |= PAP_WITHPEER; - } -#endif - auth_pending[unit] = auth; - - if (!auth) - network_phase(unit); -} - - -/* - * The peer has failed to authenticate himself using `protocol'. - */ -void auth_peer_fail(int unit, u16_t protocol) -{ - AUTHDEBUG((LOG_INFO, "auth_peer_fail: %d proto=%X\n", unit, protocol)); - /* - * Authentication failure: take the link down - */ - lcp_close(unit, "Authentication failed"); -} - - -#if PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 -/* - * The peer has been successfully authenticated using `protocol'. - */ -void auth_peer_success(int unit, u16_t protocol, char *name, int namelen) -{ - int pbit; - - AUTHDEBUG((LOG_INFO, "auth_peer_success: %d proto=%X\n", unit, protocol)); - switch (protocol) { - case PPP_CHAP: - pbit = CHAP_PEER; - break; - case PPP_PAP: - pbit = PAP_PEER; - break; - default: - AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n", - protocol)); - return; - } - - /* - * Save the authenticated name of the peer for later. - */ - if (namelen > sizeof(peer_authname) - 1) - namelen = sizeof(peer_authname) - 1; - BCOPY(name, peer_authname, namelen); - peer_authname[namelen] = 0; - - /* - * If there is no more authentication still to be done, - * proceed to the network (or callback) phase. - */ - if ((auth_pending[unit] &= ~pbit) == 0) - network_phase(unit); -} - -/* - * We have failed to authenticate ourselves to the peer using `protocol'. - */ -void auth_withpeer_fail(int unit, u16_t protocol) -{ - int errCode = PPPERR_AUTHFAIL; - - AUTHDEBUG((LOG_INFO, "auth_withpeer_fail: %d proto=%X\n", unit, protocol)); - if (passwd_from_file) - BZERO(ppp_settings.passwd, MAXSECRETLEN); - /* - * XXX Warning: the unit number indicates the interface which is - * not necessarily the PPP connection. It works here as long - * as we are only supporting PPP interfaces. - */ - pppIOCtl(unit, PPPCTLS_ERRCODE, &errCode); - - /* - * We've failed to authenticate ourselves to our peer. - * He'll probably take the link down, and there's not much - * we can do except wait for that. - */ -} - -/* - * We have successfully authenticated ourselves with the peer using `protocol'. - */ -void auth_withpeer_success(int unit, u16_t protocol) -{ - int pbit; - - AUTHDEBUG((LOG_INFO, "auth_withpeer_success: %d proto=%X\n", unit, protocol)); - switch (protocol) { - case PPP_CHAP: - pbit = CHAP_WITHPEER; - break; - case PPP_PAP: - if (passwd_from_file) - BZERO(ppp_settings.passwd, MAXSECRETLEN); - pbit = PAP_WITHPEER; - break; - default: - AUTHDEBUG((LOG_WARNING, "auth_peer_success: unknown protocol %x\n", - protocol)); - pbit = 0; - } - - /* - * If there is no more authentication still being done, - * proceed to the network (or callback) phase. - */ - if ((auth_pending[unit] &= ~pbit) == 0) - network_phase(unit); -} -#endif - - -/* - * np_up - a network protocol has come up. - */ -void np_up(int unit, u16_t proto) -{ - AUTHDEBUG((LOG_INFO, "np_up: %d proto=%X\n", unit, proto)); - if (num_np_up == 0) { - AUTHDEBUG((LOG_INFO, "np_up: maxconnect=%d idle_time_limit=%d\n",ppp_settings.maxconnect,ppp_settings.idle_time_limit)); - /* - * At this point we consider that the link has come up successfully. - */ - if (ppp_settings.idle_time_limit > 0) - TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit); - - /* - * Set a timeout to close the connection once the maximum - * connect time has expired. - */ - if (ppp_settings.maxconnect > 0) - TIMEOUT(connect_time_expired, 0, ppp_settings.maxconnect); - } - ++num_np_up; -} - -/* - * np_down - a network protocol has gone down. - */ -void np_down(int unit, u16_t proto) -{ - AUTHDEBUG((LOG_INFO, "np_down: %d proto=%X\n", unit, proto)); - if (--num_np_up == 0 && ppp_settings.idle_time_limit > 0) { - UNTIMEOUT(check_idle, NULL); - } -} - -/* - * np_finished - a network protocol has finished using the link. - */ -void np_finished(int unit, u16_t proto) -{ - AUTHDEBUG((LOG_INFO, "np_finished: %d proto=%X\n", unit, proto)); - if (--num_np_open <= 0) { - /* no further use for the link: shut up shop. */ - lcp_close(0, "No network protocols running"); - } -} - -/* - * auth_reset - called when LCP is starting negotiations to recheck - * authentication options, i.e. whether we have appropriate secrets - * to use for authenticating ourselves and/or the peer. - */ -void auth_reset(int unit) -{ - lcp_options *go = &lcp_gotoptions[unit]; - lcp_options *ao = &lcp_allowoptions[0]; - ipcp_options *ipwo = &ipcp_wantoptions[0]; - u32_t remote; - - AUTHDEBUG((LOG_INFO, "auth_reset: %d\n", unit)); - ao->neg_upap = !ppp_settings.refuse_pap && (ppp_settings.passwd[0] != 0 || get_pap_passwd(unit, NULL, NULL)); - ao->neg_chap = !ppp_settings.refuse_chap && ppp_settings.passwd[0] != 0 /*have_chap_secret(ppp_settings.user, ppp_settings.remote_name, (u32_t)0)*/; - - if (go->neg_upap && !have_pap_secret()) - go->neg_upap = 0; - if (go->neg_chap) { - remote = ipwo->accept_remote? 0: ipwo->hisaddr; - if (!have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote)) - go->neg_chap = 0; - } -} - - -#if PAP_SUPPORT > 0 -/* - * check_passwd - Check the user name and passwd against the PAP secrets - * file. If requested, also check against the system password database, - * and login the user if OK. - * - * returns: - * UPAP_AUTHNAK: Authentication failed. - * UPAP_AUTHACK: Authentication succeeded. - * In either case, msg points to an appropriate message. - */ -int check_passwd( - int unit, - char *auser, - int userlen, - char *apasswd, - int passwdlen, - char **msg, - int *msglen -) -{ -#if 1 - *msg = (char *) 0; - return UPAP_AUTHACK; /* XXX Assume all entries OK. */ -#else - int ret = 0; - struct wordlist *addrs = NULL; - char passwd[256], user[256]; - char secret[MAXWORDLEN]; - static u_short attempts = 0; - - /* - * Make copies of apasswd and auser, then null-terminate them. - */ - BCOPY(apasswd, passwd, passwdlen); - passwd[passwdlen] = '\0'; - BCOPY(auser, user, userlen); - user[userlen] = '\0'; - *msg = (char *) 0; - - /* XXX Validate user name and password. */ - ret = UPAP_AUTHACK; /* XXX Assume all entries OK. */ - - if (ret == UPAP_AUTHNAK) { - if (*msg == (char *) 0) - *msg = "Login incorrect"; - *msglen = strlen(*msg); - /* - * Frustrate passwd stealer programs. - * Allow 10 tries, but start backing off after 3 (stolen from login). - * On 10'th, drop the connection. - */ - if (attempts++ >= 10) { - AUTHDEBUG((LOG_WARNING, "%d LOGIN FAILURES BY %s\n", attempts, user)); - /*ppp_panic("Excess Bad Logins");*/ - } - if (attempts > 3) { - sys_msleep((attempts - 3) * 5); - } - if (addrs != NULL) { - free_wordlist(addrs); - } - } else { - attempts = 0; /* Reset count */ - if (*msg == (char *) 0) - *msg = "Login ok"; - *msglen = strlen(*msg); - set_allowed_addrs(unit, addrs); - } - - BZERO(passwd, sizeof(passwd)); - BZERO(secret, sizeof(secret)); - - return ret; -#endif -} -#endif - - -/* - * auth_ip_addr - check whether the peer is authorized to use - * a given IP address. Returns 1 if authorized, 0 otherwise. - */ -int auth_ip_addr(int unit, u32_t addr) -{ - return ip_addr_check(addr, addresses[unit]); -} - -/* - * bad_ip_adrs - return 1 if the IP address is one we don't want - * to use, such as an address in the loopback net or a multicast address. - * addr is in network byte order. - */ -int bad_ip_adrs(u32_t addr) -{ - addr = ntohl(addr); - return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET - || IN_MULTICAST(addr) || IN_BADCLASS(addr); -} - - -#if CHAP_SUPPORT > 0 -/* - * get_secret - open the CHAP secret file and return the secret - * for authenticating the given client on the given server. - * (We could be either client or server). - */ -int get_secret( - int unit, - char *client, - char *server, - char *secret, - int *secret_len, - int save_addrs -) -{ -#if 1 - int len; - struct wordlist *addrs; - - addrs = NULL; - - if(!client || !client[0] || strcmp(client, ppp_settings.user)) { - return 0; - } - - len = strlen(ppp_settings.passwd); - if (len > MAXSECRETLEN) { - AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server)); - len = MAXSECRETLEN; - } - BCOPY(ppp_settings.passwd, secret, len); - *secret_len = len; - - return 1; -#else - int ret = 0, len; - struct wordlist *addrs; - char secbuf[MAXWORDLEN]; - - addrs = NULL; - secbuf[0] = 0; - - /* XXX Find secret. */ - if (ret < 0) - return 0; - - if (save_addrs) - set_allowed_addrs(unit, addrs); - - len = strlen(secbuf); - if (len > MAXSECRETLEN) { - AUTHDEBUG((LOG_ERR, "Secret for %s on %s is too long\n", client, server)); - len = MAXSECRETLEN; - } - BCOPY(secbuf, secret, len); - BZERO(secbuf, sizeof(secbuf)); - *secret_len = len; - - return 1; -#endif -} -#endif - - -#if 0 /* UNUSED */ -/* - * auth_check_options - called to check authentication options. - */ -void auth_check_options(void) -{ - lcp_options *wo = &lcp_wantoptions[0]; - int can_auth; - ipcp_options *ipwo = &ipcp_wantoptions[0]; - u32_t remote; - - /* Default our_name to hostname, and user to our_name */ - if (ppp_settings.our_name[0] == 0 || ppp_settings.usehostname) - strcpy(ppp_settings.our_name, ppp_settings.hostname); - if (ppp_settings.user[0] == 0) - strcpy(ppp_settings.user, ppp_settings.our_name); - - /* If authentication is required, ask peer for CHAP or PAP. */ - if (ppp_settings.auth_required && !wo->neg_chap && !wo->neg_upap) { - wo->neg_chap = 1; - wo->neg_upap = 1; - } - - /* - * Check whether we have appropriate secrets to use - * to authenticate the peer. - */ - can_auth = wo->neg_upap && have_pap_secret(); - if (!can_auth && wo->neg_chap) { - remote = ipwo->accept_remote? 0: ipwo->hisaddr; - can_auth = have_chap_secret(ppp_settings.remote_name, ppp_settings.our_name, remote); - } - - if (ppp_settings.auth_required && !can_auth) { - ppp_panic("No auth secret"); - } -} -#endif - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ -/* - * Proceed to the network phase. - */ -static void network_phase(int unit) -{ - int i; - struct protent *protp; - lcp_options *go = &lcp_gotoptions[unit]; - - /* - * If the peer had to authenticate, run the auth-up script now. - */ - if ((go->neg_chap || go->neg_upap) && !did_authup) { - /* XXX Do setup for peer authentication. */ - did_authup = 1; - } - -#if CBCP_SUPPORT > 0 - /* - * If we negotiated callback, do it now. - */ - if (go->neg_cbcp) { - lcp_phase[unit] = PHASE_CALLBACK; - (*cbcp_protent.open)(unit); - return; - } -#endif - - lcp_phase[unit] = PHASE_NETWORK; - for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) - if (protp->protocol < 0xC000 && protp->enabled_flag - && protp->open != NULL) { - (*protp->open)(unit); - if (protp->protocol != PPP_CCP) - ++num_np_open; - } - - if (num_np_open == 0) - /* nothing to do */ - lcp_close(0, "No network protocols running"); -} - -/* - * check_idle - check whether the link has been idle for long - * enough that we can shut it down. - */ -static void check_idle(void *arg) -{ - struct ppp_idle idle; - u_short itime; - - (void)arg; - if (!get_idle_time(0, &idle)) - return; - itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle); - if (itime >= ppp_settings.idle_time_limit) { - /* link is idle: shut it down. */ - AUTHDEBUG((LOG_INFO, "Terminating connection due to lack of activity.\n")); - lcp_close(0, "Link inactive"); - } else { - TIMEOUT(check_idle, NULL, ppp_settings.idle_time_limit - itime); - } -} - -/* - * connect_time_expired - log a message and close the connection. - */ -static void connect_time_expired(void *arg) -{ - (void)arg; - - AUTHDEBUG((LOG_INFO, "Connect time expired\n")); - lcp_close(0, "Connect time expired"); /* Close connection */ -} - -#if 0 -/* - * login - Check the user name and password against the system - * password database, and login the user if OK. - * - * returns: - * UPAP_AUTHNAK: Login failed. - * UPAP_AUTHACK: Login succeeded. - * In either case, msg points to an appropriate message. - */ -static int login(char *user, char *passwd, char **msg, int *msglen) -{ - /* XXX Fail until we decide that we want to support logins. */ - return (UPAP_AUTHNAK); -} -#endif - -/* - * logout - Logout the user. - */ -static void logout(void) -{ - logged_in = 0; -} - - -/* - * null_login - Check if a username of "" and a password of "" are - * acceptable, and iff so, set the list of acceptable IP addresses - * and return 1. - */ -static int null_login(int unit) -{ - (void)unit; - /* XXX Fail until we decide that we want to support logins. */ - return 0; -} - - -/* - * get_pap_passwd - get a password for authenticating ourselves with - * our peer using PAP. Returns 1 on success, 0 if no suitable password - * could be found. - */ -static int get_pap_passwd(int unit, char *user, char *passwd) -{ -/* normally we would reject PAP if no password is provided, - but this causes problems with some providers (like CHT in Taiwan) - who incorrectly request PAP and expect a bogus/empty password, so - always provide a default user/passwd of "none"/"none" -*/ - if(user) - strcpy(user, "none"); - if(passwd) - strcpy(passwd, "none"); - - return 1; -} - - -/* - * have_pap_secret - check whether we have a PAP file with any - * secrets that we could possibly use for authenticating the peer. - */ -static int have_pap_secret(void) -{ - /* XXX Fail until we set up our passwords. */ - return 0; -} - - -/* - * have_chap_secret - check whether we have a CHAP file with a - * secret that we could possibly use for authenticating `client' - * on `server'. Either can be the null string, meaning we don't - * know the identity yet. - */ -static int have_chap_secret(char *client, char *server, u32_t remote) -{ - (void)client; - (void)server; - (void)remote; - /* XXX Fail until we set up our passwords. */ - return 0; -} - - -#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT > 0 */ -/* - * set_allowed_addrs() - set the list of allowed addresses. - */ -static void set_allowed_addrs(int unit, struct wordlist *addrs) -{ - if (addresses[unit] != NULL) - free_wordlist(addresses[unit]); - addresses[unit] = addrs; - -#if 0 - /* - * If there's only one authorized address we might as well - * ask our peer for that one right away - */ - if (addrs != NULL && addrs->next == NULL) { - char *p = addrs->word; - struct ipcp_options *wo = &ipcp_wantoptions[unit]; - u32_t a; - struct hostent *hp; - - if (wo->hisaddr == 0 && *p != '!' && *p != '-' - && strchr(p, '/') == NULL) { - hp = gethostbyname(p); - if (hp != NULL && hp->h_addrtype == AF_INET) - a = *(u32_t *)hp->h_addr; - else - a = inet_addr(p); - if (a != (u32_t) -1) - wo->hisaddr = a; - } - } -#endif -} -#endif - -static int ip_addr_check(u32_t addr, struct wordlist *addrs) -{ - - /* don't allow loopback or multicast address */ - if (bad_ip_adrs(addr)) - return 0; - - if (addrs == NULL) - return !ppp_settings.auth_required; /* no addresses authorized */ - - /* XXX All other addresses allowed. */ - return 1; -} - -#if 0 /* PAP_SUPPORT > 0 || CHAP_SUPPORT */ -/* - * free_wordlist - release memory allocated for a wordlist. - */ -static void free_wordlist(struct wordlist *wp) -{ - struct wordlist *next; - - while (wp != NULL) { - next = wp->next; - free(wp); - wp = next; - } -} -#endif - -#endif /* PPP_SUPPORT */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/auth.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/auth.h deleted file mode 100644 index d6a5de5b7..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/auth.h +++ /dev/null @@ -1,94 +0,0 @@ -/***************************************************************************** -* auth.h - PPP Authentication and phase control header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1998 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD pppd.h. -*****************************************************************************/ -/* - * pppd.h - PPP daemon global declarations. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - */ - -#ifndef AUTH_H -#define AUTH_H - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ -void link_required (int); /* we are starting to use the link */ -void link_terminated (int); /* we are finished with the link */ -void link_down (int); /* the LCP layer has left the Opened state */ -void link_established (int); /* the link is up; authenticate now */ -void np_up (int, u16_t); /* a network protocol has come up */ -void np_down (int, u16_t); /* a network protocol has gone down */ -void np_finished (int, u16_t); /* a network protocol no longer needs link */ -void auth_peer_fail (int, u16_t);/* peer failed to authenticate itself */ - -/* peer successfully authenticated itself */ -void auth_peer_success (int, u16_t, char *, int); - -/* we failed to authenticate ourselves */ -void auth_withpeer_fail (int, u16_t); - -/* we successfully authenticated ourselves */ -void auth_withpeer_success (int, u16_t); - -/* check authentication options supplied */ -void auth_check_options (void); -void auth_reset (int); /* check what secrets we have */ - -/* Check peer-supplied username/password */ -int check_passwd (int, char *, int, char *, int, char **, int *); - -/* get "secret" for chap */ -int get_secret (int, char *, char *, char *, int *, int); - -/* check if IP address is authorized */ -int auth_ip_addr (int, u32_t); - -/* check if IP address is unreasonable */ -int bad_ip_adrs (u32_t); - - -#endif /* AUTH_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/chap.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/chap.c deleted file mode 100644 index 4d1dc0d24..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/chap.c +++ /dev/null @@ -1,872 +0,0 @@ -/*** WARNING - THIS HAS NEVER BEEN FINISHED ***/ -/***************************************************************************** -* chap.c - Network Challenge Handshake Authentication Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original based on BSD chap.c. -*****************************************************************************/ -/* - * chap.c - Challenge Handshake Authentication Protocol. - * - * Copyright (c) 1993 The Australian National University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by the Australian National University. The name of the University - * may not be used to endorse or promote products derived from this - * software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * Copyright (c) 1991 Gregory M. Christy. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Gregory M. Christy. The name of the author may not be used to - * endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include "ppp.h" -#if PPP_SUPPORT > 0 -#include "magic.h" - -#if CHAP_SUPPORT > 0 - -#include "randm.h" -#include "auth.h" -#include "md5.h" -#include "chap.h" -#include "chpms.h" -#include "pppdebug.h" - - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ - - -/************************/ -/*** LOCAL DATA TYPES ***/ -/************************/ - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -/* - * Protocol entry points. - */ -static void ChapInit (int); -static void ChapLowerUp (int); -static void ChapLowerDown (int); -static void ChapInput (int, u_char *, int); -static void ChapProtocolReject (int); -static int ChapPrintPkt (u_char *, int, - void (*) (void *, char *, ...), void *); - -static void ChapChallengeTimeout (void *); -static void ChapResponseTimeout (void *); -static void ChapReceiveChallenge (chap_state *, u_char *, int, int); -static void ChapRechallenge (void *); -static void ChapReceiveResponse (chap_state *, u_char *, int, int); -static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len); -static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len); -static void ChapSendStatus (chap_state *, int); -static void ChapSendChallenge (chap_state *); -static void ChapSendResponse (chap_state *); -static void ChapGenChallenge (chap_state *); - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ -chap_state chap[NUM_PPP]; /* CHAP state; one for each unit */ - -struct protent chap_protent = { - PPP_CHAP, - ChapInit, - ChapInput, - ChapProtocolReject, - ChapLowerUp, - ChapLowerDown, - NULL, - NULL, -#if 0 - ChapPrintPkt, - NULL, -#endif - 1, - "CHAP", -#if 0 - NULL, - NULL, - NULL -#endif -}; - - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -static char *ChapCodenames[] = { - "Challenge", "Response", "Success", "Failure" -}; - - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * ChapAuthWithPeer - Authenticate us with our peer (start client). - * - */ -void ChapAuthWithPeer(int unit, char *our_name, int digest) -{ - chap_state *cstate = &chap[unit]; - - cstate->resp_name = our_name; - cstate->resp_type = digest; - - if (cstate->clientstate == CHAPCS_INITIAL || - cstate->clientstate == CHAPCS_PENDING) { - /* lower layer isn't up - wait until later */ - cstate->clientstate = CHAPCS_PENDING; - return; - } - - /* - * We get here as a result of LCP coming up. - * So even if CHAP was open before, we will - * have to re-authenticate ourselves. - */ - cstate->clientstate = CHAPCS_LISTEN; -} - - -/* - * ChapAuthPeer - Authenticate our peer (start server). - */ -void ChapAuthPeer(int unit, char *our_name, int digest) -{ - chap_state *cstate = &chap[unit]; - - cstate->chal_name = our_name; - cstate->chal_type = digest; - - if (cstate->serverstate == CHAPSS_INITIAL || - cstate->serverstate == CHAPSS_PENDING) { - /* lower layer isn't up - wait until later */ - cstate->serverstate = CHAPSS_PENDING; - return; - } - - ChapGenChallenge(cstate); - ChapSendChallenge(cstate); /* crank it up dude! */ - cstate->serverstate = CHAPSS_INITIAL_CHAL; -} - - - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ -/* - * ChapInit - Initialize a CHAP unit. - */ -static void ChapInit(int unit) -{ - chap_state *cstate = &chap[unit]; - - BZERO(cstate, sizeof(*cstate)); - cstate->unit = unit; - cstate->clientstate = CHAPCS_INITIAL; - cstate->serverstate = CHAPSS_INITIAL; - cstate->timeouttime = CHAP_DEFTIMEOUT; - cstate->max_transmits = CHAP_DEFTRANSMITS; - /* random number generator is initialized in magic_init */ -} - - -/* - * ChapChallengeTimeout - Timeout expired on sending challenge. - */ -static void ChapChallengeTimeout(void *arg) -{ - chap_state *cstate = (chap_state *) arg; - - /* if we aren't sending challenges, don't worry. then again we */ - /* probably shouldn't be here either */ - if (cstate->serverstate != CHAPSS_INITIAL_CHAL && - cstate->serverstate != CHAPSS_RECHALLENGE) - return; - - if (cstate->chal_transmits >= cstate->max_transmits) { - /* give up on peer */ - CHAPDEBUG((LOG_ERR, "Peer failed to respond to CHAP challenge\n")); - cstate->serverstate = CHAPSS_BADAUTH; - auth_peer_fail(cstate->unit, PPP_CHAP); - return; - } - - ChapSendChallenge(cstate); /* Re-send challenge */ -} - - -/* - * ChapResponseTimeout - Timeout expired on sending response. - */ -static void ChapResponseTimeout(void *arg) -{ - chap_state *cstate = (chap_state *) arg; - - /* if we aren't sending a response, don't worry. */ - if (cstate->clientstate != CHAPCS_RESPONSE) - return; - - ChapSendResponse(cstate); /* re-send response */ -} - - -/* - * ChapRechallenge - Time to challenge the peer again. - */ -static void ChapRechallenge(void *arg) -{ - chap_state *cstate = (chap_state *) arg; - - /* if we aren't sending a response, don't worry. */ - if (cstate->serverstate != CHAPSS_OPEN) - return; - - ChapGenChallenge(cstate); - ChapSendChallenge(cstate); - cstate->serverstate = CHAPSS_RECHALLENGE; -} - - -/* - * ChapLowerUp - The lower layer is up. - * - * Start up if we have pending requests. - */ -static void ChapLowerUp(int unit) -{ - chap_state *cstate = &chap[unit]; - - if (cstate->clientstate == CHAPCS_INITIAL) - cstate->clientstate = CHAPCS_CLOSED; - else if (cstate->clientstate == CHAPCS_PENDING) - cstate->clientstate = CHAPCS_LISTEN; - - if (cstate->serverstate == CHAPSS_INITIAL) - cstate->serverstate = CHAPSS_CLOSED; - else if (cstate->serverstate == CHAPSS_PENDING) { - ChapGenChallenge(cstate); - ChapSendChallenge(cstate); - cstate->serverstate = CHAPSS_INITIAL_CHAL; - } -} - - -/* - * ChapLowerDown - The lower layer is down. - * - * Cancel all timeouts. - */ -static void ChapLowerDown(int unit) -{ - chap_state *cstate = &chap[unit]; - - /* Timeout(s) pending? Cancel if so. */ - if (cstate->serverstate == CHAPSS_INITIAL_CHAL || - cstate->serverstate == CHAPSS_RECHALLENGE) - UNTIMEOUT(ChapChallengeTimeout, cstate); - else if (cstate->serverstate == CHAPSS_OPEN - && cstate->chal_interval != 0) - UNTIMEOUT(ChapRechallenge, cstate); - if (cstate->clientstate == CHAPCS_RESPONSE) - UNTIMEOUT(ChapResponseTimeout, cstate); - - cstate->clientstate = CHAPCS_INITIAL; - cstate->serverstate = CHAPSS_INITIAL; -} - - -/* - * ChapProtocolReject - Peer doesn't grok CHAP. - */ -static void ChapProtocolReject(int unit) -{ - chap_state *cstate = &chap[unit]; - - if (cstate->serverstate != CHAPSS_INITIAL && - cstate->serverstate != CHAPSS_CLOSED) - auth_peer_fail(unit, PPP_CHAP); - if (cstate->clientstate != CHAPCS_INITIAL && - cstate->clientstate != CHAPCS_CLOSED) - auth_withpeer_fail(unit, PPP_CHAP); - ChapLowerDown(unit); /* shutdown chap */ -} - - -/* - * ChapInput - Input CHAP packet. - */ -static void ChapInput(int unit, u_char *inpacket, int packet_len) -{ - chap_state *cstate = &chap[unit]; - u_char *inp; - u_char code, id; - int len; - - /* - * Parse header (code, id and length). - * If packet too short, drop it. - */ - inp = inpacket; - if (packet_len < CHAP_HEADERLEN) { - CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short header.\n")); - return; - } - GETCHAR(code, inp); - GETCHAR(id, inp); - GETSHORT(len, inp); - if (len < CHAP_HEADERLEN) { - CHAPDEBUG((LOG_INFO, "ChapInput: rcvd illegal length.\n")); - return; - } - if (len > packet_len) { - CHAPDEBUG((LOG_INFO, "ChapInput: rcvd short packet.\n")); - return; - } - len -= CHAP_HEADERLEN; - - /* - * Action depends on code (as in fact it usually does :-). - */ - switch (code) { - case CHAP_CHALLENGE: - ChapReceiveChallenge(cstate, inp, id, len); - break; - - case CHAP_RESPONSE: - ChapReceiveResponse(cstate, inp, id, len); - break; - - case CHAP_FAILURE: - ChapReceiveFailure(cstate, inp, id, len); - break; - - case CHAP_SUCCESS: - ChapReceiveSuccess(cstate, inp, id, len); - break; - - default: /* Need code reject? */ - CHAPDEBUG((LOG_WARNING, "Unknown CHAP code (%d) received.\n", code)); - break; - } -} - - -/* - * ChapReceiveChallenge - Receive Challenge and send Response. - */ -static void ChapReceiveChallenge(chap_state *cstate, u_char *inp, int id, int len) -{ - int rchallenge_len; - u_char *rchallenge; - int secret_len; - char secret[MAXSECRETLEN]; - char rhostname[256]; - MD5_CTX mdContext; - u_char hash[MD5_SIGNATURE_SIZE]; - - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: Rcvd id %d.\n", id)); - if (cstate->clientstate == CHAPCS_CLOSED || - cstate->clientstate == CHAPCS_PENDING) { - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: in state %d\n", - cstate->clientstate)); - return; - } - - if (len < 2) { - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n")); - return; - } - - GETCHAR(rchallenge_len, inp); - len -= sizeof (u_char) + rchallenge_len; /* now name field length */ - if (len < 0) { - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: rcvd short packet.\n")); - return; - } - rchallenge = inp; - INCPTR(rchallenge_len, inp); - - if (len >= sizeof(rhostname)) - len = sizeof(rhostname) - 1; - BCOPY(inp, rhostname, len); - rhostname[len] = '\000'; - - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: received name field '%s'\n", - rhostname)); - - /* Microsoft doesn't send their name back in the PPP packet */ - if (ppp_settings.remote_name[0] != 0 && (ppp_settings.explicit_remote || rhostname[0] == 0)) { - strncpy(rhostname, ppp_settings.remote_name, sizeof(rhostname)); - rhostname[sizeof(rhostname) - 1] = 0; - CHAPDEBUG((LOG_INFO, "ChapReceiveChallenge: using '%s' as remote name\n", - rhostname)); - } - - /* get secret for authenticating ourselves with the specified host */ - if (!get_secret(cstate->unit, cstate->resp_name, rhostname, - secret, &secret_len, 0)) { - secret_len = 0; /* assume null secret if can't find one */ - CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating us to %s\n", rhostname)); - } - - /* cancel response send timeout if necessary */ - if (cstate->clientstate == CHAPCS_RESPONSE) - UNTIMEOUT(ChapResponseTimeout, cstate); - - cstate->resp_id = id; - cstate->resp_transmits = 0; - - /* generate MD based on negotiated type */ - switch (cstate->resp_type) { - - case CHAP_DIGEST_MD5: - MD5Init(&mdContext); - MD5Update(&mdContext, &cstate->resp_id, 1); - MD5Update(&mdContext, (u_char*)secret, secret_len); - MD5Update(&mdContext, rchallenge, rchallenge_len); - MD5Final(hash, &mdContext); - BCOPY(hash, cstate->response, MD5_SIGNATURE_SIZE); - cstate->resp_length = MD5_SIGNATURE_SIZE; - break; - -#ifdef CHAPMS - case CHAP_MICROSOFT: - ChapMS(cstate, rchallenge, rchallenge_len, secret, secret_len); - break; -#endif - - default: - CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->resp_type)); - return; - } - - BZERO(secret, sizeof(secret)); - ChapSendResponse(cstate); -} - - -/* - * ChapReceiveResponse - Receive and process response. - */ -static void ChapReceiveResponse(chap_state *cstate, u_char *inp, int id, int len) -{ - u_char *remmd, remmd_len; - int secret_len, old_state; - int code; - char rhostname[256]; - MD5_CTX mdContext; - char secret[MAXSECRETLEN]; - u_char hash[MD5_SIGNATURE_SIZE]; - - CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: Rcvd id %d.\n", id)); - - if (cstate->serverstate == CHAPSS_CLOSED || - cstate->serverstate == CHAPSS_PENDING) { - CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: in state %d\n", - cstate->serverstate)); - return; - } - - if (id != cstate->chal_id) - return; /* doesn't match ID of last challenge */ - - /* - * If we have received a duplicate or bogus Response, - * we have to send the same answer (Success/Failure) - * as we did for the first Response we saw. - */ - if (cstate->serverstate == CHAPSS_OPEN) { - ChapSendStatus(cstate, CHAP_SUCCESS); - return; - } - if (cstate->serverstate == CHAPSS_BADAUTH) { - ChapSendStatus(cstate, CHAP_FAILURE); - return; - } - - if (len < 2) { - CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n")); - return; - } - GETCHAR(remmd_len, inp); /* get length of MD */ - remmd = inp; /* get pointer to MD */ - INCPTR(remmd_len, inp); - - len -= sizeof (u_char) + remmd_len; - if (len < 0) { - CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: rcvd short packet.\n")); - return; - } - - UNTIMEOUT(ChapChallengeTimeout, cstate); - - if (len >= sizeof(rhostname)) - len = sizeof(rhostname) - 1; - BCOPY(inp, rhostname, len); - rhostname[len] = '\000'; - - CHAPDEBUG((LOG_INFO, "ChapReceiveResponse: received name field: %s\n", - rhostname)); - - /* - * Get secret for authenticating them with us, - * do the hash ourselves, and compare the result. - */ - code = CHAP_FAILURE; - if (!get_secret(cstate->unit, rhostname, cstate->chal_name, - secret, &secret_len, 1)) { -/* CHAPDEBUG((LOG_WARNING, TL_CHAP, "No CHAP secret found for authenticating %s\n", rhostname)); */ - CHAPDEBUG((LOG_WARNING, "No CHAP secret found for authenticating %s\n", - rhostname)); - } else { - - /* generate MD based on negotiated type */ - switch (cstate->chal_type) { - - case CHAP_DIGEST_MD5: /* only MD5 is defined for now */ - if (remmd_len != MD5_SIGNATURE_SIZE) - break; /* it's not even the right length */ - MD5Init(&mdContext); - MD5Update(&mdContext, &cstate->chal_id, 1); - MD5Update(&mdContext, (u_char*)secret, secret_len); - MD5Update(&mdContext, cstate->challenge, cstate->chal_len); - MD5Final(hash, &mdContext); - - /* compare local and remote MDs and send the appropriate status */ - if (memcmp (hash, remmd, MD5_SIGNATURE_SIZE) == 0) - code = CHAP_SUCCESS; /* they are the same! */ - break; - - default: - CHAPDEBUG((LOG_INFO, "unknown digest type %d\n", cstate->chal_type)); - } - } - - BZERO(secret, sizeof(secret)); - ChapSendStatus(cstate, code); - - if (code == CHAP_SUCCESS) { - old_state = cstate->serverstate; - cstate->serverstate = CHAPSS_OPEN; - if (old_state == CHAPSS_INITIAL_CHAL) { - auth_peer_success(cstate->unit, PPP_CHAP, rhostname, len); - } - if (cstate->chal_interval != 0) - TIMEOUT(ChapRechallenge, cstate, cstate->chal_interval); - } else { - CHAPDEBUG((LOG_ERR, "CHAP peer authentication failed\n")); - cstate->serverstate = CHAPSS_BADAUTH; - auth_peer_fail(cstate->unit, PPP_CHAP); - } -} - -/* - * ChapReceiveSuccess - Receive Success - */ -static void ChapReceiveSuccess(chap_state *cstate, u_char *inp, u_char id, int len) -{ - - CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: Rcvd id %d.\n", id)); - - if (cstate->clientstate == CHAPCS_OPEN) - /* presumably an answer to a duplicate response */ - return; - - if (cstate->clientstate != CHAPCS_RESPONSE) { - /* don't know what this is */ - CHAPDEBUG((LOG_INFO, "ChapReceiveSuccess: in state %d\n", - cstate->clientstate)); - return; - } - - UNTIMEOUT(ChapResponseTimeout, cstate); - - /* - * Print message. - */ - if (len > 0) - PRINTMSG(inp, len); - - cstate->clientstate = CHAPCS_OPEN; - - auth_withpeer_success(cstate->unit, PPP_CHAP); -} - - -/* - * ChapReceiveFailure - Receive failure. - */ -static void ChapReceiveFailure(chap_state *cstate, u_char *inp, u_char id, int len) -{ - CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: Rcvd id %d.\n", id)); - - if (cstate->clientstate != CHAPCS_RESPONSE) { - /* don't know what this is */ - CHAPDEBUG((LOG_INFO, "ChapReceiveFailure: in state %d\n", - cstate->clientstate)); - return; - } - - UNTIMEOUT(ChapResponseTimeout, cstate); - - /* - * Print message. - */ - if (len > 0) - PRINTMSG(inp, len); - - CHAPDEBUG((LOG_ERR, "CHAP authentication failed\n")); - auth_withpeer_fail(cstate->unit, PPP_CHAP); -} - - -/* - * ChapSendChallenge - Send an Authenticate challenge. - */ -static void ChapSendChallenge(chap_state *cstate) -{ - u_char *outp; - int chal_len, name_len; - int outlen; - - chal_len = cstate->chal_len; - name_len = strlen(cstate->chal_name); - outlen = CHAP_HEADERLEN + sizeof (u_char) + chal_len + name_len; - outp = outpacket_buf[cstate->unit]; - - MAKEHEADER(outp, PPP_CHAP); /* paste in a CHAP header */ - - PUTCHAR(CHAP_CHALLENGE, outp); - PUTCHAR(cstate->chal_id, outp); - PUTSHORT(outlen, outp); - - PUTCHAR(chal_len, outp); /* put length of challenge */ - BCOPY(cstate->challenge, outp, chal_len); - INCPTR(chal_len, outp); - - BCOPY(cstate->chal_name, outp, name_len); /* append hostname */ - - pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); - - CHAPDEBUG((LOG_INFO, "ChapSendChallenge: Sent id %d.\n", cstate->chal_id)); - - TIMEOUT(ChapChallengeTimeout, cstate, cstate->timeouttime); - ++cstate->chal_transmits; -} - - -/* - * ChapSendStatus - Send a status response (ack or nak). - */ -static void ChapSendStatus(chap_state *cstate, int code) -{ - u_char *outp; - int outlen, msglen; - char msg[256]; - - if (code == CHAP_SUCCESS) - strcpy(msg, "Welcome!"); - else - strcpy(msg, "I don't like you. Go 'way."); - msglen = strlen(msg); - - outlen = CHAP_HEADERLEN + msglen; - outp = outpacket_buf[cstate->unit]; - - MAKEHEADER(outp, PPP_CHAP); /* paste in a header */ - - PUTCHAR(code, outp); - PUTCHAR(cstate->chal_id, outp); - PUTSHORT(outlen, outp); - BCOPY(msg, outp, msglen); - pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); - - CHAPDEBUG((LOG_INFO, "ChapSendStatus: Sent code %d, id %d.\n", code, - cstate->chal_id)); -} - -/* - * ChapGenChallenge is used to generate a pseudo-random challenge string of - * a pseudo-random length between min_len and max_len. The challenge - * string and its length are stored in *cstate, and various other fields of - * *cstate are initialized. - */ - -static void ChapGenChallenge(chap_state *cstate) -{ - int chal_len; - u_char *ptr = cstate->challenge; - int i; - - /* pick a random challenge length between MIN_CHALLENGE_LENGTH and - MAX_CHALLENGE_LENGTH */ - chal_len = (unsigned) - ((((magic() >> 16) * - (MAX_CHALLENGE_LENGTH - MIN_CHALLENGE_LENGTH)) >> 16) - + MIN_CHALLENGE_LENGTH); - cstate->chal_len = chal_len; - cstate->chal_id = ++cstate->id; - cstate->chal_transmits = 0; - - /* generate a random string */ - for (i = 0; i < chal_len; i++ ) - *ptr++ = (char) (magic() & 0xff); -} - -/* - * ChapSendResponse - send a response packet with values as specified - * in *cstate. - */ -/* ARGSUSED */ -static void ChapSendResponse(chap_state *cstate) -{ - u_char *outp; - int outlen, md_len, name_len; - - md_len = cstate->resp_length; - name_len = strlen(cstate->resp_name); - outlen = CHAP_HEADERLEN + sizeof (u_char) + md_len + name_len; - outp = outpacket_buf[cstate->unit]; - - MAKEHEADER(outp, PPP_CHAP); - - PUTCHAR(CHAP_RESPONSE, outp); /* we are a response */ - PUTCHAR(cstate->resp_id, outp); /* copy id from challenge packet */ - PUTSHORT(outlen, outp); /* packet length */ - - PUTCHAR(md_len, outp); /* length of MD */ - BCOPY(cstate->response, outp, md_len); /* copy MD to buffer */ - INCPTR(md_len, outp); - - BCOPY(cstate->resp_name, outp, name_len); /* append our name */ - - /* send the packet */ - pppWrite(cstate->unit, outpacket_buf[cstate->unit], outlen + PPP_HDRLEN); - - cstate->clientstate = CHAPCS_RESPONSE; - TIMEOUT(ChapResponseTimeout, cstate, cstate->timeouttime); - ++cstate->resp_transmits; -} - -/* - * ChapPrintPkt - print the contents of a CHAP packet. - */ -static int ChapPrintPkt( - u_char *p, - int plen, - void (*printer) (void *, char *, ...), - void *arg -) -{ - int code, id, len; - int clen, nlen; - u_char x; - - if (plen < CHAP_HEADERLEN) - return 0; - GETCHAR(code, p); - GETCHAR(id, p); - GETSHORT(len, p); - if (len < CHAP_HEADERLEN || len > plen) - return 0; - - if (code >= 1 && code <= sizeof(ChapCodenames) / sizeof(char *)) - printer(arg, " %s", ChapCodenames[code-1]); - else - printer(arg, " code=0x%x", code); - printer(arg, " id=0x%x", id); - len -= CHAP_HEADERLEN; - switch (code) { - case CHAP_CHALLENGE: - case CHAP_RESPONSE: - if (len < 1) - break; - clen = p[0]; - if (len < clen + 1) - break; - ++p; - nlen = len - clen - 1; - printer(arg, " <"); - for (; clen > 0; --clen) { - GETCHAR(x, p); - printer(arg, "%.2x", x); - } - printer(arg, ">, name = %.*Z", nlen, p); - break; - case CHAP_FAILURE: - case CHAP_SUCCESS: - printer(arg, " %.*Z", len, p); - break; - default: - for (clen = len; clen > 0; --clen) { - GETCHAR(x, p); - printer(arg, " %.2x", x); - } - } - - return len + CHAP_HEADERLEN; -} - -#endif - -#endif /* PPP_SUPPORT */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/chap.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/chap.h deleted file mode 100644 index 9a4ea4fc0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/chap.h +++ /dev/null @@ -1,167 +0,0 @@ -/***************************************************************************** -* chap.h - Network Challenge Handshake Authentication Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1998 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-03 Guy Lancaster , Global Election Systems Inc. -* Original built from BSD network code. -******************************************************************************/ -/* - * chap.h - Challenge Handshake Authentication Protocol definitions. - * - * Copyright (c) 1993 The Australian National University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by the Australian National University. The name of the University - * may not be used to endorse or promote products derived from this - * software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * Copyright (c) 1991 Gregory M. Christy - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by the author. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id$ - */ - -#ifndef CHAP_H -#define CHAP_H - -/************************* -*** PUBLIC DEFINITIONS *** -*************************/ - -/* Code + ID + length */ -#define CHAP_HEADERLEN 4 - -/* - * CHAP codes. - */ - -#define CHAP_DIGEST_MD5 5 /* use MD5 algorithm */ -#define MD5_SIGNATURE_SIZE 16 /* 16 bytes in a MD5 message digest */ -#define CHAP_MICROSOFT 0x80 /* use Microsoft-compatible alg. */ -#define MS_CHAP_RESPONSE_LEN 49 /* Response length for MS-CHAP */ - -#define CHAP_CHALLENGE 1 -#define CHAP_RESPONSE 2 -#define CHAP_SUCCESS 3 -#define CHAP_FAILURE 4 - -/* - * Challenge lengths (for challenges we send) and other limits. - */ -#define MIN_CHALLENGE_LENGTH 32 -#define MAX_CHALLENGE_LENGTH 64 -#define MAX_RESPONSE_LENGTH 64 /* sufficient for MD5 or MS-CHAP */ - -/* - * Client (peer) states. - */ -#define CHAPCS_INITIAL 0 /* Lower layer down, not opened */ -#define CHAPCS_CLOSED 1 /* Lower layer up, not opened */ -#define CHAPCS_PENDING 2 /* Auth us to peer when lower up */ -#define CHAPCS_LISTEN 3 /* Listening for a challenge */ -#define CHAPCS_RESPONSE 4 /* Sent response, waiting for status */ -#define CHAPCS_OPEN 5 /* We've received Success */ - -/* - * Server (authenticator) states. - */ -#define CHAPSS_INITIAL 0 /* Lower layer down, not opened */ -#define CHAPSS_CLOSED 1 /* Lower layer up, not opened */ -#define CHAPSS_PENDING 2 /* Auth peer when lower up */ -#define CHAPSS_INITIAL_CHAL 3 /* We've sent the first challenge */ -#define CHAPSS_OPEN 4 /* We've sent a Success msg */ -#define CHAPSS_RECHALLENGE 5 /* We've sent another challenge */ -#define CHAPSS_BADAUTH 6 /* We've sent a Failure msg */ - -/************************ -*** PUBLIC DATA TYPES *** -************************/ - -/* - * Each interface is described by a chap structure. - */ - -typedef struct chap_state { - int unit; /* Interface unit number */ - int clientstate; /* Client state */ - int serverstate; /* Server state */ - u_char challenge[MAX_CHALLENGE_LENGTH]; /* last challenge string sent */ - u_char chal_len; /* challenge length */ - u_char chal_id; /* ID of last challenge */ - u_char chal_type; /* hash algorithm for challenges */ - u_char id; /* Current id */ - char *chal_name; /* Our name to use with challenge */ - int chal_interval; /* Time until we challenge peer again */ - int timeouttime; /* Timeout time in seconds */ - int max_transmits; /* Maximum # of challenge transmissions */ - int chal_transmits; /* Number of transmissions of challenge */ - int resp_transmits; /* Number of transmissions of response */ - u_char response[MAX_RESPONSE_LENGTH]; /* Response to send */ - u_char resp_length; /* length of response */ - u_char resp_id; /* ID for response messages */ - u_char resp_type; /* hash algorithm for responses */ - char *resp_name; /* Our name to send with response */ -} chap_state; - - -/****************** -*** PUBLIC DATA *** -******************/ -extern chap_state chap[]; - -extern struct protent chap_protent; - - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ - -void ChapAuthWithPeer (int, char *, int); -void ChapAuthPeer (int, char *, int); - -#endif /* CHAP_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/chpms.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/chpms.c deleted file mode 100644 index 01755ba39..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/chpms.c +++ /dev/null @@ -1,398 +0,0 @@ -/*** WARNING - THIS CODE HAS NOT BEEN FINISHED! ***/ -/***************************************************************************** -* chpms.c - Network MicroSoft Challenge Handshake Authentication Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* Copyright (c) 1997 by Global Election Systems Inc. All rights reserved. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-08 Guy Lancaster , Global Election Systems Inc. -* Original based on BSD chap_ms.c. -*****************************************************************************/ -/* - * chap_ms.c - Microsoft MS-CHAP compatible implementation. - * - * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited. - * http://www.strataware.com/ - * - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Eric Rosenquist. The name of the author may not be used to - * endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -/* - * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997 - * - * Implemented LANManager type password response to MS-CHAP challenges. - * Now pppd provides both NT style and LANMan style blocks, and the - * prefered is set by option "ms-lanman". Default is to use NT. - * The hash text (StdText) was taken from Win95 RASAPI32.DLL. - * - * You should also use DOMAIN\\USERNAME as described in README.MSCHAP80 - */ - -#define USE_CRYPT - - -#include "ppp.h" - -#if MSCHAP_SUPPORT > 0 - -#include "md4.h" -#ifndef USE_CRYPT -#include "des.h" -#endif -#include "chap.h" -#include "chpms.h" -#include "pppdebug.h" - - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ - - -/************************/ -/*** LOCAL DATA TYPES ***/ -/************************/ -typedef struct { - u_char LANManResp[24]; - u_char NTResp[24]; - u_char UseNT; /* If 1, ignore the LANMan response field */ -} MS_ChapResponse; -/* We use MS_CHAP_RESPONSE_LEN, rather than sizeof(MS_ChapResponse), - in case this struct gets padded. */ - - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ - -/* XXX Don't know what to do with these. */ -extern void setkey(const char *); -extern void encrypt(char *, int); - -static void DesEncrypt (u_char *, u_char *, u_char *); -static void MakeKey (u_char *, u_char *); - -#ifdef USE_CRYPT -static void Expand (u_char *, u_char *); -static void Collapse (u_char *, u_char *); -#endif - -static void ChallengeResponse( - u_char *challenge, /* IN 8 octets */ - u_char *pwHash, /* IN 16 octets */ - u_char *response /* OUT 24 octets */ -); -static void ChapMS_NT( - char *rchallenge, - int rchallenge_len, - char *secret, - int secret_len, - MS_ChapResponse *response -); -static u_char Get7Bits( - u_char *input, - int startBit -); - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -void ChapMS( - chap_state *cstate, - char *rchallenge, - int rchallenge_len, - char *secret, - int secret_len -) -{ - MS_ChapResponse response; -#ifdef MSLANMAN - extern int ms_lanman; -#endif - -#if 0 - CHAPDEBUG((LOG_INFO, "ChapMS: secret is '%.*s'\n", secret_len, secret)); -#endif - BZERO(&response, sizeof(response)); - - /* Calculate both always */ - ChapMS_NT(rchallenge, rchallenge_len, secret, secret_len, &response); - -#ifdef MSLANMAN - ChapMS_LANMan(rchallenge, rchallenge_len, secret, secret_len, &response); - - /* prefered method is set by option */ - response.UseNT = !ms_lanman; -#else - response.UseNT = 1; -#endif - - BCOPY(&response, cstate->response, MS_CHAP_RESPONSE_LEN); - cstate->resp_length = MS_CHAP_RESPONSE_LEN; -} - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ -static void ChallengeResponse( - u_char *challenge, /* IN 8 octets */ - u_char *pwHash, /* IN 16 octets */ - u_char *response /* OUT 24 octets */ -) -{ - char ZPasswordHash[21]; - - BZERO(ZPasswordHash, sizeof(ZPasswordHash)); - BCOPY(pwHash, ZPasswordHash, 16); - -#if 0 - log_packet(ZPasswordHash, sizeof(ZPasswordHash), "ChallengeResponse - ZPasswordHash", LOG_DEBUG); -#endif - - DesEncrypt(challenge, ZPasswordHash + 0, response + 0); - DesEncrypt(challenge, ZPasswordHash + 7, response + 8); - DesEncrypt(challenge, ZPasswordHash + 14, response + 16); - -#if 0 - log_packet(response, 24, "ChallengeResponse - response", LOG_DEBUG); -#endif -} - - -#ifdef USE_CRYPT -static void DesEncrypt( - u_char *clear, /* IN 8 octets */ - u_char *key, /* IN 7 octets */ - u_char *cipher /* OUT 8 octets */ -) -{ - u_char des_key[8]; - u_char crypt_key[66]; - u_char des_input[66]; - - MakeKey(key, des_key); - - Expand(des_key, crypt_key); - setkey(crypt_key); - -#if 0 - CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n", - clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7])); -#endif - - Expand(clear, des_input); - encrypt(des_input, 0); - Collapse(des_input, cipher); - -#if 0 - CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n", - cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7])); -#endif -} - -#else /* USE_CRYPT */ - -static void DesEncrypt( - u_char *clear, /* IN 8 octets */ - u_char *key, /* IN 7 octets */ - u_char *cipher /* OUT 8 octets */ -) -{ - des_cblock des_key; - des_key_schedule key_schedule; - - MakeKey(key, des_key); - - des_set_key(&des_key, key_schedule); - -#if 0 - CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet input : %02X%02X%02X%02X%02X%02X%02X%02X\n", - clear[0], clear[1], clear[2], clear[3], clear[4], clear[5], clear[6], clear[7])); -#endif - - des_ecb_encrypt((des_cblock *)clear, (des_cblock *)cipher, key_schedule, 1); - -#if 0 - CHAPDEBUG((LOG_INFO, "DesEncrypt: 8 octet output: %02X%02X%02X%02X%02X%02X%02X%02X\n", - cipher[0], cipher[1], cipher[2], cipher[3], cipher[4], cipher[5], cipher[6], cipher[7])); -#endif -} - -#endif /* USE_CRYPT */ - - -static u_char Get7Bits( - u_char *input, - int startBit -) -{ - register unsigned int word; - - word = (unsigned)input[startBit / 8] << 8; - word |= (unsigned)input[startBit / 8 + 1]; - - word >>= 15 - (startBit % 8 + 7); - - return word & 0xFE; -} - -#ifdef USE_CRYPT - -/* in == 8-byte string (expanded version of the 56-bit key) - * out == 64-byte string where each byte is either 1 or 0 - * Note that the low-order "bit" is always ignored by by setkey() - */ -static void Expand(u_char *in, u_char *out) -{ - int j, c; - int i; - - for(i = 0; i < 64; in++){ - c = *in; - for(j = 7; j >= 0; j--) - *out++ = (c >> j) & 01; - i += 8; - } -} - -/* The inverse of Expand - */ -static void Collapse(u_char *in, u_char *out) -{ - int j; - int i; - unsigned int c; - - for (i = 0; i < 64; i += 8, out++) { - c = 0; - for (j = 7; j >= 0; j--, in++) - c |= *in << j; - *out = c & 0xff; - } -} -#endif - -static void MakeKey( - u_char *key, /* IN 56 bit DES key missing parity bits */ - u_char *des_key /* OUT 64 bit DES key with parity bits added */ -) -{ - des_key[0] = Get7Bits(key, 0); - des_key[1] = Get7Bits(key, 7); - des_key[2] = Get7Bits(key, 14); - des_key[3] = Get7Bits(key, 21); - des_key[4] = Get7Bits(key, 28); - des_key[5] = Get7Bits(key, 35); - des_key[6] = Get7Bits(key, 42); - des_key[7] = Get7Bits(key, 49); - -#ifndef USE_CRYPT - des_set_odd_parity((des_cblock *)des_key); -#endif - -#if 0 - CHAPDEBUG((LOG_INFO, "MakeKey: 56-bit input : %02X%02X%02X%02X%02X%02X%02X\n", - key[0], key[1], key[2], key[3], key[4], key[5], key[6])); - CHAPDEBUG((LOG_INFO, "MakeKey: 64-bit output: %02X%02X%02X%02X%02X%02X%02X%02X\n", - des_key[0], des_key[1], des_key[2], des_key[3], des_key[4], des_key[5], des_key[6], des_key[7])); -#endif -} - -static void ChapMS_NT( - char *rchallenge, - int rchallenge_len, - char *secret, - int secret_len, - MS_ChapResponse *response -) -{ - int i; - MDstruct md4Context; - u_char unicodePassword[MAX_NT_PASSWORD * 2]; - static int low_byte_first = -1; - - /* Initialize the Unicode version of the secret (== password). */ - /* This implicitly supports 8-bit ISO8859/1 characters. */ - BZERO(unicodePassword, sizeof(unicodePassword)); - for (i = 0; i < secret_len; i++) - unicodePassword[i * 2] = (u_char)secret[i]; - - MDbegin(&md4Context); - MDupdate(&md4Context, unicodePassword, secret_len * 2 * 8); /* Unicode is 2 bytes/char, *8 for bit count */ - - if (low_byte_first == -1) - low_byte_first = (htons((unsigned short int)1) != 1); - if (low_byte_first == 0) - MDreverse((u_long *)&md4Context); /* sfb 961105 */ - - MDupdate(&md4Context, NULL, 0); /* Tell MD4 we're done */ - - ChallengeResponse(rchallenge, (char *)md4Context.buffer, response->NTResp); -} - -#ifdef MSLANMAN -static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */ - -static ChapMS_LANMan( - char *rchallenge, - int rchallenge_len, - char *secret, - int secret_len, - MS_ChapResponse *response -) -{ - int i; - u_char UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */ - u_char PasswordHash[16]; - - /* LANMan password is case insensitive */ - BZERO(UcasePassword, sizeof(UcasePassword)); - for (i = 0; i < secret_len; i++) - UcasePassword[i] = (u_char)toupper(secret[i]); - DesEncrypt( StdText, UcasePassword + 0, PasswordHash + 0 ); - DesEncrypt( StdText, UcasePassword + 7, PasswordHash + 8 ); - ChallengeResponse(rchallenge, PasswordHash, response->LANManResp); -} -#endif - -#endif /* MSCHAP_SUPPORT */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/chpms.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/chpms.h deleted file mode 100644 index 1a2bd41d1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/chpms.h +++ /dev/null @@ -1,64 +0,0 @@ -/***************************************************************************** -* chpms.h - Network Microsoft Challenge Handshake Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1998 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 98-01-30 Guy Lancaster , Global Election Systems Inc. -* Original built from BSD network code. -******************************************************************************/ -/* - * chap.h - Challenge Handshake Authentication Protocol definitions. - * - * Copyright (c) 1995 Eric Rosenquist, Strata Software Limited. - * http://www.strataware.com/ - * - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Eric Rosenquist. The name of the author may not be used to - * endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id$ - */ - -#ifndef CHPMS_H -#define CHPMS_H - -#define MAX_NT_PASSWORD 256 /* Maximum number of (Unicode) chars in an NT password */ - -void ChapMS (chap_state *, char *, int, char *, int); - -#endif /* CHPMS_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/fsm.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/fsm.c deleted file mode 100644 index a745bef45..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/fsm.c +++ /dev/null @@ -1,842 +0,0 @@ -/***************************************************************************** -* fsm.c - Network Control Protocol Finite State Machine program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-01 Guy Lancaster , Global Election Systems Inc. -* Original based on BSD fsm.c. -*****************************************************************************/ -/* - * fsm.c - {Link, IP} Control Protocol Finite State Machine. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - - -/* - * TODO: - * Randomize fsm id on link/init. - * Deal with variable outgoing MTU. - */ - -#include "ppp.h" -#if PPP_SUPPORT > 0 -#include "fsm.h" -#include "pppdebug.h" - - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ - - -/************************/ -/*** LOCAL DATA TYPES ***/ -/************************/ - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -static void fsm_timeout (void *); -static void fsm_rconfreq (fsm *, u_char, u_char *, int); -static void fsm_rconfack (fsm *, int, u_char *, int); -static void fsm_rconfnakrej (fsm *, int, int, u_char *, int); -static void fsm_rtermreq (fsm *, int, u_char *, int); -static void fsm_rtermack (fsm *); -static void fsm_rcoderej (fsm *, u_char *, int); -static void fsm_sconfreq (fsm *, int); - -#define PROTO_NAME(f) ((f)->callbacks->proto_name) - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -int peer_mru[NUM_PPP]; - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ - -/* - * fsm_init - Initialize fsm. - * - * Initialize fsm state. - */ -void fsm_init(fsm *f) -{ - f->state = INITIAL; - f->flags = 0; - f->id = 0; /* XXX Start with random id? */ - f->timeouttime = FSM_DEFTIMEOUT; - f->maxconfreqtransmits = FSM_DEFMAXCONFREQS; - f->maxtermtransmits = FSM_DEFMAXTERMREQS; - f->maxnakloops = FSM_DEFMAXNAKLOOPS; - f->term_reason_len = 0; -} - - -/* - * fsm_lowerup - The lower layer is up. - */ -void fsm_lowerup(fsm *f) -{ - int oldState = f->state; - ( void )oldState; - - switch( f->state ){ - case INITIAL: - f->state = CLOSED; - break; - - case STARTING: - if( f->flags & OPT_SILENT ) - f->state = STOPPED; - else { - /* Send an initial configure-request */ - fsm_sconfreq(f, 0); - f->state = REQSENT; - } - break; - - default: - FSMDEBUG((LOG_INFO, "%s: Up event in state %d!\n", - PROTO_NAME(f), f->state)); - } - - FSMDEBUG((LOG_INFO, "%s: lowerup state %d -> %d\n", - PROTO_NAME(f), oldState, f->state)); -} - - -/* - * fsm_lowerdown - The lower layer is down. - * - * Cancel all timeouts and inform upper layers. - */ -void fsm_lowerdown(fsm *f) -{ - int oldState = f->state; - ( void )oldState; - - switch( f->state ){ - case CLOSED: - f->state = INITIAL; - break; - - case STOPPED: - f->state = STARTING; - if( f->callbacks->starting ) - (*f->callbacks->starting)(f); - break; - - case CLOSING: - f->state = INITIAL; - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - break; - - case STOPPING: - case REQSENT: - case ACKRCVD: - case ACKSENT: - f->state = STARTING; - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - break; - - case OPENED: - if( f->callbacks->down ) - (*f->callbacks->down)(f); - f->state = STARTING; - break; - - default: - FSMDEBUG((LOG_INFO, "%s: Down event in state %d!\n", - PROTO_NAME(f), f->state)); - } - - FSMDEBUG((LOG_INFO, "%s: lowerdown state %d -> %d\n", - PROTO_NAME(f), oldState, f->state)); -} - - -/* - * fsm_open - Link is allowed to come up. - */ -void fsm_open(fsm *f) -{ - int oldState = f->state; - ( void )oldState; - - switch( f->state ){ - case INITIAL: - f->state = STARTING; - if( f->callbacks->starting ) - (*f->callbacks->starting)(f); - break; - - case CLOSED: - if( f->flags & OPT_SILENT ) - f->state = STOPPED; - else { - /* Send an initial configure-request */ - fsm_sconfreq(f, 0); - f->state = REQSENT; - } - break; - - case CLOSING: - f->state = STOPPING; - /* fall through */ - case STOPPED: - case OPENED: - if( f->flags & OPT_RESTART ){ - fsm_lowerdown(f); - fsm_lowerup(f); - } - break; - } - - FSMDEBUG((LOG_INFO, "%s: open state %d -> %d\n", - PROTO_NAME(f), oldState, f->state)); -} - - -/* - * fsm_close - Start closing connection. - * - * Cancel timeouts and either initiate close or possibly go directly to - * the CLOSED state. - */ -void fsm_close(fsm *f, char *reason) -{ - int oldState = f->state; - ( void )oldState; - - f->term_reason = reason; - f->term_reason_len = (reason == NULL? 0: strlen(reason)); - switch( f->state ){ - case STARTING: - f->state = INITIAL; - break; - case STOPPED: - f->state = CLOSED; - break; - case STOPPING: - f->state = CLOSING; - break; - - case REQSENT: - case ACKRCVD: - case ACKSENT: - case OPENED: - if( f->state != OPENED ) - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - else if( f->callbacks->down ) - (*f->callbacks->down)(f); /* Inform upper layers we're down */ - - /* Init restart counter, send Terminate-Request */ - f->retransmits = f->maxtermtransmits; - fsm_sdata(f, TERMREQ, f->reqid = ++f->id, - (u_char *) f->term_reason, f->term_reason_len); - TIMEOUT(fsm_timeout, f, f->timeouttime); - --f->retransmits; - - f->state = CLOSING; - break; - } - - FSMDEBUG((LOG_INFO, "%s: close reason=%s state %d -> %d\n", - PROTO_NAME(f), reason, oldState, f->state)); -} - - -/* - * fsm_sdata - Send some data. - * - * Used for all packets sent to our peer by this module. - */ -void fsm_sdata( - fsm *f, - u_char code, - u_char id, - u_char *data, - int datalen -) -{ - u_char *outp; - int outlen; - - /* Adjust length to be smaller than MTU */ - outp = outpacket_buf[f->unit]; - if (datalen > peer_mru[f->unit] - (int)HEADERLEN) - datalen = peer_mru[f->unit] - HEADERLEN; - if (datalen && data != outp + PPP_HDRLEN + HEADERLEN) - BCOPY(data, outp + PPP_HDRLEN + HEADERLEN, datalen); - outlen = datalen + HEADERLEN; - MAKEHEADER(outp, f->protocol); - PUTCHAR(code, outp); - PUTCHAR(id, outp); - PUTSHORT(outlen, outp); - pppWrite(f->unit, outpacket_buf[f->unit], outlen + PPP_HDRLEN); - FSMDEBUG((LOG_INFO, "fsm_sdata(%s): Sent code %d,%d,%d.\n", - PROTO_NAME(f), code, id, outlen)); -} - - -/* - * fsm_input - Input packet. - */ -void fsm_input(fsm *f, u_char *inpacket, int l) -{ - u_char *inp = inpacket; - u_char code, id; - int len; - - /* - * Parse header (code, id and length). - * If packet too short, drop it. - */ - if (l < HEADERLEN) { - FSMDEBUG((LOG_WARNING, "fsm_input(%x): Rcvd short header.\n", - f->protocol)); - return; - } - GETCHAR(code, inp); - GETCHAR(id, inp); - GETSHORT(len, inp); - if (len < HEADERLEN) { - FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd illegal length.\n", - f->protocol)); - return; - } - if (len > l) { - FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd short packet.\n", - f->protocol)); - return; - } - len -= HEADERLEN; /* subtract header length */ - - if( f->state == INITIAL || f->state == STARTING ){ - FSMDEBUG((LOG_INFO, "fsm_input(%x): Rcvd packet in state %d.\n", - f->protocol, f->state)); - return; - } - FSMDEBUG((LOG_INFO, "fsm_input(%s):%d,%d,%d\n", PROTO_NAME(f), code, id, l)); - /* - * Action depends on code. - */ - switch (code) { - case CONFREQ: - fsm_rconfreq(f, id, inp, len); - break; - - case CONFACK: - fsm_rconfack(f, id, inp, len); - break; - - case CONFNAK: - case CONFREJ: - fsm_rconfnakrej(f, code, id, inp, len); - break; - - case TERMREQ: - fsm_rtermreq(f, id, inp, len); - break; - - case TERMACK: - fsm_rtermack(f); - break; - - case CODEREJ: - fsm_rcoderej(f, inp, len); - break; - - default: - if( !f->callbacks->extcode - || !(*f->callbacks->extcode)(f, code, id, inp, len) ) - fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN); - break; - } -} - - -/* - * fsm_protreject - Peer doesn't speak this protocol. - * - * Treat this as a catastrophic error (RXJ-). - */ -void fsm_protreject(fsm *f) -{ - switch( f->state ){ - case CLOSING: - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - /* fall through */ - case CLOSED: - f->state = CLOSED; - if( f->callbacks->finished ) - (*f->callbacks->finished)(f); - break; - - case STOPPING: - case REQSENT: - case ACKRCVD: - case ACKSENT: - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - /* fall through */ - case STOPPED: - f->state = STOPPED; - if( f->callbacks->finished ) - (*f->callbacks->finished)(f); - break; - - case OPENED: - if( f->callbacks->down ) - (*f->callbacks->down)(f); - - /* Init restart counter, send Terminate-Request */ - f->retransmits = f->maxtermtransmits; - fsm_sdata(f, TERMREQ, f->reqid = ++f->id, - (u_char *) f->term_reason, f->term_reason_len); - TIMEOUT(fsm_timeout, f, f->timeouttime); - --f->retransmits; - - f->state = STOPPING; - break; - - default: - FSMDEBUG((LOG_INFO, "%s: Protocol-reject event in state %d!\n", - PROTO_NAME(f), f->state)); - } -} - - - - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ - -/* - * fsm_timeout - Timeout expired. - */ -static void fsm_timeout(void *arg) -{ - fsm *f = (fsm *) arg; - - switch (f->state) { - case CLOSING: - case STOPPING: - if( f->retransmits <= 0 ){ - FSMDEBUG((LOG_WARNING, "%s: timeout sending Terminate-Request state=%d\n", - PROTO_NAME(f), f->state)); - /* - * We've waited for an ack long enough. Peer probably heard us. - */ - f->state = (f->state == CLOSING)? CLOSED: STOPPED; - if( f->callbacks->finished ) - (*f->callbacks->finished)(f); - } else { - FSMDEBUG((LOG_WARNING, "%s: timeout resending Terminate-Requests state=%d\n", - PROTO_NAME(f), f->state)); - /* Send Terminate-Request */ - fsm_sdata(f, TERMREQ, f->reqid = ++f->id, - (u_char *) f->term_reason, f->term_reason_len); - TIMEOUT(fsm_timeout, f, f->timeouttime); - --f->retransmits; - } - break; - - case REQSENT: - case ACKRCVD: - case ACKSENT: - if (f->retransmits <= 0) { - FSMDEBUG((LOG_WARNING, "%s: timeout sending Config-Requests state=%d\n", - PROTO_NAME(f), f->state)); - f->state = STOPPED; - if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished ) - (*f->callbacks->finished)(f); - - } else { - FSMDEBUG((LOG_WARNING, "%s: timeout resending Config-Request state=%d\n", - PROTO_NAME(f), f->state)); - /* Retransmit the configure-request */ - if (f->callbacks->retransmit) - (*f->callbacks->retransmit)(f); - fsm_sconfreq(f, 1); /* Re-send Configure-Request */ - if( f->state == ACKRCVD ) - f->state = REQSENT; - } - break; - - default: - FSMDEBUG((LOG_INFO, "%s: Timeout event in state %d!\n", - PROTO_NAME(f), f->state)); - } -} - - -/* - * fsm_rconfreq - Receive Configure-Request. - */ -static void fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len) -{ - int code, reject_if_disagree; - - FSMDEBUG((LOG_INFO, "fsm_rconfreq(%s): Rcvd id %d state=%d\n", - PROTO_NAME(f), id, f->state)); - switch( f->state ){ - case CLOSED: - /* Go away, we're closed */ - fsm_sdata(f, TERMACK, id, NULL, 0); - return; - case CLOSING: - case STOPPING: - return; - - case OPENED: - /* Go down and restart negotiation */ - if( f->callbacks->down ) - (*f->callbacks->down)(f); /* Inform upper layers */ - fsm_sconfreq(f, 0); /* Send initial Configure-Request */ - break; - - case STOPPED: - /* Negotiation started by our peer */ - fsm_sconfreq(f, 0); /* Send initial Configure-Request */ - f->state = REQSENT; - break; - } - - /* - * Pass the requested configuration options - * to protocol-specific code for checking. - */ - if (f->callbacks->reqci){ /* Check CI */ - reject_if_disagree = (f->nakloops >= f->maxnakloops); - code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree); - } - else if (len) - code = CONFREJ; /* Reject all CI */ - else - code = CONFACK; - - /* send the Ack, Nak or Rej to the peer */ - fsm_sdata(f, (u_char)code, id, inp, len); - - if (code == CONFACK) { - if (f->state == ACKRCVD) { - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - f->state = OPENED; - if (f->callbacks->up) - (*f->callbacks->up)(f); /* Inform upper layers */ - } - else - f->state = ACKSENT; - f->nakloops = 0; - } - else { - /* we sent CONFACK or CONFREJ */ - if (f->state != ACKRCVD) - f->state = REQSENT; - if( code == CONFNAK ) - ++f->nakloops; - } -} - - -/* - * fsm_rconfack - Receive Configure-Ack. - */ -static void fsm_rconfack(fsm *f, int id, u_char *inp, int len) -{ - FSMDEBUG((LOG_INFO, "fsm_rconfack(%s): Rcvd id %d state=%d\n", - PROTO_NAME(f), id, f->state)); - - if (id != f->reqid || f->seen_ack) /* Expected id? */ - return; /* Nope, toss... */ - if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len): - (len == 0)) ){ - /* Ack is bad - ignore it */ - FSMDEBUG((LOG_INFO, "%s: received bad Ack (length %d)\n", - PROTO_NAME(f), len)); - return; - } - f->seen_ack = 1; - - switch (f->state) { - case CLOSED: - case STOPPED: - fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); - break; - - case REQSENT: - f->state = ACKRCVD; - f->retransmits = f->maxconfreqtransmits; - break; - - case ACKRCVD: - /* Huh? an extra valid Ack? oh well... */ - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - fsm_sconfreq(f, 0); - f->state = REQSENT; - break; - - case ACKSENT: - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - f->state = OPENED; - f->retransmits = f->maxconfreqtransmits; - if (f->callbacks->up) - (*f->callbacks->up)(f); /* Inform upper layers */ - break; - - case OPENED: - /* Go down and restart negotiation */ - if (f->callbacks->down) - (*f->callbacks->down)(f); /* Inform upper layers */ - fsm_sconfreq(f, 0); /* Send initial Configure-Request */ - f->state = REQSENT; - break; - } -} - - -/* - * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject. - */ -static void fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len) -{ - int (*proc) (fsm *, u_char *, int); - int ret; - - FSMDEBUG((LOG_INFO, "fsm_rconfnakrej(%s): Rcvd id %d state=%d\n", - PROTO_NAME(f), id, f->state)); - - if (id != f->reqid || f->seen_ack) /* Expected id? */ - return; /* Nope, toss... */ - proc = (code == CONFNAK)? f->callbacks->nakci: f->callbacks->rejci; - if (!proc || !(ret = proc(f, inp, len))) { - /* Nak/reject is bad - ignore it */ - FSMDEBUG((LOG_INFO, "%s: received bad %s (length %d)\n", - PROTO_NAME(f), (code==CONFNAK? "Nak": "reject"), len)); - return; - } - f->seen_ack = 1; - - switch (f->state) { - case CLOSED: - case STOPPED: - fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); - break; - - case REQSENT: - case ACKSENT: - /* They didn't agree to what we wanted - try another request */ - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - if (ret < 0) - f->state = STOPPED; /* kludge for stopping CCP */ - else - fsm_sconfreq(f, 0); /* Send Configure-Request */ - break; - - case ACKRCVD: - /* Got a Nak/reject when we had already had an Ack?? oh well... */ - UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ - fsm_sconfreq(f, 0); - f->state = REQSENT; - break; - - case OPENED: - /* Go down and restart negotiation */ - if (f->callbacks->down) - (*f->callbacks->down)(f); /* Inform upper layers */ - fsm_sconfreq(f, 0); /* Send initial Configure-Request */ - f->state = REQSENT; - break; - } -} - - -/* - * fsm_rtermreq - Receive Terminate-Req. - */ -static void fsm_rtermreq(fsm *f, int id, u_char *p, int len) -{ - FSMDEBUG((LOG_INFO, "fsm_rtermreq(%s): Rcvd id %d state=%d\n", - PROTO_NAME(f), id, f->state)); - - switch (f->state) { - case ACKRCVD: - case ACKSENT: - f->state = REQSENT; /* Start over but keep trying */ - break; - - case OPENED: - if (len > 0) { - FSMDEBUG((LOG_INFO, "%s terminated by peer (%x)\n", PROTO_NAME(f), p)); - } else { - FSMDEBUG((LOG_INFO, "%s terminated by peer\n", PROTO_NAME(f))); - } - if (f->callbacks->down) - (*f->callbacks->down)(f); /* Inform upper layers */ - f->retransmits = 0; - f->state = STOPPING; - TIMEOUT(fsm_timeout, f, f->timeouttime); - break; - } - - fsm_sdata(f, TERMACK, (u_char)id, NULL, 0); -} - - -/* - * fsm_rtermack - Receive Terminate-Ack. - */ -static void fsm_rtermack(fsm *f) -{ - FSMDEBUG((LOG_INFO, "fsm_rtermack(%s): state=%d\n", - PROTO_NAME(f), f->state)); - - switch (f->state) { - case CLOSING: - UNTIMEOUT(fsm_timeout, f); - f->state = CLOSED; - if( f->callbacks->finished ) - (*f->callbacks->finished)(f); - break; - case STOPPING: - UNTIMEOUT(fsm_timeout, f); - f->state = STOPPED; - if( f->callbacks->finished ) - (*f->callbacks->finished)(f); - break; - - case ACKRCVD: - f->state = REQSENT; - break; - - case OPENED: - if (f->callbacks->down) - (*f->callbacks->down)(f); /* Inform upper layers */ - fsm_sconfreq(f, 0); - break; - } -} - - -/* - * fsm_rcoderej - Receive an Code-Reject. - */ -static void fsm_rcoderej(fsm *f, u_char *inp, int len) -{ - u_char code, id; - - FSMDEBUG((LOG_INFO, "fsm_rcoderej(%s): state=%d\n", - PROTO_NAME(f), f->state)); - - if (len < HEADERLEN) { - FSMDEBUG((LOG_INFO, "fsm_rcoderej: Rcvd short Code-Reject packet!\n")); - return; - } - GETCHAR(code, inp); - GETCHAR(id, inp); - FSMDEBUG((LOG_WARNING, "%s: Rcvd Code-Reject for code %d, id %d\n", - PROTO_NAME(f), code, id)); - - if( f->state == ACKRCVD ) - f->state = REQSENT; -} - - -/* - * fsm_sconfreq - Send a Configure-Request. - */ -static void fsm_sconfreq(fsm *f, int retransmit) -{ - u_char *outp; - int cilen; - - if( f->state != REQSENT && f->state != ACKRCVD && f->state != ACKSENT ){ - /* Not currently negotiating - reset options */ - if( f->callbacks->resetci ) - (*f->callbacks->resetci)(f); - f->nakloops = 0; - } - - if( !retransmit ){ - /* New request - reset retransmission counter, use new ID */ - f->retransmits = f->maxconfreqtransmits; - f->reqid = ++f->id; - } - - f->seen_ack = 0; - - /* - * Make up the request packet - */ - outp = outpacket_buf[f->unit] + PPP_HDRLEN + HEADERLEN; - if( f->callbacks->cilen && f->callbacks->addci ){ - cilen = (*f->callbacks->cilen)(f); - if( cilen > peer_mru[f->unit] - (int)HEADERLEN ) - cilen = peer_mru[f->unit] - HEADERLEN; - if (f->callbacks->addci) - (*f->callbacks->addci)(f, outp, &cilen); - } else - cilen = 0; - - /* send the request to our peer */ - fsm_sdata(f, CONFREQ, f->reqid, outp, cilen); - - /* start the retransmit timer */ - --f->retransmits; - TIMEOUT(fsm_timeout, f, f->timeouttime); - - FSMDEBUG((LOG_INFO, "%s: sending Configure-Request, id %d\n", - PROTO_NAME(f), f->reqid)); -} - -#endif /* PPP_SUPPORT */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/fsm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/fsm.h deleted file mode 100644 index b2da3e3e2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/fsm.h +++ /dev/null @@ -1,187 +0,0 @@ -/***************************************************************************** -* fsm.h - Network Control Protocol Finite State Machine header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-11-05 Guy Lancaster , Global Election Systems Inc. -* Original based on BSD code. -*****************************************************************************/ -/* - * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id$ - */ - -#ifndef FSM_H -#define FSM_H - - -/***************************************************************************** -************************* PUBLIC DEFINITIONS ********************************* -*****************************************************************************/ -/* - * LCP Packet header = Code, id, length. - */ -#define HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short)) - - -/* - * CP (LCP, IPCP, etc.) codes. - */ -#define CONFREQ 1 /* Configuration Request */ -#define CONFACK 2 /* Configuration Ack */ -#define CONFNAK 3 /* Configuration Nak */ -#define CONFREJ 4 /* Configuration Reject */ -#define TERMREQ 5 /* Termination Request */ -#define TERMACK 6 /* Termination Ack */ -#define CODEREJ 7 /* Code Reject */ - -/* - * Link states. - */ -#define INITIAL 0 /* Down, hasn't been opened */ -#define STARTING 1 /* Down, been opened */ -#define CLOSED 2 /* Up, hasn't been opened */ -#define STOPPED 3 /* Open, waiting for down event */ -#define CLOSING 4 /* Terminating the connection, not open */ -#define STOPPING 5 /* Terminating, but open */ -#define REQSENT 6 /* We've sent a Config Request */ -#define ACKRCVD 7 /* We've received a Config Ack */ -#define ACKSENT 8 /* We've sent a Config Ack */ -#define OPENED 9 /* Connection available */ - - -/* - * Flags - indicate options controlling FSM operation - */ -#define OPT_PASSIVE 1 /* Don't die if we don't get a response */ -#define OPT_RESTART 2 /* Treat 2nd OPEN as DOWN, UP */ -#define OPT_SILENT 4 /* Wait for peer to speak first */ - - -/***************************************************************************** -************************* PUBLIC DATA TYPES ********************************** -*****************************************************************************/ -/* - * Each FSM is described by an fsm structure and fsm callbacks. - */ -typedef struct fsm { - int unit; /* Interface unit number */ - u_short protocol; /* Data Link Layer Protocol field value */ - int state; /* State */ - int flags; /* Contains option bits */ - u_char id; /* Current id */ - u_char reqid; /* Current request id */ - u_char seen_ack; /* Have received valid Ack/Nak/Rej to Req */ - int timeouttime; /* Timeout time in milliseconds */ - int maxconfreqtransmits;/* Maximum Configure-Request transmissions */ - int retransmits; /* Number of retransmissions left */ - int maxtermtransmits; /* Maximum Terminate-Request transmissions */ - int nakloops; /* Number of nak loops since last ack */ - int maxnakloops; /* Maximum number of nak loops tolerated */ - struct fsm_callbacks* callbacks;/* Callback routines */ - char* term_reason; /* Reason for closing protocol */ - int term_reason_len; /* Length of term_reason */ -} fsm; - - -typedef struct fsm_callbacks { - void (*resetci) /* Reset our Configuration Information */ - (fsm*); - int (*cilen) /* Length of our Configuration Information */ - (fsm*); - void (*addci) /* Add our Configuration Information */ - (fsm*, u_char*, int*); - int (*ackci) /* ACK our Configuration Information */ - (fsm*, u_char*, int); - int (*nakci) /* NAK our Configuration Information */ - (fsm*, u_char*, int); - int (*rejci) /* Reject our Configuration Information */ - (fsm*, u_char*, int); - int (*reqci) /* Request peer's Configuration Information */ - (fsm*, u_char*, int*, int); - void (*up) /* Called when fsm reaches OPENED state */ - (fsm*); - void (*down) /* Called when fsm leaves OPENED state */ - (fsm*); - void (*starting) /* Called when we want the lower layer */ - (fsm*); - void (*finished) /* Called when we don't want the lower layer */ - (fsm*); - void (*protreject) /* Called when Protocol-Reject received */ - (int); - void (*retransmit) /* Retransmission is necessary */ - (fsm*); - int (*extcode) /* Called when unknown code received */ - (fsm*, int, u_char, u_char*, int); - char *proto_name; /* String name for protocol (for messages) */ -} fsm_callbacks; - - -/***************************************************************************** -*********************** PUBLIC DATA STRUCTURES ******************************* -*****************************************************************************/ -/* - * Variables - */ -extern int peer_mru[]; /* currently negotiated peer MRU (per unit) */ - - -/***************************************************************************** -************************** PUBLIC FUNCTIONS ********************************** -*****************************************************************************/ - -/* - * Prototypes - */ -void fsm_init (fsm*); -void fsm_lowerup (fsm*); -void fsm_lowerdown (fsm*); -void fsm_open (fsm*); -void fsm_close (fsm*, char*); -void fsm_input (fsm*, u_char*, int); -void fsm_protreject (fsm*); -void fsm_sdata (fsm*, u_char, u_char, u_char*, int); - - -#endif /* FSM_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/ipcp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/ipcp.c deleted file mode 100644 index d5b251880..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/ipcp.c +++ /dev/null @@ -1,1377 +0,0 @@ -/***************************************************************************** -* ipcp.c - Network PPP IP Control Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-08 Guy Lancaster , Global Election Systems Inc. -* Original. -*****************************************************************************/ -/* - * ipcp.c - PPP IP Control Protocol. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include - -#include "ppp.h" -#if PPP_SUPPORT > 0 -#include "auth.h" -#include "fsm.h" -#include "vj.h" -#include "ipcp.h" -#include "pppdebug.h" - - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ -/* #define OLD_CI_ADDRS 1 */ /* Support deprecated address negotiation. */ - -/* - * Lengths of configuration options. - */ -#define CILEN_VOID 2 -#define CILEN_COMPRESS 4 /* min length for compression protocol opt. */ -#define CILEN_VJ 6 /* length for RFC1332 Van-Jacobson opt. */ -#define CILEN_ADDR 6 /* new-style single address option */ -#define CILEN_ADDRS 10 /* old-style dual address option */ - - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -/* - * Callbacks for fsm code. (CI = Configuration Information) - */ -static void ipcp_resetci (fsm *); /* Reset our CI */ -static int ipcp_cilen (fsm *); /* Return length of our CI */ -static void ipcp_addci (fsm *, u_char *, int *); /* Add our CI */ -static int ipcp_ackci (fsm *, u_char *, int); /* Peer ack'd our CI */ -static int ipcp_nakci (fsm *, u_char *, int); /* Peer nak'd our CI */ -static int ipcp_rejci (fsm *, u_char *, int); /* Peer rej'd our CI */ -static int ipcp_reqci (fsm *, u_char *, int *, int); /* Rcv CI */ -static void ipcp_up (fsm *); /* We're UP */ -static void ipcp_down (fsm *); /* We're DOWN */ -#if 0 -static void ipcp_script (fsm *, char *); /* Run an up/down script */ -#endif -static void ipcp_finished (fsm *); /* Don't need lower layer */ - -/* - * Protocol entry points from main code. - */ -static void ipcp_init (int); -static void ipcp_open (int); -static void ipcp_close (int, char *); -static void ipcp_lowerup (int); -static void ipcp_lowerdown (int); -static void ipcp_input (int, u_char *, int); -static void ipcp_protrej (int); - -static void ipcp_clear_addrs (int); - -#define CODENAME(x) ((x) == CONFACK ? "ACK" : \ - (x) == CONFNAK ? "NAK" : "REJ") - - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ -/* global vars */ -ipcp_options ipcp_wantoptions[NUM_PPP]; /* Options that we want to request */ -ipcp_options ipcp_gotoptions[NUM_PPP]; /* Options that peer ack'd */ -ipcp_options ipcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */ -ipcp_options ipcp_hisoptions[NUM_PPP]; /* Options that we ack'd */ - -fsm ipcp_fsm[NUM_PPP]; /* IPCP fsm structure */ - -struct protent ipcp_protent = { - PPP_IPCP, - ipcp_init, - ipcp_input, - ipcp_protrej, - ipcp_lowerup, - ipcp_lowerdown, - ipcp_open, - ipcp_close, -#if 0 - ipcp_printpkt, - NULL, -#endif - 1, - "IPCP", -#if 0 - ip_check_options, - NULL, - ip_active_pkt -#endif -}; - - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -/* local vars */ -static int cis_received[NUM_PPP]; /* # Conf-Reqs received */ -static int default_route_set[NUM_PPP]; /* Have set up a default route */ - -static fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */ - ipcp_resetci, /* Reset our Configuration Information */ - ipcp_cilen, /* Length of our Configuration Information */ - ipcp_addci, /* Add our Configuration Information */ - ipcp_ackci, /* ACK our Configuration Information */ - ipcp_nakci, /* NAK our Configuration Information */ - ipcp_rejci, /* Reject our Configuration Information */ - ipcp_reqci, /* Request peer's Configuration Information */ - ipcp_up, /* Called when fsm reaches OPENED state */ - ipcp_down, /* Called when fsm leaves OPENED state */ - NULL, /* Called when we want the lower layer up */ - ipcp_finished, /* Called when we want the lower layer down */ - NULL, /* Called when Protocol-Reject received */ - NULL, /* Retransmission is necessary */ - NULL, /* Called to handle protocol-specific codes */ - "IPCP" /* String name of protocol */ -}; - - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ - -/* - * Non-standard inet_ntoa left here for compat with original ppp - * sources. Assumes u32_t instead of struct in_addr. - */ - -char * _inet_ntoa(u32_t n) -{ - struct in_addr ia; - ia.s_addr = n; - return inet_ntoa(ia); -} - -#define inet_ntoa _inet_ntoa - -/* - * ipcp_init - Initialize IPCP. - */ -static void ipcp_init(int unit) -{ - fsm *f = &ipcp_fsm[unit]; - ipcp_options *wo = &ipcp_wantoptions[unit]; - ipcp_options *ao = &ipcp_allowoptions[unit]; - - f->unit = unit; - f->protocol = PPP_IPCP; - f->callbacks = &ipcp_callbacks; - fsm_init(&ipcp_fsm[unit]); - - memset(wo, 0, sizeof(*wo)); - memset(ao, 0, sizeof(*ao)); - - wo->neg_addr = 1; - wo->ouraddr = 0; -#if VJ_SUPPORT > 0 - wo->neg_vj = 1; -#else - wo->neg_vj = 0; -#endif - wo->vj_protocol = IPCP_VJ_COMP; - wo->maxslotindex = MAX_SLOTS - 1; - wo->cflag = 0; - - wo->default_route = 1; - - ao->neg_addr = 1; -#if VJ_SUPPORT > 0 - ao->neg_vj = 1; -#else - ao->neg_vj = 0; -#endif - ao->maxslotindex = MAX_SLOTS - 1; - ao->cflag = 1; - - ao->default_route = 1; -} - - -/* - * ipcp_open - IPCP is allowed to come up. - */ -static void ipcp_open(int unit) -{ - fsm_open(&ipcp_fsm[unit]); -} - - -/* - * ipcp_close - Take IPCP down. - */ -static void ipcp_close(int unit, char *reason) -{ - fsm_close(&ipcp_fsm[unit], reason); -} - - -/* - * ipcp_lowerup - The lower layer is up. - */ -static void ipcp_lowerup(int unit) -{ - fsm_lowerup(&ipcp_fsm[unit]); -} - - -/* - * ipcp_lowerdown - The lower layer is down. - */ -static void ipcp_lowerdown(int unit) -{ - fsm_lowerdown(&ipcp_fsm[unit]); -} - - -/* - * ipcp_input - Input IPCP packet. - */ -static void ipcp_input(int unit, u_char *p, int len) -{ - fsm_input(&ipcp_fsm[unit], p, len); -} - - -/* - * ipcp_protrej - A Protocol-Reject was received for IPCP. - * - * Pretend the lower layer went down, so we shut up. - */ -static void ipcp_protrej(int unit) -{ - fsm_lowerdown(&ipcp_fsm[unit]); -} - - -/* - * ipcp_resetci - Reset our CI. - */ -static void ipcp_resetci(fsm *f) -{ - ipcp_options *wo = &ipcp_wantoptions[f->unit]; - - wo->req_addr = wo->neg_addr && ipcp_allowoptions[f->unit].neg_addr; - if (wo->ouraddr == 0) - wo->accept_local = 1; - if (wo->hisaddr == 0) - wo->accept_remote = 1; - /* Request DNS addresses from the peer */ - wo->req_dns1 = ppp_settings.usepeerdns; - wo->req_dns2 = ppp_settings.usepeerdns; - ipcp_gotoptions[f->unit] = *wo; - cis_received[f->unit] = 0; -} - - -/* - * ipcp_cilen - Return length of our CI. - */ -static int ipcp_cilen(fsm *f) -{ - ipcp_options *go = &ipcp_gotoptions[f->unit]; - ipcp_options *wo = &ipcp_wantoptions[f->unit]; - ipcp_options *ho = &ipcp_hisoptions[f->unit]; - -#define LENCIVJ(neg, old) (neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0) -#define LENCIADDR(neg, old) (neg ? (old? CILEN_ADDRS : CILEN_ADDR) : 0) -#define LENCIDNS(neg) (neg ? (CILEN_ADDR) : 0) - - /* - * First see if we want to change our options to the old - * forms because we have received old forms from the peer. - */ - if (wo->neg_addr && !go->neg_addr && !go->old_addrs) { - /* use the old style of address negotiation */ - go->neg_addr = 1; - go->old_addrs = 1; - } - if (wo->neg_vj && !go->neg_vj && !go->old_vj) { - /* try an older style of VJ negotiation */ - if (cis_received[f->unit] == 0) { - /* keep trying the new style until we see some CI from the peer */ - go->neg_vj = 1; - } else { - /* use the old style only if the peer did */ - if (ho->neg_vj && ho->old_vj) { - go->neg_vj = 1; - go->old_vj = 1; - go->vj_protocol = ho->vj_protocol; - } - } - } - - return (LENCIADDR(go->neg_addr, go->old_addrs) - + LENCIVJ(go->neg_vj, go->old_vj) + - LENCIDNS(go->req_dns1) + - LENCIDNS(go->req_dns2)); -} - - -/* - * ipcp_addci - Add our desired CIs to a packet. - */ -static void ipcp_addci(fsm *f, u_char *ucp, int *lenp) -{ - ipcp_options *go = &ipcp_gotoptions[f->unit]; - int len = *lenp; - -#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \ - if (neg) { \ - int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \ - if (len >= vjlen) { \ - PUTCHAR(opt, ucp); \ - PUTCHAR(vjlen, ucp); \ - PUTSHORT(val, ucp); \ - if (!old) { \ - PUTCHAR(maxslotindex, ucp); \ - PUTCHAR(cflag, ucp); \ - } \ - len -= vjlen; \ - } else \ - neg = 0; \ - } - -#define ADDCIADDR(opt, neg, old, val1, val2) \ - if (neg) { \ - int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \ - if (len >= addrlen) { \ - u32_t l; \ - PUTCHAR(opt, ucp); \ - PUTCHAR(addrlen, ucp); \ - l = ntohl(val1); \ - PUTLONG(l, ucp); \ - if (old) { \ - l = ntohl(val2); \ - PUTLONG(l, ucp); \ - } \ - len -= addrlen; \ - } else \ - neg = 0; \ - } - -#define ADDCIDNS(opt, neg, addr) \ - if (neg) { \ - if (len >= CILEN_ADDR) { \ - u32_t l; \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_ADDR, ucp); \ - l = ntohl(addr); \ - PUTLONG(l, ucp); \ - len -= CILEN_ADDR; \ - } else \ - neg = 0; \ - } - - ADDCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr, - go->old_addrs, go->ouraddr, go->hisaddr); - - ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj, - go->maxslotindex, go->cflag); - - ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]); - - ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]); - - *lenp -= len; -} - - -/* - * ipcp_ackci - Ack our CIs. - * - * Returns: - * 0 - Ack was bad. - * 1 - Ack was good. - */ -static int ipcp_ackci(fsm *f, u_char *p, int len) -{ - ipcp_options *go = &ipcp_gotoptions[f->unit]; - u_short cilen, citype, cishort; - u32_t cilong; - u_char cimaxslotindex, cicflag; - - /* - * CIs must be in exactly the same order that we sent... - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ - -#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \ - if (neg) { \ - int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \ - if ((len -= vjlen) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != vjlen || \ - citype != opt) \ - goto bad; \ - GETSHORT(cishort, p); \ - if (cishort != val) \ - goto bad; \ - if (!old) { \ - GETCHAR(cimaxslotindex, p); \ - if (cimaxslotindex != maxslotindex) \ - goto bad; \ - GETCHAR(cicflag, p); \ - if (cicflag != cflag) \ - goto bad; \ - } \ - } - -#define ACKCIADDR(opt, neg, old, val1, val2) \ - if (neg) { \ - int addrlen = (old? CILEN_ADDRS: CILEN_ADDR); \ - u32_t l; \ - if ((len -= addrlen) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != addrlen || \ - citype != opt) \ - goto bad; \ - GETLONG(l, p); \ - cilong = htonl(l); \ - if (val1 != cilong) \ - goto bad; \ - if (old) { \ - GETLONG(l, p); \ - cilong = htonl(l); \ - if (val2 != cilong) \ - goto bad; \ - } \ - } - -#define ACKCIDNS(opt, neg, addr) \ - if (neg) { \ - u32_t l; \ - if ((len -= CILEN_ADDR) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_ADDR || \ - citype != opt) \ - goto bad; \ - GETLONG(l, p); \ - cilong = htonl(l); \ - if (addr != cilong) \ - goto bad; \ - } - - ACKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), go->neg_addr, - go->old_addrs, go->ouraddr, go->hisaddr); - - ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj, - go->maxslotindex, go->cflag); - - ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]); - - ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]); - - /* - * If there are any remaining CIs, then this packet is bad. - */ - if (len != 0) - goto bad; - return (1); - -bad: - IPCPDEBUG((LOG_INFO, "ipcp_ackci: received bad Ack!\n")); - return (0); -} - -/* - * ipcp_nakci - Peer has sent a NAK for some of our CIs. - * This should not modify any state if the Nak is bad - * or if IPCP is in the OPENED state. - * - * Returns: - * 0 - Nak was bad. - * 1 - Nak was good. - */ -static int ipcp_nakci(fsm *f, u_char *p, int len) -{ - ipcp_options *go = &ipcp_gotoptions[f->unit]; - u_char cimaxslotindex, cicflag; - u_char citype, cilen, *next; - u_short cishort; - u32_t ciaddr1, ciaddr2, l, cidnsaddr; - ipcp_options no; /* options we've seen Naks for */ - ipcp_options try; /* options to request next time */ - - BZERO(&no, sizeof(no)); - try = *go; - - /* - * Any Nak'd CIs must be in exactly the same order that we sent. - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ -#define NAKCIADDR(opt, neg, old, code) \ - if (go->neg && \ - len >= (cilen = (old? CILEN_ADDRS: CILEN_ADDR)) && \ - p[1] == cilen && \ - p[0] == opt) { \ - len -= cilen; \ - INCPTR(2, p); \ - GETLONG(l, p); \ - ciaddr1 = htonl(l); \ - if (old) { \ - GETLONG(l, p); \ - ciaddr2 = htonl(l); \ - no.old_addrs = 1; \ - } else \ - ciaddr2 = 0; \ - no.neg = 1; \ - code \ - } - -#define NAKCIVJ(opt, neg, code) \ - if (go->neg && \ - ((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \ - len >= cilen && \ - p[0] == opt) { \ - len -= cilen; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - no.neg = 1; \ - code \ - } - -#define NAKCIDNS(opt, neg, code) \ - if (go->neg && \ - ((cilen = p[1]) == CILEN_ADDR) && \ - len >= cilen && \ - p[0] == opt) { \ - len -= cilen; \ - INCPTR(2, p); \ - GETLONG(l, p); \ - cidnsaddr = htonl(l); \ - no.neg = 1; \ - code \ - } - - /* - * Accept the peer's idea of {our,his} address, if different - * from our idea, only if the accept_{local,remote} flag is set. - */ - NAKCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, go->old_addrs, - if (go->accept_local && ciaddr1) { /* Do we know our address? */ - try.ouraddr = ciaddr1; - IPCPDEBUG((LOG_INFO, "local IP address %s\n", - inet_ntoa(ciaddr1))); - } - if (go->accept_remote && ciaddr2) { /* Does he know his? */ - try.hisaddr = ciaddr2; - IPCPDEBUG((LOG_INFO, "remote IP address %s\n", - inet_ntoa(ciaddr2))); - } - ); - - /* - * Accept the peer's value of maxslotindex provided that it - * is less than what we asked for. Turn off slot-ID compression - * if the peer wants. Send old-style compress-type option if - * the peer wants. - */ - NAKCIVJ(CI_COMPRESSTYPE, neg_vj, - if (cilen == CILEN_VJ) { - GETCHAR(cimaxslotindex, p); - GETCHAR(cicflag, p); - if (cishort == IPCP_VJ_COMP) { - try.old_vj = 0; - if (cimaxslotindex < go->maxslotindex) - try.maxslotindex = cimaxslotindex; - if (!cicflag) - try.cflag = 0; - } else { - try.neg_vj = 0; - } - } else { - if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) { - try.old_vj = 1; - try.vj_protocol = cishort; - } else { - try.neg_vj = 0; - } - } - ); - - NAKCIDNS(CI_MS_DNS1, req_dns1, - try.dnsaddr[0] = cidnsaddr; - IPCPDEBUG((LOG_INFO, "primary DNS address %s\n", inet_ntoa(cidnsaddr))); - ); - - NAKCIDNS(CI_MS_DNS2, req_dns2, - try.dnsaddr[1] = cidnsaddr; - IPCPDEBUG((LOG_INFO, "secondary DNS address %s\n", inet_ntoa(cidnsaddr))); - ); - - /* - * There may be remaining CIs, if the peer is requesting negotiation - * on an option that we didn't include in our request packet. - * If they want to negotiate about IP addresses, we comply. - * If they want us to ask for compression, we refuse. - */ - while (len > CILEN_VOID) { - GETCHAR(citype, p); - GETCHAR(cilen, p); - if( (len -= cilen) < 0 ) - goto bad; - next = p + cilen - 2; - - switch (citype) { - case CI_COMPRESSTYPE: - if (go->neg_vj || no.neg_vj || - (cilen != CILEN_VJ && cilen != CILEN_COMPRESS)) - goto bad; - no.neg_vj = 1; - break; - case CI_ADDRS: - if ((go->neg_addr && go->old_addrs) || no.old_addrs - || cilen != CILEN_ADDRS) - goto bad; - try.neg_addr = 1; - try.old_addrs = 1; - GETLONG(l, p); - ciaddr1 = htonl(l); - if (ciaddr1 && go->accept_local) - try.ouraddr = ciaddr1; - GETLONG(l, p); - ciaddr2 = htonl(l); - if (ciaddr2 && go->accept_remote) - try.hisaddr = ciaddr2; - no.old_addrs = 1; - break; - case CI_ADDR: - if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR) - goto bad; - try.old_addrs = 0; - GETLONG(l, p); - ciaddr1 = htonl(l); - if (ciaddr1 && go->accept_local) - try.ouraddr = ciaddr1; - if (try.ouraddr != 0) - try.neg_addr = 1; - no.neg_addr = 1; - break; - } - p = next; - } - - /* If there is still anything left, this packet is bad. */ - if (len != 0) - goto bad; - - /* - * OK, the Nak is good. Now we can update state. - */ - if (f->state != OPENED) - *go = try; - - return 1; - -bad: - IPCPDEBUG((LOG_INFO, "ipcp_nakci: received bad Nak!\n")); - return 0; -} - - -/* - * ipcp_rejci - Reject some of our CIs. - */ -static int ipcp_rejci(fsm *f, u_char *p, int len) -{ - ipcp_options *go = &ipcp_gotoptions[f->unit]; - u_char cimaxslotindex, ciflag, cilen; - u_short cishort; - u32_t cilong; - ipcp_options try; /* options to request next time */ - - try = *go; - /* - * Any Rejected CIs must be in exactly the same order that we sent. - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ -#define REJCIADDR(opt, neg, old, val1, val2) \ - if (go->neg && \ - len >= (cilen = old? CILEN_ADDRS: CILEN_ADDR) && \ - p[1] == cilen && \ - p[0] == opt) { \ - u32_t l; \ - len -= cilen; \ - INCPTR(2, p); \ - GETLONG(l, p); \ - cilong = htonl(l); \ - /* Check rejected value. */ \ - if (cilong != val1) \ - goto bad; \ - if (old) { \ - GETLONG(l, p); \ - cilong = htonl(l); \ - /* Check rejected value. */ \ - if (cilong != val2) \ - goto bad; \ - } \ - try.neg = 0; \ - } - -#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \ - if (go->neg && \ - p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \ - len >= p[1] && \ - p[0] == opt) { \ - len -= p[1]; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - /* Check rejected value. */ \ - if (cishort != val) \ - goto bad; \ - if (!old) { \ - GETCHAR(cimaxslotindex, p); \ - if (cimaxslotindex != maxslot) \ - goto bad; \ - GETCHAR(ciflag, p); \ - if (ciflag != cflag) \ - goto bad; \ - } \ - try.neg = 0; \ - } - -#define REJCIDNS(opt, neg, dnsaddr) \ - if (go->neg && \ - ((cilen = p[1]) == CILEN_ADDR) && \ - len >= cilen && \ - p[0] == opt) { \ - u32_t l; \ - len -= cilen; \ - INCPTR(2, p); \ - GETLONG(l, p); \ - cilong = htonl(l); \ - /* Check rejected value. */ \ - if (cilong != dnsaddr) \ - goto bad; \ - try.neg = 0; \ - } - - REJCIADDR((go->old_addrs? CI_ADDRS: CI_ADDR), neg_addr, - go->old_addrs, go->ouraddr, go->hisaddr); - - REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj, - go->maxslotindex, go->cflag); - - REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]); - - REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]); - - /* - * If there are any remaining CIs, then this packet is bad. - */ - if (len != 0) - goto bad; - /* - * Now we can update state. - */ - if (f->state != OPENED) - *go = try; - return 1; - -bad: - IPCPDEBUG((LOG_INFO, "ipcp_rejci: received bad Reject!\n")); - return 0; -} - - -/* - * ipcp_reqci - Check the peer's requested CIs and send appropriate response. - * - * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified - * appropriately. If reject_if_disagree is non-zero, doesn't return - * CONFNAK; returns CONFREJ if it can't return CONFACK. - */ -static int ipcp_reqci( - fsm *f, - u_char *inp, /* Requested CIs */ - int *len, /* Length of requested CIs */ - int reject_if_disagree -) -{ - ipcp_options *wo = &ipcp_wantoptions[f->unit]; - ipcp_options *ho = &ipcp_hisoptions[f->unit]; - ipcp_options *ao = &ipcp_allowoptions[f->unit]; -#ifdef OLD_CI_ADDRS - ipcp_options *go = &ipcp_gotoptions[f->unit]; -#endif - u_char *cip, *next; /* Pointer to current and next CIs */ - u_short cilen, citype; /* Parsed len, type */ - u_short cishort; /* Parsed short value */ - u32_t tl, ciaddr1; /* Parsed address values */ -#ifdef OLD_CI_ADDRS - u32_t ciaddr2; /* Parsed address values */ -#endif - int rc = CONFACK; /* Final packet return code */ - int orc; /* Individual option return code */ - u_char *p; /* Pointer to next char to parse */ - u_char *ucp = inp; /* Pointer to current output char */ - int l = *len; /* Length left */ - u_char maxslotindex, cflag; - int d; - - cis_received[f->unit] = 1; - - /* - * Reset all his options. - */ - BZERO(ho, sizeof(*ho)); - - /* - * Process all his options. - */ - next = inp; - while (l) { - orc = CONFACK; /* Assume success */ - cip = p = next; /* Remember begining of CI */ - if (l < 2 || /* Not enough data for CI header or */ - p[1] < 2 || /* CI length too small or */ - p[1] > l) { /* CI length too big? */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: bad CI length!\n")); - orc = CONFREJ; /* Reject bad CI */ - cilen = l; /* Reject till end of packet */ - l = 0; /* Don't loop again */ - goto endswitch; - } - GETCHAR(citype, p); /* Parse CI type */ - GETCHAR(cilen, p); /* Parse CI length */ - l -= cilen; /* Adjust remaining length */ - next += cilen; /* Step to next CI */ - - switch (citype) { /* Check CI type */ -#ifdef OLD_CI_ADDRS /* Need to save space... */ - case CI_ADDRS: - IPCPDEBUG((LOG_INFO, "ipcp_reqci: received ADDRS\n")); - if (!ao->neg_addr || - cilen != CILEN_ADDRS) { /* Check CI length */ - orc = CONFREJ; /* Reject CI */ - break; - } - - /* - * If he has no address, or if we both have his address but - * disagree about it, then NAK it with our idea. - * In particular, if we don't know his address, but he does, - * then accept it. - */ - GETLONG(tl, p); /* Parse source address (his) */ - ciaddr1 = htonl(tl); - IPCPDEBUG((LOG_INFO, "his addr %s\n", inet_ntoa(ciaddr1))); - if (ciaddr1 != wo->hisaddr - && (ciaddr1 == 0 || !wo->accept_remote)) { - orc = CONFNAK; - if (!reject_if_disagree) { - DECPTR(sizeof(u32_t), p); - tl = ntohl(wo->hisaddr); - PUTLONG(tl, p); - } - } else if (ciaddr1 == 0 && wo->hisaddr == 0) { - /* - * If neither we nor he knows his address, reject the option. - */ - orc = CONFREJ; - wo->req_addr = 0; /* don't NAK with 0.0.0.0 later */ - break; - } - - /* - * If he doesn't know our address, or if we both have our address - * but disagree about it, then NAK it with our idea. - */ - GETLONG(tl, p); /* Parse desination address (ours) */ - ciaddr2 = htonl(tl); - IPCPDEBUG((LOG_INFO, "our addr %s\n", inet_ntoa(ciaddr2))); - if (ciaddr2 != wo->ouraddr) { - if (ciaddr2 == 0 || !wo->accept_local) { - orc = CONFNAK; - if (!reject_if_disagree) { - DECPTR(sizeof(u32_t), p); - tl = ntohl(wo->ouraddr); - PUTLONG(tl, p); - } - } else { - go->ouraddr = ciaddr2; /* accept peer's idea */ - } - } - - ho->neg_addr = 1; - ho->old_addrs = 1; - ho->hisaddr = ciaddr1; - ho->ouraddr = ciaddr2; - break; -#endif - - case CI_ADDR: - if (!ao->neg_addr) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR not allowed\n")); - orc = CONFREJ; /* Reject CI */ - break; - } else if (cilen != CILEN_ADDR) { /* Check CI length */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR bad len\n")); - orc = CONFREJ; /* Reject CI */ - break; - } - - /* - * If he has no address, or if we both have his address but - * disagree about it, then NAK it with our idea. - * In particular, if we don't know his address, but he does, - * then accept it. - */ - GETLONG(tl, p); /* Parse source address (his) */ - ciaddr1 = htonl(tl); - if (ciaddr1 != wo->hisaddr - && (ciaddr1 == 0 || !wo->accept_remote)) { - orc = CONFNAK; - if (!reject_if_disagree) { - DECPTR(sizeof(u32_t), p); - tl = ntohl(wo->hisaddr); - PUTLONG(tl, p); - } - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Nak ADDR %s\n", inet_ntoa(ciaddr1))); - } else if (ciaddr1 == 0 && wo->hisaddr == 0) { - /* - * Don't ACK an address of 0.0.0.0 - reject it instead. - */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Reject ADDR %s\n", inet_ntoa(ciaddr1))); - orc = CONFREJ; - wo->req_addr = 0; /* don't NAK with 0.0.0.0 later */ - break; - } - - ho->neg_addr = 1; - ho->hisaddr = ciaddr1; - IPCPDEBUG((LOG_INFO, "ipcp_reqci: ADDR %s\n", inet_ntoa(ciaddr1))); - break; - - case CI_MS_DNS1: - case CI_MS_DNS2: - /* Microsoft primary or secondary DNS request */ - d = citype == CI_MS_DNS2; - - /* If we do not have a DNS address then we cannot send it */ - if (ao->dnsaddr[d] == 0 || - cilen != CILEN_ADDR) { /* Check CI length */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting DNS%d Request\n", d+1)); - orc = CONFREJ; /* Reject CI */ - break; - } - GETLONG(tl, p); - if (htonl(tl) != ao->dnsaddr[d]) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking DNS%d Request %d\n", - d+1, inet_ntoa(tl))); - DECPTR(sizeof(u32_t), p); - tl = ntohl(ao->dnsaddr[d]); - PUTLONG(tl, p); - orc = CONFNAK; - } - IPCPDEBUG((LOG_INFO, "ipcp_reqci: received DNS%d Request\n", d+1)); - break; - - case CI_MS_WINS1: - case CI_MS_WINS2: - /* Microsoft primary or secondary WINS request */ - d = citype == CI_MS_WINS2; - IPCPDEBUG((LOG_INFO, "ipcp_reqci: received WINS%d Request\n", d+1)); - - /* If we do not have a DNS address then we cannot send it */ - if (ao->winsaddr[d] == 0 || - cilen != CILEN_ADDR) { /* Check CI length */ - orc = CONFREJ; /* Reject CI */ - break; - } - GETLONG(tl, p); - if (htonl(tl) != ao->winsaddr[d]) { - DECPTR(sizeof(u32_t), p); - tl = ntohl(ao->winsaddr[d]); - PUTLONG(tl, p); - orc = CONFNAK; - } - break; - - case CI_COMPRESSTYPE: - if (!ao->neg_vj) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE not allowed\n")); - orc = CONFREJ; - break; - } else if (cilen != CILEN_VJ && cilen != CILEN_COMPRESS) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE len=%d\n", cilen)); - orc = CONFREJ; - break; - } - GETSHORT(cishort, p); - - if (!(cishort == IPCP_VJ_COMP || - (cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting COMPRESSTYPE %d\n", cishort)); - orc = CONFREJ; - break; - } - - ho->neg_vj = 1; - ho->vj_protocol = cishort; - if (cilen == CILEN_VJ) { - GETCHAR(maxslotindex, p); - if (maxslotindex > ao->maxslotindex) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ max slot %d\n", maxslotindex)); - orc = CONFNAK; - if (!reject_if_disagree){ - DECPTR(1, p); - PUTCHAR(ao->maxslotindex, p); - } - } - GETCHAR(cflag, p); - if (cflag && !ao->cflag) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Naking VJ cflag %d\n", cflag)); - orc = CONFNAK; - if (!reject_if_disagree){ - DECPTR(1, p); - PUTCHAR(wo->cflag, p); - } - } - ho->maxslotindex = maxslotindex; - ho->cflag = cflag; - } else { - ho->old_vj = 1; - ho->maxslotindex = MAX_SLOTS - 1; - ho->cflag = 1; - } - IPCPDEBUG((LOG_INFO, - "ipcp_reqci: received COMPRESSTYPE p=%d old=%d maxslot=%d cflag=%d\n", - ho->vj_protocol, ho->old_vj, ho->maxslotindex, ho->cflag)); - break; - - default: - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting unknown CI type %d\n", citype)); - orc = CONFREJ; - break; - } - -endswitch: - if (orc == CONFACK && /* Good CI */ - rc != CONFACK) /* but prior CI wasnt? */ - continue; /* Don't send this one */ - - if (orc == CONFNAK) { /* Nak this CI? */ - if (reject_if_disagree) { /* Getting fed up with sending NAKs? */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Rejecting too many naks\n")); - orc = CONFREJ; /* Get tough if so */ - } else { - if (rc == CONFREJ) /* Rejecting prior CI? */ - continue; /* Don't send this one */ - if (rc == CONFACK) { /* Ack'd all prior CIs? */ - rc = CONFNAK; /* Not anymore... */ - ucp = inp; /* Backup */ - } - } - } - - if (orc == CONFREJ && /* Reject this CI */ - rc != CONFREJ) { /* but no prior ones? */ - rc = CONFREJ; - ucp = inp; /* Backup */ - } - - /* Need to move CI? */ - if (ucp != cip) - BCOPY(cip, ucp, cilen); /* Move it */ - - /* Update output pointer */ - INCPTR(cilen, ucp); - } - - /* - * If we aren't rejecting this packet, and we want to negotiate - * their address, and they didn't send their address, then we - * send a NAK with a CI_ADDR option appended. We assume the - * input buffer is long enough that we can append the extra - * option safely. - */ - if (rc != CONFREJ && !ho->neg_addr && - wo->req_addr && !reject_if_disagree) { - IPCPDEBUG((LOG_INFO, "ipcp_reqci: Requesting peer address\n")); - if (rc == CONFACK) { - rc = CONFNAK; - ucp = inp; /* reset pointer */ - wo->req_addr = 0; /* don't ask again */ - } - PUTCHAR(CI_ADDR, ucp); - PUTCHAR(CILEN_ADDR, ucp); - tl = ntohl(wo->hisaddr); - PUTLONG(tl, ucp); - } - - *len = (int)(ucp - inp); /* Compute output length */ - IPCPDEBUG((LOG_INFO, "ipcp_reqci: returning Configure-%s\n", CODENAME(rc))); - return (rc); /* Return final code */ -} - - -#if 0 -/* - * ip_check_options - check that any IP-related options are OK, - * and assign appropriate defaults. - */ -static void ip_check_options(u_long localAddr) -{ - ipcp_options *wo = &ipcp_wantoptions[0]; - - /* - * Load our default IP address but allow the remote host to give us - * a new address. - */ - if (wo->ouraddr == 0 && !ppp_settings.disable_defaultip) { - wo->accept_local = 1; /* don't insist on this default value */ - wo->ouraddr = htonl(localAddr); - } -} -#endif - - -/* - * ipcp_up - IPCP has come UP. - * - * Configure the IP network interface appropriately and bring it up. - */ -static void ipcp_up(fsm *f) -{ - u32_t mask; - ipcp_options *ho = &ipcp_hisoptions[f->unit]; - ipcp_options *go = &ipcp_gotoptions[f->unit]; - ipcp_options *wo = &ipcp_wantoptions[f->unit]; - - np_up(f->unit, PPP_IP); - IPCPDEBUG((LOG_INFO, "ipcp: up\n")); - - /* - * We must have a non-zero IP address for both ends of the link. - */ - if (!ho->neg_addr) - ho->hisaddr = wo->hisaddr; - - if (ho->hisaddr == 0) { - IPCPDEBUG((LOG_ERR, "Could not determine remote IP address\n")); - ipcp_close(f->unit, "Could not determine remote IP address"); - return; - } - if (go->ouraddr == 0) { - IPCPDEBUG((LOG_ERR, "Could not determine local IP address\n")); - ipcp_close(f->unit, "Could not determine local IP address"); - return; - } - - if (ppp_settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) { - /*pppGotDNSAddrs(go->dnsaddr[0], go->dnsaddr[1]);*/ - } - - /* - * Check that the peer is allowed to use the IP address it wants. - */ - if (!auth_ip_addr(f->unit, ho->hisaddr)) { - IPCPDEBUG((LOG_ERR, "Peer is not authorized to use remote address %s\n", - inet_ntoa(ho->hisaddr))); - ipcp_close(f->unit, "Unauthorized remote IP address"); - return; - } - - /* set tcp compression */ - sifvjcomp(f->unit, ho->neg_vj, ho->cflag, ho->maxslotindex); - - /* - * Set IP addresses and (if specified) netmask. - */ - mask = GetMask(go->ouraddr); - - if (!sifaddr(f->unit, go->ouraddr, ho->hisaddr, mask, go->dnsaddr[0], go->dnsaddr[1])) { - IPCPDEBUG((LOG_WARNING, "sifaddr failed\n")); - ipcp_close(f->unit, "Interface configuration failed"); - return; - } - - /* bring the interface up for IP */ - if (!sifup(f->unit)) { - IPCPDEBUG((LOG_WARNING, "sifup failed\n")); - ipcp_close(f->unit, "Interface configuration failed"); - return; - } - - sifnpmode(f->unit, PPP_IP, NPMODE_PASS); - - /* assign a default route through the interface if required */ - if (ipcp_wantoptions[f->unit].default_route) - if (sifdefaultroute(f->unit, go->ouraddr, ho->hisaddr)) - default_route_set[f->unit] = 1; - - IPCPDEBUG((LOG_NOTICE, "local IP address %s\n", inet_ntoa(go->ouraddr))); - IPCPDEBUG((LOG_NOTICE, "remote IP address %s\n", inet_ntoa(ho->hisaddr))); - if (go->dnsaddr[0]) { - IPCPDEBUG((LOG_NOTICE, "primary DNS address %s\n", inet_ntoa(go->dnsaddr[0]))); - } - if (go->dnsaddr[1]) { - IPCPDEBUG((LOG_NOTICE, "secondary DNS address %s\n", inet_ntoa(go->dnsaddr[1]))); - } -} - - -/* - * ipcp_down - IPCP has gone DOWN. - * - * Take the IP network interface down, clear its addresses - * and delete routes through it. - */ -static void ipcp_down(fsm *f) -{ - IPCPDEBUG((LOG_INFO, "ipcp: down\n")); - np_down(f->unit, PPP_IP); - sifvjcomp(f->unit, 0, 0, 0); - - sifdown(f->unit); - ipcp_clear_addrs(f->unit); -} - - -/* - * ipcp_clear_addrs() - clear the interface addresses, routes, etc. - */ -static void ipcp_clear_addrs(int unit) -{ - u32_t ouraddr, hisaddr; - - ouraddr = ipcp_gotoptions[unit].ouraddr; - hisaddr = ipcp_hisoptions[unit].hisaddr; - if (default_route_set[unit]) { - cifdefaultroute(unit, ouraddr, hisaddr); - default_route_set[unit] = 0; - } - cifaddr(unit, ouraddr, hisaddr); -} - - -/* - * ipcp_finished - possibly shut down the lower layers. - */ -static void ipcp_finished(fsm *f) -{ - np_finished(f->unit, PPP_IP); -} - -#if 0 -static int ipcp_printpkt( - u_char *p, - int plen, - void (*printer) (void *, char *, ...), - void *arg -) -{ - (void)p; - (void)plen; - (void)printer; - (void)arg; - return 0; -} - -/* - * ip_active_pkt - see if this IP packet is worth bringing the link up for. - * We don't bring the link up for IP fragments or for TCP FIN packets - * with no data. - */ -#define IP_HDRLEN 20 /* bytes */ -#define IP_OFFMASK 0x1fff -#define IPPROTO_TCP 6 -#define TCP_HDRLEN 20 -#define TH_FIN 0x01 - -/* - * We use these macros because the IP header may be at an odd address, - * and some compilers might use word loads to get th_off or ip_hl. - */ - -#define net_short(x) (((x)[0] << 8) + (x)[1]) -#define get_iphl(x) (((unsigned char *)(x))[0] & 0xF) -#define get_ipoff(x) net_short((unsigned char *)(x) + 6) -#define get_ipproto(x) (((unsigned char *)(x))[9]) -#define get_tcpoff(x) (((unsigned char *)(x))[12] >> 4) -#define get_tcpflags(x) (((unsigned char *)(x))[13]) - -static int ip_active_pkt(u_char *pkt, int len) -{ - u_char *tcp; - int hlen; - - len -= PPP_HDRLEN; - pkt += PPP_HDRLEN; - if (len < IP_HDRLEN) - return 0; - if ((get_ipoff(pkt) & IP_OFFMASK) != 0) - return 0; - if (get_ipproto(pkt) != IPPROTO_TCP) - return 1; - hlen = get_iphl(pkt) * 4; - if (len < hlen + TCP_HDRLEN) - return 0; - tcp = pkt + hlen; - if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4) - return 0; - return 1; -} -#endif - -#endif /* PPP_SUPPORT */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/ipcp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/ipcp.h deleted file mode 100644 index 040a7cf4f..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/ipcp.h +++ /dev/null @@ -1,126 +0,0 @@ -/***************************************************************************** -* ipcp.h - PPP IP NCP: Internet Protocol Network Control Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD codes. -*****************************************************************************/ -/* - * ipcp.h - IP Control Protocol definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id$ - */ - -#ifndef IPCP_H -#define IPCP_H - -/************************* -*** PUBLIC DEFINITIONS *** -*************************/ -/* - * Options. - */ -#define CI_ADDRS 1 /* IP Addresses */ -#define CI_COMPRESSTYPE 2 /* Compression Type */ -#define CI_ADDR 3 - -#define CI_MS_WINS1 128 /* Primary WINS value */ -#define CI_MS_DNS1 129 /* Primary DNS value */ -#define CI_MS_WINS2 130 /* Secondary WINS value */ -#define CI_MS_DNS2 131 /* Secondary DNS value */ - -#define IPCP_VJMODE_OLD 1 /* "old" mode (option # = 0x0037) */ -#define IPCP_VJMODE_RFC1172 2 /* "old-rfc"mode (option # = 0x002d) */ -#define IPCP_VJMODE_RFC1332 3 /* "new-rfc"mode (option # = 0x002d, */ - /* maxslot and slot number compression) */ - -#define IPCP_VJ_COMP 0x002d /* current value for VJ compression option*/ -#define IPCP_VJ_COMP_OLD 0x0037 /* "old" (i.e, broken) value for VJ */ - /* compression option*/ - - -/************************ -*** PUBLIC DATA TYPES *** -************************/ - -typedef struct ipcp_options { - u_int neg_addr : 1; /* Negotiate IP Address? */ - u_int old_addrs : 1; /* Use old (IP-Addresses) option? */ - u_int req_addr : 1; /* Ask peer to send IP address? */ - u_int default_route : 1; /* Assign default route through interface? */ - u_int proxy_arp : 1; /* Make proxy ARP entry for peer? */ - u_int neg_vj : 1; /* Van Jacobson Compression? */ - u_int old_vj : 1; /* use old (short) form of VJ option? */ - u_int accept_local : 1; /* accept peer's value for ouraddr */ - u_int accept_remote : 1; /* accept peer's value for hisaddr */ - u_int req_dns1 : 1; /* Ask peer to send primary DNS address? */ - u_int req_dns2 : 1; /* Ask peer to send secondary DNS address? */ - u_short vj_protocol; /* protocol value to use in VJ option */ - u_char maxslotindex; /* VJ slots - 1. */ - u_char cflag; /* VJ slot compression flag. */ - u32_t ouraddr, hisaddr; /* Addresses in NETWORK BYTE ORDER */ - u32_t dnsaddr[2]; /* Primary and secondary MS DNS entries */ - u32_t winsaddr[2]; /* Primary and secondary MS WINS entries */ -} ipcp_options; - - -/***************************** -*** PUBLIC DATA STRUCTURES *** -*****************************/ - -extern fsm ipcp_fsm[]; -extern ipcp_options ipcp_wantoptions[]; -extern ipcp_options ipcp_gotoptions[]; -extern ipcp_options ipcp_allowoptions[]; -extern ipcp_options ipcp_hisoptions[]; - -extern struct protent ipcp_protent; - - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ - - -#endif /* IPCP_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/lcp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/lcp.c deleted file mode 100644 index 709866973..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/lcp.c +++ /dev/null @@ -1,1992 +0,0 @@ -/***************************************************************************** -* lcp.c - Network Link Control Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-01 Guy Lancaster , Global Election Systems Inc. -* Original. -*****************************************************************************/ - -/* - * lcp.c - PPP Link Control Protocol. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include -#include - -#include "ppp.h" -#if PPP_SUPPORT > 0 -#include "fsm.h" -#include "chap.h" -#include "magic.h" -#include "auth.h" -#include "lcp.h" -#include "pppdebug.h" - - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ -/* - * Length of each type of configuration option (in octets) - */ -#define CILEN_VOID 2 -#define CILEN_CHAR 3 -#define CILEN_SHORT 4 /* CILEN_VOID + sizeof(short) */ -#define CILEN_CHAP 5 /* CILEN_VOID + sizeof(short) + 1 */ -#define CILEN_LONG 6 /* CILEN_VOID + sizeof(long) */ -#define CILEN_LQR 8 /* CILEN_VOID + sizeof(short) + sizeof(long) */ -#define CILEN_CBCP 3 - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -/* - * Callbacks for fsm code. (CI = Configuration Information) - */ -static void lcp_resetci (fsm*); /* Reset our CI */ -static int lcp_cilen (fsm*); /* Return length of our CI */ -static void lcp_addci (fsm*, u_char*, int*); /* Add our CI to pkt */ -static int lcp_ackci (fsm*, u_char*, int);/* Peer ack'd our CI */ -static int lcp_nakci (fsm*, u_char*, int);/* Peer nak'd our CI */ -static int lcp_rejci (fsm*, u_char*, int);/* Peer rej'd our CI */ -static int lcp_reqci (fsm*, u_char*, int*, int); /* Rcv peer CI */ -static void lcp_up (fsm*); /* We're UP */ -static void lcp_down (fsm*); /* We're DOWN */ -static void lcp_starting (fsm*); /* We need lower layer up */ -static void lcp_finished (fsm*); /* We need lower layer down */ -static int lcp_extcode (fsm*, int, u_char, u_char*, int); - -static void lcp_rprotrej (fsm*, u_char*, int); - -/* - * routines to send LCP echos to peer - */ -static void lcp_echo_lowerup (int); -static void lcp_echo_lowerdown (int); -static void LcpEchoTimeout (void*); -static void lcp_received_echo_reply (fsm*, int, u_char*, int); -static void LcpSendEchoRequest (fsm*); -static void LcpLinkFailure (fsm*); -static void LcpEchoCheck (fsm*); - -/* - * Protocol entry points. - * Some of these are called directly. - */ -static void lcp_input (int, u_char *, int); -static void lcp_protrej (int); - -#define CODENAME(x) ((x) == CONFACK ? "ACK" : \ - (x) == CONFNAK ? "NAK" : "REJ") - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ -/* global vars */ -LinkPhase lcp_phase[NUM_PPP]; /* Phase of link session (RFC 1661) */ -lcp_options lcp_wantoptions[NUM_PPP]; /* Options that we want to request */ -lcp_options lcp_gotoptions[NUM_PPP]; /* Options that peer ack'd */ -lcp_options lcp_allowoptions[NUM_PPP]; /* Options we allow peer to request */ -lcp_options lcp_hisoptions[NUM_PPP]; /* Options that we ack'd */ -ext_accm xmit_accm[NUM_PPP]; /* extended transmit ACCM */ - - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -static fsm lcp_fsm[NUM_PPP]; /* LCP fsm structure (global)*/ -static u_int lcp_echo_interval = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */ -static u_int lcp_echo_fails = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */ -static u32_t lcp_echos_pending = 0; /* Number of outstanding echo msgs */ -static u32_t lcp_echo_number = 0; /* ID number of next echo frame */ -static u32_t lcp_echo_timer_running = 0; /* TRUE if a timer is running */ - -static u_char nak_buffer[PPP_MRU]; /* where we construct a nak packet */ - -static fsm_callbacks lcp_callbacks = { /* LCP callback routines */ - lcp_resetci, /* Reset our Configuration Information */ - lcp_cilen, /* Length of our Configuration Information */ - lcp_addci, /* Add our Configuration Information */ - lcp_ackci, /* ACK our Configuration Information */ - lcp_nakci, /* NAK our Configuration Information */ - lcp_rejci, /* Reject our Configuration Information */ - lcp_reqci, /* Request peer's Configuration Information */ - lcp_up, /* Called when fsm reaches OPENED state */ - lcp_down, /* Called when fsm leaves OPENED state */ - lcp_starting, /* Called when we want the lower layer up */ - lcp_finished, /* Called when we want the lower layer down */ - NULL, /* Called when Protocol-Reject received */ - NULL, /* Retransmission is necessary */ - lcp_extcode, /* Called to handle LCP-specific codes */ - "LCP" /* String name of protocol */ -}; - -struct protent lcp_protent = { - PPP_LCP, - lcp_init, - lcp_input, - lcp_protrej, - lcp_lowerup, - lcp_lowerdown, - lcp_open, - lcp_close, -#if 0 - lcp_printpkt, - NULL, -#endif - 1, - "LCP", -#if 0 - NULL, - NULL, - NULL -#endif -}; - -int lcp_loopbackfail = DEFLOOPBACKFAIL; - - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * lcp_init - Initialize LCP. - */ -void lcp_init(int unit) -{ - fsm *f = &lcp_fsm[unit]; - lcp_options *wo = &lcp_wantoptions[unit]; - lcp_options *ao = &lcp_allowoptions[unit]; - - f->unit = unit; - f->protocol = PPP_LCP; - f->callbacks = &lcp_callbacks; - - fsm_init(f); - - wo->passive = 0; - wo->silent = 0; - wo->restart = 0; /* Set to 1 in kernels or multi-line - * implementations */ - wo->neg_mru = 1; - wo->mru = PPP_DEFMRU; - wo->neg_asyncmap = 1; - wo->asyncmap = 0x00000000l; /* Assume don't need to escape any ctl chars. */ - wo->neg_chap = 0; /* Set to 1 on server */ - wo->neg_upap = 0; /* Set to 1 on server */ - wo->chap_mdtype = CHAP_DIGEST_MD5; - wo->neg_magicnumber = 1; - wo->neg_pcompression = 1; - wo->neg_accompression = 1; - wo->neg_lqr = 0; /* no LQR implementation yet */ - wo->neg_cbcp = 0; - - ao->neg_mru = 1; - ao->mru = PPP_MAXMRU; - ao->neg_asyncmap = 1; - ao->asyncmap = 0x00000000l; /* Assume don't need to escape any ctl chars. */ - ao->neg_chap = (CHAP_SUPPORT != 0); - ao->chap_mdtype = CHAP_DIGEST_MD5; - ao->neg_upap = (PAP_SUPPORT != 0); - ao->neg_magicnumber = 1; - ao->neg_pcompression = 1; - ao->neg_accompression = 1; - ao->neg_lqr = 0; /* no LQR implementation yet */ - ao->neg_cbcp = (CBCP_SUPPORT != 0); - - /* - * Set transmit escape for the flag and escape characters plus anything - * set for the allowable options. - */ - memset(xmit_accm[unit], 0, sizeof(xmit_accm[0])); - xmit_accm[unit][15] = 0x60; - xmit_accm[unit][0] = (u_char)(ao->asyncmap & 0xFF); - xmit_accm[unit][1] = (u_char)((ao->asyncmap >> 8) & 0xFF); - xmit_accm[unit][2] = (u_char)((ao->asyncmap >> 16) & 0xFF); - xmit_accm[unit][3] = (u_char)((ao->asyncmap >> 24) & 0xFF); - LCPDEBUG((LOG_INFO, "lcp_init: xmit_accm=%X %X %X %X\n", - xmit_accm[unit][0], - xmit_accm[unit][1], - xmit_accm[unit][2], - xmit_accm[unit][3])); - - lcp_phase[unit] = PHASE_INITIALIZE; -} - - -/* - * lcp_open - LCP is allowed to come up. - */ -void lcp_open(int unit) -{ - fsm *f = &lcp_fsm[unit]; - lcp_options *wo = &lcp_wantoptions[unit]; - - f->flags = 0; - if (wo->passive) - f->flags |= OPT_PASSIVE; - if (wo->silent) - f->flags |= OPT_SILENT; - fsm_open(f); - - lcp_phase[unit] = PHASE_ESTABLISH; -} - - -/* - * lcp_close - Take LCP down. - */ -void lcp_close(int unit, char *reason) -{ - fsm *f = &lcp_fsm[unit]; - - if (lcp_phase[unit] != PHASE_DEAD) - lcp_phase[unit] = PHASE_TERMINATE; - if (f->state == STOPPED && f->flags & (OPT_PASSIVE|OPT_SILENT)) { - /* - * This action is not strictly according to the FSM in RFC1548, - * but it does mean that the program terminates if you do an - * lcp_close() in passive/silent mode when a connection hasn't - * been established. - */ - f->state = CLOSED; - lcp_finished(f); - } - else - fsm_close(&lcp_fsm[unit], reason); -} - - -/* - * lcp_lowerup - The lower layer is up. - */ -void lcp_lowerup(int unit) -{ - lcp_options *wo = &lcp_wantoptions[unit]; - - /* - * Don't use A/C or protocol compression on transmission, - * but accept A/C and protocol compressed packets - * if we are going to ask for A/C and protocol compression. - */ - ppp_set_xaccm(unit, &xmit_accm[unit]); - ppp_send_config(unit, PPP_MRU, 0xffffffffl, 0, 0); - ppp_recv_config(unit, PPP_MRU, 0x00000000l, - wo->neg_pcompression, wo->neg_accompression); - peer_mru[unit] = PPP_MRU; - lcp_allowoptions[unit].asyncmap - = (u_long)xmit_accm[unit][0] - | ((u_long)xmit_accm[unit][1] << 8) - | ((u_long)xmit_accm[unit][2] << 16) - | ((u_long)xmit_accm[unit][3] << 24); - LCPDEBUG((LOG_INFO, "lcp_lowerup: asyncmap=%X %X %X %X\n", - xmit_accm[unit][3], - xmit_accm[unit][2], - xmit_accm[unit][1], - xmit_accm[unit][0])); - - fsm_lowerup(&lcp_fsm[unit]); -} - - -/* - * lcp_lowerdown - The lower layer is down. - */ -void lcp_lowerdown(int unit) -{ - fsm_lowerdown(&lcp_fsm[unit]); -} - -/* - * lcp_sprotrej - Send a Protocol-Reject for some protocol. - */ -void lcp_sprotrej(int unit, u_char *p, int len) -{ - /* - * Send back the protocol and the information field of the - * rejected packet. We only get here if LCP is in the OPENED state. - */ - - fsm_sdata(&lcp_fsm[unit], PROTREJ, ++lcp_fsm[unit].id, - p, len); -} - - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ -/* - * lcp_input - Input LCP packet. - */ -static void lcp_input(int unit, u_char *p, int len) -{ - fsm *f = &lcp_fsm[unit]; - - fsm_input(f, p, len); -} - - -/* - * lcp_extcode - Handle a LCP-specific code. - */ -static int lcp_extcode(fsm *f, int code, u_char id, u_char *inp, int len) -{ - u_char *magp; - - switch( code ){ - case PROTREJ: - lcp_rprotrej(f, inp, len); - break; - - case ECHOREQ: - if (f->state != OPENED) - break; - LCPDEBUG((LOG_INFO, "lcp: Echo-Request, Rcvd id %d\n", id)); - magp = inp; - PUTLONG(lcp_gotoptions[f->unit].magicnumber, magp); - fsm_sdata(f, ECHOREP, id, inp, len); - break; - - case ECHOREP: - lcp_received_echo_reply(f, id, inp, len); - break; - - case DISCREQ: - break; - - default: - return 0; - } - return 1; -} - - -/* - * lcp_rprotrej - Receive an Protocol-Reject. - * - * Figure out which protocol is rejected and inform it. - */ -static void lcp_rprotrej(fsm *f, u_char *inp, int len) -{ - int i; - struct protent *protp; - u_short prot; - - if (len < sizeof (u_short)) { - LCPDEBUG((LOG_INFO, - "lcp_rprotrej: Rcvd short Protocol-Reject packet!\n")); - return; - } - - GETSHORT(prot, inp); - - LCPDEBUG((LOG_INFO, - "lcp_rprotrej: Rcvd Protocol-Reject packet for %x!\n", - prot)); - - /* - * Protocol-Reject packets received in any state other than the LCP - * OPENED state SHOULD be silently discarded. - */ - if( f->state != OPENED ){ - LCPDEBUG((LOG_INFO, "Protocol-Reject discarded: LCP in state %d\n", - f->state)); - return; - } - - /* - * Upcall the proper Protocol-Reject routine. - */ - for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) - if (protp->protocol == prot && protp->enabled_flag) { - (*protp->protrej)(f->unit); - return; - } - - LCPDEBUG((LOG_WARNING, "Protocol-Reject for unsupported protocol 0x%x\n", - prot)); -} - - -/* - * lcp_protrej - A Protocol-Reject was received. - */ -static void lcp_protrej(int unit) -{ - (void)unit; - /* - * Can't reject LCP! - */ - LCPDEBUG((LOG_WARNING, - "lcp_protrej: Received Protocol-Reject for LCP!\n")); - fsm_protreject(&lcp_fsm[unit]); -} - - -/* - * lcp_resetci - Reset our CI. - */ -static void lcp_resetci(fsm *f) -{ - lcp_wantoptions[f->unit].magicnumber = magic(); - lcp_wantoptions[f->unit].numloops = 0; - lcp_gotoptions[f->unit] = lcp_wantoptions[f->unit]; - peer_mru[f->unit] = PPP_MRU; - auth_reset(f->unit); -} - - -/* - * lcp_cilen - Return length of our CI. - */ -static int lcp_cilen(fsm *f) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - -#define LENCIVOID(neg) ((neg) ? CILEN_VOID : 0) -#define LENCICHAP(neg) ((neg) ? CILEN_CHAP : 0) -#define LENCISHORT(neg) ((neg) ? CILEN_SHORT : 0) -#define LENCILONG(neg) ((neg) ? CILEN_LONG : 0) -#define LENCILQR(neg) ((neg) ? CILEN_LQR: 0) -#define LENCICBCP(neg) ((neg) ? CILEN_CBCP: 0) - /* - * NB: we only ask for one of CHAP and UPAP, even if we will - * accept either. - */ - return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) + - LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) + - LENCICHAP(go->neg_chap) + - LENCISHORT(!go->neg_chap && go->neg_upap) + - LENCILQR(go->neg_lqr) + - LENCICBCP(go->neg_cbcp) + - LENCILONG(go->neg_magicnumber) + - LENCIVOID(go->neg_pcompression) + - LENCIVOID(go->neg_accompression)); -} - - -/* - * lcp_addci - Add our desired CIs to a packet. - */ -static void lcp_addci(fsm *f, u_char *ucp, int *lenp) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - u_char *start_ucp = ucp; - -#define ADDCIVOID(opt, neg) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: opt=%d\n", opt)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_VOID, ucp); \ - } -#define ADDCISHORT(opt, neg, val) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: INT opt=%d %X\n", opt, val)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_SHORT, ucp); \ - PUTSHORT(val, ucp); \ - } -#define ADDCICHAP(opt, neg, val, digest) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: CHAP opt=%d %X\n", opt, val)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_CHAP, ucp); \ - PUTSHORT(val, ucp); \ - PUTCHAR(digest, ucp); \ - } -#define ADDCILONG(opt, neg, val) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: L opt=%d %lX\n", opt, val)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_LONG, ucp); \ - PUTLONG(val, ucp); \ - } -#define ADDCILQR(opt, neg, val) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: LQR opt=%d %lX\n", opt, val)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_LQR, ucp); \ - PUTSHORT(PPP_LQR, ucp); \ - PUTLONG(val, ucp); \ - } -#define ADDCICHAR(opt, neg, val) \ - if (neg) { \ - LCPDEBUG((LOG_INFO, "lcp_addci: CHAR opt=%d %X '%z'\n", opt, val, val)); \ - PUTCHAR(opt, ucp); \ - PUTCHAR(CILEN_CHAR, ucp); \ - PUTCHAR(val, ucp); \ - } - - ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru); - ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, - go->asyncmap); - ADDCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype); - ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP); - ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period); - ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT); - ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber); - ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression); - ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression); - - if (ucp - start_ucp != *lenp) { - /* this should never happen, because peer_mtu should be 1500 */ - LCPDEBUG((LOG_ERR, "Bug in lcp_addci: wrong length\n")); - } -} - - -/* - * lcp_ackci - Ack our CIs. - * This should not modify any state if the Ack is bad. - * - * Returns: - * 0 - Ack was bad. - * 1 - Ack was good. - */ -static int lcp_ackci(fsm *f, u_char *p, int len) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - u_char cilen, citype, cichar; - u_short cishort; - u32_t cilong; - - /* - * CIs must be in exactly the same order that we sent. - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ -#define ACKCIVOID(opt, neg) \ - if (neg) { \ - if ((len -= CILEN_VOID) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_VOID || \ - citype != opt) \ - goto bad; \ - } -#define ACKCISHORT(opt, neg, val) \ - if (neg) { \ - if ((len -= CILEN_SHORT) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_SHORT || \ - citype != opt) \ - goto bad; \ - GETSHORT(cishort, p); \ - if (cishort != val) \ - goto bad; \ - } -#define ACKCICHAR(opt, neg, val) \ - if (neg) { \ - if ((len -= CILEN_CHAR) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_CHAR || \ - citype != opt) \ - goto bad; \ - GETCHAR(cichar, p); \ - if (cichar != val) \ - goto bad; \ - } -#define ACKCICHAP(opt, neg, val, digest) \ - if (neg) { \ - if ((len -= CILEN_CHAP) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_CHAP || \ - citype != opt) \ - goto bad; \ - GETSHORT(cishort, p); \ - if (cishort != val) \ - goto bad; \ - GETCHAR(cichar, p); \ - if (cichar != digest) \ - goto bad; \ - } -#define ACKCILONG(opt, neg, val) \ - if (neg) { \ - if ((len -= CILEN_LONG) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_LONG || \ - citype != opt) \ - goto bad; \ - GETLONG(cilong, p); \ - if (cilong != val) \ - goto bad; \ - } -#define ACKCILQR(opt, neg, val) \ - if (neg) { \ - if ((len -= CILEN_LQR) < 0) \ - goto bad; \ - GETCHAR(citype, p); \ - GETCHAR(cilen, p); \ - if (cilen != CILEN_LQR || \ - citype != opt) \ - goto bad; \ - GETSHORT(cishort, p); \ - if (cishort != PPP_LQR) \ - goto bad; \ - GETLONG(cilong, p); \ - if (cilong != val) \ - goto bad; \ - } - - ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru); - ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl, - go->asyncmap); - ACKCICHAP(CI_AUTHTYPE, go->neg_chap, PPP_CHAP, go->chap_mdtype); - ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP); - ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period); - ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT); - ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber); - ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression); - ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression); - - /* - * If there are any remaining CIs, then this packet is bad. - */ - if (len != 0) - goto bad; - LCPDEBUG((LOG_INFO, "lcp_acki: Ack\n")); - return (1); -bad: - LCPDEBUG((LOG_WARNING, "lcp_acki: received bad Ack!\n")); - return (0); -} - - -/* - * lcp_nakci - Peer has sent a NAK for some of our CIs. - * This should not modify any state if the Nak is bad - * or if LCP is in the OPENED state. - * - * Returns: - * 0 - Nak was bad. - * 1 - Nak was good. - */ -static int lcp_nakci(fsm *f, u_char *p, int len) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - lcp_options *wo = &lcp_wantoptions[f->unit]; - u_char citype, cichar, *next; - u_short cishort; - u32_t cilong; - lcp_options no; /* options we've seen Naks for */ - lcp_options try; /* options to request next time */ - int looped_back = 0; - int cilen; - - BZERO(&no, sizeof(no)); - try = *go; - - /* - * Any Nak'd CIs must be in exactly the same order that we sent. - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ -#define NAKCIVOID(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_VOID && \ - p[1] == CILEN_VOID && \ - p[0] == opt) { \ - len -= CILEN_VOID; \ - INCPTR(CILEN_VOID, p); \ - no.neg = 1; \ - code \ - } -#define NAKCICHAP(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_CHAP && \ - p[1] == CILEN_CHAP && \ - p[0] == opt) { \ - len -= CILEN_CHAP; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - GETCHAR(cichar, p); \ - no.neg = 1; \ - code \ - } -#define NAKCICHAR(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_CHAR && \ - p[1] == CILEN_CHAR && \ - p[0] == opt) { \ - len -= CILEN_CHAR; \ - INCPTR(2, p); \ - GETCHAR(cichar, p); \ - no.neg = 1; \ - code \ - } -#define NAKCISHORT(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_SHORT && \ - p[1] == CILEN_SHORT && \ - p[0] == opt) { \ - len -= CILEN_SHORT; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - no.neg = 1; \ - code \ - } -#define NAKCILONG(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_LONG && \ - p[1] == CILEN_LONG && \ - p[0] == opt) { \ - len -= CILEN_LONG; \ - INCPTR(2, p); \ - GETLONG(cilong, p); \ - no.neg = 1; \ - code \ - } -#define NAKCILQR(opt, neg, code) \ - if (go->neg && \ - len >= CILEN_LQR && \ - p[1] == CILEN_LQR && \ - p[0] == opt) { \ - len -= CILEN_LQR; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - GETLONG(cilong, p); \ - no.neg = 1; \ - code \ - } - - /* - * We don't care if they want to send us smaller packets than - * we want. Therefore, accept any MRU less than what we asked for, - * but then ignore the new value when setting the MRU in the kernel. - * If they send us a bigger MRU than what we asked, accept it, up to - * the limit of the default MRU we'd get if we didn't negotiate. - */ - if (go->neg_mru && go->mru != PPP_DEFMRU) { - NAKCISHORT(CI_MRU, neg_mru, - if (cishort <= wo->mru || cishort < PPP_DEFMRU) - try.mru = cishort; - ); - } - - /* - * Add any characters they want to our (receive-side) asyncmap. - */ - if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) { - NAKCILONG(CI_ASYNCMAP, neg_asyncmap, - try.asyncmap = go->asyncmap | cilong; - ); - } - - /* - * If they've nak'd our authentication-protocol, check whether - * they are proposing a different protocol, or a different - * hash algorithm for CHAP. - */ - if ((go->neg_chap || go->neg_upap) - && len >= CILEN_SHORT - && p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) { - cilen = p[1]; - len -= cilen; - no.neg_chap = go->neg_chap; - no.neg_upap = go->neg_upap; - INCPTR(2, p); - GETSHORT(cishort, p); - if (cishort == PPP_PAP && cilen == CILEN_SHORT) { - /* - * If we were asking for CHAP, they obviously don't want to do it. - * If we weren't asking for CHAP, then we were asking for PAP, - * in which case this Nak is bad. - */ - if (!go->neg_chap) - goto bad; - try.neg_chap = 0; - - } else if (cishort == PPP_CHAP && cilen == CILEN_CHAP) { - GETCHAR(cichar, p); - if (go->neg_chap) { - /* - * We were asking for CHAP/MD5; they must want a different - * algorithm. If they can't do MD5, we'll have to stop - * asking for CHAP. - */ - if (cichar != go->chap_mdtype) - try.neg_chap = 0; - } else { - /* - * Stop asking for PAP if we were asking for it. - */ - try.neg_upap = 0; - } - - } else { - /* - * We don't recognize what they're suggesting. - * Stop asking for what we were asking for. - */ - if (go->neg_chap) - try.neg_chap = 0; - else - try.neg_upap = 0; - p += cilen - CILEN_SHORT; - } - } - - /* - * If they can't cope with our link quality protocol, we'll have - * to stop asking for LQR. We haven't got any other protocol. - * If they Nak the reporting period, take their value XXX ? - */ - NAKCILQR(CI_QUALITY, neg_lqr, - if (cishort != PPP_LQR) - try.neg_lqr = 0; - else - try.lqr_period = cilong; - ); - - /* - * Only implementing CBCP...not the rest of the callback options - */ - NAKCICHAR(CI_CALLBACK, neg_cbcp, - try.neg_cbcp = 0; - ); - - /* - * Check for a looped-back line. - */ - NAKCILONG(CI_MAGICNUMBER, neg_magicnumber, - try.magicnumber = magic(); - looped_back = 1; - ); - - /* - * Peer shouldn't send Nak for protocol compression or - * address/control compression requests; they should send - * a Reject instead. If they send a Nak, treat it as a Reject. - */ - NAKCIVOID(CI_PCOMPRESSION, neg_pcompression, - try.neg_pcompression = 0; - ); - NAKCIVOID(CI_ACCOMPRESSION, neg_accompression, - try.neg_accompression = 0; - ); - - /* - * There may be remaining CIs, if the peer is requesting negotiation - * on an option that we didn't include in our request packet. - * If we see an option that we requested, or one we've already seen - * in this packet, then this packet is bad. - * If we wanted to respond by starting to negotiate on the requested - * option(s), we could, but we don't, because except for the - * authentication type and quality protocol, if we are not negotiating - * an option, it is because we were told not to. - * For the authentication type, the Nak from the peer means - * `let me authenticate myself with you' which is a bit pointless. - * For the quality protocol, the Nak means `ask me to send you quality - * reports', but if we didn't ask for them, we don't want them. - * An option we don't recognize represents the peer asking to - * negotiate some option we don't support, so ignore it. - */ - while (len > CILEN_VOID) { - GETCHAR(citype, p); - GETCHAR(cilen, p); - if (cilen < CILEN_VOID || (len -= cilen) < 0) - goto bad; - next = p + cilen - 2; - - switch (citype) { - case CI_MRU: - if ((go->neg_mru && go->mru != PPP_DEFMRU) - || no.neg_mru || cilen != CILEN_SHORT) - goto bad; - GETSHORT(cishort, p); - if (cishort < PPP_DEFMRU) - try.mru = cishort; - break; - case CI_ASYNCMAP: - if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFFl) - || no.neg_asyncmap || cilen != CILEN_LONG) - goto bad; - break; - case CI_AUTHTYPE: - if (go->neg_chap || no.neg_chap || go->neg_upap || no.neg_upap) - goto bad; - break; - case CI_MAGICNUMBER: - if (go->neg_magicnumber || no.neg_magicnumber || - cilen != CILEN_LONG) - goto bad; - break; - case CI_PCOMPRESSION: - if (go->neg_pcompression || no.neg_pcompression - || cilen != CILEN_VOID) - goto bad; - break; - case CI_ACCOMPRESSION: - if (go->neg_accompression || no.neg_accompression - || cilen != CILEN_VOID) - goto bad; - break; - case CI_QUALITY: - if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR) - goto bad; - break; - } - p = next; - } - - /* If there is still anything left, this packet is bad. */ - if (len != 0) - goto bad; - - /* - * OK, the Nak is good. Now we can update state. - */ - if (f->state != OPENED) { - if (looped_back) { - if (++try.numloops >= lcp_loopbackfail) { - LCPDEBUG((LOG_NOTICE, "Serial line is looped back.\n")); - lcp_close(f->unit, "Loopback detected"); - } - } - else - try.numloops = 0; - *go = try; - } - - return 1; - -bad: - LCPDEBUG((LOG_WARNING, "lcp_nakci: received bad Nak!\n")); - return 0; -} - - -/* - * lcp_rejci - Peer has Rejected some of our CIs. - * This should not modify any state if the Reject is bad - * or if LCP is in the OPENED state. - * - * Returns: - * 0 - Reject was bad. - * 1 - Reject was good. - */ -static int lcp_rejci(fsm *f, u_char *p, int len) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - u_char cichar; - u_short cishort; - u32_t cilong; - lcp_options try; /* options to request next time */ - - try = *go; - - /* - * Any Rejected CIs must be in exactly the same order that we sent. - * Check packet length and CI length at each step. - * If we find any deviations, then this packet is bad. - */ -#define REJCIVOID(opt, neg) \ - if (go->neg && \ - len >= CILEN_VOID && \ - p[1] == CILEN_VOID && \ - p[0] == opt) { \ - len -= CILEN_VOID; \ - INCPTR(CILEN_VOID, p); \ - try.neg = 0; \ - LCPDEBUG((LOG_INFO, "lcp_rejci: void opt %d rejected\n", opt)); \ - } -#define REJCISHORT(opt, neg, val) \ - if (go->neg && \ - len >= CILEN_SHORT && \ - p[1] == CILEN_SHORT && \ - p[0] == opt) { \ - len -= CILEN_SHORT; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - /* Check rejected value. */ \ - if (cishort != val) \ - goto bad; \ - try.neg = 0; \ - LCPDEBUG((LOG_INFO,"lcp_rejci: short opt %d rejected\n", opt)); \ - } -#define REJCICHAP(opt, neg, val, digest) \ - if (go->neg && \ - len >= CILEN_CHAP && \ - p[1] == CILEN_CHAP && \ - p[0] == opt) { \ - len -= CILEN_CHAP; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - GETCHAR(cichar, p); \ - /* Check rejected value. */ \ - if (cishort != val || cichar != digest) \ - goto bad; \ - try.neg = 0; \ - try.neg_upap = 0; \ - LCPDEBUG((LOG_INFO,"lcp_rejci: chap opt %d rejected\n", opt)); \ - } -#define REJCILONG(opt, neg, val) \ - if (go->neg && \ - len >= CILEN_LONG && \ - p[1] == CILEN_LONG && \ - p[0] == opt) { \ - len -= CILEN_LONG; \ - INCPTR(2, p); \ - GETLONG(cilong, p); \ - /* Check rejected value. */ \ - if (cilong != val) \ - goto bad; \ - try.neg = 0; \ - LCPDEBUG((LOG_INFO,"lcp_rejci: long opt %d rejected\n", opt)); \ - } -#define REJCILQR(opt, neg, val) \ - if (go->neg && \ - len >= CILEN_LQR && \ - p[1] == CILEN_LQR && \ - p[0] == opt) { \ - len -= CILEN_LQR; \ - INCPTR(2, p); \ - GETSHORT(cishort, p); \ - GETLONG(cilong, p); \ - /* Check rejected value. */ \ - if (cishort != PPP_LQR || cilong != val) \ - goto bad; \ - try.neg = 0; \ - LCPDEBUG((LOG_INFO,"lcp_rejci: LQR opt %d rejected\n", opt)); \ - } -#define REJCICBCP(opt, neg, val) \ - if (go->neg && \ - len >= CILEN_CBCP && \ - p[1] == CILEN_CBCP && \ - p[0] == opt) { \ - len -= CILEN_CBCP; \ - INCPTR(2, p); \ - GETCHAR(cichar, p); \ - /* Check rejected value. */ \ - if (cichar != val) \ - goto bad; \ - try.neg = 0; \ - LCPDEBUG((LOG_INFO,"lcp_rejci: Callback opt %d rejected\n", opt)); \ - } - - REJCISHORT(CI_MRU, neg_mru, go->mru); - REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap); - REJCICHAP(CI_AUTHTYPE, neg_chap, PPP_CHAP, go->chap_mdtype); - if (!go->neg_chap) { - REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP); - } - REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period); - REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT); - REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber); - REJCIVOID(CI_PCOMPRESSION, neg_pcompression); - REJCIVOID(CI_ACCOMPRESSION, neg_accompression); - - /* - * If there are any remaining CIs, then this packet is bad. - */ - if (len != 0) - goto bad; - /* - * Now we can update state. - */ - if (f->state != OPENED) - *go = try; - return 1; - -bad: - LCPDEBUG((LOG_WARNING, "lcp_rejci: received bad Reject!\n")); - return 0; -} - - -/* - * lcp_reqci - Check the peer's requested CIs and send appropriate response. - * - * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified - * appropriately. If reject_if_disagree is non-zero, doesn't return - * CONFNAK; returns CONFREJ if it can't return CONFACK. - */ -static int lcp_reqci(fsm *f, - u_char *inp, /* Requested CIs */ - int *lenp, /* Length of requested CIs */ - int reject_if_disagree) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - lcp_options *ho = &lcp_hisoptions[f->unit]; - lcp_options *ao = &lcp_allowoptions[f->unit]; - u_char *cip, *next; /* Pointer to current and next CIs */ - int cilen, citype, cichar; /* Parsed len, type, char value */ - u_short cishort; /* Parsed short value */ - u32_t cilong; /* Parse long value */ - int rc = CONFACK; /* Final packet return code */ - int orc; /* Individual option return code */ - u_char *p; /* Pointer to next char to parse */ - u_char *rejp; /* Pointer to next char in reject frame */ - u_char *nakp; /* Pointer to next char in Nak frame */ - int l = *lenp; /* Length left */ -#if TRACELCP > 0 - char traceBuf[80]; - int traceNdx = 0; -#endif - - /* - * Reset all his options. - */ - BZERO(ho, sizeof(*ho)); - - /* - * Process all his options. - */ - next = inp; - nakp = nak_buffer; - rejp = inp; - while (l) { - orc = CONFACK; /* Assume success */ - cip = p = next; /* Remember begining of CI */ - if (l < 2 || /* Not enough data for CI header or */ - p[1] < 2 || /* CI length too small or */ - p[1] > l) { /* CI length too big? */ - LCPDEBUG((LOG_WARNING, "lcp_reqci: bad CI length!\n")); - orc = CONFREJ; /* Reject bad CI */ - cilen = l; /* Reject till end of packet */ - l = 0; /* Don't loop again */ - citype = 0; - goto endswitch; - } - GETCHAR(citype, p); /* Parse CI type */ - GETCHAR(cilen, p); /* Parse CI length */ - l -= cilen; /* Adjust remaining length */ - next += cilen; /* Step to next CI */ - - switch (citype) { /* Check CI type */ - case CI_MRU: - if (!ao->neg_mru) { /* Allow option? */ - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - not allowed\n")); - orc = CONFREJ; /* Reject CI */ - break; - } else if (cilen != CILEN_SHORT) { /* Check CI length */ - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject MRU - bad length\n")); - orc = CONFREJ; /* Reject CI */ - break; - } - GETSHORT(cishort, p); /* Parse MRU */ - - /* - * He must be able to receive at least our minimum. - * No need to check a maximum. If he sends a large number, - * we'll just ignore it. - */ - if (cishort < PPP_MINMRU) { - LCPDEBUG((LOG_INFO, "lcp_reqci: Nak - MRU too small\n")); - orc = CONFNAK; /* Nak CI */ - PUTCHAR(CI_MRU, nakp); - PUTCHAR(CILEN_SHORT, nakp); - PUTSHORT(PPP_MINMRU, nakp); /* Give him a hint */ - break; - } - ho->neg_mru = 1; /* Remember he sent MRU */ - ho->mru = cishort; /* And remember value */ -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MRU %d", cishort); - traceNdx = strlen(traceBuf); -#endif - break; - - case CI_ASYNCMAP: - if (!ao->neg_asyncmap) { - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP not allowed\n")); - orc = CONFREJ; - break; - } else if (cilen != CILEN_LONG) { - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject ASYNCMAP bad length\n")); - orc = CONFREJ; - break; - } - GETLONG(cilong, p); - - /* - * Asyncmap must have set at least the bits - * which are set in lcp_allowoptions[unit].asyncmap. - */ - if ((ao->asyncmap & ~cilong) != 0) { - LCPDEBUG((LOG_INFO, "lcp_reqci: Nak ASYNCMAP %lX missing %lX\n", - cilong, ao->asyncmap)); - orc = CONFNAK; - PUTCHAR(CI_ASYNCMAP, nakp); - PUTCHAR(CILEN_LONG, nakp); - PUTLONG(ao->asyncmap | cilong, nakp); - break; - } - ho->neg_asyncmap = 1; - ho->asyncmap = cilong; -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ASYNCMAP=%lX", cilong); - traceNdx = strlen(traceBuf); -#endif - break; - - case CI_AUTHTYPE: - if (cilen < CILEN_SHORT) { - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE missing arg\n")); - orc = CONFREJ; - break; - } else if (!(ao->neg_upap || ao->neg_chap)) { - /* - * Reject the option if we're not willing to authenticate. - */ - LCPDEBUG((LOG_INFO, "lcp_reqci: Reject AUTHTYPE not allowed\n")); - orc = CONFREJ; - break; - } - GETSHORT(cishort, p); - - /* - * Authtype must be UPAP or CHAP. - * - * Note: if both ao->neg_upap and ao->neg_chap are set, - * and the peer sends a Configure-Request with two - * authenticate-protocol requests, one for CHAP and one - * for UPAP, then we will reject the second request. - * Whether we end up doing CHAP or UPAP depends then on - * the ordering of the CIs in the peer's Configure-Request. - */ - - if (cishort == PPP_PAP) { - if (ho->neg_chap) { /* we've already accepted CHAP */ - LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP already accepted\n")); - orc = CONFREJ; - break; - } else if (cilen != CILEN_SHORT) { - LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE PAP bad len\n")); - orc = CONFREJ; - break; - } - if (!ao->neg_upap) { /* we don't want to do PAP */ - LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE PAP not allowed\n")); - orc = CONFNAK; /* NAK it and suggest CHAP */ - PUTCHAR(CI_AUTHTYPE, nakp); - PUTCHAR(CILEN_CHAP, nakp); - PUTSHORT(PPP_CHAP, nakp); - PUTCHAR(ao->chap_mdtype, nakp); - break; - } - ho->neg_upap = 1; -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PAP (%X)", cishort); - traceNdx = strlen(traceBuf); -#endif - break; - } - if (cishort == PPP_CHAP) { - if (ho->neg_upap) { /* we've already accepted PAP */ - LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP accepted PAP\n")); - orc = CONFREJ; - break; - } else if (cilen != CILEN_CHAP) { - LCPDEBUG((LOG_WARNING, "lcp_reqci: Reject AUTHTYPE CHAP bad len\n")); - orc = CONFREJ; - break; - } - if (!ao->neg_chap) { /* we don't want to do CHAP */ - LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP not allowed\n")); - orc = CONFNAK; /* NAK it and suggest PAP */ - PUTCHAR(CI_AUTHTYPE, nakp); - PUTCHAR(CILEN_SHORT, nakp); - PUTSHORT(PPP_PAP, nakp); - break; - } - GETCHAR(cichar, p); /* get digest type*/ - if (cichar != CHAP_DIGEST_MD5 -#ifdef CHAPMS - && cichar != CHAP_MICROSOFT -#endif - ) { - LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE CHAP digest=%d\n", cichar)); - orc = CONFNAK; - PUTCHAR(CI_AUTHTYPE, nakp); - PUTCHAR(CILEN_CHAP, nakp); - PUTSHORT(PPP_CHAP, nakp); - PUTCHAR(ao->chap_mdtype, nakp); - break; - } -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CHAP %X,%d", cishort, cichar); - traceNdx = strlen(traceBuf); -#endif - ho->chap_mdtype = cichar; /* save md type */ - ho->neg_chap = 1; - break; - } - - /* - * We don't recognize the protocol they're asking for. - * Nak it with something we're willing to do. - * (At this point we know ao->neg_upap || ao->neg_chap.) - */ - orc = CONFNAK; - PUTCHAR(CI_AUTHTYPE, nakp); - if (ao->neg_chap) { - LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req CHAP\n", cishort)); - PUTCHAR(CILEN_CHAP, nakp); - PUTSHORT(PPP_CHAP, nakp); - PUTCHAR(ao->chap_mdtype, nakp); - } - else { - LCPDEBUG((LOG_WARNING, "lcp_reqci: Nak AUTHTYPE %d req PAP\n", cishort)); - PUTCHAR(CILEN_SHORT, nakp); - PUTSHORT(PPP_PAP, nakp); - } - break; - - case CI_QUALITY: - GETSHORT(cishort, p); - GETLONG(cilong, p); -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " QUALITY (%x %x)", cishort, (unsigned int) cilong); - traceNdx = strlen(traceBuf); -#endif - - if (!ao->neg_lqr || - cilen != CILEN_LQR) { - orc = CONFREJ; - break; - } - - /* - * Check the protocol and the reporting period. - * XXX When should we Nak this, and what with? - */ - if (cishort != PPP_LQR) { - orc = CONFNAK; - PUTCHAR(CI_QUALITY, nakp); - PUTCHAR(CILEN_LQR, nakp); - PUTSHORT(PPP_LQR, nakp); - PUTLONG(ao->lqr_period, nakp); - break; - } - break; - - case CI_MAGICNUMBER: - if (!(ao->neg_magicnumber || go->neg_magicnumber) || - cilen != CILEN_LONG) { - orc = CONFREJ; - break; - } - GETLONG(cilong, p); -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " MAGICNUMBER (%lX)", cilong); - traceNdx = strlen(traceBuf); -#endif - - /* - * He must have a different magic number. - */ - if (go->neg_magicnumber && - cilong == go->magicnumber) { - cilong = magic(); /* Don't put magic() inside macro! */ - orc = CONFNAK; - PUTCHAR(CI_MAGICNUMBER, nakp); - PUTCHAR(CILEN_LONG, nakp); - PUTLONG(cilong, nakp); - break; - } - ho->neg_magicnumber = 1; - ho->magicnumber = cilong; - break; - - - case CI_PCOMPRESSION: -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " PCOMPRESSION"); - traceNdx = strlen(traceBuf); -#endif - if (!ao->neg_pcompression || - cilen != CILEN_VOID) { - orc = CONFREJ; - break; - } - ho->neg_pcompression = 1; - break; - - case CI_ACCOMPRESSION: -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " ACCOMPRESSION"); - traceNdx = strlen(traceBuf); -#endif - if (!ao->neg_accompression || - cilen != CILEN_VOID) { - orc = CONFREJ; - break; - } - ho->neg_accompression = 1; - break; - - case CI_MRRU: -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_MRRU"); - traceNdx = strlen(traceBuf); -#endif - orc = CONFREJ; - break; - - case CI_SSNHF: -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_SSNHF"); - traceNdx = strlen(traceBuf); -#endif - orc = CONFREJ; - break; - - case CI_EPDISC: -#if TRACELCP > 0 - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " CI_EPDISC"); - traceNdx = strlen(traceBuf); -#endif - orc = CONFREJ; - break; - - default: -#if TRACELCP - snprintf(&traceBuf[traceNdx], sizeof(traceBuf), " unknown %d", citype); - traceNdx = strlen(traceBuf); -#endif - orc = CONFREJ; - break; - } - - endswitch: -#if TRACELCP - if (traceNdx >= 80 - 32) { - LCPDEBUG((LOG_INFO, "lcp_reqci: rcvd%s\n", traceBuf)); - traceNdx = 0; - } -#endif - if (orc == CONFACK && /* Good CI */ - rc != CONFACK) /* but prior CI wasnt? */ - continue; /* Don't send this one */ - - if (orc == CONFNAK) { /* Nak this CI? */ - if (reject_if_disagree /* Getting fed up with sending NAKs? */ - && citype != CI_MAGICNUMBER) { - orc = CONFREJ; /* Get tough if so */ - } - else { - if (rc == CONFREJ) /* Rejecting prior CI? */ - continue; /* Don't send this one */ - rc = CONFNAK; - } - } - if (orc == CONFREJ) { /* Reject this CI */ - rc = CONFREJ; - if (cip != rejp) /* Need to move rejected CI? */ - BCOPY(cip, rejp, cilen); /* Move it */ - INCPTR(cilen, rejp); /* Update output pointer */ - } - } - - /* - * If we wanted to send additional NAKs (for unsent CIs), the - * code would go here. The extra NAKs would go at *nakp. - * At present there are no cases where we want to ask the - * peer to negotiate an option. - */ - - switch (rc) { - case CONFACK: - *lenp = (int)(next - inp); - break; - case CONFNAK: - /* - * Copy the Nak'd options from the nak_buffer to the caller's buffer. - */ - *lenp = (int)(nakp - nak_buffer); - BCOPY(nak_buffer, inp, *lenp); - break; - case CONFREJ: - *lenp = (int)(rejp - inp); - break; - } - -#if TRACELCP > 0 - if (traceNdx > 0) { - LCPDEBUG((LOG_INFO, "lcp_reqci: %s\n", traceBuf)); - } -#endif - LCPDEBUG((LOG_INFO, "lcp_reqci: returning CONF%s.\n", CODENAME(rc))); - return (rc); /* Return final code */ -} - - -/* - * lcp_up - LCP has come UP. - */ -static void lcp_up(fsm *f) -{ - lcp_options *wo = &lcp_wantoptions[f->unit]; - lcp_options *ho = &lcp_hisoptions[f->unit]; - lcp_options *go = &lcp_gotoptions[f->unit]; - lcp_options *ao = &lcp_allowoptions[f->unit]; - - if (!go->neg_magicnumber) - go->magicnumber = 0; - if (!ho->neg_magicnumber) - ho->magicnumber = 0; - - /* - * Set our MTU to the smaller of the MTU we wanted and - * the MRU our peer wanted. If we negotiated an MRU, - * set our MRU to the larger of value we wanted and - * the value we got in the negotiation. - */ - ppp_send_config(f->unit, LWIP_MIN(ao->mru, (ho->neg_mru? ho->mru: PPP_MRU)), - (ho->neg_asyncmap? ho->asyncmap: 0xffffffffl), - ho->neg_pcompression, ho->neg_accompression); - /* - * If the asyncmap hasn't been negotiated, we really should - * set the receive asyncmap to ffffffff, but we set it to 0 - * for backwards contemptibility. - */ - ppp_recv_config(f->unit, (go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU), - (go->neg_asyncmap? go->asyncmap: 0x00000000), - go->neg_pcompression, go->neg_accompression); - - if (ho->neg_mru) - peer_mru[f->unit] = ho->mru; - - lcp_echo_lowerup(f->unit); /* Enable echo messages */ - - link_established(f->unit); -} - - -/* - * lcp_down - LCP has gone DOWN. - * - * Alert other protocols. - */ -static void lcp_down(fsm *f) -{ - lcp_options *go = &lcp_gotoptions[f->unit]; - - lcp_echo_lowerdown(f->unit); - - link_down(f->unit); - - ppp_send_config(f->unit, PPP_MRU, 0xffffffffl, 0, 0); - ppp_recv_config(f->unit, PPP_MRU, - (go->neg_asyncmap? go->asyncmap: 0x00000000), - go->neg_pcompression, go->neg_accompression); - peer_mru[f->unit] = PPP_MRU; -} - - -/* - * lcp_starting - LCP needs the lower layer up. - */ -static void lcp_starting(fsm *f) -{ - link_required(f->unit); -} - - -/* - * lcp_finished - LCP has finished with the lower layer. - */ -static void lcp_finished(fsm *f) -{ - link_terminated(f->unit); -} - - -#if 0 -/* - * print_string - print a readable representation of a string using - * printer. - */ -static void print_string( - char *p, - int len, - void (*printer) (void *, char *, ...), - void *arg -) -{ - int c; - - printer(arg, "\""); - for (; len > 0; --len) { - c = *p++; - if (' ' <= c && c <= '~') { - if (c == '\\' || c == '"') - printer(arg, "\\"); - printer(arg, "%c", c); - } else { - switch (c) { - case '\n': - printer(arg, "\\n"); - break; - case '\r': - printer(arg, "\\r"); - break; - case '\t': - printer(arg, "\\t"); - break; - default: - printer(arg, "\\%.3o", c); - } - } - } - printer(arg, "\""); -} - - -/* - * lcp_printpkt - print the contents of an LCP packet. - */ -static char *lcp_codenames[] = { - "ConfReq", "ConfAck", "ConfNak", "ConfRej", - "TermReq", "TermAck", "CodeRej", "ProtRej", - "EchoReq", "EchoRep", "DiscReq" -}; - -static int lcp_printpkt( - u_char *p, - int plen, - void (*printer) (void *, char *, ...), - void *arg -) -{ - int code, id, len, olen; - u_char *pstart, *optend; - u_short cishort; - u32_t cilong; - - if (plen < HEADERLEN) - return 0; - pstart = p; - GETCHAR(code, p); - GETCHAR(id, p); - GETSHORT(len, p); - if (len < HEADERLEN || len > plen) - return 0; - - if (code >= 1 && code <= sizeof(lcp_codenames) / sizeof(char *)) - printer(arg, " %s", lcp_codenames[code-1]); - else - printer(arg, " code=0x%x", code); - printer(arg, " id=0x%x", id); - len -= HEADERLEN; - switch (code) { - case CONFREQ: - case CONFACK: - case CONFNAK: - case CONFREJ: - /* print option list */ - while (len >= 2) { - GETCHAR(code, p); - GETCHAR(olen, p); - p -= 2; - if (olen < 2 || olen > len) { - break; - } - printer(arg, " <"); - len -= olen; - optend = p + olen; - switch (code) { - case CI_MRU: - if (olen == CILEN_SHORT) { - p += 2; - GETSHORT(cishort, p); - printer(arg, "mru %d", cishort); - } - break; - case CI_ASYNCMAP: - if (olen == CILEN_LONG) { - p += 2; - GETLONG(cilong, p); - printer(arg, "asyncmap 0x%lx", cilong); - } - break; - case CI_AUTHTYPE: - if (olen >= CILEN_SHORT) { - p += 2; - printer(arg, "auth "); - GETSHORT(cishort, p); - switch (cishort) { - case PPP_PAP: - printer(arg, "pap"); - break; - case PPP_CHAP: - printer(arg, "chap"); - break; - default: - printer(arg, "0x%x", cishort); - } - } - break; - case CI_QUALITY: - if (olen >= CILEN_SHORT) { - p += 2; - printer(arg, "quality "); - GETSHORT(cishort, p); - switch (cishort) { - case PPP_LQR: - printer(arg, "lqr"); - break; - default: - printer(arg, "0x%x", cishort); - } - } - break; - case CI_CALLBACK: - if (olen >= CILEN_CHAR) { - p += 2; - printer(arg, "callback "); - GETSHORT(cishort, p); - switch (cishort) { - case CBCP_OPT: - printer(arg, "CBCP"); - break; - default: - printer(arg, "0x%x", cishort); - } - } - break; - case CI_MAGICNUMBER: - if (olen == CILEN_LONG) { - p += 2; - GETLONG(cilong, p); - printer(arg, "magic 0x%x", cilong); - } - break; - case CI_PCOMPRESSION: - if (olen == CILEN_VOID) { - p += 2; - printer(arg, "pcomp"); - } - break; - case CI_ACCOMPRESSION: - if (olen == CILEN_VOID) { - p += 2; - printer(arg, "accomp"); - } - break; - } - while (p < optend) { - GETCHAR(code, p); - printer(arg, " %.2x", code); - } - printer(arg, ">"); - } - break; - - case TERMACK: - case TERMREQ: - if (len > 0 && *p >= ' ' && *p < 0x7f) { - printer(arg, " "); - print_string((char*)p, len, printer, arg); - p += len; - len = 0; - } - break; - - case ECHOREQ: - case ECHOREP: - case DISCREQ: - if (len >= 4) { - GETLONG(cilong, p); - printer(arg, " magic=0x%x", cilong); - p += 4; - len -= 4; - } - break; - } - - /* print the rest of the bytes in the packet */ - for (; len > 0; --len) { - GETCHAR(code, p); - printer(arg, " %.2x", code); - } - - return (int)(p - pstart); -} -#endif - -/* - * Time to shut down the link because there is nothing out there. - */ - -static void LcpLinkFailure (fsm *f) -{ - if (f->state == OPENED) { - LCPDEBUG((LOG_INFO, "No response to %d echo-requests\n", lcp_echos_pending)); - LCPDEBUG((LOG_NOTICE, "Serial link appears to be disconnected.\n")); - lcp_close(f->unit, "Peer not responding"); - } -} - -/* - * Timer expired for the LCP echo requests from this process. - */ - -static void LcpEchoCheck (fsm *f) -{ - LcpSendEchoRequest (f); - - /* - * Start the timer for the next interval. - */ - LWIP_ASSERT("lcp_echo_timer_running == 0", lcp_echo_timer_running == 0); - - TIMEOUT (LcpEchoTimeout, f, lcp_echo_interval); - lcp_echo_timer_running = 1; -} - -/* - * LcpEchoTimeout - Timer expired on the LCP echo - */ - -static void LcpEchoTimeout (void *arg) -{ - if (lcp_echo_timer_running != 0) { - lcp_echo_timer_running = 0; - LcpEchoCheck ((fsm *) arg); - } -} - -/* - * LcpEchoReply - LCP has received a reply to the echo - */ -static void lcp_received_echo_reply (fsm *f, int id, u_char *inp, int len) -{ - u32_t magic; - - (void)id; - - /* Check the magic number - don't count replies from ourselves. */ - if (len < 4) { - LCPDEBUG((LOG_WARNING, "lcp: received short Echo-Reply, length %d\n", len)); - return; - } - GETLONG(magic, inp); - if (lcp_gotoptions[f->unit].neg_magicnumber - && magic == lcp_gotoptions[f->unit].magicnumber) { - LCPDEBUG((LOG_WARNING, "appear to have received our own echo-reply!\n")); - return; - } - - /* Reset the number of outstanding echo frames */ - lcp_echos_pending = 0; -} - -/* - * LcpSendEchoRequest - Send an echo request frame to the peer - */ - -static void LcpSendEchoRequest (fsm *f) -{ - u32_t lcp_magic; - u_char pkt[4], *pktp; - - /* - * Detect the failure of the peer at this point. - */ - if (lcp_echo_fails != 0) { - if (lcp_echos_pending++ >= lcp_echo_fails) { - LcpLinkFailure(f); - lcp_echos_pending = 0; - } - } - - /* - * Make and send the echo request frame. - */ - if (f->state == OPENED) { - lcp_magic = lcp_gotoptions[f->unit].magicnumber; - pktp = pkt; - PUTLONG(lcp_magic, pktp); - fsm_sdata(f, ECHOREQ, (u_char)(lcp_echo_number++ & 0xFF), pkt, (int)(pktp - pkt)); - } -} - -/* - * lcp_echo_lowerup - Start the timer for the LCP frame - */ - -static void lcp_echo_lowerup (int unit) -{ - fsm *f = &lcp_fsm[unit]; - - /* Clear the parameters for generating echo frames */ - lcp_echos_pending = 0; - lcp_echo_number = 0; - lcp_echo_timer_running = 0; - - /* If a timeout interval is specified then start the timer */ - if (lcp_echo_interval != 0) - LcpEchoCheck (f); -} - -/* - * lcp_echo_lowerdown - Stop the timer for the LCP frame - */ - -static void lcp_echo_lowerdown (int unit) -{ - fsm *f = &lcp_fsm[unit]; - - if (lcp_echo_timer_running != 0) { - UNTIMEOUT (LcpEchoTimeout, f); - lcp_echo_timer_running = 0; - } -} - -#endif /* PPP_SUPPORT */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/lcp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/lcp.h deleted file mode 100644 index 3bf2edd50..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/lcp.h +++ /dev/null @@ -1,169 +0,0 @@ -/***************************************************************************** -* lcp.h - Network Link Control Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-11-05 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD codes. -*****************************************************************************/ -/* - * lcp.h - Link Control Protocol definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id$ - */ - -#ifndef LCP_H -#define LCP_H - - -/************************* -*** PUBLIC DEFINITIONS *** -*************************/ -/* - * Options. - */ -#define CI_MRU 1 /* Maximum Receive Unit */ -#define CI_ASYNCMAP 2 /* Async Control Character Map */ -#define CI_AUTHTYPE 3 /* Authentication Type */ -#define CI_QUALITY 4 /* Quality Protocol */ -#define CI_MAGICNUMBER 5 /* Magic Number */ -#define CI_PCOMPRESSION 7 /* Protocol Field Compression */ -#define CI_ACCOMPRESSION 8 /* Address/Control Field Compression */ -#define CI_CALLBACK 13 /* callback */ -#define CI_MRRU 17 /* max reconstructed receive unit; multilink */ -#define CI_SSNHF 18 /* short sequence numbers for multilink */ -#define CI_EPDISC 19 /* endpoint discriminator */ - -/* - * LCP-specific packet types. - */ -#define PROTREJ 8 /* Protocol Reject */ -#define ECHOREQ 9 /* Echo Request */ -#define ECHOREP 10 /* Echo Reply */ -#define DISCREQ 11 /* Discard Request */ -#define CBCP_OPT 6 /* Use callback control protocol */ - - -/************************ -*** PUBLIC DATA TYPES *** -************************/ - -/* - * The state of options is described by an lcp_options structure. - */ -typedef struct lcp_options { - u_int passive : 1; /* Don't die if we don't get a response */ - u_int silent : 1; /* Wait for the other end to start first */ - u_int restart : 1; /* Restart vs. exit after close */ - u_int neg_mru : 1; /* Negotiate the MRU? */ - u_int neg_asyncmap : 1; /* Negotiate the async map? */ - u_int neg_upap : 1; /* Ask for UPAP authentication? */ - u_int neg_chap : 1; /* Ask for CHAP authentication? */ - u_int neg_magicnumber : 1; /* Ask for magic number? */ - u_int neg_pcompression : 1; /* HDLC Protocol Field Compression? */ - u_int neg_accompression : 1; /* HDLC Address/Control Field Compression? */ - u_int neg_lqr : 1; /* Negotiate use of Link Quality Reports */ - u_int neg_cbcp : 1; /* Negotiate use of CBCP */ -#ifdef PPP_MULTILINK - u_int neg_mrru : 1; /* Negotiate multilink MRRU */ - u_int neg_ssnhf : 1; /* Negotiate short sequence numbers */ - u_int neg_endpoint : 1; /* Negotiate endpoint discriminator */ -#endif - u_short mru; /* Value of MRU */ -#ifdef PPP_MULTILINK - u_short mrru; /* Value of MRRU, and multilink enable */ -#endif - u_char chap_mdtype; /* which MD type (hashing algorithm) */ - u32_t asyncmap; /* Value of async map */ - u32_t magicnumber; - int numloops; /* Number of loops during magic number neg. */ - u32_t lqr_period; /* Reporting period for LQR 1/100ths second */ -#ifdef PPP_MULTILINK - struct epdisc endpoint; /* endpoint discriminator */ -#endif -} lcp_options; - -/* - * Values for phase from BSD pppd.h based on RFC 1661. - */ -typedef enum { - PHASE_DEAD = 0, - PHASE_INITIALIZE, - PHASE_ESTABLISH, - PHASE_AUTHENTICATE, - PHASE_CALLBACK, - PHASE_NETWORK, - PHASE_TERMINATE -} LinkPhase; - - -/***************************** -*** PUBLIC DATA STRUCTURES *** -*****************************/ - -extern LinkPhase lcp_phase[NUM_PPP]; /* Phase of link session (RFC 1661) */ -extern lcp_options lcp_wantoptions[]; -extern lcp_options lcp_gotoptions[]; -extern lcp_options lcp_allowoptions[]; -extern lcp_options lcp_hisoptions[]; -extern ext_accm xmit_accm[]; - - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ - -void lcp_init (int); -void lcp_open (int); -void lcp_close (int, char *); -void lcp_lowerup (int); -void lcp_lowerdown (int); -void lcp_sprotrej (int, u_char *, int); /* send protocol reject */ - -extern struct protent lcp_protent; - -/* Default number of times we receive our magic number from the peer - before deciding the link is looped-back. */ -#define DEFLOOPBACKFAIL 10 - -#endif /* LCP_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/magic.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/magic.c deleted file mode 100644 index 427401691..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/magic.c +++ /dev/null @@ -1,79 +0,0 @@ -/***************************************************************************** -* magic.c - Network Random Number Generator program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original based on BSD magic.c. -*****************************************************************************/ -/* - * magic.c - PPP Magic Number routines. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include "ppp.h" -#include "randm.h" -#include "magic.h" - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * magicInit - Initialize the magic number generator. - * - * Since we use another random number generator that has its own - * initialization, we do nothing here. - */ -void magicInit() -{ - return; -} - -/* - * magic - Returns the next magic number. - */ -u32_t magic() -{ - return avRandom(); -} - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/magic.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/magic.h deleted file mode 100644 index ef776d8ad..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/magic.h +++ /dev/null @@ -1,64 +0,0 @@ -/***************************************************************************** -* magic.h - Network Random Number Generator header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD codes. -*****************************************************************************/ -/* - * magic.h - PPP Magic Number definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * $Id$ - */ - -#ifndef MAGIC_H -#define MAGIC_H - -/***************************************************************************** -************************** PUBLIC FUNCTIONS ********************************** -*****************************************************************************/ - -void magicInit(void); /* Initialize the magic number generator */ -u32_t magic(void); /* Returns the next magic number */ - -#endif /* MAGIC_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/md5.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/md5.c deleted file mode 100644 index e077cdea5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/md5.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - *********************************************************************** - ** md5.c -- the source code for MD5 routines ** - ** RSA Data Security, Inc. MD5 Message-Digest Algorithm ** - ** Created: 2/17/90 RLR ** - ** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. ** - *********************************************************************** - */ - -/* - *********************************************************************** - ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved. ** - ** ** - ** License to copy and use this software is granted provided that ** - ** it is identified as the "RSA Data Security, Inc. MD5 Message- ** - ** Digest Algorithm" in all material mentioning or referencing this ** - ** software or this function. ** - ** ** - ** License is also granted to make and use derivative works ** - ** provided that such works are identified as "derived from the RSA ** - ** Data Security, Inc. MD5 Message-Digest Algorithm" in all ** - ** material mentioning or referencing the derived work. ** - ** ** - ** RSA Data Security, Inc. makes no representations concerning ** - ** either the merchantability of this software or the suitability ** - ** of this software for any particular purpose. It is provided "as ** - ** is" without express or implied warranty of any kind. ** - ** ** - ** These notices must be retained in any copies of any part of this ** - ** documentation and/or software. ** - *********************************************************************** - */ - -#include "ppp.h" -#include "md5.h" -#include "pppdebug.h" - -#if CHAP_SUPPORT > 0 || MD5_SUPPORT > 0 - -/* - *********************************************************************** - ** Message-digest routines: ** - ** To form the message digest for a message M ** - ** (1) Initialize a context buffer mdContext using MD5Init ** - ** (2) Call MD5Update on mdContext and M ** - ** (3) Call MD5Final on mdContext ** - ** The message digest is now in mdContext->digest[0...15] ** - *********************************************************************** - */ - -/* forward declaration */ -static void Transform (u32_t *buf, u32_t *in); - -static unsigned char PADDING[64] = { - 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; - -/* F, G, H and I are basic MD5 functions */ -#define F(x, y, z) (((x) & (y)) | ((~x) & (z))) -#define G(x, y, z) (((x) & (z)) | ((y) & (~z))) -#define H(x, y, z) ((x) ^ (y) ^ (z)) -#define I(x, y, z) ((y) ^ ((x) | (~z))) - -/* ROTATE_LEFT rotates x left n bits */ -#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n)))) - -/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */ -/* Rotation is separate from addition to prevent recomputation */ -#define FF(a, b, c, d, x, s, ac) \ - {(a) += F ((b), (c), (d)) + (x) + (u32_t)(ac); \ - (a) = ROTATE_LEFT ((a), (s)); \ - (a) += (b); \ - } -#define GG(a, b, c, d, x, s, ac) \ - {(a) += G ((b), (c), (d)) + (x) + (u32_t)(ac); \ - (a) = ROTATE_LEFT ((a), (s)); \ - (a) += (b); \ - } -#define HH(a, b, c, d, x, s, ac) \ - {(a) += H ((b), (c), (d)) + (x) + (u32_t)(ac); \ - (a) = ROTATE_LEFT ((a), (s)); \ - (a) += (b); \ - } -#define II(a, b, c, d, x, s, ac) \ - {(a) += I ((b), (c), (d)) + (x) + (u32_t)(ac); \ - (a) = ROTATE_LEFT ((a), (s)); \ - (a) += (b); \ - } - -#ifdef __STDC__ -#define UL(x) x##UL -#else -#ifdef WIN32 -#define UL(x) x##UL -#else -#define UL(x) x -#endif -#endif - -/* The routine MD5Init initializes the message-digest context - mdContext. All fields are set to zero. - */ -void MD5Init (MD5_CTX *mdContext) -{ - mdContext->i[0] = mdContext->i[1] = (u32_t)0; - - /* Load magic initialization constants. - */ - mdContext->buf[0] = (u32_t)0x67452301UL; - mdContext->buf[1] = (u32_t)0xefcdab89UL; - mdContext->buf[2] = (u32_t)0x98badcfeUL; - mdContext->buf[3] = (u32_t)0x10325476UL; -} - -/* The routine MD5Update updates the message-digest context to - account for the presence of each of the characters inBuf[0..inLen-1] - in the message whose digest is being computed. - */ -void MD5Update(MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen) -{ - u32_t in[16]; - int mdi; - unsigned int i, ii; - -#if 0 - ppp_trace(LOG_INFO, "MD5Update: %u:%.*H\n", inLen, MIN(inLen, 20) * 2, inBuf); - ppp_trace(LOG_INFO, "MD5Update: %u:%s\n", inLen, inBuf); -#endif - - /* compute number of bytes mod 64 */ - mdi = (int)((mdContext->i[0] >> 3) & 0x3F); - - /* update number of bits */ - if ((mdContext->i[0] + ((u32_t)inLen << 3)) < mdContext->i[0]) - mdContext->i[1]++; - mdContext->i[0] += ((u32_t)inLen << 3); - mdContext->i[1] += ((u32_t)inLen >> 29); - - while (inLen--) { - /* add new character to buffer, increment mdi */ - mdContext->in[mdi++] = *inBuf++; - - /* transform if necessary */ - if (mdi == 0x40) { - for (i = 0, ii = 0; i < 16; i++, ii += 4) - in[i] = (((u32_t)mdContext->in[ii+3]) << 24) | - (((u32_t)mdContext->in[ii+2]) << 16) | - (((u32_t)mdContext->in[ii+1]) << 8) | - ((u32_t)mdContext->in[ii]); - Transform (mdContext->buf, in); - mdi = 0; - } - } -} - -/* The routine MD5Final terminates the message-digest computation and - ends with the desired message digest in mdContext->digest[0...15]. - */ -void MD5Final (unsigned char hash[], MD5_CTX *mdContext) -{ - u32_t in[16]; - int mdi; - unsigned int i, ii; - unsigned int padLen; - - /* save number of bits */ - in[14] = mdContext->i[0]; - in[15] = mdContext->i[1]; - - /* compute number of bytes mod 64 */ - mdi = (int)((mdContext->i[0] >> 3) & 0x3F); - - /* pad out to 56 mod 64 */ - padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi); - MD5Update (mdContext, PADDING, padLen); - - /* append length in bits and transform */ - for (i = 0, ii = 0; i < 14; i++, ii += 4) - in[i] = (((u32_t)mdContext->in[ii+3]) << 24) | - (((u32_t)mdContext->in[ii+2]) << 16) | - (((u32_t)mdContext->in[ii+1]) << 8) | - ((u32_t)mdContext->in[ii]); - Transform (mdContext->buf, in); - - /* store buffer in digest */ - for (i = 0, ii = 0; i < 4; i++, ii += 4) { - mdContext->digest[ii] = (unsigned char)(mdContext->buf[i] & 0xFF); - mdContext->digest[ii+1] = - (unsigned char)((mdContext->buf[i] >> 8) & 0xFF); - mdContext->digest[ii+2] = - (unsigned char)((mdContext->buf[i] >> 16) & 0xFF); - mdContext->digest[ii+3] = - (unsigned char)((mdContext->buf[i] >> 24) & 0xFF); - } - memcpy(hash, mdContext->digest, 16); -} - -/* Basic MD5 step. Transforms buf based on in. - */ -static void Transform (u32_t *buf, u32_t *in) -{ - u32_t a = buf[0], b = buf[1], c = buf[2], d = buf[3]; - - /* Round 1 */ -#define S11 7 -#define S12 12 -#define S13 17 -#define S14 22 - FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */ - FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */ - FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */ - FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */ - FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */ - FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */ - FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */ - FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */ - FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */ - FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */ - FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */ - FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */ - FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */ - FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */ - FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */ - FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */ - - /* Round 2 */ -#define S21 5 -#define S22 9 -#define S23 14 -#define S24 20 - GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */ - GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */ - GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */ - GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */ - GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */ - GG ( d, a, b, c, in[10], S22, UL( 38016083)); /* 22 */ - GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */ - GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */ - GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */ - GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */ - GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */ - GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */ - GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */ - GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */ - GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */ - GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */ - - /* Round 3 */ -#define S31 4 -#define S32 11 -#define S33 16 -#define S34 23 - HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */ - HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */ - HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */ - HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */ - HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */ - HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */ - HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */ - HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */ - HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */ - HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */ - HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */ - HH ( b, c, d, a, in[ 6], S34, UL( 76029189)); /* 44 */ - HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */ - HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */ - HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */ - HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */ - - /* Round 4 */ -#define S41 6 -#define S42 10 -#define S43 15 -#define S44 21 - II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */ - II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */ - II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */ - II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */ - II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */ - II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */ - II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */ - II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */ - II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */ - II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */ - II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */ - II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */ - II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */ - II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */ - II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */ - II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */ - - buf[0] += a; - buf[1] += b; - buf[2] += c; - buf[3] += d; -} - -#endif - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/md5.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/md5.h deleted file mode 100644 index 0e81cdc34..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/md5.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - *********************************************************************** - ** md5.h -- header file for implementation of MD5 ** - ** RSA Data Security, Inc. MD5 Message-Digest Algorithm ** - ** Created: 2/17/90 RLR ** - ** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version ** - ** Revised (for MD5): RLR 4/27/91 ** - ** -- G modified to have y&~z instead of y&z ** - ** -- FF, GG, HH modified to add in last register done ** - ** -- Access pattern: round 2 works mod 5, round 3 works mod 3 ** - ** -- distinct additive constant for each step ** - ** -- round 4 added, working mod 7 ** - *********************************************************************** - */ - -/* - *********************************************************************** - ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved. ** - ** ** - ** License to copy and use this software is granted provided that ** - ** it is identified as the "RSA Data Security, Inc. MD5 Message- ** - ** Digest Algorithm" in all material mentioning or referencing this ** - ** software or this function. ** - ** ** - ** License is also granted to make and use derivative works ** - ** provided that such works are identified as "derived from the RSA ** - ** Data Security, Inc. MD5 Message-Digest Algorithm" in all ** - ** material mentioning or referencing the derived work. ** - ** ** - ** RSA Data Security, Inc. makes no representations concerning ** - ** either the merchantability of this software or the suitability ** - ** of this software for any particular purpose. It is provided "as ** - ** is" without express or implied warranty of any kind. ** - ** ** - ** These notices must be retained in any copies of any part of this ** - ** documentation and/or software. ** - *********************************************************************** - */ - -#ifndef MD5_H -#define MD5_H - -/* Data structure for MD5 (Message-Digest) computation */ -typedef struct { - u32_t i[2]; /* number of _bits_ handled mod 2^64 */ - u32_t buf[4]; /* scratch buffer */ - unsigned char in[64]; /* input buffer */ - unsigned char digest[16]; /* actual digest after MD5Final call */ -} MD5_CTX; - -void MD5Init (MD5_CTX *mdContext); -void MD5Update (MD5_CTX *mdContext, unsigned char *inBuf, unsigned int inLen); -void MD5Final (unsigned char hash[], MD5_CTX *mdContext); - -#endif /* MD5_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/pap.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/pap.c deleted file mode 100644 index 23e438ff2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/pap.c +++ /dev/null @@ -1,608 +0,0 @@ -/***************************************************************************** -* pap.c - Network Password Authentication Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-12 Guy Lancaster , Global Election Systems Inc. -* Original. -*****************************************************************************/ -/* - * upap.c - User/Password Authentication Protocol. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include "ppp.h" -#include "auth.h" -#include "pap.h" -#include "pppdebug.h" - - -#if PAP_SUPPORT > 0 - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -/* - * Protocol entry points. - */ -static void upap_init (int); -static void upap_lowerup (int); -static void upap_lowerdown (int); -static void upap_input (int, u_char *, int); -static void upap_protrej (int); - -static void upap_timeout (void *); -static void upap_reqtimeout (void *); -static void upap_rauthreq (upap_state *, u_char *, int, int); -static void upap_rauthack (upap_state *, u_char *, int, int); -static void upap_rauthnak (upap_state *, u_char *, int, int); -static void upap_sauthreq (upap_state *); -static void upap_sresp (upap_state *, u_char, u_char, char *, int); - - - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ -struct protent pap_protent = { - PPP_PAP, - upap_init, - upap_input, - upap_protrej, - upap_lowerup, - upap_lowerdown, - NULL, - NULL, -#if 0 - upap_printpkt, - NULL, -#endif - 1, - "PAP", -#if 0 - NULL, - NULL, - NULL -#endif -}; - -upap_state upap[NUM_PPP]; /* UPAP state; one for each unit */ - - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * Set the default login name and password for the pap sessions - */ -void upap_setloginpasswd(int unit, const char *luser, const char *lpassword) -{ - upap_state *u = &upap[unit]; - - /* Save the username and password we're given */ - u->us_user = luser; - u->us_userlen = strlen(luser); - u->us_passwd = lpassword; - u->us_passwdlen = strlen(lpassword); -} - - -/* - * upap_authwithpeer - Authenticate us with our peer (start client). - * - * Set new state and send authenticate's. - */ -void upap_authwithpeer(int unit, char *user, char *password) -{ - upap_state *u = &upap[unit]; - - UPAPDEBUG((LOG_INFO, "upap_authwithpeer: %d user=%s password=%s s=%d\n", - unit, user, password, u->us_clientstate)); - - upap_setloginpasswd(unit, user, password); - - u->us_transmits = 0; - - /* Lower layer up yet? */ - if (u->us_clientstate == UPAPCS_INITIAL || - u->us_clientstate == UPAPCS_PENDING) { - u->us_clientstate = UPAPCS_PENDING; - return; - } - - upap_sauthreq(u); /* Start protocol */ -} - - -/* - * upap_authpeer - Authenticate our peer (start server). - * - * Set new state. - */ -void upap_authpeer(int unit) -{ - upap_state *u = &upap[unit]; - - /* Lower layer up yet? */ - if (u->us_serverstate == UPAPSS_INITIAL || - u->us_serverstate == UPAPSS_PENDING) { - u->us_serverstate = UPAPSS_PENDING; - return; - } - - u->us_serverstate = UPAPSS_LISTEN; - if (u->us_reqtimeout > 0) - TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout); -} - - - -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ -/* - * upap_init - Initialize a UPAP unit. - */ -static void upap_init(int unit) -{ - upap_state *u = &upap[unit]; - - UPAPDEBUG((LOG_INFO, "upap_init: %d\n", unit)); - u->us_unit = unit; - u->us_user = NULL; - u->us_userlen = 0; - u->us_passwd = NULL; - u->us_passwdlen = 0; - u->us_clientstate = UPAPCS_INITIAL; - u->us_serverstate = UPAPSS_INITIAL; - u->us_id = 0; - u->us_timeouttime = UPAP_DEFTIMEOUT; - u->us_maxtransmits = 10; - u->us_reqtimeout = UPAP_DEFREQTIME; -} - -/* - * upap_timeout - Retransmission timer for sending auth-reqs expired. - */ -static void upap_timeout(void *arg) -{ - upap_state *u = (upap_state *) arg; - - UPAPDEBUG((LOG_INFO, "upap_timeout: %d timeout %d expired s=%d\n", - u->us_unit, u->us_timeouttime, u->us_clientstate)); - - if (u->us_clientstate != UPAPCS_AUTHREQ) - return; - - if (u->us_transmits >= u->us_maxtransmits) { - /* give up in disgust */ - UPAPDEBUG((LOG_ERR, "No response to PAP authenticate-requests\n")); - u->us_clientstate = UPAPCS_BADAUTH; - auth_withpeer_fail(u->us_unit, PPP_PAP); - return; - } - - upap_sauthreq(u); /* Send Authenticate-Request */ -} - - -/* - * upap_reqtimeout - Give up waiting for the peer to send an auth-req. - */ -static void upap_reqtimeout(void *arg) -{ - upap_state *u = (upap_state *) arg; - - if (u->us_serverstate != UPAPSS_LISTEN) - return; /* huh?? */ - - auth_peer_fail(u->us_unit, PPP_PAP); - u->us_serverstate = UPAPSS_BADAUTH; -} - - -/* - * upap_lowerup - The lower layer is up. - * - * Start authenticating if pending. - */ -static void upap_lowerup(int unit) -{ - upap_state *u = &upap[unit]; - - UPAPDEBUG((LOG_INFO, "upap_lowerup: %d s=%d\n", unit, u->us_clientstate)); - - if (u->us_clientstate == UPAPCS_INITIAL) - u->us_clientstate = UPAPCS_CLOSED; - else if (u->us_clientstate == UPAPCS_PENDING) { - upap_sauthreq(u); /* send an auth-request */ - } - - if (u->us_serverstate == UPAPSS_INITIAL) - u->us_serverstate = UPAPSS_CLOSED; - else if (u->us_serverstate == UPAPSS_PENDING) { - u->us_serverstate = UPAPSS_LISTEN; - if (u->us_reqtimeout > 0) - TIMEOUT(upap_reqtimeout, u, u->us_reqtimeout); - } -} - - -/* - * upap_lowerdown - The lower layer is down. - * - * Cancel all timeouts. - */ -static void upap_lowerdown(int unit) -{ - upap_state *u = &upap[unit]; - - UPAPDEBUG((LOG_INFO, "upap_lowerdown: %d s=%d\n", unit, u->us_clientstate)); - - if (u->us_clientstate == UPAPCS_AUTHREQ) /* Timeout pending? */ - UNTIMEOUT(upap_timeout, u); /* Cancel timeout */ - if (u->us_serverstate == UPAPSS_LISTEN && u->us_reqtimeout > 0) - UNTIMEOUT(upap_reqtimeout, u); - - u->us_clientstate = UPAPCS_INITIAL; - u->us_serverstate = UPAPSS_INITIAL; -} - - -/* - * upap_protrej - Peer doesn't speak this protocol. - * - * This shouldn't happen. In any case, pretend lower layer went down. - */ -static void upap_protrej(int unit) -{ - upap_state *u = &upap[unit]; - - if (u->us_clientstate == UPAPCS_AUTHREQ) { - UPAPDEBUG((LOG_ERR, "PAP authentication failed due to protocol-reject\n")); - auth_withpeer_fail(unit, PPP_PAP); - } - if (u->us_serverstate == UPAPSS_LISTEN) { - UPAPDEBUG((LOG_ERR, "PAP authentication of peer failed (protocol-reject)\n")); - auth_peer_fail(unit, PPP_PAP); - } - upap_lowerdown(unit); -} - - -/* - * upap_input - Input UPAP packet. - */ -static void upap_input(int unit, u_char *inpacket, int l) -{ - upap_state *u = &upap[unit]; - u_char *inp; - u_char code, id; - int len; - - /* - * Parse header (code, id and length). - * If packet too short, drop it. - */ - inp = inpacket; - if (l < UPAP_HEADERLEN) { - UPAPDEBUG((LOG_INFO, "pap_input: rcvd short header.\n")); - return; - } - GETCHAR(code, inp); - GETCHAR(id, inp); - GETSHORT(len, inp); - if (len < UPAP_HEADERLEN) { - UPAPDEBUG((LOG_INFO, "pap_input: rcvd illegal length.\n")); - return; - } - if (len > l) { - UPAPDEBUG((LOG_INFO, "pap_input: rcvd short packet.\n")); - return; - } - len -= UPAP_HEADERLEN; - - /* - * Action depends on code. - */ - switch (code) { - case UPAP_AUTHREQ: - upap_rauthreq(u, inp, id, len); - break; - - case UPAP_AUTHACK: - upap_rauthack(u, inp, id, len); - break; - - case UPAP_AUTHNAK: - upap_rauthnak(u, inp, id, len); - break; - - default: /* XXX Need code reject */ - break; - } -} - - -/* - * upap_rauth - Receive Authenticate. - */ -static void upap_rauthreq( - upap_state *u, - u_char *inp, - int id, - int len -) -{ - u_char ruserlen, rpasswdlen; - char *ruser, *rpasswd; - int retcode; - char *msg; - int msglen; - - UPAPDEBUG((LOG_INFO, "pap_rauth: Rcvd id %d.\n", id)); - - if (u->us_serverstate < UPAPSS_LISTEN) - return; - - /* - * If we receive a duplicate authenticate-request, we are - * supposed to return the same status as for the first request. - */ - if (u->us_serverstate == UPAPSS_OPEN) { - upap_sresp(u, UPAP_AUTHACK, id, "", 0); /* return auth-ack */ - return; - } - if (u->us_serverstate == UPAPSS_BADAUTH) { - upap_sresp(u, UPAP_AUTHNAK, id, "", 0); /* return auth-nak */ - return; - } - - /* - * Parse user/passwd. - */ - if (len < sizeof (u_char)) { - UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n")); - return; - } - GETCHAR(ruserlen, inp); - len -= sizeof (u_char) + ruserlen + sizeof (u_char); - if (len < 0) { - UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n")); - return; - } - ruser = (char *) inp; - INCPTR(ruserlen, inp); - GETCHAR(rpasswdlen, inp); - if (len < rpasswdlen) { - UPAPDEBUG((LOG_INFO, "pap_rauth: rcvd short packet.\n")); - return; - } - rpasswd = (char *) inp; - - /* - * Check the username and password given. - */ - retcode = check_passwd(u->us_unit, ruser, ruserlen, rpasswd, - rpasswdlen, &msg, &msglen); - BZERO(rpasswd, rpasswdlen); - - upap_sresp(u, retcode, id, msg, msglen); - - if (retcode == UPAP_AUTHACK) { - u->us_serverstate = UPAPSS_OPEN; - auth_peer_success(u->us_unit, PPP_PAP, ruser, ruserlen); - } else { - u->us_serverstate = UPAPSS_BADAUTH; - auth_peer_fail(u->us_unit, PPP_PAP); - } - - if (u->us_reqtimeout > 0) - UNTIMEOUT(upap_reqtimeout, u); -} - - -/* - * upap_rauthack - Receive Authenticate-Ack. - */ -static void upap_rauthack( - upap_state *u, - u_char *inp, - int id, - int len -) -{ - u_char msglen; - char *msg; - - UPAPDEBUG((LOG_INFO, "pap_rauthack: Rcvd id %d s=%d\n", id, u->us_clientstate)); - - if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */ - return; - - /* - * Parse message. - */ - if (len < sizeof (u_char)) { - UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n")); - return; - } - GETCHAR(msglen, inp); - len -= sizeof (u_char); - if (len < msglen) { - UPAPDEBUG((LOG_INFO, "pap_rauthack: rcvd short packet.\n")); - return; - } - msg = (char *) inp; - PRINTMSG(msg, msglen); - - u->us_clientstate = UPAPCS_OPEN; - - auth_withpeer_success(u->us_unit, PPP_PAP); -} - - -/* - * upap_rauthnak - Receive Authenticate-Nakk. - */ -static void upap_rauthnak( - upap_state *u, - u_char *inp, - int id, - int len -) -{ - u_char msglen; - char *msg; - - UPAPDEBUG((LOG_INFO, "pap_rauthnak: Rcvd id %d s=%d\n", id, u->us_clientstate)); - - if (u->us_clientstate != UPAPCS_AUTHREQ) /* XXX */ - return; - - /* - * Parse message. - */ - if (len < sizeof (u_char)) { - UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n")); - return; - } - GETCHAR(msglen, inp); - len -= sizeof (u_char); - if (len < msglen) { - UPAPDEBUG((LOG_INFO, "pap_rauthnak: rcvd short packet.\n")); - return; - } - msg = (char *) inp; - PRINTMSG(msg, msglen); - - u->us_clientstate = UPAPCS_BADAUTH; - - UPAPDEBUG((LOG_ERR, "PAP authentication failed\n")); - auth_withpeer_fail(u->us_unit, PPP_PAP); -} - - -/* - * upap_sauthreq - Send an Authenticate-Request. - */ -static void upap_sauthreq(upap_state *u) -{ - u_char *outp; - int outlen; - - outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) - + u->us_userlen + u->us_passwdlen; - outp = outpacket_buf[u->us_unit]; - - MAKEHEADER(outp, PPP_PAP); - - PUTCHAR(UPAP_AUTHREQ, outp); - PUTCHAR(++u->us_id, outp); - PUTSHORT(outlen, outp); - PUTCHAR(u->us_userlen, outp); - BCOPY(u->us_user, outp, u->us_userlen); - INCPTR(u->us_userlen, outp); - PUTCHAR(u->us_passwdlen, outp); - BCOPY(u->us_passwd, outp, u->us_passwdlen); - - pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN); - - UPAPDEBUG((LOG_INFO, "pap_sauth: Sent id %d\n", u->us_id)); - - TIMEOUT(upap_timeout, u, u->us_timeouttime); - ++u->us_transmits; - u->us_clientstate = UPAPCS_AUTHREQ; -} - - -/* - * upap_sresp - Send a response (ack or nak). - */ -static void upap_sresp( - upap_state *u, - u_char code, - u_char id, - char *msg, - int msglen -) -{ - u_char *outp; - int outlen; - - outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen; - outp = outpacket_buf[u->us_unit]; - MAKEHEADER(outp, PPP_PAP); - - PUTCHAR(code, outp); - PUTCHAR(id, outp); - PUTSHORT(outlen, outp); - PUTCHAR(msglen, outp); - BCOPY(msg, outp, msglen); - pppWrite(u->us_unit, outpacket_buf[u->us_unit], outlen + PPP_HDRLEN); - - UPAPDEBUG((LOG_INFO, "pap_sresp: Sent code %d, id %d s=%d\n", - code, id, u->us_clientstate)); -} - -#if 0 -/* - * upap_printpkt - print the contents of a PAP packet. - */ -static int upap_printpkt( - u_char *p, - int plen, - void (*printer) (void *, char *, ...), - void *arg -) -{ - (void)p; - (void)plen; - (void)printer; - (void)arg; - return 0; -} -#endif - -#endif /* PAP_SUPPORT */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/pap.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/pap.h deleted file mode 100644 index 215c8a4f2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/pap.h +++ /dev/null @@ -1,129 +0,0 @@ -/***************************************************************************** -* pap.h - PPP Password Authentication Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-12-04 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD codes. -*****************************************************************************/ -/* - * upap.h - User/Password Authentication Protocol definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - - -#ifndef PAP_H -#define PAP_H - -/************************* -*** PUBLIC DEFINITIONS *** -*************************/ -/* - * Packet header = Code, id, length. - */ -#define UPAP_HEADERLEN (sizeof (u_char) + sizeof (u_char) + sizeof (u_short)) - - -/* - * UPAP codes. - */ -#define UPAP_AUTHREQ 1 /* Authenticate-Request */ -#define UPAP_AUTHACK 2 /* Authenticate-Ack */ -#define UPAP_AUTHNAK 3 /* Authenticate-Nak */ - -/* - * Client states. - */ -#define UPAPCS_INITIAL 0 /* Connection down */ -#define UPAPCS_CLOSED 1 /* Connection up, haven't requested auth */ -#define UPAPCS_PENDING 2 /* Connection down, have requested auth */ -#define UPAPCS_AUTHREQ 3 /* We've sent an Authenticate-Request */ -#define UPAPCS_OPEN 4 /* We've received an Ack */ -#define UPAPCS_BADAUTH 5 /* We've received a Nak */ - -/* - * Server states. - */ -#define UPAPSS_INITIAL 0 /* Connection down */ -#define UPAPSS_CLOSED 1 /* Connection up, haven't requested auth */ -#define UPAPSS_PENDING 2 /* Connection down, have requested auth */ -#define UPAPSS_LISTEN 3 /* Listening for an Authenticate */ -#define UPAPSS_OPEN 4 /* We've sent an Ack */ -#define UPAPSS_BADAUTH 5 /* We've sent a Nak */ - - -/************************ -*** PUBLIC DATA TYPES *** -************************/ - -/* - * Each interface is described by upap structure. - */ -typedef struct upap_state { - int us_unit; /* Interface unit number */ - const char *us_user; /* User */ - int us_userlen; /* User length */ - const char *us_passwd; /* Password */ - int us_passwdlen; /* Password length */ - int us_clientstate; /* Client state */ - int us_serverstate; /* Server state */ - u_char us_id; /* Current id */ - int us_timeouttime; /* Timeout (seconds) for auth-req retrans. */ - int us_transmits; /* Number of auth-reqs sent */ - int us_maxtransmits; /* Maximum number of auth-reqs to send */ - int us_reqtimeout; /* Time to wait for auth-req from peer */ -} upap_state; - - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ - -extern upap_state upap[]; - -void upap_setloginpasswd(int unit, const char *luser, const char *lpassword); -void upap_authwithpeer (int, char *, char *); -void upap_authpeer (int); - -extern struct protent pap_protent; - -#endif /* PAP_H */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/ppp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/ppp.c deleted file mode 100644 index 0d22eabfa..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/ppp.c +++ /dev/null @@ -1,1644 +0,0 @@ -/***************************************************************************** -* ppp.c - Network Point to Point Protocol program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* 06-09-13 Christian Walter -* pppMain now correctly exists by releasing all resources and destroying -* the thread. -* 06-08-04 Christian Walter -* pppOpen code now checks if thread creation was successfull. If not returns -* an error. -* pppMain now correctly closes the thread if it exists. -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-11-05 Guy Lancaster , Global Election Systems Inc. -* Original. -*****************************************************************************/ - -/* - * ppp_defs.h - PPP definitions. - * - * if_pppvar.h - private structures and declarations for PPP. - * - * Copyright (c) 1994 The Australian National University. - * All rights reserved. - * - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, provided that the above copyright - * notice appears in all copies. This software is provided without any - * warranty, express or implied. The Australian National University - * makes no representations about the suitability of this software for - * any purpose. - * - * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY - * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES - * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF - * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS - * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO - * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, - * OR MODIFICATIONS. - */ - -/* - * if_ppp.h - Point-to-Point Protocol definitions. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. - */ - -#include - -#include "ppp.h" -#if PPP_SUPPORT > 0 -#include "randm.h" -#include "fsm.h" -#if PAP_SUPPORT > 0 -#include "pap.h" -#endif -#if CHAP_SUPPORT > 0 -#include "chap.h" -#endif -#include "ipcp.h" -#include "lcp.h" -#include "magic.h" -#include "auth.h" -#if VJ_SUPPORT > 0 -#include "vj.h" -#endif - -#include "pppdebug.h" - -/*************************/ -/*** LOCAL DEFINITIONS ***/ -/*************************/ - -/* - * The basic PPP frame. - */ -#define PPP_ADDRESS(p) (((u_char *)(p))[0]) -#define PPP_CONTROL(p) (((u_char *)(p))[1]) -#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3]) - -/* PPP packet parser states. Current state indicates operation yet to be - * completed. */ -typedef enum { - PDIDLE = 0, /* Idle state - waiting. */ - PDSTART, /* Process start flag. */ - PDADDRESS, /* Process address field. */ - PDCONTROL, /* Process control field. */ - PDPROTOCOL1, /* Process protocol field 1. */ - PDPROTOCOL2, /* Process protocol field 2. */ - PDDATA /* Process data byte. */ -} PPPDevStates; - -#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & pppACCMMask[c & 0x07]) - -/************************/ -/*** LOCAL DATA TYPES ***/ -/************************/ -/* - * PPP interface control block. - */ -typedef struct PPPControl_s { - char openFlag; /* True when in use. */ - char oldFrame; /* Old framing character for fd. */ - sio_fd_t fd; /* File device ID of port. */ - int kill_link; /* Shut the link down. */ - int sig_hup; /* Carrier lost. */ - int if_up; /* True when the interface is up. */ - int errCode; /* Code indicating why interface is down. */ - struct pbuf *inHead, *inTail; /* The input packet. */ - PPPDevStates inState; /* The input process state. */ - char inEscaped; /* Escape next character. */ - u16_t inProtocol; /* The input protocol code. */ - u16_t inFCS; /* Input Frame Check Sequence value. */ - int mtu; /* Peer's mru */ - int pcomp; /* Does peer accept protocol compression? */ - int accomp; /* Does peer accept addr/ctl compression? */ - u_long lastXMit; /* Time of last transmission. */ - ext_accm inACCM; /* Async-Ctl-Char-Map for input. */ - ext_accm outACCM; /* Async-Ctl-Char-Map for output. */ -#if VJ_SUPPORT > 0 - int vjEnabled; /* Flag indicating VJ compression enabled. */ - struct vjcompress vjComp; /* Van Jabobsen compression header. */ -#endif - - struct netif netif; - - struct ppp_addrs addrs; - - void (*linkStatusCB)(void *ctx, int errCode, void *arg); - void *linkStatusCtx; - -} PPPControl; - - -/* - * Ioctl definitions. - */ - -struct npioctl { - int protocol; /* PPP procotol, e.g. PPP_IP */ - enum NPmode mode; -}; - - - -/***********************************/ -/*** LOCAL FUNCTION DECLARATIONS ***/ -/***********************************/ -static void pppMain(void *pd); -static void pppDrop(PPPControl *pc); -static void pppInProc(int pd, u_char *s, int l); - - -/******************************/ -/*** PUBLIC DATA STRUCTURES ***/ -/******************************/ -u_long subnetMask; - -static PPPControl pppControl[NUM_PPP]; /* The PPP interface control blocks. */ - -/* - * PPP Data Link Layer "protocol" table. - * One entry per supported protocol. - * The last entry must be NULL. - */ -struct protent *ppp_protocols[] = { - &lcp_protent, -#if PAP_SUPPORT > 0 - &pap_protent, -#endif -#if CHAP_SUPPORT > 0 - &chap_protent, -#endif -#if CBCP_SUPPORT > 0 - &cbcp_protent, -#endif - &ipcp_protent, -#if CCP_SUPPORT > 0 - &ccp_protent, -#endif - NULL -}; - - -/* - * Buffers for outgoing packets. This must be accessed only from the appropriate - * PPP task so that it doesn't need to be protected to avoid collisions. - */ -u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN]; - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ - -/* - * FCS lookup table as calculated by genfcstab. - */ -static const u_short fcstab[256] = { - 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, - 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, - 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, - 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, - 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd, - 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5, - 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c, - 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974, - 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb, - 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, - 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, - 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72, - 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9, - 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1, - 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738, - 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70, - 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7, - 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff, - 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036, - 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e, - 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5, - 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd, - 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134, - 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c, - 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3, - 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb, - 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232, - 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a, - 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1, - 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9, - 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330, - 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78 -}; - -/* PPP's Asynchronous-Control-Character-Map. The mask array is used - * to select the specific bit for a character. */ -static u_char pppACCMMask[] = { - 0x01, - 0x02, - 0x04, - 0x08, - 0x10, - 0x20, - 0x40, - 0x80 -}; - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* Initialize the PPP subsystem. */ - -struct ppp_settings ppp_settings; - -void pppInit(void) -{ - struct protent *protp; - int i, j; - - memset(&ppp_settings, 0, sizeof(ppp_settings)); - ppp_settings.usepeerdns = 1; - pppSetAuth(PPPAUTHTYPE_NONE, NULL, NULL); - - magicInit(); - - for (i = 0; i < NUM_PPP; i++) { - pppControl[i].openFlag = 0; - - subnetMask = htonl(0xffffff00); - - /* - * Initialize to the standard option set. - */ - for (j = 0; (protp = ppp_protocols[j]) != NULL; ++j) - (*protp->init)(i); - } - -#if LINK_STATS - /* Clear the statistics. */ - memset(&lwip_stats.link, 0, sizeof(lwip_stats.link)); -#endif -} - -void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd) -{ - switch(authType) { - case PPPAUTHTYPE_NONE: - default: -#ifdef LWIP_PPP_STRICT_PAP_REJECT - ppp_settings.refuse_pap = 1; -#else - /* some providers request pap and accept an empty login/pw */ - ppp_settings.refuse_pap = 0; -#endif - ppp_settings.refuse_chap = 1; - break; - case PPPAUTHTYPE_ANY: -/* Warning: Using PPPAUTHTYPE_ANY might have security consequences. - * RFC 1994 says: - * - * In practice, within or associated with each PPP server, there is a - * database which associates "user" names with authentication - * information ("secrets"). It is not anticipated that a particular - * named user would be authenticated by multiple methods. This would - * make the user vulnerable to attacks which negotiate the least secure - * method from among a set (such as PAP rather than CHAP). If the same - * secret was used, PAP would reveal the secret to be used later with - * CHAP. - * - * Instead, for each user name there should be an indication of exactly - * one method used to authenticate that user name. If a user needs to - * make use of different authentication methods under different - * circumstances, then distinct user names SHOULD be employed, each of - * which identifies exactly one authentication method. - * - */ - ppp_settings.refuse_pap = 0; - ppp_settings.refuse_chap = 0; - break; - case PPPAUTHTYPE_PAP: - ppp_settings.refuse_pap = 0; - ppp_settings.refuse_chap = 1; - break; - case PPPAUTHTYPE_CHAP: - ppp_settings.refuse_pap = 1; - ppp_settings.refuse_chap = 0; - break; - } - - if(user) { - strncpy(ppp_settings.user, user, sizeof(ppp_settings.user)-1); - ppp_settings.user[sizeof(ppp_settings.user)-1] = '\0'; - } else - ppp_settings.user[0] = '\0'; - - if(passwd) { - strncpy(ppp_settings.passwd, passwd, sizeof(ppp_settings.passwd)-1); - ppp_settings.passwd[sizeof(ppp_settings.passwd)-1] = '\0'; - } else - ppp_settings.passwd[0] = '\0'; -} - -/* Open a new PPP connection using the given I/O device. - * This initializes the PPP control block but does not - * attempt to negotiate the LCP session. If this port - * connects to a modem, the modem connection must be - * established before calling this. - * Return a new PPP connection descriptor on success or - * an error code (negative) on failure. */ -int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx) -{ - PPPControl *pc; - int pd; - - /* Find a free PPP session descriptor. Critical region? */ - for (pd = 0; pd < NUM_PPP && pppControl[pd].openFlag != 0; pd++); - if (pd >= NUM_PPP) - pd = PPPERR_OPEN; - else - pppControl[pd].openFlag = !0; - - /* Launch a deamon thread. */ - if (pd >= 0) { - - pppControl[pd].openFlag = 1; - - lcp_init(pd); - pc = &pppControl[pd]; - pc->fd = fd; - pc->kill_link = 0; - pc->sig_hup = 0; - pc->if_up = 0; - pc->errCode = 0; - pc->inState = PDIDLE; - pc->inHead = NULL; - pc->inTail = NULL; - pc->inEscaped = 0; - pc->lastXMit = 0; - -#if VJ_SUPPORT > 0 - pc->vjEnabled = 0; - vj_compress_init(&pc->vjComp); -#endif - - /* - * Default the in and out accm so that escape and flag characters - * are always escaped. - */ - memset(pc->inACCM, 0, sizeof(ext_accm)); - pc->inACCM[15] = 0x60; - memset(pc->outACCM, 0, sizeof(ext_accm)); - pc->outACCM[15] = 0x60; - - pc->linkStatusCB = linkStatusCB; - pc->linkStatusCtx = linkStatusCtx; - - if( sys_thread_new(pppMain, (void*)pd, PPP_THREAD_PRIO) != SYS_THREAD_NULL ) - { - if(!linkStatusCB) { - while(pd >= 0 && !pc->if_up) { - sys_msleep(500); - if (lcp_phase[pd] == PHASE_DEAD) { - pppClose(pd); - if (pc->errCode) - pd = pc->errCode; - else - pd = PPPERR_CONNECT; - } - } - } - } - else - { - pc->openFlag = 0; - pd = PPPERR_ALLOC; - } - } - return pd; -} - -/* Close a PPP connection and release the descriptor. - * Any outstanding packets in the queues are dropped. - * Return 0 on success, an error code on failure. */ -int pppClose(int pd) -{ - PPPControl *pc = &pppControl[pd]; - int st = 0; - - /* Disconnect */ - pc->kill_link = !0; - pppMainWakeup(pd); - - if(!pc->linkStatusCB) { - while(st >= 0 && lcp_phase[pd] != PHASE_DEAD) { - sys_msleep(500); - break; - } - } - return st; -} - -/* This function is called when carrier is lost on the PPP channel. */ -void pppSigHUP(int pd) -{ - PPPControl *pc = &pppControl[pd]; - - pc->sig_hup = 1; - pppMainWakeup(pd); -} - -static void nPut(PPPControl *pc, struct pbuf *nb) -{ - struct pbuf *b; - int c; - - for(b = nb; b != NULL; b = b->next) { - if((c = sio_write(pc->fd, b->payload, b->len)) != b->len) { - PPPDEBUG((LOG_WARNING, - "PPP nPut: incomplete sio_write(%d,, %u) = %d\n", pc->fd, b->len, c)); -#if LINK_STATS - lwip_stats.link.err++; -#endif /* LINK_STATS */ - pc->lastXMit = 0; /* prepend PPP_FLAG to next packet */ - break; - } - } - pbuf_free(nb); - -#if LINK_STATS - lwip_stats.link.xmit++; -#endif /* LINK_STATS */ -} - -/* - * pppAppend - append given character to end of given pbuf. If outACCM - * is not NULL and the character needs to be escaped, do so. - * If pbuf is full, append another. - * Return the current pbuf. - */ -static struct pbuf *pppAppend(u_char c, struct pbuf *nb, ext_accm *outACCM) -{ - struct pbuf *tb = nb; - - /* Make sure there is room for the character and an escape code. - * Sure we don't quite fill the buffer if the character doesn't - * get escaped but is one character worth complicating this? */ - /* Note: We assume no packet header. */ - if (nb && (PBUF_POOL_BUFSIZE - nb->len) < 2) { - tb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); - if (tb) { - nb->next = tb; - } -#if LINK_STATS - else { - lwip_stats.link.memerr++; - } -#endif /* LINK_STATS */ - nb = tb; - } - if (nb) { - if (outACCM && ESCAPE_P(*outACCM, c)) { - *((u_char*)nb->payload + nb->len++) = PPP_ESCAPE; - *((u_char*)nb->payload + nb->len++) = c ^ PPP_TRANS; - } - else - *((u_char*)nb->payload + nb->len++) = c; - } - - return tb; -} - -/* Send a packet on the given connection. */ -static err_t pppifOutput(struct netif *netif, struct pbuf *pb, struct ip_addr *ipaddr) -{ - int pd = (int)netif->state; - u_short protocol = PPP_IP; - PPPControl *pc = &pppControl[pd]; - u_int fcsOut = PPP_INITFCS; - struct pbuf *headMB = NULL, *tailMB = NULL, *p; - u_char c; - - (void)ipaddr; - - /* Validate parameters. */ - /* We let any protocol value go through - it can't hurt us - * and the peer will just drop it if it's not accepting it. */ - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag || !pb) { - PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad parms prot=%d pb=%p\n", - pd, protocol, pb)); -#if LINK_STATS - lwip_stats.link.opterr++; - lwip_stats.link.drop++; -#endif - return ERR_ARG; - } - - /* Check that the link is up. */ - if (lcp_phase[pd] == PHASE_DEAD) { - PPPDEBUG((LOG_ERR, "pppifOutput[%d]: link not up\n", pd)); -#if LINK_STATS - lwip_stats.link.rterr++; - lwip_stats.link.drop++; -#endif - return ERR_RTE; - } - - /* Grab an output buffer. */ - headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); - if (headMB == NULL) { - PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: first alloc fail\n", pd)); -#if LINK_STATS - lwip_stats.link.memerr++; - lwip_stats.link.drop++; -#endif /* LINK_STATS */ - return ERR_MEM; - } - -#if VJ_SUPPORT > 0 - /* - * Attempt Van Jacobson header compression if VJ is configured and - * this is an IP packet. - */ - if (protocol == PPP_IP && pc->vjEnabled) { - switch (vj_compress_tcp(&pc->vjComp, pb)) { - case TYPE_IP: - /* No change... - protocol = PPP_IP_PROTOCOL; - */ - break; - case TYPE_COMPRESSED_TCP: - protocol = PPP_VJC_COMP; - break; - case TYPE_UNCOMPRESSED_TCP: - protocol = PPP_VJC_UNCOMP; - break; - default: - PPPDEBUG((LOG_WARNING, "pppifOutput[%d]: bad IP packet\n", pd)); -#if LINK_STATS - lwip_stats.link.proterr++; - lwip_stats.link.drop++; -#endif - pbuf_free(headMB); - return ERR_VAL; - } - } -#endif - - tailMB = headMB; - - /* Build the PPP header. */ - if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) - tailMB = pppAppend(PPP_FLAG, tailMB, NULL); - pc->lastXMit = sys_jiffies(); - if (!pc->accomp) { - fcsOut = PPP_FCS(fcsOut, PPP_ALLSTATIONS); - tailMB = pppAppend(PPP_ALLSTATIONS, tailMB, &pc->outACCM); - fcsOut = PPP_FCS(fcsOut, PPP_UI); - tailMB = pppAppend(PPP_UI, tailMB, &pc->outACCM); - } - if (!pc->pcomp || protocol > 0xFF) { - c = (protocol >> 8) & 0xFF; - fcsOut = PPP_FCS(fcsOut, c); - tailMB = pppAppend(c, tailMB, &pc->outACCM); - } - c = protocol & 0xFF; - fcsOut = PPP_FCS(fcsOut, c); - tailMB = pppAppend(c, tailMB, &pc->outACCM); - - /* Load packet. */ - for(p = pb; p; p = p->next) { - int n; - u_char *sPtr; - - sPtr = (u_char*)p->payload; - n = p->len; - while (n-- > 0) { - c = *sPtr++; - - /* Update FCS before checking for special characters. */ - fcsOut = PPP_FCS(fcsOut, c); - - /* Copy to output buffer escaping special characters. */ - tailMB = pppAppend(c, tailMB, &pc->outACCM); - } - } - - /* Add FCS and trailing flag. */ - c = ~fcsOut & 0xFF; - tailMB = pppAppend(c, tailMB, &pc->outACCM); - c = (~fcsOut >> 8) & 0xFF; - tailMB = pppAppend(c, tailMB, &pc->outACCM); - tailMB = pppAppend(PPP_FLAG, tailMB, NULL); - - /* If we failed to complete the packet, throw it away. */ - if (!tailMB) { - PPPDEBUG((LOG_WARNING, - "pppifOutput[%d]: Alloc err - dropping proto=%d\n", - pd, protocol)); - pbuf_free(headMB); -#if LINK_STATS - lwip_stats.link.memerr++; - lwip_stats.link.drop++; -#endif - return ERR_MEM; - } - - /* Send it. */ - PPPDEBUG((LOG_INFO, "pppifOutput[%d]: proto=0x%04X\n", pd, protocol)); - - nPut(pc, headMB); - - return ERR_OK; -} - -/* Get and set parameters for the given connection. - * Return 0 on success, an error code on failure. */ -int pppIOCtl(int pd, int cmd, void *arg) -{ - PPPControl *pc = &pppControl[pd]; - int st = 0; - - if (pd < 0 || pd >= NUM_PPP) - st = PPPERR_PARAM; - else { - switch(cmd) { - case PPPCTLG_UPSTATUS: /* Get the PPP up status. */ - if (arg) - *(int *)arg = (int)(pc->if_up); - else - st = PPPERR_PARAM; - break; - case PPPCTLS_ERRCODE: /* Set the PPP error code. */ - if (arg) - pc->errCode = *(int *)arg; - else - st = PPPERR_PARAM; - break; - case PPPCTLG_ERRCODE: /* Get the PPP error code. */ - if (arg) - *(int *)arg = (int)(pc->errCode); - else - st = PPPERR_PARAM; - break; - case PPPCTLG_FD: - if (arg) - *(sio_fd_t *)arg = pc->fd; - else - st = PPPERR_PARAM; - break; - default: - st = PPPERR_PARAM; - break; - } - } - - return st; -} - -/* - * Return the Maximum Transmission Unit for the given PPP connection. - */ -u_int pppMTU(int pd) -{ - PPPControl *pc = &pppControl[pd]; - u_int st; - - /* Validate parameters. */ - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) - st = 0; - else - st = pc->mtu; - - return st; -} - -/* - * Write n characters to a ppp link. - * RETURN: >= 0 Number of characters written - * -1 Failed to write to device - */ -int pppWrite(int pd, const u_char *s, int n) -{ - PPPControl *pc = &pppControl[pd]; - u_char c; - u_int fcsOut = PPP_INITFCS; - struct pbuf *headMB = NULL, *tailMB; - headMB = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); - if (headMB == NULL) { -#if LINK_STATS - lwip_stats.link.memerr++; - lwip_stats.link.proterr++; -#endif /* LINK_STATS */ - return PPPERR_ALLOC; - } - - tailMB = headMB; - - /* If the link has been idle, we'll send a fresh flag character to - * flush any noise. */ - if ((sys_jiffies() - pc->lastXMit) >= PPP_MAXIDLEFLAG) - tailMB = pppAppend(PPP_FLAG, tailMB, NULL); - pc->lastXMit = sys_jiffies(); - - /* Load output buffer. */ - while (n-- > 0) { - c = *s++; - - /* Update FCS before checking for special characters. */ - fcsOut = PPP_FCS(fcsOut, c); - - /* Copy to output buffer escaping special characters. */ - tailMB = pppAppend(c, tailMB, &pc->outACCM); - } - - /* Add FCS and trailing flag. */ - c = ~fcsOut & 0xFF; - tailMB = pppAppend(c, tailMB, &pc->outACCM); - c = (~fcsOut >> 8) & 0xFF; - tailMB = pppAppend(c, tailMB, &pc->outACCM); - tailMB = pppAppend(PPP_FLAG, tailMB, NULL); - - /* If we failed to complete the packet, throw it away. - * Otherwise send it. */ - if (!tailMB) { - PPPDEBUG((LOG_WARNING, - "pppWrite[%d]: Alloc err - dropping pbuf len=%d\n", pd, headMB->len)); -/* "pppWrite[%d]: Alloc err - dropping %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */ - pbuf_free(headMB); -#if LINK_STATS - lwip_stats.link.memerr++; - lwip_stats.link.proterr++; -#endif /* LINK_STATS */ - return PPPERR_ALLOC; - } - - PPPDEBUG((LOG_INFO, "pppWrite[%d]: len=%d\n", pd, headMB->len)); -/* "pppWrite[%d]: %d:%.*H", pd, headMB->len, LWIP_MIN(headMB->len * 2, 40), headMB->payload)); */ - nPut(pc, headMB); - - return PPPERR_NONE; -} - -/* - * ppp_send_config - configure the transmit characteristics of - * the ppp interface. - */ -void ppp_send_config( - int unit, - int mtu, - u32_t asyncmap, - int pcomp, - int accomp -) -{ - PPPControl *pc = &pppControl[unit]; - int i; - - pc->mtu = mtu; - pc->pcomp = pcomp; - pc->accomp = accomp; - - /* Load the ACCM bits for the 32 control codes. */ - for (i = 0; i < 32/8; i++) - pc->outACCM[i] = (u_char)((asyncmap >> (8 * i)) & 0xFF); - PPPDEBUG((LOG_INFO, "ppp_send_config[%d]: outACCM=%X %X %X %X\n", - unit, - pc->outACCM[0], pc->outACCM[1], pc->outACCM[2], pc->outACCM[3])); -} - - -/* - * ppp_set_xaccm - set the extended transmit ACCM for the interface. - */ -void ppp_set_xaccm(int unit, ext_accm *accm) -{ - memcpy(pppControl[unit].outACCM, accm, sizeof(ext_accm)); - PPPDEBUG((LOG_INFO, "ppp_set_xaccm[%d]: outACCM=%X %X %X %X\n", - unit, - pppControl[unit].outACCM[0], - pppControl[unit].outACCM[1], - pppControl[unit].outACCM[2], - pppControl[unit].outACCM[3])); -} - - -/* - * ppp_recv_config - configure the receive-side characteristics of - * the ppp interface. - */ -void ppp_recv_config( - int unit, - int mru, - u32_t asyncmap, - int pcomp, - int accomp -) -{ - PPPControl *pc = &pppControl[unit]; - int i; - - (void)accomp; - (void)pcomp; - (void)mru; - - /* Load the ACCM bits for the 32 control codes. */ - for (i = 0; i < 32 / 8; i++) - pc->inACCM[i] = (u_char)(asyncmap >> (i * 8)); - PPPDEBUG((LOG_INFO, "ppp_recv_config[%d]: inACCM=%X %X %X %X\n", - unit, - pc->inACCM[0], pc->inACCM[1], pc->inACCM[2], pc->inACCM[3])); -} - -#if 0 -/* - * ccp_test - ask kernel whether a given compression method - * is acceptable for use. Returns 1 if the method and parameters - * are OK, 0 if the method is known but the parameters are not OK - * (e.g. code size should be reduced), or -1 if the method is unknown. - */ -int ccp_test( - int unit, - int opt_len, - int for_transmit, - u_char *opt_ptr -) -{ - return 0; /* XXX Currently no compression. */ -} - -/* - * ccp_flags_set - inform kernel about the current state of CCP. - */ -void ccp_flags_set(int unit, int isopen, int isup) -{ - /* XXX */ -} - -/* - * ccp_fatal_error - returns 1 if decompression was disabled as a - * result of an error detected after decompression of a packet, - * 0 otherwise. This is necessary because of patent nonsense. - */ -int ccp_fatal_error(int unit) -{ - /* XXX */ - return 0; -} -#endif - -/* - * get_idle_time - return how long the link has been idle. - */ -int get_idle_time(int u, struct ppp_idle *ip) -{ - /* XXX */ - (void)u; - (void)ip; - - return 0; -} - - -/* - * Return user specified netmask, modified by any mask we might determine - * for address `addr' (in network byte order). - * Here we scan through the system's list of interfaces, looking for - * any non-point-to-point interfaces which might appear to be on the same - * network as `addr'. If we find any, we OR in their netmask to the - * user-specified netmask. - */ -u32_t GetMask(u32_t addr) -{ - u32_t mask, nmask; - - htonl(addr); - if (IN_CLASSA(addr)) /* determine network mask for address class */ - nmask = IN_CLASSA_NET; - else if (IN_CLASSB(addr)) - nmask = IN_CLASSB_NET; - else - nmask = IN_CLASSC_NET; - /* class D nets are disallowed by bad_ip_adrs */ - mask = subnetMask | htonl(nmask); - - /* XXX - * Scan through the system's network interfaces. - * Get each netmask and OR them into our mask. - */ - - return mask; -} - -/* - * sifvjcomp - config tcp header compression - */ -int sifvjcomp( - int pd, - int vjcomp, - int cidcomp, - int maxcid -) -{ -#if VJ_SUPPORT > 0 - PPPControl *pc = &pppControl[pd]; - - pc->vjEnabled = vjcomp; - pc->vjComp.compressSlot = cidcomp; - pc->vjComp.maxSlotIndex = maxcid; - PPPDEBUG((LOG_INFO, "sifvjcomp: VJ compress enable=%d slot=%d max slot=%d\n", - vjcomp, cidcomp, maxcid)); -#endif - - return 0; -} - -/* - * pppifNetifInit - netif init callback - */ -static err_t pppifNetifInit(struct netif *netif) -{ - netif->name[0] = 'p'; - netif->name[1] = 'p'; - netif->output = pppifOutput; - netif->mtu = pppMTU((int)netif->state); - return ERR_OK; -} - - -/* - * sifup - Config the interface up and enable IP packets to pass. - */ -int sifup(int pd) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); - } else { - netif_remove(&pc->netif); - if (netif_add(&pc->netif, &pc->addrs.our_ipaddr, &pc->addrs.netmask, &pc->addrs.his_ipaddr, (void *)pd, pppifNetifInit, ip_input)) { - pc->if_up = 1; - pc->errCode = PPPERR_NONE; - /* bug #16602 */ - netif_set_up( &pc->netif ); - - PPPDEBUG((LOG_DEBUG, "sifup: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); - if(pc->linkStatusCB) - pc->linkStatusCB(pc->linkStatusCtx, pc->errCode, &pc->addrs); - } else { - st = 0; - PPPDEBUG((LOG_ERR, "sifup[%d]: netif_add failed\n", pd)); - } - } - - return st; -} - -/* - * sifnpmode - Set the mode for handling packets for a given NP. - */ -int sifnpmode(int u, int proto, enum NPmode mode) -{ - (void)u; - (void)proto; - (void)mode; - return 0; -} - -/* - * sifdown - Config the interface down and disable IP. - */ -int sifdown(int pd) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifdown[%d]: bad parms\n", pd)); - } else { - pc->if_up = 0; - netif_remove(&pc->netif); - PPPDEBUG((LOG_DEBUG, "sifdown: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); - if(pc->linkStatusCB) - pc->linkStatusCB(pc->linkStatusCtx, PPPERR_CONNECT, NULL); - } - return st; -} - -/* - * sifaddr - Config the interface IP addresses and netmask. - */ -int sifaddr( - int pd, /* Interface unit ??? */ - u32_t o, /* Our IP address ??? */ - u32_t h, /* His IP address ??? */ - u32_t m, /* IP subnet mask ??? */ - u32_t ns1, /* Primary DNS */ - u32_t ns2 /* Secondary DNS */ -) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); - } else { - memcpy(&pc->addrs.our_ipaddr, &o, sizeof(o)); - memcpy(&pc->addrs.his_ipaddr, &h, sizeof(h)); - memcpy(&pc->addrs.netmask, &m, sizeof(m)); - memcpy(&pc->addrs.dns1, &ns1, sizeof(ns1)); - memcpy(&pc->addrs.dns2, &ns2, sizeof(ns2)); - } - return st; -} - -/* - * cifaddr - Clear the interface IP addresses, and delete routes - * through the interface if possible. - */ -int cifaddr( - int pd, /* Interface unit ??? */ - u32_t o, /* Our IP address ??? */ - u32_t h /* IP broadcast address ??? */ -) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - (void)o; - (void)h; - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); - } else { - IP4_ADDR(&pc->addrs.our_ipaddr, 0,0,0,0); - IP4_ADDR(&pc->addrs.his_ipaddr, 0,0,0,0); - IP4_ADDR(&pc->addrs.netmask, 255,255,255,0); - IP4_ADDR(&pc->addrs.dns1, 0,0,0,0); - IP4_ADDR(&pc->addrs.dns2, 0,0,0,0); - } - return st; -} - -/* - * sifdefaultroute - assign a default route through the address given. - */ -int sifdefaultroute(int pd, u32_t l, u32_t g) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - (void)l; - (void)g; - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); - } else { - netif_set_default(&pc->netif); - } - - /* TODO: check how PPP handled the netMask, previously not set by ipSetDefault */ - - return st; -} - -/* - * cifdefaultroute - delete a default route through the address given. - */ -int cifdefaultroute(int pd, u32_t l, u32_t g) -{ - PPPControl *pc = &pppControl[pd]; - int st = 1; - - (void)l; - (void)g; - if (pd < 0 || pd >= NUM_PPP || !pc->openFlag) { - st = 0; - PPPDEBUG((LOG_WARNING, "sifup[%d]: bad parms\n", pd)); - } else { - netif_set_default(NULL); - } - - return st; -} - -void -pppMainWakeup(int pd) -{ - PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d\n", pd)); - sio_read_abort( pppControl[pd].fd ); -} - -/* these callbacks are necessary because lcp_* functions - must be called in the same context as pppInput(), - namely the tcpip_thread(), essentially because - they manipulate timeouts which are thread-private -*/ - -static void -pppStartCB(void *arg) -{ - int pd = (int)arg; - - PPPDEBUG((LOG_DEBUG, "pppStartCB: unit %d\n", pd)); - lcp_lowerup(pd); - lcp_open(pd); /* Start protocol */ -} - -static void -pppStopCB(void *arg) -{ - int pd = (int)arg; - - PPPDEBUG((LOG_DEBUG, "pppStopCB: unit %d\n", pd)); - lcp_close(pd, "User request"); -} - -static void -pppHupCB(void *arg) -{ - int pd = (int)arg; - - PPPDEBUG((LOG_DEBUG, "pppHupCB: unit %d\n", pd)); - lcp_lowerdown(pd); - link_terminated(pd); -} -/**********************************/ -/*** LOCAL FUNCTION DEFINITIONS ***/ -/**********************************/ -/* The main PPP process function. This implements the state machine according - * to section 4 of RFC 1661: The Point-To-Point Protocol. */ -static void pppMain(void *arg) -{ - err_t err; - int pd = (int)arg; - struct pbuf *p; - PPPControl* pc; - - pc = &pppControl[pd]; - - p = pbuf_alloc(PBUF_RAW, PPP_MRU+PPP_HDRLEN, PBUF_RAM); - if(!p) { - LWIP_ASSERT("p != NULL", p); - pc->errCode = PPPERR_ALLOC; - goto out; - } - - /* - * Start the connection and handle incoming events (packet or timeout). - */ - PPPDEBUG((LOG_INFO, "pppMain: unit %d: Connecting\n", pd)); - err = tcpip_callback(pppStartCB, arg); - LWIP_ASSERT( "pppMain: can't install callback handler\n", err == ERR_OK ); - while (lcp_phase[pd] != PHASE_DEAD) { - if (pc->kill_link) { - PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d kill_link -> pppStopCB\n", pd)); - pc->errCode = PPPERR_USER; - /* This will leave us at PHASE_DEAD. */ - tcpip_callback(pppStopCB, arg); - pc->kill_link = 0; - } - else if (pc->sig_hup) { - PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sig_hup -> pppHupCB\n", pd)); - pc->sig_hup = 0; - tcpip_callback(pppHupCB, arg); - } else { - int c = sio_read(pc->fd, p->payload, p->len); - if(c > 0) { - pppInProc(pd, p->payload, c); - } else { - /* PPPDEBUG((LOG_DEBUG, "pppMainWakeup: unit %d sio_read len=%d returned %d\n", pd, p->len, c)); */ - } - } - } - PPPDEBUG((LOG_INFO, "pppMain: unit %d: PHASE_DEAD\n", pd)); - pppDrop(pc); - pbuf_free(p); - -out: - PPPDEBUG((LOG_DEBUG, "pppMain: unit %d: linkStatusCB=%lx errCode=%d\n", pd, pc->linkStatusCB, pc->errCode)); - if(pc->linkStatusCB) - pc->linkStatusCB(pc->linkStatusCtx, pc->errCode ? pc->errCode : PPPERR_PROTOCOL, NULL); - - pc->openFlag = 0; - - /* Remove this thread from the running ones. */ - sys_arch_thread_remove( sys_arch_thread_current( ) ); - LWIP_ASSERT( "pppMain: sys_arch_thread_remove did return\n", 0 ); -} - -static struct pbuf *pppSingleBuf(struct pbuf *p) -{ - struct pbuf *q, *b; - u_char *pl; - - if(p->tot_len == p->len) - return p; - - q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); - if(!q) { - PPPDEBUG((LOG_ERR, - "pppSingleBuf: unable to alloc new buf (%d)\n", p->tot_len)); - return p; /* live dangerously */ - } - - for(b = p, pl = q->payload; b != NULL; b = b->next) { - memcpy(pl, b->payload, b->len); - pl += b->len; - } - - pbuf_free(p); - - return q; -} - -struct pppInputHeader { - int unit; - u16_t proto; -}; - -/* - * Pass the processed input packet to the appropriate handler. - * This function and all handlers run in the context of the tcpip_thread - */ -static void pppInput(void *arg) -{ - struct pbuf *nb = (struct pbuf *)arg; - u16_t protocol; - int pd; - - pd = ((struct pppInputHeader *)nb->payload)->unit; - protocol = ((struct pppInputHeader *)nb->payload)->proto; - - pbuf_header(nb, -(int)sizeof(struct pppInputHeader)); - -#if LINK_STATS - lwip_stats.link.recv++; -#endif /* LINK_STATS */ - - /* - * Toss all non-LCP packets unless LCP is OPEN. - * Until we get past the authentication phase, toss all packets - * except LCP, LQR and authentication packets. - */ - if((lcp_phase[pd] <= PHASE_AUTHENTICATE) && (protocol != PPP_LCP)) { - if(!((protocol == PPP_LQR) || (protocol == PPP_PAP) || (protocol == PPP_CHAP)) || - (lcp_phase[pd] != PHASE_AUTHENTICATE)) { - PPPDEBUG((LOG_INFO, "pppInput: discarding proto 0x%04X in phase %d\n", protocol, lcp_phase[pd])); - goto drop; - } - } - - switch(protocol) { - case PPP_VJC_COMP: /* VJ compressed TCP */ -#if VJ_SUPPORT > 0 - PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_comp in pbuf len=%d\n", pd, nb->len)); - /* - * Clip off the VJ header and prepend the rebuilt TCP/IP header and - * pass the result to IP. - */ - if (vj_uncompress_tcp(&nb, &pppControl[pd].vjComp) >= 0) { - pppControl[pd].netif.input(nb, &pppControl[pd].netif); - return; - } - /* Something's wrong so drop it. */ - PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ compressed\n", pd)); -#else - /* No handler for this protocol so drop the packet. */ - PPPDEBUG((LOG_INFO, "pppInput[%d]: drop VJ Comp in %d:%s\n", pd, nb->len, nb->payload)); -#endif /* VJ_SUPPORT > 0 */ - break; - case PPP_VJC_UNCOMP: /* VJ uncompressed TCP */ -#if VJ_SUPPORT > 0 - PPPDEBUG((LOG_INFO, "pppInput[%d]: vj_un in pbuf len=%d\n", pd, nb->len)); - /* - * Process the TCP/IP header for VJ header compression and then pass - * the packet to IP. - */ - if (vj_uncompress_uncomp(nb, &pppControl[pd].vjComp) >= 0) { - pppControl[pd].netif.input(nb, &pppControl[pd].netif); - return; - } - /* Something's wrong so drop it. */ - PPPDEBUG((LOG_WARNING, "pppInput[%d]: Dropping VJ uncompressed\n", pd)); -#else - /* No handler for this protocol so drop the packet. */ - PPPDEBUG((LOG_INFO, - "pppInput[%d]: drop VJ UnComp in %d:.*H\n", - pd, nb->len, LWIP_MIN(nb->len * 2, 40), nb->payload)); -#endif /* VJ_SUPPORT > 0 */ - break; - case PPP_IP: /* Internet Protocol */ - PPPDEBUG((LOG_INFO, "pppInput[%d]: ip in pbuf len=%d\n", pd, nb->len)); - pppControl[pd].netif.input(nb, &pppControl[pd].netif); - return; - default: - { - struct protent *protp; - int i; - - /* - * Upcall the proper protocol input routine. - */ - for (i = 0; (protp = ppp_protocols[i]) != NULL; ++i) { - if (protp->protocol == protocol && protp->enabled_flag) { - PPPDEBUG((LOG_INFO, "pppInput[%d]: %s len=%d\n", pd, protp->name, nb->len)); - nb = pppSingleBuf(nb); - (*protp->input)(pd, nb->payload, nb->len); - goto out; - } - } - - /* No handler for this protocol so reject the packet. */ - PPPDEBUG((LOG_INFO, "pppInput[%d]: rejecting unsupported proto 0x%04X len=%d\n", pd, protocol, nb->len)); - pbuf_header(nb, sizeof(protocol)); -#if BYTE_ORDER == LITTLE_ENDIAN - protocol = htons(protocol); - memcpy(nb->payload, &protocol, sizeof(protocol)); -#endif - lcp_sprotrej(pd, nb->payload, nb->len); - } - break; - } - -drop: -#if LINK_STATS - lwip_stats.link.drop++; -#endif - -out: - pbuf_free(nb); - return; -} - - -/* - * Drop the input packet. - */ -static void pppDrop(PPPControl *pc) -{ - if (pc->inHead != NULL) { -#if 0 - PPPDEBUG((LOG_INFO, "pppDrop: %d:%.*H\n", pc->inHead->len, min(60, pc->inHead->len * 2), pc->inHead->payload)); -#endif - PPPDEBUG((LOG_INFO, "pppDrop: pbuf len=%d\n", pc->inHead->len)); - if (pc->inTail && (pc->inTail != pc->inHead)) - pbuf_free(pc->inTail); - pbuf_free(pc->inHead); - pc->inHead = NULL; - pc->inTail = NULL; - } -#if VJ_SUPPORT > 0 - vj_uncompress_err(&pc->vjComp); -#endif - -#if LINK_STATS - lwip_stats.link.drop++; -#endif /* LINK_STATS */ -} - - -/* - * Process a received octet string. - */ -static void pppInProc(int pd, u_char *s, int l) -{ - PPPControl *pc = &pppControl[pd]; - struct pbuf *nextNBuf; - u_char curChar; - - PPPDEBUG((LOG_DEBUG, "pppInProc[%d]: got %d bytes\n", pd, l)); - while (l-- > 0) { - curChar = *s++; - - /* Handle special characters. */ - if (ESCAPE_P(pc->inACCM, curChar)) { - /* Check for escape sequences. */ - /* XXX Note that this does not handle an escaped 0x5d character which - * would appear as an escape character. Since this is an ASCII ']' - * and there is no reason that I know of to escape it, I won't complicate - * the code to handle this case. GLL */ - if (curChar == PPP_ESCAPE) - pc->inEscaped = 1; - /* Check for the flag character. */ - else if (curChar == PPP_FLAG) { - /* If this is just an extra flag character, ignore it. */ - if (pc->inState <= PDADDRESS) - ; - /* If we haven't received the packet header, drop what has come in. */ - else if (pc->inState < PDDATA) { - PPPDEBUG((LOG_WARNING, - "pppInProc[%d]: Dropping incomplete packet %d\n", - pd, pc->inState)); -#if LINK_STATS - lwip_stats.link.lenerr++; -#endif - pppDrop(pc); - } - /* If the fcs is invalid, drop the packet. */ - else if (pc->inFCS != PPP_GOODFCS) { - PPPDEBUG((LOG_INFO, - "pppInProc[%d]: Dropping bad fcs 0x%04X proto=0x%04X\n", - pd, pc->inFCS, pc->inProtocol)); -#if LINK_STATS - lwip_stats.link.chkerr++; -#endif - pppDrop(pc); - } - /* Otherwise it's a good packet so pass it on. */ - else { - - /* Trim off the checksum. */ - if(pc->inTail->len >= 2) { - pc->inTail->len -= 2; - - pc->inTail->tot_len = pc->inTail->len; - if (pc->inTail != pc->inHead) { - pbuf_cat(pc->inHead, pc->inTail); - } - } else { - pc->inTail->tot_len = pc->inTail->len; - if (pc->inTail != pc->inHead) { - pbuf_cat(pc->inHead, pc->inTail); - } - - pbuf_realloc(pc->inHead, pc->inHead->tot_len - 2); - } - - /* Dispatch the packet thereby consuming it. */ - if(tcpip_callback(pppInput, pc->inHead) != ERR_OK) { - PPPDEBUG((LOG_ERR, - "pppInProc[%d]: tcpip_callback() failed, dropping packet\n", pd)); - pbuf_free(pc->inHead); -#if LINK_STATS - lwip_stats.link.drop++; -#endif - } - pc->inHead = NULL; - pc->inTail = NULL; - } - - /* Prepare for a new packet. */ - pc->inFCS = PPP_INITFCS; - pc->inState = PDADDRESS; - pc->inEscaped = 0; - } - /* Other characters are usually control characters that may have - * been inserted by the physical layer so here we just drop them. */ - else { - PPPDEBUG((LOG_WARNING, - "pppInProc[%d]: Dropping ACCM char <%d>\n", pd, curChar)); - } - } - /* Process other characters. */ - else { - /* Unencode escaped characters. */ - if (pc->inEscaped) { - pc->inEscaped = 0; - curChar ^= PPP_TRANS; - } - - /* Process character relative to current state. */ - switch(pc->inState) { - case PDIDLE: /* Idle state - waiting. */ - /* Drop the character if it's not 0xff - * we would have processed a flag character above. */ - if (curChar != PPP_ALLSTATIONS) { - break; - } - - /* Fall through */ - case PDSTART: /* Process start flag. */ - /* Prepare for a new packet. */ - pc->inFCS = PPP_INITFCS; - - /* Fall through */ - case PDADDRESS: /* Process address field. */ - if (curChar == PPP_ALLSTATIONS) { - pc->inState = PDCONTROL; - break; - } - /* Else assume compressed address and control fields so - * fall through to get the protocol... */ - case PDCONTROL: /* Process control field. */ - /* If we don't get a valid control code, restart. */ - if (curChar == PPP_UI) { - pc->inState = PDPROTOCOL1; - break; - } -#if 0 - else { - PPPDEBUG((LOG_WARNING, - "pppInProc[%d]: Invalid control <%d>\n", pd, curChar)); - pc->inState = PDSTART; - } -#endif - case PDPROTOCOL1: /* Process protocol field 1. */ - /* If the lower bit is set, this is the end of the protocol - * field. */ - if (curChar & 1) { - pc->inProtocol = curChar; - pc->inState = PDDATA; - } - else { - pc->inProtocol = (u_int)curChar << 8; - pc->inState = PDPROTOCOL2; - } - break; - case PDPROTOCOL2: /* Process protocol field 2. */ - pc->inProtocol |= curChar; - pc->inState = PDDATA; - break; - case PDDATA: /* Process data byte. */ - /* Make space to receive processed data. */ - if (pc->inTail == NULL || pc->inTail->len == PBUF_POOL_BUFSIZE) { - if(pc->inTail) { - pc->inTail->tot_len = pc->inTail->len; - if (pc->inTail != pc->inHead) { - pbuf_cat(pc->inHead, pc->inTail); - } - } - /* If we haven't started a packet, we need a packet header. */ - nextNBuf = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); - if (nextNBuf == NULL) { - /* No free buffers. Drop the input packet and let the - * higher layers deal with it. Continue processing - * the received pbuf chain in case a new packet starts. */ - PPPDEBUG((LOG_ERR, "pppInProc[%d]: NO FREE MBUFS!\n", pd)); -#if LINK_STATS - lwip_stats.link.memerr++; -#endif /* LINK_STATS */ - pppDrop(pc); - pc->inState = PDSTART; /* Wait for flag sequence. */ - break; - } - if (pc->inHead == NULL) { - struct pppInputHeader *pih = nextNBuf->payload; - - pih->unit = pd; - pih->proto = pc->inProtocol; - - nextNBuf->len += sizeof(*pih); - - pc->inHead = nextNBuf; - } - pc->inTail = nextNBuf; - } - /* Load character into buffer. */ - ((u_char*)pc->inTail->payload)[pc->inTail->len++] = curChar; - break; - } - - /* update the frame check sequence number. */ - pc->inFCS = PPP_FCS(pc->inFCS, curChar); - } - } - avRandomize(); -} - -#endif /* PPP_SUPPORT */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/ppp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/ppp.h deleted file mode 100644 index dbe12171e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/ppp.h +++ /dev/null @@ -1,446 +0,0 @@ -/***************************************************************************** -* ppp.h - Network Point to Point Protocol header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1997 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 97-11-05 Guy Lancaster , Global Election Systems Inc. -* Original derived from BSD codes. -*****************************************************************************/ - -#ifndef PPP_H -#define PPP_H - -#include "lwip/opt.h" - -#if PPP_SUPPORT > 0 -#include "lwip/sio.h" -#include "lwip/api.h" -#include "lwip/sockets.h" -#include "lwip/stats.h" -#include "lwip/mem.h" -#include "lwip/tcpip.h" -#include "lwip/netif.h" - -/* - * pppd.h - PPP daemon global declarations. - * - * Copyright (c) 1989 Carnegie Mellon University. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by Carnegie Mellon University. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - */ -/* - * ppp_defs.h - PPP definitions. - * - * Copyright (c) 1994 The Australian National University. - * All rights reserved. - * - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, provided that the above copyright - * notice appears in all copies. This software is provided without any - * warranty, express or implied. The Australian National University - * makes no representations about the suitability of this software for - * any purpose. - * - * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY - * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES - * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF - * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS - * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO - * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, - * OR MODIFICATIONS. - */ - -#define TIMEOUT(f, a, t) sys_untimeout((f), (a)), sys_timeout((t)*1000, (f), (a)) -#define UNTIMEOUT(f, a) sys_untimeout((f), (a)) - - -# ifndef __u_char_defined - -/* Type definitions for BSD code. */ -typedef unsigned long u_long; -typedef unsigned int u_int; -typedef unsigned short u_short; -typedef unsigned char u_char; - -#endif - -/* - * Constants and structures defined by the internet system, - * Per RFC 790, September 1981, and numerous additions. - */ - -/* - * The basic PPP frame. - */ -#define PPP_HDRLEN 4 /* octets for standard ppp header */ -#define PPP_FCSLEN 2 /* octets for FCS */ - - -/* - * Significant octet values. - */ -#define PPP_ALLSTATIONS 0xff /* All-Stations broadcast address */ -#define PPP_UI 0x03 /* Unnumbered Information */ -#define PPP_FLAG 0x7e /* Flag Sequence */ -#define PPP_ESCAPE 0x7d /* Asynchronous Control Escape */ -#define PPP_TRANS 0x20 /* Asynchronous transparency modifier */ - -/* - * Protocol field values. - */ -#define PPP_IP 0x21 /* Internet Protocol */ -#define PPP_AT 0x29 /* AppleTalk Protocol */ -#define PPP_VJC_COMP 0x2d /* VJ compressed TCP */ -#define PPP_VJC_UNCOMP 0x2f /* VJ uncompressed TCP */ -#define PPP_COMP 0xfd /* compressed packet */ -#define PPP_IPCP 0x8021 /* IP Control Protocol */ -#define PPP_ATCP 0x8029 /* AppleTalk Control Protocol */ -#define PPP_CCP 0x80fd /* Compression Control Protocol */ -#define PPP_LCP 0xc021 /* Link Control Protocol */ -#define PPP_PAP 0xc023 /* Password Authentication Protocol */ -#define PPP_LQR 0xc025 /* Link Quality Report protocol */ -#define PPP_CHAP 0xc223 /* Cryptographic Handshake Auth. Protocol */ -#define PPP_CBCP 0xc029 /* Callback Control Protocol */ - -/* - * Values for FCS calculations. - */ -#define PPP_INITFCS 0xffff /* Initial FCS value */ -#define PPP_GOODFCS 0xf0b8 /* Good final FCS value */ -#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff]) - -/* - * Extended asyncmap - allows any character to be escaped. - */ -typedef u_char ext_accm[32]; - -/* - * What to do with network protocol (NP) packets. - */ -enum NPmode { - NPMODE_PASS, /* pass the packet through */ - NPMODE_DROP, /* silently drop the packet */ - NPMODE_ERROR, /* return an error */ - NPMODE_QUEUE /* save it up for later. */ -}; - -/* - * Inline versions of get/put char/short/long. - * Pointer is advanced; we assume that both arguments - * are lvalues and will already be in registers. - * cp MUST be u_char *. - */ -#define GETCHAR(c, cp) { \ - (c) = *(cp)++; \ -} -#define PUTCHAR(c, cp) { \ - *(cp)++ = (u_char) (c); \ -} - - -#define GETSHORT(s, cp) { \ - (s) = *(cp)++ << 8; \ - (s) |= *(cp)++; \ -} -#define PUTSHORT(s, cp) { \ - *(cp)++ = (u_char) ((s) >> 8); \ - *(cp)++ = (u_char) (s); \ -} - -#define GETLONG(l, cp) { \ - (l) = *(cp)++ << 8; \ - (l) |= *(cp)++; (l) <<= 8; \ - (l) |= *(cp)++; (l) <<= 8; \ - (l) |= *(cp)++; \ -} -#define PUTLONG(l, cp) { \ - *(cp)++ = (u_char) ((l) >> 24); \ - *(cp)++ = (u_char) ((l) >> 16); \ - *(cp)++ = (u_char) ((l) >> 8); \ - *(cp)++ = (u_char) (l); \ -} - - -#define INCPTR(n, cp) ((cp) += (n)) -#define DECPTR(n, cp) ((cp) -= (n)) - -#define BCMP(s0, s1, l) memcmp((u_char *)(s0), (u_char *)(s1), (l)) -#define BCOPY(s, d, l) memcpy((d), (s), (l)) -#define BZERO(s, n) memset(s, 0, n) -#if PPP_DEBUG -#define PRINTMSG(m, l) { m[l] = '\0'; ppp_trace(LOG_INFO, "Remote message: %s\n", m); } -#else -#define PRINTMSG(m, l) -#endif - -/* - * MAKEHEADER - Add PPP Header fields to a packet. - */ -#define MAKEHEADER(p, t) { \ - PUTCHAR(PPP_ALLSTATIONS, p); \ - PUTCHAR(PPP_UI, p); \ - PUTSHORT(t, p); } - -/************************* -*** PUBLIC DEFINITIONS *** -*************************/ - -/* Error codes. */ -#define PPPERR_NONE 0 /* No error. */ -#define PPPERR_PARAM -1 /* Invalid parameter. */ -#define PPPERR_OPEN -2 /* Unable to open PPP session. */ -#define PPPERR_DEVICE -3 /* Invalid I/O device for PPP. */ -#define PPPERR_ALLOC -4 /* Unable to allocate resources. */ -#define PPPERR_USER -5 /* User interrupt. */ -#define PPPERR_CONNECT -6 /* Connection lost. */ -#define PPPERR_AUTHFAIL -7 /* Failed authentication challenge. */ -#define PPPERR_PROTOCOL -8 /* Failed to meet protocol. */ - -/* - * PPP IOCTL commands. - */ -/* - * Get the up status - 0 for down, non-zero for up. The argument must - * point to an int. - */ -#define PPPCTLG_UPSTATUS 100 /* Get the up status - 0 down else up */ -#define PPPCTLS_ERRCODE 101 /* Set the error code */ -#define PPPCTLG_ERRCODE 102 /* Get the error code */ -#define PPPCTLG_FD 103 /* Get the fd associated with the ppp */ - -/************************ -*** PUBLIC DATA TYPES *** -************************/ - -/* - * The following struct gives the addresses of procedures to call - * for a particular protocol. - */ -struct protent { - u_short protocol; /* PPP protocol number */ - /* Initialization procedure */ - void (*init) (int unit); - /* Process a received packet */ - void (*input) (int unit, u_char *pkt, int len); - /* Process a received protocol-reject */ - void (*protrej) (int unit); - /* Lower layer has come up */ - void (*lowerup) (int unit); - /* Lower layer has gone down */ - void (*lowerdown) (int unit); - /* Open the protocol */ - void (*open) (int unit); - /* Close the protocol */ - void (*close) (int unit, char *reason); -#if 0 - /* Print a packet in readable form */ - int (*printpkt) (u_char *pkt, int len, - void (*printer) (void *, char *, ...), - void *arg); - /* Process a received data packet */ - void (*datainput) (int unit, u_char *pkt, int len); -#endif - int enabled_flag; /* 0 iff protocol is disabled */ - char *name; /* Text name of protocol */ -#if 0 - /* Check requested options, assign defaults */ - void (*check_options) (u_long); - /* Configure interface for demand-dial */ - int (*demand_conf) (int unit); - /* Say whether to bring up link for this pkt */ - int (*active_pkt) (u_char *pkt, int len); -#endif -}; - -/* - * The following structure records the time in seconds since - * the last NP packet was sent or received. - */ -struct ppp_idle { - u_short xmit_idle; /* seconds since last NP packet sent */ - u_short recv_idle; /* seconds since last NP packet received */ -}; - -struct ppp_settings { - - u_int disable_defaultip : 1; /* Don't use hostname for default IP addrs */ - u_int auth_required : 1; /* Peer is required to authenticate */ - u_int explicit_remote : 1; /* remote_name specified with remotename opt */ - u_int refuse_pap : 1; /* Don't wanna auth. ourselves with PAP */ - u_int refuse_chap : 1; /* Don't wanna auth. ourselves with CHAP */ - u_int usehostname : 1; /* Use hostname for our_name */ - u_int usepeerdns : 1; /* Ask peer for DNS adds */ - - u_short idle_time_limit; /* Shut down link if idle for this long */ - int maxconnect; /* Maximum connect time (seconds) */ - - char user[MAXNAMELEN + 1];/* Username for PAP */ - char passwd[MAXSECRETLEN + 1]; /* Password for PAP, secret for CHAP */ - char our_name[MAXNAMELEN + 1]; /* Our name for authentication purposes */ - char remote_name[MAXNAMELEN + 1]; /* Peer's name for authentication */ -}; - -struct ppp_addrs { - struct ip_addr our_ipaddr, his_ipaddr, netmask, dns1, dns2; -}; - -/***************************** -*** PUBLIC DATA STRUCTURES *** -*****************************/ -/* Buffers for outgoing packets. */ -extern u_char outpacket_buf[NUM_PPP][PPP_MRU+PPP_HDRLEN]; - -extern struct ppp_settings ppp_settings; - -extern struct protent *ppp_protocols[];/* Table of pointers to supported protocols */ - - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ - -/* Initialize the PPP subsystem. */ -void pppInit(void); - -/* Warning: Using PPPAUTHTYPE_ANY might have security consequences. - * RFC 1994 says: - * - * In practice, within or associated with each PPP server, there is a - * database which associates "user" names with authentication - * information ("secrets"). It is not anticipated that a particular - * named user would be authenticated by multiple methods. This would - * make the user vulnerable to attacks which negotiate the least secure - * method from among a set (such as PAP rather than CHAP). If the same - * secret was used, PAP would reveal the secret to be used later with - * CHAP. - * - * Instead, for each user name there should be an indication of exactly - * one method used to authenticate that user name. If a user needs to - * make use of different authentication methods under different - * circumstances, then distinct user names SHOULD be employed, each of - * which identifies exactly one authentication method. - * - */ -enum pppAuthType { - PPPAUTHTYPE_NONE, - PPPAUTHTYPE_ANY, - PPPAUTHTYPE_PAP, - PPPAUTHTYPE_CHAP -}; - -void pppSetAuth(enum pppAuthType authType, const char *user, const char *passwd); - -/* - * Open a new PPP connection using the given I/O device. - * This initializes the PPP control block but does not - * attempt to negotiate the LCP session. - * Return a new PPP connection descriptor on success or - * an error code (negative) on failure. - */ -int pppOpen(sio_fd_t fd, void (*linkStatusCB)(void *ctx, int errCode, void *arg), void *linkStatusCtx); - -/* - * Close a PPP connection and release the descriptor. - * Any outstanding packets in the queues are dropped. - * Return 0 on success, an error code on failure. - */ -int pppClose(int pd); - -/* - * Indicate to the PPP process that the line has disconnected. - */ -void pppSigHUP(int pd); - -/* - * Get and set parameters for the given connection. - * Return 0 on success, an error code on failure. - */ -int pppIOCtl(int pd, int cmd, void *arg); - -/* - * Return the Maximum Transmission Unit for the given PPP connection. - */ -u_int pppMTU(int pd); - -/* - * Write n characters to a ppp link. - * RETURN: >= 0 Number of characters written - * -1 Failed to write to device - */ -int pppWrite(int pd, const u_char *s, int n); - -void pppMainWakeup(int pd); - -/* Configure i/f transmit parameters */ -void ppp_send_config (int, int, u32_t, int, int); -/* Set extended transmit ACCM */ -void ppp_set_xaccm (int, ext_accm *); -/* Configure i/f receive parameters */ -void ppp_recv_config (int, int, u32_t, int, int); -/* Find out how long link has been idle */ -int get_idle_time (int, struct ppp_idle *); - -/* Configure VJ TCP header compression */ -int sifvjcomp (int, int, int, int); -/* Configure i/f down (for IP) */ -int sifup (int); -/* Set mode for handling packets for proto */ -int sifnpmode (int u, int proto, enum NPmode mode); -/* Configure i/f down (for IP) */ -int sifdown (int); -/* Configure IP addresses for i/f */ -int sifaddr (int, u32_t, u32_t, u32_t, u32_t, u32_t); -/* Reset i/f IP addresses */ -int cifaddr (int, u32_t, u32_t); -/* Create default route through i/f */ -int sifdefaultroute (int, u32_t, u32_t); -/* Delete default route through i/f */ -int cifdefaultroute (int, u32_t, u32_t); - -/* Get appropriate netmask for address */ -u32_t GetMask (u32_t); - -#endif /* PPP_SUPPORT */ - -#endif /* PPP_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/pppdebug.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/pppdebug.h deleted file mode 100644 index de1478cee..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/pppdebug.h +++ /dev/null @@ -1,89 +0,0 @@ -/***************************************************************************** -* pppdebug.h - System debugging utilities. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* portions Copyright (c) 1998 Global Election Systems Inc. -* portions Copyright (c) 2001 by Cognizant Pty Ltd. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY (please don't use tabs!) -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 98-07-29 Guy Lancaster , Global Election Systems Inc. -* Original. -* -***************************************************************************** -*/ -#ifndef PPPDEBUG_H -#define PPPDEBUG_H - -/************************ -*** PUBLIC DATA TYPES *** -************************/ -/* Trace levels. */ -typedef enum { - LOG_CRITICAL = 0, - LOG_ERR = 1, - LOG_NOTICE = 2, - LOG_WARNING = 3, - LOG_INFO = 5, - LOG_DETAIL = 6, - LOG_DEBUG = 7 -} LogCodes; - - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ -/* - * ppp_trace - a form of printf to send tracing information to stderr - */ -void ppp_trace(int level, const char *format,...); - -#if PPP_DEBUG > 0 - -#define AUTHDEBUG(a) ppp_trace a -#define IPCPDEBUG(a) ppp_trace a -#define UPAPDEBUG(a) ppp_trace a -#define LCPDEBUG(a) ppp_trace a -#define FSMDEBUG(a) ppp_trace a -#define CHAPDEBUG(a) ppp_trace a -#define PPPDEBUG(a) ppp_trace a - -#define TRACELCP 1 - -#else - -#define AUTHDEBUG(a) -#define IPCPDEBUG(a) -#define UPAPDEBUG(a) -#define LCPDEBUG(a) -#define FSMDEBUG(a) -#define CHAPDEBUG(a) - -#define PPPDEBUG(a) - -#define TRACELCP 0 - -#endif - -#endif /* PPPDEBUG_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/randm.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/randm.c deleted file mode 100644 index 4f86875de..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/randm.c +++ /dev/null @@ -1,246 +0,0 @@ -/***************************************************************************** -* randm.c - Random number generator program file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* Copyright (c) 1998 by Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 06-08-04 Christian Walter -* Fixed some compiler warnings. -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 98-06-03 Guy Lancaster , Global Election Systems Inc. -* Extracted from avos. -*****************************************************************************/ - -#include - -#include "ppp.h" -#if PPP_SUPPORT > 0 -#include "md5.h" -#include "randm.h" - -#include "pppdebug.h" - - -#if MD5_SUPPORT>0 /* this module depends on MD5 */ -#define RANDPOOLSZ 16 /* Bytes stored in the pool of randomness. */ - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -static char randPool[RANDPOOLSZ]; /* Pool of randomness. */ -static long randCount = 0; /* Pseudo-random incrementer */ - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * Initialize the random number generator. - * - * Since this is to be called on power up, we don't have much - * system randomess to work with. Here all we use is the - * real-time clock. We'll accumulate more randomness as soon - * as things start happening. - */ -void avRandomInit() -{ - avChurnRand(NULL, 0); -} - -/* - * Churn the randomness pool on a random event. Call this early and often - * on random and semi-random system events to build randomness in time for - * usage. For randomly timed events, pass a null pointer and a zero length - * and this will use the system timer and other sources to add randomness. - * If new random data is available, pass a pointer to that and it will be - * included. - * - * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427 - */ -void avChurnRand(char *randData, u32_t randLen) -{ - MD5_CTX md5; - -/* ppp_trace(LOG_INFO, "churnRand: %u@%P\n", randLen, randData); */ - MD5Init(&md5); - MD5Update(&md5, (u_char *)randPool, sizeof(randPool)); - if (randData) - MD5Update(&md5, (u_char *)randData, randLen); - else { - struct { - /* INCLUDE fields for any system sources of randomness */ - char foobar; - } sysData; - - /* Load sysData fields here. */ - ; - MD5Update(&md5, (u_char *)&sysData, sizeof(sysData)); - } - MD5Final((u_char *)randPool, &md5); -/* ppp_trace(LOG_INFO, "churnRand: -> 0\n"); */ -} - -/* - * Use the random pool to generate random data. This degrades to pseudo - * random when used faster than randomness is supplied using churnRand(). - * Note: It's important that there be sufficient randomness in randPool - * before this is called for otherwise the range of the result may be - * narrow enough to make a search feasible. - * - * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427 - * - * XXX Why does he not just call churnRand() for each block? Probably - * so that you don't ever publish the seed which could possibly help - * predict future values. - * XXX Why don't we preserve md5 between blocks and just update it with - * randCount each time? Probably there is a weakness but I wish that - * it was documented. - */ -void avGenRand(char *buf, u32_t bufLen) -{ - MD5_CTX md5; - u_char tmp[16]; - u32_t n; - - while (bufLen > 0) { - n = LWIP_MIN(bufLen, RANDPOOLSZ); - MD5Init(&md5); - MD5Update(&md5, (u_char *)randPool, sizeof(randPool)); - MD5Update(&md5, (u_char *)&randCount, sizeof(randCount)); - MD5Final(tmp, &md5); - randCount++; - memcpy(buf, tmp, n); - buf += n; - bufLen -= n; - } -} - -/* - * Return a new random number. - */ -u32_t avRandom() -{ - u32_t newRand; - - avGenRand((char *)&newRand, sizeof(newRand)); - - return newRand; -} - -#else /* MD5_SUPPORT */ - - -/*****************************/ -/*** LOCAL DATA STRUCTURES ***/ -/*****************************/ -static int avRandomized = 0; /* Set when truely randomized. */ -static u32_t avRandomSeed = 0; /* Seed used for random number generation. */ - - -/***********************************/ -/*** PUBLIC FUNCTION DEFINITIONS ***/ -/***********************************/ -/* - * Initialize the random number generator. - * - * Here we attempt to compute a random number seed but even if - * it isn't random, we'll randomize it later. - * - * The current method uses the fields from the real time clock, - * the idle process counter, the millisecond counter, and the - * hardware timer tick counter. When this is invoked - * in startup(), then the idle counter and timer values may - * repeat after each boot and the real time clock may not be - * operational. Thus we call it again on the first random - * event. - */ -void avRandomInit() -{ -#if 0 - /* Get a pointer into the last 4 bytes of clockBuf. */ - u32_t *lptr1 = (u32_t *)((char *)&clockBuf[3]); - - /* - * Initialize our seed using the real-time clock, the idle - * counter, the millisecond timer, and the hardware timer - * tick counter. The real-time clock and the hardware - * tick counter are the best sources of randomness but - * since the tick counter is only 16 bit (and truncated - * at that), the idle counter and millisecond timer - * (which may be small values) are added to help - * randomize the lower 16 bits of the seed. - */ - readClk(); - avRandomSeed += *(u32_t *)clockBuf + *lptr1 + OSIdleCtr - + ppp_mtime() + ((u32_t)TM1 << 16) + TM1; -#else - avRandomSeed += sys_jiffies(); /* XXX */ -#endif - - /* Initialize the Borland random number generator. */ - srand((unsigned)avRandomSeed); -} - -/* - * Randomize our random seed value. Here we use the fact that - * this function is called at *truely random* times by the polling - * and network functions. Here we only get 16 bits of new random - * value but we use the previous value to randomize the other 16 - * bits. - */ -void avRandomize(void) -{ - static u32_t last_jiffies; - - if (!avRandomized) { - avRandomized = !0; - avRandomInit(); - /* The initialization function also updates the seed. */ - } else { -/* avRandomSeed += (avRandomSeed << 16) + TM1; */ - avRandomSeed += (sys_jiffies() - last_jiffies); /* XXX */ - } - last_jiffies = sys_jiffies(); -} - -/* - * Return a new random number. - * Here we use the Borland rand() function to supply a pseudo random - * number which we make truely random by combining it with our own - * seed which is randomized by truely random events. - * Thus the numbers will be truely random unless there have been no - * operator or network events in which case it will be pseudo random - * seeded by the real time clock. - */ -u32_t avRandom() -{ - return ((((u32_t)rand() << 16) + rand()) + avRandomSeed); -} - - - -#endif /* MD5_SUPPORT */ -#endif /* PPP_SUPPORT */ - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/randm.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/randm.h deleted file mode 100644 index baa42f0c2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/randm.h +++ /dev/null @@ -1,81 +0,0 @@ -/***************************************************************************** -* randm.h - Random number generator header file. -* -* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. -* Copyright (c) 1998 Global Election Systems Inc. -* -* The authors hereby grant permission to use, copy, modify, distribute, -* and license this software and its documentation for any purpose, provided -* that existing copyright notices are retained in all copies and that this -* notice and the following disclaimer are included verbatim in any -* distributions. No written agreement, license, or royalty fee is required -* for any of the authorized uses. -* -* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR -* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -****************************************************************************** -* REVISION HISTORY -* -* 03-01-01 Marc Boucher -* Ported to lwIP. -* 98-05-29 Guy Lancaster , Global Election Systems Inc. -* Extracted from avos. -*****************************************************************************/ - -#ifndef RANDM_H -#define RANDM_H - -/*********************** -*** PUBLIC FUNCTIONS *** -***********************/ -/* - * Initialize the random number generator. - */ -void avRandomInit(void); - -/* - * Churn the randomness pool on a random event. Call this early and often - * on random and semi-random system events to build randomness in time for - * usage. For randomly timed events, pass a null pointer and a zero length - * and this will use the system timer and other sources to add randomness. - * If new random data is available, pass a pointer to that and it will be - * included. - */ -void avChurnRand(char *randData, u32_t randLen); - -/* - * Randomize our random seed value. To be called for truely random events - * such as user operations and network traffic. - */ -#if MD5_SUPPORT -#define avRandomize() avChurnRand(NULL, 0) -#else -void avRandomize(void); -#endif - -/* - * Use the random pool to generate random data. This degrades to pseudo - * random when used faster than randomness is supplied using churnRand(). - * Thus it's important to make sure that the results of this are not - * published directly because one could predict the next result to at - * least some degree. Also, it's important to get a good seed before - * the first use. - */ -void avGenRand(char *buf, u32_t bufLen); - -/* - * Return a new random number. - */ -u32_t avRandom(void); - - -#endif /* RANDM_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/vj.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/vj.c deleted file mode 100644 index 0636ee11b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/vj.c +++ /dev/null @@ -1,633 +0,0 @@ -/* - * Routines to compress and uncompess tcp packets (for transmission - * over low speed serial lines. - * - * Copyright (c) 1989 Regents of the University of California. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by the University of California, Berkeley. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989: - * - Initial distribution. - * - * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au, - * so that the entire packet being decompressed doesn't have - * to be in contiguous memory (just the compressed header). - * - * Modified March 1998 by Guy Lancaster, glanca@gesn.com, - * for a 16 bit processor. - */ - -#include - -#include "ppp.h" -#include "vj.h" -#include "pppdebug.h" - -#if VJ_SUPPORT > 0 - -#if LINK_STATS -#define INCR(counter) ++comp->stats.counter -#else -#define INCR(counter) -#endif - -#if defined(NO_CHAR_BITFIELDS) -#define getip_hl(base) ((base).ip_hl_v&0xf) -#define getth_off(base) (((base).th_x2_off&0xf0)>>4) -#else -#define getip_hl(base) ((base).ip_hl) -#define getth_off(base) ((base).th_off) -#endif - -void vj_compress_init(struct vjcompress *comp) -{ - register u_int i; - register struct cstate *tstate = comp->tstate; - -#if MAX_SLOTS == 0 - memset((char *)comp, 0, sizeof(*comp)); -#endif - comp->maxSlotIndex = MAX_SLOTS - 1; - comp->compressSlot = 0; /* Disable slot ID compression by default. */ - for (i = MAX_SLOTS - 1; i > 0; --i) { - tstate[i].cs_id = i; - tstate[i].cs_next = &tstate[i - 1]; - } - tstate[0].cs_next = &tstate[MAX_SLOTS - 1]; - tstate[0].cs_id = 0; - comp->last_cs = &tstate[0]; - comp->last_recv = 255; - comp->last_xmit = 255; - comp->flags = VJF_TOSS; -} - - -/* ENCODE encodes a number that is known to be non-zero. ENCODEZ - * checks for zero (since zero has to be encoded in the long, 3 byte - * form). - */ -#define ENCODE(n) { \ - if ((u_short)(n) >= 256) { \ - *cp++ = 0; \ - cp[1] = (n); \ - cp[0] = (n) >> 8; \ - cp += 2; \ - } else { \ - *cp++ = (n); \ - } \ -} -#define ENCODEZ(n) { \ - if ((u_short)(n) >= 256 || (u_short)(n) == 0) { \ - *cp++ = 0; \ - cp[1] = (n); \ - cp[0] = (n) >> 8; \ - cp += 2; \ - } else { \ - *cp++ = (n); \ - } \ -} - -#define DECODEL(f) { \ - if (*cp == 0) {\ - u32_t tmp = ntohl(f) + ((cp[1] << 8) | cp[2]); \ - (f) = htonl(tmp); \ - cp += 3; \ - } else { \ - u32_t tmp = ntohl(f) + (u32_t)*cp++; \ - (f) = htonl(tmp); \ - } \ -} - -#define DECODES(f) { \ - if (*cp == 0) {\ - u_short tmp = ntohs(f) + (((u_short)cp[1] << 8) | cp[2]); \ - (f) = htons(tmp); \ - cp += 3; \ - } else { \ - u_short tmp = ntohs(f) + (u_short)*cp++; \ - (f) = htons(tmp); \ - } \ -} - -#define DECODEU(f) { \ - if (*cp == 0) {\ - (f) = htons(((u_short)cp[1] << 8) | cp[2]); \ - cp += 3; \ - } else { \ - (f) = htons((u_short)*cp++); \ - } \ -} - -/* - * vj_compress_tcp - Attempt to do Van Jacobsen header compression on a - * packet. This assumes that nb and comp are not null and that the first - * buffer of the chain contains a valid IP header. - * Return the VJ type code indicating whether or not the packet was - * compressed. - */ -u_int vj_compress_tcp( - struct vjcompress *comp, - struct pbuf *pb -) -{ - register struct ip *ip = (struct ip *)pb->payload; - register struct cstate *cs = comp->last_cs->cs_next; - register u_short hlen = getip_hl(*ip); - register struct tcphdr *oth; - register struct tcphdr *th; - register u_short deltaS, deltaA; - register u_long deltaL; - register u_int changes = 0; - u_char new_seq[16]; - register u_char *cp = new_seq; - - /* - * Check that the packet is IP proto TCP. - */ - if (ip->ip_p != IPPROTO_TCP) - return (TYPE_IP); - - /* - * Bail if this is an IP fragment or if the TCP packet isn't - * `compressible' (i.e., ACK isn't set or some other control bit is - * set). - */ - if ((ip->ip_off & htons(0x3fff)) || pb->tot_len < 40) - return (TYPE_IP); - th = (struct tcphdr *)&((long *)ip)[hlen]; - if ((th->th_flags & (TCP_SYN|TCP_FIN|TCP_RST|TCP_ACK)) != TCP_ACK) - return (TYPE_IP); - - /* - * Packet is compressible -- we're going to send either a - * COMPRESSED_TCP or UNCOMPRESSED_TCP packet. Either way we need - * to locate (or create) the connection state. Special case the - * most recently used connection since it's most likely to be used - * again & we don't have to do any reordering if it's used. - */ - INCR(vjs_packets); - if (ip->ip_src.s_addr != cs->cs_ip.ip_src.s_addr - || ip->ip_dst.s_addr != cs->cs_ip.ip_dst.s_addr - || *(long *)th != ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) { - /* - * Wasn't the first -- search for it. - * - * States are kept in a circularly linked list with - * last_cs pointing to the end of the list. The - * list is kept in lru order by moving a state to the - * head of the list whenever it is referenced. Since - * the list is short and, empirically, the connection - * we want is almost always near the front, we locate - * states via linear search. If we don't find a state - * for the datagram, the oldest state is (re-)used. - */ - register struct cstate *lcs; - register struct cstate *lastcs = comp->last_cs; - - do { - lcs = cs; cs = cs->cs_next; - INCR(vjs_searches); - if (ip->ip_src.s_addr == cs->cs_ip.ip_src.s_addr - && ip->ip_dst.s_addr == cs->cs_ip.ip_dst.s_addr - && *(long *)th == ((long *)&cs->cs_ip)[getip_hl(cs->cs_ip)]) - goto found; - } while (cs != lastcs); - - /* - * Didn't find it -- re-use oldest cstate. Send an - * uncompressed packet that tells the other side what - * connection number we're using for this conversation. - * Note that since the state list is circular, the oldest - * state points to the newest and we only need to set - * last_cs to update the lru linkage. - */ - INCR(vjs_misses); - comp->last_cs = lcs; - hlen += getth_off(*th); - hlen <<= 2; - /* Check that the IP/TCP headers are contained in the first buffer. */ - if (hlen > pb->len) - return (TYPE_IP); - goto uncompressed; - - found: - /* - * Found it -- move to the front on the connection list. - */ - if (cs == lastcs) - comp->last_cs = lcs; - else { - lcs->cs_next = cs->cs_next; - cs->cs_next = lastcs->cs_next; - lastcs->cs_next = cs; - } - } - - oth = (struct tcphdr *)&((long *)&cs->cs_ip)[hlen]; - deltaS = hlen; - hlen += getth_off(*th); - hlen <<= 2; - /* Check that the IP/TCP headers are contained in the first buffer. */ - if (hlen > pb->len) { - PPPDEBUG((LOG_INFO, "vj_compress_tcp: header len %d spans buffers\n", - hlen)); - return (TYPE_IP); - } - - /* - * Make sure that only what we expect to change changed. The first - * line of the `if' checks the IP protocol version, header length & - * type of service. The 2nd line checks the "Don't fragment" bit. - * The 3rd line checks the time-to-live and protocol (the protocol - * check is unnecessary but costless). The 4th line checks the TCP - * header length. The 5th line checks IP options, if any. The 6th - * line checks TCP options, if any. If any of these things are - * different between the previous & current datagram, we send the - * current datagram `uncompressed'. - */ - if (((u_short *)ip)[0] != ((u_short *)&cs->cs_ip)[0] - || ((u_short *)ip)[3] != ((u_short *)&cs->cs_ip)[3] - || ((u_short *)ip)[4] != ((u_short *)&cs->cs_ip)[4] - || getth_off(*th) != getth_off(*oth) - || (deltaS > 5 && BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2)) - || (getth_off(*th) > 5 && BCMP(th + 1, oth + 1, (getth_off(*th) - 5) << 2))) - goto uncompressed; - - /* - * Figure out which of the changing fields changed. The - * receiver expects changes in the order: urgent, window, - * ack, seq (the order minimizes the number of temporaries - * needed in this section of code). - */ - if (th->th_flags & TCP_URG) { - deltaS = ntohs(th->th_urp); - ENCODEZ(deltaS); - changes |= NEW_U; - } else if (th->th_urp != oth->th_urp) - /* argh! URG not set but urp changed -- a sensible - * implementation should never do this but RFC793 - * doesn't prohibit the change so we have to deal - * with it. */ - goto uncompressed; - - if ((deltaS = (u_short)(ntohs(th->th_win) - ntohs(oth->th_win))) != 0) { - ENCODE(deltaS); - changes |= NEW_W; - } - - if ((deltaL = ntohl(th->th_ack) - ntohl(oth->th_ack)) != 0) { - if (deltaL > 0xffff) - goto uncompressed; - deltaA = (u_short)deltaL; - ENCODE(deltaA); - changes |= NEW_A; - } - - if ((deltaL = ntohl(th->th_seq) - ntohl(oth->th_seq)) != 0) { - if (deltaL > 0xffff) - goto uncompressed; - deltaS = (u_short)deltaL; - ENCODE(deltaS); - changes |= NEW_S; - } - - switch(changes) { - - case 0: - /* - * Nothing changed. If this packet contains data and the - * last one didn't, this is probably a data packet following - * an ack (normal on an interactive connection) and we send - * it compressed. Otherwise it's probably a retransmit, - * retransmitted ack or window probe. Send it uncompressed - * in case the other side missed the compressed version. - */ - if (ip->ip_len != cs->cs_ip.ip_len && - ntohs(cs->cs_ip.ip_len) == hlen) - break; - - /* (fall through) */ - - case SPECIAL_I: - case SPECIAL_D: - /* - * actual changes match one of our special case encodings -- - * send packet uncompressed. - */ - goto uncompressed; - - case NEW_S|NEW_A: - if (deltaS == deltaA && deltaS == ntohs(cs->cs_ip.ip_len) - hlen) { - /* special case for echoed terminal traffic */ - changes = SPECIAL_I; - cp = new_seq; - } - break; - - case NEW_S: - if (deltaS == ntohs(cs->cs_ip.ip_len) - hlen) { - /* special case for data xfer */ - changes = SPECIAL_D; - cp = new_seq; - } - break; - } - - deltaS = (u_short)(ntohs(ip->ip_id) - ntohs(cs->cs_ip.ip_id)); - if (deltaS != 1) { - ENCODEZ(deltaS); - changes |= NEW_I; - } - if (th->th_flags & TCP_PSH) - changes |= TCP_PUSH_BIT; - /* - * Grab the cksum before we overwrite it below. Then update our - * state with this packet's header. - */ - deltaA = ntohs(th->th_sum); - BCOPY(ip, &cs->cs_ip, hlen); - - /* - * We want to use the original packet as our compressed packet. - * (cp - new_seq) is the number of bytes we need for compressed - * sequence numbers. In addition we need one byte for the change - * mask, one for the connection id and two for the tcp checksum. - * So, (cp - new_seq) + 4 bytes of header are needed. hlen is how - * many bytes of the original packet to toss so subtract the two to - * get the new packet size. - */ - deltaS = (u_short)(cp - new_seq); - if (!comp->compressSlot || comp->last_xmit != cs->cs_id) { - comp->last_xmit = cs->cs_id; - hlen -= deltaS + 4; - pbuf_header(pb, -hlen); - cp = (u_char *)pb->payload; - *cp++ = changes | NEW_C; - *cp++ = cs->cs_id; - } else { - hlen -= deltaS + 3; - pbuf_header(pb, -hlen); - cp = (u_char *)pb->payload; - *cp++ = changes; - } - *cp++ = deltaA >> 8; - *cp++ = deltaA; - BCOPY(new_seq, cp, deltaS); - INCR(vjs_compressed); - return (TYPE_COMPRESSED_TCP); - - /* - * Update connection state cs & send uncompressed packet (that is, - * a regular ip/tcp packet but with the 'conversation id' we hope - * to use on future compressed packets in the protocol field). - */ -uncompressed: - BCOPY(ip, &cs->cs_ip, hlen); - ip->ip_p = cs->cs_id; - comp->last_xmit = cs->cs_id; - return (TYPE_UNCOMPRESSED_TCP); -} - -/* - * Called when we may have missed a packet. - */ -void vj_uncompress_err(struct vjcompress *comp) -{ - comp->flags |= VJF_TOSS; - INCR(vjs_errorin); -} - -/* - * "Uncompress" a packet of type TYPE_UNCOMPRESSED_TCP. - * Return 0 on success, -1 on failure. - */ -int vj_uncompress_uncomp( - struct pbuf *nb, - struct vjcompress *comp -) -{ - register u_int hlen; - register struct cstate *cs; - register struct ip *ip; - - ip = (struct ip *)nb->payload; - hlen = getip_hl(*ip) << 2; - if (ip->ip_p >= MAX_SLOTS - || hlen + sizeof(struct tcphdr) > nb->len - || (hlen += getth_off(*((struct tcphdr *)&((char *)ip)[hlen])) << 2) - > nb->len - || hlen > MAX_HDR) { - PPPDEBUG((LOG_INFO, "vj_uncompress_uncomp: bad cid=%d, hlen=%d buflen=%d\n", - ip->ip_p, hlen, nb->len)); - comp->flags |= VJF_TOSS; - INCR(vjs_errorin); - return -1; - } - cs = &comp->rstate[comp->last_recv = ip->ip_p]; - comp->flags &=~ VJF_TOSS; - ip->ip_p = IPPROTO_TCP; - BCOPY(ip, &cs->cs_ip, hlen); - cs->cs_hlen = hlen; - INCR(vjs_uncompressedin); - return 0; -} - -/* - * Uncompress a packet of type TYPE_COMPRESSED_TCP. - * The packet is composed of a buffer chain and the first buffer - * must contain an accurate chain length. - * The first buffer must include the entire compressed TCP/IP header. - * This procedure replaces the compressed header with the uncompressed - * header and returns the length of the VJ header. - */ -int vj_uncompress_tcp( - struct pbuf **nb, - struct vjcompress *comp -) -{ - u_char *cp; - struct tcphdr *th; - struct cstate *cs; - u_short *bp; - struct pbuf *n0 = *nb; - u32_t tmp; - u_int vjlen, hlen, changes; - - INCR(vjs_compressedin); - cp = (u_char *)n0->payload; - changes = *cp++; - if (changes & NEW_C) { - /* - * Make sure the state index is in range, then grab the state. - * If we have a good state index, clear the 'discard' flag. - */ - if (*cp >= MAX_SLOTS) { - PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: bad cid=%d\n", *cp)); - goto bad; - } - - comp->flags &=~ VJF_TOSS; - comp->last_recv = *cp++; - } else { - /* - * this packet has an implicit state index. If we've - * had a line error since the last time we got an - * explicit state index, we have to toss the packet. - */ - if (comp->flags & VJF_TOSS) { - PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: tossing\n")); - INCR(vjs_tossed); - return (-1); - } - } - cs = &comp->rstate[comp->last_recv]; - hlen = getip_hl(cs->cs_ip) << 2; - th = (struct tcphdr *)&((u_char *)&cs->cs_ip)[hlen]; - th->th_sum = htons((*cp << 8) | cp[1]); - cp += 2; - if (changes & TCP_PUSH_BIT) - th->th_flags |= TCP_PSH; - else - th->th_flags &=~ TCP_PSH; - - switch (changes & SPECIALS_MASK) { - case SPECIAL_I: - { - register u32_t i = ntohs(cs->cs_ip.ip_len) - cs->cs_hlen; - /* some compilers can't nest inline assembler.. */ - tmp = ntohl(th->th_ack) + i; - th->th_ack = htonl(tmp); - tmp = ntohl(th->th_seq) + i; - th->th_seq = htonl(tmp); - } - break; - - case SPECIAL_D: - /* some compilers can't nest inline assembler.. */ - tmp = ntohl(th->th_seq) + ntohs(cs->cs_ip.ip_len) - cs->cs_hlen; - th->th_seq = htonl(tmp); - break; - - default: - if (changes & NEW_U) { - th->th_flags |= TCP_URG; - DECODEU(th->th_urp); - } else - th->th_flags &=~ TCP_URG; - if (changes & NEW_W) - DECODES(th->th_win); - if (changes & NEW_A) - DECODEL(th->th_ack); - if (changes & NEW_S) - DECODEL(th->th_seq); - break; - } - if (changes & NEW_I) { - DECODES(cs->cs_ip.ip_id); - } else { - cs->cs_ip.ip_id = ntohs(cs->cs_ip.ip_id) + 1; - cs->cs_ip.ip_id = htons(cs->cs_ip.ip_id); - } - - /* - * At this point, cp points to the first byte of data in the - * packet. Fill in the IP total length and update the IP - * header checksum. - */ - vjlen = (u_short)(cp - (u_char*)n0->payload); - if (n0->len < vjlen) { - /* - * We must have dropped some characters (crc should detect - * this but the old slip framing won't) - */ - PPPDEBUG((LOG_INFO, "vj_uncompress_tcp: head buffer %d too short %d\n", - n0->len, vjlen)); - goto bad; - } - -#if BYTE_ORDER == LITTLE_ENDIAN - tmp = n0->tot_len - vjlen + cs->cs_hlen; - cs->cs_ip.ip_len = htons(tmp); -#else - cs->cs_ip.ip_len = htons(n0->tot_len - vjlen + cs->cs_hlen); -#endif - - /* recompute the ip header checksum */ - bp = (u_short *) &cs->cs_ip; - cs->cs_ip.ip_sum = 0; - for (tmp = 0; hlen > 0; hlen -= 2) - tmp += *bp++; - tmp = (tmp & 0xffff) + (tmp >> 16); - tmp = (tmp & 0xffff) + (tmp >> 16); - cs->cs_ip.ip_sum = (u_short)(~tmp); - - /* Remove the compressed header and prepend the uncompressed header. */ - pbuf_header(n0, -vjlen); - - if(MEM_ALIGN(n0->payload) != n0->payload) { - struct pbuf *np, *q; - u8_t *bufptr; - - np = pbuf_alloc(PBUF_RAW, n0->len + cs->cs_hlen, PBUF_POOL); - if(!np) { - PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: realign failed\n")); - *nb = NULL; - goto bad; - } - - pbuf_header(np, -cs->cs_hlen); - - bufptr = n0->payload; - for(q = np; q != NULL; q = q->next) { - memcpy(q->payload, bufptr, q->len); - bufptr += q->len; - } - - if(n0->next) { - pbuf_chain(np, n0->next); - pbuf_dechain(n0); - } - pbuf_free(n0); - n0 = np; - } - - if(pbuf_header(n0, cs->cs_hlen)) { - struct pbuf *np; - - LWIP_ASSERT("vj_uncompress_tcp: cs->cs_hlen <= PBUF_POOL_BUFSIZE", cs->cs_hlen <= PBUF_POOL_BUFSIZE); - np = pbuf_alloc(PBUF_RAW, cs->cs_hlen, PBUF_POOL); - if(!np) { - PPPDEBUG((LOG_WARNING, "vj_uncompress_tcp: prepend failed\n")); - *nb = NULL; - goto bad; - } - pbuf_cat(np, n0); - n0 = np; - } - LWIP_ASSERT("n0->len >= cs->cs_hlen", n0->len >= cs->cs_hlen); - memcpy(n0->payload, &cs->cs_ip, cs->cs_hlen); - - *nb = n0; - - return vjlen; - -bad: - comp->flags |= VJF_TOSS; - INCR(vjs_errorin); - return (-1); -} - -#endif - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/vj.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/vj.h deleted file mode 100644 index 252d0f5aa..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/vj.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Definitions for tcp compression routines. - * - * $Id$ - * - * Copyright (c) 1989 Regents of the University of California. - * All rights reserved. - * - * Redistribution and use in source and binary forms are permitted - * provided that the above copyright notice and this paragraph are - * duplicated in all such forms and that any documentation, - * advertising materials, and other materials related to such - * distribution and use acknowledge that the software was developed - * by the University of California, Berkeley. The name of the - * University may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989: - * - Initial distribution. - */ - -#ifndef VJ_H -#define VJ_H - -#include "vjbsdhdr.h" - -#define MAX_SLOTS 16 /* must be > 2 and < 256 */ -#define MAX_HDR 128 - -/* - * Compressed packet format: - * - * The first octet contains the packet type (top 3 bits), TCP - * 'push' bit, and flags that indicate which of the 4 TCP sequence - * numbers have changed (bottom 5 bits). The next octet is a - * conversation number that associates a saved IP/TCP header with - * the compressed packet. The next two octets are the TCP checksum - * from the original datagram. The next 0 to 15 octets are - * sequence number changes, one change per bit set in the header - * (there may be no changes and there are two special cases where - * the receiver implicitly knows what changed -- see below). - * - * There are 5 numbers which can change (they are always inserted - * in the following order): TCP urgent pointer, window, - * acknowlegement, sequence number and IP ID. (The urgent pointer - * is different from the others in that its value is sent, not the - * change in value.) Since typical use of SLIP links is biased - * toward small packets (see comments on MTU/MSS below), changes - * use a variable length coding with one octet for numbers in the - * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the - * range 256 - 65535 or 0. (If the change in sequence number or - * ack is more than 65535, an uncompressed packet is sent.) - */ - -/* - * Packet types (must not conflict with IP protocol version) - * - * The top nibble of the first octet is the packet type. There are - * three possible types: IP (not proto TCP or tcp with one of the - * control flags set); uncompressed TCP (a normal IP/TCP packet but - * with the 8-bit protocol field replaced by an 8-bit connection id -- - * this type of packet syncs the sender & receiver); and compressed - * TCP (described above). - * - * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and - * is logically part of the 4-bit "changes" field that follows. Top - * three bits are actual packet type. For backward compatibility - * and in the interest of conserving bits, numbers are chosen so the - * IP protocol version number (4) which normally appears in this nibble - * means "IP packet". - */ - -/* packet types */ -#define TYPE_IP 0x40 -#define TYPE_UNCOMPRESSED_TCP 0x70 -#define TYPE_COMPRESSED_TCP 0x80 -#define TYPE_ERROR 0x00 - -/* Bits in first octet of compressed packet */ -#define NEW_C 0x40 /* flag bits for what changed in a packet */ -#define NEW_I 0x20 -#define NEW_S 0x08 -#define NEW_A 0x04 -#define NEW_W 0x02 -#define NEW_U 0x01 - -/* reserved, special-case values of above */ -#define SPECIAL_I (NEW_S|NEW_W|NEW_U) /* echoed interactive traffic */ -#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U) /* unidirectional data */ -#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U) - -#define TCP_PUSH_BIT 0x10 - - -/* - * "state" data for each active tcp conversation on the wire. This is - * basically a copy of the entire IP/TCP header from the last packet - * we saw from the conversation together with a small identifier - * the transmit & receive ends of the line use to locate saved header. - */ -struct cstate { - struct cstate *cs_next; /* next most recently used state (xmit only) */ - u_short cs_hlen; /* size of hdr (receive only) */ - u_char cs_id; /* connection # associated with this state */ - u_char cs_filler; - union { - char csu_hdr[MAX_HDR]; - struct ip csu_ip; /* ip/tcp hdr from most recent packet */ - } vjcs_u; -}; -#define cs_ip vjcs_u.csu_ip -#define cs_hdr vjcs_u.csu_hdr - - -struct vjstat { - unsigned long vjs_packets; /* outbound packets */ - unsigned long vjs_compressed; /* outbound compressed packets */ - unsigned long vjs_searches; /* searches for connection state */ - unsigned long vjs_misses; /* times couldn't find conn. state */ - unsigned long vjs_uncompressedin; /* inbound uncompressed packets */ - unsigned long vjs_compressedin; /* inbound compressed packets */ - unsigned long vjs_errorin; /* inbound unknown type packets */ - unsigned long vjs_tossed; /* inbound packets tossed because of error */ -}; - -/* - * all the state data for one serial line (we need one of these per line). - */ -struct vjcompress { - struct cstate *last_cs; /* most recently used tstate */ - u_char last_recv; /* last rcvd conn. id */ - u_char last_xmit; /* last sent conn. id */ - u_short flags; - u_char maxSlotIndex; - u_char compressSlot; /* Flag indicating OK to compress slot ID. */ -#if LINK_STATS - struct vjstat stats; -#endif - struct cstate tstate[MAX_SLOTS]; /* xmit connection states */ - struct cstate rstate[MAX_SLOTS]; /* receive connection states */ -}; - -/* flag values */ -#define VJF_TOSS 1U /* tossing rcvd frames because of input err */ - -extern void vj_compress_init (struct vjcompress *comp); -extern u_int vj_compress_tcp (struct vjcompress *comp, struct pbuf *pb); -extern void vj_uncompress_err (struct vjcompress *comp); -extern int vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp); -extern int vj_uncompress_tcp(struct pbuf **nb, struct vjcompress *comp); - -#endif /* VJ_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/vjbsdhdr.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/vjbsdhdr.h deleted file mode 100644 index a089352ad..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/ppp/vjbsdhdr.h +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef VJBSDHDR_H -#define VJBSDHDR_H - -#include "lwip/tcp.h" - - -/* - * Structure of an internet header, naked of options. - * - * We declare ip_len and ip_off to be short, rather than u_short - * pragmatically since otherwise unsigned comparisons can result - * against negative integers quite easily, and fail in subtle ways. - */ -PACK_STRUCT_BEGIN -struct ip -{ -#if defined(NO_CHAR_BITFIELDS) - u_char ip_hl_v; /* bug in GCC for mips means the bitfield stuff will sometimes break - so we use a char for both and get round it with macro's instead... */ -#else -#if BYTE_ORDER == LITTLE_ENDIAN - unsigned ip_hl:4, /* header length */ - ip_v:4; /* version */ -#elif BYTE_ORDER == BIG_ENDIAN - unsigned ip_v:4, /* version */ - ip_hl:4; /* header length */ -#else - COMPLAIN - NO BYTE ORDER SELECTED! -#endif -#endif - u_char ip_tos; /* type of service */ - u_short ip_len; /* total length */ - u_short ip_id; /* identification */ - u_short ip_off; /* fragment offset field */ -#define IP_DF 0x4000 /* dont fragment flag */ -#define IP_MF 0x2000 /* more fragments flag */ -#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */ - u_char ip_ttl; /* time to live */ - u_char ip_p; /* protocol */ - u_short ip_sum; /* checksum */ - struct in_addr ip_src,ip_dst; /* source and dest address */ -}; -PACK_STRUCT_END - -typedef u32_t tcp_seq; - -/* - * TCP header. - * Per RFC 793, September, 1981. - */ -PACK_STRUCT_BEGIN -struct tcphdr -{ - u_short th_sport; /* source port */ - u_short th_dport; /* destination port */ - tcp_seq th_seq; /* sequence number */ - tcp_seq th_ack; /* acknowledgement number */ -#if defined(NO_CHAR_BITFIELDS) - u_char th_x2_off; -#else -#if BYTE_ORDER == LITTLE_ENDIAN - unsigned th_x2:4, /* (unused) */ - th_off:4; /* data offset */ -#endif -#if BYTE_ORDER == BIG_ENDIAN - unsigned th_off:4, /* data offset */ - th_x2:4; /* (unused) */ -#endif -#endif - u_char th_flags; - u_short th_win; /* window */ - u_short th_sum; /* checksum */ - u_short th_urp; /* urgent pointer */ -}; -PACK_STRUCT_END - -#endif /* VJBSDHDR_H */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/slipif.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/slipif.c deleted file mode 100644 index dd8db208c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwip/src/netif/slipif.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Institute nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * This file is built upon the file: src/arch/rtxc/netif/sioslip.c - * - * Author: Magnus Ivarsson - */ - -/* - * This is an arch independent SLIP netif. The specific serial hooks must be - * provided by another file. They are sio_open, sio_recv and sio_send - */ - -#include "netif/slipif.h" -#include "lwip/opt.h" -#include "lwip/def.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include "lwip/stats.h" -#include "lwip/sio.h" - -#define SLIP_END 0300 -#define SLIP_ESC 0333 -#define SLIP_ESC_END 0334 -#define SLIP_ESC_ESC 0335 - -#define MAX_SIZE 1500 - -/** - * Send a pbuf doing the necessary SLIP encapsulation - * - * Uses the serial layer's sio_send() - */ -err_t -slipif_output(struct netif *netif, struct pbuf *p, struct ip_addr *ipaddr) -{ - struct pbuf *q; - u16_t i; - u8_t c; - - /* Send pbuf out on the serial I/O device. */ - sio_send(SLIP_END, netif->state); - - for (q = p; q != NULL; q = q->next) { - for (i = 0; i < q->len; i++) { - c = ((u8_t *)q->payload)[i]; - switch (c) { - case SLIP_END: - sio_send(SLIP_ESC, netif->state); - sio_send(SLIP_ESC_END, netif->state); - break; - case SLIP_ESC: - sio_send(SLIP_ESC, netif->state); - sio_send(SLIP_ESC_ESC, netif->state); - break; - default: - sio_send(c, netif->state); - break; - } - } - } - sio_send(SLIP_END, netif->state); - return 0; -} - -/** - * Handle the incoming SLIP stream character by character - * - * Poll the serial layer by calling sio_recv() - * - * @return The IP packet when SLIP_END is received - */ -static struct pbuf * -slipif_input(struct netif *netif) -{ - u8_t c; - struct pbuf *p, *q; - u16_t recved; - u16_t i; - - q = p = NULL; - recved = i = 0; - c = 0; - - while (1) { - c = sio_recv(netif->state); - switch (c) { - case SLIP_END: - if (recved > 0) { - /* Received whole packet. */ - pbuf_realloc(q, recved); - - LINK_STATS_INC(link.recv); - - LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet\n")); - return q; - } - break; - - case SLIP_ESC: - c = sio_recv(netif->state); - switch (c) { - case SLIP_ESC_END: - c = SLIP_END; - break; - case SLIP_ESC_ESC: - c = SLIP_ESC; - break; - } - /* FALLTHROUGH */ - - default: - if (p == NULL) { - LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n")); - p = pbuf_alloc(PBUF_LINK, PBUF_POOL_BUFSIZE, PBUF_POOL); - - if (p == NULL) { - LINK_STATS_INC(link.drop); - LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n")); - } - - if (q != NULL) { - pbuf_cat(q, p); - } else { - q = p; - } - } - if (p != NULL && recved < MAX_SIZE) { - ((u8_t *)p->payload)[i] = c; - recved++; - i++; - if (i >= p->len) { - i = 0; - if (p->next != NULL && p->next->len > 0) - p = p->next; - else - p = NULL; - } - } - break; - } - - } - return NULL; -} - -/** - * The SLIP input thread. - * - * Feed the IP layer with incoming packets - */ -static void -slipif_loop(void *nf) -{ - struct pbuf *p; - struct netif *netif = (struct netif *)nf; - - while (1) { - p = slipif_input(netif); - netif->input(p, netif); - } -} - -/** - * SLIP netif initialization - * - * Call the arch specific sio_open and remember - * the opened device in the state field of the netif. - */ -err_t -slipif_init(struct netif *netif) -{ - - LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%"U16_F"\n", (u16_t)netif->num)); - - netif->name[0] = 's'; - netif->name[1] = 'l'; - netif->output = slipif_output; - netif->mtu = 1500; - netif->flags = NETIF_FLAG_POINTTOPOINT; - - netif->state = sio_open(netif->num); - if (!netif->state) - return ERR_IF; - - sys_thread_new(slipif_loop, netif, SLIPIF_THREAD_PRIO); - return ERR_OK; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwipopts.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwipopts.h deleted file mode 100644 index 4651d6131..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/lwipopts.h +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) 2001-2003 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * Modifications: Christian Walter - */ -#ifndef __LWIPOPTS_H__ -#define __LWIPOPTS_H__ - -/* ------------------------ Generic options ------------------------------- */ -#undef LWIP_NOASSERT - -#define SYS_LIGHTWEIGHT_PROT 1 -#define TCPIP_THREAD_PRIO 3 -#define LWIP_PROVIDE_ERRNO 0 -#define LWIP_DEBUG 0 -#define DBG_TYPES_ON ( DBG_LEVEL_WARNING | DBG_LEVEL_SEVERE | DBG_LEVEL_SERIOUS ) - -/* ------------------------ Memory options -------------------------------- */ -/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which - lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2 - byte alignment -> define MEM_ALIGNMENT to 2. */ -#define MEM_ALIGNMENT 4 - -/* MEM_SIZE: the size of the heap memory. If the application will send -a lot of data that needs to be copied, this should be set high. */ -#define MEM_SIZE 2048 - -/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application - sends a lot of data out of ROM (or other static memory), this - should be set high. */ -#define MEMP_NUM_PBUF 16 -/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One - per active UDP "connection". */ -#define MEMP_NUM_UDP_PCB 4 -/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP - connections. */ -#define MEMP_NUM_TCP_PCB 4 -/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP - connections. */ -#define MEMP_NUM_TCP_PCB_LISTEN 8 -/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP - segments. */ -#define MEMP_NUM_TCP_SEG 16 -/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active - timeouts. */ -#define MEMP_NUM_SYS_TIMEOUT 4 - -/* The following four are used only with the sequential API and can be - set to 0 if the application only will use the raw API. */ -/* MEMP_NUM_NETBUF: the number of struct netbufs. */ -#define MEMP_NUM_NETBUF 0 -/* MEMP_NUM_NETCONN: the number of struct netconns. */ -#define MEMP_NUM_NETCONN 0 -/* MEMP_NUM_APIMSG: the number of struct api_msg, used for - communication between the TCP/IP stack and the sequential - programs. */ -#define MEMP_NUM_API_MSG 0 -/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used - for sequential API communication and incoming packets. Used in - src/api/tcpip.c. */ -#define MEMP_NUM_TCPIP_MSG 4 - -/* ---------- Pbuf options ---------- */ -/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */ -#define PBUF_POOL_SIZE 8 - -/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */ -#define PBUF_POOL_BUFSIZE 256 - -/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a - link level header. */ -#define PBUF_LINK_HLEN 14 - -/* ------------------------ TCP options ----------------------------------- */ -#define LWIP_TCP 1 -#define TCP_TTL 255 - -/* Controls if TCP should queue segments that arrive out of - order. Define to 0 if your device is low on memory. */ -#define TCP_QUEUE_OOSEQ 1 - -/* TCP Maximum segment size. */ -#define TCP_MSS 512 - -/* TCP sender buffer space (bytes). */ -#define TCP_SND_BUF 512 - -/* TCP sender buffer space (pbufs). This must be at least = 2 * - TCP_SND_BUF/TCP_MSS for things to work. */ -#define TCP_SND_QUEUELEN ( 2 * TCP_SND_BUF/TCP_MSS ) - -/* TCP receive window. */ -#define TCP_WND 512 - -/* Maximum number of retransmissions of data segments. */ -#define TCP_MAXRTX 12 - -/* Maximum number of retransmissions of SYN segments. */ -#define TCP_SYNMAXRTX 4 - -/* ------------------------ ARP options ----------------------------------- */ -#define ARP_TABLE_SIZE 10 -#define ARP_QUEUEING 1 - -/* ------------------------ IP options ------------------------------------ */ -/* Define IP_FORWARD to 1 if you wish to have the ability to forward - IP packets across network interfaces. If you are going to run lwIP - on a device with only one network interface, define this to 0. */ -#define IP_FORWARD 0 - -/* If defined to 1, IP options are allowed (but not parsed). If - defined to 0, all packets with IP options are dropped. */ -#define IP_OPTIONS 1 - -/* ------------------------ ICMP options ---------------------------------- */ -#define ICMP_TTL 255 - - -/* ------------------------ DHCP options ---------------------------------- */ -/* Define LWIP_DHCP to 1 if you want DHCP configuration of - interfaces. DHCP is not implemented in lwIP 0.5.1, however, so - turning this on does currently not work. */ -#define LWIP_DHCP 0 - -/* 1 if you want to do an ARP check on the offered address - (recommended). */ -#define DHCP_DOES_ARP_CHECK 1 - -/* ------------------------ UDP options ----------------------------------- */ -#define LWIP_UDP 0 -#define UDP_TTL 255 - -/* ------------------------ Statistics options ---------------------------- */ -#define STATS -#undef STATS - -#ifdef STATS -#define LINK_STATS 1 -#define IP_STATS 1 -#define ICMP_STATS 1 -#define UDP_STATS 1 -#define TCP_STATS 1 -#define MEM_STATS 1 -#define MEMP_STATS 1 -#define PBUF_STATS 1 -#define SYS_STATS 1 -#endif - -/* ------------------------ PPP options ----------------------------------- */ - -#define PPP_SUPPORT 1 -#define PAP_SUPPORT 1 -#define PPP_DEBUG 0 -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/port/mbconfig.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/port/mbconfig.h deleted file mode 100644 index 490edda8c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/port/mbconfig.h +++ /dev/null @@ -1,92 +0,0 @@ - /* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _MB_CONFIG_H -#define _MB_CONFIG_H - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif -/* ----------------------- Defines ------------------------------------------*/ -/*! \defgroup modbus_cfg Modbus Configuration - * - * Most modules in the protocol stack are completly optional and can be - * excluded. This is specially important if target resources are very small - * and program memory space should be saved.
- * - * All of these settings are available in the file mbconfig.h - */ -/*! \addtogroup modbus_cfg - * @{ - */ -/*! \brief If Modbus ASCII support is enabled. */ -#define MB_ASCII_ENABLED ( 0 ) -/*! \brief If Modbus RTU support is enabled. */ -#define MB_RTU_ENABLED ( 0 ) -/*! \brief If Modbus TCP support is enabled. */ -#define MB_TCP_ENABLED ( 1 ) -/*! \brief The character timeout value for Modbus ASCII. - * - * The character timeout value is not fixed for Modbus ASCII and is therefore - * a configuration option. It should be set to the maximum expected delay - * time of the network. - */ -#define MB_ASCII_TIMEOUT_SEC ( 1 ) -/*! \brief Maximum number of Modbus functions codes the protocol stack - * should support. - * - * The maximum number of supported Modbus functions must be greater than - * the sum of all enabled functions in this file and custom function - * handlers. If set to small adding more functions will fail. - */ -#define MB_FUNC_HANDLERS_MAX ( 16 ) -/*! \brief Number of bytes which should be allocated for the Report Slave ID - * command. - * - * This number limits the maximum size of the additional segment in the - * report slave id function. See eMBSetSlaveID( ) for more information on - * how to set this value. It is only used if MB_FUNC_OTHER_REP_SLAVEID_ENABLED - * is set to 1. - */ -#define MB_FUNC_OTHER_REP_SLAVEID_BUF ( 32 ) -/*! \brief If the Report Slave ID function should be enabled. */ -#define MB_FUNC_OTHER_REP_SLAVEID_ENABLED ( 1 ) -/*! \brief If the Read Input Registers function should be enabled. */ -#define MB_FUNC_READ_INPUT_ENABLED ( 1 ) -/*! \brief If the Read Holding Registers function should be enabled. */ -#define MB_FUNC_READ_HOLDING_ENABLED ( 1 ) -/*! \brief If the Write Single Register function should be enabled. */ -#define MB_FUNC_WRITE_HOLDING_ENABLED ( 1 ) -/*! \brief If the Write Multiple registers function should be enabled. */ -#define MB_FUNC_WRITE_MULTIPLE_HOLDING_ENABLED ( 1 ) -/*! \brief If the Read Coils function should be enabled. */ -#define MB_FUNC_READ_COILS_ENABLED ( 1 ) -/*! \brief If the Write Coils function should be enabled. */ -#define MB_FUNC_WRITE_COIL_ENABLED ( 1 ) -/*! \brief If the Write Multiple Coils function should be enabled. */ -#define MB_FUNC_WRITE_MULTIPLE_COILS_ENABLED ( 1 ) -/*! \brief If the Read Discrete Inputs function should be enabled. */ -#define MB_FUNC_READ_DISCRETE_INPUTS_ENABLED ( 1 ) -/*! @} */ -#ifdef __cplusplus - PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/port/port.h deleted file mode 100644 index fcb2d13f0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/port/port.h +++ /dev/null @@ -1,84 +0,0 @@ - /* - * FreeModbus Libary: MCF5235 Port - * Copyright (C) 2006 Christian Walter - * Parts of crt0.S Copyright (c) 1995, 1996, 1998 Cygnus Support - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -/* ----------------------- Platform includes --------------------------------*/ -#include "71x_type.h" -#include "lwip/opt.h" -#include "lwip/sys.h" - -/* ----------------------- Defines ------------------------------------------*/ -#undef INLINE -#define INLINE inline - -#define assert( x ) LWIP_ASSERT( #x, x ); - -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } -/* -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif*/ - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif -#define MB_TCP_DEBUG 1 /* Debug output in TCP module. */ -/* ----------------------- Type definitions ---------------------------------*/ -typedef char BOOL; - -typedef unsigned char UCHAR; -typedef char CHAR; - -typedef unsigned short USHORT; -typedef short SHORT; - -typedef unsigned long ULONG; -typedef long LONG; - -#ifdef MB_TCP_DEBUG -typedef enum -{ - MB_LOG_DEBUG, - MB_LOG_INFO, - MB_LOG_WARN, - MB_LOG_ERROR -} eMBPortLogLevel; -#endif - -/* ----------------------- Function prototypes ------------------------------*/ -#ifdef MB_TCP_DEBUG -void vMBPortLog( eMBPortLogLevel eLevel, const CHAR * szModule, - const CHAR * szFmt, ... ); -void prvvMBTCPLogFrame( UCHAR * pucMsg, UCHAR * pucFrame, USHORT usFrameLen ); -#endif - -#ifdef __cplusplus -PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/port/portevent.c deleted file mode 100644 index b90cad743..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/port/portevent.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * FreeModbus Libary: lwIP Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- lwIP ---------------------------------------------*/ -#include "lwip/api.h" -#include "lwip/sys.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_POLL_CYCLETIME 100 /* Poll cycle time is 100ms */ -/* ----------------------- Static variables ---------------------------------*/ -static sys_mbox_t xMailBox = SYS_MBOX_NULL; -static eMBEventType eMailBoxEvent; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - eMailBoxEvent = EV_READY; - xMailBox = sys_mbox_new( ); - return xMailBox != SYS_MBOX_NULL ? TRUE : FALSE; -} - -void -vMBPortEventClose( void ) -{ - if( xMailBox != SYS_MBOX_NULL ) - { - sys_mbox_free( xMailBox ); - } -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - eMailBoxEvent = eEvent; - sys_mbox_post( xMailBox, &eMailBoxEvent ); - return TRUE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - void *peMailBoxEvent; - BOOL xEventHappend = FALSE; - u32_t uiTimeSpent; - - uiTimeSpent = sys_arch_mbox_fetch( xMailBox, &peMailBoxEvent, MB_POLL_CYCLETIME ); - if( uiTimeSpent != SYS_ARCH_TIMEOUT ) - { - *eEvent = *( eMBEventType * ) peMailBoxEvent; - eMailBoxEvent = EV_READY; - xEventHappend = TRUE; - } - return xEventHappend; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/port/portother.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/port/portother.c deleted file mode 100644 index 3b099d875..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/port/portother.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * FreeModbus Libary: lwIP Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include -#include -#include - -#include "port.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_FRAME_LOG_BUFSIZE 512 - -/* ----------------------- Start implementation -----------------------------*/ - -#ifdef MB_TCP_DEBUG -void -prvvMBTCPLogFrame( UCHAR * pucMsg, UCHAR * pucFrame, USHORT usFrameLen ) -{ - int i; - int res = 0; - int iBufPos = 0; - size_t iBufLeft = MB_FRAME_LOG_BUFSIZE; - static CHAR arcBuffer[MB_FRAME_LOG_BUFSIZE]; - - assert( pucFrame != NULL ); - - for( i = 0; i < usFrameLen; i++ ) - { - /* Print some additional frame information. */ - switch ( i ) - { - case 0: - /* TID = Transaction Identifier. */ - res = snprintf( &arcBuffer[iBufPos], iBufLeft, "| TID = " ); - break; - case 2: - /* PID = Protocol Identifier. */ - res = snprintf( &arcBuffer[iBufPos], iBufLeft, " | PID = " ); - break; - case 4: - /* Length */ - res = snprintf( &arcBuffer[iBufPos], iBufLeft, " | LEN = " ); - break; - case 6: - /* UID = Unit Identifier. */ - res = snprintf( &arcBuffer[iBufPos], iBufLeft, " | UID = " ); - break; - case 7: - /* MB Function Code. */ - res = snprintf( &arcBuffer[iBufPos], iBufLeft, "|| FUNC = " ); - break; - case 8: - /* MB PDU rest. */ - res = snprintf( &arcBuffer[iBufPos], iBufLeft, " | DATA = " ); - break; - default: - res = 0; - break; - } - if( res == -1 ) - { - break; - } - else - { - iBufPos += res; - iBufLeft -= res; - } - - /* Print the data. */ - res = snprintf( &arcBuffer[iBufPos], iBufLeft, "%02X", pucFrame[i] ); - if( res == -1 ) - { - break; - } - else - { - iBufPos += res; - iBufLeft -= res; - } - } - - if( res != -1 ) - { - /* Append an end of frame string. */ - res = snprintf( &arcBuffer[iBufPos], iBufLeft, " |\r\n" ); - if( res != -1 ) - { - vMBPortLog( MB_LOG_DEBUG, pucMsg, "%s", arcBuffer ); - } - } -} -#endif - -void -vMBPortLog( eMBPortLogLevel eLevel, const CHAR * szModule, const CHAR * szFmt, ... ) -{ - va_list args; - static const char *arszLevel2Str[] = { "DEBUG", "INFO", "WARN", "ERROR" }; - - ( void )printf( "%s: %s: ", arszLevel2Str[eLevel], szModule ); - va_start( args, szFmt ); - vprintf( szFmt, args ); - va_end( args ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/port/porttcp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/port/porttcp.c deleted file mode 100644 index 00da78176..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/port/porttcp.c +++ /dev/null @@ -1,330 +0,0 @@ -/* - * FreeModbus Libary: lwIP Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- System includes ----------------------------------*/ -#include - -#include "port.h" - -/* ----------------------- lwIP includes ------------------------------------*/ -#include "lwip/api.h" -#include "lwip/tcp.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- MBAP Header --------------------------------------*/ -#define MB_TCP_UID 6 -#define MB_TCP_LEN 4 -#define MB_TCP_FUNC 7 - -/* ----------------------- Defines -----------------------------------------*/ -#define MB_TCP_DEFAULT_PORT 502 /* TCP listening port. */ -#define MB_TCP_BUF_SIZE ( 256 + 7 ) /* Must hold a complete Modbus TCP frame. */ - -/* ----------------------- Prototypes ---------------------------------------*/ -void vMBPortEventClose( void ); -void vMBPortLog( eMBPortLogLevel eLevel, const CHAR * szModule, - const CHAR * szFmt, ... ); - -/* ----------------------- Static variables ---------------------------------*/ -static struct tcp_pcb *pxPCBListen; -static struct tcp_pcb *pxPCBClient; - -static UCHAR aucTCPBuf[MB_TCP_BUF_SIZE]; -static USHORT usTCPBufPos; - -/* ----------------------- Static functions ---------------------------------*/ -static err_t prvxMBTCPPortAccept( void *pvArg, struct tcp_pcb *pxPCB, err_t xErr ); -static err_t prvxMBTCPPortReceive( void *pvArg, struct tcp_pcb *pxPCB, struct pbuf *p, - err_t xErr ); -static void prvvMBTCPPortError( void *pvArg, err_t xErr ); - -/* ----------------------- Begin implementation -----------------------------*/ -BOOL -xMBTCPPortInit( USHORT usTCPPort ) -{ - struct tcp_pcb *pxPCBListenNew, *pxPCBListenOld; - BOOL bOkay = FALSE; - USHORT usPort; - - if( usTCPPort == 0 ) - { - usPort = MB_TCP_DEFAULT_PORT; - } - else - { - usPort = ( USHORT ) usTCPPort; - } - - if( ( pxPCBListenNew = pxPCBListenOld = tcp_new( ) ) == NULL ) - { - /* Can't create TCP socket. */ - bOkay = FALSE; - } - else if( tcp_bind( pxPCBListenNew, IP_ADDR_ANY, ( u16_t ) usPort ) != ERR_OK ) - { - /* Bind failed - Maybe illegal port value or in use. */ - ( void )tcp_close( pxPCBListenOld ); - bOkay = FALSE; - } - else if( ( pxPCBListenNew = tcp_listen( pxPCBListenNew ) ) == NULL ) - { - ( void )tcp_close( pxPCBListenOld ); - bOkay = FALSE; - } - else - { - /* Register callback function for new clients. */ - tcp_accept( pxPCBListenNew, prvxMBTCPPortAccept ); - - /* Everything okay. Set global variable. */ - pxPCBListen = pxPCBListenNew; - -#ifdef MB_TCP_DEBUG - vMBPortLog( MB_LOG_DEBUG, "MBTCP-ACCEPT", "Protocol stack ready.\r\n" ); -#endif - } - bOkay = TRUE; - return bOkay; -} - -void -prvvMBPortReleaseClient( struct tcp_pcb *pxPCB ) -{ - if( pxPCB != NULL ) - { - if( tcp_close( pxPCB ) != ERR_OK ) - { - tcp_abort( pxPCB ); - } - vPortEnterCritical( ); - if( pxPCB == pxPCBClient ) - { -#ifdef MB_TCP_DEBUG - vMBPortLog( MB_LOG_DEBUG, "MBTCP-CLOSE", "Closed connection to %d.%d.%d.%d.\r\n", - ip4_addr1( &( pxPCB->remote_ip ) ), - ip4_addr2( &( pxPCB->remote_ip ) ), - ip4_addr3( &( pxPCB->remote_ip ) ), ip4_addr4( &( pxPCB->remote_ip ) ) ); -#endif - pxPCBClient = NULL; - } - if( pxPCB == pxPCBListen ) - { - pxPCBListen = NULL; - } - vPortExitCritical( ); - } -} -void -vMBTCPPortClose( ) -{ - /* Shutdown any open client sockets. */ - prvvMBPortReleaseClient( pxPCBClient ); - - /* Shutdown or listening socket. */ - prvvMBPortReleaseClient( pxPCBListen ); - - /* Release resources for the event queue. */ - vMBPortEventClose( ); -} - -void -vMBTCPPortDisable( void ) -{ - prvvMBPortReleaseClient( pxPCBClient ); -} - -err_t -prvxMBTCPPortAccept( void *pvArg, struct tcp_pcb *pxPCB, err_t xErr ) -{ - err_t error; - - if( xErr != ERR_OK ) - { - return xErr; - } - - /* We can handle only one client. */ - if( pxPCBClient == NULL ) - { - /* Register the client. */ - pxPCBClient = pxPCB; - - /* Set up the receive function prvxMBTCPPortReceive( ) to be called when data - * arrives. - */ - tcp_recv( pxPCB, prvxMBTCPPortReceive ); - - /* Register error handler. */ - tcp_err( pxPCB, prvvMBTCPPortError ); - - /* Set callback argument later used in the error handler. */ - tcp_arg( pxPCB, pxPCB ); - - /* Reset the buffers and state variables. */ - usTCPBufPos = 0; - -#ifdef MB_TCP_DEBUG - vMBPortLog( MB_LOG_DEBUG, "MBTCP-ACCEPT", "Accepted new client %d.%d.%d.%d\r\n", - ip4_addr1( &( pxPCB->remote_ip ) ), - ip4_addr2( &( pxPCB->remote_ip ) ), - ip4_addr3( &( pxPCB->remote_ip ) ), ip4_addr4( &( pxPCB->remote_ip ) ) ); -#endif - - error = ERR_OK; - } - else - { - prvvMBPortReleaseClient( pxPCB ); - error = ERR_OK; - } - return error; -} - -/* Called in case of an unrecoverable error. In any case we drop the client - * connection. */ -void -prvvMBTCPPortError( void *pvArg, err_t xErr ) -{ - struct tcp_pcb *pxPCB = pvArg; - - if( pxPCB != NULL ) - { -#ifdef MB_TCP_DEBUG - vMBPortLog( MB_LOG_DEBUG, "MBTCP-ERROR", "Error with client connection! Droping it.\r\n" ); -#endif - prvvMBPortReleaseClient( pxPCB ); - } -} - -err_t -prvxMBTCPPortReceive( void *pvArg, struct tcp_pcb *pxPCB, struct pbuf *p, err_t xErr ) -{ - USHORT usLength; - - err_t error = xErr; - - if( error != ERR_OK ) - { - return error; - } - - /* If pbuf is NULL then remote end has closed connection. */ - if( p == NULL ) - { - prvvMBPortReleaseClient( pxPCB ); - return ERR_OK; - } - - /* Acknowledge that we have received the data bytes. */ - tcp_recved( pxPCB, p->len ); - - /* Check for internal buffer overflow. In case of an error drop the - * client. */ - if( ( usTCPBufPos + p->len ) >= MB_TCP_BUF_SIZE ) - { - prvvMBPortReleaseClient( pxPCB ); - error = ERR_OK; - } - else - { - memcpy( &aucTCPBuf[usTCPBufPos], p->payload, p->len ); - usTCPBufPos += p->len; - - /* If we have received the MBAP header we can analyze it and calculate - * the number of bytes left to complete the current request. If complete - * notify the protocol stack. - */ - if( usTCPBufPos >= MB_TCP_FUNC ) - { - /* Length is a byte count of Modbus PDU (function code + data) and the - * unit identifier. */ - usLength = aucTCPBuf[MB_TCP_LEN] << 8U; - usLength |= aucTCPBuf[MB_TCP_LEN + 1]; - - /* Is the frame already complete. */ - if( usTCPBufPos < ( MB_TCP_UID + usLength ) ) - { - } - else if( usTCPBufPos == ( MB_TCP_UID + usLength ) ) - { -#ifdef MB_TCP_DEBUG - prvvMBTCPLogFrame( "MBTCP-RECV", &aucTCPBuf[0], usTCPBufPos ); -#endif - ( void )xMBPortEventPost( EV_FRAME_RECEIVED ); - } - else - { -#ifdef MB_TCP_DEBUG - vMBPortLog( MB_LOG_DEBUG, "MBTCP-ERROR", - "Received to many bytes! Droping client.\r\n" ); -#endif - /* This should not happen. We can't deal with such a client and - * drop the connection for security reasons. - */ - prvvMBPortReleaseClient( pxPCB ); - } - } - } - pbuf_free( p ); - return error; -} - -BOOL -xMBTCPPortGetRequest( UCHAR ** ppucMBTCPFrame, USHORT * usTCPLength ) -{ - *ppucMBTCPFrame = &aucTCPBuf[0]; - *usTCPLength = usTCPBufPos; - - /* Reset the buffer. */ - usTCPBufPos = 0; - return TRUE; -} - -BOOL -xMBTCPPortSendResponse( const UCHAR * pucMBTCPFrame, USHORT usTCPLength ) -{ - BOOL bFrameSent = FALSE; - - if( pxPCBClient ) - { - /* Make sure we can send the packet. */ - assert( tcp_sndbuf( pxPCBClient ) >= usTCPLength ); - - if( tcp_write( pxPCBClient, pucMBTCPFrame, ( u16_t ) usTCPLength, NETCONN_COPY ) == ERR_OK ) - { -#ifdef MB_TCP_DEBUG - prvvMBTCPLogFrame( "MBTCP-SENT", &aucTCPBuf[0], usTCPLength ); -#endif - /* Make sure data gets sent immediately. */ - ( void )tcp_output( pxPCBClient ); - bFrameSent = TRUE; - } - else - { - /* Drop the connection in case of an write error. */ - prvvMBPortReleaseClient( pxPCBClient ); - } - } - return bFrameSent; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/simple.bat b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/simple.bat deleted file mode 100644 index c4d53d227..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/simple.bat +++ /dev/null @@ -1 +0,0 @@ -..\..\tools\modpoll.exe -m tcp 10.0.10.2 -r 1000 -t 3:int diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/simple.sh b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/simple.sh deleted file mode 100644 index 1af9b7a19..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/simple.sh +++ /dev/null @@ -1 +0,0 @@ -../../tools/modpoll -m tcp 10.0.10.2 -r 1000 -t 3:int diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/startup.s b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/startup.s deleted file mode 100644 index 494619081..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/startup.s +++ /dev/null @@ -1,195 +0,0 @@ -/***************************************************************************** - * Copyright (c) 2001, 2002 Rowley Associates Limited. * - * * - * This file may be distributed under the terms of the License Agreement * - * provided with this software. * - * * - * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * - * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * - ***************************************************************************** - * WARNING * - ***************************************************************************** - * There have been a lot of modifications to this file for the FreeRTOS port * - * for the following reason: * - * * - * - We need support for the interrupt vectors from the EIC. * - * - The default file did only make a copy of the standard vectors when in * - * FLASH mode. Because in the used EIC configuration the new programm * - * counter value is loaded with a relative offset to the current pc the * - * interrupt vectors must also be available in the RAM. * - * - The clock source configuration did not fit for the specific * - * needs of the author. * - * * - * All modifications copyright (c) 2006, Christian Walter * - *****************************************************************************/ - -#include "FreeRTOSConfig.h" /* import configUSE_PREEMPTION */ - - .equ EIC_BASE, 0xFFFFF800 /* EIC base address. */ - .equ EIC_IVR_OFF, 0x18 /* EIC interrupt vector register. */ - - .section .vectors, "ax" - .code 32 - .align 0 - -/***************************************************************************** - * Exception vectors * - *****************************************************************************/ -_vectors_start: - ldr pc, [pc, #reset_handler_address - . - 8] /* reset */ - ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */ - ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */ - ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */ - ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */ - nop - ldr pc, [pc, #irq_handler_address - . - 8] - ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq */ - -reset_handler_address: .word _reset_handler -undef_handler_address: .word _undef_handler -swi_handler_address: .word vPortYieldProcessor -pabort_handler_address: .word _pabort_handler -dabort_handler_address: .word _dabort_handler -irq_handler_address: .word _irq_handler -fiq_handler_address: .word _fiq_handler - -/******************************************************************************* - * EIC interrupt vectors - ******************************************************************************/ -.global T0TIMI_address -.global T0TIMI_Addr -T0TIMI_Addr: /* for compatibility with STR71X library. */ -T0TIMI_address: .word _undef_IRQhandler -FLASH_address: .word _undef_IRQhandler -RCCU_address: .word _undef_IRQhandler -RTC_Addr: .word _undef_IRQhandler -#if configUSE_PREEMPTION == 0 -WDG_Addr: .word vPortNonPreemptiveTick -#else -WDG_Addr: .word vPortPreemptiveTick -#endif -XTI_Addr: .word _undef_IRQhandler -USBHP_Addr: .word _undef_IRQhandler -I2C0ITERR_Addr: .word _undef_IRQhandler -I2C1ITERR_ADDR: .word _undef_IRQhandler -UART0_ADDR: .word sio_uart0_irq -UART1_ADDR: .word sio_uart1_irq -UART2_ADDR: .word _undef_IRQhandler -UART3_ADDR: .word _undef_IRQhandler -BSPI0_ADDR: .word _undef_IRQhandler -BSPI1_Addr: .word _undef_IRQhandler -I2C0_Addr: .word _undef_IRQhandler -I2C1_Addr: .word _undef_IRQhandler -CAN_Addr: .word _undef_IRQhandler -ADC12_Addr: .word _undef_IRQhandler -T1TIMI_Addr: .word _undef_IRQhandler -T2TIMI_Addr: .word _undef_IRQhandler -T3TIMI_Addr: .word _undef_IRQhandler - .word 0 /* reserved */ - .word 0 /* reserved */ - .word 0 /* reserved */ -HDLC_Addr: .word _undef_IRQhandler -USBLP_Addr: .word _undef_IRQhandler - .word 0 /* reserved */ - .word 0 /* reserved */ -T0TOI_Addr: .word _undef_IRQhandler -T0OC1_Addr: .word _undef_IRQhandler -T0OC2_Addr: .word _undef_IRQhandler -_vectors_end: - -/******************************************************************************* - * If flash execution is used and the RAM is mapped at address 0 we also need - * to place a copy of the interrupt vector address table in the RAM. - ******************************************************************************/ - #ifdef __FLASH_BUILD - .section .vectors_ram, "ax" - .code 32 - .align 0 -_vectors_ram: - .fill _vectors_end - _vectors_start -#endif - -/****************************************************************************** - * Default exception handlers * - ******************************************************************************/ - .section .init, "ax" - .code 32 - .align 0 - -_reset_handler: -#ifdef __FLASH_BUILD - ldr r0, =_vectors_start - ldr r1, =_vectors_end - sub r1, r1, r0 /* r2 = number of bytes to copy */ - ldr r2, =0x20000000 /* r0 = start address to place copy */ -_vector_copy: - ldr r3, [r0], #4 /* read a word from the source */ - str r3, [r2], #4 /* copy the word to destination */ - subs r1, r1, #4 /* decrement number of words to copy */ - bne _vector_copy -#endif - - /* Configure system and jump to the _start entry point. */ - ldr r0, =0x6C000000 - ldr r1, =0x801D - str r1, [r0, #4] /* set up the emi to 1 wait state */ - - ldr r0, =0xA0000000 - ldr r1, =0x1c2 - str r1, [r0, #0x50] /* set up the internal RAM at 0x0 */ - - /* After setup the folling clock configuration will be active. Note - * that the value of CK is dependent on the target oscillator. - * - * CK = 4Mhz - * CLK2 = 2Mhz (with DIV2 = 1) - * RCLK = 16 * CLK2 / 1 = 32Mhz - * MCLK = RCLK - * PCLK1 = RCLK/2 - * PCLK2 = RCLK/2 - */ - - /* set RCLK to 16 * CLK2 / 1 = 32Mhz - * (0x0071 = FREEN=1, FREF_RANGE=1, MX1:0=11b, DX2:0=000b) */ - ldr r1, =0x00F0 - str r1, [r0, #0x18] - - /* (0x8009 = DIV2=1, CK2_16=1, CKU_CKSEL=1) */ - ldr r1, =0x8009 - str r1, [r0, #0x8] - - /* cpu and memory clock div = 1 */ - ldr r1, =0x0 - str r1, [r0, #0x40] - - /* pclk1 = rclk/1 and pclk2 = rclk/1 = 32Mhz - * (0x0101 = FACT2_9:8=01b, FACT1_1:0=01b) */ - ldr r1, =0x0000 - str r1, [r0, #0x44] - - /* Jump to the default C runtime startup code. */ - B _start - -_undef_handler: - b _undef_handler - -_swi_handler: - b vPortYieldProcessor - -_pabort_handler: - b _pabort_handler - -_dabort_handler: - b _dabort_handler - -_irq_handler: - ldr pc, =(EIC_BASE + EIC_IVR_OFF) - -_fiq_handler: - b _fiq_handler - -/****************************************************************************** - * Default IRQ handlers * - ******************************************************************************/ -_undef_IRQhandler: - b _undef_IRQhandler diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/utils/options b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/utils/options deleted file mode 100644 index 9ca5c8820..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/utils/options +++ /dev/null @@ -1,5 +0,0 @@ -asyncmap 0 -lock -noauth -nodefaultroute -silent diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/utils/options-pap b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/utils/options-pap deleted file mode 100644 index 4876b2f25..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/utils/options-pap +++ /dev/null @@ -1,5 +0,0 @@ -asyncmap 0 -lock -auth -nodefaultroute -silent diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/utils/options.ttyS0 b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/utils/options.ttyS0 deleted file mode 100644 index 6166089ad..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/utils/options.ttyS0 +++ /dev/null @@ -1,16 +0,0 @@ -# no modem control lines -local -nocrtscts - -# local address:remote address -10.0.10.1:10.0.10.2 -# pppd waits for connection on ttyS1 -passive -# pppd stays enabled even if remote disconnects. -persist -# proxy into lan -proxyarp -# disable compressoin -#nodeflate -#nobsdcomp -#novj diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/utils/pap-secrets b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/utils/pap-secrets deleted file mode 100644 index cb8c9acf6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/utils/pap-secrets +++ /dev/null @@ -1,3 +0,0 @@ -# Secrets for authentication using PAP -# client server secret IP addresses -freemodbus * insecure * diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/utils/server.sh b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/utils/server.sh deleted file mode 100644 index 6ca242041..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/STR71XTCP/utils/server.sh +++ /dev/null @@ -1,9 +0,0 @@ -# --------------------------------------------------------------------------- -# server.sh - starts a local PPP server to connect with the target. -# -# Autor: Christian Walter -# --------------------------------------------------------------------------- -SER_DEV="/dev/ttyUSB0" -SER_SPEED="115200" -stty raw -parenb cs8 -cstopb -F $SER_DEV -/usr/sbin/pppd debug nodetach $SER_DEV $SER_SPEED diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/Port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/Port/port.h deleted file mode 100644 index 6861f5160..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/Port/port.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * FreeModbus Libary: Win32 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -#include -#include -#include - -#define INLINE -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif - -/* ----------------------- Defines ------------------------------------------*/ - -#define ENTER_CRITICAL_SECTION( ) -#define EXIT_CRITICAL_SECTION( ) -#define MB_PORT_HAS_CLOSE 1 -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - -/* ----------------------- Type definitions ---------------------------------*/ - -typedef enum -{ - MB_LOG_DEBUG, - MB_LOG_INFO, - MB_LOG_WARN, - MB_LOG_ERROR -} eMBPortLogLevel; - -/* ----------------------- Function prototypes ------------------------------*/ - -void vMBPortLog( eMBPortLogLevel eLevel, const TCHAR * szModule, - const TCHAR * szFmt, ... ); -void vMBPortTimerPoll( ); -BOOL xMBPortSerialPoll( ); -BOOL xMBPortSerialSetTimeout( DWORD dwTimeoutMs ); - -#ifdef __cplusplus -PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/Port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/Port/portevent.c deleted file mode 100644 index 07ceca498..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/Port/portevent.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * FreeModbus Libary: Win32 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static eMBEventType eQueuedEvent; -static BOOL xEventInQueue; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - xEventInQueue = FALSE; - return TRUE; -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - xEventInQueue = TRUE; - eQueuedEvent = eEvent; - return TRUE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - BOOL xEventHappened = FALSE; - - if( xEventInQueue ) - { - *eEvent = eQueuedEvent; - xEventInQueue = FALSE; - xEventHappened = TRUE; - } - else - { - /* Poll the serial device. The serial device timeouts if no - * characters have been received within for t3.5 during an - * active transmission or if nothing happens within a specified - * amount of time. Both timeouts are configured from the timer - * init functions. - */ - ( void )xMBPortSerialPoll( ); - - /* Check if any of the timers have expired. */ - vMBPortTimerPoll( ); - - } - return xEventHappened; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/Port/portother.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/Port/portother.c deleted file mode 100644 index cb0107f09..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/Port/portother.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * FreeModbus Libary: Win32 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#include -#include - -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" -#include "mbconfig.h" - -LPTSTR -Error2String( DWORD dwError ) -{ - static TCHAR szUserBuf[512]; - static LPTSTR szErrorMsg = _T( "internal error" ); - LPTSTR lpMsgBuf = NULL; - DWORD dwLength; - - dwLength = FormatMessage( FORMAT_MESSAGE_ALLOCATE_BUFFER | - FORMAT_MESSAGE_FROM_SYSTEM, - NULL, - dwError, - MAKELANGID( LANG_NEUTRAL, SUBLANG_DEFAULT ), - ( LPTSTR ) & lpMsgBuf, 0, NULL ); - if( dwLength == 0 ) - { - lpMsgBuf = _T( "internal error" ); - } - - _tcsnccpy_s( szUserBuf, _countof( szUserBuf ), lpMsgBuf, _tcslen( lpMsgBuf ) ); - LocalFree( lpMsgBuf ); - - return szUserBuf; -} - -void -vMBPortLog( eMBPortLogLevel eLevel, const TCHAR * szModule, const TCHAR * szFmt, ... ) -{ - TCHAR szBuf[512]; - int i; - va_list args; - static const LPTSTR arszLevel2Str[] = - { _T( "DEBUG" ), _T( "INFO" ), _T( "WARN" ), _T( "ERROR" ) }; - - i = _sntprintf_s( szBuf, _countof(szBuf) , _TRUNCATE, _T( "%s: %s: " ), - arszLevel2Str[eLevel], szModule ); - - if( i != 0 ) - { - va_start( args, szFmt ); - i += _vsntprintf_s( &szBuf[i], _countof(szBuf) - i, _TRUNCATE, szFmt, args ); - va_end( args ); - } - - if( i != 0 ) - { - if( eLevel == MB_LOG_DEBUG ) - { - OutputDebugString( szBuf ); - } - else - { - _fputts( szBuf, stderr ); - } - } - -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/Port/portserial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/Port/portserial.c deleted file mode 100644 index 38bb55193..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/Port/portserial.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - * FreeModbus Libary: Win32 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#include - -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" -#include "mbconfig.h" - -/* ----------------------- Defines -----------------------------------------*/ -#if MB_ASCII_ENABLED == 1 -#define BUF_SIZE 513 /* must hold a complete ASCII frame. */ -#else -#define BUF_SIZE 256 /* must hold a complete RTU frame. */ -#endif - -/* ----------------------- Static variables ---------------------------------*/ -static HANDLE g_hSerial; -static BOOL bRxEnabled; -static BOOL bTxEnabled; - -static UCHAR ucBuffer[BUF_SIZE]; -static INT uiRxBufferPos; -static INT uiTxBufferPos; - -/* ----------------------- Function prototypes ------------------------------*/ -LPTSTR Error2String( DWORD dwError ); - -/* ----------------------- Begin implementation -----------------------------*/ -void -vMBPortSerialEnable( BOOL bEnableRx, BOOL bEnableTx ) -{ - /* it is not allowed that both receiver and transmitter are enabled. */ - assert( !bEnableRx || !bEnableTx ); - - if( bEnableRx ) - { - PurgeComm( g_hSerial, PURGE_RXCLEAR ); - uiRxBufferPos = 0; - bRxEnabled = TRUE; - } - else - { - bRxEnabled = FALSE; - } - if( bEnableTx ) - { - bTxEnabled = TRUE; - uiTxBufferPos = 0; - } - else - { - bTxEnabled = FALSE; - } -} - -BOOL -xMBPortSerialInit( UCHAR ucPort, ULONG ulBaudRate, UCHAR ucDataBits, - eMBParity eParity ) -{ - TCHAR szDevice[8]; - BOOL bStatus = TRUE; - DCB dcb; - - - - memset( &dcb, 0, sizeof( dcb ) ); - - dcb.DCBlength = sizeof( dcb ); - dcb.BaudRate = ulBaudRate; - - _stprintf_s( szDevice, 8, _T( "COM%d" ), ucPort ); - - switch ( eParity ) - { - case MB_PAR_NONE: - dcb.Parity = NOPARITY; - dcb.fParity = 0; - break; - case MB_PAR_EVEN: - dcb.Parity = EVENPARITY; - dcb.fParity = 1; - break; - case MB_PAR_ODD: - dcb.Parity = ODDPARITY; - dcb.fParity = 1; - break; - default: - bStatus = FALSE; - } - - switch ( ucDataBits ) - { - case 8: - dcb.ByteSize = 8; - break; - case 7: - dcb.ByteSize = 7; - break; - default: - bStatus = FALSE; - } - - - - if( bStatus ) - { - /* we don't use XON/XOFF flow control. */ - dcb.fInX = dcb.fOutX = FALSE; - /* we don't need hardware handshake. */ - dcb.fOutxCtsFlow = dcb.fOutxCtsFlow = FALSE; - dcb.fRtsControl = RTS_CONTROL_ENABLE; - dcb.fDtrControl = DTR_CONTROL_ENABLE; - - /* misc parameters */ - dcb.fErrorChar = FALSE; - dcb.fBinary = TRUE; - dcb.fNull = FALSE; - dcb.fAbortOnError = FALSE; - dcb.wReserved = 0; - dcb.XonLim = 2; - dcb.XoffLim = 4; - dcb.XonChar = 0x13; - dcb.XoffChar = 0x19; - dcb.EvtChar = 0; - - /* Open the serial device. */ - g_hSerial = - CreateFile( szDevice, GENERIC_READ | GENERIC_WRITE, 0, NULL, - OPEN_EXISTING, 0, NULL ); - - - if( g_hSerial == INVALID_HANDLE_VALUE ) - { - vMBPortLog( MB_LOG_ERROR, _T( "SER-INIT" ), _T( "Can't open serial port %s: %s" ), - szDevice, Error2String( GetLastError( ) ) ); - bStatus = FALSE; - } - else if( !SetCommState( g_hSerial, &dcb ) ) - { - vMBPortLog( MB_LOG_ERROR, _T( "SER-INIT" ), - _T( "Can't set settings for serial device %s: %s" ), - szDevice, Error2String( GetLastError( ) ) ); - bStatus = FALSE; - } - else if( !SetCommMask( g_hSerial, 0 ) ) - { - vMBPortLog( MB_LOG_ERROR, _T( "SER-INIT" ), - _T( "Can't set communication event mask for serial device %s: %s" ), - szDevice, Error2String( GetLastError( ) ) ); - bStatus = FALSE; - } - - else - { - vMBPortSerialEnable( FALSE, FALSE ); - bStatus = TRUE; - } - } - return bStatus; -} - -BOOL -xMBPortSerialSetTimeout( DWORD dwTimeoutMs ) -{ - BOOL bStatus; - COMMTIMEOUTS cto; - - /* usTimeOut is the inter character timeout used to detect the end - * of frame. The total timeout is set to 50ms to make sure we - * can exit the blocking read. */ - cto.ReadIntervalTimeout = dwTimeoutMs; - cto.ReadTotalTimeoutConstant = 50; - cto.ReadTotalTimeoutMultiplier = 0; - cto.WriteTotalTimeoutConstant = 0; - cto.WriteTotalTimeoutMultiplier = 0; - - if( !SetCommTimeouts( g_hSerial, &cto ) ) - { - vMBPortLog( MB_LOG_ERROR, _T( "SER-INIT" ), - _T( "Can't set timeouts for serial device: %s" ), - Error2String( GetLastError( ) ) ); - bStatus = FALSE; - } - else - { - bStatus = TRUE; - } - - return bStatus; -} - -void -vMBPortClose ( void ) -{ - ( void )CloseHandle( g_hSerial ); -} - -BOOL -xMBPortSerialPoll( ) -{ - BOOL bStatus = TRUE; - DWORD dwBytesRead; - DWORD dwBytesWritten; - DWORD i; - - while( bRxEnabled ) - { - /* buffer wrap around. */ - if( uiRxBufferPos >= BUF_SIZE ) - uiRxBufferPos = 0; - - if( ReadFile( g_hSerial, &ucBuffer[uiRxBufferPos], - BUF_SIZE - uiRxBufferPos, &dwBytesRead, NULL ) ) - { - if( dwBytesRead == 0 ) - { - /* timeout with no bytes. */ - break; - } - else if( dwBytesRead > 0 ) - { - vMBPortLog( MB_LOG_DEBUG, _T( "SER-POLL" ), - _T( "detected end of frame (t3.5 expired.)\r\n" ) ); - for( i = 0; i < dwBytesRead; i++ ) - { - /* Call the modbus stack and let him fill the buffers. */ - ( void )pxMBFrameCBByteReceived( ); - } - } - } - else - { - vMBPortLog( MB_LOG_ERROR, _T( "SER-POLL" ), _T( "I/O error on serial device: %s" ), - Error2String( GetLastError ( ) ) ); - bStatus = FALSE; - } - } - if( bTxEnabled ) - { - while( bTxEnabled ) - { - ( void )pxMBFrameCBTransmitterEmpty( ); - /* Call the modbus stack to let him fill the buffer. */ - } - dwBytesWritten = 0; - if( !WriteFile - ( g_hSerial, &ucBuffer[0], uiTxBufferPos, &dwBytesWritten, NULL ) - || ( dwBytesWritten != uiTxBufferPos ) ) - { - vMBPortLog( MB_LOG_ERROR, _T( "SER-POLL" ), _T( "I/O error on serial device: %s" ), - Error2String( GetLastError ( ) ) ); - bStatus = FALSE; - } - } - - return bStatus; -} - -BOOL -xMBPortSerialPutByte( CHAR ucByte ) -{ - assert( uiTxBufferPos < BUF_SIZE ); - ucBuffer[uiTxBufferPos] = ucByte; - uiTxBufferPos++; - return TRUE; -} - -BOOL -xMBPortSerialGetByte( CHAR * pucByte ) -{ - assert( uiRxBufferPos < BUF_SIZE ); - *pucByte = ucBuffer[uiRxBufferPos]; - uiRxBufferPos++; - return TRUE; -} - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/Port/porttimer.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/Port/porttimer.c deleted file mode 100644 index 0224a300b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/Port/porttimer.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * FreeModbus Libary: Win32 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Platform includes --------------------------------*/ -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ - -/* ----------------------- Static variables ---------------------------------*/ -DWORD dwTimeOut; -BOOL bTimeoutEnable; -DWORD dwTimeLast; -extern HANDLE g_hSerial; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortTimersInit( USHORT usTim1Timerout50us ) -{ - dwTimeOut = usTim1Timerout50us / 20U; - if( dwTimeOut == 0 ) - dwTimeOut = 1; - - return xMBPortSerialSetTimeout( dwTimeOut ); -} - -void -xMBPortTimersClose( ) -{ - /* Does not use any hardware resources. */ -} - -void -vMBPortTimerPoll( ) -{ - - /* Timers are called from the serial layer because we have no high - * res timer in Win32. */ - if( bTimeoutEnable ) - { - DWORD dwTimeCurrent = GetTickCount( ); - - if( ( dwTimeCurrent - dwTimeLast ) > dwTimeOut ) - { - bTimeoutEnable = FALSE; - ( void )pxMBPortCBTimerExpired( ); - } - } -} - -void -vMBPortTimersEnable( ) -{ - bTimeoutEnable = TRUE; - dwTimeLast = GetTickCount( ); -} - -void -vMBPortTimersDisable( ) -{ - bTimeoutEnable = FALSE; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/demo.cpp b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/demo.cpp deleted file mode 100644 index c08a971b0..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/demo.cpp +++ /dev/null @@ -1,299 +0,0 @@ -/* - * FreeModbus Libary: Win32 Demo Application - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id: demo.cpp,v 1.3 2006/06/26 19:23:40 wolti Exp $ - */ - -#include "stdafx.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define PROG _T("freemodbus") - -#define REG_INPUT_START 1000 -#define REG_INPUT_NREGS 4 -#define REG_HOLDING_START 2000 -#define REG_HOLDING_NREGS 130 - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegInputStart = REG_INPUT_START; -static USHORT usRegInputBuf[REG_INPUT_NREGS]; -static USHORT usRegHoldingStart = REG_HOLDING_START; -static USHORT usRegHoldingBuf[REG_HOLDING_NREGS]; - -static HANDLE hPollThread; -static CRITICAL_SECTION hPollLock; -static enum ThreadState -{ - STOPPED, - RUNNING, - SHUTDOWN -} ePollThreadState; - -/* ----------------------- Static functions ---------------------------------*/ -static BOOL bCreatePollingThread( void ); -static enum ThreadState eGetPollingThreadState( void ); -static void eSetPollingThreadState( enum ThreadState eNewState ); -static DWORD WINAPI dwPollingThread( LPVOID lpParameter ); - -/* ----------------------- Start implementation -----------------------------*/ -int -_tmain( int argc, _TCHAR * argv[] ) -{ - int iExitCode; - TCHAR cCh; - BOOL bDoExit; - - const UCHAR ucSlaveID[] = { 0xAA, 0xBB, 0xCC }; - - if( eMBInit( MB_RTU, 0x0A, 1, 38400, MB_PAR_EVEN ) != MB_ENOERR ) - { - _ftprintf( stderr, _T( "%s: can't initialize modbus stack!\r\n" ), PROG ); - iExitCode = EXIT_FAILURE; - } - else if( eMBSetSlaveID( 0x34, TRUE, ucSlaveID, 3 ) != MB_ENOERR ) - { - _ftprintf( stderr, _T( "%s: can't set slave id!\r\n" ), PROG ); - iExitCode = EXIT_FAILURE; - } - else - { - /* Create synchronization primitives and set the current state - * of the thread to STOPPED. - */ - InitializeCriticalSection( &hPollLock ); - eSetPollingThreadState( STOPPED ); - - /* CLI interface. */ - _tprintf( _T( "Type 'q' for quit or 'h' for help!\r\n" ) ); - bDoExit = FALSE; - do - { - _tprintf( _T( "> " ) ); - cCh = _gettchar( ); - switch ( cCh ) - { - case _TCHAR( 'q' ): - bDoExit = TRUE; - break; - case _TCHAR( 'd' ): - eSetPollingThreadState( SHUTDOWN ); - break; - case _TCHAR( 'e' ): - if( bCreatePollingThread( ) != TRUE ) - { - _tprintf( _T( "Can't start protocol stack! Already running?\r\n" ) ); - } - break; - case _TCHAR( 's' ): - switch ( eGetPollingThreadState( ) ) - { - case RUNNING: - _tprintf( _T( "Protocol stack is running.\r\n" ) ); - break; - case STOPPED: - _tprintf( _T( "Protocol stack is stopped.\r\n" ) ); - break; - case SHUTDOWN: - _tprintf( _T( "Protocol stack is shuting down.\r\n" ) ); - break; - } - break; - case _TCHAR( 'h' ): - _tprintf( _T( "FreeModbus demo application help:\r\n" ) ); - _tprintf( _T( " 'd' ... disable protocol stack.\r\n" ) ); - _tprintf( _T( " 'e' ... enabled the protocol stack\r\n" ) ); - _tprintf( _T( " 's' ... show current status\r\n" ) ); - _tprintf( _T( " 'q' ... quit applicationr\r\n" ) ); - _tprintf( _T( " 'h' ... this information\r\n" ) ); - _tprintf( _T( "\r\n" ) ); - _tprintf( _T( "Copyright 2006 Christian Walter \r\n" ) ); - break; - default: - if( cCh != _TCHAR('\n') ) - { - _tprintf( _T( "illegal command '%c'!\r\n" ), cCh ); - } - break; - } - - /* eat up everything untill return character. */ - while( cCh != '\n' ) - { - cCh = _gettchar( ); - } - } - while( !bDoExit ); - - /* Release hardware resources. */ - ( void )eMBClose( ); - iExitCode = EXIT_SUCCESS; - } - return iExitCode; -} - -BOOL -bCreatePollingThread( void ) -{ - BOOL bResult; - - if( eGetPollingThreadState( ) == STOPPED ) - { - if( ( hPollThread = CreateThread( NULL, 0, dwPollingThread, NULL, 0, NULL ) ) == NULL ) - { - /* Can't create the polling thread. */ - bResult = FALSE; - } - else - { - bResult = TRUE; - } - } - else - { - bResult = FALSE; - } - - return bResult; -} - -DWORD WINAPI -dwPollingThread( LPVOID lpParameter ) -{ - eSetPollingThreadState( RUNNING ); - - if( eMBEnable( ) == MB_ENOERR ) - { - do - { - if( eMBPoll( ) != MB_ENOERR ) - break; - } - while( eGetPollingThreadState( ) != SHUTDOWN ); - } - - ( void )eMBDisable( ); - - eSetPollingThreadState( STOPPED ); - - return 0; -} - -enum ThreadState -eGetPollingThreadState( ) -{ - enum ThreadState eCurState; - - EnterCriticalSection( &hPollLock ); - eCurState = ePollThreadState; - LeaveCriticalSection( &hPollLock ); - - return eCurState; -} - -void -eSetPollingThreadState( enum ThreadState eNewState ) -{ - EnterCriticalSection( &hPollLock ); - ePollThreadState = eNewState; - LeaveCriticalSection( &hPollLock ); -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_HOLDING_START ) && - ( usAddress + usNRegs <= REG_HOLDING_START + REG_HOLDING_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegHoldingStart ); - switch ( eMode ) - { - /* Pass current register values to the protocol stack. */ - case MB_REG_READ: - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( UCHAR ) ( usRegHoldingBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( UCHAR ) ( usRegHoldingBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - break; - - /* Update current register values with new values from the - * protocol stack. */ - case MB_REG_WRITE: - while( usNRegs > 0 ) - { - usRegHoldingBuf[iRegIndex] = *pucRegBuffer++ << 8; - usRegHoldingBuf[iRegIndex] |= *pucRegBuffer++; - iRegIndex++; - usNRegs--; - } - } - } - else - { - eStatus = MB_ENOREG; - } - return eStatus; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/demo.vcproj b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/demo.vcproj deleted file mode 100644 index 7f0e5f45c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/demo.vcproj +++ /dev/null @@ -1,358 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/stdafx.cpp b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/stdafx.cpp deleted file mode 100644 index ad511a98c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/stdafx.cpp +++ /dev/null @@ -1,8 +0,0 @@ -// stdafx.cpp : source file that includes just the standard includes -// freemodbus.pch will be the pre-compiled header -// stdafx.obj will contain the pre-compiled type information - -#include "stdafx.h" - -// TODO: reference any additional headers you need in STDAFX.H -// and not in this file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/stdafx.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/stdafx.h deleted file mode 100644 index 454201a3c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32/stdafx.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * FreeModbus Libary: Win32 Demo Application - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#pragma once - - -#define WIN32_LEAN_AND_MEAN -#include -#include -#include - -#include diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/Port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/Port/port.h deleted file mode 100644 index b529da1be..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/Port/port.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * FreeModbus Libary: BSD Socket Library Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -#include -#include -#include - -#define INLINE -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif - -/* ----------------------- Defines ------------------------------------------*/ - -#define ENTER_CRITICAL_SECTION( ) -#define EXIT_CRITICAL_SECTION( ) -#define MB_PORT_HAS_CLOSE 1 -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - -/* ----------------------- Type definitions ---------------------------------*/ - -typedef enum -{ - MB_LOG_DEBUG, - MB_LOG_INFO, - MB_LOG_WARN, - MB_LOG_ERROR -} eMBPortLogLevel; - -/* ----------------------- Function prototypes ------------------------------*/ - -void vMBPortLog( eMBPortLogLevel eLevel, const TCHAR * szModule, - const TCHAR * szFmt, ... ); - -#ifdef __cplusplus -PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/Port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/Port/portevent.c deleted file mode 100644 index 4841cf9da..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/Port/portevent.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * FreeModbus Libary: Win32 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static eMBEventType eQueuedEvent; -static BOOL xEventInQueue; - -/* ----------------------- Function prototypes ------------------------------*/ -BOOL xMBPortTCPPool( void ); - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - xEventInQueue = FALSE; - return TRUE; -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - xEventInQueue = TRUE; - eQueuedEvent = eEvent; - return TRUE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - BOOL xEventHappened = FALSE; - - if( xEventInQueue ) - { - *eEvent = eQueuedEvent; - xEventInQueue = FALSE; - xEventHappened = TRUE; - } - else - { - /* We can't do anything with errors from the pooling module. */ - ( void )xMBPortTCPPool( ); - } - return xEventHappened; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/Port/portother.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/Port/portother.c deleted file mode 100644 index 42f896018..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/Port/portother.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * FreeModbus Libary: Win32 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#include -#include -#include "winsock2.h" - -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" -#include "mbconfig.h" - - -BOOL -prvMBTCPPortAddressToString( SOCKET xSocket, LPTSTR szAddr, USHORT usBufSize ) -{ - BOOL bOkay; - SOCKADDR_IN xClientAddr; - int iAddrLen = sizeof( SOCKADDR_IN ); - DWORD dwBufSize = usBufSize; - - assert( ( szAddr != NULL ) && ( usBufSize > 0 ) ); - if( getsockname( xSocket, ( SOCKADDR * ) & xClientAddr, &iAddrLen ) == SOCKET_ERROR ) - { - bOkay = FALSE; - } - else if( WSAAddressToString( ( SOCKADDR * ) & xClientAddr, iAddrLen, NULL, szAddr, - &dwBufSize ) == SOCKET_ERROR ) - { - bOkay = FALSE; - } - else - { - bOkay = TRUE; - } - return bOkay; -} - -LPTSTR -prvMBTCPPortFrameToString( UCHAR * pucFrame, USHORT usFrameLen ) -{ - LPTSTR szBuf; - int i; - int res; - int szBufPos = 0; - int szBufLength = usFrameLen + 128; - - assert( ( pucFrame != NULL ) ); - - szBuf = malloc( szBufLength * sizeof( TCHAR ) ); - if( szBuf != NULL ) - { - for( i = 0; i < usFrameLen; i++ ) - { - /* Print some additional frame information. */ - switch ( i ) - { - case 0: /* TID = Transaction Identifier. */ - res = _sntprintf_s( &szBuf[szBufPos], szBufLength, _TRUNCATE, _T( "| TID = " ) ); - break; - case 2: /* PID = Protocol Identifier. */ - res = _sntprintf_s( &szBuf[szBufPos], szBufLength, _TRUNCATE, _T( " | PID = " ) ); - break; - case 4: /* Length */ - res = _sntprintf_s( &szBuf[szBufPos], szBufLength, _TRUNCATE, _T( " | LEN = " ) ); - break; - case 6: /* UID = Unit Identifier. */ - res = _sntprintf_s( &szBuf[szBufPos], szBufLength, _TRUNCATE, _T( " | UID = " ) ); - break; - case 7: /* MB Function Code. */ - res = _sntprintf_s( &szBuf[szBufPos], szBufLength, _TRUNCATE, _T( " || FUNC = " ) ); - break; - case 8: /* MB PDU rest. */ - res = _sntprintf_s( &szBuf[szBufPos], szBufLength, _TRUNCATE, _T( " | DATA = " ) ); - break; - default: - res = 0; - break; - } - if( res == -1 ) - { - break; - } - else if( res != 0 ) - { - szBufPos += res; - szBufLength -= res; - } - - /* Print the data. */ - res = _sntprintf_s( &szBuf[szBufPos], szBufLength, _TRUNCATE, _T( "%02X" ), - pucFrame[i] ); - if( res == -1 ) - { - break; - } - szBufPos += res; - szBufLength -= res; - } - if( res != -1 ) - { - /* Append an end of frame string. */ - res = _sntprintf_s( &szBuf[szBufPos], szBufLength, _TRUNCATE, _T( " |" ), pucFrame[i] ); - } - if( res == -1 ) - { - free( szBuf ); - szBuf = NULL; - } - } - return szBuf; -} - -TCHAR * -WsaError2String( DWORD dwError ) -{ - static TCHAR szUserBuf[512]; - static LPTSTR szErrorMsg = _T( "internal error" ); - LPTSTR lpMsgBuf = NULL; - DWORD dwLength; - - dwLength = FormatMessage( FORMAT_MESSAGE_ALLOCATE_BUFFER | - FORMAT_MESSAGE_FROM_SYSTEM, - NULL, - dwError, - MAKELANGID( LANG_NEUTRAL, SUBLANG_DEFAULT ), - ( LPTSTR ) & lpMsgBuf, 0, NULL ); - if( dwLength == 0 ) - { - lpMsgBuf = _T( "internal error" ); - } - - _tcsnccpy_s( szUserBuf, _countof( szUserBuf ), lpMsgBuf, _tcslen( lpMsgBuf ) ); - LocalFree( lpMsgBuf ); - - return szUserBuf; -} - -void -vMBPortLog( eMBPortLogLevel eLevel, const TCHAR * szModule, const TCHAR * szFmt, ... ) -{ - va_list args; - static const LPTSTR arszLevel2Str[] = - { _T( "DEBUG" ), _T( "INFO" ), _T( "WARN" ), _T( "ERROR" ) }; - - _ftprintf( stderr, _T( "%s: %s: " ), arszLevel2Str[eLevel], szModule ); - - va_start( args, szFmt ); - _vftprintf( stderr, szFmt, args ); - va_end( args ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/Port/porttcp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/Port/porttcp.c deleted file mode 100644 index 0ff3f0cc2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/Port/porttcp.c +++ /dev/null @@ -1,575 +0,0 @@ -/* - * FreeModbus Libary: Win32 Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* - * Design Notes: - * - * The xMBPortTCPInit function allocates a socket and binds the socket to - * all available interfaces ( bind with INADDR_ANY ). In addition it - * creates an array of event objects which is used to check the state of - * the clients. On event object is used to handle new connections or - * closed ones. The other objects are used on a per client basis for - * processing. - */ - -#include -#include "winsock2.h" - -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- MBAP Header --------------------------------------*/ -#define MB_TCP_UID 6 -#define MB_TCP_LEN 4 -#define MB_TCP_FUNC 7 - -/* ----------------------- Defines -----------------------------------------*/ -#define MB_TCP_DEFAULT_PORT 502 /* TCP listening port. */ -#define MB_TCP_POOL_TIMEOUT 50 /* pool timeout for event waiting. */ -#define MB_TCP_READ_TIMEOUT 1000 /* Maximum timeout to wait for packets. */ -#define MB_TCP_READ_CYCLE 100 /* Time between checking for new data. */ - -#define MB_TCP_DEBUG 1 /* Set to 1 for additional debug output. */ - -#define MB_TCP_BUF_SIZE ( 256 + 7 ) /* Must hold a complete Modbus TCP frame. */ - -#define EV_CONNECTION 0 -#define EV_CLIENT 1 -#define EV_NEVENTS EV_CLIENT + 1 - -/* ----------------------- Static variables ---------------------------------*/ -SOCKET xListenSocket; -SOCKET xClientSocket; -WSAEVENT xEvents[EV_NEVENTS]; - -static UCHAR aucTCPBuf[MB_TCP_BUF_SIZE]; -static USHORT usTCPBufPos; -static USHORT usTCPFrameBytesLeft; - -/* ----------------------- External functions -------------------------------*/ -TCHAR *WsaError2String( DWORD dwError ); - -/* ----------------------- Static functions ---------------------------------*/ -BOOL prvMBTCPPortAddressToString( SOCKET xSocket, LPTSTR szAddr, USHORT usBufSize ); -LPTSTR prvMBTCPPortFrameToString( UCHAR * pucFrame, USHORT usFrameLen ); -static BOOL prvbMBPortAcceptClient( void ); -static void prvvMBPortReleaseClient( void ); -static BOOL prvMBTCPGetFrame( void ); - -/* ----------------------- Begin implementation -----------------------------*/ - -BOOL -xMBTCPPortInit( USHORT usTCPPort ) -{ - BOOL bOkay = FALSE; - USHORT usPort; - SOCKADDR_IN xService; - WSADATA wsaData; - - int i; - - if( WSAStartup( MAKEWORD( 2, 2 ), &wsaData ) != 0 ) - { - return FALSE; - } - - if( usTCPPort == 0 ) - { - usPort = MB_TCP_DEFAULT_PORT; - } - else - { - usPort = ( USHORT ) usTCPPort; - } - - xService.sin_family = AF_INET; - xService.sin_port = htons( usPort ); - xService.sin_addr.s_addr = INADDR_ANY; - - xClientSocket = INVALID_SOCKET; - for( i = 0; i < EV_NEVENTS; i++ ) - { - if( ( xEvents[i] = WSACreateEvent( ) ) == WSA_INVALID_EVENT ) - break; - } - if( i != EV_NEVENTS ) - { - vMBPortLog( MB_LOG_ERROR, _T( "TCP-POLL" ), _T( "can't create event objects: %s\r\n" ), - WsaError2String( WSAGetLastError( ) ) ); - } - else if( ( xListenSocket = socket( AF_INET, SOCK_STREAM, IPPROTO_TCP ) ) == INVALID_SOCKET ) - { - vMBPortLog( MB_LOG_ERROR, _T( "TCP-POLL" ), _T( "can't create socket: %s\r\n" ), - WsaError2String( WSAGetLastError( ) ) ); - } - else if( bind( xListenSocket, ( SOCKADDR * ) & xService, sizeof( xService ) ) == SOCKET_ERROR ) - { - vMBPortLog( MB_LOG_ERROR, _T( "TCP-POLL" ), _T( "can't bind on socket: %s\r\n" ), - WsaError2String( WSAGetLastError( ) ) ); - } - else if( listen( xListenSocket, 5 ) == SOCKET_ERROR ) - { - vMBPortLog( MB_LOG_ERROR, _T( "TCP-POLL" ), _T( "can't listen on socket: %s\r\n" ), - WsaError2String( WSAGetLastError( ) ) ); - } - else if( WSAEventSelect( xListenSocket, xEvents[EV_CONNECTION], FD_ACCEPT ) == SOCKET_ERROR ) - { - vMBPortLog( MB_LOG_ERROR, _T( "TCP-POLL" ), _T( "can't enable events on socket: %s\r\n" ), - WsaError2String( WSAGetLastError( ) ) ); - } - else - { - vMBPortLog( MB_LOG_INFO, _T( "TCP-POLL" ), _T( "Modbus TCP server listening on %S:%d\r\n" ), - inet_ntoa( xService.sin_addr ), ntohs( xService.sin_port ) ); - bOkay = TRUE; - } - - /* Perform cleanup on error. */ - if( bOkay != TRUE ) - { - for( i = 0; i < EV_NEVENTS; i++ ) - { - if( xEvents[i] != WSA_INVALID_EVENT ) - WSACloseEvent( xEvents[i] ); - } - if( xListenSocket != SOCKET_ERROR ) - closesocket( xListenSocket ); - } - - return bOkay; -} - -void -vMBTCPPortClose( ) -{ - int i; - - /* Release all event handlers. */ - for( i = 0; i < EV_NEVENTS; i++ ) - { - if( xEvents[i] != WSA_INVALID_EVENT ) - WSACloseEvent( xEvents[ i ] ); - } - /* Close all client sockets. */ - if( xClientSocket != SOCKET_ERROR ) - { - prvvMBPortReleaseClient( ); - } - /* Close the listener socket. */ - if( xListenSocket != SOCKET_ERROR ) - { - closesocket( xListenSocket ); - } - ( void )WSACleanup( ); -} - -void -vMBTCPPortDisable( void ) -{ - /* Close all client sockets. */ - if( xClientSocket != SOCKET_ERROR ) - { - prvvMBPortReleaseClient( ); - } -} - -/*! \ingroup port_win32tcp - * - * \brief Pool the listening socket and currently connected Modbus TCP clients - * for new events. - * \internal - * - * This function checks if new clients want to connect or if already connected - * clients are sending requests. If a new client is connected and there are - * still client slots left (The current implementation supports only one) - * then the connection is accepted and an event object for the new client - * socket is activated (See prvbMBPortAcceptClient() ). - * Events for already existing clients in \c FD_READ and \c FD_CLOSE. In case of - * an \c FD_CLOSE the client connection is released (See prvvMBPortReleaseClient() ). - * In case of an \c FD_READ command the existing data is read from the client - * and if a complete frame has been received the Modbus Stack is notified. - * - * \return FALSE in case of an internal I/O error. For example if the internal - * event objects are in an invalid state. Note that this does not include any - * client errors. In all other cases returns TRUE. - */ -BOOL -xMBPortTCPPool( void ) -{ - - BOOL bOkay = TRUE; - DWORD dwWaitResult; - WSANETWORKEVENTS xNetworkEvents; - int iEventNr; - int iRes; - - dwWaitResult = WSAWaitForMultipleEvents( EV_NEVENTS, xEvents, FALSE, - MB_TCP_POOL_TIMEOUT, FALSE ); - - /* Do nothing because only the timeout has expired. */ - if( ( dwWaitResult == WAIT_IO_COMPLETION ) || ( dwWaitResult == WSA_WAIT_TIMEOUT ) ) - { - } - /* Waiting for events failed. */ - else if( dwWaitResult == WSA_WAIT_FAILED ) - { - vMBPortLog( MB_LOG_ERROR, _T( "TCP-POLL" ), _T( "can't wait for network events: %s" ), - WsaError2String( WSAGetLastError( ) ) ); - bOkay = FALSE; - } - /* A event occured on one of the sockets */ - else - { - /* Get the event number for the result of the wait operation. */ - iEventNr = dwWaitResult - WSA_WAIT_EVENT_0; - - /* A client wants to connect. */ - if( iEventNr == EV_CONNECTION ) - { - if( MB_TCP_DEBUG ) - { - vMBPortLog( MB_LOG_DEBUG, _T( "TCP-POLL" ), _T( "got EV_CONNECTION event\r\n" ) ); - } - - /* Get additional event information from the socket. In addition the event - * object is reseted. - */ - iRes = WSAEnumNetworkEvents( xListenSocket, xEvents[iEventNr], &xNetworkEvents ); - if( iRes == SOCKET_ERROR ) - { - vMBPortLog( MB_LOG_ERROR, _T( "TCP-POLL" ), _T( "can't get event list: %S\r\n" ), - WsaError2String( WSAGetLastError( ) ) ); - } - else if( xNetworkEvents.lNetworkEvents & FD_ACCEPT ) - { - /* A new connection from a client. Accept it. */ - ( void )prvbMBPortAcceptClient( ); - } - } - - /* An already connected client has new data or the connection has - * been closed. */ - else if( iEventNr == EV_CLIENT ) - { - if( MB_TCP_DEBUG ) - { - vMBPortLog( MB_LOG_DEBUG, _T( "TCP-POLL" ), _T( "got EV_CLIENT event\r\n" ) ); - } - - iRes = WSAEnumNetworkEvents( xClientSocket, xEvents[iEventNr], &xNetworkEvents ); - if( iRes == SOCKET_ERROR ) - { - vMBPortLog( MB_LOG_ERROR, _T( "TCP-POLL" ), _T( "can't get event list: %s\r\n" ), - WsaError2String( WSAGetLastError( ) ) ); - } - else if( xNetworkEvents.lNetworkEvents & FD_READ ) - { - if( MB_TCP_DEBUG ) - { - vMBPortLog( MB_LOG_DEBUG, _T( "TCP-POLL" ), _T( "FD_READ event\r\n" ) ); - } - - /* Process part of the Modbus TCP frame. In case of an I/O error we have to drop - * the client connection. - */ - if( prvMBTCPGetFrame( ) != TRUE ) - { - prvvMBPortReleaseClient( ); - } - } - else if( xNetworkEvents.lNetworkEvents & FD_CLOSE ) - { - if( MB_TCP_DEBUG ) - { - vMBPortLog( MB_LOG_DEBUG, _T( "TCP-POLL" ), _T( "FD_CLOSE event\r\n" ) ); - } - - prvvMBPortReleaseClient( ); - } - else - { - vMBPortLog( MB_LOG_WARN, _T( "TCP-POLL" ), _T( "unknown EV_CLIENT event\r\n" ) ); - } - } - else - { - /* Error - Log a warning. */ - } - } - return bOkay; -} - -/*! - * \ingroup port_win32tcp - * \brief Receives parts of a Modbus TCP frame and if complete notifies - * the protocol stack. - * \internal - * - * This function reads a complete Modbus TCP frame from the protocol stack. - * It starts by reading the header with an initial request size for - * usTCPFrameBytesLeft = MB_TCP_FUNC. If the header is complete the - * number of bytes left can be calculated from it (See Length in MBAP header). - * Further read calls are issued until the frame is complete. - * - * \return \c TRUE if part of a Modbus TCP frame could be processed. In case - * of a communication error the function returns \c FALSE. - */ -BOOL -prvMBTCPGetFrame( ) -{ - BOOL bOkay = TRUE; - USHORT usLength; - int iRes; - LPTSTR szFrameAsStr; - - /* Make sure that we can safely process the next read request. If there - * is an overflow drop the client. - */ - if( ( usTCPBufPos + usTCPFrameBytesLeft ) >= MB_TCP_BUF_SIZE ) - { - vMBPortLog( MB_LOG_WARN, _T( "MBTCP-RCV" ), - _T( "Detected buffer overrun. Dropping client.\r\n" ) ); - return FALSE; - } - - iRes = recv( xClientSocket, &aucTCPBuf[usTCPBufPos], usTCPFrameBytesLeft, 0 ); - switch ( iRes ) - { - case SOCKET_ERROR: - vMBPortLog( MB_LOG_WARN, _T( "MBTCP-RCV" ), _T( "recv failed: %s\r\n" ), - WsaError2String( WSAGetLastError( ) ) ); - if( WSAGetLastError( ) != WSAEWOULDBLOCK ) - { - bOkay = FALSE; - } - break; - case 0: - bOkay = FALSE; - break; - default: - usTCPBufPos += iRes; - usTCPFrameBytesLeft -= iRes; - } - - /* If we have received the MBAP header we can analyze it and calculate - * the number of bytes left to complete the current request. If complete - * notify the protocol stack. - */ - if( usTCPBufPos >= MB_TCP_FUNC ) - { - /* Length is a byte count of Modbus PDU (function code + data) and the - * unit identifier. */ - usLength = aucTCPBuf[MB_TCP_LEN] << 8U; - usLength |= aucTCPBuf[MB_TCP_LEN + 1]; - - /* Is the frame already complete. */ - if( usTCPBufPos < ( MB_TCP_UID + usLength ) ) - { - usTCPFrameBytesLeft = usLength + MB_TCP_UID - usTCPBufPos; - } - /* The frame is complete. */ - else if( usTCPBufPos == ( MB_TCP_UID + usLength ) ) - { - if( MB_TCP_DEBUG ) - { - szFrameAsStr = prvMBTCPPortFrameToString( aucTCPBuf, usTCPBufPos ); - if( szFrameAsStr != NULL ) - { - vMBPortLog( MB_LOG_DEBUG, _T( "MBTCP-RCV" ), _T( "Received: %s\r\n" ), - szFrameAsStr ); - free( szFrameAsStr ); - } - } - ( void )xMBPortEventPost( EV_FRAME_RECEIVED ); - } - /* This can not happend because we always calculate the number of bytes - * to receive. */ - else - { - assert( usTCPBufPos <= ( MB_TCP_UID + usLength ) ); - } - } - return bOkay; -} - -BOOL -xMBTCPPortGetRequest( UCHAR ** ppucMBTCPFrame, USHORT * usTCPLength ) -{ - *ppucMBTCPFrame = &aucTCPBuf[0]; - *usTCPLength = usTCPBufPos; - - /* Reset the buffer. */ - usTCPBufPos = 0; - usTCPFrameBytesLeft = MB_TCP_FUNC; - return TRUE; -} - -BOOL -xMBTCPPortSendResponse( const UCHAR * pucMBTCPFrame, USHORT usTCPLength ) -{ - BOOL bFrameSent = FALSE; - BOOL bAbort = FALSE; - int res; - int iBytesSent = 0; - int iTimeOut = MB_TCP_READ_TIMEOUT; - LPTSTR szFrameAsStr; - - if( MB_TCP_DEBUG ) - { - szFrameAsStr = prvMBTCPPortFrameToString( aucTCPBuf, usTCPLength ); - if( szFrameAsStr != NULL ) - { - vMBPortLog( MB_LOG_DEBUG, _T( "MBTCP-SND" ), _T( "Snd: %s\r\n" ), szFrameAsStr ); - free( szFrameAsStr ); - } - } - - do - { - res = send( xClientSocket, &pucMBTCPFrame[iBytesSent], usTCPLength - iBytesSent, 0 ); - switch ( res ) - { - case SOCKET_ERROR: - if( ( WSAGetLastError( ) == WSAEWOULDBLOCK ) && ( iTimeOut > 0 ) ) - { - iTimeOut -= MB_TCP_READ_CYCLE; - Sleep( MB_TCP_READ_CYCLE ); - } - else - { - bAbort = TRUE; - } - break; - case 0: - prvvMBPortReleaseClient( ); - bAbort = TRUE; - break; - default: - iBytesSent += res; - break; - } - } - while( ( iBytesSent != usTCPLength ) && !bAbort ); - - bFrameSent = iBytesSent == usTCPLength ? TRUE : FALSE; - - return bFrameSent; -} - -void -prvvMBPortReleaseClient( ) -{ - TCHAR szIPAddr[32]; - - - if( prvMBTCPPortAddressToString( xClientSocket, szIPAddr, _countof( szIPAddr ) ) == TRUE ) - { - vMBPortLog( MB_LOG_INFO, _T( "MBTCP-CMGT" ), _T( "client %s disconnected.\r\n" ), - szIPAddr ); - } - else - { - vMBPortLog( MB_LOG_INFO, _T( "MBTCP-CMGT" ), _T( "unknown client disconnected.\r\n" ) ); - } - - /* Disable event notification for this client socket. */ - if( WSAEventSelect( xClientSocket, xEvents[EV_CLIENT], 0 ) == SOCKET_ERROR ) - { - vMBPortLog( MB_LOG_ERROR, _T( "MBTCP-CMGT" ), - _T( "can't disable events for disconnecting client socket: %s\r\n" ), - WsaError2String( WSAGetLastError( ) ) ); - } - - /* Reset event object in case an event was still pending. */ - if( WSAResetEvent( xEvents[EV_CLIENT] ) == SOCKET_ERROR ) - { - vMBPortLog( MB_LOG_ERROR, _T( "MBTCP-CMGT" ), - _T( "can't disable events for disconnecting client socket: %s\r\n" ), - WsaError2String( WSAGetLastError( ) ) ); - } - - /* Disallow the sender side. This tells the other side that we have finished. */ - if( shutdown( xClientSocket, SD_SEND ) == SOCKET_ERROR ) - { - vMBPortLog( MB_LOG_ERROR, _T( "MBTCP-CMGT" ), _T( "shutdown failed: %s\r\n" ), - WsaError2String( WSAGetLastError( ) ) ); - } - - /* Read any unread data from the socket. Note that this is not the strictly - * correct way to do it because our sockets are non blocking and therefore - * some bytes could remain. - */ - ( void )recv( xClientSocket, &aucTCPBuf[0], MB_TCP_BUF_SIZE, 0 ); - - ( void )closesocket( xClientSocket ); - xClientSocket = INVALID_SOCKET; -} - -BOOL -prvbMBPortAcceptClient( ) -{ - SOCKET xNewSocket; - BOOL bOkay; - - TCHAR szIPAddr[32]; - - /* Check if we can handle a new connection. */ - - if( xClientSocket != INVALID_SOCKET ) - { - vMBPortLog( MB_LOG_ERROR, _T( "MBTCP-CMGT" ), - _T( "can't accept new client. all connections in use.\r\n" ) ); - bOkay = FALSE; - } - else if( ( xNewSocket = accept( xListenSocket, NULL, NULL ) ) == INVALID_SOCKET ) - { - bOkay = FALSE; - } - /* Register READ events on the socket file descriptor. */ - else if( WSAEventSelect( xNewSocket, xEvents[EV_CLIENT], FD_READ | FD_CLOSE ) == SOCKET_ERROR ) - { - bOkay = FALSE; - ( void )closesocket( xNewSocket ); - } - /* Everything okay - Register the client connection. */ - else - { - xClientSocket = xNewSocket; - usTCPBufPos = 0; - usTCPFrameBytesLeft = MB_TCP_FUNC; - - if( prvMBTCPPortAddressToString( xClientSocket, szIPAddr, _countof( szIPAddr ) ) == TRUE ) - { - vMBPortLog( MB_LOG_INFO, _T( "MBTCP-CMGT" ), _T( "accepted new client %s.\r\n" ), - szIPAddr ); - } - else - { - vMBPortLog( MB_LOG_INFO, _T( "MBTCP-CMGT" ), _T( "accepted unknown client.\r\n" ) ); - } - bOkay = TRUE; - - } - return bOkay; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/demo.cpp b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/demo.cpp deleted file mode 100644 index b2f4096e4..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/demo.cpp +++ /dev/null @@ -1,292 +0,0 @@ -/* - * FreeModbus Libary: Win32 Demo Application - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id: demo.cpp,v 1.2 2006/06/26 19:24:07 wolti Exp $ - */ - -#include "stdafx.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define PROG _T("freemodbus") - -#define REG_INPUT_START 1000 -#define REG_INPUT_NREGS 4 -#define REG_HOLDING_START 2000 -#define REG_HOLDING_NREGS 130 - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegInputStart = REG_INPUT_START; -static USHORT usRegInputBuf[REG_INPUT_NREGS]; -static USHORT usRegHoldingStart = REG_HOLDING_START; -static USHORT usRegHoldingBuf[REG_HOLDING_NREGS]; - -static HANDLE hPollThread; -static CRITICAL_SECTION hPollLock; -static enum ThreadState -{ - STOPPED, - RUNNING, - SHUTDOWN -} ePollThreadState; - -/* ----------------------- Static functions ---------------------------------*/ -static BOOL bCreatePollingThread( void ); -static enum ThreadState eGetPollingThreadState( void ); -static void eSetPollingThreadState( enum ThreadState eNewState ); -static DWORD WINAPI dwPollingThread( LPVOID lpParameter ); - -/* ----------------------- Start implementation -----------------------------*/ -int -_tmain( int argc, _TCHAR * argv[] ) -{ - int iExitCode; - TCHAR cCh; - BOOL bDoExit; - - if( eMBTCPInit( MB_TCP_PORT_USE_DEFAULT ) != MB_ENOERR ) - { - _ftprintf( stderr, _T( "%s: can't initialize modbus stack!\r\n" ), PROG ); - iExitCode = EXIT_FAILURE; - } - else - { - /* Create synchronization primitives and set the current state - * of the thread to STOPPED. - */ - InitializeCriticalSection( &hPollLock ); - eSetPollingThreadState( STOPPED ); - - /* CLI interface. */ - _tprintf( _T( "Type 'q' for quit or 'h' for help!\r\n" ) ); - bDoExit = FALSE; - do - { - _tprintf( _T( "> " ) ); - cCh = _gettchar( ); - switch ( cCh ) - { - case _TCHAR( 'q' ): - bDoExit = TRUE; - break; - case _TCHAR( 'd' ): - eSetPollingThreadState( SHUTDOWN ); - break; - case _TCHAR( 'e' ): - if( bCreatePollingThread( ) != TRUE ) - { - _tprintf( _T( "Can't start protocol stack! Already running?\r\n" ) ); - } - break; - case _TCHAR( 's' ): - switch ( eGetPollingThreadState( ) ) - { - case RUNNING: - _tprintf( _T( "Protocol stack is running.\r\n" ) ); - break; - case STOPPED: - _tprintf( _T( "Protocol stack is stopped.\r\n" ) ); - break; - case SHUTDOWN: - _tprintf( _T( "Protocol stack is shuting down.\r\n" ) ); - break; - } - break; - case _TCHAR( 'h' ): - _tprintf( _T( "FreeModbus demo application help:\r\n" ) ); - _tprintf( _T( " 'd' ... disable protocol stack.\r\n" ) ); - _tprintf( _T( " 'e' ... enabled the protocol stack\r\n" ) ); - _tprintf( _T( " 's' ... show current status\r\n" ) ); - _tprintf( _T( " 'q' ... quit applicationr\r\n" ) ); - _tprintf( _T( " 'h' ... this information\r\n" ) ); - _tprintf( _T( "\r\n" ) ); - _tprintf( _T( "Copyright 2006 Christian Walter \r\n" ) ); - break; - default: - if( cCh != _TCHAR('\n') ) - { - _tprintf( _T( "illegal command '%c'!\r\n" ), cCh ); - } - break; - } - - /* eat up everything untill return character. */ - while( cCh != '\n' ) - { - cCh = _gettchar( ); - } - } - while( !bDoExit ); - - /* Release hardware resources. */ - ( void )eMBClose( ); - iExitCode = EXIT_SUCCESS; - } - return iExitCode; -} - -BOOL -bCreatePollingThread( void ) -{ - BOOL bResult; - - if( eGetPollingThreadState( ) == STOPPED ) - { - if( ( hPollThread = CreateThread( NULL, 0, dwPollingThread, NULL, 0, NULL ) ) == NULL ) - { - /* Can't create the polling thread. */ - bResult = FALSE; - } - else - { - bResult = TRUE; - } - } - else - { - bResult = FALSE; - } - - return bResult; -} - -DWORD WINAPI -dwPollingThread( LPVOID lpParameter ) -{ - eSetPollingThreadState( RUNNING ); - - if( eMBEnable( ) == MB_ENOERR ) - { - do - { - if( eMBPoll( ) != MB_ENOERR ) - break; - } - while( eGetPollingThreadState( ) != SHUTDOWN ); - } - - ( void )eMBDisable( ); - - eSetPollingThreadState( STOPPED ); - - return 0; -} - -enum ThreadState -eGetPollingThreadState( ) -{ - enum ThreadState eCurState; - - EnterCriticalSection( &hPollLock ); - eCurState = ePollThreadState; - LeaveCriticalSection( &hPollLock ); - - return eCurState; -} - -void -eSetPollingThreadState( enum ThreadState eNewState ) -{ - EnterCriticalSection( &hPollLock ); - ePollThreadState = eNewState; - LeaveCriticalSection( &hPollLock ); -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_HOLDING_START ) && - ( usAddress + usNRegs <= REG_HOLDING_START + REG_HOLDING_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegHoldingStart ); - switch ( eMode ) - { - /* Pass current register values to the protocol stack. */ - case MB_REG_READ: - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( UCHAR ) ( usRegHoldingBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( UCHAR ) ( usRegHoldingBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - break; - - /* Update current register values with new values from the - * protocol stack. */ - case MB_REG_WRITE: - while( usNRegs > 0 ) - { - usRegHoldingBuf[iRegIndex] = *pucRegBuffer++ << 8; - usRegHoldingBuf[iRegIndex] |= *pucRegBuffer++; - iRegIndex++; - usNRegs--; - } - } - } - else - { - eStatus = MB_ENOREG; - } - return eStatus; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/demo.vcproj b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/demo.vcproj deleted file mode 100644 index 480da7997..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/demo.vcproj +++ /dev/null @@ -1,317 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/stdafx.cpp b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/stdafx.cpp deleted file mode 100644 index d4c4f7eb8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/stdafx.cpp +++ /dev/null @@ -1,22 +0,0 @@ -/* - * FreeModbus Libary: Win32TCP Demo Application - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id: stdafx.cpp,v 1.1 2006/06/25 00:20:19 wolti Exp $ - */ - -#include "stdafx.h" diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/stdafx.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/stdafx.h deleted file mode 100644 index 75a86e7c1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/WIN32TCP/stdafx.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * FreeModbus Libary: Win32TCP Demo Application - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#pragma once - -#define WIN32_LEAN_AND_MEAN -#include -#include -#include -#include diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/README.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/README.txt deleted file mode 100644 index e0c457c9d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/README.txt +++ /dev/null @@ -1,53 +0,0 @@ - - FREEMODBUS 1.1 Z8Encore PORT - ============================ - -REQUIREMENTS -============ - -This demo application provides a port for the Z8 Encore! family of - microcontrollers from Zilog[1]. The microcontroller used was the Z8F6422. - -It requires a wired serial port to a host processor and a Modbus Master -Software on the PC side to be useful. Demo versions of Modbus Masters -can be found in [2] and [3]. - -SOURCE -====== - -If one wants to recompile the software, the ZDS II - Z8 Encore! 4.10.1 -should be installed. The ZDS II - Z8 Encore! can be found at [4]. The -project is for the Z8F6422 microcontroller, but has been tested with -Z8F1622. - -* The ASCII mode was disabled so flash memory of Z8F1622 was enough. - - -TESTING -======= - -Start the Modbus Sample Application and test if the input registers -starting at protocol address 1000 can be read. There are four registers -value available and the output should look like: - -Polling slave (Ctrl-C to stop) ... -[1000]: 6474 -[1001]: 0 -[1002]: 0 -[1003]: 0 -Polling slave (Ctrl-C to stop) ... -[1000]: -8831 -[1001]: 0 -[1002]: 0 -[1003]: 0 -Polling slave (Ctrl-C to stop) ... - -The simple testing utility used in the 'demo_rtu.bat' script can be found -at [5]. - - -[1] Zilog - Z8Encore 64K series: http://www.zilog.com/products/family.asp?fam=225 -[2] WinTech ModScan32: http://www.win-tech.com/html/modscan32.htm -[3] Modus Poll: http://www.modbustools.com/modbus_poll.asp -[4] ZDS II - Z8 Encore!: http://www.zilog.com/software/zds2.asp -[5] FieldTalk Modpoll: http://www.focus-sw.com/fieldtalk/modpoll.html diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/demo.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/demo.c deleted file mode 100644 index 109fdd317..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/demo.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * FreeModbus Libary: LPC214X Port - * Copyright (C) 2007 Tiago Prado Lone - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define REG_INPUT_START 1000 -#define REG_INPUT_NREGS 4 - -/* ----------------------- Static variables ---------------------------------*/ -static USHORT usRegInputStart = REG_INPUT_START; -static USHORT usRegInputBuf[REG_INPUT_NREGS]; - -/* ----------------------- Start implementation -----------------------------*/ -int -main( void ) -{ - eMBErrorCode eStatus; - - eStatus = eMBInit( MB_RTU, 0x0A, 0, 38400, MB_PAR_EVEN ); - - /* Enable the Modbus Protocol Stack. */ - eStatus = eMBEnable( ); - - for( ;; ) - { - ( void )eMBPoll( ); - - /* Here we simply count the number of poll cycles. */ - usRegInputBuf[0]++; - } -} - -eMBErrorCode -eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs ) -{ - eMBErrorCode eStatus = MB_ENOERR; - int iRegIndex; - - if( ( usAddress >= REG_INPUT_START ) - && ( usAddress + usNRegs <= REG_INPUT_START + REG_INPUT_NREGS ) ) - { - iRegIndex = ( int )( usAddress - usRegInputStart ); - while( usNRegs > 0 ) - { - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] >> 8 ); - *pucRegBuffer++ = ( unsigned char )( usRegInputBuf[iRegIndex] & 0xFF ); - iRegIndex++; - usNRegs--; - } - } - else - { - eStatus = MB_ENOREG; - } - - return eStatus; -} - -eMBErrorCode -eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNRegs, eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - - -eMBErrorCode -eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNCoils, eMBRegisterMode eMode ) -{ - return MB_ENOREG; -} - -eMBErrorCode -eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, USHORT usNDiscrete ) -{ - return MB_ENOREG; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/demo.wsp b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/demo.wsp deleted file mode 100644 index 041c317f8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/demo.wsp +++ /dev/null @@ -1,540 +0,0 @@ -[WorkState_v1_1] -ptn_Child1=DockState -ptn_Child2=ToolBarMgr -ptn_Child3=Frames - -[WorkState_v1_1.DockState] -Bars=15 -ScreenCX=1280 -ScreenCY=1024 -ptn_Child1=Bar-0 -ptn_Child10=Bar-9 -ptn_Child11=Bar-10 -ptn_Child12=Bar-11 -ptn_Child13=Bar-12 -ptn_Child14=Bar-13 -ptn_Child15=Bar-14 -ptn_Child2=Bar-1 -ptn_Child3=Bar-2 -ptn_Child4=Bar-3 -ptn_Child5=Bar-4 -ptn_Child6=Bar-5 -ptn_Child7=Bar-6 -ptn_Child8=Bar-7 -ptn_Child9=Bar-8 - -[WorkState_v1_1.DockState.Bar-0] -BarID=59393 -ClassName=SECCustomStatusBar -DockingStyle=0 -ExStyle=0 -MDIChild=False -MRUDockingState=0 -MRUFloatCX=0 -MRUFloatCY=0 -MRUHorzDockCX=0 -MRUHorzDockCY=0 -MRUVertDockCX=0 -MRUVertDockCY=0 -PctWidth=1000000 -PrevFloating=False -ResourceID=0 -Style=32768 -TypeID=0 -WindowName=Saving workspace... - -[WorkState_v1_1.DockState.Bar-1] -Bar#0=0 -Bar#1=59647 -Bar#10=59400 -Bar#11=59408 -Bar#12=0 -Bar#2=0 -Bar#3=59392 -Bar#4=59396 -Bar#5=59397 -Bar#6=0 -Bar#7=59398 -Bar#8=59399 -Bar#9=0 -BarID=59419 -Bars=13 -ClassName= -DockingStyle=0 -ExStyle=0 -MDIChild=False -MRUDockingState=0 -MRUFloatCX=0 -MRUFloatCY=0 -MRUHorzDockCX=0 -MRUHorzDockCY=0 -MRUVertDockCX=0 -MRUVertDockCY=0 -PctWidth=0 -PrevFloating=False -ResourceID=0 -Style=0 -TypeID=0 -WindowName= - -[WorkState_v1_1.DockState.Bar-10] -BarID=59397 -ClassName=SECCustomToolBar -Docking=True -DockingStyle=61440 -ExStyle=780 -MDIChild=False -MRUDockBottomPos=57 -MRUDockID=0 -MRUDockLeftPos=783 -MRUDockRightPos=975 -MRUDockTopPos=26 -MRUDockingState=0 -MRUFloatCX=0 -MRUFloatCY=0 -MRUFloatStyle=8196 -MRUFloatXPos=-2147483648 -MRUFloatYPos=0 -MRUHorzDockCX=192 -MRUHorzDockCY=31 -MRUVertDockCX=0 -MRUVertDockCY=0 -PctWidth=500000 -PrevFloating=False -ResourceID=0 -Style=12212 -TypeID=14946 -WindowName=Find -XPos=783 -YPos=26 -ptn_Child1=ToolBarInfoEx - -[WorkState_v1_1.DockState.Bar-10.ToolBarInfoEx] -Buttons=KDAIAAAAAAECBOAAAACAGJAA -Title=Find - -[WorkState_v1_1.DockState.Bar-11] -BarID=59398 -ClassName=SECCustomToolBar -Docking=True -DockingStyle=61440 -ExStyle=780 -MDIChild=False -MRUDockBottomPos=88 -MRUDockID=0 -MRUDockLeftPos=-1 -MRUDockRightPos=395 -MRUDockTopPos=57 -MRUDockingState=0 -MRUFloatCX=0 -MRUFloatCY=0 -MRUFloatStyle=8196 -MRUFloatXPos=-2147483648 -MRUFloatYPos=0 -MRUHorzDockCX=396 -MRUHorzDockCY=31 -MRUVertDockCX=0 -MRUVertDockCY=0 -PctWidth=500000 -PrevFloating=False -ResourceID=0 -Style=12212 -TypeID=14946 -Visible=False -WindowName=Debug -YPos=57 -ptn_Child1=ToolBarInfoEx - -[WorkState_v1_1.DockState.Bar-11.ToolBarInfoEx] -Buttons=APAIAAAAAAEBBIAAAAAAAAAAAAAAAAKIAIAAAAAANBAIAAAAAAAAAAAAAAAAMHAIAAAAAALBAIAAAAAALIAIAAAAAAAAAAAAAAAAIBAIAAAAAAJBAIAAAAAAKBAIAAAAAAONAIAAAAAAAAAAAAAAAAJEAIAAAAAALNAIAAAAAAMNAIAAAAAALFAIAAAAAA -Title=Debug - -[WorkState_v1_1.DockState.Bar-12] -BarID=59400 -ClassName=SECCustomToolBar -Docking=True -DockingStyle=61440 -ExStyle=780 -MDIChild=False -MRUDockBottomPos=88 -MRUDockID=0 -MRUDockLeftPos=-1 -MRUDockRightPos=364 -MRUDockTopPos=57 -MRUDockingState=0 -MRUFloatCX=0 -MRUFloatCY=0 -MRUFloatStyle=8196 -MRUFloatXPos=-2147483648 -MRUFloatYPos=0 -MRUHorzDockCX=365 -MRUHorzDockCY=31 -MRUVertDockCX=0 -MRUVertDockCY=0 -PctWidth=1000000 -PrevFloating=False -ResourceID=0 -Style=12212 -TypeID=14946 -WindowName=Command Processor -YPos=57 -ptn_Child1=ToolBarInfoEx - -[WorkState_v1_1.DockState.Bar-12.ToolBarInfoEx] -Buttons=PJAIAAAAAAIABIAAAAAABKAIAAAACAMCBA -Title=Command Processor - -[WorkState_v1_1.DockState.Bar-13] -BarID=59408 -ClassName=SECCustomToolBar -Docking=True -DockingStyle=61440 -ExStyle=780 -MDIChild=False -MRUDockBottomPos=119 -MRUDockID=0 -MRUDockLeftPos=364 -MRUDockRightPos=475 -MRUDockTopPos=88 -MRUDockingState=0 -MRUFloatCX=0 -MRUFloatCY=0 -MRUFloatStyle=8196 -MRUFloatXPos=-2147483648 -MRUFloatYPos=0 -MRUHorzDockCX=111 -MRUHorzDockCY=31 -MRUVertDockCX=0 -MRUVertDockCY=0 -PctWidth=500000 -PrevFloating=False -ResourceID=0 -Style=12212 -TypeID=14946 -Visible=False -WindowName=Bookmarks -XPos=364 -YPos=88 -ptn_Child1=ToolBarInfoEx - -[WorkState_v1_1.DockState.Bar-13.ToolBarInfoEx] -Buttons=DOPKAAAAAAEOPKAAAAAAFOPKAAAAAAGOPKAAAAAA -Title=Bookmarks - -[WorkState_v1_1.DockState.Bar-14] -BarID=59399 -ClassName=SECCustomToolBar -Docking=True -DockingStyle=61440 -ExStyle=780 -MDIChild=False -MRUDockBottomPos=88 -MRUDockID=0 -MRUDockLeftPos=395 -MRUDockRightPos=644 -MRUDockTopPos=57 -MRUDockingState=0 -MRUFloatCX=0 -MRUFloatCY=0 -MRUFloatStyle=8196 -MRUFloatXPos=-2147483648 -MRUFloatYPos=0 -MRUHorzDockCX=249 -MRUHorzDockCY=31 -MRUVertDockCX=0 -MRUVertDockCY=0 -PctWidth=1000000 -PrevFloating=False -ResourceID=0 -Style=12212 -TypeID=14946 -Visible=False -WindowName=Debug Windows -XPos=395 -YPos=57 -ptn_Child1=ToolBarInfoEx - -[WorkState_v1_1.DockState.Bar-14.ToolBarInfoEx] -Buttons=EJAIAAAAAAGLAIAAAAAADJAIAAAAAAGNAIAAAAAAIJAIAAAAAAJJAIAAAAAACNAIAAAAAANJAIAAAAAAKJAIAAAAAAOABIAAAAAA -Title=Debug Windows - -[WorkState_v1_1.DockState.Bar-2] -Bar#0=0 -Bar#1=59139 -Bar#2=0 -BarID=59422 -Bars=3 -ClassName= -DockingStyle=0 -ExStyle=0 -MDIChild=False -MRUDockingState=0 -MRUFloatCX=0 -MRUFloatCY=0 -MRUHorzDockCX=0 -MRUHorzDockCY=0 -MRUVertDockCX=0 -MRUVertDockCY=0 -PctWidth=0 -PrevFloating=False -ResourceID=0 -Style=0 -TypeID=0 -WindowName= - -[WorkState_v1_1.DockState.Bar-3] -Bar#0=0 -Bar#1=59140 -Bar#2=0 -BarID=59420 -Bars=3 -ClassName= -DockingStyle=0 -ExStyle=0 -MDIChild=False -MRUDockingState=0 -MRUFloatCX=0 -MRUFloatCY=0 -MRUHorzDockCX=0 -MRUHorzDockCY=0 -MRUVertDockCX=0 -MRUVertDockCY=0 -PctWidth=0 -PrevFloating=False -ResourceID=0 -Style=0 -TypeID=0 -WindowName= - -[WorkState_v1_1.DockState.Bar-4] -Bar#0=0 -Bar#1=38006 -Bar#10=38121 -Bar#11=38120 -Bar#12=38109 -Bar#13=38108 -Bar#14=38107 -Bar#15=38106 -Bar#16=38105 -Bar#17=38104 -Bar#18=38103 -Bar#19=38102 -Bar#2=38129 -Bar#20=38101 -Bar#21=38100 -Bar#22=38001 -Bar#23=38003 -Bar#24=38004 -Bar#25=38002 -Bar#26=38000 -Bar#27=38005 -Bar#28=0 -Bar#3=38128 -Bar#4=38127 -Bar#5=38126 -Bar#6=38125 -Bar#7=38124 -Bar#8=38123 -Bar#9=38122 -BarID=59421 -Bars=29 -ClassName= -DockingStyle=0 -ExStyle=0 -MDIChild=False -MRUDockingState=0 -MRUFloatCX=0 -MRUFloatCY=0 -MRUHorzDockCX=0 -MRUHorzDockCY=0 -MRUVertDockCX=0 -MRUVertDockCY=0 -PctWidth=0 -PrevFloating=False -ResourceID=0 -Style=0 -TypeID=0 -WindowName= - -[WorkState_v1_1.DockState.Bar-5] -BarID=59139 -ClassName=BaseControlBar -Docking=True -DockingStyle=61440 -ExStyle=3889 -MDIChild=False -MRUDockBottomPos=135 -MRUDockID=0 -MRUDockLeftPos=1 -MRUDockRightPos=1280 -MRUDockTopPos=5 -MRUDockingState=0 -MRUFloatCX=300 -MRUFloatCY=180 -MRUFloatStyle=4 -MRUFloatXPos=-2147483648 -MRUFloatYPos=1836412015 -MRUHorzDockCX=1279 -MRUHorzDockCY=130 -MRUVertDockCX=300 -MRUVertDockCY=180 -PctWidth=1000000 -PrevFloating=False -ResourceID=0 -Style=36756 -TypeID=0 -WindowName=Output -XPos=1 -YPos=5 - -[WorkState_v1_1.DockState.Bar-6] -BarID=59140 -ClassName=WorkspaceBar -Docking=True -DockingStyle=61440 -ExStyle=3889 -MDIChild=False -MRUDockBottomPos=731 -MRUDockID=0 -MRUDockLeftPos=0 -MRUDockRightPos=180 -MRUDockTopPos=-2 -MRUDockingState=0 -MRUFloatCX=300 -MRUFloatCY=180 -MRUFloatStyle=4 -MRUFloatXPos=-2147483648 -MRUFloatYPos=0 -MRUHorzDockCX=300 -MRUHorzDockCY=180 -MRUVertDockCX=180 -MRUVertDockCY=733 -PctWidth=1000000 -PrevFloating=False -ResourceID=0 -Style=8084 -TypeID=0 -WindowName=Project Workspace -XPos=0 -YPos=-2 - -[WorkState_v1_1.DockState.Bar-7] -BarID=59647 -ClassName=SECMDIMenuBar -Docking=True -DockingStyle=61440 -ExStyle=908 -MDIChild=False -MRUDockBottomPos=26 -MRUDockID=0 -MRUDockLeftPos=-1 -MRUDockRightPos=1279 -MRUDockTopPos=-1 -MRUDockingState=0 -MRUFloatCX=0 -MRUFloatCY=0 -MRUFloatStyle=8196 -MRUFloatXPos=-2147483648 -MRUFloatYPos=0 -MRUHorzDockCX=1280 -MRUHorzDockCY=27 -MRUVertDockCX=0 -MRUVertDockCY=0 -PctWidth=1000000 -PrevFloating=False -ResourceID=0 -Style=12220 -TypeID=14947 -WindowName=Menu bar -ptn_Child1=ToolBarInfoEx - -[WorkState_v1_1.DockState.Bar-7.ToolBarInfoEx] -Buttons=BAAAAAAIAACAAAAAAIAADAAAAAAIAAEAAAAAAIAAFAAAAAAIAAGAAAAAAIAAHAAAAAAIAAIAAAAAAIAAJAAAAAAIAA -Title=Menu bar - -[WorkState_v1_1.DockState.Bar-8] -BarID=59392 -ClassName=SECCustomToolBar -Docking=True -DockingStyle=61440 -ExStyle=780 -MDIChild=False -MRUDockBottomPos=57 -MRUDockID=0 -MRUDockLeftPos=-1 -MRUDockRightPos=295 -MRUDockTopPos=26 -MRUDockingState=0 -MRUFloatCX=0 -MRUFloatCY=0 -MRUFloatStyle=8196 -MRUFloatXPos=-2147483648 -MRUFloatYPos=0 -MRUHorzDockCX=296 -MRUHorzDockCY=31 -MRUVertDockCX=0 -MRUVertDockCY=0 -PctWidth=250000 -PrevFloating=False -ResourceID=0 -Style=12212 -TypeID=14946 -WindowName=File -YPos=26 -ptn_Child1=ToolBarInfoEx - -[WorkState_v1_1.DockState.Bar-8.ToolBarInfoEx] -Buttons=AABOAAAAAABABOAAAAAADABOAAAAAAMBAIAAAAAAAAAAAAAAAADCBOAAAAAACCBOAAAAAAFCBOAAAAAAACBOAAAAAAAAAAAAAAAAHABOAAAAAAAAAAAAAAAADBAIAAAAAAKAAIAAAAAA -Title=File - -[WorkState_v1_1.DockState.Bar-9] -BarID=59396 -ClassName=SECCustomToolBar -Docking=True -DockingStyle=61440 -ExStyle=780 -MDIChild=False -MRUDockBottomPos=57 -MRUDockID=0 -MRUDockLeftPos=295 -MRUDockRightPos=783 -MRUDockTopPos=26 -MRUDockingState=0 -MRUFloatCX=0 -MRUFloatCY=0 -MRUFloatStyle=8196 -MRUFloatXPos=-2147483648 -MRUFloatYPos=0 -MRUHorzDockCX=488 -MRUHorzDockCY=31 -MRUVertDockCX=0 -MRUVertDockCY=0 -PctWidth=250000 -PrevFloating=False -ResourceID=0 -Style=12212 -TypeID=14946 -WindowName=Build -XPos=295 -YPos=26 -ptn_Child1=ToolBarInfoEx - -[WorkState_v1_1.DockState.Bar-9.ToolBarInfoEx] -Buttons=HIAIAAAACAIMAAAAAAAAAAAAIGAIAAAAAAFGAIAAAAAAGGAIAAAAAAOHAIAAAAAAAAAAAAAAAAPOAIAAAAAAAPAIAAAAAAKIAIAAAAAAMHAIAAAAAAJEAIAAAAAALNAIAAAAAALFAIAAAAAA -Title=Build - -[WorkState_v1_1.Frames] -ptn_Child1=MainFrame -ptn_Child2=ChildFrames - -[WorkState_v1_1.Frames.ChildFrames] - -[WorkState_v1_1.Frames.MainFrame] -Title=demo -- ZDS II - Z8 Encore! Family -WindowPlacement=MCAAAAAACAAAAAAADAAAAAAAPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPAAAAAAAAAAAAAAAAIAEAAAAAIADAAAAA - -[WorkState_v1_1.ToolBarMgr] -CoolLook=True -LargeButtons=False -ToolTips=True - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/demo.zdsproj b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/demo.zdsproj deleted file mode 100644 index 348f5cfee..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/demo.zdsproj +++ /dev/null @@ -1,298 +0,0 @@ - -Z8F6422 - - - -.\demo.c -port\portevent.c -port\portserial.c -port\porttimer.c -..\..\modbus\mb.c -..\..\modbus\ascii\mbascii.c -..\..\modbus\functions\mbfunccoils.c -..\..\modbus\functions\mbfuncdiag.c -..\..\modbus\functions\mbfuncdisc.c -..\..\modbus\functions\mbfuncholding.c -..\..\modbus\functions\mbfuncinput.c -..\..\modbus\functions\mbfuncother.c -..\..\modbus\functions\mbutils.c -..\..\modbus\rtu\mbcrc.c -..\..\modbus\rtu\mbrtu.c -..\..\modbus\tcp\mbtcp.c - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -000000000000 -000000000000 -0 - - -000000000000 -000000000000 -0 - - -000000000000 -000000000000 -0 - - -000000000000 -000000000000 -0 - - - - \ No newline at end of file diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/port/port.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/port/port.h deleted file mode 100644 index 8bc52e00c..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/port/port.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * FreeModbus Libary: Z8Encore Port for Z8F6422 - * Copyright (C) 2007 Tiago Prado Lone - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _PORT_H -#define _PORT_H - -#include - -#include - -#define INLINE -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#define CLOCK 18432000 - -#define ENTER_CRITICAL_SECTION( ) DI() -#define EXIT_CRITICAL_SECTION( ) EI() - -typedef unsigned char BOOL; - -typedef unsigned char UCHAR; -typedef char CHAR; - -typedef unsigned int USHORT; -typedef int SHORT; - -typedef unsigned long ULONG; -typedef long LONG; - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/port/portevent.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/port/portevent.c deleted file mode 100644 index 89b035dfd..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/port/portevent.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * FreeModbus Libary: Z8Encore Port for Z8F6422 - * Copyright (C) 2007 Tiago Prado Lone - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static eMBEventType eQueuedEvent; -static BOOL xEventInQueue; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - xEventInQueue = FALSE; - return TRUE; -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - xEventInQueue = TRUE; - eQueuedEvent = eEvent; - return TRUE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - BOOL xEventHappened = FALSE; - - if( xEventInQueue ) - { - *eEvent = eQueuedEvent; - xEventInQueue = FALSE; - xEventHappened = TRUE; - } - return xEventHappened; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/port/portserial.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/port/portserial.c deleted file mode 100644 index 036e72046..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/port/portserial.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - * FreeModbus Libary: Z8Encore Port for Z8F6422 - * Copyright (C) 2007 Tiago Prado Lone - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -#define PORTA_UART_RXD 0x10 -#define PORTA_UART_TXD 0x20 - -#define RX_ENABLE 0x40 -#define TX_ENABLE 0x80 - -#define UART0_RXD_INT_PENDING 0x10 -#define UART0_TXD_INT_PENDING 0x08 - -#define UART0_RXD_INT_EN_H 0x10 -#define UART0_RXD_INT_EN_L 0x10 -#define UART0_TXD_INT_EN_H 0x08 -#define UART0_TXD_INT_EN_L 0x08 - -#define UART_PARITY_ODD 0x18 -#define UART_PARITY_EVEN 0x10 - -#define UART_ERRORS 0x70 - - -/* ----------------------- static functions ---------------------------------*/ -static void interrupt prvvUARTTxReadyISR( void ); -static void interrupt prvvUARTRxISR( void ); - -/* ----------------------- Start implementation -----------------------------*/ -void -vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable ) -{ - /* If xRXEnable enable serial receive interrupts. If xTxENable enable - * transmitter empty interrupts. - */ - if( xRxEnable ) - { - IRQ0ENL |= UART0_RXD_INT_EN_L; - } - else - { - IRQ0ENL &= ~UART0_RXD_INT_EN_L; - } - if( xTxEnable ) - { - IRQ0ENL |= UART0_TXD_INT_EN_L; - /* Force Tx Interruption */ - IRQ0 |= UART0_TXD_INT_PENDING; - } - else - { - IRQ0ENL &= ~UART0_TXD_INT_EN_L; - } -} - -BOOL -xMBPortSerialInit( UCHAR ucPORT, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity ) -{ - UCHAR cfg = 0; - - if( ucDataBits != 8 ) - { - return FALSE; - } - - switch ( eParity ) - { - case MB_PAR_NONE: - break; - - case MB_PAR_ODD: - cfg |= UART_PARITY_ODD; - break; - - case MB_PAR_EVEN: - cfg |= UART_PARITY_EVEN; - break; - - default: - return FALSE; - } - - /* Baud Rate -> U0BR = (CLOCK/(16*BAUD) */ - U0BRH = CLOCK / ( 16 * ulBaudRate ) >> 8; - U0BRL = CLOCK / ( 16 * ulBaudRate ) & 0x00FF; - - /* Enable Alternate Function of UART Pins */ - PAAF |= PORTA_UART_RXD | PORTA_UART_TXD; - - /* Disable Interrupts */ - DI( ); - - /* Configure Stop Bits, Parity and Enable Rx/Tx */ - U0CTL0 = cfg | RX_ENABLE | TX_ENABLE; - U0CTL1 = 0x00; - - /* Low Priority Rx/Tx Interrupts */ - IRQ0ENH &= ~UART0_TXD_INT_EN_H & ~UART0_RXD_INT_EN_H; - - vMBPortSerialEnable( FALSE, FALSE ); - - /* Set Rx/Tx Interruption Vectors */ - SET_VECTOR( UART0_RX, prvvUARTRxISR ); - SET_VECTOR( UART0_TX, prvvUARTTxReadyISR ); - - /* Enable Interrupts */ - EI( ); - - return TRUE; -} - -BOOL -xMBPortSerialPutByte( CHAR ucByte ) -{ - /* Put a byte in the UARTs transmit buffer. This function is called - * by the protocol stack if pxMBFrameCBTransmitterEmpty( ) has been - * called. */ - while( !( U0STAT0 & 0x04 ) ) - { - } - - U0D = ucByte; - - return TRUE; -} - -BOOL -xMBPortSerialGetByte( CHAR * pucByte ) -{ - /* Return the byte in the UARTs receive buffer. This function is called - * by the protocol stack after pxMBFrameCBByteReceived( ) has been called. - */ - while( !( U0STAT0 & 0x80 ) ) - { - } - - *pucByte = U0D; - - return TRUE; -} - -/* - * Create an interrupt handler for the transmit buffer empty interrupt - * (or an equivalent) for your target processor. This function should then - * call pxMBFrameCBTransmitterEmpty( ) which tells the protocol stack that - * a new character can be sent. The protocol stack will then call - * xMBPortSerialPutByte( ) to send the character. - */ -static unsigned int uiCnt = 0; - -static void interrupt -prvvUARTTxReadyISR( void ) -{ - pxMBFrameCBTransmitterEmpty( ); - - IRQ0 &= ~UART0_TXD_INT_PENDING; -} - - -/* - * Create an interrupt handler for the receive interrupt for your target - * processor. This function should then call pxMBFrameCBByteReceived( ). The - * protocol stack will then call xMBPortSerialGetByte( ) to retrieve the - * character. - */ -static void interrupt -prvvUARTRxISR( void ) -{ - UCHAR tmp; - - /* Verify UART error flags */ - if( U0STAT0 & UART_ERRORS ) - { - tmp = U0D; - } - else - { - pxMBFrameCBByteReceived( ); - } - - IRQ0 &= ~UART0_RXD_INT_PENDING; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/port/porttimer.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/port/porttimer.c deleted file mode 100644 index bb3e50a7d..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/demo/Z8ENCORE/port/porttimer.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * FreeModbus Libary: Z8Encore Port for Z8F6422 - * Copyright (C) 2007 Tiago Prado Lone - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Platform includes --------------------------------*/ -#include "port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- static functions ---------------------------------*/ -static void interrupt prvvTIMERExpiredISR( void ); - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortTimersInit( USHORT usTim1Timerout50us ) -{ - /* Configure Timer 0 (One Shot, Prescale = 1, Disabled) - * - * Timer Control #00000000b - * || ||_|_______ One Shot - * Disabled = 0 __||_|_____________/1 Prescale - * */ - T0CTL1 = 0x00; - - T0H = 0x00; - T0L = 0x00; - - /* Time = (reload x prescale)/CLOCK - * reload = (Time*CLOCK)/prescale - * 50us = CLOCK/20000 - * reload = usTim1Timerout50us*(CLOCK/20000) - */ - T0CPH = ( usTim1Timerout50us * ( CLOCK / 20000 ) ) >> 8; - T0CPL = ( usTim1Timerout50us * ( CLOCK / 20000 ) ) & 0x00FF; - - IRQ0ENH |= 0x20; - IRQ0ENL |= 0x20; /* Enable Timer0 High Priority */ - - /* Set Interrupt Vector */ - SET_VECTOR( TIMER0, prvvTIMERExpiredISR ); - - return TRUE; -} - - -void -vMBPortTimersEnable( ) -{ - T0H = 0x00; - T0L = 0x00; - - T0CTL1 |= 0x80; -} - -void -vMBPortTimersDisable( ) -{ - T0CTL1 &= ~0x80; -} - -/* - * Create an ISR which is called whenever the timer has expired. This function - * must then call pxMBPortCBTimerExpired( ) to notify the protocol stack that - * the timer has expired. - */ -static void interrupt -prvvTIMERExpiredISR( void ) -{ - ( void )pxMBPortCBTimerExpired( ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/TODO.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/TODO.txt deleted file mode 100644 index 1c60fc8c6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/TODO.txt +++ /dev/null @@ -1,33 +0,0 @@ - -Modbus Gernal: - -Modbus RTU/ASCII: - - - Parity checking should be used for the characters when received. This - is not strictly necessary because we use CRC or LRC but it is recommended - in the standard - - Difficulty: easy - Priority: low - -Modbus TCP: - - - vMBTCPPortEnable( ) should be called by the protocol stack to enable - processing of input connections. This function must be called by - the protocol stack and therefore must be added to the TCP porting layer. - - Difficulty: medium - Priority: high - - - MCF5235TCP port uses an outdated version of the FreeRTOS/lwIP porting - layer. They should be merged with the STR71X porting layer. - -Modbus Functions: - - - If not initialized the Get Slave ID function must also return the - run indicator byte in the result and maybe a dummy slave id. - - Difficulty: easy - Priority: medium - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/dox.css b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/dox.css deleted file mode 100644 index decae9e39..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/dox.css +++ /dev/null @@ -1,309 +0,0 @@ -BODY,H1,H2,H3,H4,H5,H6,P,CENTER,TD,TH,UL,DL,DIV { - font-family: Geneva, Arial, Helvetica, sans-serif; -} -BODY,TD { - font-size: 90%; -} -H1 { - text-align: center; - font-size: 160%; -} -H2 { - font-size: 120%; -} -H3 { - font-size: 100%; -} -CAPTION { font-weight: bold } -DIV.qindex { - width: 100%; - background-color: #eeeeff; - border: 1px solid #b0b0b0; - text-align: center; - margin: 2px; - padding: 2px; - line-height: 140%; -} -DIV.nav { - width: 100%; - background-color: #eeeeff; - border: 1px solid #b0b0b0; - text-align: center; - margin: 2px; - padding: 2px; - line-height: 140%; -} -DIV.navtab { - background-color: #eeeeff; - border: 1px solid #b0b0b0; - text-align: center; - margin: 2px; - margin-right: 15px; - padding: 2px; -} -TD.navtab { - font-size: 70%; -} -A.qindex { - text-decoration: none; - font-weight: bold; - color: #1A419D; -} -A.qindex:visited { - text-decoration: none; - font-weight: bold; - color: #1A419D -} -A.qindex:hover { - text-decoration: none; - background-color: #ddddff; -} -A.qindexHL { - text-decoration: none; - font-weight: bold; - background-color: #6666cc; - color: #ffffff; - border: 1px double #9295C2; -} -A.qindexHL:hover { - text-decoration: none; - background-color: #6666cc; - color: #ffffff; -} -A.qindexHL:visited { text-decoration: none; background-color: #6666cc; color: #ffffff } -A.el { text-decoration: none; font-weight: bold } -A.elRef { font-weight: bold } -A.code:link { text-decoration: none; font-weight: normal; color: #0000FF} -A.code:visited { text-decoration: none; font-weight: normal; color: #0000FF} -A.codeRef:link { font-weight: normal; color: #0000FF} -A.codeRef:visited { font-weight: normal; color: #0000FF} -A:hover { text-decoration: none; background-color: #f2f2ff } -DL.el { margin-left: -1cm } -.fragment { - font-family: Fixed, monospace; - font-size: 95%; -} -PRE.fragment { - border: 1px solid #CCCCCC; - background-color: #f5f5f5; - margin-top: 4px; - margin-bottom: 4px; - margin-left: 2px; - margin-right: 8px; - padding-left: 6px; - padding-right: 6px; - padding-top: 4px; - padding-bottom: 4px; -} -DIV.ah { background-color: black; font-weight: bold; color: #ffffff; margin-bottom: 3px; margin-top: 3px } -TD.md { background-color: #F4F4FB; font-weight: bold; } -TD.mdPrefix { - background-color: #F4F4FB; - color: #606060; - font-size: 80%; -} -TD.mdname1 { background-color: #F4F4FB; font-weight: bold; color: #602020; } -TD.mdname { background-color: #F4F4FB; font-weight: bold; color: #602020; width: 600px; } -DIV.groupHeader { - margin-left: 16px; - margin-top: 12px; - margin-bottom: 6px; - font-weight: bold; -} -DIV.groupText { margin-left: 16px; font-style: italic; font-size: 90% } -BODY { - background: white; - color: black; - margin-right: 20px; - margin-left: 20px; -} -TD.indexkey { - background-color: #eeeeff; - font-weight: bold; - padding-right : 10px; - padding-top : 2px; - padding-left : 10px; - padding-bottom : 2px; - margin-left : 0px; - margin-right : 0px; - margin-top : 2px; - margin-bottom : 2px; - border: 1px solid #CCCCCC; -} -TD.indexvalue { - background-color: #eeeeff; - font-style: italic; - padding-right : 10px; - padding-top : 2px; - padding-left : 10px; - padding-bottom : 2px; - margin-left : 0px; - margin-right : 0px; - margin-top : 2px; - margin-bottom : 2px; - border: 1px solid #CCCCCC; -} -TR.memlist { - background-color: #f0f0f0; -} -P.formulaDsp { text-align: center; } -IMG.formulaDsp { } -IMG.formulaInl { vertical-align: middle; } -SPAN.keyword { color: #008000 } -SPAN.keywordtype { color: #604020 } -SPAN.keywordflow { color: #e08000 } -SPAN.comment { color: #800000 } -SPAN.preprocessor { color: #806020 } -SPAN.stringliteral { color: #002080 } -SPAN.charliteral { color: #008080 } -.mdTable { - border: 1px solid #868686; - background-color: #F4F4FB; -} -.mdRow { - padding: 8px 10px; -} -.mdescLeft { - padding: 0px 8px 4px 8px; - font-size: 80%; - font-style: italic; - background-color: #FAFAFA; - border-top: 1px none #E0E0E0; - border-right: 1px none #E0E0E0; - border-bottom: 1px none #E0E0E0; - border-left: 1px none #E0E0E0; - margin: 0px; -} -.mdescRight { - padding: 0px 8px 4px 8px; - font-size: 80%; - font-style: italic; - background-color: #FAFAFA; - border-top: 1px none #E0E0E0; - border-right: 1px none #E0E0E0; - border-bottom: 1px none #E0E0E0; - border-left: 1px none #E0E0E0; - margin: 0px; -} -.memItemLeft { - padding: 1px 0px 0px 8px; - margin: 4px; - border-top-width: 1px; - border-right-width: 1px; - border-bottom-width: 1px; - border-left-width: 1px; - border-top-color: #E0E0E0; - border-right-color: #E0E0E0; - border-bottom-color: #E0E0E0; - border-left-color: #E0E0E0; - border-top-style: solid; - border-right-style: none; - border-bottom-style: none; - border-left-style: none; - background-color: #FAFAFA; - font-size: 80%; -} -.memItemRight { - padding: 1px 8px 0px 8px; - margin: 4px; - border-top-width: 1px; - border-right-width: 1px; - border-bottom-width: 1px; - border-left-width: 1px; - border-top-color: #E0E0E0; - border-right-color: #E0E0E0; - border-bottom-color: #E0E0E0; - border-left-color: #E0E0E0; - border-top-style: solid; - border-right-style: none; - border-bottom-style: none; - border-left-style: none; - background-color: #FAFAFA; - font-size: 80%; -} -.memTemplItemLeft { - padding: 1px 0px 0px 8px; - margin: 4px; - border-top-width: 1px; - border-right-width: 1px; - border-bottom-width: 1px; - border-left-width: 1px; - border-top-color: #E0E0E0; - border-right-color: #E0E0E0; - border-bottom-color: #E0E0E0; - border-left-color: #E0E0E0; - border-top-style: none; - border-right-style: none; - border-bottom-style: none; - border-left-style: none; - background-color: #FAFAFA; - font-size: 80%; -} -.memTemplItemRight { - padding: 1px 8px 0px 8px; - margin: 4px; - border-top-width: 1px; - border-right-width: 1px; - border-bottom-width: 1px; - border-left-width: 1px; - border-top-color: #E0E0E0; - border-right-color: #E0E0E0; - border-bottom-color: #E0E0E0; - border-left-color: #E0E0E0; - border-top-style: none; - border-right-style: none; - border-bottom-style: none; - border-left-style: none; - background-color: #FAFAFA; - font-size: 80%; -} -.memTemplParams { - padding: 1px 0px 0px 8px; - margin: 4px; - border-top-width: 1px; - border-right-width: 1px; - border-bottom-width: 1px; - border-left-width: 1px; - border-top-color: #E0E0E0; - border-right-color: #E0E0E0; - border-bottom-color: #E0E0E0; - border-left-color: #E0E0E0; - border-top-style: solid; - border-right-style: none; - border-bottom-style: none; - border-left-style: none; - color: #606060; - background-color: #FAFAFA; - font-size: 80%; -} -.search { color: #003399; - font-weight: bold; -} -FORM.search { - margin-bottom: 0px; - margin-top: 0px; -} -INPUT.search { font-size: 75%; - color: #000080; - font-weight: normal; - background-color: #eeeeff; -} -TD.tiny { font-size: 75%; -} -a { - color: #252E78; -} -a:visited { - color: #3D2185; -} -.dirtab { padding: 4px; - border-collapse: collapse; - border: 1px solid #b0b0b0; -} -TH.dirtab { background: #eeeeff; - font-weight: bold; -} -HR { height: 1px; - border: none; - border-top: 1px solid black; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/dox_html_footer b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/dox_html_footer deleted file mode 100644 index 00cf8c5fe..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/dox_html_footer +++ /dev/null @@ -1,6 +0,0 @@ - -
-

Automatically generated by Doxygen $doxygenversion on $date.

- - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/dox_html_header b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/dox_html_header deleted file mode 100644 index 4a59efc53..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/dox_html_header +++ /dev/null @@ -1,9 +0,0 @@ - - - - - $title - - - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/doxygen.conf b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/doxygen.conf deleted file mode 100644 index 4e29c9422..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/doxygen.conf +++ /dev/null @@ -1,909 +0,0 @@ -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = FreeModbus - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = 1.6 - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Brazilian, Catalan, Chinese, Chinese-Traditional, Croatian, Czech, Danish, Dutch, -# Finnish, French, German, Greek, Hungarian, Italian, Japanese, Japanese-en -# (Japanese with English messages), Korean, Norwegian, Polish, Portuguese, -# Romanian, Russian, Serbian, Slovak, Slovene, Spanish, Swedish, and Ukrainian. - -OUTPUT_LANGUAGE = English - -# This tag can be used to specify the encoding used in the generated output. -# The encoding is not always determined by the language that is chosen, -# but also whether or not the output is meant for Windows or non-Windows users. -# In case there is a difference, setting the USE_WINDOWS_ENCODING tag to YES -# forces the Windows encoding (this is the default for the Windows binary), -# whereas setting the tag to NO uses a Unix-style encoding (the default for -# all platforms other than Windows). - -USE_WINDOWS_ENCODING = NO - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = NO - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = YES - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all inherited -# members of a class in the documentation of that class as if those members were -# ordinary class members. Constructors, destructors and assignment operators of -# the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. It is allowed to use relative paths in the argument list. - -STRIP_FROM_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like the Qt-style comments (thus requiring an -# explict @brief command for a brief description. - -JAVADOC_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the DETAILS_AT_TOP tag is set to YES then Doxygen -# will output the detailed description near the top, like JavaDoc. -# If set to NO, the detailed description appears after the member -# documentation. - -DETAILS_AT_TOP = YES - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# reimplements. - -INHERIT_DOCS = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 8 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES = - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources -# only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java sources -# only. Doxygen will then generate output that is more tailored for Java. -# For instance, namespaces will be presented as packages, qualified scopes -# will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = NO - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = NO - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# users are advised to set this option to NO. - -CASE_SENSE_NAMES = YES - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = NO - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = YES - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = NO - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. - -WARN_FORMAT = "$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = ../modbus/include \ - ../demo/BARE/port \ - . - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx *.hpp -# *.h++ *.idl *.odl *.cs *.php *.php3 *.inc - -FILE_PATTERNS = *.c \ - *.h \ - *.S \ - *.dox - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = YES - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or directories -# that are symbolic links (a Unix filesystem feature) are excluded from the input. - -EXCLUDE_SYMLINKS = YES - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. - -EXCLUDE_PATTERNS = *CVS* - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ../demo/AVR \ - ../demo/STR71X \ - ../demo/STR71XTCP \ - ../demo/MCF5235 \ - ../demo/MCF5235TCP \ - ../demo/WIN32 \ - ../demo/WIN32TCP \ - ../demo/LINUX \ - ../demo/LPC214X \ - ../demo/Z8ENCORE \ - ../demo/AT91SAM7X_ROWLEY \ - ../demo/MSP430 - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = *.c *.h *.cpp - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = . - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. - -INPUT_FILTER = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. - -SOURCE_BROWSER = NO - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = NO - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = NO - -# If the REFERENCED_BY_RELATION tag is set to YES (the default) -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = NO - -# If the REFERENCES_RELATION tag is set to YES (the default) -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = YES - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 4 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = dox_html_header - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = dox_html_footer - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet - -HTML_STYLESHEET = dox.css - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compressed HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output dir. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = YES - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 4 - -# If the GENERATE_TREEVIEW tag is set to YES, a side panel will be -# generated containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (for instance Mozilla 1.0+, -# Netscape 6.0+, Internet explorer 5.0+, or Konqueror). Windows users are -# probably better off using the HTML help feature. - -GENERATE_TREEVIEW = YES - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 200 - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -GENERATE_LATEX = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -GENERATE_RTF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -GENERATE_MAN = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_XML = NO - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -GENERATE_PERLMOD = NO - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = NO - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_PREDEFINED tags. - -EXPAND_ONLY_PREDEF = NO - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. - -PREDEFINED = DOXYGEN - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse the -# parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::addtions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base or -# super classes. Setting the tag to NO turns the diagrams off. Note that this -# option is superceded by the HAVE_DOT option below. This is only a fallback. It is -# recommended to install and use dot, since it yields more powerful graphs. - -CLASS_DIAGRAMS = YES - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = NO - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similiar to the OMG's Unified Modeling -# Language. - -UML_LOOK = NO - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT tags are set to YES then doxygen will -# generate a call dependency graph for every global function or class method. -# Note that enabling this option will significantly increase the time of a run. -# So in most cases it will be better to enable call graphs for selected -# functions only using the \callgraph command. - -CALL_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = png - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found on the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The MAX_DOT_GRAPH_WIDTH tag can be used to set the maximum allowed width -# (in pixels) of the graphs generated by dot. If a graph becomes larger than -# this value, doxygen will try to truncate the graph, so that it fits within -# the specified constraint. Beware that most browsers cannot cope with very -# large images. - -MAX_DOT_GRAPH_WIDTH = 1024 - -# The MAX_DOT_GRAPH_HEIGHT tag can be used to set the maximum allows height -# (in pixels) of the graphs generated by dot. If a graph becomes larger than -# this value, doxygen will try to truncate the graph, so that it fits within -# the specified constraint. Beware that most browsers cannot cope with very -# large images. - -MAX_DOT_GRAPH_HEIGHT = 1024 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes that -# lay further from the root node will be omitted. Note that setting this option to -# 1 or 2 may greatly reduce the computation time needed for large code bases. Also -# note that a graph may be further truncated if the graph's image dimensions are -# not sufficient to fit the graph (see MAX_DOT_GRAPH_WIDTH and MAX_DOT_GRAPH_HEIGHT). -# If 0 is used for the depth value (the default), the graph is not depth-constrained. - -MAX_DOT_GRAPH_DEPTH = 0 - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES - -#--------------------------------------------------------------------------- -# Configuration::addtions related to the search engine -#--------------------------------------------------------------------------- - -# The SEARCHENGINE tag specifies whether or not a search engine should be -# used. If set to NO the values of all tags below this one will be ignored. - -SEARCHENGINE = NO diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/main.dox b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/main.dox deleted file mode 100644 index 55ade927a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/main.dox +++ /dev/null @@ -1,103 +0,0 @@ - /* - * FreeRTOS Modbus Library: A Modbus serial implementation for FreeRTOS - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id: main.dox,v 1.16 2010/06/05 09:59:51 wolti Exp $ - */ - -/*! \mainpage FreeModbus - -\section intro Introduction - -The latest version of this document is available on http://freemodbus.berlios.de/api. - -FreeModbus is a Modbus ASCII/RTU and Modbus TCP implementation for embedded systems. It provides an implementation of the Modbus Application Protocol v1.1a and supports the RTU/ASCII transmission modes defined in the Modbus over serial line specification 1.0. Since version 0.7 FreeModbus also supports Modbus/TCP. Version 0.9 added the first Modbus/TCP port for embedded systems using the lwIP TCP/IP stack. - -\section into_port Ports - -\par Cortex M3 devices: - - Atmel AT91SAM3S. - -\par ARM devices: -- STR71X with FreeRTOS/GCC. See STR71X/simple2.c for an example. -- STR71TCP with FreeRTOS/lwIP/GCC. This port includes FreeRTOS, lwIP and a fully working PPP stack. The lwIP, PPP and FreeRTOS part is generic and therefore can be used for other ports ( or other projects ). -- LPC214X with Keil. See LPC214X/demo.c for an example. This port uses the Keil ARM Compiler 2.41. -- AT91SAM7X with FreeRTOS/Rowley. See AT91SAM7X_ROWLEY/demo.c for an example. - -\par AVR devices: -- ATMega8/16/32/128/168/169 with WinAVR. See AVR/demo.c for an example. - -\par Coldfire devices: -- MCF5235 with GCC. See MCF5235/demo.c for an example. -- MCF5235 with CodeWarrior and FreeRTOS port for ColdFire. See MCF5235CW/demo.c for an example. -- MCF5235/TCP with GCC. This port features FreeRTOS and the lwIP stack. The lwIP part is generic and therefore it should be used as a basis for other lwIP ports. - - -\par MSP430 devices -- MSP430F169 with Rowley Crossworks. See MSP430/demo.c for an example. -- MSP430F169 with GCC. See MSP430/demo.c for an example. - -\par Z8Encore devices -- Z8F6422 and Z8F1622 port. See Z8ENCORE/demo.c for an example. The port uses ZDS II - Z8 Encore! 4.10.1 as development environment. - -\par Win32: -- A Win32 Modbus RTU/ASCII Port. -- A Win32 Modbus/TCP Port. - -\par Linux: -- A Linux (uCLinux or other distributions) Modbus RTU/ASCII Port. -*/ - -/*! - \example STR71X/simple2.c - */ - -/*! - \example AT91SAM7X_ROWLEY/demo.c - */ - -/*! - \example STR71XTCP/demo.c - */ - -/*! - \example AVR/demo.c - */ - -/*! - \example MCF5235/demo.c - */ - -/*! - \example MCF5235TCP/demo.c - */ - -/*! - \example WIN32/demo.cpp - */ - -/*! - \example WIN32TCP/demo.cpp - */ - -/*! - \example LINUX/demo.c - */ - -/*! - \example MSP430/demo.c - */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/memory.ods b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/memory.ods deleted file mode 100644 index da87693cf..000000000 Binary files a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/memory.ods and /dev/null differ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/porting.dox b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/porting.dox deleted file mode 100644 index 0dba1cc96..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/porting.dox +++ /dev/null @@ -1,111 +0,0 @@ -/*! \page sec_porting_serial Porting for RTU/ASCII - -The first steps should always be to create a new directory for the port. The recommended layout is to create a top level directory, e.g. demo/PLATFORM which hold the application and project files. In addition a subdirectory port should be created for the port specific files. -\verbatim -demo/PLATFORM/Makefile -demo/PLATFORM/main.c -demo/PLATFORM/port/portserial.c -demo/PLATFORM/port/porttimer.c -demo/PLATFORM/port/portother.c -demo/PLATFORM/port/port.h -\endverbatim -You can use demo/BARE as a starting point. Simply copy the directory and rename it to a name of your choice. - -\section sec_porting_types Platform specifics (port.h) -You should first check the file port.h and check the if the examples are already suitable for your platform. You must at least define the macros for enabling ENTER_CRITICAL_SECTION and disabling EXIT_CRITICAL_SECTION interrupts. - -\section sec_porting_timers Implementation of the timer functions (porttimer.c) -The Modbus protocol stacks needs a timer to detect the end of the frame. The timers should have a resolution of half the time of a serial character. For example for 38400 baud the character time is approx. 280us assuming 11bits for a single character. The smallest timeout used by the protocol stack is 3.5 times the character timeout. -

You should start by implementing the function xMBPortTimersInit( USHORT usTim1Timerout50us ) and vMBPortTimersEnable( ). Test the function with the following sample code: -\code -xMBPortTimersInit( 20 ); -vMBPortTimersEnable( ); -for( ;; ); -\endcode -Place a breakpoint or toggle an LED in the interrupt handler which calls pxMBPortCBTimerExpired. The ISR should occur approx. 1ms after the call to vMBPortTimersEnable(). You should also check that vMBPortTimersDisable( ) works as expected. -

-\note If you use Modbus ASCII the timers are in the range of seconds because the timeouts are much larger there. Make sure you can handle a value of 20000 for usTim1Timerout50us which corresponds to an one second timeout. See mbconfig.h for the value of the timeout defined by MB_ASCII_TIMEOUT_SEC. - -\section sec_porting_serial Implementation of the serial functions (portserial.c) -The serial porting layer must be capable of initializing the UART, disabling and enabling the receiver and transmitter components as well as performing callbacks if a character has been received or can be transmitted. You should start by implementing xMBPortSerialInit( UCHAR ucPORT, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity ) and vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable ). -In addition you need to create two interrupt service routines for you communication devices. It is usually simpler to start with the receive interrupt. -

Create an interrupt handler for the receive interrupt, set a breakpoint there and check if xMBPortSerialGetByte( CHAR * pucByte ) correctly returns the character. This can be tested by the following code: -\code -/* Initialize COM device 0 with 38400 baud, 8 data bits and no parity. */ -if( xMBPortSerialInit( 0, 38400, 8, MB_PAR_NONE ) == FALSE ) -{ - fprintf(stderr, "error: com init failed"); -} -else -{ - /* Enable the receiver. */ - vMBPortSerialEnable( TRUE, FALSE ); - /* Now block. Any character received should cause an interrupt now. */ - for( ;; ); -} -\endcode -And your serial character received ISR should look like: -\code -static void prvvUARTTxReadyISR( void ) -{ - CHAR cByte; - ( void )xMBPortSerialGetByte( &cByte ); - /* Now cByte should contain the character received. */ -} -\endcode -

-

-Next you should check that the transmitter part is actually working as expected. Open a terminal program and simply call xMBPortSerialPutByte( 'a' ) in the transmit buffer empty ISR. If you use the sample code from below exactly 10 characters should be received. -\code -/* Initialize COM device 0 with 38400 baud, 8 data bits and no parity. */ -if( xMBPortSerialInit( 0, 38400, 8, MB_PAR_NONE ) == FALSE ) -{ - fprintf(stderr, "error: com init failed"); -} -else -{ - /* Enable the transmitter. */ - vMBPortSerialEnable( FALSE, TRUE ); - /* Now block. Any character received should cause an interrupt now. */ - for( ;; ); -} -\endcode -And you serial transmit buffer empty ISR should look like: -\code -static unsigned int uiCnt = 0; - -void prvvUARTTxReadyISR( void ) -{ - if( uiCnt++ < 10 ) - { - ( void )xMBPortSerialPutByte( 'a' ); - } - else - { - vMBPortSerialEnable( FALSE, FALSE ); - } -} -\endcode -

-

-If you are sure everything works correctly change the interrupt routines back to the examples shown in portserial.c -

- -\section sec_porting_event Implementing the event queue (portevent.c) -If you are not using an operating system the port is already finished and the demo application should work as expected. If you in the luck of having an operating system usage of the FreeModbus protocol stack differs in the following way: - - - Create another task at startup which calls eMBPoll( ) in a loop. This should look like: - \code -for( ;; ) -{ - ( void )eMBPoll( ); -} - \endcode - See the STR71x port for an FreeRTOS example. - - - Change the function xMBPortEventPost to post an event to a queue. Note that this function will be called from an ISR so check your RTOS documentation for that. - - - Change the xMBPortEventGet to retrieve an event from that queue. The function eMBPoll periodically calls it. The function should block until an event has been posted to the queue. - -In addition the serial and timer interrupt function must be modified. Whenever the protocol handler callback functions pxMBFrameCBByteReceived, pxMBFrameCBTransmitterEmpty and pxMBPortCBTimerExpired return TRUE a context switch should be made after exiting the ISR because an event has been posted to the queue. Forgetting to do this will result in slow performance of the protocol stack. -*/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/tips.dox b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/tips.dox deleted file mode 100644 index e3f1b43e8..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/doc/tips.dox +++ /dev/null @@ -1,33 +0,0 @@ -/*! \page sec_tips Tips - -This page provides some tips for using the FreeModbus protocol stack. - -\section sec_tips_memory Reducing memory requirements -The memory requirements of FreeModbus can be tuned in the following way. These are basic tricks and can easily be done: - - - Decided if you need RTU, ASCII and TCP at the same time. If not disable - them in the file mbconfig.h by settings the respective options - MB_RTU_ENABLED, MB_ASCII_ENABLED and MB_TCP_ENABLED to zero. - - If you don't need all Modbus functions disable them in the file mbconfig.h. - This will reduce code requirements. - - Set the variable MB_FUNC_HANDLERS_MAX in mbconfig.h to the number - of functions codes you want to support. - -If you have stronger limits you can also try the following options. Note that this options have an impact on the features of the protocol stack. - - - Use some compiler directive to put the mapping of function codes to - handler functions into the flash memory of you CPU. You can find this - table in the file mb.c at the top of the file. The static variable is - named xFuncHandlers. - - - Reduce the size of the RTU buffer. In this case longer frames will - result in an error (Your device will drop all these frames). This is - possible if you will never get read/write requests with that number - of registers or your total amount of registers is small anyway. - - - You could also remove some function pointers which make the protocol - stack configurable and replace them by the functions itself. For - example if you only want to use RTU remove the callback functions from - the porting layer and fill in the appropriate calls. This will save - the space for all function pointers. -*/ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/gpl.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/gpl.txt deleted file mode 100644 index 3912109b5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/gpl.txt +++ /dev/null @@ -1,340 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 2, June 1991 - - Copyright (C) 1989, 1991 Free Software Foundation, Inc. - 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The licenses for most software are designed to take away your -freedom to share and change it. By contrast, the GNU General Public -License is intended to guarantee your freedom to share and change free -software--to make sure the software is free for all its users. This -General Public License applies to most of the Free Software -Foundation's software and to any other program whose authors commit to -using it. (Some other Free Software Foundation software is covered by -the GNU Library General Public License instead.) You can apply it to -your programs, too. - - When we speak of free software, we are referring to freedom, not -price. Our General Public Licenses are designed to make sure that you -have the freedom to distribute copies of free software (and charge for -this service if you wish), that you receive source code or can get it -if you want it, that you can change the software or use pieces of it -in new free programs; and that you know you can do these things. - - To protect your rights, we need to make restrictions that forbid -anyone to deny you these rights or to ask you to surrender the rights. -These restrictions translate to certain responsibilities for you if you -distribute copies of the software, or if you modify it. - - For example, if you distribute copies of such a program, whether -gratis or for a fee, you must give the recipients all the rights that -you have. You must make sure that they, too, receive or can get the -source code. And you must show them these terms so they know their -rights. - - We protect your rights with two steps: (1) copyright the software, and -(2) offer you this license which gives you legal permission to copy, -distribute and/or modify the software. - - Also, for each author's protection and ours, we want to make certain -that everyone understands that there is no warranty for this free -software. If the software is modified by someone else and passed on, we -want its recipients to know that what they have is not the original, so -that any problems introduced by others will not reflect on the original -authors' reputations. - - Finally, any free program is threatened constantly by software -patents. We wish to avoid the danger that redistributors of a free -program will individually obtain patent licenses, in effect making the -program proprietary. To prevent this, we have made it clear that any -patent must be licensed for everyone's free use or not licensed at all. - - The precise terms and conditions for copying, distribution and -modification follow. - - GNU GENERAL PUBLIC LICENSE - TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION - - 0. This License applies to any program or other work which contains -a notice placed by the copyright holder saying it may be distributed -under the terms of this General Public License. The "Program", below, -refers to any such program or work, and a "work based on the Program" -means either the Program or any derivative work under copyright law: -that is to say, a work containing the Program or a portion of it, -either verbatim or with modifications and/or translated into another -language. (Hereinafter, translation is included without limitation in -the term "modification".) Each licensee is addressed as "you". - -Activities other than copying, distribution and modification are not -covered by this License; they are outside its scope. The act of -running the Program is not restricted, and the output from the Program -is covered only if its contents constitute a work based on the -Program (independent of having been made by running the Program). -Whether that is true depends on what the Program does. - - 1. You may copy and distribute verbatim copies of the Program's -source code as you receive it, in any medium, provided that you -conspicuously and appropriately publish on each copy an appropriate -copyright notice and disclaimer of warranty; keep intact all the -notices that refer to this License and to the absence of any warranty; -and give any other recipients of the Program a copy of this License -along with the Program. - -You may charge a fee for the physical act of transferring a copy, and -you may at your option offer warranty protection in exchange for a fee. - - 2. You may modify your copy or copies of the Program or any portion -of it, thus forming a work based on the Program, and copy and -distribute such modifications or work under the terms of Section 1 -above, provided that you also meet all of these conditions: - - a) You must cause the modified files to carry prominent notices - stating that you changed the files and the date of any change. - - b) You must cause any work that you distribute or publish, that in - whole or in part contains or is derived from the Program or any - part thereof, to be licensed as a whole at no charge to all third - parties under the terms of this License. - - c) If the modified program normally reads commands interactively - when run, you must cause it, when started running for such - interactive use in the most ordinary way, to print or display an - announcement including an appropriate copyright notice and a - notice that there is no warranty (or else, saying that you provide - a warranty) and that users may redistribute the program under - these conditions, and telling the user how to view a copy of this - License. (Exception: if the Program itself is interactive but - does not normally print such an announcement, your work based on - the Program is not required to print an announcement.) - -These requirements apply to the modified work as a whole. If -identifiable sections of that work are not derived from the Program, -and can be reasonably considered independent and separate works in -themselves, then this License, and its terms, do not apply to those -sections when you distribute them as separate works. But when you -distribute the same sections as part of a whole which is a work based -on the Program, the distribution of the whole must be on the terms of -this License, whose permissions for other licensees extend to the -entire whole, and thus to each and every part regardless of who wrote it. - -Thus, it is not the intent of this section to claim rights or contest -your rights to work written entirely by you; rather, the intent is to -exercise the right to control the distribution of derivative or -collective works based on the Program. - -In addition, mere aggregation of another work not based on the Program -with the Program (or with a work based on the Program) on a volume of -a storage or distribution medium does not bring the other work under -the scope of this License. - - 3. You may copy and distribute the Program (or a work based on it, -under Section 2) in object code or executable form under the terms of -Sections 1 and 2 above provided that you also do one of the following: - - a) Accompany it with the complete corresponding machine-readable - source code, which must be distributed under the terms of Sections - 1 and 2 above on a medium customarily used for software interchange; or, - - b) Accompany it with a written offer, valid for at least three - years, to give any third party, for a charge no more than your - cost of physically performing source distribution, a complete - machine-readable copy of the corresponding source code, to be - distributed under the terms of Sections 1 and 2 above on a medium - customarily used for software interchange; or, - - c) Accompany it with the information you received as to the offer - to distribute corresponding source code. (This alternative is - allowed only for noncommercial distribution and only if you - received the program in object code or executable form with such - an offer, in accord with Subsection b above.) - -The source code for a work means the preferred form of the work for -making modifications to it. For an executable work, complete source -code means all the source code for all modules it contains, plus any -associated interface definition files, plus the scripts used to -control compilation and installation of the executable. However, as a -special exception, the source code distributed need not include -anything that is normally distributed (in either source or binary -form) with the major components (compiler, kernel, and so on) of the -operating system on which the executable runs, unless that component -itself accompanies the executable. - -If distribution of executable or object code is made by offering -access to copy from a designated place, then offering equivalent -access to copy the source code from the same place counts as -distribution of the source code, even though third parties are not -compelled to copy the source along with the object code. - - 4. You may not copy, modify, sublicense, or distribute the Program -except as expressly provided under this License. Any attempt -otherwise to copy, modify, sublicense or distribute the Program is -void, and will automatically terminate your rights under this License. -However, parties who have received copies, or rights, from you under -this License will not have their licenses terminated so long as such -parties remain in full compliance. - - 5. You are not required to accept this License, since you have not -signed it. However, nothing else grants you permission to modify or -distribute the Program or its derivative works. These actions are -prohibited by law if you do not accept this License. Therefore, by -modifying or distributing the Program (or any work based on the -Program), you indicate your acceptance of this License to do so, and -all its terms and conditions for copying, distributing or modifying -the Program or works based on it. - - 6. Each time you redistribute the Program (or any work based on the -Program), the recipient automatically receives a license from the -original licensor to copy, distribute or modify the Program subject to -these terms and conditions. You may not impose any further -restrictions on the recipients' exercise of the rights granted herein. -You are not responsible for enforcing compliance by third parties to -this License. - - 7. If, as a consequence of a court judgment or allegation of patent -infringement or for any other reason (not limited to patent issues), -conditions are imposed on you (whether by court order, agreement or -otherwise) that contradict the conditions of this License, they do not -excuse you from the conditions of this License. If you cannot -distribute so as to satisfy simultaneously your obligations under this -License and any other pertinent obligations, then as a consequence you -may not distribute the Program at all. For example, if a patent -license would not permit royalty-free redistribution of the Program by -all those who receive copies directly or indirectly through you, then -the only way you could satisfy both it and this License would be to -refrain entirely from distribution of the Program. - -If any portion of this section is held invalid or unenforceable under -any particular circumstance, the balance of the section is intended to -apply and the section as a whole is intended to apply in other -circumstances. - -It is not the purpose of this section to induce you to infringe any -patents or other property right claims or to contest validity of any -such claims; this section has the sole purpose of protecting the -integrity of the free software distribution system, which is -implemented by public license practices. Many people have made -generous contributions to the wide range of software distributed -through that system in reliance on consistent application of that -system; it is up to the author/donor to decide if he or she is willing -to distribute software through any other system and a licensee cannot -impose that choice. - -This section is intended to make thoroughly clear what is believed to -be a consequence of the rest of this License. - - 8. If the distribution and/or use of the Program is restricted in -certain countries either by patents or by copyrighted interfaces, the -original copyright holder who places the Program under this License -may add an explicit geographical distribution limitation excluding -those countries, so that distribution is permitted only in or among -countries not thus excluded. In such case, this License incorporates -the limitation as if written in the body of this License. - - 9. The Free Software Foundation may publish revised and/or new versions -of the General Public License from time to time. Such new versions will -be similar in spirit to the present version, but may differ in detail to -address new problems or concerns. - -Each version is given a distinguishing version number. If the Program -specifies a version number of this License which applies to it and "any -later version", you have the option of following the terms and conditions -either of that version or of any later version published by the Free -Software Foundation. If the Program does not specify a version number of -this License, you may choose any version ever published by the Free Software -Foundation. - - 10. If you wish to incorporate parts of the Program into other free -programs whose distribution conditions are different, write to the author -to ask for permission. For software which is copyrighted by the Free -Software Foundation, write to the Free Software Foundation; we sometimes -make exceptions for this. Our decision will be guided by the two goals -of preserving the free status of all derivatives of our free software and -of promoting the sharing and reuse of software generally. - - NO WARRANTY - - 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY -FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN -OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES -PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED -OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS -TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE -PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, -REPAIR OR CORRECTION. - - 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING -WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR -REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, -INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING -OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED -TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY -YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER -PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE -POSSIBILITY OF SUCH DAMAGES. - - END OF TERMS AND CONDITIONS - - How to Apply These Terms to Your New Programs - - If you develop a new program, and you want it to be of the greatest -possible use to the public, the best way to achieve this is to make it -free software which everyone can redistribute and change under these terms. - - To do so, attach the following notices to the program. It is safest -to attach them to the start of each source file to most effectively -convey the exclusion of warranty; and each file should have at least -the "copyright" line and a pointer to where the full notice is found. - - - Copyright (C) - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - - -Also add information on how to contact you by electronic and paper mail. - -If the program is interactive, make it output a short notice like this -when it starts in an interactive mode: - - Gnomovision version 69, Copyright (C) year name of author - Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. - This is free software, and you are welcome to redistribute it - under certain conditions; type `show c' for details. - -The hypothetical commands `show w' and `show c' should show the appropriate -parts of the General Public License. Of course, the commands you use may -be called something other than `show w' and `show c'; they could even be -mouse-clicks or menu items--whatever suits your program. - -You should also get your employer (if you work as a programmer) or your -school, if any, to sign a "copyright disclaimer" for the program, if -necessary. Here is a sample; alter the names: - - Yoyodyne, Inc., hereby disclaims all copyright interest in the program - `Gnomovision' (which makes passes at compilers) written by James Hacker. - - , 1 April 1989 - Ty Coon, President of Vice - -This General Public License does not permit incorporating your program into -proprietary programs. If your program is a subroutine library, you may -consider it more useful to permit linking proprietary applications with the -library. If this is what you want to do, use the GNU Library General -Public License instead of this License. diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/lgpl.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/lgpl.txt deleted file mode 100644 index 8add30ad5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/lgpl.txt +++ /dev/null @@ -1,504 +0,0 @@ - GNU LESSER GENERAL PUBLIC LICENSE - Version 2.1, February 1999 - - Copyright (C) 1991, 1999 Free Software Foundation, Inc. - 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - -[This is the first released version of the Lesser GPL. It also counts - as the successor of the GNU Library Public License, version 2, hence - the version number 2.1.] - - Preamble - - The licenses for most software are designed to take away your -freedom to share and change it. By contrast, the GNU General Public -Licenses are intended to guarantee your freedom to share and change -free software--to make sure the software is free for all its users. - - This license, the Lesser General Public License, applies to some -specially designated software packages--typically libraries--of the -Free Software Foundation and other authors who decide to use it. You -can use it too, but we suggest you first think carefully about whether -this license or the ordinary General Public License is the better -strategy to use in any particular case, based on the explanations below. - - When we speak of free software, we are referring to freedom of use, -not price. Our General Public Licenses are designed to make sure that -you have the freedom to distribute copies of free software (and charge -for this service if you wish); that you receive source code or can get -it if you want it; that you can change the software and use pieces of -it in new free programs; and that you are informed that you can do -these things. - - To protect your rights, we need to make restrictions that forbid -distributors to deny you these rights or to ask you to surrender these -rights. These restrictions translate to certain responsibilities for -you if you distribute copies of the library or if you modify it. - - For example, if you distribute copies of the library, whether gratis -or for a fee, you must give the recipients all the rights that we gave -you. You must make sure that they, too, receive or can get the source -code. If you link other code with the library, you must provide -complete object files to the recipients, so that they can relink them -with the library after making changes to the library and recompiling -it. And you must show them these terms so they know their rights. - - We protect your rights with a two-step method: (1) we copyright the -library, and (2) we offer you this license, which gives you legal -permission to copy, distribute and/or modify the library. - - To protect each distributor, we want to make it very clear that -there is no warranty for the free library. Also, if the library is -modified by someone else and passed on, the recipients should know -that what they have is not the original version, so that the original -author's reputation will not be affected by problems that might be -introduced by others. - - Finally, software patents pose a constant threat to the existence of -any free program. We wish to make sure that a company cannot -effectively restrict the users of a free program by obtaining a -restrictive license from a patent holder. Therefore, we insist that -any patent license obtained for a version of the library must be -consistent with the full freedom of use specified in this license. - - Most GNU software, including some libraries, is covered by the -ordinary GNU General Public License. This license, the GNU Lesser -General Public License, applies to certain designated libraries, and -is quite different from the ordinary General Public License. We use -this license for certain libraries in order to permit linking those -libraries into non-free programs. - - When a program is linked with a library, whether statically or using -a shared library, the combination of the two is legally speaking a -combined work, a derivative of the original library. The ordinary -General Public License therefore permits such linking only if the -entire combination fits its criteria of freedom. The Lesser General -Public License permits more lax criteria for linking other code with -the library. - - We call this license the "Lesser" General Public License because it -does Less to protect the user's freedom than the ordinary General -Public License. It also provides other free software developers Less -of an advantage over competing non-free programs. These disadvantages -are the reason we use the ordinary General Public License for many -libraries. However, the Lesser license provides advantages in certain -special circumstances. - - For example, on rare occasions, there may be a special need to -encourage the widest possible use of a certain library, so that it becomes -a de-facto standard. To achieve this, non-free programs must be -allowed to use the library. A more frequent case is that a free -library does the same job as widely used non-free libraries. In this -case, there is little to gain by limiting the free library to free -software only, so we use the Lesser General Public License. - - In other cases, permission to use a particular library in non-free -programs enables a greater number of people to use a large body of -free software. For example, permission to use the GNU C Library in -non-free programs enables many more people to use the whole GNU -operating system, as well as its variant, the GNU/Linux operating -system. - - Although the Lesser General Public License is Less protective of the -users' freedom, it does ensure that the user of a program that is -linked with the Library has the freedom and the wherewithal to run -that program using a modified version of the Library. - - The precise terms and conditions for copying, distribution and -modification follow. Pay close attention to the difference between a -"work based on the library" and a "work that uses the library". The -former contains code derived from the library, whereas the latter must -be combined with the library in order to run. - - GNU LESSER GENERAL PUBLIC LICENSE - TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION - - 0. This License Agreement applies to any software library or other -program which contains a notice placed by the copyright holder or -other authorized party saying it may be distributed under the terms of -this Lesser General Public License (also called "this License"). -Each licensee is addressed as "you". - - A "library" means a collection of software functions and/or data -prepared so as to be conveniently linked with application programs -(which use some of those functions and data) to form executables. - - The "Library", below, refers to any such software library or work -which has been distributed under these terms. A "work based on the -Library" means either the Library or any derivative work under -copyright law: that is to say, a work containing the Library or a -portion of it, either verbatim or with modifications and/or translated -straightforwardly into another language. (Hereinafter, translation is -included without limitation in the term "modification".) - - "Source code" for a work means the preferred form of the work for -making modifications to it. For a library, complete source code means -all the source code for all modules it contains, plus any associated -interface definition files, plus the scripts used to control compilation -and installation of the library. - - Activities other than copying, distribution and modification are not -covered by this License; they are outside its scope. The act of -running a program using the Library is not restricted, and output from -such a program is covered only if its contents constitute a work based -on the Library (independent of the use of the Library in a tool for -writing it). Whether that is true depends on what the Library does -and what the program that uses the Library does. - - 1. You may copy and distribute verbatim copies of the Library's -complete source code as you receive it, in any medium, provided that -you conspicuously and appropriately publish on each copy an -appropriate copyright notice and disclaimer of warranty; keep intact -all the notices that refer to this License and to the absence of any -warranty; and distribute a copy of this License along with the -Library. - - You may charge a fee for the physical act of transferring a copy, -and you may at your option offer warranty protection in exchange for a -fee. - - 2. You may modify your copy or copies of the Library or any portion -of it, thus forming a work based on the Library, and copy and -distribute such modifications or work under the terms of Section 1 -above, provided that you also meet all of these conditions: - - a) The modified work must itself be a software library. - - b) You must cause the files modified to carry prominent notices - stating that you changed the files and the date of any change. - - c) You must cause the whole of the work to be licensed at no - charge to all third parties under the terms of this License. - - d) If a facility in the modified Library refers to a function or a - table of data to be supplied by an application program that uses - the facility, other than as an argument passed when the facility - is invoked, then you must make a good faith effort to ensure that, - in the event an application does not supply such function or - table, the facility still operates, and performs whatever part of - its purpose remains meaningful. - - (For example, a function in a library to compute square roots has - a purpose that is entirely well-defined independent of the - application. Therefore, Subsection 2d requires that any - application-supplied function or table used by this function must - be optional: if the application does not supply it, the square - root function must still compute square roots.) - -These requirements apply to the modified work as a whole. If -identifiable sections of that work are not derived from the Library, -and can be reasonably considered independent and separate works in -themselves, then this License, and its terms, do not apply to those -sections when you distribute them as separate works. But when you -distribute the same sections as part of a whole which is a work based -on the Library, the distribution of the whole must be on the terms of -this License, whose permissions for other licensees extend to the -entire whole, and thus to each and every part regardless of who wrote -it. - -Thus, it is not the intent of this section to claim rights or contest -your rights to work written entirely by you; rather, the intent is to -exercise the right to control the distribution of derivative or -collective works based on the Library. - -In addition, mere aggregation of another work not based on the Library -with the Library (or with a work based on the Library) on a volume of -a storage or distribution medium does not bring the other work under -the scope of this License. - - 3. You may opt to apply the terms of the ordinary GNU General Public -License instead of this License to a given copy of the Library. To do -this, you must alter all the notices that refer to this License, so -that they refer to the ordinary GNU General Public License, version 2, -instead of to this License. (If a newer version than version 2 of the -ordinary GNU General Public License has appeared, then you can specify -that version instead if you wish.) Do not make any other change in -these notices. - - Once this change is made in a given copy, it is irreversible for -that copy, so the ordinary GNU General Public License applies to all -subsequent copies and derivative works made from that copy. - - This option is useful when you wish to copy part of the code of -the Library into a program that is not a library. - - 4. You may copy and distribute the Library (or a portion or -derivative of it, under Section 2) in object code or executable form -under the terms of Sections 1 and 2 above provided that you accompany -it with the complete corresponding machine-readable source code, which -must be distributed under the terms of Sections 1 and 2 above on a -medium customarily used for software interchange. - - If distribution of object code is made by offering access to copy -from a designated place, then offering equivalent access to copy the -source code from the same place satisfies the requirement to -distribute the source code, even though third parties are not -compelled to copy the source along with the object code. - - 5. A program that contains no derivative of any portion of the -Library, but is designed to work with the Library by being compiled or -linked with it, is called a "work that uses the Library". Such a -work, in isolation, is not a derivative work of the Library, and -therefore falls outside the scope of this License. - - However, linking a "work that uses the Library" with the Library -creates an executable that is a derivative of the Library (because it -contains portions of the Library), rather than a "work that uses the -library". The executable is therefore covered by this License. -Section 6 states terms for distribution of such executables. - - When a "work that uses the Library" uses material from a header file -that is part of the Library, the object code for the work may be a -derivative work of the Library even though the source code is not. -Whether this is true is especially significant if the work can be -linked without the Library, or if the work is itself a library. The -threshold for this to be true is not precisely defined by law. - - If such an object file uses only numerical parameters, data -structure layouts and accessors, and small macros and small inline -functions (ten lines or less in length), then the use of the object -file is unrestricted, regardless of whether it is legally a derivative -work. (Executables containing this object code plus portions of the -Library will still fall under Section 6.) - - Otherwise, if the work is a derivative of the Library, you may -distribute the object code for the work under the terms of Section 6. -Any executables containing that work also fall under Section 6, -whether or not they are linked directly with the Library itself. - - 6. As an exception to the Sections above, you may also combine or -link a "work that uses the Library" with the Library to produce a -work containing portions of the Library, and distribute that work -under terms of your choice, provided that the terms permit -modification of the work for the customer's own use and reverse -engineering for debugging such modifications. - - You must give prominent notice with each copy of the work that the -Library is used in it and that the Library and its use are covered by -this License. You must supply a copy of this License. If the work -during execution displays copyright notices, you must include the -copyright notice for the Library among them, as well as a reference -directing the user to the copy of this License. Also, you must do one -of these things: - - a) Accompany the work with the complete corresponding - machine-readable source code for the Library including whatever - changes were used in the work (which must be distributed under - Sections 1 and 2 above); and, if the work is an executable linked - with the Library, with the complete machine-readable "work that - uses the Library", as object code and/or source code, so that the - user can modify the Library and then relink to produce a modified - executable containing the modified Library. (It is understood - that the user who changes the contents of definitions files in the - Library will not necessarily be able to recompile the application - to use the modified definitions.) - - b) Use a suitable shared library mechanism for linking with the - Library. A suitable mechanism is one that (1) uses at run time a - copy of the library already present on the user's computer system, - rather than copying library functions into the executable, and (2) - will operate properly with a modified version of the library, if - the user installs one, as long as the modified version is - interface-compatible with the version that the work was made with. - - c) Accompany the work with a written offer, valid for at - least three years, to give the same user the materials - specified in Subsection 6a, above, for a charge no more - than the cost of performing this distribution. - - d) If distribution of the work is made by offering access to copy - from a designated place, offer equivalent access to copy the above - specified materials from the same place. - - e) Verify that the user has already received a copy of these - materials or that you have already sent this user a copy. - - For an executable, the required form of the "work that uses the -Library" must include any data and utility programs needed for -reproducing the executable from it. However, as a special exception, -the materials to be distributed need not include anything that is -normally distributed (in either source or binary form) with the major -components (compiler, kernel, and so on) of the operating system on -which the executable runs, unless that component itself accompanies -the executable. - - It may happen that this requirement contradicts the license -restrictions of other proprietary libraries that do not normally -accompany the operating system. Such a contradiction means you cannot -use both them and the Library together in an executable that you -distribute. - - 7. You may place library facilities that are a work based on the -Library side-by-side in a single library together with other library -facilities not covered by this License, and distribute such a combined -library, provided that the separate distribution of the work based on -the Library and of the other library facilities is otherwise -permitted, and provided that you do these two things: - - a) Accompany the combined library with a copy of the same work - based on the Library, uncombined with any other library - facilities. This must be distributed under the terms of the - Sections above. - - b) Give prominent notice with the combined library of the fact - that part of it is a work based on the Library, and explaining - where to find the accompanying uncombined form of the same work. - - 8. You may not copy, modify, sublicense, link with, or distribute -the Library except as expressly provided under this License. Any -attempt otherwise to copy, modify, sublicense, link with, or -distribute the Library is void, and will automatically terminate your -rights under this License. However, parties who have received copies, -or rights, from you under this License will not have their licenses -terminated so long as such parties remain in full compliance. - - 9. You are not required to accept this License, since you have not -signed it. However, nothing else grants you permission to modify or -distribute the Library or its derivative works. These actions are -prohibited by law if you do not accept this License. Therefore, by -modifying or distributing the Library (or any work based on the -Library), you indicate your acceptance of this License to do so, and -all its terms and conditions for copying, distributing or modifying -the Library or works based on it. - - 10. Each time you redistribute the Library (or any work based on the -Library), the recipient automatically receives a license from the -original licensor to copy, distribute, link with or modify the Library -subject to these terms and conditions. You may not impose any further -restrictions on the recipients' exercise of the rights granted herein. -You are not responsible for enforcing compliance by third parties with -this License. - - 11. If, as a consequence of a court judgment or allegation of patent -infringement or for any other reason (not limited to patent issues), -conditions are imposed on you (whether by court order, agreement or -otherwise) that contradict the conditions of this License, they do not -excuse you from the conditions of this License. If you cannot -distribute so as to satisfy simultaneously your obligations under this -License and any other pertinent obligations, then as a consequence you -may not distribute the Library at all. For example, if a patent -license would not permit royalty-free redistribution of the Library by -all those who receive copies directly or indirectly through you, then -the only way you could satisfy both it and this License would be to -refrain entirely from distribution of the Library. - -If any portion of this section is held invalid or unenforceable under any -particular circumstance, the balance of the section is intended to apply, -and the section as a whole is intended to apply in other circumstances. - -It is not the purpose of this section to induce you to infringe any -patents or other property right claims or to contest validity of any -such claims; this section has the sole purpose of protecting the -integrity of the free software distribution system which is -implemented by public license practices. Many people have made -generous contributions to the wide range of software distributed -through that system in reliance on consistent application of that -system; it is up to the author/donor to decide if he or she is willing -to distribute software through any other system and a licensee cannot -impose that choice. - -This section is intended to make thoroughly clear what is believed to -be a consequence of the rest of this License. - - 12. If the distribution and/or use of the Library is restricted in -certain countries either by patents or by copyrighted interfaces, the -original copyright holder who places the Library under this License may add -an explicit geographical distribution limitation excluding those countries, -so that distribution is permitted only in or among countries not thus -excluded. In such case, this License incorporates the limitation as if -written in the body of this License. - - 13. The Free Software Foundation may publish revised and/or new -versions of the Lesser General Public License from time to time. -Such new versions will be similar in spirit to the present version, -but may differ in detail to address new problems or concerns. - -Each version is given a distinguishing version number. If the Library -specifies a version number of this License which applies to it and -"any later version", you have the option of following the terms and -conditions either of that version or of any later version published by -the Free Software Foundation. If the Library does not specify a -license version number, you may choose any version ever published by -the Free Software Foundation. - - 14. If you wish to incorporate parts of the Library into other free -programs whose distribution conditions are incompatible with these, -write to the author to ask for permission. For software which is -copyrighted by the Free Software Foundation, write to the Free -Software Foundation; we sometimes make exceptions for this. Our -decision will be guided by the two goals of preserving the free status -of all derivatives of our free software and of promoting the sharing -and reuse of software generally. - - NO WARRANTY - - 15. BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO -WARRANTY FOR THE LIBRARY, TO THE EXTENT PERMITTED BY APPLICABLE LAW. -EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR -OTHER PARTIES PROVIDE THE LIBRARY "AS IS" WITHOUT WARRANTY OF ANY -KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE -LIBRARY IS WITH YOU. SHOULD THE LIBRARY PROVE DEFECTIVE, YOU ASSUME -THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. - - 16. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN -WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY -AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU -FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR -CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE -LIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING -RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A -FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF -SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -DAMAGES. - - END OF TERMS AND CONDITIONS - - How to Apply These Terms to Your New Libraries - - If you develop a new library, and you want it to be of the greatest -possible use to the public, we recommend making it free software that -everyone can redistribute and change. You can do so by permitting -redistribution under these terms (or, alternatively, under the terms of the -ordinary General Public License). - - To apply these terms, attach the following notices to the library. It is -safest to attach them to the start of each source file to most effectively -convey the exclusion of warranty; and each file should have at least the -"copyright" line and a pointer to where the full notice is found. - - - Copyright (C) - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -Also add information on how to contact you by electronic and paper mail. - -You should also get your employer (if you work as a programmer) or your -school, if any, to sign a "copyright disclaimer" for the library, if -necessary. Here is a sample; alter the names: - - Yoyodyne, Inc., hereby disclaims all copyright interest in the - library `Frob' (a library for tweaking knobs) written by James Random Hacker. - - , 1 April 1990 - Ty Coon, President of Vice - -That's all there is to it! - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/ascii/mbascii.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/ascii/mbascii.c deleted file mode 100644 index 879c36059..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/ascii/mbascii.c +++ /dev/null @@ -1,485 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "stdlib.h" -#include "string.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "mod_port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbconfig.h" -#include "mbascii.h" -#include "mbframe.h" - -#include "mbcrc.h" -#include "mbport.h" - -#if MB_ASCII_ENABLED > 0 - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_ASCII_DEFAULT_CR '\r' /*!< Default CR character for Modbus ASCII. */ -#define MB_ASCII_DEFAULT_LF '\n' /*!< Default LF character for Modbus ASCII. */ -#define MB_SER_PDU_SIZE_MIN 3 /*!< Minimum size of a Modbus ASCII frame. */ -#define MB_SER_PDU_SIZE_MAX 256 /*!< Maximum size of a Modbus ASCII frame. */ -#define MB_SER_PDU_SIZE_LRC 1 /*!< Size of LRC field in PDU. */ -#define MB_SER_PDU_ADDR_OFF 0 /*!< Offset of slave address in Ser-PDU. */ -#define MB_SER_PDU_PDU_OFF 1 /*!< Offset of Modbus-PDU in Ser-PDU. */ - -/* ----------------------- Type definitions ---------------------------------*/ -typedef enum -{ - STATE_RX_IDLE, /*!< Receiver is in idle state. */ - STATE_RX_RCV, /*!< Frame is beeing received. */ - STATE_RX_WAIT_EOF /*!< Wait for End of Frame. */ -} eMBRcvState; - -typedef enum -{ - STATE_TX_IDLE, /*!< Transmitter is in idle state. */ - STATE_TX_START, /*!< Starting transmission (':' sent). */ - STATE_TX_DATA, /*!< Sending of data (Address, Data, LRC). */ - STATE_TX_END, /*!< End of transmission. */ - STATE_TX_NOTIFY /*!< Notify sender that the frame has been sent. */ -} eMBSndState; - -typedef enum -{ - BYTE_HIGH_NIBBLE, /*!< Character for high nibble of byte. */ - BYTE_LOW_NIBBLE /*!< Character for low nibble of byte. */ -} eMBBytePos; - -/* ----------------------- Static functions ---------------------------------*/ -static UCHAR prvucMBCHAR2BIN( UCHAR ucCharacter ); - -static UCHAR prvucMBBIN2CHAR( UCHAR ucByte ); - -static UCHAR prvucMBLRC( UCHAR * pucFrame, USHORT usLen ); - -/* ----------------------- Static variables ---------------------------------*/ -static volatile eMBSndState eSndState; -static volatile eMBRcvState eRcvState; - -/* We reuse the Modbus RTU buffer because only one buffer is needed and the - * RTU buffer is bigger. */ -extern volatile UCHAR ucRTUBuf[]; -static volatile UCHAR *ucASCIIBuf = ucRTUBuf; - -static volatile USHORT usRcvBufferPos; -static volatile eMBBytePos eBytePos; - -static volatile UCHAR *pucSndBufferCur; -static volatile USHORT usSndBufferCount; - -static volatile UCHAR ucLRC; -static volatile UCHAR ucMBLFCharacter; - -/* ----------------------- Start implementation -----------------------------*/ -eMBErrorCode -eMBASCIIInit( UCHAR ucSlaveAddress, UCHAR ucPort, ULONG ulBaudRate, eMBParity eParity ) -{ - eMBErrorCode eStatus = MB_ENOERR; - ( void )ucSlaveAddress; - - ENTER_CRITICAL_SECTION( ); - ucMBLFCharacter = MB_ASCII_DEFAULT_LF; - - if( xMBPortSerialInit( ucPort, ulBaudRate, 7, eParity ) != TRUE ) - { - eStatus = MB_EPORTERR; - } - else if( xMBPortTimersInit( MB_ASCII_TIMEOUT_SEC * 20000UL ) != TRUE ) - { - eStatus = MB_EPORTERR; - } - - EXIT_CRITICAL_SECTION( ); - - return eStatus; -} - -void -eMBASCIIStart( void ) -{ - ENTER_CRITICAL_SECTION( ); - vMBPortSerialEnable( TRUE, FALSE ); - eRcvState = STATE_RX_IDLE; - EXIT_CRITICAL_SECTION( ); - - /* No special startup required for ASCII. */ - ( void )xMBPortEventPost( EV_READY ); -} - -void -eMBASCIIStop( void ) -{ - ENTER_CRITICAL_SECTION( ); - vMBPortSerialEnable( FALSE, FALSE ); - vMBPortTimersDisable( ); - EXIT_CRITICAL_SECTION( ); -} - -eMBErrorCode -eMBASCIIReceive( UCHAR * pucRcvAddress, UCHAR ** pucFrame, USHORT * pusLength ) -{ - eMBErrorCode eStatus = MB_ENOERR; - - ENTER_CRITICAL_SECTION( ); - assert( usRcvBufferPos < MB_SER_PDU_SIZE_MAX ); - - /* Length and CRC check */ - if( ( usRcvBufferPos >= MB_SER_PDU_SIZE_MIN ) - && ( prvucMBLRC( ( UCHAR * ) ucASCIIBuf, usRcvBufferPos ) == 0 ) ) - { - /* Save the address field. All frames are passed to the upper layed - * and the decision if a frame is used is done there. - */ - *pucRcvAddress = ucASCIIBuf[MB_SER_PDU_ADDR_OFF]; - - /* Total length of Modbus-PDU is Modbus-Serial-Line-PDU minus - * size of address field and CRC checksum. - */ - *pusLength = ( USHORT )( usRcvBufferPos - MB_SER_PDU_PDU_OFF - MB_SER_PDU_SIZE_LRC ); - - /* Return the start of the Modbus PDU to the caller. */ - *pucFrame = ( UCHAR * ) & ucASCIIBuf[MB_SER_PDU_PDU_OFF]; - } - else - { - eStatus = MB_EIO; - } - EXIT_CRITICAL_SECTION( ); - return eStatus; -} - -eMBErrorCode -eMBASCIISend( UCHAR ucSlaveAddress, const UCHAR * pucFrame, USHORT usLength ) -{ - eMBErrorCode eStatus = MB_ENOERR; - UCHAR usLRC; - - ENTER_CRITICAL_SECTION( ); - /* Check if the receiver is still in idle state. If not we where too - * slow with processing the received frame and the master sent another - * frame on the network. We have to abort sending the frame. - */ - if( eRcvState == STATE_RX_IDLE ) - { - /* First byte before the Modbus-PDU is the slave address. */ - pucSndBufferCur = ( UCHAR * ) pucFrame - 1; - usSndBufferCount = 1; - - /* Now copy the Modbus-PDU into the Modbus-Serial-Line-PDU. */ - pucSndBufferCur[MB_SER_PDU_ADDR_OFF] = ucSlaveAddress; - usSndBufferCount += usLength; - - /* Calculate LRC checksum for Modbus-Serial-Line-PDU. */ - usLRC = prvucMBLRC( ( UCHAR * ) pucSndBufferCur, usSndBufferCount ); - ucASCIIBuf[usSndBufferCount++] = usLRC; - - /* Activate the transmitter. */ - eSndState = STATE_TX_START; - vMBPortSerialEnable( FALSE, TRUE ); - } - else - { - eStatus = MB_EIO; - } - EXIT_CRITICAL_SECTION( ); - return eStatus; -} - -BOOL -xMBASCIIReceiveFSM( void ) -{ - BOOL xNeedPoll = FALSE; - UCHAR ucByte; - UCHAR ucResult; - - assert( eSndState == STATE_TX_IDLE ); - - ( void )xMBPortSerialGetByte( ( CHAR * ) & ucByte ); - switch ( eRcvState ) - { - /* A new character is received. If the character is a ':' the input - * buffer is cleared. A CR-character signals the end of the data - * block. Other characters are part of the data block and their - * ASCII value is converted back to a binary representation. - */ - case STATE_RX_RCV: - /* Enable timer for character timeout. */ - vMBPortTimersEnable( ); - if( ucByte == ':' ) - { - /* Empty receive buffer. */ - eBytePos = BYTE_HIGH_NIBBLE; - usRcvBufferPos = 0; - } - else if( ucByte == MB_ASCII_DEFAULT_CR ) - { - eRcvState = STATE_RX_WAIT_EOF; - } - else - { - ucResult = prvucMBCHAR2BIN( ucByte ); - switch ( eBytePos ) - { - /* High nibble of the byte comes first. We check for - * a buffer overflow here. */ - case BYTE_HIGH_NIBBLE: - if( usRcvBufferPos < MB_SER_PDU_SIZE_MAX ) - { - ucASCIIBuf[usRcvBufferPos] = ( UCHAR )( ucResult << 4 ); - eBytePos = BYTE_LOW_NIBBLE; - break; - } - else - { - /* not handled in Modbus specification but seems - * a resonable implementation. */ - eRcvState = STATE_RX_IDLE; - /* Disable previously activated timer because of error state. */ - vMBPortTimersDisable( ); - } - break; - - case BYTE_LOW_NIBBLE: - ucASCIIBuf[usRcvBufferPos] |= ucResult; - usRcvBufferPos++; - eBytePos = BYTE_HIGH_NIBBLE; - break; - } - } - break; - - case STATE_RX_WAIT_EOF: - if( ucByte == ucMBLFCharacter ) - { - /* Disable character timeout timer because all characters are - * received. */ - vMBPortTimersDisable( ); - /* Receiver is again in idle state. */ - eRcvState = STATE_RX_IDLE; - - /* Notify the caller of eMBASCIIReceive that a new frame - * was received. */ - xNeedPoll = xMBPortEventPost( EV_FRAME_RECEIVED ); - } - else if( ucByte == ':' ) - { - /* Empty receive buffer and back to receive state. */ - eBytePos = BYTE_HIGH_NIBBLE; - usRcvBufferPos = 0; - eRcvState = STATE_RX_RCV; - - /* Enable timer for character timeout. */ - vMBPortTimersEnable( ); - } - else - { - /* Frame is not okay. Delete entire frame. */ - eRcvState = STATE_RX_IDLE; - } - break; - - case STATE_RX_IDLE: - if( ucByte == ':' ) - { - /* Enable timer for character timeout. */ - vMBPortTimersEnable( ); - /* Reset the input buffers to store the frame. */ - usRcvBufferPos = 0;; - eBytePos = BYTE_HIGH_NIBBLE; - eRcvState = STATE_RX_RCV; - } - break; - } - - return xNeedPoll; -} - -BOOL -xMBASCIITransmitFSM( void ) -{ - BOOL xNeedPoll = FALSE; - UCHAR ucByte; - - assert( eRcvState == STATE_RX_IDLE ); - switch ( eSndState ) - { - /* Start of transmission. The start of a frame is defined by sending - * the character ':'. */ - case STATE_TX_START: - ucByte = ':'; - xMBPortSerialPutByte( ( CHAR )ucByte ); - eSndState = STATE_TX_DATA; - eBytePos = BYTE_HIGH_NIBBLE; - break; - - /* Send the data block. Each data byte is encoded as a character hex - * stream with the high nibble sent first and the low nibble sent - * last. If all data bytes are exhausted we send a '\r' character - * to end the transmission. */ - case STATE_TX_DATA: - if( usSndBufferCount > 0 ) - { - switch ( eBytePos ) - { - case BYTE_HIGH_NIBBLE: - ucByte = prvucMBBIN2CHAR( ( UCHAR )( *pucSndBufferCur >> 4 ) ); - xMBPortSerialPutByte( ( CHAR ) ucByte ); - eBytePos = BYTE_LOW_NIBBLE; - break; - - case BYTE_LOW_NIBBLE: - ucByte = prvucMBBIN2CHAR( ( UCHAR )( *pucSndBufferCur & 0x0F ) ); - xMBPortSerialPutByte( ( CHAR )ucByte ); - pucSndBufferCur++; - eBytePos = BYTE_HIGH_NIBBLE; - usSndBufferCount--; - break; - } - } - else - { - xMBPortSerialPutByte( MB_ASCII_DEFAULT_CR ); - eSndState = STATE_TX_END; - } - break; - - /* Finish the frame by sending a LF character. */ - case STATE_TX_END: - xMBPortSerialPutByte( ( CHAR )ucMBLFCharacter ); - /* We need another state to make sure that the CR character has - * been sent. */ - eSndState = STATE_TX_NOTIFY; - break; - - /* Notify the task which called eMBASCIISend that the frame has - * been sent. */ - case STATE_TX_NOTIFY: - eSndState = STATE_TX_IDLE; - xNeedPoll = xMBPortEventPost( EV_FRAME_SENT ); - - /* Disable transmitter. This prevents another transmit buffer - * empty interrupt. */ - vMBPortSerialEnable( TRUE, FALSE ); - eSndState = STATE_TX_IDLE; - break; - - /* We should not get a transmitter event if the transmitter is in - * idle state. */ - case STATE_TX_IDLE: - /* enable receiver/disable transmitter. */ - vMBPortSerialEnable( TRUE, FALSE ); - break; - } - - return xNeedPoll; -} - -BOOL -xMBASCIITimerT1SExpired( void ) -{ - switch ( eRcvState ) - { - /* If we have a timeout we go back to the idle state and wait for - * the next frame. - */ - case STATE_RX_RCV: - case STATE_RX_WAIT_EOF: - eRcvState = STATE_RX_IDLE; - break; - - default: - assert( ( eRcvState == STATE_RX_RCV ) || ( eRcvState == STATE_RX_WAIT_EOF ) ); - break; - } - vMBPortTimersDisable( ); - - /* no context switch required. */ - return FALSE; -} - - -static UCHAR -prvucMBCHAR2BIN( UCHAR ucCharacter ) -{ - if( ( ucCharacter >= '0' ) && ( ucCharacter <= '9' ) ) - { - return ( UCHAR )( ucCharacter - '0' ); - } - else if( ( ucCharacter >= 'A' ) && ( ucCharacter <= 'F' ) ) - { - return ( UCHAR )( ucCharacter - 'A' + 0x0A ); - } - else - { - return 0xFF; - } -} - -static UCHAR -prvucMBBIN2CHAR( UCHAR ucByte ) -{ - if( ucByte <= 0x09 ) - { - return ( UCHAR )( '0' + ucByte ); - } - else if( ( ucByte >= 0x0A ) && ( ucByte <= 0x0F ) ) - { - return ( UCHAR )( ucByte - 0x0A + 'A' ); - } - else - { - /* Programming error. */ - assert( 0 ); - } - return '0'; -} - - -static UCHAR -prvucMBLRC( UCHAR * pucFrame, USHORT usLen ) -{ - UCHAR ucLRC = 0; /* LRC char initialized */ - - while( usLen-- ) - { - ucLRC += *pucFrame++; /* Add buffer byte without carry */ - } - - /* Return twos complement */ - ucLRC = ( UCHAR ) ( -( ( CHAR ) ucLRC ) ); - return ucLRC; -} - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/ascii/mbascii.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/ascii/mbascii.h deleted file mode 100644 index 20975e29b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/ascii/mbascii.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _MB_ASCII_H -#define _MB_ASCII_H - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif - -#if MB_ASCII_ENABLED > 0 -eMBErrorCode eMBASCIIInit( UCHAR slaveAddress, UCHAR ucPort, - ULONG ulBaudRate, eMBParity eParity ); -void eMBASCIIStart( void ); -void eMBASCIIStop( void ); - -eMBErrorCode eMBASCIIReceive( UCHAR * pucRcvAddress, UCHAR ** pucFrame, - USHORT * pusLength ); -eMBErrorCode eMBASCIISend( UCHAR slaveAddress, const UCHAR * pucFrame, - USHORT usLength ); -BOOL xMBASCIIReceiveFSM( void ); -BOOL xMBASCIITransmitFSM( void ); -BOOL xMBASCIITimerT1SExpired( void ); -#endif - -#ifdef __cplusplus -PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfunccoils.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfunccoils.c deleted file mode 100644 index 0859318fb..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfunccoils.c +++ /dev/null @@ -1,269 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "stdlib.h" -#include "string.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "mod_port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbframe.h" -#include "mbproto.h" -#include "mbconfig.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_PDU_FUNC_READ_ADDR_OFF ( MB_PDU_DATA_OFF ) -#define MB_PDU_FUNC_READ_COILCNT_OFF ( MB_PDU_DATA_OFF + 2 ) -#define MB_PDU_FUNC_READ_SIZE ( 4 ) -#define MB_PDU_FUNC_READ_COILCNT_MAX ( 0x07D0 ) - -#define MB_PDU_FUNC_WRITE_ADDR_OFF ( MB_PDU_DATA_OFF ) -#define MB_PDU_FUNC_WRITE_VALUE_OFF ( MB_PDU_DATA_OFF + 2 ) -#define MB_PDU_FUNC_WRITE_SIZE ( 4 ) - -#define MB_PDU_FUNC_WRITE_MUL_ADDR_OFF ( MB_PDU_DATA_OFF ) -#define MB_PDU_FUNC_WRITE_MUL_COILCNT_OFF ( MB_PDU_DATA_OFF + 2 ) -#define MB_PDU_FUNC_WRITE_MUL_BYTECNT_OFF ( MB_PDU_DATA_OFF + 4 ) -#define MB_PDU_FUNC_WRITE_MUL_VALUES_OFF ( MB_PDU_DATA_OFF + 5 ) -#define MB_PDU_FUNC_WRITE_MUL_SIZE_MIN ( 5 ) -#define MB_PDU_FUNC_WRITE_MUL_COILCNT_MAX ( 0x07B0 ) - -/* ----------------------- Static functions ---------------------------------*/ -eMBException prveMBError2Exception( eMBErrorCode eErrorCode ); - -/* ----------------------- Start implementation -----------------------------*/ - -#if MB_FUNC_READ_COILS_ENABLED > 0 - -eMBException -eMBFuncReadCoils( UCHAR * pucFrame, USHORT * usLen ) -{ - USHORT usRegAddress; - USHORT usCoilCount; - UCHAR ucNBytes; - UCHAR *pucFrameCur; - - eMBException eStatus = MB_EX_NONE; - eMBErrorCode eRegStatus; - - if( *usLen == ( MB_PDU_FUNC_READ_SIZE + MB_PDU_SIZE_MIN ) ) - { - usRegAddress = ( USHORT )( pucFrame[MB_PDU_FUNC_READ_ADDR_OFF] << 8 ); - usRegAddress |= ( USHORT )( pucFrame[MB_PDU_FUNC_READ_ADDR_OFF + 1] ); - usRegAddress++; - - usCoilCount = ( USHORT )( pucFrame[MB_PDU_FUNC_READ_COILCNT_OFF] << 8 ); - usCoilCount |= ( USHORT )( pucFrame[MB_PDU_FUNC_READ_COILCNT_OFF + 1] ); - - /* Check if the number of registers to read is valid. If not - * return Modbus illegal data value exception. - */ - if( ( usCoilCount >= 1 ) && - ( usCoilCount < MB_PDU_FUNC_READ_COILCNT_MAX ) ) - { - /* Set the current PDU data pointer to the beginning. */ - pucFrameCur = &pucFrame[MB_PDU_FUNC_OFF]; - *usLen = MB_PDU_FUNC_OFF; - - /* First byte contains the function code. */ - *pucFrameCur++ = MB_FUNC_READ_COILS; - *usLen += 1; - - /* Test if the quantity of coils is a multiple of 8. If not last - * byte is only partially field with unused coils set to zero. */ - if( ( usCoilCount & 0x0007 ) != 0 ) - { - ucNBytes = ( UCHAR )( usCoilCount / 8 + 1 ); - } - else - { - ucNBytes = ( UCHAR )( usCoilCount / 8 ); - } - *pucFrameCur++ = ucNBytes; - *usLen += 1; - - eRegStatus = - eMBRegCoilsCB( pucFrameCur, usRegAddress, usCoilCount, - MB_REG_READ ); - - /* If an error occured convert it into a Modbus exception. */ - if( eRegStatus != MB_ENOERR ) - { - eStatus = prveMBError2Exception( eRegStatus ); - } - else - { - /* The response contains the function code, the starting address - * and the quantity of registers. We reuse the old values in the - * buffer because they are still valid. */ - *usLen += ucNBytes;; - } - } - else - { - eStatus = MB_EX_ILLEGAL_DATA_VALUE; - } - } - else - { - /* Can't be a valid read coil register request because the length - * is incorrect. */ - eStatus = MB_EX_ILLEGAL_DATA_VALUE; - } - return eStatus; -} - -#if MB_FUNC_WRITE_COIL_ENABLED > 0 -eMBException -eMBFuncWriteCoil( UCHAR * pucFrame, USHORT * usLen ) -{ - USHORT usRegAddress; - UCHAR ucBuf[2]; - - eMBException eStatus = MB_EX_NONE; - eMBErrorCode eRegStatus; - - if( *usLen == ( MB_PDU_FUNC_WRITE_SIZE + MB_PDU_SIZE_MIN ) ) - { - usRegAddress = ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_ADDR_OFF] << 8 ); - usRegAddress |= ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_ADDR_OFF + 1] ); - usRegAddress++; - - if( ( pucFrame[MB_PDU_FUNC_WRITE_VALUE_OFF + 1] == 0x00 ) && - ( ( pucFrame[MB_PDU_FUNC_WRITE_VALUE_OFF] == 0xFF ) || - ( pucFrame[MB_PDU_FUNC_WRITE_VALUE_OFF] == 0x00 ) ) ) - { - ucBuf[1] = 0; - if( pucFrame[MB_PDU_FUNC_WRITE_VALUE_OFF] == 0xFF ) - { - ucBuf[0] = 1; - } - else - { - ucBuf[0] = 0; - } - eRegStatus = - eMBRegCoilsCB( &ucBuf[0], usRegAddress, 1, MB_REG_WRITE ); - - /* If an error occured convert it into a Modbus exception. */ - if( eRegStatus != MB_ENOERR ) - { - eStatus = prveMBError2Exception( eRegStatus ); - } - } - else - { - eStatus = MB_EX_ILLEGAL_DATA_VALUE; - } - } - else - { - /* Can't be a valid write coil register request because the length - * is incorrect. */ - eStatus = MB_EX_ILLEGAL_DATA_VALUE; - } - return eStatus; -} - -#endif - -#if MB_FUNC_WRITE_MULTIPLE_COILS_ENABLED > 0 -eMBException -eMBFuncWriteMultipleCoils( UCHAR * pucFrame, USHORT * usLen ) -{ - USHORT usRegAddress; - USHORT usCoilCnt; - UCHAR ucByteCount; - UCHAR ucByteCountVerify; - - eMBException eStatus = MB_EX_NONE; - eMBErrorCode eRegStatus; - - if( *usLen > ( MB_PDU_FUNC_WRITE_SIZE + MB_PDU_SIZE_MIN ) ) - { - usRegAddress = ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_MUL_ADDR_OFF] << 8 ); - usRegAddress |= ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_MUL_ADDR_OFF + 1] ); - usRegAddress++; - - usCoilCnt = ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_MUL_COILCNT_OFF] << 8 ); - usCoilCnt |= ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_MUL_COILCNT_OFF + 1] ); - - ucByteCount = pucFrame[MB_PDU_FUNC_WRITE_MUL_BYTECNT_OFF]; - - /* Compute the number of expected bytes in the request. */ - if( ( usCoilCnt & 0x0007 ) != 0 ) - { - ucByteCountVerify = ( UCHAR )( usCoilCnt / 8 + 1 ); - } - else - { - ucByteCountVerify = ( UCHAR )( usCoilCnt / 8 ); - } - - if( ( usCoilCnt >= 1 ) && - ( usCoilCnt <= MB_PDU_FUNC_WRITE_MUL_COILCNT_MAX ) && - ( ucByteCountVerify == ucByteCount ) ) - { - eRegStatus = - eMBRegCoilsCB( &pucFrame[MB_PDU_FUNC_WRITE_MUL_VALUES_OFF], - usRegAddress, usCoilCnt, MB_REG_WRITE ); - - /* If an error occured convert it into a Modbus exception. */ - if( eRegStatus != MB_ENOERR ) - { - eStatus = prveMBError2Exception( eRegStatus ); - } - else - { - /* The response contains the function code, the starting address - * and the quantity of registers. We reuse the old values in the - * buffer because they are still valid. */ - *usLen = MB_PDU_FUNC_WRITE_MUL_BYTECNT_OFF; - } - } - else - { - eStatus = MB_EX_ILLEGAL_DATA_VALUE; - } - } - else - { - /* Can't be a valid write coil register request because the length - * is incorrect. */ - eStatus = MB_EX_ILLEGAL_DATA_VALUE; - } - return eStatus; -} - -#endif - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfuncdiag.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfuncdiag.c deleted file mode 100644 index 8c32e85b1..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfuncdiag.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfuncdisc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfuncdisc.c deleted file mode 100644 index d6f36a872..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfuncdisc.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "stdlib.h" -#include "string.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "mod_port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbframe.h" -#include "mbproto.h" -#include "mbconfig.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_PDU_FUNC_READ_ADDR_OFF ( MB_PDU_DATA_OFF ) -#define MB_PDU_FUNC_READ_DISCCNT_OFF ( MB_PDU_DATA_OFF + 2 ) -#define MB_PDU_FUNC_READ_SIZE ( 4 ) -#define MB_PDU_FUNC_READ_DISCCNT_MAX ( 0x07D0 ) - -/* ----------------------- Static functions ---------------------------------*/ -eMBException prveMBError2Exception( eMBErrorCode eErrorCode ); - -/* ----------------------- Start implementation -----------------------------*/ - -#if MB_FUNC_READ_COILS_ENABLED > 0 - -eMBException -eMBFuncReadDiscreteInputs( UCHAR * pucFrame, USHORT * usLen ) -{ - USHORT usRegAddress; - USHORT usDiscreteCnt; - UCHAR ucNBytes; - UCHAR *pucFrameCur; - - eMBException eStatus = MB_EX_NONE; - eMBErrorCode eRegStatus; - - if( *usLen == ( MB_PDU_FUNC_READ_SIZE + MB_PDU_SIZE_MIN ) ) - { - usRegAddress = ( USHORT )( pucFrame[MB_PDU_FUNC_READ_ADDR_OFF] << 8 ); - usRegAddress |= ( USHORT )( pucFrame[MB_PDU_FUNC_READ_ADDR_OFF + 1] ); - usRegAddress++; - - usDiscreteCnt = ( USHORT )( pucFrame[MB_PDU_FUNC_READ_DISCCNT_OFF] << 8 ); - usDiscreteCnt |= ( USHORT )( pucFrame[MB_PDU_FUNC_READ_DISCCNT_OFF + 1] ); - - /* Check if the number of registers to read is valid. If not - * return Modbus illegal data value exception. - */ - if( ( usDiscreteCnt >= 1 ) && - ( usDiscreteCnt < MB_PDU_FUNC_READ_DISCCNT_MAX ) ) - { - /* Set the current PDU data pointer to the beginning. */ - pucFrameCur = &pucFrame[MB_PDU_FUNC_OFF]; - *usLen = MB_PDU_FUNC_OFF; - - /* First byte contains the function code. */ - *pucFrameCur++ = MB_FUNC_READ_DISCRETE_INPUTS; - *usLen += 1; - - /* Test if the quantity of coils is a multiple of 8. If not last - * byte is only partially field with unused coils set to zero. */ - if( ( usDiscreteCnt & 0x0007 ) != 0 ) - { - ucNBytes = ( UCHAR ) ( usDiscreteCnt / 8 + 1 ); - } - else - { - ucNBytes = ( UCHAR ) ( usDiscreteCnt / 8 ); - } - *pucFrameCur++ = ucNBytes; - *usLen += 1; - - eRegStatus = - eMBRegDiscreteCB( pucFrameCur, usRegAddress, usDiscreteCnt ); - - /* If an error occured convert it into a Modbus exception. */ - if( eRegStatus != MB_ENOERR ) - { - eStatus = prveMBError2Exception( eRegStatus ); - } - else - { - /* The response contains the function code, the starting address - * and the quantity of registers. We reuse the old values in the - * buffer because they are still valid. */ - *usLen += ucNBytes;; - } - } - else - { - eStatus = MB_EX_ILLEGAL_DATA_VALUE; - } - } - else - { - /* Can't be a valid read coil register request because the length - * is incorrect. */ - eStatus = MB_EX_ILLEGAL_DATA_VALUE; - } - return eStatus; -} - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfuncholding.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfuncholding.c deleted file mode 100644 index ddac166fb..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfuncholding.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "stdlib.h" -#include "string.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "mod_port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbframe.h" -#include "mbproto.h" -#include "mbconfig.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_PDU_FUNC_READ_ADDR_OFF ( MB_PDU_DATA_OFF + 0) -#define MB_PDU_FUNC_READ_REGCNT_OFF ( MB_PDU_DATA_OFF + 2 ) -#define MB_PDU_FUNC_READ_SIZE ( 4 ) -#define MB_PDU_FUNC_READ_REGCNT_MAX ( 0x007D ) - -#define MB_PDU_FUNC_WRITE_ADDR_OFF ( MB_PDU_DATA_OFF + 0) -#define MB_PDU_FUNC_WRITE_VALUE_OFF ( MB_PDU_DATA_OFF + 2 ) -#define MB_PDU_FUNC_WRITE_SIZE ( 4 ) - -#define MB_PDU_FUNC_WRITE_MUL_ADDR_OFF ( MB_PDU_DATA_OFF + 0 ) -#define MB_PDU_FUNC_WRITE_MUL_REGCNT_OFF ( MB_PDU_DATA_OFF + 2 ) -#define MB_PDU_FUNC_WRITE_MUL_BYTECNT_OFF ( MB_PDU_DATA_OFF + 4 ) -#define MB_PDU_FUNC_WRITE_MUL_VALUES_OFF ( MB_PDU_DATA_OFF + 5 ) -#define MB_PDU_FUNC_WRITE_MUL_SIZE_MIN ( 5 ) -#define MB_PDU_FUNC_WRITE_MUL_REGCNT_MAX ( 0x0078 ) - -#define MB_PDU_FUNC_READWRITE_READ_ADDR_OFF ( MB_PDU_DATA_OFF + 0 ) -#define MB_PDU_FUNC_READWRITE_READ_REGCNT_OFF ( MB_PDU_DATA_OFF + 2 ) -#define MB_PDU_FUNC_READWRITE_WRITE_ADDR_OFF ( MB_PDU_DATA_OFF + 4 ) -#define MB_PDU_FUNC_READWRITE_WRITE_REGCNT_OFF ( MB_PDU_DATA_OFF + 6 ) -#define MB_PDU_FUNC_READWRITE_BYTECNT_OFF ( MB_PDU_DATA_OFF + 8 ) -#define MB_PDU_FUNC_READWRITE_WRITE_VALUES_OFF ( MB_PDU_DATA_OFF + 9 ) -#define MB_PDU_FUNC_READWRITE_SIZE_MIN ( 9 ) - -/* ----------------------- Static functions ---------------------------------*/ -eMBException prveMBError2Exception( eMBErrorCode eErrorCode ); - -/* ----------------------- Start implementation -----------------------------*/ - -#if MB_FUNC_WRITE_HOLDING_ENABLED > 0 - -eMBException -eMBFuncWriteHoldingRegister( UCHAR * pucFrame, USHORT * usLen ) -{ - USHORT usRegAddress; - eMBException eStatus = MB_EX_NONE; - eMBErrorCode eRegStatus; - - if( *usLen == ( MB_PDU_FUNC_WRITE_SIZE + MB_PDU_SIZE_MIN ) ) - { - usRegAddress = ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_ADDR_OFF] << 8 ); - usRegAddress |= ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_ADDR_OFF + 1] ); - usRegAddress++; - - /* Make callback to update the value. */ - eRegStatus = eMBRegHoldingCB( &pucFrame[MB_PDU_FUNC_WRITE_VALUE_OFF], - usRegAddress, 1, MB_REG_WRITE ); - - /* If an error occured convert it into a Modbus exception. */ - if( eRegStatus != MB_ENOERR ) - { - eStatus = prveMBError2Exception( eRegStatus ); - } - } - else - { - /* Can't be a valid request because the length is incorrect. */ - eStatus = MB_EX_ILLEGAL_DATA_VALUE; - } - return eStatus; -} -#endif - -#if MB_FUNC_WRITE_MULTIPLE_HOLDING_ENABLED > 0 -eMBException -eMBFuncWriteMultipleHoldingRegister( UCHAR * pucFrame, USHORT * usLen ) -{ - USHORT usRegAddress; - USHORT usRegCount; - UCHAR ucRegByteCount; - - eMBException eStatus = MB_EX_NONE; - eMBErrorCode eRegStatus; - - if( *usLen >= ( MB_PDU_FUNC_WRITE_MUL_SIZE_MIN + MB_PDU_SIZE_MIN ) ) - { - usRegAddress = ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_MUL_ADDR_OFF] << 8 ); - usRegAddress |= ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_MUL_ADDR_OFF + 1] ); - usRegAddress++; - - usRegCount = ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_MUL_REGCNT_OFF] << 8 ); - usRegCount |= ( USHORT )( pucFrame[MB_PDU_FUNC_WRITE_MUL_REGCNT_OFF + 1] ); - - ucRegByteCount = pucFrame[MB_PDU_FUNC_WRITE_MUL_BYTECNT_OFF]; - - if( ( usRegCount >= 1 ) && - ( usRegCount <= MB_PDU_FUNC_WRITE_MUL_REGCNT_MAX ) && - ( ucRegByteCount == ( UCHAR ) ( 2 * usRegCount ) ) ) - { - /* Make callback to update the register values. */ - eRegStatus = - eMBRegHoldingCB( &pucFrame[MB_PDU_FUNC_WRITE_MUL_VALUES_OFF], - usRegAddress, usRegCount, MB_REG_WRITE ); - - /* If an error occured convert it into a Modbus exception. */ - if( eRegStatus != MB_ENOERR ) - { - eStatus = prveMBError2Exception( eRegStatus ); - } - else - { - /* The response contains the function code, the starting - * address and the quantity of registers. We reuse the - * old values in the buffer because they are still valid. - */ - *usLen = MB_PDU_FUNC_WRITE_MUL_BYTECNT_OFF; - } - } - else - { - eStatus = MB_EX_ILLEGAL_DATA_VALUE; - } - } - else - { - /* Can't be a valid request because the length is incorrect. */ - eStatus = MB_EX_ILLEGAL_DATA_VALUE; - } - return eStatus; -} -#endif - -#if MB_FUNC_READ_HOLDING_ENABLED > 0 - -eMBException -eMBFuncReadHoldingRegister( UCHAR * pucFrame, USHORT * usLen ) -{ - USHORT usRegAddress; - USHORT usRegCount; - UCHAR *pucFrameCur; - - eMBException eStatus = MB_EX_NONE; - eMBErrorCode eRegStatus; - - if( *usLen == ( MB_PDU_FUNC_READ_SIZE + MB_PDU_SIZE_MIN ) ) - { - usRegAddress = ( USHORT )( pucFrame[MB_PDU_FUNC_READ_ADDR_OFF] << 8 ); - usRegAddress |= ( USHORT )( pucFrame[MB_PDU_FUNC_READ_ADDR_OFF + 1] ); - usRegAddress++; - - usRegCount = ( USHORT )( pucFrame[MB_PDU_FUNC_READ_REGCNT_OFF] << 8 ); - usRegCount = ( USHORT )( pucFrame[MB_PDU_FUNC_READ_REGCNT_OFF + 1] ); - - /* Check if the number of registers to read is valid. If not - * return Modbus illegal data value exception. - */ - if( ( usRegCount >= 1 ) && ( usRegCount <= MB_PDU_FUNC_READ_REGCNT_MAX ) ) - { - /* Set the current PDU data pointer to the beginning. */ - pucFrameCur = &pucFrame[MB_PDU_FUNC_OFF]; - *usLen = MB_PDU_FUNC_OFF; - - /* First byte contains the function code. */ - *pucFrameCur++ = MB_FUNC_READ_HOLDING_REGISTER; - *usLen += 1; - - /* Second byte in the response contain the number of bytes. */ - *pucFrameCur++ = ( UCHAR ) ( usRegCount * 2 ); - *usLen += 1; - - /* Make callback to fill the buffer. */ - eRegStatus = eMBRegHoldingCB( pucFrameCur, usRegAddress, usRegCount, MB_REG_READ ); - /* If an error occured convert it into a Modbus exception. */ - if( eRegStatus != MB_ENOERR ) - { - eStatus = prveMBError2Exception( eRegStatus ); - } - else - { - *usLen += usRegCount * 2; - } - } - else - { - eStatus = MB_EX_ILLEGAL_DATA_VALUE; - } - } - else - { - /* Can't be a valid request because the length is incorrect. */ - eStatus = MB_EX_ILLEGAL_DATA_VALUE; - } - return eStatus; -} - -#endif - -#if MB_FUNC_READWRITE_HOLDING_ENABLED > 0 - -eMBException -eMBFuncReadWriteMultipleHoldingRegister( UCHAR * pucFrame, USHORT * usLen ) -{ - USHORT usRegReadAddress; - USHORT usRegReadCount; - USHORT usRegWriteAddress; - USHORT usRegWriteCount; - UCHAR ucRegWriteByteCount; - UCHAR *pucFrameCur; - - eMBException eStatus = MB_EX_NONE; - eMBErrorCode eRegStatus; - - if( *usLen >= ( MB_PDU_FUNC_READWRITE_SIZE_MIN + MB_PDU_SIZE_MIN ) ) - { - usRegReadAddress = ( USHORT )( pucFrame[MB_PDU_FUNC_READWRITE_READ_ADDR_OFF] << 8U ); - usRegReadAddress |= ( USHORT )( pucFrame[MB_PDU_FUNC_READWRITE_READ_ADDR_OFF + 1] ); - usRegReadAddress++; - - usRegReadCount = ( USHORT )( pucFrame[MB_PDU_FUNC_READWRITE_READ_REGCNT_OFF] << 8U ); - usRegReadCount |= ( USHORT )( pucFrame[MB_PDU_FUNC_READWRITE_READ_REGCNT_OFF + 1] ); - - usRegWriteAddress = ( USHORT )( pucFrame[MB_PDU_FUNC_READWRITE_WRITE_ADDR_OFF] << 8U ); - usRegWriteAddress |= ( USHORT )( pucFrame[MB_PDU_FUNC_READWRITE_WRITE_ADDR_OFF + 1] ); - usRegWriteAddress++; - - usRegWriteCount = ( USHORT )( pucFrame[MB_PDU_FUNC_READWRITE_WRITE_REGCNT_OFF] << 8U ); - usRegWriteCount |= ( USHORT )( pucFrame[MB_PDU_FUNC_READWRITE_WRITE_REGCNT_OFF + 1] ); - - ucRegWriteByteCount = pucFrame[MB_PDU_FUNC_READWRITE_BYTECNT_OFF]; - - if( ( usRegReadCount >= 1 ) && ( usRegReadCount <= 0x7D ) && - ( usRegWriteCount >= 1 ) && ( usRegWriteCount <= 0x79 ) && - ( ( 2 * usRegWriteCount ) == ucRegWriteByteCount ) ) - { - /* Make callback to update the register values. */ - eRegStatus = eMBRegHoldingCB( &pucFrame[MB_PDU_FUNC_READWRITE_WRITE_VALUES_OFF], - usRegWriteAddress, usRegWriteCount, MB_REG_WRITE ); - - if( eRegStatus == MB_ENOERR ) - { - /* Set the current PDU data pointer to the beginning. */ - pucFrameCur = &pucFrame[MB_PDU_FUNC_OFF]; - *usLen = MB_PDU_FUNC_OFF; - - /* First byte contains the function code. */ - *pucFrameCur++ = MB_FUNC_READWRITE_MULTIPLE_REGISTERS; - *usLen += 1; - - /* Second byte in the response contain the number of bytes. */ - *pucFrameCur++ = ( UCHAR ) ( usRegReadCount * 2 ); - *usLen += 1; - - /* Make the read callback. */ - eRegStatus = - eMBRegHoldingCB( pucFrameCur, usRegReadAddress, usRegReadCount, MB_REG_READ ); - if( eRegStatus == MB_ENOERR ) - { - *usLen += 2 * usRegReadCount; - } - } - if( eRegStatus != MB_ENOERR ) - { - eStatus = prveMBError2Exception( eRegStatus ); - } - } - else - { - eStatus = MB_EX_ILLEGAL_DATA_VALUE; - } - } - return eStatus; -} - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfuncinput.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfuncinput.c deleted file mode 100644 index b510de7f9..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfuncinput.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "stdlib.h" -#include "string.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "mod_port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbframe.h" -#include "mbproto.h" -#include "mbconfig.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_PDU_FUNC_READ_ADDR_OFF ( MB_PDU_DATA_OFF ) -#define MB_PDU_FUNC_READ_REGCNT_OFF ( MB_PDU_DATA_OFF + 2 ) -#define MB_PDU_FUNC_READ_SIZE ( 4 ) -#define MB_PDU_FUNC_READ_REGCNT_MAX ( 0x007D ) - -#define MB_PDU_FUNC_READ_RSP_BYTECNT_OFF ( MB_PDU_DATA_OFF ) - -/* ----------------------- Static functions ---------------------------------*/ -eMBException prveMBError2Exception( eMBErrorCode eErrorCode ); - -/* ----------------------- Start implementation -----------------------------*/ -#if MB_FUNC_READ_INPUT_ENABLED > 0 - -eMBException -eMBFuncReadInputRegister( UCHAR * pucFrame, USHORT * usLen ) -{ - USHORT usRegAddress; - USHORT usRegCount; - UCHAR *pucFrameCur; - - eMBException eStatus = MB_EX_NONE; - eMBErrorCode eRegStatus; - - if( *usLen == ( MB_PDU_FUNC_READ_SIZE + MB_PDU_SIZE_MIN ) ) - { - usRegAddress = ( USHORT )( pucFrame[MB_PDU_FUNC_READ_ADDR_OFF] << 8 ); - usRegAddress |= ( USHORT )( pucFrame[MB_PDU_FUNC_READ_ADDR_OFF + 1] ); - usRegAddress++; - - usRegCount = ( USHORT )( pucFrame[MB_PDU_FUNC_READ_REGCNT_OFF] << 8 ); - usRegCount |= ( USHORT )( pucFrame[MB_PDU_FUNC_READ_REGCNT_OFF + 1] ); - - /* Check if the number of registers to read is valid. If not - * return Modbus illegal data value exception. - */ - if( ( usRegCount >= 1 ) - && ( usRegCount < MB_PDU_FUNC_READ_REGCNT_MAX ) ) - { - /* Set the current PDU data pointer to the beginning. */ - pucFrameCur = &pucFrame[MB_PDU_FUNC_OFF]; - *usLen = MB_PDU_FUNC_OFF; - - /* First byte contains the function code. */ - *pucFrameCur++ = MB_FUNC_READ_INPUT_REGISTER; - *usLen += 1; - - /* Second byte in the response contain the number of bytes. */ - *pucFrameCur++ = ( UCHAR )( usRegCount * 2 ); - *usLen += 1; - - eRegStatus = - eMBRegInputCB( pucFrameCur, usRegAddress, usRegCount ); - - /* If an error occured convert it into a Modbus exception. */ - if( eRegStatus != MB_ENOERR ) - { - eStatus = prveMBError2Exception( eRegStatus ); - } - else - { - *usLen += usRegCount * 2; - } - } - else - { - eStatus = MB_EX_ILLEGAL_DATA_VALUE; - } - } - else - { - /* Can't be a valid read input register request because the length - * is incorrect. */ - eStatus = MB_EX_ILLEGAL_DATA_VALUE; - } - return eStatus; -} - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfuncother.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfuncother.c deleted file mode 100644 index 77dc1d015..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbfuncother.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "stdlib.h" -#include "string.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "mod_port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbframe.h" -#include "mbproto.h" -#include "mbconfig.h" - -#if MB_FUNC_OTHER_REP_SLAVEID_ENABLED > 0 - -/* ----------------------- Static variables ---------------------------------*/ -static UCHAR ucMBSlaveID[MB_FUNC_OTHER_REP_SLAVEID_BUF]; -static USHORT usMBSlaveIDLen; - -/* ----------------------- Start implementation -----------------------------*/ - -eMBErrorCode -eMBSetSlaveID( UCHAR ucSlaveID, BOOL xIsRunning, - UCHAR const *pucAdditional, USHORT usAdditionalLen ) -{ - eMBErrorCode eStatus = MB_ENOERR; - - /* the first byte and second byte in the buffer is reserved for - * the parameter ucSlaveID and the running flag. The rest of - * the buffer is available for additional data. */ - if( usAdditionalLen + 2 < MB_FUNC_OTHER_REP_SLAVEID_BUF ) - { - usMBSlaveIDLen = 0; - ucMBSlaveID[usMBSlaveIDLen++] = ucSlaveID; - ucMBSlaveID[usMBSlaveIDLen++] = ( UCHAR )( xIsRunning ? 0xFF : 0x00 ); - if( usAdditionalLen > 0 ) - { - memcpy( &ucMBSlaveID[usMBSlaveIDLen], pucAdditional, - ( size_t )usAdditionalLen ); - usMBSlaveIDLen += usAdditionalLen; - } - } - else - { - eStatus = MB_ENORES; - } - return eStatus; -} - -eMBException -eMBFuncReportSlaveID( UCHAR * pucFrame, USHORT * usLen ) -{ - memcpy( &pucFrame[MB_PDU_DATA_OFF], &ucMBSlaveID[0], ( size_t )usMBSlaveIDLen ); - *usLen = ( USHORT )( MB_PDU_DATA_OFF + usMBSlaveIDLen ); - return MB_EX_NONE; -} - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbutils.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbutils.c deleted file mode 100644 index 7bf688b1b..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/functions/mbutils.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "stdlib.h" -#include "string.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "mod_port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbproto.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define BITS_UCHAR 8U - -/* ----------------------- Start implementation -----------------------------*/ -void -xMBUtilSetBits( UCHAR * ucByteBuf, USHORT usBitOffset, UCHAR ucNBits, - UCHAR ucValue ) -{ - USHORT usWordBuf; - USHORT usMask; - USHORT usByteOffset; - USHORT usNPreBits; - USHORT usValue = ucValue; - - assert( ucNBits <= 8 ); - assert( ( size_t )BITS_UCHAR == sizeof( UCHAR ) * 8 ); - - /* Calculate byte offset for first byte containing the bit values starting - * at usBitOffset. */ - usByteOffset = ( USHORT )( ( usBitOffset ) / BITS_UCHAR ); - - /* How many bits precede our bits to set. */ - usNPreBits = ( USHORT )( usBitOffset - usByteOffset * BITS_UCHAR ); - - /* Move bit field into position over bits to set */ - usValue <<= usNPreBits; - - /* Prepare a mask for setting the new bits. */ - usMask = ( USHORT )( ( 1 << ( USHORT ) ucNBits ) - 1 ); - usMask <<= usBitOffset - usByteOffset * BITS_UCHAR; - - /* copy bits into temporary storage. */ - usWordBuf = ucByteBuf[usByteOffset]; - usWordBuf |= ucByteBuf[usByteOffset + 1] << BITS_UCHAR; - - /* Zero out bit field bits and then or value bits into them. */ - usWordBuf = ( USHORT )( ( usWordBuf & ( ~usMask ) ) | usValue ); - - /* move bits back into storage */ - ucByteBuf[usByteOffset] = ( UCHAR )( usWordBuf & 0xFF ); - ucByteBuf[usByteOffset + 1] = ( UCHAR )( usWordBuf >> BITS_UCHAR ); -} - -UCHAR -xMBUtilGetBits( UCHAR * ucByteBuf, USHORT usBitOffset, UCHAR ucNBits ) -{ - USHORT usWordBuf; - USHORT usMask; - USHORT usByteOffset; - USHORT usNPreBits; - - /* Calculate byte offset for first byte containing the bit values starting - * at usBitOffset. */ - usByteOffset = ( USHORT )( ( usBitOffset ) / BITS_UCHAR ); - - /* How many bits precede our bits to set. */ - usNPreBits = ( USHORT )( usBitOffset - usByteOffset * BITS_UCHAR ); - - /* Prepare a mask for setting the new bits. */ - usMask = ( USHORT )( ( 1 << ( USHORT ) ucNBits ) - 1 ); - - /* copy bits into temporary storage. */ - usWordBuf = ucByteBuf[usByteOffset]; - usWordBuf |= ucByteBuf[usByteOffset + 1] << BITS_UCHAR; - - /* throw away unneeded bits. */ - usWordBuf >>= usNPreBits; - - /* mask away bits above the requested bitfield. */ - usWordBuf &= usMask; - - return ( UCHAR ) usWordBuf; -} - -eMBException -prveMBError2Exception( eMBErrorCode eErrorCode ) -{ - eMBException eStatus; - - switch ( eErrorCode ) - { - case MB_ENOERR: - eStatus = MB_EX_NONE; - break; - - case MB_ENOREG: - eStatus = MB_EX_ILLEGAL_DATA_ADDRESS; - break; - - case MB_ETIMEDOUT: - eStatus = MB_EX_SLAVE_BUSY; - break; - - default: - eStatus = MB_EX_SLAVE_DEVICE_FAILURE; - break; - } - - return eStatus; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mb.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mb.h deleted file mode 100644 index d3e1620ae..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mb.h +++ /dev/null @@ -1,416 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _MB_H -#define _MB_H - -#include "mod_port.h" - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif - -#include "mbport.h" -#include "mbproto.h" - -/*! \defgroup modbus Modbus - * \code #include "mb.h" \endcode - * - * This module defines the interface for the application. It contains - * the basic functions and types required to use the Modbus protocol stack. - * A typical application will want to call eMBInit() first. If the device - * is ready to answer network requests it must then call eMBEnable() to activate - * the protocol stack. In the main loop the function eMBPoll() must be called - * periodically. The time interval between pooling depends on the configured - * Modbus timeout. If an RTOS is available a separate task should be created - * and the task should always call the function eMBPoll(). - * - * \code - * // Initialize protocol stack in RTU mode for a slave with address 10 = 0x0A - * eMBInit( MB_RTU, 0x0A, 38400, MB_PAR_EVEN ); - * // Enable the Modbus Protocol Stack. - * eMBEnable( ); - * for( ;; ) - * { - * // Call the main polling loop of the Modbus protocol stack. - * eMBPoll( ); - * ... - * } - * \endcode - */ - -/* ----------------------- Defines ------------------------------------------*/ - -/*! \ingroup modbus - * \brief Use the default Modbus TCP port (502) - */ -#define MB_TCP_PORT_USE_DEFAULT 0 - -/* ----------------------- Type definitions ---------------------------------*/ - -/*! \ingroup modbus - * \brief Modbus serial transmission modes (RTU/ASCII). - * - * Modbus serial supports two transmission modes. Either ASCII or RTU. RTU - * is faster but has more hardware requirements and requires a network with - * a low jitter. ASCII is slower and more reliable on slower links (E.g. modems) - */ - typedef enum -{ - MB_RTU, /*!< RTU transmission mode. */ - MB_ASCII, /*!< ASCII transmission mode. */ - MB_TCP /*!< TCP mode. */ -} eMBMode; - -/*! \ingroup modbus - * \brief If register should be written or read. - * - * This value is passed to the callback functions which support either - * reading or writing register values. Writing means that the application - * registers should be updated and reading means that the modbus protocol - * stack needs to know the current register values. - * - * \see eMBRegHoldingCB( ), eMBRegCoilsCB( ), eMBRegDiscreteCB( ) and - * eMBRegInputCB( ). - */ -typedef enum -{ - MB_REG_READ, /*!< Read register values and pass to protocol stack. */ - MB_REG_WRITE /*!< Update register values. */ -} eMBRegisterMode; - -/*! \ingroup modbus - * \brief Errorcodes used by all function in the protocol stack. - */ -typedef enum -{ - MB_ENOERR, /*!< no error. */ - MB_ENOREG, /*!< illegal register address. */ - MB_EINVAL, /*!< illegal argument. */ - MB_EPORTERR, /*!< porting layer error. */ - MB_ENORES, /*!< insufficient resources. */ - MB_EIO, /*!< I/O error. */ - MB_EILLSTATE, /*!< protocol stack in illegal state. */ - MB_ETIMEDOUT /*!< timeout error occurred. */ -} eMBErrorCode; - - -/* ----------------------- Function prototypes ------------------------------*/ -/*! \ingroup modbus - * \brief Initialize the Modbus protocol stack. - * - * This functions initializes the ASCII or RTU module and calls the - * init functions of the porting layer to prepare the hardware. Please - * note that the receiver is still disabled and no Modbus frames are - * processed until eMBEnable( ) has been called. - * - * \param eMode If ASCII or RTU mode should be used. - * \param ucSlaveAddress The slave address. Only frames sent to this - * address or to the broadcast address are processed. - * \param ucPort The port to use. E.g. 1 for COM1 on windows. This value - * is platform dependent and some ports simply choose to ignore it. - * \param ulBaudRate The baudrate. E.g. 19200. Supported baudrates depend - * on the porting layer. - * \param eParity Parity used for serial transmission. - * - * \return If no error occurs the function returns eMBErrorCode::MB_ENOERR. - * The protocol is then in the disabled state and ready for activation - * by calling eMBEnable( ). Otherwise one of the following error codes - * is returned: - * - eMBErrorCode::MB_EINVAL If the slave address was not valid. Valid - * slave addresses are in the range 1 - 247. - * - eMBErrorCode::MB_EPORTERR IF the porting layer returned an error. - */ -eMBErrorCode eMBInit( eMBMode eMode, UCHAR ucSlaveAddress, - UCHAR ucPort, ULONG ulBaudRate, eMBParity eParity ); - -/*! \ingroup modbus - * \brief Initialize the Modbus protocol stack for Modbus TCP. - * - * This function initializes the Modbus TCP Module. Please note that - * frame processing is still disabled until eMBEnable( ) is called. - * - * \param usTCPPort The TCP port to listen on. - * \return If the protocol stack has been initialized correctly the function - * returns eMBErrorCode::MB_ENOERR. Otherwise one of the following error - * codes is returned: - * - eMBErrorCode::MB_EINVAL If the slave address was not valid. Valid - * slave addresses are in the range 1 - 247. - * - eMBErrorCode::MB_EPORTERR IF the porting layer returned an error. - */ -eMBErrorCode eMBTCPInit( USHORT usTCPPort ); - -/*! \ingroup modbus - * \brief Release resources used by the protocol stack. - * - * This function disables the Modbus protocol stack and release all - * hardware resources. It must only be called when the protocol stack - * is disabled. - * - * \note Note all ports implement this function. A port which wants to - * get an callback must define the macro MB_PORT_HAS_CLOSE to 1. - * - * \return If the resources where released it return eMBErrorCode::MB_ENOERR. - * If the protocol stack is not in the disabled state it returns - * eMBErrorCode::MB_EILLSTATE. - */ -eMBErrorCode eMBClose( void ); - -/*! \ingroup modbus - * \brief Enable the Modbus protocol stack. - * - * This function enables processing of Modbus frames. Enabling the protocol - * stack is only possible if it is in the disabled state. - * - * \return If the protocol stack is now in the state enabled it returns - * eMBErrorCode::MB_ENOERR. If it was not in the disabled state it - * return eMBErrorCode::MB_EILLSTATE. - */ -eMBErrorCode eMBEnable( void ); - -/*! \ingroup modbus - * \brief Disable the Modbus protocol stack. - * - * This function disables processing of Modbus frames. - * - * \return If the protocol stack has been disabled it returns - * eMBErrorCode::MB_ENOERR. If it was not in the enabled state it returns - * eMBErrorCode::MB_EILLSTATE. - */ -eMBErrorCode eMBDisable( void ); - -/*! \ingroup modbus - * \brief The main pooling loop of the Modbus protocol stack. - * - * This function must be called periodically. The timer interval required - * is given by the application dependent Modbus slave timeout. Internally the - * function calls xMBPortEventGet() and waits for an event from the receiver or - * transmitter state machines. - * - * \return If the protocol stack is not in the enabled state the function - * returns eMBErrorCode::MB_EILLSTATE. Otherwise it returns - * eMBErrorCode::MB_ENOERR. - */ -eMBErrorCode eMBPoll( void ); - -/*! \ingroup modbus - * \brief Configure the slave id of the device. - * - * This function should be called when the Modbus function Report Slave ID - * is enabled ( By defining MB_FUNC_OTHER_REP_SLAVEID_ENABLED in mbconfig.h ). - * - * \param ucSlaveID Values is returned in the Slave ID byte of the - * Report Slave ID response. - * \param xIsRunning If TRUE the Run Indicator Status byte is set to 0xFF. - * otherwise the Run Indicator Status is 0x00. - * \param pucAdditional Values which should be returned in the Additional - * bytes of the Report Slave ID response. - * \param usAdditionalLen Length of the buffer pucAdditonal. - * - * \return If the static buffer defined by MB_FUNC_OTHER_REP_SLAVEID_BUF in - * mbconfig.h is to small it returns eMBErrorCode::MB_ENORES. Otherwise - * it returns eMBErrorCode::MB_ENOERR. - */ -eMBErrorCode eMBSetSlaveID( UCHAR ucSlaveID, BOOL xIsRunning, - UCHAR const *pucAdditional, - USHORT usAdditionalLen ); - -/*! \ingroup modbus - * \brief Registers a callback handler for a given function code. - * - * This function registers a new callback handler for a given function code. - * The callback handler supplied is responsible for interpreting the Modbus PDU and - * the creation of an appropriate response. In case of an error it should return - * one of the possible Modbus exceptions which results in a Modbus exception frame - * sent by the protocol stack. - * - * \param ucFunctionCode The Modbus function code for which this handler should - * be registers. Valid function codes are in the range 1 to 127. - * \param pxHandler The function handler which should be called in case - * such a frame is received. If \c NULL a previously registered function handler - * for this function code is removed. - * - * \return eMBErrorCode::MB_ENOERR if the handler has been installed. If no - * more resources are available it returns eMBErrorCode::MB_ENORES. In this - * case the values in mbconfig.h should be adjusted. If the argument was not - * valid it returns eMBErrorCode::MB_EINVAL. - */ -eMBErrorCode eMBRegisterCB( UCHAR ucFunctionCode, - pxMBFunctionHandler pxHandler ); - -/* ----------------------- Callback -----------------------------------------*/ - -/*! \defgroup modbus_registers Modbus Registers - * \code #include "mb.h" \endcode - * The protocol stack does not internally allocate any memory for the - * registers. This makes the protocol stack very small and also usable on - * low end targets. In addition the values don't have to be in the memory - * and could for example be stored in a flash.
- * Whenever the protocol stack requires a value it calls one of the callback - * function with the register address and the number of registers to read - * as an argument. The application should then read the actual register values - * (for example the ADC voltage) and should store the result in the supplied - * buffer.
- * If the protocol stack wants to update a register value because a write - * register function was received a buffer with the new register values is - * passed to the callback function. The function should then use these values - * to update the application register values. - */ - -/*! \ingroup modbus_registers - * \brief Callback function used if the value of a Input Register - * is required by the protocol stack. The starting register address is given - * by \c usAddress and the last register is given by usAddress + - * usNRegs - 1. - * - * \param pucRegBuffer A buffer where the callback function should write - * the current value of the modbus registers to. - * \param usAddress The starting address of the register. Input registers - * are in the range 1 - 65535. - * \param usNRegs Number of registers the callback function must supply. - * - * \return The function must return one of the following error codes: - * - eMBErrorCode::MB_ENOERR If no error occurred. In this case a normal - * Modbus response is sent. - * - eMBErrorCode::MB_ENOREG If the application can not supply values - * for registers within this range. In this case a - * ILLEGAL DATA ADDRESS exception frame is sent as a response. - * - eMBErrorCode::MB_ETIMEDOUT If the requested register block is - * currently not available and the application dependent response - * timeout would be violated. In this case a SLAVE DEVICE BUSY - * exception is sent as a response. - * - eMBErrorCode::MB_EIO If an unrecoverable error occurred. In this case - * a SLAVE DEVICE FAILURE exception is sent as a response. - */ -eMBErrorCode eMBRegInputCB( UCHAR * pucRegBuffer, USHORT usAddress, - USHORT usNRegs ); - -/*! \ingroup modbus_registers - * \brief Callback function used if a Holding Register value is - * read or written by the protocol stack. The starting register address - * is given by \c usAddress and the last register is given by - * usAddress + usNRegs - 1. - * - * \param pucRegBuffer If the application registers values should be updated the - * buffer points to the new registers values. If the protocol stack needs - * to now the current values the callback function should write them into - * this buffer. - * \param usAddress The starting address of the register. - * \param usNRegs Number of registers to read or write. - * \param eMode If eMBRegisterMode::MB_REG_WRITE the application register - * values should be updated from the values in the buffer. For example - * this would be the case when the Modbus master has issued an - * WRITE SINGLE REGISTER command. - * If the value eMBRegisterMode::MB_REG_READ the application should copy - * the current values into the buffer \c pucRegBuffer. - * - * \return The function must return one of the following error codes: - * - eMBErrorCode::MB_ENOERR If no error occurred. In this case a normal - * Modbus response is sent. - * - eMBErrorCode::MB_ENOREG If the application can not supply values - * for registers within this range. In this case a - * ILLEGAL DATA ADDRESS exception frame is sent as a response. - * - eMBErrorCode::MB_ETIMEDOUT If the requested register block is - * currently not available and the application dependent response - * timeout would be violated. In this case a SLAVE DEVICE BUSY - * exception is sent as a response. - * - eMBErrorCode::MB_EIO If an unrecoverable error occurred. In this case - * a SLAVE DEVICE FAILURE exception is sent as a response. - */ -eMBErrorCode eMBRegHoldingCB( UCHAR * pucRegBuffer, USHORT usAddress, - USHORT usNRegs, eMBRegisterMode eMode ); - -/*! \ingroup modbus_registers - * \brief Callback function used if a Coil Register value is - * read or written by the protocol stack. If you are going to use - * this function you might use the functions xMBUtilSetBits( ) and - * xMBUtilGetBits( ) for working with bitfields. - * - * \param pucRegBuffer The bits are packed in bytes where the first coil - * starting at address \c usAddress is stored in the LSB of the - * first byte in the buffer pucRegBuffer. - * If the buffer should be written by the callback function unused - * coil values (I.e. if not a multiple of eight coils is used) should be set - * to zero. - * \param usAddress The first coil number. - * \param usNCoils Number of coil values requested. - * \param eMode If eMBRegisterMode::MB_REG_WRITE the application values should - * be updated from the values supplied in the buffer \c pucRegBuffer. - * If eMBRegisterMode::MB_REG_READ the application should store the current - * values in the buffer \c pucRegBuffer. - * - * \return The function must return one of the following error codes: - * - eMBErrorCode::MB_ENOERR If no error occurred. In this case a normal - * Modbus response is sent. - * - eMBErrorCode::MB_ENOREG If the application does not map an coils - * within the requested address range. In this case a - * ILLEGAL DATA ADDRESS is sent as a response. - * - eMBErrorCode::MB_ETIMEDOUT If the requested register block is - * currently not available and the application dependent response - * timeout would be violated. In this case a SLAVE DEVICE BUSY - * exception is sent as a response. - * - eMBErrorCode::MB_EIO If an unrecoverable error occurred. In this case - * a SLAVE DEVICE FAILURE exception is sent as a response. - */ -eMBErrorCode eMBRegCoilsCB( UCHAR * pucRegBuffer, USHORT usAddress, - USHORT usNCoils, eMBRegisterMode eMode ); - -/*! \ingroup modbus_registers - * \brief Callback function used if a Input Discrete Register value is - * read by the protocol stack. - * - * If you are going to use his function you might use the functions - * xMBUtilSetBits( ) and xMBUtilGetBits( ) for working with bitfields. - * - * \param pucRegBuffer The buffer should be updated with the current - * coil values. The first discrete input starting at \c usAddress must be - * stored at the LSB of the first byte in the buffer. If the requested number - * is not a multiple of eight the remaining bits should be set to zero. - * \param usAddress The starting address of the first discrete input. - * \param usNDiscrete Number of discrete input values. - * \return The function must return one of the following error codes: - * - eMBErrorCode::MB_ENOERR If no error occurred. In this case a normal - * Modbus response is sent. - * - eMBErrorCode::MB_ENOREG If no such discrete inputs exists. - * In this case a ILLEGAL DATA ADDRESS exception frame is sent - * as a response. - * - eMBErrorCode::MB_ETIMEDOUT If the requested register block is - * currently not available and the application dependent response - * timeout would be violated. In this case a SLAVE DEVICE BUSY - * exception is sent as a response. - * - eMBErrorCode::MB_EIO If an unrecoverable error occurred. In this case - * a SLAVE DEVICE FAILURE exception is sent as a response. - */ -eMBErrorCode eMBRegDiscreteCB( UCHAR * pucRegBuffer, USHORT usAddress, - USHORT usNDiscrete ); - -#ifdef __cplusplus -PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbconfig.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbconfig.h deleted file mode 100644 index 02615cb68..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbconfig.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _MB_CONFIG_H -#define _MB_CONFIG_H - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif -/* ----------------------- Defines ------------------------------------------*/ -/*! \defgroup modbus_cfg Modbus Configuration - * - * Most modules in the protocol stack are completly optional and can be - * excluded. This is specially important if target resources are very small - * and program memory space should be saved.
- * - * All of these settings are available in the file mbconfig.h - */ -/*! \addtogroup modbus_cfg - * @{ - */ -/*! \brief If Modbus ASCII support is enabled. */ -#define MB_ASCII_ENABLED ( 1 ) - -/*! \brief If Modbus RTU support is enabled. */ -#define MB_RTU_ENABLED ( 1 ) - -/*! \brief If Modbus TCP support is enabled. */ -#define MB_TCP_ENABLED ( 0 ) - -/*! \brief The character timeout value for Modbus ASCII. - * - * The character timeout value is not fixed for Modbus ASCII and is therefore - * a configuration option. It should be set to the maximum expected delay - * time of the network. - */ -#define MB_ASCII_TIMEOUT_SEC ( 1 ) - -/*! \brief Timeout to wait in ASCII prior to enabling transmitter. - * - * If defined the function calls vMBPortSerialDelay with the argument - * MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS to allow for a delay before - * the serial transmitter is enabled. This is required because some - * targets are so fast that there is no time between receiving and - * transmitting the frame. If the master is to slow with enabling its - * receiver then he will not receive the response correctly. - */ -#ifndef MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS -#define MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS ( 0 ) -#endif - -/*! \brief Maximum number of Modbus functions codes the protocol stack - * should support. - * - * The maximum number of supported Modbus functions must be greater than - * the sum of all enabled functions in this file and custom function - * handlers. If set to small adding more functions will fail. - */ -#define MB_FUNC_HANDLERS_MAX ( 16 ) - -/*! \brief Number of bytes which should be allocated for the Report Slave ID - * command. - * - * This number limits the maximum size of the additional segment in the - * report slave id function. See eMBSetSlaveID( ) for more information on - * how to set this value. It is only used if MB_FUNC_OTHER_REP_SLAVEID_ENABLED - * is set to 1. - */ -#define MB_FUNC_OTHER_REP_SLAVEID_BUF ( 32 ) - -/*! \brief If the Report Slave ID function should be enabled. */ -#define MB_FUNC_OTHER_REP_SLAVEID_ENABLED ( 1 ) - -/*! \brief If the Read Input Registers function should be enabled. */ -#define MB_FUNC_READ_INPUT_ENABLED ( 1 ) - -/*! \brief If the Read Holding Registers function should be enabled. */ -#define MB_FUNC_READ_HOLDING_ENABLED ( 1 ) - -/*! \brief If the Write Single Register function should be enabled. */ -#define MB_FUNC_WRITE_HOLDING_ENABLED ( 1 ) - -/*! \brief If the Write Multiple registers function should be enabled. */ -#define MB_FUNC_WRITE_MULTIPLE_HOLDING_ENABLED ( 1 ) - -/*! \brief If the Read Coils function should be enabled. */ -#define MB_FUNC_READ_COILS_ENABLED ( 1 ) - -/*! \brief If the Write Coils function should be enabled. */ -#define MB_FUNC_WRITE_COIL_ENABLED ( 1 ) - -/*! \brief If the Write Multiple Coils function should be enabled. */ -#define MB_FUNC_WRITE_MULTIPLE_COILS_ENABLED ( 1 ) - -/*! \brief If the Read Discrete Inputs function should be enabled. */ -#define MB_FUNC_READ_DISCRETE_INPUTS_ENABLED ( 1 ) - -/*! \brief If the Read/Write Multiple Registers function should be enabled. */ -#define MB_FUNC_READWRITE_HOLDING_ENABLED ( 1 ) - -/*! @} */ -#ifdef __cplusplus - PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbframe.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbframe.h deleted file mode 100644 index 69a76989a..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbframe.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _MB_FRAME_H -#define _MB_FRAME_H - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif - -/*! - * Constants which defines the format of a modbus frame. The example is - * shown for a Modbus RTU/ASCII frame. Note that the Modbus PDU is not - * dependent on the underlying transport. - * - * - * <------------------------ MODBUS SERIAL LINE PDU (1) -------------------> - * <----------- MODBUS PDU (1') ----------------> - * +-----------+---------------+----------------------------+-------------+ - * | Address | Function Code | Data | CRC/LRC | - * +-----------+---------------+----------------------------+-------------+ - * | | | | - * (2) (3/2') (3') (4) - * - * (1) ... MB_SER_PDU_SIZE_MAX = 256 - * (2) ... MB_SER_PDU_ADDR_OFF = 0 - * (3) ... MB_SER_PDU_PDU_OFF = 1 - * (4) ... MB_SER_PDU_SIZE_CRC = 2 - * - * (1') ... MB_PDU_SIZE_MAX = 253 - * (2') ... MB_PDU_FUNC_OFF = 0 - * (3') ... MB_PDU_DATA_OFF = 1 - * - */ - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_PDU_SIZE_MAX 253 /*!< Maximum size of a PDU. */ -#define MB_PDU_SIZE_MIN 1 /*!< Function Code */ -#define MB_PDU_FUNC_OFF 0 /*!< Offset of function code in PDU. */ -#define MB_PDU_DATA_OFF 1 /*!< Offset for response data in PDU. */ - -/* ----------------------- Prototypes 0-------------------------------------*/ -typedef void ( *pvMBFrameStart ) ( void ); - -typedef void ( *pvMBFrameStop ) ( void ); - -typedef eMBErrorCode( *peMBFrameReceive ) ( UCHAR * pucRcvAddress, - UCHAR ** pucFrame, - USHORT * pusLength ); - -typedef eMBErrorCode( *peMBFrameSend ) ( UCHAR slaveAddress, - const UCHAR * pucFrame, - USHORT usLength ); - -typedef void( *pvMBFrameClose ) ( void ); - -#ifdef __cplusplus -PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbfunc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbfunc.h deleted file mode 100644 index ccf54efe2..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbfunc.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _MB_FUNC_H -#define _MB_FUNC_H - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif -#if MB_FUNC_OTHER_REP_SLAVEID_BUF > 0 - eMBException eMBFuncReportSlaveID( UCHAR * pucFrame, USHORT * usLen ); -#endif - -#if MB_FUNC_READ_INPUT_ENABLED > 0 -eMBException eMBFuncReadInputRegister( UCHAR * pucFrame, USHORT * usLen ); -#endif - -#if MB_FUNC_READ_HOLDING_ENABLED > 0 -eMBException eMBFuncReadHoldingRegister( UCHAR * pucFrame, USHORT * usLen ); -#endif - -#if MB_FUNC_WRITE_HOLDING_ENABLED > 0 -eMBException eMBFuncWriteHoldingRegister( UCHAR * pucFrame, USHORT * usLen ); -#endif - -#if MB_FUNC_WRITE_MULTIPLE_HOLDING_ENABLED > 0 -eMBException eMBFuncWriteMultipleHoldingRegister( UCHAR * pucFrame, USHORT * usLen ); -#endif - -#if MB_FUNC_READ_COILS_ENABLED > 0 -eMBException eMBFuncReadCoils( UCHAR * pucFrame, USHORT * usLen ); -#endif - -#if MB_FUNC_WRITE_COIL_ENABLED > 0 -eMBException eMBFuncWriteCoil( UCHAR * pucFrame, USHORT * usLen ); -#endif - -#if MB_FUNC_WRITE_MULTIPLE_COILS_ENABLED > 0 -eMBException eMBFuncWriteMultipleCoils( UCHAR * pucFrame, USHORT * usLen ); -#endif - -#if MB_FUNC_READ_DISCRETE_INPUTS_ENABLED > 0 -eMBException eMBFuncReadDiscreteInputs( UCHAR * pucFrame, USHORT * usLen ); -#endif - -#if MB_FUNC_READWRITE_HOLDING_ENABLED > 0 -eMBException eMBFuncReadWriteMultipleHoldingRegister( UCHAR * pucFrame, USHORT * usLen ); -#endif - -#ifdef __cplusplus -PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbport.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbport.h deleted file mode 100644 index 3198f1be6..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbport.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _MB_PORT_H -#define _MB_PORT_H - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif - -/* ----------------------- Type definitions ---------------------------------*/ - -typedef enum -{ - EV_READY, /*!< Startup finished. */ - EV_FRAME_RECEIVED, /*!< Frame received. */ - EV_EXECUTE, /*!< Execute function. */ - EV_FRAME_SENT /*!< Frame sent. */ -} eMBEventType; - -/*! \ingroup modbus - * \brief Parity used for characters in serial mode. - * - * The parity which should be applied to the characters sent over the serial - * link. Please note that this values are actually passed to the porting - * layer and therefore not all parity modes might be available. - */ -typedef enum -{ - MB_PAR_NONE, /*!< No parity. */ - MB_PAR_ODD, /*!< Odd parity. */ - MB_PAR_EVEN /*!< Even parity. */ -} eMBParity; - -/* ----------------------- Supporting functions -----------------------------*/ -BOOL xMBPortEventInit( void ); - -BOOL xMBPortEventPost( eMBEventType eEvent ); - -BOOL xMBPortEventGet( /*@out@ */ eMBEventType * eEvent ); - -/* ----------------------- Serial port functions ----------------------------*/ - -BOOL xMBPortSerialInit( UCHAR ucPort, ULONG ulBaudRate, - UCHAR ucDataBits, eMBParity eParity ); - -void vMBPortClose( void ); - -void xMBPortSerialClose( void ); - -void vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable ); - -BOOL xMBPortSerialGetByte( CHAR * pucByte ); - -BOOL xMBPortSerialPutByte( CHAR ucByte ); - -/* ----------------------- Timers functions ---------------------------------*/ -BOOL xMBPortTimersInit( USHORT usTimeOut50us ); - -void xMBPortTimersClose( void ); - -void vMBPortTimersEnable( void ); - -void vMBPortTimersDisable( void ); - -void vMBPortTimersDelay( USHORT usTimeOutMS ); - -/* ----------------------- Callback for the protocol stack ------------------*/ - -/*! - * \brief Callback function for the porting layer when a new byte is - * available. - * - * Depending upon the mode this callback function is used by the RTU or - * ASCII transmission layers. In any case a call to xMBPortSerialGetByte() - * must immediately return a new character. - * - * \return TRUE if a event was posted to the queue because - * a new byte was received. The port implementation should wake up the - * tasks which are currently blocked on the eventqueue. - */ -extern BOOL( *pxMBFrameCBByteReceived ) ( void ); - -extern BOOL( *pxMBFrameCBTransmitterEmpty ) ( void ); - -extern BOOL( *pxMBPortCBTimerExpired ) ( void ); - -/* ----------------------- TCP port functions -------------------------------*/ -BOOL xMBTCPPortInit( USHORT usTCPPort ); - -void vMBTCPPortClose( void ); - -void vMBTCPPortDisable( void ); - -BOOL xMBTCPPortGetRequest( UCHAR **ppucMBTCPFrame, USHORT * usTCPLength ); - -BOOL xMBTCPPortSendResponse( const UCHAR *pucMBTCPFrame, USHORT usTCPLength ); - -#ifdef __cplusplus -PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbproto.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbproto.h deleted file mode 100644 index e2d14cf05..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbproto.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _MB_PROTO_H -#define _MB_PROTO_H - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif -/* ----------------------- Defines ------------------------------------------*/ -#define MB_ADDRESS_BROADCAST ( 0 ) /*! Modbus broadcast address. */ -#define MB_ADDRESS_MIN ( 1 ) /*! Smallest possible slave address. */ -#define MB_ADDRESS_MAX ( 247 ) /*! Biggest possible slave address. */ -#define MB_FUNC_NONE ( 0 ) -#define MB_FUNC_READ_COILS ( 1 ) -#define MB_FUNC_READ_DISCRETE_INPUTS ( 2 ) -#define MB_FUNC_WRITE_SINGLE_COIL ( 5 ) -#define MB_FUNC_WRITE_MULTIPLE_COILS ( 15 ) -#define MB_FUNC_READ_HOLDING_REGISTER ( 3 ) -#define MB_FUNC_READ_INPUT_REGISTER ( 4 ) -#define MB_FUNC_WRITE_REGISTER ( 6 ) -#define MB_FUNC_WRITE_MULTIPLE_REGISTERS ( 16 ) -#define MB_FUNC_READWRITE_MULTIPLE_REGISTERS ( 23 ) -#define MB_FUNC_DIAG_READ_EXCEPTION ( 7 ) -#define MB_FUNC_DIAG_DIAGNOSTIC ( 8 ) -#define MB_FUNC_DIAG_GET_COM_EVENT_CNT ( 11 ) -#define MB_FUNC_DIAG_GET_COM_EVENT_LOG ( 12 ) -#define MB_FUNC_OTHER_REPORT_SLAVEID ( 17 ) -#define MB_FUNC_ERROR ( 128 ) -/* ----------------------- Type definitions ---------------------------------*/ - typedef enum -{ - MB_EX_NONE = 0x00, - MB_EX_ILLEGAL_FUNCTION = 0x01, - MB_EX_ILLEGAL_DATA_ADDRESS = 0x02, - MB_EX_ILLEGAL_DATA_VALUE = 0x03, - MB_EX_SLAVE_DEVICE_FAILURE = 0x04, - MB_EX_ACKNOWLEDGE = 0x05, - MB_EX_SLAVE_BUSY = 0x06, - MB_EX_MEMORY_PARITY_ERROR = 0x08, - MB_EX_GATEWAY_PATH_FAILED = 0x0A, - MB_EX_GATEWAY_TGT_FAILED = 0x0B -} eMBException; - -typedef eMBException( *pxMBFunctionHandler ) ( UCHAR * pucFrame, USHORT * pusLength ); - -typedef struct -{ - UCHAR ucFunctionCode; - pxMBFunctionHandler pxHandler; -} xMBFunctionHandler; - -#ifdef __cplusplus -PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbutils.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbutils.h deleted file mode 100644 index 385b8c156..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/include/mbutils.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _MB_UTILS_H -#define _MB_UTILS_H - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif -/*! \defgroup modbus_utils Utilities - * - * This module contains some utility functions which can be used by - * the application. It includes some special functions for working with - * bitfields backed by a character array buffer. - * - */ -/*! \addtogroup modbus_utils - * @{ - */ -/*! \brief Function to set bits in a byte buffer. - * - * This function allows the efficient use of an array to implement bitfields. - * The array used for storing the bits must always be a multiple of two - * bytes. Up to eight bits can be set or cleared in one operation. - * - * \param ucByteBuf A buffer where the bit values are stored. Must be a - * multiple of 2 bytes. No length checking is performed and if - * usBitOffset / 8 is greater than the size of the buffer memory contents - * is overwritten. - * \param usBitOffset The starting address of the bits to set. The first - * bit has the offset 0. - * \param ucNBits Number of bits to modify. The value must always be smaller - * than 8. - * \param ucValues Thew new values for the bits. The value for the first bit - * starting at usBitOffset is the LSB of the value - * ucValues - * - * \code - * ucBits[2] = {0, 0}; - * - * // Set bit 4 to 1 (read: set 1 bit starting at bit offset 4 to value 1) - * xMBUtilSetBits( ucBits, 4, 1, 1 ); - * - * // Set bit 7 to 1 and bit 8 to 0. - * xMBUtilSetBits( ucBits, 7, 2, 0x01 ); - * - * // Set bits 8 - 11 to 0x05 and bits 12 - 15 to 0x0A; - * xMBUtilSetBits( ucBits, 8, 8, 0x5A); - * \endcode - */ -void xMBUtilSetBits( UCHAR * ucByteBuf, USHORT usBitOffset, - UCHAR ucNBits, UCHAR ucValues ); - -/*! \brief Function to read bits in a byte buffer. - * - * This function is used to extract up bit values from an array. Up to eight - * bit values can be extracted in one step. - * - * \param ucByteBuf A buffer where the bit values are stored. - * \param usBitOffset The starting address of the bits to set. The first - * bit has the offset 0. - * \param ucNBits Number of bits to modify. The value must always be smaller - * than 8. - * - * \code - * UCHAR ucBits[2] = {0, 0}; - * UCHAR ucResult; - * - * // Extract the bits 3 - 10. - * ucResult = xMBUtilGetBits( ucBits, 3, 8 ); - * \endcode - */ -UCHAR xMBUtilGetBits( UCHAR * ucByteBuf, USHORT usBitOffset, - UCHAR ucNBits ); - -/*! @} */ - -#ifdef __cplusplus -PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/mb.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/mb.c deleted file mode 100644 index 0c4264fbe..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/mb.c +++ /dev/null @@ -1,411 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "stdlib.h" -#include "string.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "mod_port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbconfig.h" -#include "mbframe.h" -#include "mbproto.h" -#include "mbfunc.h" - -#include "mbport.h" -#if MB_RTU_ENABLED == 1 -#include "mbrtu.h" -#endif -#if MB_ASCII_ENABLED == 1 -#include "mbascii.h" -#endif -#if MB_TCP_ENABLED == 1 -#include "mbtcp.h" -#endif - -#ifndef MB_PORT_HAS_CLOSE -#define MB_PORT_HAS_CLOSE 0 -#endif - -/* ----------------------- Static variables ---------------------------------*/ - -static UCHAR ucMBAddress; -static eMBMode eMBCurrentMode; - -static enum -{ - STATE_ENABLED, - STATE_DISABLED, - STATE_NOT_INITIALIZED -} eMBState = STATE_NOT_INITIALIZED; - -/* Functions pointer which are initialized in eMBInit( ). Depending on the - * mode (RTU or ASCII) the are set to the correct implementations. - */ -static peMBFrameSend peMBFrameSendCur; -static pvMBFrameStart pvMBFrameStartCur; -static pvMBFrameStop pvMBFrameStopCur; -static peMBFrameReceive peMBFrameReceiveCur; -static pvMBFrameClose pvMBFrameCloseCur; - -/* Callback functions required by the porting layer. They are called when - * an external event has happend which includes a timeout or the reception - * or transmission of a character. - */ -BOOL( *pxMBFrameCBByteReceived ) ( void ); -BOOL( *pxMBFrameCBTransmitterEmpty ) ( void ); -BOOL( *pxMBPortCBTimerExpired ) ( void ); - -BOOL( *pxMBFrameCBReceiveFSMCur ) ( void ); -BOOL( *pxMBFrameCBTransmitFSMCur ) ( void ); - -/* An array of Modbus functions handlers which associates Modbus function - * codes with implementing functions. - */ -static xMBFunctionHandler xFuncHandlers[MB_FUNC_HANDLERS_MAX] = { -#if MB_FUNC_OTHER_REP_SLAVEID_ENABLED > 0 - {MB_FUNC_OTHER_REPORT_SLAVEID, eMBFuncReportSlaveID}, -#endif -#if MB_FUNC_READ_INPUT_ENABLED > 0 - {MB_FUNC_READ_INPUT_REGISTER, eMBFuncReadInputRegister}, -#endif -#if MB_FUNC_READ_HOLDING_ENABLED > 0 - {MB_FUNC_READ_HOLDING_REGISTER, eMBFuncReadHoldingRegister}, -#endif -#if MB_FUNC_WRITE_MULTIPLE_HOLDING_ENABLED > 0 - {MB_FUNC_WRITE_MULTIPLE_REGISTERS, eMBFuncWriteMultipleHoldingRegister}, -#endif -#if MB_FUNC_WRITE_HOLDING_ENABLED > 0 - {MB_FUNC_WRITE_REGISTER, eMBFuncWriteHoldingRegister}, -#endif -#if MB_FUNC_READWRITE_HOLDING_ENABLED > 0 - {MB_FUNC_READWRITE_MULTIPLE_REGISTERS, eMBFuncReadWriteMultipleHoldingRegister}, -#endif -#if MB_FUNC_READ_COILS_ENABLED > 0 - {MB_FUNC_READ_COILS, eMBFuncReadCoils}, -#endif -#if MB_FUNC_WRITE_COIL_ENABLED > 0 - {MB_FUNC_WRITE_SINGLE_COIL, eMBFuncWriteCoil}, -#endif -#if MB_FUNC_WRITE_MULTIPLE_COILS_ENABLED > 0 - {MB_FUNC_WRITE_MULTIPLE_COILS, eMBFuncWriteMultipleCoils}, -#endif -#if MB_FUNC_READ_DISCRETE_INPUTS_ENABLED > 0 - {MB_FUNC_READ_DISCRETE_INPUTS, eMBFuncReadDiscreteInputs}, -#endif -}; - -/* ----------------------- Start implementation -----------------------------*/ -eMBErrorCode -eMBInit( eMBMode eMode, UCHAR ucSlaveAddress, UCHAR ucPort, ULONG ulBaudRate, eMBParity eParity ) -{ - eMBErrorCode eStatus = MB_ENOERR; - - /* check preconditions */ - if( ( ucSlaveAddress == MB_ADDRESS_BROADCAST ) || - ( ucSlaveAddress < MB_ADDRESS_MIN ) || ( ucSlaveAddress > MB_ADDRESS_MAX ) ) - { - eStatus = MB_EINVAL; - } - else - { - ucMBAddress = ucSlaveAddress; - - switch ( eMode ) - { -#if MB_RTU_ENABLED > 0 - case MB_RTU: - pvMBFrameStartCur = eMBRTUStart; - pvMBFrameStopCur = eMBRTUStop; - peMBFrameSendCur = eMBRTUSend; - peMBFrameReceiveCur = eMBRTUReceive; - pvMBFrameCloseCur = MB_PORT_HAS_CLOSE ? vMBPortClose : NULL; - pxMBFrameCBByteReceived = xMBRTUReceiveFSM; - pxMBFrameCBTransmitterEmpty = xMBRTUTransmitFSM; - pxMBPortCBTimerExpired = xMBRTUTimerT35Expired; - - eStatus = eMBRTUInit( ucMBAddress, ucPort, ulBaudRate, eParity ); - break; -#endif -#if MB_ASCII_ENABLED > 0 - case MB_ASCII: - pvMBFrameStartCur = eMBASCIIStart; - pvMBFrameStopCur = eMBASCIIStop; - peMBFrameSendCur = eMBASCIISend; - peMBFrameReceiveCur = eMBASCIIReceive; - pvMBFrameCloseCur = MB_PORT_HAS_CLOSE ? vMBPortClose : NULL; - pxMBFrameCBByteReceived = xMBASCIIReceiveFSM; - pxMBFrameCBTransmitterEmpty = xMBASCIITransmitFSM; - pxMBPortCBTimerExpired = xMBASCIITimerT1SExpired; - - eStatus = eMBASCIIInit( ucMBAddress, ucPort, ulBaudRate, eParity ); - break; -#endif - default: - eStatus = MB_EINVAL; - } - - if( eStatus == MB_ENOERR ) - { - if( !xMBPortEventInit( ) ) - { - /* port dependent event module initalization failed. */ - eStatus = MB_EPORTERR; - } - else - { - eMBCurrentMode = eMode; - eMBState = STATE_DISABLED; - } - } - } - return eStatus; -} - -#if MB_TCP_ENABLED > 0 -eMBErrorCode -eMBTCPInit( USHORT ucTCPPort ) -{ - eMBErrorCode eStatus = MB_ENOERR; - - if( ( eStatus = eMBTCPDoInit( ucTCPPort ) ) != MB_ENOERR ) - { - eMBState = STATE_DISABLED; - } - else if( !xMBPortEventInit( ) ) - { - /* Port dependent event module initalization failed. */ - eStatus = MB_EPORTERR; - } - else - { - pvMBFrameStartCur = eMBTCPStart; - pvMBFrameStopCur = eMBTCPStop; - peMBFrameReceiveCur = eMBTCPReceive; - peMBFrameSendCur = eMBTCPSend; - pvMBFrameCloseCur = MB_PORT_HAS_CLOSE ? vMBTCPPortClose : NULL; - ucMBAddress = MB_TCP_PSEUDO_ADDRESS; - eMBCurrentMode = MB_TCP; - eMBState = STATE_DISABLED; - } - return eStatus; -} -#endif - -eMBErrorCode -eMBRegisterCB( UCHAR ucFunctionCode, pxMBFunctionHandler pxHandler ) -{ - int i; - eMBErrorCode eStatus; - - if( ( 0 < ucFunctionCode ) && ( ucFunctionCode <= 127 ) ) - { - ENTER_CRITICAL_SECTION( ); - if( pxHandler != NULL ) - { - for( i = 0; i < MB_FUNC_HANDLERS_MAX; i++ ) - { - if( ( xFuncHandlers[i].pxHandler == NULL ) || - ( xFuncHandlers[i].pxHandler == pxHandler ) ) - { - xFuncHandlers[i].ucFunctionCode = ucFunctionCode; - xFuncHandlers[i].pxHandler = pxHandler; - break; - } - } - eStatus = ( i != MB_FUNC_HANDLERS_MAX ) ? MB_ENOERR : MB_ENORES; - } - else - { - for( i = 0; i < MB_FUNC_HANDLERS_MAX; i++ ) - { - if( xFuncHandlers[i].ucFunctionCode == ucFunctionCode ) - { - xFuncHandlers[i].ucFunctionCode = 0; - xFuncHandlers[i].pxHandler = NULL; - break; - } - } - /* Remove can't fail. */ - eStatus = MB_ENOERR; - } - EXIT_CRITICAL_SECTION( ); - } - else - { - eStatus = MB_EINVAL; - } - return eStatus; -} - - -eMBErrorCode -eMBClose( void ) -{ - eMBErrorCode eStatus = MB_ENOERR; - - if( eMBState == STATE_DISABLED ) - { - if( pvMBFrameCloseCur != NULL ) - { - pvMBFrameCloseCur( ); - } - } - else - { - eStatus = MB_EILLSTATE; - } - return eStatus; -} - -eMBErrorCode -eMBEnable( void ) -{ - eMBErrorCode eStatus = MB_ENOERR; - - if( eMBState == STATE_DISABLED ) - { - /* Activate the protocol stack. */ - pvMBFrameStartCur( ); - eMBState = STATE_ENABLED; - } - else - { - eStatus = MB_EILLSTATE; - } - return eStatus; -} - -eMBErrorCode -eMBDisable( void ) -{ - eMBErrorCode eStatus; - - if( eMBState == STATE_ENABLED ) - { - pvMBFrameStopCur( ); - eMBState = STATE_DISABLED; - eStatus = MB_ENOERR; - } - else if( eMBState == STATE_DISABLED ) - { - eStatus = MB_ENOERR; - } - else - { - eStatus = MB_EILLSTATE; - } - return eStatus; -} - -eMBErrorCode -eMBPoll( void ) -{ - static UCHAR *ucMBFrame; - static UCHAR ucRcvAddress; - static UCHAR ucFunctionCode; - static USHORT usLength; - static eMBException eException; - - int i; - eMBErrorCode eStatus = MB_ENOERR; - eMBEventType eEvent; - - /* Check if the protocol stack is ready. */ - if( eMBState != STATE_ENABLED ) - { - return MB_EILLSTATE; - } - - /* Check if there is a event available. If not return control to caller. - * Otherwise we will handle the event. */ - if( xMBPortEventGet( &eEvent ) == TRUE ) - { - switch ( eEvent ) - { - case EV_READY: - break; - - case EV_FRAME_RECEIVED: - eStatus = peMBFrameReceiveCur( &ucRcvAddress, &ucMBFrame, &usLength ); - if( eStatus == MB_ENOERR ) - { - /* Check if the frame is for us. If not ignore the frame. */ - if( ( ucRcvAddress == ucMBAddress ) || ( ucRcvAddress == MB_ADDRESS_BROADCAST ) ) - { - ( void )xMBPortEventPost( EV_EXECUTE ); - } - } - break; - - case EV_EXECUTE: - ucFunctionCode = ucMBFrame[MB_PDU_FUNC_OFF]; - eException = MB_EX_ILLEGAL_FUNCTION; - for( i = 0; i < MB_FUNC_HANDLERS_MAX; i++ ) - { - /* No more function handlers registered. Abort. */ - if( xFuncHandlers[i].ucFunctionCode == 0 ) - { - break; - } - else if( xFuncHandlers[i].ucFunctionCode == ucFunctionCode ) - { - eException = xFuncHandlers[i].pxHandler( ucMBFrame, &usLength ); - break; - } - } - - /* If the request was not sent to the broadcast address we - * return a reply. */ - if( ucRcvAddress != MB_ADDRESS_BROADCAST ) - { - if( eException != MB_EX_NONE ) - { - /* An exception occured. Build an error frame. */ - usLength = 0; - ucMBFrame[usLength++] = ( UCHAR )( ucFunctionCode | MB_FUNC_ERROR ); - ucMBFrame[usLength++] = eException; - } - if( ( eMBCurrentMode == MB_ASCII ) && MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS ) - { - vMBPortTimersDelay( MB_ASCII_TIMEOUT_WAIT_BEFORE_SEND_MS ); - } - eStatus = peMBFrameSendCur( ucMBAddress, ucMBFrame, usLength ); - } - break; - - case EV_FRAME_SENT: - break; - } - } - return MB_ENOERR; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/rtu/mbcrc.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/rtu/mbcrc.c deleted file mode 100644 index 5f084d712..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/rtu/mbcrc.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/* ----------------------- Platform includes --------------------------------*/ -#include "mod_port.h" - -static const UCHAR aucCRCHi[] = { - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, - 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, - 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, - 0x00, 0xC1, 0x81, 0x40 -}; - -static const UCHAR aucCRCLo[] = { - 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7, - 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E, - 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9, - 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC, - 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3, - 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32, - 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D, - 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38, - 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF, - 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26, - 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1, - 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4, - 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB, - 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA, - 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5, - 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0, - 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97, - 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E, - 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89, - 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C, - 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83, - 0x41, 0x81, 0x80, 0x40 -}; - -USHORT -usMBCRC16( UCHAR * pucFrame, USHORT usLen ) -{ - UCHAR ucCRCHi = 0xFF; - UCHAR ucCRCLo = 0xFF; - int iIndex; - - while( usLen-- ) - { - iIndex = ucCRCLo ^ *( pucFrame++ ); - ucCRCLo = ( UCHAR )( ucCRCHi ^ aucCRCHi[iIndex] ); - ucCRCHi = aucCRCLo[iIndex]; - } - return ( USHORT )( ucCRCHi << 8 | ucCRCLo ); -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/rtu/mbcrc.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/rtu/mbcrc.h deleted file mode 100644 index b182e69d3..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/rtu/mbcrc.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _MB_CRC_H -#define _MB_CRC_H - -USHORT usMBCRC16( UCHAR * pucFrame, USHORT usLen ); - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/rtu/mbrtu.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/rtu/mbrtu.c deleted file mode 100644 index 3d04252df..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/rtu/mbrtu.c +++ /dev/null @@ -1,354 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "stdlib.h" -#include "string.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "mod_port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbrtu.h" -#include "mbframe.h" - -#include "mbcrc.h" -#include "mbport.h" - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_SER_PDU_SIZE_MIN 4 /*!< Minimum size of a Modbus RTU frame. */ -#define MB_SER_PDU_SIZE_MAX 256 /*!< Maximum size of a Modbus RTU frame. */ -#define MB_SER_PDU_SIZE_CRC 2 /*!< Size of CRC field in PDU. */ -#define MB_SER_PDU_ADDR_OFF 0 /*!< Offset of slave address in Ser-PDU. */ -#define MB_SER_PDU_PDU_OFF 1 /*!< Offset of Modbus-PDU in Ser-PDU. */ - -/* ----------------------- Type definitions ---------------------------------*/ -typedef enum -{ - STATE_RX_INIT, /*!< Receiver is in initial state. */ - STATE_RX_IDLE, /*!< Receiver is in idle state. */ - STATE_RX_RCV, /*!< Frame is beeing received. */ - STATE_RX_ERROR /*!< If the frame is invalid. */ -} eMBRcvState; - -typedef enum -{ - STATE_TX_IDLE, /*!< Transmitter is in idle state. */ - STATE_TX_XMIT /*!< Transmitter is in transfer state. */ -} eMBSndState; - -/* ----------------------- Static variables ---------------------------------*/ -static volatile eMBSndState eSndState; -static volatile eMBRcvState eRcvState; - -volatile UCHAR ucRTUBuf[MB_SER_PDU_SIZE_MAX]; - -static volatile UCHAR *pucSndBufferCur; -static volatile USHORT usSndBufferCount; - -static volatile USHORT usRcvBufferPos; - -/* ----------------------- Start implementation -----------------------------*/ -eMBErrorCode -eMBRTUInit( UCHAR ucSlaveAddress, UCHAR ucPort, ULONG ulBaudRate, eMBParity eParity ) -{ - eMBErrorCode eStatus = MB_ENOERR; - ULONG usTimerT35_50us; - - ( void )ucSlaveAddress; - ENTER_CRITICAL_SECTION( ); - - /* Modbus RTU uses 8 Databits. */ - if( xMBPortSerialInit( ucPort, ulBaudRate, 8, eParity ) != TRUE ) - { - eStatus = MB_EPORTERR; - } - else - { - /* If baudrate > 19200 then we should use the fixed timer values - * t35 = 1750us. Otherwise t35 must be 3.5 times the character time. - */ - if( ulBaudRate > 19200 ) - { - usTimerT35_50us = 35; /* 1800us. */ - } - else - { - /* The timer reload value for a character is given by: - * - * ChTimeValue = Ticks_per_1s / ( Baudrate / 11 ) - * = 11 * Ticks_per_1s / Baudrate - * = 220000 / Baudrate - * The reload for t3.5 is 1.5 times this value and similary - * for t3.5. - */ - usTimerT35_50us = ( 7UL * 220000UL ) / ( 2UL * ulBaudRate ); - } - if( xMBPortTimersInit( ( USHORT ) usTimerT35_50us ) != TRUE ) - { - eStatus = MB_EPORTERR; - } - } - EXIT_CRITICAL_SECTION( ); - - return eStatus; -} - -void -eMBRTUStart( void ) -{ - ENTER_CRITICAL_SECTION( ); - /* Initially the receiver is in the state STATE_RX_INIT. we start - * the timer and if no character is received within t3.5 we change - * to STATE_RX_IDLE. This makes sure that we delay startup of the - * modbus protocol stack until the bus is free. - */ - eRcvState = STATE_RX_INIT; - vMBPortSerialEnable( TRUE, FALSE ); - vMBPortTimersEnable( ); - - EXIT_CRITICAL_SECTION( ); -} - -void -eMBRTUStop( void ) -{ - ENTER_CRITICAL_SECTION( ); - vMBPortSerialEnable( FALSE, FALSE ); - vMBPortTimersDisable( ); - EXIT_CRITICAL_SECTION( ); -} - -eMBErrorCode -eMBRTUReceive( UCHAR * pucRcvAddress, UCHAR ** pucFrame, USHORT * pusLength ) -{ - BOOL xFrameReceived = FALSE; - eMBErrorCode eStatus = MB_ENOERR; - - ENTER_CRITICAL_SECTION( ); - assert( usRcvBufferPos < MB_SER_PDU_SIZE_MAX ); - - /* Length and CRC check */ - if( ( usRcvBufferPos >= MB_SER_PDU_SIZE_MIN ) - && ( usMBCRC16( ( UCHAR * ) ucRTUBuf, usRcvBufferPos ) == 0 ) ) - { - /* Save the address field. All frames are passed to the upper layed - * and the decision if a frame is used is done there. - */ - *pucRcvAddress = ucRTUBuf[MB_SER_PDU_ADDR_OFF]; - - /* Total length of Modbus-PDU is Modbus-Serial-Line-PDU minus - * size of address field and CRC checksum. - */ - *pusLength = ( USHORT )( usRcvBufferPos - MB_SER_PDU_PDU_OFF - MB_SER_PDU_SIZE_CRC ); - - /* Return the start of the Modbus PDU to the caller. */ - *pucFrame = ( UCHAR * ) & ucRTUBuf[MB_SER_PDU_PDU_OFF]; - xFrameReceived = TRUE; - } - else - { - eStatus = MB_EIO; - } - - EXIT_CRITICAL_SECTION( ); - return eStatus; -} - -eMBErrorCode -eMBRTUSend( UCHAR ucSlaveAddress, const UCHAR * pucFrame, USHORT usLength ) -{ - eMBErrorCode eStatus = MB_ENOERR; - USHORT usCRC16; - - ENTER_CRITICAL_SECTION( ); - - /* Check if the receiver is still in idle state. If not we where to - * slow with processing the received frame and the master sent another - * frame on the network. We have to abort sending the frame. - */ - if( eRcvState == STATE_RX_IDLE ) - { - /* First byte before the Modbus-PDU is the slave address. */ - pucSndBufferCur = ( UCHAR * ) pucFrame - 1; - usSndBufferCount = 1; - - /* Now copy the Modbus-PDU into the Modbus-Serial-Line-PDU. */ - pucSndBufferCur[MB_SER_PDU_ADDR_OFF] = ucSlaveAddress; - usSndBufferCount += usLength; - - /* Calculate CRC16 checksum for Modbus-Serial-Line-PDU. */ - usCRC16 = usMBCRC16( ( UCHAR * ) pucSndBufferCur, usSndBufferCount ); - ucRTUBuf[usSndBufferCount++] = ( UCHAR )( usCRC16 & 0xFF ); - ucRTUBuf[usSndBufferCount++] = ( UCHAR )( usCRC16 >> 8 ); - - /* Activate the transmitter. */ - eSndState = STATE_TX_XMIT; - vMBPortSerialEnable( FALSE, TRUE ); - } - else - { - eStatus = MB_EIO; - } - EXIT_CRITICAL_SECTION( ); - return eStatus; -} - -BOOL -xMBRTUReceiveFSM( void ) -{ - BOOL xTaskNeedSwitch = FALSE; - UCHAR ucByte; - - assert( eSndState == STATE_TX_IDLE ); - - /* Always read the character. */ - ( void )xMBPortSerialGetByte( ( CHAR * ) & ucByte ); - - switch ( eRcvState ) - { - /* If we have received a character in the init state we have to - * wait until the frame is finished. - */ - case STATE_RX_INIT: - vMBPortTimersEnable( ); - break; - - /* In the error state we wait until all characters in the - * damaged frame are transmitted. - */ - case STATE_RX_ERROR: - vMBPortTimersEnable( ); - break; - - /* In the idle state we wait for a new character. If a character - * is received the t1.5 and t3.5 timers are started and the - * receiver is in the state STATE_RX_RECEIVCE. - */ - case STATE_RX_IDLE: - usRcvBufferPos = 0; - ucRTUBuf[usRcvBufferPos++] = ucByte; - eRcvState = STATE_RX_RCV; - - /* Enable t3.5 timers. */ - vMBPortTimersEnable( ); - break; - - /* We are currently receiving a frame. Reset the timer after - * every character received. If more than the maximum possible - * number of bytes in a modbus frame is received the frame is - * ignored. - */ - case STATE_RX_RCV: - if( usRcvBufferPos < MB_SER_PDU_SIZE_MAX ) - { - ucRTUBuf[usRcvBufferPos++] = ucByte; - } - else - { - eRcvState = STATE_RX_ERROR; - } - vMBPortTimersEnable( ); - break; - } - return xTaskNeedSwitch; -} - -BOOL -xMBRTUTransmitFSM( void ) -{ - BOOL xNeedPoll = FALSE; - - assert( eRcvState == STATE_RX_IDLE ); - - switch ( eSndState ) - { - /* We should not get a transmitter event if the transmitter is in - * idle state. */ - case STATE_TX_IDLE: - /* enable receiver/disable transmitter. */ - vMBPortSerialEnable( TRUE, FALSE ); - break; - - case STATE_TX_XMIT: - /* check if we are finished. */ - if( usSndBufferCount != 0 ) - { - xMBPortSerialPutByte( ( CHAR )*pucSndBufferCur ); - pucSndBufferCur++; /* next byte in sendbuffer. */ - usSndBufferCount--; - } - else - { - xNeedPoll = xMBPortEventPost( EV_FRAME_SENT ); - /* Disable transmitter. This prevents another transmit buffer - * empty interrupt. */ - vMBPortSerialEnable( TRUE, FALSE ); - eSndState = STATE_TX_IDLE; - } - break; - } - - return xNeedPoll; -} - -BOOL -xMBRTUTimerT35Expired( void ) -{ - BOOL xNeedPoll = FALSE; - - switch ( eRcvState ) - { - /* Timer t35 expired. Startup phase is finished. */ - case STATE_RX_INIT: - xNeedPoll = xMBPortEventPost( EV_READY ); - break; - - /* A frame was received and t35 expired. Notify the listener that - * a new frame was received. */ - case STATE_RX_RCV: - xNeedPoll = xMBPortEventPost( EV_FRAME_RECEIVED ); - break; - - /* An error occured while receiving the frame. */ - case STATE_RX_ERROR: - break; - - /* Function called in an illegal state. */ - default: - assert( ( eRcvState == STATE_RX_INIT ) || - ( eRcvState == STATE_RX_RCV ) || ( eRcvState == STATE_RX_ERROR ) ); - } - - vMBPortTimersDisable( ); - eRcvState = STATE_RX_IDLE; - - return xNeedPoll; -} diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/rtu/mbrtu.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/rtu/mbrtu.h deleted file mode 100644 index 698168712..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/rtu/mbrtu.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _MB_RTU_H -#define _MB_RTU_H - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif - eMBErrorCode eMBRTUInit( UCHAR slaveAddress, UCHAR ucPort, ULONG ulBaudRate, - eMBParity eParity ); -void eMBRTUStart( void ); -void eMBRTUStop( void ); -eMBErrorCode eMBRTUReceive( UCHAR * pucRcvAddress, UCHAR ** pucFrame, USHORT * pusLength ); -eMBErrorCode eMBRTUSend( UCHAR slaveAddress, const UCHAR * pucFrame, USHORT usLength ); -BOOL xMBRTUReceiveFSM( void ); -BOOL xMBRTUTransmitFSM( void ); -BOOL xMBRTUTimerT15Expired( void ); -BOOL xMBRTUTimerT35Expired( void ); - -#ifdef __cplusplus -PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/tcp/mbtcp.c b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/tcp/mbtcp.c deleted file mode 100644 index b9da0646e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/tcp/mbtcp.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/* ----------------------- System includes ----------------------------------*/ -#include "stdlib.h" -#include "string.h" - -/* ----------------------- Platform includes --------------------------------*/ -#include "mod_port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbconfig.h" -#include "mbtcp.h" -#include "mbframe.h" -#include "mbport.h" - -#if MB_TCP_ENABLED > 0 - -/* ----------------------- Defines ------------------------------------------*/ - -/* ----------------------- MBAP Header --------------------------------------*/ -/* - * - * <------------------------ MODBUS TCP/IP ADU(1) -------------------------> - * <----------- MODBUS PDU (1') ----------------> - * +-----------+---------------+------------------------------------------+ - * | TID | PID | Length | UID |Code | Data | - * +-----------+---------------+------------------------------------------+ - * | | | | | - * (2) (3) (4) (5) (6) - * - * (2) ... MB_TCP_TID = 0 (Transaction Identifier - 2 Byte) - * (3) ... MB_TCP_PID = 2 (Protocol Identifier - 2 Byte) - * (4) ... MB_TCP_LEN = 4 (Number of bytes - 2 Byte) - * (5) ... MB_TCP_UID = 6 (Unit Identifier - 1 Byte) - * (6) ... MB_TCP_FUNC = 7 (Modbus Function Code) - * - * (1) ... Modbus TCP/IP Application Data Unit - * (1') ... Modbus Protocol Data Unit - */ - -#define MB_TCP_TID 0 -#define MB_TCP_PID 2 -#define MB_TCP_LEN 4 -#define MB_TCP_UID 6 -#define MB_TCP_FUNC 7 - -#define MB_TCP_PROTOCOL_ID 0 /* 0 = Modbus Protocol */ - - -/* ----------------------- Start implementation -----------------------------*/ -eMBErrorCode -eMBTCPDoInit( USHORT ucTCPPort ) -{ - eMBErrorCode eStatus = MB_ENOERR; - - if( xMBTCPPortInit( ucTCPPort ) == FALSE ) - { - eStatus = MB_EPORTERR; - } - return eStatus; -} - -void -eMBTCPStart( void ) -{ -} - -void -eMBTCPStop( void ) -{ - /* Make sure that no more clients are connected. */ - vMBTCPPortDisable( ); -} - -eMBErrorCode -eMBTCPReceive( UCHAR * pucRcvAddress, UCHAR ** ppucFrame, USHORT * pusLength ) -{ - eMBErrorCode eStatus = MB_EIO; - UCHAR *pucMBTCPFrame; - USHORT usLength; - USHORT usPID; - - if( xMBTCPPortGetRequest( &pucMBTCPFrame, &usLength ) != FALSE ) - { - usPID = pucMBTCPFrame[MB_TCP_PID] << 8U; - usPID |= pucMBTCPFrame[MB_TCP_PID + 1]; - - if( usPID == MB_TCP_PROTOCOL_ID ) - { - *ppucFrame = &pucMBTCPFrame[MB_TCP_FUNC]; - *pusLength = usLength - MB_TCP_FUNC; - eStatus = MB_ENOERR; - - /* Modbus TCP does not use any addresses. Fake the source address such - * that the processing part deals with this frame. - */ - *pucRcvAddress = MB_TCP_PSEUDO_ADDRESS; - } - } - else - { - eStatus = MB_EIO; - } - return eStatus; -} - -eMBErrorCode -eMBTCPSend( UCHAR _unused, const UCHAR * pucFrame, USHORT usLength ) -{ - eMBErrorCode eStatus = MB_ENOERR; - UCHAR *pucMBTCPFrame = ( UCHAR * ) pucFrame - MB_TCP_FUNC; - USHORT usTCPLength = usLength + MB_TCP_FUNC; - - /* The MBAP header is already initialized because the caller calls this - * function with the buffer returned by the previous call. Therefore we - * only have to update the length in the header. Note that the length - * header includes the size of the Modbus PDU and the UID Byte. Therefore - * the length is usLength plus one. - */ - pucMBTCPFrame[MB_TCP_LEN] = ( usLength + 1 ) >> 8U; - pucMBTCPFrame[MB_TCP_LEN + 1] = ( usLength + 1 ) & 0xFF; - if( xMBTCPPortSendResponse( pucMBTCPFrame, usTCPLength ) == FALSE ) - { - eStatus = MB_EIO; - } - return eStatus; -} - -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/tcp/mbtcp.h b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/tcp/mbtcp.h deleted file mode 100644 index 16b651ee5..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/modbus/tcp/mbtcp.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * FreeModbus Libary: A portable Modbus implementation for Modbus ASCII/RTU. - * Copyright (c) 2006-2018 Christian Walter - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef _MB_TCP_H -#define _MB_TCP_H - -#ifdef __cplusplus -PR_BEGIN_EXTERN_C -#endif - -/* ----------------------- Defines ------------------------------------------*/ -#define MB_TCP_PSEUDO_ADDRESS 255 - -/* ----------------------- Function prototypes ------------------------------*/ - eMBErrorCode eMBTCPDoInit( USHORT ucTCPPort ); -void eMBTCPStart( void ); -void eMBTCPStop( void ); -eMBErrorCode eMBTCPReceive( UCHAR * pucRcvAddress, UCHAR ** pucFrame, - USHORT * pusLength ); -eMBErrorCode eMBTCPSend( UCHAR _unused, const UCHAR * pucFrame, - USHORT usLength ); - -#ifdef __cplusplus -PR_END_EXTERN_C -#endif -#endif diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/tools/README.txt b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/tools/README.txt deleted file mode 100644 index e37d1659e..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/tools/README.txt +++ /dev/null @@ -1,18 +0,0 @@ - -The tools have not been bundled because of license restrictions. I can -recommend the following tools to test the modbus implementation: - - - Modpoll Modbus Polling Tool: A free command line based Modbus - master simulator and test utility. - - available: http://www.focus-sw.com/fieldtalk/modpoll.html - - - Modbus Poll master simulator: A Modbus master simulator with a - excellent user interface. Support RTU and ASCII modes. - - available: http://www.modbustools.com/modbus_poll.asp - -Simple download the Modpoll Polling Tool and place it with the name -'modpoll.exe' in this directory. - - diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/tools/doxygen.exe b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/tools/doxygen.exe deleted file mode 100644 index 652614941..000000000 Binary files a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/tools/doxygen.exe and /dev/null differ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/tools/indent.sh b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/tools/indent.sh deleted file mode 100644 index 3a510a668..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/tools/indent.sh +++ /dev/null @@ -1,28 +0,0 @@ -#!/bin/sh - -MYDIR="/cygdrive/c/GnuWin32/bin/" - -$MYDIR/indent.exe --version -$MYDIR/indent.exe \ - --declaration-indentation16 \ - --procnames-start-lines \ - --blank-lines-after-procedures \ - --break-before-boolean-operator \ - --braces-after-if-line \ - --braces-after-struct-decl-line \ - --brace-indent0 \ - --case-indentation0 \ - --no-space-after-function-call-names \ - --no-space-after-for \ - --no-space-after-if \ - --no-space-after-while \ - --no-space-after-casts \ - --space-after-parentheses \ - --dont-format-comments \ - --indent-level4 \ - --ignore-newlines \ - --no-tabs \ - --line-length120 \ - $@ - -unix2dos $@ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/tools/lint-arm.sh b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/tools/lint-arm.sh deleted file mode 100644 index b54dd0b66..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/tools/lint-arm.sh +++ /dev/null @@ -1,5 +0,0 @@ -splint \ - -I. -I../../modbus/include -I../../modbus/rtu -I../../modbus/ascii \ - -Iport -Ilibrary/include \ - -Ifreertos/include -Ifreertos/portable/GCC/ARM7_STR71X/ \ - -DSTR71X_GCC=1 -nullpass +charint -booltype BOOL $@ diff --git a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/tools/lint-avr.sh b/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/tools/lint-avr.sh deleted file mode 100644 index 56c0cf7cf..000000000 --- a/components/connectivity/Modbus/3rdparty/freemodbus-v1.6/tools/lint-avr.sh +++ /dev/null @@ -1,4 +0,0 @@ -splint \ - -I. -I../../modbus/include -I../../modbus/rtu -I../../modbus/ascii \ - -Iport -I/cygdrive/c/WinAVR/avr/include \ - -nullpass +charint -booltype BOOL -D__AVR_ATmega168__=1 $@ diff --git a/components/connectivity/Modbus/Makefile b/components/connectivity/Modbus/Makefile deleted file mode 100644 index b524bbde4..000000000 --- a/components/connectivity/Modbus/Makefile +++ /dev/null @@ -1,42 +0,0 @@ -################################################################### -#automatic detection QTOP and LOCALDIR -CUR_DIR := $(patsubst %/,%,$(dir $(realpath $(firstword $(MAKEFILE_LIST))))) -TRYQTOP := $(shell if [ -n "$$QTOP" ] ; then\ - echo $$QTOP;\ - else\ - cd $(CUR_DIR); while /usr/bin/test ! -d qmk ; do \ - dir=`cd ../;pwd`; \ - if [ "$$dir" = "/" ] ; then \ - echo Cannot find QTOP in $(firstword $(MAKEFILE_LIST)) 1>&2; \ - exit 1; \ - fi ; \ - cd $$dir; \ - done ; \ - pwd; \ - fi) -QTOP ?= $(realpath ${TRYQTOP}) - -ifeq ($(QTOP),) -$(error Please run this in a tree) -endif -LOCALDIR = $(patsubst %/,%,$(subst $(realpath $(QTOP))/,,$(CUR_DIR))) - -#################################################################### - - -TREE_LIB_ENABLE=y -lib= -subdirs= - -CFGFLAGS += -std=c99 -CFGFLAGS += -I$(CUR_DIR)/porting/TencentOS_Tiny -CFGFLAGS += -I$(CUR_DIR)/3rdparty/freemodbus-v1.6/modbus/include -CFGFLAGS += -I$(CUR_DIR)/3rdparty/freemodbus-v1.6/modbus/rtu -CFGFLAGS += -I$(CUR_DIR)/3rdparty/freemodbus-v1.6/modbus/ascii - -LSRCS_DIRS += 3rdparty/freemodbus-v1.6/modbus - - -include ${QTOP}/qmk/generic/Make.tpl - - diff --git a/components/connectivity/Modbus/porting/TencentOS_Tiny/mod_port.h b/components/connectivity/Modbus/porting/TencentOS_Tiny/mod_port.h deleted file mode 100644 index 94348245c..000000000 --- a/components/connectivity/Modbus/porting/TencentOS_Tiny/mod_port.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * FreeModbus Libary: BARE Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#ifndef _MOD_PORT_H -#define _MOD_PORT_H - -#include -#include - -#define INLINE inline -#define PR_BEGIN_EXTERN_C extern "C" { -#define PR_END_EXTERN_C } - -#define ENTER_CRITICAL_SECTION( ) -#define EXIT_CRITICAL_SECTION( ) - -typedef uint8_t BOOL; - -typedef unsigned char UCHAR; -typedef char CHAR; - -typedef uint16_t USHORT; -typedef int16_t SHORT; - -typedef uint32_t ULONG; -typedef int32_t LONG; - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#endif diff --git a/components/connectivity/Modbus/porting/TencentOS_Tiny/portevent.c b/components/connectivity/Modbus/porting/TencentOS_Tiny/portevent.c deleted file mode 100644 index e700a471c..000000000 --- a/components/connectivity/Modbus/porting/TencentOS_Tiny/portevent.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * FreeModbus Libary: BARE Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- Variables ----------------------------------------*/ -static eMBEventType eQueuedEvent; -static BOOL xEventInQueue; - -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortEventInit( void ) -{ - xEventInQueue = FALSE; - return TRUE; -} - -BOOL -xMBPortEventPost( eMBEventType eEvent ) -{ - xEventInQueue = TRUE; - eQueuedEvent = eEvent; - return TRUE; -} - -BOOL -xMBPortEventGet( eMBEventType * eEvent ) -{ - BOOL xEventHappened = FALSE; - - if( xEventInQueue ) - { - *eEvent = eQueuedEvent; - xEventInQueue = FALSE; - xEventHappened = TRUE; - } - return xEventHappened; -} diff --git a/components/connectivity/Modbus/porting/TencentOS_Tiny/portserial.c b/components/connectivity/Modbus/porting/TencentOS_Tiny/portserial.c deleted file mode 100644 index df2722138..000000000 --- a/components/connectivity/Modbus/porting/TencentOS_Tiny/portserial.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * FreeModbus Libary: BARE Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -#include "mod_port.h" - -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" -#include "mcu_init.h" - -extern UART_HandleTypeDef huart2; -/* ----------------------- static functions ---------------------------------*/ -void prvvUARTTxReadyISR( void ); -void prvvUARTRxISR( void ); - -/* ----------------------- Start implementation -----------------------------*/ -void -vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable ) -{ - /* If xRXEnable enable serial receive interrupts. If xTxENable enable - * transmitter empty interrupts. - */ - if(xRxEnable == TRUE) - __HAL_UART_ENABLE_IT(&huart2, UART_IT_RXNE); - else - __HAL_UART_DISABLE_IT(&huart2, UART_IT_RXNE); - - if(xTxEnable == TRUE) - __HAL_UART_ENABLE_IT(&huart2, UART_IT_TXE); - else - __HAL_UART_DISABLE_IT(&huart2, UART_IT_TXE); -} - -BOOL -xMBPortSerialInit( UCHAR ucPORT, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity ) -{ - //HAL_UART_DeInit(&huart2); - (void)ucPORT; - huart2.Instance = USART2; - huart2.Init.BaudRate = ulBaudRate; - - - huart2.Init.StopBits = UART_STOPBITS_1; - switch (eParity) - { - case MB_PAR_ODD: - huart2.Init.WordLength = UART_WORDLENGTH_9B; - huart2.Init.Parity = UART_PARITY_ODD; - break; - case MB_PAR_EVEN: - huart2.Init.WordLength = UART_WORDLENGTH_9B; - huart2.Init.Parity = UART_PARITY_EVEN; - break; - default: - huart2.Init.WordLength = UART_WORDLENGTH_8B; - huart2.Init.Parity = UART_PARITY_NONE; - break; - } - - huart2.Init.Mode = UART_MODE_TX_RX; - huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart2.Init.OverSampling = UART_OVERSAMPLING_16; - if (HAL_UART_Init(&huart2) != HAL_OK) - { - return FALSE; - } - - return TRUE; -} - -BOOL -xMBPortSerialPutByte( CHAR ucByte ) -{ - /* Put a byte in the UARTs transmit buffer. This function is called - * by the protocol stack if pxMBFrameCBTransmitterEmpty( ) has been - * called. */ - - if(HAL_UART_Transmit(&huart2,(uint8_t*)&ucByte,1,1) == HAL_OK) - return TRUE; - else - return FALSE; -} - -BOOL -xMBPortSerialGetByte( CHAR * pucByte ) -{ - /* Return the byte in the UARTs receive buffer. This function is called - * by the protocol stack after pxMBFrameCBByteReceived( ) has been called. - */ - if(HAL_UART_Receive(&huart2,(uint8_t*)pucByte,1,1) == HAL_OK) - return TRUE; - else - return FALSE; -} - -/* Create an interrupt handler for the transmit buffer empty interrupt - * (or an equivalent) for your target processor. This function should then - * call pxMBFrameCBTransmitterEmpty( ) which tells the protocol stack that - * a new character can be sent. The protocol stack will then call - * xMBPortSerialPutByte( ) to send the character. - */ -void prvvUARTTxReadyISR( void ) -{ - pxMBFrameCBTransmitterEmpty( ); -} - -/* Create an interrupt handler for the receive interrupt for your target - * processor. This function should then call pxMBFrameCBByteReceived( ). The - * protocol stack will then call xMBPortSerialGetByte( ) to retrieve the - * character. - */ -void prvvUARTRxISR( void ) -{ - pxMBFrameCBByteReceived( ); -} diff --git a/components/connectivity/Modbus/porting/TencentOS_Tiny/porttimer.c b/components/connectivity/Modbus/porting/TencentOS_Tiny/porttimer.c deleted file mode 100644 index 146edf988..000000000 --- a/components/connectivity/Modbus/porting/TencentOS_Tiny/porttimer.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * FreeModbus Libary: BARE Port - * Copyright (C) 2006 Christian Walter - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * File: $Id$ - */ - -/* ----------------------- Platform includes --------------------------------*/ -#include "mod_port.h" -#include "mcu_init.h" -/* ----------------------- Modbus includes ----------------------------------*/ -#include "mb.h" -#include "mbport.h" - -/* ----------------------- static functions ---------------------------------*/ -void prvvTIMERExpiredISR( void ); -extern TIM_HandleTypeDef htim6; -/* ----------------------- Start implementation -----------------------------*/ -BOOL -xMBPortTimersInit( USHORT usTim1Timerout50us ) -{ - HAL_TIM_Base_DeInit(&htim6); - - TIM_MasterConfigTypeDef sMasterConfig = {0}; - - /* USER CODE BEGIN TIM6_Init 1 */ - - /* USER CODE END TIM6_Init 1 */ - htim6.Instance = TIM6; - htim6.Init.Prescaler = 4499; - htim6.Init.CounterMode = TIM_COUNTERMODE_UP; - - - htim6.Init.Period = usTim1Timerout50us-1; - - - htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - if (HAL_TIM_Base_Init(&htim6) != HAL_OK) - { - return FALSE; - } - sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; - sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; - if (HAL_TIMEx_MasterConfigSynchronization(&htim6, &sMasterConfig) != HAL_OK) - { - return FALSE; - } - return TRUE; -} - - -inline void -vMBPortTimersEnable( ) -{ - /* Enable the timer with the timeout passed to xMBPortTimersInit( ) */ - __HAL_TIM_CLEAR_IT(&htim6,TIM_IT_UPDATE); - __HAL_TIM_SetCounter(&htim6,0); - HAL_TIM_Base_Start_IT(&htim6); -} - -inline void -vMBPortTimersDisable( ) -{ - /* Disable any pending timers. */ - HAL_TIM_Base_Stop_IT(&htim6); - __HAL_TIM_SetCounter(&htim6,0); - __HAL_TIM_CLEAR_IT(&htim6,TIM_IT_UPDATE); -} - -/* Create an ISR which is called whenever the timer has expired. This function - * must then call pxMBPortCBTimerExpired( ) to notify the protocol stack that - * the timer has expired. - */ -void prvvTIMERExpiredISR( void ) -{ - ( void )pxMBPortCBTimerExpired( ); -} - diff --git a/components/fs/kv/include/tos_kv.h b/components/fs/kv/include/tos_kv.h index 8d97ea095..0cf8b1cb5 100644 --- a/components/fs/kv/include/tos_kv.h +++ b/components/fs/kv/include/tos_kv.h @@ -81,7 +81,7 @@ typedef uint64_t kv_dword_t; // double word #define KV_NO_WRITEABLE_BLK() (KV_MGR_BLK_NUM_INUSE == 0 && KV_MGR_BLK_NUM_FRESH == 0) -#define KV_ITEM_HDR_MAGIC 0xABCD1234DCBA4321 +#define KV_ITEM_HDR_MAGIC 0x69745F6D61676963 /* "it_magic" */ #define KV_ITEM_DISCARDED 0x0F0F0F0F0F0F0F0F #define KV_ITEM_IS_DISCARDED(item_hdr) ((item_hdr)->discarded_flag == KV_ITEM_DISCARDED) #define KV_ITEM_IS_LEGAL(item_hdr) ((item_hdr)->magic == KV_ITEM_HDR_MAGIC) @@ -100,10 +100,10 @@ typedef uint64_t kv_dword_t; // double word #define KV_ITEM_SIZE_OF_BODY(item) KV_ITEM_BODY_SIZE(item->hdr.k_len, item->hdr.v_len) #define KV_ITEM_ADDR_OF_BODY(item) (item->pos + KV_ITEM_HDR_SIZE) -#define KV_BLK_HDR_MAGIC 0x1234ABCD4321DCBA -#define KV_BLK_HDR_GC_SRC 0x5678DCBA8765ABCD -#define KV_BLK_HDR_GC_DST 0x8765ABCD8765DCBA -#define KV_BLK_HDR_GC_DONE 0x4321DCBA1234ABCD +#define KV_BLK_HDR_MAGIC 0x48445F4D41474943 /* "HD_MAGIC" */ +#define KV_BLK_HDR_GC_SRC 0x6D61726B5F737263 /* "mark_src" */ +#define KV_BLK_HDR_GC_DST 0x6D61726B5F647374 /* "mark_dst" */ +#define KV_BLK_HDR_GC_DONE 0x6B67635F646F6E65 /* "kgc_done" */ #define KV_BLK_IS_LEGAL(blk_hdr) ((blk_hdr)->magic == KV_BLK_HDR_MAGIC) @@ -196,7 +196,7 @@ typedef struct kv_item_st { uint8_t *body; /*< item body: key/value buffer */ } kv_item_t; -__STATIC__ kv_ctl_t kv_ctl; +extern kv_ctl_t kv_ctl; __STATIC_INLINE__ void kv_blk_freesz_set(uint32_t blk_start, uint32_t free_size) { diff --git a/components/fs/kv/tos_kv.c b/components/fs/kv/tos_kv.c index b4de95af8..2bf362e98 100644 --- a/components/fs/kv/tos_kv.c +++ b/components/fs/kv/tos_kv.c @@ -145,6 +145,20 @@ __STATIC__ uint32_t kv_blk_next_fresh(void) return KV_BLK_INVALID; } +__STATIC__ uint32_t kv_blk_get_a_fresh(void) +{ + uint32_t cur_blk; + + KV_BLK_FOR_EACH(cur_blk) { + if (kv_blk_is_fresh(cur_blk)) { + return cur_blk; + } + } + + return KV_BLK_INVALID; +} + + __STATIC__ uint32_t kv_blk_search_inuse(uint32_t item_size) { uint32_t cur_blk; @@ -940,6 +954,26 @@ __STATIC__ int kv_mgr_blk_index_rebuild(void) return is_rebuild_done; } +__STATIC__ kv_err_t kv_try_gc(void) +{ + uint32_t cur_blk, blk_dst; + + blk_dst = kv_blk_get_a_fresh(); + if (blk_dst == KV_BLK_INVALID) { + return KV_ERR_GC_NOTHING; + } + + KV_BLK_FOR_EACH(cur_blk) { + if (kv_blk_is_dirty(cur_blk)) { + if (kv_do_gc(cur_blk, blk_dst, K_FALSE) == KV_ERR_NONE) { + return KV_ERR_NONE; + } + } + } + + return KV_ERR_GC_NOTHING; +} + __STATIC__ kv_err_t kv_mgr_workspace_locate(void) { uint32_t cur_blk; @@ -949,6 +983,12 @@ __STATIC__ kv_err_t kv_mgr_workspace_locate(void) kv_mgr_blk_index_rebuild(); } + if (KV_MGR_BLK_NUM_INUSE == 0 && KV_MGR_BLK_NUM_FRESH == 1) { + /* if here, we cannot just give out the last fresh block, otherwise the kv will get into + KV_ERR_NO_WRITEABLE_BLK next time, try a gc here to get a "rescue" */ + kv_try_gc(); + } + if (KV_NO_WRITEABLE_BLK()) { return KV_ERR_NO_WRITEABLE_BLK; } @@ -1078,7 +1118,6 @@ __STATIC__ int kv_handle_incomplete_gc(struct blk_info gc_src_blk, struct blk_in __STATIC__ int kv_mgr_ctl_build(void) { - kv_err_t err; uint32_t cur_blk; kv_blk_hdr_t blk_hdr; @@ -1176,22 +1215,21 @@ __STATIC__ kv_err_t kv_gc(void) // there must be at least one fresh block left, make workspace pointer to the fresh one blk_dst = kv_blk_next_fresh(); + if (blk_dst == KV_BLK_INVALID) { + /* kinda a bug here, KV_MGR_BLK_NUM_FRESH == 1 */ + return KV_ERR_GC_NOTHING; + } KV_BLK_FOR_EACH(cur_blk) { if (kv_blk_is_dirty(cur_blk)) { - if (kv_do_gc(cur_blk, blk_dst, K_FALSE) != KV_ERR_NONE) { - // cannot do gc for this block, give others a try - continue; + if (kv_do_gc(cur_blk, blk_dst, K_FALSE) == KV_ERR_NONE) { + is_gc_done = K_TRUE; + break; } - - is_gc_done = K_TRUE; - - break; } } if (is_gc_done) { - // if do nothing, should restore the workspace; KV_MGR_WORKSPACE = blk_dst; } diff --git a/components/shell/include/tos_shell.h b/components/shell/include/tos_shell.h index 2d6c38939..77742e8e5 100644 --- a/components/shell/include/tos_shell.h +++ b/components/shell/include/tos_shell.h @@ -26,7 +26,7 @@ #define SHELL_PARSER_TASK_STACK_SIZE 1024 #define SHELL_PARSER_TASK_PRIO 3 -typedef void (*shell_output_t)(const char *str); +typedef void (*shell_output_t)(const char ch); typedef struct shell_control_st { k_task_t parser; @@ -53,6 +53,8 @@ __API__ int tos_shell_cmd_set_unregiser(const shell_cmd_set_t *cmd_set); __API__ void tos_shell_printf(const char *format, ...); +__API__ void tos_shell_printfln(const char *format, ...); + __API__ void tos_shell_input_byte(uint8_t data); #endif /* _TOS_SHELL_H_ */ diff --git a/components/shell/include/tos_shell_command.h b/components/shell/include/tos_shell_command.h index 16e8019b3..02089e3c3 100644 --- a/components/shell/include/tos_shell_command.h +++ b/components/shell/include/tos_shell_command.h @@ -33,6 +33,8 @@ typedef struct shell_command_set_st { const shell_cmd_t *const commands; } shell_cmd_set_t; +__KNL__ int cmd_help(int argc, char *argv[]); + __KNL__ int shell_cmd_set_regiser(const shell_cmd_set_t *cmd_set); __KNL__ int shell_cmd_set_unregiser(const shell_cmd_set_t *cmd_set); diff --git a/components/shell/tos_shell.c b/components/shell/tos_shell.c index f940b33e1..0646e7319 100644 --- a/components/shell/tos_shell.c +++ b/components/shell/tos_shell.c @@ -35,10 +35,23 @@ __STATIC__ int shell_getchar(void) return err == K_ERR_NONE ? chr : -1; } +__STATIC__ void shell_putchar(const char ch) +{ + SHELL_CTL->output(ch); +} + +__STATIC__ void shell_puts(const char *s) +{ + while (*s) { + SHELL_CTL->output(*s++); + } +} + __STATIC__ int shell_readline(void) { - int chr, last_chr = 0; + int chr; char *buf = SHELL_CTL->cmd_buffer; + uint16_t line_length = 0; while (K_TRUE) { if (buf - SHELL_CTL->cmd_buffer >= (SHELL_CTL->cmd_buffer_size - 1)) { @@ -50,23 +63,29 @@ __STATIC__ int shell_readline(void) return -1; } - if (chr == '\n' && last_chr == '\r') { - *--buf = '\0'; - return 0; - } else if (chr == '\n') { + if (chr == '\n' || chr == '\r') { + *buf = '\0'; + tos_shell_printf("\r\n"); + break; + } else if (chr == '\t'){ *buf = '\0'; - return 0; + tos_shell_printf("\r\n"); + cmd_help(0, NULL); + break; } - - *buf++ = chr; - last_chr = chr; + + shell_putchar(chr); + + *buf++ = chr; + line_length++; } + return line_length; } __STATIC__ void shell_cmd_do_process(int argc, char *argv[]) { const shell_cmd_t *cmd; - static const char *cmd_not_found = "command not found\n"; + static const char *cmd_not_found = "command not found\r\n"; cmd = shell_cmd_find(argv[0]); if (!cmd) { @@ -82,8 +101,6 @@ __STATIC__ void shell_cmd_process(void) static char *argv[SHELL_CMD_ARGV_MAX]; char *pos = SHELL_CTL->cmd_buffer; - tos_shell_printf("%s\n", SHELL_CTL->cmd_buffer); - // left strip while (*pos == ' ' || *pos == '\t') { ++pos; @@ -113,7 +130,7 @@ __STATIC__ void shell_cmd_process(void) __STATIC__ void shell_prompt(void) { - tos_shell_printf("> "); + tos_shell_printf("tshell>"); } __STATIC__ void shell_parser(void *arg) @@ -125,7 +142,7 @@ __STATIC__ void shell_parser(void *arg) while (K_TRUE) { rc = shell_readline(); - if (!rc) { + if (rc > 0) { shell_cmd_process(); } @@ -208,7 +225,20 @@ __API__ void tos_shell_printf(const char *format, ...) vsnprintf(buffer, sizeof(buffer), format, args); va_end(args); - (SHELL_CTL->output)(buffer); + shell_puts(buffer); +} + +__API__ void tos_shell_printfln(const char *format, ...) +{ + va_list args; + static char buffer[SHELL_OUTPUT_MAX]; + + va_start(args, format); + vsnprintf(buffer, sizeof(buffer), format, args); + va_end(args); + + shell_puts(buffer); + shell_puts("\r\n"); } __API__ void tos_shell_input_byte(uint8_t data) diff --git a/components/shell/tos_shell_commands.c b/components/shell/tos_shell_commands.c index acfcb8b78..85ef186bf 100644 --- a/components/shell/tos_shell_commands.c +++ b/components/shell/tos_shell_commands.c @@ -20,23 +20,72 @@ __STATIC__ TOS_SLIST_DEFINE(cmd_set_list); -__STATIC__ int cmd_help(int argc, char *argv[]) +int cmd_help(int argc, char *argv[]) { shell_cmd_set_t *cmd_set; const shell_cmd_t *cmd; TOS_SLIST_FOR_EACH_ENTRY(cmd_set, shell_cmd_set_t, list, &cmd_set_list) { for (cmd = cmd_set->commands; cmd->name; ++cmd) { - tos_shell_printf("%-8s: %s\n", cmd->name, cmd->help); + tos_shell_printf("%-8s: %s\r\n", cmd->name, cmd->help); } } return 0; } +static void task_shell_walker(k_task_t *task) +{ + char *state_str = "ABNORMAL"; + + if (!task) { + return; + } + + state_str = state_str; + tos_shell_printfln("task name: %s", task->name); + + if (tos_task_curr_task_get() == task) { + state_str = "RUNNING"; + } else if (task->state == K_TASK_STATE_PENDTIMEOUT_SUSPENDED) { + state_str = "PENDTIMEOUT_SUSPENDED"; + } else if (task->state == K_TASK_STATE_PEND_SUSPENDED) { + state_str = "PEND_SUSPENDED"; + } else if (task->state == K_TASK_STATE_SLEEP_SUSPENDED) { + state_str = "SLEEP_SUSPENDED"; + } else if (task->state == K_TASK_STATE_PENDTIMEOUT) { + state_str = "PENDTIMEOUT"; + } else if (task->state == K_TASK_STATE_SUSPENDED) { + state_str = "SUSPENDED"; + } else if (task->state == K_TASK_STATE_PEND) { + state_str = "PEND"; + } else if (task->state == K_TASK_STATE_SLEEP) { + state_str = "SLEEP"; + } else if (task->state == K_TASK_STATE_READY) { + state_str = "READY"; + } + + tos_shell_printfln("task stat: %s", state_str); + tos_shell_printfln("stk size : %d", task->stk_size); + tos_shell_printfln("stk base : 0x%p", task->stk_base); + tos_shell_printfln("stk top : 0x%p", task->stk_base + task->stk_size); + +#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u + int depth; + + if (tos_task_stack_draught_depth(task, &depth) != K_ERR_NONE) { + depth = -1; + } + + tos_shell_printfln("stk depth: %d", depth); +#endif /* TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN */ + + tos_shell_printf("\r\n"); +} + __STATIC__ int cmd_ps(int argc, char *argv[]) { - tos_task_info_display(); + tos_task_walkthru(task_shell_walker); return 0; } diff --git a/doc/image/introduction/Partners.png b/doc/image/introduction/Partners.png index ecc4fd7eb..ae6e42b73 100644 Binary files a/doc/image/introduction/Partners.png and b/doc/image/introduction/Partners.png differ diff --git a/examples/hello_world/hello_world.c b/examples/hello_world/hello_world.c index de4be9608..9469956be 100644 --- a/examples/hello_world/hello_world.c +++ b/examples/hello_world/hello_world.c @@ -1,72 +1,34 @@ -#include "cmsis_os.h" +#include "tos_k.h" -#define TASK1_STK_SIZE 1024 -void task1(void *arg); -osThreadDef(task1, osPriorityNormal, 1, TASK1_STK_SIZE); +#define TASK1_STK_SIZE 1024 +k_task_t task1; +uint8_t task1_stk[TASK1_STK_SIZE]; -#define TASK2_STK_SIZE 1024 -void task2(void *arg); -osThreadDef(task2, osPriorityNormal, 1, TASK2_STK_SIZE); -#if TOS_CFG_TASK_DYNAMIC_CREATE_EN > 0u -#define TASK3_STK_SIZE 512 -void task3(void *arg); -#endif +#define TASK2_STK_SIZE 1024 +k_task_t task2; +uint8_t task2_stk[TASK2_STK_SIZE]; -void task1(void *arg) +void task1_entry(void *arg) { -#if TOS_CFG_TASK_DYNAMIC_CREATE_EN > 0u - osThreadId task_dyn_created; - - osThreadDynamicDef(task3, osPriorityNormal, 1, TASK3_STK_SIZE); - task_dyn_created = osThreadCreate(osThread(task3), NULL); - - int count = 0; -#endif - while (1) { printf("###I am task1\r\n"); - osDelay(2000); - -#if TOS_CFG_TASK_DYNAMIC_CREATE_EN > 0u - if (count++ == 3) { - printf("###I am task1, kill the task3(dynamic created)\r\n"); - osThreadTerminate(task_dyn_created); - } -#endif + tos_task_delay(2000); } } -void task2(void *arg) +void task2_entry(void *arg) { while (1) { -#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u - k_err_t rc; - int depth; - - rc = tos_task_stack_draught_depth(K_NULL, &depth); - printf("%d %d\n", rc, depth); -#endif - printf("***I am task2\r\n"); - osDelay(1000); + tos_task_delay(1000); } } -#if TOS_CFG_TASK_DYNAMIC_CREATE_EN > 0u -void task3(void *arg) -{ - while (1) { - printf("$$$I am task3(dynamic created)\r\n"); - osDelay(2000); - } -} -#endif void application_entry(void *arg) { - printf("***I am task\r\n"); - osThreadCreate(osThread(task1), NULL); // Create task1 - osThreadCreate(osThread(task2), NULL); // Create task2 + tos_task_create(&task1, "task1", task1_entry, NULL, 3, task1_stk, TASK1_STK_SIZE, 0); // Create task1 + tos_task_create(&task2, "task2", task2_entry, NULL, 3, task2_stk, TASK2_STK_SIZE, 0);// Create task2 } diff --git a/examples/mqttclient_iot_explorer/mqttclient_iot_explorer.c b/examples/mqttclient_iot_explorer/mqttclient_iot_explorer.c index 4827a8372..4d1c3b17f 100644 --- a/examples/mqttclient_iot_explorer/mqttclient_iot_explorer.c +++ b/examples/mqttclient_iot_explorer/mqttclient_iot_explorer.c @@ -1,7 +1,7 @@ #include "mcu_init.h" #include "tos_k.h" #include "mqttclient.h" -#include "cjson.h" +#include "cJSON.h" #include "sal_module_wrapper.h" #define USE_ESP8266 diff --git a/examples/nnom_mnist/data/image.h b/examples/nnom_mnist/data/image.h new file mode 100644 index 000000000..855c74aef --- /dev/null +++ b/examples/nnom_mnist/data/image.h @@ -0,0 +1,36 @@ +#define IMG0 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 46, 61, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 40, 127, 84, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 123, 126, 113, 58, 0, 0, 0, 0, 0, 0, 0, 28, 112, 126, 84, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 42, 126, 126, 126, 125, 116, 111, 63, 63, 64, 81, 116, 123, 126, 125, 55, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 42, 126, 105, 42, 113, 126, 126, 126, 126, 126, 126, 126, 126, 126, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 118, 121, 17, 12, 21, 69, 73, 73, 73, 73, 122, 126, 126, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 33, 126, 21, 0, 0, 0, 0, 0, 0, 34, 122, 126, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 53, 5, 0, 0, 0, 0, 0, 16, 118, 126, 84, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 74, 126, 121, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 49, 126, 126, 93, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 49, 123, 126, 126, 124, 70, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 85, 126, 123, 105, 125, 126, 104, 65, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 98, 126, 105, 0, 55, 112, 126, 126, 115, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 37, 126, 122, 31, 0, 0, 7, 32, 63, 80, 58, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 98, 126, 73, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 116, 126, 51, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 42, 126, 108, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 42, 126, 76, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 106, 126, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 21, 126, 119, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 21, 126, 49, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +#define IMG0_LABLE 7 + +#define IMG1 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 36, 76, 76, 96, 107, 126, 127, 86, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 20, 81, 101, 126, 126, 126, 126, 126, 126, 126, 126, 51, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 81, 127, 126, 127, 126, 127, 116, 101, 101, 107, 126, 91, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 81, 116, 75, 75, 55, 25, 15, 0, 0, 25, 126, 51, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 86, 126, 51, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 126, 126, 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 86, 127, 116, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 41, 66, 126, 126, 35, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 107, 126, 127, 126, 127, 126, 127, 126, 127, 126, 96, 56, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 51, 126, 126, 126, 126, 126, 126, 126, 126, 126, 126, 126, 106, 81, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 91, 127, 106, 101, 101, 117, 126, 122, 101, 81, 61, 51, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 25, 5, 0, 0, 96, 126, 101, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 81, 127, 116, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 41, 121, 126, 55, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 127, 126, 61, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 71, 126, 85, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 26, 126, 127, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 66, 126, 106, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 86, 126, 61, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 106, 85, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +#define IMG1_LABLE 7 + +#define IMG2 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 95, 127, 127, 127, 127, 127, 64, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 95, 127, 127, 127, 127, 64, 32, 64, 127, 127, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 95, 127, 127, 127, 127, 95, 0, 0, 0, 64, 127, 127, 95, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 127, 127, 95, 64, 64, 32, 0, 0, 0, 0, 127, 127, 127, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 95, 127, 127, 64, 0, 0, 0, 0, 0, 0, 0, 32, 127, 127, 127, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 95, 127, 127, 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, 127, 127, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 127, 127, 127, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 127, 127, 95, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 95, 127, 127, 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, 127, 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 127, 127, 127, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 127, 127, 64, 0, 0, 0, 0, 0, 0, 0, 0, 64, 127, 127, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 127, 127, 64, 0, 0, 0, 0, 0, 0, 0, 0, 127, 127, 127, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 95, 127, 127, 32, 0, 0, 0, 0, 0, 0, 0, 0, 127, 127, 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, 127, 127, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 127, 127, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, 127, 127, 95, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 127, 127, 95, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, 127, 127, 127, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 127, 127, 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 95, 127, 127, 127, 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 127, 127, 127, 64, 0, 0, 0, 0, 0, 0, 32, 127, 127, 127, 127, 95, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, 127, 127, 127, 64, 0, 0, 32, 64, 95, 127, 127, 127, 127, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 95, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 95, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 95, 127, 127, 127, 127, 127, 127, 127, 95, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 127, 127, 127, 127, 127, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +#define IMG2_LABLE 0 + +#define IMG3 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 100, 127, 127, 112, 79, 79, 47, 31, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 36, 127, 127, 127, 127, 127, 127, 127, 127, 120, 43, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 60, 127, 127, 127, 127, 127, 127, 127, 127, 127, 117, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 60, 127, 90, 2, 2, 47, 50, 64, 62, 98, 106, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 101, 127, 30, 0, 0, 0, 0, 0, 0, 0, 5, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 108, 95, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 108, 83, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 108, 86, 8, 8, 25, 12, 12, 25, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 92, 127, 119, 120, 127, 127, 127, 127, 106, 67, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 51, 127, 127, 127, 127, 127, 127, 127, 127, 126, 106, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 92, 119, 116, 89, 26, 24, 42, 94, 101, 124, 108, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 40, 108, 61, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 49, 121, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 67, 124, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 81, 124, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 42, 104, 17, 0, 0, 0, 0, 0, 0, 0, 0, 8, 47, 125, 124, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 46, 127, 113, 82, 51, 47, 2, 2, 4, 51, 76, 110, 127, 126, 85, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 113, 127, 127, 127, 127, 127, 127, 109, 127, 127, 127, 127, 107, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 37, 78, 110, 117, 127, 127, 127, 127, 76, 16, 48, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 18, 112, 108, 127, 61, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +#define IMG3_LABLE 5 + +#define IMG4 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 45, 126, 100, 66, 66, 32, 6, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 102, 126, 126, 126, 126, 126, 126, 115, 72, 55, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 65, 126, 126, 126, 126, 126, 126, 126, 126, 126, 110, 55, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 42, 126, 126, 126, 126, 126, 126, 126, 126, 126, 126, 126, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 36, 90, 110, 126, 126, 126, 126, 126, 126, 126, 126, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 30, 30, 52, 106, 126, 126, 126, 126, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 94, 126, 126, 126, 126, 66, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 110, 126, 126, 126, 126, 89, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 26, 86, 126, 126, 126, 126, 110, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 26, 120, 126, 126, 126, 126, 126, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 28, 121, 126, 127, 126, 126, 114, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 24, 118, 126, 126, 126, 126, 124, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 83, 126, 126, 126, 126, 126, 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 20, 116, 126, 126, 126, 126, 126, 106, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 99, 126, 126, 126, 126, 126, 108, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 116, 126, 126, 126, 126, 126, 63, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 94, 126, 126, 126, 126, 110, 29, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 108, 126, 126, 126, 110, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 78, 126, 126, 84, 48, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 41, 106, 126, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +#define IMG4_LABLE 7 + +#define IMG5 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 40, 81, 127, 117, 97, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 69, 112, 126, 116, 99, 114, 107, 125, 85, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 98, 126, 123, 88, 24, 0, 10, 5, 42, 126, 102, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 96, 127, 92, 46, 0, 0, 0, 0, 0, 2, 78, 127, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 99, 126, 68, 2, 0, 0, 0, 0, 0, 0, 0, 13, 127, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 100, 97, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 127, 54, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 99, 81, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 127, 28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 99, 120, 23, 0, 0, 0, 0, 0, 0, 0, 0, 62, 127, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 77, 126, 109, 32, 8, 0, 0, 0, 0, 0, 30, 119, 98, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 84, 127, 126, 121, 90, 90, 62, 45, 52, 119, 126, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 29, 71, 95, 127, 127, 127, 127, 127, 127, 127, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 9, 41, 54, 54, 58, 116, 126, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 18, 126, 126, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 18, 126, 126, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 34, 126, 94, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 76, 124, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 108, 117, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 117, 117, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 126, 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 60, 126, 56, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +#define IMG5_LABLE 9 + +#define IMG6 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 37, 0, 49, 92, 89, 47, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 55, 97, 119, 47, 0, 104, 124, 127, 127, 58, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 25, 53, 98, 123, 91, 12, 0, 0, 40, 122, 127, 124, 45, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 42, 115, 127, 127, 110, 43, 0, 0, 0, 62, 126, 127, 89, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 66, 127, 127, 108, 59, 2, 0, 0, 31, 101, 127, 120, 65, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 53, 122, 127, 106, 22, 0, 0, 0, 31, 120, 127, 110, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 22, 123, 127, 104, 24, 0, 0, 0, 15, 120, 127, 110, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 47, 127, 127, 27, 0, 0, 0, 8, 99, 127, 109, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13, 109, 127, 116, 72, 19, 21, 102, 127, 102, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 57, 124, 127, 127, 122, 116, 127, 111, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 42, 84, 122, 127, 127, 127, 103, 57, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 118, 127, 115, 81, 118, 122, 105, 40, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 49, 127, 127, 49, 0, 0, 18, 112, 127, 65, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 35, 127, 114, 6, 0, 0, 0, 1, 85, 127, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 48, 127, 127, 9, 0, 0, 0, 0, 40, 127, 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 40, 127, 127, 9, 0, 0, 0, 0, 65, 127, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 107, 127, 39, 0, 0, 0, 0, 91, 122, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 126, 111, 12, 0, 1, 63, 127, 89, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 43, 119, 111, 59, 88, 127, 108, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 77, 98, 98, 50, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +#define IMG6_LABLE 8 + +#define IMG7 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 95, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13, 126, 126, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 73, 126, 126, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 59, 126, 126, 66, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13, 126, 126, 114, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 87, 126, 126, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 73, 126, 126, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 73, 126, 126, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 73, 126, 126, 45, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 73, 126, 126, 72, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 73, 126, 127, 73, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 73, 126, 126, 72, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13, 126, 126, 72, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 126, 126, 72, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 126, 126, 115, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 126, 126, 114, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 126, 126, 81, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 119, 126, 126, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 66, 126, 123, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 66, 126, 72, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +#define IMG7_LABLE 1 + +#define IMG8 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 21, 75, 84, 127, 127, 127, 104, 43, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 72, 119, 126, 105, 99, 99, 99, 113, 125, 85, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 115, 127, 83, 24, 4, 0, 0, 0, 9, 80, 126, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 48, 126, 27, 2, 0, 0, 0, 0, 0, 0, 58, 126, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13, 119, 94, 0, 0, 0, 0, 0, 0, 0, 0, 83, 94, 13, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 109, 94, 0, 0, 0, 0, 0, 0, 0, 0, 0, 29, 127, 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 73, 126, 26, 0, 0, 0, 0, 0, 0, 0, 0, 87, 127, 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 126, 89, 1, 0, 0, 0, 0, 0, 0, 31, 121, 127, 38, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 59, 127, 65, 1, 0, 0, 0, 0, 0, 73, 126, 95, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 65, 123, 89, 26, 0, 0, 0, 29, 119, 110, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 102, 127, 94, 81, 123, 127, 127, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 44, 86, 117, 110, 122, 121, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 11, 111, 94, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 47, 126, 72, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 56, 126, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 127, 72, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 116, 114, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 108, 117, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 108, 117, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 92, 117, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +#define IMG8_LABLE 9 + +#define IMG9 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 3, 3, 3, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 45, 68, 107, 127, 127, 127, 127, 81, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 71, 104, 127, 127, 127, 127, 127, 127, 127, 127, 63, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 103, 127, 127, 127, 119, 73, 52, 52, 52, 103, 127, 127, 27, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 103, 127, 127, 118, 104, 18, 0, 0, 0, 0, 34, 127, 127, 83, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 88, 127, 116, 45, 0, 0, 0, 0, 0, 0, 34, 127, 127, 83, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 22, 43, 19, 0, 0, 0, 0, 0, 0, 0, 75, 127, 127, 83, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 96, 127, 127, 83, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 36, 118, 127, 127, 39, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 93, 127, 127, 82, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 21, 119, 127, 127, 24, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 87, 127, 127, 79, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 45, 127, 127, 99, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 70, 120, 127, 127, 71, 0, 0, 0, 0, 0, 18, 44, 72, 106, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 56, 121, 127, 127, 127, 66, 47, 47, 68, 109, 109, 116, 127, 105, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 40, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 82, 77, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 78, 127, 127, 127, 127, 127, 127, 127, 127, 83, 51, 12, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 20, 127, 127, 127, 127, 113, 71, 53, 9, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 57, 36, 6, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +#define IMG9_LABLE 2 + +#define TOTAL_IMAGE 10 + +static const int8_t img[10][784] = {IMG0,IMG1,IMG2,IMG3,IMG4,IMG5,IMG6,IMG7,IMG8,IMG9}; + +static const int8_t label[10] = {IMG0_LABLE,IMG1_LABLE,IMG2_LABLE,IMG3_LABLE,IMG4_LABLE,IMG5_LABLE,IMG6_LABLE,IMG7_LABLE,IMG8_LABLE,IMG9_LABLE}; + diff --git a/examples/nnom_mnist/data/weights.h b/examples/nnom_mnist/data/weights.h new file mode 100644 index 000000000..8bf95dc57 --- /dev/null +++ b/examples/nnom_mnist/data/weights.h @@ -0,0 +1,420 @@ +#include "nnom.h" + +/* Weights, bias and Q format */ +#define TENSOR_CONV2D_KERNEL_0 {43, 49, 37, 63, 24, 74, -39, -26, 7, 86, 41, 20, 56, -10, -64, -4, 7, -78, 38, 74, 28, -16, 51, -1, -82, -87, -14, -26, -25, 61, -69, -19, 68, -55, -19, 66, 10, -34, -86, 58, 41, -36, 65, -22, 80, 7, 56, 16, -31, -31, 39, -43, -11, -76, -26, -5, 66, -14, -9, 43, 4, -32, 76, 2, -72, -70, 32, 45, 32, 44, -17, 31, 76, -2, 32, 64, 85, -60, 5, 21, -96, -24, -81, -61, 45, 69, -3, 14, 55, 69, 82, -44, -71, 83, -16, -66, 49, 55, 31, -30, 17, 46, -3, 16, 7, 19, 80, 72} + +#define TENSOR_CONV2D_KERNEL_0_DEC_BITS {8} + +#define TENSOR_CONV2D_BIAS_0 {-20, 13, 92, 22, -3, 83, -81, -4, -13, -3, -10, -16} + +#define TENSOR_CONV2D_BIAS_0_DEC_BITS {11} + +#define CONV2D_BIAS_LSHIFT {4} + +#define CONV2D_OUTPUT_RSHIFT {9} + +#define TENSOR_CONV2D_1_KERNEL_0 {25, 1, 56, -15, -11, 1, -38, 32, -22, -19, -3, -33, 16, -34, -34, 15, 25, -9, 4, -6, -16, 38, -13, 30, 41, -14, -22, 43, -24, -31, 29, -20, 45, 13, 20, 20, 19, -28, 0, 57, 5, -22, 48, -19, -35, 38, 18, 9, 21, -7, -27, 20, 2, -88, 21, -15, 39, 33, 1, 57, 19, 47, -13, -40, -34, -29, 3, -14, 41, -28, 33, -21, -1, 23, -61, -22, 20, -66, -16, 2, -1, 45, -38, 60, 3, 0, -24, -40, -16, -31, -32, -46, 33, -1, 25, 13, 19, 58, -8, -50, -9, -2, -54, -35, 46, -63, 37, -59, 48, 48, 48, -1, -11, 7, 30, 13, 55, 13, 16, 26, 37, 51, 30, 2, 0, 12, 38, -42, 60, -28, 21, 0, 12, 25, -5, -32, -39, 2, -40, -31, -10, -61, 12, -45, 36, 21, 89, 2, -48, 24, 21, -69, 11, -70, 9, -43, -1, 51, 24, -5, -43, 39, -28, -36, 21, -74, -13, -46, -41, -48, -34, 19, -5, -54, 40, -12, -64, 1, -25, 17, -35, -6, -25, -27, -16, -3, -36, 20, -32, -10, -7, -7, -55, -17, -67, 30, -31, -27, -4, 12, -59, -31, -19, 18, 17, -12, -20, 45, 27, -56, 36, -16, -16, -4, 22, 57, -33, 31, 29, 23, 6, -6, -13, -17, -12, -33, -8, -10, -28, -52, -44, 28, -20, -29, 37, -20, 2, -4, 12, -5, -22, -17, -63, -3, 14, -35, 48, 30, 18, 5, -21, 41, -30, -31, -14, 18, -25, -36, -48, -5, -29, -27, -3, -24, -30, -60, -44, 34, -35, -55, 37, -39, -3, 16, -8, 37, 42, -6, -4, 4, -32, -47, 5, -4, 20, 26, 31, 49, -25, 28, -11, -32, -12, 23, -27, -37, 28, 7, -22, -35, -6, -57, -42, 36, -36, -10, 46, -17, -51, 26, -5, 21, 21, 0, -16, 27, -8, -14, 34, -42, -22, 21, 25, 15, -14, -1, 37, 53, -17, 9, -7, 15, 31, -48, 25, -3, -20, -9, -48, 49, -4, -52, 27, -16, -31, 30, -27, 16, 6, 45, -61, 8, 41, -57, -32, -4, 40, 16, -14, 1, -7, 18, -29, 40, -34, -28, 41, -42, -42, -32, 3, -20, -6, -42, -48, 37, -31, -54, -14, -28, -15, -1, -8, 50, -17, 26, -40, 23, -8, -5, -40, 33, 11, 11, 42, -27, -6, -53, -24, -6, -16, -28, 14, -32, -68, 7, -49, 13, -3, 5, -45, 23, -21, 6, 0, -5, -25, -33, -26, -12, -10, 48, -32, -1, 47, -16, 21, -16, 19, 23, 38, 21, -22, 20, 29, 20, -49, 61, -45, -56, 6, -38, -31, -27, -20, 12, 103, -27, -22, 49, -4, -13, -8, -39, 2, -40, -25, 31, 76, -18, 17, 10, -29, -26, -34, -42, -8, -9, -11, -47, 2, -44, 17, -60, 23, 50, 8, 47, 41, 44, -22, -43, -39, -25, 53, -10, -4, 42, -46, 49, -11, 39, -37, -56, -21, 20, 0, -27, -16, 26, 5, 15, 44, 53, 17, 46, 38, 14, -21, 67, 24, 17, 38, 35, -25, -10, 29, 3, 46, -13, 1, 15, 34, 31, 19, 27, -10, 20, 20, -2, 54, -1, -11, 36, -9, 20, -18, 25, -15, 31, -4, -8, 45, 21, 23, 56, 33, -32, 29, -29, -33, 9, 21, -14, 19, 38, -39, 54, 3, -13, 34, -45, -4, -8, 5, 24, 79, -26, -26, 54, 25, 4, -6, -14, -16, 4, -42, 9, 39, -12, 17, 43, -53, -4, -3, 23, -15, -21, -53, -19, 61, -6, 3, 45, 18, -14, -11, -21, 18, -26, -23, -20, 11, -40, -16, 37, -18, 11, -41, 32, -3, -27, -3, -8, -7, 6, 40, -33, 8, 20, 3, 51, -19, 43, 22, -37, -62, -6, 51, -26, 37, 39, -28, 17, 32, 40, -17, -35, -65, 31, 43, -29, 43, -2, -17, 52, 16, 27, 26, 12, -8, 43, -31, -26, 39, -27, -22, -16, -42, -7, -8, 21, 2, 33, 23, -61, 5, 21, 13, 9, 30, 10, 22, 0, -39, 37, 35, -25, 23, -32, 47, -36, 25, 7, -14, -57, -13, 36, -61, -28, -10, -48, -15, -32, -44, 46, 1, -9, -16, -8, 17, -22, 29, -35, -23, -10, 25, -14, 29, 37, -24, -6, 23, -82, 6, -6, 34, 28, 36, 7, 6, -57, -43, 9, -22, -15, 33, -9, -47, -14, -46, -5, 25, 12, -27, -20, -24, -32, 23, -15, 28, -23, -2, 36, -7, -15, -40, -38, 10, -20, 11, 2, -21, 23, 36, -5, 16, 56, -14, 12, 39, -33, 31, -39, 74, -43, 42, 1, 8, 8, 20, -41, 12, -22, -39, -15, 64, -64, 40, -81, -53, -37, -29, 13, -14, -1, -39, -5, -76, -29, -55, -15, 15, 42, 38, -73, 4, 5, -72, -47, 57, -40, 22, -45, -8, -4, -13, -15, -28, 10, -2, -7, 12, 14, -42, 17, -23, -41, 7, 12, -26, 7, 11, 24, -57, 45, -15, 8, -49, -33, -49, 20, 22, 3, -23, -11, -44, 37, 0, -19, 4, -46, -25, 41, 13, -46, 44, 22, -48, 8, -1, 47, 16, -17, 8, 38, -12, -8, 12, -16, 0, 55, 11, 15, -8, 15, 25, -4, 28, -31, -16, 10, 4, 43, 56, -11, 7, 16, -37, 31, -9, -31, -8, 39, 31, 46, 40, 42, 61, -10, -52, 2, 23, -13, 55, 12, 13, 48, 21, 20, 25, 41, 37, 15, -8, 77, 18, 20, 24, -18, -5, -6, 20, 34, 25, 2, -44, 14, 4, -32, 40, -37, -4, -24, 18, 22, 40, -7, -23, 47, 18, -5, 23, -50, -50, -2, -24, -7, 14, -28, -41, 15, -43, -29, -28, 5, -67, -8, -14, -8, 29, 18, 8, 8, 5, -11, -1, -43, -51, -41, -26, -10, 4, 13, 4, 13, -40, -19, -12, -19, -26, -22, -28, -24, -34, 43, -41, -84, 7, -5, -1, 38, -45, 53, 12, 38, -65, 28, 5, -52, 15, -28, 52, 8, -7, 38, 17, 70, 47, -67, -21, -7, -51, -25, 16, -10, 40, -37, -1, -25, -45, 24, -28, -73, 27, -20, 29, 26, 2, 8, 40, 45, -27, -29, -4, -67, 18, 9, 19, -23, 18, 15, -8, 48, 5, -57, -3, 11, -48, -2, 43, 9, -2, -25, 37, 9, -54, 12, 15, -65, 10, -43, 49, -17, 13, 41, 40, -13, -46, 20, -12, -3, -11, -9, 13, 1, 45, -23, -26, -4, 20, -47, 17, 36, -64, -3, 24, 9, 24, -10, -40, -53, -28, 38, -5, -21, 1, 9, -10, -9, -37, 37, -18, 6, -61, 36, 8, -25, 42, -24, 7, -17, -4, -5, -5, -15, -65, 30, 1, -1, -18, 29, -4, 8, -24, 16, 17, -19, 3, 33, 7, 11, 37, -15, 11, -12, -25, 23, 2, -19, -6, 14, 3, -51, 38, 30, 0, 22, 28, 33, 23, 46, -58, -44, -11, -2, 23, 4, -11, -28, 14, -19, 20, -21, -1, -17, -1, -27, -9, -35, -6, -30, -37, 44, 3, 29, -9, -5, -4, -11, 44, 12, 5, 15, 5, -4, -4, -11, -64, -7, -18, -31, 15, -21, 21, 12, 43, -14, 46, 24, 16, 48, 20, 5, -6, -9, 16, 36, 16, 0, -5, -15, 14, 32, -3, -6, -2, -3, 29, 29, 34, 16, 59, -6, 15, -13, 8, -2, 33, 28, -17, 50, 22, 53, -4, -54, 7, -13, -12, 31, -3, -43, -37, -55, -44, -21, 45, 40, 22, -11, -32, 4, 33, -39, -22, -11, -54, 20, 46, -13, 21, 42, -41, -15, 48, -34, -30, -1, 15, 20, -69, -53, 38, -62, -32, 3, -25, 7, -34, 22, -20, -48, -51, -45, 15, 33, 1, -26, -17, -6, -9, -19, 10, -34, 32, -36, 0, -16, -42, -24, 31, -19, -42, -16, -50, 41, -28, 25, 24, -59, 18, 36, -55, -9, 26, -36, 12, -21, -32, -1, 15, -16, 16, -15, -32, -21, -52, -42, -36, 18, 42, -49, -25, 46, -34, -60, 33, 16, -19, -20, -9, 52, -26, -2, 10, 15, -14, 34, -20, 30, -5, -30, 35, 2, -39, -27, 15, 21, 13, -15, 9, 12, -19, -23, -33, 5, 20, -38, -3, 54, -19, -31, 33, -34, 12, -18, -8, 46, -22, 47, 1, 3, -21, 15, 15, -14, -24, -21, -9, 21, -20, -34, -4, 32, -26, -15, 22, 8, 4, 31, 13, 35, 40, 40, -27, 49, -40, -17, 31, -41, 26, -8, 16, 26, -19, 2, -48, 18, 16, -7, 3, -43, -7, -42, -32, -23, -15, -11, -6, -7, 26, -4, 23, 19, 31, -30, -7, -16, 4, -18, -67, 30, -31, 1, 4, -8, -34, -7, 5, 30, 28, -7, -53, -30, 22, -3, 19, 39, 27, 48, 34, 18, 22, 9, -10, -18, 9, -42, 17, 27, 6, 24, -7, 39, 16, -7, 26, -49, 9, -35, 8, -1, 17, 1, -26, 12, 12, 12, 20, 5, 32, 53, -31, 13, -2, 5, 20, -29, 36, 3, 55, -4, -25, 55, 16, -29, 46, -7, -3, 4, 44, 46, 55, 13, -3, 3, 5, -34, -2, -44, -20, -33, -59, -37, 13, -57, 29, 39, -14, 41, -35, -22, 16, -3, -1, -41, 21, -6, -48, 73, -20, -35, -2, -41, -16, -32, 1, -27, 61, 54, -28, 62, 18, -18, -31, -55, -30, 31, 44, -11, -47, -45, 23, -52, -21, 48, 33, 59, 46, 6, -29, -50, -22, -72, 53, 11, -57, -1, -4, 15, 2, -30, -53, -43, -4, -3, 14, 43, 15, -13, -31, -29, 13, 8, 23, -2, -8, -6, -2, 39, 63, 17, 41, 43, 49, 9, -23, 22, -38, 37, 16, -6, 38, 37, 44, -10, 44, -15, -17, -44, -51, -30, 39, -14, 5, 32, -39, 4, 63, 8, 43, -16, -17, -25, 40, 18, 11, 22, 14, 8, 41, 0, 18, 26, 21, -5, 35, -2, 22, 57, -31, 32, 43, -24, 25, 15, -5, -7, 26, 28, 28, 18, -15, -4, 1, -18, 38, -2, 65, 3, 18, 35, -24, -2, -28, -14, -18, -29, 7, -8, 34, -12, 45, 28, -29, 36, -12, 33, 25, -29, 35, 19, 34, -27, 33, 55, -7, -5, 14, 9, 28, 1, -30, 12, 29, -7, -53, 32, -1, -32, -21, 7, -38, -52, -34, -24, 33, 6, -7, 6, -6, -58, -16, -10, -32, 13, 2, 21, 23, 19, -42, 19, -27, 10, 17, -27, -24, -7, 36, -49, -4, 20, -26, -35, -15, -48, -22, -50, 1, 15, -9, 31, -72, 1, -17, -68, 49, 4, -10, 20, -13, 5, -18, 48, -61, -13, 15, -60, -9, 30, 62, -13, 35, -15, -5, -55, -36, 30, -57, -32, -1, -23, -15, -1, -49, 31, 12, 18, -53, 48, -13, -56, 15, 1, -14, 19, -10, 10, -36, 47, -47, -37, -16, -51, -49, -2, 31, -20, 17, -4, 12, -30, -68, 20, -36, -4, 3, -39, -35, -22, -30, 25, -28, -16, -1, 49, -21, -35, 35, 15, 3, -22, -11, -5, 15, -5, -38, -48, 14, -17, 17, 3, 26, 2, 67, 2, -9, 20, -65, -13, 41, -79, -29, -12, 2, 14, 56, 13, 3, 38, -11, 31, 25, -46, 2, 20, -4, -40, -12, 16, 23, 33, -22, 11, 24, -26, 22, -24, 31, 4, 30, -42, -19, -2, -3, 50, 19, -23, 5, 39, -17, -30, 55, 25, -31, 12, -37, 3, 50, -27, 10, 39, -15, 3, 57, -8, -52, 21, -28, 25, -28, 42, -39, -28, -9, -21, -14, -14, 32, -34, -29, 10, -33, -6, 2, 5, -12, -6, 39, -28, 12, -10, 10, 42, 53, 12, 2, 7, -8, 19, 20, -18, 7, -40, -1, -18, 67, 8, 1, 29, 14, 16, 47, -16, 35, -3, 50, 18, 23, 18, -18, 18, -19, -33, 14, -19, 44, 18, -36, 41, 0, -4, 38, 25, -22, -26, -36, 24, -22, 24, -42, 32, 15, -90, 19, 17, -5, 10, 20, 18, -2, 29, -3, 22, -2, 14, 23, -14, 28, -40, -20, -13, -4, 7, 23, 51, 0, -56, 11, -2, -18, -38, -16, 26, 6, -22, -75, 54, 35, -79, 19, 20, 33, -28, 17, 39, -39, -3, 29, -11, -30, -51, -9, -6, -11, 15, -14, 23, -28, -33, -54, 21, -41, -29, 50, -44, -7, 39, -26, 26, 29, 15, -4, 56, 13, -64, -2, 30, 42, 11, 21, 4, -34, -27, -45, -7, -1, -16, -5, 49, -5, 44, 46, 26, -40, -15, -37, -34, 1, -46, -29, -5, -46, 17, 20, -13, -1, -53, -16, 0, 38, -4, -8, 7, -61, 53, 17, -10, 25, -5, 43, 6, -5, 29, 10, 15, -12, 46, 20, -38, -15, 6, 19, -22, 19, 36, -5, 17, 32, 49, 49, 4, 3, 24, 3, -29, 19, 4, 13, -6, 23, 46, 11, 30, 37, -22, 63, -29, -62, 68, 20, -77, 11, -46, -39, -43, -12, -23, 57, 23, -56, 40, -18, -25, -14, -31, -28, -45, 2, 32, 33, -10, 2, 20, 10, -12, 18, -28, -16, 21, -6, -35, -9, 43, -41, -37, 49, -8, -36, -39, 19, -2, 27, 19, -38, 38, -8, -73, 32, -26, 41, -10, 53, 24, 8, -16, -48, 30, 11, -48, -19, 26, -13, 7, 29, 14, -1, -13, -10, 40, -28, -19, 19, -54, -33, -42, 9, -31, -14, -6, -17, 5, 42, -49, 32, 2, -6, 7, 51, 14, -2, 15, -46, 13, 1, -11, 4, 28, -5, 3, 44, -14, -23, -23, -4, -30, -40, -25, -7, -35, -33, -22, -7, -32, 34, -29, -35, 2, -4, 24, 10, 4, -28, -48, 26, 2, 39, -34, 8, 27, -5, -7, 29, -5, -3, 32, 49, -3, 20, -13, 17, 3, 27, -59, 13, 30, -8, 57, 38, -18, -26, 23, -45, -53, -12, -40, -4, 3, 27, 28, 6, 4, -21, 14, 23, -5, -38, 1, 6, -14, -52, -16, -52, -37, 19, 18, 60, 32, 9, 39, 39, 42, -10, 22, -18, -31, 2, 1, 13, -48, 57, -27, 6, 69, -23, 48, 75, -31, -39, -5, -14, -30, 2, -4, -4, 29, 15, -12, 50, -33, 24, -18, -2, 2, -18, -3, -19, -67, -57, -10, -20, -17, 28, -22, 3, 49, 21, 13, 46, -17, 1, -36, -9, 5, 25, 17, -30, -45, -12, -19, -2, 32, -2, 12, 48, -34, -54, -3, 10, -43, -11, 25, -24, 18, -8, 37, -2, -27, -11, -16, 6, -14, -11, 4, -24, -6, -41, 1, -23, -5, -11, -39, 69, 9, -11, 16, -32, -2, -50, -3, -38, -6, 6, 6, -21, -26, 43, -17, -15, 63, 0, 48, 40, 33, 11, -2, -10, -35, 18, -6, -12, 35, 10, 49, 59, -19, -31, -49, -23, 11, 31, -22, -14, 6, 20, -23, 36, -25, -10, 22, 43, 26, -29, 56, 4, -10, 22, 25, 24, -7, -18, 27, 21, 41, 35, 33, -10, 8, -25, 31, 35, 34, 15, 27, -45, -25, 42, -18, -10, 31, -12, 47, 42, -21, -25, -9, -6, -3, 4, 1, 17, 8, -16, 8, 6, 4, 10, -54, -12, -6, -9, -34, 8, -15, -51, 28, -12, 31, -21, -47, -47, -20, 34, -22, 20, 53, -10, 32, 32, 8, 41, -23, 20, -59, 3, 22, 18, 28, -18, 43, 37, 1, 30, -14, -4, -45, 4, 2, -9, 47, 26, 13, -22, -21, -8, 12, 2, -27, 16, 34, 28, 25, -8, 6, 33, 1, 40, 49, 92, -33, -14, 33, -29, -56, 35, 20, -24, -61, 44, -4, 33, 28, -27, -6, -18, 7, 5, -27, 5, -43, 24, -17, 18, 22, -21, 15, -4, -52, 38, 5, -18, -34} + +#define TENSOR_CONV2D_1_KERNEL_0_DEC_BITS {8} + +#define TENSOR_CONV2D_1_BIAS_0 {-4, 6, 6, 20, -27, -40, -15, 21, -35, -50, -13, -25, 31, -28, 0, -53, -22, -71, -47, -38, -57, -65, -6, -32} + +#define TENSOR_CONV2D_1_BIAS_0_DEC_BITS {10} + +#define CONV2D_1_BIAS_LSHIFT {4} + +#define CONV2D_1_OUTPUT_RSHIFT {9} + +#define TENSOR_CONV2D_2_KERNEL_0 {-16, -10, -12, 39, 12, 18, 2, 11, -9, 7, 15, -12, -20, 6, -4, 12, -1, -6, 4, -6, 22, -3, -7, 3, 2, -16, 12, -3, 11, 21, -1, 16, -27, -12, 21, 0, -27, 2, 7, -7, -6, -19, 19, 19, 28, 20, 16, 13, 22, -22, 6, 8, -8, -9, 3, -17, -13, -22, 12, -5, 18, 16, -19, -7, -3, -15, 30, 5, 17, 4, 12, -15, 11, -8, -25, 11, 15, 11, 2, -20, 26, -20, 1, -25, -37, 30, -20, -5, -24, -14, -13, 3, 18, 16, -22, 1, -1, 26, -6, -30, 27, 19, 3, 16, 9, -14, 25, 6, -4, -7, 8, 34, -5, -14, -26, 47, -13, -6, -9, -8, 16, 19, -38, -9, -21, -14, -19, -22, 33, -12, 1, -5, 6, 27, -29, 1, -12, -10, 24, 34, -23, 7, -8, 40, -44, 27, -10, -36, 27, 60, -10, -20, 18, -26, -40, 13, -52, -24, 27, 27, -27, -34, -26, 10, -28, 1, -19, -17, -5, 70, 4, -33, 45, 26, 10, 0, 32, -39, -24, 28, -19, -15, 18, -9, -23, -17, -25, 36, -13, -7, 13, 5, 15, 48, -45, 4, 47, 28, 9, -2, -15, -29, -3, 7, -7, -24, -28, 14, -15, -10, -13, -32, -18, -12, -4, 4, 11, -6, 14, -23, 29, 21, -40, 38, -27, -28, -24, -15, -12, 11, -38, -34, -25, -26, 5, -5, -44, -52, -5, -21, -14, 20, 9, -9, 37, 16, -30, -4, 0, 13, -1, 3, -23, -9, 15, -20, -20, -4, 10, -8, 8, 18, -10, 21, 7, -27, -12, -3, 13, -9, 3, -40, -14, 19, -6, 19, -43, -15, 30, -11, 10, -5, -28, 17, -6, -1, 25, -6, 22, -5, -11, 7, 41, 25, 16, 32, 33, -5, 26, 16, 6, 20, -25, -1, -14, 11, -4, 33, 1, -19, 14, 37, 6, 30, -20, -11, 9, 32, -24, 9, 7, -5, -12, -15, -48, 38, 2, 16, 5, 30, -33, 5, 3, 30, -5, 13, 18, 24, -30, -46, 8, 4, -23, 22, 1, -25, -22, -1, -42, -6, 6, -11, -30, -18, 14, -25, -25, 3, 6, 8, -25, 6, -3, -11, -2, 35, -7, -8, 18, -6, 15, 21, -16, -32, -14, 15, -25, -28, -4, 30, 17, 13, -18, -25, -11, -32, -31, -13, 3, 0, 12, -50, 19, 0, 18, 31, -38, -4, 8, 7, -5, 15, 6, 33, -26, 25, 9, -11, -5, -11, -47, -40, -18, -20, -24, 14, -11, 6, -5, 11, -16, -7, 8, -8, 9, -12, -14, -14, 5, -20, 16, -18, 9, 12, -6, 17, -2, -16, -6, -15, 27, -35, 4, -4, 19, 35, 27, 27, 15, 24, -9, 39, 0, 0, 2, 36, -3, -32, -10, 14, -2, -7, 0, -1, 18, 36, 25, -14, -1, 13, -2, 13, 20, 10, 24, 6, -6, -10, -6, 19, 10, -13, -22, -8, -14, -11, -2, -28, 43, 16, 15, 36, -34, 8, -27, 48, 26, -32, 9, 25, -4, -28, -31, 30, 1, 22, -20, -10, 1, -18, -5, -25, -9, -8, -27, 24, 4, -35, -30, -14, 15, -34, 15, 3, -6, -5, -17, -17, -12, -12, -29, 18, -5, 21, 19, 27, -7, 21, -4, -11, 6, 12, 6, -25, 14, 11, 3, -41, -12, -8, 0, -16, -15, -7, -12, 35, -3, 8, -7, -6, -23, -15, -12, -37, 28, -11, -17, 1, 1, 1, 5, -65, -29, -54, 9, -49, 16, -27, 14, -16, 22, 37, -36, -9, -43, -23, -26, 2, -21, -14, -10, -32, -21, -3, -2, -22, 2, -15, 10, 17, -3, 18, 2, 4, 8, -9, 1, 41, -35, -2, 24, 3, 28, 18, 6, -9, -16, -11, -6, -14, -16, -4, 10, -29, 38, 24, 8, -17, 8, -17, 20, -10, 14, 25, 26, 8, 4, 14, 13, -29, -17, 0, 13, -16, -10, -19, 23, 0, 4, -12, -5, 4, -17, -38, -7, 7, -19, 15, -8, 19, 10, -23, -16, -8, 34, 23, 17, -50, 9, 7, -9, -16, 16, -1, 19, 23, -28, -33, 28, -6, -24, 26, -7, -20, 4, -26, 3, -5, 25, 14, 29, -27, -2, 20, -26, -34, 8, -33, 14, 46, -19, 10, 9, 32, -18, 13, -7, -17, -11, 5, -25, -14, 15, -2, 22, 3, 16, -29, 22, 8, -11, -11, 8, -15, 17, 18, -21, -11, -26, 14, -11, 1, -1, 26, 28, -31, -15, 22, -23, 10, -2, 34, -13, -2, -5, -35, 40, 35, -23, -40, 31, 3, -49, 23, 15, 5, 36, 5, -27, -25, 55, 26, 25, -15, -1, -5, 3, -26, -8, -62, 18, 33, -25, -25, 35, -21, 9, 30, 2, -21, 0, 18, -22, 16, 7, 23, -8, -21, 31, 11, 18, 22, 4, 36, -11, -7, -31, -37, -28, 18, -3, -24, 4, 25, 0, -8, 19, 41, -13, -29, -17, -4, -15, 0, 3, 19, -18, -37, -14, -16, -8, -6, -19, -7, 18, 6, 21, -4, 1, 14, -42, 19, 8, 5, -25, -22, 12, 4, -30, 12, -5, -43, -1, -31, -19, 6, -19, -21, 33, -7, 11, 27, -47, 14, 18, 23, -21, 22, -46, 32, 3, 26, 0, -7, 30, 4, 2, 2, 30, -15, 5, -23, -8, -20, 24, -20, 20, 7, -29, -23, -8, 34, 14, -10, 12, 10, -17, 28, -1, -7, 0, 11, -24, 12, -21, 17, 7, 30, -6, -25, -26, -6, 12, -7, -23, -2, -26, -26, -21, 13, 29, 12, -37, 31, 23, 35, 10, -9, 0, 35, -21, -33, -28, 10, -7, 0, 3, -9, -16, -29, 14, -5, 10, 6, -4, 1, -11, -2, -18, -21, 4, 12, 20, -1, 10, -20, -9, 4, 27, -23, -37, 24, 15, -13, 17, -22, -9, 7, 10, 8, -16, 14, 4, -8, 23, 30, -24, 12, -22, 14, -10, 12, -1, 12, 20, -22, -14, 4, 5, 23, -3, 43, 8, -15, -21, -48, 0, 12, 7, -4, -21, -34, -44, 16, 19, 15, -27, -17, 34, 7, 19, 6, -18, -3, -21, 4, 19, -23, 4, -40, 14, -2, 28, -22, -4, -40, -13, -15, -3, -34, 0, 20, -40, 0, -16, -13, -1, 12, -12, -33, -13, -9, 23, 8, -8, -32, -27, -45, -11, 9, 4, 24, 6, 0, -19, -15, -4, -11, -21, -20, 16, 2, -6, 0, 7, -15, 14, -71, 33, 0, 3, 16, 11, -12, -5, 17, 18, 7, -31, -16, 25, 35, 5, 45, -8, 14, 28, 38, 35, 19, 28, 13, 10, 11, -33, 16, -11, 9, -11, -28, -6, 20, 40, -28, 20, 10, 10, -30, 40, -43, -20, -23, -30, -32, -8, -19, 4, 2, -24, -29, 34, -14, 1, -1, 3, -30, -12, 2, 15, -23, 30, 26, 4, -40, 18, 3, -35, 11, -15, 22, -20, -4, -13, -14, -18, 6, -16, 8, -2, 15, 11, -31, 10, 11, 10, 24, -24, -12, -23, 0, -31, 9, -2, -11, 9, 18, 8, 11, -10, 5, -45, 38, 17, 12, -6, 8, 6, -22, 8, 23, -25, -12, 9, 7, -6, -8, 5, 24, -15, -12, -19, 10, -1, 39, -2, 13, -14, -6, 9, 8, 10, -6, 18, 9, 13, 12, 8, -4, 28, 19, -28, -9, 28, 51, 26, 13, 9, -2, -18, 12, -20, -42, -3, -26, 3, 7, 38, 26, 21, -35, -10, 9, 15, 8, 11, 12, -2, -29, -45, -53, -11, 7, 27, -14, -8, 10, -6, -24, -30, -9, 0, 2, -26, 10, 10, 5, -26, 17, 16, -35, 4, -17, -20, -7, 19, 7, -19, 15, 5, -16, -27, -20, 22, 19, -17, -5, -22, 10, 21, 20, 2, 5, -20, 7, 1, 10, 9, -23, -23, 2, -1, -13, 11, 7, 21, -14, -10, 2, 16, -22, 5, -15, 20, 16, 13, 14, -20, 26, 5, 5, 36, 18, -33, 16, -12, -24, -25, -19, -21, -27, 12, -6, -15, -17, -24, -13, 1, -7, 19, -14, -24, -3, -16, -25, -4, 17, -34, -9, 7, -16, 2, -5, -5, -16, 15, -29, -51, 6, -28, 36, -42, 6, 34, -2, 2, -6, 10, -20, 17, 25, -26, -10, -1, -20, 28, 15, -13, -2, 35, -8, -32, 0, -11, 42, -36, 36, 47, -13, 23, -10, -1, 17, -24, -13, 31, -5, 0, -6, 22, -23, -3, 20, 5, -11, 14, -8, 21, -16, 26, 30, 15, -16, -22, -32, 3, -7, -11, -31, 5, -33, -6, 4, 7, -16, 0, -10, -3, -18, 1, 7, 24, 15, 19, 30, -5, -9, 34, 16, -10, 9, 4, 15, 20, -26, 22, 12, 13, -6, 9, 33, 2, 20, 2, -11, 12, -4, -23, 1, -17, 34, 11, -7, -18, 4, -5, 20, 18, -23, -8, 4, -19, -3, -37, 15, 16, -27, -18, -10, -16, 13, 1, 5, -9, -21, 2, -10, -14, 11, -11, 30, -5, -23, 46, 4, 3, 37, -7, 17, -35, -4, -4, -25, 5, 14, -14, -34, -1, 28, 31, 52, 2, 1, -10, -21, -14, 59, 24, 26, 16, -37, -6, 19, -75, -10, -26, -7, -20, -39, -33, -61, -31, -8, -8, -7, -23, -35, 19, 24, -38, -33, 15, -67, -36, 40, 22, -22, 51, 25, -28, -30, -18, 40, -28, 12, 28, -33, -16, -33, 10, -2, -33, 22, 13, -41, 29, -21, -9, 42, -29, 17, 5, 2, 12, 24, -18, 20, 55, 38, -23, -11, -27, -15, -36, 2, -26, 5, 22, -10, 35, -9, 16, 35, -51, -18, -21, 23, 27, 6, -2, 40, 9, 24, 25, -2, -39, -22, 0, -2, 26, 10, -15, -39, -6, -38, -7, -13, -28, 12, 40, 10, 6, -1, -23, 25, -23, 11, -3, 23, -14, -30, 6, -30, 7, 5, -27, -35, -40, -41, 2, -7, -12, -5, 40, -25, -27, 2, -19, 18, 2, 8, 38, -15, -7, 3, -17, 16, 35, 24, -31, -20, -28, 3, -33, -11, 12, -26, -8, -2, 21, 8, 20, 16, 1, -30, 30, -1, 3, -42, 28, 8, -18, -5, 25, -31, 13, -10, 1, -11, 0, -16, 15, -12, 8, 32, 21, -25, 8, 10, -2, 5, -22, -14, -26, -10, -20, -3, -10, -49, 21, -19, -20, 21, 5, -7, 23, -12, 7, 7, -12, 35, 4, -4, 0, 10, 32, 13, -7, 2, 9, -7, -14, -8, 40, -2, 20, -1, -2, -10, 15, 9, 17, -4, -26, 18, 2, -13, 1, 21, -4, 12, 7, 12, -19, 6, -5, 43, -38, 11, 1, -9, 0, 7, -16, -41, -21, -15, 3, -26, -13, -27, 0, 18, -5, 5, 42, -4, 13, 2, -1, 34, -28, 17, -3, -3, -5, -8, 3, -39, -16, 0, -15, -13, 10, -5, 18, 3, 20, 28, -20, -2, 27, 1, -28, 32, 5, -28, 14, -31, 17, -6, 4, -28, 4, -17, -3, -10, 0, -34, -8, 5, -17, -33, -23, 8, -3, -10, 14, 1, -5, -14, 19, 13, 1, 1, 21, 9, -11, 19, -4, 25, 32, 30, 32, 39, -9, -38, 12, 17, 10, -14, 5, -41, -20, 1, -5, 37, 23, -18, 44, -13, 43, 40, 9, 36, 46, 10, 37, 14, 13, -7, 50, 29, -27, -20, 12, -28, -1, 14, -11, -5, 4, -8, 28, -25, 33, 19, 3, 6, 22, 20, 23, -22, 4, 19, -25, -23, -31, 23, 2, 33, -22, -4, -2, 1, -9, -13, -17, 23, -34, -21, -8, -18, 20, -21, -34, -28, 3, -36, 21, 11, -70, -33, 25, -33, -6, -6, -18, 8, 34, -7, -29, -12, 31, -30, 26, -51, -7, 2, -34, 6, -17, -29, -10, 13, -26, -42, -6, -6, -17, 1, -15, -1, -2, -4, 40, 17, 32, 23, -21, -9, -1, -8, -3, -10, -4, 5, -13, 8, -21, -8, 19, 29, 44, 40, 17, 4, 6, 6, -54, 23, 6, 5, -19, -18, 17, -36, -42, 30, -11, 33, -42, 3, -37, -5, -8, 21, 40, -5, -6, 18, -49, 21, -48, 45, -27, -29, -35, 8, -17, -22, -14, 3, -15, 22, -1, 9, 29, 2, -22, 11, -6, -27, 3, 33, -9, -2, -23, 32, -3, -30, -19, -14, -25, 25, -3, -13, -23, 8, 34, 16, 25, 0, 0, 38, -1, 13, -14, -8, -19, -3, -8, -21, 37, -9, 29, -17, 3, -25, -17, -25, -28, -19, -30, 5, 25, 7, -16, 1, -12, -13, 14, -8, -19, 11, 30, -18, 11, 11, -20, 3, 11, 8, 24, 6, -31, -20, -16, -28, -13, -6, -14, -41, -26, -38, -45, -20, -12, -29, -5, -29, -33, -7, -43, -23, -3, -36, -22, -49, -27, -3, 8, 35, -41, -1, 25, -18, 33, -30, -28, 46, -8, -50, -16, -1, 25, -29, -18, -3, 15, -1, -4, -15, 16, 7, 9, 44, 22, -4, 29, -10, 18, -2, 35, 52, 2, -16, 15, 36, 50, -2, 29, 15, 59, 73, 28, -4, -6, -24, -19, 18, -12, -3, 16, -28, -18, -27, 12, 20, -1, 0, 28, -7, 11, -10, 22, -11, 15, 21, 1, 22, -30, -14, -4, 3, 3, -13, -5, -11, 19, 15, -23, 34, 27, 27, -3, -7, -7, -17, -3, 31, 15, -3, 18, 15, -6, -28, 23, 25, 21, 6, 10, 7, 15, 14, 20, 7, -12, 23, 24, 18, -11, -21, -8, 13, 36, 22, 26, 12, 15, -38, 3, -8, -12, -4, -10, -23, 7, 2, -1, 21, -40, 0, 18, 11, 23, -3, -16, 3, -15, 30, -12, -24, -31, -3, 7, -21, -3, -2, -5, -11, 4, -10, -3, -3, -39, -10, 11, 12, -11, -3, -5, -25, -26, 5, 8, 17, -31, -8, 15, -21, -12, -18, -1, -13, 5, -35, -26, 24, 2, -38, 6, 5, -27, 8, 18, -6, 22, -24, -12, -33, 16, -18, 10, 4, -29, 1, 8, -1, -31, -3, 14, -3, 24, -18, 3, -8, 29, -17, 8, -12, 1, 18, -4, -16, -26, -4, -2, -16, 11, 35, 1, 47, 17, -21, -21, -8, -15, -3, -1, -19, -4, -39, 23, -10, -13, -4, 7, 19, 16, -40, 18, -27, 3, 21, 24, 15, -36, -6, 7, -10, 5, -15, 28, 9, -11, -35, 16, -32, -14, 7, 20, -12, 31, -37, 15, -3, -23, -29, 0, -39, 15, 31, 23, -27, -4, 15, 15, -3, 25, -22, 19, -30, -2, -26, -3, 14, 9, 2, 3, -29, 39, -11, -21, -20, -16, -4, 21, 29, -33, 25, 19, 35, 0, 3, -14, 17, 32, 48, 44, -4, -8, 7, 14, -4, -5, -17, -9, 15, -5, 13, 20, -5, -6, 28, 2, -23, -12, -9, 10, -20, 10, 19, 22, -20, -14, 13, 28, 18, -45, 1, 12, 16, -22, 12, 9, -45, 21, -22, -24, -32, -18, -7, -14, -40, -10, -6, 2, -24, 33, -19, -10, -14, -30, -28, 32, -39, -31, -7, 12, 23, 27, 11, -42, 6, 20, -4, 29, -9, 31, 12, -24, -19, 43, -16, 33, 13, 6, -7, -3, 22, -32, 42, -8, 10, 5, -27, -6, -12, 40, 21, 28, -2, 22, 28, 14, 22, -24, -10, -1, 12, -9, 19, -5, 15, -45, -26, 1, -26, 14, -12, 28, -37, 11, 5, 13, -31, 13, 4, -6, -32, 10, -13, 0, -35, -1, -39, 12, -19, 31, -4, 13, 26, -6, 18, -29, 6, -44, -33, -3, 1, 2, -3, -39, 42, 0, 2, 25, 20, -30, -27, 23, 14, 30, 16, 9, -14, -17, 7, -3, -1, 9, 4, -10, -19, 3, 2, -35, 30, -33, -4, 2, 0, -9, 10, -16, 3, -27, -18, 23, -6, 13, 29, 3, 20, -14, 3, 5, 24, -3, -21, 23, -11, -32, 14, 0, -15, 23, 8, 14, 15, 1, -9, -19, -31, -13, 20, -5, 4, -19, -4, 8, 9, -18, 39, 19, -11, -22, -13, -11, 1, 33, 33, -35, 19, -30, -34, -17, -8, -34, -22, 31, -20, 1, 16, -29, 2, -8, 7, 18, 5, -15, -25, 6, -8, 32, 17, -9, -15, 2, -14, 0, 4, -10, 6, 18, -12, -16, -21, 14, 7, -3, 13, 25, 23, 15, 8, 35, 29, -24, 0, 20, -19, 22, 11, 9, -26, -10, -39, -39, -31, -8, -4, 3, -9, 16, -11, -7, 0, 12, 8, -17, -1, -26, 30, 3, 1, -12, -2, -20, 37, -11, -23, 18, -16, -33, 7, 27, 21, 24, 29, -14, -6, 26, -21, -19, -30, -8, -24, 34, -51, -23, 28, 3, 20, 1, -15, 16, 3, -11, -6, -6, 7, 25, 11, 2, 18, 4, 62, -13, -25, 2, -2, -27, 62, 24, -15, -15, -6, 19, -13, -42, 7, -5, -54, -11, 42, -35, -20, -50, 0, 32, 13, 8, -20, -3, 23, -14, 46, -4, -20, -2, 11, 12, 8, -30, 21, -41, -29, -7, -17, -15, -62, -31, -5, 14, 22, -19, -15, -3, -28, 22, -33, 6, 21, -15, -6, -23, -2, 16, -8, 1, -33, -11, -6, -28, -15, -25, 21, -16, -32, 17, 6, 21, 36, -35, 30, -27, -8, -28, -14, -17, 37, -17, -3, -2, 12, -30, 42, 8, -18, 10, 11, -23, -50, -29, -36, 54, 29, -18, -18, -4, 3, 5, -9, -9, 15, -8, -9, -22, 6, -47, 51, -11, -26, 3, 33, -21, 17, -1, -37, 47, 4, -26, -24, -10, -3, -4, 11, -13, 37, 26, -10, -36, -42, 8, 17, 6, -18, 7, 34, -25, 11, 1, 21, 26, 20, 18, -20, 33, -32, -22, 4, -42, -27, 17, 29, -24, 19, -17, 34, -4, -13, 9, -2, -4, 16, 1, -33, 29, 55, -27, 9, 31, -35, -10, 23, -31, 0, 2, -12, -5, -14, 28, 32, 4, 17, -12, -13, 27, -28, 42, -15, -8, -23, 14, 27, 17, 17, 16, -6, 29, 1, -18, -22, -10, 12, 24, -15, -4, -40, -26, 11, -1, -5, 33, 23, 7, 3, -9, 7, 1, 7, -6, -1, 19, -15, -7, -19, 10, -22, 33, 20, 21, 27, 4, 8, 26, -25, -3, -38, -14, -41, -19, -10, -40, -10, -3, 11, 0, 24, 9, -17, -14, -26, 14, -2, -8, 9, -8, -8, -3, -5, -14, 17, -4, -34, -5, 10, 24, 44, 20, -41, -11, 4, -34, -7, 1, 41, -9, -22, -7, 19, 7, -2, -24, 14, 23, -1, -13, -1, 1, 34, 24, -29, 10, -13, 0, -35, -23, -19, -18, -14, -6, 1, -1, -9, -20, -15, -17, -4, 22, 23, -33, -1, -9, 13, 34, -15, -6, 6, -25, -13, -9, 29, -9, 22, 15, 28, 42, 20, 5, -11, 0, 38, 17, -15, -48, 3, -4, -18, 27, -13, 0, -6, 1, 16, -16, -4, 18, -22, -20, 33, -2, -27, 5, 5, -27, -26, -10, -35, 16, 36, -15, 27, -24, -16, -18, -11, -47, 10, 31, -11, -40, -26, -10, 3, -29, 4, 15, 15, -41, 20, -5, -28, 36, 56, 0, -26, 0, -15, -5, -1, -11, 6, 38, 2, -31, 13, -23, 8, -29, 10, 28, 13, -8, 3, -18, 4, 42, 37, -17, -22, -10, -39, -14, -2, -36, -18, -5, 4, -3, 22, -9, 9, 1, 11, 15, -26, 22, 21, 15, 21, 5, -4, 1, -6, -4, -14, 20, 2, -19, 8, -43, 16, -4, -15, 2, -1, -20, 7, -12, 17, 10, -36, -10, 9, 19, -7, -12, -37, -19, 1, 28, 19, 11, 16, 29, 1, 9, -13, -10, 4, 26, 9, 29, -1, 6, -28, -21, -17, -3, 15, 20, 3, -10, -16, 33, -5, -8, -1, 45, 28, -12, 6, 11, 3, 31, 22, 11, 11, -5, -4, 24, 17, -8, -41, 22, -22, -32, 20, 34, -21, 51, 9, 0, -4, 13, 21, 16, 8, -4, 3, 3, 4, 12, -8, 2, 18, -1, 7, -2, 31, 16, 38, 12, -25, 3, 19, 44, -21, 17, -7, -21, -6, 25, 22, 31, -3, -29, 9, 18, 14, -3, 28, -11, 1, 11, -38, -23, 16, -14, -30, -8, 10, -11, -21, -36, 15, -15, -17, -16, -34, 16, -21, 10, -15, -67, -32, 8, -5, 1, 21, 13, 2, 0, -2, -2, -10, 3, -14, -2, -39, -11, 23, 9, -19, 4, -13, 34, 29, -16, -22, 30, 18, -22, 7, 17, 13, 15, -18, 18, 13, -1, 30, -11, 1, 1, 2, 2, -31, -21, -35, -4, -4, 18, 4, 9, 5, -57, -28, -4, -22, 6, -5, 10, -21, 4, -14, 22, -3, -18, 1, -3, -5, -24, -44, -3, 15, -52, -51, 20, 3, -36, 5, -24, -18, 7, 5, -3, -16, 25, 12, -10, -51, 2, -31, -17, -24, 20, -16, 38, -3, -38, -33, 30, -26, -21, 2, 30, 4, 24, -14, 6, -3, 7, 15, 5, -33, 50, -16, -12, -10, 34, -5, 25, -3, -1, -38, 12, -43, 17, 9, -5, -3, 2, 34, -11, 16, 9, -10, -15, -13, 5, 6, -21, 23, -15, 7, -1, 14, 6, -17, -6, 23, -2, 9, 10, -6, 24, 1, -17, -11, -14, -2, -1, 20, -14, -19, -7, 20, -5, 9, -7, 19, -23, 0, 13, 7, 11, 22, 18, 2, -13, 22, -54, 8, -12, -19, 12, 1, -6, -24, -19, 25, 38, 11, 18, -6, -7, -50, 8, -6, -26, 9, 27, -4, 36, 11, -15, -21, 16, 18, 15, -31, 12, -16, -30, 14, 10, 17, 5, 1, 29, -1, -28, 34, 27, -21, 15, 17, -8, 9, 7, 13, -9, 8, 26, 3, -13, 6, -15, 2, -4, 17, 26, -6, -11, -26, 4, -29, -17, 4, 16, -4, 7, 13, -50, 19, 25, -27, 16, -26, 15, -8, -22, 3, 2, -35, 16, -7, -1, -22, 1, 19, 12, 34, 4, -4, -23, -8, -43, 8, 25, 23, -1, 9, -3, 20, -15, 24, 30, -6, -20, 9, 7, 37, 0, -1, 27, -18, -21, 35, -6, -29, -11, -2, 4, -17, -8, -22, -23, -26, -22, 16, -24, 12, -31, -13, -21, -16, 17, 9, 25, -7, 19, -22, -1, 21, -24, 8, -8, -16, -31, -25, 8, -24, -2, 22, -25, -31, -14, 3, 1, 30, -5, -36, 28, -9, -35, 1, 12, -4, -4, 38, 9, 0, 15, 15, 23, -11, -17, 20, -17, 18, 5, -11, -4, 0, -24, -5, 35, -18, -40, 18, -21, -40, -5, 19, -36, -22, 21, 12, -7, -1, -24, -29, -29, 33, 28, -34, -17, -1, -10, -3, 11, -20, 9, 1, 2, -8, -27, -5, -24, -30, 8, 6, 10, 0, -28, 11, 16, -39, 26, 41, -40, -18, 23, -16, -14, 43, -17, -1, -5, -28, -13, -11, 27, 25, 28, -5, 4, 22, -6, 8, -15, -48, -21, -13, 2, 29, -24, -16, -30, -24, -27, -33, -17, 23, -14, -32, -36, -4, 6, -8, 7, -16, 19, -8, -3, -9, -20, -23, 34, 32, -5, -39, -15, -1, -21, 3, -19, -14, 29, 5, -10, -4, -18, -20, 0, 1, -6, -11, -1, -17, 39, 11, -9, 8, 15, -10, -22, 17, -9, 25, 26, -18, -22, 10, 40, -8, 41, -22, 38, 9, 19, 25, 3, 45, -23, -3, -1, 9, -20, 36, 48, -4, -12, -21, -34, 37, -5, 20, -19, -24, -15, 14, 0, 11, -10, 11, -7, 17, 15, -2, 22, -6, -27, -14, 23, -24, 0, -4, 14, 16, -19, -9, -16, -29, -5, 25, -31, 1, -2, 7, -2, 34, 17, 0, -19, -43, 6, 15, -19, 21, 16, -29, 16, 8, -42, -22, 16, -35, -20, -43, -5, -17, -12, 21, -8, -2, 43, 53, -26, -58, 4, -5, -2, 18, -12, -11, 38, -41, -4, -12, 46, -6, 32, -51, -10, -18, -19, -9, 1, -6, 17, 1, 24, 9, 21, 32, 13, 1, 17, 1, 12, 33, 7, 12, -9, -15, 7, -15, 12, -25, -9, 9, 7, 36, -16, -4, -9, -10, -11, 41, 14, -10, -8, -14, -26, -28, -3, -26, -3, 0, -17, -24, -9, -23, -25, -13, -35, 2, -3, -14, 48, 25, -1, 35, -40, -36, -26, 1, 4, -22, 39, -33, -31, -18, 10, -5, 17, -27, -3, -12, -32, 2, -27, 3, -3, 13, -14, 5, -9, -1, -20, 31, 10, 0, -18, 8, -14, -1, -4, -22, 27, 13, 11, -13, 19, 39, 6, 27, 5, -26, 9, 15, 20, 3, -16, 9, 15, 3, -3, -8, 25, 1, -15, -9, 14, -3, -3, -8, -24, -3, 23, 6, -16, -13, -18, -5, -3, 1, -17, 6, 0, 27, 28, 21, 5, 8, -27, 34, -6, 19, 18, 31, -27, -28, -8, 9, 5, -5, 11, -51, -26, 17, 4, -9, 3, 3, 2, -5, -17, 16, 17, 40, -4, 27, 31, 17, 7, -22, 0, -19, -4, 22, 20, -13, -37, 13, 5, -17, -8, 25, -2, -27, 4, -10, 0, 8, -15, 5, 10, -21, 0, -11, 1, -24, -54, -37, 30, -45, 43, -5, 9, 23, -14, -32, 22, 8, 8, 0, 26, 8, -7, 7, -28, 15, -8, -33, -13, 1, -28, -22, 31, -71, 39, -13, 25, 11, -10, -11, 16, 49, -2, 17, 8, 44, 50, 0, 2, 26, 3, -25, 5, -9, -15, -31, -8, -7, 18, -1, 12, -11, -53, 16, 15, 9, 20, 17, 16, 30, -4, 6, -3, 27, -35, -18, -17, 21, -14, -11, -25, 45, 6, -2, -24, -3, 19, -42, -10, -24, -18, -14, 10, -38, 6, -43, -37, -36, 7, -25, 22, 9, 0, 14, -4, -9, -2, 9, -3, -12, 33, -32, -8, 12, 26, 19, 24, -12, -14, -20, -24, -29, -13, -5, -9, 27, -34, -28, 2, 21, -25, -16, 1, -29, -5, -10, -22, -35, 35, -16, -1, -11, -13, -9, -11, -17, 17, 30, 35, 29, 24, -1, 2, 20, -6, 2, 3, -24, 20, 9, 22, -15, 7, 7, 11, 0, -33, -8, -1, 22, 18, 35, -1, -10, -15, 12, -13, 11, -11, -16, 28, -7, 0, 8, 25, 15, 22, -14, -26, 21, 0, -19, -10, 14, 24, 49, 4, 22, 9, -32, 17, 38, 2, 16, -2, 18, 15, 7, -46, -5, -19, -15, 10, -28, 6, -4, -35, 13, 3, 40, 15, 0, -32, -4, -3, 26, -40, -11, 23, -26, 33, -6, 14, -12, 10, 14, 23, -38, 1, 9, -26, 10, -15, 2, 19, 33, -6, 3, -17, -21, -33, 26, 14, -44, 13, 6, 16, -30, 32, 6, 1, -21, -5, -23, 24, -27, -23, -22, 23, 7, 18, 7, -5, 39, -17, 22, 24, 14, 47, -7, -3, -22, 39, 7, 27, -11, 7, 8, -7, 6, 21, -5, -16, 18, 6, 25, 8, -5, -45, 2, -14, -9, 7, 1, -16, -40, 20, 10, 6, -52, -8, -26, 17, -26, -9, -3, 14, 21, -16, 6, 28, 1, -24, 26, 2, -11, -35, -23, -15, -43, 32, 5, -20, -37, 23, 15, -6, -30, -5, -14, -25, -8, 22, 19, -15, -6, -27, 2, -19, -22, -4, -20, -2, -23, -27, -13, -25, -10, 0, -13, 4, 16, 1, -32, -34, -13, 13, -4, 8, 6, 4, -6, 11, 8, -44, 27, -2, 15, -22, 18, 4, 10, -22, -3, 5, 17, -24, -53, -40, -14, 1, 4, -7, -21, 5, -23, 20, -10, -46, 0, 5, 38, -13, 11, -19, 41, 12, 35, 0, 20, 28, -7, -23, -6, 11, 21, 14, -9, 10, 9, 3, -11, -22, 24, -12, 26, -12, 9, 4, 24, -14, 23, 23, 19, 8, 28, 33, 6, -20, -3, 8, 0, 29, -10, 0, 26, -15, 15, -5, 8, -3, -19, -18, -13, 28, 22, -2, 25, 1, 28, -16, -4, -6, 7, -16, -23, 23, 4, -11, 22, -35, -28, 5, 39, 29, -14, 18, 41, 23, -4, -4, -18, 8, 8, -39, 3, -24, 12, 6, -21, 7, 14, -31, -9, -1, -1, -3, 17, -30, 19, 22, -8, -11, 28, 7, 9, -27, -5, -19, 1, 19, 18, 15, -31, -41, -18, 0, -13, -11, 3, 37, -4, -19, 13, 20, -14, 13, 7, 9, -25, 12, -28, 8, -6, -16, 11, -9, -3, -49, -4, -16, 2, 0, -14, -22, 5, 0, -9, 32, 5, 2, 1, -6, -2, 20, -21, -4, 23, -7, -29, 19, -12, -27, 14, -7, -47, 32, -1, 3, -19, -7, -1, 7, -5, 23, 0, -2, 7, 13, 33, -12, -27, 35, 9, -3, 39, -19, -28, -14, 2, 6, 12, 0, 19, -39, -31, 13, 2, -17, -1, -13, -1, 4, -3, 8, 27, -19, 4, 30, 2, -4, 35, 16, -23, -11, -7, -28, -14, 6, 1, 36, -30, -1, -8, -7, 22, 25, -14, -8, 43, -18, -40, 10, 5, -12, 41, 27, -29, -24, 3, -17, -12, 1, 34, 10, -23, 30, -7, 26, 31, 0, -12, -13, -1, 53, 43, 5, 23, -9, -22, -16, -3, -13, 34, 25, -22, -24, -32, -33, 9, 0, -34, 20, 30, 27, 0, -32, -31, 34, -6, -4, -21, 23, 3, 30, -2, -20, -15, 12, -11, -35, -3, -6, 15, -7, -35, 10, 24, -9, 12, -44, -32, -9, 1, 18, 1, -11, 4, -3, 1, -31, 25, -12, 9, -8, -25, -2, -7, 12, -8, 19, 27, -1, 25, -12, -7, -25, -16, 3, -13, -2, 9, -6, 8, 26, -7, -13, 16, -13, -41, 0, 34, -9, -20, -30, 14, -19, 21, -2, -34, 5, -15, -18, 26, 12, 22, -19, -16, -17, -4, -43, 18, 12, -15, 13, -4, -38, -10, -10, -17, 21, 22, 27, 5, -39, -37, -8, 18, -7, 23, 19, 13, 49, -14, -29, -3, 7, -21, 26, -11, 8, 7, -36, -10, -26, -2, 41, 48, 11, 30, 8, 9, -43, -27, -27, 21, 31, -25, 20, -29, -7, 16, 7, -23, -12, -25, -3, -7, 3, -29, -2, -19, -12, -2, -14, -21, -8, -6, 17, 11, 11, -9, -9, -13, -9, -8, 5, -7, 1, 6, -6, 25, -16, -6, 3, 20, -36, -12, 18, -28, -14, 19, 17, 0, 12, 0, -2, 9, 38, 6, 24, -24, 5, 43, 24, 2, 11, -30, -12, -17, 32, -5, -14, -43, 27, -23, -24, 36, -18, 31, 8, 1, 4, -32, 0, 34, 8, -31, -15, -4, 22, -31, -33, -38, -24, -2, -6, -14, 6, 10, 24, -19, -20, -17, -5, 6, 9, -23, -18, 11, 22, -7, -36, -8, 27, -35, -23, 4, -27, -39, -17, -19, 13, 19, 20, -29, 20, -18, -17, -27, -21, -11, -13, 2, 14, 2, -5, -16, 28, 2, 10, 11, 6, 5, 4, -30, -3, 11, 4, 10, 0, -27, 16, -31, 31, -4, 38, -28, 18, -24, 16, 8, 1, 8, 35, 52, -19, -15, 6, 11, 0, -8, -9, 20, 2, -15, -10, -38, 46, 15, 32, -8, 30, -14, 2, -29, 24, -16, -2, 2, -31, -15, 2, -8, -19, -11, -11, -37, 16, -10, -28, -27, 19, 25, 19, -51, 7, -6, -21, -14, 5, 10, -9, -2, -20, -8, 2, 24, 12, 31, 2, -30, 24, -21, 2, 19, 35, -1, 2, 7, -15, -4, 24, 17, -7, -27, 14, 45, -22, 16, 20, 33, 2, 27, 15, 6, 13, -9, -2, -15, 40, -3, 28, -29, 16, -20, -20, -33, 7, -5, 28, 49, 4, -19, 4, -8, -18, 22, 21, -9, -2, 24, -13, 6, 12, 16, -8, -5, -4, 24, 11, -21, 43, -22, 31, -1, 7, -25, 13, 21, -20, 27, 7, -13, 16, 5, 8, -2, -6, 10, -15, -11, -17, 21, -7, -6, -3, 32, -21, -15, -2, 12, 10, 35, 12, 22, -7, -27, -10, -12, -3, -27, 5, -19, -13, 6, 0, 26, 7, -20, -7, 5, 12, 8, -19, -9, -25, -3, 6, -28, -11, 23, -12, 13, -26, -5, -11, -20, -9, 29, -20, -10, -33, 1, 4, 3, -22, 20, 6, 12, 5, 27, 12, 18, 2, -2, 18, -11, -27, 14, -3, 6, 21, -18, -28, -11, -28, 23, 14, -28, -16, -27, 33, 36, -25, 28, -24, 14, 16, -6, -15, 20, 31, -11, -23, 15, 7, 2, 4, 29, 35, -3, -1, -45, -27, -6, 19, 8, -33, -28, -30, -4, 13, -33, -11, 9, 53, -18, -12, 10, -18, 28, 12, 20, 37, 8, 5, -21, -10, 7, 12, -10, -3, -15, 22, -15, 1, -3, -18, -12, -43, -21, -3, 11, -16, 15, 8, -1, 11, 11, -16, -21, -5, -8, -17, -32, 14, -11, -11, -16, 8, -3, -10, -22, -23, 10, 7, 24, 19, 3, 0, 14, -2, 12, -8, -34, 21, 21, -12, 10, 11, -33, 10, 22, 25, -2, -7, 15, -7, 20, 27, 30, 11, 11, 31, -4, -11, -11, 4, -28, -9, 25, 1, -36, 16, -38, -23, 11, -28, -14, -27, 5, -37, 23, 28, 23, -9, 17, 10, 23, -5, -6, 7, -22, -30, -4, 31, 36, -22, 18, 13, -22, -3, 6, -32, -4, -21, 12, -35, 2, -9, 35, -26, 8, 20, -18, 17, -15, -30, -38, 38, -3, -20, 26, -12, 15, -7, -12, -15, -6, -19, -16, -32, 11, 5, 21, 12, 2, -1, 14, -2, -33, 23, 17, 4, -13, 15, -1, 17, -29, 2, 22, 10, 4, 12, 4, -4, 1, 6, 18, 5, -13, -14, -9, 1, -26, -1, -37, 14, 13, -4, -16, 27, 9, 6, -1, 5, 0, 2, 20, -18, -25, 25, 15, -16, 15, 19, 2, 2, 17, -57, -49, 3, -2, -4, -49, 27, -7, -10, 17, -16, -14, 12, 24, -10, -11, -16, 18, -15, -18, -6, -8, -8, 41, 5, 10, -3, 25, -22, 0, 6, -40, -25, 3, 19, -11, 6, -6, -6, -35, -12, 0, -3, -40, -14, -35, -6, 5, -3, -26, -5, 2, -1, -26, 16, -17, 3, 29, 1, 12, -41, 15, -7, -36, 28, -20, -27, 5, -13, -23, 43, -24, -1, 15, 1, -41, 21, -23, -29, 19, 4, -10, -26, 3, 17, -9, 21, -11, 37, -3, 9, 40, 6, -19, -18, 20, -17, -6, 6, -20, -15, -8, 24, -35, -14, 52, -17, -18, 28, 13, 18, -11, -7, 55, 3, 21, 20, 24, -8, -9, 25, 27, -26, -2, 15, -34, -28, -8, 23, -19, 32, -7, 16, 22, 40, 1, 18, 20, 30, 15, 9, 5, 8, -52, 9, 3, 0, -20, 5, 28, -22, -19, -17, -42, -1, -3, -13, 11, 1, -4, -6, -46, 9, -16, 20, 17, -34, 16, 25, 18, -19, -20, 4, 6, 7, -46, 0, 17, 27, -51, 41, 5, 22, 3, 29, 3, 20, -17, -16, 8, 20, 22, 38, 35, -16, -34, 19, -11, -1, 21, 29, 19, -2, -4, -46, -30, 23, -15, 17, 0, -6, -30, -17, 0, 12, -23, 6, -9, 19, 11, -9, -20, -9, 12, 16, -7, -3, 10, 14, -13, 7, 0, 5, -23, 28, 15, -17, -16, 13, -31, -3, -2, -1, -16, -8, 6, -33, -22, -1, 5, 34, 7, 28, -27, 10, 0, 29, -23, -4, 5, 17, -28, -12, -59, 21, 37, -2, -37, 43, -39, -32, 4, 6, -13, -7, -23, -14, 6, 26, 17, -9, -13, 46, -21, 16, -13, -23, -20, 2, -20, 19, 14, -1, 7, 15, -19, -12, -29, -29, 32, -6, -9, 22, 29, 0, -1, 23, 19, -3, 8, 21, -32, 0, 8, 4, -15, 22, 7, -19, -13, 3, -13, -3, 25, -33, -4, -17, 22, 9, -11, 14, 2, 15, 21, -6, -15, -25, -49, 44, -1, -21, -12, 12, 23, 24, -4, -25, 1, -19, 3, -33, 11, -2, 23, -1, 17, 6, 29, 23, 5, -27, -47, -11, 2, -15, 20, -2, -16, 12, -7, 6, -1, 10, -10, -1, 28, 23, -9, -36, 15, 5, 2, -41, -44, -6, 24, -7, 28, -5, 2, 11, 9, -6, 34, 3, 0, -15, 34, 17, 20, -18, -1, 22, -9, 6, 5, 23, -41, -36, -45, 4, -10, -10, -42, -35, -8, 2, -13, -21, 21, 17, -10, -37, 20, 19, 45, -9, 54, 22, -4, 20, -1, -9, -36, -17, 9, 11, 6, -17, 8, -7, -57, 9, 8, 22, -31, -29, -8, -10, -17, -19, 30, 24, -17, -15, -32, -21, 15, 14, 21, 10, 20, -6, -18, -14, 14, 10, -3, -20, 0, -7, -7, 6, 4, -18, -7, -10, -7, 17, -15, 10, -14, 5, -30, -12, -45, 13, -3, 2, 20, -3, -1, -39, 38, -7, -30, -12, 6, 10, 39, -15, 35, 15, -15, -33, -34, 4, -11, 1, 11, -8, -5, 10, 4, -19, 5, 19, 20, -21, 18, -28, -22, -26, 3, 16, -11, -6, -24, 16, 26, 5, 15, 21, 26, 1, 13, 25, -10, -12, -18, -23, -5, 19, -7, -25, -19, 15, -26, -26, -12, -23, -4, -5, -22, 10, 6, -35, -11, -17, -6, -5, -24, -17, 18, 14, -35, -25, 8, -15, -21, -30, -15, 5, -11, 9, -6, 29, 15, 33, -19, 0, -22, 19, -6, 4, 4, 8, 10, -2, 5, -20, 0, -23, 20, 7, -5, -9, 15, -6, 10, 15, 22, 11, -34, -12, -38, 36, 13, -7, 36, 11, 26, 12, 43, -1, -19, 16, 47, 7, -10, 18, -1, 16, -37, 14, -27, -8, 0, 27, -45, 10, -22, 1, 23, -5, 13, 20, 36, 22, 25, 15, 34, 7, 48, 34, 13, -10, -48, 27, -2, 21, 14, -12, -1, -10, 8, 14, -23, 9, 19, 0, 9, -9, -11, -29, 21, -13, -1, 19, 4, -42, 15, 18, 6, 6, 13, -17, 3, 9, -33, -10, -15, 8, -22, 25, -19, -40, -30, 0, -36, -39, -10, -23, -54, 27, -28, -15, 22, -12, 18, 2, -10, 9, 4, -8, -11, -1, -23, -31, -33, 26, -26, 21, 0, -29, -29, -60, -12, 24, 12, -25, -14, -24, 1, 6, -4, 38, -6, -5, 19, -16, 6, -21, 6, -3, -36, -23, 20, 1, -27, -32, -18, 1, 18, 20, -8, 19, 5, 20, 15, -9, -17, -7, 17, -11, -21, 3, 11, -16, -19, -7, 4, -28, -32, -8, -25, 2, -18, -22, -33, 16, -13, 0, -6, -2, 5, 22, -27, 1, 10, 2, 2, 15, 7, 6, 8, -37, -16, -9, -9, -8, -17, -19, -9, 20, 32, -41, 18, -10, -15, -10, -17, -5, -9, 19, 9, -9, -4, -16, 0, -27, -4, -7, 11, 34, 1, 16, 8, -18, -30, 2, -9, 1, 23, 4, -12, 0, -14, -5, -36, 28, -29, 31, -31, -2, -32, -16, -25, -6, 23, 19, 12, -1, -18, 11, 58, -6, 27, -14, 1, 8, 7, -1, -7, 1, 3, -23, 8, 11, 5, -13, 2, -17, 17, -28, -16, 6, -24, -11, -15, 18, -17, -22, -23, -28, 18, -7, 20, -2, 3, -11, 29, -10, 39, 21, -6, 11, -43, -6, 19, -52, -44, 30, -5, -16, 21, 28, -11, -8, 7, -13, -22, 37, 29, 6, -7, -3, 16, 8, 14, -30, 19, 0, -9, 0, 27, -10, 29, -21, -6, -22, -17, 12, -7, 24, 5, -2, -3, 1, -28, 13, -3, -6, -10, -15, -3, -5, -16, 20, -13, -28, -9, 1, -34, -19, -3, -12, -17, -22, -14, -33, 9, -1, -19, -10, 9, -25, -32, -16, 59, 2, -23, 4, 25, -24, 46, 35, -25, 4, 21, -13, 13, -42, 16, -12, -27, 24, 2, -20, -4, -28, -1, 36, -7, 28, 7, -7, -33, -8, 29, 20, 31, 14, -14, 22, -21, -19, -13, 11, -14, 29, -33, -13, -32, -39, 13, -11, -9, 6, -11, -46, -19, 31, 24, 25, 10, 9, -37, 10, -12, -23, 13, -15, -23, -12, -46, 17, -16, -14, -12, -6, -15, 7, -5, -11, -16, -14, 1, -43, -7, 14, -1, 33, -9, -17, -31, -8, 2, 3, -46, -8, -8, -19, -9, 34, 20, -18, 27, -55, -36, 1, 32, -11, 29, 29, 1, 29, -21, -10, -21, -3, 7, 5, -16, -12, -32, -33, -15, -15, 26, -29, 1, 1, -20, -24, 30, -25, -14, -25, -34, -1, 11, 16, -6, 23, 1, -23, -17, -23, -19, -12, -14, 25, -4, 15, -17, -38, -6, -21, 24, 15, 36, 12, 11, 8, 1, 0, 10, 6, 32, 4, -37, -21, -9, 16, 15, -17, 16, 4, -4, 9, -9, 4, -15, -27, 21, 2, -14, -5, 11, 3, -3, 25, -20, -18, 6, 3, -9, -18, -9, -13, -40, 1, 5, 3, 25, 6, -10, -2, -9, 16, 10, -14, 16, 33, 10, 0, 22, -8, 12, 32, 25, 22, -7, -5, 42, 24, 31, -15, -29, 28, 9, -2, -19, -18, 28, 44, -29, 9, -19, 26, 6, 14, -33, -12, -40, 0, -20, -2, -11, -14, 13, 9, -14, 16, 5, 3, 6, -12, -23, -5, 7, -6, -30, 4, -15, -16, -12, -2, 3, 1, -34, -22, -6, 4, 13, -22, -32, 24, 4, 17, -21, 2, 27, 51, 3, 32, -1, 25, 26, 23, -34, 28, -17, -2, -25, 28, 19, 23, 35, -17, 5, 11, 49, -42, 20, 19, -1, 28, -21, 7, -48, 4, 16, 6, -15, 28, -23, -5, -19, -12, 26, 9, 26, 28, 12, -5, 50, -11, 23, 9, 14, 1, 5, 19, -20, 33, -17, -3, 8, 32, -18, 9, 3, -36, -23, 2, 18, 30, 40, 9, -13, -13, -31, -6, 10, -13, 11, 38, -27, -38, -11, -16, 21, 1, -2, 26, -13, -1, 12, 20, -23, -3, -31, -21, 13, -2, 2, 17, -53, 5, 8, -22, -10, 8, 10, -22, 24, -27, 8, 7, 38, -23, 12, -32, -2, 16, -13, -12, -6, 7, -8, -23, -13, -14, -5, -11, 22, -8, -36, -40, 48, -2, -2, -23, 36, -22, -7, -9, -23, 8, -13, 8, 1, 41, -9, 12, 18, -10, 8, 1, -13, 8, -16, -15, 15, 18, -5, -1, 5, 15, 12, 11, 4, 29, 21, -9, 5, 21, -23, 37, -7, 22, 47, -25, -2, 18, 7, -10, -14, 10, -13, -16, 37, 33, -30, -9, -9, -29, -23, 8, -22, 34, 3, -2, -9, -4, 8, -27, 6, 11, 1, -23, 20, 2, 16, -20, -10, -18, 22, -25, 10, -42, 2, 4, -10, 0, -25, 3, -11, 0, -18, -23, 7, -16, -22, 14, 11, 1, -2, -8, 8, -12, 48, 37, 10, 13, 13, 6, 12, 38, -5, -10, 24, 25, -5, -16, 9, 40, -26, 4, -11, 15, -31, -25, 6, -13, 0, 4, 26, -28, 0, -21, 31, -10, -14, -2, 7, -32, -10, 7, -37, -13, -21, 4, -50, -2, -25, -37, -43, -21, -8, 40, 28, -38, -13, -3, -8, -28, -19, 17, 24, 26, -24, 13, -24, 33, -22, -6, -53, 21, -16, -30, -26, -3, 3, 38, 19, -5, 28, 26, -3, 12, -18, 20, 20, 19, -26, 28, -13, 30, -27, 36, -2, 20, -6, 12, -36, -10, 3, 10, 22, -9, -7, 34, -1, -39, 27, 33, 3, 31, -15, 0, -26, 8, 29, -5, -14, -10, 1, -9, -39, 0, -7, 30, -8, -10, -32, 31, 35, -10, -1, -13, 18, 44, 9, 22, 1, 35, 2, 25, -39, 6, -8, -9, -10, 0, 4, -25, -21, 15, 19, -9, -28, 2, -10, -1, 14, -22, 17, 21, 1, 4, -8, -18, -11, -8, 20, 29, 6, 8, -35, 24, 23, 22, -7, -2, -9, -27, 5, 9, -29, 1, 16, 12, -10, 8, -12, 15, 23, -8, 0, 2, -32, 20, -42, -16, 8, -20, 4, -13, 0, -44, -1, 33, -47, 1, 10, -20, -46, -11, 17, -8, 6, -4, -26, 27, 21, 1, 3, -4, -15, 1, 4, -15, -8, 6, -26, 18, 18, 25, 9, -18, 0, 1, -14, 18, 29, 9, -21, 5, -20, 3, -10, 11, -37, -8, -40, -18, -24, -17, -2, 23, 14, -11, -23, 11, -18, -22, -32, -2, -9, -14, -8, -8, -18, -17, -45, -17, 4, 16, 7, 6, -15, 2, 33, 18, 22, -28, 18, -3, 29, 7, 42, 18, 24, 26, 71, 44, 25, 5, 37, -15, -14, -28, -4, -6, -6, 33, -9, 16, 21, -12, -13, -21, 0, 19, 3, 4, 8, 0, -4, 5, -16, 7, -1, -16, 12, -1, 34, -5, 31, 3, 8, -32, -16, -11, -10, -31, -3, -26, -20, 2, -7, -22, -20, -16, 1, -6, -21, -37, -6, -34, 23, 32, -12, -7, -1, -19, 30, 20, -32, -13, 19, 2, -7, 28, -6, -8, -35, -10, -7, 27, -4, 18, 23, -23, 1, 13, 26, -49, 19, 28, -18, 28, -20, 12, -3, 24, 7, -14, -13, -31, -28, -26, -30, -8, -7, -26, 3, -28, -13, 5, 2, 10, 3, -5, -5, 14, -26, -11, -17, -29, 5, -8, -9, 8, -13, 12, -21, -15, 14, -9, 10, -15, -18, 17, -4, 5, -4, -30, 40, 19, -49, -14, 4, -12, -6, 12, -43, -12, 13, -36, -41, 32, 29, 3, 48, 15, 23, 33, 59, 16, 45, 15, -33, 30, 19, -21, -11, 33, 27, -11, 0, 1, 17, 6, 23, -2, -6, 23, 2, 13, -10, -23, -5, -2, 22, 25, -9, 6, -7, -14, -25, -22, -23, 9, -10, 3, 15, 13, -11, 2, -23, 45, 24, -31, -23, 34, -43, -45, 25, -14, -15, 29, -28, -19, 2, 43, -11, 16, -8, -7, -7, -36, -31, 16, 26, 0, -21, 21, -8, -18, 53, 37, -9, -26, -6, -2, 28, -6, 24, -13, -2, -29, 17, -30, -7, -11, -20, -6, -23, -23, -43, 3, 13, -4, 17, -4, -13, -1, 9, 18, 17, -34, -20, -35, -23, 1, -29, -15, -11, -3, -7, 31, -69, 26, 47, 2, -22, 21, -4, -7, 31, 11, 25, 1, 7, -6, 8, 16, 2, 33, -13, -10, -5, -25, -2, -1, -6, -17, -1, -12, 35, 10, -24, 28, -5, -20, 41, -9, -12, 8, 26, -9, 35, -7, 17, 30, 12, -9, 20, 0, -31, -22, 9, 39, 22, 17, -14, 18, 19, 23, 13, -36, 25, -17, 30, -21, 25, 2, 54, 28, 33, -18, 18, -13, -6, -1, -18, -10, -32, 2, -37, 43, 31, -8, -26, 1, 20, 11, 0, -3, -28, -20, 47, -27, 11, -28, 28, -16, -48, -3, 0, -3, -6, 1, -39, -3, 7, -1, -27, 7, -2, 17, -15, -14, 28, -24, -18, 20, -7, -3, 4, -37, -8, -34, 5, -24, 15, -22, -54, 7, -27, -2, 5, -29, 17, 12, 17, -23, 27, 1, -19, -2, 19, -13, -15, 14, 13, -31, 11, 23, -18, 4, 6, -5, 11, 6, -16, 4, -13, -38, 1, -23, -20, -11, -1, -18, -34, -30, -18, 2, -3, 36, 35, -19, -20, 21, -11, -26, -17, 16, -12, -23, -8, -1, 19, 18, 12, 26, 20, 29, 39, 7, -17, 16, -5, -1, 43, -10, 6, -10, -17, -11, -1, -21, 13, -9, -7, 29, 10, 8, 7, -13, 7, 18, 23, 1, 20, -4, 17, 15, -4, 5, 27, 9, 18, 12, -11, 21, 4, -25, -10, 6, 17, -14, 13, -18, 22, 9, -7, 2, 1, 29, 4, 2, 6, -4, 7, -3, 39, -24, 4, -9, 6, 14, -2, -17, 1, -5, -13, 2, -14, 18, -2, 19, -4, 17, -2, -8, 18, -7, -6, -4, 2, -11, -5, -10, -6, -8, 15, -22, -25, 20, 11, -25, -15, 12, 5, -22, -12, 1, 4, -51, -15, 39, -1, -39, -2, 14, -14, 10, 0, -1, -4, 8, 7, 4, 25, -31, 28, -15, 13, 15, 4, 24, -10, 32, 21, 12, -14, 36, 41, -29, 35, -9, 20, 49, -21, -49, -12, 38, 12, 19, -7, 25, -17, -29, -21, -14, -54, -22, 13, -8, 7, 23, 22, -1, 27, -5, -17, 1, 9, 11, -6, 16, -3, -24, -30, 20, 22, -6, 0, 9, 9, -25, -1, 16, -12, -26, -22, 0, -4, -2, 16, -56, 17, 7, 15, -7, 31, -21, -3, -2, 28, -12, 3, 10, -9, -24, -23, -15, -4, 3, -36, -3, 4, -17, 5, -16, -5, 7, 6, -19, -9, -24, 29, -32, -8, -11, 18, -24, -4, -7, -6, 3, 16, -21, -52, 29, 5, 11, 3, -8, 10, -16, 17, -3, 1, 4, 6, 17, 42, -21, 6, 17, 25, 12, -6, 10, 21, -13, -9, 24, 16, -27, -5, -31, -17, -3, 27, 10, -7, -12, 2, -28, -18, -25, -5, -11, -72, 8, 29, -46, -65, 17, -47, -8, 31, 18, -3, -9, 14, -42, 32, 48, 5, -6, -17, 31, 34, 15, -9, 15, -16, 1, -15, 7, -14, 33, -48, 22, 30, 2, -6, -18, -3, -1, 23, 35, 51, -1, -20, 9, 16, 14, 16, 34, -10, 29, 0, -4, -29, -1, -5, 8, -1, 3, 7, -1, 29, 8, 7, 28, 1, 40, -11, 43, -12, -29, 15, 1, -27, -2, 11, 21, 24, -24, -3, -13, -40, -39, 14, -5, -44, 5, 9, -27, -13, -23, -36, 20, 10, -11, 11, 7, -24, -26, 4, -28, -11, 26, -31, 14, -32, -6, -9, -2, -31, 17, 7, -27, 30, 15, -11, 35, 50, 11, -29, 9, -4, -8, -32, 13, 24, -8, -9, -5, -30, -23, -6, -30, 4, 20, 25, -42, 27, -10, -12, 5, 29, 11, 25, 36, 28, -1, -18, 36, -4, 17, 16, -43, 18, 28, -60, 3, 21, 4, -46, -23, -11, -20, -11, -39, -8, 11, 8, -6, 43, -7, 31, 11, 13, 2, 16, -25, 11, -1, -42, 19, 23, -41, -9, 4, 9, -6, 1, 17, -11, -14, -3, 14, 11, 17, 1, 14, 25, 10, 4, -11, -4, 0, -56, 0, 25, -19, -12, 21, 6, 5, -17, -23, -7, -23, -13, -5, -29, -34, 3, 25, -20, -23, -11, 38, 15, -9, 4, -18, -17, -23, 7, -30, -22, -21, 31, -15, 21, 23, 3, -21, -2, -33, -18, -4, 18, -34, -6, -24, 8, 11, -8, -4, -6, 25, 12, -45, -11, -9, 36, 2, 41, 26, 5, -35, -36, 15, 3, 37, 30, 18, -13, -23, -15, 9, 17, -40, -6, 28, -18, -20, 23, 12, 2, 9, 18, 21, 6, -14, 33, -16, -12, 34, 24, -14, -22, -21, 14, 22, 12, 7, -17, -14, -27, -11, -10, 14, -21, -3, -12, -15, -7, 30, -11, -20, -4, -12, -26, 11, 2, -19, -23, 5, 3, -2, -4, -8, -4, 0, -28, 3, 4, 6, 24, -24, 25, -23, -39, 13, -18, -26, -16, 16, -24, 24, -17, 1, 5, -39, -1, 10, 15, -10, 13, 19, -6, 4, 28, 4, 0, 16, 21, 24, 2, 19, -27, 10, 21, 5, 11, 31, 29, 3, 13, -17, 10, -18, -18, 7, -8, -26, -27, 15, -6, 21, 35, -19, -27, -23, -36, -27, 55, 48, -16, -4, -29, 20, 5, -13, 22, -20, -23, -6, 10, -1, -7, -28, 19, -31, 22, 24, -2, 1, -5, -11, 54, 4, 10, -7, 8, -14, -18, -27, 3, -16, -13, -14, 5, 22, -36, -12, -19, -12, 2, 27, -10, -16, 8, 25, -8, -30, 2, 22, 5, 34, 2, 4, -1, -7, -16, -17, -61, 22, 0, -2, 9, -2, -50, -2, 37, -20, -34, 14, -35, -20, 3, -6, 2, -18, -26, -15, 21, 40, 0, 31, 11, 25, 17, 6, -1, -34, -32, -32, -25, 17, 5, 21, -27, -10, 18, -10, -16, -52, -13, -14, 26, 7, 26, -21, 39, -16, 20, 11, -7, -7, -31, 14, -5, -39, -24, -3, 5, -21, 8, 17, -17, 34, 17, 20, -19, 30, 14, 0, -31, -8, 26, 4, -20, -24, -26, 8, 41, -54, -32, 7, -7, -5, 8, 22, -31, 11, 8, 12, -5, 10, -1, 26, -41, 24, 0, -9, 11, 6, 17, -26, -14, 16, 10, -29, -7, 20, -29, -2, -18, -4, -7, 24, -18, -29, -15, 19, -13, -31, -27, 23, -14, 31, -28, -8, -1, -42, -4, 16, 3, -22, 17, 4, -30, 7, 23, 18, -8, 40, 31, -14, 1, 1, -9, -1, 0, 3, -36, 34, 41, 9, 11, -16, 51, -13, -8, 13, -1, -8, -18, -17, -25, 33, -4, 36, -10, 8, -17, 20, -23, 44, 16, 19, 25, 9, 9, 31, 22, -4, 17, 27, -8, 27, -14, -12, -28, 3, -22, -1, -30, 16, 26, 14, 8, -23, 4, 17, -2, -39, 2, 11, 23, -11, -17, -11, -12, 10, 10, -38, -2, 11, 6, -16, -37, -21, -11, -30, -28, 17, 0, -31, -32, 1, 19, -22, 40, 20, -39, -35, -15, 11, -14, 4, -8, -40, -3, -10, -2, -31, -8, -10, -29, -23, -23, 45, 8, -50, -9, 23, -26, 8, 9, 14, 38, 42, -22, -21, -20, 41, 14, 27, -18, 27, -11, -23, -1, -16, 10, -18, -15, 33, 22, -25, 37, 24, 2, 14, 9, -40, 36, 26, 8, -8, -5, -31, 11, -31, 1, 28, 38, 3, -14, -32, -26, 31, 6, -27, 19, -22, 9, -9, -5, -42, 20, 7, -5, -45, -6, -30, 36, -24, -15, 23, 14, -16, 17, -27, 10, 38, 32, -6, 15, 12, 19, 2, -9, -5, -14, 32, -8, -34, -8, -32, -4, -9, -18, 37, 4, 15, 20, -10, -7, 9, 11, -29, -9, 16, -4, -24, -1, -40, -22, -20, 10, 3, -25, -16, 26, -10, 17, -17, -16, 2, 35, -3, -35, -15, -14, -7, 5, 18, -12, -25, 15, -18, 1, -5, -7, 13, -25, 14, -10, 11, -2, -10, 12, 15, -18, -4, -12, 12, -16, -24, 3, 28, 9, -22, 19, -22, 1, 18, 12, -30, -18, 17, 32, 4, -3, 18, 28, 14, -3, -22, -20, 7, 27, -27, 52, -19, -20, -17, -28, 23, 20, -23, -47, -41, -26, 3, -8, -5, -3, 20, -30, -10, -8, 10, -5, 13, 27, -12, 39, -4, 14, 19, -13, 27, -16, -12, 7, -2, -6, 25, 20, -34, -14, 9, 8, 10, 5, 27, 30, 25, 12, 7, 33, 24, -4, -1, -27, 25, 22, 17, 19, -4, 3, -8, -10, -17, 21, 17, -6, 26, 23, 5, 36, -12, -38, -11, 36, -26, 5, 19, -21, 2, 25, -58, -24, 27, 12, -19, -7, 9, -36, -4, -15, 6, 39, 1, -32, 15, -7, -9, 28, 9, 18, -3, -24, 6, -6, -56, -2, -5, -11, -5, 26, 8, 20, -28, -1, -15, 39, 14, -9, -28, -43, -13, 4, -2, 26, 3, -29, -31, 11, 10, -18, -11, -13, -19, -14, -9, -25, 1, 2, -40, -54, -17, 16, 25, 8, 9, 16, 13, 21, -10, -4, -37, -11, 17, 28, 14, 29, -25, -1, 14, 16, 12, 5, 13, 1, -36, -34, 17, 44, -8, -17, 17, -30, -18, 17, -52, 28, 14, 0, -25, -23, 16, 11, -3, 21, 33, 19, 9, 26, 1, -25, 10, 21, -10, -5, 2, 19, 20, -34, -24, -1, 9, -37, -7, -24, 4, -31, -18, -22, 19, 4, 5, -18, 17, 12, -17, 1, 3, 26, -33, 29, 6, 7, 17, -3, -47, -11, 24, -15, 37, -39, 34, -11, -7, -30, 8, -40, 26, 14, -12, -31, 18, -2, -9, 30, 24, 14, 19, 19, 26, -25, -19, 24, 18, -16, 2, -18, 17, -8, -4, -15, 13, 12, -7, 8, 22, -18, -2, -26, 23, -7, -10, 20, 31, 11, 24, -14, -2, 29, 0, -6, 13, -14, -1, -11, 3, 20, 5, 2, 27, -17, 20, -8, 21, -3, 5, 28, 4, 0, 15, 1, -18, -19, -7, -19, -31, 10, 4, 4, 15, 13, -18, -45, 25, -4, -14, 17, 5, -30, 1, 11, -1, -23, 19, -18, -31, -7, -15, -2, 9, 18, -40, 9, -2, 16, -35, -21, -19, 8, 14, -16, -34, 18, 8, 12, -18, -1, 18, -29, 21, -17, 33, 1, -25, -27, -25, 34, 16, 2, -44, 1, 12, 10, 21, 2, -5, 38, 33, 5, -44, -12, -9, -41, 9, -21, -25, 8, -17, -6, -24, 5, -13, -3, -29, 0, -7, 39, -15, 1, 17, 4, -19, -2, -37, -24, 3, -13, 6, -30, 22, 9, 10, -9, -12, -32, -23, -5, 6, -2, -36, 28, 1, -23, -14, -8, 14, -20, -15, -29, -36, -18, -30, -23, -8, 6, 1, -32, 20, -37, 13, 7, 28, -1, 19, 21, 9, -8, -21, -12, -15, -12, 0, 13, -9, 19, 4, -38, 22, -33, 9, 9, -17, 39, -34, -21, 0, 28, -11, -24, 9, -11, -5, 22, -25, -2, 5, 11, -36, -11, -21, 5, -27, -4, 5, -1, -11, 38, -21, 12, 18, 32, -2, 32, -20, 3, -13, 7, 25, -2, -20, -6, -14, 12, 1, -11, -20, 8, -1, 12, 4, 14, -12, -37, 9, 2, -27, 26, 28, 13, -4, -3, -8, 30, 6, 22, -2, -12, 5, 24, -16, -1, 18, 25, 4, 4, 3, 3, 3, -9, 32, -42, -14, -26, -13, 14, 9, 3, -39, -2, 28, -34, 24, 3, 4, -13, -23, 12, 33, -18, -14, 21, -18, -29, 21, -6, -19, 21, 17, -14, -5, -24, -3, -8, 37, 36, 18, -24, -5, -23, 17, -15, -42, 14, 16, -3, -12, 38, -37, -9, 0, -8, -25, 27, 13, -22, 21, 0, -23, -14, -15, -42, -32, -29, 11, -42, -19, 15, 20, -4, -52, -15, 16, -38, 0, 12, 24, 11, -4, -37, -22, 8, 33, -6, 10, -46, 37, 24, -10, -4, -3, -58, -9, 17, 18, -29, 15, -38, -2, 19, 19, -13, -25, -19, 19, 24, 34, 4, -9, 14, -5, 39, 8, 16, -5, -15, 21, 37, 2, 8, 39, 14, 6, 0, -5, 22, -16, 11, 0, 26, 39, 22, 38, -34, 41, -1, -30, -28, 7, -16, -4, -15, 24, -15, 19, -35, -25, -13, -2, 31, -19, 21, 15, 4, -5, 26, -12, -17, 8, -14, 21, -18, 11, 13, 1, -32, 15, -9, 11, -34, 6, 10, -10, 5, -12, 4, -10, 10, 13, 11, -8, 13, -12, -23, 21, -16, 24, -6, 0, -28, -26, -29, -1, -11, -20, 5, 30, 12, 7, 16, -10, -15, 3, -7, 10, -6, -4, -18, 11, 5, 28, 27, -21, -6, -38, -20, -15, 28, 22, 29, 15, -18, -29, 20, -9, -3, 11, 13, -12, -2, 13, 8, 12, 3, 6, 2, -33, 15, -33, -20, -29, 13, -16, -10, 11, 3, -11, -19, -23, -5, 10, -19, -17, -25, -27, 2, -20, -3, -17, 10, -17, -5, 16, 34, -6, 35, -1, 11, -8, -17, 11, -10, -16, 29, -14, 24, 11, -16, -34, -6, -7, 0, -36, 28, -7, 13, 39, 10, -34, 20, 1, -12, 3, -2, -9, -30, 22, -31, -42, 19, -36, -44, -39, -31, -5, -34, -21, 34, 21, 35, 39, 31, 20, 18, 3, -15, -12, 19, 38, -25, -17, -31, 1, -41, -1, -16, 11, -43, 8, -60, -23, 72, 6, 6, -16, 3, -21, 66, 8, -5, -27, 21, -10, -40, -41, 11, -2, -39, -15, -19, -25, 1, -13, -31, -15, 44, 34, 0, 19, 38, 17, 48, -29, 9, -14, -23, -12, -16, 20, -27, -17, -38, -7, 4, -1, -26, 10, 3, 17, -5, 6, -2, 12, 5, -4, 5, -18, 12, 21, -20, -1, -12, -13, -47, -21, -37, 0, -10, -24, -44, -11, -2, -3, -11, 21, 9, 2, 0, 20, 17, -39, 21, -15, -28, 9, 23, 21, -42, 3, -14, 14, -5, -17, 16, 20, 16, 15, 7, -3, 24, -36, -29, 33, -4, -33, 15, 16, 20, 27, -3, -19, -15, -13, 14, 19, 8, -3, 4, 11, 17, 31, 9, 31, 22, -4, -3, 33, 0, -12, 29, 31, 4, 30, 16, 15, -13, -3, 15, -13, -26, 18, -27, -4, -3, 0, -41, -14, -43, -30, -39, -12, -1, -22, 22, -2, -42, -11, 37, -14, 5, 15, 46, -13, 19, -6, -5, 19, 26, 9, -39, -4, -38, -49, -48, -2, -8, 6, 13, -4, -4, -25, 12, 8, 8, -11, 18, -21, -25, 16, -18, 0, -3, -25, -44, 14, 12, -8, -2, 17, -47, -11, 22, 1, -3, -32, -10, -14, 23, 21, 5, 16, -7, 3, 11, -2, -13, -25, 54, -17, 7, -41, -21, -14, 29, 20, 19, -12, -1, 21, 26, -26, 25, -20, 1, 23, -15, -25, 9, -23, -8, -17, 10, 38, 32, -42, -34, 23, -4, -15, -16, 8, -15, 19, -15, -36, -36, 38, -2, 10, -49, -14, 8, -8, -1, 28, -16, 2, 33, -21, -18, -2, 32, -48, 17, 16, -7, 57, -3, -15, -27, -4, -6, -23, -37, -27, 3, -8, -2, -38, 21, -25, -2, 18, 5, -20, 32, -8, -23, 1, 20, 32, -6, -17, 20, -11, 11, 26, -43, -1, 20, 13, -5, 14, 2, 42, 7, -27, -6, 35, -8, 0, 14, 14, 27, 44, 21, -32, -21, 9, -6, 20, -43, 35, -15, -8, -15, -1, -44, 10, 38, -10, -30, 37, 6, -12, 41, -5, -29, -5, 36, 3, -10, 10, -11, -25, -13, 16, -23, 9, -15, -13, -25, -10, -33, 14, 29, -11, 5, -11, -7, -13, -23, 25, 15, 21, 3, -29, -13, -11, -12, -6, 7, 25, 1, 16, -24, -11, 17, 6, -45, -7, -21, -12, 14, -3, 3, 4, 16, -23, -29, 22, -18, -1, -31, 5, -16, -3, 23, -22, 8, -34, 12, 16, 2, -12, -14, 17, 6, 14, -7, -39, 29, -2, 7, -15, -1, -42, -2, 13, 14, -1, 18, 10, -17, 12, 15, 0, -3, 17, 4, 10, 3, 8, -9, 25, 14, 8, -5, 19, 4, 27, 10, -18, 18, 2, 11, -25, -16, -3, 31, 2, 19, 6, -6, 13, 0, 25, 22, -7, 16, 22, -19, 37, 24, -13, 19, 20, 2, 22, -8, 10, -46, -17, 10, -35, -26, -6, -25, 2, -6, 10, -10, -3, 14, 2, 15, 21, 15, -4, -26, -18, 17, 11, 3, -15, 4, 22, -17, -25, 16, -14, 19, 17, -4, -26, -11, -1, 0, -3, 12, 17, 1, -15, 28, -13, -26, 0, 16, -5, -17, -12, -6, -3, -22, 32, -53, 2, -12, -1, 27, -34, 3, -17, -6, -6, -6, 25, 15, 31, -5, -24, -4, 22, -44, 16, 13, -11, -13, -5, -25, -9, 28, -10, 24, -16, 10, 44, 8, 43, 31, 38, 7, 43, 45, 3, -8, -30, 5, 21, 12, 24, 61, -32, 9, -15, -7, -27, 14, -20, -21, 12, -30, -33, -9, 0, -13, 1, -11, -33, -13, -5, -8, -12, 1, 46, 44, 3, -14, 4, 4, -25, -6, -23, -2, -46, -3, -15, -28, -14, -13, -48, -22, -4, -12, 14, -7, -8, -24, -44, -4, -4, 16, 14, 26, 2, -10, 11, 24, -17, -21, 23, 12, 6, -13, 6, -15, -19, 28} + +#define TENSOR_CONV2D_2_KERNEL_0_DEC_BITS {8} + +#define TENSOR_CONV2D_2_BIAS_0 {-102, -7, -44, 32, 5, -12, -28, -2, 36, -17, -30, 31, -72, -69, -14, 12, 7, 6, -61, -61, 15, -29, -35, -15, -1, -64, -24, -1, -33, -4, 34, -12, -71, 1, 10, -116, -28, -20, -19, -9, -46, -73, 52, -21, 37, 20, -2, -66} + +#define TENSOR_CONV2D_2_BIAS_0_DEC_BITS {11} + +#define CONV2D_2_BIAS_LSHIFT {2} + +#define CONV2D_2_OUTPUT_RSHIFT {9} + +#define TENSOR_DENSE_KERNEL_0 {32, -23, 4, -25, -1, 5, 17, 9, 11, -17, 31, 7, -9, -9, -3, 28, 8, 3, 55, -12, -5, 4, 9, -19, 12, -4, 26, 0, -20, -12, 15, -26, 49, -16, -11, -3, -5, -14, -10, -14, -1, -9, 59, -20, 8, 14, 14, 7, 0, -5, -8, -11, 9, 4, -10, -9, -21, 8, 12, 7, 0, -1, -21, -8, 5, 5, 12, -8, 18, 22, 5, -16, 11, -1, -36, 8, -15, 14, -5, 3, -10, -6, -6, -7, 10, -1, -13, 15, -8, 4, -6, -12, -14, -7, -20, -10, 5, -8, 19, -1, -15, -15, -10, 10, -9, -4, 6, -8, 2, -10, 15, 3, 47, -13, 30, 7, -18, 9, -21, -31, 39, -3, 26, -10, 16, 21, -17, -2, -27, -10, 7, 12, 9, -1, -15, 9, 58, -6, 16, -1, 5, -26, 7, 4, 25, -2, 29, -5, -4, 12, 16, -13, 2, -24, -16, 11, 3, 12, -1, -4, 25, -5, 28, -1, 13, 17, -1, -11, 8, -20, -2, -7, -14, -15, 13, -6, -29, -3, 16, -3, 8, 16, 15, 7, -9, 15, 42, -5, -6, 18, 16, 7, 29, -12, -2, -22, 9, -20, -18, 7, -11, 0, 13, -21, 1, -7, -23, -19, -19, 13, 26, -4, -12, 9, 20, 7, 22, -1, 24, 8, -17, 10, -15, -8, 13, -11, -6, -13, 1, -13, -6, -19, 11, 7, 60, 4, 8, -24, -2, -35, 21, -15, -18, -24, -22, -17, -15, 12, 11, -14, 12, 7, -8, -16, 13, -3, -4, 0, -19, 5, 13, -8, 2, 7, -13, 0, 21, 4, 9, -8, 18, -10, -5, -2, -19, -5, 2, -21, -2, 0, 4, 13, 25, 14, 3, -5, -12, -19, -14, -8, -7, -16, 1, -24, -21, 7, 37, -12, -2, 0, 7, -28, -6, -18, 23, 9, 25, -16, 5, -15, -5, -11, -20, -19, -2, -10, -22, 15, -13, -17, 12, 20, 3, -20, -6, -24, -7, -13, 4, 3, 11, -20, -9, 9, 4, 3, -10, 10, -8, 3, 21, 16, 4, 0, -12, -16, 6, 3, -9, 28, 12, 3, 4, -4, 5, -9, 16, 22, -15, 31, -6, -22, -10, -20, -3, 2, 15, -15, 21, -21, -3, 12, -7, -3, -21, -15, -14, -14, 58, 1, 0, 10, 4, -23, -36, 12, 16, -11, 5, 38, -1, -6, -14, -9, -5, -15, 17, 29, -18, -5, -8, 1, 1, -11, 6, 8, -3, -6, 13, -2, 5, -5, 2, -18, 2, -1, 21, 9, 37, -21, 8, 5, 8, 0, 5, -11, 33, -20, -7, 11, -20, 13, 12, -3, 13, -22, 15, 14, -5, -16, 3, -13, 6, 7, -17, 17, 2, 2, 17, 9, -26, -20, 3, -8, 9, 3, -14, 13, -17, -16, 6, -16, 5, 15, -14, -11, 16, 13, -19, -1, 19, 25, 25, 7, 29, -3, -10, 3, 18, -15, 15, 4, 9, -17, 17, 4, 17, -10, -4, -23, -6, -14, -11, 20, 5, 21, 18, 0, 8, 2, -5, 19, -1, 11, 27, 9, -18, -22, 1, -7, -25, 29, 14, 13, -6, 17, -20, -37, -7, 13, -17, -5, 4, -7, 0, 14, 0, -13, -1, -12, 10, -4, 0, -17, -9, -9, -5, -27, 34, -7, 9, 6, -18, -24, -19, 0, 6, -21, -3, -1, -14, -13, 13, 2, -1, -15, -6, 29, 3, -19, 27, -14, 7, -8, -4, 39, -9, -1, -7, -12, 18, 11, -23, -16, 21, 8, 7, -6, 3, -26, -5, 26, 3, 21, 6, -6, 2, -13, -19, 4, -11, -5, 2, -22, 7, -5, -11, -22, -1, 11, 1, -2, -28, -1, 0, -7, -5, 24, 13, -26, 18, 6, -3, 7, -21, 25, 27, -9, -7, 16, -5, -15, 2, -18, 37, -21, -11, -11, 18, -2, -14, 9, 0, 14, -7, 18, -8, 21, 4, 2, -32, -2, -7, -15, -19, 10, 7, 8, -12, 14, 19, -28, -18, -16, 14, 10, -14, -11, -9, -22, 7, 1, 3, -1, 16, -4, -1, 2, -10, -29, -2, 29, 1, 0, -3, 3, -12, -21, -10, -11, 21, 20, 3, -19, 12, 10, -20, 17, -24, -7, 12, -21, -19, 7, -19, 7, -7, 11, 5, 7, -7, 15, 1, -5, 3, -24, -13, 5, -9, 36, -19, 4, 15, 8, -15, 7, -19, -2, -3, 49, -15, -3, 19, -4, -24, -13, -12, -9, 15, -13, -29, 9, -6, -12, 12, 24, 4, 5, 7, -18, -1, 15, 9, -28, 1, -21, 15, 11, -4, 3, -19, 0, 37, -11, -4, -8, 10, -5, -19, 28, 8, -8, 5, -17, -20, 19, 1, -4, 18, -21, 10, -6, -8, -11, 4, 2, 3, 10, 1, 1, -21, -4, -12, 12, 4, -1, 70, -28, -13, 3, 16, -33, -11, -19, -2, -11, 0, -6, -14, 4, -23, -19, -14, -7, -17, -8, 3, 7, 40, 17, 29, 14, -8, 13, -13, 35, 28, 5, 30, 6, 0, -13, 9, -1, -9, 2, 9, -29, 13, 9, 18, -20, -27, 1, 4, 6, -9, 12, 4, 20, 6, -14, 39, -29, 5, 7, 14, 17, -4, 5, -18, -10, -2, 13, -18, 6, -6, -9, -16, 14, 16, 0, -21, 6, 14, 3, -33, 3, 7, -26, 11, 27, -2, 0, -28, 9, 10, -2, -14, 13, 1, 17, 5, 16, -19, -10, -11, 6, 21, 9, 9, 0, 18, -23, 5, -8, -5, -17, -16, -2, -8, 24, 12, 10, -15, 3, 28, 8, -21, 0, -6, 1, -29, 1, 4, -8, -13, 14, -6, -26, 0, -24, -2, 11, 2, -36, 6, -10, 14, -9, 24, 3, -15, 3, 0, 3, 39, -12, -29, -19, -16, -34, 3, 17, 10, 12, -38, -20, 19, 27, -13, -13, -31, -25, -1, -10, -7, 16, -19, 12, 12, -9, 5, -10, 8, -16, 14, 6, -24, -6, 9, 9, -17, -4, 6, 14, -7, -22, 0, 6, 1, -8, 6, 1, 14, -19, 31, -16, -9, 21, -18, -34, 4, -18, -7, -12, 11, -12, -13, 22, -7, -24, 21, 8, -4, 14, -7, 5, 8, -8, 12, 0, -11, -20, 4, -6, -8, -16, 4, -17, -8, 10, 17, 30, -15, 0, 19, 6, 6, -6, -19, 19, -13, -16, 19, 19, -16, -9, 16, 1, -16, 6, -4, -18, 0, 20, 10, 11, -18, -4, -8, 14, -8, 14, -19, 16, -13, -19, -13, -5, -22, -8, -23, 22, 11, -18, -22, -1, -13, -1, -17, 29, -23, -22, 29, -1, -10, -18, 2, 8, -14, -25, -2, -15, 4, 19, 12, 14, 30, 14, 7, 13, 4, -33, 0, -10, -10, -23, -14, -19, -19, -1, 4, 1, -12, -3, 3, 3, -8, 20, -6, 3, -52, -15, 10, -1, 4, 16, -9, 26, 31, -7, 17, 6, -2, -18, 14, 0, -16, 10, -6, -21, 4, 30, -18, -4, 33, -2, -8, 8, -17, -38, -11, -12, 3, 12, 13, -14, 10, -19, -7, 1, -17, 12, 24, -2, -11, 17, -10, -16, 13, -2, -3, -14, -5, 35, -19, -34, -4, 10, -6, -12, -12, 30, -12, 1, 6, -18, -24, 12, -6, -11, 18, -19, 9, -15, -24, 1, -22, 11, -25, -1, -6, -9, 19, -21, 16, 7, 6, 9, -8, -17, 2, 10, 11, 3, -21, 23, -27, -26, -7, 13, -3, -4, -19, 0, 30, -10, -4, 7, -25, -3, 6, 18, -31, 8, 2, 1, -2, 4, -5, -35, 43, -25, 10, 15, -18, -21, 15, -13, -3, -6, 2, 16, -14, -37, -10, 4, 5, -18, -17, -10, 12, -2, -17, -42, -21, -27, -6, 10, -12, 15, -12, 23, 25, -24, 27, -4, -10, 12, -21, 0, 5, 15, 27, -13, 15, -22, 18, -34, -3, 5, 28, -24, 7, 8, 0, -10, -14, -2, 15, -7, 10, -10, 14, 16, 6, -13, -6, -4, 14, 7, -12, 16, -11, 1, -21, 6, -11, -21, -19, -6, 25, -6, 10, -17, 19, -2, -25, 4, 11, 13, 3, -20, 7, 12, -15, -13, -21, -19, 5, 17, -4, -7, -9, -40, 13, -6, 15, 2, 16, 29, -21, 3, -9, -6, -6, -23, 17, -5, -20, 19, 9, -25, 11, -23, -7, -7, 11, 1, 10, -9, -16, 7, -1, 18, -10, 21, -8, -7, 12, -27, -22, -17, -9, 6, 44, -27, -3, 13, 4, -11, -12, -12, 20, -27, 8, 7, -9, 5, -18, 25, -6, -12, 19, 9, -21, 25, -13, 16, -12, 2, 3, -6, -7, 1, -6, -23, 13, -1, 16, 7, -10, -14, -14, -1, 27, -26, 13, 3, 9, -8, -15, -4, 34, 13, 15, 13, 15, 10, -23, 22, -5, -20, -9, -12, 12, -20, -10, 3, 14, -6, -7, -7, 9, 4, 10, 26, -20, 8, 4, 11, 12, -13, 5, -13, 9, -4, 21, 6, 2, -14, -11, 6, 3, 0, 21, 18, 14, -7, -17, -11, -14, -2, 4, 12, 9, 7, -23, 11, -14, 8, 5, 13, 15, 34, -15, -9, -27, -13, -3, -4, -19, 25, 6, -3, 18, -22, -5, -14, -18, 25, 7, -42, 34, -31, -11, 3, 4, -3, 3, 4, 5, -21, -2, 2, -10, -29, -4, 10, -24, 5, 32, 17, -17, -21, -13, -8, -13, 12, -10, -14, 17, 28, 12, 20, -6, 0, -17, -13, -18, 14, -8, -26, 6, 13, 1, 11, -18, 0, -18, 30, -15, 8, 32, -8, 4, 11, 12, -25, -12, -4, -22, -8, 1, -11, -17, 1, 5, -3, -21, 14, 10, 21, 3, 24, 10, -4, -10, -18, -17, 1, -15, 26, 18, 8, 20, -16, -6, 5, 8, -2, 0, -18, 11, -19, 17, -12, 4, -10, -10, 8, 27, 13, -8, -7, -13, 4, 9, 4, -33, -23, -16, 5, -14, 4, -12, -24, -11, 10, -13, -8, -17, -15, -10, -16, 4, -8, 3, 1, -5, 29, -2, 20, 17, 5, 14, -18, 2, 12, -9, 9, -3, -14, -12, -25, -17, 12, 19, -14, 14, 8, 15, 19, 15, 8, 1, 10, -7, -20, 19, -1, -22, 20, -13, 9, -17, -4, -12, -18, -15, -3, -20, 5, -4, -24, -14, 10, -11, -5, -20, -7, -7, -20, -9, -8, -14, 3, 10, -24, -41, -26, -6, 16, 0, -19, -8, -7, 8, -5, -13, 3, -9, -8, 14, -23, -18, 19, -16, -25, -7, -15, -1, -12, -14, 8, 14, -1, 15, 14, 17, -21, -20, -23, -24, -2, -18, -6, -11, -30, -7, -13, -2, 34, -13, 16, 16, -2, -14, 13, -1, 15, -14, 9, -2, 12, -13, 9, -17, 0, 13, 9, -6, -10, -11, -10, 14, 25, 16, 15, 14, 10, 9, 10, -9, -27, -13, -4, 4, -19, -22, 20, 10, -14, 4, 12, 21, 12, -5, -26, -18, -19, -17, 1, 27, -11, 24, -7, -18, -34, -1, -2, 13, 14, -11, -8, -13, -14, -10, 0, 24, 6, -8, 4, 14, 10, -6, 8, -19, 5, 4, 0, -5, 20, -7, -22, -2, 9, 9, 13, -24, -5, 7, -1, 12, 15, -13, -16, 8, -14, -13, 18, 14, 9, 21, -23, -11, -5, 15, 26, -1, -7, 23, 19, 0, -5, 16, -27, 22, -14, 15, 4, 16, -2, 8, 5, 6, -19, -25, -1, 2, -14, -15, -17, 24, -4, -15, 7, -7, 0, 13, 28, -9, 6, 22, -9, 2, -5, -9, -6, 11, -19, -14, -18, -3, 0, -24, 17, -21, -5, 0, -10, 15, -7, 13, -9, 1, -17, 18, 13, -23, -9, -5, 2, -2, -22, 30, 3, 1, 2, 16, 10, 10, 17, -12, 9, -25, -37, -2, 6, 16, -1, -3, -4, 7, 28, 1, -1, -6, 14, -14, 0, -2, 4, -14, 5, 1, 3, 6, -24, -16, -1, 16, 23, -19, 0, -37, -6, 1, 1, 17, -7, 0, -20, 11, -10, 21, -5, 8, -16, 11, -2, -25, -8, -20, -32, -15, 33, 0, -12, 6, -14, -8, 15, 7, -3, 10, -22, -2, 10, -18, -5, -23, -16, -28, -23, 27, -18, 14, 16, -16, 4, -17, 6, -6, 11, -5, -16, -22, 1, 7, -8, 21, 3, 15, -23, 4, 14, -1, -26, 10, -8, -19, -1, -10, -10, -15, -16, -3, 18, -7, -18, -3, -13, -9, 7, 23, 1, 6, 8, 7, 1, 22, 16, 2, 16, -4, -36, -13, 10, 24, 2, 6, -11, -11, -19, 5, -23, 15, 4, 15, -5, -15, 27, 10, 9, 3, -2, 19, -14, 0, -20, 8, -3, 11, -8, -3, -15, -15, -19, -2, 33, 11, 2, 9, -12, 9, -10, -2, 2, 7, -6, 0, -25, -3, 14, -8, 28, 17, -9, 3, 0, 8, -1, -20, -2, 16, -18, 3, -16, -8, 12, -8, -9, 19, -14, 6, -8, -20, 23, -20, 20, 9, -12, 2, 6, -5, -6, -6, 10, 15, 11, 21, 15, -3, -54, 4, -12, 6, -15, 2, 10, -7, 1, -1, -8, 19, -14, 2, 11, 24, 2, 0, -11, 41, 10, 14, 4, 5, -38, 16, -14, 0, -5, 27, 18, 8, 0, 11, -11, -7, -24, 8, -20, 7, 15, -2, -28, 46, -30, 17, 16, 15, -72, -10, -8, 12, 12, 0, 2, -19, 10, 9, -4, 10, -9, 12, -9, 2, -51, 9, -7, -5, -9, 12, 4, -2, -2, 21, -23, -11, 11, 25, -19, -15, 19, 12, 10, -23, -20, 20, 11, 12, 15, -21, -28, -4, 10, -13, -25, -4, 7, 18, -23, 9, -19, -17, 8, 20, -39, 13, 21, -7, 2, -10, -2, 4, 12, -17, 43, 14, -19, 16, -12, 11, 12, -8, 0, 5, -20, 23, -11, -12, -15, 12, -33, -15, -11, 29, 5, 18, -7, 0, -17, -16, 9, -16, -15, 15, -14, 12, -14, 30, -3, -11, 5, -6, -64, 7, -7, -21, -2, 33, 8, -17, -29, 14, 1, -12, -12, -12, -1, 11, 13, 10, 37, -17, 5, 12, 2, -4, 17, 7, -1, 8, -13, -12, -11, -22, -14, -19, 12, 28, 0, 11, 16, 17, -28, 8, -1, -4, 13, 23, 11, -8, -24, -12, 8, -8, -7, -19, 14, 19, -13, 1, 33, 12, 18, -1, -21, -10, -13, 2, 20, 24, 4, 6, 10, 7, 23, -2, -36, 3, -8, 3, 2, 4, 3, -2, -10, 22, 11, 4, -13, 12, 16, 19, 22, -14, -9, -13, -11, -15, 6, 18, 7, 10, -15, 20, 0, -7, 4, -16, -11, 12, 1, 6, -6, -13, 29, 19, 14, -12, 3, -8, 9, -1, 13, -17, -22, 37, 7, 18, 1, -14, -12, -17, 17, 23, 12, 8, -21, 18, 20, 13, 7, 9, 0, 1, 16, -19, 17, -14, -35, 16, 15, 4, -13, 4, 10, 1, 31, -5, 5, 2, 9, -13, -22, -19, 12, 34, 3, 6, -8, 18, 6, 6, -13, 9, 11, 25, -2, 10, -12, 10, -5, 10, 7, -8, 10, -11, 19, 11, 27, 3, -8, -3, -7, -23, 37, -14, -12, 2, 4, -9, -7, 16, -21, -20, 2, -16, -6, 14, 19, 5, 10, 14, -23, 22, -4, 0, -5, 17, -8, -16, -3, 11, 9, -16, -24, -1, -2, 15, 5, 22, -2, 10, -22, -10, 24, -12, -16, -27, 8, 12, 13, -17, -20, -14, 13, 5, -18, -16, 6, -14, -2, 16, 16, -8, -13, -19, -21, -18, 12, -4, -7, -1, 0, 6, 20, -6, 15, 0, 6, 0, 17, -12, 11, -2, 21, -22, 33, -9, 3, 7, 18, -22, 6, -23, -19, 18, -11, -20, -15, 2, 19, 13, 16, 25, 6, -12, -24, -11, -12, 18, 3, 15, -14, 14, -23, -20, -9, -5, 22, 13, -21, -17, 5, 3, 28, -1, 22, -1, -11, 23, -22, -12, -40, 10, -17, -14, -6, 19, 0, 10, 15, 2, 13, 1, -9, 2, -16, -5, 9, 14, 0, 14, 10, 22, -7, -18, -6, -7, -23, 1, 8, 1, 18, -23, 14, -6, -35, -2, 2, -18, -24, 9, 20, -21, 23, 23, 5, -18, 0, 13, -12, -22, -5, 8, -16, -17, 16, -6, 28, -17, -27, 24, -5, 13, -5, 11, -21, -3, -12, -3, -1, -14, 5, -3, -18, 2, 21, -14, -1, 3, -3, 6, -2, -2, -5, 8, -15, -17, 15, 7, -22, -17, 18, 13, -24, 3, -20, 16, 9, 7, -5, -2, 15, -11, -20, 8, 15, -19, -8, -10, -21, -25, 16, -9, 26, 6, -32, 12, -16, -3, -20, 13, 3, 5, 1, 5, 0, 20, -18, -11, -17, -2, -16, 12, 9, 9, -19, 22, 34, -5, -1, 19, -9, 13, -9, 8, -11, -6, -49, -9, 11, 0, -2, 18, 19, 17, 20, -13, -6, 10, -16, -1, 9, -17, -44, -33, 4, 11, 1, -12, -14, -8, -19, -23, -5, -15, -12, 7, 10, -6, 23, 17, 13, -25, 11, 12, 32, 14, 23, -8, -5, -20, -10, 10, 22, -12, -5, -17, 16, -26, 12, -9, 10, 18, -12, -13, 19, 3, -8, 9, -18, -19, 8, 18, -12, -1, 1, 17, -18, 5, -10, 16, -2, -5, -9, -5, 11, -4, 12, -8, 15, -15, -8, 11, 0, 11, -20, 16, -8, 10, 6, -4, -14, -4, -29, -7, -6, 15, -17, -2, -26, -4, -22, 0, 2, 12, 9, 8, 9, -9, 10, 27, 20, -7, -20, 8, 18, -25, 8, 34, -3, -9, -30, 2, -7, 11, 31, -41, -4, -20, 7, -14, 20, -16, 7, -17, 12, -1, 8, -10, -20, 19, -2, -34, -11, -3, -20, -14, -5, -7, 19, -33, -11, 8, 7, -11, -16, 12, -14, 12, -10, -7, -9, 11, 13, -7, -18, -14, -3, -22, 15, -4, 9, 14, -14, 17, -19, -11, 13, 2, 10, 17, -29, 14, -6, 10, 5, 18, -16, 17, 36, -13, -18, -33, 13, 4, 15, -8, 15, 24, -8, -3, -15, 11, -13, -1, -11, 31, -2, 15, 16, 20, 4, -15, -32, 1, 4, 7, -19, 18, 14, -17, -11, 23, 19, 5, -17, 13, -5, 10, -32, -16, 8, 10, -22, -4, 9, -22, -34, -24, 7, -18, 12, 21, -13, -18, -10, -3, -7, 36, -4, -16, 22, -16, 26, 33, 2, 11, 13, 17, 30, -3, 42, -5, 18, -12, -1, 2, 11, -23, 25, 0, 3, 3, -14, -12, -23, -7, -21, -25, -8, 16, -21, 16, -11, -1, -47, -36, -15, -10, -14, 4, 9, -21, 6, -27, 9, -11, 9, -13, -1, 15, 20, -18, 17, -19, -2, -6, 15, -18, 24, 11, -22, 1, 2, -7, 24, -4, 25, 25, -14, -18, -1, 4, 2, -9, -5, 12, 5, 1, 20, -29, 6, -33, 5, 11, -21, 11, 1, 0, 3, -9, -13, -7, -28, 14, -15, -6, 14, -37, -8, 18, -37, 4, 20, -12, -12, -2, 2, -20, 5, -3, 10, 23, -16, 4, 20, 9, -43, 15, -13, 26, -3, -16, -6, 10, 6, 4, -10, -7, -15, -7, 14, 18, 9, -15, -16, -14, 7, -7, -29, -14, -7, -18, -9, 10, -1, 10, 21, -17, 5, 18, 28, 3, 1, -10, 25, -3, 1, 5, 22, 7, 18, 8, 32, -9, 7, 1, -13, 5, 3, -14, 10, -7, 6, -17, -6, 3, 19, -24, -19, -22, -10, -22, -34, 14, 2, -14, 2, -7, -5, -5, -44, -37, -40, 9, -14, -2, -15, -20, -32, 8, 15, 7, 8, 1, 8, -23, 13, -10, -12, 7, 18, -16, -15, -4, 1, 15, 8, 18, -1, -20, -21, -15, -23, -20, -31, -39, -10, -21, 10, 15, -8, 18, 2, 7, 31, 10, -37, -1, 6, -18, -14, 5, -3, 9, -33, -2, -10, 24, 18, 14, 4, -10, 27, 0, -26, -25, 12, -3, 2, -2, -16, -15, 16, -1, 5, 2, 10, -9, -3, -1, -1, -9, 6, -7, -21, -12, -28, 18, 13, 19, 11, 13, -21, 13, -4, -10, -3, 10, -2, 2, 7, -17, 4, -16, 4, 12, -3, 26, -14, -17, -5, -12, 4, -5, 0, 25, 3, -11, -4, 14, -30, 32, 29, 21, -20, -3, -27, -4, -6, -11, -19, -3, 4, 14, -5, -8, 6, -11, 14, 24, -20, -20, 18, -20, -36, -10, -33, 9, -9, -18, 13, -9, 2, 16, 2, -17, 15, 2, -12, 12, 34, -3, -8, -4, -14, -20, 9, -11, 1, 7, 6, 25, -11, -18, 0, -20, -6, 13, 15, -4, 4, 13, -6, -4, -13, -25, 20, 1, 0, 6, -12, 0, 3, 13, -21, 5, -14, -13, 36, -10, -12, 24, -16, 23, -2, 5, -9, 18, 0, 11, 17, 7, -13, -16, -2, -5, -3, 0, 12, -3, -13, 5, 0, 14, 8, 8, 6, -7, 16, 9, 3, -3, 15, 18, -7, 22, 17, -23, -20, -18, 16, 4, -2, 17, -25, -13, -28, -11, 19, 5, 8, 31, -18, 7, -11, -1, 23, 53, -59, 28, -22, -13, -9, -2, -14, 23, 14, -10, -12, 1, 69, -18, -11, 2, -38, -2, -28, -8, 23, 12, 8, -17, 0, 16, 2, -3, 14, 8, 19, 5, 5, 1, 12, 16, -21, -23, 10, 12, -13, -9, -6, 6, -1, -19, 8, -12, 23, -5, 1, 0, 10, 15, -7, 2, -5, -4, -8, 13, 2, 13, -6, -6, 6, -8, -11, -17, -30, -14, 18, 17, -3, 1, 16, -18, -10, -19, 2, -8, -19, 8, -21, -4, 17, 1, -2, 24, 33, 22, -26, -14, -3, -12, 2, 33, -7, 27, -11, -20, -31, 13, 20, 49, 6, 15, 11, 11, 6, 11, -22, 15, 13, -12, 27, -22, -1, -8, -14, 6, 8, 1, -14, -20, 10, -18, -11, 13, 13, 19, 8, 0, -2, -13, 25, 8, -8, 37, 4, -1, 15, -2, 33, -32, -3, -18, 20, 12, 9, -14, -2, 17, 14, 7, -2, 13, 10, 5, 6, -5, -28, 13, -3, -2, -25, -20, -8, -7, -19, -7, 10, 2, 5, -1, 27, 7, -12, -21, -24, -7, -13, -9, 35, 12, -17, 29, 9, -3, 4, -3, -11, -9, -56, 37, 15, -18, 8, -19, 25, 19, -5, 23, 7, -12, 42, 15, 24, 19, -33, 17, -1, -4, 29, -2, 5, 9, -4, 31, 0, 10, -1, 5, -8, 26, -3, -10, -14, -8, -14, 8, -4, 17, -14, -22, -8, 12, 52, 0, 21, -9, -14, 12, -4, 8, 31, -3, -7, 21, -26, 15, -5, 11, 18, -16, 22, 22, -5, 31, 11, 15, 10, 7, -17, 35, -16, 2, -4, 13, 50, 6, -11, -7, -19, -12, -6, -10, -14, 2, 5, 0, 19, 12, 7, -6, 5, -16, 43, 35, -16, -4, -16, -7, 6, 16, 2, -29, 11, 12, -21, -8, 9, -8, 20, 6, -13, 13, 3, -25, -3, 0, 27, 16, -26, 25, 2, 6, 9, 1, 0, -2, -18, 2, -9, 5, 0, -2, -9, 11, 4, 19, 31, 2, 21, -2, -8, 27, -19, 22, 17, -16, 4, -10, -1, 15, -17, 9, 25, -8, 23, 10, -22, 11, -8, 45, 14, 18, -2, 13, 2, 27, 6, 18, -24, -12, -4, 4, -9, 23, 22, 29, 22, -9, -8, -13, 36, 21, -11, 39, 2, 6, -14, -7, 8, 33, 8, 6, -12, -10, 2, 6, 8, 3, -14, 27, -20, -1, -18, -1, -16, 4, 9, 4, -11, 7, 3, -17, 26, 11, 6, -26, 14, 9, -3, 12, -50, -23, 13, 4, -23, 0, 0, 0, 12, 22, 7, -1, -13, -21, 2, -13, 29, 1, -15, 3, 4, 15, -10, -13, -17, 40, -7, -1, -33, 9, 10, 0, -6, -7, 12, 13, 9, 7, 6, 11, 21, -9, 5, 11, -28, -11, 10, -17, 23, -29, -7, -23, -24, -6, 2, 3, -25, -9, 7, 20, -8, 3, -1, 14, 24, -28, 8, 15, -17, 5, 8, 4, 31, -12, -10, -5, 1, -6, 3, 12, -20, 9, -5, -10, -17, -26, -27, -21, -7, 19, -16, -6, -7, -2, 17, 20, -21, -14, 18, 5, -38, -4, -25, -1, -11, 23, -17, 27, 13, -17, -7, -1, 31, 22, -10, -6, -12, -20, 11, -13, -27, -20, 41, -15, -30, -2, -21, 16, -21, -8, 2, -3, -17, -2, 4, -14, -5, -4, 54, 4, -2, 10, 1, -13, -28, -20, 14, -10, 3, -7, -10, 15, 26, 11, -29, 1, 24, 19, 5, 17, -3, 35, 3, 3, -16, 10, 13, 1, 22, -10, -8, 21, -3, -6, 0, -18, -30, -17, 8, 3, 5, -8, 14, -3, 1, -10, 1, 1, 2, -11, 21, 4, -11, 22, -6, -12, 8, 6, 17, -22, -24, 8, -6, 4, 4, -17, 16, 7, -7, -4, 30, 9, 13, 1, -18, 3, -18, 5, -11, -4, 11, 4, -7, -17, -2, 15, -7, -27, 13, -18, -1, -6, 19, 6, -20, 9, 14, 0, -2, -3, 14, 5, 16, -33, 12, -20, -27, -24, -18, 23, 16, 12, -10, 16, 24, -17, -1, -17, 37, 1, -21, -18, -1, 5, 7, 19, -21, 14, 16, -8, 6, -20, -8, 2, -7, 12, 2, 15, -23, -11, -5, -22, -6, -27, 36, 5, -3, -16, -9, -29, 4, 15, -25, -17, -7, -2, 46, 7, -18, -5, -4, -5, -32, -1, 0, 39, -44, 28, -18, -8, -29, -17, -19, -3, 4, 7, -9, -21, 14, -2, -18, -24, 5, 11, -18, -12, 18, 3, 7, -6, 36, 28, 0, -8, 26, 10, -12, -3, -7, 11, 3, -17, 50, -19, 3, -41, -5, 8, 6, 10, 1, 14, 18, 0, 13, 24, -8, 5, -11, -11, -19, 28, -26, -20, -7, -15, -5, -1, -13, -20, 4, 13, -19, 13, -17, -15, 20, -9, -17, -10, 22, -11, -21, 10, 6, -29, -2, 10, 7, -14, 5, 3, 24, -22, 14, 49, -41, -13, -27, -22, 17, 6, -13, -6, 0, 10, 16, -4, -31, 49, -31, -18, 20, -4, -22, 10, 34, -1, -12, -9, -30, -15, -1, -1, -13, 18, -23, 23, -23, -24, 1, -17, 6, -3, 26, -18, 17, 10, 5, -5, -16, -14, -2, 22, 11, 6, 13, -2, 11, -53, 33, 24, -13, -2, 6, -24, -10, 13, -19, 29, -12, 10, -9, 10, -29, 4, 10, 9, 29, 1, -17, 15, 11, 18, -31, 1, 6, 9, -13, -14, 9, 31, -16, -7, 5, -19, -7, -24, 15, -2, 0, 2, 25, -18, -23, 15, -12, 22, -44, -13, 16, -25, 13, 13, 20, -27, 14, 46, -6, -13, -25, 12, 5, -4, -19, 5, -7, -21, -20, -3, 6, -20, -23, 3, 13, -1, 12, -2, 13, -14, -14, 17, 24, 10, 18, 7, -7, -8, 9, 1, -27, 15, 4, 11, -9, -8, 11, 15, 4, -14, 37, -2, -16, -5, 18, -2, 6, -16, 19, -12, 10, 10, 1, 18, -4, 3, 7, -13, 27, 1, 1, 0, -30, -11, 0, -24, -11, -9, 1, -16, 13, -11, 20, 10, -11, -29, 6, -9, -9, -2, 20, 11, -7, -13, 10, 0, 15, -22, -10, -9, 1, 14, 11, 36, 4, -11, 2, -24, -7, 4, 18, -15, 1, -13, 12, -22, -21, -6, -11, 6, 22, -17, 13, 6, -9, 28, 19, -9, -15, -4, -2, 1, 15, -16, -2, 21, -30, -6, 10, 1, 22, -7, -30, 3, 22, 13, 4, 9, 20, 15, -39, 1, 8, 3, -15, -20, 20, -13, 15, -3, -23, 3, -3, -18, 6, -2, 15, -11, 6, -6, 23, -19, 11, -2, 29, 46, 0, -15, 9, -6, 10, 21, -11, -3, 18, 7, 25, 16, 9, 16, -2, -2, 5, -2, 25, -25, 6, 22, -24, -1, 6, 13, -3, -1, 9, 15, 20, 26, 10, 20, 9, -1, 8, 3, -24, 12, 11, -6, -7, 13, -12, -31, -14, 20, 12, -22, -15, 3, 13, -35, 19, -5, 37, -12, -5, 12, 23, 28, 26, -8, -1, -11, -16, 10, 4, 3, -16, 25, 23, 10, 1, -5, -4, 8, 28, -21, 31, -5, -14, -14, 25, -13, -9, -25, 15, 12, 3, -8, 7, 24, -9, 5, -4, -11, -11, -1, -13, 9, -9, -7, 17, -2, -1, 5, -2, 10, 9, -14, 5, -17, -19, 1, -32, 19, 25, 9, -35, 3, -21, 1, -9, 27, -5, 20, -17, 7, -16, 7, -12, -7, 32, 1, -16, 9, 0, 14, -14, 15, -13, 11, -9, 3, 12, 13, 17, -7, -2, 7, 25, -20, -28, 16, -11, 13, -22, 16, 36, -8, -10, -15, 3, 7, 18, -1, 6, -14, -34, 1, 10, 17, -46, -8, 12, -10, -13, -3, -24, 8, 32, 0, 2, 1, -15, -10, -33, 8, 11, -4, 25, 4, -8, -4, -14, 20, -5, -4, -19, 14, 20, -6, 14, 18, 12, -9, 32, 8, -5, -6, 25, -7, -7, -21, 13, 19, 10, 15, -2, -9, -11, -12, -18, 11, 3, -6, -3, -29, 8, -9, -5, -11, -17, 7, 2, 19, -31, -13, 13, -1, -1, -5, -6, 24, 10, -5, 20, -6, 2, 3, 25, -6, -6, 12, 18, -1, 7, 1, -5, -15, 23, 2, 18, -6, 2, 0, 19, -14, 10, -21, -15, 10, 0, -10, -19, -4, -6, 19, 18, 12, -22, -20, 4, 15, -23, -15, 2, 15, -12, 4, -23, 22, -8, -25, -17, 3, -13, -24, 7, 2, 0, -4, -16, -18, 28, 1, -2, 31, -5, 0, -11, 8, 19, -11, -13, -24, 15, 8, -23, 11, -2, -16, -5, -33, -5, 10, -21, -11, -11, -21, -16, -5, -6, 6, 4, 1, -30, 11, 0, 6, -9, -16, 18, -12, 0, 4, 4, 8, -22, -3, -1, -2, 18, -23, 21, 8, -5, -20, 8, -10, -16, -15, 11, 0, -3, 15, 3, -20, 12, -9, 22, -37, -3, 20, -17, -16, 18, 14, -24, -31, -16, 16, 1, -17, 18, 10, -20, -6, 19, 3, 11, 9, 17, 2, 0, 12, 18, -2, -3, -23, 3, -9, 13, -18, -16, -30, 22, 8, -6, 7, 24, 10, 11, -16, -7, 8, 33, 5, 30, -10, -10, 0, 26, -24, -15, -5, -10, 2, -7, -6, 2, -10, 1, 4, 25, -12, 25, -10, 14, -22, 26, -19, -18, -32, -20, 7, -5, 1, -25, -13, -5, 25, -25, 1, 20, 13, -3, -18, 20, -24, 10, -29, -1, 3, -10, 1, -22, -8, -23, 14, -24, 18, 8, -5, 16, 8, 21, 8, -10, 7, -3, 7, 9, -12, -1, 24, -48, 13, 13, -17, -2, -3, 16, -13, 11, -16, 17, 0, 28, -31, 20, -12, -1, -14, 22, 0, -9, 6, -1, -14, 12, -25, 1, 12, 25, -7, 8, 15, 2, 17, 16, 5, 12, -3, -2, -16, 9, 13, -14, 6, -4, -10, 0, 2, 20, 12, -22, -13, 17, -8, 11, -34, 22, 1, -18, -21, 4, 8, -9, -7, -20, 5, 17, -5, 7, -11, 2, 23, 17, 10, -13, -8, 20, -12, -8, -8, 5, 14, 11, 5, -3, 17, 21, 19, -1, -6, 2, 12, -16, 13, -14, -6, -12, -4, 6, -8, 8, -23, -8, 0, 4, -21, -8, -1, -7, -7, 2, -47, 44, -11, -7, 9, -17, 21, -12, -38, -10, 6, 14, -3, -30, -11, -15, 28, -21, -22, -9, 16, 0, -38, 16, 20, -26, -16, -10, -13, 18, -17, 26, -4, -16, 15, -17, -17, -10, 18, -17, 11, -18, -3, -4, 10, 18, -15, 0, -9, 10, -5, 19, -7, -22, -41, 7, -52, 42, -12, 2, 17, 25, -27, 11, -26, -11, -15, 8, -14, 16, 11, -15, -13, -2, 11, 28, -7, -23, -21, 15, 15, 2, 12, 5, 11, 11, -35, 14, -4, 29, -24, -14, 9, 6, 8, 28, -11, 4, 13, 16, -3, 13, -22, 23, -6, 18, -24, 19, -9, 0, -20, 64, -5, -11, 13, -9, -23, 28, -11, 24, -2, 21, -23, -2, 0, 43, 18, 36, -35, 10, -9, 28, -8, -8, -12, 16, -34, 38, -11, -14, -6, -5, -11, 13, 6, 1, -15, 19, -11, 2, -28, 11, -23, 32, -3, 6, 13, 26, -15, -2, -13, -12, 13, -23, 5, -7, -28, 22, -8, 49, 7, 19, 8, 16, 1, -2, -34, 22, -9, -8, -17, -15, -9, 23, 1, 1, -13, 18, -15, 11, -1, -13, -16, 23, -9, 2, 14, 27, -33, 1, -49, 40, -1, 4, -4, 29, -4, -6, 13, 1, 2, 1, 16, -15, -8, 17, -32, -22, 2, 15, 13, -32, -1, 7, -13, 12, 17, -19, -2, -4, -18, 14, -25, 5, -9, 31, -16, -21, -4, 11, -20, -10, 10, 3, 8, 7, 8, -16, 6, -5, 3, 0, -7, 18, 23, 26, -12, 3, 10, -17, -8, -2, 15, 13, -15, -19, -7, 15, 16, 30, 10, -1, -5, -17, -17, -6, 11, 0, -29, -31, 27, -21, 13, 14, -3, -13, 13, 6, 0, -2, 17, -30, -15, -21, -9, -23, -10, 5, -22, -27, -20, 31, 10, -14, 4, 14, -11, 7, 8, -26, 15, -9, 15, 6, 0, -10, -10, -7, 19, 33, 6, -4, 16, 18, -11, -24, 4, 12, 13, -7, -5, 11, -2, -10, 6, -14, 4, -1, -12, 15, 12, -3, -20, -12, 2, -18, -10, -20, -14, 10, -14, -2, 15, 17, 17, 5, -7, -13, -3, -19, -2, -13, 8, 6, 1, 26, -6, -7, -13, 21, -6, 18, -3, 16, 10, 4, 6, 29, 9, -8, 11, 8, -13, -7, -1, 0, -17, 17, -1, -20, 0, 12, -9, 17, 20, 8, 3, 6, 9, -12, 8, 39, 16, -12, -16, -5, 19, 16, -15, -13, -21, 7, -2, 10, 2, 7, -24, -18, -12, -6, -14, -13, -6, 3, -19, -7, -14, -23, -21, 9, -6, -15, -8, 3, -8, 1, -13, -3, -13, 1, 8, -7, -7, 13, -8, -6, -14, -17, 6, 9, 10, 4, -4, -19, -13, 18, -8, -26, 8, 11, -9, -5, -10, -4, -13, 6, -6, -14, -7, -21, -22, 14, 3, -4, -13, -27, -20, 3, 10, -31, 0, -21, 17, -10, -13, 13, 7, -6, 9, -33, 14, -14, -2, 0, -6, 11, 2, 19, 1, 0, 3, 24, 16, 20, 23, -5, 11, -11, -3, -15, -8, 11, 5, 10, -5, 27, 8, 0, 0, 35, 15, -21, 0, 8, -12, -15, 15, -5, 3, -8, 1, 4, 4, 5, 4, -10, -9, 23, -15, 25, -17, 2, -14, 26, -4, -12, -11, -15, -5, 9, -6, 5, -22, 16, -17, 17, -13, -5, 5, 1, -10, 1, -9, 12, 13, -4, -6, 2, -1, 18, 8, -16, -13, 5, -3, -6, 1, 18, -5, -18, 8, -5, -21, 9, -17, 11, 2, 0, -11, -10, 24, 3, 9, 39, 16, -18, 2, 12, -18, 15, -2, 8, 11, -20, -20, -23, -14, -15, -7, -40, 4, 19, -15, -11, 8, 17, 20, -2, -4, 1, -9, -1, 6, -1, 18, -17, -16, 12, -16, 5, 9, 27, -12, -15, -11, -8, -23, -5, -5, -1, 22, 26, 11, 9, 4, 17, 13, -10, 10, 6, -19, -17, 17, 13, -1, -5, -14, 3, 3, 19, -24, 10, -18, -5, -22, -11, 4, -22, 11, -6, -25, -32, -7, 25, 19, 1, -16, -22, -6, 6, -11, -39, 0, -2, -10, -10, -22, 37, 6, 7, -7, -21, -4, -6, 36, -3, -22, -11, -9, -26, -13, 19, 19, -13, -7, 21, -12, -20, -5, 12, 12, -7, 9, -4, -7, 13, 16, 28, -21, -27, 12, -13, -19, 15, -3, 27, -13, -19, -12, 19, -4, -16, 3, 24, -27, -5, 4, 16, 14, 19, 9, -14, 7, 18, -13, -25, -11, 2, -10, -5, 9, 18, 9, -3, -14, 0, -4, 14, 13, 9, 10, 24, -20, 5, 11, 24, -1, 7, -8, 15, 14, 6, 4, -3, 12, 7, -22, 11, -12, -15, -13, 25, 14, -4, 6, 16, 9, 8, 16, 24, -13, -9, 16, 8, -2, -14, 4, -28, 20, -40, -3, 30, 9, 28, 9, -20, 25, 12, -8, -41, -4, -54, 4, -8, -26, -66, -2, 18, 4, 18, 15, 34, -16, 20, -33, 30, -7, -1, -19, 11, -25, 3, 3, 0, -20, 15, -15, -19, -4, 1, 22, 3, -12, 8, -18, 18, 34, -25, -18, 18, 6, -8, -12, 22, -2, -20, -26, 22, -17, -19, 16, 36, -1, -15, -35, 6, 18, 20, 11, -2, -7, -18, -17, -26, -3, 8, -11, 5, -13, -16, 10, -19, 17, -3, -2, 34, -18, 3, -5, -22, -3, -23, -19, 36, 0, -3, -15, -11, 6, -44, -23, 23, 12, -51, -13, 1, 4, 21, -10, 11, 3, 2, -4, -2, 1, 36, -16, 3, -10, -17, 7, 12, 16, 17, -21, 38, -26, -19, 2, 13, -13, 11, 16, -33, -3, -27, -15, 7, -11, -42, -2, -16, 13, -59, 16, -57, -23, -5, -11, -3, -28, 14, 37, -17, 15, 23, -12, -9, -22, 1, -27, -8, 3, 17, -20, 37, 10, -9, -23, 8, 11, -18, 13, 0, -1, 5, -2, -9, -20, -1, 4, -1, -1, 0, -16, -3, 5, -23, 1, 11, -15, -28, -6, 21, -11, 8, 17, -39, 18, -21, 23, -8, -21, -48, -17, 4, -1, -37, 0, 22, -3, -9, 15, -20, 14, 9, -1, -15, -31, -15, -22, 1, -3, -15, -2, 4, 4, -22, 5, -4, -19, -10, 3, -8, -4, -5, -12, -13, -7, 2, 21, 2, -33, 10, -7, 2, -1, -14, 4, -37, -17, -16, -37, 6, 32, -29, 29, -32, -27, 12, -1, -2, 3, 8, -6, 10, 13, -8, 20, -6, -13, -15, -10, 12, -1, 8, -11, -16, 10, -13, 22, 2, -21, -11, -8, -4, 6, 0, -10, -28, 11, -19, -12, 0, -8, -8, -23, -25, 12, -8, -10, 23, -8, -13, 19, -25, -7, -16, -9, 9, -2, -5, 31, -19, -9, -16, -9, -39, 19, -6, -7, 5, -20, 17, -34, 0, 5, 4, 46, 8, 3, 21, -24, -3, -5, -18, 6, 27, 16, 6, -22, 1, 17, -23, 16, -7, -27, -24, -15, -11, 24, 8, 3, 4, 1, 1, -23, 7, 29, 5, 13, -6, 4, -26, 1, 2, -5, -4, 5, -14, 19, -7, -27, 18, 0, -14, 20, 1, 20, 12, -14, 1, -14, -12, 12, -9, 27, 4, -1, 10, 5, 7, 10, -3, -10, 12, -31, 2, -4, 0, -19, 6, -8, -17, 6, -22, 29, 16, 1, 30, 3, -2, -4, -21, 18, -13, 3, 12, 3, 6, -14, 20, 19, 26, -3, -20, -13, -12, 18, -29, -13, 11, -12, 3, -6, 6, -31, 11, -15, 5, -10, 34, 0, -5, -40, -4, 9, -9, 15, -11, -32, 13, 33, -4, 22, -4, 16, 9, 0, -16, -2, -7, -12, -16, 12, 7, 12, 20, 5, 10, -6, 1, 22, 6, 4, 1, -24, -19, 26, 4, 1, 3, 27, 10, -12, 22, 2, 13, -19, 1, -5, 2, -22, 18, 8, 15, -25, -8, 26, 19, -13, 20, 13, 15, -10, 6, 21, 33, 28, -6, 18, -13, 4, -5, -18, 23, 6, -11, 11, 1, -20, -14, -29, 6, 35, 13, 13, -22, 14, -5, -20, 9, -8, 9, -48, -6, -16, -19, 16, 11, -20, -9, 1, 14, 12, -3, 15, 18, -1, 31, 13, -2, -22, 5, -10, -26, -27, 0, 24, -16, 3, -5, 18, -9, -9, -2, 3, -5, 2, -1, 10, 5, -6, 7, -7, -13, 5, 9, 0, 17, -5, -17, 33, 54, 17, -5, -2, -10, -12, -10, -4, -8, -4, -25, -1, -13, -17, -9, 27, -12, 28, 5, 11, 6, 3, -28, 5, 21, 11, -11, 13, -24, -10, 8, -6, 2, 9, -12, 9, -28, 10, 15, -4, 1, -19, 28, 27, -10, -7, -35, -2, 5, 6, -18, 14, 29, -13, -15, -15, -32, 21, 3, -17, -15, 27, -19, -15, -10, -9, 8, 16, 23, -1, -19, 16, -11, -30, -3, -5, -8, 30, 7, 24, 4, 5, -16, -26, -5, 2, -16, 5, -18, -6, 4, -1, 4, -27, -17, 21, -20, 5, -3, -32, -7, -26, -4, 6, 18, -20, -11, -11, -20, -18, 24, -11, -18, -23, -10, 19, 2, 4, 13, -22, 13, -1, -10, 4, -13, -2, -13, -2, -24, 0, -9, 7, -17, -22, -9, -13, -18, -9, 7, -42, 8, 11, 12, 0, 17, 28, -23, -4, -2, 13, 5, 10, 7, -28, 39, -6, -35, -5, -15, -11, 22, 11, -14, -3, 3, -46, 27, -11, -2, -25, 11, 27, 0, 3, 0, -11, 4, 0, -4, 13, -1, -34, -19, 6, -8, -8, 15, -16, 5, 10, -13, 34, -15, 18, -2, 21, -4, 3, -6, -11, 4, 23, -24, -32, -2, -6, 14, 27, 17, -14, 4, -32, -5, 4, -8, -1, -2, 46, -6, -30, 2, 16, 6, 35, 11, -23, -12, -2, 7, -3, -24, 28, -8, -17, 6, -39, -27, -14, 16, 18, 16, 6, -37, 9, -30, 7, -4, 26, 48, -16, -15, -30, 3, 16, 9, 15, -11, -26, -29, -19, 29, -23, 6, 14, -21, -19, -6, -16, 22, -5, -15, 53, -6, -17, -8, -29, -16, 18, -15, 39, 5, 2, -29, -10, -32, -29, -15, -11, -9, 5, -19, -19, -12, -3, -20, -6, -8, 42, -20, 5, 3, -7, -22, -11, -12, -2, 1, -15, 8, -11, -1, 22, 12, 32, 0, -18, -22, -26, -22, 11, -3, -6, -30, -3, -2, -25, -17, -6, 16, 7, 15, -28, -1, -14, -12, 0, 5, 18, -19, -12, 11, 5, 7, -5, 4, -33, -6, 11, -23, -16, -35, 1, 1, 17, -5, 2, -8, -12, -44, 15, -6, -16, -4, -17, -26, -20, -34, -8, 6, 12, 5, 10, 11, -16, -25, -9, -16, 55, 33, 9, -18, 11, 15, 6, 10, 2, 8, -17, -14, -29, 2, 26, -22, -1, -9, -7, -2, -10, 2, 15, 15, -24, 18, 0, 5, 7, -5, 13, -12, 7, 3, 16, -12, -46, 2, 13, -18, -4, 5, 7, 35, 8, -9, 1, -13, 10, -7, 20, 0, -14, -21, -4, -13, -8, 17, 1, 8, -13, 32, 3, -18, 15, -24, 2, 3, -9, 3, 10, 9, 3, 18, -13, 1, -18, 4, -16, 22, -11, 22, 8, 3, -7, 1, -9, -5, 13, 21, -17, -14, -10, -6, 0, 10, 1, 0, 13, 9, 20, -8, 3, -31, -12, -15, 21, -18, -3, 9, -30, 3, -29, 0, -9, 28, -10, 2, 12, -11, -20, -29, 3, -5, 10, 12, 24, 4, -23, -13, -6, 8, -22, -3, -3, -8, -11, -26, 13, 25, 0, 33, -2, 14, 6, -21, -10, 12, -2, 4, 4, 13, -29, 16, -3, -7, -15, -21, -14, -10, 12, 16, 14, 9, -23, -19, -30, -15, 2, 12, -6, 44, -1, -6, -27, -11, -20, 6, -11, 12, -10, -8, 7, 13, 8, -1, -21, -22, 6, 2, 24, 38, -30, 6, -4, 42, -27, 3, -25, 31, -15, 2, 6, 3, 12, 18, -18, 3, 1, -36, -8, -18, -5, -9, 33, -4, 21, 6, 26, 26, -22, 13, 2, 4, 14, -2, -15, 0, 45, 19, -5, 12, -9, -13, -15, 9, 4, -9, -14, -27, -17, 16, -5, 5, 8, 19, -7, 11, -5, -8, -4, -28, -23, 0, 5, 1, 8, -1, 27, 0, -12, 16, 22, -6, -7, -4, 3, 0, -4, 26, 6, -20, -13, -9, -2, -7, 0, 12, -1, -7, 12, 6, 8, 25, 16, -7, -28, -11, -20, -11, -19, 6, 23, -7, -22, -9, 26, 12, -4, 31, -8, -12, 10, -21, 22, -6, -22, 22, -13, -10, 11, 0, -8, -20, 27, -17, 23, 16, 0, -16, 10, -18, -10, -8, -27, 29, -20, -10, -19, 0, -5, -1, 11, 12, -15, -14, -10, -5, -25, 28, 0, 12, 7, 33, -20, -21, -9, 10, 24, -17, -10, -6, 20, 6, 28, -15, 30, 10, 22, 12, 19, 6, 35, 27, 17, -13, -4, 22, -9, -26, -21, 26, 5, -7, -15, 21, -10, 21, 8, 10, 17, 1, -3, -16, 2, -34, -26, -21, -16, -9, 13, -9, 24, 6, -6, 18, 28, -11, 11, 10, 17, 13, 25, -2, 6, -11, 14, 2, 22, 32, 9, -19, -27, 13, 38, 2, -33, 0, 7, -2, -8, 15, -16, -5, 18, -14, -28, 7, -8, 6, -8, -11, -18, 38, 10, 1, -13, -39, 27, 19, 2, 3, -35, 21, 6, 17, 26, 16, 0, -25, 5, -24, -21, 16, 13, 29, 6, -19, 12, -30, -9, -23, -5, 13, -19, 25, 5, 3, -29, 32, -21, -4, 3, 22, -9, -28, 13, -2, -25, -14, -16, 52, -8, 31, 0, -25, 4, 9, 21, -15, 5, -9, 4, -12, -31, 15, 12, 19, 11, 8, 13, 4, 1, -18, -22, 27, 24, -24, 3, 5, -6, -17, 9, -6, -10, 4, -6, 5, 6, 22, 1, 7, 0, 8, -32, 48, -18, 8, -45, -7, -2, 11, -8, 31, 26, 34, -19, 16, -4, -22, 13, 5, -10, 2, 27, 12, -27, 5, 36, 12, 1, 16, -7, 1, 11, 8, 15, -21, -9, 47, -29, 29, -18, 11, -15, -14, 26, 10, 12, -20, -18, 7, -17, -30, -8, -14, 21, -1, 33, 8, 0, -27, 9, 7, -33, 50, 0, 27, -4, -33, -15, -10, -11, -8, -19, 3, -9, -12, -12, 8, 33, -10, -21, 33, 27, 1, -14, 7, 16, 1, 7, -13, -11, -5, -13, -1, -14, 2, 3, 16, -5, 0, -2, 1, 10, -15, -46, -7, -34, -12, -4, 18, -3, 18, -14, -15, 8, -6, -1, 26, -8, 21, -3, 6, -17, 36, -28, -20, -17, -15, -5, -5, -6, -35, 19, 37, 9, -17, -10, -10, -23, 9, 31, -22, 19, -16, -30, 7, -9, 25, 7, 50, 37, 1, 4, 24, -20, 5, -8, 4, 34, 10, -19, 14, 8, -12, 35, 10, -15, -5, 11, 11, -13, -25, -30, -13, 23, -7, 18, -6, -13, 6, -2, -6, 6, 0, -25, -1, -24, -24, 10, 25, 47, 24, -27, 4, -27, 11, -6, -26, -25, 17, -1, 8, 13, -13, 12, 6, -15, -4, -17, 25, 15, -16, -7, 12, 27, 16, 17, -5, -5, 6, -9, 16, -23, 3, 2, 10, 0, -16, -16, -23, -16, 25, -5, 17, 8, 3, -19, 19, -31, -12, -11, 15, -14, 3, -5, 22, 15, -19, 5, 11, 6, 15, -4, -22, 34, -18, 14, 22, 2, 13, 21, -25, 17, 7, -8, 12, -1, 2, -13, -3, 17, -19, -8, -3, 24, 9, 11, 30, -39, 23, 29, 13, 5, 12, 28, 1, 1, -1, -20, -11, 10, 8, 22, -8, 13, -16, 11, 31, 5, 17, -1, 20, 6, 1, -47, -30, -4, -3, 1, 18, -16, 21, -10, -13, -4, 2, -5, 6, 39, -13, 0, -1, -5, 21, -24, 3, 22, 21, -9, 13, 11, 7, -20, 13, 6, 0, 25, 16, -14, -10, 8, -6, -10, -8, 22, -15, -14, 21, 19, 8, -2, 10, -5, 4, -4, 4, -21, -1, -10, 2, -4, -37, -7, 5, 17, 6, -34, 14, -20, -13, 24, -27, -16, -4, -15, 6, 8, -18, -8, 23, 2, 10, -5, 7, 12, 7, -12, 0, -10, 12, 2, -21, -1, 36, 30, 20, -2, 7, -27, 17, 15, 19, -23, 14, -7, 16, -8, 1, 36, -13, 12, 8, -20, 17, 7, 14, -15, 16, 4, -26, 20, -23, -17, -8, -7, -6, 11, 29, 10, 18, -20, 10, 17, -11, 19, 25, -5, 15, 5, 11, -20, -11, 21, 4, -16, 12, -27, 10, 2, 18, -4, 11, -26, 8, -25, -17, 21, -21, 1, -8, 15, 19, -8, -6, 16, 25, -4, 20, 19, -8, -29, -14, -23, -22, -1, 14, 9, 5, 2, 8, 8, -17, 3, -14, -6, -10, 49, -15, 0, 0, -19, 12, 6, 7, -1, -23, -20, 10, 2, 9, -6, 35, -28, 3, -9, -10, 7, -39, 8, -4, 19, 9, -11, -26, -4, -15, 35, 5, -22, -6, -21, -3, 20, -21, 10, 8, 35, 12, -17, -26, 14, 2, 2, -28, 21, -5, 11, 13, -7, 11, -22, 19, 1, -3, -20, -10, 18, -4, -3, -20, -2, -18, 11, 0, 1, 5, -8, 10, -18, 0, -5, -11, 17, -11, -21, 15, 4, 18, 19, 19, -13, -2, 16, -21, -1, 18, 5, 2, 7, 4, 16, 6, -1, 9, -8, 4, -23, -25, -1, 4, -14, -23, 17, 9, 11, 12, -9, 0, -7, -44, 6, 11, -16, -4, -16, 1, -7, -2, 22, 40, 3, 1, -13, 4, -39, 0, -11, -28, 14, 20, -3, -17, 17, -6, 29, 25, -21, -10, -15, 10, 5, -25, 7, 20, -20, 8, -32, 17, -22, 3, -15, 17, 19, -12, -11, -2, 16, 15, 5, 25, 14, 17, -29, 5, -28, 14, 0, 15, 9, -27, -19, 3, -16, 0, 24, 19, 18, 2, 6, 2, 16, -21, 2, -17, 14, -18, 23, 15, 1, 40, 5, -11, 6, -3, -6, 14, -11, 1, -27, 7, 15, -19, -17, -5, -2, 2, -13, 21, 14, 11, 23, -13, 3, -4, -7, 7, -2, -22, 1, 11, -13, 15, -14, -16, 18, -20, -17, -11, -8, 19, 26, -19, 9, 21, -6, 11, 24, 2, -10, -38, -3, 14, 8, 19, -18, 1, 1, 4, 9, 7, 22, -17, 10, -19, 15, 2, -7, 3, 23, 1, 2, -2, -21, -4, 6, 23, -19, 0, -19, -29, -9, -7, 19, -40, 10, 9, 13, -3, 13, -12, -14, -30, 25, 11, 8, 24, 18, 14, 2, -7, -11, -23, 23, -13, 6, -3, -20, 24, 3, 16, 1, 4, -4, -6, -2, 13, -10, 11, 34, -15, 20, 13, 14, -47, -1, -12, 33, 11, -6, -16, -4, -13, 4, 26, 19, 15, -1, -7, 17, 23, 0, 24, -15, -13, 3, -17, 2, -11, 9, -6, 36, -8, 17, -18, -3, 12, -12, 17, -6, 17, 7, 9, -12, -1, -37, 29, -9, 4, -34, -12, -38, 20, -19, 26, 8, 15, -5, 26, -11, -12, -2, 19, 3, -26, -4, 13, 16, -5, -19, 13, 22, -20, -14, -4, 10, 24, -14, 21, -8, 17, 21, 0, 11, 28, -11, 10, -1, 10, -1, 30, -8, -2, -15, -14, -6, 1, -38, 15, -22, 31, -43, 40, 4, -1, -15, 11, 8, -3, -15, 23, -22, 26, -23, 19, -17, 15, -19, 5, -21, 16, -20, 10, -34, -8, -17, 17, 5, 29, 19, -8, 1, 28, -19, 4, -10, 11, -4, 6, -23, 1, -3, -3, -12, 13, 7, 15, -5, 3, -14, 17, 6, 1, 5, -28, 15, 12, -26, 27, -20, -27, 33, 36, -14, -1, -9, -27, -12, -4, 9, 19, -15, 8, -3, 2, -3, 4, -25, 26, 15, 32, -13, 13, -30, 25, 15, -13, -15, 19, 19, -3, -14, -3, 1, 34, 15, 5, -7, -13, -24, 5, -4, -12, -16, -25, -37, 18, 12, 3, -5, 5, -32, -6, -31, 26, 8, -2, 2, 14, -10, 6, -9, -2, -27, -30, 17, 21, 12, 19, -25, -16, -21, -3, -2, -24, -5, 6, -2, 18, -11, -2, -37, -7, 28, 4, -6, 7, -14, -18, -12, -4, 15, -32, 19, -13, 19, -8, 15, 32, -4, 3, -18, -14, -16, 24, 16, -14, 21, 15, 26, -25, -10, 14, 22, 18, 7, -15, -46, 55, -2, 6, -17, -16, 0, 9, 12, -17, -12, -1, -6, -31, 0, 24, 22, -12, -6, 20, 4, -18, 21, 3, -13, -5, -9, 10, 22, -9, -6, 4, -11, -16, -26, 16, -7, 10, -23, -7, -26, -11, -20, 18, -5, -17, -12, -7, 13, 20, -7, 23, -17, 20, 3, -23, 13, -2, 8, -6, -11, 1, -26, 18, 0, -7, -22, 14, -18, -23, -24, 32, 28, 4, -18, -2, 40, 6, -1, 7, 16, -1, -9, -8, 6, -3, -4, 2, 13, 7, -31, -9, -6, -8, 7, -17, 19, -18, -13, 11, 3, 2, 19, 3, 8, -3, -5, 12, 14, 1, 32, 22, -1, 25, -21, -12, 16, -6, 5, 21, -3, -15, 2, 9, -24, -2, 18, 37, -24, 7, 6, 29, 14, -24, -33, -14, 6, 1, 15, -30, -16, -7, -11, 14, 19, -12, 6, 17, 7, 1, -18, -15, 15, 20, -14, 0, -22, -5, 13, -22, 14, 13, 23, -32, -7, -21, 23, -8, 14, -1, 34, -8, -28, -28, -19, 28, 24, -36, -17, -8, 11, -3, 5, -7, 0, -26, -23, 8, -20, 46, 9, -18, -5, 31, 11, 5, -2, 5, -9, -6, 19, -8, -9, -7, -4, -21, -40, -14, 0, -20, 30, -14, -11, -13, 12, 3, 22, -13, -39, -15, -31, -19, -6, -2, 14, -20, -2, -13, -17, -34, 27, -16, -13, -31, 28, -12, 15, -1, -15, 1, -11, 17, 17, 19, -49, -18, 17, -8, 33, -36, 21, -7, 21, 14, 21, -12, -19, 16, 25, -14, -8, 16, -21, -12, 8, -10, 7, -12, -2, -32, 7, -33, 37, -16, 4, -21, 21, 12, -48, -57, -7, 10, 6, -54, 33, 3, -10, 1, 4, -6, -10, 13, 1, -17, 21, 5, -4, -13, 2, -17, 14, 2, -11, -1, -24, -22, -12, -29, 0, -30, 4, 11, -12, -31, 9, -16, 11, -4, 24, 7, 24, -6, -14, -6, 10, -16, 12, -35, -1, -6, 11, -23, -9, 7, -3, -14, 14, 0, 19, -1, 8, 2, 23, 14, -14, 5, -2, -7, 17, 26, 3, -5, 14, -7, 20, -3, 6, -1, -8, 24, 3, -12, 10, 29, -13, -41, 17, 15, 30, -54, -40, 18, 2, 17, -17, -4, 6, 2, -5, 10, -5, 17, 14, 9, 28, 22, 7, -30, 19, 10, -21, 15, -20, 24, -47, 24, -17, -15, 19, -40, -31, -1, 14, -30, 4, -22, 12, 6, -2, -22, -27, 3, 0, -5, -15, 1, -22, 32, -11, -7, 6, -5, -6, -10, 41, -1, 9, 17, -3, 18, 5, 0, 4, 0, 22, 16, 14, -17, -7, 8, 39, -47, -6, -30, -1, -12, 5, -19, -10, -13, -15, -14, -3, -15, 5, 24, -8, -37, -16, 15, 9, 6, 15, -22, 31, -17, 27, -18, 15, -5, 4, -25, -11, -4, 10, -45, 17, -21, -12, 11, -12, -1, -19, 0, 21, -41, 6, 16, -8, -37, -22, 11, -11, 20, 17, -44, 2, -7, -6, -34, -17, 5, 1, -27, 24, -8, 7, -34, 2, 14, 0, 8, 25, 4, 12, -10, 11, -14, -7, -14, 0, -38, 26, -24, 22, 19, -13, 10, 28, 6, 7, -18, -2, -24, -10, 0, -19, -13, -16, 5, 10, 26, 16, -27, 4, -2, 4, -13, 4, -16, -3, -8, 19, -21, -4, 23, -6, -24, -2, 51, 42, -3, 19, -7, 25, -3, 15, 13, 4, -11, -5, -1, 2, -6, 12, -5, 7, 1, -29, 20, 24, 8, 7, 24, -26, 4, 2, -15, -12, 2, -11, -2, -24, 17, -15, -2, 3, -14, -2, 11, -18, -13, 13, -9, 1, 2, 6, -9, 7, -12, -8, -4, 5, -1, -3, -16, 13, 26, 3, 33, 5, 3, -4, 17, -21, 14, -7, 15, 12, 18, -22, -3, -25, -29, -24, 16, -4, -12, -1, -5, -30, 2, -14, -14, 7, 8, -4, 15, -6, -27, 13, -3, 14, -23, 2, -14, -1, 28, 11, -20, 13, -18, -9, 48, 20, -17, -8, -36, 20, -19, 3, -20, -26, 7, -6, 3, 9, -17, -22, -9, 25, -13, -1, -7, 5, 2, 10, 18, -14, -19, 23, 0, 10, 22, 16, -26, 5, -42, 2, -12, 18, -6, 30, -4, 24, 25, -24, -17, 1, -5, -9, 15, 11, 16, 4, 17, -9, 19, 9, -7, 16, 2, -21, -19, 14, 19, 10, 9, -19, -2, 10, 28, 7, -15, -2, 1, 7, 0, -4, -20, -6, 8, 21, -11, -21, -16, 2, 14, 29, -1, 11, 9, -10, -17, -16, 18, 14, 13, 24, 5, 4, -8, -14, -21, 30, -3, 11, -2, 8, -21, 14, -52, -4, -8, 10, -13, 10, 3, -14, -26, 4, -5, 19, -5, 1, 24, -7, 4, -4, -21, -1, -7, 8, -7, -7, -23, 15, 17, -4, 5, -4, -4, -3, 43, -13, 2, -12, 18, -11, -4, -6, 26, -11, -19, 4, 4, -14, -4, -9, 2, 11, 16, 0, -2, 10, -25, 11, -13, 12, -15, 18, 7, -10, 8, -21, 8, 26, 6, 33, 5, -12, -9, 13, -53, 22, 10, -7, 19, 2, -11, -1, -45, 14, -5, 10, 8, -7, 18, -23, -12, 10, -14, 28, 2, -7, -43, 17, -25, 8, -8, 46, -5, -1, 8, 6, -3, 24, -2, 16, 7, -13, -4, -20, 16, 5, 15, 0, -17, 6, 8, 20, 13, 2, 13, -6, 8, 10, -22, -19, -23, 20, -19, -2, -23, 5, 5, 9, -2, 15, 8, 14, -9, 4, 2, -17, -4, 1, 12, -14, 15, 16, -5, -4, 11, -14, -7, -13, 5, -13, -19, -17, -11, 20, -22, -14, -5, 8, 0, 7, 10, 3, 15, -21, 1, -9, -2, -25, -26, 16, 6, -13, -2, 11, -7, 8, -12, 1, -3, 14, 16, -5, -40, 8, -36, 24, 20, -10, 10, -20, -35, -27, 19, -10, 6, -13, -12, -6, 0, 11, 0, 9, -16, -13, -9, 11, -30, 10, 19, -8, 13, -6, 7, -14, 0, 8, 10, -17, -17, 1, -5, -2, 5, -2, 19, -4, 20, 25, 0, -9, 21, -18, 8, -5, 11, -2, -21, 14, 6, 7, 19, 15, 9, 22, -9, -1, -17, -24, 6, 25, -3, 12, -10, 17, -36, 17, -4, -17, 11, 13, -11, -14, 2, 3, 2, 24, 16, 10, -10, -1, -24, 13, -3, -5, -22, 14, 15, -7, 20, 12, -10, 19, -9, 2, -15, -3, 2, 5, 11, 2, -10, -5, -14, -10, -18, -20, 11, -7, -21, -5, 1, 4, 7, 9, 4, 22, 3, -12, -17, -6, 13, -21, -10, -9, 11, -3, -21, -11, -10, -14, -14, -12, 10, 11, 15, 7, 11, -9, -23, -16, 14, 3, -15, 3, -12, 5, -36, -15, 15, 8, -4, -1, 7, -10, 13, -7, 9, 2, 15, 6, -11, -11, 8, 11, -19, 5, 12, -17, -13, -7, 28, -6, -8, -1, -19, -12, 31, 7, 2, -5, 18, 15, 14, -3, -5, 14, -8, 5, 5, 14, 1, -1, 14, -8, 16, 12, -9, 9, 9, 15, 22, -11, 3, 7, -16, -22, -9, -20, 11, 12, -10, -19, -7, -5, 3, -7, -10, 6, 29, 0, -8, 24, -5, 6, 5, -18, -25, -13, -17, 33, 5, 8, -22, -18, -15, -23, -11, 13, 1, 1, 9, 8, -6, 2, 15, -15, 10, 10, -3, -1, 12, -28, 7, -24, -9, 19, 28, 18, -19, -7, -24, -31, -17, 0, -14, -16, 4, 14, 21, 15, -19, 7, -30, 8, 6, -15, 8, 19, 5, 8, 15, 6, 13, -27, -4, -6, -13, 6, -10, -17, -7, 6, -1, 20, -19, 15, 5, 7, -34, 7, -25, 18, -1, -18, -19, 14, 10, -18, -11, -8, -11, -21, 11, -12, 4, -14, -9, -6, 10, -6, -32, 7, 15, -17, -22, -20, 13, -18, 5, 9, -6, -28, 14, -21, 14, -6, 5, -6, -33, 6, -3, 0, -22, -3, -9, -5, -29, 8, 15, -9, 3, 10, -4, 11, -6, -30, -22, -2, 7, 19, -5, 5, 18, 6, 12, 2, -12, -1, -10, -8, -4, 12, 14, -14, 17, -18, -27, 3, 3, -26, -2, -4, 8, -7, 3, 6, 11, -23, -1, -8, -17, -21, -1, -3, -3, -6, 0, -10, 15, -12, -29, 19, 9, -26, -11, 27, -17, -3, 10, 20, 8, 7, 8, -1, 4, -13, -11, 17, -16, 13, -6, -35, -15, -21, -5, 9, -12, 17, 2, 25, -21, -18, -20, -7, 2, -13, -23, -7, 4, -8, -7, 15, -13, 7, -11, 27, -9, -7, -7, 0, -16, -17, -15, 6, -6, -14, 23, 9, 18, -11, 7, -27, -15, 3, -10, -2, 6, -10, 3, -19, 15, 9, -11, 7, -18, -15, -10, -9, 12, 6, 9, -3, 9, 7, 5, 19, -21, -5, 16, 3, 47, 0, -17, -22, -23, -14, -13, 6, -19, 13, 2, -16, -20, -3, -3, 7, -31, -13, 17, -5, -18, 11, 30, -8, 18, -3, -23, -3, -2, 17, 15, 10, -24, 6, 17, -13, 13, -21, -29, 2, -49, -11, -10, -3, 9, -8, -13, -5, 30, -7, -4, 50, -11, 14, 24, 3, -69, 9, 0, 34, -16, -15, 21, 8, 0, -5, 3, 12, 3, -20, 17, -14, -8, -10, 0, -2, 6, -1, -63, 20, 10, 8, -15, 17, 18, -17, -16, -1, -43, 15, -2, 10, -19, -8, -14, 14, -9, -4, -9, 5, 14, -20, 36, -7, 23, 15, 2, 18, -17, -9, 22, -1, -30, 12, 2, 7, -9, 7, -2, -10, 0, -12, -23, -13, -11, -6, -11, 16, 24, 0, -15, 18, -4, 10, 1, -1, 8, -10, -18, -17, -20, 14, -10, -9, -17, -5, 12, 12, 18, 8, 22, 13, -7, -3, -11, -18, -11, 5, -30, 3, -25, -8, -24, -1, -12, 2, 24, 0, 19, -19, 7, 7, -15, -10, 23, -1, -26, 2, -24, 0, 0, 1, -11, 19, -15, 5, -12, 6, -4, 2, 6, -2, 7, 7, -15, -3, -16, 9, -1, -8, -6, 25, -8, 0, -19, 0, -32, -12, 5, -5, 3, -2, 7, -5, -30, 3, 18, -20, 2, 9, -24, -5, 22, 9, 16, 9, 15, 9, -16, -19, 10, 5, -61, -19, 10, 5, -1, 3, 17, 1, -7, 5, 7, -5, 12, 3, -18, -5, 28, -14, -9, -2, -19, 0, -2, -2, -32, -32, 8, 9, 8, -13, 7, -2, 7, -42, -4, 3, -5, 5, -21, 12, 11, 2, -15, 13, -5, -17, -4, -6, -35, -6, -23, -13, -8, -23, 17, 4, 13, 19, -23, 7, -15, 12, -7, -15, 9, 2, 15, 20, 13, -3, 13, -11, -29, 14, -1, 1, -10, -22, 26, -24, 5, 21, 9, -16, -6, 2, 20, -12, -13, -16, 9, -13, 6, 13, 2, -11, 8, 10, -21, -15, -18, 6, 9, -13, 40, -12, -19, 17, 2, 5, 14, -4, -33, -10, 2, 3, 11, 3, 5, 9, 20, -1, -4, 5, -12, -15, -57, -7, -10, -19, 14, -10, -20, -20, -2, 14, -26, -15, 17, -18, -13, -16, 29, 18, -6, -11, 7, -7, -23, -16, 33, -2, -8, 12, 1, -14, -8, -12, -3, -20, -21, 10, 11, 10, -14, 7, 33, -27, 27, 70, -7, 9, -12, -16, -26, 4, 4, -11, 0, 23, 5, -12, -13, 6, -12, -33, -22, 9, 14, 10, -10, 1, -9, -11, 14, 31, 18, 13, 0, 8, -11, 16, -15, 1, 9, -20, 20, -22, -20, -6, -9, -20, -7, -22, -1, -13, -23, 3, 15, -3, 7, 18, -41, -17, 8, -43, 8, 25, -10, -13, -34, -19, 28, -9, -17, 19, 6, -16, -15, 11, -36, -19, 8, 3, -9, -21, -19, -26, 21, 5, -18, 13, -10, 1, 8, -20, -11, 14, -17, 8, -1, -21, -9, 4, -43, 14, 5, 1, -1, 0, 3, 16, -21, -7, -16, 20, -13, -19, -13, -5, -25, -4, -23, 35, 5, -6, 20, 0, -17, -5, 13, -1, -5, -14, 10, -7, -11, 6, -4, 14, -4, -11, -27, -5, -17, 18, 17, 27, -14, 3, -19, -25, -1, 11, 9, 15, -7, -13, -4, -11, 2, 13, 1, -11, -24, -12, -10, 3, -7, 22, -3, -20, -24, 2, 7, -2, -13, 12, -20, 21, -14, -19, 4, -7, -23, 16, -20, 25, 0, -16, -35, 11, 30, -13, -1, -12, 4, -11, -7, 5, 0, 3, 18, 22, -11, -23, 11, 11, 3, 30, -18, -9, -23, -20, 27, 3, 13, -3, 15, -7, 15, -13, -16, 15, -12, 27, -9, 13, 22, 9, -29, -4, -36, -18, 13, 22, 11, -13, -19, -13, -29, 18, -4, -10, -7, 6, -13, -5, 6, -12, -3, 8, -12, 11, -43, 3, 23, -26, 1, -11, -17, -9, 23, -18, -21, -12, -3, -8, -21, 21, -19, 7, -35, -5, -16, -11, 17, -13, 16, -9, 12, -13, 15, 16, -10, 0, 1, -17, -16, 19, -7, -31, -12, -18, -26, 6, -30, 18, -23, -22, 17, 13, -5, -10, 23, -12, 6, -38, -20, 18, -11, 17, -14, -14, -4, -11, 14, 3, 8, -21, -21, -13, 16, -20, 2, -16, 11, -4, -10, -25, -3, 1, -1, -14, 3, -16, -21, 5, 0, 26, 7, -7, -12, 1, 11, -6, -13, 1, -22, -6, 4, 9, 8, 6, 1, -14, 0, -4, -2, 17, -6, -21, -1, -1, 3, 5, 10, -19, -10, 19, -8, 38, 14, 4, -21, -12, 21, 20, -1, -14, -10, 11, -13, -9, 11, 29, -4, 22, 0, 1, 10, 8, -12, -23, 20, 5, -19, 20, 10, -2, -32, 30, 4, -14, -2, -15, -21, 14, 5, -6, 9, 16, 16, -14, 11, 5, 12, -20, -2, -15, 1, -9, -27, -22, -6, -8, 6, 9, 10, 13, -12, 4, -4, -16, 2, -11, 11, -7, -20, 2, 7, 17, -18, -8, 3, 21, -8, -8, 2, -23, 15, -22, 18, 15, 2, 19, -26, -18, -1, -22, 2, 10, -6, -15, 0, -2, -1, -3, -14, -22, -18, -8, -8, -1, 7, -14, -1, -13, 4, -16, -40, 6, 4, 14, 17, 14, -6, 11, 16, -1, -1, -16, -14, 6, -19, 17, -17, -22, 7, 2, -5, -6, 15, 1, -21, -3, 15, 19, 16, -15, -13, 19, -24, -4, -24, -7, 9, -6, 7, 7, -8, -1, 10, 23, 11, 3, 1, -11, -2, -6, 17, -3, -7, -2, -6, -10, 19, 6, -19, 3, 3, 1, 16, -23, -16, 21, -7, 8, -1, 0, -6, 15, -6, -15, 12, 4, 15, -9, 6, -15, 3, 46, 8, -2, 14, 8, -10, -9, 33, -5, 12, 21, -18, -2, 15, -15, -19, 9, -1, -7, 3, -9, -13, 20, -7, 28, 0, -2, -21, -21, 1, 8, -7, -16, -9, 5, -15, -19, -25, -18, 19, -21, 19, -6, -17, -18, -18, -15, 19, -17, -14, -21, -12, -12, 5, -11, 8, 20, -13, 5, -16, -7, -4, 15, -32, -7, 7, -7, -18, -18, -7, -4, 6, 6, -18, 9, 4, -11, 9, 4, 6, -4, 15, -4, 8, 19, 2, -8, 5, 3, 11, -21, 7, -16, 9, -10, 35, 8, 11, -13, -2, -17, 15, -4, -43, 23, -20, -7, -5, -15, -12, -11, 5, -3, 8, 0, -3, 11, -3, 9, 28, -5, 10, 22, -23, 7, -7, -19, 16, 19, -24, -12, -19, -12, -2, -26, 11, -26, 9, 5, 7, 10, -8, 4, 0, -9, -15, -16, -24, 15, 3, -11, 5, 9, 10, 28, -13, -15, 14, 8, -17, 26, -10, 15, -4, 5, 8, -6, -11, 13, -6, -1, -12, 10, 4, -16, -8, 5, 14, 14, 7, 0, -14, 4, 21, -6, -23, 0, -15, -27, -19, -19, 6, 3, -8, -9, -7, 8, 9, -1, 15, 3, -23, 7, 13, 2, -15, 7, 3, -23, 6, 34, 9, -23, -12, -9, -2, 30, -21, -12, -12, -17, -11, -16, -14, 30, 0, 3, 5, 11, -2, -10, 15, 11, -1, 28, 17, 1, -27, -7, 29, 8, 8, 15, -18, -12, -8, 15, -1, -23, 14, -12, 17, 4, -9, -10, 14, 6, 1, -33, 5, -25, -17, -1, -15, 10, 3, -12, 0, -18, -6, 13, -11, 57, 7, -29, 11, -2, 10, 15, -6, -7, -6, 6, -19, -19, -16, -20, -10, -17, -19, -26, -15, -10, -9, -1, -14, -15, -8, 12, -14, -21, 4, 16, -21, -14, 5, 18, -10, 11, 3, -4, -12, 16, 5, 16, -24, -9, -3, -9, -14, 0, 5, 13, -2, 11, -32, 2, 20, 7, -6, 23, 13, -16, -8, -22, 7, -4, 0, -25, -11, 14, -22, -20, 10, 0, 16, 36, -22, -18, 3, 15, 16, 1, -18, 12, 10, 9, 16, -5, -2, 3, -4, 17, -12, 8, 23, 13, -13, 19, 8, 26, -9, 6, -18, 3, 15, 4, 5, -24, 17, -19, 3, -11, -4, -15, -12, 41, -14, 17, -12, 11, -18, -2, -15, -7, 13, 14, -12, -22, 8, 17, -2, 12, -1, -15, -30, -17, 3, 0, 19, 14, -11, -5, -6, -8, 1, -20, -11, -9, -22, 0, 5, -23, -8, 17, 16, 23, -6, 3, 3, 11, -19, 23, 16, 26, -22, 13, -1, 19, 6, -12, 7, 16, 2, 6, 9, 10, -11, 31, -7, -8, -3, 19, 2, 10, 6, 27, -19, 18, 15, 1, 17, 21, -22, 15, -13, -19, -4, -7, 17, 2, -22, 16, -12, -12, -24, 11, -21, 15, 14, 52, -10, 0, -3, -7, -15, -12, 21, 25, -6, -7, -7, 12, -17, 8, -22, 6, 5, 26, 4, -6, 19, -13, -15, 26, 5, 41, 13, -17, 22, -10, -13, -1, 3, 3, 7, -10, 1, -2, -33, 20, 16, 56, -15, 20, 2, -18, 1, 8, -11, -3, 6, 2, 7, -12, -9, 31, 16, 4, -16, 14, -19, -9, 19, -23, -1, -12, 8, -17, 31, 1, 35, 27, -2, -11, 17, -20, -15, -15, -30, 3, 10, -7, -8, -16, -25, -1, -8, 9, -4, 12, 2, -1, 12, -18, -3, -3, -5, -4, -8, -12, -7, 2, -5, 28, -8, -21, -13, 8, -3, 11, 8, 25, -16, 5, -10, 8, 9, -11, -39, -3, 3, -13, 1, 3, -3, 5, 11, -31, -8, 8, -17, -16, 20, -13, -3, -15, 14, -7, 5, 3, -18, 12, 4, 9, 15, -9, 14, 6, -4, 20, 10, 9, -8, -2, 3, -3, 5, 12, 8, 4, 18, -27, 7, 6, 6, 7, 6, 23, -6, -5, 13, -3, 0, 18, -19, 6, -5, -9, 0, 12, -32, 8, 19, 2, -18, -5, 9, -5, 12, -23, 1, -1, -19, 9, -6, 0, 23, -10, -37, 6, 0, -36, -14, -4, 1, 4, 16, -24, 3, -24, 9, -15, 14, 2, -27, -33, -14, 27, 4, -7, 6, 2, 15, -12, 11, 18, -22, -14, -26, 14, -10, 13, 4, -14, 7, 8, -22, 20, 18, -1, -5, 0, 6, -15, -9, 15, -3, -3, -17, 20, 13, 9, 1, -15, -1, -4, 17, -37, 9, 6, 18, 9, 0, 38, 14, 9, -19, 14, -19, -13, -6, 3, -4, -30, -1, -8, 1, 17, 24, 14, 16, -23, -3, -20, -20, -13, -4, -10, 8, -3, -7, -14, 1, 12, 32, -15, -11, 0, 0, 8, -13, -19, 7, 25, -13, 22, -3, 2, -7, -12, -2, -13, -8, 38, 17, 1, -1, -11, 12, 44, 6, -10, -19, 12, -1, -4, -19, -4, 3, -26, -20, -11, -11, -11, -8, -1, 6, -3, 17, 13, 8, -9, -15, 41, 12, -1, -20, -4, 11, 13, -16, 34, 12, -12, 15, -2, 24, -16, 23, -8, -17, -10, -22, -13, -1, 10, 19, -24, -11, 28, 17, -6, -16, -6, 16, -6, 4, -16, 15, -16, 3, -12, -35, -30, -18, 29, 0, 16, -3, 3, 29, 20, 4, -20, -23, 0, 6, -17, -10, 33, -19, -5, 14, 17, 21, -12, -18, 58, -20, -3, 20, -7, 17, -17, 0, 8, 9, -2, 19, -19, 5, -22, 16, 54, -18, -4, -17, 9, 23, -17, 2, -19, 8, -17, 6, -1, 4, -2, 3, -26, -21, 11, -7, 5, -11, 4, 17, 8, -3, 48, -19, 0, 30, -13, 25, -11, -8, 33, -20, -7, 30, 2, 30, -16, -14, -35, 15, -2, 2, -4, -8, 18, -5, 5, -6, 5, -2, 10, 6, -15, -4, 18, -8, -25, 25, -13, 16, 25, 14, -12, 18, 2, -9, 0, 13, 18, -3, 2, 0, 5, 10, -6, -17, 2, -6, 41, 1, -21, -7, -21, 6, 9, 18, -18, -5, -17, 6, 11, 14, 9, -9, -25, -5, -23, 20, 6, -13, -17, -4, 8, 18, 8, -15, -1, 10, 1, -6, 2, -21, 6, 0, 19, 25, 29, 4, 20, 8, 4, 5, -21, 0, 62, 2, -10, 3, -13, 28, 12, 4, -1, -18, 3, -19, -9, 16, -2, -10, 7, 0, 38, -14, -18, 23, 18, -23, -30, -7, 2, -9, -9, 10, -14, -11, -24, -12, 46, -19, 10, 10, 15, 8, -1, -6, 26, -20, -13, 9, -5, 16, 44, 0, -9, 19, 15, 1, 14, 23, 18, -5, -29, -1, -9, 1, 1, -8, -1, 0, 18, 7, -18, 3, 21, 13, -17, -4, 19, 5, 12, 14, -2, 2, 8, 17, -5, -18, -6, 17, 0, -18, 22, -14, 76, 10, -1, -7, -4, 23, -14, 5, 14, 7, -1, -5, 13, 18, 10, 11, -21, 14, 8, 26, 15, 9, 10, 14, 21, -14, -10, 11, -1, -3, -20, -12, 18, 4, -18, 22, -10, -1, 21, -16, -6, 6, 5, 10, -22, 24, -3, -2, -20, -5, -17, -14, -10, -2, 0, -4, 2, -17, -1, 1, 2, 34, 10, -14, 11, -24, -8, -2, -11, -9, 10, -11, -14, 5, 21, 32, -16, -8, 36, 16, 5, -12, -4, 22, -7, -1, 19, -16, -9, -19, 8, 6, -8, 13, 14, 12, 43, -6, -12, -5, 7, 28, 23, -19, -15, 5, 14, 13, -2, -6, -29, 7, 41, 9, -19, 5, -20, 28, -10, -18, 21, 11, -12, 1, 7, 13, 3, 17, 7, -14, -15, 37, -13, 16, -29, 13, 5, 7, -7, -6, 9, 24, 2, 8, 3, -20, 3, -14, 0, 2, -4, 19, 5, -4, -9, -8, 20, 24, 12, -3, -21, 19, 0, -6, -8, 4, -20, -18, 28, 5, -6, 8, 16, -3, 1, 9, 7, -10, -19, 37, -3, 4, -2, 18, 6, 19, 17, 20, 11, -44, -14, -16, 4, -14, -20, -40, 10, -31, -12, -11, 0, 3, 10, -14, -14, 8, 34, 0, 29, -14, 12, 12, 3, 23, 9, 3, 0, -12, 5, 2, 15, 26, 9, 3, -12, 2, 20, 54, -5, 16, 40, -19, -8, -8, 13, 38, -1, 12, 23, -14, 5, 17, -10, 11, 18, -7, 0, -6, -18, 10, 10, -16, -17, -27, 5, 15, 1, -24, -4, -32, -5, 8, -23, 47, -5, -26, -46, -8, 4, 11, 8, -3, 6, -7, -13, 19, -18, 9, 7, -22, -18, 72, 13, 30, -39, -2, 9, -20, 15, 15, 13, 3, -20, -5, -5, -16, -3, -26, 8, 17, -9, 13, 17, 2, -18, -23, 30, 42, 2, 47, -6, 14, 2, 9, 5, -9, -23, 29, 12, -23, -9, 22, -18, -14, 17, 0, 15, 23, 22, -31, 1, -2, 12, 14, 2, -28, -17, -7, 25, 7, -8, 11, -7, 6, -15, -31, -12, 12, 23, 13, 1, -30, 9, -7, 21, -18, 9, 6, 6, -9, 10, 18, -2, 27, 5, 1, 8, -18, 14, 8, 18, 3, 16, 28, 7, 16, 23, 8, -1, 15, 18, 33, 5, -10, -17, 10, 13, -1, -31, 37, -2, -32, 5, -22, 23, 11, -3, 15, -8, 11, -4, -8, 8, 14, 25, 25, -5, 36, -14, 34, 1, 20, -39, -7, -5, 9, -3, -36, -5, 16, 25, 23, -3, 19, 20, 22, -4, 10, -12, -15, -13, -11, -14, -15, -11, 7, 7, 8, 6, -19, -19, 19, -13, 12, -7, 6, 13, -26, 1, -10, -13, -5, 0, 24, 6, 14, 3, -13, 1, -2, 24, -16, -11, 0, 17, -9, -2, -2, -8, -15, 3, -3, -21, 16, 10, -12, -16, 21, 12, -3, 7, 5, 9, 22, -13, 2, -3, 21, -17, 15, -16, -4, 0, -14, -3, 15, -11, 30, 4, 22, 5, 22, -21, 42, -20, -19, -41, -12, 5, -13, -21, -17, -6, -18, -8, -7, 8, 18, 10, 6, -21, 5, -5, 6, -11, -14, -23, 17, 9, -8, 22, -12, 5, 35, -19, -12, -12, 20, 18, 4, 11, -18, 18, -17, -11, 9, 8, 7, -10, 25, -15, -10, 7, -29, -27, -5, 9, 25, -9, 31, -8, 20, -26, 5, -19, -6, 15, 27, -18, 10, 22, 5, 0, -25, -11, -12, -20, 2, 7, -39, -18, -5, 0, 14, 16, 23, 26, 57, 0, 21, 11, 21, -5, 2, -37, -18, 25, 25, 15, 3, -5, 10, 3, -17, -16, -21, -17, 4, -11, 17, 8, 10, 13, 1, -9, 26, 17, -22, -18, -9, 14, -7, -17, 11, 12, -16, 13, -3, 18, 14, -21, 9, 3, -2, 35, -17, 20, 15, 10, -23, -11, 32, -2, 20, -40, 13, -22, -19, 5, 5, 35, -26, 20, 9, -9, -1, 12, -17, -12, 6, 29, 19, -9, 12, 7, 6, -20, 16, -22, -2, -5, 16, -19, 7, -13, 6, -26, 11, -8, 17, -2, 13, -22, -17, -6, 30, -19, 7, -5, 17, -23, -14, -6, 22, -6, 31, -19, 9, -35, -36, 1, -6, -19, -3, -2, -8, -8, -19, 9, 18, -22, 7, 14, 4, 10, -18, -1, -14, -4, -11, 9, 27, -7, 8, -5, -15, 16, -5, 11, -10, -6, -10, 24, -16, -10, -20, 10, 6, -28, 16, -35, 24, 14, -17, -18, -13, -21, -25, -20, 2, 3, -12, -3, 23, -5, -34, 12, -12, -23, 19, 10, 16, -1, 0, 22, -10, -4, 9, 15, -13, -21, 0, 51, 5, -13, -12, 6, -3, 32, 33, -3, 14, 3, -2, -18, 14, -15, -14, -18, -2, -5, 10, -21, 15, -4, -18, -17, 32, 12, -14, -4, -1, -12, 27, 1, 28, -12, 3, -14, 31, 16, 12, 12, 3, -4, -14, 5, 3, 4, -15, -1, -30, -1, 27, -11, -24, 52, -6, 27, 17, -10, 6, 3, 23, -1, -10, -12, -6, -22, -15, -4, -7, 34, 7, 12, 7, -4, -8, -2, 13, 30, 20, 9, 31, -12, -22, -20, -27, 23, 36, 17, -6, -16, -15, -1, 1, 30, 7, 3, -19, -10, -14, 5, 11, 8, -21, 19, 28, -17, -9, 2, -5, 16, 23, 15, 43, 3, -11, -18, -25, 37, 3, -11, 19, -2, -25, -21, 11, 23, 7, -13, 2, -14, 17, -16, -1, 24, -2, 25, 5, -22, 14, 12, 6, 15, 13, 10, 2, 21, -22, -11, 22, -3, 1, 27, -25, -2, 18, 1, 0, 8, 24, 25, 16, -2, 11, 6, 6, -11, 24, -4, -5, 4, -16, -23, -27, 23, -1, -6, -10, -17, 4, 2, -1, 24, -8, 9, 10, -5, 2, -19, -25, -8, 25, -23, 20, -18, 1, -6, -13, 58, 5, 23, -2, -20, -10, -2, -13, 14, 13, -30, -17, -3, 6, 4, -22, 10, 25, 26, 45, -19, -32, -11, -32, 2, 31, -11, -12, 8, -18, -1, -22, 9, 21, -7, 28, -14, -12, -4, 3, 9, 14, 14, 13, -13, 19, -14, 18, 36, 13, 0, -9, -19, -12, 16, -3, -7, -5, 24, -5, 15, -6, -21, 20, -18, 40, -29, 37, -20, -21, 14, -36, 5, -4, 13, 7, -20, -25, -1, 41, 12, 14, -16, 35, 6, -20, -10, 28, 12, -2, -10, 12, 11, -8, -20, 0, 23, -7, 8, 20, -8, -4, -6, -37, 24, 14, 8, -11, -10, 0, -12, 16, 8, 33, -15, 14, 4, -17, 18, 14, -8, -5, 3, -18, 13, -34, 12, 16, -7, -7, -14, 21, -12, -11, 18, 16, 22, 19, 29, 31, 9, -17, 0, -13, 6, 10, 1, 13, -22, -1, 6, -12, 11, -14, 10, -14, 5, 8, 0, -33, -8, 6, -7, -13, 19, -2, 0, -10, -21, 12, 25, -15, 16, -19, 8, -3, -11, 0, -1, -17, -6, -22, -23, -7, 38, 17, 14, -8, -21, -13, -12, -10, 4, -9, 32, 1, 11, -35, 14, 32, 0, -19, -21, 30, -16, -20, 9, 7, -6, 11, -7, 28, -18, -20, -8, -9, 0, 0, 25, -22, -7, -10, -11, 2, -13, 26, 3, 8, -12, 45, -5, -35, -1, 34, 12, 8, 12, 20, -7, -47, -6, -4, 14, -16, -4, 5, 13, -26, 16, -10, 25, -6, 16, 22, 7, 28, -25, -5, 29, 24, 1, -24, -9, -11, -17, -11, 11, 23, -1, -2, -1, -12, 8, -4, 1, 5, 11, 0, 14, 6, 10, 19, -20, -9, -20, -39, 17, -14, 20, -19, -21, -29, -15, -33, 6, 8, -2, -27, -29, 4, -5, 2, -6, 0, -9, 11, -1, 11, 0, 34, -20, 0, -9, -1, 5, -8, 3, 4, 6, -11, -31, 20, -23, -2, 13, -6, -3, 17, -26, -2, -11, -21, -5, -12, -20, 15, -18, -5, -23, 1, 14, 10, 11, 2, -15, -31, -6, -1, 9, -13, -5, -22, 7, 21, 7, -3, 3, -13, 8, -12, 14, -5, -26, -2, -8, -16, -8, -3, 6, 13, 13, 20, 20, -9, 1, -3, 41, 0, 17, -1, -8, 6, -21, -11, 18, 13, 16, -1, 12, -9, -17, -9, 15, 31, 14, 1, 1, -8, -11, 17, 42, -2, 18, -28, -14, -33, 15, -6, 13, -12, 38, 14, -20, 24, 4, -3, -17, 27, 29, -20, -7, -12, -8, -2, -31, -21, -14, -14, 19, 20, 10, 3, 15, 21, -10, -15, 5, -24, 10, -20, 26, -9, -8, 20, -5, 13, 13, 5, 6, 3, 10, 31, -15, 22, -20, -5, 26, -2, -5, 11, 10, 18, 13, -8, -10, -14, -8, -13, 4, 6, 12, -12, -10, -10, 62, -35, 17, 5, -11, -14, 37, 2, 5, 7, 16, 19, 2, 4, 22, 2, -23, -27, 6, -10, 17, -5, 19, -4, 25, 20, 0, 22, 3, 29, 5, -11, -9, -7, -16, -26, -18, 6, -5, -4, 12, 11, -6, 5, 17, 7, -3, 6, 33, 18, 8, 2, -2, 11, -41, 25, 25, 26, -18, -10, -10, 1, 6, -8, -6, -5, -21, 7, -5, 20, -20, 9, 13, 27, -20, -4, -22, -10, 21, 11, 5, 2, 12, -1, -9, 22, 25, 12, -28, -17, -14, -12, -9, 27, -1, -3, -28, 29, -8, 16, 14, 47, 7, -36, -25, 21, -6, -21, 11, -9, 17, 6, 21, -4, -4, 10, -9, -15, -15, 15, 19, -7, 10, 18, 13, 14, -20, 5, -22, -14, -17, -11, 19, 13, -1, 4, 2, -14, 10, 10, -9, 1, 6, 31, 17, 15, 13, 17, -1, -16, -10, -34, -5, 4, 1, -4, 0, 13, -7, -7, -11, -5, 5, -14, 0, -9, -13, -1, 7, 7, -15, -2, 19, 26, 14, 12, 21, -1, -10, 7, -22, -11, 0, -24, 19, 5, 1, 5, -10, 5, 0, -3, 19, -8, -10, 26, 15, 10, 19, 16, -20, 22, 16, 18, 19, -5, -6, 42, 19, -38, -13, -19, -18, 14, 15, 9, 8, 15, -15, 5, 17, 7, 28, 32, -5, -5, 17, 25, 17, -5, 22, 24, -14, 22, -6, 5, 16, 35, -13, -22, 17, -6, -15, 10, -22, 11, -21, 8, 14, 12, -16, 25, -7, -13, 26, 44, 8, -20, 14, -6, 11, 4, 12, 10, 43, 4, 1, -27, 8, 1, 11, 6, -1, -10, -1, -24, 2, 23, 0, 25, 39, 7, 20, -22, 5, 21, -11, 2, -14, -9, -2, 5, -2, -26, -14, 23, -1, -9, -20, 4, 3, -18, 31, -19, -8, 26, 13, -22, -5, -15, -11, -11, 13, -34, -7, -5, 17, 15, -3, -4, -13, 17, -9, -4, 6, -19, 12, 17, 3, -5, -6, 5, 1, 24, -5, 0, -32, 6, 11, -10, 10, 39, -23, 6, 1, 17, -12, 5, -21, -4, 38, 23, -6, 12, -17, -10, -4, -28, -5, 2, 10, 11, 8, 11, 3, -3, -3, 5, 18, -9, 16, 32, -19, 3, -9, 4, -21, -9, 17, 5, 14, -6, 4, 25, 0, 1, -6, -6, -10, -10, 8, -3, 14, -5, 7, -1, 17, -5, -11, 7, 23, 18, 18, 23, 8, 29, 10, 9, 4, 10, 2, 3, -7, 9, -23, -19, -14, -30, -10, -21, -10, 16, 3, 10, 1, 20, 8, -3, 5, -7, -4, -12, 25, 9, 2, -15, 8, -17, -12, -12, 2, 12, -5, 7, 5, -23, -8, -16, 1, 15, -9, 11, 1, -14, -16, 22, 15, 5, -11, 8, 19, 4, -15, 28, -13, 3, -9, -15, -17, -30, -16, -1, 27, 20, 10, -25, 17, -8, -16, -19, 1, 17, 16, -16, 6, 8, -26, -24, 3, -30, -20, -28, 21, -15, 10, 5, -16, 24, -7, -11, -14, -15, -2, -11, -9, 14, 6, 9, -5, -36, 6, -3, -7, -1, 7, 19, -9, -22, 8, 17, -17, 20, -3, 1, -9, 2, -4, 25, -17, -10, 10, 8, -2, -21, -13, -13, -2, -21, -2, 5, -4, -10, 9, -3, 2, -14, -15, 1, -6, 10, 13, -14, -6, 8, 7, 27, 16, 8, -14, -15, -12, -25, 9, -5, 1, 21, 24, 16, 12, -13, -3, 4, -13, 0, -1, -6, 4, 27, 17, -1, 11, -10, -7, -1, -13, 1, 16, 40, 0, -1, -11, -20, -15, 4, -10, 10, -20, 21, 15, 30, 9, -12, 9, 11, 16, 12, -6, 18, 0, -18, -11, -13, -21, 25, -10, -15, 1, 0, -11, 12, -16, 5, -6, -16, -3, 7, -1, 17, -4, -3, 0, -15, -21, -21, -13, -7, 8, 3, -18, -7, -15, 3, 17, -11, -8, 8, 13, -14, 13, -3, 14, -9, -23, -11, -24, -17, -8, 16, -16, 20, 9, -5, 16, 0, -24, 10, -11, 29, -6, -12, -4, -6, -10, -14, 1, 12, 17, -9, -5, -23, 11, -15, -20, 7, 12, 10, 19, -10, -38, -19, 2, -4, 4, 3, -8, -23, 10, -10, -19, 24, -23, 9, 5, -36, -6, -9, -21, -1, -20, 10, -10, 2, 0, -13, -13, 19, 5, -11, -3, -17, -27, 9, 11, 15, 1, 7, 18, -11, 19, -21, 5, 6, -19, 0, -12, -22, 13, 9, 18, 24, 15, -2, -3, -11, -15, -26, 11, 28, -14, -5, -1, -4, 21, 15, 9, -5, 3, -8, -6, 0, 8, -10, 13, -4, 17, -23, 20, -7, 16, -5, -7, 0, 7, 19, -42, -16, -21, 9, 9, -9, -9, 5, -37, -1, -14, 2, -24, 2, -5, 3, 9, 14, -12, -9, 11, 13, -13, -22, -31, 11, -28, 8, -19, 1, -20, 26, 14, 0, -4, -29, -11, -17, -15, 13, 20, 0, 7, 19, -23, -19, -9, 15, 10, -31, -16, 1, 12, -16, -8, -6, -18, 30, 3, -9, -2, 23, 19, -6, -8, 9, 10, 20, 13, -8, -6, 7, 7, 7, -22, -16, -20, 6, 4, -1, 3, -21, 34, 25, -8, -14, 8, -9, -3, 22, 13, -3, 9, 0, 0, -7, 8, 2, 14, -13, 11, -4, 8, 9, -6, -11, -31, -6, -5, -13, -6, 2, -15, 15, -1, 29, -13, 11, 8, 8, -8, -22, 27, 23, -23, 11, 20, -17, -8, 8, 5, -10, -16, 0, -22, 10, 26, 7, -6, 5, 3, 0, -13, -16, 12, 6, -6, 19, 8, 23, 12, -4, 2, 14, -2, 0, -18, -5, 12, -8, -25, -5, -15, -11, -1, -11, 19, 6, -26, -8, -19, -23, 20, -21, 17, 15, 6, -2, -27, 1, 7, 20, 8, 3, -5, -34, 0, -17, 16, 1, 9, 22, -44, 6, -16, 14, 8, -20, 20, 9, 1, 0, -11, 15, 5, 18, -6, -16, 8, -6, -50, 1, -22, 5, 12, 17, -13, 7, -22, 0, -6, 21, 1, 3, 4, 32, -15, -5, -7, 27, -2, 16, -38, -25, 5, -1, -18, 26, -22, -7, -29, -6, -9, 4, -8, -5, 7, -18, -6, 5, 23, -8, -22, -4, -16, -13, -24, -3, -36, 23, 21, -20, 8, -1, 6, 12, -4, 4, -17, 2, 6, -9, 8, -15, -14, 16, -22, 6, -20, 16, -25, -23, -9, -44, 17, 6, 4, 4, 0, 26, 17, -13, -6, 21, -21, -21, 11, 11, -11, 18, 10, -13, 5, -1, 5, 9, -28, -8, -15, 10, 20, 9, -32, -14, 0, 2, 16, 21, -10, -4, -55, 9, 10, 1, 14, 5, -18, 12, -42, -14, 27, 15, -8, -33, -8, 16, -8, 27, 1, -12, -5, -8, 0, -3, -11, 5, 14, 26, -1, 6, -17, 2, 10, -2, -19, -24, 9, -5, 14, -19, -16, 2, -2, -17, 6, -14, 13, 13, -5, -2, -5, -12, 12, 14, -8, -23, 6, -25, 8, -22, -13, 10, -6, 11, -22, 29, 7, -14, 19, 0, -11, -1, -7, -11, -14, 3, -4, 28, -4, -23, 6, 0, 9, -27, -12, 33, -7, -3, -18, 8, 6, -43, 8, -7, 7, -12, -30, -7, -32, -46, -16, -18, 12, 3, -16, -6, 9, -17, 2, -7, -6, -6, 20, -12, 7, -16, 5, 14, -4, -5, -17, 13, -16, -23, 12, -17, 7, 18, 6, 24, -19, 0, 6, 23, -3, 22, 7, 10, 6, -16, -19, 12, 15, 9, 3, 13, 10, -5, 2, -1, -20, 23, -29, 15, 4, -18, -9, 19, -3, -6, -23, -6, 7, -26, -13, -6, -18, -2, -8, 1, -14, -34, 13, 27, 7, 5, -15, -13, 13, 6, 3, -9, 7, 24, 10, -15, 0, -30, 0, -8, -20, 25, -7, -31, 13, 8, 0, -3, 14, 33, -4, 12, -18, 2, -6, 4, 7, 28, -8, -13, -9, -6, -1, 4, -2, -4, -31, 19, -3, 25, -19, -11, -2, 7, 18, 10, 11, -8, 9, 27, -13, 12, 4, -5, 22, -5, -19, -4, -22, -18, -19, 25, -13, 8, -5, 29, 16, -18, -11, -8, -10, -27, 13, -20, 14, -4, 13, 0, -3, -16, 10, 13, -15, 7, 5, -43, -15, 5, -9, -23, 0, -5, 7, 25, 18, -16, -10, -21, -3, 5, -8, 0, -33, 37, 1, -21, 17, -15, -17, -9, 14, -13, -9, -15, 8, -5, -53, 18, 11, -24, 13, -20, 5, 2, -28, -9, 22, 10, -5, -4, 4, -9, 21, 8, 15, -6, 16, 14, 10, -3, -36, 33, -2, 21, -20, 1, -12, 17, -8, -10, 15, 4, 18, 15, 7, 12, 11, 13, 3, -8, 18, 17, 4, -15, -6, 12, -11, 7, -9, 10, 2, 18, -7, -2, -21, 33, 2, -5, -7, 6, 5, 20, -3, -20, -16, 26, 9, -17, 3, 19, -14, -14, 7, -21, 13, 5, -1, 13, -28, -3, -12, -24, -11, 18, -48, 15, 8, 20, 0, -11, -5, 27, 4, 21, 6, -30, -15, 14, 5, 19, 1, -2, -19, 1, 8, 11, -17, -8, -17, 3, -15, 22, -2, -8, -21, -15, 6, 5, -20, 3, 8, 23, -12, -11, -24, -5, -9, 9, -1, 9, 15, 11, -21, 32, 0, -22, 10, 9, 5, 13, -35, 3, -27, -20, 17, -9, 4, 13, 6, 2, 4, -12, -21, 10, -18, 3, 23, 13, -1, -11, -1, 6, -17, -8, -18, -6, -6, -16, 4, 10, -5, 1, 1, -17, -18, 2, -9, -7, -2, -37, -1, 17, -47, 13, -8, 1, 11, -10, 4, -22, -21, -32, -21, -12, -6, 16, 2, 1, -8, 8, 10, 2, -21, -19, -3, -40, 8, 7, 13, 16, -10, -18, -2, 16, -3, 14, 13, -9, 7, 17, 0, 6, 20, -4, -11, 9, 18, 22, 6, -14, 29, -17, 8, -15, -6, -18, -8, 5, -47, 21, -16, -3, 3, 13, -3, -10, -27, -1, -12, 0, -15, -12, 2, -23, 12, -15, -24, 0, -9, -21, -4, 14, -17, 0, -12, -2, -23, -20, -31, 14, -15, 23, -2, -5, -9, -21, -17, -7, -24, -17, -2, 9, -21, 19, -1, 34, -8, 17, 12, 17, 14, 13, -29, -11, -10, -10, 11, 9, -10, -14, 41, -24, -13, -9, -8, 6, 3, -24, -4, -12, -5, -11, 13, 6, -14, -1, -29, -30, 1, -10, 1, -30, -14, -11, -16, -7, -1, -7, -14, -6, 9, 40, 22, 17, -17, -41, 15, -18, -4, 8, 19, 8, -20, -2, 11, -14, 11, -6, -12, 5, -36, -9, 18, 16, 17, 7, -18, -11, 31, -15, 16, -33, 15, -37, -8, -12, -41, -18, 18, -18, -16, 15, -15, 1, -18, 7, -2, -5, -6, 14, 7, -21, -13, -20, -13, -3, -14, 19, 45, 14, 8, -16, 17, 6, 16, 16, -12, -30, -1, -7, 11, -30, 8, 28, -29, 7, -43, -3, -8, -1, -13, -19, -5, -4, -31, -21, 7, 3, 1, 15, -5, 7, 22, 13, 14, 17, -10, -3, 30, -11, 24, 9, 8, -10, -9, -33, -18, 19, 5, -1, 2, 6, 10, 15, -16, -4, -35, 1, -16, 5, 17, 12, -9, 10, -32, 3, 18, -24, -16, 16, -40, -26, 7, 1, -8, 10, -17, 0, -12, -28, 8, 15, -5, -1, -14, -18, 13, -7, -29, -12, 8, 20, -15, -17, 21, -3, 7, 2, 21, 33, -4, 11, 39, -15, -15, 4, -8, -5, -13, 6, -8, 17, -10, 18, -19, 19, 6, -2, -8, 4, 21, -13, -15, -2, 27, 11, -3, 18, -9, -26, -22, 13, -15, 11, -5, -13, -6, 14, 47, -1, -9, 12, -10, -32, 10, 16, 3, 3, 15, -9, 18, -31, 11, -5, 36, 3, -23, 5, -4, -22, -5, 0, 14, 21, 8, 10, 12, 0, -3, 3, 15, 0, -17, 2, -15, -16, 12, 11, 21, -1, -24, 5, 6, 11, -8, -12, -27, -14, -17, 20, -6, 3, 20, 9, 3, 8, 16, 28, -8, -26, 7, -9, 9, -3, 17, 15, -9, -29, -6, -11, -18, -22, 9, -7, -2, 16, 0, -5, 31, -5, 3, -34, 2, 4, 34, -41, 4, -7, 10, 4, 15, 14, -13, -40, -2, 24, -15, 19, -1, -1, -10, 2, 22, -25, -4, -17, 10, -37, 21, -8, -23, 14, -5, -3, -20, -1, -9, -12, -17, 23, -3, 12, -10, 16, 8, 21, -10, 15, 42, -13, 10, 2, -8, -40, -33, 12, 13, -15, 21, 16, 25, -7, -36, 4, 16, 18, -22, 9, 24, -41, -7, 25, 26, -17, 12, -2, 12, -7, 12, 10, -9, -11, 12, -11, 12, 1, -5, 14, 10, 5, 26, -25, 4, -13, -6, -1, -28, 23, 5, -6, 6, -36, 26, -5, 10, -6, 23, -12, 16, -8, 11, -12, 30, -18, 4, -2, -21, -13, 15, -16, 24, -15, 28, 17, -36, -10, 30, -25, -40, -1, -15, -21, 10, 18, 8, 1, 9, 11, -38, -2, 5, -14, 14, 5, -6, 4, -6, -9, 4, 14, 1, 6, -1, -12, 11, -17, 3, -8, -16, -14, 3, 14, 7, 19, -16, 3, 28, 16, 3, 15, -14, 4, 1, -19, -17, -6, 15, 17, -1, 29, 21, -2, -7, 10, -10, -12, 6, -19, 11, 18, -8, -8, 0, 20, 26, -5, -14, -19, 10, 29, 8, 3, -13, -29, -5, -14, -10, 13, 12, -9, -20, 19, 1, -20, 5, 20, -10, -24, -18, 4, -1, -21, 14, 18, 30, 27, -11, 7, 1, -5, 10, -12, 25, 5, -8, 7, -22, 15, 11, 17, 26, 7, -8, -14, -24, -44, 15, 0, 19, -25, 15, 1, 6, -14, 42, -34, 20, -6, -24, -66, 19, -5, 0, -10, 13, -13, -5, 19, -25, -2, -13, 8, 38, 5, 19, -42, 12, -43, -15, -19, -18, -2, 3, 20, 8, -3, 11, 2, -13, 15, 0, 13, -2, 4, 5, -24, -7, 1, -16, 9, 11, 4, -22, 17, 15, 8, -23, 25, -28, -6, 10, 10, 3, 12, 3, 13, 8, -6, 14, -6, -27, 10, -26, 6, 5, -5, -2, 1, -8, -28, -13, -29, -1, 11, 31, -11, -12, -13, -23, 7, 23, -4, -33, 18, -7, 22, 29, -18, -2, 11, -16, -1, 16, 31, 22, -11, -8, -33, 22, -26, 2, 26, -18, -32, -1, -18, -14, -7, 11, -14, 7, -5, -9, -21, 8, 17, 9, -8, 7, -12, -1, 18, -11, 13, -2, 1, -14, -7, -18, 14, 13, 7, 18, 11, -8, 6, 10, -2, 24, 17, -7, 18, 33, -10, -15, -34, 15, 1, 35, 3, -24, 14, -19, 8, -18, -15, 12, 0, -14, -3, 1, -8, -9, -11, 12, 11, 30, 1, 0, -17, -32, -4, 20, 22, 21, -11, -6, 6, -9, 15, 19, -15, 7, -21, 4, -26, 30, 22, 12, -30, -31, -33, 17, -26, -36, -17, 24, 31, 9, 16, 8, -27, -2, -10, 27, 32, -8, 18, 1, -5, -21, -17, -24, 19, 4, -7, 0, -20, -19, -1, 3, -10, 2, 0, 6, 22, -9, -17, -18, 6, 13, -39, 2, 26, 9, -5, -20, 8, -44, 9, 11, -15, 2, -40, -40, -19, 4, 26, 19, -14, -11, 1, 7, -6, 0, -22, 15, 2, -26, 13, -21, 25, 23, -41, -23, 18, 10, 16, 11, 6, 6, -20, 11, -7, -5, 23, 7, 1, -13, 9, 22, 13, -12, -2, -13, 11, 3, -16, 19, -11, -26, 1, -1, 14, 0, -25, -8, -16, -4, 3, -4, 16, -3, 18, -11, 0, -2, 22, 16, 13, 15, 6, -22, 12, 1, 9, -2, 12, -4, 4, -5, -5, -21, 5, 0, 5, -18, -1, -16, -12, 17, 31, -8, 16, 0, -30, -1, -2, -8, -6, 21, 0, -35, 0, 8, -2, -9, 11, -21, 18, -21, 11, -17, -13, 18, 13, -28, 1, -17, 3, -18, 12, 2, 15, -20, -4, 14, 14, 1, -20, 4, -19, -15, -4, -7, 7, 1, -27, -10, 19, -16, 5, -21, 0, 0, -4, -7, -12, -14, -2, -14, -11, -4, -2, -37, 4, 16, 1, 13, 2, 15, 0, -21, -10, -23, -4, -1, 18, -7, 11, -10, 5, -1, -25, -3, 15, 11, 10, 15, 11, -8, 18, -3, 9, -9, 6, 1, -16, -20, -8, 6, -2, 5, -10, -5, -19, 17, 18, 27, -51, 9, -20, -4, -11, -17, -29, 4, 3, 2, 9, -21, -9, 18, 11, 20, 16, 14, 18, -15, 16, 18, 8, -22, -5, -13, 0, -1, 22, 35, 7, 11, 6, 20, -16, -29, 8, 12, -3, -13, 28, 12, 22, -4, 17, 7, -12, -10, 27, 4, -3, -22, 1, -13, 16, 13, -3, -4, 11, 10, -6, -9, 2, 14, 7, 10, 8, -23, -28, 15, -11, -17, 22, -42, -9, 7, 17, 20, -13, 37, -14, 45, -27, -5, -4, 2, -17, -21, 1, 14, 18, -8, 9, 15, -1, 23, 21, 9, -8, -11, 19, -12, -4, 12, 32, 4, -17, -8, 14, 36, 4, 24, -7, 3, -13, -11, 13, 21, 1, 20, -11, 9, 19, -1, -6, -14, -11, -11, -13, 18, 34, -12, 6, 11, 13, 23, -10, 2, 15, 7, -15, -24, 24, -15, 13, 5, 14, -27, -17, -10, -15, -17, 5, 29, 1, -29, 3, -17, 10, -12, 2, 13, 4, 20, -14, 3, -6, 19, -8, -9, 17, 9, -5, -15, 5, 11, 16, 8, 5, -12, 14, -14, -6, 21, 9, 13, -16, 19, 3, 32, -22, 8, -22, -15, -22, -13, -11, 17, 6, -4, 12, 31, -1, -2, -3, 44, 32, 2, -28, -13, -23, -10, 0, 7, 0, -16, 1, -20, -12, 9, -3, 15, 9, 11, -16, 12, 1, -19, 15, 14, -11, -17, 5, -15, -17, 8, 22, 18, -11, 19, -28, 16, 3, 5, 1, 17, 15, -8, 9, 0, 11, -4, 13, 11, 27, 11, -1, 6, 13, 12, 7, 9, -10, -3, -6, -18, -11, 22, -11, -2, -12, 22, 15, 36, 16, 7, -20, -6, -20, 22, -22, 2, -3, -6, -13, -10, -4, -12, 32, 22, -21, -17, -3, -11, -22, 23, 31, -5, -9, -4, 3, 14, 2, 35, 10, 1, -6, 19, 11, 6, 13, -1, -6, 19, 9, 1, 26, -15, 0, -27, 23, -8, -14, 30, -8, 10, 22, 23, -31, -5, -24, -2, 11, 14, 2, -28, 10, -9, 31, -1, 21, 13, 10, -4, 3, -6, 6, -13, 9, 0, -18, 8, -25, 4, 40, 13, -7, 29, 4, 9, -13, 17, -27, 15, -12, -1, -48, 2, 22, 20, 14, -20, 0, 13, -21, 13, 5, -4, 39, -6, 11, -4, 10, -22, -49, 2, 4, -19, 5, 20, -2, -2, 18, 16, -8, 11, -8, 23, -24, 16, -10, -9, 21, 5, -11, 10, 6, -6, 36, 10, 15, 34, -28, -3, -39, -8, -14, 44, 14, 17, -1, -14, -16, -13, -21, 33, -8, -18, -41, -27, -35, -7, 21, -10, 38, -8, 24, -16, -33, -17, -11, 26, 29, -3, -29, -31, 0, 0, -12, -6, 22, 13, -20, -13, -29, 3, 2, 7, -7, 14, -10, 22, 14, -19, -5, 6, 1, 6, 7, 25, 14, -4, -4, -18, 25, -2, 15, -20, -3, 19, -13, 21, -11, 9, 13, 14, 23, 23, -4, -12, 12, -2, -34, 17, -39, -8, 11, -20, 25, -21, 29, 7, -7, 28, -19, -14, 6, 16, 32, 6, -12, -24, -22, 1, 3, 20, 9, -23, -15, 6, -19, -10, 27, 23, 9, -25, 5, 8, -8, 9, 11, -15, 13, 18, 24, 13, -8, -3, -16, 11, 6, -18, 0, 3, -20, 15, 17, -1, -6, -3, 0, 4, -19, -7, 22, -7, 12, 10, 5, -9, 10, -15, 6, 5, 31, -16, 7, 0, -14, -19, 1, 12, 7, 26, -13, -18, 0, -9, -21, 12, -2, 30, 8, 16, 7, -4, -4, -6, -14, -9, -19, -2, 19, -6, 8, -33, -6, 3, -15, 13, -9, -19, -26, 8, -31, 31, -15, 7, -9, -12, -26, 34, -22, -35, 35, 14, -19, -4, 1, 2, -5, -3, -1, 18, -8, 32, -35, -11, 6, -21, 9, 2, -14, 5, 3, -11, -13, -11, -16, 0, -6, 5, 21, -30, -22, -15, -1, 13, 5, -13, -24, 27, -11, -6, -6, 1, -9, 15, 29, -27, 32, -30, -4, 22, -47, -2, 5, 15, 26, -25, -12, 13, -17, 1, 20, -19, 12, 38, -1, -3, -8, 28, -21, 32, 32, -15, -36, 6, -15, 2, 55, 13, -2, -18, 22, 25, -32, 24, 11, -23, 11, -12, 10, 3, 34, 26, 14, 12, 16, 11, 39, -3, -8, -13, -47, -20, 4, -24, -2, -16, -25, 7, -26, 5, -10, -28, -24, 7, -1, -13, 23, 13, -14, 0, -6, 0, 7, 0, -4, -16, 21, -6, -15, -3, -4, -10, -2, -14, -17, -4, 23, -28, 14, 17, 12, -14, -11, 2, -4, -1, -11, 1, -16, 20, -52, 1, -20, -6, 34, -34, 34, 8, -32, -22, -5, 4, -7, -26, 25, -9, 25, 5, -16, 1, 7, -26, -16, 20, -1, 5, -18, 14, -2, 21, 3, 9, -7, -39, -9, 9, 4, -15, 11, -14, -16, 5, 23, 8, 5, 13, -23, 2, 26, -5, 12, 21, 7, 23, -14, -29, 6, -15, -1, -23, 8, 18, -8, -2, -21, -22, -18, -29, 5, 9, 8, -15, -7, 8, -24, 20, 6, 2, 18, 11, -14, -2, 10, -14, -10, -37, -30, 8, 18, -11, 25, 29, -32, 33, 4, 0, -6, -12, -12, 14, 12, -32, 13, -19, -18, 12, -20, -4, -6, 6, -7, -13, 11, -6, -4, -23, 3, -26, 35, 2, -6, -16, -26, -2, 3, 2, -1, -3, -18, 3, 21, 31, 0, 17, -20, -3, -2, 25, 6, -19, 1, -9, 10, -8, 18, 5, 14, 6, -10, 6, -5, -3, 12, -20, -35, -18, 8, 2, 19, -19, 8, 32, -4, 24, 0, 4, -15, 3, -6, -16, 7, -15, 23, 3, -13, 23, 13, -24, 1, 8, -12, -33, -5, 23, -27, -21, 7, 2, -6, -16, 17, -1, -3, -1, 17, -18, -11, 19, -22, -4, -13, -19, -6, 6, 29, -18, 10, -25, -13, -13, -25, -36, 31, -5, -1, 15, 6, -11, -13, -10, -17, -18, -2, 25, -8, -7, 26, -16, -23, -35, 2, 6, 18, 10, -3, 14, -17, -3, 19, -13, 13, -13, -11, -13, -5, -1, 11, 23, 17, 25, 32, 9, 21, -1, -1, 8, 10, 1, 18, -30, 15, -17, 5, -9, 2, 22, -33, -6, 20, -21, 14, 9, 21, -11, -9, -20, 8, -7, 6, -3, -42, -14, 8, 15, 11, -26, 17, 13, -2, 0, 25, 3, -15, -24, 27, -3, -5, -21, -7, -10, -28, 10, 20, 22, 3, 8, -2, 6, 34, 17, 0, -22, -21, 11, 10, 4, 23, -7, 9, -19, 9, 12, 12, 24, -9, 12, -4, 23, -25, 32, -9, -8, 1, -2, -15, 9, -28, -13, 16, -15, -13, 10, 10, -3, -20, 10, 15, 13, -24, 10, 18, 9, -3, -17, -15, 0, -8, 1, 7, 16, 19, 7, 1, 1, -39, -2, 9, -11, -29, -13, -8, -22, 20, 13, 19, -3, 14, -16, -1, 22, -2, 22, -10, -8, -54, -20, -8, -17, 59, -5, -6, 11, 22, -7, -4, -8, -9, 6, -8, 25, 18, 23, 0, 15, -9, 8, -24, 5, 12, 6, 21, -6, 8, 16, 5, -12, 3, 4, -10, -30, 11, 24, 1, -5, -39, 22, 8, 5, 2, -5, 3, 3, -6, 1, -12, -2, -7, -22, 27, 6, 8, -38, -9, 12, -5, 1, 32, 8, 5, -13, 31, 4, -29, -7, -28, 2, 7, -21, 4, -8, 9, -11, 38, -20, -1, -1, -45, 0, 33, 10, 14, -1, -1, -12, -10, -2, 0, 8, -10, 16, 8, 17, 19, 10, 21, 16, 26, 16, -15, -20, 33, -5, -8, -14, -2, -16, -15, 6, -43, -8, 4, 36, 10, 33, 15, -27, -6, -7, 9, 19, -3, 35, -24, 2, -25, -10, -17, -26, 7, -34, -8, -28, -6, -18, 20, 17, 29, -9, 13, -16, -16, 13, 16, 15, 20, 2, -6, -11, -4, 20, 0, -2, 10, 9, -36, 51, -8, 22, 7, -19, 12, 23, 6, -6, 22, 2, -13, 0, -21, 24, -18, 2, 4, -6, -11, 5, -11, -2, -33, 4, -7, 1, 11, 8, 18, -23, 27, 11, -7, 7, 0, -4, -18, 14, 21, -6, -6, 6, -13, 15, 9, 15, -53, -6, -5, 20, 33, -4, -4, -6, -25, 17, -3, 23, 7, 5, 0, 2, -14, 37, 3, 16, -23, 38, 5, 30, 9, -8, -30, 18, -14, 18, 0, 10, -15, 11, 16, 51, -1, 2, 3, 8, 10, 3, -21, -6, 19, 24, 22, 30, -15, -10, -24, -13, 2, -7, -2, 22, -4, 7, -1, -12, 17, 13, -3, -7, 16, 8, 34, -9, -16, -4, -7, 17, -19, 35, -7, -7, 27, -11, -11, 10, -9, 7, -7, -7, 17, 11, 26, -9, 7, 20, -26, -15, 3, 34, 9, 18, 0, 29, -1, -27, 12, -20, 4, -2, -31, 10, -11, -17, 16, 18, 26, 32, -30, -10, -23, 15, 38, -5, 18, -2, 7, -8, 24, -14, 16, 2, 16, 4, 32, 24, 7, -2, -38, -5, -15, -10, -11, -13, 10, -6, -2, -10, 4, -5, -4, -25, 2, -32, 14, 23, 13, 32, -17, 3, -21, 0, -8, -30, 44, 1, -19, -30, 21, 3, 0, -4, -2, -26, 20, -18, -21, -29, 36, 20, -3, 1, -5, 12, 8, 0, -17, -28, -16, -13, 2, -8, 11, -39, 16, -12, 8, -39, 9, 2, -10, -23, 43, 23, -20, -4, 6, 2, -10, 15, -9, -14, -6, -23, 27, 15, 6, -4, -9, -3, -6, 5, 4, 2, 2, 21, -15, 3, 23, -3, -5, 25, -15, -3, -15, 8, 20, 32, -28, 16, 12, 28, -26, 5, -4, -25, -4, -9, -25, 12, -6, 7, -19, -4, 16, 16, -30, -41, 7, -3, -26, 12, 8, 33, 25, 1, 9, 23, -32, -17, -2, 17, -2, -14, 38, -2, -14, -30, -7, -11, -18, 4, -16, 0, -5, -8, 11, -10, 10, 13, 21, -8, -3, -8, -11, -4, 16, 23, -2, 23, -12, -18, 4, -19, 1, 20, -12, 20, -1, 24, -6, 3, -12, -31, 34, -7, 39, 21, -11, 15, -18, -9, -14, -29, -14, 2, -9, -21, 10, 3, 23, -3, -1, -30, 31, -9, -7, -4, -18, -1, 3, -2, 7, 4, 26, -24, -4, 7, 20, -8, 6, 4, 8, -36, 45, 5, 11, -12, 0, 37, 12, -27, 3, -9, 9, -16, 7, -15, -8, -5, -4, -15, -15, 36, -1, -23, -1, 20, -22, 1, 30, -7, -11, 18, -7, 3, -14, -20, -18, -21, 33, 14, -19, 17, -20, -19, 53, -18, -3, 5, 9, 5, 17, 28, -1, -5, -25, 14, 19, -19, 36, -14, -18, 13, -20, -16, -13, -27, 61, -18, 1, 20, -12, -8, 13, 15, -4, 16, 12, 7, -16, -13, 0, -51, 39, 6, 3, 6, 1, 12, 19, 15, 14, -17, -10, -17, 7, 18, -28, 14, -2, -25, 29, 5, -19, -12, -12, -16, 9, -22, 46, 2, -15, 16, -32, -8, 30, -39, 45, -21, 2, 16, -2, -4, 0, -15, -7, -3, -4, -1, 14, -12, 9, 20, -14, 4, 11, -15, 11, 8, -18, -17, -4, -6, 11, 13, 2, -13, 13, -12, -24, -5, -15, -1, -1, -49, 10, 7, 17, -13, 10, -1, -10, 7, 8, 21, 6, 1, 6, -26, -15, -20, 7, 10, 4, 2, 12, -13, 21, 5, 13, 1, -12, 12, 41, -26, -11, 31, -38, -1, 29, -33, 16, 7, -24, 14, -23, 18, 15, -18, -6, 50, -5, -8, 4, -15, -1, -15, -32, -1, 29, -7, 49, 4, -12, -17, 12, -7, -6, -27, 9, 22, 10, -7, -13, 73, -44, 15, 16, 7, 9, -5, 2, -25, 2, -4, 9, 21, 8, -10, 5, -18, -30, -2, -20, -17, 20, 15, -31, 17, -2, -17, 32, -29, 16, 9, -46, 19, 0, 1, 7, -14, -25, 14, 3, -1, 21, -7, 23, -12, 2, -37, 0, 8, 25, 14, 19, 21, -12, -19, 22, 6, 0, 15, -6, 4, -9, -6, -6, 22, -23, 14, -2, -1, -7, -30, -11, -29, -40, -3, -1, 12, 55, -27, 5, -28, 24, -22, -27, -6, -3, 21, 7, 7, 4, -13, -12, -3, 6, -25, -23, 12, -19, 1, 5, -12, 6, -18, 2, 1, -12, -24, -31, 8, 8, -10, -29, 16, 26, -11, 43, 16, -9, -16, 12, -26, 12, 22, -42, -1, 5, -6, 18, -4, -1, 25, -22, -27, 1, 3, -16, -10, 8, -22, 25, -17, -16, 5, -7, 18, -1, 22, -11, -5, 0, 8, -15, -25, 9, -2, 39, -12, 25, -33, 29, 17, -3, 5, 31, -2, 13, 0, 6, 9, -49, -18, 2, 7, 45, -11, -18, -8, 3, 14, 6, -11, 5, -4, 30, -1, -17, -6, -2, -11, 31, 8, 8, 32, 4, -21, 19, -7, 34, -10, 4, -13, 1, -8, 22, -8, -8, 22, 26, -21, 11, -11, -10, -6, -5, 31, -19, 8, 10, -2, 28, 14, 8, 25, -20, 11, -4, -17, -26, -8, 12, 0, -16, 22, -5, 23, 2, 9, 5, -20, 13, 10, -2, -8, -9, -14, 18, -13, 20, -16, -18, -14, -4, 4, 15, -25, 6, 22, -10, -18, 7, -18, -6, 4, -24, 9, 11, -5, 4, -19, 1, -21, 4, -9, 29, -22, 5, -20, -27, 21, -9, 12, -25, -12, -10, 0, 25, -20, 1, 6, 15, 8, -9, -6, 0, -18, -15, -14, -12, -18, 3, 7, -21, -4, 7, 6, 25, 12, 34, -6, -6, 18, -6, 1, 31, -5, 4, 9, 5, -1, -13, -12, 18, -21, 8, 9, -5, 13, -4, -14, 26, -25, 5, 15, 4, -5, -12, 5, 1, 18, 8, -21, -3, -3, -9, 12, 20, 11, -25, -16, 15, 6, -1, 7, 5, 11, -11, 19, -19, 28, -2, -6, 9, -10, 4, 8, -5, -26, -26, 1, 13, 5, -29, 17, -4, 36, -9, -12, -7, -7, -20, -6, -17, -4, -4, 28, -24, -11, 2, -16, 0, 32, 12, 24, 13, 14, 0, 12, 10, 2, 10, 8, -21, -10, -14, -15, 5, 2, 4, 6, -4, 8, -30, 0, 11, 16, -3, 28, -16, -8, 10, 14, -18, 33, -11, -8, -3, 18, -31, 9, -25, 20, -12, -21, 24, 12, -15, -8, -5, 3, -21, 25, -15, 9, -10, 4, 10, 11, 12, 6, 23, -8, 8, -1, -8, -9, 26, -9, 23, 20, -16, 17, 4, 28, -7, 29, 24, -6, 12, -2, -23, 2, 14, -7, 4, 3, -21, -17, 0, 13, -4, -17, 16, -5, 10, -9, 1, 31, -9, 16, -8, 8, 6, -4, 10, 13, 19, -5, 7, -21, 25, 19, -18, 2, 0, 18, 18, 13, -8, -22, 1, 19, -1, -15, -10, -1, 25, -11, -21, 9, 11, 15, -5, -7, -21, 14, -13, -14, 17, -8, 19, -9, -26, -13, 4, 12, 21, -14, -13, -1, -4, -16, 6, 7, 11, 13, 16, 7, 14, -14, -15, -15, 15, 15, -10, 19, -19, -8, 22, -34, -10, -22, -11, -15, 15, -18, 12, -4, 35, -26, -35, -13, 1, 17, -31, -42, 23, 12, 17, 0, -5, -3, 20, 3, -6, 16, 26, 10, 10, 19, -1, -21, 15, -6, -13, -4, -2, 14, 14, 8, -6, -16, -7, 15, -7, -17, -24, 17, 29, -13, 7, -12, -2, 9, 14, 5, -22, -23, -7, -4, 4, -6, -6, 22, -8, -5, -26, -9, 9, -2, -4, 0, 1, -21, 24, 13, 10, -11, 4, -2, 7, 1, 5, -8, -1, 15, 0, -6, 6, -17, 8, 14, 17, 9, 1, -10, -14, -20, 0, 18, 13, -4, -28, -4, 22, 1, -2, -9, 8, -3, -8, -1, 18, -10, -7, -3, -25, 15, -14, 12, -11, 4, 18, 10, -11, -13, -12, 1, -2, -2, 14, 18, 13, 13, -15, 26, -1, -20, -10, -8, -12, 21, 15, -51, -7, 19, 1, -4, 49, -13, -17, 5, 2, -20, 10, 10, -12, -11, -11, 30, 29, 8, 1, 12, -24, -6, 10, 19, 4, 7, -26, 3, 14, -3, -18, 10, -15, 5, -11, 19, -1, -9, -15, 19, -5, -1, 6, 1, 18, -9, -2, -17, -10, -24, -8, -11, 13, 14, -20, -20, -25, -27, -17, 6, -6, -11, 4, 5, -10, 1, 6, 9, 14, 12, 24, 3, -9, -17, 14, -10, 14, -21, -12, 8, -23, 17, 22, -21, 15, 15, 14, 10, 28, 27, 10, -23, -10, -6, -9, 24, 12, -3, 12, -10, 0, -7, -7, -32, -2, -16, -7, 6, -7, -23, -10, -12, -11, -6, -9, 13, 10, -7, 10, -24, 15, 1, 14, -12, 17, -2, 19, 6, -6, 2, 5, 7, -24, -21, 2, -24, -17, -19, 6, -18, 6, -21, -20, -4, 20, 29, 6, 18, 13, -10, -17, -21, 17, -40, 0, 18, -7, -14, 8, 15, 9, 20, 0, -13, 0, 19, -23, 5, -6, -10, 4, 13, 18, -21, -30, 40, -5, 4, 15, -16, -10, -10, -18, -11, 25, -13, 19, 18, 20, 20, 0, 26, -28, 15, -10, 9, -22, 13, 16, 29, -8, -18, -6, 12, 18, 14, -12, 22, -16, -37, 15, -9, 3, 6, 2, 4, -9, 6, 35, -12, 5, -21, -46, -4, 14, -3, -11, -6, -10, 18, -3, 20, 12, 2, 16, -2, 9, -19, 27, -32, 11, 27, 23, -21, 5, 22, -22, 26, 22, 6, 13, 18, 4, 18, -23, -13, -26, 24, -26, -7, -34, 8, -11, -6, -13, -8, -8, 10, 2, -18, 7, -2, 1, 2, -21, 10, -26, 2, 22, 17, 9, 6, -22, -9, -15, -8, 1, 18, -22, 1, 3, -3, 5, 16, 10, 27, 16, -9, -6, -3, -7, 13, -23, 16, 15, 3, -10, 4, -5, 12, -4, 14, 17, 14, 2, -18, 5, -16, -18, -1, -1, 17, -12, -5, 19, 7, -22, 15, 13, 27, 7, 4, 2, 3, -11, -11, -15, 33, -4, -11, -2, 19, -31, 4, -4, -30, -48, 8, 1, -4, 37, 5, -20, 4, -13, 1, -5, -3, -16, 9, 15, 48, 12, -4, 5, 13, -25, 21, -9, 20, 0, -15, 3, -5, 2, -13, -23, 20, 31, 12, -16, -18, -34, 2, -12, 13, 14, 5, 8, -10, -4, -2, 7, 20, -13, 12, 8, 16, -18, 18, 22, -42, 26, -2, -24, 15, 3, 0, 1, 6, -4, 18, 16, 10, -21, -3, 16, -15, 42, -22, -4, -14, 32, -6, 2, 12, -4, -5, 6, 6, -24, 19, -9, -9, 7, 10, -8, 6, 24, -36, 54, 17, -19, 2, -26, -7, -10, 16, -3, -27, 28, -10, -6, 13, -27, 2, -11, -6, 13, 13, 11, -9, 14, 9, -10, 12, -15, 17, -11, -18, -4, 13, 8, -28, 18, 11, 25, 12, 13, -8, -3, -5, -11, -20, -12, -22, 24, 3, 7, 10, -22, -10, 13, -18, -19, 0, 34, 30, -2, -3, -14, -19, -18, -5, -14, -3, -31, 11, -8, -4, 6, 18, -21, -10, -16, -22, -24, -6, 16, -19, 18, -8, 16, 6, 23, -17, -26, -9, -8, 12, -5, -19, -7, -6, 19, 38, -32, 4, 16, -13, -3, -15, -22, -1, -10, 12, -22, 1, -15, 19, 2, 36, 32, -21, -25, -3, -24, -6, 21, -7, -7, 8, -10, 1, -26, 5, 17, -13, 18, 14, -11, 11, -11, 12, -8, -14, 14, 5, -16, -9, 25, 7, -32, 34, 3, -8, -3, -12, -16, -21, -4, -2, -6, 4, 12, -2, -17, -13, 26, 32, -16, 7, -19, 1, -21, -22, 0, -26, 15, 21, 20, 7, -17, -10, -16, -13, -4, 3, 16, 3, -6, -5, 2, 12, -16, 24, 3, 20, 25, 14, 8, -6, -12, -6, -31, -15, 32, -23, -11, -16, 22, -8, 22, 6, -6, 18, -7, -6, 16, -11, -22, 11, -3, 12, 6, -15, 10, 17, 4, 13, 1, 1, -18, -19, 13, -4, 7, -15, 3, -8, 3, 19, -5, -2, 11, -11, -22, 8, -5, 4, 25, 8, -5, -1, -4, -17, 12, 20, -10, -20, -15, -19, -28, 12, 14, 12, 17, 0, -15, -19, -7, 14, 3, 14, -38, -8, -29, -1, -5, 17, 5, 22, -11, 23, 0, 11, 12, -4, -19, -33, 45, 7, -6, 1, 20, 1, 10, 11, -3, 15, 24, -21, 19, -10, 15, 35, -8, -26, -1, -20, 8, -9, 21, 34, -16, -4, 17, -9, 5, -22, -25, -5, 17, 2, -19, 11, -13, 7, 25, 44, 1, 2, 12, 1, -24, 4, -27, -14, 47, -4, -14, -21, 11, 12, 15, 11, -33, 27, 6, -19, 9, -15, 9, 9, 18, 16, 13, -18, -10, -3, -4, 10, 23, 3, -2, -21, -30, -11, 27, 17, -19, -13, 17, 20, 18, 4, -21, -20, 14, -6, 5, -9, 0, 8, 32, -3, -9, -10, 24, 4, -11, 11, 26, -27, 2, 18, -4, -4, -27, 20, 7, 11, -2, -5, 22, -9, -5, 6, -38, 1, 33, -13, -19, -3, -17, -1, 32, -4, -5, -19, 10, -1, 6, 1, 3, -3, 7, -33, 2, 17, 30, 12, 40, 17, 18, 21, 26, 1, -20, -2, 17, -3, -4, -18, 11, -17, 22, -1, -12, -2, 7, 11, -3, -12, -1, 9, 15, 12, 13, -4, -5, -2, -7, -19, 11, -13, 28, -3, 13, -21, 0, 11, -13, 10, -4, -2, 12, -22, 4, -5, 6, 18, 24, 1, -4, -4, 27, -20, 4, 7, -1, 6, 17, 3, -9, 10, 1, -19, 13, 17, 21, 3, 8, -21, 11, 1, 11, -7, -1, -21, 5, -19, -2, 0, 33, 4, -12, 19, -7, 15, 2, -11, -2, -3, 21, 11, -14, 18, -7, -5, -4, -8, 17, -22, 14, -12, 13, -5, -18, 21, -2, -20, 4, 14, 8, 4, -13, 22, 8, -18, -13, -9, 11, 3, 15, 11, 30, -18, 19, -8, -5, -13, -18, -2, -11, -20, 18, 19, 10, -12, -12, 21, -18, 0, -9, -16, 3, 20, 5, 41, 16, 11, -31, 7, -2, -16, 8, -19, -12, 0, -19, -4, 26, 0, -20, -4, 4, -10, 12, 21, 3, 35, 3, -4, 19, 19, -16, 14, -12, 10, 15, -19, -6, 13, 5, 3, -15, -13, 21, -7, 14, -8, 2, -15, -15, -15, -2, 30, 16, -7, -26, 13, -31, 22, -7, -12, -8, -20, -23, -1, -4, -11, -1, -4, -1, -18, 0, 2, -33, 15, -19, 19, 26, 2, 15, -20, 9, 18, -6, -7, 29, -20, -23, 5, -3, 15, 12, 9, -3, 14, -6, -21, 11, 28, 26, 5, 22, 19, -18, -3, 10, -3, 15, 5, -7, 15, 6, -15, 9, -25, -5, 4, 27, -12, 14, 12, -3, -34, -3, -24, -4, -15, -6, -4, -11, 1, 12, 6, 11, 9, -22, 10, 21, 15, -14, 4, 20, 6, -32, 13, 7, 5, -3, 11, 38, -21, 31, 1, -48, -22, 10, 21, -1, 13, -46, -3, -1, -15, -8, 26, 10, -16, 4, 4, -31, -9, 37, 5, 7, -5, -25, -8, -8, -18, -14, 24, 20, 10, -15, 11, -5, 12, -20, 43, -9, -3, -1, -6, 3, -21, 15, -12, 3, 5, -10, -20, -2, -17, -23, -18, -8, 12, -5, -16, -2, -13, 30, -6, 12, -11, -17, -14, -32, 18, 13, 11, 7, 0, 6, 16, -28, -25, -6, -31, 25, -2, 19, 11, -9, 4, 17, 22, -9, -8, 6, -14, -3, -12, 5, -2, -20, 4, 26, 19, -2, 13, 11, -24, -9, -9, 26, -22, 28, -6, 16, -25, -20, -21, -8, -21, 9, -6, -12, -31, -5, 18, 6, -19, 23, -11, 22, -21, -6, 18, 5, -19, -19, -26, -22, 17, -24, -17, 18, 9, -24, -14, -9, -19, 15, -9, 20, 12, 25, 6, -17, 33, -12, -21, 5, -8, -20, -33, -6, 17, 14, 14, -2, -12, -29, -6, 0, 5, -39, -10, -39, 15, -11, 18, -7, 14, -6, -7, -30, 6, 3, -16, 8, -32, 16, -14, -7, 9, 24, 0, 7, 2, -9, -3, -11, -3, 2, -23, 16, 7, -20, 3, -1, -7, 23, -24, -17, -8, 4, -17, -19, 4, 16, 3, 5, -27, -24, -17, -13, -7, 16, -15, -16, -12, 31, 4, 7, 9, 20, -1, -16, -3, -17, -17, 13, 15, -38, -11, 28, -8, 13, -18, 2, 13, -28, 7, 4, 8, -4, 18, -20, -10, -2, 19, -8, 15, -22, -19, -15, 5, 12, 16, -2, -15, -18, 1, -29, -5, 27, -8, -11, 13, 9, -12, -3, -12, -4, -12, 0, 46, -8, -5, -8, -22, -36, -36, -2, 14, -20, -12, 26, 0, 1, -10, -11, 15, -32, 4, -16, -23, -2, -14, 9, 2, 5, 16, 12, 11, 6, -12, -4, -8, -2, -16, 8, 4, -19, -14, -5, 14, 8, 16, -10, 16, 33, 10, -16, 10, -25, -1, 17, -17, -5, -11, 22, -19, 1, -19, -4, -15, 12, -4, 20, 9, -15, -15, 5, 11, -40, -29, 2, 26, 10, -17, 3, 17, -11, -28, -6, -12, -26, -10, -25, 2, 14, -6, -27, 27, -14, 12, 10, -16, 0, -10, -2, -4, -5, 0, 33, 13, -14, 9, 7, -3, -1, 19, -10, 20, -7, -23, -5, 21, -10, 9, -22, -6, -1, -8, 3, -11, 2, -11, 15, 4, 16, -34, 12, -9, 4, -19, 19, 6, 12, -26, -15, 19, 14, -15, -2, -1, -19, -14, 22, -16, 16, -11, 8, -2, 23, -2, -10, 9, -4, 11, -19, 5, -6, 30, -1, -6, 21, -15, -13, -8, -16, 1, 8, -5, -8, -12, 3, -7, 33, -2, -3, -19, 14, -23, 13, -21, 15, -18, -28, 4, -3, -1, 8, -1, -11, -7, -36, 18, 23, 8, 36, -7, -22, -25, 6, -21, -5, 9, 24, -12, 2, 17, 2, 9, -19, -3, -22, -20, -10, -18, 4, -3, 7, -19, -4, 1, -4, -15, -11, -14, 20, -11, 14, -19, -22, 9, -10, 18, -18, -16, -5, 7, -26, 37, 10, -32, 9, 19, -19, 14, 24, 18, -19, 22, 12, -17, -16, -14, 2, -1, 16, 2, -5, -21, -7, -6, -12, 9, -9, -16, -6, -2, -32, -9, -25, -31, 11, 11, -11, -9, -23, 14, -24, -35, -29, -19, 10, -21, 35, -2, -5, -10, 26, 27, -15, 12, 16, -23, -7, -26, 10, -7, 2, -16, 12, -6, -20, -37, 8, -3, 14, 19, 5, -8, -12, -17, -7, -22, 8, -17, 16, -6, -3, -3, 17, -32, 0, -20, -12, -16, -24, -9, -26, 5, 4, -7, -12, 2, -4, 13, 20, 1, -16, 8, 18, -5, -28, 5, -1, -24, -16, 19, -32, 5, 25, -8, -4, 31, -15, -7, 28, -18, -30, -16, -14, 28, 14, 9, -11, 0, 8, 18, 18, 10, -9, 4, 1, 15, 6, 10, -5, -22, 9, -7, -9, 0, 22, 19, 17, -29, 33, -16, 17, -18, 15, 15, -11, 12, 15, -19, 31, 18, 19, -13, 15, -28, -5, 15, 9, -15, -3, 3, -14, 30, -9, 15, 16, -13, -17, -12, -16, 20, 0, -6, 9, -20, -16, -2, -17, -1, 1, -13, -7, -15, 4, 41, 1, 3, -1, 3, -19, -16, 2, -6, -15, -24, 11, 16, 23, -14, -7, 6, -6, 5, 19, -8, 10, 5, 3, 31, -22, -7, -4, -7, 8, -7, 9, 17, 11, 12, -27, -6, -2, 17, -18, -20, 24, -10, 8, -5, -14, 12, 16, 12, 12, -3, 13, -14, 23, 18, -12, 1, 2, -10, 27, -13, 30, 21, 14, 15, 11, -23, -11, 2, 19, -7, 3, -11, -2, -21, 25, 19, 12, -9, -8, -7, -6, 16, 7, 5, 5, 18, -10, -2, 7, 21, -36, -16, 10, -12, -29, -14, 1, -10, 22, -17, -4, -5, 9, 21, 1, -5, 20, -13, -18, 16, -1, -72, 18, 21, -28, -1, 18, -2, 17, 15, -16, -24, -8, -9, -16, 6, -11, 34, 21, -27, 18, 5, -14, 7, 0, -1, -10, -13, 15, 14, 8, -8, 2, 1, -19, -28, -5, -7, -1, 1, -6, -20, -12, -9, -12, 4, 37, -4, -6, -10, -10, 0, -7, 18, 0, 15, 0, -27, 12, -8, 1, 15, 16, 8, -10, -3, -18, -13, -7, -11, -14, -3, 3, 2, 13, -23, -11, 12, 4, 19, 10, 14, -23, 0, 6, 18, 8, 12, 14, 20, 22, 5, 8, -9, 11, -7, -9, 5, 12, 5, -2, 0, 4, -10, -1, 19, -27, -18, -1, 14, 17, 7, 28, -13, 19, 0, -14, -5, 14, -4, 8, 16, 7, 11, 13, 16, 16, 16, 17, 11, 9, -13, 17, -17, -15, 21, -34, -23, -17, 43, -24, 20, 9, 6, -3, 39, -15, 15, 16, -12, -27, 13, -5, -7, -14, 22, -11, -23, 9, -11, 12, -25, 11, 35, -19, -7, -18, -6, -7, 53, -30, -17, 2, -21, -13, 6, 11, 39, -27, -2, -41, -22, -33, -20, 5, 6, 8, 14, -26, 14, -14, -5, 6, -18, -5, 37, 16, 4, 29, -5, -34, -10, -14, -26, -24, -13, -6, 7, -15, 8, 3, 55, -10, 9, 6, 5, -18, 8, 8, -9, 9, -2, -28, -4, 23, 3, -11, -18, 14, 5, -48, -3, -8, 35, -14, 22, 4, -13, -2, 7, 0, -14, -12, 1, 9, 17, 5, 4, 4, 59, -6, 1, 12, 21, -21, -15, -30, 1, 15, 20, 7, 15, 21, 19, -3, 21, 4, 32, 1, 2, 16, -1, -43, 18, -28, 20, -13, -3, -23, 18, -29, -2, 17, 46, -30, -3, 16, -14, -46, 20, -14, -22, 5, 11, 16, 3, 10, 29, 10, 30, -6, -22, 4, -21, 1, -17, 17, -3, 9, -15, 21, 7, -2, 12, -9, -2, 19, 13, -42, 16, -12, 11, -8, -18, 2, 8, 10, -15, 8, -1, 3, 38, 2, -1, 4, -17, -34, -2, -6, 21, 18, -19, -50, -3, -16, 4, -1, 12, 18, -21, 16, -3, 17, -31, 16, 37, -1, -21, 20, -20, -8, 18, 12, 21, 9, -17, 17, 14, 26, 19, 26, -38, -37, -10, -51, -21, 2, 31, 11, 17, -7, -3, -24, 14, 15, 18, -18, -4, -10, -5, 1, 16, 0, -9, 6, -28, -15, 16, -5, 3, 12, -11, 11, 2, 3, 13, 18, -15, -36, 13, 20, 27, 6, -16, -13, 1, -42, -1, -12, -10, 5, -11, 24, 4, -8, 34, 3, -29, -6, 5, 8, -20, -8, -12, -10, -9, -20, -14, 21, 8, 12, 11, 23, 3, 6, 9, -26, 3, -5, -7, 2, -6, -16, 12, 9, 14, 19, 29, -6, -43, 21, -8, 9, 6, 16, 2, -3, 20, 11, -10, -30, -17, -36, 11, -9, 39, -1, -6, -17, 7, -16, -3, 3, -19, -17, -16, -12, -23, -16, 39, 5, -4, 20, -11, -26, 7, 22, -7, -15, 13, 4, 16, -26, -16, -32, 45, 10, 9, 10, 17, -28, -1, -30, -12, 37, 6, -8, 20, -24, -11, 12, 8, 29, 33, -2, -2, -11, 19, -10, -3, -34, -5, -17, -20, 10, 15, -19, 11, 9, -5, 8, -15, 5, -4, 14, 11, -28, 15, 6, -9, 21, -14, -10, 51, -12, -30, 6, 14, -27, -12, -6, -3, -10, 34, 17, 12, 11, -5, 8, 13, -14, 16, 10, -1, -17, 18, 16, -6, -27, 29, 0, 14, -12, 12, -14, -14, 19, -17, -7, -10, -9, 19, 19, 2, 15, 56, -1, 11, 6, 15, -16, -7, 7, 22, 17, -12, -29, 12, 18, -31, -2, 27, -8, -6, 20, -13, 3, -20, -23, 6, -11, -7, 4, 1, 6, -29, -14, 15, 3, -5, -6, 11, 8, 34, -15, -24, 26, -9, 4, 17, -31, 21, -4, 27, -11, 7, 4, -7, -16, 27, -18, -43, 5, 1, -9, 1, 9, -8, 24, 5, -2, -4, -7, 4, -9, -14, 1, -3, 14, 12, -27, 6, -49, -7, 28, 12, 3, -13, 15, -4, 17, 18, -12, 39, 5, -17, 0, -3, 24, 31, 21, 14, -10, 11, 2, -1, -21, 7, -19, -2, 17, 0, -22, -4, -2, -12, 10, -14, -6, -5, -2, 21, -24, -8, -7, -27, 1, -19, 5, -14, -21, 2, -19, 23, 8, 14, -2, 1, -14, 28, -24, -9, -22, 2, 41, -9, -10, -21, -15, -10, -5, 2, -18, -21, -2, 1, -23, 12, -4, -2, 1, -8, 42, -26, 8, -18, 4, -19, -3, -18, 21, -32, -2, -2, 7, 14, -9, 2, 11, -5, 22, 2, 16, -13, -54, -12, -10, -16, -2, -9, 10, -7, -1, 5, -8, 7, 4, -19, 2, -22, -12, -6, 11, 4, -18, -22, -4, 17, -15, 1, -21, 6, 13, 19, 1, -13, -1, -6, 4, -11, 9, -11, -10, -6, -10, -5, -8, -19, -24, 7, -3, -27, -16, -25, 10, 3, -21, -18, 16, 20, 11, 0, -11, -25, -17, -20, 13, -4, -11, -2, -28, 24, 2, -17, -8, -20, -6, -3, -49, -12, -17, -9, 8, -24, -10, -5, -10, -23, -7, -10, 0, -12, 11, -21, 7, -12, 11, 5, -1, -3, -23, -18, 6, 16, 7, 21, -24, -17, 1, -9, 47, 25, -1, -18, -3, -4, 28, 12, -22, -9, 14, -18, 16, 10, -4, 9, -2, 8, 17, -28, -18, 17, 8, -26, -16, 20, -4, 1, -16, 1, 25, -27, -5, -32, 5, -22, -23, 16, -21, -1, -32, -6, -4, -3, -11, -10, -6, -2, 4, -12, 9, 5, 8, 8, 2, 4, -30, -6, 13, 4, -15, 1, 31, 7, 20, -8, -22, -15, 9, 9, -7, -16, -11, -2, -15, 5, -3, 2, -27, 28, -12, 1, -10, -20, -2, -5, 10, 22, -21, 16, 16, 3, 9, 13, 36, -11, 17, -1, 9, -33, 12, -13, 3, 20, -26, -14, -2, -7, 16, 13, -1, -10, -4, -6, -12, -6, -9, 10, -14, -1, -15, 28, -13, -12, 1, -12, -5, 7, 7, 6, 14, -10, -20, 11, -24, 3, 2, 24, 14, -21, 15, -3, 25, -6, -6, 17, -19, 16, 15, -1, 26, 3, -14, -7, 12, -1, -22, 12, 7, 14, -5, -20, -19, 20, -3, -6, -17, -28, -8, -7, 5, -17, 6, -6, -39, -21, -2, 14, -11, 3, 10, -16, 3, -23, -8, -22, 8, -24, 6, -13, 16, -9, 4, -12, -19, -20, -18, -5, -16, 26, -8, 28, -22, -31, 12, -14, 18, 15, -29, -13, 17, -12, 17, -26, 7, 17, 4, 57, 14, -10, 2, 13, -49, 1, 8, 7, -21, 18, 10, 23, -14, 11, 32, -44, 10, 2, -1, -15, -29, -16, -28, 19, -14, -14, 17, -9, 12, -4, -14, 25, 4, -4, -6, -15, 17, 22, -8, -7, -5, -12, -23, -11, -9, -6, -5, 10, 14, -8, -19, 4, 45, 9, -19, 2, 17, 24, -14, -16, 44, 7, -3, 9, 13, 32, -21, 10, 27, 9, -4, -7, 1, 0, 17, 1, 23, 4, -15, -25, 14, 8, -7, -17, 2, -8, 26, -30, 19, -7, -20, -15, 4, 2, 7, -11, 13, -34, 0, -24, 14, 9, -28, 2, 19, -17, -11, 32, -32, 23, 3, 9, -21, 5, -1, -9, 3, 9, -13, 11, -11, -11, 9, 12, 19, -5, 9, -2, -11, -13, -8, 5, 7, -5, -16, -5, -11, -15, 0, 23, -1, 1, -11, -32, 17, -5, 6, 12, -51, -15, 16, 9, -21, 3, 9, 16, 14, 16, 14, 7, -1, 1, -12, -18, -9, 1, -16, -8, -23, -33, -12, 17, -19, 9, -33, 2, -18, 7, 18, 2, -7, 13, -11, 10, 14, -28, -18, -22, -13, 0, -24, -16, -18, -29, -11, -36, -28, -20, -30, -7, -24, -7, 17, 3, 12, 1, 28, -25, 11, -37, 14, 5, -25, -37, -3, -5, 3, 5, 9, -2, -5, -27, -31, -26, 18, 12, -4, 0, 4, -20, 13, -19, -19, -13, -22, -27, 2, 5, 35, -23, 5, -23, 4, 6, -9, -31, -11, 6, 4, -25, 17, 8, -2, 7, -12, -39, -8, 5, 1, -12, -20, 5, -7, -33, -1, -22, -15, -6, -36, 14, 16, -30, -1, 0, -10, -24, -50, 2, -27, -14, 19, -7, -10, -1, -35, -8, -16, -8, -3, -31, -20, -20, -18, -45, -3, -22, -8, 19, -2, 27, -7, -5, -20, 11, 15, -33, -11, 0, -6, -12, 7, -19, -9, -23, -19, -34, -9, -3, -24, -10, -14, -10, -6, -3, -37, -24, 5, -25, 9, 14, -26, 13, -2, 7, -15, -12, -13, -15, -23, -43, -35, -6, -37, -2, -14, 28, 1, 15, -27, -11, 12, 10, -1, -35, -19, -20, -26, 11, -9, -15, -12, -4, -1, -1, -18, -16, 31, -16, -10, 5, -7, 11, -5, 4, -15, -20, 13, -4, -23, -6, -8, 2, -38, -20, -16, 2, 14, 5, -35, 5, 14, 9, -12, 4, 16, 7, -10, -25, -21, 4, 3, -8, 9, 20, 12, 24, 20, 2, -2, -4, -24, 3, -16, -14, -26, -2, 0, 10, -1, -6, -7, 21, 15, 14, -21, -20, 12, -3, -7, -31, -25, 3, 10, -19, 3, -3, 2, 15, 4, -8, 17, 40, -2, -33, -7, -35, -23, -16, 6, -17, 4, -4, -2, 16, -5, 21, -15, 17, 2, 3, 7, 21, 0, -12, -1, -1, -6, -5, -15, 10, 1, -16, -18, -42, 7, -22, -10, 2, -21, 13, -26, 6, 8, -5, 10, 2, 9, -20, -1, 9, 5, 8, 6, 3, -28, 23, 15, 21, 14, -18, 7, -7, -3, 21, 9, -15, 8, -7, -15, 21, -25, 2, -14, 23, 15, 31, 30, 8, 9, -16, -4, 2, -6, -8, -30, 19, -1, 19, 8, -6, -9, 11, -15, -15, -23, -6, 4, 17, 15, 1, -4, -12, 16, 27, -13, 1, -20, -2, -9, 24, -37, -34, -10, -7, 2, 12, 33, -15, -21, -21, -18, 1, 11, 0, 4, -4, -7, 5, -20, 11, 10, 4, -6, 9, 6, 0, -20, -17, -13, 10, -20, -15, -40, -8, -22, -23, -12, -18, 9, -28, -23, 6, 12, -18, -24, -11, 24, -3, -23, -2, 3, -20, 1, 18, 27, 21, -4, -24, 5, 25, -23, 11, -15, 21, -11, -1, -23, -18, -14, 12, -8, 22, 1, -14, -8, -16, -21, 14, -4, 0, -31, -3, 13, 8, -6, 5, -24, -7, 8, 20, 16, -25, -14, 1, 8, -5, 8, -9, 12, -9, 4, -16, 14, 1, -6, 18, -20, -7, 7, -9, 28, -3, 19, -17, 14, 2, -20, 21, -32, 16, -22, -26, -2, 12, 3, -13, 1, 1, 11, 0, 14, 1, -21, -8, 17, 1, -17, -8, -22, -9, 9, -15, 9, -3, 4, 17, -4, -6, -8, -9, -22, -5, 34, -7, 10, 5, -20, 27, -17, -11, -8, 6, 17, -29, -5, 1, -20, -10, -3, -3, 5, -25, -20, 12, -46, 0, -27, -4, -7, -9, -16, 4, -11, 4, -2, -9, -1, 13, -4, -1, -18, -4, 6, -30, -14, 10, -12, -19, -19, -6, -23, -16, 4, 7, -17, -4, 3, 20, 6, 27, -6, -11, -1, 17, 21, -23, -21, -48, 9, 1, -14, 16, -46, 24, -28, -5, -8, -17, 9, -5, -28, 8, -19, 26, -3, -4, -12, -33, -10, -21, 11, 7, -23, 12, -2, -7, -17, 11, 3, 22, 6, 0, 10, -8, 0, 4, 14, 3, 3, -33, -9, 4, 16, 8, -17, 19, -20, 11, -18, 2, 8, 18, 7, 8, 5, 32, -24, -9, -52, 0, 7, -12, -19, -11, 20, -4, -13, -18, 3, -10, -22, 12, 8, -9, -9, 42, -24, 16, 9, -30, 2, 31, 14, 3, -10, -20, -2, 7, -15, 26, -25, 29, -27, -16, 14, -9, -4, 12, 3, -17, -23, -6, 7, 17, -7, 28, -3, 21, -8, -6, -2, 2, -11, -13, 8, -4, -31, -15, -7, 22, 16, -14, -14, -4, -16, -3, -25, 10, -13, -12, -7, 9, 2, -9, 2, -48, -17, 2, 17, 26, 7, -18, 15, 26, -13, -23, -18, 4, 0, 5, 6, -5, -2, -2, -4, -5, -20, -15, 15, 5, 7, 20, 10, 0, 29, 31, 6, -15, 18, 6, -4, 21, 10, -17, -2, 25, -1, -30, -2, -6, -7, -11, -21, -9, -8, -23, 29, 12, -26, 22, -21, -33, 17, -3, 32, 47, -29, -13, 0, -5, -16, 10, 11, -12, -10, -38, 5, 1, 15, -3, 0, -21, -27, -8, 14, -11, -11, -14, -15, -41, 6, -14, 1, 5, -24, 10, -16, 12, -4, -19, 14, -5, 5, -19, 1, -22, -14, -22, -10, -25, -21, -21, -21, 15, 11, 12, 2, 1, -7, 23, 24, -19, -13, -6, -2, 8, 19, -18, 0, 12, 3, -33, 13, 7, 13, -7, -17, 5, 5, -5, -9, 19, -9, -2, -10, 8, 0, -13, -16, -28, -8, 20, -61, -1, -16, 15, -7, -18, -6, 6, -7, -28, 13, -31, -18, -10, -1, -3, -35, 6, 4, 3, -23, -17, -3, -11, 17, -31, -6, -18, 14, 0, 10, -10, -2, -4, -15, -9, 11, -14, 13, -5, -21, -27, -29, -7, 16, -23, -1, -16, 6, 12, -24, -28, 9, 8, 15, -16, -13, -10, 34, -11, -2, -2, 19, -26, -28, 5, -30, 8, 7, -37, -12, 20, -16, 5, 6, -12, 14, -2, -9, 2, 2, 15, 21, -15, -22, -4, -25, -5, 7, -1, 3, -18, 4, 0, 8, 5, 0, -4, 28, -10, 10, -6, 16, 5, -5, -38, -8, -3, -20, -9, 8, -24, -18, -4, -3, -3, 15, -15, 11, 13, 10, 27, 18, 1, 7, 0, -2, 6, 11, -13, 7, 2, -19, -16, 18, -10, 1, 22, -33, 11, 17, 6, -18, 5, 5, -14, 3, 3, 11, -16, 10, -18, 13, -2, -3, -7, 7, 15, 7, 2, -37, 3, -12, -16, -15, 11, -1, 16, 12, -1, -19, -13, 1, -10, -7, 23, 13, -2, 21, 2, 15, -19, 6, 13, 13, -3, 15, 13, 0, -12, -20, 3, -9, -4, -17, 24, 5, -27, 2, -10, -3, -2, 4, -3, 12, 1, -2, -11, 2, 17, -8, 28, -10, 15, 5, -23, 11, -6, -5, -16, 5, 19, 19, 7, -1, 11, -12, 5, -18, 11, 3, -22, 3, -11, -15, -7, 5, -1, -11, 3, 12, -12, -21, -7, 0, -4, 6, 5, -9, 0, 26, 8, -19, -7, 2, -10, 28, 2, 1, 25, -22, 23, -10, 26, 18, 2, -30, 26, 5, 18, 3, -24, 16, 23, -14, -14, -4, 15, -8, -3, 1, 9, 7, -5, 11, -28, 9, 16, -11, 9, 35, 3, -20, 14, 13, 33, -6, 21, -11, -18, 17, -5, 18, -2, 0, -14, -1, 16, -6, 29, -2, -7, 0, 32, 1, 5, -8, -25, 3, -7, -3, 18, -11, 0, -22, 20, 11, -14, -13, -35, -9, -9, -17, 16, -20, -11, -18, -10, 5, 11, -4, 7, -5, 0, -12, 19, 1, 19, -6, -5, 9, 47, -12, 19, 4, 19, -21, 43, -22, -8, 12, -14, 17, 4, -4, 2, 10, 8, 5, -15, 25, -20, 15, -7, -7, -5, 2, -11, 7, 10, 9, 10, -2, 20, 15, 19, 18, 0, 9, -8, 15, -19, 11, 38, -15, 8, 14, 28, 15, -5, 15, 27, 15, 19, 6, 13, 12, -19, 23, 24, -16, 0, -17, 5, 1, 19, -7, -8, -5, -5, 12, 23, -17, 11, -2, 19, -19, 14, 9, 4, -4, 11, -9, 9, 10, 8, -19, -7, -5, 22, 18, 19, -30, 12, -2, 17, 15, 7, -11, 7, 0, -4, 10, -16, -14, 5, 19, 8, -9, 22, 14, 2, 8, -10, 27, 3, -20, 18, 11, -15, -20, 19, -6, 25, -25, -36, -2, -5, 8, 26, 36, 28, 22, -2, -12, -25, 1, 24, 11, 23, -5, -21, 4, 18, -12, 22, 1, -12, 18, -14, 5, -9, 16, 9, 6, 3, 1, -20, -22, 24, -13, -2, 8, 1, 1, 23, -21, -15, -19, 10, 44, -22, 9, -6, -11, 8, 14, 4, -24, 4, -24, -11, -19, -8, 5, 34, 33, -1, -12, 10, 16, -6, 6, 39, -22, -27, 9, 3, 10, 4, 7, -16, 20, 0, 20, -6, -2, -7, 6, -4, 2, -5, -6, -12, -8, 20, -20, -11, -16, 13, 11, 55, -7, -19, -5, -4, -21, 8, 2, -5, 7, 21, 9, 27, -25, 5, 17, -17, -23, 20, -8, -30, -15, -1, 10, -5, -11, -21, 0, 0, 20, -9, -17, -26, -11, 11, -19, -14, 7, 15, 27, -21, 6, 17, -16, 19, 0, 22, 18, -5, 9, 20, -6, 0, -13, 22, 2, 30, 6, 10, 15, 6, 8, -21, -25, -13, -15, -4, -19, 4, 24, 2, -16, -10, 11, 6, -9, 12, -18, -21, 31, 3, -9, 5, 17, -16, 39, 2, -16, -5, 5, 26, -3, 13, 18, -5, -3, 0, -1, 14, 10, 42, 18, 9, -19, 4, -17, 28, 3, -32, -26, 15, -15, 11, -6, 13, -3, 17, -1, 14, 16, 4, 1, 10, -23, 29, -26, 4, -11, -18, -10, 2, 4, 26, -13, 36, 1, 1, -17, 0, -8, -5, 17, 2, 10, -22, 6, -24, -18, 26, 22, -14, -33, -36, 0, -2, -17, 48, 20, 17, -16, -13, 2, -13, 5, 5, 6, 11, 2, 1, 7, 13, 1, -19, 14, 1, 3, -55, -15, 4, 8, 40, 0, 30, -12, 7, 9, -39, -9, 23, -9, 42, 16, -4, 7, -23, 0, 46, 5, 20, 22, 5, -16, -23, 12, 14, 33, 33, -1, -1, -10, -14, -2, -1, 1, -2, 0, -17, 9, 5, 9, 2, -5, -7, -14, -7, -11, 11, 10, 26, -24, -4, -20, -15, 15, 4, -22, 35, -5, -21, 14, 17, 8, 12, 17, -8, 7, -5, 11, 16, 8, -22, -3, -14, -3, -12, 12, 8, -20, -33, -18, 5, 12, -1, 1, 24, -6, -19, 13, 2, 18, 14, -5, 12, 13, -4, -13, 25, 6, 11, -2, -8, 11, 15, -17, 48, -6, 37, -12, 15, 2, -15, 8, 29, 32, 19, -14, 21, 13, 19, -1, -24, 8, -12, 13, -23, -8, -11, -8, 5, 46, 6, -21, 21, -17, -3, -12, -2, -14, 9, 5, 17, -11, -22, -2, 25, -29, -17, 8, -31, -6, 36, 14, 4, 17, -16, -15, 15, -24, 12, -16, 9, -15, -1, 21, 48, 4, 19, -6, 2, -8, 9, 3, 2, -19, 6, 11, 28, 34, 1, -27, -2, 7, 4, 14, 14, 0, 0, 15, 27, 3, 14, 16, -20, -22, 15, 21, -7, -8, -18, 4, 24, -25, 35, -2, -28, -3, -23, 15, -6, 15, -7, 8, -28, 15, -13, -18, 22, -2, 14, 2, 8, -21, -1, -10, -18, 16, 21, -4, -22, -14, 21, -4, 27, 1, -17, -3, 6, 7, 19, -12, 22, 14, 42, 25, 0, 11, 3, 5, -1, 12, 11, 3, 10, 0, -24, -12, 25, 31, 0, 18, 29, 0, -18, -15, 37, 23, -18, -34, 14, -4, -13, -22, -9, 22, 20, 22, -2, -4, 7, 10, 16, 3, -17, 3, -34, 6, -49, 16, -18, 5, -17, 48, -24, -15, -20, 18, -4, 9, -14, 11, 2, -2, 42, -6, 4, 3, 15, 3, 18, -13, -6, -6, 9, 4, 23, -25, 5, -2, -1, -7, -2, 0, 13, -4, 14, -20, 1, 9, 2, 25, 17, -6, 17, -3, 8, -1, -10, 29, 26, 3, 33, -14, 13, -8, -11, -49, -27, 26, 8, 16, -16, 4, 21, -50, -10, -2, 14, 8, -17, -16, -11, 32, -14, -11, 20, -10, 38, -8, 31, -16, -16, 5, -12, 8, 4, 16, 15, -1, -32, -4, -2, -23, 12, -7, -18, -2, 14, -71, 6, -18, 14, 15, -1, -10, 4, -12, 15, 20, -7, -5, 38, -36, -7, 5, 20, -5, 13, -14, 31, -32, 4, -14, 23, 10, 21, 8, 1, 12, -19, 7, 27, -5, 7, 20, 25, -57, -2, 4, 5, 18, -6, -3, -17, 8, -14, -11, -12, -5, 26, -21, 18, 5, 24, -22, 21, -6, 29, 3, 14, 9, 39, -9, 8, -15, 30, -14, -1, 25, 22, -58, 14, -12, -16, -6, -19, 25, -27, -7, 23, 4, -4, 19, 13, -5, -2, -8, -8, -8, 9, 20, -2, -1, 3, 11, 11, 21, -14, -14, 34, 8, 18, 15, 34, 9, 47, 11, 3, 17, -18, -9, 15, -9, 5, 2, -7, 15, 28, -16, 34, 17, 11, 2, 10, -1, -10, -14, -15, 8, 3, -20, 19, -5, -5, 21, -35, -8, 18, 7, 2, 26, -7, 7, -13, -20, 21, -2, -16, 27, 24, -5, 12, 20, 16, -2, 22, 26, 56, -19, 13, -15, -16, -14, -3, -19, -7, 21, 39, 12, 11, 22, -23, 12, 2, -3, -20, -14, 27, 18, 31, 3, 70, -23, -20, 15, 21, 9, 30, 21, -5, 0, 24, 17, -17, -22, -25, 15, 42, -8, 28, -1, -16, 9, 34, -24, 29, 6, 11, 14, -27, -11, 37, -21, -10, -2, 16, 1, 15, 0, -6, 18, -19, 22, 7, 8, 14, 10, -11, 0, -3, -5, -12, -14, -17, -23, 23, -8, -9, 13, 4, -1, 28, -4, -2, 2, -36, 11, 18, 9, 41, -14, 8, 25, 15, 17, 4, -19, 31, -18, -10, -7, -11, -16, -11, -23, -8, -21, -1, -9, 1, 11, 16, 9, 18, -8, 7, -3, 0, 11, 6, 12, 16, 22, 6, -11, 33, 20, 30, 11, 4, 19, -13, -35, 27, 39, -15, 16, 4, 18, -13, 28, -14, 17, -11, -22, 34, 15, 1, -12, -46, -13, 64, 15, -17, 8, -26, -21, -1, -9, 15, 7, -5, 13, 18, 16, 36, 14, 37, -11, 18, -4, 44, -9, 4, 15, 3, 1, -11, 18, 1, -23, -16, 7, -8, -19, -1, -8, -22, -9, 62, -25, 28, 17, -12, 12, -6, -5, -1, -9, -16, 9, -2, -21, -7, 6, 47, 20, 6, -7, 26, -13, -5, -14, -36, -34, -6, -21, -9, -11, -1, 20, -7, 19, -28, -5, 10, 6, 36, 14, -10, 18, 1, -17, -36, 19, 16, -37, 8, -4, 21, 4, 2, 10, -34, -27, 25, 11, 10, -9, -14, -7, 22, 24, 20, -3, -2, 8, -29, 4, -7, 14, 50, 13, 15, 4, -11, 20, 26, 9, 24, 21, 15, -12, -15, -8, 15, -14, -2, 12, 24, -12, 25, -2, -20, -21, -48, -10, 7, -18, 5, -22, 24, 11, -1, -5, -13, -20, 12, 17, 29, 3, 4, -26, -21, -3, 5, 12, -8, 1, 8, -5, 22, -15, 3, -1, 2, -9, 11, -7, 44, -19, -7, 7, 18, -22, -14, 8, 6, 4, -2, -22, -34, -43, 13, 18, 12, -11, 20, -10, -41, -1, -28, -3, 10, 14, -3, 8, -12, -9, 20, 5, -32, -9, 33, 2, 19, -3, -15, -23, -22, -8, 4, -17, 23, -27, -16, 9, 17, 7, -38, -11, 16, 19, 26, -3, -14, 14, -4, 6, -11, 18, 28, -10, 11, 17, 29, -18, -3, 3, -27, 5, 7, -16, -15, -19, 3, 30, 12, 16, 12, 3, -24, 8, 19, 1, 17, -12, 3, 13, -2, -16, -44, -14, -3, 1, -31, -2, 27, -2, -4, 9, 9, -12, 7, -23, 11, -8, -7, -6, -33, -27, 5, 3, 26, -11, 0, -4, -21, 11, 14, -19, 23, -23, -5, 8, -20, 15, -3, -12, -11, -12, -11, 15, -21, 4, 19, 15, -14, 1, -28, -8, 32, 6, -14, 15, -27, -2, 12, 27, 20, 39, -12, 8, -34, 6, -2, -24, 20, -2, 41, 6, 42, 12, -34, -20, -23, 5, -32, -2, -6, 2, 15, 41, -4, -16, 9, -13, -18, -17, 19, 11, -6, -44, 31, -2, 25, -11, -24, -32, 3, -11, -21, -6, -25, -19, -7, 24, -4, -4, -17, 17, 36, 7, 0, -23, -28, -2, 26, -9, -4, 0, -26, -31, 17, -8, -7, 8, 23, -6, -21, 12, 3, 28, -22, -23, 0, -2, 28, 24, 17, -10, -8, -1, 10, -11, -6, 3, -13, 4, -19, -3, -8, -7, -8, -17, 11, 2, 7, 11, -23, 1, 11, -13, 9, -14, -5, 18, -26, -15, 33, 21, -16, 16, -25, -1, -17, 16, -11, 14, 11, 17, -15, -17, -23, 10, -1, 0, -24, 11, 1, -16, 7, -10, 4, -16, -5, 13, -20, -7, -17, 16, 34, 14, -4, -14, 15, 9, -13, -14, 18, 7, 4, 11, 14, -2, -16, -20, 16, 22, -23, -20, 18, -12, -2, -5, 16, -15, -35, 16, -22, -6, 23, 6, 6, -21, -37, 21, -33, 2, -23, -13, 24, 8, 13, 18, -16, -18, 0, 0, 0, 3, 0, 0, 22, -9, -18, 17, -5, -2, -28, 16, -11, -14, 19, 5, -20, 5, -15, 18, -24, 16, 0, 14, 3, -16, 0, 28, -2, -11, 10, -5, 9, 8, -1, -1, 11, -21, -17, 4, 10, 9, -17, -2, 5, -23, -2, 9, 14, 5, 17, 9, 11, 18, -17, -21, 18, 6, -13, -9, -21, -2, -4, 8, 13, 12, -7, 25, 0, -13, -24, -5, -13, -11, -4, -20, 74, -19, 6, -6, 5, 20, -12, 8, -6, 1, -5, -14, -18, 1, -22, 13, 10, 11, -19, -16, -29, -29, 14, -24, 4, -21, 10, 6, -12, 10, 2, -9, -23, 3, -9, 12, 20, -18, -14, 22, -12, -6, -38, -14, 2, -46, 10, -21, -3, -3, -5, -24, 17, -11, -16, -14, -10, -18, -14, -3, -19, -32, -44, 25, -1, 17, 15, 13, 3, 10, -6, 11, 33, -16, 25, -23, -23, -3, -16, 30, 13, 15, 1, -16, -24, -12, -34, 25, -40, -4, -20, 6, -5, 9, -23, -6, 15, -3, 10, -4, 10, -25, 17, -2, -7, 6, -23, 11, -14, 1, 10, -1, -6, -14, 9, 1, -8, -4, -20, 24, -11, -11, 38, -5, -19, 18, -18, 9, 13, 18, -2, 9, -3, -5, -20, 46, 1, -17, -1, 17, 22, 14, -8, -3, -9, -4, -9, 14, -1, 17, 14, 7, -18, -18, -3, -5, -1, -4, 4, 15, 14, -16, 3, -1, -11, 6, -8, 3, 17, -23, 8, -10, -21, -6, 7, 7, 56, 4, -7, -17, -12, 33, -2, 1, -17, 7, 8, 12, -7, 9, 0, 16, 41, -19, 0, 6, -5, -2, -9, -10, 0, 9, 2, 23, 17, 17, -8, -9, 13, -11, -3, -3, 18, 1, -1, -3, 25, -20, 9, -15, -22, -11, -32, -8, 22, 8, 37, -6, 32, -9, 18, -3, 27, -11, -6, 0, -18, -1, 0, 27, 35, -2, 3, 4, -16, 3, -6, 4, 44, -16, 16, -17, -31, -16, -1, -14, 69, -19, 19, 12, -10, 13, -8, -9, 9, -13, -25, -13, -15, 7, -11, -15, 5, -7, 49, 7, -15, 8, -5, -4, -4, 15, 24, 15, 18, 15, 10, 2, -13, 3, 19, -11, 16, 10, -7, -12, 40, -1, -3, 7, 9, -4, -4, -7, 19, -19, 7, 8, -5, -13, 4, 13, 17, -18, -2, -22, -14, -16, 8, 4, 51, 7, 5, 14, -30, 0, -10, 30, 6, 12, -4, 2, -15, 11, -37, -17, 33, 16, 7, -13, -18, 26, 6, 13, -10, -2, 40, -16, -25, -14, -10, -34, 25, -11, 3, -12, -5, -8, -3, -3, -1, 6, 17, -20, -15, -5, 4, 19, 34, 3, -3, -9, -7, -12, -7, 0, 16, -1, 28, -14, -4, 5, -2, 17, -3, -15, -9, -16, -4, 22, 15, 0, 6, -19, 47, -11, -8, -31, -33, -26, 1, 8, -39, 4, -27, -32, -14, 6, 24, -10, -13, -10, -14, -22, 17, -7, 18, 16, 22, -4, -25, -1, -6, -9, -60, -19, 9, -6, 1, 6, -1, -1, 12, -1, -45, -8, -17, -17, 18, 8, 15, 2, 11, -1, -9, -7, 0, 2, 25, -11, -11, 10, -5, -22, -9, -10, 19, 11, 0, -9, -41, 10, -22, -2, 10, 14, 17, 5, -24, -6, -4, -8, -1, 8, 25, 8, -9, -12, -31, -13, -26, 13, 10, -18, -16, -3, 10, -19, -19, -9, 15, -21, -17, -18, -7, -41, 2, -13, 19, 8, -26, -43, 18, -37, -6, 18, 3, 7, -27, 14, -13, -14, 11, 12, 11, 8, -8, -18, -40, -11, 33, -15, -46, -17, -8, -11, 12, 35, 18, 2, 21, -19, 1, -46, 19, -12, -16, -1, 11, -5, 18, -19, -27, -27, 6, 8, -1, 17, 9, -10, 3, -21, -29, -17, 32, -10, -19, 10, -31, -20, -29, 23, 46, -5, -23, -26, -38, -28, 31, -2, 4, -13, -22, -17, -23, 4, -13, -24, -12, 10, -12, -13, -15, 21, 20, -3, -3, -22, 2, -16, -18, -7, 14, 4, 5, 12, -21, 13, 8, -10, 31, -4, -42, -20, -23, -22, 51, 2, 16, -10, 18, 16, -12, 3, 10, -23, -5, 10, -16, -23, 24, 39, 1, -4, 4, -7, -5, -9, -6, 6, 12, -15, -26, 16, 5, -15, 9, -1, -34, 26, -5, 3, -4, -6, -24, 10, -7, 25, 18, -9, -12, -18, -13, -7, 29, 3, 6, -4, 0, 9, -16, 2, -7, 28, -7, -3, 6, -12, -18, 12, -17, -1, 16, 11, 23, -4, 1, 9, 1, 13, 31, 2, -5, -11, -7, 9, -12, 15, 24, 2, 22, -11, -23, -14, 12, 6, 2, -23, 28, -12, -11, -15, 6, 10, 6, 12, 8, -18, -15, 12, -20, -23, -8, -2, -9, 2, -13, -16, -5, 22, 32, 3, -17, -15, -32, 6, -6, -9, 42, -5, 6, -21, -20, -1, -42, 4, 11, 7, 3, -9, -15, -28, -34, 21, 5, 18, -13, -23, 4, -10, -35, 4, 25, -3, 18, -3, 0, 17, 5, -3, -11, 10, -8, -24, -30, -18, -26, -14, 16, -3, 14, 18, 1, 10, -10, 13, -8, 20, -4, -12, -28, -3, -3, -74, -15, 12, 14, -14, 12, 2, -9, -10, -19, -19, 15, 12, 31, -26, 19, 32, -15, -5, -1, 17, -7, 8, -4, -2, 24, -19, 6, -11, 14, 20, -21, -36, 21, 15, 8, -3, 6, 4, -24, 34, 0, 5, 3, -21, 11, 11, -17, 0, 5, -11, 24, -23, -21, -23, 23, 4, 21, 11, -4, 15, 2, 9, 3, -12, 21, -4, 16, -8, 37, 12, -4, 26, 11, -1, 11, 13, -3, -32, -16, 6, 16, -8, -7, -3, -1, -3, -3, -18, 4, -22, 21, -4, -1, 23, -18, 1, -16, 10, -9, 1, -13, 20, 4, -17, -2, -2, 12, 0, -28, -3, 40, -16, 23, -8, -10, -18, 8, 23, 28, -35, -19, -11, 26, -21, 6, 0, -24, 20, -6, -13, 22, -9, -3, -5, -23, 9, -11, -2, 1, 17, -6, 1, -13, -26, 20, 6, 20, 15, 15, 17, 3, -1, 13, 15, 22, 2, 28, 25, -7, 17, 27, -10, 11, 15, -16, -44, -12, -25, 27, -17, 21, -18, 10, -3, -4, -22, -11, 20, 15, -15, 19, -2, 7, 16, -13, -14, 16, 11, 29, -4, 13, -23, 8, 1, -14, -1, 10, 5, -3, -17, -12, -6, 17, -1, -1, -29, -11, -12, -2, -4, 4, 11, 28, 21, 22, 6, -16, 12, -9, -5, 15, 13, -27, -23, 7, -20, 2, -16, 6, -2, -11, -3, 44, 10, 29, -22, 19, -7, -32, -22, 0, 1, 8, -3, -8, 18, 22, 0, 29, 7, 22, -1, 14, 9, 4, 37, -35, 8, 36, -14, 14, -14, 25, 25, 32, 3, 2, 4, 20, -7, -14, -12, -12, -16, 42, 12, -7, 10, -4, 10, 19, -6, 7, -5, 12, 22, 9, -16, -8, 11, 5, 2, 0, 40, 14, 26, 3, -13, 4, -12, 7, 6, 27, -8, 24, -16, -6, 4, -6, 31, 8, -43, 10, -13, 21, 14, -11, -14, 4, 5, 11, 6, 9, -12, -18, -45, 13, -6, -21, 18, -38, -14, 17, 0, 25, -24, 26, 13, 0, 7, 22, 2, -5, -30, -16, 18, 10, 6, 12, -14, 5, -17, 7, 15, -14, 17, -33, -41, 7, 12, 8, 1, 29, -22, 0, 19, 19, -3, -9, -13, -11, 8, -9, -10, -27, -1, -31, 17, -7, -14, -20, 2, -27, -20, -7, 21, -15, 14, -5, 25, 14, 20, -17, 0, 15, -5, -23, -5, -9, 7, -5, -2, -12, 0, -7, -35, -25, -37, 1, 11, -5, 1, -30, 23, 6, 16, 13, 13, 11, -17, 3, 35, -16, 40, 11, 17, -5, 21, 35, -18, -6, -14, -2, 10, -37, -17, -24, -24, -34, 18, -16, 18, 3, -3, 7, -11, -5, -15, -4, 16, -14, -12, -26, -3, 8, -63, -4, -1, 4, 3, -39, -12, -33, -13, -1, 0, -5, -11, 5, 38, -2, -13, -14, -21, -13, -18, 0, 7, 5, 14, -2, -7, -32, 6, -25, 15, -22, -5, -6, -9, -4, -12, 13, -12, -6, 14, -10, -11, -17, 15, 6, -33, -22, -57, -10, 8, 32, -11, -14, -30, 12, -20, -2, 10, 19, 16, -40, -24, 21, 29, 19, -12, -6, 18, -8, 22, -8, -5, 9, -6, -2, -7, -18, 49, 0, -33, -13, -19, -21, -20, 0, -4, 8, -29, -1, 7, 27, -14, -24, -3, -10, -34, 10, -20, 15, -13, -40, -59, -34, -42, 11, 9, -13, 0, 1, -2, 4, 0, -20, -18, 10, 9, -8, -12, -1, 5, 5, -1, -10, -18, -30, 8, 2, 1, -17, -4, -17, 3, -17, -19, 3, 18, -9, 17, 16, 4, 22, 21, -18, -7, -28, -16, 18, -17, -5, 4, 12, 2, -6, -3, -18, -6, 22, 3, -1, 13, 11, 14, -32, 19, 2, 20, 9, -10, -1, 8, 16, 7, -28, -15, -8, 49, 6, -10, 24, -2, -10, 34, 9, -2, -3, -11, -12, 13, -8, -1, 12, 7, 8, -21, 20, -9, -1, 13, -8, -28, -1, 12, 4, 1, 15, -8, 7, -40, 4, -18, 8, -19, 14, 2, -5, -1, 4, -13, 13, 1, 2, -11, 5, -25, 11, 5, 20, -17, 7, -22, -17, -14, -27, 1, -9, -16, -41, -19, -8, -4, -11, 10, 35, -23, -22, 17, 22, -27, -8, 1, -7, -7, 15, -11, -21, -1, 14, -21, 0, -13, -47, -10, 6, -15, -10, 2, 24, -12, -29, 20, -29, -10, -10, -15, 7, 1, -7, -11, 2, -28, -5, 5, -13, -16, -41, -37, -4, -16, -23, -19, 9, 14, -9, -25, -25, 13, -26, 13, 7, 12, -26, -14, -14, -27, 14, 7, 2, -18, 18, -17, -39, 11, -9, -22, 18, -22, -25, 15, -1, 28, -6, -14, -12, 17, -17, 10, -13, 2, 8, 8, -17, 9, -25, 25, -19, 15, -12, -22, -2, -15, -16, -34, -19, 21, -4, 13, -14, -11, -10, 10, 27, 8, -3, -13, -7, 8, 13, 25, -24, -3, -6, -9, -5, -14, -8, -32, 18, -7, -10, -6, -5, 0, -3, 13, -18, 5, -8, -22, 16, -1, -26, 21, 10, 6, 21, -7, 19, 8, -3, 14, -25, -2, 1, -8, 17, -17, -8, 16, -12, -2, -27, 4, -16, -15, -5, -14, -20, 4, -14, 3, -13, -2, -30, -3, -14, -2, 3, 1, -3, 13, -16, 9, -3, 25, 0, -24, -14, 7, 10, 3, -15, -4, -5, -9, -4, 13, -29, 4, 14, -5, -11, -20, -13, 0, -2, 0, 16, 10, -24, 0, -21, 17, -6, 4, 2, -29, 21, -12, 18, -2, -29, -8, -18, 5, -8, -5, -3, 4, -7, -18, -2, 0, 12, -19, 11, 8, -29, 11, -22, -24, 1, -21, -20, 1, -27, -5, -5, 9, -12, -2, 2, -20, 14, -8, 19, 4, -9, -23, -16, 4, 8, 3, -15, 3, -11, -15, -6, 6, -22, -7, -26, -13, -13, 13, 27, -13, 3, -5, -6, 6, -25, 4, -3, 16, -18, 25, -22, -14, 12, 10, 1, 13, 21, -39, 21, 4, -4, 0, 5, -1, 16, -15, -33, -2, -18, 8, -7, 14, 9, -13, -5, 1, 9, -11, -22, 19, 4, 7, -39, 0, -9, -18, 5, 3, -14, 10, 0, 19, -17, -19, -1, 18, -36, -2, 0, 6, 3, 0, -21, 4, 6, -1, 9, 3, 13, -12, 0, -11, -19, -12, 18, -4, -10, 7, -15, 11, -4, -8, -33, 20, 18, -18, 6, -7, 12, -3, 20, -32, 21, 2, 28, -3, 21, 3, -4, -35, -6, 5, -20, -21, 19, -29, -4, 4, -13, -3, -4, -10, -9, 26, -8, -3, 27, -6, -4, 8, -7, -6, 19, 10, 7, -4, 24, -22, 1, 13, 1, -17, -15, -10, 0, 14, -14, 27, 13, 3, -34, 10, -5, 19, -41, 2, -3, 10, 8, 7, -4, -17, -24, -18, 10, -7, -23, 9, -3, -4, -14, 12, 14, 13, -10, 8, 20, 3, 13, -3, -21, -1, -8, 15, 2, 6, 7, 9, -11, 6, -24, -14, -11, -12, -12, 6, -13, 32, -24, 9, 29, -10, -9, -52, -17, 19, -14, -17, -10, 13, -13, -9, -27, 5, -37, -18, -18, -9, -47, -2, -2, -16, -32, -11, 6, 18, -32, 7, -13, 4, 6, 10, 10, 13, 2, 28, 24, -23, 5, 2, -5, -17, -13, -13, -24, -48, 16, -1, -12, 18, 12, -20, -12, -8, 18, -7, -22, 5, 19, -21, -24, 10, -22, 12, -4, 2, -9, 8, 3, -13, -3, -10, 2, -10, -5, 18, -12, 7, -11, -18, -30, -18, -43, -14, 1, 18, -25, -8, 5, 1, -17, 44, 3, 5, -31, -4, 15, 8, -18, -3, 37, -38, 13, 8, 14, -1, -17, -9, 17, -52, -34, -21, -18, -21, -16, 25, -5, 18, -16, 8, 5, -11, 1, -11, -6, 14, -11, -11, -19, -6, -10, -13, 1, -10, 4, -6, -17, 4, 9, -40, 1, -17, 7, -17, -9, -7, -33, 6, 6, -3, -19, 20, -15, 7, -34, -7, 5, -14, -8, 1, 4, 3, 8, -7, -18, 11, 3, 15, -10, 11, 14, 8, -43, 17, -45, 11, 6, 4, 10, 25, 3, -11, 4, 13, 5, -8, 2, -22, 0, 17, 16, -6, 15, 8, -9, -43, 12, -3, -35, 9, -17, -14, 13, 18, 3, 3, -2, -15, 11, -7, -40, -25, 25, 0, -9, -9, 26, -18, -17, -8, -36, -14, -7, -14, 18, -9, -23, 18, 15, -22, 6, -6, -4, 6, -5, 18, 2, -4, -15, 9, 12, 14, 21, -32, 17, -21, 6, -13, 0, -11, 30, 5, 9, 28, -12, -3, -6, -3, -31, -2, -13, 16, -1, -2, -1, 12, 34, -4, 13, -35, 12, 14, 2, -7, -19, 2, -13, -14, -26, 8, 3, 10, -17, -28, -10, 28, 9, 16, 5, -20, 20, 8, 24, -31, 27, 13, 8, 9, -33, 11, 4, -16, -5, 2, 22, 1, -9, 22, 11, 3, 2, -14, 16, -8, 15, -32, 8, 0, -2, 10, -8, -10, 8, -19, 40, 4, -35, 12, -12, 13, -7, 15, -14, -28, -6, -10, -3, 3, 20, 4, -31, -29, 4, 10, 21, 16, 5, 4, 24, -30, -5, 6, -4, 2, 0, 34, 21, -9, -11, 7, 10, -2, 18, 10, -8, -18, 8, -9, 21, -12, -6, -4, -13, -6, -5, 16, 11, -18, -17, -4, 2, -4, 0, -7, -17, 9, 16, -4, 4, 1, 7, 10, -4, 6, 21, -1, -12, -8, 13, 4, -2, -16, -29, 10, 27, -10, -5, -12, -14, 5, 26, 16, -6, 13, 7, -5, -17, 3, -8, -15, -3, 11, 3, -18, 11, 18, -28, 19, 3, -43, 1, -6, -9, -2, -20, -3, -29, 0, 27, 19, 11, -16, -11, -18, -21, 4, -6, -20, -19, 14, -20, 8, -17, -12, 11, -5, -1, -2, 9, 12, 9, -9, -8, -5, -8, 14, -3, -20, 9, 0, -14, -20, -9, 17, 6, -24, -42, 26, -25, 16, 21, -2, 6, -20, 20, -24, 9, -13, -10, 18, -17, 8, 7, 17, 5, -7, -9, -4, 6, 2, -25, -15, 9, 15, 18, -21, -9, -3, 10, -5, -7, 3, -27, -8, -24, -28, -8, 9, 37, 1, -10, 2, 21, 0, -7, 22, -29, -2, -2, -18, 5, 35, 8, 5, -5, -3, 6, 9, 15, -13, -33, 6, 5, 6, 1, -4, -9, 17, -10, -16, 17, 7, 11, -5, 11, -26, -9, -17, 6, -7, 14, -6, -4, -10, -6, -6, 8, -4, -12, 0, 3, -5, 0, 29, -12, 0, 1, 19, -2, 9, 11, -20, 17, -3, 13, -13, -18, -33, -10, -17, -10, 10, 30, -7, 16, 15, 12, 2, 9, -11, 23, 11, -30, -11, -18, -17, -1, -7, 23, 18, -7, 18, -13, -26, -22, -9, 24, 12, -21, 28, 2, -14, -16, 17, 23, 14, 11, -1, -21, 16, -31, -2, 19, 12, 4, -15, -11, -2, -5, -8, 15, -19, -24, -14, 8, 9, -1, -18, -20, 3, -10, -19, 29, 14, 25, 2, 24, -24, -19, 6, 13, 13, -3, 2, -25, -15, -12, 8, 11, 11, -6, 15, 2, 19, -14, 32, -6, 8, 6, -4, 24, 12, -18, 17, -26, 14, -7, -1, 23, 0, -33, -2, -6, 13, -11, -3, 2, 17, -10, 4, 3, 23, 11, 2, 3, -15, 20, 1, 7, -25, -2, 11, -7, -4, -12, -26, -7, -14, -13, 17, -12, -12, -6, 6, -10, -22, -3, 4, -5, 11, 18, 13, -12, 22, -8, -19, 15, 7, 22, -2, -15, -13, -9, -15, -3, -23, 8, -14, 2, -25, 3, -10, -23, -37, -10, 27, 8, 11, -5, -20, 5, -9, 6, -23, -14, 1, 17, 14, 3, -19, -1, 5, -11, -18, -24, 16, 12, 5, 24, -9, -10, -1, -11, -25, 6, -26, 29, 8, -3, 21, -10, 8, -11, -20, 18, 7, -10, 18, 4, 23, 36, -7, 10, 1, -19, 5, -22, -3, -20, -39, 23, -3, 12, 21, -14, -28, 15, -17, 25, 3, -23, 13, 2, -19, -9, -21, -25, 15, 8, -7, 14, 13, 0, -3, 6, -18, 11, -11, 9, 5, -33, -27, -22, -19, -5, 20, -4, 13, 1, -23, -9, -17, -11, -11, 22, 22, -9, -21, -23, -10, 7, 14, 10, -19, -18, 6, 40, -18, -28, 23, 6, -30, -19, 4, 18, -20, 22, 9, -16, 17, -14, -22, 10, -5, -7, 4, 17, -35, -21, -15, -17, -16, 32, 20, 8, 2, -22, -23, -13, 16, 9, 16, 21, -16, 11, -21, -4, 4, -6, -1, 17, 1, 3, -24, -3, 17, -22, -29, -9, -8, 11, -34, -20, -10, -18, 6, -11, 11, -10, -1, -13, -19, 2, 17, -25, -18, 16, -4, -10, 3, 16, 3, -9, 21, 19, 4, -12, -4, -19, -8, 24, -16, -23, 7, -2, 2, -26, -5, -12, 9, 32, 17, 17, 9, -20, -4, -2, -9, 9, -1, 22, -13, 2, 19, -15, 0, -44, -2, -12, 5, 4, -1, -14, 7, 18, -6, 13, 15, -35, 16, 6, 10, -15, 15, 31, 28, -3, -14, -6, 6, -19, -14, 4, -11, -33, -12, 25, 19, -12, 14, -11, -6, 36, 2, 5, -17, -16, 2, -23, -8, 22, -10, -16, -9, -16, 8, 18, 15, 36, 5, 15, -21, -4, 9, -6, -8, 7, -18, 8, 9, 10, -7, -16, 0, -29, 15, 14, -1, -20, -13, -5, 21, 1, 8, 14, 5, 24, 12, 10, -15, -50, 6, -23, -13, -10, -23, 54, 6, 40, 1, 4, 21, 1, 1, -46, 14, 6, 32, 21, -8, -20, 7, -26, 11, -17, 15, 15, 4, -5, 14, -22, 16, 32, 6, 23, -11, -10, -4, -47, 3, 22, -1, 10, -40, 2, 5, -7, 10, -9, -32, 56, 25, -27, -24, 32, 15, 23, 15, -19, 0, -24, 18, 11, -14, 8, 35, 1, 3, -6, -9, 3, -2, 15, 28, 40, 7, -16, 30, -38, 2, 20, 16, 17, -23, 10, 10, 5, -16, 1, 0, 29, -23, 0, 21, -9, -10, -4, -6, 1, 3, -18, -24, -27, 2, 7, 19, 15, 23, 13, 2, 20, -10, -2, 21, 25, -16, 5, -4, 24, 26, -23, 5, 3, 10, -11, 24, -2, -6, 29, 13, -20, -3, 3, -8, 36, -15, -27, -14, 12, 20, -16, -11, 2, -3, 8, 28, 34, 5, 2, -20, -33, 11, 9, -3, -10, -7, -38, -7, 32, 27, 35, -19, 13, -5, -9, 12, -6, -2, 4, 19, 22, 8, 37, -6, -19, -7, -9, -12, 16, -5, 4, -7, -13, -13, 21, 4, 12, -18, -5, -19, 26, 23, 22, -14, -38, 42, -16, -10, 18, -10, 1, 15, 27, -2, 21, -13, -6, 22, 19, 22, 21, 18, -8, -8, 27, 7, 32, 33, -14, 16, -35, 8, -17, 12, 46, 18, 19, -10, 7, -22, -36, 10, -6, 28, 18, -9, 1, 10, -33, 16, -1, -35, 13, -2, -5, 8, 21, 39, 15, 11, 1, -17, -9, -12, -16, 12, 3, 23, 3, 4, 2, 8, 23, -14, 18, 41, 0, -5, 16, 4, 19, -7, -19, 39, -12, 38, 2, 11, 31, -8, -2, -8, -13, 20, 18, -5, 18, -10, 18, 14, 8, 20, -17, 3, 20, 22, 1, 23, 4, 9, -31, 2, 14, 8, 10, -11, -18, -8, 6, 1, 37, -14, -1, -13, 6, -13, -6, -3, 26, 12, 27, 10, 7, -6, 20, -14, 7, -9, 6, 10, -8, 7, -6, -6, -1, -6, 12, 6, -23, 13, 15, -37, 30, -16, 32, 5, 14, -28, -12, -10, -15, -13, 16, 39, -16, -8, -15, -16, -10, 12, -9, 21, 4, 16, -12, 25, 8, -8, -3, -8, -4, 18, -25, -7, -11, -3, 27, 25, -7, -12, -11, 19, -1, -15, 24, 2, -29, -44, -33, -2, 33, 20, 6, 17, 20, 25, 19, -12, 30, -8, 3, -12, 0, 35, -33, -23, 14, -6, 46, 4, 2, -4, 10, -15, 22, 12, -29, 14, -13, 13, -23, 17, -12, -1, -13, -11, -1, 5, -11, 10, 8, 17, 8, 9, 1, -7, 5, -17, 29, -13, 12, 16, -16, -1, -16, -2, 10, -1, 38, 11, 5, -21, -4, 15, -35, -23, 10, -15, 6, -26, 1, 18, -2, -2, 26, -33, -5, 17, -18, 7, -5, -7, 2, 26, -14, -13, -27, -8, 2, -9, 1, 12, -5, 0, 4, -33, 4, 5, 0, 17, -3, -11, 13, 11, -54, 16, 13, 8, 10, 1, -1, -14, 1, -8, -12, 20, 14, -5, -4, 24, 3, 15, 4, -3, -5, -17, -33, -7, 28, 8, 28, -11, -18, 0, -11, -1, 24, 10, -6, 16, 5, 22, 18, -9, 11, -30, 30, -11, 5, -18, -14, -29, 28, 1, 6, -1, -10, 7, 2, -12, 4, 25, 3, -10, -10, 3, -7, 12, -26, 0, -6, 2, 8, -26, 15, 9, -8, 12, -1, 20, -6, -27, 10, -12, 1, -2, -43, 31, 6, -21, 30, -1, -1, -18, 4, 6, -16, -2, 13, -37, 9, -18, -4, 19, 17, -17, 11, -12, -32, 1, -23, -11, -9, -12, -9, -17, -15, -40, 34, -1, 2, -19, 16, -37, 6, 7, -10, 8, -10, -7, -17, 0, -18, 4, 15, -8, 17, -22, 15, -4, 9, -23, 22, -15, -3, 5, -5, -33, -9, 9, 15, 7, -9, -15, 14, -28, -30, -8, -29, -11, 16, 3, 3, -17, -23, -23, 12, -23, -17, -23, 30, -19, 14, 7, -32, -19, -2, 4, 7, 4, 2, -7, -39, 8, 19, -2, 34, -14, 8, -13, -6, -6, 18, -3, 13, -24, -12, -13, 18, -8, -6, 6, 5, 9, -32, 21, -15, -24, 24, -30, -17, -3, -28, 7, 22, -10, -3, 0, -25, -3, -11, 13, 27, 8, 19, 18, 4, -14, -12, -6, -25, 17, -9, 0, 1, -14, 10, -16, -13, 23, 13, 10, 11, -33, -32, -15, -20, 1, -11, -14, 8, -31, 5, 3, 4, -2, -7, 10, -26, -3, -27, 3, -26, -31, -13, -19, 16, -7, 10, -20, 36, 24, 32, 2, -13, 15, -1, 2, 20, -4, 3, 0, 27, 15, -14, 14, 1, 1, -13, -32, 0, -1, 10, 21, -68, -16, -15, -1, 28, -21, -1, -16, -37, -10, 21, -16, -4, 9, -11, -67, 0, 9, -5, 31, 9, -9, 3, -6, 10, 9, -2, -7, -19, 6, 23, -21, 1, 23, 2, -22, 5, 13, -8, -12, 22, -6, -15, 9, -5, -13, 7, -13, -23, -9, 7, 5, 9, -7, -16, 21, 6, 11, -26, 10, -6, 6, 2, 21, 4, -37, -8, -8, 15, 13, 1, 21, 15, -4, -14, 2, 29, 28, -2, 11, -47, -5, -8, -4, 7, 1, -17, 9, -31, -10, 0, 10, 24, -31, -15, 55, -16, -14, 11, -17, -30, -10, 0, -6, 21, 7, 25, -14, 22, 0, -29, 10, -9, 19, -1, -36, -13, 21, 33, 5, 24, 13, 28, 29, 18, 4, -9, 11, -22, 16, -21, 11, 13, 5, 16, -1, -31, 26, 36, -7, 23, -36, 6, -3, -29, -15, -4, -19, 15, 5, 15, 24, -11, 11, 5, 9, -14, 8, -41, -15, 3, 14, -20, -19, 15, 6, -15, 38, 4, -3, 2, 7, -19, 1, 25, 8, 6, -2, -7, 23, 4, 15, -22, 14, 26, 23, 19, -26, -17, -2, 9, 17, -42, -22, -19, 22, 10, 0, 24, 21, 0, 17, 2, 12, 10, -17, 2, 1, 25, 6, -7, -18, 31, 8, 10, 37, 7, -12, -13, 0, 19, -18, 11, 30, -28, 21, 9, 2, -9, -6, -13, -3, -13, -35, 9, 2, 5, -10, 16, 9, -10, -5, 4, -4, -1, 18, -12, -43, -22, 21, -15, -12, 8, -2, 16, 5, 1, 40, 13, 30, -14, 7, -15, -7, 18, -12, 0, -13, 14, 9, 13, -3, -12, 29, -48, -11, -3, -8, 17, 16, -9, -12, -30, -12, 25, -21, 21, -1, 9, 9, 8, -17, 0, -12, 11, 9, 6, -8, 10, -14, 0, -5, -6, -33, 19, -5, -6, 7, -34, -17, 1, -5, 4, 32, -9, -21, -26, 23, 30, 28, -19, -14, 7, -5, -19, 10, -5, 27, -16, -19, -36, 0, -13, -14, 3, -5, 15, -19, 8, -21, -34, -11, 2, -9, -1, 11, -14, 15, 11, -10, 17, -3, 5, -17, -7, 5, -11, 5, 20, -28, 17, 26, -23, 16, -6, -21, -4, 0, 19, -8, -11, 17, -12, -22, -17, -4, 32, 23, -2, 15, -8, -8, 0, -15, -28, 5, 0, -13, -22, 13, -8, -17, 31, 0, -18, -18, -12, -3, -10, 26, 15, 20, -15, -9, -16, -2, 6, 12, -2, 11, -40, -28, 2, -23, 27, 4, -14, -10, 33, -26, -22, -13, 19, -14, -19, 22, -1, 5, 9, -3, 2, 10, -15, -10, -21, -21, 20, 4, -4, -26, -17, -25, -38, -18, -3, -27, 6, 1, 23, 0, -16, 9, -16, 7, -38, 1, -6, 8, -5, 4, -14, -28, -11, 28, -5, -15, -3, 7, 14, -8, 11, 7, 6, 19, -36, -12, -17, -26, 9, 0, 4, 37, 11, -2, -17, -3, 15, -20, -20, -6, 17, -17, -3, -9, -6, -12, 0, 13, -4, -27, 27, 20, -6, 13, 15, 27, -5, -15, 14, -29, 16, 12, 3, -23, -24, 16, -6, -23, -14, 0, 15, -23, -12, -31, 19, -4, -1, 10, -5, -15, -29, -1, 19, -34, -8, -1, -2, 23, 10, 10, 6, -32, 19, -35, -8, 17, -22, -13, 1, 2, -37, -15, 26, 11, 21, -14, -20, -16, 6, -30, -9, 17, 6, -7, 24, -6, -13, -13, -4, -5, -5, -16, 11, 4, -2, -26, 8, 13, 9, -6, 9, 2, 4, 11, 0, 17, -7, 20, 25, 18, 13, 13, 14, -22, 5, 2, -10, 12, 0, 6, 1, 20, 17, -5, 20, 20, 12, -16, -28, 11, 1, 12, 8, -28, 32, 13, 16, -2, 13, -6, 16, -13, -2, -12, -2, 14, -2, -18, -11, -18, 16, -15, -13, -27, -2, 3, 3, -12, -20, -2, 7, 22, -10, -10, -4, -19, 19, -2, -3, 20, 12, -29, -13, -2, -5, 15, -22, 5, -3, -6, -12, 22, 18, -16, -12, -10, -3, -11, -3, -25, -25, -8, 8, -2, -5, 13, -9, -13, 4, -8, -48, -12, -15, 16, 18, -28, 22, -9, 13, 36, 11, -24, -18, -5, -7, -7, -6, 22, 12, -30, -2, -26, -19, 32, 10, -23, -4, 17, -8, 4, 1, 22, 12, -22, -7, -10, 20, -30, 21, -12, 7, 7, -16, 15, 28, -26, -16, -6, 9, -20, -10, 9, 0, 10, 19, -24, 4, 6, -20, -26, 36, -3, -6, 6, 24, -9, -2, 3, -11, -5, -13, 8, 14, -13, 19, 28, 18, -30, 4, -1, 9, 7, -19, 4, -5, -1, -8, -4, -1, -2, -19, -13, -3, 6, 20, -21, 16, -24, -6, -19, -9, -6, 10, 29, -2, -22, 0, 8, 7, -6, -6, -10, 3, -5, -1, 16, 40, -2, -13, -11, 4, -7, 0, 7, 18, -38, 32, 18, -11, 27, 13, -19, -11, -23, 6, 2, 9, 20, -13, 12, 19, -18, -5, 5, 31, -27, -2, 7, -19, 10, 22, -14, -7, 7, -24, 22, -25, -12, -13, -17, -27, 21, 4, -11, 14, 5, -3, 15, -28, -15, -9, 23, -19, 4, -16, -14, 20, 7, 29, 5, -36, -1, 31, -23, -21, 13, -38, 1, -14, 1, 19, -14, -30, -21, 17, 16, 28, 1, 14, -2, -5, 12, -3, -33, -21, -14, 1, -3, 0, -10, 21, -10, -1, -19, -7, 7, -15, -17, 37, 19, 4, 21, -24, -2, 11, 4, 10, -3, 15, -22, 1, 30, 1, -1, -27, 3, -6, 10, 5, -11, -7, -7, -25, -10, -2, 6, 6, -17, -2, 4, 3, -4, -10, -35, -8, -31, -19, 1, 26, -6, 3, 13, 13, 26, 2, 16, -1, 9, -11, 4, 41, 20, -23, -7, -27, -12, -3, 6, 19, -10, -11, -14, -17, -27, -23, -4, -5, 8, 18, 5, -8, 10, 28, -23, -14, 10, -10, 17, -20, 25, 2, -24, -6, -16, -7, 26, 18, -8, -1, -9, -9, -1, 1, 18, -4, -1, 26, 16, 3, 27, -30, -7, -29, -40, -1, -16, -8, -2, 15, 5, -2, -17, 30, -18, -1, -21, 13, 2, -4, -23, 18, 19, 2, -33, -3, -24, 25, 17, 0, -2, 10, -18, -3, 15, 20, -26, -3, 1, 29, -6, -37, -10, -8, 10, 3, -4, -5, -32, 15, -24, 16, -11, 1, -22, -2, 19, -10, -11, -29, -11, 23, 12, 13, -14, -25, -29, 3, 10, -1, -24, 46, -47, -8, -3, -19, -10, 3, 6, 8, -4, -7, -8, 4, 20, -6, -25, -17, -52, 24, -22, 11, 6, 18, -14, 6, -36, 33, -5, 13, 13, -25, 5, 26, -13, -13, 21, -3, 5, 6, -24, 14, 15, 33, -16, 17, 13, -12, 18, 23, -1, -1, -21, 11, 21, 25, 6, -19, 10, 24, -2, 11, -3, -12, -8, -9, -7, 0, -15, -3, -27, 0, 1, -1, -5, -6, 29, -5, 25, -13, 14, -14, -16, 7, -33, -17, -15, 6, -8, 25, 18, -3, -22, 6, 9, 1, 24, 15, -4, 11, -2, 14, 7, -1, -11, 9, -40, -2, -15, 17, -18, -19, -17, -34, -22, -11, 8, 20, -21, 20, -17, 4, -17, -4, 12, -13, 22, 0, -4, -7, -25, 18, 6, 4, -4, 9, -5, -16, 17, 9, 10, -12, -10, 8, -3, -15, 4, -3, 13, 16, 1, 6, -11, -13, -2, -1, 15, 25, 5, -15, -16, -25, -14, 26, 17, -4, -25, 13, 9, 20, 20, -5, 8, 30, -10, 23, -5, 14, -16, -24, -5, -26, -1, 6, -15, -26, 27, 6, 20, 3, 10, 9, 21, -26, 13, 19, -9, 13, 21, 22, 4, -18, -9, 20, -29, 16, -8, -16, 6, 12, -12, -6, -13, 5, -29, 5, 5, 14, 0, -12, -5, -14, -19, -1, -17, -3, 9, -16, 5, -6, -9, 0, 8, 10, 9, -13, 9, 2, 9, 4, 13, -37, 15, -21, 23, 3, -35, 8, 17, -18, 26, -12, -4, 31, -2, 8, -12, 8, 25, 4, 16, 9, -5, 23, -12, 0, 6, -6, 6, 10, -2, -6, -27, -25, -9, -23, -9, 10, 0, -14, -2, -4, -18, 2, 25, -19, -7, 0, 0, -22, -21, -31, -2, 5, -24, -17, -11, 11, -15, 4, 10, 5, 19, 5, 20, 13, -22, 28, 8, 14, -11, 21, -10, -18, 3, 5, 6, 17, 24, 5, -20, 3, 13, 6, 1, 3, -6, 20, -6, 3, -3, -8, 6, -53, 22, 26, -15, -7, 26, 16, -4, 21, -14, -23, 18, 3, -31, -9, 23, 21, -31, 9, 10, -7, -18, 20, 21, -29, 13, 5, 5, -1, 22, -19, 13, 22, 15, 7, -14, 15, 1, 10, 14, -17, -11, -24, 9, -5, -10, -16, -1, 1, 0, 2, 7, -18, 13, 18, -14, -10, -6, 23, -38, -10, -7, 6, 6, 5, -4, -26, -19, 26, 17, 22, -4, -10, 0, -1, -17, 32, -14, -4, -15, 16, 5, 0, -39, -7, -11, -14, -5, -14, -4, 19, -3, 43, 23, 13, 9, -19, 18, -21, -19, 0, 23, -19, 13, 13, -5, -25, 4, -14, -11, 16, -6, 24, -20, 29, -13, -1, -19, 16, -6, 22, -23, 25, -14, -14, -25, 24, 16, -16, -5, -23, 6, -28, 16, -10, 12, 13, -31, -14, 9, -16, 14, -2, -17, 26, 6, 1, -3, 10, -7, 14, 1, -7, -15, 17, -18, 11, -3, -3, -10, -23, 14, 33, 5, -6, 13, -7, -1, 13, -25, 10, -35, 6, -9, 12, 23, 17, -21, -7, 12, 6, 8, -30, 12, 6, 18, -28, -7, -4, -8, -4, 15, -22, 20, 26, -22, -14, -33, 17, 21, 3, 4, -1, -16, -22, 30, -16, -18, -5, -1, -6, 14, 4, 10, 13, -19, 10, -6, -11, 17, -8, -1, -25, 16, -9, -3, 3, 9, 1, 29, -35, 1, 20, 2, 43, 34, -29, -26, 22, 8, -16, 9, 1, -16, -18, -14, -19, 31, -3, -19, 7, -9, -8, -5, 26, -28, 45, 6, 8, -4, -13, -4, 11, 1, 11, -14, -34, 0, -30, 15, -9, -7, 7, -23, -15, -10, 0, 6, -26, 0, 15, -20, -1, 23, -9, 24, -3, -25, 18, -11, -7, -3, -12, 5, 5, 15, -3, -5, 9, -26, -15, 11, 0, 29, 11, -10, 4, -17, -24, 19, 12, 10, -13, -5, 13, -14, 14, -5, 0, 1, 16, 19, -9, 9, -14, -10, 11, -8, 14, -11, -14, -7, -18, 3, -37, -4, 8, -12, 8, -10, -17, -1, 16, 19, 5, 1, 6, 7, 7, -7, 4, -14, -35, -3, 10, -17, 8, 16, -9, 2, 28, 16, -4, -8, 3, -1, 2, 9, 0, -4, 9, 5, 14, 11, -5, 7, -12, 31, -17, -3, 1, -4, -5, -22, 40, -21, 15, 14, 0, -19, -13, 35, 26, 12, 11, -32, -2, -9, 22, 10, 8, -18, 24, 13, 17, 9, 17, -26, 34, -36, -15, 11, -9, 41, -8, 0, -23, 6, -10, -5, -25, 5, -1, -60, -24, 11, 6, -34, 6, 0, -3, 17, -18, 9, 28, 20, -2, -21, 1, -15, 8, 20, 8, -2, 2, -16, -27, -1, -7, -31, -12, 17, 39, 20, 7, -41, 16, -9, 20, 15, 35, 24, 2, -20, -13, -19, -4, 9, -12, 8, -5, -38, 20, 29, 9, -5, -18, -31, -13, -40, -10, -11, -7, 6, -10, -3, -22, -37, 15, -6, -32, -7, -11, -12, 21, 38, -4, -35, 1, -34, 19, 38, -7, 32, -6, 7, 6, 18, -15, 1, -8, -3, 14, 11, 27, 4, -21, -7, -4, -4, 13, -38, 4, 19, -10, 16, -3, -35, 17, -8, 10, 2, -12, -8, -1, 19, 31, -41, 6, 11, -5, 21, 3, -2, -3, -40, -19, -12, 37, 32, -28, 9, -4, -4, -14, -5, -16, -10, -25, 15, -6, -43, -16, 1, 26, 38, -6, -2, -32, 7, 7, -14, 27, 21, 2, 6, -7, 22, -17, -19, -27, 10, 0, -2, -2, -19, -2, 14, -13, 31, 20, -31, 8, -7, 6, 6, -19, 13, -29, 17, -3, -11, -1, -4, -18, 0, -14, -4, -12, -23, -28, 11, -11, -7, 0, 20, 9, -18, -34, -1, -3, -8, 2, 15, -1, 1, -13, 9, -21, 6, 0, -3, 19, 8, -11, 5, -12, -17, -23, -1, 20, -14, -9, -20, 6, 10, 6, -5, -20, 12, -11, -24, -7, 22, -4, 22, -12, -19, -28, -4, -28, -13, -15, -13, -23, 10, -17, 7, -19, -2, -22, 0, 1, 1, -28, 8, -23, 34, -6, 18, 18, 0, -11, 4, 22, -15, -56, 36, -4, 10, 12, -1, -8, -5, 27, -21, 15, -22, -13, -7, -1, -15, -28, 9, 5, 2, -6, -16, -11, 0, -21, 17, -27, 5, -3, 25, 18, 28, 7, 5, -20, 11, 6, 3, -8, 9, -2, -15, -9, -19, -1, 2, -3, 9, 12, -6, -17, 15, -11, 10, -6, 13, -2, 0, 12, -8, -10, -16, 2, 17, -21, -13, 19, -18, -13, -17, 3, 11, -38, -9, 1, 9, 16, -16, 11, -2, 29, 5, 22, 4, -2, 2, -4, -9, 5, -1, 3, 9, 13, 11, 7, 12, 8, -26, -1, -18, -13, 6, 6, 16, 6, 9, -5, 18, 27, 7, 11, -12, 20, 8, -3, 25, 31, -17, 21, 56, -4, 9, 23, 24, 8, 0, 40, 11, 1, -1, -17, -2, 1, 11, 6, 3, -25, 6, 3, 13, -19, -19, -3, -15, 4, 13, -14, -18, -30, -14, 10, -8, -34, 18, 3, 6, 20, 0, 18, 26, 2, -8, 19, -9, 13, -13, 31, 5, 4, 10, -11, -8, 23, -16, -2, -6, -10, -3, -16, -6, 28, 16, 21, -19, 15, 22, 13, 3, 9, -15, -18, 28, -3, 3, 8, -22, 2, 15, -10, -22, 17, -17, -16, -14, -15, 13, -11, 22, 6, -9, 22, -13, 10, -20, 1, -22, -21, -9, 35, 7, -12, -3, -18, -32, 11, -26, 4, -2, 17, -18, 11, 14, -23, -18, -7, -7, -15, 6, -5, 14, 14, -29, -27, 7, 9, -13, -24, 7, 24, -18, 15, 15, -9, 12, 23, -5, -7, 14, -2, 12, -2, 0, 22, 2, 16, -11, 23, -28, -2, -2, -55, -3, -25, 5, -2, -14, -7, -1, 12, 16, -6, -10, -28, -14, -3, -19, 17, 22, 4, 19, 9, -16, -12, -2, 26, -1, 2, 5, -8, 11, -36, -13, 18, 5, -14, 3, -20, -18, -1, 24, 13, 8, 3, -10, -3, -24, 16, -6, 31, -17, -5, 4, -37, 4, -9, 18, -1, 19, 12, -1, -2, -14, -7, 8, -24, 21, -2, 14, -13, 16, 11, -21, -37, 36, -28, -21, 19, -7, 9, -1, -7, 12, -20, 10, -3, -17, -4, 15, 5, 21, -35, 40, 25, -8, 3, -8, 6, -21, 9, 12, 1, -19, 5, 16, -6, -25, 1, 13, -21, -8, 16, -16, -27, -2, -10, 10, -28, -14, -6, -28, -4, 5, -21, -7, 31, -4, 7, 11, -28, 28, -11, -5, -1, 3, 19, -10, -11, 11, 11, 13, 13, 2, -16, 12, 5, -15, -18, 20, -3, -10, -16, -7, 18, 2, -24, 34, -9, -16, 17, 1, -11, -1, -3, -9, 3, 0, 0, -19, -25, -10, 10, -6, -14, 4, 5, -14, -24, -7, -1, 6, -4, -21, -6, -1, 18, -6, -13, -4, 4, -5, -12, 19, -31, 4, -9, 1, 11, -20, -18, -4, -29, 22, -17, 5, -9, -5, 10, 2, -21, -10, -14, -9, -21, 14, -3, 17, -26, 36, -2, -22, 15, -14, 12, -12, -25, 11, -37, 7, 53, 1, 3, -20, 3, -18, -29, 44, 18, -5, -22, 18, -43, -22, 13, 24, -9, -15, 2, -8, -30, 7, 7, 23, -17, -16, 12, 1, -42, -22, -12, 4, 5, -5, -17, -4, -14, 5, -4, -8, 7, 6, -5, -3, -7, -6, -26, -12, 13, 5, -13, -19, -8, 2, 2, -3, -12, -4, -9, -15, -25, -4, 5, -3, 11, 7, -10, 15, -39, 7, -36, -7, -23, 11, -19, -9, -35, 5, -10, 16, -8, 3, 6, 2, -22, 14, -29, 40, -25, 13, -8, 18, -34, -13, -22, -6, 9, -19, 3, -1, 2, -8, 34, -1, 1, -3, -23, 8, -1, -6, -41, 29, -1, 17, -23, -7, -7, 2, 5, 5, 5, -20, -10, -14, -32, -15, -6, 11, 1, 1, 23, -18, 8, 6, -40, 18, 7, -11, -23, -24, -30, 32, 14, 10, -16, -16, -12, -12, -8, 5, -23, 4, 20, -16, -5, 6, -17, 2, -6, 5, -5, 9, 12, -13, 10, 7, 9, 14, -7, 22, -20, -20, 7, -9, -17, 35, 6, 4, -25, 13, 5, -4, -18, 13, -26, -1, -23, -8, -5, 16, -30, 31, 3, 15, 1, -13, -20, 26, 8, -20, 1, 7, -4, 0, -23, 27, -4, -9, -22, -17, -23, -26, -16, 15, 10, -8, -15, 3, -8, -14, -13, -18, 30, -30, -14, 6, 4, 11, -14, 25, -43, 31, -11, 8, -12, 18, -13, -10, 11, 5, -1, 11, -12, 20, 4, -4, -10, 15, 15, 4, -6, -12, -19, -6, 18, 11, -15, 12, -10, 12, -5, 8, 7, 18, -8, -16, 6, -13, -27, 6, 34, -2, -2, -12, 0, 15, -14, 2, 5, -13, 11, -2, 1, 0, -3, -24, -1, -1, 6, 8, -12, -19, -7, -1, 10, 3, -14, -8, -27, -15, 13, -15, 1, 1, 26, -8, -3, -17, -38, -2, -6, 13, 0, -10, -2, -8, 2, 11, 13, 22, 0, -3, -24, -6, -32, -8, 5, 7, -33, 2, -20, -7, -6, -2, -26, -2, 2, -7, -5, -21, 15, 11, -20, 7, 15, -11, 3, -15, 14, -32, -48, 25, 1, 11, -11, -19, 30, -45, -12, -15, -2, -10, 7, -17, 9, -24, 23, -4, 1, -2, -5, 0, 14, -8, -26, 5, -17, -21, 2, 15, -12, -8, -11, 19, 51, -10, -5, 5, 18, 7, 24, 5, 1, -20, 11, 11, 2, -16, -14, -17, 3, -13, -10, -9, 18, 15, -20, 4, -15, -16, 9, 5, 22, -24, -24, -44, 14, -2, -17, 14, 7, 2, -4, 9, -9, -5, 15, -3, 2, -45, -15, 6, -25, -14, 1, -18, -7, -8, -9, -17, 20, -22, -24, -16, -28, -17, 2, 15, 14, 2, 2, -20, 10, -10, 28, -6, -20, -14, -7, 2, 0, -24, 16, -5, -18, 13, 21, -9, -15, 33, -50, 21, 20, -4, 8, -4, -5, 3, 11, 2, -10, 8, 2, -18, -6, 0, -22, 26, 11, -25, 16, -12, -10, -9, -3, -2, 17, -14, -14, 4, -10, -18, -10, -14, 18, -15, 19, 18, -8, 19, -2, 24, 9, -20, 0, 2, 3, -19, 0, -12, 5, -14, 15, -14, -51, -1, -16, -18, 6, 18, 3, -22, 19, -4, 10, -17, 15, -3, -2, 8, -3, -18, -12, -7, 5, 10, 8, -7, 0, -18, -8, 17, 13, -23, -20, -12, -3, -13, 10, -9, 6, -9, 40, 0, 16, -9, -17, 7, -14, 10, 18, -10, 2, 20, -21, 9, -6, -21, -11, -17, -28, 1, 9, -5, -5, 9, -7, 14, 7, 20, -16, -20, 14, 4, 11, -8, -16, 8, 24, 22, -9, -9, -2, -23, 20, 35, -17, -3, 15, -5, 31, -19, 8, 5, -30, 52, -34, -10, -7, 8, -33, 0, -10, 6, 34, 6, -3, 2, 11, 14, -5, 29, 3, 12, 16, 11, 9, -27, -16, 21, 2, 2, -14, -7, 2, 28, -7, -3, 6, 10, 4, -10, -4, 3, 8, 13, 8, -7, -21, -17, -16, -9, -23, 40, 9, -12, -24, -18, -29, -8, -3, -8, -30, -24, 21, -6, 1, -14, 6, 6, -24, -20, -12, 4, 8, 3, 15, -5, 9, 17, 25, 2, -9, 0, 21, 2, 2, -6, -16, 7, -33, 6, 4, 0, -1, 5, -2, 9, 6, -23, -8, 14, -21, -5, 32, -21, -1, -16, -3, 3, 7, 17, -1, 10, -35, -29, 10, 22, -15, 17, 18, 18, -7, 26, -17, 4, 0, -21, 7, -6, -31, 0, -1, 1, 0, 19, -14, 13, 7, -3, 3, -9, -13, -10, -13, 3, -6, 3, 0, 3, -1, -3, -2, -3, -38, -4, -13, 14, -17, 0, -12, -24, 10, 13, -11, -6, -10, -16, -3, 5, 16, 24, -24, -32, 2, 1, 9, -11, -29, -26, -11, 23, -16, -6, 20, -20, -19, 8, -7, -1, 14, 15, 27, -11, -27, -40, -20, -43, 23, -22, -6, 14, -19, -7, -30, -20, -5, -14, 7, -19, -44, -16, -28, -13, -22, 3, 27, -15, 15, 15, -20, 1, -7, 2, 14, 18, 10, 19, -19, 22, -2, -16, 20, 16, -39, 14, -37, -9, 14, -2, 1, -25, 10, 22, -12, 12, -14, 0, -13, 16, -13, 9, -18, 23, -6, 15, 27, -1, -23, 10, -33, 20, 16, -11, -13, 1, -14, 15, -21, 3, -16, 17, 9, -11, 33, -11, 40, -4, -35, -24, 8, 17, -9, -22, -1, 25, 14, -12, -12, 7, -13, 3, -8, -4, 16, -18, 9, -6, 24, 1, -17, 11, 2, 17, -13, 16, -34, -16, -8, -15, -16, 3, 8, 7, -5, -9, -15, 4, 7, -19, -18, -23, -21, 10, -2, -21, 39, 15, 33, -21, 2, -8, -17, -22, -11, -1, -23, -6, -8, -14, 0, -6, 13, -14, -11, 14, -20, -17, -15, -6, -10, -7, 18, -4, 15, 12, 8, -13, 14, 5, 42, -10, -8, -19, -9, -25, -26, -9, 14, -17, -18, 20, 16, -28, -10, -16, -10, -15, 0, 24, -17, 36, 14, 8, 7, -15, -14, -2, 17, -6, 29, -12, -22, 14, -3, 4, -23, 8, -16, -16, -21, 14, -10, 17, 14, 23, 23, -20, -8, -2, 10, -15, -10, 12, 21, -19, 13, 0, -5, -12, -5, 10, 8, 6, -13, -3, 23, 5, -9, 17, 4, -11, -3, 13, 22, -9, 20, -29, 6, -6, -4, 17, -10, 18, 20, -18, -23, 3, 22, -12, 7, 1, -5, -30, 30, -23, 22, -4, 3, -6, 16, -17, -2, 16, 17, -18, -9, 6, 25, -30, 14, -4, -13, 13, 9, 12, 11, 0, 5, 8, 15, 10, 7, 13, -4, 10, -15, -20, -31, -11, 2, -2, -3, 16, -22, -1, -17, 4, -12, 2, 0, 14, -5, 13, 5, -22, 30, -26, 30, -14, -2, 12, 1, -20, -24, -16, -15, -2, -23, -5, 35, 21, 19, -15, -8, 2, -29, 16, 33, -20, -7, 21, 46, -15, -2, 1, 6, -12, -3, 13, -4, -4, 20, 12, -20, 10, -11, 9, 20, 4, -2, -17, 50, -17, -16, -23, 34, -22, 17, -6, -21, -9, 12, -16, 22, 28, 9, -14, 27, -20, -12, -6, 26, 8, -3, -7, -5, -16, 6, -32, 18, -22, 25, -21, -5, -9, 28, -2, 17, -8, -9, -10, -27, -14, -17, 12, -14, 1, -16, 14, -21, -9, 15, 10, 0, 15, 11, -12, 12, -12, -5, -26, 8, -31, 1, 17, -4, 13, -18, -11, 20, 15, -6, -20, -4, -18, 23, 13, 15, 20, -10, -1, -1, -3, -9, 8, -4, 1, 16, -18, -22, -11, 9, -24, -4, -25, 6, -11, 26, -11, -2, 10, 13, -5, -4, 14, 10, 5, 8, -16, 8, 16, 20, -19, -23, -16, 10, 13, -8, 10, 0, -13, -35, 17, 18, 17, -6, -13, -7, -13, -24, 2, 8, 5, 16, 18, 21, 11, 15, -10, -23, -6, 2, -31, -10, 17, -6, -21, 5, 10, -9, 1, 26, 5, -12, -19, -3, 16, 17, 13, 17, -11, -6, -25, 11, -11, 11, 2, 13, 18, 35, -14, -24, 12, 30, -10, 6, -24, 1, -9, -20, -14, -19, 7, 19, 2, -3, 19, 23, 15, 14, -21, 28, 7, -4, -19, -23, -32, 2, -23, 14, 5, 11, -20, -21, -2, 12, 17, 21, 3, -12, -4, 2, -16, -14, -30, 1, -23, 8, 3, 7, 33, 12, 17, 27, -8, -13, 15, -4, 0, 5, 13, 14, -10, -15, 8, -4, 8, 21, -25, 18, -3, -9, 15, -14, 3, -2, 2, -6, 12, -18, 9, 9, -11, 8, -26, 27, 2, 4, -6, 11, -10, 10, 15, -1, -18, 20, -9, -14, 10, 27, -16, 15, 2, -2, -4, 11, 18, -2, 17, 26, -22, -13, 13, -9, 9, 5, 21, -16, -18, 2, -11, -1, -21, -9, -24, 0, 13, 7, 10, 18, -4, -43, 4, 7, 2, 5, -10, 4, 14, 0, -3, -18, 0, 12, -22, 4, 27, -2, -3, 11, 21, 37, -9, 5, -3, 17, 4, 12, 17, -15, 12, 2, -6, -6, -20, -21, 5, 17, 9, -18, -7, 5, 13, 2, -3, 23, -21, -7, 15, 18, -3, -1, -11, -14, -16, -4, 4, 5, 15, 13, -13, 23, 17, 6, 1, -24, 2, 13, -9, -18, 15, -34, -24, -2, 23, -34, -11, 7, 1, -15, 25, 4, 16, -20, 12, -3, -12, -20, 2, -4, 3, 8, -4, 20, 13, -47, 6, 10, 0, -21, -18, 5, -11, -15, -4, 9, -7, 1, -14, 40, -2, 4, -1, -10, -3, 22, -6, -24, -26, -12, -32, -23, -6, -15, -14, -23, -3, -32, 17, 12, -11, -16, 5, -6, 12, 14, 10, -16, 16, -8, -1, 26, -20, -20, -8, -5, 0, -8, -10, -24, 12, 11, 15, -11, -8, 7, -8, -12, -24, -6, -3, -7, -9, -32, -12, 14, -21, -2, 1, 12, -3, -5, 16, 15, -17, -33, 12, -35, -18, -11, 7, -3, -7, -7, -9, -21, 5, 44, -2, 15, -12, -5, -3, 5, -4, -7, -15, 24, 13, -22, -7, -1, 0, 38, -5, -4, 16, -1, -23, 3, 21, -15, -14, -26, -6, 13, 4, 20, 23, 0, 11, -24, 2, 3, 3, 12, 8, -3, -19, 7, 10, 1, -3, -4, -1, -13, -17, 12, 12, 18, 7, 3, 17, 33, -21, 37, -22, 0, 26, 26, -44, 15, -14, -7, -7, 7, 17, -11, 2, -18, 1, 27, -18, -4, -35, 4, 11, 31, 13, -21, -2, -9, 33, 9, 6, 39, 3, -6, -17, 18, -20, -13, -2, 14, 18, 13, 18, 6, 2, -13, 1, 2, 2, -2, -11, 14, 8, 13, 19, 0, 7, -12, 12, 9, 12, 5, 2, -16, 13, 1, -15, -24, 25, 19, -13, -6, 4, 15, 5, 17, -14, 16, -9, 0, 17, -16, 19, 3, 9, 20, -9, -4, -21, 28, -10, -5, -5, 13, 1, -4, 9, 17, 3, 21, 3, -9, 10, -18, -5, -8, 3, -14, 3, -7, -1, 22, 18, -45, 7, -18, -23, -20, 6, 5, -9, 20, 6, 4, -19, 8, -11, -30, 11, 0, 17, 18, -1, 12, 12, 4, 5, -23, -14, 3, -13, -19, 15, 10, -7, 14, 14, -3, 13, -2, -22, 2, 9, 15, -21, -21, -13, 3, -38, 16, 16, -24, 15, 0, 9, 1, 14, -22, 19, 2, 9, -20, 0, 18, 15, 16, -22, 6, -4, 23, -22, 13, -9, 48, -12, -19, -10, 46, -37, 8, -2, 6, -13, -3, -19, 1, 9, 3, 8, -44, -16, -17, -5, -1, 4, 7, 6, -2, 14, 14, 3, 21, 19, 8, -10, 13, -22, -10, 8, 2, 30, 22, -12, 17, 5, 13, 2, 20, 9, -12, -19, -3, 7, -32, -11, 30, 14, -6, -4, -1, -13, -26, 17, -13, -5, -13, 38, -37, 12, 8, -12, -3, 6, -6, 7, -21, 4, 2, -1, 14, 5, -4, 14, 1, -1, 18, 17, -17, -27, -11, 12, -37, 17, -27, 12, -28, 4, 8, -9, -2, 6, -9, -4, 30, 0, -13, 9, -4, -20, -17, -12, -6, 13, 7, 6, -22, 16, 0, -20, -4, -3, -2, 17, 4, 10, -16, -11, 18, -4, -18, -8, 10, 12, 20, -10, 28, 5, 26, 16, -19, 11, -15, 21, 14, -6, -16, -2, -12, -4, -24, -1, -13, 10, 17, 14, -1, 4, -3, 9, 3, -10, -14, -5, 45, -8, -3, 14, 7, -23, 18, -14, -11, 7, -33, 3, 16, 14, -22, 17, 2, 12, -3, 15, 18, -17, 18, -21, 6, -3, -8, 12, -6, -19, 10, -20, 20, -15, -6, -3, 6, -26, -12, -9, 1, -8, 31, 14, 9, 5, -15, 0, -16, -16, -5, -8, 9, -5, -17, -13, -1, 14, 9, -20, 6, 7, -14, -18, -1, -2, -4, 21, 17, -13, 10, 9, -15, 21, 7, 4, 14, -14, 14, 1, 16, -1, 16, 9, 26, -9, -1, -4, -9, -2, -4, -7, 25, 12, 9, -4, 9, -8, -27, 13, 5, 28, -2, -29, -12, -12, 24, -6, 7, 21, 1, -19, 6, -23, -7, 4, 7, -23, -5, -3, 16, -10, -13, 19, 12, 18, 10, -3, -19, -14, -3, 12, 15, -11, 20, 2, -17, -9, -9, -9, 25, 2, 0, 7, -5, 5, 1, 5, 30, 3, -6, 15, -10, -1, -32, 22, 10, -3, 14, 15, 18, -22, 7, 3, 15, -15, -16, -22, -6, 16, 18, 18, 20, -4, 1, -20, -20, 13, 5, -4, 14, -8, 13, 4, 5, -8, 13, 4, -6, -23, 17, -14, 0, 17, -3, 14, -1, 3, -12, -6, -20, 3, -12, -19, 0, -15, 21, 10, -11, -11, 12, 18, 27, 4, 16, -1, 30, 6, -6, -15, -14, 0, 13, -4, -21, 15, 18, -7, 28, 13, -6, 14, -9, 8, 20, 20, 7, -11, -10, 15, -19, -19, 12, 0, 17, -10, -1, 2, -21, 14, 18, -14, 18, 12, -15, -7, -30, -21, 20, 0, 21, -21, -7, -10, 27, 2, 9, -13, -17, -27, 22, -1, -15, -11, -3, 17, -21, -44, -3, -11, -16, 7, 28, -2, 12, 0, 8, -4, -7, -25, 44, -19, 4, 18, -14, -13, 24, -1, 21, -10, 37, 31, -8, 0, -3, -6, 22, 15, 17, -6, 8, 1, 9, -8, 12, -17, 2, -14, -22, 11, -5, -8, 6, -21, -9, -22, -15, -12, 19, -5, -11, 16, 6, -13, 18, -21, 27, 3, -7, -2, -7, 26, -3, 1, 4, -5, -14, -19, 1, -9, 15, -5, 14, -3, 8, 17, -15, -32, 2, -2, 0, 10, 10, -1, 2, -16, -19, -3, 19, -17, -9, -15, -4, -9, 8, -15, -15, -11, 10, 14, 7, -5, 21, 1, 3, -10, -5, 8, 10, 18, -20, -8, 30, 16, -19, -7, -1, -17, 6, -12, -9, -10, -10, -7, 39, 7, -17, -27, 20, 11, -5, -5, 9, -23, -12, 8, -7, -22, 2, -7, 16, -14, 7, -7, 12, -17, 42, 23, 9, 6, 13, -3, 8, -16, 3, 33, -11, 5, -19, -4, 7, -24, 12, -11, 7, -35, 13, 7, -29, -28, -6, -16, -17, -36, -6, -31, 16, -20, 0, 3, 17, -16, -10, -19, -6, -10, 14, 26, 9, 14, -5, -14, 23, -24, 2, 11, 19, -25, -19, -7, 24, 22, -9, -3, 11, -15, 3, 2, 17, 21, -13, 11, -18, -12, -10, -9, -8, 12, 15, -3, -11, 4, 20, -29, 19, -8, -10, -12, 4, 3, -20, -23, -3, -33, 2, -22, 12, -27, 21, -25, -14, 29, 2, -20, 14, -17, -10, -15, -20, -13, 3, 15, -18, 4, -9, -32, -1, 4, 9, 3, 0, -7, -21, 9, 19, -28, -12, -20, -4, -16, -19, 14, -2, -13, 37, 2, 7, 13, -22, -15, 3, 28, 25, 7, -3, -22, 8, -9, 22, 33, 9, 2, -21, -1, -10, -11, 17, -7, 2, -10, -10, -6, -13, -28, 15, 16, -2, -2, -16, 7, 13, 10, 23, -17, -23, 2, 0, -19, 12, -35, 16, 5, -2, 4, -2, 5, -14, 10, 10, -6, 5, -21, 8, 19, -3, -14, 16, 4, 5, 12, -1, 1, -6, 17, 15, -20, 4, -14, 3, 9, 9, -27, -8, -20, 3, -42, 8, -5, -22, -14, -5, -36, -20, -8, 2, 7, 0, -1, 21, -2, 7, -5, -22, -11, -15, 16, 11, -12, -11, -18, 7, -3, -15, 14, 0, 9, 2, 25, -7, 23, 17, 23, -17, 9, -11, -8, 0, -7, 10, -31, 10, 35, -19, -24, 1, -11, 3, -20, 0, -22, 11, -27, -22, -7, -9, -23, 19, 28, -11, -16, 2, 3, -21, -28, 33, 8, 0, 4, 12, 22, -19, 16, 10, 20, -22, 15, -12, 16, -8, -7, 15, -14, 1, -1, 1, 16, 1, 7, -33, -37, -12, 2, 11, -35, -18, 10, 2, 25, -30, 9, -23, 11, 1, -14, 34, -7, 0, 2, -8, 7, 5, -18, 19, -14, -16, -8, 19, 4, 5, -17, 18, 16, -23, -15, -12, 10, -6, 5, -3, -10, -22, -20, -19, 22, -23, 6, -51, -16, 8, 14, -9, 0, 7, 12, 8, -20, 25, 15, -2, 17, -8, -7, -37, -42, -1, 5, 16, -25, -16, -12, 13, 33, 8, -34, -1, 30, 0, 3, -10, 8, 9, 1, -18, 22, -20, -7, -2, 2, 16, 24, 15, 21, 6, 2, 34, 5, 6, -2, 14, 21, 1, -14, -12, -8, -11, 3, -1, 2, 5, 6, 3, 4, -12, 28, -5, -6, -9, 7, 27, 21, -9, -11, 13, 34, -18, 19, -21, -20, 12, 15, -2, -11, -10, 9, -2, -3, 9, -8, 1, -29, -15, 6, -9, 0, 3, -32, -11, -8, 19, -13, -18, -9, -12, -37, 4, -24, -4, -43, 16, 4, -1, -26, -9, 23, -5, -3, 14, 24, -8, 33, 7, 13, 5, 11, 23, 27, -8, -3, -3, 2, -9, -8, -22, -4, -10, -14, 12, -9, -20, -7, -28, -29, 29, -11, 1, -64, -14, 17, 22, 11, -15, -17, -17, 21, -6, -20, -18, -20, 10, -19, 16, 13, -16, -5, 15, -3, 4, -57, -21, 11, -15, -64, -4, 11, -5, -13, 0, 25, 9, 16, 1, 23, -3, -14, -5, 10, 13, 3, -14, -26, -13, -1, 1, -8, 2, -26, 19, 19, 13, -25, -15, 0, -23, 17, -18, -21, -21, -15, -12, -13, -10, -33, 0, -18, -1, 26, 2, 8, -22, 5, -17, -27, -12, 4, 1, -39, -19, 12, -3, -7, -13, -5, -3, -3, -7, 20, -34, -28, 3, 13, -20, -7, 14, -17, 8, 3, 26, -26, -4, -4, -11, 4, -2, -38, -26, 6, 6, 0, -6, 19, -20, -28, -7, -1, 7, 3, -4, 0, -15, -16, -3, -10, 13, -9, -22, 4, 16, -6, -10, 16, -8, -27, 18, -21, -7, -27, -14, -7, 10, 13, 18, -15, 25, 16, -15, 10, -8, 8, -20, 31, -20, -28, -23, 21, -3, 10, -12, 6, 1, -29, -29, -20, -14, -28, 1, -31, -8, -23, 5, -15, 13, -24, -7, 1, 12, 5, 23, -15, 6, -11, -9, -25, 0, -17, 27, 8, 4, -18, -5, 7, -32, -20, -18, 25, 20, 19, -1, 9, -17, -2, 14, -25, -1, -27, -4, -10, 2, -4, 7, -9, -16, 5, -10, -15, -12, -1, 16, -30, -5, 17, 5, -13, -1, 16, 2, -24, 3, 14, 1, -20, -5, -10, 17, -8, 7, 6, 8, 21, 10, 5, -6, -29, -4, -11, 18, -20, 40, 12, -15, -18, 14, -37, 13, -9, -8, 7, -10, 15, -11, -6, -17, -24, 11, -16, -12, -24, -23, 8, 7, -41, 12, 13, -1, -2, -22, 26, -9, -25, -8, 9, -14, 1, 19, -14, 5, 2, 8, -9, -11, 6, 16, 0, -18, 30, -28, 7, 20, -3, -17, -28, -16, -11, -13, -17, -3, 4, -21, -29, -22, 5, 15, 10, -6, -7, -16, -11, 1, -10, -15, -2, -31, -26, -22, 14, 11, -43, 27, 26, -21, 7, 14, -14, 17, 19, 4, -24, -17, -3, -21, -21, 18, -5, -6, -5, -25, 0, 9, 14, -7, -2, -16, 24, -27, -7, 18, -17, 18, -14, -9, 1, -20, 43, 0, -14, 11, 31, -31, -19, 24, 6, 15, -24, 8, 17, 20, -22, -17, -15, -21, 19, -9, -7, -7, 13, -12, 28, 14, 4, -1, 2, 5, 0, -25, -10, 20, -6, -7, 14, 25, -13, -22, -21, -20, -20, -2, 18, 20, -15, -1, 5, 11, 2, -8, -11, -15, -2, -27, 1, -15, -5, 2, -18, -17, 4, -5, -11, -16, 24, -14, 14, -15, -14, 6, 5, -12, -12, -17, -1, 29, 0, -2, -8, -10, 0, -20, -25, 21, 21, 16, 12, 4, 3, 18, 4, -15, 0, -7, 39, -7, -9, -14, 37, -1, -21, 12, -3, 12, 19, 4, 8, 3, -32, -9, 7, 9, -5, -11, -11, -15, 19, -19, 12, -9, -1, -6, -10, 9, 18, -9, -25, 10, 21, -20, -27, -14, 13, -18, -14, 11, 24, -17, -24, 24, -2, 34, -21, 14, 22, -19, 0, -24, -19, -7, 6, -4, 34, -22, -15, -4, -2, 7, 18, 11, 0, -18, 8, -8, 24, -18, 18, 12, -8, 3, -16, -16, -11, -7, 5, -4, 3, 17, 29, 8, 7, 33, 20, 5, 17, -19, 9, 27, 9, 1, -31, 5, 11, -18, -7, -37, 7, -2, 14, -22, -23, -2, -2, -11, -23, -18, 7, -17, -11, -17, 13, 0, -20, -6, -3, 6, 10, -8, 13, 26, 11, -14, -14, -13, -2, -5, 8, 7, -8, -8, 5, -8, -21, -7, -5, 0, -3, -10, 4, -19, -32, 10, 0, 15, 15, -17, 18, -11, -12, -10, -6, 25, -56, -18, -27, -20, -53, 4, 22, 10, -18, 27, 1, 11, -10, -21, -20, 11, 16, 20, -15, -7, -8, 4, -38, 13, 8, 11, -6, 6, 16, 14, -28, 19, 14, -20, 1, 19, -21, -3, -3, -2, 13, -11, -49, -14, 4, 5, -19, 6, 2, -5, -13, 5, -27, -12, 2, 1, -2, 15, 23, -16, -6, -15, 32, -22, 18, -28, 5, 4, 11, 11, -30, -15, 19, 2, 11, -21, 7, 11, 17, -18, -6, 0, 4, 11, -14, -4, -39, -32, 4, -27, -7, -10, -15, -13, -3, 33, -9, -9, -18, 5, -23, 15, -12, -16, 4, -21, 7, -10, 0, -22, 3, 5, 7, -18, -21, -23, -13, -20, -7, 25, -10, 12, 11, 10, 8, -21, 17, -2, -5, 4, 8, -17, -23, 3, 8, 3, -10, -17, -35, -14, 21, 16, -6, -11, -5, 1, -3, 9, -8, 19, 6, 12, 11, 0, -20, 19, 15, 10, 6, 2, 13, 16, 14, -19, -3, 1, 7, -15, -23, -24, -23, -14, 6, -22, -5, 5, 7, -3, 16, -11, -19, 2, 26, 16, 0, -8, -27, -11, 4, -17, -10, 36, 10, -1, -27, -16, 26, -12, -39, 8, -23, 7, -12, 8, -25, -3, 10, 11, -31, 1, -6, -8, -26, -19, -14, -26, -26, -13, 9, 4, -32, 18, -12, -19, -18, -18, 1, -2, 5, -21, -18, 13, -5, -14, 16, -2, -24, 18, -9, -11, -4, -5, -11, 7, -23, -7, -2, 14, -13, -37, 5, -21, -16, -5, -8, 5, -5, 1, 4, -21, -2, -4, -2, 1, -27, -26, 0, -2, -29, 16, 5, 9, 16, -7, 26, -22, 8, 1, -32, -7, -18, -21, -16, -2, -13, 6, -19, 11, -8, 17, 0, -6, -9, -22, 7, 15, 11, -12, 0, -2, -38, 1, -13, -23, -1, 21, 8, -8, -20, -1, -6, 14, -4, 17, -34, 7, 19, 19, 9, 20, -16, -9, -23, -2, -25, 18, -8, -8, -10, 21, -24, -8, -13, -1, -19, 36, 1, 2, -19, 14, -13, 4, -12, -25, -19, -4, 10, 6, 16, -6, -33, 4, -3, -22, -8, 7, 18, -17, 4, 25, 24, 6, 3, -19, -17, 2, 2, -17, 19, 7, 3, 15, -7, -14, -23, 23, -18, -2, 13, -18, -27, -22, 15, 8, 22, 18, 17, -15, -4, 12, -4, -11, -14, 5, -4, 8, -29, -16, -3, -17, -18, 20, 25, -13, 10, 11, -15, 22, -2, -24, 1, -11, -31, 0, 6, -2, 12, 16, -15, 17, -4, 11, -19, 18, -16, 26, 11, -13, -20, 11, -19, 15, -7, 8, -8, 17, -8, -21, -19, -7, -24, -25, -19, 17, 10, -17, 20, -6, -8, 54, 23, -4, -23, 9, -4, 5, 8, 34, 0, -9, 9, 13, 26, -3, -14, -12, -25, 1, -8, -19, -27, -23, 13, 11, -4, -20, 1, -8, 9, 25, 30, -1, -5, -9, 28, 19, 8, -20, 15, -17, 13, 13, -4, 4, 2, 19, -17, -7, -4, -12, -1, 4, -15, 19, -6, 10, 21, 12, -7, -9, -2, 11, 3, -6, -25, 4, 14, -16, -15, 1, -1, 14, 24, 12, -1, -17, 25, -3, -9, -14, -25, -8, -5, -16, 15, -8, 7, 16, -10, 11, -11, -16, -24, -10, -11, 1, -12, 18, 5, -10, -26, 18, 20, -14, 22, 14, -22, -2, 34, 23, 25, -15, -10, -17, 15, -9, 9, -7, -5, 0, -14, 1, 6, -11, 9, 15, 6, -11, 2, 19, -17, -2, 16, -2, -19, -9, 18, -5, -1, -23, -9, 24, -11, 10, -10, -7, 12, -6, -1, -17, 10, -12, 4, -12, -4, 6, -12, 9, -5, 15, 9, -22, -10, 0, -15, 13, -7, 43, 14, -2, 1, 11, 19, 7, -7, 16, -11, 7, -5, 6, 17, 20, -2, -1, -3, 13, 2, -21, 20, 16, -6, 40, 33, 13, -9, -14, 10, 33, 19, -38, -27, -11, -3, -17, 12, 10, -10, -2, 7, 15, -8, 8, -13, 31, -8, 5, 17, 11, 13, 7, 15, -7, -22, 16, 2, 14, 10, -21, -5, 14, 25, -1, 1, -1, -15, -16, 31, 0, -15, -36, 4, 16, 14, 16, 10, -19, -5, -11, 8, -11, -12, -10, -19, -8, -20, 11, 24, 9, 17, -17, 11, 0, 26, -12, -21, 13, 15, -13, 8, 23, -9, -28, -19, -11, -20, -1, -9, -8, -11, 14, 20, -8, -20, -6, 24, 7, -31, 32, 7, -11, -8, -3, 3, -6, 4, -9, 0, -15, -4, 11, 26, -14, -13, -24, -17, 7, -10, 2, -4, -20, 9, 18, 26, 12, -9, -15, 25, 6, -25, -25, -29, 18, -10, -12, -10, -3, -15, -10, -17, -21, 9, -20, -12, -29, 2, -21, 3, 14, 8, -12, 21, -15, 4, -20, -16, -5, -16, 13, -12, 25, 22, -4, 3, 19, -7, -1, -13, -8, 7, -15, -6, 1, -9, 6, -16, 10, -18, -4, -14, 0, 4, 10, -20, 21, 35, 26, 11, -11, 4, -15, 2, 32, -9, 14, -33, -22, -27, -12, -25, -13, 7, 30, 1, 3, -15, -19, 20, -14, 7, 13, -27, 17, 19, 14, -11, -25, -14, 18, -17, -2, 10, -5, -18, -15, -7, -6, 17, -19, -34, 2, 4, 24, 4, 37, -10, -22, 14, 16, 20, 24, 9, 3, 10, -10, -11, -4, -2, 9, 12, -7, -6, 8, -18, 2, -17, 14, 15, 28, 7, -13, -16, 0, 1, -13, 7, -17, 9, 11, -5, 18, -25, 15, 7, 13, -14, -6, 10, -14, 10, 14, -12, -19, -3, 9, 6, -23, -24, 24, 14, 16, 9, -7, -22, 19, -22, -3, 12, -10, 8, 12, -4, -12, -27, -16, -19, 0, -11, 5, -13, -19, 0, 4, -7, 5, -2, -13, -36, 11, 23, -3, -4, -1, -21, -5, 9, -9, 0, 5, -7, -6, 3, -15, -12, 10, -17, -22, -19, -27, -10, 19, -26, 10, 0, -2, -22, 17, 6, -8, -42, -20, -9, -23, -10, 23, -15, 14, 18, 0, 11, -3, -21, -12, -12, 1, -4, -18, -12, 4, 10, -14, -7, 10, -11, 2, -9, 7, 10, 21, 9, -7, 27, -21, -27, -20, -16, 11, -1, 8, -11, 7, -14, -10, -9, 18, -14, 11, -14, 7, 13, -6, -4, 15, -33, 14, -42, -7, -27, 31, 12, 3, -24, -1, -8, -16, -2, 10, -1, -15, -6, 14, -26, -18, -15, -12, -8, -25, -17, -12, 14, 12, -1, 13, -23, 9, 4, -11, -30, 18, -9, -12, -4, 3, 11, -8, 3, 2, -37, 3, -26, -27, 21, -5, -32, -21, 21, 0, -4, -9, 17, -20, 13, -3, 3, -23, -11, 4, 11, -9, -14, 1, -25, 4, -1, -20, 1, -22, -28, -20, -28, -18, -9, 25, -24, 5, 7, 5, -41, -8, 25, -1, -18, -16, 9, 5, -11, 5, 2, 13, -13, -13, -27, -19, -25, 24, 1, -18, 2, -7, 1, -11, -8, -1, 3, -11, -3, -19, 18, -8, 16, 4, 26, -34, -16, 5, 15, -5, -17, -7, 28, 7, -10, 8, 23, -8, -14, -6, 26, 1, -8, 6, 0, 9, 17, 39, -31, 42, 29, 11, -11, -22, 22, -11, 11, -25, 3, 9, 29, 8, -14, 27, 42, -17, -13, -13, -3, 9, 16, -49, -62, 24, 19, -10, -34, 11, 3, 11, -2, -14, -29, 16, 3, -19, 14, 46, 18, -2, 0, 6, 22, -17, -12, -5, 12, -1, 1, 12, 3, -10, 1, -2, 11, 1, -7, 9, 17, -11, 15, -19, -24, -1, 29, 7, 17, -16, -10, -5, 0, -11, 2, -12, 10, 3, 25, -12, -35, 16, 19, 15, -22, -5, -4, 31, 7, -5, -1, 3, -3, 10, -14, 16, 23, -4, -36, 13, 26, 19, -10, -9, 4, -33, -25, 3, 17, -1, 4, 32, -1, -33, 9, -21, 5, 7, -21, 15, -4, 5, -15, 11, 7, -12, 14, 14, 22, 8, -8, -13, -13, -13, 9, -13, -36, 8, 3, -17, -6, -20, 25, -27, -33, 14, 6, 16, 22, -15, -3, 9, 9, 24, 20, -13, 16, 18, 13, -3, -17, 11, -7, 19, -2, -6, 29, 23, 46, -2, -3, -19, 23, -13, 24, 9, -10, 5, 24, 15, -13, 4, -7, 55, -1, 13, 25, -12, 1, 14, -10, -16, 30, -5, 20, -4, 21, 14, -11, -21, 7, -53, -18, -7, 36, -2, 9, 36, 0, -12, 13, 13, 8, 13, -14, 1, -49, 16, 45, 11, 40, -8, 6, 8, 3, -15, -6, -18, -7, 11, 6, 16, 2, 0, 10, 0, 0, -3, 40, 31, 18, -32, 1, 6, -3, -19, 33, 24, 9, -1, 7, -19, 23, 19, 8, 7, 30, 11, -7, 14, 9, 6, 18, -18, 9, 15, 14, 5, -2, -3, 3, 15, 2, 33, 7, 17, 23, 5, 31, -16, 8, 2, -6, -1, 5, 6, -6, 13, 21, -10, 22, 14, 9, 6, -13, 8, 19, 19, 20, -13, -2, 10, 2, 31, 27, -6, 28, 14, -3, -13, 36, -5, -11, -15, -7, 8, 9, 8, -1, 9, 17, -11, -15, -5, 18, -17, 4, 5, -14, 16, 7, -14, 5, 11, 31, 22, 3, 4, 24, -21, 4, 19, 15, 39, 0, 18, 41, 2, 6, -8, 13, -15, 11, 11, 30, 13, -2, -23, 1, 47, 39, 6, 16, 19, 3, 1, 8, -5, 3, 19, 9, 8, 5, 14, -9, 16, -15, 2, 15, 5, -29, -1, -4, 8, 12, -1, 14, -18, 9, -2, 0, 34, 10, -16, -3, -10, -16, 9, -4, -5, 7, 0, -12, -10, 13, -21, -11, -12, -19, -7, 9, 10, -6, 4, 21, -12, 15, -19, -12, 8, -17, -14, 8, 18, -18, -3, 24, 14, -6, -7, 13, 9, 0, 27, 17, -6, 25, 12, 9, -38, -17, 11, -8, 4, 21, 0, -10, -16, 15, 2, -18, -5, 8, 11, -26, -5, -6, 5, 0, 0, 11, 2, -14, 28, 11, 35, -1, 14, 16, -4, 19, 2, -3, -26, -6, 15, -5, -16, 13, 16, 25, -10, -17, -7, 1, -6, 4, 19, -6, 39, 26, -4, 14, -17, 16, 13, 23, 44, 33, 13, 20, 18, 33, -2, 15, -2, -1, 3, 17, 3, -25, 29, 0, 8, 16, 4, 31, -5, -23, 4, -18, 21, 23, 0, -1, 3, 13, 3, 40, 31, 19, -22, 17, -22, 15, 24, 16, 32, 20, -11, -29, -2, 21, 33, 16, 23, 15, 12, -4, -11, 46, -18, 15, -4, 4, -13, 56, 8, -4, 19, -1, 2, 0, 15, -22, 12, -10, 28, 37, 14, 20, 10, 1, 18, -10, 7, -4, 1, -4, -9, 14, -9, -12, 7, -17, 18, 10, 7, 20, 20, -31, 25, 12, -5, -18, 11, 25, -21, -28, 7, -10, 34, -20, -21, -15, 14, -9, 21, -6, -7, 0, 9, -19, -15, 31, 7, 15, 25, 24, -10, -11, -9, 15, 29, 17, 12, 11, -16, -32, -12, -24, -17, 21, -6, -1, -16, -18, 16, 1, -33, -12, -19, -12, -17, 22, -5, -30, 10, -12, 17, 6, 8, -7, -16, 1, 19, 9, 1, -12, 19, -16, 14, -13, 24, 18, -6, -2, 8, 15, -14, -17, 7, 32, -3, -16, 19, -7, -6, 4, 3, -5, 19, 13, -1, -25, 14, -10, -10, 13, 14, -15, 2, -10, -18, 25, 31, 13, 6, 3, 19, -29, -3, -35, 14, -2, 15, -20, 18, 0, -5, -6, 29, 25, 10, -14, -18, -15, 5, 3, 17, 12, 16, 5, -16, 41, 7, -11, -19, 5, -7, 22, -1, -2, -13, -10, 13, -19, 5, 9, -16, -18, -8, -13, -20, 25, -9, -8, 13, -8, -10, -3, 30, -11, -20, 2, -13, -10, -15, -17, -11, -20, 17, -9, -21, 2, 10, 3, 1, -23, 38, -4, -34, -11, 10, 17, 16, -6, -15, 5, -14, 4, 0, -18, -3, -16, 9, 0, 19, 2, -17, 2, -34, -5, 2, 4, 6, -17, -28, -8, 0, 5, -29, 10, -4, -20, -21, 8, -5, 12, -10, 10, -22, -1, -22, 28, 12, -17, 16, -21, -7, -2, 9, 14, 7, -2, -14, 2, 11, -17, -25, -19, -7, -12, -14, 8, -14, 19, 1, -1, -11, 10, -4, 15, 5, -12, -3, -13, -25, -2, -11, -14, -10, -2, -14, -3, -8, -3, 2, 16, -15, -26, -12, 23, 12, -1, -6, -14, -23, 2, -13, 12, 20, 18, 12, -4, -18, -34, -5, 15, -14, 19, -2, -9, 12, -4, -36, -13, -4, 7, 30, 4, 39, 3, -18, 10, 6, 19, 16, -2, -25, 9, 0, -9, -13, 6, 5, -13, -39, 5, -20, 0, 27, -22, 4, 13, -7, -15, -21, -18, 4, -5, 2, 16, -28, -4, -30, -5, -12, 9, -16, -18, -6, 7, -22, 12, 13, -13, 12, -4, -14, 12, -6, 17, 43, -16, -25, -7, 4, 7, -10, -21, 16, -4, -5, -4, -11, 5, -15, 2, 8, -10, 5, -10, -7, 9, 20, 3, -2, -14, -23, 11, 10, -5, -6, 13, 18, 14, 11, -23, 25, -7, 19, 6, -2, -7, 11, -9, 10, 9, 8, 8, 1, 11, 1, -1, -1, -15, 9, 3, -15, -15, 1, 11, 17, -2, 24, 22, 17, -13, -17, 6, -4, 9, -9, 19, -22, -8, 0, 3, 7, -5, 23, -31, 20, -19, -16, 27, -8, -1, 14, 6, -23, 8, 11, 22, 18, -8, 4, -19, -9, -5, -20, 7, -19, 6, -6, -28, 1, 21, 8, -11, 3, -3, -8, 11, 10, 0, -16, -15, 17, 10, -8, -1, -21, -15, -4, -16, -24, 0, -17, 17, -22, -16, -18, -13, 33, -43, 37, -10, 2, 5, -29, -5, -13, -2, -4, 33, 7, 8, 6, 7, -11, 14, 11, -11, -5, -16, 2, -6, -14, -9, 19, -16, 28, 8, -10, -13, -26, 4, 26, -11, 8, 7, 9, 10, -2, 6, 4, -11, -36, -15, -11, -1, 21, 36, 15, 15, -4, -18, 9, -10, 25, -8, 23, -2, -1, -12, -32, -9, 9, 40, -5, 14, 16, 18, -21, -7, -11, 4, -1, -8, -8, 13, -9, -8, 16, -16, 25, -20, 13, -1, -1, -8, -12, -2, -2, -17, 19, 5, -31, -8, -8, 2, -13, 3, -17, -17, 6, -9, 5, -48, 19, 4, 40, -27, 7, -6, 11, -23, 7, -7, 26, -13, 23, -7, -4, -24, 8, -23, 3, -23, 19, 19, 31, 30, -18, 9, -5, 6, -34, -6, 10, 3, -7, 8, 19, -16, -13, -13, 8, 1, -17, 8, -7, -3, -23, 13, 34, 3, -2, -31, -3, -19, 18, -11, -1, 7, 34, -24, 29, 14, 4, -10, 13, 6, -17, -12, -3, -6, -13, -15, 14, -7, -3, 12, 9, -5, -33, -8, 27, -2, 2, 7, -22, 14, -19, -22, 31, 7, -2, 9, -1, -10, 14, -22, -10, -22, 21, 3, -5, 2, -15, -1, 8, 3, 8, -9, 0, -13, 8, 17, 12, 0, -10, -27, -14, -16, -21, 18, -2, -7, -10, -12, -14, -11, -12, -6, 6, 18, 4, -5, -20, -14, 0, 7, -19, 3, 9, 7, -7, -21, 25, -11, -11, -12, 12, -13, -31, -21, -3, -18, 20, 36, -34, 16, -15, 5, -17, -11, 10, 16, 18, 25, 4, 20, 17, 14, 6, 12, 6, -18, -14, 0, 8, -27, 10, -13, -18, -12, -1, -3, -11, 5, 10, 18, 2, -6, -25, 6, -16, 16, 17, 42, 38, -23, -25, 1, 4, -9, -4, -5, -26, 4, -1, 4, 14, -13, -26, -25, 17, -27, 3, -1, -13, 12, -12, 52, 14, -16, 0, -9, 9, 5, 2, 20, -4, -2, -21, 17, -22, 8, -9, -14, 2, -26, -3, -6, -4, -15, -2, 26, -3, 7, -9, -1, 20, 5, 12, -23, -9, -2, -3, -11, -3, 14, 30, 24, 14, -9, -38, 14, 0, -6, 14, -4, 6, 6, -18, 4, -16, -6, -2, 7, 28, 12, -24, 9, 8, -8, -17, 23, 26, -13, -1, -3, -30, -7, -15, 12, -3, -45, -2, -8, -14, -10, -1, 11, 18, 6, -14, 1, 4, -18, 1, 1, -29, -22, -1, -5, -26, -4, 1, -21, 12, 7, -1, 14, 4, 22, 1, -7, 28, 33, -45, -6, -7, -1, 11, -31, -14, 10, -5, -20, 3, 19, -22, -13, 11, 20, 34, 14, 16, 4, 0, 7, 21, -8, 6, 5, -41, 15, -30, 7, -5, -9, 17, 9, 0, -12, 20, -18, -11, 5, -1, -7, -6, -25, -20, -6, -18, 9, -34, -7, -27, -19, -35, -22, -11, -8, 69, 15, 1, -21, 34, 40, 1, 27, -23, -17, 38, 15, 7, -14, -1, 20, -7, 1, -6, -7, -17, -13, -15, -10, -15, 5, -11, 6, 15, -2, 19, 6, -3, -14, -2, 19, 8, -16, -24, -22, -12, 7, -16, 13, 3, -23, -5, 5, -28, 2, -5, -15, 1, -18, -20, -26, 19, 17, -24, 5, -30, 9, 7, 22, 5, 12, -15, -3, -6, -15, -21, -10, -6, 8, -33, -12, -27, -23, -10, 17, -3, -4, 16, 15, -42, 27, -19, 22, -18, 2, -8, 5, 8, -2, 1, -5, -30, -23, 35, 20, -16, 2, 11, 26, -17, 17, -22, -3, -3, -15, -5, 3, 25, -11, 14, -10, 17, -22, -11, -14, 24, -7, 1, 10, -12, 1, -5, -6, 9, 2, -29, 7, -31, 31, -7, -25, 10, 10, -32, -16, -22, -35, -2, 7, -6, -25, -24, -2, -3, 4, 1, 1, 14, -9, -15, -21, 2, 10, -14, -7, 6, -21, 5, -1, 32, -8, 6, 13, -13, -5, -13, -19, 19, -10, -10, 9, -8, 10, -9, 10, 13, -19, -13, 25, -22, -9, 4, 22, -17, -25, 0, -21, -7, -6, -23, -24, -23, 19, -2, 26, 22, -17, 29, 19, 1, 24, 11, -12, 0, -18, -6, -11, -15, 12, -6, 6, -5, -7, 17, -17, 23, 11, 12, 8, 26, 0, 9, 11, 20, 26, -2, -3, -10, 3, 20, 3, 26, -2, 0, 11, -11, -1, -23, 9, -16, -19, 7, 17, -6, 11, -5, -8, -32, 0, 9, 7, -10, 17, 0, -16, 0, -1, -5, -8, -1, 3, -25, -4, 12, -20, 2, -4, -33, -23, -17, -13, -28, 21, -14, -2, -19, -8, -22, -4, 2, 33, 22, 18, 6, -25, 24, 12, -19, -4, -27, 19, -16, 11, 2, -13, 9, 1, -16, -7, -12, -7, 17, -12, -1, -18, 19, 20, 1, -15, -22, -1, 10, 13, -20, 14, 4, 1, -14, -18, 25, 4, -6, -5, -19, -9, -22, 13, -22, 10, 11, 2, 8, -7, 21, 16, -4, 0, 16, 9, 13, -4, -1, -18, -3, -10, -20, -2, 10, -25, -6, -4, 23, 2, -6, -24, 0, -27, -2, -8, -8, 5, -15, -18, 13, 9, -26, -1, -11, 5, 11, 44, 6, 5, 12, 10, -34, 15, -1, 13, -4, -13, -9, -8, 35, 16, -17, -2, -14, 16, 13, -32, 3, -9, -9, 5, 13, -7, 14, 7, -22, 29, -11, 6, -13, 20, -2, -10, 1, 2, 9, 2, -25, 11, 13, 25, -12, 20, -50, 15, -11, 14, -13, 0, -22, -27, -21, 27, -16, -10, 21, 10, -25, 13, -26, 1, 9, 5, 6, -3, 4, 17, -9, -1, 3, -17, 10, -9, 11, -4, 0, 7, 6, 23, -3, 1, -10, 24, -6, -21, 2, 17, -3, 19, 5, -4, -32, -29, -9, 15, 12, 18, 4, 40, -8, -10, -2, 13, 24, -12, -20, 19, -13, 8, 17, -1, 17, -4, -14, -18, -11, 4, 8, 23, -23, 11, 25, 6, -14, -7, -2, 17, 4, -10, -17, -3, 24, 11, -5, 3, -16, -11, -13, -4, 15, 45, 6, 12, -23, 6, -4, -20, 11, -21, 6, -11, 25, -19, -6, -7, 12, -8, -4, -7, -14, 18, -19, -19, -3, 19, -2, 14, 17, 19, -19, 3, -16, 14, -3, 1, -11, -18, -21, 4, -7, 16, 1, 12, 10, 18, -3, -37, 13, 10, -4, 16, -5, -3, 0, 1, 8, 0, -3, -6, -16, 0, 42, 3, -15, -33, 0, 10, -20, 3, -30, -20, -27, 20, 3, -19, -26, 8, 28, 3, -31, 5, -2, 16, -14, -20, 16, -5, 5, -12, -6, 16, 28, 27, 18, 24, 29, -1, -13, -20, -19, -21, -20, 29, 22, 10, -5, 10, 5, -8, 26, 29, -24, -20, -13, -9, 17, -24, 6, -29, 27, 16, -24, -1, 12, 5, -16, -20, -18, -1, 20, 0, 0, 4, 7, -14, 32, 22, -16, 13, -2, 20, -6, 13, -4, -19, 3, -12, -4, -12, 17, 14, 1, -22, -3, -17, 8, -19, 6, -20, -17, 25, 16, 12, -12, -6, -16, -33, -7, 7, 23, 16, -5, 11, -23, -24, -17, -9, -11, 28, -2, 2, -8, 0, -18, -23, 7, 17, -1, -12, -2, -8, 10, -2, 0, -20, 11, -13, 17, -21, -11, 19, 20, -11, 5, -5, 4, 10, 17, -9, -19, -7, -2, 19, -9, 7, -4, -13, 17, 12, 3, -14, 24, -5, -7, -22, 14, -17, 22, 11, 13, 36, 49, 37, -17, 4, -5, -13, 30, 11, 0, 15, 34, 3, -20, 5, 5, -6, -14, -10, 0, -5, -20, -12, 21, -9, 21, 3, 14, 8, 12, 17, 4, 22, 46, 41, -11, 11, 23, -1, -15, -22, 37, -12, -14, -19, -11, -6, -34, -9, -9, -5, 1, 4, -34, 15, -25, 1, 6, 12, 22, 10, 7, -9, 2, 15, -37, -30, 5, -5, 21, -6, -22, -38, -9, -10, 20, 18, -5, 7, 23, 29, -9, -14, -24, -3, -15, -1, 19, 11, 14, 20, 28, -16, -17, -22, 24, -4, -7, 12, -31, -28, -2, 0, -2, 2, 58, 42, 17, 4, 8, 4, -13, -26, -33, -39, -3, 15, -4, -23, -1, -25, 39, 6, -8, 8, -2, -6, 5, 1, 8, 22, 7, -24, 0, 4, 15, 24, 12, 16, -6, -5, 10, 5, 22, 37, -7, 14, 14, 0, 25, -3, 18, -19, -6, -32, -18, 5, 14, 3, 17, 2, -26, -40, 18, -22, -7, 1, 10, -41, 4, -5, 13, -27, 11, 3, -6, -13, 23, 21, 0, 19, -7, -5, 3, 3, 1, -8, 10, 15, 16, 2, 18, 9, -14, 16, -16, -2, -4, -25, 2, -3, 38, 11, 23, 3, -15, -18, 14, 11, -5, 8, -20, 4, 10, -8, 10, 13, -18, 1, -13, 4, 1, -2, 10, 8, 48, 55, -5, -2, -2, 19, 45, 35, -26, 8, -3, -6, 2, -18, 7, -1, 22, 47, -9, 9, -16, -22, 50, 15, 17, 8, -1, -18, -1, -22, -5, -1, 10, -2, 16, 10, -4, -6, 6, 12, 21, -10, -10, -9, -15, 9, 18, -22, 10, -28, -18, 8, 22, 12, -4, -18, 9, 0, 6, -29, -15, -5, 15, -9, -4, -8, 16, 0, 4, 3, 16, -14, 8, -4, -3, 25, -26, 6, 4, 6, 12, 17, 20, 6, 5, 9, 26, -1, 11, -8, 23, 1, 31, -9, -19, -24, 10, 1, 1, -20, -24, -14, 32, -1, -8, -9, 7, -2, 17, -15, 18, 14, -8, -12, 31, 9, 10, 11, 6, -33, -16, 10, 0, -19, 3, 20, 32, -9, -7, 4, 19, -6, -10, -4, -3, 0, 1, 6, -17, 9, -16, -4, 5, -7, -15, -19, 8, 9, 9, 12, -16, -2, 10, -1, -8, 6, -13, -12, -2, -1, -19, 15, 0, -16, -20, 11, -9, 7, 22, 11, -1, 16, 21, -11, -8, 9, 25, 18, 17, 31, -1, -31, -10, 18, -2, -8, 0, 3, -5, 1, 0, -23, 20, 16, 3, -15, 3, -17, 11, 2, 40, -1, -9, -12, 2, 7, -15, 18, -5, -4, -26, -12, 35, 2, 12, 9, 27, 1, -28, -3, -12, -9, -20, 22, 14, -1, -2, -5, 7, -19, -1, 22, 8, 27, -14, -20, 5, -15, -4, 9, -8, 8, 23, -10, 4, -22, 16, -23, 8, -5, -17, 0, -18, 12, -9, -12, -6, -20, -20, -18, -3, -3, 12, 27, 15, 23, 15, 12, 10, 13, -19, 5, 40, 6, 18, -26, -3, -6, -4, -12, -10, -18, -5, 6, 21, -2, 16, -3, 10, 18, 9, -23, -15, -3, 25, 13, -21, 8, -11, 3, 0, -27, -26, 12, -16, -9, -9, 18, 18, -8, -13, -6, -3, 28, -18, -25, -2, -13, -3, 30, 27, 15, -8, 11, 9, -17, 10, -6, 5, -18, 6, 16, -13, 21, -2, 10, -36, -21, 7, 7, -6, 22, 4, -16, 15, 16, -21, -20, 1, -10, -2, 3, 19, 1, -13, 12, -12, 23, 5, -11, 15, 19, 27, 19, -3, -12, 11, 13, -19, 2, -17, 13, 3, -3, -17, -18, 8, 13, 1, 19, 17, 7, -14, -6, 18, -3, 10, -2, 17, 4, -27, -9, 6, 1, -13, 0, 13, -13, -13, -25, -2, -2, -1, 5, 4, -7, 9, 1, -23, -8, 18, 23, -10, 7, 32, 9, -35, -7, -20, 3, -15, -18, -9, -29, -43, -5, -19, -10, -3, 11, 2, -6, 9, -15, 1, 16, 3, -27, 5, -22, -2, -5, -25, -3, 21, -7, -16, 23, -9, -40, 1, 8, 23, -12, 15, 20, -19, 14, 6, -16, -24, 5, -28, -7, -4, -25, -5, 6, 4, 18, -8, -11, -28, -31, -6, -4, -14, 1, 5, -6, -13, -33, 3, -8, -35, 12, 7, 31, -6, 26, -2, 19, -22, 4, 32, 7, -4, -13, 23, -11, -8, 12, 33, 10, 4, -24, -18, 8, 13, -1, -3, 17, -1, -35, 21, 19, -20, -17, 7, -31, -13, -24, -1, 0, -9, 2, 0, 1, -14, 9, -15, 14, -1, 6, 21, 9, -23, -1, -8, 14, -3, -17, 28, -17, 58, 45, -16, 20, -11, 0, 2, 5, 2, 9, -12, 3, 0, -19, 25, 21, 16, 5, 14, 3, -7, -16, -4, -13, -8, 37, 9, -5, -18, -15, 30, 17, 1, -22, -22, -5, -26, -11, 6, 55, -23, 24, 12, 12, 27, 20, 16, -21, -7, -11, 15, -12, 2, -17, -27, -11, -1, -16, 29, -2, 17, 9, -13, -20, -13, -7, 2, -13, 12, -18, 27, 1, 3, -3, 27, 21, -15, -3, -24, -3, 10, -6, -8, -17, -7, -18, -4, 18, -15, -4, -11, -17, 1, -7, 13, 29, 17, -23, -8, 8, 0, -17, -2, -3, -15, 0, 32, -20, -10, -15, 31, -14, -12, -9, 24, 25, -9, -8, 32, 5, 13, -18, -31, 19, 19, 19, -17, -8, 20, 24, 20, -13, 6, 13, 3, -32, -2, -12, 5, -22, 15, 1, -20, -33, 12, 7, 7, -22, 1, -6, 20, 21, 27, 52, -8, 0, -11, -6, 11, -12, -1, 14, 14, 9, 2, -6, -12, 0, 10, 1, 19, 7, 8, 11, -8, -10, 7, 11, 10, 6, -24, 18, 27, 26, -15, 22, -27, -16, -12, 10, 5, 29, 7, 23, -7, 18, -4, -19, 2, 1, -13, 2, 28, -21, -14, -28, -8, 22, -10, 10, 26, -24, -24, -9, 17, 7, -6, 32, 8, -8, 15, 3, 10, 25, -24, -14, -5, 16, -21, 3, 18, 16, 9, 42, 3, 11, -7, 5, 14, 16, -4, -4, -4, -20, -15, -22, -3, 0, -17, -16, -38, -2, -3, 9, 2, 20, -5, 22, 21, 1, -16, -28, 3, -15, 18, 10, -25, 26, -16, 1, 14, 47, 15, 6, -4, -14, 7, -5, -17, -13, -11, -9, 15, 23, -24, -2, 16, -12, 35, 1, 13, -2, -20, 0, 28, 29, 25, 4, 8, 7, -54, -17, 17, 5, 21, 61, -5, -16, -9, -14, 6, 1, 11, -11, -9, 13, 3, 7, 10, 28, -20, -13, -17, 10, -3, 14, -24, -12, -20, 23, 14, 9, 4, 3, 37, 14, 2, -3, 27, -16, 36, 24, 32, 44, -14, 9, -16, -13, -21, -20, -6, -17, -11, 30, 22, -12, 8, 14, 17, 17, -17, -1, 0, 10, 24, -9, 20, -19, -8, 3, 10, 9, 4, -3, 19, -11, -16, 14, 8, -21, -3, 26, -11, 3, -11, 12, -12, 1, 9, 9, -2, 3, 23, 18, -14, 0, 13, -11, 12, 38, 3, 12, 3, -26, -1, -2, -10, -12, -26, -11, 4, 6, -21, 16, -1, -19, 5, -10, -15, 8, 12, -13, 16, -25, 13, 15, 6, -6, -12, 0, 18, 7, 8, -4, -26, 12, 3, -4, -3, 7, 14, -32, -40, -18, 20, -22, 3, 16, 0, -9, -5, -16, 13, 4, 6, 3, 16, -11, 12, -23, 11, -14, -6, 24, 7, 17, -14, 4, -19, -13, -17, 8, 4, 11, -20, 2, 33, 9, 6, -5, 6, -1, 13, -1, -17, 1, 11, 25, 3, 1, 24, -8, -7, -5, 13, -14, 0, 16, 19, 18, 10, -17, 19, 1, 12, 4, 19, 6, -4, -9, -11, 8, -4, -2, -22, -11, 13, -23, 9, -20, -10, -18, -3, 10, -13, -10, 13, 26, -1, -20, 27, -9, -10, -5, 23, 26, 7, 11, 5, 3, -5, -11, 15, 5, 28, 37, -15, 13, -12, 0, 25, 58, -4, 11, -4, -22, -7, -12, 13, -14, 8, -21, 13, 5, -25, -13, 11, 27, 1, 4, -17, -6, -12, 4, 28, 27, 2, -12, 25, 17, 3, -11, 8, 33, -2, 10, -4, -8, -23, 7, -8, 35, 4, -3, -4, -27, -10, -16, 11, -15, 41, -6, 24, 14, -3, -20, 28, -2, 7, -4, 7, 5, 4, -7, 13, -10, -5, -16, 10, -7, 1, 12, 35, -5, 20, -8, 15, -22, -3, -18, 10, -7, 6, 14, -6, -12, 11, -17, 11, -19, 4, -14, -10, -18, -13, -3, 8, 24, 18, 1, 4, 11, 12, -22, -15, -17, 5, 16, 9, -5, 16, 3, -3, -14, 31, -13, 11, -3, 16, -10, 13, 28, 12, -16, -3, 3, 5, -12, 3, 17, 1, 24, 4, 16, -11, -6, 12, -10, 14, 4, 5, -12, 9, 10, 16, 8, -3, 32, 2, 0, 1, -19, 31, -12, -3, -9, -20, 12, 10, 11, 22, 18, 17, 10, -28, 16, -5, 10, -21, 9, 14, -13, -21, -17, -4, -16, 21, 27, -17, -1, -1, -9, 6, -23, 15, 17, -13, -13, -13, 7, 10, -16, -12, -7, 12, 13, -31, -18, 1, -27, 10, 4, -24, 11, -12, 12, -18, 3, 8, -13, 18, -17, -7, 9, -48, 22, -22, -3, 17, -2, 6, -9, -24, 9, 4, -7, -12, 13, 9, -4, 6, -4, 29, -4, 19, 4, 21, 14, -22, 9, 0, 3, 4, 18, -5, 19, 14, -1, 5, 10, 2, -17, 16, -10, 8, -6, -12, -18, 22, 0, -14, 8, -4, 4, 3, -20, -11, -13, -2, 16, -16, 2, -3, -21, 10, 5, 13, 5, 14, 9, -6, -14, 8, 9, -5, -2, 20, 2, -9, 5, -5, -13, 4, 26, -14, 2, 12, -3, 15, 17, 30, 8, -19, -16, -6, 12, 1, -15, -10, 18, 20, 4, 10, -23, -15, -8, -3, -11, -11, -8, -2, 22, 0, 14, 21, 16, 1, -20, 3, 5, -23, 4, 11, 8, 0, -26, 9, -11, 9, -16, 6, 14, -40, -3, -12, -21, 4, 1, -17, -45, 9, -8, -15, -16, -20, 10, 12, 15, -40, -10, -9, -8, 7, -8, 3, -5, 5, 11, 10, -2, -18, 11, 6, -25, 1, 28, 1, 18, 23, 8, -6, -6, 11, -6, 17, -11, 9, 11, -21, 5, -8, 11, -12, 8, -15, 16, 3, -3, 24, 7, 9, -20, -12, 1, -8, -5, -27, 15, 18, -23, 6, -5, 6, 15, 3, 13, 9, 2, -5, 9, 25, 22, 26, 13, 0, -22, 24, -11, -6, -10, -1, 14, -3, -6, 12, 14, -8, -2, 15, -20, 19, 18, -12, -6, 22, 12, 23, 17, 14, 6, 14, 16, 14, 22, -20, -2, -5, -3, -15, 12, 9, 9, 28, -15, 0, -21, 10, 15, 1, 2, 7, 17, -3, -17, 24, -12, 26, 32, 17, -2, 19, -4, 11, 6, 0, -22, -3, 17, 10, 6, 11, -17, -18, -4, 11, -11, -17, 15, 12, -9, -21, 19, 9, 8, 8, 0, 24, -14, 9, 31, 2, 9, 25, -8, -11, -4, 10, -16, -6, 11, 19, -7, 14, 7, -19, -4, 23, 22, 20, -10, 4, 13, -15, 26, -17, 26, -14, -5, 12, -17, -5, -14, 6, 10, -4, 19, 14, -2, -23, -12, -10, 15, -8, -3, -1, 18, -20, 17, -16, -3, -3, -6, 23, 13, 54, 35, 19, 27, 39, 5, -8, -6, 13, 12, -35, -7, 13, -18, 0, -21, 17, 46, -3, 22, 16, -17, 21, -6, 4, 15, 3, -10, -3, 6, 0, 2, -12, 0, -13, 16, 1, -13, 8, -15, -10, -25, -14, -17, -21, -16, 1, -13, -37, -6, -11, 12, -34, -19, 32, -11, -23, 16, -10, -7, -7, 6, 0, -6, -12, -7, -17, -3, 15, 13, -5, -14, -36, -7, 5, 3, -11, 20, -12, -18, 35, 9, -19, -16, 1, 18, -18, -14, 0, -8, 0, 12, -19, -23, 8, -19, 21, -14, 11, 23, -26, 12, 4, 2, 29, 24, -22, 5, 22, 13, 14, -9, 17, -14, 12, 9, -29, 16, 18, 13, -8, -5, 2, -7, 26, 19, 3, -12, -25, 19, 10, -8, 24, -9, -1, 10, 17, -9, 25, 20, 16, -3, 15, 15, 19, -20, 3, 46, 2, 3, -10, 19, -21, 30, -7, 0, -19, -17, 35, 5, 14, 18, -9, 1, 18, -12, 19, -12, 24, -6, -1, -14, -22, 11, -5, -9, -9, 0, 16, 5, -34, 6, 22, 16, -4, 6, 19, 27, 22, -10, 9, -3, -9, 57, 33, -12, 39, 12, -6, -9, 1, -13, -5, 16, -9, 1, 53, 12, 18, 31, -10, 27, 3, 10, 32, -1, 35, -8, -2, 28, -10, -22, 1, -9, 7, 9, -6, -8, -3, -15, -10, 6, 17, 31, -29, -10, -19, 16, -7, 3, 3, 20, 2, -1, 29, -19, 16, 21, 19, -17, 38, 18, -13, 20, -11, 18, 34, 28, 17, 27, 12, -22, -10, -12, -12, 51, 13, -3, 3, 0, -1, 19, 24, 35, 6, 18, 4, 9, -12, 12, 29, 24, -23, -3, -11, 14, -20, -21, -9, 0, -22, 50, -23, -5, 10, 0, 0, 5, -11, 57, -13, 1, 13, -22, -8, 4, -15, -9, -24, -15, 7, -18, 39, 26, -3, -4, 20, -8, 14, -4, 11, 18, 9, 13, -5, 12, 11, -6, 10, 18, 26, 0, -25, 6, -24, -2, 17, 23, 36, 46, 4, -15, -28, 6, -1, 32, -23, 0, 15, -17, -8, -5, -9, 2, 24, 21, -24, 1, 10, 20, 2, -9, -19, -17, 2, 19, -18, 6, 5, 28, 15, 24, -7, 3, -16, 5, 9, -11, 45, 47, 12, 10, 9, -11, 27, 49, -31, -21, -7, -1, 16, 3, -22, -8, -5, 8, -16, -18, 30, -5, 3, 17, -14, -13, -11, 11, 35, -10, 10, 8, 4, -3, -2, 13, -23, -12, 7, -13, -31, -16, -17, -18, 4, 14, 2, 5, 16, -15, 17, -1, 4, -19, 18, -8, -10, -7, -8, 2, -19, 1, -9, 45, -17, 10, -3, -16, 11, -9, 4, -13, 2, -11, -28, 10, 1, 14, 12, -23, -9, -19, -14, -21, -8, -13, 14, -23, -2, 7, 5, -19, -13, 18, -8, 2, -20, -15, 11, -23, 4, -18, 16, -1, 3, 6, 1, -14, 8, 9, -6, 3, -19, -24, -18, -6, 4, -5, -25, 6, 15, 2, -20, 13, 15, -10, -12, 11, 22, -11, -15, -22, -2, 15, -6, -11, -27, -9, -24, 2, -1, -19, 0, 1, -14, -1, 0, 14, -6, -10, 14, 33, -1, 4, 20, 13, -20, -18, -4, -6, 11, -7, -7, -20, -2, -25, 15, -27, 23, 13, 18, -7, 0, -7, -4, 2, -1, 17, 12, -4, 11, 5, -13, -6, -15, -7, -4, -20, -23, 18, 5, -22, 25, -4, 14, -2, 0, 16, -18, -10, -3, -17, -19, 4, -15, -18, -11, -24, -10, 10, -8, -22, -4, -20, 7, -14, -13, -17, -11, 15, 12, -11, 12, 9, -14, 3, -10, 9, -16, 0, -10, 23, -9, 18, 8, -3, -16, -23, -9, -19, -10, -20, 15, -14, 31, -1, 1, 4, 1, -11, -10, -15, 24, -18, 41, 27, 3, -7, -13, -13, 1, 13, -18, -27, -1, -21, 1, -21, -10, 13, -31, 15, 13, 39, -7, -2, 9, -24, -10, 11, 9, 22, -5, -6, 18, 4, 3, 8, -17, 9, 37, 7, 3, -21, -8, 10, 2, 20, 7, -2, 2, -9, -30, -5, -19, 22, 3, 9, -15, -1, -6, -12, 29, 28, 4, 6, 17, 10, -1, -12, 0, 18, -6, -2, -5, 14, 22, 22, 6, 23, -14, -14, 30, 15, 7, 8, -5, -17, 14, 8, 9, -17, 29, -21, 26, 4, 5, -2, 16, -11, -14, 2, 6, -17, -30, 13, -12, -16, 12, 9, -10, 12, -21, 13, -19, -9, -2, 6, 11, 8, 8, -13, 2, 3, 7, -21, 0, 7, 10, -2, -4, -12, -10, -12, 15, 17, -5, -10, -10, -14, 21, -15, -6, 6, 5, 4, 3, -14, 27, 1, -11, -3, -14, -20, -14, -19, 12, 17, 9, -15, -12, -1, 13, -21, -12, 5, 2, -27, 7, 19, -28, 4, 1, 12, -14, -1, 18, 2, 12, -14, -3, -9, 44, -4, 15, -19, 12, 5, -3, -13, 5, 3, -23, -8, -30, -13, 33, 53, -36, -24, 38, 5, -16, 4, 2, -6, 17, 34, 9, -15, 25, -25, 4, -2, 23, -24, -23, 14, -16, -16, -16, -39, 7, 18, -34, -23, -2, 9, 12, -35, 16, -60, 1, -13, -24, -10, -8, 7, 9, -19, 18, -8, -18, 19, 28, -50, 5, -37, -43, -6, -49, -6, -21, 17, 16, -16, 12, 0, -22, -2, -1, -6, -15, -6, -13, -11, 11, 12, 15, -9, 3, -20, 15, -3, -3, 6, -22, 22, -18, -23, 11, -16, 9, 3, 6, 29, 4, -13, 30, 9, 8, 2, -3, -19, 25, 40, 10, 11, -15, -9, -2, 11, -20, -2, 21, -19, -5, -18, 34, -48, 37, -32, -11, 13, -16, -10, 10, 20, -4, -20, -2, 11, 2, 8, 4, 43, 34, 20, 6, 3, 1, 5, -49, 8, 4, -50, 32, -21, -30, 16, -20, 12, 21, -26, 9, 4, -22, -21, 19, -3, 36, 47, 16, 6, 24, -11, 8, 17, -3, -18, -11, 8, 1, 13, 15, -15, 26, -9, 11, -5, -19, 1, -18, -28, -4, -10, 36, -23, 10, -8, -4, -6, -7, 7, -19, 16, 7, -20, 13, 17, 5, -17, 17, 14, 18, -9, -19, 8, -10, -16, -15, -13, 29, 13, 30, 1, 15, 2, -10, 12, 1, -13, 25, 39, -5, 13, 1, -3, 19, 4, 50, -15, 16, 14, 31, -7, 15, 11, -12, 3, 24, 22, 27, 7, 7, 9, 19, 32, 13, 24, -10, 12, 22, 8, 19, -26, 14, 40, 16, -5, -6, 2, 11, 23, 27, -21, -4, 9, -8, 7, 37, -3, 45, 39, 8, -22, 3, -3, 13, -16, -20, -26, 22, 11, 17, -2, 21, 44, -19, 2, 20, -9, -18, -5, -9, 5, 9, 14, 14, 10, 0, -21, 0, -21, 5, 6, 0, 12, 24, -23, -28, -6, 1, -34, 10, 8, -38, 4, 9, -19, 9, -1, 21, 8, -19, 15, 1, -1, -21, 9, -20, 10, -6, 18, 7, -14, 0, 55, 10, 14, 22, 12, -16, 16, 24, 31, 6, 9, 5, 11, 14, 22, 23, -16, 23, -6, -34, 2, 14, -2, -27, -19, -24, 6, 24, 13, 0, 10, 6, 21, 13, -15, 9, -22, 23, -12, 16, 2, -24, -7, -29, 7, -23, -11, 13, -5, 30, -10, 21, -13, -2, 9, -6, -2, 12, -8, -10, 15, -2, 12, 22, 33, -15, -14, -4, -24, -1, 8, -5, 37, 17, 14, 10, 6, 10, -15, 1, 1, 9, 4, -9, 7, -18, 7, -13, -11, 10, 16, -41, -24, -16, 32, -18, -1, -10, -4, 16, -18, 3, -2, 14, -15, -11, 9, 20, -10, -4, 41, -4, 13, -19, 22, 2, -9, -3, 4, 30, 12, -11, -19, -12, 17, 4, 28, -10, -30, -17, -11, -22, -4, 4, 3, -4, 58, 9, -13, -33, -8, -18, -12, -1, 14, 6, 0, 7, -15, 18, -3, 31, 9, -5, -13, -28, -5, -4, -12, 6, 12, -16, 3, -2, -2, 3, 9, -8, -24, 11, -10, 14, 17, 27, 22, -3, -27, -7, -14, -2, 12, -6, 1, -27, -2, -1, -10, 19, -14, -17, -12, -12, -25, -3, -20, 12, 15, -11, -25, 9, -15, 22, -7, 20, 15, -9, -11, 13, 5, 14, -13, -7, 5, 15, -15, 10, 31, 19, 14, -2, -1, 35, -14, 4, -4, 15, 16, -10, -20, 0, 14, -2, 50, 13, -19, -8, -4, -9, -15, 20, 17, -11, 5, 0, 11, 0, -17, 5, -12, -1, -18, 7, 14, 12, -23, 15, 18, 7, -15, -11, 14, 29, -10, 4, 9, -32, -12, 4, -12, -17, 26, 9, 9, 12, -7, -10, 7, 6, 37, -1, 8, -18, -6, -8, -16, 10, -5, -19, 16, 14, 13, 16, -7, -22, -15, 2, -9, -17, 13, 9, -7, 8, 20, -20, 4, 10, -12, 20, 10, 20, 1, 4, 4, -14, -4, -14, -17, 18, 6, 2, -5, 14, 12, 6, -19, 10, -1, -8, -21, 0, 2, -6, 2, -7, -29, 21, 9, -11, -4, -8, 18, -13, -11, 13, 27, 6, -19, -8, 8, -11, 9, 1, -12, 0, -6, -14, -14, 1, 2, 7, 20, 5, 2, 21, -18, 26, 5, 3, 9, -30, -20, 15, -21, -5, -3, -21, -23, 33, -3, -12, -8, -10, -13, -12, 15, 16, 11, 40, 6, 6, 15, -15, 9, 6, -3, -24, 16, 1, 16, 13, 11, 25, -15, 23, 8, 16, -34, 7, 7, -9, 7, -32, 16, 2, 2, -1, 32, 23, -17, -10, 8, 7, 7, 36, -1, -31, -14, 10, 16, -20, -7, -2, -3, -10, 2, 18, -17, 11, -64, -13, 24, -16, 7, -11, -17, 9, 20, -1, -2, 5, 4, -3, 14, -1, 15, -20, 6, -12, 5, 15, 2, -4, -7, -17, -18, -20, -21, 9, -19, 10, -8, 24, -10, -6, -19, -2, -4, 13, -11, 22, -19, -24, 19, 3, -16, -7, -14, -17, 22, 9, -1, -25, 0, 1, 6, 10, 4, 25, 4, -4, 17, -14, 17, 1, 6, 6, -26, -10, -24, 11, 10, 10, -2, 12, -3, -26, -21, 14, -19, 17, -32, -25, 10, -11, 0, 10, 1, 16, 6, -20, 7, -4, -20, 19, -9, -2, -27, 9, -22, -3, 12, -3, 16, 5, -1, -26, 6, 2, 16, -3, -7, 0, -24, 25, 19, -32, -18, 0, -6, 17, 12, -6, -21, -27, -11, -17, -22, -22, 0, -1, 16, -10, -10, -8, 36, 3, 8, -26, 14, -16, 9, 4, 16, -22, 24, 7, -15, -1, -15, -1, -5, 13, -29, -8, -4, 13, -15, 8, -48, 11, 7, -11, 11, 10, 16, 13, 1, -13, 11, 2, 1, 4, 6, -2, -17, 21, 3, 12, -18, -8, -11, 12, -22, 10, -22, 16, 0, 13, 15, -4, -33, 10, -5, 7, 1, 8, -22, 7, 1, -17, -20, 9, -14, 23, -11, -14, -73, 15, -20, -20, -16, 4, -17, -16, -16, 4, -4, -33, 11, 33, -15, 22, -30, 2, -12, 15, 13, 0, 5, -7, -28, -8, -40, 8, -9, -6, 15, -14, -26, -4, 16, 16, 3, 32, -6, -8, 6, -2, -47, 4, -11, -19, 14, 18, -30, 3, -24, 6, 13, 0, -7, 18, -9, -6, -6, 10, 2, 26, -17, -24, 4, -3, 18, -19, -5, 14, 0, 3, -31, -11, -13, -18, -15, -4, 19, 22, -24, 0, -12, -6, 14, 1, 3, -20, -24, 26, -14, 17, 6, 19, -18, 29, -19, 8, -11, 28, -17, 9, -17, 18, -38, 3, -22, 15, -3, 6, -13, -21, -7, 4, -14, -10, -13, -27, 6, -1, -18, -20, -23, -7, -7, 19, 0, -19, 7, 23, -19, 5, 19, -16, -3, -15, 17, -24, 25, 16, -1, -3, 14, -2, -6, -13, 2, -17, 6, 4, 13, -12, 22, 5, 39, 19, 0, -34, -10, -14, -16, 1, 30, -6, -2, 25, 12, -9, 27, -20, 11, -15, 1, -11, 12, 13, -7, 6, 10, 5, -10, 22, 6, 6, 19, 24, 3, -28, -22, 16, -22, -17, 4, 15, 4, -40, 11, 5, 12, -19, 9, 7, 8, -7, 8, 7, 5, -31, 13, -19, 9, -7, 14, 20, -4, -30, 4, -22, -21, 21, 2, 10, -17, 18, -15, 12, 1, -10, -5, -4, -11, -18, 1, -26, 12, 3, 4, 16, -16, -13, 6, 20, -9, -4, -18, 5, -6, -20, 13, -19, -2, -18, 0, 41, 14, -17, 15, 6, 5, -12, -16, 29, 5, -19, -11, -2, -22, -6, 6, -16, 0, -27, 31, 8, 16, -26, -3, -20, -22, 9, -9, -18, 14, -19, -8, 0, -2, -3, -7, -33, 37, 1, -15, -5, 0, 8, 14, 3, 8, -5, -8, -5, -11, -2, 4, -6, -32, 18, -24, -9, -14, 6, -13, 4, 7, -6, 12, -20, -20, -4, 8, 2, 1, -32, -9, -12, 17, -4, 35, 4, 9, 4, -17, 3, 18, -15, 43, -13, -34, -13, -10, -23, 17, 21, -14, 24, 11, 12, 2, -27, -15, -14, -28, -26, 9, 1, 2, 20, -20, -14, -15, -16, 13, 3, 7, -4, -12, 23, 2, 2, -1, 37, 10, -27, 16, -5, 25, -5, 6, -25, -7, 39, 10, -20, 30, -1, -12, -8, -18, -32, 18, -19, -11, 6, -6, -17, 0, 9, -3, -12, -31, -12, -11, -26, 9, 28, 14, -4, -18, 1, -1, 13, 2, -26, -2, 9, 4, -10, 27, -4, -21, 14, 3, 44, -31, -10, -21, -11, 8, 1, 6, 13, 31, -8, 9, -21, 9, 20, -21, -2, 23, -7, 15, 6, 7, 10, 10, 6, -7, 11, -7, -11, 6, -11, 5, -4, -2, -13, -26, 2, 4, 9, 15, -2, -14, -12, -5, -9, -10, -8, -4, -12, -29, -15, -8, 8, -11, 9, -2, -12, 13, -11, -14, -14, -13, -2, 16, -11, 11, -12, -14, -17, 14, -12, 20, -8, 10, -9, -11, 6, -14, 40, -5, -9, 0, -21, -33, -2, 16, -1, -13, -20, -12, -13, -9, -26, -17, -14, 1, -8, 13, 12, 22, 18, 3, 7, 19, 6, 27, -30, -32, 17, 10, -31, 16, -10, -12, 5, -30, -4, -7, -14, 3, -27, -28, -5, 7, -16, 2, 21, 14, -15, -7, -3, 3, -4, -14, 22, -21, -11, 6, -21, 0, -4, 8, -4, -2, -5, 8, 35, -13, 14, -12, 29, -4, -17, -3, 3, -12, 13, -16, -1, 4, -11, 24, -7, -36, -20, -17, 8, -12, 35, -4, -19, 3, 49, 5, 4, -3, 13, -6, 13, 30, 0, 5, -15, -17, -11, -8, -23, 8, 15, -4, 3, -21, -4, 3, -19, -20, -33, -3, 6, 10, 8, -22, 17, -19, -19, 1, 0, 1, -3, -7, -24, 25, -17, -16, -10, -21, -6, -3, 0, -34, -21, 13, -27, 19, 15, 17, 1, 16, -21, -14, -12, -15, 9, 22, -10, -5, 16, 19, 8, -16, -33, -19, 12, -11, -17, -2, 17, -20, -12, 14, -31, -19, 23, 10, -8, 13, -27, -27, -1, 1, -23, 6, 1, 3, -20, 47, 11, 27, 12, -15, -18, 13, -35, -13, -2, 42, 4, -2, -23, 4, 4, 3, 12, 13, 13, 19, 2, -22, 19, -3, -21, -9, 14, -14, 21, 20, -2, -27, 18, 14, -1, -12, 16, 14, -9, -6, 14, 9, -5, -19, -2, -12, 27, -6, 25, -20, 15, -10, 7, -7, -20, -4, -2, 2, 18, 2, -3, -22, -5, -10, 8, -11, -4, 17, -16, 17, -18, -16, -5, 14, 12, 2, 10, -2, -6, -7, -10, -6, 1, -16, -13, 20, 13, -15, -4, 10, -1, -17, -4, -8, 17, 16, 7, -11, 28, -6, -6, 7, 21, 1, -14, -1, 5, 5, 3, -13, 11, -16, -5, -20, 22, 15, 24, 4, 10, -11, -15, -35, 14, -19, -7, -15, 7, -25, -9, -7, 3, -2, -8, -13, 2, 10, -2, 4, -3, 16, 26, 17, -13, 7, -14, 21, 29, 4, 16, 14, 18, -10, 6, 6, 13, -12, -13, 7, -5, 2, -13, 4, -2, -15, 42, 16, 24, -11, 19, -10, -3, 1, 9, -16, -9, 14, 12, 3, -4, 4, 15, -10, -18, -4, -1, 9, -27, 7, -10, -11, 17, -6, -28, 4, 1, -9, 8, 9, -16, 12, -9, 13, 7, -16, 11, 10, 9, 7, -16, 18, 2, 8, 1, -6, 5, 7, 3, -13, -20, 25, 16, 6, 6, -2, -16, 21, 2, -28, 13, 2, -7, 1, -30, 31, -13, 10, 7, -4, 10, 3, -25, 27, -21, 1, 14, 7, 16, 7, -21, -16, -5, -25, 11, -17, 3, 12, -11, 5, 0, 29, 21, -3, -4, 10, -20, 9, -3, 29, -2, 22, 19, 3, -21, 15, -19, -10, 7, -6, 13, 9, -12, 17, -7, -19, 12, -13, -22, 9, -14, 22, -16, -12, 2, -34, 12, 23, 21, 15, 9, -4, -5, -18, -2, 3, 6, 8, 11, 7, -19, -4, 4, 5, -16, 21, -13, 13, 18, 13, -8, -15, -25, 23, 6, -3, -14, 1, -8, -4, -47, 28, 10, -11, -12, 15, -26, 4, -12, 17, -14, 20, -8, 21, 1, 8, 15, -15, -3, -21, -18, -8, -24, -16, 11, 4, -6, -11, -3, 8, -11, -1, -23, -1, 10, 15, 19, 0, 8, 33, 10, 9, 1, 10, -11, -17, -18, 3, -16, -12, 5, -1, -18, 15, -15, 18, 5, 14, 16, -12, 8, -15, 5, -27, -24, 18, -13, 12, 14, 7, 10, -8, 2, -15, -16, -2, 18, 10, -19, 4, 34, -18, 1, -3, 9, -21, -14, 16, -5, -19, -12, -10, -5, -7, 12, 5, -29, 3, -16, 26, -5, -23, -12, 4, -10, 17, 14, 25, 5, 2, -12, -4, -8, 4, 10, 5, -22, -10, -13, 1, 5, -10, -25, 21, 0, 0, -23, 8, 10, 25, 2, -10, -1, 22, -11, 3, 11, -18, 14, 2, 14, -11, -5, 15, -12, 27, 9, -3, -17, 7, 6, -19, -21, -22, 16, -13, -22, -6, -18, 23, 0, 14, -18, -4, 12, 9, 5, 7, 26, -23, 15, -16, -12, -15, -17, -4, 2, -14, 10, 11, -3, 13, 1, 20, -12, 11, -20, 7, -21, 11, -17, -5, 9, 20, -21, -25, -12, 15, 11, 25, -19, 30, 13, 15, 1, -1, 6, -9, -20, -9, -22, 5, 8, -27, 14, -3, 3, -3, -12, -32, -19, 14, 13, 22, 9, 20, 18, -11, 14, 3, 13, 15, 1, -9, -21, -21, -8, -9, -6, 6, 7, 11, -1, 16, 12, -7, 13, 27, 9, -9, -11, -5, -11, 8, 51, 13, 8, -21, -13, -2, 17, 9, 29, 2, -2, 20, -9, -26, -13, -10, -35, -29, -13, 32, -16, -1, -11, 7, 7, 14, 15, -7, 18, -29, -3, -25, 3, -10, 30, 8, 2, -20, 0, -32, -3, 19, 12, 5, -2, -12, 7, 12, 4, 24, -1, 24, -1, -51, -17, -9, -18, 29, 14, 6, -1, -27, -18, -45, 21, 6, -4, 22, 11, -7, -19, -16, 21, 16, 21, -18, -7, 2, -20, -19, -27, 1, 10, 9, 17, 14, 13, 1, -9, -13, -30, -22, -14, -27, 18, -13, -11, 21, 13, 8, -7, -19, -7, -21, 40, 15, 8, 0, 2, -3, 13, 2, 4, 3, 22, 5, 12, -19, 19, -14, 21, 25, 6, 29, 15, -18, -20, -22, 19, 17, 17, -2, -14, -21, -19, -15, -1, -21, -7, -23, -12, -3, 4, -28, -16, -3, -13, 17, 7, 4, 0, -33, 10, 14, 21, 1, 15, -25, -20, 14, 22, -16, -6, 18, -5, -45, -21, -26, -14, -8, -30, -42, 7, -3, 17, -10, -10, 6, 8, 8, -19, -32, -7, -4, -13, -2, 10, 18, 1, -18, 16, -3, -36, -24, 22, 3, 21, -2, -8, 4, -3, -16, 0, -6, 5, 8, -21, -6, 1, -9, -5, 5, -19, 17, 1, -10, 5, -5, -28, 15, 4, -20, 7, -43, -13, -2, -8, -10, 3, 7, 7, 5, -6, 19, 6, 10, -7, -14, -5, -36, 6, 6, -4, -12, -13, -26, 7, -3, -10, 2, -7, -8, -5, 15, 6, -18, -18, -23, 4, 3, 18, -28, 5, -24, 16, 8, -2, -12, -17, 1, -22, -21, 5, -13, -7, -20, 17, 24, 10, -16, -11, -12, -34, 27, 19, -10, -14, -35, -17, -15, -14, 5, 19, -47, 0, 19, -16, 20, 21, -6, 15, -39, -21, -17, -20, -14, -11, -19, -3, -17, -15, -4, 6, -35, 2, -14, -15, 35, -19, -11, 22, 16, 10, -2, -21, -10, -5, -25, -18, -8, -21, -4, -18, -24, -20, -28, -27, -9, 1, -4, 8, 4, -8, -14, 5, -21, 11, -14, -11, -37, 10, -29, 14, -24, -7, 16, 16, -9, 16, -34, -16, 16, 2, -15, 8, -34, 3, -35, -3, -9, -24, -16, 14, -11, 9, -32, -7, 13, -6, -19, -9, -22, 4, -26, 22, -21, -11, 13, -13, 5, 9, -24, -23, 9, -14, -20, -10, -39, 23, 14, -22, 23, 12, 10, -19, 15, 2, -4, 5, 31, -30, -28, 15, -3, -10, -6, -28, -19, -37, 15, 18, -26, 13, 40, -7, 12, -20, -28, 6, -25, 11, -2, -27, -26, -14, -24, -12, -6, -9, 8, -23, -4, -15, -16, -21, -6, 14, -17, -19, -8, -13, 3, -17, 0, -6, 7, 15, 4, -24, -9, -5, 5, 2, 0, -15, -22, -17, -11, 16, -1, -5, 2, 12, 13, -20, 12, 4, 9, 13, 48, -11, -9, 16, -21, -4, -7, -6, 8, 0, -17, -7, -21, -11, 7, -19, -1, -14, 32, 7, 0, -4, -15, 14, -10, 7, 15, -25, -15, 15, -6, 1, -8, -8, -15, -5, -4, 2, 13, 16, -16, 26, 24, -3, 8, 17, -24, -24, 4, 7, -14, -7, -28, 0, 19, -13, -21, -5, 5, 2, 37, -10, 7, -22, 25, -10, -2, -15, -22, -17, -13, 20, -11, -1, 45, 7, -6, 8, -10, 5, 14, -16, 20, -25, -9, 9, -16, -3, 12, -14, 18, -27, -31, 2, -1, -8, 0, -7, 13, -6, -25, -8, -17, -11, -17, 8, -7, 19, 11, -15, -23, 7, 14, -19, 9, 9, 32, -8, -20, 12, 1, 16, -6, 2, 0, -5, 27, -11, -8, 6, -9, -17, -7, -14, 5, -20, 12, -15, 3, 17, 25, 12, 29, 3, -14, 38, -13, 9, 23, 9, 5, 15, -9, 34, -15, 22, -9, 19, 16, 11, 28, -7, 25, -22, -6, -19, 19, 7, -11, -11, 30, 17, -13, -13, -6, -11, 18, 17, 22, 5, 11, -5, -1, 1, -7, 10, 41, -12, -7, -16, 7, -21, 7, -3, -18, -10, 3, -7, -10, 18, -14, 20, 32, 2, 19, -1, -1, 13, 21, 2, 9, 12, 1, 5, 24, -2, 11, -17, 9, -5, 31, 18, 11, -7, -1, 30, -14, 4, -19, 5, -11, 11, 5, 11, -4, 1, -9, 7, -11, -17, 1, 11, -9, -15, -16, 14, 11, -3, -31, -20, -18, 4, 18, 16, 17, -10, 2, 0, -17, 16, 13, -20, 24, -15, 37, 32, 18, -7, -17, -8, -16, -18, 10, 12, 0, 20, -12, 2, 11, 1, 17, -1, -18, 11, 8, -5, -28, 1, 18, 4, -3, -6, -8, -6, 10, 6, -19, -16, -17, 16, 6, 16, -21, 17, 3, -11, -20, -15, 17, -3, -17, -6, -9, -30, -31, -6, -7, -1, 4, -11, -21, -26, -18, 2, 17, -21, 4, -15, 2, 10, -16, 24, -15, -17, -13, 13, 6, -5, -28, -19, -11, 14, 19, 0, -33, -15, -24, -10, 9, -17, -8, 9, 20, -6, -21, -11, -28, 8, -22, -3, 30, -6, -7, 18, 2, 15, -10, -19, 10, 28, 10, -4, -6, 9, -1, -20, -5, 5, 0, -13, -2, -6, 22, -10, 5, -43, -12, -23, 15, -5, 33, -15, -20, -16, -39, -2, -4, 10, -14, -10, -20, 5, 17, -22, -21, 10, 23, 6, -32, 15, 3, -11, -16, 0, 9, 6, 25, -29, 7, 14, 17, -21, 6, -18, -23, 14, 22, -7, 10, 8, -3, 14, 29, -12, 23, -15, 2, -11, -2, -20, -23, -7, -3, -1, -15, -12, 1, -7, -27, 4, 0, -16, 4, 7, 6, -5, 8, -2, -31, 1, -17, -17, 12, -1, -12, -44, -9, 24, 0, -4, -1, -16, -23, -18, -6, 31, -15, -17, 3, -20, 1, 12, 54, 2, -35, 12, 6, 6, -1, 25, 11, 12, -25, 19, -33, 16, -15, 4, 27, 2, -12, 14, 23, -6, -8, -22, -14, -37, -50, 16, 16, -13, -9, 12, 9, -8, 1, 18, 11, 8, -32, 9, -37, -15, -19, -25, -3, 7, 22, -29, -17, 19, -4, -1, 16, -9, -13, 7, -15, -9, -3, -14, 0, -6, 7, 16, 28, -27, 6, -22, -11, 9, 5, 7, -16, 4, -4, -9, 25, -25, 4, -6, 17, 17, -22, 3, 7, 5, 5, -15, -26, 5, 7, 19, 0, -8, 20, 0, -11, 19, -15, 15, 20, -5, -28, -17, -3, 5, -3, 21, -5, -22, -32, 16, -1, -37, -49, -5, -16, -18, -2, 9, 8, -25, -10, 9, -13, -2, 5, 11, -35, -28, -28, 15, 30, 3, -7, -8, -29, 0, -6, 17, 3, -4, -15, -14, 21, 9, -5, -16, -28, -5, -5, -13, 16, -13, -30, -14, -16, 13, -3, 24, -3, -9, 11, -17, 6, -5, 5, -15, 25, 16, -16, -12, 42, 12, -20, -45, -12, 21, -18, -22, 18, -15, 10, -23, -5, -5, 8, -14, -13, 12, 20, 21, 6, 14, 20, 11, -10, -10, -25, -39, -5, 17, -12, -1, 11, 19, -2, -12, 14, 12, 3, -15, -8, -5, -14, 8, -3, 10, 11, 9, 1, -2, -11, 14, 21, -25, -7, 20, -1, 8, -25, -16, 16, 6, 5, -11, 16, -7, -25, 13, -6, 8, 4, -13, -2, 5, -8, 13, 17, -33, -59, -9, -34, -20, -22, -26, -3, -7, -10, 3, -32, -17, -15, 24, 32, -11, 5, -14, -35, 13, -1, -5, 3, -10, -9, 11, 24, 4, 8, 16, -17, 7, -24, -5, -1, 10, -2, -20, -23, 15, 30, -9, 8, 4, -34, 5, -9, -5, 3, -3, 1, 17, 8, -21, 8, -12, 6, 11, -23, -1, 6, 0, 14, 0, 11, 10, -2, -6, -19, -9, -8, 19, -12, -7, -6, 6, -19, 1, 16, -31, -34, 7, -12, -21, -24, 23, 40, 9, 7, 8, -1, 0, 6, -15, -13, -28, -17, -4, -10, -1, -28, -13, -21, -8, -14, -5, -4, -17, -2, -49, -23, -19, -2, 14, -4, -10, -22, 6, 5, -23, -19, -20, -3, -6, -31, -6, 8, 10, -11, -12, -5, 11, -4, -39, -39, -3, -15, 13, 6, -8, 10, -2, 20, -12, -18, -6, -15, -6, 13, 10, -24, -24, -19, 1, 5, -16, -13, -7, 8, 2, 10, -5, 3, 3, 1, 4, -17, -17, 8, 14, -18, 2, 8, 1, -6, -5, -21, -21, 3, -16, -30, -17, 21, 6, -12, 4, -35, -15, -14, -28, 0, 27, 22, -19, -3, -15, -29, -12, -17, -10, -32, 13, 13, 17, -16, -36, 7, 0, -6, -6, -22, 5, 8, 26, -4, 19, 12, 10, -7, -17, 18, -10, -1, -10, -27, -10, -25, -2, 2, 28, 5, -25, -17, -16, 15, 1, 5, 2, -5, 13, 22, -16, -24, 5, -6, 12, -19, 34, 27, 16, 12, -13, -20, -20, -25, 7, -3, -19, 7, -5, -23, -11, -14, -2, 28, 14, -20, -14, -31, 6, 0, 7, -12, -5, 15, 14, 18, -2, 30, 4, 14, 4, 15, 8, -12, 19, -2, -28, 14, -8, -14, 8, 2, 12, 18, -13, 13, 10, 11, 0, 6, -25, 9, 41, 30, 2, 13, -17, -12, -3, 4, 21, 10, 0, -30, -9, -5, 10, 24, 29, 31, -23, 14, 0, -32, -23, -35, 4, 19, -14, 22, -14, -15, -12, 2, -11, -10, -5, 1, 2, -10, 14, 1, -21, 3, -6, 23, 6, 24, 12, 12, 1, -9, 16, 39, 14, -31, 10, 17, -23, -29, 2, -6, 13, 20, 0, 11, 9, -62, 8, 7, -14, -11, 14, 27, -6, 4, -9, -15, 10, 7, -16, 19, -1, -26, -13, 9, 18, -19, -7, 11, 2, 14, -14, 10, -6, -3, -22, -10, 0, 14, -5, -6, 2, -19, -6, -13, -2, 14, 11, -26, -6, -25, 10, -3, -6, -14, 3, -6, 19, -4, 17, -6, 1, 8, -18, 18, 19, 14, -2, 12, -18, -28, 4, 14, -17, -8, 22, 15, -27, -26, 6, -32, -17, 1, -3, 25, 12, -7, -16, 31, 13, -17, -2, 8, -17, 6, -18, 13, 13, -25, -29, -26, 16, -15, -13, -17, -2, -3, 5, 8, 1, -2, -24, 21, -18, -37, -16, -1, -24, 7, -2, -3, -21, -2, 1, -16, -29, -4, 5, 5, -20, 1, -15, -30, -2, -19, 16, 17, -9, 2, -4, -11, 6, -11, -9, 12, 14, -14, 9, 23, -11, -13, 2, -15, 10, 16, -29, -29, 20, 17, -23, 14, -10, -45, 18, -26, 7, 11, -9, -11, -22, 20, -20, -2, -11, 17, 5, 5, 13, 30, 18, 37, 26, 44, 9, 26, 14, 10, -4, 4, 13, 10, 9, -12, -12, 3, -3, -11, 26, -6, 1, 11, 8, 2, 0, 39, -14, 4, -12, -36, -20, 22, 4, 3, -6, -21, -9, -13, -22, 2, -20, 4, -4, 38, 11, -12, -12, 15, 4, 11, -15, 5, 7, 15, -3, 13, -27, -11, 28, 15, 12, 6, -11, -18, 31, 32, -7, -25, -4, 0, -7, -8, 20, 43, 11, 24, -18, -25, -14, -3, 18, 15, 27, -2, 8, 12, -3, 4, -11, 8, -15, -12, -19, -4, 22, 12, 9, -13, 16, 1, -16, 30, -19, 22, 1, -14, 7, 2, -8, 22, -15, 27, -8, 20, 4, -8, -2, -17, 7, -45, 15, 28, 26, -8, -24, 19, -8, 6, 11, -14, -15, -20, 6, 21, 17, -1, 14, -20, -16, -9, 5, 4, 6, 7, -3, 17, -5, -26, 10, 17, -1, -16, 4, 18, 6, -13, -8, -14, -8, -9, 26, 41, -6, 7, 8, -23, 19, 2, -17, -18, -3, -1, -20, 15, 10, 23, 32, 23, -23, 11, 16, -12, -5, -20, 7, -2, 0, 2, 11, -23, 8, 20, 16, 7, -10, 10, 15, -40, 4, -26, -8, -8, 3, -1, 20, 32, -6, -5, 26, 29, -22, 7, -17, -3, -12, -32, -26, 2, 1, 2, 16, -28, 19, -4, -30, 1, 15, 39, -15, -20, 9, 1, 6, -21, -33, 15, -4, -26, 4, -13, -13, -6, -12, 24, -18, -9, -21, 6, -11, 0, 49, 43, 14, -44, -20, -30, 33, 8, 6, -2, -7, -26, -16, -18, 41, 29, 0, 28, -14, 8, -17, 0, 4, 2, -3, 30, -1, 2, 7, -16, 7, -8, 5, -4, 16, 20, 15, -8, -8, 13, -10, 26, 1, -20, 8, -12, -4, 6, 38, 29, 10, 11, 10, 26, 2, 3, 28, -5, -11, 17, 17, -13, -43, -7, 1, 29, 19, -21, 19, -5, 0, 27, 2, -1, -6, -30, -8, -9, -9, 17, -2, -17, -21, 4, -5, -12, 5, -19, 8, 33, 5, -10, 4, 5, 43, 34, 11, 6, -6, 5, -2, -7, 10, -4, -44, 4, -22, -26, -5, 4, -7, 33, 1, 29, -12, -15, 8, -6, -27, -17, 5, -3, -8, -7, -20, -19, 20, 3, -10, 11, -1, -28, -4, -17, -14, -1, 1, 26, -3, 14, -8, -25, 19, -5, -24, -12, -13, -12, -13, -15, 10, 20, -4, 6, 4, -41, -7, 15, -16, -24, 16, 29, -5, 3, 5, -1, -17, 29, -37, -38, 16, 5, -4, -13, 4, -26, -2, -3, -5, -18, -15, 7, 13, 15, -30, 19, -23, -9, 16, -16, -9, 16, 42, 28, 5, -35, -27, -7, -1, 26, -16, 4, 13, -26, 6, -33, -42, 11, -16, -2, -18, -50, -14, 18, 1, 7, 7, 1, 9, 9, -18, -21, -25, 12, 1, -6, -18, 3, -15, -20, 12, -16, 17, 17, -16, -13, -21, -21, 12, 7, -25, -6, -18, 9, 7, -25, -13, -1, -12, 1, -13, -29, -14, -55, 3, 18, -10, 13, 17, 21, -10, -43, 3, 2, 4, 0, 6, -11, -7, -24, -3, 36, 10, 9, -1, -12, 7, -48, 13, 20, 17, 20, 12, -22, 18, -16, 14, -6, 7, 10, -8, -41, 17, -18, -8, -22, 0, -5, 9, -14, 2, 5, 9, 6, -30, 16, 8, -6, -21, -24, -48, -4, 2, 4, -21, 16, -21, -30, 27, -14, 15, -13, 19, -32, -3, -5, 20, -8, 7, -7, 12, 3, -7, 5, -2, 11, 20, 13, 1, -37, 13, 9, -35, 4, 31, 30, 17, -25, -8, 27, -18, 17, 28, 6, -11, -9, 1, -16, 1, -23, 14, 23, 8, -10, -5, 1, 16, 5, 0, 34, -14, -11, -6, 18, 18, 4, -19, 7, -8, -3, 14, -11, 0, -11, -7, 37, 8, -21, -11, -42, 9, 3, 29, 15, 3, 0, 11, -11, -1, 2, 13, -6, 19, 36, -18, -23, 21, -15, -7, -1, 15, 17, -9, -31, 7, 1, 25, 13, -9, -36, -12, -49, 16, 14, -2, 0, -14, -37, -16, -21, -15, 9, -31, -22, -14, -2, 14, -3, -26, -1, -19, 4, -9, -17, -1, -39, 7, -11, -23, 8, -23, 8, 1, -19, 12, 24, 12, 19, 3, -36, 6, -12, -21, 8, 30, 11, -18, -38, -7, -22, -7, 0, 25, -9, 7, -17, 10, -41, -4, -15, 5, 29, -2, -15, 3, 1, -7, -21, -8, 0, 15, 13, 7, 1, -2, 4, -6, 5, -9, -49, 10, 18, -32, -22, -12, 11, 9, 59, -19, -14, 6, -3, 24, 21, -3, -7, 7, -15, -28, 7, -2, 7, 13, 10, 15, -24, -9, -8, 1, 0, -8, -23, -18, 10, 11, -19, 16, 24, -17, -4, 19, 33, -5, 13, 7, -7, -1, 0, 7, -1, 6, -13, -1, 7, -8, -9, -2, 3, 10, -1, -38, 2, -12, -28, -12, -9, 19, -8, 19, -20, 7, 5, -16, -40, -1, 10, -14, 9, -12, -3, 18, -10, -18, -7, 14, 20, -5, 14, 8, 28, -28, -37, 13, 14, -20, -3, -17, -3, -1, 25, 23, 0, 17, 32, 15, -11, 31, 20, 26, 40, 7, -10, 13, -1, 8, -3, -7, -11, 20, -15, 10, 12, -7, 15, 17, -10, 12, 9, -16, 42, 3, -45, -18, -9, 14, 32, 9, 22, 13, -5, 12, 12, 11, -28, -16, -19, 11, 17, 6, -7, -16, -27, -6, 17, -18, -18, 38, -4, -21, -15, -18, -20, 26, -1, -26, 14, 3, -37, -18, 1, -30, -12, -20, -18, 20, -27, -8, 1, -18, -28, -2, -3, 15, -1, 5, -31, -5, -36, 18, -8, 7, -29, -20, -2, -28, -31, 19, 0, 4, -10, -19, -39, 43, -16, -11, 19, -22, -45, 5, 18, 19, 4, 11, -6, 18, -32, -4, 7, -23, -11, 56, 14, 7, -6, -19, -10, -10, 14, -14, 8, -1, -26, 16, -20, -21, -19, -14, -4, 3, -19, -11, -25, -4, -8, -14, 6, 26, 5, -4, -56, 19, 0, 5, 3, -16, -25, 1, 2, -23, -13, -15, 0, -10, 11, 15, -30, 15, 4, 2, 13, -13, -27, 25, -9, -21, -11, -1, -18, 21, -3, -7, 5, 16, -3, -45, 15, 26, -6, -1, 15, -14, -5, -11, 8, 11, 4, 13, -5, -31, -20, -18, -16, 30, -22, 10, -23, -16, -5, -8, 9, 44, -9, 13, -3, 35, 12, -14, 11, -10, -9, 39, -24, 14, -10, 12, 7, -19, -33, 15, -39, -23, -4, -40, -10, 3, 19, -4, 5, 13, 1, -6, 14, 25, -15, 6, -30, -7, -21, 46, -3, 29, -18, -15, -24, 10, -25, -5, 15, -22, -13, 25, 23, 13, 4, 8, -14, -10, 1, -13, -44, 31, -3, -2, 6, -9, 1, 20, 14, -1, -22, -3, 0, -19, 9, 12, -18, -24, -22, 2, 15, -3, -13, 8, 7, 20, -20, 29, 19, -23, -23, -18, -12, 7, 7, -26, -16, -15, -14, -10, 7, 17, 9, 17, -23, -19, -14, 21, -17, 17, -3, -9, -20, 21, 13, 30, -3, 19, -1, 24, 20, 8, 12, -9, 26, 21, 6, 14, 18, 13, 19, 26, -13, 31, 3, 18, 1, 6, 6, 10, 8, 11, -12, -14, -10, 4, 3, 5, -8, 8, -1, -17, -5, -4, 11, 4, -8, -4, 2, 6, 9, 2, 9, 20, -15, 19, -23, 1, 9, -13, -16, -6, 14, 7, 8, -17, 13, 10, -9, 26, 26, 20, -9, -32, 11, 2, -12, 0, 15, 25, 14, 25, 11, -20, -14, 2, -15, 24, 3, 9, -10, 9, -31, 8, 3, -53, -10, 4, 6, 14, -4, -12, 1, -10, 13, 16, 11, 46, 12, 2, 1, 18, 3, -17, -12, -39, -23, -10, -11, 11, -19, 18, -15, -15, 1, -34, -32, 27, 0, -4, -14, -6, -12, -6, 4, 6, -3, -17, 17, -6, -24, -3, -1, -11, 6, -18, 0, 25, -29, 11, 29, -4, -6, 13, 0, -5, 30, 15, -21, -6, -13, 23, -10, 24, 16, -3, 5, -26, -21, 7, 3, -8, 25, 17, -20, 6, 4, -19, -21, 13, -16, 11, 21, 10, -12, 19, 1, -14, 7, 13, -6, 25, -3, -13, 7, -5, -6, 0, 32, 18, 3, 11, -23, -16, -5, 30, -23, 23, 18, -4, -18, 2, 1, 9, -20, 6, -20, -4, 9, -36, -28, -8, -4, -23, -20, 0, 19, 23, -21, -12, 6, 12, -20, 4, 6, -3, 15, 15, 8, -11, 15, 10, -16, 22, 6, 22, -12, 10, 11, -3, 11, 4, -13, -11, -25, 14, -3, 9, 0, 41, 21, 8, -19, 9, 17, -9, 6, -13, -7, 17, 5, 6, -1, -2, -18, -12, -10, -1, -16, 6, -2, 0, -3, -24, -22, -2, -13, -27, 0, -22, 5, -5, 17, 37, 26, -27, -20, 14, -3, 24, 23, 20, -14, 22, 15, 9, 15, -26, -20, -4, 24, -14, -13, 25, 1, 28, 30, 23, -22, -1, -3, -3, -15, 8, 28, 12, -9, -7, 4, 7, 0, -17, 0, -4, -15, -12, -19, 18, 18, -6, -27, 7, 0, 12, -10, 0, -13, -19, -6, 20, -9, 2, -6, 5, -22, 2, 19, -34, -27, -19, -9, -23, -14, 0, 38, 5, -19, -25, 7, -31, 9, 38, 13, 17, 6, -35, 8, -9, -13, 41, 17, 3, -14, 7, -2, 3, 7, 15, 4, -12, 15, -20, -3, 16, 3, -1, 15, 1, -32, 30, 17, -11, 0, 33, 35, 53, -3, 0, 6, -19, -9, 0, -2, 24, 10, -35, 5, 7, -12, 10, 6, -6, -2, -25, 6, -26, 12, -34, -3, -10, 16, -38, 15, -14, -14, 52, 9, 31, 5, -7, -20, -36, -3, 11, 2, -15, 15, -20, 18, -15, 10, 31, 7, 8, -27, 5, 7, 10, 10, 18, 8, -16, -20, -5, -19, -11, -10, 16, 33, 24, 44, -32, 12, -31, 17, 31, 22, 22, -22, -3, -14, -32, 18, -4, 4, 47, 18, 4, 1, -38, -10, -3, 7, 10, 21, -11, 0, 14, -2, 28, 21, -6, 18, -26, -19, -2, -3, 4, 11, 39, 25, 11, 7, -13, 19, 35, 10, -20, 3, -15, -3, -31, 6, 31, 6, 47, 15, -16, 2, -26, -18, -5, 22, 28, 5, -1, -21, 11, -24, 35, 6, 10, -6, -3, 0, -10, -8, 22, -16, -25, -9, -1, -10, 8, -19, 31, -16, -19, -30, 28, 17, 2, -14, 13, 7, -9, -5, 18, -15, 19, 5, 4, 12, 20, -55, 18, -19, -7, -12, -8, -8, 3, -6, -15, -2, 14, -16, -4, -5, -15, 9, 31, -18, 16, -15, 20, -41, -18, 8, -27, -18, -10, 15, 8, 19, 31, -5, 17, -10, 13, -17, -17, -1, 24, -1, 2, -13, 3, -12, 23, 9, 2, 28, -11, -15, -8, -16, -6, 13, 21, -35, -5, 3, 7, -7, 15, 20, 0, -8, -4, 18, 0, 9, 9, 5, -22, 16, 8, -3, -24, -6, 10, -4, -23, -14, -5, 9, 2, 16, 4, -36, 13, 1, 18, 7, 32, 12, -16, 26, -6, -4, -6, 14, -10, -8, 5, -12, -7, -22, -7, 1, -29, 7, 11, 20, 1, 14, -27, -13, 20, -23, -17, 13, 4, 7, -17, 2, -23, -6, 7, 24, 11, 5, -12, 14, 0, -3, 6, 11, -24, 2, -16, -22, -15, -20, 24, 11, 1, -3, 16, -6, -2, -22, 25, -21, -14, 14, 6, -18, -10, 12, 8, 2, 21, 24, -23, -23, -13, -17, -8, 20, 16, -1, 20, -5, 5, 8, 2, 31, 8, -36, 7, 14, -36, -11, 8, 5, 25, 25, -17, 4, 12, 4, -15, 3, 4, -3, -20, 14, 7, 1, 21, -9, 35, -3, -30, 19, -5, 12, 19, 0, 15, 11, -3, -5, 7, -15, -9, -11, 16, -2, -3, -7, -5, -17, -3, -19, -4, -7, 5, 16, -20, -23, -9, -19, -9, -3, -2, 12, 14, 19, -8, 22, 17, 5, -13, -10, -24, -6, -5, -9, -3, -11, -7, 1, 19, -12, -10, -4, 24, -27, -19, -12, -12, 2, 2, 6, 23, -29, 0, -7, -21, 5, 8, 9, -13, -3, 8, -9, -6, 3, 8, 2, -28, 12, -18, 16, -8, -12, 0, 29, 10, 17, -31, 15, -23, 15, 28, -25, 14, 9, -6, 14, 6, 19, 31, -31, 32, 11, 6, -11, 8, -9, 10, 21, -3, -28, -33, 13, 9, -17, 9, 2, 7, 11, -25, 4, -9, 1, -4, -4, 1, -15, -3, -17, -4, 1, 18, -13, 27, 14, -5, 1, 7, 2, -9, 28, 0, 5, -35, -13, -8, -20, 40, 11, -11, 5, -21, 1, -2, -23, 28, 29, -12, 6, -20, -19, -11, 12, 8, 25, 29, -12, -18, 11, 20, -9, -2, -19, 29, 13, 1, -17, -19, -20, -22, -17, -19, -14, 0, -15, -31, -10, 10, -24, 23, 8, 22, 9, 15, -10, 0, -17, 9, 1, -18, -8, 6, -6, 44, -2, -6, 16, 11, 4, -25, 14, 11, 6, 6, -9, -15, 13, -7, -12, 2, 0, 11, 32, -11, -1, -14, 9, 25, -16, 16, -29, 4, -5, -3, -10, 4, -5, -2, -33, 18, -1, 12, -7, 17, -11, 36, -9, -8, 15, 12, -2, 25, 26, -12, -10, -10, -4, -3, -1, -12, -14, 10, -2, -8, -24, 2, 9, 29, 9, -2, -9, 21, 4, -11, -14, 26, -13, 9, -12, 7, 3, 12, -11, -7, 10, 34, -10, -25, -2, 31, 5, 12, 17, 11, 2, -10, 15, -11, -8, 20, 19, 13, -25, -9, -4, 19, -10, -10, 9, -26, -22, 11, 1, 31, -12, 14, 12, 19, 17, -11, 9, -19, -17, 22, -27, 13, 22, 27, -13, -1, -2, 16, -15, 36, 2, 3, -17, 17, -7, -10, 6, 13, 33, -24, -6, -4, -18, -18, 0, -6, -12, -31, 2, -23, 12, 19, 3, 29, 3, -17, 14, 17, 19, 2, 11, -6, -22, -31, -23, 4, -19, 6, -4, -2, -8, 5, -13, -13, 11, -5, -14, -17, -12, -2, -6, -12, -16, 44, -10, 21, 22, 16, 6, -3, 5, 21, 9, 6, -27, 11, 9, -13, -15, -1, -22, 4, 4, -41, -8, -15, -14, 32, 19, 33, 18, -6, -20, -7, -19, 38, 4, -13, -1, -14, 16, 1, -21, -6, 32, -14, -16, -15, -10, -21, -20, -8, -40, 32, 14, -23, -17, -27, 3, 28, 34, 4, 16, -15, 10, -14, 11, 7, -25, -3, 11, -10, 15, 12, -22, 15, -7, -2, -9, -4, -8, 4, -12, 10, 11, -6, 12, 27, -8, 7, -21, 3, -3, 34, -2, -2, 14, -14, 7, 12, 3, 11, -35, -5, -9, -40, 19, 1, -14, 26, 40, 2, 14, -5, 16, -10, 7, 29, -5, 16, -12, 9, -17, -29, -25, 9, 40, 14, -12, -21, -20, -6, -21, 8, -21, -6, -1, -1, 17, 21, 23, 15, 11, 9, 15, -4, 9, 5, -3, 18, -29, 16, -3, -8, 0, -16, -16, 21, -2, -3, -17, -15, -21, -5, -3, 25, 36, 15, 14, 25, 3, 5, -30, -27, 14, 20, -5, -1, -17, 7, 21, 25, 15, -9, 16, -24, -21, -15, 18, 14, 0, 22, -3, -14, 2, -16, 14, -12, -5, 21, 0, 33, 6, 7, 11, -5, 2, -16, 5, 12, -18, 22, 10, 28, 11, -6, 0, 9, -13, -5, 12, -2, -17, 18, -8, -4, 0, -5, -23, 5, -34, -10, -3, -13, 18, -20, -1, 0, -12, -10, -5, -17, 13, 15, 6, 33, 11, -13, -4, -17, 7, -10, -4, 12, -19, 3, 8, 15, -14, 1, 2, -7, 7, -22, 8, 24, -5, 48, 8, 13, 19, 20, 19, -18, 13, 10, 14, 16, -25, 14, -1, 20, -2, -14, 16, -10, 28, -13, 4, -11, -18, 4, -22, 4, -19, -6, 17, 11, 5, 10, -5, 9, 27, -6, -18, 12, 13, -39, -5, -3, -1, 34, -18, -18, -6, -9, -12, 17, 45, 12, -7, 21, -5, -2, -5, -9, 3, 19, 0, -15, 9, -5, -10, -26, -28, 22, -13, 5, 16, 12, -3, -14, -21, 2, -2, 17, 8, 5, -5, 18, -1, 10, -23, 1, 3, -40, 11, -12, 16, 15, 2, -1, -3, -18, -13, 4, 2, 24, -11, 25, 5, 31, 20, -18, -15, -27, 2, -22, 10, 12, 12, 24, 27, -15, 4, -1, 11, 8, 17, -14, 19, -2, 2, -10, 15, 36, 22, 3, 16, 21, 15, 12, 1, 12, 36, -5, 37, 7, 18, -4, 4, 1, 5, 14, -33, -18, 5, -15, 3, -16, 12, -14, 6, -6, -12, -32, 4, 8, 3, 1, 37, 11, -22, -5, -13, -31, -10, -15, 1, -3, -11, -4, -15, 16, 17, 7, -6, -13, 0, -37, 11, -6, 13, 9, -16, 4, -24, 12, -12, -6, 27, -17, 6, 16, -5, -39, -19, 9, 9, 27, 22, -6, 17, 14, 2, 9, 13, 21, -5, 10, -22, -13, -18, 14, 7, 15, 5, 3, -6, 6, -16, 13, -8, -3, 10, 17, -11, 30, 4, 8, -19, 11, -5, 23, -15, -5, 19, -41, 10, -11, 15, -4, -3, 2, -15, -14, 22, 12, -15, -17, 19, 3, -22, -13, -26, 8, 0, 49, -9, -9, 19, -22, 6, 2, -16, 26, -8, 3, 9, -15, -21, -20, 10, 17, -1, 14, -9, -25, -34, -22, 26, 23, 12, -7, 3, 2, -8, 7, 10, -2, -22, 16, 12, -5, -9, -2, -19, 7, 0, -3, 20, -14, 0, 20, -5, 13, 6, -25, -4, -23, 6, 16, 12, -12, 0, 18, -7, 31, 18, -30, -15, 6, 7, 21, -15, 7, -12, 4, 3, -24, -23, 20, -10, 6, -6, 0, -2, 14, 10, 15, 0, -10, 11, 13, 15, 7, -15, -2, -18, 43, 16, -15, 7, -17, -15, 22, -5, -18, 12, -2, 6, 11, -19, -13, -5, 11, -21, -9, 23, 15, -8, 7, -6, -20, 5, 20, 0, 3, -10, 13, 18, -11, -26, -18, -9, -13, 13, 2, -9, -3, -10, 1, -2, 6, 19, 15, 12, 19, 25, 3, 22, 33, -16, 0, -15, -29, 1, 12, 4, 19, -11, -16, 3, 15, -3, 21, 13, -5, 19, 18, 15, 14, -13, -26, 0, 9, 19, -17, 1, -45, -16, 15, -28, 1, -1, 2, 5, -6, 0, 8, 7, -5, 19, 9, -10, -12, -14, -13, 5, -6, -9, -29, -19, -17, 4, 25, 21, 12, -15, 3, -8, -30, -16, -11, 10, -8, 1, -21, 4, 5, 6, -14, -12, -2, -17, 39, 6, -1, 10, -27, -3, 14, 9, 10, -20, -2, -7, 12, 15, 28, -9, -19, 16, 3, 18, 17, 24, 3, 3, -13, 2, 38, -15, 4, -28, 16, 3, -25, -20, -5, -29, 6, -11, 20, -15, -6, -15, -11, -18, -23, 11, -9, 3, -9, 5, 27, 13, 16, -7, 17, -19, 36, -22, 19, -10, -44, 14, -21, -16, 20, 14, 5, 18, -16, -4, -3, 3, 13, -8, -39, 18, 26, 8, 1, 12, -24, -8, 15, 13, 17, 3, -13, 13, 2, 5, -16, -22, 5, -12, 19, -17, 12, 14, -10, 5, 8, -10, 8, 19, -21, 4, 1, 11, 15, -30, -15, 4, -2, 2, -8, -12, -34, -5, 8, -17, 9, -19, 0, -9, 3, -26, 6, 19, 20, 18, 10, -23, 20, 20, -5, -7, -26, -7, 10, 3, 12, -19, 25, -15, 11, -22, -29, 5, -7, 3, -9, -7, -5, 15, -2, 18, -7, 10, 18, 6, 19, -12, -8, 11, 14, -8, 25, 9, 22, 11, -2, -4, -30, -21, 4, 7, 3, 6, -36, -33, -13, -22, 29, 8, -10, -20, -10, 17, -27, -20, -26, -2, -18, -8, 24, 8, 20, -17, -13, -5, 1, 13, -21, 11, 22, 37, -15, 17, -22, 18, 11, 17, -8, -26, -4, -5, 22, 6, 8, -9, -1, -15, 53, -13, 3, -20, -23, -8, 18, -13, 7, 3, 14, -2, -11, -3, 18, -6, -20, -15, 36, -8, 27, 33, 4, -16, 11, 14, -7, 5, 15, 18, 3, 12, -33, -4, 22, -1, -8, -2, 5, -4, -3, -9, 1, 2, -11, -15, 26, -17, -9, -13, 25, 19, 5, -8, 15, -5, 18, 9, -2, -4, -19, -1, -3, -9, -12, 19, 12, -13, 4, 5, -24, -33, 28, 0, 1, -13, -3, 11, 13, -19, -3, -3, -31, 18, 6, -17, -11, -17, -3, -3, -22, 9, 1, 12, 2, 9, 28, -20, -1, -25, -6, 10, 11, 13, -1, 13, -7, 7, 6, 4, 16, 18, 6, -6, -30, 12, -14, -4, 6, -33, -27, 12, 19, -16, 7, 0, -32, 12, 4, 19, 28, -10, 14, 19, -45, -2, 13, -13, -12, -7, -1, -16, 40, 8, 8, -12, 14, -12, -6, 11, 19, 14, -2, 3, 21, -1, -5, -8, 13, -4, 51, -6, -19, 20, -40, 5, 17, 9, -46, -15, 11, 16, 27, 29, 4, 3, -12, -1, -12, 7, 4, -4, -21, -13, -6, -9, -5, -10, -6, 2, -3, -10, 9, 3, 10, -12, -9, 22, 24, 22, -16, -6, -1, -22, 5, 25, -46, -13, 9, -19, -45, 15, -1, 17, 42, 51, 19, -19, -9, 11, -10, 8, 7, 2, -10, -8, 7, 13, 21, 0, 3, -27, -25, 18, 4, 4, 27, 31, -8, 19, 18, -2, 3, -16, -11, 4, 17, 13, -40, -20, -34, -10, 34, 51, 23, 7, -15, 8, 15, -6, -32, 12, -23, -9, 20, 10, 2, -26, -5, -16, 28, 34, -5, 11, -14, -3, 1, 16, 43, 38, 0, 8, -58, 19, -30, -4, 21, 9, 10, 13, -6, -23, 7, 4, -5, 4, -20, -4, -3, 0, 13, 24, 12, -8, -23, -17, -23, -2, 13, -26, 15, -17, -20, 16, -1, -9, 4, 11, 17, 3, 7, 22, 32, 0, -18, 25, -50, -3, 8, 4, -42, -9, 4, -5, -1, 10, 26, 3, 15, -6, -24, -19, 19, 11, 17, 7, -10, 13, 6, 20, -18, -24, -2, -13, 19, -11, -36, -12, 19, 10, 10, -20, -10, -19, 1, -28, -23, 12, -12, 11, -25, -13, 36, 4, -28, -7, 6, -5, -4, -3, 4, 39, -16, 19, -13, 6, 10, 9, -23, 4, 12, 17, 17, -9, -11, -19, 16, 24, 28, 21, 9, -12, -10, 16, -15, 20, -10, -20, 19, -4, 26, 13, -9, 3, 23, 9, 15, -3, 15, -4, -18, 19, 15, 29, -32, -1, -6, 11, 41, -3, -29, 11, 31, -13, -16, 7, -40, -28, -14, 5, 19, -17, -8, 3, 24, -10, -9, 6, -3, -7, -20, 18, 5, 16, -12, -2, -26, 12, 16, -4, -14, 12, -8, -23, 13, 16, -19, -16, -5, 0, 2, 6, -13, -14, -6, 18, -20, -31, 7, -9, -17, -1, 16, 17, -1, 6, -16, -16, -23, 17, 5, -23, 18, -8, -13, -7, -2, -14, 3, 3, 3, 16, -3, 2, -3, -19, 19, 9, 0, 29, 5, -3, 40, -16, 9, 2, -42, -19, 22, -11, -12, -19, 4, 11, -2, -31, -16, 18, 15, -11, 19, -14, -29, 35, -11, 18, -13, -11, 6, -12, -23, 0, -1, 21, 28, -16, 1, 2, -40, 43, 2, 12, -25, 3, 12, 16, 8, 39, -25, 8, -38, -1, -13, -19, 16, 26, 2, 6, 23, -11, -6, -11, 5, -6, -14, 15, 8, -10, -3, 5, -11, -27, 5, 61, -2, 15, 9, 19, 11, 14, 5, -14, -12, -3, -3, 19, 7, 37, 9, 27, 5, -7, -5, 3, 7, -18, -21, 25, -9, 9, -4, 12, -4, -10, 13, -16, 1, -12, 16, 16, -26, -14, -12, 19, 7, 6, 3, 5, -16, -21, -18, 17, 22, 9, 24, 18, 9, -5, -4, 7, -3, 12, 21, -22, -22, 2, 11, 10, -13, -16, 17, -7, -38, -1, -34, -29, 24, 5, 25, 16, 3, -24, 9, -17, 1, -4, 11, 15, -19, -5, 7, 20, -3, -7, -10, -20, -26, 5, -22, 19, -6, -13, -13, -21, -28, -10, 25, 27, 22, -13, -19, 18, 8, 22, -14, 17, 10, -14, 13, -1, -20, 8, -27, 13, 27, -6, 16, 11, -2, 17, -30, 6, 24, 15, -11, 16, -22, 28, 3, -38, 27, -18, 17, -4, 3, 4, 4, -6, 42, 15, -21, 14, -18, -10, -16, -8, -7, 3, 8, -22, -4, -13, -17, -12, -25, -6, 14, -19, -10, 22, -11, -21, -7, -25, 12, -4, 4, -7, -27, -4, -20, 11, -2, -3, 38, -9, -5, 0, -21, -17, 18, -15, 39, -10, -7, -7, 9, -26, -27, -18, -16, 10, -7, -16, -19, -25, -15, 3, -8, -10, -18, -10, -10, 14, -6, 5, 23, 4, 15, 11, -11, 8, -10, 3, 13, 20, 2, 7, -6, 3, -31, -5, -18, -3, 32, -16, 5, -22, -3, 0, 7, -15, -1, 5, -2, -13, 28, -7, -17, -6, 10, 19, -21, 8, -28, 16, 24, -2, -17, -11, -12, -8, -13, 11, 2, -16, 0, 30, 19, -16, 17, -12, -1, -11, -28, 3, 5, -17, -27, -2, 4, 16, 21, 29, 4, 2, -29, -1, -7, 23, -14, 30, -3, -12, 50, -24, -22, -5, -33, -5, -8, 1, 0, -4, -39, -15, -21, -6, -10, 4, 17, -12, -24, -18, 21, 1, 10, -13, -27, 0, -21, 25, 17, -5, 13, 18, -2, -23, -6, 15, 7, -17, 0, -18, -3, -25, 13, -5, 20, 22, 17, -4, 4, -3, -60, 0, 19, -22, -22, -8, -7, -13, -32, -4, 4, -2, -9, -4, 11, -5, -2, -7, -27, 14, -15, -3, -3, 13, 15, 3, 7, 24, -21, -12, -5, -6, 6, 5, 7, -23, -6, -15, 3, 9, 30, 29, 12, -7, 32, 14, 12, 10, 13, 1, -19, 5, -10, -3, 11, 13, -1, 11, 10, 10, -2, -17, -4, 8, -14, -10, 10, 7, -6, 11, -28, 10, 24, -20, 13, -11, 11, -16, 0, -16, -18, 16, 10, -15, 3, -11, -7, 6, 12, 4, -4, 9, 9, 15, 9, -1, -1, 8, 2, 23, 8, 19, 12, 10, -26, -11, -10, 1, -3, -22, -18, -21, -11, -9, 26, 15, 9, 7, -16, 9, 13, 19, -18, 12, 23, -8, -4, -16, 52, 7, 15, -20, 0, -16, 6, -1, -32, 0, -17, -6, 10, -27, 20, 16, -4, 6, 2, -4, 19, -14, -16, -10, 5, -9, 16, -8, -11, -10, 18, -17, -10, -21, 32, -6, -8, 14, 16, 11, -18, 10, -8, -11, 36, -2, 7, 11, 74, -34, 7, -15, -4, -13, 9, -7, -11, -2, 15, 16, 16, 13, 29, -26, -25, -6, 13, 6, -8, 6, 7, 14, -40, 0, 7, -11, 21, -6, 19, -21, -14, -13, 10, 1, -15, -21, 5, -16, -22, 8, -25, -15, -8, -14, -20, -1, -27, 10, 21, -8, 9, -8, -16, -1, 5, 6, 17, -13, 6, -17, -8, 7, 18, 17, -3, -6, -32, 9, 6, 24, 2, -23, -11, -4, 0, -9, 13, 1, 35, 11, -31, -8, -5, -11, 1, -4, -23, 34, 9, 19, 3, -7, -13, 9, -4, -21, -6, -13, -29, -10, -4, -14, 55, -17, 35, 1, 12, -10, 6, -1, 14, 6, -4, 2, 6, -4, -17, 9, -18, -19, -25, 20, 0, 18, 8, -12, 8, 18, 7, 13, 5, 1, -8, -13, 20, -11, 13, -24, 7, 25, -7, 18, 38, 39, -8, -4, 18, -6, 0, -23, 11, -3, 6, -14, -3, 7, -8, 1, -1, -31, 13, -19, -11, -1, 14, 8, -8, 4, 26, 41, -8, -16, 17, 9, -43, -5, 19, -10, -1, -10, 15, 12, 12, 0, -3, 8, 25, -12, 11, -15, 0, 5, 19, -10, -3, 15, 27, 1, 9, 3, 5, 0, 6, -10, 30, -11, 27, 3, 10, -10, -17, 1, -11, -7, 37, 1, -19, -13, 5, -9, 20, 13, 20, -3, 1, -5, -1, -12, 2, -2, 26, -24, -20, -8, 16, -4, -18, 12, 37, 1, -3, 20, -3, 22, -20, -8, 11, -17, 11, 32, 1, 13, -3, -20, 0, -3, -8, -17, 11, 12, -29, -2, 20, -12, 18, -3, 25, -13, -10, -1, 19, -18, 12, 0, 0, 14, -6, -23, -10, 25, 9, -5, -16, -14, 5, -10, 25, -5, 4, -25, -48, -15, -16, -4, -3, -9, 10, -11, -17, -19, -19, -6, -6, -14, -16, 8, 15, 22, 3, -10, 23, -13, 22, -14, -14, 18, -16, -15, 1, -10, -11, -4, -20, 2, -24, 2, -6, 3, 24, 24, 8, -12, -10, 9, 10, -18, -8, -12, -2, -11, 24, 7, 21, 13, 26, -44, 2, 1, -36, 5, 6, 10, 44, 6, 2, -7, 13, -16, 22, 3, -12, 11, -1, 15, 14, 12, 18, 1, 17, 5, 6, -18, 35, -15, 17, -15, 11, 5, 7, -1, -9, -5, 43, 5, -18, 10, -14, 11, 25, -2, -4, 4, -4, -24, -36, 6, 38, 12, -5, 5, 16, 37, -17, -20, -19, -6, -8, 14, 18, 0, 30, -1, -8, -15, -22, -5, 8, 19, 20, 7, -12, 11, 8, 17, 3, 13, -8, -23, 21, -24, 4, -12, 4, -6, 26, 6, -13, -1, -25, 44, 22, -14, -8, -11, -2, -17, 8, 4, -1, 10, 21, 5, 14, 9, 11, -18, 7, 21, -27, 12, 22, -5, 8, 0, 11, -11, 8, -21, 5, -4, 11, -15, 34, 39, -5, 12, 21, 18, 8, -10, 5, -22, 14, -27, 2, -7, 0, -6, 7, -11, 8, 6, -17, 17, -33, 24, 5, 3, -23, -1, 19, -10, -1, -28, -5, 5, -26, 3, 23, 19, 9, 18, 23, -38, -25, 14, -10, -17, -14, -16, 3, -14, 0, 4, -3, -2, 9, 3, 4, 12, -28, 15, 17, -24, 9, 6, -24, 7, -41, -21, -20, -3, 15, -23, 17, 0, -38, 2, 6, 17, -12, 36, 10, 24, 2, 5, 10, 4, 10, 39, 3, 7, 5, -22, 30, -5, -32, -8, 17, -20, -4, -20, -3, -7, -1, 34, 7, -7, 22, 10, 5, -24, -6, -5, -5, 6, 6, -16, 14, -25, -12, 16, -30, 16, -4, -19, 10, -11, -24, 10, -4, -10, -10, -11, 5, -18, -4, 23, -25, -19, 13, -6, 6, -10, 14, 9, -8, 11, -4, 9, 6, -26, 13, -8, -5, 2, 13, -10, -17, 6, -29, -43, 19, -1, -25, -1, -16, -17, -14, 1, 5, 31, 1, -2, 5, 8, -22, -28, 41, -6, -12, -6, 14, -20, -8, -10, -17, 23, 4, -4, 12, -11, -4, 3, 7, 29, -8, -17, -6, 16, 14, 17, -27, -21, -15, 11, -23, 7, -4, 2, -5, -7, 19, -26, 0, -1, 1, 9, 8, 11, -27, -23, 5, -23, -16, -6, 9, 9, -30, 2, 26, 3, 26, -1, 33, 16, 23, -17, 5, -7, 7, 2, 0, 23, -15, -18, -4, 4, 9, 9, 5, 20, 1, 15, -20, 10, 10, -8, -55, 1, 17, -18, 26, -1, 6, -4, 8, -30, -8, -18, 1, -3, -5, 8, -4, -7, 8, 1, -12, -21, -16, 9, 28, -10, 19, -19, -16, 17, 6, 12, -16, -2, -25, 9, 2, 19, 11, 18, 26, -16, 6, -21, -1, -7, 25, -15, -22, 4, -14, -5, -2, 10, -7, -21, 4, 25, -7, -23, -10, -21, 11, 23, 7, 45, 28, -8, 22, 0, -4, -16, 6, -1, -5, -16, 42, 18, 8, 21, -9, -14, 19, 11, 3, 0, 30, -5, 2, 0, -5, 14, -16, -15, 21, -15, -11, 15, -7, 0, 1, -3, -2, -25, 13, -9, -11, -27, -11, 13, -23, -17, 22, 1, 21, -4, 16, 11, 43, -10, 16, 16, 2, -8, -6, 15, -17, 16, 7, -6, 7, 17, 11, -8, 21, 48, -13, -15, -18, 11, 3, -28, 7, 13, -4, -1, 10, -3, 12, -16, 22, -11, -21, 8, 17, 2, 15, 10, 12, 4, -10, -4, 7, 14, -5, -21, -20, -1, -17, 5, 2, -2, -13, 10, -2, 14, 2, 15, -14, -17, -4, -6, -23, -24, 16, 0, -11, -5, 17, -14, -14, 19, -3, -23, -2, -7, 12, -25, 23, 16, -23, 8, 35, -3, 35, 14, 8, 28, -5, 20, 24, -7, -18, 4, -22, 28, 6, -8, -5, -9, 4, 9, 17, 18, -8, 19, -23, 11, 20, 3, -13, -39, 23, 7, -5, -14, 14, 7, 17, 7, 12, 10, -18, -23, 30, -18, -3, 26, -4, -15, 2, 11, 67, -10, 0, 27, -10, 53, 24, -2, 24, 4, 2, -25, -11, 4, -13, 17, 32, -16, 27, 23, 18, -22, 9, 7, -13, 14, 5, 39, 2, 11, -19, 2, 16, -5, 49, 7, 24, -20, 15, -28, 29, 16, 12, 4, 10, 28, 10, 15, -20, 6, -12, 13, 32, -7, -19, -15, 14, -7, -15, 8, -21, 16, 13, -10, 19, -22, 21, 30, 4, 17, -13, 11, -17, -3, -32, 11, -14, -4, -9, -12, -13, -26, 19, 11, 14, -20, 13, 9, 16, -7, 1, -8, 9, -4, 10, -5, 5, 10, 4, -9, 9, 19, 20, -25, 36, 17, 13, 22, -1, 17, 4, 16, -15, 9, 24, -9, 11, 14, -22, 0, 11, -4, 8, 0, 16, 23, 5, -13, 3, -2, 15, -24, -10, -9, 9, -10, 9, 1, -15, -18, 21, 4, 17, 5, 2, -5, -31, 1, -8, -9, 10, -7, 19, 1, -1, 7, 1, -4, -34, -17, -6, 8, -9, 10, -13, -4, -24, 4, 3, -8, 11, 13, -5, 15, 23, 22, -4, -3, -18, 6, 15, 14, 14, -11, -39, 8, 14, 3, -19, 23, 28, 4, 21, -7, -1, 24, 8, 5, 7, -1, -12, 7, -27, -20, -27, 5, 25, -3, 7, -18, 15, -8, -1, -18, 42, 14, 8, -27, -18, 12, 15, 4, -18, 26, 4, -7, 35, -38, 20, 10, -5, -15, 15, -11, -25, 10, -16, -4, -15, 3, 26, -22, 5, 11, -25, -8, 2, -2, 22, 1, 30, -4, -8, 0, 35, 11, -21, -22, -1, -14, -18, -1, 19, 5, -14, -16, -13, -5, -4, -2, -9, 12, 1, -8, 4, 19, 0, 14, 25, 4, 16, 0, -14, -29, -10, 0, -20, 4, 9, 5, -11, -22, 5, -8, 31, -12, -6, -22, -20, 1, 28, 6, -2, 16, 8, 17, -2, -6, -8, -36, 7, 16, 32, -22, 22, -3, -1, 8, 0, 3, 19, -18, -12, -9, 15, 12, 35, -15, 5, -17, 1, 19, -25, -4, 16, 23, 12, -21, 13, 20, -19, 21, -12, 5, -7, 5, -15, -30, -1, 14, -13, -8, 1, 14, 6, 4, 18, 5, -3, 19, 13, 9, 12, 13, 4, -12, 40, -25, 6, -20, 30, 10, 22, -14, 43, 5, -12, -18, 2, -18, 12, 7, 38, 10, -24, -1, -18, -4, 25, -2, 0, 7, 10, 16, -3, -3, -18, 2, -17, -16, -14, 6, -12, -20, 11, -45, -16, 15, -22, -16, 18, -7, 17, -31, 47, -7, -2, 12, 18, -2, 10, -21, 15, 3, -10, 15, 8, 8, -36, -15, -8, 0, 11, 18, -14, 15, 26, -32, -12, 15, 1, 11, -7, 10, -22, -20, -29, 7, -40, 14, 16, -29, 14, -17, 29, -22, -22, 6, -2, -3, 14, -12, -11, 2, 9, -3, 3, 19, 26, 14, 28, 8, -13, 5, -3, 1, 10, -18, 24, -10, 24, -9, 11, 21, -5, 23, 11, 11, -29, 1, -3, 8, 32, -20, -7, -4, -23, 14, 16, -9, 2, -21, 9, 4, 3, -17, 11, 4, 7, -15, -7, 10, 13, 14, 8, 11, -18, 9, 4, -7, -7, -15, 15, 0, -17, 17, 46, -23, 20, -10, 14, 3, 24, -17, 6, -4, 25, 10, -10, 4, -9, 17, -4, -17, -41, -10, -11, 24, -3, -3, 10, 19, -11, 18, 6, 45, 11, 3, -6, -14, -17, 15, 19, 26, 6, 0, 33, -21, 4, 9, -20, -24, -15, -2, 24, -2, -13, -23, 4, 6, -14, 2, 4, 8, 10, 3, -17, -2, 12, 5, 12, 9, 15, -16, 18, 19, -18, -6, -30, 23, -4, 3, 5, 14, -13, 31, 8, 3, -20, 9, 17, 26, -2, 4, -4, -5, -9, -11, 4, 18, -23, -29, 2, 12, 6, -22, -16, 6, -1, -27, 9, 10, -5, -21, -11, 17, 16, 20, 22, -10, -4, -20, 14, -24, -20, 16, 19, -16, 26, -1, 1, -11, 0, -19, -1, -6, 4, -19, 10, 19, -10, -4, 6, -9, -8, 0, -20, 6, -6, -14, 27, -17, -19, -6, -13, 16, -8, -2, -17, -14, 17, -5, -26, -1, -15, -15, 0, -23, 5, 17, 20, -8, -6, 12, -8, 7, 10, -3, 13, -11, -4, -10, 9, -17, 9, -12, -15, 21, -11, 21, -24, -21, 26, 5, 1, 9, -29, 16, 23, 9, 2, -21, 4, -4, 16, -22, 3, -24, 16, -19, -20, -17, -10, -4, 18, 0, 1, 2, 28, -4, 11, 12, 15, -1, -29, 15, -2, -14, 24, -31, 1, 17, 3, 4, 16, 7, 18, 3, 1, -13, -3, 12, -1, 9, 1, 12, 14, -8, -25, -14, 3, 7, 2, 6, 10, 15, -4, 0, 7, 8, 2, 20, 9, -19, -4, 2, -17, 6, -8, -34, -3, 0, 0, -2, -24, 27, -17, 2, -14, -8, -8, -1, 8, -10, -22, -2, 23, -9, 6, -7, -17, 22, -27, -12, 14, -14, -20, 19, 16, 51, 17, 22, -1, -16, 23, -20, 11, 20, -19, 17, -16, 10, 29, -21, 17, -1, 17, 45, -9, 1, -13, 7, -26, 1, -22, 19, -12, 0, -14, -19, -12, 9, -11, 13, 26, 15, -2, 7, -5, -11, -17, 68, -12, 9, -17, -24, -17, 25, -4, 27, 21, -22, 3, 1, 3, 5, 13, 25, -27, -20, -10, 10, -11, 24, 10, -22, -4, -24, 19, -9, 19, 1, -8, -7, -6, -7, 21, -19, -23, 28, -7, 30, -7, 3, -16, -22, 15, -12, 7, 44, -3, 0, 1, -8, 2, 20, -7, -42, 12, 14, 14, -19, -33, 20, 17, 20, -2, -10, 23, -3, 3, -25, -1, 22, -21, 6, -11, -16, 4, 2, -20, -12, -11, -3, 18, 0, -3, -20, -4, 1, 12, 16, 16, -9, 0, 0, -26, 0, -53, -5, -6, 13, 30, -4, 4, -21, 10, -4, -42, -10, 22, 16, -9, -15, 10, 19, 19, 5, -5, -2, -17, -1, -29, -17, -6, -24, 6, -16, -12, -2, 54, 9, 0, 5, 3, -22, 32, -23, -10, -15, -2, 13, -9, 11, 22, -16, -30, -22, 26, 1, -29, -5, -17, 11, -22, 11, 10, -7, 0, 18, 24, 22, -9, 15, 23, -8, -11, -15, 11, -11, 4, 1, -36, -1, 9, 24, -13, -3, -14, 1, -3, -8, 1, 2, 13, 6, 10, 19, -23, 16, -12, 33, -3, -16, -19, -19, 4, 7, -9, -17, 9, -3, -8, -3, 25, 4, -13, -14, 13, 8, -39, -11, 17, -15, -20, -19, 15, 23, 16, -8, -16, 10, 13, 5, 28, -2, -33, -6, 8, 7, -10, 3, -20, 16, -14, 14, -2, 9, -22, 26, 10, -20, 29, -16, 3, 1, -1, -8, 6, 16, 15, -9, -5, 4, 23, 20, -18, 6, -30, 9, 35, -22, -14, 18, -20, 3, 12, 10, -48, -10, -20, 8, 23, -23, -31, -7, 9, 13, 8, 21, -4, -2, -17, -23, -1, -21, 6, 14, -17, 9, 28, 11, -9, 1, -29, -5, -12, -10, 3, -21, 16, -17, 18, 22, -22, -9, -51, -24, 9, 2, 7, 27, 22, 1, -8, -17, -1, -3, -3, -22, 8, 0, 38, 2, 8, 3, -2, 1, -15, 3, 6, 14, 58, 15, -8, 6, -34, -15, 6, 13, -48, 20, -20, 4, 9, 18, -8, 18, -10, -6, 6, 20, 10, 4, -24, 25, 21, 3, 1, -14, 7, 11, -23, -22, 9, -21, 17, 16, 5, -16, -4, 6, 6, 16, 17, 19, -1, 2, -37, 3, -36, -13, 38, 15, 4, -10, -8, -8, 28, -21, -10, -13, -1, -18, 1, -15, -17, -17, -4, 1, 0, 5, -35, -6, -47, 2, -9, 22, 28, 14, -5, -6, -54, -14, 12, 4, 31, 12, -13, -20, 19, 19, 2, -29, 20, -9, -36, -19, -28, -1, 25, -9, -6, -17, 13, 11, -10, -18, 9, 10, 29, -4, -20, -3, -24, -22, 14, 1, -2, -16, -11, -2, 32, -9, -8, 15, 16, 12, 17, -14, -46, 9, 0, 0, 6, -4, 16, -20, -1, 9, -20, 19, -11, 0, 16, 6, -9, 15, -10, 3, -25, -12, -16, 1, -31, -7, -44, -20, 8, 13, 0, -12, 28, 1, -3, -11, 0, 15, -43, 0, 11, 0, 6, 21, 12, -5, -13, 11, -19, -13, -15, -5, -7, -11, 9, 9, 11, -6, 0, 2, -6, 17, -5, -2, -8, 18, 13, -24, 1, -7, 25, 13, -31, 15, 1, -32, -21, -12, 14, -18, -30, -13, -22, -5, 15, -17, 19, 3, -10, -11, 7, -21, 16, -1, 13, -12, 24, -4, -13, 7, -23, 0, 43, 9, -10, 1, -9, -13, -23, 14, -15, -4, -29, 10, 11, -6, 6, 2, -12, 14, 5, -6, 13, -13, 13, 6, -21, -15, 25, -16, -14, -22, -5, -2, -26, -12, -46, 25, -19, -22, 7, 16, -10, -18, -42, 8, 8, 4, -2, -1, -11, 12, 18, -3, 17, 6, -16, -22, -36, -6, 6, 18, -16, 16, -13, -13, 10, 11, 1, -19, 10, -14, -12, -7, -13, -17, -26, -21, -4, 27, -4, 4, -7, -10, -33, 4, 9, -6, -18, -15, -11, 13, 17, -17, -11, -2, 18, -1, 23, 17, -23, 16, -2, 9, -4, 4, 17, 10, 4, 14, -25, -7, 9, -12, 22, 18, -17, -20, 19, -13, -5, -15, -7, -4, 28, -19, 2, -7, 6, -3, 5, -2, -26, 4, 19, 27, 1, -8, -16, -12, -9, -14, -2, -3, -12, 14, 3, -20, -7, -6, -33, -2, -5, -3, 29, -18, -17, -10, -16, 8, -3, -8, 13, -18, -21, 7, -6, -8, 10, 7, -14, -15, -12, 2, -15, 3, -28, -2, 11, 17, -34, 12, 8, 9, 0, -13, 47, 10, 2, -14, 38, 11, -6, 0, -8, -11, -5, -2, -42, 16, -3, 0, -16, 8, -17, -18, -14, -9, 15, -12, -17, -22, -15, -2, -24, -13, 8, 3, 6, 0, 22, -21, -11, 1, -5, -6, 52, -2, 0, -15, 8, 19, 27, 6, -1, 1, -29, 9, -1, -21, -28, 1, 22, -12, 5, -15, -4, 3, -32, -17, 0, -17, -3, -4, 0, 10, -14, -13, -13, -1, 14, 10, -30, 1, -2, 17, -36, -6, -6, 13, -36, -31, 11, 15, 18, -22, 27, -8, -10, -6, -19, -8, -4, 0, 0, -20, -3, 12, -7, -12, 20, -16, -5, 9, 19, -16, -26, 2, -23, 1, 20, -14, 34, 30, 34, 9, 5, -10, 22, -20, -23, 1, -7, -7, 15, -8, -18, -13, 25, -4, 2, 2, 16, -18, -18, 15, 1, -14, 1, 16, 16, -8, -7, -13, -12, -30, 7, 6, -10, -18, -16, -11, -43, -6, -17, -10, -13, -5, -9, 6, 21, -8, 20, 29, 14, -20, 18, -16, 26, -5, -7, -3, 10, 17, -12, -10, -16, 1, 12, 7, -20, 15, -20, -17, 0, -18, 1, -11, -17, 19, 14, 1, -21, 11, 11, 7, 8, -8, -13, -1, 20, -13, 17, -8, -13, 14, 13, -18, -3, 15, -36, -16, -12, 4, -8, 7, -5, -18, 3, 23, -5, 11, 6, 5, -10, -3, -12, 7, -19, -7, 21, 7, 15, -5, -12, 13, -18, -14, -7, 23, -20, -9, 14, -24, 5, -1, 19, -5, -33, 11, 11, 31, 0, -8, -18, -28, 1, 23, 25, 10, 3, -11, 1, -24, 39, 27, 10, -11, -18, -20, -5, -10, 11, -9, 3, 5, 11, -10, -8, -3, 22, 22, 12, -2, 7, -15, -15, -44, 9, -11, 5, 8, 9, -11, -18, 24, 8, -11, 1, -22, -11, -11, 3, 6, -3, 8, -5, 15, -10, 13, -5, -1, 17, 26, -21, -1, 10, -3, 0, -3, 17, 15, 0, -3, 17, 10, -9, 18, 2, 18, -15, 27, 2, -8, -18, 7, -11, -2, -26, 1, -4, -17, 4, 7, -13, 10, -35, -3, -2, 13, 18, 25, -39, 29, 19, 29, -17, 6, 8, 29, -32, 2, 5, 0, -9, -20, -14, 3, -3, 6, 5, 20, -22, -11, 2, -28, 3, 17, -22, -14, -17, 9, -17, -5, -2, 6, 5, 27, -12, -21, 4, 0, -16, -1, -32, -20, 6, 13, -14, -9, 22, 1, 0, -14, -21, 17, -18, 4, -22, 14, -10, 0, -2, 13, -19, 9, 14, 18, 3, -21, 13, 10, -8, 7, 7, -16, 10, -4, -11, -10, 2, 19, -44, -8, -25, -20, -9, -10, -14, 3, 25, 19, -2, -17, 13, 0, -15, 1, 19, -20, 28, -23, 0, 8, 6, 3, -31, 15, -4, -19, -9, -3, 4, 0, 13, 10, -10, -34, 10, 13, -1, 9, 17, 2, -27, 15, -17, 16, 8, 6, -47, -45, 4, -15, -14, -20, -19, -5, -17, 15, -13, 27, 12, 5, -2, 11, -14, -40, -2, -1, -11, -16, 16, 36, 2, 7, -23, 15, -1, -22, 11, -8, -11, -4, 0, 13, -10, -11, -24, -1, -8, 5, 11, -5, 6, 7, -25, -1, 9, 45, -22, -1, -14, 15, -15, -6, 19, 36, -22, 2, -21, 1, 18, -4, 15, 8, 19, 25, -2, 9, 17, -6, -2, 38, -22, 7, 4, -21, 3, -4, -27, -29, 26, 28, -18, 2, -21, -14, -23, -3, 15, 2, -5, 16, 13, 8, 0, -10, 16, 10, -4, -12, -4, 6, -32, 14, -4, 5, 16, -17, 3, 13, 15, 21, -20, 11, -15, -13, 5, -25, 15, 10, 12, 11, 5, 11, -14, 15, 19, 11, -16, -1, 3, -16, 5, 19, -8, -22, -26, -32, 9, 20, 4, 1, -21, -19, -6, -4, -19, -3, 10, 12, 4, 0, 15, 22, -17, -4, -13, 2, -12, -22, -37, 4, -2, 11, 6, 16, -32, 10, -15, -3, 14, 3, -16, 17, 16, -5, -22, -11, -8, -6, 11, -13, 13, 20, 15, -4, 21, -1, -18, 2, -6, -38, -25, -2, -7, 25, -12, 5, 15, -1, 2, 14, -14, 0, -3, 6, 5, -15, -5, -15, 4, 17, -13, -13, -11, 3, -27, -30, -3, 14, 8, -18, -2, 5, 17, -2, -5, -3, 18, 14, -36, -11, 24, -3, -15, -16, -14, 9, -14, -23, -27, -18, 16, 15, -17, 25, -17, -19, -29, 2, -14, 11, 12, -19, -41, -33, 21, 24, 2, -4, 11, 8, 16, -30, -4, -21, -5, 16, 15, -18, -24, -54, 11, -16, -9, 18, 14, -3, -31, -20, 18, -14, 15, -22, 0, -6, 2, -18, -6, -5, -4, -13, 18, 14, -13, 15, -58, -14, 8, 23, -14, 1, -1, 14, 15, -25, -20, 10, 17, 33, -27, -20, -13, 4, 14, 1, -13, 6, -4, -20, 15, -12, -22, 7, -14, 7, -17, -16, -31, -14, -7, -13, -3, -22, -29, -43, -25, -19, -8, 13, -7, 9, -7, -20, 20, 33, -6, 7, -13, 7, -7, -6, -11, 0, -14, -33, 9, 7, -12, 25, -5, -27, 2, 13, 7, 14, -23, -4, -27, -16, 10, -27, 10, 13, 7, 8, -46, -31, -8, -32, -20, -19, -8, -18, 10, -17, 5, -12, -22, -24, -17, -14, -21, -39, -2, 16, -11, -3, -3, -13, -24, 39, 20, 6, -1, -12, 21, 24, 9, -3, -26, -15, -15, -5, -9, -4, -3, 9, -7, 6, 4, 4, 23, 3, 13, 10, -12, -9, 9, -7, 26, 2, -12, 9, -5, 29, 16, -20, -54, 4, 3, -21, 13, -13, 3, -9, 17, 2, -16, -4, 19, -18, -15, 0, -9, -9, 1, 14, -3, -5, 3, -9, 7, 2, -28, 1, 12, -25, -3, 2, 19, 0, 10, 27, -23, 4, -19, -22, -6, 3, -11, 16, -11, -19, -9, 0, -7, -17, 23, 3, 7, 6, -17, -16, -7, 4, -6, -19, -20, 3, -1, -2, -19, 27, 18, -4, 13, -20, 0, -2, 11, -10, 18, -4, -2, 10, -3, 22, -5, -13, -13, -1, -21, -6, 13, -1, -7, -8, 28, -15, -2, -3, -22, -35, 8, 15, 10, 19, -10, 17, 6, -12, 33, -26, 12, 16, -5, -25, 0, -11, 26, 9, -16, 15, 15, 5, 19, -6, -9, 21, 12, 19, -14, -16, -10, -5, 18, -10, -3, 7, -23, -3, 12, 16, -9, 21, 3, -41, -19, -18, -11, 14, 6, -5, 22, 1, -9, -3, -14, -12, 3, 8, 14, 4, -20, 0, -23, -6, 3, 10, -3, -22, -3, -3, -10, -9, -15, -21, 27, -13, 6, 14, 15, 11, -19, -18, -7, 25, -6, 12, 16, -1, -18, 14, 18, 16, -18, 14, 16, 6, 34, 7, -24, 2, -17, 14, -20, -8, 6, 21, 24, 4, 16, -17, -13, 14, 4, 16, -3, -23, -3, -2, -13, -15, -23, -2, -4, -27, 3, 28, 15, 21, -15, -18, 16, 20, 17, 4, -4, 20, 1, -6, -10, 17, 17, -13, -15, 28, -5, -7, -1, -13, 11, 1, 16, 20, 25, -29, -9, 4, -2, 8, -15, -19, 1, 0, 8, -5, 22, 5, -19, 24, 18, -18, -11, -5, 16, -37, 6, -19, 18, -7, -2, -7, -7, -11, 11, -3, -18, 5, -4, -4, -6, 7, -5, -11, 4, 16, -9, 8, 18, -18, -10, 7, 2, -4, 7, -3, 5, -5, 3, 9, 20, 19, 11, -2, -11, -4, 11, 8, 13, 19, -26, 14, -19, -10, -8, -2, 7, 1, 11, -26, -2, -24, -5, 11, -14, 9, -8, 6, 3, 13, -10, 7, -12, -26, 8, -3, 1, -6, -8, 3, -21, -18, 6, -14, 3, 15, -28, -14, -7, -23, 22, 13, -13, -1, -10, -13, 13, -4, -5, -14, -8, 19, 9, -8, -6, 13, 1, 3, 18, 8, 7, -33, -22, 16, -10, 2, 3, 2, 7, 3, -46, -30, 31, 19, -1, -23, 2, -28, 7, -5, -17, -7, 7, -5, -18, 14, 32, -20, 14, -13, 14, -28, -4, -1, 26, 12, 16, -21, 3, -11, 9, 7, 38, 11, 42, 17, -3, -14, -18, -33, -8, -18, 14, -16, 19, 6, -1, 24, 20, -23, -3, 16, 14, 2, 3, -19, -22, -22, 32, 1, -8, -36, 18, 3, -25, -6, 12, -4, -9, 0, -15, 19, -20, 14, 2, 26, -25, 23, -1, 5, 1, 1, 0, 31, 8, -8, -1, -10, -8, -31, 13, -6, -21, -9, 12, -13, 15, 25, -1, 3, 2, 14, -12, 15, -35, 18, 32, 23, -8, -4, -13, -5, -2, -4, -21, 14, -11, -6, 16, 3, -11, -24, 10, -12, 2, -28, 17, -12, -4, -3, -26, -9, 14, 22, 17, 28, 13, 15, 21, 8, -14, 2, -6, 8, 13, -6, -9, -11, 3, 24, -15, -7, -16, 20, -24, -30, 3, -20, 2, 33, 9, -3, 13, 12, 5, -17, 19, 6, 17, 24, 18, 7, -1, -31, 22, 12, 9, 8, -8, -34, 5, -16, -6, -7, 3, -31, -19, -18, 10, 19, 17, -22, -7, 28, 47, 5, -24, -18, -9, -14, 4, 17, 4, 9, -20, -6, -27, -16, -18, -9, -22, 3, -4, 6, 17, -6, 2, -5, -16, 19, -12, -13, 15, -16, -22, -27, -16, -6, 15, 9, -12, -6, -13, 5, -21, -16, 2, 20, -24, 16, -44, -17, 15, -2, 15, -20, 19, -3, 22, 27, -26, -23, 1, -6, 9, 0, 15, -17, 25, -12, 5, 11, 13, -26, -1, -7, -40, -20, 16, -21, 2, -12, 8, -28, 13, 12, -5, -14, -4, -14, -14, -20, 8, 19, -21, -6, -15, 0, 22, 3, -26, -16, 15, -29, 16, -4, -3, 3, 9, -14, -3, -3, 6, -11, 14, 7, 8, 2, -20, -4, -18, 8, -15, -5, 5, 3, -12, 14, -15, 1, -23, 7, -3, 35, -2, -19, 8, 13, 5, 6, -20, 10, -9, 8, 16, -11, 3, -26, -19, 15, -18, 1, 20, -6, -8, 9, 5, -23, 2, -2, -18, -18, -1, 13, 9, 18, -8, -9, 11, 9, -25, 21, -11, 2, -18, 3, -20, 10, 5, 15, -4, -8, 14, -20, -13, 10, -6, 6, 15, 14, -9, -15, 16, 1, -17, -2, -25, 11, 10, -17, 2, 24, -8, -18, -31, -20, -14, -17, 13, -7, 14, 37, -19, -30, -17, -17, -15, 7, 2, 9, 3, 16, -15, 6, -13, 7, 3, -1, 15, -4, -8, 20, -13, 2, -9, 3, 21, 7, -21, -15, -17, -2, 16, 20, 7, 13, -12, -6, -9, -24, -5, -7, 5, 0, 16, -10, 16, -28, -16, -1, -27, -14, -21, -9, 15, -5, -1, 19, -23, 16, 0, 1, -20, -7, -1, -4, -19, -21, -9, 9, -2, 5, 14, 29, 23, 37, 0, -23, -20, -23, 0, 6, -5, -10, 8, -25, -16, -29, 16, -16, -22, 4, 11, -19, 1, -8, -13, -18, -9, -29, -21, 6, -13, -8, -21, 10, 17, -21, -3, 1, 20, -23, -33, 0, -1, -4, -20, -24, -12, -7, 17, -4, 34, -4, -11, -16, 6, -26, -8, 19, -16, 19, -17, -4, -23, -13, 16, 2, 0, -35, 1, 21, 1, 15, -6, 24, 25, 8, 12, 2, 7, -19, -20, 0, 7, -10, 3, 0, 1, 12, -3, 30, -26, -9, 5, -7, 7, -3, 2, 5, -16, -4, 9, -3, -5, -9, -30, -31, 13, -6, 7, -10, 19, -3, -19, -17, -33, -5, -3, -11, -21, -9, -1, -17, -10, 27, 12, -16, 6, 11, 11, -12, -12, 11, -8, 3, -6, -11, -34, -23, -7, -25, 23, 4, -1, -3, 8, 3, 19, 5, -4, 19, 12, 7, -6, -23, 18, 6, 16, -9, -18, 8, -9, -12, 10, 11, -13, -27, 9, -16, 6, -3, -1, -14, -10, -21, -19, 2, 11, -5, 14, -13, -16, -20, 1, 2, 2, -22, 17, -9, -10, -13, -23, -14, -9, -15, 2, 0, -11, 15, -14, -19, 13, -21, 24, -25, 9, -15, 5, 16, 19, 14, -7, 0, 14, -10, 4, -25, 30, 1, 1, 34, 2, 17, -16, -18, 5, -10, 7, 8, 4, -15, -5, 2, 11, 42, 28, 30, -24, -6, 19, 12, -14, -21, 9, 17, 2, -9, 0, -12, 16, -3, -13, 9, 8, 22, 7, -20, 16, 28, 3, 23, 6, 5, -7, -11, -10, -9, -4, -2, -4, -4, 5, -9, -12, 13, -27, -10, 2, 14, -3, -18, 4, -8, -4, -4, 17, 1, 5, 0, 7, 18, -22, 10, -22, -2, 17, 7, 25, 2, -16, -13, -8, 17, 14, 25, -18, 4, -15, 19, -20, 9, -19, 21, -6, 5, -4, 17, -2, -14, -20, 17, 16, -25, -11, -11, 3, -14, -12, -10, -18, 25, -2, -11, 18, 15, -17, -3, 18, -24, -3, 5, 13, -31, -16, -15, -18, -16, -2, -10, -11, 17, 15, 11, -21, 10, -10, -31, -13, -16, 11, -6, 3, 29, -22, 20, 8, 6, -14, 3, -7, 22, 14, -14, -9, -6, -7, 13, 11, -20, 11, 4, 2, -3, 3, 7, 9, -19, -9, -11, -17, -23, 18, -11, -19, -16, 7, 32, -10, -15, -19, 15, 7, -20, -6, -6, -2, -8, -12, 19, -10, -6, -16, -19, 13, -4, -13, 17, 13, 8, -20, 1, 0, -17, -18, -28, 18, -2, -14, 7, -9, 23, 20, 11, -27, -7, -4, -9, -14, 19, 9, -11, 12, -18, 7, 12, -15, -18, 4, 11, -9, 15, 13, 23, 19, -8, -12, -16, 8, -9, -10, -6, -9, 5, 19, -2, 10, -11, -14, -10, 18, -36, -8, 0, -5, 5, -30, 16, -14, 17, -13, -20, 18, 21, 9, 39, -12, 13, 19, -26, 26, 6, -4, 2, 6, -3, -12, 7, 4, 15, 15, -5, -11, 14, -10, -23, 11, 15, 18, 9, -9, -18, 25, -29, 12, 32, 26, -5, 14, -23, 3, 0, 4, 13, 23, 27, 11, -28, 7, 25, -7, 8, 0, 9, 7, 14, -18, -6, -1, 25, -10, 16, -6, 3, -21, 12, 4, -16, 25, 19, -7, -24, -1, -11, 12, -2, 7, -16, 7, -25, -11, 8, 20, -7, 20, 26, 4, -17, 6, 7, 0, -7, -4, 7, 0, -9, -3, -18, 23, 33, -1, -3, -10, -12, -22, -3, -23, -1, 5, 22, 3, -33, -5, 6, 22, -17, 20, 6, 18, 6, -10, 3, 10, 1, 1, -23, -22, -11, 2, -16, 12, 6, 7, 13, 13, -18, 3, -13, 9, -3, -12, 26, 19, -12, -13, 15, -13, 4, 11, 23, -22, 7, -2, -6, 26, 21, 3, 12, -18, 9, 3, 8, 5, 13, 15, -13, 8, -32, 19, -5, -19, -10, -5, 24, -7, 15, 9, 10, 1, -10, 3, -38, -27, -8, 11, 1, 7, 5, -21, 7, 9, -12, 15, -5, -8, -39, 15, 16, 1, -21, 13, -16, -6, 55, 2, -29, 15, 14, 0, -11, -12, -34, -1, 35, -17, 14, -10, -27, -19, -10, -5, 10, -21, -11, 7, 2, 25, -14, -12, 4, -7, 8, 17, 2, 8, 17, -1, 18, 22, 12, -12, -12, 12, 20, 1, 25, 19, -26, 20, -11, -10, -6, 20, 24, 16, 7, -17, -16, 9, 30, 11, 17, -12, 3, 10, 9, -8, -11, -11, 30, -9, 15, -12, 10, -16, -17, -1, -4, -1, 14, 18, 4, 7, 37, 3, 17, 7, 3, -18, 8, 25, 21, 5, 27, -10, -2, 18, 11, -18, 4, 13, 13, 0, 20, 2, -23, -10, 15, -17, 6, 18, -16, -2, -6, 21, 5, 38, 13, -4, -10, -19, -19, 3, 7, -15, 21, -23, -9, -12, -17, -11, -3, 3, -24, 12, -2, -18, 5, 17, 1, 22, -4, -12, 13, -5, -3, 2, 0, 0, 14, -14, -15, -24, -13, -10, -1, -3, 0, 13, 17, -6, -5, -22, -11, 13, 7, -30, -23, -17, -12, -18, -4, -22, -25, 17, -3, 3, -8, 30, -31, 17, 4, -19, -12, 1, -7, 1, -6, -19, 9, -10, -7, -2, 14, -6, 28, 19, -9, 4, -2, 6, 12, -15, 5, 4, 18, -7, 10, 19, -7, -21, 13, -11, -34, 12, -7, 10, 17, -20, -15, -15, 34, 16, 10, 5, 6, 21, -10, 20, -10, 15, 13, 1, 16, 28, 1, 1, -1, -5, -7, 18, 14, 4, -13, -19, -17, 11, 11, 19, 15, -11, -33, 10, -21, -20, 18, 6, 24, -4, 23, -5, 28, -8, -9, 15, -11, 10, 12, -30, -30, -6, -14, 14, -38, -9, 0, 23, -13, -24, 13, -7, -17, 25, 29, -5, -25, 19, 20, -1, 25, -21, -13, 13, 5, 5, -3, 14, -12, 7, -5, 21, -5, -20, 9, 0, -1, -6, 25, 27, -13, 16, -8, -10, -16, 8, 1, -3, 0, -9, -4, -18, -18, -7, -23, 6, -4, 0, -19, 2, 3, -5, -4, 38, -29, -14, 5, -3, -11, 9, -22, -7, 14, -21, -5, 3, -18, 11, -10, 4, -11, -18, 3, -17, -6, 20, 10, 14, -21, 5, -6, -6, -1, 7, 6, 14, -4, -15, -24, -21, -6, 20, -3, 27, 14, -9, -26, 18, -6, 26, -14, -10, -6, -6, 0, -16, -18, -12, -3, 0, 17, 7, 27, 12, 1, -5, 11, 14, 14, 8, 23, -11, -20, 15, -17, -21, 12, -17, -23, -1, -3, -28, -20, 21, -17, -17, -16, -18, -19, 11, 22, -7, -4, -32, 9, 2, 23, 13, -34, -21, 19, 0, -5, 9, -3, -3, 9, -2, -9, -10, -1, 10, 6, -15, -3, -9, -2, -17, -10, 9, -12, 22, -5, 15, 10, 0, -20, 17, 0, -3, -22, 6, -6, 4, 2, 6, 10, 0, -31, 20, -19, 4, 12, 4, 3, 4, -17, 4, 10, -17, 22, -4, -20, -19, 8, 15, 20, -7, -4, -17, 19, 32, -24, -12, 0, -16, -33, 6, -1, 3, 7, -9, -25, -19, 23, 7, -5, 18, -36, 4, 0, -16, 11, 4, -14, -22, -25, -29, 5, -3, -9, -23, -15, 22, 17, -9, -33, 9, -14, 7, -3, 0, 3, 6, 17, -13, 25, 16, 17, 5, -2, -7, -16, 11, 10, 3, 7, 43, -8, -12, -27, 5, -18, 0, 7, -15, -10, 20, -10, 18, 9, 0, 11, -16, -34, 30, 0, 13, 10, -9, -5, 2, -24, -12, 15, -3, -4, 7, -5, -23, 16, 18, -12, -14, 20, -7, -6, -1, -17, 3, 12, -10, -20, 24, 2, -23, -12, -21, -2, 5, -22, 15, -1, -27, 0, 5, 4, 12, -3, -12, -7, -8, 8, 4, -11, -15, 0, 5, -12, 1, 6, -3, 6, 14, -17, 14, 4, -1, 19, 10, 12, 15, -24, -15, -19, 15, -35, 2, -21, 3, -15, -16, 13, 20, -27, 1, -9, 1, -8, 14, 4, -8, -34, -15, 16, 6, 2, 20, 4, -20, 24, -29, 5, 3, 7, 9, 11, -10, -2, 7, -21, -20, 10, -20, -7, 22, 10, 25, -6, 1, 9, -17, 9, -25, -25, 10, 13, -17, 15, 12, 12, 10, -5, -28, -23, -10, -16, 8, 3, 41, -16, -13, -25, -13, 13, -17, -9, 12, 13, 19, 2, -13, -17, -17, 3, -12, -5, -35, -10, -19, 3, 1, -7, 29, 12, -9, 8, -1, -11, 27, -5, 12, -3, 15, 23, 5, 13, 5, 12, 7, -26, -15, -9, -17, 6, -28, -4, -5, -2, 19, -13, 20, -24, 0, 13, -17, -20, 0, 20, 4, -17, -10, -23, -14, 3, 28, -2, 22, -24, 5, -11, -15, -10, -13, 2, -5, -20, -7, -7, 8, 12, 10, 7, 10, -20, 8, -8, -21, 14, -18, -19, 5, -25, 24, -13, -26, 0, 16, -15, -2, -9, 18, -18, 24, 10, -14, -7, 31, 12, 18, -26, 6, -12, 9, -3, -9, 16, 20, 1, -21, -4, -3, 12, 25, -16, 18, -24, -23, 8, -10, -43, 25, -18, -16, 12, 10, -24, 28, -25, 18, -11, -8, 0, -12, 1, 13, -34, -3, 6, -1, -9, 26, 0, -36, -10, 7, -8, 27, -9, 12, 7, 11, -12, 0, -11, -19, 8, 3, -16, -10, -6, 14, 10, 19, -15, 17, -17, -2, -1, -17, -1, -5, -22, -1, -1, -2, 26, 2, 6, -11, 1, -8, 10, -24, 9, 3, -24, 25, 2, -17, 15, 5, 17, -2, -8, 4, -11, 4, 30, -11, -20, 9, -15, 13, -4, -21, 10, 10, -12, 19, -9, 8, -9, -13, -21, 14, 0, 10, 14, -10, -2, -13, -1, -9, 9, 0, -13, 33, 8, 16, 18, -4, 0, 13, 6, 23, -19, 1, 8, -19, -9, 8, 1, -9, 14, -5, -28, 3, -17, 8, 6, -9, 29, -23, -3, 10, -28, -18, -7, 0, -6, 8, -24, 0, -1, 26, 16, -4, -9, -17, -9, -25, -2, -24, 1, 13, -22, 3, 23, -15, 15, -11, -20, 2, -15, 18, -15, -19, -13, 15, -12, -10, 14, -5, 16, 0, 10, -22, -14, -21, 10, 0, -7, -9, -7, 8, -7, -4, -3, 8, -4, -1, 16, -5, -11, -11, 13, -12, 11, -14, 2, -18, -16, 16, -2, 1, -19, 11, -30, -1, -25, 0, -24, 12, -26, -2, -19, 21, 1, 29, -14, -25, -18, -2, -25, -17, 24, -29, -4, -28, 4, 11, -14, -10, 16, -11, 0, 4, 7, 5, 5, -13, 5, -17, 1, -8, -33, 23, -31, -7, -16, 28, -13, -10, 8, -2, -29, 25, -1, -26, 2, -1, 2, 16, 8, -30, -23, -6, -15, 27, -23, -9, -11, -16, 9, -3, -6, 6, 26, 7, 6, -8, 16, -9, -2, 8, -2, 15, -38, -21, -15, 0, 8, -5, 34, 12, -1, 2, -6, 24, -22, 16, -12, -16, -4, -18, 9, -11, -13, -7, 1, -16, 24, 4, 2, 0, -2, 4, 8, 12, -27, 16, 6, 2, 6, -9, -5, -1, -15, -17, -19, -9, -22, 9, -2, 1, 21, 30, -4, 10, 16, 1, -24, 0, -7, -9, 5, 13, -1, 9, -32, 18, 13, 7, -5, 14, -20, -17, -15, 28, 10, 7, -18, -8, 11, 2, -6, -14, -5, -10, 7, 38, 1, 22, -42, -27, 2, 17, -19, 40, -16, -5, 7, -8, 4, 14, -14, -22, 3, 0, 23, 4, 14, 16, -6, 8, 16, -12, -20, 12, -18, 21, -6, -17, -13, 2, -10, -8, -24, 21, 12, 15, 14, -10, 6, -8, 7, 6, 2, -13, 0, -15, -10, -8, -13, 0, -25, 3, 14, 11, 10, 15, -8, -22, -5, 21, -9, 17, -2, 15, 13, 24, -25, -21, 14, -1, 3, -11, -10, 6, -1, -9, 4, 8, 11, -3, -15, -12, -12, -10, -10, 20, -29, -11, 19, -7, 13, 11, 7, 15, 18, -27, -4, -10, 4, 6, -10, -13, -29, 11, -20, 5, 10, 18, 14, -5, -10, -4, -3, 4, -7, -12, -2, 2, 12, 16, 24, 8, 12, -3, -11, -21, -4, -2, 8, -40, 23, 16, -17, 14, -53, -14, -13, -23, 5, 2, 6, -21, -4, -34, -20, 11, 9, -4, 12, -14, -12, -11, -8, 1, -16, 19, 4, -17, 9, 8, -15, -11, 4, 15, -5, 17, -36, -12, 18, 27, 3, 0, -22, 4, -17, 14, -19, 24, -19, -34, 12, -6, 4, -17, -21, 27, 0, 38, -5, 33, 8, -6, -25, 11, -11, 20, 14, 8, 4, 17, -8, 3, 26, 15, -4, 9, -13, -16, -11, -19, -7, 22, 9, 9, -6, -13, 3, -8, -8, 17, -6, -3, -2, 22, -30, -14, 8, 20, 18, -10, 2, 12, -30, -2, -21, 14, -9, 19, -29, 16, -5, 0, 13, 50, 19, 2, 7, 14, -4, 26, 6, 24, 1, 15, -10, 2, -10, -3, 17, 3, 16, 8, -7, -11, -1, 21, -8, -9, -13, 4, -7, -17, -29, 8, 4, -6, -26, -1, 2, 5, 3, 5, 9, -10, -9, 5, -8, -20, -21, -9, -18, -11, 14, -14, 8, -32, 21, -12, 14, 2, 15, -9, -5, 37, 10, 17, -17, -27, -8, 23, 5, 3, -12, 15, -7, -4, -2, -6, 13, 20, -7, 0, -5, 4, 12, 28, -21, -7, -10, 14, -12, -12, -6, -13, 0, 51, -27, 7, -4, -17, 5, -8, 14, -25, -13, 12, -18, -11, 7, 13, 3, 19, -14, 8, -20, 4, -13, 10, -4, 13, -30, -9, -15, -20, -1, -5, 16, 0, -17, 1, -15, -20, -29, 10, 23, 10, 25, 4, 7, 7, -9, 7, 26, 11, -13, 1, 9, 1, -16, -8, 4, 50, -1, 2, -9, -5, 11, 4, -22, 8, -16, 20, 4, -5, -9, 8, 7, 25, -36, -4, 2, 25, 11, 19, -9, 7, 18, 11, -22, -12, -22, 2, -15, 22, 7, 4, 4, -5, -12, -4, 36, -10, -24, -7, -20, 13, -18, -1, 4, 14, 4, -8, -12, 6, -19, -43, 43, 8, 12, 3, 14, 7, -9, -12, 13, 18, -27, -26, 12, 10, -18, 8, -25, 29, -1, -17, 2, -32, -7, -13, 4, 48, -19, -6, -2, 19, 1, 24, -16, -11, 8, 5, 10, -21, 9, -13, -19, -15, -5, -7, -22, -1, -17, -27, 13, -10, 12, 12, 0, -23, 8, -4, -17, 6, 21, -1, -21, -7, -6, 0, -26, 10, -5, -6, -15, -6, -20, -12, 17, 16, 1, -17, 8, 16, 7, 2, 15, 9, -19, 14, 9, 3, -14, 0, -24, -3, 11, 17, 13, 18, -19, 10, 7, 4, -19, -18, 20, 13, -1, -9, -2, -11, 2, 14, 14, -15, 0, -11, 23, 3, -12, 14, 7, -19, 2, -25, 10, -9, 9, 10, 17, 17, 17, 13, -3, -2, -18, 11, 7, -2, 7, -16, -17, -12, -22, 16, -5, 34, 13, 14, 8, -30, 15, 2, 12, 2, 9, -12, -17, 12, -30, 1, -21, 1, 3, 27, -4, -14, -14, -24, 3, -6, -11, 12, 2, 3, 15, -18, -14, 4, -18, 16, -8, 13, 20, -20, 16, -25, -14, 5, 8, 15, 17, 4, -18, -15, 3, -32, 58, 19, -15, 6, -13, 12, -2, -12, 2, 8, -22, 21, -7, 11, -2, 10, -9, 17, -2, -5, -18, 10, -16, -2, -2, -23, 8, -25, -13, 6, -22, 18, -2, 23, 12, 32, -25, -13, 6, -4, 18, -2, -10, 10, -12, -21, -13, 12, 0, 18, 30, -9, 19, -13, -8, 4, 2, -1, -4, -1, 9, -45, 11, 2, -12, -2, 16, -7, 5, -13, -15, 6, 2, 33, -14, -8, 13, 12, 15, -2, -29, 10, 16, -9, 3, -14, -27, 6, 18, -1, -10, -17, -5, -36, -11, -8, -17, 14, 9, -23, -18, -7, -23, 32, -13, -5, -31, -31, 6, -33, -19, 30, -11, 27, 7, 27, -23, -13, -10, 15, 0, 19, -17, -41, -13, -19, -14, 16, 12, 16, 17, -20, 1, -38, 3, -15, 3, 14, 6, -24, -3, -8, -23, 12, -3, -8, 8, -3, 13, -1, -26, 9, -1, 24, 20, 13, -17, 10, 7, 0, -11, 19, 24, -41, -11, -15, 11, -1, 2, 3, 2, 6, -24, 25, -26, 24, -15, -9, 7, -4, -15, -8, -21, 12, -7, 19, 0, -7, 9, -23, -4, 14, 17, 12, 14, 20, -11, 4, 11, 18, -25, 22, 15, 19, -18, 9, -9, -37, -23, 12, -23, 13, 10, -33, -23, -21, 18, 30, 21, -16, -12, -7, 13, 24, -12, -12, 1, 35, 17, -4, -7, -30, 22, -29, -30, 22, 1, -1, 5, -17, 27, -12, 9, 18, 11, 2, -6, -10, 26, 20, 11, 4, -1, -22, -25, 17, 6, 4, -6, 11, -21, 22, -11, -19, -34, 12, -10, 35, 21, -17, -7, -24, -9, -1, 30, -7, -7, 13, 6, 13, 24, 18, -8, 25, 20, -17, -8, 0, 0, 31, 0, 35, 10, -21, 13, -28, 9, 3, 9, -39, 9, -27, 3, -27, -53, -33, -26, -36, -12, 41, 8, 3, 2, -1, 9, 10, -13, 14, 4, 13, -29, -26, 3, 23, 6, -7, 14, -12, -9, 2, -9, 2, 17, 14, -24, 7, 24, -7, 13, 10, 9, 10, -8, -12, 8, -13, -19, 18, -3, -24, 12, 26, -25, -5, 11, 39, -11, 21, -13, -35, -6, -10, 12, -8, -23, 15, 6, -12, 12, -10, -6, -4, -2, 16, -23, -7, -1, -25, 27, -10, 0, -21, -11, -13, -2, 15, 22, 21, -25, 25, -14, -4, -15, -12, 16, 4, -4, 22, -21, 4, -16, -17, 24, -17, 4, 17, -21, 1, 29, -49, -9, -5, 6, 15, 0, -10, -29, -7, -17, 0, -1, -13, 2, 9, -8, 18, -19, -9, 12, 2, 2, -38, -1, 25, 17, 20, -7, 15, 2, -22, -7, -1, 4, 0, -27, 24, 8, 1, -17, -15, 17, 16, 30, 17, -19, -21, 8, -9, 13, 1, 7, 3, 17, -11, -34, 7, -23, -1, 11, -7, 17, -26, -16, -26, -57, 2, -9, 8, -18, -2, 1, -29, -17, 17, 5, -6, -17, -5, 16, 5, -1, -17, 6, -8, -17, -4, 26, 22, -17, 7, -19, 4, -1, -8, 7, 16, 3, 28, 4, -17, -3, -5, 28, -6, -5, 7, 18, 10, -9, -26, -26, 8, -4, -6, 2, 20, -14, -9, 11, 2, -15, 26, -14, -9, 4, -45, 14, 33, -18, -19, 7, 19, -10, 7, 6, -28, -24, -18, -16, 22, -23, 21, 6, -14, 6, -16, -3, -13, 16, 11, -13, 16, 4, -9, -16, -19, 17, 16, -2, -12, -24, -37, 16, -29, -12, 40, -24, 36, 12, 20, 12, -18, -18, -10, -25, -9, 5, -23, 1, 4, -18, -4, 9, -21, 17, 6, 6, -19, 7, 16, 1, 0, 2, -14, -17, -6, 13, 2, 34, -2, 18, 13, 17, -29, 0, -20, -19, -8, -26, -19, 1, -7, 8, -24, 4, -3, -13, 5, -19, -8, 0, 6, 6, -23, -12, -6, 1, 15, 6, -4, 27, -27, -14, -22, 3, -16, 15, 23, -4, 5, -28, -9, -12, -18, -11, -12, -24, 23, 21, -15, -24, 11, -17, -12, -27, -18, -12, -21, 18, -4, -7, 41, -13, 10, -1, -15, -4, 9, 16, 0, 18, -26, 0, 23, 17, 22, -12, 1, -20, 15, -28, -15, 6, -10, 11, -18, -6, 22, -2, 4, -14, 16, 6, -6, -19, -5, -18, 3, 14, 11, -23, -13, -11, -2, -7, 10, -7, 7, 5, 11, 18, -21, 9, 7, -10, -23, -3, 6, -3, 22, -2, 10, -19, 0, -22, -1, 12, 4, -13, -4, 4, -5, 7, 19, -6, 40, 3, -6, -1, 16, -18, -9, 4, -11, -6, -5, -11, -13, -10, 1, 10, 17, 12, -4, -11, -17, -5, -16, -8, 0, 30, -21, -13, -10, -10, 0, 8, -7, 8, 7, 7, 10, -19, -21, 43, 19, 16, -24, -8, -2, -15, 19, -21, -6, -22, -34, -10, 10, -9, 7, -6, 1, -2, 12, -2, -1, 16, -6, 6, 26, 21, -21, 10, -4, -23, -21, -16, 30, 4, -5, 13, -3, -11, -45, 23, 0, -6, -10, 10, -17, 22, -9, -22, 4, 3, -14, 1, -1, -18, 1, -5, 17, 21, -39, -2, 20, -3, 31, -18, -34, 6, 27, -19, -2, -10, -18, 25, -10, 13, 3, -16, -15, 5, -23, 9, -1, 17, -20, 5, -31, 8, 37, -15, -2, 17, -3, 8, 19, -4, 45, 14, -29, 10, -44, -23, -15, 10, 7, -9, -11, 21, 14, 14, -15, 12, 2, 0, 22, -2, 10, 9, 8, 16, -17, 13, -7, -7, -14, 12, -5, -9, -26, 8, -10, -10, 10, 6, -17, 15, 9, 12, 27, 1, -29, -20, -44, 17, 17, -28, 29, -10, -15, 20, 9, 16, 39, -16, 17, 9, 10, -11, -3, -9, -5, 13, -2, -2, 2, -15, 32, 13, -16, -23, -43, 6, -4, 5, -29, 7, -10, -2, 34, -24, -19, -7, 16, -12, -6, 9, 16, -13, -31, 11, 19, 0, 23, 24, 5, 9, 16, 15, 9, 6, 4, 8, 10, -20, -5, 23, -16, -26, -9, 11, 11, 10, -12, 8, -26, -1, 6, 8, 28, 24, -11, -3, -11, -9, 15, 18, -9, -20, -20, 14, 16, 11, 13, 22, -33, -12, 8, 6, 11, 17, 1, -15, -33, -33, -13, -6, -11, -2, -15, 29, -6, 5, 2, 6, 22, 11, 18, 18, -5, -11, -2, -23, -18, 8, 17, -22, 4, -7, -28, -23, -38, -23, 14, 25, 30, -15, 2, -12, -11, -1, 15, 1, 1, 25, 6, -21, -26, -5, -3, 15, -12, 24, -24, 7, -24, -16, -5, 32, -14, 14, 8, -12, 15, -3, -4, 19, -8, -7, -18, 6, -2, 12, -12, -17, 21, 18, -26, 8, -2, -12, 1, -8, -10, 16, -12, -7, 3, -3, 16, 11, 3, 23, 13, -22, 4, -25, -15, 26, 22, 5, -14, 6, -11, 6, -1, -11, 18, -19, 4, -17, 2, 6, -18, 2, 10, 19, 12, 9, -2, 3, 2, 1, 9, 15, -27, 0, -25, -15, 3, 4, 26, 23, -30, 10, -20, -17, 17, 1, 19, 19, -38, -12, 1, -1, 8, 20, 6, -7, -15, 15, 1, -23, 29, 12, 2, 30, 25, -25, 5, -26, -30, 7, -5, -9, 21, -14, -17, 7, 7, -12, 0, -3, -13, -8, 32, -3, 35, -23, -19, 23, 4, 2, -4, 12, -7, 9, 19, -42, -8, -22, 11, 15, 14, 8, -32, 2, 8, -12, -3, -6, 12, -43, -10, 23, 9, -24, -21, -14, -26, 52, 27, -3, -6, 27, -10, -12, -13, -9, 8, 8, -12, 13, -1, 24, 2, -55, 7, -2, 4, 11, -13, 3, -12, -11, -23, 41, 10, -18, 4, -18, -20, 22, -17, -4, 6, -13, -19, -23, -44, 38, -11, -5, 20, -6, -16, -14, 7, 10, -13, 12, 11, -7, -18, -21, 3, -1, 4, 7, 12, -5, 3, 15, 2, -15, 0, -2, -19, 12, -36, -3, -14, -39, -4, 14, -3, -4, -2, -3, 15, 11, -11, 5, -2, -27, -17, -18, 9, -5, 33, 1, 16, -13, 14, -12, -10, 2, -19, 1, -13, -7, 24, 22, 2, 2, -35, 20, -2, 0, 33, 14, -17, 19, -3, 56, -5, -20, -5, -17, -19, 16, -27, -6, -23, -11, -28, 3, 10, 8, 18, 1, -17, 15, 6, 10, 0, -10, 13, -12, 22, 13, 17, -22, 36, -40, -17, -3, -2, 15, -2, -11, -46, 16, 9, -12, 6, 13, -7, -4, -36, -12, 25, -23, 9, -3, -11, -4, 42, -7, -11, -21, -17, 4, -13, -14, 36, -32, 47, -13, 15, 3, -14, -24, -8, -22, -11, 28, -5, -26, 4, -10, -13, 4, 24, -1, 22, 5, -6, 9, -20, -10, -21, 15, 7, -1, -24, 1, -25, 13, 52, -62, 1, -19, 32, 11, 15, -7, -2, 34, -9, 0, 0, -4, 49, -54, -25, 22, -6, 3, -3, 11, 46, -43, -24, -13, -2, -25, 9, -8, -16, -7, 2, -19, -35, 5, -16, -8, 68, -52, 27, 4, 37, -13, 19, -4, -24, 2, -16, -19, 1, -19, -4, 19, 8, 22, 22, -35, -19, 8, -2, -9, 25, -21, 43, -38, 15, 11, -10, 8, -8, -6, 63, -61, 15, 9, 10, -11, 4, -8, -4, -7, 17, 4, 9, 22, 24, -14, -12, 10, 15, -11, -16, -14, -25, 16, 43, -8, 5, 4, 21, 15, -4, -12, -12, 14, 6, -8, -19, -7, 13, -11, 43, 5, 18, 17, -5, -2, 13, 10, 11, -28, -14, 2, 18, -23, -7, -8, -27, -7, -2, -13, 9, 14, -3, 27, 3, 13, -8, -5, 4, 13, -66, 53, 11, 15, 16, 0, -34, -5, -11, 2, -11, 24, -26, -4, -31, -11, 3, 3, 8, 33, -48, 10, 13, -20, 48, -3, -15, 2, 7, 9, 14, -17, 1, -10, -14, -3, -27, 4, -58, 0, 4, -3, 39, -3, 24, 13, 20, -19, -21, -9, 18, -4, 29, -8, 1, -5, -12, -6, 33, 9, -9, -21, 9, 1, 3, 32, -10, -13, -16, 17, 14, 14, 50, -5, -47, 13, -15, 5, 29, 9, -7, 21, 9, 11, -1, 10, -24, 3, 24, 3, -15, -21, 1, 4, 3, 9, -5, 17, 13, 16, 2, 15, -12, 9, 29, 6, -4, 17, -13, 12, -39, -17, 22, -2, 37, -24, 10, -20, 6, 5, -25, 13, 14, -32, 19, 12, -3, 18, -24, -3, 7, 6, 7, -3, -6, -7, -6, -10, 3, 25, 15, -5, 2, 20, 33, -5, 5, -3, -3, -1, -7, -5, 50, 5, 7, 0, 8, -4, 2, 0, -52, 10, -14, -10, -14, 2, -13, 15, 8, -3, 1, -26, -34, 7, 8, 1, 34, -13, 0, -1, -16, 0, -17, -4, -6, -2, -33, 0, -10, 16, 23, 4, 42, 14, -4, -18, 23, -21, 8, 15, 13, -10, 23, 2, -15, 20, -30, -3, 22, -41, 20, -6, -13, 13, -5, -6, 34, -14, -3, 23, 18, -29, -12, -18, -2, 13, -6, -11, 12, -3, -1, 19, 7, 13, 25, -8, -12, 16, 15, 5, -13, 4, 7, -2, 14, -6, -34, -15, -28, 27, -22, 23, -19, 1, -17, -17, 17, 7, 15, -6, -22, 19, -1, 7, 31, -33, 8, 5, -3, -22, -17, 0, -14, 8, -3, 21, 21, -23, -32, 14, 0, 11, 12, 10, 0, -17, 14, -6, 18, 8, 10, 9, -4, 7, 17, 13, 16, 3, 10, -21, -30, 0, 13, 8, 5, 8, -18, 2, -10, 13, 18, 14, -18, -2, -13, -15, -10, -3, -32, 12, -6, 2, 9, 16, 7, 2, -30, -6, 1, 9, 6, 3, 13, -14, 6, -5, -13, 13, 14, -4, -49, 5, -14, -2, 25, -35, -12, 11, 11, -23, 3, -13, 30, -13, -25, 6, -7, -21, 31, -24, -5, 5, -5, 15, -15, 3, 16, -2, 31, -31, -19, -5, -7, -2, 9, 10, -16, 14, 12, 7, 11, 21, -19, 17, -29, 4, -15, -15, -15, -12, 17, -6, 22, -18, -3, 8, 14, -14, -2, -6, 4, 5, -9, -21, 18, 9, -14, 20, -3, -23, -5, -4, -8, 5, 8, 33, -49, -1, -27, 0, -7, 5, 2, 5, 5, -4, -19, -4, -7, -14, 10, -10, 11, -7, 13, 13, -9, 8, 13, 19, 12, -15, -33, 13, -10, 7, 15, -12, -9, 2, -7, -17, -21, 2, -8, 23, -6, -20, 15, -28, -10, 13, 18, -4, -3, 11, 15, -10, 1, -9, -11, -14, -14, 16, 2, 10, -22, -1, 5, -15, -9, -9, -7, -14, -19, -7, 4, -6, -29, -16, -7, 7, -11, 2, 4, -5, 15, -21, -28, -25, -4, -2, 0, 3, 13, -1, 19, -16, -8, -8, -17, 3, 1, -25, 3, -26, 12, -6, -17, 19, -23, -1, 20, -11, -23, -11, -21, -20, 4, -16, -9, -17, -24, 11, 17, -1, 5, 10, 13, -4, 5, 8, -23, 11, 1, -18, 0, -19, 15, 15, -4, 4, 22, 6, 7, -3, -4, -16, -10, -6, -13, -26, 2, -2, -16, 24, 10, -24, -12, -16, -14, 19, -14, -17, 12, -19, -3, -30, -2, 1, -18, -12, -10, -7, 5, -3, -12, -22, -6, 7, 8, -14, -10, -13, -4, 14, 7, -24, 16, -19, -1, -8, 1, 7, 2, 26, 11, -2, 5, 6, -3, -20, 11, 0, -15, -8, -8, -1, -2, -15, -10, 12, 6, 3, 9, -15, 7, 7, -4, -26, 3, -18, -4, -10, 22, -10, -18, -13, -1, -14, -27, 13, -14, -11, 13, -12, -21, -30, 11, -18, 24, 16, -4, -30, 2, -16, -12, 17, 24, -17, -15, -12, -1, 22, 11, -5, 12, -7, -10, -19, -9, 9, 10, -17, 21, -19, 11, 14, -9, 28, -30, -25, -2, 10, 13, 5, -6, -1, -8, 5, 21, 12, -9, -14, -23, -23, -3, 13, 12, 10, -9, -9, 15, -3, 19, 11, -28, -2, -10, 1, 7, -6, 5, -3, -4, 10, 15, -3, 1, -13, 15, 24, 7, -5, 9, -18, -1, 19, 6, -22, -20, -17, -7, 28, 15, -32, 1, -34, 18, -11, -7, -20, -4, 19, -15, -5, 15, 10, -19, 11, -10, -9, -11, 1, 19, -14, -8, -1, 13, -24, 18, -8, -7, 19, -19, -24, -2, 7, 27, -7, -20, -9, -16, -4, 2, -2, 18, -15, -13, -8, -2, -14, -15, -11, 11, -20, 3, 8, -5, 1, 8, 1, 3, -16, -17, -1, -15, -15, 1, 2, -2, -5, -16, 1, -18, 7, 1, -11, 14, 10, 5, -10, -11, 13, -16, -18, 15, 10, 10, 30, -8, 0, -19, 12, -30, 30, -10, 12, 7, -5, 5, -25, 25, 14, 9, -15, 10, -12, 22, -17, -11, 2, -7, 4, -1, -19, 13, 0, -15, 35, 15, 10, 1, 13, -21, -2, -4, -16, 17, 7, 10, 5, -13, -8, 15, -6, -6, -14, -3, 5, -13, -30, 30, -8, -10, 14, -5, -9, 11, -24, -19, 3, -19, 8, -17, 18, -9, -20, -4, 21, -5, -11, -5, -1, -9, -6, 12, -6, 2, 11, 17, -20, -14, -15, 1, 27, 0, 15, -1, 13, 11, -24, -30, 13, -33, 8, 6, -3, 1, 24, -5, -12, -15, -15, -24, 2, 12, -22, 2, 15, 24, 13, -4, 2, -6, -31, -39, 22, 5, -15, -20, -2, -9, -14, -26, 15, 6, 8, 11, 4, 12, 17, -28, -10, -22, -18, -1, 7, -22, -22, -9, 9, -50, -15, -20, -6, -23, -21, -15, -16, 15, -22, 12, -32, -14, 16, -26, 6, -4, 1, -10, 8, -15, -1, -32, 0, 10, -12, 3, -3, 15, 20, -12, 27, 11, 10, -9, -1, -21, -11, -35, 8, -12, 13, -4, 16, -15, 6, 1, 11, -16, -22, 14, -19, -17, 7, -35, 1, -10, -3, -24, 14, 10, 4, -22, 16, 10, 35, -11, -1, -14, -5, 15, 14, -18, -29, -19, 11, 19, -32, 6, -13, -8, 20, 17, -17, 7, -20, 6, 4, 17, 14, 4, 4, -5, -6, -19, -12, 18, 19, -11, 6, 14, -9, 17, -14, 2, -11, 7, 27, 17, -9, 13, 27, -12, 8, -3, -8, -12, -18, -39, -19, -7, 26, -17, -6, 5, 5, -6, 22, -18, 7, -11, 23, -2, -6, -10, -11, -9, -6, -1, 2, -6, -7, 11, 12, -11, -11, 10, -8, -14, -12, -2, 2, -25, 4, -7, -5, 7, 2, -15, 8, -39, -6, 21, -26, 4, -1, -3, 14, -20, 3, -22, 6, 13, -4, -19, -8, -9, -25, -4, 6, -13, 14, 16, -27, 3, 15, 0, 5, -23, 1, 17, 3, -17, 1, 21, -11, 9, -8, -2, 5, -21, -8, 7, -26, 10, -10, -21, -20, -30, -14, 19, 3, 8, 11, -25, -23, -1, 26, -14, -1, -11, -11, -25, -21, -32, 6, -20, -1, -11, -17, -22, 9, 2, -9, -14, -23, 16, 5, -5, 19, -16, 20, -4, 0, -23, -19, -8, -9, -21, 14, -24, -2, 10, 22, 3, -15, -18, 21, 0, -4, 9, 10, -13, -14, 2, 2, -19, -10, -3, -9, 0, 19, -27, -8, 0, 14, 3, -16, 22, 11, -9, 16, 9, -7, -12, 8, 6, 7, -9, 17, 10, 24, -16, 0, 3, 0, -23, 12, -15, 10, 18, -5, -18, 4, 1, -20, 9, -11, 8, -20, 7, -12, -7, -14, 12, 5, -15, 18, 6, -22, 0, -14, 11, -19, 7, 18, -11, 12, 7, -23, 10, -2, -22, -15, 69, 15, -15, 31, -16, 17, 3, 7, 8, 4, -8, -2, -23, 7, 11, 23, 4, -4, 11, -8, 6, -24, 24, 8, 28, 4, -30, -12, 1, -10, 3, -16, -10, -20, -6, -2, -14, 4, -4, 21, -6, -30, -7, -8, 17, -12, -2, -22, 22, -17, -6, 4, 12, -13, -5, 12, 14, -6, 9, 0, -22, -12, 6, 19, -17, 21, 32, -14, 6, 23, -15, 12, 18, -27, 14, -7, -14, -10, -15, 2, 6, -16, -7, -23, -22, -25, 14, -13, -2, 8, 13, -17, 11, -11, -5, 33, -3, -21, 1, -21, -19, -9, 10, 16, 7, 10, 14, -20, 14, -21, 12, 14, 14, 17, 21, 8, 15, 15, -8, -16, -6, 19, -11, -5, 8, -25, -15, -19, 17, 9, -7, 14, 14, -14, -18, -2, 16, -25, -12, -17, 0, 1, -3, 12, -2, -5, 42, -28, 18, -17, 8, 5, 26, -36, 0, -12, 5, 0, -20, 23, 20, 12, 0, 17, -10, -9, 17, -1, 7, 2, 12, 16, 14, -23, -22, -21, -14, -11, 12, -29, -17, -8, -7, -13, -14, 6, -15, 2, -22, 29, -19, -24, 36, 4, -25, -17, -14, -16, 18, 1, 7, -20, 6, 16, 4, 14, 14, 3, -17, -15, -11, -20, -16, 0, -21, -7, 26, 19, -11, 7, -21, -9, -13, 0, -25, -15, 27, -14, 11, -18, -15, 15, 6, 8, 2, -24, 12, -18, -10, 15, -26, -19, 23, 3, -12, 3, 0, -8, 7, -9, -9, 12, -20, -21, -6, -4, -1, -14, 8, 12, -9, 18, -8, -8, -33, -4, -16, -12, 16, 0, -22, 14, -37, 8, -14, 11, -18, -30, -23, -11, 5, 12, -28, -6, -14, 4, 6, 18, 12, -10, -8, -18, 16, -7, 15, 14, 11, 15, -26, -43, -4, -15, -17, 3, 1, -9, -21, 14, 19, 30, -17, 16, -12, -26, -20, 8, -16, 11, -10, -3, -16, 17, -9, -19, -18, 11, -5, 17, -22, -15, -8, -17, -22, -1, -1, 4, 13, -19, -21, -12, 11, -8, -19, 11, -6, -19, 5, 9, 9, 6, -1, 36, -11, 3, 21, 3, 13, 5, 2, -7, -10, 3, -7, 11, 15, -20, -24, -5, 20, 4, -11, 7, -21, -8, 7, -22, 12, 21, 23, 13, -22, -28, 4, 11, -13, 15, -16, -2, -8, -23, -9, 3, 5, -6, 13, 19, -20, -13, -11, 14, -15, 1, -6, 32, 0, -15, -14, 8, 47, 1, 6, 12, -17, 7, 0, 10, 19, 10, 12, -17, -4, 9, -16, -10, 27, -5, 2, 10, 11, -3, 5, 23, 15, -17, -26, 3, 9, 8, -19, -21, -3, 28, -4, 3, -17, 9, -2, -12, -14, 17, -22, 0, -16, -8, 9, 1, -33, -16, 15, -15, 12, 5, 13, 4, 7, -7, 18, 38, -12, 13, -19, -6, -11, -13, 1, 1, 10, -26, -6, -8, -6, -7, -32, 22, 12, 9, -23, 1, -7, -22, 9, -22, -23, -11, -6, 21, 3, -25, -12, 12, -24, 10, -25, 9, 2, 12, 20, 1, -18, -27, 6, -28, -31, 5, 6, 20, -4, -13, 14, -42, -18, -12, -11, -18, -4, 16, 12, 10, 7, 17, -11, 8, -1, 2, 10, 5, -26, 10, -40, 3, -18, -2, 15, 30, 7, 23, 17, 9, 8, 6, 19, 17, 7, 24, 9, 6, 5, -30, 0, -7, -27, 4, -20, 7, 18, 17, -1, -12, 0, 26, 1, 30, 2, 17, -18, -10, 3, -15, -8, 21, -18, 7, 7, -2, 3, 4, -8, 15, -19, 36, -7, 8, 17, -5, 0, 17, -5, 20, -21, 21, -11, 32, -8, -16, 13, -23, -13, 9, -49, -14, -18, -7, -3, -12, -24, 9, -13, -12, 3, 15, -6, -7, 19, 18, 3, -11, 12, -3, 12, -4, -23, -1, 11, 16, 9, 22, -13, 9, -16, 16, 7, -4, -12, -2, -13, -12, -6, -9, 19, 19, -17, -12, 17, -21, -20, -18, -28, -6, -48, 18, -11, -4, -14, 1, 19, 9, -26, 9, -7, -18, 18, -35, 12, 12, 3, -2, 15, 13, -8, 6, 6, -5, 12, 18, -22, -19, 15, -14, -13, -17, -24, -15, -9, 3, -21, -33, -12, 2, 1, 5, -21, 7, 4, 6, 29, 16, 15, 16, 4, -37, -3, -22, -27, -15, 0, 28, 0, -29, 0, -1, 2, -4, -8, -17, 2, 2, -14, -9, 11, 22, 5, 9, 7, -24, -11, -8, 35, 22, -3, -3, -15, 11, -12, 7, 38, -5, 16, -9, -22, -26, 9, 12, 16, 23, -23, 8, -21, -19, 6, -13, 12, -17, -31, 9, -2, -10, -4, 4, 8, -6, -16, -4, -11, -16, 13, 9, -16, -11, -2, -5, -24, 13, -19, 0, 14, -9, 29, -5, 8, -17, 23, 4, 14, -2, 7, 39, -12, -24, 4, 14, -5, 18, 1, -12, -5, -15, -4, -23, 21, 18, -8, -15, -9, 5, -17, -8, 23, 12, 2, 1, -21, -18, -23, 3, -19, -17, -7, 15, 6, 12, 11, 0, 6, -7, -9, -29, 13, 3, 9, -26, 16, -24, 4, 12, -5, -11, -21, -23, 11, -14, -1, 12, 16, -31, -11, -25, -29, -12, -8, -35, -10, -8, 7, -27, -9, 6, 20, -12, -19, 7, 11, -29, -3, -4, -10, -29, -20, -28, 10, 5, 18, 1, 5, -5, -19, -23, 2, -15, -5, 22, -9, 6, -11, 10, 4, 6, -11, 0, -15, 11, -7, -6, -20, 14, -21, -9, -4, 16, -4, -18, -14, -16, -22, 9, -10, 7, -12, 5, -13, 2, -11, -7, -18, 12, -12, 10, -7, -2, 15, -2, 4, 5, -3, 8, -12, -14, 9, -6, -13, -1, -11, 4, 17, 10, 15, -11, 4, -3, -18, -17, 0, -12, 10, -1, 6, 0, 2, 15, -20, 7, 5, -21, 11, -8, 16, -25, -23, 9, -7, -5, 8, 16, -11, 18, -20, 2, 41, 17, 7, 3, -17, -14, 14, 12, 9, 15, -4, -13, -18, -4, -23, -2, 6, 21, -22, -28, 16, 7, 0, -11, -14, 0, 20, -4, 15, 3, 11, -17, -3, -12, 0, 8, 5, -2, -2, -23, 29, 8, 7, -19, -6, -9, -17, -19, -22, -5, 10, -19, 13, 13, -4, -18, 16, -23, 7, -13, 10, 23, -12, 0, -5, -3, 24, -3, -9, 8, 12, 15, 26, 7, -1, -12, -3, 17, -17, -10, -18, 3, 24, 11, -9, 8, -2, -12, -14, -9, 6, 1, 3, 13, 17, 6, -25, -18, 3, -19, 18, -4, -16, 7, -10, -6, 1, -2, -15, 16, 5, -4, 23, 19, 19, 1, 10, -8, 11, -19, 26, -4, -4, 12, 1, 7, -13, 7, 5, 9, 2, -26, -7, 2, 1, 11, 9, -16, -21, 4, -6, 10, -2, 7, -34, -28, -12, 2, -11, -23, -11, -30, 17, 14, -23, 13, -16, 16, 12, 11, 3, -19, 3, -7, -21, -12, -18, -16, 11, 14, -14, 10, -10, -5, -4, -12, 8, 12, -9, 2, -2, -9, -17, -8, 16, -12, 1, -5, -10, 5, -9, -22, -18, -13, -3, -4, 12, -6, -18, -17, -30, -9, 14, 4, -13, -11, 17, 17, -22, -20, 2, -22, -17, 33, 15, -3, 7, 11, 22, 7, 8, -4, 20, -1, -4, -23, 31, -13, 13, -5, 9, 21, 11, 17, 15, 7, 0, 20, 2, 1, -15, -10, 7, -19, 13, 5, -1, 3, 33, -1, 19, 13, -9, -8, -12, -13, 18, 14, 20, -4, -23, 20, 10, 6, 0, 4, 24, -4, -14, 7, 17, 19, 32, 2, 27, 21, 0, -11, -12, 20, -13, -3, 15, -18, -19, 9, -4, -6, 41, -21, 8, 11, 18, -5, 5, 21, 0, 0, 5, 2, -12, 1, -22, -4, 13, 0, -8, -20, 0, 5, -14, 3, 15, 14, 27, -6, 10, -2, -12, -5, 12, -20, 13, 8, 16, 17, 1, -17, -15, -5, 13, 7, -18, 6, 9, 8, 2, -2, 10, 9, 8, 12, -9, -10, -26, -16, -9, 7, 1, 26, 12, -8, -13, -25, 4, 13, 6, 12, -2, 16, -22, 3, 23, -25, -14, -5, 7, 1, -3, 1, 19, 8, 1, 22, 15, 17, 17, -5, -13, 2, 2, 10, -2, -3, 52, -23, -17, -15, -7, 17, 12, -23, 24, -17, -3, -2, -21, 19, -9, -6, 9, -22, -8, -18, -23, -17, -20, -16, 1, -15, 30, 8, -10, -6, -17, -8, 0, 8, -2, -15, -16, 12, -18, -33, 12, -24, -18, -16, -4, 15, -11, -4, 15, 8, 21, 18, -20, -4, -23, 7, -20, -1, 20, 25, 18, -11, 2, 3, 4, -13, -16, 3, -5, -26, 2, 8, -20, 4, 15, -8, 10, -27, -18, 11, -10, -1, 1, 19, -23, 12, 4, 11, 6, 8, 23, 3, 12, 10, -3, 5, 5, -11, 29, 18, 12, -24, 8, 6, 26, -5, 2, 2, 2, -21, -5, -19, 13, 12, 10, 10, 9, -22, 16, 2, -2, 7, 14, -1, 14, 15, -15, 17, 17, 24, 28, 5, 16, -14, 7, -23, 6, 23, 23, 6, 19, 26, -5, 15, 18, -3, 3, -2, 13, 3, -13, -14, 3, -24, -20, -16, -10, -18, 15, -16, -7, -22, 2, 30, 3, 7, 16, -27, 51, 25, -4, -6, -25, -21, 21, -17, 10, -10, 28, 32, -23, 22, 3, -2, 20, -8, 17, 25, -23, -14, 2, 1, 16, 24, 15, 16, 19, 5, -7, 2, 0, 35, -3, -3, -2, -11, -6, -19, -38, -26, 3, 6, -18, -8, -4, 13, 10, -5, 8, -15, -21, 13, -5, 21, 7, 3, 12, 0, -5, 1, 14, 11, -7, -2, -17, -21, -15, 14, 18, -4, -42, 12, 21, 5, -13, 10, 4, -4, 13, -28, -1, 17, -23, 7, 6, -18, 22, 2, -10, -15, 16, 6, 14, -16, 16, -17, 25, -9, 17, 7, 21, -15, 12, 1, -20, 8, -2, 4, 2, 24, 4, -21, -2, 30, 2, -7, 17, -11, 2, 17, 13, -8, -10, -3, -8, -21, -29, 0, 20, 2, -4, 14, -3, -21, 14, -8, 11, -1, -1, 1, 16, 21, -36, 19, 7, -8, -8, -29, -1, 1, -8, 5, 10, 36, 13, 5, 14, -13, -1, 2, -15, -25, -22, -7, 11, -9, 18, 4, -37, 6, -16, -20, 20, -12, 0, -8, -15, -2, -2, -23, -7, -17, 9, 7, 18, 17, -17, -1, -10, 1, -17, 3, 12, -11, -19, 0, 8, -11, 13, 7, 11, -21, -22, 5, 5, -5, 24, -19, -11, 9, 9, -27, 6, 9, -21, -7, -2, 24, 5, -24, 11, -20, -7, 18, -20, -16, -11, 14, -2, -6, -5, 8, 20, 16, -16, 4, -21, 8, 26, 6, -18, -12, 0, 15, 6, -1, 52, -1, 21, -14, -17, -2, -24, -18, -11, -7, 6, 27, -7, 18, 7, 24, 29, 14, 38, -8, 10, 17, 12, -15, 16, -13, 28, -27, 5, 7, -14, 12, -12, -12, 10, -14, 8, 19, 2, 5, 12, -18, 4, 11, -21, -13, 1, 23, 1, -27, 4, -6, -1, -18, 4, 0, 7, -20, 16, 9, -17, -1, 23, -8, -12, -4, 25, -6, 1, 16, -20, 8, -22, 22, 25, -11, 2, 19, -2, -19, -13, -20, -10, 1, 17, 16, 6, 19, -24, 14, 35, -2, -12, 0, 8, 15, 1, -21, -8, -12, -19, 8, 14, 12, -7, -14, 0, 15, 6, -19, -10, 17, -10, 1, -1, -13, -21, -4, 1, -12, -6, 6, -24, -13, 17, -7, -5, -18, 5, -22, 8, -23, -17, 11, -5, -21, -7, 10, 4, -1, 8, -1, -5, 7, 19, -19, 23, 15, 16, -29, 3, -10, -25, 15, 27, 11, -2, 2, 17, -24, 11, -13, -2, 15, 1, 16, 6, -27, 28, -1, -37, -14, 8, -20, 10, 8, -41, 33, 12, 12, -10, 14, 15, 2, 1, -1, 22, -8, 1, -19, -15, -16, 20, -23, -2, -4, 16, 5, -11, 13, -3, -18, 3, -18, -9, 8, -18, 2, -32, 17, 46, -5, -7, -22, -11, 9, -24, -5, -5, -18, -12, 0, 15, 20, -24, -4, 15, -2, 18, -17, 5, -18, -11, -2, -22, -1, -13, -2, 3, -11, -19, -30, 10, 13, 8, 12, -17, -10, 28, -16, 25, -5, -6, -7, 5, -7, -12, 7, 3, -15, 4, -41, -18, 31, -43, 6, 17, 6, -7, 27, -16, -6, 8, 4, 8, -11, -19, -7, 3, 24, 28, -15, 23, -1, 23, 3, -12, 24, 17, 0, 17, 7, 20, 18, -18, 2, 7, -18, 1, 15, 14, -25, -21, -37, -31, -6, -49, 2, -15, -9, 24, -2, -10, -23, 3, -11, -16, 19, -14, 41, 10, 11, 27, -21, 5, -24, 0, 19, 7, 12, 8, -21, -7, -29, 7, -8, 21, 8, 1, -18, 0, 9, 7, -4, -24, 5, 5, 12, 11, 6, -4, 0, -23, 7, 4, -24, -10, -15, -20, 9, 6, -15, -17, 7, -20, -35, -5, -13, -6, 5, 5, -3, 13, -5, 4, 6, 7, -10, -16, 15, -20, -17, 15, -9, 23, -21, 22, -11, -10, 15, 19, 7, 38, 11, -23, -6, -22, -23, 1, -10, 34, -4, -5, -11, -17, -13, -19, -9, 32, 11, 14, -20, 13, 14, -21, 1, 13, 1, 29, -36, 15, -13, -21, -5, -16, 5, 40, 12, -1, 14, -2, 20, 27, 17, -13, 22, -11, -7, -8, -3, -4, -15, 11, -18, 13, 1, 0, -4, 12, 9, -25, 8, 5, 6, 3, -2, 21, -15, -6, 33, -1, 6, 12, 16, 6, 19, 5, 6, 18, 13, 2, 12, 40, 3, 20, 16, 7, 16, 5, -5, 7, -7, 35, -21, -4, 8, -14, -18, -8, 2, 42, -13, -19, 19, -6, -15, -10, -11, 23, -5, 11, 11, 14, -11, 2, 4, 5, 9, 16, -19, -23, -5, 25, -4, 36, -35, 17, -17, 9, -16, 20, -18, -14, 2, -15, 0, 4, -11, 14, 13, 15, 7, -5, -10, 9, 18, -3, 12, -1, -12, 6, 3, 19, -15, 26, -13, 1, -18, -2, 8, -15, 9, -4, 16, 8, -1, 14, 4, 6, -3, 5, 7, 5, -32, -20, 6, 14, 13, -9, -17, -16, 26, 6, 2, 20, 10, 1, -18, -17, 19, 8, 0, 2, -1, -17, 11, 30, -17, -20, -7, 12, -4, -2, -9, 19, 12, 6, 10, -23, 18, 0, -3, 14, -20, -6, 21, -10, 7, 21, -57, 8, -18, -18, 16, -10, 1, 6, -8, 5, -18, -10, 12, 13, -8, 7, 7, -21, -24, 5, -8, -22, -1, -20, -3, 6, -10, -16, -19, -12, 5, -11, -8, 13, 12, 1, -9, 7, 7, -7, -11, -14, -2, 5, -4, -18, -5, 11, 25, -8, -27, -20, -12, -13, 18, -14, 1, -18, 5, -6, 10, 5, -11, 16, -33, -18, 6, -15, 10, -6, -17, -18, -26, -1, 0, 13, -6, -7, -16, -15, 40, 8, 8, 0, 7, -16, 7, 48, 7, 8, -17, -15, -12, -9, -6, 11, 14, -5, 3, -9, -4, 7, -8, 13, -7, -10, 0, 1, -6, 1, 10, 3, 1, 26, 6, 2, -23, 18, -5, -18, 16, 8, 15, -21, 6, -8, -10, 20, 16, -2, -13, 15, 12, 6, -7, -21, 22, -1, 12, -15, 12, 8, 7, 15, -11, -7, -37, 3, -12, 13, 16, -25, 25, -25, -14, -6, -17, 9, 13, 1, 31, -4, -8, -15, -20, -12, 18, 15, -17, 18, 9, -20, 11, -20, 14, 13, 3, -9, -10, 3, -7, -16, -23, 21, -10, 9, -17, -10, 1, -21, -1, 24, 13, 16, -23, 12, -14, -13, -20, -17, -9, -14, -15, 16, -11, 2, -20, 21, -18, 21, -7, 19, -11, -17, 0, -7, -1, 13, -10, 3, -17, 0, -6, 29, 17, -19, 6, 15, -1, 12, 7, -8, 27, -8, -12, 2, -5, -3, 3, 19, -11, 49, -10, -10, -8, 18, 1, -9, 3, 21, -10, 2, -20, -18, -7, -15, 4, 2, 14, -19, 13, 9, -18, -2, -12, 1, -3, 18, -14, 9, -20, 1, -13, 2, 7, -2, -15, 18, -22, 27, -3, -13, 22, 13, -12, -4, -17, -6, 11, -18, 15, 17, 2, 17, -5, -26, 6, 29, -28, 1, 16, 11, 14, 13, -3, 40, -6, -9, -18, 2, 3, -16, 19, 13, -14, 4, 6, 6, -18, -21, 11, -2, -23, -16, -22, -14, 0, -42, 53, 27, -12, 16, 7, -18, -16, -19, -14, -14, -16, -8, 3, -13, -2, -30, 35, 17, 14, -13, -6, 7, 15, 15, 27, -6, 22, -13, -16, -2, 11, 10, 4, 11, 1, 1, -3, -7, 0, 20, 7, -2, 4, 1, -16, -3, 4, -20, 9, -8, 26, 8, -5, -2, -14, 11, 13, -1, 11, 6, -6, 17, 3, -27, 22, 5, 19, 7, -13, 20, 8, -14, 13, 13, 11, 14, -18, -20, -21, -24, 48, 15, 10, 13, 4, -11, -13, 20, 27, 19, 0, -3, -1, 14, -1, 5, 1, -26, 21, 14, -4, 7, 8, 46, 34, 20, 34, 16, -1, -16, 19, 4, 20, 12, -14, -7, -11, 18, 6, -10, 28, 10, 20, -22, -13, -6, -10, 18, 14, 5, -7, -22, 3, 10, 6, 19, 13, 42, -23, -8, 14, 12, 2, -41, 42, -12, 9, 10, -4, -21, 2, -8, 10, 9, 3, -20, 5, 12, -13, 13, 22, 17, -20, 8, 10, 8, 18, 19, 10, -25, -8, 14, -5, 2, 19, 17, 23, 7, -14, 6, 16, 8, -22, 15, -4, -15, 20, 14, -18, 18, -22, 33, -1, 4, -2, 13, 15, 8, 9, 20, 6, -1, 36, 13, 18, 20, -22, 19, -38, 15, -19, 11, 0, -9, 1, 19, -4, -26, 31, 18, -16, -10, 3, -7, 28, 46, -74, 15, -9, -15, 3, -4, 2, 32, -16, -15, -22, 3, 9, -17, 2, 12, 8, 7, 2, -20, -9, 7, -13, -22, -6, 12, 12, -16, -4, 15, -15, 31, -14, -14, 0, 17, 8, -6, 15, 13, -10, -13, -4, -13, -13, 2, 22, -34, 0, -11, -13, 8, 7, -5, 33, 18, -37, -17, 0, -2, 14, 2, 12, -27, -5, -2, -9, 12, -12, 9, 15, -9, 4, 17, -20, -23, 10, 1, -18, -3, 17, -8, 8, -1, 19, 1, -24, -9, 11, 1, -11, 0, 16, 4, 8, -23, 19, -14, 16, 0, 15, 15, -14, 28, 21, -16, -12, 1, -4, -15, 5, -21, 17, -23, -14, 6, -10, 25, 7, 29, -30, 7, 1, 4, -21, 32, 43, 18, -11, 15, -7, -3, 18, 30, 7, 0, -2, 8, -4, -12, 10, 25, -14, -13, 7, -15, 4, 15, -17, -16, -14, -25, 10, 17, -13, -18, 15, 36, 3, -12, -1, -15, -4, -18, 15, -13, 1, 16, 6, 0, -19, -17, -19, -8, -14, 7, -19, 8, -4, -15, -11, 10, 5, -15, 28, -18, -6, 16, -17, -3, 2, -28, 14, -8, -20, -4, -5, -7, 14, 41, -2, -4, -9, -7, -6, 5, 3, 21, 16, -6, -7, -20, -17, 7, 27, -9, 3, 5, -9, 9, -7, 13, -16, 2, -8, -18, -3, -11, 18, 9, 13, 10, 28, -12, -4, -3, -16, -4, -2, 22, 15, 5, -10, -7, -3, 22, -4, 14, -24, -21, -8, 11, 1, -14, 27, 21, 7, -20, 4, 15, 4, 17, -5, 13, -12, -17, 10, -15, 18, 16, 11, -11, 0, -15, 5, 16, -2, 14, -3, -5, -5, 5, -2, -18, 16, -1, 0, 0, 17, 9, -5, 0, 6, -12, -1, 5, -1, 2, 12, -21, 16, 14, -11, -8, -16, -23, -15, -10, -11, 23, 5, -8, 0, -3, -1, -10, 12, -11, 29, -17, 5, 13, 5, 13, -15, 14, 16, 5, 24, -14, 16, 16, -21, 22, -10, 12, 8, 16, 18, -9, -19, -9, 21, -5, 3, -11, 7, 11, -2, -16, -32, 10, 14, -18, -22, -4, 0, 11, -11, 3, 3, 1, 3, -13, -22, -19, -8, -4, -3, -4, 17, 0, -19, -5, 17, 23, -44, -5, -22, 10, 11, 1, 18, 7, 8, 4, 2, -20, 19, 19, -16, -33, 9, 10, -7, 4, 11, -2, -12, -24, -16, 5, 4, -10, -10, 11, 47, 9, -19, -8, -22, -15, -5, 2, 15, -24, -4, 12, 7, -4, -2, -13, 23, -28, -27, 1, -16, -16, 2, -3, -14, 3, 2, -2, 13, -12, -15, -21, -1, 15, -38, -12, 8, 0, -9, 44, -17, 1, -11, 7, -8, -14, -14, -22, -23, -3, -26, -23, -14, -18, -16, 19, -8, 26, -9, -16, -6, 3, -15, -21, 18, -13, 22, -9, -1, -19, 2, -10, -11, 1, -34, 9, -21, -10, 0, 39, -26, 60, -15, 14, 1, 7, 15, -6, 11, -14, -13, -13, 1, -19, 3, -14, -8, -4, 13, -20, 13, 6, -22, 9, -12, -9, 3, 4, -2, -14, -2, -35, -29, 0, -10, 7, -11, -17, -19, 25, -14, 22, 16, 13, -16, 10, -1, 10, 23, -4, -26, -16, -21, -17, -4, -3, -5, -17, -36, 3, 16, -10, -5, -5, 21, 8, 4, 16, -3, -19, -3, 4, 14, -5, 41, -15, 16, -9, -20, -4, 13, -36, -6, -12, -8, -12, -20, 28, 4, 12, 7, -12, 13, -5, -9, 18, -17, -28, 30, 11, -14, 3, 13, 22, -20, 33, -13, 0, -9, -1, 9, 25, 6, -8, 18, -1, -4, 17, 19, 29, 8, -1, -4, 13, 17, -13, 9, 3, 13, -1, -1, -10, 10, 17, 18, 22, 5, 11, -1, 5, 1, -6, -6, 0, 8, 8, 8, -13, -1, 6, 5, -11, 3, 9, 13, 11, 9, -2, -1, -27, 22, -12, 14, -20, 9, -11, 12, -5, 1, -16, 45, 18, 1, -2, 2, -6, 25, -9, -5, -3, 11, 16, 3, 7, 0, -11, 0, 16, 6, -3, -10, -20, -12, 43, -41, -1, 13, 8, 4, 40, 11, 43, -13, 12, 8, 6, -11, 5, 10, 1, 28, -2, -1, 4, 9, 1, 3, 17, -5, 13, 3, -19, -12, 0, 16, -8, -8, -5, 9, -17, 8, 21, 21, 15, 13, -19, 7, -6, 0, 26, -5, 31, 13, -13, -12, 16, 16, 34, -38, 27, 8, -5, 9, -20, -16, -12, 3, 0, 19, -2, 8, -2, 1, -8, -7, 16, 13, 2, 17, -7, -15, 0, -43, -9, 14, 9, 7, -6, -1, -10, -17, -13, -26, -1, -23, -11, 3, -19, -19, -8, 5, 1, -4, 10, 8, -33, -6, 20, 19, -4, 14, -17, 2, 34, -29, -37, 11, -15, 18, 17, -13, -5, -21, -22, -25, 18, -18, -22, 6, 43, -2, -1, -17, -18, 10, 8, 2, 17, 12, 1, 1, -11, 1, 15, 1, 1, 26, 4, 28, 11, 10, 1, 14, -14, 13, 24, -13, -15, 7, -10, -10, -6, -5, -1, 26, -8, -14, -4, -1, -4, 10, -19, 1, 10, -12, -13, 9, 39, -25, -19, -17, 0, -10, -6, 17, -1, -11, 21, -38, -15, 9, -24, 11, 2, 1, -1, 14, 4, -22, 6, 0, 17, 22, 23, 29, 14, -2, -16, 18, 5, 17, -18, 6, 13, -3, -18, -20, -35, -35, -11, 19, 6, 9, 15, -3, -13, -9, -19, 2, -23, 7, -7, 9, -12, -4, -21, -19, 15, -19, -10, -7, 12, -43, -21, -11, 6, -5, -18, 13, 26, -10, -21, -8, 17, -10, 14, -8, 5, 14, -20, 23, -8, 1, -15, 1, 3, 7, -18, 8, -12, 7, 10, -18, -14, 10, 9, 6, -18, 0, 16, 18, -10, 8, -6, -1, 15, -4, 10, -13, -18, -3, -11, 30, -18, -18, 3, 14, -25, -7, -8, 22, 2, 14, 12, 5, -41, -20, 20, 27, -20, -13, -23, -19, -22, -14, -40, 6, 10, -9, 3, -17, -19, -13, -20, 4, 13, 9, 7, -15, 21, 1, 7, 5, 1, -10, 17, -9, 27, 3, -12, 23, -12, -10, -17, -8, -24, 7, -6, 2, -19, 7, 9, -19, 6, 9, -17, 5, -4, 19, -17, 5, 8, 6, 3, 13, 1, 13, -15, -23, -15, 13, -11, 0, -5, 1, -1, 17, -26, 3, -13, -14, -18, -7, 2, -6, 20, -21, -6, -23, -11, -10, 20, -8, 8, -10, -12, -19, -18, 16, 15, -10, 4, -15, -10, 9, -11, -16, 10, -6, 1, 21, -1, -26, 6, 8, -16, -18, -33, 8, 14, 3, 15, 14, -18, 13, -31, -17, 2, -7, 2, -20, -8, 7, 21, 11, 36, -21, -21, -7, -22, -13, -42, 21, -12, -8, 8, 0, -22, 5, -24, -2, 8, -3, 7, -5, -15, 18, 12, -6, 9, -11, -13, 0, 17, -15, 11, 11, -39, 2, 18, 11, -12, 11, -2, 12, 18, 1, -21, 9, -14, -1, 7, -15, -39, 26, -6, -1, 1, -19, 30, -13, 13, -16, -21, 6, -11, -13, -7, -13, 18, 14, -24, -22, -20, 15, -5, 14, -14, -20, -12, -18, 5, -2, 29, -11, -18, 20, 5, -19, -23, 9, -17, -9, -25, -32, -18, -20, 1, -11, -35, -18, 4, 4, 2, -13, -12, 8, -5, 3, 0, 11, -19, -21, 16, -7, -17, -3, -35, -12, 0, -4, 5, -14, 4, 9, -17, -5, -9, -13, 12, -16, 36, 5, 20, 17, 3, 3, -19, -17, 12, -17, -18, -8, 12, -18, -11, -13, -25, -15, -19, -24, -14, -11, -8, 7, -14, 9, -4, -2, -14, -1, 6, -14, -11, 14, 33, -27, -17, -13, 6, 2, 5, -18, -1, 13, 11, 7, 11, -12, -20, 18, -18, 2, 12, -7, -14, -16, -9, 13, -2, 25, 16, -14, 0, -16, 1, -32, -19, 15, -17, 13, 13, -23, 3, 13, -25, 6, 18, 5, -18, 13, -24, 6, -18, 18, -10, -13, -3, -6, 4, -30, 35, -24, 5, -7, 2, 9, 10, -11, 20, -21, -20, -14, -16, 7, -22, -5, 7, 9, 12, 4, 17, 5, -23, -44, 19, -9, 19, 9, -22, -15, 3, -51, 31, 1, 19, 15, 19, 11, 14, 5, -4, -10, 16, 1, -19, 19, 33, 3, 7, -4, -3, 10, -21, -17, 46, -64, -12, -34, 14, 1, -14, -2, 20, -9, 14, -28, 17, -12, -12, -5, 10, -27, 16, 1, 4, -4, -2, -19, -6, -26, 29, -10, -17, -9, -2, -10, 13, 17, 30, -6, -17, -8, 5, -18, -22, -16, 45, -31, 7, 7, 4, -10, 13, -14, 18, 5, -4, 6, 5, -16, 10, -17, 51, 12, 5, -4, -3, 12, 1, 3, 12, -8, -11, 18, -12, 1, 27, -14, -9, -13, -10, -23, -21, -9, 14, -17, 34, -27, 21, 3, -19, -9, -1, 2, 14, -14, -10, -5, 20, -17, -23, -18, 10, -1, 17, -6, -19, 8, 29, -24, -38, 8, 11, 14, -10, 9, 6, -21, 21, -22, -7, 12, 19, -8, -17, -12, 11, -20, 14, -9, 20, -15, 44, 9, -7, -16, -13, -23, -21, 5, -16, 14, -12, -14, 4, -12, -6, -2, 5, -4, 26, -11, 19, 17, -20, 6, 41, -21, -19, 3, 17, 5, 1, 19, 6, -17, -22, 12, 13, -20, 11, 0, -18, 5, -15, -21, -21, 7, 0, -17, 28, -19, 7, 0, 8, -24, 19, -18, -10, -10, -19, -14, -3, 17, 0, 21, 4, -27, 7, 25, -11, 17, 7, -20, -2, -13, -10, -26, -21, 11, -4, -17, 15, 33, -29, 9, 9, -22, -8, -6, 19, 7, 12, -3, -17, 15, 2, -10, 1, -2, -21, 11, 17, -16, -19, -9, -12, 3, -6, -10, 6, -18, 11, 2, 7, -26, 7, -21, 1, 2, 19, -20, -22, 3, -7, -18, -23, -11, 20, 13, 10, -23, 5, 4, -6, -13, -20, -19, 14, -33, 32, 26, -24, 19, -23, 16, 9, 0, -15, -17, 9, 8, -18, 0, -3, -2, -14, 5, 11, 6, -1, 9, -19, 23, 25, -19, 8, 9, -7, -8, 30, 35, -12, -16, -7, -1, -16, 12, -5, 6, -39, -17, -17, -17, -14, -1, 5, 4, 24, -8, 15, -21, -19, -15, 0, -24, -11, -2, -11, -18, -12, -9, 0, 17, 8, 4, -13, -4, -13, 18, -22, 5, -3, -20, 0, 2, -13, 5, 9, -8, -33, 10, -8, 11, 13, 1, 7, 1, 17, 27, -12, -21, -23, -16, -12, -5, 8, 14, -20, 2, -8, -22, -14, -14, -23, 15, -15, 3, 6, 1, -23, -9, -28, 20, 4, -18, 8, -13, -7, 4, -9, -18, 4, 7, -18, -4, 7, 4, 8, -1, 10, -16, 18, -15, 6, -30, -9, 6, 11, -5, 16, 13, 10, -1, -1, 18, 1, 14, 7, -7, -12, -3, 9, 20, 7, -13, -3, -9, -13, -26, -9, 13, 0, -5, -18, -22, -18, 17, 5, 13, 4, -20, 1, -16, 7, 24, -18, -14, -22, -19, 5, -6, 12, 20, 21, 11, 6, 18, -5, -5, -28, -20, 9, -23, 2, -23, -18, -10, -12, 18, 18, 16, 7, -4, -1, 19, 9, 11, 24, 17, -9, -6, 15, 2, 29, 5, 7, -22, 5, -8, -21, 18, 1, -27, 20, -5, 8, -7, 2, 15, -24, -2, -7, -9, 13, -21, -7, 11, -4, 7, 3, -20, -14, 19, 4, -1, -23, -23, 22, 2, -7, 8, -14, 15, 15, 23, 18, 24, -10, 6, 21, -1, -8, 25, 25, -21, 14, -11, 16, -15, 9, 25, -27, 3, -3, 8, -17, -20, -8, -26, 10, -17, 17, -2, 4, 14, -14, 1, -5, 13, 13, -5, -17, 18, -7, 32, -4, -26, 1, -3, 20, -15, -11, 10, 19, -16, 8, -13, -23, -17, 10, 7, -1, -1, 6, 11, 12, 0, 12, 8, 0, -32, 5, -15, 5, -18, -33, -2, -3, 5, 14, -16, -17, 16, -3, -12, 18, 26, -15, -2, -19, -22, -22, 6, -1, -5, 3, -2, -17, -2, 23, 2, -13, 3, 17, 3, -2, -22, -15, -2, -2, 24, 3, 11, 18, 10, -1, -5, -32, 15, -12, 20, -21, -11, 0, -29, 8, -15, 5, -18, 4, 15, 6, 23, 8, 12, 15, 9, -20, -5, -12, -10, 3, -10, -17, -2, -3, 9, 17, 5, 9, 12, 4, -4, 15, -5, 34, -2, -5, -28, 7, -14, 11, 9, -40, 23, 18, 6, 10, 5, -7, -6, 4, -22, -6, 6, 21, 0, -16, -14, 17, -7, 3, 2, 10, 1, 13, -3, -41, 28, 13, 4, -2, 17, -20, -3, -23, 24, 3, 3, 10, 19, -15, 13, -20, 24, 18, -2, 0, -3, -9, 3, 3, 5, -1, -19, -14, 6, 11, 0, 5, -15, -21, -23, 18, 0, -10, -4, 15, -16, -8, -18, -8, -17, -1, -20, -14, 8, 3, -11, 6, 6, -12, -2, -13, 14, 11, 20, -3, -8, -19, 15, -19, 25, 19, 23, -21, -20, 7, -19, 17, -10, 13, -3, 10, 15, -17, -9, 19, -24, 19, -2, -9, 2, 0, -4, -25, 19, -18, 15, 17, -19, -18, -17, -26, -11, -7, -20, -12, 8, -4, -12, -7, 1, 14, -21, -6, -6, 21, 9, 2, 7, 10, -1, 6, -2, 8, 12, -33, 29, 0, -7, -13, 0, 5, -6, -19, 12, 16, -2, -12, 14, -2, 18, 12, -6, -3, -16, -8, -5, 17, -5, -7, -10, 15, -16, -8, -17, 14, -13, 5, -2, 20, -2, 16, -7, 10, 4, 13, 3, 8, -11, -22, 8, 4, 18, -1, 13, -7, 15, 11, -16, -8, 0, -9, 25, -8, -9, 10, 17, -2, 14, -26, 13, -8, 18, 14, 15, -17, -13, -25, -6, 13, 19, -13, 28, 23, -11, 9, 7, -6, 24, -8, -17, -2, -18, 6, -4, -16, -4, -1, -4, -42, 7, 17, -1, 16, 11, 15, -35, 25, -13, 20, -6, 19, 13, 4, 1, -3, 10, -22, 0, -4, 6, -14, -16, 9, -9, -3, 3, -18, 14, 7, 33, -2, -23, -27, 12, -9, 14, -18, 11, -13, -17, 8, -11, -7, -14, -1, 13, -15, 12, -13, -17, -14, -9, 10, -8, 11, -1, -22, 6, -22, 24, -13, 3, 12, -27, -3, -5, -3, 5, 13, -23, 30, -17, -21, 6, -12, 22, 7, -43, 4, -8, 8, -6, 15, 0, -3, -14, 13, -24, -5, 17, -3, 0, -39, 10, -3, -26, -1, 14, -5, -16, 18, 20, -16, -7, -16, -16, -25, 19, -7, 2, 20, 9, -5, 14, 17, 5, -10, -4, -2, -7, -3, -15, -8, -13, -33, 18, 9, 3, -19, 6, 14, 14, -22, 8, 18, -4, -20, 10, -9, 2, 11, -8, -26, -16, 16, 4, -6, -15, 13, -17, 9, -23, -10, -17, -25, -12, 2, -1, -15, -12, 7, -8, 13, -6, -3, -10, -4, -14, -6, 11, -15, -33, -11, -35, -10, 11, -22, -1, -14, 2, -18, 4, -10, 6, -7, 14, 6, 17, -11, 2, -1, -11, -19, 18, 3, 29, 10, 10, -3, -2, -21, -3, 9, 2, 7, -22, 7, 18, 13, -21, -23, 9, 15, -14, 7, -9, 14, -38, -3, -42, -20, 2, 17, -28, -13, -10, -26, -7, 2, -5, 2, 11, -21, 23, 12, 2, -29, 22, -2, 8, -20, -6, -26, 1, -16, 15, 16, 6, -14, 13, 11, -6, -13, -9, 26, 5, -15, 5, 10, 6, -5, -4, 5, -18, -15, -5, 15, -22, 7, -20, -2, 24, -11, 7, -22, -17, -14, 15, -18, -20, 10, -8, -13, 9, -27, -1, -25, -13, -20, 15, -21, -18, 19, -17, -26, -9, -9, 24, 5, 22, 42, 14, -7, 4, -21, -41, -4, 14, -13, 20, -10, -27, 6, 25, -17, 10, -5, -5, 2, 37, 7, -12, 14, -24, -2, -8, 9, -6, 1, 0, -9, 1, -20, -6, -3, -4, 11, 7, 18, 27, 9, -11, 7, 6, 14, 22, -12, 6, -78, 23, 9, -17, 1, 7, -21, 17, 5, 2, -8, 7, -12, -3, 18, 5, 0, 7, -28, 16, -9, 19, -2, -26, -25, 14, -15, 2, -23, -13, -5, -22, 13, -5, 18, 4, 17, -16, 8, 15, 7, 17, 2, 8, 13, -7, 0, -3, 4, 23, 3, 8, -15, -6, 2, -11, 9, 15, 1, 22, 4, 14, -9, -1, 6, 33, 4, -17, -10, -2, -1, 4, 21, 3, 21, 3, 15, 3, -4, 5, -14, -14, -7, -3, 10, 15, -20, 6, 42, -15, -6, 6, -11, -7, -14, -7, 11, 17, -7, 15, 14, 4, 11, 18, -16, -2, 27, -17, -19, -14, -15, -17, -6, 7, 18, -11, -6, -7, -16, 4, 0, 9, 14, 19, 1, 4, -12, 10, 7, -16, -5, 1, 9, 20, 9, -14, -16, 5, -20, -17, -5, -13, 9, -5, 48, -9, 9, -10, -7, -48, 15, 16, 3, 6, -33, 17, -22, 7, 9, -15, -17, 5, -19, 9, -4, -15, 8, -14, -20, -7, 32, 8, -9, -18, 4, -34, 3, -16, -11, -8, -3, 11, -2, 7, -24, 14, 1, -6, 8, 28, -4, -16, -47, 15, -13, -7, -4, 55, 15, 1, -16, -15, 19, 5, -13, 5, 12, 16, -23, 13, -18, 38, -11, 0, 15, 0, -7, -5, 5, -30, -3, 5, -17, 31, 9, -3, -9, 26, -8, -7, -15, 16, 2, -26, 4, -2, -14, 12, -15, -9, -17, 40, 12, 2, -17, 18, 19, 18, -13, 5, 35, -1, -12, -24, -9, -14, 12, -6, 5, -6, 16, 1, 14, -6, 4, 13, 1, -5, -15, 30, -21, -19, -28, 24, -8, 10, -6, 53, 16, -10, 26, -32, -8, -21, 4, 24, -6, 4, -8, 18, 8, 7, 3, 17, 11, 9, 34, -26, -4, -10, 2, 11, -3, 26, 14, 6, -5, -7, 16, 0, -4, 32, -1, 1, -10, -21, 9, 8, 9, 28, -5, 12, -7, -15, 1, 7, -11, 8, 27, 14, 19, 8, 16, -18, -7, -15, -3, -3, -7, -24, -14, 20, -8, 9, -11, 3, -3, 34, -21, -11, 9, -14, 20, -8, 35, -10, 19, -4, -9, 17, 29, -15, 8, 7, -18, 11, 13, -11, 9, -23, 8, 9, -19, 19, 6, -20, -14, 12, 5, -13, 12, -6, 10, 8, 19, 9, -19, 10, 8, 9, 8, 16, 2, -2, 3, -13, 5, -8, 1, 8, -4, -46, 21, 33, 2, 5, 14, -26, -26, 14, 11, 11, -4, -1, 6, 16, 4, -6, -19, 14, -10, -7, 2, -61, 10, 4, 4, 7, 5, -10, -12, -12, -18, 17, 8, 11, 0, -5, 12, -3, 2, -53, -46, 17, -20, 20, -8, 9, 21, 8, 26, -29, 22, 10, -9, 5, -3, 33, 3, -3, 9, -13, 12, -30, 3, 2, 1, 11, 13, -6, -23, -2, 6, -11, 13, 2, -17, -14, 2, -35, -6, -2, 7, 26, -16, 14, -1, 18, -11, 10, -10, 14, -4, -27, 14, 12, 25, -17, -15, 16, 12, -28, -13, -4, -18, -10, 4, -9, -18, 4, 4, 4, 12, -14, -56, 19, 1, -22, 11, 1, -6, 3, -10, -18, 8, -4, -1, 0, -31, -1, -10, 0, -24, -8, -24, -8, 20, -27, -12, 10, -2, 26, 5, 7, 0, -19, -3, -19, -20, 27, -13, 6, 48, -50, 15, 0, 0, -14, 1, -11, 24, -9, -14, -4, -23, -23, 3, -21, -1, 28, 13, 29, -12, -30, 2, -20, 26, 7, 5, 1, -17, 10, -20, 16, -1, 27, 12, 13, -16, 4, 12, -12, 0, -14, -1, 15, -18, -13, -2, -12, 14, -34, -10, 5, -13, 37, 12, 27, -11, 6, -7, -7, -13, -7, -19, 2, 4, 21, 8, -32, 9, 7, 3, -26, 9, -26, 1, -21, -18, 15, -7, -7, -35, 1, 2, -32, -15, 40, -21, -5, -16, 6, 27, -14, -5, -4, -1, 0, -19, -26, 22, -2, -6, 7, 0, 16, -13, -30, 5, 13, -24, 24, -19, 6, 18, -34, 7, -16, 15, -9, -15, -25, 33, -4, -13, 9, -14, 12, 6, 14, 7, -16, 6, -21, -12, 19, -6, 19, 3, 15, -1, 11, 5, -19, -14, -13, -11, -20, 8, -53, 20, 3, 14, 9, 15, -15, -22, 16, 15, -2, -14, 0, -12, 18, 31, 8, 10, 8, 7, 3, -37, 30, 8, -14, -28, -46, 8, -16, -4, -20, -17, 13, 1, 15, -22, 6, 17, 4, 1, 2, -3, -4, -15, -12, 63, -27, -6, 12, 0, 12, 0, 17, 28, -28, -3, 7, -18, -13, 12, -12, -13, -17, -22, -5, -15, 22, -13, 27, 43, -23, 5, 12, -3, -9, -5, 3, 10, 12, 12, -15, 14, 11, 2, -8, -5, -7, 3, -6, -17, 11, -5, 16, 1, -8, 11, -1, -3, 11, 4, -23, -40, 8, -3, -6, -24, -2, -6, 10, 6, -20, -22, 40, -1, 2, -8, -49, -10, 37, 7, 28, 12, -3, -6, -18, -29, -3, -25, -9, 4, 33, -25, 9, 0, -3, -1, 17, -8, 1, -4, 24, 0, 18, -21, 19, -13, -18, 4, -26, -8, -2, 10, 7, 16, -29, -1, -24, 4, -8, -16, 13, 1, -4, -16, -48, 30, -16, -15, -16, -12, 10, -21, -5, -21, 5, -5, 9, -20, -45, -2, -42, -17, 9, -15, 8, -23, 17, 1, -28, -18, -24, -14, 18, 14, -6, -18, 4, -16, -9, 11, -4, -2, -15, 12, -3, 2, 7, 45, 1, -8, -4, -15, -10, -12, 3, -1, 12, -4, 16, 11, -4, 9, -11, -14, 10, 12, -1, -24, 26, 0, 17, -7, -13, 16, 11, -8, 5, -22, -1, 2, 36, -23, -44, 9, -33, 21, 6, -13, -2, 20, -3, 13, 19, -3, -12, -4, -6, -11, 37, -19, -18, 25, -9, 0, -8, 11, 15, -3, -38, -3, 28, -5, 7, 2, 2, -22, -22, 18, -27, 19, 0, -14, -1, 6, 21, 47, -12, 2, 23, 4, 7, 8, -6, 8, 0, -18, 17, -21, -16, -17, -12, 28, 13, -14, 7, 16, -28, -10, 17, 60, -11, 14, -19, -21, 22, 0, 25, -5, -22, 17, 16, -20, -7, -1, -9, -2, 9, -2, 27, -14, 0, -19, -23, 34, 16, -6, 24, -5, 18, -16, -20, 6, -35, -4, 24, -6, 17, -22, 7, -15, 24, -21, 3, -18, -3, -9, 7, -4, -14, 23, -22, 1, -5, -11, 55, 19, -9, 12, -15, -3, 37, 4, 18, -9, -4, 3, -9, 19, -17, 9, 32, 9, 5, 30, -4, -6, 12, 5, -28, 36, -11, 15, 1, -9, -17, 0, 33, -17, 6, 27, -15, -17, -12, 14, -5, -1, -19, 39, -5, -17, 14, 4, 0, 19, 21, 28, -15, 4, 27, -1, 6, -12, 8, 22, 12, -22, -26, 6, -19, -26, -9, -16, 5, -20, 28, 15, -32, 28, 5, 35, -21, -7, 12, -19, -26, 38, -9, 30, -32, -16, -5, -4, 24, 4, -18, -10, -21, 12, -25, -19, 33, -22, -6, 35, -1, 16, 24, -18, 23, -6, -8, -1, -43, -22, 9, -27, 13, 3, -39, 0, 15, -8, -12, 14, 1, 0, -37, 18, -15, -5, -2, -9, -3, -14, 7, 0, 7, -9, 12, 2, 16, -1, 4, 19, 11, 13, -25, -6, 13, -30, -7, -31, 22, -25, -14, -8, -23, 11, -15, -33, -37, -8, 11, -7, 17, -5, 2, -2, -10, -5, 7, 10, -3, 12, 15, 6, 20, -23, -12, -13, -16, 12, -3, -3, -7, -1, 1, -5, -14, 5, -16, 37, 4, -22, 29, -19, 2, 20, 19, 18, 13, -21, -14, 9, 12, -26, -17, -21, 10, 5, 9, 0, 10, 19, -19, -10, 17, -16, -18, 17, 6, 1, -21, -4, 0, 8, 19, -1, -30, 6, -21, -43, -23, 13, 10, -23, 31, 11, -3, 36, 23, 16, 10, 15, 4, -4, 7, 9, -11, -22, -21, 10, -8, -22, 9, 9, 7, 19, -4, 17, 22, -20, 3, -20, 7, 13, -16, -15, 5, -15, -30, -12, 15, -8, 49, -1, 2, -11, -29, 24, 1, -4, -28, -1, 8, 2, -13, 5, 30, 4, 1, 14, -26, 28, 4, -3, 16, 8, -4, 12, 2, 15, 23, -2, -17, -15, -7, 2, 22, -1, -7, 14, 14, -10, 1, -10, 19, -15, 20, 2, 10, 12, -32, -7, 7, 4, 16, -33, -58, -15, 16, 6, 40, -23, 17, -10, -35, -23, -23, 6, 15, -1, -18, -11, 18, 4, -37, 8, -2, 6, -6, -8, -38, -5, -2, 9, 17, -4, -19, -32, 0, -10, 1, 6, -38, 11, 11, -37, -10, -5, 1, -7, 10, -31, -29, 8, -20, 10, -4, -6, 5, -8, 12, -5, -23, -14, -6, -21, -5, 13, -30, 5, 0, 2, -10, -11, 10, 8, -2, 22, 19, -8, -4, -17, -2, 1, 17, -3, -8, -23, 6, 15, 2, 8, 1, -16, -23, -2, -19, 2, -3, 2, -20, -22, 8, 17, -21, -13, -10, 4, -29, -27, -25, 12, -3, -22, -5, 8, -7, 11, -39, 14, -21, 6, 40, 23, -7, 8, 7, -14, -21, -14, 13, -19, 10, 11, 18, -7, 21, -1, 5, -38, 23, -9, -6, -14, -5, 17, -20, 26, 10, 22, -29, -10, 11, -8, 9, -3, 25, -24, 3, 4, -17, -13, 8, -9, 15, -7, -8, 19, 4, -21, 5, 9, 16, 18, 5, -21, -3, 5, -25, -19, 6, -8, 17, -19, -8, 0, -17, 24, -35, 6, 25, 3, 32, 0, 3, -1, -5, 3, 27, -8, -3, -12, 4, 13, 7, 29, 13, 12, -16, -4, 10, 9, 15, 19, 5, 7, -49, -22, 18, 34, 14, 1, -24, 3, -8, 1, 5, -1, -1, -7, -15, -3, 6, -9, 11, -8, 3, -6, 6, -20, -17, 0, -10, 7, 1, 10, -23, 0, -22, -4, 19, -29, -2, 7, -4, 13, -6, -17, -4, 1, -38, -20, -3, 2, 27, -14, -8, 22, -7, -27, 5, 12, -6, 3, -19, -9, -2, 6, -16, -21, -7, 9, 21, 4, 11, 10, 10, -3, -26, -18, -3, -13, 4, -3, 13, 9, -18, -28, -16, 12, 13, -32, 14, -3, 21, 17, -10, 13, 21, 21, 7, -5, -17, 0, -14, 5, -10, 17, -13, -3, 29, -18, 22, 7, 1, -25, -2, 0, -12, -21, -20, -11, 15, 1, -1, 0, 7, 0, -1, -11, -3, -3, 6, -7, -31, 4, -23, -24, -12, -21, -11, 13, 7, 14, 15, -17, 4, 5, 20, -10, 12, 8, 14, 15, 31, 14, 11, 20, 0, -9, -35, 32, 11, -14, -21, -28, -18, 13, -5, 11, 3, -4, -18, 10, 3, 11, 11, 0, -5, 18, -23, -8, -6, -17, 10, 17, -22, 7, 20, -9, -25, -10, -13, -11, 14, 28, -22, 8, -19, 17, 7, -13, 3, -11, -18, -5, 10, -21, -7, 6, -22, 6, -2, -15, -37, -20, 5, -7, 32, 26, 15, -13, -16, -16, -38, 6, -31, 32, 23, -12, -13, -12, -33, 23, 23, 32, 29, -15, -4, 6, -34, 36, -4, 23, 20, -2, -10, -9, 0, 1, 11, 36, -14, -10, -12, 10, 3, 17, 26, -21, 10, -7, -12, -11, -22, -3, 13, 26, -20, -5, -13, -9, 2, 34, -27, 0, 4, 14, 17, -6, 23, -17, 5, -25, 28, -5, -1, 12, 16, 4, 22, 17, 2, -4, 2, 18, -27, 14, 19, 23, 13, 20, 18, -20, -31, -6, 21, 2, 18, -6, -10, -15, -3, 19, -25, -21, 31, -16, -30, -3, -7, -9, 9, -21, 31, -17, -21, -15, 6, 17, 5, 29, -11, 5, -6, -14, -5, 22, -43, 13, 19, -16, -2, -5, -2, 13, 2, 23, 17, 7, 12, 21, 9, -14, -13, -8, -11, -13, 15, -12, 19, 30, -20, -34, -57, -17, -8, -4, 43, 11, 10, 19, 20, -17, 9, 3, 6, -27, -39, -17, 7, -18, 14, -12, 17, -20, 42, -27, -29, 8, -38, -19, -15, -11, -21, 12, -11, -2, 27, 1, -19, -37, -27, -21, 19, -20, 35, 9, -31, -7, -10, -1, -39, -19, 5, -9, -4, 38, -1, 23, -20, -5, -7, -15, -9, 1, 39, -5, -17, 23, -3, -8, 6, -22, -11, -21, 20, 7, -14, 16, -2, 42, 5, -13, 1, 6, 3, 19, -15, -10, -28, -9, -8, 7, 27, -14, 15, -20, -22, -6, 1, 2, 34, 9, -32, 10, -16, 10, 30, -4, 23, -19, -14, -13, 13, -14, 7, -1, -3, 2, -7, -19, -21, 11, -13, -15, 33, 19, -9, 15, -1, 12, -8, -14, 11, 11, 30, 8, -3, 18, -12, 10, -24, -5, -4, -6, 20, -6, 0, 9, -8, -2, -15, 6, 6, 3, -32, 17, -12, 16, -16, -14, -22, -17, -38, 19, 11, 18, -6, -19, -15, -19, -24, 16, 27, -13, 21, 8, 5, -25, 10, -5, 6, 17, -6, -22, -53, -18, -5, -16, 16, -10, 1, -6, -12, -20, -16, -4, -9, -1, 2, -1, -16, -11, 28, -5, 1, -2, -8, -8, -33, -15, 9, 8, 6, 11, -9, 0, 8, 0, -1, -3, -14, -5, 9, 18, -12, -10, 18, -6, -1, 8, 16, 7, -12, -32, -19, -20, -1, 1, 0, 16, -37, 4, 29, -18, 23, 4, -19, 8, -57, -10, 22, 17, 4, 11, 22, -30, -27, -24, -12, 13, -17, 2, 3, -11, 10, 12, 9, 18, -1, 2, 10, -33, -34, 13, -7, 8, -19, 2, 15, 13, -4, 10, 3, -12, 3, -2, -12, 10, -33, 9, -5, -15, -9, -2, 6, 0, -38, -9, -47, -10, -5, 17, -14, 10, 20, -38, -7, -15, -11, 17, 4, 6, -28, 7, 27, -6, 24, -16, 24, 4, 16, 16, -21, 19, -9, -18, 25, 0, 10, -18, -6, -16, 18, 7, -11, 12, -17, -19, -4, 16, 8, 19, -9, 3, -31, -22, 1, -12, -5, -11, -6, -5, 36, 14, -57, -22, -13, 14, -23, -20, -37, 14, -2, 11, 24, 11, 14, -1, -17, 17, -17, 0, -18, -15, -3, -7, -16, 4, -36, -19, 9, -14, 19, -14, 24, -4, 16, 7, 7, 16, -21, -10, -47, -14, -11, 6, 1, -1, 8, 11, -29, -9, 1, -5, -14, 17, 7, -2, 4, 20, -19, -7, 29, 11, 10, 11, 10, 2, 20, -10, -6, -17, -19, -4, 4, 5, 7, -15, -9, -18, 5, -9, -30, -23, -34, -5, 37, 7, -6, -39, 1, 4, 25, 7, 19, 6, -26, 3, 11, -16, 5, -7, -11, -1, 29, -1, 11, 5, 11, 4, -11, -11, -2, -24, -38, 8, -23, 18, 3, -8, 10, 17, 13, -23, 20, -1, 16, 14, 24, -23, -19, -32, 22, -10, 3, 3, -10, 10, -29, -17, -29, 11, -13, 6, -19, 10, 2, 10, -38, -12, 37, -12, 2, -12, 11, 7, 21, 16, 17, 6, -4, 17, -42, 15, -16, 10, -8, -22, -21, 10, -2, 17, -33, 10, -23, 8, 16, 13, -14, 11, -43, 10, 26, 2, -16, -9, 17, 10, -12, 6, 9, -19, -4, 26, -32, -14, -10, -25, -18, 16, 42, -49, 35, -3, -20, 15, -1, -12, 19, -2, 4, -1, -1, -14, 16, -10, -1, -31, -10, 1, -10, -22, -16, 3, 12, 19, -39, 6, 17, 6, -11, -18, -3, 7, 7, -1, -20, 0, 18, -12, -26, -37, -5, 21, 0, 19, 2, 2, -16, 8, 1, -8, -13, 4, 18, -12, 0, 10, 8, -17, 16, 1, -8, 4, 3, -25, 6, 24, -27, 5, 21, -3, 17, 17, -27, 11, -19, 15, 22, 6, -18, 4, 31, 4, -13, -6, 21, 3, -12, -31, 21, 23, -5, -13, 10, 11, 4, -10, 12, 14, 12, 3, 22, 4, 9, 1, -25, 15, 8, 0, 15, -6, -11, -14, -4, 17, -31, 8, 5, -8, 7, -7, -8, 13, -4, -14, 14, 13, -6, -12, 19, -28, 24, -1, -2, 2, 1, -3, 12, 3, -15, 15, 22, 3, 47, 0, 16, -5, -16, 15, -26, 19, 18, 19, 10, -6, -30, -13, 22, -17, 9, 11, -33, 1, -13, 19, -5, -12, 23, -7, 28, -11, -17, -15, 10, 3, -18, -36, 16, -9, -4, 22, 3, -6, 19, 3, 2, -13, 11, 17, -17, 15, 42, -38, 36, 14, -13, -20, -1, -1, 2, 18, -30, 3, 11, -29, 6, 24, -8, 30, 1, -2, 16, 9, 15, -11, -3, -1, -8, 6, -29, 10, 1, -17, -23, -11, -8, -19, -13, -18, 11, 8, 29, -7, 28, 7, -9, 7, 7, 4, 17, 18, -8, 41, -7, 17, 22, -13, 16, 13, 3, 12, 2, 12, -9, 18, -9, -19, -12, -17, 8, 4, 10, -37, -1, 3, -3, 39, 24, -6, 19, -1, 21, -9, -10, -28, 9, 11, 5, -17, -26, 23, 10, 20, -1, 1, 3, 19, 7, 2, -4, -1, 11, 7, 17, 6, -12, 8, 4, -1, -9, 14, 19, -20, 2, 22, -10, 23, 5, 33, 19, -7, 8, 15, -8, 41, -37, -30, 0, -19, 30, -24, -2, -6, -33, -20, 5, -2, 27, -17, 1, 9, 19, 5, -9, 0, -26, -1, -12, 2, -9, 25, 19, -10, 15, 6, -11, 3, -15, -26, 8, -10, -3, -15, -7, 29, 9, -3, -14, -1, -6, -13, 6, 15, 11, -6, 0, -29, -11, -4, 8, 31, 23, -10, 10, 15, -22, 28, 23, -12, 5, 33, -23, -29, 3, 12, 17, 4, 22, -2, 19, 11, 4, -21, -34, 17, -6, -20, 39, 31, 18, -10, 0, -5, -7, -21, -8, 13, -5, -3, -5, -7, -9, 15, -13, 10, 9, 5, 4, 2, 10, 8, -6, -14, 5, 5, -6, 12, 10, 37, 13, 2, -7, 24, -23, 2, 2, 13, 27, 18, -20, -22, 6, -11, -14, 5, -1, 9, -2, 12, 23, 24, -17, 16, -9, -4, -19, -14, 12, 17, -15, -29, -15, 25, 17, -19, 15, 9, 29, 21, -9, 18, 15, -4, -26, 20, 31, -11, -8, 26, 2, -1, 3, 22, -5, 4, -13, -1, -6, 7, 0, 21, -5, -22, 12, 20, 21, -26, -9, -22, -24, -6, 0, -22, 8, 8, 0, -10, 12, -34, 25, -22, -7, -5, 22, -14, -17, -17, -31, -53, 32, 36, 39, 2, 5, 25, -4, 6, -5, -24, 4, 15, -18, -21, 6, 10, 4, 5, 0, -34, -14, -20, 13, -29, -11, 19, -6, 15, 35, 8, 27, 15, -4, -16, -1, 12, -3, -13, 14, 3, 3, -14, -3, -18, 20, -29, 2, 22, -20, -16, 42, -5, -16, 6, -41, -8, 0, 29, -6, 3, -16, 18, -2, -10, 20, 2, -1, -15, 27, -38, 22, -28, -7, -15, -27, 11, 15, -15, -21, -8, 5, 19, 13, -17, -17, -2, -12, 15, 17, 4, 11, -24, 7, 6, 12, 16, 17, -24, 0, 15, 34, 20, 12, 23, -2, -10, 8, -20, -9, -14, 5, 13, -16, 4, -2, -1, 2, -12, 12, -18, 19, -17, 27, 15, 23, 19, 1, 4, -16, -38, 12, -11, -8, -7, -19, 2, -9, -11, 6, 1, -3, -28, 21, -13, -3, -1, 12, -11, 19, 2, 23, -13, 23, 7, 51, 41, 21, 10, -13, 9, -8, 4, -2, 15, 9, 2, -20, 33, -10, -21, 16, -23, -18, 0, -10, -8, 16, -13, -10, 1, 20, -14, -9, 1, -9, -16, 21, -26, -14, 4, -12, -28, 18, 14, 15, -29, -19, -19, 24, -4, 10, 6, -19, -12, -3, -21, 6, 14, -15, -8, 5, -9, -6, 17, 11, 6, 3, -8, -11, 15, 52, -11, 18, -5, -9, -17, -31, -24, -7, -19, 25, -25, -5, -11, -19, -31, -17, -35, 21, 7, -20, -4, -10, -23, -9, -47, -14, 14, 9, -27, 14, -14, -2, 22, 5, 4, 1, -14, -7, 32, 34, -7, -37, -41, 4, -30, -5, -18, -30, 19, -7, -4, 34, 13, -17, 17, -1, -14, 19, 12, 15, -13, 21, -1, -9, 31, 18, 16, -2, -42, 6, 16, -28, 2, -29, -21, -7, 15, -41, 7, -17, 27, -5, 19, 9, 11, -15, 5, 25, 5, -17, -12, 22, -23, 7, 3, 2, -25, -29, 10, 11, -32, 16, -21, 1, -25, -9, 9, -5, -29, -30, 2, 17, -11, 34, -3, -15, -27, 8, 13, 9, 14, 10, -34, -38, -9, -23, 25, 4, 29, 7, -27, 47, -21, 28, -11, -12, 26, 13, -7, 14, -25, -11, -19, -10, 3, 1, -11, 2, -7, -2, 46, -3, -7, -5, -12, 26, -3, -2, 4, 16, 27, 16, 29, 32, 22, 19, 9, -19, -44, 2, -2, 43, -5, -1, -2, 24, -18, -1, 25, -7, 12, 11, 10, 15, 10, 20, 33, 10, 20, 32, 0, -24, -1, -10, 26, -7, -30, -16, -10, 23, -8, -16, 10, 28, 13, 31, -23, 11, -1, 9, -8, 2, 17, 44, 12, 19, 28, 13, 0, 0, 23, 15, -10, -12, -17, 24, -37, -15, 3, -36, -1, -15, -17, 9, 20, -3, 21, -12, -3, 6, 12, -9, 18, -23, 27, -3, 45, -42, 7, -1, -11, 6, -21, 3, 26, -9, 10, -16, 6, 9, 9, 21, -4, 22, 7, 11, 10, 18, 12, -71, 8, 32, -15, 39, -21, -19, 17, 10, -6, -23, 26, 6, 8, 0, 34, -7, 25, 8, -2, 1, -5, -27, 17, 9, -25, 13, 22, -11, 17, -10, 3, 1, -9, -14, 0, -2, -16, -6, -9, 23, 25, -5, -11, -10, 1, -17, -14, 16, 2, 11, 9, -12, -8, -30, 40, -31, -31, 26, -38, -12, -10, -22, 16, -5, 7, 9, 13, 29, 23, -10, 2, 3, 4, 18, 5, -18, -16, -25, 21, -10, 2, -5, 17, -16, -15, 4, 3, -2, 2, 37, -9, -27, 1, -6, -10, 10, -7, -27, 23, 20, -16, -9, 25, -11, 26, 0, -22, -21, -14, 1, -24, -37, 10, 25, -31, 2, -7, 0, 25, -8, 9, -15, 23, 1, -20, 16, -3, -35, -5, 30, -29, 3, -11, -7, 6, 17, -7, 14, -9, -1, 17, -20, -9, 4, -8, 24, -13, -8, 21, 13, 13, 2, 14, -17, 10, 17, -27, -4, -2, -18, -7, -2, 3, 2, 8, 4, -9, 3, 11, -24, 1, 6, 5, -8, 14, 26, -10, -42, 5, 15, 8, -2, 29, 36, -2, -7, 30, 0, -3, 0, -17, -2, -4, 0, 3, -4, 33, -15, 21, -25, 9, -6, -21, 7, -15, 5, 1, -13, 1, 50, -23, 21, -25, 15, 12, 17, -11, -11, 10, -9, -19, 3, -9, -31, -8, 3, 11, 0, -11, 19, 6, 7, 12, -28, -8, -8, -45, 10, 0, 0, 15, -9, 8, -12, 11, -5, -1, 21, -16, 0, -8, 17, 30, -5, -1, -25, 21, -18, -16, -2, 14, -10, 12, 20, -5, 20, -1, -10, -7, 3, -12, 11, 15, -7, -8, 7, -6, -26, -11, -32, 18, 10, -16, -15, 9, 5, -10, 15, -26, -5, 22, 18, -8, 11, -8, -2, -20, 5, -16, -11, -19, -18, -3, 8, 15, -10, 26, 15, -15, 2, 29, 10, 1, -1, -2, -18, -3, -18, -2, 19, -9, -2, -6, -23, -6, 15, 5, -42, -32, 19, -14, -22, 12, 13, 4, 17, 9, -3, 22, -11, -3, 5, 3, -11, -5, -12, 13, 4, -39, -5, 10, 4, 29, 8, -20, 20, 33, -7, -18, 15, -17, 2, -1, 4, 3, -5, 25, 16, -9, -30, -7, 20, -12, -14, 8, -17, 21, 1, -3, 9, -7, -5, 6, 25, 28, 3, -1, 6, 20, 3, -28, -4, 13, -4, -11, -13, -34, -6, 7, 5, -9, -8, -19, 15, 27, -32, 3, 9, 19, 4, 36, -15, -33, 12, 1, -6, 20, -29, 7, -10, 11, -9, 24, 7, -15, -29, 2, 12, -17, 21, 9, 7, 8, -15, 11, -41, 9, 5, -3, 3, 21, -21, 1, 9, -1, -34, -12, -7, 7, -8, -17, 22, -6, 9, 14, -11, -15, -5, -7, -10, 7, -14, -22, 9, 14, 36, -4, 6, -11, 9, -2, -39, 5, -3, -29, 1, 17, -13, -18, 22, 14, 10, 11, 2, -19, 17, 9, 26, -17, 23, 16, 1, -3, -2, -4, -17, -7, 4, 8, -14, -3, -28, -6, -15, -4, 13, -24, 5, 17, -12, -16, 30, -14, -14, -23, 35, -22, -7, 23, 1, 5, 5, -22, 24, 31, -43, 22, 19, 8, -14, -10, -11, 13, -18, -11, -15, -20, 6, 8, 24, -20, 36, -7, 13, 25, -12, 14, -11, 2, 31, 7, 5, 15, 4, -15, 14, -13, 2, 37, 17, 10, 24, 33, 2, -27, -19, -6, 10, 13, -30, 7, 33, -6, -4, 11, 37, -17, 18, 54, 14, 8, -31, -29, 4, 3, -5, 12, 8, -17, 13, -25, 1, 29, 25, -15, -3, -7, -6, 1, -3, 19, 15, 30, 37, 3, 16, -10, -15, 14, -38, -3, -22, -29, -11, 20, -20, -13, 0, -3, -33, 8, 39, -30, -18, -23, 17, -13, 16, -5, 13, 17, 22, 5, -10, 1, 25, -26, 30, 2, 10, -7, -17, 10, 23, -6, -18, -21, -12, 12, -23, 2, 31, -21, 15, 13, 10, 42, -2, -13, 3, 25, -43, -8, 20, 27, 7, 11, 27, 29, 11, 0, 23, -24, -5, -20, 8, 4, 27, -7, 34, -15, 15, 10, 6, -35, 24, -7, 9, 27, 19, -18, 0, 15, -40, -1, -1, 25, 30, -25, -4, 25, -6, 33, 4, 0, 17, 41, 1, 30, 25, 12, -7, 0, -12, 6, 1, -7, 16, 20, 5, -21, -9, -32, 12, 23, 0, 15, 4, 4, 3, -13, -14, 10, 13, -19, -11, -17, 33, -16, -14, -11, 4, 2, -27, -2, -29, -17, 34, -16, -15, -24, -12, 9, 23, -20, 20, 12, -14, -20, -19, 15, 31, -16, 4, 18, 14, 32, 4, 9, -16, 6, -12, 20, 23, 10, -3, -5, -48, 5, 15, -19, -4, -19, -1, -12, -27, -10, 6, -19, 15, 18, 42, -2, 5, -3, -4, 17, 0, 17, 10, 34, -5, -4, 18, 0, -21, -30, 11, -5, 7, 14, 20, 14, -4, 9, 15, -13, 10, 9, 6, 25, 13, -16, -16, 9, -2, 2, 3, -7, -28, -21, -5, -1, 12, 2, 20, 7, -10, -5, -15, 26, 20, -3, 5, 31, -10, 5, -17, -31, -6, 19, -2, -1, 8, 23, 16, -5, 11, 7, 2, 22, 16, 7, 13, -14, 20, -4, 10, -5, -21, 0, -25, -5, -29, -19, -18, -4, -15, 3, 0, -6, -17, -21, -36, -18, -29, -2, 6, -8, -18, 9, 30, -11, 16, 18, 11, 2, 17, 29, 10, -4, 23, 15, 17, -8, 25, 25, 7, 20, 11, -1, 6, -16, 34, 12, -12, 15, -6, -11, 1, 5, -12, 6, 4, 26, 9, 9, -24, 0, 33, -13, -18, -6, 15, -11, 1, 1, -25, 12, -3, -22, -10, -9, 15, 2, -21, 0, 17, 19, 12, 6, -26, -4, -17, -12, -14, 12, -8, 1, -23, 0, 25, 13, -8, 9, 12, -2, -28, -27, -17, 3, -11, -7, 4, 16, 2, 12, 4, -4, 7, 2, -16, 14, 13, -4, -18, -14, 0, -12, 4, 1, -20, 24, 0, -14, -6, 29, 11, -25, -10, -3, -1, 7, -5, 13, -26, -6, -15, 3, 26, -9, -18, -6, 12, 9, -8, -18, 26, -23, -19, 13, -8, -9, 21, -28, 24, 16, 10, 7, -9, -7, -6, -8, 5, 20, 4, 32, -36, 2, -12, -4, -14, 8, -34, 0, -24, 12, 2, 7, -4, 2, -4, 30, 6, -19, -3, 8, 21, 11, -9, -4, 18, 10, 6, -11, -25, -5, -5, -14, 0, 8, 33, -3, 22, 2, -22, 28, -6, -36, -1, 4, -6, -22, -27, 3, -7, 3, -5, -1, -6, -1, -1, -9, -1, 23, 10, -20, 26, -27, -42, -1, -17, -3, -37, 10, 3, -13, -37, -15, 1, -9, 14, 3, 6, 7, 2, 7, -12, -11, -10, -9, 12, -5, -4, 3, -12, -32, 11, -29, 15, 8, 30, -30, 41, -19, -18, -13, 16, 10, -24, 19, 31, -21, -30, 3, -10, 5, -13, 25, 5, 4, 3, 9, 19, 41, -54, 4, 19, -8, 11, 8, -4, -20, -4, -9, -4, -5, -17, -4, 22, 3, 11, 4, 7, -6, 9, -5, -9, -14, -3, 6, -29, 23, 20, 27, 1, 29, 6, 19, 16, -20, -7, 15, -10, -12, -32, 13, -18, 31, -12, -1, -14, -5, 18, 13, -28, -12, 7, 22, -17, -27, 24, 16, -24, 16, -6, -6, -12, 10, 9, 4, 0, -16, 14, 27, -29, 12, 7, -8, -23, 13, -24, 14, -3, 6, 9, -15, -22, -2, -7, 4, -19, 14, -27, 14, -18, -4, -1, 28, -2, 17, 5, 5, 16, -24, -27, 17, 12, 7, -12, -22, 24, -11, 16, 8, -39, 17, -14, -4, -4, -11, -1, 15, 14, -3, -22, -4, -9, -33, 27, -16, -20, 16, -2, 19, -23, -3, 2, 23, -14, 4, 12, 21, -4, 11, -4, -16, -19, 5, -4, 7, -9, -4, 10, 34, -10, -6, -41, -5, -34, 22, -7, 21, 6, -4, -11, -30, -19, -16, 21, -16, -9, 8, 0, 4, 4, 2, 0, -33, -10, -8, 8, -2, 20, 0, -15, 30, 15, -18, -35, -4, -34, -1, 9, 17, 3, -9, 0, 13, 40, 4, -8, -9, -8, 0, 18, -33, -16, 15, -6, 6, -19, 5, -56, -23, -22, 28, 16, -6, 3, 2, -20, -26, -34, -28, -18, -4, -14, -13, -6, -11, -18, -19, -26, 30, -3, -3, -19, 16, -2, 3, -2, 11, 16, 24, 6, 13, 15, 16, 19, 33, -1, -9, 17, 13, 10, 0, 18, -2, 0, -3, 1, 5, -24, 2, -19, -2, 37, 15, -32, 31, 27, -9, -10, 3, 24, 15, 27, -36, -5, 15, 14, -5, 11, 3, -16, 7, 16, 6, -9, 5, -10, -5, -16, 12, -6, 9, 9, -4, -3, -20, 12, 18, -10, -9, 0, 16, -10, 25, -34, 15, -21, -14, -14, 21, 4, -23, -46, -11, -15, -25, -17, 27, 30, -31, -37, 26, 4, -9, 2, 6, 25, -3, -4, -15, -2, -4, 25, -8, 26, 1, 6, 15, -8, 16, 11, -38, -20, 11, -4, -19, 19, 7, -12, 0, 8, 12, -9, 13, -10, 28, 13, -10, -30, 26, 26, 0, -1, -25, -2, -19, 5, -12, -1, -26, -4, -10, -29, 7, 2, -11, 4, -17, -6, -1, 9, -2, -18, -6, -24, -8, -3, -7, 3, -22, -16, -5, 23, 26, -4, 7, -25, -3, -3, -20, -2, -4, 6, -1, 15, -35, 1, 19, 9, 19, 20, -8, 8, -43, -6, 18, 8, -16, 11, 11, 38, -28, -7, 29, 32, -23, -10, 1, -12, 6, 6, -8, 24, 17, -14, -3, 17, 4, -19, 32, -3, -22, 26, -19, 0, -15, 5, -2, -11, 23, 9, -33, -37, 8, 2, -23, 16, -20, -29, -9, -9, 4, 38, -8, 13, 12, 3, 5, -2, -12, 27, 7, -17, -15, -21, 23, 13, -23, 1, 7, 20, 1, 35, -7, -1, -15, 3, -3, 9, 9, -1, -22, 14, 1, 20, -2, -5, 3, 42, -26, 47, -28, 7, 18, 32, -21, -6, 6, -24, 42, -7, -15, -30, -7, -16, -12, -12, 29, 13, -16, 12, 31, -6, 32, 4, 11, -14, -25, -17, 13, -18, -11, 12, -35, -13, 13, 24, 7, -10, 15, -4, 21, 8, -20, 20, -6, -13, 6, 19, 17, 3, 17, -33, 19, 29, 12, 12, -6, 7, -5, -12, -28, -21, -11, -24, -19, -3, 6, -10, -4, -15, -21, 4, -20, -6, -5, -10, 18, 7, -7, -7, -13, 12, 14, 0, -19, -4, -10, 21, 34, 5, 23, -7, 3, -29, -1, -19, -12, 14, -8, -9, 13, 18, 5, -19, -32, 3, 1, -22, 3, 0, 1, 6, -30, -19, 28, -41, 10, 11, 9, -18, -12, 16, -31, 2, 5, -5, 41, 17, -16, -20, 33, -29, 7, 15, -25, -8, -4, -8, 9, -4, -11, 7, -2, 14, -11, -19, -11, -7, 10, -10, -15, -24, 0, 4, -13, -31, 19, -18, 1, 8, 27, -27, -1, 10, 11, -44, 12, -6, -31, -5, -5, 1, -2, 2, -24, 5, -3, 2, 9, -4, -11, 11, -29, 19, -1, 10, 0, 10, 19, -4, -6, -3, -12, 29, 12, 22, 9, 12, -17, -33, -10, -8, 15, -17, 1, -40, -11, 4, 1, -6, 1, 24, -27, -20, 10, -14, -33, 17, -21, -23, -16, 29, -18, -2, -37, 3, 6, -6, -5, 17, 10, 20, 14, -12, -7, 22, -19, -12, 8, -7, 7, 4, -3, 9, -16, -37, -6, -14, 7, -11, -8, 18, 5, -32, -15, -16, 10, 4, -4, -27, 2, 14, 10, 9, -12, -2, -6, 13, -4, 6, -2, -12, 12, 16, -13, 8, 10, -88, -13, 9, 28, 7, 3, 1, -18, 0, 7, 8, 4, 0, 14, 10, -8, -4, -10, 14, 4, -5, -18, 2, 10, -35, 39, -15, -31, 6, 3, -38, -19, 25, 2, -13, 3, 19, -9, -30, -17, -8, 9, -28, 23, -7, -18, 30, -20, 11, -20, 3, -5, 6, 17, -18, -16, -10, 7, -16, -3, 10, 5, -26, -36, -13, -4, -20, 2, -40, -16, 0, 2, 2, 2, 23, 14, -4, 25, -4, -18, -8, -31, 15, 2, 22, -3, 15, 7, -21, -17, -6, -25, -17, -5, 4, 2, -9, 19, 13, -8, -31, 23, 32, -1, -10, 19, -3, 7, -19, -31, -20, 8, -5, 21, 3, 17, -5, 3, 38, 0, -8, -6, 11, -27, -4, -30, -5, -16, 6, 16, 4, 9, 9, 4, -8, 18, 19, -14, 2, 7, -16, 14, 21, 18, 11, 15, -13, -21, 11, -8, -8, -8, 4, -5, 3, -7, 20, 23, -5, -20, -13, 16, -21, 0, -20, -23, 19, 5, -28, 13, 6, 3, 11, 4, -3, 8, -5, -20, 23, 2, -36, 16, 10, -10, -25, 0, -15, -28, -6, -25, -3, -5, -30, 19, -17, -1, -3, 2, -14, -3, 23, -20, -17, -2, -5, 2, 4, -3, -4, -2, -11, 2, -40, -17, -16, -28, -5, 2, 31, 12, 8, -18, -5, -19, -19, 8, -26, -24, -19, -12, -15, -19, -27, -2, 21, 25, 2, 8, 26, -20, -38, -18, 3, -15, -17, -15, -21, 3, -16, -22, -16, -5, -26, -20, 11, -13, 0, -8, -15, 1, -6, -23, -4, 14, 10, 11, -2, -2, 15, -1, 11, -19, -4, -13, -1, -1, -1, -5, -25, 8, -17, 4, 8, -28, 0, 0, 23, -13, -21, -19, -35, 8, -10, 5, 5, -16, -13, -1, -24, -1, 11, -26, -10, -22, 9, 12, 16, -15, -9, -19, 0, -22, -2, -22, -3, 17, -6, -23, 36, 7, 38, 27, -5, 8, 16, -36, -18, 0, -13, -8, 15, -23, -12, -28, 27, -8, -26, 1, 6, 8, 2, -35, 11, -12, 16, 15, -6, -2, 9, -22, 11, 11, 52, 8, -10, 15, -22, 8, -4, -23, 21, 30, 6, -2, -9, 22, 10, -18, 17, 6, -3, 36, -2, 8, -21, 6, 27, 8, -11, 31, -19, 4, -15, 12, -2, -3, 1, -23, -23, -13, -18, 18, -6, 24, -19, -8, -29, -16, 8, -1, -7, -26, -10, 1, -4, -24, -6, -18, -27, 3, -5, 3, -2, -18, -8, -16, -10, 2, 5, -21, -13, -13, -23, -26, -27, 18, 14, 15, -11, -22, -8, -6, -22, -12, 2, 15, 1, -12, -5, -25, -15, 1, 14, 58, -21, -21, 17, -39, 9, -35, 11, 25, 30, -26, 11, 0, 39, -7, -13, 17, -15, 2, -20, 11, 9, 19, 13, 27, -2, -3, 7, 20, -4, 24, -15, 10, 4, -7, 19, -26, 30, 1, 9, 14, -11, -21, 2, -2, -28, 7, 23, 6, -13, -14, 3, -12, 1, 8, -7, -10, 1, 5, -15, -11, 17, -3, 10, -14, -16, -10, -12, 3, -1, 8, -21, 11, -28, -13, 4, 15, -13, 12, 5, 3, -25, -5, 30, 29, -20, 7, 7, -19, -4, -5, 8, -2, -15, 6, 11, 7, -4, -13, 9, 5, 13, 17, -26, 23, 20, 8, 9, 26, 5, -1, 10, -10, -14, 30, 11, 6, -8, 33, 20, -4, 12, 14, 32, 21, 13, 32, 2, 5, 0, 24, 43, -24, 15, 22, 16, -15, -15, 16, -14, 9, 2, 19, -9, -8, 8, 6, 3, -1, -19, 8, -14, 4, -30, 18, 9, -11, -1, -3, 26, -12, 1, -17, 24, 27, 0, -15, 7, 8, -25, 13, -15, 14, 12, 4, 18, -5, -7, -8, 15, 1, -35, 15, 3, 16, 19, 22, 6, 5, 15, 6, 7, 8, 6, -7, 6, -16, 14, -19, -17, -1, 0, 26, -10, 7, 30, 19, 15, 9, -6, 0, 13, -8, -2, 19, -15, -11, 9, 22, 20, -2, 10, 6, -8, -17, 7, -4, 29, 4, -14, 9, -9, -3, -11, 3, 19, -13, -14, -24, 12, -13, 5, -17, 18, -6, 1, 25, 4, -8, 20, 5, -2, 7, 13, -9, 5, -15, 4, 41, 3, 2, 10, 37, 6, 44, -11, -3, -28, -1, 8, -36, 0, -8, 5, 4, -30, 8, 20, 6, 7, 5, 9, 12, 14, 13, 6, -4, -35, -9, 4, -25, -15, 8, 4, 8, -13, 12, -19, 22, 11, -2, -14, 18, -2, 22, -7, -16, -4, -5, -4, -10, 21, 31, -6, -15, 1, 17, 27, -23, -10, 0, 8, -14, 15, 8, -9, 33, -21, 21, 5, 4, -7, 7, 4, -4, -12, 21, 15, -2, 6, 15, 12, 8, -25, -2, 8, 2, 15, -10, 12, -3, 6, 13, 10, -8, -3, -8, -11, 28, -1, 6, -10, 4, -8, -18, 10, -14, -19, 44, -17, 7, -3, 6, -3, -27, -13, -2, 15, 23, 3, -15, -5, 25, -27, -9, 6, 18, 31, -14, -6, 5, -22, -13, 5, 5, -11, 27, 0, -6, -12, 31, -8, 13, 16, 21, -24, -12, -22, -10, 8, 5, 21, 12, -16, -13, -5, -4, 3, 32, -3, -3, 32, 21, 3, 8, -8, 6, -5, -13, 16, 4, -19, 20, -17, 1, -8, 26, -1, -2, -16, -6, -3, -12, -2, 13, 18, -36, 14, 1, 7, -12, -32, 10, -4, -15, -21, 17, -25, 5, 9, 4, 15, -13, -12, -19, -29, 31, -54, 13, 14, 15, -8, 15, -2, 27, -33, 6, -14, 31, 9, -16, 9, 22, -11, -1, 11, 8, -5, -20, -35, -3, 5, -22, -19, -39, -9, 23, 8, 8, -2, -30, -1, 34, 4, 33, 5, -9, -13, 15, -3, -20, 20, 13, 0, -3, -5, -23, -26, -15, -21, 11, 20, -12, -39, -33, -20, -5, -20, 5, -19, 29, -34, -15, -19, 6, -17, 30, 1, -22, -19, -27, 0, 6, 10, -16, -23, -4, -23, 13, -10, 36, -11, 46, 7, -1, -21, -5, 12, 14, -5, 16, 16, 15, -9, 8, -26, -22, 26, 8, 8, -8, 2, -6, 2, -5, 8, -9, 7, -3, -15, -16, 0, 8, -21, 21, 5, -8, -13, -29, 5, -30, -8, 0, -4, 11, -44, 9, 13, -1, -26, 9, 9, -5, -11, -6, -48, -11, -11, 23, -20, 9, -6, -5, 10, 29, -19, -18, 12, 7, 10, 1, -2, -20, -9, 7, -4, -16, -1, -4, -21, -5, -6, 11, -17, -24, 4, 14, -25, -8, -15, -10, -26, 4, -14, -29, 10, -11, -15, 6, -31, -8, -5, 16, -24, 43, 11, 33, 0, -10, 21, -14, -13, -3, -5, -29, -30, 7, -7, 2, -31, -18, -2, 12, -4, 7, -15, 6, 41, -19, 11, 27, -10, -24, 7, -30, -3, -25, -23, -15, -5, -31, -17, 8, -4, 55, -11, -1, 2, 12, 61, 5, -25, -7, 22, 18, -10, 8, -2, 5, 52, -29, 0, -7, -31, -24, 10, -14, 16, -26, -31, -8, -30, -25, -35, -4, -7, -12, -8, 27, -4, 3, -15, 14, -3, 19, 4, -24, -32, -21, 2, 2, -5, -21, -27, -3, -6, -1, -1, 8, -1, -4, -18, -15, -13, -11, 29, -8, -17, 7, 15, 10, -1, -14, 18, -8, -32, 7, 15, -41, 7, 2, 6, 14, 5, -1, 22, 8, -9, 25, -26, 35, -1, -24, -4, -30, -21, 13, -33, -8, -22, -6, 9, 19, 20, -13, -31, 2, 12, -14, -7, 14, 8, -8, -41, 13, -7, -1, -28, -14, -2, 10, 10, -7, -3, 39, -11, -7, -4, -16, -4, 9, -9, -6, -11, -15, -15, 5, 40, -5, -12, 6, 9, -23, 4, 3, -19, -14, -7, -49, -26, 5, 8, -9, -29, 0, 3, 31, 0, 10, 10, -35, 29, 17, 25, 1, -24, 18, -20, -4, -20, -16, 0, 7, -4, -26, 17, 8, -8, -15, -15, 3, -11, 33, 9, -13, 5, 38, 34, 18, -6, -11, -4, 30, -38, 4, 17, 22, 16, 15, -19, 43, -6, -7, -39, -6, -5, -4, -3, -17, 9, 28, -7, 20, -6, -27, 12, 1, 7, 30, -30, 11, -9, 27, -6, 8, -4, -10, 15, 21, 28, 16, -9, 9, -1, 28, 7, -6, -19, -22, 5, -22, -8, 4, 28, 20, 18, 25, 6, 28, 11, 1, 22, 5, -29, 9, -13, 2, -22, 20, -10, 4, -15, 14, 0, -13, -2, 9, -30, 6, -7, 10, -13, -20, -34, 4, 4, -13, -8, -2, -11, 19, 0, -15, -27, 9, -17, -2, 4, 25, 0, 27, 1, -12, -3, 14, -9, -14, 1, 11, 24, -1, -1, -15, 9, -32, -42, -9, -19, 21, -2, -18, -27, -12, -39, 13, -19, 5, 20, 9, 2, 6, 9, 30, 17, -30, -12, -18, 16, -10, 6, -14, -1, -7, 3, 14, 23, 37, 17, 26, 2, 11, -3, -1, -10, -2, -17, 6, 20, 13, -3, 4, -11, -25, -10, -9, 37, 18, -1, 20, 3, -35, -11, -17, 0, -8, -9, -20, -19, -15, 10, -20, 9, 23, 3, -19, -4, 8, 13, 50, 0, -9, 9, -26, -6, -31, -2, 2, -16, 26, -21, -6, -3, 10, -12, 5, 8, 0, -19, 4, -23, -16, 7, 19, -21, -6, -16, 9, 14, 15, -17, 46, 11, -18, -25, 15, -18, -15, 17, 13, -3, -27, -11, -44, -16, -6, -25, 16, 25, 34, -1, 9, 2, -14, 20, -2, 17, 1, -18, -15, -14, 37, -11, 1, 2, 6, -20, -11, -3, 14, -10, 14, -5, -7, 8, -9, 6, 6, 13, -22, -19, 15, -3, -2, -5, 11, -2, 2, 21, 28, 4, 18, 21, -12, 21, 28, 12, -21, 7, -1, 7, 6, 13, -4, 0, -1, 9, 0, -9, 4, 16, -21, 5, 4, 11, 5, -13, 11, -13, -27, 8, 12, -13, -21, -13, -1, -1, 4, -10, 20, -6, 21, -23, -17, 18, 17, -3, 4, -4, 19, 4, -29, -9, 9, -18, 16, -16, -8, -22, 0, 2, 33, -7, -16, -5, 1, -15, 13, 5, -11, 1, 34, -24, -7, -18, -13, -9, 11, 2, 12, -4, -17, 14, -17, -2, -8, -2, 17, -6, -29, -3, 12, -13, 5, 13, -25, -5, -29, -19, 9, 8, -16, -29, 21, -20, 12, 2, -43, 8, -10, -3, 60, -4, -34, 6, 12, 8, 8, -14, 11, -8, -24, -11, 4, -11, 11, 9, -3, -21, -2, -8, 20, -36, -26, -7, 55, -16, 19, 25, 6, 7, -18, -12, -32, 10, -5, 14, 9, 11, 25, 17, 29, -21, 41, -29, 17, 22, 7, -11, 34, -22, 13, 7, 1, 0, -11, -3, 17, -19, -1, -15, 2, 9, -16, -22, 13, -1, 10, -4, -24, 5, -20, -4, 10, 15, 30, -14, -14, -2, 24, 6, -17, -12, 20, -23, -9, -20, -18, 6, 43, -14, -1, 6, 18, -11, -40, -4, -4, -19, -17, 9, -7, -2, 13, -33, 15, 21, -8, -14, -17, -10, 26, -8, 20, 5, -6, -15, 22, 24, 31, -1, -12, 11, -8, -11, -18, 15, -9, 3, 19, -3, 26, -19, 2, -7, -50, -23, 0, -3, 34, -16, -13, -11, 11, 20, -10, -22, 27, -8, -2, 13, -20, -16, -1, -15, -8, -13, -18, 1, -19, -3, 31, 8, 0, -13, 8, 7, -21, -18, 14, 6, 29, 24, 14, 19, -4, 22, -13, -12, -5, -30, 14, -14, -24, 0, -3, -24, -9, -18, -8, 7, -3, 1, -10, 8, 7, 15, 18, -6, 21, -8, 21, 6, 26, -17, -13, 23, 19, 9, 22, 2, 23, 14, 8, -20, -13, -12, -20, -23, 15, 26, -10, -11, 11, 31, -27, -27, 11, -25, 6, -7, -4, -27, 10, 5, 10, -26, 19, -1, -13, 2, 1, 2, -27, -11, -9, -26, -12, -16, 28, -19, -5, -10, -21, 36, -1, 3, 26, -27, -12, 6, -5, -5, 20, 3, 11, -1, 20, -9, -12, 28, 12, 17, 13, -14, 40, -11, -23, 8, -11, -14, -7, 0, -20, -33, 0, 1, -1, 6, 11, 4, -2, 4, 1, -1, -20, -1, 12, 2, 27, -9, 4, 20, -15, -5, -22, -28, -2, 8, -21, 10, 7, -18, 10, -21, -12, -5, -17, -13, -10, 1, 29, -4, 11, -30, -3, 0, -6, -6, 12, -12, -5, 6, 7, 17, -21, -26, -12, -14, -10, -29, 17, -3, 10, -25, -2, -21, -6, 8, -11, -5, -11, -20, -12, 1, -24, -17, -16, 2, -4, -24, 14, 3, 8, 21, 8, -9, 24, -12, -5, -24, 37, -13, 21, -21, -8, 5, 11, -1, -10, -18, 14, 17, 7, -13, 6, -1, -17, 2, 11, 2, 20, -17, -21, 20, 25, -15, -14, 18, -10, 8, -2, -24, 2, 35, -9, 2, 25, -7, -2, -16, -2, -28, 6, 9, -5, 27, 9, -3, 1, -10, 23, -7, -3, -11, -3, -12, -2, 2, 26, -13, -21, 2, -2, -9, -17, -20, -18, 2, 8, 0, -12, -7, -10, -26, 0, -5, 3, 9, 12, -15, 18, -29, 3, -7, -3, -4, -1, 2, 8, -11, -20, -26, 24, 17, -5, 3, -7, 1, 6, 9, 23, 3, 5, -24, -7, 6, -19, 4, -6, -24, 19, -6, 0, 5, 10, -10, -40, -25, -14, 9, 13, 14, 16, -2, 3, -17, -37, -1, 2, 4, -17, -8, 21, -17, 11, -13, 10, 21, -13, 20, -2, 20, 15, 4, 6, -14, 7, 12, -21, 7, -16, -11, -11, -24, -4, 8, 9, 20, 14, 0, 0, -30, 7, 21, 15, 13, 1, -19, 1, -16, -16, 8, -10, -22, 12, -18, -10, -17, -2, -10, 10, -18, 12, 12, 2, -19, 16, 13, -14, -19, -27, 4, -25, 0, -15, 17, 13, -18, 0, -23, -3, 29, 23, 11, -4, 16, -11, -7, 30, -10, 10, 16, -6, -20, 23, -22, -5, 12, 3, 12, 18, 19, 15, 4, 15, -4, -20, 25, -3, 9, -15, 10, -6, 1, 0, -35, 6, 24, 2, -2, 21, -18, -2, -11, -18, -13, -27, -18, -5, -5, 9, 25, 15, -16, 17, -8, -21, 0, -11, -20, -27, -31, 27, -24, -22, -15, -5, -14, -15, 4, 25, -22, 31, -16, 18, 2, 7, -18, 4, 2, -26, -18, 30, 6, -2, -6, -8, -2, -11, -12, -14, 2, 11, -11, -6, 17, 2, -2, -28, 7, 24, -28, 20, -24, 14, -22, -21, -6, -23, 8, -4, -12, 25, -31, -3, -11, -17, 21, -16, -15, -19, 17, -20, 5, 21, 21, 3, -5, -18, 6, 30, 19, 5, -14, -1, -25, 8, -6, 15, 8, 21, -2, 25, -11, 3, -14, -11, 16, -18, -22, -11, 2, 18, -7, 12, 19, 5, -3, 3, -2, 15, 4, 18, 18, -1, 25, 8, 13, 36, -26, 9, 22, 10, -10, -2, -6, -1, -12, 27, -20, -24, -7, 16, -17, 19, -21, -2, -13, 4, -3, 15, -21, 9, -28, -9, 31, -6, 6, -17, 13, 4, 17, -31, -3, 17, -2, 28, 21, 4, 8, 7, 11, 16, -19, -14, -19, 4, 10, 22, 36, -4, 26, -3, 7, -17, -4, -15, 12, 39, 13, 51, -28, -3, -15, 29, 39, 10, -16, 7, -3, 1, 8, 26, 19, 15, 28, 0, 6, 2, -15, -6, 26, 6, 9, -11, -3, 17, 7, 10, 7, -28, 24, 8, -7, -5, -17, -24, -8, -9, 27, -30, 27, -9, 1, 22, 22, -38, 21, 30, -4, -18, 14, 29, -4, 26, -12, 19, -27, -12, -30, -18, -1, -14, 12, -3, -17, 19, 7, -20, -14, 11, 21, -17, -12, -1, -2, 2, -6, 17, 14, -32, -8, -3, 17, 21, 19, 7, -33, -14, -16, -20, 3, -5, 10, 3, -5, -2, -28, 6, -2, 19, -19, 2, 19, 18, -3, 17, -22, -6, -6, -10, 6, 16, 5, 4, -5, -16, 19, 17, -7, 21, -11, 29, -23, -15, -13, 5, -4, -4, -8, 5, -6, -27, -7, -6, -19, 36, -1, 15, -10, -9, 4, -22, 26, -6, -10, 33, 0, -4, -3, -22, 10, 4, 8, 11, 11, -20, 10, -6, 4, -1, -13, 19, 2, 8, 11, 23, 13, 24, -13, 8, -25, -12, 4, 11, -25, 10, 15, -10, -20, 6, 5, 1, -14, 12, -12, 31, 20, -12, 7, 31, -4, 3, -6, 9, 3, -2, -6, -7, 2, -5, -8, 7, -20, 28, -25, -9, 26, 23, 6, -2, 9, -16, -20, -14, -3, -21, -2, -12, -17, -5, 18, 4, 21, -13, 9, -7, -7, 7, -3, 17, -5, 21, -25, 3, 5, 24, 17, 0, -7, -3, 1, 26, -1, 9, 1, 32, -18, 19, -23, -8, -13, 8, 10, 6, 12, -8, 14, 0, -6, -24, 3, -10, -7, 6, -7, 14, -27, -10, 14, 12, 6, 3, -22, 8, -2, 15, 16, 5, -17, -10, -18, 1, -29, 6, 0, -20, -11, 3, -17, -22, -1, -6, -7, -46, 2, -7, -13, -3, -14, -11, -5, -10, -6, 0, 17, 4, -9, -3, 19, -17, 10, -4, -4, 13, -1, 11, -12, 4, 5, 29, 21, -23, 9, -28, 38, -13, -11, -28, 30, -1, 0, 11, 1, -18, 0, 9, -11, -7, -11, -14, 27, 22, -19, -11, 8, 10, -18, -14, -8, 8, 0, 12, -3, -24, -5, -6, 14, -3, 7, 13, -6, -32, -28, -9, -14, -25, -8, 12, -4, 1, -1, -10, 12, 0, -7, 20, -13, 29, -25, 0, -15, 37, 19, 30, -28, 11, -12, -25, -20, 21, -31, 1, 26, -6, 8, -25, -2, 8, 9, -10, 3, 21, -10, 1, 18, 10, 16, -21, 8, 14, 13, 10, 13, -2, 18, 18, -34, -5, -27, -11, -6, 4, -4, 0, 16, -8, -2, -9, -13, 3, -10, 11, 9, -9, -5, 7, 6, -2, -5, -13, -18, -14, 22, 15, 1, 3, 13, -8, 1, -4, -15, -11, 13, 9, -1, -3, 7, 15, 8, 15, -8, 0, -15, 39, -1, 6, -4, 18, -1, 11, 0, 20, -13, 13, 13, 16, -18, -2, -3, 23, 14, -18, 11, -17, 2, -18, 15, -2, -11, -4, -1, 7, 11, -23, -3, -14, -5, -7, 7, -33, 10, -11, -3, -12, 9, 11, -9, -6, 9, 5, -4, -13, 13, -3, 17, -17, 8, -20, 9, 14, -32, -8, -2, 2, -20, 1, 20, 25, -2, -12, 4, -14, 0, 10, -16, -41, 10, 19, -3, -27, 7, -11, -12, -12, 12, 10, -7, -3, -9, 16, -4, 16, -16, -26, 0, 13, 13, -8, -1, -8, -22, 4, -20, 25, -25, -22, -18, 7, -14, 7, -10, 3, -35, 8, -21, -23, 9, -22, -25, 18, 10, -8, -1, 4, 29, 22, 7, 1, 7, 28, -12, -12, -24, 20, 8, -3, 6, 21, -17, 24, 5, 0, 20, -17, -14, -6, -3, -2, -25, -5, -19, 17, -12, -23, 13, -7, -13, 3, 21, -9, 15, -2, 11, -10, 4, 15, 22, -34, -30, -18, -22, 31, -16, 19, 15, 4, -14, -28, 18, -13, -17, 4, -26, 8, 9, 11, 15, 15, -13, 16, 5, -24, 6, 15, 8, 38, -2, 10, 4, 18, -21, -13, -3, -44, 17, 26, -19, -11, 6, -19, -3, 22, -1, 29, 2, 7, -16, 8, 14, 33, -1, -18, 2, -13, 20, 10, -7, -47, 16, 7, -9, -26, -31, 20, -22, -5, 8, 16, 2, 12, -33, -2, 24, -21, 15, 13, -1, -1, -30, 17, 17, 8, 16, 4, 7, -18, -30, 18, 29, 13, 17, -34, 11, 16, 18, -5, -3, 5, 10, 12, 12, 19, 6, -17, -23, 28, -12, -31, -17, 10, 4, 3, -10, 6, -7, 1, -25, -16, -26, -8, -11, -26, -19, -12, 8, 2, -40, -10, -49, 18, -25, -7, -17, -2, 8, 1, -13, -13, -9, 29, -11, -10, 9, -2, -2, 25, 12, -11, -24, -7, -2, 7, 5, 27, 11, 11, -19, -5, 32, 14, 2, 4, 1, 7, 0, 6, -45, 6, 11, -13, -9, -4, 10, 20, -16, -8, 7, -37, 10, 2, -5, -7, -2, -11, 20, 16, -21, 20, -17, -31, 33, -26, 6, 7, -21, 0, -16, -11, 10, -17, -36, -21, 1, -7, 12, 1, -10, 8, 14, 1, -11, -25, 1, -9, -10, 54, 11, 3, -11, -2, 16, 22, -1, -18, 14, -8, -3, -11, 4, -11, -27, 14, -14, 4, 9, -5, 7, 4, -19, -24, -5, -17, -10, 28, -1, -14, -25, -4, 17, 14, 12, 12, -14, -12, 12, 15, -25} + +#define TENSOR_DENSE_KERNEL_0_DEC_BITS {8} + +#define TENSOR_DENSE_BIAS_0 {19, -29, -30, 28, -15, -17, 6, 6, 8, 35, 4, -17, 12, -28, -17, 12, -13, 18, -22, -3, 17, 24, -6, -11, -22, -5, -11, 17, 29, -18, 24, 48, -24, -12, -91, -28, 31, -70, 8, 34, -10, -13, 39, -2, 22, 41, -15, 38, 22, -35, 31, 7, -11, 58, 17, -14, 32, 45, -12, -20, 32, -14, -12, -12, -3, -27, 27, 0, -17, -1, -14, 35, 32, -25, -19, 15, -24, -46, 62, -18, -23, -20, 46, 19, -2, -22, -17, 40, -1, 35, 31, 34, 62, -86, -4, -14} + +#define TENSOR_DENSE_BIAS_0_DEC_BITS {11} + +#define DENSE_BIAS_LSHIFT {1} + +#define DENSE_OUTPUT_RSHIFT {9} + +#define TENSOR_DENSE_1_KERNEL_0 {-55, 67, 47, -19, 50, 47, 15, -41, 28, 35, 13, -67, -11, -4, -54, 6, 14, -13, 10, 65, -59, 10, -59, -54, -19, -35, -3, 16, 37, -71, 46, -25, 42, -62, -67, -28, 17, 26, -57, 48, -16, -28, 62, 32, 48, -15, 54, -21, -35, 14, -22, -9, 45, 15, 32, -52, 52, 22, -54, -4, -3, 15, -58, -1, 55, -54, 58, -89, -27, -39, -63, -69, -40, 31, -2, -61, 41, 52, -53, 10, -10, 57, 12, -46, 43, -15, 43, -17, -68, -34, 22, -89, -25, 18, 2, -40, -61, -53, -18, 51, -55, -7, 8, -16, -43, -66, 80, 25, 43, 24, 23, -49, 44, 1, 7, 56, -27, 60, 31, -84, -44, 21, -38, -48, -29, -40, 53, 57, 11, -85, -40, -37, -40, -65, 16, -3, 33, 34, -21, 61, 29, 56, -50, 2, 28, 29, 6, 15, 10, -23, 10, 8, -3, -44, 8, -16, 8, -22, -44, 45, 30, 47, 51, 46, 39, 22, -9, 44, -11, 37, 67, 37, -21, 11, 8, -61, -58, 25, -29, -36, 41, 61, 15, -10, -36, -68, -23, -5, -11, 51, -77, 16, -65, -51, -49, 52, 41, 37, 5, 43, 29, 52, -14, 47, 59, -4, -23, 25, 50, 9, -31, 42, -70, -65, 47, -46, -57, 14, -22, 11, -78, 16, -22, -58, 42, 54, 58, 56, 26, -73, 11, -49, -35, 24, 26, -13, 19, 7, 51, 18, -1, -43, -39, 38, 20, 34, -63, -73, -18, 44, 25, 44, 34, 11, -54, -47, 57, -15, 22, 47, 43, 42, -71, -75, -40, 28, -44, -41, -24, -26, 47, -13, 5, -7, 45, -81, 10, -46, 57, -18, -37, 50, 58, 20, -23, -11, 44, 23, -82, -44, 16, 16, -90, 24, -66, -36, 58, 43, 38, -49, -49, 54, 43, -18, 46, -14, -59, 46, -20, 43, 66, 6, -40, -31, 36, 17, 52, -20, -70, -61, -29, -60, -38, 21, 58, 44, 0, -26, -21, -45, 24, -58, -43, 25, -65, -21, -55, -65, -14, -24, 23, -49, -11, -27, 60, -86, -72, -2, 0, -19, -86, 45, 22, -32, 58, 35, 41, 13, -62, -17, 43, 17, 7, -51, -39, -44, -9, 49, -89, 53, 17, 44, 17, 42, 25, -62, 7, 45, -13, 28, -31, -49, 51, 49, 46, -21, 47, -12, 33, 60, 56, 35, -62, -38, -77, 17, -52, 18, 45, -95, 39, -35, -88, 53, 55, -61, 1, 36, 22, 15, 69, -50, 41, -92, -13, 32, -76, 14, -25, 46, -38, 13, -47, 29, -15, -38, 33, 30, 29, -43, 0, -51, 47, -30, -4, -17, 13, 60, -12, -29, 12, 10, 38, -10, 54, -10, -27, -17, -3, -40, -46, 67, -28, 2, 57, 50, -68, -32, 42, 8, 40, 50, -42, 23, -11, -63, -83, 42, 48, -37, -19, 40, 2, 12, 45, -48, 51, -14, -92, 3, 42, 26, 16, -60, -83, 31, -11, -47, -57, 32, -72, -54, -22, 31, -10, -18, -6, -30, 36, -65, -63, 21, -24, -1, 55, 16, -10, -81, 30, 29, -27, -47, 17, 42, 2, 24, 41, 14, -16, 48, 11, 34, -45, 19, 58, 46, -39, -44, -70, -63, 71, -3, -87, 37, 55, -49, -24, 42, -86, -3, -29, -25, 31, 28, -64, 52, -44, -44, -35, -63, -72, -63, -26, 3, 40, 8, -47, 13, -46, 66, 45, 42, -57, -28, -63, 37, 41, -28, -17, -39, -45, -63, -38, 37, -81, 1, -50, -9, 55, 47, -104, 11, 4, -75, -42, 38, -52, 43, -1, 50, -61, 43, 20, 47, -46, -32, -6, -40, 64, -49, -32, 32, -17, -34, 36, -83, -57, -14, -42, -46, -44, -24, -15, -50, -17, 37, -33, -89, -72, -17, -51, 27, 17, -45, -9, -45, 49, 30, -11, -45, -57, 47, 7, -46, 75, 35, 57, 7, -48, -59, -4, 41, 37, -29, 59, -79, 51, -27, -56, -36, 37, 16, 29, -41, -4, 21, -18, 16, 11, -67, 2, -22, 28, 33, -1, 35, -6, -61, -44, 16, -21, 31, 40, 23, 33, -63, 7, -30, 9, 51, 35, 40, -36, -20, -59, -37, -76, -45, 41, 35, -29, -45, -61, 31, -69, -25, 47, -18, -43, 23, 3, 18, -14, 11, 53, -31, 23, -81, 37, -20, -50, 22, -15, -31, -44, 25, 45, -42, 34, -88, 29, 3, -5, -24, -27, -40, 0, 33, -10, -51, -17, 41, 55, -83, 37, -17, 34, -37, 52, -52, -11, 41, -33, -28, 32, -46, 19, 53, 59, -79, 12, 5, 28, 29, -66, 43, -34, 26, -3, -23, -25, -65, -14, -13, 3, 14, -46, 71, -42, 1, -47, 30, -36, 16, 21, 51, 39, 24, -16, -29, -48, -3, 25, 38, -44, -71, 7, -30, -23, 55, 54, -56, 16, 4, -33, 20, -37, 13, -44, 24, 29, 27, -1, -76, 13, -15, -25, -35, -38, 56, -4, 25, 38, 27, 34, 14, -5, 18, -19, -85, -69, 22, 24, 11, 31, 17, -48, -32, -65, 46, -11, -36, 15, -31, -37, -19, -17, 6, 46, 43, 55, -42, -58, 59, -24, 33, 51, 27, 28, -41, 36, 33, 24, -58, -8, 55, -13, 28, -2, 52, 31, -33, -10, -40, -56, 3, -30, -8, -10, 9, -70, 16, 38, -50, 34, -73, 37, -34, 39, 70, -40, -10, -22, -46, -43, 4, -53, 41, 48, -34, 14, -47, 56, 25, 12, -14, 37, -12, 5, -56, 39, 8, -10, -48, 40, 9, 39, -53, 48, 60, -48, 37, -18, 29, 20, 43, -43, -9, 3, -53, -26, 8, 51, -21, -20, 51, -5, 67, 1, 43, -36, -23, 2, -49, 53, -45, -39, 41, 47, -28, 20, 3, 16, 45, -31, -13, -71, 17, -76, -14, -31, 48, -22, -19, -5, -32, -26, 38, -53, -28} + +#define TENSOR_DENSE_1_KERNEL_0_DEC_BITS {8} + +#define TENSOR_DENSE_1_BIAS_0 {-27, 45, -79, 21, 36, -19, 9, -24, 46, -42} + +#define TENSOR_DENSE_1_BIAS_0_DEC_BITS {11} + +#define DENSE_1_BIAS_LSHIFT {0} + +#define DENSE_1_OUTPUT_RSHIFT {9} + + +/* output q format for each layer */ +#define INPUT_1_OUTPUT_DEC 7 +#define INPUT_1_OUTPUT_OFFSET 17 +#define CONV2D_OUTPUT_DEC 6 +#define CONV2D_OUTPUT_OFFSET 3 +#define RE_LU_OUTPUT_DEC 6 +#define RE_LU_OUTPUT_OFFSET 0 +#define MAX_POOLING2D_OUTPUT_DEC 6 +#define MAX_POOLING2D_OUTPUT_OFFSET 0 +#define CONV2D_1_OUTPUT_DEC 5 +#define CONV2D_1_OUTPUT_OFFSET -1 +#define RE_LU_1_OUTPUT_DEC 5 +#define RE_LU_1_OUTPUT_OFFSET 0 +#define MAX_POOLING2D_1_OUTPUT_DEC 5 +#define MAX_POOLING2D_1_OUTPUT_OFFSET 0 +#define CONV2D_2_OUTPUT_DEC 4 +#define CONV2D_2_OUTPUT_OFFSET -4 +#define RE_LU_2_OUTPUT_DEC 4 +#define RE_LU_2_OUTPUT_OFFSET 0 +#define DROPOUT_OUTPUT_DEC 4 +#define DROPOUT_OUTPUT_OFFSET 0 +#define MAX_POOLING2D_2_OUTPUT_DEC 4 +#define MAX_POOLING2D_2_OUTPUT_OFFSET 0 +#define FLATTEN_OUTPUT_DEC 4 +#define FLATTEN_OUTPUT_OFFSET 0 +#define DENSE_OUTPUT_DEC 3 +#define DENSE_OUTPUT_OFFSET -7 +#define DROPOUT_1_OUTPUT_DEC 3 +#define DROPOUT_1_OUTPUT_OFFSET 0 +#define RE_LU_3_OUTPUT_DEC 3 +#define RE_LU_3_OUTPUT_OFFSET 0 +#define DENSE_1_OUTPUT_DEC 2 +#define DENSE_1_OUTPUT_OFFSET -4 +#define SOFTMAX_OUTPUT_DEC 7 +#define SOFTMAX_OUTPUT_OFFSET 13 + +/* bias shift and output shift for none-weighted layer */ + +/* tensors and configurations for each layer */ +static int8_t nnom_input_data[784] = {0}; + +const nnom_shape_data_t tensor_input_1_0_dim[] = {28, 28, 1}; +const nnom_qformat_param_t tensor_input_1_0_dec[] = {7}; +const nnom_qformat_param_t tensor_input_1_0_offset[] = {0}; +const nnom_tensor_t tensor_input_1_0 = { + .p_data = (void*)nnom_input_data, + .dim = (nnom_shape_data_t*)tensor_input_1_0_dim, + .q_dec = (nnom_qformat_param_t*)tensor_input_1_0_dec, + .q_offset = (nnom_qformat_param_t*)tensor_input_1_0_offset, + .qtype = NNOM_QTYPE_PER_TENSOR, + .num_dim = 3, + .bitwidth = 8 +}; + +const nnom_io_config_t input_1_config = { + .super = {.name = "input_1"}, + .tensor = (nnom_tensor_t*)&tensor_input_1_0 +}; +const int8_t tensor_conv2d_kernel_0_data[] = TENSOR_CONV2D_KERNEL_0; + +const nnom_shape_data_t tensor_conv2d_kernel_0_dim[] = {3, 3, 1, 12}; +const nnom_qformat_param_t tensor_conv2d_kernel_0_dec[] = TENSOR_CONV2D_KERNEL_0_DEC_BITS; +const nnom_qformat_param_t tensor_conv2d_kernel_0_offset[] = {0}; +const nnom_tensor_t tensor_conv2d_kernel_0 = { + .p_data = (void*)tensor_conv2d_kernel_0_data, + .dim = (nnom_shape_data_t*)tensor_conv2d_kernel_0_dim, + .q_dec = (nnom_qformat_param_t*)tensor_conv2d_kernel_0_dec, + .q_offset = (nnom_qformat_param_t*)tensor_conv2d_kernel_0_offset, + .qtype = NNOM_QTYPE_PER_TENSOR, + .num_dim = 4, + .bitwidth = 8 +}; +const int8_t tensor_conv2d_bias_0_data[] = TENSOR_CONV2D_BIAS_0; + +const nnom_shape_data_t tensor_conv2d_bias_0_dim[] = {12}; +const nnom_qformat_param_t tensor_conv2d_bias_0_dec[] = TENSOR_CONV2D_BIAS_0_DEC_BITS; +const nnom_qformat_param_t tensor_conv2d_bias_0_offset[] = {0}; +const nnom_tensor_t tensor_conv2d_bias_0 = { + .p_data = (void*)tensor_conv2d_bias_0_data, + .dim = (nnom_shape_data_t*)tensor_conv2d_bias_0_dim, + .q_dec = (nnom_qformat_param_t*)tensor_conv2d_bias_0_dec, + .q_offset = (nnom_qformat_param_t*)tensor_conv2d_bias_0_offset, + .qtype = NNOM_QTYPE_PER_TENSOR, + .num_dim = 1, + .bitwidth = 8 +}; + +const nnom_qformat_param_t conv2d_output_shift[] = CONV2D_OUTPUT_RSHIFT; +const nnom_qformat_param_t conv2d_bias_shift[] = CONV2D_BIAS_LSHIFT; +const nnom_conv2d_config_t conv2d_config = { + .super = {.name = "conv2d"}, + .qtype = NNOM_QTYPE_PER_TENSOR, + .weight = (nnom_tensor_t*)&tensor_conv2d_kernel_0, + .bias = (nnom_tensor_t*)&tensor_conv2d_bias_0, + .output_shift = (nnom_qformat_param_t *)&conv2d_output_shift, + .bias_shift = (nnom_qformat_param_t *)&conv2d_bias_shift, + .filter_size = 12, + .kernel_size = {3, 3}, + .stride_size = {1, 1}, + .padding_size = {0, 0}, + .dilation_size = {1, 1}, + .padding_type = PADDING_SAME +}; + +const nnom_pool_config_t max_pooling2d_config = { + .super = {.name = "max_pooling2d"}, + .padding_type = PADDING_SAME, + .output_shift = 0, + .kernel_size = {2, 2}, + .stride_size = {2, 2}, + .num_dim = 2 +}; +const int8_t tensor_conv2d_1_kernel_0_data[] = TENSOR_CONV2D_1_KERNEL_0; + +const nnom_shape_data_t tensor_conv2d_1_kernel_0_dim[] = {3, 3, 12, 24}; +const nnom_qformat_param_t tensor_conv2d_1_kernel_0_dec[] = TENSOR_CONV2D_1_KERNEL_0_DEC_BITS; +const nnom_qformat_param_t tensor_conv2d_1_kernel_0_offset[] = {0}; +const nnom_tensor_t tensor_conv2d_1_kernel_0 = { + .p_data = (void*)tensor_conv2d_1_kernel_0_data, + .dim = (nnom_shape_data_t*)tensor_conv2d_1_kernel_0_dim, + .q_dec = (nnom_qformat_param_t*)tensor_conv2d_1_kernel_0_dec, + .q_offset = (nnom_qformat_param_t*)tensor_conv2d_1_kernel_0_offset, + .qtype = NNOM_QTYPE_PER_TENSOR, + .num_dim = 4, + .bitwidth = 8 +}; +const int8_t tensor_conv2d_1_bias_0_data[] = TENSOR_CONV2D_1_BIAS_0; + +const nnom_shape_data_t tensor_conv2d_1_bias_0_dim[] = {24}; +const nnom_qformat_param_t tensor_conv2d_1_bias_0_dec[] = TENSOR_CONV2D_1_BIAS_0_DEC_BITS; +const nnom_qformat_param_t tensor_conv2d_1_bias_0_offset[] = {0}; +const nnom_tensor_t tensor_conv2d_1_bias_0 = { + .p_data = (void*)tensor_conv2d_1_bias_0_data, + .dim = (nnom_shape_data_t*)tensor_conv2d_1_bias_0_dim, + .q_dec = (nnom_qformat_param_t*)tensor_conv2d_1_bias_0_dec, + .q_offset = (nnom_qformat_param_t*)tensor_conv2d_1_bias_0_offset, + .qtype = NNOM_QTYPE_PER_TENSOR, + .num_dim = 1, + .bitwidth = 8 +}; + +const nnom_qformat_param_t conv2d_1_output_shift[] = CONV2D_1_OUTPUT_RSHIFT; +const nnom_qformat_param_t conv2d_1_bias_shift[] = CONV2D_1_BIAS_LSHIFT; +const nnom_conv2d_config_t conv2d_1_config = { + .super = {.name = "conv2d_1"}, + .qtype = NNOM_QTYPE_PER_TENSOR, + .weight = (nnom_tensor_t*)&tensor_conv2d_1_kernel_0, + .bias = (nnom_tensor_t*)&tensor_conv2d_1_bias_0, + .output_shift = (nnom_qformat_param_t *)&conv2d_1_output_shift, + .bias_shift = (nnom_qformat_param_t *)&conv2d_1_bias_shift, + .filter_size = 24, + .kernel_size = {3, 3}, + .stride_size = {1, 1}, + .padding_size = {0, 0}, + .dilation_size = {1, 1}, + .padding_type = PADDING_SAME +}; + +const nnom_pool_config_t max_pooling2d_1_config = { + .super = {.name = "max_pooling2d_1"}, + .padding_type = PADDING_SAME, + .output_shift = 0, + .kernel_size = {2, 2}, + .stride_size = {2, 2}, + .num_dim = 2 +}; +const int8_t tensor_conv2d_2_kernel_0_data[] = TENSOR_CONV2D_2_KERNEL_0; + +const nnom_shape_data_t tensor_conv2d_2_kernel_0_dim[] = {3, 3, 24, 48}; +const nnom_qformat_param_t tensor_conv2d_2_kernel_0_dec[] = TENSOR_CONV2D_2_KERNEL_0_DEC_BITS; +const nnom_qformat_param_t tensor_conv2d_2_kernel_0_offset[] = {0}; +const nnom_tensor_t tensor_conv2d_2_kernel_0 = { + .p_data = (void*)tensor_conv2d_2_kernel_0_data, + .dim = (nnom_shape_data_t*)tensor_conv2d_2_kernel_0_dim, + .q_dec = (nnom_qformat_param_t*)tensor_conv2d_2_kernel_0_dec, + .q_offset = (nnom_qformat_param_t*)tensor_conv2d_2_kernel_0_offset, + .qtype = NNOM_QTYPE_PER_TENSOR, + .num_dim = 4, + .bitwidth = 8 +}; +const int8_t tensor_conv2d_2_bias_0_data[] = TENSOR_CONV2D_2_BIAS_0; + +const nnom_shape_data_t tensor_conv2d_2_bias_0_dim[] = {48}; +const nnom_qformat_param_t tensor_conv2d_2_bias_0_dec[] = TENSOR_CONV2D_2_BIAS_0_DEC_BITS; +const nnom_qformat_param_t tensor_conv2d_2_bias_0_offset[] = {0}; +const nnom_tensor_t tensor_conv2d_2_bias_0 = { + .p_data = (void*)tensor_conv2d_2_bias_0_data, + .dim = (nnom_shape_data_t*)tensor_conv2d_2_bias_0_dim, + .q_dec = (nnom_qformat_param_t*)tensor_conv2d_2_bias_0_dec, + .q_offset = (nnom_qformat_param_t*)tensor_conv2d_2_bias_0_offset, + .qtype = NNOM_QTYPE_PER_TENSOR, + .num_dim = 1, + .bitwidth = 8 +}; + +const nnom_qformat_param_t conv2d_2_output_shift[] = CONV2D_2_OUTPUT_RSHIFT; +const nnom_qformat_param_t conv2d_2_bias_shift[] = CONV2D_2_BIAS_LSHIFT; +const nnom_conv2d_config_t conv2d_2_config = { + .super = {.name = "conv2d_2"}, + .qtype = NNOM_QTYPE_PER_TENSOR, + .weight = (nnom_tensor_t*)&tensor_conv2d_2_kernel_0, + .bias = (nnom_tensor_t*)&tensor_conv2d_2_bias_0, + .output_shift = (nnom_qformat_param_t *)&conv2d_2_output_shift, + .bias_shift = (nnom_qformat_param_t *)&conv2d_2_bias_shift, + .filter_size = 48, + .kernel_size = {3, 3}, + .stride_size = {1, 1}, + .padding_size = {0, 0}, + .dilation_size = {1, 1}, + .padding_type = PADDING_SAME +}; + +const nnom_pool_config_t max_pooling2d_2_config = { + .super = {.name = "max_pooling2d_2"}, + .padding_type = PADDING_SAME, + .output_shift = 0, + .kernel_size = {2, 2}, + .stride_size = {2, 2}, + .num_dim = 2 +}; + +const nnom_flatten_config_t flatten_config = { + .super = {.name = "flatten"} +}; +const int8_t tensor_dense_kernel_0_data[] = TENSOR_DENSE_KERNEL_0; + +const nnom_shape_data_t tensor_dense_kernel_0_dim[] = {768, 96}; +const nnom_qformat_param_t tensor_dense_kernel_0_dec[] = TENSOR_DENSE_KERNEL_0_DEC_BITS; +const nnom_qformat_param_t tensor_dense_kernel_0_offset[] = {0}; +const nnom_tensor_t tensor_dense_kernel_0 = { + .p_data = (void*)tensor_dense_kernel_0_data, + .dim = (nnom_shape_data_t*)tensor_dense_kernel_0_dim, + .q_dec = (nnom_qformat_param_t*)tensor_dense_kernel_0_dec, + .q_offset = (nnom_qformat_param_t*)tensor_dense_kernel_0_offset, + .qtype = NNOM_QTYPE_PER_TENSOR, + .num_dim = 2, + .bitwidth = 8 +}; +const int8_t tensor_dense_bias_0_data[] = TENSOR_DENSE_BIAS_0; + +const nnom_shape_data_t tensor_dense_bias_0_dim[] = {96}; +const nnom_qformat_param_t tensor_dense_bias_0_dec[] = TENSOR_DENSE_BIAS_0_DEC_BITS; +const nnom_qformat_param_t tensor_dense_bias_0_offset[] = {0}; +const nnom_tensor_t tensor_dense_bias_0 = { + .p_data = (void*)tensor_dense_bias_0_data, + .dim = (nnom_shape_data_t*)tensor_dense_bias_0_dim, + .q_dec = (nnom_qformat_param_t*)tensor_dense_bias_0_dec, + .q_offset = (nnom_qformat_param_t*)tensor_dense_bias_0_offset, + .qtype = NNOM_QTYPE_PER_TENSOR, + .num_dim = 1, + .bitwidth = 8 +}; + +const nnom_qformat_param_t dense_output_shift[] = DENSE_OUTPUT_RSHIFT; +const nnom_qformat_param_t dense_bias_shift[] = DENSE_BIAS_LSHIFT; +const nnom_dense_config_t dense_config = { + .super = {.name = "dense"}, + .qtype = NNOM_QTYPE_PER_TENSOR, + .weight = (nnom_tensor_t*)&tensor_dense_kernel_0, + .bias = (nnom_tensor_t*)&tensor_dense_bias_0, + .output_shift = (nnom_qformat_param_t *)&dense_output_shift, + .bias_shift = (nnom_qformat_param_t *)&dense_bias_shift +}; +const int8_t tensor_dense_1_kernel_0_data[] = TENSOR_DENSE_1_KERNEL_0; + +const nnom_shape_data_t tensor_dense_1_kernel_0_dim[] = {96, 10}; +const nnom_qformat_param_t tensor_dense_1_kernel_0_dec[] = TENSOR_DENSE_1_KERNEL_0_DEC_BITS; +const nnom_qformat_param_t tensor_dense_1_kernel_0_offset[] = {0}; +const nnom_tensor_t tensor_dense_1_kernel_0 = { + .p_data = (void*)tensor_dense_1_kernel_0_data, + .dim = (nnom_shape_data_t*)tensor_dense_1_kernel_0_dim, + .q_dec = (nnom_qformat_param_t*)tensor_dense_1_kernel_0_dec, + .q_offset = (nnom_qformat_param_t*)tensor_dense_1_kernel_0_offset, + .qtype = NNOM_QTYPE_PER_TENSOR, + .num_dim = 2, + .bitwidth = 8 +}; +const int8_t tensor_dense_1_bias_0_data[] = TENSOR_DENSE_1_BIAS_0; + +const nnom_shape_data_t tensor_dense_1_bias_0_dim[] = {10}; +const nnom_qformat_param_t tensor_dense_1_bias_0_dec[] = TENSOR_DENSE_1_BIAS_0_DEC_BITS; +const nnom_qformat_param_t tensor_dense_1_bias_0_offset[] = {0}; +const nnom_tensor_t tensor_dense_1_bias_0 = { + .p_data = (void*)tensor_dense_1_bias_0_data, + .dim = (nnom_shape_data_t*)tensor_dense_1_bias_0_dim, + .q_dec = (nnom_qformat_param_t*)tensor_dense_1_bias_0_dec, + .q_offset = (nnom_qformat_param_t*)tensor_dense_1_bias_0_offset, + .qtype = NNOM_QTYPE_PER_TENSOR, + .num_dim = 1, + .bitwidth = 8 +}; + +const nnom_qformat_param_t dense_1_output_shift[] = DENSE_1_OUTPUT_RSHIFT; +const nnom_qformat_param_t dense_1_bias_shift[] = DENSE_1_BIAS_LSHIFT; +const nnom_dense_config_t dense_1_config = { + .super = {.name = "dense_1"}, + .qtype = NNOM_QTYPE_PER_TENSOR, + .weight = (nnom_tensor_t*)&tensor_dense_1_kernel_0, + .bias = (nnom_tensor_t*)&tensor_dense_1_bias_0, + .output_shift = (nnom_qformat_param_t *)&dense_1_output_shift, + .bias_shift = (nnom_qformat_param_t *)&dense_1_bias_shift +}; + +const nnom_softmax_config_t softmax_config = { + .super = {.name = "softmax"} +}; +static int8_t nnom_output_data[10] = {0}; + +const nnom_shape_data_t tensor_output_dim[] = {10}; +const nnom_qformat_param_t tensor_output_dec[] = {SOFTMAX_OUTPUT_DEC}; +const nnom_qformat_param_t tensor_output_offset[] = {0}; +const nnom_tensor_t tensor_output = { + .p_data = (void*)nnom_output_data, + .dim = (nnom_shape_data_t*)tensor_output_dim, + .q_dec = (nnom_qformat_param_t*)tensor_output_dec, + .q_offset = (nnom_qformat_param_t*)tensor_output_offset, + .qtype = NNOM_QTYPE_PER_TENSOR, + .num_dim = 1, + .bitwidth = 8 +}; + +const nnom_io_config_t output_config = { + .super = {.name = "output"}, + .tensor = (nnom_tensor_t*)&tensor_output +}; +/* model version */ +#define NNOM_MODEL_VERSION (10000*0 + 100*4 + 0) + +/* nnom model */ +static nnom_model_t* nnom_model_create(void) +{ + static nnom_model_t model; + nnom_layer_t* layer[16]; + + check_model_version(NNOM_MODEL_VERSION); + new_model(&model); + + layer[0] = input_s(&input_1_config); + layer[1] = model.hook(conv2d_s(&conv2d_config), layer[0]); + layer[2] = model.active(act_relu(), layer[1]); + layer[3] = model.hook(maxpool_s(&max_pooling2d_config), layer[2]); + layer[4] = model.hook(conv2d_s(&conv2d_1_config), layer[3]); + layer[5] = model.active(act_relu(), layer[4]); + layer[6] = model.hook(maxpool_s(&max_pooling2d_1_config), layer[5]); + layer[7] = model.hook(conv2d_s(&conv2d_2_config), layer[6]); + layer[8] = model.active(act_relu(), layer[7]); + layer[9] = model.hook(maxpool_s(&max_pooling2d_2_config), layer[8]); + layer[10] = model.hook(flatten_s(&flatten_config), layer[9]); + layer[11] = model.hook(dense_s(&dense_config), layer[10]); + layer[12] = model.active(act_relu(), layer[11]); + layer[13] = model.hook(dense_s(&dense_1_config), layer[12]); + layer[14] = model.hook(softmax_s(&softmax_config), layer[13]); + layer[15] = model.hook(output_s(&output_config), layer[14]); + model_compile(&model, layer[0], layer[15]); + return &model; +} \ No newline at end of file diff --git a/examples/nnom_mnist/nnom_mnsit_example.c b/examples/nnom_mnist/nnom_mnsit_example.c new file mode 100644 index 000000000..407737722 --- /dev/null +++ b/examples/nnom_mnist/nnom_mnsit_example.c @@ -0,0 +1,120 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ************** + **************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "dcmi.h" +#include "dma.h" +#include "i2c.h" +#include "usart.h" +#include "spi.h" +#include "gpio.h" +#include "cmsis_os.h" +#include "nnom.h" +#include "image.h" +#include "weights.h" + +//task1 +#define TASK1_STK_SIZE 256 +void task1(void *pdata); +osThreadDef(task1, osPriorityNormal, 1, TASK1_STK_SIZE); + +//task2 +#define TASK2_STK_SIZE 256 +void task2(void *pdata); + +osThreadDef(task2, osPriorityNormal, 1, TASK2_STK_SIZE); + +#ifdef NNOM_USING_STATIC_MEMORY + uint8_t static_buf[1024*20]; +#endif + +nnom_model_t *model; +const char codeLib[] = "@B%8&WM#*oahkbdpqwmZO0QLCJUYXzcvunxrjft/\\|()1{}[]?-_+~<>i!lI;:,\"^`'. "; +void print_img_nnom(int8_t * buf) +{ + for(int y = 0; y < 28; y++) + { + for (int x = 0; x < 28; x++) + { + int index = 69 / 127.0 * (127 - buf[y*28+x]); + if(index > 69) index =69; + if(index < 0) index = 0; + printf("%c",codeLib[index]); + printf("%c",codeLib[index]); + } + printf("\n"); + } +} + +void mnist_nnom() +{ + uint32_t tick, time; + uint32_t predic_label; + float prob; + int32_t index = 0; + + printf("\nprediction start.. \n"); + tick = tos_systick_get(); + + // copy data and do prediction + memcpy(nnom_input_data, (int8_t*)&img[index][0], 784); + nnom_predict(model, &predic_label, &prob); + time = tos_systick_get() - tick; + + //print original image to console + print_img_nnom((int8_t*)&img[index][0]); + + printf("Time: %d tick\n", time); + printf("Truth label: %d\n", label[index]); + printf("Predicted label: %d\n", predic_label); + printf("Probability: %d%%\n", (int)(prob*100)); +} + + + +void task1(void *pdata) +{ + nnom_set_static_buf(static_buf, sizeof(static_buf)); + model = nnom_model_create(); + model_run(model); + mnist_nnom(); + while(1) + { + osDelay(1000); + } +} + +void task2(void *pdata) +{ + while(1) + { + osDelay(1000); + } +} + + +void application_entry(void *arg) +{ + printf("***nnom mnist example\r\n"); + osThreadCreate(osThread(task1), NULL); // Create task1 + osThreadCreate(osThread(task2), NULL); // Create task2 +} + diff --git a/examples/shell/shell_sample.c b/examples/shell/shell_sample.c index 919868bee..5eb53b17e 100644 --- a/examples/shell/shell_sample.c +++ b/examples/shell/shell_sample.c @@ -6,9 +6,9 @@ char cmd_buf[CMD_LEN_MAX]; hal_uart_t shell_uart; -void uart_output(const char *str) +void uart_output(const char ch) { - tos_hal_uart_write(&shell_uart, (const uint8_t *)str, strlen(str), 0xFF); + tos_hal_uart_write(&shell_uart, (const uint8_t *)&ch, 1, 0xFF); #if 0 /* if using c lib printf through uart, a simpler one is: */ @@ -19,34 +19,34 @@ void uart_output(const char *str) __STATIC__ int cmd_test00(int argc, char *argv[]) { int i = 0; - tos_shell_printf("test00:\n"); + tos_shell_printf("test00:\r\n"); for (i = 0; i < argc; ++i) { - tos_shell_printf("argv[%d]: %s\n", i, argv[i]); + tos_shell_printf("argv[%d]: %s\r\n", i, argv[i]); } return 0; } __STATIC__ int cmd_test01(int argc, char *argv[]) { - tos_shell_printf("test01:\n"); + tos_shell_printf("test01:\r\n"); return 0; } __STATIC__ int cmd_test10(int argc, char *argv[]) { int i = 0; - tos_shell_printf("test10:\n"); + tos_shell_printf("test10:\r\n"); for (i = 0; i < argc; ++i) { - tos_shell_printf("argv[%d]: %s\n", i, argv[i]); + tos_shell_printf("argv[%d]: %s\r\n", i, argv[i]); } return 0; } __STATIC__ int cmd_test11(int argc, char *argv[]) { - tos_shell_printf("test11:\n"); + tos_shell_printf("test11:\r\n"); return 0; } @@ -74,10 +74,16 @@ __STATIC__ shell_cmd_set_t custom_shell_cmd_set1 = { void application_entry(void *arg) { + int ret; + /* if test on ALIENTEK_STM32F429, switch HAL_UART_PORT_2 to HAL_UART_PORT_1 */ tos_hal_uart_init(&shell_uart, HAL_UART_PORT_2); - tos_shell_init(cmd_buf, sizeof(cmd_buf), uart_output, &custom_shell_cmd_set0); + ret = tos_shell_init(cmd_buf, sizeof(cmd_buf), uart_output, &custom_shell_cmd_set0); + if (ret < 0) { + printf("tos shell init fail, ret is %d\r\n", ret); + } + printf("tos shell init success\r\n"); tos_shell_cmd_set_regiser(&custom_shell_cmd_set1); diff --git a/examples/tflitemicro_person_detection/tflitemicro_person_detection.c b/examples/tflitemicro_person_detection/tflitemicro_person_detection.c index cc80ac752..ad3e9f223 100644 --- a/examples/tflitemicro_person_detection/tflitemicro_person_detection.c +++ b/examples/tflitemicro_person_detection/tflitemicro_person_detection.c @@ -54,6 +54,7 @@ void task1(void *arg) printf("*person_detect_task\r\n"); if(HAL_DCMI_Stop(&hdcmi))Error_Handler(); //stop DCMI input_convert(camera_buffer,model_buffer); + extern void person_detect(uint8_t*); person_detect(model_buffer); LCD_2IN4_Display(camera_buffer,OV2640_PIXEL_WIDTH,OV2640_PIXEL_HEIGHT); @@ -87,7 +88,7 @@ void application_entry(void *arg) { Error_Handler(); } - + extern void person_detect_init(void); person_detect_init(); printf("***Start person detection task! \r\n"); diff --git a/examples/tflitemicro_person_detection/tflu_person_detection/main_functions.cc b/examples/tflitemicro_person_detection/tflu_person_detection/main_functions.cc index 904eda48a..c756a5d2a 100644 --- a/examples/tflitemicro_person_detection/tflu_person_detection/main_functions.cc +++ b/examples/tflitemicro_person_detection/tflu_person_detection/main_functions.cc @@ -45,7 +45,7 @@ static uint8_t tensor_arena[kTensorArenaSize]; } // namespace // The name of this function is important for Arduino compatibility. -void person_detect_init() { +extern "C" void person_detect_init() { // Set up logging. Google style is to avoid globals or statics because of // lifetime uncertainty, but since this has a trivial destructor it's okay. // NOLINTNEXTLINE(runtime-global-variables) @@ -96,7 +96,7 @@ void person_detect_init() { } // The name of this function is important for Arduino compatibility. -int person_detect(uint8_t * hardware_input) { +extern "C" int person_detect(uint8_t * hardware_input) { // Get image from provider. if (kTfLiteOk != GetImage(error_reporter, kNumCols, kNumRows, kNumChannels, input->data.int8, hardware_input)) { diff --git a/examples/tflitemicro_speech_detection/tflitemicro_speech_detection.c b/examples/tflitemicro_speech_detection/tflitemicro_speech_detection.c new file mode 100644 index 000000000..0888cc5c3 --- /dev/null +++ b/examples/tflitemicro_speech_detection/tflitemicro_speech_detection.c @@ -0,0 +1,53 @@ +/** + * @file tflitemicro_person_detection.c + * @author Derekduke (dkeji627@gmail.com); QingChuanWS (bingshan45@163.com); yangqings (yangqingsheng12@outlook.com) + * @brief Person detection example based on TencentOS-Tiny and TFlite_Micro. + * @version 0.1 + * @date 2021-01-05 + * @copyright Copyright (c) 2021 + * + */ + +#include "cmsis_os.h" +#include "mcu_init.h" +#include "micro_speech.h" + +uint8_t tensor_flag = 0; + +#define TASK1_STK_SIZE 1024 +void task1(void *arg); +osThreadDef(task1, osPriorityNormal, 1, TASK1_STK_SIZE); + +#define TASK2_STK_SIZE 1024 +void task2(void *arg); +osThreadDef(task2, osPriorityNormal, 1, TASK2_STK_SIZE); + +void task1(void *arg) +{ + while (1) { + printf("***task1\r\n"); + osDelay(1000); + } +} + +void task2(void *arg) +{ + uint8_t* data = NULL;//you can input your own data + extern void speech_run(uint8_t*); + speech_run(data); + while (1) { + printf("***task2\r\n"); + osDelay(2000); + } +} + + +void application_entry(void *arg) +{ + extern void speech_init(void); + speech_init(); + printf("***Start speech detection task! \r\n"); + osThreadCreate(osThread(task1), NULL); // Create task1 + osThreadCreate(osThread(task2), NULL); // Create task2 +} + diff --git a/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/model.cc b/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/model.cc new file mode 100644 index 000000000..0490e7d9d --- /dev/null +++ b/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/model.cc @@ -0,0 +1,1596 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +// This is a standard TensorFlow Lite FlatBuffer model file that has been +// converted into a C data array, so it can be easily compiled into a binary +// for devices that don't have a file system. It was created using the command: +// xxd -i model.tflite > model.cc + +#include "model.h" + +// We need to keep the data array aligned on some architectures. +#ifdef __has_attribute +#define HAVE_ATTRIBUTE(x) __has_attribute(x) +#else +#define HAVE_ATTRIBUTE(x) 0 +#endif +#if HAVE_ATTRIBUTE(aligned) || (defined(__GNUC__) && !defined(__clang__)) +#define DATA_ALIGN_ATTRIBUTE __attribute__((aligned(4))) +#else +#define DATA_ALIGN_ATTRIBUTE +#endif + +const unsigned char g_model[] DATA_ALIGN_ATTRIBUTE = { + 0x20, 0x00, 0x00, 0x00, 0x54, 0x46, 0x4c, 0x33, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x12, 0x00, 0x1c, 0x00, 0x04, 0x00, 0x08, 0x00, 0x0c, 0x00, + 0x10, 0x00, 0x14, 0x00, 0x00, 0x00, 0x18, 0x00, 0x12, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x94, 0x48, 0x00, 0x00, 0x34, 0x42, 0x00, 0x00, + 0x1c, 0x42, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x08, 0x00, 0x0c, 0x00, + 0x04, 0x00, 0x08, 0x00, 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x0b, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x6d, 0x69, 0x6e, 0x5f, + 0x72, 0x75, 0x6e, 0x74, 0x69, 0x6d, 0x65, 0x5f, 0x76, 0x65, 0x72, 0x73, + 0x69, 0x6f, 0x6e, 0x00, 0x0c, 0x00, 0x00, 0x00, 0xd4, 0x41, 0x00, 0x00, + 0xb4, 0x41, 0x00, 0x00, 0x24, 0x03, 0x00, 0x00, 0xf4, 0x02, 0x00, 0x00, + 0xec, 0x02, 0x00, 0x00, 0xe4, 0x02, 0x00, 0x00, 0xc4, 0x02, 0x00, 0x00, + 0xbc, 0x02, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, + 0x1c, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x16, 0xbd, 0xff, 0xff, + 0x04, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x31, 0x2e, 0x35, 0x2e, + 0x30, 0x00, 0x00, 0x00, 0x94, 0xba, 0xff, 0xff, 0x98, 0xba, 0xff, 0xff, + 0x32, 0xbd, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, 0x80, 0x02, 0x00, 0x00, + 0xfa, 0xee, 0x28, 0xc4, 0xee, 0xfe, 0xcf, 0x0f, 0x1e, 0xf7, 0x1f, 0x06, + 0x0d, 0xed, 0xe9, 0x83, 0x5c, 0xc9, 0x18, 0xe3, 0xf9, 0x14, 0x28, 0x2a, + 0x09, 0xf2, 0x18, 0x34, 0x62, 0xea, 0xef, 0xd6, 0x36, 0xb7, 0x1e, 0xf7, + 0x3b, 0x22, 0x28, 0x39, 0xc2, 0x9d, 0xf1, 0x07, 0x5e, 0x0b, 0x1e, 0x2c, + 0x07, 0xdd, 0xfd, 0xc3, 0xd8, 0x4a, 0xf3, 0x28, 0xa7, 0x16, 0xd5, 0xf1, + 0xc3, 0x05, 0xfd, 0x27, 0xcc, 0xba, 0x1e, 0xcb, 0xd7, 0x3d, 0xd4, 0x29, + 0x00, 0xfd, 0x28, 0x44, 0xfb, 0xf2, 0xf3, 0xb6, 0x4f, 0xcf, 0x09, 0xf0, + 0xfa, 0x45, 0x41, 0x49, 0x05, 0xc5, 0x17, 0x5d, 0x64, 0x00, 0xf8, 0xee, + 0x48, 0x17, 0xf4, 0xe9, 0x2e, 0x4b, 0x2e, 0x3f, 0xdf, 0xee, 0xe4, 0x08, + 0x38, 0xf1, 0x16, 0x13, 0x2f, 0x2a, 0xed, 0xc2, 0xbf, 0x36, 0xf4, 0x02, + 0xcf, 0xaa, 0xd2, 0xfa, 0xac, 0x13, 0xf6, 0xe8, 0xb5, 0x68, 0x12, 0xb6, + 0xce, 0x0e, 0xdf, 0x58, 0xe4, 0x49, 0x14, 0x15, 0x03, 0xed, 0xfa, 0xd4, + 0x40, 0xa7, 0xf6, 0xca, 0xfb, 0x00, 0x4d, 0x5e, 0xe4, 0x55, 0x1d, 0x30, + 0x45, 0xe2, 0xfc, 0x01, 0x48, 0x81, 0xe9, 0xf1, 0x1e, 0xfc, 0x21, 0x32, + 0xed, 0x4b, 0xed, 0xfa, 0x2f, 0xd2, 0xfa, 0xfb, 0x4d, 0xa7, 0xed, 0xc7, + 0x92, 0xdf, 0xe6, 0xdb, 0xf8, 0x1f, 0xd9, 0xfa, 0x91, 0xf5, 0xe5, 0xc5, + 0x8c, 0x17, 0x0f, 0xb9, 0xd2, 0xc7, 0xfe, 0x68, 0xd3, 0x51, 0x2e, 0x49, + 0x1f, 0xbd, 0x01, 0xeb, 0x31, 0x17, 0xf0, 0xef, 0xff, 0xb8, 0x5d, 0x62, + 0x02, 0x0f, 0x1f, 0x78, 0x6a, 0xb0, 0xf9, 0xfe, 0x4f, 0xcc, 0xd3, 0xff, + 0x0a, 0x96, 0x1e, 0x2c, 0xed, 0xbc, 0xf4, 0x0b, 0x42, 0xc8, 0xf1, 0xea, + 0x6e, 0x58, 0xec, 0xc4, 0x99, 0xae, 0xdc, 0xd7, 0x12, 0x87, 0xd8, 0x06, + 0xa2, 0xc2, 0xe6, 0xa2, 0x81, 0x24, 0xe9, 0xac, 0xce, 0xb6, 0x15, 0x6b, + 0xba, 0x00, 0x19, 0x58, 0x29, 0xb6, 0xfe, 0x01, 0x25, 0x96, 0xd2, 0xec, + 0x0e, 0x9c, 0x60, 0x5f, 0xe9, 0xf4, 0xf5, 0x69, 0x6b, 0xb5, 0xe1, 0xf6, + 0x5e, 0xb7, 0xb1, 0xe5, 0x11, 0x9b, 0x18, 0x10, 0xe3, 0xe1, 0xe0, 0x0d, + 0x4f, 0xa5, 0xde, 0xe5, 0x6f, 0xe2, 0xfb, 0x99, 0x82, 0xa5, 0xc9, 0xb6, + 0x1f, 0x46, 0xf3, 0x04, 0xc6, 0xca, 0xd6, 0x97, 0x90, 0x1d, 0xc0, 0x95, + 0xf0, 0x19, 0x30, 0x77, 0xc2, 0x3c, 0xfa, 0x24, 0x02, 0x4d, 0x06, 0x07, + 0x15, 0x02, 0xb0, 0xe7, 0x27, 0x22, 0x67, 0x4d, 0xf1, 0xc2, 0xf4, 0x64, + 0x38, 0x40, 0xdf, 0xf6, 0x3a, 0x43, 0xb8, 0xe1, 0x0d, 0x15, 0x11, 0xfe, + 0xf5, 0xec, 0xf9, 0xe5, 0x22, 0x36, 0xe4, 0xfd, 0x6d, 0xbf, 0x0d, 0x8e, + 0xb7, 0x15, 0xbf, 0x9f, 0x16, 0xad, 0x0a, 0x02, 0x8e, 0x14, 0xda, 0x9b, + 0x8e, 0xc3, 0xa6, 0xca, 0xf5, 0x7f, 0x51, 0x56, 0xc1, 0xb3, 0xd9, 0x35, + 0xf8, 0x7f, 0x04, 0x0a, 0x03, 0x3f, 0xbe, 0xee, 0x19, 0x68, 0x78, 0x50, + 0xf9, 0xa7, 0xf7, 0x7f, 0x1d, 0x76, 0xdb, 0xe8, 0x33, 0xb9, 0xd7, 0xe7, + 0xe8, 0x69, 0x15, 0xf7, 0xf5, 0xb2, 0xfe, 0xe8, 0xf3, 0x5b, 0xe2, 0x06, + 0x6e, 0x09, 0x36, 0xb7, 0xcc, 0x38, 0xbf, 0x8a, 0x28, 0x14, 0x2e, 0x18, + 0xa7, 0x26, 0xcb, 0xb2, 0x95, 0x37, 0xac, 0xcd, 0xd7, 0x51, 0x67, 0x44, + 0xcd, 0x31, 0xde, 0x04, 0xe9, 0x6a, 0x00, 0x13, 0x0a, 0x0c, 0xdd, 0x16, + 0xe0, 0x24, 0x7e, 0x49, 0xf1, 0xb5, 0x04, 0x52, 0x01, 0x50, 0xdd, 0xf5, + 0x26, 0xc9, 0xf4, 0xf8, 0xd6, 0x31, 0x1b, 0xd0, 0xef, 0x03, 0x0a, 0xc0, + 0xd4, 0x4f, 0xe2, 0xfd, 0x72, 0xf4, 0x5a, 0xc9, 0xd7, 0x31, 0xc0, 0x8e, + 0x17, 0x5e, 0x57, 0x00, 0xb4, 0x3a, 0xc8, 0xd2, 0x92, 0x32, 0xcb, 0xd8, + 0xc3, 0xa6, 0x63, 0x26, 0xcf, 0xbc, 0xe8, 0x57, 0x9b, 0xe9, 0xf7, 0x1c, + 0xea, 0x12, 0xf1, 0xf7, 0xdb, 0xb9, 0x7f, 0x16, 0xf6, 0xe0, 0x08, 0x70, + 0xa2, 0xed, 0xcc, 0xf1, 0x1e, 0x10, 0x04, 0xf7, 0xa9, 0xb7, 0x34, 0xaa, + 0x0a, 0xdb, 0x2a, 0xa6, 0xb6, 0x10, 0xea, 0xf8, 0x5e, 0x06, 0x72, 0xdd, + 0xd0, 0xb9, 0xd6, 0xa0, 0x10, 0x9f, 0x5a, 0x17, 0xb1, 0xe7, 0xc0, 0x01, + 0x9d, 0x01, 0xe0, 0xe0, 0xaf, 0x9c, 0x46, 0xd8, 0xaf, 0xe8, 0xce, 0x02, + 0x8a, 0xbb, 0xe4, 0xf6, 0xf3, 0x36, 0x07, 0xca, 0xcb, 0x87, 0x6e, 0xcc, + 0xd6, 0x9e, 0x0a, 0x2a, 0x81, 0xd7, 0xcf, 0xc0, 0x04, 0xeb, 0x24, 0xcc, + 0xc9, 0x95, 0x33, 0x81, 0xf7, 0xad, 0x1c, 0x9c, 0xa4, 0xd6, 0xf9, 0xe6, + 0x3d, 0x84, 0x7f, 0xcc, 0xd4, 0xb0, 0xf4, 0xa2, 0xe9, 0x3c, 0x36, 0xee, + 0xd5, 0xcf, 0xcd, 0x2d, 0x28, 0xbd, 0xff, 0xff, 0xc2, 0xbf, 0xff, 0xff, + 0x04, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0x31, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x48, 0xbd, 0xff, 0xff, 0x4c, 0xbd, 0xff, 0xff, 0xe6, 0xbf, 0xff, 0xff, + 0x04, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x8a, 0xfe, 0xff, 0xff, + 0xa9, 0x00, 0x00, 0x00, 0xd0, 0xff, 0xff, 0xff, 0xd0, 0x00, 0x00, 0x00, + 0x52, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x4f, 0xfb, 0xff, 0xff, + 0x4a, 0xfd, 0xff, 0xff, 0x12, 0xc0, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, + 0x80, 0x3e, 0x00, 0x00, 0xff, 0xf9, 0xfd, 0x0a, 0x07, 0x08, 0x07, 0x03, + 0x07, 0xf2, 0xd1, 0x09, 0xf0, 0xe9, 0x28, 0x09, 0xdf, 0x05, 0xfa, 0xf0, + 0xe8, 0xe3, 0x13, 0x0e, 0x08, 0xef, 0xd3, 0xee, 0x0f, 0xe8, 0xeb, 0x14, + 0xf7, 0xed, 0xfd, 0x1f, 0xe8, 0xd5, 0xeb, 0xfc, 0x0e, 0xf4, 0xf7, 0x07, + 0x05, 0xea, 0xf6, 0x1f, 0xf8, 0xdb, 0xdc, 0x0b, 0x03, 0xdd, 0xd8, 0xf3, + 0x0f, 0x19, 0xe1, 0x09, 0xfc, 0xe4, 0x02, 0x04, 0xf1, 0x04, 0xeb, 0xf3, + 0x1e, 0x06, 0xfd, 0x11, 0xfc, 0xfa, 0xf6, 0x1f, 0x0f, 0x02, 0xf5, 0xf7, + 0xff, 0x24, 0xdf, 0xf7, 0xf8, 0xf3, 0xf6, 0xe9, 0xef, 0x03, 0xdd, 0xf2, + 0x28, 0xe1, 0xf2, 0x22, 0xf4, 0x09, 0xf7, 0xf9, 0xf0, 0xd4, 0xf9, 0xee, + 0xff, 0x14, 0xda, 0xf3, 0x11, 0xe2, 0xf6, 0x0c, 0xf2, 0xeb, 0xf8, 0xe8, + 0xe3, 0x08, 0x02, 0x17, 0xf4, 0x0b, 0x0c, 0x27, 0xe6, 0x02, 0x03, 0xf9, + 0x14, 0x18, 0xf6, 0xeb, 0x1f, 0x0c, 0xf1, 0xee, 0xfc, 0x08, 0xf0, 0xfe, + 0xfd, 0xee, 0x17, 0xfd, 0x1c, 0xef, 0xfd, 0xde, 0x04, 0x05, 0xf0, 0x31, + 0xfa, 0x0b, 0xdc, 0x0d, 0xed, 0xf5, 0xfa, 0xf4, 0x08, 0x0c, 0xd7, 0x1e, + 0x15, 0x03, 0xf5, 0x02, 0xf4, 0xfb, 0xed, 0x01, 0xfe, 0xd6, 0x1f, 0xfd, + 0xfd, 0x0e, 0xfa, 0x06, 0xf1, 0xf9, 0xe2, 0x16, 0xe9, 0xf1, 0x03, 0x0d, + 0x0d, 0xdf, 0xf9, 0x1a, 0x0e, 0xf6, 0xfc, 0x0a, 0x19, 0xe2, 0xe0, 0x09, + 0x15, 0xf0, 0xf1, 0x06, 0xf1, 0xe1, 0xef, 0x1a, 0x08, 0xe8, 0xfd, 0x12, + 0x14, 0x06, 0xf1, 0xfc, 0xea, 0xfb, 0xf7, 0xea, 0x1d, 0x09, 0xfa, 0xf6, + 0x08, 0xf2, 0xe7, 0xf8, 0xfc, 0x16, 0xf5, 0x0e, 0x08, 0xf9, 0x0a, 0x03, + 0x26, 0xd8, 0x02, 0xf5, 0xf6, 0xf6, 0xef, 0x1f, 0xe4, 0xe2, 0xfb, 0x02, + 0x1b, 0xe6, 0xde, 0x00, 0xf2, 0xed, 0xfb, 0x18, 0xe4, 0x16, 0x1a, 0x1d, + 0xf1, 0xf6, 0xea, 0x16, 0x05, 0xde, 0xfb, 0x18, 0xf5, 0xe4, 0xfe, 0xe2, + 0x1b, 0x1c, 0x0c, 0xe8, 0x02, 0xee, 0xfb, 0x07, 0x24, 0xf2, 0xe9, 0xfa, + 0x0d, 0x05, 0xf1, 0x03, 0xfe, 0xf6, 0x19, 0x06, 0xff, 0xf9, 0x04, 0xfb, + 0x15, 0xef, 0xf1, 0xf8, 0xe9, 0xe1, 0x10, 0x04, 0xfc, 0xe6, 0x1f, 0xed, + 0x0b, 0xef, 0x00, 0x1e, 0xe6, 0x16, 0xf3, 0x09, 0xfd, 0x08, 0x08, 0x06, + 0x06, 0x23, 0xdf, 0xfc, 0x08, 0xf4, 0xea, 0x0c, 0xf2, 0xe6, 0x18, 0xf5, + 0x02, 0xf9, 0x50, 0x09, 0x01, 0xda, 0x0b, 0x05, 0x12, 0x18, 0xef, 0x04, + 0x0e, 0xd9, 0xff, 0xdc, 0xf6, 0x16, 0xf9, 0xf4, 0xec, 0xff, 0xea, 0xe6, + 0xfa, 0x0a, 0xed, 0xef, 0x02, 0xf0, 0x25, 0x21, 0xf1, 0x26, 0xf5, 0xed, + 0x09, 0xea, 0xea, 0x24, 0xfa, 0x11, 0xfc, 0xdf, 0xf3, 0x0a, 0x28, 0x0c, + 0x19, 0xff, 0xf5, 0xd6, 0x0e, 0xe2, 0x2a, 0x06, 0xfa, 0x03, 0xf9, 0xe6, + 0xef, 0x23, 0xf9, 0xfa, 0xe6, 0xfe, 0xfc, 0x03, 0x06, 0x1a, 0xf9, 0x08, + 0xe0, 0xe5, 0xff, 0x05, 0x01, 0xe7, 0x12, 0x02, 0x1d, 0x05, 0x03, 0x05, + 0x0b, 0xee, 0xed, 0xfc, 0x0f, 0xf3, 0x02, 0xe0, 0x15, 0xdf, 0x02, 0xed, + 0x10, 0x26, 0xef, 0x0d, 0x06, 0xee, 0xef, 0xf6, 0xeb, 0x11, 0x09, 0xf4, + 0xf7, 0x06, 0x0f, 0x01, 0x2a, 0x0b, 0x01, 0xdd, 0xfc, 0xf4, 0xf1, 0x17, + 0x03, 0x04, 0x07, 0xfc, 0x22, 0xfc, 0xde, 0xfe, 0x0b, 0x03, 0xf3, 0xfb, + 0x0c, 0x25, 0x04, 0x19, 0x04, 0x03, 0x01, 0xfa, 0xfb, 0xf7, 0xf6, 0x0e, + 0x15, 0x0e, 0x09, 0xff, 0x06, 0xfa, 0xfb, 0x1e, 0xfb, 0x05, 0x22, 0xf9, + 0xfe, 0xf7, 0x1d, 0xed, 0xdf, 0x18, 0x09, 0xeb, 0xef, 0x04, 0x12, 0xea, + 0xdf, 0xfb, 0xda, 0xf6, 0xdf, 0x17, 0xef, 0xef, 0xe1, 0x1a, 0xd9, 0xe2, + 0xe2, 0xfc, 0x05, 0x11, 0xf6, 0xee, 0xe8, 0xf2, 0xe1, 0x08, 0x26, 0x04, + 0xed, 0x03, 0xe0, 0xfb, 0xee, 0x0c, 0xee, 0xf6, 0x04, 0x2d, 0xf2, 0xd3, + 0xf4, 0xe0, 0xf8, 0x0c, 0xfe, 0x11, 0x0b, 0xd7, 0xfd, 0x18, 0x07, 0x0d, + 0x07, 0x08, 0xf4, 0xc6, 0x0a, 0x0a, 0x1f, 0x0c, 0xf4, 0x1d, 0x02, 0x0b, + 0x09, 0x0e, 0x21, 0xff, 0x17, 0x0b, 0x0d, 0xf2, 0xed, 0xd7, 0x0a, 0xf8, + 0x03, 0x06, 0xfa, 0xe5, 0xfd, 0x03, 0x14, 0x0f, 0xe9, 0x1a, 0xf4, 0xda, + 0x01, 0xe6, 0x09, 0x06, 0x11, 0x0d, 0xfd, 0xeb, 0x16, 0x23, 0xfa, 0x00, + 0x0b, 0x17, 0xf7, 0xda, 0xd7, 0x1b, 0xfa, 0x01, 0x03, 0x05, 0xfe, 0xd6, + 0x02, 0xee, 0xee, 0x02, 0xf3, 0x06, 0xed, 0x03, 0xec, 0x01, 0xf2, 0x0f, + 0x05, 0x17, 0x0b, 0xfb, 0x0f, 0x05, 0x03, 0x13, 0xff, 0x06, 0x02, 0xf5, + 0xf4, 0x18, 0x2b, 0xf0, 0x00, 0x17, 0xfc, 0xfd, 0x05, 0x0b, 0x0e, 0x14, + 0xe1, 0x24, 0x08, 0x24, 0xe6, 0xeb, 0x21, 0x12, 0xfb, 0x12, 0xe7, 0xf4, + 0xe8, 0x0e, 0x18, 0xee, 0xf5, 0xf3, 0xd9, 0xf3, 0xdb, 0xec, 0x0c, 0x1e, + 0xcf, 0x14, 0xdb, 0xe3, 0xdc, 0x02, 0x0c, 0xfb, 0xdb, 0x1b, 0xd0, 0xfe, + 0xf9, 0xfe, 0x2a, 0xf5, 0x00, 0x0b, 0xcd, 0xe0, 0xe2, 0x0e, 0x04, 0xf8, + 0xda, 0x1c, 0xe5, 0x0f, 0xe8, 0xf4, 0xf7, 0x15, 0x06, 0xf8, 0x02, 0xf7, + 0x0f, 0xfb, 0x17, 0xf9, 0xda, 0x01, 0xda, 0xd1, 0xf6, 0x02, 0xfd, 0x16, + 0xf1, 0xe4, 0xfa, 0x07, 0xee, 0x0a, 0xf3, 0xfd, 0xf2, 0x23, 0xf0, 0xe1, + 0x0a, 0x1a, 0x12, 0x1f, 0xef, 0x27, 0x09, 0xf1, 0x0c, 0x13, 0x23, 0xfd, + 0xf5, 0x03, 0xfe, 0x09, 0xfd, 0x16, 0xf8, 0x07, 0x08, 0x25, 0x08, 0xf8, + 0xf6, 0x0a, 0xf1, 0xf5, 0x07, 0x09, 0x05, 0xcc, 0xf8, 0x08, 0x13, 0xf9, + 0x1d, 0x11, 0x0f, 0xdc, 0xee, 0xf3, 0x27, 0xf9, 0xf9, 0x22, 0xfa, 0x0d, + 0xe2, 0x13, 0xfb, 0x11, 0x03, 0x1e, 0xff, 0xfb, 0xed, 0xf1, 0x0e, 0x0b, + 0x0f, 0x00, 0x06, 0xe0, 0x15, 0xf3, 0x13, 0xfc, 0x18, 0xf9, 0xff, 0x09, + 0xfa, 0x1f, 0x12, 0xe5, 0xe2, 0x06, 0xf9, 0xf4, 0x07, 0x15, 0x0b, 0x04, + 0xdb, 0x0d, 0xeb, 0xf3, 0xe6, 0x06, 0xe5, 0xee, 0xd8, 0x22, 0xd8, 0x10, + 0xea, 0xf9, 0x1c, 0xf7, 0xd3, 0x11, 0xc3, 0xf8, 0xde, 0x05, 0x00, 0xe6, + 0x07, 0xfd, 0xd3, 0x03, 0xea, 0xe0, 0x13, 0x14, 0xcf, 0xeb, 0xcd, 0xd3, + 0xde, 0xf5, 0xf0, 0x0c, 0x0c, 0xfa, 0xeb, 0xd3, 0xfb, 0xfd, 0x08, 0xf9, + 0xf4, 0x10, 0xfa, 0xd3, 0xf4, 0x11, 0x11, 0xf8, 0xef, 0xf8, 0xf8, 0xf1, + 0xfc, 0xe1, 0xf7, 0x12, 0x04, 0xf4, 0xfb, 0xed, 0xef, 0x0c, 0xfd, 0x1c, + 0xfe, 0x0e, 0xfd, 0xe2, 0xfe, 0x0a, 0x02, 0xfe, 0xe6, 0x1f, 0xef, 0xe5, + 0xe6, 0xf8, 0x16, 0x27, 0xe8, 0x20, 0x05, 0xe3, 0xf1, 0xef, 0xee, 0xed, + 0x0d, 0x11, 0x16, 0xfb, 0xf3, 0xff, 0x14, 0x01, 0xff, 0x15, 0x10, 0x02, + 0xe5, 0x28, 0x29, 0x13, 0x13, 0x16, 0xe6, 0x00, 0xd2, 0x26, 0xfd, 0x03, + 0x04, 0x05, 0x07, 0x06, 0xf1, 0x0e, 0x05, 0x0d, 0xe2, 0x0f, 0x02, 0xe1, + 0x07, 0xf7, 0x1c, 0xfa, 0x14, 0x30, 0xf7, 0xee, 0x00, 0xfa, 0x3d, 0x06, + 0x1c, 0x04, 0x06, 0x07, 0x05, 0x1a, 0x10, 0xf6, 0xee, 0x0a, 0xeb, 0x04, + 0xeb, 0xdf, 0x1d, 0x09, 0xd5, 0xe8, 0xd6, 0xf4, 0xf0, 0x0f, 0x1d, 0xea, + 0xf2, 0xf8, 0xa6, 0x0b, 0xdc, 0x09, 0x08, 0x24, 0xee, 0x24, 0xaa, 0xe4, + 0xcb, 0x15, 0xef, 0xe7, 0xe9, 0x0c, 0xcf, 0x06, 0xe3, 0x12, 0x11, 0x00, + 0x07, 0x14, 0xd7, 0xde, 0xf6, 0x0f, 0x0b, 0x04, 0xfb, 0x0d, 0xf8, 0x0d, + 0xf6, 0x1b, 0xf1, 0x21, 0xdd, 0xfc, 0xf4, 0xe9, 0xf8, 0xe8, 0xf7, 0x06, + 0x03, 0x1e, 0xce, 0xe1, 0xea, 0xf6, 0x05, 0xf9, 0x16, 0x15, 0x04, 0xe0, + 0x14, 0xf7, 0x1e, 0x1c, 0x0a, 0x27, 0xef, 0xf3, 0x0f, 0xf3, 0xee, 0x04, + 0xf8, 0xf1, 0x07, 0xe3, 0x05, 0x0b, 0x00, 0x1c, 0x15, 0x27, 0x07, 0xf7, + 0xfa, 0x0b, 0xfa, 0xfa, 0x17, 0x13, 0xe1, 0xf5, 0xfb, 0x0c, 0x21, 0x2f, + 0xd7, 0xfb, 0xf5, 0xfd, 0xd3, 0xf4, 0x07, 0x0e, 0xfd, 0x0b, 0xfc, 0xfa, + 0xf5, 0x0e, 0x02, 0xfa, 0xfa, 0x19, 0xfd, 0xfa, 0xfc, 0x13, 0x24, 0x0c, + 0xe4, 0x31, 0xf8, 0x12, 0xf4, 0x04, 0x18, 0x29, 0x27, 0x19, 0xfc, 0x08, + 0x11, 0xe3, 0x07, 0xfe, 0x26, 0x40, 0x05, 0x02, 0x04, 0x02, 0x0f, 0xee, + 0xf4, 0x27, 0xea, 0xf4, 0xf5, 0x11, 0x26, 0x0b, 0xe7, 0x05, 0xd2, 0xf6, + 0xea, 0xfa, 0x0b, 0xf9, 0xfa, 0x16, 0xba, 0x00, 0xfb, 0x0d, 0x0b, 0xf9, + 0xe6, 0xf6, 0xc5, 0xf8, 0xf6, 0x01, 0x0f, 0xed, 0xed, 0x13, 0xcd, 0x0d, + 0xda, 0x06, 0x17, 0xee, 0x07, 0x1d, 0xb8, 0xfa, 0xe2, 0xea, 0xf2, 0xee, + 0x04, 0x00, 0xdc, 0xd0, 0xfb, 0xf5, 0xec, 0xfe, 0xf1, 0x0d, 0xf0, 0xdb, + 0xf9, 0x0d, 0x03, 0x03, 0x0e, 0x0a, 0xda, 0xd6, 0x01, 0xf2, 0x06, 0x14, + 0x1c, 0x1f, 0xe8, 0xe8, 0x0e, 0xfd, 0x0c, 0xf5, 0xf3, 0x3d, 0xf3, 0x05, + 0x10, 0xfa, 0x1b, 0x18, 0x08, 0x36, 0x09, 0xf1, 0xeb, 0xf9, 0x22, 0x01, + 0xf3, 0xf7, 0xff, 0xf0, 0x0c, 0xe9, 0x01, 0x29, 0x21, 0x15, 0x03, 0xee, + 0xe9, 0x1a, 0xf7, 0x15, 0x06, 0x25, 0xfa, 0xf0, 0xe4, 0xf1, 0x1f, 0x01, + 0xdc, 0x2d, 0xce, 0xe9, 0xea, 0x0b, 0x06, 0x2c, 0x0a, 0x30, 0xe7, 0x09, + 0xf4, 0xf0, 0x10, 0x29, 0xf9, 0x3d, 0xe7, 0xdc, 0xe4, 0xf7, 0x3b, 0x27, + 0x23, 0x3a, 0x0a, 0x06, 0x0e, 0xfd, 0x2c, 0x07, 0x2b, 0x1c, 0xfa, 0x00, + 0xf9, 0x11, 0xea, 0x14, 0xeb, 0xfc, 0x18, 0x03, 0xf1, 0x16, 0x12, 0x04, + 0xcf, 0x12, 0xdd, 0xe4, 0x0e, 0xf0, 0x09, 0xe8, 0xf3, 0xfb, 0xa8, 0xf9, + 0xee, 0xfb, 0x1e, 0x1d, 0xfd, 0x05, 0xab, 0xe5, 0xff, 0x01, 0xfe, 0x04, + 0xf9, 0x02, 0xb9, 0xdc, 0xdf, 0x05, 0xf1, 0xef, 0xf1, 0x1e, 0xc7, 0xee, + 0xf7, 0x1e, 0x00, 0x00, 0xf8, 0x10, 0xec, 0xe8, 0x04, 0x0f, 0xf6, 0xff, + 0x04, 0x09, 0xe0, 0x0a, 0x0e, 0xe4, 0xf0, 0xf1, 0x16, 0x2b, 0xd3, 0xe1, + 0x0a, 0xef, 0xf9, 0xfe, 0x0b, 0x22, 0xf5, 0x01, 0x0a, 0xf8, 0x02, 0x00, + 0x17, 0x19, 0xf3, 0x05, 0x21, 0xfa, 0xee, 0xee, 0x12, 0xf2, 0xfa, 0xf5, + 0x05, 0x12, 0xee, 0xe4, 0x28, 0xfa, 0xf1, 0x03, 0x15, 0x16, 0x18, 0xfd, + 0x0f, 0x21, 0x04, 0xf4, 0xe5, 0x0c, 0x06, 0x13, 0xde, 0x36, 0xe8, 0xfb, + 0xe7, 0xfd, 0xf6, 0x12, 0x0e, 0x1d, 0xea, 0xf8, 0xd4, 0xe8, 0x19, 0x07, + 0xe5, 0x1c, 0xf7, 0x0c, 0xef, 0x05, 0x0f, 0x09, 0xdd, 0x1a, 0xea, 0xd7, + 0xf9, 0xf9, 0x12, 0x17, 0x2e, 0x10, 0x08, 0xfe, 0x14, 0xf5, 0x1d, 0xfa, + 0x06, 0x33, 0xed, 0xfe, 0xf7, 0x11, 0xf0, 0x15, 0xe2, 0x24, 0xf6, 0x0a, + 0xe2, 0xfc, 0x23, 0x12, 0xdd, 0x11, 0xfd, 0xe5, 0x08, 0xff, 0x15, 0xf6, + 0xf1, 0x1b, 0xae, 0xfe, 0xe6, 0x15, 0x2c, 0x2d, 0x15, 0x15, 0xc5, 0xf8, + 0xea, 0xe7, 0x07, 0x04, 0xfe, 0x28, 0xa1, 0xf2, 0xe1, 0xf9, 0xf8, 0xff, + 0xf4, 0x22, 0xb4, 0xdb, 0x03, 0x20, 0xe6, 0xf3, 0x0e, 0x19, 0xe3, 0x0a, + 0xfa, 0xee, 0xf3, 0xe5, 0xd8, 0xf9, 0xf1, 0xde, 0x06, 0x05, 0xf2, 0xf5, + 0xe7, 0x16, 0xd8, 0xfe, 0x07, 0xea, 0xee, 0x0e, 0xfa, 0xff, 0xdb, 0xe7, + 0x03, 0xed, 0x01, 0xfd, 0x09, 0x1a, 0xfa, 0xe6, 0x05, 0x10, 0xe9, 0x01, + 0x1f, 0x13, 0xf7, 0xf6, 0xfb, 0x13, 0xff, 0xdb, 0xed, 0xfe, 0x0a, 0x10, + 0x09, 0x29, 0xf5, 0x04, 0xf5, 0x26, 0x0d, 0x0c, 0xf9, 0x16, 0xfa, 0x02, + 0xf4, 0x2e, 0xde, 0xf5, 0xe1, 0x1d, 0xfb, 0x02, 0x0b, 0x23, 0x07, 0xea, + 0xd9, 0x0a, 0xf3, 0x0a, 0x0f, 0x1e, 0xe7, 0xf1, 0xd7, 0x0b, 0xf6, 0xff, + 0x0d, 0x24, 0xcc, 0x0a, 0xee, 0xda, 0x14, 0x12, 0x11, 0x29, 0xf4, 0x1a, + 0xef, 0x0b, 0xfa, 0xec, 0x0c, 0x1b, 0xf4, 0xff, 0xf5, 0xef, 0x0f, 0x10, + 0xd4, 0x04, 0xf9, 0xf8, 0xec, 0xf9, 0x21, 0x05, 0xd3, 0x27, 0xf3, 0x17, + 0xff, 0xf6, 0x15, 0xf9, 0xed, 0x0a, 0xac, 0x02, 0xfd, 0xfb, 0x04, 0x29, + 0x06, 0x03, 0xb8, 0xe6, 0xd5, 0x17, 0x09, 0x1b, 0xf6, 0x1b, 0xab, 0xdc, + 0xdf, 0xfd, 0x06, 0x09, 0x09, 0x37, 0xbb, 0xed, 0x19, 0xd7, 0xe2, 0xdd, + 0x05, 0x01, 0xec, 0xfb, 0xe4, 0x0e, 0xeb, 0xf0, 0x03, 0x17, 0x04, 0xeb, + 0x09, 0xee, 0xeb, 0xe7, 0x0c, 0x16, 0xcb, 0x0e, 0x17, 0xd8, 0xe1, 0xf8, + 0x2b, 0x19, 0xde, 0xeb, 0x10, 0xf2, 0xff, 0xf8, 0xee, 0x0e, 0xe7, 0xf0, + 0x15, 0x08, 0xf8, 0xdf, 0x06, 0x0d, 0xf9, 0x14, 0xfa, 0x0b, 0x04, 0xfd, + 0x15, 0x23, 0x20, 0xff, 0xfd, 0x1d, 0x0c, 0xf1, 0xfe, 0x15, 0x0a, 0x02, + 0xed, 0xfe, 0xfb, 0x04, 0xfb, 0x1e, 0xdd, 0x05, 0xe0, 0x16, 0xf9, 0xf6, + 0xfd, 0x32, 0xdc, 0xf2, 0xd3, 0x08, 0xf4, 0xec, 0x17, 0x25, 0xe2, 0xf0, + 0xee, 0xf1, 0x0d, 0xfe, 0x13, 0x2d, 0x01, 0x11, 0xd4, 0xe4, 0x07, 0xfb, + 0x32, 0x11, 0x14, 0x07, 0xd7, 0x02, 0x10, 0xeb, 0x2b, 0x1d, 0x01, 0xfc, + 0xf3, 0xf0, 0x13, 0x1a, 0xdb, 0x20, 0x00, 0xf0, 0xf0, 0x05, 0x16, 0x03, + 0xd4, 0xe3, 0xc2, 0xf0, 0x06, 0x02, 0x1e, 0x0a, 0xec, 0x1f, 0xab, 0xea, + 0xfa, 0xe3, 0x20, 0x22, 0x03, 0x1b, 0xb3, 0x0e, 0xe3, 0xf3, 0x1d, 0x27, + 0xe3, 0x10, 0xa7, 0xda, 0xf3, 0x00, 0x0a, 0x0a, 0x04, 0xfb, 0xb2, 0x0f, + 0x0c, 0xf5, 0x07, 0xff, 0x13, 0x1e, 0xdb, 0xf6, 0xf9, 0xef, 0xe8, 0xe7, + 0xfb, 0x18, 0xeb, 0xec, 0x09, 0xda, 0xf1, 0xf0, 0x0b, 0x04, 0xe1, 0xfa, + 0x1c, 0x25, 0xee, 0x01, 0x0b, 0x29, 0xd7, 0x0c, 0x04, 0x0b, 0xef, 0xfd, + 0x1c, 0xfc, 0xf1, 0xfb, 0x0b, 0x0f, 0xdf, 0xed, 0x17, 0x38, 0x0c, 0xd7, + 0xff, 0xfd, 0x01, 0xfc, 0xfb, 0xfb, 0x18, 0x1a, 0x18, 0xe3, 0xf9, 0xf4, + 0xfa, 0x20, 0x06, 0x09, 0x11, 0x08, 0x1d, 0xf8, 0xfa, 0x1d, 0xf5, 0x1c, + 0xf5, 0xfe, 0x03, 0x07, 0xe4, 0x33, 0xc8, 0x0c, 0xe1, 0x13, 0xff, 0xe5, + 0x10, 0x2c, 0xd3, 0xf0, 0xed, 0x04, 0x07, 0x01, 0xf1, 0x16, 0xe0, 0x13, + 0xfa, 0x11, 0x07, 0xfa, 0x19, 0x16, 0x01, 0x00, 0x07, 0x26, 0x00, 0xec, + 0x1d, 0x23, 0x05, 0xf4, 0x07, 0x17, 0x2c, 0x1d, 0xee, 0xf0, 0x0c, 0x09, + 0xe3, 0x1a, 0x24, 0x0b, 0xf3, 0x1e, 0xce, 0xfe, 0xfe, 0x12, 0x21, 0x1a, + 0xf6, 0x23, 0xc3, 0x03, 0xf4, 0x10, 0x1a, 0x2a, 0xf4, 0x08, 0xbf, 0xff, + 0x04, 0xf4, 0x0b, 0x1d, 0x1a, 0xf8, 0xcc, 0x00, 0xf7, 0x13, 0xf4, 0xfd, + 0xf4, 0x19, 0xbd, 0xef, 0x0c, 0x0d, 0x02, 0xfc, 0x12, 0x13, 0xe9, 0xe7, + 0xf5, 0xfa, 0xfa, 0xf6, 0x1a, 0x2e, 0xce, 0xd4, 0x01, 0x12, 0xfd, 0xfc, + 0x26, 0x10, 0xcc, 0xe7, 0xee, 0x13, 0xee, 0xff, 0xef, 0xea, 0x00, 0x0e, + 0x1a, 0x17, 0x04, 0x0c, 0x04, 0x0c, 0xe6, 0xf3, 0xf6, 0xdb, 0xdd, 0x04, + 0xf4, 0x22, 0x11, 0x16, 0xf3, 0x07, 0xec, 0xf8, 0xf2, 0x07, 0x03, 0x02, + 0xf5, 0x0a, 0xf6, 0x02, 0x1d, 0x1b, 0x11, 0x06, 0xf8, 0x06, 0x02, 0xea, + 0xf3, 0x1d, 0xce, 0x00, 0xed, 0xf9, 0xef, 0xf6, 0xec, 0x22, 0xc7, 0xf0, + 0xed, 0xdb, 0xe0, 0x02, 0x11, 0x07, 0xe8, 0xf0, 0xd1, 0xed, 0xff, 0xfd, + 0x0c, 0x2e, 0xd4, 0xed, 0xec, 0x0e, 0xf1, 0x07, 0x01, 0x0e, 0x0e, 0xfe, + 0xda, 0x0b, 0x0a, 0x0a, 0x1f, 0x2e, 0x13, 0x07, 0x00, 0x07, 0x14, 0x21, + 0xe9, 0xfc, 0xf0, 0x1e, 0xd7, 0xea, 0x34, 0x07, 0xc6, 0x0c, 0xd4, 0xec, + 0xfd, 0x06, 0x24, 0x0a, 0xf3, 0x15, 0xaf, 0xff, 0xe9, 0xf1, 0x0d, 0x3e, + 0xe9, 0x18, 0xba, 0x13, 0xed, 0xd7, 0x0b, 0x31, 0x05, 0x0e, 0xaf, 0x13, + 0xd6, 0x0e, 0x10, 0x02, 0x02, 0x14, 0xcb, 0xd5, 0xf9, 0x0c, 0xf9, 0x0e, + 0x1f, 0x24, 0xd5, 0xeb, 0xff, 0xf1, 0xf5, 0x0c, 0x08, 0x07, 0xf4, 0xd7, + 0x06, 0x10, 0xe8, 0xef, 0xfc, 0x2f, 0xee, 0xf1, 0x18, 0xf8, 0xf4, 0x02, + 0x11, 0x21, 0xd3, 0x12, 0x14, 0xe4, 0xf4, 0x02, 0x05, 0x24, 0xca, 0xf2, + 0xf3, 0xeb, 0xe7, 0xf8, 0x16, 0x1a, 0xeb, 0x0d, 0x05, 0x16, 0xf1, 0xec, + 0x11, 0x1c, 0x09, 0x1e, 0xe0, 0xe6, 0xfa, 0x0e, 0x0d, 0x2a, 0xea, 0x2e, + 0xed, 0xf9, 0xf7, 0x16, 0x09, 0x05, 0xdd, 0xd6, 0x02, 0xeb, 0xf5, 0xf3, + 0xe4, 0x3b, 0xed, 0x04, 0xe0, 0x0e, 0xfd, 0x09, 0xfd, 0x35, 0xdc, 0x18, + 0xf3, 0x04, 0xfa, 0x05, 0x15, 0x34, 0xe5, 0xe1, 0xe4, 0xf4, 0xe0, 0xf9, + 0x08, 0x32, 0x04, 0x08, 0xf4, 0x0f, 0xff, 0x08, 0x09, 0x2f, 0x06, 0x02, + 0xfd, 0x05, 0x0c, 0x24, 0xe3, 0x1e, 0xf5, 0x0c, 0xdd, 0xf8, 0x18, 0x20, + 0xd8, 0x14, 0xef, 0xf4, 0x17, 0x08, 0x25, 0x14, 0x04, 0x06, 0xb0, 0xf5, + 0xf5, 0x09, 0x0f, 0x3e, 0xff, 0x28, 0xb3, 0xf5, 0x19, 0xd8, 0x14, 0x21, + 0xd9, 0xf7, 0xb7, 0xe5, 0xfe, 0xe7, 0x07, 0x1e, 0x04, 0x15, 0xc5, 0xf9, + 0x14, 0x20, 0xeb, 0x01, 0x01, 0x18, 0xce, 0x00, 0xe6, 0xe2, 0xf7, 0xfb, + 0xf3, 0x0d, 0xd3, 0xf3, 0x04, 0xf8, 0xf0, 0x03, 0xf1, 0x25, 0xb5, 0xef, + 0x05, 0xe0, 0x01, 0xf6, 0x04, 0x16, 0xd1, 0x01, 0x0a, 0x21, 0x01, 0x05, + 0x0e, 0x01, 0xf0, 0x0a, 0xf3, 0x00, 0x03, 0xf8, 0xfa, 0x03, 0x0b, 0xde, + 0xfe, 0xff, 0xfb, 0xea, 0x09, 0x02, 0xf5, 0xe8, 0xe7, 0x08, 0x00, 0xf5, + 0xf8, 0x0f, 0x13, 0xfa, 0xeb, 0xe8, 0xfb, 0x1f, 0x08, 0x16, 0xe6, 0xfa, + 0xe1, 0x00, 0x03, 0xdd, 0xf1, 0x26, 0xe5, 0x1d, 0xd9, 0xff, 0xf2, 0xf8, + 0xff, 0x33, 0xea, 0xe5, 0x03, 0x0c, 0x07, 0xf9, 0xf8, 0x0f, 0xe1, 0x1e, + 0xdd, 0x0f, 0x00, 0xf1, 0x06, 0x21, 0x09, 0x05, 0xf3, 0xec, 0xe6, 0x04, + 0x07, 0x32, 0xf1, 0xf9, 0xf2, 0x01, 0x18, 0x1f, 0xd2, 0xe2, 0x0a, 0xf4, + 0xca, 0xfc, 0x28, 0x16, 0xc2, 0x10, 0xf2, 0xfc, 0x08, 0xe9, 0x2a, 0x0f, + 0xfa, 0xf5, 0xa9, 0x07, 0xec, 0xe9, 0x19, 0x43, 0x0b, 0x1c, 0xa6, 0xe9, + 0xf4, 0x16, 0x0d, 0x2b, 0xfc, 0x11, 0x9a, 0xe1, 0xf1, 0x1c, 0xf5, 0x0f, + 0xe4, 0x18, 0xc0, 0xd9, 0x14, 0x26, 0xe6, 0xf8, 0x0a, 0x17, 0xec, 0xfb, + 0xe1, 0x22, 0xdf, 0xf2, 0xfe, 0x1e, 0xd4, 0xeb, 0xd7, 0x0e, 0x08, 0xf6, + 0xef, 0xfc, 0xe6, 0xd4, 0xf7, 0x0b, 0xfb, 0xf5, 0x01, 0x25, 0xd7, 0xfb, + 0x0d, 0xfe, 0xff, 0xf3, 0x1d, 0x32, 0xfe, 0xee, 0x12, 0xf2, 0x0c, 0xec, + 0x02, 0x10, 0xef, 0x01, 0xf2, 0x0b, 0xf3, 0xf7, 0xfa, 0x25, 0xfb, 0x0d, + 0x11, 0x15, 0x04, 0xfc, 0x0c, 0x21, 0x12, 0x29, 0x00, 0xfa, 0xf6, 0xf5, + 0x06, 0x22, 0xea, 0xe2, 0xee, 0x00, 0xfd, 0xf0, 0x0b, 0x1d, 0xd3, 0xe4, + 0xe4, 0x0a, 0xfc, 0xe8, 0xea, 0x2c, 0xed, 0xed, 0xef, 0xe8, 0xf2, 0x05, + 0xfd, 0x15, 0xd8, 0xda, 0xca, 0xee, 0xfa, 0x00, 0xfe, 0x0e, 0xf2, 0xf0, + 0x0e, 0xf5, 0x04, 0x03, 0x1d, 0x2b, 0xee, 0x05, 0x0f, 0x10, 0x13, 0x35, + 0xe2, 0x04, 0x10, 0xdf, 0xcf, 0xeb, 0x40, 0x26, 0xe4, 0x03, 0xf3, 0xf9, + 0xf5, 0x14, 0x24, 0x2a, 0xdf, 0xfe, 0xab, 0xe5, 0xfe, 0x1c, 0x27, 0x35, + 0xdb, 0xff, 0xac, 0x01, 0xf6, 0xfc, 0x19, 0x1a, 0x11, 0x1f, 0xa8, 0xf5, + 0x02, 0x0f, 0x1a, 0x1f, 0xf7, 0xf2, 0xa2, 0x00, 0x15, 0x22, 0xe4, 0x13, + 0x00, 0x09, 0xd9, 0xd5, 0x02, 0x19, 0xfd, 0xf8, 0xe7, 0xff, 0xfb, 0xe0, + 0xef, 0xf7, 0xee, 0xf3, 0xf3, 0x19, 0xb0, 0xdf, 0x00, 0x0f, 0x08, 0xf3, + 0x15, 0x17, 0xec, 0x0f, 0x11, 0x14, 0x02, 0x08, 0x10, 0x17, 0xe6, 0x08, + 0xf7, 0x00, 0xed, 0xf7, 0x29, 0x07, 0x10, 0x05, 0x05, 0xe7, 0xed, 0xf4, + 0xf9, 0x15, 0xf9, 0xf0, 0x08, 0x00, 0x03, 0x09, 0x21, 0x28, 0xf6, 0x0e, + 0xfb, 0xf3, 0x03, 0xf7, 0x0f, 0x0c, 0xf0, 0xf5, 0xe3, 0xd8, 0xf8, 0xf2, + 0x09, 0x1c, 0xe7, 0xfb, 0xe4, 0xf6, 0xfa, 0xf8, 0xf1, 0x42, 0xf6, 0xda, + 0xdd, 0xd7, 0xfa, 0xff, 0x2f, 0x2c, 0xda, 0x0a, 0xde, 0xec, 0xf1, 0x14, + 0xfb, 0x1d, 0xeb, 0xee, 0xf2, 0xeb, 0xf3, 0xed, 0x0e, 0x35, 0xf0, 0x06, + 0x19, 0x04, 0x2f, 0x23, 0xe2, 0x07, 0x13, 0x0f, 0xe9, 0xf0, 0x22, 0x2e, + 0xd9, 0x1a, 0xcb, 0xed, 0xfd, 0x04, 0x27, 0x1e, 0xf6, 0x07, 0x96, 0xd6, + 0xd8, 0x11, 0x18, 0x56, 0xd2, 0xfb, 0x92, 0xfc, 0x0b, 0x0a, 0x17, 0x2c, + 0xe5, 0x04, 0xa2, 0xf8, 0xe2, 0x04, 0x1a, 0x0d, 0xeb, 0x11, 0xa2, 0xe5, + 0xe5, 0xf8, 0x02, 0xf7, 0x17, 0x03, 0xca, 0xe9, 0x0c, 0x1f, 0xfe, 0xf5, + 0x18, 0x12, 0xdd, 0x08, 0x15, 0xff, 0xfc, 0xf6, 0xe1, 0x1d, 0xe2, 0xe1, + 0xfe, 0xfc, 0x03, 0xff, 0xf2, 0x23, 0xd2, 0x01, 0x13, 0xdd, 0xf3, 0xf4, + 0xf2, 0x07, 0xef, 0x03, 0x15, 0x21, 0xd8, 0xf8, 0x09, 0xf3, 0xe8, 0xea, + 0xe8, 0xf2, 0x08, 0xf0, 0x04, 0x1a, 0xf2, 0x19, 0xfb, 0x1b, 0x15, 0xfc, + 0x1d, 0x30, 0xe5, 0x1e, 0x09, 0xe8, 0xe9, 0x09, 0xf7, 0x2a, 0xe1, 0x0e, + 0x00, 0x21, 0xf3, 0xff, 0xfb, 0x01, 0xdf, 0xf2, 0xfe, 0xf4, 0xfc, 0xf0, + 0x0b, 0x0b, 0xdd, 0xe4, 0xd2, 0x14, 0xf7, 0xfe, 0x0b, 0x39, 0x01, 0xe6, + 0xe4, 0x27, 0xfa, 0xe4, 0x04, 0x2c, 0xe2, 0x04, 0xf5, 0x07, 0xf2, 0x03, + 0xf0, 0x10, 0xf5, 0xf6, 0xfc, 0x16, 0x22, 0x1b, 0xf8, 0x11, 0xe4, 0x09, + 0xf6, 0xf0, 0x41, 0x1e, 0xcf, 0x04, 0xea, 0xee, 0x0e, 0xf6, 0x1b, 0x2f, + 0xc7, 0xf1, 0xba, 0xef, 0x0f, 0x16, 0x1e, 0x39, 0x05, 0x1e, 0x90, 0xe6, + 0x0d, 0xfa, 0x22, 0x3f, 0xe3, 0x23, 0xa5, 0xe3, 0xe9, 0x0f, 0x05, 0x27, + 0x02, 0x11, 0x99, 0x05, 0xfa, 0x05, 0x03, 0x01, 0xff, 0x26, 0xd3, 0xf7, + 0xf7, 0xf9, 0x05, 0xf4, 0xef, 0x23, 0xd2, 0xdd, 0x05, 0x08, 0xfa, 0xff, + 0x03, 0x04, 0xbd, 0xd7, 0x14, 0x06, 0xef, 0x06, 0xe5, 0x05, 0xea, 0xea, + 0x02, 0xfd, 0x0d, 0x00, 0x08, 0xff, 0xe7, 0xfb, 0xfe, 0x13, 0xfe, 0xec, + 0xf9, 0x02, 0xf3, 0xff, 0xff, 0x08, 0x04, 0xed, 0x19, 0x1d, 0xfa, 0x0a, + 0x0d, 0xf2, 0x0f, 0xec, 0x25, 0x1c, 0xec, 0x0b, 0x01, 0xff, 0x01, 0xf6, + 0x08, 0x09, 0xe8, 0xe2, 0xec, 0x23, 0xe5, 0xe9, 0xf0, 0x2e, 0xbd, 0xe1, + 0xef, 0x14, 0xe9, 0xf6, 0xf5, 0x1d, 0xdc, 0xe3, 0xd7, 0xfc, 0xf9, 0xf2, + 0xfe, 0x24, 0xf2, 0x05, 0xd5, 0xed, 0xe9, 0xf9, 0xfa, 0x2d, 0xf0, 0xfe, + 0xee, 0xf2, 0xe8, 0xf7, 0x06, 0x14, 0x01, 0x10, 0x06, 0xf3, 0x0e, 0x0e, + 0xc2, 0x1d, 0xf2, 0x1c, 0xed, 0xe3, 0x53, 0x21, 0xb8, 0x0c, 0xde, 0x03, + 0x15, 0xeb, 0x46, 0x39, 0xdf, 0xf6, 0xa3, 0xee, 0xf6, 0xe0, 0x33, 0x50, + 0xdd, 0x27, 0x9f, 0x07, 0x13, 0xe2, 0x1f, 0x35, 0xed, 0x1f, 0xb7, 0x07, + 0x11, 0xed, 0x17, 0x28, 0xf4, 0x20, 0xc1, 0xec, 0xef, 0x16, 0x02, 0xfa, + 0xe0, 0x1b, 0xf7, 0xdb, 0xfd, 0x0a, 0xe7, 0xfb, 0xe7, 0x25, 0xe2, 0xe7, + 0xf8, 0xf0, 0xee, 0xe9, 0x02, 0x06, 0xc9, 0xe4, 0x14, 0xe3, 0xe2, 0xf7, + 0xf8, 0xfd, 0xdd, 0xe2, 0x08, 0x0a, 0xe4, 0x05, 0xf5, 0x16, 0xe7, 0x01, + 0x00, 0x1c, 0xe7, 0xf0, 0xf6, 0x19, 0xfe, 0x0c, 0xf2, 0x06, 0x03, 0xe8, + 0x0b, 0xfe, 0xe3, 0x19, 0x08, 0x1a, 0x10, 0xfd, 0x00, 0x21, 0xf0, 0xeb, + 0x18, 0x02, 0xf3, 0x04, 0xf0, 0x18, 0xdb, 0x05, 0x01, 0xde, 0xed, 0xe9, + 0x23, 0x15, 0xaf, 0xe6, 0xf1, 0x0a, 0xe6, 0xea, 0x01, 0x18, 0xd8, 0xfd, + 0xf1, 0xe6, 0xec, 0xf5, 0x0e, 0x1e, 0xcc, 0xfc, 0xe7, 0x00, 0xe9, 0x11, + 0x00, 0x30, 0xf9, 0x14, 0xf4, 0x19, 0xdd, 0xf7, 0xf7, 0x2f, 0xf4, 0xf2, + 0xff, 0x27, 0x15, 0x1c, 0xbc, 0x2f, 0xe9, 0x14, 0xf5, 0xe8, 0x44, 0x30, + 0xe8, 0x1d, 0xe4, 0x18, 0x11, 0x00, 0x0c, 0x2b, 0xf3, 0x29, 0x96, 0xe0, + 0x06, 0xee, 0x3e, 0x55, 0xdc, 0x13, 0x98, 0xdf, 0xf0, 0xfe, 0x17, 0x33, + 0xe8, 0x09, 0xa3, 0x07, 0xef, 0x0e, 0x1d, 0x37, 0xdd, 0xfe, 0xb5, 0x00, + 0xf7, 0xe0, 0xea, 0xfd, 0xfd, 0x19, 0xbc, 0xfd, 0x15, 0xfe, 0x01, 0xf3, + 0xd5, 0x20, 0xbf, 0xe3, 0x15, 0x0e, 0xf0, 0xf6, 0xf2, 0x14, 0xcc, 0xf0, + 0xf7, 0x04, 0xf2, 0xff, 0x0b, 0x02, 0xd2, 0xd8, 0xfa, 0xfc, 0xe5, 0x02, + 0x00, 0xfb, 0xf0, 0xdc, 0x1e, 0x10, 0x02, 0x01, 0x00, 0x18, 0xe9, 0xdb, + 0x1e, 0xf6, 0xfc, 0x03, 0xef, 0x0a, 0x00, 0x16, 0x00, 0x0f, 0xf4, 0x16, + 0xfa, 0x0b, 0xe2, 0xfa, 0xe0, 0x07, 0xfb, 0x02, 0x21, 0x0e, 0xdd, 0x0b, + 0xea, 0xf0, 0xeb, 0xfb, 0x19, 0x09, 0xd4, 0xf2, 0xef, 0x0b, 0x00, 0xeb, + 0x1a, 0x2f, 0xea, 0x06, 0x03, 0xf6, 0xf8, 0xfb, 0xfe, 0x1d, 0xea, 0xdd, + 0xed, 0xfd, 0xfb, 0xe7, 0xfe, 0x18, 0xf4, 0xfc, 0x0b, 0xf6, 0xfc, 0x0b, + 0xfb, 0x28, 0x07, 0xff, 0x07, 0x1e, 0x03, 0x21, 0xcf, 0x22, 0x05, 0xe6, + 0xea, 0xe7, 0x43, 0x2e, 0xe7, 0x14, 0xfb, 0x0a, 0x1e, 0xfe, 0x2c, 0x24, + 0xd5, 0xfd, 0x9e, 0xd1, 0xf2, 0x1c, 0x32, 0x51, 0x01, 0xf3, 0xac, 0xe1, + 0xf4, 0xe5, 0x1c, 0x37, 0xf1, 0x0f, 0xa7, 0xdb, 0x00, 0xf6, 0x0f, 0x18, + 0xe1, 0x10, 0xc9, 0xc5, 0xe8, 0xeb, 0xf2, 0xfd, 0xf6, 0x02, 0xc2, 0xff, + 0x00, 0x19, 0x03, 0x0f, 0x02, 0x22, 0xd4, 0xe7, 0x07, 0x0f, 0xe5, 0x1a, + 0x09, 0x0b, 0xdc, 0xd2, 0x00, 0x05, 0xee, 0xf8, 0xdc, 0x14, 0xd0, 0x0a, + 0x0a, 0xfa, 0xeb, 0x04, 0xf3, 0x06, 0xde, 0x05, 0xfb, 0xfd, 0xe3, 0xec, + 0xfd, 0x14, 0xd7, 0x11, 0x0e, 0xe6, 0x06, 0xec, 0xde, 0x22, 0xd7, 0x00, + 0x03, 0xf5, 0xf5, 0x0d, 0x01, 0x05, 0xea, 0x0b, 0x16, 0x04, 0xff, 0x13, + 0xf3, 0x12, 0xd2, 0xdf, 0x0b, 0xe4, 0x06, 0xf6, 0x08, 0x2d, 0xd3, 0xd6, + 0xe7, 0x0a, 0xec, 0xff, 0xfe, 0x01, 0xdf, 0xf4, 0xdf, 0x1c, 0xfe, 0xf9, + 0xf7, 0x13, 0xca, 0xff, 0x03, 0x06, 0xe9, 0xf7, 0x06, 0x08, 0xd7, 0xf3, + 0xed, 0x08, 0xe3, 0xfd, 0x0c, 0x11, 0x15, 0xfb, 0x15, 0x08, 0x28, 0x40, + 0xe7, 0x0d, 0x08, 0xec, 0xe8, 0x16, 0x67, 0x46, 0xc8, 0x16, 0xf1, 0x02, + 0x24, 0x00, 0x3a, 0x43, 0xd6, 0x12, 0xae, 0xe7, 0xf4, 0xf8, 0x3a, 0x65, + 0xe4, 0x0c, 0xb2, 0xef, 0x1f, 0xe8, 0x29, 0x59, 0xf8, 0x11, 0xc4, 0xe1, + 0xfe, 0xfa, 0x27, 0x43, 0xc9, 0x1e, 0xbb, 0xfb, 0xf3, 0x13, 0x15, 0x0d, + 0xf1, 0x13, 0xcd, 0xf0, 0x07, 0x19, 0x07, 0x00, 0xd8, 0xeb, 0xbf, 0xf0, + 0xfc, 0xf6, 0xef, 0x16, 0x01, 0x02, 0xc1, 0xdf, 0xfd, 0xe9, 0x06, 0x06, + 0xf1, 0x08, 0xd7, 0xcc, 0xfb, 0x0e, 0xfc, 0x14, 0xf2, 0x1a, 0xe2, 0x0d, + 0xeb, 0x09, 0x07, 0x10, 0xe6, 0x13, 0xeb, 0xf5, 0x15, 0x14, 0xeb, 0xfe, + 0xf9, 0x17, 0xd2, 0xe3, 0x1e, 0xf5, 0x04, 0x0a, 0xf1, 0x0e, 0xde, 0xe7, + 0x01, 0x20, 0x0c, 0xfc, 0xdc, 0xf9, 0xe5, 0xe9, 0xff, 0x1d, 0x0a, 0xfe, + 0xec, 0x25, 0xaf, 0xd2, 0x01, 0x16, 0xfc, 0x17, 0xe8, 0x1e, 0xcd, 0xd9, + 0xe2, 0xf1, 0xeb, 0x08, 0xff, 0x33, 0xe5, 0xfb, 0xeb, 0x04, 0xfe, 0xf7, + 0xfd, 0x1f, 0xee, 0xff, 0xed, 0xf8, 0xe0, 0xff, 0xfd, 0x2b, 0x0a, 0xf5, + 0x15, 0x1d, 0xf3, 0x3f, 0x16, 0xf6, 0xf2, 0xee, 0xf4, 0xef, 0xf0, 0x56, + 0x0a, 0x1a, 0xbc, 0xfc, 0x2f, 0xfb, 0xf0, 0x56, 0x1e, 0x0e, 0xc6, 0xe8, + 0x06, 0x0b, 0x11, 0x62, 0x3e, 0xf9, 0xb8, 0xc9, 0xed, 0xeb, 0x02, 0x63, + 0x2c, 0xfd, 0xc5, 0xe9, 0x00, 0x17, 0x0f, 0x37, 0xfe, 0x20, 0xcc, 0xe0, + 0xe0, 0x0e, 0xe6, 0x20, 0x0a, 0xfd, 0xdf, 0xee, 0x0b, 0x02, 0xee, 0x1f, + 0xfb, 0x06, 0xd2, 0xed, 0xfe, 0xeb, 0xfc, 0x12, 0xfd, 0x14, 0x00, 0xd8, + 0x08, 0xf6, 0xec, 0x17, 0xf9, 0x10, 0x00, 0xd9, 0x18, 0xf1, 0xee, 0x0f, + 0xf4, 0x03, 0xee, 0xeb, 0xf0, 0xef, 0xf2, 0x06, 0x04, 0x00, 0xf4, 0x0f, + 0x09, 0x06, 0xf7, 0x0b, 0xfd, 0x01, 0x03, 0x03, 0xf4, 0xf6, 0xdd, 0x14, + 0x1c, 0xef, 0xf1, 0xdd, 0xf7, 0x13, 0xd9, 0x15, 0xef, 0x02, 0xd2, 0xe7, + 0x05, 0x05, 0xe2, 0x09, 0xf2, 0x11, 0xf5, 0xba, 0xf0, 0x04, 0xe0, 0x01, + 0x06, 0x10, 0xe6, 0xef, 0xfc, 0x12, 0xf9, 0xf4, 0x1b, 0x2f, 0xe3, 0x0f, + 0xd7, 0xf6, 0x0b, 0x11, 0xf7, 0x0c, 0x00, 0x06, 0x18, 0xef, 0x06, 0x03, + 0x0a, 0x09, 0xf6, 0x1a, 0x0d, 0xed, 0xfe, 0x2c, 0x43, 0xf4, 0xe5, 0xde, + 0xf5, 0x02, 0x25, 0x5a, 0x49, 0xd4, 0xe6, 0x24, 0x1e, 0xf7, 0x0e, 0x5c, + 0x5d, 0xf0, 0xf9, 0xe4, 0x1c, 0xeb, 0x28, 0x7f, 0x5b, 0xec, 0xfa, 0xdb, + 0x0c, 0xf5, 0x20, 0x49, 0x51, 0xe1, 0xed, 0xe6, 0x0e, 0x26, 0x28, 0x33, + 0x35, 0x05, 0xe1, 0xe4, 0x1f, 0xfc, 0xf9, 0x39, 0x18, 0x04, 0xed, 0xed, + 0x01, 0xe7, 0xe6, 0x08, 0x09, 0x03, 0xe7, 0xf9, 0x0e, 0x06, 0xec, 0x08, + 0x12, 0x1a, 0xda, 0xef, 0xdf, 0xf9, 0xe2, 0x1e, 0x1c, 0x00, 0x12, 0xd7, + 0x01, 0xf7, 0x21, 0x17, 0x13, 0x19, 0xde, 0xe0, 0xec, 0x16, 0x01, 0x1b, + 0x06, 0x0c, 0xf0, 0xe8, 0x18, 0x03, 0x06, 0x0e, 0x09, 0xfa, 0x03, 0xf3, + 0xdd, 0x01, 0xfb, 0x0a, 0x2a, 0xf4, 0xf6, 0xda, 0xe9, 0xfe, 0xe9, 0x12, + 0x19, 0xe9, 0x05, 0xdf, 0x00, 0xeb, 0xf2, 0x10, 0x0c, 0xe1, 0xcd, 0xcb, + 0xf2, 0x1f, 0xd9, 0x0c, 0xfa, 0xfb, 0xe8, 0xde, 0x00, 0xfc, 0xe5, 0x00, + 0x11, 0x02, 0xe6, 0x17, 0x14, 0x00, 0xf2, 0xfd, 0x00, 0xe1, 0x10, 0x24, + 0x12, 0xec, 0xed, 0x1e, 0x09, 0x18, 0x03, 0x0c, 0x04, 0xf4, 0x15, 0x0f, + 0x10, 0x18, 0xd6, 0x29, 0x10, 0x04, 0x1c, 0xef, 0x0f, 0x0c, 0xc7, 0x04, + 0xfe, 0xeb, 0xff, 0xf5, 0xe3, 0x15, 0xfe, 0xcb, 0x10, 0xff, 0x12, 0xfb, + 0xe4, 0xeb, 0xf9, 0x00, 0x02, 0xf1, 0x14, 0x13, 0x01, 0x02, 0xf9, 0x01, + 0x06, 0x0c, 0xf5, 0x0a, 0x1e, 0x01, 0x19, 0x0e, 0x05, 0xf5, 0x0a, 0xff, + 0xff, 0xf2, 0xfb, 0xdb, 0xf8, 0x06, 0x17, 0xf2, 0xf7, 0x0d, 0x0e, 0xf4, + 0xfa, 0xf7, 0x14, 0xdb, 0xe0, 0xfd, 0x08, 0x16, 0xf7, 0x16, 0xfc, 0x09, + 0x27, 0x07, 0x09, 0xfb, 0x0a, 0xfc, 0x0c, 0xe4, 0xdb, 0xee, 0xff, 0x10, + 0xf3, 0x09, 0xfa, 0xf4, 0x23, 0xf3, 0xf4, 0x19, 0xff, 0xfa, 0xff, 0x19, + 0x0f, 0x11, 0xed, 0xec, 0xf8, 0x0f, 0x10, 0xf3, 0xff, 0x0b, 0xf7, 0x06, + 0x0b, 0x0e, 0x07, 0xe4, 0x18, 0x0a, 0x08, 0x0e, 0x02, 0x0a, 0x05, 0x19, + 0x02, 0xf3, 0xfe, 0xfe, 0x0b, 0x0f, 0xfc, 0xfa, 0x05, 0xf9, 0xe2, 0xf9, + 0x1b, 0xf7, 0x0f, 0x07, 0xfc, 0x12, 0xfe, 0x01, 0xfd, 0xf0, 0x04, 0xf4, + 0xfd, 0x07, 0xf2, 0x04, 0x04, 0x07, 0xef, 0x0c, 0xed, 0x0e, 0xf6, 0xef, + 0x08, 0x07, 0x04, 0xe9, 0xf3, 0x20, 0xda, 0x15, 0xf8, 0xff, 0xec, 0xe0, + 0xf6, 0xff, 0xe9, 0x08, 0x01, 0x10, 0xf0, 0xfc, 0xe9, 0x08, 0xe8, 0xf5, + 0xf8, 0xe5, 0x17, 0xe6, 0x03, 0xfc, 0x09, 0xf5, 0xdd, 0xf2, 0xff, 0x05, + 0xf6, 0xf8, 0xf5, 0x07, 0xfc, 0xf1, 0x04, 0xf3, 0x13, 0xe1, 0x0f, 0xf2, + 0x0a, 0xf9, 0xfd, 0x1c, 0xe0, 0x11, 0x1b, 0xe6, 0xef, 0x05, 0x05, 0x0c, + 0x23, 0x10, 0x09, 0xfe, 0xf7, 0x1a, 0xf1, 0xfc, 0x11, 0x1d, 0xff, 0x03, + 0x03, 0xe6, 0x07, 0x11, 0x0c, 0x0d, 0x16, 0x05, 0x05, 0x25, 0xf3, 0x10, + 0x10, 0x06, 0x09, 0xe8, 0x1a, 0xf0, 0xee, 0x09, 0xff, 0x24, 0xf7, 0xfb, + 0xe6, 0x06, 0xfa, 0x08, 0x03, 0x00, 0xf2, 0x04, 0xf0, 0xeb, 0x14, 0x1c, + 0x03, 0x21, 0x14, 0x1d, 0xfe, 0x03, 0xf6, 0x02, 0x09, 0xff, 0x00, 0x13, + 0xef, 0x10, 0x1e, 0x0b, 0x1d, 0x1c, 0xf1, 0xf6, 0xe7, 0xfd, 0x14, 0x01, + 0xff, 0x13, 0xf7, 0xfc, 0x00, 0x21, 0xe3, 0xeb, 0x07, 0x0e, 0x09, 0xf1, + 0xf8, 0xfd, 0x03, 0xee, 0x19, 0xfd, 0xff, 0xfb, 0xff, 0xea, 0xfb, 0x07, + 0xf0, 0x0a, 0x04, 0x04, 0x0b, 0x12, 0xfe, 0x0b, 0xe0, 0xff, 0xf6, 0xe5, + 0xfc, 0x11, 0xed, 0xfd, 0x15, 0x03, 0xdd, 0xdb, 0x04, 0xfe, 0xff, 0x0e, + 0xff, 0xfa, 0xfb, 0xe5, 0xef, 0xf6, 0xfe, 0x22, 0x0f, 0xe8, 0xfe, 0xf4, + 0xfd, 0xd9, 0x03, 0x0a, 0xdf, 0xcf, 0xf1, 0x14, 0x05, 0xfd, 0xfb, 0xf3, + 0xfb, 0xfb, 0x0f, 0xf8, 0x05, 0x09, 0x03, 0xf7, 0x05, 0x05, 0x13, 0xfb, + 0xeb, 0x23, 0xe7, 0x18, 0xfb, 0x00, 0xfe, 0xdd, 0xe9, 0xea, 0xd3, 0xe8, + 0x1a, 0xef, 0x01, 0xf1, 0x09, 0x1d, 0xd8, 0xfc, 0xda, 0x19, 0x03, 0xec, + 0xe5, 0xf3, 0xed, 0x0a, 0xf4, 0x13, 0x0b, 0xf7, 0x0c, 0x00, 0xf9, 0xea, + 0xe3, 0xfe, 0xff, 0x0d, 0x0a, 0x1b, 0xd7, 0x17, 0xeb, 0xe9, 0x00, 0x0e, + 0xee, 0x24, 0xef, 0x09, 0x07, 0xf0, 0xf5, 0x07, 0xf5, 0xf5, 0x10, 0x17, + 0x06, 0xf7, 0xfc, 0x02, 0xfb, 0xf9, 0xe7, 0x0a, 0x26, 0xf3, 0x01, 0x01, + 0x09, 0x0b, 0x02, 0x27, 0xf8, 0xee, 0xfd, 0x1c, 0xf8, 0xf2, 0x0f, 0xfc, + 0x0d, 0xe0, 0xea, 0x02, 0x0b, 0x00, 0xe0, 0x08, 0xfe, 0x10, 0x04, 0xfe, + 0xeb, 0x13, 0x01, 0x0c, 0x0e, 0xed, 0x09, 0x01, 0x0c, 0xe3, 0x10, 0xdf, + 0xd1, 0x14, 0xf3, 0xef, 0x09, 0xf0, 0xee, 0xe5, 0x11, 0xf4, 0xf6, 0x00, + 0xe8, 0x20, 0x0a, 0xfc, 0xea, 0xf7, 0x02, 0x16, 0xe7, 0xf3, 0x0d, 0xe4, + 0x04, 0xe6, 0xef, 0xf8, 0x0f, 0x23, 0x02, 0xe0, 0x01, 0x01, 0x01, 0x05, + 0xf5, 0x0d, 0xf5, 0xf5, 0xe1, 0xff, 0x04, 0x00, 0xf4, 0x0d, 0xee, 0xf1, + 0xef, 0xf7, 0x0b, 0xff, 0x1b, 0xec, 0x05, 0xe7, 0xf3, 0x13, 0x12, 0xf2, + 0xf3, 0xfc, 0xea, 0x06, 0xfe, 0x13, 0x12, 0xdb, 0x11, 0xe2, 0xfc, 0x0d, + 0x1c, 0xe8, 0x1d, 0xfc, 0xf2, 0xe2, 0x13, 0x1d, 0xda, 0xf6, 0x1c, 0x18, + 0x1e, 0xf4, 0xfa, 0x03, 0xdc, 0x0f, 0xff, 0xff, 0x18, 0x0b, 0xed, 0xf1, + 0xf8, 0x02, 0xf4, 0x10, 0xf9, 0xeb, 0x0b, 0x0e, 0x0f, 0x01, 0x02, 0x1b, + 0x06, 0x10, 0x00, 0xe7, 0x23, 0x0d, 0xf6, 0x11, 0x08, 0xf5, 0x0f, 0x05, + 0x13, 0xf7, 0x01, 0x01, 0x0c, 0xf6, 0xf9, 0xf0, 0x29, 0x01, 0xe9, 0x11, + 0x02, 0xfa, 0xeb, 0x16, 0x0e, 0x10, 0x09, 0x0e, 0x1c, 0x0a, 0xe3, 0xd3, + 0x01, 0xe3, 0x00, 0x06, 0xe2, 0xe9, 0x19, 0xef, 0x12, 0xf3, 0xfc, 0x02, + 0x0b, 0x0c, 0x0d, 0xed, 0xfd, 0xf6, 0xf9, 0xe9, 0xf2, 0x28, 0xfe, 0x03, + 0xec, 0x03, 0x00, 0xf8, 0xde, 0x0d, 0x25, 0x07, 0x1a, 0xe7, 0xfd, 0x29, + 0xd8, 0xf7, 0xfb, 0xde, 0x0c, 0x08, 0x06, 0x22, 0xee, 0x1d, 0x05, 0x07, + 0xf0, 0xfb, 0xfe, 0x07, 0xf1, 0x04, 0xe9, 0x01, 0xfc, 0xf1, 0x00, 0xeb, + 0xe3, 0x08, 0xec, 0xfe, 0x04, 0xeb, 0xfc, 0x01, 0xf6, 0x0e, 0xdf, 0xf8, + 0x12, 0xe3, 0x16, 0xdc, 0x21, 0x0a, 0xe6, 0x06, 0xe5, 0x10, 0x07, 0xf7, + 0x1e, 0xde, 0xe3, 0x07, 0x16, 0xed, 0x23, 0xf2, 0x12, 0x0d, 0xe9, 0xf9, + 0xe8, 0xfe, 0x0e, 0x02, 0x18, 0x0a, 0xea, 0xec, 0xfb, 0xfe, 0x0c, 0x1b, + 0x19, 0x20, 0xfa, 0x07, 0xe5, 0x0c, 0x04, 0x27, 0xdb, 0xe6, 0xfe, 0x0d, + 0x0a, 0x0a, 0xfe, 0x39, 0xdd, 0xde, 0x05, 0xec, 0x09, 0x05, 0x0a, 0x2c, + 0xf4, 0x02, 0x1f, 0xd3, 0x24, 0xee, 0x0f, 0x3c, 0xf5, 0xfd, 0xf8, 0xf8, + 0x12, 0xf5, 0xf3, 0x19, 0xf9, 0xda, 0xf6, 0x0a, 0x0a, 0xf4, 0x09, 0x0f, + 0xfc, 0x00, 0x01, 0x01, 0xf3, 0xf8, 0x05, 0xf3, 0x0c, 0x19, 0x0e, 0xfd, + 0xfa, 0xe1, 0xfc, 0x0c, 0x03, 0xfb, 0x1b, 0x06, 0xcc, 0xe4, 0x08, 0xf9, + 0x10, 0xe9, 0x06, 0x00, 0x17, 0xe8, 0x0d, 0x12, 0xca, 0xf5, 0x23, 0xe4, + 0x21, 0xf6, 0x19, 0x33, 0xdd, 0xfa, 0x0c, 0x01, 0x14, 0x07, 0x00, 0x34, + 0xda, 0x05, 0x07, 0x01, 0x07, 0xe4, 0x06, 0x24, 0x02, 0xff, 0xf0, 0x09, + 0xfc, 0xf4, 0x03, 0x06, 0xee, 0x08, 0xe2, 0x1d, 0xfa, 0x0c, 0xfc, 0x02, + 0x03, 0xe5, 0xf0, 0xe2, 0x0a, 0x18, 0x12, 0x0c, 0x1e, 0x20, 0xed, 0x20, + 0xe4, 0x01, 0x2a, 0x09, 0x0d, 0x0e, 0xd0, 0xf4, 0xdd, 0xfd, 0x2b, 0xf2, + 0x08, 0x0c, 0xf8, 0xf7, 0xfc, 0xf9, 0x15, 0xef, 0x19, 0x1c, 0x01, 0xff, + 0xe2, 0x01, 0xf3, 0x30, 0x0e, 0xfb, 0x15, 0xe8, 0x1c, 0x00, 0xfa, 0x16, + 0xef, 0xea, 0xfb, 0x05, 0xf0, 0x0e, 0x02, 0x13, 0xf4, 0x01, 0x03, 0xe5, + 0x29, 0x07, 0x09, 0x24, 0xf9, 0xe3, 0xf8, 0xde, 0x2d, 0xf4, 0xf5, 0x40, + 0xed, 0xdf, 0x07, 0xef, 0x0f, 0x0a, 0x0b, 0x32, 0x0d, 0xe8, 0x00, 0xe6, + 0xf6, 0xfc, 0xfd, 0x19, 0x11, 0x09, 0xf3, 0x03, 0xea, 0xf1, 0xfb, 0x02, + 0xfd, 0x06, 0xff, 0xfe, 0x09, 0xec, 0x06, 0x0c, 0x15, 0xf9, 0x06, 0xd7, + 0xe3, 0xf7, 0xed, 0x01, 0x03, 0xfd, 0x14, 0x01, 0x0e, 0xe0, 0x37, 0x0d, + 0xd2, 0x18, 0x2f, 0xea, 0x12, 0x0d, 0x05, 0x3a, 0xd5, 0x07, 0x1e, 0xf2, + 0x21, 0x11, 0xf9, 0x36, 0xd3, 0xf5, 0x12, 0xf6, 0xfb, 0xf6, 0x06, 0x0f, + 0xde, 0xf9, 0x06, 0x09, 0xdf, 0xff, 0x0b, 0xf3, 0xf5, 0x01, 0xf1, 0xea, + 0xf2, 0x02, 0x12, 0xfc, 0x0e, 0xee, 0xf8, 0xeb, 0x00, 0xef, 0x21, 0x0f, + 0x09, 0xef, 0xeb, 0x1e, 0xef, 0xf2, 0x26, 0xf9, 0x17, 0xf1, 0xf1, 0xf0, + 0x0c, 0x10, 0x1d, 0xff, 0x1d, 0x06, 0x03, 0xf6, 0xfb, 0x14, 0x1b, 0x03, + 0x22, 0xfd, 0xec, 0x03, 0xfa, 0xf8, 0x01, 0x2b, 0x1e, 0x1b, 0x09, 0x09, + 0x07, 0xff, 0xf0, 0x20, 0xee, 0x14, 0xfb, 0xf6, 0xf8, 0x11, 0xd9, 0x29, + 0xf4, 0xfa, 0x07, 0xef, 0x20, 0xf9, 0xf2, 0x30, 0xee, 0xf0, 0xf3, 0xd6, + 0x0d, 0xfe, 0x03, 0x36, 0xf5, 0xd7, 0x01, 0xe6, 0x04, 0xf0, 0x05, 0x1f, + 0x0f, 0xdd, 0xff, 0xf8, 0x1f, 0xf2, 0x04, 0x37, 0xfa, 0x00, 0xfd, 0xf8, + 0x10, 0xe1, 0xfb, 0x0d, 0xed, 0xf6, 0xe2, 0xfe, 0x08, 0xfe, 0x07, 0x08, + 0x08, 0x11, 0x0a, 0xf0, 0xf8, 0xf5, 0x04, 0xea, 0x08, 0x12, 0x06, 0x0d, + 0x0f, 0x10, 0x40, 0x28, 0xc0, 0xfb, 0x3f, 0x08, 0x1d, 0x09, 0x1b, 0x3d, + 0xee, 0xf4, 0x29, 0x13, 0x20, 0xfc, 0x11, 0x4c, 0xdb, 0x02, 0x15, 0x05, + 0xec, 0xeb, 0x0a, 0x22, 0xe7, 0x00, 0x02, 0x01, 0xd4, 0xea, 0x0a, 0xf3, + 0xe3, 0xf8, 0xf5, 0xfa, 0x01, 0x0d, 0x19, 0x06, 0x24, 0x13, 0x02, 0xf5, + 0xf1, 0xf1, 0x1b, 0x0f, 0x19, 0x04, 0xe3, 0xf9, 0xe7, 0x02, 0x29, 0xfc, + 0x29, 0xec, 0xe9, 0x04, 0xdc, 0x22, 0x1d, 0xfd, 0x1f, 0x01, 0xec, 0xe8, + 0xf5, 0x14, 0x1b, 0x19, 0x06, 0x0e, 0x02, 0x0d, 0xf9, 0x06, 0xfc, 0x15, + 0x07, 0xfa, 0x0c, 0xe1, 0x18, 0x1a, 0xe8, 0x1b, 0xe9, 0xef, 0x0a, 0x18, + 0xfc, 0x05, 0xf9, 0x14, 0xdc, 0x04, 0x01, 0xff, 0x07, 0xfd, 0xf0, 0x2c, + 0xf2, 0xec, 0x0e, 0xe7, 0x1a, 0x05, 0xe8, 0x35, 0x13, 0x09, 0xf9, 0x07, + 0xfe, 0xfa, 0x0d, 0x40, 0x0c, 0xea, 0xf4, 0x04, 0x01, 0x11, 0xfc, 0x23, + 0xeb, 0xf4, 0xe9, 0x04, 0xeb, 0xe7, 0x07, 0x09, 0xfb, 0xf1, 0xf6, 0xfd, + 0x02, 0xfa, 0x02, 0xff, 0x00, 0xff, 0xf1, 0xf1, 0x1a, 0xe9, 0x10, 0xe3, + 0x0b, 0x0c, 0x08, 0x04, 0x1b, 0x0a, 0x2b, 0x10, 0xe1, 0x01, 0x1f, 0x06, + 0x04, 0xec, 0x19, 0x49, 0xee, 0xf8, 0x22, 0x0c, 0x20, 0x02, 0x07, 0x31, + 0xe7, 0xff, 0x0f, 0xf0, 0xfd, 0xea, 0x13, 0x26, 0xce, 0xfa, 0xff, 0xee, + 0xe9, 0xfe, 0x15, 0x08, 0x04, 0x05, 0x0d, 0xfa, 0xdd, 0xf8, 0x07, 0x0b, + 0x33, 0xef, 0xec, 0xf9, 0xd9, 0xe6, 0x1d, 0x10, 0x41, 0xf6, 0xdf, 0x11, + 0xe3, 0x14, 0x1d, 0xfb, 0x2b, 0x15, 0xdc, 0x09, 0xf6, 0x05, 0x16, 0x00, + 0x1c, 0x27, 0xe4, 0xfc, 0xf7, 0x16, 0x08, 0x08, 0x2f, 0xdd, 0xf8, 0xfa, + 0xe9, 0x0e, 0x0b, 0x0b, 0x02, 0x12, 0x02, 0xfd, 0x19, 0x03, 0xeb, 0x11, + 0xf4, 0x09, 0x09, 0x15, 0x12, 0x0d, 0xef, 0x1c, 0xe4, 0xfe, 0x17, 0x0c, + 0x09, 0x04, 0xea, 0x2f, 0xf2, 0x1e, 0x02, 0xfb, 0xfe, 0xe3, 0x00, 0x2e, + 0x04, 0xf9, 0x0c, 0x05, 0x27, 0x0c, 0x07, 0x2d, 0xf7, 0x0b, 0xfb, 0xf9, + 0x1c, 0xdf, 0x11, 0x36, 0x05, 0xf2, 0x02, 0xf8, 0x0b, 0x07, 0x05, 0xfb, + 0xfc, 0x0e, 0x13, 0xfa, 0xfb, 0x09, 0xf5, 0xfd, 0x06, 0x15, 0xf9, 0x03, + 0x18, 0xfd, 0x1a, 0x0a, 0x03, 0xe2, 0xfb, 0x00, 0x1e, 0xfe, 0x4f, 0x27, + 0xe1, 0xf7, 0x31, 0xf0, 0x1b, 0xec, 0x07, 0x5f, 0xe2, 0xf8, 0x40, 0x05, + 0x17, 0x24, 0x0c, 0x3c, 0xf3, 0x10, 0x13, 0xf8, 0x0b, 0xf3, 0xf9, 0x36, + 0xe1, 0xf3, 0xf4, 0xe8, 0xef, 0xf8, 0xfc, 0xeb, 0xe3, 0xfb, 0xf0, 0xee, + 0xdb, 0x06, 0x0c, 0x11, 0x1e, 0x10, 0xe2, 0xe9, 0xeb, 0x0d, 0x34, 0x0f, + 0x43, 0xd9, 0xef, 0x08, 0xec, 0x05, 0x1d, 0x02, 0x33, 0xef, 0xf4, 0xf7, + 0xe6, 0xf9, 0x22, 0x07, 0x04, 0x06, 0xe9, 0x02, 0xf0, 0xfc, 0x24, 0x20, + 0x24, 0x17, 0xe6, 0x0f, 0x05, 0xf6, 0xfc, 0x1f, 0xf2, 0x01, 0x0d, 0xe7, + 0xff, 0x1d, 0xf0, 0xfa, 0xd0, 0x00, 0xff, 0x0e, 0x23, 0xf9, 0xf3, 0x11, + 0xde, 0x0d, 0x05, 0x04, 0x0b, 0x0b, 0xfb, 0x26, 0x0d, 0x0d, 0xff, 0xe8, + 0x16, 0xe8, 0x0b, 0x3c, 0x18, 0xe4, 0x04, 0xff, 0xfa, 0xf3, 0xff, 0x40, + 0xee, 0x06, 0xfc, 0x0d, 0x00, 0xf7, 0x13, 0x3f, 0xf7, 0x13, 0x06, 0x08, + 0xf9, 0x13, 0xf2, 0x19, 0xfd, 0xf9, 0xf3, 0xe6, 0xfc, 0x07, 0xf6, 0xfd, + 0x0a, 0x22, 0x00, 0x01, 0x19, 0xff, 0xe7, 0xff, 0x08, 0xfd, 0x03, 0xfd, + 0x1f, 0xe7, 0x28, 0x08, 0xde, 0xf3, 0x43, 0xf6, 0x0c, 0xfe, 0x1e, 0x52, + 0xf2, 0x04, 0x17, 0xf2, 0x08, 0x0d, 0x04, 0x38, 0xde, 0x0c, 0x10, 0xef, + 0xdf, 0x0f, 0x01, 0x24, 0xde, 0xe1, 0x0d, 0xfd, 0xd4, 0xf6, 0x12, 0x0e, + 0xed, 0x01, 0xf0, 0xf3, 0xfd, 0xff, 0x18, 0xf3, 0x36, 0xda, 0xf6, 0xef, + 0xe8, 0xef, 0x37, 0x27, 0x4e, 0xf8, 0xf4, 0xff, 0xe5, 0xf3, 0x32, 0x0b, + 0x36, 0x08, 0xe9, 0xf6, 0xe2, 0x13, 0x21, 0xfe, 0x12, 0xed, 0xdd, 0xfb, + 0xf8, 0x05, 0x0f, 0x03, 0x1c, 0x04, 0xfc, 0xf2, 0x23, 0x0e, 0x03, 0xfc, + 0xf9, 0x18, 0xf7, 0x01, 0x1b, 0x03, 0xf5, 0xfd, 0xde, 0xf3, 0x19, 0xfc, + 0x11, 0x02, 0xe7, 0x13, 0xde, 0xd8, 0xf2, 0x05, 0x28, 0x02, 0x02, 0x27, + 0x07, 0x08, 0xff, 0x07, 0x27, 0x0e, 0x19, 0x40, 0xfb, 0x02, 0x0c, 0xf6, + 0x0d, 0x07, 0x0f, 0x47, 0xf8, 0x05, 0x0e, 0xfd, 0x03, 0x1e, 0x07, 0x32, + 0xe7, 0xf6, 0x24, 0x01, 0x01, 0x02, 0x0a, 0xff, 0xf6, 0x26, 0x15, 0xf0, + 0x04, 0x13, 0x03, 0xfa, 0xfe, 0xf6, 0xf1, 0x09, 0x2a, 0xe6, 0xea, 0xf6, + 0x17, 0x13, 0xeb, 0xff, 0x15, 0xeb, 0x23, 0x06, 0xc8, 0xf6, 0x33, 0xeb, + 0xf4, 0xe7, 0x12, 0x2a, 0xe3, 0xe6, 0x32, 0xfa, 0x16, 0x15, 0x17, 0x40, + 0xf1, 0x08, 0x1a, 0xf3, 0xf6, 0x0c, 0x0c, 0x11, 0xd0, 0x22, 0x02, 0xee, + 0xea, 0xf4, 0xf8, 0xf9, 0x13, 0x10, 0x17, 0xf5, 0xf1, 0x0a, 0x0e, 0xfd, + 0x32, 0xda, 0xf1, 0xe2, 0xdb, 0xf2, 0x34, 0x1f, 0x53, 0xfc, 0xe4, 0xf2, + 0xf6, 0xf2, 0x1d, 0x04, 0x4a, 0xec, 0xee, 0x06, 0xdf, 0x01, 0x1a, 0x04, + 0x27, 0xfc, 0xe6, 0xfd, 0xd9, 0xfd, 0x0e, 0x00, 0x0c, 0x16, 0xf3, 0x03, + 0xf7, 0xfc, 0x0e, 0x0f, 0x09, 0x06, 0x06, 0x04, 0x08, 0x02, 0xed, 0xf5, + 0xe4, 0xe6, 0x07, 0x06, 0x03, 0x18, 0xea, 0x13, 0xe2, 0xfa, 0x10, 0xf2, + 0x02, 0xec, 0x03, 0x3c, 0xf6, 0xf6, 0x0a, 0x10, 0x09, 0xf8, 0x15, 0x24, + 0xfd, 0x0d, 0x09, 0x01, 0x00, 0xff, 0x00, 0x1a, 0xf0, 0xee, 0x08, 0x03, + 0x1d, 0x05, 0x16, 0x46, 0xe6, 0xf8, 0x08, 0x00, 0x09, 0x09, 0xff, 0x01, + 0xfc, 0x20, 0xfc, 0xec, 0x05, 0x1b, 0x03, 0xf1, 0x12, 0xe4, 0xfa, 0x24, + 0x1c, 0xf5, 0xf2, 0x05, 0x11, 0xe7, 0xfa, 0x02, 0x20, 0xea, 0x31, 0x10, + 0xcf, 0xd8, 0x33, 0xee, 0xff, 0x09, 0x20, 0x3f, 0xe2, 0x0a, 0x29, 0xee, + 0x3a, 0xf2, 0x1e, 0x39, 0x02, 0x1e, 0xfe, 0xf2, 0xef, 0xe2, 0x0d, 0x0f, + 0xf1, 0x19, 0x02, 0xe7, 0xec, 0xff, 0xfe, 0xe4, 0xfe, 0xfb, 0x02, 0xf6, + 0xf1, 0xf4, 0x07, 0x1a, 0x2a, 0xf9, 0x06, 0xf9, 0xda, 0xf4, 0x22, 0x02, + 0x4f, 0x0a, 0xf3, 0xfc, 0xf3, 0xf6, 0x25, 0x0a, 0x28, 0x01, 0xf7, 0x09, + 0xe6, 0x05, 0x28, 0xf7, 0x1e, 0xf2, 0xee, 0x13, 0xee, 0x05, 0x0f, 0x0a, + 0x09, 0xe8, 0xe8, 0x0e, 0x05, 0x12, 0x0f, 0x15, 0x02, 0xec, 0xf8, 0x02, + 0xf7, 0x05, 0xf8, 0xff, 0xdc, 0x00, 0x01, 0x00, 0x12, 0x17, 0xec, 0x19, + 0xfa, 0x09, 0xfa, 0xf3, 0x1d, 0x0b, 0x07, 0x25, 0xea, 0x0c, 0xf5, 0xfa, + 0x04, 0xf7, 0xfe, 0x33, 0xfe, 0x14, 0xef, 0x04, 0xf0, 0x00, 0x00, 0x3a, + 0xea, 0xfa, 0x10, 0x01, 0xe4, 0x00, 0xff, 0x23, 0xe9, 0x26, 0x15, 0x10, + 0x04, 0x14, 0x0d, 0x08, 0xf8, 0xfd, 0x10, 0xfb, 0x00, 0x21, 0x06, 0xfa, + 0x0f, 0x08, 0xf1, 0x09, 0x28, 0xf0, 0xd8, 0x0d, 0x08, 0x09, 0x02, 0xfb, + 0x12, 0x03, 0x0e, 0xfb, 0xce, 0xf0, 0x39, 0xe5, 0x09, 0xf6, 0x1f, 0x35, + 0xdd, 0x1c, 0x25, 0xef, 0x17, 0x0c, 0xf6, 0x3e, 0xf0, 0x21, 0x08, 0xff, + 0xd7, 0xfc, 0xfd, 0x1f, 0xe5, 0x18, 0x12, 0xe9, 0xf5, 0xe9, 0x12, 0xf6, + 0x02, 0x13, 0xf4, 0x0a, 0xfd, 0x03, 0x09, 0x08, 0x2f, 0x07, 0xee, 0xfd, + 0xd7, 0x00, 0x2b, 0x29, 0x3b, 0xdb, 0xde, 0xf1, 0xe1, 0xf7, 0x47, 0x12, + 0x35, 0x0c, 0xe4, 0x09, 0xef, 0x17, 0x2b, 0xea, 0x2d, 0xf8, 0xe8, 0x18, + 0xef, 0x03, 0x11, 0x0a, 0x10, 0xff, 0xe8, 0x07, 0x0c, 0x07, 0x03, 0x18, + 0x05, 0x08, 0xf8, 0xf8, 0x06, 0x18, 0xe9, 0xf9, 0xe0, 0x0f, 0x0d, 0x18, + 0x04, 0x01, 0xf0, 0x1c, 0xf6, 0x14, 0xfd, 0x12, 0x0c, 0x0c, 0x02, 0x34, + 0xf6, 0xe6, 0xfd, 0xf9, 0xf9, 0xfd, 0x00, 0x2a, 0xfc, 0xf9, 0xff, 0x0a, + 0xfe, 0x1b, 0xf5, 0x34, 0xdc, 0xf9, 0x15, 0x13, 0xe7, 0x1b, 0xf7, 0x25, + 0xfd, 0x09, 0x08, 0x0a, 0xf0, 0x17, 0x0f, 0x04, 0xf4, 0xe9, 0x06, 0x07, + 0xf5, 0x02, 0xfc, 0xf5, 0x09, 0xee, 0xf1, 0x07, 0x38, 0x03, 0x05, 0x0f, + 0x16, 0x0f, 0xed, 0xff, 0x21, 0xf8, 0x34, 0x07, 0xd1, 0xf9, 0x27, 0x00, + 0x0c, 0x21, 0x18, 0x42, 0xe6, 0x02, 0x1a, 0xf1, 0x2f, 0xf1, 0x0e, 0x3b, + 0xee, 0xf8, 0x08, 0xea, 0xfe, 0xf9, 0x03, 0x18, 0xf5, 0xf8, 0x0d, 0xeb, + 0x01, 0x10, 0x09, 0x02, 0x15, 0xfb, 0xf1, 0x0b, 0xf2, 0x06, 0x08, 0x09, + 0x2f, 0x19, 0x02, 0xfe, 0xe4, 0x06, 0x1f, 0x17, 0x49, 0xf2, 0xe2, 0x02, + 0xef, 0x04, 0x26, 0x16, 0x3f, 0x08, 0xf1, 0x0a, 0xfd, 0xf9, 0x28, 0x01, + 0x15, 0x0b, 0xf9, 0x10, 0xdc, 0x02, 0x20, 0xf7, 0x16, 0xe6, 0x09, 0x03, + 0xf1, 0xf5, 0x12, 0x1c, 0xfb, 0x2a, 0x08, 0xfa, 0x0a, 0x16, 0xf6, 0x15, + 0xf0, 0x06, 0x11, 0xfd, 0x0e, 0xf9, 0xf6, 0x12, 0xed, 0xf3, 0xfd, 0x1f, + 0x0b, 0xfa, 0x08, 0x30, 0xf8, 0xff, 0x0b, 0xeb, 0x10, 0xff, 0x07, 0x22, + 0x0d, 0x07, 0x09, 0x03, 0xf6, 0xf8, 0xfc, 0x26, 0xf8, 0xee, 0x11, 0x02, + 0x03, 0x0a, 0xef, 0x38, 0xfe, 0x13, 0x1b, 0x09, 0xfe, 0x06, 0x05, 0xf3, + 0x04, 0xdf, 0xfc, 0x00, 0xe7, 0x15, 0xec, 0xf1, 0xf8, 0xfc, 0xed, 0x05, + 0x0e, 0xf3, 0x15, 0x09, 0x01, 0x0d, 0xfd, 0x00, 0x24, 0xe2, 0x31, 0x13, + 0xd5, 0x1b, 0x2b, 0xe8, 0x03, 0x08, 0x1d, 0x33, 0xdc, 0xfd, 0x24, 0xe4, + 0x20, 0xfa, 0x07, 0x33, 0x01, 0x12, 0x06, 0xf5, 0xef, 0xf7, 0xfa, 0x13, + 0x01, 0xec, 0xee, 0xe0, 0xfd, 0x0d, 0xff, 0x09, 0xf6, 0x00, 0xed, 0x07, + 0xea, 0x0e, 0xff, 0x0e, 0x26, 0xfc, 0xf0, 0xe7, 0xe7, 0xfe, 0x30, 0xff, + 0x24, 0x04, 0x06, 0xf4, 0xf5, 0xf8, 0x23, 0x0e, 0x3d, 0xf2, 0xfd, 0x04, + 0xe8, 0xfb, 0x23, 0xfe, 0x33, 0xe1, 0x01, 0xfd, 0xdc, 0xfb, 0x0e, 0xfa, + 0x22, 0xfb, 0x11, 0xfa, 0xff, 0x08, 0x21, 0x30, 0x13, 0x03, 0xf2, 0x03, + 0xf8, 0x0f, 0xec, 0x0d, 0xef, 0x0f, 0x10, 0x10, 0x0f, 0xf6, 0xf9, 0x1e, + 0xf7, 0xe5, 0x08, 0xfa, 0x09, 0xff, 0x00, 0x15, 0x02, 0x00, 0x08, 0xfe, + 0xfb, 0x0e, 0x15, 0x28, 0xfa, 0xfb, 0x13, 0x06, 0xfb, 0x05, 0xf6, 0x11, + 0xf6, 0x0b, 0x06, 0x15, 0xe1, 0x00, 0xe9, 0x0f, 0xe1, 0x1d, 0x18, 0xfd, + 0x0b, 0x0f, 0xff, 0xf2, 0xf5, 0xfd, 0x14, 0xff, 0xf4, 0xfe, 0xe2, 0xf8, + 0x14, 0x0b, 0xeb, 0x07, 0x35, 0xe2, 0xeb, 0x0b, 0x04, 0x22, 0xfe, 0x0e, + 0x1d, 0xf2, 0x24, 0x11, 0xcc, 0xec, 0x25, 0xf7, 0xff, 0xf9, 0x06, 0x29, + 0xe4, 0x07, 0x1c, 0xdb, 0xf8, 0x1d, 0xfa, 0x44, 0xf2, 0x01, 0x0f, 0xe6, + 0x11, 0x03, 0xee, 0x17, 0x06, 0xe0, 0x0c, 0xd8, 0xe9, 0xfd, 0x11, 0xfe, + 0x07, 0xdd, 0xea, 0xff, 0xde, 0xdd, 0x0a, 0x09, 0x30, 0xf2, 0x01, 0xe4, + 0xe0, 0xeb, 0x2d, 0x12, 0x2d, 0xeb, 0xfc, 0xf0, 0xe8, 0xf9, 0x1f, 0x08, + 0x3f, 0xeb, 0x0e, 0x13, 0xf9, 0x0c, 0x1c, 0x02, 0x25, 0xec, 0xf6, 0x05, + 0xf3, 0xf4, 0x18, 0x08, 0x12, 0xe9, 0xfb, 0xfd, 0xf9, 0x08, 0x13, 0x1c, + 0x08, 0xec, 0xfe, 0x02, 0xf1, 0x19, 0xf3, 0x1d, 0xf1, 0x07, 0x11, 0x12, + 0xfa, 0xf2, 0xf6, 0x0d, 0xff, 0x17, 0x0a, 0xfb, 0x1f, 0xf8, 0x11, 0x24, + 0xf6, 0xfc, 0xfe, 0x07, 0xed, 0x05, 0x1c, 0x21, 0xfe, 0xfe, 0x16, 0x0d, + 0x08, 0x0f, 0x09, 0x33, 0xf4, 0x1f, 0x14, 0x0c, 0xfe, 0xf5, 0xeb, 0x2a, + 0xee, 0xf3, 0x12, 0x19, 0xec, 0x01, 0x06, 0xf7, 0x05, 0x22, 0x0b, 0xeb, + 0xeb, 0x06, 0xe1, 0xf5, 0x0d, 0xee, 0xfb, 0x0a, 0x31, 0xff, 0xe3, 0xea, + 0x18, 0x09, 0xe3, 0x07, 0x1a, 0xf8, 0x15, 0xfc, 0xcc, 0xf2, 0x2a, 0xe5, + 0x01, 0xea, 0x10, 0x1f, 0xd9, 0x02, 0x13, 0xf6, 0x16, 0x01, 0x0e, 0x3c, + 0x02, 0x17, 0x04, 0xf1, 0xf7, 0x02, 0x07, 0x0c, 0x02, 0x1f, 0xf4, 0xe6, + 0xf0, 0xe9, 0x05, 0xf4, 0xfd, 0xe4, 0xf7, 0xe9, 0xfc, 0xef, 0x06, 0x02, + 0x26, 0xf1, 0xf1, 0xeb, 0xe9, 0xe6, 0x30, 0x1c, 0x38, 0x0f, 0x03, 0xf1, + 0x10, 0x04, 0x30, 0x19, 0x1f, 0xfb, 0xfc, 0x05, 0xe2, 0xfe, 0x18, 0xf2, + 0x1c, 0xf2, 0xf5, 0x0e, 0xf2, 0x05, 0x1d, 0x28, 0x12, 0xf0, 0xf0, 0x0f, + 0x0a, 0x03, 0x1a, 0x1a, 0xf3, 0x08, 0x13, 0xef, 0xf5, 0x1c, 0x06, 0x00, + 0xee, 0x12, 0x1d, 0x03, 0x18, 0x06, 0x0a, 0x0e, 0xf0, 0xeb, 0xfa, 0x0d, + 0x08, 0xff, 0x06, 0x24, 0x0f, 0x03, 0x0a, 0x0f, 0x0e, 0xff, 0x08, 0x33, + 0xfc, 0x00, 0x0e, 0xfb, 0xfb, 0x05, 0x07, 0x19, 0xe8, 0xe7, 0x12, 0x11, + 0x15, 0xf7, 0x0c, 0x1a, 0xf6, 0x28, 0x08, 0xeb, 0xf2, 0x25, 0xee, 0x01, + 0x03, 0xec, 0xed, 0xfa, 0xf0, 0xf2, 0xef, 0xf1, 0x02, 0x23, 0xef, 0x01, + 0x41, 0xfa, 0xf4, 0xf4, 0x15, 0xf5, 0xf5, 0xf9, 0x28, 0xde, 0x20, 0xf6, + 0xc7, 0xde, 0x21, 0xe4, 0xfe, 0xec, 0x0d, 0x2c, 0xee, 0x24, 0x10, 0xf0, + 0x1d, 0x12, 0x0e, 0x2b, 0x06, 0xf8, 0xfd, 0x01, 0x08, 0xef, 0xfd, 0x0f, + 0xeb, 0xed, 0xe1, 0xdf, 0xf1, 0xe5, 0x16, 0xe3, 0x08, 0xfc, 0xf6, 0xf6, + 0xd8, 0xf0, 0x23, 0xfc, 0x2b, 0xf5, 0xff, 0xe7, 0xf4, 0xe9, 0x29, 0x09, + 0x2b, 0x0c, 0xff, 0x08, 0x0b, 0xed, 0x29, 0x14, 0x3c, 0xf5, 0xeb, 0x18, + 0xf6, 0x10, 0x22, 0xf9, 0x17, 0x23, 0x02, 0x0c, 0xf6, 0xfa, 0x2f, 0xfe, + 0x1e, 0xeb, 0xfd, 0x03, 0xf0, 0x07, 0x1c, 0x09, 0xfa, 0xe1, 0x0d, 0x0f, + 0x18, 0x03, 0xfe, 0xf0, 0xec, 0x0b, 0x10, 0x02, 0x14, 0x06, 0xef, 0xf7, + 0xea, 0x0b, 0x05, 0xfe, 0x1f, 0x06, 0x0e, 0x07, 0x00, 0xe1, 0x01, 0x01, + 0x07, 0x05, 0x09, 0xf7, 0xef, 0x15, 0xf7, 0x12, 0x05, 0x03, 0x04, 0x1d, + 0x04, 0x10, 0x12, 0x06, 0x05, 0x00, 0x08, 0x18, 0xd6, 0xf2, 0xfa, 0x07, + 0xf8, 0x12, 0x07, 0xfd, 0xdd, 0x00, 0x04, 0xfb, 0xf8, 0x09, 0xf3, 0x09, + 0xfb, 0xf0, 0xe8, 0x09, 0x27, 0xf5, 0xf8, 0x06, 0x01, 0x02, 0x0e, 0xf6, + 0x1f, 0xfa, 0x29, 0xf8, 0xd6, 0x01, 0x22, 0xf8, 0x1d, 0xe3, 0x1a, 0x39, + 0x0a, 0x0d, 0x19, 0xf5, 0x12, 0xfb, 0x1d, 0x2a, 0x03, 0xf6, 0x0c, 0xf2, + 0xfd, 0xec, 0x18, 0x13, 0xfe, 0x1a, 0xe8, 0xdd, 0x01, 0xf8, 0x30, 0x01, + 0xf8, 0xfe, 0xe4, 0xe7, 0xff, 0xeb, 0x23, 0xfa, 0x2c, 0xf0, 0xfc, 0xe7, + 0x0a, 0xf8, 0x18, 0x10, 0x23, 0x01, 0xfa, 0xe8, 0xf1, 0xfa, 0x1d, 0x0e, + 0x17, 0xe7, 0xe4, 0xf5, 0xf9, 0x0c, 0x17, 0x0c, 0x13, 0xe8, 0xe1, 0x17, + 0x19, 0x05, 0x0b, 0x0f, 0x23, 0xed, 0xff, 0xfe, 0xe0, 0x14, 0x16, 0x00, + 0x0d, 0x1c, 0x0b, 0xf5, 0xfb, 0x18, 0xee, 0xff, 0xff, 0xf3, 0x18, 0x0c, + 0x05, 0xfa, 0xf6, 0xfe, 0xfe, 0xf8, 0xf8, 0x09, 0xef, 0xf8, 0x0e, 0xf0, + 0x00, 0xf8, 0x0c, 0xf8, 0xf6, 0x07, 0x16, 0x11, 0xf8, 0xea, 0xff, 0xff, + 0x01, 0x20, 0x07, 0x08, 0xfd, 0x1c, 0xfc, 0x06, 0xed, 0x0d, 0x08, 0x15, + 0xf0, 0x25, 0x01, 0x1b, 0x00, 0x02, 0xfe, 0x01, 0x05, 0x01, 0xfd, 0xf1, + 0xe5, 0x0c, 0xe4, 0xe1, 0xf0, 0xfa, 0xee, 0x0e, 0x35, 0xee, 0x15, 0xef, + 0x0a, 0xf9, 0x01, 0xf5, 0x1f, 0x05, 0x1f, 0x0d, 0xe1, 0xf4, 0xff, 0xf5, + 0x23, 0x02, 0x18, 0x30, 0xfc, 0xf0, 0x0d, 0x04, 0x0d, 0x06, 0x29, 0x1d, + 0xf9, 0x08, 0x06, 0xe5, 0x13, 0xfd, 0x0d, 0x26, 0xef, 0x09, 0xdc, 0xf2, + 0x05, 0xdf, 0x0c, 0xf6, 0xf3, 0xd9, 0xf8, 0x08, 0xef, 0xeb, 0x0f, 0xf9, + 0x3a, 0x03, 0xff, 0xe0, 0xf7, 0xf0, 0x15, 0x12, 0x41, 0x0b, 0xf1, 0x04, + 0x04, 0xe2, 0x0e, 0x0b, 0x2c, 0x03, 0xea, 0x02, 0xfb, 0xe7, 0x08, 0xe9, + 0x22, 0xf3, 0xf2, 0x1c, 0xfa, 0xf3, 0x11, 0x04, 0x1f, 0xf5, 0x02, 0x0f, + 0x1a, 0x1f, 0x24, 0x0b, 0x06, 0x1f, 0xf3, 0x06, 0x00, 0x02, 0xe8, 0xf6, + 0xf4, 0xe8, 0x07, 0x2e, 0xfb, 0xf8, 0x10, 0x09, 0xf0, 0x0e, 0xff, 0xfe, + 0x1c, 0x14, 0x17, 0x06, 0xe2, 0xf1, 0xfa, 0x01, 0x11, 0x13, 0x12, 0x29, + 0xf1, 0x0f, 0x1f, 0xfa, 0xfd, 0xfd, 0x02, 0x07, 0x0e, 0xfb, 0x0e, 0x04, + 0x01, 0x01, 0xed, 0xfe, 0xde, 0xfd, 0x08, 0xef, 0xf6, 0x0a, 0xff, 0x0f, + 0xe7, 0xf2, 0x0f, 0x02, 0xea, 0x10, 0xf9, 0xec, 0xfd, 0x09, 0xea, 0x1f, + 0x46, 0xdd, 0xe2, 0xf7, 0x08, 0xf5, 0xf7, 0xe9, 0x33, 0xfb, 0x2f, 0xf6, + 0xb5, 0x1d, 0x15, 0xeb, 0x11, 0xf7, 0x2a, 0x2e, 0x08, 0x1d, 0xf4, 0xfb, + 0x15, 0xfa, 0x22, 0x34, 0xff, 0x06, 0xf6, 0xfd, 0xfa, 0xf9, 0x03, 0xf5, + 0xf4, 0xf4, 0xd5, 0xea, 0x01, 0x08, 0x22, 0xf1, 0xf2, 0x06, 0xd1, 0xe5, + 0x0c, 0xef, 0x12, 0x03, 0x08, 0x02, 0xf7, 0x05, 0x1b, 0x07, 0x39, 0x34, + 0x21, 0xe2, 0xe3, 0x0b, 0x0c, 0xf6, 0x29, 0xf7, 0x24, 0x0a, 0xfc, 0xff, + 0x1a, 0xfd, 0x05, 0xff, 0xff, 0x0e, 0x0a, 0x1a, 0x09, 0xfb, 0x15, 0x04, + 0x03, 0xf7, 0xfe, 0x00, 0xfc, 0xfb, 0x11, 0xfa, 0x1d, 0x0e, 0x06, 0xed, + 0xfc, 0x23, 0xd8, 0xf2, 0x04, 0xe5, 0x0f, 0x16, 0x29, 0xfe, 0xf5, 0xec, + 0xe2, 0x0e, 0xeb, 0x09, 0x1d, 0x11, 0x05, 0x11, 0xe4, 0x29, 0x12, 0x02, + 0x12, 0x19, 0x0e, 0x1a, 0xee, 0xf9, 0x05, 0x09, 0xf5, 0xfd, 0x05, 0x04, + 0xe4, 0xf1, 0x17, 0x01, 0xf2, 0xfe, 0x0b, 0xf4, 0x0d, 0x04, 0x06, 0xfe, + 0xff, 0xec, 0xe9, 0x00, 0xff, 0x03, 0x03, 0xfd, 0xf1, 0x15, 0xfc, 0xf3, + 0xff, 0xfe, 0x09, 0xee, 0x3c, 0x01, 0xec, 0x02, 0xf0, 0xf6, 0x20, 0xeb, + 0x16, 0x07, 0x32, 0xf3, 0xce, 0xf0, 0x02, 0xd4, 0x11, 0xe6, 0x28, 0x0e, + 0xe3, 0x21, 0xee, 0xce, 0x1e, 0xd9, 0x23, 0x26, 0x06, 0xfa, 0xf9, 0xf1, + 0x01, 0xe6, 0x0b, 0x07, 0xdc, 0x21, 0xbc, 0xe3, 0xef, 0xf8, 0x12, 0xfc, + 0xe6, 0xfe, 0xf5, 0xd4, 0x15, 0x0a, 0x00, 0x13, 0xfc, 0xec, 0xf3, 0xd6, + 0x1a, 0xe3, 0x21, 0x36, 0x2a, 0x03, 0xe9, 0xe3, 0xff, 0x00, 0x13, 0x1c, + 0x0e, 0x20, 0xe5, 0xf5, 0x24, 0x0b, 0x20, 0x14, 0x13, 0xf8, 0x04, 0x1b, + 0x2f, 0x0a, 0x15, 0x00, 0xf4, 0x1a, 0x11, 0x0d, 0x03, 0x18, 0x0f, 0x18, + 0x04, 0x1f, 0xfb, 0xf2, 0x1f, 0x15, 0x03, 0xfb, 0x0b, 0x17, 0xfb, 0x0b, + 0x1b, 0x1f, 0xf4, 0x07, 0xf9, 0xf9, 0xf8, 0xf4, 0x14, 0x0f, 0xf6, 0xfe, + 0xdd, 0x0b, 0xff, 0x01, 0x18, 0x04, 0x1b, 0x0a, 0xed, 0xe7, 0xf9, 0x16, + 0x02, 0x01, 0x00, 0xf7, 0xf1, 0x07, 0xf0, 0x06, 0xf8, 0x0b, 0x02, 0xf3, + 0xff, 0x20, 0xfd, 0x01, 0x04, 0xf5, 0xd9, 0xf4, 0xf4, 0xf2, 0xe8, 0xff, + 0x04, 0x00, 0xf0, 0xe2, 0xfe, 0xed, 0x1b, 0xef, 0x20, 0xfa, 0xfb, 0xf4, + 0x02, 0x18, 0x07, 0xfb, 0xef, 0xe4, 0x08, 0x0d, 0xe1, 0x0e, 0x25, 0xc6, + 0xfd, 0x0c, 0x1c, 0x0b, 0xf0, 0x01, 0x1c, 0xd4, 0x11, 0xf5, 0x1b, 0x09, + 0xfb, 0xda, 0x13, 0xe3, 0xf9, 0x10, 0x14, 0xf0, 0xf0, 0xfd, 0x1f, 0xcf, + 0xf4, 0xe4, 0xfb, 0x0e, 0x0a, 0x11, 0xed, 0xdc, 0xfc, 0xe6, 0xf7, 0xfc, + 0x13, 0xe1, 0x0b, 0xe4, 0x04, 0x11, 0xee, 0x21, 0x14, 0xe1, 0x07, 0xe4, + 0xfb, 0x08, 0x03, 0x2b, 0x27, 0xf6, 0x0d, 0x02, 0x1b, 0x09, 0x09, 0xf8, + 0x14, 0x19, 0x0f, 0x0b, 0x01, 0x10, 0x09, 0x12, 0x03, 0xf5, 0x18, 0xf3, + 0xfb, 0xf5, 0x02, 0x0e, 0x0d, 0x00, 0x07, 0xfc, 0x18, 0x25, 0x0b, 0xf0, + 0xf9, 0xe6, 0x08, 0x01, 0x24, 0x14, 0xfa, 0xed, 0xe5, 0x1f, 0x09, 0xfe, + 0x08, 0xee, 0x1a, 0x1a, 0x05, 0x00, 0xff, 0x0c, 0xfe, 0xf9, 0x11, 0x11, + 0xea, 0xfe, 0x08, 0xf9, 0xf0, 0xe4, 0x01, 0x0d, 0xf1, 0x00, 0x0b, 0xea, + 0x19, 0xea, 0xf3, 0xf8, 0x08, 0x12, 0x1c, 0x1f, 0xfb, 0xef, 0xf0, 0xf2, + 0x14, 0xe1, 0x03, 0xfa, 0xf9, 0xda, 0xe9, 0xfc, 0xf3, 0xff, 0x12, 0x04, + 0xf7, 0xfc, 0x17, 0x0f, 0xfc, 0x29, 0x03, 0xe5, 0xf2, 0xee, 0x1e, 0xfa, + 0x04, 0xed, 0x25, 0xf4, 0xe1, 0x15, 0x10, 0x1e, 0xef, 0x1c, 0x04, 0xde, + 0xe5, 0x08, 0x21, 0xfd, 0xfd, 0xea, 0x03, 0xca, 0xda, 0x26, 0x00, 0x0a, + 0xfd, 0x05, 0xf0, 0xd4, 0xe1, 0x1a, 0xe4, 0xf5, 0x07, 0xe7, 0xfa, 0xdf, + 0xd4, 0x03, 0xf0, 0x10, 0x15, 0x0c, 0xf4, 0xed, 0xe3, 0xfb, 0x0f, 0x1e, + 0x16, 0x09, 0x00, 0xec, 0xea, 0x13, 0x16, 0x0b, 0x01, 0xfb, 0xff, 0x00, + 0xfb, 0x07, 0x13, 0x08, 0xf4, 0xe4, 0x12, 0x00, 0xfb, 0xfa, 0xfc, 0x08, + 0xeb, 0x19, 0x02, 0x1c, 0xe8, 0x26, 0xf3, 0x10, 0x09, 0x0f, 0x19, 0x02, + 0xfb, 0xec, 0xf7, 0xe2, 0xfb, 0xfa, 0x11, 0xf3, 0x0b, 0x08, 0xff, 0xd9, + 0xf8, 0x12, 0x18, 0x06, 0x07, 0x22, 0xff, 0x19, 0xf5, 0x0b, 0x0a, 0x13, + 0xf2, 0xfa, 0x02, 0x21, 0xeb, 0x11, 0x17, 0x17, 0xec, 0xe1, 0x0e, 0xf7, + 0xe8, 0xd8, 0x0e, 0x01, 0xf1, 0xed, 0xed, 0xf0, 0x09, 0xf7, 0xe7, 0xfd, + 0xf0, 0xf9, 0xdb, 0xee, 0xdc, 0xfb, 0xf8, 0x0a, 0xf5, 0x0b, 0xd4, 0xd7, + 0x08, 0x06, 0x18, 0x06, 0x0c, 0x13, 0xfd, 0x09, 0x13, 0x26, 0x12, 0xf4, + 0xef, 0x00, 0xf5, 0x28, 0x18, 0xfe, 0x04, 0x0e, 0x21, 0x1a, 0x0a, 0x1e, + 0x09, 0xf0, 0x0d, 0x0f, 0xec, 0xf3, 0x17, 0x22, 0x00, 0xec, 0x0e, 0x01, + 0xe9, 0x08, 0x09, 0xf2, 0xf2, 0x08, 0xf0, 0x0b, 0xd9, 0x09, 0x14, 0xf5, + 0xf6, 0x04, 0x19, 0xf4, 0x11, 0xe9, 0xf2, 0x0d, 0x20, 0x17, 0x0a, 0x05, + 0x0c, 0x04, 0x01, 0xfd, 0xf4, 0xfb, 0x1b, 0x0c, 0xf2, 0x0b, 0xff, 0xfe, + 0x01, 0xd8, 0xfa, 0x0e, 0xf5, 0x14, 0xf9, 0x01, 0x04, 0xf8, 0xfa, 0x02, + 0xe8, 0xf9, 0xf9, 0xea, 0xf1, 0x07, 0xff, 0x1e, 0x01, 0x0b, 0xf7, 0x0a, + 0xf7, 0x0c, 0xfd, 0xec, 0xf3, 0x05, 0xf8, 0xda, 0x0b, 0x15, 0xf6, 0xee, + 0xf9, 0x10, 0xfa, 0xfe, 0x08, 0xf0, 0xe6, 0xec, 0x05, 0xff, 0x15, 0x19, + 0x1f, 0x11, 0xfc, 0x09, 0x08, 0x01, 0x06, 0xfe, 0x04, 0x08, 0xfb, 0xfb, + 0x08, 0xf4, 0xf6, 0x28, 0x10, 0xf9, 0x28, 0x0b, 0xf8, 0x0d, 0x01, 0x00, + 0xff, 0x02, 0x05, 0x08, 0xea, 0xe9, 0xf4, 0xf6, 0x01, 0xea, 0xdf, 0x1f, + 0xfe, 0x0a, 0xf9, 0xf7, 0x0c, 0x1b, 0x06, 0xed, 0xf6, 0xf2, 0x03, 0x03, + 0xfd, 0x04, 0xf5, 0x10, 0x0a, 0x0b, 0xf4, 0xf8, 0xf1, 0xe7, 0x05, 0xfe, + 0xe7, 0x0b, 0xf1, 0xec, 0xf4, 0xec, 0x06, 0xee, 0xde, 0x05, 0x1b, 0xfe, + 0x13, 0xf3, 0xd9, 0xea, 0x04, 0x10, 0x05, 0xed, 0x15, 0x02, 0x0b, 0x10, + 0xfa, 0x02, 0x05, 0x0b, 0x02, 0x07, 0xfc, 0xf5, 0x15, 0x14, 0x05, 0xf7, + 0x0c, 0xfe, 0xf6, 0xf4, 0xfa, 0x06, 0xfc, 0x13, 0xdc, 0xe4, 0x09, 0xfa, + 0x02, 0x23, 0xec, 0x06, 0x11, 0x13, 0xf8, 0xfa, 0x27, 0x28, 0x0b, 0x23, + 0xec, 0xf1, 0x09, 0x17, 0x0f, 0x13, 0xff, 0xf2, 0xfc, 0x0a, 0xf5, 0x0d, + 0x03, 0x26, 0x01, 0x0f, 0xfe, 0xf1, 0xfb, 0xe6, 0xf0, 0x02, 0xf2, 0xff, + 0x02, 0x11, 0xff, 0xfd, 0x1c, 0x02, 0x0b, 0xf6, 0x14, 0x0c, 0x0b, 0x21, + 0x28, 0xf0, 0x11, 0x05, 0x06, 0xed, 0xf9, 0x0a, 0xf2, 0xef, 0xf8, 0xf1, + 0xfe, 0x0d, 0xf9, 0xf7, 0xea, 0x00, 0x08, 0xdb, 0x02, 0x0f, 0xfe, 0x04, + 0xef, 0x20, 0x16, 0x01, 0xe8, 0xed, 0xe4, 0x22, 0xf6, 0x19, 0x00, 0x04, + 0x01, 0x13, 0xeb, 0x0d, 0xec, 0x01, 0x08, 0x05, 0x0c, 0x0e, 0xfe, 0x02, + 0x12, 0xf7, 0x27, 0xf9, 0xfd, 0x18, 0xfe, 0x24, 0xf7, 0x13, 0xed, 0x1e, + 0x09, 0xff, 0xd8, 0xf4, 0x12, 0xf8, 0x04, 0x0c, 0x1c, 0x11, 0xfd, 0x17, + 0x1d, 0x01, 0x13, 0xee, 0x11, 0xf3, 0xf8, 0x06, 0xf6, 0x16, 0xfe, 0x15, + 0x16, 0xdc, 0x1f, 0x00, 0x25, 0xee, 0xff, 0xf7, 0xf6, 0x02, 0xdd, 0x15, + 0xf1, 0x14, 0x08, 0xe8, 0xe5, 0x21, 0xea, 0xf0, 0x1a, 0x07, 0xea, 0x08, + 0xea, 0xe4, 0x1e, 0x00, 0x13, 0x17, 0xec, 0x11, 0xd6, 0x11, 0x18, 0x17, + 0x04, 0x15, 0x03, 0x3a, 0xd6, 0x02, 0x07, 0x04, 0xe6, 0xe5, 0xfe, 0x0e, + 0xff, 0xed, 0xfc, 0xfb, 0xff, 0x1c, 0x06, 0x0a, 0xfb, 0xf9, 0xea, 0x1a, + 0x21, 0xf5, 0x04, 0x06, 0x0a, 0xe3, 0x16, 0xea, 0x04, 0xe2, 0xf9, 0xf9, + 0xe6, 0xfb, 0x0f, 0xfc, 0x06, 0xfb, 0x10, 0x07, 0x07, 0x13, 0x07, 0xfc, + 0x16, 0xef, 0x07, 0xdc, 0x12, 0x1f, 0x08, 0xf4, 0xe9, 0x14, 0x06, 0xf7, + 0xf1, 0x0c, 0x01, 0x0c, 0xe6, 0x04, 0xf3, 0xf2, 0xe5, 0xf3, 0xef, 0x1d, + 0xf6, 0x20, 0x07, 0xfe, 0xf4, 0x05, 0xee, 0x10, 0xfd, 0x0e, 0x0b, 0x02, + 0x0d, 0xd8, 0x07, 0xfb, 0x26, 0x0a, 0x1c, 0x21, 0x06, 0x1f, 0xf4, 0x06, + 0x37, 0x18, 0xfa, 0x16, 0x1e, 0x24, 0xfb, 0xf0, 0x12, 0xf9, 0x02, 0x09, + 0x17, 0x16, 0xf3, 0xf9, 0x17, 0xf2, 0x02, 0x0a, 0x2d, 0xe7, 0xe3, 0x25, + 0xf0, 0xf9, 0x0f, 0xdd, 0x15, 0xe6, 0x04, 0xfc, 0xf1, 0x17, 0x0a, 0xea, + 0x24, 0x07, 0xf1, 0x11, 0x13, 0x29, 0xf4, 0xc5, 0xfb, 0x07, 0xef, 0x13, + 0x0b, 0xe1, 0xf1, 0xeb, 0xf8, 0x1b, 0x09, 0x08, 0x1f, 0x15, 0xf2, 0x05, + 0x02, 0xdd, 0x09, 0x0f, 0x16, 0x10, 0x01, 0x30, 0xf2, 0xe0, 0x27, 0xfe, + 0xf1, 0x0e, 0x0e, 0x07, 0xe6, 0x07, 0x0b, 0x18, 0xfe, 0x0f, 0x01, 0x07, + 0xf4, 0x07, 0x10, 0xe7, 0xfb, 0xf3, 0xf7, 0x0b, 0xf9, 0x15, 0x18, 0x25, + 0x0c, 0x14, 0x02, 0x08, 0x0a, 0x0f, 0x10, 0xec, 0xee, 0x1a, 0x03, 0x14, + 0x0f, 0xfa, 0x25, 0xff, 0x18, 0x0d, 0x0b, 0xea, 0x1f, 0x28, 0x10, 0x0c, + 0xe7, 0xee, 0xf7, 0xfa, 0x03, 0x15, 0x0c, 0x1d, 0x01, 0x00, 0x12, 0xee, + 0x01, 0xf1, 0xf8, 0x0b, 0xf3, 0xfd, 0x04, 0xf8, 0x02, 0x1e, 0x0e, 0xf3, + 0x02, 0x10, 0xfd, 0x07, 0x0b, 0x09, 0x03, 0x10, 0x3e, 0x08, 0x0e, 0x0c, + 0xf4, 0xe7, 0xfd, 0x1c, 0x27, 0x1a, 0xed, 0xe1, 0x08, 0xdc, 0xd9, 0xf1, + 0x1e, 0x07, 0x12, 0xf1, 0x10, 0xfb, 0xc8, 0x08, 0x0f, 0x03, 0x1d, 0xdc, + 0x23, 0x04, 0xf9, 0x0a, 0xff, 0x08, 0x0e, 0xc9, 0x39, 0x0a, 0x01, 0x07, + 0xec, 0xe0, 0x05, 0xe8, 0x14, 0xd8, 0xe1, 0xfa, 0xd6, 0xf8, 0xed, 0xdb, + 0xff, 0x1d, 0xf5, 0x17, 0x0f, 0x1c, 0xdc, 0xed, 0xff, 0xff, 0x04, 0x13, + 0xf5, 0xe7, 0xd2, 0x12, 0xdb, 0xe1, 0x13, 0x11, 0x23, 0x0e, 0xf9, 0x31, + 0xdc, 0xef, 0x07, 0x0a, 0x20, 0xf2, 0xf9, 0x13, 0xff, 0x1c, 0x2a, 0xdf, + 0xdb, 0xe7, 0x11, 0xf2, 0xfd, 0xfb, 0x28, 0x00, 0x15, 0x03, 0x02, 0x20, + 0x07, 0xf7, 0x19, 0x13, 0x13, 0xf6, 0x09, 0xfe, 0xfd, 0x20, 0x14, 0xf5, + 0xf5, 0xfc, 0x14, 0x0e, 0x17, 0xfe, 0x15, 0x04, 0xf9, 0xf6, 0x1d, 0xf6, + 0x1b, 0xe4, 0xee, 0xfd, 0x00, 0xe9, 0xee, 0xce, 0x0f, 0x20, 0x05, 0x02, + 0x0d, 0x06, 0x05, 0xf8, 0xef, 0xdf, 0x16, 0x17, 0xe6, 0xf1, 0x10, 0xf3, + 0x06, 0x04, 0xdb, 0xfb, 0xe7, 0xf8, 0x02, 0x11, 0xff, 0x0d, 0x0a, 0xfa, + 0x27, 0x0a, 0xfc, 0xe8, 0x11, 0x17, 0xf0, 0x0d, 0x0d, 0xee, 0xdf, 0xdd, + 0xf1, 0x15, 0xd6, 0xf7, 0x00, 0xef, 0x2e, 0xe6, 0x24, 0xfd, 0xd5, 0x04, + 0xf0, 0x08, 0x08, 0xed, 0x22, 0x07, 0xe1, 0x09, 0xd0, 0x0b, 0x18, 0xe6, + 0x3f, 0x0a, 0xe5, 0xe2, 0xf9, 0x08, 0x02, 0xd6, 0x13, 0x15, 0xbd, 0x00, + 0x0e, 0xf8, 0xe2, 0xca, 0xec, 0x0e, 0xe6, 0xef, 0x15, 0x11, 0xcb, 0xdf, + 0xf9, 0x03, 0x22, 0x10, 0xfb, 0xf9, 0xe5, 0x08, 0xe1, 0x11, 0x10, 0xfc, + 0xfa, 0x00, 0xf8, 0x30, 0xe5, 0x08, 0x14, 0xe8, 0x12, 0xe2, 0x04, 0x19, + 0x0b, 0xfa, 0x33, 0xf3, 0xec, 0xfe, 0xf8, 0x25, 0xf8, 0x21, 0x28, 0xef, + 0x00, 0xde, 0xff, 0x2b, 0x03, 0xfc, 0x10, 0x0c, 0xcf, 0xfd, 0x19, 0x0a, + 0x0c, 0xf2, 0xf7, 0x0c, 0xfd, 0x02, 0x1c, 0xdf, 0x26, 0x0d, 0xf0, 0x0b, + 0xce, 0x15, 0xfb, 0xec, 0x27, 0xf6, 0xf9, 0xe5, 0xe2, 0xfb, 0xfd, 0xd8, + 0x28, 0xec, 0xe9, 0xf2, 0xca, 0x09, 0x02, 0x06, 0x0c, 0xfa, 0x05, 0x01, + 0xd5, 0x0a, 0x02, 0xfb, 0x04, 0x17, 0xdd, 0xfe, 0xeb, 0xf1, 0x09, 0x10, + 0x12, 0xff, 0x00, 0xe0, 0x26, 0xf7, 0xed, 0xf4, 0x00, 0xf2, 0xfa, 0x07, + 0x02, 0xf5, 0x06, 0xe8, 0x03, 0xfd, 0xdc, 0xf2, 0xc2, 0xff, 0x0b, 0xd6, + 0x25, 0x04, 0xe9, 0xf0, 0xd9, 0x08, 0x09, 0xc5, 0x23, 0x12, 0xf6, 0x13, + 0x11, 0xf3, 0x18, 0xf0, 0x34, 0xfe, 0xfe, 0xed, 0xea, 0x02, 0x17, 0xdc, + 0x1b, 0x1b, 0xea, 0xfe, 0xea, 0xfe, 0xf2, 0xc4, 0xfd, 0x04, 0xe9, 0x0d, + 0x0d, 0x09, 0xca, 0xd4, 0xe1, 0x04, 0x1e, 0xff, 0x0f, 0xef, 0xd6, 0x0f, + 0xd5, 0xf8, 0x26, 0xd6, 0x33, 0xe8, 0xf5, 0x3b, 0xf1, 0xe8, 0x39, 0xe8, + 0x08, 0xe5, 0x01, 0x02, 0x04, 0xf6, 0x19, 0x0a, 0xd0, 0xeb, 0x0b, 0x15, + 0xf7, 0x0e, 0x23, 0xf6, 0xf4, 0xd8, 0xf4, 0x17, 0x23, 0x25, 0x14, 0x01, + 0xd7, 0xfd, 0xf9, 0x1f, 0x1b, 0x11, 0x0a, 0x18, 0xf5, 0xf5, 0x0f, 0xe0, + 0x2e, 0x01, 0xe5, 0xdb, 0xe2, 0xf2, 0x14, 0xfa, 0x2a, 0x00, 0xe2, 0xea, + 0xfd, 0x0e, 0xfc, 0xc1, 0x35, 0x08, 0xf6, 0xf9, 0xec, 0x00, 0x06, 0x00, + 0x0b, 0xf6, 0x01, 0xfe, 0xea, 0x0b, 0x08, 0x05, 0xe4, 0xea, 0xd7, 0xfd, + 0xee, 0xf3, 0x0c, 0x0c, 0x0d, 0x02, 0xfd, 0xee, 0x17, 0x10, 0x13, 0xfd, + 0x07, 0x03, 0xf8, 0x0c, 0xd4, 0xed, 0xfe, 0x07, 0xf4, 0xee, 0xf4, 0x03, + 0xc2, 0x18, 0x2c, 0xd1, 0x33, 0xd8, 0xdb, 0xfa, 0xed, 0x10, 0x1c, 0xe3, + 0x37, 0x0a, 0xea, 0xfe, 0xf6, 0xef, 0x20, 0xed, 0x32, 0xf7, 0xf5, 0xf3, + 0xca, 0xfd, 0x0a, 0xcf, 0x0d, 0x10, 0xde, 0x07, 0x18, 0x10, 0xf0, 0xd6, + 0x0c, 0x04, 0xeb, 0x1a, 0xf9, 0x08, 0xc4, 0xcb, 0xe4, 0x0b, 0x19, 0xfc, + 0x29, 0xf6, 0xec, 0x07, 0xf3, 0xed, 0x2b, 0xe9, 0xfa, 0x02, 0xec, 0x2b, + 0xf0, 0xf2, 0x2d, 0xe8, 0xed, 0x00, 0x12, 0x13, 0xed, 0x1a, 0x3d, 0xf0, + 0x05, 0x04, 0xfc, 0x13, 0x10, 0x01, 0x40, 0xf2, 0x06, 0x02, 0xf9, 0x22, + 0x24, 0xff, 0x18, 0x00, 0xeb, 0xe8, 0x14, 0xf9, 0x25, 0xe0, 0xff, 0x03, + 0xe5, 0xfd, 0x08, 0xea, 0x2e, 0x0b, 0x05, 0xe7, 0xde, 0xe4, 0xf5, 0xea, + 0x3a, 0xf4, 0xf4, 0xe7, 0xed, 0xec, 0xf8, 0xee, 0x30, 0x0a, 0xdb, 0x05, + 0xf7, 0x16, 0xff, 0xf7, 0xfa, 0x1f, 0xef, 0xe4, 0xce, 0xf8, 0x13, 0x04, + 0xf9, 0x01, 0xe1, 0x03, 0xf9, 0xf9, 0x08, 0x04, 0xfa, 0xe4, 0xe7, 0xf7, + 0x28, 0xfd, 0xfd, 0x00, 0xfc, 0xfb, 0xef, 0x0a, 0xec, 0x0c, 0x0a, 0xd2, + 0x05, 0xfb, 0xcd, 0xfb, 0x9d, 0xea, 0x1c, 0xe5, 0x25, 0xe8, 0xea, 0x0b, + 0xf0, 0xf3, 0x0d, 0xab, 0x49, 0x0e, 0xeb, 0x00, 0xe2, 0x03, 0x29, 0xe0, + 0x3d, 0x06, 0xf7, 0xf8, 0xcf, 0x0c, 0x1a, 0xd6, 0x1f, 0xef, 0xfd, 0xff, + 0xef, 0x0c, 0xdb, 0xe0, 0x20, 0x06, 0xdf, 0x1a, 0xe7, 0xfc, 0xb2, 0xd1, + 0xdf, 0x13, 0x07, 0x1f, 0x0c, 0xf7, 0xde, 0x0a, 0xdb, 0xdf, 0x1a, 0xf5, + 0x29, 0x0d, 0xeb, 0x2c, 0xcf, 0x0e, 0x26, 0xfe, 0xef, 0x04, 0xf5, 0x14, + 0x09, 0x13, 0x34, 0xff, 0xfe, 0x0e, 0x06, 0x0e, 0x10, 0xf9, 0x2a, 0x0b, + 0xe6, 0xfe, 0xf1, 0x1a, 0x36, 0x29, 0x29, 0x05, 0x05, 0xd8, 0x14, 0x12, + 0x26, 0x0b, 0x18, 0xff, 0xd7, 0xdf, 0x0f, 0xed, 0x31, 0xf7, 0xfc, 0xec, + 0x0b, 0xef, 0x0c, 0xd2, 0x30, 0xf9, 0x04, 0xfe, 0xef, 0xe4, 0xfb, 0xd1, + 0x32, 0xe5, 0xee, 0xf0, 0x0c, 0xe6, 0x13, 0xed, 0x1e, 0x0b, 0xe4, 0xe0, + 0xfa, 0xf4, 0x14, 0xf4, 0x18, 0xf7, 0xd9, 0xf6, 0xed, 0xea, 0xfc, 0x06, + 0xfc, 0xf5, 0xed, 0xeb, 0x05, 0x03, 0x1b, 0x0b, 0xff, 0x0b, 0xef, 0x01, + 0xf1, 0x16, 0x05, 0x00, 0xee, 0x0a, 0xdb, 0x10, 0xb4, 0x14, 0x0f, 0xe1, + 0x1c, 0xfd, 0xf0, 0xf8, 0xc3, 0x11, 0x17, 0xba, 0x47, 0x15, 0xe6, 0x01, + 0xea, 0xf1, 0x0c, 0x08, 0x4a, 0x15, 0xf0, 0xf7, 0xea, 0x00, 0xf5, 0xd4, + 0xf1, 0xff, 0xe0, 0x0c, 0xf4, 0x17, 0xd8, 0xea, 0x03, 0xff, 0xd5, 0x18, + 0xfb, 0x07, 0xc7, 0xc9, 0xdd, 0xf3, 0x15, 0x0d, 0x22, 0xea, 0xdb, 0x0a, + 0xd6, 0x09, 0x1d, 0xe5, 0x2d, 0x04, 0xfc, 0x35, 0xc6, 0x0e, 0x33, 0xf1, + 0xd7, 0xea, 0x01, 0x1b, 0x0e, 0x01, 0x2a, 0xff, 0xef, 0xf1, 0xf7, 0x0f, + 0xff, 0x00, 0x3b, 0xe8, 0x0a, 0xff, 0xf4, 0x0d, 0x1f, 0x04, 0x17, 0xf7, + 0xdf, 0xec, 0x12, 0x26, 0x36, 0x07, 0x0c, 0x06, 0xe7, 0xd6, 0x13, 0xe3, + 0x30, 0x09, 0x00, 0xf5, 0xe0, 0xf3, 0x11, 0xe2, 0x38, 0x0d, 0xf6, 0x05, + 0xec, 0x05, 0x00, 0xe5, 0x24, 0xef, 0xfe, 0xf8, 0x00, 0xd8, 0x18, 0xf1, + 0x26, 0x0b, 0xf2, 0xfc, 0xe0, 0xe4, 0x06, 0x0b, 0x1a, 0x05, 0xc6, 0xf6, + 0xe8, 0xde, 0xfe, 0x0c, 0x03, 0x09, 0xfe, 0xe2, 0x18, 0x1b, 0xfb, 0xf7, + 0x06, 0xf1, 0xfe, 0xf6, 0xef, 0x1b, 0x07, 0x0d, 0x01, 0x0a, 0xed, 0xf0, + 0xad, 0x1a, 0x17, 0xd6, 0x37, 0xfd, 0xd8, 0xec, 0xca, 0xf1, 0x15, 0xc4, + 0x33, 0xf1, 0xed, 0xf0, 0xe9, 0x15, 0x0d, 0xf2, 0x36, 0xde, 0xfd, 0x0e, + 0xfb, 0x10, 0x0f, 0xf6, 0xf9, 0x0c, 0xea, 0xf0, 0xe5, 0x0b, 0xee, 0xc1, + 0x10, 0xf4, 0xe8, 0x1f, 0xee, 0x00, 0xd0, 0xe4, 0xe7, 0x13, 0x07, 0x27, + 0x12, 0xea, 0xea, 0x0f, 0xea, 0xf4, 0x14, 0xee, 0xfe, 0x09, 0xfb, 0x31, + 0xdb, 0x1b, 0x1c, 0xe7, 0xef, 0xf5, 0xf7, 0x1a, 0x06, 0x01, 0x2c, 0xed, + 0xfb, 0x04, 0xfa, 0x07, 0x19, 0xec, 0x2b, 0x0d, 0xfc, 0xd8, 0xfc, 0x0f, + 0x1f, 0xfc, 0x2d, 0xf3, 0xc9, 0xda, 0x0a, 0xfe, 0x29, 0x00, 0xfa, 0x09, + 0xe8, 0xf6, 0x21, 0xf3, 0x4a, 0x1a, 0xf8, 0x00, 0xe7, 0xf0, 0x21, 0x01, + 0x22, 0xf3, 0x00, 0xe9, 0x06, 0xe3, 0x15, 0xd7, 0x3d, 0x0c, 0x07, 0xf1, + 0xf3, 0xec, 0x17, 0xdf, 0x29, 0x1b, 0xfd, 0xfe, 0xeb, 0xed, 0x17, 0xf6, + 0x23, 0x0a, 0xea, 0xee, 0xf9, 0xf3, 0x0f, 0x0c, 0xf8, 0xf5, 0xed, 0xe8, + 0x1c, 0x14, 0x07, 0x17, 0x0b, 0x0d, 0xed, 0xf7, 0xed, 0x10, 0x07, 0xd5, + 0xf2, 0x09, 0xd6, 0xf7, 0xb5, 0xf6, 0x19, 0xc9, 0x25, 0x15, 0xe8, 0xf5, + 0xc4, 0xf9, 0x2a, 0xb0, 0x39, 0x0e, 0x02, 0x11, 0xf0, 0xf7, 0x1d, 0xeb, + 0x39, 0x10, 0x02, 0x15, 0xe0, 0x08, 0x01, 0xee, 0x1c, 0x1e, 0x08, 0x04, + 0xf2, 0x02, 0xe8, 0xda, 0xfa, 0xfb, 0xe0, 0xfe, 0x05, 0x02, 0xd3, 0xca, + 0xf4, 0xec, 0x10, 0x16, 0x05, 0x0d, 0xd7, 0x09, 0xdc, 0xf6, 0x1e, 0xf8, + 0x10, 0xed, 0xf7, 0x27, 0xf5, 0x08, 0x28, 0xee, 0xec, 0xe0, 0xf8, 0x17, + 0xfb, 0x23, 0x2e, 0xf1, 0xfa, 0xf5, 0xfc, 0x1a, 0x10, 0xf7, 0x32, 0xfb, + 0xfb, 0xe8, 0xf1, 0x03, 0x24, 0xeb, 0x25, 0xf9, 0xca, 0xf1, 0xfe, 0x01, + 0x2e, 0x07, 0x18, 0x03, 0xe5, 0xea, 0x10, 0xfa, 0x3b, 0x07, 0x0f, 0x11, + 0x04, 0xf7, 0x1d, 0xf1, 0x24, 0xd9, 0x08, 0xef, 0x02, 0xdd, 0x07, 0xc8, + 0x2c, 0x0d, 0x06, 0xec, 0x17, 0xda, 0x21, 0xdf, 0x34, 0xd9, 0xfb, 0xf2, + 0xf4, 0xec, 0x0e, 0x0a, 0x0f, 0x0f, 0xdb, 0xf0, 0xfb, 0xe6, 0x0f, 0x00, + 0x04, 0xf9, 0x01, 0x05, 0x05, 0xfe, 0x08, 0xf3, 0x0e, 0xf2, 0xfb, 0x01, + 0xfd, 0x18, 0x1d, 0xf6, 0xee, 0x06, 0xcf, 0xfc, 0xae, 0x27, 0x21, 0xd2, + 0x33, 0x03, 0xe0, 0xe0, 0xc9, 0xfb, 0x3a, 0xbd, 0x4d, 0x04, 0xe8, 0xf5, + 0xe6, 0xeb, 0x19, 0xf2, 0x4b, 0x1d, 0xfc, 0xf7, 0xd9, 0xff, 0xfe, 0xea, + 0x0f, 0x04, 0x0e, 0x00, 0xed, 0x19, 0xe9, 0xe9, 0xff, 0x11, 0xef, 0x14, + 0x01, 0x17, 0xbc, 0xb5, 0xef, 0x0c, 0x22, 0x27, 0x0f, 0x01, 0xd4, 0x03, + 0xce, 0x01, 0x25, 0xff, 0xf9, 0xf0, 0x0a, 0x1c, 0xe5, 0x0f, 0x1c, 0xee, + 0xf4, 0xf1, 0xf4, 0x0c, 0x00, 0x08, 0x1c, 0xf4, 0xd5, 0xf1, 0xfc, 0x1f, + 0x11, 0x00, 0x18, 0x03, 0xf7, 0xe4, 0xff, 0x07, 0x09, 0x1a, 0x18, 0xff, + 0xea, 0xec, 0xfd, 0x13, 0x2b, 0xf8, 0x0c, 0xfa, 0xdf, 0xf6, 0x11, 0xda, + 0x2a, 0xdc, 0xfc, 0xff, 0xff, 0xec, 0x12, 0xe1, 0x37, 0xfd, 0xeb, 0xfe, + 0xea, 0xd1, 0x12, 0xfa, 0x28, 0x1a, 0x0d, 0xf0, 0xf7, 0xe0, 0x0c, 0xeb, + 0x35, 0x14, 0xeb, 0x00, 0xeb, 0xe7, 0x1b, 0xfc, 0x09, 0x00, 0xf2, 0x04, + 0xf9, 0xe5, 0x1a, 0x0e, 0x08, 0x12, 0xf8, 0xfe, 0x09, 0x0f, 0x0d, 0xea, + 0x03, 0xe1, 0xfe, 0xf2, 0xec, 0x0d, 0x02, 0xdb, 0x04, 0x1d, 0xd4, 0x01, + 0xca, 0x13, 0x29, 0xca, 0x28, 0x04, 0xe2, 0xf1, 0xdb, 0x0b, 0x2c, 0xcd, + 0x44, 0x00, 0xe7, 0xf4, 0xd0, 0x12, 0x15, 0xff, 0x42, 0x11, 0x05, 0xfd, + 0xd9, 0x11, 0x1c, 0xf4, 0x15, 0xec, 0xf2, 0x24, 0xd6, 0x1d, 0xec, 0xda, + 0xf5, 0xec, 0xe5, 0x22, 0xf2, 0x0b, 0xbd, 0xd0, 0xeb, 0x05, 0x07, 0x1b, + 0x01, 0xed, 0xf5, 0x02, 0xcf, 0x08, 0x15, 0xfd, 0x1c, 0xe5, 0x04, 0x19, + 0xc7, 0x25, 0x22, 0xf3, 0xde, 0xfb, 0xfb, 0x20, 0xf6, 0xeb, 0x25, 0xfe, + 0xf5, 0x08, 0xf5, 0x17, 0x0e, 0x04, 0x1c, 0xf9, 0xee, 0xec, 0xe1, 0x06, + 0x12, 0xff, 0x2a, 0x13, 0xed, 0xfe, 0x05, 0x18, 0x25, 0x20, 0x09, 0x13, + 0xea, 0xd7, 0x05, 0x06, 0x33, 0x25, 0xff, 0x0a, 0xf0, 0xea, 0x17, 0xe1, + 0x30, 0xfa, 0x0d, 0x0a, 0x04, 0x00, 0x0e, 0xe9, 0x16, 0x20, 0x0d, 0x02, + 0xe8, 0xed, 0x07, 0xe8, 0x3c, 0xf1, 0xd9, 0xfa, 0xe1, 0xed, 0x18, 0xfc, + 0xf0, 0x09, 0xe3, 0x05, 0xfe, 0xd1, 0x0b, 0x0e, 0xf5, 0x25, 0xfd, 0xfb, + 0x30, 0x1e, 0x08, 0xfc, 0x0c, 0x21, 0xea, 0xfc, 0xe5, 0x1e, 0x16, 0xf5, + 0xf4, 0xfc, 0xf0, 0xea, 0xc4, 0x21, 0x27, 0xe9, 0x2b, 0xdb, 0xdb, 0xec, + 0xe5, 0xfe, 0x37, 0xe2, 0x46, 0x25, 0xfa, 0xec, 0xe4, 0xf3, 0x19, 0xf2, + 0x4c, 0x06, 0x00, 0xfb, 0xeb, 0x10, 0x10, 0xf7, 0x2a, 0xf8, 0xe9, 0x18, + 0xee, 0x21, 0xe8, 0xd5, 0xf4, 0x0a, 0xed, 0x24, 0xfe, 0xf9, 0xb2, 0xbc, + 0xf3, 0x1d, 0x00, 0x2f, 0x07, 0x08, 0xe1, 0xf1, 0xed, 0x27, 0x27, 0xfe, + 0x22, 0xfd, 0x02, 0x20, 0xd8, 0x05, 0x25, 0xec, 0xf1, 0xff, 0x0a, 0x0f, + 0xe6, 0xfe, 0x46, 0xfd, 0xe1, 0xca, 0xf7, 0x22, 0x03, 0x08, 0x21, 0xf5, + 0x0f, 0xf7, 0xfb, 0x0c, 0xfb, 0x14, 0x2d, 0x03, 0xe5, 0xe4, 0x09, 0x0b, + 0x1a, 0xe6, 0x01, 0x28, 0xe9, 0xd6, 0x0b, 0xf7, 0x2c, 0xfb, 0x11, 0xee, + 0x0b, 0xed, 0x17, 0xf0, 0x3c, 0xf5, 0x08, 0xfa, 0xf8, 0xcd, 0x17, 0xfa, + 0x39, 0xea, 0x11, 0xf5, 0xed, 0xee, 0x0a, 0xec, 0x41, 0xd6, 0xe7, 0xf9, + 0xfa, 0xc8, 0x15, 0xf7, 0x08, 0x0e, 0xe3, 0x08, 0xe8, 0xec, 0xfd, 0xfe, + 0xf1, 0x00, 0xe9, 0xf4, 0x09, 0x26, 0x02, 0x16, 0xf0, 0x01, 0xef, 0x01, + 0xff, 0x03, 0x22, 0xdb, 0xfc, 0xf5, 0xde, 0xe5, 0xc4, 0x01, 0x28, 0xd4, + 0x38, 0x08, 0xd0, 0xec, 0xd5, 0x04, 0x2f, 0xce, 0x4e, 0xeb, 0xf9, 0xe7, + 0xdf, 0xf0, 0x1b, 0xf5, 0x42, 0xf1, 0xf6, 0x09, 0xd5, 0x0a, 0x0d, 0x08, + 0x04, 0x05, 0xe2, 0x0e, 0xd7, 0x19, 0xdb, 0xda, 0xe1, 0x25, 0xde, 0x15, + 0x0e, 0x14, 0xbd, 0xb0, 0xe3, 0xe5, 0x24, 0x1e, 0xf8, 0x0d, 0xd8, 0xf7, + 0xf2, 0xff, 0x18, 0xf5, 0x07, 0xf0, 0x02, 0x25, 0xd5, 0x1e, 0x2e, 0xdf, + 0xe7, 0x05, 0xef, 0x11, 0xe8, 0xe7, 0x47, 0xf4, 0xe1, 0xde, 0x09, 0x36, + 0x1a, 0x11, 0x11, 0xf5, 0x12, 0xe5, 0xe7, 0x18, 0x01, 0x17, 0x2a, 0x03, + 0x05, 0xea, 0x09, 0x0b, 0x12, 0x04, 0x17, 0xf0, 0xee, 0xd7, 0x11, 0xed, + 0x3c, 0x17, 0x16, 0xff, 0x02, 0xdc, 0x21, 0xf3, 0x2e, 0xe5, 0x13, 0xef, + 0xec, 0xe2, 0x10, 0xd0, 0x2e, 0xee, 0xff, 0x01, 0xe0, 0xe5, 0x0b, 0xda, + 0x1f, 0xf8, 0xf6, 0xfb, 0x07, 0xdb, 0x05, 0xf6, 0x0c, 0xf3, 0xf0, 0x10, + 0xf9, 0xf5, 0xf2, 0x0d, 0x10, 0xf7, 0xf6, 0xff, 0x2b, 0x0d, 0x06, 0x1e, + 0xf3, 0x0c, 0xe9, 0x01, 0xf2, 0x23, 0xfe, 0xe9, 0xdd, 0x12, 0xdd, 0xf7, + 0xbb, 0x22, 0x1b, 0xd4, 0x38, 0x29, 0xd4, 0xcf, 0xf5, 0xf9, 0x27, 0xdd, + 0x47, 0x00, 0xf2, 0xe5, 0x09, 0xfc, 0x0e, 0xf9, 0x34, 0x0a, 0x02, 0xfd, + 0xec, 0x25, 0x1d, 0x03, 0x15, 0x09, 0xf1, 0x1b, 0xd0, 0x17, 0xda, 0xda, + 0xe7, 0x07, 0xe3, 0x15, 0xf1, 0x02, 0xb9, 0xce, 0xe6, 0x0c, 0x10, 0x31, + 0xfe, 0xf7, 0xd9, 0xfa, 0xed, 0xed, 0x33, 0xf4, 0x19, 0xe7, 0xfe, 0x3f, + 0xe5, 0x06, 0x2e, 0xe6, 0xf2, 0xdc, 0xf5, 0x18, 0xe6, 0x01, 0x2f, 0xee, + 0xe7, 0xe4, 0xfe, 0x2c, 0x03, 0xf7, 0x20, 0x05, 0x07, 0xe2, 0x06, 0x1e, + 0x05, 0xed, 0x2f, 0x03, 0xea, 0xf8, 0x0e, 0x0c, 0x1f, 0xff, 0x20, 0xf4, + 0xe8, 0xe1, 0x1c, 0xec, 0x22, 0x1e, 0x05, 0xfd, 0xf5, 0xca, 0x30, 0xe9, + 0x30, 0xe4, 0x14, 0xff, 0xf2, 0xdc, 0x17, 0xf8, 0x26, 0xe1, 0x0b, 0x01, + 0x11, 0xc2, 0x02, 0xf1, 0x36, 0x10, 0x02, 0x05, 0xed, 0xf1, 0x15, 0xfa, + 0x17, 0xf8, 0xf7, 0xf1, 0xe8, 0xd3, 0xfd, 0x08, 0xfb, 0x27, 0xf5, 0xf5, + 0x13, 0x06, 0x0b, 0xf0, 0x01, 0xf9, 0xd7, 0x0e, 0xec, 0x12, 0xfe, 0xfd, + 0xee, 0x25, 0xd8, 0xf1, 0xb2, 0x09, 0x1c, 0xbf, 0x34, 0xea, 0xc8, 0xea, + 0xdb, 0x0e, 0x24, 0xde, 0x47, 0xfe, 0xdc, 0xe0, 0xf3, 0x06, 0x20, 0xfe, + 0x2b, 0xf6, 0x18, 0x14, 0xcd, 0x19, 0x16, 0xfe, 0x1a, 0x15, 0xf8, 0x11, + 0xf4, 0x22, 0xd7, 0xcc, 0xdd, 0x15, 0xdc, 0x14, 0xf9, 0x02, 0xbb, 0xca, + 0xe3, 0xf3, 0x0d, 0x1e, 0x2a, 0x0c, 0xe4, 0x05, 0xe0, 0x18, 0x2a, 0x07, + 0x20, 0xed, 0xf6, 0x17, 0xcf, 0xf4, 0x2a, 0xd6, 0xfb, 0xce, 0x03, 0x37, + 0xe2, 0xfd, 0x1d, 0xfb, 0xe5, 0xe0, 0x05, 0x29, 0xef, 0x16, 0x23, 0xf7, + 0x01, 0xf4, 0x0c, 0x14, 0xff, 0xee, 0x31, 0xf9, 0x12, 0xf9, 0x14, 0xf6, + 0x0c, 0xf6, 0x0b, 0x0f, 0xd8, 0xdc, 0xfe, 0x0f, 0x37, 0xfa, 0x01, 0x09, + 0x04, 0xd1, 0x0b, 0x0c, 0x29, 0xf3, 0x0a, 0xf9, 0xed, 0xc2, 0x18, 0xf4, + 0x25, 0x18, 0x0f, 0x08, 0xf7, 0xed, 0x1f, 0xf7, 0x4f, 0x0e, 0xf0, 0xe4, + 0x00, 0xeb, 0xfa, 0x1a, 0x0c, 0x03, 0xe9, 0xfc, 0xf0, 0xcc, 0x06, 0x05, + 0xf2, 0x12, 0x04, 0xe2, 0x16, 0x0a, 0x0a, 0xf3, 0x0b, 0xf3, 0xdc, 0xfd, + 0x10, 0xfc, 0x0e, 0xe2, 0xe0, 0xfe, 0xf0, 0xff, 0xb1, 0x06, 0x1b, 0xe4, + 0x30, 0x13, 0xc6, 0xc3, 0xfa, 0x0c, 0x1e, 0xd9, 0x57, 0x11, 0xe1, 0xd6, + 0xfa, 0xee, 0x1d, 0xf7, 0x37, 0xea, 0xf0, 0x05, 0xef, 0x24, 0x1e, 0xf1, + 0x10, 0xe8, 0xeb, 0x19, 0xd1, 0x18, 0xf5, 0xc8, 0xf8, 0xec, 0xf5, 0x1f, + 0xf2, 0xff, 0xb3, 0xd2, 0xe6, 0x0e, 0x06, 0x2e, 0x07, 0x17, 0xe0, 0xf5, + 0x02, 0xf9, 0x20, 0x07, 0x16, 0x08, 0xe8, 0x1d, 0xd3, 0x08, 0x34, 0xda, + 0xf2, 0xce, 0xfb, 0x1f, 0xe1, 0x00, 0x2d, 0xdb, 0xdf, 0xcc, 0x05, 0xfb, + 0xf7, 0x00, 0x33, 0xf9, 0x0b, 0x01, 0x13, 0x28, 0xf8, 0x07, 0x24, 0xf8, + 0x0f, 0x03, 0x0d, 0xe9, 0x06, 0xfe, 0x18, 0xf9, 0xed, 0xf5, 0x0c, 0xe0, + 0x2c, 0x0e, 0xf9, 0x06, 0xfb, 0xce, 0x27, 0xe8, 0x29, 0x19, 0xf9, 0x01, + 0x0e, 0xc8, 0x25, 0xed, 0x30, 0xeb, 0x01, 0xfe, 0x10, 0xdc, 0x1e, 0x00, + 0x1e, 0x10, 0xf9, 0x00, 0xfc, 0xc8, 0x0e, 0x04, 0x13, 0x04, 0xf0, 0x02, + 0xfe, 0xd8, 0x0f, 0x1b, 0xf7, 0xe1, 0xf8, 0xde, 0x12, 0xe2, 0xef, 0x0a, + 0x02, 0xe0, 0xdd, 0xf1, 0x0e, 0x2a, 0x25, 0x15, 0xeb, 0x02, 0xf4, 0xf0, + 0xbf, 0xfc, 0x27, 0xdc, 0x42, 0x0f, 0xe9, 0xbf, 0xe8, 0x20, 0x33, 0xc9, + 0x3f, 0x10, 0xec, 0xf3, 0x03, 0x02, 0x2c, 0x04, 0x38, 0x06, 0x0a, 0xf9, + 0xe5, 0x1c, 0x3f, 0x0f, 0x0c, 0x25, 0xe2, 0x06, 0xe6, 0x03, 0xf4, 0xd7, + 0xfe, 0xf6, 0xe7, 0x2f, 0xfa, 0x03, 0xb6, 0xcb, 0xf1, 0x11, 0x0a, 0x2c, + 0xfc, 0x1e, 0xe0, 0xff, 0xc2, 0xdd, 0x1d, 0xf3, 0x10, 0xfa, 0x07, 0x1e, + 0xf6, 0x20, 0x07, 0xe6, 0xf1, 0x0a, 0xe8, 0x27, 0xf1, 0xf5, 0x24, 0xed, + 0xfd, 0xee, 0x13, 0x15, 0xe9, 0xe2, 0x22, 0xe5, 0xf9, 0xdd, 0x1d, 0x32, + 0x04, 0xfa, 0x25, 0x00, 0xee, 0xfd, 0x0b, 0x0e, 0x23, 0xfa, 0x0f, 0x01, + 0xf8, 0xf0, 0x15, 0xe4, 0x21, 0xf7, 0x10, 0xf9, 0xe7, 0xc3, 0x19, 0xe1, + 0x34, 0xff, 0xed, 0xf4, 0xef, 0xd7, 0x21, 0x01, 0x31, 0xee, 0xf7, 0xf2, + 0xf3, 0xe5, 0x0a, 0xee, 0x2e, 0x1e, 0xf2, 0x0c, 0x07, 0xc2, 0x08, 0x0a, + 0x14, 0x14, 0x00, 0xfc, 0xf9, 0xd6, 0xfb, 0xf8, 0xe5, 0xf1, 0xfa, 0xe0, + 0x15, 0x21, 0xef, 0x06, 0xf9, 0x00, 0xf5, 0xf4, 0x0b, 0x0b, 0x18, 0x02, + 0xf5, 0x04, 0xdb, 0xfd, 0xcc, 0x32, 0x1d, 0xc9, 0x3b, 0x12, 0xd9, 0xaf, + 0xcf, 0x0f, 0x26, 0xde, 0x35, 0xe4, 0xdb, 0xd3, 0x22, 0x11, 0x2e, 0xfb, + 0x36, 0xfa, 0xfd, 0x02, 0xeb, 0x0f, 0x37, 0x0b, 0x14, 0x1d, 0xdd, 0x18, + 0xe0, 0x10, 0xe0, 0xdf, 0x14, 0xf9, 0xf0, 0x19, 0xf7, 0xfb, 0xc4, 0xe5, + 0xe7, 0x11, 0x01, 0x31, 0x1a, 0xf7, 0xd8, 0xf1, 0xe9, 0xf3, 0x21, 0xf9, + 0xfe, 0xe4, 0xe9, 0x02, 0xd0, 0x06, 0x14, 0xd7, 0xfc, 0xec, 0x06, 0x10, + 0xfc, 0xf0, 0x1c, 0xe7, 0xec, 0xe3, 0x03, 0x21, 0xe4, 0x04, 0x12, 0xf0, + 0xf3, 0xed, 0x16, 0x36, 0x02, 0xfd, 0x13, 0x11, 0xdf, 0xeb, 0x19, 0x07, + 0x10, 0x0c, 0xf9, 0x08, 0xf8, 0xf4, 0x1d, 0xfd, 0x1d, 0x16, 0xf4, 0x0a, + 0x08, 0xec, 0x0c, 0x09, 0x3d, 0xe0, 0x0b, 0xee, 0x10, 0xd1, 0x1e, 0x15, + 0x43, 0xeb, 0xfa, 0xf3, 0x05, 0xc7, 0xf2, 0xd9, 0x25, 0x20, 0xee, 0xe9, + 0xfd, 0xce, 0x16, 0x0c, 0x27, 0x06, 0x0a, 0x06, 0xf9, 0xd6, 0x0b, 0x05, + 0xe8, 0x02, 0xe8, 0xd2, 0x10, 0x01, 0xf2, 0x15, 0x09, 0x04, 0xd3, 0xe2, + 0xfe, 0xf0, 0x32, 0x1b, 0xd9, 0xf5, 0xea, 0xcc, 0xcb, 0x10, 0x1c, 0xf1, + 0x3b, 0x02, 0xd4, 0xbf, 0xca, 0xfe, 0x12, 0xdb, 0x3b, 0xf8, 0xd5, 0xe7, + 0x13, 0x10, 0x1a, 0xf4, 0x38, 0x09, 0x08, 0xee, 0xf4, 0xf4, 0x3c, 0xf7, + 0x15, 0x04, 0xe4, 0xfa, 0xf4, 0x04, 0xee, 0xf4, 0x07, 0xf8, 0xe9, 0x3b, + 0xe2, 0x1f, 0xd5, 0xed, 0xe6, 0xfd, 0x18, 0x49, 0x21, 0x06, 0xd8, 0xde, + 0xfa, 0xf0, 0x1b, 0xfe, 0xde, 0x08, 0xf7, 0x14, 0xc7, 0x0f, 0x1d, 0xcf, + 0x00, 0xea, 0xff, 0x1b, 0xd5, 0x08, 0x0d, 0xd9, 0xf1, 0xf4, 0x16, 0x23, + 0xd8, 0x0c, 0x29, 0xdc, 0xf1, 0xf2, 0x21, 0x49, 0xfc, 0xe2, 0x08, 0x01, + 0xf0, 0xf8, 0x17, 0xf9, 0x0f, 0xf5, 0xfa, 0x1a, 0xef, 0xec, 0x09, 0xeb, + 0x1a, 0x0c, 0x17, 0x09, 0x11, 0xe9, 0x1a, 0xf7, 0x29, 0xf9, 0xfd, 0x07, + 0x01, 0xdd, 0x0a, 0xec, 0x22, 0x15, 0x03, 0xfd, 0xe2, 0xd2, 0x15, 0xec, + 0x4d, 0xd7, 0xfc, 0xf6, 0x0b, 0xcc, 0x0e, 0x04, 0x03, 0xf7, 0xfb, 0xfb, + 0x0d, 0xeb, 0x19, 0x07, 0xf4, 0xf4, 0xe5, 0xde, 0x22, 0x07, 0xea, 0xf7, + 0xeb, 0x23, 0xc8, 0xee, 0x03, 0x04, 0x0f, 0x19, 0xc3, 0xf8, 0x06, 0xd0, + 0xf7, 0xfe, 0x0e, 0xe7, 0x0a, 0x02, 0xb0, 0xb8, 0x00, 0xfb, 0x18, 0x0f, + 0x22, 0xf7, 0xe9, 0xdc, 0x09, 0x15, 0x23, 0x0d, 0x22, 0x13, 0xe2, 0xed, + 0xeb, 0x18, 0x20, 0x0b, 0x12, 0xfc, 0x02, 0xf1, 0xdb, 0x0e, 0xe1, 0x04, + 0xdb, 0x0f, 0xf3, 0x1a, 0x06, 0xef, 0xdb, 0xdc, 0xdd, 0xfb, 0x00, 0x2a, + 0x20, 0xfd, 0xc1, 0xe3, 0xef, 0x01, 0x14, 0xf2, 0x14, 0x00, 0x0f, 0x28, + 0xd9, 0xff, 0xf4, 0xdc, 0x09, 0xfa, 0x1c, 0x08, 0xd1, 0x03, 0x0a, 0xf4, + 0xe4, 0xdb, 0x20, 0x30, 0xea, 0x06, 0x11, 0xe2, 0x26, 0xf7, 0x16, 0x22, + 0xf9, 0x07, 0x02, 0xf5, 0xf6, 0xfb, 0x1d, 0x0c, 0x16, 0x0a, 0x07, 0xf9, + 0x11, 0xde, 0x20, 0x08, 0x19, 0x04, 0x0a, 0x0b, 0x0c, 0xf7, 0xf4, 0xfc, + 0x41, 0xf1, 0xf8, 0x16, 0x09, 0xdc, 0x0e, 0x1a, 0x2b, 0x1f, 0xe7, 0xfe, + 0x01, 0xe0, 0xfd, 0xe2, 0x34, 0xec, 0xf3, 0xf5, 0x03, 0xec, 0x0b, 0xfb, + 0x04, 0xf6, 0xdd, 0xfd, 0x06, 0x14, 0x0d, 0xfa, 0xfc, 0xf1, 0x0a, 0xca, + 0x01, 0xec, 0x0e, 0x0e, 0xec, 0xd7, 0xee, 0xd4, 0xf2, 0xfe, 0x16, 0xfa, + 0xbd, 0x0d, 0xef, 0xcb, 0xc4, 0xee, 0xed, 0x13, 0x10, 0x19, 0xf8, 0xb1, + 0xf1, 0xe3, 0x00, 0xf3, 0x0c, 0xf6, 0xde, 0xc6, 0x15, 0x27, 0x14, 0x29, + 0x15, 0xf6, 0xf4, 0xf5, 0xe7, 0x00, 0x0b, 0x2f, 0x0c, 0xef, 0x03, 0x0f, + 0xfd, 0x08, 0xf3, 0xf9, 0xf9, 0x05, 0x0d, 0x34, 0x15, 0x1b, 0xc8, 0xd1, + 0xf2, 0x1b, 0x0a, 0x22, 0x12, 0x11, 0xe9, 0xf4, 0xe1, 0x2a, 0x20, 0x03, + 0xf2, 0xf8, 0x14, 0x0b, 0xd0, 0xf4, 0x0e, 0xbf, 0xc6, 0xd8, 0x04, 0x05, + 0xf8, 0xf4, 0x04, 0xc9, 0xea, 0xfd, 0xf7, 0xfa, 0xe3, 0x1b, 0x11, 0xde, + 0x0c, 0x11, 0x25, 0x29, 0xe5, 0x02, 0xef, 0xef, 0x02, 0xfa, 0x1a, 0x21, + 0x19, 0x09, 0x08, 0x05, 0x04, 0xe5, 0xfa, 0xed, 0x2d, 0x26, 0xfa, 0x17, + 0xf6, 0xe8, 0x12, 0x12, 0x31, 0xfc, 0x0d, 0x00, 0xf7, 0xeb, 0x19, 0xf1, + 0x2a, 0x06, 0x14, 0xec, 0x08, 0xd3, 0x21, 0x07, 0x32, 0xe3, 0x02, 0x0b, + 0xfb, 0xd8, 0x27, 0x07, 0x05, 0xe6, 0xf5, 0xf5, 0x0a, 0xf7, 0x2c, 0x2a, + 0xd8, 0x1b, 0xda, 0xf7, 0xea, 0xf6, 0xf9, 0x0e, 0xf8, 0x0c, 0x05, 0xc7, + 0xd6, 0x06, 0x12, 0xe3, 0xe1, 0xe1, 0xd8, 0xdb, 0xc6, 0xf8, 0xe6, 0xfa, + 0x0c, 0x07, 0xf8, 0xe7, 0xe1, 0x0f, 0x00, 0xf3, 0x03, 0xf0, 0xde, 0xcc, + 0xf5, 0xfc, 0xef, 0x1e, 0x16, 0x13, 0xfb, 0xf4, 0x03, 0xe9, 0xfc, 0xfa, + 0x15, 0xe8, 0x15, 0x09, 0xf1, 0x0d, 0xdb, 0x0a, 0xe8, 0x09, 0xf5, 0x1a, + 0x04, 0xf8, 0xd8, 0xd4, 0x04, 0xee, 0x25, 0x29, 0x09, 0xfe, 0xf3, 0xf5, + 0xd4, 0x0a, 0x15, 0x19, 0xf5, 0x12, 0xfe, 0x04, 0xe7, 0x01, 0xeb, 0xde, + 0xbe, 0xfe, 0x09, 0x12, 0xdf, 0x13, 0xe0, 0xef, 0xc7, 0xff, 0x03, 0x08, + 0xfe, 0xf2, 0x19, 0xe0, 0xe4, 0x0c, 0x22, 0x1e, 0x05, 0xf7, 0x16, 0xf2, + 0xf9, 0x06, 0x17, 0xf6, 0x0c, 0x1e, 0x23, 0x08, 0xfe, 0xdc, 0xfd, 0x17, + 0x11, 0xdf, 0xf5, 0x0f, 0x01, 0x03, 0x08, 0xee, 0x1b, 0x02, 0x0b, 0x1b, + 0x0c, 0x16, 0x1a, 0x00, 0x0f, 0x26, 0x14, 0xf8, 0xf4, 0xf3, 0x19, 0x16, + 0x22, 0x0a, 0xd0, 0xf9, 0xf1, 0x05, 0x2b, 0x1e, 0x1e, 0xef, 0xf5, 0x06, + 0x05, 0xe7, 0x3f, 0x2a, 0x06, 0xf0, 0x15, 0x14, 0x13, 0x20, 0x1b, 0xde, + 0x10, 0x05, 0x33, 0xf8, 0x08, 0x04, 0x17, 0x0d, 0x0f, 0xf6, 0x01, 0xed, + 0x28, 0x25, 0x1c, 0x13, 0xfb, 0xea, 0xfb, 0xf3, 0x1c, 0xf9, 0x1f, 0xf0, + 0xfb, 0x17, 0xf8, 0xff, 0x10, 0xf7, 0x0b, 0x24, 0x04, 0x00, 0x0d, 0x0c, + 0xf7, 0x0a, 0x16, 0x13, 0xf8, 0x05, 0x0a, 0xf1, 0xf5, 0xee, 0xf8, 0x14, + 0x0e, 0xed, 0xfe, 0x1b, 0xfe, 0x17, 0x13, 0x10, 0x12, 0x21, 0x1c, 0xfa, + 0xe5, 0x0b, 0x08, 0x0c, 0x10, 0x1b, 0x03, 0xef, 0x0d, 0x05, 0x0a, 0xf0, + 0x04, 0x11, 0x15, 0x00, 0xfd, 0xef, 0x02, 0x18, 0xf4, 0x09, 0xfa, 0xf6, + 0x02, 0xf7, 0xfd, 0x13, 0xef, 0x13, 0xf7, 0xf9, 0x17, 0x0f, 0xfa, 0xf8, + 0x15, 0xff, 0x04, 0xef, 0xf0, 0x15, 0xfa, 0xfe, 0xf0, 0xf4, 0xed, 0x06, + 0x1c, 0x02, 0xfb, 0xf7, 0x05, 0xfb, 0x0c, 0xef, 0xf4, 0xf0, 0xf6, 0xec, + 0x17, 0xf3, 0xf5, 0xef, 0x02, 0xfd, 0xe5, 0x21, 0x0c, 0xf1, 0x1e, 0x08, + 0xf1, 0x0b, 0xf7, 0x09, 0x1d, 0xf2, 0xf9, 0xf2, 0xfb, 0x0e, 0xed, 0xf8, + 0xfa, 0xdd, 0xf0, 0xfd, 0xdb, 0x1a, 0xf4, 0xef, 0x0c, 0x06, 0x0f, 0xdf, + 0xe2, 0x06, 0x06, 0xee, 0xfa, 0x0d, 0x17, 0xfc, 0xf9, 0x15, 0x1a, 0xe4, + 0xfb, 0x0c, 0x1a, 0xfc, 0x1b, 0x04, 0x07, 0x20, 0xff, 0x09, 0x0f, 0xf2, + 0x26, 0x19, 0x1f, 0x0d, 0x02, 0x16, 0x03, 0x03, 0xfd, 0x05, 0x01, 0x1b, + 0x0a, 0x11, 0xfa, 0x21, 0x13, 0xfb, 0x0c, 0x05, 0xf3, 0xdd, 0xe4, 0xdc, + 0x22, 0x1b, 0x15, 0x14, 0x0e, 0xe8, 0x00, 0xf7, 0xf8, 0xf4, 0x0b, 0x0b, + 0xfd, 0x21, 0xe3, 0x0f, 0xe1, 0x22, 0x01, 0x21, 0x0b, 0x1f, 0x09, 0x10, + 0xe2, 0x18, 0x11, 0x0e, 0xed, 0x01, 0x14, 0x12, 0xfd, 0x11, 0xf6, 0xe9, + 0x20, 0xe1, 0xf5, 0x1b, 0x27, 0x22, 0xfa, 0xf7, 0xfe, 0x13, 0xf6, 0xdc, + 0x06, 0x0d, 0xf4, 0x05, 0x20, 0x0d, 0x0b, 0xe4, 0x15, 0x28, 0x0c, 0x00, + 0xf5, 0x07, 0x0c, 0x0a, 0x06, 0x0e, 0xf3, 0xfb, 0xfe, 0x04, 0x08, 0xf4, + 0xef, 0x03, 0xe4, 0xeb, 0x06, 0xee, 0xed, 0xdb, 0xeb, 0x1d, 0xf4, 0xfa, + 0x0c, 0xfc, 0xfe, 0x11, 0xf7, 0xf8, 0xf5, 0xef, 0xe7, 0xfc, 0x1b, 0xdc, + 0x17, 0xfd, 0xfe, 0x00, 0xea, 0xf4, 0xf1, 0xf7, 0x0f, 0x21, 0x04, 0xfd, + 0x0d, 0x0c, 0x0a, 0x14, 0xfd, 0x19, 0x09, 0x01, 0xfd, 0xe2, 0x0c, 0x0c, + 0xe0, 0x25, 0xfb, 0xff, 0x0d, 0x18, 0xf6, 0x0b, 0x19, 0x12, 0x10, 0x09, + 0x0b, 0x06, 0x12, 0x1c, 0x10, 0x03, 0x13, 0x0a, 0x05, 0x0f, 0x09, 0x01, + 0x21, 0xe4, 0x01, 0x26, 0xf9, 0xf4, 0x05, 0x19, 0x00, 0xff, 0x0b, 0xff, + 0x16, 0x09, 0xe7, 0xee, 0xed, 0xf5, 0x0f, 0x2f, 0xee, 0x19, 0x03, 0x0a, + 0x10, 0xee, 0xf7, 0x2e, 0xf4, 0x08, 0xf7, 0xee, 0x07, 0x00, 0xfc, 0x0e, + 0xf0, 0x12, 0x08, 0x05, 0xed, 0x11, 0xfc, 0xfb, 0xf7, 0x25, 0xf1, 0x05, + 0x0c, 0xf9, 0xfa, 0x03, 0x0c, 0x16, 0x04, 0x25, 0xf8, 0xe7, 0xfc, 0x11, + 0x0d, 0x19, 0xd8, 0xfa, 0x0b, 0x06, 0xfd, 0xef, 0x13, 0xf6, 0xff, 0x0e, + 0xf9, 0x04, 0xf1, 0xdc, 0xfb, 0xe1, 0xf6, 0x0b, 0x15, 0x07, 0xf7, 0x02, + 0x0e, 0xf1, 0xfd, 0xe3, 0xeb, 0x07, 0xf1, 0xef, 0x03, 0xfe, 0xf8, 0x07, + 0x10, 0xf7, 0x00, 0xf9, 0xf2, 0x0e, 0xf9, 0xf2, 0x1d, 0xf5, 0xd8, 0xff, + 0xe6, 0x18, 0x2a, 0x1b, 0x03, 0x16, 0xfe, 0xf4, 0xf5, 0xfd, 0x04, 0x01, + 0xfe, 0xfe, 0x07, 0xfc, 0x0e, 0xfa, 0x15, 0xeb, 0x02, 0x15, 0xea, 0xfd, + 0x04, 0xe5, 0xfe, 0xed, 0xfe, 0x1a, 0x09, 0x2a, 0x1b, 0xdf, 0xfb, 0xf8, + 0xf1, 0x04, 0x1a, 0x34, 0x07, 0xf9, 0x0d, 0xf5, 0xef, 0xec, 0x10, 0x1a, + 0x0b, 0x0f, 0x13, 0xfe, 0x10, 0x22, 0x1e, 0x02, 0xe6, 0xf7, 0x11, 0xfa, + 0x11, 0xfc, 0x1b, 0x21, 0x12, 0xf4, 0x18, 0x16, 0x29, 0xe4, 0x0c, 0x2e, + 0x12, 0x07, 0x20, 0xf6, 0x1d, 0xf4, 0x12, 0x33, 0xf4, 0xee, 0xfe, 0x05, + 0x06, 0xfb, 0x13, 0x0c, 0x0e, 0xf0, 0x00, 0xf8, 0xee, 0xf3, 0x17, 0x00, + 0xf7, 0xfb, 0xfc, 0x0f, 0xf4, 0xd5, 0x0a, 0xed, 0xeb, 0xf5, 0xe9, 0xef, + 0xd8, 0xf0, 0xf8, 0xe2, 0x19, 0xf7, 0xf8, 0x0a, 0x0b, 0x09, 0xfa, 0xe7, + 0x0f, 0xfc, 0xe8, 0x02, 0x00, 0x1a, 0xfe, 0xfd, 0x1b, 0xe6, 0xef, 0x0f, + 0xe3, 0x10, 0xf1, 0xe2, 0x0b, 0x0e, 0x06, 0x29, 0x00, 0x01, 0xf3, 0x00, + 0x11, 0x04, 0xf2, 0xf7, 0xea, 0xf8, 0xe0, 0x09, 0x0e, 0x13, 0xf4, 0x00, + 0x09, 0xfa, 0xf5, 0x0c, 0xff, 0x18, 0x08, 0x0d, 0xfa, 0xde, 0xfa, 0x03, + 0xf2, 0xf3, 0x1b, 0xeb, 0x06, 0xea, 0xfb, 0xff, 0x0d, 0xf5, 0x10, 0x17, + 0xf8, 0xe8, 0xf1, 0xf1, 0xf5, 0x00, 0x03, 0x0a, 0x09, 0x0a, 0xf3, 0xfb, + 0x33, 0x26, 0xe7, 0x17, 0xe3, 0xfa, 0x1f, 0x24, 0xfc, 0x07, 0x02, 0xe2, + 0xeb, 0x08, 0x2c, 0xf8, 0x02, 0x1f, 0x04, 0xeb, 0x0b, 0x04, 0x17, 0xf7, + 0xff, 0x1c, 0xed, 0x00, 0x3f, 0xd5, 0x17, 0x1d, 0xfe, 0x03, 0xf1, 0x1c, + 0x17, 0xec, 0x0e, 0x54, 0xee, 0xf5, 0x25, 0xfa, 0x08, 0xee, 0x13, 0x32, + 0x0e, 0xd8, 0x09, 0x0f, 0xee, 0xe5, 0x06, 0x10, 0xf4, 0xfb, 0xe4, 0xfb, + 0x09, 0xde, 0x13, 0xff, 0x02, 0xf9, 0xec, 0x0a, 0x00, 0xe9, 0xfd, 0xdc, + 0x06, 0x04, 0xdb, 0x06, 0x01, 0xf8, 0x09, 0xe2, 0x0c, 0x14, 0xda, 0xfe, + 0x20, 0xe3, 0x09, 0xda, 0x14, 0x12, 0xe1, 0x05, 0xff, 0xf3, 0x00, 0x08, + 0xfb, 0xf1, 0xfd, 0xf3, 0x04, 0xfa, 0x08, 0xff, 0x01, 0x1d, 0x0b, 0xfd, + 0x0a, 0xf4, 0xfb, 0xfc, 0xf9, 0x19, 0xed, 0xfc, 0xf2, 0x06, 0xe7, 0x02, + 0xf6, 0x0c, 0xfc, 0xfb, 0x01, 0x0c, 0xeb, 0x1b, 0xff, 0xff, 0x08, 0x1d, + 0xf7, 0xe8, 0xfc, 0xf4, 0x0c, 0xfa, 0xf1, 0xee, 0xed, 0xdd, 0xfc, 0x06, + 0x05, 0xdc, 0x1a, 0xfc, 0xf9, 0x07, 0xdf, 0x1b, 0x14, 0x0c, 0xfc, 0x01, + 0x16, 0xe1, 0xed, 0x09, 0x34, 0xee, 0xe4, 0x1c, 0x1b, 0xfc, 0x3b, 0x03, + 0x15, 0xf2, 0xeb, 0x14, 0x00, 0xdd, 0x24, 0x04, 0xf1, 0xed, 0xfd, 0xe6, + 0x32, 0xf9, 0x24, 0x04, 0x0e, 0x22, 0x03, 0x14, 0x2f, 0xf5, 0x1a, 0x37, + 0xf4, 0x18, 0x03, 0x0f, 0x4b, 0xe6, 0x0d, 0x5c, 0xf7, 0x1f, 0x1c, 0xe6, + 0x23, 0x0c, 0x15, 0x4e, 0xe0, 0x05, 0x1c, 0xec, 0xff, 0x04, 0x13, 0x15, + 0xee, 0x07, 0xec, 0x0c, 0xdd, 0xf8, 0x0e, 0x03, 0x0c, 0x1f, 0xe8, 0x0e, + 0xf5, 0xec, 0xfc, 0xe2, 0xe8, 0xfb, 0xf6, 0x00, 0xe5, 0xea, 0xf3, 0xd3, + 0xf5, 0xfd, 0xd2, 0xfd, 0x1b, 0xed, 0x09, 0xd1, 0x23, 0xfa, 0xd4, 0xf7, + 0xe9, 0xf0, 0x0a, 0xd6, 0x14, 0x03, 0xe6, 0x10, 0xf4, 0x18, 0xfe, 0xe1, + 0x0b, 0x25, 0xf5, 0xfc, 0xe9, 0xf2, 0xe9, 0xf4, 0x0d, 0xf5, 0x00, 0xf9, + 0x17, 0x02, 0xfd, 0x03, 0x04, 0xf8, 0xf5, 0x14, 0xe3, 0xd3, 0xeb, 0xe7, + 0x09, 0xf3, 0x14, 0x17, 0xee, 0xe6, 0xf6, 0xff, 0x11, 0x26, 0xf4, 0xf7, + 0x02, 0xfa, 0x05, 0x08, 0x16, 0xff, 0x0d, 0xf7, 0xf1, 0xf7, 0xe6, 0xfb, + 0x04, 0x04, 0x07, 0x02, 0x04, 0x09, 0xf5, 0xfc, 0x5f, 0xd6, 0xe7, 0x2a, + 0x23, 0xf4, 0x1b, 0x06, 0x01, 0xea, 0xe7, 0x05, 0x25, 0xe3, 0x25, 0x07, + 0xea, 0xfb, 0xfb, 0x09, 0x25, 0xde, 0x37, 0x04, 0x07, 0xe5, 0xff, 0x14, + 0x2f, 0x0a, 0x30, 0x23, 0x04, 0xf0, 0x23, 0xfe, 0x1c, 0xd2, 0x2b, 0x55, + 0x01, 0xe5, 0x26, 0xfe, 0x14, 0xed, 0x24, 0x46, 0xe6, 0xee, 0x0f, 0xfd, + 0xed, 0xef, 0x0e, 0x1e, 0x05, 0x0a, 0x12, 0xff, 0xe4, 0xf5, 0x0c, 0xed, + 0xfd, 0xea, 0x0d, 0x13, 0x1a, 0xe5, 0xfc, 0xc2, 0xef, 0x0a, 0xe2, 0x0f, + 0xfe, 0xff, 0x0c, 0xf0, 0xff, 0xdf, 0xea, 0x00, 0xf6, 0xe1, 0x04, 0xd8, + 0x26, 0x20, 0xdc, 0xf4, 0x19, 0x06, 0xe8, 0xd2, 0x10, 0x04, 0xf1, 0x02, + 0x0c, 0x06, 0xf0, 0xf0, 0x04, 0x1f, 0xf4, 0xf5, 0xed, 0xf1, 0xfa, 0xf1, + 0x04, 0x02, 0xf8, 0xfb, 0x04, 0xf1, 0xe5, 0xe4, 0x0a, 0xf0, 0xfe, 0xef, + 0x1c, 0xe3, 0xeb, 0xf3, 0x00, 0x17, 0x01, 0x13, 0x19, 0xda, 0xf8, 0x06, + 0xde, 0x11, 0xea, 0xf7, 0xf4, 0xef, 0x03, 0x04, 0x0b, 0xe8, 0x08, 0x0e, + 0xe2, 0xee, 0xde, 0x06, 0x0e, 0x29, 0xfb, 0xfa, 0x00, 0x02, 0xec, 0x1b, + 0x52, 0xff, 0xde, 0x3a, 0x2f, 0x13, 0x30, 0xe9, 0xff, 0xf6, 0xe7, 0x15, + 0x1d, 0xd9, 0x3c, 0x0f, 0xe6, 0x14, 0xee, 0x13, 0x1f, 0xe7, 0x33, 0x08, + 0xfc, 0x06, 0x0c, 0x08, 0x19, 0xd9, 0x2b, 0x1f, 0x07, 0x10, 0x24, 0x16, + 0x29, 0xfc, 0x31, 0x4d, 0xf0, 0xd9, 0x3f, 0xf2, 0x20, 0xe2, 0x25, 0x49, + 0xe5, 0xec, 0x0a, 0xf5, 0xf2, 0xd9, 0x22, 0x1f, 0xed, 0x22, 0x02, 0x0a, + 0x16, 0x08, 0xf7, 0xfb, 0x0e, 0xfb, 0xfb, 0x1d, 0xf3, 0x1c, 0xf6, 0xe1, + 0xcf, 0x19, 0xf4, 0x0f, 0xee, 0xf9, 0x04, 0xd1, 0xf9, 0xe2, 0xda, 0xf1, + 0x24, 0xf5, 0x07, 0xdf, 0x1d, 0xf9, 0xdb, 0x18, 0x0b, 0xea, 0x08, 0xca, + 0xf2, 0xfa, 0xec, 0x04, 0x0e, 0x17, 0xed, 0xf1, 0x06, 0x15, 0xfc, 0xfd, + 0x08, 0xfa, 0xe3, 0xe4, 0x0a, 0xfc, 0xee, 0x08, 0xf5, 0x09, 0xef, 0xee, + 0x06, 0xef, 0xe1, 0x19, 0x07, 0xe8, 0xe6, 0xdf, 0xea, 0x0d, 0xf1, 0x16, + 0xee, 0xed, 0xf8, 0x09, 0xfa, 0xfb, 0x0c, 0xf8, 0xeb, 0xda, 0x00, 0xfc, + 0x04, 0xfe, 0xf5, 0xff, 0xf6, 0xe1, 0x0c, 0x0a, 0x13, 0x0d, 0xf6, 0xf5, + 0x15, 0x07, 0xca, 0xec, 0x50, 0x0e, 0xd0, 0x26, 0x4c, 0xf8, 0x23, 0xeb, + 0xff, 0x08, 0xe3, 0x11, 0x2c, 0xf9, 0x2a, 0xf1, 0xe9, 0x0b, 0xe9, 0x0f, + 0x15, 0xec, 0x33, 0x11, 0x0c, 0x0d, 0x01, 0x01, 0x32, 0xe3, 0x41, 0x27, + 0x11, 0x02, 0x2e, 0x07, 0x09, 0xe3, 0x22, 0x4d, 0xf1, 0x05, 0x27, 0x03, + 0x25, 0xf5, 0x2c, 0x3b, 0xf4, 0x00, 0x16, 0x0b, 0xec, 0xfe, 0x17, 0x0d, + 0xff, 0xe7, 0xfe, 0x24, 0x06, 0xee, 0xf0, 0xe9, 0xfa, 0x1c, 0xf2, 0x19, + 0x08, 0xfa, 0xff, 0xd2, 0x01, 0x02, 0xea, 0x05, 0xf2, 0xf4, 0x0b, 0xd2, + 0xf9, 0x0d, 0xcd, 0x0d, 0x12, 0xf2, 0x0e, 0xe1, 0x1f, 0x00, 0xe7, 0x14, + 0x04, 0xff, 0x09, 0xdb, 0xfc, 0xd9, 0x06, 0xf9, 0xeb, 0x01, 0xef, 0xfa, + 0xfb, 0xf5, 0xfc, 0xfb, 0x14, 0xe2, 0xf9, 0xf5, 0x02, 0xfd, 0xfc, 0x01, + 0xf7, 0xf3, 0x00, 0xec, 0xe7, 0xf2, 0x00, 0xf1, 0x11, 0xec, 0xf0, 0xe9, + 0x11, 0x0a, 0x07, 0x04, 0x01, 0xee, 0xfb, 0xf2, 0x14, 0x01, 0x12, 0xf0, + 0xf2, 0xf1, 0xf0, 0xfb, 0x08, 0x03, 0xf8, 0x01, 0xe8, 0xf9, 0x17, 0x26, + 0x0f, 0xea, 0xf7, 0xf8, 0x1e, 0xfe, 0xf2, 0xf8, 0x3f, 0x00, 0xd4, 0x1c, + 0x53, 0xfe, 0x1e, 0x0f, 0xef, 0xdd, 0xed, 0x10, 0x19, 0xe7, 0x34, 0x0e, + 0xde, 0xdf, 0xfa, 0x0e, 0x29, 0xe3, 0x16, 0x09, 0x06, 0x12, 0xeb, 0xf9, + 0x32, 0xe0, 0x1a, 0x1d, 0xf3, 0xed, 0x10, 0x07, 0x31, 0xf2, 0x12, 0x52, + 0xeb, 0xf7, 0x1e, 0xf7, 0x1a, 0xdc, 0x3e, 0x33, 0xe3, 0xfb, 0x1f, 0x0b, + 0x08, 0xfe, 0x13, 0x1a, 0xf4, 0xf8, 0xfe, 0x08, 0xfc, 0xe9, 0xfe, 0xeb, + 0xe6, 0xf6, 0x02, 0x18, 0x02, 0xe8, 0xfb, 0xf3, 0x01, 0x08, 0xd7, 0x13, + 0x04, 0xe6, 0x02, 0xe6, 0xd7, 0x01, 0xd4, 0xf0, 0x0e, 0x05, 0x18, 0xe5, + 0x08, 0xe5, 0xd2, 0x16, 0x12, 0xfe, 0x0e, 0xd3, 0xfc, 0x1f, 0xe9, 0xf8, + 0x11, 0x06, 0xf3, 0xd5, 0xf8, 0xff, 0xf0, 0x04, 0x0a, 0xd9, 0xf8, 0xfd, + 0xf5, 0x12, 0xff, 0x06, 0x1b, 0xe6, 0xfe, 0xfe, 0xde, 0xee, 0xf6, 0x18, + 0xf1, 0xf8, 0x06, 0xf3, 0x02, 0xea, 0x04, 0x14, 0xfc, 0xee, 0xe6, 0x09, + 0xf9, 0xee, 0xe3, 0xe7, 0xfc, 0xd9, 0xef, 0xfc, 0x0a, 0x0c, 0x03, 0xf6, + 0xe2, 0x11, 0x0f, 0x19, 0x18, 0x10, 0xef, 0xe5, 0x22, 0xf5, 0xe5, 0xe9, + 0x4b, 0xf7, 0xdb, 0x0c, 0x4f, 0xde, 0x22, 0x16, 0x09, 0x16, 0xd1, 0xf8, + 0x19, 0xe0, 0x24, 0xfe, 0xb8, 0xfb, 0xe5, 0x12, 0x1c, 0xe3, 0x22, 0x09, + 0x05, 0x29, 0xf7, 0x10, 0x31, 0xe1, 0x33, 0x3f, 0xfd, 0xed, 0x04, 0x03, + 0x2e, 0xed, 0x30, 0x36, 0xee, 0x16, 0x2f, 0xf5, 0x1b, 0xdc, 0x3a, 0x56, + 0xe5, 0xef, 0x26, 0xff, 0x03, 0xd7, 0x31, 0x16, 0xef, 0xf1, 0x08, 0x13, + 0x01, 0x02, 0x03, 0xf1, 0xf2, 0x08, 0xff, 0x05, 0x12, 0xf2, 0xee, 0xda, + 0xed, 0xec, 0xea, 0xf7, 0x0c, 0xf1, 0x09, 0xe6, 0xe6, 0x00, 0xcc, 0x10, + 0x0d, 0x0d, 0x20, 0xf4, 0x18, 0x23, 0xec, 0xf9, 0x00, 0xe4, 0x07, 0xd4, + 0xfb, 0x16, 0xd2, 0x01, 0xe6, 0x01, 0x06, 0xf0, 0xfe, 0x03, 0xf3, 0x09, + 0x01, 0x0d, 0x05, 0xf7, 0xd4, 0x02, 0xfb, 0xfb, 0x08, 0xf0, 0x1f, 0xf3, + 0xfe, 0xeb, 0x02, 0x0e, 0x1b, 0x0f, 0x04, 0xf5, 0xf0, 0x1f, 0x14, 0xf7, + 0x06, 0xdc, 0xf9, 0xe9, 0x01, 0xff, 0x08, 0xf2, 0x06, 0xff, 0xff, 0xf3, + 0x05, 0x1a, 0xfc, 0xfa, 0xeb, 0xfb, 0xfa, 0x12, 0x20, 0xf6, 0xe0, 0xe8, + 0x1c, 0xfa, 0xd6, 0x0d, 0x2c, 0x04, 0xe1, 0x09, 0x3b, 0xd3, 0x2a, 0xee, + 0xf7, 0xed, 0xf1, 0xf7, 0x0d, 0xf0, 0x32, 0x0f, 0xc9, 0x0e, 0x00, 0x10, + 0x24, 0xfb, 0x31, 0xf0, 0xf4, 0xdd, 0xf5, 0x04, 0x25, 0xc7, 0x27, 0x25, + 0x16, 0x11, 0x2e, 0x09, 0x30, 0xd1, 0x2c, 0x34, 0xe6, 0xf0, 0x21, 0xf5, + 0x21, 0xc8, 0x40, 0x39, 0xde, 0xf0, 0x12, 0xf3, 0x10, 0xe8, 0x1f, 0x18, + 0xfa, 0xea, 0x07, 0x11, 0xdf, 0xed, 0xfa, 0xf0, 0x07, 0xef, 0xf3, 0x05, + 0x10, 0xe5, 0xf3, 0xe9, 0xe9, 0xe8, 0xd6, 0x01, 0xf9, 0x05, 0x0b, 0xee, + 0xf9, 0x12, 0xe3, 0x05, 0xfd, 0xe6, 0x16, 0xe2, 0x1b, 0x12, 0xc5, 0x00, + 0xfd, 0x02, 0x04, 0xd2, 0xff, 0xec, 0xf6, 0xfd, 0x00, 0xe4, 0xf7, 0xf3, + 0xeb, 0xfa, 0xf8, 0x0d, 0x03, 0xfa, 0xfe, 0xe4, 0xdb, 0xe3, 0x06, 0xff, + 0xf4, 0xf2, 0x1b, 0xf1, 0xf7, 0x02, 0x01, 0x04, 0x13, 0xe5, 0x0c, 0x05, + 0xf7, 0x0a, 0x03, 0x03, 0x0b, 0x03, 0xee, 0xf7, 0x21, 0x20, 0xff, 0xf3, + 0x09, 0xe5, 0xff, 0xec, 0x17, 0x00, 0x06, 0x14, 0xeb, 0xf2, 0x18, 0x16, + 0x1f, 0xec, 0xee, 0xe1, 0x1e, 0x03, 0xfa, 0xfe, 0x28, 0x03, 0xc9, 0x0c, + 0x3f, 0xd8, 0x30, 0x16, 0x03, 0xf8, 0xe9, 0xfb, 0x28, 0xe1, 0x36, 0x0a, + 0xdf, 0xe5, 0xeb, 0x08, 0x1c, 0xcd, 0x29, 0xf2, 0xfc, 0x0a, 0xed, 0x01, + 0x29, 0xf1, 0x20, 0x13, 0x04, 0xec, 0x17, 0x0a, 0x35, 0xc3, 0x1a, 0x46, + 0xe0, 0xd7, 0x3c, 0x09, 0x28, 0xd1, 0x22, 0x20, 0xd5, 0xfa, 0x28, 0xfa, + 0xff, 0xea, 0x1d, 0x23, 0xe0, 0x07, 0x07, 0x0f, 0xf1, 0xf1, 0x08, 0xf0, + 0xf8, 0xff, 0x05, 0x1b, 0x05, 0xfa, 0xf0, 0xfb, 0xe3, 0xe4, 0xcc, 0x1a, + 0xf9, 0x09, 0x06, 0xee, 0xf4, 0x03, 0xd0, 0x14, 0xf4, 0xff, 0x1d, 0xe8, + 0x11, 0xf4, 0xd1, 0xf4, 0x04, 0x0b, 0xfb, 0xdc, 0x0a, 0x0c, 0xeb, 0xed, + 0x06, 0xf3, 0x04, 0xdd, 0xdf, 0xf9, 0xea, 0xfc, 0xf5, 0xf2, 0xfb, 0xea, + 0xe3, 0x03, 0xee, 0x0e, 0xff, 0xdb, 0x1e, 0x04, 0xf7, 0x1a, 0x04, 0x0c, + 0x0d, 0xda, 0x04, 0xe9, 0xff, 0x04, 0x00, 0x0c, 0xf9, 0xe4, 0xfb, 0xf6, + 0x14, 0xde, 0x1b, 0x00, 0x0b, 0xfe, 0x06, 0xf8, 0x0f, 0xdc, 0x01, 0xef, + 0xef, 0x0d, 0xf8, 0xf1, 0x0f, 0xf9, 0xf9, 0xdf, 0x0d, 0xe4, 0xd9, 0xf9, + 0x2b, 0xee, 0xe8, 0x09, 0x40, 0xf9, 0x2f, 0x0a, 0xfa, 0xe8, 0xe9, 0x01, + 0x0e, 0xe7, 0x23, 0x0a, 0xd0, 0x19, 0xd3, 0x0e, 0x04, 0xda, 0x2b, 0x0f, + 0xe7, 0xe6, 0xf3, 0xfb, 0x2c, 0xd3, 0x36, 0x19, 0x0e, 0xfe, 0x03, 0x1a, + 0x2e, 0xd0, 0x23, 0x32, 0xf1, 0xe1, 0x2a, 0x09, 0x1b, 0xf6, 0x29, 0x3e, + 0xce, 0x15, 0x0a, 0xe8, 0xec, 0xdf, 0x44, 0x28, 0xd9, 0xfd, 0xfa, 0x09, + 0xff, 0xe7, 0x08, 0xec, 0xf4, 0xef, 0x01, 0x19, 0x11, 0xf3, 0xeb, 0xeb, + 0xed, 0x1a, 0xdd, 0x15, 0x0f, 0x07, 0xfe, 0xeb, 0xff, 0xd6, 0xd5, 0x04, + 0xf5, 0x07, 0x10, 0xe6, 0x0c, 0xe4, 0xda, 0x0c, 0x08, 0xee, 0x06, 0xd8, + 0xf8, 0xf1, 0xe0, 0x01, 0x08, 0xfe, 0xf9, 0xf3, 0xdf, 0x03, 0xe6, 0xf4, + 0x0a, 0xff, 0xf2, 0xe0, 0xd9, 0xeb, 0x01, 0x10, 0x02, 0xfc, 0x0d, 0x14, + 0xea, 0xf8, 0x03, 0x18, 0xf3, 0x09, 0xfc, 0x0c, 0x0b, 0x1f, 0xf5, 0x05, + 0xf7, 0xf9, 0x00, 0xfd, 0x04, 0xfc, 0x16, 0x07, 0x00, 0xdf, 0xf9, 0xfa, + 0x0c, 0xfb, 0xf4, 0xf7, 0xf0, 0xeb, 0x07, 0x17, 0x20, 0xfb, 0xf0, 0xec, + 0x04, 0x00, 0xf8, 0xf2, 0x2d, 0xf9, 0xd9, 0x0b, 0x55, 0xec, 0x33, 0x26, + 0xf8, 0x0a, 0xf2, 0x0b, 0x25, 0xdf, 0x29, 0x05, 0xd1, 0x14, 0xe2, 0xf2, + 0x12, 0xdd, 0x28, 0xfc, 0xec, 0x08, 0xfd, 0x02, 0x3a, 0xe6, 0x29, 0x25, + 0x0d, 0x10, 0x09, 0x0a, 0x32, 0xf5, 0x17, 0x2d, 0xea, 0xfb, 0x35, 0xfc, + 0x28, 0xd0, 0x29, 0x2f, 0xcb, 0x06, 0x0f, 0x04, 0xf2, 0xf3, 0x34, 0x1c, + 0xf4, 0x08, 0x05, 0xfc, 0xfd, 0xed, 0x0f, 0xf8, 0xe9, 0xf0, 0x09, 0x16, + 0xfe, 0x02, 0xff, 0xd4, 0xea, 0x0a, 0xeb, 0x0c, 0xf8, 0xf4, 0x09, 0xf4, + 0xf2, 0x07, 0xd9, 0x0b, 0xfd, 0xe4, 0x1a, 0xef, 0x14, 0x08, 0xd8, 0xfc, + 0xf5, 0xe1, 0x03, 0xcf, 0xf1, 0x11, 0xdb, 0x15, 0x07, 0x10, 0xf8, 0xfc, + 0xe2, 0xf1, 0xf5, 0xde, 0xff, 0xe7, 0x01, 0xea, 0xee, 0xe9, 0x02, 0x0a, + 0x18, 0xec, 0xfe, 0xf9, 0x09, 0xf3, 0x0e, 0x02, 0xf1, 0xfc, 0xf9, 0x16, + 0x05, 0x07, 0x09, 0x0d, 0x0e, 0xf7, 0x04, 0xed, 0x04, 0xdb, 0x04, 0x04, + 0xf6, 0xdc, 0xee, 0xec, 0xf5, 0xfe, 0xf4, 0x02, 0xe4, 0x0b, 0xe0, 0x17, + 0x0a, 0xe0, 0xf7, 0xdc, 0x11, 0xd6, 0xfe, 0xfa, 0x35, 0xde, 0xe6, 0x06, + 0x44, 0xf9, 0x35, 0x0a, 0xfb, 0xff, 0xec, 0xfb, 0x16, 0xd9, 0x23, 0x0f, + 0xd4, 0xef, 0xdf, 0x06, 0x0b, 0xd9, 0x25, 0xff, 0xf8, 0xeb, 0xf4, 0x0a, + 0x20, 0xe5, 0x22, 0x1c, 0xeb, 0xf4, 0x0d, 0x0c, 0x19, 0xe1, 0x1e, 0x31, + 0xe9, 0xfb, 0x20, 0xf0, 0x23, 0xfe, 0x35, 0x28, 0xb4, 0x06, 0x28, 0xe7, + 0xfb, 0xe9, 0x2a, 0x1a, 0xef, 0x15, 0x0c, 0xed, 0xf1, 0x04, 0x0e, 0x0a, + 0xff, 0x16, 0x01, 0x04, 0x17, 0xea, 0xec, 0xdc, 0xf4, 0xf7, 0x04, 0x16, + 0x1f, 0x0a, 0x11, 0xef, 0x12, 0xdf, 0xd9, 0x0c, 0xf5, 0x10, 0x02, 0xf3, + 0x10, 0x03, 0xd3, 0xf5, 0x0b, 0x02, 0x00, 0xcb, 0xf6, 0x23, 0xf6, 0xf1, + 0x1f, 0xf9, 0xfc, 0xf0, 0xf6, 0xfe, 0xfa, 0xf8, 0xf9, 0xf4, 0xfb, 0x0a, + 0xd6, 0x29, 0x09, 0x02, 0x00, 0xfc, 0xfc, 0xee, 0xf5, 0x05, 0xfb, 0x1e, + 0xf1, 0xf1, 0xf3, 0x02, 0xec, 0x1c, 0x0c, 0x0e, 0x0b, 0x04, 0xf6, 0xe7, + 0x14, 0x08, 0x27, 0x01, 0xfe, 0xe5, 0xe7, 0x01, 0x1b, 0xf0, 0xf6, 0xff, + 0xf4, 0xe7, 0xee, 0x18, 0x0d, 0x08, 0xf8, 0xd6, 0x07, 0xf4, 0x08, 0xff, + 0x1d, 0x13, 0xe7, 0x0b, 0x42, 0xef, 0x28, 0x00, 0xf9, 0xf0, 0xf3, 0x00, + 0x15, 0xfd, 0x1a, 0x22, 0xc1, 0xf5, 0xe0, 0xf8, 0x09, 0xe6, 0x0e, 0x05, + 0xf9, 0xf6, 0x01, 0x01, 0x13, 0xdc, 0x1f, 0x0d, 0xfb, 0x04, 0x08, 0x0b, + 0x15, 0xdb, 0x28, 0x34, 0xed, 0x0b, 0x3a, 0xed, 0x16, 0xe3, 0x39, 0x32, + 0xc4, 0x0b, 0x20, 0xe7, 0xf7, 0x02, 0x35, 0x24, 0xfc, 0xe8, 0x1c, 0xf8, + 0xf1, 0xfa, 0x0c, 0x1d, 0xf2, 0x05, 0xff, 0x12, 0x0f, 0x01, 0xec, 0xea, + 0xf0, 0x03, 0xe7, 0x15, 0xfd, 0x05, 0x08, 0xe0, 0x1b, 0xf8, 0xe1, 0x1e, + 0xed, 0xdc, 0x11, 0xeb, 0xfd, 0x1a, 0xeb, 0x09, 0xf9, 0xf3, 0x00, 0xe8, + 0xe6, 0x08, 0xf7, 0xde, 0x1e, 0x00, 0x00, 0x00, 0xe4, 0x09, 0xf2, 0xf8, + 0xe7, 0xf2, 0x0d, 0xfa, 0xe2, 0x0f, 0x04, 0x08, 0xf2, 0x13, 0xf8, 0xf9, + 0xf1, 0xff, 0x03, 0x11, 0x12, 0xe9, 0xf4, 0x13, 0x07, 0x0c, 0x13, 0x2b, + 0xf7, 0xdd, 0xf9, 0xe9, 0xfa, 0xdb, 0x1d, 0xf6, 0xf6, 0xf9, 0xe4, 0xf6, + 0x0d, 0xeb, 0x0d, 0x08, 0xe7, 0xe7, 0xf2, 0x03, 0x1d, 0xd9, 0xd8, 0xe4, + 0xf7, 0xea, 0xdc, 0xdc, 0x26, 0x02, 0xee, 0xfa, 0x38, 0xfc, 0x1a, 0xef, + 0xda, 0xf1, 0xdf, 0x0b, 0x1a, 0xe0, 0x16, 0x16, 0xdc, 0x04, 0xfa, 0xf7, + 0xee, 0x02, 0x25, 0x02, 0xf5, 0xfb, 0x08, 0xf6, 0x11, 0xf5, 0x12, 0x08, + 0xf4, 0xe3, 0x1b, 0xf5, 0x3a, 0xdc, 0x20, 0x2e, 0xe0, 0xf5, 0x30, 0xe4, + 0x09, 0xf8, 0x3c, 0x45, 0xd3, 0x08, 0x23, 0xd8, 0x09, 0xe4, 0x35, 0x30, + 0xe4, 0xfe, 0x07, 0xf6, 0x05, 0x01, 0x05, 0xff, 0xf6, 0x0d, 0x02, 0xfd, + 0x03, 0x05, 0x0d, 0x00, 0xf5, 0xd6, 0xcf, 0x19, 0x06, 0xee, 0x0d, 0xf2, + 0x01, 0x18, 0xef, 0x12, 0x04, 0x02, 0x21, 0xd9, 0x02, 0x0d, 0xeb, 0xe9, + 0x13, 0x08, 0x15, 0xf0, 0xee, 0x03, 0xec, 0x06, 0x17, 0xed, 0x00, 0x1a, + 0xee, 0xf2, 0xfc, 0x09, 0xec, 0xf8, 0xf8, 0x18, 0xf4, 0x13, 0x04, 0xf6, + 0x02, 0xf0, 0xfc, 0xfe, 0xe3, 0x01, 0x0a, 0x1c, 0x1b, 0xec, 0x0e, 0x01, + 0xfb, 0x08, 0x11, 0xf5, 0x00, 0x14, 0xe6, 0x12, 0x07, 0xf4, 0x15, 0x07, + 0xfc, 0xfb, 0xf5, 0xf1, 0x01, 0x21, 0x01, 0xe9, 0xe8, 0xef, 0xdb, 0xdf, + 0x1f, 0x0a, 0xdd, 0xd1, 0x16, 0x04, 0xfd, 0xe1, 0x24, 0xf0, 0xec, 0xf4, + 0x38, 0xe1, 0x16, 0xfd, 0xe0, 0xec, 0xe7, 0x0c, 0x2a, 0x04, 0x0c, 0x17, + 0xdc, 0xe8, 0xf2, 0x03, 0xec, 0xfd, 0x19, 0xfe, 0xf3, 0xf0, 0xf3, 0xfb, + 0x18, 0xdf, 0x1c, 0x00, 0x09, 0xf4, 0x18, 0x0b, 0x1f, 0xf6, 0x34, 0x22, + 0xf4, 0x22, 0x45, 0xeb, 0x23, 0xcf, 0x32, 0x34, 0xf2, 0xf9, 0x29, 0xd4, + 0xf7, 0x0b, 0x38, 0x2a, 0x09, 0xe6, 0x05, 0x01, 0x0b, 0xfe, 0x17, 0xfb, + 0x00, 0xeb, 0x08, 0xfd, 0x0c, 0x02, 0x1d, 0xea, 0xfa, 0x0b, 0xeb, 0x09, + 0xfe, 0xfe, 0x10, 0xe0, 0xf6, 0x06, 0xf0, 0x15, 0xf3, 0x09, 0x11, 0xe4, + 0xf9, 0x07, 0xe1, 0xed, 0x17, 0x05, 0x0c, 0xe1, 0xdb, 0xf2, 0xf8, 0xea, + 0x22, 0xe9, 0x02, 0x00, 0xfd, 0xe7, 0xf2, 0xf8, 0xf9, 0xfc, 0xfa, 0xe8, + 0xe8, 0xeb, 0xe9, 0x0d, 0x04, 0xf8, 0xf8, 0xf7, 0xf8, 0x0d, 0x03, 0x0c, + 0x13, 0xf2, 0x0f, 0xf9, 0xe6, 0xfd, 0x0f, 0x19, 0x08, 0xf7, 0xfa, 0x01, + 0xf3, 0x12, 0x1e, 0x05, 0x0a, 0x09, 0xfd, 0x0b, 0x07, 0x08, 0x02, 0xfc, + 0xd6, 0xe8, 0x14, 0x01, 0x13, 0x19, 0xef, 0xda, 0x0e, 0x0a, 0x07, 0xef, + 0x34, 0xe0, 0x05, 0x1e, 0x4e, 0xe9, 0x19, 0xff, 0xe1, 0x04, 0xfb, 0x0e, + 0x11, 0x05, 0x1f, 0x15, 0xd4, 0xec, 0xf9, 0xe7, 0xf9, 0xfc, 0x25, 0xff, + 0x06, 0xf2, 0x01, 0xf6, 0x2a, 0x17, 0x24, 0x11, 0xf3, 0x1a, 0x1f, 0xfb, + 0x32, 0xeb, 0x33, 0x2f, 0x00, 0x08, 0x2c, 0xf0, 0x26, 0xf4, 0x25, 0x36, + 0xd9, 0xf1, 0x1a, 0xd5, 0xec, 0xf9, 0x32, 0x27, 0xfc, 0xf4, 0xf0, 0xe3, + 0xfa, 0x0c, 0x16, 0x17, 0xfa, 0xf9, 0xe5, 0x1f, 0x1f, 0xfa, 0xff, 0xfd, + 0x0d, 0x02, 0xe9, 0x0e, 0xf0, 0x12, 0x09, 0xda, 0x02, 0xea, 0xe5, 0x0a, + 0xff, 0x03, 0x13, 0xf0, 0x0a, 0xf9, 0xe9, 0xff, 0x10, 0xfc, 0x1a, 0xf3, + 0xf7, 0x0f, 0xf4, 0xfa, 0xf4, 0x05, 0x10, 0x0a, 0xdd, 0x09, 0xf7, 0xf0, + 0xe5, 0x07, 0x07, 0xfa, 0x02, 0xd7, 0xf8, 0xf7, 0x01, 0xfb, 0x0e, 0xf8, + 0x07, 0x0f, 0xfe, 0x03, 0x12, 0x05, 0x09, 0x13, 0xf8, 0xdc, 0xfd, 0x27, + 0x0f, 0xec, 0xf7, 0x07, 0x00, 0xfc, 0x12, 0xf8, 0xfb, 0xea, 0xe4, 0xe9, + 0xe9, 0xe0, 0xff, 0xdc, 0xd6, 0xeb, 0xf2, 0xf7, 0x0d, 0x1b, 0xe9, 0xc4, + 0x06, 0x00, 0xfd, 0x04, 0x46, 0xf9, 0xe9, 0x13, 0x2d, 0x0c, 0x1f, 0xf8, + 0xd3, 0x0c, 0x14, 0x11, 0x05, 0xe5, 0x27, 0x08, 0xc5, 0xef, 0xdf, 0xdd, + 0x04, 0xf8, 0x11, 0x10, 0xf0, 0xe7, 0xfb, 0x03, 0x3c, 0xe7, 0x14, 0x0c, + 0xf4, 0xf6, 0x1b, 0x0a, 0x23, 0xf2, 0x2d, 0x1a, 0x08, 0xff, 0x32, 0xe7, + 0x1a, 0x05, 0x2b, 0x34, 0xf1, 0x0a, 0x00, 0xe8, 0x02, 0xdf, 0x2c, 0x2a, + 0x03, 0xe6, 0xfc, 0xef, 0xfc, 0xe4, 0x03, 0x01, 0x03, 0xee, 0xe9, 0x15, + 0x05, 0x03, 0x13, 0x11, 0x0e, 0xee, 0xf5, 0x22, 0x1b, 0x0e, 0xfd, 0xf3, + 0x0a, 0x02, 0xdd, 0x20, 0xeb, 0x06, 0xf8, 0xe2, 0x06, 0x0e, 0xde, 0x0d, + 0xf9, 0x16, 0x1c, 0x0c, 0xe0, 0xf0, 0xec, 0x0c, 0x0f, 0xf2, 0x27, 0x1d, + 0xde, 0xe6, 0xf0, 0xf9, 0xf0, 0x02, 0x0a, 0x07, 0x06, 0xf9, 0x0f, 0xfa, + 0xf0, 0xee, 0xf1, 0xf7, 0xff, 0x02, 0x0b, 0x0d, 0x1b, 0xee, 0xf6, 0x05, + 0xff, 0x1c, 0x17, 0x04, 0x05, 0x17, 0x00, 0xff, 0x0d, 0xf3, 0x23, 0x10, + 0xfd, 0x05, 0xfb, 0xea, 0x03, 0x10, 0x07, 0xd7, 0xf7, 0xff, 0xf3, 0xf1, + 0x17, 0xed, 0xd3, 0xcb, 0x14, 0x1c, 0xf5, 0x03, 0x47, 0xf6, 0xf7, 0xf2, + 0x3e, 0xf2, 0x22, 0xf4, 0xed, 0xfc, 0xee, 0x0b, 0xf4, 0xf1, 0x25, 0x10, + 0xd0, 0xf6, 0x00, 0xef, 0x10, 0xfc, 0x15, 0xe5, 0xdb, 0xf3, 0xea, 0x10, + 0x22, 0xf2, 0x2b, 0x11, 0xf9, 0x0a, 0xfc, 0xf5, 0x53, 0x16, 0x25, 0x43, + 0xe0, 0x0e, 0x13, 0xfc, 0x2d, 0xe2, 0x55, 0x65, 0xf4, 0x08, 0x01, 0xdf, + 0x0a, 0x00, 0x49, 0x1c, 0xfe, 0xdf, 0xef, 0xf2, 0xf9, 0xf6, 0xfd, 0xff, + 0xf3, 0x02, 0xf6, 0x14, 0x0b, 0xe8, 0x09, 0xfc, 0xfc, 0xe2, 0xe5, 0x11, + 0x03, 0x09, 0xfb, 0x06, 0x10, 0x1a, 0xf3, 0x0d, 0xfa, 0x0a, 0xd5, 0xf5, + 0x1a, 0x11, 0xf2, 0xfc, 0x1f, 0xfe, 0x0e, 0xe4, 0xef, 0xd7, 0xee, 0x06, + 0x1e, 0x04, 0x12, 0x28, 0xf7, 0x0e, 0x06, 0xf8, 0xee, 0xf0, 0x1a, 0x01, + 0xf7, 0xfd, 0x03, 0x11, 0x19, 0x10, 0x04, 0xfb, 0xd7, 0xfa, 0x16, 0x06, + 0x07, 0x23, 0xfa, 0x14, 0x11, 0xf1, 0x12, 0x10, 0x04, 0xe1, 0xee, 0xf7, + 0x21, 0x0e, 0x0a, 0x0a, 0xf8, 0x07, 0x0a, 0xee, 0x03, 0x1f, 0xfa, 0xc4, + 0xec, 0x12, 0x01, 0x1e, 0xfd, 0xf1, 0xe8, 0xcc, 0xf4, 0x17, 0xff, 0xdd, + 0x45, 0x10, 0xee, 0xfa, 0x3d, 0xe7, 0x27, 0xdd, 0xd7, 0xf9, 0xf4, 0xf6, + 0x06, 0xf8, 0x1e, 0x13, 0xe7, 0xe2, 0xf1, 0xe3, 0xf3, 0xf7, 0x18, 0x12, + 0xe4, 0x0a, 0xdb, 0xff, 0xff, 0xfe, 0x20, 0x09, 0x00, 0xf7, 0x23, 0xf6, + 0x2d, 0x14, 0x26, 0x28, 0xe5, 0xff, 0x0f, 0xe3, 0x1d, 0xe8, 0x56, 0x43, + 0xe7, 0xfb, 0xf9, 0xe6, 0xe9, 0xe2, 0x19, 0x19, 0x08, 0xfa, 0xf3, 0xe5, + 0x23, 0x07, 0x0f, 0xf8, 0xf8, 0xf3, 0xfc, 0x11, 0x2a, 0x05, 0xf4, 0xf1, + 0xfa, 0xfb, 0xf1, 0x1e, 0x13, 0x0f, 0xf9, 0xf5, 0xfa, 0x09, 0xf9, 0x03, + 0xf0, 0xf0, 0xe7, 0xec, 0xf1, 0x0c, 0xe6, 0xee, 0xf6, 0x20, 0x0f, 0xe9, + 0x00, 0xf4, 0xfe, 0xf0, 0x13, 0x0a, 0x17, 0x13, 0xee, 0x13, 0xfb, 0xff, + 0xf8, 0xfd, 0xf4, 0xe2, 0xe8, 0x06, 0xfc, 0x14, 0x03, 0x17, 0x00, 0x03, + 0xe6, 0xfd, 0xf2, 0x12, 0x12, 0x20, 0xeb, 0x10, 0x02, 0xf7, 0x13, 0x0d, + 0x11, 0xfd, 0xde, 0xf5, 0x07, 0xf3, 0x04, 0xff, 0x06, 0x05, 0xfb, 0xea, + 0xf0, 0x0a, 0x00, 0xb5, 0xe8, 0x1a, 0x03, 0xfe, 0x0d, 0x1a, 0xe7, 0xc0, + 0xd6, 0xdc, 0xf6, 0xf8, 0x39, 0xf5, 0xd5, 0xf8, 0x22, 0xfa, 0x22, 0x05, + 0xd0, 0xf4, 0x2d, 0xfc, 0x00, 0x0a, 0x1b, 0xfc, 0xe6, 0x09, 0x14, 0xfa, + 0x00, 0x1d, 0x1a, 0xfd, 0xf3, 0x18, 0xfc, 0xeb, 0x15, 0xf5, 0x0e, 0x0a, + 0xf3, 0xf1, 0x1b, 0x05, 0x14, 0x03, 0x2d, 0x27, 0xfb, 0x18, 0x22, 0xef, + 0xf6, 0x06, 0x28, 0x2b, 0xde, 0xec, 0xef, 0xe8, 0xd3, 0xfe, 0x17, 0x12, + 0x01, 0x13, 0x05, 0xf7, 0x00, 0xde, 0xf3, 0xe5, 0x03, 0xfb, 0x07, 0x0b, + 0xfd, 0xdc, 0xdf, 0x03, 0x0c, 0x00, 0xfa, 0x06, 0x0e, 0x02, 0x05, 0xfa, + 0xfd, 0xed, 0x09, 0x0c, 0xfd, 0xfb, 0x0c, 0xf0, 0xe4, 0x04, 0xd6, 0xf3, + 0x09, 0x0a, 0xf9, 0xf8, 0xe2, 0xef, 0xdf, 0xf0, 0xf8, 0x03, 0x0f, 0x20, + 0xf4, 0xe3, 0xf8, 0x02, 0xe2, 0xe5, 0x25, 0x0f, 0xeb, 0xf8, 0xe9, 0xfd, + 0x04, 0x0c, 0x0c, 0xfe, 0x01, 0x08, 0xfc, 0xfc, 0x1b, 0x01, 0xe5, 0x13, + 0xf9, 0xe8, 0x07, 0x20, 0xfe, 0x06, 0xec, 0xfe, 0x09, 0xef, 0x14, 0x04, + 0x0b, 0xf5, 0xe7, 0xff, 0x0a, 0x02, 0x09, 0xe9, 0xc4, 0x16, 0x0d, 0xe7, + 0x15, 0x14, 0xf1, 0xd0, 0xec, 0xe7, 0xf0, 0xf0, 0x33, 0x05, 0xda, 0xf2, + 0x0b, 0x08, 0x38, 0x01, 0x07, 0xfd, 0xd8, 0x06, 0xd9, 0xf0, 0x16, 0x1f, + 0xff, 0xf7, 0xe0, 0xd8, 0xf3, 0xf7, 0x12, 0x08, 0x0e, 0x05, 0xf6, 0x03, + 0xef, 0x1b, 0x12, 0xf4, 0xe8, 0x0f, 0x02, 0xfd, 0xf2, 0x16, 0x26, 0x22, + 0xe0, 0x07, 0xf7, 0xe6, 0xeb, 0x16, 0x22, 0x1a, 0x0b, 0x01, 0xf5, 0xea, + 0xd2, 0x22, 0x0f, 0x13, 0x15, 0x08, 0xf0, 0xfb, 0xed, 0x11, 0xf3, 0xe9, + 0xff, 0xde, 0x0a, 0x18, 0x0f, 0x02, 0xfb, 0xf9, 0xfb, 0xe8, 0x12, 0x18, + 0x01, 0xf4, 0xf6, 0xf8, 0xf0, 0x1f, 0x24, 0x15, 0xf5, 0x00, 0x1c, 0xf9, + 0x01, 0x0a, 0x11, 0xd5, 0x01, 0x12, 0x02, 0xec, 0xfd, 0x07, 0xf2, 0xea, + 0xf9, 0xff, 0xf7, 0xfb, 0x15, 0xec, 0xe5, 0x01, 0xeb, 0x05, 0xf9, 0x10, + 0xfe, 0x28, 0xe5, 0x0a, 0xeb, 0x1b, 0x0e, 0xf9, 0xde, 0x02, 0x15, 0x0a, + 0xff, 0xfe, 0x11, 0x24, 0x03, 0xf8, 0x00, 0x08, 0xfd, 0x0e, 0xeb, 0xf3, + 0xf6, 0xf7, 0x14, 0x0e, 0xfc, 0xf5, 0xde, 0xf5, 0x9e, 0xfe, 0xff, 0xff, + 0x04, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0xab, 0x01, 0x00, 0x00, + 0xfa, 0xfd, 0xff, 0xff, 0xa2, 0xff, 0xff, 0xff, 0xba, 0x00, 0x00, 0x00, + 0x24, 0xfc, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x54, 0x4f, 0x43, 0x4f, + 0x20, 0x43, 0x6f, 0x6e, 0x76, 0x65, 0x72, 0x74, 0x65, 0x64, 0x2e, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x24, 0xfb, 0xff, 0xff, + 0x68, 0x01, 0x00, 0x00, 0x5c, 0x01, 0x00, 0x00, 0x50, 0x01, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xf4, 0x00, 0x00, 0x00, + 0x90, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0xce, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x09, 0x03, 0x00, 0x00, 0x00, + 0x1c, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x1a, 0xff, 0xff, 0xff, 0x00, 0x00, 0x80, 0x3f, 0x01, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x0e, 0x00, 0x18, 0x00, 0x08, 0x00, 0x0c, 0x00, 0x10, 0x00, + 0x07, 0x00, 0x14, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, + 0x01, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0xc4, 0xfc, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, + 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x07, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x00, + 0x16, 0x00, 0x00, 0x00, 0x08, 0x00, 0x0c, 0x00, 0x07, 0x00, 0x10, 0x00, + 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x38, 0x00, 0x00, 0x00, + 0x2c, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x00, + 0x14, 0x00, 0x00, 0x00, 0x08, 0x00, 0x0c, 0x00, 0x10, 0x00, 0x07, 0x00, + 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x00, + 0x1a, 0x00, 0x08, 0x00, 0x0c, 0x00, 0x10, 0x00, 0x07, 0x00, 0x14, 0x00, + 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x02, 0x00, 0x00, 0x00, + 0x38, 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x06, 0x00, 0x08, 0x00, 0x04, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0x31, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, + 0x0a, 0x00, 0x00, 0x00, 0x34, 0x04, 0x00, 0x00, 0xcc, 0x03, 0x00, 0x00, + 0x4c, 0x03, 0x00, 0x00, 0xdc, 0x02, 0x00, 0x00, 0x60, 0x02, 0x00, 0x00, + 0x20, 0x02, 0x00, 0x00, 0xb0, 0x01, 0x00, 0x00, 0x44, 0x01, 0x00, 0x00, + 0x70, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x02, 0xfc, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x09, 0x44, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, + 0x28, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xf4, 0xfb, 0xff, 0xff, + 0x14, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x80, 0x3b, 0x0e, 0x00, 0x00, 0x00, 0x6c, 0x61, 0x62, 0x65, + 0x6c, 0x73, 0x5f, 0x73, 0x6f, 0x66, 0x74, 0x6d, 0x61, 0x78, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x0e, 0x00, 0x1a, 0x00, 0x08, 0x00, 0x07, 0x00, 0x0c, 0x00, + 0x10, 0x00, 0x14, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, + 0xb4, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x94, 0x00, 0x00, 0x00, + 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00, 0x10, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x04, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, + 0x12, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x11, 0x1e, 0x23, 0x3a, 0x9e, 0xa1, 0x15, 0x39, + 0x23, 0x69, 0x45, 0x3a, 0x09, 0xe4, 0xe4, 0x39, 0x65, 0xd7, 0x13, 0x3a, + 0xe0, 0xb2, 0xfd, 0x39, 0x1b, 0xc1, 0x53, 0x3a, 0xc2, 0x50, 0x2d, 0x3a, + 0x12, 0x00, 0x00, 0x00, 0x66, 0x69, 0x72, 0x73, 0x74, 0x5f, 0x77, 0x65, + 0x69, 0x67, 0x68, 0x74, 0x73, 0x2f, 0x72, 0x65, 0x61, 0x64, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x3a, 0xfd, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x09, 0x54, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x28, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x2c, 0xfd, 0xff, 0xff, + 0x14, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0xb5, 0xfa, 0xfa, 0x39, 0x1f, 0x00, 0x00, 0x00, 0x66, 0x69, 0x6e, 0x61, + 0x6c, 0x5f, 0x66, 0x63, 0x5f, 0x77, 0x65, 0x69, 0x67, 0x68, 0x74, 0x73, + 0x2f, 0x72, 0x65, 0x61, 0x64, 0x2f, 0x74, 0x72, 0x61, 0x6e, 0x73, 0x70, + 0x6f, 0x73, 0x65, 0x00, 0x02, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0xa0, 0x0f, 0x00, 0x00, 0xa2, 0xfd, 0xff, 0xff, 0x00, 0x00, 0x00, 0x09, + 0x58, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x74, 0xfe, 0xff, 0xff, 0x30, 0x00, 0x00, 0x00, + 0x24, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xf2, 0xdd, 0xbb, 0x3d, + 0x01, 0x00, 0x00, 0x00, 0x32, 0xa3, 0x25, 0x41, 0x01, 0x00, 0x00, 0x00, + 0xf6, 0xa0, 0x50, 0xc1, 0x05, 0x00, 0x00, 0x00, 0x61, 0x64, 0x64, 0x5f, + 0x31, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x0e, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x02, + 0x2c, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x0f, 0x00, 0x00, 0x00, 0x52, 0x65, 0x73, 0x68, 0x61, 0x70, 0x65, 0x5f, + 0x32, 0x2f, 0x73, 0x68, 0x61, 0x70, 0x65, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x4a, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x09, + 0x5c, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x1c, 0xff, 0xff, 0xff, 0x30, 0x00, 0x00, 0x00, + 0x24, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x50, 0x50, 0xd0, 0x3d, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0xcf, 0x41, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x52, 0x65, 0x73, 0x68, + 0x61, 0x70, 0x65, 0x5f, 0x32, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0xc2, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x09, + 0x58, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x94, 0xff, 0xff, 0xff, 0x2c, 0x00, 0x00, 0x00, + 0x20, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x01, 0x00, 0x00, 0x00, 0x50, 0x50, 0xd0, 0x3d, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x80, 0xcf, 0x41, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x52, 0x65, 0x73, 0x68, 0x61, 0x70, 0x65, 0x5f, + 0x31, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0xa8, 0x07, 0x00, 0x00, 0x2e, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x09, + 0x60, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x4c, 0x00, 0x00, 0x00, + 0x10, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x14, 0x00, 0x04, 0x00, 0x08, 0x00, + 0x0c, 0x00, 0x10, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x00, + 0x20, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x01, 0x00, 0x00, 0x00, 0x3a, 0x6a, 0xac, 0x3d, 0x01, 0x00, 0x00, 0x00, + 0xd0, 0xbd, 0xab, 0x41, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x52, 0x65, 0x6c, 0x75, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0xaa, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x02, 0x44, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x2c, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x9c, 0xff, 0xff, 0xff, + 0x18, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x96, 0x08, 0x29, 0x38, 0x0b, 0x00, 0x00, 0x00, + 0x4d, 0x61, 0x74, 0x4d, 0x75, 0x6c, 0x5f, 0x62, 0x69, 0x61, 0x73, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x00, + 0x18, 0x00, 0x08, 0x00, 0x07, 0x00, 0x0c, 0x00, 0x10, 0x00, 0x14, 0x00, + 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x08, 0x00, + 0x0c, 0x00, 0x00, 0x00, 0x4c, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x9a, 0xbb, 0x84, 0x38, 0x83, 0x84, 0x73, 0x37, 0x5b, 0xa3, 0xa0, 0x38, + 0x16, 0x41, 0x3a, 0x38, 0xc7, 0x9a, 0x70, 0x38, 0xed, 0x70, 0x4e, 0x38, + 0x54, 0x4f, 0xac, 0x38, 0xfd, 0x07, 0x8d, 0x38, 0x0b, 0x00, 0x00, 0x00, + 0x43, 0x6f, 0x6e, 0x76, 0x32, 0x44, 0x5f, 0x62, 0x69, 0x61, 0x73, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, + 0x4c, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0xe6, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x19, + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x06, 0x00, 0x05, 0x00, + 0x06, 0x00, 0x00, 0x00, 0x00, 0x16, 0x0a, 0x00, 0x0e, 0x00, 0x07, 0x00, + 0x00, 0x00, 0x08, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x0c, 0x00, 0x07, 0x00, + 0x00, 0x00, 0x08, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, + 0x03, 0x00, 0x00, 0x00}; +const int g_model_len = 18712; diff --git a/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/model.h b/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/model.h new file mode 100644 index 000000000..deec2d646 --- /dev/null +++ b/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/model.h @@ -0,0 +1,27 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +// This is a standard TensorFlow Lite FlatBuffer model file that has been +// converted into a C data array, so it can be easily compiled into a binary +// for devices that don't have a file system. It was created using the command: +// xxd -i model.tflite > model.cc + +#ifndef TENSORFLOW_LITE_MICRO_EXAMPLES_MICRO_SPEECH_MICRO_FEATURES_MODEL_H_ +#define TENSORFLOW_LITE_MICRO_EXAMPLES_MICRO_SPEECH_MICRO_FEATURES_MODEL_H_ + +extern const unsigned char g_model[]; +extern const int g_model_len; + +#endif // TENSORFLOW_LITE_MICRO_EXAMPLES_MICRO_SPEECH_MICRO_FEATURES_MODEL_H_ diff --git a/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/no_micro_features_data.cc b/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/no_micro_features_data.cc new file mode 100644 index 000000000..64bd8b528 --- /dev/null +++ b/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/no_micro_features_data.cc @@ -0,0 +1,188 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "no_micro_features_data.h" + +// Golden test values for the expected spectrogram from a "no" sample file +// speech_commands_test_set_v0.02/no/f9643d42_nohash_4.wav. + +const int g_no_micro_f9643d42_nohash_4_width = 40; +const int g_no_micro_f9643d42_nohash_4_height = 49; +const signed char g_no_micro_f9643d42_nohash_4_data[] = { + 103, 78, 64, 76, 75, 54, 53, 67, 77, 60, 56, 70, + 76, 71, 68, 58, 74, 32, 23, -2, -18, 11, 13, 15, + 9, 20, 5, -7, -18, -2, -10, -18, -10, -12, 9, 7, + -33, -12, -4, -18, 57, 17, 55, 62, 70, 45, 61, 37, + 67, 52, 48, 47, 55, 46, 57, 47, 73, 17, 27, 20, + 19, 8, 15, -6, -1, 10, -12, -29, -6, -23, -18, -3, + -1, 5, 3, -4, -12, -8, -1, -14, 65, 48, 58, 43, + 48, 19, 39, 39, 57, 57, 58, 55, 67, 58, 49, 50, + 70, 27, 9, 16, 37, 4, 25, 4, 11, 9, 7, -33, + -7, -12, 3, -6, -29, -7, -7, -18, -12, -18, -2, -1, + 0, 31, 60, -8, 51, 59, 70, 40, 71, 57, 52, 38, + 66, 48, 17, 6, 59, 8, 15, 7, 18, 4, 18, -23, + -8, -4, -3, -12, -3, -26, 1, 10, 2, -29, -29, -37, + -7, -4, 6, -33, 67, 44, 59, -4, 64, 51, 68, 55, + 74, 9, 40, 15, 57, 33, 60, 18, 40, 25, 27, -20, + 25, -16, 6, 17, -10, -12, -23, -43, -23, -23, -29, -37, + -4, -16, -16, -60, -20, -23, -10, -29, -12, 15, 12, -37, + 27, 15, 61, 44, 50, 8, 48, 22, 49, -18, 46, 33, + 42, 34, 46, -8, 4, -18, -43, -43, -10, 1, -10, -16, + -10, -77, -16, -33, 11, -26, -23, -37, 0, -8, -16, -29, + 42, 40, 68, 24, 47, 46, 53, -128, 30, 2, 42, 21, + 21, -4, 43, 2, 43, 5, 32, -26, 7, -37, -43, -23, + -2, -8, 2, -37, -50, -60, -1, -7, -33, -77, -6, -18, + -16, -50, -12, -33, 53, 8, 52, 18, 51, 35, 69, 26, + 44, 8, 27, -128, 21, -33, 17, -14, 38, -128, -14, -18, + 17, -20, -14, -37, 8, -60, -33, -33, -33, -43, -12, -29, + -12, -128, -33, -60, -26, -77, -26, -50, 57, 29, 11, 30, + 53, -10, 45, 15, 18, -10, 42, 2, 31, -29, 10, -4, + 42, -37, -50, -128, -4, -43, -20, -77, -14, -26, -33, -128, + -12, -43, -8, -33, -33, -60, -43, -77, -12, -60, -26, -50, + 40, -23, 36, 35, 50, -2, 37, 27, 26, -77, 49, -7, + 28, -43, 6, 11, 41, -37, 33, -26, -14, -12, -6, -33, + -16, -26, -20, -77, -14, -43, -8, -50, -14, -37, -26, -77, + -26, -77, -14, -29, 50, -60, 25, -26, 57, 38, 51, 1, + 50, 1, 53, -18, 30, -23, 11, -128, 18, -43, 20, -26, + -10, -26, -12, -128, -50, -60, -37, -77, -20, -43, -50, -128, + -77, -128, -77, -128, -33, -77, -20, -60, 53, -10, -37, -128, + 10, -128, 60, 18, -8, 13, 37, -37, 8, -128, 3, -77, + 32, -29, 14, 10, -12, -77, -37, -77, -37, -60, -23, -128, + -43, -50, -16, -77, -6, -33, 0, -60, -43, -128, -16, -60, + 20, -2, 51, 19, 43, 2, 63, 20, 60, -4, 42, -50, + 4, -128, 2, -3, 32, -33, -26, -128, -18, -128, -33, -43, + -7, -60, -50, -77, -29, -77, -23, -128, -16, -26, -23, -60, + -37, -77, -37, -128, -1, -33, 39, 48, 60, 5, 8, -128, + 44, 11, 4, 0, 13, -77, -2, -20, 33, -128, -33, -77, + -8, -128, -14, -128, -33, -18, -12, -77, -16, -128, -37, -128, + -12, -77, -60, -128, -23, -60, -23, -128, 36, -50, 46, -128, + 66, 39, 18, -14, -12, -77, -20, -6, 24, -128, 28, -26, + 21, -77, -6, -33, 1, -128, -43, -128, -1, -50, -37, -128, + -50, -128, -33, -128, -18, -128, -60, -8, -7, -60, -60, -128, + -6, -29, 20, -1, 73, 40, -43, -14, 33, -43, 33, -3, + 15, -29, 29, -43, 20, -60, -29, -128, -20, -26, 4, -77, + -16, -60, -33, -50, -29, -128, -60, -128, -77, -128, -37, -50, + 0, -77, -33, -128, 39, 8, 47, 10, 62, 16, 2, 1, + 10, 7, 4, -7, 6, -128, -77, -50, 19, -77, -77, -128, + -77, -128, -50, -128, -60, -60, -33, -50, -37, -128, -128, -128, + -60, -128, -37, -60, -18, -128, -33, -77, 37, 23, 29, -128, + -128, -128, -16, -128, -16, -33, 21, -20, -8, -60, -2, -60, + 11, -128, -50, -128, -50, -128, -29, -77, -16, -128, -26, -128, + -50, -77, -43, -128, -128, -128, -50, -128, -33, -128, -33, -50, + -23, -128, 24, -128, -128, -77, 4, -23, 32, -128, 1, -26, + -14, -128, 10, -77, -4, -128, 1, -50, -8, -77, -77, -77, + -23, -128, -50, -43, -33, -128, -43, -128, -128, -128, -43, -128, + -50, -128, -128, -128, 44, 15, 14, -128, 9, -128, 21, 0, + 29, -7, 18, -7, -7, -128, -33, -50, 14, -60, -60, -128, + -60, -128, -37, -128, -43, -128, -20, -128, -50, -128, -43, -77, + -26, -128, -60, -50, -60, -128, -77, -128, -3, -128, 14, -77, + -26, 11, 47, -77, -7, -77, 45, -43, -12, 14, 37, -60, + 22, -4, 5, -77, -14, -128, -10, -60, 22, -77, -12, -60, + -50, -128, -60, -128, -60, -128, -43, -128, -50, -128, -77, -50, + 27, -37, 33, -128, 4, -29, -4, -50, -20, -128, 6, -37, + -33, -128, -50, -128, 34, 15, -43, -128, -20, -50, -3, -37, + -37, -77, -77, -128, -43, -128, -128, -128, 4, -26, -26, 27, + 0, -128, -29, -60, 35, -26, 23, -128, -29, -77, 19, 14, + 28, -128, -16, -7, 31, -1, 17, 11, 60, 44, 8, 11, + 18, -128, -33, -60, -1, -128, -43, -128, -23, -128, -128, -128, + 59, 43, 35, 61, 37, -77, -77, -50, 116, 88, 98, 69, + 78, 53, 78, 40, 48, 7, 29, -18, -2, -14, 5, 12, + 65, 35, 31, -12, 33, -2, -6, -1, 44, -29, -14, -60, + -4, -43, -37, -128, 29, 18, 38, 51, 8, -128, -12, -37, + 115, 91, 113, 77, 89, 36, 60, 44, 49, 36, 27, 31, + 63, 30, 62, 14, 55, 49, 42, 0, 45, 17, -23, 1, + 30, -37, -50, -77, -8, -60, 9, -60, -12, -50, 13, 4, + 23, -6, 28, 13, 107, 78, 101, 73, 89, 46, 63, 17, + 34, -43, -6, 30, 67, 40, 77, 21, 53, 39, 38, 12, + -6, 5, 28, -2, 18, -43, 0, -128, -29, -77, 18, -128, + -2, -77, 39, 35, 38, 35, 50, 29, 100, 70, 94, 69, + 86, 50, 45, 38, 45, 12, 58, 64, 74, 36, 77, 45, + 78, 62, 8, -60, 38, 6, 21, 7, 8, -37, -1, -20, + 48, -37, 8, -10, 8, 13, 45, 39, 38, 22, 49, 25, + 94, 63, 87, 66, 84, -128, 29, 20, 55, 51, 80, 36, + 62, 30, 81, 72, 68, 37, 51, 27, 54, 22, 16, -29, + 4, 9, 57, 15, 35, -43, -77, -20, 4, 6, 37, -1, + 40, 31, 47, 14, 89, 68, 96, 83, 111, 96, 115, 87, + 99, 76, 105, 84, 105, 86, 113, 91, 108, 87, 110, 78, + 80, 46, 22, 74, 88, 72, 103, 86, 80, 68, 48, 24, + 68, 48, 55, 36, 108, 90, 90, 63, 83, 63, 87, 64, + 90, 92, 113, 88, 102, 79, 109, 83, 100, 89, 109, 60, + 56, 21, 75, 62, 81, 45, 63, 73, 93, 65, 94, 80, + 89, 81, 73, 3, 43, 60, 102, 70, 84, 67, 99, 74, + 78, 57, 79, 50, 93, 82, 98, 56, 77, 70, 91, 71, + 85, 82, 86, 13, 45, -18, 48, 40, 53, 28, 85, 60, + 65, 52, 86, 78, 76, 46, 73, 19, 35, 54, 75, 40, + 71, 60, 82, 37, 69, 42, 62, 40, 96, 70, 85, 77, + 70, 68, 103, 84, 94, 69, 81, -128, -128, -128, -43, -37, + 40, 2, 48, 45, 76, 37, 65, 16, 43, 18, 58, 20, + 27, 12, 71, 31, 53, 44, 88, 47, 50, 33, 39, 8, + 89, 57, 88, 69, 72, 63, 100, 68, 81, -77, -10, -128, + -128, -128, -128, -128, 13, -77, 8, 27, 60, 28, 41, -128, + -37, -128, 28, -43, -18, -128, 47, -37, 45, 27, 51, -29, + 15, 39, 52, 30, 49, -33, 65, 15, 76, 71, 90, 19, + 46, -128, -16, -128, -128, -128, -128, -128, -128, -128, -18, -128, + -20, -128, 32, -128, 21, -33, 45, -128, -128, -128, -12, -128, + -6, -14, 43, -128, -128, -128, -128, -128, 52, -18, 69, -43, + 78, 55, 42, -128, -29, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, 14, -128, -16, -128, -128, -128, 7, -128, + -128, -128, -128, -128, -128, -128, 12, -128, -128, -128, -128, -16, + 59, -50, 35, -128, 42, 0, 47, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -33, -128, -23, -128, + -128, -128, -23, -128, -128, -128, -128, -128, -128, -128, -33, -128, + -128, -128, -128, -128, -128, -128, -8, -128, 36, -50, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -37, -128, -128, -60, -10, -128, -128, -128, -128, -128, + -128, -128, 21, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -12, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -77, -128, -128, -128, -29, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -29, -128, -128, -128, -128, -128, -128, -128, -128, -128, -50, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, +}; diff --git a/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/no_micro_features_data.h b/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/no_micro_features_data.h new file mode 100644 index 000000000..8c1b6d5b5 --- /dev/null +++ b/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/no_micro_features_data.h @@ -0,0 +1,23 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_EXAMPLES_MICRO_SPEECH_MICRO_FEATURES_NO_MICRO_FEATURES_DATA_H_ +#define TENSORFLOW_LITE_MICRO_EXAMPLES_MICRO_SPEECH_MICRO_FEATURES_NO_MICRO_FEATURES_DATA_H_ + +extern const int g_no_micro_f9643d42_nohash_4_width; +extern const int g_no_micro_f9643d42_nohash_4_height; +extern const signed char g_no_micro_f9643d42_nohash_4_data[]; + +#endif // TENSORFLOW_LITE_MICRO_EXAMPLES_MICRO_SPEECH_MICRO_FEATURES_NO_MICRO_FEATURES_DATA_H_ diff --git a/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/yes_micro_features_data.cc b/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/yes_micro_features_data.cc new file mode 100644 index 000000000..951c01bf0 --- /dev/null +++ b/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/yes_micro_features_data.cc @@ -0,0 +1,188 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "yes_micro_features_data.h" + +// Golden test values for the expected spectrogram from a "yes" sample file +// speech_commands_test_set_v0.02/yes/f2e59fea_nohash_1.wav. + +const int g_yes_micro_f2e59fea_nohash_1_width = 40; +const int g_yes_micro_f2e59fea_nohash_1_height = 49; +const signed char g_yes_micro_f2e59fea_nohash_1_data[] = { + 116, 98, 118, 95, 106, 85, 101, 81, 67, -18, -33, -12, + -26, -128, 9, 34, 56, 45, 9, -12, 5, 30, 23, 28, + 0, -18, 0, -128, -60, -50, -50, -37, -60, -60, -50, -26, + -33, -50, -33, -50, 83, 61, 81, 55, 76, 61, 73, 64, + 38, -8, -37, -20, -18, -20, 48, 29, 52, 41, 55, 18, + 25, 37, 44, 37, 8, 15, -6, -60, -128, -50, -37, -37, + -18, -37, -26, -29, -37, -60, -50, -60, 95, 59, 52, -4, + 54, -18, 68, 43, 31, -18, -26, -33, -37, -29, 33, 7, + -3, 8, 26, 24, 36, 6, 36, 23, 14, 8, -29, -37, + -37, -37, -50, -50, -26, -8, -26, -37, -18, -37, -60, -77, + 50, 48, 83, 44, 56, -128, -33, -60, 1, -26, -60, -43, + -14, -23, -18, -43, -26, -33, 13, -77, -43, -77, -33, -37, + 16, -12, -37, -50, -50, -77, -20, -43, -60, -128, -60, -77, + -37, -77, -60, -128, 37, -10, 65, -7, 28, -128, 10, -77, + -37, -128, -77, -128, -77, -43, -128, -128, -77, -128, -128, -128, + -128, -128, -14, -128, -43, -50, -37, -77, -128, -128, -77, -43, + -29, -43, -20, -60, -37, -43, -50, -128, -77, -128, -18, -128, + -60, -128, -128, -128, -77, -128, -77, -128, -128, -128, -60, -37, + -20, -128, -60, -128, -128, -128, -60, -128, -77, -60, -128, -50, + -60, -128, -77, -128, -50, -60, -37, -60, -50, -77, -77, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -37, -128, + -128, -128, -128, -128, -77, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -77, -60, -128, -128, -50, -128, -50, -128, + -50, -128, -77, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -77, -128, -77, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -77, -128, -77, -128, -77, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -77, -128, -128, -128, + -128, -77, -50, -128, -128, -77, -77, -128, -128, -128, -50, -128, + 85, 43, 65, 53, 69, 60, 45, 3, 46, -12, 9, -23, + 32, -1, -128, -128, -128, -128, -1, 37, 38, 33, 43, 36, + 58, 70, 68, 39, 6, 10, 32, 6, 8, -23, -77, -128, + -29, -128, -77, -128, 101, 87, 102, 91, 110, 88, 101, 83, + 110, 95, 111, 83, 81, 84, 106, 90, 93, 82, 98, 91, + 108, 95, 118, 97, 118, 97, 116, 96, 113, 90, 110, 96, + 107, 85, 94, 66, 69, 36, 29, 0, 100, 60, 105, 68, + 92, 93, 113, 92, 107, 85, 107, 83, 104, 91, 105, 85, + 112, 88, 101, 80, 101, 79, 96, 80, 98, 80, 105, 83, + 98, 81, 103, 71, 100, 79, 83, 78, 91, 47, 50, 13, + 108, 81, 93, 78, 98, 76, 105, 76, 98, 40, 77, 72, + 81, 62, 93, 77, 96, 80, 98, 61, 97, 69, 88, 61, + 71, 56, 98, 68, 97, 72, 89, 51, 81, 61, 88, 75, + 86, 56, 48, 13, 71, 22, 84, 66, 76, -7, 48, 61, + 77, 62, 91, 65, 95, 74, 88, 59, 75, 58, 83, 55, + 87, 55, 76, 43, 76, -3, 56, 60, 79, 57, 71, 54, + 82, 33, 74, 71, 91, 45, 18, -7, 61, 56, 77, 41, + 73, 42, 82, 49, 59, 63, 82, 65, 66, 38, 83, 34, + 48, -8, 46, 20, 54, 33, 54, 6, 48, 16, 60, 37, + 58, 22, 58, 14, 65, 53, 75, -4, 42, 16, 16, -50, + 22, -128, 80, 54, 43, -50, 42, -128, -10, -77, 28, -29, + 68, 43, 73, 2, 25, -60, 47, 14, 45, 7, 66, 4, + 62, 37, 71, 7, 46, -10, 44, 22, 55, 53, 57, -29, + 26, -10, -3, -128, 38, -128, 46, -10, 16, -128, -10, -26, + 60, -7, 65, 38, 70, -60, 35, -8, 42, -29, 6, -128, + 34, -128, 36, -60, 44, -12, -2, -128, -7, -60, -60, -128, + -23, -128, 31, -33, 22, -77, -37, -43, -128, -128, 3, -128, + -23, -128, 17, -77, 43, -77, -7, -128, -20, -128, 17, -43, + 32, -128, -43, -128, -128, -77, 21, -128, -50, -128, -128, -128, + -128, -128, -128, -128, -37, -128, -16, -128, -50, -26, -6, -128, + -128, -128, -128, -128, -23, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -16, -128, 36, -7, 16, -128, -128, -128, -128, -128, + -77, -128, -37, -128, -50, -128, -128, -128, -128, -128, -18, -128, + 11, -128, -16, -77, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -26, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -20, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -50, -128, -77, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -77, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -1, -18, 5, -128, + 40, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, 4, -128, 63, 66, 75, -128, + 70, 60, 34, -128, -128, -128, -128, -128, -128, -128, -128, -128, + 87, 86, 95, 76, 91, 62, 72, -6, -50, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, 64, 83, 104, 70, + 98, 90, 111, 89, 109, 80, 71, -128, -128, -128, -128, -128, + -20, -6, 27, 33, 86, 88, 108, 75, 108, 76, 98, 64, + 75, 61, 71, 66, 85, -1, -77, -128, 46, 61, 92, 69, + 100, 93, 113, 80, 108, 93, 113, 91, 110, 80, 85, 15, + -33, -128, 12, -50, 34, 50, 70, 55, 84, 72, 108, 81, + 111, 88, 100, 80, 84, 73, 97, 86, 99, 65, 85, 43, + 96, 78, 107, 94, 118, 98, 115, 92, 118, 94, 111, 93, + 111, 86, 99, 52, 32, -16, 48, 31, 81, 74, 85, 64, + 78, 64, 98, 70, 110, 92, 96, 73, 100, 72, 94, 73, + 98, 76, 85, 67, 101, 83, 101, 83, 112, 89, 98, 85, + 105, 78, 98, 72, 102, 80, 95, 23, 19, -8, 52, 57, + 103, 91, 95, 65, 74, 8, 77, 49, 96, 76, 100, 87, + 105, 81, 94, 62, 94, 78, 81, 72, 99, 82, 101, 78, + 108, 65, 82, 70, 100, 63, 79, 58, 80, 59, 87, 48, + 50, 57, 93, 67, 86, 80, 103, 56, 77, 31, 81, 57, + 62, 41, 96, 85, 91, 71, 101, 76, 89, 78, 95, 76, + 96, 79, 103, 81, 103, 48, 70, 57, 88, 66, 84, 11, + 85, 67, 104, 37, 38, 67, 90, 54, 81, 62, 90, 52, + 78, -60, 54, -8, 68, 40, 55, 8, 77, 52, 66, 31, + 55, 13, 60, 26, 69, 42, 63, -29, 57, -128, -3, -128, + 3, -128, -29, -60, 52, -43, 63, 56, 86, 75, 95, 75, + 85, 63, 82, 10, 50, -128, 31, -77, 0, -77, -23, -128, + 12, -77, 51, -3, 58, -14, 44, 0, 48, 4, 53, 47, + 28, -128, -128, -128, -37, -128, -3, -128, 49, 61, 100, 90, + 117, 88, 107, 94, 112, 64, 96, 83, -128, -128, 7, -128, + -77, -128, -23, -128, -23, -128, 16, -37, 65, -8, 48, 20, + 14, -77, 57, -18, -43, -128, -128, -128, -128, -128, -128, -128, + 24, 12, 74, 76, 105, 76, 99, 80, 108, 79, 103, 85, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + 42, -128, -8, -128, -50, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -60, -128, -128, 5, 73, 53, 93, 70, 101, 73, + 94, 57, 86, 66, -18, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -50, -128, 36, -128, -128, -128, -128, -128, -20, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, 23, 37, + 75, 54, 97, 70, 83, 52, 85, 65, 7, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -43, -128, 23, -128, -43, -128, + -33, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -26, -37, 65, 33, 76, 37, 73, 50, 77, 47, + -12, -128, -128, -128, -128, -128, -128, -128, -128, -128, -7, -14, + -4, -128, -14, -128, 18, -60, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -26, -60, 71, 42, 68, 53, + 81, 49, 73, 36, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -18, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, 15, -26, + 44, -18, 59, 39, 57, 20, 62, 26, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, 49, -128, 30, 8, 69, 27, 62, 38, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -43, -128, 28, -37, 48, -10, + 48, 11, 74, 37, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -77, -128, 11, -128, -7, -60, -77, -4, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -8, -128, -50, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, -128, + -128, -128, -128, -128, +}; diff --git a/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/yes_micro_features_data.h b/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/yes_micro_features_data.h new file mode 100644 index 000000000..cd1ad1088 --- /dev/null +++ b/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_features/yes_micro_features_data.h @@ -0,0 +1,23 @@ +/* Copyright 2019 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifndef TENSORFLOW_LITE_MICRO_EXAMPLES_MICRO_SPEECH_MICRO_FEATURES_YES_MICRO_FEATURES_DATA_H_ +#define TENSORFLOW_LITE_MICRO_EXAMPLES_MICRO_SPEECH_MICRO_FEATURES_YES_MICRO_FEATURES_DATA_H_ + +extern const int g_yes_micro_f2e59fea_nohash_1_width; +extern const int g_yes_micro_f2e59fea_nohash_1_height; +extern const signed char g_yes_micro_f2e59fea_nohash_1_data[]; + +#endif // TENSORFLOW_LITE_MICRO_EXAMPLES_MICRO_SPEECH_MICRO_FEATURES_YES_MICRO_FEATURES_DATA_H_ diff --git a/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_speech.cc b/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_speech.cc new file mode 100644 index 000000000..5797c2310 --- /dev/null +++ b/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_speech.cc @@ -0,0 +1,116 @@ +/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "model.h" +#include "no_micro_features_data.h" +#include "yes_micro_features_data.h" +#include "micro_speech.h" +#include "tensorflow/lite/micro/micro_error_reporter.h" +#include "tensorflow/lite/micro/micro_interpreter.h" +#include "tensorflow/lite/micro/micro_mutable_op_resolver.h" +#include "tensorflow/lite/schema/schema_generated.h" +#include "tensorflow/lite/version.h" + +namespace { +tflite::MicroErrorReporter micro_error_reporter; +tflite::MicroMutableOpResolver<4> micro_op_resolver; +const tflite::Model* model = nullptr; +tflite::MicroInterpreter* interpreter = nullptr; +TfLiteTensor* model_input = nullptr; + +// In order to use optimized tensorflow lite kernels, a signed int8_t quantized +// model is preferred over the legacy unsigned model format. This means that +// throughout this project, input images must be converted from unisgned to +// signed format. The easiest and quickest way to convert from unsigned to +// signed 8-bit integers is to subtract 128 from the unsigned value to get a +// signed value. + +// An area of memory to use for input, output, and intermediate arrays. +// Create an area of memory to use for input, output, and intermediate arrays. +const int tensor_arena_size = 10 * 1024; +uint8_t tensor_arena[tensor_arena_size]; +} // namespace + +//TF_LITE_MICRO_TESTS_BEGIN + +//TF_LITE_MICRO_TEST(TestInvoke) { +extern "C" void speech_init(int8_t* input_data){ + // Set up logging. + + + // Map the model into a usable data structure. This doesn't involve any + // copying or parsing, it's a very lightweight operation. + const tflite::Model* model = ::tflite::GetModel(g_model); + + static tflite::MicroMutableOpResolver<4> micro_op_resolver; + micro_op_resolver.AddDepthwiseConv2D(); + micro_op_resolver.AddFullyConnected(); + micro_op_resolver.AddReshape(); + micro_op_resolver.AddSoftmax(); + +// Build an interpreter to run the model with. + static tflite::MicroInterpreter static_interpreter(model, micro_op_resolver, tensor_arena, + tensor_arena_size, + µ_error_reporter); + interpreter = &static_interpreter; + interpreter->AllocateTensors(); + + // Get information about the memory area to use for the model's input. + model_input = interpreter->input(0); +} + +extern "C" void speech_run(int8_t* input_data){ + // Copy a spectrogram created from a .wav audio file of someone saying "Yes", + // into the memory area used for the input. + const int8_t* yes_features_data = g_yes_micro_f2e59fea_nohash_1_data; + //const int8_t* yes_features_data = input_data; //input your own speech data + for (size_t i = 0; i < model_input->bytes; ++i) { + model_input->data.int8[i] = yes_features_data[i]; + } + + // Run the model on this input and make sure it succeeds. + TfLiteStatus invoke_status = interpreter->Invoke(); + TfLiteTensor* output = interpreter->output(0); + const int kSilenceIndex = 0; + const int kUnknownIndex = 1; + const int kYesIndex = 2; + const int kNoIndex = 3; + + // Make sure that the expected "Yes" score is higher than the other classes. + uint8_t silence_score = output->data.uint8[kSilenceIndex] + 128; + uint8_t unknown_score = output->data.uint8[kUnknownIndex] + 128; + uint8_t yes_score = output->data.int8[kYesIndex] + 128; + uint8_t no_score = output->data.int8[kNoIndex] + 128; + + // Run the model on this "No" input. + invoke_status = interpreter->Invoke(); + if (invoke_status != kTfLiteOk) { + TF_LITE_REPORT_ERROR(µ_error_reporter, "Invoke failed\n"); + } +// TF_LITE_MICRO_EXPECT_EQ(kTfLiteOk, invoke_status); + + // Get the output from the model, and make sure it's the expected size and + // type. + output = interpreter->output(0); + silence_score = output->data.int8[kSilenceIndex] + 128; + unknown_score = output->data.int8[kUnknownIndex] + 128; + yes_score = output->data.int8[kYesIndex] + 128; + no_score = output->data.int8[kNoIndex] + 128; + printf("speech test-> silence: %d unknown_score: %d yes_score: %d no_score: %d\n" , silence_score,unknown_score,yes_score,no_score); + + TF_LITE_REPORT_ERROR(µ_error_reporter, "Ran successfully\n"); +} + +//TF_LITE_MICRO_TESTS_END diff --git a/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_speech.h b/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_speech.h new file mode 100644 index 000000000..d9d422094 --- /dev/null +++ b/examples/tflitemicro_speech_detection/tflu_speech_yes_or_no/micro_speech.h @@ -0,0 +1,32 @@ +#ifndef TENSORFLOW_LITE_MICRO_EXAMPLES_SPEECH_EXPERIMENTAL_MAIN_FUNCTIONS_H_ +#define TENSORFLOW_LITE_MICRO_EXAMPLES_SPEECH_EXPERIMENTAL_MAIN_FUNCTIONS_H_ +// Initializes all data needed for the example. The name is important, and needs +// to be setup() for Arduino compatibility. + +#include "tensorflow/lite/c/common.h" +/* +#ifdef __cplusplus +extern "C" +{ +#endif +void speech_init(void); +#ifdef __cplusplus +} +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif +void speech_run(uint8_t*); + +#ifdef __cplusplus +} +#endif +*/ + // Runs one iteration of data gathering and inference. This should be called +// repeatedly from the application code. The name needs to be loop() for Arduino +// compatibility. +//extern "C" int person_detect(); + +#endif // TENSORFLOW_LITE_MICRO_EXAMPLES_PERSON_DETECTION_EXPERIMENTAL_MAIN_FUNCTIONS_H_ \ No newline at end of file diff --git a/kernel/core/include/tos_timer.h b/kernel/core/include/tos_timer.h index 5ad3b3aea..bca901c5d 100644 --- a/kernel/core/include/tos_timer.h +++ b/kernel/core/include/tos_timer.h @@ -177,13 +177,13 @@ __API__ k_err_t tos_timer_period_change(k_timer_t *tmr, k_tick_t period); * * @return None */ -__KNL__ void timer_update(void); +__KNL__ void soft_timer_update(void); #endif -__KNL__ k_err_t timer_init(void); +__KNL__ k_err_t soft_timer_init(void); -__KNL__ k_tick_t timer_next_expires_get(void); +__KNL__ k_tick_t soft_timer_next_expires_get(void); #endif diff --git a/kernel/core/tos_sys.c b/kernel/core/tos_sys.c index 89bf904be..8dd8a0c44 100644 --- a/kernel/core/tos_sys.c +++ b/kernel/core/tos_sys.c @@ -42,7 +42,7 @@ __API__ k_err_t tos_knl_init(void) } #if TOS_CFG_TIMER_EN > 0 - err = timer_init(); + err = soft_timer_init(); if (err != K_ERR_NONE) { return err; } @@ -187,7 +187,7 @@ __KNL__ k_tick_t knl_next_expires_get(void) tick_next_expires = tick_next_expires_get(); #if TOS_CFG_TIMER_EN > 0u - timer_next_expires = timer_next_expires_get(); + timer_next_expires = soft_timer_next_expires_get(); #endif #if TOS_CFG_TIMER_EN > 0u diff --git a/kernel/core/tos_tick.c b/kernel/core/tos_tick.c index 8fb4bfc52..49feeb90f 100644 --- a/kernel/core/tos_tick.c +++ b/kernel/core/tos_tick.c @@ -139,7 +139,7 @@ __API__ void tos_tick_handler(void) tick_update((k_tick_t)1u); #if TOS_CFG_TIMER_EN > 0u && TOS_CFG_TIMER_AS_PROC > 0u - timer_update(); + soft_timer_update(); #endif #if TOS_CFG_ROUND_ROBIN_EN > 0u diff --git a/kernel/core/tos_timer.c b/kernel/core/tos_timer.c index 4e71f9ca5..71d17442c 100644 --- a/kernel/core/tos_timer.c +++ b/kernel/core/tos_timer.c @@ -253,7 +253,7 @@ __API__ k_err_t tos_timer_period_change(k_timer_t *tmr, k_tick_t period) return timer_change(tmr, period, TIMER_CHANGE_TYPE_PERIOD); } -__KNL__ k_tick_t timer_next_expires_get(void) +__KNL__ k_tick_t soft_timer_next_expires_get(void) { TOS_CPU_CPSR_ALLOC(); k_tick_t next_expires; @@ -274,7 +274,7 @@ __KNL__ k_tick_t timer_next_expires_get(void) #if TOS_CFG_TIMER_AS_PROC > 0u -__KNL__ void timer_update(void) +__KNL__ void soft_timer_update(void) { k_timer_t *tmr, *tmp; @@ -314,7 +314,7 @@ __STATIC__ void timer_task_entry(void *arg) arg = arg; // make compiler happy while (K_TRUE) { - next_expires = timer_next_expires_get(); + next_expires = soft_timer_next_expires_get(); if (next_expires == TOS_TIME_FOREVER) { tos_task_suspend(K_NULL); } else if (next_expires > (k_tick_t)0u) { @@ -347,13 +347,13 @@ __STATIC__ void timer_task_entry(void *arg) #endif -__KNL__ k_err_t timer_init(void) +__KNL__ k_err_t soft_timer_init(void) { #if TOS_CFG_TIMER_AS_PROC > 0u return K_ERR_NONE; #else return tos_task_create(&k_timer_task, - "timer", + "soft_timer", timer_task_entry, K_NULL, k_timer_task_prio, diff --git a/kernel/pm/tos_tickless.c b/kernel/pm/tos_tickless.c index 4446eacd5..90d21d540 100644 --- a/kernel/pm/tos_tickless.c +++ b/kernel/pm/tos_tickless.c @@ -111,7 +111,7 @@ __STATIC__ void tickless_tick_fix(k_tick_t tick_sleep) tick_update(tick_sleep); #if TOS_CFG_TIMER_EN > 0u && TOS_CFG_TIMER_AS_PROC > 0u - timer_update(); + soft_timer_update(); #endif tickless_tick_resume(); diff --git a/osal/cmsis_os/cmsis_os2.c b/osal/cmsis_os/cmsis_os2.c index 3890fb723..a6ea54418 100644 --- a/osal/cmsis_os/cmsis_os2.c +++ b/osal/cmsis_os/cmsis_os2.c @@ -156,7 +156,7 @@ osThreadId_t osThreadNew(osThreadFunc_t func, k_err_t err; uint32_t stack_size = K_TASK_STK_SIZE_MIN; k_task_t* taskId = NULL; - k_prio_t prio; + k_prio_t prio = osPriorityNormal; if (attr && func) { if (attr->priority != osPriorityNone) { diff --git a/platform/hal/st/stm32h7xx/src/tos_hal_uart.c b/platform/hal/st/stm32h7xx/src/tos_hal_uart.c index 755a2a0d3..7d4830a28 100644 --- a/platform/hal/st/stm32h7xx/src/tos_hal_uart.c +++ b/platform/hal/st/stm32h7xx/src/tos_hal_uart.c @@ -12,23 +12,11 @@ __API__ int tos_hal_uart_init(hal_uart_t *uart, hal_uart_port_t port) // uart->private_uart = &hlpuart1; // MX_LPUART1_UART_Init(); } else if (port == HAL_UART_PORT_1) { -// uart->private_uart = &huart1; -// MX_USART1_UART_Init(); + uart->private_uart = &huart1; + MX_USART1_UART_Init(); } else if (port == HAL_UART_PORT_2) { uart->private_uart = &huart2; MX_USART2_UART_Init(); - } else if (port == HAL_UART_PORT_3) { -// uart->private_uart = &huart3; -// MX_USART3_UART_Init(); - } else if (port == HAL_UART_PORT_4) { - uart->private_uart = &huart4; - MX_UART4_Init(); - } else if (port == HAL_UART_PORT_5) { - uart->private_uart = &huart5; - MX_UART5_Init(); - } else if (port == HAL_UART_PORT_6) { - uart->private_uart = &huart6; - MX_USART6_UART_Init(); } return 0; diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/arm_common_tables.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/arm_common_tables.h new file mode 100644 index 000000000..6a4337f7e --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,378 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + extern const uint16_t armBitRevTable[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) + extern const float32_t twiddleCoef_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + extern const float32_t twiddleCoef_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) + extern const float32_t twiddleCoef_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + extern const float32_t twiddleCoef_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) + extern const float32_t twiddleCoef_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + extern const float32_t twiddleCoef_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) + extern const float32_t twiddleCoef_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + extern const float32_t twiddleCoef_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + extern const float32_t twiddleCoef_4096[8192]; + #define twiddleCoef twiddleCoef_4096 + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) + extern const q31_t twiddleCoef_16_q31[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + extern const q31_t twiddleCoef_32_q31[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) + extern const q31_t twiddleCoef_64_q31[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + extern const q31_t twiddleCoef_128_q31[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) + extern const q31_t twiddleCoef_256_q31[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + extern const q31_t twiddleCoef_512_q31[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) + extern const q31_t twiddleCoef_1024_q31[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + extern const q31_t twiddleCoef_2048_q31[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) + extern const q31_t twiddleCoef_4096_q31[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) + extern const q15_t twiddleCoef_16_q15[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + extern const q15_t twiddleCoef_32_q15[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) + extern const q15_t twiddleCoef_64_q15[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + extern const q15_t twiddleCoef_128_q15[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) + extern const q15_t twiddleCoef_256_q15[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + extern const q15_t twiddleCoef_512_q15[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) + extern const q15_t twiddleCoef_1024_q15[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + extern const q15_t twiddleCoef_2048_q15[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) + extern const q15_t twiddleCoef_4096_q15[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32) + extern const float32_t twiddleCoef_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64) + extern const float32_t twiddleCoef_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128) + extern const float32_t twiddleCoef_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256) + extern const float32_t twiddleCoef_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512) + extern const float32_t twiddleCoef_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024) + extern const float32_t twiddleCoef_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048) + extern const float32_t twiddleCoef_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096) + extern const float32_t twiddleCoef_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + /* floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16) + #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) + extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32) + #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) + extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64) + #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128) + #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) + extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256) + #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) + extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512) + #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) + extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024) + #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) + extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048) + #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) + extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096) + #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* fixed-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16) + #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32) + #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64) + #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128) + #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256) + #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512) + #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024) + #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048) + #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096) + #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) + extern const float32_t realCoefA[8192]; + extern const float32_t realCoefB[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31) + extern const q31_t realCoefAQ31[8192]; + extern const q31_t realCoefBQ31[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) + extern const q15_t realCoefAQ15[8192]; + extern const q15_t realCoefBQ15[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + extern const float32_t Weights_128[256]; + extern const float32_t cos_factors_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) + extern const float32_t Weights_512[1024]; + extern const float32_t cos_factors_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) + extern const float32_t Weights_2048[4096]; + extern const float32_t cos_factors_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) + extern const float32_t Weights_8192[16384]; + extern const float32_t cos_factors_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + extern const q15_t WeightsQ15_128[256]; + extern const q15_t cos_factorsQ15_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + extern const q15_t WeightsQ15_512[1024]; + extern const q15_t cos_factorsQ15_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + extern const q15_t WeightsQ15_2048[4096]; + extern const q15_t cos_factorsQ15_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + extern const q15_t WeightsQ15_8192[16384]; + extern const q15_t cos_factorsQ15_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + extern const q31_t WeightsQ31_128[256]; + extern const q31_t cos_factorsQ31_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + extern const q31_t WeightsQ31_512[1024]; + extern const q31_t cos_factorsQ31_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + extern const q31_t WeightsQ31_2048[4096]; + extern const q31_t cos_factorsQ31_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + extern const q31_t WeightsQ31_8192[16384]; + extern const q31_t cos_factorsQ31_8192[8192]; + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) + extern const q15_t armRecipTableQ15[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) + extern const q31_t armRecipTableQ31[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + /* Tables for Fast Math Sine and Cosine */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) + extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) + extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) + extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */ + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/arm_const_structs.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/arm_const_structs.h new file mode 100644 index 000000000..80a3e8bbe --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/arm_math.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/arm_math.h new file mode 100644 index 000000000..eb37f8223 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/arm_math.h @@ -0,0 +1,7361 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.6.0 + * @date 18. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transform functions + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP\\Projects\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_LOOPUNROLL: + * + * Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions + * + * - ARM_MATH_NEON: + * + * Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions. + * It is not enabled by default when Neon is available because performances are + * dependent on the compiler and target architecture. + * + * - ARM_MATH_NEON_EXPERIMENTAL: + * + * Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of + * of some DSP functions. Experimental Neon versions currently do not have better + * performances than the scalar versions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |---------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP\\DSP_Lib_TestSuite | DSP_Lib test suite | + * |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP\\Include | DSP_Lib include files | + * |\b CMSIS\\DSP\\Lib | DSP_Lib binaries | + * |\b CMSIS\\DSP\\Projects | Projects to rebuild DSP_Lib binaries | + * |\b CMSIS\\DSP\\Source | DSP_Lib source files | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + *
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * 
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + *
+ *     pData[i*numCols + j]
+ * 
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15() + * for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ * 
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + *
+ *     ARM_MATH_SIZE_MISMATCH
+ * 
+ * Otherwise the functions return + *
+ *     ARM_MATH_SUCCESS
+ * 
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + *
+ *     ARM_MATH_MATRIX_CHECK
+ * 
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ + +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ + + +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wsign-conversion" + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + + +/* Included for instrinsics definitions */ +#if !defined ( _MSC_VER ) +#include "cmsis_compiler.h" +#else +#include +#define __STATIC_FORCEINLINE static __forceinline +#define __ALIGNED(x) __declspec(align(x)) +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#endif + +#include "string.h" +#include "math.h" +#include "float.h" + +/* evaluate ARM DSP feature */ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define ARM_MATH_DSP 1 +#endif + +#if defined(__ARM_NEON) +#include +#endif + + +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + +/** + @brief definition to read/write two 16 bit values. + @deprecated + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __un(aligned) int32_t +#elif defined(_MSC_VER ) + #define __SIMD32_TYPE int32_t +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr)) +#define __SIMD64(addr) (*( int64_t **) & (addr)) + +/* SIMD replacement */ + + +/** + @brief Read 2 Q15 from Q15 pointer. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2 ( + q15_t * pQ15) +{ + q31_t val; + + memcpy (&val, pQ15, 4); + + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_ia ( + q15_t ** pQ15) +{ + q31_t val; + + memcpy (&val, *pQ15, 4); + *pQ15 += 2; + + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_da ( + q15_t ** pQ15) +{ + q31_t val; + + memcpy (&val, *pQ15, 4); + *pQ15 -= 2; + + return (val); +} + +/** + @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2_ia ( + q15_t ** pQ15, + q31_t value) +{ + q31_t val = value; + + memcpy (*pQ15, &val, 4); + *pQ15 += 2; +} + +/** + @brief Write 2 Q15 to Q15 pointer. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2 ( + q15_t * pQ15, + q31_t value) +{ + q31_t val = value; + + memcpy (pQ15, &val, 4); +} + + +/** + @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_ia ( + q7_t ** pQ7) +{ + q31_t val; + + memcpy (&val, *pQ7, 4); + *pQ7 += 4; + + return (val); +} + +/** + @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_da ( + q7_t ** pQ7) +{ + q31_t val; + + memcpy (&val, *pQ7, 4); + *pQ7 -= 4; + + return (val); +} + +/** + @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q7x4_ia ( + q7_t ** pQ7, + q31_t value) +{ + q31_t val = value; + + memcpy (*pQ7, &val, 4); + *pQ7 += 4; +} + +/* + +Normally those kind of definitions are in a compiler file +in Core or Core_A. + +But for MSVC compiler it is a bit special. The goal is very specific +to CMSIS-DSP and only to allow the use of this library from other +systems like Python or Matlab. + +MSVC is not going to be used to cross-compile to ARM. So, having a MSVC +compiler file in Core or Core_A would not make sense. + +*/ +#if defined ( _MSC_VER ) + __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#ifndef ARM_MATH_DSP + /** + * @brief definition to pack two 16 bit values. + */ + #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) +#endif + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + __STATIC_FORCEINLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + __STATIC_FORCEINLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + __STATIC_FORCEINLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y) ) ); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + const q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + const q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + +#if defined(ARM_MATH_NEON) + +static inline float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x) +{ + float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN)); + float32x4_t e = vrsqrteq_f32(x1); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + return vmulq_f32(x, e); +} + +static inline int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec) +{ + float32x4_t tempF; + int32x4_t tempHI,tempLO; + + tempLO = vmovl_s16(vget_low_s16(vec)); + tempF = vcvtq_n_f32_s32(tempLO,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempLO = vcvtq_n_s32_f32(tempF,15); + + tempHI = vmovl_s16(vget_high_s16(vec)); + tempF = vcvtq_n_f32_s32(tempHI,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempHI = vcvtq_n_s32_f32(tempF,15); + + return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI))); +} + +static inline int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec) +{ + float32x4_t temp; + + temp = vcvtq_n_f32_s32(vec,31); + temp = __arm_vec_sqrt_f32_neon(temp); + return(vcvtq_n_s32_f32(temp,31)); +} + +#endif + +/* + * @brief C custom defined intrinsic functions + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 + */ + __STATIC_FORCEINLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 + */ + __STATIC_FORCEINLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 + */ + __STATIC_FORCEINLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 + */ + __STATIC_FORCEINLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 + */ + __STATIC_FORCEINLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 + */ + __STATIC_FORCEINLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX + */ + __STATIC_FORCEINLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX + */ + __STATIC_FORCEINLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX + */ + __STATIC_FORCEINLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX + */ + __STATIC_FORCEINLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX + */ + __STATIC_FORCEINLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX + */ + __STATIC_FORCEINLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD + */ + __STATIC_FORCEINLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB + */ + __STATIC_FORCEINLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD + */ + __STATIC_FORCEINLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX + */ + __STATIC_FORCEINLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX + */ + __STATIC_FORCEINLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD + */ + __STATIC_FORCEINLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX + */ + __STATIC_FORCEINLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD + */ + __STATIC_FORCEINLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD + */ + __STATIC_FORCEINLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 + */ + __STATIC_FORCEINLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA + */ + __STATIC_FORCEINLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter (fast version). + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns either + * ARM_MATH_SUCCESS if initialization was successful or + * ARM_MATH_ARGUMENT_ERROR if numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter (fast version). + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +arm_status arm_rfft_32_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_64_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_128_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_256_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_512_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_1024_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_2048_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + +arm_status arm_rfft_4096_fast_init_f32 ( arm_rfft_fast_instance_f32 * S ); + + + void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + const float32_t *pTwiddle; /**< points to the twiddle factor table. */ + const float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + const float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + const q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + const q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + +/** + @brief Instance structure for floating-point FIR decimator. + */ +typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + */ +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + */ +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + +#if defined(ARM_MATH_NEON) +void arm_biquad_cascade_df2T_compute_coefs_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs); +#endif + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + +/** + @brief Correlation of Q15 sequences + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +*/ +void arm_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ +void arm_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ +void arm_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + *
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+   * 
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return processed output sample. + */ + __STATIC_FORCEINLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + +/** + @brief Process function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ +__STATIC_FORCEINLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + +/** + @brief Process function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ +__STATIC_FORCEINLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @return none + */ + __STATIC_FORCEINLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + +/** + @brief Clarke transform for Q31 version + @param[in] Ia input three-phase coordinate a + @param[in] Ib input three-phase coordinate b + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + +/** + @brief Inverse Clarke transform for Q31 version + @param[in] Ialpha input two-phase orthogonal vector axis alpha + @param[in] Ibeta input two-phase orthogonal vector axis beta + @param[out] pIa points to output three-phase coordinate a + @param[out] pIb points to output three-phase coordinate b + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + * + * The function implements the forward Park transform. + * + */ + __STATIC_FORCEINLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + +/** + @brief Park transform for Q31 version + @param[in] Ialpha input two-phase vector coordinate alpha + @param[in] Ibeta input two-phase vector coordinate beta + @param[out] pId points to output rotor reference frame d + @param[out] pIq points to output rotor reference frame q + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + +/** + @brief Inverse Park transform for Q31 version + @param[in] Id input coordinate of rotor reference frame d + @param[in] Iq input coordinate of rotor reference frame q + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + *
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * 
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + __STATIC_FORCEINLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + __STATIC_FORCEINLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + __STATIC_FORCEINLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + __STATIC_FORCEINLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + *
+   *      x1 = x0 - f(x0)/f'(x0)
+   * 
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + *
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * 
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +__STATIC_FORCEINLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + *pOut = __sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); + #else + *pOut = sqrtf(in); + #endif + +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @brief Vector Floating-point square root function. + * @param[in] pIn input vector. + * @param[out] pOut vector of square roots of input elements. + * @param[in] len length of input vector. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + void arm_vsqrt_f32( + float32_t * pIn, + float32_t * pOut, + uint16_t len); + + void arm_vsqrt_q31( + q31_t * pIn, + q31_t * pOut, + uint16_t len); + + void arm_vsqrt_q15( + q15_t * pIn, + q15_t * pOut, + uint16_t len); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset; + int32_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q15_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q7_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + *
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * 
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + *
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * 
+ * \par + * The interpolated output point is computed as: + *
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * 
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_armcc.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 000000000..59f173ac7 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_armclang.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 000000000..e917f357a --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_armclang_ltm.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 000000000..feec32405 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_compiler.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 000000000..adbf296f1 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_gcc.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 000000000..3ddcc58b6 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_iccarm.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 000000000..12d68fd9a --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_version.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_version.h new file mode 100644 index 000000000..f2e274662 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_armv81mml.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_armv81mml.h new file mode 100644 index 000000000..8441e57fb --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_armv8mbl.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 000000000..344dca514 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_armv8mml.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_armv8mml.h new file mode 100644 index 000000000..5ddb8aeda --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm0.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm0.h new file mode 100644 index 000000000..cafae5a0a --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm0plus.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm0plus.h new file mode 100644 index 000000000..d104965db --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm1.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm1.h new file mode 100644 index 000000000..76b456974 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm23.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm23.h new file mode 100644 index 000000000..b79c6af0b --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm23.h @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm3.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm3.h new file mode 100644 index 000000000..8157ca782 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm33.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm33.h new file mode 100644 index 000000000..7fed59a88 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm35p.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm35p.h new file mode 100644 index 000000000..5579c8230 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm4.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm4.h new file mode 100644 index 000000000..12c023b80 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm7.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm7.h new file mode 100644 index 000000000..d1b2f2ca2 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + register uint32_t ccsidr; + register uint32_t sets; + register uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_dsp.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_dsp.h new file mode 100644 index 000000000..6c21a47d8 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_dsp.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file cmsis_xcc.h + * @brief CMSIS DSP Core Peripheral Access Layer Header File + * @version V1.0 + * @date 20. January 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CORE_DSP_H_GENERIC +#define __CORE_DSP_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +#define __STATIC_INLINE static inline + +#define __BKPT(value) do {} while(0) +#define __NOP() do {} while(0) + +#define NVIC_SetPriorityGrouping(value) do {} while(0) +#define NVIC_GetPriorityGrouping() do {} while(0) +#define NVIC_EnableIRQ(value) do {} while(0) +#define NVIC_GetEnableIRQ(value) do {} while(0) +#define NVIC_DisableIRQ(value) do {} while(0) +#define NVIC_GetPendingIRQ(value) do {} while(0) +#define NVIC_SetPendingIRQ(value) do {} while(0) +#define NVIC_ClearPendingIRQ(value) do {} while(0) +#define NVIC_GetActive(value) do {} while(0) + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_DSP_H_GENERIC */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_sc000.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_sc000.h new file mode 100644 index 000000000..cf92577b6 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_sc000.h @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_sc300.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_sc300.h new file mode 100644 index 000000000..40f3af81b --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_sc300.h @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_star.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_star.h new file mode 100644 index 000000000..01ba0f3a6 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/core_star.h @@ -0,0 +1,3598 @@ +/**************************************************************************//** + * @file core_star.h + * @brief CMSIS ArmChina STAR Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 13. Oct 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. + * Copyright (c) 2018-2021 ArmChina. + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_STAR_H_GENERIC +#define __CORE_STAR_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_STAR + @{ + */ + +#include "cmsis_version.h" + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_STAR_H_DEPENDANT +#define __CORE_STAR_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __STAR_REV + #define __STAR_REV 0x0000U + #warning "__STAR_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_STAR */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED_ADD1[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +typedef struct +{ + __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ + __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ +}EMSS_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ +#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ + +#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ +#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ + + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache line Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ +#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ + +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean line by Set-way Register Definitions */ +#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ +#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ + +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ +#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ + +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* ArmChina: Implementation Defined */ +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ +#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ +#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ +#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ +#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ +#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/** + \brief Software Reset + \details Initiates a system reset request to reset the CPU. + */ +__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses including + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ + SCB_AIRCR_SYSRESETREQ_Msk ); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_STAR_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/mpu_armv7.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/mpu_armv7.h new file mode 100644 index 000000000..66ef59b4a --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/mpu_armv8.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/mpu_armv8.h new file mode 100644 index 000000000..0041d4dc6 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/tz_context.h b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/tz_context.h new file mode 100644 index 000000000..0d09749f3 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/platform/vendor_bsp/MindMotion/MM32F527/armgcc/linker/mm32f5277e_flash.ld b/platform/vendor_bsp/MindMotion/MM32F527/armgcc/linker/mm32f5277e_flash.ld new file mode 100644 index 000000000..b46b1dc4e --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/armgcc/linker/mm32f5277e_flash.ld @@ -0,0 +1,298 @@ + + +/* + *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- + Flash Configuration + Flash Base Address <0x0-0xFFFFFFFF:8> + Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x08000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- + RAM Configuration + RAM Base Address <0x0-0xFFFFFFFF:8> + RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x30000000; +__RAM_SIZE = 0x0001C000; + +/*--------------------- Stack / Heap Configuration ---------------------------- + Stack / Heap Configuration + Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00001000; +__HEAP_SIZE = 0x00001000; + +/* + *-------------------- <<< end of configuration section >>> ------------------- + */ + +/* ARMv8-M stack sealing: + to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 + */ +__STACKSEAL_SIZE = 0; + + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __StackSeal (only if ARMv8-M stack sealing is used) + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + _stext = .; + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option ��--section-start�� or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + _etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + _sstack = .; + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + _estack = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* ARMv8-M stack sealing: + to use ARMv8-M stack sealing uncomment '.stackseal' section + */ +/* + .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : + { + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > RAM +*/ + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/platform/vendor_bsp/MindMotion/MM32F527/armgcc/startup_mm32f5277e.S b/platform/vendor_bsp/MindMotion/MM32F527/armgcc/startup_mm32f5277e.S new file mode 100644 index 000000000..e925e6212 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/armgcc/startup_mm32f5277e.S @@ -0,0 +1,348 @@ +/* ------------------------------------------------------------------------- */ +/* @file: startup_MM32F5277.S */ +/* @purpose: CMSIS Star-MC1 Core Device Startup File */ +/* */ +/* @version: 1.0 */ +/* @date: 2022-07-01 */ +/* @build: b220701 */ +/* ------------------------------------------------------------------------- */ +/* */ +/* Copyright 2022 MindMotion */ +/* All rights reserved. */ +/* */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/*****************************************************************************/ +/* Version: ICC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv8-m.main + + #define __INITIAL_SP __StackTop + #define __STACK_LIMIT __StackLimit + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define __STACK_SEAL __StackSeal + #endif + .section .vectors + .align 2 + .globl __Vectors + .globl __Vectors_End + .globl __Vectors_Size +__Vectors: + .long __INITIAL_SP /* Initial Stack Pointer */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + .long WWDG_IWDG_IRQHandler /* 0 Watchdog interrupt (IWDG is EXTI21) */ + .long PVD_IRQHandler /* 1 Supply Voltage Detect (PVD) Interrupt (EXTI16) */ + .long BKP_TAMPER_IRQHandler /* 2 BKP intrusion detection interrupted */ + .long RTC_IRQHandler /* 3 RTC global interrupt */ + .long FLASH_IRQHandler /* 4 Flash Global Interrupt */ + .long RCC_CRS_IRQHandler /* 5 RCC and CRS global interrupt */ + .long EXTI0_IRQHandler /* 6 EXTI line 0 interrupt */ + .long EXTI1_IRQHandler /* 7 EXTI line 1 interrupt */ + .long EXTI2_IRQHandler /* 8 EXTI line 2 interrupt */ + .long EXTI3_IRQHandler /* 9 EXTI line 3 interrupt */ + .long EXTI4_IRQHandler /* 10 EXTI line 4 interrupt */ + .long DMA1_CH1_IRQHandler /* 11 DMA1 channel 1 global interrupt */ + .long DMA1_CH2_IRQHandler /* 12 DMA1 channel 2 global interrupt */ + .long DMA1_CH3_IRQHandler /* 13 DMA1 channel 3 global interrupt */ + .long DMA1_CH4_IRQHandler /* 14 DMA1 channel 4 global interrupt */ + .long DMA1_CH5_IRQHandler /* 15 DMA1 channel 5 global interrupt */ + .long DMA1_CH6_IRQHandler /* 16 DMA1 channel 6 global interrupt */ + .long DMA1_CH7_IRQHandler /* 17 DMA1 channel 7 global interrupt */ + .long ADC1_2_IRQHandler /* 18 ADC1/2 global interrupt */ + .long 0 /* 19 Reserved */ + .long DMA1_CH8_IRQHandler /* 20 DMA1 channel 8 global interrupt */ + .long FlexCAN1_IRQHandler /* 21 FlexCAN1 global interrupt */ + .long 0 /* 22 Reserved */ + .long EXTI9_5_IRQHandler /* 23 EXTI line[9:5] interrupt */ + .long TIM1_BRK_IRQHandler /* 24 TIM1 brake interrupt */ + .long TIM1_UP_IRQHandler /* 25 TIM1 update interrupted */ + .long TIM1_TRG_COM_IRQHandler /* 26 TIM1 trigger/COM interrupt */ + .long TIM1_CC_IRQHandler /* 27 TIM1 capture compare interrupt */ + .long TIM2_IRQHandler /* 28 TIM2 global interrupt */ + .long TIM3_IRQHandler /* 29 TIM3 global interrupt */ + .long TIM4_IRQHandler /* 30 TIM4 global interrupt */ + .long I2C1_IRQHandler /* 31 I2C1 global interrupt */ + .long 0 /* 32 Reserved */ + .long I2C2_IRQHandler /* 33 I2C2 global interrupt */ + .long 0 /* 34 Reserved */ + .long SPI1_IRQHandler /* 35 SPI1 global interrupt */ + .long SPI2_IRQHandler /* 36 SPI2 global interrupt */ + .long UART1_IRQHandler /* 37 UART1 global interrupt */ + .long UART2_IRQHandler /* 38 UART2 global interrupt */ + .long UART3_IRQHandler /* 39 UART3 global interrupt */ + .long EXTI15_10_IRQHandler /* 40 Interrupt on EXTI line[15:10] */ + .long RTC_ALR_IRQHandler /* 41 RTC Alarm Interrupt (EXTI17) */ + .long USB_WKUP_IRQHandler /* 42 USB Wakeup Interrupt (EXTI18) */ + .long TIM8_BRK_IRQHandler /* 43 TIM8 brake interrupt */ + .long TIM8_UP_IRQHandler /* 44 TIM8 update interrupted */ + .long TIM8_TRG_COM_IRQHandler /* 45 TIM8 trigger/COM interrupt */ + .long TIM8_CC_IRQHandler /* 46 TIM8 capture compare interrupt */ + .long 0 /* 47 Reserved */ + .long 0 /* 48 Reserved */ + .long 0 /* 49 Reserved */ + .long TIM5_IRQHandler /* 50 TIM5 global interrupt */ + .long SPI3_IRQHandler /* 51 SPI3 global interrupt */ + .long UART4_IRQHandler /* 52 UART4 global interrupt */ + .long UART5_IRQHandler /* 53 UART5 global interrupt */ + .long TIM6_IRQHandler /* 54 TIM6 global interrupt */ + .long TIM7_IRQHandler /* 55 TIM7 global interrupt */ + .long DMA2_CH1_IRQHandler /* 56 DMA2 channel 1 global interrupt */ + .long DMA2_CH2_IRQHandler /* 57 DMA2 channel 2 global interrupt */ + .long DMA2_CH3_IRQHandler /* 58 DMA2 channel 3 global interrupt */ + .long DMA2_CH4_IRQHandler /* 59 DMA2 channel 4 global interrupt */ + .long DMA2_CH5_IRQHandler /* 60 DMA2 channel 5 global interrupt */ + .long ENET_IRQHandler /* 61 ENET global interrupt */ + .long ENET_WKUP_IRQHandler /* 62 ENET wake-up interrupt (EXTI25) */ + .long 0 /* 63 Reserved */ + .long COMP_IRQHandler /* 64 Comparator 1/2/3 Global Interrupts (EXTI19/20/24) */ + .long FlexCAN2_IRQHandler /* 65 FLexCAN2 global interrupt */ + .long 0 /* 66 Reserved */ + .long USB_FS_IRQHandler /* 67 USB OTG global interrupt */ + .long DMA2_CH6_IRQHandler /* 68 DMA2 channel 6 global interrupt */ + .long DMA2_CH7_IRQHandler /* 69 DMA2 channel 7 global interrupt */ + .long DMA2_CH8_IRQHandler /* 70 DMA2 channel 8 global interrupt */ + .long UART6_IRQHandler /* 71 UART6 global interrupt */ + .long 0 /* 72 Reserved */ + .long 0 /* 73 Reserved */ + .long 0 /* 74 Reserved */ + .long 0 /* 75 Reserved */ + .long 0 /* 76 Reserved */ + .long 0 /* 77 Reserved */ + .long 0 /* 78 Reserved */ + .long 0 /* 79 Reserved */ + .long 0 /* 80 Reserved */ + .long 0 /* 81 Reserved */ + .long UART7_IRQHandler /* 82 UART7 global interrupt */ + .long 0 /* 83 Reserved */ + .long 0 /* 84 Reserved */ + .long 0 /* 85 Reserved */ + .long 0 /* 86 Reserved */ + .long 0 /* 87 Reserved */ + .long 0 /* 88 Reserved */ + .long 0 /* 89 Reserved */ + .long 0 /* 90 Reserved */ + .long 0 /* 91 Reserved */ + .long 0 /* 92 Reserved */ + .long 0 /* 93 Reserved */ + .long 0 /* 94 Reserved */ + .long QSPI_IRQHandler /* 95 QSPI global interrupt */ + .long 0 /* 96 Reserved */ + .long 0 /* 97 Reserved */ + .long 0 /* 98 Reserved */ + .long 0 /* 99 Reserved */ + .long 0 /* 100 Reserved */ + .long 0 /* 101 Reserved */ + .long LPTIM_IRQHandler /* 102 LPTIM global interrupt (EXTI22) */ + .long 0 /* 103 Reserved */ + .long LPUART_IRQHandler /* 104 LPUART global interrupt (EXTI23) */ + + .space (470 * 4) /* Interrupts 10 .. 480 are left out */ +__Vectors_End: + .equ __Vectors_Size, __Vectors_End - __Vectors + .size __Vectors, . - __Vectors + + + .thumb + .section .text + .align 2 + + .thumb_func + .type Reset_Handler, %function + .globl Reset_Handler + .fnstart +Reset_Handler: + ldr r0, =__INITIAL_SP + msr psp, r0 + + #ifdef STACK_LIMIT_CHECK + ldr r0, =__STACK_LIMIT + msr msplim, r0 + msr psplim, r0 + #else + ldr r0, =0xE000ED14 + ldr r1, [r0] + orr r1, #0x400 + str r1, [r0] + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + ldr r0, =__STACK_SEAL + ldr r1, =0xFEF5EDA5U + strd r1,r1,[r0,#0] + #endif + + bl SystemInit + + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] /* source address */ + ldr r2, [r4, #4] /* destination address */ + ldr r3, [r4, #8] /* word count */ + lsls r3, r3, #2 /* byte count */ + +.L_loop0_0: + subs r3, #4 /* decrement byte count */ + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 +.L_loop0_done: + + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] /* destination address */ + ldr r2, [r3, #4] /* word count */ + lsls r2, r2, #2 /* byte count */ + movs r0, 0 + +.L_loop2_0: + subs r2, #4 /* decrement byte count */ + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: + + bl _start + + .fnend + .size Reset_Handler, . - Reset_Handler + + +/* The default macro is not used for HardFault_Handler + * because this results in a poor debug illusion. + */ + .thumb_func + .type HardFault_Handler, %function + .weak HardFault_Handler + .fnstart +HardFault_Handler: + b . + .fnend + .size HardFault_Handler, . - HardFault_Handler + + .thumb_func + .type Default_Handler, %function + .weak Default_Handler + .fnstart +Default_Handler: + b . + .fnend + .size Default_Handler, . - Default_Handler + +/* Macro to define default exception/interrupt handlers. + * Default handler are weak symbols with an endless loop. + * They can be overwritten by real handlers. + */ + .macro Set_Default_Handler Handler_Name + .weak \Handler_Name + .set \Handler_Name, Default_Handler + .endm + +/* Exception Handlers */ + Set_Default_Handler NMI_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler WWDG_IWDG_IRQHandler + Set_Default_Handler PVD_IRQHandler + Set_Default_Handler BKP_TAMPER_IRQHandler + Set_Default_Handler RTC_IRQHandler + Set_Default_Handler FLASH_IRQHandler + Set_Default_Handler RCC_CRS_IRQHandler + Set_Default_Handler EXTI0_IRQHandler + Set_Default_Handler EXTI1_IRQHandler + Set_Default_Handler EXTI2_IRQHandler + Set_Default_Handler EXTI3_IRQHandler + Set_Default_Handler EXTI4_IRQHandler + Set_Default_Handler DMA1_CH1_IRQHandler + Set_Default_Handler DMA1_CH2_IRQHandler + Set_Default_Handler DMA1_CH3_IRQHandler + Set_Default_Handler DMA1_CH4_IRQHandler + Set_Default_Handler DMA1_CH5_IRQHandler + Set_Default_Handler DMA1_CH6_IRQHandler + Set_Default_Handler DMA1_CH7_IRQHandler + Set_Default_Handler ADC1_2_IRQHandler + Set_Default_Handler DMA1_CH8_IRQHandler + Set_Default_Handler FlexCAN1_IRQHandler + Set_Default_Handler EXTI9_5_IRQHandler + Set_Default_Handler TIM1_BRK_IRQHandler + Set_Default_Handler TIM1_UP_IRQHandler + Set_Default_Handler TIM1_TRG_COM_IRQHandler + Set_Default_Handler TIM1_CC_IRQHandler + Set_Default_Handler TIM2_IRQHandler + Set_Default_Handler TIM3_IRQHandler + Set_Default_Handler TIM4_IRQHandler + Set_Default_Handler I2C1_IRQHandler + Set_Default_Handler I2C2_IRQHandler + Set_Default_Handler SPI1_IRQHandler + Set_Default_Handler SPI2_IRQHandler + Set_Default_Handler UART1_IRQHandler + Set_Default_Handler UART2_IRQHandler + Set_Default_Handler UART3_IRQHandler + Set_Default_Handler EXTI15_10_IRQHandler + Set_Default_Handler RTC_ALR_IRQHandler + Set_Default_Handler USB_WKUP_IRQHandler + Set_Default_Handler TIM8_BRK_IRQHandler + Set_Default_Handler TIM8_UP_IRQHandler + Set_Default_Handler TIM8_TRG_COM_IRQHandler + Set_Default_Handler TIM8_CC_IRQHandler + Set_Default_Handler TIM5_IRQHandler + Set_Default_Handler SPI3_IRQHandler + Set_Default_Handler UART4_IRQHandler + Set_Default_Handler UART5_IRQHandler + Set_Default_Handler TIM6_IRQHandler + Set_Default_Handler TIM7_IRQHandler + Set_Default_Handler DMA2_CH1_IRQHandler + Set_Default_Handler DMA2_CH2_IRQHandler + Set_Default_Handler DMA2_CH3_IRQHandler + Set_Default_Handler DMA2_CH4_IRQHandler + Set_Default_Handler DMA2_CH5_IRQHandler + Set_Default_Handler ENET_IRQHandler + Set_Default_Handler ENET_WKUP_IRQHandler + Set_Default_Handler COMP_IRQHandler + Set_Default_Handler FlexCAN2_IRQHandler + Set_Default_Handler USB_FS_IRQHandler + Set_Default_Handler DMA2_CH6_IRQHandler + Set_Default_Handler DMA2_CH7_IRQHandler + Set_Default_Handler DMA2_CH8_IRQHandler + Set_Default_Handler UART6_IRQHandler + Set_Default_Handler UART7_IRQHandler + Set_Default_Handler QSPI_IRQHandler + Set_Default_Handler LPTIM_IRQHandler + Set_Default_Handler LPUART_IRQHandler + + .end diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_adc.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_adc.c new file mode 100644 index 000000000..d10dc935a --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_adc.c @@ -0,0 +1,505 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_adc.h" + +void ADC_Init(ADC_Type * ADCx, ADC_Init_Type * init) +{ + + if (!init) + { + return; + } + + ADCx->ADCFG = (ADCx->ADCFG & ~ADC_ADCFG_RSLTCTL_MASK)| ADC_ADCFG_RSLTCTL(init->Resolution); + /* ADC conversion mode and conversion data result align. */ + ADCx->ADCR = (ADCx->ADCR & ~( ADC_ADCR_ADMD_MASK | ADC_ADCR_ALIGN_MASK) ) + | ADC_ADCR_ADMD(init->ConvMode) + | ADC_ADCR_ALIGN(init->Align) + ; + /* Set the single-end or diff conversion mode. */ + ADCx->ADCFG2 = ADCx->ADCFG2 & ~(ADC_ADCFG2_ADCSREF_MASK | ADC_ADCFG2_DC_MASK | ADC_ADCFG2_PSDC_MASK); + if (ADC_SingleDiffConvMode_SingleEnd == init->SingleDiffMode) + { + ADCx->ADCFG2 |= ADC_ADCFG2_ADCSREF(init->SingleVolt); + } + else if (ADC_SingleDiffConvMode_Diff == init->SingleDiffMode) + { + ADCx->ADCFG2 |= ADC_ADCFG2_DC(init->DiffPair); + } + else if (ADC_SingleDiffConvMode_PseudoDiff == init->SingleDiffMode) + { + ADCx->ADCFG2 = ADCx->ADCFG2 | ( ADC_ADCFG2_DC(init->DiffPair) | ADC_ADCFG2_PSDC(init->DiffPair) ); + } +} + +void ADC_Enable(ADC_Type * ADCx, bool enable) +{ + if (enable) + { + ADCx->ADCFG |= ADC_ADCFG_ADEN_MASK; + } + else + { + ADCx->ADCFG &= ~ADC_ADCFG_ADEN_MASK; + } +} + +void ADC_EnableTempSensor(ADC_Type * ADCx, bool enable) +{ + if (enable) + { + ADCx->ADCFG |= ADC_ADCFG_TSEN_MASK; + } + else + { + ADCx->ADCFG &= ~ADC_ADCFG_TSEN_MASK; + } +} + +/* Use VBG 1.2V as default voltage sensor. */ +void ADC_EnableVoltSensor(ADC_Type * ADCx, bool enable) +{ + if (enable) + { + ADCx ->ADCFG |= ADC_ADCFG_VSEN_MASK; + } + else + { + ADCx->ADCFG &= ~ADC_ADCFG_VSEN_MASK; + } +} + +void ADC_EnableDMA(ADC_Type * ADCx, bool enable) +{ + if (enable) + { + ADCx->ADCR |= ADC_ADCR_DMAEN_MASK; + } + else + { + ADCx->ADCR &= ~ADC_ADCR_DMAEN_MASK; + } +} + +void ADC_EnableInterrupts(ADC_Type * ADCx, uint32_t interrupts, bool enable) +{ + if (enable) + { + if ( 0u != (ADC_INT_CONV_SLOT_DONE & interrupts) ) + { + ADCx->ADCR |= ADC_ADCR_EOCIE_MASK; + } + if ( 0u != (ADC_INT_CONV_SAMPLE_DONE & interrupts) ) + { + ADCx->ADCR |= ADC_ADCR_EOSMPIE_MASK; + } + if ( 0u != (ADC_INT_CONV_SEQ_DONE & interrupts) ) + { + ADCx->ADCR |= ADC_ADCR_EOSIE_MASK; + } + if ( 0u != (ADC_INT_CONV_COMPARE_DONE & interrupts) ) + { + ADCx->ADCR |= ADC_ADCR_AWDIE_MASK; + } + if ( 0u != (ADC_INT_CONV_CALIB_DONE & interrupts) ) + { + ADCx->ANYCR |= ADC_ANYCR_EOCALIE_MASK; + } + if ( 0u != (ADC_INT_JCONV_SLOT_DONE & interrupts) ) + { + ADCx->ANYCR |= ADC_ANYCR_JEOCIE_MASK; + } + if ( 0u != (ADC_INT_JCONV_SAMPLE_DONE & interrupts) ) + { + ADCx->ANYCR |= ADC_ANYCR_JEOSMPIE_MASK; + } + if ( 0u != (ADC_INT_JCONV_SEQ_DONE & interrupts) ) + { + ADCx->ANYCR |= ADC_ANYCR_JEOSIE_MASK; + } + } + else + { + if ( 0u != (ADC_INT_CONV_SLOT_DONE & interrupts) ) + { + ADCx->ADCR &= ~ADC_ADCR_EOCIE_MASK; + } + if ( 0u != (ADC_INT_CONV_SAMPLE_DONE & interrupts) ) + { + ADCx->ADCR &= ~ADC_ADCR_EOSMPIE_MASK; + } + if ( 0u != (ADC_INT_CONV_SEQ_DONE & interrupts) ) + { + ADCx->ADCR &= ~ADC_ADCR_EOSIE_MASK; + } + if ( 0u != (ADC_INT_CONV_COMPARE_DONE & interrupts) ) + { + ADCx->ADCR &= ~ADC_ADCR_AWDIE_MASK; + } + if ( 0u != (ADC_INT_CONV_CALIB_DONE & interrupts) ) + { + ADCx->ANYCR &= ~ ADC_ANYCR_EOCALIE_MASK; + } + if ( 0u != (ADC_INT_JCONV_SLOT_DONE & interrupts) ) + { + ADCx->ANYCR &= ~ ADC_ANYCR_JEOCIE_MASK; + } + if ( 0u != (ADC_INT_JCONV_SAMPLE_DONE & interrupts) ) + { + ADCx->ANYCR &= ~ ADC_ANYCR_JEOSMPIE_MASK; + } + if ( 0u != (ADC_INT_JCONV_SEQ_DONE & interrupts) ) + { + ADCx->ANYCR &= ~ ADC_ANYCR_JEOSIE_MASK; + } + } +} + +uint32_t ADC_GetStatus(ADC_Type * ADCx) +{ + uint32_t flags = 0u; + + if ( 0u != (ADC_ADSTAEXT_EOCALIF_MASK & ADCx->ADSTAEXT) ) + { + flags |= ADC_STATUS_CONV_CALIB_DONE; + } + if ( 0u != (ADC_ADSTAEXT_JEOCIF_MASK & ADCx->ADSTAEXT) ) + { + flags |= ADC_STATUS_JCONV_SLOT_DONE; + } + if ( 0u != (ADC_ADSTAEXT_JEOSMPIF_MASK & ADCx->ADSTAEXT) ) + { + flags |= ADC_STATUS_JCONV_SAMPLE_DONE; + } + if ( 0u != (ADC_ADSTAEXT_JEOSIF_MASK & ADCx->ADSTAEXT) ) + { + flags |= ADC_STATUS_JCONV_SEQ_DONE; + } + if ( 0u != (ADC_ADSTAEXT_EOCIF_MASK & ADCx->ADSTAEXT) ) + { + flags |= ADC_STATUS_CONV_SLOT_DONE; + } + if ( 0u != (ADC_ADSTAEXT_EOSMPIF_MASK & ADCx->ADSTAEXT) ) + { + flags |= ADC_STATUS_CONV_SAMPLE_DONE; + } + if ( 0u != (ADC_ADSTA_EOSIF_MASK & ADCx->ADSTA) ) + { + flags |= ADC_STATUS_CONV_SEQ_DONE; + } + if ( 0u != (ADC_ADSTA_AWDIF_MASK & ADCx->ADSTA) ) + { + flags |= ADC_STATUS_CONV_COMPARE_DONE; + } + + return flags; +} + +void ADC_ClearStatus(ADC_Type * ADCx, uint32_t flags) +{ + + if ( 0u != (ADC_STATUS_CONV_CALIB_DONE & flags) ) + { + ADCx->ADSTAEXT = ADC_ADSTAEXT_EOCALIF_MASK; + } + if ( 0u != (ADC_STATUS_JCONV_SLOT_DONE & flags) ) + { + ADCx->ADSTAEXT = ADC_ADSTAEXT_JEOCIF_MASK; + } + if ( 0u != (ADC_STATUS_JCONV_SAMPLE_DONE & flags) ) + { + ADCx->ADSTAEXT = ADC_ADSTAEXT_JEOSMPIF_MASK; + } + if ( 0u != ( ADC_STATUS_JCONV_SEQ_DONE & flags) ) + { + ADCx->ADSTAEXT = ADC_ADSTAEXT_JEOSIF_MASK; + } + if ( 0u != (ADC_STATUS_CONV_SLOT_DONE & flags) ) + { + ADCx->ADSTAEXT = ADC_ADSTAEXT_EOCIF_MASK; + } + if ( 0u != (ADC_STATUS_CONV_SAMPLE_DONE & flags) ) + { + ADCx->ADSTAEXT = ADC_ADSTAEXT_EOSMPIF_MASK; + } + if ( 0u != (ADC_STATUS_CONV_SEQ_DONE & flags) ) + { + ADCx->ADSTA = ADC_ADSTA_EOSIF_MASK; + } + if ( 0u != (ADC_STATUS_CONV_COMPARE_DONE & flags) ) + { + ADCx->ADSTA = ADC_ADSTA_AWDIF_MASK; + } +} + +uint32_t ADC_GetChnConvResult(ADC_Type * ADCx, uint32_t * channel, uint32_t * flags) +{ + uint32_t tmp32 = ADCx->ADDATA; + + *channel = (tmp32 & (ADC_ADDATA_CHANNELSEL_MASK | ADC_ADDATA_CHANNELSELH_MASK) ) >> ADC_ADDATA_CHANNELSEL_SHIFT; + if (flags) + { + *flags = (tmp32 & (ADC_ADDATA_OVERRUN_MASK | ADC_ADDATA_VALID_MASK) ) >> ADC_ADDATA_OVERRUN_SHIFT; + } + + return (tmp32 & ADC_ADDATA_DATA_MASK ) >> ADC_ADDATA_DATA_SHIFT; +} + +uint32_t ADC_GetSlotConvResult(ADC_Type * ADCx, uint32_t slot, uint32_t * flags) +{ + uint32_t tmp32 = ADCx ->ADDR[slot]; + + if (flags) + { + *flags = (tmp32 & (ADC_ADDR_OVERRUN_MASK | ADC_ADDR_VALID_MASK) ) >> ADC_ADDR_OVERRUN_SHIFT; + } + + return (tmp32 & ADC_ADDR_DATA_MASK ) >> ADC_ADDR_DATA_SHIFT; +} + +uint32_t ADC_GetExtChnConvResult(ADC_Type * ADCx, uint32_t * channel, uint32_t * flags) +{ + uint32_t tmp32 = ADCx->JADDATA; + + *channel = (tmp32 & ADC_JADDATA_JCHANNELSEL_MASK) >> ADC_JADDATA_JCHANNELSEL_SHIFT; + if (flags) + { + *flags = (tmp32 & (ADC_JADDATA_JOVERRUN_MASK | ADC_JADDATA_JVALID_MASK) ) >> ADC_JADDATA_JOVERRUN_SHIFT; + } + + return (tmp32 & ADC_JADDATA_JDATA_MASK ) >> ADC_JADDATA_JDATA_SHIFT; +} + +uint32_t ADC_GetExtSlotConvResult(ADC_Type * ADCx, uint32_t slot, uint32_t * flags) +{ + uint32_t tmp32 = ADCx ->JDR[slot]; + + if (flags) + { + *flags = (tmp32 & (ADC_JDR_JOVERRUN_MASK | ADC_JDR_JVALID_MASK) ) >> ADC_JDR_JOVERRUN_SHIFT; + } + + return (tmp32 & ADC_JDR_JDATA_MASK ) >> ADC_JDR_JDATA_SHIFT; +} + +void ADC_SetChnSampleTime(ADC_Type * ADCx, uint32_t channel, ADC_SampleTime_Type sample_time) +{ + if (channel < 8u) + { + ADCx->SMPR1 = (ADCx->SMPR1 & ~(0xF << (4u * channel))) | (sample_time << (4u * channel)); + } + else if (channel-8 < 8u) + { + channel-= 8u; + ADCx->SMPR2 = (ADCx->SMPR2 & ~(0xF << (4u * channel))) | (sample_time << (4u * channel)); + } + else + { + channel-= 16u; + ADCx->SMPR3 = (ADCx->SMPR3 & ~(0xF << (4u * channel))) | (sample_time << (4u * channel)); + } +} + +void ADC_EnableHwTrigger(ADC_Type * ADCx, ADC_HwTriggerConf_Type * conf) +{ + if ( !conf ) + { + ADCx->ADCR &= ~ADC_ADCR_TRGEN_MASK; + return; + } + /* Enable the hardware trigger. */ + ADCx->ADCR = ( ADCx->ADCR & ~( ADC_ADCR_TRGSHIFT_MASK | ADC_ADCR_TRGEDGE_MASK) ) + | ADC_ADCR_TRGEN_MASK + | ADC_ADCR_TRGSHIFT(conf->DelayCycle) + | ADC_ADCR_TRGEDGE(conf->Edge) + ; +} + +void ADC_EnableSeqSlotFixed(ADC_Type * ADCx, uint32_t seq_slot, ADC_SeqFixedDirection_Type dir) +{ + ADCx->ANYCR &= ~ADC_ANYCR_CHANYMDEN_MASK; + /* enable fixed channel. */ + ADCx->ADCHS = seq_slot; + /* configure the scan direction. */ + ADCx->ADCR = (ADCx->ADCR & ~ADC_ADCR_SCANDIR_MASK) + | ADC_ADCR_SCANDIR(dir) + ; +} + +void ADC_EnableSeqSlot(ADC_Type * ADCx, uint32_t slot_idx, uint32_t channel) +{ + + if (slot_idx > 16u) + { + return; /* the available range of seq length is within 16u. */ + } + + /* enable any channel sequence mode. */ + ADCx->ANYCR |= ADC_ANYCR_CHANYMDEN_MASK; + /* select the any slots number. */ + ADCx->ANYCFG = ADC_ANYCFG_CHANYNUM(slot_idx); + uint32_t offset = slot_idx; + /* fill the channel into each slot. */ + if (slot_idx < 8u) + { + ADCx->CHANY0 = (ADCx->CHANY0 & ~( 0xFF << (offset * 4u) )) | ( (channel & 0xF) << (offset * 4u) ); + } + else + { + ADCx->CHANY1 = (ADCx->CHANY1 & ~( 0xFF << ((offset - 8u) * 4u) )) | ( (channel & 0xF) << ((offset - 8u) * 4u) ); + } + ADCx->ANYCFG = (ADCx->ANYCFG & ~( 0x01 << (offset + 8u) )) | ( (channel & 0x10) << (offset + 8u) ); + +} + +void ADC_EnableExtSeqSlot(ADC_Type * ADCx, uint32_t slot_idx, uint32_t channel) +{ + if (slot_idx > 4u) + { + return; /* the available range of seq length is within 4u. */ + } + /* enable the inject channel sequence mode. */ + ADCx->ANYCR |= ADC_ANYCR_JCEN_MASK; + /* select the inject slot number. */ + ADCx->JSQR = ADC_JSQR_JNUM(slot_idx); + /* fill the channels into each slot of inject sequence. */ + uint32_t offset = slot_idx; + ADCx->JSQR = (ADCx->JSQR &~(0x1F << (5u * offset)))| (channel & 0x1F) << (5u * offset); +} + +void ADC_EnableAutoExtSeqSlot(ADC_Type * ADCx, bool enable) +{ + if (enable) + { + ADCx->ANYCR |= ADC_ANYCR_JAUTO_MASK; + } + else + { + ADCx->ANYCR &= ~ADC_ANYCR_JAUTO_MASK; + } +} + +void ADC_DoExtSeqSlotSwTrigger(ADC_Type * ADCx, bool enable) +{ + if (enable) + { + ADCx->ANYCR |= ADC_ANYCR_JADST_MASK; + } + else + { + ADCx->ANYCR &= ~ADC_ANYCR_JADST_MASK; + } +} + +void ADC_SetExtSlotCalibParam(ADC_Type * ADCx, uint32_t slot, uint32_t value) +{ + ADCx->JOFR[slot] = ADC_JOFR_JOFFSET(value); +} + +void ADC_DoSwTrigger(ADC_Type * ADCx, bool enable) +{ + if (enable) + { + ADCx->ADCR |= ADC_ADCR_ADST_MASK; + } + else + { + ADCx->ADCR &= ~ADC_ADCR_ADST_MASK; + } +} + +void ADC_EnableHwComp(ADC_Type * ADCx, ADC_HwCompConf_Type * conf) +{ + if ( !conf ) + { + /* disable the hardware compare feature for both regular & any seq. */ + ADCx->ADCFG &= ~ADC_ADCFG_AWDEN_MASK; + return; + } + + /* enable the hardware compare feature. */ + ADCx->ADCFG |= ADC_ADCFG_AWDEN_MASK; + + /* setup the compare channel. */ + + ADCx->ADCR = (ADCx->ADCR & ~(ADC_ADCR_CMPCHL_MASK | ADC_ADCR_CMPCHH_MASK)) + | ADC_ADCR_CMPCHL(0xf & conf->ChnNum) + | ADC_ADCR_CMPCHH(conf->ChnNum >> 4) + ; + /* setup the compare boundary. */ + ADCx->ADCMPR = ADC_ADCMPR_CMPLDATA(conf->LowLimit) + | ADC_ADCMPR_CMPHDATA(conf->HighLimit) + ; +} + +void ADC_DoAutoCalib(ADC_Type * ADCx) +{ + ADCx->ANYCR |= ADC_ANYCR_ADCAL_MASK; + while(0u == (ADCx->ADSTAEXT & ADC_ADSTAEXT_EOCALIF_MASK)); + /* clear the status. */ + ADCx->ADSTAEXT = ADC_ADSTAEXT_EOCALIF_MASK; +} + +uint32_t ADC_GetCalibFactor(ADC_Type * ADCx, uint32_t * factor) +{ + for (uint32_t i = 0; i < 17; i++) + { + ADCx->ADDATA = ADC_ADDATA_DATA((i + 1) << 9); + factor[i]= ADCx->ADDATA & 0x1FF; + while ( 0u == (ADCx->ADSTAEXT & ADC_ADSTAEXT_FREOCIF_MASK)) + {} + ADCx->ADSTAEXT |= ADC_ADSTAEXT_FREOCIF_MASK; + } + return 1; +} + +void ADC_SetCalibFactor(ADC_Type * ADCx, uint32_t * factor) +{ + for (uint32_t i = 0; i < 17; i++) + { + ADCx->ADDATA = factor[i] | ( (i + 1) << 9); + while ( 0u == (ADCx->ADSTAEXT & ADC_ADSTAEXT_FREOCIF_MASK)) + {} + ADCx->ADSTAEXT |= ADC_ADSTAEXT_FREOCIF_MASK; + } +} + +void ADC_SetOverSample(ADC_Type * ADCx, ADC_OverSampleConf_Type *conf) +{ + if (!conf) + { + return; + } + ADCx->ADCFG2 = ( ADCx->ADCFG2 & ~ (ADC_ADCFG2_ROVSE_MASK |ADC_ADCFG2_JOVSE_MASK | ADC_ADCFG2_OVSR_MASK | ADC_ADCFG2_OVSS_MASK | ADC_ADCFG2_TROVS_MASK) ) + | ADC_ADCFG2_OVSR(conf->Ratio) + | ADC_ADCFG2_OVSS(conf->Div) + | ADC_ADCFG2_TROVS(conf->Mode) + | ADC_ADCFG2_JOVSE(conf->injectOverSampleMode) + ; +} + +void ADC_ResetAllSlot(ADC_Type * ADCx) +{ + /* wait for the latest conversion done. */ + while( (0u != (ADCx->ADSTA & ADC_ADSTA_BUSY_MASK)) | (0u != (ADCx->ADSTAEXT & ADC_ADSTAEXT_JBUSY_MASK)) ) + {} + /* disable the regular channel. */ + ADCx->ADCHS = 0x00; + /* disable the any sequence. */ + ADCx->CHANY0 = 0x00; + ADCx->CHANY1 = 0x00; + /* reset the inject slot . */ + ADCx->JSQR = 0x00; + /* disable inject conversion. */ + ADCx->ANYCR &= ~ADC_ANYCR_JCEN_MASK; + /* disable sequence conversion. */ + ADCx->ANYCR &= ~ADC_ANYCR_CHANYMDEN_MASK; + /* stop adc conversion. */ + ADCx->ADCR |= ADC_ADCR_ADST_MASK; +} +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_adc.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_adc.h new file mode 100644 index 000000000..87b2fea72 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_adc.h @@ -0,0 +1,591 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_ADC_H__ +#define __HAL_ADC_H__ + +#include "hal_common.h" + +/*! + * @addtogroup ADC + * @{ + */ + +/*! + * @brief ADC driver version number. + */ +#define ADC_DRIVER_VERSION 1u /*!< adc_1. */ + +/*! + * @addtogroup ADC_STATUS + * Define ADC status. + * @{ + */ + +#define ADC_STATUS_CONV_SLOT_DONE (1u << 0u) /*!< Status flag when ADC slot conversion done. */ +#define ADC_STATUS_CONV_SAMPLE_DONE (1u << 1u) /*!< Status flag when ADC sample done. */ +#define ADC_STATUS_CONV_SEQ_DONE (1u << 2u) /*!< Status flag when ADC sequence conversion done. */ +#define ADC_STATUS_CONV_COMPARE_DONE (1u << 3u) /*!< Status flag when ADC compare done. */ +#define ADC_STATUS_CONV_CALIB_DONE (1u << 4u) /*!< Status flag when ADC calibration done */ +#define ADC_STATUS_JCONV_SLOT_DONE (1u << 5u) /*!< Status flag when ADC inject slot conversion done. */ +#define ADC_STATUS_JCONV_SAMPLE_DONE (1u << 6u) /*!< Status flag when ADC inject sample done. */ +#define ADC_STATUS_JCONV_SEQ_DONE (1u << 7u) /*!< Status flag when ADC inject sequence conversion done. */ + +/*! + * @} + */ + +/*! + * @addtogroup ADC_INT + * ADC interrupt define. + * @{ + */ + +#define ADC_INT_CONV_SLOT_DONE (1u << 0u) /*!< Interrupt when ADC slot conversion done. */ +#define ADC_INT_CONV_SAMPLE_DONE (1u << 1u) /*!< Interrupt enable when ADC sample done. */ +#define ADC_INT_CONV_SEQ_DONE (1u << 2u) /*!< Interrupt enable when ADC sequence conversion done. */ +#define ADC_INT_CONV_COMPARE_DONE (1u << 3u) /*!< Interrupt enable when ADC compare done. */ +#define ADC_INT_CONV_CALIB_DONE (1u << 4u) /*!< Interrupt enable when ADC calibration done */ +#define ADC_INT_JCONV_SLOT_DONE (1u << 5u) /*!< Interrupt enable when ADC inject slot conversion done. */ +#define ADC_INT_JCONV_SAMPLE_DONE (1u << 6u) /*!< Interrupt enable when ADC inject sample done. */ +#define ADC_INT_JCONV_SEQ_DONE (1u << 7u) /*!< Interrupt enable when ADC inject sequence conversion done. */ + +/*! + * @} + */ + +/*! + * @addtogroup ADC_RESULT_FLAGS + * Define ADC Convert result flags. + * @{ + */ + +#define ADC_CONV_RESULT_FLAG_OVERRUN (1u << 0u) /*!< Result flag when adc conversion result is overrun. */ +#define ADC_CONV_RESULT_FLAG_VALID (1u << 1u) /*!< Result flag when adc conversion result valid. */ + +/*! + * @} + */ + + +/*! + * @brief ADC Resolution type. + * + * Select ADC conversion data resolution. + */ +typedef enum +{ + ADC_Resolution_Alt0 = 0u, /*!< source 0 as a resolution source for ADC. */ + ADC_Resolution_Alt1 = 1u, /*!< source 1 as a resolution source for ADC. */ + ADC_Resolution_Alt2 = 2u, /*!< source 2 as a resolution source for ADC. */ + ADC_Resolution_Alt3 = 3u, /*!< source 3 as a resolution source for ADC. */ + ADC_Resolution_Alt4 = 4u, /*!< source 4 as a resolution source for ADC. */ +} ADC_Resolution_Type; + + +/*! + * @brief ADC HwTriggerEdge type. + * + * Use hardware trigger in ADC, this trigger edge must be rising edge. + */ +typedef enum +{ + ADC_HwTriggerEdge_RisingEdge = 2u, /*!< Rising edge trigger. */ +} ADC_HwTriggerEdge_Type; + +/*! + * @brief ADC HwTriggerDelayCycle type. + * + * After the hardware trigger signal is generated, delay N PCLK2 clock cycles before starting the first sample. + */ +typedef enum +{ + ADC_HwTriggerDelayCycle_0 = 0u, /*!< Delay 0 cycle. */ + ADC_HwTriggerDelayCycle_4 = 1u, /*!< Delay 4 cycle. */ + ADC_HwTriggerDelayCycle_16 = 2u, /*!< Delay 16 cycle. */ + ADC_HwTriggerDelayCycle_32 = 3u, /*!< Delay 32 cycle. */ + ADC_HwTriggerDelayCycle_64 = 4u, /*!< Delay 64 cycle. */ + ADC_HwTriggerDelayCycle_128 = 5u, /*!< Delay 128 cycle. */ + ADC_HwTriggerDelayCycle_256 = 6u, /*!< Delay 256 cycle. */ + ADC_HwTriggerDelayCycle_512 = 7u, /*!< Delay 512 cycle. */ +} ADC_HwTriggerDelayCycle_Type; + +/*! + * @brief ADC Align type. + * + * Choose to store the converted data as left-aligned or right-aligned. + */ +typedef enum +{ + ADC_Align_Right = 0u, /*!< Data right align. */ + ADC_Align_Left = 1u, /*!< Data left align. */ +} ADC_Align_Type; + +/*! + * @brief ADC SeqFixedDirection type. + * + * In single-cycle scan or continuous scan mode, set the order of scan channels. + */ +typedef enum +{ + ADC_SeqFixedDirection_LowFirst = 0u, /*!< ADC scan direction from low channel to high channel. */ + ADC_SeqFixedDirection_HighFirst = 1u, /*!< ADC scan direction from high channel to low channel. */ +} ADC_SeqFixedDirection_Type; + +/*! + * @brief ADC ConvMode type. + * + * Select the adc channel or sequence convert mode. + */ +typedef enum +{ + ADC_ConvMode_SingleSlot = 0u, /*!< Run the conversion by channel. */ + ADC_ConvMode_SeqOneTime = 1u, /*!< Run the conversion by sequence once. */ + ADC_ConvMode_SeqContinues = 2u, /*!< Run the conversion by sequence again and again. */ +} ADC_ConvMode_Type; + +/*! + * @brief ADC SampleTime type. + * + * Select channel sample time. + */ +typedef enum +{ + ADC_SampleTime_Alt0 = 0u, /*!< Channel sample time mode 0 . */ + ADC_SampleTime_Alt1 = 1u, /*!< Channel sample time mode 1 . */ + ADC_SampleTime_Alt2 = 2u, /*!< Channel sample time mode 2 . */ + ADC_SampleTime_Alt3 = 3u, /*!< Channel sample time mode 3 . */ + ADC_SampleTime_Alt4 = 4u, /*!< Channel sample time mode 4 . */ + ADC_SampleTime_Alt5 = 5u, /*!< Channel sample time mode 5 . */ + ADC_SampleTime_Alt6 = 6u, /*!< Channel sample time mode 6 . */ + ADC_SampleTime_Alt7 = 7u, /*!< Channel sample time mode 7 . */ + ADC_SampleTime_Alt8 = 8u, /*!< Channel sample time mode 8 . */ + ADC_SampleTime_Alt9 = 9u, /*!< Channel sample time mode 9 . */ + ADC_SampleTime_Alt10 = 10u, /*!< Channel sample time mode 10. */ + ADC_SampleTime_Alt11 = 11u, /*!< Channel sample time mode 11. */ + ADC_SampleTime_Alt12 = 12u, /*!< Channel sample time mode 12. */ + ADC_SampleTime_Alt13 = 13u, /*!< Channel sample time mode 13. */ + ADC_SampleTime_Alt14 = 14u, /*!< Channel sample time mode 14. */ + ADC_SampleTime_Alt15 = 15u, /*!< Channel sample time mode 15. */ +} ADC_SampleTime_Type; + +/*! + * @brief ADC SingDiffConvMode type. + * + * Select ADC channel single-ended or difference conversion mode. + */ +typedef enum +{ + ADC_SingleDiffConvMode_SingleEnd = 1u, /*!< Channel conversion mode is single-ended conversion. */ + ADC_SingleDiffConvMode_Diff = 2u, /*!< Channel conversion mode is differential conversion. */ + ADC_SingleDiffConvMode_PseudoDiff = 3u, /*!< Channel conversion mode is pseudo-difference conversion. */ +}ADC_SingleDiffConvMode_Type; + +/*! + * @brief ADC SingleConvVref type. + * + * Select the reference voltage for single-ended conversion mode. + */ +typedef enum +{ + ADC_SingleConvVref_Internal = 1u, /*!< Select the internal reference voltage as the reference voltage for single-ended conversion. */ + ADC_SingleConvVref_External = 0u, /*!< Select the external reference voltage as the reference voltage for single-ended conversion. */ +}ADC_SingleConvVref_Type; + +/*! + * @brief ADC DiffPair type. + * + * Select channel source as ADC differential or pseudo-difference conversion channels. + */ +typedef enum +{ + ADC_DiffChnPair_0_1 = 1u, /*!< Select channel 0 and 1 for a group of differential or pseudo-difference channels. */ + ADC_DiffChnPair_2_3 = 2u, /*!< Select channel 2 and 3 for a group of differential or pseudo-difference channels */ + ADC_DiffChnPair_4_5 = 4u, /*!< Select channel 4 and 5 for a group of differential or pseudo-difference channels. */ + ADC_DiffChnPair_6_7 = 8u, /*!< Select channel 6 and 7 for a group of differential or pseudo-difference channels. */ +}ADC_DiffPair_Type; + +/*! + * @brief ADC OverSampleRatio type. + * + * Select ADC oversampling rate, to confirm the number of conversions performed by ADC, the sum of these conversion data is calculated as ADC oversampling conversion data (before potential shift). + */ +typedef enum +{ + ADC_OverSampleRatio_2 = 0u, /*!< Select the oversample ratio of 2, 2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data,before potential shift. */ + ADC_OverSampleRatio_4 = 1u, /*!< Select the oversample ratio of 4, 4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data,before potential shift. */ + ADC_OverSampleRatio_8 = 2u, /*!< Select the oversample ratio of 8, 8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data,before potential shift. */ + ADC_OverSampleRatio_16 = 3u, /*!< Select the oversample ratio of 16, 16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data,before potential shift. */ + ADC_OverSampleRatio_32 = 4u, /*!< Select the oversample ratio of 32, 32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data,before potential shift. */ + ADC_OverSampleRatio_64 = 5u, /*!< Select the oversample ratio of 64, 64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data,before potential shift. */ + ADC_OverSampleRatio_128 = 6u, /*!< Select the oversample ratio of 128,128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data,before potential shift. */ + ADC_OverSampleRatio_256 = 7u, /*!< Select the oversample ratio of 256, 256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data,before potential shift. */ +}ADC_OverSampleRatio_Type; + +/*! + * @brief ADC OverSampleDataDiv type. + * + * Select ADC oversampling rate, to confirm the number of conversions performed by ADC, the sum of these conversion data is calculated as ADC oversampling conversion data (before potential shift). + */ +typedef enum +{ + ADC_OverSampleDataDiv_0 = 0u, /*!< Select ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data). */ + ADC_OverSampleDataDiv_1 = 1u, /*!< Select ADC oversampling 1 shift (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data). */ + ADC_OverSampleDataDiv_2 = 2u, /*!< Select ADC oversampling 2 shift (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data). */ + ADC_OverSampleDataDiv_3 = 3u, /*!< Select ADC oversampling 3 shift (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data). */ + ADC_OverSampleDataDiv_4 = 4u, /*!< Select ADC oversampling 4 shift (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data). */ + ADC_OverSampleDataDiv_5 = 5u, /*!< Select ADC oversampling 5 shift (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data). */ + ADC_OverSampleDataDiv_6 = 6u, /*!< Select ADC oversampling 6 shift (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data). */ + ADC_OverSampleDataDiv_7 = 7u, /*!< Select ADC oversampling 7 shift (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data). */ + ADC_OverSampleDataDiv_8 = 8u, /*!< Select ADC oversampling 8 shift (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data). */ +}ADC_OverSampleDataDiv_Type; + +/*! + * @brief ADC ADC_OverSampleTrigMode type. + * + * Select ADC oversampling continuous or discontinuous mode + */ +typedef enum +{ + ADC_OverSampleTriggerMode_Multi = 0u, /*!< All conversions of oversampling ratio are done from 1 trigger. */ + ADC_OverSampleTriggerMode_Single = 1u, /*!< Each conversion of oversampling ratio needs a trigger. */ +}ADC_OverSampleTriggerMode_Type; + + +/*! + * @brief This type of structure instance is used to keep the settings + * when calling the @ref ADC_Init() to initialize the ADC module. + */ +typedef struct +{ + ADC_Resolution_Type Resolution; /*!< Specify the available bits for the conversion result data. */ + ADC_Align_Type Align; /*!< Specify the data alignment. */ + ADC_ConvMode_Type ConvMode; /*!< Specify the adc conversion mode. */ + ADC_SingleDiffConvMode_Type SingleDiffMode; /*!< Select ADC channel single-ended or difference conversion mode.*/ + ADC_DiffPair_Type DiffPair; /*!< Select channel source as ADC differential or pseudo-difference conversion channels. */ + ADC_SingleConvVref_Type SingleVolt; /*!< Select the single-ended conversion vref source. */ +} ADC_Init_Type; + +/*! + * @brief This type of structure instance is used to keep the settings + * when calling the @ref ADC_EnableHwTrigger() to initialize the ADC hardware trigger module. + */ +typedef struct +{ + ADC_HwTriggerEdge_Type Edge; /*!< Select the trigger edge. */ + ADC_HwTriggerDelayCycle_Type DelayCycle; /*!< Select the hardware trigger shift sample. */ +} ADC_HwTriggerConf_Type; + +/*! + * @brief This type of structure instance is used to keep the settings + * when calling the @ref ADC_EnableHwComp() to enable the ADC windows compare mode. + */ +typedef struct +{ + uint32_t ChnNum; /*!< Select the channel number binding to the compare. */ + uint32_t HighLimit; /*!< The comparator high limit. */ + uint32_t LowLimit; /*!< The comparator low limit. */ +} ADC_HwCompConf_Type; + +/*! + * @brief This type of structure instance is used to keep the settings + * This function just only used in any channel or inject channel. + * when calling the @ref ADC_SetOverSample() to initialize the ADC oversample module. + */ +typedef struct +{ + ADC_OverSampleRatio_Type Ratio; /*!< Configures the oversampling ratio. */ + ADC_OverSampleDataDiv_Type Div; /*!< Configures the division coefficient for the Oversampler. */ + ADC_OverSampleTriggerMode_Type Mode; /*!< Select the oversample trigger mode. */ + bool injectOverSampleMode; /*!< Whether injection channel oversampling is enable, ture is enable, false is disable. */ +}ADC_OverSampleConf_Type; + +/*! + * @brief Initialize the ADC module. + * + * @param ADCx ADC instance. + * @param init Pointer to the initialization structure. See to @ref ADC_Init_Type. + * @return None. + */ +void ADC_Init(ADC_Type * ADCx, ADC_Init_Type * init); + +/*! + * @brief Enable the ADC module. + * + * The ADC module should be enabled before conversion data. + * + * @param ADCx ADC instance. + * @param enable 'true' to enable the module, 'false' to disable the module. + * @return None. + */ +void ADC_Enable(ADC_Type * ADCx, bool enable); + +/*! + * @brief Enable Temperature sensor from the ADC module. + * + * The module should be enabled when Using the built-in temperature sensor to + * detect temperature changes inside the device. + * + * @param ADCx ADC instance. + * @param enable 'true' to enable the module, 'false' to disable the module. + * @return None. + */ +void ADC_EnableTempSensor(ADC_Type * ADCx, bool enable); + +/*! + * @brief Enable Voltage sensor from the ADC module. + * + * The module should be enabled when using internal reference voltage . + * + * @param ADCx ADC instance. + * @param enable 'true' to enable the module, 'false' to disable the module. + * @return None. + */ +void ADC_EnableVoltSensor(ADC_Type * ADCx, bool enable); + +/*! + * @brief Enable the DMA from the ADC module. + * + * @param ADCx ADC instance. + * @param enable 'true' to enable the DMA, 'false' to disable the DMA. + * @return None. + */ +void ADC_EnableDMA(ADC_Type * ADCx, bool enable); + +/*! + * @brief Enable interrupts of the ADC module. + * + * @param ADCx ADC instance. + * @param interrupts Interrupt code masks. + * @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts. + * @return None. + */ +void ADC_EnableInterrupts(ADC_Type * ADCx, uint32_t interrupts, bool enable); + +/*! + * @brief Get the current status flags of the ADC module. + * + * @param ADCx ADC instance. + * @return Status flags. + */ +uint32_t ADC_GetStatus(ADC_Type * ADCx); + +/*! + * @brief Clear the status flags of the ADC module. + * + * @param ADCx ADC instance. + * @param flags The mask codes of the indicated interrupt flags to be cleared. + * @return None. + */ +void ADC_ClearStatus(ADC_Type * ADCx, uint32_t flags); + +/*! + * @brief Get the channel convert data from the ADC module. + * + * @param ADCx ADC instance. + * @param channel The convert channel. + * @param flags The ADC convert result flags. See to @ref ADC_RESULT_FLAGS. + * @return The data value. + */ +uint32_t ADC_GetChnConvResult(ADC_Type * ADCx, uint32_t * channel, uint32_t * flags); + +/*! + * @brief Get the indication slot conversion data from the ADC module. + * + * @param ADCx ADC instance. + * @param slot the adc conversion slot. + * @param flags The ADC convert result flags. See to @ref ADC_RESULT_FLAGS. + * @return The data value. + */ +uint32_t ADC_GetSlotConvResult(ADC_Type * ADCx, uint32_t slot, uint32_t * flags); + +/*! + * @brief Get the inject channel convert data from the ADC module. + * + * @param ADCx ADC instance. + * @param channel The convert channel. + * @param flags The ADC convert result flags. See to @ref ADC_RESULT_FLAGS. + * @return The data value. + */ +uint32_t ADC_GetExtChnConvResult(ADC_Type * ADCx, uint32_t * channel, uint32_t * flags); + +/*! + * @brief Get the indication external slot convert data from the ADC module. + * + * @param ADCx ADC instance. + * @param slot the adc external slot. + * @param flags The ADC convert result flags. See to @ref ADC_RESULT_FLAGS. + * @return The data value. + */ +uint32_t ADC_GetExtSlotConvResult(ADC_Type * ADCx, uint32_t slot, uint32_t * flags); + +/*! + * @brief Configuration channel sample time of the ADC module. + * + * @param ADCx ADC instance. + * @param channel the adc convert channel. + * @param sampletime the adc channel sample time + * @return None. + */ +void ADC_SetChnSampleTime(ADC_Type * ADCx, uint32_t channel, ADC_SampleTime_Type sample_time); + +/*! + * @brief Enable hardware trigger from the ADC module. + * + * The ADC module should be enabled before using hardware trrigger function. + * it also have interrupt. + * + * @param ADCx ADC instance. + * @param conf Select the hardware trigger source. See to @ref ADC_HwTrgConf_Type. + * @return None. + */ +void ADC_EnableHwTrigger(ADC_Type * ADCx, ADC_HwTriggerConf_Type * conf); + +/*! + * @brief Enable fixed slot sequence conversion from the ADC module. + * + * The ADC module should be enabled before regular sequence function. + * it also have interrupt. + * + * @param ADCx ADC instance. + * @param seq_slot the fixed channel, it can be ascending or descending. + * @param seq_direction the sequence fixed scan direction. + * @return None. + */ +void ADC_EnableSeqSlotFixed(ADC_Type * ADCx, uint32_t seq_slot, ADC_SeqFixedDirection_Type dir); + + +/*! + * @brief Enable sequence conversion from the ADC module. + * + * The ADC module should be enabled before Any sequence function. + * it also have interrupt. + * + * @param ADCx ADC instance. + * @param slot_idx the sequence slot index. + * @param channel the conversion channel, it will be placed in each slot. + * @return None. + */ +void ADC_EnableSeqSlot(ADC_Type * ADCx, uint32_t slot_idx, uint32_t channel); + +/*! + * @brief Enable external sequence conversion from the ADC module. + * + * The ADC module should be enabled before sequence conversion function. + * it also have interrupt. + * + * @param ADCx ADC instance. + * @param slot_idx the sequence slot index. + * @param channel the conversion channel, it will be placed in each slot. + * @return None. + */ +void ADC_EnableExtSeqSlot(ADC_Type * ADCx, uint32_t slot_idx, uint32_t channel); + +/*! + * @brief Enable Inject sequence auto conversion from the ADC module. + * the sequence conversion done, the inject sequence start conversion. + * + * @param ADCx ADC instance. + * @param enable 'true' to enable the ADC start inject sequence convert, 'false' to disable. + * @return None. + */ +void ADC_EnableAutoExtSeqSlot(ADC_Type * ADCx, bool enable); + +/*! + * @brief Do external chanenel sequence conversion software trigger. + * + * @param ADCx ADC instance. + * @param enable 'true' to enable the ADC start inject channel convert, 'false' to disable. + * @return None. + */ +void ADC_DoExtSeqSlotSwTrigger(ADC_Type * ADCx, bool enable); + +/*! + * @brief Set inject chanenel data offset compensation. + * + * @param ADCx ADC instance. + * @param value difference between actual input value and converted value. + * @param slot the inject slot. + * @return None. + */ +void ADC_SetExtSlotCalibParam(ADC_Type * ADCx, uint32_t slot, uint32_t value); + +/*! + * @brief Enable window comparison from the ADC module. + * + * The ADC module should be enabled before using analog watchdog function. + * it also have interrupt. + * + * @param ADCx ADC instance. + * @param conf Pointer to the initialization structure. See to @ref ADC_HwCompConf_Type. + * @return None. + */ +void ADC_EnableHwComp(ADC_Type * ADCx, ADC_HwCompConf_Type * conf); + +/*! + * @brief Do soft trigger. + * + * @param ADCx ADC instance. + * @param enable 'true' to enable the ADC start convert, 'false' to disable. + * @return None. + */ +void ADC_DoSwTrigger(ADC_Type * ADCx, bool enable); + +/*! + * @brief Do auto self-calibration. + * + * @param ADCx ADC instance. + * @return None. + */ +void ADC_DoAutoCalib(ADC_Type * ADCx); + +/*! + * @brief Get Calibration factor through auto calibration. + * + * when you use the use this api to get the calibration factor when you write the calibration through the register. + * @param ADCx ADC instance. + * @param factor from self-calibration,the calibration parameter consists of 17 9-digit numbers. + * @param return 1; + */ +uint32_t ADC_GetCalibFactor(ADC_Type * ADCx, uint32_t * factor); + +/*! + * @brief Set Calibration factor through register. + * + * when you use the use this api to write the calibration factor when you write the calibration through the register. + * @param ADCx ADC instance. + * @param factor the calibration parameters from ADC_GetCalibFactor(). + * @return None. + */ +void ADC_SetCalibFactor(ADC_Type * ADCx, uint32_t * factor); + +/*! + * @brief Set Set OverSample mode. + * + * Average value of converted data using hardware implementation. + * @param ADCx ADC instance. + * @param conf Pointer to the initialization structure. See to @ref ADC_OverSampleConf_Type. + * @return None. + */ + +void ADC_SetOverSample(ADC_Type * ADCx, ADC_OverSampleConf_Type *conf); + +/*! + * @brief Reset all the slot conversion. + * + * @param ADCx ADC instance. + * @return None. + */ + +void ADC_ResetAllSlot(ADC_Type * ADCx); + + +/*! + *@} + */ + +#endif /*__HAL_ADC_H__. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_common.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_common.h new file mode 100644 index 000000000..d9737d901 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_common.h @@ -0,0 +1,17 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __HAL_COMMON_H__ +#define __HAL_COMMON_H__ + +#include +#include +#include + +#include "hal_device_registers.h" + +#endif /* __HAL_COMMON_H__ */ + diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_comp.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_comp.c new file mode 100644 index 000000000..d433d6d64 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_comp.c @@ -0,0 +1,204 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_comp.h" + +static __IO uint32_t * COMP_GetCSR(COMP_Type * COMPx, uint32_t channel) +{ + __IO uint32_t * csr[] = + { + &COMPx->CSR[0], + &COMPx->CSR[1], + &COMPx->CSR3, + }; + return csr[channel]; +} + +/* init comp. */ +void COMP_Init(COMP_Type * COMPx, uint32_t channel, COMP_Init_Type * init) +{ + if ( channel < COMP_CHANNEL_NUM ) + { + __IO uint32_t * csr = COMP_GetCSR(COMPx, channel); + *csr = (*csr & ~(COMP_CSR_HYST_MASK | COMP_CSR_OUTSEL_MASK | COMP_CSR_INPSEL_MASK | COMP_CSR_INMSEL_MASK | COMP_CSR_MODE_MASK) ) + | COMP_CSR_HYST(init->Hysteresis) + | COMP_CSR_OUTSEL(init->OutMux) + | COMP_CSR_INPSEL(init->PosInMux) + | COMP_CSR_INMSEL(init->InvInMux) + | COMP_CSR_MODE(init->Speed) + ; + } +} + +/* enable comp. */ +void COMP_Enable(COMP_Type * COMPx, uint32_t channel, bool enable) +{ + if ( channel < COMP_CHANNEL_NUM ) + { + __IO uint32_t * csr = COMP_GetCSR(COMPx, channel); + if ( true == enable ) + { + *csr |= COMP_CSR_EN_MASK; + } + else + { + *csr &= ~COMP_CSR_EN_MASK; + } + } +} + +/* lock. */ +void COMP_Lock(COMP_Type * COMPx, uint32_t channel) +{ + if ( channel < COMP_CHANNEL_NUM ) + { + __IO uint32_t * csr = COMP_GetCSR(COMPx, channel); + *csr |= COMP_CSR_LOCK_MASK; + } +} + +/* get output status. */ +bool COMP_GetOutputStatus(COMP_Type * COMPx, uint32_t channel) +{ + if ( channel < COMP_CHANNEL_NUM ) + { + __IO uint32_t * csr = COMP_GetCSR(COMPx, channel); + if ( 0u != ( COMP_CSR_OUT_MASK & (*csr) ) ) + { + return true; + } + else + { + return false; /* normal input voltage lower than inverting input. */ + } + } + else + { + return false; + } +} + +/* enable external vref. */ +void COMP_EnableExtVrefConf(COMP_Type * COMPx, COMP_ExtVrefConf_Type * conf) +{ + if ( NULL == conf) /* disable the ext vref. */ + { + COMPx->CRV &= ~COMP_CRV_CRVEN_MASK; + } + else /* init & enable ext vref. */ + { + COMPx->CRV = (COMPx->CRV & ~(COMP_CRV_CRVSRC_MASK | COMP_CRV_CRVSEL_MASK | COMP_CRV_CRVEN_MASK) ) + | COMP_CRV_CRVSRC(conf->VrefSource) + | COMP_CRV_CRVSEL(conf->Volt) + | COMP_CRV_CRVEN_MASK + ; + } +} + +/* enable round robin (poll compare). */ +void COMP_EnableRoundRobinConf(COMP_Type * COMPx, uint32_t channel, COMP_RoundRobinConf_Type * conf) +{ + if ( channel < COMP_CHANNEL_NUM ) + { + if ( NULL == conf ) + { + COMPx->POLL[channel] &= ~COMP_POLL_POLLEN_MASK; + } + else + { + COMPx->POLL[channel] = (COMPx->POLL[channel] & ~(COMP_POLL_PERIOD_MASK | COMP_POLL_FIXN_MASK | COMP_POLL_POLLCH_MASK | COMP_POLL_POLLEN_MASK) ) + | COMP_POLL_PERIOD(conf->Period) + | COMP_POLL_FIXN(conf->EnableInvInFix) + | COMP_POLL_POLLCH(conf->ChnGroup) + | COMP_POLL_POLLEN_MASK; + ; + } + } +} + +/* get round robin (poll compare) status. */ +bool COMP_GetRoundRobinOutStatus(COMP_Type * COMPx, uint32_t channel, COMP_InMux_Type pos_in) +{ + if ( channel < COMP_CHANNEL_NUM ) + { + uint32_t mask = COMP_POLL_POUT(1u << ( (uint32_t)pos_in - 1u ) ); + if ( 0u != (COMPx->POLL[channel] & mask) ) + { + return true; + } + else + { + return false; + } + } + else + { + return false; + } +} + +/* set output filter. */ +void COMP_SetOutFilter(COMP_Type * COMPx, uint32_t channel, COMP_OutFilter_Type filter) +{ + if (channel < COMP_CHANNEL_NUM) + { + __IO uint32_t * csr = COMP_GetCSR(COMPx, channel); + *csr = (*csr & ~COMP_CSR_OFLT_MASK) | COMP_CSR_OFLT(filter); + } +} + +/* enable output invert. */ +void COMP_EnableOutInvert(COMP_Type * COMPx, uint32_t channel, bool invert) +{ + if (channel < COMP_CHANNEL_NUM) + { + __IO uint32_t * csr = COMP_GetCSR(COMPx, channel); + if(true == invert) + { + *csr = (*csr & ~COMP_CSR_POL_MASK) | COMP_CSR_POL(1u); + } + else + { + *csr = (*csr & ~COMP_CSR_POL_MASK) | COMP_CSR_POL(0u); + } + } +} + +/* enable bypass output. */ +void COMP_EnableBypassOutput(COMP_Type * COMPx, uint32_t channel, bool enable) +{ + if (channel < COMP_CHANNEL_NUM) + { + __IO uint32_t * csr = COMP_GetCSR(COMPx, channel); + if (enable) + { + *csr |= COMP_CSR_OUTANASEL_MASK; + } + else + { + *csr &= ~COMP_CSR_OUTANASEL_MASK; + } + } +} + +void COMP_EnableWindow(COMP_Type * COMPx, uint32_t channel, bool enable) +{ + if (channel < COMP_CHANNEL_NUM) + { + __IO uint32_t * csr = COMP_GetCSR(COMPx, channel); + if (enable) + { + *csr |= COMP_CSR_WE_MASK; + } + else + { + *csr &= ~COMP_CSR_WE_MASK; + } + } +} + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_comp.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_comp.h new file mode 100644 index 000000000..a71c980d5 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_comp.h @@ -0,0 +1,306 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_COMP_H__ +#define __HAL_COMP_H__ + +#include "hal_common.h" + +/*! + * @addtogroup COMP + * @{ + */ + +/*! + * @brief COMP driver version number. + */ +#define COMP_DRIVER_VERSION 1u /*!< COMP_1. */ + +/*! + * @brief COMP number. + */ +#define COMP_CHANNEL_NUM 3u + +/*! + * @brief COMP output filter type. + * + * If the compare result keeps n APB Clocks unchanged, the output is valid. + */ +typedef enum +{ + COMP_OutFilter_1 = 0x00, /*!< 1 PCLK filter. */ + COMP_OutFilter_2 = 0x01, /*!< 2 PCLK filter. */ + COMP_OutFilter_4 = 0x02, /*!< 4 PCLK filter. */ + COMP_OutFilter_8 = 0x03, /*!< 8 PCLK filter. */ + COMP_OutFilter_16 = 0x04, /*!< 16 PCLK filter. */ + COMP_OutFilter_32 = 0x05, /*!< 32 PCLK filter. */ + COMP_OutFilter_64 = 0x06, /*!< 64 PCLK filter. */ + COMP_OutFilter_128 = 0x07, /*!< 128 PCLK filter. */ +} COMP_OutFilter_Type; + +/*! + * @brief COMP hysteresis type. + * + * If V(InvInput) > V(PosInput), the compare result is high, if V(InvInput) < (V(PosInput) - hysteresis), the compare result is low. + */ +typedef enum +{ + COMP_Hysteresis_Alt0 = 0x00, /*!< Hysteresis alt 0. */ + COMP_Hysteresis_Alt1 = 0x01, /*!< Hysteresis alt 1. */ + COMP_Hysteresis_Alt2 = 0x02, /*!< Hysteresis alt 2. */ + COMP_Hysteresis_Alt3 = 0x03, /*!< Hysteresis alt 3. */ +} COMP_Hysteresis_Type; + +/*! + * @brief COMP output mux type. + */ +typedef enum +{ + COMP_OutMux_Alt0 = 0x00, /*!< Output mux alt 0. */ + COMP_OutMux_Alt1 = 0x01, /*!< Output mux alt 1. */ + COMP_OutMux_Alt2 = 0x02, /*!< Output mux alt 2. */ + COMP_OutMux_Alt3 = 0x03, /*!< Output mux alt 3. */ + COMP_OutMux_Alt4 = 0x04, /*!< Output mux alt 4. */ + COMP_OutMux_Alt5 = 0x05, /*!< Output mux alt 5. */ + COMP_OutMux_Alt6 = 0x06, /*!< Output mux alt 6. */ + COMP_OutMux_Alt7 = 0x07, /*!< Output mux alt 7. */ + COMP_OutMux_Alt8 = 0x08, /*!< Output mux alt 8. */ + COMP_OutMux_Alt9 = 0x09, /*!< Output mux alt 0. */ + COMP_OutMux_Alt11 = 0x0A, /*!< Output mux alt 1. */ + COMP_OutMux_Alt12 = 0x0B, /*!< Output mux alt 2. */ + COMP_OutMux_Alt13 = 0x0C, /*!< Output mux alt 3. */ + COMP_OutMux_Alt14 = 0x0D, /*!< Output mux alt 4. */ + COMP_OutMux_Alt15 = 0x0E, /*!< Output mux alt 5. */ +} COMP_OutMux_Type; + +/*! + * @brief COMP input Mux type. + */ +typedef enum +{ + COMP_InMux_Alt0 = 0x00, /*!< Input mux 0. */ + COMP_InMux_Alt1 = 0x01, /*!< Input mux 1. */ + COMP_InMux_Alt2 = 0x02, /*!< Input mux 2. */ + COMP_InMux_Alt3 = 0x03, /*!< Input mux 3. */ + COMP_InMux_Alt4 = 0x04, /*!< Input mux 4. */ + COMP_InMux_Alt5 = 0x05, /*!< Input mux 5. */ +} COMP_InMux_Type; + +/*! + * @brief COMP speed type. + */ +typedef enum +{ + COMP_Speed_High = 0x00, /*!< High speed. */ + COMP_Speed_Middle = 0x01, /*!< Middle speed. */ + COMP_Speed_Low = 0x02, /*!< Low speed. */ + COMP_Speed_DeepLow = 0x03, /*!< Deep low speed. */ +} COMP_Speed_Type; + +/*! + * @brief COMP external reference voltage source type. + */ +typedef enum +{ + COMP_ExtVrefSource_VREFINT = 0x00, /*!< Internal reference voltage. */ + COMP_ExtVrefSource_VDDA = 0x01, /*!< VDDA voltage. */ +} COMP_ExtVrefSource_Type; + +/*! + * @brief COMP external reference voltage type. + */ +typedef enum +{ + COMP_ExtVrefVolt_Alt0 = 0x00, /*!< External reference voltage alt 0. */ + COMP_ExtVrefVolt_Alt1 = 0x01, /*!< External reference voltage alt 1. */ + COMP_ExtVrefVolt_Alt2 = 0x02, /*!< External reference voltage alt 2. */ + COMP_ExtVrefVolt_Alt3 = 0x03, /*!< External reference voltage alt 3. */ + COMP_ExtVrefVolt_Alt4 = 0x04, /*!< External reference voltage alt 4. */ + COMP_ExtVrefVolt_Alt5 = 0x05, /*!< External reference voltage alt 5. */ + COMP_ExtVrefVolt_Alt6 = 0x06, /*!< External reference voltage alt 6. */ + COMP_ExtVrefVolt_Alt7 = 0x07, /*!< External reference voltage alt 7. */ + COMP_ExtVrefVolt_Alt8 = 0x08, /*!< External reference voltage alt 8. */ + COMP_ExtVrefVolt_Alt9 = 0x09, /*!< External reference voltage alt 9. */ + COMP_ExtVrefVolt_Alt10 = 0x0A, /*!< External reference voltage alt 10. */ + COMP_ExtVrefVolt_Alt11 = 0x0B, /*!< External reference voltage alt 11. */ + COMP_ExtVrefVolt_Alt12 = 0x0C, /*!< External reference voltage alt 12. */ + COMP_ExtVrefVolt_Alt13 = 0x0D, /*!< External reference voltage alt 13. */ + COMP_ExtVrefVolt_Alt14 = 0x0E, /*!< External reference voltage alt 14. */ + COMP_ExtVrefVolt_Alt15 = 0x0F, /*!< External reference voltage alt 15. */ +} COMP_ExtVrefVolt_Type; + +/*! + * @brief COMP round robin period type. + * + * wait n APB clock to compare next channel. + */ +typedef enum +{ + COMP_RoundRobinPeriod_1 = 0x00, /*!< Wait 1 PCLK to compare next channel. */ + COMP_RoundRobinPeriod_2 = 0x01, /*!< Wait 2 PCLK to compare next channel. */ + COMP_RoundRobinPeriod_4 = 0x02, /*!< Wait 4 PCLK to compare next channel. */ + COMP_RoundRobinPeriod_8 = 0x03, /*!< Wait 8 PCLK to compare next channel. */ + COMP_RoundRobinPeriod_16 = 0x04, /*!< Wait 16 PCLK to compare next channel. */ + COMP_RoundRobinPeriod_32 = 0x05, /*!< Wait 32 PCLK to compare next channel. */ + COMP_RoundRobinPeriod_64 = 0x06, /*!< Wait 64 PCLK to compare next channel. */ + COMP_RoundRobinPeriod_128 = 0x07, /*!< Wait 128 PCLK to compare next channel. */ +} COMP_RoundRobinPeriod_Type; + +/*! + * @brief COMP round robin channel Type. + */ +typedef enum +{ + COMP_RoundRobinChnGroup_Alt0 = 0x00, /*!< Compare the positive input 1 & 2. */ + COMP_RoundRobinChnGroup_Alt1 = 0x01, /*!< Compare the positive input 1, 2 & 3. */ +} COMP_RoundRobinChnGroup_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref COMP_Init() to initialize the COMP module. + */ +typedef struct +{ + COMP_Hysteresis_Type Hysteresis; /*!< Specify the hysteresis. */ + COMP_OutMux_Type OutMux; /*!< Specify the output. */ + COMP_InMux_Type PosInMux; /*!< Specify the positive input. */ + COMP_InMux_Type InvInMux; /*!< Specify the nagetive input. */ + COMP_Speed_Type Speed; /*!< Specify the compare speed. */ +} COMP_Init_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref COMP_EnableExtVrefConf() to enable the COMP ext vref. + */ +typedef struct +{ + COMP_ExtVrefSource_Type VrefSource; /*!< Specify the Vref source. */ + COMP_ExtVrefVolt_Type Volt; /*!< Specify the Vref voltage. */ +} COMP_ExtVrefConf_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref COMP_EnableRoundRobinConf() to enable the COMP round robin. + */ +typedef struct +{ + COMP_RoundRobinPeriod_Type Period; /*!< Specify the round robin period. */ + bool EnableInvInFix; /*!< Specify the nagetive input fix. */ + COMP_RoundRobinChnGroup_Type ChnGroup; /*!< Specify the round robin channel. */ +} COMP_RoundRobinConf_Type; + +/*! + * @brief Initialize the COMP module. + * + * @param COMPx COMP instance. + * @param channel COMP channel. + * @param init Pointer to the initialization structure. See to @ref COMP_Init_Type. + * @return None. + */ +void COMP_Init(COMP_Type * COMPx, uint32_t channel, COMP_Init_Type * init); + +/*! + * @brief Enable the COMP module. + * + * @param COMPx COMP instance. + * @param channel COMP channel. + * @param enable 'true' to enable the module, 'false' to disable the module. + * @return None. + */ +void COMP_Enable(COMP_Type * COMPx, uint32_t channel, bool enable); + +/*! + * @brief Keep the COMP settings not changed. + * + * @param COMPx COMP instance. + * @param channel COMP channel. + * @return None. + */ +void COMP_Lock(COMP_Type * COMPx, uint32_t channel); + +/*! + * @brief Get comp output status. + * + * @param COMPx COMP instance. + * @param channel COMP channel. + * @return output status. + */ +bool COMP_GetOutputStatus(COMP_Type * COMPx, uint32_t channel); + +/*! + * @brief Enable the COMP ext Vref. + * + * @param COMPx COMP instance. + * @param init Pointer to the initialization structure. See to @ref COMP_ExtVrefConf_Type, if null, disable ext Vref. + * @return None. + */ +void COMP_EnableExtVrefConf(COMP_Type * COMPx, COMP_ExtVrefConf_Type * conf); + +/*! + * @brief Enable polling function. + * + * Enable round robin function, the comp channel can get positive input 1, 2 & 3 status. + * + * @param COMPx COMP instance. + * @param channel COMP channel. + * @param init Pointer to the initialization structure. See to @ref COMP_RoundRobinConf_Type, if null, disable round robin. + * @return None. + */ +void COMP_EnableRoundRobinConf(COMP_Type * COMPx, uint32_t channel, COMP_RoundRobinConf_Type * conf); + +/*! + * @brief Get round robin output status. + * + * @param COMPx COMP instance. + * @param channel COMP channel. + * @param pos_in Positive input Mux. + * @return Status of comp channel output level. + */ +bool COMP_GetRoundRobinOutStatus(COMP_Type * COMPx, uint32_t channel, COMP_InMux_Type pos_in); + +/*! + * @brief Enable COMP window control. + * + * @param COMPx COMP instance. + * @param channel COMP channel. + * @param enable 'true' to enable window control, 'false' to disable window control. + * @return None. + */ +void COMP_EnableWindow(COMP_Type * COMPx, uint32_t channel, bool enable); + +/*! + * @brief Set the output filter. + * + * @param COMPx COMP instance. + * @param channel COMP channel. + * @param filter Output filter, See to @ref COMP_OutFilter_Type. + * @return None. + */ +void COMP_SetOutFilter(COMP_Type * COMPx, uint32_t channel, COMP_OutFilter_Type filter); + +/*! + * @brief Enable the out invert. + * + * @param COMPx COMP instance. + * @param channel COMP channel. + * @param enable 'true' to enable the out invert, 'false' to disable the out invert. + * @return None. + */ +void COMP_EnableOutInvert(COMP_Type * COMPx, uint32_t channel, bool enable); + +/*! + * @brief Enable the bypass output. + * + * @param COMPx COMP instance. + * @param channel COMP channel. + * @param enable 'true' to enable the bypass output, 'false' to disable the bypass output. + * @return None. + */ +void COMP_EnableBypassOutput(COMP_Type * COMPx, uint32_t channel, bool enable); + +/*! + *@} + */ + +#endif /* __HAL_COMP_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_crc.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_crc.c new file mode 100644 index 000000000..1a700ca47 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_crc.c @@ -0,0 +1,39 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_crc.h" + +/* CRC initialization. */ +void CRC_Init(CRC_Type * CRCx, CRC_Init_Type * init) +{ + CRCx->CR &= ~(CRC_PR_PR_MASK | CRC_CR_RO_MASK | CRC_CR_RI_MASK | CRC_CR_BEO_MASK | CRC_CR_BEI_MASK); + CRCx->PR &= ~CRC_PR_PR_MASK; + CRCx->CR |= CRC_CR_PWIDTH(init->PolynomialWidth) | CRC_CR_RO(init->OutRev) + | CRC_CR_RI(init->InRev) | CRC_CR_BEO(init->OutEndian) | CRC_CR_BEI(init->InEndian); + CRCx->PR = CRC_PR_PR(init->Polynomial); +} + +/* Set the value in CRC calculation unit as the initial value. */ +void CRC_SetSeed(CRC_Type * CRCx, uint32_t val) +{ + CRCx->IVR = CRC_IVR_IVR(val); + CRCx->CR |= CRC_CR_RST_MASK; +} + +/* Set data for CRC calculation. */ +void CRC_SetData(CRC_Type * CRCx, uint32_t val) +{ + CRCx->DR = val; +} + +/* Get CRC calculation result. */ +uint32_t CRC_GetResult(CRC_Type * CRCx) +{ + return CRCx->DR; +} + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_crc.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_crc.h new file mode 100644 index 000000000..a227f1e95 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_crc.h @@ -0,0 +1,102 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_CRC_H__ +#define __HAL_CRC_H__ + +#include "hal_common.h" + +/*! + * @addtogroup CRC + * @{ + */ + +/*! + * @brief CRC polynomail width type. + */ +typedef enum +{ + CRC_PolynomialWidth_32b = 0, /*!< Polynomial Width 32 bits. */ + CRC_PolynomialWidth_16b = 1, /*!< Polynomial Width 16 bits. */ + CRC_PolynomialWidth_8b = 2, /*!< Polynomial Width 8 bits. */ +} CRC_PolynomialWidth_Type; + +/*! + * @brief Whether the data in reverse order. + */ +typedef enum +{ + CRC_Rev_Normal = 0, /*!< Transfer data in normal order. */ + CRC_Rev_Rev = 1, /*!< Transfer data in reverse order. */ +} CRC_Rev_Type; + +/*! + * @brief The data endian is little-endian or big-endian. + */ +typedef enum +{ + CRC_DataEndian_LittleEndian = 0, /*!< Specofy the data endian is little-endian. */ + CRC_DataEndian_BigEndian = 1, /*!< Specofy the data endian is big-endian. */ +} CRC_DataEndian_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref CRC_Init() to initialize the CRC module. + */ +typedef struct +{ + uint32_t Polynomial; /*!< Configure arbitrary polynomial. */ + CRC_PolynomialWidth_Type PolynomialWidth; /*!< Specify the CRC polynomial width. */ + CRC_DataEndian_Type InEndian; /*!< Specify input endian is little-endian or big-endian. */ + CRC_DataEndian_Type OutEndian; /*!< Specify output endian is little-endian or big-ndian. */ + CRC_Rev_Type InRev; /*!< Specify whether the input data in reverse order. */ + CRC_Rev_Type OutRev; /*!< Specify whether the output data in reverse order. */ +} CRC_Init_Type; + +/*! + * @brief Initialize the CRC module. + * + * Initialize polynomial width, polynomial and input/output configuration + * The highest power of polynomial is determined by polynomial width. + * + * @param CRCx CRC instance. + * @param init Pointer to the initialization structure. See to @ref CRC_Init_Type. + * @return None. + */ +void CRC_Init(CRC_Type * CRCx, CRC_Init_Type * init); + +/*! + * @brief Set the first data for CRC calculation. + * + * @param CRCx CRC instance. + * @param val The first data of CRC calculation. + * @return None. + */ +void CRC_SetSeed(CRC_Type * CRCx, uint32_t val); + +/*! + * @brief Set data for CRC calculation. + * + * @param CRCx CRC instance. + * @param val The value used for CRC calculation. + * @return None. + */ +void CRC_SetData(CRC_Type * CRCx, uint32_t val); + +/*! + * @brief Get the most recent result of CRC calculation. + * + * @param CRCx CRC instance. + * @return Return the most recent result of CRC calculation. + */ +uint32_t CRC_GetResult(CRC_Type * CRCx); + +/*! + *@} + */ + +#endif /*__HAL_CRC_H__. */ + diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_dac.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_dac.c new file mode 100644 index 000000000..e1da7b7b0 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_dac.c @@ -0,0 +1,338 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_dac.h" + +void DAC_Init(DAC_Type * DACx, uint32_t channel, DAC_Init_Type * init) +{ + uint32_t cr = 0u; + + cr = DACx->CR & ~(( DAC_CR_BOFF1_MASK + | DAC_CR_TEN1_MASK + ) << (channel<<4u)); /* Calculate the shift and clear the indicated bit. */ + + /* Enable Output Buffer. */ + if (init->EnableOutBuf == false) + { + cr |= (DAC_CR_BOFF1_MASK << (channel<<4u)); + } + + /* Trigger Source. */ + if (init->EnableTrigger) + { + cr |= ((DAC_CR_TEN1_MASK) << (channel<<4u)); + } + + DAC->CR = cr; +} + +void DAC_Enable(DAC_Type * DACx, uint32_t channel, bool enable) +{ + if (enable) + { + DACx->CR |= (DAC_CR_EN1_MASK << (channel << 4u)); + } + else + { + DACx->CR &= ~(DAC_CR_EN1_MASK << (channel << 4u)); + } +} + +void DAC_EnableChannelOutput(DAC_Type * DACx, uint32_t channel, bool enable) +{ + if (enable) + { + DACx->CR |= (DAC_CR_OEEN1_MASK << (channel << 4u)); + } + else + { + DACx->CR &= ~(DAC_CR_OEEN1_MASK << (channel << 4u)); + } +} + +uint32_t DAC_GetData(DAC_Type * DACx, uint32_t channel) +{ + uint32_t ret = 0u; + + if(channel == DAC_CHN_1) + { + ret = (DACx->DOR1 & DAC_DOR1_DACC1DOR_MASK); + } + else if (channel == DAC_CHN_2) + { + ret = (DACx->DOR2 & DAC_DOR2_DACC2DOR_MASK); + } + + return ret; +} + +uint32_t DAC_PutData(DAC_Type * DACx, uint32_t channel, uint32_t value, DAC_Align_Type align) +{ + uint32_t ret = 0u; + + switch (align) + { + case DAC_Align_8b_Dual: + { + DAC_PutDualChannelData8bRightAlign(DACx, value); + ret = DAC_GetData(DACx, DAC_CHN_1) | ( DAC_GetData(DACx, DAC_CHN_2) << 16u); + break; + } + case DAC_Align_8b_Right: + { + DAC_PutData8bRightAlign(DACx, channel, value); + ret = DAC_GetData(DACx, channel); + break; + } + case DAC_Align_12b_Left: + { + DAC_PutData12bLeftAlign(DACx, channel, value); + ret = DAC_GetData(DACx, channel); + break; + } + case DAC_Align_12b_Right: + { + DAC_PutData12bRightAlign(DACx, channel, value); + ret = DAC_GetData(DACx, channel); + break; + } + case DAC_Align_12b_Dual_Left: + { + DAC_PutDualChannelData12bLeftAlign(DACx, value); + ret = DAC_GetData(DACx, DAC_CHN_1) + | ( DAC_GetData(DACx, DAC_CHN_2) << 16u); + break; + } + case DAC_Align_12b_Dual_Right: + { + DAC_PutDualChannelData12bRightAlign(DACx, value); + ret = DAC_GetData(DACx, DAC_CHN_1) + | ( DAC_GetData(DACx, DAC_CHN_2) << 16u); + break; + } + default: + break; + } + return ret; +} + +void DAC_EnableAddNoise(DAC_Type * DACx, uint32_t channel, DAC_AddNoise_Init_Type * init) +{ + if (init == NULL) + { + DAC->CR &= ~(DAC_CR_WAVE1_MASK << (channel << 4u)); + } + else + { + DAC->CR |= (( DAC_CR_WAVE1(1u) /* Noise wave need to set WAVEx = 01. */ + | DAC_CR_MAMP1(init->AddNoise) + ) << (channel << 4u)); + } +} + +void DAC_EnableAddTriangle(DAC_Type * DACx, uint32_t channel, DAC_AddTriangle_Init_Type * init) +{ + if (init == NULL) + { + DAC->CR &= ~(DAC_CR_WAVE1_MASK << (channel << 4u)); + } + else + { + DAC->CR |= (( DAC_CR_WAVE1(2u) /* Noise wave need to set WAVEx = 1x. */ + | DAC_CR_MAMP1(init->AddTriangle) + ) << (channel << 4u)); + } +} + +void DAC_EnableDMA(DAC_Type * DACx, uint32_t channel, bool enable) +{ + if (enable) + { + DACx->CR |= (DAC_CR_DMAEN1_MASK << (channel<<4u)); + } + else + { + DACx->CR &= ~(DAC_CR_DMAEN1_MASK << (channel<<4u)); + } +} + +void DAC_DoSwTrigger(DAC_Type * DACx, uint32_t channel) +{ + DACx->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1_MASK << channel); +} + +void DAC_DoDualChannelSwTrigger(DAC_Type * DACx) +{ + DACx->SWTRIGR |= DAC_SWTRIGR_SWTRIG1_MASK + | DAC_SWTRIGR_SWTRIG2_MASK + ; +} + +uint32_t DAC_GetDataRegAddr(DAC_Type * DACx, uint32_t channel, DAC_Align_Type align) +{ + uint32_t ret = 0u; + + switch (align) + { + case DAC_Align_8b_Dual: + { + ret = DAC_GetDualChannelData8bRegAddr(DACx); + break; + } + case DAC_Align_8b_Right: + { + ret = DAC_GetData8bRegAddr(DACx, channel); + break; + } + case DAC_Align_12b_Left: + { + ret = DAC_GetData12bLeftRegAddr(DACx, channel); + break; + } + case DAC_Align_12b_Right: + { + ret = DAC_GetData12bRightRegAddr(DACx, channel); + break; + } + case DAC_Align_12b_Dual_Left: + { + ret = DAC_GetDualChannelData12bLeftRegAddr(DACx); + break; + } + case DAC_Align_12b_Dual_Right: + { + ret = DAC_GetDualChannelData12bRightRegAddr(DACx); + break; + } + default: + break; + } + return ret; +} + +/* input value bit[7:0]. 12b output: xxxxxxxx0000. */ +void DAC_PutData8bRightAlign(DAC_Type * DACx, uint32_t channel, uint32_t value) +{ + if (channel == DAC_CHN_1) + { + DACx->DHR8R1 = value; + } + else if (channel == DAC_CHN_2) + { + DACx->DHR8R2 = value; + } +} + +/* input value bit[15:4]. 12b output: xxxxxxxxxxxx. */ +void DAC_PutData12bLeftAlign(DAC_Type * DACx, uint32_t channel, uint32_t value) +{ + if (channel == DAC_CHN_1) + { + DACx->DHR12L1 = value; + } + else if (channel == DAC_CHN_2) + { + DACx->DHR12L2 = value; + } +} + +/* input value bit[11:0], 12b output: xxxxxxxxxxxx. */ +void DAC_PutData12bRightAlign(DAC_Type * DACx, uint32_t channel, uint32_t value) +{ + if (channel == DAC_CHN_1) + { + DACx->DHR12R1 = value; + } + else if (channel == DAC_CHN_2) + { + DACx->DHR12R2 = value; + } +} + +/* bit[15:8] for channel 2, bit[7:0] for channel 1. */ +void DAC_PutDualChannelData8bRightAlign(DAC_Type * DACx, uint32_t value) +{ + DACx->DHR8RD = value; +} + +/* bit[31:16] for channel 2, bit[15:0] for channel 1. */ +void DAC_PutDualChannelData12bLeftAlign(DAC_Type * DACx, uint32_t value) +{ + DACx->DHR12LD = value; +} + +/* bit[31:16] for channel 2, bit[15:0] for channel 1. */ +void DAC_PutDualChannelData12bRightAlign(DAC_Type * DACx, uint32_t value) +{ + DACx->DHR12RD = value; +} + +uint32_t DAC_GetData8bRegAddr(DAC_Type * DACx, uint32_t channel) +{ + uint32_t ret = 0u; + + if (channel == DAC_CHN_1) + { + ret = (uint32_t)(&(DACx->DHR8R1)); + } + else if (channel == DAC_CHN_2) + { + ret = (uint32_t)(&(DACx->DHR8R2)); + } + + return ret; +} + +uint32_t DAC_GetData12bLeftRegAddr(DAC_Type * DACx, uint32_t channel) +{ + uint32_t ret = 0u; + + if (channel == DAC_CHN_1) + { + ret = (uint32_t)(&(DACx->DHR12L1)); + } + else if (channel == DAC_CHN_2) + { + ret = (uint32_t)(&(DACx->DHR12L2)); + } + + return ret; +} + +uint32_t DAC_GetData12bRightRegAddr(DAC_Type * DACx, uint32_t channel) +{ + uint32_t ret = 0; + + if (channel == DAC_CHN_1) + { + ret = (uint32_t)(&(DACx->DHR12R1)); + } + else if (channel == DAC_CHN_2) + { + ret = (uint32_t)(&(DACx->DHR12R2)); + } + + return ret; +} + +uint32_t DAC_GetDualChannelData8bRegAddr(DAC_Type * DACx) +{ + return (uint32_t)(&(DACx->DHR8RD)); +} + +uint32_t DAC_GetDualChannelData12bLeftRegAddr(DAC_Type * DACx) +{ + return (uint32_t)(&(DACx->DHR12LD)); +} + +uint32_t DAC_GetDualChannelData12bRightRegAddr(DAC_Type * DACx) +{ + return (uint32_t)(&(DACx->DHR12RD)); +} + +/* EOF. */ + diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_dac.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_dac.h new file mode 100644 index 000000000..a398fe28f --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_dac.h @@ -0,0 +1,361 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_DAC_H__ +#define __HAL_DAC_H__ + +#include "hal_common.h" + +/*! + * @addtogroup DAC + * @{ + */ + +/*! + * @brief DAC driver version number. + */ +#define DAC_DRIVER_VERSION 0u /*!< dac_0. */ + +/*! + * @addtogroup DAC_CHANNEL_SELECTION + * @{ + */ +#define DAC_CHN_NUM (2u) /*!< The total number of DAC channel. */ +#define DAC_CHN_1 (0u) /*!< The selection of DAC Channel 1. */ +#define DAC_CHN_2 (1u) /*!< The selection of DAC Channel 2. */ +/*! + *@} + */ + +/*! + * @brief DAC align type. + */ +typedef enum +{ + DAC_Align_8b_Dual = 0u, /*!< The selection of dual channel data alignment of 8b right. */ + DAC_Align_8b_Right = 1u, /*!< The selection of single channel data alignment of 8b right. */ + DAC_Align_12b_Left = 2u, /*!< The selection of single channel data alignment of 12b left. */ + DAC_Align_12b_Right = 3u, /*!< The selection of single channel data alignment of 12b right. */ + DAC_Align_12b_Dual_Left = 4u, /*!< The selection of dual channel data alignment of 12b left. */ + DAC_Align_12b_Dual_Right = 5u, /*!< The selection of dual channel data alignment of 12b right. */ +} DAC_Align_Type; + +/*! + * @brief DAC LFSR unmask bit selector type for adding noise wave. + */ +typedef enum +{ + DAC_AddNoise_LFSRUnMask_0 = 0u, /*!< Unmask DAC channel LFSR bit0. */ + DAC_AddNoise_LFSRUnMask_1 = 1u, /*!< Unmask DAC channel LFSR bit[1:0]. */ + DAC_AddNoise_LFSRUnMask_2 = 2u, /*!< Unmask DAC channel LFSR bit[2:0]. */ + DAC_AddNoise_LFSRUnMask_3 = 3u, /*!< Unmask DAC channel LFSR bit[3:0]. */ + DAC_AddNoise_LFSRUnMask_4 = 4u, /*!< Unmask DAC channel LFSR bit[4:0]. */ + DAC_AddNoise_LFSRUnMask_5 = 5u, /*!< Unmask DAC channel LFSR bit[5:0]. */ + DAC_AddNoise_LFSRUnMask_6 = 6u, /*!< Unmask DAC channel LFSR bit[6:0]. */ + DAC_AddNoise_LFSRUnMask_7 = 7u, /*!< Unmask DAC channel LFSR bit[7:0]. */ + DAC_AddNoise_LFSRUnMask_8 = 8u, /*!< Unmask DAC channel LFSR bit[8:0]. */ + DAC_AddNoise_LFSRUnMask_9 = 9u, /*!< Unmask DAC channel LFSR bit[9:0]. */ + DAC_AddNoise_LFSRUnMask_10 = 10u, /*!< Unmask DAC channel LFSR bit[10:0]. */ + DAC_AddNoise_LFSRUnMask_11 = 11u, /*!< Unmask DAC channel LFSR bit[11:0]. */ +} DAC_AddNoise_Type; + +/*! + * @brief DAC triangle amplitude selector type for adding triangle wave. + */ +typedef enum +{ + DAC_AddTriangle_LFSRAmplitude_1 = 0u, /*!< Max triangle amplitude of 1. */ + DAC_AddTriangle_LFSRAmplitude_3 = 1u, /*!< Max triangle amplitude of 3. */ + DAC_AddTriangle_LFSRAmplitude_7 = 2u, /*!< Max triangle amplitude of 7. */ + DAC_AddTriangle_LFSRAmplitude_15 = 3u, /*!< Max triangle amplitude of 15. */ + DAC_AddTriangle_LFSRAmplitude_31 = 4u, /*!< Max triangle amplitude of 31. */ + DAC_AddTriangle_LFSRAmplitude_63 = 5u, /*!< Max triangle amplitude of 63. */ + DAC_AddTriangle_LFSRAmplitude_127 = 6u, /*!< Max triangle amplitude of 127. */ + DAC_AddTriangle_LFSRAmplitude_255 = 7u, /*!< Max triangle amplitude of 255. */ + DAC_AddTriangle_LFSRAmplitude_511 = 8u, /*!< Max triangle amplitude of 511. */ + DAC_AddTriangle_LFSRAmplitude_1023 = 9u, /*!< Max triangle amplitude of 1023. */ + DAC_AddTriangle_LFSRAmplitude_2047 = 10u, /*!< Max triangle amplitude of 2047. */ + DAC_AddTriangle_LFSRAmplitude_4095 = 11u, /*!< Max triangle amplitude of 4095. */ +} DAC_AddTriangle_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref DAC_EnableAddNoise() to initialize the DAC noise wave generation. + */ +typedef struct +{ + DAC_AddNoise_Type AddNoise; /*!< Specify the noise wave pattern. */ +} DAC_AddNoise_Init_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref DAC_EnableAddTriangle() to initialize the DAC triangle wave generation. + */ +typedef struct +{ + DAC_AddTriangle_Type AddTriangle; /*!< Specify the triangle wave pattern. */ +} DAC_AddTriangle_Init_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref DAC_Init() to initialize the DAC module. + */ +typedef struct +{ + bool EnableTrigger; /*!< Specify whether to use the trigger and the trigger type. */ + bool EnableOutBuf; /*!< Specify whether output buffer is enabled. */ +} DAC_Init_Type; + +/*! + * @brief Initialize the DAC module. + * + * @param DACx DAC instance. + * @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION. + * @param init Pointer to the initialization structure. See to @ref DAC_Init_Type. + * @return None. + */ +void DAC_Init(DAC_Type * DACx, uint32_t channel, DAC_Init_Type * init); + +/*! + * @brief Enable the DAC module. + * + * The DAC module should be enabled before outputting voltage. + * + * @param DACx DAC instance. + * @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION. + * @param enable 'true' to enable the module, 'false' to disable the module. + * @return None. + */ +void DAC_Enable(DAC_Type * DACx, uint32_t channel, bool enable); + +/*! + * @brief Enable the DAC channel output. + * + * The DAC output channel should be enabled before outputting voltage. + * + * @param DACx DAC instance. + * @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION. + * @param enable 'true' to enable the DAC channel output, 'false' to disable the DAC channel output. + * @return None. + */ +void DAC_EnableChannelOutput(DAC_Type * DACx, uint32_t channel, bool enable); + +/*! + * @brief Get the echo data from the output of the indicated DAC channel. + * + * The value in DAC_DORx register takes effect on the actual output of DAC. + * + * @param DACx DAC instance. + * @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION. + * @return The indicated DAC channel data output value. + */ +uint32_t DAC_GetData(DAC_Type * DACx, uint32_t channel); + +/*! + * @brief Put the value into the indicated channel of the DAC module with the alignment. + * + * The value in DAC_DORx register takes effect on the actual output of DAC. + * + * @param DACx DAC instance. + * @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION. + * @param value Data value to be put in indicated DAC channel for conversion. + * @param align Alignment the value expected to be put into the conversion. See to @ref DAC_Align_Type. + * @return The current converted value of the indicated DAC channel. + */ +uint32_t DAC_PutData(DAC_Type * DACx, uint32_t channel, uint32_t value, DAC_Align_Type align); + +/*! + * @brief Enable the feature of generating noise wave from the DAC module. + * + * If enable additional noise wave, the output value will depend on the the unmask LFSR bit and input of the indicated channel. + * + * @param DACx DAC instance. + * @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION. + * @param init Pointer to the initialization structure. See to @ref DAC_AddNoise_Init_Type. If null, disable the wave generation. + * @return None. + */ +void DAC_EnableAddNoise(DAC_Type * DACx, uint32_t channel, DAC_AddNoise_Init_Type * init); + +/*! + * @brief Enable the feature of generating triangle wave from the DAC module. + * + * Defaultedly, DAC does not generate any wave. + * If enable additional triangle wave, the output value will depend on the the indicated amplitude and input of the indicated channel. + * + * @param DACx DAC instance. + * @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION. + * @param init Pointer to the initialization structure. See to @ref DAC_AddTriangle_Init_Type. If null, disable the wave generation. + * @return None. + */ +void DAC_EnableAddTriangle(DAC_Type * DACx, uint32_t channel, DAC_AddTriangle_Init_Type * init); + +/*! + * @brief Enable the DMA trigger from the DAC module. + * + * The DMA trigger events are the same as the intertupts. + * + * @param DACx DAC instance. + * @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION. + * @param enable 'true' to enable the DMA trigger, 'false' to disable the DMA trigger. + * @return None. + */ +void DAC_EnableDMA(DAC_Type * DACx, uint32_t channel, bool enable); + +/*! + * @brief Do trigger the indicated DAC channel with software trigger. + * + * @param DACx DAC instance. + * @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION. + * @return None. + */ +void DAC_DoSwTrigger(DAC_Type * DACx, uint32_t channel); + +/*! + * @brief Do trigger the dual DAC channels with software trigger simultaneously. + * + * @param DACx DAC instance. + * @return None. + */ +void DAC_DoDualChannelSwTrigger(DAC_Type * DACx); + +/*! + * @brief Get the indicated register address of the DAC module. + * + * @param DACx DAC instance. + * @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION. + * @param align Alignment that the data expects to br transferred. See to @ref DAC_Align_Type. + * @return The value of the address for indicated align type of the DAC channel. + */ +uint32_t DAC_GetDataRegAddr(DAC_Type * DACx, uint32_t channel, DAC_Align_Type align); + +/*! + * @brief Put 8-bit value into the indicated channel of the DAC module. + * + * The low 8-bit of the setting value here will be output with 4-bit left shift. + * If the value is 0x1f, the output will be 0x1f0. + * + * @param DACx DAC instance. + * @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION. + * @param value Data value to be put in indicated DAC channel for conversion. + * @return None. + */ +void DAC_PutData8bRightAlign(DAC_Type * DACx, uint32_t channel, uint32_t value); + +/*! + * @brief Put the 12-bit value into indicated channel of the DAC module. + * + * The low 12-bit of the setting value here will be output after 4-bit right shift. + * If the value is 0x1ff, the output will be 0x1f. + * + * @param DACx DAC instance. + * @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION. + * @param value Data value to be put in indicated DAC channel for conversion. + * @return None. + */ +void DAC_PutData12bLeftAlign(DAC_Type * DACx, uint32_t channel, uint32_t value); + +/*! + * @brief Put the current data into indicated channel of the DAC module. + * + * The low 12-bit of the setting value here will output with the original value. + * + * @param DACx DAC instance. + * @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION. + * @param value Data value to be put in indicated DAC channel for conversion. + * @return None. + */ +void DAC_PutData12bRightAlign(DAC_Type * DACx, uint32_t channel, uint32_t value); + +/*! + * @brief Respectively put the value into the dual channels of the DAC module 8b right aligned. + * + * Simultaneously output the low 8-bit of the low 16-bit and high 16-bit of the 32-bit value seperately with a 4-bit left shift. + * If value is 0x011f01ff, the output of each channel will be 0xff0 ( channel 1 ) and 0x1f0 ( channel 2 ). + * + * @param DACx DAC instance. + * @param value Data value to be put in DAC channel 1 and DAC channel 2 for conversion. + * @return None. + */ +void DAC_PutDualChannelData8bRightAlign(DAC_Type * DACx, uint32_t value); + +/*! + * @brief Put the data into the dual channel of the DAC module 12b left aligned. + * + * Simultaneously output the high 12-bit of the low 16-bit and high 16-bit of the 32-bit value seperately after 4-bit right shift. + * If value is 0x011f01ff, the output of each channel will be 0x01f ( channel 1 ) and 0x011 ( channel 2 ). + * + * @param DACx DAC instance. + * @param value Data value to be put in DAC channel 1 and DAC channel 2 for conversion. + * @return None. + */ +void DAC_PutDualChannelData12bLeftAlign(DAC_Type * DACx, uint32_t value); + +/*! + * @brief Put the data into the dual channel of the DAC module 12b right aligned. + * + * Simultaneously output the low 12-bit of the low 16-bit and high 16-bit of the 32-bit value seperately. + * + * @param DACx DAC instance. + * @param value Data value to be put in DAC channel 1 and DAC channel 2 for conversion. + * @return None. + */ +void DAC_PutDualChannelData12bRightAlign(DAC_Type * DACx, uint32_t value); + +/*! + * @brief Get the 8-bit data register address of the DAC module. + * + * @param DACx DAC instance. + * @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION. + * @return The value of the address for DAC module's 8-bit data register . + */ +uint32_t DAC_GetData8bRegAddr(DAC_Type * DACx, uint32_t channel); + +/*! + * @brief Get the 12-bit left-aligned data register address of the DAC module. + * + * @param DACx DAC instance. + * @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION. + * @return The value of the address for DAC module's 12-bit left-aligned data register . + */ +uint32_t DAC_GetData12bLeftRegAddr(DAC_Type * DACx, uint32_t channel); + +/*! + * @brief Get the 12-bit right-aligned data register address of the DAC module. + * + * @param DACx DAC instance. + * @param channel Indicated DAC channel. See to @ref DAC_CHANNEL_SELECTION. + * @return The value of the address for DAC module's 12-bit right-aligned data register . + */ +uint32_t DAC_GetData12bRightRegAddr(DAC_Type * DACx, uint32_t channel); + +/*! + * @brief Get the dual channel 8-bit data register address of the DAC module. + * + * @param DACx DAC instance. + * @return The value of the address for DAC module's dual channel 8-bit data register . + */ +uint32_t DAC_GetDualChannelData8bRegAddr(DAC_Type * DACx); + +/*! + * @brief Get the dual channel 12-bit left-aligned data register address of the DAC module. + * + * @param DACx DAC instance. + * @return The value of the address for DAC module's 12-bit dual channel left-aligned data register . + */ +uint32_t DAC_GetDualChannelData12bLeftRegAddr(DAC_Type * DACx); + +/*! + * @brief Get the dual channel 12-bit right-aligned data register address of the DAC module. + * + * @param DACx DAC instance. + * @return The value of the address for DAC module's 12-bit dual channel right-aligned data register . + */ +uint32_t DAC_GetDualChannelData12bRightRegAddr(DAC_Type * DACx); + +/*! + *@} + */ + +#endif /* __HAL_DAC_H__ */ + diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_dma.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_dma.c new file mode 100644 index 000000000..b4c22e236 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_dma.c @@ -0,0 +1,96 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_dma.h" + +/* clear all the interrupt enables and disable the dma channel. */ +uint32_t DMA_InitChannel(DMA_Type * DMAx, uint32_t channel, DMA_Channel_Init_Type * init) +{ + uint32_t ccr = 0u; + + if ( (init->XferMode == DMA_XferMode_MemoryToPeriph) + || (init->XferMode == DMA_XferMode_MemoryToPeriphBurst) ) + { + ccr |= DMA_CCR_DIR_MASK; + } + + if ( (init->XferMode == DMA_XferMode_PeriphToMemoryBurst) + || (init->XferMode == DMA_XferMode_MemoryToPeriphBurst) ) + { + ccr |= DMA_CCR_MEM2MEM_MASK; + } + + if (init->ReloadMode == DMA_ReloadMode_AutoReload) + { + ccr |= DMA_CCR_ARE_MASK; + } + else if (init->ReloadMode == DMA_ReloadMode_AutoReloadContinuous) + { + ccr |= (DMA_CCR_ARE_MASK | DMA_CCR_CIRC_MASK); + } + + ccr |= DMA_CCR_PINC(init->PeriphAddrIncMode) + | DMA_CCR_MINC(init->MemAddrIncMode) + | DMA_CCR_PSIZE(init->XferWidth) + | DMA_CCR_MSIZE(init->XferWidth) + | DMA_CCR_PL(init->Priority) + ; + + DMAx->CH[channel].CCR = ccr; + DMAx->CH[channel].CNDTR = init->XferCount; + DMAx->CH[channel].CPAR = init->PeriphAddr; + DMAx->CH[channel].CMAR = init->MemAddr; + + return 0u; +} + +void DMA_EnableChannelInterrupts(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts, bool enable) +{ + if (enable) + { + DMAx->CH[channel].CCR |= (interrupts & 0xEu); + } + else + { + DMAx->CH[channel].CCR &= ~(interrupts & 0xEu); + } +} + +uint32_t DMA_GetChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel) +{ + return (DMAx->ISR >> (channel * 4u)) & 0xFu; +} + +void DMA_ClearChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts) +{ + DMAx->IFCR = ( (interrupts & 0xFu) << (channel * 4u) ); +} + +void DMA_EnableChannel(DMA_Type * DMAx, uint32_t channel, bool enable) +{ + if (enable) + { + DMAx->CH[channel].CCR |= DMA_CCR_EN_MASK; + } + else + { + DMAx->CH[channel].CCR &= ~DMA_CCR_EN_MASK; + } +} + +void DMA_EnableBurstMode(DMA_Type * DMAx, uint32_t channel, bool enable) +{ + if (enable) + { + DMAx->CH[channel].CCR |= DMA_CCR_BURSTEN_MASK; + } + else + { + DMAx->CH[channel].CCR &= ~DMA_CCR_BURSTEN_MASK; + } +} +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_dma.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_dma.h new file mode 100644 index 000000000..dff14b851 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_dma.h @@ -0,0 +1,162 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_DMA_H__ +#define __HAL_DMA_H__ + +#include "hal_common.h" + +/*! + * @addtogroup DMA + * @{ + */ + +/*! + * @addtogroup DMA_CHANNEL_INT + * @{ + */ +#define DMA_CHN_INT_XFER_GLOBAL (0x1u << 0u) /*!< DMA global interrupt channel. */ +#define DMA_CHN_INT_XFER_DONE (0x1u << 1u) /*!< DMA end of transfer interrupt channel. */ +#define DMA_CHN_INT_XFER_HALF_DONE (0x1u << 2u) /*!< DMA half transfer interrupt channel. */ +#define DMA_CHN_INT_XFER_ERR (0x1u << 3u) /*!< DMA transfer error interrupt channel. */ +/*! + * @} + */ + + +/*! + * @brief Define the enum type of DMA_XferMode_Type. + */ +typedef enum +{ + DMA_XferMode_PeriphToMemory = 0u, /*!< memory to memory mode, from periph addr to memory addr. */ + DMA_XferMode_MemoryToPeriph = 1u, /*!< memory to memory mode, from periph addr to memory addr. */ + DMA_XferMode_PeriphToMemoryBurst = 2u, /*!< memory to memory mode, from periph addr to memory addr. */ + DMA_XferMode_MemoryToPeriphBurst = 3u, /*!< memory to memory mode, from memory addr to periph addr. */ +} DMA_XferMode_Type; + +/*! + * @brief Define the enum type of DMA_ReloadMode_Type. + */ +typedef enum +{ + DMA_ReloadMode_OneTime = 0u, /*!< the count is exhausted after the xfer is done. */ + DMA_ReloadMode_AutoReload = 1u, /*!< auto reload the count for the new xfer. */ + DMA_ReloadMode_AutoReloadContinuous = 2u, /*!< auto reload the count for the next xfer, and always run. */ +} DMA_ReloadMode_Type; + +/*! + * @brief Incremental mode of peripherals and memories. + */ +typedef enum +{ + DMA_AddrIncMode_StayAfterXfer = 0u, /*!< Peripheral access address accumulation. */ + DMA_AddrIncMode_IncAfterXfer = 1u, /*!< Memory access address accumulation. */ +} DMA_AddrIncMode_Type; + +/*! + * @brief Define the enum type of DMA xfer width type. + */ +typedef enum +{ + DMA_XferWidth_8b = 0u, /*!< Xfer width 8 bits. */ + DMA_XferWidth_16b = 1u, /*!< Xfer width 16 bits. */ + DMA_XferWidth_32b = 2u, /*!< Xfer width 32 bits. */ +} DMA_XferWidth_Type; + +/*! + * @brief Configure DMA Priority. + */ +typedef enum +{ + DMA_Priority_Low = 0u, /*!< Low Priority. */ + DMA_Priority_Middle = 1u, /*!< Middle Priority. */ + DMA_Priority_High = 2u, /*!< High Priority. */ + DMA_Priority_Highest = 3u, /*!< Highest Priority. */ +} DMA_Priority_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref DMA_InitChannel() to initialize the DMA module. + */ +typedef struct +{ + DMA_XferMode_Type XferMode; /*!< Specify whether the Receive or Transmit mode is enabled or not. */ + DMA_ReloadMode_Type ReloadMode; /*!< Specify whether to automatically reload the next transfer count when the count is exhausted. */ + DMA_AddrIncMode_Type PeriphAddrIncMode; /*!< Specify peripheral Address Inc Mode. */ + DMA_AddrIncMode_Type MemAddrIncMode; /*!< Specify Memory Address Inc Mode. */ + DMA_XferWidth_Type XferWidth; /*!< Specify the transmission data width. */ + DMA_Priority_Type Priority; /*!< Specify priority mode. */ + uint32_t XferCount; /*!< Specify CircularMode's count. */ + uint32_t MemAddr; /*!< Specify Memory Address. */ + uint32_t PeriphAddr; /*!< Specify Periph Address. */ +} DMA_Channel_Init_Type; + +/*! + * @brief Initialize the DMA module. + * + * @param DMAx DMA instance. + * @param channel Channel corresponding to DMA controller. + * @param init Pointer to the initialization structure. See to @ref DMA_Channel_Init_Type. + * @return None. + */ +uint32_t DMA_InitChannel(DMA_Type * DMAx, uint32_t channel, DMA_Channel_Init_Type * init); + +/*! + * @brief enable the DMA channel interrupts of the DMA module. + * + * @param DMAx DMA instance. + * @param channel Channel corresponding to DMA controller. + * @param interrupts Interrupt code masks. See to @ref DMA_CHANNEL_INT. + * @param enable 'true' to enable the DMA channel interrupts, 'false' to disable the DMA channel interrupts. + * @return None. + */ +void DMA_EnableChannelInterrupts(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts, bool enable); + +/*! + * @brief Get the channel interrupts status flags of the DMA module. + * + * @param DMAx DMA instance. + * @param channel Channel corresponding to DMA controller in DMA. See to @ref DMA_CHANNEL_INT. + * @return Interrupt status flags. + */ +uint32_t DMA_GetChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel); + +/*! + * @brief Clear the channel interrupts status flags of the DMA module. + * + * @param DMAx DMA instance. + * @param channel Channel corresponding to DMA controller. See to @ref DMA_CHANNEL_INT. + * @param interrupts Interrupt code masks. + * @return None. + */ +void DMA_ClearChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts); + +/*! + * @brief Enable the channel of the DMA module. + * + * @param DMAx DMA instance. + * @param channel Channel corresponding to DMA controller. + * @param enable 'true' to enable the DMA controller sends a reply signal to the peripheral, 'false' to disable the DMA controller sends a reply signal to the peripheral. + * @return None. + */ +void DMA_EnableChannel(DMA_Type * DMAx, uint32_t channel, bool enable); + +/*! + * @brief Enable the burst mode of the DMA module. + * + * @param DMAx DMA instance. +* @param channel Channel corresponding to DMA controller. + * @param enable 'true' to enable the DMA controller sends a reply signal to the peripheral, 'false' to disable the DMA controller sends a reply signal to the peripheral. + * @return None. + */ +void DMA_EnableBurstMode(DMA_Type * DMAx, uint32_t channel, bool enable); + +/*! + *@} + */ + +#endif /* __HAL_DMA_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_dma_request.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_dma_request.h new file mode 100644 index 000000000..084b3817b --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_dma_request.h @@ -0,0 +1,196 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_DMA_REQUESET_H__ +#define __HAL_DMA_REQUESET_H__ + +/* DMA1 Requests Remap. */ +/* ADC1. */ +#define DMA_REQ_DMA1_ADC1 0u + +/* ADC2. */ +#define DMA_REQ_DMA1_ADC2 1u + +/* SPI1. */ +#define DMA_REQ_DMA1_SPI1_RX 1u +#define DMA_REQ_DMA1_SPI1_TX 2u + +/* SPI2. */ +#define DMA_REQ_DMA1_SPI2_RX 3u +#define DMA_REQ_DMA1_SPI2_TX 4u + +/* UART1. */ +#define DMA_REQ_DMA1_UART1_TX 3u +#define DMA_REQ_DMA1_UART1_RX 4u + +/* UART2. */ +#define DMA_REQ_DMA1_UART2_TX 5u +#define DMA_REQ_DMA1_UART2_RX 6u + +/* UART3. */ +#define DMA_REQ_DMA1_UART3_TX 1u +#define DMA_REQ_DMA1_UART3_RX 2u + +/* UART4. */ + +/* UART5. */ + +/* UART6. */ +#define DMA_REQ_DMA1_UART6_RX 0u +#define DMA_REQ_DMA1_UART6_TX 7u + +/* UART7. */ + +/* I2C1. */ +#define DMA_REQ_DMA1_I2C1_TX 5u +#define DMA_REQ_DMA1_I2C1_RX 6u + +/* I2C2. */ +#define DMA_REQ_DMA1_I2C2_TX 3u +#define DMA_REQ_DMA1_I2C2_RX 4u + +/* TIM1. */ +#define DMA_REQ_DMA1_TIM1_CC1 1u +#define DMA_REQ_DMA1_TIM1_CC2 2u +#define DMA_REQ_DMA1_TIM1_CC4 3u +#define DMA_REQ_DMA1_TIM1_UP 4u +#define DMA_REQ_DMA1_TIM1_CC3 5u +#define DMA_REQ_DMA1_TIM1_TRIG_2 6u +#define DMA_REQ_DMA1_TIM1_COM_2 7u + +#define DMA_REQ_DMA1_TIM1_TRIG_1 3u + +#define DMA_REQ_DMA1_TIM1_COM_1 3u + +/* TIM2. */ +#define DMA_REQ_DMA1_TIM2_CC3_1 0u +#define DMA_REQ_DMA1_TIM2_UP_1 1u +#define DMA_REQ_DMA1_TIM2_UP_2 2u +#define DMA_REQ_DMA1_TIM2_CC1 4u +#define DMA_REQ_DMA1_TIM2_CC2 6u +#define DMA_REQ_DMA1_TIM2_UP_3 7u + +#define DMA_REQ_DMA1_TIM2_CC3_2 2u +#define DMA_REQ_DMA1_TIM2_CC4_1 6u +#define DMA_REQ_DMA1_TIM2_CC4_2 7u + +/* TIM3. */ +#define DMA_REQ_DMA1_TIM3_CC3 1u +#define DMA_REQ_DMA1_TIM3_CC4 2u +#define DMA_REQ_DMA1_TIM3_CC1 5u +#define DMA_REQ_DMA1_TIM3_CC2 7u + +#define DMA_REQ_DMA1_TIM3_UP 2u +#define DMA_REQ_DMA1_TIM3_TRIG 5u + +/* TIM4. */ +#define DMA_REQ_DMA1_TIM4_CC1 0u +#define DMA_REQ_DMA1_TIM4_CC2 3u +#define DMA_REQ_DMA1_TIM4_CC3 4u +#define DMA_REQ_DMA1_TIM4_UP 6u +#define DMA_REQ_DMA1_TIM4_CC4 7u + +/* TIM5. */ + +/* TIM6. */ + +/* TIM7. */ + +/* TIM8. */ + +/* FELXCAN1. */ +#define DMA_REQ_DMA1_FLEXCAN1_RX 7u + +/* QSPI. */ + +/* DMA2 Requests Remap. */ +/* ADC. */ + +/* DAC. */ +#define DMA_REQ_DMA2_DAC_CH1_1 2u +#define DMA_REQ_DMA2_DAC_CH2_1 3u +#define DMA_REQ_DMA2_DAC_CH1_2 6u + +#define DMA_REQ_DMA2_DAC_CH2_2 6u + +/* SPI3. */ +#define DMA_REQ_DMA2_SPI3_RX 0u +#define DMA_REQ_DMA2_SPI3_TX 1u + +/* UART4. */ +#define DMA_REQ_DMA2_UART4_RX_1 2u +#define DMA_REQ_DMA2_UART4_TX_1 4u +#define DMA_REQ_DMA2_UART4_RX_2 6u +#define DMA_REQ_DMA2_UART4_TX_2 7u + +/* UART5. */ +#define DMA_REQ_DMA2_UART5_RX 0u +#define DMA_REQ_DMA2_UART5_TX 1u + +/* UART6. */ +#define DMA_REQ_DMA2_UART6_TX 3u +#define DMA_REQ_DMA2_UART6_RX 5u + +/* UART7. */ +#define DMA_REQ_DMA2_UART7_RX_1 0u +#define DMA_REQ_DMA2_UART7_TX_1 1u +#define DMA_REQ_DMA2_UART7_RX_2 6u +#define DMA_REQ_DMA2_UART7_TX_2 7u + +/* LPUART. */ +#define DMA_REQ_DMA2_LPUART_TX 3u +#define DMA_REQ_DMA2_LPUART_RX 5u + +/* I2C. */ + +/* TIM1. */ + +/* TIM2. */ + +/* TIM3. */ + +/* TIM4. */ + +/* TIM5. */ +#define DMA_REQ_DMA2_TIM5_CC4 0u +#define DMA_REQ_DMA2_TIM5_CC3 1u +#define DMA_REQ_DMA2_TIM5_CC2 3u +#define DMA_REQ_DMA2_TIM5_CC1 4u +#define DMA_REQ_DMA2_TIM5_UP_2 5u + +#define DMA_REQ_DMA2_TIM5_TRIG 0u +#define DMA_REQ_DMA2_TIM5_UP_1 1u + +/* TIM6. */ +#define DMA_REQ_DMA2_TIM6_UP_1 2u +#define DMA_REQ_DMA2_TIM6_UP_2 5u + +/* TIM7. */ +#define DMA_REQ_DMA2_TIM7_UP_1 3u +#define DMA_REQ_DMA2_TIM7_UP_2 5u + +/* TIM8. */ +#define DMA_REQ_DMA2_TIM8_CC3 0u +#define DMA_REQ_DMA2_TIM8_CC4 1u +#define DMA_REQ_DMA2_TIM8_CC1 2u +#define DMA_REQ_DMA2_TIM8_CC2 4u +#define DMA_REQ_DMA2_TIM8_UP_2 5u +#define DMA_REQ_DMA2_TIM8_TRIG_2 6u +#define DMA_REQ_DMA2_TIM8_COM_2 7u + +#define DMA_REQ_DMA2_TIM8_UP_1 0u +#define DMA_REQ_DMA2_TIM8_TRIG_1 1u + +#define DMA_REQ_DMA2_TIM8_COM_1 1u + +/* FELXCAN2. */ +#define DMA_REQ_DMA2_FLEXCAN2_RX 5u + +/* QSPI. */ +#define DMA_REQ_DMA2_QSPI 7u + +#endif /* __HAL_DMA_REQUESET_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_exti.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_exti.c new file mode 100644 index 000000000..3b443446f --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_exti.c @@ -0,0 +1,74 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "hal_exti.h" + +void EXTI_EnableLineInterrupt(EXTI_Type * EXTIx, uint32_t lines, bool enable) +{ + if (enable) + { + EXTIx->IMR |= lines; + } + else + { + EXTIx->IMR &= ~ lines; + } +} + +void EXTI_EnableLineEvent(EXTI_Type * EXTIx, uint32_t lines, bool enable) +{ + if (enable) + { + EXTIx->EMR |= lines; + } + else + { + EXTIx->EMR &= ~ lines; + } +} + +void EXTI_SetTriggerIn(EXTI_Type * EXTIx, uint32_t lines, EXTI_TriggerIn_Type trgin) +{ + switch (trgin) + { + case EXTI_TriggerIn_Disable: + EXTIx->RTSR &= ~ lines; + EXTIx->FTSR &= ~ lines; + break; + case EXTI_TriggerIn_RisingEdge: + EXTI->RTSR |= lines; + EXTIx->FTSR &= ~ lines; + break; + case EXTI_TriggerIn_FallingEdge: + EXTI->RTSR &= ~ lines; + EXTI->FTSR |= lines; + break; + case EXTI_TriggerIn_BothEdges: + EXTI->RTSR |= lines; + EXTI->FTSR |= lines; + break; + default: + break; + } +} + +void EXTI_DoSwTrigger(EXTI_Type * EXTIx, uint32_t lines) +{ + EXTIx->SWIER = lines; +} + +uint32_t EXTI_GetLineStatus(EXTI_Type * EXTIx) +{ + return EXTIx->PR; +} + +void EXTI_ClearLineStatus(EXTI_Type * EXTIx, uint32_t lines) +{ + EXTIx->PR |= lines; +} + +/* EOF. */ + diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_exti.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_exti.h new file mode 100644 index 000000000..95fb4596a --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_exti.h @@ -0,0 +1,128 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_EXTI_H__ +#define __HAL_EXTI_H__ + +#include "hal_common.h" + +/*! + * @addtogroup EXTI + * @{ + */ + +/*! + * @brief EXTI driver version number. + */ +#define EXTI_DRIVER_VERSION 0u /*!< exti_0. */ + +/*! + * @addtogroup EXTI_LINE + * @{ + */ +#define EXTI_LINE_0 (1u << 0u) /*!MCR &= ~ FLEXCAN_MCR_MDIS_MASK; /* Unmask the module disable. */ + } + else + { + FLEXCANx->MCR |= FLEXCAN_MCR_MDIS_MASK; + } +} + +void FLEXCAN_DoSoftReset(FLEXCAN_Type * FLEXCANx) +{ + /* Wait for exiting from low power mode. */ + while ( 0u != (FLEXCANx->MCR & FLEXCAN_MCR_LPMACK_MASK) ) + { + } + FLEXCANx->MCR |= FLEXCAN_MCR_SOFTRST_MASK; + while ( 0u != (FLEXCANx->MCR & FLEXCAN_MCR_SOFTRST_MASK) ) + { + } + + /* Enable overall warning interrupt. Detailed tx warning and rx warning will be setup by detailed func.*/ + FLEXCANx->MCR |= (FLEXCAN_MCR_WRNEN_MASK | FLEXCAN_MCR_LPRIOEN_MASK); + /* Set sampling mode, using three sampling points. */ + FLEXCANx->CTRL1 |= FLEXCAN_CTRL1_SMP_MASK; + /* No response automatically generated after receiving remote frame. */ + FLEXCANx->CTRL2 |= ( FLEXCAN_CTRL2_RRS_MASK + | FLEXCAN_CTRL2_EACEN_MASK + ); + + /* Get the defaulted max message buffer number. */ + uint32_t mb_num = ( (FLEXCANx->MCR & FLEXCAN_MCR_MAXMB_MASK) >> FLEXCAN_MCR_MAXMB_SHIFT ); + + /* Clear the individual mask and CS for all message buffers. */ + for (uint32_t i = 0u; i <= mb_num; i++) + { + FLEXCANx->RXIMRN[i] = 0x3FFFFFFFu; /* Defaultedly, this mask value is for standard data frame. */ + FLEXCAN_ResetMb(FLEXCANx, i); + } + + /* Clear the global mask. */ + FLEXCANx->RXMGMASK = 0x3FFFFFFFu; + FLEXCANx->RX14MASK = 0x3FFFFFFFu; + FLEXCANx->RX15MASK = 0x3FFFFFFFu; + FLEXCANx->RXFGMASK = 0x3FFFFFFFu; +} + +bool FLEXCAN_Init(FLEXCAN_Type * FLEXCANx, FLEXCAN_Init_Type * init) +{ + /* Just enable the module shortly for soft reset. */ + FLEXCAN_Enable(FLEXCANx, true); + + /* softreset the module to enter freezemode and do some default setup. */ + FLEXCAN_DoSoftReset(FLEXCANx); + + /* Clear register setting bit and save other settings. */ + uint32_t mcr = FLEXCANx->MCR & ~ ( FLEXCAN_MCR_SLFWAK_MASK + | FLEXCAN_MCR_WAKSRC_MASK + | FLEXCAN_MCR_MAXMB_MASK + | FLEXCAN_MCR_SRXDIS_MASK + | FLEXCAN_MCR_IRMQ_MASK + ); + uint32_t ctrl1 = FLEXCANx->CTRL1 & ~ ( FLEXCAN_CTRL1_LOM_MASK + | FLEXCAN_CTRL1_LPB_MASK + | FLEXCAN_CTRL1_CLKSRC_MASK + | FLEXCAN_CTRL1_BOFFREC_MASK + | FLEXCAN_CTRL1_TSYN_MASK + ); + + uint32_t ctrl2 = FLEXCANx->CTRL2 & ~ ( FLEXCAN_CTRL2_RRS_MASK + | FLEXCAN_CTRL2_EACEN_MASK + ); + + /* Select the work mode. */ + switch (init->WorkMode) + { + case FLEXCAN_WorkMode_LoopBack: + ctrl1 |= FLEXCAN_CTRL1_LPB_MASK; + break; + case FLEXCAN_WorkMode_ListenOnly: + ctrl1 |= FLEXCAN_CTRL1_LOM_MASK; + break; + case FLEXCAN_WorkMode_Normal: + break; + } + + /* Set the self wake up mechanism. */ + switch (init->SelfWakeUp) + { + case FLEXCAN_SelfWakeUp_BypassFilter: + mcr |= FLEXCAN_MCR_SLFWAK_MASK; + break; + case FLEXCAN_SelfWakeUp_WithFilter: + mcr |= ( FLEXCAN_MCR_SLFWAK_MASK + | FLEXCAN_MCR_WAKSRC_MASK + ); + break; + case FLEXCAN_SelfWakeUp_Disabled: + break; + default: + break; + } + + /* Set the max number of message buffer to be used during xferring. */ + mcr |= FLEXCAN_MCR_MAXMB(init->MaxXferNum); + + /* If enable timer synchronization. */ + if ( init->EnableTimerSync ) + { + ctrl1 |= FLEXCAN_CTRL1_TSYN_MASK; + } + + /* Set the global mask or individual mask. */ + if (init->Mask == FLEXCAN_Mask_Individual) + { + mcr |= FLEXCAN_MCR_IRMQ_MASK; + } + + /* Enable the self reception for self rx frame. */ + if (!init->EnableSelfReception) + { + mcr |= FLEXCAN_MCR_SRXDIS_MASK; + } + + /* Set the clock source of protocol engine. */ + ctrl1 |= FLEXCAN_CTRL1_CLKSRC(init->ClockSource); + /* Store the remote request but not automatically generate a response. */ + ctrl2 |= ( FLEXCAN_CTRL2_RRS_MASK + | FLEXCAN_CTRL2_EACEN_MASK /* Enable comparison of IDE and RTR. */ + ); + + /* Write back to the register. */ + FLEXCANx->MCR = mcr; + FLEXCANx->CTRL1 = ctrl1; + FLEXCANx->CTRL2 = ctrl2; + + /* Calculate divider and set timing. */ + /* Calculate the time quantum for resynchronization. */ + uint32_t quantum = ( 1u + + ( init->TimConf->PropSegLen + 1u ) + + ( init->TimConf->PhaSegLen1 + 1u ) + + ( init->TimConf->PhaSegLen2 + 1u ) + ); + /* Check validity. */ + if ( (quantum * init->BaudRate > init->ClockFreqHz) || (init->BaudRate == 0u) ) + { + return false; + } + /* Calculate the prescaler value. */ + init->TimConf->PreDiv = init->ClockFreqHz / ( quantum * init->BaudRate ) - 1u; + + FLEXCAN_SetTimingConf(FLEXCANx, init->TimConf); + + return true; +} + +void FLEXCAN_SetTimingConf(FLEXCAN_Type * FLEXCANx, FLEXCAN_TimConf_Type * conf) +{ + /* Enter freeze mode before setting timing parameters. */ + FLEXCAN_EnableFreezeMode(FLEXCANx, true); + + /* If use extended then set up the CBT reg. */ + if ( conf->EnableExtendedTime ) + { + /* clear extended timing conf. */ + uint32_t cbt = FLEXCANx->CBT & ~ ( FLEXCAN_CBT_BTF_MASK + | FLEXCAN_CBT_EPRESDIV_MASK + | FLEXCAN_CBT_ERJW_MASK + | FLEXCAN_CBT_EPROPSEG_MASK + | FLEXCAN_CBT_EPSEG1_MASK + | FLEXCAN_CBT_EPSEG2_MASK + ); + cbt = FLEXCAN_CBT_BTF_MASK + | FLEXCAN_CBT_EPRESDIV(conf->PreDiv) + | FLEXCAN_CBT_EPSEG1(conf->PhaSegLen1) + | FLEXCAN_CBT_EPSEG2(conf->PhaSegLen2) + | FLEXCAN_CBT_EPROPSEG(conf->PropSegLen) + | FLEXCAN_CBT_ERJW(conf->JumpWidth); + FLEXCANx->CBT = cbt; + } + else + { + /* Clear registers for writing. */ + uint32_t ctrl1 = FLEXCANx->CTRL1 & ~ ( FLEXCAN_CTRL1_PRESDIV_MASK + | FLEXCAN_CTRL1_PSEG1_MASK + | FLEXCAN_CTRL1_PSEG2_MASK + | FLEXCAN_CTRL1_PROPSEG_MASK + | FLEXCAN_CTRL1_RJW_MASK + ); + ctrl1 |= FLEXCAN_CTRL1_PRESDIV(conf->PreDiv) + | FLEXCAN_CTRL1_PSEG1(conf->PhaSegLen1) + | FLEXCAN_CTRL1_PSEG2(conf->PhaSegLen2) + | FLEXCAN_CTRL1_PROPSEG(conf->PropSegLen) + | FLEXCAN_CTRL1_RJW(conf->JumpWidth); + FLEXCANx->CTRL1 = ctrl1; + } + + /* Exit the freeze mode after setting timing parameters. */ + FLEXCAN_EnableFreezeMode(FLEXCANx, false); +} + +void FLEXCAN_EnableFreezeMode(FLEXCAN_Type * FLEXCANx, bool enable) +{ + if (enable) + { + FLEXCANx->MCR |= ( FLEXCAN_MCR_FRZ_MASK | FLEXCAN_MCR_HALT_MASK ); + + /* Wait a period of time for entering. */ + while (0u == (FLEXCANx->MCR & FLEXCAN_MCR_FRZACK_MASK)) + { + } + } + else + { + FLEXCANx->MCR &= ~( FLEXCAN_MCR_FRZ_MASK | FLEXCAN_MCR_HALT_MASK ); + + /* Wait a period of time for entirely exiting. */ + while (0u != (FLEXCANx->MCR & FLEXCAN_MCR_FRZACK_MASK)) + { + } + } +} + +/* RXMGMASK register macro. */ +#define FLEXCAN_RXMGMASK_RTR_SHIFT (31u) +#define FLEXCAN_RXMGMASK_RTR_MASK (0x1u << FLEXCAN_RXMGMASK_RTR_SHIFT) +#define FLEXCAN_RXMGMASK_RTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXMGMASK_RTR_SHIFT)) & FLEXCAN_RXMGMASK_RTR_MASK) +#define FLEXCAN_RXMGMASK_IDE_SHIFT (30u) +#define FLEXCAN_RXMGMASK_IDE_MASK (0x1u << FLEXCAN_RXMGMASK_IDE_SHIFT) +#define FLEXCAN_RXMGMASK_IDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXMGMASK_IDE_SHIFT)) & FLEXCAN_RXMGMASK_IDE_MASK) +#define FLEXCAN_RXMGMASK_STD_SHIFT (18u) +#define FLEXCAN_RXMGMASK_STD_MASK (0x7FFU << FLEXCAN_RXMGMASK_STD_SHIFT) +#define FLEXCAN_RXMGMASK_STD(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXMGMASK_STD_SHIFT)) & FLEXCAN_RXMGMASK_STD_MASK) +#define FLEXCAN_RXMGMASK_EXT_SHIFT (0u) +#define FLEXCAN_RXMGMASK_EXT_MASK (0x1FFFFFFFu << FLEXCAN_RXMGMASK_EXT_SHIFT) +#define FLEXCAN_RXMGMASK_EXT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXMGMASK_EXT_SHIFT)) & FLEXCAN_RXMGMASK_EXT_MASK) + +void FLEXCAN_SetGlobalMbMaskConf(FLEXCAN_Type * FLEXCANx, FLEXCAN_RxMbMaskConf_Type * conf) +{ + /* Calculate the mask value. */ + uint32_t mask = ( FLEXCAN_RXMGMASK_RTR(conf->MbType) + | FLEXCAN_RXMGMASK_IDE(conf->MbFormat) + | ( (conf->MbFormat == FLEXCAN_MbFormat_Extended) ? (FLEXCAN_RXMGMASK_EXT(conf->IdMask)) : (FLEXCAN_RXMGMASK_STD(conf->IdMask)) ) + ); + + FLEXCANx->RXMGMASK = mask; + FLEXCANx->RX14MASK = mask; + FLEXCANx->RX15MASK = mask; +} + +/* RXFGMASK register macro. */ +#define FLEXCAN_RXFGMASK_RXIDA_RTR_SHIFT (31u) +#define FLEXCAN_RXFGMASK_RXIDA_RTR_MASK (0x1u << FLEXCAN_RXFGMASK_RXIDA_RTR_SHIFT) +#define FLEXCAN_RXFGMASK_RXIDA_RTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDA_RTR_SHIFT)) & FLEXCAN_RXFGMASK_RXIDA_RTR_MASK) +#define FLEXCAN_RXFGMASK_RXIDA_IDE_SHIFT (30u) +#define FLEXCAN_RXFGMASK_RXIDA_IDE_MASK (0x1u << FLEXCAN_RXFGMASK_RXIDA_IDE_SHIFT) +#define FLEXCAN_RXFGMASK_RXIDA_IDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDA_IDE_SHIFT)) & FLEXCAN_RXFGMASK_RXIDA_IDE_MASK) +#define FLEXCAN_RXFGMASK_RXIDA_STD_SHIFT (19u) +#define FLEXCAN_RXFGMASK_RXIDA_STD_MASK (0x7FFu << FLEXCAN_RXFGMASK_RXIDA_STD_SHIFT) +#define FLEXCAN_RXFGMASK_RXIDA_STD(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDA_STD_SHIFT)) & FLEXCAN_RXFGMASK_RXIDA_STD_MASK) +#define FLEXCAN_RXFGMASK_RXIDA_EXT_SHIFT (1u) +#define FLEXCAN_RXFGMASK_RXIDA_EXT_MASK (0x1FFFFFFFu << FLEXCAN_RXFGMASK_RXIDA_EXT_SHIFT) +#define FLEXCAN_RXFGMASK_RXIDA_EXT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDA_EXT_SHIFT)) & FLEXCAN_RXFGMASK_RXIDA_EXT_MASK) + +#define FLEXCAN_RXFGMASK_RXIDB_RTR_HIGH_SHIFT (31u) +#define FLEXCAN_RXFGMASK_RXIDB_RTR_HIGH_MASK (0x1u << FLEXCAN_RXFGMASK_RXIDB_RTR_HIGH_SHIFT) +#define FLEXCAN_RXFGMASK_RXIDB_RTR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDB_RTR_HIGH_SHIFT)) & FLEXCAN_RXFGMASK_RXIDB_RTR_HIGH_MASK) +#define FLEXCAN_RXFGMASK_RXIDB_IDE_HIGH_SHIFT (30u) +#define FLEXCAN_RXFGMASK_RXIDB_IDE_HIGH_MASK (0x1u << FLEXCAN_RXFGMASK_RXIDB_IDE_HIGH_SHIFT) +#define FLEXCAN_RXFGMASK_RXIDB_IDE_HIGH(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDB_IDE_HIGH_SHIFT)) & FLEXCAN_RXFGMASK_RXIDB_IDE_HIGH_MASK) +#define FLEXCAN_RXFGMASK_RXIDB_STD_HIGH_SHIFT (19u) +#define FLEXCAN_RXFGMASK_RXIDB_STD_HIGH_MASK (0x7FFu << FLEXCAN_RXFGMASK_RXIDB_STD_HIGH_SHIFT) +#define FLEXCAN_RXFGMASK_RXIDB_STD_HIGH(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDB_STD_HIGH_SHIFT)) & FLEXCAN_RXFGMASK_RXIDB_STD_HIGH_MASK) +#define FLEXCAN_RXFGMASK_RXIDB_EXT_HIGH_SHIFT (16u) +#define FLEXCAN_RXFGMASK_RXIDB_EXT_HIGH_MASK (0x3FFFu << FLEXCAN_RXFGMASK_RXIDB_EXT_HIGH_SHIFT) +#define FLEXCAN_RXFGMASK_RXIDB_EXT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDB_EXT_HIGH_SHIFT)) & FLEXCAN_RXFGMASK_RXIDB_EXT_HIGH_MASK) +#define FLEXCAN_RXFGMASK_RXIDB_RTR_LOW_SHIFT (15u) +#define FLEXCAN_RXFGMASK_RXIDB_RTR_LOW_MASK (0x1u << FLEXCAN_RXFGMASK_RXIDB_RTR_LOW_SHIFT) +#define FLEXCAN_RXFGMASK_RXIDB_RTR_LOW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDB_RTR_LOW_SHIFT)) & FLEXCAN_RXFGMASK_RXIDB_RTR_LOW_MASK) +#define FLEXCAN_RXFGMASK_RXIDB_IDE_LOW_SHIFT (14u) +#define FLEXCAN_RXFGMASK_RXIDB_IDE_LOW_MASK (0x1u << FLEXCAN_RXFGMASK_RXIDB_IDE_LOW_SHIFT) +#define FLEXCAN_RXFGMASK_RXIDB_IDE_LOW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDB_IDE_LOW_SHIFT)) & FLEXCAN_RXFGMASK_RXIDB_IDE_LOW_MASK) +#define FLEXCAN_RXFGMASK_RXIDB_STD_LOW_SHIFT (3u) +#define FLEXCAN_RXFGMASK_RXIDB_STD_LOW_MASK (0x7FFu << FLEXCAN_RXFGMASK_RXIDB_STD_LOW_SHIFT) +#define FLEXCAN_RXFGMASK_RXIDB_STD_LOW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDB_STD_LOW_SHIFT)) & FLEXCAN_RXFGMASK_RXIDB_STD_LOW_MASK) +#define FLEXCAN_RXFGMASK_RXIDB_EXT_LOW_SHIFT (0u) +#define FLEXCAN_RXFGMASK_RXIDB_EXT_LOW_MASK (0x3FFFu << FLEXCAN_RXFGMASK_RXIDB_EXT_LOW_SHIFT) +#define FLEXCAN_RXFGMASK_RXIDB_EXT_LOW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDB_EXT_LOW_SHIFT)) & FLEXCAN_RXFGMASK_RXIDB_EXT_LOW_MASK) + +#define FLEXCAN_RXFGMASK_RXIDC_HIGH_SHIFT (24u) +#define FLEXCAN_RXFGMASK_RXIDC_HIGH_MASK (0xFFu << FLEXCAN_RXFGMASK_RXIDC_HIGH_SHIFT) +#define FLEXCAN_RXFGMASK_RXIDC_HIGH(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDC_HIGH_SHIFT)) & FLEXCAN_RXFGMASK_RXIDC_HIGH_MASK) +#define FLEXCAN_RXFGMASK_RXIDC_MIDHIGH_SHIFT (16u) +#define FLEXCAN_RXFGMASK_RXIDC_MIDHIGH_MASK (0xFFu << FLEXCAN_RXFGMASK_RXIDC_MIDHIGH_SHIFT) +#define FLEXCAN_RXFGMASK_RXIDC_MIDHIGH(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDC_MIDHIGH_SHIFT)) & FLEXCAN_RXFGMASK_RXIDC_MIDHIGH_MASK) +#define FLEXCAN_RXFGMASK_RXIDC_MIDLOW_SHIFT (8u) +#define FLEXCAN_RXFGMASK_RXIDC_MIDLOW_MASK (0xFFu << FLEXCAN_RXFGMASK_RXIDC_MIDLOW_SHIFT) +#define FLEXCAN_RXFGMASK_RXIDC_MIDLOW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDC_MIDLOW_SHIFT)) & FLEXCAN_RXFGMASK_RXIDC_MIDLOW_MASK) +#define FLEXCAN_RXFGMASK_RXIDC_LOW_SHIFT (0u) +#define FLEXCAN_RXFGMASK_RXIDC_LOW_MASK (0xFFu << FLEXCAN_RXFGMASK_RXIDC_LOW_SHIFT) +#define FLEXCAN_RXFGMASK_RXIDC_LOW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_RXIDC_LOW_SHIFT)) & FLEXCAN_RXFGMASK_RXIDC_LOW_MASK) + +void FLEXCAN_SetRxFifoGlobalMaskConf(FLEXCAN_Type *FLEXCANx, FLEXCAN_RxFifoMaskConf_Type * conf) +{ + uint32_t mask = 0u; + /* Select filter format. */ + switch(conf->FilterFormat) + { + case FLEXCAN_FifoIdFilterFormat_A: + mask = ( FLEXCAN_RXFGMASK_RXIDA_RTR(conf->MbType) + | FLEXCAN_RXFGMASK_RXIDA_IDE(conf->MbFormat) + | ( (conf->MbFormat == FLEXCAN_MbFormat_Extended) ? FLEXCAN_RXFGMASK_RXIDA_EXT(conf->RxIdA) : FLEXCAN_RXFGMASK_RXIDA_STD(conf->RxIdA) ) + ); + break; + case FLEXCAN_FifoIdFilterFormat_B: + mask = ( FLEXCAN_RXFGMASK_RXIDB_RTR_HIGH(conf->MbType) + | FLEXCAN_RXFGMASK_RXIDB_IDE_HIGH(conf->MbFormat) + | ( (conf->MbFormat == FLEXCAN_MbFormat_Extended) ? FLEXCAN_RXFGMASK_RXIDB_EXT_HIGH(conf->RxIdB[0]) : FLEXCAN_RXFGMASK_RXIDB_STD_HIGH(conf->RxIdB[0]) ) + | FLEXCAN_RXFGMASK_RXIDB_RTR_LOW(conf->MbType) + | FLEXCAN_RXFGMASK_RXIDB_IDE_LOW(conf->MbFormat) + | ( (conf->MbFormat == FLEXCAN_MbFormat_Extended) ? FLEXCAN_RXFGMASK_RXIDB_EXT_LOW(conf->RxIdB[1]) : FLEXCAN_RXFGMASK_RXIDB_STD_LOW(conf->RxIdB[1]) ) + ); + break; + case FLEXCAN_FifoIdFilterFormat_C: + mask = ( FLEXCAN_RXFGMASK_RXIDC_HIGH(conf->RxIdC[0]) + | FLEXCAN_RXFGMASK_RXIDC_MIDHIGH(conf->RxIdC[1]) + | FLEXCAN_RXFGMASK_RXIDC_MIDLOW(conf->RxIdC[2]) + | FLEXCAN_RXFGMASK_RXIDC_LOW(conf->RxIdC[3]) + ); + break; + default: + break; + } + FLEXCANx->RXFGMASK = mask; +} + +void FLEXCAN_SetRxMbIndividualMaskConf(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_RxMbMaskConf_Type * conf) +{ + /* Calculate the mask value. */ + uint32_t mask = ( FLEXCAN_RXMGMASK_RTR(conf->MbType) + | FLEXCAN_RXMGMASK_IDE(conf->MbFormat) + | ( (conf->MbFormat == FLEXCAN_MbFormat_Extended) ? (FLEXCAN_RXMGMASK_EXT(conf->IdMask)) : (FLEXCAN_RXMGMASK_STD(conf->IdMask)) ) + ); + FLEXCANx->RXIMRN[channel] = mask; +} + +void FLEXCAN_ResetMb(FLEXCAN_Type * FLEXCANx, uint32_t channel) +{ + FLEXCANx->MB[channel].CS = 0u; + FLEXCANx->MB[channel].ID = 0u; + FLEXCANx->MB[channel].WORD0 = 0u; + FLEXCANx->MB[channel].WORD1 = 0u; +} + +void FLEXCAN_SetMbCode(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_MbCode_Type code) +{ + FLEXCANx->MB[channel].CS = (FLEXCANx->MB[channel].CS & ~FLEXCAN_CS_CODE_MASK) | FLEXCAN_CS_CODE(code); +} + +void FLEXCAN_SetRxMb(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_RxMbConf_Type * conf) +{ + if (NULL != conf) + { + uint32_t cs = 0u; + + /* Select the mb format type for seting ID area with different format. */ + if (conf->MbFormat == FLEXCAN_MbFormat_Extended) + { + cs |= FLEXCAN_CS_IDE_MASK; /* Set extended frame flag bit. */ + FLEXCANx->MB[channel].ID = ( (conf->Id) << FLEXCAN_ID_EXT_SHIFT ) & ( FLEXCAN_ID_EXT_MASK | FLEXCAN_ID_STD_MASK); + } + else + { + FLEXCANx->MB[channel].ID = FLEXCAN_ID_STD(conf->Id); + } + + /* Set RTR area for remote frame. */ + if (conf->MbType == FLEXCAN_MbType_Remote) + { + cs |= FLEXCAN_CS_RTR_MASK; + } + FLEXCANx->MB[channel].CS = cs; + /* FLEXCAN_SetMbCode(FLEXCANx, channel, FLEXCAN_MbCode_RxEmpty); */ + } + else + { + /* If not use Rx Mb anymore, just reset for neither Tx nor Rx. */ + FLEXCAN_ResetMb(FLEXCANx, channel); + } +} + +bool FLEXCAN_EnableRxFifo(FLEXCAN_Type * FLEXCANx, FLEXCAN_RxFifoConf_Type * conf) +{ + if ( NULL == conf ) + { + /* Disable the fifo. */ + FLEXCANx->MCR &= ~ FLEXCAN_MCR_RFEN_MASK; + /* Clear rffn value. */ + uint32_t rffn = ( (FLEXCANx->CTRL2 & FLEXCAN_CTRL2_RFFN_MASK) >> FLEXCAN_CTRL2_RFFN_SHIFT ); + uint32_t max_channel = 8u + rffn * 2u; + + /* Clear the mb used for fifo and fifo filters. */ + for (uint32_t i = 0u; i < max_channel; i++) + { + FLEXCAN_ResetMb(FLEXCANx, i); + } + } + else + { + /* Clear registers for setting. */ + uint32_t mcr = FLEXCANx->MCR & ~ ( FLEXCAN_MCR_RFEN_MASK + | FLEXCAN_MCR_IDAM_MASK + ); + uint32_t ctrl2 = FLEXCANx->CTRL2 & ~ ( FLEXCAN_CTRL2_RFFN_MASK + | FLEXCAN_CTRL2_MRP_MASK + ); + + /* Set FLEXCAN fifo filter format. */ + mcr |= FLEXCAN_MCR_IDAM(conf->FilterFormat); + + /* Calculate the mb to be used for fifo. */ + uint32_t max_mb = ( (FLEXCANx->MCR & FLEXCAN_MCR_MAXMB_MASK) >> FLEXCAN_MCR_MAXMB_SHIFT ); + max_mb = max_mb < 0xFu ? 0xFu : max_mb; + /* Calculate the rffn setting value from the Id filter number to be used. */ + uint32_t rffn = 0u; + for (uint32_t i = 0u; i < 0xFu; i++) + { + if ( ( ( i + 1u ) * 8u) >= (conf->IdFilterNum) ) + { + if ( max_mb < (6u + ( i + 1u ) * 2u) ) + { + return false; + } + rffn = i; + break; + } + } + ctrl2 |= FLEXCAN_CTRL2_RFFN(rffn); + + /* Set the filter value, for left Mb space, just set it all 1. */ + uint32_t idx = 0u; + for (uint32_t i = 6u; i < 6u + ( rffn + 1u ) * 2u; i++) + { + volatile uint32_t * mb = &(FLEXCANx->MB[i].CS); + for (uint32_t k = 0u; k < 4u; k++) + { + /* Fill all valid filter in the mail box occupied by filter. + * Disable unused Rx FIFO Filter, the other rest of register in the last Mail box occupied by fiter set + * as 0xffffffff. + */ + mb[k] = (idx < conf->IdFilterNum) ? (conf->IdFilterTable[idx]) : 0xFFFFFFFFU; + + /* Try to fill next filter in current Mail Box. */ + idx++; + } + } + + /* Set Rx priority between Mb and fifo. */ + if (FLEXCAN_FifoPriority_FifoFirst == conf->priority) + { + ctrl2 |= FLEXCAN_CTRL2_MRP_MASK; + } + + /* Enable the fifo. */ + mcr |= FLEXCAN_MCR_RFEN_MASK; + FLEXCANx->MCR = mcr; + FLEXCANx->CTRL2 = ctrl2; + + return true; + } + return false; +} + +void FLEXCAN_EnableInterrupts(FLEXCAN_Type * FLEXCANx, uint32_t interrupts, bool enable) +{ + uint32_t ctrl1 = FLEXCANx->CTRL1; + + /* Enable interrupts. */ + if (enable) + { + ctrl1 |= interrupts; + } + else + { + ctrl1 &= ~interrupts; + } + + FLEXCANx->CTRL1 = ctrl1; +} + +uint32_t FLEXCAN_GetStatus(FLEXCAN_Type * FLEXCANx) +{ + return FLEXCANx->ESR1; +} + +void FLEXCAN_ClearStatus(FLEXCAN_Type * FLEXCANx, uint32_t flags) +{ + FLEXCANx->ESR1 = flags; +} + +void FLEXCAN_EnableMbInterrupts(FLEXCAN_Type * FLEXCANx, uint32_t interrupts, bool enable) +{ + if (enable) + { + FLEXCANx->IMASK1 |= interrupts; + } + else + { + FLEXCANx->IMASK1 &= ~ interrupts; + } +} + +uint32_t FLEXCAN_GetMbStatus(FLEXCAN_Type * FLEXCANx) +{ + return FLEXCANx->IFLAG1; +} + +void FLEXCAN_ClearMbStatus(FLEXCAN_Type * FLEXCANx, uint32_t interrupts) +{ + FLEXCANx->IFLAG1 = interrupts; +} + +void FLEXCAN_EnableFifoDMA(FLEXCAN_Type * FLEXCANx, bool enable) +{ + if (enable) + { + FLEXCANx->MCR |= FLEXCAN_MCR_DMA_MASK; + } + else + { + FLEXCANx->MCR &= ~ FLEXCAN_MCR_DMA_MASK; + } +} + +uint32_t FLEXCAN_GetTxError(FLEXCAN_Type * FLEXCANx) +{ + return ( (FLEXCANx->ECR & FLEXCAN_ECR_TXERRCNT_MASK) >> FLEXCAN_ECR_TXERRCNT_SHIFT ); +} + +uint32_t FLEXCAN_GetRxError(FLEXCAN_Type * FLEXCANx) +{ + return ( (FLEXCANx->ECR & FLEXCAN_ECR_RXERRCNT_MASK) >> FLEXCAN_ECR_RXERRCNT_SHIFT ); +} + +uint32_t FLEXCAN_GetFifoAddr(FLEXCAN_Type * FLEXCANx) +{ + return (uint32_t)(&(FLEXCANx->MB[0].CS)); +} + +bool FLEXCAN_WriteTxMb(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_Mb_Type * mb) +{ + if ( FLEXCAN_MbCode_TxDataOrRemote != ( (FLEXCANx->MB[channel].CS & FLEXCAN_CS_CODE_MASK) >> FLEXCAN_CS_CODE_SHIFT ) ) + { + /* Reset the CODE for transfer. */ + uint32_t cs = (FLEXCANx->MB[channel].CS & ~ FLEXCAN_CS_CODE_MASK) | FLEXCAN_CS_CODE(FLEXCAN_MbCode_TxInactive); + + /* Switch mb format. */ + if (mb->FORMAT == FLEXCAN_MbFormat_Extended) + { + /* Extended Mb frame with longer ID. */ + FLEXCANx->MB[channel].ID = ( ( ( mb->ID ) & ( FLEXCAN_ID_STD_MASK | FLEXCAN_ID_EXT_MASK ) ) + | FLEXCAN_ID_PRIO(mb->PRIORITY) + ); + cs |= FLEXCAN_CS_SRR_MASK | FLEXCAN_CS_IDE_MASK; + } + else + { + FLEXCANx->MB[channel].ID = ( FLEXCAN_ID_STD(mb->ID) + | FLEXCAN_ID_PRIO(mb->PRIORITY) + ); + cs &= ~ (FLEXCAN_CS_SRR_MASK | FLEXCAN_CS_IDE_MASK); + } + + /* Switch Mb type. */ + if (mb->TYPE == FLEXCAN_MbType_Remote) + { + cs |= FLEXCAN_CS_RTR_MASK; + } + else + { + cs &= ~ FLEXCAN_CS_RTR_MASK; + } + + /* Set Mb length for Tx. */ + cs |= FLEXCAN_CS_DLC(mb->LENGTH); + FLEXCANx->MB[channel].WORD0 = mb->WORD0; + FLEXCANx->MB[channel].WORD1 = mb->WORD1; + FLEXCANx->MB[channel].CS = cs; /* Always set the CS area at last. */ + /* FLEXCAN_SetMbCode(FLEXCANx, channel, FLEXCAN_MbCode_TxDataOrRemote); */ + return true; + } + + return false; +} + +bool FLEXCAN_ReadRxMb(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_Mb_Type * mb) +{ + uint32_t cs = FLEXCANx->MB[channel].CS; + + /* Switch the Mb format to get the ID. */ + if ( 0u != (cs & FLEXCAN_CS_IDE_MASK) ) + { + mb->ID = FLEXCANx->MB[channel].ID; + mb->FORMAT = FLEXCAN_MbFormat_Extended; + } + else + { + mb->ID = ( (FLEXCANx->MB[channel].ID & FLEXCAN_ID_STD_MASK) >> FLEXCAN_ID_STD_SHIFT); + mb->FORMAT = FLEXCAN_MbFormat_Standard; + } + + /* Swith the Mb type. */ + if ( 0u != (cs & FLEXCAN_CS_RTR_MASK) ) + { + mb->TYPE = FLEXCAN_MbType_Remote; + } + else + { + mb->TYPE = FLEXCAN_MbType_Data; + } + + /* Get the valid data length. */ + mb->LENGTH = ( (cs & FLEXCAN_CS_DLC_MASK) >> FLEXCAN_CS_DLC_SHIFT ); + /* Get the Rx Mb frame timestamp. */ + mb->TIMESTAMP = ( (cs & FLEXCAN_CS_TIMESTAMP_MASK) >> FLEXCAN_CS_TIMESTAMP_SHIFT); + /* Read the data. */ + mb->WORD0 = FLEXCANx->MB[channel].WORD0; + mb->WORD1 = FLEXCANx->MB[channel].WORD1; + /* Unlock the Mb. */ + (void)FLEXCANx->TIMER; + return true; +} + +bool FLEXCAN_ReadRxFifo(FLEXCAN_Type * FLEXCANx, FLEXCAN_Mb_Type * mb) +{ + if ( 0u != ( FLEXCANx->MCR & FLEXCAN_MCR_RFEN_MASK ) ) /* If fifo is enabled, MB0 will be the only output of fifo. */ + { + /* Mb 0 is the fifo output. */ + FLEXCAN_ReadRxMb(FLEXCANx, 0u, mb); + /* Get the id filter hit number. */ + mb->IDHIT = (FLEXCANx->RXFIR & FLEXCAN_RXFIR_IDHIT_MASK); /* Get the fifo output idhit number. */ + return true; + } + else + { + (void)FLEXCANx->TIMER; /* Unlock the Mb. */ + return false; + } +} + +uint32_t FLEXCAN_GetMatchCrcValue(FLEXCAN_Type * FLEXCANx, uint32_t * channel) +{ + if (channel) + { + *channel = ( FLEXCANx->CRCR & FLEXCAN_CRCR_MBCRC_MASK) >> FLEXCAN_CRCR_MBCRC_SHIFT; /* Get the number of the Mb who has succeeded in arbitration for Tx. */ + } + + return FLEXCANx->CRCR & FLEXCAN_CRCR_TXCRC_MASK;/* Get the CRC value of the last Tx frame. */ +} + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_flexcan.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_flexcan.h new file mode 100644 index 000000000..9e1a66850 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_flexcan.h @@ -0,0 +1,606 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_FLEXCAN_H__ +#define __HAL_FLEXCAN_H__ + +#include "hal_common.h" + +/*! + * @addtogroup FLEXCAN + * @{ + */ + +/*! + * @brief FLEXCAN driver version number. + */ +#define FLEXCAN_DRIVER_VERSION 0u /*!< FLEXCAN_0. */ + +/*! + * @addtogroup FLEXCAN_GLOBAL_INT + * @{ + */ +#define FLEXCAN_INT_RWRN FLEXCAN_CTRL1_RWRNMSK_MASK /*!< Tx warning interrupt switchers. */ +#define FLEXCAN_INT_TWRN FLEXCAN_CTRL1_TWRNMSK_MASK /*!< Rx warning interrupt switchers. */ +#define FLEXCAN_INT_ERR FLEXCAN_CTRL1_ERRMSK_MASK /*!< Error interrupt switchers. */ +#define FLEXCAN_INT_BOFF FLEXCAN_CTRL1_BOFFMSK_MASK /*!< Bus off interrupt switchers. */ +/*! + * @} + */ + +/*! + * @addtogroup FLEXCAN_STATUS + * @{ + */ +#define FLEXCAN_STATUS_WAK (1 << 0u) /*!< Wake up interrupt flag. */ +#define FLEXCAN_STATUS_ERR (1 << 1u) /*!< Error interrupt flag. */ +#define FLEXCAN_STATUS_BOFF (1 << 2u) /*!< Bus off interrupt flag. */ +#define FLEXCAN_STATUS_RX (1 << 3u) /*!< Reception state flag. */ +#define FLEXCAN_STATUS_FLTCONF (0 << 4u) /*!< Fault confinement state flag. */ +#define FLEXCAN_STATUS_TX (1 << 6u) /*!< Transmission state flag. */ +#define FLEXCAN_STATUS_IDLE (1 << 7u) /*!< Idele state flag. */ +#define FLEXCAN_STATUS_RXWRN (1 << 8u) /*!< Rx error warning flag. */ +#define FLEXCAN_STATUS_TXWRN (1 << 9u) /*!< Tx error warning flag. */ +#define FLEXCAN_STATUS_STFERR (1 << 10u) /*!< Stuffing error flag. */ +#define FLEXCAN_STATUS_FMRERR (1 << 11u) /*!< Form error flag. */ +#define FLEXCAN_STATUS_CRCERR (1 << 12u) /*!< CRC error flag. */ +#define FLEXCAN_STATUS_ACKERR (1 << 13u) /*!< ACK error flag. */ +#define FLEXCAN_STATUS_BIT0ERR (1 << 14u) /*!< Bit 0 error flag. */ +#define FLEXCAN_STATUS_BIT1ERR (1 << 15u) /*!< Bit 1 error flag. */ +#define FLEXCAN_STATUS_RWRN (1 << 16u) /*!< Rx warning interrupt flag. */ +#define FLEXCAN_STATUS_TWRN (1 << 17u) /*!< Tx warning interrupt flag. */ +#define FLEXCAN_STATUS_SYNCH (1 << 18u) /*!< Synchronization status flag. */ +#define FLEXCAN_STATUS_BOFFDONE (1 << 19u) /*!< Bus off done interrupt flag. */ +#define FLEXCAN_STATUS_ERROVR (1 << 21u) /*!< Error Overrun interrupt flag. */ +/*! + * @} + */ + +/*! + * @addtogroup FLEXCAN_CHANNEL_SELECTION + * @{ + */ +#define FLEXCAN_CHN_NUM (16u) /*!< The total number of FLEXCAN channel. */ +#define FLEXCAN_CHN_0 (0u) /*!< The selection of FLEXCAN MB Channel 0. */ +#define FLEXCAN_CHN_1 (1u) /*!< The selection of FLEXCAN MB Channel 1. */ +#define FLEXCAN_CHN_2 (2u) /*!< The selection of FLEXCAN MB Channel 2. */ +#define FLEXCAN_CHN_3 (3u) /*!< The selection of FLEXCAN MB Channel 3. */ +#define FLEXCAN_CHN_4 (4u) /*!< The selection of FLEXCAN MB Channel 4. */ +#define FLEXCAN_CHN_5 (5u) /*!< The selection of FLEXCAN MB Channel 5. */ +#define FLEXCAN_CHN_6 (6u) /*!< The selection of FLEXCAN MB Channel 6. */ +#define FLEXCAN_CHN_7 (7u) /*!< The selection of FLEXCAN MB Channel 7. */ +#define FLEXCAN_CHN_8 (8u) /*!< The selection of FLEXCAN MB Channel 8. */ +#define FLEXCAN_CHN_9 (9u) /*!< The selection of FLEXCAN MB Channel 9. */ +#define FLEXCAN_CHN_10 (10u) /*!< The selection of FLEXCAN MB Channel 10. */ +#define FLEXCAN_CHN_11 (11u) /*!< The selection of FLEXCAN MB Channel 11. */ +#define FLEXCAN_CHN_12 (12u) /*!< The selection of FLEXCAN MB Channel 12. */ +#define FLEXCAN_CHN_13 (13u) /*!< The selection of FLEXCAN MB Channel 13. */ +#define FLEXCAN_CHN_14 (14u) /*!< The selection of FLEXCAN MB Channel 14. */ +#define FLEXCAN_CHN_15 (15u) /*!< The selection of FLEXCAN MB Channel 15. */ +/*! + *@} + */ + +/*! + * @addtogroup FLEXCAN_MB_INT + * @{ + */ +#define FLEXCAN_INT_MB_0 (1u << 0u) /*!< Individual Mb 0 interrupt and clear fifo switcher. */ +#define FLEXCAN_INT_MB_1 (1u << 1u) /*!< Individual Mb 1 interrupt switcher. */ +#define FLEXCAN_INT_MB_2 (1u << 2u) /*!< Individual Mb 2 interrupt switcher. */ +#define FLEXCAN_INT_MB_3 (1u << 3u) /*!< Individual Mb 3 interrupt switcher. */ +#define FLEXCAN_INT_MB_4 (1u << 4u) /*!< Individual Mb 4 interrupt switcher. */ +#define FLEXCAN_INT_MB_5 (1u << 5u) /*!< Individual Mb 5 interrupt and Rx fifo frame available switcher. */ +#define FLEXCAN_INT_MB_6 (1u << 6u) /*!< Individual Mb 6 interrupt and Rx fifo warning interrupt switcher. */ +#define FLEXCAN_INT_MB_7 (1u << 7u) /*!< Individual Mb 7 interrupt and Rx fifo overflow interrupt switcher. */ +#define FLEXCAN_INT_MB_8 (1u << 8u) /*!< Individual Mb 8 interrupt switcher. */ +#define FLEXCAN_INT_MB_9 (1u << 9u) /*!< Individual Mb 9 interrupt switcher. */ +#define FLEXCAN_INT_MB_10 (1u << 10u) /*!< Individual Mb 10 interrupt switcher. */ +#define FLEXCAN_INT_MB_11 (1u << 11u) /*!< Individual Mb 11 interrupt switcher. */ +#define FLEXCAN_INT_MB_12 (1u << 12u) /*!< Individual Mb 12 interrupt switcher. */ +#define FLEXCAN_INT_MB_13 (1u << 13u) /*!< Individual Mb 13 interrupt switcher. */ +#define FLEXCAN_INT_MB_14 (1u << 14u) /*!< Individual Mb 14 interrupt switcher. */ +#define FLEXCAN_INT_MB_15 (1u << 15u) /*!< Individual Mb 15 interrupt switcher. */ +/*! + * @} + */ + +/*! + * @addtogroup FLEXCAN_MB_STATUS + * @{ + */ +#define FLEXCAN_STATUS_MB_0 (1u << 0u) /*!< Individual Mb 0 interrupt and clear fifo switcher. */ +#define FLEXCAN_STATUS_MB_1 (1u << 1u) /*!< Individual Mb 1 interrupt switcher. */ +#define FLEXCAN_STATUS_MB_2 (1u << 2u) /*!< Individual Mb 2 interrupt switcher. */ +#define FLEXCAN_STATUS_MB_3 (1u << 3u) /*!< Individual Mb 3 interrupt switcher. */ +#define FLEXCAN_STATUS_MB_4 (1u << 4u) /*!< Individual Mb 4 interrupt switcher. */ +#define FLEXCAN_STATUS_MB_5 (1u << 5u) /*!< Individual Mb 5 interrupt and Rx fifo frame available switcher. */ +#define FLEXCAN_STATUS_MB_6 (1u << 6u) /*!< Individual Mb 6 interrupt and Rx fifo warning interrupt switcher. */ +#define FLEXCAN_STATUS_MB_7 (1u << 7u) /*!< Individual Mb 7 interrupt and Rx fifo overflow interrupt switcher. */ +#define FLEXCAN_STATUS_MB_8 (1u << 8u) /*!< Individual Mb 8 interrupt switcher. */ +#define FLEXCAN_STATUS_MB_9 (1u << 9u) /*!< Individual Mb 9 interrupt switcher. */ +#define FLEXCAN_STATUS_MB_10 (1u << 10u) /*!< Individual Mb 10 interrupt switcher. */ +#define FLEXCAN_STATUS_MB_11 (1u << 11u) /*!< Individual Mb 11 interrupt switcher. */ +#define FLEXCAN_STATUS_MB_12 (1u << 12u) /*!< Individual Mb 12 interrupt switcher. */ +#define FLEXCAN_STATUS_MB_13 (1u << 13u) /*!< Individual Mb 13 interrupt switcher. */ +#define FLEXCAN_STATUS_MB_14 (1u << 14u) /*!< Individual Mb 14 interrupt switcher. */ +#define FLEXCAN_STATUS_MB_15 (1u << 15u) /*!< Individual Mb 15 interrupt switcher. */ +/*! + * @} + */ + +/*! + * @brief FLEXCAN clock source type. + */ +typedef enum +{ + FLEXCAN_ClockSource_Osc = 0u, /*!< CAN Protocol Engine will use the Oscillator clock. */ + FLEXCAN_ClockSource_Periph = 1u, /*!< CAN Protocol Engine will use the Peripheral clock.*/ +} FLEXCAN_ClockSource_Type; + +/*! + * @brief FLEXCAN self wake up from bus off source. + */ +typedef enum +{ + FLEXCAN_SelfWakeUp_Disabled = 0u, /*!< Disable self wake up, FLEXCAN can only back from Stop mode when its request is cleared. */ + FLEXCAN_SelfWakeUp_BypassFilter = 1u, /*!< FLEXCAN can use the unfiltered Rx input to detect events on CAN bus then back from Stop mode. */ + FLEXCAN_SelfWakeUp_WithFilter = 2u, /*!< FLEXCAN can use the filtered Rx input to detect events on CAN bus then back from Stop mode. */ +} FLEXCAN_SelfWakeUp_Type; + +/*! + * @brief FLEXCAN function mode. + */ +typedef enum +{ + FLEXCAN_WorkMode_Normal = 0u, /*!< Normal work mode. */ + FLEXCAN_WorkMode_LoopBack = 1u, /*!< Loop-back working mode, transfer and receive its own frame. */ + FLEXCAN_WorkMode_ListenOnly = 2u, /*!< Listen-only mode, no transfer. */ +} FLEXCAN_WorkMode_Type; + +/*! + * @brief FLEXCAN Rx message buffer filter type. + */ +typedef enum +{ + FLEXCAN_Mask_Global = 0u, /*!< Use global mask to filter all the received frame. */ + FLEXCAN_Mask_Individual = 1u, /*!< Use individual mask to filter the received frame. */ +} FLEXCAN_Mask_Type; + +/*! + * @brief FLEXCAN Xfer Mb frame type switcher. + */ +typedef enum +{ + FLEXCAN_MbType_Data = 0u, /*!< Data frames can be accepted and remote frames are rejected. */ + FLEXCAN_MbType_Remote = 1u, /*!< Data frames can be rejected and remote frames are accepted. */ +} FLEXCAN_MbType_Type; + +/*! + * @brief FLEXCAN Xfer Mb frame format switcher. + */ +typedef enum +{ + FLEXCAN_MbFormat_Standard = 0u, /*!< Only Standard format frames can be accepted. */ + FLEXCAN_MbFormat_Extended = 1u, /*!< Only Extended format frames can be accepted. */ +} FLEXCAN_MbFormat_Type; + +/*! + * @brief FLEXCAN Rx fifo ID filter type. + */ +typedef enum +{ + FLEXCAN_FifoIdFilterFormat_A = 0u, /*!< Format A: One full ID (standard and extended) per ID Filter Table element. */ + FLEXCAN_FifoIdFilterFormat_B = 1u, /*!< Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element.*/ + FLEXCAN_FifoIdFilterFormat_C = 2u, /*!< Format C: Four partial 8-bit Standard IDs per ID Filter Table element. */ + FLEXCAN_FifoIdFilterFormat_D = 3u, /*!< Format D: All frames rejected. */ +} FLEXCAN_FifoIdFilterFormat_Type; + +/*! + * @brief FLEXCAN fifo priority type. + */ +typedef enum +{ + FLEXCAN_FifoPriority_MbFirst = 0u, /*!< Mactching process start with message buffer. */ + FLEXCAN_FifoPriority_FifoFirst = 1u, /*!< Mactching process start with fifo. */ +}FLEXCAN_FifoPriority_Type; + +/*! + * @brief FLEXCAN Xfer MB frame code switcher. + */ +typedef enum +{ + FLEXCAN_MbCode_RxInactive = 0u, /*!< Code for MB being not active. */ + FLEXCAN_MbCode_RxFull = 2u, /*!< Code for MB being full. */ + FLEXCAN_MbCode_RxEmpty = 4u, /*!< Code for MB being active and empty. */ + FLEXCAN_MbCode_RxOverrun = 6u, /*!< Code for MB being over written without accessing the received frame. */ + FLEXCAN_MbCode_TxInactive = 8u, /*!< Code for data response for Tx inactive. */ + FLEXCAN_MbCode_TxAbort = 9u, /*!< Code for Tx abort after transmission. */ + FLEXCAN_MbCode_RxRanswer = 10u, /*!< Code for Rx waiting for remote frame. */ + FLEXCAN_MbCode_TxDataOrRemote = 12u, /*!< Code for data frame or remote frame transmission. */ + FLEXCAN_MbCode_TxTanswer = 14u, /*!< Code for data response for remote frame. */ + FLEXCAN_MbCode_RxBusy = 15u, /*!< Code for Rx updating MB. */ +} FLEXCAN_MbCode_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref FLEXCAN_SetTimingConf() to initialize the time configuration. + */ +typedef struct +{ + bool EnableExtendedTime; /*!< If enable, the setting time range can be broader. */ + uint32_t PhaSegLen1; /*!< Phase segment 1. Compensate for edge phase errors and may be lengthened during resynchronization.*/ + uint32_t PhaSegLen2; /*!< Phase segment 2. Compensate for edge phase errors and may be lengthened during resynchronization.*/ + uint32_t PropSegLen; /*!< Propagation segment. Compensate for signal delays across the network.*/ + uint32_t JumpWidth; /*!< Resynchronize jump width. */ + uint32_t PreDiv; /*!< The divider for FLEXCAN clock source. */ +} FLEXCAN_TimConf_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref FLEXCAN_Init() to initialize the general setting of FLEXCAN. + */ +typedef struct +{ + uint8_t MaxXferNum; /*!< Max number of message buffer to be used. */ + uint32_t BaudRate; /*!< Data bit per second when using FLEXCAN for transmision and reception. */ + uint32_t ClockFreqHz; /*!< Clock source frequency. */ + FLEXCAN_ClockSource_Type ClockSource; /*!< Clock source selection. */ + FLEXCAN_SelfWakeUp_Type SelfWakeUp; /*!< Stop mode self wake up source. */ + FLEXCAN_WorkMode_Type WorkMode; /*!< FLEXCAN function mode. */ + FLEXCAN_Mask_Type Mask; /*!< Filter work range for filtering the received frames. */ + FLEXCAN_TimConf_Type * TimConf; /*!< FLEXCAN timer and time synchronization setup. */ + bool EnableSelfReception; /*!< Whether to receive frames sent by FLEXCAN itself. */ + bool EnableTimerSync; /*!< Refresh the timer every frame reception. */ +} FLEXCAN_Init_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref FLEXCAN_SetGlobalMbMaskConf() to set the mask for buffer. + */ +typedef struct +{ + FLEXCAN_MbType_Type MbType; /*!< Data frame or Remote frame switcher. */ + FLEXCAN_MbFormat_Type MbFormat; /*!< Extended or standard id switcher. */ + uint32_t IdMask; /*!< Id mask. */ +} FLEXCAN_RxMbMaskConf_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref FLEXCAN_SetRxFifoGlobalMaskConf() to set the conf for fifo mask filter. + */ +typedef struct +{ + FLEXCAN_MbType_Type MbType; /*!< Data frame or Remote frame switcher. */ + FLEXCAN_MbFormat_Type MbFormat; /*!< Extended or standard id switcher. */ + FLEXCAN_FifoIdFilterFormat_Type FilterFormat; /*!< fifo filter format. */ + union + { + uint32_t RxIdA; /*!< The fifo Id setting for filter format A. */ + uint16_t RxIdB[2]; /*!< The fifo Id setting for filter format B. */ + uint8_t RxIdC[4]; /*!< The fifo Id setting for filter format C. */ + }; +} FLEXCAN_RxFifoMaskConf_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref FLEXCAN_SetRxMb() to set the mask for buffer. + */ +typedef struct +{ + FLEXCAN_MbType_Type MbType; /*!< Data frame or Remote frame switcher. */ + FLEXCAN_MbFormat_Type MbFormat; /*!< Extended or standard id switcher. */ + uint32_t Id; /*!< Id value. */ +} FLEXCAN_RxMbConf_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref FLEXCAN_EnableRxFifo() to initialize the fifo setting. + */ +typedef struct +{ + FLEXCAN_FifoIdFilterFormat_Type FilterFormat; /*!< fifo filter format which will decide how to filter the fifo reception. */ + uint32_t IdFilterNum; /*!< The fifo filter element num. */ + uint32_t * IdFilterTable; /*!< Filter array to be set for Rx fifo. */ + FLEXCAN_FifoPriority_Type priority; /*!< Enable matching process start with fifo. */ +} FLEXCAN_RxFifoConf_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref FLEXCAN_WriteTxMb() to set the mask for buffer. + */ +typedef struct +{ + struct + { + uint32_t TIMESTAMP : 16; /*!< Free-running counter time stamp. */ + uint32_t LENGTH : 4; /*!< Length of Data in Bytes. */ + uint32_t TYPE : 1; /*!< Frame data type or remote type. */ + uint32_t FORMAT : 1; /*!< Frame extended format or standard format. */ + uint32_t RESERVED_0 : 1; /*!< Reservation. */ + uint32_t IDHIT : 9; /*!< Id filter number hit by fifo. */ + }; + struct + { + uint32_t ID :29; /*!< Frame Identifier. */ + uint32_t PRIORITY: 3; /*!< Local priority. */ + }; + union + { + struct + { + uint32_t WORD0; /*!< CAN Frame payload word0. */ + uint32_t WORD1; /*!< CAN Frame payload word1. */ + }; + struct + { + /* The sequence refers to the little-endian-storage and big-endian transfer. */ + uint8_t BYTE3; /*!< CAN Frame payload byte3. */ + uint8_t BYTE2; /*!< CAN Frame payload byte2. */ + uint8_t BYTE1; /*!< CAN Frame payload byte1. */ + uint8_t BYTE0; /*!< CAN Frame payload byte0. */ + uint8_t BYTE7; /*!< CAN Frame payload byte7. */ + uint8_t BYTE6; /*!< CAN Frame payload byte6. */ + uint8_t BYTE5; /*!< CAN Frame payload byte5. */ + uint8_t BYTE4; /*!< CAN Frame payload byte4. */ + }; + }; +} FLEXCAN_Mb_Type; + +/*! + * @brief Enable the FLEXCAN module. + * + * @param FLEXCANx FLEXCAN instance. + * @param enable 'true' to enable the module, 'false' to disable the module. + * @return None. + */ +void FLEXCAN_Enable(FLEXCAN_Type * FLEXCANx, bool enable); + +/*! + * @brief Enable soft reset of FLEXCAN registers. + * + * This will reset most part of the FLEXCAN registers. + * + * @param FLEXCANx FLEXCAN instance. + * @return None. + */ +void FLEXCAN_DoSoftReset(FLEXCAN_Type * FLEXCANx); + +/*! + * @brief Set up the FLEXCAN module with the indicated setting. + * + * @param FLEXCANx FLEXCAN instance. + * @param init Pointer to the initialization structure. See to @ref FLEXCAN_Init_Type. + * @return 'true' to setup the FLEXCAN module successfully, false to fail to set the baudrate wrongly. + */ +bool FLEXCAN_Init(FLEXCAN_Type * FLEXCANx, FLEXCAN_Init_Type * init); + +/*! + * @brief Set up the FLEXCAN timing module with the indicated setting. + * + * This would work when people want to change the boadrate after setting up the module. + * + * @param FLEXCANx FLEXCAN instance. + * @param conf Pointer to the initialization structure. See to @ref FLEXCAN_TimConf_Type. + * @return None. + */ +void FLEXCAN_SetTimingConf(FLEXCAN_Type * FLEXCANx, FLEXCAN_TimConf_Type * conf); + +/*! + * @brief Enter freeze mode for configuration. + * + * @param FLEXCANx FLEXCAN instance. + * @param enable 'true' to enable the module, 'false' to disable the module. + * @return None. + */ +void FLEXCAN_EnableFreezeMode(FLEXCAN_Type * FLEXCANx, bool enable); + +/*! + * @brief Set the Rx message buffer mask globally. + * + * Setting should be done after entering Freeze Mode. + * + * @param FLEXCANx FLEXCAN instance. + * @param conf Indicated mask and Mb frame type and format to be set for 16 message buffer globally. See to @ref FLEXCAN_RxMbMaskConf_Type. + * @return None. + */ +void FLEXCAN_SetGlobalMbMaskConf(FLEXCAN_Type * FLEXCANx, FLEXCAN_RxMbMaskConf_Type * conf); + +/*! + * @brief Set the Rx fifo mask globally. + * + * Setting should be done after entering Freeze Mode. + * + * @param FLEXCANx FLEXCAN instance. + * @param mask Indicated mask to be set for 16 message buffer globally. See to @ref FLEXCAN_RxFifoMaskConf_Type. + * @return None. + */ +void FLEXCAN_SetRxFifoGlobalMaskConf(FLEXCAN_Type * FLEXCANx, FLEXCAN_RxFifoMaskConf_Type * mask); + +/*! + * @brief Set Rx message buffer mask individually. + * + * Setting should be done after entering Freeze Mode. + * + * @param FLEXCANx FLEXCAN instance. + * @param channel The Mb channel to be masked indicatedly. See to @ref FLEXCAN_CHANNEL_SELECTION. + * @param mask Indicated mask to be set for 16 message buffer globally. See to @ref FLEXCAN_RxMbMaskConf_Type. + * @return None. + */ +void FLEXCAN_SetRxMbIndividualMaskConf(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_RxMbMaskConf_Type * mask); + +/*! + * @brief Clear the indicated MB. + * + * Clear the previous information in the buffer. + * + * @param FLEXCANx FLEXCAN instance. + * @param channel The Mb channel to be masked indicatedly. See to @ref FLEXCAN_CHANNEL_SELECTION. + * @return None. + */ +void FLEXCAN_ResetMb(FLEXCAN_Type * FLEXCANx, uint32_t channel); + +/*! + * @brief Clear message buffer with value 0. + * + * Clear the previous information in the buffer. + * + * @param FLEXCANx FLEXCAN instance. + * @param channel The Mb channel to be masked indicatedly. See to @ref FLEXCAN_CHANNEL_SELECTION. + * @param code The code to be set in Mb channel. See to @ref FLEXCAN_MbCode_Type. + * @return None. + */ +void FLEXCAN_SetMbCode(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_MbCode_Type code); + +/*! + * @brief Set Rx message buffer before reception. + * + * Prepare the type, format and id for Rx receiving. + * + * @param FLEXCANx FLEXCAN instance. + * @param channel The Mb channel to be masked indicatedly. See to @ref FLEXCAN_CHANNEL_SELECTION. + * @param conf Configuration for Rx Mb receiving. See to @ref FLEXCAN_RxMbConf_Type. + * @return None. + */ +void FLEXCAN_SetRxMb(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_RxMbConf_Type * conf); + +/*! + * @brief Setup the Rx fifo setting. + * + * Need to be done under freeze mode. + * + * @param FLEXCANx FLEXCAN instance. + * @param conf Pointer to the configuration structure. See to @ref FLEXCAN_RxFifoConf_Type. + * @return 'true' to enbale the Rx fifo successfully, 'false' to fail for setting the filter number wrongly. + */ +bool FLEXCAN_EnableRxFifo(FLEXCAN_Type * FLEXCANx, FLEXCAN_RxFifoConf_Type * conf); + +/*! + * @brief Enable global FLEXCAN interrupts. + * + * @param FLEXCANx FLEXCAN instance. + * @param interrupts Global interrupts to be set simultaneously. See to @ref FLEXCAN_GLOBAL_INT. + * @param enable 'true' to enable the interrupts, 'false' to disable the interrupts. + * @return None. + */ +void FLEXCAN_EnableInterrupts(FLEXCAN_Type * FLEXCANx, uint32_t interrupts, bool enable); + +/*! + * @brief Get the error status and global status of FLEXCAN. + * + * @param FLEXCANx FLEXCAN instance. + * @return FLEXCAN status. See to @ref FLEXCAN_STATUS. + */ +uint32_t FLEXCAN_GetStatus(FLEXCAN_Type * FLEXCANx); + +/*! + * @brief Get the error status and global status of FLEXCAN. + * + * @param FLEXCANx FLEXCAN instance. + * @param flags Flags to be cleared. See to @ref FLEXCAN_STATUS. + * @return None. + */ +void FLEXCAN_ClearStatus(FLEXCAN_Type * FLEXCANx, uint32_t flags); + +/*! + * @brief Enable FLEXCAN individual message buffer interrupts. + * + * @param FLEXCANx FLEXCAN instance. + * @param interrupts Global interrupts to be set simultaneously. See to @ref FLEXCAN_MB_INT. + * @param enable 'true' to enable the interrupts, 'false' to disable the interrupts. + * @return None. + */ +void FLEXCAN_EnableMbInterrupts(FLEXCAN_Type * FLEXCANx, uint32_t interrupts, bool enable); + +/*! + * @brief Get the buffer status or fifo status of FLEXCAN. + * + * @param FLEXCANx FLEXCAN instance. + * @return FLEXCAN buffer status. See to @ref FLEXCAN_MB_STATUS. + */ +uint32_t FLEXCAN_GetMbStatus(FLEXCAN_Type * FLEXCANx); + +/*! + * @brief Get the buffer status or fifo status of FLEXCAN. + * + * @param FLEXCANx FLEXCAN instance. + * @param mbs FLEXCAN buffer status to be cleared. See to @ref FLEXCAN_MB_STATUS. + * @return None. + */ +void FLEXCAN_ClearMbStatus(FLEXCAN_Type * FLEXCANx, uint32_t mbs); + +/*! + * @brief Enable Fifo DMA of FLEXCAN fifo. + * + * Should be done under freeze mode. + * + * @param FLEXCANx FLEXCAN instance. + * @param enable 'true' to enable the DMA, 'false' to disable the DMA. + * @return None. + */ +void FLEXCAN_EnableFifoDMA(FLEXCAN_Type * FLEXCANx, bool enable); + +/*! + * @brief Get the Tx error counter value. + * + * @param FLEXCANx FLEXCAN instance. + * @return Tx error counter value. + */ +uint32_t FLEXCAN_GetTxError(FLEXCAN_Type * FLEXCANx); + +/*! + * @brief Get the Rx error counter value. + * + * @param FLEXCANx FLEXCAN instance. + * @return Rx error counter value. + */ +uint32_t FLEXCAN_GetRxError(FLEXCAN_Type * FLEXCANx); + +/*! + * @brief Get the fifo address. + * + * @param FLEXCANx FLEXCAN instance. + * @return fifo address of the FLEXCAN. + */ +uint32_t FLEXCAN_GetFifoAddr(FLEXCAN_Type * FLEXCANx); + +/*! + * @brief Write the Mb frame into the indicated Mb channel. + * + * @param FLEXCANx FLEXCAN instance. + * @param channel The indicated FLEXCAN Mb channel. + * @param mb The prepared Mb for Tx. See to @ref FLEXCAN_Mb_Type. + * @return 'true' to put the Mb frame successfully, 'false' to fail. + */ +bool FLEXCAN_WriteTxMb(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_Mb_Type * mb); + +/*! + * @brief Read the Mb frame from the indicated Mb channel. + * + * @param FLEXCANx FLEXCAN instance. + * @param channel The indicated FLEXCAN Mb channel. + * @param mb The Mb for Rx. See to @ref FLEXCAN_Mb_Type. + * @return 'true' to get the Mb frame successfully, 'false' to fail. + */ +bool FLEXCAN_ReadRxMb(FLEXCAN_Type * FLEXCANx, uint32_t channel, FLEXCAN_Mb_Type * mb); + +/*! + * @brief Read the fifo Mb frame from fifo. + * + * @param FLEXCANx FLEXCAN instance. + * @param mb Pointer to the Mb structure. See to @ref FLEXCAN_Mb_Type. + * @return 'true' to get the Mb frame successfully, 'false' to fail. + */ +bool FLEXCAN_ReadRxFifo(FLEXCAN_Type * FLEXCANx, FLEXCAN_Mb_Type * mb); + +/*! + * @brief Get the number of buffer corresponding to the latest transmitted crc. + * + * @param FLEXCANx FLEXCAN instance. + * @param channel Channel match the latest transmission crc value. + * @return Latest transmission crc value. + */ +uint32_t FLEXCAN_GetMatchCrcValue(FLEXCAN_Type * FLEXCANx, uint32_t * channel); + +/*! + *@} + */ + +#endif /* __HAL_FLEXCAN_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_fsmc.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_fsmc.c new file mode 100644 index 000000000..faf044728 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_fsmc.c @@ -0,0 +1,115 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_fsmc.h" + +const uint32_t FSMC_BankBases[] = +{ + FSMC_BANK0_BASE, + FSMC_BANK1_BASE, + FSMC_BANK2_BASE, + FSMC_BANK3_BASE +}; + +void FSMC_Init(FSMC_Type * FSMCx, uint32_t bankn, FSMC_Init_Type * init) +{ + FSMCx->SMSKR[bankn] = ( (FSMCx->SMSKR[bankn] & ~(FSMC_SMSKR_MEMSIZE_MASK | FSMC_SMSKR_MEMTYPE_MASK) ) + | FSMC_SMSKR_MEMSIZE(init->MemSize) + | FSMC_SMSKR_MEMTYPE(init->MemType) ) + ; +} + +void FSMC_SetConf(FSMC_Type * FSMCx, uint32_t index, FSMC_Conf_Type * init) +{ + if (index >= FSMC_SMTMGR_REG_NUM) + { + return; + } + FSMCx->SMTMGRSET[index] = FSMC_SMTMGRSET_TRC(init->ReadPeriod) + | FSMC_SMTMGRSET_TAS(init->AddrSetTime) + | FSMC_SMTMGRSET_TWR(init->WriteHoldTime) + | FSMC_SMTMGRSET_TWP(init->WritePeriod) + | FSMC_SMTMGRSET_READYMODE(init->ReadySignal) + | FSMC_SMTMGRSET_SMREADPIPE(init->SMReadPipe) + ; + switch (index) + { + case 0u: + FSMCx->SMCTLR = ( (FSMCx->SMCTLR & ~FSMC_SMCTLR_SMDW_MASK) + | FSMC_SMCTLR_SMDW(init->BusWidth) ) + ; + break; + case 1u: + FSMCx->SMCTLR = ( (FSMCx->SMCTLR & ~FSMC_SMCTLR_SMDW1_MASK) + | FSMC_SMCTLR_SMDW1(init->BusWidth) ) + ; + break; + case 2u: + FSMCx->SMCTLR = ( (FSMCx->SMCTLR & ~FSMC_SMCTLR_SMDW2_MASK) + | FSMC_SMCTLR_SMDW2(init->BusWidth) ) + ; + break; + default: + break; + } +} + + /* only last enabled bankn is available. */ +void FSMC_EnableConf(FSMC_Type * FSMCx, uint32_t bankn, uint32_t index) +{ + if (index >= FSMC_SMTMGR_REG_NUM) + { + return; + } + FSMCx->SMSKR[bankn] = ( (FSMCx->SMSKR[bankn] & ~FSMC_SMSKR_REGSELECT_MASK) + | FSMC_SMSKR_REGSELECT(index) ) + ; +} + +void FSMC_PutData32(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint32_t data) +{ + (void)FSMCx; + *( (uint32_t *)(FSMC_BankBases[bankn] + offset) ) = data; +} + +uint32_t FSMC_GetData32(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset) +{ + (void)FSMCx; + return (*( (uint32_t *)(FSMC_BankBases[bankn] + offset) ) ); +} + +uint32_t FSMC_GetXferDataRegAddr(FSMC_Type *FSMCx, uint32_t bankn, uint32_t offset) +{ + (void)FSMCx; + return (FSMC_BankBases[bankn] + offset); +} + +void FSMC_PutData16(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint16_t data) +{ + (void)FSMCx; + *( (uint16_t *)(FSMC_BankBases[bankn] + offset) ) = data; +} + +uint16_t FSMC_GetData16(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset) +{ + (void)FSMCx; + return (*( (uint16_t *)(FSMC_BankBases[bankn] + offset) ) ); +} + +void FSMC_PutData8(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint8_t data) +{ + (void)FSMCx; + *( (uint8_t *)(FSMC_BankBases[bankn] + offset) ) = data; +} + +uint8_t FSMC_GetData8(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset) +{ + (void)FSMCx; + return (*( (uint8_t *)(FSMC_BankBases[bankn] + offset) ) ); +} + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_fsmc.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_fsmc.h new file mode 100644 index 000000000..43b4bdbaa --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_fsmc.h @@ -0,0 +1,216 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_FSMC_H__ +#define __HAL_FSMC_H__ + +#include "hal_common.h" + +/* +* There are still some configurations in SYSCFG_CFGR1: +* - switch between 8080 mode and NOR FLASH mode. +* - disable the reuse of data pins as address pins. +* - enable the fsmc sync. +*/ + +/*! + * @addtogroup FSMC + * @{ + */ + +/*! + * @brief FSMC driver version number. + */ +#define FSMC_DRIVER_VERSION 0u /*!< fsmc_0. */ + +/*! + * @brief FSMC memory type. + */ +typedef enum +{ + FSMC_MemType_SRAM = 1u, /*!< Mem type: SRAM. */ + FSMC_MemType_NorFlash = 2u, /*!< Mem type: NorFlash. */ + FSMC_MemType_PSRAM = 3u, /*!< Mem type: PSRAM. */ +} FSMC_MemType_Type; + +/*! + * @brief FSMC memory size type. + */ +typedef enum +{ + FSMC_MemSize_NoDevice = 0u, /*!< Mem Size type: NoDevice. */ + FSMC_MemSize_64KB = 1u, /*!< Mem Size type: 64KB. */ + FSMC_MemSize_128KB = 2u, /*!< Mem Size type: 128KB. */ + FSMC_MemSize_256KB = 3u, /*!< Mem Size type: 256KB. */ + FSMC_MemSize_512KB = 4u, /*!< Mem Size type: 512KB. */ + FSMC_MemSize_1MB = 5u, /*!< Mem Size type: 1MB. */ + FSMC_MemSize_2MB = 6u, /*!< Mem Size type: 2MB. */ + FSMC_MemSize_4MB = 7u, /*!< Mem Size type: 4MB. */ + FSMC_MemSize_8MB = 8u, /*!< Mem Size type: 8MB. */ + FSMC_MemSize_16MB = 9u, /*!< Mem Size type: 16MB. */ + FSMC_MemSize_32MB = 10u, /*!< Mem Size type: 32MB. */ + FSMC_MemSize_64MB = 11u, /*!< Mem Size type: 64MB. */ + FSMC_MemSize_128MB = 12u, /*!< Mem Size type: 128MB. */ + FSMC_MemSize_256MB = 13u, /*!< Mem Size type: 256MB. */ + FSMC_MemSize_512MB = 14u, /*!< Mem Size type: 512MB. */ + FSMC_MemSize_1GB = 15u, /*!< Mem Size type: 1GB. */ + FSMC_MemSize_2GB = 16u, /*!< Mem Size type: 2GB. */ + FSMC_MemSize_4GB = 17u, /*!< Mem Size type: 4GB. */ +} FSMC_MemSize_Type; + +/*! + * @brief FSMC ready signal type. + */ +typedef enum +{ + FSMC_ReadySignal_Internal = 0u, /*!< The ready signal is inside the FSMC, do not need the external ready signal. */ + FSMC_ReadySignal_External = 1u, /*!< The ready signal is from external device. */ +} FSMC_ReadySignal_Type; + +/*! + * @brief FSMC bus width type. + */ +typedef enum +{ + FSMC_BusWidth_8b = 4u, /*!< Bus width: 8bit. */ + FSMC_BusWidth_16b = 0u, /*!< Bus width: 16bit. */ + FSMC_BusWidth_32b = 1u, /*!< Bus width: 32bit. */ +} FSMC_BusWidth_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref FSMC_Init() to initialize the FSMC module. + */ +typedef struct +{ + FSMC_MemType_Type MemType; /*!< Specify the memory type. */ + FSMC_MemSize_Type MemSize; /*!< Specify the memory size. */ +} FSMC_Init_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref FSMC_SetConf() to initialize the FSMC config. + */ +typedef struct +{ + uint32_t ReadPeriod; /*!< the cycles for 'reading data', NOE available period. */ + uint32_t AddrSetTime; /*!< the cycles for 'setup' when writing. */ + uint32_t WriteHoldTime; /*!< the cycles between the master write action and slave capture done. */ + uint32_t WritePeriod; /*!< the cycles for 'keep data' in writing operation, NWE available period. */ + FSMC_ReadySignal_Type ReadySignal; /*!< select if capture the external ready signal. */ + uint32_t SMReadPipe; /*!< the cycles between the read action and release the bus.*/ + FSMC_BusWidth_Type BusWidth; /*!< Specify the bus width. */ +} FSMC_Conf_Type; + +/*! + * @brief Initialize the FSMC module. + * + * @param FSMCx FSMC instance. + * @param bankn FSMC bank number. + * @param init Pointer to the initialization structure. See to @ref FSMC_Init_Type. + * @return None. + */ +void FSMC_Init(FSMC_Type * FSMCx, uint32_t bankn, FSMC_Init_Type * init); + +/*! + * @brief Set the FSMC config. + * + * @param FSMCx FSMC instance. + * @param index Config index. + * @param conf Pointer to the config structure. See to @ref FSMC_Conf_Type. + * @return None. + */ +void FSMC_SetConf(FSMC_Type * FSMCx, uint32_t index, FSMC_Conf_Type * conf); + +/*! + * @brief Enable the FSMC config. + * + * Only last enabled config is available. + * + * @param FSMCx FSMC instance. + * @param bankn FSMC bank number. + * @param index Config index. + * @return None. + */ +void FSMC_EnableConf(FSMC_Type * FSMCx, uint32_t bankn, uint32_t index); + +/*! + * @brief Get the Xfer data reg addr. + * + * @param FSMCx FSMC instance. + * @param bankn FSMC bank number. + * @param offset offset of data in FSMC bank. + * @return The addr value of Xfer data reg. + */ +uint32_t FSMC_GetXferDataRegAddr(FSMC_Type *FSMCx, uint32_t bankn, uint32_t offset); + +/*! + * @brief Put the 32bit data by FSMC module. + * + * @param FSMCx FSMC instance. + * @param bankn FSMC bank number. + * @param offset offset of data in FSMC bank. + * @param data Data value to be send through the transmiter. + * @return None. + */ +void FSMC_PutData32(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint32_t data); + +/*! + * @brief Get the 32bit data by FSMC module. + * + * @param FSMCx FSMC instance. + * @param bankn FSMC bank number. + * @param offset offset of data in FSMC bank. + * @return The data value received from FSMC. + */ +uint32_t FSMC_GetData32(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset); + +/*! + * @brief Put the 16bit data by FSMC module. + * + * @param FSMCx FSMC instance. + * @param bankn FSMC bank number. + * @param offset offset of data in FSMC bank. + * @param data Data value to be send through the transmiter. + * @return None. + */ +void FSMC_PutData16(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint16_t data); + +/*! + * @brief Get the 16bit data by FSMC module. + * + * @param FSMCx FSMC instance. + * @param bankn FSMC bank number. + * @param offset offset of data in FSMC bank. + * @return The data value received from FSMC. + */ +uint16_t FSMC_GetData16(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset); + +/*! + * @brief Put the 8bit data by FSMC module. + * + * @param FSMCx FSMC instance. + * @param bankn FSMC bank number. + * @param offset offset of data in FSMC bank. + * @param data Data value to be send through the transmiter. + * @return None. + */ +void FSMC_PutData8(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint8_t data); + +/*! + * @brief Get the 8bit data by FSMC module. + * + * @param FSMCx FSMC instance. + * @param bankn FSMC bank number. + * @param offset offset of data in FSMC bank. + * @return The data value received from FSMC. + */ +uint8_t FSMC_GetData8(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset); + +/*! + *@} + */ + +#endif /* __HAL_FSMC_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_gpio.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_gpio.c new file mode 100644 index 000000000..dc291b83a --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_gpio.c @@ -0,0 +1,149 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_gpio.h" + +void GPIO_Init(GPIO_Type * GPIOx, GPIO_Init_Type * init) +{ + uint8_t idx; + uint8_t i; + uint32_t pin; + __IO uint32_t * addr; + + /* 1x. */ + uint32_t dat = init->PinMode & 0xFu; + if (init->PinMode & 0x10u) + { + dat |= init->Speed; + } + + /* 0x. */ + addr = &(GPIOx->CRL); + for (i = 0u; i < 8u; i++) + { + idx = i * 4u; + if ( (init->Pins) & (1u << i) ) + { + *addr = ( *addr & ~(0xFu << idx) ) | (dat << idx); + } + } + + addr = &(GPIOx->CRH); + pin = init->Pins >> 8u; + for (i = 0u; i < 8u; i++) + { + idx = i * 4u; + if ( pin & (1u << i) ) + { + *addr = ( *addr & ~(0xFu << idx) ) | (dat << idx); + } + } + + /* 2x,4x. */ + if (init->PinMode == GPIO_PinMode_In_PullDown) + { + GPIOx->BRR |= init->Pins; + } + else if (init->PinMode == GPIO_PinMode_In_PullUp) + { + GPIOx->BSRR |= init->Pins; + } +} + +bool GPIO_ReadInDataBit(GPIO_Type * GPIOx, uint16_t pin) +{ + return (GPIOx->IDR & pin); +} + +uint16_t GPIO_ReadInData(GPIO_Type * GPIOx) +{ + return (uint16_t)(GPIOx->IDR); +} + +bool GPIO_ReadOutDataBit(GPIO_Type * GPIOx, uint16_t pins) +{ + return (GPIOx->ODR & pins); +} + +uint16_t GPIO_ReadOutData(GPIO_Type * GPIOx) +{ + return (uint16_t)GPIOx->ODR; +} + +void GPIO_SetBits(GPIO_Type * GPIOx, uint16_t pins) +{ + GPIOx->BSRR = pins; +} + +void GPIO_ClearBits(GPIO_Type * GPIOx, uint16_t pins) +{ + GPIOx->BRR = pins; +} + +void GPIO_WriteBit(GPIO_Type * GPIOx, uint16_t pins, uint16_t val) +{ + (val != 0u) ? (GPIOx->BSRR = pins) : (GPIOx->BRR = pins); +} + +void GPIO_WriteBits(GPIO_Type * GPIOx, uint16_t val) +{ + GPIOx->ODR = val; +} + +void GPIO_PinLock(GPIO_Type * GPIOx, uint16_t pins, bool enable_lock) +{ + (enable_lock) ? (GPIOx->LCKR |= pins) : (GPIOx->LCKR &= ~pins); +} + +void GPIO_PinLockConf(GPIO_Type * GPIOx, uint16_t pins) +{ + GPIOx->LCKR = GPIO_LCKR_LCKK_MASK | GPIO_LCKR_LCK(pins); + GPIOx->LCKR = pins; + GPIOx->LCKR = GPIO_LCKR_LCKK_MASK | GPIO_LCKR_LCK(pins); + GPIOx->LCKR; + GPIOx->LCKR; +} + +void GPIO_PinAFConf(GPIO_Type * GPIOx, uint16_t pins, uint8_t af) +{ + uint32_t shift = 0u; + uint32_t idx = 0u; + uint32_t val = GPIOx->AFRL; + while (idx < 8u) + { + if ( ( (1u << idx) & pins) != 0u ) + { + shift = idx * 4u; + val &= ~(0xFu << shift); + val |= (uint32_t)af << shift; + } + idx++; + } + GPIOx->AFRL = val; + + val = GPIOx->AFRH; + while (idx < 16u) + { + if ( ( (1u << idx) & pins) != 0u ) + { + shift = (idx - 8u) * 4u; + val &= ~(0xFu << shift); + val |= (uint32_t)af << shift; + } + idx++; + } + GPIOx->AFRH = val; +} + +void GPIO_PortAFConfig(GPIO_Type * GPIOx, uint32_t af_high, uint32_t af_low) +{ + GPIOx->AFRL = af_low; + GPIOx->AFRH = af_high; +} + +/* EOF. */ + diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_gpio.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_gpio.h new file mode 100644 index 000000000..682067ced --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_gpio.h @@ -0,0 +1,218 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_GPIO_H__ +#define __HAL_GPIO_H__ + +#include "hal_common.h" + +/*! + * @addtogroup GPIO + * @{ + */ + +/*! + * @addtogroup GPIO_PIN + * @brief GPIO pin mask codes. + * @{ + */ +#define GPIO_PIN_0 (0x0001u) /*!< Pin 0 selected. */ +#define GPIO_PIN_1 (0x0002u) /*!< Pin 1 selected. */ +#define GPIO_PIN_2 (0x0004u) /*!< Pin 2 selected. */ +#define GPIO_PIN_3 (0x0008u) /*!< Pin 3 selected. */ +#define GPIO_PIN_4 (0x0010u) /*!< Pin 4 selected. */ +#define GPIO_PIN_5 (0x0020u) /*!< Pin 5 selected. */ +#define GPIO_PIN_6 (0x0040u) /*!< Pin 6 selected. */ +#define GPIO_PIN_7 (0x0080u) /*!< Pin 7 selected. */ +#define GPIO_PIN_8 (0x0100u) /*!< Pin 8 selected. */ +#define GPIO_PIN_9 (0x0200u) /*!< Pin 9 selected. */ +#define GPIO_PIN_10 (0x0400u) /*!< Pin 10 selected. */ +#define GPIO_PIN_11 (0x0800u) /*!< Pin 11 selected. */ +#define GPIO_PIN_12 (0x1000u) /*!< Pin 12 selected. */ +#define GPIO_PIN_13 (0x2000u) /*!< Pin 13 selected. */ +#define GPIO_PIN_14 (0x4000u) /*!< Pin 14 selected. */ +#define GPIO_PIN_15 (0x8000u) /*!< Pin 15 selected. */ +#define GPIO_PINS_ALL (0xFFFFu) /*!< All pins selected. */ +/*! + * @} + */ + +/*! + * @addtogroup GPIO_AF + * @brief GPIO pin alternative function. + * @{ + */ +#define GPIO_AF_0 (0x00u) /*!< Alternative function 0. */ +#define GPIO_AF_1 (0x01u) /*!< Alternative function 1. */ +#define GPIO_AF_2 (0x02u) /*!< Alternative function 2. */ +#define GPIO_AF_3 (0x03u) /*!< Alternative function 3. */ +#define GPIO_AF_4 (0x04u) /*!< Alternative function 4. */ +#define GPIO_AF_5 (0x05u) /*!< Alternative function 5. */ +#define GPIO_AF_6 (0x06u) /*!< Alternative function 6. */ +#define GPIO_AF_7 (0x07u) /*!< Alternative function 7. */ +#define GPIO_AF_8 (0x08u) /*!< Alternative function 8. */ +#define GPIO_AF_9 (0x09u) /*!< Alternative function 9. */ +#define GPIO_AF_10 (0x0Au) /*!< Alternative function 10. */ +#define GPIO_AF_11 (0x0Bu) /*!< Alternative function 11. */ +#define GPIO_AF_12 (0x0Cu) /*!< Alternative function 12. */ +#define GPIO_AF_13 (0x0Du) /*!< Alternative function 13. */ +#define GPIO_AF_14 (0x0Eu) /*!< Alternative function 14. */ +#define GPIO_AF_15 (0x0Fu) /*!< Alternative function 15. */ +/*! + * @} + */ + +/*! + * @brief GPIO maximum speed type. + */ +typedef enum +{ + GPIO_Speed_10MHz = 1u, /*!< Maximum speed is 10MHz. */ + GPIO_Speed_20MHz = 2u, /*!< Maximum speed is 20MHz. */ + GPIO_Speed_50MHz = 3u, /*!< Maximum speed is 50MHz. */ +} GPIO_Speed_Type; + +/*! +* @brief Port input / output mode. +*/ +typedef enum +{ + GPIO_PinMode_In_Analog = 0x00u, /*!< Analog input. */ + GPIO_PinMode_In_Floating = 0x04u, /*!< Floating input. */ + GPIO_PinMode_In_PullDown = 0x28u, /*!< Pull down input. */ + GPIO_PinMode_In_PullUp = 0x48u, /*!< Pull up input. */ + GPIO_PinMode_Out_OpenDrain = 0x14u, /*!< Universal open drain output. */ + GPIO_PinMode_Out_PushPull = 0x10u, /*!< Universal push-pull output. */ + GPIO_PinMode_AF_OpenDrain = 0x1Cu, /*!< Multiplex open drain output. */ + GPIO_PinMode_AF_PushPull = 0x18u, /*!< Multiplexed push-pull output. */ +} GPIO_PinMode_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref GPIO_Init() to initialize the GPIO module. + */ +typedef struct +{ + uint16_t Pins; /*!< GPIO operating pins. */ + GPIO_Speed_Type Speed; /*!< GPIO pin speed mode. */ + GPIO_PinMode_Type PinMode; /*!< GPIO pin input / output functional mode. */ +} GPIO_Init_Type; + +/*! + * @brief Initialize the GPIO module. + * + * @param GPIOx GPIO instance. + * @param init Pointer to the initialization structure. See to @ref GPIO_Init_Type. + * @return None. + */ +void GPIO_Init(GPIO_Type * GPIOx, GPIO_Init_Type * init); + +/*! + * @brief Set the specified data port bit. + * + * @param GPIOx GPIO instance. + * @param pins GPIO operating pins. See to @ref GPIO_PIN. + * @return None. + */ +void GPIO_SetBits(GPIO_Type * GPIOx, uint16_t pins); + +/*! + * @brief Clear the specified data port bit. + * + * @param GPIOx GPIO instance. + * @param pins GPIO operating pins. See to @ref GPIO_PIN. + * @return None. + */ +void GPIO_ClearBits(GPIO_Type * GPIOx, uint16_t pins); + +/*! + * @brief Writes 0 or 1 to the specified bit. + * + * @param GPIOx GPIO instance. + * @param pins GPIO operating pins. See to @ref GPIO_PIN. + * @param val Decide whether to set or clear. + * @return None. + */ +void GPIO_WriteBit(GPIO_Type * GPIOx, uint16_t pins, uint16_t val); + +/*! + * @brief Write 0 or 1 for multiple I/O ports. + * + * @param GPIOx GPIO instance. + * @param val Decide whether to set or clear. + * @return None. + */ +void GPIO_WriteBits(GPIO_Type * GPIOx, uint16_t val); + +/*! + * @brief Keep the set I/O configuration can not be changed. + * + * @param GPIOx GPIO instance. + * @param pins GPIO operating pins. See to @ref GPIO_PIN. + * @param enable_lock enable 'true' to enable the lock, 'false' to disable the lock. + * @return None. + */ +void GPIO_PinLock(GPIO_Type * GPIOx, uint16_t pins, bool enable_lock); + +/*! + * @brief Lock the corresponding bit of the select port configuration register. + * + * @param GPIOx GPIO instance. + * @param pins GPIO operating pins. See to @ref GPIO_PIN. + * @return None. + */ +void GPIO_PinLockConf(GPIO_Type * GPIOx, uint16_t pins); + +/*! + * @brief Read the value once entered before by the specified pin. + * + * @param GPIOx GPIO instance. + * @param pins GPIO operating pins. See to @ref GPIO_PIN. + * @return Status of a pin's logic level, 0 for low level or 1 for high level. + */ +bool GPIO_ReadInDataBit(GPIO_Type * GPIOx, uint16_t pins); + +/*! + * @brief Read the value previously output by the specified pin. + * + * @param GPIOx GPIO instance. + * @param pins GPIO operating pins. See to @ref GPIO_PIN. + * @return Status of a pin's logic level, 0 for low level or 1 for high level. + */ +bool GPIO_ReadOutDataBit(GPIO_Type * GPIOx, uint16_t pins); + +/*! + * @brief Read the specified GPIO port input. + * + * @param GPIOx GPIO instance. + * @return A hexadecimal number. + */ +uint16_t GPIO_ReadInData(GPIO_Type * GPIOx); + +/*! + * @brief Read the specified GPIO port output. + * + * @param GPIOx GPIO instance. + * @return A hexadecimal number. + */ +uint16_t GPIO_ReadOutData(GPIO_Type * GPIOx); + +/*! + * @brief Pin alternate function configuration of GPIO. + * + * @param GPIOx GPIO instance. + * @param pins GPIO operating pins. See to @ref GPIO_PIN. + * @param alternate_function Reuse the unified I/O port, but the function is different. + * @return None. + */ +void GPIO_PinAFConf(GPIO_Type* GPIOx, uint16_t pins, uint8_t alternate_function); + +/*! + * @} + */ + +#endif /* __HAL_GPIO_H__ */ + diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_i2c.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_i2c.c new file mode 100644 index 000000000..b17b774b1 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_i2c.c @@ -0,0 +1,357 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_i2c.h" + +/* Configure I2C speed to ordinary speed. */ +static bool I2C_CalcBandrate(I2C_Type * I2Cx, uint32_t clk, uint32_t bandrate) +{ + /* + * SCLH = (xSHR + 12) * I2C_CLK + tSYNC1; + * SCLL = (xSLR + 1) * I2C_CLK + tSYNC2; + * tSYNC1 & tSYNC2 equal 0 ~ 1 clk. + */ + if ( (clk / 24u) < bandrate ) /* the system clock cannot meet the baud rate requirement. */ + { + return false; + } + else + { + uint32_t tmp = clk / bandrate; + I2Cx->SSHR = tmp / 2u - 12u; /* Configure high level count in normal speed. */ + I2Cx->SSLR = tmp / 2u - 1u; /* Configure low level count in normal speed. */ + I2Cx->FSHR = tmp / 2u - 14u; /* Configure high level count in fast speed. */ + I2Cx->FSLR = tmp / 2u - 3u; /* Configure low level count in fast speed. */ + return true; + } +} + +/* Initialize I2C, Initialization failure return false, Initialization success return true. */ +bool I2C_InitMaster(I2C_Type * I2Cx, I2C_Master_Init_Type * init) +{ + I2Cx->ENR &= ~I2C_ENR_ENABLE_MASK; /* Disable I2C. */ + + if ( !I2C_CalcBandrate(I2Cx, init->ClockFreqHz, init->BaudRate) ) /* The system clock cannot meet the baud rate requirement. */ + { + return false; + } + + I2Cx->CR = I2C_CR_SPEED(1u); + + /* Setup I2C. */ + I2Cx->CR &= ~I2C_CR_MASTER10_MASK; /* Address format. */ + I2Cx->CR |= I2C_CR_RESTART_MASK /* Generate restart signal. */ + | I2C_CR_DISSLAVE_MASK /* Disable slave module. */ + | I2C_CR_REPEN_MASK /* Enable sending restart condition. */ + | I2C_CR_EMPINT_MASK /* Control tx_empty interrupt generation. */ + | I2C_CR_MASTER_MASK; /* Enable master module. */ + + I2Cx->IMR = 0u; /* Close all interrupts. */ + I2Cx->RXTLR = 0u; /* Configure the sending receive value. */ + I2Cx->TXTLR = 0u; /* Configure the sending threshold value. */ + return true; /* Initialize I2C succeeded, return true. */ +} + +/* Enable I2C. */ +void I2C_Enable(I2C_Type * I2Cx, bool enable) +{ + if (enable) + { + I2Cx->ENR |= I2C_ENR_ENABLE_MASK; + } + else + { + I2Cx->ENR &= ~I2C_ENR_ENABLE_MASK; + } +} + +/* Configuration the target device address. */ +void I2C_SetTargetAddr(I2C_Type * I2Cx, uint8_t addr) +{ + I2Cx->TAR = I2C_TAR_ADDR(addr); +} + +/* Get I2C target device address. */ +uint16_t I2C_GetTargetAddr(I2C_Type * I2Cx) +{ + return (I2Cx->TAR & I2C_TAR_ADDR_MASK); +} + +/* Put data to target device. */ +void I2C_PutData(I2C_Type * I2Cx, uint8_t val) +{ + I2Cx->DR = I2C_DR_DAT(val); +} + +/* Control read-write bit to prepare to read data. */ +void I2C_PrepareToGetData(I2C_Type * I2Cx) +{ + I2Cx->DR = I2C_DR_CMD_MASK; +} + +/* Get the data received by target device. */ +uint8_t I2C_GetData(I2C_Type * I2Cx) +{ + return ( (uint8_t)I2Cx->DR ); +} + +/* Get the current status flags of the I2C module. */ +uint32_t I2C_GetStatus(I2C_Type * I2Cx) +{ + return I2Cx->SR; +} + +/* Prepare for the stop, when transfer finish. */ +void I2C_Stop(I2C_Type * I2Cx) +{ + I2Cx->ENR |= I2C_ENR_ABORT_MASK; /* Prepare for the stop. */ + I2Cx->TXABRT; /* Read register to release tx fifo. */ +} + +/* Enable I2C interrupt. */ +void I2C_EnableInterrupts(I2C_Type * I2Cx, uint32_t interrupts, bool enable) +{ + if (enable) + { + I2Cx->IMR |= interrupts; + } + else + { + I2Cx->IMR &= ~interrupts; + } +} + +/* Get the current enabled interrupts the I2C module. */ +uint32_t I2C_GetEnabledInterrupts(I2C_Type * I2Cx) +{ + return I2Cx->IMR; +} + +/* Get the I2C interrupt status flags of the I2C module. */ +uint32_t I2C_GetInterruptStatus(I2C_Type * I2Cx) +{ + return (I2Cx->RAWISR & I2Cx->IMR); /* To ensure that the acquired interrupt is an enabled interrupt. */ +} + +/* Clear I2C interrupt status. */ +void I2C_ClearInterruptStatus(I2C_Type * I2Cx, uint32_t interrupts) +{ + if ( (I2C_INT_RX_UNDER & interrupts) != 0u ) /* Clear receive buffer under status. */ + { + I2Cx->RXUNDER; + } + if ( (I2C_INT_TX_ABORT & interrupts) != 0u ) /* Clear I2C transmit abort status. */ + { + I2Cx->TXABRT; + } + if ( (I2C_INT_ACTIVE & interrupts) != 0u ) /* Clear I2C interface activation status. */ + { + I2Cx->ACTIV; + } + if ( (I2C_INT_STOP & interrupts) != 0u ) /* Clear I2C stop condition detection status. */ + { + I2Cx->STOP; + } + if ( (I2C_INT_START & interrupts) != 0u ) /* Clear I2C start condition detection status. */ + { + I2Cx->START; + } +} + +/* Performs polling tx. */ +bool I2C_MasterWriteBlocking(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer) +{ + /* Put register address. */ + I2C_PutData(I2Cx, xfer->TxBuf[0u]); + + uint32_t waittime1 = xfer->WaitTimes; + /* Wait to tx fifo empty. */ + while ( (0u == (I2C_GetStatus(I2Cx) & I2C_STATUS_TX_EMPTY) ) && (0u != waittime1) ) + { + waittime1--; + } + if (0u == waittime1) /* I2C write register address timeout. */ + { + return false; + } + + uint32_t waittime2 = xfer->WaitTimes; + /* Write data to target device. */ + for (uint32_t i = 1u; i < xfer->TxLen; i++) + { + I2C_PutData(I2Cx, xfer->TxBuf[i]); + + while ( ( 0u == (I2C_GetStatus(I2Cx) & I2C_STATUS_TX_EMPTY) ) && (0u != waittime2) ) /* Wait to tx fifo empty. */ + { + waittime2--; + } + if (0u == waittime2) /* I2C write timeout. */ + { + return false; + } + } + + I2C_Stop(I2Cx); /* Prepare to stop send data. */ + + uint32_t waittime3 = xfer->WaitTimes; + /* Wait to I2C not active, which means stop is taking effect. */ + while ( (I2C_GetStatus(I2Cx) & I2C_STATUS_ACTIVE) && (0u != waittime3) ) + { + waittime3--; + } + if (0u == waittime3) /* The wait operation is timeout. */ + { + return false; + } + + /* Clear fifo and flags. */ + I2C1->ICR; + I2C1->TXABRT; + return true; +} + +/* Performs polling rx. */ +bool I2C_MasterReadBlocking(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer) +{ + I2C_PutData(I2Cx, xfer->TxBuf[0u]); /* Put device register address. */ + + uint32_t waittime1 = xfer->WaitTimes; + while ( ( 0u == (I2C_GetStatus(I2Cx) & I2C_STATUS_TX_EMPTY) ) && (0u != waittime1) ) /* Wait to tx fifo empty. */ + { + waittime1--; + } + if (0u == waittime1) + { + return false; + } + + /* read data from target device. */ + for (uint32_t i = 0u; i < xfer->RxLen; i++) + { + I2C_PrepareToGetData(I2Cx); /* Swich read-write bit, prepare to get data. */ + + while ( 0u == (I2C_GetStatus(I2Cx) & I2C_STATUS_RX_NOTEMPTY) ) /* Wait to rx fifo not empty. */ + { + if ( 0u == (I2C_GetStatus(I2Cx) & I2C_STATUS_ACTIVE) ) /* Receive is active. */ + { + return false; + } + } + xfer->RxBuf[i] = I2C_GetData(I2Cx); + } + + I2C_Stop(I2Cx); /* Prepare to stop I2C. */ + + uint32_t waittime2 = xfer->WaitTimes; + while ( (I2C_GetStatus(I2Cx) & I2C_STATUS_ACTIVE) && (0u != waittime2) ) /* Wait I2C not active, which means stop being effective. */ + { + waittime2--; + } + if (0u == waittime2) + { + return false; + } + + /* Clear fifo and flags. */ + I2C1->ICR; + I2C1->TXABRT; + + return true; +} + +/* I2C master interrupt transfer of the I2C module. */ +void I2C_MasterXfer(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer) +{ + I2C_PutData(I2Cx, (uint8_t)xfer->TxBuf[0u]); /* Put target register address. */ + I2C_EnableInterrupts(I2Cx, I2C_INT_TX_EMPTY | I2C_INT_TX_ABORT | I2C_INT_STOP, true); /* Enable tx required interrupt. */ + xfer->TxIdx = 1u; /* One data has been sent. */ + xfer->RxIdx = 0u; + xfer->TxLen--; +} + +/* I2C Master handler. */ +void I2C_MasterXferHandler(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer, uint32_t interrupts) +{ + if ( 0u != (interrupts & I2C_INT_TX_ABORT) ) /* Early termination of program. */ + { + I2C_EnableInterrupts(I2Cx, I2C_INT_TX_EMPTY | I2C_INT_TX_ABORT | I2C_INT_STOP, false); /* Clear the interrupt used for tx. */ + if (NULL != xfer->AbortCallback) + { + xfer->AbortCallback(xfer); /* Use abort call back. */ + } + } + else if ( 0u != (interrupts & I2C_INT_TX_EMPTY) ) /* Tx fifo is empty, can send data. */ + { + if (I2C_Direction_Rx == xfer->Direction) /* The current operation is receive, the register address has been sent. */ + { + I2C_EnableInterrupts(I2Cx, I2C_INT_TX_EMPTY | I2C_INT_TX_ABORT, false); /* Clear tx interrupt. */ + I2C_EnableInterrupts(I2Cx, I2C_INT_RX_NOTEMPTY, true); /* Enable receive required interrupt. */ + if (0u != xfer->RxLen) /* The data to be received is not 0. */ + { + I2C_PrepareToGetData(I2Cx); /* Prepare to get data. */ + xfer->RxLen--; + } + else + { + I2C_Stop(I2Cx); /* No more transmition, prepare to stop. */ + } + } + else + { + if (0u == xfer->TxLen) /* Tx finish. */ + { + I2C_EnableInterrupts(I2Cx, I2C_INT_TX_EMPTY | I2C_INT_TX_ABORT, false); /* Clear Tx interrupt. */ + I2C_Stop(I2Cx); /* Prepare to stop. */ + } + else + { + xfer->TxLen--; + I2C_PutData(I2Cx, xfer->TxBuf[xfer->TxIdx++]); /* Tx is not over, continue to put data. */ + } + } + } + else if ( 0u != (interrupts & I2C_INT_RX_NOTEMPTY) ) /* Receive interrupt. */ + { + if (0u == xfer->RxLen) /* Receive finish. */ + { + xfer->RxBuf[xfer->RxIdx++] = I2C_GetData(I2Cx); /* Get last data from I2C bus. */ + I2C_EnableInterrupts(I2Cx, I2C_INT_RX_NOTEMPTY, false); /* Clear receive interrupt. */ + I2C_Stop(I2Cx); /* Prepare to stop. */ + } + else + { + xfer->RxLen--; /* Current count length count -1. */ + xfer->RxBuf[xfer->RxIdx++] = I2C_GetData(I2Cx); /* Receive is not over, continue to get data. */ + I2C_PrepareToGetData(I2Cx); /* Prepare to get data. */ + } + } + else if ( 0u != (interrupts & I2C_INT_STOP) ) /* Xfer stop. */ + { + I2C_EnableInterrupts(I2Cx, I2C_INT_STOP, false); /* Clear stop interrupt. */ + if ( (0u != xfer->TxLen) || (0u != xfer->RxLen) ) /* The transmission was not completed but terminated. */ + { + if (NULL != xfer->AbortCallback) + { + xfer->AbortCallback(xfer); /* Early termination of program, abort callback. */ + I2C1->ICR; + I2C1->TXABRT; /* Clear FIFO. */ + } + } + else + { + if (NULL != xfer->DoneCallback) + { + xfer->DoneCallback(xfer); /* Transmission finish and stop, xfer done callback. */ + I2C1->ICR; + I2C1->TXABRT; /* Clear FIFO. */ + } + } + } +} + +/* EOF. */ + diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_i2c.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_i2c.h new file mode 100644 index 000000000..134202d1c --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_i2c.h @@ -0,0 +1,247 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_I2C_H__ +#define __HAL_I2C_H__ + +#include "hal_common.h" + +/*! + * @addtogroup I2C + * @{ + */ + +/*! + * @addtogroup I2C_INT + * @{ + */ +#define I2C_INT_RX_UNDER I2C_RAWISR_RXUNDER_MASK /*!< Assert when attempting to read the RX fifo, even it is empty. */ +#define I2C_INT_RX_NOTEMPTY I2C_RAWISR_RXFULL_MASK /*!< Assert when the data in RX fifo is available. */ +#define I2C_INT_TX_EMPTY I2C_RAWISR_TXEMPTY_MASK /*!< When working as master, this bit asserts if the data count is under or equal to the tx threshold. */ +#define I2C_INT_TX_ABORT I2C_RAWISR_TXABRT_MASK /*!< Assert when transmit abort. */ +#define I2C_INT_ACTIVE I2C_RAWISR_ACTIV_MASK /*!< Assert when the i2c bus is active, while the clocks are transfered. */ +#define I2C_INT_STOP I2C_RAWISR_STOP_MASK /*!< Assert when detecting a STOP on the i2c bus, no mater working as master or slave. */ +#define I2C_INT_START I2C_RAWISR_START_MASK /*!< Assert when detecting a START on the i2c bus, no matter working as master or slave. */ +/*! + * @} + */ + +/*! + * @addtogroup I2C_STATUS + * @{ + */ +#define I2C_STATUS_ACTIVE I2C_SR_ACTIV_MASK /*!< I2C bus is active. */ +#define I2C_STATUS_TX_EMPTY I2C_SR_TFE_MASK /*!< I2C tx fifo is empty. */ +#define I2C_STATUS_RX_NOTEMPTY I2C_SR_RFNE_MASK /*!< I2C rx fifo is not empty. */ +/*! + * @} + */ + +/*! + * @brief I2C baudrate type. + */ +typedef enum +{ + I2C_BaudRate_50K = 50000u, /*!< Specify operate at the speed of 50K. */ + I2C_BaudRate_100K = 100000u, /*!< Specify operate at the speed of 100K. */ +} I2C_BaudRate_Type; + +/*! + * @brief I2C transmission direction type. + */ +typedef enum +{ + I2C_Direction_Tx = 0u, /*!< Specify I2C transmission direction as tx. */ + I2C_Direction_Rx = 1u, /*!< Specify I2C transmission direction as rx. */ +} I2C_Direction_Type; + +/*! + * @brief Define the callback function called when the I2C master transfer is abort. + */ +typedef void (*I2C_Callback_1_Type)(void *param); + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref I2C_MasterXfer() to transfer the I2C address and data. + */ +typedef struct +{ + uint16_t TargetAddr; /*!< Specify I2C target device address. */ + I2C_Direction_Type Direction; /*!< specify transmission direction. */ + uint8_t *TxBuf; /*!< Specify the tx buffer array. */ + uint32_t TxIdx; /*!< Specify the number of data currently sent. */ + uint8_t TxLen; /*!< Specify the tx data len. */ + uint8_t *RxBuf; /*!< Specify the rx buffer array. */ + uint32_t RxIdx; /*!< Specify the number of data currently receive. */ + uint8_t RxLen; /*!< Specify the rx data len. */ + uint32_t WaitTimes; /*!< Specify the time limit for wait to the flag to be generated. If the required flag is not generated after this time, considered as timeout. */ + I2C_Callback_1_Type DoneCallback; /*!< Callback function, called when the i2c transmit is done. */ + I2C_Callback_1_Type AbortCallback; /*!< Callback function, called when the i2c transmit is abort. */ +} I2C_MasterXfer_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref I2C_InitMaster() to initialize the I2C master module. + */ +typedef struct +{ + uint32_t ClockFreqHz; /*!< Specify bus clock frequency. */ + I2C_BaudRate_Type BaudRate; /*!< Specify the I2C communication baud rate. */ +} I2C_Master_Init_Type; + +/*! + * @brief Initialize the I2C master module. + * + * @param I2Cx I2C instance. + * @param init Pointer to the master initialization structure. See to @ref I2C_Master_Init_Type. + * @return The initialize succeed return true, the misconfiguration of speed or baud rate return false. + */ +bool I2C_InitMaster(I2C_Type * I2Cx, I2C_Master_Init_Type * init); + +/*! + * @brief Enabel the I2C module. + * + * @param I2Cx I2C instance. + * @param enable 'true' to enable the module, 'false' to disable the module. + * @return None. + */ +void I2C_Enable(I2C_Type *I2Cx, bool enable); + +/*! + * @brief Set the I2C target device address that matches the slave device. + * + * @param I2Cx I2C instance. + * @param addr I2C target device address. + * @return None. + */ +void I2C_SetTargetAddr(I2C_Type * I2Cx, uint8_t addr); + +/*! + * @brief Get I2C target device address. + * + * @param I2Cx I2C instance. + * @return I2C target device addr. + */ +uint16_t I2C_GetTargetAddr(I2C_Type * I2Cx); + +/*! + * @brief Put the data into transmiter buffer of the I2C module. + * + * @param I2Cx I2C instance. + * @param val Data value to be send through the transmiter. + * @return None. + */ +void I2C_PutData(I2C_Type * I2Cx, uint8_t val); + +/*! + * @brief Control read-write bit to prepare for data acquisition. + * + * @param I2Cx I2C instance. + * @return None. + */ +void I2C_PrepareToGetData(I2C_Type * I2Cx); + +/*! + * @brief Get the data from receiver buffer of the I2C module. + * + * @param I2Cx I2C instance. + * @return Data received by I2C bus. + */ +uint8_t I2C_GetData(I2C_Type * I2Cx); + +/*! + * @brief Get the current status flags of the I2C module. + * + * @param I2Cx I2C instance. + * @return Status flags. See to @ref I2C_STATUS. + */ +uint32_t I2C_GetStatus(I2C_Type * I2Cx); + +/*! + * @brief Prepare for the stop, when transfer finish. + * + * @param I2Cx I2C instance. + * @return None. + */ +void I2C_Stop(I2C_Type * I2Cx); + +/*! + * @brief Enable interrupts of I2C module. + * + * @param I2Cx I2C instance. + * @param interrupts Interrupt code masks. See to @ref I2C_INT. + * @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts. + * @return None. + */ +void I2C_EnableInterrupts(I2C_Type * I2Cx, uint32_t interrupts, bool enable); + +/*! + * @brief Read the current enabled interrupts the I2C module. + * + * @param I2Cx I2C instance. + * @return The mask codes enabled interrupts. See to @ref I2C_INT. + */ +uint32_t I2C_GetEnabledInterrupts(I2C_Type * I2Cx); + +/*! + * @brief Get the I2C interrupt status flags of the I2C module. + * + * @param I2Cx I2C instance. + * @return Interrupt status flags. See to @ref I2C_INT. + */ +uint32_t I2C_GetInterruptStatus(I2C_Type * I2Cx); + +/*! + * @brief Clear the I2C interrupt status flags of the I2C module. + * + * @param I2Cx I2C instance. + * @param interrupts The mask codes of the indicated interrupt flags to be cleared. + * @return None. + */ +void I2C_ClearInterruptStatus(I2C_Type * I2Cx, uint32_t interrupts); + +/*! + * @brief I2C master interrupt transfer of the I2C module. + * + * @param I2Cx I2C instance. + * @param xfer Pointer to the I2C master transimt structure. See to @ref I2C_MasterXfer_Type. + * @return None. + */ +void I2C_MasterXfer(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer); + +/*! + * @brief I2C master transfer interrupt handler. + * + * @param I2Cx I2C instance. + * @param xfer Pointer to the I2C master transimt structure. See to @ref I2C_MasterXfer_Type. + * @param interrupts Interrupt status flags. See to @ref I2C_INT. + * @return None. + */ +void I2C_MasterXferHandler(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer, uint32_t interrupts); + +/*! + * @brief I2C master write polling. + * + * @param I2Cx I2C instance. + * @param xfer Pointer to the I2C master transimt structure. See to @ref I2C_MasterXfer_Type. + * @return 'true' to I2C write polling succeed, 'false' to I2C write polling failed. + */ +bool I2C_MasterWriteBlocking(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer); + +/*! + * @brief I2C master read polling. + * + * @param I2Cx I2C instance. + * @param xfer Pointer to the I2C master transimt structure. See to @ref I2C_MasterXfer_Type. + * @return 'true' to I2C read polling succeed, 'false' to I2C read polling failed. + */ +bool I2C_MasterReadBlocking(I2C_Type * I2Cx, I2C_MasterXfer_Type * xfer); + +/*! + *@} + */ + +#endif /* __HAL_I2C_H__ */ + diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_i2s.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_i2s.c new file mode 100644 index 000000000..885d12e6c --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_i2s.c @@ -0,0 +1,195 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_i2s.h" + +/* init i2s in master mode. */ +void I2S_InitMaster(I2S_Type * I2Sx, I2S_Master_Init_Type * init) +{ + if (NULL == init || + 0u == init->SampleRate) + { + return; + } + + /* get I2Sx->GCTL value & clear the field to be configured. */ + uint32_t gctl = I2Sx->GCTL & ~(SPI_I2S_GCTL_RXEN_MASK + | SPI_I2S_GCTL_TXEN_MASK + | SPI_I2S_GCTL_MODE_MASK + | SPI_I2S_GCTL_INTEN_MASK); + + /* get I2Sx->CCTL value & clear the field to be configured. */ + uint32_t cctl = I2Sx->CCTL & ~(SPI_I2S_CCTL_RXEDGE_MASK + | SPI_I2S_CCTL_CPOL_MASK); + + /* get I2Sx->I2SCFGR value & clear the field to be configured. */ + uint32_t cfgr = I2Sx->I2SCFGR & ~(SPI_I2S_I2SCFGR_I2SDIV_MASK + | SPI_I2S_I2SCFGR_HFDSEL_MASK + | SPI_I2S_I2SCFGR_MCKOE_MASK + | SPI_I2S_I2SCFGR_SPII2S_MASK + | SPI_I2S_I2SCFGR_I2SSTD_MASK + | SPI_I2S_I2SCFGR_DATLEN_MASK + | SPI_I2S_I2SCFGR_CHLEN_MASK); + + /* set the xfer mode. */ + switch (init->XferMode) + { + case I2S_XferMode_TxOnly: + gctl |= SPI_I2S_GCTL_TXEN_MASK; + gctl &= ~SPI_I2S_GCTL_RXEN_MASK; + cfgr |= SPI_I2S_I2SCFGR_HFDSEL_MASK; + break; + case I2S_XferMode_RxOnly: + gctl |= SPI_I2S_GCTL_RXEN_MASK; + gctl &= ~SPI_I2S_GCTL_TXEN_MASK; + cfgr |= SPI_I2S_I2SCFGR_HFDSEL_MASK; + break; + case I2S_XferMode_TxRx: + gctl |= SPI_I2S_GCTL_TXEN_MASK | SPI_I2S_GCTL_RXEN_MASK; + cfgr &= ~SPI_I2S_I2SCFGR_HFDSEL_MASK; + break; + default: + break; + } + + /* master mode. */ + gctl |= SPI_I2S_GCTL_MODE_MASK /* master mode, disable i2s, and reset the other bits in CCTL. */ + | SPI_I2S_GCTL_INTEN_MASK; /* always enable the global interrupt. the specific events are controlled by each bits in INTEN register. */ + + /* set CPOL. */ + cctl |= SPI_I2S_CCTL_RXEDGE_MASK + | SPI_I2S_CCTL_CPOL(init->Polarity); + + uint32_t div = 0u; + + /* calc the i2s_div value. */ + if (!(init->EnableMCLK) ) + { + if (I2S_DataWidth_16b == init->DataWidth) + { + div = (init->ClockFreqHz) / (32u * (init->SampleRate) ); + } + else + { + div = (init->ClockFreqHz) / (64u * (init->SampleRate) ); + cfgr |= SPI_I2S_I2SCFGR_CHLEN_MASK; + } + } + else + { + div = (init->ClockFreqHz) / (256u * (init->SampleRate) ); + if (I2S_DataWidth_16b != init->DataWidth) + { + cfgr |= SPI_I2S_I2SCFGR_CHLEN_MASK; + } + } + + cfgr |= SPI_I2S_I2SCFGR_I2SDIV(div) + | SPI_I2S_I2SCFGR_MCKOE(1u) + | SPI_I2S_I2SCFGR_SPII2S_MASK + | SPI_I2S_I2SCFGR_I2SSTD(init->Protocol) + | SPI_I2S_I2SCFGR_DATLEN(init->DataWidth); + + I2Sx->GCTL = gctl; /* set I2Sx->GCTL. */ + I2Sx->CCTL = cctl; /* set I2Sx->CCTL. */ + I2Sx->I2SCFGR = cfgr; /* set I2Sx->I2SCFGR. */ +} + +/* enable i2s. */ +void I2S_Enable(I2S_Type * I2Sx, bool enable) +{ + if (enable) + { + I2Sx->GCTL |= SPI_I2S_GCTL_SPIEN_MASK; + } + else + { + I2Sx->GCTL &= ~SPI_I2S_GCTL_SPIEN_MASK; + } +} + +/* get i2s status. */ +uint32_t I2S_GetStatus(I2S_Type * I2Sx) +{ + return I2Sx->CSTAT; +} + +/* enable interrupt. */ +void I2S_EnableInterrupts(I2S_Type * I2Sx, uint32_t interrupts, bool enable) +{ + if (enable) + { + I2Sx->INTEN |= interrupts; + } + else + { + I2Sx->INTEN &= ~interrupts; + } +} + +/* get interrupt status. */ +uint32_t I2S_GetInterruptStatus(I2S_Type * I2Sx) +{ + return I2Sx->INTSTAT; +} + +/* clear interrupt status. */ +void I2S_ClearInterruptStatus(I2S_Type * I2Sx, uint32_t interrupts) +{ + I2Sx->INTCLR = interrupts; +} + +/* put data to tx buffer. */ +void I2S_PutData(I2S_Type * I2Sx, uint32_t data) +{ + I2Sx->TXREG = data; +} + +/* get data in rx buffer. */ +uint32_t I2S_GetData(I2S_Type * I2Sx) +{ + return I2Sx->RXREG; +} + +I2S_Channel_Type I2S_GetXferChannel(I2S_Type * I2Sx) +{ + if (0u != (I2Sx->CSTAT & SPI_I2S_CSTAT_CHSIDE_MASK) ) + { + return I2S_Channel_Right; + } + else + { + return I2S_Channel_Left; + } +} + +/* enable dma. */ +void I2S_EnableDMA(I2S_Type * I2Sx, bool enable) +{ + if (enable) + { + I2Sx->GCTL |= SPI_I2S_GCTL_DMAMODE_MASK; + } + else + { + I2Sx->GCTL &= ~SPI_I2S_GCTL_DMAMODE_MASK; + } +} + +/* get rx buffer reg addr. */ +uint32_t I2S_GetRxDataRegAddr(I2S_Type * I2Sx) +{ + return (uint32_t)(&(I2Sx->RXREG) ); +} + +/* get tx buffer reg addr. */ +uint32_t I2S_GetTxDataRegAddr(I2S_Type * I2Sx) +{ + return (uint32_t)(&(I2Sx->TXREG) ); +} + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_i2s.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_i2s.h new file mode 100644 index 000000000..7d1db0de3 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_i2s.h @@ -0,0 +1,229 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_I2S_H__ +#define __HAL_I2S_H__ + +#include "hal_common.h" + +/*! + * @addtogroup I2S + * @{ + */ + +/*! + * @brief I2S driver version number. + */ +#define I2S_DRIVER_VERSION 0u /*!< i2s_0. */ + +/*! + * @addtogroup I2S_STATUS + * @{ + */ +#define I2S_STATUS_BUSY SPI_I2S_CSTAT_BUSY_MASK /*!< Status flag when I2S is transmitting or receiving. */ +#define I2S_STATUS_TX_FULL SPI_I2S_CSTAT_TXFULL_MASK /*!< Status flag when I2S transmiter buffer is full. */ +#define I2S_STATUS_TX_DONE SPI_I2S_CSTAT_TXEPT_MASK /*!< Status flag when I2S transmiter buffer & transmiter are empty. */ +#define I2S_STATUS_RX_DONE SPI_I2S_CSTAT_RXAVL_MASK /*!< Status flag when I2S receiving buffer is with available data. */ +/*! + * @} + */ + +/*! + * @addtogroup I2S_INT + * @{ + */ +#define I2S_INT_TX_EMPTY SPI_I2S_INTEN_TXIEN_MASK /*!< Interrupt flag when I2S transmiter buffer is empty. */ +#define I2S_INT_TX_DONE SPI_I2S_INTSTAT_TXEPTINTF_MASK /*!< Interrupt flag when I2S transmiter buffer & transmiter are empty. */ +#define I2S_INT_RX_DONE SPI_I2S_INTEN_RXIEN_MASK /*!< Interrupt flag when I2S receiving buffer is with available data. */ +#define I2S_INT_XFER_ERROR SPI_I2S_INTEN_FREIEN_MASK /*!< Interrupt flag when I2S xfer data error. */ +/*! + * @} + */ + +/*! + * @brief I2S polarity type. + */ +typedef enum +{ + I2S_Polarity_0 = 0u, /*!< CPOL = 0, Clock line is low when idle. */ + I2S_Polarity_1 = 1u, /*!< CPOL = 1, Clock line is high when idle. */ +} I2S_Polarity_Type; + +/*! + * @brief I2S data width type. + */ +typedef enum +{ + I2S_DataWidth_16b = 0u, /*!< Data width is 16 bit. */ + I2S_DataWidth_24b = 1u, /*!< Data width is 24 bit. */ + I2S_DataWidth_32b = 2u, /*!< Data width is 32 bit. */ +} I2S_DataWidth_Type; + +/*! + * @brief I2S protocol type. + */ +typedef enum +{ + I2S_Protocol_PHILIPS = 0u, /*!< Philips xfer protocol. */ + I2S_Protocol_MSB = 1u, /*!< MSB xfer protocol. */ + I2S_Protocol_LSB = 2u, /*!< LSB xfer protocol. */ + I2S_Protocol_PCM = 3u, /*!< PCM xfer protocol. */ +} I2S_Protocol_Type; + +/*! + * @brief I2S xfer mode type. + */ +typedef enum +{ + I2S_XferMode_TxOnly = 0u, /*!< Enable Tx only. */ + I2S_XferMode_RxOnly = 1u, /*!< Enable Rx only. */ + I2S_XferMode_TxRx = 2u, /*!< Enable both Tx and Rx. */ +} I2S_XferMode_Type; + +/*! + * @brief I2S xfer channel type. + */ +typedef enum +{ + I2S_Channel_Left = 0u, /*!< Left Xfer channel. */ + I2S_Channel_Right = 1u, /*!< Right Xfer channel. */ +} I2S_Channel_Type; + + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref I2S_InitMaster() to initialize the I2S module. + */ +typedef struct +{ + uint32_t ClockFreqHz; /*!< Bus Clock Freq. */ + uint32_t SampleRate; /*!< This member configures the I2S sample rate. */ + I2S_DataWidth_Type DataWidth; /*!< Specifies the number of bits of data to be transmitted. */ + I2S_Polarity_Type Polarity; /*!< Specifies the polarity of clock. */ + I2S_Protocol_Type Protocol; /*!< Specifies different communication protocols. */ + I2S_XferMode_Type XferMode; /*!< Specifies different communication transmit modes. */ + bool EnableMCLK; /*!< Specifies whether enable MCLK. */ +} I2S_Master_Init_Type; + +/*! + * @brief Initialize the I2S Master module. + * + * @param I2Sx I2S instance. + * @param init Pointer to the initialization structure. See to @ref I2S_Master_Init_Type. + * @return None. + */ +void I2S_InitMaster(I2S_Type * I2Sx, I2S_Master_Init_Type * init); + +/*! + * @brief Enable the I2S module. + * + * The I2S module should be enabled before sending or receiving data. + * + * @param I2Sx I2S instance. + * @param enable 'true' to enable the module, 'false' to disable the module. + * @return None. + */ +void I2S_Enable(I2S_Type * I2Sx, bool enable); + +/*! + * @brief Get the current status flags of the I2S module. + * + * @param I2Sx I2S instance. + * @return Status flags. See to @ref I2S_STATUS. + */ +uint32_t I2S_GetStatus(I2S_Type * I2Sx); + +/*! + * @brief Enable interrupts of the I2S module. + * + * @param I2Sx I2S instance. + * @param interrupts Interrupt code masks. See to @ref I2S_INT. + * @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts. + * @return None. + */ +void I2S_EnableInterrupts(I2S_Type * I2Sx, uint32_t interrupts, bool enable); + +/*! + * @brief Get the interrupts status flags of the I2S module. + * + * @param I2Sx I2S instance. + * @return Interrupt status flags. See to @ref I2S_INT. + */ +uint32_t I2S_GetInterruptStatus(I2S_Type * I2Sx); + +/*! + * @brief Clear the interrupt status flags of the I2S module. + * + * @param I2Sx I2S instance. + * @param interrupts The mask codes of the indicated interrupt flags to be cleared. + * @return None. + */ +void I2S_ClearInterruptStatus(I2S_Type * I2Sx, uint32_t interrupts); + +/*! + * @brief Put the data into transmiter buffer of the I2S module. + * + * @param I2Sx I2S instance. + * @param data Data value to be send through the transmiter. + * @return None. + */ +void I2S_PutData(I2S_Type * I2Sx, uint32_t dat); + +/*! + * @brief Get the data from receiver buffer of the I2S module. + * + * @param I2Sx I2S instance. + * @return The data value received from the receiver. + * @return data Data value to be received from the transmiter. + */ +uint32_t I2S_GetData(I2S_Type * I2Sx); + +/*! + * @brief Enable the DMA trigger from the I2S module. + * + * The DMA trigger events are the same as the interrupts. + * + * @param I2Sx I2S instance. + * @param enable 'true' to enable the DMA trigger, 'false' to disable the DMA trigger. + * @return None. + */ +void I2S_EnableDMA(I2S_Type * I2Sx, bool enable); + +/*! + * @brief Get the hardware Rx data buffer's address the I2S module. + * + * The return value of the address is most used with DMA module. + * + * @param I2Sx I2S instance. + * @return The value of the address for I2S module's hardware Rx data buffer. + */ +uint32_t I2S_GetRxDataRegAddr(I2S_Type * I2Sx); + +/*! + * @brief Get the hardware Tx data buffer's address the I2S module. + * + * The return value of the address is most used with DMA module. + * + * @param I2Sx I2S instance. + * @return The value of the address for I2S module's hardware Tx data buffer. + */ +uint32_t I2S_GetTxDataRegAddr(I2S_Type * I2Sx); + +/*! + * @brief Get the transmitting channel of the I2S module. + * + * @param I2Sx I2S instance. + * @return The current transmitting channel. + */ +I2S_Channel_Type I2S_GetXferChannel(I2S_Type * I2Sx); + +/*! + *@} + */ + +#endif /* __HAL_I2S_H__ */ + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_iwdg.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_iwdg.c new file mode 100644 index 000000000..08125aa54 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_iwdg.c @@ -0,0 +1,59 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_iwdg.h" + +void IWDG_Init(IWDG_Type * IWDGx, IWDG_Init_Type * init) +{ + if ( NULL != init ) + { + IWDGx->KR = IWDG_KEY_UNLOCK; + IWDGx->PR = init->Prescaler; + + IWDGx->KR = IWDG_KEY_UNLOCK; + IWDGx->RLR = init->Relaod; + + IWDG_DoReload(IWDGx); + } +} + +void IWDG_Start(IWDG_Type * IWDGx) +{ + IWDGx->KR = IWDG_KEY_ENABLE; +} + +uint32_t IWDG_GetStatus(IWDG_Type * IWDGx) +{ + return IWDGx->SR; +} + +void IWDG_DoReload(IWDG_Type * IWDGx) +{ + IWDGx->KR = IWDG_KEY_RELOAD; +} + +void IWDG_EnableInterrupts(IWDG_Type * IWDGx, uint32_t interrupts, bool enable) +{ + if( (true == enable ) && (IWDG_INT_ALMOST_TIMEOUT == interrupts) ) + { + IWDGx->CR |= IWDG_CR_IRQSEL_MASK; + } + else + { + /* if IWDG_EnableInterrupts interrupt was enabled, only MCU reset can close it. */ + } +} + +void IWDG_ClearStatus(IWDG_Type * IWDGx, uint32_t status) +{ + if( 0u != ( status & IWDG_CR_IRQCLR_MASK ) ) + { + IWDGx->CR |= IWDG_CR_IRQCLR_MASK; + } +} + +/* EOF. */ \ No newline at end of file diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_iwdg.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_iwdg.h new file mode 100644 index 000000000..7ee730087 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_iwdg.h @@ -0,0 +1,133 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_IWDG_H__ +#define __HAL_IWDG_H__ + +#include "hal_common.h" + +/*! + * @addtogroup IWDG + * @{ + */ + +/*! + * @brief IWDG driver version number. + */ +#define IWDG_DRIVER_VERSION 0u /*!< IWDG_0. */ + +/*! + * @brief IWDG key values + */ +#define IWDG_KEY_ENABLE 0xCCCC /*!< IWDG Peripheral Enable . */ +#define IWDG_KEY_RELOAD 0xAAAA /*!< IWDG Reload Counter Enable. */ +#define IWDG_KEY_UNLOCK 0x5555 /*!< IWDG KR Write Access Enable*/ + +/*! + * @addtogroup IWDG_STATUS + * @{ + */ +#define IWDG_STATUS_RELOAD_UPDATE IWDG_SR_RVU_MASK /*!< Status flag when IWDG counter reload value update, can not be cleared. */ +#define IWDG_STATUS_PRESCALER_UPDATE IWDG_SR_PVU_MASK /*!< Status flag when IWDG prescaler value update, can not be cleared. */ +#define IWDG_STATUS_ALMOST_TIMEOUT IWDG_SR_IVU_MASK /*!< Status flag when IWDG almost timeout. */ +/*! + * @} + */ + +/*! + * @addtogroup IWDG_INT + * @{ + */ +#define IWDG_INT_ALMOST_TIMEOUT IWDG_CR_IRQSEL_MASK /*!< IWDG Interrupt: Select IWDG interrupt method */ +/*! + * @} + */ + +/*! + * @brief IWDG prescaler type. + * + * Select the prescaler of time base as the IWDG counter clock. + */ +typedef enum +{ + IWDG_Prescaler_4 = 0u, /*!< IWDG prescaler 4. */ + IWDG_Prescaler_8 = 1u, /*!< IWDG prescaler 8. */ + IWDG_Prescaler_16 = 2u, /*!< IWDG prescaler 16. */ + IWDG_Prescaler_32 = 3u, /*!< IWDG prescaler 32. */ + IWDG_Prescaler_64 = 4u, /*!< IWDG prescaler 64. */ + IWDG_Prescaler_128 = 5u, /*!< IWDG prescaler 128. */ + IWDG_Prescaler_256 = 6u, /*!< IWDG prescaler 256. */ +} IWDG_Prescaler_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref IWDG_Init() to initialize the IWDG module. + */ +typedef struct +{ + IWDG_Prescaler_Type Prescaler; /*!< Specify the IWDG counter time base division value. */ + uint32_t Relaod; /*!< Specify the IWDG counter reload value. */ +} IWDG_Init_Type; + +/*! + * @brief Initialize the IWDG module. + * + * @param IWDGx IWDG instance. + * @param init Pointer to the initialization structure. See to @ref IWDG_Init_Type. + * @return None. + */ +void IWDG_Init(IWDG_Type * IWDGx, IWDG_Init_Type * init); + +/*! + * @brief Start the IWDG counter. + * + * Once IWDG counter is started, it cannot be stopped unless reset MCU. + * + * @param IWDGx IWDG instance. + * @return None. + */ +void IWDG_Start(IWDG_Type * IWDGx); + +/*! + * @brief Get the current status flags of the IWDG module. + * + * @param IWDGx IWDG instance. + * @return Status flags. See to @ref IWDG_STATUS. + */ +uint32_t IWDG_GetStatus(IWDG_Type * IWDGx); + +/*! + * @brief Clear the status flags of the IWDG module. + * + * @param IWDGx IWDG instance. + * @param status Status flags. See to @ref IWDG_STATUS. + * @return None. + */ +void IWDG_ClearStatus(IWDG_Type * IWDGx, uint32_t status); + +/*! + * @brief Do reload IWDG counter (i.e. "feed dog"). + * + * @param IWDGx IWDG instance. + * @return None. + */ +void IWDG_DoReload(IWDG_Type * IWDGx); + +/*! + * @brief Enable interrupts of the IWDG module. + * + * @param IWDGx IWDG instance. + * @param interrupts Interrupt code masks. See to @ref IWDG_INT. + * @param enable 'true' to enable the indicated interrupts, 'false' has no effect. + * @return None. + */ +void IWDG_EnableInterrupts(IWDG_Type * IWDGx, uint32_t interrupts, bool enable); + +/*! + *@} + */ + +#endif /* __HAL_IWDG_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_lptim.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_lptim.c new file mode 100644 index 000000000..5fe6a59af --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_lptim.c @@ -0,0 +1,78 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_lptim.h" + +void LPTIM_Init(LPTIM_Type * LPTIMx, LPTIM_Init_Type * init) +{ + LPTIMx->CFG = (LPTIMx->CFG & ~( LPTIM_CFG_TMODE_MASK | LPTIM_CFG_DIVSEL_MASK | LPTIM_CFG_MODE_MASK) ) + | LPTIM_CFG_TMODE(init->WorkMode) /* Setup the work mode. */ + | LPTIM_CFG_DIVSEL(init->Prescaler) /* Setup the prescaler. */ + | LPTIM_CFG_MODE(init->PeriodMode); /* Setup the period mode. */ + + /* Setup the period value. */ + LPTIMx->TARGET = LPTIM_TARGET_TARGETREG(init->Period); +} + +void LPTIM_Start(LPTIM_Type * LPTIMx) +{ + LPTIMx->CTRL |= LPTIM_CTRL_LPTEN_MASK; /* Start the counter. */ +} + +void LPTIM_Stop(LPTIM_Type * LPTIMx) +{ + LPTIMx->CTRL &= ~LPTIM_CTRL_LPTEN_MASK; /* Stop the counter. */ +} + +void LPTIM_EnableInterrupts(LPTIM_Type * LPTIMx, uint32_t interrupts, bool enable) +{ + if (enable) + { + LPTIMx->IE |= interrupts; + } + else + { + LPTIMx->IE &= ~interrupts; + } +} + +uint32_t LPTIM_GetInterruptStatus(LPTIM_Type * LPTIMx) +{ + return LPTIMx->IF; /* return flags */ +} + +void LPTIM_ClearInterruptStatus(LPTIM_Type * LPTIMx, uint32_t status) +{ + LPTIMx->IF = status; +} + +void LPTIM_EnableTriggerIn(LPTIM_Type * LPTIMx, LPTIM_TriggerInConf_Type * conf) +{ + LPTIMx->CFG = (LPTIMx->CFG & ~(LPTIM_CFG_TRIGSEL_MASK | LPTIM_CFG_FLTEN_MASK | LPTIM_CFG_TRIGCFG_MASK) ) + | LPTIM_CFG_TRIGSEL(conf->Channel) /* Setup trigger input channel. */ + | LPTIM_CFG_FLTEN(conf->EnableFilter) /* Setup the external trigger input filter. */ + | LPTIM_CFG_TRIGCFG(conf->TriggerInPolarity); /* Setup the trigger input polarity. */ +} + +void LPTIM_EnableOutWave(LPTIM_Type * LPTIMx, LPTIM_OutWaveConf_Type * conf) +{ + LPTIMx->CFG = (LPTIMx->CFG & ~ (LPTIM_CFG_PWM_MASK | LPTIM_CFG_POLARITY_MASK) ) + | LPTIM_CFG_PWM(conf->Wave) /* Setup the output waveform. */ + | LPTIM_CFG_POLARITY(conf->OutPolarity); /* Setup the output waveform polarity. */ +} + +void LPTIM_SetCompareValue(LPTIM_Type * LPTIMx, uint32_t value) +{ + LPTIMx->CMP = LPTIM_CMP_COMPAREREG(value); +} + +uint32_t LPTIM_GetCounterValue(LPTIM_Type * LPTIMx) +{ + return LPTIMx->CNT; /* return current counter value. */ +} + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_lptim.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_lptim.h new file mode 100644 index 000000000..67c2e6e56 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_lptim.h @@ -0,0 +1,244 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_LPTIM_H__ +#define __HAL_LPTIM_H__ + +#include "hal_common.h" + +/*! + * @addtogroup LPTIM + * @{ + */ + +/*! + * @brief LPTIM driver version number. + */ +#define LPTIM_DRIVER_VERSION 0u /*!< LPTIM_0. */ + +/*! + * @addtogroup LPTIM_STATUS + * @{ + */ +#define LPTIM_STATUS_COUNTER_OVERFLOW (1u << 0u) /*!< Status flag when LPTIM counter overflow. */ +#define LPTIM_STATUS_TRIGGER_INPUT (1u << 2u) /*!< Status flag when LPTIM trigger input. */ +#define LPTIM_STATUS_COMPARE_MATCH (1u << 1u) /*!< Status flag when LPTIM compare match. */ +/*! + * @} + */ + +/*! + * @addtogroup LPTIM_INT + * @{ + */ +#define LPTIM_INT_COUNTER_OVERFLOW (1u << 0u) /*!< Interrupt enable when LPTIM counter overflow. */ +#define LPTIM_INT_TRIGGER_INPUT (1u << 1u) /*!< Interrupt enable when LPTIM trigger input. */ +#define LPTIM_INT_COMPARE_MATCH (1u << 2u) /*!< Interrupt enable when LPTIM compare match. */ +/*! + * @} + */ + +/*! + * @brief LPTIM counter period working mode. + */ +typedef enum +{ + LPTIM_PeriodMode_Continuous = 0u, /*!< Counter works circularly once started. */ + LPTIM_PeriodMode_OneTimeRun = 1u, /*!< Counter only works one time once started. */ +} LPTIM_PeriodMode_Type; + +/*! + * @brief LPTIM work mode type. + */ +typedef enum +{ + LPTIM_WorkMode_Timer = 0u, /*!< Normal timer mode with output waveform feature. */ + LPTIM_WorkMode_Trigger = 1u, /*!< Pulse trigger counting mode. */ + LPTIM_WorkMode_WakeUpLowPower =3, /*!< Counter time out wake up MCU from low power mode. */ +} LPTIM_WorkMode_Type; + +/*! + * @brief LPTIM trigger input channel type. + */ +typedef enum +{ + LPTIM_TriggerInChannel_Pin = 0u, /*!< Select trigger pin as trigger input channel. */ + LPTIM_TriggerInChannel_Comp = 1u, /*!< Select Comparator output as trigger input channel. */ +} LPTIM_TriggerInChannel_Type; + +/*! + * @brief LPTIM trigger input polarity type. + */ +typedef enum +{ + LPTIM_TriggerInPolarity_Rising = 0u, /*!< Select rising edge as external trigger signal. */ + LPTIM_TriggerInPolarity_Falling = 1u, /*!< Select falling edge as external trigger signal. */ + LPTIM_TriggerInPolarity_RisingOrFalling = 2u, /*!< Select both the rising and falling edge as external trigger signal. */ +}LPTIM_TriggerInPolarity_Type; + +/*! + * @brief LPTIM output waveform type. + */ +typedef enum +{ + LPTIM_OutWave_Square = 0u, /*!< Select Square wave to output. */ + LPTIM_OutWave_PWM = 1u, /*!< Select PWM wave to output. */ +} LPTIM_OutWave_Type; + +/*! + * @brief LPTIM output polarity type. + */ +typedef enum +{ + LPTIM_OutPolarity_Rising = 0u, /*!< Output rising edge when the count value is equal to the compare value. */ + LPTIM_OutPolarity_Falling = 1u, /*!< Output falling edge when the count value is equal to the compare value. */ +} LPTIM_OutPolarity_Type; + +/*! + * @brief LPTIM prescaler type. + * + * Select the prescaler of time base as the LPTIM counter clock. + */ +typedef enum +{ + LPTIM_Prescaler_1 = 0u, /*!< LPTIM prescaler 1. */ + LPTIM_Prescaler_2 = 1u, /*!< LPTIM prescaler 2. */ + LPTIM_Prescaler_4 = 2u, /*!< LPTIM prescaler 4. */ + LPTIM_Prescaler_8 = 3u, /*!< LPTIM prescaler 8. */ + LPTIM_Prescaler_16 = 4u, /*!< LPTIM prescaler 16. */ + LPTIM_Prescaler_32 = 5u, /*!< LPTIM prescaler 32. */ + LPTIM_Prescaler_64 = 6u, /*!< LPTIM prescaler 64. */ + LPTIM_Prescaler_128 = 7u, /*!< LPTIM prescaler 128. */ +} LPTIM_Prescaler_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref LPTIM_Init() to initialize the LPTIM module. + */ +typedef struct +{ + uint32_t Period; /*!< Counter counting length, from 0 to period value, the value range: 0 ~ 65535.*/ + LPTIM_PeriodMode_Type PeriodMode; /*!< Specify the counter period mode. */ + LPTIM_WorkMode_Type WorkMode; /*!< Specify the LPTIM worke mode. */ + LPTIM_Prescaler_Type Prescaler; /*!< Specify the LPTIM counter time base division value. */ +} LPTIM_Init_Type; + +/*! + * @brief Setup the external trigger input configuration when calling the @ref LPTIM_EnableTriggerIn(). + */ +typedef struct +{ + LPTIM_TriggerInChannel_Type Channel; /*!< Specify the trigger input channel. */ + bool EnableFilter; /*!< 'true' to enable the external tirgger pin filter, 'false' to disable the filer. */ + LPTIM_TriggerInPolarity_Type TriggerInPolarity; /*!< Specify the trigger input polarity. */ +} LPTIM_TriggerInConf_Type; + +/*! + * @brief Setup the output waveform configuration when calling the @ref LPTIM_OutWaveConf_Type(). + */ +typedef struct +{ + LPTIM_OutWave_Type Wave; /*!< Specify output waveform. */ + LPTIM_OutPolarity_Type OutPolarity; /*!< Specify the waveform output pin polarity. */ +} LPTIM_OutWaveConf_Type; + +/*! + * @brief Initialize the LPTIM module. + * + * @param LPTIMx LPTIM instance. + * @param init Pointer to the initialization structure. See to @ref LPTIM_Init_Type. + * @return None. + */ +void LPTIM_Init(LPTIM_Type * LPTIMx, LPTIM_Init_Type * init); + +/*! + * @brief Start counting. + * + * @param LPTIMx LPTIM instance. + * @return None. + */ +void LPTIM_Start(LPTIM_Type * LPTIMx); + +/*! + * @brief Stop counting immediately. + * + * @param LPTIMx LPTIM instance. + * @return None. + */ +void LPTIM_Stop(LPTIM_Type * LPTIMx); + +/*! + * @brief Enable interrupts of the LPTIM module. + * + * @param LPTIMx LPTIM_Type instance. + * @param interrupts Interrupt code masks. See to @ref LPTIM_INT. + * @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts. + * @return None. + */ +void LPTIM_EnableInterrupts(LPTIM_Type * LPTIMx, uint32_t interrupts, bool enable); + +/*! + * @brief Get the interrupts status flags of the LPTIM module. + * + * @param LPTIMx LPTIM_Type instance. + * @return Interrupt status flags. See to @ref LPTIM_STATUS. + */ +uint32_t LPTIM_GetInterruptStatus(LPTIM_Type * LPTIMx); + +/*! + * @brief Clear the interrupts status flags of the LPTIM module. + * + * @param LPTIMx LPTIM_Type instance. + * @param interrupts The mask codes of the indicated interrupt flags to be cleared. + * @return None. + */ +void LPTIM_ClearInterruptStatus(LPTIM_Type * LPTIMx, uint32_t interrupts); + +/*! + * @brief Enable the external trigger input of the indicated counter. + * + * External trigger signal will trigger counter do addition. + * + * @param LPTIMx LPTIM_Type instance. + * @param conf Pointer to the configuration structure. See to @ref LPTIM_TriggerInConf_Type. + * @return None. + */ +void LPTIM_EnableTriggerIn(LPTIM_Type * LPTIMx, LPTIM_TriggerInConf_Type * conf); + +/*! + * @brief Enable output waveform. + * + * The output waveform could be PWM wave or suqare wave. + * + * @param LPTIMx LPTIM_Type instance. + * @param conf Pointer to the configuration structure. See to @ref LPTIM_OutWaveConf_Type. + * @return None. + */ +void LPTIM_EnableOutWave(LPTIM_Type * LPTIMx, LPTIM_OutWaveConf_Type * conf); + +/*! + * @brief Set the compare value. + * + * The compare value would be compared with counter value. + * + * @param LPTIMx LPTIM_Type instance. + * @param value The compare value to be set, the value range: 0 ~ 65535. + * @return none. + */ +void LPTIM_SetCompareValue(LPTIM_Type * LPTIMx, uint32_t value); + +/*! + * @brief Get the current counter value. + * + * @param LPTIMx LPTIM_Type instance. + * @return The current counter value. + */ +uint32_t LPTIM_GetCounterValue(LPTIM_Type * LPTIMx); + +/*! + *@} + */ +#endif /* __HAL_TIM_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_lpuart.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_lpuart.c new file mode 100644 index 000000000..79eb7bf49 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_lpuart.c @@ -0,0 +1,205 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_lpuart.h" + +void LPUART_SetBaudrate2(LPUART_Type * LPUARTx, uint32_t freq, uint32_t baudrate) +{ + LPUARTx->LPUBAUD |= LPUART_LPUBAUD_BREN_MASK; + uint32_t base_cycles = freq / baudrate; + uint32_t current_cycles = 0; + uint32_t ideal_K; + uint32_t K; + K = 0xFFFFFFFF / freq / 4 * 2; + LPUARTx->LPUBAUD |= LPUART_LPUBAUD_BR(base_cycles); + LPUARTx->MODU = 0; + for (uint8_t bit_idx = 0; bit_idx < 12; bit_idx++) + { + ideal_K = (uint32_t)( (base_cycles * K + 0.5) * (bit_idx + 1) ); + current_cycles += base_cycles; + if (current_cycles * K >= ideal_K) + { + continue; + } + else if ( (ideal_K - current_cycles * K) >= (K / 2) ) + { + LPUARTx->MODU |= 1 << bit_idx; + current_cycles += 1; + } + } +} + +/* LPUART initialization use LSE(32.768KHz) clock source. */ +void LPUART_Init(LPUART_Type * LPUARTx, LPUART_Init_Type * init) +{ + uint32_t lpuart_mctl[6] = {0x952, 0xefb, 0x6db, 0x482,0x6d6, 0x842}; + if (init->ClockSource == LPUART_ClockSource_LSE) + { + LPUARTx->LPUBAUD &= ~LPUART_LPUBAUD_BREN_MASK; /* BREN = 0, only 32.768KHz clock is supported as clock source. */ + LPUARTx->LPUBAUD = LPUART_LPUBAUD_BAUD(init->BaudRate); + LPUARTx->MODU = lpuart_mctl[init->BaudRate]; + } + + /* WordLength. */ + LPUARTx->LPUCON |= LPUART_LPUCON_DL(init->WordLength); + + /* StopBits. */ + LPUARTx->LPUCON |= LPUART_LPUCON_SL(init->StopBits); + + /* Parity. */ + if (init->Parity == LPUART_Parity_Even) + { + LPUARTx->LPUCON |= LPUART_LPUCON_PAREN_MASK; + LPUARTx->LPUCON &= ~LPUART_LPUCON_PTYP_MASK; + } + if (init->Parity == LPUART_Parity_Odd) + { + LPUARTx->LPUCON |= (LPUART_LPUCON_PAREN_MASK | LPUART_LPUCON_PTYP_MASK); + } +} + +/* LPUART enable tx. */ +void LPUART_EnableTx(LPUART_Type * LPUARTx, bool enable) +{ + if (enable) + { + LPUARTx->LPUEN |= LPUART_LPUEN_TXEN_MASK; + } + else + { + LPUARTx->LPUEN &= ~LPUART_LPUEN_TXEN_MASK; + } +} + +/* LPUART enable rx. */ +void LPUART_EnableRx(LPUART_Type * LPUARTx, bool enable) +{ + if (enable) + { + LPUARTx->LPUEN |= LPUART_LPUEN_RXEN_MASK; + } + else + { + LPUARTx->LPUEN &= ~LPUART_LPUEN_RXEN_MASK; + } +} + +/* LPUART get status. */ +uint32_t LPUART_GetStatus(LPUART_Type * LPUARTx) +{ + return LPUARTx->LPUSTA; +} + +/* LPUART put data. */ +void LPUART_PutData(LPUART_Type * LPUARTx, uint8_t value) +{ + LPUARTx->LPUTXD = value; +} + +/* LPAURT put data. */ +uint8_t LPUART_GetData(LPUART_Type * LPUARTx) +{ + return (uint8_t)(LPUARTx->LPURXD & 0xff); +} + +/* LPUART enable interrupt. */ +void LPUART_EnableInterrupts(LPUART_Type * LPUARTx, uint32_t interrupts, bool enable) +{ + switch (interrupts) + { + case LPUART_INT_RX_FULL: + if (enable) + { + LPUARTx->LPUCON |= LPUART_LPUCON_RXIE_MASK; + } + else + { + LPUARTx->LPUCON &= ~LPUART_LPUCON_TCIE_MASK; + } + break; + case LPUART_INT_TX_EMPTY: + if (enable) + { + LPUARTx->LPUCON |= LPUART_LPUCON_TXIE_MASK; + } + else + { + LPUARTx->LPUCON &= ~LPUART_LPUCON_TXIE_MASK; + } + break; + case LPUART_INT_TX_DONE: + if (enable) + { + LPUARTx->LPUCON |= LPUART_LPUCON_TCIE_MASK; + } + else + { + LPUARTx->LPUCON &= ~LPUART_LPUCON_TCIE_MASK; + } + break; + default: + break; + } +} + +/* Get LPUART interrupt status. */ +uint32_t LPUART_GetInterruptStatus(LPUART_Type * LPUARTx) +{ + return LPUARTx->LPUIF; +} + +/* Get LPUART interrupt enable status. */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type * LPUARTx) +{ + uint32_t flags = 0u; + if ( 0u != (LPUART_LPUCON_RXIE_MASK & LPUARTx->LPUCON) ) + { + flags |= LPUART_INT_RX_FULL; + } + if ( 0u != (LPUART_LPUCON_TXIE_MASK & LPUARTx->LPUCON) ) + { + flags |= LPUART_INT_TX_EMPTY; + } + if ( 0u != (LPUART_LPUCON_TCIE_MASK & LPUARTx->LPUCON) ) + { + flags |= LPUART_INT_TX_DONE; + } + return flags; +} + +/* Clear LPUART interrupt status. */ +void LPUART_ClearInterruptStatus(LPUART_Type * LPUARTx, uint32_t interrupts) +{ + LPUARTx->LPUIF |= interrupts; +} + +/* LPUART enable DMA. */ +void LPUART_EnableDMA(LPUART_Type * LPUARTx, uint32_t dma, bool enable) +{ + if (enable) + { + LPUARTx->LPUEN |= dma; + } + else + { + LPUARTx->LPUEN &= ~dma; + } +} + +/* LPUART get tx data register address. */ +uint32_t LPUART_GetTxDataRegAddr(LPUART_Type * LPUARTx) +{ + return (uint32_t)(&(LPUARTx->LPUTXD)); +} + +/* LPUART get rx data register address. */ +uint32_t LPUART_GetRxDataRegAddr(LPUART_Type * LPUARTx) +{ + return (uint32_t)(&(LPUARTx->LPURXD)); +} + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_lpuart.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_lpuart.h new file mode 100644 index 000000000..bf1726d98 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_lpuart.h @@ -0,0 +1,239 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_LPUART_H__ +#define __HAL_LPUART_H__ + +#include "hal_common.h" + +/*! + * @addtogroup LPUART + * @{ + */ + +/*! + * @addtogroup LPUART_STATUS + * @{ + */ +#define LPUART_STATUS_RX_FULL LPUART_LPUSTA_RXF_MASK /*!< Status flag when LPUART receiving buffer is full. */ +#define LPUART_STATUS_TX_EMPTY LPUART_LPUSTA_TXE_MASK /*!< Status flag when LPUART transmiter buffer is empty. */ +#define LPUART_STATUS_TX_DONE LPUART_LPUSTA_TC_MASK /*!< Status flag when LPUART transmiter shifter is empty after the transfer is done. */ +/*! + * @} + */ + +/*! + * @addtogroup LPUART_INT + * @{ + */ +#define LPUART_INT_RX_FULL (1u << 0u) /*!< Interrupt enable when LPUART receiving buffer is full. */ +#define LPUART_INT_TX_EMPTY (1u << 1u) /*!< Interrupt enable when LPUART transmiter buffer is empty. */ +#define LPUART_INT_TX_DONE (1u << 3u) /*!< Interrupt enable when LPUART transmiter is done. */ +/*! + * @} + */ + +/*! + * @addtogroup LPUART_DMA + * @{ + */ +#define LPUART_DMA_TX LPUART_LPUEN_DMAT_MASK /*!< Enable LPUART DMA tx only. */ +#define LPUART_DMA_RX LPUART_LPUEN_DMAR_MASK /*!< Enable LPUART DMA rx only. */ +#define LPUART_DMA_TXRX (LPUART_LPUEN_DMAT_MASK | LPUART_LPUEN_DMAR_MASK) /*!< Enable LPUART DMA tx and rx. */ +/*! + * @} + */ + +/*! + * @brief LPUART clock source select. + */ +typedef enum +{ + LPUART_ClockSource_LSE = 0u, /*!< Clock soucre is LSE. */ +} LPUART_ClockSource_Type; + +/*! + * @brief LPUART use LSE as clock source's baudrate type. + */ +typedef enum +{ + LPUART_Baudrate_9600 = 0x000, /*!< Baudrate is 9600 when clock source is LSE. */ + LPUART_Baudrate_4800 = 0x001, /*!< Baudrate is 4800 when clock source is LSE. */ + LPUART_Baudrate_2400 = 0x010, /*!< Baudrate is 2400 when clock source is LSE. */ + LPUART_Baudrate_1200 = 0x011, /*!< Baudrate is 1200 when clock source is LSE. */ + LPUART_Baudrate_600 = 0x100, /*!< Baudrate is 600 when clock source is LSE. */ + LPUART_Baudrate_300 = 0x101, /*!< Baudrate is 300 when clock source is LSE. */ +} LPUART_Baudrate_Type; + +/*! + * @brief LPUART word length type. + */ +typedef enum +{ + LPUART_WordLength_8 = 0u, /*!< Word length 8 bits. */ + LPUART_WordLength_7 = 1u, /*!< Word length 7 bits. */ +} LPUART_WordLength_Type; + +/*! + * @brief LPUART stop bits type. + */ +typedef enum +{ + LPUART_StopBits_1 = 0u, /* stop bit is 1 bit */ + LPUART_StopBits_2 = 1u, /* stop bit is 2 bit */ +} LPUART_StopBits_Type; + +/*! + * @brief LPUART parity type. + */ +typedef enum +{ + LPUART_Parity_None = 0u, /*!< No parity. */ + LPUART_Parity_Even = 1u, /*!< Even parity. */ + LPUART_Parity_Odd = 2u, /*!< Odd parity. */ +} LPUART_Parity_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref LPUART_Init() to initialize the LPUART module. + */ +typedef struct +{ + LPUART_ClockSource_Type ClockSource; /*!< LPUART clock source. */ + LPUART_Baudrate_Type BaudRate; /*!< Specify the LPUART LSE specific baud rate. */ + LPUART_WordLength_Type WordLength; /*!< Specify the number of data bits transmitted or received in a frame. */ + LPUART_StopBits_Type StopBits; /*!< Specify the number of stop bits transmitted. */ + LPUART_Parity_Type Parity; /*!< Specify the parity mode. */ +} LPUART_Init_Type; + +/*! + * @brief Initialize the LPUART module. + * + * @param LPUARTx LPUART instance. + * @param init Pointer to the initialization structure. See to @ref LPUART_Init_Type. + * @return None. + */ +void LPUART_Init(LPUART_Type * LPUARTx, LPUART_Init_Type * init); + +/*! + * @brief Enable the LPUART tx module. + * + * The LPUART Tx module should be enabled before sending data. + * + * @param LPUARTx LPUART instance. + * @param enable 'true' to enable the module, 'false' to disable the module. + * @return None. + */ +void LPUART_EnableTx(LPUART_Type * LPUARTx, bool enable); + +/*! + * @brief Enable the LPUART rx module. + * + * The LPUART module should be enabled before receiving data. + * + * @param LPUARTx LPUART instance. + * @param enable 'true' to enable the module, 'false' to disable the module. + * @return None. + */ +void LPUART_EnableRx(LPUART_Type * LPUARTx, bool enable); + +/*! + * @brief Get the current status flags of the LPUART module. + * + * @param LPUARTx LPUART instance. + * @return Status flags. See to @ref LPUART_STATUS. + */ +uint32_t LPUART_GetStatus(LPUART_Type * LPUARTx); + +/*! + * @brief Put the data into transmiter buffer of the LPUART module. + * + * @param LPUARTx LPUART instance. + * @param value Data value to be send through the transmiter. + * @return None. + */ +void LPUART_PutData(LPUART_Type * LPUARTx, uint8_t value); + +/*! + * @brief Get the data from receiver buffer of the LPUART module. + * + * @param LPUARTx LPUART instance. + * @return The data value received from the receiver. + */ +uint8_t LPUART_GetData(LPUART_Type * LPUARTx); + +/*! + * @brief Enable interrupts of the LPUART module. + * + * @param LPUARTx LPUART instance. + * @param interrupts Interrupt code masks. See to @ref LPUART_INT. + * @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts. + * @return None. + */ +void LPUART_EnableInterrupts(LPUART_Type * LPUARTx, uint32_t interrupts, bool enable); + +/*! + * @brief Get the interrupts status flags of the LPUART module. + * + * @param LPUARTx LPUART instance. + * @return Interrupt status flags. See to @ref LPUART_INT. + */ +uint32_t LPUART_GetInterruptStatus(LPUART_Type * LPUARTx); + +/*! + * @brief Read the current enabled interrupts the LPUART module. + * + * @param LPUARTx LPUART instance. + * @return The mask codes enabled interrupts. See to @ref LPUART_INT + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type * LPUARTx); + +/*! + * @brief Clear the interrupts status flags of the LPUART module. + * + * @param LPUARTx LPUART instance. + * @param interrupts The mask codes of the indicated interrupt flags to be cleared. + * @return Interrupt status flags. See to @ref LPUART_INT. + */ +void LPUART_ClearInterruptStatus(LPUART_Type * LPUARTx, uint32_t interrupts); + +/*! + * @brief Enable the DMA trigger from the LPUART module. + * + * The DMA trigger events are the same as the interrupts. + * + * @param LPUARTx LPUART instance. + * @param dma DMA xfer direction. + * @param enable 'true' to enable the DMA trigger, 'false' to disable the DMA trigger. + * @return None. + */ +void LPUART_EnableDMA(LPUART_Type * LPUARTx, uint32_t dma, bool enable); + +/*! + * @brief Get the hardware Tx data buffer's address the LPUART module. + * + * The return value of the address is most used with DMA module. + * + * @param LPUARTx LPUART instance. + * @return The value of the address for LPUART module's hardware Tx data buffer. + */ +uint32_t LPUART_GetTxDataRegAddr(LPUART_Type * LPUARTx); + +/*! + * @brief Get the hardware Rx data buffer's address the LPUART module. + * + * The return value of the address is most used with DMA module. + * + * @param LPUARTx LPUART instance. + * @return The value of the address for LPUART module's hardware Rx data buffer. + */ +uint32_t LPUART_GetRxDataRegAddr(LPUART_Type * LPUARTx); + +/*! + *@} + */ + +#endif /* __HAL_UART_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_mds.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_mds.c new file mode 100644 index 000000000..86f1891a4 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_mds.c @@ -0,0 +1,82 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_mds.h" + +/* Configure the trigger mode, not using clu out as the trigger in. */ +void MDS_EnableTrigger(MDS_Type * MDSx, uint32_t out, uint32_t in, MDS_TriggerInMode_Type trigger_mode) +{ + MDSx->TRIGXCR[out] =( MDSx->TRIGXCR[out] & ~(MDS_TRIGXCR_CLUEN_MASK | MDS_TRIGXCR_TRGSEL_MASK | MDS_TRIGXCR_EDGESEL_MASK) ) + | MDS_TRIGXCR_TRGSEL(trigger_mode) + | MDS_TRIGXCR_TRGSEL(in) + ; +} + +/* enable the software trigger as the trigger source. */ +void MDS_DoSwTrigger(MDS_Type * MDSx) +{ + MDSx->SWTRIG = MDS_SWTRIG_SWTRIG_MASK; +} + +/* Configure the connection mode, not using clu out as the connection in. */ +void MDS_EnableConn(MDS_Type * MDSx, uint32_t out, uint32_t in) +{ + MDSx->CONNXCR[out] =( MDSx->CONNXCR[out] & ~(MDS_CONNXCR_CLUEN_MASK | MDS_CONNXCR_TRGSEL_MASK ) ) + | MDS_CONNXCR_TRGSEL(in) + ; +} + +/* Configure the trigger mode, using clu out as the trigger in. */ +void MDS_EnableTriggerClu(MDS_Type * MDSx, uint32_t out, uint32_t in, MDS_CluConf_Type * conf) +{ + if (!conf) + { + return; + } + + MDSx->TRIGXCR[out] =( MDSx->TRIGXCR[out] & ~(MDS_TRIGXCR_CLUEN_MASK | MDS_TRIGXCR_TRGSEL_MASK | MDS_TRIGXCR_EDGESEL_MASK) ) + | MDS_TRIGXCR_CLUSEL(in) + ; + /* configure the trigger in for one clu in. */ + for (uint32_t i = 0; iTRIGCLUXSEL[in] |= conf->CluInSource[i] << (i * 8u); + } + /* configure the each trigger detection edge mode. */ + MDSx->TRIGCLUXCFG[in] = conf->CluInSourceTriggerEdgeMask; + /* configure the each trigger in inverter and the clu operation logic. */ + MDSx->CONNCLUXCFG[in] = conf->CluInSourceInvertMask | conf->CluLogic; + /* enable the clu mode. */ + MDSx->TRIGXCR[out] |= MDS_TRIGXCR_CLUEN_MASK; +} + +/* Configure the clu out as the trigger source mode . */ +void MDS_EnableConnClu(MDS_Type * MDSx, uint32_t out, uint32_t in, MDS_CluConf_Type * conf) +{ + if (!conf) + { + return; + } + + MDSx->CONNXCR[out] = ( MDSx->CONNXCR[out] & ~ (MDS_CONNXCR_CLUEN_MASK | MDS_CONNXCR_CLUSEL_MASK)) + | MDS_CONNXCR_CLUSEL(in) + ; + + /* configure the connection in for one clu in. */ + for (uint32_t i = 0; iCONNCLUXSEL[in] |= conf->CluInSource[i] << (i * 8u); + } + /* configure the each trigger in inverter and the clu operation logic. */ + MDSx->CONNCLUXCFG[in] = conf->CluInSourceInvertMask | conf->CluLogic; + /* enable the clu mode. */ + MDSx->CONNXCR[out] |= MDS_CONNXCR_CLUEN_MASK; + +} + + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_mds.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_mds.h new file mode 100644 index 000000000..af8f18805 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_mds.h @@ -0,0 +1,123 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_MDS_H__ +#define __HAL_MDS_H__ + +#include "hal_common.h" +#include "hal_mds_remap.h" +/*! + * @addtogroup MDS + * @{ + */ + +/*! + * @brief MDS driver version number. + */ +#define MDS_DRIVER_VERSION 0u /*!< mds_0. */ + +/*! + * @brief MDS TriggerInMode type. + * + * Use the Trigger in mode, selecting the edge detection mode for the trigger source. + */ +typedef enum +{ + MDS_TriggerInMode_RisingEdge = 0u, /*!< Select Rising edge detection. */ + MDS_TriggerInMode_FallingEdge = 1u, /*!< Select Falling edge detection. */ + MDS_TriggerInMode_BothEdges = 2u, /*!< Select Rising and Falling edge detection. */ +}MDS_TriggerInMode_Type; + +/*! + * @brief MDS CluLogic type. + * + * Select the operation logic of the Clu. + */ +typedef enum +{ + MDS_CluLogic_OR_OR = 0u, /*!< The operation logic selects the OR-OR logic, and the four input logics are in0|in1|in2|in3. */ + MDS_CluLogic_AND_OR = 1u, /*!< The operation logic selects the AND-OR logic, and the four input logics are (in0&in1)|(in2&in3). */ + MDS_CluLogic_OR_XOR = 2u, /*!< The operation logic selects the OR-XOR logic, and the four input logics are (in0|in1)^(in2|in3). */ + MDS_CluLogic_AND_AND = 3u, /*!< The operation logic selects the OR-OR logic, and the four input logics are in0&in1&in2&in3. */ +}MDS_CluLogic_Type; + +/*! + * @brief This type of structure instance is used to keep the settings + * when calling the @ref MDS_EnableTriggerClu() or @ref MDS_EnableConnClu() to configure using the Clu out as the trigger source. + */ + +typedef struct +{ + uint32_t CluInSource[MDS_CLU_IN_LEN]; /*!< Select the trigger and connection source for each of Clu in, TRIGGER_IN_SOURCE_LEN is the max input length. */ + uint32_t CluInSourceInvertMask; /*!< Select trigger or connect the source after taking the inverse as input to the clu. */ + uint32_t CluInSourceTriggerEdgeMask; /*!< Select the clu in source trigger edge detection mode. */ + MDS_CluLogic_Type CluLogic; /*!< Select the Clu operation logic. */ +} MDS_CluConf_Type; + +/*! + * @brief Enable the trigger mode without clu output as connection source in. + * the hal_mds_remap.h define the mds(mindswitch) in or out, the trigger in correspond to trigger out. + * + * @param MDSx MDS instance. + * @param out the trigger source, see to hal_mds_remap.h. + * @param in the trigger target, see to hal_mds_remap.h. + * @param trigger_mode select the trigger in edge detection mode. + * @return None. + */ +void MDS_EnableTrigger(MDS_Type * MDSx, uint32_t out, uint32_t in, MDS_TriggerInMode_Type trigger_mode); + +/*! + * @brief Enable software trigger as the trigger source in. + * when using the software trigger as the trigger source, enable it and it can only finish once trigger. + * + * @param MDSx MDS instance. + * @param enable true is enable the software trigger as the trigger source, false is not enable. + * @return None. + */ +void MDS_DoSwTrigger(MDS_Type * MDSx); + +/*! + * @brief Enable the connection mode without clu output as connection source in. + * the hal_mds_remap.h define the mds(mindswitch) in or out, the connection in correspond to conntion out. + * + * @param MDSx MDS instance. + * @param out the connection target, see to hal_mds_remap.h. + * @param in the input of connection, see to hal_mds_remap.h. + * @return None. + */ +void MDS_EnableConn(MDS_Type * MDSx, uint32_t out, uint32_t in); + +/*! + * @brief Enable the clu output as the trigger source in. + * the hal_mds_remap.h define the mds(mindswitch) in or out, the connection in correspond to conntion out. + * + * @param MDSx MDS instance. + * @param conf configure the clu parameter, @ref MDS_CluConf_Type. + * @param out select the trigger out, see to hal_mds_remap.h. + * @param in select which clu in, see to hal_mds_remap.h. + * @return None. + */ +void MDS_EnableTriggerClu(MDS_Type * MDSx, uint32_t out, uint32_t in, MDS_CluConf_Type * conf); + +/*! + * @brief Enable the clu output as the connection source in. + * the hal_mds_remap.h define the mds(mindswitch) in or out, the connection in correspond to conntion out. + * + * @param MDSx MDS instance. + * @param conf configure the clu parameter, @ref MDS_CluConf_Type. + * @param out select the connection out, see to hal_mds_remap.h. + * @param in select which clu in, see to hal_mds_remap.h. + * @return None. + */ +void MDS_EnableConnClu(MDS_Type * MDSx, uint32_t out, uint32_t in, MDS_CluConf_Type * conf); + + +/*! + *@} + */ + +#endif /*__HAL_MDS_H__. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_mds_remap.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_mds_remap.h new file mode 100644 index 000000000..0aa8e202b --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_mds_remap.h @@ -0,0 +1,119 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* define the mds(mindswitch) in and out, the trigger in only from trigger out. the connection in only for connection out. */ + +#ifndef __HAL_MDS_REMAP_H__ +#define __HAL_MDS_REMAP_H__ + +#define MDS_CLU_IN_LEN 4u /* one clu input max length. */ + +#define CONN_TRIGGER_IN_MASK 19u /* define the connection trigger source mask. */ + +/* Trigger In. */ +#define MDS_TRIGGER_IN_LOGIC_0 0u +#define MDS_TRIGGER_IN_LOGIC_1 1u +#define MDS_TRIGGER_IN_SW 2u +#define MDS_TRIGGER_IN_TIM1_CC1 3u +#define MDS_TRIGGER_IN_TIM1_CC2 4u +#define MDS_TRIGGER_IN_TIM1_CC3 5u +#define MDS_TRIGGER_IN_TIM1_CC4 6u +#define MDS_TRIGGER_IN_TIM1_CC5 7u +#define MDS_TRIGGER_IN_TIM2_CC1 8u +#define MDS_TRIGGER_IN_TIM2_CC2 9u +#define MDS_TRIGGER_IN_TIM2_CC3 10u +#define MDS_TRIGGER_IN_TIM2_CC4 11u +#define MDS_TRIGGER_IN_TIM3_CC1 12u +#define MDS_TRIGGER_IN_TIM3_CC2 13u +#define MDS_TRIGGER_IN_TIM3_CC3 14u +#define MDS_TRIGGER_IN_TIM3_CC4 15u +#define MDS_TRIGGER_IN_TIM4_CC1 16u +#define MDS_TRIGGER_IN_TIM4_CC2 17u +#define MDS_TRIGGER_IN_TIM4_CC3 18u +#define MDS_TRIGGER_IN_TIM4_CC4 19u +#define MDS_TRIGGER_IN_TIM5_CC1 20u +#define MDS_TRIGGER_IN_TIM5_CC2 21u +#define MDS_TRIGGER_IN_TIM5_CC3 22u +#define MDS_TRIGGER_IN_TIM5_CC4 23u +#define MDS_TRIGGER_IN_TIM8_CC1 24u +#define MDS_TRIGGER_IN_TIM8_CC2 25u +#define MDS_TRIGGER_IN_TIM8_CC3 26u +#define MDS_TRIGGER_IN_TIM8_CC4 27u +#define MDS_TRIGGER_IN_TIM8_CC5 28u +#define MDS_TRIGGER_IN_TIM1_OUT 29u +#define MDS_TRIGGER_IN_TIM2_OUT 30u +#define MDS_TRIGGER_IN_TIM3_OUT 31u +#define MDS_TRIGGER_IN_TIM4_OUT 32u +#define MDS_TRIGGER_IN_TIM5_OUT 33u +#define MDS_TRIGGER_IN_TIM8_OUT 36u +#define MDS_TRIGGER_IN_EXTI0 37u +#define MDS_TRIGGER_IN_EXTI1 38u +#define MDS_TRIGGER_IN_EXTI2 39u +#define MDS_TRIGGER_IN_EXTI3 40u +#define MDS_TRIGGER_IN_EXTI4 41u +#define MDS_TRIGGER_IN_EXTI5 42u +#define MDS_TRIGGER_IN_EXTI6 43u +#define MDS_TRIGGER_IN_EXTI7 44u +#define MDS_TRIGGER_IN_EXTI8 45u +#define MDS_TRIGGER_IN_EXTI9 46u +#define MDS_TRIGGER_IN_EXTI10 47u +#define MDS_TRIGGER_IN_EXTI11 48u +#define MDS_TRIGGER_IN_EXTI12 49u +#define MDS_TRIGGER_IN_EXTI13 50u +#define MDS_TRIGGER_IN_EXTI14 51u +#define MDS_TRIGGER_IN_EXTI15 52u +#define MDS_TRIGGER_IN_CLU0 (0u << 17u) +#define MDS_TRIGGER_IN_CLU1 (1u << 17u) +#define MDS_TRIGGER_IN_CLU2 (2u << 17u) +#define MDS_TRIGGER_IN_CLU3 (3u << 17u) + +/* Trigger Out. */ +#define MDS_TRIGGER_OUT_ADC1_EXT_TRIGGER 0u +#define MDS_TRIGGER_OUT_ADC1_INJECT_EXT_TRIGGER 1u +#define MDS_TRIGGER_OUT_ADC2_EXT_TRIGGER 2u +#define MDS_TRIGGER_OUT_ADC2_INJECT_EXT_TRIGGER 3u +#define MDS_TRIGGER_OUT_DAC1_EXT_TRIGGER 6u +#define MDS_TRIGGER_OUT_DAC2_EXT_TRIGGER 7u + +/* Connection In. */ +#define MDS_CONN_IN_LOGIC_0 0u +#define MDS_CONN_IN_LOGIC_1 1u +#define MDS_CONN_IN_TIM1_CH1_OUT 2u +#define MDS_CONN_IN_TIM1_CH1N_OUT 3u +#define MDS_CONN_IN_TIM1_CH2_OUT 4u +#define MDS_CONN_IN_TIM1_CH2N_OUT 5u +#define MDS_CONN_IN_TIM1_CH3_OUT 6u +#define MDS_CONN_IN_TIM1_CH3N_OUT 7u +#define MDS_CONN_IN_TIM1_CH4_OUT 8u +#define MDS_CONN_IN_TIM1_CH4N_OUT 9u +#define MDS_CONN_IN_TIM2_CH1_OUT 10u +#define MDS_CONN_IN_TIM2_CH2_OUT 11u +#define MDS_CONN_IN_TIM2_CH3_OUT 12u +#define MDS_CONN_IN_TIM2_CH4_OUT 13u +#define MDS_CONN_IN_TIM3_CH4_OUT 14u +#define MDS_CONN_IN_TIM4_CH4_OUT 15u +#define MDS_CONN_IN_TIM5_CH4_OUT 16u +#define MDS_CONN_IN_TIM8_CH4_OUT 17u +#define MDS_CONN_IN_MDS_IN0 18u +#define MDS_CONN_IN_MDS_IN1 19u +#define MDS_CONN_IN_MDS_IN2 20u +#define MDS_CONN_IN_MDS_IN3 21u +#define MDS_CONN_IN_CLU0 (0u << 17u) +#define MDS_CONN_IN_CLU1 (1u << 17u) +#define MDS_CONN_IN_CLU2 (2u << 17u) +#define MDS_CONN_IN_CLU3 (3u << 17u) + +/*Connection Out. */ +#define MDS_CONN_OUT_COMP1_BLANK 0u +#define MDS_CONN_OUT_COMP2_BLANK 1u +#define MDS_CONN_OUT_COMP3_BLANK 2u +#define MDS_CONN_OUT_MDS_OUT0 3u +#define MDS_CONN_OUT_MDS_OUT1 4u +#define MDS_CONN_OUT_MDS_OUT2 5u +#define MDS_CONN_OUT_MDS_OUT3 6u + +#endif /*__HAL_MDS_REMAP_H__. */ \ No newline at end of file diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_power.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_power.c new file mode 100644 index 000000000..e3a261173 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_power.c @@ -0,0 +1,105 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_power.h" + +void CORE_EnterSleepMode(bool sleep_on_exit, bool sleep_deep, POWER_WakeUp_Type mode) +{ + if (sleep_on_exit) + { + SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; + } + else + { + SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk; + } + + if (sleep_deep) + { + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + } + else + { + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + } + + if (mode == POWER_WakeUp_Interrupt) + { + __WFI(); + } + if (mode == POWER_WakeUp_Event) + { + __WFE(); + } +} + +void POWER_EnterRunMode(void) +{ + PWR_EnableLowPowerRunMode(PWR, false); +} + +void POWER_EnableLowPowerRunMode(void) +{ + PWR_EnableLowPowerRunMode(PWR, true); +} + +void POWER_EnterSleepMode(POWER_SleepConf_Type * conf) +{ + CORE_EnterSleepMode(conf->SleepOnExit, false, conf->WakeUpMode); +} + +void POWER_EnterStopMode(POWER_StopConf_Type * conf) +{ + PWR_EnterStopMode(PWR, conf->DeepStop); + + CORE_EnterSleepMode(false, true, conf->WakeUpMode); +} + +void POWER_EnableStandbyWakeUpPin(PWR_StandbyWakeUpPinConf_Type * conf) +{ + PWR_EnableStandbyWakeUpPin(PWR, conf); +} + +void POWER_EnterStandbyMode(POWER_StandbyConf_Type * conf) +{ + PWR_EnterStandbyMode(PWR, conf->Delay); + + CORE_EnterSleepMode(false, true, conf->WakeUpMode); +} + +void POWER_SelectMode(POWER_Mode_Type mode, void * conf) +{ + switch (mode) + { + case POWER_Mode_Run: + POWER_EnterRunMode(); + break; + case POWER_Mode_LowPowerRun: + POWER_EnableLowPowerRunMode(); + break; + case POWER_Mode_Sleep: + POWER_EnterSleepMode( (POWER_SleepConf_Type *) conf); + break; + case POWER_Mode_LowPowerSleep: + POWER_EnableLowPowerRunMode(); + POWER_EnterSleepMode( (POWER_SleepConf_Type *) conf); + break; + case POWER_Mode_Stop: + POWER_EnterStopMode( (POWER_StopConf_Type *) conf); + break; + case POWER_Mode_DeepStop: + POWER_EnterStopMode( (POWER_StopConf_Type *) conf); + break; + case POWER_Mode_Standby: + POWER_EnterStandbyMode( (POWER_StandbyConf_Type *) conf); + break; + default: + break; + } +} + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_power.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_power.h new file mode 100644 index 000000000..095ed07c5 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_power.h @@ -0,0 +1,120 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_POWER_H__ +#define __HAL_POWER_H__ + +#include "hal_common.h" +#include "hal_pwr.h" + +/*! + * @brief POWER mode type. + */ +typedef enum +{ + POWER_Mode_Run = 0u, /*!< Run mode selected. */ + POWER_Mode_LowPowerRun = 1u, /*!< Low power run mode selected. */ + POWER_Mode_Sleep = 2u, /*!< Sleep mode selected. */ + POWER_Mode_LowPowerSleep = 3u, /*!< Low power sleep mode selected. */ + POWER_Mode_Stop = 4u, /*!< Stop mode selected. */ + POWER_Mode_DeepStop = 5u, /*!< Deep stop mode selected. */ + POWER_Mode_Standby = 6u, /*!< Standby mode selected. */ +} POWER_Mode_Type; + +/*! + * @brief POWER wake up type. + */ +typedef enum +{ + POWER_WakeUp_Interrupt = 0u, /*!< Select the interrupt wake up. */ + POWER_WakeUp_Event = 1u, /*!< Select the event wake up. */ +} POWER_WakeUp_Type; + +/*! + * @brief POWER sleep mode parameter type. + */ +typedef struct +{ + bool SleepOnExit; /*!< 'true' to sleep after exit from ISR, 'false' to sleep immediately. */ + POWER_WakeUp_Type WakeUpMode; /*!< Specify wake up mode. See to @ref POWER_WakeUp_Type. */ +} POWER_SleepConf_Type; + +/*! + * @brief POWER stop mode parameter type. + */ +typedef struct +{ + bool DeepStop; /*!< 'true' to enable the deep stop mode, 'false' to disable the deep stop mode. */ + POWER_WakeUp_Type WakeUpMode; /*!< Specify wake up mode. See to @ref POWER_WakeUp_Type. */ +} POWER_StopConf_Type; + +/*! + * @brief POWER standby mode parameter type. + */ +typedef struct +{ + PWR_StandbyWakeUpDelay_Type Delay; /*!< Specify standby mode wake up delay value. See to @ref PWR_StandbyWakeUpDelay_Type. */ + POWER_WakeUp_Type WakeUpMode; /*!< Specify wake up mode. See to @ref POWER_WakeUp_Type. */ +} POWER_StandbyConf_Type; + +/*! + * @brief Select power mode. + * + * @param mode power mode. See to @ref POWER_Mode_Type. + * @param param Pointer to the initialization structure. + * @return None. + */ +void POWER_SelectMode(POWER_Mode_Type mode, void * conf); + +/*! + * @brief Enter run mode. + * + * @return None. + */ +void POWER_EnterRunMode(void); + +/*! + * @brief Enable low power run mode. + * + * @return None. + */ +void POWER_EnableLowPowerRunMode(void); + +/*! + * @brief Enter sleep mode. + * + * @param param Pointer to the initialization structure. See to @ref POWER_SleepConf_Type. + * @return None. + */ +void POWER_EnterSleepMode(POWER_SleepConf_Type * conf); + +/*! + * @brief Enter stop mode. + * + * @param param Pointer to the initialization structure. See to @ref POWER_StopConf_Type. + * @return None. + */ +void POWER_EnterStopMode(POWER_StopConf_Type * conf); + +/*! + * @brief Enable standby wake up pin. + * + * @param PWRx PWR instance. + * @param init Pointer to the initialization structure. See to @ref PWR_StandbyWakeUpPinConf_Type. + * @return None. + */ +void POWER_EnableStandbyWakeUpPin(PWR_StandbyWakeUpPinConf_Type * conf); + +/*! + * @brief Enter standby mode. + * + * @param param Pointer to the initialization structure. See to @ref POWER_StandbyConf_Type. + * @return None. + */ +void POWER_EnterStandbyMode(POWER_StandbyConf_Type * conf); + +#endif /* __HAL_POWER_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_pwr.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_pwr.c new file mode 100644 index 000000000..0ec4fa011 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_pwr.c @@ -0,0 +1,163 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_pwr.h" + +void PWR_EnableLowPowerRunMode(PWR_Type * PWRx, bool enable) +{ + if (enable) + { + PWRx->CR1 |= PWR_CR1_LPR_MASK; + } + else + { + PWRx->CR1 &= ~PWR_CR1_LPR_MASK; + } +} + +void PWR_EnterStopMode(PWR_Type * PWRx, bool deep_stop) +{ + PWRx->CR1 &= ~PWR_CR1_PDDS_MASK; + + if (deep_stop) + { + PWRx->CR1 |= PWR_CR1_LPDS_MASK; + } + else + { + PWRx->CR1 &= ~PWR_CR1_LPDS_MASK; + } +} + +void PWR_EnableStandbyWakeUpPin(PWR_Type * PWRx, PWR_StandbyWakeUpPinConf_Type * conf) +{ + if (NULL != conf) + { + PWRx->CR2 |= PWR_CR2_EWUP(conf->Pins); + + if (conf->TrgIn == PWR_StandbyWakeUpPinTriggerIn_FallingEdge) + { + PWRx->CR3 |= PWR_CR3_WP(conf->Pins); + } + if (conf->TrgIn == PWR_StandbyWakeUpPinTriggerIn_RisingEdge) + { + PWRx->CR3 &= ~PWR_CR3_WP(conf->Pins); + } + } + else + { + PWRx->CR2 &= ~PWR_CR2_EWUP_MASK; + } +} + +void PWR_EnableStandbyWakeUpPinFilter0(PWR_Type * PWRx, PWR_StandbyWakeUpPinFilter0Conf_Type * conf) +{ + if (NULL != conf) + { + if (conf->Pin == PWR_WAKEUP_PIN_0) + { + PWRx->CR4 |= PWR_CR4_FILTSEL0(0u); + } + if (conf->Pin == PWR_WAKEUP_PIN_1) + { + PWRx->CR4 |= PWR_CR4_FILTSEL0(1u); + } + if (conf->Pin == PWR_WAKEUP_PIN_2) + { + PWRx->CR4 |= PWR_CR4_FILTSEL0(2u); + } + if ( (conf->Pin == PWR_WAKEUP_PIN_0) || (conf->Pin == PWR_WAKEUP_PIN_1) || (conf->Pin == PWR_WAKEUP_PIN_2) ) + { + PWRx->CR4 |= PWR_CR4_FILTE0(conf->TrgIn); + PWRx->CR4 |= PWR_CR4_FILTCNT0(conf->CountValue); + PWRx->CR4 |= PWR_CR4_FILTF0(1u); + } + else + { + PWRx->CR4 |= PWR_CR4_FILTF0(0u); + } + } + else + { + PWRx->CR4 |= PWR_CR4_FILTF0(0u); + } +} + +void PWR_EnableStandbyWakeUpPinFilter1(PWR_Type * PWRx, PWR_StandbyWakeUpPinFilter1Conf_Type * conf) +{ + if (NULL != conf) + { + if (conf->Pin == PWR_WAKEUP_PIN_3) + { + PWRx->CR5 |= PWR_CR5_FILTSEL1(0u); + } + if (conf->Pin == PWR_WAKEUP_PIN_4) + { + PWRx->CR5 |= PWR_CR5_FILTSEL1(1u); + } + if (conf->Pin == PWR_WAKEUP_PIN_5) + { + PWRx->CR5 |= PWR_CR5_FILTSEL1(2u); + } + if ( (conf->Pin == PWR_WAKEUP_PIN_3) || (conf->Pin == PWR_WAKEUP_PIN_4) || (conf->Pin == PWR_WAKEUP_PIN_5) ) + { + PWRx->CR5 |= PWR_CR5_FILTE1(conf->TrgIn); + PWRx->CR5 |= PWR_CR5_FILTCNT1(conf->CountValue); + PWRx->CR5 |= PWR_CR5_FILTF1(1u); + } + else + { + PWRx->CR5 |= PWR_CR5_FILTF1(0u); + } + } + else + { + PWRx->CR5 |= PWR_CR5_FILTF1(0u); + } +} + +void PWR_EnterStandbyMode(PWR_Type * PWRx, PWR_StandbyWakeUpDelay_Type delay) +{ + PWRx->CR1 |= PWR_CR1_PDDS_MASK; + PWRx->SCR |= ( PWR_WAKEUP_PIN_0 + | PWR_WAKEUP_PIN_1 + | PWR_WAKEUP_PIN_2 + | PWR_WAKEUP_PIN_3 + | PWR_WAKEUP_PIN_4 + | PWR_WAKEUP_PIN_5 + ); + PWRx->CR6 |= PWR_CR6_STDBYFSWK(delay); +} + +uint32_t PWR_GetStatus(PWR_Type * PWRx) +{ + uint32_t flags = 0u; + + if ( 0u != (PWR_CR1_LPR_MASK & PWRx->CR1) ) + { + flags |= PWR_STATUS_LOWPOWERRUN; + } + if ( 0u != (PWR_CSR_SBF_MASK & PWRx->CSR) ) + { + flags |= PWR_STATUS_STANDBYRESET; + } + return flags; +} + +void PWR_ClearStatus(PWR_Type * PWRx, uint32_t flags) +{ + if ( 0u != (PWR_STATUS_LOWPOWERRUN & flags) ) + { + PWRx->CR1 &= ~PWR_CR1_LPR_MASK; + } + if ( 0u != (PWR_STATUS_STANDBYRESET & flags) ) + { + PWRx->CR1 |= PWR_CR1_CSBF_MASK; + } +} + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_pwr.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_pwr.h new file mode 100644 index 000000000..8516add62 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_pwr.h @@ -0,0 +1,174 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_PWR_H__ +#define __HAL_PWR_H__ + +#include "hal_common.h" + +/*! + * @addtogroup PWR + * @{ + */ + +/*! + * @brief PWR driver version number. + */ +#define PWR_DRIVER_VERSION 0u /*!< PWR_0. */ + +/*! + * @addtogroup PWR_WAKEUP_PIN + * @{ + */ +#define PWR_WAKEUP_PIN_0 (1u << 0u) /*!< Wake up pin 0 selected. */ +#define PWR_WAKEUP_PIN_1 (1u << 1u) /*!< Wake up pin 1 selected. */ +#define PWR_WAKEUP_PIN_2 (1u << 2u) /*!< Wake up pin 2 selected. */ +#define PWR_WAKEUP_PIN_3 (1u << 3u) /*!< Wake up pin 3 selected. */ +#define PWR_WAKEUP_PIN_4 (1u << 4u) /*!< Wake up pin 4 selected. */ +#define PWR_WAKEUP_PIN_5 (1u << 5u) /*!< Wake up pin 5 selected. */ +/*! + * @} + */ + +/*! + * @addtogroup PWR_STATUS + * @{ + */ +#define PWR_STATUS_LOWPOWERRUN (1u << 0u) /*!< Low power run mode flag. */ +#define PWR_STATUS_STANDBYRESET (1u << 1u) /*!< Standby reset flag. */ +/*! + * @} + */ + +/*! + * @brief PWR standby wake up delay type. + */ +typedef enum +{ + PWR_StandbyWakeUpDelay_2 = 1u, /*!< 2 LSI period selected. */ + PWR_StandbyWakeUpDelay_3 = 2u, /*!< 3 LSI period selected. */ + PWR_StandbyWakeUpDelay_4 = 3u, /*!< 4 LSI period selected. */ + PWR_StandbyWakeUpDelay_5 = 4u, /*!< 5 LSI period selected. */ + PWR_StandbyWakeUpDelay_6 = 5u, /*!< 6 LSI period selected. */ + PWR_StandbyWakeUpDelay_7 = 6u, /*!< 7 LSI period selected. */ + PWR_StandbyWakeUpDelay_8 = 7u, /*!< 8 LSI period selected. */ +} PWR_StandbyWakeUpDelay_Type; + +/*! + * @brief PWR standby mode wake up pin trigger input type. + */ +typedef enum +{ + PWR_StandbyWakeUpPinTriggerIn_RisingEdge = 0u, /*!< Enable the wake up pin rising edge trigger. */ + PWR_StandbyWakeUpPinTriggerIn_FallingEdge = 1u, /*!< Enable the wake up pin falling edge trigger. */ +} PWR_StandbyWakeUpPinTriggerIn_Type; + +/*! + * @brief This type of structure instance is used to keep setting when calling. + */ +typedef struct +{ + uint32_t Pins; /*!< Specify wake up pins. See to @ref PWR_WAKEUP_PIN. */ + PWR_StandbyWakeUpPinTriggerIn_Type TrgIn; /*!< @ref Specify wake up pin trigger input type. See to @ref PWR_StandbyWakeUpPinTriggerIn_Type. */ +} PWR_StandbyWakeUpPinConf_Type; + +/*! + * @brief This type of structure instance is used to keep setting when calling. + */ +typedef struct +{ + uint32_t Pin; /*!< Specify one of the PWR_WAKEUP_PIN_0, PWR_WAKEUP_PIN_1, and PWR_WAKEUP_PIN_2 for filtering. */ + PWR_StandbyWakeUpPinTriggerIn_Type TrgIn; /*!< @ref Specify wake up pin trigger input type. See to @ref PWR_StandbyWakeUpPinTriggerIn_Type. */ + uint32_t CountValue; /*!< Specify filter count value. */ +} PWR_StandbyWakeUpPinFilter0Conf_Type; + +/*! + * @brief This type of structure instance is used to keep setting when calling. + */ +typedef struct +{ + uint32_t Pin; /*!< Specify one of PWR_WAKEUP_PIN_3, PWR_WAKEUP_PIN_4, and PWR_WAKEUP_PIN_5 for filtering. */ + PWR_StandbyWakeUpPinTriggerIn_Type TrgIn; /*!< @ref Specify wake up pin trigger input type. See to @ref PWR_StandbyWakeUpPinTriggerIn_Type. */ + uint32_t CountValue; /*!< Specify filter count value. */ +} PWR_StandbyWakeUpPinFilter1Conf_Type; + +/*! + * @brief Enable low power run mode. + * + * @param PWRx PWR instance. + * @param enable 'true' to enable the mode, 'false' to disable the mode. + * @return None. + */ +void PWR_EnableLowPowerRunMode(PWR_Type * PWRx, bool enable); + +/*! + * @brief Enter stop mode. + * + * @param PWRx PWR instance. + * @param deep_stop 'true' to enable the deep stop mode, 'false' to disable the deep stop mode. + * @return None. + */ +void PWR_EnterStopMode(PWR_Type * PWRx, bool deep_stop); + +/*! + * @brief Enable standby mode wake up pin. + * + * @param PWRx PWR instance. + * @param init Pointer to the initialization structure. See to @ref PWR_StandbyWakeUpPinConf_Type. + * @return None. + */ +void PWR_EnableStandbyWakeUpPin(PWR_Type * PWRx, PWR_StandbyWakeUpPinConf_Type * conf); + +/*! + * @brief Enable standby mode wake up pin filter 0. + * + * @param PWRx PWR instance. + * @param init Pointer to the initialization structure. See to @ref PWR_StandbyWakeUpPinFilter0Conf_Type. + * @return None. + */ +void PWR_EnableStandbyWakeUpPinFilter0(PWR_Type * PWRx, PWR_StandbyWakeUpPinFilter0Conf_Type * conf); + +/*! + * @brief Enable standby mode wake up pin filter 1. + * + * @param PWRx PWR instance. + * @param init Pointer to the initialization structure. See to @ref PWR_StandbyWakeUpPinFilter1Conf_Type. + * @return None. + */ +void PWR_EnableStandbyWakeUpPinFilter1(PWR_Type * PWRx, PWR_StandbyWakeUpPinFilter1Conf_Type * conf); + +/*! + * @brief Enter standby mode. + * + * @param PWRx PWR instance. + * @param Delay Specify standby mode wake up delay value. See to @ref PWR_StandbyWakeUpDelay_Type. + * @return None. + */ +void PWR_EnterStandbyMode(PWR_Type * PWRx, PWR_StandbyWakeUpDelay_Type delay); + +/*! + * @brief Get the current status flags of PWR module. + * + * @param PWRx PWR instance. + * @return PWR status flags. See to @ref PWR_STATUS. + */ +uint32_t PWR_GetStatus(PWR_Type * PWRx); + +/*! + * @brief Clear PWR status flags. + * + * @param PWRx PWR instance. + * @param flags PWR status flags. See to @ref PWR_STATUS. + * @return None. + */ +void PWR_ClearStatus(PWR_Type * PWRx, uint32_t flags); + +/*! + *@} + */ + +#endif /* __HAL_PWR_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_qspi.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_qspi.c new file mode 100644 index 000000000..4c07a2154 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_qspi.c @@ -0,0 +1,222 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_qspi.h" + +void QSPI_Init(QSPI_Type * QSPIx, QSPI_Init_Type * init) +{ + if (NULL == init /* if the init pointer is null, quit init. */ + || init->SckDiv < 2u || init->SckDiv > 9u || init->SckDiv % 2u != 0u /* The available value must be even & the range would be 2 ~ 128. */ + || init->CsHighLevelCycles < 2u || init->CsHighLevelCycles > 9u) /* available range would be 2 ~ 9. */ + { + return; + } + + QSPIx->CR = (QSPIx->CR & ~(QSPI_CR_SCKDIV_MASK | QSPI_CR_CSRHT_MASK | QSPI_CR_SCKMODE_MASK | QSPI_CR_OPMODE_MASK) ) + | QSPI_CR_SCKDIV(init->SckDiv / 2u - 1u) /* set the baudrate. */ + | QSPI_CR_CSRHT(init->CsHighLevelCycles - 2u) /* set the CS high level cycle. */ + | QSPI_CR_SCKMODE(init->SpiMode) /* set the SPI mode. */ + | QSPI_CR_OPMODE(QSPI_OpMode_Idle); /* set the operation mode, idle by default. */ +} + +void QSPI_EnableDirectRead(QSPI_Type * QSPIx, QSPI_DirectXferConf_Type * conf) +{ + if (NULL == conf) /* disabled. */ + { + QSPIx->CR = (QSPIx->CR & ~QSPI_CR_OPMODE_MASK) | QSPI_CR_OPMODE(QSPI_OpMode_Idle); + return; + } + + /* calculate the optimal value of rxdly, the value is SCK / 4. */ + uint32_t rxdly = ( ( (QSPIx->CR & QSPI_CR_SCKDIV_MASK) >> QSPI_CR_SCKDIV_SHIFT) + 1u ) >> 1u; + if (rxdly > 3) + { + rxdly = 3; /* available range would be 0 ~ 3. */ + } + + QSPIx->DMCR = (QSPIx->DMCR & ~(QSPI_DMCR_RXDLY_MASK | QSPI_DMCR_NUMDC_MASK | QSPI_DMCR_DMODE_MASK + | QSPI_DMCR_ABMODE_MASK | QSPI_DMCR_ABSIZE_MASK | QSPI_DMCR_ADSIZE_MASK + | QSPI_DMCR_ADMODE_MASK | QSPI_DMCR_IMODE_MASK | QSPI_DMCR_INST_MASK) ) + | QSPI_DMCR_RXDLY(rxdly) + | QSPI_DMCR_NUMDC(conf->DummyCycles) + | QSPI_DMCR_DMODE(conf->DataBusWidth) + | QSPI_DMCR_ABSIZE(conf->AltWordWidth) + | QSPI_DMCR_ABMODE(conf->AltBusWidth) + | QSPI_DMCR_ADSIZE(conf->AddrWordWidth) + | QSPI_DMCR_ADMODE(conf->AddrBusWidth) + | QSPI_DMCR_IMODE(conf->CmdBusWidth) + | QSPI_DMCR_INST(conf->CmdValue); + + QSPIx->DABR = QSPI_DABR_DALT(conf->AltValue); + + QSPIx->CR = ( QSPIx->CR & ~( QSPI_CR_OPMODE_MASK) ) | QSPI_CR_OPMODE(QSPI_OpMode_Direct); +} + +uint8_t QSPI_GetDirectData8b(QSPI_Type * QSPIx, uint32_t offset) +{ + (void)QSPIx; + return (*( (uint8_t *)(QSPI_M_BASE + offset) ) ); +} + +uint16_t QSPI_GetDirectData16b(QSPI_Type * QSPIx, uint32_t offset) +{ + (void)QSPIx; + return (*( (uint16_t *)(QSPI_M_BASE + offset) ) ); +} + +uint32_t QSPI_GetDirectData32b(QSPI_Type * QSPIx, uint32_t offset) +{ + (void)QSPIx; + return (*( (uint32_t *)(QSPI_M_BASE + offset) ) ); +} + +void QSPI_SetIndirectReadConf(QSPI_Type * QSPIx, QSPI_IndirectXferConf_Type * conf) +{ + if(NULL == conf) + { + return; + } + + /* calculate the optimal value of rxdly, the value is SCK / 4. */ + uint32_t rxdly = ( ( (QSPIx->CR & QSPI_CR_SCKDIV_MASK) >> QSPI_CR_SCKDIV_SHIFT) + 1u ) >> 1u; + if (rxdly > 3) + { + rxdly = 3; /* available range would be 0 ~ 3. */ + } + + QSPIx->IMCR = ( QSPIx->IMCR & ~(QSPI_IMCR_IDMODE_MASK | QSPI_IMCR_NUMDC_MASK | QSPI_IMCR_DSIZE_MASK + | QSPI_IMCR_DMODE_MASK | QSPI_IMCR_ABSIZE_MASK | QSPI_IMCR_ABMODE_MASK + | QSPI_IMCR_ADSIZE_MASK | QSPI_IMCR_ADMODE_MASK | QSPI_IMCR_IMODE_MASK + | QSPI_IMCR_INST_MASK | QSPI_IMCR_RXDLY_MASK) ) + | QSPI_IMCR_RXDLY(rxdly) + | QSPI_IMCR_IDMODE(0u) /* read. */ + | QSPI_IMCR_NUMDC(conf->DummyCycles) + | QSPI_IMCR_DSIZE(conf->DataWordWidth) + | QSPI_IMCR_DMODE(conf->DataBusWidth) + | QSPI_IMCR_ABSIZE(conf->AltWordWidth) + | QSPI_IMCR_ABMODE(conf->AltBusWidth) + | QSPI_IMCR_ADSIZE(conf->AddrWordWidth) + | QSPI_IMCR_ADMODE(conf->AddrBusWidth) + | QSPI_IMCR_IMODE(conf->CmdBusWidth) + | QSPI_IMCR_INST(conf->CmdValue); + QSPIx->IABR = QSPI_IABR_IALT(conf->AltValue); + QSPIx->IADR = QSPI_IADR_IADDR(conf->AddrValue); + QSPIx->IWCR = QSPI_IWCR_IWCNT(0u); /* wait 7 AHB_CLK to quit inrect mode. */ + QSPIx->IDLR = QSPI_IDLR_IDLEN(conf->DataLen - 1u); + QSPIx->CR = (QSPIx->CR & ~QSPI_CR_OPMODE_MASK) | QSPI_CR_OPMODE(QSPI_OpMode_Indirect); +} + +uint32_t QSPI_GetIndirectData(QSPI_Type * QSPIx) +{ + return QSPIx->IDFR; +} + +void QSPI_SetIndirectWriteConf(QSPI_Type * QSPIx, QSPI_IndirectXferConf_Type * conf) +{ + if(NULL == conf) + { + return; + } + + /* calculate the optimal value of rxdly, the value is SCK / 4. */ + uint32_t rxdly = ( ( (QSPIx->CR & QSPI_CR_SCKDIV_MASK) >> QSPI_CR_SCKDIV_SHIFT) + 1u ) >> 1u; + if (rxdly > 3) + { + rxdly = 3; /* available range would be 0 ~ 3. */ + } + + QSPIx->IMCR = ( QSPIx->IMCR & ~(QSPI_IMCR_IDMODE_MASK | QSPI_IMCR_NUMDC_MASK | QSPI_IMCR_DSIZE_MASK + | QSPI_IMCR_DMODE_MASK | QSPI_IMCR_ABSIZE_MASK | QSPI_IMCR_ABMODE_MASK + | QSPI_IMCR_ADSIZE_MASK | QSPI_IMCR_ADMODE_MASK | QSPI_IMCR_IMODE_MASK + | QSPI_IMCR_INST_MASK | QSPI_IMCR_RXDLY_MASK) ) + | QSPI_IMCR_RXDLY(rxdly) + | QSPI_IMCR_IDMODE(1u) /* write. */ + | QSPI_IMCR_NUMDC(conf->DummyCycles) + | QSPI_IMCR_DSIZE(conf->DataWordWidth) + | QSPI_IMCR_DMODE(conf->DataBusWidth) + | QSPI_IMCR_ABSIZE(conf->AltWordWidth) + | QSPI_IMCR_ABMODE(conf->AltBusWidth) + | QSPI_IMCR_ADSIZE(conf->AddrWordWidth) + | QSPI_IMCR_ADMODE(conf->AddrBusWidth) + | QSPI_IMCR_IMODE(conf->CmdBusWidth) + | QSPI_IMCR_INST(conf->CmdValue); + QSPIx->IABR = QSPI_IABR_IALT(conf->AltValue); + QSPIx->IADR = QSPI_IADR_IADDR(conf->AddrValue); + QSPIx->IWCR = QSPI_IWCR_IWCNT(0u); /* wait 7 AHB_CLK to quit inrect mode. */ + QSPIx->IDLR = QSPI_IDLR_IDLEN(conf->DataLen - 1u); + QSPIx->CR = (QSPIx->CR & ~QSPI_CR_OPMODE_MASK) | QSPI_CR_OPMODE(QSPI_OpMode_Indirect); +} + +void QSPI_PutIndirectData(QSPI_Type * QSPIx, uint32_t value) +{ + QSPIx->IDFR = value; +} + +void QSPI_EnableXIP(QSPI_Type * QSPIx, bool enable) +{ + if (true == enable) + { + QSPIx->CR = QSPIx->CR | QSPI_CR_XIPMODE_MASK; + } + else + { + QSPIx->CR = QSPIx->CR & ~QSPI_CR_XIPMODE_MASK; + } +} + +void QSPI_SetIndirectAutoXIP(QSPI_Type * QSPIx, bool enable) +{ + if (true == enable) + { + QSPIx->IMCR |= QSPI_IMCR_XIPIM_MASK; + } + else + { + QSPIx->IMCR &= ~QSPI_IMCR_XIPIM_MASK; + } +} + +uint32_t QSPI_GetStatus(QSPI_Type * QSPIx) +{ + return QSPIx->SR; +} + +void QSPI_ClearStatus(QSPI_Type * QSPIx, uint32_t status) +{ + QSPIx->SR &= status; /* write 1 to clear status. */ +} + +uint32_t QSPI_GetOpMode(QSPI_Type * QSPIx) +{ + return (QSPIx->SR & QSPI_SR_OPCRCF_MASK) >> QSPI_SR_OPCRCF_SHIFT; +} + +void QSPI_EnableInterrupts(QSPI_Type * QSPIx, uint32_t interrupts, bool enable) +{ + if(true == enable) + { + QSPIx->IDER |= interrupts; + } + else + { + QSPIx->IDER &= ~interrupts; + } +} + +void QSPI_EnableDMARequest(QSPI_Type * QSPIx, uint32_t request, bool enable) +{ + if(true == enable) + { + QSPIx->IDER |= request; + } + else + { + QSPIx->IDER &= ~request; + } +} + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_qspi.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_qspi.h new file mode 100644 index 000000000..25b090e9b --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_qspi.h @@ -0,0 +1,319 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_QSPI_H__ +#define __HAL_QSPI_H__ + +#include "hal_common.h" + +/*! + * @addtogroup QSPI + * @{ + */ + +/*! + * @brief QSPI driver version number. + */ +#define QSPI_DRIVER_VERSION 0u /*!< QSPI_0. */ + +/*! + * @addtogroup QSPI_STATUS + * @{ + */ +#define QSPI_STATUS_XIP_ENABLE QSPI_SR_XIPST_MASK /*!< Status flag when QSPI XIP enabled. */ +#define QSPI_STATUS_FIFO_FULL QSPI_SR_FULL_MASK /*!< Status flag when QSPI FIFO full. */ +#define QSPI_STATUS_FIFO_EMPTY QSPI_SR_EMPTY_MASK /*!< Status flag when QSPI FIFO empty. */ +#define QSPI_STATUS_BUSY QSPI_SR_BUSY_MASK /*!< Status flag when QSPI xfer data. */ +#define QSPI_STATUS_XFER_DONE QSPI_SR_TCF_MASK /*!< Status flag when QSPI xfer done. */ +#define QSPI_STATUS_OPMODE_CHANGE_DONE QSPI_SR_OPCRCF_MASK /*!< Status flag when QSPI change the operation mode done. */ +/*! + * @} + */ + +/*! + * @addtogroup QSPI_INT + * @{ + */ +#define QSPI_INT_FIFO_FULL QSPI_IDER_FULLINTEN_MASK /*!< Interrupt enable when QSPI FIFO is full. */ +#define QSPI_INT_FIFO_EMPTY QSPI_IDER_EMPTYINTEN_MASK /*!< Interrupt enable when QSPI FIFO is empty. */ +#define QSPI_INT_XFER_DONE QSPI_IDER_TCFINTEN_MASK /*!< Interrupt enable when QSPI xfer done. */ +/*! + * @} + */ + +/*! + * @addtogroup QSPI_DMA + * @{ + */ +#define QSPI_DMA_FIFO_FULL QSPI_IDER_FULLDMAEN_MASK /*!< DMA request enable when QSPI FIFO is full. */ +#define QSPI_DMA_FIFO_EMPTY QSPI_IDER_EMPTYDMAEN_MASK /*!< DMA request enable when QSPI FIFO is empty. */ +#define QSPI_DMA_XFER_DONE QSPI_IDER_TCFDMAEN_MASK /*!< DMA request enable when QSPI xfer done. */ +/*! + * @} + */ + +/*! + * @brief SPI mode, set the clock polarity(CPOL) & clock phase(CPHA). + */ +typedef enum +{ + QSPI_SpiMode_0 = 0x00, /*!< SPI mode 0, CPOL = 0, CPHA = 0. */ + QSPI_SpiMode_3 = 0x01, /*!< SPI mode 0, CPOL = 1, CPHA = 1. */ +} QSPI_SpiMode_Type; + +/*! + * @brief Operation mode, defines the QSPI operation status. + */ +typedef enum +{ + QSPI_OpMode_Direct = 0x00, /*!< Direct mode, read data by mapped addr. */ + QSPI_OpMode_Indirect = 0x02, /*!< Indirect mode, read & write data by QSPI peripheral. */ + QSPI_OpMode_Idle = 0x03, /*!< Idle mode, cannot read data by direct mode. */ +} QSPI_OpMode_Type; + +/*! + * @brief Word width, defines the word width when xfer content. + */ +typedef enum +{ + QSPI_WordWidth_8b = 0x00, /*!< The word wide is 8 bit. */ + QSPI_WordWidth_16b = 0x01, /*!< The word wide is 16 bit. */ + QSPI_WordWidth_24b = 0x02, /*!< The word wide is 24 bit. */ + QSPI_WordWidth_32b = 0x03, /*!< The word wide is 32 bit. */ +} QSPI_WordWidth_Type; + +/*! + * @brief Bus width or line mode, defines the bus width when xfer content. + */ +typedef enum +{ + QSPI_BusWidth_None = 0x00, /*!< No more content in this phase. */ + QSPI_BusWidth_1b = 0x01, /*!< Xfer content by signal line. (using MOSI or MISO xfer content). */ + QSPI_BusWidth_2b = 0x02, /*!< Xfer content by dual lines. (using DA0 & DA1 xfer content). */ + QSPI_BusWidth_4b = 0x03, /*!< Xfer content by quad lines. (using DA0, DA1, DA2 & DA3 xfer content). */ +} QSPI_BusWidth_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref QSPI_Init() to initialize the QSPI module. + */ +typedef struct +{ + uint32_t SckDiv; /*!< Specify the QSPI SCK Prescaler. + The SCK output clock = AHB_CLK / SckDiv. + The available value must be even & the range would be 2 ~ 128. */ + uint32_t CsHighLevelCycles; /*!< Specify the QSPI CS High Level Cycles. + The minimum duration for CS output high level (invalid level) is AHB_CLK * CsHighLevelCycles. + The available range would be 2 ~ 9. */ + QSPI_SpiMode_Type SpiMode; /*!< Specify the SPI mode. */ +} QSPI_Init_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref QSPI_EnableDirectRead() to enable direct mode. + */ +typedef struct +{ + /* instruction phase. */ + QSPI_BusWidth_Type CmdBusWidth; /*!< Specify the QSPI instruction bus width. */ + uint32_t CmdValue; /*!< Specify the QSPI instruction value. */ + + /* addr phase. */ + /* the addr value will be determined when accessing QSPI device by direct operation mode. */ + QSPI_BusWidth_Type AddrBusWidth; /*!< Specify the QSPI addr bus width. */ + QSPI_WordWidth_Type AddrWordWidth; /*!< Specify the QSPI addr bit width. */ + + /* alt phase. */ + QSPI_BusWidth_Type AltBusWidth; /*!< Specify the QSPI alt bus width. */ + QSPI_WordWidth_Type AltWordWidth; /*!< Specify the QSPI alt bit width. */ + uint32_t AltValue; /*!< Specify the QSPI alt value. */ + + /* dummy phase. */ + uint32_t DummyCycles; /*!< Specify the QSPI dummy cycles, available range would be 0 ~ 31. */ + + /* data phase. */ + QSPI_BusWidth_Type DataBusWidth; /*!< Specify the QSPI data bus width. */ +} QSPI_DirectXferConf_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref QSPI_SetIndirectReadConf() or @ref QSPI_SetIndirectWriteConf() to set xfer configure. + */ +typedef struct +{ + /* instruction phase. */ + QSPI_BusWidth_Type CmdBusWidth; /*!< Specify the QSPI instruction bus width. */ + uint32_t CmdValue; /*!< Specify the QSPI instruction value. */ + + /* addr phase. */ + QSPI_BusWidth_Type AddrBusWidth; /*!< Specify the QSPI addr bus width. */ + QSPI_WordWidth_Type AddrWordWidth; /*!< Specify the QSPI addr bit width. */ + uint32_t AddrValue; /*!< Specify the QSPI addr value. */ + + /* alt phase. */ + QSPI_BusWidth_Type AltBusWidth; /*!< Specify the QSPI alt bus width. */ + QSPI_WordWidth_Type AltWordWidth; /*!< Specify the QSPI alt bit width. */ + uint32_t AltValue; /*!< Specify the QSPI alt value. */ + + /* dummy phase. */ + uint32_t DummyCycles; /*!< Specify the QSPI dummy cycles, available range would be 0 ~ 31. */ + + /* data phase. */ + QSPI_BusWidth_Type DataBusWidth; /*!< Specify the QSPI data bus width. */ + QSPI_WordWidth_Type DataWordWidth; /*!< Specify the QSPI data bit width. */ + uint32_t DataLen; /*!< Specify the QSPI data length. */ +} QSPI_IndirectXferConf_Type; + +/*! + * @brief Initialize the QSPI module. + * + * @param QSPIx QSPI instance. + * @param init Pointer to the initialization structure. See to @ref QSPI_Init_Type. + * @return None. + */ +void QSPI_Init(QSPI_Type * QSPIx, QSPI_Init_Type * init); + +/*! + * @brief Enable the QSPI direct read configure. + * + * @param QSPIx QSPI instance. + * @param conf Pointer to the initialization structure. See to @ref QSPI_DirectXferConf_Type. + * @return None. + */ +void QSPI_EnableDirectRead(QSPI_Type * QSPIx, QSPI_DirectXferConf_Type * conf); + +/*! + * @brief Get the data from mapped addr as 8 bit. + * + * @param QSPIx QSPI instance. + * @param offset offset of data in QSPI Device. + * @return The data value received from the mapped addr. + */ +uint8_t QSPI_GetDirectData8b(QSPI_Type * QSPIx, uint32_t offset); + +/*! + * @brief Get the data from mapped addr as 16 bit. + * + * @param QSPIx QSPI instance. + * @param offset offset of data in QSPI Device. + * @return The data value received from the mapped addr. + */ +uint16_t QSPI_GetDirectData16b(QSPI_Type * QSPIx, uint32_t addr); + +/*! + * @brief Get the data from mapped addr as 32 bit. + * + * @param QSPIx QSPI instance. + * @param offset offset of data in QSPI Device. + * @return The data value received from the mapped addr. + */ +uint32_t QSPI_GetDirectData32b(QSPI_Type * QSPIx, uint32_t addr); + +/*! + * @brief Set the QSPI indirect read configure. + * + * After configuration, the indirect read process will start. + * + * @param QSPIx QSPI instance. + * @param conf Pointer to the config structure. See to @ref QSPI_IndirectXferConf_Type. + * @return None. + */ +void QSPI_SetIndirectReadConf(QSPI_Type * QSPIx, QSPI_IndirectXferConf_Type * conf); + +/*! + * @brief Get the data from FIFO in indirect mode of the QSPI module. + * + * @param QSPIx QSPI instance. + * @return The data value received from the FIFO. + */ +uint32_t QSPI_GetIndirectData(QSPI_Type * QSPIx); + +/*! + * @brief Set the QSPI indirect write configure. + * + * After configuration, the indirect write process will start. + * + * @param QSPIx QSPI instance. + * @param conf Pointer to the config structure. See to @ref QSPI_IndirectXferConf_Type. + * @return None. + */ +void QSPI_SetIndirectWriteConf(QSPI_Type * QSPIx, QSPI_IndirectXferConf_Type * conf); + +/*! + * @brief Put the data into FIFO of the QSPI module. + * + * @param QSPIx QSPI instance. + * @param value Data value to be send through the FIFO. + * @return None. + */ +void QSPI_PutIndirectData(QSPI_Type * QSPIx, uint32_t value); + +/*! + * @brief Enable the QSPI XIP mode. + * + * @param QSPIx QSPI instance. + * @param enable 'true' to enable XIP, 'false' to disable XIP. + * @return None. + */ +void QSPI_EnableXIP(QSPI_Type * QSPIx, bool enable); + +/*! + * @brief Set the QSPI enbale XIP mode after quit indirect mode. + * + * @param QSPIx QSPI instance. + * @param enable 'true' to enable XIP, 'false' to disable XIP. + * @return None. + */ +void QSPI_SetIndirectAutoXIP(QSPI_Type * QSPIx, bool enable); + +/*! + * @brief Get the current status flags of the QSPI module. + * + * @param QSPIx QSPI instance. + * @return Status flags. See to @ref QSPI_STATUS. + */ +uint32_t QSPI_GetStatus(QSPI_Type * QSPIx); + +/*! + * @brief Clear the interrupts status flags of the QSPI module. + * + * @param QSPIx QSPI instance. + * @param status The mask codes of the indicated status flags to be cleared. + * @return Status flags. See to @ref QSPI_INT. + */ +void QSPI_ClearStatus(QSPI_Type * QSPIx, uint32_t status); + +/*! + * @brief Gets the current operating mode. + * + * @param QSPIx QSPI instance. + * @return Operation, See to @ref QSPI_OpMode_Type. + */ +uint32_t QSPI_GetOpMode(QSPI_Type * QSPIx); + +/*! + * @brief Enable interrupts of the QSPI module. + * + * @param QSPIx QSPI instance. + * @param interrupts Interrupt code masks. See to @ref QSPI_INT. + * @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts. + * @return None. + */ +void QSPI_EnableInterrupts(QSPI_Type * QSPIx, uint32_t interrupts, bool enable); + +/*! + * @brief Enable DMA request of the QSPI module. + * + * @param QSPIx QSPI instance. + * @param dmas dma request code masks. See to @ref QSPI_DMA. + * @param enable 'true' to enable the indicated request, 'false' to disable the indicated request. + * @return None. + */ +void QSPI_EnableDMA(QSPI_Type * QSPIx, uint32_t dmas, bool enable); + +/*! + *@} + */ + +#endif /* __HAL_QSPI_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_rcc.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_rcc.c new file mode 100644 index 000000000..1711fabf6 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_rcc.c @@ -0,0 +1,159 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#include "hal_common.h" +#include "hal_rcc.h" + +void RCC_EnableAHB1Periphs(uint32_t ahb1_periphs, bool enable) +{ + (enable) ? (RCC->AHB1ENR |= ahb1_periphs) : (RCC->AHB1ENR &= ~ahb1_periphs); +} + +void RCC_EnableAPB1Periphs(uint32_t apb1_periphs, bool enable) +{ + (enable) ? (RCC->APB1ENR |= apb1_periphs) : (RCC->APB1ENR &= ~apb1_periphs); +} + +void RCC_EnableAPB2Periphs(uint32_t apb2_periphs, bool enable) +{ + (enable) ? (RCC->APB2ENR |= apb2_periphs) : (RCC->APB2ENR &= ~apb2_periphs); +} + +void RCC_ResetAHB1Periphs(uint32_t ahb1_periphs) +{ + RCC->AHB1RSTR |= ahb1_periphs; + RCC->AHB1RSTR &= ~ahb1_periphs; +} + +void RCC_ResetAPB1Periphs(uint32_t apb1_periphs) +{ + RCC->APB1RSTR |= apb1_periphs; + RCC->APB1RSTR &= ~apb1_periphs; +} + +void RCC_ResetAPB2Periphs(uint32_t apb2_periphs) +{ + RCC->APB2RSTR |= apb2_periphs; + RCC->APB2RSTR &= ~apb2_periphs; +} + +void RCC_SetMCOConf(RCC_MCO_Type source) +{ + RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_MCO_MASK) | RCC_CFGR_MCO(source); +} + +void RCC_SetADCClockDiv(ADC_Type * ADCx, uint32_t div) +{ + if (ADCx == ADC1) + { + RCC->ADC1CFGR = (RCC->ADC1CFGR & ~RCC_ADC1CFGR_PRE_MASK) | RCC_ADC1CFGR_PRE(div); + } + else if (ADCx == ADC2) + { + RCC->ADC2CFGR = (RCC->ADC2CFGR & ~RCC_ADC2CFGR_PRE_MASK) | RCC_ADC2CFGR_PRE(div); + } +} + +void RCC_SetADCCalibClockDiv(ADC_Type * ADCx, uint32_t div) +{ + if (ADCx == ADC1) + { + RCC->ADC1CFGR = (RCC->ADC1CFGR & ~RCC_ADC1CFGR_PRECAL_MASK) | RCC_ADC1CFGR_PRECAL(div); + } + else if (ADCx == ADC2) + { + RCC->ADC2CFGR = (RCC->ADC2CFGR & ~RCC_ADC2CFGR_PRECAL_MASK) | RCC_ADC1CFGR_PRECAL(div); + } +} + +void RCC_SetDACClockDiv(uint32_t div) +{ + RCC->DACCFGR = (RCC->DACCFGR & ~RCC_DACCFGR_PRE_MASK) | RCC_DACCFGR_PRE(div); +} + +void RCC_EnableFSMCSyncMode(bool enable) +{ + (enable) ? (RCC->FSMCCFGR |= RCC_FSMCCFGR_FSMCSYNCEN_MASK) : (RCC->FSMCCFGR &= ~RCC_FSMCCFGR_FSMCSYNCEN_MASK); +} + +void RCC_SetFSMCClockDiv(uint32_t div) +{ + RCC->FSMCCFGR = (RCC->FSMCCFGR & ~RCC_FSMCCFGR_FSMCPRE_MASK) | RCC_FSMCCFGR_FSMCPRE(div); +} + +void RCC_SetTPIUClockDiv(uint32_t div) +{ + RCC->TPIUCFGR = (RCC->TPIUCFGR & ~RCC_TPIUCFGR_PRE_MASK) | RCC_TPIUCFGR_PRE(div); +} + +void RCC_EanbleBKPWriteProtect(bool enable) +{ + (enable) ? (RCC->BDCR &= ~RCC_BDCR_DBP_MASK) : (RCC->BDCR |= RCC_BDCR_DBP_MASK); +} + +void RCC_EanbleBKPReset(bool enable) +{ + (enable) ? (RCC->BDCR |= RCC_BDCR_BDRST_MASK) : (RCC->BDCR &= ~RCC_BDCR_BDRST_MASK); +} + +void RCC_EanbleRTCClock(bool enable) +{ + (enable) ? (RCC->BDCR |= RCC_BDCR_RTCEN_MASK) : (RCC->BDCR &= ~RCC_BDCR_RTCEN_MASK); +} + +void RCC_SetRTCClockSource(uint32_t source) +{ + RCC->BDCR |= RCC_BDCR_RTCSEL(source); +} + +void RCC_EanbleLSEBypassMode(bool enable) +{ + (enable) ? (RCC->BDCR |= RCC_BDCR_LSEBYP_MASK) : (RCC->BDCR &= ~RCC_BDCR_LSEBYP_MASK); +} + +uint32_t GetLSEReadyStatus(void) +{ + return (RCC->BDCR &= RCC_BDCR_LSERDY_MASK); +} + +void RCC_EanbleLSEClock(bool enable) +{ + (enable) ? (RCC->BDCR |= RCC_BDCR_LSEON_MASK) : (RCC->BDCR &= ~RCC_BDCR_LSEON_MASK); +} + +uint32_t GetResetStatus(ResetStatus_Type status ) +{ + return (RCC->CSR &= status); +} + +void ClearResetStatus(void) +{ + RCC->CSR = RCC_CSR_RMVF_MASK; +} + +void RCC_EanbleCPULock(bool enable) +{ + (enable) ? (RCC->CSR |= RCC_CSR_LOCKUPEN_MASK) : (RCC->BDCR &= ~RCC_CSR_LOCKUPEN_MASK); +} + +void RCC_EanblePVDReset(bool enable) +{ + (enable) ? (RCC->CSR |= RCC_CSR_PVDRSTEN_MASK) : (RCC->BDCR &= ~RCC_CSR_PVDRSTEN_MASK); +} + +void RCC_EanbleLSIClockOutput(bool enable) +{ + (enable) ? (RCC->CSR |= RCC_CSR_LSIOE_MASK) : (RCC->BDCR &= ~RCC_CSR_LSIOE_MASK); +} + +void RCC_EanbleLSIClock(bool enable) +{ + (enable) ? (RCC->CSR |= RCC_CSR_LSION_MASK) : (RCC->BDCR &= ~RCC_CSR_LSION_MASK); +} + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_rcc.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_rcc.h new file mode 100644 index 000000000..1e5790bbb --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_rcc.h @@ -0,0 +1,345 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef __HAL_RCC_H__ +#define __HAL_RCC_H__ + +#include "hal_common.h" + +/*! + * @addtogroup RCC + * @{ + */ + +/*! + * @addtogroup RCC_AHB1_PERIPH + * @{ + */ +#define RCC_AHB1_PERIPH_GPIOA (1u << 0u) /*!< AHB1 peripheral GPIOA clock 0 bit. */ +#define RCC_AHB1_PERIPH_GPIOB (1u << 1u) /*!< AHB1 peripheral GPIOB clock 1 bit. */ +#define RCC_AHB1_PERIPH_GPIOC (1u << 2u) /*!< AHB1 peripheral GPIOC clock 2 bit. */ +#define RCC_AHB1_PERIPH_GPIOD (1u << 3u) /*!< AHB1 peripheral GPIOD clock 3 bit. */ +#define RCC_AHB1_PERIPH_GPIOE (1u << 4u) /*!< AHB1 peripheral GPIOE clock 4 bit. */ +#define RCC_AHB1_PERIPH_GPIOF (1u << 5u) /*!< AHB1 peripheral GPIOF clock 5 bit. */ +#define RCC_AHB1_PERIPH_GPIOG (1u << 6u) /*!< AHB1 peripheral GPIOG clock 6 bit. */ +#define RCC_AHB1_PERIPH_GPIOH (1u << 7u) /*!< AHB1 peripheral GPIOH clock 7 bit. */ +#define RCC_AHB1_PERIPH_GPIOI (1u << 8u) /*!< AHB1 peripheral GPIOI clock 8 bit. */ +#define RCC_AHB1_PERIPH_CRC (1u << 12u) /*!< AHB1 peripheral CRC clock 12 bit. */ +#define RCC_AHB1_PERIPH_FLASH (1u << 13u) /*!< AHB1 peripheral FLASH clock 13 bit. */ +#define RCC_AHB1_PERIPH_SRAM (1u << 14u) /*!< AHB1 peripheral SRAM clock 14 bit. */ +#define RCC_AHB1_PERIPH_CORDIC (1u << 15u) /*!< AHB1 peripheral CORDIC clock 15 bit. */ +#define RCC_AHB1_PERIPH_ITCM (1u << 16u) /*!< AHB1 peripheral ITCM clock 16 bit. */ +#define RCC_AHB1_PERIPH_DTCM (1u << 17u) /*!< AHB1 peripheral DTCM clock 17 bit. */ +#define RCC_AHB1_PERIPH_ETHMAC (1u << 19u) /*!< AHB1 peripheral ETHMAC clock 19 bit. */ + +#define RCC_AHB1_PERIPH_DMA1 (1u << 21u) /*!< AHB1 peripheral DMA1 clock 21 bit. */ +#define RCC_AHB1_PERIPH_DMA2 (1u << 22u) /*!< AHB1 peripheral DMA2 clock 22 bit. */ +#define RCC_AHB1_PERIPH_USBOTGFS (1u << 24u) /*!< AHB1 peripheral USBOTGFS clock 24 bit. */ +#define RCC_AHB1_PERIPH_FSMC (1u << 28u) /*!< AHB1 peripheral FSMC clock 28 bit. */ +#define RCC_AHB1_PERIPH_QSPI (1u << 30u) /*!< AHB1 peripheral QSPI clock 30 bit. */ + +/*! + * @} + */ + +/*! + * @addtogroup RCC_APB1_PERIPH + * @{ + */ +#define RCC_APB1_PERIPH_TIM2 (1u << 0u) /*!< APB1 peripheral TIM2 clock 0 bit. */ +#define RCC_APB1_PERIPH_TIM3 (1u << 1u) /*!< APB1 peripheral TIM3 clock 1 bit. */ +#define RCC_APB1_PERIPH_TIM4 (1u << 2u) /*!< APB1 peripheral TIM4 clock 2 bit. */ +#define RCC_APB1_PERIPH_TIM5 (1u << 3u) /*!< APB1 peripheral TIM5 clock 3 bit. */ +#define RCC_APB1_PERIPH_TIM6 (1u << 4u) /*!< APB1 peripheral TIM6 clock 4 bit. */ +#define RCC_APB1_PERIPH_TIM7 (1u << 5u) /*!< APB1 peripheral TIM7 clock 5 bit. */ +#define RCC_APB1_PERIPH_WWDG (1u << 11u) /*!< APB1 peripheral WWDG clock 11 bit. */ +#define RCC_APB1_PERIPH_SPI2 (1u << 14u) /*!< APB1 peripheral SPI2 clock 14 bit. */ +#define RCC_APB1_PERIPH_SPI3 (1u << 15u) /*!< APB1 peripheral SPI3 clock 15 bit. */ +#define RCC_APB1_PERIPH_UART2 (1u << 17u) /*!< APB1 peripheral UART2 clock 17 bit. */ +#define RCC_APB1_PERIPH_UART3 (1u << 18u) /*!< APB1 peripheral UART3 clock 18 bit. */ +#define RCC_APB1_PERIPH_UART4 (1u << 19u) /*!< APB1 peripheral UART4 clock 19 bit. */ +#define RCC_APB1_PERIPH_UART5 (1u << 20u) /*!< APB1 peripheral UART5 clock 20 bit. */ +#define RCC_APB1_PERIPH_I2C1 (1u << 21u) /*!< APB1 peripheral I2C1 clock 21 bit. */ +#define RCC_APB1_PERIPH_I2C2 (1u << 22u) /*!< APB1 peripheral I2C2 clock 22 bit. */ +#define RCC_APB1_PERIPH_CRS (1u << 24u) /*!< APB1 peripheral CRS clock 24 bit. */ +#define RCC_APB1_PERIPH_FLEXCAN1 (1u << 25u) /*!< APB1 peripheral FLEXCAN1 clock 25 bit. */ +#define RCC_APB1_PERIPH_BKP (1u << 27u) /*!< APB1 peripheral BKP clock 27 bit. */ +#define RCC_APB1_PERIPH_PWR_DBG (1u << 28u) /*!< APB1 peripheral PWR clock 28 bit. */ +#define RCC_APB1_PERIPH_DAC (1u << 29u) /*!< APB1 peripheral DAC clock 29 bit. */ +#define RCC_APB1_PERIPH_UART7 (1u << 30u) /*!< APB1 peripheral UART7 clock 30 bit. */ + +/*! + * @} + */ + +/*! + * @addtogroup RCC_APB2_PERIPH + * @{ + */ +#define RCC_APB2_PERIPH_TIM1 (1u << 0u) /*!< APB2 peripheral TIM1 clock 0 bit. */ +#define RCC_APB2_PERIPH_TIM8 (1u << 1u) /*!< APB2 peripheral TIM8 clock 1 bit. */ +#define RCC_APB2_PERIPH_UART1 (1u << 4u) /*!< APB2 peripheral UART1 clock 4 bit. */ +#define RCC_APB2_PERIPH_UART6 (1u << 5u) /*!< APB2 peripheral UART6 clock 5 bit. */ +#define RCC_APB2_PERIPH_ADC1 (1u << 8u) /*!< APB2 peripheral ADC1 clock 8 bit. */ +#define RCC_APB2_PERIPH_ADC2 (1u << 9u) /*!< APB2 peripheral ADC2 clock 9 bit. */ +#define RCC_APB2_PERIPH_SPI1 (1u << 12u) /*!< APB2 peripheral SPI1 clock 12 bit. */ +#define RCC_APB2_PERIPH_SYSCFG (1u << 14u) /*!< APB2 peripheral SYSCFG clock 14 bit. */ +#define RCC_APB2_PERIPH_COMP (1u << 15u) /*!< APB2 peripheral COMP clock 15 bit. */ +#define RCC_APB2_PERIPH_FLEXCAN2 (1u << 24u) /*!< APB2 peripheral FLEXCAN2 clock 24 bit. */ +#define RCC_APB2_PERIPH_MINDSWITCH (1u << 28u) /*!< APB2 peripheral MINDSWITCH clock 28 bit. */ +#define RCC_APB2_PERIPH_LPTIM (1u << 30u) /*!< APB2 peripheral LPTIM clock 30 bit. */ +#define RCC_APB2_PERIPH_LPUART (1u << 31u) /*!< APB2 peripheral LPUART clock 31 bit. */ + +/*! + * @} + */ + +/*! + * @brief Define the clock source for MCO output. + */ +typedef enum +{ + RCC_MCO_NoClock = 0u, /*!< MCO NoClock 0 bits. */ + RCC_MCO_LSI = 2u, /*!< MCO LSI 2 bits. */ + RCC_MCO_LSE = 3u, /*!< MCO LSE 3 bits. */ + RCC_MCO_SYSCLK = 4u, /*!< MCO SYSCLK 4 bits. */ + RCC_MCO_HSI = 5u, /*!< MCO HSI 5 bits. */ + RCC_MCO_HSE = 6u, /*!< MCO HSE 6 bits. */ + RCC_MCO_PLL1CLK = 7u, /*!< MCO PLL1CLK 7 bits. */ + RCC_MCO_PLL2CLK = 8u, /*!< MCO PLL2CLK 8 bits. */ +} RCC_MCO_Type; + +/*! + * @brief Define the clock source for MCO output. + */ +typedef enum +{ + RCC_ResetStatus_LPWR = 31u, /*!< Low Power Reset Flag. */ + RCC_ResetStatus_WWDG = 30u, /*!< Window Watchdog Reset Flag. */ + RCC_ResetStatus_IWDG = 29u, /*!< Independent Watchdog Reset Flag. */ + RCC_ResetStatus_SW = 26u, /*!< Software Reset Flag. */ + RCC_ResetStatus_POR = 27u, /*!< POR/PDR Reset Flag. */ + RCC_ResetStatus_PIN = 26u, /*!< PIN Reset Flag. */ + RCC_ResetStatus_CPULOCKUP = 23u, /*!< CPU Lockup Reset Flag. */ + RCC_ResetStatus_PVD = 22u, /*!< PVD Reset Flag. */ + RCC_ResetStatus_LSIREADY = 22u, /*!< LSI Ready. */ +}ResetStatus_Type; + +/*! + * @brief Enable the RCC AHB1 periphs clock module. + * + * @param ahb1_periphs AHB1 Peripheral instance. + * @param enable 'true' to enable the AHB1Periphs, 'false' to disable the AHB1Periphs. + * @return None. + */ +void RCC_EnableAHB1Periphs(uint32_t ahb1_periphs, bool enable); + +/*! + * @brief Reset the RCC AHB1 periphs clock module. + * + * @param ahb1_periphs AHB1 Peripheral instance. + * @return None. + */ +void RCC_ResetAHB1Periphs(uint32_t ahb1_periphs); + +/*! + * @brief Enable the RCC APB1 periphs clock module. + * + * @param apb1_periphs APB1 Peripheral instance. + * @param enable 'true' to enable the APB1Periphs, 'false' to disable the APB1Periphs. + * @return None. + */ +void RCC_EnableAPB1Periphs(uint32_t apb1_periphs, bool enable); + +/*! + * @brief Reset the RCC APB1 periphs clock module. + * + * @param apb1_periphs APB1 Peripheral instance. + * @return None. + */ +void RCC_ResetAPB1Periphs(uint32_t apb1_periphs); + +/*! + * @brief Enable the RCC APB2 periphs clock module. + * + * @param apb2_periphs APB1 Peripheral instance. + * @param enable 'true' to enable the APB2Periphs, 'false' to disable the APB2Periphs. + * @return None. + */ +void RCC_EnableAPB2Periphs(uint32_t apb2_periphs, bool enable); + +/*! + * @brief Reset the RCC APB2 periphs clock module. + * + * @param apb2_periphs APB2 Peripheral instance. + * @return None. + */ +void RCC_ResetAPB2Periphs(uint32_t apb2_periphs); + +/*! + * @brief MCO Configuration clock source. + * + * @param source The clock source for MCO Configuration. + * @return None. + */ +void RCC_SetMCOConf(RCC_MCO_Type source); + +/*! + * @brief Set ADC clock div. + * + * @param ADCx ADC instance. + * @param div The ADC clock div. + * @return None. + */ +void RCC_SetADCClockDiv(ADC_Type * ADCx, uint32_t div); + +/*! + * @brief Set ADC calibration clock div. + * + * @param ADCx ADC instance. + * @param div The ADC calibration clock div. + * @return None. + */ +void RCC_SetADCCalibClockDiv(ADC_Type * ADCx, uint32_t div); + +/*! + * @brief Set DAC clock div. + * + * @param div The DAC clock div. + * @return None. + */ +void RCC_SetDACClockDiv(uint32_t div); + +/*! + * @brief Enable FSMC synchronization. + * + * @param enable 'true' to enable the FSMC synchronization,'false' to disable the FSMC synchronization, . + * @return None. + */ +void RCC_EnableFSMCSyncMode(bool enable); + +/*! + * @brief Set FSMC clock div. + * + * @param div The FSMC clock div. + * @return None. + */ +void RCC_SetFSMCClockdiv(uint32_t div); + +/*! + * @brief Set TPIU clock div. + * + * @param div The TPIU clock div. + * @return None. + */ +void RCC_SetTPIUClockDiv(uint32_t div); + +/*! + * @brief Enable BKP write Protect. + * + * @param enable 'true' to can not allow writting BKP & RTC ,'false' to allow writting BKP & RTC . + * @return None. + */ +void RCC_EanbleBKPWriteProtect(bool enable); + +/*! + * @brief Enable BKP reset. + * + * @param enable 'true' to reset BKP ,'false' to not reset. + * @return None. + */ +void RCC_EanbleBKPReset(bool enable); + +/*! + * @brief Enable RTC clock. + * + * @param enable 'true' to enable RTC cloxk ,'false' to disable. + * @return None. + */ +void RCC_EanbleRTCClock(bool enable); + +/*! + * @brief Set RTC clock source. + * + * @param source the RTC clock source. + * @return None. + */ +void RCC_SetRTCClockSource(uint32_t source); + +/*! + * @brief Enable LSE Bypass Mode. + * + * @param enable 'true' to enable LSE Bypass Mode ,'false' to disable. + * @return None. + */ +void RCC_EanbleLSEBypassMode(bool enable); + +/*! + * @brief Get LSE Oscillator Ready. + * + * @param None. + * @return Ready Status. + */ +uint32_t GetLSEReadyStatus(void); + +/*! + * @brief Enable LSE oscillator clock. + * + * @param enable 'true' to enable LSE oscillator clock ,'false' to disable. + * @return None. + */ +void RCC_EanbleLSEClock(bool enable); + +/*! + * @brief Get Reset Status. + * + * @param status the reset status ,see to @ref ResetStatus_Type. + * @return the reset status. + */ +uint32_t GetResetStatus(ResetStatus_Type status ); + +/*! + * @brief Clear all Reset Status. + * + * @param None. + * @return None. + */ +void ClearResetStatus(void); +/*! + * @brief Enable CPU Lock. + * + * @param enable 'true' to enable lock CPU ,'false' to disable. + * @return None. + */ +void RCC_EanbleCPULock(bool enable); +/*! + * @brief Enable PVD Reset. + * + * @param enable 'true' to reset PVD ,'false' to disable. + * @return None. + */ +void RCC_EanblePVDReset(bool enable); +/*! + * @brief Enable LSI clock output. + * + * @param enable 'true' to enable LSI clock output,'false' to disable. + * @return None. + */ +void RCC_EanbleLSIClockOutput(bool enable); +/*! + * @brief Enable LSI Oscillator . + * + * @param enable 'true' to enable LSI Oscillator ,'false' to disable. + * @return None. + */ +void RCC_EanbleLSIClock(bool enable); +/*! + *@} + */ + +#endif /* __HAL_RCC_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_rtc.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_rtc.c new file mode 100644 index 000000000..634ecce8d --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_rtc.c @@ -0,0 +1,229 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_rtc.h" + +/* Initialize RTC. */ +void RTC_Init(RTC_Type * RTCx, RTC_Init_Type * init) +{ + uint32_t temp = ( (init->ClockFreq / init->CountFreq) - 1u); + RTC_PutPrescalerValue(RTCx, temp); +} + +/* Get the current status flags of the RTC module. */ +uint32_t RTC_GetStatus(RTC_Type * RTCx) +{ + return RTCx->CRL; +} + +/* Clear the status flag of the RTC module. */ +void RTC_ClearStatus(RTC_Type * RTCx, uint32_t status) +{ + RTCx->CRL &= ~status; +} + +/* Set the counter hopping frequency, open configration module before put data into RTC register. */ +void RTC_PutPrescalerValue(RTC_Type * RTCx, uint32_t div) +{ + RTCx->CRL |= RTC_CRL_CNF_MASK; /* Enable the configuration mode. */ + RTCx->PRLH = div >> 16u; /* Setup the upper 16-bit value of prescaler, RTC_PRL[19:0] = (fRTC_CLK / fSC_CLK ) - 1u. */ + RTCx->PRLL = div; /* Setup the lower 16-bit value of prescaler. */ + RTCx->CRL &= ~RTC_CRL_CNF_MASK; /* Disable the configuration mode. */ +} + +/* Configure the value at which the counter starts counting. */ +void RTC_PutCounterValue(RTC_Type * RTCx, uint32_t cnt) +{ + RTCx->CRL |= RTC_CRL_CNF_MASK; /* Enable the configuration mode. */ + RTCx->CNTH = cnt >> 16u; /* Setup the upper 16-bit value of counter. */ + RTCx->CNTL = cnt; /* Setup the lower 16-bit value of counter. */ + RTCx->CRL &= ~RTC_CRL_CNF_MASK; /* Disable the configuration mode. */ +} + +/* Configure alarm clock response time. */ +void RTC_PutAlarmValue(RTC_Type * RTCx, uint32_t alarm) +{ + RTCx->CRL |= RTC_CRL_CNF_MASK; /* Enable the configuration mode. */ + RTCx->ALRH = alarm >> 16u; /* Setup the upper 16-bit value of alarm counter. */ + RTCx->ALRL = alarm; /* Setup the lower 16-bit value of alarm counter. */ + RTCx->CRL &= ~RTC_CRL_CNF_MASK; /* Disable the configuration mode. */ +} + +/* Get the current value from counter of RTC module. */ +uint32_t RTC_GetCounterValue(RTC_Type * RTCx) +{ + return ( (RTCx->CNTH << 16u) | RTCx->CNTL ); +} + +/* Get the alarm clock response time */ +uint32_t RTC_GetAlarmValue(RTC_Type * RTCx) +{ + return ( (RTCx->ALRH << 16u) | RTCx->ALRL); +} + +/* Enable RTC interrupt of RTC module. */ +void RTC_EnableInterrupts(RTC_Type * RTCx, uint32_t interrupts, bool enable) +{ + if (enable) + { + RTCx->CRH |= interrupts; + } + else + { + RTCx->CRH &= ~interrupts; + } +} + +/* Get the interrupts status flags of the RTC module. */ +uint32_t RTC_GetInterruptStatus(RTC_Type * RTCx) +{ + return (RTCx->CRL & RTCx->CRH); +} + +/* Clear the status of RTC interrupt. */ +void RTC_ClearInterruptStatus(RTC_Type * RTCx, uint32_t interrupts) +{ + RTCx->CRL &= ~interrupts; +} + +/* Judging whether the current year is a leap year, an ordinary leap year or a century leap year. */ +bool RTC_JudgeLeapYear(uint16_t years) +{ + if (years % 4u == 0u) + { + if (years % 100u == 0u) + { + if (years % 400u == 0u) + { + return true; /* Century leap year. */ + } + else + { + return false; + } + } + else + { + return true; /* Ordinary leap year. */ + } + } + else + { + return false; + } +} + +/* Month correction table, used for calculation of month. */ +const uint8_t month_table[12u] = {31u, 28u, 31u, 30u, 31u, 30u, 31u, 31u, 30u, 31u, 30u, 31u}; + +/* Setup initialization time, calculate the year, month, day, hour, minute and second as the total number of seconds. */ +void RTC_SetTime(RTC_Type * RTCx, RTC_Time_Type * time) +{ + /* Calculate the total number of seconds of the current configuration time. */ + uint32_t seccnt = 0u; + /* Calculate the number of seconds from the lowest years to the current setup years. */ + for (uint16_t years = time->Lyears; years < time->Years; years++) + { + if ( RTC_JudgeLeapYear(years) ) + { + seccnt += 31622400u; /* The number of seconds in leap year is 31622400. */ + } + else + { + seccnt += 31536000u; /* The number of seconds in normal year is 31622400. */ + } + } + + /* Add up the seconds of the previous month. */ + time->Months -= 1u; /* The month count starts from 0 instead of 1, so current months - 1. */ + for (uint16_t months = 0u; months < time->Months; months++) + { + seccnt += (uint32_t)month_table[months] * 86400u; /* Calculate the number of seconds of months, the total number of seconds in a day is 86400. */ + if ( ( RTC_JudgeLeapYear(time->Years) ) && (months == 1u) ) /* The time is in a leap year and february, add the number of seconds in one day. */ + { + seccnt += 86400u; /* The number of seconds in day is 86400. */ + } + } + /* Add up the seconds of the previous date. */ + seccnt += (uint32_t)(time->Days - 1u) * 86400u; /* The day set for initialization is less than 24 hours, which needs to be subtracted by one day. */ + seccnt += (uint32_t)(time->Hours) * 3600u; /* There are 3600 seconds in a hour. */ + seccnt += (uint32_t)(time->Mins) * 60u; /* There are 60 seconds in a minute. */ + seccnt += (time->Secs); + + /* Configrate counter value. */ + RTC_PutCounterValue(RTCx, seccnt); /* Put data into counter. */ +} + +/* Calculate the total number of seconds as year, month, day, hour, minute and second.. */ +void RTC_CalcTime(RTC_Type * RTCx, RTC_Time_Type * time) +{ + uint32_t count = RTC_GetCounterValue(RTCx); /* Get current seconds count. */ + + /* Calculated in days. */ + uint16_t years = time->Lyears; + uint32_t days = count / 86400u; + + for (; days >= 365u; days -= 365u) + { + if ( RTC_JudgeLeapYear(years) ) /* Determine whether it is a leap year. */ + { + if (days >= 366u) + { + days -= 1u; + } + else + { + break; + } + } + years++; + } + time->Years = years; /* Get current years. */ + + uint16_t months = 0u; + for (; days >= 28u; days -= 28u) + { + if ( ( true == RTC_JudgeLeapYear(time->Years) ) && (months == 1u) ) /* The time is February of leap year. */ + { + if (days >= 29u) + { + days -= 1u; + } + else + { + break; + } + } + else + { + if (days >= month_table[months]) /* Reach the maximum number of days in the current month. */ + { + days = days - month_table[months] + 28u; + } + else + { + break; + } + } + months++; + } + time->Months = months + 1u; /* Get current months. */ + time->Days = days + 1u; /* Get current days. */ + time->Hours = ( count % 86400u) / 3600u; /* Get current hours. */ + time->Mins = ((count % 86400u) % 3600u) / 60u; /* Get current minutes. */ + time->Secs = ((count % 86400u) % 3600u) % 60u; /* Get current seconds. */ +} + +/* Setup the alarm response time. */ +void RTC_SetAlarm(RTC_Type * RTCx, RTC_Time_Type * time) +{ + uint32_t value = RTC_GetCounterValue(RTCx); /* Get the current total number of seconds. */ + RTC_PutAlarmValue(RTCx, value + time->AlarmTime); /* Set alarm respond time. */ +} + +/* EOF. */ + diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_rtc.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_rtc.h new file mode 100644 index 000000000..daab71c3c --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_rtc.h @@ -0,0 +1,210 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_RTC_H__ +#define __HAL_RTC_H__ + +#include "hal_common.h" +#include "hal_rcc.h" + +/*! + * @addtogroup RTC + * @{ + */ + +/*! + * @addtogroup RTC_STATUS + * @{ + */ +#define RTC_STATUS_OPERATION RTC_CRL_RTOFF_MASK /*!< Status flag when write operation of RTC register is completed. */ +#define RTC_STATUS_SYNC RTC_CRL_RSF_MASK /*!< Status flag when registers synchronized. */ +/*! + * @} + */ + +/*! + * @addtogroup RTC_INT + * @{ + */ +#define RTC_INT_SEC RTC_CRL_SECF_MASK /*!< Interrupt enable when seconds interrupt generation or overflow of prescaler. After the flag is generated, RTC counter + 1. */ +#define RTC_INT_ALARM RTC_CRL_ALRF_MASK /*!< Interrupt enable when the alarm interrupt is generated, in other words, the value of the alarm counter is the same as the RTC counter. */ +#define RTC_INT_OVERFLOW RTC_CRL_OWF_MASK /*!< Interrupt enable when overflow interrupt generaton or programmable counter overflow. */ +/*! + * @} + */ + +/*! + * @brief Define the callback function called when the RTC interrupt is done. + */ +typedef void (*RTC_Callback_1_Type)(void *param); + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref RTC_Init() to initialize the RTC module. + */ +typedef struct +{ + uint32_t ClockFreq; /*!< Used to calculate the overload value of prescaler, RTC_PRL[19:0] = (ClockFreq / CountFreq) - 1u. */ + uint32_t CountFreq; /*!< Used to set the clock hopping frequency of the counter, and the maximum frequency should not exceed 1 second. */ +} RTC_Init_Type; + +/*! + * @brief This type of structure instance is used to set and get time when set time and get current time. + */ +typedef struct +{ + uint8_t Secs; /*!< Specify the clock seconds. */ + uint8_t Mins; /*!< Specify the clock minutes. */ + uint8_t Hours; /*!< Specify the clock hours. */ + uint8_t Days; /*!< Specify the clock days. */ + uint8_t Months; /*!< Specify the clock months. */ + uint16_t Years; /*!< Specify the clock years. */ + uint16_t Lyears; /*!< Specify term of lowest years. */ + uint32_t AlarmTime; /*!< Specify the number of seconds that alarm clock will respond. */ +} RTC_Time_Type; + +/*! + * @brief Initialize the RTC module. + * + * @param RTCx RTC instance. + * @param init Pointer to the initialization structure. See to @ref RTC_Init_Type. + * @return None. + */ +void RTC_Init(RTC_Type * RTCx, RTC_Init_Type * init); + +/*! + * @brief Get the current status flags of the RTC module. + * + * @param RTCx RTC instance. + * @return Status flags. See to @ref RTC_STATUS. + */ +uint32_t RTC_GetStatus(RTC_Type * RTCx); + +/*! + * @brief Clear the status flags of the RTC module. + * + * @param RTCx RTC instance. + * @param status The mask code of the indicated flags to be clear. See to @ref RTC_STATUS. + * @return None. + */ +void RTC_ClearStatus(RTC_Type * RTCx, uint32_t status); + +/*! + * @brief Configure the prescaler reload value. + * + * The value of div determines the hopping frequency of the counter. + * div = (ClockFreq / CountFreq) - 1u, CountFreq is hopping frequency of the counter, the counter jumps once every second at most. + * The counter maximum jumps once every second, so the maximum CountFreq is no more than 1. + * + * @param RTCx RTC instance. + * @param div Data value to be send into the prescaler register. + * @return None. + */ +void RTC_PutPrescalerValue(RTC_Type * RTCx, uint32_t div); + +/*! + * @brief Configure the value at which the counter starts counting. + * + * The counter starts counting from value of cnt. + * + * @param RTCx RTC instance. + * @param cnt The value of counter starts counting. + * @return None. + */ +void RTC_PutCounterValue(RTC_Type * RTCx, uint32_t cnt); + +/*! + * @brief Configure alarm clock response time. + * + * @param RTCx RTC instance. + * @param alarm Data value to be send into the alarm register. + * @return None. + */ +void RTC_PutAlarmValue(RTC_Type * RTCx, uint32_t alarm); + +/*! + * @brief Get the current value from counter. + * + * @param RTCx RTC instance. + * @return The data value from counter. + */ +uint32_t RTC_GetCounterValue(RTC_Type * RTCx); + +/*! + * @brief Get the value the alarm clock will respond to. + * + * @param RTCx RTC instance. + * @return The value the alarm clock will respond to. + */ +uint32_t RTC_GetAlarmValue(RTC_Type * RTCx); + +/*! + * @brief Enabel interrupt of the RTC module. + * + * @param RTCx RTC instance. + * @param interrupts Interrupt code masks. See to @ref RTC_INT. + * @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts. + * @return None. + */ +void RTC_EnableInterrupts(RTC_Type * RTCx, uint32_t interrupts, bool enable); + +/*! + * @brief Get the interrupts status flags of the RTC module. + * + * @param RTCx RTC instance. + * @return Interrupt status flags. See to @ref RTC_INT. + */ +uint32_t RTC_GetInterruptStatus(RTC_Type * RTCx); + +/*! + * @brief Clear the interrupts status flags of the RTC module. + * + * @param RTCx RTC instance. + * @param interrupts The mask codes of the indicated interrupt flags to be cleared. See to @ref RTC_INT. + * @return None. + */ +void RTC_ClearInterruptStatus(RTC_Type * RTCx, uint32_t interrupts); + +/*! + * @brief Setup the initialization time of the RTC module. + * + * Use RTC_PutCounterValue(), calculate the year, month, day, hour, minute and second as the total number of seconds. + * + * @param RTCx RTC instance. + * @param time Pointer to the time structure. See to @ref RTC_Time_Type. + * @return 'true' to set time succeess, 'false' to set time failed. + */ +void RTC_SetTime(RTC_Type * RTCx, RTC_Time_Type * time); + +/*! + * @brief Calculate and get current time. + * + * Use RTC_GetCounterValue(), calculate the total number of seconds as year, month, day, hour, minute and second. + * + * @param RTCx RTC instance. + * @param time Pointer to the time structure. See to @ref RTC_Time_Type. + * @return None. + */ +void RTC_CalcTime(RTC_Type * RTCx, RTC_Time_Type * time); + +/*! + * @brief Set alarm time of the RTC module. + * + * Use RTC_GetCounterValue() and RTC_PutAlarmValue() + * Get the current total seconds, plus the alarm response time, and put it into the alarm register. + * + * @param RTCx RTC instance. + * @param time Pointer to the time structure. See to @ref RTC_Time_Type. + * @return 'true' to set alarm time succeess, 'false' to set alarm time failed. + */ +void RTC_SetAlarm(RTC_Type * RTCx, RTC_Time_Type * time); + +/*! + *@} + */ + +#endif /* __HAL_RTC_H__ */ + diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_spi.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_spi.c new file mode 100644 index 000000000..bbd1a428c --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_spi.c @@ -0,0 +1,273 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_spi.h" + +void SPI_SetBaudrate(SPI_Type * SPIx, uint32_t src_clk, uint32_t baudrate) +{ + uint32_t div = src_clk / baudrate; + if (div < 2u) + { + /* div = 0, 1 is not allowed. */ + div = 2u; + } + SPIx->SPBRG = div; + if (div <= 4) + { + /* to support high speed mode. */ + SPIx->CCTL |= (SPI_I2S_CCTL_TXEDGE_MASK | SPI_I2S_CCTL_RXEDGE_MASK); + } + else + { + SPIx->CCTL &= ~(SPI_I2S_CCTL_TXEDGE_MASK | SPI_I2S_CCTL_RXEDGE_MASK); + } +} + +/* SPI peripheral is disabled just after the initialization. + * user needs to call SPI_Enable() before using the module. + */ +void SPI_InitMaster(SPI_Type * SPIx, SPI_Master_Init_Type * init) +{ + uint32_t gctl = SPIx->GCTL &~ ( SPI_I2S_GCTL_MODE_MASK + | SPI_I2S_GCTL_RXEN_MASK + | SPI_I2S_GCTL_TXEN_MASK + | SPI_I2S_GCTL_NSS_MASK + | SPI_I2S_GCTL_INTEN_MASK + | SPI_I2S_GCTL_DW832_MASK + ); + uint32_t extctl = 0u; + + uint32_t cctl = SPIx->CCTL &~ ( SPI_I2S_CCTL_CPHA_MASK + | SPI_I2S_CCTL_CPOL_MASK + | SPI_I2S_CCTL_LSBFE_MASK + | SPI_I2S_CCTL_SPILEN_MASK + ); + + /* Master. */ + gctl |= SPI_I2S_GCTL_MODE_MASK; /* master mode, disable spi, and reset the other bits in CCTL. */ + + /* XferMode. */ + switch (init->XferMode) + { + case SPI_XferMode_RxOnly: + gctl |= SPI_I2S_GCTL_RXEN_MASK; + break; + + case SPI_XferMode_TxRx: + gctl |= (SPI_I2S_GCTL_RXEN_MASK | SPI_I2S_GCTL_TXEN_MASK); + break; + + default: + break; + } + + /* AutoCS. */ + if (init->AutoCS) + { + gctl |= SPI_I2S_GCTL_NSS_MASK; + } + + /* Interrupts. Always enable the global interrupt. The specific events are controlled by each bits in INTEN register. */ + gctl |= SPI_I2S_GCTL_INTEN_MASK; + + /* DataWidth. */ + if (init->DataWidth == SPI_DataWidth_7b) + { + } + else if (init->DataWidth == SPI_DataWidth_8b) + { + cctl |= SPI_I2S_CCTL_SPILEN_MASK; + } + else + { + gctl |= SPI_I2S_GCTL_DW832_MASK; + extctl = SPI_I2S_EXTCTL_EXTLEN(init->DataWidth); + } + + /* CPOL & CPHA. */ + cctl |= ( (SPI_I2S_CCTL_CPHA_MASK | SPI_I2S_CCTL_CPOL_MASK) + & ((init->PolPha) << SPI_I2S_CCTL_CPHA_SHIFT) + ); + + /* MSB. */ + if (init->LSB) + { + cctl |= SPI_I2S_CCTL_LSBFE_MASK; + } + + SPIx->GCTL = gctl; + SPIx->CCTL = cctl; + SPIx->EXTCTL = extctl; + + /* BaudRate. */ + SPI_SetBaudrate(SPIx, init->ClockFreqHz, init->BaudRate); +} + +void SPI_InitSlave(SPI_Type * SPIx, SPI_Slave_Init_Type * init) +{ + uint32_t gctl = SPIx->GCTL &~ ( SPI_I2S_GCTL_MODE_MASK + | SPI_I2S_GCTL_RXEN_MASK + | SPI_I2S_GCTL_TXEN_MASK + | SPI_I2S_GCTL_NSS_MASK + | SPI_I2S_GCTL_INTEN_MASK + | SPI_I2S_GCTL_DW832_MASK + ); + uint32_t cctl = SPIx->CCTL &~ ( SPI_I2S_CCTL_CPHA_MASK + | SPI_I2S_CCTL_CPOL_MASK + | SPI_I2S_CCTL_LSBFE_MASK + | SPI_I2S_CCTL_SPILEN_MASK + ); + uint32_t extctl = 0u; + + /* XferMode. */ + switch (init->XferMode) + { + case SPI_XferMode_RxOnly: + gctl |= SPI_I2S_GCTL_RXEN_MASK; + break; + + case SPI_XferMode_TxRx: + gctl |= (SPI_I2S_GCTL_RXEN_MASK | SPI_I2S_GCTL_TXEN_MASK); + break; + + default: + break; + } + + /* AutoCS. */ + if (init->AutoCS) + { + gctl |= SPI_I2S_GCTL_NSS_MASK; + } + + /* Interrupts. Always enable the global interrupt. The specific events are controlled by each bits in INTEN register. */ + gctl |= SPI_I2S_GCTL_INTEN_MASK; + + /* DataWidth. */ + if (init->DataWidth == SPI_DataWidth_7b) + { + } + else if (init->DataWidth == SPI_DataWidth_8b) + { + cctl |= SPI_I2S_CCTL_SPILEN_MASK; + } + else + { + gctl |= SPI_I2S_GCTL_DW832_MASK; + extctl = SPI_I2S_EXTCTL_EXTLEN(init->DataWidth); + } + + /* CPOL & CPHA. */ + cctl |= ( (SPI_I2S_CCTL_CPHA_MASK | SPI_I2S_CCTL_CPOL_MASK) + & ((init->PolPha) << SPI_I2S_CCTL_CPHA_SHIFT) + ); + + /* MSB. */ + if (init->LSB) + { + cctl |= SPI_I2S_CCTL_LSBFE_MASK; + } + + SPIx->GCTL = gctl; + SPIx->CCTL = cctl; + SPIx->EXTCTL = extctl; +} + +void SPI_Enable(SPI_Type * SPIx, bool enable) +{ + if (enable) + { + SPIx->GCTL |= SPI_I2S_GCTL_SPIEN_MASK; + } + else + { + SPIx->GCTL &= ~SPI_I2S_GCTL_SPIEN_MASK; + } +} + +uint32_t SPI_GetStatus(SPI_Type * SPIx) +{ + return SPIx->CSTAT; +} + +void SPI_EnableInterrupts(SPI_Type * SPIx, uint32_t interrupts, bool enable) +{ + if (enable) + { + SPIx->INTEN |= interrupts; + } + else + { + SPIx->INTEN &= ~interrupts; + } +} + +uint32_t SPI_GetInterruptStatus(SPI_Type * SPIx) +{ + return SPIx->INTSTAT; +} + +void SPI_ClearInterruptStatus(SPI_Type * SPIx, uint32_t interrupts) +{ + SPIx->INTCLR = interrupts; +} + +void SPI_PutData(SPI_Type * SPIx, uint32_t data) +{ + SPIx->TXREG = data; +} + +uint32_t SPI_GetData(SPI_Type * SPIx) +{ + return SPIx->RXREG; +} + +void SPI_EnableDMA(SPI_Type * SPIx, bool enable) +{ + if (enable) + { + SPIx->GCTL |= SPI_I2S_GCTL_DMAMODE_MASK; + } + else + { + SPIx->GCTL &= ~SPI_I2S_GCTL_DMAMODE_MASK; + } +} + +uint32_t SPI_GetEnabledInterrupts(SPI_Type * SPIx) +{ + return SPIx->INTEN; +} + +uint32_t SPI_GetRxDataRegAddr(SPI_Type * SPIx) +{ + return (uint32_t)(&(SPIx->RXREG)); +} + +uint32_t SPI_GetTxDataRegAddr(SPI_Type * SPIx) +{ + return (uint32_t)(&(SPIx->TXREG)); +} + +void SPI_EnableCS(SPI_Type * SPIx, uint32_t cs_mask) +{ + SPIx->NSSR = ~(cs_mask); +} + +void SPI_SetRxDataNum(SPI_Type * SPIx, uint16_t number) +{ + SPIx->RXDNR = number; +} + + +void SPI_SetPadMux(SPI_Type * SPIx, SPI_PadMux_Type opt) +{ + SPIx->GCTL = ( (SPIx->GCTL &~ SPI_I2S_GCTL_PADSEL_MASK) + | SPI_I2S_GCTL_PADSEL(opt) + ); +} +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_spi.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_spi.h new file mode 100644 index 000000000..472501c38 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_spi.h @@ -0,0 +1,319 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_SPI_H__ +#define __HAL_SPI_H__ + +#include "hal_common.h" + +/*! + * @addtogroup SPI + * @{ + */ + +/*! + * @brief SPI driver version number. + */ +#define SPI_DRIVER_VERSION 0u /*!< spi_0. */ + +/*! + * @addtogroup SPI_STATUS + * @{ + */ +#define SPI_STATUS_BUSY SPI_I2S_CSTAT_BUSY_MASK /*!< Status flag when SPI is transmitting or receiving. */ +#define SPI_STATUS_TX_EMPTY SPI_I2S_CSTAT_TXEPT_MASK /*!< Status flag when SPI transmiter buffer is empty. */ +#define SPI_STATUS_RX_DONE SPI_I2S_CSTAT_RXAVL_MASK /*!< Status flag when SPI receiving buffer is with available data. */ +#define SPI_STATUS_TX_FULL SPI_I2S_CSTAT_TXFULL_MASK /*!< Status flag when SPI transmiter buffer is full. */ +/*! + * @} + */ + +/*! + * @addtogroup SPI_INT + * @{ + */ +#define SPI_INT_TX_DONE SPI_I2S_INTEN_TXIEN_MASK /*!< Interrupt enable when SPI transmiter buffer has started sending data. */ +#define SPI_INT_RX_DONE SPI_I2S_INTEN_RXIEN_MASK /*!< Interrupt enable when SPI receiving buffer is with available data. */ +#define SPI_INT_TX_UNDERRUN SPI_I2S_INTEN_UNDERRUNIEN_MASK /*!< Interrupt enable when SPI transmiter transmit empty data. */ +#define SPI_INT_RX_OVERRUN SPI_I2S_INTEN_RXOERRIEN_MASK /*!< Interrupt enable when SPI receive data using the full buffer. */ +#define SPI_INT_RX_MATCH SPI_I2S_INTEN_RXMATCHIEN_MASK /*!< Interrupt enable when SPI receiving buffer match the width set in RXDNR. */ +#define SPI_INT_RX_FULL SPI_I2S_INTEN_RXFULLIEN_MASK /*!< Interrupt enable when SPI receiving buffer is full. */ +#define SPI_INT_TX_EMPTY SPI_I2S_INTEN_TXEPTIEN_MASK /*!< Interrupt enable when SPI transmiter buffer is empty. */ +/*! + * @} + */ + +/*! + * @brief SPI Polarity Phase type. + */ +typedef enum +{ + SPI_PolPha_Alt0 = 0u, /*!< CPOL = 0, CPHA = 1, Clock line is low when idle, Data valid when at falling edge */ + SPI_PolPha_Alt1 = 1u, /*!< CPOL = 0, CPHA = 0, Clock line is low when idle, Data valid when at rising edge */ + SPI_PolPha_Alt2 = 2u, /*!< CPOL = 1, CPHA = 1, Clock line is high when idle, Data valid when at rising edge */ + SPI_PolPha_Alt3 = 3u, /*!< CPOL = 1, CPHA = 0, Clock line is high when idle, Data valid when at falling edge */ +} SPI_PolPha_Type; + +/*! + * @brief SPI data width type. + */ +typedef enum +{ + SPI_DataWidth_32b = 0u, /*!< Data Width 32 bits. */ + SPI_DataWidth_1b = 1u, /*!< Data Width 1 bits. */ + SPI_DataWidth_2b = 2u, /*!< Data Width 2 bits. */ + SPI_DataWidth_3b = 3u, /*!< Data Width 3 bits. */ + SPI_DataWidth_4b = 4u, /*!< Data Width 4 bits. */ + SPI_DataWidth_5b = 5u, /*!< Data Width 5 bits. */ + SPI_DataWidth_6b = 6u, /*!< Data Width 6 bits. */ + SPI_DataWidth_7b = 7u, /*!< Data Width 7 bits. */ + SPI_DataWidth_8b = 8u, /*!< Data Width 8 bits. */ + SPI_DataWidth_9b = 9u, /*!< Data Width 9 bits. */ + SPI_DataWidth_10b = 10u, /*!< Data Width 10 bits. */ + SPI_DataWidth_11b = 11u, /*!< Data Width 11 bits. */ + SPI_DataWidth_12b = 12u, /*!< Data Width 12 bits. */ + SPI_DataWidth_13b = 13u, /*!< Data Width 13 bits. */ + SPI_DataWidth_14b = 14u, /*!< Data Width 14 bits. */ + SPI_DataWidth_15b = 15u, /*!< Data Width 15 bits. */ + SPI_DataWidth_16b = 16u, /*!< Data Width 16 bits. */ + SPI_DataWidth_17b = 17u, /*!< Data Width 17 bits. */ + SPI_DataWidth_18b = 18u, /*!< Data Width 18 bits. */ + SPI_DataWidth_19b = 19u, /*!< Data Width 19 bits. */ + SPI_DataWidth_20b = 20u, /*!< Data Width 20 bits. */ + SPI_DataWidth_21b = 21u, /*!< Data Width 21 bits. */ + SPI_DataWidth_22b = 22u, /*!< Data Width 22 bits. */ + SPI_DataWidth_23b = 23u, /*!< Data Width 23 bits. */ + SPI_DataWidth_24b = 24u, /*!< Data Width 24 bits. */ + SPI_DataWidth_25b = 25u, /*!< Data Width 25 bits. */ + SPI_DataWidth_26b = 26u, /*!< Data Width 26 bits. */ + SPI_DataWidth_27b = 27u, /*!< Data Width 27 bits. */ + SPI_DataWidth_28b = 28u, /*!< Data Width 28 bits. */ + SPI_DataWidth_29b = 29u, /*!< Data Width 29 bits. */ + SPI_DataWidth_30b = 30u, /*!< Data Width 30 bits. */ + SPI_DataWidth_31b = 31u, /*!< Data Width 31 bits. */ +} SPI_DataWidth_Type; + +/*! + * @brief Pin mux for SCK, MOSI, NSS, MISO. + */ +typedef enum +{ + SPI_PadMux_SCK_MOSI_NSS_MISO = 0u, /*!< Specifies SPI pin mux switcher 0. */ + SPI_PadMux_SCK_MOSI_MISO_NSS = 1u, /*!< Specifies SPI pin mux switcher 1. */ + SPI_PadMux_SCK_NSS_MOSI_MISO = 2u, /*!< Specifies SPI pin mux switcher 2. */ + SPI_PadMux_SCK_NSS_MISO_MOSI = 3u, /*!< Specifies SPI pin mux switcher 3. */ + SPI_PadMux_SCK_MISO_MOSI_NSS = 4u, /*!< Specifies SPI pin mux switcher 4. */ + SPI_PadMux_SCK_MISO_NSS_MOSI = 5u, /*!< Specifies SPI pin mux switcher 5. */ + SPI_PadMux_MOSI_SCK_NSS_MISO = 6u, /*!< Specifies SPI pin mux switcher 6. */ + SPI_PadMux_MOSI_SCK_MISO_NSS = 7u, /*!< Specifies SPI pin mux switcher 7. */ + SPI_PadMux_MOSI_NSS_SCK_MISO = 8u, /*!< Specifies SPI pin mux switcher 8. */ + SPI_PadMux_MOSI_NSS_MISO_SCK = 9u, /*!< Specifies SPI pin mux switcher 9. */ + SPI_PadMux_MOSI_MISO_SCK_NSS = 10u, /*!< Specifies SPI pin mux switcher 10. */ + SPI_PadMux_MOSI_MISO_NSS_SCK = 11u, /*!< Specifies SPI pin mux switcher 11. */ + SPI_PadMux_NSS_SCK_MOSI_MISO = 12u, /*!< Specifies SPI pin mux switcher 12. */ + SPI_PadMux_NSS_SCK_MISO_MOSI = 13u, /*!< Specifies SPI pin mux switcher 13. */ + SPI_PadMux_NSS_MOSI_SCK_MISO = 14u, /*!< Specifies SPI pin mux switcher 14. */ + SPI_PadMux_NSS_MOSI_MISO_SCK = 15u, /*!< Specifies SPI pin mux switcher 15. */ + SPI_PadMux_NSS_MISO_SCK_MOSI = 16u, /*!< Specifies SPI pin mux switcher 16. */ + SPI_PadMux_NSS_MISO_MOSI_SCK = 17u, /*!< Specifies SPI pin mux switcher 17. */ + SPI_PadMux_MISO_SCK_MOSI_NSS = 18u, /*!< Specifies SPI pin mux switcher 18. */ + SPI_PadMux_MISO_SCK_NSS_MOSI = 19u, /*!< Specifies SPI pin mux switcher 19. */ + SPI_PadMux_MISO_MOSI_SCK_NSS = 20u, /*!< Specifies SPI pin mux switcher 20. */ + SPI_PadMux_MISO_MOSI_NSS_SCK = 21u, /*!< Specifies SPI pin mux switcher 21. */ + SPI_PadMux_MISO_NSS_SCK_MOSI = 22u, /*!< Specifies SPI pin mux switcher 22. */ + SPI_PadMux_MISO_NSS_MOSI_SCK = 23u, /*!< Specifies SPI pin mux switcher 23. */ +} SPI_PadMux_Type; + +/*! + * @brief SPI xfer mode type. + */ +typedef enum +{ + SPI_XferMode_Disabled = 0u, /*!< Disable both Tx and Rx. */ + SPI_XferMode_RxOnly = 1u, /*!< Enable Rx only. */ + SPI_XferMode_TxRx = 2u, /*!< Enable both Tx and Rx. */ +} SPI_XferMode_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref SPI_InitMaster() to initialize the SPI module. + */ +typedef struct +{ + uint32_t ClockFreqHz; /*!< Bus Clock Freq. */ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. */ + SPI_PolPha_Type PolPha; /*!< Specifies different communication modes. */ + SPI_DataWidth_Type DataWidth; /*!< Specifies the number of bits of data to be transmitted. */ + SPI_XferMode_Type XferMode; /*!< Specifies whether the Receive or Transmit mode is enable or not. */ + bool AutoCS; /*!< Specifies whether the chip selection signal is controlled by SPI or not. */ + bool LSB; /*!< Specifies whether the current state is Thumb or ARM mode. */ +} SPI_Master_Init_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref SPI_InitSlave() to initialize the SPI module. + */ +typedef struct +{ + SPI_PolPha_Type PolPha; /*!< Specifies different communication modes. */ + SPI_DataWidth_Type DataWidth; /*!< Specifies the number of bits of data to be transmitted. */ + SPI_XferMode_Type XferMode; /*!< Specifies whether the Receive or Transmit mode is enable or not. */ + bool AutoCS; /*!< Specifies whether the chip selection signal is controlled by SPI or not. */ + bool LSB; /*!< Specifies whether the current state is Thumb or ARM mode. */ +} SPI_Slave_Init_Type; + +/*! + * @brief Initialize the SPI Master module. + * + * @param SPIx SPI instance. + * @param init Pointer to the initialization structure. See to @ref SPI_Master_Init_Type. + * @return None. + */ +void SPI_InitMaster(SPI_Type * SPIx, SPI_Master_Init_Type * init); + +/*! + * @brief Initialize the SPI Slave module. + * + * @param SPIx SPI instance. + * @param init Pointer to the initialization structure. See to @ref SPI_Slave_Init_Type. + * @return None. + */ +void SPI_InitSlave(SPI_Type * SPIx, SPI_Slave_Init_Type * init); + +/*! + * @brief Enable the SPI module. + * + * The SPI module should be enabled before sending or receiving data. + * + * @param SPIx SPI instance. + * @param enable 'true' to enable the module, 'false' to disable the module. + * @return None. + */ +void SPI_Enable(SPI_Type * SPIx, bool enable); + +/*! + * @brief Get the current status flags of the SPI module. + * + * @param SPIx SPI instance. + * @return Status flags. See to @ref SPI_STATUS. + */ +uint32_t SPI_GetStatus(SPI_Type * SPIx); + +/*! + * @brief Enable interrupts of the SPI module. + * + * @param SPIx SPI instance. + * @param interrupts Interrupt code masks. See to @ref SPI_INT. + * @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts. + * @return None. + */ +void SPI_EnableInterrupts(SPI_Type * SPIx, uint32_t interrupts, bool enable); + +/*! + * @brief Get the interrupts status flags of the SPI module. + * + * @param SPIx SPI instance. + * @return Interrupt status flags. See to @ref SPI_INT. + */ +uint32_t SPI_GetInterruptStatus(SPI_Type * SPIx); + +/*! + * @brief Clear the interrupts status flags of the SPI module. + * + * @param SPIx SPI instance. + * @param interrupts The mask codes of the indicated interrupt flags to be cleared. + * @return Interrupt status flags. See to @ref SPI_INT. + */ +void SPI_ClearInterruptStatus(SPI_Type * SPIx, uint32_t interrupts); + +/*! + * @brief Put the data into transmiter buffer of the SPI module. + * + * @param SPIx SPI instance. + * @param data Data value to be send through the transmiter. + * @return None. + */ +void SPI_PutData(SPI_Type * SPIx, uint32_t data); + +/*! + * @brief Get the data from receiver buffer of the SPI module. + * + * @param SPIx SPI instance. + * @return The data value received from the receiver. + * @return None. + */ +uint32_t SPI_GetData(SPI_Type * SPIx); + +/*! + * @brief Enable the DMA trigger from the SPI module. + * + * The DMA trigger events are the same as the intertupts. + * + * @param SPIx SPI instance. + * @param enable 'true' to enable the DMA trigger, 'false' to disable the DMA trigger. + * @return None. + */ +void SPI_EnableDMA(SPI_Type * SPIx, bool enable); + +/*! + * @brief Read the current enabled interrupts the SPI module. + * + * @param SPIx SPI instance. + * @return The mask codes enabled interrupts. See to ref@ SPI_INT. + */ +uint32_t SPI_GetEnabledInterrupts(SPI_Type * SPIx); + +/*! + * @brief Get the hardware Rx data buffer's address the SPI module. + * + * The return value of the address is most used with DMA module. + * + * @param SPIx SPI instance. + * @return The value of the address for SPI module's hardware Rx data buffer. + */ +uint32_t SPI_GetRxDataRegAddr(SPI_Type * SPIx); + +/*! + * @brief Get the hardware Tx data buffer's address the SPI module. + * + * The return value of the address is most used with DMA module. + * + * @param SPIx SPI instance. + * @return The value of the address for SPI module's hardware Tx data buffer. + */ +uint32_t SPI_GetTxDataRegAddr(SPI_Type * SPIx); + +/*! + * @brief Enable the SPI CS module. + * + * @param SPIx SPI instance. + * @param cs_mask Code mask of whether the chip selection signal is controlled by SPI + * @return None. + */ +void SPI_EnableCS(SPI_Type * SPIx, uint32_t cs_mask); + +/*! + * @brief Set the SPI master read only data length. + * + * @param SPIx SPI instance. + * @param length Data length the rx is expectated to receive. + * @return None. + */ +void SPI_SetRxDataLen(SPI_Type * SPIx, uint16_t length); + +/*! + * @brief Set the PAD selection for SPI pins. + * + * @param SPIx SPI instance. + * @param opt SPI pad selection. See to @ref SPI_PadMux_Type. + * @return None. + */ +void SPI_SetPadMux(SPI_Type * SPIx, SPI_PadMux_Type opt); + +/*! + *@} + */ + +#endif /* __HAL_SPI_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_syscfg.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_syscfg.c new file mode 100644 index 000000000..67919a8b3 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_syscfg.c @@ -0,0 +1,136 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#include "hal_syscfg.h" + +#define SYSCFG_EXTICR_MASK(x) ( (0x0Fu) << ( ( (uint32_t)(x) & 0x3u ) << 2u ) ) /* mask bit for clear exti line. */ +#define SYSCFG_EXTICR(x, y) ( (uint32_t)( (uint32_t)(x) << ( ( (uint32_t)(y) & 0x3u ) << 2u ) ) ) /* set the data for indicated exti port and line. */ + +// void SYSCFG_SetBootMemMode(SYSCFG_BootMemMode_Type mode) +// { +// SYSCFG->CFGR = ( SYSCFG->CFGR & ~ SYSCFG_CFGR_MEMMODE_MASK ) +// | SYSCFG_CFGR_MEMMODE(mode); +// } + +void SYSCFG_SetFSMCPinUseMode(SYSCFG_FSMCPinUseMode_Type mode) +{ + SYSCFG->CFGR = ( SYSCFG->CFGR & ~ SYSCFG_CFGR_FCODATAEN_MASK ) + | SYSCFG_CFGR_FCODATAEN(mode); +} + +void SYSCFG_SetFSMCMode(SYSCFG_FSMCMode_Type mode) +{ + SYSCFG->CFGR = ( SYSCFG->CFGR & ~ SYSCFG_CFGR_FCMODESEL_MASK ) + | SYSCFG_CFGR_FCMODESEL(mode); +} + +void SYSCFG_SetExtIntMux(SYSCFG_EXTIPort_Type port, SYSCFG_EXTILine_Type line) +{ + if ( line < SYSCFG_EXTILine_4) + { + SYSCFG->EXTICR1 = ( SYSCFG->EXTICR1 & ~ SYSCFG_EXTICR_MASK(line) ) + | ( SYSCFG_EXTICR(port, line) ); + } + else if ( line < SYSCFG_EXTILine_8 ) + { + SYSCFG->EXTICR2 = ( SYSCFG->EXTICR1 & ~ SYSCFG_EXTICR_MASK(line) ) + | ( SYSCFG_EXTICR(port, line) ); + } + else if ( line < SYSCFG_EXTILine_12 ) + { + SYSCFG->EXTICR3 = ( SYSCFG->EXTICR1 & ~ SYSCFG_EXTICR_MASK(line) ) + | ( SYSCFG_EXTICR(port, line) ); + } + else + { + SYSCFG->EXTICR4 = ( SYSCFG->EXTICR1 & ~ SYSCFG_EXTICR_MASK(line) ) + | ( SYSCFG_EXTICR(port, line) ); + } +} + +void SYSCFG_SetI2C0PortMode(SYSCFG_I2CPortMode_Type mode) +{ + SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_I2C1MODESEL_MASK ) + | SYSCFG_CFGR2_I2C1MODESEL(mode); +} + +void SYSCFG_SetI2C1PortMode(SYSCFG_I2CPortMode_Type mode) +{ + SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_I2C2MODESEL_MASK ) + | SYSCFG_CFGR2_I2C2MODESEL(mode); +} + +void SYSCFG_SetENETPortMode(SYSCFG_ENETPortMode_Type mode) +{ + SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_ENETMIIRMIISEL_MASK ) + | SYSCFG_CFGR2_ENETMIIRMIISEL(mode); +} + +void SYSCFG_SetENETSpeedMode(SYSCFG_ENETSpeedMode_Type mode) +{ + SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_ENETSPDSEL_MASK ) + | SYSCFG_CFGR2_ENETSPDSEL(mode); +} + +void SYSCFG_EnablePVD(SYSCFG_PVDConf_Type * conf) +{ + if (conf == NULL) + { + SYSCFG->PDETCSR &= ~ SYSCFG_PDETCSR_PVDE_MASK; + } + else + { + SYSCFG->PDETCSR = ( ( SYSCFG->PDETCSR & ~ ( SYSCFG_PDETCSR_PVDE_MASK + | SYSCFG_PDETCSR_PLS_MASK + | SYSCFG_PDETCSR_PVDO_MASK + ) ) + | SYSCFG_PDETCSR_PLS(conf->Thold) + | SYSCFG_PDETCSR_PVDO(conf->Output) + | SYSCFG_PDETCSR_PVDE_MASK + ); + + } +} + +void SYSCFG_EnableVDT(SYSCFG_VDTConf_Type * conf) +{ + if (conf == NULL) + { + SYSCFG->PDETCSR &= ~ SYSCFG_PDETCSR_VDTE_MASK; + } + else + { + SYSCFG->PDETCSR = ( ( SYSCFG->PDETCSR & ~ ( SYSCFG_PDETCSR_VDTE_MASK + | SYSCFG_PDETCSR_VDTLS_MASK + | SYSCFG_PDETCSR_VDTO_MASK + ) ) + | SYSCFG_PDETCSR_VDTLS(conf->Thold) + | SYSCFG_PDETCSR_VDTO(conf->Output) + | SYSCFG_PDETCSR_VDTE_MASK + ); + } +} + +void SYSCFG_EnableADCCheckVBatDiv3(bool enable) +{ + if (enable) + { + SYSCFG->PDETCSR |= SYSCFG_PDETCSR_VBATDIV3EN_MASK; + } + else + { + SYSCFG->PDETCSR &= ~ SYSCFG_PDETCSR_VBATDIV3EN_MASK; + } +} + +void SYSCFG_SetVOSDelayValue(uint32_t val) +{ + SYSCFG->VOSDLY = val; +} + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_syscfg.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_syscfg.h new file mode 100644 index 000000000..071ca9cdd --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_syscfg.h @@ -0,0 +1,277 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef __HAL_SYSCFG_H__ +#define __HAL_SYSCFG_H__ + +#include "hal_common.h" + +/*! + * @addtogroup SYSCFG + * @{ + */ + +/*! + * @brief Boot memory mapping mode. + */ +typedef enum +{ + SYSCFG_BootMemMode_Flash = 0u, /*!< SYSCFG Boot Memory Flash mode. */ + SYSCFG_BootMemMode_ROM = 1u, /*!< SYSCFG Boot Memory ROM mode. */ + SYSCFG_BootMemMode_SRAM = 3u, /*!< SYSCFG Boot Memory SRAM mode. */ +} SYSCFG_BootMemMode_Type; + +/*! + * @brief Set FSMC compatible mode. + */ +typedef enum +{ + SYSCFG_FSMCMode_NorFlash = 0u, /*!< SYSCFG FSMC compatible with Nor Flash. */ + SYSCFG_FSMCMode_8080 = 1u, /*!< SYSCFG FSMC compatible with 8080 protocal. */ +} SYSCFG_FSMCMode_Type; + +/*! + * @brief FSMC pin usage. + * FSMC pins can be used as data use only or mixed as data use and address use. + */ +typedef enum +{ + SYSCFG_FSMCPinUseMode_DataAndAddrMixed = 0u, /*!< FSMC pins can be used mixedly. */ + SYSCFG_FSMCPinUseMode_DataOnly = 1u, /*!< FSMC pins can be used for data only. */ +} SYSCFG_FSMCPinUseMode_Type; + +/*! + * @brief External interrupt port. + */ +typedef enum +{ + SYSCFG_EXTIPort_GPIOA = (0x00U), /*!< SYSCFG External Interrupt GPIOA. */ + SYSCFG_EXTIPort_GPIOB = (0x01U), /*!< SYSCFG External Interrupt GPIOB. */ + SYSCFG_EXTIPort_GPIOC = (0x02U), /*!< SYSCFG External Interrupt GPIOC. */ + SYSCFG_EXTIPort_GPIOD = (0x03U), /*!< SYSCFG External Interrupt GPIOD. */ + SYSCFG_EXTIPort_GPIOE = (0x04U), /*!< SYSCFG External Interrupt GPIOE. */ + SYSCFG_EXTIPort_GPIOF = (0x05U), /*!< SYSCFG External Interrupt GPIOF. */ +} SYSCFG_EXTIPort_Type; + +/*! + * @brief External interrupt line. + */ +typedef enum +{ + SYSCFG_EXTILine_0 = (0x00U), /*!< Pin 0 selected. */ + SYSCFG_EXTILine_1 = (0x01U), /*!< Pin 1 selected. */ + SYSCFG_EXTILine_2 = (0x02U), /*!< Pin 2 selected. */ + SYSCFG_EXTILine_3 = (0x03U), /*!< Pin 3 selected. */ + SYSCFG_EXTILine_4 = (0x04U), /*!< Pin 4 selected. */ + SYSCFG_EXTILine_5 = (0x05U), /*!< Pin 5 selected. */ + SYSCFG_EXTILine_6 = (0x06U), /*!< Pin 6 selected. */ + SYSCFG_EXTILine_7 = (0x07U), /*!< Pin 7 selected. */ + SYSCFG_EXTILine_8 = (0x08U), /*!< Pin 8 selected. */ + SYSCFG_EXTILine_9 = (0x09U), /*!< Pin 9 selected. */ + SYSCFG_EXTILine_10 = (0x0AU), /*!< Pin 10 selected. */ + SYSCFG_EXTILine_11 = (0x0BU), /*!< Pin 11 selected. */ + SYSCFG_EXTILine_12 = (0x0CU), /*!< Pin 12 selected. */ + SYSCFG_EXTILine_13 = (0x0DU), /*!< Pin 13 selected. */ + SYSCFG_EXTILine_14 = (0x0EU), /*!< Pin 14 selected. */ + SYSCFG_EXTILine_15 = (0x0FU), /*!< Pin 15 selected. */ +} SYSCFG_EXTILine_Type; + +/*! + * @brief I2C port mode. + */ +typedef enum +{ + SYSCFG_I2CPortMode_OpenDrain = 0u, /*!< I2C output open-drain mode. */ + SYSCFG_I2CPortMode_PushPull = 1u, /*!< I2C output push-pull mode. */ +} SYSCFG_I2CPortMode_Type; + +/*! + * @brief Ethernet port mode. + */ +typedef enum +{ + SYSCFG_ENETPortMode_MII = 0u, /*!< Ethernet connect on MMI port. */ + SYSCFG_ENETPortMode_RMII = 1u, /*!< Ethernet connect on RMMI port. */ +} SYSCFG_ENETPortMode_Type; + +/*! + * @brief Ethernet speed mode. + */ +typedef enum +{ + SYSCFG_ENETSpeedMode_10Mb = 0u, /*!< Ethernet speed mode of 10 Mbps. */ + SYSCFG_ENETSpeedMode_100Mb = 1u, /*!< Ethernet speed mode of 100 Mbps. */ +} SYSCFG_ENETSpeedMode_Type; + +/*! + * @brief PVD threshold. + */ +typedef enum +{ + SYSCFG_PVDThold_1v8 = 0u, /*!< PVD threshold of 1.8 v.*/ + SYSCFG_PVDThold_2v1 = 1u, /*!< PVD threshold of 2.1 v.*/ + SYSCFG_PVDThold_2v4 = 2u, /*!< PVD threshold of 2.4 v.*/ + SYSCFG_PVDThold_2v7 = 3u, /*!< PVD threshold of 2.7 v.*/ + SYSCFG_PVDThold_3v0 = 4u, /*!< PVD threshold of 3.0 v.*/ + SYSCFG_PVDThold_3v3 = 5u, /*!< PVD threshold of 3.3 v.*/ + SYSCFG_PVDThold_3v6 = 6u, /*!< PVD threshold of 3.6 v.*/ + SYSCFG_PVDThold_3v9 = 7u, /*!< PVD threshold of 3.9 v.*/ + SYSCFG_PVDThold_4v2 = 8u, /*!< PVD threshold of 4.2 v.*/ + SYSCFG_PVDThold_4v5 = 9u, /*!< PVD threshold of 4.5 v.*/ + SYSCFG_PVDThold_4v8 = 10u, /*!< PVD threshold of 4.8 v.*/ +} SYSCFG_PVDThold_Type; + +/*! + * @brief PVD output state. + */ +typedef enum +{ + SYSCFG_PVDOut_Low = 0u, /*!< PVD output low.*/ + SYSCFG_PVDOut_High = 1u, /*!< PVD output high.*/ +} SYSCFG_PVDOut_Type; + +/*! + * @brief VDT threshold alt. + */ +typedef enum +{ + SYSCFG_VDTThold_1v2 = 0u, /*!< VDT threshold of 1.2 v.*/ + SYSCFG_VDTThold_1v1 = 1u, /*!< VDT threshold of 1.1 v.*/ + SYSCFG_VDTThold_1v0 = 2u, /*!< VDT threshold of 1.0 v.*/ + SYSCFG_VDTThold_0v9 = 3u, /*!< VDT threshold of 0.9 v.*/ +} SYSCFG_VDTThold_Type; + +/*! + * @brief VDT output state. + */ +typedef enum +{ + SYSCFG_VDTOut_Low = 0u, /*!< VDT output low.*/ + SYSCFG_VDTOut_High = 1u, /*!< VDT output high.*/ +} SYSCFG_VDTOut_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref SYSCFG_EnablePVD(). + */ +typedef struct +{ + SYSCFG_PVDThold_Type Thold; /* Set the threshold of the PVD. */ + SYSCFG_PVDOut_Type Output; /* Set the output of the PVD. */ +} SYSCFG_PVDConf_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref SYSCFG_EnableVDT(). + */ +typedef struct +{ + SYSCFG_VDTThold_Type Thold; /* Set the threshold of the VDT. */ + SYSCFG_VDTOut_Type Output; /* Set the output of the VDT. */ +} SYSCFG_VDTConf_Type; + +/*! + * @brief Set boot memory mode. + * + * @param mode The memory mode. See to @ref SYSCFG_BootMemMode_Type. + * @return None. + */ +void SYSCFG_SetBootMemMode(SYSCFG_BootMemMode_Type mode); + +/*! + * @brief Set FSMC pin usage mode. + * + * @param mode FMSC pin use mode to be set. See to @ref SYSCFG_FSMCPinUseMode_Type. + * @return None. + */ +void SYSCFG_SetFSMCPinUseMode(SYSCFG_FSMCPinUseMode_Type mode); + +/*! + * @brief Set the FMSC compatible mode. + * + * @param mode The compatible mode to be set for FMSC. See to @ref SYSCFG_FSMCMode_Type. + * @return None. + */ +void SYSCFG_SetFSMCMode(SYSCFG_FSMCMode_Type mode); + +/*! + * @brief Set the external interrupt mux. + * + * @param port external interrupt port. See to @ref SYSCFG_EXTIPort_Type. + * @param line external interrupt line. See to @ref SYSCFG_EXTILine_Type. + * @return None. + */ +void SYSCFG_SetExtIntMux(SYSCFG_EXTIPort_Type port, SYSCFG_EXTILine_Type line); + +/*! + * @brief Set the I2C port 0 mode. + * + * @param mode The I2C output state to be set. See to @ref SYSCFG_I2CPortMode_Type. + * @return None. + */ +void SYSCFG_SetI2C0PortMode(SYSCFG_I2CPortMode_Type mode); + +/*! + * @brief Set the I2C port 1 mode. + * + * @param mode The I2C output state to be set. See to @ref SYSCFG_I2CPortMode_Type. + * @return None. + */ +void SYSCFG_SetI2C1PortMode(SYSCFG_I2CPortMode_Type mode); + +/*! + * @brief Set the Ethernet port mode. + * + * @param mode The Ethernet port mode. See to @ref SYSCFG_ENETPortMode_Type. + * @return None. + */ +void SYSCFG_SetENETPortMode(SYSCFG_ENETPortMode_Type mode); + +/*! + * @brief Set the Ethernet speed mode. + * + * @param mode The Ethernet speed mode. See to @ref SYSCFG_ENETSpeedMode_Type. + * @return None. + */ +void SYSCFG_SetENETSpeedMode(SYSCFG_ENETSpeedMode_Type mode); + +/*! + * @brief Enable the PVD. + * + * @param conf Pointer to the PDV configuration structure. See to @ref SYSCFG_PVDConf_Type. + * @return None. + */ +void SYSCFG_EnablePVD(SYSCFG_PVDConf_Type * conf); + +/*! + * @brief Enable the VDT. + * + * @param conf Pointer to the VDT configuration structure. See to @ref SYSCFG_VDTConf_Type. + * @return None. + */ +void SYSCFG_EnableVDT(SYSCFG_VDTConf_Type * conf); + +/*! + * @brief Enable ADC checking VBat_Div3. + * + * @param enable 'true' to enable ADC checking, 'false' to disable ADC checking. + * @return None. + */ +void SYSCFG_EnableADCCheckVBatDiv3(bool enable); + +/*! + * @brief Set the VOS delay time. + * + * @param time VOS delay time. + * @return None. + */ +void SYSCFG_SetVOSDelayValue(uint32_t val); + +/*! + * @} + */ + +#endif /* __HAL_SYSCFG_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_tim.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_tim.c new file mode 100644 index 000000000..12b2ffdc5 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_tim.c @@ -0,0 +1,462 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_tim.h" + +bool TIM_Init(TIM_Type * TIMx, TIM_Init_Type * init) +{ + uint32_t cr1 = TIMx->CR1 &~ ( TIM_CR1_OPM_MASK + | TIM_CR1_ARPE_MASK + | TIM_CR1_CMS_MASK + | TIM_CR1_DIR_MASK + ); + cr1 |= TIM_CR1_OPM(init->PeriodMode); + cr1 |= ((init->EnablePreloadPeriod) ? TIM_CR1_ARPE_MASK: 0u); + TIMx->CR1 = cr1; + + /* Check the vadility of StepFreqHz. */ + if ( (init->StepFreqHz == 0u) || (init->StepFreqHz > init->ClockFreqHz) ) + { + return false; + } + + switch (init->CountMode) + { + case TIM_CountMode_Increasing: + break; + case TIM_CountMode_Decreasing: + cr1 |= TIM_CR1_DIR_MASK; + break; + case TIM_CountMode_CenterAligned1: + cr1 |= TIM_CR1_CMS(1u); + break; + case TIM_CountMode_CenterAligned2: + cr1 |= TIM_CR1_CMS(2u); + break; + case TIM_CountMode_CenterAligned3: + cr1 |= TIM_CR1_CMS(3u); + break; + default: + break; + } + + /* Calculate the prescaler. */ + TIMx->PSC = init->ClockFreqHz / init->StepFreqHz - 1u; + TIMx->ARR = init->Period; + return true; +} + +void TIM_Start(TIM_Type * TIMx) +{ + TIMx->CR1 |= TIM_CR1_CEN_MASK; +} + +void TIM_Stop(TIM_Type * TIMx) +{ + TIMx->CR1 &= ~TIM_CR1_CEN_MASK; +} + +uint32_t TIM_GetCounterValue(TIM_Type * TIMx) +{ + return TIMx->CNT; +} + +void TIM_ClearCounterValue(TIM_Type * TIMx) +{ + TIMx->CNT = 0u; +} + +void TIM_EnableInterrupts(TIM_Type * TIMx, uint32_t interrupts, bool enable) +{ + if (enable) + { + TIMx->DIER |= interrupts; + } + else + { + TIMx->DIER &= ~interrupts; + } +} + +void TIM_EnableDMA(TIM_Type * TIMx, uint32_t dmas, bool enable) +{ + if (enable) + { + TIMx->DIER |= dmas; + } + else + { + TIMx->DIER &= ~dmas; + } +} + +void TIM_DoSwTrigger(TIM_Type * TIMx, uint32_t swtrgs) +{ + TIMx->EGR = swtrgs; +} + +uint32_t TIM_GetInterruptStatus(TIM_Type * TIMx) +{ + return TIMx->SR; +} + +void TIM_ClearInterruptStatus(TIM_Type * TIMx, uint32_t status) +{ + TIMx->SR &= ~status; +} + +/*******************************/ +static void _TIM_WriteChannelCtrlReg(TIM_Type * TIMx, uint32_t channel, uint32_t regval) +{ + switch (channel) + { + case TIM_CHN_1: + TIMx->CCMR1 = (TIMx->CCMR1 & ~(0xFF)) | (regval & 0xFF); + break; + case TIM_CHN_2: + TIMx->CCMR1 = (TIMx->CCMR1 & ~(0xFF00)) | ((regval & 0xFF) << 8u); + break; + case TIM_CHN_3: + TIMx->CCMR2 = (TIMx->CCMR2 & ~(0xFF)) | (regval & 0xFF); + break; + case TIM_CHN_4: + TIMx->CCMR2 = (TIMx->CCMR2 & ~(0xFF00)) | ((regval & 0xFF) << 8u); + break; + case TIM_CHN_5: + TIMx->CCMR3 = (TIMx->CCMR2 & ~(0xFF)) | (regval & 0xFF); + break; + default: + break; + } +} + +void TIM_EnableOutputCompare(TIM_Type * TIMx, uint32_t channel, TIM_OutputCompareConf_Type * conf) +{ + uint32_t regval = TIM_CCMR1_CC1S(TIM_ChannelIOMode_Out) /* output compare mode. */ + | ( (conf->EnableFastOutput) ? TIM_CCMR1_OC1FE_MASK : 0u ) /* fast output. */ + | ( (conf->EnablePreLoadChannelValue) ? TIM_CCMR1_OC1PE_MASK : 0u) /* preload of channel value. */ + | TIM_CCMR1_OC1M(conf->RefOutMode) /* output compare comparison mode. */ + | ( (conf->ClearRefOutOnExtTrigger) ? TIM_CCMR1_OC1CE_MASK : 0u) /* external trigger clear ref. */ + ; + + _TIM_WriteChannelCtrlReg(TIMx, channel, regval); + + TIM_PutChannelValue(TIMx, channel, conf->ChannelValue); + + switch (conf->PinPolarity) + { + case TIM_PinPolarity_Disabled: + TIMx->CCER &= ~( ( TIM_CCER_CC1E_MASK + | TIM_CCER_CC1NE_MASK + ) << (channel<<2u) ); /* Disable both channel. */ + break; + + case TIM_PinPolarity_Rising: + TIMx->CCER = ( ( TIMx->CCER & ~(0xF << (channel<<2u)) ) + | ( ( TIM_CCER_CC1E_MASK ) /* Enable the pin output / input. */ + ) << (channel<<2u)); + break; + + case TIM_PinPolarity_Falling: + TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) ) + | (( TIM_CCER_CC1E_MASK /* Enable the pin output / input. */ + | TIM_CCER_CC1P_MASK /* Set output active polarity. */ + ) << (channel<<2u)); + break; + + default: + break; + } + +} + +void TIM_EnableCompOutput(TIM_Type * TIMx, uint32_t channel, bool enable) +{ + if (enable) + { + switch (channel) + { + case TIM_CHN_1: + TIMx->CCER |= TIM_CCER_CC1NE_MASK; + break; + case TIM_CHN_2: + TIMx->CCER |= TIM_CCER_CC2NE_MASK; + break; + case TIM_CHN_3: + TIMx->CCER |= TIM_CCER_CC3NE_MASK; + break; + case TIM_CHN_4: + TIMx->CCER |= TIM_CCER_CC4NE_MASK; + break; + default: + break; + } + } + else + { + switch (channel) + { + case TIM_CHN_1: + TIMx->CCER &= ~ TIM_CCER_CC1NE_MASK; + break; + case TIM_CHN_2: + TIMx->CCER &= ~ TIM_CCER_CC2NE_MASK; + break; + case TIM_CHN_3: + TIMx->CCER &= ~ TIM_CCER_CC3NE_MASK; + break; + case TIM_CHN_4: + TIMx->CCER &= ~ TIM_CCER_CC4NE_MASK; + break; + default: + break; + } + } +} + +/* for some TIM instance, there is an additional switch to let the output signal go. + * in this case, the output is disabled by default. then, only the switch is enabled, the output signal can go. + */ +void TIM_EnableOutputCompareSwitch(TIM_Type * TIMx, bool enable) +{ + if (enable) + { + TIMx->BDTR |= TIM_BDTR_MOE_MASK; + } + else + { + TIMx->BDTR &= ~ TIM_BDTR_MOE_MASK; + } +} + +void TIM_EnableInputCapture(TIM_Type * TIMx, uint32_t channel, TIM_InputCaptureConf_Type * conf) +{ + uint32_t regval = TIM_CCMR1_CC1S(TIM_ChannelIOMode_In) /* input capture mode. */ + | TIM_CCMR1_IC1PSC(conf->InDiv) + | TIM_CCMR1_IC1F(conf->InFilter) + ; + + _TIM_WriteChannelCtrlReg(TIMx, channel, regval); + + switch (conf->PinPolarity) + { + case TIM_PinPolarity_Disabled: + TIMx->CCER &= ~(TIM_CCER_CC1E_MASK << (channel<<2u)); + break; + case TIM_PinPolarity_Rising: + TIMx->CCER = (TIMx->CCER & ~(0xF << (channel<<2u)) ) + | (( TIM_CCER_CC1E_MASK /* Enable the pin output / input */ + ) << (channel<<2u) ); + break; + case TIM_PinPolarity_Falling: + TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) ) + | (( TIM_CCER_CC1E_MASK /* Enable the pin output / input */ + | TIM_CCER_CC1P_MASK /* Set active input edge. */ + ) << (channel<<2u) ); + break; + case TIM_PinPolarity_RisingOrFalling: + TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) ) + | (( TIM_CCER_CC1E_MASK /* Enable the pin output / input */ + | TIM_CCER_CC1P_MASK /* Set active input edge. */ + | TIM_CCER_CC1NP_MASK + ) << (channel<<2u) ); + break; + default: + break; + } +} + +uint32_t TIM_GetChannelValue(TIM_Type * TIMx, uint32_t channel) +{ + return TIMx->CCR[channel]; +} + +void TIM_PutChannelValue(TIM_Type * TIMx, uint32_t channel, uint32_t value) +{ + if ( channel == TIM_CHN_5 ) + { + TIMx->CCR5 = value; + } + else + { + TIMx->CCR[channel] = value; + } +} + +void TIM_SetClockDiv(TIM_Type * TIMx, TIM_ClockDiv_Type div) +{ + TIMx->CR1 = ( TIMx->CR1 &~ TIM_CR1_CKD_MASK ) + | ( TIM_CR1_CKD(div) ); /* set the frequncy ratio. */ +} + +void TIM_EnableDeadPeriod(TIM_Type * TIMx, TIM_DeadPeriodConf_Type * conf) +{ + TIMx->BDTR = ( TIMx->BDTR &~ TIM_BDTR_DTG_MASK ) + | ( TIM_BDTR_DTG(conf->DeadPeriodCoef) ); /* set the coefficient. */ +} + +void TIM_EnableMasterMode(TIM_Type * TIMx, TIM_MasterModeConf_Type * conf) +{ + TIMx->CR2 = ( TIMx->CR2 &~ TIM_CR2_MMS_MASK ) + | ( TIM_CR2_MMS(conf->Out) ); /* Set master mode output. */ + + uint32_t smcr = TIMx->SMCR &~ TIM_SMCR_MSM_MASK; + if (conf->EnableSync) /* synchronize with slave timers. */ + { + smcr |= TIM_SMCR_MSM_MASK; + } + TIMx->SMCR = smcr; +} + +void TIM_EnableSlaveMode(TIM_Type * TIMx, TIM_SlaveModeConf_Type * conf) +{ + if ( conf->Resp != TIM_SlaveResp_Disabled ) + { + TIMx->SMCR = ( TIMx->SMCR &~ ( TIM_SMCR_TS_MASK + | TIM_SMCR_SMS_MASK + ) ) + | TIM_SMCR_TS(conf->In) /* set input trigger source. */ + | TIM_SMCR_SMS(conf->Resp); /* set response to the source */ + } + else + { + TIMx->SMCR &= ~ TIM_SMCR_SMS_MASK; + } +} + +void TIM_EnableExtTriggerIn(TIM_Type * TIMx, TIM_ExtTriggerInConf_Type * conf) +{ + uint32_t smcr = TIMx->SMCR &~ ( TIM_SMCR_ETPS_MASK + | TIM_SMCR_ETF_MASK + | TIM_SMCR_ECE_MASK + | TIM_SMCR_ETP_MASK + ); + switch (conf->PinPolarity) + { + case TIM_PinPolarity_Disabled: + break; + case TIM_PinPolarity_Rising: + smcr |= TIM_SMCR_ECE_MASK; /* enable external trigger input. */ + break; + case TIM_PinPolarity_Falling: + smcr |= TIM_SMCR_ETP_MASK; /* falling edge active. */ + smcr |= TIM_SMCR_ECE_MASK; /* enable external trigger input. */ + break; + default: + break; + } + smcr |= TIM_SMCR_ETPS( conf->InDiv ); /* division to the input external trigger. */ + smcr |= TIM_SMCR_ETF( conf->InFilter ); /* set filter. */ + TIMx->SMCR = smcr; +} + +uint32_t TIM_EnableDMABurst(TIM_Type * TIMx, TIM_DMABurstConf_Type * conf) +{ + TIMx->DCR = TIM_DCR_DBA(conf->BaseAddr) | TIM_DCR_DBL(conf->Length); + return (uint32_t)(&(TIMx->DMAR)); +} + +TIM_EncoderDirection_Type TIM_GetEncoder(TIM_Type * TIMx, uint32_t * value) +{ + if (value) + { + * value = TIM_GetCounterValue(TIMx); + } + + if ( (TIMx->CR1 & TIM_CR1_DIR_MASK) != 0u ) + { + return TIM_EncoderDirection_Backward; + } + else + { + return TIM_EncoderDirection_Forward; + } +} + +void TIM_SetRepCounter(TIM_Type * TIMx, uint8_t value) +{ + TIMx->RCR = TIM_RCR_REP(value); +} + +uint8_t TIM_GetRepCounterValue(TIM_Type * TIMx) +{ + return TIMx->RCR >> TIM_RCR_REPCNT_SHIFT; +} + +void TIM_EnableIdleOut(TIM_Type * TIMx, uint32_t channel, TIM_IdleOut_Type * conf) +{ + uint32_t cr2 = TIMx->CR2 & ~ ( ( TIM_CR2_OIS1_MASK + | TIM_CR2_OIS1N_MASK + ) << ( channel << 1u ) + ); + if ( conf->PinPolarity == TIM_PinPolarity_Rising ) + { + cr2 |= ( TIM_CR2_OIS1_MASK << ( channel << 1u ) ); + } + if ( conf->CompPinPolarity == TIM_PinPolarity_Rising ) + { + cr2 |= ( TIM_CR2_OIS1N_MASK << ( channel << 1u ) ); + } + TIMx->CR2 = cr2; +} + +void TIM_EnableLock(TIM_Type * TIMx, TIM_LockLevel_Type lock) +{ + TIMx->BDTR = ( TIMx->BDTR & ~ TIM_BDTR_LOCK_MASK ) + | TIM_BDTR_LOCK(lock); +} + +void TIM_EnableBreakIn(TIM_Type * TIMx, TIM_BreakIn_Type * conf) +{ + uint32_t bdtr = TIMx->BDTR &~ ( TIM_BDTR_BKE_MASK + | TIM_BDTR_BKP_MASK + | TIM_BDTR_AOE_MASK + | TIM_BDTR_DOE_MASK + ); + uint32_t bkinf = 0u; + switch (conf->PinPolarity) + { + case TIM_PinPolarity_Disabled: + break; + case TIM_PinPolarity_Rising: + bdtr |= ( TIM_BDTR_BKE_MASK + | TIM_BDTR_BKP_MASK + | ( conf->AutoSwitchOutput ? TIM_BDTR_AOE_MASK : 0u ) + | ( conf->DirectIdleOutput ? TIM_BDTR_DOE_MASK : 0u ) + ); + break; + case TIM_PinPolarity_Falling: + bdtr |= ( TIM_BDTR_BKE_MASK + | ( conf->AutoSwitchOutput ? TIM_BDTR_AOE_MASK : 0u ) + | ( conf->DirectIdleOutput ? TIM_BDTR_DOE_MASK : 0u ) + ); + break; + default: + break; + } + if ( conf->Filter != TIM_BreakInFilter_Disabled ) + { + bkinf |= ( TIM_BKINF_BKINFE_MASK | TIM_BKINF_BKINF(conf->Filter) ); + } + bkinf |= conf->Source; + TIMx->BKINF = bkinf; +} + +void TIM_EnablePWMShift(TIM_Type * TIMx, uint32_t channel, uint16_t value) +{ + if ( value == TIM_GetChannelValue(TIMx, channel) ) + { + TIMx->PDER &= ~( TIM_PDER_CCR1SHIFTEN_MASK << channel ); + } + else + { + TIMx->PDER |= ( TIM_PDER_CCR1SHIFTEN_MASK << channel ); + TIMx->CCRFALL[channel] = value; + } +} + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_tim.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_tim.h new file mode 100644 index 000000000..53394964e --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_tim.h @@ -0,0 +1,829 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_TIM_H__ +#define __HAL_TIM_H__ + +#include "hal_common.h" + +/*! + * @addtogroup TIM + * @{ + */ + +/*! + * @brief TIM driver version number. + */ +#define TIM_DRIVER_VERSION 1u /*!< TIM_1. */ + +/*! + * @addtogroup TIM_CHANNEL_SELECTION + * @{ + */ +#define TIM_CHN_NUM (5u) /*!< The total number of TIM channel. */ +#define TIM_CHN_1 (0u) /*!< The selection of TIM Channel 1. */ +#define TIM_CHN_2 (1u) /*!< The selection of TIM Channel 2. */ +#define TIM_CHN_3 (2u) /*!< The selection of TIM Channel 3. */ +#define TIM_CHN_4 (3u) /*!< The selection of TIM Channel 4. */ +#define TIM_CHN_5 (4u) /*!< The selection of TIM Channel 5. */ +/*! + *@} + */ + +/*! + * @addtogroup TIM_INT + * @brief Enable interrupt. + * @{ + */ +#define TIM_INT_UPDATE_PERIOD (1u << 0u) /*!< Timer update period interrupt switchers. */ +#define TIM_INT_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture interrupt switchers. */ +#define TIM_INT_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture interrupt switchers. */ +#define TIM_INT_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture interrupt switchers. */ +#define TIM_INT_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture interrupt switchers. */ +#define TIM_INT_COMP_EVENT (1u << 5u) /*!< Channel complementary pwm commutation interrupt switchers. */ +#define TIM_INT_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event interrupt switchers. */ +#define TIM_INT_BREAK_EVENT (1u << 7u) /*!< Break event interrupt switchers. */ +#define TIM_INT_CHN5_EVENT (1u << 16u) /*!< Channel 5 event for output compare or input capture interrupt switchers. */ +/*! + * @} + */ + +/*! + * @addtogroup TIM_DMA + * @brief Enable DMA. + * @{ + */ +#define TIM_DMA_UPDATE_PERIOD (1u << 8u) /*!< Timer update period DMA switchers. */ +#define TIM_DMA_CHN1_EVENT (1u << 9u) /*!< Channel 1 event for output compare or input capture DMA switchers. */ +#define TIM_DMA_CHN2_EVENT (1u << 10u) /*!< Channel 2 event for output compare or input capture DMA switchers. */ +#define TIM_DMA_CHN3_EVENT (1u << 11u) /*!< Channel 3 event for output compare or input capture DMA switchers. */ +#define TIM_DMA_CHN4_EVENT (1u << 12u) /*!< Channel 4 event for output compare or input capture DMA switchers. */ +#define TIM_DMA_COMP_EVENT (1u << 13u) /*!< Channel complementary pwm commutation interrupt switchers. */ +#define TIM_DMA_TRGOUT_EVENT (1u << 14u) /*!< Trigger out event DMA switchers. */ +#define TIM_DMA_CHN5_EVENT (1u << 17u) /*!< Channel 5 event for output compare or input capture DMA switchers. */ +/*! + * @} + */ + +/*! + * @addtogroup TIM_INT_STATUS + * @brief Check interrupt status. + * @{ + */ +#define TIM_STATUS_UPDATE_PERIOD (1u << 0u) /*!< Timer update period interrupt flag. */ +#define TIM_STATUS_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture interrupt flag. */ +#define TIM_STATUS_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture interrupt flag. */ +#define TIM_STATUS_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture interrupt flag. */ +#define TIM_STATUS_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture interrupt flag. */ +#define TIM_STATUS_COMP_EVENT (1u << 5u) /*!< Channel complementary pwm commutation interrupt flag. */ +#define TIM_STATUS_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event interrupt flag. */ +#define TIM_STATUS_BREAK_EVENT (1u << 7u) /*!< Break event interrupt flag. */ +#define TIM_STATUS_CHN1_OVER_EVENT (1u << 9u) /*!< Channel 1 event for output overcompare or input overcapture interrupt flag. */ +#define TIM_STATUS_CHN2_OVER_EVENT (1u << 10u) /*!< Channel 2 event for output overcompare or input overcapture interrupt flag. */ +#define TIM_STATUS_CHN3_OVER_EVENT (1u << 11u) /*!< Channel 3 event for output overcompare or input overcapture interrupt flag. */ +#define TIM_STATUS_CHN4_OVER_EVENT (1u << 12u) /*!< Channel 4 event for output overcompare or input overcapture interrupt flag. */ +#define TIM_STATUS_CHN5_EVENT (1u << 16u) /*!< Channel 5 event for output compare or input capture interrupt flag. */ +/*! + * @} + */ + +/*! + * @addtogroup TIM_SWTRG + * @brief Events to be triggered by software. + * @{ + */ +#define TIM_SWTRG_UPDATE_PERIOD (1u << 0u) /*!< Timer update period software trigger. */ +#define TIM_SWTRG_CHN1_EVENT (1u << 1u) /*!< Channel 1 event for output compare or input capture software trigger. */ +#define TIM_SWTRG_CHN2_EVENT (1u << 2u) /*!< Channel 2 event for output compare or input capture software trigger. */ +#define TIM_SWTRG_CHN3_EVENT (1u << 3u) /*!< Channel 3 event for output compare or input capture software trigger. */ +#define TIM_SWTRG_CHN4_EVENT (1u << 4u) /*!< Channel 4 event for output compare or input capture software trigger. */ +#define TIM_SWTRG_COMP_EVENT (1u << 5u) /*!< Channel complementary pwm commutation software trigger. */ +#define TIM_SWTRG_TRGOUT_EVENT (1u << 6u) /*!< Trigger out event software trigger. */ +#define TIM_SWTRG_BREAK_EVENT (1u << 7u) /*!< Break event software trigger. */ +#define TIM_SWTRG_CHN5_EVENT (1u << 16u) /*!< Channel 5 event for output compare or input capture software trigger. */ +/*! + * @} + */ + +/*! + * @addtogroup TIM_BKEAK_IN + * @brief Enable interrupt. + * @{ + */ +#define TIM_BKEAK_IN_MASK0 (1u << 5u) /*!< TIM ADV break in source mask 0. */ +#define TIM_BKEAK_IN_MASK1 (1u << 6u) /*!< TIM ADV break in source mask 1. */ +#define TIM_BKEAK_IN_MASK2 (1u << 7u) /*!< TIM ADV break in source mask 2. */ +#define TIM_BKEAK_IN_MASK3 (1u << 8u) /*!< TIM ADV break in source mask 3. */ +#define TIM_BKEAK_IN_MASK4 (1u << 9u) /*!< TIM ADV break in source mask 4. */ +#define TIM_BKEAK_IN_MASK5 (1u << 10u) /*!< TIM ADV break in source mask 5. */ +#define TIM_BKEAK_IN_MASK6 (1u << 11u) /*!< TIM ADV break in source mask 6. */ +#define TIM_BKEAK_IN_MASK7 (1u << 13u) /*!< TIM ADV break in source mask 7. */ +#define TIM_BKEAK_IN_MASK8 (1u << 13u) /*!< TIM ADV break in source mask 8. */ +#define TIM_BKEAK_IN_MASK9 (1u << 14u) /*!< TIM ADV break in source mask 9. */ +#define TIM_BKEAK_IN_MASK10 (1u << 15u) /*!< TIM ADV break in source mask 10. */ +#define TIM_BKEAK_IN_MASK11 (1u << 16u) /*!< TIM ADV break in source mask 11. */ +/*! + * @} + */ + +/*! + * @brief Counter period working mode. + */ +typedef enum +{ + TIM_PeriodMode_Continuous = 0u, /*!< Counter works circularly once started. */ + TIM_PeriodMode_OneTimeRun = 1u, /*!< Counter only works one time once started. */ +} TIM_PeriodMode_Type; + +/*! + * @brief Counter count direction. + */ +typedef enum +{ + TIM_CountMode_Increasing = 0u, /*!< Counter counts incrementally from 0 to period and generates an update. */ + TIM_CountMode_Decreasing = 1u, /*!< Counter counts decrementally from period to 0 and generates an update. */ + TIM_CountMode_CenterAligned1 = 2u, /*!< Counter counts center-aligned from 0 to period - 1 then from period to 0 and generates an update. */ + TIM_CountMode_CenterAligned2 = 3u, /*!< Counter counts center-aligned from 0 to period - 1 and generates an update then from period to 0. */ + TIM_CountMode_CenterAligned3 = 4u, /*!< Counter counts center-aligned from 0 to period - 1 and generates an update then from period to 0 and generates another update. */ +} TIM_CountMode_Type; + +/*! + * @brief TIM output compare reference polairty event. + */ +typedef enum +{ + TIM_OutputCompareRefOut_None = 0u, /*!< Reference will not be changed. */ + TIM_OutputCompareRefOut_HighOnMatch = 1u, /*!< Reference will be high when counter value equals channel value. */ + TIM_OutputCompareRefOut_LowOnMatch = 2u, /*!< Reference will be low when counter value equals channel value. */ + TIM_OutputCompareRefOut_ToggleOnMatch = 3u, /*!< Reference will toggle. */ + TIM_OutputCompareRefOut_LowAlways = 4u, /*!< Reference will always be low. */ + TIM_OutputCompareRefOut_HighAlways = 5u, /*!< Reference will always be high. */ + TIM_OutputCompareRefOut_FallingEdgeOnMatch = 6u, /*!< PWM mode 1. */ + TIM_OutputCompareRefOut_RisingEdgeOnMatch = 7u, /*!< PWM mode 2. */ +} TIM_OutputCompareRefOut_Type; + +/*! + * @brief TIM input capture active edge selection and output compare active polarity selection. + * | conf | TIM_PinPolarity_Rising | TIM_PinPolarity_Falling | + * | ----------------------- | -------------------------- | --------------------------- | + * | input capture | detects rising edge | detects falling edge | + * | output compare | high polarity is active | low polarity is active | + * | encoder mode | input remains | input reverses | + * | output under idle state | output high polarity | output low polarity | + */ +typedef enum +{ + TIM_PinPolarity_Disabled = 0u, /*!< Disable channel. */ + TIM_PinPolarity_Rising = 1u, /*!< See the table above. */ + TIM_PinPolarity_Falling = 2u, /*!< See the table above.*/ + TIM_PinPolarity_RisingOrFalling = 3u, /*!< For input capture, detect both the rising and falling edge. */ +}TIM_PinPolarity_Type; + +/*! + * @brief TIM Input active times to evoke capture. + */ +typedef enum +{ + TIM_InputCaptureInDiv_OnEach1Capture = 0u, /*!< Every input call capture. */ + TIM_InputCaptureInDiv_OnEach2Capture = 1u, /*!< Every two input call capture. */ + TIM_InputCaptureInDiv_OnEach4Capture = 2u, /*!< Every four input call capture. */ + TIM_InputCaptureInDiv_OnEach8Capture = 3u, /*!< Every eight input call capture. */ +} TIM_InputCaptureInDiv_Type; + +/*! + * @brief TIM Input sampling filter. + */ +typedef enum +{ + TIM_InputCaptureInFilter_Alt0 = 0u, /*!< Filter swicther 0. */ + TIM_InputCaptureInFilter_Alt1 = 1u, /*!< Filter swicther 1. */ + TIM_InputCaptureInFilter_Alt2 = 2u, /*!< Filter swicther 2. */ + TIM_InputCaptureInFilter_Alt3 = 3u, /*!< Filter swicther 3. */ + TIM_InputCaptureInFilter_Alt4 = 4u, /*!< Filter swicther 4. */ + TIM_InputCaptureInFilter_Alt5 = 5u, /*!< Filter swicther 5. */ + TIM_InputCaptureInFilter_Alt6 = 6u, /*!< Filter swicther 6. */ + TIM_InputCaptureInFilter_Alt7 = 7u, /*!< Filter swicther 7. */ + TIM_InputCaptureInFilter_Alt8 = 8u, /*!< Filter swicther 8. */ + TIM_InputCaptureInFilter_Alt9 = 9u, /*!< Filter swicther 9. */ + TIM_InputCaptureInFilter_Alt10 = 10u, /*!< Filter swicther 10. */ + TIM_InputCaptureInFilter_Alt11 = 11u, /*!< Filter swicther 11. */ + TIM_InputCaptureInFilter_Alt12 = 12u, /*!< Filter swicther 12. */ + TIM_InputCaptureInFilter_Alt13 = 13u, /*!< Filter swicther 13. */ + TIM_InputCaptureInFilter_Alt14 = 14u, /*!< Filter swicther 14. */ + TIM_InputCaptureInFilter_Alt15 = 15u, /*!< Filter swicther 15. */ +} TIM_InputCaptureInFilter_Type; + +/*! + * @brief TIM channel IO mode. + */ +typedef enum +{ + TIM_ChannelIOMode_Alt0 = 0u, /*!< Channel output. */ + TIM_ChannelIOMode_Alt1 = 1u, /*!< Channel input, capture signal from direct channel. */ + TIM_ChannelIOMode_Alt2 = 2u, /*!< Channel input, capture signal from indirect channel. */ + TIM_ChannelIOMode_Alt3 = 3u, /*!< Channel input, capture signal from trc. */ + + TIM_ChannelIOMode_Out = TIM_ChannelIOMode_Alt0, /*!< Channel output. */ + TIM_ChannelIOMode_In = TIM_ChannelIOMode_Alt1, /*!< Channel input, capture signal from direct channel. */ +} TIM_ChannelIOMode_Type; + +/*! + * @brief TIM external trigger input active edge selection. + */ +typedef enum +{ + TIM_ExtTriggerPinPolarity_Disabled = 0u, /*!< Disable external trigger input. */ + TIM_ExtTriggerPinPolarity_Rising = 1u, /*!< Detect the rising edge from external trigger. */ + TIM_ExtTriggerPinPolarity_Falling = 2u, /*!< Detect the falling edge from external trigger. */ +}TIM_ExtTriggerPinPolarity_Type; + +/*! + * @brief TIM external trigger active input times to drive counter. + */ +typedef enum +{ + TIM_ExtTriggerInDiv_OnEach1Capture = 0u, /*!< Every input call capture. */ + TIM_ExtTriggerInDiv_OnEach2Capture = 1u, /*!< Every two input call capture. */ + TIM_ExtTriggerInDiv_OnEach4Capture = 2u, /*!< Every four input call capture. */ + TIM_ExtTriggerInDiv_OnEach8Capture = 3u, /*!< Every eight input call capture. */ +} TIM_ExtTriggerInDiv_Type; + +/*! + * @brief TIM external trigger sampling filter. + */ +typedef enum +{ + TIM_ExtTriggerInFilter_Alt0 = 0u, /*!< Filter swicther 0. */ + TIM_ExtTriggerInFilter_Alt1 = 1u, /*!< Filter swicther 1. */ + TIM_ExtTriggerInFilter_Alt2 = 2u, /*!< Filter swicther 2. */ + TIM_ExtTriggerInFilter_Alt3 = 3u, /*!< Filter swicther 3. */ + TIM_ExtTriggerInFilter_Alt4 = 4u, /*!< Filter swicther 4. */ + TIM_ExtTriggerInFilter_Alt5 = 5u, /*!< Filter swicther 5. */ + TIM_ExtTriggerInFilter_Alt6 = 6u, /*!< Filter swicther 6. */ + TIM_ExtTriggerInFilter_Alt7 = 7u, /*!< Filter swicther 7. */ + TIM_ExtTriggerInFilter_Alt8 = 8u, /*!< Filter swicther 8. */ + TIM_ExtTriggerInFilter_Alt9 = 9u, /*!< Filter swicther 9. */ + TIM_ExtTriggerInFilter_Alt10 = 10u, /*!< Filter swicther 10. */ + TIM_ExtTriggerInFilter_Alt11 = 11u, /*!< Filter swicther 11. */ + TIM_ExtTriggerInFilter_Alt12 = 12u, /*!< Filter swicther 12. */ + TIM_ExtTriggerInFilter_Alt13 = 13u, /*!< Filter swicther 13. */ + TIM_ExtTriggerInFilter_Alt14 = 14u, /*!< Filter swicther 14. */ + TIM_ExtTriggerInFilter_Alt15 = 15u, /*!< Filter swicther 15. */ +} TIM_ExtTriggerInFilter_Type; + +/*! + * @brief TIM Dead area / ETR / TI time step length during sampling. + */ +typedef enum +{ + TIM_ClockDiv_Alt0 = 0u, /*!< Dead area / ETR / TI step = clock source step. */ + TIM_ClockDiv_Alt1 = 1u, /*!< Dead area / ETR / TI step = 2 * clock source step. */ + TIM_ClockDiv_Alt2 = 2u, /*!< Dead area / ETR / TI step = 4 * clock source step. */ +} TIM_ClockDiv_Type; + +/*! + * @brief TIM master mode output signal source. + */ +typedef enum +{ + TIM_MasterOut_Alt0 = 0u, /*!< Software update period trigger signal works as master output. */ + TIM_MasterOut_Alt1 = 1u, /*!< Counter enable signal works as master output. */ + TIM_MasterOut_Alt2 = 2u, /*!< Update period event works as master output. */ + TIM_MasterOut_Alt3 = 3u, /*!< Channel capture or compare event works as master output. */ + TIM_MasterOut_Alt4 = 4u, /*!< Reference signal of channel 1 works as master output. */ + TIM_MasterOut_Alt5 = 5u, /*!< Reference signal of channel 2 works as master output. */ + TIM_MasterOut_Alt6 = 6u, /*!< Reference signal of channel 3 works as master output. */ + TIM_MasterOut_Alt7 = 7u, /*!< Reference signal of channel 4 works as master output. */ +} TIM_MasterOut_Type; + +/*! + * @brief TIM slave mode input object source. + */ +typedef enum +{ + TIM_SlaveIn_Alt0 = 0u, /*!< Internal trigger 0. */ + TIM_SlaveIn_Alt1 = 1u, /*!< Internal trigger 1. */ + TIM_SlaveIn_Alt2 = 2u, /*!< Internal trigger 2.*/ + TIM_SlaveIn_Alt3 = 3u, /*!< Internal trigger 3. */ + TIM_SlaveIn_Alt4 = 4u, /*!< Edge detector of timer input channel 1. */ + TIM_SlaveIn_Alt5 = 5u, /*!< Timer input channel 1. */ + TIM_SlaveIn_Alt6 = 6u, /*!< Timer input channel 2. */ + TIM_SlaveIn_Alt7 = 7u, /*!< External trigger input. */ +} TIM_SlaveIn_Type; + +/*! + * @brief TIM slave mode counter response. + */ +typedef enum +{ + TIM_SlaveResp_Disabled = 0u, /*!< Disable the slave mode. */ + TIM_SlaveResp_Alt1 = 1u, /*!< Counting in encoder mode 1. */ + TIM_SlaveResp_Alt2 = 2u, /*!< Counting in encoder mode 2.*/ + TIM_SlaveResp_Alt3 = 3u, /*!< Counting in encoder mode 3. */ + TIM_SlaveResp_Alt4 = 4u, /*!< Reset counter. */ + TIM_SlaveResp_Alt5 = 5u, /*!< Counter treat the signal as a gate. */ + TIM_SlaveResp_Alt6 = 6u, /*!< Start the counter. */ + TIM_SlaveResp_Alt7 = 7u, /*!< Counter counts on rising edges. */ +} TIM_SlaveResp_Type; + +/*! + * @brief TIM DMA Burst transfer base address. + */ +typedef enum +{ + TIM_DMABurstBaseAddr_Alt0 = 0u, /*!< Start from CR1 register. */ + TIM_DMABurstBaseAddr_Alt1 = 1u, /*!< Start from CR2 register. */ + TIM_DMABurstBaseAddr_Alt2 = 2u, /*!< Start from SMCR register. */ + TIM_DMABurstBaseAddr_Alt3 = 3u, /*!< Start from DIER register. */ + TIM_DMABurstBaseAddr_Alt4 = 4u, /*!< Start from SR register. */ + TIM_DMABurstBaseAddr_Alt5 = 5u, /*!< Start from EGR register. */ + TIM_DMABurstBaseAddr_Alt6 = 6u, /*!< Start from CCMR1 register. */ + TIM_DMABurstBaseAddr_Alt7 = 7u, /*!< Start from CCMR2 register. */ + TIM_DMABurstBaseAddr_Alt8 = 8u, /*!< Start from CCER register. */ + TIM_DMABurstBaseAddr_Alt9 = 9u, /*!< Start from CNT register. */ + TIM_DMABurstBaseAddr_Alt10 = 10u, /*!< Start from PSC register. */ + TIM_DMABurstBaseAddr_Alt11 = 11u, /*!< Start from ARR register. */ + TIM_DMABurstBaseAddr_Alt12 = 12u, /*!< Start from CCR1 register. */ + TIM_DMABurstBaseAddr_Alt13 = 13u, /*!< Start from CCR2 register. */ + TIM_DMABurstBaseAddr_Alt14 = 14u, /*!< Start from CCR3 register. */ + TIM_DMABurstBaseAddr_Alt15 = 15u, /*!< Start from CCR4 register. */ +} TIM_DMABurstBaseAddr_Type; + +/*! + * @brief TIM DMA Burst transfer length. + */ +typedef enum +{ + TIM_DMABurstBaseLen_Alt0 = 0u, /*!< Sequentially visit 1 register from base register */ + TIM_DMABurstBaseLen_Alt1 = 1u, /*!< Sequentially visit 2 registers from base register */ + TIM_DMABurstBaseLen_Alt2 = 2u, /*!< Sequentially visit 3 registers from base register */ + TIM_DMABurstBaseLen_Alt3 = 3u, /*!< Sequentially visit 4 registers from base register */ + TIM_DMABurstBaseLen_Alt4 = 4u, /*!< Sequentially visit 5 registers from base register */ + TIM_DMABurstBaseLen_Alt5 = 5u, /*!< Sequentially visit 6 registers from base register */ + TIM_DMABurstBaseLen_Alt6 = 6u, /*!< Sequentially visit 7 registers from base register */ + TIM_DMABurstBaseLen_Alt7 = 7u, /*!< Sequentially visit 8 registers from base register */ + TIM_DMABurstBaseLen_Alt8 = 8u, /*!< Sequentially visit 9 registers from base register */ + TIM_DMABurstBaseLen_Alt9 = 9u, /*!< Sequentially visit 10 registers from base register */ + TIM_DMABurstBaseLen_Alt10 = 10u, /*!< Sequentially visit 11 registers from base register */ + TIM_DMABurstBaseLen_Alt11 = 11u, /*!< Sequentially visit 12 registers from base register */ + TIM_DMABurstBaseLen_Alt12 = 12u, /*!< Sequentially visit 13 registers from base register */ + TIM_DMABurstBaseLen_Alt13 = 13u, /*!< Sequentially visit 14 registers from base register */ + TIM_DMABurstBaseLen_Alt14 = 14u, /*!< Sequentially visit 15 registers from base register */ + TIM_DMABurstBaseLen_Alt15 = 15u, /*!< Sequentially visit 16 registers from base register */ + TIM_DMABurstBaseLen_Alt16 = 16u, /*!< Sequentially visit 17 registers from base register */ + TIM_DMABurstBaseLen_Alt17 = 17u, /*!< Sequentially visit 18 registers from base register */ +} TIM_DMABurstBaseLen_Type; + +/*! + * @brief TIM encoder direction. + */ +typedef enum +{ + TIM_EncoderDirection_Forward = 0u, /*!< Encoder rotates in forward direction. */ + TIM_EncoderDirection_Backward = 1u, /*!< Encoder rotates in backward direction. */ +} TIM_EncoderDirection_Type; + +/*! + * @brief TIM break input sampling filter. + */ +typedef enum +{ + TIM_BreakInFilter_Alt0 = 0u, /*!< Break In Filter swicther 0. */ + TIM_BreakInFilter_Alt1 = 1u, /*!< Break In Filter swicther 1. */ + TIM_BreakInFilter_Alt2 = 2u, /*!< Break In Filter swicther 2. */ + TIM_BreakInFilter_Alt3 = 3u, /*!< Break In Filter swicther 3. */ + TIM_BreakInFilter_Alt4 = 4u, /*!< Break In Filter swicther 4. */ + TIM_BreakInFilter_Alt5 = 5u, /*!< Break In Filter swicther 5. */ + TIM_BreakInFilter_Alt6 = 6u, /*!< Break In Filter swicther 6. */ + TIM_BreakInFilter_Alt7 = 7u, /*!< Break In Filter swicther 7. */ + TIM_BreakInFilter_Alt8 = 8u, /*!< Break In Filter swicther 8. */ + TIM_BreakInFilter_Alt9 = 9u, /*!< Break In Filter swicther 9. */ + TIM_BreakInFilter_Alt10 = 10u, /*!< Break In Filter swicther 10. */ + TIM_BreakInFilter_Alt11 = 11u, /*!< Break In Filter swicther 11. */ + TIM_BreakInFilter_Alt12 = 12u, /*!< Break In Filter swicther 12. */ + TIM_BreakInFilter_Alt13 = 13u, /*!< Break In Filter swicther 13. */ + TIM_BreakInFilter_Alt14 = 14u, /*!< Break In Filter swicther 14. */ + TIM_BreakInFilter_Alt15 = 15u, /*!< Break In Filter swicther 15. */ + TIM_BreakInFilter_Disabled = 16u, /*!< Not using Break In Filter. */ +} TIM_BreakInFilter_Type; + +/*! + * @brief TIM break input source switcher. + */ +typedef enum +{ + TIM_BreakInSource_Alt0 = 1u, /*!< Break In Source swicther 0. */ + TIM_BreakInSource_Alt1 = 2u, /*!< Break In Source swicther 1. */ +} TIM_BreakInSource_Type; + +/*! + * @brief TIM lock level. + */ +typedef enum +{ + TIM_LockLevel_Disabled = 0u, /*!< Unlock. */ + TIM_LockLevel_Alt0 = 1u, /*!< Lock level 1. */ + TIM_LockLevel_Alt1 = 2u, /*!< Lock level 2. */ + TIM_LockLevel_Alt2 = 3u, /*!< Lock level 3. */ +} TIM_LockLevel_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref TIM_Init() to initialize the TIM module time base unit. + */ +typedef struct +{ + uint32_t ClockFreqHz; /*!< Frequence of clock source for counter. */ + uint32_t StepFreqHz; /*!< Step length value. Counter freq = ClockSourceFreqHz / (ClockSourceDiv+1). */ + uint32_t Period; /*!< Counter counting period length, from 0 to Period. */ + bool EnablePreloadPeriod; /*!< Enable the preload of period value. If enable, it will be updated in next period, otherwise immediately. */ + TIM_PeriodMode_Type PeriodMode; /*!< Counter working period times. */ + TIM_CountMode_Type CountMode; /*!< Counter count direction. */ +} TIM_Init_Type; + +/*! + * @brief This type of structure instance is used to setup the output compare feature when calling the @ref TIM_EnableOutputCompare() to enable the TIM module output compare channel. + */ +typedef struct +{ + uint32_t ChannelValue; /*!< Value to be compared with counter. */ + bool EnableFastOutput; /*!< Enable fast response to the trigger input event. */ + bool EnablePreLoadChannelValue; /*!< Enable the preload of channel value. If enable, it will be updated in next period, otherwise immediately. */ + TIM_OutputCompareRefOut_Type RefOutMode; /*!< The reference output when counter matching the channel value. */ + bool ClearRefOutOnExtTrigger; /*!< External trigger high will clear the reference. */ + TIM_PinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */ +} TIM_OutputCompareConf_Type; + +/*! + * @brief This type of structure instance is used to setup the input capture feature when calling the @ref TIM_EnableInputCapture() to enable the TIM module input capture channel. + */ +typedef struct +{ + TIM_InputCaptureInDiv_Type InDiv; /*!< The division of filtered input. */ + TIM_InputCaptureInFilter_Type InFilter; /*!< The filter sampling time for initial input. */ + TIM_PinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */ +} TIM_InputCaptureConf_Type; + +/*! + * @brief This type of structure instance is used to setup the dead time feature when calling the @ref TIM_EnableDeadPeriod() to enable the TIM module dead time area set. + * | DeadPeriodCoef | Real Dead Area Time | + * | ------------ | --------------------------------------------------- | + * | 0xxxxxxx | DeadPeriodCoef * DeadPeriodStep | + * | 10xxxxxx | ( 64 + DeadPeriodCoef[5:0] ) * ( 2 * DeadPeriodStep ) | + * | 110xxxxx | ( 32 + DeadPeriodCoef[4:0] ) * ( 8 * DeadPeriodStep ) | + * | 111xxxxx | ( 32 + DeadPeriodCoef[4:0] ) * ( 16 * DeadPeriodStep ) | + */ +typedef struct +{ + uint8_t DeadPeriodCoef; /*!< The coefficient with bias to multiply with StepFreqHz to get the final dead area time. */ +} TIM_DeadPeriodConf_Type; + +/*! + * @brief This type of structure instance is used to setup the master mode configuration when calling the @ref TIM_EnableMasterMode(). + */ +typedef struct +{ + TIM_MasterOut_Type Out; /*!< Master mode output selection. */ + bool EnableSync; /*!< Enable sychronize with slave timers. */ +} TIM_MasterModeConf_Type; + +/*! + * @brief This type of structure instance is used to setup the slave mode configuration when calling the @ref TIM_EnableSlaveMode(). + */ +typedef struct +{ + TIM_SlaveIn_Type In; /*!< Input trigger selection for slave timer. */ + TIM_SlaveResp_Type Resp; /*!< Slave timer counter response for its input trigger. */ +} TIM_SlaveModeConf_Type; + +/*! + * @brief This type of structure instance is used to setup the external trigger input configuration when calling the @ref TIM_EnableExtTriggerIn(). + */ +typedef struct +{ + TIM_ExtTriggerInDiv_Type InDiv; /*!< The division of filtered input. */ + TIM_ExtTriggerInFilter_Type InFilter; /*!< The filter sampling time for initial input. */ + TIM_ExtTriggerPinPolarity_Type PinPolarity; /*!< Setup the output pin's polarity. */ +} TIM_ExtTriggerInConf_Type; + +/*! + * @brief This type of structure instance is used to setup the dma burst configuration when calling the @ref TIM_EnableDMABurst(). + */ +typedef struct +{ + TIM_DMABurstBaseAddr_Type BaseAddr; /*!< The base address to start transfer. */ + TIM_DMABurstBaseLen_Type Length; /*!< Length of sequential registers DMA burst visits. */ +} TIM_DMABurstConf_Type; + +/*! + * @brief This type of structure instance is used to setup the idle state output when calling the @ref TIM_EnableIdleOut(). + */ +typedef struct +{ + TIM_PinPolarity_Type PinPolarity; /*!< The output state of channel under idle mode. */ + TIM_PinPolarity_Type CompPinPolarity; /*!< The output state of complementary channel under idle mode. */ +} TIM_IdleOut_Type; + +/*! + * @brief This type of structure instance is used to setup the break in configuration when calling the @ref TIM_EnableBreakIn(). + */ +typedef struct +{ + TIM_PinPolarity_Type PinPolarity; /*!< The active edge of the break in signal. */ + bool AutoSwitchOutput; /*!< If input signal is inactive, switch the output compare at next update. */ + bool DirectIdleOutput; /*!< If enable, output the set idle state directly. */ + TIM_BreakInFilter_Type Filter; /*!< Break input filter type switcher. */ + uint32_t Source; /*!< Break input source mask. See to macro TIM_BKEAK_IN_MASKx. */ +} TIM_BreakIn_Type; + +/*! + * @brief Set the timer's step for indicated TIM module. + * + * @param TIMx TIM instance. + * @param init Pointer to the initialization structure. See to @ref TIM_Init_Type. + * @return val 'true' to set the timer's step successfully, 'false' to fail because the invalid StepFreqHz. + */ +bool TIM_Init(TIM_Type * TIMx, TIM_Init_Type * init); + +/*! + * @brief Start counting. + * + * @param TIMx TIM instance. + * @return None. + */ +void TIM_Start(TIM_Type * TIMx); + +/*! + * @brief Stop counting immediately. + * + * @param TIMx TIM instance. + * @return None. + */ +void TIM_Stop(TIM_Type * TIMx); + +/*! + * @brief Get the indicated TIMx Counter value. + * + * @param TIMx TIM_Type instance. + * @return The current value of the counter register. + */ +uint32_t TIM_GetCounterValue(TIM_Type * TIMx); + +/*! + * @brief Clear the indicated TIMx Counter. + * + * @param TIMx TIM_Type instance. + * @return None. + */ +void TIM_ClearCounterValue(TIM_Type * TIMx); + +/*! + * @brief Enable the TIM interrupts. + * + * @param TIMx TIM_Type instance. + * @param interrupts Interrupts to be enabled.See to @ref TIM_INT. + * @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs. + * @return None. + */ +void TIM_EnableInterrupts(TIM_Type * TIMx, uint32_t interrupts, bool enable); + +/*! + * @brief Enable the TIM DMAs. + * + * @param TIMx TIM_Type instance. + * @param dmas DMA masks to be enabled. See to @ref TIM_DMA. + * @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs. + * @return None. + */ +void TIM_EnableDMA(TIM_Type * TIMx, uint32_t dmas, bool enable); + +/*! + * @brief Software trigger events to call interrupts or DMAs. + * + * Can simultaneously trigger multiple events. + * + * @param TIMx TIM instance. See to @ref TIM_SWTRG. + * @param swtrgs Trigger the events to generate interrupts. + */ +void TIM_DoSwTrigger(TIM_Type * TIMx, uint32_t swtrgs); + +/*! + * @brief Get the status of the indicated timer. + * + * @param TIMx TIM_Type instance. + * @return Interrupt status flags. See to @ref TIM_INT_STATUS. + */ +uint32_t TIM_GetInterruptStatus(TIM_Type * TIMx); + +/*! + * @brief Clear the status of indicated interrupt. + * + * @param TIMx TIM_Type instance. + * @param status The required clear flag type. See to @ref TIM_INT_STATUS. + * @return None. + */ +void TIM_ClearInterruptStatus(TIM_Type * TIMx, uint32_t status); + +/*! + * @brief Set up the output compare feature of indicated timer channel. + * + * If need to change the IO mode of the working channel, channel must be disabled first, then modify. + * + * @param TIMx TIM_Type instance. + * @param channel Output channel instance. See to @ref TIM_CHANNEL_SELECTION. + * @param conf Pointer to the configuration structure. See to @ref TIM_OutputCompareConf_Type. + * @return None. + */ +void TIM_EnableOutputCompare(TIM_Type * TIMx, uint32_t channel, TIM_OutputCompareConf_Type * conf); + +/*! + * @brief Set up the complementary output compare feature of indicated timer channel. + * + * If need to change the IO mode of the working channel, channel must be disabled first, then modify. + * + * @param TIMx TIM_Type instance. + * @param channel Output channel instance. See to @ref TIM_CHANNEL_SELECTION. + * @param enable 'true' to enable the complementary channel output, 'false' to disable the complementary channel output. + * @return None. + */ +void TIM_EnableCompOutput(TIM_Type * TIMx, uint32_t channel, bool enable); + +/*! + * @brief Enable the TIM channel output for pulse generation. + * + * @param TIMx TIM_Type instance. + * @param enable 'true' to enable the channel output, 'false' to disable the channel output. + * @return None. + */ +void TIM_EnableOutputCompareSwitch(TIM_Type * TIMx, bool enable); + +/*! + * @brief Enable the input capture feature of indicated timer channel. + * + * If need to change the IO mode of the working channel, channel must be disabled first, then modify. + * + * @param TIMx TIM_Type instance. + * @param channel Input channel instance. See to @ref TIM_CHANNEL_SELECTION. + * @param conf Pointer to the configuration structure. See to @ref TIM_InputCaptureConf_Type. + * @return None. + */ +void TIM_EnableInputCapture(TIM_Type * TIMx, uint32_t channel, TIM_InputCaptureConf_Type * conf); + +/*! + * @brief Get the value of the indicated timer channel. + * + * When capture event happens, counter value will be kept in its indicated channel. + * + * @param TIMx TIM_Type instance. + * @param channel Channel instance to get the value. See to @ref TIM_CHANNEL_SELECTION. + * @return Value of the indiacted timer channel. + */ +uint32_t TIM_GetChannelValue(TIM_Type * TIMx, uint32_t channel); + +/*! + * @brief Put the value into the indicated timer channel. + * + * When in output compare, channel value would be the compared with counter value. + * + * @param TIMx TIM_Type instance. + * @param channel Channel instance to put the value. See to @ref TIM_CHANNEL_SELECTION. + * @param value The value to be set in the indicated timer channel. + * @return None. + */ +void TIM_PutChannelValue(TIM_Type * TIMx, uint32_t channel, uint32_t value); + +/*! + * @brief Set the step length between TIM internal clock and dead area clock / ETR / TI sample clock. + * + * @param TIMx TIM_Type instance. + * @param div Selected sample clock devision ratio. + * @return None. + */ +void TIM_SetClockDiv(TIM_Type * TIMx, TIM_ClockDiv_Type div); + +/*! + * @brief Enable the dead area of the indicated timer. + * + * @param TIMx TIM_Type instance. + * @param conf Pointer to the configuration structure. See to @ref TIM_DeadPeriodConf_Type. + * @return None. + */ +void TIM_EnableDeadPeriod(TIM_Type * TIMx, TIM_DeadPeriodConf_Type * conf); + +/*! + * @brief Enable the master mode of the indicated timer. + * + * Master mode transfer the timer signal to other timers. + * + * @param TIMx TIM_Type instance. + * @param conf Pointer to the configuration structure. See to @ref TIM_MasterModeConf_Type. + * @return None. + */ +void TIM_EnableMasterMode(TIM_Type * TIMx, TIM_MasterModeConf_Type * conf); + +/*! + * @brief Enable the slave mode of the indicated timer. + * + * Slave mode can control the working state of counter. + * + * @param TIMx TIM_Type instance. + * @param conf Pointer to the configuration structure. See to @ref TIM_SlaveModeConf_Type. + * @return None. + */ +void TIM_EnableSlaveMode(TIM_Type * TIMx, TIM_SlaveModeConf_Type * conf); + +/*! + * @brief Enable the external trigger input of the indicated counter. + * + * External trigger signal will trigger counter do addition. + * Its div and filter along with the counter StepFreqHz will affect. + * + * @param TIMx TIM_Type instance. + * @param conf Pointer to the configuration structure. See to @ref TIM_ExtTriggerInConf_Type. + * @return None. + */ +void TIM_EnableExtTriggerIn(TIM_Type * TIMx, TIM_ExtTriggerInConf_Type * conf); + +/*! + * @brief Enable the dma burst transfer of the indicated timer. + * + * @param TIMx TIM_Type instance. + * @param conf Pointer to the configuration structure. See to @ref TIM_DMABurstConf_Type. + * @return Address of DMA Burst transfer base register address. + */ +uint32_t TIM_EnableDMABurst(TIM_Type * TIMx, TIM_DMABurstConf_Type * conf); + +/*! + * @brief Get the encoder rotating direction and the counted encoder pulse times. + * + * @param TIMx TIM_Type instance. + * @param value The counter value for pulse times. + * @return Encoder rotating direction. See to @ref TIM_EncoderDirection_Type. + */ +TIM_EncoderDirection_Type TIM_GetEncoder(TIM_Type * TIMx, uint32_t * value); + +/*! + * @brief Set the indicated TIMx repetition counter value. + * + * @param TIMx TIM_Type instance. + * @param value The repetition value to be set. + * @return The current value of the counter register. + */ +void TIM_SetRepCounter(TIM_Type * TIMx, uint8_t value); + +/*! + * @brief Get the indicated TIMx Counter value. + * + * Real repetition's times number, meaning left repetition period times to run. + * + * @param TIMx TIM_Type instance. + * @return The current value of the counter register. + */ +uint8_t TIM_GetRepCounterValue(TIM_Type * TIMx); + +/*! + * @brief Set the channel idle state output when switch off the output compare. + * + * @param TIMx TIM_Type instance. + * @param channel Channel instance to set the idle state output. See to @ref TIM_CHANNEL_SELECTION. + * @param conf Pointer to the configuration structure. See to @ref TIM_IdleOut_Type. + * @return None. + */ +void TIM_EnableIdleOut(TIM_Type * TIMx, uint32_t channel, TIM_IdleOut_Type * conf); + +/*! + * @brief Set the lock level for protecting the timer config setting. + * + * @param TIMx TIM_Type instance. + * @param lock Lock level to be set for protecting Timer set. See to @ref TIM_LockLevel_Type. + * @return None. + */ +void TIM_EnableLock(TIM_Type * TIMx, TIM_LockLevel_Type lock); + +/*! + * @brief Set the break input of the timer. + * + * @param TIMx TIM_Type instance. + * @param conf Pointer to the configuration structure. See to @ref TIM_BreakIn_Type. + * @return None. + */ +void TIM_EnableBreakIn(TIM_Type * TIMx, TIM_BreakIn_Type * conf); + +/*! + * @brief Set the PWM shift of the indicated channel. + * + * @param TIMx TIM_Type instance. + * @param channel Channel instance to set the pwm shift. See to @ref TIM_CHANNEL_SELECTION. + * @param value The counter time when need pwm output shift. If val equals the channel value, disable the shift. + * @return None. + */ +void TIM_EnablePWMShift(TIM_Type * TIMx, uint32_t channel, uint16_t value); + +/*! + *@} + */ +#endif /* __HAL_TIM_H__ */ + diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_uart.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_uart.c new file mode 100644 index 000000000..98ad86de2 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_uart.c @@ -0,0 +1,130 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_uart.h" + +void UART_Init(UART_Type * UARTx, UART_Init_Type * init) +{ + uint32_t ccr = UARTx->CCR & ~( UART_CCR_PEN_MASK + | UART_CCR_PSEL_MASK + | UART_CCR_SPB0_MASK + | UART_CCR_CHAR_MASK + | UART_CCR_SPB1_MASK + ); + /* WordLength. */ + ccr |= UART_CCR_CHAR(init->WordLength); + + /* StopBits. */ + if ( (init->StopBits == UART_StopBits_2) || (init->StopBits == UART_StopBits_1_5) ) + { + ccr |= UART_CCR_SPB0_MASK; + } + if ( (init->StopBits == UART_StopBits_0_5) || (init->StopBits == UART_StopBits_1_5) ) + { + ccr |= UART_CCR_SPB1_MASK; + } + + /* Parity. */ + if (init->Parity == UART_Parity_Even) + { + ccr |= UART_CCR_PEN_MASK; + } + if (init->Parity == UART_Parity_Odd) + { + ccr |= UART_CCR_PEN_MASK | UART_CCR_PSEL_MASK; + } + UARTx->CCR = ccr; + + /* XferMode. */ + uint32_t gcr = UARTx->GCR & ~( UART_GCR_RXEN_MASK + | UART_GCR_TXEN_MASK + | UART_GCR_AUTOFLOWEN_MASK + ); + gcr |= ((uint32_t)(init->XferMode) << UART_GCR_RXEN_SHIFT); + if (init->HwFlowControl == UART_HwFlowControl_RTS_CTS) + { + gcr |= UART_GCR_AUTOFLOWEN_MASK; + } + UARTx->GCR = gcr; + + /* Setup the baudrate. */ + UARTx->BRR = (init->ClockFreqHz / init->BaudRate) / 16u; + UARTx->FRA = (init->ClockFreqHz / init->BaudRate) % 16u; +} + +void UART_Enable(UART_Type * UARTx, bool enable) +{ + if (enable) + { + UARTx->GCR |= UART_GCR_UARTEN_MASK; + } + else + { + UARTx->GCR &= ~UART_GCR_UARTEN_MASK; + } +} + +void UART_EnableInterrupts(UART_Type * UARTx, uint32_t interrupts, bool enable) +{ + (enable) ? (UARTx->IER |= interrupts) : (UARTx->IER &= ~interrupts); +} + +uint32_t UART_GetEnabledInterrupts(UART_Type * UARTx) +{ + return UARTx->IER; +} + +void UART_EnableDMA(UART_Type * UARTx, bool enable) +{ + if (enable) + { + UARTx->GCR |= UART_GCR_DMAMODE_MASK; + } + else + { + UARTx->GCR &= ~UART_GCR_DMAMODE_MASK; + } +} + +void UART_PutData(UART_Type * UARTx, uint8_t value) +{ + UARTx->TDR = value; +} + +uint8_t UART_GetData(UART_Type * UARTx) +{ + return (uint8_t)(UARTx->RDR & 0xFFU); +} + +/* return flags */ +uint32_t UART_GetStatus(UART_Type * UARTx) +{ + return UARTx->CSR; +} + +/* return flags. */ +uint32_t UART_GetInterruptStatus(UART_Type * UARTx) +{ + return UARTx->ISR; +} + +void UART_ClearInterruptStatus(UART_Type * UARTx, uint32_t interrupts) +{ + UARTx->ICR = interrupts; +} + +uint32_t UART_GetRxDataRegAddr(UART_Type * UARTx) +{ + return (uint32_t)(&(UARTx->RDR)); +} + +uint32_t UART_GetTxDataRegAddr(UART_Type * UARTx) +{ + return (uint32_t)(&(UARTx->TDR)); +} + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_uart.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_uart.h new file mode 100644 index 000000000..f1e8d5847 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_uart.h @@ -0,0 +1,228 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_UART_H__ +#define __HAL_UART_H__ + +#include "hal_common.h" + +/*! + * @addtogroup UART + * @{ + */ + +/*! + * @brief UART driver version number. + */ +#define UART_DRIVER_VERSION 0u /*!< uart_0. */ + +/*! + * @addtogroup UART_STATUS + * @{ + */ +#define UART_STATUS_TX_DONE UART_CSR_TXC_MASK /*!< Status flag when UART transmiter shifter is empty after the transfer is done. */ +#define UART_STATUS_RX_DONE UART_CSR_RXAVL_MASK /*!< Status flag when UART receiving buffer is with available data. */ +#define UART_STATUS_TX_FULL UART_CSR_TXFULL_MASK /*!< Status flag when UART transmiter buffer is full. */ +#define UART_STATUS_TX_EMPTY UART_CSR_TXEPT_MASK /*!< Status flag when UART transmiter buffer is empty. */ +/*! + * @} + */ + +/*! + * @addtogroup UART_INT + * @{ + */ +#define UART_INT_TX_EMPTY UART_ISR_TXINTF_MASK /*!< Interrupt enable when UART transmiter buffer is empty. */ +#define UART_INT_RX_DONE UART_ISR_RXINTF_MASK /*!< Interrupt enable when UART receiving buffer is with available data. */ +#define UART_INT_TX_DONE UART_ISR_TXCINTF_MASK /*!< Interrupt enable when UART transmiter shifter is empty. */ +/*! + * @} + */ + +/*! + * @brief UART word length type. + */ +typedef enum +{ + UART_WordLength_5b = 0u, /*!< Word length 5 bits. */ + UART_WordLength_6b = 1u, /*!< Word length 6 bits. */ + UART_WordLength_7b = 2u, /*!< Word length 7 bits. */ + UART_WordLength_8b = 3u, /*!< Word length 8 bits. */ +} UART_WordLength_Type; + +/*! + * @brief UART stop bits type. + */ +typedef enum +{ + UART_StopBits_1 = 0u, /*!< 1 stop bits. */ + UART_StopBits_2 = 1u, /*!< 2 stop bits. */ + UART_StopBits_0_5 = 2u, /*!< 0.5 stop bits. */ + UART_StopBits_1_5 = 3u, /*!< 1.5 stop bits. */ +} UART_StopBits_Type; + +/*! + * @brief UART parity type. + */ +typedef enum +{ + UART_Parity_None = 0u, /*!< No parity. */ + UART_Parity_Even = 1u, /*!< Even parity. */ + UART_Parity_Odd = 2u, /*!< Odd parity. */ +} UART_Parity_Type; + +/*! + * @brief UART hardware flow control type. + */ +typedef enum +{ + UART_HwFlowControl_None = 0u, /*!< No hardware flow control. */ + UART_HwFlowControl_RTS_CTS = 1u, /*!< Enable RTS and CTS hardware flow control.*/ +} UART_HwFlowControl_Type; + +/*! + * @brief UART xfer mode type. + */ +typedef enum +{ + UART_XferMode_None = 0u, /*!< Disable both Tx and Rx. */ + UART_XferMode_RxOnly = 1u, /*!< Enable Rx only. */ + UART_XferMode_TxOnly = 2u, /*!< Enable Tx only. */ + UART_XferMode_RxTx = 3u, /*!< Enable both Rx and Tx. */ +} UART_XferMode_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref UART_Init() to initialize the UART module. + */ +typedef struct +{ + uint32_t ClockFreqHz; /*!< Bus Clock Freq. */ + uint32_t BaudRate; /*!< Specify the UART communication baud rate. */ + UART_WordLength_Type WordLength; /*!< Specify the number of data bits transmitted or received in a frame. */ + UART_StopBits_Type StopBits; /*!< Specify the number of stop bits transmitted. */ + UART_Parity_Type Parity; /*!< Specify the parity mode. */ + UART_XferMode_Type XferMode; /*!< Specify whether the Receive or Transmit mode is enabled or not. */ + UART_HwFlowControl_Type HwFlowControl; /*!< Specify whether the hardware flow control mode is enabled or not. */ +} UART_Init_Type; + +/*! + * @brief Initialize the UART module. + * + * @param UARTx UART instance. + * @param init Pointer to the initialization structure. See to @ref UART_Init_Type. + * @return None. + */ +void UART_Init(UART_Type * UARTx, UART_Init_Type * init); + +/*! + * @brief Enable the UART module. + * + * The UART module should be enabled before sending or receiving data. + * + * @param UARTx UART instance. + * @param enable 'true' to enable the module, 'false' to disable the module. + * @return None. + */ +void UART_Enable(UART_Type * UARTx, bool enable); + +/*! + * @brief Get the current status flags of the UART module. + * + * @param UARTx UART instance. + * @return Status flags. See to @ref UART_STATUS. + */ +uint32_t UART_GetStatus(UART_Type * UARTx); + +/*! + * @brief Enable interrupts of the UART module. + * + * @param UARTx UART instance. + * @param interrupts Interrupt code masks. See to @ref UART_INT. + * @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts. + * @return None. + */ +void UART_EnableInterrupts(UART_Type * UARTx, uint32_t interrupts, bool enable); + +/*! + * @brief Get the interrupts status flags of the UART module. + * + * @param UARTx UART instance. + * @return Interrupt status flags. See to @ref UART_INT. + */ +uint32_t UART_GetInterruptStatus(UART_Type * UARTx); + +/*! + * @brief Clear the interrupts status flags of the UART module. + * + * @param UARTx UART instance. + * @param interrupts The mask codes of the indicated interrupt flags to be cleared. + * @return Interrupt status flags. See to @ref UART_INT. + */ +void UART_ClearInterruptStatus(UART_Type * UARTx, uint32_t interrupts); + +/*! + * @brief Put the data into transmiter buffer of the UART module. + * + * @param UARTx UART instance. + * @param value Data value to be send through the transmiter. + * @return None. + */ +void UART_PutData(UART_Type * UARTx, uint8_t value); + +/*! + * @brief Get the data from receiver buffer of the UART module. + * + * @param UARTx UART instance. + * @return The data value received from the receiver. + * @return None. + */ +uint8_t UART_GetData(UART_Type * UARTx); + +/*! + * @brief Enable the DMA trigger from the UART module. + * + * The DMA trigger events are the same as the intertupts. + * + * @param UARTx UART instance. + * @param enable 'true' to enable the DMA trigger, 'false' to disable the DMA trigger. + * @return None. + */ +void UART_EnableDMA(UART_Type * UARTx, bool enable); + +/*! + * @brief Read the current enabled interrupts the UART module. + * + * @param UARTx UART instance. + * @return The mask codes enabled interrupts. See to @ref UART_INT + */ +uint32_t UART_GetEnabledInterrupts(UART_Type * UARTx); + +/*! + * @brief Get the hardware Rx data buffer's address the UART module. + * + * The return value of the address is most used with DMA module. + * + * @param UARTx UART instance. + * @return The value of the address for UART module's hardware Rx data buffer. + */ +uint32_t UART_GetRxDataRegAddr(UART_Type * UARTx); + +/*! + * @brief Get the hardware Tx data buffer's address the UART module. + * + * The return value of the address is most used with DMA module. + * + * @param UARTx UART instance. + * @return The value of the address for UART module's hardware Tx data buffer. + */ +uint32_t UART_GetTxDataRegAddr(UART_Type * UARTx); + +/*! + *@} + */ + +#endif /* __HAL_UART_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_usb.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_usb.c new file mode 100644 index 000000000..a4955a674 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_usb.c @@ -0,0 +1,313 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_usb.h" + + +void USB_SetBufDespTableAddr(USB_Type * USBx, uint32_t addr) +{ + USBx->FSBDTPAGE1 = USB_FSBDTPAGE1_BDTBA(addr >> 9u); + USBx->FSBDTPAGE2 = USB_FSBDTPAGE2_BDTBA(addr >> 16u); + USBx->FSBDTPAGE3 = USB_FSBDTPAGE3_BDTBA(addr >> 24u); +} + +void USB_InitDevice(USB_Type * USBx, USB_Device_Init_Type *init) +{ + if ( (uintptr_t)(init->BufDespTable_Addr) % 512u != 0u) + { + return; + } + USB_SetDeviceAddr(USBx, 0x00u); + USB_SetBufDespTableAddr(USBx, init->BufDespTable_Addr); + USB_Enable(USBx, true); +} + +void USB_EnableInterrupts(USB_Type * USBx, uint32_t interrupts, bool enable) +{ + if(enable) + { + USBx->FSINTENB |= interrupts; + } + else + { + USBx->FSINTENB &= ~interrupts; + } +} + +uint32_t USB_GetEnabledInterrupts(USB_Type * USBx) +{ + return USBx->FSINTENB; +} + +uint32_t USB_GetInterruptStatus(USB_Type * USBx) +{ + uint32_t stat = USBx->FSINTSTAT; + uint32_t enb = USBx->FSINTENB; + return stat & enb; +} + +void USB_ClearInterruptStatus(USB_Type * USBx, uint32_t interrupts) +{ + uint32_t enb = USBx->FSINTENB; + USBx->FSINTSTAT = interrupts & enb; +} + +void USB_EnableErrInterrupts(USB_Type * USBx, uint32_t interrupts, bool enable) +{ + if(enable) + { + USBx->FSERRENB |= interrupts; + } + else + { + USBx->FSERRENB &= ~interrupts; + } +} + + +uint32_t USB_GetEnabledErrInterrupts(USB_Type * USBx) +{ + return USBx->FSERRENB; +} + +uint32_t USB_GetErrInterruptStatus(USB_Type * USBx) +{ + uint32_t stat = USBx->FSERRSTAT; + uint32_t enb = USBx->FSERRENB; + USBx->FSERRSTAT = stat & ~enb; + return stat & enb; +} + +void USB_ClearErrInterruptStatus(USB_Type * USBx, uint32_t interrupts) +{ + uint32_t enb = USBx->FSERRENB; + USBx->FSERRSTAT = interrupts & enb; +} + +uint32_t USB_GetBufDespIndex(USB_Type * USBx) +{ + return (USBx->FSSTAT)>>2; +} + +void USB_Enable(USB_Type * USBx, bool enable) +{ + if(enable) + { + USBx->FSCTL |= USB_FSCTL_USBEN_MASK; + } + else + { + USBx->FSCTL &= ~USB_FSCTL_USBEN_MASK; + } +} + +void USB_EnableOddEvenReset(USB_Type * USBx, bool enable) +{ + if(enable) + { + USBx->FSCTL |= USB_FSCTL_ODDRST_MASK; + } + else + { + USBx->FSCTL &= ~USB_FSCTL_ODDRST_MASK; + } +} + +void USB_EnableResumeSignal(USB_Type * USBx, bool enable) +{ + if(enable) + { + USBx->FSCTL |= USB_FSCTL_RESUME_MASK; + } + else + { + USBx->FSCTL &= ~USB_FSCTL_RESUME_MASK; + } +} + +void USB_EnableSuspend(USB_Type * USBx, bool enable) +{ + if(true == enable) + { + USBx->FSCTL |= USB_FSCTL_TXDSUSPENDTOKENBUSY_MASK; + } + else + { + USBx->FSCTL &= ~USB_FSCTL_TXDSUSPENDTOKENBUSY_MASK; + } + +} + + +void USB_SetDeviceAddr(USB_Type * USBx, uint8_t addr) +{ + USBx->FSADDR = ( (USBx->FSADDR & ~USB_FSADDR_ADDR_MASK) + | (addr & USB_FSADDR_ADDR_MASK) ) + ; +} + +uint8_t USB_GetDeviceAddr(USB_Type * USBx) +{ + return USBx->FSADDR & USB_FSADDR_ADDR_MASK; +} + +uint32_t USB_GetBufDespTableAddr(USB_Type * USBx) +{ + return (uint32_t) + ( ( (USBx->FSBDTPAGE1 >> USB_FSBDTPAGE1_BDTBA_SHIFT) << 9u ) + | ( (USBx->FSBDTPAGE2 >> USB_FSBDTPAGE2_BDTBA_SHIFT) << 16u) + | ( (USBx->FSBDTPAGE3 >> USB_FSBDTPAGE3_BDTBA_SHIFT) << 24u) + ); +} + +uint32_t USB_GetFrameNumber(USB_Type * USBx) +{ + return (USBx->FSFRMNUML) | (USBx->FSFRMNUML << 7u); +} + +USB_BufDesp_Type * USB_GetBufDesp(USB_Type * USBx) +{ + USB_BufDespTable_Type *bdt = (USB_BufDespTable_Type *)USB_GetBufDespTableAddr(USBx); + return &bdt->Index[USBx->FSSTAT >> 2]; +} + +USB_TokenPid_Type USB_BufDesp_GetTokenPid(USB_BufDesp_Type * bd) +{ + return (USB_TokenPid_Type)bd->TOK_PID; +} + +uint32_t USB_BufDesp_GetPacketAddr(USB_BufDesp_Type * bd) +{ + return bd->ADDR; +} + +uint32_t USB_BufDesp_GetPacketSize(USB_BufDesp_Type * bd) +{ + return bd->BC; +} + +void USB_BufDesp_Reset(USB_BufDesp_Type * bd) +{ + bd->BDT_STALL = 0u; + bd->NINC = 0u; + bd->KEEP = 0u; + bd->DTS = 1u; +} + +uint32_t USB_GetEndPointIndex(USB_Type * USBx) +{ + return (USBx->FSSTAT & USB_FSSTAT_ENDP_MASK) >> USB_FSSTAT_ENDP_SHIFT; +} + +USB_Direction_Type USB_GetXferDirection(USB_Type * USBx) +{ + return (USB_Direction_Type)( (USBx->FSSTAT & USB_FSSTAT_TX_MASK) >> USB_FSSTAT_TX_SHIFT); +} + +USB_BufDesp_OddEven_Type USB_GetBufDespOddEven(USB_Type * USBx) +{ + return (USB_BufDesp_OddEven_Type)( (USBx->FSSTAT & USB_FSSTAT_ODD_MASK) >> USB_FSSTAT_ODD_SHIFT ); +} + +bool USB_BufDesp_Xfer(USB_BufDesp_Type * bd, uint32_t data_n, uint8_t * buffer, uint32_t len) +{ + if (1u == bd->OWN) + { + return false; + } + bd->ADDR = (uint32_t)buffer; + bd->DATA = data_n; + bd->BC = len; + bd->OWN = 1u; + return true; +} + +bool USB_BufDesp_IsBusy(USB_BufDesp_Type * bd) +{ + if (1u == bd->OWN) + { + return true; + } + else + { + return false; + } +} + +void USB_EnableEndPoint(USB_Type * USBx, uint32_t index, USB_EndPointMode_Type mode, bool enable) +{ + if (false == enable) + { + USBx->FSEPCTL[index] = 0u; + USB_BufDespTable_Type * bdt = (USB_BufDespTable_Type * )USB_GetBufDespTableAddr(USBx); + bdt->Table[index][0u][0u].HEAD = 0u; + bdt->Table[index][0u][1u].HEAD = 0u; + bdt->Table[index][1u][0u].HEAD = 0u; + bdt->Table[index][1u][1u].HEAD = 0u; + return; + } + if (USB_EndPointMode_Control == mode) + { + USBx->FSEPCTL[index] |= USB_FSEPCTL_EPCTLDISEPRXENEPTXEN(3) | USB_FSEPCTL_EPHSHK_MASK; + } + else if (USB_EndPointMode_Bulk == mode) + { + USBx->FSEPCTL[index] |= USB_FSEPCTL_EPCTLDISEPRXENEPTXEN(7u) | USB_FSEPCTL_EPHSHK_MASK; + } + else if (USB_EndPointMode_Interrupt == mode) + { + USBx->FSEPCTL[index] |= USB_FSEPCTL_EPCTLDISEPRXENEPTXEN(7u) | USB_FSEPCTL_EPHSHK_MASK; + } + else if (USB_EndPointMode_Isochronous == mode) + { + USBx->FSEPCTL[index] |= USB_FSEPCTL_EPCTLDISEPRXENEPTXEN(7u); + } +} + +void USB_EnableEndPointStall(USB_Type * USBx, uint32_t index, bool enable) +{ + USB_BufDespTable_Type * bdt = (USB_BufDespTable_Type * )USB_GetBufDespTableAddr(USBx); + for (uint32_t i = 0; i < USB_BDT_EP_NUM; i++) + { + if (true == enable) + { + USBx->FSEPCTL[i] |= USB_FSEPCTL_EPSTALL_MASK; + bdt->Table[i][USB_BufDesp_OddEven_Odd ][USB_Direction_IN ].BDT_STALL = 1u; + bdt->Table[i][USB_BufDesp_OddEven_Odd ][USB_Direction_OUT].BDT_STALL = 1u; + bdt->Table[i][USB_BufDesp_OddEven_Even][USB_Direction_IN ].BDT_STALL = 1u; + bdt->Table[i][USB_BufDesp_OddEven_Even][USB_Direction_OUT].BDT_STALL = 1u; + } + else + { + USBx->FSEPCTL[i] &= ~USB_FSEPCTL_EPSTALL_MASK; + bdt->Table[i][USB_BufDesp_OddEven_Odd ][USB_Direction_IN ].BDT_STALL = 0u; + bdt->Table[i][USB_BufDesp_OddEven_Odd ][USB_Direction_IN ].OWN = 0u; + bdt->Table[i][USB_BufDesp_OddEven_Odd ][USB_Direction_OUT].BDT_STALL = 0u; + bdt->Table[i][USB_BufDesp_OddEven_Odd ][USB_Direction_OUT].OWN = 0u; + bdt->Table[i][USB_BufDesp_OddEven_Even][USB_Direction_IN ].BDT_STALL = 0u; + bdt->Table[i][USB_BufDesp_OddEven_Even][USB_Direction_IN ].OWN = 0u; + bdt->Table[i][USB_BufDesp_OddEven_Even][USB_Direction_OUT].BDT_STALL = 0u; + bdt->Table[i][USB_BufDesp_OddEven_Even][USB_Direction_OUT].OWN = 0u; + } + } +} + +uint32_t USB_GetEnabledEndPointStall(USB_Type * USBx) +{ + uint32_t status = 0u; + for(uint32_t i = 0u; i < USB_BDT_EP_NUM; i++) + { + if (0 != (USBx->FSEPCTL[i] & USB_FSEPCTL_EPSTALL_MASK) ) + { + status |= 1u << i; + } + } + return status; +} + +/* EOF. */ + diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_usb.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_usb.h new file mode 100644 index 000000000..68d4dc2fc --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_usb.h @@ -0,0 +1,399 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_USB_H__ +#define __HAL_USB_H__ + +#include "hal_common.h" +#include "hal_usb_bdt.h" + +/*! + * @addtogroup USB + * @{ + */ + +/*! + * @brief USB driver version number. + */ +#define USB_DRIVER_VERSION 0u /*!< USB_0. */ + + +/*! + * @addtogroup USB_INT + * @brief USB_INT mask codes + * @{ + */ +#define USB_INT_RESET USB_FSINTSTAT_USBRST_MASK /*!< USB Interrupt: USB bus reset. */ +#define USB_INT_ERROR USB_FSINTSTAT_ERROR_MASK /*!< USB Interrupt: Error happend. */ +#define USB_INT_SOFTOK USB_FSINTSTAT_SOFTOK_MASK /*!< USB Interrupt: Recv a SOF_Tok. */ +#define USB_INT_TOKENDONE USB_FSINTSTAT_TOKDNE_MASK /*!< USB Interrupt: Token done. */ +#define USB_INT_SLEEP USB_FSINTSTAT_SLEEP_MASK /*!< USB Interrupt: Sleep. */ +#define USB_INT_RESUME USB_FSINTSTAT_RESUME_MASK /*!< USB Interrupt: Resume. */ +#define USB_INT_ATTACH USB_FSINTSTAT_ATTACH_MASK /*!< USB Interrupt: Attach. */ +#define USB_INT_STALL USB_FSINTSTAT_STALL_MASK /*!< USB Interrupt: Stall. */ +/*! + * @} + */ + +/*! + * @addtogroup USB_INT_ERR + * @brief USB_INT_ERR mask codes + * @{ + */ +#define USB_INT_ERR_PID USB_FSERRSTAT_PIDERR_MASK /*!< USB Error: PID check error. */ +#define USB_INT_ERR_CRC5 USB_FSERRSTAT_CRC5EOF_MASK /*!< USB Error: CRC5 check failed. */ +#define USB_INT_ERR_EOF USB_FSERRSTAT_CRC5EOF_MASK /*!< USB Error: EOF Error. */ +#define USB_INT_ERR_CRC16 USB_FSERRSTAT_CRC16_MASK /*!< USB Error: CRC16 check failed. */ +#define USB_INT_ERR_DFN8 USB_FSERRSTAT_DFN8_MASK /*!< USB Error: Data not 8bit. */ +#define USB_INT_ERR_BTO USB_FSERRSTAT_BTOERR_MASK /*!< USB Error: BTO error. */ +#define USB_INT_ERR_DMA USB_FSERRSTAT_DMAERR_MASK /*!< USB Error: DMA error. */ +#define USB_INT_ERR_BTS USB_FSERRSTAT_BTSERR_MASK /*!< USB Error: Bit stuff error. */ +/*! + * @} + */ + +/*! + * @addtogroup USB_EP + * @brief USB_EP mask codes + * @{ + */ +#define USB_EP_0 (1u << 0u ) /*!< EndPoint 0. */ +#define USB_EP_1 (1u << 1u ) /*!< EndPoint 1. */ +#define USB_EP_2 (1u << 2u ) /*!< EndPoint 2. */ +#define USB_EP_3 (1u << 3u ) /*!< EndPoint 3. */ +#define USB_EP_4 (1u << 4u ) /*!< EndPoint 4. */ +#define USB_EP_5 (1u << 5u ) /*!< EndPoint 5. */ +#define USB_EP_6 (1u << 6u ) /*!< EndPoint 6. */ +#define USB_EP_7 (1u << 7u ) /*!< EndPoint 7. */ +#define USB_EP_8 (1u << 8u ) /*!< EndPoint 8. */ +#define USB_EP_9 (1u << 9u ) /*!< EndPoint 9. */ +#define USB_EP_10 (1u << 10u) /*!< EndPoint 10. */ +#define USB_EP_11 (1u << 11u) /*!< EndPoint 11. */ +#define USB_EP_12 (1u << 12u) /*!< EndPoint 12. */ +#define USB_EP_13 (1u << 13u) /*!< EndPoint 13. */ +#define USB_EP_14 (1u << 14u) /*!< EndPoint 14. */ +#define USB_EP_15 (1u << 15u) /*!< EndPoint 15. */ +/*! + * @} + */ + +/*! + * @brief USB TokenPid type. + */ +typedef enum +{ + USB_TokenPid_OUT = 0x1u, /*!< USB Token Pid: OUT. */ + USB_TokenPid_IN = 0x9u, /*!< USB Token Pid: IN. */ + USB_TokenPid_SETUP = 0xDu, /*!< USB Token Pid: SETUP. */ +} USB_TokenPid_Type; + +/*! + * @brief USB Direction type. + */ +typedef enum +{ + USB_Direction_OUT = 0x0u, /*!< USB Direstion: IN. */ + USB_Direction_IN = 0x1u, /*!< USB Direstion: OUT. */ + USB_Direction_NULL, /*!< USB Direstion: NULL. */ +} USB_Direction_Type; + +/*! + * @brief USB BufDesp OddEven type. + */ +typedef enum +{ + USB_BufDesp_OddEven_Even = 0x0u, /*!< Buffer Descriptor OddEven: Even. */ + USB_BufDesp_OddEven_Odd = 0x1u, /*!< Buffer Descriptor OddEven: Odd. */ +} USB_BufDesp_OddEven_Type; + +/*! + * @brief USB EndPoint Mode. + */ +typedef enum +{ + USB_EndPointMode_Control = 1u, /*!< USB EndPoint Mode: Control xfer. */ + USB_EndPointMode_Bulk = 2u, /*!< USB EndPoint Mode: Bulk xfer. */ + USB_EndPointMode_Interrupt = 3u, /*!< USB EndPoint Mode: Interrupt xfer. */ + USB_EndPointMode_Isochronous = 4u, /*!< USB EndPoint Mode: isoch xfer. */ + USB_EndPointMode_NULL, /*!< USB EndPoint Mode: NULL. */ +} USB_EndPointMode_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref USB_InitDevice() to initialize the USB module. + */ +typedef struct +{ + uint32_t BufDespTable_Addr; /*!< BufDespTable addr. */ +} USB_Device_Init_Type; + +/*! + * @brief Initialize the USB module. + * + * @param USBx USB instance. + * @param init Pointer to the initialization structure. See to @ref USB_Device_Init_Type. + * @return None. + */ +void USB_InitDevice(USB_Type * USBx, USB_Device_Init_Type * init); + +/*! + * @brief Enable interrupts of the USB module. + * + * @param USBx USB instance. + * @param interrupts Interrupt code masks. See to @ref USB_INT. + * @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts. + * @return None. + */ +void USB_EnableInterrupts(USB_Type * USBx, uint32_t interrupts, bool enable); + +/*! + * @brief Get the enabled interrupts status flags of the USB module. + * + * @param USBx USB instance. + * @return Interrupt status flags. See to @ref USB_INT. + */ +uint32_t USB_GetEnabledInterrupts(USB_Type * USBx); + +/*! + * @brief Get the interrupts status flags of the USB module. + * + * @param USBx USB instance. + * @return Interrupt status flags. See to @ref USB_INT. + */ +uint32_t USB_GetInterruptStatus(USB_Type * USBx); + +/*! + * @brief Clear the interrupts status flags of the USB module. + + * @param USBx USB instance. + * @param interrupts Interrupt status flags. See to @ref USB_INT. + * @return None. + */ +void USB_ClearInterruptStatus(USB_Type * USBx, uint32_t interrupts); + +/*! + * @brief Enable error interrupts of the USB module. + * + * @param USBx USB instance. + * @param interrupts Error Interrupt code masks. See to @ref USB_INT_ERR. + * @param enable 'true' to enable the indicated interrupts, 'false' to disable the indicated interrupts. + * @return None. + */ +void USB_EnableErrInterrupts(USB_Type * USBx, uint32_t interrupts, bool enable); + +/*! + * @brief Get the enabled error interrupts status flags of the USB module. + * + * @param USBx USB instance. + * @return Interrupt status flags. See to @ref USB_INT_ERR. + */ +uint32_t USB_GetEnabledErrInterrupts(USB_Type * USBx); + +/*! + * @brief Get the error interrupts status flags of the USB module. + * + * @param USBx USB instance. + * @return Interrupt status flags. See to @ref USB_INT_ERR. + */ +uint32_t USB_GetErrInterruptStatus(USB_Type * USBx); + +/*! + * @brief Clear the error interrupts status flags of the USB module. + + * @param USBx USB instance. + * @param interrupts Interrupt status flags. See to @ref USB_INT_ERR. + * @return None. + */ +void USB_ClearErrInterruptStatus(USB_Type * USBx, uint32_t interrupts); + +/*! + * @brief Enable USB. + * + * @param USBx USB instance. + * @param enable 'true' to enable the module, 'false' to disable the module. + * @return None. + */ +void USB_Enable(USB_Type * USBx, bool enable); + +/*! + * @brief Enable USB BufDesp ODD_EVEN Reset, and make only even BufDesp can be used. + * + * @param USBx USB instance. + * @param enable 'true' to enable the feature, 'false' to disable the feature. + * @return None. + */ +void USB_EnableOddEvenReset(USB_Type * USBx, bool enable); + +/*! + * @brief Enable USB Resume signal. + * + * @param USBx USB instance. + * @param enable 'true' to enable the resume signal, 'false' to disable the resume signal. + * @return None. + */ +void USB_EnableResumeSignal(USB_Type * USBx, bool enable); + +/*! + * @brief Enable USB Suspend. + * + * @param USBx USB instance. + * @param enable 'true' to enable suspend, 'false' to disable suspend. + * @return None. + */ +void USB_EnableSuspend(USB_Type * USBx, bool enable); + +/*! + * @brief Set Device address. This address is distribute by host. + * + * @param USBx USB instance. + * @param addr The Device address. + * @return None. + */ +void USB_SetDeviceAddr(USB_Type * USBx, uint8_t addr); + +/*! + * @brief Get Device address. + * + * @param USBx USB instance. + * @return The Device address. + */ +uint8_t USB_GetDeviceAddr(USB_Type * USBx); + +/*! + * @brief Get buffer descriptor table address. + * + * @param USBx USB instance. + * @return The BufDespTable address. + */ +uint32_t USB_GetBufDespTableAddr(USB_Type * USBx); + +/*! + * @brief Get the USB Frame Number. + * + * @param USBx USB instance. + * @return The USB Frame Number. + */ +uint32_t USB_GetFrameNumber(USB_Type * USBx); + +/*! + * @brief Get BufDesp after USB_INT_TOKENDONE interrupt happened and before clear USB_INT_TOKENDONE interrupt status. + * + * @param USBx USB instance. + * @return BufDesp address. + */ +USB_BufDesp_Type * USB_GetBufDesp(USB_Type * USBx); + +/*! + * @brief Get Token Pid from BufDesp before the BufDesp Reset. + * + * @param bd BufDesp addr. + * @return Token Pid. + */ +USB_TokenPid_Type USB_BufDesp_GetTokenPid(USB_BufDesp_Type * bd); + +/*! + * @brief Get packet addr from BufDesp before the BufDesp Reset. + * + * @param bd BufDesp addr. + * @return Packet addrress. + */ +uint32_t USB_BufDesp_GetPacketAddr(USB_BufDesp_Type * bd); + +/*! + * @brief Get packet size from BufDesp before the BufDesp Reset. + * + * @param bd BufDesp addr. + * @return Packet size. + */ +uint32_t USB_BufDesp_GetPacketSize(USB_BufDesp_Type * bd); + +/*! + * @brief Reset BufDesp. + * + * @param bd BufDesp addr. + * @return None. + */ +void USB_BufDesp_Reset(USB_BufDesp_Type * bd); + +/*! + * @brief Get EndPoint index after USB_INT_TOKENDONE interrupt happened and before clear USB_INT_TOKENDONE interrupt status. + * + * @param USBx USB instance. + * @return EndPoint index. + */ +uint32_t USB_GetEndPointIndex(USB_Type * USBx); + +/*! + * @brief Get Xfer Direction after USB_INT_TOKENDONE interrupt happened and before clear USB_INT_TOKENDONE interrupt status. + * + * @param USBx USB instance. + * @return Xfer Direction, See to @ref USB_Direction_Type. + */ +USB_Direction_Type USB_GetXferDirection(USB_Type * USBx); + +/*! + * @brief Get BufDesp OddEven after USB_INT_TOKENDONE interrupt happened and before clear USB_INT_TOKENDONE interrupt status. + * + * @param USBx USB instance. + * @return BufDesp OddEven. + */ +USB_BufDesp_OddEven_Type USB_GetBufDespOddEven(USB_Type * USBx); + +/*! + * @brief Enable the end point. + * + * @param USBx USB instance. + * @param index endpoint index. + * @param mode End point mode, See to @ref USB_EndPointMode_Type. + * @param enable 'true' to enable the EndPoint, 'false' to disable the EndPoint. + * @return None. + */ +void USB_EnableEndPoint(USB_Type * USBx, uint32_t index, USB_EndPointMode_Type mode, bool enable); + +/*! + * @brief Stall EndPoint n. + * + * @param USBx USB instance. + * @param ep_mask EndPoint mask, see to @ref USB_EP mask codes. + * @param enable 'true' to enable the EndPoint stall, 'false' to disable the EndPoint stall. + * @return None. + */ +void USB_EnableEndPointStall(USB_Type * USBx, uint32_t ep_mask, bool enable); + +/*! + * @brief Get Enabled EndPoint stall status. + * + * @param USBx USB instance. + * @return stall status, see to @ref USB_EP mask codes. + */ +uint32_t USB_GetEnabledEndPointStall(USB_Type * USBx); + +/*! + * @brief Xfer data by usb. + * + * @param bd BufDesp. + * @param data_n DATAn packet, n equal 0 or 1. + * @param data the address of data. + * @param len Data length. + * @return 'true': BufDesp can be xfer data, 'false': BufDesp is busy. + */ +bool USB_BufDesp_Xfer(USB_BufDesp_Type * bd, uint32_t data_n, uint8_t * data, uint32_t len); + +/*! + * @brief Check whether BufDesp is busy. + * + * @param bd BufDesp addr. + * @return 'true': BufDesp is busy, 'false': BufDesp is not busy. + */ +bool USB_BufDesp_IsBusy(USB_BufDesp_Type * bd); + + +/*! + *@} + */ + +#endif /* __HAL_USB_H__ */ + diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_usb_bdt.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_usb_bdt.h new file mode 100644 index 000000000..6dbb5fbf0 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_usb_bdt.h @@ -0,0 +1,78 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_USB_BDT_H__ +#define __HAL_USB_BDT_H__ + +#include "hal_common.h" + +/*! + * @addtogroup USB + * @{ + */ + +/*! + * @brief USB BufDesp EndPoint number. + */ +#define USB_BDT_EP_NUM 16u /*!< USB BufDesp EndPoint num. */ + +/*! + * @brief USB BufDesp EndPoint direction number. + */ +#define USB_BDT_DIRECTION_NUM 2u /*!< USB BufDesp EndPoint direction num. */ + +/*! + * @brief USB BufDesp EndPoint buffer number. + */ +#define USB_BDT_BUF_NUM 2u /*!< USB BufDesp EndPoint buffer num. */ + +/*! + * @brief This type of structure instance is used to implement the buffer descriptor for USB. + */ +typedef struct +{ + union + { + uint32_t HEAD; /*!< Head. */ + struct + { + uint32_t RESEVED0 :2; /*!< RESEVED. */ + uint32_t BDT_STALL :1; /*!< Stall. */ + uint32_t DTS :1; /*!< Data shift sync. */ + uint32_t NINC :1; /*!< DMA addr cannot increasing. */ + uint32_t KEEP :1; /*!< Keep BD held by USB. */ + uint32_t DATA :1; /*!< DATA0 or DATA1. */ + uint32_t OWN :1; /*!< Owner, 0 is CPU, 1 is USB. */ + uint32_t RESEVED1 :8; /*!< RESEVED. */ + uint32_t BC :10; /*!< Packet size. */ + uint32_t RESEVED2 :6; /*!< RESEVED. */ + }; + struct + { + uint32_t RESEVED3 :2; /*!< RESEVED. */ + uint32_t TOK_PID :4; /*!< Token pid. */ + uint32_t RESEVED4 :26; /*!< RESEVED. */ + }; + }; + uint32_t ADDR; /*!< Buffer addr. */ +} USB_BufDesp_Type; + +/*! + * @brief This type of structure instance is used to implement the buffer descriptor table for USB. + */ +typedef union +{ + USB_BufDesp_Type Table[USB_BDT_EP_NUM][ USB_BDT_DIRECTION_NUM][ USB_BDT_BUF_NUM]; /*!< [EndPoint] [Direction] [Odd_Even]. */ + USB_BufDesp_Type Index[USB_BDT_EP_NUM * USB_BDT_DIRECTION_NUM * USB_BDT_BUF_NUM]; /*!< Index. */ +} USB_BufDespTable_Type; + +/*! + * @} + */ + +#endif /* __HAL_USB_BDT_H__ */ + diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_wwdg.c b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_wwdg.c new file mode 100644 index 000000000..2cfd1b0c7 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_wwdg.c @@ -0,0 +1,56 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "hal_wwdg.h" + +void WWDG_Init(WWDG_Type * WWDGx, WWDG_Init_Type * init) +{ + if (NULL != init) + { + WWDGx->CFGR = WWDG_CFGR_WDGTB(init->Prescaler) + | WWDG_CFGR_W(init->UpperLimit); + } +} + +void WWDG_Start(WWDG_Type * WWDGx) +{ + WWDGx->CR |= WWDG_CR_WDGA_MASK; +} + +void WWDG_Reload(WWDG_Type * WWDGx, uint32_t value) +{ + if (value > WWDG_LOWER_LIMIT) + { + WWDGx->CR = (WWDGx->CR & ~WWDG_CR_T_MASK) | WWDG_CR_T(value); + } +} + +void WWDG_EnableInterrupts(WWDG_Type * WWDGx, uint32_t interrupts, bool enable) +{ + if ( (true == enable) && (WWDG_INT_ALMOST_TIMEOUT == interrupts) ) + { + WWDGx->CFGR |= WWDG_CFGR_EWI_MASK; + } + else + { + /* if WWDG_INT_ALMOST_TIMEOUT interrupt is enabled, only MCU reset can close it. */ + } +} + + +uint32_t WWDG_GetStatus(WWDG_Type * WWDGx) +{ + return WWDGx->SR; +} + +void WWDG_ClearStatus(WWDG_Type * WWDGx, uint32_t status) +{ + WWDGx->SR &= ~status; +} + + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_wwdg.h b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_wwdg.h new file mode 100644 index 000000000..b5fc015d3 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/drivers/hal_wwdg.h @@ -0,0 +1,133 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_WWDG_H__ +#define __HAL_WWDG_H__ + +/*! + * @addtogroup WWDG + * @{ + */ + +#include "hal_common.h" + +/*! + * @brief WWDG driver version number. + */ +#define WWDG_DRIVER_VERSION 0u /*!< WWDG_0. */ + +/*! + * @brief The lower limit value of WWDG counter. + */ +#define WWDG_LOWER_LIMIT 0x40u /*!< If WWDG counter Below this value, WWDG will generate a reset request. */ + +/*! + * @addtogroup WWDG_INT + * @brief WWDG_STATUS mask codes + * @{ + */ +#define WWDG_INT_ALMOST_TIMEOUT WWDG_CFGR_EWI_MASK /*!< WWDG interrupt: Almost timeout. */ +/*! + * @} + */ + +/*! + * @addtogroup WWDG_STATUS + * @brief WWDG_STATUS mask codes + * @{ + */ +#define WWDG_STATUS_ALMOST_TIMEOUT WWDG_SR_EWIF_MASK /*!< WWDG status: Almost timeout. */ +/*! + * @} + */ + +/*! + * @brief WWDG prescaler type. + * + * Select the prescaler of WWDG counter clock. + */ +typedef enum +{ + WWDG_Prescaler_1 = 0u, /*!< WWDG Prescaler 1. */ + WWDG_Prescaler_2 = 1u, /*!< WWDG Prescaler 2. */ + WWDG_Prescaler_4 = 2u, /*!< WWDG Prescaler 4. */ + WWDG_Prescaler_8 = 3u, /*!< WWDG Prescaler 8. */ +} WWDG_Prescaler_Type; + +/*! + * @brief This type of structure instance is used to keep the settings when calling the @ref WWDG_Init() to initialize the USB module. + */ +typedef struct +{ + WWDG_Prescaler_Type Prescaler; /*!< Specify the WWDG counter prescaler. */ + uint32_t UpperLimit; /*!< Specify the upperLimit, WWDG will generate a reset request if reload WWDG counter before the counter value greater than UpperLimit. */ +} WWDG_Init_Type; + +/*! + * @brief Initialize the WWDG module. + * + * @param WWDGx WWDG instance. + * @param init Pointer to the initialization structure. See to @ref WWDG_Init_Type. + * @return None. + */ +void WWDG_Init(WWDG_Type * WWDGx, WWDG_Init_Type * init); + +/*! + * @brief Start counting. + * + * If the counter is started, it cannot be stoped unless reset MCU. + * + * @param WWDGx WWDG instance. + * @return None. + */ +void WWDG_Start(WWDG_Type * WWDGx); + +/*! + * @brief Reolad WWDG counter (Feed dog). + * + * Reload WWDG counter to ensure that the counter value greater than WWDG_LOWER_LIMIT_VALUE and prevent generate a reset request. + * + * @param WWDGx WWDG instance. + * @param value The value of reload WWDG counter, the value ranges from 0x40 to 0x7f. + * @return None. + */ +void WWDG_Reload(WWDG_Type * WWDGx, uint32_t value); + +/*! + * @brief Enable interrupts of the WWDG module. + * + * @param WWDGx WWDG instance. + * @param interrupts Interrupt code masks. See to @ref WWDG_INT. + * @param enable 'true' to enable the indicated interrupts, 'false' has no effect. + * @return None. + */ +void WWDG_EnableInterrupts(WWDG_Type * WWDGx, uint32_t interrupts, bool enable); + +/*! + * @brief Get the status flags of the WWDG module. + * + * @param WWDGx WWDG instance. + * @return status flags. See to @ref WWDG_STATUS. + */ +uint32_t WWDG_GetStatus(WWDG_Type * WWDGx); + +/*! + * @brief Clear the status flags of the WWDG module. + * + * @param WWDGx WWDG instance. + * @param status status flags. See to @ref WWDG_STATUS. + * @return None. + */ +void WWDG_ClearStatus(WWDG_Type * WWDGx, uint32_t status); + +/*! + *@} + */ + +#endif /* __HAL_WWDG_H__. */ + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/hal_device_registers.h b/platform/vendor_bsp/MindMotion/MM32F527/hal_device_registers.h new file mode 100644 index 000000000..1dd7f7d40 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/hal_device_registers.h @@ -0,0 +1,16 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef __HAL_DEVICE_REGISTER_H__ +#define __HAL_DEVICE_REGISTER_H__ + + +#include "mm32f5277e.h" +#include "mm32f5277e_features.h" +#include "system_mm32f5277e.h" +#endif /* __HAL_DEVICE_REGISTER_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/mm32f5277e.h b/platform/vendor_bsp/MindMotion/MM32F527/mm32f5277e.h new file mode 100644 index 000000000..6f54c6076 --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/mm32f5277e.h @@ -0,0 +1,11662 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef __MM32F5277E_H__ +#define __MM32F5277E_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* ----------------------------------------------------------------------------- + -- Interrupt vector numbers + ----------------------------------------------------------------------------- */ + +/*! +* @addtogroup Interrupt_vector_numbers Interrupt vector numbers + +* @{ +*/ + +/** Interrupt Number Definitions */ + +#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */ + +typedef enum IRQ { + Reset_IRQn = -15, /*!< reset */ + NMI_IRQn = -14, /*!< Non-Maskable Interrupt/RCC Clock Security System (CSS) connected to NMI vector */ + HardFault_IRQn = -13, /*!< All types of failures */ + MemManage_IRQn = -12, /*!< memory management */ + BusFault_IRQn = -11, /*!< Prefetch failed, memory access failed */ + UsageFault_IRQn = -10, /*!< undefined instruction or illegal status */ + SVCall_IRQn = -5, /*!< System service calls via SWI instructions */ + DebugMonitor_IRQn = -4, /*!< debug monitor */ + PendSV_IRQn = -2, /*!< Suspendable system services */ + SysTick_IRQn = -1, /*!< System tick timer */ + WWDG_IWDG_IRQn = 0, /*!< Watchdog interrupt (IWDG is EXTI21) */ + PVD_IRQn = 1, /*!< Supply Voltage Detect (PVD) Interrupt (EXTI16) */ + BKP_TAMPER_IRQn = 2, /*!< BKP intrusion detection interrupted */ + RTC_IRQn = 3, /*!< RTC global interrupt */ + FLASH_IRQn = 4, /*!< Flash Global Interrupt */ + RCC_CRS_IRQn = 5, /*!< RCC and CRS global interrupt */ + EXTI0_IRQn = 6, /*!< EXTI line 0 interrupt */ + EXTI1_IRQn = 7, /*!< EXTI line 1 interrupt */ + EXTI2_IRQn = 8, /*!< EXTI line 2 interrupt */ + EXTI3_IRQn = 9, /*!< EXTI line 3 interrupt */ + EXTI4_IRQn = 10, /*!< EXTI line 4 interrupt */ + DMA1_CH1_IRQn = 11, /*!< DMA1 channel 1 global interrupt */ + DMA1_CH2_IRQn = 12, /*!< DMA1 channel 2 global interrupt */ + DMA1_CH3_IRQn = 13, /*!< DMA1 channel 3 global interrupt */ + DMA1_CH4_IRQn = 14, /*!< DMA1 channel 4 global interrupt */ + DMA1_CH5_IRQn = 15, /*!< DMA1 channel 5 global interrupt */ + DMA1_CH6_IRQn = 16, /*!< DMA1 channel 6 global interrupt */ + DMA1_CH7_IRQn = 17, /*!< DMA1 channel 7 global interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1/2 global interrupt */ + DMA1_CH8_IRQn = 20, /*!< DMA1 channel 8 global interrupt */ + FlexCAN1_IRQn = 21, /*!< FlexCAN1 global interrupt */ + EXTI9_5_IRQn = 23, /*!< EXTI line[9:5] interrupt */ + TIM1_BRK_IRQn = 24, /*!< TIM1 brake interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 update interrupted */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 trigger/COM interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 capture compare interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global interrupt */ + I2C1_IRQn = 31, /*!< I2C1 global interrupt */ + I2C2_IRQn = 33, /*!< I2C2 global interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global interrupt */ + UART1_IRQn = 37, /*!< UART1 global interrupt */ + UART2_IRQn = 38, /*!< UART2 global interrupt */ + UART3_IRQn = 39, /*!< UART3 global interrupt */ + EXTI15_10_IRQn = 40, /*!< Interrupt on EXTI line[15:10] */ + RTC_ALR_IRQn = 41, /*!< RTC Alarm Interrupt (EXTI17) */ + USB_WKUP_IRQn = 42, /*!< USB Wakeup Interrupt (EXTI18) */ + TIM8_BRK_IRQn = 43, /*!< TIM8 brake interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 update interrupted */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 trigger/COM interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 capture compare interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global interrupt */ + UART4_IRQn = 52, /*!< UART4 global interrupt */ + UART5_IRQn = 53, /*!< UART5 global interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_CH1_IRQn = 56, /*!< DMA2 channel 1 global interrupt */ + DMA2_CH2_IRQn = 57, /*!< DMA2 channel 2 global interrupt */ + DMA2_CH3_IRQn = 58, /*!< DMA2 channel 3 global interrupt */ + DMA2_CH4_IRQn = 59, /*!< DMA2 channel 4 global interrupt */ + DMA2_CH5_IRQn = 60, /*!< DMA2 channel 5 global interrupt */ + ENET_IRQn = 61, /*!< ENET global interrupt */ + ENET_WKUP_IRQn = 62, /*!< ENET wake-up interrupt (EXTI25) */ + COMP_IRQn = 64, /*!< Comparator 1/2/3 Global Interrupts (EXTI19/20/24) */ + FlexCAN2_IRQn = 65, /*!< FLexCAN2 global interrupt */ + USB_FS_IRQn = 67, /*!< USB OTG global interrupt */ + DMA2_CH6_IRQn = 68, /*!< DMA2 channel 6 global interrupt */ + DMA2_CH7_IRQn = 69, /*!< DMA2 channel 7 global interrupt */ + DMA2_CH8_IRQn = 70, /*!< DMA2 channel 8 global interrupt */ + UART6_IRQn = 71, /*!< UART6 global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + QSPI_IRQn = 95, /*!< QSPI global interrupt */ + LPTIM_IRQn = 102, /*!< LPTIM global interrupt (EXTI22) */ + LPUART_IRQn = 104, /*!< LPUART global interrupt (EXTI23) */ +} IRQn_Type; + +/*! + + * @} + */ /* end of group Interrupt_vector_numbers */ + + + +/* ----------------------------------------------------------------------------- + -- STAR MC1 Core Configuration + ----------------------------------------------------------------------------- */ + +/*! + * @addtogroup Core_Configuration STAR MC1 Core Configuration + * @{ + */ +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +#define __STAR_REV 0x0100U /* Core revision r1p0 */ +#define __SAUREGION_PRESENT 0U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ +#define __ICACHE_PRESENT 1U /* Define if an ICACHE is present or not */ +#define __DCACHE_PRESENT 1U /* Define if an DCACHE is present or not */ + +#include "core_star.h" /* Core Peripheral Access Layer */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + + +/* ----------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ----------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + + */ + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif +/* Define the base address of the large memory block mapping */ + +#define FLASH_ADDR_BASE 0x08000000u +#define SRAM_BASE 0x30000000u + +#define APB1_BASE 0x40000000u +#define APB2_BASE 0x40010000u +#define AHB1_BASE 0x40020000u +#define AHB1_1_BASE 0x40040000u +#define AHB2_BASE 0x50000000u +#define AHB3_BASE 0x60000000u +#define AHB3_1_BASE 0x64000000u +#define AHB3_2_BASE 0x68000000u +#define AHB3_3_BASE 0x6C000000u +#define AHB4_BASE 0x90000000u +#define AHB4_1_BASE 0xA0000000u + + +/* Define the mapping base address of the peripheral module */ +#define TIM2_BASE (APB1_BASE + 0x0000 ) +#define TIM3_BASE (APB1_BASE + 0x0400 ) +#define TIM4_BASE (APB1_BASE + 0x0800 ) +#define TIM5_BASE (APB1_BASE + 0x0C00 ) +#define TIM6_BASE (APB1_BASE + 0x1000 ) +#define TIM7_BASE (APB1_BASE + 0x1400 ) +#define RTC_BKP_BASE (APB1_BASE + 0x2800 ) +#define WWDG_BASE (APB1_BASE + 0x2C00 ) +#define IWDG_BASE (APB1_BASE + 0x3000 ) +#define SPI2_BASE (APB1_BASE + 0x3800 ) +#define SPI3_BASE (APB1_BASE + 0x3C00 ) +#define UART2_BASE (APB1_BASE + 0x4400 ) +#define UART3_BASE (APB1_BASE + 0x4800 ) +#define UART4_BASE (APB1_BASE + 0x4C00 ) +#define UART5_BASE (APB1_BASE + 0x5000 ) +#define I2C1_BASE (APB1_BASE + 0x5400 ) +#define I2C2_BASE (APB1_BASE + 0x5800 ) +#define CRS_BASE (APB1_BASE + 0x6C00 ) +#define PWR_BASE (APB1_BASE + 0x7000 ) +#define DBGMCU_BASE (APB1_BASE + 0x7080 ) +#define DAC_BASE (APB1_BASE + 0x7400 ) +#define UART7_BASE (APB1_BASE + 0x7800 ) +#define FLEXCAN1_BASE (APB1_BASE + 0xC000 ) + +#define SYSCFG_BASE (APB2_BASE + 0x0000 ) +#define EXTI_BASE (APB2_BASE + 0x0400 ) +#define LPUART_BASE (APB2_BASE + 0x0800 ) +#define ADC1_BASE (APB2_BASE + 0x2400 ) +#define ADC2_BASE (APB2_BASE + 0x2800 ) +#define TIM1_BASE (APB2_BASE + 0x2C00 ) +#define SPI1_BASE (APB2_BASE + 0x3000 ) +#define TIM8_BASE (APB2_BASE + 0x3400 ) +#define UART1_BASE (APB2_BASE + 0x3800 ) +#define UART6_BASE (APB2_BASE + 0x3C00 ) +#define COMP_BASE (APB2_BASE + 0x4000 ) +#define FLEXCAN2_BASE (APB2_BASE + 0x8000 ) +#define LPTIM_BASE (APB2_BASE + 0xD000 ) +#define MDS_BASE (APB2_BASE + 0xFC00 ) + +#define DMA1_BASE (AHB1_BASE + 0x0000 ) +#define DMA2_BASE (AHB1_BASE + 0x0400 ) +#define RCC_BASE (AHB1_BASE + 0x1000 ) +#define FLASH_BASE (AHB1_BASE + 0x2000 ) +#define CRC_BASE (AHB1_BASE + 0x3000 ) +#define ENET_BASE (AHB1_BASE + 0x8000 ) +#define CORDIC_BASE (AHB1_BASE + 0xA000 ) + +#define GPIOA_BASE (AHB1_1_BASE + 0x0000 ) +#define GPIOB_BASE (AHB1_1_BASE + 0x0400 ) +#define GPIOC_BASE (AHB1_1_BASE + 0x0800 ) +#define GPIOD_BASE (AHB1_1_BASE + 0x0C00 ) +#define GPIOE_BASE (AHB1_1_BASE + 0x1000 ) +#define GPIOF_BASE (AHB1_1_BASE + 0x1400 ) +#define GPIOG_BASE (AHB1_1_BASE + 0x1800 ) +#define GPIOH_BASE (AHB1_1_BASE + 0x1C00 ) +#define GPIOI_BASE (AHB1_1_BASE + 0x2000 ) + +#define USB_BASE (AHB2_BASE + 0x0000 ) + +#define FSMC_BANK0_BASE (AHB3_BASE + 0x0000 ) + +#define FSMC_BANK1_BASE (AHB3_1_BASE + 0x0000 ) + +#define FSMC_BANK2_BASE (AHB3_2_BASE + 0x0000 ) + +#define FSMC_BANK3_BASE (AHB3_3_BASE + 0x0000 ) + +#define QSPI_M_BASE (AHB4_BASE + 0x0000 ) + +#define FSMC_BASE (AHB4_1_BASE + 0x0000 ) +#define QSPI_BASE (AHB4_1_BASE + 0x1000 ) +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * ADC Type + ******************************************************************************/ +typedef struct { + __IO uint32_t ADDATA; ///< A/D data register offset: 0x00 + __IO uint32_t ADCFG; ///< A/D Configuration Register offset: 0x04 + __IO uint32_t ADCR; ///< A/D Control Register offset: 0x08 + __IO uint32_t ADCHS; ///< A/D Channel Select Register offset: 0x0C + __IO uint32_t ADCMPR; ///< A/D Analog Watchdog Compare Register offset: 0x10 + __IO uint32_t ADSTA; ///< A/D Status Register offset: 0x14 + __IO uint32_t ADDR[16]; ///< A/D Channel Data Register offset: 0x18 + __IO uint32_t ADSTAEXT; ///< A/D Extended Status Register offset: 0x58 + __IO uint32_t CHANY0; ///< A/D any channel channel select register 0 offset: 0x5C + __IO uint32_t CHANY1; ///< A/D arbitrary channel channel selection register 1offset: 0x60 + __IO uint32_t ANYCFG; ///< A/D Arbitrary Channel Configuration Register offset: 0x64 + __IO uint32_t ANYCR; ///< A/D arbitrary channel control register offset: 0x68 + __IO uint32_t ADCFG2; ///< ADC Configuration Register offset: 0x6C + __IO uint32_t SMPR1; ///< A/D Sampling Configuration Register 1 offset: 0x70 + __IO uint32_t SMPR2; ///< A/D Sampling Configuration Register 2 offset: 0x74 + __IO uint32_t SMPR3; ///< A/D Sampling Configuration Register 2 offset: 0x78 + __IO uint32_t JOFR[4]; ///< A/D Injection Channel Data Compensation Registeroffset: 0x7C + __IO uint32_t JSQR; ///< A/D injection channel sequence register offset: 0x8C + __IO uint32_t JADDATA; ///< A/D injection data register offset: 0x90 + __IO uint32_t Reserved1[7]; ///< Reserved + __IO uint32_t JDR[4]; ///< A/D injection channel data register offset: 0xB0 +} ADC_Type; + +/******************************************************************************* + * ADC Type + ******************************************************************************/ + +/*! + * @addtogroup ADC_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief ADC_ADDATA Register Bit Definition + */ + +#define ADC_ADDATA_CHANNELSELH_SHIFT (22) +#define ADC_ADDATA_CHANNELSELH_MASK (0x01U << ADC_ADDATA_CHANNELSELH_SHIFT) +#define ADC_ADDATA_CHANNELSELH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADDATA_CHANNELSELH_SHIFT)) & ADC_ADDATA_CHANNELSELH_MASK) + +#define ADC_ADDATA_VALID_SHIFT (21) +#define ADC_ADDATA_VALID_MASK (0x01U << ADC_ADDATA_VALID_SHIFT) +#define ADC_ADDATA_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADDATA_VALID_SHIFT)) & ADC_ADDATA_VALID_MASK) + +#define ADC_ADDATA_OVERRUN_SHIFT (20) +#define ADC_ADDATA_OVERRUN_MASK (0x01U << ADC_ADDATA_OVERRUN_SHIFT) +#define ADC_ADDATA_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADDATA_OVERRUN_SHIFT)) & ADC_ADDATA_OVERRUN_MASK) + +#define ADC_ADDATA_CHANNELSEL_SHIFT (16) +#define ADC_ADDATA_CHANNELSEL_MASK (0xFU << ADC_ADDATA_CHANNELSEL_SHIFT) +#define ADC_ADDATA_CHANNELSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADDATA_CHANNELSEL_SHIFT)) & ADC_ADDATA_CHANNELSEL_MASK) + +#define ADC_ADDATA_DATA_SHIFT (0) +#define ADC_ADDATA_DATA_MASK (0xFFFFU << ADC_ADDATA_DATA_SHIFT) +#define ADC_ADDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADDATA_DATA_SHIFT)) & ADC_ADDATA_DATA_MASK) + +/*! + * @brief ADC_ADCFG Register Bit Definition + */ + +#define ADC_ADCFG_JAWDEN_SHIFT (16) +#define ADC_ADCFG_JAWDEN_MASK (0x01U << ADC_ADCFG_JAWDEN_SHIFT) +#define ADC_ADCFG_JAWDEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCFG_JAWDEN_SHIFT)) & ADC_ADCFG_JAWDEN_MASK) + +#define ADC_ADCFG_RSLTCTL_SHIFT (7) +#define ADC_ADCFG_RSLTCTL_MASK (0x7U << ADC_ADCFG_RSLTCTL_SHIFT) +#define ADC_ADCFG_RSLTCTL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCFG_RSLTCTL_SHIFT)) & ADC_ADCFG_RSLTCTL_MASK) + +#define ADC_ADCFG_VSEN_SHIFT (3) +#define ADC_ADCFG_VSEN_MASK (0x01U << ADC_ADCFG_VSEN_SHIFT) +#define ADC_ADCFG_VSEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCFG_VSEN_SHIFT)) & ADC_ADCFG_VSEN_MASK) + +#define ADC_ADCFG_TSEN_SHIFT (2) +#define ADC_ADCFG_TSEN_MASK (0x01U << ADC_ADCFG_TSEN_SHIFT) +#define ADC_ADCFG_TSEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCFG_TSEN_SHIFT)) & ADC_ADCFG_TSEN_MASK) + +#define ADC_ADCFG_AWDEN_SHIFT (1) +#define ADC_ADCFG_AWDEN_MASK (0x01U << ADC_ADCFG_AWDEN_SHIFT) +#define ADC_ADCFG_AWDEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCFG_AWDEN_SHIFT)) & ADC_ADCFG_AWDEN_MASK) + +#define ADC_ADCFG_ADEN_SHIFT (0) +#define ADC_ADCFG_ADEN_MASK (0x01U << ADC_ADCFG_ADEN_SHIFT) +#define ADC_ADCFG_ADEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCFG_ADEN_SHIFT)) & ADC_ADCFG_ADEN_MASK) + +/*! + * @brief ADC_ADCR Register Bit Definition + */ + +#define ADC_ADCR_CMPCHH_SHIFT (28) +#define ADC_ADCR_CMPCHH_MASK (0x01U << ADC_ADCR_CMPCHH_SHIFT) +#define ADC_ADCR_CMPCHH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCR_CMPCHH_SHIFT)) & ADC_ADCR_CMPCHH_MASK) + +#define ADC_ADCR_EOCIE_SHIFT (27) +#define ADC_ADCR_EOCIE_MASK (0x01U << ADC_ADCR_EOCIE_SHIFT) +#define ADC_ADCR_EOCIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCR_EOCIE_SHIFT)) & ADC_ADCR_EOCIE_MASK) + +#define ADC_ADCR_EOSMPIE_SHIFT (26) +#define ADC_ADCR_EOSMPIE_MASK (0x01U << ADC_ADCR_EOSMPIE_SHIFT) +#define ADC_ADCR_EOSMPIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCR_EOSMPIE_SHIFT)) & ADC_ADCR_EOSMPIE_MASK) + +#define ADC_ADCR_TRGEDGE_SHIFT (24) +#define ADC_ADCR_TRGEDGE_MASK (0x3U << ADC_ADCR_TRGEDGE_SHIFT) +#define ADC_ADCR_TRGEDGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCR_TRGEDGE_SHIFT)) & ADC_ADCR_TRGEDGE_MASK) + +#define ADC_ADCR_TRGSHIFT_SHIFT (19) +#define ADC_ADCR_TRGSHIFT_MASK (0x7U << ADC_ADCR_TRGSHIFT_SHIFT) +#define ADC_ADCR_TRGSHIFT(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCR_TRGSHIFT_SHIFT)) & ADC_ADCR_TRGSHIFT_MASK) + +#define ADC_ADCR_SCANDIR_SHIFT (16) +#define ADC_ADCR_SCANDIR_MASK (0x01U << ADC_ADCR_SCANDIR_SHIFT) +#define ADC_ADCR_SCANDIR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCR_SCANDIR_SHIFT)) & ADC_ADCR_SCANDIR_MASK) + +#define ADC_ADCR_CMPCHL_SHIFT (12) +#define ADC_ADCR_CMPCHL_MASK (0xFU << ADC_ADCR_CMPCHL_SHIFT) +#define ADC_ADCR_CMPCHL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCR_CMPCHL_SHIFT)) & ADC_ADCR_CMPCHL_MASK) + +#define ADC_ADCR_ALIGN_SHIFT (11) +#define ADC_ADCR_ALIGN_MASK (0x01U << ADC_ADCR_ALIGN_SHIFT) +#define ADC_ADCR_ALIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCR_ALIGN_SHIFT)) & ADC_ADCR_ALIGN_MASK) + +#define ADC_ADCR_ADMD_SHIFT (9) +#define ADC_ADCR_ADMD_MASK (0x3U << ADC_ADCR_ADMD_SHIFT) +#define ADC_ADCR_ADMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCR_ADMD_SHIFT)) & ADC_ADCR_ADMD_MASK) + +#define ADC_ADCR_ADST_SHIFT (8) +#define ADC_ADCR_ADST_MASK (0x01U << ADC_ADCR_ADST_SHIFT) +#define ADC_ADCR_ADST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCR_ADST_SHIFT)) & ADC_ADCR_ADST_MASK) + +#define ADC_ADCR_DMAEN_SHIFT (3) +#define ADC_ADCR_DMAEN_MASK (0x01U << ADC_ADCR_DMAEN_SHIFT) +#define ADC_ADCR_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCR_DMAEN_SHIFT)) & ADC_ADCR_DMAEN_MASK) + +#define ADC_ADCR_TRGEN_SHIFT (2) +#define ADC_ADCR_TRGEN_MASK (0x01U << ADC_ADCR_TRGEN_SHIFT) +#define ADC_ADCR_TRGEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCR_TRGEN_SHIFT)) & ADC_ADCR_TRGEN_MASK) + +#define ADC_ADCR_AWDIE_SHIFT (1) +#define ADC_ADCR_AWDIE_MASK (0x01U << ADC_ADCR_AWDIE_SHIFT) +#define ADC_ADCR_AWDIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCR_AWDIE_SHIFT)) & ADC_ADCR_AWDIE_MASK) + +#define ADC_ADCR_EOSIE_SHIFT (0) +#define ADC_ADCR_EOSIE_MASK (0x01U << ADC_ADCR_EOSIE_SHIFT) +#define ADC_ADCR_EOSIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCR_EOSIE_SHIFT)) & ADC_ADCR_EOSIE_MASK) + +/*! + * @brief ADC_ADCHS Register Bit Definition + */ + +#define ADC_ADCHS_CHEN15_SHIFT (15) +#define ADC_ADCHS_CHEN15_MASK (0x01U << ADC_ADCHS_CHEN15_SHIFT) +#define ADC_ADCHS_CHEN15(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCHS_CHEN15_SHIFT)) & ADC_ADCHS_CHEN15_MASK) + +#define ADC_ADCHS_CHEN14_SHIFT (14) +#define ADC_ADCHS_CHEN14_MASK (0x01U << ADC_ADCHS_CHEN14_SHIFT) +#define ADC_ADCHS_CHEN14(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCHS_CHEN14_SHIFT)) & ADC_ADCHS_CHEN14_MASK) + +#define ADC_ADCHS_CHEN13_SHIFT (13) +#define ADC_ADCHS_CHEN13_MASK (0x01U << ADC_ADCHS_CHEN13_SHIFT) +#define ADC_ADCHS_CHEN13(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCHS_CHEN13_SHIFT)) & ADC_ADCHS_CHEN13_MASK) + +#define ADC_ADCHS_CHEN12_SHIFT (12) +#define ADC_ADCHS_CHEN12_MASK (0x01U << ADC_ADCHS_CHEN12_SHIFT) +#define ADC_ADCHS_CHEN12(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCHS_CHEN12_SHIFT)) & ADC_ADCHS_CHEN12_MASK) + +#define ADC_ADCHS_CHEN11_SHIFT (11) +#define ADC_ADCHS_CHEN11_MASK (0x01U << ADC_ADCHS_CHEN11_SHIFT) +#define ADC_ADCHS_CHEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCHS_CHEN11_SHIFT)) & ADC_ADCHS_CHEN11_MASK) + +#define ADC_ADCHS_CHEN10_SHIFT (10) +#define ADC_ADCHS_CHEN10_MASK (0x01U << ADC_ADCHS_CHEN10_SHIFT) +#define ADC_ADCHS_CHEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCHS_CHEN10_SHIFT)) & ADC_ADCHS_CHEN10_MASK) + +#define ADC_ADCHS_CHEN9_SHIFT (9) +#define ADC_ADCHS_CHEN9_MASK (0x01U << ADC_ADCHS_CHEN9_SHIFT) +#define ADC_ADCHS_CHEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCHS_CHEN9_SHIFT)) & ADC_ADCHS_CHEN9_MASK) + +#define ADC_ADCHS_CHEN8_SHIFT (8) +#define ADC_ADCHS_CHEN8_MASK (0x01U << ADC_ADCHS_CHEN8_SHIFT) +#define ADC_ADCHS_CHEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCHS_CHEN8_SHIFT)) & ADC_ADCHS_CHEN8_MASK) + +#define ADC_ADCHS_CHEN7_SHIFT (7) +#define ADC_ADCHS_CHEN7_MASK (0x01U << ADC_ADCHS_CHEN7_SHIFT) +#define ADC_ADCHS_CHEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCHS_CHEN7_SHIFT)) & ADC_ADCHS_CHEN7_MASK) + +#define ADC_ADCHS_CHEN6_SHIFT (6) +#define ADC_ADCHS_CHEN6_MASK (0x01U << ADC_ADCHS_CHEN6_SHIFT) +#define ADC_ADCHS_CHEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCHS_CHEN6_SHIFT)) & ADC_ADCHS_CHEN6_MASK) + +#define ADC_ADCHS_CHEN5_SHIFT (5) +#define ADC_ADCHS_CHEN5_MASK (0x01U << ADC_ADCHS_CHEN5_SHIFT) +#define ADC_ADCHS_CHEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCHS_CHEN5_SHIFT)) & ADC_ADCHS_CHEN5_MASK) + +#define ADC_ADCHS_CHEN4_SHIFT (4) +#define ADC_ADCHS_CHEN4_MASK (0x01U << ADC_ADCHS_CHEN4_SHIFT) +#define ADC_ADCHS_CHEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCHS_CHEN4_SHIFT)) & ADC_ADCHS_CHEN4_MASK) + +#define ADC_ADCHS_CHEN3_SHIFT (3) +#define ADC_ADCHS_CHEN3_MASK (0x01U << ADC_ADCHS_CHEN3_SHIFT) +#define ADC_ADCHS_CHEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCHS_CHEN3_SHIFT)) & ADC_ADCHS_CHEN3_MASK) + +#define ADC_ADCHS_CHEN2_SHIFT (2) +#define ADC_ADCHS_CHEN2_MASK (0x01U << ADC_ADCHS_CHEN2_SHIFT) +#define ADC_ADCHS_CHEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCHS_CHEN2_SHIFT)) & ADC_ADCHS_CHEN2_MASK) + +#define ADC_ADCHS_CHEN1_SHIFT (1) +#define ADC_ADCHS_CHEN1_MASK (0x01U << ADC_ADCHS_CHEN1_SHIFT) +#define ADC_ADCHS_CHEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCHS_CHEN1_SHIFT)) & ADC_ADCHS_CHEN1_MASK) + +#define ADC_ADCHS_CHEN0_SHIFT (0) +#define ADC_ADCHS_CHEN0_MASK (0x01U << ADC_ADCHS_CHEN0_SHIFT) +#define ADC_ADCHS_CHEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCHS_CHEN0_SHIFT)) & ADC_ADCHS_CHEN0_MASK) + +/*! + * @brief ADC_ADCMPR Register Bit Definition + */ + +#define ADC_ADCMPR_CMPHDATA_SHIFT (16) +#define ADC_ADCMPR_CMPHDATA_MASK (0xFFFU << ADC_ADCMPR_CMPHDATA_SHIFT) +#define ADC_ADCMPR_CMPHDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCMPR_CMPHDATA_SHIFT)) & ADC_ADCMPR_CMPHDATA_MASK) + +#define ADC_ADCMPR_CMPLDATA_SHIFT (0) +#define ADC_ADCMPR_CMPLDATA_MASK (0xFFFU << ADC_ADCMPR_CMPLDATA_SHIFT) +#define ADC_ADCMPR_CMPLDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCMPR_CMPLDATA_SHIFT)) & ADC_ADCMPR_CMPLDATA_MASK) + +/*! + * @brief ADC_ADSTA Register Bit Definition + */ + +#define ADC_ADSTA_OVERRUN_SHIFT (20) +#define ADC_ADSTA_OVERRUN_MASK (0xFFFU << ADC_ADSTA_OVERRUN_SHIFT) +#define ADC_ADSTA_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTA_OVERRUN_SHIFT)) & ADC_ADSTA_OVERRUN_MASK) + +#define ADC_ADSTA_VALID_SHIFT (8) +#define ADC_ADSTA_VALID_MASK (0xFFFU << ADC_ADSTA_VALID_SHIFT) +#define ADC_ADSTA_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTA_VALID_SHIFT)) & ADC_ADSTA_VALID_MASK) + +#define ADC_ADSTA_CHANNELL_SHIFT (4) +#define ADC_ADSTA_CHANNELL_MASK (0xFU << ADC_ADSTA_CHANNELL_SHIFT) +#define ADC_ADSTA_CHANNELL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTA_CHANNELL_SHIFT)) & ADC_ADSTA_CHANNELL_MASK) + +#define ADC_ADSTA_CHANNELH_SHIFT (3) +#define ADC_ADSTA_CHANNELH_MASK (0x01U << ADC_ADSTA_CHANNELH_SHIFT) +#define ADC_ADSTA_CHANNELH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTA_CHANNELH_SHIFT)) & ADC_ADSTA_CHANNELH_MASK) + +#define ADC_ADSTA_BUSY_SHIFT (2) +#define ADC_ADSTA_BUSY_MASK (0x01U << ADC_ADSTA_BUSY_SHIFT) +#define ADC_ADSTA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTA_BUSY_SHIFT)) & ADC_ADSTA_BUSY_MASK) + +#define ADC_ADSTA_AWDIF_SHIFT (1) +#define ADC_ADSTA_AWDIF_MASK (0x01U << ADC_ADSTA_AWDIF_SHIFT) +#define ADC_ADSTA_AWDIF(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTA_AWDIF_SHIFT)) & ADC_ADSTA_AWDIF_MASK) + +#define ADC_ADSTA_EOSIF_SHIFT (0) +#define ADC_ADSTA_EOSIF_MASK (0x01U << ADC_ADSTA_EOSIF_SHIFT) +#define ADC_ADSTA_EOSIF(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTA_EOSIF_SHIFT)) & ADC_ADSTA_EOSIF_MASK) + +/*! + * @brief ADC_ADDR Register Bit Definition + */ + +#define ADC_ADDR_VALID_SHIFT (21) +#define ADC_ADDR_VALID_MASK (0x01U << ADC_ADDR_VALID_SHIFT) +#define ADC_ADDR_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADDR_VALID_SHIFT)) & ADC_ADDR_VALID_MASK) + +#define ADC_ADDR_OVERRUN_SHIFT (20) +#define ADC_ADDR_OVERRUN_MASK (0x01U << ADC_ADDR_OVERRUN_SHIFT) +#define ADC_ADDR_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADDR_OVERRUN_SHIFT)) & ADC_ADDR_OVERRUN_MASK) + +#define ADC_ADDR_DATA_SHIFT (0) +#define ADC_ADDR_DATA_MASK (0xFFFFU << ADC_ADDR_DATA_SHIFT) +#define ADC_ADDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADDR_DATA_SHIFT)) & ADC_ADDR_DATA_MASK) + +/*! + * @brief ADC_ADSTA_EXT Register Bit Definition + */ + +#define ADC_ADSTAEXT_FREOCIF_SHIFT (26) +#define ADC_ADSTAEXT_FREOCIF_MASK (0x01U << ADC_ADSTAEXT_FREOCIF_SHIFT) +#define ADC_ADSTAEXT_FREOCIF(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTAEXT_FREOCIF_SHIFT)) & ADC_ADSTAEXT_FREOCIF_MASK) + +#define ADC_ADSTAEXT_CALBUSY_SHIFT (25) +#define ADC_ADSTAEXT_CALBUSY_MASK (0x01U << ADC_ADSTAEXT_CALBUSY_SHIFT) +#define ADC_ADSTAEXT_CALBUSY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTAEXT_CALBUSY_SHIFT)) & ADC_ADSTAEXT_CALBUSY_MASK) + +#define ADC_ADSTAEXT_EOCALIF_SHIFT (24) +#define ADC_ADSTAEXT_EOCALIF_MASK (0x01U << ADC_ADSTAEXT_EOCALIF_SHIFT) +#define ADC_ADSTAEXT_EOCALIF(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTAEXT_EOCALIF_SHIFT)) & ADC_ADSTAEXT_EOCALIF_MASK) + +#define ADC_ADSTAEXT_JBUSY_SHIFT (21) +#define ADC_ADSTAEXT_JBUSY_MASK (0x01U << ADC_ADSTAEXT_JBUSY_SHIFT) +#define ADC_ADSTAEXT_JBUSY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTAEXT_JBUSY_SHIFT)) & ADC_ADSTAEXT_JBUSY_MASK) + +#define ADC_ADSTAEXT_JEOSIF_SHIFT (20) +#define ADC_ADSTAEXT_JEOSIF_MASK (0x01U << ADC_ADSTAEXT_JEOSIF_SHIFT) +#define ADC_ADSTAEXT_JEOSIF(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTAEXT_JEOSIF_SHIFT)) & ADC_ADSTAEXT_JEOSIF_MASK) + +#define ADC_ADSTAEXT_JEOCIF_SHIFT (19) +#define ADC_ADSTAEXT_JEOCIF_MASK (0x01U << ADC_ADSTAEXT_JEOCIF_SHIFT) +#define ADC_ADSTAEXT_JEOCIF(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTAEXT_JEOCIF_SHIFT)) & ADC_ADSTAEXT_JEOCIF_MASK) + +#define ADC_ADSTAEXT_JEOSMPIF_SHIFT (18) +#define ADC_ADSTAEXT_JEOSMPIF_MASK (0x01U << ADC_ADSTAEXT_JEOSMPIF_SHIFT) +#define ADC_ADSTAEXT_JEOSMPIF(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTAEXT_JEOSMPIF_SHIFT)) & ADC_ADSTAEXT_JEOSMPIF_MASK) + +#define ADC_ADSTAEXT_EOCIF_SHIFT (17) +#define ADC_ADSTAEXT_EOCIF_MASK (0x01U << ADC_ADSTAEXT_EOCIF_SHIFT) +#define ADC_ADSTAEXT_EOCIF(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTAEXT_EOCIF_SHIFT)) & ADC_ADSTAEXT_EOCIF_MASK) + +#define ADC_ADSTAEXT_EOSMPIF_SHIFT (16) +#define ADC_ADSTAEXT_EOSMPIF_MASK (0x01U << ADC_ADSTAEXT_EOSMPIF_SHIFT) +#define ADC_ADSTAEXT_EOSMPIF(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTAEXT_EOSMPIF_SHIFT)) & ADC_ADSTAEXT_EOSMPIF_MASK) + +#define ADC_ADSTAEXT_OVERRUN_SHIFT (4) +#define ADC_ADSTAEXT_OVERRUN_MASK (0xFU << ADC_ADSTAEXT_OVERRUN_SHIFT) +#define ADC_ADSTAEXT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTAEXT_OVERRUN_SHIFT)) & ADC_ADSTAEXT_OVERRUN_MASK) + +#define ADC_ADSTAEXT_VALID_SHIFT (0) +#define ADC_ADSTAEXT_VALID_MASK (0xFU << ADC_ADSTAEXT_VALID_SHIFT) +#define ADC_ADSTAEXT_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADSTAEXT_VALID_SHIFT)) & ADC_ADSTAEXT_VALID_MASK) + +/*! + * @brief ADC_CHANY0 Register Bit Definition + */ + +#define ADC_CHANY0_CHANYSELL7_SHIFT (28) +#define ADC_CHANY0_CHANYSELL7_MASK (0xFU << ADC_CHANY0_CHANYSELL7_SHIFT) +#define ADC_CHANY0_CHANYSELL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHANY0_CHANYSELL7_SHIFT)) & ADC_CHANY0_CHANYSELL7_MASK) + +#define ADC_CHANY0_CHANYSELL6_SHIFT (24) +#define ADC_CHANY0_CHANYSELL6_MASK (0xFU << ADC_CHANY0_CHANYSELL6_SHIFT) +#define ADC_CHANY0_CHANYSELL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHANY0_CHANYSELL6_SHIFT)) & ADC_CHANY0_CHANYSELL6_MASK) + +#define ADC_CHANY0_CHANYSELL5_SHIFT (20) +#define ADC_CHANY0_CHANYSELL5_MASK (0xFU << ADC_CHANY0_CHANYSELL5_SHIFT) +#define ADC_CHANY0_CHANYSELL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHANY0_CHANYSELL5_SHIFT)) & ADC_CHANY0_CHANYSELL5_MASK) + +#define ADC_CHANY0_CHANYSELL4_SHIFT (16) +#define ADC_CHANY0_CHANYSELL4_MASK (0xFU << ADC_CHANY0_CHANYSELL4_SHIFT) +#define ADC_CHANY0_CHANYSELL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHANY0_CHANYSELL4_SHIFT)) & ADC_CHANY0_CHANYSELL4_MASK) + +#define ADC_CHANY0_CHANYSELL3_SHIFT (12) +#define ADC_CHANY0_CHANYSELL3_MASK (0xFU << ADC_CHANY0_CHANYSELL3_SHIFT) +#define ADC_CHANY0_CHANYSELL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHANY0_CHANYSELL3_SHIFT)) & ADC_CHANY0_CHANYSELL3_MASK) + +#define ADC_CHANY0_CHANYSELL2_SHIFT (8) +#define ADC_CHANY0_CHANYSELL2_MASK (0xFU << ADC_CHANY0_CHANYSELL2_SHIFT) +#define ADC_CHANY0_CHANYSELL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHANY0_CHANYSELL2_SHIFT)) & ADC_CHANY0_CHANYSELL2_MASK) + +#define ADC_CHANY0_CHANYSELL1_SHIFT (4) +#define ADC_CHANY0_CHANYSELL1_MASK (0xFU << ADC_CHANY0_CHANYSELL1_SHIFT) +#define ADC_CHANY0_CHANYSELL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHANY0_CHANYSELL1_SHIFT)) & ADC_CHANY0_CHANYSELL1_MASK) + +#define ADC_CHANY0_CHANYSELL0_SHIFT (0) +#define ADC_CHANY0_CHANYSELL0_MASK (0xFU << ADC_CHANY0_CHANYSELL0_SHIFT) +#define ADC_CHANY0_CHANYSELL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHANY0_CHANYSELL0_SHIFT)) & ADC_CHANY0_CHANYSELL0_MASK) + +/*! + * @brief ADC_CHANY1 Register Bit Definition + */ + +#define ADC_CHANY1_CHANYSELL15_SHIFT (28) +#define ADC_CHANY1_CHANYSELL15_MASK (0xFU << ADC_CHANY1_CHANYSEL15_SHIFT) +#define ADC_CHANY1_CHANYSELL15(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHANY1_CHANYSEL15_SHIFT)) & ADC_CHANY1_CHANYSEL15_MASK) + +#define ADC_CHANY1_CHANYSELL14_SHIFT (24) +#define ADC_CHANY1_CHANYSELL14_MASK (0xFU << ADC_CHANY1_CHANYSELL14_SHIFT) +#define ADC_CHANY1_CHANYSELL14(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHANY1_CHANYSELL14_SHIFT)) & ADC_CHANY1_CHANYSELL14_MASK) + +#define ADC_CHANY1_CHANYSELL13_SHIFT (20) +#define ADC_CHANY1_CHANYSELL13_MASK (0xFU << ADC_CHANY1_CHANYSELL13_SHIFT) +#define ADC_CHANY1_CHANYSELL13(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHANY1_CHANYSELL13_SHIFT)) & ADC_CHANY1_CHANYSELL13_MASK) + +#define ADC_CHANY1_CHANYSELL12_SHIFT (16) +#define ADC_CHANY1_CHANYSELL12_MASK (0xFU << ADC_CHANY1_CHANYSELL12_SHIFT) +#define ADC_CHANY1_CHANYSELL12(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHANY1_CHANYSELL12_SHIFT)) & ADC_CHANY1_CHANYSELL12_MASK) + +#define ADC_CHANY1_CHANYSELL11_SHIFT (12) +#define ADC_CHANY1_CHANYSELL11_MASK (0xFU << ADC_CHANY1_CHANYSELL11_SHIFT) +#define ADC_CHANY1_CHANYSELL11(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHANY1_CHANYSELL11_SHIFT)) & ADC_CHANY1_CHANYSELL11_MASK) + +#define ADC_CHANY1_CHANYSELL10_SHIFT (8) +#define ADC_CHANY1_CHANYSELL10_MASK (0xFU << ADC_CHANY1_CHANYSELL10_SHIFT) +#define ADC_CHANY1_CHANYSELL10(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHANY1_CHANYSELL10_SHIFT)) & ADC_CHANY1_CHANYSELL10_MASK) + +#define ADC_CHANY1_CHANYSELL9_SHIFT (4) +#define ADC_CHANY1_CHANYSELL9_MASK (0xFU << ADC_CHANY1_CHANYSELL9_SHIFT) +#define ADC_CHANY1_CHANYSELL9(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHANY1_CHANYSELL9_SHIFT)) & ADC_CHANY1_CHANYSELL9_MASK) + +#define ADC_CHANY1_CHANYSELL8_SHIFT (0) +#define ADC_CHANY1_CHANYSELL8_MASK (0xFU << ADC_CHANY1_CHANYSELL8_SHIFT) +#define ADC_CHANY1_CHANYSELL8(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHANY1_CHANYSELL8_SHIFT)) & ADC_CHANY1_CHANYSELL8_MASK) + +/*! + * @brief ADC_ANY_CFG Register Bit Definition + */ + +#define ADC_ANYCFG_CHANYSELH15_SHIFT (23) +#define ADC_ANYCFG_CHANYSELH15_MASK (0x01U << ADC_ANYCFG_CHANYSELH15_SHIFT) +#define ADC_ANYCFG_CHANYSELH15(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCFG_CHANYSELH15_SHIFT)) & ADC_ANYCFG_CHANYSELH15_MASK) + +#define ADC_ANYCFG_CHANYSELH14_SHIFT (22) +#define ADC_ANYCFG_CHANYSELH14_MASK (0x01U << ADC_ANYCFG_CHANYSELH14_SHIFT) +#define ADC_ANYCFG_CHANYSELH14(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCFG_CHANYSELH14_SHIFT)) & ADC_ANYCFG_CHANYSELH14_MASK) + +#define ADC_ANYCFG_CHANYSELH13_SHIFT (21) +#define ADC_ANYCFG_CHANYSELH13_MASK (0x01U << ADC_ANYCFG_CHANYSELH13_SHIFT) +#define ADC_ANYCFG_CHANYSELH13(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCFG_CHANYSELH13_SHIFT)) & ADC_ANYCFG_CHANYSELH13_MASK) + +#define ADC_ANYCFG_CHANYSELH12_SHIFT (20) +#define ADC_ANYCFG_CHANYSELH12_MASK (0x01U << ADC_ANYCFG_CHANYSELH12_SHIFT) +#define ADC_ANYCFG_CHANYSELH12(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCFG_CHANYSELH12_SHIFT)) & ADC_ANYCFG_CHANYSELH12_MASK) + +#define ADC_ANYCFG_CHANYSELH11_SHIFT (19) +#define ADC_ANYCFG_CHANYSELH11_MASK (0x01U << ADC_ANYCFG_CHANYSELH11_SHIFT) +#define ADC_ANYCFG_CHANYSELH11(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCFG_CHANYSELH11_SHIFT)) & ADC_ANYCFG_CHANYSELH11_MASK) + +#define ADC_ANYCFG_CHANYSELH10_SHIFT (18) +#define ADC_ANYCFG_CHANYSELH10_MASK (0x01U << ADC_ANYCFG_CHANYSELH10_SHIFT) +#define ADC_ANYCFG_CHANYSELH10(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCFG_CHANYSELH10_SHIFT)) & ADC_ANYCFG_CHANYSELH10_MASK) + +#define ADC_ANYCFG_CHANYSELH9_SHIFT (17) +#define ADC_ANYCFG_CHANYSELH9_MASK (0x01U << ADC_ANYCFG_CHANYSELH9_SHIFT) +#define ADC_ANYCFG_CHANYSELH9(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCFG_CHANYSELH9_SHIFT)) & ADC_ANYCFG_CHANYSELH9_MASK) + +#define ADC_ANYCFG_CHANYSELH8_SHIFT (16) +#define ADC_ANYCFG_CHANYSELH8_MASK (0x01U << ADC_ANYCFG_CHANYSELH8_SHIFT) +#define ADC_ANYCFG_CHANYSELH8(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCFG_CHANYSELH8_SHIFT)) & ADC_ANYCFG_CHANYSELH8_MASK) + +#define ADC_ANYCFG_CHANYSELH7_SHIFT (15) +#define ADC_ANYCFG_CHANYSELH7_MASK (0x01U << ADC_ANYCFG_CHANYSELH7_SHIFT) +#define ADC_ANYCFG_CHANYSELH7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCFG_CHANYSELH7_SHIFT)) & ADC_ANYCFG_CHANYSELH7_MASK) + +#define ADC_ANYCFG_CHANYSELH6_SHIFT (14) +#define ADC_ANYCFG_CHANYSELH6_MASK (0x01U << ADC_ANYCFG_CHANYSELH6_SHIFT) +#define ADC_ANYCFG_CHANYSELH6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCFG_CHANYSELH6_SHIFT)) & ADC_ANYCFG_CHANYSELH6_MASK) + +#define ADC_ANYCFG_CHANYSELH5_SHIFT (13) +#define ADC_ANYCFG_CHANYSELH5_MASK (0x01U << ADC_ANYCFG_CHANYSELH5_SHIFT) +#define ADC_ANYCFG_CHANYSELH5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCFG_CHANYSELH5_SHIFT)) & ADC_ANYCFG_CHANYSELH5_MASK) + +#define ADC_ANYCFG_CHANYSELH4_SHIFT (12) +#define ADC_ANYCFG_CHANYSELH4_MASK (0x01U << ADC_ANYCFG_CHANYSELH4_SHIFT) +#define ADC_ANYCFG_CHANYSELH4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCFG_CHANYSELH4_SHIFT)) & ADC_ANYCFG_CHANYSELH4_MASK) + +#define ADC_ANYCFG_CHANYSELH3_SHIFT (11) +#define ADC_ANYCFG_CHANYSELH3_MASK (0x01U << ADC_ANYCFG_CHANYSELH3_SHIFT) +#define ADC_ANYCFG_CHANYSELH3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCFG_CHANYSELH3_SHIFT)) & ADC_ANYCFG_CHANYSELH3_MASK) + +#define ADC_ANYCFG_CHANYSELH2_SHIFT (10) +#define ADC_ANYCFG_CHANYSELH2_MASK (0x01U << ADC_ANYCFG_CHANYSELH2_SHIFT) +#define ADC_ANYCFG_CHANYSELH2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCFG_CHANYSELH2_SHIFT)) & ADC_ANYCFG_CHANYSELH2_MASK) + +#define ADC_ANYCFG_CHANYSELH1_SHIFT (9) +#define ADC_ANYCFG_CHANYSELH1_MASK (0x01U << ADC_ANYCFG_CHANYSELH1_SHIFT) +#define ADC_ANYCFG_CHANYSELH1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCFG_CHANYSELH1_SHIFT)) & ADC_ANYCFG_CHANYSELH1_MASK) + +#define ADC_ANYCFG_CHANYSELH0_SHIFT (8) +#define ADC_ANYCFG_CHANYSELH0_MASK (0x01U << ADC_ANYCFG_CHANYSELH0_SHIFT) +#define ADC_ANYCFG_CHANYSELH0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCFG_CHANYSELH0_SHIFT)) & ADC_ANYCFG_CHANYSELH0_MASK) + +#define ADC_ANYCFG_CHANYNUM_SHIFT (0) +#define ADC_ANYCFG_CHANYNUM_MASK (0xFU << ADC_ANYCFG_CHANYNUM_SHIFT) +#define ADC_ANYCFG_CHANYNUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCFG_CHANYNUM_SHIFT)) & ADC_ANYCFG_CHANYNUM_MASK) + +/*! + * @brief ADC_ANY_CR Register Bit Definition + */ + +#define ADC_ANYCR_EOCALIE_SHIFT (21) +#define ADC_ANYCR_EOCALIE_MASK (0x01U << ADC_ANYCR_EOCALIE_SHIFT) +#define ADC_ANYCR_EOCALIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCR_EOCALIE_SHIFT)) & ADC_ANYCR_EOCALIE_MASK) + +#define ADC_ANYCR_ADCAL_SHIFT (20) +#define ADC_ANYCR_ADCAL_MASK (0x01U << ADC_ANYCR_ADCAL_SHIFT) +#define ADC_ANYCR_ADCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCR_ADCAL_SHIFT)) & ADC_ANYCR_ADCAL_MASK) + +#define ADC_ANYCR_JTRGEDGE_SHIFT (16) +#define ADC_ANYCR_JTRGEDGE_MASK (0x3U << ADC_ANYCR_JTRGEDGE_SHIFT) +#define ADC_ANYCR_JTRGEDGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCR_JTRGEDGE_SHIFT)) & ADC_ANYCR_JTRGEDGE_MASK) + +#define ADC_ANYCR_JTRGSHIFT_SHIFT (13) +#define ADC_ANYCR_JTRGSHIFT_MASK (0x7U << ADC_ANYCR_JTRGSHIFT_SHIFT) +#define ADC_ANYCR_JTRGSHIFT(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCR_JTRGSHIFT_SHIFT)) & ADC_ANYCR_JTRGSHIFT_MASK) + +#define ADC_ANYCR_JTRGEN_SHIFT (7) +#define ADC_ANYCR_JTRGEN_MASK (0x01U << ADC_ANYCR_JTRGEN_SHIFT) +#define ADC_ANYCR_JTRGEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCR_JTRGEN_SHIFT)) & ADC_ANYCR_JTRGEN_MASK) + +#define ADC_ANYCR_JADST_SHIFT (6) +#define ADC_ANYCR_JADST_MASK (0x01U << ADC_ANYCR_JADST_SHIFT) +#define ADC_ANYCR_JADST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCR_JADST_SHIFT)) & ADC_ANYCR_JADST_MASK) + +#define ADC_ANYCR_JAUTO_SHIFT (5) +#define ADC_ANYCR_JAUTO_MASK (0x01U << ADC_ANYCR_JAUTO_SHIFT) +#define ADC_ANYCR_JAUTO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCR_JAUTO_SHIFT)) & ADC_ANYCR_JAUTO_MASK) + +#define ADC_ANYCR_JEOSIE_SHIFT (4) +#define ADC_ANYCR_JEOSIE_MASK (0x01U << ADC_ANYCR_JEOSIE_SHIFT) +#define ADC_ANYCR_JEOSIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCR_JEOSIE_SHIFT)) & ADC_ANYCR_JEOSIE_MASK) + +#define ADC_ANYCR_JEOCIE_SHIFT (3) +#define ADC_ANYCR_JEOCIE_MASK (0x01U << ADC_ANYCR_JEOCIE_SHIFT) +#define ADC_ANYCR_JEOCIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCR_JEOCIE_SHIFT)) & ADC_ANYCR_JEOCIE_MASK) + +#define ADC_ANYCR_JEOSMPIE_SHIFT (2) +#define ADC_ANYCR_JEOSMPIE_MASK (0x01U << ADC_ANYCR_JEOSMPIE_SHIFT) +#define ADC_ANYCR_JEOSMPIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCR_JEOSMPIE_SHIFT)) & ADC_ANYCR_JEOSMPIE_MASK) + +#define ADC_ANYCR_JCEN_SHIFT (1) +#define ADC_ANYCR_JCEN_MASK (0x01U << ADC_ANYCR_JCEN_SHIFT) +#define ADC_ANYCR_JCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCR_JCEN_SHIFT)) & ADC_ANYCR_JCEN_MASK) + +#define ADC_ANYCR_CHANYMDEN_SHIFT (0) +#define ADC_ANYCR_CHANYMDEN_MASK (0x01U << ADC_ANYCR_CHANYMDEN_SHIFT) +#define ADC_ANYCR_CHANYMDEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ANYCR_CHANYMDEN_SHIFT)) & ADC_ANYCR_CHANYMDEN_MASK) + +/*! + * @brief ADC_ADCFG2 Register Bit Definition + */ + +#define ADC_ADCFG2_TROVSM_SHIFT (26) +#define ADC_ADCFG2_TROVSM_MASK (0x01U << ADC_ADCFG2_TROVSM_SHIFT) +#define ADC_ADCFG2_TROVSM(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCFG2_TROVSM_SHIFT)) & ADC_ADCFG2_TROVSM_MASK) + +#define ADC_ADCFG2_TROVS_SHIFT (25) +#define ADC_ADCFG2_TROVS_MASK (0x01U << ADC_ADCFG2_TROVS_SHIFT) +#define ADC_ADCFG2_TROVS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCFG2_TROVS_SHIFT)) & ADC_ADCFG2_TROVS_MASK) + +#define ADC_ADCFG2_OVSS_SHIFT (21) +#define ADC_ADCFG2_OVSS_MASK (0xFU << ADC_ADCFG2_OVSS_SHIFT) +#define ADC_ADCFG2_OVSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCFG2_OVSS_SHIFT)) & ADC_ADCFG2_OVSS_MASK) + +#define ADC_ADCFG2_OVSR_SHIFT (18) +#define ADC_ADCFG2_OVSR_MASK (0x7U << ADC_ADCFG2_OVSR_SHIFT) +#define ADC_ADCFG2_OVSR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCFG2_OVSR_SHIFT)) & ADC_ADCFG2_OVSR_MASK) + +#define ADC_ADCFG2_JOVSE_SHIFT (17) +#define ADC_ADCFG2_JOVSE_MASK (0x01U << ADC_ADCFG2_JOVSE_SHIFT) +#define ADC_ADCFG2_JOVSE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCFG2_JOVSE_SHIFT)) & ADC_ADCFG2_JOVSE_MASK) + +#define ADC_ADCFG2_ROVSE_SHIFT (16) +#define ADC_ADCFG2_ROVSE_MASK (0x01U << ADC_ADCFG2_ROVSE_SHIFT) +#define ADC_ADCFG2_ROVSE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCFG2_ROVSE_SHIFT)) & ADC_ADCFG2_ROVSE_MASK) + +#define ADC_ADCFG2_PSDC_SHIFT (10) +#define ADC_ADCFG2_PSDC_MASK (0x1FU << ADC_ADCFG2_PSDC_SHIFT) +#define ADC_ADCFG2_PSDC(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCFG2_PSDC_SHIFT)) & ADC_ADCFG2_PSDC_MASK) + +#define ADC_ADCFG2_DC_SHIFT (4) +#define ADC_ADCFG2_DC_MASK (0x1FU << ADC_ADCFG2_DC_SHIFT) +#define ADC_ADCFG2_DC(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCFG2_DC_SHIFT)) & ADC_ADCFG2_DC_MASK) + +#define ADC_ADCFG2_ADCSREF_SHIFT (2) +#define ADC_ADCFG2_ADCSREF_MASK (0x01U << ADC_ADCFG2_ADCSREF_SHIFT) +#define ADC_ADCFG2_ADCSREF(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCFG2_ADCSREF_SHIFT)) & ADC_ADCFG2_ADCSREF_MASK) + +#define ADC_ADCFG2_ADCCR_SHIFT (1) +#define ADC_ADCFG2_ADCCR_MASK (0x01U << ADC_ADCFG2_ADCCR_SHIFT) +#define ADC_ADCFG2_ADCCR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADCFG2_ADCCR_SHIFT)) & ADC_ADCFG2_ADCCR_MASK) + +/*! + * @brief ADC_SMPR1 Register Bit Definition + */ + +#define ADC_SMPR1_SAMP_SHIFT (0) +#define ADC_SMPR1_SAMP_MASK (0xFFFFFFFFU << ADC_SMPR1_SAMP_SHIFT) +#define ADC_SMPR1_SAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SMPR1_SAMP_SHIFT)) & ADC_SMPR1_SAMP_MASK) + +/*! + * @brief ADC_SMPR2 Register Bit Definition + */ + +#define ADC_SMPR2_SAMP_SHIFT (0) +#define ADC_SMPR2_SAMP_MASK (0xFFFFFFFFU << ADC_SMPR2_SAMP_SHIFT) +#define ADC_SMPR2_SAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SMPR2_SAMP_SHIFT)) & ADC_SMPR2_SAMP_MASK) + +/*! + * @brief ADC_SMPR3 Register Bit Definition + */ + +#define ADC_SMPR3_SAMP_SHIFT (0) +#define ADC_SMPR3_SAMP_MASK (0xFFFU << ADC_SMPR3_SAMP_SHIFT) +#define ADC_SMPR3_SAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SMPR3_SAMP_SHIFT)) & ADC_SMPR3_SAMP_MASK) + +/*! + * @brief ADC_JOFR Register Bit Definition + */ + +#define ADC_JOFR_JOFFSET_SHIFT (0) +#define ADC_JOFR_JOFFSET_MASK (0xFFFU << ADC_JOFR_JOFFSET_SHIFT) +#define ADC_JOFR_JOFFSET(x) (((uint32_t)(((uint32_t)(x)) << ADC_JOFR_JOFFSET_SHIFT)) & ADC_JOFR_JOFFSET_MASK) + +/*! + * @brief ADC_JSQR Register Bit Definition + */ + +#define ADC_JSQR_JNUM_SHIFT (20) +#define ADC_JSQR_JNUM_MASK (0x3U << ADC_JSQR_JNUM_SHIFT) +#define ADC_JSQR_JNUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_JSQR_JNUM_SHIFT)) & ADC_JSQR_JNUM_MASK) + +#define ADC_JSQR_JSQ3_SHIFT (15) +#define ADC_JSQR_JSQ3_MASK (0x1FU << ADC_JSQR_JSQ3_SHIFT) +#define ADC_JSQR_JSQ3(x) (((uint32_t)(((uint32_t)(x)) << ADC_JSQR_JSQ3_SHIFT)) & ADC_JSQR_JSQ3_MASK) + +#define ADC_JSQR_JSQ2_SHIFT (10) +#define ADC_JSQR_JSQ2_MASK (0x1FU << ADC_JSQR_JSQ2_SHIFT) +#define ADC_JSQR_JSQ2(x) (((uint32_t)(((uint32_t)(x)) << ADC_JSQR_JSQ2_SHIFT)) & ADC_JSQR_JSQ2_MASK) + +#define ADC_JSQR_JSQ1_SHIFT (5) +#define ADC_JSQR_JSQ1_MASK (0x1FU << ADC_JSQR_JSQ1_SHIFT) +#define ADC_JSQR_JSQ1(x) (((uint32_t)(((uint32_t)(x)) << ADC_JSQR_JSQ1_SHIFT)) & ADC_JSQR_JSQ1_MASK) + +#define ADC_JSQR_JSQ0_SHIFT (0) +#define ADC_JSQR_JSQ0_MASK (0x1FU << ADC_JSQR_JSQ0_SHIFT) +#define ADC_JSQR_JSQ0(x) (((uint32_t)(((uint32_t)(x)) << ADC_JSQR_JSQ0_SHIFT)) & ADC_JSQR_JSQ0_MASK) + +/*! + * @brief ADC_JADDATA Register Bit Definition + */ + +#define ADC_JADDATA_JVALID_SHIFT (22) +#define ADC_JADDATA_JVALID_MASK (0x01U << ADC_JADDATA_JVALID_SHIFT) +#define ADC_JADDATA_JVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_JADDATA_JVALID_SHIFT)) & ADC_JADDATA_JVALID_MASK) + +#define ADC_JADDATA_JOVERRUN_SHIFT (21) +#define ADC_JADDATA_JOVERRUN_MASK (0x01U << ADC_JADDATA_JOVERRUN_SHIFT) +#define ADC_JADDATA_JOVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_JADDATA_JOVERRUN_SHIFT)) & ADC_JADDATA_JOVERRUN_MASK) + +#define ADC_JADDATA_JCHANNELSEL_SHIFT (16) +#define ADC_JADDATA_JCHANNELSEL_MASK (0x1FU << ADC_JADDATA_JCHANNELSEL_SHIFT) +#define ADC_JADDATA_JCHANNELSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_JADDATA_JCHANNELSEL_SHIFT)) & ADC_JADDATA_JCHANNELSEL_MASK) + +#define ADC_JADDATA_JDATA_SHIFT (0) +#define ADC_JADDATA_JDATA_MASK (0xFFFFU << ADC_JADDATA_JDATA_SHIFT) +#define ADC_JADDATA_JDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_JADDATA_JDATA_SHIFT)) & ADC_JADDATA_JDATA_MASK) + +/*! + * @brief ADC_JDR Register Bit Definition + */ + +#define ADC_JDR_JVALID_SHIFT (22) +#define ADC_JDR_JVALID_MASK (0x01U << ADC_JDR_JVALID_SHIFT) +#define ADC_JDR_JVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_JDR_JVALID_SHIFT)) & ADC_JDR_JVALID_MASK) + +#define ADC_JDR_JOVERRUN_SHIFT (21) +#define ADC_JDR_JOVERRUN_MASK (0x01U << ADC_JDR_JOVERRUN_SHIFT) +#define ADC_JDR_JOVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_JDR_JOVERRUN_SHIFT)) & ADC_JDR_JOVERRUN_MASK) + +#define ADC_JDR_JDATA_SHIFT (0) +#define ADC_JDR_JDATA_MASK (0xFFFFU << ADC_JDR_JDATA_SHIFT) +#define ADC_JDR_JDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_JDR_JDATA_SHIFT)) & ADC_JDR_JDATA_MASK) + +/*! + * @} + */ /* end of group ADC_Register_Masks */ +/****************************************************************************** + *ADC Instance +*******************************************************************************/ + +#define ADC1 ((ADC_Type*)ADC1_BASE) +#define ADC2 ((ADC_Type*)ADC2_BASE) + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + +/*! + * @addtogroup BKP_Peripheral_Access_Layer BKP Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * BKP Type + ******************************************************************************/ +typedef struct { + __IO uint32_t Reserved2[16]; ///< Reserved + __IO uint32_t RTCCR; ///< RTC Clock Calibration Register offset: 0x40 + __IO uint32_t CR; ///< Backup Control Register offset: 0x44 + __IO uint32_t CSR; ///< Backup Control Status Register offset: 0x48 + __IO uint32_t Reserved3[1]; ///< Reserved + __IO uint32_t DR[20]; ///< Backup data register n offset: 0x50 +} BKP_Type; + +/******************************************************************************* + * BKP Type + ******************************************************************************/ + +/*! + * @addtogroup BKP_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief BKP_RTCCR Register Bit Definition + */ + +#define BKP_RTCCR_ASOS_SHIFT (9) +#define BKP_RTCCR_ASOS_MASK (0x01U << BKP_RTCCR_ASOS_SHIFT) +#define BKP_RTCCR_ASOS(x) (((uint32_t)(((uint32_t)(x)) << BKP_RTCCR_ASOS_SHIFT)) & BKP_RTCCR_ASOS_MASK) + +#define BKP_RTCCR_ASOE_SHIFT (8) +#define BKP_RTCCR_ASOE_MASK (0x01U << BKP_RTCCR_ASOE_SHIFT) +#define BKP_RTCCR_ASOE(x) (((uint32_t)(((uint32_t)(x)) << BKP_RTCCR_ASOE_SHIFT)) & BKP_RTCCR_ASOE_MASK) + +#define BKP_RTCCR_CCO_SHIFT (7) +#define BKP_RTCCR_CCO_MASK (0x01U << BKP_RTCCR_CCO_SHIFT) +#define BKP_RTCCR_CCO(x) (((uint32_t)(((uint32_t)(x)) << BKP_RTCCR_CCO_SHIFT)) & BKP_RTCCR_CCO_MASK) + +#define BKP_RTCCR_CAL_SHIFT (0) +#define BKP_RTCCR_CAL_MASK (0x7FU << BKP_RTCCR_CAL_SHIFT) +#define BKP_RTCCR_CAL(x) (((uint32_t)(((uint32_t)(x)) << BKP_RTCCR_CAL_SHIFT)) & BKP_RTCCR_CAL_MASK) + +/*! + * @brief BKP_CR Register Bit Definition + */ + +#define BKP_CR_TPAL_SHIFT (1) +#define BKP_CR_TPAL_MASK (0x01U << BKP_CR_TPAL_SHIFT) +#define BKP_CR_TPAL(x) (((uint32_t)(((uint32_t)(x)) << BKP_CR_TPAL_SHIFT)) & BKP_CR_TPAL_MASK) + +#define BKP_CR_TPE_SHIFT (0) +#define BKP_CR_TPE_MASK (0x01U << BKP_CR_TPE_SHIFT) +#define BKP_CR_TPE(x) (((uint32_t)(((uint32_t)(x)) << BKP_CR_TPE_SHIFT)) & BKP_CR_TPE_MASK) + +/*! + * @brief BKP_CSR Register Bit Definition + */ + +#define BKP_CSR_TIF_SHIFT (9) +#define BKP_CSR_TIF_MASK (0x01U << BKP_CSR_TIF_SHIFT) +#define BKP_CSR_TIF(x) (((uint32_t)(((uint32_t)(x)) << BKP_CSR_TIF_SHIFT)) & BKP_CSR_TIF_MASK) + +#define BKP_CSR_TEF_SHIFT (8) +#define BKP_CSR_TEF_MASK (0x01U << BKP_CSR_TEF_SHIFT) +#define BKP_CSR_TEF(x) (((uint32_t)(((uint32_t)(x)) << BKP_CSR_TEF_SHIFT)) & BKP_CSR_TEF_MASK) + +#define BKP_CSR_TPIE_SHIFT (2) +#define BKP_CSR_TPIE_MASK (0x01U << BKP_CSR_TPIE_SHIFT) +#define BKP_CSR_TPIE(x) (((uint32_t)(((uint32_t)(x)) << BKP_CSR_TPIE_SHIFT)) & BKP_CSR_TPIE_MASK) + +#define BKP_CSR_CTI_SHIFT (1) +#define BKP_CSR_CTI_MASK (0x01U << BKP_CSR_CTI_SHIFT) +#define BKP_CSR_CTI(x) (((uint32_t)(((uint32_t)(x)) << BKP_CSR_CTI_SHIFT)) & BKP_CSR_CTI_MASK) + +#define BKP_CSR_CTE_SHIFT (0) +#define BKP_CSR_CTE_MASK (0x01U << BKP_CSR_CTE_SHIFT) +#define BKP_CSR_CTE(x) (((uint32_t)(((uint32_t)(x)) << BKP_CSR_CTE_SHIFT)) & BKP_CSR_CTE_MASK) + +/*! + * @brief BKP_DR Register Bit Definition + */ + +#define BKP_DR_BKP_SHIFT (0) +#define BKP_DR_BKP_MASK (0xFFFFU << BKP_DR_BKP_SHIFT) +#define BKP_DR_BKP(x) (((uint32_t)(((uint32_t)(x)) << BKP_DR_BKP_SHIFT)) & BKP_DR_BKP_MASK) + +/*! + * @} + */ /* end of group BKP_Register_Masks */ +/****************************************************************************** + *BKP Instance +*******************************************************************************/ + +#define BKP ((BKP_Type*)RTC_BKP_BASE) + +/*! + * @} + */ /* end of group BKP_Peripheral_Access_Layer */ + +/*! + * @addtogroup COMP_Peripheral_Access_Layer COMP Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * COMP Type + ******************************************************************************/ +typedef struct { + __IO uint32_t Reserved4[3]; ///< Reserved + __IO uint32_t CSR[2]; ///< Comparator x (x=1,2) Control and Status Registeroffset: 0x0C + __IO uint32_t Reserved5[1]; ///< Reserved + __IO uint32_t CRV; ///< Comparator External Reference Voltage Registeroffset: 0x18 + __IO uint32_t POLL[3]; ///< Comparator x (x=1,2,3) polling register offset: 0x1C + __IO uint32_t Reserved6[1]; ///< Reserved + __IO uint32_t CSR3; ///< Comparator x (x=3) Control and Status Registeroffset: 0x0C +} COMP_Type; + +/******************************************************************************* + * COMP Type + ******************************************************************************/ + +/*! + * @addtogroup COMP_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief COMP_CSR Register Bit Definition + */ + +#define COMP_CSR_LOCK_SHIFT (31) +#define COMP_CSR_LOCK_MASK (0x01U << COMP_CSR_LOCK_SHIFT) +#define COMP_CSR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << COMP_CSR_LOCK_SHIFT)) & COMP_CSR_LOCK_MASK) + +#define COMP_CSR_OUT_SHIFT (30) +#define COMP_CSR_OUT_MASK (0x01U << COMP_CSR_OUT_SHIFT) +#define COMP_CSR_OUT(x) (((uint32_t)(((uint32_t)(x)) << COMP_CSR_OUT_SHIFT)) & COMP_CSR_OUT_MASK) + +#define COMP_CSR_OUTANASEL_SHIFT (29) +#define COMP_CSR_OUTANASEL_MASK (0x01U << COMP_CSR_OUTANASEL_SHIFT) +#define COMP_CSR_OUTANASEL(x) (((uint32_t)(((uint32_t)(x)) << COMP_CSR_OUTANASEL_SHIFT)) & COMP_CSR_OUTANASEL_MASK) + +#define COMP_CSR_WE_SHIFT (28) +#define COMP_CSR_WE_MASK (0x01U << COMP_CSR_WE_SHIFT) +#define COMP_CSR_WE(x) (((uint32_t)(((uint32_t)(x)) << COMP_CSR_WE_SHIFT)) & COMP_CSR_WE_MASK) + +#define COMP_CSR_OFLT_SHIFT (18) +#define COMP_CSR_OFLT_MASK (0x7U << COMP_CSR_OFLT_SHIFT) +#define COMP_CSR_OFLT(x) (((uint32_t)(((uint32_t)(x)) << COMP_CSR_OFLT_SHIFT)) & COMP_CSR_OFLT_MASK) + +#define COMP_CSR_HYST_SHIFT (16) +#define COMP_CSR_HYST_MASK (0x3U << COMP_CSR_HYST_SHIFT) +#define COMP_CSR_HYST(x) (((uint32_t)(((uint32_t)(x)) << COMP_CSR_HYST_SHIFT)) & COMP_CSR_HYST_MASK) + +#define COMP_CSR_POL_SHIFT (15) +#define COMP_CSR_POL_MASK (0x01U << COMP_CSR_POL_SHIFT) +#define COMP_CSR_POL(x) (((uint32_t)(((uint32_t)(x)) << COMP_CSR_POL_SHIFT)) & COMP_CSR_POL_MASK) + +#define COMP_CSR_OUTSEL_SHIFT (10) +#define COMP_CSR_OUTSEL_MASK (0xFU << COMP_CSR_OUTSEL_SHIFT) +#define COMP_CSR_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << COMP_CSR_OUTSEL_SHIFT)) & COMP_CSR_OUTSEL_MASK) + +#define COMP_CSR_INPSEL_SHIFT (7) +#define COMP_CSR_INPSEL_MASK (0x3U << COMP_CSR_INPSEL_SHIFT) +#define COMP_CSR_INPSEL(x) (((uint32_t)(((uint32_t)(x)) << COMP_CSR_INPSEL_SHIFT)) & COMP_CSR_INPSEL_MASK) + +#define COMP_CSR_INMSEL_SHIFT (4) +#define COMP_CSR_INMSEL_MASK (0x3U << COMP_CSR_INMSEL_SHIFT) +#define COMP_CSR_INMSEL(x) (((uint32_t)(((uint32_t)(x)) << COMP_CSR_INMSEL_SHIFT)) & COMP_CSR_INMSEL_MASK) + +#define COMP_CSR_MODE_SHIFT (2) +#define COMP_CSR_MODE_MASK (0x3U << COMP_CSR_MODE_SHIFT) +#define COMP_CSR_MODE(x) (((uint32_t)(((uint32_t)(x)) << COMP_CSR_MODE_SHIFT)) & COMP_CSR_MODE_MASK) + +#define COMP_CSR_EN_SHIFT (0) +#define COMP_CSR_EN_MASK (0x01U << COMP_CSR_EN_SHIFT) +#define COMP_CSR_EN(x) (((uint32_t)(((uint32_t)(x)) << COMP_CSR_EN_SHIFT)) & COMP_CSR_EN_MASK) + +/*! + * @brief COMP_CRV Register Bit Definition + */ + +#define COMP_CRV_CRVSRC_SHIFT (5) +#define COMP_CRV_CRVSRC_MASK (0x01U << COMP_CRV_CRVSRC_SHIFT) +#define COMP_CRV_CRVSRC(x) (((uint32_t)(((uint32_t)(x)) << COMP_CRV_CRVSRC_SHIFT)) & COMP_CRV_CRVSRC_MASK) + +#define COMP_CRV_CRVEN_SHIFT (4) +#define COMP_CRV_CRVEN_MASK (0x01U << COMP_CRV_CRVEN_SHIFT) +#define COMP_CRV_CRVEN(x) (((uint32_t)(((uint32_t)(x)) << COMP_CRV_CRVEN_SHIFT)) & COMP_CRV_CRVEN_MASK) + +#define COMP_CRV_CRVSEL_SHIFT (0) +#define COMP_CRV_CRVSEL_MASK (0xFU << COMP_CRV_CRVSEL_SHIFT) +#define COMP_CRV_CRVSEL(x) (((uint32_t)(((uint32_t)(x)) << COMP_CRV_CRVSEL_SHIFT)) & COMP_CRV_CRVSEL_MASK) + +/*! + * @brief COMP_POLL Register Bit Definition + */ + +#define COMP_POLL_POUT_SHIFT (8) +#define COMP_POLL_POUT_MASK (0x7U << COMP_POLL_POUT_SHIFT) +#define COMP_POLL_POUT(x) (((uint32_t)(((uint32_t)(x)) << COMP_POLL_POUT_SHIFT)) & COMP_POLL_POUT_MASK) + +#define COMP_POLL_PERIOD_SHIFT (4) +#define COMP_POLL_PERIOD_MASK (0x7U << COMP_POLL_PERIOD_SHIFT) +#define COMP_POLL_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << COMP_POLL_PERIOD_SHIFT)) & COMP_POLL_PERIOD_MASK) + +#define COMP_POLL_FIXN_SHIFT (2) +#define COMP_POLL_FIXN_MASK (0x01U << COMP_POLL_FIXN_SHIFT) +#define COMP_POLL_FIXN(x) (((uint32_t)(((uint32_t)(x)) << COMP_POLL_FIXN_SHIFT)) & COMP_POLL_FIXN_MASK) + +#define COMP_POLL_POLLCH_SHIFT (1) +#define COMP_POLL_POLLCH_MASK (0x01U << COMP_POLL_POLLCH_SHIFT) +#define COMP_POLL_POLLCH(x) (((uint32_t)(((uint32_t)(x)) << COMP_POLL_POLLCH_SHIFT)) & COMP_POLL_POLLCH_MASK) + +#define COMP_POLL_POLLEN_SHIFT (0) +#define COMP_POLL_POLLEN_MASK (0x01U << COMP_POLL_POLLEN_SHIFT) +#define COMP_POLL_POLLEN(x) (((uint32_t)(((uint32_t)(x)) << COMP_POLL_POLLEN_SHIFT)) & COMP_POLL_POLLEN_MASK) + +/*! + * @} + */ /* end of group COMP_Register_Masks */ +/****************************************************************************** + *COMP Instance +*******************************************************************************/ + +#define COMP ((COMP_Type*)COMP_BASE) + +/*! + * @} + */ /* end of group COMP_Peripheral_Access_Layer */ + +/*! + * @addtogroup CORDIC_Peripheral_Access_Layer CORDIC Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * CORDIC Type + ******************************************************************************/ +typedef struct { + __IO uint32_t DXR; ///< CORDIC X Data Register offset: 0x00 + __IO uint32_t DYR; ///< CORDIC Y data register offset: 0x04 + __IO uint32_t DZR; ///< CORDIC Z data register offset: 0x08 + __IO uint32_t RXR; ///< CORDIC X Result Register offset: 0x0C + __IO uint32_t RYR; ///< CORDIC Y result register offset: 0x10 + __IO uint32_t RZR; ///< CORDIC Z result register offset: 0x14 + __IO uint32_t CR; ///< CORDIC Control Register offset: 0x18 + __IO uint32_t SR; ///< CORDIC Status Register offset: 0x1C +} CORDIC_Type; + +/******************************************************************************* + * CORDIC Type + ******************************************************************************/ + +/*! + * @addtogroup CORDIC_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief CORDIC_DXR Register Bit Definition + */ + +#define CORDIC_DXR_DX_SHIFT (0) +#define CORDIC_DXR_DX_MASK (0xFFFFFFU << CORDIC_DXR_DX_SHIFT) +#define CORDIC_DXR_DX(x) (((uint32_t)(((uint32_t)(x)) << CORDIC_DXR_DX_SHIFT)) & CORDIC_DXR_DX_MASK) + +/*! + * @brief CORDIC_DYR Register Bit Definition + */ + +#define CORDIC_DYR_DY_SHIFT (0) +#define CORDIC_DYR_DY_MASK (0xFFFFFFU << CORDIC_DYR_DY_SHIFT) +#define CORDIC_DYR_DY(x) (((uint32_t)(((uint32_t)(x)) << CORDIC_DYR_DY_SHIFT)) & CORDIC_DYR_DY_MASK) + +/*! + * @brief CORDIC_DZR Register Bit Definition + */ + +#define CORDIC_DZR_DZ_SHIFT (0) +#define CORDIC_DZR_DZ_MASK (0xFFFFFFU << CORDIC_DZR_DZ_SHIFT) +#define CORDIC_DZR_DZ(x) (((uint32_t)(((uint32_t)(x)) << CORDIC_DZR_DZ_SHIFT)) & CORDIC_DZR_DZ_MASK) + +/*! + * @brief CORDIC_RXR Register Bit Definition + */ + +#define CORDIC_RXR_RX_SHIFT (0) +#define CORDIC_RXR_RX_MASK (0x1FFFFFFU << CORDIC_RXR_RX_SHIFT) +#define CORDIC_RXR_RX(x) (((uint32_t)(((uint32_t)(x)) << CORDIC_RXR_RX_SHIFT)) & CORDIC_RXR_RX_MASK) + +/*! + * @brief CORDIC_RYR Register Bit Definition + */ + +#define CORDIC_RYR_RY_SHIFT (0) +#define CORDIC_RYR_RY_MASK (0x1FFFFFFU << CORDIC_RYR_RY_SHIFT) +#define CORDIC_RYR_RY(x) (((uint32_t)(((uint32_t)(x)) << CORDIC_RYR_RY_SHIFT)) & CORDIC_RYR_RY_MASK) + +/*! + * @brief CORDIC_RZR Register Bit Definition + */ + +#define CORDIC_RZR_RZ_SHIFT (0) +#define CORDIC_RZR_RZ_MASK (0xFFFFFFU << CORDIC_RZR_RZ_SHIFT) +#define CORDIC_RZR_RZ(x) (((uint32_t)(((uint32_t)(x)) << CORDIC_RZR_RZ_SHIFT)) & CORDIC_RZR_RZ_MASK) + +/*! + * @brief CORDIC_CR Register Bit Definition + */ + +#define CORDIC_CR_ENABLE_SHIFT (3) +#define CORDIC_CR_ENABLE_MASK (0x01U << CORDIC_CR_ENABLE_SHIFT) +#define CORDIC_CR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CORDIC_CR_ENABLE_SHIFT)) & CORDIC_CR_ENABLE_MASK) + +#define CORDIC_CR_STARTMODE_SHIFT (2) +#define CORDIC_CR_STARTMODE_MASK (0x01U << CORDIC_CR_STARTMODE_SHIFT) +#define CORDIC_CR_STARTMODE(x) (((uint32_t)(((uint32_t)(x)) << CORDIC_CR_STARTMODE_SHIFT)) & CORDIC_CR_STARTMODE_MASK) + +#define CORDIC_CR_WORKMODE_SHIFT (1) +#define CORDIC_CR_WORKMODE_MASK (0x01U << CORDIC_CR_WORKMODE_SHIFT) +#define CORDIC_CR_WORKMODE(x) (((uint32_t)(((uint32_t)(x)) << CORDIC_CR_WORKMODE_SHIFT)) & CORDIC_CR_WORKMODE_MASK) + +#define CORDIC_CR_START_SHIFT (0) +#define CORDIC_CR_START_MASK (0x01U << CORDIC_CR_START_SHIFT) +#define CORDIC_CR_START(x) (((uint32_t)(((uint32_t)(x)) << CORDIC_CR_START_SHIFT)) & CORDIC_CR_START_MASK) + +/*! + * @brief CORDIC_SR Register Bit Definition + */ + +#define CORDIC_SR_BSY_SHIFT (0) +#define CORDIC_SR_BSY_MASK (0x01U << CORDIC_SR_BSY_SHIFT) +#define CORDIC_SR_BSY(x) (((uint32_t)(((uint32_t)(x)) << CORDIC_SR_BSY_SHIFT)) & CORDIC_SR_BSY_MASK) + +/*! + * @} + */ /* end of group CORDIC_Register_Masks */ +/****************************************************************************** + *CORDIC Instance +*******************************************************************************/ + +#define CORDIC ((CORDIC_Type*)CORDIC_BASE) + +/*! + * @} + */ /* end of group CORDIC_Peripheral_Access_Layer */ + + + + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * CRC Type + ******************************************************************************/ +typedef struct { + __IO uint32_t DR; ///< CRC data register offset: 0x00 + __IO uint32_t IDR; ///< CRC independent data register offset: 0x04 + __IO uint32_t CR; ///< CRC Control Register offset: 0x08 + __IO uint32_t IVR; ///< CRC initial value register offset: 0x0C + __IO uint32_t PR; ///< CRC polynomial register offset: 0x10 +} CRC_Type; + +/******************************************************************************* + * CRC Type + ******************************************************************************/ + +/*! + * @addtogroup CRC_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief CRC_DR Register Bit Definition + */ + +#define CRC_DR_DR_SHIFT (0) +#define CRC_DR_DR_MASK (0xFFFFFFFFU << CRC_DR_DR_SHIFT) +#define CRC_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << CRC_DR_DR_SHIFT)) & CRC_DR_DR_MASK) + +/*! + * @brief CRC_IDR Register Bit Definition + */ + +#define CRC_IDR_IDR_SHIFT (0) +#define CRC_IDR_IDR_MASK (0xFFFFFFFFU << CRC_IDR_IDR_SHIFT) +#define CRC_IDR_IDR(x) (((uint32_t)(((uint32_t)(x)) << CRC_IDR_IDR_SHIFT)) & CRC_IDR_IDR_MASK) + +/*! + * @brief CRC_CR Register Bit Definition + */ + +#define CRC_CR_PWIDTH_SHIFT (14) +#define CRC_CR_PWIDTH_MASK (0x3U << CRC_CR_PWIDTH_SHIFT) +#define CRC_CR_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << CRC_CR_PWIDTH_SHIFT)) & CRC_CR_PWIDTH_MASK) + +#define CRC_CR_RO_SHIFT (6) +#define CRC_CR_RO_MASK (0x01U << CRC_CR_RO_SHIFT) +#define CRC_CR_RO(x) (((uint32_t)(((uint32_t)(x)) << CRC_CR_RO_SHIFT)) & CRC_CR_RO_MASK) + +#define CRC_CR_BEO_SHIFT (5) +#define CRC_CR_BEO_MASK (0x01U << CRC_CR_BEO_SHIFT) +#define CRC_CR_BEO(x) (((uint32_t)(((uint32_t)(x)) << CRC_CR_BEO_SHIFT)) & CRC_CR_BEO_MASK) + +#define CRC_CR_BEI_SHIFT (4) +#define CRC_CR_BEI_MASK (0x01U << CRC_CR_BEI_SHIFT) +#define CRC_CR_BEI(x) (((uint32_t)(((uint32_t)(x)) << CRC_CR_BEI_SHIFT)) & CRC_CR_BEI_MASK) + +#define CRC_CR_RI_SHIFT (1) +#define CRC_CR_RI_MASK (0x01U << CRC_CR_RI_SHIFT) +#define CRC_CR_RI(x) (((uint32_t)(((uint32_t)(x)) << CRC_CR_RI_SHIFT)) & CRC_CR_RI_MASK) + +#define CRC_CR_RST_SHIFT (0) +#define CRC_CR_RST_MASK (0x01U << CRC_CR_RST_SHIFT) +#define CRC_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << CRC_CR_RST_SHIFT)) & CRC_CR_RST_MASK) + +/*! + * @brief CRC_IVR Register Bit Definition + */ + +#define CRC_IVR_IVR_SHIFT (0) +#define CRC_IVR_IVR_MASK (0xFFFFFFFFU << CRC_IVR_IVR_SHIFT) +#define CRC_IVR_IVR(x) (((uint32_t)(((uint32_t)(x)) << CRC_IVR_IVR_SHIFT)) & CRC_IVR_IVR_MASK) + +/*! + * @brief CRC_PR Register Bit Definition + */ + +#define CRC_PR_PR_SHIFT (0) +#define CRC_PR_PR_MASK (0xFFFFFFFFU << CRC_PR_PR_SHIFT) +#define CRC_PR_PR(x) (((uint32_t)(((uint32_t)(x)) << CRC_PR_PR_SHIFT)) & CRC_PR_PR_MASK) + +/*! + * @} + */ /* end of group CRC_Register_Masks */ +/****************************************************************************** + *CRC Instance +*******************************************************************************/ + +#define CRC ((CRC_Type*)CRC_BASE) + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + + + +/*! + * @addtogroup CRS_Peripheral_Access_Layer CRS Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * CRS Type + ******************************************************************************/ +typedef struct { + __IO uint32_t CR; ///< CRS Control Register offset: 0x00 + __IO uint32_t CFGR; ///< CRS Configuration Register offset: 0x04 + __IO uint32_t LSR; ///< CRS Interrupt Status Register offset: 0x08 + __IO uint32_t LCR; ///< CRS Interrupt Flag Clear Register offset: 0x0C +} CRS_Type; + +/******************************************************************************* + * CRS Type + ******************************************************************************/ + +/*! + * @addtogroup CRS_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief CRS_CR Register Bit Definition + */ + +#define CRS_CR_TRIM_SHIFT (8) +#define CRS_CR_TRIM_MASK (0x3FFU << CRS_CR_TRIM_SHIFT) +#define CRS_CR_TRIM(x) (((uint32_t)(((uint32_t)(x)) << CRS_CR_TRIM_SHIFT)) & CRS_CR_TRIM_MASK) + +#define CRS_CR_SWSYNC_SHIFT (7) +#define CRS_CR_SWSYNC_MASK (0x01U << CRS_CR_SWSYNC_SHIFT) +#define CRS_CR_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << CRS_CR_SWSYNC_SHIFT)) & CRS_CR_SWSYNC_MASK) + +#define CRS_CR_AUTOTRIMEN_SHIFT (6) +#define CRS_CR_AUTOTRIMEN_MASK (0x01U << CRS_CR_AUTOTRIMEN_SHIFT) +#define CRS_CR_AUTOTRIMEN(x) (((uint32_t)(((uint32_t)(x)) << CRS_CR_AUTOTRIMEN_SHIFT)) & CRS_CR_AUTOTRIMEN_MASK) + +#define CRS_CR_CEN_SHIFT (5) +#define CRS_CR_CEN_MASK (0x01U << CRS_CR_CEN_SHIFT) +#define CRS_CR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CRS_CR_CEN_SHIFT)) & CRS_CR_CEN_MASK) + +#define CRS_CR_ESYNCIE_SHIFT (3) +#define CRS_CR_ESYNCIE_MASK (0x01U << CRS_CR_ESYNCIE_SHIFT) +#define CRS_CR_ESYNCIE(x) (((uint32_t)(((uint32_t)(x)) << CRS_CR_ESYNCIE_SHIFT)) & CRS_CR_ESYNCIE_MASK) + +#define CRS_CR_ERRIE_SHIFT (2) +#define CRS_CR_ERRIE_MASK (0x01U << CRS_CR_ERRIE_SHIFT) +#define CRS_CR_ERRIE(x) (((uint32_t)(((uint32_t)(x)) << CRS_CR_ERRIE_SHIFT)) & CRS_CR_ERRIE_MASK) + +#define CRS_CR_SYNCWARNIE_SHIFT (1) +#define CRS_CR_SYNCWARNIE_MASK (0x01U << CRS_CR_SYNCWARNIE_SHIFT) +#define CRS_CR_SYNCWARNIE(x) (((uint32_t)(((uint32_t)(x)) << CRS_CR_SYNCWARNIE_SHIFT)) & CRS_CR_SYNCWARNIE_MASK) + +#define CRS_CR_SYNCOKIE_SHIFT (0) +#define CRS_CR_SYNCOKIE_MASK (0x01U << CRS_CR_SYNCOKIE_SHIFT) +#define CRS_CR_SYNCOKIE(x) (((uint32_t)(((uint32_t)(x)) << CRS_CR_SYNCOKIE_SHIFT)) & CRS_CR_SYNCOKIE_MASK) + +/*! + * @brief CRS_CFGR Register Bit Definition + */ + +#define CRS_CFGR_SYNCPOL_SHIFT (31) +#define CRS_CFGR_SYNCPOL_MASK (0x01U << CRS_CFGR_SYNCPOL_SHIFT) +#define CRS_CFGR_SYNCPOL(x) (((uint32_t)(((uint32_t)(x)) << CRS_CFGR_SYNCPOL_SHIFT)) & CRS_CFGR_SYNCPOL_MASK) + +#define CRS_CFGR_SYNCSRC_SHIFT (28) +#define CRS_CFGR_SYNCSRC_MASK (0x3U << CRS_CFGR_SYNCSRC_SHIFT) +#define CRS_CFGR_SYNCSRC(x) (((uint32_t)(((uint32_t)(x)) << CRS_CFGR_SYNCSRC_SHIFT)) & CRS_CFGR_SYNCSRC_MASK) + +#define CRS_CFGR_SYNCDIV_SHIFT (24) +#define CRS_CFGR_SYNCDIV_MASK (0x7U << CRS_CFGR_SYNCDIV_SHIFT) +#define CRS_CFGR_SYNCDIV(x) (((uint32_t)(((uint32_t)(x)) << CRS_CFGR_SYNCDIV_SHIFT)) & CRS_CFGR_SYNCDIV_MASK) + +#define CRS_CFGR_FELIM_SHIFT (16) +#define CRS_CFGR_FELIM_MASK (0xFFU << CRS_CFGR_FELIM_SHIFT) +#define CRS_CFGR_FELIM(x) (((uint32_t)(((uint32_t)(x)) << CRS_CFGR_FELIM_SHIFT)) & CRS_CFGR_FELIM_MASK) + +#define CRS_CFGR_RELOAD_SHIFT (0) +#define CRS_CFGR_RELOAD_MASK (0xFFFFU << CRS_CFGR_RELOAD_SHIFT) +#define CRS_CFGR_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << CRS_CFGR_RELOAD_SHIFT)) & CRS_CFGR_RELOAD_MASK) + +/*! + * @brief CRS_LSR Register Bit Definition + */ + +#define CRS_LSR_FECAP_SHIFT (16) +#define CRS_LSR_FECAP_MASK (0xFFFFU << CRS_LSR_FECAP_SHIFT) +#define CRS_LSR_FECAP(x) (((uint32_t)(((uint32_t)(x)) << CRS_LSR_FECAP_SHIFT)) & CRS_LSR_FECAP_MASK) + +#define CRS_LSR_FEDIR_SHIFT (15) +#define CRS_LSR_FEDIR_MASK (0x01U << CRS_LSR_FEDIR_SHIFT) +#define CRS_LSR_FEDIR(x) (((uint32_t)(((uint32_t)(x)) << CRS_LSR_FEDIR_SHIFT)) & CRS_LSR_FEDIR_MASK) + +#define CRS_LSR_TRIMOVF_SHIFT (10) +#define CRS_LSR_TRIMOVF_MASK (0x01U << CRS_LSR_TRIMOVF_SHIFT) +#define CRS_LSR_TRIMOVF(x) (((uint32_t)(((uint32_t)(x)) << CRS_LSR_TRIMOVF_SHIFT)) & CRS_LSR_TRIMOVF_MASK) + +#define CRS_LSR_SYNCMISS_SHIFT (9) +#define CRS_LSR_SYNCMISS_MASK (0x01U << CRS_LSR_SYNCMISS_SHIFT) +#define CRS_LSR_SYNCMISS(x) (((uint32_t)(((uint32_t)(x)) << CRS_LSR_SYNCMISS_SHIFT)) & CRS_LSR_SYNCMISS_MASK) + +#define CRS_LSR_SYNCERR_SHIFT (8) +#define CRS_LSR_SYNCERR_MASK (0x01U << CRS_LSR_SYNCERR_SHIFT) +#define CRS_LSR_SYNCERR(x) (((uint32_t)(((uint32_t)(x)) << CRS_LSR_SYNCERR_SHIFT)) & CRS_LSR_SYNCERR_MASK) + +#define CRS_LSR_ESYNCF_SHIFT (3) +#define CRS_LSR_ESYNCF_MASK (0x01U << CRS_LSR_ESYNCF_SHIFT) +#define CRS_LSR_ESYNCF(x) (((uint32_t)(((uint32_t)(x)) << CRS_LSR_ESYNCF_SHIFT)) & CRS_LSR_ESYNCF_MASK) + +#define CRS_LSR_ERRF_SHIFT (2) +#define CRS_LSR_ERRF_MASK (0x01U << CRS_LSR_ERRF_SHIFT) +#define CRS_LSR_ERRF(x) (((uint32_t)(((uint32_t)(x)) << CRS_LSR_ERRF_SHIFT)) & CRS_LSR_ERRF_MASK) + +#define CRS_LSR_SYNCWARNF_SHIFT (1) +#define CRS_LSR_SYNCWARNF_MASK (0x01U << CRS_LSR_SYNCWARNF_SHIFT) +#define CRS_LSR_SYNCWARNF(x) (((uint32_t)(((uint32_t)(x)) << CRS_LSR_SYNCWARNF_SHIFT)) & CRS_LSR_SYNCWARNF_MASK) + +#define CRS_LSR_SYNCOKF_SHIFT (0) +#define CRS_LSR_SYNCOKF_MASK (0x01U << CRS_LSR_SYNCOKF_SHIFT) +#define CRS_LSR_SYNCOKF(x) (((uint32_t)(((uint32_t)(x)) << CRS_LSR_SYNCOKF_SHIFT)) & CRS_LSR_SYNCOKF_MASK) + +/*! + * @brief CRS_LCR Register Bit Definition + */ + +#define CRS_LCR_ESYNCC_SHIFT (3) +#define CRS_LCR_ESYNCC_MASK (0x01U << CRS_LCR_ESYNCC_SHIFT) +#define CRS_LCR_ESYNCC(x) (((uint32_t)(((uint32_t)(x)) << CRS_LCR_ESYNCC_SHIFT)) & CRS_LCR_ESYNCC_MASK) + +#define CRS_LCR_ERRC_SHIFT (2) +#define CRS_LCR_ERRC_MASK (0x01U << CRS_LCR_ERRC_SHIFT) +#define CRS_LCR_ERRC(x) (((uint32_t)(((uint32_t)(x)) << CRS_LCR_ERRC_SHIFT)) & CRS_LCR_ERRC_MASK) + +#define CRS_LCR_SYNCWARNC_SHIFT (1) +#define CRS_LCR_SYNCWARNC_MASK (0x01U << CRS_LCR_SYNCWARNC_SHIFT) +#define CRS_LCR_SYNCWARNC(x) (((uint32_t)(((uint32_t)(x)) << CRS_LCR_SYNCWARNC_SHIFT)) & CRS_LCR_SYNCWARNC_MASK) + +#define CRS_LCR_SYNCOKC_SHIFT (0) +#define CRS_LCR_SYNCOKC_MASK (0x01U << CRS_LCR_SYNCOKC_SHIFT) +#define CRS_LCR_SYNCOKC(x) (((uint32_t)(((uint32_t)(x)) << CRS_LCR_SYNCOKC_SHIFT)) & CRS_LCR_SYNCOKC_MASK) + +/*! + * @} + */ /* end of group CRS_Register_Masks */ +/****************************************************************************** + *CRS Instance +*******************************************************************************/ + +#define CRS ((CRS_Type*)CRS_BASE) + +/*! + * @} + */ /* end of group CRS_Peripheral_Access_Layer */ + + + + +/*! + * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * DAC Type + ******************************************************************************/ +typedef struct { + __IO uint32_t CR; ///< DAC Control Register offset: 0x00 + __IO uint32_t SWTRIGR; ///< DAC Software Trigger Register offset: 0x04 + __IO uint32_t DHR12R1; ///< 12-Bit Right-Justified Data Holding Register for DAC Channel 1offset: 0x08 + __IO uint32_t DHR12L1; ///< 12-Bit Left-Justified Data Holding Register for DAC Channel 1offset: 0x0C + __IO uint32_t DHR8R1; ///< 8-Bit Right-Justified Data Holding Register for DAC Channel 1offset: 0x10 + __IO uint32_t DHR12R2; ///< 12-Bit Right-Justified Data Holding Register for DAC Channel 2offset: 0x14 + __IO uint32_t DHR12L2; ///< 12-Bit Left-Justified Data Holding Register for DAC Channel 2offset: 0x18 + __IO uint32_t DHR8R2; ///< 8-Bit Right-Justified Data Holding Register for DAC Channel 2offset: 0x1C + __IO uint32_t DHR12RD; ///< 12-Bit Right-Justified Data Holding Registers for Dual DACsoffset: 0x20 + __IO uint32_t DHR12LD; ///< 12-Bit Left-Justified Data Holding Registers for Dual DACsoffset: 0x24 + __IO uint32_t DHR8RD; ///< 8-Bit Right-Justified Data Holding Registers for Dual DACsoffset: 0x28 + __IO uint32_t DOR1; ///< DAC Channel 1 Data Output Register offset: 0x2C + __IO uint32_t DOR2; ///< DAC Channel 2 Data Output Register offset: 0x30 +} DAC_Type; + +/******************************************************************************* + * DAC Type + ******************************************************************************/ + +/*! + * @addtogroup DAC_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief DAC_CR Register Bit Definition + */ + +#define DAC_CR_OE2EN_SHIFT (29) +#define DAC_CR_OE2EN_MASK (0x01U << DAC_CR_OE2EN_SHIFT) +#define DAC_CR_OE2EN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_OE2EN_SHIFT)) & DAC_CR_OE2EN_MASK) + +#define DAC_CR_DMAEN2_SHIFT (28) +#define DAC_CR_DMAEN2_MASK (0x01U << DAC_CR_DMAEN2_SHIFT) +#define DAC_CR_DMAEN2(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN2_SHIFT)) & DAC_CR_DMAEN2_MASK) + +#define DAC_CR_MAMP2_SHIFT (24) +#define DAC_CR_MAMP2_MASK (0xFU << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_MAMP2_SHIFT)) & DAC_CR_MAMP2_MASK) + +#define DAC_CR_WAVE2_SHIFT (22) +#define DAC_CR_WAVE2_MASK (0x3U << DAC_CR_WAVE2_SHIFT) +#define DAC_CR_WAVE2(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WAVE2_SHIFT)) & DAC_CR_WAVE2_MASK) + +#define DAC_CR_TEN2_SHIFT (18) +#define DAC_CR_TEN2_MASK (0x01U << DAC_CR_TEN2_SHIFT) +#define DAC_CR_TEN2(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_TEN2_SHIFT)) & DAC_CR_TEN2_MASK) + +#define DAC_CR_BOFF2_SHIFT (17) +#define DAC_CR_BOFF2_MASK (0x01U << DAC_CR_BOFF2_SHIFT) +#define DAC_CR_BOFF2(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_BOFF2_SHIFT)) & DAC_CR_BOFF2_MASK) + +#define DAC_CR_EN2_SHIFT (16) +#define DAC_CR_EN2_MASK (0x01U << DAC_CR_EN2_SHIFT) +#define DAC_CR_EN2(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_EN2_SHIFT)) & DAC_CR_EN2_MASK) + +#define DAC_CR_OEEN1_SHIFT (13) +#define DAC_CR_OEEN1_MASK (0x01U << DAC_CR_OEEN1_SHIFT) +#define DAC_CR_OEEN1(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_OEEN1_SHIFT)) & DAC_CR_OEEN1_MASK) + +#define DAC_CR_DMAEN1_SHIFT (12) +#define DAC_CR_DMAEN1_MASK (0x01U << DAC_CR_DMAEN1_SHIFT) +#define DAC_CR_DMAEN1(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN1_SHIFT)) & DAC_CR_DMAEN1_MASK) + +#define DAC_CR_MAMP1_SHIFT (8) +#define DAC_CR_MAMP1_MASK (0xFU << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_MAMP1_SHIFT)) & DAC_CR_MAMP1_MASK) + +#define DAC_CR_WAVE1_SHIFT (6) +#define DAC_CR_WAVE1_MASK (0x3U << DAC_CR_WAVE1_SHIFT) +#define DAC_CR_WAVE1(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WAVE1_SHIFT)) & DAC_CR_WAVE1_MASK) + +#define DAC_CR_TEN1_SHIFT (2) +#define DAC_CR_TEN1_MASK (0x01U << DAC_CR_TEN1_SHIFT) +#define DAC_CR_TEN1(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_TEN1_SHIFT)) & DAC_CR_TEN1_MASK) + +#define DAC_CR_BOFF1_SHIFT (1) +#define DAC_CR_BOFF1_MASK (0x01U << DAC_CR_BOFF1_SHIFT) +#define DAC_CR_BOFF1(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_BOFF1_SHIFT)) & DAC_CR_BOFF1_MASK) + +#define DAC_CR_EN1_SHIFT (0) +#define DAC_CR_EN1_MASK (0x01U << DAC_CR_EN1_SHIFT) +#define DAC_CR_EN1(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_EN1_SHIFT)) & DAC_CR_EN1_MASK) + +/*! + * @brief DAC_SWTRIGR Register Bit Definition + */ + +#define DAC_SWTRIGR_SWTRIG2_SHIFT (1) +#define DAC_SWTRIGR_SWTRIG2_MASK (0x01U << DAC_SWTRIGR_SWTRIG2_SHIFT) +#define DAC_SWTRIGR_SWTRIG2(x) (((uint32_t)(((uint32_t)(x)) << DAC_SWTRIGR_SWTRIG2_SHIFT)) & DAC_SWTRIGR_SWTRIG2_MASK) + +#define DAC_SWTRIGR_SWTRIG1_SHIFT (0) +#define DAC_SWTRIGR_SWTRIG1_MASK (0x01U << DAC_SWTRIGR_SWTRIG1_SHIFT) +#define DAC_SWTRIGR_SWTRIG1(x) (((uint32_t)(((uint32_t)(x)) << DAC_SWTRIGR_SWTRIG1_SHIFT)) & DAC_SWTRIGR_SWTRIG1_MASK) + +/*! + * @brief DAC_DHR12R1 Register Bit Definition + */ + +#define DAC_DHR12R1_DACC1DHR_SHIFT (0) +#define DAC_DHR12R1_DACC1DHR_MASK (0xFFFU << DAC_DHR12R1_DACC1DHR_SHIFT) +#define DAC_DHR12R1_DACC1DHR(x) (((uint32_t)(((uint32_t)(x)) << DAC_DHR12R1_DACC1DHR_SHIFT)) & DAC_DHR12R1_DACC1DHR_MASK) + +/*! + * @brief DAC_DHR12L1 Register Bit Definition + */ + +#define DAC_DHR12L1_DACC1DHR_SHIFT (4) +#define DAC_DHR12L1_DACC1DHR_MASK (0xFFFU << DAC_DHR12L1_DACC1DHR_SHIFT) +#define DAC_DHR12L1_DACC1DHR(x) (((uint32_t)(((uint32_t)(x)) << DAC_DHR12L1_DACC1DHR_SHIFT)) & DAC_DHR12L1_DACC1DHR_MASK) + +/*! + * @brief DAC_DHR8R1 Register Bit Definition + */ + +#define DAC_DHR8R1_DACC1DHR_SHIFT (0) +#define DAC_DHR8R1_DACC1DHR_MASK (0xFFU << DAC_DHR8R1_DACC1DHR_SHIFT) +#define DAC_DHR8R1_DACC1DHR(x) (((uint32_t)(((uint32_t)(x)) << DAC_DHR8R1_DACC1DHR_SHIFT)) & DAC_DHR8R1_DACC1DHR_MASK) + +/*! + * @brief DAC_DHR12R2 Register Bit Definition + */ + +#define DAC_DHR12R2_DACC2DHR_SHIFT (0) +#define DAC_DHR12R2_DACC2DHR_MASK (0xFFFU << DAC_DHR12R2_DACC2DHR_SHIFT) +#define DAC_DHR12R2_DACC2DHR(x) (((uint32_t)(((uint32_t)(x)) << DAC_DHR12R2_DACC2DHR_SHIFT)) & DAC_DHR12R2_DACC2DHR_MASK) + +/*! + * @brief DAC_DHR12L2 Register Bit Definition + */ + +#define DAC_DHR12L2_DACC2DHR_SHIFT (4) +#define DAC_DHR12L2_DACC2DHR_MASK (0xFFFU << DAC_DHR12L2_DACC2DHR_SHIFT) +#define DAC_DHR12L2_DACC2DHR(x) (((uint32_t)(((uint32_t)(x)) << DAC_DHR12L2_DACC2DHR_SHIFT)) & DAC_DHR12L2_DACC2DHR_MASK) + +/*! + * @brief DAC_DHR8R2 Register Bit Definition + */ + +#define DAC_DHR8R2_DACC2DHR_SHIFT (0) +#define DAC_DHR8R2_DACC2DHR_MASK (0xFFU << DAC_DHR8R2_DACC2DHR_SHIFT) +#define DAC_DHR8R2_DACC2DHR(x) (((uint32_t)(((uint32_t)(x)) << DAC_DHR8R2_DACC2DHR_SHIFT)) & DAC_DHR8R2_DACC2DHR_MASK) + +/*! + * @brief DAC_DHR12RD Register Bit Definition + */ + +#define DAC_DHR12RD_DACC2DHR_SHIFT (16) +#define DAC_DHR12RD_DACC2DHR_MASK (0xFFFU << DAC_DHR12RD_DACC2DHR_SHIFT) +#define DAC_DHR12RD_DACC2DHR(x) (((uint32_t)(((uint32_t)(x)) << DAC_DHR12RD_DACC2DHR_SHIFT)) & DAC_DHR12RD_DACC2DHR_MASK) + +#define DAC_DHR12RD_DACC1DHR_SHIFT (0) +#define DAC_DHR12RD_DACC1DHR_MASK (0xFFFU << DAC_DHR12RD_DACC1DHR_SHIFT) +#define DAC_DHR12RD_DACC1DHR(x) (((uint32_t)(((uint32_t)(x)) << DAC_DHR12RD_DACC1DHR_SHIFT)) & DAC_DHR12RD_DACC1DHR_MASK) + +/*! + * @brief DAC_DHR12LD Register Bit Definition + */ + +#define DAC_DHR12LD_DACC2DHR_SHIFT (20) +#define DAC_DHR12LD_DACC2DHR_MASK (0xFFFU << DAC_DHR12LD_DACC2DHR_SHIFT) +#define DAC_DHR12LD_DACC2DHR(x) (((uint32_t)(((uint32_t)(x)) << DAC_DHR12LD_DACC2DHR_SHIFT)) & DAC_DHR12LD_DACC2DHR_MASK) + +#define DAC_DHR12LD_DACC1DHR_SHIFT (4) +#define DAC_DHR12LD_DACC1DHR_MASK (0xFFFU << DAC_DHR12LD_DACC1DHR_SHIFT) +#define DAC_DHR12LD_DACC1DHR(x) (((uint32_t)(((uint32_t)(x)) << DAC_DHR12LD_DACC1DHR_SHIFT)) & DAC_DHR12LD_DACC1DHR_MASK) + +/*! + * @brief DAC_DHR8RD Register Bit Definition + */ + +#define DAC_DHR8RD_DACC2DHR_SHIFT (8) +#define DAC_DHR8RD_DACC2DHR_MASK (0xFFU << DAC_DHR8RD_DACC2DHR_SHIFT) +#define DAC_DHR8RD_DACC2DHR(x) (((uint32_t)(((uint32_t)(x)) << DAC_DHR8RD_DACC2DHR_SHIFT)) & DAC_DHR8RD_DACC2DHR_MASK) + +#define DAC_DHR8RD_DACC1DHR_SHIFT (0) +#define DAC_DHR8RD_DACC1DHR_MASK (0xFFU << DAC_DHR8RD_DACC1DHR_SHIFT) +#define DAC_DHR8RD_DACC1DHR(x) (((uint32_t)(((uint32_t)(x)) << DAC_DHR8RD_DACC1DHR_SHIFT)) & DAC_DHR8RD_DACC1DHR_MASK) + +/*! + * @brief DAC_DOR1 Register Bit Definition + */ + +#define DAC_DOR1_DACC1DOR_SHIFT (0) +#define DAC_DOR1_DACC1DOR_MASK (0xFFFU << DAC_DOR1_DACC1DOR_SHIFT) +#define DAC_DOR1_DACC1DOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_DOR1_DACC1DOR_SHIFT)) & DAC_DOR1_DACC1DOR_MASK) + +/*! + * @brief DAC_DOR2 Register Bit Definition + */ + +#define DAC_DOR2_DACC2DOR_SHIFT (0) +#define DAC_DOR2_DACC2DOR_MASK (0xFFFU << DAC_DOR2_DACC2DOR_SHIFT) +#define DAC_DOR2_DACC2DOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_DOR2_DACC2DOR_SHIFT)) & DAC_DOR2_DACC2DOR_MASK) + +/*! + * @} + */ /* end of group DAC_Register_Masks */ +/****************************************************************************** + *DAC Instance +*******************************************************************************/ + +#define DAC ((DAC_Type*)DAC_BASE) + +/*! + * @} + */ /* end of group DAC_Peripheral_Access_Layer */ + + + + +/*! + * @addtogroup DBGMCU_Peripheral_Access_Layer DBGMCU Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * DBGMCU Type + ******************************************************************************/ +typedef struct { + __IO uint32_t IDCODE; ///< MCU_IDCODE register offset: 0x00 + __IO uint32_t CR; ///< DEBUG control register offset: 0x04 +} DBGMCU_Type; + +/******************************************************************************* + * DBGMCU Type + ******************************************************************************/ + +/*! + * @addtogroup DBGMCU_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief DBGMCU_IDCODE Register Bit Definition + */ + +#define DBGMCU_IDCODE_DEVID_SHIFT (0) +#define DBGMCU_IDCODE_DEVID_MASK (0xFFFFFFFFU << DBGMCU_IDCODE_DEVID_SHIFT) +#define DBGMCU_IDCODE_DEVID(x) (((uint32_t)(((uint32_t)(x)) << DBGMCU_IDCODE_DEVID_SHIFT)) & DBGMCU_IDCODE_DEVID_MASK) + +/*! + * @brief DBGMCU_CR Register Bit Definition + */ + +#define DBGMCU_CR_DBGTIM7STOP_SHIFT (20) +#define DBGMCU_CR_DBGTIM7STOP_MASK (0x01U << DBGMCU_CR_DBGTIM7STOP_SHIFT) +#define DBGMCU_CR_DBGTIM7STOP(x) (((uint32_t)(((uint32_t)(x)) << DBGMCU_CR_DBGTIM7STOP_SHIFT)) & DBGMCU_CR_DBGTIM7STOP_MASK) + +#define DBGMCU_CR_DBGTIM6STOP_SHIFT (19) +#define DBGMCU_CR_DBGTIM6STOP_MASK (0x01U << DBGMCU_CR_DBGTIM6STOP_SHIFT) +#define DBGMCU_CR_DBGTIM6STOP(x) (((uint32_t)(((uint32_t)(x)) << DBGMCU_CR_DBGTIM6STOP_SHIFT)) & DBGMCU_CR_DBGTIM6STOP_MASK) + +#define DBGMCU_CR_DBGTIM5STOP_SHIFT (18) +#define DBGMCU_CR_DBGTIM5STOP_MASK (0x01U << DBGMCU_CR_DBGTIM5STOP_SHIFT) +#define DBGMCU_CR_DBGTIM5STOP(x) (((uint32_t)(((uint32_t)(x)) << DBGMCU_CR_DBGTIM5STOP_SHIFT)) & DBGMCU_CR_DBGTIM5STOP_MASK) + +#define DBGMCU_CR_DBGTIM8STOP_SHIFT (17) +#define DBGMCU_CR_DBGTIM8STOP_MASK (0x01U << DBGMCU_CR_DBGTIM8STOP_SHIFT) +#define DBGMCU_CR_DBGTIM8STOP(x) (((uint32_t)(((uint32_t)(x)) << DBGMCU_CR_DBGTIM8STOP_SHIFT)) & DBGMCU_CR_DBGTIM8STOP_MASK) + +#define DBGMCU_CR_DBGTIM4STOP_SHIFT (13) +#define DBGMCU_CR_DBGTIM4STOP_MASK (0x01U << DBGMCU_CR_DBGTIM4STOP_SHIFT) +#define DBGMCU_CR_DBGTIM4STOP(x) (((uint32_t)(((uint32_t)(x)) << DBGMCU_CR_DBGTIM4STOP_SHIFT)) & DBGMCU_CR_DBGTIM4STOP_MASK) + +#define DBGMCU_CR_DBGTIM3STOP_SHIFT (12) +#define DBGMCU_CR_DBGTIM3STOP_MASK (0x01U << DBGMCU_CR_DBGTIM3STOP_SHIFT) +#define DBGMCU_CR_DBGTIM3STOP(x) (((uint32_t)(((uint32_t)(x)) << DBGMCU_CR_DBGTIM3STOP_SHIFT)) & DBGMCU_CR_DBGTIM3STOP_MASK) + +#define DBGMCU_CR_DBGTIM2STOP_SHIFT (11) +#define DBGMCU_CR_DBGTIM2STOP_MASK (0x01U << DBGMCU_CR_DBGTIM2STOP_SHIFT) +#define DBGMCU_CR_DBGTIM2STOP(x) (((uint32_t)(((uint32_t)(x)) << DBGMCU_CR_DBGTIM2STOP_SHIFT)) & DBGMCU_CR_DBGTIM2STOP_MASK) + +#define DBGMCU_CR_DBGTIM1STOP_SHIFT (10) +#define DBGMCU_CR_DBGTIM1STOP_MASK (0x01U << DBGMCU_CR_DBGTIM1STOP_SHIFT) +#define DBGMCU_CR_DBGTIM1STOP(x) (((uint32_t)(((uint32_t)(x)) << DBGMCU_CR_DBGTIM1STOP_SHIFT)) & DBGMCU_CR_DBGTIM1STOP_MASK) + +#define DBGMCU_CR_DBGWWDGSTOP_SHIFT (9) +#define DBGMCU_CR_DBGWWDGSTOP_MASK (0x01U << DBGMCU_CR_DBGWWDGSTOP_SHIFT) +#define DBGMCU_CR_DBGWWDGSTOP(x) (((uint32_t)(((uint32_t)(x)) << DBGMCU_CR_DBGWWDGSTOP_SHIFT)) & DBGMCU_CR_DBGWWDGSTOP_MASK) + +#define DBGMCU_CR_DBGIWDGSTOP_SHIFT (8) +#define DBGMCU_CR_DBGIWDGSTOP_MASK (0x01U << DBGMCU_CR_DBGIWDGSTOP_SHIFT) +#define DBGMCU_CR_DBGIWDGSTOP(x) (((uint32_t)(((uint32_t)(x)) << DBGMCU_CR_DBGIWDGSTOP_SHIFT)) & DBGMCU_CR_DBGIWDGSTOP_MASK) + +#define DBGMCU_CR_TRACEMODE_SHIFT (6) +#define DBGMCU_CR_TRACEMODE_MASK (0x3U << DBGMCU_CR_TRACEMODE_SHIFT) +#define DBGMCU_CR_TRACEMODE(x) (((uint32_t)(((uint32_t)(x)) << DBGMCU_CR_TRACEMODE_SHIFT)) & DBGMCU_CR_TRACEMODE_MASK) + +#define DBGMCU_CR_TRACEIOEN_SHIFT (5) +#define DBGMCU_CR_TRACEIOEN_MASK (0x01U << DBGMCU_CR_TRACEIOEN_SHIFT) +#define DBGMCU_CR_TRACEIOEN(x) (((uint32_t)(((uint32_t)(x)) << DBGMCU_CR_TRACEIOEN_SHIFT)) & DBGMCU_CR_TRACEIOEN_MASK) + +#define DBGMCU_CR_DBGSTOPFORLDO_SHIFT (3) +#define DBGMCU_CR_DBGSTOPFORLDO_MASK (0x01U << DBGMCU_CR_DBGSTOPFORLDO_SHIFT) +#define DBGMCU_CR_DBGSTOPFORLDO(x) (((uint32_t)(((uint32_t)(x)) << DBGMCU_CR_DBGSTOPFORLDO_SHIFT)) & DBGMCU_CR_DBGSTOPFORLDO_MASK) + +/*! + * @} + */ /* end of group DBGMCU_Register_Masks */ +/****************************************************************************** + *DBGMCU Instance +*******************************************************************************/ + +#define DBGMCU ((DBGMCU_Type*)DBGMCU_BASE) + +/*! + * @} + */ /* end of group DBGMCU_Peripheral_Access_Layer */ + + + + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * DMA Type + ******************************************************************************/ +#define DMA_CHANNEL_COUNT 8u + +typedef struct { + __IO uint32_t ISR; ///< DMA Interrupt Status Register offset: 0x00 + __IO uint32_t IFCR; ///< DMA Interrupt Flag Clear Register offset: 0x04 + struct { + __IO uint32_t CCR; ///< DMAchannelxconfigurationregister offset: 0x08 + __IO uint32_t CNDTR; ///< DMAchannelxtransferquantityregister offset: 0x0C + __IO uint32_t CPAR; ///< DMAchannelxperipheraladdressregister offset: 0x10 + __IO uint32_t CMAR; ///< DMAchannelxmemoryaddressregister offset: 0x14 + __IO uint32_t Reserved0; + } CH[DMA_CHANNEL_COUNT]; +} DMA_Type; + +/******************************************************************************* + * DMA Type + ******************************************************************************/ + +/*! + * @addtogroup DMA_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief DMA_ISR Register Bit Definition + */ + +#define DMA_ISR_TEIF8_SHIFT (31) +#define DMA_ISR_TEIF8_MASK (0x01U << DMA_ISR_TEIF8_SHIFT) +#define DMA_ISR_TEIF8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_TEIF8_SHIFT)) & DMA_ISR_TEIF8_MASK) + +#define DMA_ISR_HTIF8_SHIFT (30) +#define DMA_ISR_HTIF8_MASK (0x01U << DMA_ISR_HTIF8_SHIFT) +#define DMA_ISR_HTIF8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_HTIF8_SHIFT)) & DMA_ISR_HTIF8_MASK) + +#define DMA_ISR_TCIF8_SHIFT (29) +#define DMA_ISR_TCIF8_MASK (0x01U << DMA_ISR_TCIF8_SHIFT) +#define DMA_ISR_TCIF8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_TCIF8_SHIFT)) & DMA_ISR_TCIF8_MASK) + +#define DMA_ISR_GIF8_SHIFT (28) +#define DMA_ISR_GIF8_MASK (0x01U << DMA_ISR_GIF8_SHIFT) +#define DMA_ISR_GIF8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_GIF8_SHIFT)) & DMA_ISR_GIF8_MASK) + +#define DMA_ISR_TEIF7_SHIFT (27) +#define DMA_ISR_TEIF7_MASK (0x01U << DMA_ISR_TEIF7_SHIFT) +#define DMA_ISR_TEIF7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_TEIF7_SHIFT)) & DMA_ISR_TEIF7_MASK) + +#define DMA_ISR_HTIF7_SHIFT (26) +#define DMA_ISR_HTIF7_MASK (0x01U << DMA_ISR_HTIF7_SHIFT) +#define DMA_ISR_HTIF7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_HTIF7_SHIFT)) & DMA_ISR_HTIF7_MASK) + +#define DMA_ISR_TCIF7_SHIFT (25) +#define DMA_ISR_TCIF7_MASK (0x01U << DMA_ISR_TCIF7_SHIFT) +#define DMA_ISR_TCIF7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_TCIF7_SHIFT)) & DMA_ISR_TCIF7_MASK) + +#define DMA_ISR_GIF7_SHIFT (24) +#define DMA_ISR_GIF7_MASK (0x01U << DMA_ISR_GIF7_SHIFT) +#define DMA_ISR_GIF7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_GIF7_SHIFT)) & DMA_ISR_GIF7_MASK) + +#define DMA_ISR_TEIF6_SHIFT (23) +#define DMA_ISR_TEIF6_MASK (0x01U << DMA_ISR_TEIF6_SHIFT) +#define DMA_ISR_TEIF6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_TEIF6_SHIFT)) & DMA_ISR_TEIF6_MASK) + +#define DMA_ISR_HTIF6_SHIFT (22) +#define DMA_ISR_HTIF6_MASK (0x01U << DMA_ISR_HTIF6_SHIFT) +#define DMA_ISR_HTIF6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_HTIF6_SHIFT)) & DMA_ISR_HTIF6_MASK) + +#define DMA_ISR_TCIF6_SHIFT (21) +#define DMA_ISR_TCIF6_MASK (0x01U << DMA_ISR_TCIF6_SHIFT) +#define DMA_ISR_TCIF6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_TCIF6_SHIFT)) & DMA_ISR_TCIF6_MASK) + +#define DMA_ISR_GIF6_SHIFT (20) +#define DMA_ISR_GIF6_MASK (0x01U << DMA_ISR_GIF6_SHIFT) +#define DMA_ISR_GIF6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_GIF6_SHIFT)) & DMA_ISR_GIF6_MASK) + +#define DMA_ISR_TEIF5_SHIFT (19) +#define DMA_ISR_TEIF5_MASK (0x01U << DMA_ISR_TEIF5_SHIFT) +#define DMA_ISR_TEIF5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_TEIF5_SHIFT)) & DMA_ISR_TEIF5_MASK) + +#define DMA_ISR_HTIF5_SHIFT (18) +#define DMA_ISR_HTIF5_MASK (0x01U << DMA_ISR_HTIF5_SHIFT) +#define DMA_ISR_HTIF5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_HTIF5_SHIFT)) & DMA_ISR_HTIF5_MASK) + +#define DMA_ISR_TCIF5_SHIFT (17) +#define DMA_ISR_TCIF5_MASK (0x01U << DMA_ISR_TCIF5_SHIFT) +#define DMA_ISR_TCIF5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_TCIF5_SHIFT)) & DMA_ISR_TCIF5_MASK) + +#define DMA_ISR_GIF5_SHIFT (16) +#define DMA_ISR_GIF5_MASK (0x01U << DMA_ISR_GIF5_SHIFT) +#define DMA_ISR_GIF5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_GIF5_SHIFT)) & DMA_ISR_GIF5_MASK) + +#define DMA_ISR_TEIF4_SHIFT (15) +#define DMA_ISR_TEIF4_MASK (0x01U << DMA_ISR_TEIF4_SHIFT) +#define DMA_ISR_TEIF4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_TEIF4_SHIFT)) & DMA_ISR_TEIF4_MASK) + +#define DMA_ISR_HTIF4_SHIFT (14) +#define DMA_ISR_HTIF4_MASK (0x01U << DMA_ISR_HTIF4_SHIFT) +#define DMA_ISR_HTIF4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_HTIF4_SHIFT)) & DMA_ISR_HTIF4_MASK) + +#define DMA_ISR_TCIF4_SHIFT (13) +#define DMA_ISR_TCIF4_MASK (0x01U << DMA_ISR_TCIF4_SHIFT) +#define DMA_ISR_TCIF4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_TCIF4_SHIFT)) & DMA_ISR_TCIF4_MASK) + +#define DMA_ISR_GIF4_SHIFT (12) +#define DMA_ISR_GIF4_MASK (0x01U << DMA_ISR_GIF4_SHIFT) +#define DMA_ISR_GIF4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_GIF4_SHIFT)) & DMA_ISR_GIF4_MASK) + +#define DMA_ISR_TEIF3_SHIFT (11) +#define DMA_ISR_TEIF3_MASK (0x01U << DMA_ISR_TEIF3_SHIFT) +#define DMA_ISR_TEIF3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_TEIF3_SHIFT)) & DMA_ISR_TEIF3_MASK) + +#define DMA_ISR_HTIF3_SHIFT (10) +#define DMA_ISR_HTIF3_MASK (0x01U << DMA_ISR_HTIF3_SHIFT) +#define DMA_ISR_HTIF3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_HTIF3_SHIFT)) & DMA_ISR_HTIF3_MASK) + +#define DMA_ISR_TCIF3_SHIFT (9) +#define DMA_ISR_TCIF3_MASK (0x01U << DMA_ISR_TCIF3_SHIFT) +#define DMA_ISR_TCIF3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_TCIF3_SHIFT)) & DMA_ISR_TCIF3_MASK) + +#define DMA_ISR_GIF3_SHIFT (8) +#define DMA_ISR_GIF3_MASK (0x01U << DMA_ISR_GIF3_SHIFT) +#define DMA_ISR_GIF3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_GIF3_SHIFT)) & DMA_ISR_GIF3_MASK) + +#define DMA_ISR_TEIF2_SHIFT (7) +#define DMA_ISR_TEIF2_MASK (0x01U << DMA_ISR_TEIF2_SHIFT) +#define DMA_ISR_TEIF2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_TEIF2_SHIFT)) & DMA_ISR_TEIF2_MASK) + +#define DMA_ISR_HTIF2_SHIFT (6) +#define DMA_ISR_HTIF2_MASK (0x01U << DMA_ISR_HTIF2_SHIFT) +#define DMA_ISR_HTIF2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_HTIF2_SHIFT)) & DMA_ISR_HTIF2_MASK) + +#define DMA_ISR_TCIF2_SHIFT (5) +#define DMA_ISR_TCIF2_MASK (0x01U << DMA_ISR_TCIF2_SHIFT) +#define DMA_ISR_TCIF2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_TCIF2_SHIFT)) & DMA_ISR_TCIF2_MASK) + +#define DMA_ISR_GIF2_SHIFT (4) +#define DMA_ISR_GIF2_MASK (0x01U << DMA_ISR_GIF2_SHIFT) +#define DMA_ISR_GIF2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_GIF2_SHIFT)) & DMA_ISR_GIF2_MASK) + +#define DMA_ISR_TEIF1_SHIFT (3) +#define DMA_ISR_TEIF1_MASK (0x01U << DMA_ISR_TEIF1_SHIFT) +#define DMA_ISR_TEIF1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_TEIF1_SHIFT)) & DMA_ISR_TEIF1_MASK) + +#define DMA_ISR_HTIF1_SHIFT (2) +#define DMA_ISR_HTIF1_MASK (0x01U << DMA_ISR_HTIF1_SHIFT) +#define DMA_ISR_HTIF1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_HTIF1_SHIFT)) & DMA_ISR_HTIF1_MASK) + +#define DMA_ISR_TCIF1_SHIFT (1) +#define DMA_ISR_TCIF1_MASK (0x01U << DMA_ISR_TCIF1_SHIFT) +#define DMA_ISR_TCIF1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_TCIF1_SHIFT)) & DMA_ISR_TCIF1_MASK) + +#define DMA_ISR_GIF1_SHIFT (0) +#define DMA_ISR_GIF1_MASK (0x01U << DMA_ISR_GIF1_SHIFT) +#define DMA_ISR_GIF1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ISR_GIF1_SHIFT)) & DMA_ISR_GIF1_MASK) + +/*! + * @brief DMA_IFCR Register Bit Definition + */ + +#define DMA_IFCR_CTEIF8_SHIFT (31) +#define DMA_IFCR_CTEIF8_MASK (0x01U << DMA_IFCR_CTEIF8_SHIFT) +#define DMA_IFCR_CTEIF8(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CTEIF8_SHIFT)) & DMA_IFCR_CTEIF8_MASK) + +#define DMA_IFCR_CHTIF8_SHIFT (30) +#define DMA_IFCR_CHTIF8_MASK (0x01U << DMA_IFCR_CHTIF8_SHIFT) +#define DMA_IFCR_CHTIF8(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CHTIF8_SHIFT)) & DMA_IFCR_CHTIF8_MASK) + +#define DMA_IFCR_CTCIF8_SHIFT (29) +#define DMA_IFCR_CTCIF8_MASK (0x01U << DMA_IFCR_CTCIF8_SHIFT) +#define DMA_IFCR_CTCIF8(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CTCIF8_SHIFT)) & DMA_IFCR_CTCIF8_MASK) + +#define DMA_IFCR_CGIF8_SHIFT (28) +#define DMA_IFCR_CGIF8_MASK (0x01U << DMA_IFCR_CGIF8_SHIFT) +#define DMA_IFCR_CGIF8(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CGIF8_SHIFT)) & DMA_IFCR_CGIF8_MASK) + +#define DMA_IFCR_CTEIF7_SHIFT (27) +#define DMA_IFCR_CTEIF7_MASK (0x01U << DMA_IFCR_CTEIF7_SHIFT) +#define DMA_IFCR_CTEIF7(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CTEIF7_SHIFT)) & DMA_IFCR_CTEIF7_MASK) + +#define DMA_IFCR_CHTIF7_SHIFT (26) +#define DMA_IFCR_CHTIF7_MASK (0x01U << DMA_IFCR_CHTIF7_SHIFT) +#define DMA_IFCR_CHTIF7(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CHTIF7_SHIFT)) & DMA_IFCR_CHTIF7_MASK) + +#define DMA_IFCR_CTCIF7_SHIFT (25) +#define DMA_IFCR_CTCIF7_MASK (0x01U << DMA_IFCR_CTCIF7_SHIFT) +#define DMA_IFCR_CTCIF7(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CTCIF7_SHIFT)) & DMA_IFCR_CTCIF7_MASK) + +#define DMA_IFCR_CGIF7_SHIFT (24) +#define DMA_IFCR_CGIF7_MASK (0x01U << DMA_IFCR_CGIF7_SHIFT) +#define DMA_IFCR_CGIF7(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CGIF7_SHIFT)) & DMA_IFCR_CGIF7_MASK) + +#define DMA_IFCR_CTEIF6_SHIFT (23) +#define DMA_IFCR_CTEIF6_MASK (0x01U << DMA_IFCR_CTEIF6_SHIFT) +#define DMA_IFCR_CTEIF6(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CTEIF6_SHIFT)) & DMA_IFCR_CTEIF6_MASK) + +#define DMA_IFCR_CHTIF6_SHIFT (22) +#define DMA_IFCR_CHTIF6_MASK (0x01U << DMA_IFCR_CHTIF6_SHIFT) +#define DMA_IFCR_CHTIF6(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CHTIF6_SHIFT)) & DMA_IFCR_CHTIF6_MASK) + +#define DMA_IFCR_CTCIF6_SHIFT (21) +#define DMA_IFCR_CTCIF6_MASK (0x01U << DMA_IFCR_CTCIF6_SHIFT) +#define DMA_IFCR_CTCIF6(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CTCIF6_SHIFT)) & DMA_IFCR_CTCIF6_MASK) + +#define DMA_IFCR_CGIF6_SHIFT (20) +#define DMA_IFCR_CGIF6_MASK (0x01U << DMA_IFCR_CGIF6_SHIFT) +#define DMA_IFCR_CGIF6(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CGIF6_SHIFT)) & DMA_IFCR_CGIF6_MASK) + +#define DMA_IFCR_CTEIF5_SHIFT (19) +#define DMA_IFCR_CTEIF5_MASK (0x01U << DMA_IFCR_CTEIF5_SHIFT) +#define DMA_IFCR_CTEIF5(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CTEIF5_SHIFT)) & DMA_IFCR_CTEIF5_MASK) + +#define DMA_IFCR_CHTIF5_SHIFT (18) +#define DMA_IFCR_CHTIF5_MASK (0x01U << DMA_IFCR_CHTIF5_SHIFT) +#define DMA_IFCR_CHTIF5(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CHTIF5_SHIFT)) & DMA_IFCR_CHTIF5_MASK) + +#define DMA_IFCR_CTCIF5_SHIFT (17) +#define DMA_IFCR_CTCIF5_MASK (0x01U << DMA_IFCR_CTCIF5_SHIFT) +#define DMA_IFCR_CTCIF5(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CTCIF5_SHIFT)) & DMA_IFCR_CTCIF5_MASK) + +#define DMA_IFCR_CGIF5_SHIFT (16) +#define DMA_IFCR_CGIF5_MASK (0x01U << DMA_IFCR_CGIF5_SHIFT) +#define DMA_IFCR_CGIF5(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CGIF5_SHIFT)) & DMA_IFCR_CGIF5_MASK) + +#define DMA_IFCR_CTEIF4_SHIFT (15) +#define DMA_IFCR_CTEIF4_MASK (0x01U << DMA_IFCR_CTEIF4_SHIFT) +#define DMA_IFCR_CTEIF4(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CTEIF4_SHIFT)) & DMA_IFCR_CTEIF4_MASK) + +#define DMA_IFCR_CHTIF4_SHIFT (14) +#define DMA_IFCR_CHTIF4_MASK (0x01U << DMA_IFCR_CHTIF4_SHIFT) +#define DMA_IFCR_CHTIF4(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CHTIF4_SHIFT)) & DMA_IFCR_CHTIF4_MASK) + +#define DMA_IFCR_CTCIF4_SHIFT (13) +#define DMA_IFCR_CTCIF4_MASK (0x01U << DMA_IFCR_CTCIF4_SHIFT) +#define DMA_IFCR_CTCIF4(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CTCIF4_SHIFT)) & DMA_IFCR_CTCIF4_MASK) + +#define DMA_IFCR_CGIF4_SHIFT (12) +#define DMA_IFCR_CGIF4_MASK (0x01U << DMA_IFCR_CGIF4_SHIFT) +#define DMA_IFCR_CGIF4(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CGIF4_SHIFT)) & DMA_IFCR_CGIF4_MASK) + +#define DMA_IFCR_CTEIF3_SHIFT (11) +#define DMA_IFCR_CTEIF3_MASK (0x01U << DMA_IFCR_CTEIF3_SHIFT) +#define DMA_IFCR_CTEIF3(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CTEIF3_SHIFT)) & DMA_IFCR_CTEIF3_MASK) + +#define DMA_IFCR_CHTIF3_SHIFT (10) +#define DMA_IFCR_CHTIF3_MASK (0x01U << DMA_IFCR_CHTIF3_SHIFT) +#define DMA_IFCR_CHTIF3(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CHTIF3_SHIFT)) & DMA_IFCR_CHTIF3_MASK) + +#define DMA_IFCR_CTCIF3_SHIFT (9) +#define DMA_IFCR_CTCIF3_MASK (0x01U << DMA_IFCR_CTCIF3_SHIFT) +#define DMA_IFCR_CTCIF3(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CTCIF3_SHIFT)) & DMA_IFCR_CTCIF3_MASK) + +#define DMA_IFCR_CGIF3_SHIFT (8) +#define DMA_IFCR_CGIF3_MASK (0x01U << DMA_IFCR_CGIF3_SHIFT) +#define DMA_IFCR_CGIF3(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CGIF3_SHIFT)) & DMA_IFCR_CGIF3_MASK) + +#define DMA_IFCR_CTEIF2_SHIFT (7) +#define DMA_IFCR_CTEIF2_MASK (0x01U << DMA_IFCR_CTEIF2_SHIFT) +#define DMA_IFCR_CTEIF2(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CTEIF2_SHIFT)) & DMA_IFCR_CTEIF2_MASK) + +#define DMA_IFCR_CHTIF2_SHIFT (6) +#define DMA_IFCR_CHTIF2_MASK (0x01U << DMA_IFCR_CHTIF2_SHIFT) +#define DMA_IFCR_CHTIF2(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CHTIF2_SHIFT)) & DMA_IFCR_CHTIF2_MASK) + +#define DMA_IFCR_CTCIF2_SHIFT (5) +#define DMA_IFCR_CTCIF2_MASK (0x01U << DMA_IFCR_CTCIF2_SHIFT) +#define DMA_IFCR_CTCIF2(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CTCIF2_SHIFT)) & DMA_IFCR_CTCIF2_MASK) + +#define DMA_IFCR_CGIF2_SHIFT (4) +#define DMA_IFCR_CGIF2_MASK (0x01U << DMA_IFCR_CGIF2_SHIFT) +#define DMA_IFCR_CGIF2(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CGIF2_SHIFT)) & DMA_IFCR_CGIF2_MASK) + +#define DMA_IFCR_CTEIF1_SHIFT (3) +#define DMA_IFCR_CTEIF1_MASK (0x01U << DMA_IFCR_CTEIF1_SHIFT) +#define DMA_IFCR_CTEIF1(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CTEIF1_SHIFT)) & DMA_IFCR_CTEIF1_MASK) + +#define DMA_IFCR_CHTIF1_SHIFT (2) +#define DMA_IFCR_CHTIF1_MASK (0x01U << DMA_IFCR_CHTIF1_SHIFT) +#define DMA_IFCR_CHTIF1(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CHTIF1_SHIFT)) & DMA_IFCR_CHTIF1_MASK) + +#define DMA_IFCR_CTCIF1_SHIFT (1) +#define DMA_IFCR_CTCIF1_MASK (0x01U << DMA_IFCR_CTCIF1_SHIFT) +#define DMA_IFCR_CTCIF1(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CTCIF1_SHIFT)) & DMA_IFCR_CTCIF1_MASK) + +#define DMA_IFCR_CGIF1_SHIFT (0) +#define DMA_IFCR_CGIF1_MASK (0x01U << DMA_IFCR_CGIF1_SHIFT) +#define DMA_IFCR_CGIF1(x) (((uint32_t)(((uint32_t)(x)) << DMA_IFCR_CGIF1_SHIFT)) & DMA_IFCR_CGIF1_MASK) + +/*! + * @brief DMA_CCR Register Bit Definition + */ + +#define DMA_CCR_BURSTEN_SHIFT (16) +#define DMA_CCR_BURSTEN_MASK (0x01U << DMA_CCR_BURSTEN_SHIFT) +#define DMA_CCR_BURSTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CCR_BURSTEN_SHIFT)) & DMA_CCR_BURSTEN_MASK) + +#define DMA_CCR_ARE_SHIFT (15) +#define DMA_CCR_ARE_MASK (0x01U << DMA_CCR_ARE_SHIFT) +#define DMA_CCR_ARE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CCR_ARE_SHIFT)) & DMA_CCR_ARE_MASK) + +#define DMA_CCR_MEM2MEM_SHIFT (14) +#define DMA_CCR_MEM2MEM_MASK (0x01U << DMA_CCR_MEM2MEM_SHIFT) +#define DMA_CCR_MEM2MEM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CCR_MEM2MEM_SHIFT)) & DMA_CCR_MEM2MEM_MASK) + +#define DMA_CCR_PL_SHIFT (12) +#define DMA_CCR_PL_MASK (0x3U << DMA_CCR_PL_SHIFT) +#define DMA_CCR_PL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CCR_PL_SHIFT)) & DMA_CCR_PL_MASK) + +#define DMA_CCR_MSIZE_SHIFT (10) +#define DMA_CCR_MSIZE_MASK (0x3U << DMA_CCR_MSIZE_SHIFT) +#define DMA_CCR_MSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CCR_MSIZE_SHIFT)) & DMA_CCR_MSIZE_MASK) + +#define DMA_CCR_PSIZE_SHIFT (8) +#define DMA_CCR_PSIZE_MASK (0x3U << DMA_CCR_PSIZE_SHIFT) +#define DMA_CCR_PSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CCR_PSIZE_SHIFT)) & DMA_CCR_PSIZE_MASK) + +#define DMA_CCR_MINC_SHIFT (7) +#define DMA_CCR_MINC_MASK (0x01U << DMA_CCR_MINC_SHIFT) +#define DMA_CCR_MINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CCR_MINC_SHIFT)) & DMA_CCR_MINC_MASK) + +#define DMA_CCR_PINC_SHIFT (6) +#define DMA_CCR_PINC_MASK (0x01U << DMA_CCR_PINC_SHIFT) +#define DMA_CCR_PINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CCR_PINC_SHIFT)) & DMA_CCR_PINC_MASK) + +#define DMA_CCR_CIRC_SHIFT (5) +#define DMA_CCR_CIRC_MASK (0x01U << DMA_CCR_CIRC_SHIFT) +#define DMA_CCR_CIRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CCR_CIRC_SHIFT)) & DMA_CCR_CIRC_MASK) + +#define DMA_CCR_DIR_SHIFT (4) +#define DMA_CCR_DIR_MASK (0x01U << DMA_CCR_DIR_SHIFT) +#define DMA_CCR_DIR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CCR_DIR_SHIFT)) & DMA_CCR_DIR_MASK) + +#define DMA_CCR_TEIE_SHIFT (3) +#define DMA_CCR_TEIE_MASK (0x01U << DMA_CCR_TEIE_SHIFT) +#define DMA_CCR_TEIE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CCR_TEIE_SHIFT)) & DMA_CCR_TEIE_MASK) + +#define DMA_CCR_HTIE_SHIFT (2) +#define DMA_CCR_HTIE_MASK (0x01U << DMA_CCR_HTIE_SHIFT) +#define DMA_CCR_HTIE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CCR_HTIE_SHIFT)) & DMA_CCR_HTIE_MASK) + +#define DMA_CCR_TCIE_SHIFT (1) +#define DMA_CCR_TCIE_MASK (0x01U << DMA_CCR_TCIE_SHIFT) +#define DMA_CCR_TCIE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CCR_TCIE_SHIFT)) & DMA_CCR_TCIE_MASK) + +#define DMA_CCR_EN_SHIFT (0) +#define DMA_CCR_EN_MASK (0x01U << DMA_CCR_EN_SHIFT) +#define DMA_CCR_EN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CCR_EN_SHIFT)) & DMA_CCR_EN_MASK) + +/*! + * @brief DMA_CNDTR Register Bit Definition + */ + +#define DMA_CNDTR_NDT_SHIFT (0) +#define DMA_CNDTR_NDT_MASK (0xFFFFU << DMA_CNDTR_NDT_SHIFT) +#define DMA_CNDTR_NDT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CNDTR_NDT_SHIFT)) & DMA_CNDTR_NDT_MASK) + +/*! + * @brief DMA_CPAR Register Bit Definition + */ + +#define DMA_CPAR_PA_SHIFT (0) +#define DMA_CPAR_PA_MASK (0xFFFFFFFFU << DMA_CPAR_PA_SHIFT) +#define DMA_CPAR_PA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CPAR_PA_SHIFT)) & DMA_CPAR_PA_MASK) + +/*! + * @brief DMA_CMAR Register Bit Definition + */ + +#define DMA_CMAR_MA_SHIFT (0) +#define DMA_CMAR_MA_MASK (0xFFFFFFFFU << DMA_CMAR_MA_SHIFT) +#define DMA_CMAR_MA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CMAR_MA_SHIFT)) & DMA_CMAR_MA_MASK) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ +/****************************************************************************** + *DMA Instance +*******************************************************************************/ + +#define DMA1 ((DMA_Type*)DMA1_BASE) +#define DMA2 ((DMA_Type*)DMA2_BASE) + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + +/*! + * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * ENET Type + ******************************************************************************/ +typedef struct { + __IO uint32_t MACCR; ///< MAC configuration register offset: 0x0000 + __IO uint32_t MACAFR; ///< MAC address filter control register offset: 0x0004 + __IO uint32_t MACHTHR; ///< MAC HASH table high register offset: 0x0008 + __IO uint32_t MACHTLR; ///< MAC HASH table low register offset: 0x000C + __IO uint32_t MACSMIAR; ///< SMI address register offset: 0x0010 + __IO uint32_t MACSMIDR; ///< SMI data register offset: 0x0014 + __IO uint32_t MACFCR; ///< MAC flow control register offset: 0x0018 + __IO uint32_t MACVLTRR; ///< MAC VLAN Tag Register offset: 0x001C + __IO uint32_t Reserved7[1]; ///< Reserved + __IO uint32_t MACSR; ///< MAC status register offset: 0x0024 + __IO uint32_t PMTRWFR; ///< MAC Remote Wakeup Frame Filter Register offset: 0x0028 + __IO uint32_t PMTCR; ///< MAC PMT Control Register offset: 0x002C + __IO uint32_t Reserved8[2]; ///< Reserved + __IO uint32_t MACISR; ///< MAC Interrupt Status Register offset: 0x0038 + __IO uint32_t MACIMR; ///< MAC Interrupt Mask Register offset: 0x003C + struct{ + __IO uint32_t MACAHR; ///< MAC filter address high register offset: 0x0040 + __IO uint32_t MACALR; ///< MAC filter address low register offset: 0x0044 + }MACAH_L[6]; ///< 0~5 group + __IO uint32_t MMCCR; ///< MMC Control Register offset: 0x0100 + __IO uint32_t MMCRSR; ///< MMC Receive Status Register offset: 0x0104 + __IO uint32_t MMCTSR; ///< MMC Transmit Status Register offset: 0x0108 + __IO uint32_t MMCRIR; ///< MMC receive interrupt register offset: 0x010C + __IO uint32_t MMCTIR; ///< MMC Transmit Interrupt Register offset: 0x0110 + __IO uint32_t Reserved9[14]; ///< Reserved + __IO uint32_t MMCTGSCR; ///< MMC sends a good frame statistics register after a single collision error offset: 0x014C + __IO uint32_t MMCTGMCR; ///< MMC sends good frame statistics register after multiple collision errors offset: 0x0150 + __IO uint32_t Reserved10[5]; ///< Reserved + __IO uint32_t MMCTGR; ///< MMC sends good frame pass statistics register offset: 0x0168 + __IO uint32_t Reserved11[10]; ///< Reserved + __IO uint32_t MMCRCRCER; ///< MMC CRC Error Received Frame Statistics Register offset: 0x0194 + __IO uint32_t MMCRALIER; ///< MMC Alignment Error Received Frame Statistics Register offset: 0x0198 + __IO uint32_t Reserved12[10]; ///< Reserved + __IO uint32_t MMCRUGR; ///< MMC Receive Unicast Good Frame Statistics Register offset: 0x01C4 + __IO uint32_t Reserved13[239]; ///< Reserved + __IO uint32_t MACVLTTR; ///< MAC VLAN TAG send register offset: 0x0584 + __IO uint32_t MACVLHTR; ///< MAC VLAN HASH Table Register offset: 0x0588 + __IO uint32_t Reserved14[93]; ///< Reserved + __IO uint32_t PTPCR; ///< PTP Control Register offset: 0x0700 + __IO uint32_t PTPNSAR; ///< PTP subsecond adder register offset: 0x0704 + __IO uint32_t PTPSBSR; ///< PTP System Second Register offset: 0x0708 + __IO uint32_t PTPSNSR; ///< PTP System Subsecond Register offset: 0x070C + __IO uint32_t PTPUBSR; ///< PTP Update Seconds Register offset: 0x0710 + __IO uint32_t PTPUNSR; ///< PTP update subsecond register offset: 0x0714 + __IO uint32_t PTPBSAR; ///< PTP Basic Addend Register offset: 0x0718 + __IO uint32_t PTPTBSR0; ///< PTP Target Seconds Register 0 offset: 0x071C + __IO uint32_t PTPTNSR0; ///< PTP Target Subsecond Register 0 offset: 0x0720 + __IO uint32_t Reserved15[1]; ///< Reserved + __IO uint32_t PTPSR; ///< PTP Status Register offset: 0x0728 + __IO uint32_t PTPPPSR; ///< PTP PPS Control Register offset: 0x072C + __IO uint32_t Reserved16[20]; ///< Reserved + __IO uint32_t PTPTBSR1; ///< PTP Target Seconds Register 1 offset: 0x0780 + __IO uint32_t PTPTNSR1; ///< PTP Target Subsecond Register 1 offset: 0x0784 + __IO uint32_t Reserved17[542]; ///< Reserved + __IO uint32_t DMABSR; ///< DMA bus control register offset: 0x1000 + __IO uint32_t DMATXPDR; ///< DMA transmit polling register offset: 0x1004 + __IO uint32_t DMARXPDR; ///< DMA Receive Polling Register offset: 0x1008 + __IO uint32_t DMARXDSAR; ///< DMA Receive Descriptor Address Register offset: 0x100C + __IO uint32_t DMATXDSAR; ///< DMA transmit descriptor address register offset: 0x1010 + __IO uint32_t DMASR; ///< DMA status register offset: 0x1014 + __IO uint32_t DMAMDR; ///< DMA work mode register offset: 0x1018 + __IO uint32_t DMAIR; ///< DMA Interrupt Register offset: 0x101C + __IO uint32_t DMAFLCR; ///< DMA Frame Loss Statistics Register offset: 0x1020 + __IO uint32_t DMAWDTR; ///< DMA Watchdog Timing Register offset: 0x1024 + __IO uint32_t Reserved18[8]; ///< Reserved + __IO uint32_t DMACURTXDSAR; ///< DMA current transmit descriptor address registeroffset: 0x1048 + __IO uint32_t DMACURRXDSAR; ///< DMA current receive descriptor address registeroffset: 0x104C + __IO uint32_t DMACURTXBFAR; ///< DMA current send buffer address register offset: 0x1050 + __IO uint32_t DMACURRXBFAR; ///< DMA current receive buffer address register offset: 0x1054 + +} ENET_Type; + +/******************************************************************************* + * ENET Type + ******************************************************************************/ + +/*! + * @addtogroup ENET_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief ENET_MACSMIAR Register Bit Definition + */ + +#define ENET_MACSMIAR_SMIADD_SHIFT (11) +#define ENET_MACSMIAR_SMIADD_MASK (0x1FU << ENET_MACSMIAR_SMIADD_SHIFT) +#define ENET_MACSMIAR_SMIADD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSMIAR_SMIADD_SHIFT)) & ENET_MACSMIAR_SMIADD_MASK) + +#define ENET_MACSMIAR_SMIREG_SHIFT (6) +#define ENET_MACSMIAR_SMIREG_MASK (0x1FU << ENET_MACSMIAR_SMIREG_SHIFT) +#define ENET_MACSMIAR_SMIREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSMIAR_SMIREG_SHIFT)) & ENET_MACSMIAR_SMIREG_MASK) + +#define ENET_MACSMIAR_SMICLK_SHIFT (2) +#define ENET_MACSMIAR_SMICLK_MASK (0xFU << ENET_MACSMIAR_SMICLK_SHIFT) +#define ENET_MACSMIAR_SMICLK(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSMIAR_SMICLK_SHIFT)) & ENET_MACSMIAR_SMICLK_MASK) + +#define ENET_MACSMIAR_SMIWR_SHIFT (1) +#define ENET_MACSMIAR_SMIWR_MASK (0x01U << ENET_MACSMIAR_SMIWR_SHIFT) +#define ENET_MACSMIAR_SMIWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSMIAR_SMIWR_SHIFT)) & ENET_MACSMIAR_SMIWR_MASK) + +#define ENET_MACSMIAR_SMIBY_SHIFT (0) +#define ENET_MACSMIAR_SMIBY_MASK (0x01U << ENET_MACSMIAR_SMIBY_SHIFT) +#define ENET_MACSMIAR_SMIBY(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSMIAR_SMIBY_SHIFT)) & ENET_MACSMIAR_SMIBY_MASK) + +/*! + * @brief ENET_MACSMIDR Register Bit Definition + */ + +#define ENET_MACSMIDR_SMIDATA_SHIFT (0) +#define ENET_MACSMIDR_SMIDATA_MASK (0xFFFFU << ENET_MACSMIDR_SMIDATA_SHIFT) +#define ENET_MACSMIDR_SMIDATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSMIDR_SMIDATA_SHIFT)) & ENET_MACSMIDR_SMIDATA_MASK) + +/*! + * @brief ENET_MACCR Register Bit Definition + */ + +#define ENET_MACCR_SAIRC_SHIFT (28) +#define ENET_MACCR_SAIRC_MASK (0xFU << ENET_MACCR_SAIRC_SHIFT) +#define ENET_MACCR_SAIRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACCR_SAIRC_SHIFT)) & ENET_MACCR_SAIRC_MASK) + +#define ENET_MACCR_CST_SHIFT (25) +#define ENET_MACCR_CST_MASK (0x01U << ENET_MACCR_CST_SHIFT) +#define ENET_MACCR_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACCR_CST_SHIFT)) & ENET_MACCR_CST_MASK) + +#define ENET_MACCR_WTD_SHIFT (23) +#define ENET_MACCR_WTD_MASK (0x01U << ENET_MACCR_WTD_SHIFT) +#define ENET_MACCR_WTD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACCR_WTD_SHIFT)) & ENET_MACCR_WTD_MASK) + +#define ENET_MACCR_JAB_SHIFT (22) +#define ENET_MACCR_JAB_MASK (0x01U << ENET_MACCR_JAB_SHIFT) +#define ENET_MACCR_JAB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACCR_JAB_SHIFT)) & ENET_MACCR_JAB_MASK) + +#define ENET_MACCR_IFG_SHIFT (17) +#define ENET_MACCR_IFG_MASK (0x7U << ENET_MACCR_IFG_SHIFT) +#define ENET_MACCR_IFG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACCR_IFG_SHIFT)) & ENET_MACCR_IFG_MASK) + +#define ENET_MACCR_MCRS_SHIFT (16) +#define ENET_MACCR_MCRS_MASK (0x01U << ENET_MACCR_MCRS_SHIFT) +#define ENET_MACCR_MCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACCR_MCRS_SHIFT)) & ENET_MACCR_MCRS_MASK) + +#define ENET_MACCR_RDIS_SHIFT (13) +#define ENET_MACCR_RDIS_MASK (0x01U << ENET_MACCR_RDIS_SHIFT) +#define ENET_MACCR_RDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACCR_RDIS_SHIFT)) & ENET_MACCR_RDIS_MASK) + +#define ENET_MACCR_LM_SHIFT (12) +#define ENET_MACCR_LM_MASK (0x01U << ENET_MACCR_LM_SHIFT) +#define ENET_MACCR_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACCR_LM_SHIFT)) & ENET_MACCR_LM_MASK) + +#define ENET_MACCR_DM_SHIFT (11) +#define ENET_MACCR_DM_MASK (0x01U << ENET_MACCR_DM_SHIFT) +#define ENET_MACCR_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACCR_DM_SHIFT)) & ENET_MACCR_DM_MASK) + +#define ENET_MACCR_IPCO_SHIFT (10) +#define ENET_MACCR_IPCO_MASK (0x01U << ENET_MACCR_IPCO_SHIFT) +#define ENET_MACCR_IPCO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACCR_IPCO_SHIFT)) & ENET_MACCR_IPCO_MASK) + +#define ENET_MACCR_RETY_SHIFT (9) +#define ENET_MACCR_RETY_MASK (0x01U << ENET_MACCR_RETY_SHIFT) +#define ENET_MACCR_RETY(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACCR_RETY_SHIFT)) & ENET_MACCR_RETY_MASK) + +#define ENET_MACCR_APCS_SHIFT (7) +#define ENET_MACCR_APCS_MASK (0x01U << ENET_MACCR_APCS_SHIFT) +#define ENET_MACCR_APCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACCR_APCS_SHIFT)) & ENET_MACCR_APCS_MASK) + +#define ENET_MACCR_BL_SHIFT (5) +#define ENET_MACCR_BL_MASK (0x3U << ENET_MACCR_BL_SHIFT) +#define ENET_MACCR_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACCR_BL_SHIFT)) & ENET_MACCR_BL_MASK) + +#define ENET_MACCR_DLYC_SHIFT (4) +#define ENET_MACCR_DLYC_MASK (0x01U << ENET_MACCR_DLYC_SHIFT) +#define ENET_MACCR_DLYC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACCR_DLYC_SHIFT)) & ENET_MACCR_DLYC_MASK) + +#define ENET_MACCR_TE_SHIFT (3) +#define ENET_MACCR_TE_MASK (0x01U << ENET_MACCR_TE_SHIFT) +#define ENET_MACCR_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACCR_TE_SHIFT)) & ENET_MACCR_TE_MASK) + +#define ENET_MACCR_RE_SHIFT (2) +#define ENET_MACCR_RE_MASK (0x01U << ENET_MACCR_RE_SHIFT) +#define ENET_MACCR_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACCR_RE_SHIFT)) & ENET_MACCR_RE_MASK) + +/*! + * @brief ENET_MACSR Register Bit Definition + */ + +#define ENET_MACSR_TXFF_SHIFT (25) +#define ENET_MACSR_TXFF_MASK (0x01U << ENET_MACSR_TXFF_SHIFT) +#define ENET_MACSR_TXFF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSR_TXFF_SHIFT)) & ENET_MACSR_TXFF_MASK) + +#define ENET_MACSR_TXFNE_SHIFT (24) +#define ENET_MACSR_TXFNE_MASK (0x01U << ENET_MACSR_TXFNE_SHIFT) +#define ENET_MACSR_TXFNE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSR_TXFNE_SHIFT)) & ENET_MACSR_TXFNE_MASK) + +#define ENET_MACSR_TXFWA_SHIFT (22) +#define ENET_MACSR_TXFWA_MASK (0x01U << ENET_MACSR_TXFWA_SHIFT) +#define ENET_MACSR_TXFWA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSR_TXFWA_SHIFT)) & ENET_MACSR_TXFWA_MASK) + +#define ENET_MACSR_TXFRS_SHIFT (20) +#define ENET_MACSR_TXFRS_MASK (0x3U << ENET_MACSR_TXFRS_SHIFT) +#define ENET_MACSR_TXFRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSR_TXFRS_SHIFT)) & ENET_MACSR_TXFRS_MASK) + +#define ENET_MACSR_MTP_SHIFT (19) +#define ENET_MACSR_MTP_MASK (0x01U << ENET_MACSR_MTP_SHIFT) +#define ENET_MACSR_MTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSR_MTP_SHIFT)) & ENET_MACSR_MTP_MASK) + +#define ENET_MACSR_MTS_SHIFT (17) +#define ENET_MACSR_MTS_MASK (0x3U << ENET_MACSR_MTS_SHIFT) +#define ENET_MACSR_MTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSR_MTS_SHIFT)) & ENET_MACSR_MTS_MASK) + +#define ENET_MACSR_MTE_SHIFT (16) +#define ENET_MACSR_MTE_MASK (0x01U << ENET_MACSR_MTE_SHIFT) +#define ENET_MACSR_MTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSR_MTE_SHIFT)) & ENET_MACSR_MTE_MASK) + +#define ENET_MACSR_RXFL_SHIFT (8) +#define ENET_MACSR_RXFL_MASK (0x3U << ENET_MACSR_RXFL_SHIFT) +#define ENET_MACSR_RXFL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSR_RXFL_SHIFT)) & ENET_MACSR_RXFL_MASK) + +#define ENET_MACSR_RXFRS_SHIFT (5) +#define ENET_MACSR_RXFRS_MASK (0x3U << ENET_MACSR_RXFRS_SHIFT) +#define ENET_MACSR_RXFRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSR_RXFRS_SHIFT)) & ENET_MACSR_RXFRS_MASK) + +#define ENET_MACSR_RXFWA_SHIFT (4) +#define ENET_MACSR_RXFWA_MASK (0x01U << ENET_MACSR_RXFWA_SHIFT) +#define ENET_MACSR_RXFWA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSR_RXFWA_SHIFT)) & ENET_MACSR_RXFWA_MASK) + +#define ENET_MACSR_MRS_SHIFT (1) +#define ENET_MACSR_MRS_MASK (0x3U << ENET_MACSR_MRS_SHIFT) +#define ENET_MACSR_MRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSR_MRS_SHIFT)) & ENET_MACSR_MRS_MASK) + +#define ENET_MACSR_MRE_SHIFT (0) +#define ENET_MACSR_MRE_MASK (0x01U << ENET_MACSR_MRE_SHIFT) +#define ENET_MACSR_MRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACSR_MRE_SHIFT)) & ENET_MACSR_MRE_MASK) + +/*! + * @brief ENET_MACFCR Register Bit Definition + */ + +#define ENET_MACFCR_PSET_SHIFT (16) +#define ENET_MACFCR_PSET_MASK (0xFFFFU << ENET_MACFCR_PSET_SHIFT) +#define ENET_MACFCR_PSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACFCR_PSET_SHIFT)) & ENET_MACFCR_PSET_MASK) + +#define ENET_MACFCR_DZQP_SHIFT (7) +#define ENET_MACFCR_DZQP_MASK (0x01U << ENET_MACFCR_DZQP_SHIFT) +#define ENET_MACFCR_DZQP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACFCR_DZQP_SHIFT)) & ENET_MACFCR_DZQP_MASK) + +#define ENET_MACFCR_PLT_SHIFT (4) +#define ENET_MACFCR_PLT_MASK (0x3U << ENET_MACFCR_PLT_SHIFT) +#define ENET_MACFCR_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACFCR_PLT_SHIFT)) & ENET_MACFCR_PLT_MASK) + +#define ENET_MACFCR_UPF_SHIFT (3) +#define ENET_MACFCR_UPF_MASK (0x01U << ENET_MACFCR_UPF_SHIFT) +#define ENET_MACFCR_UPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACFCR_UPF_SHIFT)) & ENET_MACFCR_UPF_MASK) + +#define ENET_MACFCR_FRE_SHIFT (2) +#define ENET_MACFCR_FRE_MASK (0x01U << ENET_MACFCR_FRE_SHIFT) +#define ENET_MACFCR_FRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACFCR_FRE_SHIFT)) & ENET_MACFCR_FRE_MASK) + +#define ENET_MACFCR_FTE_SHIFT (1) +#define ENET_MACFCR_FTE_MASK (0x01U << ENET_MACFCR_FTE_SHIFT) +#define ENET_MACFCR_FTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACFCR_FTE_SHIFT)) & ENET_MACFCR_FTE_MASK) + +#define ENET_MACFCR_FCBBPA_SHIFT (0) +#define ENET_MACFCR_FCBBPA_MASK (0x01U << ENET_MACFCR_FCBBPA_SHIFT) +#define ENET_MACFCR_FCBBPA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACFCR_FCBBPA_SHIFT)) & ENET_MACFCR_FCBBPA_MASK) + +/*! + * @brief ENET_MACISR Register Bit Definition + */ + +#define ENET_MACISR_PTPIS_SHIFT (9) +#define ENET_MACISR_PTPIS_MASK (0x01U << ENET_MACISR_PTPIS_SHIFT) +#define ENET_MACISR_PTPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACISR_PTPIS_SHIFT)) & ENET_MACISR_PTPIS_MASK) + +#define ENET_MACISR_MMCTXIS_SHIFT (6) +#define ENET_MACISR_MMCTXIS_MASK (0x01U << ENET_MACISR_MMCTXIS_SHIFT) +#define ENET_MACISR_MMCTXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACISR_MMCTXIS_SHIFT)) & ENET_MACISR_MMCTXIS_MASK) + +#define ENET_MACISR_MMCRXIS_SHIFT (5) +#define ENET_MACISR_MMCRXIS_MASK (0x01U << ENET_MACISR_MMCRXIS_SHIFT) +#define ENET_MACISR_MMCRXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACISR_MMCRXIS_SHIFT)) & ENET_MACISR_MMCRXIS_MASK) + +#define ENET_MACISR_MMCIS_SHIFT (4) +#define ENET_MACISR_MMCIS_MASK (0x01U << ENET_MACISR_MMCIS_SHIFT) +#define ENET_MACISR_MMCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACISR_MMCIS_SHIFT)) & ENET_MACISR_MMCIS_MASK) + +#define ENET_MACISR_PMTIS_SHIFT (3) +#define ENET_MACISR_PMTIS_MASK (0x01U << ENET_MACISR_PMTIS_SHIFT) +#define ENET_MACISR_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACISR_PMTIS_SHIFT)) & ENET_MACISR_PMTIS_MASK) + +/*! + * @brief ENET_MACIMR Register Bit Definition + */ + +#define ENET_MACIMR_PTPIM_SHIFT (9) +#define ENET_MACIMR_PTPIM_MASK (0x01U << ENET_MACIMR_PTPIM_SHIFT) +#define ENET_MACIMR_PTPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACIMR_PTPIM_SHIFT)) & ENET_MACIMR_PTPIM_MASK) + +#define ENET_MACIMR_PMTIM_SHIFT (3) +#define ENET_MACIMR_PMTIM_MASK (0x01U << ENET_MACIMR_PMTIM_SHIFT) +#define ENET_MACIMR_PMTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACIMR_PMTIM_SHIFT)) & ENET_MACIMR_PMTIM_MASK) + +/*! + * @brief ENET_MACAFR Register Bit Definition + */ + +#define ENET_MACAFR_RALL_SHIFT (31) +#define ENET_MACAFR_RALL_MASK (0x01U << ENET_MACAFR_RALL_SHIFT) +#define ENET_MACAFR_RALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACAFR_RALL_SHIFT)) & ENET_MACAFR_RALL_MASK) + +#define ENET_MACAFR_DNTU_SHIFT (21) +#define ENET_MACAFR_DNTU_MASK (0x01U << ENET_MACAFR_DNTU_SHIFT) +#define ENET_MACAFR_DNTU(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACAFR_DNTU_SHIFT)) & ENET_MACAFR_DNTU_MASK) + +#define ENET_MACAFR_VLTF_SHIFT (16) +#define ENET_MACAFR_VLTF_MASK (0x01U << ENET_MACAFR_VLTF_SHIFT) +#define ENET_MACAFR_VLTF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACAFR_VLTF_SHIFT)) & ENET_MACAFR_VLTF_MASK) + +#define ENET_MACAFR_HPF_SHIFT (10) +#define ENET_MACAFR_HPF_MASK (0x01U << ENET_MACAFR_HPF_SHIFT) +#define ENET_MACAFR_HPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACAFR_HPF_SHIFT)) & ENET_MACAFR_HPF_MASK) + +#define ENET_MACAFR_SAF_SHIFT (9) +#define ENET_MACAFR_SAF_MASK (0x01U << ENET_MACAFR_SAF_SHIFT) +#define ENET_MACAFR_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACAFR_SAF_SHIFT)) & ENET_MACAFR_SAF_MASK) + +#define ENET_MACAFR_SAIF_SHIFT (8) +#define ENET_MACAFR_SAIF_MASK (0x01U << ENET_MACAFR_SAIF_SHIFT) +#define ENET_MACAFR_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACAFR_SAIF_SHIFT)) & ENET_MACAFR_SAIF_MASK) + +#define ENET_MACAFR_PCF_SHIFT (6) +#define ENET_MACAFR_PCF_MASK (0x3U << ENET_MACAFR_PCF_SHIFT) +#define ENET_MACAFR_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACAFR_PCF_SHIFT)) & ENET_MACAFR_PCF_MASK) + +#define ENET_MACAFR_BCF_SHIFT (5) +#define ENET_MACAFR_BCF_MASK (0x01U << ENET_MACAFR_BCF_SHIFT) +#define ENET_MACAFR_BCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACAFR_BCF_SHIFT)) & ENET_MACAFR_BCF_MASK) + +#define ENET_MACAFR_MCF_SHIFT (4) +#define ENET_MACAFR_MCF_MASK (0x01U << ENET_MACAFR_MCF_SHIFT) +#define ENET_MACAFR_MCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACAFR_MCF_SHIFT)) & ENET_MACAFR_MCF_MASK) + +#define ENET_MACAFR_DAIF_SHIFT (3) +#define ENET_MACAFR_DAIF_MASK (0x01U << ENET_MACAFR_DAIF_SHIFT) +#define ENET_MACAFR_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACAFR_DAIF_SHIFT)) & ENET_MACAFR_DAIF_MASK) + +#define ENET_MACAFR_HM_SHIFT (2) +#define ENET_MACAFR_HM_MASK (0x01U << ENET_MACAFR_HM_SHIFT) +#define ENET_MACAFR_HM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACAFR_HM_SHIFT)) & ENET_MACAFR_HM_MASK) + +#define ENET_MACAFR_HU_SHIFT (1) +#define ENET_MACAFR_HU_MASK (0x01U << ENET_MACAFR_HU_SHIFT) +#define ENET_MACAFR_HU(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACAFR_HU_SHIFT)) & ENET_MACAFR_HU_MASK) + +#define ENET_MACAFR_PM_SHIFT (0) +#define ENET_MACAFR_PM_MASK (0x01U << ENET_MACAFR_PM_SHIFT) +#define ENET_MACAFR_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACAFR_PM_SHIFT)) & ENET_MACAFR_PM_MASK) + +/*! + * @brief ENET_MACAHR Register Bit Definition + */ + +#define ENET_MACAHR_ADDE_SHIFT (31) +#define ENET_MACAHR_ADDE_MASK (0x01U << ENET_MACAHR_ADDE_SHIFT) +#define ENET_MACAHR_ADDE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACAHR_ADDE_SHIFT)) & ENET_MACAHR_ADDE_MASK) + +#define ENET_MACAHR_SELE_SHIFT (30) +#define ENET_MACAHR_SELE_MASK (0x01U << ENET_MACAHR_SELE_SHIFT) +#define ENET_MACAHR_SELE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACAHR_SELE_SHIFT)) & ENET_MACAHR_SELE_MASK) + +#define ENET_MACAHR_MBYTEC_SHIFT (24) +#define ENET_MACAHR_MBYTEC_MASK (0x3FU << ENET_MACAHR_MBYTEC_SHIFT) +#define ENET_MACAHR_MBYTEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACAHR_MBYTEC_SHIFT)) & ENET_MACAHR_MBYTEC_MASK) + +#define ENET_MACAHR_MACADDH_SHIFT (0) +#define ENET_MACAHR_MACADDH_MASK (0xFFFFU << ENET_MACAHR_MACADDH_SHIFT) +#define ENET_MACAHR_MACADDH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACAHR_MACADDH_SHIFT)) & ENET_MACAHR_MACADDH_MASK) + +/*! + * @brief ENET_MACALR0 Register Bit Definition + */ + +#define ENET_MACALR0_MACADDL_SHIFT (0) +#define ENET_MACALR0_MACADDL_MASK (0xFFFFFFFFU << ENET_MACALR0_MACADDL_SHIFT) +#define ENET_MACALR0_MACADDL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACALR0_MACADDL_SHIFT)) & ENET_MACALR0_MACADDL_MASK) + +/*! + * @brief ENET_MACHTHR Register Bit Definition + */ + +#define ENET_MACHTHR_MACHTABH_SHIFT (0) +#define ENET_MACHTHR_MACHTABH_MASK (0xFFFFFFFFU << ENET_MACHTHR_MACHTABH_SHIFT) +#define ENET_MACHTHR_MACHTABH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACHTHR_MACHTABH_SHIFT)) & ENET_MACHTHR_MACHTABH_MASK) + +/*! + * @brief ENET_MACHTLR Register Bit Definition + */ + +#define ENET_MACHTLR_MACHTABL_SHIFT (0) +#define ENET_MACHTLR_MACHTABL_MASK (0xFFFFFFFFU << ENET_MACHTLR_MACHTABL_SHIFT) +#define ENET_MACHTLR_MACHTABL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACHTLR_MACHTABL_SHIFT)) & ENET_MACHTLR_MACHTABL_MASK) + +/*! + * @brief ENET_MACVLTTR Register Bit Definition + */ + +#define ENET_MACVLTTR_VLANS_SHIFT (18) +#define ENET_MACVLTTR_VLANS_MASK (0x01U << ENET_MACVLTTR_VLANS_SHIFT) +#define ENET_MACVLTTR_VLANS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACVLTTR_VLANS_SHIFT)) & ENET_MACVLTTR_VLANS_MASK) + +#define ENET_MACVLTTR_VLANC_SHIFT (16) +#define ENET_MACVLTTR_VLANC_MASK (0x3U << ENET_MACVLTTR_VLANC_SHIFT) +#define ENET_MACVLTTR_VLANC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACVLTTR_VLANC_SHIFT)) & ENET_MACVLTTR_VLANC_MASK) + +#define ENET_MACVLTTR_VLANV_SHIFT (0) +#define ENET_MACVLTTR_VLANV_MASK (0xFFFFU << ENET_MACVLTTR_VLANV_SHIFT) +#define ENET_MACVLTTR_VLANV(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACVLTTR_VLANV_SHIFT)) & ENET_MACVLTTR_VLANV_MASK) + +/*! + * @brief ENET_MACVLTRR Register Bit Definition + */ + +#define ENET_MACVLTRR_VTHM_SHIFT (19) +#define ENET_MACVLTRR_VTHM_MASK (0x01U << ENET_MACVLTRR_VTHM_SHIFT) +#define ENET_MACVLTRR_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACVLTRR_VTHM_SHIFT)) & ENET_MACVLTRR_VTHM_MASK) + +#define ENET_MACVLTRR_VTIM_SHIFT (17) +#define ENET_MACVLTRR_VTIM_MASK (0x01U << ENET_MACVLTRR_VTIM_SHIFT) +#define ENET_MACVLTRR_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACVLTRR_VTIM_SHIFT)) & ENET_MACVLTRR_VTIM_MASK) + +#define ENET_MACVLTRR_VTSEL_SHIFT (16) +#define ENET_MACVLTRR_VTSEL_MASK (0x01U << ENET_MACVLTRR_VTSEL_SHIFT) +#define ENET_MACVLTRR_VTSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACVLTRR_VTSEL_SHIFT)) & ENET_MACVLTRR_VTSEL_MASK) + +#define ENET_MACVLTRR_VLFLT_SHIFT (0) +#define ENET_MACVLTRR_VLFLT_MASK (0xFFFFU << ENET_MACVLTRR_VLFLT_SHIFT) +#define ENET_MACVLTRR_VLFLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACVLTRR_VLFLT_SHIFT)) & ENET_MACVLTRR_VLFLT_MASK) + +/*! + * @brief ENET_MACVLHTR Register Bit Definition + */ + +#define ENET_MACVLHTR_VLHTAB_SHIFT (0) +#define ENET_MACVLHTR_VLHTAB_MASK (0xFFFFU << ENET_MACVLHTR_VLHTAB_SHIFT) +#define ENET_MACVLHTR_VLHTAB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MACVLHTR_VLHTAB_SHIFT)) & ENET_MACVLHTR_VLHTAB_MASK) + +/*! + * @brief ENET_DMAMDR Register Bit Definition + */ + +#define ENET_DMAMDR_DTCOE_SHIFT (26) +#define ENET_DMAMDR_DTCOE_MASK (0x01U << ENET_DMAMDR_DTCOE_SHIFT) +#define ENET_DMAMDR_DTCOE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAMDR_DTCOE_SHIFT)) & ENET_DMAMDR_DTCOE_MASK) + +#define ENET_DMAMDR_RSF_SHIFT (25) +#define ENET_DMAMDR_RSF_MASK (0x01U << ENET_DMAMDR_RSF_SHIFT) +#define ENET_DMAMDR_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAMDR_RSF_SHIFT)) & ENET_DMAMDR_RSF_MASK) + +#define ENET_DMAMDR_DFRF_SHIFT (24) +#define ENET_DMAMDR_DFRF_MASK (0x01U << ENET_DMAMDR_DFRF_SHIFT) +#define ENET_DMAMDR_DFRF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAMDR_DFRF_SHIFT)) & ENET_DMAMDR_DFRF_MASK) + +#define ENET_DMAMDR_TSF_SHIFT (21) +#define ENET_DMAMDR_TSF_MASK (0x01U << ENET_DMAMDR_TSF_SHIFT) +#define ENET_DMAMDR_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAMDR_TSF_SHIFT)) & ENET_DMAMDR_TSF_MASK) + +#define ENET_DMAMDR_FTF_SHIFT (20) +#define ENET_DMAMDR_FTF_MASK (0x01U << ENET_DMAMDR_FTF_SHIFT) +#define ENET_DMAMDR_FTF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAMDR_FTF_SHIFT)) & ENET_DMAMDR_FTF_MASK) + +#define ENET_DMAMDR_TTC_SHIFT (14) +#define ENET_DMAMDR_TTC_MASK (0x7U << ENET_DMAMDR_TTC_SHIFT) +#define ENET_DMAMDR_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAMDR_TTC_SHIFT)) & ENET_DMAMDR_TTC_MASK) + +#define ENET_DMAMDR_STT_SHIFT (13) +#define ENET_DMAMDR_STT_MASK (0x01U << ENET_DMAMDR_STT_SHIFT) +#define ENET_DMAMDR_STT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAMDR_STT_SHIFT)) & ENET_DMAMDR_STT_MASK) + +#define ENET_DMAMDR_FEF_SHIFT (7) +#define ENET_DMAMDR_FEF_MASK (0x01U << ENET_DMAMDR_FEF_SHIFT) +#define ENET_DMAMDR_FEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAMDR_FEF_SHIFT)) & ENET_DMAMDR_FEF_MASK) + +#define ENET_DMAMDR_FUF_SHIFT (6) +#define ENET_DMAMDR_FUF_MASK (0x01U << ENET_DMAMDR_FUF_SHIFT) +#define ENET_DMAMDR_FUF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAMDR_FUF_SHIFT)) & ENET_DMAMDR_FUF_MASK) + +#define ENET_DMAMDR_DGF_SHIFT (5) +#define ENET_DMAMDR_DGF_MASK (0x01U << ENET_DMAMDR_DGF_SHIFT) +#define ENET_DMAMDR_DGF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAMDR_DGF_SHIFT)) & ENET_DMAMDR_DGF_MASK) + +#define ENET_DMAMDR_RTC_SHIFT (3) +#define ENET_DMAMDR_RTC_MASK (0x3U << ENET_DMAMDR_RTC_SHIFT) +#define ENET_DMAMDR_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAMDR_RTC_SHIFT)) & ENET_DMAMDR_RTC_MASK) + +#define ENET_DMAMDR_OSF_SHIFT (2) +#define ENET_DMAMDR_OSF_MASK (0x01U << ENET_DMAMDR_OSF_SHIFT) +#define ENET_DMAMDR_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAMDR_OSF_SHIFT)) & ENET_DMAMDR_OSF_MASK) + +#define ENET_DMAMDR_STR_SHIFT (1) +#define ENET_DMAMDR_STR_MASK (0x01U << ENET_DMAMDR_STR_SHIFT) +#define ENET_DMAMDR_STR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAMDR_STR_SHIFT)) & ENET_DMAMDR_STR_MASK) + +/*! + * @brief ENET_DMABSR Register Bit Definition + */ + +#define ENET_DMABSR_TXPR_SHIFT (27) +#define ENET_DMABSR_TXPR_MASK (0x01U << ENET_DMABSR_TXPR_SHIFT) +#define ENET_DMABSR_TXPR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMABSR_TXPR_SHIFT)) & ENET_DMABSR_TXPR_MASK) + +#define ENET_DMABSR_MBST_SHIFT (26) +#define ENET_DMABSR_MBST_MASK (0x01U << ENET_DMABSR_MBST_SHIFT) +#define ENET_DMABSR_MBST(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMABSR_MBST_SHIFT)) & ENET_DMABSR_MBST_MASK) + +#define ENET_DMABSR_AAL_SHIFT (25) +#define ENET_DMABSR_AAL_MASK (0x01U << ENET_DMABSR_AAL_SHIFT) +#define ENET_DMABSR_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMABSR_AAL_SHIFT)) & ENET_DMABSR_AAL_MASK) + +#define ENET_DMABSR_MPBL_SHIFT (24) +#define ENET_DMABSR_MPBL_MASK (0x01U << ENET_DMABSR_MPBL_SHIFT) +#define ENET_DMABSR_MPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMABSR_MPBL_SHIFT)) & ENET_DMABSR_MPBL_MASK) + +#define ENET_DMABSR_SPBL_SHIFT (23) +#define ENET_DMABSR_SPBL_MASK (0x01U << ENET_DMABSR_SPBL_SHIFT) +#define ENET_DMABSR_SPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMABSR_SPBL_SHIFT)) & ENET_DMABSR_SPBL_MASK) + +#define ENET_DMABSR_RPBL_SHIFT (17) +#define ENET_DMABSR_RPBL_MASK (0x3FU << ENET_DMABSR_RPBL_SHIFT) +#define ENET_DMABSR_RPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMABSR_RPBL_SHIFT)) & ENET_DMABSR_RPBL_MASK) + +#define ENET_DMABSR_FBST_SHIFT (16) +#define ENET_DMABSR_FBST_MASK (0x01U << ENET_DMABSR_FBST_SHIFT) +#define ENET_DMABSR_FBST(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMABSR_FBST_SHIFT)) & ENET_DMABSR_FBST_MASK) + +#define ENET_DMABSR_FTPR_SHIFT (14) +#define ENET_DMABSR_FTPR_MASK (0x3U << ENET_DMABSR_FTPR_SHIFT) +#define ENET_DMABSR_FTPR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMABSR_FTPR_SHIFT)) & ENET_DMABSR_FTPR_MASK) + +#define ENET_DMABSR_TPBL_SHIFT (8) +#define ENET_DMABSR_TPBL_MASK (0x3FU << ENET_DMABSR_TPBL_SHIFT) +#define ENET_DMABSR_TPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMABSR_TPBL_SHIFT)) & ENET_DMABSR_TPBL_MASK) + +#define ENET_DMABSR_DSEN_SHIFT (7) +#define ENET_DMABSR_DSEN_MASK (0x01U << ENET_DMABSR_DSEN_SHIFT) +#define ENET_DMABSR_DSEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMABSR_DSEN_SHIFT)) & ENET_DMABSR_DSEN_MASK) + +#define ENET_DMABSR_DSL_SHIFT (2) +#define ENET_DMABSR_DSL_MASK (0x1FU << ENET_DMABSR_DSL_SHIFT) +#define ENET_DMABSR_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMABSR_DSL_SHIFT)) & ENET_DMABSR_DSL_MASK) + +#define ENET_DMABSR_DMAA_SHIFT (1) +#define ENET_DMABSR_DMAA_MASK (0x01U << ENET_DMABSR_DMAA_SHIFT) +#define ENET_DMABSR_DMAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMABSR_DMAA_SHIFT)) & ENET_DMABSR_DMAA_MASK) + +#define ENET_DMABSR_SR_SHIFT (0) +#define ENET_DMABSR_SR_MASK (0x01U << ENET_DMABSR_SR_SHIFT) +#define ENET_DMABSR_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMABSR_SR_SHIFT)) & ENET_DMABSR_SR_MASK) + +/*! + * @brief ENET_DMASR Register Bit Definition + */ + +#define ENET_DMASR_PTPS_SHIFT (29) +#define ENET_DMASR_PTPS_MASK (0x01U << ENET_DMASR_PTPS_SHIFT) +#define ENET_DMASR_PTPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_PTPS_SHIFT)) & ENET_DMASR_PTPS_MASK) + +#define ENET_DMASR_PMTS_SHIFT (28) +#define ENET_DMASR_PMTS_MASK (0x01U << ENET_DMASR_PMTS_SHIFT) +#define ENET_DMASR_PMTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_PMTS_SHIFT)) & ENET_DMASR_PMTS_MASK) + +#define ENET_DMASR_MMCS_SHIFT (27) +#define ENET_DMASR_MMCS_MASK (0x01U << ENET_DMASR_MMCS_SHIFT) +#define ENET_DMASR_MMCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_MMCS_SHIFT)) & ENET_DMASR_MMCS_MASK) + +#define ENET_DMASR_EBUS_SHIFT (23) +#define ENET_DMASR_EBUS_MASK (0x7U << ENET_DMASR_EBUS_SHIFT) +#define ENET_DMASR_EBUS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_EBUS_SHIFT)) & ENET_DMASR_EBUS_MASK) + +#define ENET_DMASR_TPS_SHIFT (20) +#define ENET_DMASR_TPS_MASK (0x7U << ENET_DMASR_TPS_SHIFT) +#define ENET_DMASR_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_TPS_SHIFT)) & ENET_DMASR_TPS_MASK) + +#define ENET_DMASR_RPS_SHIFT (17) +#define ENET_DMASR_RPS_MASK (0x7U << ENET_DMASR_RPS_SHIFT) +#define ENET_DMASR_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_RPS_SHIFT)) & ENET_DMASR_RPS_MASK) + +#define ENET_DMASR_NIS_SHIFT (16) +#define ENET_DMASR_NIS_MASK (0x01U << ENET_DMASR_NIS_SHIFT) +#define ENET_DMASR_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_NIS_SHIFT)) & ENET_DMASR_NIS_MASK) + +#define ENET_DMASR_AIS_SHIFT (15) +#define ENET_DMASR_AIS_MASK (0x01U << ENET_DMASR_AIS_SHIFT) +#define ENET_DMASR_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_AIS_SHIFT)) & ENET_DMASR_AIS_MASK) + +#define ENET_DMASR_ERS_SHIFT (14) +#define ENET_DMASR_ERS_MASK (0x01U << ENET_DMASR_ERS_SHIFT) +#define ENET_DMASR_ERS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_ERS_SHIFT)) & ENET_DMASR_ERS_MASK) + +#define ENET_DMASR_FBS_SHIFT (13) +#define ENET_DMASR_FBS_MASK (0x01U << ENET_DMASR_FBS_SHIFT) +#define ENET_DMASR_FBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_FBS_SHIFT)) & ENET_DMASR_FBS_MASK) + +#define ENET_DMASR_ETS_SHIFT (10) +#define ENET_DMASR_ETS_MASK (0x01U << ENET_DMASR_ETS_SHIFT) +#define ENET_DMASR_ETS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_ETS_SHIFT)) & ENET_DMASR_ETS_MASK) + +#define ENET_DMASR_RWS_SHIFT (9) +#define ENET_DMASR_RWS_MASK (0x01U << ENET_DMASR_RWS_SHIFT) +#define ENET_DMASR_RWS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_RWS_SHIFT)) & ENET_DMASR_RWS_MASK) + +#define ENET_DMASR_RSS_SHIFT (8) +#define ENET_DMASR_RSS_MASK (0x01U << ENET_DMASR_RSS_SHIFT) +#define ENET_DMASR_RSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_RSS_SHIFT)) & ENET_DMASR_RSS_MASK) + +#define ENET_DMASR_RUS_SHIFT (7) +#define ENET_DMASR_RUS_MASK (0x01U << ENET_DMASR_RUS_SHIFT) +#define ENET_DMASR_RUS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_RUS_SHIFT)) & ENET_DMASR_RUS_MASK) + +#define ENET_DMASR_RCS_SHIFT (6) +#define ENET_DMASR_RCS_MASK (0x01U << ENET_DMASR_RCS_SHIFT) +#define ENET_DMASR_RCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_RCS_SHIFT)) & ENET_DMASR_RCS_MASK) + +#define ENET_DMASR_UNS_SHIFT (5) +#define ENET_DMASR_UNS_MASK (0x01U << ENET_DMASR_UNS_SHIFT) +#define ENET_DMASR_UNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_UNS_SHIFT)) & ENET_DMASR_UNS_MASK) + +#define ENET_DMASR_OVS_SHIFT (4) +#define ENET_DMASR_OVS_MASK (0x01U << ENET_DMASR_OVS_SHIFT) +#define ENET_DMASR_OVS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_OVS_SHIFT)) & ENET_DMASR_OVS_MASK) + +#define ENET_DMASR_TJS_SHIFT (3) +#define ENET_DMASR_TJS_MASK (0x01U << ENET_DMASR_TJS_SHIFT) +#define ENET_DMASR_TJS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_TJS_SHIFT)) & ENET_DMASR_TJS_MASK) + +#define ENET_DMASR_TUS_SHIFT (2) +#define ENET_DMASR_TUS_MASK (0x01U << ENET_DMASR_TUS_SHIFT) +#define ENET_DMASR_TUS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_TUS_SHIFT)) & ENET_DMASR_TUS_MASK) + +#define ENET_DMASR_TSS_SHIFT (1) +#define ENET_DMASR_TSS_MASK (0x01U << ENET_DMASR_TSS_SHIFT) +#define ENET_DMASR_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_TSS_SHIFT)) & ENET_DMASR_TSS_MASK) + +#define ENET_DMASR_TCS_SHIFT (0) +#define ENET_DMASR_TCS_MASK (0x01U << ENET_DMASR_TCS_SHIFT) +#define ENET_DMASR_TCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMASR_TCS_SHIFT)) & ENET_DMASR_TCS_MASK) + +/*! + * @brief ENET_DMAIR Register Bit Definition + */ + +#define ENET_DMAIR_NIE_SHIFT (16) +#define ENET_DMAIR_NIE_MASK (0x01U << ENET_DMAIR_NIE_SHIFT) +#define ENET_DMAIR_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAIR_NIE_SHIFT)) & ENET_DMAIR_NIE_MASK) + +#define ENET_DMAIR_AIE_SHIFT (15) +#define ENET_DMAIR_AIE_MASK (0x01U << ENET_DMAIR_AIE_SHIFT) +#define ENET_DMAIR_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAIR_AIE_SHIFT)) & ENET_DMAIR_AIE_MASK) + +#define ENET_DMAIR_ERE_SHIFT (14) +#define ENET_DMAIR_ERE_MASK (0x01U << ENET_DMAIR_ERE_SHIFT) +#define ENET_DMAIR_ERE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAIR_ERE_SHIFT)) & ENET_DMAIR_ERE_MASK) + +#define ENET_DMAIR_FBE_SHIFT (13) +#define ENET_DMAIR_FBE_MASK (0x01U << ENET_DMAIR_FBE_SHIFT) +#define ENET_DMAIR_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAIR_FBE_SHIFT)) & ENET_DMAIR_FBE_MASK) + +#define ENET_DMAIR_ETE_SHIFT (10) +#define ENET_DMAIR_ETE_MASK (0x01U << ENET_DMAIR_ETE_SHIFT) +#define ENET_DMAIR_ETE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAIR_ETE_SHIFT)) & ENET_DMAIR_ETE_MASK) + +#define ENET_DMAIR_RWE_SHIFT (9) +#define ENET_DMAIR_RWE_MASK (0x01U << ENET_DMAIR_RWE_SHIFT) +#define ENET_DMAIR_RWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAIR_RWE_SHIFT)) & ENET_DMAIR_RWE_MASK) + +#define ENET_DMAIR_RSE_SHIFT (8) +#define ENET_DMAIR_RSE_MASK (0x01U << ENET_DMAIR_RSE_SHIFT) +#define ENET_DMAIR_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAIR_RSE_SHIFT)) & ENET_DMAIR_RSE_MASK) + +#define ENET_DMAIR_RUE_SHIFT (7) +#define ENET_DMAIR_RUE_MASK (0x01U << ENET_DMAIR_RUE_SHIFT) +#define ENET_DMAIR_RUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAIR_RUE_SHIFT)) & ENET_DMAIR_RUE_MASK) + +#define ENET_DMAIR_RCE_SHIFT (6) +#define ENET_DMAIR_RCE_MASK (0x01U << ENET_DMAIR_RCE_SHIFT) +#define ENET_DMAIR_RCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAIR_RCE_SHIFT)) & ENET_DMAIR_RCE_MASK) + +#define ENET_DMAIR_UNE_SHIFT (5) +#define ENET_DMAIR_UNE_MASK (0x01U << ENET_DMAIR_UNE_SHIFT) +#define ENET_DMAIR_UNE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAIR_UNE_SHIFT)) & ENET_DMAIR_UNE_MASK) + +#define ENET_DMAIR_OVE_SHIFT (4) +#define ENET_DMAIR_OVE_MASK (0x01U << ENET_DMAIR_OVE_SHIFT) +#define ENET_DMAIR_OVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAIR_OVE_SHIFT)) & ENET_DMAIR_OVE_MASK) + +#define ENET_DMAIR_TJE_SHIFT (3) +#define ENET_DMAIR_TJE_MASK (0x01U << ENET_DMAIR_TJE_SHIFT) +#define ENET_DMAIR_TJE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAIR_TJE_SHIFT)) & ENET_DMAIR_TJE_MASK) + +#define ENET_DMAIR_TUE_SHIFT (2) +#define ENET_DMAIR_TUE_MASK (0x01U << ENET_DMAIR_TUE_SHIFT) +#define ENET_DMAIR_TUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAIR_TUE_SHIFT)) & ENET_DMAIR_TUE_MASK) + +#define ENET_DMAIR_TSE_SHIFT (1) +#define ENET_DMAIR_TSE_MASK (0x01U << ENET_DMAIR_TSE_SHIFT) +#define ENET_DMAIR_TSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAIR_TSE_SHIFT)) & ENET_DMAIR_TSE_MASK) + +#define ENET_DMAIR_TCE_SHIFT (0) +#define ENET_DMAIR_TCE_MASK (0x01U << ENET_DMAIR_TCE_SHIFT) +#define ENET_DMAIR_TCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAIR_TCE_SHIFT)) & ENET_DMAIR_TCE_MASK) + +/*! + * @brief ENET_DMAFLCR Register Bit Definition + */ + +#define ENET_DMAFLCR_OVFF_SHIFT (28) +#define ENET_DMAFLCR_OVFF_MASK (0x01U << ENET_DMAFLCR_OVFF_SHIFT) +#define ENET_DMAFLCR_OVFF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAFLCR_OVFF_SHIFT)) & ENET_DMAFLCR_OVFF_MASK) + +#define ENET_DMAFLCR_OVFC_SHIFT (17) +#define ENET_DMAFLCR_OVFC_MASK (0x7FFU << ENET_DMAFLCR_OVFC_SHIFT) +#define ENET_DMAFLCR_OVFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAFLCR_OVFC_SHIFT)) & ENET_DMAFLCR_OVFC_MASK) + +#define ENET_DMAFLCR_BUAF_SHIFT (16) +#define ENET_DMAFLCR_BUAF_MASK (0x01U << ENET_DMAFLCR_BUAF_SHIFT) +#define ENET_DMAFLCR_BUAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAFLCR_BUAF_SHIFT)) & ENET_DMAFLCR_BUAF_MASK) + +#define ENET_DMAFLCR_BUAC_SHIFT (0) +#define ENET_DMAFLCR_BUAC_MASK (0xFFFFU << ENET_DMAFLCR_BUAC_SHIFT) +#define ENET_DMAFLCR_BUAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAFLCR_BUAC_SHIFT)) & ENET_DMAFLCR_BUAC_MASK) + +/*! + * @brief ENET_DMAWDTR Register Bit Definition + */ + +#define ENET_DMAWDTR_RIWT_SHIFT (0) +#define ENET_DMAWDTR_RIWT_MASK (0xFFFFFFFFU << ENET_DMAWDTR_RIWT_SHIFT) +#define ENET_DMAWDTR_RIWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMAWDTR_RIWT_SHIFT)) & ENET_DMAWDTR_RIWT_MASK) + +/*! + * @brief ENET_DMARXPDR Register Bit Definition + */ + +#define ENET_DMARXPDR_RXPD_SHIFT (0) +#define ENET_DMARXPDR_RXPD_MASK (0xFFFFFFFFU << ENET_DMARXPDR_RXPD_SHIFT) +#define ENET_DMARXPDR_RXPD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMARXPDR_RXPD_SHIFT)) & ENET_DMARXPDR_RXPD_MASK) + +/*! + * @brief ENET_DMATXPDR Register Bit Definition + */ + +#define ENET_DMATXPDR_TXPD_SHIFT (0) +#define ENET_DMATXPDR_TXPD_MASK (0xFFFFFFFFU << ENET_DMATXPDR_TXPD_SHIFT) +#define ENET_DMATXPDR_TXPD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMATXPDR_TXPD_SHIFT)) & ENET_DMATXPDR_TXPD_MASK) + +/*! + * @brief ENET_DMARXDSAR Register Bit Definition + */ + +#define ENET_DMARXDSAR_RXDSA_SHIFT (0) +#define ENET_DMARXDSAR_RXDSA_MASK (0xFFFFFFFFU << ENET_DMARXDSAR_RXDSA_SHIFT) +#define ENET_DMARXDSAR_RXDSA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMARXDSAR_RXDSA_SHIFT)) & ENET_DMARXDSAR_RXDSA_MASK) + +/*! + * @brief ENET_DMATXDSAR Register Bit Definition + */ + +#define ENET_DMATXDSAR_TXDSA_SHIFT (0) +#define ENET_DMATXDSAR_TXDSA_MASK (0xFFFFFFFFU << ENET_DMATXDSAR_TXDSA_SHIFT) +#define ENET_DMATXDSAR_TXDSA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMATXDSAR_TXDSA_SHIFT)) & ENET_DMATXDSAR_TXDSA_MASK) + +/*! + * @brief ENET_DMACURRXDSAR Register Bit Definition + */ + +#define ENET_DMACURRXDSAR_CURRXDSA_SHIFT (0) +#define ENET_DMACURRXDSAR_CURRXDSA_MASK (0xFFFFFFFFU << ENET_DMACURRXDSAR_CURRXDSA_SHIFT) +#define ENET_DMACURRXDSAR_CURRXDSA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACURRXDSAR_CURRXDSA_SHIFT)) & ENET_DMACURRXDSAR_CURRXDSA_MASK) + +/*! + * @brief ENET_DMACURTXDSAR Register Bit Definition + */ + +#define ENET_DMACURTXDSAR_CURTXDSA_SHIFT (0) +#define ENET_DMACURTXDSAR_CURTXDSA_MASK (0xFFFFFFFFU << ENET_DMACURTXDSAR_CURTXDSA_SHIFT) +#define ENET_DMACURTXDSAR_CURTXDSA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACURTXDSAR_CURTXDSA_SHIFT)) & ENET_DMACURTXDSAR_CURTXDSA_MASK) + +/*! + * @brief ENET_DMACURRXBFAR Register Bit Definition + */ + +#define ENET_DMACURRXBFAR_CURRXBFA_SHIFT (0) +#define ENET_DMACURRXBFAR_CURRXBFA_MASK (0xFFFFFFFFU << ENET_DMACURRXBFAR_CURRXBFA_SHIFT) +#define ENET_DMACURRXBFAR_CURRXBFA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACURRXBFAR_CURRXBFA_SHIFT)) & ENET_DMACURRXBFAR_CURRXBFA_MASK) + +/*! + * @brief ENET_DMACURTXBFAR Register Bit Definition + */ + +#define ENET_DMACURTXBFAR_CURTXBFA_SHIFT (0) +#define ENET_DMACURTXBFAR_CURTXBFA_MASK (0xFFFFFFFFU << ENET_DMACURTXBFAR_CURTXBFA_SHIFT) +#define ENET_DMACURTXBFAR_CURTXBFA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACURTXBFAR_CURTXBFA_SHIFT)) & ENET_DMACURTXBFAR_CURTXBFA_MASK) + +/*! + * @brief ENET_PTPCR Register Bit Definition + */ + +#define ENET_PTPCR_PTPDAF_SHIFT (18) +#define ENET_PTPCR_PTPDAF_MASK (0x01U << ENET_PTPCR_PTPDAF_SHIFT) +#define ENET_PTPCR_PTPDAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPCR_PTPDAF_SHIFT)) & ENET_PTPCR_PTPDAF_MASK) + +#define ENET_PTPCR_PTPTYPS_SHIFT (14) +#define ENET_PTPCR_PTPTYPS_MASK (0xFU << ENET_PTPCR_PTPTYPS_SHIFT) +#define ENET_PTPCR_PTPTYPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPCR_PTPTYPS_SHIFT)) & ENET_PTPCR_PTPTYPS_MASK) + +#define ENET_PTPCR_PTPIPV4_SHIFT (13) +#define ENET_PTPCR_PTPIPV4_MASK (0x01U << ENET_PTPCR_PTPIPV4_SHIFT) +#define ENET_PTPCR_PTPIPV4(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPCR_PTPIPV4_SHIFT)) & ENET_PTPCR_PTPIPV4_MASK) + +#define ENET_PTPCR_PTPIPV6_SHIFT (12) +#define ENET_PTPCR_PTPIPV6_MASK (0x01U << ENET_PTPCR_PTPIPV6_SHIFT) +#define ENET_PTPCR_PTPIPV6(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPCR_PTPIPV6_SHIFT)) & ENET_PTPCR_PTPIPV6_MASK) + +#define ENET_PTPCR_PTPETH_SHIFT (11) +#define ENET_PTPCR_PTPETH_MASK (0x01U << ENET_PTPCR_PTPETH_SHIFT) +#define ENET_PTPCR_PTPETH(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPCR_PTPETH_SHIFT)) & ENET_PTPCR_PTPETH_MASK) + +#define ENET_PTPCR_PTPVER_SHIFT (10) +#define ENET_PTPCR_PTPVER_MASK (0x01U << ENET_PTPCR_PTPVER_SHIFT) +#define ENET_PTPCR_PTPVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPCR_PTPVER_SHIFT)) & ENET_PTPCR_PTPVER_MASK) + +#define ENET_PTPCR_PTPNSS_SHIFT (9) +#define ENET_PTPCR_PTPNSS_MASK (0x01U << ENET_PTPCR_PTPNSS_SHIFT) +#define ENET_PTPCR_PTPNSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPCR_PTPNSS_SHIFT)) & ENET_PTPCR_PTPNSS_MASK) + +#define ENET_PTPCR_PTPEALL_SHIFT (8) +#define ENET_PTPCR_PTPEALL_MASK (0x01U << ENET_PTPCR_PTPEALL_SHIFT) +#define ENET_PTPCR_PTPEALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPCR_PTPEALL_SHIFT)) & ENET_PTPCR_PTPEALL_MASK) + +#define ENET_PTPCR_PTPADUP_SHIFT (5) +#define ENET_PTPCR_PTPADUP_MASK (0x01U << ENET_PTPCR_PTPADUP_SHIFT) +#define ENET_PTPCR_PTPADUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPCR_PTPADUP_SHIFT)) & ENET_PTPCR_PTPADUP_MASK) + +#define ENET_PTPCR_PTPINT_SHIFT (4) +#define ENET_PTPCR_PTPINT_MASK (0x01U << ENET_PTPCR_PTPINT_SHIFT) +#define ENET_PTPCR_PTPINT(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPCR_PTPINT_SHIFT)) & ENET_PTPCR_PTPINT_MASK) + +#define ENET_PTPCR_PTPUP_SHIFT (3) +#define ENET_PTPCR_PTPUP_MASK (0x01U << ENET_PTPCR_PTPUP_SHIFT) +#define ENET_PTPCR_PTPUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPCR_PTPUP_SHIFT)) & ENET_PTPCR_PTPUP_MASK) + +#define ENET_PTPCR_PTPINI_SHIFT (2) +#define ENET_PTPCR_PTPINI_MASK (0x01U << ENET_PTPCR_PTPINI_SHIFT) +#define ENET_PTPCR_PTPINI(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPCR_PTPINI_SHIFT)) & ENET_PTPCR_PTPINI_MASK) + +#define ENET_PTPCR_PTPCS_SHIFT (1) +#define ENET_PTPCR_PTPCS_MASK (0x01U << ENET_PTPCR_PTPCS_SHIFT) +#define ENET_PTPCR_PTPCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPCR_PTPCS_SHIFT)) & ENET_PTPCR_PTPCS_MASK) + +#define ENET_PTPCR_PTPEN_SHIFT (0) +#define ENET_PTPCR_PTPEN_MASK (0x01U << ENET_PTPCR_PTPEN_SHIFT) +#define ENET_PTPCR_PTPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPCR_PTPEN_SHIFT)) & ENET_PTPCR_PTPEN_MASK) + +/*! + * @brief ENET_PTPSR Register Bit Definition + */ + +#define ENET_PTPSR_TSER1_SHIFT (5) +#define ENET_PTPSR_TSER1_MASK (0x01U << ENET_PTPSR_TSER1_SHIFT) +#define ENET_PTPSR_TSER1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPSR_TSER1_SHIFT)) & ENET_PTPSR_TSER1_MASK) + +#define ENET_PTPSR_TSTA1_SHIFT (4) +#define ENET_PTPSR_TSTA1_MASK (0x01U << ENET_PTPSR_TSTA1_SHIFT) +#define ENET_PTPSR_TSTA1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPSR_TSTA1_SHIFT)) & ENET_PTPSR_TSTA1_MASK) + +#define ENET_PTPSR_TSER0_SHIFT (3) +#define ENET_PTPSR_TSER0_MASK (0x01U << ENET_PTPSR_TSER0_SHIFT) +#define ENET_PTPSR_TSER0(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPSR_TSER0_SHIFT)) & ENET_PTPSR_TSER0_MASK) + +#define ENET_PTPSR_TSTA0_SHIFT (1) +#define ENET_PTPSR_TSTA0_MASK (0x01U << ENET_PTPSR_TSTA0_SHIFT) +#define ENET_PTPSR_TSTA0(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPSR_TSTA0_SHIFT)) & ENET_PTPSR_TSTA0_MASK) + +#define ENET_PTPSR_TSOVF_SHIFT (0) +#define ENET_PTPSR_TSOVF_MASK (0x01U << ENET_PTPSR_TSOVF_SHIFT) +#define ENET_PTPSR_TSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPSR_TSOVF_SHIFT)) & ENET_PTPSR_TSOVF_MASK) + +/*! + * @brief ENET_PTPBSAR Register Bit Definition + */ + +#define ENET_PTPBSAR_BSADD_SHIFT (0) +#define ENET_PTPBSAR_BSADD_MASK (0xFFFFFFFFU << ENET_PTPBSAR_BSADD_SHIFT) +#define ENET_PTPBSAR_BSADD(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPBSAR_BSADD_SHIFT)) & ENET_PTPBSAR_BSADD_MASK) + +/*! + * @brief ENET_PTPNSAR Register Bit Definition + */ + +#define ENET_PTPNSAR_NSADD_SHIFT (0) +#define ENET_PTPNSAR_NSADD_MASK (0xFFU << ENET_PTPNSAR_NSADD_SHIFT) +#define ENET_PTPNSAR_NSADD(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPNSAR_NSADD_SHIFT)) & ENET_PTPNSAR_NSADD_MASK) + +/*! + * @brief ENET_PTPSBSR Register Bit Definition + */ + +#define ENET_PTPSBSR_SBSEC_SHIFT (0) +#define ENET_PTPSBSR_SBSEC_MASK (0xFFFFFFFFU << ENET_PTPSBSR_SBSEC_SHIFT) +#define ENET_PTPSBSR_SBSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPSBSR_SBSEC_SHIFT)) & ENET_PTPSBSR_SBSEC_MASK) + +/*! + * @brief ENET_PTPSNSR Register Bit Definition + */ + +#define ENET_PTPSNSR_SNSEC_SHIFT (0) +#define ENET_PTPSNSR_SNSEC_MASK (0x7FFFFFFFU << ENET_PTPSNSR_SNSEC_SHIFT) +#define ENET_PTPSNSR_SNSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPSNSR_SNSEC_SHIFT)) & ENET_PTPSNSR_SNSEC_MASK) + +/*! + * @brief ENET_PTPUBSR Register Bit Definition + */ + +#define ENET_PTPUBSR_UBSEC_SHIFT (0) +#define ENET_PTPUBSR_UBSEC_MASK (0xFFFFFFFFU << ENET_PTPUBSR_UBSEC_SHIFT) +#define ENET_PTPUBSR_UBSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPUBSR_UBSEC_SHIFT)) & ENET_PTPUBSR_UBSEC_MASK) + +/*! + * @brief ENET_PTPUNSR Register Bit Definition + */ + +#define ENET_PTPUNSR_UPNSEC_SHIFT (31) +#define ENET_PTPUNSR_UPNSEC_MASK (0x01U << ENET_PTPUNSR_UPNSEC_SHIFT) +#define ENET_PTPUNSR_UPNSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPUNSR_UPNSEC_SHIFT)) & ENET_PTPUNSR_UPNSEC_MASK) + +#define ENET_PTPUNSR_UNSEC_SHIFT (0) +#define ENET_PTPUNSR_UNSEC_MASK (0x7FFFFFFFU << ENET_PTPUNSR_UNSEC_SHIFT) +#define ENET_PTPUNSR_UNSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPUNSR_UNSEC_SHIFT)) & ENET_PTPUNSR_UNSEC_MASK) + +/*! + * @brief ENET_PTPTBSR Register Bit Definition + */ + +#define ENET_PTPTBSR_TBSEC_SHIFT (0) +#define ENET_PTPTBSR_TBSEC_MASK (0xFFFFFFFFU << ENET_PTPTBSR_TBSEC_SHIFT) +#define ENET_PTPTBSR_TBSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPTBSR_TBSEC_SHIFT)) & ENET_PTPTBSR_TBSEC_MASK) + +/*! + * @brief ENET_PTPTNSR Register Bit Definition + */ + +#define ENET_PTPTNSR_TNSEC_SHIFT (0) +#define ENET_PTPTNSR_TNSEC_MASK (0x7FFFFFFFU << ENET_PTPTNSR_TNSEC_SHIFT) +#define ENET_PTPTNSR_TNSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPTNSR_TNSEC_SHIFT)) & ENET_PTPTNSR_TNSEC_MASK) + +/*! + * @brief ENET_PTPPPSR Register Bit Definition + */ + +#define ENET_PTPPPSR_TTSEL1_SHIFT (13) +#define ENET_PTPPPSR_TTSEL1_MASK (0x3U << ENET_PTPPPSR_TTSEL1_SHIFT) +#define ENET_PTPPPSR_TTSEL1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPPPSR_TTSEL1_SHIFT)) & ENET_PTPPPSR_TTSEL1_MASK) + +#define ENET_PTPPPSR_PPSOUT1_SHIFT (8) +#define ENET_PTPPPSR_PPSOUT1_MASK (0x7U << ENET_PTPPPSR_PPSOUT1_SHIFT) +#define ENET_PTPPPSR_PPSOUT1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPPPSR_PPSOUT1_SHIFT)) & ENET_PTPPPSR_PPSOUT1_MASK) + +#define ENET_PTPPPSR_TTSEL0_SHIFT (5) +#define ENET_PTPPPSR_TTSEL0_MASK (0x3U << ENET_PTPPPSR_TTSEL0_SHIFT) +#define ENET_PTPPPSR_TTSEL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPPPSR_TTSEL0_SHIFT)) & ENET_PTPPPSR_TTSEL0_MASK) + +#define ENET_PTPPPSR_PPSOMD_SHIFT (4) +#define ENET_PTPPPSR_PPSOMD_MASK (0x01U << ENET_PTPPPSR_PPSOMD_SHIFT) +#define ENET_PTPPPSR_PPSOMD(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPPPSR_PPSOMD_SHIFT)) & ENET_PTPPPSR_PPSOMD_MASK) + +#define ENET_PTPPPSR_PPSOUT0_SHIFT (0) +#define ENET_PTPPPSR_PPSOUT0_MASK (0xFU << ENET_PTPPPSR_PPSOUT0_SHIFT) +#define ENET_PTPPPSR_PPSOUT0(x) (((uint32_t)(((uint32_t)(x)) << ENET_PTPPPSR_PPSOUT0_SHIFT)) & ENET_PTPPPSR_PPSOUT0_MASK) + +/*! + * @brief ENET_PMTCR Register Bit Definition + */ + +#define ENET_PMTCR_RTWKFR_SHIFT (31) +#define ENET_PMTCR_RTWKFR_MASK (0x01U << ENET_PMTCR_RTWKFR_SHIFT) +#define ENET_PMTCR_RTWKFR(x) (((uint32_t)(((uint32_t)(x)) << ENET_PMTCR_RTWKFR_SHIFT)) & ENET_PMTCR_RTWKFR_MASK) + +#define ENET_PMTCR_RTWKPT_SHIFT (24) +#define ENET_PMTCR_RTWKPT_MASK (0x7U << ENET_PMTCR_RTWKPT_SHIFT) +#define ENET_PMTCR_RTWKPT(x) (((uint32_t)(((uint32_t)(x)) << ENET_PMTCR_RTWKPT_SHIFT)) & ENET_PMTCR_RTWKPT_MASK) + +#define ENET_PMTCR_RTWKTR_SHIFT (10) +#define ENET_PMTCR_RTWKTR_MASK (0x01U << ENET_PMTCR_RTWKTR_SHIFT) +#define ENET_PMTCR_RTWKTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_PMTCR_RTWKTR_SHIFT)) & ENET_PMTCR_RTWKTR_MASK) + +#define ENET_PMTCR_GLUB_SHIFT (9) +#define ENET_PMTCR_GLUB_MASK (0x01U << ENET_PMTCR_GLUB_SHIFT) +#define ENET_PMTCR_GLUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_PMTCR_GLUB_SHIFT)) & ENET_PMTCR_GLUB_MASK) + +#define ENET_PMTCR_WKFR_SHIFT (6) +#define ENET_PMTCR_WKFR_MASK (0x01U << ENET_PMTCR_WKFR_SHIFT) +#define ENET_PMTCR_WKFR(x) (((uint32_t)(((uint32_t)(x)) << ENET_PMTCR_WKFR_SHIFT)) & ENET_PMTCR_WKFR_MASK) + +#define ENET_PMTCR_MPFR_SHIFT (5) +#define ENET_PMTCR_MPFR_MASK (0x01U << ENET_PMTCR_MPFR_SHIFT) +#define ENET_PMTCR_MPFR(x) (((uint32_t)(((uint32_t)(x)) << ENET_PMTCR_MPFR_SHIFT)) & ENET_PMTCR_MPFR_MASK) + +#define ENET_PMTCR_WKEN_SHIFT (2) +#define ENET_PMTCR_WKEN_MASK (0x01U << ENET_PMTCR_WKEN_SHIFT) +#define ENET_PMTCR_WKEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_PMTCR_WKEN_SHIFT)) & ENET_PMTCR_WKEN_MASK) + +#define ENET_PMTCR_MPEN_SHIFT (1) +#define ENET_PMTCR_MPEN_MASK (0x01U << ENET_PMTCR_MPEN_SHIFT) +#define ENET_PMTCR_MPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_PMTCR_MPEN_SHIFT)) & ENET_PMTCR_MPEN_MASK) + +#define ENET_PMTCR_PWDN_SHIFT (0) +#define ENET_PMTCR_PWDN_MASK (0x01U << ENET_PMTCR_PWDN_SHIFT) +#define ENET_PMTCR_PWDN(x) (((uint32_t)(((uint32_t)(x)) << ENET_PMTCR_PWDN_SHIFT)) & ENET_PMTCR_PWDN_MASK) + +/*! + * @brief ENET_PMTRWFR Register Bit Definition + */ + +#define ENET_PMTRWFR_RTWKFLT_SHIFT (0) +#define ENET_PMTRWFR_RTWKFLT_MASK (0xFFFFFFFFU << ENET_PMTRWFR_RTWKFLT_SHIFT) +#define ENET_PMTRWFR_RTWKFLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_PMTRWFR_RTWKFLT_SHIFT)) & ENET_PMTRWFR_RTWKFLT_MASK) + +/*! + * @brief ENET_MMCCR Register Bit Definition + */ + +#define ENET_MMCCR_CPSEL_SHIFT (5) +#define ENET_MMCCR_CPSEL_MASK (0x01U << ENET_MMCCR_CPSEL_SHIFT) +#define ENET_MMCCR_CPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCCR_CPSEL_SHIFT)) & ENET_MMCCR_CPSEL_MASK) + +#define ENET_MMCCR_CPSET_SHIFT (4) +#define ENET_MMCCR_CPSET_MASK (0x01U << ENET_MMCCR_CPSET_SHIFT) +#define ENET_MMCCR_CPSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCCR_CPSET_SHIFT)) & ENET_MMCCR_CPSET_MASK) + +#define ENET_MMCCR_CFIX_SHIFT (3) +#define ENET_MMCCR_CFIX_MASK (0x01U << ENET_MMCCR_CFIX_SHIFT) +#define ENET_MMCCR_CFIX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCCR_CFIX_SHIFT)) & ENET_MMCCR_CFIX_MASK) + +#define ENET_MMCCR_CRRST_SHIFT (2) +#define ENET_MMCCR_CRRST_MASK (0x01U << ENET_MMCCR_CRRST_SHIFT) +#define ENET_MMCCR_CRRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCCR_CRRST_SHIFT)) & ENET_MMCCR_CRRST_MASK) + +#define ENET_MMCCR_COSR_SHIFT (1) +#define ENET_MMCCR_COSR_MASK (0x01U << ENET_MMCCR_COSR_SHIFT) +#define ENET_MMCCR_COSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCCR_COSR_SHIFT)) & ENET_MMCCR_COSR_MASK) + +#define ENET_MMCCR_CRST_SHIFT (0) +#define ENET_MMCCR_CRST_MASK (0x01U << ENET_MMCCR_CRST_SHIFT) +#define ENET_MMCCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCCR_CRST_SHIFT)) & ENET_MMCCR_CRST_MASK) + +/*! + * @brief ENET_MMCRSR Register Bit Definition + */ + +#define ENET_MMCRSR_RUGIS_SHIFT (17) +#define ENET_MMCRSR_RUGIS_MASK (0x01U << ENET_MMCRSR_RUGIS_SHIFT) +#define ENET_MMCRSR_RUGIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCRSR_RUGIS_SHIFT)) & ENET_MMCRSR_RUGIS_MASK) + +#define ENET_MMCRSR_RALIEIS_SHIFT (6) +#define ENET_MMCRSR_RALIEIS_MASK (0x01U << ENET_MMCRSR_RALIEIS_SHIFT) +#define ENET_MMCRSR_RALIEIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCRSR_RALIEIS_SHIFT)) & ENET_MMCRSR_RALIEIS_MASK) + +#define ENET_MMCRSR_RCRCEIS_SHIFT (5) +#define ENET_MMCRSR_RCRCEIS_MASK (0x01U << ENET_MMCRSR_RCRCEIS_SHIFT) +#define ENET_MMCRSR_RCRCEIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCRSR_RCRCEIS_SHIFT)) & ENET_MMCRSR_RCRCEIS_MASK) + +/*! + * @brief ENET_MMCTSR Register Bit Definition + */ + +#define ENET_MMCTSR_TAGIS_SHIFT (21) +#define ENET_MMCTSR_TAGIS_MASK (0x01U << ENET_MMCTSR_TAGIS_SHIFT) +#define ENET_MMCTSR_TAGIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCTSR_TAGIS_SHIFT)) & ENET_MMCTSR_TAGIS_MASK) + +#define ENET_MMCTSR_TGMCIS_SHIFT (15) +#define ENET_MMCTSR_TGMCIS_MASK (0x01U << ENET_MMCTSR_TGMCIS_SHIFT) +#define ENET_MMCTSR_TGMCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCTSR_TGMCIS_SHIFT)) & ENET_MMCTSR_TGMCIS_MASK) + +#define ENET_MMCTSR_TGSCIS_SHIFT (14) +#define ENET_MMCTSR_TGSCIS_MASK (0x01U << ENET_MMCTSR_TGSCIS_SHIFT) +#define ENET_MMCTSR_TGSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCTSR_TGSCIS_SHIFT)) & ENET_MMCTSR_TGSCIS_MASK) + +/*! + * @brief ENET_MMCRIR Register Bit Definition + */ + +#define ENET_MMCRIR_RUGIM_SHIFT (17) +#define ENET_MMCRIR_RUGIM_MASK (0x01U << ENET_MMCRIR_RUGIM_SHIFT) +#define ENET_MMCRIR_RUGIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCRIR_RUGIM_SHIFT)) & ENET_MMCRIR_RUGIM_MASK) + +#define ENET_MMCRIR_RALIEIM_SHIFT (6) +#define ENET_MMCRIR_RALIEIM_MASK (0x01U << ENET_MMCRIR_RALIEIM_SHIFT) +#define ENET_MMCRIR_RALIEIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCRIR_RALIEIM_SHIFT)) & ENET_MMCRIR_RALIEIM_MASK) + +#define ENET_MMCRIR_RCRCEIM_SHIFT (5) +#define ENET_MMCRIR_RCRCEIM_MASK (0x01U << ENET_MMCRIR_RCRCEIM_SHIFT) +#define ENET_MMCRIR_RCRCEIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCRIR_RCRCEIM_SHIFT)) & ENET_MMCRIR_RCRCEIM_MASK) + +/*! + * @brief ENET_MMCTIR Register Bit Definition + */ + +#define ENET_MMCTIR_TAGIM_SHIFT (21) +#define ENET_MMCTIR_TAGIM_MASK (0x01U << ENET_MMCTIR_TAGIM_SHIFT) +#define ENET_MMCTIR_TAGIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCTIR_TAGIM_SHIFT)) & ENET_MMCTIR_TAGIM_MASK) + +#define ENET_MMCTIR_TGMCIM_SHIFT (15) +#define ENET_MMCTIR_TGMCIM_MASK (0x01U << ENET_MMCTIR_TGMCIM_SHIFT) +#define ENET_MMCTIR_TGMCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCTIR_TGMCIM_SHIFT)) & ENET_MMCTIR_TGMCIM_MASK) + +#define ENET_MMCTIR_TGSCIM_SHIFT (14) +#define ENET_MMCTIR_TGSCIM_MASK (0x01U << ENET_MMCTIR_TGSCIM_SHIFT) +#define ENET_MMCTIR_TGSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCTIR_TGSCIM_SHIFT)) & ENET_MMCTIR_TGSCIM_MASK) + +/*! + * @brief ENET_MMCRUGR Register Bit Definition + */ + +#define ENET_MMCRUGR_MMCRUG_SHIFT (0) +#define ENET_MMCRUGR_MMCRUG_MASK (0xFFFFFFFFU << ENET_MMCRUGR_MMCRUG_SHIFT) +#define ENET_MMCRUGR_MMCRUG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCRUGR_MMCRUG_SHIFT)) & ENET_MMCRUGR_MMCRUG_MASK) + +/*! + * @brief ENET_MMCRALIER Register Bit Definition + */ + +#define ENET_MMCRALIER_RALIE_SHIFT (0) +#define ENET_MMCRALIER_RALIE_MASK (0xFFFFFFFFU << ENET_MMCRALIER_RALIE_SHIFT) +#define ENET_MMCRALIER_RALIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCRALIER_RALIE_SHIFT)) & ENET_MMCRALIER_RALIE_MASK) + +/*! + * @brief ENET_MMCRCRCER Register Bit Definition + */ + +#define ENET_MMCRCRCER_RCRCE_SHIFT (0) +#define ENET_MMCRCRCER_RCRCE_MASK (0xFFFFFFFFU << ENET_MMCRCRCER_RCRCE_SHIFT) +#define ENET_MMCRCRCER_RCRCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCRCRCER_RCRCE_SHIFT)) & ENET_MMCRCRCER_RCRCE_MASK) + +/*! + * @brief ENET_MMCTGR Register Bit Definition + */ + +#define ENET_MMCTGR_MMCTG_SHIFT (0) +#define ENET_MMCTGR_MMCTG_MASK (0xFFFFFFFFU << ENET_MMCTGR_MMCTG_SHIFT) +#define ENET_MMCTGR_MMCTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCTGR_MMCTG_SHIFT)) & ENET_MMCTGR_MMCTG_MASK) + +/*! + * @brief ENET_MMCTGSCR Register Bit Definition + */ + +#define ENET_MMCTGSCR_TGSC_SHIFT (0) +#define ENET_MMCTGSCR_TGSC_MASK (0xFFFFFFFFU << ENET_MMCTGSCR_TGSC_SHIFT) +#define ENET_MMCTGSCR_TGSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCTGSCR_TGSC_SHIFT)) & ENET_MMCTGSCR_TGSC_MASK) + +/*! + * @brief ENET_MMCTGMCR Register Bit Definition + */ + +#define ENET_MMCTGMCR_TGMC_SHIFT (0) +#define ENET_MMCTGMCR_TGMC_MASK (0xFFFFFFFFU << ENET_MMCTGMCR_TGMC_SHIFT) +#define ENET_MMCTGMCR_TGMC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMCTGMCR_TGMC_SHIFT)) & ENET_MMCTGMCR_TGMC_MASK) + +/*! + * @} + */ /* end of group ENET_Register_Masks */ +/****************************************************************************** + *ENET Instance +*******************************************************************************/ + +#define ENET ((ENET_Type*)ENET_BASE) + +/*! + * @} + */ /* end of group ENET_Peripheral_Access_Layer */ + +/*! + * @addtogroup EXTI_Peripheral_Access_Layer EXTI Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * EXTI Type + ******************************************************************************/ +typedef struct { + __IO uint32_t IMR; ///< interrupt mask register offset: 0x00 + __IO uint32_t EMR; ///< event mask register offset: 0x04 + __IO uint32_t RTSR; ///< Rising edge trigger select register offset: 0x08 + __IO uint32_t FTSR; ///< Falling edge trigger select register offset: 0x0C + __IO uint32_t SWIER; ///< Software Interrupt Event Register offset: 0x10 + __IO uint32_t PR; ///< pending register offset: 0x14 +} EXTI_Type; + +/******************************************************************************* + * EXTI Type + ******************************************************************************/ + +/*! + * @addtogroup EXTI_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief EXTI_IMR Register Bit Definition + */ + +#define EXTI_IMR_IMR_SHIFT (0) +#define EXTI_IMR_IMR_MASK (0xFFFFFFFFU << EXTI_IMR_IMR_SHIFT) +#define EXTI_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << EXTI_IMR_IMR_SHIFT)) & EXTI_IMR_IMR_MASK) + +/*! + * @brief EXTI_EMR Register Bit Definition + */ + +#define EXTI_EMR_IMR_SHIFT (0) +#define EXTI_EMR_IMR_MASK (0xFFFFFFFFU << EXTI_EMR_IMR_SHIFT) +#define EXTI_EMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << EXTI_EMR_IMR_SHIFT)) & EXTI_EMR_IMR_MASK) + +/*! + * @brief EXTI_RTSR Register Bit Definition + */ + +#define EXTI_RTSR_TR_SHIFT (0) +#define EXTI_RTSR_TR_MASK (0xFFFFFFFFU << EXTI_RTSR_TR_SHIFT) +#define EXTI_RTSR_TR(x) (((uint32_t)(((uint32_t)(x)) << EXTI_RTSR_TR_SHIFT)) & EXTI_RTSR_TR_MASK) + +/*! + * @brief EXTI_FTSR Register Bit Definition + */ + +#define EXTI_FTSR_TR_SHIFT (0) +#define EXTI_FTSR_TR_MASK (0xFFFFFFFFU << EXTI_FTSR_TR_SHIFT) +#define EXTI_FTSR_TR(x) (((uint32_t)(((uint32_t)(x)) << EXTI_FTSR_TR_SHIFT)) & EXTI_FTSR_TR_MASK) + +/*! + * @brief EXTI_SWIER Register Bit Definition + */ + +#define EXTI_SWIER_SWIER_SHIFT (0) +#define EXTI_SWIER_SWIER_MASK (0xFFFFFFFFU << EXTI_SWIER_SWIER_SHIFT) +#define EXTI_SWIER_SWIER(x) (((uint32_t)(((uint32_t)(x)) << EXTI_SWIER_SWIER_SHIFT)) & EXTI_SWIER_SWIER_MASK) + +#define EXTI_SWIER_SWIER_SHIFT (0) +#define EXTI_SWIER_SWIER_MASK (0xFFFFFFFFU << EXTI_SWIER_SWIER_SHIFT) +#define EXTI_SWIER_SWIER(x) (((uint32_t)(((uint32_t)(x)) << EXTI_SWIER_SWIER_SHIFT)) & EXTI_SWIER_SWIER_MASK) + +/*! + * @brief EXTI_PR Register Bit Definition + */ + +#define EXTI_PR_PR_SHIFT (0) +#define EXTI_PR_PR_MASK (0xFFFFFFFFU << EXTI_PR_PR_SHIFT) +#define EXTI_PR_PR(x) (((uint32_t)(((uint32_t)(x)) << EXTI_PR_PR_SHIFT)) & EXTI_PR_PR_MASK) + +/*! + * @} + */ /* end of group EXTI_Register_Masks */ +/****************************************************************************** + *EXTI Instance +*******************************************************************************/ + +#define EXTI ((EXTI_Type*)EXTI_BASE) + +/*! + * @} + */ /* end of group EXTI_Peripheral_Access_Layer */ + + + + +/*! + * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * FLASH Type + ******************************************************************************/ +typedef struct { + __IO uint32_t ACR; ///< Flash Access Control Register offset: 0x00 + __IO uint32_t KEYR; ///< FPEC key register offset: 0x04 + __IO uint32_t OPTKEYR; ///< Flash OPTKEY register offset: 0x08 + __IO uint32_t SR; ///< Flash Status Register offset: 0x0C + __IO uint32_t CR; ///< Flash Control Register offset: 0x10 + __IO uint32_t AR; ///< Flash Address Register offset: 0x14 + __IO uint32_t Reserved24[1]; ///< Reserved + __IO uint32_t OBR; ///< option byte register offset: 0x1C + __IO uint32_t WRPR[2]; ///< write protect register 0 offset: 0x20 +} FLASH_Type; + +/******************************************************************************* + * FLASH Type + ******************************************************************************/ + +/*! + * @addtogroup FLASH_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief FLASH_ACR Register Bit Definition + */ + +#define FLASH_ACR_PRFTBS_SHIFT (5) +#define FLASH_ACR_PRFTBS_MASK (0x01U << FLASH_ACR_PRFTBS_SHIFT) +#define FLASH_ACR_PRFTBS(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ACR_PRFTBS_SHIFT)) & FLASH_ACR_PRFTBS_MASK) + +#define FLASH_ACR_PRFTBE_SHIFT (4) +#define FLASH_ACR_PRFTBE_MASK (0x01U << FLASH_ACR_PRFTBE_SHIFT) +#define FLASH_ACR_PRFTBE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ACR_PRFTBE_SHIFT)) & FLASH_ACR_PRFTBE_MASK) + +#define FLASH_ACR_LATENCY_SHIFT (0) +#define FLASH_ACR_LATENCY_MASK (0x7U << FLASH_ACR_LATENCY_SHIFT) +#define FLASH_ACR_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_ACR_LATENCY_SHIFT)) & FLASH_ACR_LATENCY_MASK) + +/*! + * @brief FLASH_KEYR Register Bit Definition + */ + +#define FLASH_KEYR_FKEYR_SHIFT (0) +#define FLASH_KEYR_FKEYR_MASK (0xFFFFFFFFU << FLASH_KEYR_FKEYR_SHIFT) +#define FLASH_KEYR_FKEYR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEYR_FKEYR_SHIFT)) & FLASH_KEYR_FKEYR_MASK) + +/*! + * @brief FLASH_OPTKEYR Register Bit Definition + */ + +#define FLASH_OPTKEYR_OPTKEYR_SHIFT (0) +#define FLASH_OPTKEYR_OPTKEYR_MASK (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_SHIFT) +#define FLASH_OPTKEYR_OPTKEYR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_OPTKEYR_OPTKEYR_SHIFT)) & FLASH_OPTKEYR_OPTKEYR_MASK) + +/*! + * @brief FLASH_SR Register Bit Definition + */ + +#define FLASH_SR_EOP_SHIFT (5) +#define FLASH_SR_EOP_MASK (0x01U << FLASH_SR_EOP_SHIFT) +#define FLASH_SR_EOP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_SR_EOP_SHIFT)) & FLASH_SR_EOP_MASK) + +#define FLASH_SR_WRPRTERR_SHIFT (4) +#define FLASH_SR_WRPRTERR_MASK (0x01U << FLASH_SR_WRPRTERR_SHIFT) +#define FLASH_SR_WRPRTERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_SR_WRPRTERR_SHIFT)) & FLASH_SR_WRPRTERR_MASK) + +#define FLASH_SR_PGERR_SHIFT (2) +#define FLASH_SR_PGERR_MASK (0x01U << FLASH_SR_PGERR_SHIFT) +#define FLASH_SR_PGERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_SR_PGERR_SHIFT)) & FLASH_SR_PGERR_MASK) + +#define FLASH_SR_BSY_SHIFT (0) +#define FLASH_SR_BSY_MASK (0x01U << FLASH_SR_BSY_SHIFT) +#define FLASH_SR_BSY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_SR_BSY_SHIFT)) & FLASH_SR_BSY_MASK) + +/*! + * @brief FLASH_CR Register Bit Definition + */ + +#define FLASH_CR_OPTWRE_SHIFT (9) +#define FLASH_CR_OPTWRE_MASK (0x01U << FLASH_CR_OPTWRE_SHIFT) +#define FLASH_CR_OPTWRE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CR_OPTWRE_SHIFT)) & FLASH_CR_OPTWRE_MASK) + +#define FLASH_CR_LOCK_SHIFT (7) +#define FLASH_CR_LOCK_MASK (0x01U << FLASH_CR_LOCK_SHIFT) +#define FLASH_CR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CR_LOCK_SHIFT)) & FLASH_CR_LOCK_MASK) + +#define FLASH_CR_STRT_SHIFT (6) +#define FLASH_CR_STRT_MASK (0x01U << FLASH_CR_STRT_SHIFT) +#define FLASH_CR_STRT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CR_STRT_SHIFT)) & FLASH_CR_STRT_MASK) + +#define FLASH_CR_OPTER_SHIFT (5) +#define FLASH_CR_OPTER_MASK (0x01U << FLASH_CR_OPTER_SHIFT) +#define FLASH_CR_OPTER(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CR_OPTER_SHIFT)) & FLASH_CR_OPTER_MASK) + +#define FLASH_CR_OPTPG_SHIFT (4) +#define FLASH_CR_OPTPG_MASK (0x01U << FLASH_CR_OPTPG_SHIFT) +#define FLASH_CR_OPTPG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CR_OPTPG_SHIFT)) & FLASH_CR_OPTPG_MASK) + +#define FLASH_CR_MER_SHIFT (2) +#define FLASH_CR_MER_MASK (0x01U << FLASH_CR_MER_SHIFT) +#define FLASH_CR_MER(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CR_MER_SHIFT)) & FLASH_CR_MER_MASK) + +#define FLASH_CR_PER_SHIFT (1) +#define FLASH_CR_PER_MASK (0x01U << FLASH_CR_PER_SHIFT) +#define FLASH_CR_PER(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CR_PER_SHIFT)) & FLASH_CR_PER_MASK) + +#define FLASH_CR_PG_SHIFT (0) +#define FLASH_CR_PG_MASK (0x01U << FLASH_CR_PG_SHIFT) +#define FLASH_CR_PG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CR_PG_SHIFT)) & FLASH_CR_PG_MASK) + +/*! + * @brief FLASH_AR Register Bit Definition + */ + +#define FLASH_AR_FAR_SHIFT (0) +#define FLASH_AR_FAR_MASK (0xFFFFFFFFU << FLASH_AR_FAR_SHIFT) +#define FLASH_AR_FAR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_AR_FAR_SHIFT)) & FLASH_AR_FAR_MASK) + +/*! + * @brief FLASH_OBR Register Bit Definition + */ + +#define FLASH_OBR_DATA1_SHIFT (18) +#define FLASH_OBR_DATA1_MASK (0xFFU << FLASH_OBR_DATA1_SHIFT) +#define FLASH_OBR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_OBR_DATA1_SHIFT)) & FLASH_OBR_DATA1_MASK) + +#define FLASH_OBR_DATA0_SHIFT (10) +#define FLASH_OBR_DATA0_MASK (0xFFU << FLASH_OBR_DATA0_SHIFT) +#define FLASH_OBR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_OBR_DATA0_SHIFT)) & FLASH_OBR_DATA0_MASK) + +#define FLASH_OBR_NRSTSTDBY_SHIFT (4) +#define FLASH_OBR_NRSTSTDBY_MASK (0x01U << FLASH_OBR_NRSTSTDBY_SHIFT) +#define FLASH_OBR_NRSTSTDBY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_OBR_NRSTSTDBY_SHIFT)) & FLASH_OBR_NRSTSTDBY_MASK) + +#define FLASH_OBR_NRSTSTOP_SHIFT (3) +#define FLASH_OBR_NRSTSTOP_MASK (0x01U << FLASH_OBR_NRSTSTOP_SHIFT) +#define FLASH_OBR_NRSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_OBR_NRSTSTOP_SHIFT)) & FLASH_OBR_NRSTSTOP_MASK) + +#define FLASH_OBR_WDGSW_SHIFT (2) +#define FLASH_OBR_WDGSW_MASK (0x01U << FLASH_OBR_WDGSW_SHIFT) +#define FLASH_OBR_WDGSW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_OBR_WDGSW_SHIFT)) & FLASH_OBR_WDGSW_MASK) + +#define FLASH_OBR_RDPRT_SHIFT (1) +#define FLASH_OBR_RDPRT_MASK (0x01U << FLASH_OBR_RDPRT_SHIFT) +#define FLASH_OBR_RDPRT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_OBR_RDPRT_SHIFT)) & FLASH_OBR_RDPRT_MASK) + +#define FLASH_OBR_OPTERR_SHIFT (0) +#define FLASH_OBR_OPTERR_MASK (0x01U << FLASH_OBR_OPTERR_SHIFT) +#define FLASH_OBR_OPTERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_OBR_OPTERR_SHIFT)) & FLASH_OBR_OPTERR_MASK) + +/*! + * @brief FLASH_WRPR Register Bit Definition + */ + +#define FLASH_WRPR_WRP_SHIFT (0) +#define FLASH_WRPR_WRP_MASK (0xFFFFFFFFU << FLASH_WRPR_WRP_SHIFT) +#define FLASH_WRPR_WRP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_WRPR_WRP_SHIFT)) & FLASH_WRPR_WRP_MASK) + + +/*! + * @} + */ /* end of group FLASH_Register_Masks */ +/****************************************************************************** + *FLASH Instance +*******************************************************************************/ + +#define FLASH ((FLASH_Type*)FLASH_BASE) + +/*! + * @} + */ /* end of group FLASH_Peripheral_Access_Layer */ + + + + +/*! + * @addtogroup FLEXCAN_Peripheral_Access_Layer FLEXCAN Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * FLEXCAN Type + ******************************************************************************/ +typedef struct { + __IO uint32_t MCR ; ///< Module configuration register offset: 0x0 + __IO uint32_t CTRL1 ; ///< Control 1 register offset: 0x4 + __IO uint32_t TIMER ; ///< Free running timer register offset: 0x8 + __IO uint32_t Reserved0[1]; ///< Reserved + __IO uint32_t RXMGMASK; ///< Rx mailbox global mask register offset: 0x10 + __IO uint32_t RX14MASK; ///< Rx 14 mask register offset: 0x14 + __IO uint32_t RX15MASK; ///< Rx 15 mask register offset: 0x18 + __IO uint32_t ECR ; ///< Error count register offset: 0x1C + __IO uint32_t ESR1 ; ///< Error and status 1 register offset: 0x20 + __IO uint32_t Reserved1[1]; ///< Reserved + __IO uint32_t IMASK1 ; ///< Interrupt mask 1 register offset: 0x28 + __IO uint32_t Reserved2[1]; ///< Reserved + __IO uint32_t IFLAG1 ; ///< Interrupt flag 1 register offset: 0x30 + __IO uint32_t CTRL2; ///< Control 2 register offset: 0x34 + __IO uint32_t ESR2 ; ///< Error and status 2 register offset: 0x38 + __IO uint32_t Reserved3[2]; ///< Reserved + __IO uint32_t CRCR ; ///< CRC register offset: 0x44 + __IO uint32_t RXFGMASK ; ///< Rx FIFO global mask register offset: 0x48 + __IO uint32_t RXFIR ; ///< Rx FIFO information register offset: 0x4C + __IO uint32_t CBT ; ///< CAN bit timing register offset: 0x50 + __IO uint32_t Reserved4[11]; ///< Reserved + struct { + __IO uint32_t CS ; ///< Message Buffer 0 CS Register offset: 0x80 + __IO uint32_t ID; ///< Message Buffer 0 ID Register offset: 0x84 + __IO uint32_t WORD0; ///< Message Buffer 0 WORD0 Register offset: 0x88 + __IO uint32_t WORD1; ///< Message Buffer 0 WORD1 Register offset: 0x8C + } MB[16]; + __IO uint32_t Reserved5[448]; ///< Reserved + __IO uint32_t RXIMRN[16] ; ///< Rx single mask register offset: 0x880 +} FLEXCAN_Type; + +/******************************************************************************* + * FLEXCAN Type + ******************************************************************************/ + +/*! + * @addtogroup FLEXCAN_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief FLEXCAN_MCR Register Bit Definition + */ + +#define FLEXCAN_MCR_MDIS_SHIFT (31) +#define FLEXCAN_MCR_MDIS_MASK (0x01U << FLEXCAN_MCR_MDIS_SHIFT) +#define FLEXCAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_MDIS_SHIFT)) & FLEXCAN_MCR_MDIS_MASK) + +#define FLEXCAN_MCR_FRZ_SHIFT (30) +#define FLEXCAN_MCR_FRZ_MASK (0x01U << FLEXCAN_MCR_FRZ_SHIFT) +#define FLEXCAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_FRZ_SHIFT)) & FLEXCAN_MCR_FRZ_MASK) + +#define FLEXCAN_MCR_RFEN_SHIFT (29) +#define FLEXCAN_MCR_RFEN_MASK (0x01U << FLEXCAN_MCR_RFEN_SHIFT) +#define FLEXCAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_RFEN_SHIFT)) & FLEXCAN_MCR_RFEN_MASK) + +#define FLEXCAN_MCR_HALT_SHIFT (28) +#define FLEXCAN_MCR_HALT_MASK (0x01U << FLEXCAN_MCR_HALT_SHIFT) +#define FLEXCAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_HALT_SHIFT)) & FLEXCAN_MCR_HALT_MASK) + +#define FLEXCAN_MCR_NOTRDY_SHIFT (27) +#define FLEXCAN_MCR_NOTRDY_MASK (0x01U << FLEXCAN_MCR_NOTRDY_SHIFT) +#define FLEXCAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_NOTRDY_SHIFT)) & FLEXCAN_MCR_NOTRDY_MASK) + +#define FLEXCAN_MCR_SOFTRST_SHIFT (25) +#define FLEXCAN_MCR_SOFTRST_MASK (0x01U << FLEXCAN_MCR_SOFTRST_SHIFT) +#define FLEXCAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_SOFTRST_SHIFT)) & FLEXCAN_MCR_SOFTRST_MASK) + +#define FLEXCAN_MCR_FRZACK_SHIFT (24) +#define FLEXCAN_MCR_FRZACK_MASK (0x01U << FLEXCAN_MCR_FRZACK_SHIFT) +#define FLEXCAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_FRZACK_SHIFT)) & FLEXCAN_MCR_FRZACK_MASK) + +#define FLEXCAN_MCR_SUPV_SHIFT (23) +#define FLEXCAN_MCR_SUPV_MASK (0x01U << FLEXCAN_MCR_SUPV_SHIFT) +#define FLEXCAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_SUPV_SHIFT)) & FLEXCAN_MCR_SUPV_MASK) + +#define FLEXCAN_MCR_SLFWAK_SHIFT (22) +#define FLEXCAN_MCR_SLFWAK_MASK (0x01U << FLEXCAN_MCR_SLFWAK_SHIFT) +#define FLEXCAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_SLFWAK_SHIFT)) & FLEXCAN_MCR_SLFWAK_MASK) + +#define FLEXCAN_MCR_WRNEN_SHIFT (21) +#define FLEXCAN_MCR_WRNEN_MASK (0x01U << FLEXCAN_MCR_WRNEN_SHIFT) +#define FLEXCAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_WRNEN_SHIFT)) & FLEXCAN_MCR_WRNEN_MASK) + +#define FLEXCAN_MCR_LPMACK_SHIFT (20) +#define FLEXCAN_MCR_LPMACK_MASK (0x01U << FLEXCAN_MCR_LPMACK_SHIFT) +#define FLEXCAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_LPMACK_SHIFT)) & FLEXCAN_MCR_LPMACK_MASK) + +#define FLEXCAN_MCR_WAKSRC_SHIFT (19) +#define FLEXCAN_MCR_WAKSRC_MASK (0x01U << FLEXCAN_MCR_WAKSRC_SHIFT) +#define FLEXCAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_WAKSRC_SHIFT)) & FLEXCAN_MCR_WAKSRC_MASK) + +#define FLEXCAN_MCR_SRXDIS_SHIFT (17) +#define FLEXCAN_MCR_SRXDIS_MASK (0x01U << FLEXCAN_MCR_SRXDIS_SHIFT) +#define FLEXCAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_SRXDIS_SHIFT)) & FLEXCAN_MCR_SRXDIS_MASK) + +#define FLEXCAN_MCR_IRMQ_SHIFT (16) +#define FLEXCAN_MCR_IRMQ_MASK (0x01U << FLEXCAN_MCR_IRMQ_SHIFT) +#define FLEXCAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_IRMQ_SHIFT)) & FLEXCAN_MCR_IRMQ_MASK) + +#define FLEXCAN_MCR_DMA_SHIFT (15) +#define FLEXCAN_MCR_DMA_MASK (0x01U << FLEXCAN_MCR_DMA_SHIFT) +#define FLEXCAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_DMA_SHIFT)) & FLEXCAN_MCR_DMA_MASK) + +#define FLEXCAN_MCR_LPRIOEN_SHIFT (13) +#define FLEXCAN_MCR_LPRIOEN_MASK (0x01U << FLEXCAN_MCR_LPRIOEN_SHIFT) +#define FLEXCAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_LPRIOEN_SHIFT)) & FLEXCAN_MCR_LPRIOEN_MASK) + +#define FLEXCAN_MCR_AEN_SHIFT (12) +#define FLEXCAN_MCR_AEN_MASK (0x01U << FLEXCAN_MCR_AEN_SHIFT) +#define FLEXCAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_AEN_SHIFT)) & FLEXCAN_MCR_AEN_MASK) + +#define FLEXCAN_MCR_IDAM_SHIFT (8) +#define FLEXCAN_MCR_IDAM_MASK (0x3U << FLEXCAN_MCR_IDAM_SHIFT) +#define FLEXCAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_IDAM_SHIFT)) & FLEXCAN_MCR_IDAM_MASK) + +#define FLEXCAN_MCR_MAXMB_SHIFT (0) +#define FLEXCAN_MCR_MAXMB_MASK (0x7FU << FLEXCAN_MCR_MAXMB_SHIFT) +#define FLEXCAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_MAXMB_SHIFT)) & FLEXCAN_MCR_MAXMB_MASK) + +/*! + * @brief FLEXCAN_CTRL1 Register Bit Definition + */ + +#define FLEXCAN_CTRL1_PRESDIV_SHIFT (24) +#define FLEXCAN_CTRL1_PRESDIV_MASK (0xFFU << FLEXCAN_CTRL1_PRESDIV_SHIFT) +#define FLEXCAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_PRESDIV_SHIFT)) & FLEXCAN_CTRL1_PRESDIV_MASK) + +#define FLEXCAN_CTRL1_RJW_SHIFT (22) +#define FLEXCAN_CTRL1_RJW_MASK (0x3U << FLEXCAN_CTRL1_RJW_SHIFT) +#define FLEXCAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_RJW_SHIFT)) & FLEXCAN_CTRL1_RJW_MASK) + +#define FLEXCAN_CTRL1_PSEG1_SHIFT (19) +#define FLEXCAN_CTRL1_PSEG1_MASK (0x7U << FLEXCAN_CTRL1_PSEG1_SHIFT) +#define FLEXCAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_PSEG1_SHIFT)) & FLEXCAN_CTRL1_PSEG1_MASK) + +#define FLEXCAN_CTRL1_PSEG2_SHIFT (16) +#define FLEXCAN_CTRL1_PSEG2_MASK (0x7U << FLEXCAN_CTRL1_PSEG2_SHIFT) +#define FLEXCAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_PSEG2_SHIFT)) & FLEXCAN_CTRL1_PSEG2_MASK) + +#define FLEXCAN_CTRL1_BOFFMSK_SHIFT (15) +#define FLEXCAN_CTRL1_BOFFMSK_MASK (0x01U << FLEXCAN_CTRL1_BOFFMSK_SHIFT) +#define FLEXCAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_BOFFMSK_SHIFT)) & FLEXCAN_CTRL1_BOFFMSK_MASK) + +#define FLEXCAN_CTRL1_ERRMSK_SHIFT (14) +#define FLEXCAN_CTRL1_ERRMSK_MASK (0x01U << FLEXCAN_CTRL1_ERRMSK_SHIFT) +#define FLEXCAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_ERRMSK_SHIFT)) & FLEXCAN_CTRL1_ERRMSK_MASK) + +#define FLEXCAN_CTRL1_CLKSRC_SHIFT (13) +#define FLEXCAN_CTRL1_CLKSRC_MASK (0x01U << FLEXCAN_CTRL1_CLKSRC_SHIFT) +#define FLEXCAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_CLKSRC_SHIFT)) & FLEXCAN_CTRL1_CLKSRC_MASK) + +#define FLEXCAN_CTRL1_LPB_SHIFT (12) +#define FLEXCAN_CTRL1_LPB_MASK (0x01U << FLEXCAN_CTRL1_LPB_SHIFT) +#define FLEXCAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_LPB_SHIFT)) & FLEXCAN_CTRL1_LPB_MASK) + +#define FLEXCAN_CTRL1_TWRNMSK_SHIFT (11) +#define FLEXCAN_CTRL1_TWRNMSK_MASK (0x01U << FLEXCAN_CTRL1_TWRNMSK_SHIFT) +#define FLEXCAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_TWRNMSK_SHIFT)) & FLEXCAN_CTRL1_TWRNMSK_MASK) + +#define FLEXCAN_CTRL1_RWRNMSK_SHIFT (10) +#define FLEXCAN_CTRL1_RWRNMSK_MASK (0x01U << FLEXCAN_CTRL1_RWRNMSK_SHIFT) +#define FLEXCAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_RWRNMSK_SHIFT)) & FLEXCAN_CTRL1_RWRNMSK_MASK) + +#define FLEXCAN_CTRL1_SMP_SHIFT (7) +#define FLEXCAN_CTRL1_SMP_MASK (0x01U << FLEXCAN_CTRL1_SMP_SHIFT) +#define FLEXCAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_SMP_SHIFT)) & FLEXCAN_CTRL1_SMP_MASK) + +#define FLEXCAN_CTRL1_BOFFREC_SHIFT (6) +#define FLEXCAN_CTRL1_BOFFREC_MASK (0x01U << FLEXCAN_CTRL1_BOFFREC_SHIFT) +#define FLEXCAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_BOFFREC_SHIFT)) & FLEXCAN_CTRL1_BOFFREC_MASK) + +#define FLEXCAN_CTRL1_TSYN_SHIFT (5) +#define FLEXCAN_CTRL1_TSYN_MASK (0x01U << FLEXCAN_CTRL1_TSYN_SHIFT) +#define FLEXCAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_TSYN_SHIFT)) & FLEXCAN_CTRL1_TSYN_MASK) + +#define FLEXCAN_CTRL1_LBUF_SHIFT (4) +#define FLEXCAN_CTRL1_LBUF_MASK (0x01U << FLEXCAN_CTRL1_LBUF_SHIFT) +#define FLEXCAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_LBUF_SHIFT)) & FLEXCAN_CTRL1_LBUF_MASK) + +#define FLEXCAN_CTRL1_LOM_SHIFT (3) +#define FLEXCAN_CTRL1_LOM_MASK (0x01U << FLEXCAN_CTRL1_LOM_SHIFT) +#define FLEXCAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_LOM_SHIFT)) & FLEXCAN_CTRL1_LOM_MASK) + +#define FLEXCAN_CTRL1_PROPSEG_SHIFT (0) +#define FLEXCAN_CTRL1_PROPSEG_MASK (0x7U << FLEXCAN_CTRL1_PROPSEG_SHIFT) +#define FLEXCAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_PROPSEG_SHIFT)) & FLEXCAN_CTRL1_PROPSEG_MASK) + +/*! + * @brief FLEXCAN_TIMER Register Bit Definition + */ + +#define FLEXCAN_TIMER_TIMER_SHIFT (0) +#define FLEXCAN_TIMER_TIMER_MASK (0xFFFFU << FLEXCAN_TIMER_TIMER_SHIFT) +#define FLEXCAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_TIMER_TIMER_SHIFT)) & FLEXCAN_TIMER_TIMER_MASK) + +/*! + * @brief FLEXCAN_RXMGMASK Register Bit Definition + */ + +#define FLEXCAN_RXMGMASK_MG_SHIFT (0) +#define FLEXCAN_RXMGMASK_MG_MASK (0xFFFFFFFFU << FLEXCAN_RXMGMASK_MG_SHIFT) +#define FLEXCAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXMGMASK_MG_SHIFT)) & FLEXCAN_RXMGMASK_MG_MASK) + +/*! + * @brief FLEXCAN_RX14MASK Register Bit Definition + */ + +#define FLEXCAN_RX14MASK_RX14M_SHIFT (0) +#define FLEXCAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU << FLEXCAN_RX14MASK_RX14M_SHIFT) +#define FLEXCAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RX14MASK_RX14M_SHIFT)) & FLEXCAN_RX14MASK_RX14M_MASK) + +/*! + * @brief FLEXCAN_RX15MASK Register Bit Definition + */ + +#define FLEXCAN_RX15MASK_RX15M_SHIFT (0) +#define FLEXCAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU << FLEXCAN_RX15MASK_RX15M_SHIFT) +#define FLEXCAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RX15MASK_RX15M_SHIFT)) & FLEXCAN_RX15MASK_RX15M_MASK) + +/*! + * @brief FLEXCAN_ECR Register Bit Definition + */ + +#define FLEXCAN_ECR_RXERRCNT_SHIFT (8) +#define FLEXCAN_ECR_RXERRCNT_MASK (0xFFU << FLEXCAN_ECR_RXERRCNT_SHIFT) +#define FLEXCAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ECR_RXERRCNT_SHIFT)) & FLEXCAN_ECR_RXERRCNT_MASK) + +#define FLEXCAN_ECR_TXERRCNT_SHIFT (0) +#define FLEXCAN_ECR_TXERRCNT_MASK (0xFFU << FLEXCAN_ECR_TXERRCNT_SHIFT) +#define FLEXCAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ECR_TXERRCNT_SHIFT)) & FLEXCAN_ECR_TXERRCNT_MASK) + +/*! + * @brief FLEXCAN_ESR1 Register Bit Definition + */ + +#define FLEXCAN_ESR1_ERROVR_SHIFT (21) +#define FLEXCAN_ESR1_ERROVR_MASK (0x01U << FLEXCAN_ESR1_ERROVR_SHIFT) +#define FLEXCAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_ERROVR_SHIFT)) & FLEXCAN_ESR1_ERROVR_MASK) + +#define FLEXCAN_ESR1_BOFFDONEINT_SHIFT (19) +#define FLEXCAN_ESR1_BOFFDONEINT_MASK (0x01U << FLEXCAN_ESR1_BOFFDONEINT_SHIFT) +#define FLEXCAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_BOFFDONEINT_SHIFT)) & FLEXCAN_ESR1_BOFFDONEINT_MASK) + +#define FLEXCAN_ESR1_SYNCH_SHIFT (18) +#define FLEXCAN_ESR1_SYNCH_MASK (0x01U << FLEXCAN_ESR1_SYNCH_SHIFT) +#define FLEXCAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_SYNCH_SHIFT)) & FLEXCAN_ESR1_SYNCH_MASK) + +#define FLEXCAN_ESR1_TWRNINT_SHIFT (17) +#define FLEXCAN_ESR1_TWRNINT_MASK (0x01U << FLEXCAN_ESR1_TWRNINT_SHIFT) +#define FLEXCAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_TWRNINT_SHIFT)) & FLEXCAN_ESR1_TWRNINT_MASK) + +#define FLEXCAN_ESR1_RWRNINT_SHIFT (16) +#define FLEXCAN_ESR1_RWRNINT_MASK (0x01U << FLEXCAN_ESR1_RWRNINT_SHIFT) +#define FLEXCAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_RWRNINT_SHIFT)) & FLEXCAN_ESR1_RWRNINT_MASK) + +#define FLEXCAN_ESR1_BIT1ERR_SHIFT (15) +#define FLEXCAN_ESR1_BIT1ERR_MASK (0x01U << FLEXCAN_ESR1_BIT1ERR_SHIFT) +#define FLEXCAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_BIT1ERR_SHIFT)) & FLEXCAN_ESR1_BIT1ERR_MASK) + +#define FLEXCAN_ESR1_BIT0ERR_SHIFT (14) +#define FLEXCAN_ESR1_BIT0ERR_MASK (0x01U << FLEXCAN_ESR1_BIT0ERR_SHIFT) +#define FLEXCAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_BIT0ERR_SHIFT)) & FLEXCAN_ESR1_BIT0ERR_MASK) + +#define FLEXCAN_ESR1_ACKERR_SHIFT (13) +#define FLEXCAN_ESR1_ACKERR_MASK (0x01U << FLEXCAN_ESR1_ACKERR_SHIFT) +#define FLEXCAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_ACKERR_SHIFT)) & FLEXCAN_ESR1_ACKERR_MASK) + +#define FLEXCAN_ESR1_CRCERR_SHIFT (12) +#define FLEXCAN_ESR1_CRCERR_MASK (0x01U << FLEXCAN_ESR1_CRCERR_SHIFT) +#define FLEXCAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_CRCERR_SHIFT)) & FLEXCAN_ESR1_CRCERR_MASK) + +#define FLEXCAN_ESR1_FRMERR_SHIFT (11) +#define FLEXCAN_ESR1_FRMERR_MASK (0x01U << FLEXCAN_ESR1_FRMERR_SHIFT) +#define FLEXCAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_FRMERR_SHIFT)) & FLEXCAN_ESR1_FRMERR_MASK) + +#define FLEXCAN_ESR1_STFERR_SHIFT (10) +#define FLEXCAN_ESR1_STFERR_MASK (0x01U << FLEXCAN_ESR1_STFERR_SHIFT) +#define FLEXCAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_STFERR_SHIFT)) & FLEXCAN_ESR1_STFERR_MASK) + +#define FLEXCAN_ESR1_TXWRN_SHIFT (9) +#define FLEXCAN_ESR1_TXWRN_MASK (0x01U << FLEXCAN_ESR1_TXWRN_SHIFT) +#define FLEXCAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_TXWRN_SHIFT)) & FLEXCAN_ESR1_TXWRN_MASK) + +#define FLEXCAN_ESR1_RXWRN_SHIFT (8) +#define FLEXCAN_ESR1_RXWRN_MASK (0x01U << FLEXCAN_ESR1_RXWRN_SHIFT) +#define FLEXCAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_RXWRN_SHIFT)) & FLEXCAN_ESR1_RXWRN_MASK) + +#define FLEXCAN_ESR1_IDLE_SHIFT (7) +#define FLEXCAN_ESR1_IDLE_MASK (0x01U << FLEXCAN_ESR1_IDLE_SHIFT) +#define FLEXCAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_IDLE_SHIFT)) & FLEXCAN_ESR1_IDLE_MASK) + +#define FLEXCAN_ESR1_TX_SHIFT (6) +#define FLEXCAN_ESR1_TX_MASK (0x01U << FLEXCAN_ESR1_TX_SHIFT) +#define FLEXCAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_TX_SHIFT)) & FLEXCAN_ESR1_TX_MASK) + +#define FLEXCAN_ESR1_FLTCONF_SHIFT (4) +#define FLEXCAN_ESR1_FLTCONF_MASK (0x3U << FLEXCAN_ESR1_FLTCONF_SHIFT) +#define FLEXCAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_FLTCONF_SHIFT)) & FLEXCAN_ESR1_FLTCONF_MASK) + +#define FLEXCAN_ESR1_RX_SHIFT (3) +#define FLEXCAN_ESR1_RX_MASK (0x01U << FLEXCAN_ESR1_RX_SHIFT) +#define FLEXCAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_RX_SHIFT)) & FLEXCAN_ESR1_RX_MASK) + +#define FLEXCAN_ESR1_BOFFINT_SHIFT (2) +#define FLEXCAN_ESR1_BOFFINT_MASK (0x01U << FLEXCAN_ESR1_BOFFINT_SHIFT) +#define FLEXCAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_BOFFINT_SHIFT)) & FLEXCAN_ESR1_BOFFINT_MASK) + +#define FLEXCAN_ESR1_ERRINT_SHIFT (1) +#define FLEXCAN_ESR1_ERRINT_MASK (0x01U << FLEXCAN_ESR1_ERRINT_SHIFT) +#define FLEXCAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_ERRINT_SHIFT)) & FLEXCAN_ESR1_ERRINT_MASK) + +#define FLEXCAN_ESR1_WAKINT_SHIFT (0) +#define FLEXCAN_ESR1_WAKINT_MASK (0x01U << FLEXCAN_ESR1_WAKINT_SHIFT) +#define FLEXCAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_WAKINT_SHIFT)) & FLEXCAN_ESR1_WAKINT_MASK) + +/*! + * @brief FLEXCAN_IMASK1 Register Bit Definition + */ + +#define FLEXCAN_IMASK1_BUF15TO0M_SHIFT (0) +#define FLEXCAN_IMASK1_BUF15TO0M_MASK (0xFFFFU << FLEXCAN_IMASK1_BUF15TO0M_SHIFT) +#define FLEXCAN_IMASK1_BUF15TO0M(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IMASK1_BUF15TO0M_SHIFT)) & FLEXCAN_IMASK1_BUF15TO0M_MASK) + +/*! + * @brief FLEXCAN_IFLAG1 Register Bit Definition + */ + +#define FLEXCAN_IFLAG1_BUF15TO8I_SHIFT (8) +#define FLEXCAN_IFLAG1_BUF15TO8I_MASK (0xFFU << FLEXCAN_IFLAG1_BUF15TO8I_SHIFT) +#define FLEXCAN_IFLAG1_BUF15TO8I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF15TO8I_SHIFT)) & FLEXCAN_IFLAG1_BUF15TO8I_MASK) + +#define FLEXCAN_IFLAG1_BUF7I_SHIFT (7) +#define FLEXCAN_IFLAG1_BUF7I_MASK (0x01U << FLEXCAN_IFLAG1_BUF7I_SHIFT) +#define FLEXCAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF7I_SHIFT)) & FLEXCAN_IFLAG1_BUF7I_MASK) + +#define FLEXCAN_IFLAG1_BUF6I_SHIFT (6) +#define FLEXCAN_IFLAG1_BUF6I_MASK (0x01U << FLEXCAN_IFLAG1_BUF6I_SHIFT) +#define FLEXCAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF6I_SHIFT)) & FLEXCAN_IFLAG1_BUF6I_MASK) + +#define FLEXCAN_IFLAG1_BUF5I_SHIFT (5) +#define FLEXCAN_IFLAG1_BUF5I_MASK (0x01U << FLEXCAN_IFLAG1_BUF5I_SHIFT) +#define FLEXCAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF5I_SHIFT)) & FLEXCAN_IFLAG1_BUF5I_MASK) + +#define FLEXCAN_IFLAG1_BUF4TO1I_SHIFT (1) +#define FLEXCAN_IFLAG1_BUF4TO1I_MASK (0xFU << FLEXCAN_IFLAG1_BUF4TO1I_SHIFT) +#define FLEXCAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF4TO1I_SHIFT)) & FLEXCAN_IFLAG1_BUF4TO1I_MASK) + +#define FLEXCAN_IFLAG1_BUF0I_SHIFT (0) +#define FLEXCAN_IFLAG1_BUF0I_MASK (0x01U << FLEXCAN_IFLAG1_BUF0I_SHIFT) +#define FLEXCAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF0I_SHIFT)) & FLEXCAN_IFLAG1_BUF0I_MASK) + +/*! + * @brief FLEXCAN_CTRL2 Register Bit Definition + */ + +#define FLEXCAN_CTRL2_BOFFDONEMSK_SHIFT (30) +#define FLEXCAN_CTRL2_BOFFDONEMSK_MASK (0x01U << FLEXCAN_CTRL2_BOFFDONEMSK_SHIFT) +#define FLEXCAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_BOFFDONEMSK_SHIFT)) & FLEXCAN_CTRL2_BOFFDONEMSK_MASK) + +#define FLEXCAN_CTRL2_RFFN_SHIFT (24) +#define FLEXCAN_CTRL2_RFFN_MASK (0xFU << FLEXCAN_CTRL2_RFFN_SHIFT) +#define FLEXCAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_RFFN_SHIFT)) & FLEXCAN_CTRL2_RFFN_MASK) + +#define FLEXCAN_CTRL2_TASD_SHIFT (19) +#define FLEXCAN_CTRL2_TASD_MASK (0x1FU << FLEXCAN_CTRL2_TASD_SHIFT) +#define FLEXCAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_TASD_SHIFT)) & FLEXCAN_CTRL2_TASD_MASK) + +#define FLEXCAN_CTRL2_MRP_SHIFT (18) +#define FLEXCAN_CTRL2_MRP_MASK (0x01U << FLEXCAN_CTRL2_MRP_SHIFT) +#define FLEXCAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_MRP_SHIFT)) & FLEXCAN_CTRL2_MRP_MASK) + +#define FLEXCAN_CTRL2_RRS_SHIFT (17) +#define FLEXCAN_CTRL2_RRS_MASK (0x01U << FLEXCAN_CTRL2_RRS_SHIFT) +#define FLEXCAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_RRS_SHIFT)) & FLEXCAN_CTRL2_RRS_MASK) + +#define FLEXCAN_CTRL2_EACEN_SHIFT (16) +#define FLEXCAN_CTRL2_EACEN_MASK (0x01U << FLEXCAN_CTRL2_EACEN_SHIFT) +#define FLEXCAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_EACEN_SHIFT)) & FLEXCAN_CTRL2_EACEN_MASK) + +/*! + * @brief FLEXCAN_ESR2 Register Bit Definition + */ + +#define FLEXCAN_ESR2_LPTM_SHIFT (16) +#define FLEXCAN_ESR2_LPTM_MASK (0x7FU << FLEXCAN_ESR2_LPTM_SHIFT) +#define FLEXCAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR2_LPTM_SHIFT)) & FLEXCAN_ESR2_LPTM_MASK) + +#define FLEXCAN_ESR2_VPS_SHIFT (14) +#define FLEXCAN_ESR2_VPS_MASK (0x01U << FLEXCAN_ESR2_VPS_SHIFT) +#define FLEXCAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR2_VPS_SHIFT)) & FLEXCAN_ESR2_VPS_MASK) + +#define FLEXCAN_ESR2_IMB_SHIFT (13) +#define FLEXCAN_ESR2_IMB_MASK (0x01U << FLEXCAN_ESR2_IMB_SHIFT) +#define FLEXCAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR2_IMB_SHIFT)) & FLEXCAN_ESR2_IMB_MASK) + +/*! + * @brief FLEXCAN_CRCR Register Bit Definition + */ + +#define FLEXCAN_CRCR_MBCRC_SHIFT (16) +#define FLEXCAN_CRCR_MBCRC_MASK (0x7FU << FLEXCAN_CRCR_MBCRC_SHIFT) +#define FLEXCAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CRCR_MBCRC_SHIFT)) & FLEXCAN_CRCR_MBCRC_MASK) + +#define FLEXCAN_CRCR_TXCRC_SHIFT (0) +#define FLEXCAN_CRCR_TXCRC_MASK (0x7FFFU << FLEXCAN_CRCR_TXCRC_SHIFT) +#define FLEXCAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CRCR_TXCRC_SHIFT)) & FLEXCAN_CRCR_TXCRC_MASK) + +/*! + * @brief FLEXCAN_RXFGMASK Register Bit Definition + */ + +#define FLEXCAN_RXFGMASK_FGM_SHIFT (0) +#define FLEXCAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU << FLEXCAN_RXFGMASK_FGM_SHIFT) +#define FLEXCAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_FGM_SHIFT)) & FLEXCAN_RXFGMASK_FGM_MASK) + +/*! + * @brief FLEXCAN_RXFIR Register Bit Definition + */ + +#define FLEXCAN_RXFIR_IDHIT_SHIFT (0) +#define FLEXCAN_RXFIR_IDHIT_MASK (0x1FFU << FLEXCAN_RXFIR_IDHIT_SHIFT) +#define FLEXCAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFIR_IDHIT_SHIFT)) & FLEXCAN_RXFIR_IDHIT_MASK) + +/*! + * @brief FLEXCAN_CBT Register Bit Definition + */ + +#define FLEXCAN_CBT_BTF_SHIFT (31) +#define FLEXCAN_CBT_BTF_MASK (0x01U << FLEXCAN_CBT_BTF_SHIFT) +#define FLEXCAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_BTF_SHIFT)) & FLEXCAN_CBT_BTF_MASK) + +#define FLEXCAN_CBT_EPRESDIV_SHIFT (21) +#define FLEXCAN_CBT_EPRESDIV_MASK (0x3FFU << FLEXCAN_CBT_EPRESDIV_SHIFT) +#define FLEXCAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_EPRESDIV_SHIFT)) & FLEXCAN_CBT_EPRESDIV_MASK) + +#define FLEXCAN_CBT_ERJW_SHIFT (16) +#define FLEXCAN_CBT_ERJW_MASK (0x1FU << FLEXCAN_CBT_ERJW_SHIFT) +#define FLEXCAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_ERJW_SHIFT)) & FLEXCAN_CBT_ERJW_MASK) + +#define FLEXCAN_CBT_EPROPSEG_SHIFT (10) +#define FLEXCAN_CBT_EPROPSEG_MASK (0x3FU << FLEXCAN_CBT_EPROPSEG_SHIFT) +#define FLEXCAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_EPROPSEG_SHIFT)) & FLEXCAN_CBT_EPROPSEG_MASK) + +#define FLEXCAN_CBT_EPSEG1_SHIFT (5) +#define FLEXCAN_CBT_EPSEG1_MASK (0x1FU << FLEXCAN_CBT_EPSEG1_SHIFT) +#define FLEXCAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_EPSEG1_SHIFT)) & FLEXCAN_CBT_EPSEG1_MASK) + +#define FLEXCAN_CBT_EPSEG2_SHIFT (0) +#define FLEXCAN_CBT_EPSEG2_MASK (0x1FU << FLEXCAN_CBT_EPSEG2_SHIFT) +#define FLEXCAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_EPSEG2_SHIFT)) & FLEXCAN_CBT_EPSEG2_MASK) + +/*! + * @brief FLEXCAN_CS Register Bit Definition + */ + +#define FLEXCAN_CS_CODE_SHIFT (24) +#define FLEXCAN_CS_CODE_MASK (0xFU << FLEXCAN_CS_CODE_SHIFT) +#define FLEXCAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CS_CODE_SHIFT)) & FLEXCAN_CS_CODE_MASK) + +#define FLEXCAN_CS_SRR_SHIFT (22) +#define FLEXCAN_CS_SRR_MASK (0x01U << FLEXCAN_CS_SRR_SHIFT) +#define FLEXCAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CS_SRR_SHIFT)) & FLEXCAN_CS_SRR_MASK) + +#define FLEXCAN_CS_IDE_SHIFT (21) +#define FLEXCAN_CS_IDE_MASK (0x01U << FLEXCAN_CS_IDE_SHIFT) +#define FLEXCAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CS_IDE_SHIFT)) & FLEXCAN_CS_IDE_MASK) + +#define FLEXCAN_CS_RTR_SHIFT (20) +#define FLEXCAN_CS_RTR_MASK (0x01U << FLEXCAN_CS_RTR_SHIFT) +#define FLEXCAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CS_RTR_SHIFT)) & FLEXCAN_CS_RTR_MASK) + +#define FLEXCAN_CS_DLC_SHIFT (16) +#define FLEXCAN_CS_DLC_MASK (0xFU << FLEXCAN_CS_DLC_SHIFT) +#define FLEXCAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CS_DLC_SHIFT)) & FLEXCAN_CS_DLC_MASK) + +#define FLEXCAN_CS_TIMESTAMP_SHIFT (0) +#define FLEXCAN_CS_TIMESTAMP_MASK (0xFFFFU << FLEXCAN_CS_TIMESTAMP_SHIFT) +#define FLEXCAN_CS_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CS_TIMESTAMP_SHIFT)) & FLEXCAN_CS_TIMESTAMP_MASK) + +/*! + * @brief FLEXCAN_ID Register Bit Definition + */ + +#define FLEXCAN_ID_PRIO_SHIFT (29) +#define FLEXCAN_ID_PRIO_MASK (0x7U << FLEXCAN_ID_PRIO_SHIFT) +#define FLEXCAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ID_PRIO_SHIFT)) & FLEXCAN_ID_PRIO_MASK) + +#define FLEXCAN_ID_STD_SHIFT (18) +#define FLEXCAN_ID_STD_MASK (0x7FFU << FLEXCAN_ID_STD_SHIFT) +#define FLEXCAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ID_STD_SHIFT)) & FLEXCAN_ID_STD_MASK) + +#define FLEXCAN_ID_EXT_SHIFT (0) +#define FLEXCAN_ID_EXT_MASK (0x3FFFFU << FLEXCAN_ID_EXT_SHIFT) +#define FLEXCAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ID_EXT_SHIFT)) & FLEXCAN_ID_EXT_MASK) + +/*! + * @brief FLEXCAN_WORD0 Register Bit Definition + */ + +#define FLEXCAN_WORD0_BYTE0_SHIFT (24) +#define FLEXCAN_WORD0_BYTE0_MASK (0xFFU << FLEXCAN_WORD0_BYTE0_SHIFT) +#define FLEXCAN_WORD0_BYTE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_WORD0_BYTE0_SHIFT)) & FLEXCAN_WORD0_BYTE0_MASK) + +#define FLEXCAN_WORD0_BYTE1_SHIFT (16) +#define FLEXCAN_WORD0_BYTE1_MASK (0x3FU << FLEXCAN_WORD0_BYTE1_SHIFT) +#define FLEXCAN_WORD0_BYTE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_WORD0_BYTE1_SHIFT)) & FLEXCAN_WORD0_BYTE1_MASK) + +#define FLEXCAN_WORD0_BYTE2_SHIFT (8) +#define FLEXCAN_WORD0_BYTE2_MASK (0xFFU << FLEXCAN_WORD0_BYTE2_SHIFT) +#define FLEXCAN_WORD0_BYTE2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_WORD0_BYTE2_SHIFT)) & FLEXCAN_WORD0_BYTE2_MASK) + +#define FLEXCAN_WORD0_BYTE3_SHIFT (0) +#define FLEXCAN_WORD0_BYTE3_MASK (0xFFU << FLEXCAN_WORD0_BYTE3_SHIFT) +#define FLEXCAN_WORD0_BYTE3(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_WORD0_BYTE3_SHIFT)) & FLEXCAN_WORD0_BYTE3_MASK) + +/*! + * @brief FLEXCAN_WORD1 Register Bit Definition + */ + +#define FLEXCAN_WORD1_BYTE4_SHIFT (24) +#define FLEXCAN_WORD1_BYTE4_MASK (0xFFU << FLEXCAN_WORD1_BYTE4_SHIFT) +#define FLEXCAN_WORD1_BYTE4(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_WORD1_BYTE4_SHIFT)) & FLEXCAN_WORD1_BYTE4_MASK) + +#define FLEXCAN_WORD1_BYTE5_SHIFT (16) +#define FLEXCAN_WORD1_BYTE5_MASK (0x3FU << FLEXCAN_WORD1_BYTE5_SHIFT) +#define FLEXCAN_WORD1_BYTE5(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_WORD1_BYTE5_SHIFT)) & FLEXCAN_WORD1_BYTE5_MASK) + +#define FLEXCAN_WORD1_BYTE6_SHIFT (8) +#define FLEXCAN_WORD1_BYTE6_MASK (0xFFU << FLEXCAN_WORD1_BYTE6_SHIFT) +#define FLEXCAN_WORD1_BYTE6(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_WORD1_BYTE6_SHIFT)) & FLEXCAN_WORD1_BYTE6_MASK) + +#define FLEXCAN_WORD1_BYTE7_SHIFT (0) +#define FLEXCAN_WORD1_BYTE7_MASK (0xFFU << FLEXCAN_WORD1_BYTE7_SHIFT) +#define FLEXCAN_WORD1_BYTE7(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_WORD1_BYTE7_SHIFT)) & FLEXCAN_WORD1_BYTE7_MASK) + +/*! + * @brief FLEXCAN_RXIMRN Register Bit Definition + */ + +#define FLEXCAN_RXIMRN_MI_SHIFT (0) +#define FLEXCAN_RXIMRN_MI_MASK (0xFFFFFFFFU << FLEXCAN_RXIMRN_MI_SHIFT) +#define FLEXCAN_RXIMRN_MI(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXIMRN_MI_SHIFT)) & FLEXCAN_RXIMRN_MI_MASK) + +/*! + * @} + */ /* end of group FLEXCAN_Register_Masks */ +/****************************************************************************** + *FLEXCAN Instance +*******************************************************************************/ + +#define FLEXCAN1 ((FLEXCAN_Type*)FLEXCAN1_BASE) +#define FLEXCAN2 ((FLEXCAN_Type*)FLEXCAN2_BASE) + +/*! + * @} + */ /* end of group FLEXCAN_Peripheral_Access_Layer */ + + + + +/*! + * @addtogroup FSMC_Peripheral_Access_Layer FSMC Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * FSMC Type + ******************************************************************************/ +#define FSMC_SMTMGR_REG_NUM 3u /*!< the number of FSMC SMTMGR. */ +typedef struct { + __IO uint32_t Reserved37[21]; ///< Reserved + __IO uint32_t SMSKR[4]; ///< Memory mask register offset: 0x54 + __IO uint32_t Reserved38[12]; ///< Reserved + __IO uint32_t SMTMGRSET[FSMC_SMTMGR_REG_NUM]; ///< Memory timing register 0 offset: 0x94 + __IO uint32_t Reserved39[1]; ///< Reserved + __IO uint32_t SMCTLR; ///< Memory control register offset: 0xA4 +} FSMC_Type; + +/******************************************************************************* + * FSMC Type + ******************************************************************************/ + +/*! + * @addtogroup FSMC_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief FSMC_SMSKR Register Bit Definition + */ + +#define FSMC_SMSKR_REGSELECT_SHIFT (8) +#define FSMC_SMSKR_REGSELECT_MASK (0x7U << FSMC_SMSKR_REGSELECT_SHIFT) +#define FSMC_SMSKR_REGSELECT(x) (((uint32_t)(((uint32_t)(x)) << FSMC_SMSKR_REGSELECT_SHIFT)) & FSMC_SMSKR_REGSELECT_MASK) + +#define FSMC_SMSKR_MEMTYPE_SHIFT (5) +#define FSMC_SMSKR_MEMTYPE_MASK (0x7U << FSMC_SMSKR_MEMTYPE_SHIFT) +#define FSMC_SMSKR_MEMTYPE(x) (((uint32_t)(((uint32_t)(x)) << FSMC_SMSKR_MEMTYPE_SHIFT)) & FSMC_SMSKR_MEMTYPE_MASK) + +#define FSMC_SMSKR_MEMSIZE_SHIFT (0) +#define FSMC_SMSKR_MEMSIZE_MASK (0x1FU << FSMC_SMSKR_MEMSIZE_SHIFT) +#define FSMC_SMSKR_MEMSIZE(x) (((uint32_t)(((uint32_t)(x)) << FSMC_SMSKR_MEMSIZE_SHIFT)) & FSMC_SMSKR_MEMSIZE_MASK) + +/*! + * @brief FSMC_SMTMGRSET Register Bit Definition + */ + +#define FSMC_SMTMGRSET_SMREADPIPE_SHIFT (28) +#define FSMC_SMTMGRSET_SMREADPIPE_MASK (0x3U << FSMC_SMTMGRSET_SMREADPIPE_SHIFT) +#define FSMC_SMTMGRSET_SMREADPIPE(x) (((uint32_t)(((uint32_t)(x)) << FSMC_SMTMGRSET_SMREADPIPE_SHIFT)) & FSMC_SMTMGRSET_SMREADPIPE_MASK) + +#define FSMC_SMTMGRSET_READYMODE_SHIFT (26) +#define FSMC_SMTMGRSET_READYMODE_MASK (0x01U << FSMC_SMTMGRSET_READYMODE_SHIFT) +#define FSMC_SMTMGRSET_READYMODE(x) (((uint32_t)(((uint32_t)(x)) << FSMC_SMTMGRSET_READYMODE_SHIFT)) & FSMC_SMTMGRSET_READYMODE_MASK) + +#define FSMC_SMTMGRSET_TWP_SHIFT (10) +#define FSMC_SMTMGRSET_TWP_MASK (0x3FU << FSMC_SMTMGRSET_TWP_SHIFT) +#define FSMC_SMTMGRSET_TWP(x) (((uint32_t)(((uint32_t)(x)) << FSMC_SMTMGRSET_TWP_SHIFT)) & FSMC_SMTMGRSET_TWP_MASK) + +#define FSMC_SMTMGRSET_TWR_SHIFT (8) +#define FSMC_SMTMGRSET_TWR_MASK (0x3U << FSMC_SMTMGRSET_TWR_SHIFT) +#define FSMC_SMTMGRSET_TWR(x) (((uint32_t)(((uint32_t)(x)) << FSMC_SMTMGRSET_TWR_SHIFT)) & FSMC_SMTMGRSET_TWR_MASK) + +#define FSMC_SMTMGRSET_TAS_SHIFT (6) +#define FSMC_SMTMGRSET_TAS_MASK (0x3U << FSMC_SMTMGRSET_TAS_SHIFT) +#define FSMC_SMTMGRSET_TAS(x) (((uint32_t)(((uint32_t)(x)) << FSMC_SMTMGRSET_TAS_SHIFT)) & FSMC_SMTMGRSET_TAS_MASK) + +#define FSMC_SMTMGRSET_TRC_SHIFT (0) +#define FSMC_SMTMGRSET_TRC_MASK (0x3FU << FSMC_SMTMGRSET_TRC_SHIFT) +#define FSMC_SMTMGRSET_TRC(x) (((uint32_t)(((uint32_t)(x)) << FSMC_SMTMGRSET_TRC_SHIFT)) & FSMC_SMTMGRSET_TRC_MASK) + + +/*! + * @brief FSMC_SMCTLR Register Bit Definition + */ + +#define FSMC_SMCTLR_SMDW2_SHIFT (13) +#define FSMC_SMCTLR_SMDW2_MASK (0x7U << FSMC_SMCTLR_SMDW2_SHIFT) +#define FSMC_SMCTLR_SMDW2(x) (((uint32_t)(((uint32_t)(x)) << FSMC_SMCTLR_SMDW2_SHIFT)) & FSMC_SMCTLR_SMDW2_MASK) + +#define FSMC_SMCTLR_SMDW1_SHIFT (10) +#define FSMC_SMCTLR_SMDW1_MASK (0x7U << FSMC_SMCTLR_SMDW1_SHIFT) +#define FSMC_SMCTLR_SMDW1(x) (((uint32_t)(((uint32_t)(x)) << FSMC_SMCTLR_SMDW1_SHIFT)) & FSMC_SMCTLR_SMDW1_MASK) + +#define FSMC_SMCTLR_SMDW_SHIFT (7) +#define FSMC_SMCTLR_SMDW_MASK (0x7U << FSMC_SMCTLR_SMDW_SHIFT) +#define FSMC_SMCTLR_SMDW(x) (((uint32_t)(((uint32_t)(x)) << FSMC_SMCTLR_SMDW_SHIFT)) & FSMC_SMCTLR_SMDW_MASK) + +#define FSMC_SMCTLR_FLASHRP_SHIFT (0) +#define FSMC_SMCTLR_FLASHRP_MASK (0x01U << FSMC_SMCTLR_FLASHRP_SHIFT) +#define FSMC_SMCTLR_FLASHRP(x) (((uint32_t)(((uint32_t)(x)) << FSMC_SMCTLR_FLASHRP_SHIFT)) & FSMC_SMCTLR_FLASHRP_MASK) + +/*! + * @} + */ /* end of group FSMC_Register_Masks */ +/****************************************************************************** + * FSMC Instance +******************************************************************************/ +#define FSMC ((FSMC_Type*)FSMC_BASE) + +/*! + * @} + */ /* end of group FSMC_Peripheral_Access_Layer */ + + + + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * GPIO Type + ******************************************************************************/ +typedef struct { + __IO uint32_t CRL; ///< Port Configuration Low Register offset: 0x00 + __IO uint32_t CRH; ///< Port Configuration High Register offset: 0x04 + __IO uint32_t IDR; ///< Port Input Data Register offset: 0x08 + __IO uint32_t ODR; ///< PORT OUTPUT DATA REGISTER offset: 0x0C + __IO uint32_t BSRR; ///< Port Set/Clear Register offset: 0x10 + __IO uint32_t BRR; ///< Port Bit Clear Register offset: 0x14 + __IO uint32_t LCKR; ///< Port Configuration Lock Register offset: 0x18 + __IO uint32_t DCR; ///< PORT OUTPUT OPEN DRAIN CONTROL REGISTER offset: 0x1C + __IO uint32_t AFRL; ///< Port alternate function low-order register offset: 0x20 + __IO uint32_t AFRH; ///< Port alternate function high-order register offset: 0x24 +} GPIO_Type; + +/******************************************************************************* + * GPIO Type + ******************************************************************************/ + +/*! + * @addtogroup GPIO_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief GPIO_CRL Register Bit Definition + */ + +#define GPIO_CRL_CNF7_SHIFT (30) +#define GPIO_CRL_CNF7_MASK (0x3U << GPIO_CRL_CNF7_SHIFT) +#define GPIO_CRL_CNF7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRL_CNF7_SHIFT)) & GPIO_CRL_CNF7_MASK) + +#define GPIO_CRL_CNF6_SHIFT (26) +#define GPIO_CRL_CNF6_MASK (0x3U << GPIO_CRL_CNF6_SHIFT) +#define GPIO_CRL_CNF6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRL_CNF6_SHIFT)) & GPIO_CRL_CNF6_MASK) + +#define GPIO_CRL_CNF5_SHIFT (22) +#define GPIO_CRL_CNF5_MASK (0x3U << GPIO_CRL_CNF5_SHIFT) +#define GPIO_CRL_CNF5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRL_CNF5_SHIFT)) & GPIO_CRL_CNF5_MASK) + +#define GPIO_CRL_CNF4_SHIFT (18) +#define GPIO_CRL_CNF4_MASK (0x3U << GPIO_CRL_CNF4_SHIFT) +#define GPIO_CRL_CNF4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRL_CNF4_SHIFT)) & GPIO_CRL_CNF4_MASK) + +#define GPIO_CRL_CNF3_SHIFT (14) +#define GPIO_CRL_CNF3_MASK (0x3U << GPIO_CRL_CNF3_SHIFT) +#define GPIO_CRL_CNF3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRL_CNF3_SHIFT)) & GPIO_CRL_CNF3_MASK) + +#define GPIO_CRL_CNF2_SHIFT (10) +#define GPIO_CRL_CNF2_MASK (0x3U << GPIO_CRL_CNF2_SHIFT) +#define GPIO_CRL_CNF2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRL_CNF2_SHIFT)) & GPIO_CRL_CNF2_MASK) + +#define GPIO_CRL_CNF1_SHIFT (6) +#define GPIO_CRL_CNF1_MASK (0x3U << GPIO_CRL_CNF1_SHIFT) +#define GPIO_CRL_CNF1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRL_CNF1_SHIFT)) & GPIO_CRL_CNF1_MASK) + +#define GPIO_CRL_CNF0_SHIFT (2) +#define GPIO_CRL_CNF0_MASK (0x3U << GPIO_CRL_CNF0_SHIFT) +#define GPIO_CRL_CNF0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRL_CNF0_SHIFT)) & GPIO_CRL_CNF0_MASK) + +#define GPIO_CRL_MODE7_SHIFT (28) +#define GPIO_CRL_MODE7_MASK (0x3U << GPIO_CRL_MODE7_SHIFT) +#define GPIO_CRL_MODE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRL_MODE7_SHIFT)) & GPIO_CRL_MODE7_MASK) + +#define GPIO_CRL_MODE6_SHIFT (24) +#define GPIO_CRL_MODE6_MASK (0x3U << GPIO_CRL_MODE6_SHIFT) +#define GPIO_CRL_MODE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRL_MODE6_SHIFT)) & GPIO_CRL_MODE6_MASK) + +#define GPIO_CRL_MODE5_SHIFT (20) +#define GPIO_CRL_MODE5_MASK (0x3U << GPIO_CRL_MODE5_SHIFT) +#define GPIO_CRL_MODE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRL_MODE5_SHIFT)) & GPIO_CRL_MODE5_MASK) + +#define GPIO_CRL_MODE4_SHIFT (16) +#define GPIO_CRL_MODE4_MASK (0x3U << GPIO_CRL_MODE4_SHIFT) +#define GPIO_CRL_MODE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRL_MODE4_SHIFT)) & GPIO_CRL_MODE4_MASK) + +#define GPIO_CRL_MODE3_SHIFT (12) +#define GPIO_CRL_MODE3_MASK (0x3U << GPIO_CRL_MODE3_SHIFT) +#define GPIO_CRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRL_MODE3_SHIFT)) & GPIO_CRL_MODE3_MASK) + +#define GPIO_CRL_MODE2_SHIFT (8) +#define GPIO_CRL_MODE2_MASK (0x3U << GPIO_CRL_MODE2_SHIFT) +#define GPIO_CRL_MODE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRL_MODE2_SHIFT)) & GPIO_CRL_MODE2_MASK) + +#define GPIO_CRL_MODE1_SHIFT (4) +#define GPIO_CRL_MODE1_MASK (0x3U << GPIO_CRL_MODE1_SHIFT) +#define GPIO_CRL_MODE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRL_MODE1_SHIFT)) & GPIO_CRL_MODE1_MASK) + +#define GPIO_CRL_MODE0_SHIFT (0) +#define GPIO_CRL_MODE0_MASK (0x3U << GPIO_CRL_MODE0_SHIFT) +#define GPIO_CRL_MODE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRL_MODE0_SHIFT)) & GPIO_CRL_MODE0_MASK) + +/*! + * @brief GPIO_CRH Register Bit Definition + */ + +#define GPIO_CRH_CNF15_SHIFT (30) +#define GPIO_CRH_CNF15_MASK (0x3U << GPIO_CRH_CNF15_SHIFT) +#define GPIO_CRH_CNF15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRH_CNF15_SHIFT)) & GPIO_CRH_CNF15_MASK) + +#define GPIO_CRH_CNF14_SHIFT (26) +#define GPIO_CRH_CNF14_MASK (0x3U << GPIO_CRH_CNF14_SHIFT) +#define GPIO_CRH_CNF14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRH_CNF14_SHIFT)) & GPIO_CRH_CNF14_MASK) + +#define GPIO_CRH_CNF13_SHIFT (22) +#define GPIO_CRH_CNF13_MASK (0x3U << GPIO_CRH_CNF13_SHIFT) +#define GPIO_CRH_CNF13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRH_CNF13_SHIFT)) & GPIO_CRH_CNF13_MASK) + +#define GPIO_CRH_CNF12_SHIFT (18) +#define GPIO_CRH_CNF12_MASK (0x3U << GPIO_CRH_CNF12_SHIFT) +#define GPIO_CRH_CNF12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRH_CNF12_SHIFT)) & GPIO_CRH_CNF12_MASK) + +#define GPIO_CRH_CNF11_SHIFT (14) +#define GPIO_CRH_CNF11_MASK (0x3U << GPIO_CRH_CNF11_SHIFT) +#define GPIO_CRH_CNF11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRH_CNF11_SHIFT)) & GPIO_CRH_CNF11_MASK) + +#define GPIO_CRH_CNF10_SHIFT (10) +#define GPIO_CRH_CNF10_MASK (0x3U << GPIO_CRH_CNF10_SHIFT) +#define GPIO_CRH_CNF10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRH_CNF10_SHIFT)) & GPIO_CRH_CNF10_MASK) + +#define GPIO_CRH_CNF9_SHIFT (6) +#define GPIO_CRH_CNF9_MASK (0x3U << GPIO_CRH_CNF9_SHIFT) +#define GPIO_CRH_CNF9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRH_CNF9_SHIFT)) & GPIO_CRH_CNF9_MASK) + +#define GPIO_CRH_CNF8_SHIFT (2) +#define GPIO_CRH_CNF8_MASK (0x3U << GPIO_CRH_CNF8_SHIFT) +#define GPIO_CRH_CNF8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRH_CNF8_SHIFT)) & GPIO_CRH_CNF8_MASK) + +#define GPIO_CRH_MODE15_SHIFT (28) +#define GPIO_CRH_MODE15_MASK (0x3U << GPIO_CRH_MODE15_SHIFT) +#define GPIO_CRH_MODE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRH_MODE15_SHIFT)) & GPIO_CRH_MODE15_MASK) + +#define GPIO_CRH_MODE14_SHIFT (24) +#define GPIO_CRH_MODE14_MASK (0x3U << GPIO_CRH_MODE14_SHIFT) +#define GPIO_CRH_MODE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRH_MODE14_SHIFT)) & GPIO_CRH_MODE14_MASK) + +#define GPIO_CRH_MODE13_SHIFT (20) +#define GPIO_CRH_MODE13_MASK (0x3U << GPIO_CRH_MODE13_SHIFT) +#define GPIO_CRH_MODE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRH_MODE13_SHIFT)) & GPIO_CRH_MODE13_MASK) + +#define GPIO_CRH_MODE12_SHIFT (16) +#define GPIO_CRH_MODE12_MASK (0x3U << GPIO_CRH_MODE12_SHIFT) +#define GPIO_CRH_MODE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRH_MODE12_SHIFT)) & GPIO_CRH_MODE12_MASK) + +#define GPIO_CRH_MODE11_SHIFT (12) +#define GPIO_CRH_MODE11_MASK (0x3U << GPIO_CRH_MODE11_SHIFT) +#define GPIO_CRH_MODE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRH_MODE11_SHIFT)) & GPIO_CRH_MODE11_MASK) + +#define GPIO_CRH_MODE10_SHIFT (8) +#define GPIO_CRH_MODE10_MASK (0x3U << GPIO_CRH_MODE10_SHIFT) +#define GPIO_CRH_MODE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRH_MODE10_SHIFT)) & GPIO_CRH_MODE10_MASK) + +#define GPIO_CRH_MODE9_SHIFT (4) +#define GPIO_CRH_MODE9_MASK (0x3U << GPIO_CRH_MODE9_SHIFT) +#define GPIO_CRH_MODE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRH_MODE9_SHIFT)) & GPIO_CRH_MODE9_MASK) + +#define GPIO_CRH_MODE8_SHIFT (0) +#define GPIO_CRH_MODE8_MASK (0x3U << GPIO_CRH_MODE8_SHIFT) +#define GPIO_CRH_MODE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CRH_MODE8_SHIFT)) & GPIO_CRH_MODE8_MASK) + +/*! + * @brief GPIO_IDR Register Bit Definition + */ + +#define GPIO_IDR_IDRY_SHIFT (0) +#define GPIO_IDR_IDRY_MASK (0xFFFFU << GPIO_IDR_IDRY_SHIFT) +#define GPIO_IDR_IDRY(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IDR_IDRY_SHIFT)) & GPIO_IDR_IDRY_MASK) + +/*! + * @brief GPIO_ODR Register Bit Definition + */ + +#define GPIO_ODR_ODRY_SHIFT (0) +#define GPIO_ODR_ODRY_MASK (0xFFFFU << GPIO_ODR_ODRY_SHIFT) +#define GPIO_ODR_ODRY(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ODR_ODRY_SHIFT)) & GPIO_ODR_ODRY_MASK) + +/*! + * @brief GPIO_BSRR Register Bit Definition + */ + +#define GPIO_BSRR_BRY_SHIFT (16) +#define GPIO_BSRR_BRY_MASK (0xFFFFU << GPIO_BSRR_BRY_SHIFT) +#define GPIO_BSRR_BRY(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BSRR_BRY_SHIFT)) & GPIO_BSRR_BRY_MASK) + +#define GPIO_BSRR_BSY_SHIFT (0) +#define GPIO_BSRR_BSY_MASK (0xFFFFU << GPIO_BSRR_BSY_SHIFT) +#define GPIO_BSRR_BSY(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BSRR_BSY_SHIFT)) & GPIO_BSRR_BSY_MASK) + +/*! + * @brief GPIO_BRR Register Bit Definition + */ + +#define GPIO_BRR_BRY_SHIFT (0) +#define GPIO_BRR_BRY_MASK (0xFFFFU << GPIO_BRR_BRY_SHIFT) +#define GPIO_BRR_BRY(x) (((uint32_t)(((uint32_t)(x)) << GPIO_BRR_BRY_SHIFT)) & GPIO_BRR_BRY_MASK) + +/*! + * @brief GPIO_LCKR Register Bit Definition + */ + +#define GPIO_LCKR_PX15PX1_SHIFT (2) +#define GPIO_LCKR_PX15PX1_MASK (0x3FFFFFFFU << GPIO_LCKR_PX15PX1_SHIFT) +#define GPIO_LCKR_PX15PX1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LCKR_PX15PX1_SHIFT)) & GPIO_LCKR_PX15PX1_MASK) + +#define GPIO_LCKR_LCKK_SHIFT (16) +#define GPIO_LCKR_LCKK_MASK (0x01U << GPIO_LCKR_LCKK_SHIFT) +#define GPIO_LCKR_LCKK(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LCKR_LCKK_SHIFT)) & GPIO_LCKR_LCKK_MASK) + +#define GPIO_LCKR_LCK_SHIFT (0) +#define GPIO_LCKR_LCK_MASK (0xFFFFU << GPIO_LCKR_LCK_SHIFT) +#define GPIO_LCKR_LCK(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LCKR_LCK_SHIFT)) & GPIO_LCKR_LCK_MASK) + +/*! + * @brief GPIO_DCR Register Bit Definition + */ + +#define GPIO_DCR_PX15PX1_SHIFT (2) +#define GPIO_DCR_PX15PX1_MASK (0x3FFFFFFFU << GPIO_DCR_PX15PX1_SHIFT) +#define GPIO_DCR_PX15PX1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DCR_PX15PX1_SHIFT)) & GPIO_DCR_PX15PX1_MASK) + +#define GPIO_DCR_PX0_SHIFT (0) +#define GPIO_DCR_PX0_MASK (0x3U << GPIO_DCR_PX0_SHIFT) +#define GPIO_DCR_PX0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DCR_PX0_SHIFT)) & GPIO_DCR_PX0_MASK) + +/*! + * @brief GPIO_AFRL Register Bit Definition + */ + +#define GPIO_AFRL_AFRY_SHIFT (0) +#define GPIO_AFRL_AFRY_MASK (0xFFFFFFFFU << GPIO_AFRL_AFRY_SHIFT) +#define GPIO_AFRL_AFRY(x) (((uint32_t)(((uint32_t)(x)) << GPIO_AFRL_AFRY_SHIFT)) & GPIO_AFRL_AFRY_MASK) + +/*! + * @brief GPIO_AFRH Register Bit Definition + */ + +#define GPIO_AFRH_AFRY_SHIFT (0) +#define GPIO_AFRH_AFRY_MASK (0xFFFFFFFFU << GPIO_AFRH_AFRY_SHIFT) +#define GPIO_AFRH_AFRY(x) (((uint32_t)(((uint32_t)(x)) << GPIO_AFRH_AFRY_SHIFT)) & GPIO_AFRH_AFRY_MASK) + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ +/****************************************************************************** + *GPIO Instance +*******************************************************************************/ + +#define GPIOA ((GPIO_Type*)GPIOA_BASE) +#define GPIOB ((GPIO_Type*)GPIOB_BASE) +#define GPIOC ((GPIO_Type*)GPIOC_BASE) +#define GPIOD ((GPIO_Type*)GPIOD_BASE) +#define GPIOE ((GPIO_Type*)GPIOE_BASE) +#define GPIOF ((GPIO_Type*)GPIOF_BASE) +#define GPIOG ((GPIO_Type*)GPIOG_BASE) +#define GPIOH ((GPIO_Type*)GPIOH_BASE) +#define GPIOI ((GPIO_Type*)GPIOI_BASE) + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + + + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * I2C Type + ******************************************************************************/ +typedef struct { + __IO uint32_t CR; ///< control register offset: 0x00 + __IO uint32_t TAR; ///< target address register offset: 0x04 + __IO uint32_t SAR; ///< slave address register offset: 0x08 + __IO uint32_t Reserved0[1]; ///< Reserved + __IO uint32_t DR; ///< Data Command Register offset: 0x10 + __IO uint32_t SSHR; ///< Standard Mode Clock High Count Register offset: 0x14 + __IO uint32_t SSLR; ///< Standard Mode Clock Low Count Register offset: 0x18 + __IO uint32_t FSHR; ///< Fast/Super Fast Mode Clock High Count Registeroffset: 0x1C + __IO uint32_t FSLR; ///< Fast/Super Fast Mode Clock Low Count Registeroffset: 0x20 + __IO uint32_t Reserved1[2]; ///< Reserved + __IO uint32_t ISR; ///< Interrupt Status Register offset: 0x2C + __IO uint32_t IMR; ///< interrupt mask register offset: 0x30 + __IO uint32_t RAWISR; ///< RAW interrupt register offset: 0x34 + __IO uint32_t RXTLR; ///< receive threshold register offset: 0x38 + __IO uint32_t TXTLR; ///< Transmit Threshold Register offset: 0x3C + __IO uint32_t ICR; ///< Combined and Independent Interrupt Clear Registersoffset: 0x40 + __IO uint32_t RXUNDER; ///< Clear the RX_UNDER interrupt register offset: 0x44 + __IO uint32_t RXOVER; ///< Clear the RX_OVER interrupt register offset: 0x48 + __IO uint32_t TXOVER; ///< Clear the TX_OVER interrupt register offset: 0x4C + __IO uint32_t RDREQ; ///< Clear the RD_REQ interrupt register offset: 0x50 + __IO uint32_t TXABRT; ///< Clear the TX_ABRT interrupt register offset: 0x54 + __IO uint32_t RXDONE; ///< Clear the RX_DONE interrupt register offset: 0x58 + __IO uint32_t ACTIV; ///< Clear the ACTIVITY interrupt register offset: 0x5C + __IO uint32_t STOP; ///< Clear the STOP_DET interrupt register offset: 0x60 + __IO uint32_t START; ///< Clear the START_DET interrupt register offset: 0x64 + __IO uint32_t GC; ///< Clear the GEN_CALL interrupt register offset: 0x68 + __IO uint32_t ENR; ///< enable register offset: 0x6C + __IO uint32_t SR; ///< status register offset: 0x70 + __IO uint32_t TXFLR; ///< Transmit buffer level register offset: 0x74 + __IO uint32_t RXFLR; ///< Receive buffer level register offset: 0x78 + __IO uint32_t HOLD; ///< SDA hold time register offset: 0x7C + __IO uint32_t TXABRTSRC; ///< Transfer Abort Source Register offset: 0x80 + __IO uint32_t SLVNACK; ///< Slave Receive NACK Register offset: 0x84 + __IO uint32_t DMA; ///< DMA Control Register offset: 0x88 + __IO uint32_t Reserved2[2]; ///< Reserved + __IO uint32_t SETUP; ///< SDA setup time register offset: 0x94 + __IO uint32_t GCR; ///< General Call ACK Register offset: 0x98 + __IO uint32_t ENSR; ///< ENABLE Status Register offset: 0x9C + __IO uint32_t SPKLEN; ///< filter register offset: 0xA0 + __IO uint32_t Reserved3[2]; ///< Reserved + __IO uint32_t SCLTMO; ///< SCL Low Timeout Register offset: 0xAC + __IO uint32_t SDATMO; ///< SDA Low Timeout Register offset: 0xB0 + __IO uint32_t SCLSTUCK; ///< Clear the SCL_STUCK interrupt register offset: 0xB4 + __IO uint32_t Reserved4[1]; ///< Reserved + __IO uint32_t SMBSEXT; ///< SMBus Slave Clock Stretching Timeout Registeroffset: 0xBC + __IO uint32_t SMBMEXT; ///< SMBus Master Clock Stretching Timeout Registeroffset: 0xC0 + __IO uint32_t SMBIDLE; ///< SMBus Bus Idle Count Register offset: 0xC4 + __IO uint32_t SMBISR; ///< SMBus Interrupt Status Register offset: 0xC8 + __IO uint32_t SMBIMR; ///< SMBus Interrupt Mask Register offset: 0xCC + __IO uint32_t SMBRAWISR; ///< SMBus RAW Interrupt Register offset: 0xD0 + __IO uint32_t SMBICR; ///< SMBus Combined and Independent Interrupt Clear Registersoffset: 0xD4 + __IO uint32_t OPTSAR; ///< Optional Slave Address Register offset: 0xD8 + __IO uint32_t SMBUDIDLSB; ///< SMBus UDID LSB Register offset: 0xDC + __IO uint32_t SMBUDIDMSB0; ///< SMBus UDID MSB Register 0 offset: 0XE0 + __IO uint32_t SMBUDIDMSB1; ///< SMBus UDID MSB Register 1 offset: 0XE4 + __IO uint32_t SMBUDIDMSB2; ///< SMBus UDID MSB Register 2 offset: 0xE8 + __IO uint32_t SLVMASK; ///< Slave Address Mask Register offset: 0xEC + __IO uint32_t SLVRCVADDR; ///< Slave Receive Address Register offset: 0xF0 +} I2C_Type; + +/******************************************************************************* + * I2C Type + ******************************************************************************/ + +/*! + * @addtogroup I2C_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief I2C_CR Register Bit Definition + */ + +#define I2C_CR_RXFULLHLD_SHIFT (22) +#define I2C_CR_RXFULLHLD_MASK (0x01U << I2C_CR_RXFULLHLD_SHIFT) +#define I2C_CR_RXFULLHLD(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_RXFULLHLD_SHIFT)) & I2C_CR_RXFULLHLD_MASK) + +#define I2C_CR_BUSCLR_SHIFT (21) +#define I2C_CR_BUSCLR_MASK (0x01U << I2C_CR_BUSCLR_SHIFT) +#define I2C_CR_BUSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_BUSCLR_SHIFT)) & I2C_CR_BUSCLR_MASK) + +#define I2C_CR_STOPDETMSTACT_SHIFT (20) +#define I2C_CR_STOPDETMSTACT_MASK (0x01U << I2C_CR_STOPDETMSTACT_SHIFT) +#define I2C_CR_STOPDETMSTACT(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_STOPDETMSTACT_SHIFT)) & I2C_CR_STOPDETMSTACT_MASK) + +#define I2C_CR_SMBPSAEN_SHIFT (19) +#define I2C_CR_SMBPSAEN_MASK (0x01U << I2C_CR_SMBPSAEN_SHIFT) +#define I2C_CR_SMBPSAEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_SMBPSAEN_SHIFT)) & I2C_CR_SMBPSAEN_MASK) + +#define I2C_CR_SMBARPEN_SHIFT (18) +#define I2C_CR_SMBARPEN_MASK (0x01U << I2C_CR_SMBARPEN_SHIFT) +#define I2C_CR_SMBARPEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_SMBARPEN_SHIFT)) & I2C_CR_SMBARPEN_MASK) + +#define I2C_CR_SMBSLVQCEN_SHIFT (17) +#define I2C_CR_SMBSLVQCEN_MASK (0x01U << I2C_CR_SMBSLVQCEN_SHIFT) +#define I2C_CR_SMBSLVQCEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_SMBSLVQCEN_SHIFT)) & I2C_CR_SMBSLVQCEN_MASK) + +#define I2C_CR_OPTSAREN_SHIFT (16) +#define I2C_CR_OPTSAREN_MASK (0x01U << I2C_CR_OPTSAREN_SHIFT) +#define I2C_CR_OPTSAREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_OPTSAREN_SHIFT)) & I2C_CR_OPTSAREN_MASK) + +#define I2C_CR_PADSEL_SHIFT (12) +#define I2C_CR_PADSEL_MASK (0x01U << I2C_CR_PADSEL_SHIFT) +#define I2C_CR_PADSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_PADSEL_SHIFT)) & I2C_CR_PADSEL_MASK) + +#define I2C_CR_SLVTXABRTDIS_SHIFT (11) +#define I2C_CR_SLVTXABRTDIS_MASK (0x01U << I2C_CR_SLVTXABRTDIS_SHIFT) +#define I2C_CR_SLVTXABRTDIS(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_SLVTXABRTDIS_SHIFT)) & I2C_CR_SLVTXABRTDIS_MASK) + +#define I2C_CR_RESTART_SHIFT (10) +#define I2C_CR_RESTART_MASK (0x01U << I2C_CR_RESTART_SHIFT) +#define I2C_CR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_RESTART_SHIFT)) & I2C_CR_RESTART_MASK) + +#define I2C_CR_STOP_SHIFT (9) +#define I2C_CR_STOP_MASK (0x01U << I2C_CR_STOP_SHIFT) +#define I2C_CR_STOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_STOP_SHIFT)) & I2C_CR_STOP_MASK) + +#define I2C_CR_EMPINT_SHIFT (8) +#define I2C_CR_EMPINT_MASK (0x01U << I2C_CR_EMPINT_SHIFT) +#define I2C_CR_EMPINT(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_EMPINT_SHIFT)) & I2C_CR_EMPINT_MASK) + +#define I2C_CR_STOPINT_SHIFT (7) +#define I2C_CR_STOPINT_MASK (0x01U << I2C_CR_STOPINT_SHIFT) +#define I2C_CR_STOPINT(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_STOPINT_SHIFT)) & I2C_CR_STOPINT_MASK) + +#define I2C_CR_DISSLAVE_SHIFT (6) +#define I2C_CR_DISSLAVE_MASK (0x01U << I2C_CR_DISSLAVE_SHIFT) +#define I2C_CR_DISSLAVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_DISSLAVE_SHIFT)) & I2C_CR_DISSLAVE_MASK) + +#define I2C_CR_REPEN_SHIFT (5) +#define I2C_CR_REPEN_MASK (0x01U << I2C_CR_REPEN_SHIFT) +#define I2C_CR_REPEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_REPEN_SHIFT)) & I2C_CR_REPEN_MASK) + +#define I2C_CR_MASTER10_SHIFT (4) +#define I2C_CR_MASTER10_MASK (0x01U << I2C_CR_MASTER10_SHIFT) +#define I2C_CR_MASTER10(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_MASTER10_SHIFT)) & I2C_CR_MASTER10_MASK) + +#define I2C_CR_SLAVE10_SHIFT (3) +#define I2C_CR_SLAVE10_MASK (0x01U << I2C_CR_SLAVE10_SHIFT) +#define I2C_CR_SLAVE10(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_SLAVE10_SHIFT)) & I2C_CR_SLAVE10_MASK) + +#define I2C_CR_SPEED_SHIFT (1) +#define I2C_CR_SPEED_MASK (0x3U << I2C_CR_SPEED_SHIFT) +#define I2C_CR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_SPEED_SHIFT)) & I2C_CR_SPEED_MASK) + +#define I2C_CR_MASTER_SHIFT (0) +#define I2C_CR_MASTER_MASK (0x01U << I2C_CR_MASTER_SHIFT) +#define I2C_CR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << I2C_CR_MASTER_SHIFT)) & I2C_CR_MASTER_MASK) + +/*! + * @brief I2C_TAR Register Bit Definition + */ + +#define I2C_TAR_SMBQC_SHIFT (16) +#define I2C_TAR_SMBQC_MASK (0x01U << I2C_TAR_SMBQC_SHIFT) +#define I2C_TAR_SMBQC(x) (((uint32_t)(((uint32_t)(x)) << I2C_TAR_SMBQC_SHIFT)) & I2C_TAR_SMBQC_MASK) + +#define I2C_TAR_SPECIAL_SHIFT (11) +#define I2C_TAR_SPECIAL_MASK (0x01U << I2C_TAR_SPECIAL_SHIFT) +#define I2C_TAR_SPECIAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_TAR_SPECIAL_SHIFT)) & I2C_TAR_SPECIAL_MASK) + +#define I2C_TAR_GC_SHIFT (10) +#define I2C_TAR_GC_MASK (0x01U << I2C_TAR_GC_SHIFT) +#define I2C_TAR_GC(x) (((uint32_t)(((uint32_t)(x)) << I2C_TAR_GC_SHIFT)) & I2C_TAR_GC_MASK) + +#define I2C_TAR_ADDR_SHIFT (0) +#define I2C_TAR_ADDR_MASK (0x3FFU << I2C_TAR_ADDR_SHIFT) +#define I2C_TAR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I2C_TAR_ADDR_SHIFT)) & I2C_TAR_ADDR_MASK) + +/*! + * @brief I2C_SAR Register Bit Definition + */ + +#define I2C_SAR_ADDR_SHIFT (0) +#define I2C_SAR_ADDR_MASK (0x3FFU << I2C_SAR_ADDR_SHIFT) +#define I2C_SAR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SAR_ADDR_SHIFT)) & I2C_SAR_ADDR_MASK) + +/*! + * @brief I2C_DR Register Bit Definition + */ + +#define I2C_DR_FIRSTDATA_SHIFT (11) +#define I2C_DR_FIRSTDATA_MASK (0x01U << I2C_DR_FIRSTDATA_SHIFT) +#define I2C_DR_FIRSTDATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_DR_FIRSTDATA_SHIFT)) & I2C_DR_FIRSTDATA_MASK) + +#define I2C_DR_CMD_SHIFT (8) +#define I2C_DR_CMD_MASK (0x01U << I2C_DR_CMD_SHIFT) +#define I2C_DR_CMD(x) (((uint32_t)(((uint32_t)(x)) << I2C_DR_CMD_SHIFT)) & I2C_DR_CMD_MASK) + +#define I2C_DR_DAT_SHIFT (0) +#define I2C_DR_DAT_MASK (0xFFU << I2C_DR_DAT_SHIFT) +#define I2C_DR_DAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_DR_DAT_SHIFT)) & I2C_DR_DAT_MASK) + +/*! + * @brief I2C_SSHR Register Bit Definition + */ + +#define I2C_SSHR_CNT_SHIFT (0) +#define I2C_SSHR_CNT_MASK (0xFFFFU << I2C_SSHR_CNT_SHIFT) +#define I2C_SSHR_CNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_SSHR_CNT_SHIFT)) & I2C_SSHR_CNT_MASK) + +/*! + * @brief I2C_SSLR Register Bit Definition + */ + +#define I2C_SSLR_CNT_SHIFT (0) +#define I2C_SSLR_CNT_MASK (0xFFFFU << I2C_SSLR_CNT_SHIFT) +#define I2C_SSLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_SSLR_CNT_SHIFT)) & I2C_SSLR_CNT_MASK) + +/*! + * @brief I2C_FSHR Register Bit Definition + */ + +#define I2C_FSHR_CNT_SHIFT (0) +#define I2C_FSHR_CNT_MASK (0xFFFFU << I2C_FSHR_CNT_SHIFT) +#define I2C_FSHR_CNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_FSHR_CNT_SHIFT)) & I2C_FSHR_CNT_MASK) + +/*! + * @brief I2C_FSLR Register Bit Definition + */ + +#define I2C_FSLR_CNT_SHIFT (0) +#define I2C_FSLR_CNT_MASK (0xFFFFU << I2C_FSLR_CNT_SHIFT) +#define I2C_FSLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_FSLR_CNT_SHIFT)) & I2C_FSLR_CNT_MASK) + +/*! + * @brief I2C_ISR Register Bit Definition + */ + +#define I2C_ISR_RSCLSTUCKATLOW_SHIFT (14) +#define I2C_ISR_RSCLSTUCKATLOW_MASK (0x01U << I2C_ISR_RSCLSTUCKATLOW_SHIFT) +#define I2C_ISR_RSCLSTUCKATLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_ISR_RSCLSTUCKATLOW_SHIFT)) & I2C_ISR_RSCLSTUCKATLOW_MASK) + +#define I2C_ISR_RMSTONHOLD_SHIFT (13) +#define I2C_ISR_RMSTONHOLD_MASK (0x01U << I2C_ISR_RMSTONHOLD_SHIFT) +#define I2C_ISR_RMSTONHOLD(x) (((uint32_t)(((uint32_t)(x)) << I2C_ISR_RMSTONHOLD_SHIFT)) & I2C_ISR_RMSTONHOLD_MASK) + +#define I2C_ISR_RGC_SHIFT (11) +#define I2C_ISR_RGC_MASK (0x01U << I2C_ISR_RGC_SHIFT) +#define I2C_ISR_RGC(x) (((uint32_t)(((uint32_t)(x)) << I2C_ISR_RGC_SHIFT)) & I2C_ISR_RGC_MASK) + +#define I2C_ISR_RSTART_SHIFT (10) +#define I2C_ISR_RSTART_MASK (0x01U << I2C_ISR_RSTART_SHIFT) +#define I2C_ISR_RSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_ISR_RSTART_SHIFT)) & I2C_ISR_RSTART_MASK) + +#define I2C_ISR_RSTOP_SHIFT (9) +#define I2C_ISR_RSTOP_MASK (0x01U << I2C_ISR_RSTOP_SHIFT) +#define I2C_ISR_RSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_ISR_RSTOP_SHIFT)) & I2C_ISR_RSTOP_MASK) + +#define I2C_ISR_RACTIV_SHIFT (8) +#define I2C_ISR_RACTIV_MASK (0x01U << I2C_ISR_RACTIV_SHIFT) +#define I2C_ISR_RACTIV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ISR_RACTIV_SHIFT)) & I2C_ISR_RACTIV_MASK) + +#define I2C_ISR_RRXDONE_SHIFT (7) +#define I2C_ISR_RRXDONE_MASK (0x01U << I2C_ISR_RRXDONE_SHIFT) +#define I2C_ISR_RRXDONE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ISR_RRXDONE_SHIFT)) & I2C_ISR_RRXDONE_MASK) + +#define I2C_ISR_RTXABRT_SHIFT (6) +#define I2C_ISR_RTXABRT_MASK (0x01U << I2C_ISR_RTXABRT_SHIFT) +#define I2C_ISR_RTXABRT(x) (((uint32_t)(((uint32_t)(x)) << I2C_ISR_RTXABRT_SHIFT)) & I2C_ISR_RTXABRT_MASK) + +#define I2C_ISR_RRDREQ_SHIFT (5) +#define I2C_ISR_RRDREQ_MASK (0x01U << I2C_ISR_RRDREQ_SHIFT) +#define I2C_ISR_RRDREQ(x) (((uint32_t)(((uint32_t)(x)) << I2C_ISR_RRDREQ_SHIFT)) & I2C_ISR_RRDREQ_MASK) + +#define I2C_ISR_RTXEMPTY_SHIFT (4) +#define I2C_ISR_RTXEMPTY_MASK (0x01U << I2C_ISR_RTXEMPTY_SHIFT) +#define I2C_ISR_RTXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2C_ISR_RTXEMPTY_SHIFT)) & I2C_ISR_RTXEMPTY_MASK) + +#define I2C_ISR_RTXOVER_SHIFT (3) +#define I2C_ISR_RTXOVER_MASK (0x01U << I2C_ISR_RTXOVER_SHIFT) +#define I2C_ISR_RTXOVER(x) (((uint32_t)(((uint32_t)(x)) << I2C_ISR_RTXOVER_SHIFT)) & I2C_ISR_RTXOVER_MASK) + +#define I2C_ISR_RRXFULL_SHIFT (2) +#define I2C_ISR_RRXFULL_MASK (0x01U << I2C_ISR_RRXFULL_SHIFT) +#define I2C_ISR_RRXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2C_ISR_RRXFULL_SHIFT)) & I2C_ISR_RRXFULL_MASK) + +#define I2C_ISR_RRXOVER_SHIFT (1) +#define I2C_ISR_RRXOVER_MASK (0x01U << I2C_ISR_RRXOVER_SHIFT) +#define I2C_ISR_RRXOVER(x) (((uint32_t)(((uint32_t)(x)) << I2C_ISR_RRXOVER_SHIFT)) & I2C_ISR_RRXOVER_MASK) + +#define I2C_ISR_RRXUNDER_SHIFT (0) +#define I2C_ISR_RRXUNDER_MASK (0x01U << I2C_ISR_RRXUNDER_SHIFT) +#define I2C_ISR_RRXUNDER(x) (((uint32_t)(((uint32_t)(x)) << I2C_ISR_RRXUNDER_SHIFT)) & I2C_ISR_RRXUNDER_MASK) + +/*! + * @brief I2C_IMR Register Bit Definition + */ + +#define I2C_IMR_MSCLSTUCK_SHIFT (14) +#define I2C_IMR_MSCLSTUCK_MASK (0x01U << I2C_IMR_MSCLSTUCK_SHIFT) +#define I2C_IMR_MSCLSTUCK(x) (((uint32_t)(((uint32_t)(x)) << I2C_IMR_MSCLSTUCK_SHIFT)) & I2C_IMR_MSCLSTUCK_MASK) + +#define I2C_IMR_MMSTONHOLD_SHIFT (13) +#define I2C_IMR_MMSTONHOLD_MASK (0x01U << I2C_IMR_MMSTONHOLD_SHIFT) +#define I2C_IMR_MMSTONHOLD(x) (((uint32_t)(((uint32_t)(x)) << I2C_IMR_MMSTONHOLD_SHIFT)) & I2C_IMR_MMSTONHOLD_MASK) + +#define I2C_IMR_MGC_SHIFT (11) +#define I2C_IMR_MGC_MASK (0x01U << I2C_IMR_MGC_SHIFT) +#define I2C_IMR_MGC(x) (((uint32_t)(((uint32_t)(x)) << I2C_IMR_MGC_SHIFT)) & I2C_IMR_MGC_MASK) + +#define I2C_IMR_MSTART_SHIFT (10) +#define I2C_IMR_MSTART_MASK (0x01U << I2C_IMR_MSTART_SHIFT) +#define I2C_IMR_MSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_IMR_MSTART_SHIFT)) & I2C_IMR_MSTART_MASK) + +#define I2C_IMR_MSTOP_SHIFT (9) +#define I2C_IMR_MSTOP_MASK (0x01U << I2C_IMR_MSTOP_SHIFT) +#define I2C_IMR_MSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_IMR_MSTOP_SHIFT)) & I2C_IMR_MSTOP_MASK) + +#define I2C_IMR_MACTIV_SHIFT (8) +#define I2C_IMR_MACTIV_MASK (0x01U << I2C_IMR_MACTIV_SHIFT) +#define I2C_IMR_MACTIV(x) (((uint32_t)(((uint32_t)(x)) << I2C_IMR_MACTIV_SHIFT)) & I2C_IMR_MACTIV_MASK) + +#define I2C_IMR_MRXDONE_SHIFT (7) +#define I2C_IMR_MRXDONE_MASK (0x01U << I2C_IMR_MRXDONE_SHIFT) +#define I2C_IMR_MRXDONE(x) (((uint32_t)(((uint32_t)(x)) << I2C_IMR_MRXDONE_SHIFT)) & I2C_IMR_MRXDONE_MASK) + +#define I2C_IMR_MTXABRT_SHIFT (6) +#define I2C_IMR_MTXABRT_MASK (0x01U << I2C_IMR_MTXABRT_SHIFT) +#define I2C_IMR_MTXABRT(x) (((uint32_t)(((uint32_t)(x)) << I2C_IMR_MTXABRT_SHIFT)) & I2C_IMR_MTXABRT_MASK) + +#define I2C_IMR_MRDREQ_SHIFT (5) +#define I2C_IMR_MRDREQ_MASK (0x01U << I2C_IMR_MRDREQ_SHIFT) +#define I2C_IMR_MRDREQ(x) (((uint32_t)(((uint32_t)(x)) << I2C_IMR_MRDREQ_SHIFT)) & I2C_IMR_MRDREQ_MASK) + +#define I2C_IMR_MTXEMPTY_SHIFT (4) +#define I2C_IMR_MTXEMPTY_MASK (0x01U << I2C_IMR_MTXEMPTY_SHIFT) +#define I2C_IMR_MTXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2C_IMR_MTXEMPTY_SHIFT)) & I2C_IMR_MTXEMPTY_MASK) + +#define I2C_IMR_MTXOVER_SHIFT (3) +#define I2C_IMR_MTXOVER_MASK (0x01U << I2C_IMR_MTXOVER_SHIFT) +#define I2C_IMR_MTXOVER(x) (((uint32_t)(((uint32_t)(x)) << I2C_IMR_MTXOVER_SHIFT)) & I2C_IMR_MTXOVER_MASK) + +#define I2C_IMR_MRXFULL_SHIFT (2) +#define I2C_IMR_MRXFULL_MASK (0x01U << I2C_IMR_MRXFULL_SHIFT) +#define I2C_IMR_MRXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2C_IMR_MRXFULL_SHIFT)) & I2C_IMR_MRXFULL_MASK) + +#define I2C_IMR_MRXOVER_SHIFT (1) +#define I2C_IMR_MRXOVER_MASK (0x01U << I2C_IMR_MRXOVER_SHIFT) +#define I2C_IMR_MRXOVER(x) (((uint32_t)(((uint32_t)(x)) << I2C_IMR_MRXOVER_SHIFT)) & I2C_IMR_MRXOVER_MASK) + +#define I2C_IMR_MRXUNDER_SHIFT (0) +#define I2C_IMR_MRXUNDER_MASK (0x01U << I2C_IMR_MRXUNDER_SHIFT) +#define I2C_IMR_MRXUNDER(x) (((uint32_t)(((uint32_t)(x)) << I2C_IMR_MRXUNDER_SHIFT)) & I2C_IMR_MRXUNDER_MASK) + +/*! + * @brief I2C_RAWISR Register Bit Definition + */ + +#define I2C_RAWISR_SCLSTUCK_SHIFT (14) +#define I2C_RAWISR_SCLSTUCK_MASK (0x01U << I2C_RAWISR_SCLSTUCK_SHIFT) +#define I2C_RAWISR_SCLSTUCK(x) (((uint32_t)(((uint32_t)(x)) << I2C_RAWISR_SCLSTUCK_SHIFT)) & I2C_RAWISR_SCLSTUCK_MASK) + +#define I2C_RAWISR_MSTONHOLD_SHIFT (13) +#define I2C_RAWISR_MSTONHOLD_MASK (0x01U << I2C_RAWISR_MSTONHOLD_SHIFT) +#define I2C_RAWISR_MSTONHOLD(x) (((uint32_t)(((uint32_t)(x)) << I2C_RAWISR_MSTONHOLD_SHIFT)) & I2C_RAWISR_MSTONHOLD_MASK) + +#define I2C_RAWISR_GC_SHIFT (11) +#define I2C_RAWISR_GC_MASK (0x01U << I2C_RAWISR_GC_SHIFT) +#define I2C_RAWISR_GC(x) (((uint32_t)(((uint32_t)(x)) << I2C_RAWISR_GC_SHIFT)) & I2C_RAWISR_GC_MASK) + +#define I2C_RAWISR_START_SHIFT (10) +#define I2C_RAWISR_START_MASK (0x01U << I2C_RAWISR_START_SHIFT) +#define I2C_RAWISR_START(x) (((uint32_t)(((uint32_t)(x)) << I2C_RAWISR_START_SHIFT)) & I2C_RAWISR_START_MASK) + +#define I2C_RAWISR_STOP_SHIFT (9) +#define I2C_RAWISR_STOP_MASK (0x01U << I2C_RAWISR_STOP_SHIFT) +#define I2C_RAWISR_STOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_RAWISR_STOP_SHIFT)) & I2C_RAWISR_STOP_MASK) + +#define I2C_RAWISR_ACTIV_SHIFT (8) +#define I2C_RAWISR_ACTIV_MASK (0x01U << I2C_RAWISR_ACTIV_SHIFT) +#define I2C_RAWISR_ACTIV(x) (((uint32_t)(((uint32_t)(x)) << I2C_RAWISR_ACTIV_SHIFT)) & I2C_RAWISR_ACTIV_MASK) + +#define I2C_RAWISR_RXDONE_SHIFT (7) +#define I2C_RAWISR_RXDONE_MASK (0x01U << I2C_RAWISR_RXDONE_SHIFT) +#define I2C_RAWISR_RXDONE(x) (((uint32_t)(((uint32_t)(x)) << I2C_RAWISR_RXDONE_SHIFT)) & I2C_RAWISR_RXDONE_MASK) + +#define I2C_RAWISR_TXABRT_SHIFT (6) +#define I2C_RAWISR_TXABRT_MASK (0x01U << I2C_RAWISR_TXABRT_SHIFT) +#define I2C_RAWISR_TXABRT(x) (((uint32_t)(((uint32_t)(x)) << I2C_RAWISR_TXABRT_SHIFT)) & I2C_RAWISR_TXABRT_MASK) + +#define I2C_RAWISR_RDREQ_SHIFT (5) +#define I2C_RAWISR_RDREQ_MASK (0x01U << I2C_RAWISR_RDREQ_SHIFT) +#define I2C_RAWISR_RDREQ(x) (((uint32_t)(((uint32_t)(x)) << I2C_RAWISR_RDREQ_SHIFT)) & I2C_RAWISR_RDREQ_MASK) + +#define I2C_RAWISR_TXEMPTY_SHIFT (4) +#define I2C_RAWISR_TXEMPTY_MASK (0x01U << I2C_RAWISR_TXEMPTY_SHIFT) +#define I2C_RAWISR_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2C_RAWISR_TXEMPTY_SHIFT)) & I2C_RAWISR_TXEMPTY_MASK) + +#define I2C_RAWISR_TXOVER_SHIFT (3) +#define I2C_RAWISR_TXOVER_MASK (0x01U << I2C_RAWISR_TXOVER_SHIFT) +#define I2C_RAWISR_TXOVER(x) (((uint32_t)(((uint32_t)(x)) << I2C_RAWISR_TXOVER_SHIFT)) & I2C_RAWISR_TXOVER_MASK) + +#define I2C_RAWISR_RXFULL_SHIFT (2) +#define I2C_RAWISR_RXFULL_MASK (0x01U << I2C_RAWISR_RXFULL_SHIFT) +#define I2C_RAWISR_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2C_RAWISR_RXFULL_SHIFT)) & I2C_RAWISR_RXFULL_MASK) + +#define I2C_RAWISR_RXOVER_SHIFT (1) +#define I2C_RAWISR_RXOVER_MASK (0x01U << I2C_RAWISR_RXOVER_SHIFT) +#define I2C_RAWISR_RXOVER(x) (((uint32_t)(((uint32_t)(x)) << I2C_RAWISR_RXOVER_SHIFT)) & I2C_RAWISR_RXOVER_MASK) + +#define I2C_RAWISR_RXUNDER_SHIFT (0) +#define I2C_RAWISR_RXUNDER_MASK (0x01U << I2C_RAWISR_RXUNDER_SHIFT) +#define I2C_RAWISR_RXUNDER(x) (((uint32_t)(((uint32_t)(x)) << I2C_RAWISR_RXUNDER_SHIFT)) & I2C_RAWISR_RXUNDER_MASK) + +/*! + * @brief I2C_RXTLR Register Bit Definition + */ + +#define I2C_RXTLR_TL_SHIFT (0) +#define I2C_RXTLR_TL_MASK (0x3U << I2C_RXTLR_TL_SHIFT) +#define I2C_RXTLR_TL(x) (((uint32_t)(((uint32_t)(x)) << I2C_RXTLR_TL_SHIFT)) & I2C_RXTLR_TL_MASK) + +/*! + * @brief I2C_TXTLR Register Bit Definition + */ + +#define I2C_TXTLR_TL_SHIFT (0) +#define I2C_TXTLR_TL_MASK (0x3U << I2C_TXTLR_TL_SHIFT) +#define I2C_TXTLR_TL(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXTLR_TL_SHIFT)) & I2C_TXTLR_TL_MASK) + +/*! + * @brief I2C_ICR Register Bit Definition + */ + +#define I2C_ICR_ICR_SHIFT (0) +#define I2C_ICR_ICR_MASK (0x01U << I2C_ICR_ICR_SHIFT) +#define I2C_ICR_ICR(x) (((uint32_t)(((uint32_t)(x)) << I2C_ICR_ICR_SHIFT)) & I2C_ICR_ICR_MASK) + +/*! + * @brief I2C_RX_UNDER Register Bit Definition + */ + +#define I2C_RXUNDER_RXUNDER_SHIFT (0) +#define I2C_RXUNDER_RXUNDER_MASK (0x01U << I2C_RXUNDER_RXUNDER_SHIFT) +#define I2C_RXUNDER_RXUNDER(x) (((uint32_t)(((uint32_t)(x)) << I2C_RXUNDER_RXUNDER_SHIFT)) & I2C_RXUNDER_RXUNDER_MASK) + +/*! + * @brief I2C_RX_OVER Register Bit Definition + */ + +#define I2C_RXOVER_RXOVER_SHIFT (0) +#define I2C_RXOVER_RXOVER_MASK (0x01U << I2C_RXOVER_RXOVER_SHIFT) +#define I2C_RXOVER_RXOVER(x) (((uint32_t)(((uint32_t)(x)) << I2C_RXOVER_RXOVER_SHIFT)) & I2C_RXOVER_RXOVER_MASK) + +/*! + * @brief I2C_TX_OVER Register Bit Definition + */ + +#define I2C_TXOVER_TXOVER_SHIFT (0) +#define I2C_TXOVER_TXOVER_MASK (0x01U << I2C_TXOVER_TXOVER_SHIFT) +#define I2C_TXOVER_TXOVER(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXOVER_TXOVER_SHIFT)) & I2C_TXOVER_TXOVER_MASK) + +/*! + * @brief I2C_RD_REQ Register Bit Definition + */ + +#define I2C_RDREQ_RDREQ_SHIFT (0) +#define I2C_RDREQ_RDREQ_MASK (0x01U << I2C_RDREQ_RDREQ_SHIFT) +#define I2C_RDREQ_RDREQ(x) (((uint32_t)(((uint32_t)(x)) << I2C_RDREQ_RDREQ_SHIFT)) & I2C_RDREQ_RDREQ_MASK) + +/*! + * @brief I2C_TX_ABRT Register Bit Definition + */ + +#define I2C_TXABRT_TXABRT_SHIFT (0) +#define I2C_TXABRT_TXABRT_MASK (0x01U << I2C_TXABRT_TXABRT_SHIFT) +#define I2C_TXABRT_TXABRT(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRT_TXABRT_SHIFT)) & I2C_TXABRT_TXABRT_MASK) + +/*! + * @brief I2C_RX_DONE Register Bit Definition + */ + +#define I2C_RXDONE_RXDONE_SHIFT (0) +#define I2C_RXDONE_RXDONE_MASK (0x01U << I2C_RXDONE_RXDONE_SHIFT) +#define I2C_RXDONE_RXDONE(x) (((uint32_t)(((uint32_t)(x)) << I2C_RXDONE_RXDONE_SHIFT)) & I2C_RXDONE_RXDONE_MASK) + +/*! + * @brief I2C_ACTIV Register Bit Definition + */ + +#define I2C_ACTIV_ACTIV_SHIFT (0) +#define I2C_ACTIV_ACTIV_MASK (0x01U << I2C_ACTIV_ACTIV_SHIFT) +#define I2C_ACTIV_ACTIV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ACTIV_ACTIV_SHIFT)) & I2C_ACTIV_ACTIV_MASK) + +/*! + * @brief I2C_STOP Register Bit Definition + */ + +#define I2C_STOP_STOP_SHIFT (0) +#define I2C_STOP_STOP_MASK (0x01U << I2C_STOP_STOP_SHIFT) +#define I2C_STOP_STOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_STOP_STOP_SHIFT)) & I2C_STOP_STOP_MASK) + +/*! + * @brief I2C_START Register Bit Definition + */ + +#define I2C_START_START_SHIFT (0) +#define I2C_START_START_MASK (0x01U << I2C_START_START_SHIFT) +#define I2C_START_START(x) (((uint32_t)(((uint32_t)(x)) << I2C_START_START_SHIFT)) & I2C_START_START_MASK) + +/*! + * @brief I2C_GC Register Bit Definition + */ + +#define I2C_GC_GC_SHIFT (0) +#define I2C_GC_GC_MASK (0x01U << I2C_GC_GC_SHIFT) +#define I2C_GC_GC(x) (((uint32_t)(((uint32_t)(x)) << I2C_GC_GC_SHIFT)) & I2C_GC_GC_MASK) + +/*! + * @brief I2C_ENR Register Bit Definition + */ + +#define I2C_ENR_SMBALTEN_SHIFT (18) +#define I2C_ENR_SMBALTEN_MASK (0x01U << I2C_ENR_SMBALTEN_SHIFT) +#define I2C_ENR_SMBALTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_ENR_SMBALTEN_SHIFT)) & I2C_ENR_SMBALTEN_MASK) + +#define I2C_ENR_SMBCLKRST_SHIFT (16) +#define I2C_ENR_SMBCLKRST_MASK (0x01U << I2C_ENR_SMBCLKRST_SHIFT) +#define I2C_ENR_SMBCLKRST(x) (((uint32_t)(((uint32_t)(x)) << I2C_ENR_SMBCLKRST_SHIFT)) & I2C_ENR_SMBCLKRST_MASK) + +#define I2C_ENR_SDARCVEN_SHIFT (3) +#define I2C_ENR_SDARCVEN_MASK (0x01U << I2C_ENR_SDARCVEN_SHIFT) +#define I2C_ENR_SDARCVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_ENR_SDARCVEN_SHIFT)) & I2C_ENR_SDARCVEN_MASK) + +#define I2C_ENR_TXCMDBLOCK_SHIFT (2) +#define I2C_ENR_TXCMDBLOCK_MASK (0x01U << I2C_ENR_TXCMDBLOCK_SHIFT) +#define I2C_ENR_TXCMDBLOCK(x) (((uint32_t)(((uint32_t)(x)) << I2C_ENR_TXCMDBLOCK_SHIFT)) & I2C_ENR_TXCMDBLOCK_MASK) + +#define I2C_ENR_ABORT_SHIFT (1) +#define I2C_ENR_ABORT_MASK (0x01U << I2C_ENR_ABORT_SHIFT) +#define I2C_ENR_ABORT(x) (((uint32_t)(((uint32_t)(x)) << I2C_ENR_ABORT_SHIFT)) & I2C_ENR_ABORT_MASK) + +#define I2C_ENR_ENABLE_SHIFT (0) +#define I2C_ENR_ENABLE_MASK (0x01U << I2C_ENR_ENABLE_SHIFT) +#define I2C_ENR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ENR_ENABLE_SHIFT)) & I2C_ENR_ENABLE_MASK) + +/*! + * @brief I2C_SR Register Bit Definition + */ + +#define I2C_SR_SMBALT_SHIFT (20) +#define I2C_SR_SMBALT_MASK (0x01U << I2C_SR_SMBALT_SHIFT) +#define I2C_SR_SMBALT(x) (((uint32_t)(((uint32_t)(x)) << I2C_SR_SMBALT_SHIFT)) & I2C_SR_SMBALT_MASK) + +#define I2C_SR_SMBSLVAR_SHIFT (18) +#define I2C_SR_SMBSLVAR_MASK (0x01U << I2C_SR_SMBSLVAR_SHIFT) +#define I2C_SR_SMBSLVAR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SR_SMBSLVAR_SHIFT)) & I2C_SR_SMBSLVAR_MASK) + +#define I2C_SR_SMBSLVAV_SHIFT (17) +#define I2C_SR_SMBSLVAV_MASK (0x01U << I2C_SR_SMBSLVAV_SHIFT) +#define I2C_SR_SMBSLVAV(x) (((uint32_t)(((uint32_t)(x)) << I2C_SR_SMBSLVAV_SHIFT)) & I2C_SR_SMBSLVAV_MASK) + +#define I2C_SR_SMBQC_SHIFT (16) +#define I2C_SR_SMBQC_MASK (0x01U << I2C_SR_SMBQC_SHIFT) +#define I2C_SR_SMBQC(x) (((uint32_t)(((uint32_t)(x)) << I2C_SR_SMBQC_SHIFT)) & I2C_SR_SMBQC_MASK) + +#define I2C_SR_SDANOTRECOVERED_SHIFT (11) +#define I2C_SR_SDANOTRECOVERED_MASK (0x01U << I2C_SR_SDANOTRECOVERED_SHIFT) +#define I2C_SR_SDANOTRECOVERED(x) (((uint32_t)(((uint32_t)(x)) << I2C_SR_SDANOTRECOVERED_SHIFT)) & I2C_SR_SDANOTRECOVERED_MASK) + +#define I2C_SR_SLVHOLDRXFULL_SHIFT (10) +#define I2C_SR_SLVHOLDRXFULL_MASK (0x01U << I2C_SR_SLVHOLDRXFULL_SHIFT) +#define I2C_SR_SLVHOLDRXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2C_SR_SLVHOLDRXFULL_SHIFT)) & I2C_SR_SLVHOLDRXFULL_MASK) + +#define I2C_SR_SLVHOLDTXEMPTY_SHIFT (9) +#define I2C_SR_SLVHOLDTXEMPTY_MASK (0x01U << I2C_SR_SLVHOLDTXEMPTY_SHIFT) +#define I2C_SR_SLVHOLDTXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2C_SR_SLVHOLDTXEMPTY_SHIFT)) & I2C_SR_SLVHOLDTXEMPTY_MASK) + +#define I2C_SR_MSTHOLDRXFULL_SHIFT (8) +#define I2C_SR_MSTHOLDRXFULL_MASK (0x01U << I2C_SR_MSTHOLDRXFULL_SHIFT) +#define I2C_SR_MSTHOLDRXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2C_SR_MSTHOLDRXFULL_SHIFT)) & I2C_SR_MSTHOLDRXFULL_MASK) + +#define I2C_SR_MSTHOLDTXEMPTY_SHIFT (7) +#define I2C_SR_MSTHOLDTXEMPTY_MASK (0x01U << I2C_SR_MSTHOLDTXEMPTY_SHIFT) +#define I2C_SR_MSTHOLDTXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2C_SR_MSTHOLDTXEMPTY_SHIFT)) & I2C_SR_MSTHOLDTXEMPTY_MASK) + +#define I2C_SR_SLVACTIV_SHIFT (6) +#define I2C_SR_SLVACTIV_MASK (0x01U << I2C_SR_SLVACTIV_SHIFT) +#define I2C_SR_SLVACTIV(x) (((uint32_t)(((uint32_t)(x)) << I2C_SR_SLVACTIV_SHIFT)) & I2C_SR_SLVACTIV_MASK) + +#define I2C_SR_MSTACTIV_SHIFT (5) +#define I2C_SR_MSTACTIV_MASK (0x01U << I2C_SR_MSTACTIV_SHIFT) +#define I2C_SR_MSTACTIV(x) (((uint32_t)(((uint32_t)(x)) << I2C_SR_MSTACTIV_SHIFT)) & I2C_SR_MSTACTIV_MASK) + +#define I2C_SR_RFF_SHIFT (4) +#define I2C_SR_RFF_MASK (0x01U << I2C_SR_RFF_SHIFT) +#define I2C_SR_RFF(x) (((uint32_t)(((uint32_t)(x)) << I2C_SR_RFF_SHIFT)) & I2C_SR_RFF_MASK) + +#define I2C_SR_RFNE_SHIFT (3) +#define I2C_SR_RFNE_MASK (0x01U << I2C_SR_RFNE_SHIFT) +#define I2C_SR_RFNE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SR_RFNE_SHIFT)) & I2C_SR_RFNE_MASK) + +#define I2C_SR_TFE_SHIFT (2) +#define I2C_SR_TFE_MASK (0x01U << I2C_SR_TFE_SHIFT) +#define I2C_SR_TFE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SR_TFE_SHIFT)) & I2C_SR_TFE_MASK) + +#define I2C_SR_TFNF_SHIFT (1) +#define I2C_SR_TFNF_MASK (0x01U << I2C_SR_TFNF_SHIFT) +#define I2C_SR_TFNF(x) (((uint32_t)(((uint32_t)(x)) << I2C_SR_TFNF_SHIFT)) & I2C_SR_TFNF_MASK) + +#define I2C_SR_ACTIV_SHIFT (0) +#define I2C_SR_ACTIV_MASK (0x01U << I2C_SR_ACTIV_SHIFT) +#define I2C_SR_ACTIV(x) (((uint32_t)(((uint32_t)(x)) << I2C_SR_ACTIV_SHIFT)) & I2C_SR_ACTIV_MASK) + +/*! + * @brief I2C_TXFLR Register Bit Definition + */ + +#define I2C_TXFLR_CNT_SHIFT (0) +#define I2C_TXFLR_CNT_MASK (0x7U << I2C_TXFLR_CNT_SHIFT) +#define I2C_TXFLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXFLR_CNT_SHIFT)) & I2C_TXFLR_CNT_MASK) + +/*! + * @brief I2C_RXFLR Register Bit Definition + */ + +#define I2C_RXFLR_CNT_SHIFT (0) +#define I2C_RXFLR_CNT_MASK (0x7U << I2C_RXFLR_CNT_SHIFT) +#define I2C_RXFLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_RXFLR_CNT_SHIFT)) & I2C_RXFLR_CNT_MASK) + +/*! + * @brief I2C_HOLD Register Bit Definition + */ + +#define I2C_HOLD_RXHOLD_SHIFT (16) +#define I2C_HOLD_RXHOLD_MASK (0xFFU << I2C_HOLD_RXHOLD_SHIFT) +#define I2C_HOLD_RXHOLD(x) (((uint32_t)(((uint32_t)(x)) << I2C_HOLD_RXHOLD_SHIFT)) & I2C_HOLD_RXHOLD_MASK) + +#define I2C_HOLD_TXHOLD_SHIFT (0) +#define I2C_HOLD_TXHOLD_MASK (0xFFFFU << I2C_HOLD_TXHOLD_SHIFT) +#define I2C_HOLD_TXHOLD(x) (((uint32_t)(((uint32_t)(x)) << I2C_HOLD_TXHOLD_SHIFT)) & I2C_HOLD_TXHOLD_MASK) + +/*! + * @brief I2C_TX_ABRT_SRC Register Bit Definition + */ + +#define I2C_TXABRTSRC_TXFLUSHCNT_SHIFT (23) +#define I2C_TXABRTSRC_TXFLUSHCNT_MASK (0x1FFU << I2C_TXABRTSRC_TXFLUSHCNT_SHIFT) +#define I2C_TXABRTSRC_TXFLUSHCNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRTSRC_TXFLUSHCNT_SHIFT)) & I2C_TXABRTSRC_TXFLUSHCNT_MASK) + +#define I2C_TXABRTSRC_SDALOW_SHIFT (17) +#define I2C_TXABRTSRC_SDALOW_MASK (0x01U << I2C_TXABRTSRC_SDALOW_SHIFT) +#define I2C_TXABRTSRC_SDALOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRTSRC_SDALOW_SHIFT)) & I2C_TXABRTSRC_SDALOW_MASK) + +#define I2C_TXABRTSRC_USERABRT_SHIFT (16) +#define I2C_TXABRTSRC_USERABRT_MASK (0x01U << I2C_TXABRTSRC_USERABRT_SHIFT) +#define I2C_TXABRTSRC_USERABRT(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRTSRC_USERABRT_SHIFT)) & I2C_TXABRTSRC_USERABRT_MASK) + +#define I2C_TXABRTSRC_SLVRDINTX_SHIFT (15) +#define I2C_TXABRTSRC_SLVRDINTX_MASK (0x01U << I2C_TXABRTSRC_SLVRDINTX_SHIFT) +#define I2C_TXABRTSRC_SLVRDINTX(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRTSRC_SLVRDINTX_SHIFT)) & I2C_TXABRTSRC_SLVRDINTX_MASK) + +#define I2C_TXABRTSRC_SLVARBLOST_SHIFT (14) +#define I2C_TXABRTSRC_SLVARBLOST_MASK (0x01U << I2C_TXABRTSRC_SLVARBLOST_SHIFT) +#define I2C_TXABRTSRC_SLVARBLOST(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRTSRC_SLVARBLOST_SHIFT)) & I2C_TXABRTSRC_SLVARBLOST_MASK) + +#define I2C_TXABRTSRC_SLVFLUSHTXFIFO_SHIFT (13) +#define I2C_TXABRTSRC_SLVFLUSHTXFIFO_MASK (0x01U << I2C_TXABRTSRC_SLVFLUSHTXFIFO_SHIFT) +#define I2C_TXABRTSRC_SLVFLUSHTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRTSRC_SLVFLUSHTXFIFO_SHIFT)) & I2C_TXABRTSRC_SLVFLUSHTXFIFO_MASK) + +#define I2C_TXABRTSRC_LOST_SHIFT (12) +#define I2C_TXABRTSRC_LOST_MASK (0x01U << I2C_TXABRTSRC_LOST_SHIFT) +#define I2C_TXABRTSRC_LOST(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRTSRC_LOST_SHIFT)) & I2C_TXABRTSRC_LOST_MASK) + +#define I2C_TXABRTSRC_MSTDIS_SHIFT (11) +#define I2C_TXABRTSRC_MSTDIS_MASK (0x01U << I2C_TXABRTSRC_MSTDIS_SHIFT) +#define I2C_TXABRTSRC_MSTDIS(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRTSRC_MSTDIS_SHIFT)) & I2C_TXABRTSRC_MSTDIS_MASK) + +#define I2C_TXABRTSRC_10BRDNORSTRT_SHIFT (10) +#define I2C_TXABRTSRC_10BRDNORSTRT_MASK (0x01U << I2C_TXABRTSRC_10BRDNORSTRT_SHIFT) +#define I2C_TXABRTSRC_10BRDNORSTRT(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRTSRC_10BRDNORSTRT_SHIFT)) & I2C_TXABRTSRC_10BRDNORSTRT_MASK) + +#define I2C_TXABRTSRC_SBYTENORSTRT_SHIFT (9) +#define I2C_TXABRTSRC_SBYTENORSTRT_MASK (0x01U << I2C_TXABRTSRC_SBYTENORSTRT_SHIFT) +#define I2C_TXABRTSRC_SBYTENORSTRT(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRTSRC_SBYTENORSTRT_SHIFT)) & I2C_TXABRTSRC_SBYTENORSTRT_MASK) + +#define I2C_TXABRTSRC_SBYTEACKDET_SHIFT (7) +#define I2C_TXABRTSRC_SBYTEACKDET_MASK (0x01U << I2C_TXABRTSRC_SBYTEACKDET_SHIFT) +#define I2C_TXABRTSRC_SBYTEACKDET(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRTSRC_SBYTEACKDET_SHIFT)) & I2C_TXABRTSRC_SBYTEACKDET_MASK) + +#define I2C_TXABRTSRC_GCREAD_SHIFT (5) +#define I2C_TXABRTSRC_GCREAD_MASK (0x01U << I2C_TXABRTSRC_GCREAD_SHIFT) +#define I2C_TXABRTSRC_GCREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRTSRC_GCREAD_SHIFT)) & I2C_TXABRTSRC_GCREAD_MASK) + +#define I2C_TXABRTSRC_GCNOACK_SHIFT (4) +#define I2C_TXABRTSRC_GCNOACK_MASK (0x01U << I2C_TXABRTSRC_GCNOACK_SHIFT) +#define I2C_TXABRTSRC_GCNOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRTSRC_GCNOACK_SHIFT)) & I2C_TXABRTSRC_GCNOACK_MASK) + +#define I2C_TXABRTSRC_TXDATANOACK_SHIFT (3) +#define I2C_TXABRTSRC_TXDATANOACK_MASK (0x01U << I2C_TXABRTSRC_TXDATANOACK_SHIFT) +#define I2C_TXABRTSRC_TXDATANOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRTSRC_TXDATANOACK_SHIFT)) & I2C_TXABRTSRC_TXDATANOACK_MASK) + +#define I2C_TXABRTSRC_10ADDR2NOACK_SHIFT (2) +#define I2C_TXABRTSRC_10ADDR2NOACK_MASK (0x01U << I2C_TXABRTSRC_10ADDR2NOACK_SHIFT) +#define I2C_TXABRTSRC_10ADDR2NOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRTSRC_10ADDR2NOACK_SHIFT)) & I2C_TXABRTSRC_10ADDR2NOACK_MASK) + +#define I2C_TXABRTSRC_10ADDR1NOACK_SHIFT (1) +#define I2C_TXABRTSRC_10ADDR1NOACK_MASK (0x01U << I2C_TXABRTSRC_10ADDR1NOACK_SHIFT) +#define I2C_TXABRTSRC_10ADDR1NOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRTSRC_10ADDR1NOACK_SHIFT)) & I2C_TXABRTSRC_10ADDR1NOACK_MASK) + +#define I2C_TXABRTSRC_7ADDRNOACK_SHIFT (0) +#define I2C_TXABRTSRC_7ADDRNOACK_MASK (0x01U << I2C_TXABRTSRC_7ADDRNOACK_SHIFT) +#define I2C_TXABRTSRC_7ADDRNOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_TXABRTSRC_7ADDRNOACK_SHIFT)) & I2C_TXABRTSRC_7ADDRNOACK_MASK) + +/*! + * @brief I2C_SLV_NACK Register Bit Definition + */ + +#define I2C_SLVNACK_NACK_SHIFT (0) +#define I2C_SLVNACK_NACK_MASK (0x01U << I2C_SLVNACK_NACK_SHIFT) +#define I2C_SLVNACK_NACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVNACK_NACK_SHIFT)) & I2C_SLVNACK_NACK_MASK) + +/*! + * @brief I2C_DMA Register Bit Definition + */ + +#define I2C_DMA_TXEN_SHIFT (1) +#define I2C_DMA_TXEN_MASK (0x01U << I2C_DMA_TXEN_SHIFT) +#define I2C_DMA_TXEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_DMA_TXEN_SHIFT)) & I2C_DMA_TXEN_MASK) + +#define I2C_DMA_RXEN_SHIFT (0) +#define I2C_DMA_RXEN_MASK (0x01U << I2C_DMA_RXEN_SHIFT) +#define I2C_DMA_RXEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_DMA_RXEN_SHIFT)) & I2C_DMA_RXEN_MASK) + +/*! + * @brief I2C_SETUP Register Bit Definition + */ + +#define I2C_SETUP_CNT_SHIFT (0) +#define I2C_SETUP_CNT_MASK (0xFFU << I2C_SETUP_CNT_SHIFT) +#define I2C_SETUP_CNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_SETUP_CNT_SHIFT)) & I2C_SETUP_CNT_MASK) + +/*! + * @brief I2C_GCR Register Bit Definition + */ + +#define I2C_GCR_GC_SHIFT (0) +#define I2C_GCR_GC_MASK (0x01U << I2C_GCR_GC_SHIFT) +#define I2C_GCR_GC(x) (((uint32_t)(((uint32_t)(x)) << I2C_GCR_GC_SHIFT)) & I2C_GCR_GC_MASK) + +/*! + * @brief I2C_EN_SR Register Bit Definition + */ + +#define I2C_ENSR_SLVRXDATALOST_SHIFT (2) +#define I2C_ENSR_SLVRXDATALOST_MASK (0x01U << I2C_ENSR_SLVRXDATALOST_SHIFT) +#define I2C_ENSR_SLVRXDATALOST(x) (((uint32_t)(((uint32_t)(x)) << I2C_ENSR_SLVRXDATALOST_SHIFT)) & I2C_ENSR_SLVRXDATALOST_MASK) + +#define I2C_ENSR_SLVDISWHILEBUSY_SHIFT (1) +#define I2C_ENSR_SLVDISWHILEBUSY_MASK (0x01U << I2C_ENSR_SLVDISWHILEBUSY_SHIFT) +#define I2C_ENSR_SLVDISWHILEBUSY(x) (((uint32_t)(((uint32_t)(x)) << I2C_ENSR_SLVDISWHILEBUSY_SHIFT)) & I2C_ENSR_SLVDISWHILEBUSY_MASK) + +#define I2C_ENSR_ICEN_SHIFT (0) +#define I2C_ENSR_ICEN_MASK (0x01U << I2C_ENSR_ICEN_SHIFT) +#define I2C_ENSR_ICEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_ENSR_ICEN_SHIFT)) & I2C_ENSR_ICEN_MASK) + +/*! + * @brief I2C_SPKLEN Register Bit Definition + */ + +#define I2C_SPKLEN_SPKLEN_SHIFT (0) +#define I2C_SPKLEN_SPKLEN_MASK (0xFFU << I2C_SPKLEN_SPKLEN_SHIFT) +#define I2C_SPKLEN_SPKLEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_SPKLEN_SPKLEN_SHIFT)) & I2C_SPKLEN_SPKLEN_MASK) + +/*! + * @brief I2C_SCL_TMO Register Bit Definition + */ + +#define I2C_SCLTMO_SCLTIMEOUT_SHIFT (0) +#define I2C_SCLTMO_SCLTIMEOUT_MASK (0xFFFFFFFFU << I2C_SCLTMO_SCLTIMEOUT_SHIFT) +#define I2C_SCLTMO_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_SCLTMO_SCLTIMEOUT_SHIFT)) & I2C_SCLTMO_SCLTIMEOUT_MASK) + +/*! + * @brief I2C_SDA_TMO Register Bit Definition + */ + +#define I2C_SDATMO_SDATIMEOUT_SHIFT (0) +#define I2C_SDATMO_SDATIMEOUT_MASK (0xFFFFFFFFU << I2C_SDATMO_SDATIMEOUT_SHIFT) +#define I2C_SDATMO_SDATIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_SDATMO_SDATIMEOUT_SHIFT)) & I2C_SDATMO_SDATIMEOUT_MASK) + +/*! + * @brief I2C_SCL_STUCK Register Bit Definition + */ + +#define I2C_SCLSTUCK_SCLSTUCK_SHIFT (0) +#define I2C_SCLSTUCK_SCLSTUCK_MASK (0x01U << I2C_SCLSTUCK_SCLSTUCK_SHIFT) +#define I2C_SCLSTUCK_SCLSTUCK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SCLSTUCK_SCLSTUCK_SHIFT)) & I2C_SCLSTUCK_SCLSTUCK_MASK) + +/*! + * @brief I2C_SMB_SEXT Register Bit Definition + */ + +#define I2C_SMBSEXT_SMBSEXT_SHIFT (0) +#define I2C_SMBSEXT_SMBSEXT_MASK (0xFFFFFFFFU << I2C_SMBSEXT_SMBSEXT_SHIFT) +#define I2C_SMBSEXT_SMBSEXT(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBSEXT_SMBSEXT_SHIFT)) & I2C_SMBSEXT_SMBSEXT_MASK) + +/*! + * @brief I2C_SMB_MEXT Register Bit Definition + */ + +#define I2C_SMBMEXT_SMBMEXT_SHIFT (0) +#define I2C_SMBMEXT_SMBMEXT_MASK (0xFFFFFFFFU << I2C_SMBMEXT_SMBMEXT_SHIFT) +#define I2C_SMBMEXT_SMBMEXT(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBMEXT_SMBMEXT_SHIFT)) & I2C_SMBMEXT_SMBMEXT_MASK) + +/*! + * @brief I2C_SMB_IDLE Register Bit Definition + */ + +#define I2C_SMBIDLE_SMBIDLECNT_SHIFT (0) +#define I2C_SMBIDLE_SMBIDLECNT_MASK (0xFFFFU << I2C_SMBIDLE_SMBIDLECNT_SHIFT) +#define I2C_SMBIDLE_SMBIDLECNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBIDLE_SMBIDLECNT_SHIFT)) & I2C_SMBIDLE_SMBIDLECNT_MASK) + +/*! + * @brief I2C_SMB_ISR Register Bit Definition + */ + +#define I2C_SMBISR_RSMBALT_SHIFT (10) +#define I2C_SMBISR_RSMBALT_MASK (0x01U << I2C_SMBISR_RSMBALT_SHIFT) +#define I2C_SMBISR_RSMBALT(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBISR_RSMBALT_SHIFT)) & I2C_SMBISR_RSMBALT_MASK) + +#define I2C_SMBISR_RPECNACK_SHIFT (8) +#define I2C_SMBISR_RPECNACK_MASK (0x01U << I2C_SMBISR_RPECNACK_SHIFT) +#define I2C_SMBISR_RPECNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBISR_RPECNACK_SHIFT)) & I2C_SMBISR_RPECNACK_MASK) + +#define I2C_SMBISR_RARPASSGN_SHIFT (7) +#define I2C_SMBISR_RARPASSGN_MASK (0x01U << I2C_SMBISR_RARPASSGN_SHIFT) +#define I2C_SMBISR_RARPASSGN(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBISR_RARPASSGN_SHIFT)) & I2C_SMBISR_RARPASSGN_MASK) + +#define I2C_SMBISR_RARPUDID_SHIFT (6) +#define I2C_SMBISR_RARPUDID_MASK (0x01U << I2C_SMBISR_RARPUDID_SHIFT) +#define I2C_SMBISR_RARPUDID(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBISR_RARPUDID_SHIFT)) & I2C_SMBISR_RARPUDID_MASK) + +#define I2C_SMBISR_RARPRST_SHIFT (5) +#define I2C_SMBISR_RARPRST_MASK (0x01U << I2C_SMBISR_RARPRST_SHIFT) +#define I2C_SMBISR_RARPRST(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBISR_RARPRST_SHIFT)) & I2C_SMBISR_RARPRST_MASK) + +#define I2C_SMBISR_RARPPRE_SHIFT (4) +#define I2C_SMBISR_RARPPRE_MASK (0x01U << I2C_SMBISR_RARPPRE_SHIFT) +#define I2C_SMBISR_RARPPRE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBISR_RARPPRE_SHIFT)) & I2C_SMBISR_RARPPRE_MASK) + +#define I2C_SMBISR_RARPNOTIFY_SHIFT (3) +#define I2C_SMBISR_RARPNOTIFY_MASK (0x01U << I2C_SMBISR_RARPNOTIFY_SHIFT) +#define I2C_SMBISR_RARPNOTIFY(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBISR_RARPNOTIFY_SHIFT)) & I2C_SMBISR_RARPNOTIFY_MASK) + +#define I2C_SMBISR_RARPQUICK_SHIFT (2) +#define I2C_SMBISR_RARPQUICK_MASK (0x01U << I2C_SMBISR_RARPQUICK_SHIFT) +#define I2C_SMBISR_RARPQUICK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBISR_RARPQUICK_SHIFT)) & I2C_SMBISR_RARPQUICK_MASK) + +#define I2C_SMBISR_RMSTTMO_SHIFT (1) +#define I2C_SMBISR_RMSTTMO_MASK (0x01U << I2C_SMBISR_RMSTTMO_SHIFT) +#define I2C_SMBISR_RMSTTMO(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBISR_RMSTTMO_SHIFT)) & I2C_SMBISR_RMSTTMO_MASK) + +#define I2C_SMBISR_RSLVTMO_SHIFT (0) +#define I2C_SMBISR_RSLVTMO_MASK (0x01U << I2C_SMBISR_RSLVTMO_SHIFT) +#define I2C_SMBISR_RSLVTMO(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBISR_RSLVTMO_SHIFT)) & I2C_SMBISR_RSLVTMO_MASK) + +/*! + * @brief I2C_SMB_IMR Register Bit Definition + */ + +#define I2C_SMBIMR_MSMBALT_SHIFT (10) +#define I2C_SMBIMR_MSMBALT_MASK (0x01U << I2C_SMBIMR_MSMBALT_SHIFT) +#define I2C_SMBIMR_MSMBALT(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBIMR_MSMBALT_SHIFT)) & I2C_SMBIMR_MSMBALT_MASK) + +#define I2C_SMBIMR_MPECNACK_SHIFT (8) +#define I2C_SMBIMR_MPECNACK_MASK (0x01U << I2C_SMBIMR_MPECNACK_SHIFT) +#define I2C_SMBIMR_MPECNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBIMR_MPECNACK_SHIFT)) & I2C_SMBIMR_MPECNACK_MASK) + +#define I2C_SMBIMR_MARPASSGN_SHIFT (7) +#define I2C_SMBIMR_MARPASSGN_MASK (0x01U << I2C_SMBIMR_MARPASSGN_SHIFT) +#define I2C_SMBIMR_MARPASSGN(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBIMR_MARPASSGN_SHIFT)) & I2C_SMBIMR_MARPASSGN_MASK) + +#define I2C_SMBIMR_MARPUDID_SHIFT (6) +#define I2C_SMBIMR_MARPUDID_MASK (0x01U << I2C_SMBIMR_MARPUDID_SHIFT) +#define I2C_SMBIMR_MARPUDID(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBIMR_MARPUDID_SHIFT)) & I2C_SMBIMR_MARPUDID_MASK) + +#define I2C_SMBIMR_MARPRST_SHIFT (5) +#define I2C_SMBIMR_MARPRST_MASK (0x01U << I2C_SMBIMR_MARPRST_SHIFT) +#define I2C_SMBIMR_MARPRST(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBIMR_MARPRST_SHIFT)) & I2C_SMBIMR_MARPRST_MASK) + +#define I2C_SMBIMR_MARPPRE_SHIFT (4) +#define I2C_SMBIMR_MARPPRE_MASK (0x01U << I2C_SMBIMR_MARPPRE_SHIFT) +#define I2C_SMBIMR_MARPPRE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBIMR_MARPPRE_SHIFT)) & I2C_SMBIMR_MARPPRE_MASK) + +#define I2C_SMBIMR_MARPNOTIFY_SHIFT (3) +#define I2C_SMBIMR_MARPNOTIFY_MASK (0x01U << I2C_SMBIMR_MARPNOTIFY_SHIFT) +#define I2C_SMBIMR_MARPNOTIFY(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBIMR_MARPNOTIFY_SHIFT)) & I2C_SMBIMR_MARPNOTIFY_MASK) + +#define I2C_SMBIMR_MARPQUICK_SHIFT (2) +#define I2C_SMBIMR_MARPQUICK_MASK (0x01U << I2C_SMBIMR_MARPQUICK_SHIFT) +#define I2C_SMBIMR_MARPQUICK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBIMR_MARPQUICK_SHIFT)) & I2C_SMBIMR_MARPQUICK_MASK) + +#define I2C_SMBIMR_MMSTTMO_SHIFT (1) +#define I2C_SMBIMR_MMSTTMO_MASK (0x01U << I2C_SMBIMR_MMSTTMO_SHIFT) +#define I2C_SMBIMR_MMSTTMO(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBIMR_MMSTTMO_SHIFT)) & I2C_SMBIMR_MMSTTMO_MASK) + +#define I2C_SMBIMR_MSLVTMO_SHIFT (0) +#define I2C_SMBIMR_MSLVTMO_MASK (0x01U << I2C_SMBIMR_MSLVTMO_SHIFT) +#define I2C_SMBIMR_MSLVTMO(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBIMR_MSLVTMO_SHIFT)) & I2C_SMBIMR_MSLVTMO_MASK) + +/*! + * @brief I2C_SMB_RAWISR Register Bit Definition + */ + +#define I2C_SMBRAWISR_SMBALT_SHIFT (10) +#define I2C_SMBRAWISR_SMBALT_MASK (0x01U << I2C_SMBRAWISR_SMBALT_SHIFT) +#define I2C_SMBRAWISR_SMBALT(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBRAWISR_SMBALT_SHIFT)) & I2C_SMBRAWISR_SMBALT_MASK) + +#define I2C_SMBRAWISR_PECNACK_SHIFT (8) +#define I2C_SMBRAWISR_PECNACK_MASK (0x01U << I2C_SMBRAWISR_PECNACK_SHIFT) +#define I2C_SMBRAWISR_PECNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBRAWISR_PECNACK_SHIFT)) & I2C_SMBRAWISR_PECNACK_MASK) + +#define I2C_SMBRAWISR_ARPASSGN_SHIFT (7) +#define I2C_SMBRAWISR_ARPASSGN_MASK (0x01U << I2C_SMBRAWISR_ARPASSGN_SHIFT) +#define I2C_SMBRAWISR_ARPASSGN(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBRAWISR_ARPASSGN_SHIFT)) & I2C_SMBRAWISR_ARPASSGN_MASK) + +#define I2C_SMBRAWISR_ARPUDID_SHIFT (6) +#define I2C_SMBRAWISR_ARPUDID_MASK (0x01U << I2C_SMBRAWISR_ARPUDID_SHIFT) +#define I2C_SMBRAWISR_ARPUDID(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBRAWISR_ARPUDID_SHIFT)) & I2C_SMBRAWISR_ARPUDID_MASK) + +#define I2C_SMBRAWISR_ARPRST_SHIFT (5) +#define I2C_SMBRAWISR_ARPRST_MASK (0x01U << I2C_SMBRAWISR_ARPRST_SHIFT) +#define I2C_SMBRAWISR_ARPRST(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBRAWISR_ARPRST_SHIFT)) & I2C_SMBRAWISR_ARPRST_MASK) + +#define I2C_SMBRAWISR_ARPPRE_SHIFT (4) +#define I2C_SMBRAWISR_ARPPRE_MASK (0x01U << I2C_SMBRAWISR_ARPPRE_SHIFT) +#define I2C_SMBRAWISR_ARPPRE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBRAWISR_ARPPRE_SHIFT)) & I2C_SMBRAWISR_ARPPRE_MASK) + +#define I2C_SMBRAWISR_ARPNOTIFY_SHIFT (3) +#define I2C_SMBRAWISR_ARPNOTIFY_MASK (0x01U << I2C_SMBRAWISR_ARPNOTIFY_SHIFT) +#define I2C_SMBRAWISR_ARPNOTIFY(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBRAWISR_ARPNOTIFY_SHIFT)) & I2C_SMBRAWISR_ARPNOTIFY_MASK) + +#define I2C_SMBRAWISR_ARPQUICK_SHIFT (2) +#define I2C_SMBRAWISR_ARPQUICK_MASK (0x01U << I2C_SMBRAWISR_ARPQUICK_SHIFT) +#define I2C_SMBRAWISR_ARPQUICK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBRAWISR_ARPQUICK_SHIFT)) & I2C_SMBRAWISR_ARPQUICK_MASK) + +#define I2C_SMBRAWISR_MSTTMO_SHIFT (1) +#define I2C_SMBRAWISR_MSTTMO_MASK (0x01U << I2C_SMBRAWISR_MSTTMO_SHIFT) +#define I2C_SMBRAWISR_MSTTMO(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBRAWISR_MSTTMO_SHIFT)) & I2C_SMBRAWISR_MSTTMO_MASK) + +#define I2C_SMBRAWISR_SLVTMO_SHIFT (0) +#define I2C_SMBRAWISR_SLVTMO_MASK (0x01U << I2C_SMBRAWISR_SLVTMO_SHIFT) +#define I2C_SMBRAWISR_SLVTMO(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBRAWISR_SLVTMO_SHIFT)) & I2C_SMBRAWISR_SLVTMO_MASK) + +/*! + * @brief I2C_SMB_ICR Register Bit Definition + */ + +#define I2C_SMBICR_CLRSMBALT_SHIFT (10) +#define I2C_SMBICR_CLRSMBALT_MASK (0x01U << I2C_SMBICR_CLRSMBALT_SHIFT) +#define I2C_SMBICR_CLRSMBALT(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBICR_CLRSMBALT_SHIFT)) & I2C_SMBICR_CLRSMBALT_MASK) + +#define I2C_SMBICR_CLRPECNACK_SHIFT (8) +#define I2C_SMBICR_CLRPECNACK_MASK (0x01U << I2C_SMBICR_CLRPECNACK_SHIFT) +#define I2C_SMBICR_CLRPECNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBICR_CLRPECNACK_SHIFT)) & I2C_SMBICR_CLRPECNACK_MASK) + +#define I2C_SMBICR_CLRARPASSGN_SHIFT (7) +#define I2C_SMBICR_CLRARPASSGN_MASK (0x01U << I2C_SMBICR_CLRARPASSGN_SHIFT) +#define I2C_SMBICR_CLRARPASSGN(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBICR_CLRARPASSGN_SHIFT)) & I2C_SMBICR_CLRARPASSGN_MASK) + +#define I2C_SMBICR_CLRARPUDID_SHIFT (6) +#define I2C_SMBICR_CLRARPUDID_MASK (0x01U << I2C_SMBICR_CLRARPUDID_SHIFT) +#define I2C_SMBICR_CLRARPUDID(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBICR_CLRARPUDID_SHIFT)) & I2C_SMBICR_CLRARPUDID_MASK) + +#define I2C_SMBICR_CLRARPRST_SHIFT (5) +#define I2C_SMBICR_CLRARPRST_MASK (0x01U << I2C_SMBICR_CLRARPRST_SHIFT) +#define I2C_SMBICR_CLRARPRST(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBICR_CLRARPRST_SHIFT)) & I2C_SMBICR_CLRARPRST_MASK) + +#define I2C_SMBICR_CLRARPPRE_SHIFT (4) +#define I2C_SMBICR_CLRARPPRE_MASK (0x01U << I2C_SMBICR_CLRARPPRE_SHIFT) +#define I2C_SMBICR_CLRARPPRE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBICR_CLRARPPRE_SHIFT)) & I2C_SMBICR_CLRARPPRE_MASK) + +#define I2C_SMBICR_CLRARPNOTIFY_SHIFT (3) +#define I2C_SMBICR_CLRARPNOTIFY_MASK (0x01U << I2C_SMBICR_CLRARPNOTIFY_SHIFT) +#define I2C_SMBICR_CLRARPNOTIFY(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBICR_CLRARPNOTIFY_SHIFT)) & I2C_SMBICR_CLRARPNOTIFY_MASK) + +#define I2C_SMBICR_CLRARPQUICK_SHIFT (2) +#define I2C_SMBICR_CLRARPQUICK_MASK (0x01U << I2C_SMBICR_CLRARPQUICK_SHIFT) +#define I2C_SMBICR_CLRARPQUICK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBICR_CLRARPQUICK_SHIFT)) & I2C_SMBICR_CLRARPQUICK_MASK) + +#define I2C_SMBICR_CLRMSTTMO_SHIFT (1) +#define I2C_SMBICR_CLRMSTTMO_MASK (0x01U << I2C_SMBICR_CLRMSTTMO_SHIFT) +#define I2C_SMBICR_CLRMSTTMO(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBICR_CLRMSTTMO_SHIFT)) & I2C_SMBICR_CLRMSTTMO_MASK) + +#define I2C_SMBICR_CLRSLVTMO_SHIFT (0) +#define I2C_SMBICR_CLRSLVTMO_MASK (0x01U << I2C_SMBICR_CLRSLVTMO_SHIFT) +#define I2C_SMBICR_CLRSLVTMO(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBICR_CLRSLVTMO_SHIFT)) & I2C_SMBICR_CLRSLVTMO_MASK) + +/*! + * @brief I2C_OPT_SAR Register Bit Definition + */ + +#define I2C_OPTSAR_ADDR_SHIFT (0) +#define I2C_OPTSAR_ADDR_MASK (0x7FU << I2C_OPTSAR_ADDR_SHIFT) +#define I2C_OPTSAR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I2C_OPTSAR_ADDR_SHIFT)) & I2C_OPTSAR_ADDR_MASK) + +/*! + * @brief I2C_SMB_UDID_LSB Register Bit Definition + */ + +#define I2C_SMBUDIDLSB_SMBUDIDLSB_SHIFT (0) +#define I2C_SMBUDIDLSB_SMBUDIDLSB_MASK (0xFFFFFFFFU << I2C_SMBUDIDLSB_SMBUDIDLSB_SHIFT) +#define I2C_SMBUDIDLSB_SMBUDIDLSB(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBUDIDLSB_SMBUDIDLSB_SHIFT)) & I2C_SMBUDIDLSB_SMBUDIDLSB_MASK) + +/*! + * @brief I2C_SMB_UDID_MSB0 Register Bit Definition + */ + +#define I2C_SMBUDIDMSB0_SMBUDIDMSB0_SHIFT (0) +#define I2C_SMBUDIDMSB0_SMBUDIDMSB0_MASK (0xFFFFFFFFU << I2C_SMBUDIDMSB0_SMBUDIDMSB0_SHIFT) +#define I2C_SMBUDIDMSB0_SMBUDIDMSB0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBUDIDMSB0_SMBUDIDMSB0_SHIFT)) & I2C_SMBUDIDMSB0_SMBUDIDMSB0_MASK) + +/*! + * @brief I2C_SMB_UDID_MSB1 Register Bit Definition + */ + +#define I2C_SMBUDIDMSB1_SMBUDIDMSB1_SHIFT (0) +#define I2C_SMBUDIDMSB1_SMBUDIDMSB1_MASK (0xFFFFFFFFU << I2C_SMBUDIDMSB1_SMBUDIDMSB1_SHIFT) +#define I2C_SMBUDIDMSB1_SMBUDIDMSB1(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBUDIDMSB1_SMBUDIDMSB1_SHIFT)) & I2C_SMBUDIDMSB1_SMBUDIDMSB1_MASK) + +/*! + * @brief I2C_SMB_UDID_MSB2 Register Bit Definition + */ + +#define I2C_SMBUDIDMSB2_SMBUDIDMSB2_SHIFT (0) +#define I2C_SMBUDIDMSB2_SMBUDIDMSB2_MASK (0xFFFFFFFFU << I2C_SMBUDIDMSB2_SMBUDIDMSB2_SHIFT) +#define I2C_SMBUDIDMSB2_SMBUDIDMSB2(x) (((uint32_t)(((uint32_t)(x)) << I2C_SMBUDIDMSB2_SMBUDIDMSB2_SHIFT)) & I2C_SMBUDIDMSB2_SMBUDIDMSB2_MASK) + +/*! + * @brief I2C_SLVMASK Register Bit Definition + */ + +#define I2C_SLVMASK_MASK_SHIFT (0) +#define I2C_SLVMASK_MASK_MASK (0x3FFU << I2C_SLVMASK_MASK_SHIFT) +#define I2C_SLVMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVMASK_MASK_SHIFT)) & I2C_SLVMASK_MASK_MASK) + +/*! + * @brief I2C_SLVRCVADDR Register Bit Definition + */ + +#define I2C_SLVRCVADDR_ADDR_SHIFT (0) +#define I2C_SLVRCVADDR_ADDR_MASK (0x3FFU << I2C_SLVRCVADDR_ADDR_SHIFT) +#define I2C_SLVRCVADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVRCVADDR_ADDR_SHIFT)) & I2C_SLVRCVADDR_ADDR_MASK) + +/*! + * @} + */ /* end of group I2C_Register_Masks */ +/****************************************************************************** + *I2C Instance +*******************************************************************************/ + +#define I2C1 ((I2C_Type*)I2C1_BASE) +#define I2C2 ((I2C_Type*)I2C2_BASE) + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + +/*! + * @addtogroup IWDG_Peripheral_Access_Layer IWDG Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * IWDG Type + ******************************************************************************/ +typedef struct { + __IO uint32_t KR; ///< key register offset: 0x00 + __IO uint32_t PR; ///< Prescaler register offset: 0x04 + __IO uint32_t RLR; ///< reload register offset: 0x08 + __IO uint32_t SR; ///< status register offset: 0x0C + __IO uint32_t CR; ///< control register offset: 0x10 + __IO uint32_t IGEN; ///< Interrupt Generation Register offset: 0x14 + __IO uint32_t CNT; ///< count register offset: 0x18 + __IO uint32_t PS; ///< Frequency division count register offset: 0x1c +} IWDG_Type; + +/******************************************************************************* + * IWDG Type + ******************************************************************************/ + +/*! + * @addtogroup IWDG_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief IWDG_KR Register Bit Definition + */ + +#define IWDG_KR_KEY_SHIFT (0) +#define IWDG_KR_KEY_MASK (0xFFFFU << IWDG_KR_KEY_SHIFT) +#define IWDG_KR_KEY(x) (((uint32_t)(((uint32_t)(x)) << IWDG_KR_KEY_SHIFT)) & IWDG_KR_KEY_MASK) + +/*! + * @brief IWDG_PR Register Bit Definition + */ + +#define IWDG_PR_PR_SHIFT (0) +#define IWDG_PR_PR_MASK (0x7U << IWDG_PR_PR_SHIFT) +#define IWDG_PR_PR(x) (((uint32_t)(((uint32_t)(x)) << IWDG_PR_PR_SHIFT)) & IWDG_PR_PR_MASK) + +/*! + * @brief IWDG_RLR Register Bit Definition + */ + +#define IWDG_RLR_RL_SHIFT (0) +#define IWDG_RLR_RL_MASK (0xFFFU << IWDG_RLR_RL_SHIFT) +#define IWDG_RLR_RL(x) (((uint32_t)(((uint32_t)(x)) << IWDG_RLR_RL_SHIFT)) & IWDG_RLR_RL_MASK) + +/*! + * @brief IWDG_SR Register Bit Definition + */ + +#define IWDG_SR_UPDATE_SHIFT (3) +#define IWDG_SR_UPDATE_MASK (0x01U << IWDG_SR_UPDATE_SHIFT) +#define IWDG_SR_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << IWDG_SR_UPDATE_SHIFT)) & IWDG_SR_UPDATE_MASK) + +#define IWDG_SR_IVU_SHIFT (2) +#define IWDG_SR_IVU_MASK (0x01U << IWDG_SR_IVU_SHIFT) +#define IWDG_SR_IVU(x) (((uint32_t)(((uint32_t)(x)) << IWDG_SR_IVU_SHIFT)) & IWDG_SR_IVU_MASK) + +#define IWDG_SR_RVU_SHIFT (1) +#define IWDG_SR_RVU_MASK (0x01U << IWDG_SR_RVU_SHIFT) +#define IWDG_SR_RVU(x) (((uint32_t)(((uint32_t)(x)) << IWDG_SR_RVU_SHIFT)) & IWDG_SR_RVU_MASK) + +#define IWDG_SR_PVU_SHIFT (0) +#define IWDG_SR_PVU_MASK (0x01U << IWDG_SR_PVU_SHIFT) +#define IWDG_SR_PVU(x) (((uint32_t)(((uint32_t)(x)) << IWDG_SR_PVU_SHIFT)) & IWDG_SR_PVU_MASK) + +/*! + * @brief IWDG_CR Register Bit Definition + */ + +#define IWDG_CR_IRQCLR_SHIFT (1) +#define IWDG_CR_IRQCLR_MASK (0x01U << IWDG_CR_IRQCLR_SHIFT) +#define IWDG_CR_IRQCLR(x) (((uint32_t)(((uint32_t)(x)) << IWDG_CR_IRQCLR_SHIFT)) & IWDG_CR_IRQCLR_MASK) + +#define IWDG_CR_IRQSEL_SHIFT (0) +#define IWDG_CR_IRQSEL_MASK (0x01U << IWDG_CR_IRQSEL_SHIFT) +#define IWDG_CR_IRQSEL(x) (((uint32_t)(((uint32_t)(x)) << IWDG_CR_IRQSEL_SHIFT)) & IWDG_CR_IRQSEL_MASK) + +/*! + * @brief IWDG_IGEN Register Bit Definition + */ + +#define IWDG_IGEN_IGEN_SHIFT (0) +#define IWDG_IGEN_IGEN_MASK (0xFFFU << IWDG_IGEN_IGEN_SHIFT) +#define IWDG_IGEN_IGEN(x) (((uint32_t)(((uint32_t)(x)) << IWDG_IGEN_IGEN_SHIFT)) & IWDG_IGEN_IGEN_MASK) + +/*! + * @brief IWDG_CNT Register Bit Definition + */ + +#define IWDG_CNT_IWDGCNT_SHIFT (0) +#define IWDG_CNT_IWDGCNT_MASK (0xFFFU << IWDG_CNT_IWDGCNT_SHIFT) +#define IWDG_CNT_IWDGCNT(x) (((uint32_t)(((uint32_t)(x)) << IWDG_CNT_IWDGCNT_SHIFT)) & IWDG_CNT_IWDGCNT_MASK) + +/*! + * @brief IWDG_PS Register Bit Definition + */ + +#define IWDG_PS_IWDGPS_SHIFT (0) +#define IWDG_PS_IWDGPS_MASK (0xFFU << IWDG_PS_IWDGPS_SHIFT) +#define IWDG_PS_IWDGPS(x) (((uint32_t)(((uint32_t)(x)) << IWDG_PS_IWDGPS_SHIFT)) & IWDG_PS_IWDGPS_MASK) + +/*! + * @} + */ /* end of group IWDG_Register_Masks */ +/****************************************************************************** + *IWDG Instance +*******************************************************************************/ + +#define IWDG ((IWDG_Type*)IWDG_BASE) + +/*! + * @} + */ /* end of group IWDG_Peripheral_Access_Layer */ + + + + +/*! + * @addtogroup LPTIM_Peripheral_Access_Layer LPT Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * LPT Type + ******************************************************************************/ +typedef struct { + __IO uint32_t CFG; ///< LPTIM Configuration Register offset: 0x00 + __IO uint32_t IE; ///< LPTIM Interrupt Enable Register offset: 0x04 + __IO uint32_t IF; ///< LPTIM Interrupt Flag Register offset: 0x08 + __IO uint32_t CTRL; ///< LPTIM Control Register offset: 0x0C + __IO uint32_t CNT; ///< LPTIM count register offset: 0x10 + __IO uint32_t CMP; ///< LPTIM Compare Value Register offset: 0x14 + __IO uint32_t TARGET; ///< LPTIM target value register offset: 0x18 +} LPTIM_Type; + +/******************************************************************************* + * LPT Type + ******************************************************************************/ + +/*! + * @addtogroup LPTIM_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief LPTIM_CFG Register Bit Definition + */ + +#define LPTIM_CFG_FLTEN_SHIFT (15) +#define LPTIM_CFG_FLTEN_MASK (0x01U << LPTIM_CFG_FLTEN_SHIFT) +#define LPTIM_CFG_FLTEN(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_CFG_FLTEN_SHIFT)) & LPTIM_CFG_FLTEN_MASK) + +#define LPTIM_CFG_DIVSEL_SHIFT (8) +#define LPTIM_CFG_DIVSEL_MASK (0x7U << LPTIM_CFG_DIVSEL_SHIFT) +#define LPTIM_CFG_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_CFG_DIVSEL_SHIFT)) & LPTIM_CFG_DIVSEL_MASK) + +#define LPTIM_CFG_TRIGCFG_SHIFT (6) +#define LPTIM_CFG_TRIGCFG_MASK (0x3U << LPTIM_CFG_TRIGCFG_SHIFT) +#define LPTIM_CFG_TRIGCFG(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_CFG_TRIGCFG_SHIFT)) & LPTIM_CFG_TRIGCFG_MASK) + +#define LPTIM_CFG_TRIGSEL_SHIFT (5) +#define LPTIM_CFG_TRIGSEL_MASK (0x01U << LPTIM_CFG_TRIGSEL_SHIFT) +#define LPTIM_CFG_TRIGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_CFG_TRIGSEL_SHIFT)) & LPTIM_CFG_TRIGSEL_MASK) + +#define LPTIM_CFG_POLARITY_SHIFT (4) +#define LPTIM_CFG_POLARITY_MASK (0x01U << LPTIM_CFG_POLARITY_SHIFT) +#define LPTIM_CFG_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_CFG_POLARITY_SHIFT)) & LPTIM_CFG_POLARITY_MASK) + +#define LPTIM_CFG_PWM_SHIFT (3) +#define LPTIM_CFG_PWM_MASK (0x01U << LPTIM_CFG_PWM_SHIFT) +#define LPTIM_CFG_PWM(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_CFG_PWM_SHIFT)) & LPTIM_CFG_PWM_MASK) + +#define LPTIM_CFG_TMODE_SHIFT (1) +#define LPTIM_CFG_TMODE_MASK (0x3U << LPTIM_CFG_TMODE_SHIFT) +#define LPTIM_CFG_TMODE(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_CFG_TMODE_SHIFT)) & LPTIM_CFG_TMODE_MASK) + +#define LPTIM_CFG_MODE_SHIFT (0) +#define LPTIM_CFG_MODE_MASK (0x01U << LPTIM_CFG_MODE_SHIFT) +#define LPTIM_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_CFG_MODE_SHIFT)) & LPTIM_CFG_MODE_MASK) + +/*! + * @brief LPTIM_IE Register Bit Definition + */ + +#define LPTIM_IE_COMPIE_SHIFT (2) +#define LPTIM_IE_COMPIE_MASK (0x01U << LPTIM_IE_COMPIE_SHIFT) +#define LPTIM_IE_COMPIE(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_IE_COMPIE_SHIFT)) & LPTIM_IE_COMPIE_MASK) + +#define LPTIM_IE_TRIGIE_SHIFT (1) +#define LPTIM_IE_TRIGIE_MASK (0x01U << LPTIM_IE_TRIGIE_SHIFT) +#define LPTIM_IE_TRIGIE(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_IE_TRIGIE_SHIFT)) & LPTIM_IE_TRIGIE_MASK) + +#define LPTIM_IE_OVIE_SHIFT (0) +#define LPTIM_IE_OVIE_MASK (0x01U << LPTIM_IE_OVIE_SHIFT) +#define LPTIM_IE_OVIE(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_IE_OVIE_SHIFT)) & LPTIM_IE_OVIE_MASK) + +/*! + * @brief LPTIM_IF Register Bit Definition + */ + +#define LPTIM_IF_COMPIF_SHIFT (2) +#define LPTIM_IF_COMPIF_MASK (0x01U << LPTIM_IF_COMPIF_SHIFT) +#define LPTIM_IF_COMPIF(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_IF_COMPIF_SHIFT)) & LPTIM_IF_COMPIF_MASK) + +#define LPTIM_IF_TRIGIF_SHIFT (1) +#define LPTIM_IF_TRIGIF_MASK (0x01U << LPTIM_IF_TRIGIF_SHIFT) +#define LPTIM_IF_TRIGIF(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_IF_TRIGIF_SHIFT)) & LPTIM_IF_TRIGIF_MASK) + +#define LPTIM_IF_OVIF_SHIFT (0) +#define LPTIM_IF_OVIF_MASK (0x01U << LPTIM_IF_OVIF_SHIFT) +#define LPTIM_IF_OVIF(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_IF_OVIF_SHIFT)) & LPTIM_IF_OVIF_MASK) + +/*! + * @brief LPTIM_CTRL Register Bit Definition + */ + +#define LPTIM_CTRL_LPTEN_SHIFT (0) +#define LPTIM_CTRL_LPTEN_MASK (0x01U << LPTIM_CTRL_LPTEN_SHIFT) +#define LPTIM_CTRL_LPTEN(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_CTRL_LPTEN_SHIFT)) & LPTIM_CTRL_LPTEN_MASK) + +/*! + * @brief LPTIM_CNT Register Bit Definition + */ + +#define LPTIM_CNT_CNT_SHIFT (0) +#define LPTIM_CNT_CNT_MASK (0xFFFFU << LPTIM_CNT_CNT_SHIFT) +#define LPTIM_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_CNT_CNT_SHIFT)) & LPTIM_CNT_CNT_MASK) + +/*! + * @brief LPTIM_CMP Register Bit Definition + */ + +#define LPTIM_CMP_COMPAREREG_SHIFT (0) +#define LPTIM_CMP_COMPAREREG_MASK (0xFFFFU << LPTIM_CMP_COMPAREREG_SHIFT) +#define LPTIM_CMP_COMPAREREG(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_CMP_COMPAREREG_SHIFT)) & LPTIM_CMP_COMPAREREG_MASK) + +/*! + * @brief LPTIM_TARGET Register Bit Definition + */ + +#define LPTIM_TARGET_TARGETREG_SHIFT (0) +#define LPTIM_TARGET_TARGETREG_MASK (0xFFFFU << LPTIM_TARGET_TARGETREG_SHIFT) +#define LPTIM_TARGET_TARGETREG(x) (((uint32_t)(((uint32_t)(x)) << LPTIM_TARGET_TARGETREG_SHIFT)) & LPTIM_TARGET_TARGETREG_MASK) + +/*! + * @} + */ /* end of group LPTIM_Register_Masks */ +/****************************************************************************** + *LPT Instance +*******************************************************************************/ + +#define LPTIM ((LPTIM_Type*)LPTIM_BASE) + +/*! + * @} + */ /* end of group LPTIM_Peripheral_Access_Layer */ + + + + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPU Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * LPU Type + ******************************************************************************/ +typedef struct { + __IO uint32_t LPUBAUD; ///< LPUART Baud Rate Register offset: 0x00 + __IO uint32_t MODU; ///< LPUART Baud Rate Modulation Control Register offset: 0x04 + __IO uint32_t LPUIF; ///< LPUART Interrupt Flag Register offset: 0x08 + __IO uint32_t LPUSTA; ///< LPUART Status Register offset: 0x0C + __IO uint32_t LPUCON; ///< LPUART Control Register offset: 0x10 + __IO uint32_t LPUEN; ///< LPUART transmit and receive enable register offset: 0x14 + __IO uint32_t LPURXD; ///< LPUART receive data register offset: 0x18 + __IO uint32_t LPUTXD; ///< LPUART transmit data register offset: 0x1C + __IO uint32_t COMPARE; ///< LPUART data match register offset: 0x20 + __IO uint32_t WKCKE; ///< LPUART Wakeup Register offset: 0x24 +} LPUART_Type; + +/******************************************************************************* + * LPU Type + ******************************************************************************/ + +/*! + * @addtogroup LPUART_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief LPUART_LPUBAUD Register Bit Definition + */ + +#define LPUART_LPUBAUD_BR_SHIFT (16) +#define LPUART_LPUBAUD_BR_MASK (0xFFFFU << LPUART_LPUBAUD_BR_SHIFT) +#define LPUART_LPUBAUD_BR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUBAUD_BR_SHIFT)) & LPUART_LPUBAUD_BR_MASK) + +#define LPUART_LPUBAUD_BREN_SHIFT (8) +#define LPUART_LPUBAUD_BREN_MASK (0x01U << LPUART_LPUBAUD_BREN_SHIFT) +#define LPUART_LPUBAUD_BREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUBAUD_BREN_SHIFT)) & LPUART_LPUBAUD_BREN_MASK) + +#define LPUART_LPUBAUD_BAUD_SHIFT (0) +#define LPUART_LPUBAUD_BAUD_MASK (0x7U << LPUART_LPUBAUD_BAUD_SHIFT) +#define LPUART_LPUBAUD_BAUD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUBAUD_BAUD_SHIFT)) & LPUART_LPUBAUD_BAUD_MASK) + +/*! + * @brief LPUART_MODU Register Bit Definition + */ + +#define LPUART_MODU_MCTL_SHIFT (0) +#define LPUART_MODU_MCTL_MASK (0xFFFU << LPUART_MODU_MCTL_SHIFT) +#define LPUART_MODU_MCTL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODU_MCTL_SHIFT)) & LPUART_MODU_MCTL_MASK) + +/*! + * @brief LPUART_LPUIF Register Bit Definition + */ + +#define LPUART_LPUIF_TCIF_SHIFT (3) +#define LPUART_LPUIF_TCIF_MASK (0x01U << LPUART_LPUIF_TCIF_SHIFT) +#define LPUART_LPUIF_TCIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUIF_TCIF_SHIFT)) & LPUART_LPUIF_TCIF_MASK) + +#define LPUART_LPUIF_RXNEGIF_SHIFT (2) +#define LPUART_LPUIF_RXNEGIF_MASK (0x01U << LPUART_LPUIF_RXNEGIF_SHIFT) +#define LPUART_LPUIF_RXNEGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUIF_RXNEGIF_SHIFT)) & LPUART_LPUIF_RXNEGIF_MASK) + +#define LPUART_LPUIF_TXIF_SHIFT (1) +#define LPUART_LPUIF_TXIF_MASK (0x01U << LPUART_LPUIF_TXIF_SHIFT) +#define LPUART_LPUIF_TXIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUIF_TXIF_SHIFT)) & LPUART_LPUIF_TXIF_MASK) + +#define LPUART_LPUIF_RXIF_SHIFT (0) +#define LPUART_LPUIF_RXIF_MASK (0x01U << LPUART_LPUIF_RXIF_SHIFT) +#define LPUART_LPUIF_RXIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUIF_RXIF_SHIFT)) & LPUART_LPUIF_RXIF_MASK) + +/*! + * @brief LPUART_LPUSTA Register Bit Definition + */ + +#define LPUART_LPUSTA_START_SHIFT (7) +#define LPUART_LPUSTA_START_MASK (0x01U << LPUART_LPUSTA_START_SHIFT) +#define LPUART_LPUSTA_START(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUSTA_START_SHIFT)) & LPUART_LPUSTA_START_MASK) + +#define LPUART_LPUSTA_PERR_SHIFT (6) +#define LPUART_LPUSTA_PERR_MASK (0x01U << LPUART_LPUSTA_PERR_SHIFT) +#define LPUART_LPUSTA_PERR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUSTA_PERR_SHIFT)) & LPUART_LPUSTA_PERR_MASK) + +#define LPUART_LPUSTA_TC_SHIFT (5) +#define LPUART_LPUSTA_TC_MASK (0x01U << LPUART_LPUSTA_TC_SHIFT) +#define LPUART_LPUSTA_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUSTA_TC_SHIFT)) & LPUART_LPUSTA_TC_MASK) + +#define LPUART_LPUSTA_TXE_SHIFT (4) +#define LPUART_LPUSTA_TXE_MASK (0x01U << LPUART_LPUSTA_TXE_SHIFT) +#define LPUART_LPUSTA_TXE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUSTA_TXE_SHIFT)) & LPUART_LPUSTA_TXE_MASK) + +#define LPUART_LPUSTA_RXF_SHIFT (3) +#define LPUART_LPUSTA_RXF_MASK (0x01U << LPUART_LPUSTA_RXF_SHIFT) +#define LPUART_LPUSTA_RXF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUSTA_RXF_SHIFT)) & LPUART_LPUSTA_RXF_MASK) + +#define LPUART_LPUSTA_MATCH_SHIFT (2) +#define LPUART_LPUSTA_MATCH_MASK (0x01U << LPUART_LPUSTA_MATCH_SHIFT) +#define LPUART_LPUSTA_MATCH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUSTA_MATCH_SHIFT)) & LPUART_LPUSTA_MATCH_MASK) + +#define LPUART_LPUSTA_FERR_SHIFT (1) +#define LPUART_LPUSTA_FERR_MASK (0x01U << LPUART_LPUSTA_FERR_SHIFT) +#define LPUART_LPUSTA_FERR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUSTA_FERR_SHIFT)) & LPUART_LPUSTA_FERR_MASK) + +#define LPUART_LPUSTA_RXOV_SHIFT (0) +#define LPUART_LPUSTA_RXOV_MASK (0x01U << LPUART_LPUSTA_RXOV_SHIFT) +#define LPUART_LPUSTA_RXOV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUSTA_RXOV_SHIFT)) & LPUART_LPUSTA_RXOV_MASK) + +/*! + * @brief LPUART_LPUCON Register Bit Definition + */ + +#define LPUART_LPUCON_TXPOL_SHIFT (12) +#define LPUART_LPUCON_TXPOL_MASK (0x01U << LPUART_LPUCON_TXPOL_SHIFT) +#define LPUART_LPUCON_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUCON_TXPOL_SHIFT)) & LPUART_LPUCON_TXPOL_MASK) + +#define LPUART_LPUCON_RXPOL_SHIFT (11) +#define LPUART_LPUCON_RXPOL_MASK (0x01U << LPUART_LPUCON_RXPOL_SHIFT) +#define LPUART_LPUCON_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUCON_RXPOL_SHIFT)) & LPUART_LPUCON_RXPOL_MASK) + +#define LPUART_LPUCON_PAREN_SHIFT (10) +#define LPUART_LPUCON_PAREN_MASK (0x01U << LPUART_LPUCON_PAREN_SHIFT) +#define LPUART_LPUCON_PAREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUCON_PAREN_SHIFT)) & LPUART_LPUCON_PAREN_MASK) + +#define LPUART_LPUCON_PTYP_SHIFT (9) +#define LPUART_LPUCON_PTYP_MASK (0x01U << LPUART_LPUCON_PTYP_SHIFT) +#define LPUART_LPUCON_PTYP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUCON_PTYP_SHIFT)) & LPUART_LPUCON_PTYP_MASK) + +#define LPUART_LPUCON_SL_SHIFT (8) +#define LPUART_LPUCON_SL_MASK (0x01U << LPUART_LPUCON_SL_SHIFT) +#define LPUART_LPUCON_SL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUCON_SL_SHIFT)) & LPUART_LPUCON_SL_MASK) + +#define LPUART_LPUCON_DL_SHIFT (7) +#define LPUART_LPUCON_DL_MASK (0x01U << LPUART_LPUCON_DL_SHIFT) +#define LPUART_LPUCON_DL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUCON_DL_SHIFT)) & LPUART_LPUCON_DL_MASK) + +#define LPUART_LPUCON_RXEV_SHIFT (5) +#define LPUART_LPUCON_RXEV_MASK (0x3U << LPUART_LPUCON_RXEV_SHIFT) +#define LPUART_LPUCON_RXEV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUCON_RXEV_SHIFT)) & LPUART_LPUCON_RXEV_MASK) + +#define LPUART_LPUCON_ERRIE_SHIFT (4) +#define LPUART_LPUCON_ERRIE_MASK (0x01U << LPUART_LPUCON_ERRIE_SHIFT) +#define LPUART_LPUCON_ERRIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUCON_ERRIE_SHIFT)) & LPUART_LPUCON_ERRIE_MASK) + +#define LPUART_LPUCON_TCIE_SHIFT (3) +#define LPUART_LPUCON_TCIE_MASK (0x01U << LPUART_LPUCON_TCIE_SHIFT) +#define LPUART_LPUCON_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUCON_TCIE_SHIFT)) & LPUART_LPUCON_TCIE_MASK) + +#define LPUART_LPUCON_TXIE_SHIFT (2) +#define LPUART_LPUCON_TXIE_MASK (0x01U << LPUART_LPUCON_TXIE_SHIFT) +#define LPUART_LPUCON_TXIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUCON_TXIE_SHIFT)) & LPUART_LPUCON_TXIE_MASK) + +#define LPUART_LPUCON_NEDET_SHIFT (1) +#define LPUART_LPUCON_NEDET_MASK (0x01U << LPUART_LPUCON_NEDET_SHIFT) +#define LPUART_LPUCON_NEDET(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUCON_NEDET_SHIFT)) & LPUART_LPUCON_NEDET_MASK) + +#define LPUART_LPUCON_RXIE_SHIFT (0) +#define LPUART_LPUCON_RXIE_MASK (0x01U << LPUART_LPUCON_RXIE_SHIFT) +#define LPUART_LPUCON_RXIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUCON_RXIE_SHIFT)) & LPUART_LPUCON_RXIE_MASK) + +/*! + * @brief LPUART_LPUEN Register Bit Definition + */ + +#define LPUART_LPUEN_DMAR_SHIFT (3) +#define LPUART_LPUEN_DMAR_MASK (0x01U << LPUART_LPUEN_DMAR_SHIFT) +#define LPUART_LPUEN_DMAR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUEN_DMAR_SHIFT)) & LPUART_LPUEN_DMAR_MASK) + +#define LPUART_LPUEN_DMAT_SHIFT (2) +#define LPUART_LPUEN_DMAT_MASK (0x01U << LPUART_LPUEN_DMAT_SHIFT) +#define LPUART_LPUEN_DMAT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUEN_DMAT_SHIFT)) & LPUART_LPUEN_DMAT_MASK) + +#define LPUART_LPUEN_RXEN_SHIFT (1) +#define LPUART_LPUEN_RXEN_MASK (0x01U << LPUART_LPUEN_RXEN_SHIFT) +#define LPUART_LPUEN_RXEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUEN_RXEN_SHIFT)) & LPUART_LPUEN_RXEN_MASK) + +#define LPUART_LPUEN_TXEN_SHIFT (0) +#define LPUART_LPUEN_TXEN_MASK (0x01U << LPUART_LPUEN_TXEN_SHIFT) +#define LPUART_LPUEN_TXEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUEN_TXEN_SHIFT)) & LPUART_LPUEN_TXEN_MASK) + +/*! + * @brief LPUART_LPURXD Register Bit Definition + */ + +#define LPUART_LPURXD_DATA_SHIFT (0) +#define LPUART_LPURXD_DATA_MASK (0xFFU << LPUART_LPURXD_DATA_SHIFT) +#define LPUART_LPURXD_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPURXD_DATA_SHIFT)) & LPUART_LPURXD_DATA_MASK) + +/*! + * @brief LPUART_LPUTXD Register Bit Definition + */ + +#define LPUART_LPUTXD_DATA_SHIFT (0) +#define LPUART_LPUTXD_DATA_MASK (0xFFU << LPUART_LPUTXD_DATA_SHIFT) +#define LPUART_LPUTXD_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_LPUTXD_DATA_SHIFT)) & LPUART_LPUTXD_DATA_MASK) + +/*! + * @brief LPUART_COMPARE Register Bit Definition + */ + +#define LPUART_COMPARE_COMPARE_SHIFT (0) +#define LPUART_COMPARE_COMPARE_MASK (0xFFU << LPUART_COMPARE_COMPARE_SHIFT) +#define LPUART_COMPARE_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_COMPARE_COMPARE_SHIFT)) & LPUART_COMPARE_COMPARE_MASK) + +/*! + * @brief LPUART_WKCKE Register Bit Definition + */ + +#define LPUART_WKCKE_WKCKE_SHIFT (0) +#define LPUART_WKCKE_WKCKE_MASK (0x01U << LPUART_WKCKE_WKCKE_SHIFT) +#define LPUART_WKCKE_WKCKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WKCKE_WKCKE_SHIFT)) & LPUART_WKCKE_WKCKE_MASK) + +/*! + * @} + */ /* end of group LPUART_Register_Masks */ +/****************************************************************************** + *LPU Instance +*******************************************************************************/ + +#define LPUART ((LPUART_Type*)LPUART_BASE) + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + + + + +/*! + * @addtogroup MDS_Peripheral_Access_Layer MDS Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * MDS Type + ******************************************************************************/ +typedef struct { + __IO uint32_t TRIGXCR[8]; ///< Trigger Channel x Control Register offset: 0x000 + __IO uint32_t Reserved0[24]; ///< Reserved + __IO uint32_t TRIGCLUXSEL[4]; ///< Trigger channel CLUx logic operation input select register offset: 0x080 + __IO uint32_t Reserved1[12]; ///< Reserved + __IO uint32_t TRIGCLUXCFG[4]; ///< Trigger channel CLUx logic operation input control register offset: 0x080 + __IO uint32_t Reserved2[11]; ///< Reserved + __IO uint32_t SWTRIG; ///< Software Trigger Control Register offset: 0x0FC + __IO uint32_t CONNXCR[7]; ///< Connect Channel x Control Register offset: 0x100 + __IO uint32_t Reserved3[25]; ///< Reserved + __IO uint32_t CONNCLUXSEL[4]; ///< Connection channel CLUx logic operation input control register offset: 0x180 + __IO uint32_t Reserved4[12]; ///< Reserved + __IO uint32_t CONNCLUXCFG[4]; ///< Connection Channel CLUx Logic Operation Configuration Register offset: 0x1C0 +} MDS_Type; + +/******************************************************************************* + * MDS Type + ******************************************************************************/ + +/*! + * @addtogroup MDS_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief MDS_TRIGXCR Register Bit Definition + */ +#define MDS_TRIGXCR_EDGESEL_SHIFT (24) +#define MDS_TRIGXCR_EDGESEL_MASK (0x3U << MDS_TRIGXCR_EDGESEL_SHIFT) +#define MDS_TRIGXCR_EDGESEL(x) (((uint32_t)(((uint32_t)(x)) << MDS_TRIGXCR_EDGESEL_SHIFT)) & MDS_TRIGXCR_EDGESEL_MASK) + +#define MDS_TRIGXCR_CLUSEL_SHIFT (17) +#define MDS_TRIGXCR_CLUSEL_MASK (0x3U << MDS_TRIGXCR_CLUSEL_SHIFT) +#define MDS_TRIGXCR_CLUSEL(x) (((uint32_t)(((uint32_t)(x)) << MDS_TRIGXCR_CLUSEL_SHIFT)) & MDS_TRIGXCR_CLUSEL_MASK) + +#define MDS_TRIGXCR_CLUEN_SHIFT (16) +#define MDS_TRIGXCR_CLUEN_MASK (0x01U << MDS_TRIGXCR_CLUEN_SHIFT) +#define MDS_TRIGXCR_CLUEN(x) (((uint32_t)(((uint32_t)(x)) << MDS_TRIGXCR_CLUEN_SHIFT)) & MDS_TRIGXCR_CLUEN_MASK) + +#define MDS_TRIGXCR_TRGSEL_SHIFT (0) +#define MDS_TRIGXCR_TRGSEL_MASK (0x3FU << MDS_TRIGXCR_TRGSEL_SHIFT) +#define MDS_TRIGXCR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << MDS_TRIGXCR_TRGSEL_SHIFT)) & MDS_TRIGXCR_TRGSEL_MASK) + +/*! + * @brief MDS_TRIG_CLUXSEL Register Bit Definition + */ + +#define MDS_TRIGCLUXSEL_CLUIN3SEL_SHIFT (24) +#define MDS_TRIGCLUXSEL_CLUIN3SEL_MASK (0xFFU << MDS_TRIGCLUXSEL_CLUIN3SEL_SHIFT) +#define MDS_TRIGCLUXSEL_CLUIN3SEL(x) (((uint32_t)(((uint32_t)(x)) << MDS_TRIGCLUXSEL_CLUIN3SEL_SHIFT)) & MDS_TRIGCLUXSEL_CLUIN3SEL_MASK) + +#define MDS_TRIGCLUXSEL_CLUIN2SEL_SHIFT (16) +#define MDS_TRIGCLUXSEL_CLUIN2SEL_MASK (0xFFU << MDS_TRIGCLUXSEL_CLUIN2SEL_SHIFT) +#define MDS_TRIGCLUXSEL_CLUIN2SEL(x) (((uint32_t)(((uint32_t)(x)) << MDS_TRIGCLUXSEL_CLUIN2SEL_SHIFT)) & MDS_TRIGCLUXSEL_CLUIN2SEL_MASK) + +#define MDS_TRIGCLUXSEL_CLUIN1SEL_SHIFT (8) +#define MDS_TRIGCLUXSEL_CLUIN1SEL_MASK (0xFFU << MDS_TRIGCLUXSEL_CLUIN1SEL_SHIFT) +#define MDS_TRIGCLUXSEL_CLUIN1SEL(x) (((uint32_t)(((uint32_t)(x)) << MDS_TRIGCLUXSEL_CLUIN1SEL_SHIFT)) & MDS_TRIGCLUXSEL_CLUIN1SEL_MASK) + +#define MDS_TRIGCLUXSEL_CLUIN0SEL_SHIFT (0) +#define MDS_TRIGCLUXSEL_CLUIN0SEL_MASK (0xFFU << MDS_TRIGCLUXSEL_CLUIN0SEL_SHIFT) +#define MDS_TRIGCLUXSEL_CLUIN0SEL(x) (((uint32_t)(((uint32_t)(x)) << MDS_TRIGCLUXSEL_CLUIN0SEL_SHIFT)) & MDS_TRIGCLUXSEL_CLUIN0SEL_MASK) + +/*! + * @brief MDS_TRIG_CLUXCFG Register Bit Definition + */ + +#define MDS_TRIGCLUXCFG_CLUIN3SED_SHIFT (24) +#define MDS_TRIGCLUXCFG_CLUIN3SED_MASK (0x03U << MDS_TRIGCLUXCFG_CLUIN3SED_SHIFT) +#define MDS_TRIGCLUXCFG_CLUIN3SED(x) (((uint32_t)(((uint32_t)(x)) << MDS_TRIGCLUXCFG_CLUIN3SED_SHIFT)) & MDS_TRIGCLUXCFG_CLUIN3SED_MASK) + +#define MDS_TRIGCLUXCFG_CLUIN2SED_SHIFT (16) +#define MDS_TRIGCLUXCFG_CLUIN2SED_MASK (0x03U << MDS_TRIGCLUXCFG_CLUIN2SED_SHIFT) +#define MDS_TRIGCLUXCFG_CLUIN2SED(x) (((uint32_t)(((uint32_t)(x)) << MDS_TRIGCLUXCFG_CLUIN2SED_SHIFT)) & MDS_TRIGCLUXCFG_CLUIN2SED_MASK) + +#define MDS_TRIGCLUXCFG_CLUIN1SED_SHIFT (8) +#define MDS_TRIGCLUXCFG_CLUIN1SED_MASK (0x03U << MDS_TRIGCLUXCFG_CLUIN1SED_SHIFT) +#define MDS_TRIGCLUXCFG_CLUIN1SED(x) (((uint32_t)(((uint32_t)(x)) << MDS_TRIGCLUXCFG_CLUIN1SED_SHIFT)) & MDS_TRIGCLUXCFG_CLUIN1SED_MASK) + +#define MDS_TRIGCLUXCFG_CLUIN0SED_SHIFT (0) +#define MDS_TRIGCLUXCFG_CLUIN0SED_MASK (0x03U << MDS_TRIGCLUXCFG_CLUIN0SED_SHIFT) +#define MDS_TRIGCLUXCFG_CLUIN0SED(x) (((uint32_t)(((uint32_t)(x)) << MDS_TRIGCLUXCFG_CLUIN0SED_SHIFT)) & MDS_TRIGCLUXCFG_CLUIN0SED_MASK) + +/*! + * @brief MDS_SWTRIG Register Bit Definition + */ + +#define MDS_SWTRIG_SWTRIG_SHIFT (0) +#define MDS_SWTRIG_SWTRIG_MASK (0x01U << MDS_SWTRIG_SWTRIG_SHIFT) +#define MDS_SWTRIG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << MDS_SWTRIG_SWTRIG_SHIFT)) & MDS_SWTRIG_SWTRIG_MASK) + +/*! + * @brief MDS_CONNXCR Register Bit Definition + */ + +#define MDS_CONNXCR_CLUSEL_SHIFT (17) +#define MDS_CONNXCR_CLUSEL_MASK (0x3U << MDS_CONNXCR_CLUSEL_SHIFT) +#define MDS_CONNXCR_CLUSEL(x) (((uint32_t)(((uint32_t)(x)) << MDS_CONNXCR_CLUSEL_SHIFT)) & MDS_CONNXCR_CLUSEL_MASK) + +#define MDS_CONNXCR_CLUEN_SHIFT (16) +#define MDS_CONNXCR_CLUEN_MASK (0x01U << MDS_CONNXCR_CLUEN_SHIFT) +#define MDS_CONNXCR_CLUEN(x) (((uint32_t)(((uint32_t)(x)) << MDS_CONNXCR_CLUEN_SHIFT)) & MDS_CONNXCR_CLUEN_MASK) + +#define MDS_CONNXCR_TRGSEL_SHIFT (0) +#define MDS_CONNXCR_TRGSEL_MASK (0x3FU << MDS_CONNXCR_TRGSEL_SHIFT) +#define MDS_CONNXCR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << MDS_CONNXCR_TRGSEL_SHIFT)) & MDS_CONNXCR_TRGSEL_MASK) + +/*! + * @brief MDS_CONN_CLUXSEL Register Bit Definition + */ + +#define MDS_CONNCLUXSEL_CLUIN3SEL_SHIFT (24) +#define MDS_CONNCLUXSEL_CLUIN3SEL_MASK (0xFFU << MDS_CONNCLUXSEL_CLUIN3SEL_SHIFT) +#define MDS_CONNCLUXSEL_CLUIN3SEL(x) (((uint32_t)(((uint32_t)(x)) << MDS_CONNCLUXSEL_CLUIN3SEL_SHIFT)) & MDS_CONNCLUXSEL_CLUIN3SEL_MASK) + +#define MDS_CONNCLUXSEL_CLUIN2SEL_SHIFT (16) +#define MDS_CONNCLUXSEL_CLUIN2SEL_MASK (0xFFU << MDS_CONNCLUXSEL_CLUIN2SEL_SHIFT) +#define MDS_CONNCLUXSEL_CLUIN2SEL(x) (((uint32_t)(((uint32_t)(x)) << MDS_CONNCLUXSEL_CLUIN2SEL_SHIFT)) & MDS_CONNCLUXSEL_CLUIN2SEL_MASK) + +#define MDS_CONNCLUXSEL_CLUIN1SEL_SHIFT (8) +#define MDS_CONNCLUXSEL_CLUIN1SEL_MASK (0xFFU << MDS_CONNCLUXSEL_CLUIN1SEL_SHIFT) +#define MDS_CONNCLUXSEL_CLUIN1SEL(x) (((uint32_t)(((uint32_t)(x)) << MDS_CONNCLUXSEL_CLUIN1SEL_SHIFT)) & MDS_CONNCLUXSEL_CLUIN1SEL_MASK) + +#define MDS_CONNCLUXSEL_CLUIN0SEL_SHIFT (0) +#define MDS_CONNCLUXSEL_CLUIN0SEL_MASK (0xFFU << MDS_CONNCLUXSEL_CLUIN0SEL_SHIFT) +#define MDS_CONNCLUXSEL_CLUIN0SEL(x) (((uint32_t)(((uint32_t)(x)) << MDS_CONNCLUXSEL_CLUIN0SEL_SHIFT)) & MDS_CONNCLUXSEL_CLUIN0SEL_MASK) + +/*! + * @brief MDS_CONN_CLUXCFG Register Bit Definition + */ + +#define MDS_CONNCLUXCFG_INV3_SHIFT (11) +#define MDS_CONNCLUXCFG_INV3_MASK (0x01U << MDS_CONNCLUXCFG_INV3_SHIFT) +#define MDS_CONNCLUXCFG_INV3(x) (((uint32_t)(((uint32_t)(x)) << MDS_CONNCLUXCFG_INV3_SHIFT)) & MDS_CONNCLUXCFG_INV3_MASK) + +#define MDS_CONNCLUXCFG_INV2_SHIFT (10) +#define MDS_CONNCLUXCFG_INV2_MASK (0x01U << MDS_CONNCLUXCFG_INV2_SHIFT) +#define MDS_CONNCLUXCFG_INV2(x) (((uint32_t)(((uint32_t)(x)) << MDS_CONNCLUXCFG_INV2_SHIFT)) & MDS_CONNCLUXCFG_INV2_MASK) + +#define MDS_CONNCLUXCFG_INV1_SHIFT (9) +#define MDS_CONNCLUXCFG_INV1_MASK (0x01U << MDS_CONNCLUXCFG_INV1_SHIFT) +#define MDS_CONNCLUXCFG_INV1(x) (((uint32_t)(((uint32_t)(x)) << MDS_CONNCLUXCFG_INV1_SHIFT)) & MDS_CONNCLUXCFG_INV1_MASK) + +#define MDS_CONNCLUXCFG_INV0_SHIFT (8) +#define MDS_CONNCLUXCFG_INV0_MASK (0x01U << MDS_CONNCLUXCFG_INV0_SHIFT) +#define MDS_CONNCLUXCFG_INV0(x) (((uint32_t)(((uint32_t)(x)) << MDS_CONNCLUXCFG_INV0_SHIFT)) & MDS_CONNCLUXCFG_INV0_MASK) + +#define MDS_CONNCLUXCFG_CLMODE_SHIFT (0) +#define MDS_CONNCLUXCFG_CLMODE_MASK (0x3U << MDS_CONNCLUXCFG_CLMODE_SHIFT) +#define MDS_CONNCLUXCFG_CLMODE(x) (((uint32_t)(((uint32_t)(x)) << MDS_CONNCLUXCFG_CLMODE_SHIFT)) & MDS_CONNCLUXCFG_CLMODE_MASK) + +/*! + * @} + */ /* end of group MDS_Register_Masks */ +/****************************************************************************** + *MDS Instance +*******************************************************************************/ + +#define MDS ((MDS_Type*)MDS_BASE) + +/*! + * @} + */ /* end of group MDS_Peripheral_Access_Layer */ + +/*! + * @addtogroup PWR_Peripheral_Access_Layer PWR Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * PWR Type + ******************************************************************************/ +typedef struct { + __IO uint32_t CR1; ///< Power Control Register 1 offset: 0x00 + __IO uint32_t CSR; ///< Power Control Status Register offset: 0x04 + __IO uint32_t CR2; ///< Power Control Register 2 offset: 0x08 + __IO uint32_t CR3; ///< Power Control Register 3 offset: 0x0C + __IO uint32_t CR4; ///< Power Control Register 4 offset: 0x10 + __IO uint32_t CR5; ///< Power Control Register 5 offset: 0x14 + __IO uint32_t CR6; ///< Power Control Register 6 offset: 0x18 + __IO uint32_t SR; ///< Power Status Register offset: 0x1C + __IO uint32_t SCR; ///< Power Status Clear Register offset: 0x20 + __IO uint32_t CFGR; ///< Power Configuration Register offset: 0x24 +} PWR_Type; + +/******************************************************************************* + * PWR Type + ******************************************************************************/ + +/*! + * @addtogroup PWR_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief PWR_CR1 Register Bit Definition + */ + +#define PWR_CR1_VOS_SHIFT (14) +#define PWR_CR1_VOS_MASK (0x3U << PWR_CR1_VOS_SHIFT) +#define PWR_CR1_VOS(x) (((uint32_t)(((uint32_t)(x)) << PWR_CR1_VOS_SHIFT)) & PWR_CR1_VOS_MASK) + +#define PWR_CR1_LPR_SHIFT (13) +#define PWR_CR1_LPR_MASK (0x01U << PWR_CR1_LPR_SHIFT) +#define PWR_CR1_LPR(x) (((uint32_t)(((uint32_t)(x)) << PWR_CR1_LPR_SHIFT)) & PWR_CR1_LPR_MASK) + +#define PWR_CR1_CSBF_SHIFT (3) +#define PWR_CR1_CSBF_MASK (0x01U << PWR_CR1_CSBF_SHIFT) +#define PWR_CR1_CSBF(x) (((uint32_t)(((uint32_t)(x)) << PWR_CR1_CSBF_SHIFT)) & PWR_CR1_CSBF_MASK) + +#define PWR_CR1_PDDS_SHIFT (1) +#define PWR_CR1_PDDS_MASK (0x01U << PWR_CR1_PDDS_SHIFT) +#define PWR_CR1_PDDS(x) (((uint32_t)(((uint32_t)(x)) << PWR_CR1_PDDS_SHIFT)) & PWR_CR1_PDDS_MASK) + +#define PWR_CR1_LPDS_SHIFT (0) +#define PWR_CR1_LPDS_MASK (0x01U << PWR_CR1_LPDS_SHIFT) +#define PWR_CR1_LPDS(x) (((uint32_t)(((uint32_t)(x)) << PWR_CR1_LPDS_SHIFT)) & PWR_CR1_LPDS_MASK) + +/*! + * @brief PWR_CSR Register Bit Definition + */ + +#define PWR_CSR_VOSRDY_SHIFT (14) +#define PWR_CSR_VOSRDY_MASK (0x01U << PWR_CSR_VOSRDY_SHIFT) +#define PWR_CSR_VOSRDY(x) (((uint32_t)(((uint32_t)(x)) << PWR_CSR_VOSRDY_SHIFT)) & PWR_CSR_VOSRDY_MASK) + +#define PWR_CSR_SBF_SHIFT (1) +#define PWR_CSR_SBF_MASK (0x01U << PWR_CSR_SBF_SHIFT) +#define PWR_CSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << PWR_CSR_SBF_SHIFT)) & PWR_CSR_SBF_MASK) + +/*! + * @brief PWR_CR2 Register Bit Definition + */ + +#define PWR_CR2_EWUP_SHIFT (0) +#define PWR_CR2_EWUP_MASK (0x3FU << PWR_CR2_EWUP_SHIFT) +#define PWR_CR2_EWUP(x) (((uint32_t)(((uint32_t)(x)) << PWR_CR2_EWUP_SHIFT)) & PWR_CR2_EWUP_MASK) + +/*! + * @brief PWR_CR3 Register Bit Definition + */ + +#define PWR_CR3_WP_SHIFT (0) +#define PWR_CR3_WP_MASK (0x3FU << PWR_CR3_WP_SHIFT) +#define PWR_CR3_WP(x) (((uint32_t)(((uint32_t)(x)) << PWR_CR3_WP_SHIFT)) & PWR_CR3_WP_MASK) + +/*! + * @brief PWR_CR4 Register Bit Definition + */ + +#define PWR_CR4_FILTCNT0_SHIFT (8) +#define PWR_CR4_FILTCNT0_MASK (0xFFU << PWR_CR4_FILTCNT0_SHIFT) +#define PWR_CR4_FILTCNT0(x) (((uint32_t)(((uint32_t)(x)) << PWR_CR4_FILTCNT0_SHIFT)) & PWR_CR4_FILTCNT0_MASK) + +#define PWR_CR4_FILTF0_SHIFT (4) +#define PWR_CR4_FILTF0_MASK (0x01U << PWR_CR4_FILTF0_SHIFT) +#define PWR_CR4_FILTF0(x) (((uint32_t)(((uint32_t)(x)) << PWR_CR4_FILTF0_SHIFT)) & PWR_CR4_FILTF0_MASK) + +#define PWR_CR4_FILTE0_SHIFT (2) +#define PWR_CR4_FILTE0_MASK (0x3U << PWR_CR4_FILTE0_SHIFT) +#define PWR_CR4_FILTE0(x) (((uint32_t)(((uint32_t)(x)) << PWR_CR4_FILTE0_SHIFT)) & PWR_CR4_FILTE0_MASK) + +#define PWR_CR4_FILTSEL0_SHIFT (0) +#define PWR_CR4_FILTSEL0_MASK (0x3U << PWR_CR4_FILTSEL0_SHIFT) +#define PWR_CR4_FILTSEL0(x) (((uint32_t)(((uint32_t)(x)) << PWR_CR4_FILTSEL0_SHIFT)) & PWR_CR4_FILTSEL0_MASK) + +/*! + * @brief PWR_CR5 Register Bit Definition + */ + +#define PWR_CR5_FILTCNT1_SHIFT (8) +#define PWR_CR5_FILTCNT1_MASK (0xFFU << PWR_CR5_FILTCNT1_SHIFT) +#define PWR_CR5_FILTCNT1(x) (((uint32_t)(((uint32_t)(x)) << PWR_CR5_FILTCNT1_SHIFT)) & PWR_CR5_FILTCNT1_MASK) + +#define PWR_CR5_FILTF1_SHIFT (4) +#define PWR_CR5_FILTF1_MASK (0x01U << PWR_CR5_FILTF1_SHIFT) +#define PWR_CR5_FILTF1(x) (((uint32_t)(((uint32_t)(x)) << PWR_CR5_FILTF1_SHIFT)) & PWR_CR5_FILTF1_MASK) + +#define PWR_CR5_FILTE1_SHIFT (2) +#define PWR_CR5_FILTE1_MASK (0x3U << PWR_CR5_FILTE1_SHIFT) +#define PWR_CR5_FILTE1(x) (((uint32_t)(((uint32_t)(x)) << PWR_CR5_FILTE1_SHIFT)) & PWR_CR5_FILTE1_MASK) + +#define PWR_CR5_FILTSEL1_SHIFT (0) +#define PWR_CR5_FILTSEL1_MASK (0x3U << PWR_CR5_FILTSEL1_SHIFT) +#define PWR_CR5_FILTSEL1(x) (((uint32_t)(((uint32_t)(x)) << PWR_CR5_FILTSEL1_SHIFT)) & PWR_CR5_FILTSEL1_MASK) + +/*! + * @brief PWR_CR6 Register Bit Definition + */ + +#define PWR_CR6_STDBYFSWK_SHIFT (0) +#define PWR_CR6_STDBYFSWK_MASK (0x7U << PWR_CR6_STDBYFSWK_SHIFT) +#define PWR_CR6_STDBYFSWK(x) (((uint32_t)(((uint32_t)(x)) << PWR_CR6_STDBYFSWK_SHIFT)) & PWR_CR6_STDBYFSWK_MASK) + +/*! + * @brief PWR_SR Register Bit Definition + */ + +#define PWR_SR_WUF_SHIFT (0) +#define PWR_SR_WUF_MASK (0x3FU << PWR_SR_WUF_SHIFT) +#define PWR_SR_WUF(x) (((uint32_t)(((uint32_t)(x)) << PWR_SR_WUF_SHIFT)) & PWR_SR_WUF_MASK) + +/*! + * @brief PWR_SCR Register Bit Definition + */ + +#define PWR_SCR_CWUF_SHIFT (0) +#define PWR_SCR_CWUF_MASK (0x3FU << PWR_SCR_CWUF_SHIFT) +#define PWR_SCR_CWUF(x) (((uint32_t)(((uint32_t)(x)) << PWR_SCR_CWUF_SHIFT)) & PWR_SCR_CWUF_MASK) + +/*! + * @brief PWR_CFGR Register Bit Definition + */ + +#define PWR_CFGR_LSICAL_SHIFT (5) +#define PWR_CFGR_LSICAL_MASK (0x1FU << PWR_CFGR_LSICAL_SHIFT) +#define PWR_CFGR_LSICAL(x) (((uint32_t)(((uint32_t)(x)) << PWR_CFGR_LSICAL_SHIFT)) & PWR_CFGR_LSICAL_MASK) + +#define PWR_CFGR_LSICALSEL_SHIFT (0) +#define PWR_CFGR_LSICALSEL_MASK (0x1FU << PWR_CFGR_LSICALSEL_SHIFT) +#define PWR_CFGR_LSICALSEL(x) (((uint32_t)(((uint32_t)(x)) << PWR_CFGR_LSICALSEL_SHIFT)) & PWR_CFGR_LSICALSEL_MASK) + +/*! + * @} + */ /* end of group PWR_Register_Masks */ +/****************************************************************************** + *PWR Instance +*******************************************************************************/ + +#define PWR ((PWR_Type*)PWR_BASE) + +/*! + * @} + */ /* end of group PWR_Peripheral_Access_Layer */ + +/*! + * @addtogroup QSPI_Peripheral_Access_Layer QSPI Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * QSPI Type + ******************************************************************************/ +typedef struct { + __IO uint32_t CR; ///< control register offset: 0x00 + __IO uint32_t SR; ///< status register offset: 0x04 + __IO uint32_t DMCR; ///< Direct Mode Control Register offset: 0x08 + __IO uint32_t IMCR; ///< Indirect Mode Control Register offset: 0x0C + __IO uint32_t DABR; ///< Direct Mode Interactive Byte Register offset: 0x10 + __IO uint32_t IABR; ///< Indirect Mode Interactive Byte Register offset: 0x14 + __IO uint32_t IADR; ///< Indirect Mode Address Register offset: 0x18 + __IO uint32_t IDFR; ///< Indirect Mode Data FIFO Register offset: 0x1C + __IO uint32_t IDLR; ///< Indirect Mode Data Length Register offset: 0x20 + __IO uint32_t IWCR; ///< Indirect Mode Wait Count Register offset: 0x24 + __IO uint32_t IDER; ///< Interrupt DMA Enable Register offset: 0x28 +} QSPI_Type; + +/******************************************************************************* + * QSPI Type + ******************************************************************************/ + +/*! + * @addtogroup QSPI_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief QSPI_CR Register Bit Definition + */ + +#define QSPI_CR_SCKDIV_SHIFT (24) +#define QSPI_CR_SCKDIV_MASK (0x3FU << QSPI_CR_SCKDIV_SHIFT) +#define QSPI_CR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CR_SCKDIV_SHIFT)) & QSPI_CR_SCKDIV_MASK) + +#define QSPI_CR_CSRHT_SHIFT (16) +#define QSPI_CR_CSRHT_MASK (0x7U << QSPI_CR_CSRHT_SHIFT) +#define QSPI_CR_CSRHT(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CR_CSRHT_SHIFT)) & QSPI_CR_CSRHT_MASK) + +#define QSPI_CR_XIPMODE_SHIFT (5) +#define QSPI_CR_XIPMODE_MASK (0x01U << QSPI_CR_XIPMODE_SHIFT) +#define QSPI_CR_XIPMODE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CR_XIPMODE_SHIFT)) & QSPI_CR_XIPMODE_MASK) + +#define QSPI_CR_SCKMODE_SHIFT (4) +#define QSPI_CR_SCKMODE_MASK (0x01U << QSPI_CR_SCKMODE_SHIFT) +#define QSPI_CR_SCKMODE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CR_SCKMODE_SHIFT)) & QSPI_CR_SCKMODE_MASK) + +#define QSPI_CR_OPMODE_SHIFT (0) +#define QSPI_CR_OPMODE_MASK (0x3U << QSPI_CR_OPMODE_SHIFT) +#define QSPI_CR_OPMODE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CR_OPMODE_SHIFT)) & QSPI_CR_OPMODE_MASK) + +/*! + * @brief QSPI_SR Register Bit Definition + */ + +#define QSPI_SR_DEPTH_SHIFT (24) +#define QSPI_SR_DEPTH_MASK (0xFU << QSPI_SR_DEPTH_SHIFT) +#define QSPI_SR_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << QSPI_SR_DEPTH_SHIFT)) & QSPI_SR_DEPTH_MASK) + +#define QSPI_SR_LEVEL_SHIFT (12) +#define QSPI_SR_LEVEL_MASK (0xFU << QSPI_SR_LEVEL_SHIFT) +#define QSPI_SR_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << QSPI_SR_LEVEL_SHIFT)) & QSPI_SR_LEVEL_MASK) + +#define QSPI_SR_FULL_SHIFT (9) +#define QSPI_SR_FULL_MASK (0x01U << QSPI_SR_FULL_SHIFT) +#define QSPI_SR_FULL(x) (((uint32_t)(((uint32_t)(x)) << QSPI_SR_FULL_SHIFT)) & QSPI_SR_FULL_MASK) + +#define QSPI_SR_EMPTY_SHIFT (8) +#define QSPI_SR_EMPTY_MASK (0x01U << QSPI_SR_EMPTY_SHIFT) +#define QSPI_SR_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << QSPI_SR_EMPTY_SHIFT)) & QSPI_SR_EMPTY_MASK) + +#define QSPI_SR_XIPST_SHIFT (6) +#define QSPI_SR_XIPST_MASK (0x01U << QSPI_SR_XIPST_SHIFT) +#define QSPI_SR_XIPST(x) (((uint32_t)(((uint32_t)(x)) << QSPI_SR_XIPST_SHIFT)) & QSPI_SR_XIPST_MASK) + +#define QSPI_SR_BUSY_SHIFT (5) +#define QSPI_SR_BUSY_MASK (0x01U << QSPI_SR_BUSY_SHIFT) +#define QSPI_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << QSPI_SR_BUSY_SHIFT)) & QSPI_SR_BUSY_MASK) + +#define QSPI_SR_TCF_SHIFT (4) +#define QSPI_SR_TCF_MASK (0x01U << QSPI_SR_TCF_SHIFT) +#define QSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << QSPI_SR_TCF_SHIFT)) & QSPI_SR_TCF_MASK) + +#define QSPI_SR_OPCRCF_SHIFT (2) +#define QSPI_SR_OPCRCF_MASK (0x01U << QSPI_SR_OPCRCF_SHIFT) +#define QSPI_SR_OPCRCF(x) (((uint32_t)(((uint32_t)(x)) << QSPI_SR_OPCRCF_SHIFT)) & QSPI_SR_OPCRCF_MASK) + +#define QSPI_SR_CUROP_SHIFT (0) +#define QSPI_SR_CUROP_MASK (0x3U << QSPI_SR_CUROP_SHIFT) +#define QSPI_SR_CUROP(x) (((uint32_t)(((uint32_t)(x)) << QSPI_SR_CUROP_SHIFT)) & QSPI_SR_CUROP_MASK) + +/*! + * @brief QSPI_DMCR Register Bit Definition + */ + +#define QSPI_DMCR_NUMDC_SHIFT (24) +#define QSPI_DMCR_NUMDC_MASK (0x1FU << QSPI_DMCR_NUMDC_SHIFT) +#define QSPI_DMCR_NUMDC(x) (((uint32_t)(((uint32_t)(x)) << QSPI_DMCR_NUMDC_SHIFT)) & QSPI_DMCR_NUMDC_MASK) + +#define QSPI_DMCR_RXDLY_SHIFT (22) +#define QSPI_DMCR_RXDLY_MASK (0x3U << QSPI_DMCR_RXDLY_SHIFT) +#define QSPI_DMCR_RXDLY(x) (((uint32_t)(((uint32_t)(x)) << QSPI_DMCR_RXDLY_SHIFT)) & QSPI_DMCR_RXDLY_MASK) + +#define QSPI_DMCR_DSIZE_SHIFT (20) +#define QSPI_DMCR_DSIZE_MASK (0x3U << QSPI_DMCR_DSIZE_SHIFT) +#define QSPI_DMCR_DSIZE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_DMCR_DSIZE_SHIFT)) & QSPI_DMCR_DSIZE_MASK) + +#define QSPI_DMCR_DMODE_SHIFT (18) +#define QSPI_DMCR_DMODE_MASK (0x3U << QSPI_DMCR_DMODE_SHIFT) +#define QSPI_DMCR_DMODE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_DMCR_DMODE_SHIFT)) & QSPI_DMCR_DMODE_MASK) + +#define QSPI_DMCR_ABSIZE_SHIFT (16) +#define QSPI_DMCR_ABSIZE_MASK (0x3U << QSPI_DMCR_ABSIZE_SHIFT) +#define QSPI_DMCR_ABSIZE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_DMCR_ABSIZE_SHIFT)) & QSPI_DMCR_ABSIZE_MASK) + +#define QSPI_DMCR_ABMODE_SHIFT (14) +#define QSPI_DMCR_ABMODE_MASK (0x3U << QSPI_DMCR_ABMODE_SHIFT) +#define QSPI_DMCR_ABMODE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_DMCR_ABMODE_SHIFT)) & QSPI_DMCR_ABMODE_MASK) + +#define QSPI_DMCR_ADSIZE_SHIFT (12) +#define QSPI_DMCR_ADSIZE_MASK (0x3U << QSPI_DMCR_ADSIZE_SHIFT) +#define QSPI_DMCR_ADSIZE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_DMCR_ADSIZE_SHIFT)) & QSPI_DMCR_ADSIZE_MASK) + +#define QSPI_DMCR_ADMODE_SHIFT (10) +#define QSPI_DMCR_ADMODE_MASK (0x3U << QSPI_DMCR_ADMODE_SHIFT) +#define QSPI_DMCR_ADMODE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_DMCR_ADMODE_SHIFT)) & QSPI_DMCR_ADMODE_MASK) + +#define QSPI_DMCR_IMODE_SHIFT (8) +#define QSPI_DMCR_IMODE_MASK (0x3U << QSPI_DMCR_IMODE_SHIFT) +#define QSPI_DMCR_IMODE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_DMCR_IMODE_SHIFT)) & QSPI_DMCR_IMODE_MASK) + +#define QSPI_DMCR_INST_SHIFT (0) +#define QSPI_DMCR_INST_MASK (0xFFU << QSPI_DMCR_INST_SHIFT) +#define QSPI_DMCR_INST(x) (((uint32_t)(((uint32_t)(x)) << QSPI_DMCR_INST_SHIFT)) & QSPI_DMCR_INST_MASK) + +/*! + * @brief QSPI_IMCR Register Bit Definition + */ + +#define QSPI_IMCR_IDMODE_SHIFT (30) +#define QSPI_IMCR_IDMODE_MASK (0x01U << QSPI_IMCR_IDMODE_SHIFT) +#define QSPI_IMCR_IDMODE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMCR_IDMODE_SHIFT)) & QSPI_IMCR_IDMODE_MASK) + +#define QSPI_IMCR_XIPIM_SHIFT (29) +#define QSPI_IMCR_XIPIM_MASK (0x01U << QSPI_IMCR_XIPIM_SHIFT) +#define QSPI_IMCR_XIPIM(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMCR_XIPIM_SHIFT)) & QSPI_IMCR_XIPIM_MASK) + +#define QSPI_IMCR_NUMDC_SHIFT (24) +#define QSPI_IMCR_NUMDC_MASK (0x1FU << QSPI_IMCR_NUMDC_SHIFT) +#define QSPI_IMCR_NUMDC(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMCR_NUMDC_SHIFT)) & QSPI_IMCR_NUMDC_MASK) + +#define QSPI_IMCR_RXDLY_SHIFT (22) +#define QSPI_IMCR_RXDLY_MASK (0x3U << QSPI_IMCR_RXDLY_SHIFT) +#define QSPI_IMCR_RXDLY(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMCR_RXDLY_SHIFT)) & QSPI_IMCR_RXDLY_MASK) + +#define QSPI_IMCR_DSIZE_SHIFT (20) +#define QSPI_IMCR_DSIZE_MASK (0x3U << QSPI_IMCR_DSIZE_SHIFT) +#define QSPI_IMCR_DSIZE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMCR_DSIZE_SHIFT)) & QSPI_IMCR_DSIZE_MASK) + +#define QSPI_IMCR_DMODE_SHIFT (18) +#define QSPI_IMCR_DMODE_MASK (0x3U << QSPI_IMCR_DMODE_SHIFT) +#define QSPI_IMCR_DMODE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMCR_DMODE_SHIFT)) & QSPI_IMCR_DMODE_MASK) + +#define QSPI_IMCR_ABSIZE_SHIFT (16) +#define QSPI_IMCR_ABSIZE_MASK (0x3U << QSPI_IMCR_ABSIZE_SHIFT) +#define QSPI_IMCR_ABSIZE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMCR_ABSIZE_SHIFT)) & QSPI_IMCR_ABSIZE_MASK) + +#define QSPI_IMCR_ABMODE_SHIFT (14) +#define QSPI_IMCR_ABMODE_MASK (0x3U << QSPI_IMCR_ABMODE_SHIFT) +#define QSPI_IMCR_ABMODE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMCR_ABMODE_SHIFT)) & QSPI_IMCR_ABMODE_MASK) + +#define QSPI_IMCR_ADSIZE_SHIFT (12) +#define QSPI_IMCR_ADSIZE_MASK (0x3U << QSPI_IMCR_ADSIZE_SHIFT) +#define QSPI_IMCR_ADSIZE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMCR_ADSIZE_SHIFT)) & QSPI_IMCR_ADSIZE_MASK) + +#define QSPI_IMCR_ADMODE_SHIFT (10) +#define QSPI_IMCR_ADMODE_MASK (0x3U << QSPI_IMCR_ADMODE_SHIFT) +#define QSPI_IMCR_ADMODE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMCR_ADMODE_SHIFT)) & QSPI_IMCR_ADMODE_MASK) + +#define QSPI_IMCR_IMODE_SHIFT (8) +#define QSPI_IMCR_IMODE_MASK (0x3U << QSPI_IMCR_IMODE_SHIFT) +#define QSPI_IMCR_IMODE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMCR_IMODE_SHIFT)) & QSPI_IMCR_IMODE_MASK) + +#define QSPI_IMCR_INST_SHIFT (0) +#define QSPI_IMCR_INST_MASK (0xFFU << QSPI_IMCR_INST_SHIFT) +#define QSPI_IMCR_INST(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMCR_INST_SHIFT)) & QSPI_IMCR_INST_MASK) + +/*! + * @brief QSPI_DABR Register Bit Definition + */ + +#define QSPI_DABR_DALT_SHIFT (0) +#define QSPI_DABR_DALT_MASK (0xFFFFFFFFU << QSPI_DABR_DALT_SHIFT) +#define QSPI_DABR_DALT(x) (((uint32_t)(((uint32_t)(x)) << QSPI_DABR_DALT_SHIFT)) & QSPI_DABR_DALT_MASK) + +/*! + * @brief QSPI_IABR Register Bit Definition + */ + +#define QSPI_IABR_IALT_SHIFT (0) +#define QSPI_IABR_IALT_MASK (0xFFFFFFFFU << QSPI_IABR_IALT_SHIFT) +#define QSPI_IABR_IALT(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IABR_IALT_SHIFT)) & QSPI_IABR_IALT_MASK) + +/*! + * @brief QSPI_IADR Register Bit Definition + */ + +#define QSPI_IADR_IADDR_SHIFT (0) +#define QSPI_IADR_IADDR_MASK (0xFFFFFFFFU << QSPI_IADR_IADDR_SHIFT) +#define QSPI_IADR_IADDR(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IADR_IADDR_SHIFT)) & QSPI_IADR_IADDR_MASK) + +/*! + * @brief QSPI_IDFR Register Bit Definition + */ + +#define QSPI_IDFR_IDATA_SHIFT (0) +#define QSPI_IDFR_IDATA_MASK (0xFFFFFFFFU << QSPI_IDFR_IDATA_SHIFT) +#define QSPI_IDFR_IDATA(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IDFR_IDATA_SHIFT)) & QSPI_IDFR_IDATA_MASK) + +/*! + * @brief QSPI_IDLR Register Bit Definition + */ + +#define QSPI_IDLR_IDLEN_SHIFT (0) +#define QSPI_IDLR_IDLEN_MASK (0xFFFFFU << QSPI_IDLR_IDLEN_SHIFT) +#define QSPI_IDLR_IDLEN(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IDLR_IDLEN_SHIFT)) & QSPI_IDLR_IDLEN_MASK) + +/*! + * @brief QSPI_IWCR Register Bit Definition + */ + +#define QSPI_IWCR_IWCNT_SHIFT (0) +#define QSPI_IWCR_IWCNT_MASK (0x3FFFFFFFU << QSPI_IWCR_IWCNT_SHIFT) +#define QSPI_IWCR_IWCNT(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IWCR_IWCNT_SHIFT)) & QSPI_IWCR_IWCNT_MASK) + +/*! + * @brief QSPI_IDER Register Bit Definition + */ + +#define QSPI_IDER_FULLDMAEN_SHIFT (15) +#define QSPI_IDER_FULLDMAEN_MASK (0x01U << QSPI_IDER_FULLDMAEN_SHIFT) +#define QSPI_IDER_FULLDMAEN(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IDER_FULLDMAEN_SHIFT)) & QSPI_IDER_FULLDMAEN_MASK) + +#define QSPI_IDER_EMPTYDMAEN_SHIFT (14) +#define QSPI_IDER_EMPTYDMAEN_MASK (0x01U << QSPI_IDER_EMPTYDMAEN_SHIFT) +#define QSPI_IDER_EMPTYDMAEN(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IDER_EMPTYDMAEN_SHIFT)) & QSPI_IDER_EMPTYDMAEN_MASK) + +#define QSPI_IDER_TCFDMAEN_SHIFT (8) +#define QSPI_IDER_TCFDMAEN_MASK (0x01U << QSPI_IDER_TCFDMAEN_SHIFT) +#define QSPI_IDER_TCFDMAEN(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IDER_TCFDMAEN_SHIFT)) & QSPI_IDER_TCFDMAEN_MASK) + +#define QSPI_IDER_FULLINTEN_SHIFT (7) +#define QSPI_IDER_FULLINTEN_MASK (0x01U << QSPI_IDER_FULLINTEN_SHIFT) +#define QSPI_IDER_FULLINTEN(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IDER_FULLINTEN_SHIFT)) & QSPI_IDER_FULLINTEN_MASK) + +#define QSPI_IDER_EMPTYINTEN_SHIFT (6) +#define QSPI_IDER_EMPTYINTEN_MASK (0x01U << QSPI_IDER_EMPTYINTEN_SHIFT) +#define QSPI_IDER_EMPTYINTEN(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IDER_EMPTYINTEN_SHIFT)) & QSPI_IDER_EMPTYINTEN_MASK) + +#define QSPI_IDER_TCFINTEN_SHIFT (0) +#define QSPI_IDER_TCFINTEN_MASK (0x01U << QSPI_IDER_TCFINTEN_SHIFT) +#define QSPI_IDER_TCFINTEN(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IDER_TCFINTEN_SHIFT)) & QSPI_IDER_TCFINTEN_MASK) + +/*! + * @} + */ /* end of group QSPI_Register_Masks */ +/****************************************************************************** + *QSPI Instance +*******************************************************************************/ + +#define QSPI ((QSPI_Type*)QSPI_BASE) + +/*! + * @} + */ /* end of group QSPI_Peripheral_Access_Layer */ + + +/*! + * @addtogroup RCC_Peripheral_Access_Layer RCC Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * RCC Type + ******************************************************************************/ +typedef struct { + __IO uint32_t CR; ///< clock control register offset: 0x00 + __IO uint32_t CFGR; ///< Clock Configuration Register offset: 0x04 + __IO uint32_t CIR; ///< clock interrupt register offset: 0x08 + __IO uint32_t Reserved42[2]; ///< Reserved + __IO uint32_t AHB1RSTR; ///< AHB1 Peripheral Reset Register offset: 0x14 + __IO uint32_t APB2RSTR; ///< APB2 Peripheral Reset Register offset: 0x18 + __IO uint32_t APB1RSTR; ///< APB1 Peripheral Reset Register offset: 0x1C + __IO uint32_t Reserved43[2]; ///< Reserved + __IO uint32_t AHB1ENR; ///< AHB1 peripheral clock enable register offset: 0x28 + __IO uint32_t APB2ENR; ///< APB2 Peripheral Clock Enable Register offset: 0x2C + __IO uint32_t APB1ENR; ///< APB1 Peripheral Clock Enable Register offset: 0x30 + __IO uint32_t BDCR; ///< Backup Domain Control Register offset: 0x34 + __IO uint32_t CSR; ///< Control Status Register offset: 0x38 + __IO uint32_t SYSCFG; ///< System Configuration Register offset: 0x3C + __IO uint32_t CFGR2; ///< Clock Configuration Register 2 offset: 0x40 + __IO uint32_t Reserved44; ///< Reserved offset: 0x44 + __IO uint32_t PLL1CFGR; ///< PLL1 Configuration Register offset: 0x48 + __IO uint32_t PLL2CFGR; ///< PLL2 Configuration Register offset: 0x4C + __IO uint32_t Reserved45[4]; ///< Reserved + __IO uint32_t ADC1CFGR; ///< ADC1 Configuration Register offset: 0x60 + __IO uint32_t ADC2CFGR; ///< ADC2 Configuration Register offset: 0x64 + __IO uint32_t Reserved46[2]; ///< Reserved + __IO uint32_t DACCFGR; ///< DAC Configuration Register offset: 0x70 + __IO uint32_t Reserved47[1]; ///< Reserved + __IO uint32_t FSMCCFGR; ///< FSMC Configuration Register offset: 0x78 + __IO uint32_t TPIUCFGR; ///< TPIU configuration register offset: 0x7C +} RCC_Type; + +/******************************************************************************* + * RCC Type + ******************************************************************************/ + +/*! + * @addtogroup RCC_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief RCC_CR Register Bit Definition + */ + +#define RCC_CR_PLL2RDY_SHIFT (29) +#define RCC_CR_PLL2RDY_MASK (0x01U << RCC_CR_PLL2RDY_SHIFT) +#define RCC_CR_PLL2RDY(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_PLL2RDY_SHIFT)) & RCC_CR_PLL2RDY_MASK) + +#define RCC_CR_PLL2ON_SHIFT (28) +#define RCC_CR_PLL2ON_MASK (0x01U << RCC_CR_PLL2ON_SHIFT) +#define RCC_CR_PLL2ON(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_PLL2ON_SHIFT)) & RCC_CR_PLL2ON_MASK) + +#define RCC_CR_PLL1RDY_SHIFT (25) +#define RCC_CR_PLL1RDY_MASK (0x01U << RCC_CR_PLL1RDY_SHIFT) +#define RCC_CR_PLL1RDY(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_PLL1RDY_SHIFT)) & RCC_CR_PLL1RDY_MASK) + +#define RCC_CR_PLL1ON_SHIFT (24) +#define RCC_CR_PLL1ON_MASK (0x01U << RCC_CR_PLL1ON_SHIFT) +#define RCC_CR_PLL1ON(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_PLL1ON_SHIFT)) & RCC_CR_PLL1ON_MASK) + +#define RCC_CR_HSEIB_SHIFT (22) +#define RCC_CR_HSEIB_MASK (0x3U << RCC_CR_HSEIB_SHIFT) +#define RCC_CR_HSEIB(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_HSEIB_SHIFT)) & RCC_CR_HSEIB_MASK) + +#define RCC_CR_HSEAACSEL_SHIFT (21) +#define RCC_CR_HSEAACSEL_MASK (0x01U << RCC_CR_HSEAACSEL_SHIFT) +#define RCC_CR_HSEAACSEL(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_HSEAACSEL_SHIFT)) & RCC_CR_HSEAACSEL_MASK) + +#define RCC_CR_CSSON_SHIFT (19) +#define RCC_CR_CSSON_MASK (0x01U << RCC_CR_CSSON_SHIFT) +#define RCC_CR_CSSON(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_CSSON_SHIFT)) & RCC_CR_CSSON_MASK) + +#define RCC_CR_HSEBYP_SHIFT (18) +#define RCC_CR_HSEBYP_MASK (0x01U << RCC_CR_HSEBYP_SHIFT) +#define RCC_CR_HSEBYP(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_HSEBYP_SHIFT)) & RCC_CR_HSEBYP_MASK) + +#define RCC_CR_HSERDY_SHIFT (17) +#define RCC_CR_HSERDY_MASK (0x01U << RCC_CR_HSERDY_SHIFT) +#define RCC_CR_HSERDY(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_HSERDY_SHIFT)) & RCC_CR_HSERDY_MASK) + +#define RCC_CR_HSEON_SHIFT (16) +#define RCC_CR_HSEON_MASK (0x01U << RCC_CR_HSEON_SHIFT) +#define RCC_CR_HSEON(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_HSEON_SHIFT)) & RCC_CR_HSEON_MASK) + +#define RCC_CR_HSIDIV_SHIFT (11) +#define RCC_CR_HSIDIV_MASK (0x7U << RCC_CR_HSIDIV_SHIFT) +#define RCC_CR_HSIDIV(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_HSIDIV_SHIFT)) & RCC_CR_HSIDIV_MASK) + +#define RCC_CR_HSEDR_SHIFT (9) +#define RCC_CR_HSEDR_MASK (0x3U << RCC_CR_HSEDR_SHIFT) +#define RCC_CR_HSEDR(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_HSEDR_SHIFT)) & RCC_CR_HSEDR_MASK) + +#define RCC_CR_HSEOUTPUTSEL_SHIFT (8) +#define RCC_CR_HSEOUTPUTSEL_MASK (0x01U << RCC_CR_HSEOUTPUTSEL_SHIFT) +#define RCC_CR_HSEOUTPUTSEL(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_HSEOUTPUTSEL_SHIFT)) & RCC_CR_HSEOUTPUTSEL_MASK) + +#define RCC_CR_HSEDEGLITCHSEL_SHIFT (7) +#define RCC_CR_HSEDEGLITCHSEL_MASK (0x01U << RCC_CR_HSEDEGLITCHSEL_SHIFT) +#define RCC_CR_HSEDEGLITCHSEL(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_HSEDEGLITCHSEL_SHIFT)) & RCC_CR_HSEDEGLITCHSEL_MASK) + +#define RCC_CR_HSEDEGLITCHBYP_SHIFT (6) +#define RCC_CR_HSEDEGLITCHBYP_MASK (0x01U << RCC_CR_HSEDEGLITCHBYP_SHIFT) +#define RCC_CR_HSEDEGLITCHBYP(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_HSEDEGLITCHBYP_SHIFT)) & RCC_CR_HSEDEGLITCHBYP_MASK) + +#define RCC_CR_HSELPFSEL_SHIFT (5) +#define RCC_CR_HSELPFSEL_MASK (0x01U << RCC_CR_HSELPFSEL_SHIFT) +#define RCC_CR_HSELPFSEL(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_HSELPFSEL_SHIFT)) & RCC_CR_HSELPFSEL_MASK) + +#define RCC_CR_HSELPFBYP_SHIFT (4) +#define RCC_CR_HSELPFBYP_MASK (0x01U << RCC_CR_HSELPFBYP_SHIFT) +#define RCC_CR_HSELPFBYP(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_HSELPFBYP_SHIFT)) & RCC_CR_HSELPFBYP_MASK) + +#define RCC_CR_HSIRDY_SHIFT (1) +#define RCC_CR_HSIRDY_MASK (0x01U << RCC_CR_HSIRDY_SHIFT) +#define RCC_CR_HSIRDY(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_HSIRDY_SHIFT)) & RCC_CR_HSIRDY_MASK) + +#define RCC_CR_HSION_SHIFT (0) +#define RCC_CR_HSION_MASK (0x01U << RCC_CR_HSION_SHIFT) +#define RCC_CR_HSION(x) (((uint32_t)(((uint32_t)(x)) << RCC_CR_HSION_SHIFT)) & RCC_CR_HSION_MASK) + +/*! + * @brief RCC_CFGR Register Bit Definition + */ + +#define RCC_CFGR_MCO_SHIFT (24) +#define RCC_CFGR_MCO_MASK (0xFU << RCC_CFGR_MCO_SHIFT) +#define RCC_CFGR_MCO(x) (((uint32_t)(((uint32_t)(x)) << RCC_CFGR_MCO_SHIFT)) & RCC_CFGR_MCO_MASK) + +#define RCC_CFGR_USBPRE_SHIFT (22) +#define RCC_CFGR_USBPRE_MASK (0x3U << RCC_CFGR_USBPRE_SHIFT) +#define RCC_CFGR_USBPRE(x) (((uint32_t)(((uint32_t)(x)) << RCC_CFGR_USBPRE_SHIFT)) & RCC_CFGR_USBPRE_MASK) + +#define RCC_CFGR_USBCLKSEL_SHIFT (19) +#define RCC_CFGR_USBCLKSEL_MASK (0x01U << RCC_CFGR_USBCLKSEL_SHIFT) +#define RCC_CFGR_USBCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << RCC_CFGR_USBCLKSEL_SHIFT)) & RCC_CFGR_USBCLKSEL_MASK) + +#define RCC_CFGR_ADC2CLKSEL_SHIFT (17) +#define RCC_CFGR_ADC2CLKSEL_MASK (0x01U << RCC_CFGR_ADC2CLKSEL_SHIFT) +#define RCC_CFGR_ADC2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << RCC_CFGR_ADC2CLKSEL_SHIFT)) & RCC_CFGR_ADC2CLKSEL_MASK) + +#define RCC_CFGR_ADC1CLKSEL_SHIFT (16) +#define RCC_CFGR_ADC1CLKSEL_MASK (0x01U << RCC_CFGR_ADC1CLKSEL_SHIFT) +#define RCC_CFGR_ADC1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << RCC_CFGR_ADC1CLKSEL_SHIFT)) & RCC_CFGR_ADC1CLKSEL_MASK) + +#define RCC_CFGR_PPRE2_SHIFT (11) +#define RCC_CFGR_PPRE2_MASK (0x7U << RCC_CFGR_PPRE2_SHIFT) +#define RCC_CFGR_PPRE2(x) (((uint32_t)(((uint32_t)(x)) << RCC_CFGR_PPRE2_SHIFT)) & RCC_CFGR_PPRE2_MASK) + +#define RCC_CFGR_PPRE1_SHIFT (8) +#define RCC_CFGR_PPRE1_MASK (0x7U << RCC_CFGR_PPRE1_SHIFT) +#define RCC_CFGR_PPRE1(x) (((uint32_t)(((uint32_t)(x)) << RCC_CFGR_PPRE1_SHIFT)) & RCC_CFGR_PPRE1_MASK) + +#define RCC_CFGR_HPRE_SHIFT (4) +#define RCC_CFGR_HPRE_MASK (0xFU << RCC_CFGR_HPRE_SHIFT) +#define RCC_CFGR_HPRE(x) (((uint32_t)(((uint32_t)(x)) << RCC_CFGR_HPRE_SHIFT)) & RCC_CFGR_HPRE_MASK) + +#define RCC_CFGR_SWS_SHIFT (2) +#define RCC_CFGR_SWS_MASK (0x3U << RCC_CFGR_SWS_SHIFT) +#define RCC_CFGR_SWS(x) (((uint32_t)(((uint32_t)(x)) << RCC_CFGR_SWS_SHIFT)) & RCC_CFGR_SWS_MASK) + +#define RCC_CFGR_SW_SHIFT (0) +#define RCC_CFGR_SW_MASK (0x3U << RCC_CFGR_SW_SHIFT) +#define RCC_CFGR_SW(x) (((uint32_t)(((uint32_t)(x)) << RCC_CFGR_SW_SHIFT)) & RCC_CFGR_SW_MASK) + +/*! + * @brief RCC_CIR Register Bit Definition + */ + +#define RCC_CIR_CSSC_SHIFT (23) +#define RCC_CIR_CSSC_MASK (0x01U << RCC_CIR_CSSC_SHIFT) +#define RCC_CIR_CSSC(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_CSSC_SHIFT)) & RCC_CIR_CSSC_MASK) + +#define RCC_CIR_PLL2RDYC_SHIFT (21) +#define RCC_CIR_PLL2RDYC_MASK (0x01U << RCC_CIR_PLL2RDYC_SHIFT) +#define RCC_CIR_PLL2RDYC(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_PLL2RDYC_SHIFT)) & RCC_CIR_PLL2RDYC_MASK) + +#define RCC_CIR_PLL1RDYC_SHIFT (20) +#define RCC_CIR_PLL1RDYC_MASK (0x01U << RCC_CIR_PLL1RDYC_SHIFT) +#define RCC_CIR_PLL1RDYC(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_PLL1RDYC_SHIFT)) & RCC_CIR_PLL1RDYC_MASK) + +#define RCC_CIR_HSERDYC_SHIFT (19) +#define RCC_CIR_HSERDYC_MASK (0x01U << RCC_CIR_HSERDYC_SHIFT) +#define RCC_CIR_HSERDYC(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_HSERDYC_SHIFT)) & RCC_CIR_HSERDYC_MASK) + +#define RCC_CIR_HSIRDYC_SHIFT (18) +#define RCC_CIR_HSIRDYC_MASK (0x01U << RCC_CIR_HSIRDYC_SHIFT) +#define RCC_CIR_HSIRDYC(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_HSIRDYC_SHIFT)) & RCC_CIR_HSIRDYC_MASK) + +#define RCC_CIR_LSERDYC_SHIFT (17) +#define RCC_CIR_LSERDYC_MASK (0x01U << RCC_CIR_LSERDYC_SHIFT) +#define RCC_CIR_LSERDYC(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_LSERDYC_SHIFT)) & RCC_CIR_LSERDYC_MASK) + +#define RCC_CIR_LSIRDYC_SHIFT (16) +#define RCC_CIR_LSIRDYC_MASK (0x01U << RCC_CIR_LSIRDYC_SHIFT) +#define RCC_CIR_LSIRDYC(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_LSIRDYC_SHIFT)) & RCC_CIR_LSIRDYC_MASK) + +#define RCC_CIR_PLL2RDYIE_SHIFT (13) +#define RCC_CIR_PLL2RDYIE_MASK (0x01U << RCC_CIR_PLL2RDYIE_SHIFT) +#define RCC_CIR_PLL2RDYIE(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_PLL2RDYIE_SHIFT)) & RCC_CIR_PLL2RDYIE_MASK) + +#define RCC_CIR_PLL1RDYIE_SHIFT (12) +#define RCC_CIR_PLL1RDYIE_MASK (0x01U << RCC_CIR_PLL1RDYIE_SHIFT) +#define RCC_CIR_PLL1RDYIE(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_PLL1RDYIE_SHIFT)) & RCC_CIR_PLL1RDYIE_MASK) + +#define RCC_CIR_HSERDYIE_SHIFT (11) +#define RCC_CIR_HSERDYIE_MASK (0x01U << RCC_CIR_HSERDYIE_SHIFT) +#define RCC_CIR_HSERDYIE(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_HSERDYIE_SHIFT)) & RCC_CIR_HSERDYIE_MASK) + +#define RCC_CIR_HSIRDYIE_SHIFT (10) +#define RCC_CIR_HSIRDYIE_MASK (0x01U << RCC_CIR_HSIRDYIE_SHIFT) +#define RCC_CIR_HSIRDYIE(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_HSIRDYIE_SHIFT)) & RCC_CIR_HSIRDYIE_MASK) + +#define RCC_CIR_LSERDYIE_SHIFT (9) +#define RCC_CIR_LSERDYIE_MASK (0x01U << RCC_CIR_LSERDYIE_SHIFT) +#define RCC_CIR_LSERDYIE(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_LSERDYIE_SHIFT)) & RCC_CIR_LSERDYIE_MASK) + +#define RCC_CIR_LSIRDYIE_SHIFT (8) +#define RCC_CIR_LSIRDYIE_MASK (0x01U << RCC_CIR_LSIRDYIE_SHIFT) +#define RCC_CIR_LSIRDYIE(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_LSIRDYIE_SHIFT)) & RCC_CIR_LSIRDYIE_MASK) + +#define RCC_CIR_CSSF_SHIFT (7) +#define RCC_CIR_CSSF_MASK (0x01U << RCC_CIR_CSSF_SHIFT) +#define RCC_CIR_CSSF(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_CSSF_SHIFT)) & RCC_CIR_CSSF_MASK) + +#define RCC_CIR_PLL2RDYF_SHIFT (5) +#define RCC_CIR_PLL2RDYF_MASK (0x01U << RCC_CIR_PLL2RDYF_SHIFT) +#define RCC_CIR_PLL2RDYF(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_PLL2RDYF_SHIFT)) & RCC_CIR_PLL2RDYF_MASK) + +#define RCC_CIR_PLL1RDYF_SHIFT (4) +#define RCC_CIR_PLL1RDYF_MASK (0x01U << RCC_CIR_PLL1RDYF_SHIFT) +#define RCC_CIR_PLL1RDYF(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_PLL1RDYF_SHIFT)) & RCC_CIR_PLL1RDYF_MASK) + +#define RCC_CIR_HSERDYF_SHIFT (3) +#define RCC_CIR_HSERDYF_MASK (0x01U << RCC_CIR_HSERDYF_SHIFT) +#define RCC_CIR_HSERDYF(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_HSERDYF_SHIFT)) & RCC_CIR_HSERDYF_MASK) + +#define RCC_CIR_HSIRDYF_SHIFT (2) +#define RCC_CIR_HSIRDYF_MASK (0x01U << RCC_CIR_HSIRDYF_SHIFT) +#define RCC_CIR_HSIRDYF(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_HSIRDYF_SHIFT)) & RCC_CIR_HSIRDYF_MASK) + +#define RCC_CIR_LSERDYF_SHIFT (1) +#define RCC_CIR_LSERDYF_MASK (0x01U << RCC_CIR_LSERDYF_SHIFT) +#define RCC_CIR_LSERDYF(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_LSERDYF_SHIFT)) & RCC_CIR_LSERDYF_MASK) + +#define RCC_CIR_LSIRDYF_SHIFT (0) +#define RCC_CIR_LSIRDYF_MASK (0x01U << RCC_CIR_LSIRDYF_SHIFT) +#define RCC_CIR_LSIRDYF(x) (((uint32_t)(((uint32_t)(x)) << RCC_CIR_LSIRDYF_SHIFT)) & RCC_CIR_LSIRDYF_MASK) + +/*! + * @brief RCC_AHB1RSTR Register Bit Definition + */ + +#define RCC_AHB1RSTR_QSPI_SHIFT (30) +#define RCC_AHB1RSTR_QSPI_MASK (0x01U << RCC_AHB1RSTR_QSPI_SHIFT) +#define RCC_AHB1RSTR_QSPI(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1RSTR_QSPI_SHIFT)) & RCC_AHB1RSTR_QSPI_MASK) + +#define RCC_AHB1RSTR_FSMC_SHIFT (28) +#define RCC_AHB1RSTR_FSMC_MASK (0x01U << RCC_AHB1RSTR_FSMC_SHIFT) +#define RCC_AHB1RSTR_FSMC(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1RSTR_FSMC_SHIFT)) & RCC_AHB1RSTR_FSMC_MASK) + +#define RCC_AHB1RSTR_USBOTGFS_SHIFT (24) +#define RCC_AHB1RSTR_USBOTGFS_MASK (0x01U << RCC_AHB1RSTR_USBOTGFS_SHIFT) +#define RCC_AHB1RSTR_USBOTGFS(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1RSTR_USBOTGFS_SHIFT)) & RCC_AHB1RSTR_USBOTGFS_MASK) + +#define RCC_AHB1RSTR_DMA2_SHIFT (22) +#define RCC_AHB1RSTR_DMA2_MASK (0x01U << RCC_AHB1RSTR_DMA2_SHIFT) +#define RCC_AHB1RSTR_DMA2(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1RSTR_DMA2_SHIFT)) & RCC_AHB1RSTR_DMA2_MASK) + +#define RCC_AHB1RSTR_DMA1_SHIFT (21) +#define RCC_AHB1RSTR_DMA1_MASK (0x01U << RCC_AHB1RSTR_DMA1_SHIFT) +#define RCC_AHB1RSTR_DMA1(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1RSTR_DMA1_SHIFT)) & RCC_AHB1RSTR_DMA1_MASK) + +#define RCC_AHB1RSTR_ENET_SHIFT (19) +#define RCC_AHB1RSTR_ENET_MASK (0x01U << RCC_AHB1RSTR_ENET_SHIFT) +#define RCC_AHB1RSTR_ENET(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1RSTR_ENET_SHIFT)) & RCC_AHB1RSTR_ENET_MASK) + +#define RCC_AHB1RSTR_CORDIC_SHIFT (15) +#define RCC_AHB1RSTR_CORDIC_MASK (0x01U << RCC_AHB1RSTR_CORDIC_SHIFT) +#define RCC_AHB1RSTR_CORDIC(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1RSTR_CORDIC_SHIFT)) & RCC_AHB1RSTR_CORDIC_MASK) + +#define RCC_AHB1RSTR_CRC_SHIFT (12) +#define RCC_AHB1RSTR_CRC_MASK (0x01U << RCC_AHB1RSTR_CRC_SHIFT) +#define RCC_AHB1RSTR_CRC(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1RSTR_CRC_SHIFT)) & RCC_AHB1RSTR_CRC_MASK) + +#define RCC_AHB1RSTR_GPIOI_SHIFT (8) +#define RCC_AHB1RSTR_GPIOI_MASK (0x01U << RCC_AHB1RSTR_GPIOI_SHIFT) +#define RCC_AHB1RSTR_GPIOI(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1RSTR_GPIOI_SHIFT)) & RCC_AHB1RSTR_GPIOI_MASK) + +#define RCC_AHB1RSTR_GPIOH_SHIFT (7) +#define RCC_AHB1RSTR_GPIOH_MASK (0x01U << RCC_AHB1RSTR_GPIOH_SHIFT) +#define RCC_AHB1RSTR_GPIOH(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1RSTR_GPIOH_SHIFT)) & RCC_AHB1RSTR_GPIOH_MASK) + +#define RCC_AHB1RSTR_GPIOG_SHIFT (6) +#define RCC_AHB1RSTR_GPIOG_MASK (0x01U << RCC_AHB1RSTR_GPIOG_SHIFT) +#define RCC_AHB1RSTR_GPIOG(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1RSTR_GPIOG_SHIFT)) & RCC_AHB1RSTR_GPIOG_MASK) + +#define RCC_AHB1RSTR_GPIOF_SHIFT (5) +#define RCC_AHB1RSTR_GPIOF_MASK (0x01U << RCC_AHB1RSTR_GPIOF_SHIFT) +#define RCC_AHB1RSTR_GPIOF(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1RSTR_GPIOF_SHIFT)) & RCC_AHB1RSTR_GPIOF_MASK) + +#define RCC_AHB1RSTR_GPIOE_SHIFT (4) +#define RCC_AHB1RSTR_GPIOE_MASK (0x01U << RCC_AHB1RSTR_GPIOE_SHIFT) +#define RCC_AHB1RSTR_GPIOE(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1RSTR_GPIOE_SHIFT)) & RCC_AHB1RSTR_GPIOE_MASK) + +#define RCC_AHB1RSTR_GPIOD_SHIFT (3) +#define RCC_AHB1RSTR_GPIOD_MASK (0x01U << RCC_AHB1RSTR_GPIOD_SHIFT) +#define RCC_AHB1RSTR_GPIOD(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1RSTR_GPIOD_SHIFT)) & RCC_AHB1RSTR_GPIOD_MASK) + +#define RCC_AHB1RSTR_GPIOC_SHIFT (2) +#define RCC_AHB1RSTR_GPIOC_MASK (0x01U << RCC_AHB1RSTR_GPIOC_SHIFT) +#define RCC_AHB1RSTR_GPIOC(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1RSTR_GPIOC_SHIFT)) & RCC_AHB1RSTR_GPIOC_MASK) + +#define RCC_AHB1RSTR_GPIOB_SHIFT (1) +#define RCC_AHB1RSTR_GPIOB_MASK (0x01U << RCC_AHB1RSTR_GPIOB_SHIFT) +#define RCC_AHB1RSTR_GPIOB(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1RSTR_GPIOB_SHIFT)) & RCC_AHB1RSTR_GPIOB_MASK) + +#define RCC_AHB1RSTR_GPIOA_SHIFT (0) +#define RCC_AHB1RSTR_GPIOA_MASK (0x01U << RCC_AHB1RSTR_GPIOA_SHIFT) +#define RCC_AHB1RSTR_GPIOA(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1RSTR_GPIOA_SHIFT)) & RCC_AHB1RSTR_GPIOA_MASK) + +/*! + * @brief RCC_APB2RSTR Register Bit Definition + */ + +#define RCC_APB2RSTR_LPUART_SHIFT (31) +#define RCC_APB2RSTR_LPUART_MASK (0x01U << RCC_APB2RSTR_LPUART_SHIFT) +#define RCC_APB2RSTR_LPUART(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2RSTR_LPUART_SHIFT)) & RCC_APB2RSTR_LPUART_MASK) + +#define RCC_APB2RSTR_LPTIM_SHIFT (30) +#define RCC_APB2RSTR_LPTIM_MASK (0x01U << RCC_APB2RSTR_LPTIM_SHIFT) +#define RCC_APB2RSTR_LPTIM(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2RSTR_LPTIM_SHIFT)) & RCC_APB2RSTR_LPTIM_MASK) + +#define RCC_APB2RSTR_MINDSWITCH_SHIFT (28) +#define RCC_APB2RSTR_MINDSWITCH_MASK (0x01U << RCC_APB2RSTR_MINDSWITCH_SHIFT) +#define RCC_APB2RSTR_MINDSWITCH(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2RSTR_MINDSWITCH_SHIFT)) & RCC_APB2RSTR_MINDSWITCH_MASK) + +#define RCC_APB2RSTR_FLEXCAN2_SHIFT (24) +#define RCC_APB2RSTR_FLEXCAN2_MASK (0x01U << RCC_APB2RSTR_FLEXCAN2_SHIFT) +#define RCC_APB2RSTR_FLEXCAN2(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2RSTR_FLEXCAN2_SHIFT)) & RCC_APB2RSTR_FLEXCAN2_MASK) + +#define RCC_APB2RSTR_COMP_SHIFT (15) +#define RCC_APB2RSTR_COMP_MASK (0x01U << RCC_APB2RSTR_COMP_SHIFT) +#define RCC_APB2RSTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2RSTR_COMP_SHIFT)) & RCC_APB2RSTR_COMP_MASK) + +#define RCC_APB2RSTR_SYSCFG_SHIFT (14) +#define RCC_APB2RSTR_SYSCFG_MASK (0x01U << RCC_APB2RSTR_SYSCFG_SHIFT) +#define RCC_APB2RSTR_SYSCFG(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2RSTR_SYSCFG_SHIFT)) & RCC_APB2RSTR_SYSCFG_MASK) + +#define RCC_APB2RSTR_SPI1_SHIFT (12) +#define RCC_APB2RSTR_SPI1_MASK (0x01U << RCC_APB2RSTR_SPI1_SHIFT) +#define RCC_APB2RSTR_SPI1(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2RSTR_SPI1_SHIFT)) & RCC_APB2RSTR_SPI1_MASK) + +#define RCC_APB2RSTR_ADC2_SHIFT (9) +#define RCC_APB2RSTR_ADC2_MASK (0x01U << RCC_APB2RSTR_ADC2_SHIFT) +#define RCC_APB2RSTR_ADC2(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2RSTR_ADC2_SHIFT)) & RCC_APB2RSTR_ADC2_MASK) + +#define RCC_APB2RSTR_ADC1_SHIFT (8) +#define RCC_APB2RSTR_ADC1_MASK (0x01U << RCC_APB2RSTR_ADC1_SHIFT) +#define RCC_APB2RSTR_ADC1(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2RSTR_ADC1_SHIFT)) & RCC_APB2RSTR_ADC1_MASK) + +#define RCC_APB2RSTR_UART6_SHIFT (5) +#define RCC_APB2RSTR_UART6_MASK (0x01U << RCC_APB2RSTR_UART6_SHIFT) +#define RCC_APB2RSTR_UART6(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2RSTR_UART6_SHIFT)) & RCC_APB2RSTR_UART6_MASK) + +#define RCC_APB2RSTR_UART1_SHIFT (4) +#define RCC_APB2RSTR_UART1_MASK (0x01U << RCC_APB2RSTR_UART1_SHIFT) +#define RCC_APB2RSTR_UART1(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2RSTR_UART1_SHIFT)) & RCC_APB2RSTR_UART1_MASK) + +#define RCC_APB2RSTR_TIM8_SHIFT (1) +#define RCC_APB2RSTR_TIM8_MASK (0x01U << RCC_APB2RSTR_TIM8_SHIFT) +#define RCC_APB2RSTR_TIM8(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2RSTR_TIM8_SHIFT)) & RCC_APB2RSTR_TIM8_MASK) + +#define RCC_APB2RSTR_TIM1_SHIFT (0) +#define RCC_APB2RSTR_TIM1_MASK (0x01U << RCC_APB2RSTR_TIM1_SHIFT) +#define RCC_APB2RSTR_TIM1(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2RSTR_TIM1_SHIFT)) & RCC_APB2RSTR_TIM1_MASK) + +/*! + * @brief RCC_APB1RSTR Register Bit Definition + */ + +#define RCC_APB1RSTR_UART7_SHIFT (30) +#define RCC_APB1RSTR_UART7_MASK (0x01U << RCC_APB1RSTR_UART7_SHIFT) +#define RCC_APB1RSTR_UART7(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_UART7_SHIFT)) & RCC_APB1RSTR_UART7_MASK) + +#define RCC_APB1RSTR_DAC_SHIFT (29) +#define RCC_APB1RSTR_DAC_MASK (0x01U << RCC_APB1RSTR_DAC_SHIFT) +#define RCC_APB1RSTR_DAC(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_DAC_SHIFT)) & RCC_APB1RSTR_DAC_MASK) + +#define RCC_APB1RSTR_PWR_SHIFT (28) +#define RCC_APB1RSTR_PWR_MASK (0x01U << RCC_APB1RSTR_PWR_SHIFT) +#define RCC_APB1RSTR_PWR(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_PWR_SHIFT)) & RCC_APB1RSTR_PWR_MASK) + +#define RCC_APB1RSTR_BKP_SHIFT (27) +#define RCC_APB1RSTR_BKP_MASK (0x01U << RCC_APB1RSTR_BKP_SHIFT) +#define RCC_APB1RSTR_BKP(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_BKP_SHIFT)) & RCC_APB1RSTR_BKP_MASK) + +#define RCC_APB1RSTR_DBG_SHIFT (26) +#define RCC_APB1RSTR_DBG_MASK (0x01U << RCC_APB1RSTR_DBG_SHIFT) +#define RCC_APB1RSTR_DBG(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_DBG_SHIFT)) & RCC_APB1RSTR_DBG_MASK) + +#define RCC_APB1RSTR_FLEXCAN1_SHIFT (25) +#define RCC_APB1RSTR_FLEXCAN1_MASK (0x01U << RCC_APB1RSTR_FLEXCAN1_SHIFT) +#define RCC_APB1RSTR_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_FLEXCAN1_SHIFT)) & RCC_APB1RSTR_FLEXCAN1_MASK) + +#define RCC_APB1RSTR_CRS_SHIFT (24) +#define RCC_APB1RSTR_CRS_MASK (0x01U << RCC_APB1RSTR_CRS_SHIFT) +#define RCC_APB1RSTR_CRS(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_CRS_SHIFT)) & RCC_APB1RSTR_CRS_MASK) + +#define RCC_APB1RSTR_I2C2_SHIFT (22) +#define RCC_APB1RSTR_I2C2_MASK (0x01U << RCC_APB1RSTR_I2C2_SHIFT) +#define RCC_APB1RSTR_I2C2(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_I2C2_SHIFT)) & RCC_APB1RSTR_I2C2_MASK) + +#define RCC_APB1RSTR_I2C1_SHIFT (21) +#define RCC_APB1RSTR_I2C1_MASK (0x01U << RCC_APB1RSTR_I2C1_SHIFT) +#define RCC_APB1RSTR_I2C1(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_I2C1_SHIFT)) & RCC_APB1RSTR_I2C1_MASK) + +#define RCC_APB1RSTR_UART5_SHIFT (20) +#define RCC_APB1RSTR_UART5_MASK (0x01U << RCC_APB1RSTR_UART5_SHIFT) +#define RCC_APB1RSTR_UART5(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_UART5_SHIFT)) & RCC_APB1RSTR_UART5_MASK) + +#define RCC_APB1RSTR_UART4_SHIFT (19) +#define RCC_APB1RSTR_UART4_MASK (0x01U << RCC_APB1RSTR_UART4_SHIFT) +#define RCC_APB1RSTR_UART4(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_UART4_SHIFT)) & RCC_APB1RSTR_UART4_MASK) + +#define RCC_APB1RSTR_UART3_SHIFT (18) +#define RCC_APB1RSTR_UART3_MASK (0x01U << RCC_APB1RSTR_UART3_SHIFT) +#define RCC_APB1RSTR_UART3(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_UART3_SHIFT)) & RCC_APB1RSTR_UART3_MASK) + +#define RCC_APB1RSTR_UART2_SHIFT (17) +#define RCC_APB1RSTR_UART2_MASK (0x01U << RCC_APB1RSTR_UART2_SHIFT) +#define RCC_APB1RSTR_UART2(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_UART2_SHIFT)) & RCC_APB1RSTR_UART2_MASK) + +#define RCC_APB1RSTR_SPI3_SHIFT (15) +#define RCC_APB1RSTR_SPI3_MASK (0x01U << RCC_APB1RSTR_SPI3_SHIFT) +#define RCC_APB1RSTR_SPI3(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_SPI3_SHIFT)) & RCC_APB1RSTR_SPI3_MASK) + +#define RCC_APB1RSTR_SPI2_SHIFT (14) +#define RCC_APB1RSTR_SPI2_MASK (0x01U << RCC_APB1RSTR_SPI2_SHIFT) +#define RCC_APB1RSTR_SPI2(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_SPI2_SHIFT)) & RCC_APB1RSTR_SPI2_MASK) + +#define RCC_APB1RSTR_WWDG_SHIFT (11) +#define RCC_APB1RSTR_WWDG_MASK (0x01U << RCC_APB1RSTR_WWDG_SHIFT) +#define RCC_APB1RSTR_WWDG(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_WWDG_SHIFT)) & RCC_APB1RSTR_WWDG_MASK) + +#define RCC_APB1RSTR_TIM7_SHIFT (5) +#define RCC_APB1RSTR_TIM7_MASK (0x01U << RCC_APB1RSTR_TIM7_SHIFT) +#define RCC_APB1RSTR_TIM7(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_TIM7_SHIFT)) & RCC_APB1RSTR_TIM7_MASK) + +#define RCC_APB1RSTR_TIM6_SHIFT (4) +#define RCC_APB1RSTR_TIM6_MASK (0x01U << RCC_APB1RSTR_TIM6_SHIFT) +#define RCC_APB1RSTR_TIM6(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_TIM6_SHIFT)) & RCC_APB1RSTR_TIM6_MASK) + +#define RCC_APB1RSTR_TIM5_SHIFT (3) +#define RCC_APB1RSTR_TIM5_MASK (0x01U << RCC_APB1RSTR_TIM5_SHIFT) +#define RCC_APB1RSTR_TIM5(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_TIM5_SHIFT)) & RCC_APB1RSTR_TIM5_MASK) + +#define RCC_APB1RSTR_TIM4_SHIFT (2) +#define RCC_APB1RSTR_TIM4_MASK (0x01U << RCC_APB1RSTR_TIM4_SHIFT) +#define RCC_APB1RSTR_TIM4(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_TIM4_SHIFT)) & RCC_APB1RSTR_TIM4_MASK) + +#define RCC_APB1RSTR_TIM3_SHIFT (1) +#define RCC_APB1RSTR_TIM3_MASK (0x01U << RCC_APB1RSTR_TIM3_SHIFT) +#define RCC_APB1RSTR_TIM3(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_TIM3_SHIFT)) & RCC_APB1RSTR_TIM3_MASK) + +#define RCC_APB1RSTR_TIM2_SHIFT (0) +#define RCC_APB1RSTR_TIM2_MASK (0x01U << RCC_APB1RSTR_TIM2_SHIFT) +#define RCC_APB1RSTR_TIM2(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1RSTR_TIM2_SHIFT)) & RCC_APB1RSTR_TIM2_MASK) + +/*! + * @brief RCC_AHB1ENR Register Bit Definition + */ + +#define RCC_AHB1ENR_QSPI_SHIFT (30) +#define RCC_AHB1ENR_QSPI_MASK (0x01U << RCC_AHB1ENR_QSPI_SHIFT) +#define RCC_AHB1ENR_QSPI(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_QSPI_SHIFT)) & RCC_AHB1ENR_QSPI_MASK) + +#define RCC_AHB1ENR_FSMC_SHIFT (28) +#define RCC_AHB1ENR_FSMC_MASK (0x01U << RCC_AHB1ENR_FSMC_SHIFT) +#define RCC_AHB1ENR_FSMC(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_FSMC_SHIFT)) & RCC_AHB1ENR_FSMC_MASK) + +#define RCC_AHB1ENR_USBOTGFS_SHIFT (24) +#define RCC_AHB1ENR_USBOTGFS_MASK (0x01U << RCC_AHB1ENR_USBOTGFS_SHIFT) +#define RCC_AHB1ENR_USBOTGFS(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_USBOTGFS_SHIFT)) & RCC_AHB1ENR_USBOTGFS_MASK) + +#define RCC_AHB1ENR_DMA2_SHIFT (22) +#define RCC_AHB1ENR_DMA2_MASK (0x01U << RCC_AHB1ENR_DMA2_SHIFT) +#define RCC_AHB1ENR_DMA2(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_DMA2_SHIFT)) & RCC_AHB1ENR_DMA2_MASK) + +#define RCC_AHB1ENR_DMA1_SHIFT (21) +#define RCC_AHB1ENR_DMA1_MASK (0x01U << RCC_AHB1ENR_DMA1_SHIFT) +#define RCC_AHB1ENR_DMA1(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_DMA1_SHIFT)) & RCC_AHB1ENR_DMA1_MASK) + +#define RCC_AHB1ENR_ENET_SHIFT (19) +#define RCC_AHB1ENR_ENET_MASK (0x01U << RCC_AHB1ENR_ENET_SHIFT) +#define RCC_AHB1ENR_ENET(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_ENET_SHIFT)) & RCC_AHB1ENR_ENET_MASK) + +#define RCC_AHB1ENR_DTCM_SHIFT (17) +#define RCC_AHB1ENR_DTCM_MASK (0x01U << RCC_AHB1ENR_DTCM_SHIFT) +#define RCC_AHB1ENR_DTCM(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_DTCM_SHIFT)) & RCC_AHB1ENR_DTCM_MASK) + +#define RCC_AHB1ENR_ITCM_SHIFT (16) +#define RCC_AHB1ENR_ITCM_MASK (0x01U << RCC_AHB1ENR_ITCM_SHIFT) +#define RCC_AHB1ENR_ITCM(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_ITCM_SHIFT)) & RCC_AHB1ENR_ITCM_MASK) + +#define RCC_AHB1ENR_CORDIC_SHIFT (15) +#define RCC_AHB1ENR_CORDIC_MASK (0x01U << RCC_AHB1ENR_CORDIC_SHIFT) +#define RCC_AHB1ENR_CORDIC(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_CORDIC_SHIFT)) & RCC_AHB1ENR_CORDIC_MASK) + +#define RCC_AHB1ENR_SRAM_SHIFT (14) +#define RCC_AHB1ENR_SRAM_MASK (0x01U << RCC_AHB1ENR_SRAM_SHIFT) +#define RCC_AHB1ENR_SRAM(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_SRAM_SHIFT)) & RCC_AHB1ENR_SRAM_MASK) + +#define RCC_AHB1ENR_FLASH_SHIFT (13) +#define RCC_AHB1ENR_FLASH_MASK (0x01U << RCC_AHB1ENR_FLASH_SHIFT) +#define RCC_AHB1ENR_FLASH(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_FLASH_SHIFT)) & RCC_AHB1ENR_FLASH_MASK) + +#define RCC_AHB1ENR_CRC_SHIFT (12) +#define RCC_AHB1ENR_CRC_MASK (0x01U << RCC_AHB1ENR_CRC_SHIFT) +#define RCC_AHB1ENR_CRC(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_CRC_SHIFT)) & RCC_AHB1ENR_CRC_MASK) + +#define RCC_AHB1ENR_GPIOI_SHIFT (8) +#define RCC_AHB1ENR_GPIOI_MASK (0x01U << RCC_AHB1ENR_GPIOI_SHIFT) +#define RCC_AHB1ENR_GPIOI(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_GPIOI_SHIFT)) & RCC_AHB1ENR_GPIOI_MASK) + +#define RCC_AHB1ENR_GPIOH_SHIFT (7) +#define RCC_AHB1ENR_GPIOH_MASK (0x01U << RCC_AHB1ENR_GPIOH_SHIFT) +#define RCC_AHB1ENR_GPIOH(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_GPIOH_SHIFT)) & RCC_AHB1ENR_GPIOH_MASK) + +#define RCC_AHB1ENR_GPIOG_SHIFT (6) +#define RCC_AHB1ENR_GPIOG_MASK (0x01U << RCC_AHB1ENR_GPIOG_SHIFT) +#define RCC_AHB1ENR_GPIOG(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_GPIOG_SHIFT)) & RCC_AHB1ENR_GPIOG_MASK) + +#define RCC_AHB1ENR_GPIOF_SHIFT (5) +#define RCC_AHB1ENR_GPIOF_MASK (0x01U << RCC_AHB1ENR_GPIOF_SHIFT) +#define RCC_AHB1ENR_GPIOF(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_GPIOF_SHIFT)) & RCC_AHB1ENR_GPIOF_MASK) + +#define RCC_AHB1ENR_GPIOE_SHIFT (4) +#define RCC_AHB1ENR_GPIOE_MASK (0x01U << RCC_AHB1ENR_GPIOE_SHIFT) +#define RCC_AHB1ENR_GPIOE(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_GPIOE_SHIFT)) & RCC_AHB1ENR_GPIOE_MASK) + +#define RCC_AHB1ENR_GPIOD_SHIFT (3) +#define RCC_AHB1ENR_GPIOD_MASK (0x01U << RCC_AHB1ENR_GPIOD_SHIFT) +#define RCC_AHB1ENR_GPIOD(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_GPIOD_SHIFT)) & RCC_AHB1ENR_GPIOD_MASK) + +#define RCC_AHB1ENR_GPIOC_SHIFT (2) +#define RCC_AHB1ENR_GPIOC_MASK (0x01U << RCC_AHB1ENR_GPIOC_SHIFT) +#define RCC_AHB1ENR_GPIOC(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_GPIOC_SHIFT)) & RCC_AHB1ENR_GPIOC_MASK) + +#define RCC_AHB1ENR_GPIOB_SHIFT (1) +#define RCC_AHB1ENR_GPIOB_MASK (0x01U << RCC_AHB1ENR_GPIOB_SHIFT) +#define RCC_AHB1ENR_GPIOB(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_GPIOB_SHIFT)) & RCC_AHB1ENR_GPIOB_MASK) + +#define RCC_AHB1ENR_GPIOA_SHIFT (0) +#define RCC_AHB1ENR_GPIOA_MASK (0x01U << RCC_AHB1ENR_GPIOA_SHIFT) +#define RCC_AHB1ENR_GPIOA(x) (((uint32_t)(((uint32_t)(x)) << RCC_AHB1ENR_GPIOA_SHIFT)) & RCC_AHB1ENR_GPIOA_MASK) + +/*! + * @brief RCC_APB2ENR Register Bit Definition + */ + +#define RCC_APB2ENR_LPUART_SHIFT (31) +#define RCC_APB2ENR_LPUART_MASK (0x01U << RCC_APB2ENR_LPUART_SHIFT) +#define RCC_APB2ENR_LPUART(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2ENR_LPUART_SHIFT)) & RCC_APB2ENR_LPUART_MASK) + +#define RCC_APB2ENR_LPTIM_SHIFT (30) +#define RCC_APB2ENR_LPTIM_MASK (0x01U << RCC_APB2ENR_LPTIM_SHIFT) +#define RCC_APB2ENR_LPTIM(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2ENR_LPTIM_SHIFT)) & RCC_APB2ENR_LPTIM_MASK) + +#define RCC_APB2ENR_MINDSWITCH_SHIFT (28) +#define RCC_APB2ENR_MINDSWITCH_MASK (0x01U << RCC_APB2ENR_MINDSWITCH_SHIFT) +#define RCC_APB2ENR_MINDSWITCH(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2ENR_MINDSWITCH_SHIFT)) & RCC_APB2ENR_MINDSWITCH_MASK) + +#define RCC_APB2ENR_FLEXCAN2_SHIFT (24) +#define RCC_APB2ENR_FLEXCAN2_MASK (0x01U << RCC_APB2ENR_FLEXCAN2_SHIFT) +#define RCC_APB2ENR_FLEXCAN2(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2ENR_FLEXCAN2_SHIFT)) & RCC_APB2ENR_FLEXCAN2_MASK) + +#define RCC_APB2ENR_COMP_SHIFT (15) +#define RCC_APB2ENR_COMP_MASK (0x01U << RCC_APB2ENR_COMP_SHIFT) +#define RCC_APB2ENR_COMP(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2ENR_COMP_SHIFT)) & RCC_APB2ENR_COMP_MASK) + +#define RCC_APB2ENR_SYSCFG_SHIFT (14) +#define RCC_APB2ENR_SYSCFG_MASK (0x01U << RCC_APB2ENR_SYSCFG_SHIFT) +#define RCC_APB2ENR_SYSCFG(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2ENR_SYSCFG_SHIFT)) & RCC_APB2ENR_SYSCFG_MASK) + +#define RCC_APB2ENR_SPI1_SHIFT (12) +#define RCC_APB2ENR_SPI1_MASK (0x01U << RCC_APB2ENR_SPI1_SHIFT) +#define RCC_APB2ENR_SPI1(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2ENR_SPI1_SHIFT)) & RCC_APB2ENR_SPI1_MASK) + +#define RCC_APB2ENR_ADC2_SHIFT (9) +#define RCC_APB2ENR_ADC2_MASK (0x01U << RCC_APB2ENR_ADC2_SHIFT) +#define RCC_APB2ENR_ADC2(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2ENR_ADC2_SHIFT)) & RCC_APB2ENR_ADC2_MASK) + +#define RCC_APB2ENR_ADC1_SHIFT (8) +#define RCC_APB2ENR_ADC1_MASK (0x01U << RCC_APB2ENR_ADC1_SHIFT) +#define RCC_APB2ENR_ADC1(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2ENR_ADC1_SHIFT)) & RCC_APB2ENR_ADC1_MASK) + +#define RCC_APB2ENR_UART6_SHIFT (5) +#define RCC_APB2ENR_UART6_MASK (0x01U << RCC_APB2ENR_UART6_SHIFT) +#define RCC_APB2ENR_UART6(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2ENR_UART6_SHIFT)) & RCC_APB2ENR_UART6_MASK) + +#define RCC_APB2ENR_UART1_SHIFT (4) +#define RCC_APB2ENR_UART1_MASK (0x01U << RCC_APB2ENR_UART1_SHIFT) +#define RCC_APB2ENR_UART1(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2ENR_UART1_SHIFT)) & RCC_APB2ENR_UART1_MASK) + +#define RCC_APB2ENR_TIM8_SHIFT (1) +#define RCC_APB2ENR_TIM8_MASK (0x01U << RCC_APB2ENR_TIM8_SHIFT) +#define RCC_APB2ENR_TIM8(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2ENR_TIM8_SHIFT)) & RCC_APB2ENR_TIM8_MASK) + +#define RCC_APB2ENR_TIM1_SHIFT (0) +#define RCC_APB2ENR_TIM1_MASK (0x01U << RCC_APB2ENR_TIM1_SHIFT) +#define RCC_APB2ENR_TIM1(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB2ENR_TIM1_SHIFT)) & RCC_APB2ENR_TIM1_MASK) + +/*! + * @brief RCC_APB1ENR Register Bit Definition + */ + +#define RCC_APB1ENR_UART7_SHIFT (30) +#define RCC_APB1ENR_UART7_MASK (0x01U << RCC_APB1ENR_UART7_SHIFT) +#define RCC_APB1ENR_UART7(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_UART7_SHIFT)) & RCC_APB1ENR_UART7_MASK) + +#define RCC_APB1ENR_DAC_SHIFT (29) +#define RCC_APB1ENR_DAC_MASK (0x01U << RCC_APB1ENR_DAC_SHIFT) +#define RCC_APB1ENR_DAC(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_DAC_SHIFT)) & RCC_APB1ENR_DAC_MASK) + +#define RCC_APB1ENR_PWRDBG_SHIFT (28) +#define RCC_APB1ENR_PWRDBG_MASK (0x01U << RCC_APB1ENR_PWRDBG_SHIFT) +#define RCC_APB1ENR_PWRDBG(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_PWRDBG_SHIFT)) & RCC_APB1ENR_PWRDBG_MASK) + +#define RCC_APB1ENR_BKP_SHIFT (27) +#define RCC_APB1ENR_BKP_MASK (0x01U << RCC_APB1ENR_BKP_SHIFT) +#define RCC_APB1ENR_BKP(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_BKP_SHIFT)) & RCC_APB1ENR_BKP_MASK) + +#define RCC_APB1ENR_FLEXCAN1_SHIFT (25) +#define RCC_APB1ENR_FLEXCAN1_MASK (0x01U << RCC_APB1ENR_FLEXCAN1_SHIFT) +#define RCC_APB1ENR_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_FLEXCAN1_SHIFT)) & RCC_APB1ENR_FLEXCAN1_MASK) + +#define RCC_APB1ENR_CRS_SHIFT (24) +#define RCC_APB1ENR_CRS_MASK (0x01U << RCC_APB1ENR_CRS_SHIFT) +#define RCC_APB1ENR_CRS(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_CRS_SHIFT)) & RCC_APB1ENR_CRS_MASK) + +#define RCC_APB1ENR_I2C2_SHIFT (22) +#define RCC_APB1ENR_I2C2_MASK (0x01U << RCC_APB1ENR_I2C2_SHIFT) +#define RCC_APB1ENR_I2C2(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_I2C2_SHIFT)) & RCC_APB1ENR_I2C2_MASK) + +#define RCC_APB1ENR_I2C1_SHIFT (21) +#define RCC_APB1ENR_I2C1_MASK (0x01U << RCC_APB1ENR_I2C1_SHIFT) +#define RCC_APB1ENR_I2C1(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_I2C1_SHIFT)) & RCC_APB1ENR_I2C1_MASK) + +#define RCC_APB1ENR_UART5_SHIFT (20) +#define RCC_APB1ENR_UART5_MASK (0x01U << RCC_APB1ENR_UART5_SHIFT) +#define RCC_APB1ENR_UART5(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_UART5_SHIFT)) & RCC_APB1ENR_UART5_MASK) + +#define RCC_APB1ENR_UART4_SHIFT (19) +#define RCC_APB1ENR_UART4_MASK (0x01U << RCC_APB1ENR_UART4_SHIFT) +#define RCC_APB1ENR_UART4(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_UART4_SHIFT)) & RCC_APB1ENR_UART4_MASK) + +#define RCC_APB1ENR_UART3_SHIFT (18) +#define RCC_APB1ENR_UART3_MASK (0x01U << RCC_APB1ENR_UART3_SHIFT) +#define RCC_APB1ENR_UART3(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_UART3_SHIFT)) & RCC_APB1ENR_UART3_MASK) + +#define RCC_APB1ENR_UART2_SHIFT (17) +#define RCC_APB1ENR_UART2_MASK (0x01U << RCC_APB1ENR_UART2_SHIFT) +#define RCC_APB1ENR_UART2(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_UART2_SHIFT)) & RCC_APB1ENR_UART2_MASK) + +#define RCC_APB1ENR_SPI3_SHIFT (15) +#define RCC_APB1ENR_SPI3_MASK (0x01U << RCC_APB1ENR_SPI3_SHIFT) +#define RCC_APB1ENR_SPI3(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_SPI3_SHIFT)) & RCC_APB1ENR_SPI3_MASK) + +#define RCC_APB1ENR_SPI2_SHIFT (14) +#define RCC_APB1ENR_SPI2_MASK (0x01U << RCC_APB1ENR_SPI2_SHIFT) +#define RCC_APB1ENR_SPI2(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_SPI2_SHIFT)) & RCC_APB1ENR_SPI2_MASK) + +#define RCC_APB1ENR_WWDG_SHIFT (11) +#define RCC_APB1ENR_WWDG_MASK (0x01U << RCC_APB1ENR_WWDG_SHIFT) +#define RCC_APB1ENR_WWDG(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_WWDG_SHIFT)) & RCC_APB1ENR_WWDG_MASK) + +#define RCC_APB1ENR_TIM7_SHIFT (5) +#define RCC_APB1ENR_TIM7_MASK (0x01U << RCC_APB1ENR_TIM7_SHIFT) +#define RCC_APB1ENR_TIM7(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_TIM7_SHIFT)) & RCC_APB1ENR_TIM7_MASK) + +#define RCC_APB1ENR_TIM6_SHIFT (4) +#define RCC_APB1ENR_TIM6_MASK (0x01U << RCC_APB1ENR_TIM6_SHIFT) +#define RCC_APB1ENR_TIM6(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_TIM6_SHIFT)) & RCC_APB1ENR_TIM6_MASK) + +#define RCC_APB1ENR_TIM5_SHIFT (3) +#define RCC_APB1ENR_TIM5_MASK (0x01U << RCC_APB1ENR_TIM5_SHIFT) +#define RCC_APB1ENR_TIM5(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_TIM5_SHIFT)) & RCC_APB1ENR_TIM5_MASK) + +#define RCC_APB1ENR_TIM4_SHIFT (2) +#define RCC_APB1ENR_TIM4_MASK (0x01U << RCC_APB1ENR_TIM4_SHIFT) +#define RCC_APB1ENR_TIM4(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_TIM4_SHIFT)) & RCC_APB1ENR_TIM4_MASK) + +#define RCC_APB1ENR_TIM3_SHIFT (1) +#define RCC_APB1ENR_TIM3_MASK (0x01U << RCC_APB1ENR_TIM3_SHIFT) +#define RCC_APB1ENR_TIM3(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_TIM3_SHIFT)) & RCC_APB1ENR_TIM3_MASK) + +#define RCC_APB1ENR_TIM2_SHIFT (0) +#define RCC_APB1ENR_TIM2_MASK (0x01U << RCC_APB1ENR_TIM2_SHIFT) +#define RCC_APB1ENR_TIM2(x) (((uint32_t)(((uint32_t)(x)) << RCC_APB1ENR_TIM2_SHIFT)) & RCC_APB1ENR_TIM2_MASK) + +/*! + * @brief RCC_BDCR Register Bit Definition + */ + +#define RCC_BDCR_DBP_SHIFT (24) +#define RCC_BDCR_DBP_MASK (0x01U << RCC_BDCR_DBP_SHIFT) +#define RCC_BDCR_DBP(x) (((uint32_t)(((uint32_t)(x)) << RCC_BDCR_DBP_SHIFT)) & RCC_BDCR_DBP_MASK) + +#define RCC_BDCR_BDRST_SHIFT (16) +#define RCC_BDCR_BDRST_MASK (0x01U << RCC_BDCR_BDRST_SHIFT) +#define RCC_BDCR_BDRST(x) (((uint32_t)(((uint32_t)(x)) << RCC_BDCR_BDRST_SHIFT)) & RCC_BDCR_BDRST_MASK) + +#define RCC_BDCR_RTCEN_SHIFT (15) +#define RCC_BDCR_RTCEN_MASK (0x01U << RCC_BDCR_RTCEN_SHIFT) +#define RCC_BDCR_RTCEN(x) (((uint32_t)(((uint32_t)(x)) << RCC_BDCR_RTCEN_SHIFT)) & RCC_BDCR_RTCEN_MASK) + +#define RCC_BDCR_RTCSEL_SHIFT (8) +#define RCC_BDCR_RTCSEL_MASK (0x3U << RCC_BDCR_RTCSEL_SHIFT) +#define RCC_BDCR_RTCSEL(x) (((uint32_t)(((uint32_t)(x)) << RCC_BDCR_RTCSEL_SHIFT)) & RCC_BDCR_RTCSEL_MASK) + +#define RCC_BDCR_LSEBYP_SHIFT (2) +#define RCC_BDCR_LSEBYP_MASK (0x01U << RCC_BDCR_LSEBYP_SHIFT) +#define RCC_BDCR_LSEBYP(x) (((uint32_t)(((uint32_t)(x)) << RCC_BDCR_LSEBYP_SHIFT)) & RCC_BDCR_LSEBYP_MASK) + +#define RCC_BDCR_LSERDY_SHIFT (1) +#define RCC_BDCR_LSERDY_MASK (0x01U << RCC_BDCR_LSERDY_SHIFT) +#define RCC_BDCR_LSERDY(x) (((uint32_t)(((uint32_t)(x)) << RCC_BDCR_LSERDY_SHIFT)) & RCC_BDCR_LSERDY_MASK) + +#define RCC_BDCR_LSEON_SHIFT (0) +#define RCC_BDCR_LSEON_MASK (0x01U << RCC_BDCR_LSEON_SHIFT) +#define RCC_BDCR_LSEON(x) (((uint32_t)(((uint32_t)(x)) << RCC_BDCR_LSEON_SHIFT)) & RCC_BDCR_LSEON_MASK) + +/*! + * @brief RCC_CSR Register Bit Definition + */ + +#define RCC_CSR_LPWRRSTF_SHIFT (31) +#define RCC_CSR_LPWRRSTF_MASK (0x01U << RCC_CSR_LPWRRSTF_SHIFT) +#define RCC_CSR_LPWRRSTF(x) (((uint32_t)(((uint32_t)(x)) << RCC_CSR_LPWRRSTF_SHIFT)) & RCC_CSR_LPWRRSTF_MASK) + +#define RCC_CSR_WWDGRSTF_SHIFT (30) +#define RCC_CSR_WWDGRSTF_MASK (0x01U << RCC_CSR_WWDGRSTF_SHIFT) +#define RCC_CSR_WWDGRSTF(x) (((uint32_t)(((uint32_t)(x)) << RCC_CSR_WWDGRSTF_SHIFT)) & RCC_CSR_WWDGRSTF_MASK) + +#define RCC_CSR_IWDGRSTF_SHIFT (29) +#define RCC_CSR_IWDGRSTF_MASK (0x01U << RCC_CSR_IWDGRSTF_SHIFT) +#define RCC_CSR_IWDGRSTF(x) (((uint32_t)(((uint32_t)(x)) << RCC_CSR_IWDGRSTF_SHIFT)) & RCC_CSR_IWDGRSTF_MASK) + +#define RCC_CSR_SFTRSTF_SHIFT (28) +#define RCC_CSR_SFTRSTF_MASK (0x01U << RCC_CSR_SFTRSTF_SHIFT) +#define RCC_CSR_SFTRSTF(x) (((uint32_t)(((uint32_t)(x)) << RCC_CSR_SFTRSTF_SHIFT)) & RCC_CSR_SFTRSTF_MASK) + +#define RCC_CSR_PORRSTF_SHIFT (27) +#define RCC_CSR_PORRSTF_MASK (0x01U << RCC_CSR_PORRSTF_SHIFT) +#define RCC_CSR_PORRSTF(x) (((uint32_t)(((uint32_t)(x)) << RCC_CSR_PORRSTF_SHIFT)) & RCC_CSR_PORRSTF_MASK) + +#define RCC_CSR_PINRSTF_SHIFT (26) +#define RCC_CSR_PINRSTF_MASK (0x01U << RCC_CSR_PINRSTF_SHIFT) +#define RCC_CSR_PINRSTF(x) (((uint32_t)(((uint32_t)(x)) << RCC_CSR_PINRSTF_SHIFT)) & RCC_CSR_PINRSTF_MASK) + +#define RCC_CSR_RMVF_SHIFT (24) +#define RCC_CSR_RMVF_MASK (0x01U << RCC_CSR_RMVF_SHIFT) +#define RCC_CSR_RMVF(x) (((uint32_t)(((uint32_t)(x)) << RCC_CSR_RMVF_SHIFT)) & RCC_CSR_RMVF_MASK) + +#define RCC_CSR_LOCKUPF_SHIFT (23) +#define RCC_CSR_LOCKUPF_MASK (0x01U << RCC_CSR_LOCKUPF_SHIFT) +#define RCC_CSR_LOCKUPF(x) (((uint32_t)(((uint32_t)(x)) << RCC_CSR_LOCKUPF_SHIFT)) & RCC_CSR_LOCKUPF_MASK) + +#define RCC_CSR_PVDRSTF_SHIFT (22) +#define RCC_CSR_PVDRSTF_MASK (0x01U << RCC_CSR_PVDRSTF_SHIFT) +#define RCC_CSR_PVDRSTF(x) (((uint32_t)(((uint32_t)(x)) << RCC_CSR_PVDRSTF_SHIFT)) & RCC_CSR_PVDRSTF_MASK) + +#define RCC_CSR_LOCKUPEN_SHIFT (7) +#define RCC_CSR_LOCKUPEN_MASK (0x01U << RCC_CSR_LOCKUPEN_SHIFT) +#define RCC_CSR_LOCKUPEN(x) (((uint32_t)(((uint32_t)(x)) << RCC_CSR_LOCKUPEN_SHIFT)) & RCC_CSR_LOCKUPEN_MASK) + +#define RCC_CSR_PVDRSTEN_SHIFT (6) +#define RCC_CSR_PVDRSTEN_MASK (0x01U << RCC_CSR_PVDRSTEN_SHIFT) +#define RCC_CSR_PVDRSTEN(x) (((uint32_t)(((uint32_t)(x)) << RCC_CSR_PVDRSTEN_SHIFT)) & RCC_CSR_PVDRSTEN_MASK) + +#define RCC_CSR_LSIOE_SHIFT (5) +#define RCC_CSR_LSIOE_MASK (0x01U << RCC_CSR_LSIOE_SHIFT) +#define RCC_CSR_LSIOE(x) (((uint32_t)(((uint32_t)(x)) << RCC_CSR_LSIOE_SHIFT)) & RCC_CSR_LSIOE_MASK) + +#define RCC_CSR_LSIRDY_SHIFT (1) +#define RCC_CSR_LSIRDY_MASK (0x01U << RCC_CSR_LSIRDY_SHIFT) +#define RCC_CSR_LSIRDY(x) (((uint32_t)(((uint32_t)(x)) << RCC_CSR_LSIRDY_SHIFT)) & RCC_CSR_LSIRDY_MASK) + +#define RCC_CSR_LSION_SHIFT (0) +#define RCC_CSR_LSION_MASK (0x01U << RCC_CSR_LSION_SHIFT) +#define RCC_CSR_LSION(x) (((uint32_t)(((uint32_t)(x)) << RCC_CSR_LSION_SHIFT)) & RCC_CSR_LSION_MASK) + +/*! + * @brief RCC_SYSCFG Register Bit Definition + */ + +#define RCC_SYSCFG_HSELPFEN_SHIFT (14) +#define RCC_SYSCFG_HSELPFEN_MASK (0x01U << RCC_SYSCFG_HSELPFEN_SHIFT) +#define RCC_SYSCFG_HSELPFEN(x) (((uint32_t)(((uint32_t)(x)) << RCC_SYSCFG_HSELPFEN_SHIFT)) & RCC_SYSCFG_HSELPFEN_MASK) + +#define RCC_SYSCFG_HSERFBSEL_SHIFT (8) +#define RCC_SYSCFG_HSERFBSEL_MASK (0x3U << RCC_SYSCFG_HSERFBSEL_SHIFT) +#define RCC_SYSCFG_HSERFBSEL(x) (((uint32_t)(((uint32_t)(x)) << RCC_SYSCFG_HSERFBSEL_SHIFT)) & RCC_SYSCFG_HSERFBSEL_MASK) + +#define RCC_SYSCFG_SECTOR1KCFG_SHIFT (1) +#define RCC_SYSCFG_SECTOR1KCFG_MASK (0x01U << RCC_SYSCFG_SECTOR1KCFG_SHIFT) +#define RCC_SYSCFG_SECTOR1KCFG(x) (((uint32_t)(((uint32_t)(x)) << RCC_SYSCFG_SECTOR1KCFG_SHIFT)) & RCC_SYSCFG_SECTOR1KCFG_MASK) + +#define RCC_SYSCFG_PROGCHECKEN_SHIFT (0) +#define RCC_SYSCFG_PROGCHECKEN_MASK (0x01U << RCC_SYSCFG_PROGCHECKEN_SHIFT) +#define RCC_SYSCFG_PROGCHECKEN(x) (((uint32_t)(((uint32_t)(x)) << RCC_SYSCFG_PROGCHECKEN_SHIFT)) & RCC_SYSCFG_PROGCHECKEN_MASK) + +/*! + * @brief RCC_CFGR2 Register Bit Definition + */ + +#define RCC_CFGR2_LPTIMCLKSEL_SHIFT (29) +#define RCC_CFGR2_LPTIMCLKSEL_MASK (0x3U << RCC_CFGR2_LPTIMCLKSEL_SHIFT) +#define RCC_CFGR2_LPTIMCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << RCC_CFGR2_LPTIMCLKSEL_SHIFT)) & RCC_CFGR2_LPTIMCLKSEL_MASK) + +#define RCC_CFGR2_LPUARTCLKSEL_SHIFT (26) +#define RCC_CFGR2_LPUARTCLKSEL_MASK (0x3U << RCC_CFGR2_LPUARTCLKSEL_SHIFT) +#define RCC_CFGR2_LPUARTCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << RCC_CFGR2_LPUARTCLKSEL_SHIFT)) & RCC_CFGR2_LPUARTCLKSEL_MASK) + +#define RCC_CFGR2_MCOPRE_SHIFT (20) +#define RCC_CFGR2_MCOPRE_MASK (0xFU << RCC_CFGR2_MCOPRE_SHIFT) +#define RCC_CFGR2_MCOPRE(x) (((uint32_t)(((uint32_t)(x)) << RCC_CFGR2_MCOPRE_SHIFT)) & RCC_CFGR2_MCOPRE_MASK) + +#define RCC_CFGR2_APB1CLKHVPRE_SHIFT (16) +#define RCC_CFGR2_APB1CLKHVPRE_MASK (0xFU << RCC_CFGR2_APB1CLKHVPRE_SHIFT) +#define RCC_CFGR2_APB1CLKHVPRE(x) (((uint32_t)(((uint32_t)(x)) << RCC_CFGR2_APB1CLKHVPRE_SHIFT)) & RCC_CFGR2_APB1CLKHVPRE_MASK) + +#define RCC_CFGR2_TIMADVPRE_SHIFT (1) +#define RCC_CFGR2_TIMADVPRE_MASK (0x7U << RCC_CFGR2_TIMADVPRE_SHIFT) +#define RCC_CFGR2_TIMADVPRE(x) (((uint32_t)(((uint32_t)(x)) << RCC_CFGR2_TIMADVPRE_SHIFT)) & RCC_CFGR2_TIMADVPRE_MASK) + +#define RCC_CFGR2_TIMADVCKSEL_SHIFT (0) +#define RCC_CFGR2_TIMADVCKSEL_MASK (0x01U << RCC_CFGR2_TIMADVCKSEL_SHIFT) +#define RCC_CFGR2_TIMADVCKSEL(x) (((uint32_t)(((uint32_t)(x)) << RCC_CFGR2_TIMADVCKSEL_SHIFT)) & RCC_CFGR2_TIMADVCKSEL_MASK) + +/*! + * @brief RCC_PLL1CFGR Register Bit Definition + */ + +#define RCC_PLL1CFGR_PLL1MUL_SHIFT (16) +#define RCC_PLL1CFGR_PLL1MUL_MASK (0x7FU << RCC_PLL1CFGR_PLL1MUL_SHIFT) +#define RCC_PLL1CFGR_PLL1MUL(x) (((uint32_t)(((uint32_t)(x)) << RCC_PLL1CFGR_PLL1MUL_SHIFT)) & RCC_PLL1CFGR_PLL1MUL_MASK) + +#define RCC_PLL1CFGR_PLL1DIV_SHIFT (8) +#define RCC_PLL1CFGR_PLL1DIV_MASK (0x7U << RCC_PLL1CFGR_PLL1DIV_SHIFT) +#define RCC_PLL1CFGR_PLL1DIV(x) (((uint32_t)(((uint32_t)(x)) << RCC_PLL1CFGR_PLL1DIV_SHIFT)) & RCC_PLL1CFGR_PLL1DIV_MASK) + +#define RCC_PLL1CFGR_PLL1LDS_SHIFT (4) +#define RCC_PLL1CFGR_PLL1LDS_MASK (0x7U << RCC_PLL1CFGR_PLL1LDS_SHIFT) +#define RCC_PLL1CFGR_PLL1LDS(x) (((uint32_t)(((uint32_t)(x)) << RCC_PLL1CFGR_PLL1LDS_SHIFT)) & RCC_PLL1CFGR_PLL1LDS_MASK) + +#define RCC_PLL1CFGR_PLL1ICTRL_SHIFT (2) +#define RCC_PLL1CFGR_PLL1ICTRL_MASK (0x3U << RCC_PLL1CFGR_PLL1ICTRL_SHIFT) +#define RCC_PLL1CFGR_PLL1ICTRL(x) (((uint32_t)(((uint32_t)(x)) << RCC_PLL1CFGR_PLL1ICTRL_SHIFT)) & RCC_PLL1CFGR_PLL1ICTRL_MASK) + +#define RCC_PLL1CFGR_PLL1XTPRE_SHIFT (1) +#define RCC_PLL1CFGR_PLL1XTPRE_MASK (0x01U << RCC_PLL1CFGR_PLL1XTPRE_SHIFT) +#define RCC_PLL1CFGR_PLL1XTPRE(x) (((uint32_t)(((uint32_t)(x)) << RCC_PLL1CFGR_PLL1XTPRE_SHIFT)) & RCC_PLL1CFGR_PLL1XTPRE_MASK) + +#define RCC_PLL1CFGR_PLL1SRC_SHIFT (0) +#define RCC_PLL1CFGR_PLL1SRC_MASK (0x01U << RCC_PLL1CFGR_PLL1SRC_SHIFT) +#define RCC_PLL1CFGR_PLL1SRC(x) (((uint32_t)(((uint32_t)(x)) << RCC_PLL1CFGR_PLL1SRC_SHIFT)) & RCC_PLL1CFGR_PLL1SRC_MASK) + +/*! + * @brief RCC_PLL2CFGR Register Bit Definition + */ + +#define RCC_PLL2CFGR_PLL2PDIV_SHIFT (24) +#define RCC_PLL2CFGR_PLL2PDIV_MASK (0x7U << RCC_PLL2CFGR_PLL2PDIV_SHIFT) +#define RCC_PLL2CFGR_PLL2PDIV(x) (((uint32_t)(((uint32_t)(x)) << RCC_PLL2CFGR_PLL2PDIV_SHIFT)) & RCC_PLL2CFGR_PLL2PDIV_MASK) + +#define RCC_PLL2CFGR_PLL2MUL_SHIFT (16) +#define RCC_PLL2CFGR_PLL2MUL_MASK (0xFFU << RCC_PLL2CFGR_PLL2MUL_SHIFT) +#define RCC_PLL2CFGR_PLL2MUL(x) (((uint32_t)(((uint32_t)(x)) << RCC_PLL2CFGR_PLL2MUL_SHIFT)) & RCC_PLL2CFGR_PLL2MUL_MASK) + +#define RCC_PLL2CFGR_PLL2DIV_SHIFT (8) +#define RCC_PLL2CFGR_PLL2DIV_MASK (0x7U << RCC_PLL2CFGR_PLL2DIV_SHIFT) +#define RCC_PLL2CFGR_PLL2DIV(x) (((uint32_t)(((uint32_t)(x)) << RCC_PLL2CFGR_PLL2DIV_SHIFT)) & RCC_PLL2CFGR_PLL2DIV_MASK) + +#define RCC_PLL2CFGR_PLL2LDS_SHIFT (4) +#define RCC_PLL2CFGR_PLL2LDS_MASK (0x7U << RCC_PLL2CFGR_PLL2LDS_SHIFT) +#define RCC_PLL2CFGR_PLL2LDS(x) (((uint32_t)(((uint32_t)(x)) << RCC_PLL2CFGR_PLL2LDS_SHIFT)) & RCC_PLL2CFGR_PLL2LDS_MASK) + +#define RCC_PLL2CFGR_PLL2ICTRL_SHIFT (2) +#define RCC_PLL2CFGR_PLL2ICTRL_MASK (0x3U << RCC_PLL2CFGR_PLL2ICTRL_SHIFT) +#define RCC_PLL2CFGR_PLL2ICTRL(x) (((uint32_t)(((uint32_t)(x)) << RCC_PLL2CFGR_PLL2ICTRL_SHIFT)) & RCC_PLL2CFGR_PLL2ICTRL_MASK) + +#define RCC_PLL2CFGR_PLL2XTPRE_SHIFT (1) +#define RCC_PLL2CFGR_PLL2XTPRE_MASK (0x01U << RCC_PLL2CFGR_PLL2XTPRE_SHIFT) +#define RCC_PLL2CFGR_PLL2XTPRE(x) (((uint32_t)(((uint32_t)(x)) << RCC_PLL2CFGR_PLL2XTPRE_SHIFT)) & RCC_PLL2CFGR_PLL2XTPRE_MASK) + +#define RCC_PLL2CFGR_PLL2SRC_SHIFT (0) +#define RCC_PLL2CFGR_PLL2SRC_MASK (0x01U << RCC_PLL2CFGR_PLL2SRC_SHIFT) +#define RCC_PLL2CFGR_PLL2SRC(x) (((uint32_t)(((uint32_t)(x)) << RCC_PLL2CFGR_PLL2SRC_SHIFT)) & RCC_PLL2CFGR_PLL2SRC_MASK) + +/*! + * @brief RCC_ADC1CFGR Register Bit Definition + */ + +#define RCC_ADC1CFGR_PRECAL_SHIFT (8) +#define RCC_ADC1CFGR_PRECAL_MASK (0x1FFU << RCC_ADC1CFGR_PRECAL_SHIFT) +#define RCC_ADC1CFGR_PRECAL(x) (((uint32_t)(((uint32_t)(x)) << RCC_ADC1CFGR_PRECAL_SHIFT)) & RCC_ADC1CFGR_PRECAL_MASK) + +#define RCC_ADC1CFGR_PRE_SHIFT (0) +#define RCC_ADC1CFGR_PRE_MASK (0xFU << RCC_ADC1CFGR_PRE_SHIFT) +#define RCC_ADC1CFGR_PRE(x) (((uint32_t)(((uint32_t)(x)) << RCC_ADC1CFGR_PRE_SHIFT)) & RCC_ADC1CFGR_PRE_MASK) + +/*! + * @brief RCC_ADC2CFGR Register Bit Definition + */ + +#define RCC_ADC2CFGR_PRECAL_SHIFT (8) +#define RCC_ADC2CFGR_PRECAL_MASK (0x1FFU << RCC_ADC2CFGR_PRECAL_SHIFT) +#define RCC_ADC2CFGR_PRECAL(x) (((uint32_t)(((uint32_t)(x)) << RCC_ADC2CFGR_PRECAL_SHIFT)) & RCC_ADC2CFGR_PRECAL_MASK) + +#define RCC_ADC2CFGR_PRE_SHIFT (0) +#define RCC_ADC2CFGR_PRE_MASK (0xFU << RCC_ADC2CFGR_PRE_SHIFT) +#define RCC_ADC2CFGR_PRE(x) (((uint32_t)(((uint32_t)(x)) << RCC_ADC2CFGR_PRE_SHIFT)) & RCC_ADC2CFGR_PRE_MASK) + +/*! + * @brief RCC_DACCFGR Register Bit Definition + */ + +#define RCC_DACCFGR_PRE_SHIFT (0) +#define RCC_DACCFGR_PRE_MASK (0x7FU << RCC_DACCFGR_PRE_SHIFT) +#define RCC_DACCFGR_PRE(x) (((uint32_t)(((uint32_t)(x)) << RCC_DACCFGR_PRE_SHIFT)) & RCC_DACCFGR_PRE_MASK) + +/*! + * @brief RCC_FSMCCFGR Register Bit Definition + */ + +#define RCC_FSMCCFGR_FSMCSYNCEN_SHIFT (8) +#define RCC_FSMCCFGR_FSMCSYNCEN_MASK (0x01U << RCC_FSMCCFGR_FSMCSYNCEN_SHIFT) +#define RCC_FSMCCFGR_FSMCSYNCEN(x) (((uint32_t)(((uint32_t)(x)) << RCC_FSMCCFGR_FSMCSYNCEN_SHIFT)) & RCC_FSMCCFGR_FSMCSYNCEN_MASK) + +#define RCC_FSMCCFGR_FSMCPRE_SHIFT (0) +#define RCC_FSMCCFGR_FSMCPRE_MASK (0x1FU << RCC_FSMCCFGR_FSMCPRE_SHIFT) +#define RCC_FSMCCFGR_FSMCPRE(x) (((uint32_t)(((uint32_t)(x)) << RCC_FSMCCFGR_FSMCPRE_SHIFT)) & RCC_FSMCCFGR_FSMCPRE_MASK) + +/*! + * @brief RCC_TPIUCFGR Register Bit Definition + */ + +#define RCC_TPIUCFGR_PRE_SHIFT (0) +#define RCC_TPIUCFGR_PRE_MASK (0x3U << RCC_TPIUCFGR_PRE_SHIFT) +#define RCC_TPIUCFGR_PRE(x) (((uint32_t)(((uint32_t)(x)) << RCC_TPIUCFGR_PRE_SHIFT)) & RCC_TPIUCFGR_PRE_MASK) + +/*! + * @} + */ /* end of group RCC_Register_Masks */ +/****************************************************************************** + *RCC Instance +*******************************************************************************/ + +#define RCC ((RCC_Type*)RCC_BASE) + +/*! + * @} + */ /* end of group RCC_Peripheral_Access_Layer */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * RTC Type + ******************************************************************************/ +typedef struct { + __IO uint32_t CRH; ///< RTC control register high bits offset: 0x00 + __IO uint32_t CRL; ///< RTC control register low bits offset: 0x04 + __IO uint32_t PRLH; ///< RTC prescaler load register high bits offset: 0x08 + __IO uint32_t PRLL; ///< RTC prescaler load register low bits offset: 0x0C + __IO uint32_t DIVH; ///< RTC prescaler division factor register high bitsoffset: 0x10 + __IO uint32_t DIVL; ///< RTC prescaler division factor register low bitsoffset: 0x14 + __IO uint32_t CNTH; ///< RTC counter register high bits offset: 0x18 + __IO uint32_t CNTL; ///< RTC counter register low bits offset: 0x1C + __IO uint32_t ALRH; ///< RTC alarm register high bit offset: 0x20 + __IO uint32_t ALRL; ///< RTC alarm register low bits offset: 0x24 + __IO uint32_t MSRH; ///< RTC millisecond register high bit offset: 0x28 + __IO uint32_t MSRL; ///< RTC millisecond register low bit offset: 0x2C + __IO uint32_t Reserved48[3]; ///< Reserved + __IO uint32_t LSECFG; ///< RTC LSE Configuration Register offset: 0x3C +} RTC_Type; + +/******************************************************************************* + * RTC Type + ******************************************************************************/ + +/*! + * @addtogroup RTC_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief RTC_CRH Register Bit Definition + */ + +#define RTC_CRH_OWIE_SHIFT (2) +#define RTC_CRH_OWIE_MASK (0x01U << RTC_CRH_OWIE_SHIFT) +#define RTC_CRH_OWIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CRH_OWIE_SHIFT)) & RTC_CRH_OWIE_MASK) + +#define RTC_CRH_ALRIE_SHIFT (1) +#define RTC_CRH_ALRIE_MASK (0x01U << RTC_CRH_ALRIE_SHIFT) +#define RTC_CRH_ALRIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CRH_ALRIE_SHIFT)) & RTC_CRH_ALRIE_MASK) + +#define RTC_CRH_SECIE_SHIFT (0) +#define RTC_CRH_SECIE_MASK (0x01U << RTC_CRH_SECIE_SHIFT) +#define RTC_CRH_SECIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CRH_SECIE_SHIFT)) & RTC_CRH_SECIE_MASK) + +/*! + * @brief RTC_CRL Register Bit Definition + */ + +#define RTC_CRL_ALPEN_SHIFT (6) +#define RTC_CRL_ALPEN_MASK (0x01U << RTC_CRL_ALPEN_SHIFT) +#define RTC_CRL_ALPEN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CRL_ALPEN_SHIFT)) & RTC_CRL_ALPEN_MASK) + +#define RTC_CRL_RTOFF_SHIFT (5) +#define RTC_CRL_RTOFF_MASK (0x01U << RTC_CRL_RTOFF_SHIFT) +#define RTC_CRL_RTOFF(x) (((uint32_t)(((uint32_t)(x)) << RTC_CRL_RTOFF_SHIFT)) & RTC_CRL_RTOFF_MASK) + +#define RTC_CRL_CNF_SHIFT (4) +#define RTC_CRL_CNF_MASK (0x01U << RTC_CRL_CNF_SHIFT) +#define RTC_CRL_CNF(x) (((uint32_t)(((uint32_t)(x)) << RTC_CRL_CNF_SHIFT)) & RTC_CRL_CNF_MASK) + +#define RTC_CRL_RSF_SHIFT (3) +#define RTC_CRL_RSF_MASK (0x01U << RTC_CRL_RSF_SHIFT) +#define RTC_CRL_RSF(x) (((uint32_t)(((uint32_t)(x)) << RTC_CRL_RSF_SHIFT)) & RTC_CRL_RSF_MASK) + +#define RTC_CRL_OWF_SHIFT (2) +#define RTC_CRL_OWF_MASK (0x01U << RTC_CRL_OWF_SHIFT) +#define RTC_CRL_OWF(x) (((uint32_t)(((uint32_t)(x)) << RTC_CRL_OWF_SHIFT)) & RTC_CRL_OWF_MASK) + +#define RTC_CRL_ALRF_SHIFT (1) +#define RTC_CRL_ALRF_MASK (0x01U << RTC_CRL_ALRF_SHIFT) +#define RTC_CRL_ALRF(x) (((uint32_t)(((uint32_t)(x)) << RTC_CRL_ALRF_SHIFT)) & RTC_CRL_ALRF_MASK) + +#define RTC_CRL_SECF_SHIFT (0) +#define RTC_CRL_SECF_MASK (0x01U << RTC_CRL_SECF_SHIFT) +#define RTC_CRL_SECF(x) (((uint32_t)(((uint32_t)(x)) << RTC_CRL_SECF_SHIFT)) & RTC_CRL_SECF_MASK) + +/*! + * @brief RTC_PRLH Register Bit Definition + */ + +#define RTC_PRLH_PRL_SHIFT (0) +#define RTC_PRLH_PRL_MASK (0xFU << RTC_PRLH_PRL_SHIFT) +#define RTC_PRLH_PRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_PRLH_PRL_SHIFT)) & RTC_PRLH_PRL_MASK) + +/*! + * @brief RTC_PRLL Register Bit Definition + */ + +#define RTC_PRLL_PRL_SHIFT (0) +#define RTC_PRLL_PRL_MASK (0xFFFFU << RTC_PRLL_PRL_SHIFT) +#define RTC_PRLL_PRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_PRLL_PRL_SHIFT)) & RTC_PRLL_PRL_MASK) + +/*! + * @brief RTC_DIVH Register Bit Definition + */ + +#define RTC_DIVH_DIV_SHIFT (0) +#define RTC_DIVH_DIV_MASK (0xFU << RTC_DIVH_DIV_SHIFT) +#define RTC_DIVH_DIV(x) (((uint32_t)(((uint32_t)(x)) << RTC_DIVH_DIV_SHIFT)) & RTC_DIVH_DIV_MASK) + +/*! + * @brief RTC_DIVL Register Bit Definition + */ + +#define RTC_DIVL_DIV_SHIFT (0) +#define RTC_DIVL_DIV_MASK (0xFFFFU << RTC_DIVL_DIV_SHIFT) +#define RTC_DIVL_DIV(x) (((uint32_t)(((uint32_t)(x)) << RTC_DIVL_DIV_SHIFT)) & RTC_DIVL_DIV_MASK) + +/*! + * @brief RTC_CNTH Register Bit Definition + */ + +#define RTC_CNTH_CNT_SHIFT (0) +#define RTC_CNTH_CNT_MASK (0xFFFFU << RTC_CNTH_CNT_SHIFT) +#define RTC_CNTH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNTH_CNT_SHIFT)) & RTC_CNTH_CNT_MASK) + +/*! + * @brief RTC_CNTL Register Bit Definition + */ + +#define RTC_CNTL_CNT_SHIFT (0) +#define RTC_CNTL_CNT_MASK (0xFFFFU << RTC_CNTL_CNT_SHIFT) +#define RTC_CNTL_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNTL_CNT_SHIFT)) & RTC_CNTL_CNT_MASK) + +/*! + * @brief RTC_ALRH Register Bit Definition + */ + +#define RTC_ALRH_ALR_SHIFT (0) +#define RTC_ALRH_ALR_MASK (0xFFFFU << RTC_ALRH_ALR_SHIFT) +#define RTC_ALRH_ALR(x) (((uint32_t)(((uint32_t)(x)) << RTC_ALRH_ALR_SHIFT)) & RTC_ALRH_ALR_MASK) + +/*! + * @brief RTC_ALRL Register Bit Definition + */ + +#define RTC_ALRL_ALR_SHIFT (0) +#define RTC_ALRL_ALR_MASK (0xFFFFU << RTC_ALRL_ALR_SHIFT) +#define RTC_ALRL_ALR(x) (((uint32_t)(((uint32_t)(x)) << RTC_ALRL_ALR_SHIFT)) & RTC_ALRL_ALR_MASK) + +/*! + * @brief RTC_MSRH Register Bit Definition + */ + +#define RTC_MSRH_MSR_SHIFT (0) +#define RTC_MSRH_MSR_MASK (0xFU << RTC_MSRH_MSR_SHIFT) +#define RTC_MSRH_MSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_MSRH_MSR_SHIFT)) & RTC_MSRH_MSR_MASK) + +/*! + * @brief RTC_MSRL Register Bit Definition + */ + +#define RTC_MSRL_MSR_SHIFT (0) +#define RTC_MSRL_MSR_MASK (0xFFFFU << RTC_MSRL_MSR_SHIFT) +#define RTC_MSRL_MSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_MSRL_MSR_SHIFT)) & RTC_MSRL_MSR_MASK) + +/*! + * @brief RTC_LSE_CFG Register Bit Definition + */ + +#define RTC_LSECFG_LSEAAC_SHIFT (10) +#define RTC_LSECFG_LSEAAC_MASK (0x01U << RTC_LSECFG_LSEAAC_SHIFT) +#define RTC_LSECFG_LSEAAC(x) (((uint32_t)(((uint32_t)(x)) << RTC_LSECFG_LSEAAC_SHIFT)) & RTC_LSECFG_LSEAAC_MASK) + +#define RTC_LSECFG_LSEIB_SHIFT (8) +#define RTC_LSECFG_LSEIB_MASK (0x3U << RTC_LSECFG_LSEIB_SHIFT) +#define RTC_LSECFG_LSEIB(x) (((uint32_t)(((uint32_t)(x)) << RTC_LSECFG_LSEIB_SHIFT)) & RTC_LSECFG_LSEIB_MASK) + +#define RTC_LSECFG_LSERFBSEL_SHIFT (6) +#define RTC_LSECFG_LSERFBSEL_MASK (0x3U << RTC_LSECFG_LSERFBSEL_SHIFT) +#define RTC_LSECFG_LSERFBSEL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LSECFG_LSERFBSEL_SHIFT)) & RTC_LSECFG_LSERFBSEL_MASK) + +#define RTC_LSECFG_LSEDR_SHIFT (4) +#define RTC_LSECFG_LSEDR_MASK (0x3U << RTC_LSECFG_LSEDR_SHIFT) +#define RTC_LSECFG_LSEDR(x) (((uint32_t)(((uint32_t)(x)) << RTC_LSECFG_LSEDR_SHIFT)) & RTC_LSECFG_LSEDR_MASK) + +#define RTC_LSECFG_LSEOUTENH_SHIFT (2) +#define RTC_LSECFG_LSEOUTENH_MASK (0x01U << RTC_LSECFG_LSEOUTENH_SHIFT) +#define RTC_LSECFG_LSEOUTENH(x) (((uint32_t)(((uint32_t)(x)) << RTC_LSECFG_LSEOUTENH_SHIFT)) & RTC_LSECFG_LSEOUTENH_MASK) + +#define RTC_LSECFG_LSETC_SHIFT (0) +#define RTC_LSECFG_LSETC_MASK (0x02U << RTC_LSECFG_LSETC_SHIFT) +#define RTC_LSECFG_LSETC(x) (((uint32_t)(((uint32_t)(x)) << RTC_LSECFG_LSETC_SHIFT)) & RTC_LSECFG_LSETC_MASK) + +/*! + * @} + */ /* end of group RTC_Register_Masks */ +/****************************************************************************** + *RTC Instance +*******************************************************************************/ + +#define RTC ((RTC_Type*)RTC_BKP_BASE) + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + + + +/*! + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * SPI Type + ******************************************************************************/ +typedef struct { + __IO uint32_t TXREG; ///< transmit data register offset: 0x00 + __IO uint32_t RXREG; ///< receive data register offset: 0x04 + __IO uint32_t CSTAT; ///< current status register offset: 0x08 + __IO uint32_t INTSTAT; ///< Interrupt Status Register offset: 0x0C + __IO uint32_t INTEN; ///< Interrupt Enable Register offset: 0x10 + __IO uint32_t INTCLR; ///< interrupt clear register offset: 0x14 + __IO uint32_t GCTL; ///< global control register offset: 0x18 + __IO uint32_t CCTL; ///< General Control Register offset: 0x1C + __IO uint32_t SPBRG; ///< baud rate generator offset: 0x20 + __IO uint32_t RXDNR; ///< Receive data count register offset: 0x24 + __IO uint32_t NSSR; ///< Slave Chip Select Register offset: 0x28 + __IO uint32_t EXTCTL; ///< data control register offset: 0x2C + __IO uint32_t I2SCFGR; ///< I2S_ configuration register offset: 0x30 +} SPI_Type, I2S_Type; + +/******************************************************************************* + * SPI Type + ******************************************************************************/ + +/*! + * @addtogroup SPI_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief SPI_I2S_TXREG Register Bit Definition + */ + +#define SPI_I2S_TXREG_TXREG_SHIFT (0) +#define SPI_I2S_TXREG_TXREG_MASK (0xFFFFFFFFU << SPI_I2S_TXREG_TXREG_SHIFT) +#define SPI_I2S_TXREG_TXREG(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_TXREG_TXREG_SHIFT)) & SPI_I2S_TXREG_TXREG_MASK) + +/*! + * @brief SPI_I2S_RXREG Register Bit Definition + */ + +#define SPI_I2S_RXREG_RXREG_SHIFT (0) +#define SPI_I2S_RXREG_RXREG_MASK (0xFFFFFFFFU << SPI_I2S_RXREG_RXREG_SHIFT) +#define SPI_I2S_RXREG_RXREG(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_RXREG_RXREG_SHIFT)) & SPI_I2S_RXREG_RXREG_MASK) + +/*! + * @brief SPI_I2S_CSTAT Register Bit Definition + */ + +#define SPI_I2S_CSTAT_CHSIDE_SHIFT (13) +#define SPI_I2S_CSTAT_CHSIDE_MASK (0x01U << SPI_I2S_CSTAT_CHSIDE_SHIFT) +#define SPI_I2S_CSTAT_CHSIDE(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_CSTAT_CHSIDE_SHIFT)) & SPI_I2S_CSTAT_CHSIDE_MASK) + +#define SPI_I2S_CSTAT_BUSY_SHIFT (12) +#define SPI_I2S_CSTAT_BUSY_MASK (0x01U << SPI_I2S_CSTAT_BUSY_SHIFT) +#define SPI_I2S_CSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_CSTAT_BUSY_SHIFT)) & SPI_I2S_CSTAT_BUSY_MASK) + +#define SPI_I2S_CSTAT_RXFADDR_SHIFT (8) +#define SPI_I2S_CSTAT_RXFADDR_MASK (0xFU << SPI_I2S_CSTAT_RXFADDR_SHIFT) +#define SPI_I2S_CSTAT_RXFADDR(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_CSTAT_RXFADDR_SHIFT)) & SPI_I2S_CSTAT_RXFADDR_MASK) + +#define SPI_I2S_CSTAT_TXFADDR_SHIFT (4) +#define SPI_I2S_CSTAT_TXFADDR_MASK (0xFU << SPI_I2S_CSTAT_TXFADDR_SHIFT) +#define SPI_I2S_CSTAT_TXFADDR(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_CSTAT_TXFADDR_SHIFT)) & SPI_I2S_CSTAT_TXFADDR_MASK) + +#define SPI_I2S_CSTAT_RXAVL4BYTE_SHIFT (3) +#define SPI_I2S_CSTAT_RXAVL4BYTE_MASK (0x01U << SPI_I2S_CSTAT_RXAVL4BYTE_SHIFT) +#define SPI_I2S_CSTAT_RXAVL4BYTE(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_CSTAT_RXAVL4BYTE_SHIFT)) & SPI_I2S_CSTAT_RXAVL4BYTE_MASK) + +#define SPI_I2S_CSTAT_TXFULL_SHIFT (2) +#define SPI_I2S_CSTAT_TXFULL_MASK (0x01U << SPI_I2S_CSTAT_TXFULL_SHIFT) +#define SPI_I2S_CSTAT_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_CSTAT_TXFULL_SHIFT)) & SPI_I2S_CSTAT_TXFULL_MASK) + +#define SPI_I2S_CSTAT_RXAVL_SHIFT (1) +#define SPI_I2S_CSTAT_RXAVL_MASK (0x01U << SPI_I2S_CSTAT_RXAVL_SHIFT) +#define SPI_I2S_CSTAT_RXAVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_CSTAT_RXAVL_SHIFT)) & SPI_I2S_CSTAT_RXAVL_MASK) + +#define SPI_I2S_CSTAT_TXEPT_SHIFT (0) +#define SPI_I2S_CSTAT_TXEPT_MASK (0x01U << SPI_I2S_CSTAT_TXEPT_SHIFT) +#define SPI_I2S_CSTAT_TXEPT(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_CSTAT_TXEPT_SHIFT)) & SPI_I2S_CSTAT_TXEPT_MASK) + +/*! + * @brief SPI_I2S_INTSTAT Register Bit Definition + */ + +#define SPI_I2S_INTSTAT_FREINTF_SHIFT (7) +#define SPI_I2S_INTSTAT_FREINTF_MASK (0x01U << SPI_I2S_INTSTAT_FREINTF_SHIFT) +#define SPI_I2S_INTSTAT_FREINTF(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTSTAT_FREINTF_SHIFT)) & SPI_I2S_INTSTAT_FREINTF_MASK) + +#define SPI_I2S_INTSTAT_TXEPTINTF_SHIFT (6) +#define SPI_I2S_INTSTAT_TXEPTINTF_MASK (0x01U << SPI_I2S_INTSTAT_TXEPTINTF_SHIFT) +#define SPI_I2S_INTSTAT_TXEPTINTF(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTSTAT_TXEPTINTF_SHIFT)) & SPI_I2S_INTSTAT_TXEPTINTF_MASK) + +#define SPI_I2S_INTSTAT_RXFULLINTF_SHIFT (5) +#define SPI_I2S_INTSTAT_RXFULLINTF_MASK (0x01U << SPI_I2S_INTSTAT_RXFULLINTF_SHIFT) +#define SPI_I2S_INTSTAT_RXFULLINTF(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTSTAT_RXFULLINTF_SHIFT)) & SPI_I2S_INTSTAT_RXFULLINTF_MASK) + +#define SPI_I2S_INTSTAT_RXMATCHINTF_SHIFT (4) +#define SPI_I2S_INTSTAT_RXMATCHINTF_MASK (0x01U << SPI_I2S_INTSTAT_RXMATCHINTF_SHIFT) +#define SPI_I2S_INTSTAT_RXMATCHINTF(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTSTAT_RXMATCHINTF_SHIFT)) & SPI_I2S_INTSTAT_RXMATCHINTF_MASK) + +#define SPI_I2S_INTSTAT_RXOERRINTF_SHIFT (3) +#define SPI_I2S_INTSTAT_RXOERRINTF_MASK (0x01U << SPI_I2S_INTSTAT_RXOERRINTF_SHIFT) +#define SPI_I2S_INTSTAT_RXOERRINTF(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTSTAT_RXOERRINTF_SHIFT)) & SPI_I2S_INTSTAT_RXOERRINTF_MASK) + +#define SPI_I2S_INTSTAT_UNDERRUNINTF_SHIFT (2) +#define SPI_I2S_INTSTAT_UNDERRUNINTF_MASK (0x01U << SPI_I2S_INTSTAT_UNDERRUNINTF_SHIFT) +#define SPI_I2S_INTSTAT_UNDERRUNINTF(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTSTAT_UNDERRUNINTF_SHIFT)) & SPI_I2S_INTSTAT_UNDERRUNINTF_MASK) + +#define SPI_I2S_INTSTAT_RXINTF_SHIFT (1) +#define SPI_I2S_INTSTAT_RXINTF_MASK (0x01U << SPI_I2S_INTSTAT_RXINTF_SHIFT) +#define SPI_I2S_INTSTAT_RXINTF(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTSTAT_RXINTF_SHIFT)) & SPI_I2S_INTSTAT_RXINTF_MASK) + +#define SPI_I2S_INTSTAT_TXINTF_SHIFT (0) +#define SPI_I2S_INTSTAT_TXINTF_MASK (0x01U << SPI_I2S_INTSTAT_TXINTF_SHIFT) +#define SPI_I2S_INTSTAT_TXINTF(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTSTAT_TXINTF_SHIFT)) & SPI_I2S_INTSTAT_TXINTF_MASK) + +/*! + * @brief SPI_I2S_INTEN Register Bit Definition + */ + +#define SPI_I2S_INTEN_FREIEN_SHIFT (7) +#define SPI_I2S_INTEN_FREIEN_MASK (0x01U << SPI_I2S_INTEN_FREIEN_SHIFT) +#define SPI_I2S_INTEN_FREIEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTEN_FREIEN_SHIFT)) & SPI_I2S_INTEN_FREIEN_MASK) + +#define SPI_I2S_INTEN_TXEPTIEN_SHIFT (6) +#define SPI_I2S_INTEN_TXEPTIEN_MASK (0x01U << SPI_I2S_INTEN_TXEPTIEN_SHIFT) +#define SPI_I2S_INTEN_TXEPTIEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTEN_TXEPTIEN_SHIFT)) & SPI_I2S_INTEN_TXEPTIEN_MASK) + +#define SPI_I2S_INTEN_RXFULLIEN_SHIFT (5) +#define SPI_I2S_INTEN_RXFULLIEN_MASK (0x01U << SPI_I2S_INTEN_RXFULLIEN_SHIFT) +#define SPI_I2S_INTEN_RXFULLIEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTEN_RXFULLIEN_SHIFT)) & SPI_I2S_INTEN_RXFULLIEN_MASK) + +#define SPI_I2S_INTEN_RXMATCHIEN_SHIFT (4) +#define SPI_I2S_INTEN_RXMATCHIEN_MASK (0x01U << SPI_I2S_INTEN_RXMATCHIEN_SHIFT) +#define SPI_I2S_INTEN_RXMATCHIEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTEN_RXMATCHIEN_SHIFT)) & SPI_I2S_INTEN_RXMATCHIEN_MASK) + +#define SPI_I2S_INTEN_RXOERRIEN_SHIFT (3) +#define SPI_I2S_INTEN_RXOERRIEN_MASK (0x01U << SPI_I2S_INTEN_RXOERRIEN_SHIFT) +#define SPI_I2S_INTEN_RXOERRIEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTEN_RXOERRIEN_SHIFT)) & SPI_I2S_INTEN_RXOERRIEN_MASK) + +#define SPI_I2S_INTEN_UNDERRUNIEN_SHIFT (2) +#define SPI_I2S_INTEN_UNDERRUNIEN_MASK (0x01U << SPI_I2S_INTEN_UNDERRUNIEN_SHIFT) +#define SPI_I2S_INTEN_UNDERRUNIEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTEN_UNDERRUNIEN_SHIFT)) & SPI_I2S_INTEN_UNDERRUNIEN_MASK) + +#define SPI_I2S_INTEN_RXIEN_SHIFT (1) +#define SPI_I2S_INTEN_RXIEN_MASK (0x01U << SPI_I2S_INTEN_RXIEN_SHIFT) +#define SPI_I2S_INTEN_RXIEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTEN_RXIEN_SHIFT)) & SPI_I2S_INTEN_RXIEN_MASK) + +#define SPI_I2S_INTEN_TXIEN_SHIFT (0) +#define SPI_I2S_INTEN_TXIEN_MASK (0x01U << SPI_I2S_INTEN_TXIEN_SHIFT) +#define SPI_I2S_INTEN_TXIEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTEN_TXIEN_SHIFT)) & SPI_I2S_INTEN_TXIEN_MASK) + +/*! + * @brief SPI_I2S_INTCLR Register Bit Definition + */ + +#define SPI_I2S_INTCLR_FREICLR_SHIFT (7) +#define SPI_I2S_INTCLR_FREICLR_MASK (0x01U << SPI_I2S_INTCLR_FREICLR_SHIFT) +#define SPI_I2S_INTCLR_FREICLR(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTCLR_FREICLR_SHIFT)) & SPI_I2S_INTCLR_FREICLR_MASK) + +#define SPI_I2S_INTCLR_TXEPTICLR_SHIFT (6) +#define SPI_I2S_INTCLR_TXEPTICLR_MASK (0x01U << SPI_I2S_INTCLR_TXEPTICLR_SHIFT) +#define SPI_I2S_INTCLR_TXEPTICLR(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTCLR_TXEPTICLR_SHIFT)) & SPI_I2S_INTCLR_TXEPTICLR_MASK) + +#define SPI_I2S_INTCLR_RXFULLICLR_SHIFT (5) +#define SPI_I2S_INTCLR_RXFULLICLR_MASK (0x01U << SPI_I2S_INTCLR_RXFULLICLR_SHIFT) +#define SPI_I2S_INTCLR_RXFULLICLR(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTCLR_RXFULLICLR_SHIFT)) & SPI_I2S_INTCLR_RXFULLICLR_MASK) + +#define SPI_I2S_INTCLR_RXMATCHICLR_SHIFT (4) +#define SPI_I2S_INTCLR_RXMATCHICLR_MASK (0x01U << SPI_I2S_INTCLR_RXMATCHICLR_SHIFT) +#define SPI_I2S_INTCLR_RXMATCHICLR(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTCLR_RXMATCHICLR_SHIFT)) & SPI_I2S_INTCLR_RXMATCHICLR_MASK) + +#define SPI_I2S_INTCLR_RXOERRICLR_SHIFT (3) +#define SPI_I2S_INTCLR_RXOERRICLR_MASK (0x01U << SPI_I2S_INTCLR_RXOERRICLR_SHIFT) +#define SPI_I2S_INTCLR_RXOERRICLR(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTCLR_RXOERRICLR_SHIFT)) & SPI_I2S_INTCLR_RXOERRICLR_MASK) + +#define SPI_I2S_INTCLR_UNDERRUNICLR_SHIFT (2) +#define SPI_I2S_INTCLR_UNDERRUNICLR_MASK (0x01U << SPI_I2S_INTCLR_UNDERRUNICLR_SHIFT) +#define SPI_I2S_INTCLR_UNDERRUNICLR(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTCLR_UNDERRUNICLR_SHIFT)) & SPI_I2S_INTCLR_UNDERRUNICLR_MASK) + +#define SPI_I2S_INTCLR_RXICLR_SHIFT (1) +#define SPI_I2S_INTCLR_RXICLR_MASK (0x01U << SPI_I2S_INTCLR_RXICLR_SHIFT) +#define SPI_I2S_INTCLR_RXICLR(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTCLR_RXICLR_SHIFT)) & SPI_I2S_INTCLR_RXICLR_MASK) + +#define SPI_I2S_INTCLR_TXICLR_SHIFT (0) +#define SPI_I2S_INTCLR_TXICLR_MASK (0x01U << SPI_I2S_INTCLR_TXICLR_SHIFT) +#define SPI_I2S_INTCLR_TXICLR(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_INTCLR_TXICLR_SHIFT)) & SPI_I2S_INTCLR_TXICLR_MASK) + +/*! + * @brief SPI_I2S_GCTL Register Bit Definition + */ + +#define SPI_I2S_GCTL_PADSEL_SHIFT (13) +#define SPI_I2S_GCTL_PADSEL_MASK (0x1FU << SPI_I2S_GCTL_PADSEL_SHIFT) +#define SPI_I2S_GCTL_PADSEL(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_GCTL_PADSEL_SHIFT)) & SPI_I2S_GCTL_PADSEL_MASK) + +#define SPI_I2S_GCTL_DW832_SHIFT (11) +#define SPI_I2S_GCTL_DW832_MASK (0x01U << SPI_I2S_GCTL_DW832_SHIFT) +#define SPI_I2S_GCTL_DW832(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_GCTL_DW832_SHIFT)) & SPI_I2S_GCTL_DW832_MASK) + +#define SPI_I2S_GCTL_NSS_SHIFT (10) +#define SPI_I2S_GCTL_NSS_MASK (0x01U << SPI_I2S_GCTL_NSS_SHIFT) +#define SPI_I2S_GCTL_NSS(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_GCTL_NSS_SHIFT)) & SPI_I2S_GCTL_NSS_MASK) + +#define SPI_I2S_GCTL_DMAMODE_SHIFT (9) +#define SPI_I2S_GCTL_DMAMODE_MASK (0x01U << SPI_I2S_GCTL_DMAMODE_SHIFT) +#define SPI_I2S_GCTL_DMAMODE(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_GCTL_DMAMODE_SHIFT)) & SPI_I2S_GCTL_DMAMODE_MASK) + +#define SPI_I2S_GCTL_RXEN_SHIFT (4) +#define SPI_I2S_GCTL_RXEN_MASK (0x01U << SPI_I2S_GCTL_RXEN_SHIFT) +#define SPI_I2S_GCTL_RXEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_GCTL_RXEN_SHIFT)) & SPI_I2S_GCTL_RXEN_MASK) + +#define SPI_I2S_GCTL_TXEN_SHIFT (3) +#define SPI_I2S_GCTL_TXEN_MASK (0x01U << SPI_I2S_GCTL_TXEN_SHIFT) +#define SPI_I2S_GCTL_TXEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_GCTL_TXEN_SHIFT)) & SPI_I2S_GCTL_TXEN_MASK) + +#define SPI_I2S_GCTL_MODE_SHIFT (2) +#define SPI_I2S_GCTL_MODE_MASK (0x01U << SPI_I2S_GCTL_MODE_SHIFT) +#define SPI_I2S_GCTL_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_GCTL_MODE_SHIFT)) & SPI_I2S_GCTL_MODE_MASK) + +#define SPI_I2S_GCTL_INTEN_SHIFT (1) +#define SPI_I2S_GCTL_INTEN_MASK (0x01U << SPI_I2S_GCTL_INTEN_SHIFT) +#define SPI_I2S_GCTL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_GCTL_INTEN_SHIFT)) & SPI_I2S_GCTL_INTEN_MASK) + +#define SPI_I2S_GCTL_SPIEN_SHIFT (0) +#define SPI_I2S_GCTL_SPIEN_MASK (0x01U << SPI_I2S_GCTL_SPIEN_SHIFT) +#define SPI_I2S_GCTL_SPIEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_GCTL_SPIEN_SHIFT)) & SPI_I2S_GCTL_SPIEN_MASK) + +/*! + * @brief SPI_I2S_CCTL Register Bit Definition + */ + +#define SPI_I2S_CCTL_MRDECHG_SHIFT (8) +#define SPI_I2S_CCTL_MRDECHG_MASK (0x7U << SPI_I2S_CCTL_MRDECHG_SHIFT) +#define SPI_I2S_CCTL_MRDECHG(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_CCTL_MRDECHG_SHIFT)) & SPI_I2S_CCTL_MRDECHG_MASK) + +#define SPI_I2S_CCTL_TISEL_SHIFT (7) +#define SPI_I2S_CCTL_TISEL_MASK (0x01U << SPI_I2S_CCTL_TISEL_SHIFT) +#define SPI_I2S_CCTL_TISEL(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_CCTL_TISEL_SHIFT)) & SPI_I2S_CCTL_TISEL_MASK) + +#define SPI_I2S_CCTL_CPHASEL_SHIFT (6) +#define SPI_I2S_CCTL_CPHASEL_MASK (0x01U << SPI_I2S_CCTL_CPHASEL_SHIFT) +#define SPI_I2S_CCTL_CPHASEL(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_CCTL_CPHASEL_SHIFT)) & SPI_I2S_CCTL_CPHASEL_MASK) + +#define SPI_I2S_CCTL_TXEDGE_SHIFT (5) +#define SPI_I2S_CCTL_TXEDGE_MASK (0x01U << SPI_I2S_CCTL_TXEDGE_SHIFT) +#define SPI_I2S_CCTL_TXEDGE(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_CCTL_TXEDGE_SHIFT)) & SPI_I2S_CCTL_TXEDGE_MASK) + +#define SPI_I2S_CCTL_RXEDGE_SHIFT (4) +#define SPI_I2S_CCTL_RXEDGE_MASK (0x01U << SPI_I2S_CCTL_RXEDGE_SHIFT) +#define SPI_I2S_CCTL_RXEDGE(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_CCTL_RXEDGE_SHIFT)) & SPI_I2S_CCTL_RXEDGE_MASK) + +#define SPI_I2S_CCTL_SPILEN_SHIFT (3) +#define SPI_I2S_CCTL_SPILEN_MASK (0x01U << SPI_I2S_CCTL_SPILEN_SHIFT) +#define SPI_I2S_CCTL_SPILEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_CCTL_SPILEN_SHIFT)) & SPI_I2S_CCTL_SPILEN_MASK) + +#define SPI_I2S_CCTL_LSBFE_SHIFT (2) +#define SPI_I2S_CCTL_LSBFE_MASK (0x01U << SPI_I2S_CCTL_LSBFE_SHIFT) +#define SPI_I2S_CCTL_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_CCTL_LSBFE_SHIFT)) & SPI_I2S_CCTL_LSBFE_MASK) + +#define SPI_I2S_CCTL_CPOL_SHIFT (1) +#define SPI_I2S_CCTL_CPOL_MASK (0x01U << SPI_I2S_CCTL_CPOL_SHIFT) +#define SPI_I2S_CCTL_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_CCTL_CPOL_SHIFT)) & SPI_I2S_CCTL_CPOL_MASK) + +#define SPI_I2S_CCTL_CPHA_SHIFT (0) +#define SPI_I2S_CCTL_CPHA_MASK (0x01U << SPI_I2S_CCTL_CPHA_SHIFT) +#define SPI_I2S_CCTL_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_CCTL_CPHA_SHIFT)) & SPI_I2S_CCTL_CPHA_MASK) + +/*! + * @brief SPI_I2S_SPBRG Register Bit Definition + */ + +#define SPI_I2S_SPBRG_SPBRG_SHIFT (0) +#define SPI_I2S_SPBRG_SPBRG_MASK (0xFFFFU << SPI_I2S_SPBRG_SPBRG_SHIFT) +#define SPI_I2S_SPBRG_SPBRG(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_SPBRG_SPBRG_SHIFT)) & SPI_I2S_SPBRG_SPBRG_MASK) + +/*! + * @brief SPI_I2S_RXDNR Register Bit Definition + */ + +#define SPI_I2S_RXDNR_RXDNR_SHIFT (0) +#define SPI_I2S_RXDNR_RXDNR_MASK (0xFFFFU << SPI_I2S_RXDNR_RXDNR_SHIFT) +#define SPI_I2S_RXDNR_RXDNR(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_RXDNR_RXDNR_SHIFT)) & SPI_I2S_RXDNR_RXDNR_MASK) + +/*! + * @brief SPI_I2S_NSSR Register Bit Definition + */ + +#define SPI_I2S_NSSR_NSS_SHIFT (0) +#define SPI_I2S_NSSR_NSS_MASK (0x01U << SPI_I2S_NSSR_NSS_SHIFT) +#define SPI_I2S_NSSR_NSS(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_NSSR_NSS_SHIFT)) & SPI_I2S_NSSR_NSS_MASK) + +/*! + * @brief SPI_I2S_EXTCTL Register Bit Definition + */ + +#define SPI_I2S_EXTCTL_EXTLEN_SHIFT (0) +#define SPI_I2S_EXTCTL_EXTLEN_MASK (0x1FU << SPI_I2S_EXTCTL_EXTLEN_SHIFT) +#define SPI_I2S_EXTCTL_EXTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_EXTCTL_EXTLEN_SHIFT)) & SPI_I2S_EXTCTL_EXTLEN_MASK) + +/*! + * @brief SPI_I2S_I2SCFGR Register Bit Definition + */ + +#define SPI_I2S_I2SCFGR_I2SDIV_SHIFT (16) +#define SPI_I2S_I2SCFGR_I2SDIV_MASK (0x1FFU << SPI_I2S_I2SCFGR_I2SDIV_SHIFT) +#define SPI_I2S_I2SCFGR_I2SDIV(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_I2SCFGR_I2SDIV_SHIFT)) & SPI_I2S_I2SCFGR_I2SDIV_MASK) + +#define SPI_I2S_I2SCFGR_HFDSEL_SHIFT (13) +#define SPI_I2S_I2SCFGR_HFDSEL_MASK (0x01U << SPI_I2S_I2SCFGR_HFDSEL_SHIFT) +#define SPI_I2S_I2SCFGR_HFDSEL(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_I2SCFGR_HFDSEL_SHIFT)) & SPI_I2S_I2SCFGR_HFDSEL_MASK) + +#define SPI_I2S_I2SCFGR_MCKSEL_SHIFT (12) +#define SPI_I2S_I2SCFGR_MCKSEL_MASK (0x01U << SPI_I2S_I2SCFGR_MCKSEL_SHIFT) +#define SPI_I2S_I2SCFGR_MCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_I2SCFGR_MCKSEL_SHIFT)) & SPI_I2S_I2SCFGR_MCKSEL_MASK) + +#define SPI_I2S_I2SCFGR_MCKOE_SHIFT (11) +#define SPI_I2S_I2SCFGR_MCKOE_MASK (0x01U << SPI_I2S_I2SCFGR_MCKOE_SHIFT) +#define SPI_I2S_I2SCFGR_MCKOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_I2SCFGR_MCKOE_SHIFT)) & SPI_I2S_I2SCFGR_MCKOE_MASK) + +#define SPI_I2S_I2SCFGR_SPII2S_SHIFT (10) +#define SPI_I2S_I2SCFGR_SPII2S_MASK (0x01U << SPI_I2S_I2SCFGR_SPII2S_SHIFT) +#define SPI_I2S_I2SCFGR_SPII2S(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_I2SCFGR_SPII2S_SHIFT)) & SPI_I2S_I2SCFGR_SPII2S_MASK) + +#define SPI_I2S_I2SCFGR_PCMSYNC_SHIFT (6) +#define SPI_I2S_I2SCFGR_PCMSYNC_MASK (0x01U << SPI_I2S_I2SCFGR_PCMSYNC_SHIFT) +#define SPI_I2S_I2SCFGR_PCMSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_I2SCFGR_PCMSYNC_SHIFT)) & SPI_I2S_I2SCFGR_PCMSYNC_MASK) + +#define SPI_I2S_I2SCFGR_I2SSTD_SHIFT (4) +#define SPI_I2S_I2SCFGR_I2SSTD_MASK (0x3U << SPI_I2S_I2SCFGR_I2SSTD_SHIFT) +#define SPI_I2S_I2SCFGR_I2SSTD(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_I2SCFGR_I2SSTD_SHIFT)) & SPI_I2S_I2SCFGR_I2SSTD_MASK) + +#define SPI_I2S_I2SCFGR_DATLEN_SHIFT (1) +#define SPI_I2S_I2SCFGR_DATLEN_MASK (0x3U << SPI_I2S_I2SCFGR_DATLEN_SHIFT) +#define SPI_I2S_I2SCFGR_DATLEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_I2SCFGR_DATLEN_SHIFT)) & SPI_I2S_I2SCFGR_DATLEN_MASK) + +#define SPI_I2S_I2SCFGR_CHLEN_SHIFT (0) +#define SPI_I2S_I2SCFGR_CHLEN_MASK (0x01U << SPI_I2S_I2SCFGR_CHLEN_SHIFT) +#define SPI_I2S_I2SCFGR_CHLEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_I2S_I2SCFGR_CHLEN_SHIFT)) & SPI_I2S_I2SCFGR_CHLEN_MASK) + +/*! + * @} + */ /* end of group SPI_Register_Masks */ +/****************************************************************************** + *SPI Instance +*******************************************************************************/ + +#define SPI1 ((SPI_Type*)SPI1_BASE) +#define SPI2 ((SPI_Type*)SPI2_BASE) +#define SPI3 ((SPI_Type*)SPI3_BASE) + +/*! + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + +/*! + * @addtogroup SYSCFG_Peripheral_Access_Layer SYSCFG Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * SYSCFG Type + ******************************************************************************/ +typedef struct { + __IO uint32_t CFGR; ///< SYSCFG Configuration Register offset: 0x00 + __IO uint32_t Reserved49[1]; ///< Reserved + __IO uint32_t EXTICR1; ///< External Interrupt Configuration Register 1 offset: 0x08 + __IO uint32_t EXTICR2; ///< External Interrupt Configuration Register 2 offset: 0x0C + __IO uint32_t EXTICR3; ///< External Interrupt Configuration Register 3 offset: 0x10 + __IO uint32_t EXTICR4; ///< External Interrupt Configuration Register 4 offset: 0x14 + __IO uint32_t CFGR2; ///< SYSCFG Configuration Register 2 offset: 0x18 + __IO uint32_t PDETCSR; ///< Power Detect Configuration Status Register offset: 0x1C + __IO uint32_t VOSDLY; ///< VOSDLY configuration register offset: 0x20 + __IO uint32_t DMARMP; ///< DAM remap register offset: 0x24 + __IO uint32_t BUSPRIORITY; ///< Bus Priority Configuration Register offset: 0x28 +} SYSCFG_Type; + +/******************************************************************************* + * SYSCFG Type + ******************************************************************************/ + +/*! + * @addtogroup SYSCFG_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief SYSCFG_CFGR Register Bit Definition + */ + +#define SYSCFG_CFGR_FCMODESEL_SHIFT (29) +#define SYSCFG_CFGR_FCMODESEL_MASK (0x3U << SYSCFG_CFGR_FCMODESEL_SHIFT) +#define SYSCFG_CFGR_FCMODESEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_CFGR_FCMODESEL_SHIFT)) & SYSCFG_CFGR_FCMODESEL_MASK) + +#define SYSCFG_CFGR_FCODATAEN_SHIFT (28) +#define SYSCFG_CFGR_FCODATAEN_MASK (0x01U << SYSCFG_CFGR_FCODATAEN_SHIFT) +#define SYSCFG_CFGR_FCODATAEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_CFGR_FCODATAEN_SHIFT)) & SYSCFG_CFGR_FCODATAEN_MASK) + +#define SYSCFG_CFGR_CAN2STOP_SHIFT (21) +#define SYSCFG_CFGR_CAN2STOP_MASK (0x01U << SYSCFG_CFGR_CAN2STOP_SHIFT) +#define SYSCFG_CFGR_CAN2STOP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_CFGR_CAN2STOP_SHIFT)) & SYSCFG_CFGR_CAN2STOP_MASK) + +#define SYSCFG_CFGR_CAN2TEST_SHIFT (20) +#define SYSCFG_CFGR_CAN2TEST_MASK (0x01U << SYSCFG_CFGR_CAN2TEST_SHIFT) +#define SYSCFG_CFGR_CAN2TEST(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_CFGR_CAN2TEST_SHIFT)) & SYSCFG_CFGR_CAN2TEST_MASK) + +#define SYSCFG_CFGR_CAN2SPV_SHIFT (19) +#define SYSCFG_CFGR_CAN2SPV_MASK (0x01U << SYSCFG_CFGR_CAN2SPV_SHIFT) +#define SYSCFG_CFGR_CAN2SPV(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_CFGR_CAN2SPV_SHIFT)) & SYSCFG_CFGR_CAN2SPV_MASK) + +#define SYSCFG_CFGR_CAN1STOP_SHIFT (18) +#define SYSCFG_CFGR_CAN1STOP_MASK (0x01U << SYSCFG_CFGR_CAN1STOP_SHIFT) +#define SYSCFG_CFGR_CAN1STOP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_CFGR_CAN1STOP_SHIFT)) & SYSCFG_CFGR_CAN1STOP_MASK) + +#define SYSCFG_CFGR_CAN1TEST_SHIFT (17) +#define SYSCFG_CFGR_CAN1TEST_MASK (0x01U << SYSCFG_CFGR_CAN1TEST_SHIFT) +#define SYSCFG_CFGR_CAN1TEST(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_CFGR_CAN1TEST_SHIFT)) & SYSCFG_CFGR_CAN1TEST_MASK) + +#define SYSCFG_CFGR_CAN1SPV_SHIFT (16) +#define SYSCFG_CFGR_CAN1SPV_MASK (0x01U << SYSCFG_CFGR_CAN1SPV_SHIFT) +#define SYSCFG_CFGR_CAN1SPV(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_CFGR_CAN1SPV_SHIFT)) & SYSCFG_CFGR_CAN1SPV_MASK) + +#define SYSCFG_CFGR_USBFSIDORV_SHIFT (3) +#define SYSCFG_CFGR_USBFSIDORV_MASK (0x01U << SYSCFG_CFGR_USBFSIDORV_SHIFT) +#define SYSCFG_CFGR_USBFSIDORV(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_CFGR_USBFSIDORV_SHIFT)) & SYSCFG_CFGR_USBFSIDORV_MASK) + +#define SYSCFG_CFGR_USBFSVBUSORV_SHIFT (2) +#define SYSCFG_CFGR_USBFSVBUSORV_MASK (0x01U << SYSCFG_CFGR_USBFSVBUSORV_SHIFT) +#define SYSCFG_CFGR_USBFSVBUSORV(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_CFGR_USBFSVBUSORV_SHIFT)) & SYSCFG_CFGR_USBFSVBUSORV_MASK) + +#define SYSCFG_CFGR_USBFSIDOWDIS_SHIFT (1) +#define SYSCFG_CFGR_USBFSIDOWDIS_MASK (0x01U << SYSCFG_CFGR_USBFSIDOWDIS_SHIFT) +#define SYSCFG_CFGR_USBFSIDOWDIS(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_CFGR_USBFSIDOWDIS_SHIFT)) & SYSCFG_CFGR_USBFSIDOWDIS_MASK) + +#define SYSCFG_CFGR_USBFSVBUSOWDIS_SHIFT (0) +#define SYSCFG_CFGR_USBFSVBUSOWDIS_MASK (0x01U << SYSCFG_CFGR_USBFSVBUSOWDIS_SHIFT) +#define SYSCFG_CFGR_USBFSVBUSOWDIS(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_CFGR_USBFSVBUSOWDIS_SHIFT)) & SYSCFG_CFGR_USBFSVBUSOWDIS_MASK) + +/*! + * @brief SYSCFG_EXTICR1 Register Bit Definition + */ + +#define SYSCFG_EXTICR1_EXTIX_SHIFT (0) +#define SYSCFG_EXTICR1_EXTIX_MASK (0xFFFFU << SYSCFG_EXTICR1_EXTIX_SHIFT) +#define SYSCFG_EXTICR1_EXTIX(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_EXTICR1_EXTIX_SHIFT)) & SYSCFG_EXTICR1_EXTIX_MASK) + +/*! + * @brief SYSCFG_EXTICR2 Register Bit Definition + */ + +#define SYSCFG_EXTICR2_EXTIX_SHIFT (0) +#define SYSCFG_EXTICR2_EXTIX_MASK (0xFFFFU << SYSCFG_EXTICR2_EXTIX_SHIFT) +#define SYSCFG_EXTICR2_EXTIX(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_EXTICR2_EXTIX_SHIFT)) & SYSCFG_EXTICR2_EXTIX_MASK) + +/*! + * @brief SYSCFG_EXTICR3 Register Bit Definition + */ + +#define SYSCFG_EXTICR3_EXTIX_SHIFT (0) +#define SYSCFG_EXTICR3_EXTIX_MASK (0xFFFFU << SYSCFG_EXTICR3_EXTIX_SHIFT) +#define SYSCFG_EXTICR3_EXTIX(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_EXTICR3_EXTIX_SHIFT)) & SYSCFG_EXTICR3_EXTIX_MASK) + +/*! + * @brief SYSCFG_EXTICR4 Register Bit Definition + */ + +#define SYSCFG_EXTICR4_EXTIX_SHIFT (0) +#define SYSCFG_EXTICR4_EXTIX_MASK (0xFFFFU << SYSCFG_EXTICR4_EXTIX_SHIFT) +#define SYSCFG_EXTICR4_EXTIX(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_EXTICR4_EXTIX_SHIFT)) & SYSCFG_EXTICR4_EXTIX_MASK) + +/*! + * @brief SYSCFG_CFGR2 Register Bit Definition + */ + +#define SYSCFG_CFGR2_QSPIAUTOIDLEEN_SHIFT (25) +#define SYSCFG_CFGR2_QSPIAUTOIDLEEN_MASK (0x01U << SYSCFG_CFGR2_QSPIAUTOIDLEEN_SHIFT) +#define SYSCFG_CFGR2_QSPIAUTOIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_CFGR2_QSPIAUTOIDLEEN_SHIFT)) & SYSCFG_CFGR2_QSPIAUTOIDLEEN_MASK) + +#define SYSCFG_CFGR2_ENETSPDSEL_SHIFT (21) +#define SYSCFG_CFGR2_ENETSPDSEL_MASK (0x01U << SYSCFG_CFGR2_ENETSPDSEL_SHIFT) +#define SYSCFG_CFGR2_ENETSPDSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_CFGR2_ENETSPDSEL_SHIFT)) & SYSCFG_CFGR2_ENETSPDSEL_MASK) + +#define SYSCFG_CFGR2_ENETMIIRMIISEL_SHIFT (20) +#define SYSCFG_CFGR2_ENETMIIRMIISEL_MASK (0x01U << SYSCFG_CFGR2_ENETMIIRMIISEL_SHIFT) +#define SYSCFG_CFGR2_ENETMIIRMIISEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_CFGR2_ENETMIIRMIISEL_SHIFT)) & SYSCFG_CFGR2_ENETMIIRMIISEL_MASK) + +#define SYSCFG_CFGR2_I2C2MODESEL_SHIFT (17) +#define SYSCFG_CFGR2_I2C2MODESEL_MASK (0x01U << SYSCFG_CFGR2_I2C2MODESEL_SHIFT) +#define SYSCFG_CFGR2_I2C2MODESEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_CFGR2_I2C2MODESEL_SHIFT)) & SYSCFG_CFGR2_I2C2MODESEL_MASK) + +#define SYSCFG_CFGR2_I2C1MODESEL_SHIFT (16) +#define SYSCFG_CFGR2_I2C1MODESEL_MASK (0x01U << SYSCFG_CFGR2_I2C1MODESEL_SHIFT) +#define SYSCFG_CFGR2_I2C1MODESEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_CFGR2_I2C1MODESEL_SHIFT)) & SYSCFG_CFGR2_I2C1MODESEL_MASK) + +/*! + * @brief SYSCFG_PDETCSR Register Bit Definition + */ + +#define SYSCFG_PDETCSR_VBATDIV3EN_SHIFT (11) +#define SYSCFG_PDETCSR_VBATDIV3EN_MASK (0x01U << SYSCFG_PDETCSR_VBATDIV3EN_SHIFT) +#define SYSCFG_PDETCSR_VBATDIV3EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_PDETCSR_VBATDIV3EN_SHIFT)) & SYSCFG_PDETCSR_VBATDIV3EN_MASK) + +#define SYSCFG_PDETCSR_VDTLS_SHIFT (9) +#define SYSCFG_PDETCSR_VDTLS_MASK (0x3U << SYSCFG_PDETCSR_VDTLS_SHIFT) +#define SYSCFG_PDETCSR_VDTLS(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_PDETCSR_VDTLS_SHIFT)) & SYSCFG_PDETCSR_VDTLS_MASK) + +#define SYSCFG_PDETCSR_VDTE_SHIFT (8) +#define SYSCFG_PDETCSR_VDTE_MASK (0x01U << SYSCFG_PDETCSR_VDTE_SHIFT) +#define SYSCFG_PDETCSR_VDTE(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_PDETCSR_VDTE_SHIFT)) & SYSCFG_PDETCSR_VDTE_MASK) + +#define SYSCFG_PDETCSR_VDTO_SHIFT (6) +#define SYSCFG_PDETCSR_VDTO_MASK (0x01U << SYSCFG_PDETCSR_VDTO_SHIFT) +#define SYSCFG_PDETCSR_VDTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_PDETCSR_VDTO_SHIFT)) & SYSCFG_PDETCSR_VDTO_MASK) + +#define SYSCFG_PDETCSR_PVDO_SHIFT (5) +#define SYSCFG_PDETCSR_PVDO_MASK (0x01U << SYSCFG_PDETCSR_PVDO_SHIFT) +#define SYSCFG_PDETCSR_PVDO(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_PDETCSR_PVDO_SHIFT)) & SYSCFG_PDETCSR_PVDO_MASK) + +#define SYSCFG_PDETCSR_PLS_SHIFT (1) +#define SYSCFG_PDETCSR_PLS_MASK (0xFU << SYSCFG_PDETCSR_PLS_SHIFT) +#define SYSCFG_PDETCSR_PLS(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_PDETCSR_PLS_SHIFT)) & SYSCFG_PDETCSR_PLS_MASK) + +#define SYSCFG_PDETCSR_PVDE_SHIFT (0) +#define SYSCFG_PDETCSR_PVDE_MASK (0x01U << SYSCFG_PDETCSR_PVDE_SHIFT) +#define SYSCFG_PDETCSR_PVDE(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_PDETCSR_PVDE_SHIFT)) & SYSCFG_PDETCSR_PVDE_MASK) + +/*! + * @brief SYSCFG_VOSDLY Register Bit Definition + */ + +#define SYSCFG_VOSDLY_VOSDLYCNT_SHIFT (0) +#define SYSCFG_VOSDLY_VOSDLYCNT_MASK (0x3FFU << SYSCFG_VOSDLY_VOSDLYCNT_SHIFT) +#define SYSCFG_VOSDLY_VOSDLYCNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_VOSDLY_VOSDLYCNT_SHIFT)) & SYSCFG_VOSDLY_VOSDLYCNT_MASK) + +/*! + * @brief SYSCFG_DMARMP Register Bit Definition + */ + +#define SYSCFG_DMARMP_DACCH2RMP_SHIFT (29) +#define SYSCFG_DMARMP_DACCH2RMP_MASK (0x01U << SYSCFG_DMARMP_DACCH2RMP_SHIFT) +#define SYSCFG_DMARMP_DACCH2RMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_DACCH2RMP_SHIFT)) & SYSCFG_DMARMP_DACCH2RMP_MASK) + +#define SYSCFG_DMARMP_DACCH1RMP_SHIFT (28) +#define SYSCFG_DMARMP_DACCH1RMP_MASK (0x01U << SYSCFG_DMARMP_DACCH1RMP_SHIFT) +#define SYSCFG_DMARMP_DACCH1RMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_DACCH1RMP_SHIFT)) & SYSCFG_DMARMP_DACCH1RMP_MASK) + +#define SYSCFG_DMARMP_UART7TXRMP_SHIFT (23) +#define SYSCFG_DMARMP_UART7TXRMP_MASK (0x01U << SYSCFG_DMARMP_UART7TXRMP_SHIFT) +#define SYSCFG_DMARMP_UART7TXRMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_UART7TXRMP_SHIFT)) & SYSCFG_DMARMP_UART7TXRMP_MASK) + +#define SYSCFG_DMARMP_UART7RXTMP_SHIFT (22) +#define SYSCFG_DMARMP_UART7RXTMP_MASK (0x01U << SYSCFG_DMARMP_UART7RXTMP_SHIFT) +#define SYSCFG_DMARMP_UART7RXTMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_UART7RXTMP_SHIFT)) & SYSCFG_DMARMP_UART7RXTMP_MASK) + +#define SYSCFG_DMARMP_UART6TXRMP_SHIFT (21) +#define SYSCFG_DMARMP_UART6TXRMP_MASK (0x01U << SYSCFG_DMARMP_UART6TXRMP_SHIFT) +#define SYSCFG_DMARMP_UART6TXRMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_UART6TXRMP_SHIFT)) & SYSCFG_DMARMP_UART6TXRMP_MASK) + +#define SYSCFG_DMARMP_UART6RXRMP_SHIFT (20) +#define SYSCFG_DMARMP_UART6RXRMP_MASK (0x01U << SYSCFG_DMARMP_UART6RXRMP_SHIFT) +#define SYSCFG_DMARMP_UART6RXRMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_UART6RXRMP_SHIFT)) & SYSCFG_DMARMP_UART6RXRMP_MASK) + +#define SYSCFG_DMARMP_UART4TXRMP_SHIFT (17) +#define SYSCFG_DMARMP_UART4TXRMP_MASK (0x01U << SYSCFG_DMARMP_UART4TXRMP_SHIFT) +#define SYSCFG_DMARMP_UART4TXRMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_UART4TXRMP_SHIFT)) & SYSCFG_DMARMP_UART4TXRMP_MASK) + +#define SYSCFG_DMARMP_UART4RXRMP_SHIFT (16) +#define SYSCFG_DMARMP_UART4RXRMP_MASK (0x01U << SYSCFG_DMARMP_UART4RXRMP_SHIFT) +#define SYSCFG_DMARMP_UART4RXRMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_UART4RXRMP_SHIFT)) & SYSCFG_DMARMP_UART4RXRMP_MASK) + +#define SYSCFG_DMARMP_TIM8COMRMP_SHIFT (15) +#define SYSCFG_DMARMP_TIM8COMRMP_MASK (0x01U << SYSCFG_DMARMP_TIM8COMRMP_SHIFT) +#define SYSCFG_DMARMP_TIM8COMRMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_TIM8COMRMP_SHIFT)) & SYSCFG_DMARMP_TIM8COMRMP_MASK) + +#define SYSCFG_DMARMP_TIM8UPRMP_SHIFT (14) +#define SYSCFG_DMARMP_TIM8UPRMP_MASK (0x01U << SYSCFG_DMARMP_TIM8UPRMP_SHIFT) +#define SYSCFG_DMARMP_TIM8UPRMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_TIM8UPRMP_SHIFT)) & SYSCFG_DMARMP_TIM8UPRMP_MASK) + +#define SYSCFG_DMARMP_TIM8TRIGRMP_SHIFT (13) +#define SYSCFG_DMARMP_TIM8TRIGRMP_MASK (0x01U << SYSCFG_DMARMP_TIM8TRIGRMP_SHIFT) +#define SYSCFG_DMARMP_TIM8TRIGRMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_TIM8TRIGRMP_SHIFT)) & SYSCFG_DMARMP_TIM8TRIGRMP_MASK) + +#define SYSCFG_DMARMP_TIM7UPRMP_SHIFT (12) +#define SYSCFG_DMARMP_TIM7UPRMP_MASK (0x01U << SYSCFG_DMARMP_TIM7UPRMP_SHIFT) +#define SYSCFG_DMARMP_TIM7UPRMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_TIM7UPRMP_SHIFT)) & SYSCFG_DMARMP_TIM7UPRMP_MASK) + +#define SYSCFG_DMARMP_TIM6UPRMP_SHIFT (10) +#define SYSCFG_DMARMP_TIM6UPRMP_MASK (0x01U << SYSCFG_DMARMP_TIM6UPRMP_SHIFT) +#define SYSCFG_DMARMP_TIM6UPRMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_TIM6UPRMP_SHIFT)) & SYSCFG_DMARMP_TIM6UPRMP_MASK) + +#define SYSCFG_DMARMP_TIM5UPRMP_SHIFT (8) +#define SYSCFG_DMARMP_TIM5UPRMP_MASK (0x01U << SYSCFG_DMARMP_TIM5UPRMP_SHIFT) +#define SYSCFG_DMARMP_TIM5UPRMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_TIM5UPRMP_SHIFT)) & SYSCFG_DMARMP_TIM5UPRMP_MASK) + +#define SYSCFG_DMARMP_TIM2CC4RMP_SHIFT (5) +#define SYSCFG_DMARMP_TIM2CC4RMP_MASK (0x01U << SYSCFG_DMARMP_TIM2CC4RMP_SHIFT) +#define SYSCFG_DMARMP_TIM2CC4RMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_TIM2CC4RMP_SHIFT)) & SYSCFG_DMARMP_TIM2CC4RMP_MASK) + +#define SYSCFG_DMARMP_TIM2CC3RMP_SHIFT (4) +#define SYSCFG_DMARMP_TIM2CC3RMP_MASK (0x01U << SYSCFG_DMARMP_TIM2CC3RMP_SHIFT) +#define SYSCFG_DMARMP_TIM2CC3RMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_TIM2CC3RMP_SHIFT)) & SYSCFG_DMARMP_TIM2CC3RMP_MASK) + +#define SYSCFG_DMARMP_TIM2UPRMP_SHIFT (2) +#define SYSCFG_DMARMP_TIM2UPRMP_MASK (0x3U << SYSCFG_DMARMP_TIM2UPRMP_SHIFT) +#define SYSCFG_DMARMP_TIM2UPRMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_TIM2UPRMP_SHIFT)) & SYSCFG_DMARMP_TIM2UPRMP_MASK) + +#define SYSCFG_DMARMP_TIM1COMRMP_SHIFT (1) +#define SYSCFG_DMARMP_TIM1COMRMP_MASK (0x01U << SYSCFG_DMARMP_TIM1COMRMP_SHIFT) +#define SYSCFG_DMARMP_TIM1COMRMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_TIM1COMRMP_SHIFT)) & SYSCFG_DMARMP_TIM1COMRMP_MASK) + +#define SYSCFG_DMARMP_TIM1TRIGRMP_SHIFT (0) +#define SYSCFG_DMARMP_TIM1TRIGRMP_MASK (0x01U << SYSCFG_DMARMP_TIM1TRIGRMP_SHIFT) +#define SYSCFG_DMARMP_TIM1TRIGRMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_DMARMP_TIM1TRIGRMP_SHIFT)) & SYSCFG_DMARMP_TIM1TRIGRMP_MASK) + +/*! + * @brief SYSCFG_BUS_PRIORITY Register Bit Definition + */ + +#define SYSCFG_BUSPRI_PRIM6_SHIFT (15) +#define SYSCFG_BUSPRI_PRIM6_MASK (0x7U << SYSCFG_BUSPRI_PRIM6_SHIFT) +#define SYSCFG_BUSPRI_PRIM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_BUSPRI_PRIM6_SHIFT)) & SYSCFG_BUSPRI_PRIM6_MASK) + +#define SYSCFG_BUSPRI_PRIM5_SHIFT (12) +#define SYSCFG_BUSPRI_PRIM5_MASK (0x7U << SYSCFG_BUSPRI_PRIM5_SHIFT) +#define SYSCFG_BUSPRI_PRIM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_BUSPRI_PRIM5_SHIFT)) & SYSCFG_BUSPRI_PRIM5_MASK) + +#define SYSCFG_BUSPRI_PRIM4_SHIFT (9) +#define SYSCFG_BUSPRI_PRIM4_MASK (0x7U << SYSCFG_BUSPRI_PRIM4_SHIFT) +#define SYSCFG_BUSPRI_PRIM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_BUSPRI_PRIM4_SHIFT)) & SYSCFG_BUSPRI_PRIM4_MASK) + +#define SYSCFG_BUSPRI_PRIM3_SHIFT (6) +#define SYSCFG_BUSPRI_PRIM3_MASK (0x7U << SYSCFG_BUSPRI_PRIM3_SHIFT) +#define SYSCFG_BUSPRI_PRIM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_BUSPRI_PRIM3_SHIFT)) & SYSCFG_BUSPRI_PRIM3_MASK) + +#define SYSCFG_BUSPRI_PRIM2_SHIFT (3) +#define SYSCFG_BUSPRI_PRIM2_MASK (0x7U << SYSCFG_BUSPRI_PRIM2_SHIFT) +#define SYSCFG_BUSPRI_PRIM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_BUSPRI_PRIM2_SHIFT)) & SYSCFG_BUSPRI_PRIM2_MASK) + +#define SYSCFG_BUSPRI_PRIM1_SHIFT (0) +#define SYSCFG_BUSPRI_PRIM1_MASK (0x7U << SYSCFG_BUSPRI_PRIM1_SHIFT) +#define SYSCFG_BUSPRI_PRIM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCFG_BUSPRI_PRIM1_SHIFT)) & SYSCFG_BUSPRI_PRIM1_MASK) + +/*! + * @} + */ /* end of group SYSCFG_Register_Masks */ +/****************************************************************************** + *SYSCFG Instance +*******************************************************************************/ + +#define SYSCFG ((SYSCFG_Type*)SYSCFG_BASE) + +/*! + * @} + */ /* end of group SYSCFG_Peripheral_Access_Layer */ + + + + +/*! + * @addtogroup TIM1_Peripheral_Access_Layer TIM1 Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * TIM1 Type + ******************************************************************************/ +typedef struct { + __IO uint32_t CR1; ///< Control Register 1 offset: 0x00 + __IO uint32_t CR2; ///< Control Register 2 offset: 0x04 + __IO uint32_t SMCR; ///< Slave Mode Control Register offset: 0x08 + __IO uint32_t DIER; ///< DMA/Interrupt Enable Register offset: 0x0C + __IO uint32_t SR; ///< status register offset: 0x10 + __IO uint32_t EGR; ///< event generation register offset: 0x14 + __IO uint32_t CCMR1; ///< Capture/Compare Mode Register 1 offset: 0x18 + __IO uint32_t CCMR2; ///< Capture/Compare Mode Register 2 offset: 0x1C + __IO uint32_t CCER; ///< Capture/Compare Enable Register offset: 0x20 + __IO uint32_t CNT; ///< counter offset: 0x24 + __IO uint32_t PSC; ///< Prescaler offset: 0x28 + __IO uint32_t ARR; ///< autoload register offset: 0x2C + __IO uint32_t RCR; ///< Repeat count register offset: 0x30 + __IO uint32_t CCR[4]; ///< Capture/Compare Register 1 offset: 0x34 + __IO uint32_t BDTR; ///< Brake and Deadband Registers offset: 0x44 + __IO uint32_t DCR; ///< DMA Control Register offset: 0x48 + __IO uint32_t DMAR; ///< DMA address for continuous mode offset: 0x4C + __IO uint32_t Reserved0[1]; ///< Reserved + __IO uint32_t CCMR3; ///< Capture/Compare Mode Register 3 offset: 0x54 + __IO uint32_t CCR5; ///< Capture/Compare Register 5 offset: 0x58 + __IO uint32_t PDER; ///< PWM phase shift/DMA repeat update request enable registeroffset: 0x5C + __IO uint32_t CCRFALL[5]; ///< PWM Phase Shift Down Count Capture/Compare Registeroffset: 0x60 + __IO uint32_t BKINF; ///< brake input filter register offset: 0x74 +} TIM1_Type; + +/******************************************************************************* + * TIM1 Type + ******************************************************************************/ + +/*! + * @addtogroup TIM1_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief TIM1_CR1 Register Bit Definition + */ + +#define TIM1_CR1_CKD_SHIFT (8) +#define TIM1_CR1_CKD_MASK (0x3U << TIM1_CR1_CKD_SHIFT) +#define TIM1_CR1_CKD(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR1_CKD_SHIFT)) & TIM1_CR1_CKD_MASK) + +#define TIM1_CR1_ARPE_SHIFT (7) +#define TIM1_CR1_ARPE_MASK (0x01U << TIM1_CR1_ARPE_SHIFT) +#define TIM1_CR1_ARPE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR1_ARPE_SHIFT)) & TIM1_CR1_ARPE_MASK) + +#define TIM1_CR1_CMS_SHIFT (5) +#define TIM1_CR1_CMS_MASK (0x3U << TIM1_CR1_CMS_SHIFT) +#define TIM1_CR1_CMS(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR1_CMS_SHIFT)) & TIM1_CR1_CMS_MASK) + +#define TIM1_CR1_DIR_SHIFT (4) +#define TIM1_CR1_DIR_MASK (0x01U << TIM1_CR1_DIR_SHIFT) +#define TIM1_CR1_DIR(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR1_DIR_SHIFT)) & TIM1_CR1_DIR_MASK) + +#define TIM1_CR1_OPM_SHIFT (3) +#define TIM1_CR1_OPM_MASK (0x01U << TIM1_CR1_OPM_SHIFT) +#define TIM1_CR1_OPM(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR1_OPM_SHIFT)) & TIM1_CR1_OPM_MASK) + +#define TIM1_CR1_URS_SHIFT (2) +#define TIM1_CR1_URS_MASK (0x01U << TIM1_CR1_URS_SHIFT) +#define TIM1_CR1_URS(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR1_URS_SHIFT)) & TIM1_CR1_URS_MASK) + +#define TIM1_CR1_UDIS_SHIFT (1) +#define TIM1_CR1_UDIS_MASK (0x01U << TIM1_CR1_UDIS_SHIFT) +#define TIM1_CR1_UDIS(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR1_UDIS_SHIFT)) & TIM1_CR1_UDIS_MASK) + +#define TIM1_CR1_CEN_SHIFT (0) +#define TIM1_CR1_CEN_MASK (0x01U << TIM1_CR1_CEN_SHIFT) +#define TIM1_CR1_CEN(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR1_CEN_SHIFT)) & TIM1_CR1_CEN_MASK) + +/*! + * @brief TIM1_CR2 Register Bit Definition + */ + +#define TIM1_CR2_OIS4N_SHIFT (15) +#define TIM1_CR2_OIS4N_MASK (0x01U << TIM1_CR2_OIS4N_SHIFT) +#define TIM1_CR2_OIS4N(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR2_OIS4N_SHIFT)) & TIM1_CR2_OIS4N_MASK) + +#define TIM1_CR2_OIS4_SHIFT (14) +#define TIM1_CR2_OIS4_MASK (0x01U << TIM1_CR2_OIS4_SHIFT) +#define TIM1_CR2_OIS4(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR2_OIS4_SHIFT)) & TIM1_CR2_OIS4_MASK) + +#define TIM1_CR2_OIS3N_SHIFT (13) +#define TIM1_CR2_OIS3N_MASK (0x01U << TIM1_CR2_OIS3N_SHIFT) +#define TIM1_CR2_OIS3N(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR2_OIS3N_SHIFT)) & TIM1_CR2_OIS3N_MASK) + +#define TIM1_CR2_OIS3_SHIFT (12) +#define TIM1_CR2_OIS3_MASK (0x01U << TIM1_CR2_OIS3_SHIFT) +#define TIM1_CR2_OIS3(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR2_OIS3_SHIFT)) & TIM1_CR2_OIS3_MASK) + +#define TIM1_CR2_OIS2N_SHIFT (11) +#define TIM1_CR2_OIS2N_MASK (0x01U << TIM1_CR2_OIS2N_SHIFT) +#define TIM1_CR2_OIS2N(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR2_OIS2N_SHIFT)) & TIM1_CR2_OIS2N_MASK) + +#define TIM1_CR2_OIS2_SHIFT (10) +#define TIM1_CR2_OIS2_MASK (0x01U << TIM1_CR2_OIS2_SHIFT) +#define TIM1_CR2_OIS2(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR2_OIS2_SHIFT)) & TIM1_CR2_OIS2_MASK) + +#define TIM1_CR2_OIS1N_SHIFT (9) +#define TIM1_CR2_OIS1N_MASK (0x01U << TIM1_CR2_OIS1N_SHIFT) +#define TIM1_CR2_OIS1N(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR2_OIS1N_SHIFT)) & TIM1_CR2_OIS1N_MASK) + +#define TIM1_CR2_OIS1_SHIFT (8) +#define TIM1_CR2_OIS1_MASK (0x01U << TIM1_CR2_OIS1_SHIFT) +#define TIM1_CR2_OIS1(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR2_OIS1_SHIFT)) & TIM1_CR2_OIS1_MASK) + +#define TIM1_CR2_TI1S_SHIFT (7) +#define TIM1_CR2_TI1S_MASK (0x01U << TIM1_CR2_TI1S_SHIFT) +#define TIM1_CR2_TI1S(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR2_TI1S_SHIFT)) & TIM1_CR2_TI1S_MASK) + +#define TIM1_CR2_MMS_SHIFT (4) +#define TIM1_CR2_MMS_MASK (0x7U << TIM1_CR2_MMS_SHIFT) +#define TIM1_CR2_MMS(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR2_MMS_SHIFT)) & TIM1_CR2_MMS_MASK) + +#define TIM1_CR2_CCDS_SHIFT (3) +#define TIM1_CR2_CCDS_MASK (0x01U << TIM1_CR2_CCDS_SHIFT) +#define TIM1_CR2_CCDS(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR2_CCDS_SHIFT)) & TIM1_CR2_CCDS_MASK) + +#define TIM1_CR2_CCUS_SHIFT (2) +#define TIM1_CR2_CCUS_MASK (0x01U << TIM1_CR2_CCUS_SHIFT) +#define TIM1_CR2_CCUS(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR2_CCUS_SHIFT)) & TIM1_CR2_CCUS_MASK) + +#define TIM1_CR2_CCPC_SHIFT (0) +#define TIM1_CR2_CCPC_MASK (0x01U << TIM1_CR2_CCPC_SHIFT) +#define TIM1_CR2_CCPC(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CR2_CCPC_SHIFT)) & TIM1_CR2_CCPC_MASK) + +/*! + * @brief TIM1_SMCR Register Bit Definition + */ + +#define TIM1_SMCR_ETP_SHIFT (15) +#define TIM1_SMCR_ETP_MASK (0x01U << TIM1_SMCR_ETP_SHIFT) +#define TIM1_SMCR_ETP(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SMCR_ETP_SHIFT)) & TIM1_SMCR_ETP_MASK) + +#define TIM1_SMCR_ECE_SHIFT (14) +#define TIM1_SMCR_ECE_MASK (0x01U << TIM1_SMCR_ECE_SHIFT) +#define TIM1_SMCR_ECE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SMCR_ECE_SHIFT)) & TIM1_SMCR_ECE_MASK) + +#define TIM1_SMCR_ETPS_SHIFT (12) +#define TIM1_SMCR_ETPS_MASK (0x3U << TIM1_SMCR_ETPS_SHIFT) +#define TIM1_SMCR_ETPS(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SMCR_ETPS_SHIFT)) & TIM1_SMCR_ETPS_MASK) + +#define TIM1_SMCR_ETF_SHIFT (8) +#define TIM1_SMCR_ETF_MASK (0xFU << TIM1_SMCR_ETF_SHIFT) +#define TIM1_SMCR_ETF(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SMCR_ETF_SHIFT)) & TIM1_SMCR_ETF_MASK) + +#define TIM1_SMCR_MSM_SHIFT (7) +#define TIM1_SMCR_MSM_MASK (0x01U << TIM1_SMCR_MSM_SHIFT) +#define TIM1_SMCR_MSM(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SMCR_MSM_SHIFT)) & TIM1_SMCR_MSM_MASK) + +#define TIM1_SMCR_TS_SHIFT (4) +#define TIM1_SMCR_TS_MASK (0x7U << TIM1_SMCR_TS_SHIFT) +#define TIM1_SMCR_TS(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SMCR_TS_SHIFT)) & TIM1_SMCR_TS_MASK) + +#define TIM1_SMCR_OCCS_SHIFT (3) +#define TIM1_SMCR_OCCS_MASK (0x01U << TIM1_SMCR_OCCS_SHIFT) +#define TIM1_SMCR_OCCS(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SMCR_OCCS_SHIFT)) & TIM1_SMCR_OCCS_MASK) + +#define TIM1_SMCR_SMS_SHIFT (0) +#define TIM1_SMCR_SMS_MASK (0x7U << TIM1_SMCR_SMS_SHIFT) +#define TIM1_SMCR_SMS(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SMCR_SMS_SHIFT)) & TIM1_SMCR_SMS_MASK) + +/*! + * @brief TIM1_DIER Register Bit Definition + */ + +#define TIM1_DIER_CC5DE_SHIFT (17) +#define TIM1_DIER_CC5DE_MASK (0x01U << TIM1_DIER_CC5DE_SHIFT) +#define TIM1_DIER_CC5DE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DIER_CC5DE_SHIFT)) & TIM1_DIER_CC5DE_MASK) + +#define TIM1_DIER_CC5IE_SHIFT (16) +#define TIM1_DIER_CC5IE_MASK (0x01U << TIM1_DIER_CC5IE_SHIFT) +#define TIM1_DIER_CC5IE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DIER_CC5IE_SHIFT)) & TIM1_DIER_CC5IE_MASK) + +#define TIM1_DIER_TDE_SHIFT (14) +#define TIM1_DIER_TDE_MASK (0x01U << TIM1_DIER_TDE_SHIFT) +#define TIM1_DIER_TDE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DIER_TDE_SHIFT)) & TIM1_DIER_TDE_MASK) + +#define TIM1_DIER_COMDE_SHIFT (13) +#define TIM1_DIER_COMDE_MASK (0x01U << TIM1_DIER_COMDE_SHIFT) +#define TIM1_DIER_COMDE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DIER_COMDE_SHIFT)) & TIM1_DIER_COMDE_MASK) + +#define TIM1_DIER_CC4DE_SHIFT (12) +#define TIM1_DIER_CC4DE_MASK (0x01U << TIM1_DIER_CC4DE_SHIFT) +#define TIM1_DIER_CC4DE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DIER_CC4DE_SHIFT)) & TIM1_DIER_CC4DE_MASK) + +#define TIM1_DIER_CC3DE_SHIFT (11) +#define TIM1_DIER_CC3DE_MASK (0x01U << TIM1_DIER_CC3DE_SHIFT) +#define TIM1_DIER_CC3DE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DIER_CC3DE_SHIFT)) & TIM1_DIER_CC3DE_MASK) + +#define TIM1_DIER_CC2DE_SHIFT (10) +#define TIM1_DIER_CC2DE_MASK (0x01U << TIM1_DIER_CC2DE_SHIFT) +#define TIM1_DIER_CC2DE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DIER_CC2DE_SHIFT)) & TIM1_DIER_CC2DE_MASK) + +#define TIM1_DIER_CC1DE_SHIFT (9) +#define TIM1_DIER_CC1DE_MASK (0x01U << TIM1_DIER_CC1DE_SHIFT) +#define TIM1_DIER_CC1DE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DIER_CC1DE_SHIFT)) & TIM1_DIER_CC1DE_MASK) + +#define TIM1_DIER_UDE_SHIFT (8) +#define TIM1_DIER_UDE_MASK (0x01U << TIM1_DIER_UDE_SHIFT) +#define TIM1_DIER_UDE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DIER_UDE_SHIFT)) & TIM1_DIER_UDE_MASK) + +#define TIM1_DIER_BIE_SHIFT (7) +#define TIM1_DIER_BIE_MASK (0x01U << TIM1_DIER_BIE_SHIFT) +#define TIM1_DIER_BIE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DIER_BIE_SHIFT)) & TIM1_DIER_BIE_MASK) + +#define TIM1_DIER_TIE_SHIFT (6) +#define TIM1_DIER_TIE_MASK (0x01U << TIM1_DIER_TIE_SHIFT) +#define TIM1_DIER_TIE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DIER_TIE_SHIFT)) & TIM1_DIER_TIE_MASK) + +#define TIM1_DIER_COMIE_SHIFT (5) +#define TIM1_DIER_COMIE_MASK (0x01U << TIM1_DIER_COMIE_SHIFT) +#define TIM1_DIER_COMIE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DIER_COMIE_SHIFT)) & TIM1_DIER_COMIE_MASK) + +#define TIM1_DIER_CC4IE_SHIFT (4) +#define TIM1_DIER_CC4IE_MASK (0x01U << TIM1_DIER_CC4IE_SHIFT) +#define TIM1_DIER_CC4IE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DIER_CC4IE_SHIFT)) & TIM1_DIER_CC4IE_MASK) + +#define TIM1_DIER_CC3IE_SHIFT (3) +#define TIM1_DIER_CC3IE_MASK (0x01U << TIM1_DIER_CC3IE_SHIFT) +#define TIM1_DIER_CC3IE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DIER_CC3IE_SHIFT)) & TIM1_DIER_CC3IE_MASK) + +#define TIM1_DIER_CC2IE_SHIFT (2) +#define TIM1_DIER_CC2IE_MASK (0x01U << TIM1_DIER_CC2IE_SHIFT) +#define TIM1_DIER_CC2IE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DIER_CC2IE_SHIFT)) & TIM1_DIER_CC2IE_MASK) + +#define TIM1_DIER_CC1IE_SHIFT (1) +#define TIM1_DIER_CC1IE_MASK (0x01U << TIM1_DIER_CC1IE_SHIFT) +#define TIM1_DIER_CC1IE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DIER_CC1IE_SHIFT)) & TIM1_DIER_CC1IE_MASK) + +#define TIM1_DIER_UIE_SHIFT (0) +#define TIM1_DIER_UIE_MASK (0x01U << TIM1_DIER_UIE_SHIFT) +#define TIM1_DIER_UIE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DIER_UIE_SHIFT)) & TIM1_DIER_UIE_MASK) + +/*! + * @brief TIM1_SR Register Bit Definition + */ + +#define TIM1_SR_CC5IF_SHIFT (16) +#define TIM1_SR_CC5IF_MASK (0x01U << TIM1_SR_CC5IF_SHIFT) +#define TIM1_SR_CC5IF(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SR_CC5IF_SHIFT)) & TIM1_SR_CC5IF_MASK) + +#define TIM1_SR_CC4OF_SHIFT (12) +#define TIM1_SR_CC4OF_MASK (0x01U << TIM1_SR_CC4OF_SHIFT) +#define TIM1_SR_CC4OF(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SR_CC4OF_SHIFT)) & TIM1_SR_CC4OF_MASK) + +#define TIM1_SR_CC3OF_SHIFT (11) +#define TIM1_SR_CC3OF_MASK (0x01U << TIM1_SR_CC3OF_SHIFT) +#define TIM1_SR_CC3OF(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SR_CC3OF_SHIFT)) & TIM1_SR_CC3OF_MASK) + +#define TIM1_SR_CC2OF_SHIFT (10) +#define TIM1_SR_CC2OF_MASK (0x01U << TIM1_SR_CC2OF_SHIFT) +#define TIM1_SR_CC2OF(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SR_CC2OF_SHIFT)) & TIM1_SR_CC2OF_MASK) + +#define TIM1_SR_CC1OF_SHIFT (9) +#define TIM1_SR_CC1OF_MASK (0x01U << TIM1_SR_CC1OF_SHIFT) +#define TIM1_SR_CC1OF(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SR_CC1OF_SHIFT)) & TIM1_SR_CC1OF_MASK) + +#define TIM1_SR_BIF_SHIFT (7) +#define TIM1_SR_BIF_MASK (0x01U << TIM1_SR_BIF_SHIFT) +#define TIM1_SR_BIF(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SR_BIF_SHIFT)) & TIM1_SR_BIF_MASK) + +#define TIM1_SR_TIF_SHIFT (6) +#define TIM1_SR_TIF_MASK (0x01U << TIM1_SR_TIF_SHIFT) +#define TIM1_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SR_TIF_SHIFT)) & TIM1_SR_TIF_MASK) + +#define TIM1_SR_COMIF_SHIFT (5) +#define TIM1_SR_COMIF_MASK (0x01U << TIM1_SR_COMIF_SHIFT) +#define TIM1_SR_COMIF(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SR_COMIF_SHIFT)) & TIM1_SR_COMIF_MASK) + +#define TIM1_SR_CC4IF_SHIFT (4) +#define TIM1_SR_CC4IF_MASK (0x01U << TIM1_SR_CC4IF_SHIFT) +#define TIM1_SR_CC4IF(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SR_CC4IF_SHIFT)) & TIM1_SR_CC4IF_MASK) + +#define TIM1_SR_CC3IF_SHIFT (3) +#define TIM1_SR_CC3IF_MASK (0x01U << TIM1_SR_CC3IF_SHIFT) +#define TIM1_SR_CC3IF(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SR_CC3IF_SHIFT)) & TIM1_SR_CC3IF_MASK) + +#define TIM1_SR_CC2IF_SHIFT (2) +#define TIM1_SR_CC2IF_MASK (0x01U << TIM1_SR_CC2IF_SHIFT) +#define TIM1_SR_CC2IF(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SR_CC2IF_SHIFT)) & TIM1_SR_CC2IF_MASK) + +#define TIM1_SR_CC1IF_SHIFT (1) +#define TIM1_SR_CC1IF_MASK (0x01U << TIM1_SR_CC1IF_SHIFT) +#define TIM1_SR_CC1IF(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SR_CC1IF_SHIFT)) & TIM1_SR_CC1IF_MASK) + +#define TIM1_SR_UIF_SHIFT (0) +#define TIM1_SR_UIF_MASK (0x01U << TIM1_SR_UIF_SHIFT) +#define TIM1_SR_UIF(x) (((uint32_t)(((uint32_t)(x)) << TIM1_SR_UIF_SHIFT)) & TIM1_SR_UIF_MASK) + +/*! + * @brief TIM1_EGR Register Bit Definition + */ + +#define TIM1_EGR_CC5G_SHIFT (16) +#define TIM1_EGR_CC5G_MASK (0x01U << TIM1_EGR_CC5G_SHIFT) +#define TIM1_EGR_CC5G(x) (((uint32_t)(((uint32_t)(x)) << TIM1_EGR_CC5G_SHIFT)) & TIM1_EGR_CC5G_MASK) + +#define TIM1_EGR_BG_SHIFT (7) +#define TIM1_EGR_BG_MASK (0x01U << TIM1_EGR_BG_SHIFT) +#define TIM1_EGR_BG(x) (((uint32_t)(((uint32_t)(x)) << TIM1_EGR_BG_SHIFT)) & TIM1_EGR_BG_MASK) + +#define TIM1_EGR_TG_SHIFT (6) +#define TIM1_EGR_TG_MASK (0x01U << TIM1_EGR_TG_SHIFT) +#define TIM1_EGR_TG(x) (((uint32_t)(((uint32_t)(x)) << TIM1_EGR_TG_SHIFT)) & TIM1_EGR_TG_MASK) + +#define TIM1_EGR_COMG_SHIFT (5) +#define TIM1_EGR_COMG_MASK (0x01U << TIM1_EGR_COMG_SHIFT) +#define TIM1_EGR_COMG(x) (((uint32_t)(((uint32_t)(x)) << TIM1_EGR_COMG_SHIFT)) & TIM1_EGR_COMG_MASK) + +#define TIM1_EGR_CC4G_SHIFT (4) +#define TIM1_EGR_CC4G_MASK (0x01U << TIM1_EGR_CC4G_SHIFT) +#define TIM1_EGR_CC4G(x) (((uint32_t)(((uint32_t)(x)) << TIM1_EGR_CC4G_SHIFT)) & TIM1_EGR_CC4G_MASK) + +#define TIM1_EGR_CC3G_SHIFT (3) +#define TIM1_EGR_CC3G_MASK (0x01U << TIM1_EGR_CC3G_SHIFT) +#define TIM1_EGR_CC3G(x) (((uint32_t)(((uint32_t)(x)) << TIM1_EGR_CC3G_SHIFT)) & TIM1_EGR_CC3G_MASK) + +#define TIM1_EGR_CC2G_SHIFT (2) +#define TIM1_EGR_CC2G_MASK (0x01U << TIM1_EGR_CC2G_SHIFT) +#define TIM1_EGR_CC2G(x) (((uint32_t)(((uint32_t)(x)) << TIM1_EGR_CC2G_SHIFT)) & TIM1_EGR_CC2G_MASK) + +#define TIM1_EGR_CC1G_SHIFT (1) +#define TIM1_EGR_CC1G_MASK (0x01U << TIM1_EGR_CC1G_SHIFT) +#define TIM1_EGR_CC1G(x) (((uint32_t)(((uint32_t)(x)) << TIM1_EGR_CC1G_SHIFT)) & TIM1_EGR_CC1G_MASK) + +#define TIM1_EGR_UG_SHIFT (0) +#define TIM1_EGR_UG_MASK (0x01U << TIM1_EGR_UG_SHIFT) +#define TIM1_EGR_UG(x) (((uint32_t)(((uint32_t)(x)) << TIM1_EGR_UG_SHIFT)) & TIM1_EGR_UG_MASK) + +/*! + * @brief TIM1_CCMR1 Register Bit Definition + */ + +#define TIM1_CCMR1_OC2CE_SHIFT (15) +#define TIM1_CCMR1_OC2CE_MASK (0x01U << TIM1_CCMR1_OC2CE_SHIFT) +#define TIM1_CCMR1_OC2CE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR1_OC2CE_SHIFT)) & TIM1_CCMR1_OC2CE_MASK) + +#define TIM1_CCMR1_OC2M_SHIFT (12) +#define TIM1_CCMR1_OC2M_MASK (0x7U << TIM1_CCMR1_OC2M_SHIFT) +#define TIM1_CCMR1_OC2M(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR1_OC2M_SHIFT)) & TIM1_CCMR1_OC2M_MASK) + +#define TIM1_CCMR1_OC2PE_SHIFT (11) +#define TIM1_CCMR1_OC2PE_MASK (0x01U << TIM1_CCMR1_OC2PE_SHIFT) +#define TIM1_CCMR1_OC2PE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR1_OC2PE_SHIFT)) & TIM1_CCMR1_OC2PE_MASK) + +#define TIM1_CCMR1_OC2FE_SHIFT (10) +#define TIM1_CCMR1_OC2FE_MASK (0x01U << TIM1_CCMR1_OC2FE_SHIFT) +#define TIM1_CCMR1_OC2FE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR1_OC2FE_SHIFT)) & TIM1_CCMR1_OC2FE_MASK) + +#define TIM1_CCMR1_CC2S_SHIFT (8) +#define TIM1_CCMR1_CC2S_MASK (0x3U << TIM1_CCMR1_CC2S_SHIFT) +#define TIM1_CCMR1_CC2S(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR1_CC2S_SHIFT)) & TIM1_CCMR1_CC2S_MASK) + +#define TIM1_CCMR1_OC1CE_SHIFT (7) +#define TIM1_CCMR1_OC1CE_MASK (0x01U << TIM1_CCMR1_OC1CE_SHIFT) +#define TIM1_CCMR1_OC1CE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR1_OC1CE_SHIFT)) & TIM1_CCMR1_OC1CE_MASK) + +#define TIM1_CCMR1_OC1M_SHIFT (4) +#define TIM1_CCMR1_OC1M_MASK (0x7U << TIM1_CCMR1_OC1M_SHIFT) +#define TIM1_CCMR1_OC1M(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR1_OC1M_SHIFT)) & TIM1_CCMR1_OC1M_MASK) + +#define TIM1_CCMR1_OC1PE_SHIFT (3) +#define TIM1_CCMR1_OC1PE_MASK (0x01U << TIM1_CCMR1_OC1PE_SHIFT) +#define TIM1_CCMR1_OC1PE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR1_OC1PE_SHIFT)) & TIM1_CCMR1_OC1PE_MASK) + +#define TIM1_CCMR1_OC1FE_SHIFT (2) +#define TIM1_CCMR1_OC1FE_MASK (0x01U << TIM1_CCMR1_OC1FE_SHIFT) +#define TIM1_CCMR1_OC1FE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR1_OC1FE_SHIFT)) & TIM1_CCMR1_OC1FE_MASK) + +#define TIM1_CCMR1_CC1S_SHIFT (0) +#define TIM1_CCMR1_CC1S_MASK (0x3U << TIM1_CCMR1_CC1S_SHIFT) +#define TIM1_CCMR1_CC1S(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR1_CC1S_SHIFT)) & TIM1_CCMR1_CC1S_MASK) + +/*! + * @brief TIM1_CCMR1 Register Bit Definition + */ + +#define TIM1_CCMR1_IC2F_SHIFT (12) +#define TIM1_CCMR1_IC2F_MASK (0xFU << TIM1_CCMR1_IC2F_SHIFT) +#define TIM1_CCMR1_IC2F(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR1_IC2F_SHIFT)) & TIM1_CCMR1_IC2F_MASK) + +#define TIM1_CCMR1_IC2PSC_SHIFT (10) +#define TIM1_CCMR1_IC2PSC_MASK (0x3U << TIM1_CCMR1_IC2PSC_SHIFT) +#define TIM1_CCMR1_IC2PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR1_IC2PSC_SHIFT)) & TIM1_CCMR1_IC2PSC_MASK) + +#define TIM1_CCMR1_CC2S_SHIFT (8) +#define TIM1_CCMR1_CC2S_MASK (0x3U << TIM1_CCMR1_CC2S_SHIFT) +#define TIM1_CCMR1_CC2S(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR1_CC2S_SHIFT)) & TIM1_CCMR1_CC2S_MASK) + +#define TIM1_CCMR1_IC1F_SHIFT (4) +#define TIM1_CCMR1_IC1F_MASK (0xFU << TIM1_CCMR1_IC1F_SHIFT) +#define TIM1_CCMR1_IC1F(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR1_IC1F_SHIFT)) & TIM1_CCMR1_IC1F_MASK) + +#define TIM1_CCMR1_IC1PSC_SHIFT (2) +#define TIM1_CCMR1_IC1PSC_MASK (0x3U << TIM1_CCMR1_IC1PSC_SHIFT) +#define TIM1_CCMR1_IC1PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR1_IC1PSC_SHIFT)) & TIM1_CCMR1_IC1PSC_MASK) + +#define TIM1_CCMR1_CC1S_SHIFT (0) +#define TIM1_CCMR1_CC1S_MASK (0x3U << TIM1_CCMR1_CC1S_SHIFT) +#define TIM1_CCMR1_CC1S(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR1_CC1S_SHIFT)) & TIM1_CCMR1_CC1S_MASK) + +/*! + * @brief TIM1_CCMR2 Register Bit Definition + */ + +#define TIM1_CCMR2_OC4CE_SHIFT (15) +#define TIM1_CCMR2_OC4CE_MASK (0x01U << TIM1_CCMR2_OC4CE_SHIFT) +#define TIM1_CCMR2_OC4CE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR2_OC4CE_SHIFT)) & TIM1_CCMR2_OC4CE_MASK) + +#define TIM1_CCMR2_OC4M_SHIFT (12) +#define TIM1_CCMR2_OC4M_MASK (0x7U << TIM1_CCMR2_OC4M_SHIFT) +#define TIM1_CCMR2_OC4M(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR2_OC4M_SHIFT)) & TIM1_CCMR2_OC4M_MASK) + +#define TIM1_CCMR2_OC4PE_SHIFT (11) +#define TIM1_CCMR2_OC4PE_MASK (0x01U << TIM1_CCMR2_OC4PE_SHIFT) +#define TIM1_CCMR2_OC4PE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR2_OC4PE_SHIFT)) & TIM1_CCMR2_OC4PE_MASK) + +#define TIM1_CCMR2_OC4FE_SHIFT (10) +#define TIM1_CCMR2_OC4FE_MASK (0x01U << TIM1_CCMR2_OC4FE_SHIFT) +#define TIM1_CCMR2_OC4FE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR2_OC4FE_SHIFT)) & TIM1_CCMR2_OC4FE_MASK) + +#define TIM1_CCMR2_CC4S_SHIFT (8) +#define TIM1_CCMR2_CC4S_MASK (0x3U << TIM1_CCMR2_CC4S_SHIFT) +#define TIM1_CCMR2_CC4S(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR2_CC4S_SHIFT)) & TIM1_CCMR2_CC4S_MASK) + +#define TIM1_CCMR2_OC3CE_SHIFT (7) +#define TIM1_CCMR2_OC3CE_MASK (0x01U << TIM1_CCMR2_OC3CE_SHIFT) +#define TIM1_CCMR2_OC3CE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR2_OC3CE_SHIFT)) & TIM1_CCMR2_OC3CE_MASK) + +#define TIM1_CCMR2_OC3M_SHIFT (4) +#define TIM1_CCMR2_OC3M_MASK (0x7U << TIM1_CCMR2_OC3M_SHIFT) +#define TIM1_CCMR2_OC3M(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR2_OC3M_SHIFT)) & TIM1_CCMR2_OC3M_MASK) + +#define TIM1_CCMR2_OC3PE_SHIFT (3) +#define TIM1_CCMR2_OC3PE_MASK (0x01U << TIM1_CCMR2_OC3PE_SHIFT) +#define TIM1_CCMR2_OC3PE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR2_OC3PE_SHIFT)) & TIM1_CCMR2_OC3PE_MASK) + +#define TIM1_CCMR2_OC3FE_SHIFT (2) +#define TIM1_CCMR2_OC3FE_MASK (0x01U << TIM1_CCMR2_OC3FE_SHIFT) +#define TIM1_CCMR2_OC3FE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR2_OC3FE_SHIFT)) & TIM1_CCMR2_OC3FE_MASK) + +#define TIM1_CCMR2_CC3S_SHIFT (0) +#define TIM1_CCMR2_CC3S_MASK (0x3U << TIM1_CCMR2_CC3S_SHIFT) +#define TIM1_CCMR2_CC3S(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR2_CC3S_SHIFT)) & TIM1_CCMR2_CC3S_MASK) + +/*! + * @brief TIM1_CCMR2 Register Bit Definition + */ + +#define TIM1_CCMR2_IC4F_SHIFT (12) +#define TIM1_CCMR2_IC4F_MASK (0xFU << TIM1_CCMR2_IC4F_SHIFT) +#define TIM1_CCMR2_IC4F(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR2_IC4F_SHIFT)) & TIM1_CCMR2_IC4F_MASK) + +#define TIM1_CCMR2_IC4PSC_SHIFT (10) +#define TIM1_CCMR2_IC4PSC_MASK (0x3U << TIM1_CCMR2_IC4PSC_SHIFT) +#define TIM1_CCMR2_IC4PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR2_IC4PSC_SHIFT)) & TIM1_CCMR2_IC4PSC_MASK) + +#define TIM1_CCMR2_CC4S_SHIFT (8) +#define TIM1_CCMR2_CC4S_MASK (0x3U << TIM1_CCMR2_CC4S_SHIFT) +#define TIM1_CCMR2_CC4S(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR2_CC4S_SHIFT)) & TIM1_CCMR2_CC4S_MASK) + +#define TIM1_CCMR2_IC3F_SHIFT (4) +#define TIM1_CCMR2_IC3F_MASK (0xFU << TIM1_CCMR2_IC3F_SHIFT) +#define TIM1_CCMR2_IC3F(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR2_IC3F_SHIFT)) & TIM1_CCMR2_IC3F_MASK) + +#define TIM1_CCMR2_IC3PSC_SHIFT (2) +#define TIM1_CCMR2_IC3PSC_MASK (0x3U << TIM1_CCMR2_IC3PSC_SHIFT) +#define TIM1_CCMR2_IC3PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR2_IC3PSC_SHIFT)) & TIM1_CCMR2_IC3PSC_MASK) + +#define TIM1_CCMR2_CC3S_SHIFT (0) +#define TIM1_CCMR2_CC3S_MASK (0x3U << TIM1_CCMR2_CC3S_SHIFT) +#define TIM1_CCMR2_CC3S(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR2_CC3S_SHIFT)) & TIM1_CCMR2_CC3S_MASK) + +/*! + * @brief TIM1_CCER Register Bit Definition + */ + +#define TIM1_CCER_CC4NP_SHIFT (15) +#define TIM1_CCER_CC4NP_MASK (0x01U << TIM1_CCER_CC4NP_SHIFT) +#define TIM1_CCER_CC4NP(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCER_CC4NP_SHIFT)) & TIM1_CCER_CC4NP_MASK) + +#define TIM1_CCER_CC4NE_SHIFT (14) +#define TIM1_CCER_CC4NE_MASK (0x01U << TIM1_CCER_CC4NE_SHIFT) +#define TIM1_CCER_CC4NE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCER_CC4NE_SHIFT)) & TIM1_CCER_CC4NE_MASK) + +#define TIM1_CCER_CC4P_SHIFT (13) +#define TIM1_CCER_CC4P_MASK (0x01U << TIM1_CCER_CC4P_SHIFT) +#define TIM1_CCER_CC4P(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCER_CC4P_SHIFT)) & TIM1_CCER_CC4P_MASK) + +#define TIM1_CCER_CC4E_SHIFT (12) +#define TIM1_CCER_CC4E_MASK (0x01U << TIM1_CCER_CC4E_SHIFT) +#define TIM1_CCER_CC4E(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCER_CC4E_SHIFT)) & TIM1_CCER_CC4E_MASK) + +#define TIM1_CCER_CC3NP_SHIFT (11) +#define TIM1_CCER_CC3NP_MASK (0x01U << TIM1_CCER_CC3NP_SHIFT) +#define TIM1_CCER_CC3NP(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCER_CC3NP_SHIFT)) & TIM1_CCER_CC3NP_MASK) + +#define TIM1_CCER_CC3NE_SHIFT (10) +#define TIM1_CCER_CC3NE_MASK (0x01U << TIM1_CCER_CC3NE_SHIFT) +#define TIM1_CCER_CC3NE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCER_CC3NE_SHIFT)) & TIM1_CCER_CC3NE_MASK) + +#define TIM1_CCER_CC3P_SHIFT (9) +#define TIM1_CCER_CC3P_MASK (0x01U << TIM1_CCER_CC3P_SHIFT) +#define TIM1_CCER_CC3P(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCER_CC3P_SHIFT)) & TIM1_CCER_CC3P_MASK) + +#define TIM1_CCER_CC3E_SHIFT (8) +#define TIM1_CCER_CC3E_MASK (0x01U << TIM1_CCER_CC3E_SHIFT) +#define TIM1_CCER_CC3E(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCER_CC3E_SHIFT)) & TIM1_CCER_CC3E_MASK) + +#define TIM1_CCER_CC2NP_SHIFT (7) +#define TIM1_CCER_CC2NP_MASK (0x01U << TIM1_CCER_CC2NP_SHIFT) +#define TIM1_CCER_CC2NP(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCER_CC2NP_SHIFT)) & TIM1_CCER_CC2NP_MASK) + +#define TIM1_CCER_CC2NE_SHIFT (6) +#define TIM1_CCER_CC2NE_MASK (0x01U << TIM1_CCER_CC2NE_SHIFT) +#define TIM1_CCER_CC2NE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCER_CC2NE_SHIFT)) & TIM1_CCER_CC2NE_MASK) + +#define TIM1_CCER_CC2P_SHIFT (5) +#define TIM1_CCER_CC2P_MASK (0x01U << TIM1_CCER_CC2P_SHIFT) +#define TIM1_CCER_CC2P(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCER_CC2P_SHIFT)) & TIM1_CCER_CC2P_MASK) + +#define TIM1_CCER_CC2E_SHIFT (4) +#define TIM1_CCER_CC2E_MASK (0x01U << TIM1_CCER_CC2E_SHIFT) +#define TIM1_CCER_CC2E(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCER_CC2E_SHIFT)) & TIM1_CCER_CC2E_MASK) + +#define TIM1_CCER_CC1NP_SHIFT (3) +#define TIM1_CCER_CC1NP_MASK (0x01U << TIM1_CCER_CC1NP_SHIFT) +#define TIM1_CCER_CC1NP(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCER_CC1NP_SHIFT)) & TIM1_CCER_CC1NP_MASK) + +#define TIM1_CCER_CC1NE_SHIFT (2) +#define TIM1_CCER_CC1NE_MASK (0x01U << TIM1_CCER_CC1NE_SHIFT) +#define TIM1_CCER_CC1NE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCER_CC1NE_SHIFT)) & TIM1_CCER_CC1NE_MASK) + +#define TIM1_CCER_CC1P_SHIFT (1) +#define TIM1_CCER_CC1P_MASK (0x01U << TIM1_CCER_CC1P_SHIFT) +#define TIM1_CCER_CC1P(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCER_CC1P_SHIFT)) & TIM1_CCER_CC1P_MASK) + +#define TIM1_CCER_CC1E_SHIFT (0) +#define TIM1_CCER_CC1E_MASK (0x01U << TIM1_CCER_CC1E_SHIFT) +#define TIM1_CCER_CC1E(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCER_CC1E_SHIFT)) & TIM1_CCER_CC1E_MASK) + +/*! + * @brief TIM1_CNT Register Bit Definition + */ + +#define TIM1_CNT_CNT_SHIFT (0) +#define TIM1_CNT_CNT_MASK (0xFFFFU << TIM1_CNT_CNT_SHIFT) +#define TIM1_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CNT_CNT_SHIFT)) & TIM1_CNT_CNT_MASK) + +/*! + * @brief TIM1_PSC Register Bit Definition + */ + +#define TIM1_PSC_PSC_SHIFT (0) +#define TIM1_PSC_PSC_MASK (0xFFFFU << TIM1_PSC_PSC_SHIFT) +#define TIM1_PSC_PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM1_PSC_PSC_SHIFT)) & TIM1_PSC_PSC_MASK) + +/*! + * @brief TIM1_ARR Register Bit Definition + */ + +#define TIM1_ARR_ARR_SHIFT (0) +#define TIM1_ARR_ARR_MASK (0xFFFFU << TIM1_ARR_ARR_SHIFT) +#define TIM1_ARR_ARR(x) (((uint32_t)(((uint32_t)(x)) << TIM1_ARR_ARR_SHIFT)) & TIM1_ARR_ARR_MASK) + +/*! + * @brief TIM1_RCR Register Bit Definition + */ + +#define TIM1_RCR_REPCNT_SHIFT (8) +#define TIM1_RCR_REPCNT_MASK (0xFFU << TIM1_RCR_REPCNT_SHIFT) +#define TIM1_RCR_REPCNT(x) (((uint32_t)(((uint32_t)(x)) << TIM1_RCR_REPCNT_SHIFT)) & TIM1_RCR_REPCNT_MASK) + +#define TIM1_RCR_REP_SHIFT (0) +#define TIM1_RCR_REP_MASK (0xFFU << TIM1_RCR_REP_SHIFT) +#define TIM1_RCR_REP(x) (((uint32_t)(((uint32_t)(x)) << TIM1_RCR_REP_SHIFT)) & TIM1_RCR_REP_MASK) + +/*! + * @brief TIM1_CCR Register Bit Definition + */ + +#define TIM1_CCR_CCR_SHIFT (0) +#define TIM1_CCR_CCR_MASK (0xFFFFU << TIM1_CCR_CCR_SHIFT) +#define TIM1_CCR_CCR(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCR_CCR_SHIFT)) & TIM1_CCR_CCR_MASK) + +/*! + * @brief TIM1_BDTR Register Bit Definition + */ + +#define TIM1_BDTR_DOE_SHIFT (16) +#define TIM1_BDTR_DOE_MASK (0x01U << TIM1_BDTR_DOE_SHIFT) +#define TIM1_BDTR_DOE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_BDTR_DOE_SHIFT)) & TIM1_BDTR_DOE_MASK) + +#define TIM1_BDTR_MOE_SHIFT (15) +#define TIM1_BDTR_MOE_MASK (0x01U << TIM1_BDTR_MOE_SHIFT) +#define TIM1_BDTR_MOE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_BDTR_MOE_SHIFT)) & TIM1_BDTR_MOE_MASK) + +#define TIM1_BDTR_AOE_SHIFT (14) +#define TIM1_BDTR_AOE_MASK (0x01U << TIM1_BDTR_AOE_SHIFT) +#define TIM1_BDTR_AOE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_BDTR_AOE_SHIFT)) & TIM1_BDTR_AOE_MASK) + +#define TIM1_BDTR_BKP_SHIFT (13) +#define TIM1_BDTR_BKP_MASK (0x01U << TIM1_BDTR_BKP_SHIFT) +#define TIM1_BDTR_BKP(x) (((uint32_t)(((uint32_t)(x)) << TIM1_BDTR_BKP_SHIFT)) & TIM1_BDTR_BKP_MASK) + +#define TIM1_BDTR_BKE_SHIFT (12) +#define TIM1_BDTR_BKE_MASK (0x01U << TIM1_BDTR_BKE_SHIFT) +#define TIM1_BDTR_BKE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_BDTR_BKE_SHIFT)) & TIM1_BDTR_BKE_MASK) + +#define TIM1_BDTR_OSSR_SHIFT (11) +#define TIM1_BDTR_OSSR_MASK (0x01U << TIM1_BDTR_OSSR_SHIFT) +#define TIM1_BDTR_OSSR(x) (((uint32_t)(((uint32_t)(x)) << TIM1_BDTR_OSSR_SHIFT)) & TIM1_BDTR_OSSR_MASK) + +#define TIM1_BDTR_OSSI_SHIFT (10) +#define TIM1_BDTR_OSSI_MASK (0x01U << TIM1_BDTR_OSSI_SHIFT) +#define TIM1_BDTR_OSSI(x) (((uint32_t)(((uint32_t)(x)) << TIM1_BDTR_OSSI_SHIFT)) & TIM1_BDTR_OSSI_MASK) + +#define TIM1_BDTR_LOCK_SHIFT (8) +#define TIM1_BDTR_LOCK_MASK (0x3U << TIM1_BDTR_LOCK_SHIFT) +#define TIM1_BDTR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << TIM1_BDTR_LOCK_SHIFT)) & TIM1_BDTR_LOCK_MASK) + +#define TIM1_BDTR_DTG_SHIFT (0) +#define TIM1_BDTR_DTG_MASK (0xFFU << TIM1_BDTR_DTG_SHIFT) +#define TIM1_BDTR_DTG(x) (((uint32_t)(((uint32_t)(x)) << TIM1_BDTR_DTG_SHIFT)) & TIM1_BDTR_DTG_MASK) + +/*! + * @brief TIM1_DCR Register Bit Definition + */ + +#define TIM1_DCR_DBL_SHIFT (8) +#define TIM1_DCR_DBL_MASK (0x1FU << TIM1_DCR_DBL_SHIFT) +#define TIM1_DCR_DBL(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DCR_DBL_SHIFT)) & TIM1_DCR_DBL_MASK) + +#define TIM1_DCR_DBA_SHIFT (0) +#define TIM1_DCR_DBA_MASK (0x1FU << TIM1_DCR_DBA_SHIFT) +#define TIM1_DCR_DBA(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DCR_DBA_SHIFT)) & TIM1_DCR_DBA_MASK) + +/*! + * @brief TIM1_DMAR Register Bit Definition + */ + +#define TIM1_DMAR_DMAB_SHIFT (0) +#define TIM1_DMAR_DMAB_MASK (0xFFFFU << TIM1_DMAR_DMAB_SHIFT) +#define TIM1_DMAR_DMAB(x) (((uint32_t)(((uint32_t)(x)) << TIM1_DMAR_DMAB_SHIFT)) & TIM1_DMAR_DMAB_MASK) + +/*! + * @brief TIM1_CCMR3 Register Bit Definition + */ + +#define TIM1_CCMR3_OC5M_SHIFT (4) +#define TIM1_CCMR3_OC5M_MASK (0x7U << TIM1_CCMR3_OC5M_SHIFT) +#define TIM1_CCMR3_OC5M(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR3_OC5M_SHIFT)) & TIM1_CCMR3_OC5M_MASK) + +#define TIM1_CCMR3_OC5PE_SHIFT (3) +#define TIM1_CCMR3_OC5PE_MASK (0x01U << TIM1_CCMR3_OC5PE_SHIFT) +#define TIM1_CCMR3_OC5PE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR3_OC5PE_SHIFT)) & TIM1_CCMR3_OC5PE_MASK) + +#define TIM1_CCMR3_OC5FE_SHIFT (2) +#define TIM1_CCMR3_OC5FE_MASK (0x01U << TIM1_CCMR3_OC5FE_SHIFT) +#define TIM1_CCMR3_OC5FE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCMR3_OC5FE_SHIFT)) & TIM1_CCMR3_OC5FE_MASK) + +/*! + * @brief TIM1_CCR5 Register Bit Definition + */ + +#define TIM1_CCR5_CCR5_SHIFT (0) +#define TIM1_CCR5_CCR5_MASK (0xFFFFU << TIM1_CCR5_CCR5_SHIFT) +#define TIM1_CCR5_CCR5(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCR5_CCR5_SHIFT)) & TIM1_CCR5_CCR5_MASK) + +/*! + * @brief TIM1_PDER Register Bit Definition + */ + +#define TIM1_PDER_CCR5SHIFTEN_SHIFT (5) +#define TIM1_PDER_CCR5SHIFTEN_MASK (0x01U << TIM1_PDER_CCR5SHIFTEN_SHIFT) +#define TIM1_PDER_CCR5SHIFTEN(x) (((uint32_t)(((uint32_t)(x)) << TIM1_PDER_CCR5SHIFTEN_SHIFT)) & TIM1_PDER_CCR5SHIFTEN_MASK) + +#define TIM1_PDER_CCR4SHIFTEN_SHIFT (4) +#define TIM1_PDER_CCR4SHIFTEN_MASK (0x01U << TIM1_PDER_CCR4SHIFTEN_SHIFT) +#define TIM1_PDER_CCR4SHIFTEN(x) (((uint32_t)(((uint32_t)(x)) << TIM1_PDER_CCR4SHIFTEN_SHIFT)) & TIM1_PDER_CCR4SHIFTEN_MASK) + +#define TIM1_PDER_CCR3SHIFTEN_SHIFT (3) +#define TIM1_PDER_CCR3SHIFTEN_MASK (0x01U << TIM1_PDER_CCR3SHIFTEN_SHIFT) +#define TIM1_PDER_CCR3SHIFTEN(x) (((uint32_t)(((uint32_t)(x)) << TIM1_PDER_CCR3SHIFTEN_SHIFT)) & TIM1_PDER_CCR3SHIFTEN_MASK) + +#define TIM1_PDER_CCR2SHIFTEN_SHIFT (2) +#define TIM1_PDER_CCR2SHIFTEN_MASK (0x01U << TIM1_PDER_CCR2SHIFTEN_SHIFT) +#define TIM1_PDER_CCR2SHIFTEN(x) (((uint32_t)(((uint32_t)(x)) << TIM1_PDER_CCR2SHIFTEN_SHIFT)) & TIM1_PDER_CCR2SHIFTEN_MASK) + +#define TIM1_PDER_CCR1SHIFTEN_SHIFT (1) +#define TIM1_PDER_CCR1SHIFTEN_MASK (0x01U << TIM1_PDER_CCR1SHIFTEN_SHIFT) +#define TIM1_PDER_CCR1SHIFTEN(x) (((uint32_t)(((uint32_t)(x)) << TIM1_PDER_CCR1SHIFTEN_SHIFT)) & TIM1_PDER_CCR1SHIFTEN_MASK) + +#define TIM1_PDER_CCDREPE_SHIFT (0) +#define TIM1_PDER_CCDREPE_MASK (0x01U << TIM1_PDER_CCDREPE_SHIFT) +#define TIM1_PDER_CCDREPE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_PDER_CCDREPE_SHIFT)) & TIM1_PDER_CCDREPE_MASK) + +/*! + * @brief TIM1_CCRFALL Register Bit Definition + */ + +#define TIM1_CCRFALL_CCRFALL_SHIFT (0) +#define TIM1_CCRFALL_CCRFALL_MASK (0xFFFFU << TIM1_CCRFALL_CCRFALL_SHIFT) +#define TIM1_CCRFALL_CCRFALL(x) (((uint32_t)(((uint32_t)(x)) << TIM1_CCRFALL_CCRFALL_SHIFT)) & TIM1_CCRFALL_CCRFALL_MASK) + +/*! + * @brief TIM1_BKINF Register Bit Definition + */ + +#define TIM1_BKINF_COMPBKINSEL_SHIFT (13) +#define TIM1_BKINF_COMPBKINSEL_MASK (0x7U << TIM1_BKINF_COMPBKINSEL_SHIFT) +#define TIM1_BKINF_COMPBKINSEL(x) (((uint32_t)(((uint32_t)(x)) << TIM1_BKINF_COMPBKINSEL_SHIFT)) & TIM1_BKINF_COMPBKINSEL_MASK) + +#define TIM1_BKINF_IOBKINSEL_SHIFT (6) +#define TIM1_BKINF_IOBKINSEL_MASK (0xFU << TIM1_BKINF_IOBKINSEL_SHIFT) +#define TIM1_BKINF_IOBKINSEL(x) (((uint32_t)(((uint32_t)(x)) << TIM1_BKINF_IOBKINSEL_SHIFT)) & TIM1_BKINF_IOBKINSEL_MASK) + +#define TIM1_BKINF_CSSBKINSEL_SHIFT (5) +#define TIM1_BKINF_CSSBKINSEL_MASK (0x01U << TIM1_BKINF_CSSBKINSEL_SHIFT) +#define TIM1_BKINF_CSSBKINSEL(x) (((uint32_t)(((uint32_t)(x)) << TIM1_BKINF_CSSBKINSEL_SHIFT)) & TIM1_BKINF_CSSBKINSEL_MASK) + +#define TIM1_BKINF_BKINF_SHIFT (1) +#define TIM1_BKINF_BKINF_MASK (0xFU << TIM1_BKINF_BKINF_SHIFT) +#define TIM1_BKINF_BKINF(x) (((uint32_t)(((uint32_t)(x)) << TIM1_BKINF_BKINF_SHIFT)) & TIM1_BKINF_BKINF_MASK) + +#define TIM1_BKINF_BKINFE_SHIFT (0) +#define TIM1_BKINF_BKINFE_MASK (0x01U << TIM1_BKINF_BKINFE_SHIFT) +#define TIM1_BKINF_BKINFE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_BKINF_BKINFE_SHIFT)) & TIM1_BKINF_BKINFE_MASK) + +/*! + * @} + */ /* end of group TIM1_Register_Masks */ +/****************************************************************************** + *TIM1 Instance +*******************************************************************************/ + +#define TIM1 ((TIM1_Type*)TIM1_BASE) +#define TIM8 ((TIM1_Type*)TIM8_BASE) + +/*! + * @} + */ /* end of group TIM1_Peripheral_Access_Layer */ + +/*! + * @addtogroup TIM2_Peripheral_Access_Layer TIM2 Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * TIM2 Type + ******************************************************************************/ +typedef struct { + __IO uint32_t CR1; ///< Control Register 1 offset: 0x00 + __IO uint32_t CR2; ///< Control Register 2 offset: 0x04 + __IO uint32_t SMCR; ///< Slave Mode Control Register offset: 0x08 + __IO uint32_t DIER; ///< DMA/Interrupt Enable Register offset: 0x0C + __IO uint32_t SR; ///< status register offset: 0x10 + __IO uint32_t EGR; ///< event generation register offset: 0x14 + __IO uint32_t CCMR1; ///< Capture/Compare Mode Register 1 offset: 0x18 + __IO uint32_t CCMR2; ///< Capture/Compare Mode Register 2 offset: 0x1C + __IO uint32_t CCER; ///< Capture/Compare Enable Register offset: 0x20 + __IO uint32_t CNT; ///< counter offset: 0x24 + __IO uint32_t PSC; ///< Prescaler offset: 0x28 + __IO uint32_t ARR; ///< autoload register offset: 0x2C + __IO uint32_t Reserved51[1]; ///< Reserved + __IO uint32_t CCR[4]; ///< Capture/Compare Register 1 offset: 0x34 + __IO uint32_t Reserved52[1]; ///< Reserved + __IO uint32_t DCR; ///< DMA Control Register offset: 0x48 + __IO uint32_t DMAR; ///< DMA address for continuous mode offset: 0x4C + __IO uint32_t OR; ///< TIMERx option register offset: 0x50 +} TIM2_Type; + +/******************************************************************************* + * TIM2 Type + ******************************************************************************/ + +/*! + * @addtogroup TIM2_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief TIM2_CR1 Register Bit Definition + */ + +#define TIM2_CR1_CKD_SHIFT (8) +#define TIM2_CR1_CKD_MASK (0x3U << TIM2_CR1_CKD_SHIFT) +#define TIM2_CR1_CKD(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CR1_CKD_SHIFT)) & TIM2_CR1_CKD_MASK) + +#define TIM2_CR1_ARPE_SHIFT (7) +#define TIM2_CR1_ARPE_MASK (0x01U << TIM2_CR1_ARPE_SHIFT) +#define TIM2_CR1_ARPE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CR1_ARPE_SHIFT)) & TIM2_CR1_ARPE_MASK) + +#define TIM2_CR1_CMS_SHIFT (5) +#define TIM2_CR1_CMS_MASK (0x3U << TIM2_CR1_CMS_SHIFT) +#define TIM2_CR1_CMS(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CR1_CMS_SHIFT)) & TIM2_CR1_CMS_MASK) + +#define TIM2_CR1_DIR_SHIFT (4) +#define TIM2_CR1_DIR_MASK (0x01U << TIM2_CR1_DIR_SHIFT) +#define TIM2_CR1_DIR(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CR1_DIR_SHIFT)) & TIM2_CR1_DIR_MASK) + +#define TIM2_CR1_OPM_SHIFT (3) +#define TIM2_CR1_OPM_MASK (0x01U << TIM2_CR1_OPM_SHIFT) +#define TIM2_CR1_OPM(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CR1_OPM_SHIFT)) & TIM2_CR1_OPM_MASK) + +#define TIM2_CR1_URS_SHIFT (2) +#define TIM2_CR1_URS_MASK (0x01U << TIM2_CR1_URS_SHIFT) +#define TIM2_CR1_URS(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CR1_URS_SHIFT)) & TIM2_CR1_URS_MASK) + +#define TIM2_CR1_UDIS_SHIFT (1) +#define TIM2_CR1_UDIS_MASK (0x01U << TIM2_CR1_UDIS_SHIFT) +#define TIM2_CR1_UDIS(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CR1_UDIS_SHIFT)) & TIM2_CR1_UDIS_MASK) + +#define TIM2_CR1_CEN_SHIFT (0) +#define TIM2_CR1_CEN_MASK (0x01U << TIM2_CR1_CEN_SHIFT) +#define TIM2_CR1_CEN(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CR1_CEN_SHIFT)) & TIM2_CR1_CEN_MASK) + +/*! + * @brief TIM2_CR2 Register Bit Definition + */ + +#define TIM2_CR2_TI1S_SHIFT (7) +#define TIM2_CR2_TI1S_MASK (0x01U << TIM2_CR2_TI1S_SHIFT) +#define TIM2_CR2_TI1S(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CR2_TI1S_SHIFT)) & TIM2_CR2_TI1S_MASK) + +#define TIM2_CR2_MMS_SHIFT (4) +#define TIM2_CR2_MMS_MASK (0x7U << TIM2_CR2_MMS_SHIFT) +#define TIM2_CR2_MMS(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CR2_MMS_SHIFT)) & TIM2_CR2_MMS_MASK) + +#define TIM2_CR2_CCDS_SHIFT (3) +#define TIM2_CR2_CCDS_MASK (0x01U << TIM2_CR2_CCDS_SHIFT) +#define TIM2_CR2_CCDS(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CR2_CCDS_SHIFT)) & TIM2_CR2_CCDS_MASK) + +/*! + * @brief TIM2_SMCR Register Bit Definition + */ + +#define TIM2_SMCR_ETP_SHIFT (15) +#define TIM2_SMCR_ETP_MASK (0x01U << TIM2_SMCR_ETP_SHIFT) +#define TIM2_SMCR_ETP(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SMCR_ETP_SHIFT)) & TIM2_SMCR_ETP_MASK) + +#define TIM2_SMCR_ECE_SHIFT (14) +#define TIM2_SMCR_ECE_MASK (0x01U << TIM2_SMCR_ECE_SHIFT) +#define TIM2_SMCR_ECE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SMCR_ECE_SHIFT)) & TIM2_SMCR_ECE_MASK) + +#define TIM2_SMCR_ETPS_SHIFT (12) +#define TIM2_SMCR_ETPS_MASK (0x3U << TIM2_SMCR_ETPS_SHIFT) +#define TIM2_SMCR_ETPS(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SMCR_ETPS_SHIFT)) & TIM2_SMCR_ETPS_MASK) + +#define TIM2_SMCR_ETF_SHIFT (8) +#define TIM2_SMCR_ETF_MASK (0xFU << TIM2_SMCR_ETF_SHIFT) +#define TIM2_SMCR_ETF(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SMCR_ETF_SHIFT)) & TIM2_SMCR_ETF_MASK) + +#define TIM2_SMCR_MSM_SHIFT (7) +#define TIM2_SMCR_MSM_MASK (0x01U << TIM2_SMCR_MSM_SHIFT) +#define TIM2_SMCR_MSM(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SMCR_MSM_SHIFT)) & TIM2_SMCR_MSM_MASK) + +#define TIM2_SMCR_TS_SHIFT (4) +#define TIM2_SMCR_TS_MASK (0x7U << TIM2_SMCR_TS_SHIFT) +#define TIM2_SMCR_TS(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SMCR_TS_SHIFT)) & TIM2_SMCR_TS_MASK) + +#define TIM2_SMCR_OCCS_SHIFT (3) +#define TIM2_SMCR_OCCS_MASK (0x01U << TIM2_SMCR_OCCS_SHIFT) +#define TIM2_SMCR_OCCS(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SMCR_OCCS_SHIFT)) & TIM2_SMCR_OCCS_MASK) + +#define TIM2_SMCR_SMS_SHIFT (0) +#define TIM2_SMCR_SMS_MASK (0x7U << TIM2_SMCR_SMS_SHIFT) +#define TIM2_SMCR_SMS(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SMCR_SMS_SHIFT)) & TIM2_SMCR_SMS_MASK) + +/*! + * @brief TIM2_DIER Register Bit Definition + */ + +#define TIM2_DIER_TDE_SHIFT (14) +#define TIM2_DIER_TDE_MASK (0x01U << TIM2_DIER_TDE_SHIFT) +#define TIM2_DIER_TDE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_DIER_TDE_SHIFT)) & TIM2_DIER_TDE_MASK) + +#define TIM2_DIER_CC4DE_SHIFT (12) +#define TIM2_DIER_CC4DE_MASK (0x01U << TIM2_DIER_CC4DE_SHIFT) +#define TIM2_DIER_CC4DE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_DIER_CC4DE_SHIFT)) & TIM2_DIER_CC4DE_MASK) + +#define TIM2_DIER_CC3DE_SHIFT (11) +#define TIM2_DIER_CC3DE_MASK (0x01U << TIM2_DIER_CC3DE_SHIFT) +#define TIM2_DIER_CC3DE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_DIER_CC3DE_SHIFT)) & TIM2_DIER_CC3DE_MASK) + +#define TIM2_DIER_CC2DE_SHIFT (10) +#define TIM2_DIER_CC2DE_MASK (0x01U << TIM2_DIER_CC2DE_SHIFT) +#define TIM2_DIER_CC2DE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_DIER_CC2DE_SHIFT)) & TIM2_DIER_CC2DE_MASK) + +#define TIM2_DIER_CC1DE_SHIFT (9) +#define TIM2_DIER_CC1DE_MASK (0x01U << TIM2_DIER_CC1DE_SHIFT) +#define TIM2_DIER_CC1DE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_DIER_CC1DE_SHIFT)) & TIM2_DIER_CC1DE_MASK) + +#define TIM2_DIER_UDE_SHIFT (8) +#define TIM2_DIER_UDE_MASK (0x01U << TIM2_DIER_UDE_SHIFT) +#define TIM2_DIER_UDE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_DIER_UDE_SHIFT)) & TIM2_DIER_UDE_MASK) + +#define TIM2_DIER_TIE_SHIFT (6) +#define TIM2_DIER_TIE_MASK (0x01U << TIM2_DIER_TIE_SHIFT) +#define TIM2_DIER_TIE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_DIER_TIE_SHIFT)) & TIM2_DIER_TIE_MASK) + +#define TIM2_DIER_CC4IE_SHIFT (4) +#define TIM2_DIER_CC4IE_MASK (0x01U << TIM2_DIER_CC4IE_SHIFT) +#define TIM2_DIER_CC4IE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_DIER_CC4IE_SHIFT)) & TIM2_DIER_CC4IE_MASK) + +#define TIM2_DIER_CC3IE_SHIFT (3) +#define TIM2_DIER_CC3IE_MASK (0x01U << TIM2_DIER_CC3IE_SHIFT) +#define TIM2_DIER_CC3IE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_DIER_CC3IE_SHIFT)) & TIM2_DIER_CC3IE_MASK) + +#define TIM2_DIER_CC2IE_SHIFT (2) +#define TIM2_DIER_CC2IE_MASK (0x01U << TIM2_DIER_CC2IE_SHIFT) +#define TIM2_DIER_CC2IE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_DIER_CC2IE_SHIFT)) & TIM2_DIER_CC2IE_MASK) + +#define TIM2_DIER_CC1IE_SHIFT (1) +#define TIM2_DIER_CC1IE_MASK (0x01U << TIM2_DIER_CC1IE_SHIFT) +#define TIM2_DIER_CC1IE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_DIER_CC1IE_SHIFT)) & TIM2_DIER_CC1IE_MASK) + +#define TIM2_DIER_UIE_SHIFT (0) +#define TIM2_DIER_UIE_MASK (0x01U << TIM2_DIER_UIE_SHIFT) +#define TIM2_DIER_UIE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_DIER_UIE_SHIFT)) & TIM2_DIER_UIE_MASK) + +/*! + * @brief TIM2_SR Register Bit Definition + */ + +#define TIM2_SR_CC4OF_SHIFT (12) +#define TIM2_SR_CC4OF_MASK (0x01U << TIM2_SR_CC4OF_SHIFT) +#define TIM2_SR_CC4OF(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SR_CC4OF_SHIFT)) & TIM2_SR_CC4OF_MASK) + +#define TIM2_SR_CC3OF_SHIFT (11) +#define TIM2_SR_CC3OF_MASK (0x01U << TIM2_SR_CC3OF_SHIFT) +#define TIM2_SR_CC3OF(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SR_CC3OF_SHIFT)) & TIM2_SR_CC3OF_MASK) + +#define TIM2_SR_CC2OF_SHIFT (10) +#define TIM2_SR_CC2OF_MASK (0x01U << TIM2_SR_CC2OF_SHIFT) +#define TIM2_SR_CC2OF(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SR_CC2OF_SHIFT)) & TIM2_SR_CC2OF_MASK) + +#define TIM2_SR_CC1OF_SHIFT (9) +#define TIM2_SR_CC1OF_MASK (0x01U << TIM2_SR_CC1OF_SHIFT) +#define TIM2_SR_CC1OF(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SR_CC1OF_SHIFT)) & TIM2_SR_CC1OF_MASK) + +#define TIM2_SR_TIF_SHIFT (6) +#define TIM2_SR_TIF_MASK (0x01U << TIM2_SR_TIF_SHIFT) +#define TIM2_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SR_TIF_SHIFT)) & TIM2_SR_TIF_MASK) + +#define TIM2_SR_CC4IF_SHIFT (4) +#define TIM2_SR_CC4IF_MASK (0x01U << TIM2_SR_CC4IF_SHIFT) +#define TIM2_SR_CC4IF(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SR_CC4IF_SHIFT)) & TIM2_SR_CC4IF_MASK) + +#define TIM2_SR_CC3IF_SHIFT (3) +#define TIM2_SR_CC3IF_MASK (0x01U << TIM2_SR_CC3IF_SHIFT) +#define TIM2_SR_CC3IF(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SR_CC3IF_SHIFT)) & TIM2_SR_CC3IF_MASK) + +#define TIM2_SR_CC2IF_SHIFT (2) +#define TIM2_SR_CC2IF_MASK (0x01U << TIM2_SR_CC2IF_SHIFT) +#define TIM2_SR_CC2IF(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SR_CC2IF_SHIFT)) & TIM2_SR_CC2IF_MASK) + +#define TIM2_SR_CC1IF_SHIFT (1) +#define TIM2_SR_CC1IF_MASK (0x01U << TIM2_SR_CC1IF_SHIFT) +#define TIM2_SR_CC1IF(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SR_CC1IF_SHIFT)) & TIM2_SR_CC1IF_MASK) + +#define TIM2_SR_UIF_SHIFT (0) +#define TIM2_SR_UIF_MASK (0x01U << TIM2_SR_UIF_SHIFT) +#define TIM2_SR_UIF(x) (((uint32_t)(((uint32_t)(x)) << TIM2_SR_UIF_SHIFT)) & TIM2_SR_UIF_MASK) + +/*! + * @brief TIM2_EGR Register Bit Definition + */ + +#define TIM2_EGR_TG_SHIFT (6) +#define TIM2_EGR_TG_MASK (0x01U << TIM2_EGR_TG_SHIFT) +#define TIM2_EGR_TG(x) (((uint32_t)(((uint32_t)(x)) << TIM2_EGR_TG_SHIFT)) & TIM2_EGR_TG_MASK) + +#define TIM2_EGR_COMG_SHIFT (5) +#define TIM2_EGR_COMG_MASK (0x01U << TIM2_EGR_COMG_SHIFT) +#define TIM2_EGR_COMG(x) (((uint32_t)(((uint32_t)(x)) << TIM2_EGR_COMG_SHIFT)) & TIM2_EGR_COMG_MASK) + +#define TIM2_EGR_CC4G_SHIFT (4) +#define TIM2_EGR_CC4G_MASK (0x01U << TIM2_EGR_CC4G_SHIFT) +#define TIM2_EGR_CC4G(x) (((uint32_t)(((uint32_t)(x)) << TIM2_EGR_CC4G_SHIFT)) & TIM2_EGR_CC4G_MASK) + +#define TIM2_EGR_CC3G_SHIFT (3) +#define TIM2_EGR_CC3G_MASK (0x01U << TIM2_EGR_CC3G_SHIFT) +#define TIM2_EGR_CC3G(x) (((uint32_t)(((uint32_t)(x)) << TIM2_EGR_CC3G_SHIFT)) & TIM2_EGR_CC3G_MASK) + +#define TIM2_EGR_CC2G_SHIFT (2) +#define TIM2_EGR_CC2G_MASK (0x01U << TIM2_EGR_CC2G_SHIFT) +#define TIM2_EGR_CC2G(x) (((uint32_t)(((uint32_t)(x)) << TIM2_EGR_CC2G_SHIFT)) & TIM2_EGR_CC2G_MASK) + +#define TIM2_EGR_CC1G_SHIFT (1) +#define TIM2_EGR_CC1G_MASK (0x01U << TIM2_EGR_CC1G_SHIFT) +#define TIM2_EGR_CC1G(x) (((uint32_t)(((uint32_t)(x)) << TIM2_EGR_CC1G_SHIFT)) & TIM2_EGR_CC1G_MASK) + +#define TIM2_EGR_UG_SHIFT (0) +#define TIM2_EGR_UG_MASK (0x01U << TIM2_EGR_UG_SHIFT) +#define TIM2_EGR_UG(x) (((uint32_t)(((uint32_t)(x)) << TIM2_EGR_UG_SHIFT)) & TIM2_EGR_UG_MASK) + +/*! + * @brief TIM2_CCMR1 Register Bit Definition + */ + +#define TIM2_CCMR1_OC2CE_SHIFT (15) +#define TIM2_CCMR1_OC2CE_MASK (0x01U << TIM2_CCMR1_OC2CE_SHIFT) +#define TIM2_CCMR1_OC2CE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR1_OC2CE_SHIFT)) & TIM2_CCMR1_OC2CE_MASK) + +#define TIM2_CCMR1_OC2M_SHIFT (12) +#define TIM2_CCMR1_OC2M_MASK (0x7U << TIM2_CCMR1_OC2M_SHIFT) +#define TIM2_CCMR1_OC2M(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR1_OC2M_SHIFT)) & TIM2_CCMR1_OC2M_MASK) + +#define TIM2_CCMR1_OC2PE_SHIFT (11) +#define TIM2_CCMR1_OC2PE_MASK (0x01U << TIM2_CCMR1_OC2PE_SHIFT) +#define TIM2_CCMR1_OC2PE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR1_OC2PE_SHIFT)) & TIM2_CCMR1_OC2PE_MASK) + +#define TIM2_CCMR1_OC2FE_SHIFT (10) +#define TIM2_CCMR1_OC2FE_MASK (0x01U << TIM2_CCMR1_OC2FE_SHIFT) +#define TIM2_CCMR1_OC2FE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR1_OC2FE_SHIFT)) & TIM2_CCMR1_OC2FE_MASK) + +#define TIM2_CCMR1_CC2S_SHIFT (8) +#define TIM2_CCMR1_CC2S_MASK (0x3U << TIM2_CCMR1_CC2S_SHIFT) +#define TIM2_CCMR1_CC2S(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR1_CC2S_SHIFT)) & TIM2_CCMR1_CC2S_MASK) + +#define TIM2_CCMR1_OC1CE_SHIFT (7) +#define TIM2_CCMR1_OC1CE_MASK (0x01U << TIM2_CCMR1_OC1CE_SHIFT) +#define TIM2_CCMR1_OC1CE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR1_OC1CE_SHIFT)) & TIM2_CCMR1_OC1CE_MASK) + +#define TIM2_CCMR1_OC1M_SHIFT (4) +#define TIM2_CCMR1_OC1M_MASK (0x7U << TIM2_CCMR1_OC1M_SHIFT) +#define TIM2_CCMR1_OC1M(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR1_OC1M_SHIFT)) & TIM2_CCMR1_OC1M_MASK) + +#define TIM2_CCMR1_OC1PE_SHIFT (3) +#define TIM2_CCMR1_OC1PE_MASK (0x01U << TIM2_CCMR1_OC1PE_SHIFT) +#define TIM2_CCMR1_OC1PE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR1_OC1PE_SHIFT)) & TIM2_CCMR1_OC1PE_MASK) + +#define TIM2_CCMR1_OC1FE_SHIFT (2) +#define TIM2_CCMR1_OC1FE_MASK (0x01U << TIM2_CCMR1_OC1FE_SHIFT) +#define TIM2_CCMR1_OC1FE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR1_OC1FE_SHIFT)) & TIM2_CCMR1_OC1FE_MASK) + +#define TIM2_CCMR1_CC1S_SHIFT (0) +#define TIM2_CCMR1_CC1S_MASK (0x3U << TIM2_CCMR1_CC1S_SHIFT) +#define TIM2_CCMR1_CC1S(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR1_CC1S_SHIFT)) & TIM2_CCMR1_CC1S_MASK) + +/*! + * @brief TIM2_CCMR1 Register Bit Definition + */ + +#define TIM2_CCMR1_IC2F_SHIFT (12) +#define TIM2_CCMR1_IC2F_MASK (0xFU << TIM2_CCMR1_IC2F_SHIFT) +#define TIM2_CCMR1_IC2F(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR1_IC2F_SHIFT)) & TIM2_CCMR1_IC2F_MASK) + +#define TIM2_CCMR1_IC2PSC_SHIFT (10) +#define TIM2_CCMR1_IC2PSC_MASK (0x3U << TIM2_CCMR1_IC2PSC_SHIFT) +#define TIM2_CCMR1_IC2PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR1_IC2PSC_SHIFT)) & TIM2_CCMR1_IC2PSC_MASK) + +#define TIM2_CCMR1_CC2S_SHIFT (8) +#define TIM2_CCMR1_CC2S_MASK (0x3U << TIM2_CCMR1_CC2S_SHIFT) +#define TIM2_CCMR1_CC2S(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR1_CC2S_SHIFT)) & TIM2_CCMR1_CC2S_MASK) + +#define TIM2_CCMR1_IC1F_SHIFT (4) +#define TIM2_CCMR1_IC1F_MASK (0xFU << TIM2_CCMR1_IC1F_SHIFT) +#define TIM2_CCMR1_IC1F(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR1_IC1F_SHIFT)) & TIM2_CCMR1_IC1F_MASK) + +#define TIM2_CCMR1_IC1PSC_SHIFT (2) +#define TIM2_CCMR1_IC1PSC_MASK (0x3U << TIM2_CCMR1_IC1PSC_SHIFT) +#define TIM2_CCMR1_IC1PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR1_IC1PSC_SHIFT)) & TIM2_CCMR1_IC1PSC_MASK) + +#define TIM2_CCMR1_CC1S_SHIFT (0) +#define TIM2_CCMR1_CC1S_MASK (0x3U << TIM2_CCMR1_CC1S_SHIFT) +#define TIM2_CCMR1_CC1S(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR1_CC1S_SHIFT)) & TIM2_CCMR1_CC1S_MASK) + +/*! + * @brief TIM2_CCMR2 Register Bit Definition + */ + +#define TIM2_CCMR2_OC4CE_SHIFT (15) +#define TIM2_CCMR2_OC4CE_MASK (0x01U << TIM2_CCMR2_OC4CE_SHIFT) +#define TIM2_CCMR2_OC4CE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR2_OC4CE_SHIFT)) & TIM2_CCMR2_OC4CE_MASK) + +#define TIM2_CCMR2_OC4M_SHIFT (12) +#define TIM2_CCMR2_OC4M_MASK (0x7U << TIM2_CCMR2_OC4M_SHIFT) +#define TIM2_CCMR2_OC4M(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR2_OC4M_SHIFT)) & TIM2_CCMR2_OC4M_MASK) + +#define TIM2_CCMR2_OC4PE_SHIFT (11) +#define TIM2_CCMR2_OC4PE_MASK (0x01U << TIM2_CCMR2_OC4PE_SHIFT) +#define TIM2_CCMR2_OC4PE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR2_OC4PE_SHIFT)) & TIM2_CCMR2_OC4PE_MASK) + +#define TIM2_CCMR2_OC4FE_SHIFT (10) +#define TIM2_CCMR2_OC4FE_MASK (0x01U << TIM2_CCMR2_OC4FE_SHIFT) +#define TIM2_CCMR2_OC4FE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR2_OC4FE_SHIFT)) & TIM2_CCMR2_OC4FE_MASK) + +#define TIM2_CCMR2_CC4S_SHIFT (8) +#define TIM2_CCMR2_CC4S_MASK (0x3U << TIM2_CCMR2_CC4S_SHIFT) +#define TIM2_CCMR2_CC4S(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR2_CC4S_SHIFT)) & TIM2_CCMR2_CC4S_MASK) + +#define TIM2_CCMR2_OC3CE_SHIFT (7) +#define TIM2_CCMR2_OC3CE_MASK (0x01U << TIM2_CCMR2_OC3CE_SHIFT) +#define TIM2_CCMR2_OC3CE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR2_OC3CE_SHIFT)) & TIM2_CCMR2_OC3CE_MASK) + +#define TIM2_CCMR2_OC3M_SHIFT (4) +#define TIM2_CCMR2_OC3M_MASK (0x7U << TIM2_CCMR2_OC3M_SHIFT) +#define TIM2_CCMR2_OC3M(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR2_OC3M_SHIFT)) & TIM2_CCMR2_OC3M_MASK) + +#define TIM2_CCMR2_OC3PE_SHIFT (3) +#define TIM2_CCMR2_OC3PE_MASK (0x01U << TIM2_CCMR2_OC3PE_SHIFT) +#define TIM2_CCMR2_OC3PE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR2_OC3PE_SHIFT)) & TIM2_CCMR2_OC3PE_MASK) + +#define TIM2_CCMR2_OC3FE_SHIFT (2) +#define TIM2_CCMR2_OC3FE_MASK (0x01U << TIM2_CCMR2_OC3FE_SHIFT) +#define TIM2_CCMR2_OC3FE(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR2_OC3FE_SHIFT)) & TIM2_CCMR2_OC3FE_MASK) + +#define TIM2_CCMR2_CC3S_SHIFT (0) +#define TIM2_CCMR2_CC3S_MASK (0x3U << TIM2_CCMR2_CC3S_SHIFT) +#define TIM2_CCMR2_CC3S(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR2_CC3S_SHIFT)) & TIM2_CCMR2_CC3S_MASK) + +/*! + * @brief TIM2_CCMR2 Register Bit Definition + */ + +#define TIM2_CCMR2_IC4F_SHIFT (12) +#define TIM2_CCMR2_IC4F_MASK (0xFU << TIM2_CCMR2_IC4F_SHIFT) +#define TIM2_CCMR2_IC4F(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR2_IC4F_SHIFT)) & TIM2_CCMR2_IC4F_MASK) + +#define TIM2_CCMR2_IC4PSC_SHIFT (10) +#define TIM2_CCMR2_IC4PSC_MASK (0x3U << TIM2_CCMR2_IC4PSC_SHIFT) +#define TIM2_CCMR2_IC4PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR2_IC4PSC_SHIFT)) & TIM2_CCMR2_IC4PSC_MASK) + +#define TIM2_CCMR2_CC4S_SHIFT (8) +#define TIM2_CCMR2_CC4S_MASK (0x3U << TIM2_CCMR2_CC4S_SHIFT) +#define TIM2_CCMR2_CC4S(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR2_CC4S_SHIFT)) & TIM2_CCMR2_CC4S_MASK) + +#define TIM2_CCMR2_IC3F_SHIFT (4) +#define TIM2_CCMR2_IC3F_MASK (0xFU << TIM2_CCMR2_IC3F_SHIFT) +#define TIM2_CCMR2_IC3F(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR2_IC3F_SHIFT)) & TIM2_CCMR2_IC3F_MASK) + +#define TIM2_CCMR2_IC3PSC_SHIFT (2) +#define TIM2_CCMR2_IC3PSC_MASK (0x3U << TIM2_CCMR2_IC3PSC_SHIFT) +#define TIM2_CCMR2_IC3PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR2_IC3PSC_SHIFT)) & TIM2_CCMR2_IC3PSC_MASK) + +#define TIM2_CCMR2_CC3S_SHIFT (0) +#define TIM2_CCMR2_CC3S_MASK (0x3U << TIM2_CCMR2_CC3S_SHIFT) +#define TIM2_CCMR2_CC3S(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCMR2_CC3S_SHIFT)) & TIM2_CCMR2_CC3S_MASK) + +/*! + * @brief TIM2_CCER Register Bit Definition + */ + +#define TIM2_CCER_CC4NP_SHIFT (15) +#define TIM2_CCER_CC4NP_MASK (0x01U << TIM2_CCER_CC4NP_SHIFT) +#define TIM2_CCER_CC4NP(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCER_CC4NP_SHIFT)) & TIM2_CCER_CC4NP_MASK) + +#define TIM2_CCER_CC4P_SHIFT (13) +#define TIM2_CCER_CC4P_MASK (0x01U << TIM2_CCER_CC4P_SHIFT) +#define TIM2_CCER_CC4P(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCER_CC4P_SHIFT)) & TIM2_CCER_CC4P_MASK) + +#define TIM2_CCER_CC4E_SHIFT (12) +#define TIM2_CCER_CC4E_MASK (0x01U << TIM2_CCER_CC4E_SHIFT) +#define TIM2_CCER_CC4E(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCER_CC4E_SHIFT)) & TIM2_CCER_CC4E_MASK) + +#define TIM2_CCER_CC3NP_SHIFT (11) +#define TIM2_CCER_CC3NP_MASK (0x01U << TIM2_CCER_CC3NP_SHIFT) +#define TIM2_CCER_CC3NP(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCER_CC3NP_SHIFT)) & TIM2_CCER_CC3NP_MASK) + +#define TIM2_CCER_CC3P_SHIFT (9) +#define TIM2_CCER_CC3P_MASK (0x01U << TIM2_CCER_CC3P_SHIFT) +#define TIM2_CCER_CC3P(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCER_CC3P_SHIFT)) & TIM2_CCER_CC3P_MASK) + +#define TIM2_CCER_CC3E_SHIFT (8) +#define TIM2_CCER_CC3E_MASK (0x01U << TIM2_CCER_CC3E_SHIFT) +#define TIM2_CCER_CC3E(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCER_CC3E_SHIFT)) & TIM2_CCER_CC3E_MASK) + +#define TIM2_CCER_CC2NP_SHIFT (7) +#define TIM2_CCER_CC2NP_MASK (0x01U << TIM2_CCER_CC2NP_SHIFT) +#define TIM2_CCER_CC2NP(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCER_CC2NP_SHIFT)) & TIM2_CCER_CC2NP_MASK) + +#define TIM2_CCER_CC2P_SHIFT (5) +#define TIM2_CCER_CC2P_MASK (0x01U << TIM2_CCER_CC2P_SHIFT) +#define TIM2_CCER_CC2P(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCER_CC2P_SHIFT)) & TIM2_CCER_CC2P_MASK) + +#define TIM2_CCER_CC2E_SHIFT (4) +#define TIM2_CCER_CC2E_MASK (0x01U << TIM2_CCER_CC2E_SHIFT) +#define TIM2_CCER_CC2E(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCER_CC2E_SHIFT)) & TIM2_CCER_CC2E_MASK) + +#define TIM2_CCER_CC1NP_SHIFT (3) +#define TIM2_CCER_CC1NP_MASK (0x01U << TIM2_CCER_CC1NP_SHIFT) +#define TIM2_CCER_CC1NP(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCER_CC1NP_SHIFT)) & TIM2_CCER_CC1NP_MASK) + +#define TIM2_CCER_CC1P_SHIFT (1) +#define TIM2_CCER_CC1P_MASK (0x01U << TIM2_CCER_CC1P_SHIFT) +#define TIM2_CCER_CC1P(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCER_CC1P_SHIFT)) & TIM2_CCER_CC1P_MASK) + +#define TIM2_CCER_CC1E_SHIFT (0) +#define TIM2_CCER_CC1E_MASK (0x01U << TIM2_CCER_CC1E_SHIFT) +#define TIM2_CCER_CC1E(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCER_CC1E_SHIFT)) & TIM2_CCER_CC1E_MASK) + +/*! + * @brief TIM2_CNT Register Bit Definition + */ + +#define TIM2_CNT_CNT_SHIFT (0) +#define TIM2_CNT_CNT_MASK (0xFFFFU << TIM2_CNT_CNT_SHIFT) +#define TIM2_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CNT_CNT_SHIFT)) & TIM2_CNT_CNT_MASK) + +/*! + * @brief TIM2_PSC Register Bit Definition + */ + +#define TIM2_PSC_PSC_SHIFT (0) +#define TIM2_PSC_PSC_MASK (0xFFFFU << TIM2_PSC_PSC_SHIFT) +#define TIM2_PSC_PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM2_PSC_PSC_SHIFT)) & TIM2_PSC_PSC_MASK) + +/*! + * @brief TIM2_ARR Register Bit Definition + */ + +#define TIM2_ARR_ARR_SHIFT (0) +#define TIM2_ARR_ARR_MASK (0xFFFFU << TIM2_ARR_ARR_SHIFT) +#define TIM2_ARR_ARR(x) (((uint32_t)(((uint32_t)(x)) << TIM2_ARR_ARR_SHIFT)) & TIM2_ARR_ARR_MASK) + +/*! + * @brief TIM2_CCR Register Bit Definition + */ + +#define TIM2_CCR_CCR_SHIFT (0) +#define TIM2_CCR_CCR_MASK (0xFFFFU << TIM2_CCR_CCR_SHIFT) +#define TIM2_CCR_CCR(x) (((uint32_t)(((uint32_t)(x)) << TIM2_CCR_CCR_SHIFT)) & TIM2_CCR_CCR_MASK) + +/*! + * @brief TIM2_DCR Register Bit Definition + */ + +#define TIM2_DCR_DBL_SHIFT (8) +#define TIM2_DCR_DBL_MASK (0x1FU << TIM2_DCR_DBL_SHIFT) +#define TIM2_DCR_DBL(x) (((uint32_t)(((uint32_t)(x)) << TIM2_DCR_DBL_SHIFT)) & TIM2_DCR_DBL_MASK) + +#define TIM2_DCR_DBA_SHIFT (0) +#define TIM2_DCR_DBA_MASK (0x1FU << TIM2_DCR_DBA_SHIFT) +#define TIM2_DCR_DBA(x) (((uint32_t)(((uint32_t)(x)) << TIM2_DCR_DBA_SHIFT)) & TIM2_DCR_DBA_MASK) + +/*! + * @brief TIM2_DMAR Register Bit Definition + */ + +#define TIM2_DMAR_DMAB_SHIFT (0) +#define TIM2_DMAR_DMAB_MASK (0xFFFFU << TIM2_DMAR_DMAB_SHIFT) +#define TIM2_DMAR_DMAB(x) (((uint32_t)(((uint32_t)(x)) << TIM2_DMAR_DMAB_SHIFT)) & TIM2_DMAR_DMAB_MASK) + +/*! + * @brief TIM2_OR Register Bit Definition + */ + +#define TIM2_OR_TI4RMP_SHIFT (6) +#define TIM2_OR_TI4RMP_MASK (0x3U << TIM2_OR_TI4RMP_SHIFT) +#define TIM2_OR_TI4RMP(x) (((uint32_t)(((uint32_t)(x)) << TIM2_OR_TI4RMP_SHIFT)) & TIM2_OR_TI4RMP_MASK) + +#define TIM2_OR_ETRRMP_SHIFT (0) +#define TIM2_OR_ETRRMP_MASK (0x7U << TIM2_OR_ETRRMP_SHIFT) +#define TIM2_OR_ETRRMP(x) (((uint32_t)(((uint32_t)(x)) << TIM2_OR_ETRRMP_SHIFT)) & TIM2_OR_ETRRMP_MASK) + +/*! + * @} + */ /* end of group TIM2_Register_Masks */ +/****************************************************************************** + *TIM2 Instance +*******************************************************************************/ + +#define TIM2 ((TIM2_Type*)TIM2_BASE) +#define TIM5 ((TIM2_Type*)TIM5_BASE) + +/*! + * @} + */ /* end of group TIM2_Peripheral_Access_Layer */ + +/*! + * @addtogroup TIM3_Peripheral_Access_Layer TIM3 Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * TIM3 Type + ******************************************************************************/ +typedef struct { + __IO uint32_t CR1; ///< Control Register 1 offset: 0x00 + __IO uint32_t CR2; ///< Control Register 2 offset: 0x04 + __IO uint32_t SMCR; ///< Slave Mode Control Register offset: 0x08 + __IO uint32_t DIER; ///< DMA/Interrupt Enable Register offset: 0x0C + __IO uint32_t SR; ///< status register offset: 0x10 + __IO uint32_t EGR; ///< event generation register offset: 0x14 + __IO uint32_t CCMR1; ///< Capture/Compare Mode Register 1 offset: 0x18 + __IO uint32_t CCMR2; ///< Capture/Compare Mode Register 2 offset: 0x1C + __IO uint32_t CCER; ///< Capture/Compare Enable Register offset: 0x20 + __IO uint32_t CNT; ///< counter offset: 0x24 + __IO uint32_t PSC; ///< Prescaler offset: 0x28 + __IO uint32_t ARR; ///< autoload register offset: 0x2C + __IO uint32_t Reserved51[1]; ///< Reserved + __IO uint32_t CCR[4]; ///< Capture/Compare Register 1 offset: 0x34 + __IO uint32_t Reserved52[1]; ///< Reserved + __IO uint32_t DCR; ///< DMA Control Register offset: 0x48 + __IO uint32_t DMAR; ///< DMA address for continuous mode offset: 0x4C +} TIM3_Type; + +/******************************************************************************* + * TIM3 Type + ******************************************************************************/ + +/*! + * @addtogroup TIM3_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief TIM3_CR1 Register Bit Definition + */ + +#define TIM3_CR1_CKD_SHIFT (8) +#define TIM3_CR1_CKD_MASK (0x3U << TIM3_CR1_CKD_SHIFT) +#define TIM3_CR1_CKD(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CR1_CKD_SHIFT)) & TIM3_CR1_CKD_MASK) + +#define TIM3_CR1_ARPE_SHIFT (7) +#define TIM3_CR1_ARPE_MASK (0x01U << TIM3_CR1_ARPE_SHIFT) +#define TIM3_CR1_ARPE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CR1_ARPE_SHIFT)) & TIM3_CR1_ARPE_MASK) + +#define TIM3_CR1_CMS_SHIFT (5) +#define TIM3_CR1_CMS_MASK (0x3U << TIM3_CR1_CMS_SHIFT) +#define TIM3_CR1_CMS(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CR1_CMS_SHIFT)) & TIM3_CR1_CMS_MASK) + +#define TIM3_CR1_DIR_SHIFT (4) +#define TIM3_CR1_DIR_MASK (0x01U << TIM3_CR1_DIR_SHIFT) +#define TIM3_CR1_DIR(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CR1_DIR_SHIFT)) & TIM3_CR1_DIR_MASK) + +#define TIM3_CR1_OPM_SHIFT (3) +#define TIM3_CR1_OPM_MASK (0x01U << TIM3_CR1_OPM_SHIFT) +#define TIM3_CR1_OPM(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CR1_OPM_SHIFT)) & TIM3_CR1_OPM_MASK) + +#define TIM3_CR1_URS_SHIFT (2) +#define TIM3_CR1_URS_MASK (0x01U << TIM3_CR1_URS_SHIFT) +#define TIM3_CR1_URS(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CR1_URS_SHIFT)) & TIM3_CR1_URS_MASK) + +#define TIM3_CR1_UDIS_SHIFT (1) +#define TIM3_CR1_UDIS_MASK (0x01U << TIM3_CR1_UDIS_SHIFT) +#define TIM3_CR1_UDIS(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CR1_UDIS_SHIFT)) & TIM3_CR1_UDIS_MASK) + +#define TIM3_CR1_CEN_SHIFT (0) +#define TIM3_CR1_CEN_MASK (0x01U << TIM3_CR1_CEN_SHIFT) +#define TIM3_CR1_CEN(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CR1_CEN_SHIFT)) & TIM3_CR1_CEN_MASK) + +/*! + * @brief TIM3_CR2 Register Bit Definition + */ + +#define TIM3_CR2_TI1S_SHIFT (7) +#define TIM3_CR2_TI1S_MASK (0x01U << TIM3_CR2_TI1S_SHIFT) +#define TIM3_CR2_TI1S(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CR2_TI1S_SHIFT)) & TIM3_CR2_TI1S_MASK) + +#define TIM3_CR2_MMS_SHIFT (4) +#define TIM3_CR2_MMS_MASK (0x7U << TIM3_CR2_MMS_SHIFT) +#define TIM3_CR2_MMS(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CR2_MMS_SHIFT)) & TIM3_CR2_MMS_MASK) + +#define TIM3_CR2_CCDS_SHIFT (3) +#define TIM3_CR2_CCDS_MASK (0x01U << TIM3_CR2_CCDS_SHIFT) +#define TIM3_CR2_CCDS(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CR2_CCDS_SHIFT)) & TIM3_CR2_CCDS_MASK) + +/*! + * @brief TIM3_SMCR Register Bit Definition + */ + +#define TIM3_SMCR_ETP_SHIFT (15) +#define TIM3_SMCR_ETP_MASK (0x01U << TIM3_SMCR_ETP_SHIFT) +#define TIM3_SMCR_ETP(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SMCR_ETP_SHIFT)) & TIM3_SMCR_ETP_MASK) + +#define TIM3_SMCR_ECE_SHIFT (14) +#define TIM3_SMCR_ECE_MASK (0x01U << TIM3_SMCR_ECE_SHIFT) +#define TIM3_SMCR_ECE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SMCR_ECE_SHIFT)) & TIM3_SMCR_ECE_MASK) + +#define TIM3_SMCR_ETPS_SHIFT (12) +#define TIM3_SMCR_ETPS_MASK (0x3U << TIM3_SMCR_ETPS_SHIFT) +#define TIM3_SMCR_ETPS(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SMCR_ETPS_SHIFT)) & TIM3_SMCR_ETPS_MASK) + +#define TIM3_SMCR_ETF_SHIFT (8) +#define TIM3_SMCR_ETF_MASK (0xFU << TIM3_SMCR_ETF_SHIFT) +#define TIM3_SMCR_ETF(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SMCR_ETF_SHIFT)) & TIM3_SMCR_ETF_MASK) + +#define TIM3_SMCR_MSM_SHIFT (7) +#define TIM3_SMCR_MSM_MASK (0x01U << TIM3_SMCR_MSM_SHIFT) +#define TIM3_SMCR_MSM(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SMCR_MSM_SHIFT)) & TIM3_SMCR_MSM_MASK) + +#define TIM3_SMCR_TS_SHIFT (4) +#define TIM3_SMCR_TS_MASK (0x7U << TIM3_SMCR_TS_SHIFT) +#define TIM3_SMCR_TS(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SMCR_TS_SHIFT)) & TIM3_SMCR_TS_MASK) + +#define TIM3_SMCR_OCCS_SHIFT (3) +#define TIM3_SMCR_OCCS_MASK (0x01U << TIM3_SMCR_OCCS_SHIFT) +#define TIM3_SMCR_OCCS(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SMCR_OCCS_SHIFT)) & TIM3_SMCR_OCCS_MASK) + +#define TIM3_SMCR_SMS_SHIFT (0) +#define TIM3_SMCR_SMS_MASK (0x7U << TIM3_SMCR_SMS_SHIFT) +#define TIM3_SMCR_SMS(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SMCR_SMS_SHIFT)) & TIM3_SMCR_SMS_MASK) + +/*! + * @brief TIM3_DIER Register Bit Definition + */ + +#define TIM3_DIER_TDE_SHIFT (14) +#define TIM3_DIER_TDE_MASK (0x01U << TIM3_DIER_TDE_SHIFT) +#define TIM3_DIER_TDE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_DIER_TDE_SHIFT)) & TIM3_DIER_TDE_MASK) + +#define TIM3_DIER_CC4DE_SHIFT (12) +#define TIM3_DIER_CC4DE_MASK (0x01U << TIM3_DIER_CC4DE_SHIFT) +#define TIM3_DIER_CC4DE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_DIER_CC4DE_SHIFT)) & TIM3_DIER_CC4DE_MASK) + +#define TIM3_DIER_CC3DE_SHIFT (11) +#define TIM3_DIER_CC3DE_MASK (0x01U << TIM3_DIER_CC3DE_SHIFT) +#define TIM3_DIER_CC3DE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_DIER_CC3DE_SHIFT)) & TIM3_DIER_CC3DE_MASK) + +#define TIM3_DIER_CC2DE_SHIFT (10) +#define TIM3_DIER_CC2DE_MASK (0x01U << TIM3_DIER_CC2DE_SHIFT) +#define TIM3_DIER_CC2DE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_DIER_CC2DE_SHIFT)) & TIM3_DIER_CC2DE_MASK) + +#define TIM3_DIER_CC1DE_SHIFT (9) +#define TIM3_DIER_CC1DE_MASK (0x01U << TIM3_DIER_CC1DE_SHIFT) +#define TIM3_DIER_CC1DE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_DIER_CC1DE_SHIFT)) & TIM3_DIER_CC1DE_MASK) + +#define TIM3_DIER_UDE_SHIFT (8) +#define TIM3_DIER_UDE_MASK (0x01U << TIM3_DIER_UDE_SHIFT) +#define TIM3_DIER_UDE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_DIER_UDE_SHIFT)) & TIM3_DIER_UDE_MASK) + +#define TIM3_DIER_TIE_SHIFT (6) +#define TIM3_DIER_TIE_MASK (0x01U << TIM3_DIER_TIE_SHIFT) +#define TIM3_DIER_TIE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_DIER_TIE_SHIFT)) & TIM3_DIER_TIE_MASK) + +#define TIM3_DIER_CC4IE_SHIFT (4) +#define TIM3_DIER_CC4IE_MASK (0x01U << TIM3_DIER_CC4IE_SHIFT) +#define TIM3_DIER_CC4IE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_DIER_CC4IE_SHIFT)) & TIM3_DIER_CC4IE_MASK) + +#define TIM3_DIER_CC3IE_SHIFT (3) +#define TIM3_DIER_CC3IE_MASK (0x01U << TIM3_DIER_CC3IE_SHIFT) +#define TIM3_DIER_CC3IE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_DIER_CC3IE_SHIFT)) & TIM3_DIER_CC3IE_MASK) + +#define TIM3_DIER_CC2IE_SHIFT (2) +#define TIM3_DIER_CC2IE_MASK (0x01U << TIM3_DIER_CC2IE_SHIFT) +#define TIM3_DIER_CC2IE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_DIER_CC2IE_SHIFT)) & TIM3_DIER_CC2IE_MASK) + +#define TIM3_DIER_CC1IE_SHIFT (1) +#define TIM3_DIER_CC1IE_MASK (0x01U << TIM3_DIER_CC1IE_SHIFT) +#define TIM3_DIER_CC1IE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_DIER_CC1IE_SHIFT)) & TIM3_DIER_CC1IE_MASK) + +#define TIM3_DIER_UIE_SHIFT (0) +#define TIM3_DIER_UIE_MASK (0x01U << TIM3_DIER_UIE_SHIFT) +#define TIM3_DIER_UIE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_DIER_UIE_SHIFT)) & TIM3_DIER_UIE_MASK) + +/*! + * @brief TIM3_SR Register Bit Definition + */ + +#define TIM3_SR_CC4OF_SHIFT (12) +#define TIM3_SR_CC4OF_MASK (0x01U << TIM3_SR_CC4OF_SHIFT) +#define TIM3_SR_CC4OF(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SR_CC4OF_SHIFT)) & TIM3_SR_CC4OF_MASK) + +#define TIM3_SR_CC3OF_SHIFT (11) +#define TIM3_SR_CC3OF_MASK (0x01U << TIM3_SR_CC3OF_SHIFT) +#define TIM3_SR_CC3OF(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SR_CC3OF_SHIFT)) & TIM3_SR_CC3OF_MASK) + +#define TIM3_SR_CC2OF_SHIFT (10) +#define TIM3_SR_CC2OF_MASK (0x01U << TIM3_SR_CC2OF_SHIFT) +#define TIM3_SR_CC2OF(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SR_CC2OF_SHIFT)) & TIM3_SR_CC2OF_MASK) + +#define TIM3_SR_CC1OF_SHIFT (9) +#define TIM3_SR_CC1OF_MASK (0x01U << TIM3_SR_CC1OF_SHIFT) +#define TIM3_SR_CC1OF(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SR_CC1OF_SHIFT)) & TIM3_SR_CC1OF_MASK) + +#define TIM3_SR_TIF_SHIFT (6) +#define TIM3_SR_TIF_MASK (0x01U << TIM3_SR_TIF_SHIFT) +#define TIM3_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SR_TIF_SHIFT)) & TIM3_SR_TIF_MASK) + +#define TIM3_SR_CC4IF_SHIFT (4) +#define TIM3_SR_CC4IF_MASK (0x01U << TIM3_SR_CC4IF_SHIFT) +#define TIM3_SR_CC4IF(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SR_CC4IF_SHIFT)) & TIM3_SR_CC4IF_MASK) + +#define TIM3_SR_CC3IF_SHIFT (3) +#define TIM3_SR_CC3IF_MASK (0x01U << TIM3_SR_CC3IF_SHIFT) +#define TIM3_SR_CC3IF(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SR_CC3IF_SHIFT)) & TIM3_SR_CC3IF_MASK) + +#define TIM3_SR_CC2IF_SHIFT (2) +#define TIM3_SR_CC2IF_MASK (0x01U << TIM3_SR_CC2IF_SHIFT) +#define TIM3_SR_CC2IF(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SR_CC2IF_SHIFT)) & TIM3_SR_CC2IF_MASK) + +#define TIM3_SR_CC1IF_SHIFT (1) +#define TIM3_SR_CC1IF_MASK (0x01U << TIM3_SR_CC1IF_SHIFT) +#define TIM3_SR_CC1IF(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SR_CC1IF_SHIFT)) & TIM3_SR_CC1IF_MASK) + +#define TIM3_SR_UIF_SHIFT (0) +#define TIM3_SR_UIF_MASK (0x01U << TIM3_SR_UIF_SHIFT) +#define TIM3_SR_UIF(x) (((uint32_t)(((uint32_t)(x)) << TIM3_SR_UIF_SHIFT)) & TIM3_SR_UIF_MASK) + +/*! + * @brief TIM3_EGR Register Bit Definition + */ + +#define TIM3_EGR_TG_SHIFT (6) +#define TIM3_EGR_TG_MASK (0x01U << TIM3_EGR_TG_SHIFT) +#define TIM3_EGR_TG(x) (((uint32_t)(((uint32_t)(x)) << TIM3_EGR_TG_SHIFT)) & TIM3_EGR_TG_MASK) + +#define TIM3_EGR_COMG_SHIFT (5) +#define TIM3_EGR_COMG_MASK (0x01U << TIM3_EGR_COMG_SHIFT) +#define TIM3_EGR_COMG(x) (((uint32_t)(((uint32_t)(x)) << TIM3_EGR_COMG_SHIFT)) & TIM3_EGR_COMG_MASK) + +#define TIM3_EGR_CC4G_SHIFT (4) +#define TIM3_EGR_CC4G_MASK (0x01U << TIM3_EGR_CC4G_SHIFT) +#define TIM3_EGR_CC4G(x) (((uint32_t)(((uint32_t)(x)) << TIM3_EGR_CC4G_SHIFT)) & TIM3_EGR_CC4G_MASK) + +#define TIM3_EGR_CC3G_SHIFT (3) +#define TIM3_EGR_CC3G_MASK (0x01U << TIM3_EGR_CC3G_SHIFT) +#define TIM3_EGR_CC3G(x) (((uint32_t)(((uint32_t)(x)) << TIM3_EGR_CC3G_SHIFT)) & TIM3_EGR_CC3G_MASK) + +#define TIM3_EGR_CC2G_SHIFT (2) +#define TIM3_EGR_CC2G_MASK (0x01U << TIM3_EGR_CC2G_SHIFT) +#define TIM3_EGR_CC2G(x) (((uint32_t)(((uint32_t)(x)) << TIM3_EGR_CC2G_SHIFT)) & TIM3_EGR_CC2G_MASK) + +#define TIM3_EGR_CC1G_SHIFT (1) +#define TIM3_EGR_CC1G_MASK (0x01U << TIM3_EGR_CC1G_SHIFT) +#define TIM3_EGR_CC1G(x) (((uint32_t)(((uint32_t)(x)) << TIM3_EGR_CC1G_SHIFT)) & TIM3_EGR_CC1G_MASK) + +#define TIM3_EGR_UG_SHIFT (0) +#define TIM3_EGR_UG_MASK (0x01U << TIM3_EGR_UG_SHIFT) +#define TIM3_EGR_UG(x) (((uint32_t)(((uint32_t)(x)) << TIM3_EGR_UG_SHIFT)) & TIM3_EGR_UG_MASK) + +/*! + * @brief TIM3_CCMR1 Register Bit Definition + */ + +#define TIM3_CCMR1_OC2CE_SHIFT (15) +#define TIM3_CCMR1_OC2CE_MASK (0x01U << TIM3_CCMR1_OC2CE_SHIFT) +#define TIM3_CCMR1_OC2CE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR1_OC2CE_SHIFT)) & TIM3_CCMR1_OC2CE_MASK) + +#define TIM3_CCMR1_OC2M_SHIFT (12) +#define TIM3_CCMR1_OC2M_MASK (0x7U << TIM3_CCMR1_OC2M_SHIFT) +#define TIM3_CCMR1_OC2M(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR1_OC2M_SHIFT)) & TIM3_CCMR1_OC2M_MASK) + +#define TIM3_CCMR1_OC2PE_SHIFT (11) +#define TIM3_CCMR1_OC2PE_MASK (0x01U << TIM3_CCMR1_OC2PE_SHIFT) +#define TIM3_CCMR1_OC2PE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR1_OC2PE_SHIFT)) & TIM3_CCMR1_OC2PE_MASK) + +#define TIM3_CCMR1_OC2FE_SHIFT (10) +#define TIM3_CCMR1_OC2FE_MASK (0x01U << TIM3_CCMR1_OC2FE_SHIFT) +#define TIM3_CCMR1_OC2FE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR1_OC2FE_SHIFT)) & TIM3_CCMR1_OC2FE_MASK) + +#define TIM3_CCMR1_CC2S_SHIFT (8) +#define TIM3_CCMR1_CC2S_MASK (0x3U << TIM3_CCMR1_CC2S_SHIFT) +#define TIM3_CCMR1_CC2S(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR1_CC2S_SHIFT)) & TIM3_CCMR1_CC2S_MASK) + +#define TIM3_CCMR1_OC1CE_SHIFT (7) +#define TIM3_CCMR1_OC1CE_MASK (0x01U << TIM3_CCMR1_OC1CE_SHIFT) +#define TIM3_CCMR1_OC1CE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR1_OC1CE_SHIFT)) & TIM3_CCMR1_OC1CE_MASK) + +#define TIM3_CCMR1_OC1M_SHIFT (4) +#define TIM3_CCMR1_OC1M_MASK (0x7U << TIM3_CCMR1_OC1M_SHIFT) +#define TIM3_CCMR1_OC1M(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR1_OC1M_SHIFT)) & TIM3_CCMR1_OC1M_MASK) + +#define TIM3_CCMR1_OC1PE_SHIFT (3) +#define TIM3_CCMR1_OC1PE_MASK (0x01U << TIM3_CCMR1_OC1PE_SHIFT) +#define TIM3_CCMR1_OC1PE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR1_OC1PE_SHIFT)) & TIM3_CCMR1_OC1PE_MASK) + +#define TIM3_CCMR1_OC1FE_SHIFT (2) +#define TIM3_CCMR1_OC1FE_MASK (0x01U << TIM3_CCMR1_OC1FE_SHIFT) +#define TIM3_CCMR1_OC1FE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR1_OC1FE_SHIFT)) & TIM3_CCMR1_OC1FE_MASK) + +#define TIM3_CCMR1_CC1S_SHIFT (0) +#define TIM3_CCMR1_CC1S_MASK (0x3U << TIM3_CCMR1_CC1S_SHIFT) +#define TIM3_CCMR1_CC1S(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR1_CC1S_SHIFT)) & TIM3_CCMR1_CC1S_MASK) + +/*! + * @brief TIM3_CCMR1 Register Bit Definition + */ + +#define TIM3_CCMR1_IC2F_SHIFT (12) +#define TIM3_CCMR1_IC2F_MASK (0xFU << TIM3_CCMR1_IC2F_SHIFT) +#define TIM3_CCMR1_IC2F(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR1_IC2F_SHIFT)) & TIM3_CCMR1_IC2F_MASK) + +#define TIM3_CCMR1_IC2PSC_SHIFT (10) +#define TIM3_CCMR1_IC2PSC_MASK (0x3U << TIM3_CCMR1_IC2PSC_SHIFT) +#define TIM3_CCMR1_IC2PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR1_IC2PSC_SHIFT)) & TIM3_CCMR1_IC2PSC_MASK) + +#define TIM3_CCMR1_CC2S_SHIFT (8) +#define TIM3_CCMR1_CC2S_MASK (0x3U << TIM3_CCMR1_CC2S_SHIFT) +#define TIM3_CCMR1_CC2S(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR1_CC2S_SHIFT)) & TIM3_CCMR1_CC2S_MASK) + +#define TIM3_CCMR1_IC1F_SHIFT (4) +#define TIM3_CCMR1_IC1F_MASK (0xFU << TIM3_CCMR1_IC1F_SHIFT) +#define TIM3_CCMR1_IC1F(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR1_IC1F_SHIFT)) & TIM3_CCMR1_IC1F_MASK) + +#define TIM3_CCMR1_IC1PSC_SHIFT (2) +#define TIM3_CCMR1_IC1PSC_MASK (0x3U << TIM3_CCMR1_IC1PSC_SHIFT) +#define TIM3_CCMR1_IC1PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR1_IC1PSC_SHIFT)) & TIM3_CCMR1_IC1PSC_MASK) + +#define TIM3_CCMR1_CC1S_SHIFT (0) +#define TIM3_CCMR1_CC1S_MASK (0x3U << TIM3_CCMR1_CC1S_SHIFT) +#define TIM3_CCMR1_CC1S(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR1_CC1S_SHIFT)) & TIM3_CCMR1_CC1S_MASK) + +/*! + * @brief TIM3_CCMR2 Register Bit Definition + */ + +#define TIM3_CCMR2_OC4CE_SHIFT (15) +#define TIM3_CCMR2_OC4CE_MASK (0x01U << TIM3_CCMR2_OC4CE_SHIFT) +#define TIM3_CCMR2_OC4CE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR2_OC4CE_SHIFT)) & TIM3_CCMR2_OC4CE_MASK) + +#define TIM3_CCMR2_OC4M_SHIFT (12) +#define TIM3_CCMR2_OC4M_MASK (0x7U << TIM3_CCMR2_OC4M_SHIFT) +#define TIM3_CCMR2_OC4M(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR2_OC4M_SHIFT)) & TIM3_CCMR2_OC4M_MASK) + +#define TIM3_CCMR2_OC4PE_SHIFT (11) +#define TIM3_CCMR2_OC4PE_MASK (0x01U << TIM3_CCMR2_OC4PE_SHIFT) +#define TIM3_CCMR2_OC4PE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR2_OC4PE_SHIFT)) & TIM3_CCMR2_OC4PE_MASK) + +#define TIM3_CCMR2_OC4FE_SHIFT (10) +#define TIM3_CCMR2_OC4FE_MASK (0x01U << TIM3_CCMR2_OC4FE_SHIFT) +#define TIM3_CCMR2_OC4FE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR2_OC4FE_SHIFT)) & TIM3_CCMR2_OC4FE_MASK) + +#define TIM3_CCMR2_CC4S_SHIFT (8) +#define TIM3_CCMR2_CC4S_MASK (0x3U << TIM3_CCMR2_CC4S_SHIFT) +#define TIM3_CCMR2_CC4S(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR2_CC4S_SHIFT)) & TIM3_CCMR2_CC4S_MASK) + +#define TIM3_CCMR2_OC3CE_SHIFT (7) +#define TIM3_CCMR2_OC3CE_MASK (0x01U << TIM3_CCMR2_OC3CE_SHIFT) +#define TIM3_CCMR2_OC3CE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR2_OC3CE_SHIFT)) & TIM3_CCMR2_OC3CE_MASK) + +#define TIM3_CCMR2_OC3M_SHIFT (4) +#define TIM3_CCMR2_OC3M_MASK (0x7U << TIM3_CCMR2_OC3M_SHIFT) +#define TIM3_CCMR2_OC3M(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR2_OC3M_SHIFT)) & TIM3_CCMR2_OC3M_MASK) + +#define TIM3_CCMR2_OC3PE_SHIFT (3) +#define TIM3_CCMR2_OC3PE_MASK (0x01U << TIM3_CCMR2_OC3PE_SHIFT) +#define TIM3_CCMR2_OC3PE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR2_OC3PE_SHIFT)) & TIM3_CCMR2_OC3PE_MASK) + +#define TIM3_CCMR2_OC3FE_SHIFT (2) +#define TIM3_CCMR2_OC3FE_MASK (0x01U << TIM3_CCMR2_OC3FE_SHIFT) +#define TIM3_CCMR2_OC3FE(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR2_OC3FE_SHIFT)) & TIM3_CCMR2_OC3FE_MASK) + +#define TIM3_CCMR2_CC3S_SHIFT (0) +#define TIM3_CCMR2_CC3S_MASK (0x3U << TIM3_CCMR2_CC3S_SHIFT) +#define TIM3_CCMR2_CC3S(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR2_CC3S_SHIFT)) & TIM3_CCMR2_CC3S_MASK) + +/*! + * @brief TIM3_CCMR2 Register Bit Definition + */ + +#define TIM3_CCMR2_IC4F_SHIFT (12) +#define TIM3_CCMR2_IC4F_MASK (0xFU << TIM3_CCMR2_IC4F_SHIFT) +#define TIM3_CCMR2_IC4F(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR2_IC4F_SHIFT)) & TIM3_CCMR2_IC4F_MASK) + +#define TIM3_CCMR2_IC4PSC_SHIFT (10) +#define TIM3_CCMR2_IC4PSC_MASK (0x3U << TIM3_CCMR2_IC4PSC_SHIFT) +#define TIM3_CCMR2_IC4PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR2_IC4PSC_SHIFT)) & TIM3_CCMR2_IC4PSC_MASK) + +#define TIM3_CCMR2_CC4S_SHIFT (8) +#define TIM3_CCMR2_CC4S_MASK (0x3U << TIM3_CCMR2_CC4S_SHIFT) +#define TIM3_CCMR2_CC4S(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR2_CC4S_SHIFT)) & TIM3_CCMR2_CC4S_MASK) + +#define TIM3_CCMR2_IC3F_SHIFT (4) +#define TIM3_CCMR2_IC3F_MASK (0xFU << TIM3_CCMR2_IC3F_SHIFT) +#define TIM3_CCMR2_IC3F(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR2_IC3F_SHIFT)) & TIM3_CCMR2_IC3F_MASK) + +#define TIM3_CCMR2_IC3PSC_SHIFT (2) +#define TIM3_CCMR2_IC3PSC_MASK (0x3U << TIM3_CCMR2_IC3PSC_SHIFT) +#define TIM3_CCMR2_IC3PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR2_IC3PSC_SHIFT)) & TIM3_CCMR2_IC3PSC_MASK) + +#define TIM3_CCMR2_CC3S_SHIFT (0) +#define TIM3_CCMR2_CC3S_MASK (0x3U << TIM3_CCMR2_CC3S_SHIFT) +#define TIM3_CCMR2_CC3S(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCMR2_CC3S_SHIFT)) & TIM3_CCMR2_CC3S_MASK) + +/*! + * @brief TIM3_CCER Register Bit Definition + */ + +#define TIM3_CCER_CC4NP_SHIFT (15) +#define TIM3_CCER_CC4NP_MASK (0x01U << TIM3_CCER_CC4NP_SHIFT) +#define TIM3_CCER_CC4NP(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCER_CC4NP_SHIFT)) & TIM3_CCER_CC4NP_MASK) + +#define TIM3_CCER_CC4P_SHIFT (13) +#define TIM3_CCER_CC4P_MASK (0x01U << TIM3_CCER_CC4P_SHIFT) +#define TIM3_CCER_CC4P(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCER_CC4P_SHIFT)) & TIM3_CCER_CC4P_MASK) + +#define TIM3_CCER_CC4E_SHIFT (12) +#define TIM3_CCER_CC4E_MASK (0x01U << TIM3_CCER_CC4E_SHIFT) +#define TIM3_CCER_CC4E(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCER_CC4E_SHIFT)) & TIM3_CCER_CC4E_MASK) + +#define TIM3_CCER_CC3NP_SHIFT (11) +#define TIM3_CCER_CC3NP_MASK (0x01U << TIM3_CCER_CC3NP_SHIFT) +#define TIM3_CCER_CC3NP(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCER_CC3NP_SHIFT)) & TIM3_CCER_CC3NP_MASK) + +#define TIM3_CCER_CC3P_SHIFT (9) +#define TIM3_CCER_CC3P_MASK (0x01U << TIM3_CCER_CC3P_SHIFT) +#define TIM3_CCER_CC3P(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCER_CC3P_SHIFT)) & TIM3_CCER_CC3P_MASK) + +#define TIM3_CCER_CC3E_SHIFT (8) +#define TIM3_CCER_CC3E_MASK (0x01U << TIM3_CCER_CC3E_SHIFT) +#define TIM3_CCER_CC3E(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCER_CC3E_SHIFT)) & TIM3_CCER_CC3E_MASK) + +#define TIM3_CCER_CC2NP_SHIFT (7) +#define TIM3_CCER_CC2NP_MASK (0x01U << TIM3_CCER_CC2NP_SHIFT) +#define TIM3_CCER_CC2NP(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCER_CC2NP_SHIFT)) & TIM3_CCER_CC2NP_MASK) + +#define TIM3_CCER_CC2P_SHIFT (5) +#define TIM3_CCER_CC2P_MASK (0x01U << TIM3_CCER_CC2P_SHIFT) +#define TIM3_CCER_CC2P(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCER_CC2P_SHIFT)) & TIM3_CCER_CC2P_MASK) + +#define TIM3_CCER_CC2E_SHIFT (4) +#define TIM3_CCER_CC2E_MASK (0x01U << TIM3_CCER_CC2E_SHIFT) +#define TIM3_CCER_CC2E(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCER_CC2E_SHIFT)) & TIM3_CCER_CC2E_MASK) + +#define TIM3_CCER_CC1NP_SHIFT (3) +#define TIM3_CCER_CC1NP_MASK (0x01U << TIM3_CCER_CC1NP_SHIFT) +#define TIM3_CCER_CC1NP(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCER_CC1NP_SHIFT)) & TIM3_CCER_CC1NP_MASK) + +#define TIM3_CCER_CC1P_SHIFT (1) +#define TIM3_CCER_CC1P_MASK (0x01U << TIM3_CCER_CC1P_SHIFT) +#define TIM3_CCER_CC1P(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCER_CC1P_SHIFT)) & TIM3_CCER_CC1P_MASK) + +#define TIM3_CCER_CC1E_SHIFT (0) +#define TIM3_CCER_CC1E_MASK (0x01U << TIM3_CCER_CC1E_SHIFT) +#define TIM3_CCER_CC1E(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCER_CC1E_SHIFT)) & TIM3_CCER_CC1E_MASK) + +/*! + * @brief TIM3_CNT Register Bit Definition + */ + +#define TIM3_CNT_CNT_SHIFT (0) +#define TIM3_CNT_CNT_MASK (0xFFFFU << TIM3_CNT_CNT_SHIFT) +#define TIM3_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CNT_CNT_SHIFT)) & TIM3_CNT_CNT_MASK) + +/*! + * @brief TIM3_PSC Register Bit Definition + */ + +#define TIM3_PSC_PSC_SHIFT (0) +#define TIM3_PSC_PSC_MASK (0xFFFFU << TIM3_PSC_PSC_SHIFT) +#define TIM3_PSC_PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM3_PSC_PSC_SHIFT)) & TIM3_PSC_PSC_MASK) + +/*! + * @brief TIM3_ARR Register Bit Definition + */ + +#define TIM3_ARR_ARR_SHIFT (0) +#define TIM3_ARR_ARR_MASK (0xFFFFU << TIM3_ARR_ARR_SHIFT) +#define TIM3_ARR_ARR(x) (((uint32_t)(((uint32_t)(x)) << TIM3_ARR_ARR_SHIFT)) & TIM3_ARR_ARR_MASK) + +/*! + * @brief TIM3_CCR Register Bit Definition + */ + +#define TIM3_CCR_CCR_SHIFT (0) +#define TIM3_CCR_CCR_MASK (0xFFFFU << TIM3_CCR_CCR_SHIFT) +#define TIM3_CCR_CCR(x) (((uint32_t)(((uint32_t)(x)) << TIM3_CCR_CCR_SHIFT)) & TIM3_CCR_CCR_MASK) + +/*! + * @brief TIM3_DCR Register Bit Definition + */ + +#define TIM3_DCR_DBL_SHIFT (8) +#define TIM3_DCR_DBL_MASK (0x1FU << TIM3_DCR_DBL_SHIFT) +#define TIM3_DCR_DBL(x) (((uint32_t)(((uint32_t)(x)) << TIM3_DCR_DBL_SHIFT)) & TIM3_DCR_DBL_MASK) + +#define TIM3_DCR_DBA_SHIFT (0) +#define TIM3_DCR_DBA_MASK (0x1FU << TIM3_DCR_DBA_SHIFT) +#define TIM3_DCR_DBA(x) (((uint32_t)(((uint32_t)(x)) << TIM3_DCR_DBA_SHIFT)) & TIM3_DCR_DBA_MASK) + +/*! + * @brief TIM3_DMAR Register Bit Definition + */ + +#define TIM3_DMAR_DMAB_SHIFT (0) +#define TIM3_DMAR_DMAB_MASK (0xFFFFU << TIM3_DMAR_DMAB_SHIFT) +#define TIM3_DMAR_DMAB(x) (((uint32_t)(((uint32_t)(x)) << TIM3_DMAR_DMAB_SHIFT)) & TIM3_DMAR_DMAB_MASK) + +/*! + * @} + */ /* end of group TIM3_Register_Masks */ +/****************************************************************************** + *TIM3 Instance +*******************************************************************************/ + +#define TIM3 ((TIM3_Type*)TIM3_BASE) +#define TIM4 ((TIM3_Type*)TIM4_BASE) + +/*! + * @} + */ /* end of group TIM3_Peripheral_Access_Layer */ + +/*! + * @addtogroup TIM6_Peripheral_Access_Layer TIM6 Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * TIM6 Type + ******************************************************************************/ +typedef struct { + __IO uint32_t CR1; ///< Control Register 1 offset: 0x00 + __IO uint32_t Reserved53[2]; ///< Reserved + __IO uint32_t DIER; ///< DMA/Interrupt Enable Register offset: 0x0C + __IO uint32_t SR; ///< status register offset: 0x10 + __IO uint32_t EGR; ///< event generation register offset: 0x14 + __IO uint32_t Reserved54[3]; ///< Reserved + __IO uint32_t CNT; ///< counter offset: 0x24 + __IO uint32_t PSC; ///< Prescaler offset: 0x28 + __IO uint32_t ARR; ///< autoload register offset: 0x2C +} TIM6_Type; + +/******************************************************************************* + * TIM6 Type + ******************************************************************************/ + +/*! + * @addtogroup TIM6_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief TIM6_CR1 Register Bit Definition + */ + +#define TIM6_CR1_ARPE_SHIFT (7) +#define TIM6_CR1_ARPE_MASK (0x01U << TIM6_CR1_ARPE_SHIFT) +#define TIM6_CR1_ARPE(x) (((uint32_t)(((uint32_t)(x)) << TIM6_CR1_ARPE_SHIFT)) & TIM6_CR1_ARPE_MASK) + +#define TIM6_CR1_OPM_SHIFT (3) +#define TIM6_CR1_OPM_MASK (0x01U << TIM6_CR1_OPM_SHIFT) +#define TIM6_CR1_OPM(x) (((uint32_t)(((uint32_t)(x)) << TIM6_CR1_OPM_SHIFT)) & TIM6_CR1_OPM_MASK) + +#define TIM6_CR1_URS_SHIFT (2) +#define TIM6_CR1_URS_MASK (0x01U << TIM6_CR1_URS_SHIFT) +#define TIM6_CR1_URS(x) (((uint32_t)(((uint32_t)(x)) << TIM6_CR1_URS_SHIFT)) & TIM6_CR1_URS_MASK) + +#define TIM6_CR1_UDIS_SHIFT (1) +#define TIM6_CR1_UDIS_MASK (0x01U << TIM6_CR1_UDIS_SHIFT) +#define TIM6_CR1_UDIS(x) (((uint32_t)(((uint32_t)(x)) << TIM6_CR1_UDIS_SHIFT)) & TIM6_CR1_UDIS_MASK) + +#define TIM6_CR1_CEN_SHIFT (0) +#define TIM6_CR1_CEN_MASK (0x01U << TIM6_CR1_CEN_SHIFT) +#define TIM6_CR1_CEN(x) (((uint32_t)(((uint32_t)(x)) << TIM6_CR1_CEN_SHIFT)) & TIM6_CR1_CEN_MASK) + +/*! + * @brief TIM6_DIER Register Bit Definition + */ + +#define TIM6_DIER_UDE_SHIFT (8) +#define TIM6_DIER_UDE_MASK (0x01U << TIM6_DIER_UDE_SHIFT) +#define TIM6_DIER_UDE(x) (((uint32_t)(((uint32_t)(x)) << TIM6_DIER_UDE_SHIFT)) & TIM6_DIER_UDE_MASK) + +#define TIM6_DIER_UIE_SHIFT (0) +#define TIM6_DIER_UIE_MASK (0x01U << TIM6_DIER_UIE_SHIFT) +#define TIM6_DIER_UIE(x) (((uint32_t)(((uint32_t)(x)) << TIM6_DIER_UIE_SHIFT)) & TIM6_DIER_UIE_MASK) + +/*! + * @brief TIM6_SR Register Bit Definition + */ + +#define TIM6_SR_UIF_SHIFT (0) +#define TIM6_SR_UIF_MASK (0x01U << TIM6_SR_UIF_SHIFT) +#define TIM6_SR_UIF(x) (((uint32_t)(((uint32_t)(x)) << TIM6_SR_UIF_SHIFT)) & TIM6_SR_UIF_MASK) + +/*! + * @brief TIM6_EGR Register Bit Definition + */ + +#define TIM6_EGR_UG_SHIFT (0) +#define TIM6_EGR_UG_MASK (0x01U << TIM6_EGR_UG_SHIFT) +#define TIM6_EGR_UG(x) (((uint32_t)(((uint32_t)(x)) << TIM6_EGR_UG_SHIFT)) & TIM6_EGR_UG_MASK) + +/*! + * @brief TIM6_CNT Register Bit Definition + */ + +#define TIM6_CNT_CNT_SHIFT (0) +#define TIM6_CNT_CNT_MASK (0xFFFFU << TIM6_CNT_CNT_SHIFT) +#define TIM6_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << TIM6_CNT_CNT_SHIFT)) & TIM6_CNT_CNT_MASK) + +/*! + * @brief TIM6_PSC Register Bit Definition + */ + +#define TIM6_PSC_PSC_SHIFT (0) +#define TIM6_PSC_PSC_MASK (0xFFFFU << TIM6_PSC_PSC_SHIFT) +#define TIM6_PSC_PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM6_PSC_PSC_SHIFT)) & TIM6_PSC_PSC_MASK) + +/*! + * @brief TIM6_ARR Register Bit Definition + */ + +#define TIM6_ARR_ARR_SHIFT (0) +#define TIM6_ARR_ARR_MASK (0xFFFFU << TIM6_ARR_ARR_SHIFT) +#define TIM6_ARR_ARR(x) (((uint32_t)(((uint32_t)(x)) << TIM6_ARR_ARR_SHIFT)) & TIM6_ARR_ARR_MASK) + +/*! + * @} + */ /* end of group TIM6_Register_Masks */ +/****************************************************************************** + *TIM6 Instance +*******************************************************************************/ + +#define TIM6 ((TIM6_Type*)TIM6_BASE) + +/*! + * @} + */ /* end of group TIM6_Peripheral_Access_Layer */ + + + + +/*! + * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * UART Type + ******************************************************************************/ +typedef struct { + __IO uint32_t TDR; ///< UART transmit data register offset: 0x00 + __IO uint32_t RDR; ///< UART receive data register offset: 0x04 + __IO uint32_t CSR; ///< UART current status register offset: 0x08 + __IO uint32_t ISR; ///< UART Interrupt Status Register offset: 0x0C + __IO uint32_t IER; ///< UART Interrupt Enable Register offset: 0x10 + __IO uint32_t ICR; ///< UART Interrupt Clear Register offset: 0x14 + __IO uint32_t GCR; ///< UART Global Control Register offset: 0x18 + __IO uint32_t CCR; ///< UART General Control Register offset: 0x1C + __IO uint32_t BRR; ///< UART Baud Rate Register offset: 0x20 + __IO uint32_t FRA; ///< UART Fractional Baud Rate Register offset: 0x24 + __IO uint32_t RXADDR; ///< UART receive address register offset: 0x28 + __IO uint32_t RXMASK; ///< UART Receive Mask Register offset: 0x2C + __IO uint32_t SCR; ///< UART SCR register offset: 0x30 + __IO uint32_t IDLR; ///< UART IDLE Data Length Register offset: 0x34 + __IO uint32_t ABRCR; ///< UART ABRCR Auto-Baud Rate Control Register offset: 0x38 + __IO uint32_t IRDA; ///< UART IRDA infrared function control register offset: 0x3C +} UART_Type; + +/******************************************************************************* + * UART Type + ******************************************************************************/ + +/*! + * @addtogroup UART_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief UART_TDR Register Bit Definition + */ + +#define UART_TDR_TXREG_SHIFT (0) +#define UART_TDR_TXREG_MASK (0x1FFU << UART_TDR_TXREG_SHIFT) +#define UART_TDR_TXREG(x) (((uint32_t)(((uint32_t)(x)) << UART_TDR_TXREG_SHIFT)) & UART_TDR_TXREG_MASK) + +/*! + * @brief UART_RDR Register Bit Definition + */ + +#define UART_RDR_RXREG_SHIFT (0) +#define UART_RDR_RXREG_MASK (0x1FFU << UART_RDR_RXREG_SHIFT) +#define UART_RDR_RXREG(x) (((uint32_t)(((uint32_t)(x)) << UART_RDR_RXREG_SHIFT)) & UART_RDR_RXREG_MASK) + +/*! + * @brief UART_CSR Register Bit Definition + */ + +#define UART_CSR_TXEPT_SHIFT (3) +#define UART_CSR_TXEPT_MASK (0x01U << UART_CSR_TXEPT_SHIFT) +#define UART_CSR_TXEPT(x) (((uint32_t)(((uint32_t)(x)) << UART_CSR_TXEPT_SHIFT)) & UART_CSR_TXEPT_MASK) + +#define UART_CSR_TXFULL_SHIFT (2) +#define UART_CSR_TXFULL_MASK (0x01U << UART_CSR_TXFULL_SHIFT) +#define UART_CSR_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_CSR_TXFULL_SHIFT)) & UART_CSR_TXFULL_MASK) + +#define UART_CSR_RXAVL_SHIFT (1) +#define UART_CSR_RXAVL_MASK (0x01U << UART_CSR_RXAVL_SHIFT) +#define UART_CSR_RXAVL(x) (((uint32_t)(((uint32_t)(x)) << UART_CSR_RXAVL_SHIFT)) & UART_CSR_RXAVL_MASK) + +#define UART_CSR_TXC_SHIFT (0) +#define UART_CSR_TXC_MASK (0x01U << UART_CSR_TXC_SHIFT) +#define UART_CSR_TXC(x) (((uint32_t)(((uint32_t)(x)) << UART_CSR_TXC_SHIFT)) & UART_CSR_TXC_MASK) + +/*! + * @brief UART_ISR Register Bit Definition + */ + +#define UART_ISR_ABRERRINTF_SHIFT (11) +#define UART_ISR_ABRERRINTF_MASK (0x01U << UART_ISR_ABRERRINTF_SHIFT) +#define UART_ISR_ABRERRINTF(x) (((uint32_t)(((uint32_t)(x)) << UART_ISR_ABRERRINTF_SHIFT)) & UART_ISR_ABRERRINTF_MASK) + +#define UART_ISR_ABRENDINTF_SHIFT (10) +#define UART_ISR_ABRENDINTF_MASK (0x01U << UART_ISR_ABRENDINTF_SHIFT) +#define UART_ISR_ABRENDINTF(x) (((uint32_t)(((uint32_t)(x)) << UART_ISR_ABRENDINTF_SHIFT)) & UART_ISR_ABRENDINTF_MASK) + +#define UART_ISR_RXIDLEINTF_SHIFT (9) +#define UART_ISR_RXIDLEINTF_MASK (0x01U << UART_ISR_RXIDLEINTF_SHIFT) +#define UART_ISR_RXIDLEINTF(x) (((uint32_t)(((uint32_t)(x)) << UART_ISR_RXIDLEINTF_SHIFT)) & UART_ISR_RXIDLEINTF_MASK) + +#define UART_ISR_RXB8INTF_SHIFT (8) +#define UART_ISR_RXB8INTF_MASK (0x01U << UART_ISR_RXB8INTF_SHIFT) +#define UART_ISR_RXB8INTF(x) (((uint32_t)(((uint32_t)(x)) << UART_ISR_RXB8INTF_SHIFT)) & UART_ISR_RXB8INTF_MASK) + +#define UART_ISR_TXBRKINTF_SHIFT (7) +#define UART_ISR_TXBRKINTF_MASK (0x01U << UART_ISR_TXBRKINTF_SHIFT) +#define UART_ISR_TXBRKINTF(x) (((uint32_t)(((uint32_t)(x)) << UART_ISR_TXBRKINTF_SHIFT)) & UART_ISR_TXBRKINTF_MASK) + +#define UART_ISR_RXBRKINTF_SHIFT (6) +#define UART_ISR_RXBRKINTF_MASK (0x01U << UART_ISR_RXBRKINTF_SHIFT) +#define UART_ISR_RXBRKINTF(x) (((uint32_t)(((uint32_t)(x)) << UART_ISR_RXBRKINTF_SHIFT)) & UART_ISR_RXBRKINTF_MASK) + +#define UART_ISR_RXFERRINTF_SHIFT (5) +#define UART_ISR_RXFERRINTF_MASK (0x01U << UART_ISR_RXFERRINTF_SHIFT) +#define UART_ISR_RXFERRINTF(x) (((uint32_t)(((uint32_t)(x)) << UART_ISR_RXFERRINTF_SHIFT)) & UART_ISR_RXFERRINTF_MASK) + +#define UART_ISR_RXPERRINTF_SHIFT (4) +#define UART_ISR_RXPERRINTF_MASK (0x01U << UART_ISR_RXPERRINTF_SHIFT) +#define UART_ISR_RXPERRINTF(x) (((uint32_t)(((uint32_t)(x)) << UART_ISR_RXPERRINTF_SHIFT)) & UART_ISR_RXPERRINTF_MASK) + +#define UART_ISR_RXOERRINTF_SHIFT (3) +#define UART_ISR_RXOERRINTF_MASK (0x01U << UART_ISR_RXOERRINTF_SHIFT) +#define UART_ISR_RXOERRINTF(x) (((uint32_t)(((uint32_t)(x)) << UART_ISR_RXOERRINTF_SHIFT)) & UART_ISR_RXOERRINTF_MASK) + +#define UART_ISR_TXCINTF_SHIFT (2) +#define UART_ISR_TXCINTF_MASK (0x01U << UART_ISR_TXCINTF_SHIFT) +#define UART_ISR_TXCINTF(x) (((uint32_t)(((uint32_t)(x)) << UART_ISR_TXCINTF_SHIFT)) & UART_ISR_TXCINTF_MASK) + +#define UART_ISR_RXINTF_SHIFT (1) +#define UART_ISR_RXINTF_MASK (0x01U << UART_ISR_RXINTF_SHIFT) +#define UART_ISR_RXINTF(x) (((uint32_t)(((uint32_t)(x)) << UART_ISR_RXINTF_SHIFT)) & UART_ISR_RXINTF_MASK) + +#define UART_ISR_TXINTF_SHIFT (0) +#define UART_ISR_TXINTF_MASK (0x01U << UART_ISR_TXINTF_SHIFT) +#define UART_ISR_TXINTF(x) (((uint32_t)(((uint32_t)(x)) << UART_ISR_TXINTF_SHIFT)) & UART_ISR_TXINTF_MASK) + +/*! + * @brief UART_IER Register Bit Definition + */ + +#define UART_IER_ABRERRIEN_SHIFT (11) +#define UART_IER_ABRERRIEN_MASK (0x01U << UART_IER_ABRERRIEN_SHIFT) +#define UART_IER_ABRERRIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_ABRERRIEN_SHIFT)) & UART_IER_ABRERRIEN_MASK) + +#define UART_IER_ABRENDIEN_SHIFT (10) +#define UART_IER_ABRENDIEN_MASK (0x01U << UART_IER_ABRENDIEN_SHIFT) +#define UART_IER_ABRENDIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_ABRENDIEN_SHIFT)) & UART_IER_ABRENDIEN_MASK) + +#define UART_IER_RXIDLEIEN_SHIFT (9) +#define UART_IER_RXIDLEIEN_MASK (0x01U << UART_IER_RXIDLEIEN_SHIFT) +#define UART_IER_RXIDLEIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_RXIDLEIEN_SHIFT)) & UART_IER_RXIDLEIEN_MASK) + +#define UART_IER_RXB8IEN_SHIFT (8) +#define UART_IER_RXB8IEN_MASK (0x01U << UART_IER_RXB8IEN_SHIFT) +#define UART_IER_RXB8IEN(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_RXB8IEN_SHIFT)) & UART_IER_RXB8IEN_MASK) + +#define UART_IER_TXBRKIEN_SHIFT (7) +#define UART_IER_TXBRKIEN_MASK (0x01U << UART_IER_TXBRKIEN_SHIFT) +#define UART_IER_TXBRKIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_TXBRKIEN_SHIFT)) & UART_IER_TXBRKIEN_MASK) + +#define UART_IER_RXBRKIEN_SHIFT (6) +#define UART_IER_RXBRKIEN_MASK (0x01U << UART_IER_RXBRKIEN_SHIFT) +#define UART_IER_RXBRKIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_RXBRKIEN_SHIFT)) & UART_IER_RXBRKIEN_MASK) + +#define UART_IER_RXFERRIEN_SHIFT (5) +#define UART_IER_RXFERRIEN_MASK (0x01U << UART_IER_RXFERRIEN_SHIFT) +#define UART_IER_RXFERRIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_RXFERRIEN_SHIFT)) & UART_IER_RXFERRIEN_MASK) + +#define UART_IER_RXPERRIEN_SHIFT (4) +#define UART_IER_RXPERRIEN_MASK (0x01U << UART_IER_RXPERRIEN_SHIFT) +#define UART_IER_RXPERRIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_RXPERRIEN_SHIFT)) & UART_IER_RXPERRIEN_MASK) + +#define UART_IER_RXOERRIEN_SHIFT (3) +#define UART_IER_RXOERRIEN_MASK (0x01U << UART_IER_RXOERRIEN_SHIFT) +#define UART_IER_RXOERRIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_RXOERRIEN_SHIFT)) & UART_IER_RXOERRIEN_MASK) + +#define UART_IER_TXCIEN_SHIFT (2) +#define UART_IER_TXCIEN_MASK (0x01U << UART_IER_TXCIEN_SHIFT) +#define UART_IER_TXCIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_TXCIEN_SHIFT)) & UART_IER_TXCIEN_MASK) + +#define UART_IER_RXIEN_SHIFT (1) +#define UART_IER_RXIEN_MASK (0x01U << UART_IER_RXIEN_SHIFT) +#define UART_IER_RXIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_RXIEN_SHIFT)) & UART_IER_RXIEN_MASK) + +#define UART_IER_TXIEN_SHIFT (0) +#define UART_IER_TXIEN_MASK (0x01U << UART_IER_TXIEN_SHIFT) +#define UART_IER_TXIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_TXIEN_SHIFT)) & UART_IER_TXIEN_MASK) + +/*! + * @brief UART_ICR Register Bit Definition + */ + +#define UART_ICR_ABRERRICLR_SHIFT (11) +#define UART_ICR_ABRERRICLR_MASK (0x01U << UART_ICR_ABRERRICLR_SHIFT) +#define UART_ICR_ABRERRICLR(x) (((uint32_t)(((uint32_t)(x)) << UART_ICR_ABRERRICLR_SHIFT)) & UART_ICR_ABRERRICLR_MASK) + +#define UART_ICR_ABRENDICLR_SHIFT (10) +#define UART_ICR_ABRENDICLR_MASK (0x01U << UART_ICR_ABRENDICLR_SHIFT) +#define UART_ICR_ABRENDICLR(x) (((uint32_t)(((uint32_t)(x)) << UART_ICR_ABRENDICLR_SHIFT)) & UART_ICR_ABRENDICLR_MASK) + +#define UART_ICR_RXIDLEICLR_SHIFT (9) +#define UART_ICR_RXIDLEICLR_MASK (0x01U << UART_ICR_RXIDLEICLR_SHIFT) +#define UART_ICR_RXIDLEICLR(x) (((uint32_t)(((uint32_t)(x)) << UART_ICR_RXIDLEICLR_SHIFT)) & UART_ICR_RXIDLEICLR_MASK) + +#define UART_ICR_RXB8ICLR_SHIFT (8) +#define UART_ICR_RXB8ICLR_MASK (0x01U << UART_ICR_RXB8ICLR_SHIFT) +#define UART_ICR_RXB8ICLR(x) (((uint32_t)(((uint32_t)(x)) << UART_ICR_RXB8ICLR_SHIFT)) & UART_ICR_RXB8ICLR_MASK) + +#define UART_ICR_TXBRKICLR_SHIFT (7) +#define UART_ICR_TXBRKICLR_MASK (0x01U << UART_ICR_TXBRKICLR_SHIFT) +#define UART_ICR_TXBRKICLR(x) (((uint32_t)(((uint32_t)(x)) << UART_ICR_TXBRKICLR_SHIFT)) & UART_ICR_TXBRKICLR_MASK) + +#define UART_ICR_RXBRKICLR_SHIFT (6) +#define UART_ICR_RXBRKICLR_MASK (0x01U << UART_ICR_RXBRKICLR_SHIFT) +#define UART_ICR_RXBRKICLR(x) (((uint32_t)(((uint32_t)(x)) << UART_ICR_RXBRKICLR_SHIFT)) & UART_ICR_RXBRKICLR_MASK) + +#define UART_ICR_RXFERRICLR_SHIFT (5) +#define UART_ICR_RXFERRICLR_MASK (0x01U << UART_ICR_RXFERRICLR_SHIFT) +#define UART_ICR_RXFERRICLR(x) (((uint32_t)(((uint32_t)(x)) << UART_ICR_RXFERRICLR_SHIFT)) & UART_ICR_RXFERRICLR_MASK) + +#define UART_ICR_RXPERRICLR_SHIFT (4) +#define UART_ICR_RXPERRICLR_MASK (0x01U << UART_ICR_RXPERRICLR_SHIFT) +#define UART_ICR_RXPERRICLR(x) (((uint32_t)(((uint32_t)(x)) << UART_ICR_RXPERRICLR_SHIFT)) & UART_ICR_RXPERRICLR_MASK) + +#define UART_ICR_RXOERRICLR_SHIFT (3) +#define UART_ICR_RXOERRICLR_MASK (0x01U << UART_ICR_RXOERRICLR_SHIFT) +#define UART_ICR_RXOERRICLR(x) (((uint32_t)(((uint32_t)(x)) << UART_ICR_RXOERRICLR_SHIFT)) & UART_ICR_RXOERRICLR_MASK) + +#define UART_ICR_TXCICLR_SHIFT (2) +#define UART_ICR_TXCICLR_MASK (0x01U << UART_ICR_TXCICLR_SHIFT) +#define UART_ICR_TXCICLR(x) (((uint32_t)(((uint32_t)(x)) << UART_ICR_TXCICLR_SHIFT)) & UART_ICR_TXCICLR_MASK) + +#define UART_ICR_RXICLR_SHIFT (1) +#define UART_ICR_RXICLR_MASK (0x01U << UART_ICR_RXICLR_SHIFT) +#define UART_ICR_RXICLR(x) (((uint32_t)(((uint32_t)(x)) << UART_ICR_RXICLR_SHIFT)) & UART_ICR_RXICLR_MASK) + +#define UART_ICR_TXICLR_SHIFT (0) +#define UART_ICR_TXICLR_MASK (0x01U << UART_ICR_TXICLR_SHIFT) +#define UART_ICR_TXICLR(x) (((uint32_t)(((uint32_t)(x)) << UART_ICR_TXICLR_SHIFT)) & UART_ICR_TXICLR_MASK) + +/*! + * @brief UART_GCR Register Bit Definition + */ + +#define UART_GCR_TXTOG_SHIFT (10) +#define UART_GCR_TXTOG_MASK (0x01U << UART_GCR_TXTOG_SHIFT) +#define UART_GCR_TXTOG(x) (((uint32_t)(((uint32_t)(x)) << UART_GCR_TXTOG_SHIFT)) & UART_GCR_TXTOG_MASK) + +#define UART_GCR_RXTOG_SHIFT (9) +#define UART_GCR_RXTOG_MASK (0x01U << UART_GCR_RXTOG_SHIFT) +#define UART_GCR_RXTOG(x) (((uint32_t)(((uint32_t)(x)) << UART_GCR_RXTOG_SHIFT)) & UART_GCR_RXTOG_MASK) + +#define UART_GCR_SWAP_SHIFT (8) +#define UART_GCR_SWAP_MASK (0x01U << UART_GCR_SWAP_SHIFT) +#define UART_GCR_SWAP(x) (((uint32_t)(((uint32_t)(x)) << UART_GCR_SWAP_SHIFT)) & UART_GCR_SWAP_MASK) + +#define UART_GCR_SELB8_SHIFT (7) +#define UART_GCR_SELB8_MASK (0x01U << UART_GCR_SELB8_SHIFT) +#define UART_GCR_SELB8(x) (((uint32_t)(((uint32_t)(x)) << UART_GCR_SELB8_SHIFT)) & UART_GCR_SELB8_MASK) + +#define UART_GCR_TXEN_SHIFT (4) +#define UART_GCR_TXEN_MASK (0x01U << UART_GCR_TXEN_SHIFT) +#define UART_GCR_TXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_GCR_TXEN_SHIFT)) & UART_GCR_TXEN_MASK) + +#define UART_GCR_RXEN_SHIFT (3) +#define UART_GCR_RXEN_MASK (0x01U << UART_GCR_RXEN_SHIFT) +#define UART_GCR_RXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_GCR_RXEN_SHIFT)) & UART_GCR_RXEN_MASK) + +#define UART_GCR_AUTOFLOWEN_SHIFT (2) +#define UART_GCR_AUTOFLOWEN_MASK (0x01U << UART_GCR_AUTOFLOWEN_SHIFT) +#define UART_GCR_AUTOFLOWEN(x) (((uint32_t)(((uint32_t)(x)) << UART_GCR_AUTOFLOWEN_SHIFT)) & UART_GCR_AUTOFLOWEN_MASK) + +#define UART_GCR_DMAMODE_SHIFT (1) +#define UART_GCR_DMAMODE_MASK (0x01U << UART_GCR_DMAMODE_SHIFT) +#define UART_GCR_DMAMODE(x) (((uint32_t)(((uint32_t)(x)) << UART_GCR_DMAMODE_SHIFT)) & UART_GCR_DMAMODE_MASK) + +#define UART_GCR_UARTEN_SHIFT (0) +#define UART_GCR_UARTEN_MASK (0x01U << UART_GCR_UARTEN_SHIFT) +#define UART_GCR_UARTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_GCR_UARTEN_SHIFT)) & UART_GCR_UARTEN_MASK) + +/*! + * @brief UART_CCR Register Bit Definition + */ + +#define UART_CCR_LIN_SHIFT (14) +#define UART_CCR_LIN_MASK (0x01U << UART_CCR_LIN_SHIFT) +#define UART_CCR_LIN(x) (((uint32_t)(((uint32_t)(x)) << UART_CCR_LIN_SHIFT)) & UART_CCR_LIN_MASK) + +#define UART_CCR_WAKE_SHIFT (13) +#define UART_CCR_WAKE_MASK (0x01U << UART_CCR_WAKE_SHIFT) +#define UART_CCR_WAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_CCR_WAKE_SHIFT)) & UART_CCR_WAKE_MASK) + +#define UART_CCR_RWU_SHIFT (12) +#define UART_CCR_RWU_MASK (0x01U << UART_CCR_RWU_SHIFT) +#define UART_CCR_RWU(x) (((uint32_t)(((uint32_t)(x)) << UART_CCR_RWU_SHIFT)) & UART_CCR_RWU_MASK) + +#define UART_CCR_B8EN_SHIFT (11) +#define UART_CCR_B8EN_MASK (0x01U << UART_CCR_B8EN_SHIFT) +#define UART_CCR_B8EN(x) (((uint32_t)(((uint32_t)(x)) << UART_CCR_B8EN_SHIFT)) & UART_CCR_B8EN_MASK) + +#define UART_CCR_B8TOG_SHIFT (10) +#define UART_CCR_B8TOG_MASK (0x01U << UART_CCR_B8TOG_SHIFT) +#define UART_CCR_B8TOG(x) (((uint32_t)(((uint32_t)(x)) << UART_CCR_B8TOG_SHIFT)) & UART_CCR_B8TOG_MASK) + +#define UART_CCR_B8POL_SHIFT (9) +#define UART_CCR_B8POL_MASK (0x01U << UART_CCR_B8POL_SHIFT) +#define UART_CCR_B8POL(x) (((uint32_t)(((uint32_t)(x)) << UART_CCR_B8POL_SHIFT)) & UART_CCR_B8POL_MASK) + +#define UART_CCR_B8TXD_SHIFT (8) +#define UART_CCR_B8TXD_MASK (0x01U << UART_CCR_B8TXD_SHIFT) +#define UART_CCR_B8TXD(x) (((uint32_t)(((uint32_t)(x)) << UART_CCR_B8TXD_SHIFT)) & UART_CCR_B8TXD_MASK) + +#define UART_CCR_B8RXD_SHIFT (7) +#define UART_CCR_B8RXD_MASK (0x01U << UART_CCR_B8RXD_SHIFT) +#define UART_CCR_B8RXD(x) (((uint32_t)(((uint32_t)(x)) << UART_CCR_B8RXD_SHIFT)) & UART_CCR_B8RXD_MASK) + +#define UART_CCR_SPB1_SHIFT (6) +#define UART_CCR_SPB1_MASK (0x01U << UART_CCR_SPB1_SHIFT) +#define UART_CCR_SPB1(x) (((uint32_t)(((uint32_t)(x)) << UART_CCR_SPB1_SHIFT)) & UART_CCR_SPB1_MASK) + +#define UART_CCR_CHAR_SHIFT (4) +#define UART_CCR_CHAR_MASK (0x3U << UART_CCR_CHAR_SHIFT) +#define UART_CCR_CHAR(x) (((uint32_t)(((uint32_t)(x)) << UART_CCR_CHAR_SHIFT)) & UART_CCR_CHAR_MASK) + +#define UART_CCR_BRK_SHIFT (3) +#define UART_CCR_BRK_MASK (0x01U << UART_CCR_BRK_SHIFT) +#define UART_CCR_BRK(x) (((uint32_t)(((uint32_t)(x)) << UART_CCR_BRK_SHIFT)) & UART_CCR_BRK_MASK) + +#define UART_CCR_SPB0_SHIFT (2) +#define UART_CCR_SPB0_MASK (0x01U << UART_CCR_SPB0_SHIFT) +#define UART_CCR_SPB0(x) (((uint32_t)(((uint32_t)(x)) << UART_CCR_SPB0_SHIFT)) & UART_CCR_SPB0_MASK) + +#define UART_CCR_PSEL_SHIFT (1) +#define UART_CCR_PSEL_MASK (0x01U << UART_CCR_PSEL_SHIFT) +#define UART_CCR_PSEL(x) (((uint32_t)(((uint32_t)(x)) << UART_CCR_PSEL_SHIFT)) & UART_CCR_PSEL_MASK) + +#define UART_CCR_PEN_SHIFT (0) +#define UART_CCR_PEN_MASK (0x01U << UART_CCR_PEN_SHIFT) +#define UART_CCR_PEN(x) (((uint32_t)(((uint32_t)(x)) << UART_CCR_PEN_SHIFT)) & UART_CCR_PEN_MASK) + +/*! + * @brief UART_BRR Register Bit Definition + */ + +#define UART_BRR_DIVMANTISSA_SHIFT (0) +#define UART_BRR_DIVMANTISSA_MASK (0xFFFFU << UART_BRR_DIVMANTISSA_SHIFT) +#define UART_BRR_DIVMANTISSA(x) (((uint32_t)(((uint32_t)(x)) << UART_BRR_DIVMANTISSA_SHIFT)) & UART_BRR_DIVMANTISSA_MASK) + +/*! + * @brief UART_FRA Register Bit Definition + */ + +#define UART_FRA_DIVFRACTION_SHIFT (0) +#define UART_FRA_DIVFRACTION_MASK (0xFU << UART_FRA_DIVFRACTION_SHIFT) +#define UART_FRA_DIVFRACTION(x) (((uint32_t)(((uint32_t)(x)) << UART_FRA_DIVFRACTION_SHIFT)) & UART_FRA_DIVFRACTION_MASK) + +/*! + * @brief UART_RXADDR Register Bit Definition + */ + +#define UART_RXADDR_RXADDR_SHIFT (0) +#define UART_RXADDR_RXADDR_MASK (0xFFU << UART_RXADDR_RXADDR_SHIFT) +#define UART_RXADDR_RXADDR(x) (((uint32_t)(((uint32_t)(x)) << UART_RXADDR_RXADDR_SHIFT)) & UART_RXADDR_RXADDR_MASK) + +/*! + * @brief UART_RXMASK Register Bit Definition + */ + +#define UART_RXMASK_RXMASK_SHIFT (0) +#define UART_RXMASK_RXMASK_MASK (0xFFU << UART_RXMASK_RXMASK_SHIFT) +#define UART_RXMASK_RXMASK(x) (((uint32_t)(((uint32_t)(x)) << UART_RXMASK_RXMASK_SHIFT)) & UART_RXMASK_RXMASK_MASK) + +/*! + * @brief UART_SCR Register Bit Definition + */ + +#define UART_SCR_HDSEL_SHIFT (12) +#define UART_SCR_HDSEL_MASK (0x01U << UART_SCR_HDSEL_SHIFT) +#define UART_SCR_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << UART_SCR_HDSEL_SHIFT)) & UART_SCR_HDSEL_MASK) + +#define UART_SCR_SCFCNT_SHIFT (4) +#define UART_SCR_SCFCNT_MASK (0xFFU << UART_SCR_SCFCNT_SHIFT) +#define UART_SCR_SCFCNT(x) (((uint32_t)(((uint32_t)(x)) << UART_SCR_SCFCNT_SHIFT)) & UART_SCR_SCFCNT_MASK) + +#define UART_SCR_NACK_SHIFT (2) +#define UART_SCR_NACK_MASK (0x01U << UART_SCR_NACK_SHIFT) +#define UART_SCR_NACK(x) (((uint32_t)(((uint32_t)(x)) << UART_SCR_NACK_SHIFT)) & UART_SCR_NACK_MASK) + +#define UART_SCR_SCAEN_SHIFT (1) +#define UART_SCR_SCAEN_MASK (0x01U << UART_SCR_SCAEN_SHIFT) +#define UART_SCR_SCAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_SCR_SCAEN_SHIFT)) & UART_SCR_SCAEN_MASK) + +#define UART_SCR_SCEN_SHIFT (0) +#define UART_SCR_SCEN_MASK (0x01U << UART_SCR_SCEN_SHIFT) +#define UART_SCR_SCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_SCR_SCEN_SHIFT)) & UART_SCR_SCEN_MASK) + +/*! + * @brief UART_IDLR Register Bit Definition + */ + +#define UART_IDLR_IDLR_SHIFT (0) +#define UART_IDLR_IDLR_MASK (0xFFFFU << UART_IDLR_IDLR_SHIFT) +#define UART_IDLR_IDLR(x) (((uint32_t)(((uint32_t)(x)) << UART_IDLR_IDLR_SHIFT)) & UART_IDLR_IDLR_MASK) + +/*! + * @brief UART_ABRCR Register Bit Definition + */ + +#define UART_ABRCR_LATTEREDGE_SHIFT (4) +#define UART_ABRCR_LATTEREDGE_MASK (0x01U << UART_ABRCR_LATTEREDGE_SHIFT) +#define UART_ABRCR_LATTEREDGE(x) (((uint32_t)(((uint32_t)(x)) << UART_ABRCR_LATTEREDGE_SHIFT)) & UART_ABRCR_LATTEREDGE_MASK) + +#define UART_ABRCR_FORMEREDGE_SHIFT (3) +#define UART_ABRCR_FORMEREDGE_MASK (0x01U << UART_ABRCR_FORMEREDGE_SHIFT) +#define UART_ABRCR_FORMEREDGE(x) (((uint32_t)(((uint32_t)(x)) << UART_ABRCR_FORMEREDGE_SHIFT)) & UART_ABRCR_FORMEREDGE_MASK) + +#define UART_ABRCR_ABRBITCNT_SHIFT (1) +#define UART_ABRCR_ABRBITCNT_MASK (0x3U << UART_ABRCR_ABRBITCNT_SHIFT) +#define UART_ABRCR_ABRBITCNT(x) (((uint32_t)(((uint32_t)(x)) << UART_ABRCR_ABRBITCNT_SHIFT)) & UART_ABRCR_ABRBITCNT_MASK) + +#define UART_ABRCR_ABREN_SHIFT (0) +#define UART_ABRCR_ABREN_MASK (0x01U << UART_ABRCR_ABREN_SHIFT) +#define UART_ABRCR_ABREN(x) (((uint32_t)(((uint32_t)(x)) << UART_ABRCR_ABREN_SHIFT)) & UART_ABRCR_ABREN_MASK) + +/*! + * @brief UART_IRDA Register Bit Definition + */ + +#define UART_IRDA_PSCREG_SHIFT (8) +#define UART_IRDA_PSCREG_MASK (0xFFU << UART_IRDA_PSCREG_SHIFT) +#define UART_IRDA_PSCREG(x) (((uint32_t)(((uint32_t)(x)) << UART_IRDA_PSCREG_SHIFT)) & UART_IRDA_PSCREG_MASK) + +#define UART_IRDA_SIRLP_SHIFT (1) +#define UART_IRDA_SIRLP_MASK (0x01U << UART_IRDA_SIRLP_SHIFT) +#define UART_IRDA_SIRLP(x) (((uint32_t)(((uint32_t)(x)) << UART_IRDA_SIRLP_SHIFT)) & UART_IRDA_SIRLP_MASK) + +#define UART_IRDA_SIREN_SHIFT (0) +#define UART_IRDA_SIREN_MASK (0x01U << UART_IRDA_SIREN_SHIFT) +#define UART_IRDA_SIREN(x) (((uint32_t)(((uint32_t)(x)) << UART_IRDA_SIREN_SHIFT)) & UART_IRDA_SIREN_MASK) + +/*! + * @} + */ /* end of group UART_Register_Masks */ +/****************************************************************************** + *UART Instance +*******************************************************************************/ + +#define UART1 ((UART_Type*)UART1_BASE) +#define UART2 ((UART_Type*)UART2_BASE) +#define UART3 ((UART_Type*)UART3_BASE) +#define UART4 ((UART_Type*)UART4_BASE) +#define UART5 ((UART_Type*)UART5_BASE) +#define UART6 ((UART_Type*)UART6_BASE) +#define UART7 ((UART_Type*)UART7_BASE) + +/*! + * @} + */ /* end of group UART_Peripheral_Access_Layer */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * USB Type + ******************************************************************************/ +typedef struct { + __IO uint32_t Reserved55[4]; ///< Reserved + __IO uint32_t FSOTGISTAT; ///< OTG Interrupt Status Register offset: 0x10 + __IO uint32_t FSOTGICTRL; ///< OTG Interrupt Control Register offset: 0x14 + __IO uint32_t FSOTGSTAT; ///< OTG Status Register offset: 0x18 + __IO uint32_t FSOTGCTRL; ///< OTG Control Register offset: 0x1C + __IO uint32_t Reserved56[24]; ///< Reserved + __IO uint32_t FSINTSTAT; ///< Interrupt Status Register offset: 0x80 + __IO uint32_t FSINTENB; ///< Interrupt Enable Register offset: 0x84 + __IO uint32_t FSERRSTAT; ///< Error Interrupt Status Register offset: 0x88 + __IO uint32_t FSERRENB; ///< Error Interrupt Enable Register offset: 0x8C + __IO uint32_t FSSTAT; ///< Status Register offset: 0x90 + __IO uint32_t FSCTL; ///< Control Register offset: 0x94 + __IO uint32_t FSADDR; ///< Address Register offset: 0x98 + __IO uint32_t FSBDTPAGE1; ///< BDT Page Register 1 offset: 0x9C + __IO uint32_t FSFRMNUML; ///< Frame Number Register offset: 0xA0 + __IO uint32_t FSFRMNUMH; ///< Frame Number Register offset: 0xA4 + __IO uint32_t FSTOKEN; ///< Token Register offset: 0xA8 + __IO uint32_t FSSOFTHLD; ///< SOF Threshold Register offset: 0xAC + __IO uint32_t FSBDTPAGE2; ///< BDT Page Register 2 offset: 0xB0 + __IO uint32_t FSBDTPAGE3; ///< BDT Page Register 3 offset: 0xB4 + __IO uint32_t Reserved57[2]; ///< Reserved + __IO uint32_t FSEPCTL[16]; ///< Endpoint control register 0 ~15 offset: 0xC0 + __IO uint32_t FSUSBCTRL; ///< USB control register offset 0x100 +} USB_Type; + +/******************************************************************************* + * USB Type + ******************************************************************************/ + +/*! + * @addtogroup USB_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief USB_FS_OTGISTAT Register Bit Definition + */ + +#define USB_FSOTGISTAT_IDCHG_SHIFT (7) +#define USB_FSOTGISTAT_IDCHG_MASK (0x01U << USB_FSOTGISTAT_IDCHG_SHIFT) +#define USB_FSOTGISTAT_IDCHG(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGISTAT_IDCHG_SHIFT)) & USB_FSOTGISTAT_IDCHG_MASK) + +#define USB_FSOTGISTAT_1MSEC_SHIFT (6) +#define USB_FSOTGISTAT_1MSEC_MASK (0x01U << USB_FSOTGISTAT_1MSEC_SHIFT) +#define USB_FSOTGISTAT_1MSEC(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGISTAT_1MSEC_SHIFT)) & USB_FSOTGISTAT_1MSEC_MASK) + +#define USB_FSOTGISTAT_LINESTATECHG_SHIFT (5) +#define USB_FSOTGISTAT_LINESTATECHG_MASK (0x01U << USB_FSOTGISTAT_LINESTATECHG_SHIFT) +#define USB_FSOTGISTAT_LINESTATECHG(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGISTAT_LINESTATECHG_SHIFT)) & USB_FSOTGISTAT_LINESTATECHG_MASK) + +#define USB_FSOTGISTAT_SESSVLDCHG_SHIFT (2) +#define USB_FSOTGISTAT_SESSVLDCHG_MASK (0x01U << USB_FSOTGISTAT_SESSVLDCHG_SHIFT) +#define USB_FSOTGISTAT_SESSVLDCHG(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGISTAT_SESSVLDCHG_SHIFT)) & USB_FSOTGISTAT_SESSVLDCHG_MASK) + +#define USB_FSOTGISTAT_BSESSENDCHG_SHIFT (2) +#define USB_FSOTGISTAT_BSESSENDCHG_MASK (0x01U << USB_FSOTGISTAT_BSESSENDCHG_SHIFT) +#define USB_FSOTGISTAT_BSESSENDCHG(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGISTAT_BSESSENDCHG_SHIFT)) & USB_FSOTGISTAT_BSESSENDCHG_MASK) + +#define USB_FSOTGISTAT_AVBUSVLDCHG_SHIFT (0) +#define USB_FSOTGISTAT_AVBUSVLDCHG_MASK (0x01U << USB_FSOTGISTAT_AVBUSVLDCHG_SHIFT) +#define USB_FSOTGISTAT_AVBUSVLDCHG(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGISTAT_AVBUSVLDCHG_SHIFT)) & USB_FSOTGISTAT_AVBUSVLDCHG_MASK) + +/*! + * @brief USB_FS_OTGICTRL Register Bit Definition + */ + +#define USB_FSOTGICTRL_IDEN_SHIFT (7) +#define USB_FSOTGICTRL_IDEN_MASK (0x01U << USB_FSOTGICTRL_IDEN_SHIFT) +#define USB_FSOTGICTRL_IDEN(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGICTRL_IDEN_SHIFT)) & USB_FSOTGICTRL_IDEN_MASK) + +#define USB_FSOTGICTRL_1MSECEN_SHIFT (6) +#define USB_FSOTGICTRL_1MSECEN_MASK (0x01U << USB_FSOTGICTRL_1MSECEN_SHIFT) +#define USB_FSOTGICTRL_1MSECEN(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGICTRL_1MSECEN_SHIFT)) & USB_FSOTGICTRL_1MSECEN_MASK) + +#define USB_FSOTGICTRL_LINESTATEEN_SHIFT (5) +#define USB_FSOTGICTRL_LINESTATEEN_MASK (0x01U << USB_FSOTGICTRL_LINESTATEEN_SHIFT) +#define USB_FSOTGICTRL_LINESTATEEN(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGICTRL_LINESTATEEN_SHIFT)) & USB_FSOTGICTRL_LINESTATEEN_MASK) + +#define USB_FSOTGICTRL_SESSVLDEN_SHIFT (3) +#define USB_FSOTGICTRL_SESSVLDEN_MASK (0x01U << USB_FSOTGICTRL_SESSVLDEN_SHIFT) +#define USB_FSOTGICTRL_SESSVLDEN(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGICTRL_SESSVLDEN_SHIFT)) & USB_FSOTGICTRL_SESSVLDEN_MASK) + +#define USB_FSOTGICTRL_BSESSENDEN_SHIFT (2) +#define USB_FSOTGICTRL_BSESSENDEN_MASK (0x01U << USB_FSOTGICTRL_BSESSENDEN_SHIFT) +#define USB_FSOTGICTRL_BSESSENDEN(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGICTRL_BSESSENDEN_SHIFT)) & USB_FSOTGICTRL_BSESSENDEN_MASK) + +#define USB_FSOTGICTRL_AVBUSVLDEN_SHIFT (0) +#define USB_FSOTGICTRL_AVBUSVLDEN_MASK (0x01U << USB_FSOTGICTRL_AVBUSVLDEN_SHIFT) +#define USB_FSOTGICTRL_AVBUSVLDEN(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGICTRL_AVBUSVLDEN_SHIFT)) & USB_FSOTGICTRL_AVBUSVLDEN_MASK) + +/*! + * @brief USB_FS_OTGSTAT Register Bit Definition + */ + +#define USB_FSOTGSTAT_ID_SHIFT (7) +#define USB_FSOTGSTAT_ID_MASK (0x01U << USB_FSOTGSTAT_ID_SHIFT) +#define USB_FSOTGSTAT_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGSTAT_ID_SHIFT)) & USB_FSOTGSTAT_ID_MASK) + +#define USB_FSOTGSTAT_LINESTATESTABLE_SHIFT (5) +#define USB_FSOTGSTAT_LINESTATESTABLE_MASK (0x01U << USB_FSOTGSTAT_LINESTATESTABLE_SHIFT) +#define USB_FSOTGSTAT_LINESTATESTABLE(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGSTAT_LINESTATESTABLE_SHIFT)) & USB_FSOTGSTAT_LINESTATESTABLE_MASK) + +#define USB_FSOTGSTAT_SESSVLD_SHIFT (3) +#define USB_FSOTGSTAT_SESSVLD_MASK (0x01U << USB_FSOTGSTAT_SESSVLD_SHIFT) +#define USB_FSOTGSTAT_SESSVLD(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGSTAT_SESSVLD_SHIFT)) & USB_FSOTGSTAT_SESSVLD_MASK) + +#define USB_FSOTGSTAT_BSESSEND_SHIFT (2) +#define USB_FSOTGSTAT_BSESSEND_MASK (0x01U << USB_FSOTGSTAT_BSESSEND_SHIFT) +#define USB_FSOTGSTAT_BSESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGSTAT_BSESSEND_SHIFT)) & USB_FSOTGSTAT_BSESSEND_MASK) + +#define USB_FSOTGSTAT_AVBUSVLD_SHIFT (0) +#define USB_FSOTGSTAT_AVBUSVLD_MASK (0x01U << USB_FSOTGSTAT_AVBUSVLD_SHIFT) +#define USB_FSOTGSTAT_AVBUSVLD(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGSTAT_AVBUSVLD_SHIFT)) & USB_FSOTGSTAT_AVBUSVLD_MASK) + +/*! + * @brief USB_FS_OTGCTRL Register Bit Definition + */ + +#define USB_FSOTGCTRL_DPHIGH_SHIFT (7) +#define USB_FSOTGCTRL_DPHIGH_MASK (0x01U << USB_FSOTGCTRL_DPHIGH_SHIFT) +#define USB_FSOTGCTRL_DPHIGH(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGCTRL_DPHIGH_SHIFT)) & USB_FSOTGCTRL_DPHIGH_MASK) + +#define USB_FSOTGCTRL_DMHIGH_SHIFT (6) +#define USB_FSOTGCTRL_DMHIGH_MASK (0x01U << USB_FSOTGCTRL_DMHIGH_SHIFT) +#define USB_FSOTGCTRL_DMHIGH(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGCTRL_DMHIGH_SHIFT)) & USB_FSOTGCTRL_DMHIGH_MASK) + +#define USB_FSOTGCTRL_DPLOW_SHIFT (5) +#define USB_FSOTGCTRL_DPLOW_MASK (0x01U << USB_FSOTGCTRL_DPLOW_SHIFT) +#define USB_FSOTGCTRL_DPLOW(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGCTRL_DPLOW_SHIFT)) & USB_FSOTGCTRL_DPLOW_MASK) + +#define USB_FSOTGCTRL_DMLOW_SHIFT (4) +#define USB_FSOTGCTRL_DMLOW_MASK (0x01U << USB_FSOTGCTRL_DMLOW_SHIFT) +#define USB_FSOTGCTRL_DMLOW(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGCTRL_DMLOW_SHIFT)) & USB_FSOTGCTRL_DMLOW_MASK) + +#define USB_FSOTGCTRL_VBUSON_SHIFT (3) +#define USB_FSOTGCTRL_VBUSON_MASK (0x01U << USB_FSOTGCTRL_VBUSON_SHIFT) +#define USB_FSOTGCTRL_VBUSON(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGCTRL_VBUSON_SHIFT)) & USB_FSOTGCTRL_VBUSON_MASK) + +#define USB_FSOTGCTRL_OTGEN_SHIFT (2) +#define USB_FSOTGCTRL_OTGEN_MASK (0x01U << USB_FSOTGCTRL_OTGEN_SHIFT) +#define USB_FSOTGCTRL_OTGEN(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGCTRL_OTGEN_SHIFT)) & USB_FSOTGCTRL_OTGEN_MASK) + +#define USB_FSOTGCTRL_VBUSCHG_SHIFT (1) +#define USB_FSOTGCTRL_VBUSCHG_MASK (0x01U << USB_FSOTGCTRL_VBUSCHG_SHIFT) +#define USB_FSOTGCTRL_VBUSCHG(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGCTRL_VBUSCHG_SHIFT)) & USB_FSOTGCTRL_VBUSCHG_MASK) + +#define USB_FSOTGCTRL_VBUSDSCHG_SHIFT (0) +#define USB_FSOTGCTRL_VBUSDSCHG_MASK (0x01U << USB_FSOTGCTRL_VBUSDSCHG_SHIFT) +#define USB_FSOTGCTRL_VBUSDSCHG(x) (((uint32_t)(((uint32_t)(x)) << USB_FSOTGCTRL_VBUSDSCHG_SHIFT)) & USB_FSOTGCTRL_VBUSDSCHG_MASK) + +/*! + * @brief USB_FS_INTSTAT Register Bit Definition + */ + +#define USB_FSINTSTAT_STALL_SHIFT (7) +#define USB_FSINTSTAT_STALL_MASK (0x01U << USB_FSINTSTAT_STALL_SHIFT) +#define USB_FSINTSTAT_STALL(x) (((uint32_t)(((uint32_t)(x)) << USB_FSINTSTAT_STALL_SHIFT)) & USB_FSINTSTAT_STALL_MASK) + +#define USB_FSINTSTAT_ATTACH_SHIFT (6) +#define USB_FSINTSTAT_ATTACH_MASK (0x01U << USB_FSINTSTAT_ATTACH_SHIFT) +#define USB_FSINTSTAT_ATTACH(x) (((uint32_t)(((uint32_t)(x)) << USB_FSINTSTAT_ATTACH_SHIFT)) & USB_FSINTSTAT_ATTACH_MASK) + +#define USB_FSINTSTAT_RESUME_SHIFT (5) +#define USB_FSINTSTAT_RESUME_MASK (0x01U << USB_FSINTSTAT_RESUME_SHIFT) +#define USB_FSINTSTAT_RESUME(x) (((uint32_t)(((uint32_t)(x)) << USB_FSINTSTAT_RESUME_SHIFT)) & USB_FSINTSTAT_RESUME_MASK) + +#define USB_FSINTSTAT_SLEEP_SHIFT (4) +#define USB_FSINTSTAT_SLEEP_MASK (0x01U << USB_FSINTSTAT_SLEEP_SHIFT) +#define USB_FSINTSTAT_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << USB_FSINTSTAT_SLEEP_SHIFT)) & USB_FSINTSTAT_SLEEP_MASK) + +#define USB_FSINTSTAT_TOKDNE_SHIFT (3) +#define USB_FSINTSTAT_TOKDNE_MASK (0x01U << USB_FSINTSTAT_TOKDNE_SHIFT) +#define USB_FSINTSTAT_TOKDNE(x) (((uint32_t)(((uint32_t)(x)) << USB_FSINTSTAT_TOKDNE_SHIFT)) & USB_FSINTSTAT_TOKDNE_MASK) + +#define USB_FSINTSTAT_SOFTOK_SHIFT (2) +#define USB_FSINTSTAT_SOFTOK_MASK (0x01U << USB_FSINTSTAT_SOFTOK_SHIFT) +#define USB_FSINTSTAT_SOFTOK(x) (((uint32_t)(((uint32_t)(x)) << USB_FSINTSTAT_SOFTOK_SHIFT)) & USB_FSINTSTAT_SOFTOK_MASK) + +#define USB_FSINTSTAT_ERROR_SHIFT (1) +#define USB_FSINTSTAT_ERROR_MASK (0x01U << USB_FSINTSTAT_ERROR_SHIFT) +#define USB_FSINTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << USB_FSINTSTAT_ERROR_SHIFT)) & USB_FSINTSTAT_ERROR_MASK) + +#define USB_FSINTSTAT_USBRST_SHIFT (0) +#define USB_FSINTSTAT_USBRST_MASK (0x01U << USB_FSINTSTAT_USBRST_SHIFT) +#define USB_FSINTSTAT_USBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_FSINTSTAT_USBRST_SHIFT)) & USB_FSINTSTAT_USBRST_MASK) + +/*! + * @brief USB_FS_INTENB Register Bit Definition + */ + +#define USB_FSINTENB_STALL_SHIFT (7) +#define USB_FSINTENB_STALL_MASK (0x01U << USB_FSINTENB_STALL_SHIFT) +#define USB_FSINTENB_STALL(x) (((uint32_t)(((uint32_t)(x)) << USB_FSINTENB_STALL_SHIFT)) & USB_FSINTENB_STALL_MASK) + +#define USB_FSINTENB_ATTACH_SHIFT (6) +#define USB_FSINTENB_ATTACH_MASK (0x01U << USB_FSINTENB_ATTACH_SHIFT) +#define USB_FSINTENB_ATTACH(x) (((uint32_t)(((uint32_t)(x)) << USB_FSINTENB_ATTACH_SHIFT)) & USB_FSINTENB_ATTACH_MASK) + +#define USB_FSINTENB_RESUME_SHIFT (5) +#define USB_FSINTENB_RESUME_MASK (0x01U << USB_FSINTENB_RESUME_SHIFT) +#define USB_FSINTENB_RESUME(x) (((uint32_t)(((uint32_t)(x)) << USB_FSINTENB_RESUME_SHIFT)) & USB_FSINTENB_RESUME_MASK) + +#define USB_FSINTENB_SLEEP_SHIFT (4) +#define USB_FSINTENB_SLEEP_MASK (0x01U << USB_FSINTENB_SLEEP_SHIFT) +#define USB_FSINTENB_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << USB_FSINTENB_SLEEP_SHIFT)) & USB_FSINTENB_SLEEP_MASK) + +#define USB_FSINTENB_TOKDNE_SHIFT (3) +#define USB_FSINTENB_TOKDNE_MASK (0x01U << USB_FSINTENB_TOKDNE_SHIFT) +#define USB_FSINTENB_TOKDNE(x) (((uint32_t)(((uint32_t)(x)) << USB_FSINTENB_TOKDNE_SHIFT)) & USB_FSINTENB_TOKDNE_MASK) + +#define USB_FSINTENB_SOFTOK_SHIFT (2) +#define USB_FSINTENB_SOFTOK_MASK (0x01U << USB_FSINTENB_SOFTOK_SHIFT) +#define USB_FSINTENB_SOFTOK(x) (((uint32_t)(((uint32_t)(x)) << USB_FSINTENB_SOFTOK_SHIFT)) & USB_FSINTENB_SOFTOK_MASK) + +#define USB_FSINTENB_ERROR_SHIFT (1) +#define USB_FSINTENB_ERROR_MASK (0x01U << USB_FSINTENB_ERROR_SHIFT) +#define USB_FSINTENB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << USB_FSINTENB_ERROR_SHIFT)) & USB_FSINTENB_ERROR_MASK) + +#define USB_FSINTENB_USBRST_SHIFT (0) +#define USB_FSINTENB_USBRST_MASK (0x01U << USB_FSINTENB_USBRST_SHIFT) +#define USB_FSINTENB_USBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_FSINTENB_USBRST_SHIFT)) & USB_FSINTENB_USBRST_MASK) + +/*! + * @brief USB_FS_ERRSTAT Register Bit Definition + */ + +#define USB_FSERRSTAT_BTSERR_SHIFT (7) +#define USB_FSERRSTAT_BTSERR_MASK (0x01U << USB_FSERRSTAT_BTSERR_SHIFT) +#define USB_FSERRSTAT_BTSERR(x) (((uint32_t)(((uint32_t)(x)) << USB_FSERRSTAT_BTSERR_SHIFT)) & USB_FSERRSTAT_BTSERR_MASK) + +#define USB_FSERRSTAT_DMAERR_SHIFT (5) +#define USB_FSERRSTAT_DMAERR_MASK (0x01U << USB_FSERRSTAT_DMAERR_SHIFT) +#define USB_FSERRSTAT_DMAERR(x) (((uint32_t)(((uint32_t)(x)) << USB_FSERRSTAT_DMAERR_SHIFT)) & USB_FSERRSTAT_DMAERR_MASK) + +#define USB_FSERRSTAT_BTOERR_SHIFT (4) +#define USB_FSERRSTAT_BTOERR_MASK (0x01U << USB_FSERRSTAT_BTOERR_SHIFT) +#define USB_FSERRSTAT_BTOERR(x) (((uint32_t)(((uint32_t)(x)) << USB_FSERRSTAT_BTOERR_SHIFT)) & USB_FSERRSTAT_BTOERR_MASK) + +#define USB_FSERRSTAT_DFN8_SHIFT (3) +#define USB_FSERRSTAT_DFN8_MASK (0x01U << USB_FSERRSTAT_DFN8_SHIFT) +#define USB_FSERRSTAT_DFN8(x) (((uint32_t)(((uint32_t)(x)) << USB_FSERRSTAT_DFN8_SHIFT)) & USB_FSERRSTAT_DFN8_MASK) + +#define USB_FSERRSTAT_CRC16_SHIFT (2) +#define USB_FSERRSTAT_CRC16_MASK (0x01U << USB_FSERRSTAT_CRC16_SHIFT) +#define USB_FSERRSTAT_CRC16(x) (((uint32_t)(((uint32_t)(x)) << USB_FSERRSTAT_CRC16_SHIFT)) & USB_FSERRSTAT_CRC16_MASK) + +#define USB_FSERRSTAT_CRC5EOF_SHIFT (1) +#define USB_FSERRSTAT_CRC5EOF_MASK (0x01U << USB_FSERRSTAT_CRC5EOF_SHIFT) +#define USB_FSERRSTAT_CRC5EOF(x) (((uint32_t)(((uint32_t)(x)) << USB_FSERRSTAT_CRC5EOF_SHIFT)) & USB_FSERRSTAT_CRC5EOF_MASK) + +#define USB_FSERRSTAT_PIDERR_SHIFT (0) +#define USB_FSERRSTAT_PIDERR_MASK (0x01U << USB_FSERRSTAT_PIDERR_SHIFT) +#define USB_FSERRSTAT_PIDERR(x) (((uint32_t)(((uint32_t)(x)) << USB_FSERRSTAT_PIDERR_SHIFT)) & USB_FSERRSTAT_PIDERR_MASK) + +/*! + * @brief USB_FS_ERRENB Register Bit Definition + */ + +#define USB_FSERRENB_BTSERR_SHIFT (7) +#define USB_FSERRENB_BTSERR_MASK (0x01U << USB_FSERRENB_BTSERR_SHIFT) +#define USB_FSERRENB_BTSERR(x) (((uint32_t)(((uint32_t)(x)) << USB_FSERRENB_BTSERR_SHIFT)) & USB_FSERRENB_BTSERR_MASK) + +#define USB_FSERRENB_DMAERR_SHIFT (5) +#define USB_FSERRENB_DMAERR_MASK (0x01U << USB_FSERRENB_DMAERR_SHIFT) +#define USB_FSERRENB_DMAERR(x) (((uint32_t)(((uint32_t)(x)) << USB_FSERRENB_DMAERR_SHIFT)) & USB_FSERRENB_DMAERR_MASK) + +#define USB_FSERRENB_BTOERR_SHIFT (4) +#define USB_FSERRENB_BTOERR_MASK (0x01U << USB_FSERRENB_BTOERR_SHIFT) +#define USB_FSERRENB_BTOERR(x) (((uint32_t)(((uint32_t)(x)) << USB_FSERRENB_BTOERR_SHIFT)) & USB_FSERRENB_BTOERR_MASK) + +#define USB_FSERRENB_DFN8_SHIFT (3) +#define USB_FSERRENB_DFN8_MASK (0x01U << USB_FSERRENB_DFN8_SHIFT) +#define USB_FSERRENB_DFN8(x) (((uint32_t)(((uint32_t)(x)) << USB_FSERRENB_DFN8_SHIFT)) & USB_FSERRENB_DFN8_MASK) + +#define USB_FSERRENB_CRC16_SHIFT (2) +#define USB_FSERRENB_CRC16_MASK (0x01U << USB_FSERRENB_CRC16_SHIFT) +#define USB_FSERRENB_CRC16(x) (((uint32_t)(((uint32_t)(x)) << USB_FSERRENB_CRC16_SHIFT)) & USB_FSERRENB_CRC16_MASK) + +#define USB_FSERRENB_CRC5EOF_SHIFT (1) +#define USB_FSERRENB_CRC5EOF_MASK (0x01U << USB_FSERRENB_CRC5EOF_SHIFT) +#define USB_FSERRENB_CRC5EOF(x) (((uint32_t)(((uint32_t)(x)) << USB_FSERRENB_CRC5EOF_SHIFT)) & USB_FSERRENB_CRC5EOF_MASK) + +#define USB_FSERRENB_PIDERR_SHIFT (0) +#define USB_FSERRENB_PIDERR_MASK (0x01U << USB_FSERRENB_PIDERR_SHIFT) +#define USB_FSERRENB_PIDERR(x) (((uint32_t)(((uint32_t)(x)) << USB_FSERRENB_PIDERR_SHIFT)) & USB_FSERRENB_PIDERR_MASK) + +/*! + * @brief USB_FS_STAT Register Bit Definition + */ + +#define USB_FSSTAT_ENDP_SHIFT (4) +#define USB_FSSTAT_ENDP_MASK (0xFU << USB_FSSTAT_ENDP_SHIFT) +#define USB_FSSTAT_ENDP(x) (((uint32_t)(((uint32_t)(x)) << USB_FSSTAT_ENDP_SHIFT)) & USB_FSSTAT_ENDP_MASK) + +#define USB_FSSTAT_TX_SHIFT (3) +#define USB_FSSTAT_TX_MASK (0x01U << USB_FSSTAT_TX_SHIFT) +#define USB_FSSTAT_TX(x) (((uint32_t)(((uint32_t)(x)) << USB_FSSTAT_TX_SHIFT)) & USB_FSSTAT_TX_MASK) + +#define USB_FSSTAT_ODD_SHIFT (2) +#define USB_FSSTAT_ODD_MASK (0x01U << USB_FSSTAT_ODD_SHIFT) +#define USB_FSSTAT_ODD(x) (((uint32_t)(((uint32_t)(x)) << USB_FSSTAT_ODD_SHIFT)) & USB_FSSTAT_ODD_MASK) + +/*! + * @brief USB_FS_CTL Register Bit Definition + */ + +#define USB_FSCTL_JSTATE_SHIFT (7) +#define USB_FSCTL_JSTATE_MASK (0x01U << USB_FSCTL_JSTATE_SHIFT) +#define USB_FSCTL_JSTATE(x) (((uint32_t)(((uint32_t)(x)) << USB_FSCTL_JSTATE_SHIFT)) & USB_FSCTL_JSTATE_MASK) + +#define USB_FSCTL_SE0_SHIFT (6) +#define USB_FSCTL_SE0_MASK (0x01U << USB_FSCTL_SE0_SHIFT) +#define USB_FSCTL_SE0(x) (((uint32_t)(((uint32_t)(x)) << USB_FSCTL_SE0_SHIFT)) & USB_FSCTL_SE0_MASK) + +#define USB_FSCTL_TXDSUSPENDTOKENBUSY_SHIFT (5) +#define USB_FSCTL_TXDSUSPENDTOKENBUSY_MASK (0x01U << USB_FSCTL_TXDSUSPENDTOKENBUSY_SHIFT) +#define USB_FSCTL_TXDSUSPENDTOKENBUSY(x) (((uint32_t)(((uint32_t)(x)) << USB_FSCTL_TXDSUSPENDTOKENBUSY_SHIFT)) & USB_FSCTL_TXDSUSPENDTOKENBUSY_MASK) + +#define USB_FSCTL_RESET_SHIFT (4) +#define USB_FSCTL_RESET_MASK (0x01U << USB_FSCTL_RESET_SHIFT) +#define USB_FSCTL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USB_FSCTL_RESET_SHIFT)) & USB_FSCTL_RESET_MASK) + +#define USB_FSCTL_HOSTMODEEN_SHIFT (3) +#define USB_FSCTL_HOSTMODEEN_MASK (0x01U << USB_FSCTL_HOSTMODEEN_SHIFT) +#define USB_FSCTL_HOSTMODEEN(x) (((uint32_t)(((uint32_t)(x)) << USB_FSCTL_HOSTMODEEN_SHIFT)) & USB_FSCTL_HOSTMODEEN_MASK) + +#define USB_FSCTL_RESUME_SHIFT (2) +#define USB_FSCTL_RESUME_MASK (0x01U << USB_FSCTL_RESUME_SHIFT) +#define USB_FSCTL_RESUME(x) (((uint32_t)(((uint32_t)(x)) << USB_FSCTL_RESUME_SHIFT)) & USB_FSCTL_RESUME_MASK) + +#define USB_FSCTL_ODDRST_SHIFT (1) +#define USB_FSCTL_ODDRST_MASK (0x01U << USB_FSCTL_ODDRST_SHIFT) +#define USB_FSCTL_ODDRST(x) (((uint32_t)(((uint32_t)(x)) << USB_FSCTL_ODDRST_SHIFT)) & USB_FSCTL_ODDRST_MASK) + +#define USB_FSCTL_USBEN_SHIFT (0) +#define USB_FSCTL_USBEN_MASK (0x01U << USB_FSCTL_USBEN_SHIFT) +#define USB_FSCTL_USBEN(x) (((uint32_t)(((uint32_t)(x)) << USB_FSCTL_USBEN_SHIFT)) & USB_FSCTL_USBEN_MASK) + +/*! + * @brief USB_FS_ADDR Register Bit Definition + */ + +#define USB_FSADDR_LSEN_SHIFT (7) +#define USB_FSADDR_LSEN_MASK (0x01U << USB_FSADDR_LSEN_SHIFT) +#define USB_FSADDR_LSEN(x) (((uint32_t)(((uint32_t)(x)) << USB_FSADDR_LSEN_SHIFT)) & USB_FSADDR_LSEN_MASK) + +#define USB_FSADDR_ADDR_SHIFT (0) +#define USB_FSADDR_ADDR_MASK (0x7FU << USB_FSADDR_ADDR_SHIFT) +#define USB_FSADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_FSADDR_ADDR_SHIFT)) & USB_FSADDR_ADDR_MASK) + +/*! + * @brief USB_FS_BDTPAGE1 Register Bit Definition + */ + +#define USB_FSBDTPAGE1_BDTBA_SHIFT (1) +#define USB_FSBDTPAGE1_BDTBA_MASK (0x7FU << USB_FSBDTPAGE1_BDTBA_SHIFT) +#define USB_FSBDTPAGE1_BDTBA(x) (((uint32_t)(((uint32_t)(x)) << USB_FSBDTPAGE1_BDTBA_SHIFT)) & USB_FSBDTPAGE1_BDTBA_MASK) + +/*! + * @brief USB_FS_FRMNUML Register Bit Definition + */ + +#define USB_FSFRMNUML_FRM_SHIFT (0) +#define USB_FSFRMNUML_FRM_MASK (0xFFU << USB_FSFRMNUML_FRM_SHIFT) +#define USB_FSFRMNUML_FRM(x) (((uint32_t)(((uint32_t)(x)) << USB_FSFRMNUML_FRM_SHIFT)) & USB_FSFRMNUML_FRM_MASK) + +/*! + * @brief USB_FS_FRMNUMH Register Bit Definition + */ + +#define USB_FSFRMNUMH_FRM_SHIFT (0) +#define USB_FSFRMNUMH_FRM_MASK (0x7U << USB_FSFRMNUMH_FRM_SHIFT) +#define USB_FSFRMNUMH_FRM(x) (((uint32_t)(((uint32_t)(x)) << USB_FSFRMNUMH_FRM_SHIFT)) & USB_FSFRMNUMH_FRM_MASK) + +/*! + * @brief USB_FS_TOKEN Register Bit Definition + */ + +#define USB_FSTOKEN_TOKENPID_SHIFT (4) +#define USB_FSTOKEN_TOKENPID_MASK (0xFU << USB_FSTOKEN_TOKENPID_SHIFT) +#define USB_FSTOKEN_TOKENPID(x) (((uint32_t)(((uint32_t)(x)) << USB_FSTOKEN_TOKENPID_SHIFT)) & USB_FSTOKEN_TOKENPID_MASK) + +#define USB_FSTOKEN_TOKENENDPT_SHIFT (0) +#define USB_FSTOKEN_TOKENENDPT_MASK (0xFU << USB_FSTOKEN_TOKENENDPT_SHIFT) +#define USB_FSTOKEN_TOKENENDPT(x) (((uint32_t)(((uint32_t)(x)) << USB_FSTOKEN_TOKENENDPT_SHIFT)) & USB_FSTOKEN_TOKENENDPT_MASK) + +/*! + * @brief USB_FS_SOFTHLD Register Bit Definition + */ + +#define USB_FSSOFTHLD_CNT_SHIFT (0) +#define USB_FSSOFTHLD_CNT_MASK (0xFFU << USB_FSSOFTHLD_CNT_SHIFT) +#define USB_FSSOFTHLD_CNT(x) (((uint32_t)(((uint32_t)(x)) << USB_FSSOFTHLD_CNT_SHIFT)) & USB_FSSOFTHLD_CNT_MASK) + +/*! + * @brief USB_FS_BDTPAGE2 Register Bit Definition + */ + +#define USB_FSBDTPAGE2_BDTBA_SHIFT (0) +#define USB_FSBDTPAGE2_BDTBA_MASK (0xFFU << USB_FSBDTPAGE2_BDTBA_SHIFT) +#define USB_FSBDTPAGE2_BDTBA(x) (((uint32_t)(((uint32_t)(x)) << USB_FSBDTPAGE2_BDTBA_SHIFT)) & USB_FSBDTPAGE2_BDTBA_MASK) + +/*! + * @brief USB_FS_BDTPAGE3 Register Bit Definition + */ + +#define USB_FSBDTPAGE3_BDTBA_SHIFT (0) +#define USB_FSBDTPAGE3_BDTBA_MASK (0xFFU << USB_FSBDTPAGE3_BDTBA_SHIFT) +#define USB_FSBDTPAGE3_BDTBA(x) (((uint32_t)(((uint32_t)(x)) << USB_FSBDTPAGE3_BDTBA_SHIFT)) & USB_FSBDTPAGE3_BDTBA_MASK) + +/*! + * @brief USB_FS_EPCTL0 Register Bit Definition + */ + +#define USB_FSEPCTL_HOSTWOHUB_SHIFT (7) +#define USB_FSEPCTL_HOSTWOHUB_MASK (0x01U << USB_FSEPCTL_HOSTWOHUB_SHIFT) +#define USB_FSEPCTL_HOSTWOHUB(x) (((uint32_t)(((uint32_t)(x)) << USB_FSEPCTL_HOSTWOHUB_SHIFT)) & USB_FSEPCTL_HOSTWOHUB_MASK) + +#define USB_FSEPCTL_RETRYDIS_SHIFT (6) +#define USB_FSEPCTL_RETRYDIS_MASK (0x01U << USB_FSEPCTL_RETRYDIS_SHIFT) +#define USB_FSEPCTL_RETRYDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_FSEPCTL_RETRYDIS_SHIFT)) & USB_FSEPCTL_RETRYDIS_MASK) + +#define USB_FSEPCTL_EPCTLDISEPRXENEPTXEN_SHIFT (2) +#define USB_FSEPCTL_EPCTLDISEPRXENEPTXEN_MASK (0x7U << USB_FSEPCTL_EPCTLDISEPRXENEPTXEN_SHIFT) +#define USB_FSEPCTL_EPCTLDISEPRXENEPTXEN(x) (((uint32_t)(((uint32_t)(x)) << USB_FSEPCTL_EPCTLDISEPRXENEPTXEN_SHIFT)) & USB_FSEPCTL_EPCTLDISEPRXENEPTXEN_MASK) + +#define USB_FSEPCTL_EPSTALL_SHIFT (1) +#define USB_FSEPCTL_EPSTALL_MASK (0x01U << USB_FSEPCTL_EPSTALL_SHIFT) +#define USB_FSEPCTL_EPSTALL(x) (((uint32_t)(((uint32_t)(x)) << USB_FSEPCTL_EPSTALL_SHIFT)) & USB_FSEPCTL_EPSTALL_MASK) + +#define USB_FSEPCTL_EPHSHK_SHIFT (0) +#define USB_FSEPCTL_EPHSHK_MASK (0x01U << USB_FSEPCTL_EPHSHK_SHIFT) +#define USB_FSEPCTL_EPHSHK(x) (((uint32_t)(((uint32_t)(x)) << USB_FSEPCTL_EPHSHK_SHIFT)) & USB_FSEPCTL_EPHSHK_MASK) +/*! + * @brief USB_FS_USBCTRL Register Bit Definition + */ + +#define USB_FSUSBCTRL_SUSPE_SHIFT (7) +#define USB_FSUSBCTRL_SUSPE_MASK (0x01U << USB_FSUSBCTRL_SUSPE_SHIFT) +#define USB_FSUSBCTRL_SUSPE(x) (((uint32_t)(((uint32_t)(x)) << USB_FSUSBCTRL_SUSPE_SHIFT)) & USB_FSUSBCTRL_SUSPE_MASK) + +/*! + * @} + */ /* end of group USB_Register_Masks */ +/****************************************************************************** + *USB Instance +*******************************************************************************/ + +#define USB ((USB_Type*)USB_BASE) + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + +/*! + * @addtogroup WWDG_Peripheral_Access_Layer WWDG Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * WWDG Type + ******************************************************************************/ +typedef struct { + __IO uint32_t CR; ///< control register offset: 0x00 + __IO uint32_t CFGR; ///< configuration register offset: 0x04 + __IO uint32_t SR; ///< status register offset: 0x08 +} WWDG_Type; + +/******************************************************************************* + * WWDG Type + ******************************************************************************/ + +/*! + * @addtogroup WWDG_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief WWDG_CR Register Bit Definition + */ + +#define WWDG_CR_WDGA_SHIFT (7) +#define WWDG_CR_WDGA_MASK (0x01U << WWDG_CR_WDGA_SHIFT) +#define WWDG_CR_WDGA(x) (((uint32_t)(((uint32_t)(x)) << WWDG_CR_WDGA_SHIFT)) & WWDG_CR_WDGA_MASK) + +#define WWDG_CR_T_SHIFT (0) +#define WWDG_CR_T_MASK (0x7FU << WWDG_CR_T_SHIFT) +#define WWDG_CR_T(x) (((uint32_t)(((uint32_t)(x)) << WWDG_CR_T_SHIFT)) & WWDG_CR_T_MASK) + +/*! + * @brief WWDG_CFGR Register Bit Definition + */ + +#define WWDG_CFGR_EWI_SHIFT (9) +#define WWDG_CFGR_EWI_MASK (0x01U << WWDG_CFGR_EWI_SHIFT) +#define WWDG_CFGR_EWI(x) (((uint32_t)(((uint32_t)(x)) << WWDG_CFGR_EWI_SHIFT)) & WWDG_CFGR_EWI_MASK) + +#define WWDG_CFGR_WDGTB_SHIFT (7) +#define WWDG_CFGR_WDGTB_MASK (0x3U << WWDG_CFGR_WDGTB_SHIFT) +#define WWDG_CFGR_WDGTB(x) (((uint32_t)(((uint32_t)(x)) << WWDG_CFGR_WDGTB_SHIFT)) & WWDG_CFGR_WDGTB_MASK) + +#define WWDG_CFGR_W_SHIFT (0) +#define WWDG_CFGR_W_MASK (0x7FU << WWDG_CFGR_W_SHIFT) +#define WWDG_CFGR_W(x) (((uint32_t)(((uint32_t)(x)) << WWDG_CFGR_W_SHIFT)) & WWDG_CFGR_W_MASK) + +/*! + * @brief WWDG_SR Register Bit Definition + */ + +#define WWDG_SR_EWIF_SHIFT (0) +#define WWDG_SR_EWIF_MASK (0x01U << WWDG_SR_EWIF_SHIFT) +#define WWDG_SR_EWIF(x) (((uint32_t)(((uint32_t)(x)) << WWDG_SR_EWIF_SHIFT)) & WWDG_SR_EWIF_MASK) + +/*! + * @} + */ /* end of group WWDG_Register_Masks */ +/****************************************************************************** + *WWDG Instance +*******************************************************************************/ + +#define WWDG ((WWDG_Type*)WWDG_BASE) + +/*! + * @} + */ /* end of group WWDG_Peripheral_Access_Layer */ + +/* +** End of section using anonymous unions +*/ + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +#ifdef __cplusplus +} +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + +#endif /* __MM32F5277E_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/mm32f5277e_features.h b/platform/vendor_bsp/MindMotion/MM32F527/mm32f5277e_features.h new file mode 100644 index 000000000..d36289fad --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/mm32f5277e_features.h @@ -0,0 +1,2067 @@ + +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef __MM32F5277E_FEATURES_H__ +#define __MM32F5277E_FEATURES_H__ + +#include "mm32f5277e.h" + +/*! + * @brief TIM_ADV_Type. + */ +#define TIM_ADV_Type TIM1_Type /*!< TIM ADV Module Register set referring to TIM1. */ + +/*! + * @brief TIM_16B_Type. + */ +#define TIM_16B_Type TIM2_Type /*!< TIM 16B Module Register set referring to TIM3. */ + +/*! + * @brief TIM_32B_Type. + */ +#define TIM_32B_Type TIM_16B_Type /*!< TIM 32B Module Register set referring to TIM2. */ + +/*! + * @brief TIM_BASIC_Type. + */ +#define TIM_BASIC_Type TIM6_Type /*!< TIM BASIC Module Register set referring to TIM6. */ + + +/******************************************************************************* + * TIM_ADV Type + ******************************************************************************/ + +/*! + * @addtogroup TIM_ADV_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief TIM_ADV_CR1 Register Bit Definition + */ + +#define TIM_ADV_CR1_CKD_SHIFT TIM1_CR1_CKD_SHIFT +#define TIM_ADV_CR1_CKD_MASK TIM1_CR1_CKD_MASK +#define TIM_ADV_CR1_CKD(x) TIM1_CR1_CKD(x) + +#define TIM_ADV_CR1_ARPE_SHIFT TIM1_CR1_ARPE_SHIFT +#define TIM_ADV_CR1_ARPE_MASK TIM1_CR1_ARPE_MASK +#define TIM_ADV_CR1_ARPE(x) TIM1_CR1_ARPE(x) + +#define TIM_ADV_CR1_CMS_SHIFT TIM1_CR1_CMS_SHIFT +#define TIM_ADV_CR1_CMS_MASK TIM1_CR1_CMS_MASK +#define TIM_ADV_CR1_CMS(x) TIM1_CR1_CMS(x) + +#define TIM_ADV_CR1_DIR_SHIFT TIM1_CR1_DIR_SHIFT +#define TIM_ADV_CR1_DIR_MASK TIM1_CR1_DIR_MASK +#define TIM_ADV_CR1_DIR(x) TIM1_CR1_DIR(x) + +#define TIM_ADV_CR1_OPM_SHIFT TIM1_CR1_OPM_SHIFT +#define TIM_ADV_CR1_OPM_MASK TIM1_CR1_OPM_MASK +#define TIM_ADV_CR1_OPM(x) TIM1_CR1_OPM(x) + +#define TIM_ADV_CR1_URS_SHIFT TIM1_CR1_URS_SHIFT +#define TIM_ADV_CR1_URS_MASK TIM1_CR1_URS_MASK +#define TIM_ADV_CR1_URS(x) TIM1_CR1_URS(x) + +#define TIM_ADV_CR1_UDIS_SHIFT TIM1_CR1_UDIS_SHIFT +#define TIM_ADV_CR1_UDIS_MASK TIM1_CR1_UDIS_MASK +#define TIM_ADV_CR1_UDIS(x) TIM1_CR1_UDIS(x) + +#define TIM_ADV_CR1_CEN_SHIFT TIM1_CR1_CEN_SHIFT +#define TIM_ADV_CR1_CEN_MASK TIM1_CR1_CEN_MASK +#define TIM_ADV_CR1_CEN(x) TIM1_CR1_CEN(x) + +/*! + * @brief TIM_ADV_CR2 Register Bit Definition + */ + +#define TIM_ADV_CR2_OIS4N_SHIFT TIM1_CR2_OIS4N_SHIFT +#define TIM_ADV_CR2_OIS4N_MASK TIM1_CR2_OIS4N_MASK +#define TIM_ADV_CR2_OIS4N(x) TIM1_CR2_OIS4N(x) + +#define TIM_ADV_CR2_OIS4_SHIFT TIM1_CR2_OIS4_SHIFT +#define TIM_ADV_CR2_OIS4_MASK TIM1_CR2_OIS4_MASK +#define TIM_ADV_CR2_OIS4(x) TIM1_CR2_OIS4(x) + +#define TIM_ADV_CR2_OIS3N_SHIFT TIM1_CR2_OIS3N_SHIFT +#define TIM_ADV_CR2_OIS3N_MASK TIM1_CR2_OIS3N_MASK +#define TIM_ADV_CR2_OIS3N(x) TIM1_CR2_OIS3N(x) + +#define TIM_ADV_CR2_OIS3_SHIFT TIM1_CR2_OIS3_SHIFT +#define TIM_ADV_CR2_OIS3_MASK TIM1_CR2_OIS3_MASK +#define TIM_ADV_CR2_OIS3(x) TIM1_CR2_OIS3(x) + +#define TIM_ADV_CR2_OIS2N_SHIFT TIM1_CR2_OIS2N_SHIFT +#define TIM_ADV_CR2_OIS2N_MASK TIM1_CR2_OIS2N_MASK +#define TIM_ADV_CR2_OIS2N(x) TIM1_CR2_OIS2N(x) + +#define TIM_ADV_CR2_OIS2_SHIFT TIM1_CR2_OIS2_SHIFT +#define TIM_ADV_CR2_OIS2_MASK TIM1_CR2_OIS2_MASK +#define TIM_ADV_CR2_OIS2(x) TIM1_CR2_OIS2(x) + +#define TIM_ADV_CR2_OIS1N_SHIFT TIM1_CR2_OIS1N_SHIFT +#define TIM_ADV_CR2_OIS1N_MASK TIM1_CR2_OIS1N_MASK +#define TIM_ADV_CR2_OIS1N(x) TIM1_CR2_OIS1N(x) + +#define TIM_ADV_CR2_OIS1_SHIFT TIM1_CR2_OIS1_SHIFT +#define TIM_ADV_CR2_OIS1_MASK TIM1_CR2_OIS1_MASK +#define TIM_ADV_CR2_OIS1(x) TIM1_CR2_OIS1(x) + +#define TIM_ADV_CR2_TI1S_SHIFT TIM1_CR2_TI1S_SHIFT +#define TIM_ADV_CR2_TI1S_MASK TIM1_CR2_TI1S_MASK +#define TIM_ADV_CR2_TI1S(x) TIM1_CR2_TI1S(x) + +#define TIM_ADV_CR2_MMS_SHIFT TIM1_CR2_MMS_SHIFT +#define TIM_ADV_CR2_MMS_MASK TIM1_CR2_MMS_MASK +#define TIM_ADV_CR2_MMS(x) TIM1_CR2_MMS(x) + +#define TIM_ADV_CR2_CCDS_SHIFT TIM1_CR2_CCDS_SHIFT +#define TIM_ADV_CR2_CCDS_MASK TIM1_CR2_CCDS_MASK +#define TIM_ADV_CR2_CCDS(x) TIM1_CR2_CCDS(x) + +#define TIM_ADV_CR2_CCUS_SHIFT TIM1_CR2_CCUS_SHIFT +#define TIM_ADV_CR2_CCUS_MASK TIM1_CR2_CCUS_MASK +#define TIM_ADV_CR2_CCUS(x) TIM1_CR2_CCUS(x) + +#define TIM_ADV_CR2_CCPC_SHIFT TIM1_CR2_CCPC_SHIFT +#define TIM_ADV_CR2_CCPC_MASK TIM1_CR2_CCPC_MASK +#define TIM_ADV_CR2_CCPC(x) TIM1_CR2_CCPC(x) + +/*! + * @brief TIM_ADV_SMCR Register Bit Definition + */ + +#define TIM_ADV_SMCR_ETP_SHIFT TIM1_SMCR_ETP_SHIFT +#define TIM_ADV_SMCR_ETP_MASK TIM1_SMCR_ETP_MASK +#define TIM_ADV_SMCR_ETP(x) TIM1_SMCR_ETP(x) + +#define TIM_ADV_SMCR_ECE_SHIFT TIM1_SMCR_ECE_SHIFT +#define TIM_ADV_SMCR_ECE_MASK TIM1_SMCR_ECE_MASK +#define TIM_ADV_SMCR_ECE(x) TIM1_SMCR_ECE(x) + +#define TIM_ADV_SMCR_ETPS_SHIFT TIM1_SMCR_ETPS_SHIFT +#define TIM_ADV_SMCR_ETPS_MASK TIM1_SMCR_ETPS_MASK +#define TIM_ADV_SMCR_ETPS(x) TIM1_SMCR_ETPS(x) + +#define TIM_ADV_SMCR_ETF_SHIFT TIM1_SMCR_ETF_SHIFT +#define TIM_ADV_SMCR_ETF_MASK TIM1_SMCR_ETF_MASK +#define TIM_ADV_SMCR_ETF(x) TIM1_SMCR_ETF(x) + +#define TIM_ADV_SMCR_MSM_SHIFT TIM1_SMCR_MSM_SHIFT +#define TIM_ADV_SMCR_MSM_MASK TIM1_SMCR_MSM_MASK +#define TIM_ADV_SMCR_MSM(x) TIM1_SMCR_MSM(x) + +#define TIM_ADV_SMCR_TS_SHIFT TIM1_SMCR_TS_SHIFT +#define TIM_ADV_SMCR_TS_MASK TIM1_SMCR_TS_MASK +#define TIM_ADV_SMCR_TS(x) TIM1_SMCR_TS(x) + +#define TIM_ADV_SMCR_OCCS_SHIFT TIM1_SMCR_OCCS_SHIFT +#define TIM_ADV_SMCR_OCCS_MASK TIM1_SMCR_OCCS_MASK +#define TIM_ADV_SMCR_OCCS(x) TIM1_SMCR_OCCS(x) + +#define TIM_ADV_SMCR_SMS_SHIFT TIM1_SMCR_SMS_SHIFT +#define TIM_ADV_SMCR_SMS_MASK TIM1_SMCR_SMS_MASK +#define TIM_ADV_SMCR_SMS(x) TIM1_SMCR_SMS(x) + +/*! + * @brief TIM_ADV_DIER Register Bit Definition + */ + +#define TIM_ADV_DIER_CC5DE_SHIFT TIM1_DIER_CC5DE_SHIFT +#define TIM_ADV_DIER_CC5DE_MASK TIM1_DIER_CC5DE_MASK +#define TIM_ADV_DIER_CC5DE(x) TIM1_DIER_CC5DE(x) + +#define TIM_ADV_DIER_CC5IE_SHIFT TIM1_DIER_CC5IE_SHIFT +#define TIM_ADV_DIER_CC5IE_MASK TIM1_DIER_CC5IE_MASK +#define TIM_ADV_DIER_CC5IE(x) TIM1_DIER_CC5IE(x) + +#define TIM_ADV_DIER_TDE_SHIFT TIM1_DIER_TDE_SHIFT +#define TIM_ADV_DIER_TDE_MASK TIM1_DIER_TDE_MASK +#define TIM_ADV_DIER_TDE(x) TIM1_DIER_TDE(x) + +#define TIM_ADV_DIER_COMDE_SHIFT TIM1_DIER_COMDE_SHIFT +#define TIM_ADV_DIER_COMDE_MASK TIM1_DIER_COMDE_MASK +#define TIM_ADV_DIER_COMDE(x) TIM1_DIER_COMDE(x) + +#define TIM_ADV_DIER_CC4DE_SHIFT TIM1_DIER_CC4DE_SHIFT +#define TIM_ADV_DIER_CC4DE_MASK TIM1_DIER_CC4DE_MASK +#define TIM_ADV_DIER_CC4DE(x) TIM1_DIER_CC4DE(x) + +#define TIM_ADV_DIER_CC3DE_SHIFT TIM1_DIER_CC3DE_SHIFT +#define TIM_ADV_DIER_CC3DE_MASK TIM1_DIER_CC3DE_MASK +#define TIM_ADV_DIER_CC3DE(x) TIM1_DIER_CC3DE(x) + +#define TIM_ADV_DIER_CC2DE_SHIFT TIM1_DIER_CC2DE_SHIFT +#define TIM_ADV_DIER_CC2DE_MASK TIM1_DIER_CC2DE_MASK +#define TIM_ADV_DIER_CC2DE(x) TIM1_DIER_CC2DE(x) + +#define TIM_ADV_DIER_CC1DE_SHIFT TIM1_DIER_CC1DE_SHIFT +#define TIM_ADV_DIER_CC1DE_MASK TIM1_DIER_CC1DE_MASK +#define TIM_ADV_DIER_CC1DE(x) TIM1_DIER_CC1DE(x) + +#define TIM_ADV_DIER_UDE_SHIFT TIM1_DIER_UDE_SHIFT +#define TIM_ADV_DIER_UDE_MASK TIM1_DIER_UDE_MASK +#define TIM_ADV_DIER_UDE(x) TIM1_DIER_UDE(x) + +#define TIM_ADV_DIER_BIE_SHIFT TIM1_DIER_BIE_SHIFT +#define TIM_ADV_DIER_BIE_MASK TIM1_DIER_BIE_MASK +#define TIM_ADV_DIER_BIE(x) TIM1_DIER_BIE(x) + +#define TIM_ADV_DIER_TIE_SHIFT TIM1_DIER_TIE_SHIFT +#define TIM_ADV_DIER_TIE_MASK TIM1_DIER_TIE_MASK +#define TIM_ADV_DIER_TIE(x) TIM1_DIER_TIE(x) + +#define TIM_ADV_DIER_COMIE_SHIFT TIM1_DIER_COMIE_SHIFT +#define TIM_ADV_DIER_COMIE_MASK TIM1_DIER_COMIE_MASK +#define TIM_ADV_DIER_COMIE(x) TIM1_DIER_COMIE(x) + +#define TIM_ADV_DIER_CC4IE_SHIFT TIM1_DIER_CC4IE_SHIFT +#define TIM_ADV_DIER_CC4IE_MASK TIM1_DIER_CC4IE_MASK +#define TIM_ADV_DIER_CC4IE(x) TIM1_DIER_CC4IE(x) + +#define TIM_ADV_DIER_CC3IE_SHIFT TIM1_DIER_CC3IE_SHIFT +#define TIM_ADV_DIER_CC3IE_MASK TIM1_DIER_CC3IE_MASK +#define TIM_ADV_DIER_CC3IE(x) TIM1_DIER_CC3IE(x) + +#define TIM_ADV_DIER_CC2IE_SHIFT TIM1_DIER_CC2IE_SHIFT +#define TIM_ADV_DIER_CC2IE_MASK TIM1_DIER_CC2IE_MASK +#define TIM_ADV_DIER_CC2IE(x) TIM1_DIER_CC2IE(x) + +#define TIM_ADV_DIER_CC1IE_SHIFT TIM1_DIER_CC1IE_SHIFT +#define TIM_ADV_DIER_CC1IE_MASK TIM1_DIER_CC1IE_MASK +#define TIM_ADV_DIER_CC1IE(x) TIM1_DIER_CC1IE(x) + +#define TIM_ADV_DIER_UIE_SHIFT TIM1_DIER_UIE_SHIFT +#define TIM_ADV_DIER_UIE_MASK TIM1_DIER_UIE_MASK +#define TIM_ADV_DIER_UIE(x) TIM1_DIER_UIE(x) + +/*! + * @brief TIM_ADV_SR Register Bit Definition + */ + +#define TIM_ADV_SR_CC5IF_SHIFT TIM1_SR_CC5IF_SHIFT +#define TIM_ADV_SR_CC5IF_MASK TIM1_SR_CC5IF_MASK +#define TIM_ADV_SR_CC5IF(x) TIM1_SR_CC5IF(x) + +#define TIM_ADV_SR_CC4OF_SHIFT TIM1_SR_CC4OF_SHIFT +#define TIM_ADV_SR_CC4OF_MASK TIM1_SR_CC4OF_MASK +#define TIM_ADV_SR_CC4OF(x) TIM1_SR_CC4OF(x) + +#define TIM_ADV_SR_CC3OF_SHIFT TIM1_SR_CC3OF_SHIFT +#define TIM_ADV_SR_CC3OF_MASK TIM1_SR_CC3OF_MASK +#define TIM_ADV_SR_CC3OF(x) TIM1_SR_CC3OF(x) + +#define TIM_ADV_SR_CC2OF_SHIFT TIM1_SR_CC2OF_SHIFT +#define TIM_ADV_SR_CC2OF_MASK TIM1_SR_CC2OF_MASK +#define TIM_ADV_SR_CC2OF(x) TIM1_SR_CC2OF(x) + +#define TIM_ADV_SR_CC1OF_SHIFT TIM1_SR_CC1OF_SHIFT +#define TIM_ADV_SR_CC1OF_MASK TIM1_SR_CC1OF_MASK +#define TIM_ADV_SR_CC1OF(x) TIM1_SR_CC1OF(x) + +#define TIM_ADV_SR_BIF_SHIFT TIM1_SR_BIF_SHIFT +#define TIM_ADV_SR_BIF_MASK TIM1_SR_BIF_MASK +#define TIM_ADV_SR_BIF(x) TIM1_SR_BIF(x) + +#define TIM_ADV_SR_TIF_SHIFT TIM1_SR_TIF_SHIFT +#define TIM_ADV_SR_TIF_MASK TIM1_SR_TIF_MASK +#define TIM_ADV_SR_TIF(x) TIM1_SR_TIF(x) + +#define TIM_ADV_SR_COMIF_SHIFT TIM1_SR_COMIF_SHIFT +#define TIM_ADV_SR_COMIF_MASK TIM1_SR_COMIF_MASK +#define TIM_ADV_SR_COMIF(x) TIM1_SR_COMIF(x) + +#define TIM_ADV_SR_CC4IF_SHIFT TIM1_SR_CC4IF_SHIFT +#define TIM_ADV_SR_CC4IF_MASK TIM1_SR_CC4IF_MASK +#define TIM_ADV_SR_CC4IF(x) TIM1_SR_CC4IF(x) + +#define TIM_ADV_SR_CC3IF_SHIFT TIM1_SR_CC3IF_SHIFT +#define TIM_ADV_SR_CC3IF_MASK TIM1_SR_CC3IF_MASK +#define TIM_ADV_SR_CC3IF(x) TIM1_SR_CC3IF(x) + +#define TIM_ADV_SR_CC2IF_SHIFT TIM1_SR_CC2IF_SHIFT +#define TIM_ADV_SR_CC2IF_MASK TIM1_SR_CC2IF_MASK +#define TIM_ADV_SR_CC2IF(x) TIM1_SR_CC2IF(x) + +#define TIM_ADV_SR_CC1IF_SHIFT TIM1_SR_CC1IF_SHIFT +#define TIM_ADV_SR_CC1IF_MASK TIM1_SR_CC1IF_MASK +#define TIM_ADV_SR_CC1IF(x) TIM1_SR_CC1IF(x) + +#define TIM_ADV_SR_UIF_SHIFT TIM1_SR_UIF_SHIFT +#define TIM_ADV_SR_UIF_MASK TIM1_SR_UIF_MASK +#define TIM_ADV_SR_UIF(x) TIM1_SR_UIF(x) + +/*! + * @brief TIM_ADV_EGR Register Bit Definition + */ + +#define TIM_ADV_EGR_CC5G_SHIFT TIM1_EGR_CC5G_SHIFT +#define TIM_ADV_EGR_CC5G_MASK TIM1_EGR_CC5G_MASK +#define TIM_ADV_EGR_CC5G(x) TIM1_EGR_CC5G(x) + +#define TIM_ADV_EGR_BG_SHIFT TIM1_EGR_BG_SHIFT +#define TIM_ADV_EGR_BG_MASK TIM1_EGR_BG_MASK +#define TIM_ADV_EGR_BG(x) TIM1_EGR_BG(x) + +#define TIM_ADV_EGR_TG_SHIFT TIM1_EGR_TG_SHIFT +#define TIM_ADV_EGR_TG_MASK TIM1_EGR_TG_MASK +#define TIM_ADV_EGR_TG(x) TIM1_EGR_TG(x) + +#define TIM_ADV_EGR_COMG_SHIFT TIM1_EGR_COMG_SHIFT +#define TIM_ADV_EGR_COMG_MASK TIM1_EGR_COMG_MASK +#define TIM_ADV_EGR_COMG(x) TIM1_EGR_COMG(x) + +#define TIM_ADV_EGR_CC4G_SHIFT TIM1_EGR_CC4G_SHIFT +#define TIM_ADV_EGR_CC4G_MASK TIM1_EGR_CC4G_MASK +#define TIM_ADV_EGR_CC4G(x) TIM1_EGR_CC4G(x) + +#define TIM_ADV_EGR_CC3G_SHIFT TIM1_EGR_CC3G_SHIFT +#define TIM_ADV_EGR_CC3G_MASK TIM1_EGR_CC3G_MASK +#define TIM_ADV_EGR_CC3G(x) TIM1_EGR_CC3G(x) + +#define TIM_ADV_EGR_CC2G_SHIFT TIM1_EGR_CC2G_SHIFT +#define TIM_ADV_EGR_CC2G_MASK TIM1_EGR_CC2G_MASK +#define TIM_ADV_EGR_CC2G(x) TIM1_EGR_CC2G(x) + +#define TIM_ADV_EGR_CC1G_SHIFT TIM1_EGR_CC1G_SHIFT +#define TIM_ADV_EGR_CC1G_MASK TIM1_EGR_CC1G_MASK +#define TIM_ADV_EGR_CC1G(x) TIM1_EGR_CC1G(x) + +#define TIM_ADV_EGR_UG_SHIFT TIM1_EGR_UG_SHIFT +#define TIM_ADV_EGR_UG_MASK TIM1_EGR_UG_MASK +#define TIM_ADV_EGR_UG(x) TIM1_EGR_UG(x) + +/*! + * @brief TIM_ADV_CCMR1 Register Bit Definition + */ + +#define TIM_ADV_CCMR1_OC2CE_SHIFT TIM1_CCMR1_OC2CE_SHIFT +#define TIM_ADV_CCMR1_OC2CE_MASK TIM1_CCMR1_OC2CE_MASK +#define TIM_ADV_CCMR1_OC2CE(x) TIM1_CCMR1_OC2CE(x) + +#define TIM_ADV_CCMR1_OC2M_SHIFT TIM1_CCMR1_OC2M_SHIFT +#define TIM_ADV_CCMR1_OC2M_MASK TIM1_CCMR1_OC2M_MASK +#define TIM_ADV_CCMR1_OC2M(x) TIM1_CCMR1_OC2M(x) + +#define TIM_ADV_CCMR1_OC2PE_SHIFT TIM1_CCMR1_OC2PE_SHIFT +#define TIM_ADV_CCMR1_OC2PE_MASK TIM1_CCMR1_OC2PE_MASK +#define TIM_ADV_CCMR1_OC2PE(x) TIM1_CCMR1_OC2PE(x) + +#define TIM_ADV_CCMR1_OC2FE_SHIFT TIM1_CCMR1_OC2FE_SHIFT +#define TIM_ADV_CCMR1_OC2FE_MASK TIM1_CCMR1_OC2FE_MASK +#define TIM_ADV_CCMR1_OC2FE(x) TIM1_CCMR1_OC2FE(x) + +#define TIM_ADV_CCMR1_CC2S_SHIFT TIM1_CCMR1_CC2S_SHIFT +#define TIM_ADV_CCMR1_CC2S_MASK TIM1_CCMR1_CC2S_MASK +#define TIM_ADV_CCMR1_CC2S(x) TIM1_CCMR1_CC2S(x) + +#define TIM_ADV_CCMR1_OC1CE_SHIFT TIM1_CCMR1_OC1CE_SHIFT +#define TIM_ADV_CCMR1_OC1CE_MASK TIM1_CCMR1_OC1CE_MASK +#define TIM_ADV_CCMR1_OC1CE(x) TIM1_CCMR1_OC1CE(x) + +#define TIM_ADV_CCMR1_OC1M_SHIFT TIM1_CCMR1_OC1M_SHIFT +#define TIM_ADV_CCMR1_OC1M_MASK TIM1_CCMR1_OC1M_MASK +#define TIM_ADV_CCMR1_OC1M(x) TIM1_CCMR1_OC1M(x) + +#define TIM_ADV_CCMR1_OC1PE_SHIFT TIM1_CCMR1_OC1PE_SHIFT +#define TIM_ADV_CCMR1_OC1PE_MASK TIM1_CCMR1_OC1PE_MASK +#define TIM_ADV_CCMR1_OC1PE(x) TIM1_CCMR1_OC1PE(x) + +#define TIM_ADV_CCMR1_OC1FE_SHIFT TIM1_CCMR1_OC1FE_SHIFT +#define TIM_ADV_CCMR1_OC1FE_MASK TIM1_CCMR1_OC1FE_MASK +#define TIM_ADV_CCMR1_OC1FE(x) TIM1_CCMR1_OC1FE(x) + +#define TIM_ADV_CCMR1_CC1S_SHIFT TIM1_CCMR1_CC1S_SHIFT +#define TIM_ADV_CCMR1_CC1S_MASK TIM1_CCMR1_CC1S_MASK +#define TIM_ADV_CCMR1_CC1S(x) TIM1_CCMR1_CC1S(x) + +/*! + * @brief TIM_ADV_CCMR1 Register Bit Definition + */ + +#define TIM_ADV_CCMR1_IC2F_SHIFT TIM1_CCMR1_IC2F_SHIFT +#define TIM_ADV_CCMR1_IC2F_MASK TIM1_CCMR1_IC2F_MASK +#define TIM_ADV_CCMR1_IC2F(x) TIM1_CCMR1_IC2F(x) + +#define TIM_ADV_CCMR1_IC2PSC_SHIFT TIM1_CCMR1_IC2PSC_SHIFT +#define TIM_ADV_CCMR1_IC2PSC_MASK TIM1_CCMR1_IC2PSC_MASK +#define TIM_ADV_CCMR1_IC2PSC(x) TIM1_CCMR1_IC2PSC(x) + +#define TIM_ADV_CCMR1_CC2S_SHIFT TIM1_CCMR1_CC2S_SHIFT +#define TIM_ADV_CCMR1_CC2S_MASK TIM1_CCMR1_CC2S_MASK +#define TIM_ADV_CCMR1_CC2S(x) TIM1_CCMR1_CC2S(x) + +#define TIM_ADV_CCMR1_IC1F_SHIFT TIM1_CCMR1_IC1F_SHIFT +#define TIM_ADV_CCMR1_IC1F_MASK TIM1_CCMR1_IC1F_MASK +#define TIM_ADV_CCMR1_IC1F(x) TIM1_CCMR1_IC1F(x) + +#define TIM_ADV_CCMR1_IC1PSC_SHIFT TIM1_CCMR1_IC1PSC_SHIFT +#define TIM_ADV_CCMR1_IC1PSC_MASK TIM1_CCMR1_IC1PSC_MASK +#define TIM_ADV_CCMR1_IC1PSC(x) TIM1_CCMR1_IC1PSC(x) + +#define TIM_ADV_CCMR1_CC1S_SHIFT TIM1_CCMR1_CC1S_SHIFT +#define TIM_ADV_CCMR1_CC1S_MASK TIM1_CCMR1_CC1S_MASK +#define TIM_ADV_CCMR1_CC1S(x) TIM1_CCMR1_CC1S(x) + +/*! + * @brief TIM_ADV_CCMR2 Register Bit Definition + */ + +#define TIM_ADV_CCMR2_OC4CE_SHIFT TIM1_CCMR2_OC4CE_SHIFT +#define TIM_ADV_CCMR2_OC4CE_MASK TIM1_CCMR2_OC4CE_MASK +#define TIM_ADV_CCMR2_OC4CE(x) TIM1_CCMR2_OC4CE(x) + +#define TIM_ADV_CCMR2_OC4M_SHIFT TIM1_CCMR2_OC4M_SHIFT +#define TIM_ADV_CCMR2_OC4M_MASK TIM1_CCMR2_OC4M_MASK +#define TIM_ADV_CCMR2_OC4M(x) TIM1_CCMR2_OC4M(x) + +#define TIM_ADV_CCMR2_OC4PE_SHIFT TIM1_CCMR2_OC4PE_SHIFT +#define TIM_ADV_CCMR2_OC4PE_MASK TIM1_CCMR2_OC4PE_MASK +#define TIM_ADV_CCMR2_OC4PE(x) TIM1_CCMR2_OC4PE(x) + +#define TIM_ADV_CCMR2_OC4FE_SHIFT TIM1_CCMR2_OC4FE_SHIFT +#define TIM_ADV_CCMR2_OC4FE_MASK TIM1_CCMR2_OC4FE_MASK +#define TIM_ADV_CCMR2_OC4FE(x) TIM1_CCMR2_OC4FE(x) + +#define TIM_ADV_CCMR2_CC4S_SHIFT TIM1_CCMR2_CC4S_SHIFT +#define TIM_ADV_CCMR2_CC4S_MASK TIM1_CCMR2_CC4S_MASK +#define TIM_ADV_CCMR2_CC4S(x) TIM1_CCMR2_CC4S(x) + +#define TIM_ADV_CCMR2_OC3CE_SHIFT TIM1_CCMR2_OC3CE_SHIFT +#define TIM_ADV_CCMR2_OC3CE_MASK TIM1_CCMR2_OC3CE_MASK +#define TIM_ADV_CCMR2_OC3CE(x) TIM1_CCMR2_OC3CE(x) + +#define TIM_ADV_CCMR2_OC3M_SHIFT TIM1_CCMR2_OC3M_SHIFT +#define TIM_ADV_CCMR2_OC3M_MASK TIM1_CCMR2_OC3M_MASK +#define TIM_ADV_CCMR2_OC3M(x) TIM1_CCMR2_OC3M(x) + +#define TIM_ADV_CCMR2_OC3PE_SHIFT TIM1_CCMR2_OC3PE_SHIFT +#define TIM_ADV_CCMR2_OC3PE_MASK TIM1_CCMR2_OC3PE_MASK +#define TIM_ADV_CCMR2_OC3PE(x) TIM1_CCMR2_OC3PE(x) + +#define TIM_ADV_CCMR2_OC3FE_SHIFT TIM1_CCMR2_OC3FE_SHIFT +#define TIM_ADV_CCMR2_OC3FE_MASK TIM1_CCMR2_OC3FE_MASK +#define TIM_ADV_CCMR2_OC3FE(x) TIM1_CCMR2_OC3FE(x) + +#define TIM_ADV_CCMR2_CC3S_SHIFT TIM1_CCMR2_CC3S_SHIFT +#define TIM_ADV_CCMR2_CC3S_MASK TIM1_CCMR2_CC3S_MASK +#define TIM_ADV_CCMR2_CC3S(x) TIM1_CCMR2_CC3S(x) + +/*! + * @brief TIM_ADV_CCMR2 Register Bit Definition + */ + +#define TIM_ADV_CCMR2_IC4F_SHIFT TIM1_CCMR2_IC4F_SHIFT +#define TIM_ADV_CCMR2_IC4F_MASK TIM1_CCMR2_IC4F_MASK +#define TIM_ADV_CCMR2_IC4F(x) TIM1_CCMR2_IC4F(x) + +#define TIM_ADV_CCMR2_IC4PSC_SHIFT TIM1_CCMR2_IC4PSC_SHIFT +#define TIM_ADV_CCMR2_IC4PSC_MASK TIM1_CCMR2_IC4PSC_MASK +#define TIM_ADV_CCMR2_IC4PSC(x) TIM1_CCMR2_IC4PSC(x) + +#define TIM_ADV_CCMR2_CC4S_SHIFT TIM1_CCMR2_CC4S_SHIFT +#define TIM_ADV_CCMR2_CC4S_MASK TIM1_CCMR2_CC4S_MASK +#define TIM_ADV_CCMR2_CC4S(x) TIM1_CCMR2_CC4S(x) + +#define TIM_ADV_CCMR2_IC3F_SHIFT TIM1_CCMR2_IC3F_SHIFT +#define TIM_ADV_CCMR2_IC3F_MASK TIM1_CCMR2_IC3F_MASK +#define TIM_ADV_CCMR2_IC3F(x) TIM1_CCMR2_IC3F(x) + +#define TIM_ADV_CCMR2_IC3PSC_SHIFT TIM1_CCMR2_IC3PSC_SHIFT +#define TIM_ADV_CCMR2_IC3PSC_MASK TIM1_CCMR2_IC3PSC_MASK +#define TIM_ADV_CCMR2_IC3PSC(x) TIM1_CCMR2_IC3PSC(x) + +#define TIM_ADV_CCMR2_CC3S_SHIFT TIM1_CCMR2_CC3S_SHIFT +#define TIM_ADV_CCMR2_CC3S_MASK TIM1_CCMR2_CC3S_MASK +#define TIM_ADV_CCMR2_CC3S(x) TIM1_CCMR2_CC3S(x) + +/*! + * @brief TIM_ADV_CCER Register Bit Definition + */ + +#define TIM_ADV_CCER_CC4NP_SHIFT TIM1_CCER_CC4NP_SHIFT +#define TIM_ADV_CCER_CC4NP_MASK TIM1_CCER_CC4NP_MASK +#define TIM_ADV_CCER_CC4NP(x) TIM1_CCER_CC4NP(x) + +#define TIM_ADV_CCER_CC4NE_SHIFT TIM1_CCER_CC4NE_SHIFT +#define TIM_ADV_CCER_CC4NE_MASK TIM1_CCER_CC4NE_MASK +#define TIM_ADV_CCER_CC4NE(x) TIM1_CCER_CC4NE(x) + +#define TIM_ADV_CCER_CC4P_SHIFT TIM1_CCER_CC4P_SHIFT +#define TIM_ADV_CCER_CC4P_MASK TIM1_CCER_CC4P_MASK +#define TIM_ADV_CCER_CC4P(x) TIM1_CCER_CC4P(x) + +#define TIM_ADV_CCER_CC4E_SHIFT TIM1_CCER_CC4E_SHIFT +#define TIM_ADV_CCER_CC4E_MASK TIM1_CCER_CC4E_MASK +#define TIM_ADV_CCER_CC4E(x) TIM1_CCER_CC4E(x) + +#define TIM_ADV_CCER_CC3NP_SHIFT TIM1_CCER_CC3NP_SHIFT +#define TIM_ADV_CCER_CC3NP_MASK TIM1_CCER_CC3NP_MASK +#define TIM_ADV_CCER_CC3NP(x) TIM1_CCER_CC3NP(x) + +#define TIM_ADV_CCER_CC3NE_SHIFT TIM1_CCER_CC3NE_SHIFT +#define TIM_ADV_CCER_CC3NE_MASK TIM1_CCER_CC3NE_MASK +#define TIM_ADV_CCER_CC3NE(x) TIM1_CCER_CC3NE(x) + +#define TIM_ADV_CCER_CC3P_SHIFT TIM1_CCER_CC3P_SHIFT +#define TIM_ADV_CCER_CC3P_MASK TIM1_CCER_CC3P_MASK +#define TIM_ADV_CCER_CC3P(x) TIM1_CCER_CC3P(x) + +#define TIM_ADV_CCER_CC3E_SHIFT TIM1_CCER_CC3E_SHIFT +#define TIM_ADV_CCER_CC3E_MASK TIM1_CCER_CC3E_MASK +#define TIM_ADV_CCER_CC3E(x) TIM1_CCER_CC3E(x) + +#define TIM_ADV_CCER_CC2NP_SHIFT TIM1_CCER_CC2NP_SHIFT +#define TIM_ADV_CCER_CC2NP_MASK TIM1_CCER_CC2NP_MASK +#define TIM_ADV_CCER_CC2NP(x) TIM1_CCER_CC2NP(x) + +#define TIM_ADV_CCER_CC2NE_SHIFT TIM1_CCER_CC2NE_SHIFT +#define TIM_ADV_CCER_CC2NE_MASK TIM1_CCER_CC2NE_MASK +#define TIM_ADV_CCER_CC2NE(x) TIM1_CCER_CC2NE(x) + +#define TIM_ADV_CCER_CC2P_SHIFT TIM1_CCER_CC2P_SHIFT +#define TIM_ADV_CCER_CC2P_MASK TIM1_CCER_CC2P_MASK +#define TIM_ADV_CCER_CC2P(x) TIM1_CCER_CC2P(x) + +#define TIM_ADV_CCER_CC2E_SHIFT TIM1_CCER_CC2E_SHIFT +#define TIM_ADV_CCER_CC2E_MASK TIM1_CCER_CC2E_MASK +#define TIM_ADV_CCER_CC2E(x) TIM1_CCER_CC2E(x) + +#define TIM_ADV_CCER_CC1NP_SHIFT TIM1_CCER_CC1NP_SHIFT +#define TIM_ADV_CCER_CC1NP_MASK TIM1_CCER_CC1NP_MASK +#define TIM_ADV_CCER_CC1NP(x) TIM1_CCER_CC1NP(x) + +#define TIM_ADV_CCER_CC1NE_SHIFT TIM1_CCER_CC1NE_SHIFT +#define TIM_ADV_CCER_CC1NE_MASK TIM1_CCER_CC1NE_MASK +#define TIM_ADV_CCER_CC1NE(x) TIM1_CCER_CC1NE(x) + +#define TIM_ADV_CCER_CC1P_SHIFT TIM1_CCER_CC1P_SHIFT +#define TIM_ADV_CCER_CC1P_MASK TIM1_CCER_CC1P_MASK +#define TIM_ADV_CCER_CC1P(x) TIM1_CCER_CC1P(x) + +#define TIM_ADV_CCER_CC1E_SHIFT TIM1_CCER_CC1E_SHIFT +#define TIM_ADV_CCER_CC1E_MASK TIM1_CCER_CC1E_MASK +#define TIM_ADV_CCER_CC1E(x) TIM1_CCER_CC1E(x) + +/*! + * @brief TIM_ADV_CNT Register Bit Definition + */ + +#define TIM_ADV_CNT_CNT_SHIFT TIM1_CNT_CNT_SHIFT +#define TIM_ADV_CNT_CNT_MASK TIM1_CNT_CNT_MASK +#define TIM_ADV_CNT_CNT(x) TIM1_CNT_CNT(x) + +/*! + * @brief TIM_ADV_PSC Register Bit Definition + */ + +#define TIM_ADV_PSC_PSC_SHIFT TIM1_PSC_PSC_SHIFT +#define TIM_ADV_PSC_PSC_MASK TIM1_PSC_PSC_MASK +#define TIM_ADV_PSC_PSC(x) TIM1_PSC_PSC(x) + +/*! + * @brief TIM_ADV_ARR Register Bit Definition + */ + +#define TIM_ADV_ARR_ARR_SHIFT TIM1_ARR_ARR_SHIFT +#define TIM_ADV_ARR_ARR_MASK TIM1_ARR_ARR_MASK +#define TIM_ADV_ARR_ARR(x) TIM1_ARR_ARR(x) + +/*! + * @brief TIM_ADV_RCR Register Bit Definition + */ + +#define TIM_ADV_RCR_REPCNT_SHIFT TIM1_RCR_REPCNT_SHIFT +#define TIM_ADV_RCR_REPCNT_MASK TIM1_RCR_REPCNT_MASK +#define TIM_ADV_RCR_REPCNT(x) TIM1_RCR_REPCNT(x) + +#define TIM_ADV_RCR_REP_SHIFT TIM1_RCR_REP_SHIFT +#define TIM_ADV_RCR_REP_MASK TIM1_RCR_REP_MASK +#define TIM_ADV_RCR_REP(x) TIM1_RCR_REP(x) + +/*! + * @brief TIM_ADV_CCR Register Bit Definition + */ + +#define TIM_ADV_CCR_CCR_SHIFT TIM1_CCR_CCR_SHIFT +#define TIM_ADV_CCR_CCR_MASK TIM1_CCR_CCR_MASK +#define TIM_ADV_CCR_CCR(x) TIM1_CCR_CCR(x) + +/*! + * @brief TIM_ADV_BDTR Register Bit Definition + */ + +#define TIM_ADV_BDTR_DOE_SHIFT (16) +#define TIM_ADV_BDTR_DOE_MASK (0x01U << TIM1_BDTR_DOE_SHIFT) +#define TIM_ADV_BDTR_DOE(x) (((uint32_t)(((uint32_t)(x)) << TIM1_BDTR_DOE_SHIFT)) & TIM1_BDTR_DOE_MASK) + +#define TIM_ADV_BDTR_MOE_SHIFT TIM1_BDTR_MOE_SHIFT +#define TIM_ADV_BDTR_MOE_MASK TIM1_BDTR_MOE_MASK +#define TIM_ADV_BDTR_MOE(x) TIM1_BDTR_MOE(x) + +#define TIM_ADV_BDTR_AOE_SHIFT TIM1_BDTR_AOE_SHIFT +#define TIM_ADV_BDTR_AOE_MASK TIM1_BDTR_AOE_MASK +#define TIM_ADV_BDTR_AOE(x) TIM1_BDTR_AOE(x) + +#define TIM_ADV_BDTR_BKP_SHIFT TIM1_BDTR_BKP_SHIFT +#define TIM_ADV_BDTR_BKP_MASK TIM1_BDTR_BKP_MASK +#define TIM_ADV_BDTR_BKP(x) TIM1_BDTR_BKP(x) + +#define TIM_ADV_BDTR_BKE_SHIFT TIM1_BDTR_BKE_SHIFT +#define TIM_ADV_BDTR_BKE_MASK TIM1_BDTR_BKE_MASK +#define TIM_ADV_BDTR_BKE(x) TIM1_BDTR_BKE(x) + +#define TIM_ADV_BDTR_OSSR_SHIFT TIM1_BDTR_OSSR_SHIFT +#define TIM_ADV_BDTR_OSSR_MASK TIM1_BDTR_OSSR_MASK +#define TIM_ADV_BDTR_OSSR(x) TIM1_BDTR_OSSR(x) + +#define TIM_ADV_BDTR_OSSI_SHIFT TIM1_BDTR_OSSI_SHIFT +#define TIM_ADV_BDTR_OSSI_MASK TIM1_BDTR_OSSI_MASK +#define TIM_ADV_BDTR_OSSI(x) TIM1_BDTR_OSSI(x) + +#define TIM_ADV_BDTR_LOCK_SHIFT TIM1_BDTR_LOCK_SHIFT +#define TIM_ADV_BDTR_LOCK_MASK TIM1_BDTR_LOCK_MASK +#define TIM_ADV_BDTR_LOCK(x) TIM1_BDTR_LOCK(x) + +#define TIM_ADV_BDTR_DTG_SHIFT TIM1_BDTR_DTG_SHIFT +#define TIM_ADV_BDTR_DTG_MASK TIM1_BDTR_DTG_MASK +#define TIM_ADV_BDTR_DTG(x) TIM1_BDTR_DTG(x) + +/*! + * @brief TIM_ADV_DCR Register Bit Definition + */ + +#define TIM_ADV_DCR_DBL_SHIFT TIM1_DCR_DBL_SHIFT +#define TIM_ADV_DCR_DBL_MASK TIM1_DCR_DBL_MASK +#define TIM_ADV_DCR_DBL(x) TIM1_DCR_DBL(x) + +#define TIM_ADV_DCR_DBA_SHIFT TIM1_DCR_DBA_SHIFT +#define TIM_ADV_DCR_DBA_MASK TIM1_DCR_DBA_MASK +#define TIM_ADV_DCR_DBA(x) TIM1_DCR_DBA(x) + +/*! + * @brief TIM_ADV_DMAR Register Bit Definition + */ + +#define TIM_ADV_DMAR_DMAB_SHIFT TIM1_DMAR_DMAB_SHIFT +#define TIM_ADV_DMAR_DMAB_MASK TIM1_DMAR_DMAB_MASK +#define TIM_ADV_DMAR_DMAB(x) TIM1_DMAR_DMAB(x) + +/*! + * @brief TIM_ADV_CCMR3 Register Bit Definition + */ + +#define TIM_ADV_CCMR3_OC5M_SHIFT TIM1_CCMR3_OC5M_SHIFT +#define TIM_ADV_CCMR3_OC5M_MASK TIM1_CCMR3_OC5M_MASK +#define TIM_ADV_CCMR3_OC5M(x) TIM1_CCMR3_OC5M(x) + +#define TIM_ADV_CCMR3_OC5PE_SHIFT TIM1_CCMR3_OC5PE_SHIFT +#define TIM_ADV_CCMR3_OC5PE_MASK TIM1_CCMR3_OC5PE_MASK +#define TIM_ADV_CCMR3_OC5PE(x) TIM1_CCMR3_OC5PE(x) + +#define TIM_ADV_CCMR3_OC5FE_SHIFT TIM1_CCMR3_OC5FE_SHIFT +#define TIM_ADV_CCMR3_OC5FE_MASK TIM1_CCMR3_OC5FE_MASK +#define TIM_ADV_CCMR3_OC5FE(x) TIM1_CCMR3_OC5FE(x) + +/*! + * @brief TIM_ADV_CCR5 Register Bit Definition + */ + +#define TIM_ADV_CCR5_CCR5_SHIFT TIM1_CCR5_CCR5_SHIFT +#define TIM_ADV_CCR5_CCR5_MASK TIM1_CCR5_CCR5_MASK +#define TIM_ADV_CCR5_CCR5(x) TIM1_CCR5_CCR5(x) + +/*! + * @brief TIM_ADV_PDER Register Bit Definition + */ + +#define TIM_ADV_PDER_CCR5SHIFTEN_SHIFT TIM1_PDER_CCR5SHIFTEN_SHIFT +#define TIM_ADV_PDER_CCR5SHIFTEN_MASK TIM1_PDER_CCR5SHIFTEN_MASK +#define TIM_ADV_PDER_CCR5SHIFTEN(x) TIM1_PDER_CCR5SHIFTEN(x) + +#define TIM_ADV_PDER_CCR4SHIFTEN_SHIFT TIM1_PDER_CCR4SHIFTEN_SHIFT +#define TIM_ADV_PDER_CCR4SHIFTEN_MASK TIM1_PDER_CCR4SHIFTEN_MASK +#define TIM_ADV_PDER_CCR4SHIFTEN(x) TIM1_PDER_CCR4SHIFTEN(x) + +#define TIM_ADV_PDER_CCR3SHIFTEN_SHIFT TIM1_PDER_CCR3SHIFTEN_SHIFT +#define TIM_ADV_PDER_CCR3SHIFTEN_MASK TIM1_PDER_CCR3SHIFTEN_MASK +#define TIM_ADV_PDER_CCR3SHIFTEN(x) TIM1_PDER_CCR3SHIFTEN(x) + +#define TIM_ADV_PDER_CCR2SHIFTEN_SHIFT TIM1_PDER_CCR2SHIFTEN_SHIFT +#define TIM_ADV_PDER_CCR2SHIFTEN_MASK TIM1_PDER_CCR2SHIFTEN_MASK +#define TIM_ADV_PDER_CCR2SHIFTEN(x) TIM1_PDER_CCR2SHIFTEN(x) + +#define TIM_ADV_PDER_CCR1SHIFTEN_SHIFT TIM1_PDER_CCR1SHIFTEN_SHIFT +#define TIM_ADV_PDER_CCR1SHIFTEN_MASK TIM1_PDER_CCR1SHIFTEN_MASK +#define TIM_ADV_PDER_CCR1SHIFTEN(x) TIM1_PDER_CCR1SHIFTEN(x) + +#define TIM_ADV_PDER_CCDREPE_SHIFT TIM1_PDER_CCDREPE_SHIFT +#define TIM_ADV_PDER_CCDREPE_MASK TIM1_PDER_CCDREPE_MASK +#define TIM_ADV_PDER_CCDREPE(x) TIM1_PDER_CCDREPE(x) + +/*! + * @brief TIM_ADV_CCRFALL Register Bit Definition + */ + +#define TIM_ADV_CCRFALL_CCRFALL_SHIFT TIM1_CCRFALL_CCRFALL_SHIFT +#define TIM_ADV_CCRFALL_CCRFALL_MASK TIM1_CCRFALL_CCRFALL_MASK +#define TIM_ADV_CCRFALL_CCRFALL(x) TIM1_CCRFALL_CCRFALL(x) + +/*! + * @brief TIM_ADV_BKINF Register Bit Definition + */ + +#define TIM_ADV_BKINF_COMPBKINSEL_SHIFT TIM1_BKINF_COMPBKINSEL_SHIFT +#define TIM_ADV_BKINF_COMPBKINSEL_MASK TIM1_BKINF_COMPBKINSEL_MASK +#define TIM_ADV_BKINF_COMPBKINSEL(x) TIM1_BKINF_COMPBKINSEL(x) + +#define TIM_ADV_BKINF_IOBKINSEL_SHIFT TIM1_BKINF_IOBKINSEL_SHIFT +#define TIM_ADV_BKINF_IOBKINSEL_MASK TIM1_BKINF_IOBKINSEL_MASK +#define TIM_ADV_BKINF_IOBKINSEL(x) TIM1_BKINF_IOBKINSEL(x) + +#define TIM_ADV_BKINF_CSSBKINSEL_SHIFT TIM1_BKINF_CSSBKINSEL_SHIFT +#define TIM_ADV_BKINF_CSSBKINSEL_MASK TIM1_BKINF_CSSBKINSEL_MASK +#define TIM_ADV_BKINF_CSSBKINSEL(x) TIM1_BKINF_CSSBKINSEL(x) + +#define TIM_ADV_BKINF_BKINF_SHIFT TIM1_BKINF_BKINF_SHIFT +#define TIM_ADV_BKINF_BKINF_MASK TIM1_BKINF_BKINF_MASK +#define TIM_ADV_BKINF_BKINF(x) TIM1_BKINF_BKINF(x) + +#define TIM_ADV_BKINF_BKINFE_SHIFT TIM1_BKINF_BKINFE_SHIFT +#define TIM_ADV_BKINF_BKINFE_MASK TIM1_BKINF_BKINFE_MASK +#define TIM_ADV_BKINF_BKINFE(x) TIM1_BKINF_BKINFE(x) + +/*! + * @} + */ /* end of group TIM_ADV_Register_Masks */ + +/******************************************************************************* + * TIM2 Type + ******************************************************************************/ +/*! + * @addtogroup TIM_32B_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief TIM_32B_CR1 Register Bit Definition + */ + +#define TIM_32B_CR1_CKD_SHIFT TIM2_CR1_CKD_SHIFT +#define TIM_32B_CR1_CKD_MASK TIM2_CR1_CKD_MASK +#define TIM_32B_CR1_CKD(x) TIM2_CR1_CKD(x) + +#define TIM_32B_CR1_ARPE_SHIFT TIM2_CR1_ARPE_SHIFT +#define TIM_32B_CR1_ARPE_MASK TIM2_CR1_ARPE_MASK +#define TIM_32B_CR1_ARPE(x) TIM2_CR1_ARPE(x) + +#define TIM_32B_CR1_CMS_SHIFT TIM2_CR1_CMS_SHIFT +#define TIM_32B_CR1_CMS_MASK TIM2_CR1_CMS_MASK +#define TIM_32B_CR1_CMS(x) TIM2_CR1_CMS(x) + +#define TIM_32B_CR1_DIR_SHIFT TIM2_CR1_DIR_SHIFT +#define TIM_32B_CR1_DIR_MASK TIM2_CR1_DIR_MASK +#define TIM_32B_CR1_DIR(x) TIM2_CR1_DIR(x) + +#define TIM_32B_CR1_OPM_SHIFT TIM2_CR1_OPM_SHIFT +#define TIM_32B_CR1_OPM_MASK TIM2_CR1_OPM_MASK +#define TIM_32B_CR1_OPM(x) TIM2_CR1_OPM(x) + +#define TIM_32B_CR1_URS_SHIFT TIM2_CR1_URS_SHIFT +#define TIM_32B_CR1_URS_MASK TIM2_CR1_URS_MASK +#define TIM_32B_CR1_URS(x) TIM2_CR1_URS(x) + +#define TIM_32B_CR1_UDIS_SHIFT TIM2_CR1_UDIS_SHIFT +#define TIM_32B_CR1_UDIS_MASK TIM2_CR1_UDIS_MASK +#define TIM_32B_CR1_UDIS(x) TIM2_CR1_UDIS(x) + +#define TIM_32B_CR1_CEN_SHIFT TIM2_CR1_CEN_SHIFT +#define TIM_32B_CR1_CEN_MASK TIM2_CR1_CEN_MASK +#define TIM_32B_CR1_CEN(x) TIM2_CR1_CEN(x) + +/*! + * @brief TIM_32B_CR2 Register Bit Definition + */ + +#define TIM_32B_CR2_TI1S_SHIFT TIM2_CR2_TI1S_SHIFT +#define TIM_32B_CR2_TI1S_MASK TIM2_CR2_TI1S_MASK +#define TIM_32B_CR2_TI1S(x) TIM2_CR2_TI1S(x) + +#define TIM_32B_CR2_MMS_SHIFT TIM2_CR2_MMS_SHIFT +#define TIM_32B_CR2_MMS_MASK TIM2_CR2_MMS_MASK +#define TIM_32B_CR2_MMS(x) TIM2_CR2_MMS(x) + +#define TIM_32B_CR2_CCDS_SHIFT TIM2_CR2_CCDS_SHIFT +#define TIM_32B_CR2_CCDS_MASK TIM2_CR2_CCDS_MASK +#define TIM_32B_CR2_CCDS(x) TIM2_CR2_CCDS(x) + +/*! + * @brief TIM_32B_SMCR Register Bit Definition + */ + +#define TIM_32B_SMCR_ETP_SHIFT TIM2_SMCR_ETP_SHIFT +#define TIM_32B_SMCR_ETP_MASK TIM2_SMCR_ETP_MASK +#define TIM_32B_SMCR_ETP(x) TIM2_SMCR_ETP(x) + +#define TIM_32B_SMCR_ECE_SHIFT TIM2_SMCR_ECE_SHIFT +#define TIM_32B_SMCR_ECE_MASK TIM2_SMCR_ECE_MASK +#define TIM_32B_SMCR_ECE(x) TIM2_SMCR_ECE(x) + +#define TIM_32B_SMCR_ETPS_SHIFT TIM2_SMCR_ETPS_SHIFT +#define TIM_32B_SMCR_ETPS_MASK TIM2_SMCR_ETPS_MASK +#define TIM_32B_SMCR_ETPS(x) TIM2_SMCR_ETPS(x) + +#define TIM_32B_SMCR_ETF_SHIFT TIM2_SMCR_ETF_SHIFT +#define TIM_32B_SMCR_ETF_MASK TIM2_SMCR_ETF_MASK +#define TIM_32B_SMCR_ETF(x) TIM2_SMCR_ETF(x) + +#define TIM_32B_SMCR_MSM_SHIFT TIM2_SMCR_MSM_SHIFT +#define TIM_32B_SMCR_MSM_MASK TIM2_SMCR_MSM_MASK +#define TIM_32B_SMCR_MSM(x) TIM2_SMCR_MSM(x) + +#define TIM_32B_SMCR_TS_SHIFT TIM2_SMCR_TS_SHIFT +#define TIM_32B_SMCR_TS_MASK TIM2_SMCR_TS_MASK +#define TIM_32B_SMCR_TS(x) TIM2_SMCR_TS(x) + +#define TIM_32B_SMCR_OCCS_SHIFT TIM2_SMCR_OCCS_SHIFT +#define TIM_32B_SMCR_OCCS_MASK TIM2_SMCR_OCCS_MASK +#define TIM_32B_SMCR_OCCS(x) TIM2_SMCR_OCCS(x) + +#define TIM_32B_SMCR_SMS_SHIFT TIM2_SMCR_SMS_SHIFT +#define TIM_32B_SMCR_SMS_MASK TIM2_SMCR_SMS_MASK +#define TIM_32B_SMCR_SMS(x) TIM2_SMCR_SMS(x) + +/*! + * @brief TIM_32B_DIER Register Bit Definition + */ + +#define TIM_32B_DIER_TDE_SHIFT TIM2_DIER_TDE_SHIFT +#define TIM_32B_DIER_TDE_MASK TIM2_DIER_TDE_MASK +#define TIM_32B_DIER_TDE(x) TIM2_DIER_TDE(x) + +#define TIM_32B_DIER_CC4DE_SHIFT TIM2_DIER_CC4DE_SHIFT +#define TIM_32B_DIER_CC4DE_MASK TIM2_DIER_CC4DE_MASK +#define TIM_32B_DIER_CC4DE(x) TIM2_DIER_CC4DE(x) + +#define TIM_32B_DIER_CC3DE_SHIFT TIM2_DIER_CC3DE_SHIFT +#define TIM_32B_DIER_CC3DE_MASK TIM2_DIER_CC3DE_MASK +#define TIM_32B_DIER_CC3DE(x) TIM2_DIER_CC3DE(x) + +#define TIM_32B_DIER_CC2DE_SHIFT TIM2_DIER_CC2DE_SHIFT +#define TIM_32B_DIER_CC2DE_MASK TIM2_DIER_CC2DE_MASK +#define TIM_32B_DIER_CC2DE(x) TIM2_DIER_CC2DE(x) + +#define TIM_32B_DIER_CC1DE_SHIFT TIM2_DIER_CC1DE_SHIFT +#define TIM_32B_DIER_CC1DE_MASK TIM2_DIER_CC1DE_MASK +#define TIM_32B_DIER_CC1DE(x) TIM2_DIER_CC1DE(x) + +#define TIM_32B_DIER_UDE_SHIFT TIM2_DIER_UDE_SHIFT +#define TIM_32B_DIER_UDE_MASK TIM2_DIER_UDE_MASK +#define TIM_32B_DIER_UDE(x) TIM2_DIER_UDE(x) + +#define TIM_32B_DIER_TIE_SHIFT TIM2_DIER_TIE_SHIFT +#define TIM_32B_DIER_TIE_MASK TIM2_DIER_TIE_MASK +#define TIM_32B_DIER_TIE(x) TIM2_DIER_TIE(x) + +#define TIM_32B_DIER_CC4IE_SHIFT TIM2_DIER_CC4IE_SHIFT +#define TIM_32B_DIER_CC4IE_MASK TIM2_DIER_CC4IE_MASK +#define TIM_32B_DIER_CC4IE(x) TIM2_DIER_CC4IE(x) + +#define TIM_32B_DIER_CC3IE_SHIFT TIM2_DIER_CC3IE_SHIFT +#define TIM_32B_DIER_CC3IE_MASK TIM2_DIER_CC3IE_MASK +#define TIM_32B_DIER_CC3IE(x) TIM2_DIER_CC3IE(x) + +#define TIM_32B_DIER_CC2IE_SHIFT TIM2_DIER_CC2IE_SHIFT +#define TIM_32B_DIER_CC2IE_MASK TIM2_DIER_CC2IE_MASK +#define TIM_32B_DIER_CC2IE(x) TIM2_DIER_CC2IE(x) + +#define TIM_32B_DIER_CC1IE_SHIFT TIM2_DIER_CC1IE_SHIFT +#define TIM_32B_DIER_CC1IE_MASK TIM2_DIER_CC1IE_MASK +#define TIM_32B_DIER_CC1IE(x) TIM2_DIER_CC1IE(x) + +#define TIM_32B_DIER_UIE_SHIFT TIM2_DIER_UIE_SHIFT +#define TIM_32B_DIER_UIE_MASK TIM2_DIER_UIE_MASK +#define TIM_32B_DIER_UIE(x) TIM2_DIER_UIE(x) + +/*! + * @brief TIM_32B_SR Register Bit Definition + */ + +#define TIM_32B_SR_CC4OF_SHIFT TIM2_SR_CC4OF_SHIFT +#define TIM_32B_SR_CC4OF_MASK TIM2_SR_CC4OF_MASK +#define TIM_32B_SR_CC4OF(x) TIM2_SR_CC4OF(x) + +#define TIM_32B_SR_CC3OF_SHIFT TIM2_SR_CC3OF_SHIFT +#define TIM_32B_SR_CC3OF_MASK TIM2_SR_CC3OF_MASK +#define TIM_32B_SR_CC3OF(x) TIM2_SR_CC3OF(x) + +#define TIM_32B_SR_CC2OF_SHIFT TIM2_SR_CC2OF_SHIFT +#define TIM_32B_SR_CC2OF_MASK TIM2_SR_CC2OF_MASK +#define TIM_32B_SR_CC2OF(x) TIM2_SR_CC2OF(x) + +#define TIM_32B_SR_CC1OF_SHIFT TIM2_SR_CC1OF_SHIFT +#define TIM_32B_SR_CC1OF_MASK TIM2_SR_CC1OF_MASK +#define TIM_32B_SR_CC1OF(x) TIM2_SR_CC1OF(x) + +#define TIM_32B_SR_TIF_SHIFT TIM2_SR_TIF_SHIFT +#define TIM_32B_SR_TIF_MASK TIM2_SR_TIF_MASK +#define TIM_32B_SR_TIF(x) TIM2_SR_TIF(x) + +#define TIM_32B_SR_CC4IF_SHIFT TIM2_SR_CC4IF_SHIFT +#define TIM_32B_SR_CC4IF_MASK TIM2_SR_CC4IF_MASK +#define TIM_32B_SR_CC4IF(x) TIM2_SR_CC4IF(x) + +#define TIM_32B_SR_CC3IF_SHIFT TIM2_SR_CC3IF_SHIFT +#define TIM_32B_SR_CC3IF_MASK TIM2_SR_CC3IF_MASK +#define TIM_32B_SR_CC3IF(x) TIM2_SR_CC3IF(x) + +#define TIM_32B_SR_CC2IF_SHIFT TIM2_SR_CC2IF_SHIFT +#define TIM_32B_SR_CC2IF_MASK TIM2_SR_CC2IF_MASK +#define TIM_32B_SR_CC2IF(x) TIM2_SR_CC2IF(x) + +#define TIM_32B_SR_CC1IF_SHIFT TIM2_SR_CC1IF_SHIFT +#define TIM_32B_SR_CC1IF_MASK TIM2_SR_CC1IF_MASK +#define TIM_32B_SR_CC1IF(x) TIM2_SR_CC1IF(x) + +#define TIM_32B_SR_UIF_SHIFT TIM2_SR_UIF_SHIFT +#define TIM_32B_SR_UIF_MASK TIM2_SR_UIF_MASK +#define TIM_32B_SR_UIF(x) TIM2_SR_UIF(x) + +/*! + * @brief TIM_32B_EGR Register Bit Definition + */ + +#define TIM_32B_EGR_TG_SHIFT TIM2_EGR_TG_SHIFT +#define TIM_32B_EGR_TG_MASK TIM2_EGR_TG_MASK +#define TIM_32B_EGR_TG(x) TIM2_EGR_TG(x) + +#define TIM_32B_EGR_COMG_SHIFT TIM2_EGR_COMG_SHIFT +#define TIM_32B_EGR_COMG_MASK TIM2_EGR_COMG_MASK +#define TIM_32B_EGR_COMG(x) TIM2_EGR_COMG(x) + +#define TIM_32B_EGR_CC4G_SHIFT TIM2_EGR_CC4G_SHIFT +#define TIM_32B_EGR_CC4G_MASK TIM2_EGR_CC4G_MASK +#define TIM_32B_EGR_CC4G(x) TIM2_EGR_CC4G(x) + +#define TIM_32B_EGR_CC3G_SHIFT TIM2_EGR_CC3G_SHIFT +#define TIM_32B_EGR_CC3G_MASK TIM2_EGR_CC3G_MASK +#define TIM_32B_EGR_CC3G(x) TIM2_EGR_CC3G(x) + +#define TIM_32B_EGR_CC2G_SHIFT TIM2_EGR_CC2G_SHIFT +#define TIM_32B_EGR_CC2G_MASK TIM2_EGR_CC2G_MASK +#define TIM_32B_EGR_CC2G(x) TIM2_EGR_CC2G(x) + +#define TIM_32B_EGR_CC1G_SHIFT TIM2_EGR_CC1G_SHIFT +#define TIM_32B_EGR_CC1G_MASK TIM2_EGR_CC1G_MASK +#define TIM_32B_EGR_CC1G(x) TIM2_EGR_CC1G(x) + +#define TIM_32B_EGR_UG_SHIFT TIM2_EGR_UG_SHIFT +#define TIM_32B_EGR_UG_MASK TIM2_EGR_UG_MASK +#define TIM_32B_EGR_UG(x) TIM2_EGR_UG(x) + +/*! + * @brief TIM_32B_CCMR1 Register Bit Definition + */ + +#define TIM_32B_CCMR1_OC2CE_SHIFT TIM2_CCMR1_OC2CE_SHIFT +#define TIM_32B_CCMR1_OC2CE_MASK TIM2_CCMR1_OC2CE_MASK +#define TIM_32B_CCMR1_OC2CE(x) TIM2_CCMR1_OC2CE(x) + +#define TIM_32B_CCMR1_OC2M_SHIFT TIM2_CCMR1_OC2M_SHIFT +#define TIM_32B_CCMR1_OC2M_MASK TIM2_CCMR1_OC2M_MASK +#define TIM_32B_CCMR1_OC2M(x) TIM2_CCMR1_OC2M(x) + +#define TIM_32B_CCMR1_OC2PE_SHIFT TIM2_CCMR1_OC2PE_SHIFT +#define TIM_32B_CCMR1_OC2PE_MASK TIM2_CCMR1_OC2PE_MASK +#define TIM_32B_CCMR1_OC2PE(x) TIM2_CCMR1_OC2PE(x) + +#define TIM_32B_CCMR1_OC2FE_SHIFT TIM2_CCMR1_OC2FE_SHIFT +#define TIM_32B_CCMR1_OC2FE_MASK TIM2_CCMR1_OC2FE_MASK +#define TIM_32B_CCMR1_OC2FE(x) TIM2_CCMR1_OC2FE(x) + +#define TIM_32B_CCMR1_CC2S_SHIFT TIM2_CCMR1_CC2S_SHIFT +#define TIM_32B_CCMR1_CC2S_MASK TIM2_CCMR1_CC2S_MASK +#define TIM_32B_CCMR1_CC2S(x) TIM2_CCMR1_CC2S(x) + +#define TIM_32B_CCMR1_OC1CE_SHIFT TIM2_CCMR1_OC1CE_SHIFT +#define TIM_32B_CCMR1_OC1CE_MASK TIM2_CCMR1_OC1CE_MASK +#define TIM_32B_CCMR1_OC1CE(x) TIM2_CCMR1_OC1CE(x) + +#define TIM_32B_CCMR1_OC1M_SHIFT TIM2_CCMR1_OC1M_SHIFT +#define TIM_32B_CCMR1_OC1M_MASK TIM2_CCMR1_OC1M_MASK +#define TIM_32B_CCMR1_OC1M(x) TIM2_CCMR1_OC1M(x) + +#define TIM_32B_CCMR1_OC1PE_SHIFT TIM2_CCMR1_OC1PE_SHIFT +#define TIM_32B_CCMR1_OC1PE_MASK TIM2_CCMR1_OC1PE_MASK +#define TIM_32B_CCMR1_OC1PE(x) TIM2_CCMR1_OC1PE(x) + +#define TIM_32B_CCMR1_OC1FE_SHIFT TIM2_CCMR1_OC1FE_SHIFT +#define TIM_32B_CCMR1_OC1FE_MASK TIM2_CCMR1_OC1FE_MASK +#define TIM_32B_CCMR1_OC1FE(x) TIM2_CCMR1_OC1FE(x) + +#define TIM_32B_CCMR1_CC1S_SHIFT TIM2_CCMR1_CC1S_SHIFT +#define TIM_32B_CCMR1_CC1S_MASK TIM2_CCMR1_CC1S_MASK +#define TIM_32B_CCMR1_CC1S(x) TIM2_CCMR1_CC1S(x) + +/*! + * @brief TIM_32B_CCMR1 Register Bit Definition + */ + +#define TIM_32B_CCMR1_IC2F_SHIFT TIM2_CCMR1_IC2F_SHIFT +#define TIM_32B_CCMR1_IC2F_MASK TIM2_CCMR1_IC2F_MASK +#define TIM_32B_CCMR1_IC2F(x) TIM2_CCMR1_IC2F(x) + +#define TIM_32B_CCMR1_IC2PSC_SHIFT TIM2_CCMR1_IC2PSC_SHIFT +#define TIM_32B_CCMR1_IC2PSC_MASK TIM2_CCMR1_IC2PSC_MASK +#define TIM_32B_CCMR1_IC2PSC(x) TIM2_CCMR1_IC2PSC(x) + +#define TIM_32B_CCMR1_CC2S_SHIFT TIM2_CCMR1_CC2S_SHIFT +#define TIM_32B_CCMR1_CC2S_MASK TIM2_CCMR1_CC2S_MASK +#define TIM_32B_CCMR1_CC2S(x) TIM2_CCMR1_CC2S(x) + +#define TIM_32B_CCMR1_IC1F_SHIFT TIM2_CCMR1_IC1F_SHIFT +#define TIM_32B_CCMR1_IC1F_MASK TIM2_CCMR1_IC1F_MASK +#define TIM_32B_CCMR1_IC1F(x) TIM2_CCMR1_IC1F(x) + +#define TIM_32B_CCMR1_IC1PSC_SHIFT TIM2_CCMR1_IC1PSC_SHIFT +#define TIM_32B_CCMR1_IC1PSC_MASK TIM2_CCMR1_IC1PSC_MASK +#define TIM_32B_CCMR1_IC1PSC(x) TIM2_CCMR1_IC1PSC(x) + +#define TIM_32B_CCMR1_CC1S_SHIFT TIM2_CCMR1_CC1S_SHIFT +#define TIM_32B_CCMR1_CC1S_MASK TIM2_CCMR1_CC1S_MASK +#define TIM_32B_CCMR1_CC1S(x) TIM2_CCMR1_CC1S(x) + +/*! + * @brief TIM_32B_CCMR2 Register Bit Definition + */ + +#define TIM_32B_CCMR2_OC4CE_SHIFT TIM2_CCMR2_OC4CE_SHIFT +#define TIM_32B_CCMR2_OC4CE_MASK TIM2_CCMR2_OC4CE_MASK +#define TIM_32B_CCMR2_OC4CE(x) TIM2_CCMR2_OC4CE(x) + +#define TIM_32B_CCMR2_OC4M_SHIFT TIM2_CCMR2_OC4M_SHIFT +#define TIM_32B_CCMR2_OC4M_MASK TIM2_CCMR2_OC4M_MASK +#define TIM_32B_CCMR2_OC4M(x) TIM2_CCMR2_OC4M(x) + +#define TIM_32B_CCMR2_OC4PE_SHIFT TIM2_CCMR2_OC4PE_SHIFT +#define TIM_32B_CCMR2_OC4PE_MASK TIM2_CCMR2_OC4PE_MASK +#define TIM_32B_CCMR2_OC4PE(x) TIM2_CCMR2_OC4PE(x) + +#define TIM_32B_CCMR2_OC4FE_SHIFT TIM2_CCMR2_OC4FE_SHIFT +#define TIM_32B_CCMR2_OC4FE_MASK TIM2_CCMR2_OC4FE_MASK +#define TIM_32B_CCMR2_OC4FE(x) TIM2_CCMR2_OC4FE(x) + +#define TIM_32B_CCMR2_CC4S_SHIFT TIM2_CCMR2_CC4S_SHIFT +#define TIM_32B_CCMR2_CC4S_MASK TIM2_CCMR2_CC4S_MASK +#define TIM_32B_CCMR2_CC4S(x) TIM2_CCMR2_CC4S(x) + +#define TIM_32B_CCMR2_OC3CE_SHIFT TIM2_CCMR2_OC3CE_SHIFT +#define TIM_32B_CCMR2_OC3CE_MASK TIM2_CCMR2_OC3CE_MASK +#define TIM_32B_CCMR2_OC3CE(x) TIM2_CCMR2_OC3CE(x) + +#define TIM_32B_CCMR2_OC3M_SHIFT TIM2_CCMR2_OC3M_SHIFT +#define TIM_32B_CCMR2_OC3M_MASK TIM2_CCMR2_OC3M_MASK +#define TIM_32B_CCMR2_OC3M(x) TIM2_CCMR2_OC3M(x) + +#define TIM_32B_CCMR2_OC3PE_SHIFT TIM2_CCMR2_OC3PE_SHIFT +#define TIM_32B_CCMR2_OC3PE_MASK TIM2_CCMR2_OC3PE_MASK +#define TIM_32B_CCMR2_OC3PE(x) TIM2_CCMR2_OC3PE(x) + +#define TIM_32B_CCMR2_OC3FE_SHIFT TIM2_CCMR2_OC3FE_SHIFT +#define TIM_32B_CCMR2_OC3FE_MASK TIM2_CCMR2_OC3FE_MASK +#define TIM_32B_CCMR2_OC3FE(x) TIM2_CCMR2_OC3FE(x) + +#define TIM_32B_CCMR2_CC3S_SHIFT TIM2_CCMR2_CC3S_SHIFT +#define TIM_32B_CCMR2_CC3S_MASK TIM2_CCMR2_CC3S_MASK +#define TIM_32B_CCMR2_CC3S(x) TIM2_CCMR2_CC3S(x) + +/*! + * @brief TIM_32B_CCMR2 Register Bit Definition + */ + +#define TIM_32B_CCMR2_IC4F_SHIFT TIM2_CCMR2_IC4F_SHIFT +#define TIM_32B_CCMR2_IC4F_MASK TIM2_CCMR2_IC4F_MASK +#define TIM_32B_CCMR2_IC4F(x) TIM2_CCMR2_IC4F(x) + +#define TIM_32B_CCMR2_IC4PSC_SHIFT TIM2_CCMR2_IC4PSC_SHIFT +#define TIM_32B_CCMR2_IC4PSC_MASK TIM2_CCMR2_IC4PSC_MASK +#define TIM_32B_CCMR2_IC4PSC(x) TIM2_CCMR2_IC4PSC(x) + +#define TIM_32B_CCMR2_CC4S_SHIFT TIM2_CCMR2_CC4S_SHIFT +#define TIM_32B_CCMR2_CC4S_MASK TIM2_CCMR2_CC4S_MASK +#define TIM_32B_CCMR2_CC4S(x) TIM2_CCMR2_CC4S(x) + +#define TIM_32B_CCMR2_IC3F_SHIFT TIM2_CCMR2_IC3F_SHIFT +#define TIM_32B_CCMR2_IC3F_MASK TIM2_CCMR2_IC3F_MASK +#define TIM_32B_CCMR2_IC3F(x) TIM2_CCMR2_IC3F(x) + +#define TIM_32B_CCMR2_IC3PSC_SHIFT TIM2_CCMR2_IC3PSC_SHIFT +#define TIM_32B_CCMR2_IC3PSC_MASK TIM2_CCMR2_IC3PSC_MASK +#define TIM_32B_CCMR2_IC3PSC(x) TIM2_CCMR2_IC3PSC(x) + +#define TIM_32B_CCMR2_CC3S_SHIFT TIM2_CCMR2_CC3S_SHIFT +#define TIM_32B_CCMR2_CC3S_MASK TIM2_CCMR2_CC3S_MASK +#define TIM_32B_CCMR2_CC3S(x) TIM2_CCMR2_CC3S(x) + +/*! + * @brief TIM_32B_CCER Register Bit Definition + */ + +#define TIM_32B_CCER_CC4NP_SHIFT TIM2_CCER_CC4NP_SHIFT +#define TIM_32B_CCER_CC4NP_MASK TIM2_CCER_CC4NP_MASK +#define TIM_32B_CCER_CC4NP(x) TIM2_CCER_CC4NP(x) + +#define TIM_32B_CCER_CC4P_SHIFT TIM2_CCER_CC4P_SHIFT +#define TIM_32B_CCER_CC4P_MASK TIM2_CCER_CC4P_MASK +#define TIM_32B_CCER_CC4P(x) TIM2_CCER_CC4P(x) + +#define TIM_32B_CCER_CC4E_SHIFT TIM2_CCER_CC4E_SHIFT +#define TIM_32B_CCER_CC4E_MASK TIM2_CCER_CC4E_MASK +#define TIM_32B_CCER_CC4E(x) TIM2_CCER_CC4E(x) + +#define TIM_32B_CCER_CC3NP_SHIFT TIM2_CCER_CC3NP_SHIFT +#define TIM_32B_CCER_CC3NP_MASK TIM2_CCER_CC3NP_MASK +#define TIM_32B_CCER_CC3NP(x) TIM2_CCER_CC3NP(x) + +#define TIM_32B_CCER_CC3P_SHIFT TIM2_CCER_CC3P_SHIFT +#define TIM_32B_CCER_CC3P_MASK TIM2_CCER_CC3P_MASK +#define TIM_32B_CCER_CC3P(x) TIM2_CCER_CC3P(x) + +#define TIM_32B_CCER_CC3E_SHIFT TIM2_CCER_CC3E_SHIFT +#define TIM_32B_CCER_CC3E_MASK TIM2_CCER_CC3E_MASK +#define TIM_32B_CCER_CC3E(x) TIM2_CCER_CC3E(x) + +#define TIM_32B_CCER_CC2NP_SHIFT TIM2_CCER_CC2NP_SHIFT +#define TIM_32B_CCER_CC2NP_MASK TIM2_CCER_CC2NP_MASK +#define TIM_32B_CCER_CC2NP(x) TIM2_CCER_CC2NP(x) + +#define TIM_32B_CCER_CC2P_SHIFT TIM2_CCER_CC2P_SHIFT +#define TIM_32B_CCER_CC2P_MASK TIM2_CCER_CC2P_MASK +#define TIM_32B_CCER_CC2P(x) TIM2_CCER_CC2P(x) + +#define TIM_32B_CCER_CC2E_SHIFT TIM2_CCER_CC2E_SHIFT +#define TIM_32B_CCER_CC2E_MASK TIM2_CCER_CC2E_MASK +#define TIM_32B_CCER_CC2E(x) TIM2_CCER_CC2E(x) + +#define TIM_32B_CCER_CC1NP_SHIFT TIM2_CCER_CC1NP_SHIFT +#define TIM_32B_CCER_CC1NP_MASK TIM2_CCER_CC1NP_MASK +#define TIM_32B_CCER_CC1NP(x) TIM2_CCER_CC1NP(x) + +#define TIM_32B_CCER_CC1P_SHIFT TIM2_CCER_CC1P_SHIFT +#define TIM_32B_CCER_CC1P_MASK TIM2_CCER_CC1P_MASK +#define TIM_32B_CCER_CC1P(x) TIM2_CCER_CC1P(x) + +#define TIM_32B_CCER_CC1E_SHIFT TIM2_CCER_CC1E_SHIFT +#define TIM_32B_CCER_CC1E_MASK TIM2_CCER_CC1E_MASK +#define TIM_32B_CCER_CC1E(x) TIM2_CCER_CC1E(x) + +/*! + * @brief TIM_32B_CNT Register Bit Definition + */ + +#define TIM_32B_CNT_CNT_SHIFT TIM2_CNT_CNT_SHIFT +#define TIM_32B_CNT_CNT_MASK TIM2_CNT_CNT_MASK +#define TIM_32B_CNT_CNT(x) TIM2_CNT_CNT(x) + +/*! + * @brief TIM_32B_PSC Register Bit Definition + */ + +#define TIM_32B_PSC_PSC_SHIFT TIM2_PSC_PSC_SHIFT +#define TIM_32B_PSC_PSC_MASK TIM2_PSC_PSC_MASK +#define TIM_32B_PSC_PSC(x) TIM2_PSC_PSC(x) + +/*! + * @brief TIM_32B_ARR Register Bit Definition + */ + +#define TIM_32B_ARR_ARR_SHIFT TIM2_ARR_ARR_SHIFT +#define TIM_32B_ARR_ARR_MASK TIM2_ARR_ARR_MASK +#define TIM_32B_ARR_ARR(x) TIM2_ARR_ARR(x) + +/*! + * @brief TIM_32B_CCR Register Bit Definition + */ + +#define TIM_32B_CCR_CCR_SHIFT TIM2_CCR_CCR_SHIFT +#define TIM_32B_CCR_CCR_MASK TIM2_CCR_CCR_MASK +#define TIM_32B_CCR_CCR(x) TIM2_CCR_CCR(x) + +/*! + * @brief TIM_32B_DCR Register Bit Definition + */ + +#define TIM_32B_DCR_DBL_SHIFT TIM2_DCR_DBL_SHIFT +#define TIM_32B_DCR_DBL_MASK TIM2_DCR_DBL_MASK +#define TIM_32B_DCR_DBL(x) TIM2_DCR_DBL(x) + +#define TIM_32B_DCR_DBA_SHIFT TIM2_DCR_DBA_SHIFT +#define TIM_32B_DCR_DBA_MASK TIM2_DCR_DBA_MASK +#define TIM_32B_DCR_DBA(x) TIM2_DCR_DBA(x) + +/*! + * @brief TIM_32B_DMAR Register Bit Definition + */ + +#define TIM_32B_DMAR_DMAB_SHIFT TIM2_DMAR_DMAB_SHIFT +#define TIM_32B_DMAR_DMAB_MASK TIM2_DMAR_DMAB_MASK +#define TIM_32B_DMAR_DMAB(x) TIM2_DMAR_DMAB(x) + +/*! + * @brief TIM_32B_OR Register Bit Definition + */ + +#define TIM_32B_OR_TI4RMP_SHIFT TIM2_OR_TI4RMP_SHIFT +#define TIM_32B_OR_TI4RMP_MASK TIM2_OR_TI4RMP_MASK +#define TIM_32B_OR_TI4RMP(x) TIM2_OR_TI4RMP(x) + +#define TIM_32B_OR_ETRRMP_SHIFT TIM2_OR_ETRRMP_SHIFT +#define TIM_32B_OR_ETRRMP_MASK TIM2_OR_ETRRMP_MASK +#define TIM_32B_OR_ETRRMP(x) TIM2_OR_ETRRMP(x) + +/*! + * @} + */ /* end of group TIM_32B_Register_Masks */ + +/******************************************************************************* + * TIM_BASIC Type + ******************************************************************************/ + +/*! + * @addtogroup TIM_BASIC_Register_Masks Register Masks + * @{ + */ +/*! + * @brief TIM_BASIC_CR1 Register Bit Definition + */ + +#define TIM_BASIC_CR1_ARPE_SHIFT TIM6_CR1_ARPE_SHIFT +#define TIM_BASIC_CR1_ARPE_MASK TIM6_CR1_ARPE_MASK +#define TIM_BASIC_CR1_ARPE(x) TIM6_CR1_ARPE(x) + +#define TIM_BASIC_CR1_OPM_SHIFT TIM6_CR1_OPM_SHIFT +#define TIM_BASIC_CR1_OPM_MASK TIM6_CR1_OPM_MASK +#define TIM_BASIC_CR1_OPM(x) TIM6_CR1_OPM(x) + +#define TIM_BASIC_CR1_URS_SHIFT TIM6_CR1_URS_SHIFT +#define TIM_BASIC_CR1_URS_MASK TIM6_CR1_URS_MASK +#define TIM_BASIC_CR1_URS(x) TIM6_CR1_URS(x) + +#define TIM_BASIC_CR1_UDIS_SHIFT TIM6_CR1_UDIS_SHIFT +#define TIM_BASIC_CR1_UDIS_MASK TIM6_CR1_UDIS_MASK +#define TIM_BASIC_CR1_UDIS(x) TIM6_CR1_UDIS(x) + +#define TIM_BASIC_CR1_CEN_SHIFT TIM6_CR1_CEN_SHIFT +#define TIM_BASIC_CR1_CEN_MASK TIM6_CR1_CEN_MASK +#define TIM_BASIC_CR1_CEN(x) TIM6_CR1_CEN(x) + +/*! + * @brief TIM_BASIC_DIER Register Bit Definition + */ + +#define TIM_BASIC_DIER_UDE_SHIFT TIM6_DIER_UDE_SHIFT +#define TIM_BASIC_DIER_UDE_MASK TIM6_DIER_UDE_MASK +#define TIM_BASIC_DIER_UDE(x) TIM6_DIER_UDE(x) + +#define TIM_BASIC_DIER_UIE_SHIFT TIM6_DIER_UIE_SHIFT +#define TIM_BASIC_DIER_UIE_MASK TIM6_DIER_UIE_MASK +#define TIM_BASIC_DIER_UIE(x) TIM6_DIER_UIE(x) + +/*! + * @brief TIM_BASIC_SR Register Bit Definition + */ + +#define TIM_BASIC_SR_UIF_SHIFT TIM6_SR_UIF_SHIFT +#define TIM_BASIC_SR_UIF_MASK TIM6_SR_UIF_MASK +#define TIM_BASIC_SR_UIF(x) TIM6_SR_UIF(x) + +/*! + * @brief TIM_BASIC_EGR Register Bit Definition + */ + +#define TIM_BASIC_EGR_UG_SHIFT TIM6_EGR_UG_SHIFT +#define TIM_BASIC_EGR_UG_MASK TIM6_EGR_UG_MASK +#define TIM_BASIC_EGR_UG(x) TIM6_EGR_UG(x) + +/*! + * @brief TIM_BASIC_CNT Register Bit Definition + */ + +#define TIM_BASIC_CNT_CNT_SHIFT TIM6_CNT_CNT_SHIFT +#define TIM_BASIC_CNT_CNT_MASK TIM6_CNT_CNT_MASK +#define TIM_BASIC_CNT_CNT(x) TIM6_CNT_CNT(x) + +/*! + * @brief TIM_BASIC_PSC Register Bit Definition + */ + +#define TIM_BASIC_PSC_PSC_SHIFT TIM6_PSC_PSC_SHIFT +#define TIM_BASIC_PSC_PSC_MASK TIM6_PSC_PSC_MASK +#define TIM_BASIC_PSC_PSC(x) TIM6_PSC_PSC(x) + +/*! + * @brief TIM_BASIC_ARR Register Bit Definition + */ + +#define TIM_BASIC_ARR_ARR_SHIFT TIM6_ARR_ARR_SHIFT +#define TIM_BASIC_ARR_ARR_MASK TIM6_ARR_ARR_MASK +#define TIM_BASIC_ARR_ARR(x) TIM6_ARR_ARR(x) + + +/*! + * @addtogroup TIM_Peripheral_Access_Layer TIM Peripheral Access Layer + * @{ + */ + +/******************************************************************************* + * TIM Type + ******************************************************************************/ +typedef struct { + __IO uint32_t CR1; ///< Control Register 1 offset: 0x00 + __IO uint32_t CR2; ///< Control Register 2 offset: 0x04 + __IO uint32_t SMCR; ///< Slave Mode Control Register offset: 0x08 + __IO uint32_t DIER; ///< DMA/Interrupt Enable Register offset: 0x0C + __IO uint32_t SR; ///< status register offset: 0x10 + __IO uint32_t EGR; ///< event generation register offset: 0x14 + __IO uint32_t CCMR1; ///< Capture/Compare Mode Register 1 offset: 0x18 + __IO uint32_t CCMR2; ///< Capture/Compare Mode Register 2 offset: 0x1C + __IO uint32_t CCER; ///< Capture/Compare Enable Register offset: 0x20 + __IO uint32_t CNT; ///< counter offset: 0x24 + __IO uint32_t PSC; ///< Prescaler offset: 0x28 + __IO uint32_t ARR; ///< autoload register offset: 0x2C + __IO uint32_t RCR; ///< Repeat count register offset: 0x30 + __IO uint32_t CCR[4]; ///< Capture/Compare Register 1 offset: 0x34 + __IO uint32_t BDTR; ///< Brake and Deadband Registers offset: 0x44 + __IO uint32_t DCR; ///< DMA Control Register offset: 0x48 + __IO uint32_t DMAR; ///< DMA address for continuous mode offset: 0x4C + __IO uint32_t Reserved0[1]; ///< Reserved + __IO uint32_t CCMR3; ///< Capture/Compare Mode Register 3 offset: 0x54 + __IO uint32_t CCR5; ///< Capture/Compare Register 5 offset: 0x58 + __IO uint32_t PDER; ///< PWM phase shift/DMA repeat update request enable registeroffset: 0x5C + __IO uint32_t CCRFALL[5]; ///< PWM Phase Shift Down Count Capture/Compare Registeroffset: 0x60 + __IO uint32_t BKINF; ///< brake input filter register offset: 0x74 +} TIM_Type; + +/******************************************************************************* + * TIM Type + ******************************************************************************/ + +/*! + * @addtogroup TIM_Register_Masks Register Masks + * @{ + */ + +/*! + * @brief TIM_CR1 Register Bit Definition + */ + +#define TIM_CR1_CKD_SHIFT (8) +#define TIM_CR1_CKD_MASK (0x3U << TIM_CR1_CKD_SHIFT) +#define TIM_CR1_CKD(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR1_CKD_SHIFT)) & TIM_CR1_CKD_MASK) + +#define TIM_CR1_ARPE_SHIFT (7) +#define TIM_CR1_ARPE_MASK (0x01U << TIM_CR1_ARPE_SHIFT) +#define TIM_CR1_ARPE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR1_ARPE_SHIFT)) & TIM_CR1_ARPE_MASK) + +#define TIM_CR1_CMS_SHIFT (5) +#define TIM_CR1_CMS_MASK (0x3U << TIM_CR1_CMS_SHIFT) +#define TIM_CR1_CMS(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR1_CMS_SHIFT)) & TIM_CR1_CMS_MASK) + +#define TIM_CR1_DIR_SHIFT (4) +#define TIM_CR1_DIR_MASK (0x01U << TIM_CR1_DIR_SHIFT) +#define TIM_CR1_DIR(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR1_DIR_SHIFT)) & TIM_CR1_DIR_MASK) + +#define TIM_CR1_OPM_SHIFT (3) +#define TIM_CR1_OPM_MASK (0x01U << TIM_CR1_OPM_SHIFT) +#define TIM_CR1_OPM(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR1_OPM_SHIFT)) & TIM_CR1_OPM_MASK) + +#define TIM_CR1_URS_SHIFT (2) +#define TIM_CR1_URS_MASK (0x01U << TIM_CR1_URS_SHIFT) +#define TIM_CR1_URS(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR1_URS_SHIFT)) & TIM_CR1_URS_MASK) + +#define TIM_CR1_UDIS_SHIFT (1) +#define TIM_CR1_UDIS_MASK (0x01U << TIM_CR1_UDIS_SHIFT) +#define TIM_CR1_UDIS(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR1_UDIS_SHIFT)) & TIM_CR1_UDIS_MASK) + +#define TIM_CR1_CEN_SHIFT (0) +#define TIM_CR1_CEN_MASK (0x01U << TIM_CR1_CEN_SHIFT) +#define TIM_CR1_CEN(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR1_CEN_SHIFT)) & TIM_CR1_CEN_MASK) + +/*! + * @brief TIM_CR2 Register Bit Definition + */ + +#define TIM_CR2_OIS4N_SHIFT (15) +#define TIM_CR2_OIS4N_MASK (0x01U << TIM_CR2_OIS4N_SHIFT) +#define TIM_CR2_OIS4N(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR2_OIS4N_SHIFT)) & TIM_CR2_OIS4N_MASK) + +#define TIM_CR2_OIS4_SHIFT (14) +#define TIM_CR2_OIS4_MASK (0x01U << TIM_CR2_OIS4_SHIFT) +#define TIM_CR2_OIS4(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR2_OIS4_SHIFT)) & TIM_CR2_OIS4_MASK) + +#define TIM_CR2_OIS3N_SHIFT (13) +#define TIM_CR2_OIS3N_MASK (0x01U << TIM_CR2_OIS3N_SHIFT) +#define TIM_CR2_OIS3N(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR2_OIS3N_SHIFT)) & TIM_CR2_OIS3N_MASK) + +#define TIM_CR2_OIS3_SHIFT (12) +#define TIM_CR2_OIS3_MASK (0x01U << TIM_CR2_OIS3_SHIFT) +#define TIM_CR2_OIS3(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR2_OIS3_SHIFT)) & TIM_CR2_OIS3_MASK) + +#define TIM_CR2_OIS2N_SHIFT (11) +#define TIM_CR2_OIS2N_MASK (0x01U << TIM_CR2_OIS2N_SHIFT) +#define TIM_CR2_OIS2N(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR2_OIS2N_SHIFT)) & TIM_CR2_OIS2N_MASK) + +#define TIM_CR2_OIS2_SHIFT (10) +#define TIM_CR2_OIS2_MASK (0x01U << TIM_CR2_OIS2_SHIFT) +#define TIM_CR2_OIS2(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR2_OIS2_SHIFT)) & TIM_CR2_OIS2_MASK) + +#define TIM_CR2_OIS1N_SHIFT (9) +#define TIM_CR2_OIS1N_MASK (0x01U << TIM_CR2_OIS1N_SHIFT) +#define TIM_CR2_OIS1N(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR2_OIS1N_SHIFT)) & TIM_CR2_OIS1N_MASK) + +#define TIM_CR2_OIS1_SHIFT (8) +#define TIM_CR2_OIS1_MASK (0x01U << TIM_CR2_OIS1_SHIFT) +#define TIM_CR2_OIS1(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR2_OIS1_SHIFT)) & TIM_CR2_OIS1_MASK) + +#define TIM_CR2_TI1S_SHIFT (7) +#define TIM_CR2_TI1S_MASK (0x01U << TIM_CR2_TI1S_SHIFT) +#define TIM_CR2_TI1S(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR2_TI1S_SHIFT)) & TIM_CR2_TI1S_MASK) + +#define TIM_CR2_MMS_SHIFT (4) +#define TIM_CR2_MMS_MASK (0x7U << TIM_CR2_MMS_SHIFT) +#define TIM_CR2_MMS(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR2_MMS_SHIFT)) & TIM_CR2_MMS_MASK) + +#define TIM_CR2_CCDS_SHIFT (3) +#define TIM_CR2_CCDS_MASK (0x01U << TIM_CR2_CCDS_SHIFT) +#define TIM_CR2_CCDS(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR2_CCDS_SHIFT)) & TIM_CR2_CCDS_MASK) + +#define TIM_CR2_CCUS_SHIFT (2) +#define TIM_CR2_CCUS_MASK (0x01U << TIM_CR2_CCUS_SHIFT) +#define TIM_CR2_CCUS(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR2_CCUS_SHIFT)) & TIM_CR2_CCUS_MASK) + +#define TIM_CR2_CCPC_SHIFT (0) +#define TIM_CR2_CCPC_MASK (0x01U << TIM_CR2_CCPC_SHIFT) +#define TIM_CR2_CCPC(x) (((uint32_t)(((uint32_t)(x)) << TIM_CR2_CCPC_SHIFT)) & TIM_CR2_CCPC_MASK) + +/*! + * @brief TIM_SMCR Register Bit Definition + */ + +#define TIM_SMCR_ETP_SHIFT (15) +#define TIM_SMCR_ETP_MASK (0x01U << TIM_SMCR_ETP_SHIFT) +#define TIM_SMCR_ETP(x) (((uint32_t)(((uint32_t)(x)) << TIM_SMCR_ETP_SHIFT)) & TIM_SMCR_ETP_MASK) + +#define TIM_SMCR_ECE_SHIFT (14) +#define TIM_SMCR_ECE_MASK (0x01U << TIM_SMCR_ECE_SHIFT) +#define TIM_SMCR_ECE(x) (((uint32_t)(((uint32_t)(x)) << TIM_SMCR_ECE_SHIFT)) & TIM_SMCR_ECE_MASK) + +#define TIM_SMCR_ETPS_SHIFT (12) +#define TIM_SMCR_ETPS_MASK (0x3U << TIM_SMCR_ETPS_SHIFT) +#define TIM_SMCR_ETPS(x) (((uint32_t)(((uint32_t)(x)) << TIM_SMCR_ETPS_SHIFT)) & TIM_SMCR_ETPS_MASK) + +#define TIM_SMCR_ETF_SHIFT (8) +#define TIM_SMCR_ETF_MASK (0xFU << TIM_SMCR_ETF_SHIFT) +#define TIM_SMCR_ETF(x) (((uint32_t)(((uint32_t)(x)) << TIM_SMCR_ETF_SHIFT)) & TIM_SMCR_ETF_MASK) + +#define TIM_SMCR_MSM_SHIFT (7) +#define TIM_SMCR_MSM_MASK (0x01U << TIM_SMCR_MSM_SHIFT) +#define TIM_SMCR_MSM(x) (((uint32_t)(((uint32_t)(x)) << TIM_SMCR_MSM_SHIFT)) & TIM_SMCR_MSM_MASK) + +#define TIM_SMCR_TS_SHIFT (4) +#define TIM_SMCR_TS_MASK (0x7U << TIM_SMCR_TS_SHIFT) +#define TIM_SMCR_TS(x) (((uint32_t)(((uint32_t)(x)) << TIM_SMCR_TS_SHIFT)) & TIM_SMCR_TS_MASK) + +#define TIM_SMCR_OCCS_SHIFT (3) +#define TIM_SMCR_OCCS_MASK (0x01U << TIM_SMCR_OCCS_SHIFT) +#define TIM_SMCR_OCCS(x) (((uint32_t)(((uint32_t)(x)) << TIM_SMCR_OCCS_SHIFT)) & TIM_SMCR_OCCS_MASK) + +#define TIM_SMCR_SMS_SHIFT (0) +#define TIM_SMCR_SMS_MASK (0x7U << TIM_SMCR_SMS_SHIFT) +#define TIM_SMCR_SMS(x) (((uint32_t)(((uint32_t)(x)) << TIM_SMCR_SMS_SHIFT)) & TIM_SMCR_SMS_MASK) + +/*! + * @brief TIM_DIER Register Bit Definition + */ + +#define TIM_DIER_CC5DE_SHIFT (17) +#define TIM_DIER_CC5DE_MASK (0x01U << TIM_DIER_CC5DE_SHIFT) +#define TIM_DIER_CC5DE(x) (((uint32_t)(((uint32_t)(x)) << TIM_DIER_CC5DE_SHIFT)) & TIM_DIER_CC5DE_MASK) + +#define TIM_DIER_CC5IE_SHIFT (16) +#define TIM_DIER_CC5IE_MASK (0x01U << TIM_DIER_CC5IE_SHIFT) +#define TIM_DIER_CC5IE(x) (((uint32_t)(((uint32_t)(x)) << TIM_DIER_CC5IE_SHIFT)) & TIM_DIER_CC5IE_MASK) + +#define TIM_DIER_TDE_SHIFT (14) +#define TIM_DIER_TDE_MASK (0x01U << TIM_DIER_TDE_SHIFT) +#define TIM_DIER_TDE(x) (((uint32_t)(((uint32_t)(x)) << TIM_DIER_TDE_SHIFT)) & TIM_DIER_TDE_MASK) + +#define TIM_DIER_COMDE_SHIFT (13) +#define TIM_DIER_COMDE_MASK (0x01U << TIM_DIER_COMDE_SHIFT) +#define TIM_DIER_COMDE(x) (((uint32_t)(((uint32_t)(x)) << TIM_DIER_COMDE_SHIFT)) & TIM_DIER_COMDE_MASK) + +#define TIM_DIER_CC4DE_SHIFT (12) +#define TIM_DIER_CC4DE_MASK (0x01U << TIM_DIER_CC4DE_SHIFT) +#define TIM_DIER_CC4DE(x) (((uint32_t)(((uint32_t)(x)) << TIM_DIER_CC4DE_SHIFT)) & TIM_DIER_CC4DE_MASK) + +#define TIM_DIER_CC3DE_SHIFT (11) +#define TIM_DIER_CC3DE_MASK (0x01U << TIM_DIER_CC3DE_SHIFT) +#define TIM_DIER_CC3DE(x) (((uint32_t)(((uint32_t)(x)) << TIM_DIER_CC3DE_SHIFT)) & TIM_DIER_CC3DE_MASK) + +#define TIM_DIER_CC2DE_SHIFT (10) +#define TIM_DIER_CC2DE_MASK (0x01U << TIM_DIER_CC2DE_SHIFT) +#define TIM_DIER_CC2DE(x) (((uint32_t)(((uint32_t)(x)) << TIM_DIER_CC2DE_SHIFT)) & TIM_DIER_CC2DE_MASK) + +#define TIM_DIER_CC1DE_SHIFT (9) +#define TIM_DIER_CC1DE_MASK (0x01U << TIM_DIER_CC1DE_SHIFT) +#define TIM_DIER_CC1DE(x) (((uint32_t)(((uint32_t)(x)) << TIM_DIER_CC1DE_SHIFT)) & TIM_DIER_CC1DE_MASK) + +#define TIM_DIER_UDE_SHIFT (8) +#define TIM_DIER_UDE_MASK (0x01U << TIM_DIER_UDE_SHIFT) +#define TIM_DIER_UDE(x) (((uint32_t)(((uint32_t)(x)) << TIM_DIER_UDE_SHIFT)) & TIM_DIER_UDE_MASK) + +#define TIM_DIER_BIE_SHIFT (7) +#define TIM_DIER_BIE_MASK (0x01U << TIM_DIER_BIE_SHIFT) +#define TIM_DIER_BIE(x) (((uint32_t)(((uint32_t)(x)) << TIM_DIER_BIE_SHIFT)) & TIM_DIER_BIE_MASK) + +#define TIM_DIER_TIE_SHIFT (6) +#define TIM_DIER_TIE_MASK (0x01U << TIM_DIER_TIE_SHIFT) +#define TIM_DIER_TIE(x) (((uint32_t)(((uint32_t)(x)) << TIM_DIER_TIE_SHIFT)) & TIM_DIER_TIE_MASK) + +#define TIM_DIER_COMIE_SHIFT (5) +#define TIM_DIER_COMIE_MASK (0x01U << TIM_DIER_COMIE_SHIFT) +#define TIM_DIER_COMIE(x) (((uint32_t)(((uint32_t)(x)) << TIM_DIER_COMIE_SHIFT)) & TIM_DIER_COMIE_MASK) + +#define TIM_DIER_CC4IE_SHIFT (4) +#define TIM_DIER_CC4IE_MASK (0x01U << TIM_DIER_CC4IE_SHIFT) +#define TIM_DIER_CC4IE(x) (((uint32_t)(((uint32_t)(x)) << TIM_DIER_CC4IE_SHIFT)) & TIM_DIER_CC4IE_MASK) + +#define TIM_DIER_CC3IE_SHIFT (3) +#define TIM_DIER_CC3IE_MASK (0x01U << TIM_DIER_CC3IE_SHIFT) +#define TIM_DIER_CC3IE(x) (((uint32_t)(((uint32_t)(x)) << TIM_DIER_CC3IE_SHIFT)) & TIM_DIER_CC3IE_MASK) + +#define TIM_DIER_CC2IE_SHIFT (2) +#define TIM_DIER_CC2IE_MASK (0x01U << TIM_DIER_CC2IE_SHIFT) +#define TIM_DIER_CC2IE(x) (((uint32_t)(((uint32_t)(x)) << TIM_DIER_CC2IE_SHIFT)) & TIM_DIER_CC2IE_MASK) + +#define TIM_DIER_CC1IE_SHIFT (1) +#define TIM_DIER_CC1IE_MASK (0x01U << TIM_DIER_CC1IE_SHIFT) +#define TIM_DIER_CC1IE(x) (((uint32_t)(((uint32_t)(x)) << TIM_DIER_CC1IE_SHIFT)) & TIM_DIER_CC1IE_MASK) + +#define TIM_DIER_UIE_SHIFT (0) +#define TIM_DIER_UIE_MASK (0x01U << TIM_DIER_UIE_SHIFT) +#define TIM_DIER_UIE(x) (((uint32_t)(((uint32_t)(x)) << TIM_DIER_UIE_SHIFT)) & TIM_DIER_UIE_MASK) + +/*! + * @brief TIM_SR Register Bit Definition + */ + +#define TIM_SR_CC5IF_SHIFT (16) +#define TIM_SR_CC5IF_MASK (0x01U << TIM_SR_CC5IF_SHIFT) +#define TIM_SR_CC5IF(x) (((uint32_t)(((uint32_t)(x)) << TIM_SR_CC5IF_SHIFT)) & TIM_SR_CC5IF_MASK) + +#define TIM_SR_CC4OF_SHIFT (12) +#define TIM_SR_CC4OF_MASK (0x01U << TIM_SR_CC4OF_SHIFT) +#define TIM_SR_CC4OF(x) (((uint32_t)(((uint32_t)(x)) << TIM_SR_CC4OF_SHIFT)) & TIM_SR_CC4OF_MASK) + +#define TIM_SR_CC3OF_SHIFT (11) +#define TIM_SR_CC3OF_MASK (0x01U << TIM_SR_CC3OF_SHIFT) +#define TIM_SR_CC3OF(x) (((uint32_t)(((uint32_t)(x)) << TIM_SR_CC3OF_SHIFT)) & TIM_SR_CC3OF_MASK) + +#define TIM_SR_CC2OF_SHIFT (10) +#define TIM_SR_CC2OF_MASK (0x01U << TIM_SR_CC2OF_SHIFT) +#define TIM_SR_CC2OF(x) (((uint32_t)(((uint32_t)(x)) << TIM_SR_CC2OF_SHIFT)) & TIM_SR_CC2OF_MASK) + +#define TIM_SR_CC1OF_SHIFT (9) +#define TIM_SR_CC1OF_MASK (0x01U << TIM_SR_CC1OF_SHIFT) +#define TIM_SR_CC1OF(x) (((uint32_t)(((uint32_t)(x)) << TIM_SR_CC1OF_SHIFT)) & TIM_SR_CC1OF_MASK) + +#define TIM_SR_BIF_SHIFT (7) +#define TIM_SR_BIF_MASK (0x01U << TIM_SR_BIF_SHIFT) +#define TIM_SR_BIF(x) (((uint32_t)(((uint32_t)(x)) << TIM_SR_BIF_SHIFT)) & TIM_SR_BIF_MASK) + +#define TIM_SR_TIF_SHIFT (6) +#define TIM_SR_TIF_MASK (0x01U << TIM_SR_TIF_SHIFT) +#define TIM_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << TIM_SR_TIF_SHIFT)) & TIM_SR_TIF_MASK) + +#define TIM_SR_COMIF_SHIFT (5) +#define TIM_SR_COMIF_MASK (0x01U << TIM_SR_COMIF_SHIFT) +#define TIM_SR_COMIF(x) (((uint32_t)(((uint32_t)(x)) << TIM_SR_COMIF_SHIFT)) & TIM_SR_COMIF_MASK) + +#define TIM_SR_CC4IF_SHIFT (4) +#define TIM_SR_CC4IF_MASK (0x01U << TIM_SR_CC4IF_SHIFT) +#define TIM_SR_CC4IF(x) (((uint32_t)(((uint32_t)(x)) << TIM_SR_CC4IF_SHIFT)) & TIM_SR_CC4IF_MASK) + +#define TIM_SR_CC3IF_SHIFT (3) +#define TIM_SR_CC3IF_MASK (0x01U << TIM_SR_CC3IF_SHIFT) +#define TIM_SR_CC3IF(x) (((uint32_t)(((uint32_t)(x)) << TIM_SR_CC3IF_SHIFT)) & TIM_SR_CC3IF_MASK) + +#define TIM_SR_CC2IF_SHIFT (2) +#define TIM_SR_CC2IF_MASK (0x01U << TIM_SR_CC2IF_SHIFT) +#define TIM_SR_CC2IF(x) (((uint32_t)(((uint32_t)(x)) << TIM_SR_CC2IF_SHIFT)) & TIM_SR_CC2IF_MASK) + +#define TIM_SR_CC1IF_SHIFT (1) +#define TIM_SR_CC1IF_MASK (0x01U << TIM_SR_CC1IF_SHIFT) +#define TIM_SR_CC1IF(x) (((uint32_t)(((uint32_t)(x)) << TIM_SR_CC1IF_SHIFT)) & TIM_SR_CC1IF_MASK) + +#define TIM_SR_UIF_SHIFT (0) +#define TIM_SR_UIF_MASK (0x01U << TIM_SR_UIF_SHIFT) +#define TIM_SR_UIF(x) (((uint32_t)(((uint32_t)(x)) << TIM_SR_UIF_SHIFT)) & TIM_SR_UIF_MASK) + +/*! + * @brief TIM_EGR Register Bit Definition + */ + +#define TIM_EGR_CC5G_SHIFT (16) +#define TIM_EGR_CC5G_MASK (0x01U << TIM_EGR_CC5G_SHIFT) +#define TIM_EGR_CC5G(x) (((uint32_t)(((uint32_t)(x)) << TIM_EGR_CC5G_SHIFT)) & TIM_EGR_CC5G_MASK) + +#define TIM_EGR_BG_SHIFT (7) +#define TIM_EGR_BG_MASK (0x01U << TIM_EGR_BG_SHIFT) +#define TIM_EGR_BG(x) (((uint32_t)(((uint32_t)(x)) << TIM_EGR_BG_SHIFT)) & TIM_EGR_BG_MASK) + +#define TIM_EGR_TG_SHIFT (6) +#define TIM_EGR_TG_MASK (0x01U << TIM_EGR_TG_SHIFT) +#define TIM_EGR_TG(x) (((uint32_t)(((uint32_t)(x)) << TIM_EGR_TG_SHIFT)) & TIM_EGR_TG_MASK) + +#define TIM_EGR_COMG_SHIFT (5) +#define TIM_EGR_COMG_MASK (0x01U << TIM_EGR_COMG_SHIFT) +#define TIM_EGR_COMG(x) (((uint32_t)(((uint32_t)(x)) << TIM_EGR_COMG_SHIFT)) & TIM_EGR_COMG_MASK) + +#define TIM_EGR_CC4G_SHIFT (4) +#define TIM_EGR_CC4G_MASK (0x01U << TIM_EGR_CC4G_SHIFT) +#define TIM_EGR_CC4G(x) (((uint32_t)(((uint32_t)(x)) << TIM_EGR_CC4G_SHIFT)) & TIM_EGR_CC4G_MASK) + +#define TIM_EGR_CC3G_SHIFT (3) +#define TIM_EGR_CC3G_MASK (0x01U << TIM_EGR_CC3G_SHIFT) +#define TIM_EGR_CC3G(x) (((uint32_t)(((uint32_t)(x)) << TIM_EGR_CC3G_SHIFT)) & TIM_EGR_CC3G_MASK) + +#define TIM_EGR_CC2G_SHIFT (2) +#define TIM_EGR_CC2G_MASK (0x01U << TIM_EGR_CC2G_SHIFT) +#define TIM_EGR_CC2G(x) (((uint32_t)(((uint32_t)(x)) << TIM_EGR_CC2G_SHIFT)) & TIM_EGR_CC2G_MASK) + +#define TIM_EGR_CC1G_SHIFT (1) +#define TIM_EGR_CC1G_MASK (0x01U << TIM_EGR_CC1G_SHIFT) +#define TIM_EGR_CC1G(x) (((uint32_t)(((uint32_t)(x)) << TIM_EGR_CC1G_SHIFT)) & TIM_EGR_CC1G_MASK) + +#define TIM_EGR_UG_SHIFT (0) +#define TIM_EGR_UG_MASK (0x01U << TIM_EGR_UG_SHIFT) +#define TIM_EGR_UG(x) (((uint32_t)(((uint32_t)(x)) << TIM_EGR_UG_SHIFT)) & TIM_EGR_UG_MASK) + +/*! + * @brief TIM_CCMR1 Register Bit Definition + */ + +#define TIM_CCMR1_OC2CE_SHIFT (15) +#define TIM_CCMR1_OC2CE_MASK (0x01U << TIM_CCMR1_OC2CE_SHIFT) +#define TIM_CCMR1_OC2CE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR1_OC2CE_SHIFT)) & TIM_CCMR1_OC2CE_MASK) + +#define TIM_CCMR1_OC2M_SHIFT (12) +#define TIM_CCMR1_OC2M_MASK (0x7U << TIM_CCMR1_OC2M_SHIFT) +#define TIM_CCMR1_OC2M(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR1_OC2M_SHIFT)) & TIM_CCMR1_OC2M_MASK) + +#define TIM_CCMR1_OC2PE_SHIFT (11) +#define TIM_CCMR1_OC2PE_MASK (0x01U << TIM_CCMR1_OC2PE_SHIFT) +#define TIM_CCMR1_OC2PE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR1_OC2PE_SHIFT)) & TIM_CCMR1_OC2PE_MASK) + +#define TIM_CCMR1_OC2FE_SHIFT (10) +#define TIM_CCMR1_OC2FE_MASK (0x01U << TIM_CCMR1_OC2FE_SHIFT) +#define TIM_CCMR1_OC2FE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR1_OC2FE_SHIFT)) & TIM_CCMR1_OC2FE_MASK) + +#define TIM_CCMR1_CC2S_SHIFT (8) +#define TIM_CCMR1_CC2S_MASK (0x3U << TIM_CCMR1_CC2S_SHIFT) +#define TIM_CCMR1_CC2S(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR1_CC2S_SHIFT)) & TIM_CCMR1_CC2S_MASK) + +#define TIM_CCMR1_OC1CE_SHIFT (7) +#define TIM_CCMR1_OC1CE_MASK (0x01U << TIM_CCMR1_OC1CE_SHIFT) +#define TIM_CCMR1_OC1CE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR1_OC1CE_SHIFT)) & TIM_CCMR1_OC1CE_MASK) + +#define TIM_CCMR1_OC1M_SHIFT (4) +#define TIM_CCMR1_OC1M_MASK (0x7U << TIM_CCMR1_OC1M_SHIFT) +#define TIM_CCMR1_OC1M(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR1_OC1M_SHIFT)) & TIM_CCMR1_OC1M_MASK) + +#define TIM_CCMR1_OC1PE_SHIFT (3) +#define TIM_CCMR1_OC1PE_MASK (0x01U << TIM_CCMR1_OC1PE_SHIFT) +#define TIM_CCMR1_OC1PE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR1_OC1PE_SHIFT)) & TIM_CCMR1_OC1PE_MASK) + +#define TIM_CCMR1_OC1FE_SHIFT (2) +#define TIM_CCMR1_OC1FE_MASK (0x01U << TIM_CCMR1_OC1FE_SHIFT) +#define TIM_CCMR1_OC1FE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR1_OC1FE_SHIFT)) & TIM_CCMR1_OC1FE_MASK) + +#define TIM_CCMR1_CC1S_SHIFT (0) +#define TIM_CCMR1_CC1S_MASK (0x3U << TIM_CCMR1_CC1S_SHIFT) +#define TIM_CCMR1_CC1S(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR1_CC1S_SHIFT)) & TIM_CCMR1_CC1S_MASK) + +/*! + * @brief TIM_CCMR1 Register Bit Definition + */ + +#define TIM_CCMR1_IC2F_SHIFT (12) +#define TIM_CCMR1_IC2F_MASK (0xFU << TIM_CCMR1_IC2F_SHIFT) +#define TIM_CCMR1_IC2F(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR1_IC2F_SHIFT)) & TIM_CCMR1_IC2F_MASK) + +#define TIM_CCMR1_IC2PSC_SHIFT (10) +#define TIM_CCMR1_IC2PSC_MASK (0x3U << TIM_CCMR1_IC2PSC_SHIFT) +#define TIM_CCMR1_IC2PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR1_IC2PSC_SHIFT)) & TIM_CCMR1_IC2PSC_MASK) + +#define TIM_CCMR1_CC2S_SHIFT (8) +#define TIM_CCMR1_CC2S_MASK (0x3U << TIM_CCMR1_CC2S_SHIFT) +#define TIM_CCMR1_CC2S(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR1_CC2S_SHIFT)) & TIM_CCMR1_CC2S_MASK) + +#define TIM_CCMR1_IC1F_SHIFT (4) +#define TIM_CCMR1_IC1F_MASK (0xFU << TIM_CCMR1_IC1F_SHIFT) +#define TIM_CCMR1_IC1F(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR1_IC1F_SHIFT)) & TIM_CCMR1_IC1F_MASK) + +#define TIM_CCMR1_IC1PSC_SHIFT (2) +#define TIM_CCMR1_IC1PSC_MASK (0x3U << TIM_CCMR1_IC1PSC_SHIFT) +#define TIM_CCMR1_IC1PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR1_IC1PSC_SHIFT)) & TIM_CCMR1_IC1PSC_MASK) + +#define TIM_CCMR1_CC1S_SHIFT (0) +#define TIM_CCMR1_CC1S_MASK (0x3U << TIM_CCMR1_CC1S_SHIFT) +#define TIM_CCMR1_CC1S(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR1_CC1S_SHIFT)) & TIM_CCMR1_CC1S_MASK) + +/*! + * @brief TIM_CCMR2 Register Bit Definition + */ + +#define TIM_CCMR2_OC4CE_SHIFT (15) +#define TIM_CCMR2_OC4CE_MASK (0x01U << TIM_CCMR2_OC4CE_SHIFT) +#define TIM_CCMR2_OC4CE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR2_OC4CE_SHIFT)) & TIM_CCMR2_OC4CE_MASK) + +#define TIM_CCMR2_OC4M_SHIFT (12) +#define TIM_CCMR2_OC4M_MASK (0x7U << TIM_CCMR2_OC4M_SHIFT) +#define TIM_CCMR2_OC4M(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR2_OC4M_SHIFT)) & TIM_CCMR2_OC4M_MASK) + +#define TIM_CCMR2_OC4PE_SHIFT (11) +#define TIM_CCMR2_OC4PE_MASK (0x01U << TIM_CCMR2_OC4PE_SHIFT) +#define TIM_CCMR2_OC4PE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR2_OC4PE_SHIFT)) & TIM_CCMR2_OC4PE_MASK) + +#define TIM_CCMR2_OC4FE_SHIFT (10) +#define TIM_CCMR2_OC4FE_MASK (0x01U << TIM_CCMR2_OC4FE_SHIFT) +#define TIM_CCMR2_OC4FE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR2_OC4FE_SHIFT)) & TIM_CCMR2_OC4FE_MASK) + +#define TIM_CCMR2_CC4S_SHIFT (8) +#define TIM_CCMR2_CC4S_MASK (0x3U << TIM_CCMR2_CC4S_SHIFT) +#define TIM_CCMR2_CC4S(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR2_CC4S_SHIFT)) & TIM_CCMR2_CC4S_MASK) + +#define TIM_CCMR2_OC3CE_SHIFT (7) +#define TIM_CCMR2_OC3CE_MASK (0x01U << TIM_CCMR2_OC3CE_SHIFT) +#define TIM_CCMR2_OC3CE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR2_OC3CE_SHIFT)) & TIM_CCMR2_OC3CE_MASK) + +#define TIM_CCMR2_OC3M_SHIFT (4) +#define TIM_CCMR2_OC3M_MASK (0x7U << TIM_CCMR2_OC3M_SHIFT) +#define TIM_CCMR2_OC3M(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR2_OC3M_SHIFT)) & TIM_CCMR2_OC3M_MASK) + +#define TIM_CCMR2_OC3PE_SHIFT (3) +#define TIM_CCMR2_OC3PE_MASK (0x01U << TIM_CCMR2_OC3PE_SHIFT) +#define TIM_CCMR2_OC3PE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR2_OC3PE_SHIFT)) & TIM_CCMR2_OC3PE_MASK) + +#define TIM_CCMR2_OC3FE_SHIFT (2) +#define TIM_CCMR2_OC3FE_MASK (0x01U << TIM_CCMR2_OC3FE_SHIFT) +#define TIM_CCMR2_OC3FE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR2_OC3FE_SHIFT)) & TIM_CCMR2_OC3FE_MASK) + +#define TIM_CCMR2_CC3S_SHIFT (0) +#define TIM_CCMR2_CC3S_MASK (0x3U << TIM_CCMR2_CC3S_SHIFT) +#define TIM_CCMR2_CC3S(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR2_CC3S_SHIFT)) & TIM_CCMR2_CC3S_MASK) + +/*! + * @brief TIM_CCMR2 Register Bit Definition + */ + +#define TIM_CCMR2_IC4F_SHIFT (12) +#define TIM_CCMR2_IC4F_MASK (0xFU << TIM_CCMR2_IC4F_SHIFT) +#define TIM_CCMR2_IC4F(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR2_IC4F_SHIFT)) & TIM_CCMR2_IC4F_MASK) + +#define TIM_CCMR2_IC4PSC_SHIFT (10) +#define TIM_CCMR2_IC4PSC_MASK (0x3U << TIM_CCMR2_IC4PSC_SHIFT) +#define TIM_CCMR2_IC4PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR2_IC4PSC_SHIFT)) & TIM_CCMR2_IC4PSC_MASK) + +#define TIM_CCMR2_CC4S_SHIFT (8) +#define TIM_CCMR2_CC4S_MASK (0x3U << TIM_CCMR2_CC4S_SHIFT) +#define TIM_CCMR2_CC4S(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR2_CC4S_SHIFT)) & TIM_CCMR2_CC4S_MASK) + +#define TIM_CCMR2_IC3F_SHIFT (4) +#define TIM_CCMR2_IC3F_MASK (0xFU << TIM_CCMR2_IC3F_SHIFT) +#define TIM_CCMR2_IC3F(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR2_IC3F_SHIFT)) & TIM_CCMR2_IC3F_MASK) + +#define TIM_CCMR2_IC3PSC_SHIFT (2) +#define TIM_CCMR2_IC3PSC_MASK (0x3U << TIM_CCMR2_IC3PSC_SHIFT) +#define TIM_CCMR2_IC3PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR2_IC3PSC_SHIFT)) & TIM_CCMR2_IC3PSC_MASK) + +#define TIM_CCMR2_CC3S_SHIFT (0) +#define TIM_CCMR2_CC3S_MASK (0x3U << TIM_CCMR2_CC3S_SHIFT) +#define TIM_CCMR2_CC3S(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR2_CC3S_SHIFT)) & TIM_CCMR2_CC3S_MASK) + +/*! + * @brief TIM_CCER Register Bit Definition + */ + +#define TIM_CCER_CC4NP_SHIFT (15) +#define TIM_CCER_CC4NP_MASK (0x01U << TIM_CCER_CC4NP_SHIFT) +#define TIM_CCER_CC4NP(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCER_CC4NP_SHIFT)) & TIM_CCER_CC4NP_MASK) + +#define TIM_CCER_CC4NE_SHIFT (14) +#define TIM_CCER_CC4NE_MASK (0x01U << TIM_CCER_CC4NE_SHIFT) +#define TIM_CCER_CC4NE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCER_CC4NE_SHIFT)) & TIM_CCER_CC4NE_MASK) + +#define TIM_CCER_CC4P_SHIFT (13) +#define TIM_CCER_CC4P_MASK (0x01U << TIM_CCER_CC4P_SHIFT) +#define TIM_CCER_CC4P(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCER_CC4P_SHIFT)) & TIM_CCER_CC4P_MASK) + +#define TIM_CCER_CC4E_SHIFT (12) +#define TIM_CCER_CC4E_MASK (0x01U << TIM_CCER_CC4E_SHIFT) +#define TIM_CCER_CC4E(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCER_CC4E_SHIFT)) & TIM_CCER_CC4E_MASK) + +#define TIM_CCER_CC3NP_SHIFT (11) +#define TIM_CCER_CC3NP_MASK (0x01U << TIM_CCER_CC3NP_SHIFT) +#define TIM_CCER_CC3NP(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCER_CC3NP_SHIFT)) & TIM_CCER_CC3NP_MASK) + +#define TIM_CCER_CC3NE_SHIFT (10) +#define TIM_CCER_CC3NE_MASK (0x01U << TIM_CCER_CC3NE_SHIFT) +#define TIM_CCER_CC3NE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCER_CC3NE_SHIFT)) & TIM_CCER_CC3NE_MASK) + +#define TIM_CCER_CC3P_SHIFT (9) +#define TIM_CCER_CC3P_MASK (0x01U << TIM_CCER_CC3P_SHIFT) +#define TIM_CCER_CC3P(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCER_CC3P_SHIFT)) & TIM_CCER_CC3P_MASK) + +#define TIM_CCER_CC3E_SHIFT (8) +#define TIM_CCER_CC3E_MASK (0x01U << TIM_CCER_CC3E_SHIFT) +#define TIM_CCER_CC3E(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCER_CC3E_SHIFT)) & TIM_CCER_CC3E_MASK) + +#define TIM_CCER_CC2NP_SHIFT (7) +#define TIM_CCER_CC2NP_MASK (0x01U << TIM_CCER_CC2NP_SHIFT) +#define TIM_CCER_CC2NP(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCER_CC2NP_SHIFT)) & TIM_CCER_CC2NP_MASK) + +#define TIM_CCER_CC2NE_SHIFT (6) +#define TIM_CCER_CC2NE_MASK (0x01U << TIM_CCER_CC2NE_SHIFT) +#define TIM_CCER_CC2NE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCER_CC2NE_SHIFT)) & TIM_CCER_CC2NE_MASK) + +#define TIM_CCER_CC2P_SHIFT (5) +#define TIM_CCER_CC2P_MASK (0x01U << TIM_CCER_CC2P_SHIFT) +#define TIM_CCER_CC2P(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCER_CC2P_SHIFT)) & TIM_CCER_CC2P_MASK) + +#define TIM_CCER_CC2E_SHIFT (4) +#define TIM_CCER_CC2E_MASK (0x01U << TIM_CCER_CC2E_SHIFT) +#define TIM_CCER_CC2E(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCER_CC2E_SHIFT)) & TIM_CCER_CC2E_MASK) + +#define TIM_CCER_CC1NP_SHIFT (3) +#define TIM_CCER_CC1NP_MASK (0x01U << TIM_CCER_CC1NP_SHIFT) +#define TIM_CCER_CC1NP(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCER_CC1NP_SHIFT)) & TIM_CCER_CC1NP_MASK) + +#define TIM_CCER_CC1NE_SHIFT (2) +#define TIM_CCER_CC1NE_MASK (0x01U << TIM_CCER_CC1NE_SHIFT) +#define TIM_CCER_CC1NE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCER_CC1NE_SHIFT)) & TIM_CCER_CC1NE_MASK) + +#define TIM_CCER_CC1P_SHIFT (1) +#define TIM_CCER_CC1P_MASK (0x01U << TIM_CCER_CC1P_SHIFT) +#define TIM_CCER_CC1P(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCER_CC1P_SHIFT)) & TIM_CCER_CC1P_MASK) + +#define TIM_CCER_CC1E_SHIFT (0) +#define TIM_CCER_CC1E_MASK (0x01U << TIM_CCER_CC1E_SHIFT) +#define TIM_CCER_CC1E(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCER_CC1E_SHIFT)) & TIM_CCER_CC1E_MASK) + +/*! + * @brief TIM_CNT Register Bit Definition + */ + +#define TIM_CNT_CNT_SHIFT (0) +#define TIM_CNT_CNT_MASK (0xFFFFU << TIM_CNT_CNT_SHIFT) +#define TIM_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << TIM_CNT_CNT_SHIFT)) & TIM_CNT_CNT_MASK) + +/*! + * @brief TIM_PSC Register Bit Definition + */ + +#define TIM_PSC_PSC_SHIFT (0) +#define TIM_PSC_PSC_MASK (0xFFFFU << TIM_PSC_PSC_SHIFT) +#define TIM_PSC_PSC(x) (((uint32_t)(((uint32_t)(x)) << TIM_PSC_PSC_SHIFT)) & TIM_PSC_PSC_MASK) + +/*! + * @brief TIM_ARR Register Bit Definition + */ + +#define TIM_ARR_ARR_SHIFT (0) +#define TIM_ARR_ARR_MASK (0xFFFFU << TIM_ARR_ARR_SHIFT) +#define TIM_ARR_ARR(x) (((uint32_t)(((uint32_t)(x)) << TIM_ARR_ARR_SHIFT)) & TIM_ARR_ARR_MASK) + +/*! + * @brief TIM_RCR Register Bit Definition + */ + +#define TIM_RCR_REPCNT_SHIFT (8) +#define TIM_RCR_REPCNT_MASK (0xFFU << TIM_RCR_REPCNT_SHIFT) +#define TIM_RCR_REPCNT(x) (((uint32_t)(((uint32_t)(x)) << TIM_RCR_REPCNT_SHIFT)) & TIM_RCR_REPCNT_MASK) + +#define TIM_RCR_REP_SHIFT (0) +#define TIM_RCR_REP_MASK (0xFFU << TIM_RCR_REP_SHIFT) +#define TIM_RCR_REP(x) (((uint32_t)(((uint32_t)(x)) << TIM_RCR_REP_SHIFT)) & TIM_RCR_REP_MASK) + +/*! + * @brief TIM_CCR Register Bit Definition + */ + +#define TIM_CCR_CCR_SHIFT (0) +#define TIM_CCR_CCR_MASK (0xFFFFU << TIM_CCR_CCR_SHIFT) +#define TIM_CCR_CCR(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCR_CCR_SHIFT)) & TIM_CCR_CCR_MASK) + +/*! + * @brief TIM_BDTR Register Bit Definition + */ + +#define TIM_BDTR_DOE_SHIFT (16) +#define TIM_BDTR_DOE_MASK (0x01U << TIM_BDTR_DOE_SHIFT) +#define TIM_BDTR_DOE(x) (((uint32_t)(((uint32_t)(x)) << TIM_BDTR_DOE_SHIFT)) & TIM_BDTR_DOE_MASK) + +#define TIM_BDTR_MOE_SHIFT (15) +#define TIM_BDTR_MOE_MASK (0x01U << TIM_BDTR_MOE_SHIFT) +#define TIM_BDTR_MOE(x) (((uint32_t)(((uint32_t)(x)) << TIM_BDTR_MOE_SHIFT)) & TIM_BDTR_MOE_MASK) + +#define TIM_BDTR_AOE_SHIFT (14) +#define TIM_BDTR_AOE_MASK (0x01U << TIM_BDTR_AOE_SHIFT) +#define TIM_BDTR_AOE(x) (((uint32_t)(((uint32_t)(x)) << TIM_BDTR_AOE_SHIFT)) & TIM_BDTR_AOE_MASK) + +#define TIM_BDTR_BKP_SHIFT (13) +#define TIM_BDTR_BKP_MASK (0x01U << TIM_BDTR_BKP_SHIFT) +#define TIM_BDTR_BKP(x) (((uint32_t)(((uint32_t)(x)) << TIM_BDTR_BKP_SHIFT)) & TIM_BDTR_BKP_MASK) + +#define TIM_BDTR_BKE_SHIFT (12) +#define TIM_BDTR_BKE_MASK (0x01U << TIM_BDTR_BKE_SHIFT) +#define TIM_BDTR_BKE(x) (((uint32_t)(((uint32_t)(x)) << TIM_BDTR_BKE_SHIFT)) & TIM_BDTR_BKE_MASK) + +#define TIM_BDTR_OSSR_SHIFT (11) +#define TIM_BDTR_OSSR_MASK (0x01U << TIM_BDTR_OSSR_SHIFT) +#define TIM_BDTR_OSSR(x) (((uint32_t)(((uint32_t)(x)) << TIM_BDTR_OSSR_SHIFT)) & TIM_BDTR_OSSR_MASK) + +#define TIM_BDTR_OSSI_SHIFT (10) +#define TIM_BDTR_OSSI_MASK (0x01U << TIM_BDTR_OSSI_SHIFT) +#define TIM_BDTR_OSSI(x) (((uint32_t)(((uint32_t)(x)) << TIM_BDTR_OSSI_SHIFT)) & TIM_BDTR_OSSI_MASK) + +#define TIM_BDTR_LOCK_SHIFT (8) +#define TIM_BDTR_LOCK_MASK (0x3U << TIM_BDTR_LOCK_SHIFT) +#define TIM_BDTR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << TIM_BDTR_LOCK_SHIFT)) & TIM_BDTR_LOCK_MASK) + +#define TIM_BDTR_DTG_SHIFT (0) +#define TIM_BDTR_DTG_MASK (0xFFU << TIM_BDTR_DTG_SHIFT) +#define TIM_BDTR_DTG(x) (((uint32_t)(((uint32_t)(x)) << TIM_BDTR_DTG_SHIFT)) & TIM_BDTR_DTG_MASK) + +/*! + * @brief TIM_DCR Register Bit Definition + */ + +#define TIM_DCR_DBL_SHIFT (8) +#define TIM_DCR_DBL_MASK (0x1FU << TIM_DCR_DBL_SHIFT) +#define TIM_DCR_DBL(x) (((uint32_t)(((uint32_t)(x)) << TIM_DCR_DBL_SHIFT)) & TIM_DCR_DBL_MASK) + +#define TIM_DCR_DBA_SHIFT (0) +#define TIM_DCR_DBA_MASK (0x1FU << TIM_DCR_DBA_SHIFT) +#define TIM_DCR_DBA(x) (((uint32_t)(((uint32_t)(x)) << TIM_DCR_DBA_SHIFT)) & TIM_DCR_DBA_MASK) + +/*! + * @brief TIM_DMAR Register Bit Definition + */ + +#define TIM_DMAR_DMAB_SHIFT (0) +#define TIM_DMAR_DMAB_MASK (0xFFFFU << TIM_DMAR_DMAB_SHIFT) +#define TIM_DMAR_DMAB(x) (((uint32_t)(((uint32_t)(x)) << TIM_DMAR_DMAB_SHIFT)) & TIM_DMAR_DMAB_MASK) + +/*! + * @brief TIM_CCMR3 Register Bit Definition + */ + +#define TIM_CCMR3_OC5M_SHIFT (4) +#define TIM_CCMR3_OC5M_MASK (0x7U << TIM_CCMR3_OC5M_SHIFT) +#define TIM_CCMR3_OC5M(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR3_OC5M_SHIFT)) & TIM_CCMR3_OC5M_MASK) + +#define TIM_CCMR3_OC5PE_SHIFT (3) +#define TIM_CCMR3_OC5PE_MASK (0x01U << TIM_CCMR3_OC5PE_SHIFT) +#define TIM_CCMR3_OC5PE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR3_OC5PE_SHIFT)) & TIM_CCMR3_OC5PE_MASK) + +#define TIM_CCMR3_OC5FE_SHIFT (2) +#define TIM_CCMR3_OC5FE_MASK (0x01U << TIM_CCMR3_OC5FE_SHIFT) +#define TIM_CCMR3_OC5FE(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCMR3_OC5FE_SHIFT)) & TIM_CCMR3_OC5FE_MASK) + +/*! + * @brief TIM_CCR5 Register Bit Definition + */ + +#define TIM_CCR5_CCR5_SHIFT (0) +#define TIM_CCR5_CCR5_MASK (0xFFFFU << TIM_CCR5_CCR5_SHIFT) +#define TIM_CCR5_CCR5(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCR5_CCR5_SHIFT)) & TIM_CCR5_CCR5_MASK) + +/*! + * @brief TIM_PDER Register Bit Definition + */ + +#define TIM_PDER_CCR5SHIFTEN_SHIFT (5) +#define TIM_PDER_CCR5SHIFTEN_MASK (0x01U << TIM_PDER_CCR5SHIFTEN_SHIFT) +#define TIM_PDER_CCR5SHIFTEN(x) (((uint32_t)(((uint32_t)(x)) << TIM_PDER_CCR5SHIFTEN_SHIFT)) & TIM_PDER_CCR5SHIFTEN_MASK) + +#define TIM_PDER_CCR4SHIFTEN_SHIFT (4) +#define TIM_PDER_CCR4SHIFTEN_MASK (0x01U << TIM_PDER_CCR4SHIFTEN_SHIFT) +#define TIM_PDER_CCR4SHIFTEN(x) (((uint32_t)(((uint32_t)(x)) << TIM_PDER_CCR4SHIFTEN_SHIFT)) & TIM_PDER_CCR4SHIFTEN_MASK) + +#define TIM_PDER_CCR3SHIFTEN_SHIFT (3) +#define TIM_PDER_CCR3SHIFTEN_MASK (0x01U << TIM_PDER_CCR3SHIFTEN_SHIFT) +#define TIM_PDER_CCR3SHIFTEN(x) (((uint32_t)(((uint32_t)(x)) << TIM_PDER_CCR3SHIFTEN_SHIFT)) & TIM_PDER_CCR3SHIFTEN_MASK) + +#define TIM_PDER_CCR2SHIFTEN_SHIFT (2) +#define TIM_PDER_CCR2SHIFTEN_MASK (0x01U << TIM_PDER_CCR2SHIFTEN_SHIFT) +#define TIM_PDER_CCR2SHIFTEN(x) (((uint32_t)(((uint32_t)(x)) << TIM_PDER_CCR2SHIFTEN_SHIFT)) & TIM_PDER_CCR2SHIFTEN_MASK) + +#define TIM_PDER_CCR1SHIFTEN_SHIFT (1) +#define TIM_PDER_CCR1SHIFTEN_MASK (0x01U << TIM_PDER_CCR1SHIFTEN_SHIFT) +#define TIM_PDER_CCR1SHIFTEN(x) (((uint32_t)(((uint32_t)(x)) << TIM_PDER_CCR1SHIFTEN_SHIFT)) & TIM_PDER_CCR1SHIFTEN_MASK) + +#define TIM_PDER_CCDREPE_SHIFT (0) +#define TIM_PDER_CCDREPE_MASK (0x01U << TIM_PDER_CCDREPE_SHIFT) +#define TIM_PDER_CCDREPE(x) (((uint32_t)(((uint32_t)(x)) << TIM_PDER_CCDREPE_SHIFT)) & TIM_PDER_CCDREPE_MASK) + +/*! + * @brief TIM_CCRFALL Register Bit Definition + */ + +#define TIM_CCRFALL_CCRFALL_SHIFT (0) +#define TIM_CCRFALL_CCRFALL_MASK (0xFFFFU << TIM_CCRFALL_CCRFALL_SHIFT) +#define TIM_CCRFALL_CCRFALL(x) (((uint32_t)(((uint32_t)(x)) << TIM_CCRFALL_CCRFALL_SHIFT)) & TIM_CCRFALL_CCRFALL_MASK) + +/*! + * @brief TIM_BKINF Register Bit Definition + */ + +#define TIM_BKINF_COMPBKINSEL_SHIFT (13) +#define TIM_BKINF_COMPBKINSEL_MASK (0x7U << TIM_BKINF_COMPBKINSEL_SHIFT) +#define TIM_BKINF_COMPBKINSEL(x) (((uint32_t)(((uint32_t)(x)) << TIM_BKINF_COMPBKINSEL_SHIFT)) & TIM_BKINF_COMPBKINSEL_MASK) + +#define TIM_BKINF_IOBKINSEL_SHIFT (6) +#define TIM_BKINF_IOBKINSEL_MASK (0xFU << TIM_BKINF_IOBKINSEL_SHIFT) +#define TIM_BKINF_IOBKINSEL(x) (((uint32_t)(((uint32_t)(x)) << TIM_BKINF_IOBKINSEL_SHIFT)) & TIM_BKINF_IOBKINSEL_MASK) + +#define TIM_BKINF_CSSBKINSEL_SHIFT (5) +#define TIM_BKINF_CSSBKINSEL_MASK (0x01U << TIM_BKINF_CSSBKINSEL_SHIFT) +#define TIM_BKINF_CSSBKINSEL(x) (((uint32_t)(((uint32_t)(x)) << TIM_BKINF_CSSBKINSEL_SHIFT)) & TIM_BKINF_CSSBKINSEL_MASK) + +#define TIM_BKINF_BKINF_SHIFT (1) +#define TIM_BKINF_BKINF_MASK (0xFU << TIM_BKINF_BKINF_SHIFT) +#define TIM_BKINF_BKINF(x) (((uint32_t)(((uint32_t)(x)) << TIM_BKINF_BKINF_SHIFT)) & TIM_BKINF_BKINF_MASK) + +#define TIM_BKINF_BKINFE_SHIFT (0) +#define TIM_BKINF_BKINFE_MASK (0x01U << TIM_BKINF_BKINFE_SHIFT) +#define TIM_BKINF_BKINFE(x) (((uint32_t)(((uint32_t)(x)) << TIM_BKINF_BKINFE_SHIFT)) & TIM_BKINF_BKINFE_MASK) + +/*! + * @} + */ /* end of group TIM_Register_Masks */ + +/*! + * @} + */ /* end of group TIM_Peripheral_Access_Layer */ + + + + #endif /* __MM32F5277E_FEATURES_H__ */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/system_mm32f5277e.c b/platform/vendor_bsp/MindMotion/MM32F527/system_mm32f5277e.c new file mode 100644 index 000000000..c50bd52aa --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/system_mm32f5277e.c @@ -0,0 +1,43 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#include "hal_device_registers.h" + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __VECTOR_TABLE; +#endif + +void SystemInit(void) +{ + +#if defined (__FPU_PRESENT ) && (__FPU_PRESENT == 1U) + #if defined(__FPU_USED) && (__FPU_USED == 1u) + SCB->CPACR |= (SCB_CPACR_CP10_MASK | SCB_CPACR_CP11_MASK); /* set CP10, CP11 Full Access */ + #endif +#endif /* __FPU_PRESENT */ + +#if defined (__ICACHE_PRESENT )&& (__ICACHE_PRESENT == 1U) +#ifndef ICACHE_DISABLED + if (SCB->CLIDR & SCB_CLIDR_IC_Msk) + { + SCB_EnableICache(); + } +#endif /* DCACHE_DISABLED */ + +#endif /* __ICACHE_PRESENT */ +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) +#ifndef DCACHE_DISABLED + if (SCB->CLIDR & SCB_CLIDR_IC_Msk) + { + SCB_EnableDCache(); + } +#endif /* DCACHE_DISABLED */ +#endif /* __DCACHE_PRESENT */ +} + +/* EOF. */ diff --git a/platform/vendor_bsp/MindMotion/MM32F527/system_mm32f5277e.h b/platform/vendor_bsp/MindMotion/MM32F527/system_mm32f5277e.h new file mode 100644 index 000000000..099a4855d --- /dev/null +++ b/platform/vendor_bsp/MindMotion/MM32F527/system_mm32f5277e.h @@ -0,0 +1,18 @@ +/* + * Copyright 2022 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + +#ifndef __SYSTEM_MM32F5277E_H__ +#define __SYSTEM_MM32F5277E_H__ + +/* define the CP10 & CP11 full access to the FP Extension. */ +#define SCB_CPACR_CP10_MASK ( 0x03 << 20u) +#define SCB_CPACR_CP11_MASK (0x03 << 22u) + +void SystemInit(void); + +#endif /* __SYSTEM_MM32F5277E_H__ */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Include/gd32f3x0.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Include/gd32f3x0.h new file mode 100644 index 000000000..97d121559 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Include/gd32f3x0.h @@ -0,0 +1,243 @@ +/*! + \file gd32f3x0.h + \brief general definitions for gd32f3x0 + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_H +#define GD32F3X0_H + +#ifdef cplusplus +extern "C" { +#endif + + /* define GD32F3x0 */ +#if !defined (GD32F3x0) +#define GD32F3x0 +#endif /* define GD32F3x0 */ +#if !defined (GD32F3x0) +#error "Please select the target GD32F3x0 device used in your application (in gd32f3x0.h file)" +#endif /* undefine GD32F3x0 tip */ + + /* define GD32F3x0 device category */ +#if (!defined (GD32F310))&&(!defined (GD32F330))&&(!defined (GD32F350)) +#error "Please select GD32F3x0 device category( GD32F310 or GD32F330 or GD32F350 )" +#endif /* undefine GD32F330 or GD32F350 tip */ +#if (defined (GD32F310))&&(defined (GD32F330))&&(defined (GD32F350)) +#error "Please select one GD32F3x0 device category( GD32F310 or GD32F330 or GD32F350 )" +#endif /* define GD32F330 and GD32F350 tip */ + + /* define value of high speed crystal oscillator (HXTAL) in Hz */ +#if !defined (HXTAL_VALUE) +#define HXTAL_VALUE ((uint32_t)8000000) +#endif /* high speed crystal oscillator value */ + + /* define startup timeout value of high speed crystal oscillator (HXTAL) */ +#if !defined (HXTAL_STARTUP_TIMEOUT) +#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800) +#endif /* high speed crystal oscillator startup timeout */ + + /* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ +#if !defined (IRC8M_VALUE) +#define IRC8M_VALUE ((uint32_t)8000000) +#endif /* internal 8MHz RC oscillator value */ + + /* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ +#if !defined (IRC8M_STARTUP_TIMEOUT) +#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) +#endif /* internal 8MHz RC oscillator startup timeout */ + + /* define value of internal RC oscillator for ADC in Hz */ +#if !defined (IRC28M_VALUE) +#define IRC28M_VALUE ((uint32_t)28000000) +#endif /* IRC28M_VALUE */ + +#if !defined (IRC48M_VALUE) +#define IRC48M_VALUE ((uint32_t)48000000) +#endif /* IRC48M_VALUE */ + + /* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ +#if !defined (IRC40K_VALUE) +#define IRC40K_VALUE ((uint32_t)40000) +#endif /* internal 40KHz RC oscillator value */ + + /* define value of low speed crystal oscillator (LXTAL)in Hz */ +#if !defined (LXTAL_VALUE) +#define LXTAL_VALUE ((uint32_t)32768) +#endif /* low speed crystal oscillator value */ + + /* GD32F3x0 firmware library version number V1.0 */ +#define __GD32F3x0_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __GD32F3x0_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ +#define __GD32F3x0_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __GD32F3x0_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __GD32F3x0_STDPERIPH_VERSION ((__GD32F3x0_STDPERIPH_VERSION_MAIN << 24)\ + |(__GD32F3x0_STDPERIPH_VERSION_SUB1 << 16)\ + |(__GD32F3x0_STDPERIPH_VERSION_SUB2 << 8)\ + |(__GD32F3x0_STDPERIPH_VERSION_RC)) + + /* configuration of the Cortex-M4 processor and core peripherals */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0U /*!< GD32F3x0 do not provide MPU */ +#define __NVIC_PRIO_BITS 4U /*!< GD32F3x0 uses 4 bits for the priority levels */ +#define __Vendor_SysTickConfig 0U /*!< set to 1 if different sysTick config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ + + /* define interrupt number */ + typedef enum IRQn { + /* Cortex-M4 processor exceptions numbers */ + NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */ + /* interruput numbers */ + WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */ + LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ + RTC_IRQn = 2, /*!< RTC interrupt */ + FMC_IRQn = 3, /*!< FMC interrupt */ + RCU_CTC_IRQn = 4, /*!< RCU and CTC interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI line 0 and 1 interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI line 2 and 3 interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI line 4 to 15 interrupts */ + TSI_IRQn = 8, /*!< TSI Interrupt */ + DMA_Channel0_IRQn = 9, /*!< DMA channel 0 interrupt */ + DMA_Channel1_2_IRQn = 10, /*!< DMA channel 1 and channel 2 interrupts */ + DMA_Channel3_4_IRQn = 11, /*!< DMA channel 3 and channel 4 interrupts */ + ADC_CMP_IRQn = 12, /*!< ADC, CMP0 and CMP1 interrupts */ + TIMER0_BRK_UP_TRG_COM_IRQn = 13, /*!< TIMER0 break, update, trigger and commutation interrupts */ + TIMER0_Channel_IRQn = 14, /*!< TIMER0 channel capture compare interrupts */ + TIMER1_IRQn = 15, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 16, /*!< TIMER2 interrupt */ +#ifdef GD32F350 + TIMER5_DAC_IRQn = 17, /*!< TIMER5 and DAC interrupts */ +#endif /* GD32F350 */ + TIMER13_IRQn = 19, /*!< TIMER13 interrupt */ + TIMER14_IRQn = 20, /*!< TIMER14 interrupt */ + TIMER15_IRQn = 21, /*!< TIMER15 interrupt */ + TIMER16_IRQn = 22, /*!< TIMER16 interrupt */ + I2C0_EV_IRQn = 23, /*!< I2C0 event interrupt */ + I2C1_EV_IRQn = 24, /*!< I2C1 event interrupt */ + SPI0_IRQn = 25, /*!< SPI0 interrupt */ + SPI1_IRQn = 26, /*!< SPI1 interrupt */ + USART0_IRQn = 27, /*!< USART0 interrupt */ + USART1_IRQn = 28, /*!< USART1 interrupt */ +#ifdef GD32F350 + CEC_IRQn = 30, /*!< CEC interrupt */ +#endif /* GD32F350 */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ + DMA_Channel5_6_IRQn = 48, /*!< DMA channel 5 and channel 6 interrupts */ +#ifdef GD32F350 + USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ + USBFS_IRQn = 67, /*!< USBFS global interrupt */ +#endif /* GD32F350 */ + } IRQn_Type; + + /* includes */ +#include "core_cm4.h" +#include "system_gd32f3x0.h" +#include + + /* enum definitions */ + typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; + typedef enum {FALSE = 0, TRUE = !FALSE} bool; + typedef enum {RESET = 0, SET = !RESET} FlagStatus; + typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + + /* bit operations */ +#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) +#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) +#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) +#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) + + /* main flash and SRAM memory map */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */ + /* SRAM and peripheral base bit-band region */ +#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM bit-band base address */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< peripheral bit-band base address */ + /* peripheral memory map */ +#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ +#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ +#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */ +#define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */ + /* advanced peripheral bus 1 memory map */ +#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ +#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ +#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ +#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ +#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ +#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ +#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ +#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ +#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ +#define CEC_BASE (APB1_BUS_BASE + 0x00007800U) /*!< CEC base address */ +#define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */ + /* advanced peripheral bus 2 memory map */ +#define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */ +#define CMP_BASE (APB2_BUS_BASE + 0x0000001CU) /*!< CMP base address */ +#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ +#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ + /* advanced high performance bus 1 memory map */ +#define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */ +#define DMA_CHANNEL_BASE (DMA_BASE + 0x00000008U) /*!< DMA channel base address */ +#define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */ +#define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */ +#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */ +#define TSI_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< TSI base address */ +#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE0000U) /*!< USBFS base address */ + /* advanced high performance bus 2 memory map */ +#define GPIO_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address */ + /* option byte and debug memory map */ +#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ +#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ + + /* define marco USE_STDPERIPH_DRIVER */ +#if !defined USE_STDPERIPH_DRIVER +#define USE_STDPERIPH_DRIVER +#endif +#ifdef USE_STDPERIPH_DRIVER +#include "gd32f3x0_libopt.h" +#endif /* USE_STDPERIPH_DRIVER */ + +#ifdef cplusplus +} +#endif +#endif diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Include/system_gd32f3x0.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Include/system_gd32f3x0.h new file mode 100644 index 000000000..732330557 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Include/system_gd32f3x0.h @@ -0,0 +1,58 @@ +/*! + \file system_gd32f3x0.h + \brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for + GD32F3x0 Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#ifndef SYSTEM_GD32F3X0_H +#define SYSTEM_GD32F3X0_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* system clock frequency (core clock) */ +extern uint32_t SystemCoreClock; + +/* function declarations */ +/* initialize the system and update the SystemCoreClock variable */ +extern void SystemInit(void); +/* update the SystemCoreClock with current core clock retrieved from cpu registers */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_GD32F3X0_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Source/ARM/startup_gd32f3x0.s b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Source/ARM/startup_gd32f3x0.s new file mode 100644 index 000000000..712152c8f --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Source/ARM/startup_gd32f3x0.s @@ -0,0 +1,320 @@ +;/*! +; \file startup_gd32f3x0.s +; \brief start up file +; +; \version 2017-06-06, V1.0.0, firmware for GD32F3x0 +; \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +; \version 2020-09-30, V2.1.0, firmware for GD32F3x0 +; \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +;*/ + +;/* + ;Copyright (c) 2022, GigaDevice Semiconductor Inc. + + ;Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: + + ;1. Redistributions of source code must retain the above copyright notice, this + ;list of conditions and the following disclaimer. + ;2. Redistributions in binary form must reproduce the above copyright notice, + ;this list of conditions and the following disclaimer in the documentation + ;and/or other materials provided with the distribution. + ;3. Neither the name of the copyright holder nor the names of its contributors + ;may be used to endorse or promote products derived from this software without + ;specific prior written permission. + + ;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD RTC_IRQHandler ; 18:RTC through EXTI Line + DCD FMC_IRQHandler ; 19:FMC + DCD RCU_CTC_IRQHandler ; 20:RCU and CTC + DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1 + DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3 + DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15 + DCD TSI_IRQHandler ; 24:TSI + DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0 + DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2 + DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4 + DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator 0-1 + DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation + DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; 31:TIMER1 + DCD TIMER2_IRQHandler ; 32:TIMER2 + DCD TIMER5_DAC_IRQHandler ; 33:TIMER5 and DAC + DCD 0 ; Reserved + DCD TIMER13_IRQHandler ; 35:TIMER13 + DCD TIMER14_IRQHandler ; 36:TIMER14 + DCD TIMER15_IRQHandler ; 37:TIMER15 + DCD TIMER16_IRQHandler ; 38:TIMER16 + DCD I2C0_EV_IRQHandler ; 39:I2C0 Event + DCD I2C1_EV_IRQHandler ; 40:I2C1 Event + DCD SPI0_IRQHandler ; 41:SPI0 + DCD SPI1_IRQHandler ; 42:SPI1 + DCD USART0_IRQHandler ; 43:USART0 + DCD USART1_IRQHandler ; 44:USART1 + DCD 0 ; Reserved + DCD CEC_IRQHandler ; 46:CEC + DCD 0 ; Reserved + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD 0 ; Reserved + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA_Channel5_6_IRQHandler ; 64:DMA Channel5 and Channel6 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USBFS_IRQHandler ; 83:USBFS +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_CTC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSI_IRQHandler [WEAK] + EXPORT DMA_Channel0_IRQHandler [WEAK] + EXPORT DMA_Channel1_2_IRQHandler [WEAK] + EXPORT DMA_Channel3_4_IRQHandler [WEAK] + EXPORT ADC_CMP_IRQHandler [WEAK] + EXPORT TIMER0_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER5_DAC_IRQHandler [WEAK] + EXPORT TIMER13_IRQHandler [WEAK] + EXPORT TIMER14_IRQHandler [WEAK] + EXPORT TIMER15_IRQHandler [WEAK] + EXPORT TIMER16_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT USBFS_WKUP_IRQHandler [WEAK] + EXPORT DMA_Channel5_6_IRQHandler [WEAK] + EXPORT USBFS_IRQHandler [WEAK] + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCU_CTC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSI_IRQHandler +DMA_Channel0_IRQHandler +DMA_Channel1_2_IRQHandler +DMA_Channel3_4_IRQHandler +ADC_CMP_IRQHandler +TIMER0_BRK_UP_TRG_COM_IRQHandler +TIMER0_Channel_IRQHandler +TIMER1_IRQHandler +TIMER2_IRQHandler +TIMER5_DAC_IRQHandler +TIMER13_IRQHandler +TIMER14_IRQHandler +TIMER15_IRQHandler +TIMER16_IRQHandler +I2C0_EV_IRQHandler +I2C1_EV_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +CEC_IRQHandler +I2C0_ER_IRQHandler +I2C1_ER_IRQHandler +USBFS_WKUP_IRQHandler +DMA_Channel5_6_IRQHandler +USBFS_IRQHandler + + B . + ENDP + + ALIGN + +; user Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Source/GCC/startup_gd32f3x0.s b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Source/GCC/startup_gd32f3x0.s new file mode 100644 index 000000000..78a23ac8f --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Source/GCC/startup_gd32f3x0.s @@ -0,0 +1,265 @@ +;/*! +; \file startup_gd32f3x0.s +; \brief start up file +; +; \version 2017-06-06, V1.0.0, firmware for GD32F3x0 +; \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +; \version 2020-09-30, V2.1.0, firmware for GD32F3x0 +; \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +;*/ + +;/* + ;Copyright (c) 2022, GigaDevice Semiconductor Inc. + + ;Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: + + ;1. Redistributions of source code must retain the above copyright notice, this + ;list of conditions and the following disclaimer. + ;2. Redistributions in binary form must reproduce the above copyright notice, + ;this list of conditions and the following disclaimer in the documentation + ;and/or other materials provided with the distribution. + ;3. Neither the name of the copyright holder nor the names of its contributors + ;may be used to endorse or promote products derived from this software without + ;specific prior written permission. + + ;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + +.syntax unified +.cpu cortex-m4 +.fpu fpv4-sp-d16 +.thumb + +.section .isr_vector,"a",%progbits +.type g_pfnVectors, %object +g_pfnVectors: + .word _estack // Top of Stack + .word Reset_Handler // Reset Handler + .word NMI_Handler // NMI Handler + .word HardFault_Handler // Hard Fault Handler + .word MemManage_Handler // MPU Fault Handler + .word BusFault_Handler // Bus Fault Handler + .word UsageFault_Handler // Usage Fault Handler + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word SVC_Handler // SVCall Handler + .word DebugMon_Handler // Debug Monitor Handler + .word 0 // Reserved + .word PendSV_Handler // PendSV Handler + .word SysTick_Handler // SysTick Handler + + /* external interrupts handler */ + .word WWDGT_IRQHandler // 16:Window Watchdog Timer + .word LVD_IRQHandler // 17:LVD through EXTI Line detect + .word RTC_IRQHandler // 18:RTC through EXTI Line + .word FMC_IRQHandler // 19:FMC + .word RCU_CTC_IRQHandler // 20:RCU and CTC + .word EXTI0_1_IRQHandler // 21:EXTI Line 0 and EXTI Line 1 + .word EXTI2_3_IRQHandler // 22:EXTI Line 2 and EXTI Line 3 + .word EXTI4_15_IRQHandler // 23:EXTI Line 4 to EXTI Line 15 + .word TSI_IRQHandler // 24:TSI + .word DMA_Channel0_IRQHandler // 25:DMA Channel 0 + .word DMA_Channel1_2_IRQHandler // 26:DMA Channel 1 and DMA Channel 2 + .word DMA_Channel3_4_IRQHandler // 27:DMA Channel 3 and DMA Channel 4 + .word ADC_CMP_IRQHandler // 28:ADC and Comparator 0-1 + .word TIMER0_BRK_UP_TRG_COM_IRQHandler // 29:TIMER0 Break,Update,Trigger and Commutation + .word TIMER0_Channel_IRQHandler // 30:TIMER0 Channel Capture Compare + .word TIMER1_IRQHandler // 31:TIMER1 + .word TIMER2_IRQHandler // 32:TIMER2 + .word TIMER5_DAC_IRQHandler // 33:TIMER5 and DAC + .word 0 // Reserved + .word TIMER13_IRQHandler // 35:TIMER13 + .word TIMER14_IRQHandler // 36:TIMER14 + .word TIMER15_IRQHandler // 37:TIMER15 + .word TIMER16_IRQHandler // 38:TIMER16 + .word I2C0_EV_IRQHandler // 39:I2C0 Event + .word I2C1_EV_IRQHandler // 40:I2C1 Event + .word SPI0_IRQHandler // 41:SPI0 + .word SPI1_IRQHandler // 42:SPI1 + .word USART0_IRQHandler // 43:USART0 + .word USART1_IRQHandler // 44:USART1 + .word 0 // Reserved + .word CEC_IRQHandler // 46:CEC + .word 0 // Reserved + .word I2C0_ER_IRQHandler // 48:I2C0 Error + .word 0 // Reserved + .word I2C1_ER_IRQHandler // 50:I2C1 Error + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word USBFS_WKUP_IRQHandler // 58:USBFS Wakeup + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word DMA_Channel5_6_IRQHandler // 64:DMA Channel5 and Channel6 + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word 0 // Reserved + .word USBFS_IRQHandler // 83:USBFS + /* set size of g_pfnVectors */ + .size g_pfnVectors, . - g_pfnVectors + +.weak Reset_Handler +.type Reset_Handler, %function +Reset_Handler: + ldr r1, =_sidata + ldr r2, =_sdata + ldr r3, =_edata + + subs r3, r2 + ble fill_bss_start + +loop_copy_data: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt loop_copy_data + +fill_bss_start: + ldr r1, =__bss_start + ldr r2, =__bss_end + movs r0, 0 + subs r2, r1 + ble startup_enter + +loop_fill_bss: + subs r2, #4 + str r0, [r1, r2] + bgt loop_fill_bss + +startup_enter: + bl SystemInit + bl main + + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + b . + .size NMI_Handler, . - NMI_Handler + + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + b . + .size HardFault_Handler, . - HardFault_Handler + + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + b . + .size MemManage_Handler, . - MemManage_Handler + + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + b . + .size BusFault_Handler, . - BusFault_Handler + + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + b . + .size UsageFault_Handler, . - UsageFault_Handler + + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + b . + .size SVC_Handler, . - SVC_Handler + + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + b . + .size DebugMon_Handler, . - DebugMon_Handler + + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + b . + .size PendSV_Handler, . - PendSV_Handler + + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + b . + .size SysTick_Handler, . - SysTick_Handler + + .section .text.Default_Handler,"ax",%progbits + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + .macro IRQ handler + .weak \handler + .set \handler, Default_Handler + .endm +/* external interrupts handler */ + IRQ WWDGT_IRQHandler + IRQ LVD_IRQHandler + IRQ RTC_IRQHandler + IRQ FMC_IRQHandler + IRQ RCU_CTC_IRQHandler + IRQ EXTI0_1_IRQHandler + IRQ EXTI2_3_IRQHandler + IRQ EXTI4_15_IRQHandler + IRQ TSI_IRQHandler + IRQ DMA_Channel0_IRQHandler + IRQ DMA_Channel1_2_IRQHandler + IRQ DMA_Channel3_4_IRQHandler + IRQ ADC_CMP_IRQHandler + IRQ TIMER0_BRK_UP_TRG_COM_IRQHandler + IRQ TIMER0_Channel_IRQHandler + IRQ TIMER1_IRQHandler + IRQ TIMER2_IRQHandler + IRQ TIMER5_DAC_IRQHandler + IRQ TIMER13_IRQHandler + IRQ TIMER14_IRQHandler + IRQ TIMER15_IRQHandler + IRQ TIMER16_IRQHandler + IRQ I2C0_EV_IRQHandler + IRQ I2C1_EV_IRQHandler + IRQ SPI0_IRQHandler + IRQ SPI1_IRQHandler + IRQ USART0_IRQHandler + IRQ USART1_IRQHandler + IRQ CEC_IRQHandler + IRQ I2C0_ER_IRQHandler + IRQ I2C1_ER_IRQHandler + IRQ USBFS_WKUP_IRQHandler + IRQ DMA_Channel5_6_IRQHandler + IRQ USBFS_IRQHandler diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Source/IAR/startup_gd32f3x0.s b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Source/IAR/startup_gd32f3x0.s new file mode 100644 index 000000000..8c264c7b4 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Source/IAR/startup_gd32f3x0.s @@ -0,0 +1,368 @@ +;/*! +; \file startup_gd32f3x0.s +; \brief start up file +; +; \version 2017-06-06, V1.0.0, firmware for GD32F3x0 +; \version 2019-06-01, V2.0.0, firmware for GD32F3x0 +; \version 2020-09-30, V2.1.0, firmware for GD32F3x0 +; \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +;*/ + +;/* + ;Copyright (c) 2022, GigaDevice Semiconductor Inc. + + ;Redistribution and use in source and binary forms, with or without modification, +;are permitted provided that the following conditions are met: + + ;1. Redistributions of source code must retain the above copyright notice, this + ;list of conditions and the following disclaimer. + ;2. Redistributions in binary form must reproduce the above copyright notice, + ;this list of conditions and the following disclaimer in the documentation + ;and/or other materials provided with the distribution. + ;3. Neither the name of the copyright holder nor the names of its contributors + ;may be used to endorse or promote products derived from this software without + ;specific prior written permission. + + ;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +;OF SUCH DAMAGE. +;*/ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; top of stack + DCD Reset_Handler ; Vector Number 1,Reset Handler + + DCD NMI_Handler ; Vector Number 2,NMI Handler + DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler + DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler + DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler + DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; Vector Number 11,SVCall Handler + DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; Vector Number 14,PendSV Handler + DCD SysTick_Handler ; Vector Number 15,SysTick Handler + + ; External Interrupts + DCD WWDGT_IRQHandler ; Vector Number 16,Window watchdog timer + DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect + DCD RTC_IRQHandler ; Vector Number 18,RTC through EXTI Line + DCD FMC_IRQHandler ; Vector Number 19,FMC + DCD RCU_CTC_IRQHandler ; Vector Number 20,RCU and CTC + DCD EXTI0_1_IRQHandler ; Vector Number 21,EXTI Line 0 and EXTI Line 1 + DCD EXTI2_3_IRQHandler ; Vector Number 22,EXTI Line 2 and EXTI Line 3 + DCD EXTI4_15_IRQHandler ; Vector Number 23,EXTI Line 4 to EXTI Line 15 + DCD TSI_IRQHandler ; Vector Number 24,TSI + DCD DMA_Channel0_IRQHandler ; Vector Number 25,DMA Channel 0 + DCD DMA_Channel1_2_IRQHandler ; Vector Number 26,DMA Channel 1 and DMA Channel 2 + DCD DMA_Channel3_4_IRQHandler ; Vector Number 27,DMA Channel 3 and DMA Channel 4 + DCD ADC_CMP_IRQHandler ; Vector Number 28,ADC and Comparator 1-2 + DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; Vector Number 29,TIMER0 Break, Update, Trigger and Commutation + DCD TIMER0_Channel_IRQHandler ; Vector Number 30,TIMER0 Channel Capture Compare + DCD TIMER1_IRQHandler ; Vector Number 31,TIMER1 + DCD TIMER2_IRQHandler ; Vector Number 32,TIMER2 + DCD TIMER5_DAC_IRQHandler ; Vector Number 33,TIMER5 and DAC + DCD 0 ; Reserved + DCD TIMER13_IRQHandler ; Vector Number 35,TIMER13 + DCD TIMER14_IRQHandler ; Vector Number 36,TIMER14 + DCD TIMER15_IRQHandler ; Vector Number 37,TIMER15 + DCD TIMER16_IRQHandler ; Vector Number 38,TIMER16 + DCD I2C0_EV_IRQHandler ; Vector Number 39,I2C0 Event + DCD I2C1_EV_IRQHandler ; Vector Number 40,I2C1 Event + DCD SPI0_IRQHandler ; Vector Number 41,SPI0 + DCD SPI1_IRQHandler ; Vector Number 42,SPI1 + DCD USART0_IRQHandler ; Vector Number 43,USART0 + DCD USART1_IRQHandler ; Vector Number 44,USART1 + DCD 0 ; Reserved + DCD CEC_IRQHandler ; Vector Number 46,CEC + DCD 0 ; Reserved + DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error + DCD 0 ; Reserved + DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USBFS_WKUP_IRQHandler ; Vector Number 58,USBFS Wakeup + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA_Channel5_6_IRQHandler ; Vector Number 64,DMA Channel5 and Channel6 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USBFS_IRQHandler ; Vector Number 83,USBFS + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDGT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDGT_IRQHandler + B WWDGT_IRQHandler + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK RCU_CTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCU_CTC_IRQHandler + B RCU_CTC_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK TSI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSI_IRQHandler + B TSI_IRQHandler + + PUBWEAK DMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_Channel0_IRQHandler + B DMA_Channel0_IRQHandler + + PUBWEAK DMA_Channel1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_Channel1_2_IRQHandler + B DMA_Channel1_2_IRQHandler + + PUBWEAK DMA_Channel3_4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_Channel3_4_IRQHandler + B DMA_Channel3_4_IRQHandler + + PUBWEAK ADC_CMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_CMP_IRQHandler + B ADC_CMP_IRQHandler + + PUBWEAK TIMER0_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_BRK_UP_TRG_COM_IRQHandler + B TIMER0_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIMER0_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_Channel_IRQHandler + B TIMER0_Channel_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER5_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER5_DAC_IRQHandler + B TIMER5_DAC_IRQHandler + + PUBWEAK TIMER13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER13_IRQHandler + B TIMER13_IRQHandler + + PUBWEAK TIMER14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER14_IRQHandler + B TIMER14_IRQHandler + + PUBWEAK TIMER15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER15_IRQHandler + B TIMER15_IRQHandler + + PUBWEAK TIMER16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER16_IRQHandler + B TIMER16_IRQHandler + + PUBWEAK I2C0_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_IRQHandler + B I2C0_EV_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART0_IRQHandler + B USART0_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK I2C0_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ER_IRQHandler + B I2C0_ER_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK USBFS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_WKUP_IRQHandler + B USBFS_WKUP_IRQHandler + + PUBWEAK DMA_Channel5_6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_Channel5_6_IRQHandler + B DMA_Channel5_6_IRQHandler + + PUBWEAK USBFS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBFS_IRQHandler + B USBFS_IRQHandler + + END diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Source/system_gd32f3x0.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Source/system_gd32f3x0.c new file mode 100644 index 000000000..3c1f25c74 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/GD/GD32F3x0/Source/system_gd32f3x0.c @@ -0,0 +1,830 @@ +/*! + \file system_gd32f3x0.c + \brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for + GD32F3x0 Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32f3x0.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */ + +/* select a system clock by uncommenting the following line */ +#if defined (GD32F310) +//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) +//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) +#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2 (uint32_t)(72000000) +#endif /* GD32F310 */ + +#if defined (GD32F330) +//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) +//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2 (uint32_t)(72000000) +#define __SYSTEM_CLOCK_84M_PLL_HXTAL (uint32_t)(84000000) +//#define __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2 (uint32_t)(84000000) +#endif /* GD32F330 */ + +#if defined (GD32F350) +//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) +//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) +//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_84M_PLL_HXTAL (uint32_t)(84000000) +//#define __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2 (uint32_t)(84000000) +//#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) +//#define __SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2 (uint32_t)(96000000) +//#define __SYSTEM_CLOCK_97M_PLL_IRC48M_DIV2 (uint32_t)(96000000) +//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) +//#define __SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2 (uint32_t)(108000000) +#endif /* GD32F350 */ + +#define SEL_IRC8M 0x00 +#define SEL_HXTAL 0x01 +#define SEL_PLL 0x02 + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_8M_HXTAL +uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL; +static void system_clock_8m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2; +static void system_clock_72m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2; +static void system_clock_72m_irc48m(void); + +#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_84M_PLL_HXTAL; +static void system_clock_84m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2; +static void system_clock_84m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; +static void system_clock_96m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2; +static void system_clock_96m_irc8m(void); + +#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2; +static void system_clock_96m_irc48m(void); + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; +static void system_clock_108m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2; +static void system_clock_108m_irc8m(void); + +#else +uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M; +static void system_clock_8m_irc8m(void); +#endif /* __SYSTEM_CLOCK_8M_HXTAL */ + +/* configure the system clock */ +static void system_clock_config(void); + +/*! + \brief setup the microcontroller system, initialize the system + \param[in] none + \param[out] none + \retval none +*/ +void SystemInit(void) +{ +#if (defined(GD32F350)) + RCU_APB2EN |= BIT(0); + CMP_CS |= (CMP_CS_CMP1MSEL | CMP_CS_CMP0MSEL); +#endif /* GD32F350 */ + if(((FMC_OBSTAT & OB_OBSTAT_PLEVEL_HIGH) != OB_OBSTAT_PLEVEL_HIGH) && + (((FMC_OBSTAT >> 13) & 0x1) == SET)) { + FMC_KEY = UNLOCK_KEY0; + FMC_KEY = UNLOCK_KEY1 ; + FMC_OBKEY = UNLOCK_KEY0; + FMC_OBKEY = UNLOCK_KEY1 ; + FMC_CTL |= FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_START; + while((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)); + FMC_CTL &= ~FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_OBPG; + if((FMC_OBSTAT & OB_OBSTAT_PLEVEL_HIGH) == OB_OBSTAT_PLEVEL_NO) { + OB_SPC = FMC_NSPC; + } else if((FMC_OBSTAT & OB_OBSTAT_PLEVEL_HIGH) == OB_OBSTAT_PLEVEL_LOW) { + OB_SPC = FMC_LSPC; + } + OB_USER = OB_USER_DEFAULT & ((uint8_t)(FMC_OBSTAT >> 8)); + OB_DATA0 = ((uint8_t)(FMC_OBSTAT >> 16)); + OB_DATA1 = ((uint8_t)(FMC_OBSTAT >> 24)); + OB_WP0 = ((uint8_t)(FMC_WP)); + OB_WP1 = ((uint8_t)(FMC_WP >> 8)); + while((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)); + FMC_CTL &= ~FMC_CTL_OBPG; + FMC_CTL &= ~FMC_CTL_OBWEN; + FMC_CTL |= FMC_CTL_LK; + } + /* FPU settings */ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ +#endif + + /* enable IRC8M */ + RCU_CTL0 |= RCU_CTL0_IRC8MEN; + while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)) { + } + RCU_CFG0 &= ~(RCU_CFG0_SCS); + RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS); + + /* reset RCU */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | \ + RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); +#if (defined(GD32F350)) + RCU_CFG0 &= ~(RCU_CFG0_USBFSPSC); + RCU_CFG2 &= ~(RCU_CFG2_CECSEL | RCU_CFG2_USBFSPSC2); +#endif /* GD32F350 */ + + RCU_CFG1 &= ~(RCU_CFG1_PREDV | RCU_CFG1_PLLMF5 | RCU_CFG1_PLLPRESEL); + RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL); + RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; + RCU_CFG2 &= ~RCU_CFG2_ADCPSC2; + RCU_CTL1 &= ~RCU_CTL1_IRC28MEN; + RCU_ADDCTL &= ~RCU_ADDCTL_IRC48MEN; + RCU_INT = 0x00000000U; + RCU_ADDINT = 0x00000000U; + + /* configure system clock */ + system_clock_config(); + +#ifdef VECT_TAB_SRAM + nvic_vector_table_set(NVIC_VECTTAB_RAM, VECT_TAB_OFFSET); +#else + nvic_vector_table_set(NVIC_VECTTAB_FLASH, VECT_TAB_OFFSET); +#endif +} + +/*! + \brief configure the system clock + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_config(void) +{ +#ifdef __SYSTEM_CLOCK_8M_HXTAL + system_clock_8m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) + system_clock_72m_hxtal(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) + system_clock_72m_irc8m(); +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2) + system_clock_72m_irc48m(); +#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL) + system_clock_84m_hxtal(); +#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2) + system_clock_84m_irc8m(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) + system_clock_96m_hxtal(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2) + system_clock_96m_irc8m(); +#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2) + system_clock_96m_irc48m(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) + system_clock_108m_hxtal(); +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2) + system_clock_108m_irc8m(); +#else + system_clock_8m_irc8m(); +#endif /* __SYSTEM_CLOCK_8M_HXTAL */ +} + +#ifdef __SYSTEM_CLOCK_8M_HXTAL +/*! + \brief configure the system clock to 8M by HXTAL + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_8m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL0 |= RCU_CTL0_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ + if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)) { + return; + } + + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; + + /* select HXTAL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; + + /* wait until HXTAL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_HXTAL)) { + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +/*! + \brief configure the system clock to 72M by PLL which selects HXTAL as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL0 |= RCU_CTL0_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ + if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)) { + return; + } + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* PLL = HXTAL * 9 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLPREDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5 | RCU_CFG1_PREDV); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | (RCU_PLL_MUL9 & (~RCU_CFG1_PLLMF5))); + RCU_CFG1 |= (RCU_PLLPRESEL_HXTAL); + RCU_CFG1 |= (RCU_PLL_MUL9 & RCU_CFG1_PLLMF5); + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)) { + } +} + + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) +/*! + \brief configure the system clock to 72M by PLL which selects IRC8M/2 as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc8m(void) +{ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + /* PLL = (IRC8M/2) * 18 = 72 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLPREDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5 | RCU_CFG1_PREDV); + RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | (RCU_PLL_MUL18 & (~RCU_CFG1_PLLMF5))); + RCU_CFG1 |= (RCU_PLL_MUL18 & RCU_CFG1_PLLMF5); + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)) { + } +} + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2) +/*! + \brief configure the system clock to 72M by PLL which selects IRC48M/2 as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_72m_irc48m(void) +{ + /* enable IRC48M */ + RCU_ADDCTL |= RCU_ADDCTL_IRC48MEN; + + /* wait until IRC48M is stable*/ + while(0U == (RCU_ADDCTL & RCU_ADDCTL_IRC48MSTB)) { + } + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + /* PLL = (IRC48M/2) * 3 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLPREDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5 | RCU_CFG1_PREDV); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | (RCU_PLL_MUL3 & (~RCU_CFG1_PLLMF5))); + RCU_CFG1 |= (RCU_PLLPRESEL_IRC48M | RCU_PLL_PREDV2); + RCU_CFG1 |= (RCU_PLL_MUL3 & RCU_CFG1_PLLMF5); + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)) { + } +} + +#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL) +/*! + \brief configure the system clock to 84M by PLL which selects HXTAL as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_84m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + /* enable HXTAL */ + RCU_CTL0 |= RCU_CTL0_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ + if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)) { + return; + } + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* PLL = HXTAL /2 * 21 = 84 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLPREDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5 | RCU_CFG1_PREDV); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | (RCU_PLL_MUL21 & (~RCU_CFG1_PLLMF5))); + RCU_CFG1 |= (RCU_PLLPRESEL_HXTAL | RCU_PLL_PREDV2); + RCU_CFG1 |= (RCU_PLL_MUL21 & RCU_CFG1_PLLMF5); + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)) { + } +} + +#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2) +/*! + \brief configure the system clock to 84M by PLL which selects IRC8M/2 as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_84m_irc8m(void) +{ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + /* PLL = (IRC8M/2) * 21 = 84 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLPREDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5 | RCU_CFG1_PREDV); + RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | (RCU_PLL_MUL21 & (~RCU_CFG1_PLLMF5))); + RCU_CFG1 |= (RCU_PLL_MUL21 & RCU_CFG1_PLLMF5); + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)) { + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) +/*! + \brief configure the system clock to 96M by PLL which selects HXTAL as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + /* enable HXTAL */ + RCU_CTL0 |= RCU_CTL0_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ + if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)) { + return; + } + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* PLL = HXTAL /2 * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLPREDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5 | RCU_CFG1_PREDV); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | (RCU_PLL_MUL24 & (~RCU_CFG1_PLLMF5))); + RCU_CFG1 |= (RCU_PLLPRESEL_HXTAL | RCU_PLL_PREDV2); + RCU_CFG1 |= (RCU_PLL_MUL24 & RCU_CFG1_PLLMF5); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)) { + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2) +/*! + \brief configure the system clock to 96M by PLL which selects IRC8M/2 as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_irc8m(void) +{ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + /* PLL = (IRC8M/2) * 24 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLPREDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5 | RCU_CFG1_PREDV); + RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | (RCU_PLL_MUL24 & (~RCU_CFG1_PLLMF5))); + RCU_CFG1 |= (RCU_PLL_MUL24 & RCU_CFG1_PLLMF5); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)) { + } +} + +#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2) +/*! + \brief configure the system clock to 96M by PLL which selects IRC48M/2 as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_96m_irc48m(void) +{ + /* enable IRC48M */ + RCU_ADDCTL |= RCU_ADDCTL_IRC48MEN; + + /* wait until IRC48M is stable*/ + while(0U == (RCU_ADDCTL & RCU_ADDCTL_IRC48MSTB)) { + } + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + /* PLL = (IRC48M/2) * 4 = 96 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLPREDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5 | RCU_CFG1_PREDV); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | (RCU_PLL_MUL4 & (~RCU_CFG1_PLLMF5))); + RCU_CFG1 |= (RCU_PLLPRESEL_IRC48M | RCU_PLL_PREDV2); + RCU_CFG1 |= (RCU_PLL_MUL4 & RCU_CFG1_PLLMF5); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)) { + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) +/*! + \brief configure the system clock to 84M by PLL which selects HXTAL as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_hxtal(void) +{ + uint32_t timeout = 0U; + uint32_t stab_flag = 0U; + + /* enable HXTAL */ + RCU_CTL0 |= RCU_CTL0_HXTALEN; + + /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ + do { + timeout++; + stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); + } while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); + /* if fail */ + if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)) { + return; + } + /* HXTAL is stable */ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + + /* PLL = HXTAL /2 * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLPREDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5 | RCU_CFG1_PREDV); + RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | (RCU_PLL_MUL27 & (~RCU_CFG1_PLLMF5))); + RCU_CFG1 |= (RCU_PLLPRESEL_HXTAL | RCU_PLL_PREDV2); + RCU_CFG1 |= (RCU_PLL_MUL27 & RCU_CFG1_PLLMF5); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)) { + } +} + +#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2) +/*! + \brief configure the system clock to 108M by PLL which selects IRC8M/2 as its clock source + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_108m_irc8m(void) +{ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB/2 */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; + /* APB1 = AHB/2 */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; + /* PLL = (IRC8M/2) * 27 = 108 MHz */ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLPREDV); + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5 | RCU_CFG1_PREDV); + RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | (RCU_PLL_MUL27 & (~RCU_CFG1_PLLMF5))); + RCU_CFG1 |= (RCU_PLL_MUL27 & RCU_CFG1_PLLMF5); + + /* enable PLL */ + RCU_CTL0 |= RCU_CTL0_PLLEN; + + /* wait until PLL is stable */ + while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)) { + } + + /* select PLL as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_PLL; + + /* wait until PLL is selected as system clock */ + while(0U == (RCU_CFG0 & RCU_SCSS_PLL)) { + } +} + +#else +/*! + \brief configure the system clock to 8M by IRC8M + \param[in] none + \param[out] none + \retval none +*/ +static void system_clock_8m_irc8m(void) +{ + /* AHB = SYSCLK */ + RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; + /* APB2 = AHB */ + RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; + /* APB1 = AHB */ + RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; + + /* select IRC8M as system clock */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CFG0 |= RCU_CKSYSSRC_IRC8M; + + /* wait until IRC8M is selected as system clock */ + while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)) { + } +} +#endif /* __SYSTEM_CLOCK_8M_HXTAL */ + +/*! + \brief update the SystemCoreClock with current core clock retrieved from cpu registers + \param[in] none + \param[out] none + \retval none +*/ +void SystemCoreClockUpdate(void) +{ + uint32_t sws = 0U; + uint32_t pllmf = 0U, pllmf4 = 0U, pllmf5 = 0U, pllsel = 0U, pllpresel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U; + /* exponent of AHB clock divider */ + const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + sws = GET_BITS(RCU_CFG0, 2, 3); + switch(sws) { + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + SystemCoreClock = IRC8M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + SystemCoreClock = HXTAL_VALUE; + break; + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* get the value of PLLMF[3:0] */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + pllmf4 = GET_BITS(RCU_CFG0, 27, 27); + pllmf5 = GET_BITS(RCU_CFG1, 31, 31); + /* high 16 bits */ + if((0U == pllmf4) && (0U == pllmf5)) { + pllmf += 2U; + } + if((1U == pllmf4) && (0U == pllmf5)) { + pllmf += 17U; + } + if((0U == pllmf4) && (1U == pllmf5)) { + pllmf += 33U; + } + if((1U == pllmf4) && (1U == pllmf5)) { + pllmf += 49U; + } + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = GET_BITS(RCU_CFG0, 16, 16); + if(0U != pllsel) { + prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U); + if(0U == pllpresel) { + SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf; + } else { + SystemCoreClock = (IRC48M_VALUE / prediv) * pllmf; + } + } else { + SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf; + } + break; + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + SystemCoreClock >>= clk_exp; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/core_cm4.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/core_cm4.h new file mode 100644 index 000000000..ad5789d41 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/core_cm4.h @@ -0,0 +1,1778 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ +#define __packed +#define __ASM _asm /*!< asm keyword for COSMIC Compiler */ +#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __TMS470__ ) +#if defined __TI_VFP_SUPPORT__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined ( __CSMC__ ) /* Cosmic */ +#if ( __CSMC__ & 0x400) // FPU present for parser +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM4_REV +#define __CM4_REV 0x0000 +#warning "__CM4_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0 +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 4 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __O union { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits)) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority) & ((1 << (SubPriorityBits)) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if((ticks - 1) > SysTick_LOAD_RELOAD_Msk) { + return (1); /* Reload value impossible */ + } + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) +{ + if((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0))) { /* ITM Port #0 enabled */ + while(ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar(void) +{ + int32_t ch = -1; /* no character available */ + + if(ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar(void) +{ + + if(ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/core_cm4_simd.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/core_cm4_simd.h new file mode 100644 index 000000000..c7e144079 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/core_cm4_simd.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usad8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("usada8 %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile("uxtb16 %0, %1" : "=r"(result) : "r"(op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile("sxtb16 %0, %1" : "=r"(result) : "r"(op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smuad %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smuadx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlad %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smladx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else // Big endian + __ASM volatile("smlald %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else // Big endian + __ASM volatile("smlaldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smusd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smusdx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlsd %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlsdx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else // Big endian + __ASM volatile("smlsld %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[0]), "=r"(llr.w32[1]): "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else // Big endian + __ASM volatile("smlsldx %0, %1, %2, %3" : "=r"(llr.w32[1]), "=r"(llr.w32[0]): "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sel %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qadd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsub %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile("smmla %0, %1, %2, %3" : "=r"(result): "r"(op1), "r"(op2), "r"(op3)); + return(result); +} + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* not yet supported */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_SIMD_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/core_cmFunc.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/core_cmFunc.h new file mode 100644 index 000000000..30c0036cb --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/core_cmFunc.h @@ -0,0 +1,616 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) +#error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, control" : "=r"(result)); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile("MSR control, %0" : : "r"(control)); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, ipsr" : "=r"(result)); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, apsr" : "=r"(result)); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, xpsr" : "=r"(result)); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, psp\n" : "=r"(result)); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile("MSR psp, %0\n" : : "r"(topOfProcStack)); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, msp\n" : "=r"(result)); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile("MSR msp, %0\n" : : "r"(topOfMainStack)); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, primask" : "=r"(result)); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile("MSR primask, %0" : : "r"(priMask)); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, basepri_max" : "=r"(result)); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile("MSR basepri, %0" : : "r"(value)); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, faultmask" : "=r"(result)); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile("MSR faultmask, %0" : : "r"(faultMask)); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + __ASM volatile("VMRS %0, fpscr" : "=r"(result)); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + __ASM volatile("VMSR fpscr, %0" : : "r"(fpscr)); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/core_cmInstr.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/core_cmInstr.h new file mode 100644 index 000000000..b177d6a5d --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/CMSIS/core_cmInstr.h @@ -0,0 +1,618 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) +#error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rev %0, %1" : "=r"(result) : "r"(value)); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rev16 %0, %1" : "=r"(result) : "r"(value)); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile("revsh %0, %1" : "=r"(result) : "r"(value)); + return(result); +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + + __ASM volatile("ror %0, %0, %1" : "+r"(op1) : "r"(op2)); + return(op1); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value)); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr)); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr)); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("ldrex %0, [%1]" : "=r"(result) : "r"(addr)); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile("strexb %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value)); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile("strexh %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value)); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("strex %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value)); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile("clz %0, %1" : "=r"(result) : "r"(value)); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_adc.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_adc.h new file mode 100644 index 000000000..fb7df4245 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_adc.h @@ -0,0 +1,367 @@ +/*! + \file gd32f3x0_adc.h + \brief definitions for the ADC + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_ADC_H +#define GD32F3X0_ADC_H + +#include "gd32f3x0.h" + +/* ADC definitions */ +#define ADC ADC_BASE /*!< ADC base address */ + +/* registers definitions */ +#define ADC_STAT REG32(ADC + 0x00000000U) /*!< ADC status register */ +#define ADC_CTL0 REG32(ADC + 0x00000004U) /*!< ADC control register 0 */ +#define ADC_CTL1 REG32(ADC + 0x00000008U) /*!< ADC control register 1 */ +#define ADC_SAMPT0 REG32(ADC + 0x0000000CU) /*!< ADC sample time register 0 */ +#define ADC_SAMPT1 REG32(ADC + 0x00000010U) /*!< ADC sample time register 1 */ +#define ADC_IOFF0 REG32(ADC + 0x00000014U) /*!< ADC inserted channel data offset register 0 */ +#define ADC_IOFF1 REG32(ADC + 0x00000018U) /*!< ADC inserted channel data offset register 1 */ +#define ADC_IOFF2 REG32(ADC + 0x0000001CU) /*!< ADC inserted channel data offset register 2 */ +#define ADC_IOFF3 REG32(ADC + 0x00000020U) /*!< ADC inserted channel data offset register 3 */ +#define ADC_WDHT REG32(ADC + 0x00000024U) /*!< ADC watchdog high threshold register */ +#define ADC_WDLT REG32(ADC + 0x00000028U) /*!< ADC watchdog low threshold register */ +#define ADC_RSQ0 REG32(ADC + 0x0000002CU) /*!< ADC regular sequence register 0 */ +#define ADC_RSQ1 REG32(ADC + 0x00000030U) /*!< ADC regular sequence register 1 */ +#define ADC_RSQ2 REG32(ADC + 0x00000034U) /*!< ADC regular sequence register 2 */ +#define ADC_ISQ REG32(ADC + 0x00000038U) /*!< ADC inserted sequence register */ +#define ADC_IDATA0 REG32(ADC + 0x0000003CU) /*!< ADC inserted data register 0 */ +#define ADC_IDATA1 REG32(ADC + 0x00000040U) /*!< ADC inserted data register 1 */ +#define ADC_IDATA2 REG32(ADC + 0x00000044U) /*!< ADC inserted data register 2 */ +#define ADC_IDATA3 REG32(ADC + 0x00000048U) /*!< ADC inserted data register 3 */ +#define ADC_RDATA REG32(ADC + 0x0000004CU) /*!< ADC regular data register */ +#define ADC_OVSAMPCTL REG32(ADC + 0x00000080U) /*!< ADC oversampling control register */ + +/* bits definitions */ +/* ADC_STAT */ +#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ +#define ADC_STAT_EOC BIT(1) /*!< end of conversion flag */ +#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion flag */ +#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ +#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ + +/* ADC_CTL0 */ +#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ +#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ +#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ +#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ +#define ADC_CTL0_SM BIT(8) /*!< scan mode */ +#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ +#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ +#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ +#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ +#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ +#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ +#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ + +/* ADC_CTL1 */ +#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ +#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ +#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ +#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ +#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ +#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ +#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ +#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ +#define ADC_CTL1_ETERC BIT(20) /*!< external trigger enable for regular channel */ +#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ +#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ +#define ADC_CTL1_TSVREN BIT(23) /*!< enable channel 16 and 17 */ +#define ADC_CTL1_VBETEN BIT(24) /*!< VBAT enable */ + +/* ADC_SAMPTx x=0,1 */ +#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n(n=0..18) sample time selection */ + +/* ADC_IOFFx x=0..3 */ +#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ + +/* ADC_WDHT */ +#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ + +/* ADC_WDLT */ +#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ + +/* ADC_RSQx x=0..2 */ +#define ADC_RSQX_RSQN BITS(0,4) /*!< n conversion in regular sequence */ +#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ + +/* ADC_ISQ */ +#define ADC_ISQ_ISQN BITS(0,4) /*!< n conversion in regular sequence */ +#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ + +/* ADC_IDATAx x=0..3 */ +#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted channel x conversion data */ + +/* ADC_RDATA */ +#define ADC_RDATA_RDATA BITS(0,15) /*!< regular channel data */ + +/* ADC_OVSAMPCTL */ +#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ +#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ +#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ +#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ + +/* constants definitions */ +/* ADC flag definitions */ +#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ +#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion flag */ +#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted channel group conversion flag */ +#define ADC_FLAG_STIC ADC_STAT_STIC /*!< start flag of inserted channel group */ +#define ADC_FLAG_STRC ADC_STAT_STRC /*!< start flag of regular channel group */ + +/* adc_ctl0 register value */ +#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< number of conversions in discontinuous mode */ + +/* ADC special function */ +#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ +#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ + +/* ADC data alignment */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< right alignment */ +#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< left alignment */ + +/* external trigger select for regular channel */ +#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) +#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ +#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ +#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ +#define ADC_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */ +#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ +#define ADC_EXTTRIG_REGULAR_T14_CH0 CTL1_ETSRC(5) /*!< TIMER14 CH0 event select */ +#define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ +#define ADC_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ + +/* external trigger select for inserted channel */ +#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) +#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ +#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ +#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */ +#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */ +#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ +#define ADC_EXTTRIG_INSERTED_T14_TRGO CTL1_ETSIC(5) /*!< TIMER14 TRGO event select */ +#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ +#define ADC_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ + +/* adc_samptx register value */ +#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ +#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ +#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ +#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ +#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ +#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ +#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ +#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ + +/* ADC data offset for inserted channel x */ +#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + +/* ADC analog watchdog high threshold */ +#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + +/* ADC analog watchdog low threshold */ +#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + +/* ADC regular channel group length */ +#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) + +/* ADC inserted channel group length */ +#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) + +/* ADC resolution definitions */ +#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< ADC resolution */ +#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ +#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ +#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ +#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ + +/* ADC oversampling shift */ +#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) +#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ + +/* ADC oversampling ratio */ +#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) +#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ +#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ +#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ +#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ +#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ +#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ +#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ +#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ + +/* ADC triggered oversampling */ +#define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */ +#define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */ + +/* ADC channel group definitions */ +#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< ADC regular channel group */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted channel group */ +#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ + +/* ADC inserted channel definitions */ +#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC inserted channel 0 */ +#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC inserted channel 1 */ +#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC inserted channel 2 */ +#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC inserted channel 3 */ + +/* ADC channel definitions */ +#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ +#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ +#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ +#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ +#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ +#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ +#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ +#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ +#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ +#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ +#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ +#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ +#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ +#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ +#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ +#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ +#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ +#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ +#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ + +/* ADC interrupt definitions */ +#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ +#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ +#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ + +/* ADC interrupt flag */ +#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ + +/* function declarations */ +/* reset ADC */ +void adc_deinit(void); +/* enable ADC interface */ +void adc_enable(void); +/* disable ADC interface */ +void adc_disable(void); + +/* ADC calibration and reset calibration */ +void adc_calibration_enable(void); +/* enable DMA request */ +void adc_dma_mode_enable(void); +/* disable DMA request */ +void adc_dma_mode_disable(void); + +/* enable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_enable(void); +/* disable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_disable(void); +/* enable the Vbat channel */ +void adc_vbat_enable(void); +/* disable the Vbat channel */ +void adc_vbat_disable(void); + +/* configure ADC discontinuous mode */ +void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length); +/* enable or disable ADC special function */ +void adc_special_function_config(uint32_t function, ControlStatus newvalue); + +/* configure ADC data alignment */ +void adc_data_alignment_config(uint32_t data_alignment); +/* configure the length of regular channel group or inserted channel group */ +void adc_channel_length_config(uint8_t channel_group, uint32_t length); +/* configure ADC regular channel */ +void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time); +/* configure ADC inserted channel */ +void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time); +/* configure ADC inserted channel offset */ +void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset); +/* enable ADC external trigger */ +void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue); +/* configure ADC external trigger source */ +void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source); +/* enable ADC software trigger */ +void adc_software_trigger_enable(uint8_t channel_group); + +/* read ADC regular group data register */ +uint16_t adc_regular_data_read(void); +/* read ADC inserted group data register */ +uint16_t adc_inserted_data_read(uint8_t inserted_channel); + +/* configure ADC analog watchdog single channel */ +void adc_watchdog_single_channel_enable(uint8_t channel); +/* configure ADC analog watchdog group channel */ +void adc_watchdog_group_channel_enable(uint8_t channel_group); +/* disable ADC analog watchdog */ +void adc_watchdog_disable(void); +/* configure ADC analog watchdog threshold */ +void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold); + +/* configure ADC resolution */ +void adc_resolution_config(uint32_t resolution); +/* configure ADC oversample mode */ +void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio); +/* enable ADC oversample mode */ +void adc_oversample_mode_enable(void); +/* disable ADC oversample mode */ +void adc_oversample_mode_disable(void); + +/* get the ADC flag bits */ +FlagStatus adc_flag_get(uint32_t flag); +/* clear the ADC flag bits */ +void adc_flag_clear(uint32_t flag); +/* enable ADC interrupt */ +void adc_interrupt_enable(uint32_t interrupt); +/* disable ADC interrupt */ +void adc_interrupt_disable(uint32_t interrupt); +/* get the ADC interrupt bits */ +FlagStatus adc_interrupt_flag_get(uint32_t flag); +/* clear the ADC interrupt flag */ +void adc_interrupt_flag_clear(uint32_t flag); + +#endif /* GD32F3X0_ADC_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_cec.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_cec.h new file mode 100644 index 000000000..2c5f15dae --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_cec.h @@ -0,0 +1,252 @@ +/*! + \file gd32f3x0_cec.h + \brief definitions for the CEC + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifdef GD32F350 + +#ifndef GD32F3X0_CEC_H +#define GD32F3X0_CEC_H + +#include "gd32f3x0.h" + +/* CEC definitions */ +#define CEC CEC_BASE /*!< CEC base address */ + +/* registers definitions */ +#define CEC_CTL REG32(CEC + 0x00000000U) /*!< CEC control register */ +#define CEC_CFG REG32(CEC + 0x00000004U) /*!< CEC configuration register */ +#define CEC_TDATA REG32(CEC + 0x00000008U) /*!< CEC transmit data register */ +#define CEC_RDATA REG32(CEC + 0x0000000CU) /*!< CEC receive data register */ +#define CEC_INTF REG32(CEC + 0x00000010U) /*!< CEC interrupt flag Register */ +#define CEC_INTEN REG32(CEC + 0x00000014U) /*!< CEC interrupt enable register */ + +/* bits definitions */ +/* CEC_CTL */ +#define CEC_CTL_CECEN BIT(0) /*!< enable or disable HDMI-CEC controller bit */ +#define CEC_CTL_STAOM BIT(1) /*!< start of sending a message. */ +#define CEC_CTL_ENDOM BIT(2) /*!< ENDOM bit value in the next frame in Tx mode */ + +/* CEC_CFG */ +#define CEC_CFG_SFT BITS(0,2) /*!< signal free time */ +#define CEC_CFG_RTOL BIT(3) /*!< reception bit timing tolerance */ +#define CEC_CFG_BRES BIT(4) /*!< whether stop receive message when detected BRE */ +#define CEC_CFG_BREG BIT(5) /*!< generate Error-bit when detected BRE in singlecast */ +#define CEC_CFG_BPLEG BIT(6) /*!< generate Error-bit when detected BPLE in singlecast */ +#define CEC_CFG_BCNG BIT(7) /*!< do not generate Error-bit in broadcast message */ +#define CEC_CFG_SFTOPT BIT(8) /*!< the SFT start option bit */ +#define CEC_CFG_OAD BITS(16,30) /*!< own address */ +#define CEC_CFG_LMEN BIT(31) /*!< listen mode enable bit */ + +/* CEC_TDATA */ +#define CEC_TDATA_TDATA BITS(0,7) /*!< Tx data register */ + +/* CEC_RDATA */ +#define CEC_RDATA_RDATA BITS(0,7) /*!< Rx data register */ + +/* CEC_INTF */ +#define CEC_INTF_BR BIT(0) /*!< Rx-byte data received */ +#define CEC_INTF_REND BIT(1) /*!< end of reception */ +#define CEC_INTF_RO BIT(2) /*!< Rx overrun */ +#define CEC_INTF_BRE BIT(3) /*!< bit rising error */ +#define CEC_INTF_BPSE BIT(4) /*!< short bit period error */ +#define CEC_INTF_BPLE BIT(5) /*!< long bit period error */ +#define CEC_INTF_RAE BIT(6) /*!< Rx ACK error */ +#define CEC_INTF_ARBF BIT(7) /*!< arbitration fail */ +#define CEC_INTF_TBR BIT(8) /*!< Tx-byte data request */ +#define CEC_INTF_TEND BIT(9) /*!< transmission successfully end */ +#define CEC_INTF_TU BIT(10) /*!< Tx data buffer underrun */ +#define CEC_INTF_TERR BIT(11) /*!< Tx-error */ +#define CEC_INTF_TAERR BIT(12) /*!< Tx ACK error flag */ + +/* CEC_INTEN */ +#define CEC_INTEN_BRIE BIT(0) /*!< BR interrupt enable */ +#define CEC_INTEN_RENDIE BIT(1) /*!< REND interrupt enable */ +#define CEC_INTEN_ROIE BIT(2) /*!< RO interrupt enable */ +#define CEC_INTEN_BREIE BIT(3) /*!< BRE interrupt enable. */ +#define CEC_INTEN_BPSEIE BIT(4) /*!< BPSE interrupt enable */ +#define CEC_INTEN_BPLEIE BIT(5) /*!< BPLE interrupt enable. */ +#define CEC_INTEN_RAEIE BIT(6) /*!< RAE interrupt enable */ +#define CEC_INTEN_ARBFIE BIT(7) /*!< ARBF interrupt enable */ +#define CEC_INTEN_TBRIE BIT(8) /*!< TBR interrupt enable */ +#define CEC_INTEN_TENDIE BIT(9) /*!< TEND interrupt enable */ +#define CEC_INTEN_TUIE BIT(10) /*!< TU interrupt enable */ +#define CEC_INTEN_TERRIE BIT(11) /*!< TE interrupt enable */ +#define CEC_INTEN_TAERRIE BIT(12) /*!< TAE interrupt enable */ + +/* constants definitions */ +/* signal free time */ +#define CFG_SFT(regval) (BITS(0, 2) & ((regval) << 0U)) +#define CEC_SFT_PROTOCOL_PERIOD CFG_SFT(0) /*!< the signal free time will perform as HDMI-CEC protocol description */ +#define CEC_SFT_1POINT5_PERIOD CFG_SFT(1) /*!< 1.5 nominal data bit periods */ +#define CEC_SFT_2POINT5_PERIOD CFG_SFT(2) /*!< 2.5 nominal data bit periods */ +#define CEC_SFT_3POINT5_PERIOD CFG_SFT(3) /*!< 3.5 nominal data bit periods */ +#define CEC_SFT_4POINT5_PERIOD CFG_SFT(4) /*!< 4.5 nominal data bit periods */ +#define CEC_SFT_5POINT5_PERIOD CFG_SFT(5) /*!< 5.5 nominal data bit periods */ +#define CEC_SFT_6POINT5_PERIOD CFG_SFT(6) /*!< 6.5 nominal data bit periods */ +#define CEC_SFT_7POINT5_PERIOD CFG_SFT(7) /*!< 7.5 nominal data bit periods */ + +/* signal free time start option */ +#define CEC_SFT_START_STAOM ((uint32_t)0x00000000U) /*!< signal free time counter starts counting when STAOM is asserted */ +#define CEC_SFT_START_LAST CEC_CFG_SFTOPT /*!< signal free time counter starts automatically after transmission/reception end */ + +/* own address */ +#define CEC_OWN_ADDRESS_CLEAR ((uint32_t)0x00000000U) /*!< own address is cleared */ +#define CEC_OWN_ADDRESS0 BIT(16) /*!< own address is 0 */ +#define CEC_OWN_ADDRESS1 BIT(17) /*!< own address is 1 */ +#define CEC_OWN_ADDRESS2 BIT(18) /*!< own address is 2 */ +#define CEC_OWN_ADDRESS3 BIT(19) /*!< own address is 3 */ +#define CEC_OWN_ADDRESS4 BIT(20) /*!< own address is 4 */ +#define CEC_OWN_ADDRESS5 BIT(21) /*!< own address is 5 */ +#define CEC_OWN_ADDRESS6 BIT(22) /*!< own address is 6 */ +#define CEC_OWN_ADDRESS7 BIT(23) /*!< own address is 7 */ +#define CEC_OWN_ADDRESS8 BIT(24) /*!< own address is 8 */ +#define CEC_OWN_ADDRESS9 BIT(25) /*!< own address is 9 */ +#define CEC_OWN_ADDRESS10 BIT(26) /*!< own address is 10 */ +#define CEC_OWN_ADDRESS11 BIT(27) /*!< own address is 11 */ +#define CEC_OWN_ADDRESS12 BIT(28) /*!< own address is 12 */ +#define CEC_OWN_ADDRESS13 BIT(29) /*!< own address is 13 */ +#define CEC_OWN_ADDRESS14 BIT(30) /*!< own address is 14 */ + +/* error-bit generate */ +#define CEC_BROADCAST_ERROR_BIT_ON ((uint32_t)0x00000000U) /*!< generate Error-bit in broadcast */ +#define CEC_BROADCAST_ERROR_BIT_OFF CEC_CFG_BCNG /*!< do not generate Error-bit in broadcast */ +#define CEC_LONG_PERIOD_ERROR_BIT_OFF ((uint32_t)0x00000000U) /*!< generate Error-bit on long bit period error */ +#define CEC_LONG_PERIOD_ERROR_BIT_ON CEC_CFG_BPLEG /*!< do not generate Error-bit on long bit period error */ +#define CEC_RISING_PERIOD_ERROR_BIT_OFF ((uint32_t)0x00000000U) /*!< generate Error-bit on bit rising error */ +#define CEC_RISING_PERIOD_ERROR_BIT_ON CEC_CFG_BREG /*!< do not generate Error-bit on bit rising error */ + +/* whether stop receive message when detected bit rising error */ +#define CEC_STOP_RISING_ERROR_BIT_ON ((uint32_t)0x00000000U) /*!< stop reception when detected bit rising error */ +#define CEC_STOP_RISING_ERROR_BIT_OFF ((uint32_t)0x00000001U) /*!< do not stop reception when detected bit rising error */ + +/* flag bits */ +#define CEC_FLAG_BR CEC_INTF_BR /*!< RX-byte data received */ +#define CEC_FLAG_REND CEC_INTF_REND /*!< end of reception */ +#define CEC_FLAG_RO CEC_INTF_RO /*!< RX overrun */ +#define CEC_FLAG_BRE CEC_INTF_BRE /*!< bit rising error */ +#define CEC_FLAG_BPSE CEC_INTF_BPSE /*!< short bit period error */ +#define CEC_FLAG_BPLE CEC_INTF_BPLE /*!< long bit period error */ +#define CEC_FLAG_RAE CEC_INTF_RAE /*!< RX ACK error */ +#define CEC_FLAG_ARBF CEC_INTF_ARBF /*!< arbitration lost */ +#define CEC_FLAG_TBR CEC_INTF_TBR /*!< TX-byte data request */ +#define CEC_FLAG_TEND CEC_INTF_TEND /*!< transmission successfully end */ +#define CEC_FLAG_TU CEC_INTF_TU /*!< TX data buffer underrun */ +#define CEC_FLAG_TERR CEC_INTF_TERR /*!< TX-error */ +#define CEC_FLAG_TAERR CEC_INTF_TAERR /*!< TX ACK error flag */ + +/* interrupt flag bits */ +#define CEC_INT_FLAG_BR CEC_INTF_BR /*!< RX-byte data received */ +#define CEC_INT_FLAG_REND CEC_INTF_REND /*!< end of reception */ +#define CEC_INT_FLAG_RO CEC_INTF_RO /*!< RX overrun */ +#define CEC_INT_FLAG_BRE CEC_INTF_BRE /*!< bit rising error */ +#define CEC_INT_FLAG_BPSE CEC_INTF_BPSE /*!< short bit period error */ +#define CEC_INT_FLAG_BPLE CEC_INTF_BPLE /*!< long bit period error */ +#define CEC_INT_FLAG_RAE CEC_INTF_RAE /*!< RX ACK error */ +#define CEC_INT_FLAG_ARBF CEC_INTF_ARBF /*!< arbitration lost */ +#define CEC_INT_FLAG_TBR CEC_INTF_TBR /*!< TX-byte data request */ +#define CEC_INT_FLAG_TEND CEC_INTF_TEND /*!< transmission successfully end */ +#define CEC_INT_FLAG_TU CEC_INTF_TU /*!< TX data buffer underrun */ +#define CEC_INT_FLAG_TERR CEC_INTF_TERR /*!< TX-error */ +#define CEC_INT_FLAG_TAERR CEC_INTF_TAERR /*!< TX ACK error flag */ + +/* interrupt enable bits */ +#define CEC_INT_BR CEC_INTEN_BRIE /*!< RBR interrupt enable */ +#define CEC_INT_REND CEC_INTEN_RENDIE /*!< REND interrupt enable */ +#define CEC_INT_RO CEC_INTEN_ROIE /*!< RO interrupt enable */ +#define CEC_INT_BRE CEC_INTEN_BREIE /*!< RBRE interrupt enable. */ +#define CEC_INT_BPSE CEC_INTEN_BPSEIE /*!< RSBPE interrupt enable */ +#define CEC_INT_BPLE CEC_INTEN_BPLEIE /*!< RLBPE interrupt enable. */ +#define CEC_INT_RAE CEC_INTEN_RAEIE /*!< RAE interrupt enable */ +#define CEC_INT_ARBF CEC_INTEN_ARBFIE /*!< ALRLST interrupt enable */ +#define CEC_INT_TBR CEC_INTEN_TBRIE /*!< TBR interrupt enable */ +#define CEC_INT_TEND CEC_INTEN_TENDIE /*!< TEND interrupt enable */ +#define CEC_INT_TU CEC_INTEN_TUIE /*!< TU interrupt enable */ +#define CEC_INT_TERR CEC_INTEN_TERRIE /*!< TE interrupt enable */ +#define CEC_INT_TAERR CEC_INTEN_TAERRIE /*!< TAE interrupt enable */ + +/* function declarations */ +/* reset HDMI-CEC controller */ +void cec_deinit(void); +/* configure signal free time,the signal free time counter start option,own address */ +void cec_init(uint32_t sftmopt, uint32_t sft, uint32_t address); +/* configure generate Error-bit, whether stop receive message when detected bit rising error */ +void cec_error_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre, uint32_t rxbrestp); +/* enable HDMI-CEC controller */ +void cec_enable(void); +/* disable HDMI-CEC controller */ +void cec_disable(void); + +/* start CEC message transmission */ +void cec_transmission_start(void); +/* end CEC message transmission */ +void cec_transmission_end(void); +/* enable CEC listen mode */ +void cec_listen_mode_enable(void); +/* disable CEC listen mode */ +void cec_listen_mode_disable(void); +/* configure and clear own address */ +void cec_own_address_config(uint32_t address); +/* configure signal free time and the signal free time counter start option */ +void cec_sft_config(uint32_t sftmopt, uint32_t sft); +/* configure generate Error-bit when detected some abnormal situation or not */ +void cec_generate_errorbit_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre); +/* whether stop receive message when detected bit rising error */ +void cec_stop_receive_bre_config(uint32_t rxbrestp); +/* enable reception bit timing tolerance */ +void cec_reception_tolerance_enable(void); +/* disable reception bit timing tolerance */ +void cec_reception_tolerance_disable(void); +/* send a data by the CEC peripheral */ +void cec_data_send(uint8_t data); +/* receive a data by the CEC peripheral */ +uint8_t cec_data_receive(void); + +/* enable interrupt */ +void cec_interrupt_enable(uint32_t flag); +/* disable interrupt */ +void cec_interrupt_disable(uint32_t flag); +/* get CEC status */ +FlagStatus cec_flag_get(uint32_t flag); +/* clear CEC status */ +void cec_flag_clear(uint32_t flag); +/* get CEC int flag and status */ +FlagStatus cec_interrupt_flag_get(uint32_t flag); +/* clear CEC int flag and status */ +void cec_interrupt_flag_clear(uint32_t flag); + +#endif /* GD32F3X0_CEC_H */ + +#endif /* GD32F350 */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_cmp.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_cmp.h new file mode 100644 index 000000000..083dd4c2b --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_cmp.h @@ -0,0 +1,223 @@ +/*! + \file gd32f3x0_cmp.h + \brief definitions for the CMP + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2021-05-19, V2.1.1, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_CMP_H +#define GD32F3X0_CMP_H + +#include "gd32f3x0.h" + +/* CMP definitions */ +#define CMP CMP_BASE /*!< CMP base address */ + +/* registers definitions */ +#define CMP_CS REG32((CMP) + 0x00000000U) /*!< CMP control and status register */ + +/* CMP_CS bits definitions */ +#define CMP_CS_CMP0EN BIT(0) /*!< CMP0 enable */ +#define CMP_CS_CMP0SW BIT(1) /*!< CMP0 switch */ +#define CMP_CS_CMP0M BITS(2,3) /*!< CMP0 mode */ +#define CMP_CS_CMP0MSEL BITS(4,6) /*!< COMP0_M input selection */ +#define CMP_CS_CMP0OSEL BITS(8,10) /*!< CMP0 output selection */ +#define CMP_CS_CMP0PL BIT(11) /*!< polarity of CMP0 output */ +#define CMP_CS_CMP0HST BITS(12,13) /*!< CMP0 hysteresis */ +#define CMP_CS_CMP0O BIT(14) /*!< CMP0 output */ +#define CMP_CS_CMP0LK BIT(15) /*!< CMP0 lock */ +#define CMP_CS_CMP1EN BIT(16) /*!< CMP1 enable */ +#define CMP_CS_CMP1M BITS(18,19) /*!< CMP1 mode */ +#define CMP_CS_CMP1MSEL BITS(20,22) /*!< CMP1_M input selection */ +#define CMP_CS_WNDEN BIT(23) /*!< window mode enable */ +#define CMP_CS_CMP1OSEL BITS(24,26) /*!< CMP1 output selection */ +#define CMP_CS_CMP1PL BIT(27) /*!< polarity of CMP1 output */ +#define CMP_CS_CMP1HST BITS(28,29) /*!< CMP1 hysteresis */ +#define CMP_CS_CMP1O BIT(30) /*!< CMP1 output */ +#define CMP_CS_CMP1LK BIT(31) /*!< CMP1 lock */ + +/* consts definitions */ +/* operating mode */ +typedef enum { + CMP_HIGHSPEED = 0, /*!< high speed mode */ + CMP_MIDDLESPEED, /*!< medium speed mode */ + CMP_LOWSPEED, /*!< low speed mode */ + CMP_VERYLOWSPEED /*!< very-low speed mode */ +} operating_mode_enum; + +/* inverting input */ +typedef enum { + CMP_1_4VREFINT = 0, /*!< VREFINT /4 input */ + CMP_1_2VREFINT, /*!< VREFINT /2 input */ + CMP_3_4VREFINT, /*!< VREFINT *3/4 input */ + CMP_VREFINT, /*!< VREFINT input */ + CMP_DAC, /*!< PA4 (DAC) input */ + CMP_PA5, /*!< PA5 input */ + CMP_PA_0_2 /*!< PA0 or PA2 input */ +} inverting_input_enum; + +/* hysteresis */ +typedef enum { + CMP_HYSTERESIS_NO = 0, /*!< output no hysteresis */ + CMP_HYSTERESIS_LOW, /*!< output low hysteresis */ + CMP_HYSTERESIS_MIDDLE, /*!< output middle hysteresis */ + CMP_HYSTERESIS_HIGH /*!< output high hysteresis */ +} cmp_hysteresis_enum; + +/* output */ +typedef enum { + CMP_OUTPUT_NONE = 0, /*!< output no selection */ + CMP_OUTPUT_TIMER0BKIN, /*!< TIMER 0 break input */ + CMP_OUTPUT_TIMER0IC0, /*!< TIMER 0 channel0 input capture */ + CMP_OUTPUT_TIMER0OCPRECLR, /*!< TIMER 0 OCPRE_CLR input */ + CMP_OUTPUT_TIMER1IC3, /*!< TIMER 1 channel3 input capture */ + CMP_OUTPUT_TIMER1OCPRECLR, /*!< TIMER 1 OCPRE_CLR input */ + CMP_OUTPUT_TIMER2IC0, /*!< TIMER 2 channel0 input capture */ + CMP_OUTPUT_TIMER2OCPRECLR /*!< TIMER 2 OCPRE_CLR input */ +} cmp_output_enum; + +/* CMP0 mode */ +#define CS_CMP0M(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define CS_CMP0M_HIGHSPEED CS_CMP0M(0) /*!< CMP0 mode high speed */ +#define CS_CMP0M_MIDDLESPEED CS_CMP0M(1) /*!< CMP0 mode middle speed */ +#define CS_CMP0M_LOWSPEED CS_CMP0M(2) /*!< CMP0 mode low speed */ +#define CS_CMP0M_VERYLOWSPEED CS_CMP0M(3) /*!< CMP0 mode very low speed */ + +/* comparator 0 inverting input */ +#define CS_CMP0MSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) +#define CS_CMP0MSEL_1_4VREFINT CS_CMP0MSEL(0) /*!< CMP0 inverting input 1/4 Vrefint */ +#define CS_CMP0MSEL_1_2VREFINT CS_CMP0MSEL(1) /*!< CMP0 inverting input 1/2 Vrefint */ +#define CS_CMP0MSEL_3_4VREFINT CS_CMP0MSEL(2) /*!< CMP0 inverting input 3/4 Vrefint */ +#define CS_CMP0MSEL_VREFINT CS_CMP0MSEL(3) /*!< CMP0 inverting input Vrefint */ +#define CS_CMP0MSEL_DAC CS_CMP0MSEL(4) /*!< CMP0 inverting input DAC*/ +#define CS_CMP0MSEL_PA5 CS_CMP0MSEL(5) /*!< CMP0 inverting input PA5*/ +#define CS_CMP0MSEL_PA0 CS_CMP0MSEL(6) /*!< CMP0 inverting input PA0*/ + +/* CMP0 output */ +#define CS_CMP0OSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) +#define CS_CMP0OSEL_OUTPUT_NONE CS_CMP0OSEL(0) /*!< CMP0 output none */ +#define CS_CMP0OSEL_OUTPUT_TIMER0BKIN CS_CMP0OSEL(1) /*!< CMP0 output TIMER 0 break input */ +#define CS_CMP0OSEL_OUTPUT_TIMER0IC0 CS_CMP0OSEL(2) /*!< CMP0 output TIMER 0 channel 0 input capture */ +#define CS_CMP0OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP0OSEL(3) /*!< CMP0 output TIMER 0 ocpreclear input */ +#define CS_CMP0OSEL_OUTPUT_TIMER1IC3 CS_CMP0OSEL(4) /*!< CMP0 output TIMER 1 channel 3 input capture */ +#define CS_CMP0OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP0OSEL(5) /*!< CMP0 output TIMER 1 ocpreclear input */ +#define CS_CMP0OSEL_OUTPUT_TIMER2IC0 CS_CMP0OSEL(6) /*!< CMP0 output TIMER 2 channle 0 input capture */ +#define CS_CMP0OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP0OSEL(7) /*!< CMP0 output TIMER 2 ocpreclear input */ + +/* CMP0 hysteresis */ +#define CS_CMP0HST(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) +#define CS_CMP0HST_HYSTERESIS_NO CS_CMP0HST(0) /*!< CMP0 output no hysteresis */ +#define CS_CMP0HST_HYSTERESIS_LOW CS_CMP0HST(1) /*!< CMP0 output low hysteresis */ +#define CS_CMP0HST_HYSTERESIS_MIDDLE CS_CMP0HST(2) /*!< CMP0 output middle hysteresis */ +#define CS_CMP0HST_HYSTERESIS_HIGH CS_CMP0HST(3) /*!< CMP0 output high hysteresis */ + +/* CMP1 mode */ +#define CS_CMP1M(regval) (BITS(18,19) & ((uint32_t)(regval) << 18)) +#define CS_CMP1M_HIGHSPEED CS_CMP1M(0) /*!< CMP1 mode high speed */ +#define CS_CMP1M_MIDDLESPEED CS_CMP1M(1) /*!< CMP1 mode middle speed */ +#define CS_CMP1M_LOWSPEED CS_CMP1M(2) /*!< CMP1 mode low speed */ +#define CS_CMP1M_VERYLOWSPEED CS_CMP1M(3) /*!< CMP1 mode very low speed */ + +/* CMP1 inverting input */ +#define CS_CMP1MSEL(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) +#define CS_CMP1MSEL_1_4VREFINT CS_CMP1MSEL(0) /*!< CMP1 inverting input 1/4 Vrefint */ +#define CS_CMP1MSEL_1_2VREFINT CS_CMP1MSEL(1) /*!< CMP1 inverting input 1/2 Vrefint */ +#define CS_CMP1MSEL_3_4VREFINT CS_CMP1MSEL(2) /*!< CMP1 inverting input 3/4 Vrefint */ +#define CS_CMP1MSEL_VREFINT CS_CMP1MSEL(3) /*!< CMP1 inverting input Vrefint */ +#define CS_CMP1MSEL_DAC CS_CMP1MSEL(4) /*!< CMP1 inverting input DAC */ +#define CS_CMP1MSEL_PA5 CS_CMP1MSEL(5) /*!< CMP1 inverting input PA5 */ +#define CS_CMP1MSEL_PA2 CS_CMP1MSEL(6) /*!< CMP1 inverting input PA2 */ + +/* CMP1 output */ +#define CS_CMP1OSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) +#define CS_CMP1OSEL_OUTPUT_NONE CS_CMP1OSEL(0) /*!< CMP1 output none */ +#define CS_CMP1OSEL_OUTPUT_TIMER0BKIN CS_CMP1OSEL(1) /*!< CMP1 output TIMER 0 break input */ +#define CS_CMP1OSEL_OUTPUT_TIMER0IC0 CS_CMP1OSEL(2) /*!< CMP1 output TIMER 0 channel 0 input capture */ +#define CS_CMP1OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP1OSEL(3) /*!< CMP1 output TIMER 0 ocpreclear input */ +#define CS_CMP1OSEL_OUTPUT_TIMER1IC3 CS_CMP1OSEL(4) /*!< CMP1 output TIMER 1 channel 3 input capture */ +#define CS_CMP1OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP1OSEL(5) /*!< CMP1 output TIMER 1 ocpreclear input */ +#define CS_CMP1OSEL_OUTPUT_TIMER2IC0 CS_CMP1OSEL(6) /*!< CMP1 output TIMER 2 channle 0 input capture */ +#define CS_CMP1OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP1OSEL(7) /*!< CMP1 output TIMER 2 ocpreclear input */ + +/* CMP1 hysteresis */ +#define CS_CMP1HST(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) +#define CS_CMP1HST_HSTHYSTERESIS_NO CS_CMP1HST(0) /*!< CMP1 output no hysteresis */ +#define CS_CMP1HST_HYSTERESIS_LOW CS_CMP1HST(1) /*!< CMP1 output low hysteresis */ +#define CS_CMP1HST_HYSTERESIS_MIDDLE CS_CMP1HST(2) /*!< CMP1 output middle hysteresis */ +#define CS_CMP1HST_HYSTERESIS_HIGH CS_CMP1HST(3) /*!< CMP1 output high hysteresis */ + +/* comparator x definitions */ +#define CMP0 ((uint32_t)0x00000000U) /*!< comparator 0 */ +#define CMP1 ((uint32_t)0x00000010U) /*!< comparator 1 */ + +/* comparator output level */ +#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001U) /*!< comparator output high */ +#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000U) /*!< comparator output low */ + +/* output polarity of comparator */ +#define CMP_OUTPUT_POLARITY_INVERTED ((uint32_t)0x00000001U) /*!< output is inverted */ +#define CMP_OUTPUT_POLARITY_NOINVERTED ((uint32_t)0x00000000U) /*!< output is not inverted */ + +/* function declarations */ + +/* initialization functions */ +/* CMP deinit */ +void cmp_deinit(void); +/* CMP mode init */ +void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, + cmp_hysteresis_enum output_hysteresis); +/* CMP output init */ +void cmp_output_init(uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity); + +/* enable functions */ +/* enable CMP */ +void cmp_enable(uint32_t cmp_periph); +/* disable CMP */ +void cmp_disable(uint32_t cmp_periph); +/* enable CMP switch */ +void cmp_switch_enable(void); +/* disable CMP switch */ +void cmp_switch_disable(void); +/* enable the window mode */ +void cmp_window_enable(void); +/* disable the window mode */ +void cmp_window_disable(void); +/* lock the CMP */ +void cmp_lock_enable(uint32_t cmp_periph); + +/* output functions */ +/* get output level */ +uint32_t cmp_output_level_get(uint32_t cmp_periph); + +#endif /* GD32F3X0_CMP_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_crc.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_crc.h new file mode 100644 index 000000000..3d6324f60 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_crc.h @@ -0,0 +1,126 @@ +/*! + \file gd32f3x0_crc.h + \brief definitions for the CRC + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_CRC_H +#define GD32F3X0_CRC_H + +#include "gd32f3x0.h" + +/* CRC definitions */ +#define CRC CRC_BASE + +/* registers definitions */ +#define CRC_DATA REG32(CRC + 0x00000000U) /*!< CRC data register */ +#define CRC_FDATA REG32(CRC + 0x00000004U) /*!< CRC free data register */ +#define CRC_CTL REG32(CRC + 0x00000008U) /*!< CRC control register */ +#define CRC_IDATA REG32(CRC + 0x00000010U) /*!< CRC initialization data register */ +#define CRC_POLY REG32(CRC + 0x00000014U) /*!< CRC polynomial register */ + +/* bits definitions */ +/* CRC_DATA */ +#define CRC_DATA_DATA BITS(0,31) /*!< CRC data bits */ + +/* CRC_FDATA */ +#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ + +/* CRC_CTL */ +#define CRC_CTL_RST BIT(0) /*!< CRC reset bit */ +#define CRC_CTL_PS BITS(3,4) /*!< size of polynomial function bits */ +#define CRC_CTL_REV_I BITS(5,6) /*!< input data reverse function bits */ +#define CRC_CTL_REV_O BIT(7) /*!< output data reverse function bit */ + +/* CRC_INIT */ +#define CRC_IDATA_IDATA BITS(0,31) /*!< CRC initialization data bits */ + +/* CRC_POLY */ +#define CRC_POLY_POLY BITS(0,31) /*!< CRC polynomial value bits */ + +/* constants definitions */ +/* size of polynomial function */ +#define CTL_PS(regval) (BITS(3, 4) & ((regval) << 3)) +#define CRC_CTL_PS_32 CTL_PS(0) /*!< 32-bit polynomial for CRC calculation */ +#define CRC_CTL_PS_16 CTL_PS(1) /*!< 16-bit polynomial for CRC calculation */ +#define CRC_CTL_PS_8 CTL_PS(2) /*!< 8-bit polynomial for CRC calculation */ +#define CRC_CTL_PS_7 CTL_PS(3) /*!< 7-bit polynomial for CRC calculation */ + +/* input data reverse function */ +#define CTL_REV_I(regval) (BITS(5, 6) & ((regval) << 5)) +#define CRC_INPUT_DATA_NOT CTL_REV_I(0) /*!< input data not reverse */ +#define CRC_INPUT_DATA_BYTE CTL_REV_I(1) /*!< input data reversed by byte type */ +#define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2) /*!< input data reversed by half-word type */ +#define CRC_INPUT_DATA_WORD CTL_REV_I(3) /*!< input data reversed by word type */ + +/* input data format */ +#define INPUT_FORMAT_WORD 0U /*!< input data in word format */ +#define INPUT_FORMAT_HALFWORD 1U /*!< input data in half-word format */ +#define INPUT_FORMAT_BYTE 2U /*!< input data in byte format */ + +/* function declarations */ +/* deinit CRC calculation unit */ +void crc_deinit(void); + +/* enable the reverse operation of output data */ +void crc_reverse_output_data_enable(void); +/* disable the reverse operation of output data */ +void crc_reverse_output_data_disable(void); + +/* reset data register to the value of initializaiton data register */ +void crc_data_register_reset(void); +/* read the data register */ +uint32_t crc_data_register_read(void); + +/* read the free data register */ +uint8_t crc_free_data_register_read(void); +/* write the free data register */ +void crc_free_data_register_write(uint8_t free_data); + +/* write the initial value register */ +void crc_init_data_register_write(uint32_t init_data); +/* configure the CRC input data function */ +void crc_input_data_reverse_config(uint32_t data_reverse); + +/* configure the CRC size of polynomial function */ +void crc_polynomial_size_set(uint32_t poly_size); +/* configure the CRC polynomial value function */ +void crc_polynomial_set(uint32_t poly); + +/* CRC calculate single data */ +uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format); +/* CRC calculate a data array */ +uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format); + +#endif /* GD32F3X0_CRC_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_ctc.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_ctc.h new file mode 100644 index 000000000..364ac5923 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_ctc.h @@ -0,0 +1,193 @@ +/*! + \file gd32f3x0_ctc.h + \brief definitions for the CTC + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_CTC_H +#define GD32F3X0_CTC_H + +#include "gd32f3x0.h" + +/* CTC definitions */ +#define CTC CTC_BASE + +/* registers definitions */ +#define CTC_CTL0 REG32(CTC + 0x00000000U) /*!< CTC control register 0 */ +#define CTC_CTL1 REG32(CTC + 0x00000004U) /*!< CTC control register 1 */ +#define CTC_STAT REG32(CTC + 0x00000008U) /*!< CTC status register */ +#define CTC_INTC REG32(CTC + 0x0000000CU) /*!< CTC interrupt clear register */ + +/* bits definitions */ +/* CTC_CTL0 */ +#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ +#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */ +#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */ +#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */ +#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */ +#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */ +#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */ +#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */ + +/* CTC_CTL1 */ +#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */ +#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ +#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ +#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ +#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ + +/* CTC_STAT */ +#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */ +#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */ +#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */ +#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */ +#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */ +#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */ +#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */ +#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */ +#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ + +/* CTC_INTC */ +#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */ +#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */ +#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */ +#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */ + +/* constants definitions */ +#define CTL0_TRIMVALUE(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) +#define CTL1_CKLIM(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) +#define GET_STAT_REFCAP(regval) GET_BITS((regval),16,31) +#define GET_CTL0_TRIMVALUE(regval) GET_BITS((regval),8,13) + +/* hardware automatically trim mode definitions */ +#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/ +#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/ + +/* reference signal source polarity definitions */ +#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/ +#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ + +/* reference signal source selection definitions */ +#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) +#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ +#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */ +#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBFSSOF selected */ + +/* reference signal source prescaler definitions */ +#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) +#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */ +#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */ +#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */ +#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */ +#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */ +#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */ +#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */ +#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */ + +/* CTC interrupt enable definitions */ +#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */ +#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */ +#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */ +#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */ + +/* CTC interrupt source definitions */ +#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */ +#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */ +#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */ +#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */ +#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ +#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ +#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */ + +/* CTC flag definitions */ +#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */ +#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */ +#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */ +#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */ +#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ +#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ +#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */ + +/* function declarations */ +/* initialization functions */ +/* reset ctc clock trim controller */ +void ctc_deinit(void); +/* configure reference signal source polarity */ +void ctc_refsource_polarity_config(uint32_t polarity); +/* select reference signal source */ +void ctc_refsource_signal_select(uint32_t refs); +/* configure reference signal source prescaler */ +void ctc_refsource_prescaler_config(uint32_t prescaler); +/* configure clock trim base limit value */ +void ctc_clock_limit_value_config(uint8_t limit_value); +/* configure CTC counter reload value */ +void ctc_counter_reload_value_config(uint16_t reload_value); +/* enable CTC trim counter */ +void ctc_counter_enable(void); +/* disable CTC trim counter */ +void ctc_counter_disable(void); + +/* function configuration */ +/* configure the IRC48M trim value */ +void ctc_irc48m_trim_value_config(uint8_t trim_value); +/* generate software reference source sync pulse */ +void ctc_software_refsource_pulse_generate(void); +/* configure hardware automatically trim mode */ +void ctc_hardware_trim_mode_config(uint32_t hardmode); + +/* reading functions */ +/* read CTC counter capture value when reference sync pulse occurred */ +uint16_t ctc_counter_capture_value_read(void); +/* read CTC trim counter direction when reference sync pulse occurred */ +FlagStatus ctc_counter_direction_read(void); +/* read CTC counter reload value */ +uint16_t ctc_counter_reload_value_read(void); +/* read the IRC48M trim value */ +uint8_t ctc_irc48m_trim_value_read(void); + +/* interrupt & flag functions */ +/* enable the CTC interrupt */ +void ctc_interrupt_enable(uint32_t interrupt); +/* disable the CTC interrupt */ +void ctc_interrupt_disable(uint32_t interrupt); +/* get CTC flag */ +FlagStatus ctc_flag_get(uint32_t flag); +/* clear CTC flag */ +void ctc_flag_clear(uint32_t flag); +/* get CTC interrupt flag */ +FlagStatus ctc_interrupt_flag_get(uint32_t interrupt); +/* clear CTC interrupt flag */ +void ctc_interrupt_flag_clear(uint32_t interrupt); + +#endif /* GD32F3X0_CTC_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_dac.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_dac.h new file mode 100644 index 000000000..62027e1f6 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_dac.h @@ -0,0 +1,205 @@ +/*! + \file gd32f3x0_dac.h + \brief definitions for the DAC + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifdef GD32F350 +#ifndef GD32F3X0_DAC_H +#define GD32F3X0_DAC_H + +#include "gd32f3x0.h" + +/* DAC definitions */ +#define DAC DAC_BASE /*!< DAC base address */ + +/* registers definitions */ +#define DAC_CTL REG32(DAC + (0x00000000U)) /*!< DAC control register */ +#define DAC_SWT REG32(DAC + (0x00000004U)) /*!< DAC software trigger register */ +#define DAC_R12DH REG32(DAC + (0x00000008U)) /*!< DAC 12-bit right-aligned data holding register */ +#define DAC_L12DH REG32(DAC + (0x0000000CU)) /*!< DAC 12-bit left-aligned data holding register */ +#define DAC_R8DH REG32(DAC + (0x00000010U)) /*!< DAC 8-bit right-aligned data holding register */ +#define DAC_DO REG32(DAC + (0x0000002CU)) /*!< DAC output data register */ +#define DAC_STAT REG32(DAC + (0x00000034U)) /*!< DAC status register */ + +/* bits definitions */ +/* DAC_CTL */ +#define DAC_CTL_DEN BIT(0) /*!< DAC enable/disable bit */ +#define DAC_CTL_DBOFF BIT(1) /*!< DAC output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN BIT(2) /*!< DAC trigger enable/disable bit */ +#define DAC_CTL_DTSEL BITS(3,5) /*!< DAC trigger source selection enable/disable bits */ +#define DAC_CTL_DWM BITS(6,7) /*!< DAC noise wave mode */ +#define DAC_CTL_DWBW BITS(8,11) /*!< DAC noise wave bit width */ +#define DAC_CTL_DDMAEN BIT(12) /*!< DAC DMA enable/disable bit */ +#define DAC_CTL_DDUDRIE BIT(13) /*!< DAC DMA underrun interrupt enable/disable bit */ + +/* DAC_SWT */ +#define DAC_SWT_SWTR BIT(0) /*!< DAC software trigger bit,cleared by hardware */ + +/* DAC_R12DH */ +#define DAC_R12DH_DAC_DH BITS(0,11) /*!< DAC 12-bit right-aligned data bits */ + +/* DAC_L12DH */ +#define DAC_L12DH_DAC_DH BITS(4,15) /*!< DAC 12-bit left-aligned data bits */ + +/* DAC_R8DH */ +#define DAC_R8DH_DAC_DH BITS(0,7) /*!< DAC 8-bit right-aligned data bits */ + +/* DAC_DO */ +#define DAC_DO_DAC_DO BITS(0,11) /*!< DAC 12-bit output data bits */ + +/* DAC_STAT */ +#define DAC_STAT_DDUDR BIT(13) /*!< DAC DMA underrun flag */ + +/* constants definitions */ +/* DAC trigger source */ +#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ +#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ +#define DAC_TRIGGER_T14_TRGO CTL_DTSEL(3) /*!< TIMER14 TRGO */ +#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ +#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ +#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ + +/* DAC noise wave mode */ +#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ +#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ +#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ + +/* DAC noise wave bit width */ +#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ +#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ +#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ +#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ +#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ +#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ +#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ +#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ +#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ +#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ +#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ +#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ + +/* unmask LFSR bits in DAC LFSR noise mode */ +#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ +#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ +#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ +#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ +#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ +#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ +#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ +#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ +#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ +#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ +#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ +#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ + +/* triangle amplitude in DAC triangle noise mode */ +#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ +#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ +#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ +#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ +#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ +#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ +#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ +#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ +#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ +#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ +#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ +#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ + +/* DAC data alignment */ +#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ +#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ +#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ + +/* function declarations */ +/* deinitialize DAC */ +void dac_deinit(void); + +/* enable DAC */ +void dac_enable(void); +/* disable DAC */ +void dac_disable(void); +/* enable DAC DMA */ +void dac_dma_enable(void); +/* disable DAC DMA */ +void dac_dma_disable(void); +/* enable DAC output buffer */ +void dac_output_buffer_enable(void); +/* disable DAC output buffer */ +void dac_output_buffer_disable(void); +/* enable DAC trigger */ +void dac_trigger_enable(void); +/* disable DAC trigger */ +void dac_trigger_disable(void); +/* enable DAC software trigger */ +void dac_software_trigger_enable(void); +/* disable DAC software trigger */ +void dac_software_trigger_disable(void); + +/* configure DAC trigger source */ +void dac_trigger_source_config(uint32_t triggersource); +/* configure DAC wave mode */ +void dac_wave_mode_config(uint32_t wave_mode); +/* configure DAC wave bit width */ +void dac_wave_bit_width_config(uint32_t bit_width); +/* configure DAC LFSR noise mode */ +void dac_lfsr_noise_config(uint32_t unmask_bits); +/* configure DAC triangle noise mode */ +void dac_triangle_noise_config(uint32_t amplitude); +/* get the last data output value */ +uint16_t dac_output_value_get(void); +/* set DAC data holding register value */ +void dac_data_set(uint32_t dac_align, uint16_t data); + +/* get the specified DAC flag(DAC DMA underrun flag) */ +FlagStatus dac_flag_get(void); +/* clear the specified DAC flag(DAC DMA underrun flag) */ +void dac_flag_clear(void); +/* enable DAC interrupt(DAC DMA underrun interrupt) */ +void dac_interrupt_enable(void); +/* disable DAC interrupt(DAC DMA underrun interrupt) */ +void dac_interrupt_disable(void); +/* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */ +FlagStatus dac_interrupt_flag_get(void); +/* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */ +void dac_interrupt_flag_clear(void); + +#endif /* GD32F3X0_DAC_H */ + +#endif /* GD32F350 */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_dbg.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_dbg.h new file mode 100644 index 000000000..99a126865 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_dbg.h @@ -0,0 +1,132 @@ +/*! + \file gd32f3x0_dbg.h + \brief definitions for the DBG + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_DBG_H +#define GD32F3X0_DBG_H + +#include "gd32f3x0.h" + +/* DBG definitions */ +#define DBG DBG_BASE + +/* registers definitions */ +#define DBG_ID REG32(DBG + 0x00000000U) /*!< DBG_ID code register */ +#define DBG_CTL0 REG32(DBG + 0x00000004U) /*!< DBG control register 0 */ +#define DBG_CTL1 REG32(DBG + 0x00000008U) /*!< DBG control register 1 */ + +/* bits definitions */ +/* DBG_ID */ +#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ + +/* DBG_CTL0 */ +#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ +#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ +#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ +#define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ +#define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ +#define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ +#if (defined(GD32F350) || defined(GD32F330)) +#define DBG_CTL0_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ +#endif /* GD32F350 and GD32F330 */ +#define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ +#define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ +#define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ +#ifdef GD32F350 +#define DBG_CTL0_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */ +#endif /* GD32F350 */ +#define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */ + +/* DBG_CTL1 */ +#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */ +#define DBG_CTL1_TIMER14_HOLD BIT(16) /*!< hold TIMER14 counter when core is halted */ +#define DBG_CTL1_TIMER15_HOLD BIT(17) /*!< hold TIMER15 counter when core is halted */ +#define DBG_CTL1_TIMER16_HOLD BIT(18) /*!< hold TIMER16 counter when core is halted */ + +/* constants definitions */ +#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */ +#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ +#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ + +/* define the peripheral debug hold bit position and its register index offset */ +#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) +#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) +#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) + +/* register index */ +typedef enum { + DBG_IDX_CTL0 = 0x04U, /*!< DBG control register 0 offset */ + DBG_IDX_CTL1 = 0x08U, /*!< DBG control register 1 offset */ +} dbg_reg_idx; + +/* peripherals hold bit */ +typedef enum { + DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), /*!< debug FWDGT kept when core is halted */ + DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), /*!< debug WWDGT kept when core is halted */ + DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U), /*!< hold TIMER0 counter when core is halted */ +#if (defined(GD32F350) || defined(GD32F330)) + DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 11U), /*!< hold TIMER1 counter when core is halted */ +#endif /* GD32F350 and GD32F330 */ + DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), /*!< hold TIMER2 counter when core is halted */ +#ifdef GD32F350 + DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U), /*!< hold TIMER5 counter when core is halted */ +#endif /* GD32F350 */ + DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U), /*!< hold TIMER13 counter when core is halted */ + DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U), /*!< hold TIMER14 counter when core is halted */ + DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U), /*!< hold TIMER15 counter when core is halted */ + DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U), /*!< hold TIMER16 counter when core is halted */ + DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), /*!< hold I2C0 smbus when core is halted */ + DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), /*!< hold I2C1 smbus when core is halted */ + DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< hold RTC calendar and wakeup counter when core is halted */ +} dbg_periph_enum; + +/* function declarations */ +/* deinitialize the DBG */ +void dbg_deinit(void); +/* read DBG_ID code register */ +uint32_t dbg_id_get(void); + +/* enable low power behavior when the MCU is in debug mode */ +void dbg_low_power_enable(uint32_t dbg_low_power); +/* disable low power behavior when the MCU is in debug mode */ +void dbg_low_power_disable(uint32_t dbg_low_power); + +/* enable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_enable(dbg_periph_enum dbg_periph); +/* disable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_disable(dbg_periph_enum dbg_periph); + +#endif /* GD32F3X0_DBG_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_dma.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_dma.h new file mode 100644 index 000000000..57ab6f82c --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_dma.h @@ -0,0 +1,273 @@ +/*! + \file gd32f3x0_dma.h + \brief definitions for the DMA + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_DMA_H +#define GD32F3X0_DMA_H + +#include "gd32f3x0.h" + +/* DMA definitions */ +#define DMA DMA_BASE /*!< DMA base address */ + +/* registers definitions */ +#define DMA_INTF REG32(DMA + 0x00000000U) /*!< DMA interrupt flag register */ +#define DMA_INTC REG32(DMA + 0x00000004U) /*!< DMA interrupt flag clear register */ +#define DMA_CH0CTL REG32(DMA + 0x00000008U) /*!< DMA channel 0 control register */ +#define DMA_CH0CNT REG32(DMA + 0x0000000CU) /*!< DMA channel 0 counter register */ +#define DMA_CH0PADDR REG32(DMA + 0x00000010U) /*!< DMA channel 0 peripheral base address register */ +#define DMA_CH0MADDR REG32(DMA + 0x00000014U) /*!< DMA channel 0 memory base address register */ +#define DMA_CH1CTL REG32(DMA + 0x0000001CU) /*!< DMA channel 1 control register */ +#define DMA_CH1CNT REG32(DMA + 0x00000020U) /*!< DMA channel 1 counter register */ +#define DMA_CH1PADDR REG32(DMA + 0x00000024U) /*!< DMA channel 1 peripheral base address register */ +#define DMA_CH1MADDR REG32(DMA + 0x00000028U) /*!< DMA channel 1 memory base address register */ +#define DMA_CH2CTL REG32(DMA + 0x00000030U) /*!< DMA channel 2 control register */ +#define DMA_CH2CNT REG32(DMA + 0x00000034U) /*!< DMA channel 2 counter register */ +#define DMA_CH2PADDR REG32(DMA + 0x00000038U) /*!< DMA channel 2 peripheral base address register */ +#define DMA_CH2MADDR REG32(DMA + 0x0000003CU) /*!< DMA channel 2 memory base address register */ +#define DMA_CH3CTL REG32(DMA + 0x00000044U) /*!< DMA channel 3 control register */ +#define DMA_CH3CNT REG32(DMA + 0x00000048U) /*!< DMA channel 3 counter register */ +#define DMA_CH3PADDR REG32(DMA + 0x0000004CU) /*!< DMA channel 3 peripheral base address register */ +#define DMA_CH3MADDR REG32(DMA + 0x00000050U) /*!< DMA channel 3 memory base address register */ +#define DMA_CH4CTL REG32(DMA + 0x00000058U) /*!< DMA channel 4 control register */ +#define DMA_CH4CNT REG32(DMA + 0x0000005CU) /*!< DMA channel 4 counter register */ +#define DMA_CH4PADDR REG32(DMA + 0x00000060U) /*!< DMA channel 4 peripheral base address register */ +#define DMA_CH4MADDR REG32(DMA + 0x00000064U) /*!< DMA channel 4 memory base address register */ +#define DMA_CH5CTL REG32(DMA + 0x0000006CU) /*!< DMA channel 5 control register */ +#define DMA_CH5CNT REG32(DMA + 0x00000070U) /*!< DMA channel 5 counter register */ +#define DMA_CH5PADDR REG32(DMA + 0x00000074U) /*!< DMA channel 5 peripheral base address register */ +#define DMA_CH5MADDR REG32(DMA + 0x00000078U) /*!< DMA channel 5 memory base address register */ +#define DMA_CH6CTL REG32(DMA + 0x00000080U) /*!< DMA channel 6 control register */ +#define DMA_CH6CNT REG32(DMA + 0x00000084U) /*!< DMA channel 6 counter register */ +#define DMA_CH6PADDR REG32(DMA + 0x00000088U) /*!< DMA channel 6 peripheral base address register */ +#define DMA_CH6MADDR REG32(DMA + 0x0000008CU) /*!< DMA channel 6 memory base address register */ + +/* bits definitions */ +/* DMA_INTF */ +#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ +#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ +#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ +#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ + +/* DMA_INTC */ +#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ +#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ +#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ +#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ + +/* DMA_CHxCTL,x=0..6 */ +#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */ +#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel x transfer complete interrupt */ +#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel x transfer half complete interrupt */ +#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel x error interrupt */ +#define DMA_CHXCTL_DIR BIT(4) /*!< direction of the data transfer on the channel */ +#define DMA_CHXCTL_CMEN BIT(5) /*!< circulation mode */ +#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ +#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ +#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data size of peripheral */ +#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data size of memory */ +#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level of channelx */ +#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ + +/* DMA_CHxCNT,x=0..6 */ +#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ + +/* DMA_CHxPADDR,x=0..6 */ +#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ + +/* DMA_CHxMADDR,x=0..6 */ +#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ + +/* constants definitions */ +/* DMA channel select */ +typedef enum { + DMA_CH0 = 0, /*!< DMA Channel0 */ + DMA_CH1, /*!< DMA Channel1 */ + DMA_CH2, /*!< DMA Channel2 */ + DMA_CH3, /*!< DMA Channel3 */ + DMA_CH4, /*!< DMA Channel4 */ + DMA_CH5, /*!< DMA Channel5 */ + DMA_CH6 /*!< DMA Channel6 */ +} dma_channel_enum; + +/* DMA initialize struct */ +typedef struct { + uint32_t periph_addr; /*!< peripheral base address */ + uint32_t periph_width; /*!< transfer data size of peripheral */ + uint8_t periph_inc; /*!< peripheral increasing mode */ + uint32_t memory_addr; /*!< memory base address */ + uint32_t memory_width; /*!< transfer data size of memory */ + uint8_t memory_inc; /*!< memory increasing mode */ + uint8_t direction; /*!< channel data transfer direction */ + uint32_t number; /*!< channel transfer number */ + uint32_t priority; /*!< channel priority level */ +} dma_parameter_struct; + +/* DMA reset value */ +#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ +#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ +#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ +#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ +#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ + DMA_INTF_HTFIF | DMA_INTF_ERRIF) + +#define DMA_FLAG_ADD(flag,shift) ((flag) << ((uint32_t)(shift) * 4U)) /*!< DMA channel flag shift */ + +/* DMA_CHCTL base address */ +#define DMA_CHXCTL_BASE (DMA + (uint32_t)0x00000008U) /*!< the base address of DMA channel CHXCTL register */ +#define DMA_CHXCNT_BASE (DMA + (uint32_t)0x0000000CU) /*!< the base address of DMA channel CHXCNT register */ +#define DMA_CHXPADDR_BASE (DMA + (uint32_t)0x00000010U) /*!< the base address of DMA channel CHXPADDR register */ +#define DMA_CHXMADDR_BASE (DMA + (uint32_t)0x00000014U) /*!< the base address of DMA channel CHXMADDR register */ + +/* DMA channel shift bit */ +#define DMA_CHCTL(channel) REG32(DMA_CHXCTL_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ +#define DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ +#define DMA_CHPADDR(channel) REG32(DMA_CHXPADDR_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ +#define DMA_CHMADDR(channel) REG32(DMA_CHXMADDR_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ + +/* DMA_INTF register */ +/* interrupt flag bits */ +#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ + +/* flag bits */ +#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ +#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ +#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ + +/* DMA_CHxCTL register */ +/* interrupt enable bits */ +#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ +#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ +#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ + +/* transfer direction */ +#define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U) /*!< read from peripheral and write to memory */ +#define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U) /*!< read from memory and write to peripheral */ + +/* peripheral increasing mode */ +#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is fixed address mode */ +#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is increasing address mode */ + +/* memory increasing mode */ +#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of memory is fixed address mode */ +#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of memory is increasing address mode */ + +/* transfer data size of peripheral */ +#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */ +#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data size of peripheral is 8-bit */ +#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data size of peripheral is 16-bit */ +#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data size of peripheral is 32-bit */ + +/* transfer data size of memory */ +#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */ +#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data size of memory is 8-bit */ +#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data size of memory is 16-bit */ +#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data size of memory is 32-bit */ + +/* channel priority level */ +#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ +#define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */ +#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */ +#define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */ +#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */ + +/* DMA_CHxCNT register */ +/* transfer counter */ +#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT + +/* function declarations */ +/* deinitialize DMA a channel registers */ +void dma_deinit(dma_channel_enum channelx); +/* initialize the parameters of DMA struct with the default values */ +void dma_struct_para_init(dma_parameter_struct *init_struct); +/* initialize DMA channel */ +void dma_init(dma_channel_enum channelx, dma_parameter_struct *init_struct); +/* enable DMA circulation mode */ +void dma_circulation_enable(dma_channel_enum channelx); +/* disable DMA circulation mode */ +void dma_circulation_disable(dma_channel_enum channelx); +/* enable memory to memory mode */ +void dma_memory_to_memory_enable(dma_channel_enum channelx); +/* disable memory to memory mode */ +void dma_memory_to_memory_disable(dma_channel_enum channelx); +/* enable DMA channel */ +void dma_channel_enable(dma_channel_enum channelx); +/* disable DMA channel */ +void dma_channel_disable(dma_channel_enum channelx); + +/* set DMA peripheral base address */ +void dma_periph_address_config(dma_channel_enum channelx, uint32_t address); +/* set DMA memory base address */ +void dma_memory_address_config(dma_channel_enum channelx, uint32_t address); +/* set the number of remaining data to be transferred by the DMA */ +void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number); +/* get the number of remaining data to be transferred by the DMA */ +uint32_t dma_transfer_number_get(dma_channel_enum channelx); +/* configure priority level of DMA channel */ +void dma_priority_config(dma_channel_enum channelx, uint32_t priority); +/* configure transfer data size of memory */ +void dma_memory_width_config(dma_channel_enum channelx, uint32_t mwidth); +/* configure transfer data size of peripheral */ +void dma_periph_width_config(dma_channel_enum channelx, uint32_t pwidth); +/* enable next address increasement algorithm of memory */ +void dma_memory_increase_enable(dma_channel_enum channelx); +/* disable next address increasement algorithm of memory */ +void dma_memory_increase_disable(dma_channel_enum channelx); +/* enable next address increasement algorithm of peripheral */ +void dma_periph_increase_enable(dma_channel_enum channelx); +/* disable next address increasement algorithm of peripheral */ +void dma_periph_increase_disable(dma_channel_enum channelx); +/* configure the direction of data transfer on the channel */ +void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction); + +/* check DMA flag is set or not */ +FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag); +/* clear DMA a channel flag */ +void dma_flag_clear(dma_channel_enum channelx, uint32_t flag); +/* enable DMA interrupt */ +void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source); +/* disable DMA interrupt */ +void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source); +/* check DMA flag and interrupt enable bit is set or not */ +FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag); +/* clear DMA a channel flag */ +void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag); + +#endif /* GD32F3X0_DMA_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_exti.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_exti.h new file mode 100644 index 000000000..b236c3227 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_exti.h @@ -0,0 +1,285 @@ +/*! + \file gd32f3x0_exti.h + \brief definitions for the EXTI + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_EXTI_H +#define GD32F3X0_EXTI_H + +#include "gd32f3x0.h" + +/* EXTI definitions */ +#define EXTI EXTI_BASE /*!< EXTI base address */ + +/* registers definitions */ +#define EXTI_INTEN REG32(EXTI + 0x00000000U) /*!< interrupt enable register */ +#define EXTI_EVEN REG32(EXTI + 0x00000004U) /*!< event enable register */ +#define EXTI_RTEN REG32(EXTI + 0x00000008U) /*!< rising edge trigger enable register */ +#define EXTI_FTEN REG32(EXTI + 0x0000000CU) /*!< falling trigger enable register */ +#define EXTI_SWIEV REG32(EXTI + 0x00000010U) /*!< software interrupt event register */ +#define EXTI_PD REG32(EXTI + 0x00000014U) /*!< pending register */ + +/* bits definitions */ +/* EXTI_INTEN */ +#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ +#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ +#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ +#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ +#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ +#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ +#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ +#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ +#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ +#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ +#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ +#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ +#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ +#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ +#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ +#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ +#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ +#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ +#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ +#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */ +#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */ +#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */ +#define EXTI_INTEN_INTEN22 BIT(22) /*!< interrupt from line 22 */ +#define EXTI_INTEN_INTEN23 BIT(23) /*!< interrupt from line 23 */ +#define EXTI_INTEN_INTEN24 BIT(24) /*!< interrupt from line 24 */ +#define EXTI_INTEN_INTEN25 BIT(25) /*!< interrupt from line 25 */ +#define EXTI_INTEN_INTEN26 BIT(26) /*!< interrupt from line 26 */ +#define EXTI_INTEN_INTEN27 BIT(27) /*!< interrupt from line 27 */ + +/* EXTI_EVEN */ +#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ +#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ +#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ +#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ +#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ +#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ +#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ +#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ +#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ +#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ +#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ +#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ +#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ +#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ +#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ +#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ +#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ +#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ +#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ +#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */ +#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */ +#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */ +#define EXTI_EVEN_EVEN22 BIT(22) /*!< event from line 22 */ +#define EXTI_EVEN_EVEN23 BIT(23) /*!< event from line 23 */ +#define EXTI_EVEN_EVEN24 BIT(24) /*!< event from line 24 */ +#define EXTI_EVEN_EVEN25 BIT(25) /*!< event from line 25 */ +#define EXTI_EVEN_EVEN26 BIT(26) /*!< event from line 26 */ +#define EXTI_EVEN_EVEN27 BIT(27) /*!< event from line 27 */ + +/* EXTI_RTEN */ +#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ +#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ +#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ +#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ +#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ +#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ +#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ +#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ +#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ +#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ +#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ +#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ +#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ +#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ +#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ +#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ +#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ +#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ +#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ +#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ +#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */ +#define EXTI_RTEN_RTEN22 BIT(22) /*!< rising edge from line 22 */ + +/* EXTI_FTEN */ +#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ +#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ +#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ +#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ +#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ +#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ +#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ +#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ +#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ +#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ +#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ +#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ +#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ +#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ +#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ +#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ +#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ +#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ +#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ +#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ +#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */ +#define EXTI_FTEN_FTEN22 BIT(22) /*!< falling edge from line 22 */ + +/* EXTI_SWIEV */ +#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ +#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ +#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ +#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ +#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ +#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ +#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ +#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ +#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ +#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ +#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ +#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ +#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ +#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ +#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ +#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ +#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ +#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ +#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ +#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ +#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */ +#define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */ + +/* EXTI_PD */ +#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ +#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ +#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ +#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ +#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ +#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ +#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ +#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ +#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ +#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ +#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ +#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ +#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ +#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ +#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ +#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ +#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ +#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ +#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ +#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ +#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */ +#define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */ + +/* constants definitions */ +/* EXTI line number */ +typedef enum { + EXTI_0 = BIT(0), /*!< EXTI line 0 */ + EXTI_1 = BIT(1), /*!< EXTI line 1 */ + EXTI_2 = BIT(2), /*!< EXTI line 2 */ + EXTI_3 = BIT(3), /*!< EXTI line 3 */ + EXTI_4 = BIT(4), /*!< EXTI line 4 */ + EXTI_5 = BIT(5), /*!< EXTI line 5 */ + EXTI_6 = BIT(6), /*!< EXTI line 6 */ + EXTI_7 = BIT(7), /*!< EXTI line 7 */ + EXTI_8 = BIT(8), /*!< EXTI line 8 */ + EXTI_9 = BIT(9), /*!< EXTI line 9 */ + EXTI_10 = BIT(10), /*!< EXTI line 10 */ + EXTI_11 = BIT(11), /*!< EXTI line 11 */ + EXTI_12 = BIT(12), /*!< EXTI line 12 */ + EXTI_13 = BIT(13), /*!< EXTI line 13 */ + EXTI_14 = BIT(14), /*!< EXTI line 14 */ + EXTI_15 = BIT(15), /*!< EXTI line 15 */ + EXTI_16 = BIT(16), /*!< EXTI line 16 */ + EXTI_17 = BIT(17), /*!< EXTI line 17 */ + EXTI_18 = BIT(18), /*!< EXTI line 18 */ + EXTI_19 = BIT(19), /*!< EXTI line 19 */ + EXTI_20 = BIT(20), /*!< EXTI line 20 */ + EXTI_21 = BIT(21), /*!< EXTI line 21 */ + EXTI_22 = BIT(22), /*!< EXTI line 22 */ + EXTI_23 = BIT(23), /*!< EXTI line 23 */ + EXTI_24 = BIT(24), /*!< EXTI line 24 */ + EXTI_25 = BIT(25), /*!< EXTI line 25 */ + EXTI_26 = BIT(26), /*!< EXTI line 26 */ + EXTI_27 = BIT(27), /*!< EXTI line 27 */ +} exti_line_enum; + +/* external interrupt and event */ +typedef enum { + EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ + EXTI_EVENT /*!< EXTI event mode */ +} exti_mode_enum; + +/* interrupt trigger mode */ +typedef enum { + EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ + EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ + EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */ + EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */ +} exti_trig_type_enum; + +/* function declarations */ +/* reset EXTI, reset the value of all EXTI registers into initial values */ +void exti_deinit(void); +/* initialize the EXTI, enable the configuration of EXTI initialize */ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); +/* enable the interrupts from EXTI line x */ +void exti_interrupt_enable(exti_line_enum linex); +/* disable the interrupts from EXTI line x */ +void exti_interrupt_disable(exti_line_enum linex); +/* enable the events from EXTI line x */ +void exti_event_enable(exti_line_enum linex); +/* disable the events from EXTI line x */ +void exti_event_disable(exti_line_enum linex); + +/* enable EXTI software interrupt event */ +void exti_software_interrupt_enable(exti_line_enum linex); +/* disable EXTI software interrupt event */ +void exti_software_interrupt_disable(exti_line_enum linex); +/* get EXTI line x pending flag */ +FlagStatus exti_flag_get(exti_line_enum linex); +/* clear EXTI line x pending flag */ +void exti_flag_clear(exti_line_enum linex); +/* get EXTI line x flag when the interrupt flag is set */ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex); +/* clear EXTI line x pending flag */ +void exti_interrupt_flag_clear(exti_line_enum linex); + +#endif /* GD32F3X0_EXTI_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_fmc.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_fmc.h new file mode 100644 index 000000000..d2bd5a78d --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_fmc.h @@ -0,0 +1,258 @@ +/*! + \file gd32f3x0_fmc.h + \brief definitions for the FMC + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#ifndef GD32F3X0_FMC_H +#define GD32F3X0_FMC_H + +#include "gd32f3x0.h" + +/* FMC and option byte definition */ +#define FMC FMC_BASE /*!< FMC register base address */ +#define OB OB_BASE /*!< option byte base address */ + +/* registers definitions */ +#define FMC_WS REG32(FMC + 0x00000000U) /*!< FMC wait state register */ +#define FMC_KEY REG32(FMC + 0x00000004U) /*!< FMC unlock key register */ +#define FMC_OBKEY REG32(FMC + 0x00000008U) /*!< FMC option bytes unlock key register */ +#define FMC_STAT REG32(FMC + 0x0000000CU) /*!< FMC status register */ +#define FMC_CTL REG32(FMC + 0x00000010U) /*!< FMC control register */ +#define FMC_ADDR REG32(FMC + 0x00000014U) /*!< FMC address register */ +#define FMC_OBSTAT REG32(FMC + 0x0000001CU) /*!< FMC option bytes status register */ +#define FMC_WP REG32(FMC + 0x00000020U) /*!< FMC write protection register */ +#define FMC_WSEN REG32(FMC + 0x000000FCU) /*!< FMC wait state enable register */ +#define FMC_PID REG32(FMC + 0x00000100U) /*!< FMC product ID register */ + +#define OB_SPC REG16(OB + 0x00000000U) /*!< option byte security protection value */ +#define OB_USER REG16(OB + 0x00000002U) /*!< option byte user value */ +#define OB_DATA0 REG16(OB + 0x00000004U) /*!< option byte data bit[7:0] value */ +#define OB_DATA1 REG16(OB + 0x00000006U) /*!< option byte data bit[15:8] value */ +#define OB_WP0 REG16(OB + 0x00000008U) /*!< option byte write protection 0 */ +#define OB_WP1 REG16(OB + 0x0000000AU) /*!< option byte write protection 1 */ + +/* bits definitions */ +/* FMC_WS */ +#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ + +/* FMC_KEY */ +#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash unlock key bits */ + +/* FMC_OBKEY */ +#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ + +/* FMC_STAT */ +#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */ +#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */ +#define FMC_STAT_WPERR BIT(4) /*!< flash write protection error flag bit */ +#define FMC_STAT_ENDF BIT(5) /*!< end of operation flag bit */ + +/* FMC_CTL */ +#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */ +#define FMC_CTL_PER BIT(1) /*!< main flash page erase bit */ +#define FMC_CTL_MER BIT(2) /*!< main flash mass erase bit */ +#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */ +#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */ +#define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */ +#define FMC_CTL_LK BIT(7) /*!< flash lock bit */ +#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ +#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */ +#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ +#define FMC_CTL_OBRLD BIT(13) /*!< option bytes reload bit */ + +/* FMC_ADDR */ +#define FMC_ADDR_ADDR BITS(0,31) /*!< flash command address bits */ + +/* FMC_OBSTAT */ +#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit */ +#define FMC_OBSTAT_PLEVEL_BIT0 BIT(1) /*!< protection level bit 0 */ +#define FMC_OBSTAT_PLEVEL_BIT1 BIT(2) /*!< protection level bit 1 */ +#define FMC_OBSTAT_USER BITS(8,15) /*!< option bytes user bits */ +#define FMC_OBSTAT_DATA BITS(16,31) /*!< option byte data bits */ + +/* FMC_WSEN */ +#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ +#define FMC_WSEN_BPEN BIT(1) /*!< FMC bit program enable bit */ + +/* FMC_PID */ +#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ + +/* constants definitions */ +/* fmc state */ +typedef enum { + FMC_READY, /*!< the operation has been completed */ + FMC_BUSY, /*!< the operation is in progress */ + FMC_PGERR, /*!< program error */ + FMC_WPERR, /*!< erase/program protection error */ + FMC_TOERR, /*!< timeout error */ + FMC_OB_HSPC /*!< option byte security protection code high */ +} fmc_state_enum; + +/* option byte parameter */ +typedef struct { + uint8_t spc; /*!< option byte parameter spc */ + uint8_t user; /*!< option byte parameter user */ + uint8_t data0; /*!< option byte parameter data0 */ + uint8_t data1; /*!< option byte parameter data1 */ + uint8_t wp0; /*!< option byte parameter wp0 */ + uint8_t wp1; /*!< option byte parameter wp1 */ +} ob_parm_struct; + +/* unlock key */ +#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ +#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ + +/* wait state counter value */ +#define WS_WSCNT_0 ((uint8_t)0x00U) /*!< 0 wait state added */ +#define WS_WSCNT_1 ((uint8_t)0x01U) /*!< 1 wait state added */ +#define WS_WSCNT_2 ((uint8_t)0x02U) /*!< 2 wait state added */ + +/* read protect configure */ +#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ +#define FMC_LSPC ((uint8_t)0xBBU) /*!< low security protection, any value except 0xA5 or 0xCC */ +#define FMC_HSPC ((uint8_t)0xCCU) /*!< high security protection */ + +/* option byte write protection */ +#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */ +#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */ + +#define OB_FWDGT_HW ((uint8_t)(~BIT(0))) /*!< hardware free watchdog timer */ +#define OB_DEEPSLEEP_RST ((uint8_t)(~BIT(1))) /*!< generate a reset instead of entering deepsleep mode */ +#define OB_STDBY_RST ((uint8_t)(~BIT(2))) /*!< generate a reset instead of entering standby mode */ +#define OB_BOOT1_SET_1 ((uint8_t)(~BIT(4))) /*!< BOOT1 bit is 1 */ +#define OB_VDDA_DISABLE ((uint8_t)(~BIT(5))) /*!< disable VDDA monitor */ +#define OB_SRAM_PARITY_ENABLE ((uint8_t)(~BIT(6))) /*!< enable SRAM parity check */ + +/* option byte security protection level in FMC_OBSTAT register */ +#define OB_OBSTAT_PLEVEL_NO ((uint32_t)0x00000000U) /*!< no security protection */ +#define OB_OBSTAT_PLEVEL_LOW ((uint32_t)0x00000002U) /*!< low security protection */ +#define OB_OBSTAT_PLEVEL_HIGH ((uint32_t)0x00000006U) /*!< high security protection */ + +#define OB_USER_DEFAULT ((uint8_t)0xDFU) /*!< OB_USER default value */ + +/* option byte parameter address */ +#define OB_SPC_ADDR (uint32_t)(OB + 0x00000000U)/*!< option byte spc address */ +#define OB_USER_ADDR (uint32_t)(OB + 0x00000002U)/*!< option byte user address */ +#define OB_DATA_ADDR0 (uint32_t)(OB + 0x00000004U)/*!< option byte data address 0 */ +#define OB_DATA_ADDR1 (uint32_t)(OB + 0x00000006U)/*!< option byte data address 1 */ +#define OB_WP_ADDR0 (uint32_t)(OB + 0x00000008U)/*!< option byte wp address 0 */ +#define OB_WP_ADDR1 (uint32_t)(OB + 0x0000000AU)/*!< option byte wp address 1 */ + +/* FMC flags */ +#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */ +#define FMC_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */ +#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */ +#define FMC_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */ + +/* FMC interrupt enable */ +#define FMC_INTEN_END FMC_CTL_ENDIE /*!< enable FMC end of operation interrupt */ +#define FMC_INTEN_ERR FMC_CTL_ERRIE /*!< enable FMC error interrupt */ + +/* FMC time out */ +#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< count to judge of FMC timeout */ + +/* function declarations */ +/* FMC main memory programming functions */ +/* unlock the main FMC operation */ +void fmc_unlock(void); +/* lock the main FMC operation */ +void fmc_lock(void); +/* set the wait state counter value */ +void fmc_wscnt_set(uint8_t wscnt); +/* fmc wait state enable */ +void fmc_wait_state_enable(void); +/* fmc wait state disable */ +void fmc_wait_state_disable(void); +/* FMC erase page */ +fmc_state_enum fmc_page_erase(uint32_t page_address); +/* FMC erase whole chip */ +fmc_state_enum fmc_mass_erase(void); +/* FMC program a word at the corresponding address */ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); +/* FMC program a half word at the corresponding address */ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); +/* FMC program a word at the corresponding address without erasing */ +fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data); + +/* FMC option bytes programming functions */ +/* unlock the option byte operation */ +void ob_unlock(void); +/* lock the option byte operation */ +void ob_lock(void); +/* reload the option byte and generate a system reset */ +void ob_reset(void); +/* erase option byte */ +fmc_state_enum ob_erase(void); +/* enable option byte write protection (OB_WP) */ +fmc_state_enum ob_write_protection_enable(uint16_t ob_wp); +/* configure read out protect */ +fmc_state_enum ob_security_protection_config(uint8_t ob_spc); +/* write the FMC option byte user */ +fmc_state_enum ob_user_write(uint8_t ob_user); +/* write the FMC option byte data */ +fmc_state_enum ob_data_program(uint32_t address, uint8_t data); +/* get the FMC option byte OB_USER */ +uint8_t ob_user_get(void); +/* get the FMC option byte OB_DATA */ +uint16_t ob_data_get(void); +/* get the FMC option byte write protection */ +uint16_t ob_write_protection_get(void); +/* get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register */ +uint32_t ob_obstat_plevel_get(void); + +/* FMC interrupts and flags management functions */ +/* enable FMC interrupt */ +void fmc_interrupt_enable(uint32_t interrupt); +/* disable FMC interrupt */ +void fmc_interrupt_disable(uint32_t interrupt); +/* get flag set or reset */ +FlagStatus fmc_flag_get(uint32_t flag); +/* clear the FMC pending flag */ +void fmc_flag_clear(uint32_t flag); +/* get interrupt flag set or reset */ +FlagStatus fmc_interrupt_flag_get(uint32_t flag); +/* clear the FMC interrupt pending flag */ +void fmc_interrupt_flag_clear(uint32_t flag); +/* return the FMC state */ +fmc_state_enum fmc_state_get(void); +/* check FMC ready or not */ +fmc_state_enum fmc_ready_wait(uint32_t timeout); +/* get current option byte value */ +void ob_parm_get(ob_parm_struct *ob_parm); +/* modify the target option byte depending on the original value */ +void ob_value_modify(uint32_t address, uint16_t value, ob_parm_struct *ob_parm); + +#endif /* GD32F3X0_FMC_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_fwdgt.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_fwdgt.h new file mode 100644 index 000000000..852aa009c --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_fwdgt.h @@ -0,0 +1,126 @@ +/*! + \file gd32f3x0_fwdgt.h + \brief definitions for the FWDGT + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#ifndef GD32F3X0_FWDGT_H +#define GD32F3X0_FWDGT_H + +#include "gd32f3x0.h" + +/* FWDGT definitions */ +#define FWDGT FWDGT_BASE + +/* registers definitions */ +#define FWDGT_CTL REG32(FWDGT + 0x00000000U) /*!< FWDGT control register */ +#define FWDGT_PSC REG32(FWDGT + 0x00000004U) /*!< FWDGT prescaler register */ +#define FWDGT_RLD REG32(FWDGT + 0x00000008U) /*!< FWDGT reload register */ +#define FWDGT_STAT REG32(FWDGT + 0x0000000CU) /*!< FWDGT status register */ +#define FWDGT_WND REG32(FWDGT + 0x00000010U) /*!< FWDGT window register */ + +/* bits definitions */ +/* FWDGT_CTL */ +#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ + +/* FWDGT_PSC */ +#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ + +/* FWDGT_RLD */ +#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ + +/* FWDGT_STAT */ +#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ +#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ +#define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */ + +/* FWDGT_WND */ +#define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */ + +/* constants definitions */ +/* FWDGT_CTL register value */ +#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_CTL_CMD bit field */ + +/* FWDGT_PSC register value */ +#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U)) +#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ +#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ +#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ +#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ +#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ +#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ +#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ + +/* FWDGT_RLD register value */ +#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_RLD_RLD bit field */ + +/* FWDGT_WND register value */ +#define WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_WND_WND bit field */ + +/* control value */ +#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ +#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ +#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ +#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ + +/* FWDGT timeout value */ +#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */ +#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ +#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ + +/* FWDGT flag definitions */ +#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */ +#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */ +#define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */ + +/* function declarations */ +/* enable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND */ +void fwdgt_write_enable(void); +/* disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND */ +void fwdgt_write_disable(void); +/* start the free watchdog timer counter */ +void fwdgt_enable(void); + +/* configure the free watchdog timer counter window value */ +ErrStatus fwdgt_window_value_config(uint16_t window_value); +/* reload the counter of FWDGT */ +void fwdgt_counter_reload(void); +/* configure counter reload value, and prescaler divider value */ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); + +/* get flag state of FWDGT */ +FlagStatus fwdgt_flag_get(uint16_t flag); + +#endif /* GD32F3X0_FWDGT_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_gpio.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_gpio.h new file mode 100644 index 000000000..02dc0a7b1 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_gpio.h @@ -0,0 +1,410 @@ +/*! + \file gd32f3x0_gpio.h + \brief definitions for the GPIO + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_GPIO_H +#define GD32F3X0_GPIO_H + +#include "gd32f3x0.h" + +/* GPIOx(x=A,B,C,D,F) definitions */ +#define GPIOA (GPIO_BASE + 0x00000000U) +#define GPIOB (GPIO_BASE + 0x00000400U) +#define GPIOC (GPIO_BASE + 0x00000800U) +#define GPIOD (GPIO_BASE + 0x00000C00U) +#define GPIOF (GPIO_BASE + 0x00001400U) + +/* registers definitions */ +#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00000000U) /*!< GPIO port control register */ +#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x00000004U) /*!< GPIO port output mode register */ +#define GPIO_OSPD0(gpiox) REG32((gpiox) + 0x00000008U) /*!< GPIO port output speed register 0 */ +#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0000000CU) /*!< GPIO port pull-up/pull-down register */ +#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x00000010U) /*!< GPIO port input status register */ +#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x00000014U) /*!< GPIO port output control register */ +#define GPIO_BOP(gpiox) REG32((gpiox) + 0x00000018U) /*!< GPIO port bit operation register */ +#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x0000001CU) /*!< GPIO port configuration lock register */ +#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x00000020U) /*!< GPIO alternate function selected register 0 */ +#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x00000024U) /*!< GPIO alternate function selected register 1 */ +#define GPIO_BC(gpiox) REG32((gpiox) + 0x00000028U) /*!< GPIO bit clear register */ +#define GPIO_TG(gpiox) REG32((gpiox) + 0x0000002CU) /*!< GPIO port bit toggle register */ +#define GPIO_OSPD1(gpiox) REG32((gpiox) + 0x0000003CU) /*!< GPIO port output speed register 1 */ + +/* bits definitions */ +/* GPIO_CTL */ +#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */ +#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */ +#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */ +#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */ +#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */ +#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */ +#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */ +#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */ +#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */ +#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */ +#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */ +#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */ +#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */ +#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */ +#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */ +#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ + +/* GPIO_OMODE */ +#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */ +#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */ +#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */ +#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */ +#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */ +#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */ +#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */ +#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */ +#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */ +#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */ +#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */ +#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */ +#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */ +#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */ +#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */ +#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */ + +/* GPIO_OSPD0 */ +#define GPIO_OSPD0_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */ +#define GPIO_OSPD0_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */ +#define GPIO_OSPD0_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */ +#define GPIO_OSPD0_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */ +#define GPIO_OSPD0_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */ +#define GPIO_OSPD0_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */ +#define GPIO_OSPD0_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */ +#define GPIO_OSPD0_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */ +#define GPIO_OSPD0_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */ +#define GPIO_OSPD0_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */ +#define GPIO_OSPD0_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */ +#define GPIO_OSPD0_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */ +#define GPIO_OSPD0_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */ +#define GPIO_OSPD0_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */ +#define GPIO_OSPD0_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */ +#define GPIO_OSPD0_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */ + +/* GPIO_PUD */ +#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */ +#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */ +#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */ +#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */ +#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */ +#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */ +#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */ +#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */ +#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */ +#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */ +#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */ +#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */ +#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */ +#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */ +#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */ +#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */ + +/* GPIO_ISTAT */ +#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ +#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ +#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ +#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ +#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ +#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ +#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ +#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ +#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ +#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ +#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ +#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ +#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ +#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ +#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ +#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ + +/* GPIO_OCTL */ +#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ +#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ +#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ +#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ +#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ +#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ +#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ +#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ +#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ +#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ +#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ +#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ +#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ +#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ +#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ +#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ + +/* GPIO_BOP */ +#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ +#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ +#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ +#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ +#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ +#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ +#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ +#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ +#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ +#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ +#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ +#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ +#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ +#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ +#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ +#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ +#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ +#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ +#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ +#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ +#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ +#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ +#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ +#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ +#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ +#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ +#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ +#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ +#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ +#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ +#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ +#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ + +/* GPIO_LOCK */ +#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ +#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ +#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ +#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ +#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ +#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ +#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ +#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ +#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ +#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ +#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ +#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ +#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ +#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ +#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ +#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ +#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ + +/* GPIO_AFSEL0 */ +#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */ +#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */ +#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */ +#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */ +#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */ +#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */ +#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */ +#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */ + +/* GPIO_AFSEL1 */ +#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */ +#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */ +#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */ +#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */ +#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */ +#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */ +#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */ +#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */ + +/* GPIO_BC */ +#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ +#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ +#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ +#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ +#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ +#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ +#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ +#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ +#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ +#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ +#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ +#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ +#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ +#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ +#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ +#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ + +/* GPIO_TG */ +#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */ +#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */ +#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */ +#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */ +#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */ +#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */ +#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */ +#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */ +#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */ +#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */ +#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */ +#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */ +#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */ +#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */ +#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */ +#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */ + +/* GPIO_OSPD1 */ +#define GPIO_OSPD1_SPD0 BIT(0) /*!< set pin 0 very high output speed when OSPD0 is "11" */ +#define GPIO_OSPD1_SPD1 BIT(1) /*!< set pin 1 very high output speed when OSPD1 is "11" */ +#define GPIO_OSPD1_SPD2 BIT(2) /*!< set pin 2 very high output speed when OSPD2 is "11" */ +#define GPIO_OSPD1_SPD3 BIT(3) /*!< set pin 3 very high output speed when OSPD3 is "11" */ +#define GPIO_OSPD1_SPD4 BIT(4) /*!< set pin 4 very high output speed when OSPD4 is "11" */ +#define GPIO_OSPD1_SPD5 BIT(5) /*!< set pin 5 very high output speed when OSPD5 is "11" */ +#define GPIO_OSPD1_SPD6 BIT(6) /*!< set pin 6 very high output speed when OSPD6 is "11" */ +#define GPIO_OSPD1_SPD7 BIT(7) /*!< set pin 7 very high output speed when OSPD7 is "11" */ +#define GPIO_OSPD1_SPD8 BIT(8) /*!< set pin 8 very high output speed when OSPD8 is "11" */ +#define GPIO_OSPD1_SPD9 BIT(9) /*!< set pin 9 very high output speed when OSPD9 is "11" */ +#define GPIO_OSPD1_SPD10 BIT(10) /*!< set pin 10 very high output speed when OSPD10 is "11" */ +#define GPIO_OSPD1_SPD11 BIT(11) /*!< set pin 11 very high output speed when OSPD11 is "11" */ +#define GPIO_OSPD1_SPD12 BIT(12) /*!< set pin 12 very high output speed when OSPD12 is "11" */ +#define GPIO_OSPD1_SPD13 BIT(13) /*!< set pin 13 very high output speed when OSPD13 is "11" */ +#define GPIO_OSPD1_SPD14 BIT(14) /*!< set pin 14 very high output speed when OSPD14 is "11" */ +#define GPIO_OSPD1_SPD15 BIT(15) /*!< set pin 15 very high output speed when OSPD15 is "11" */ + +/* constants definitions */ +typedef FlagStatus bit_status; + +/* output mode definitions */ +#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */ +#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */ +#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */ +#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */ + +/* pull-up/pull-down definitions */ +#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */ +#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */ +#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */ + +/* GPIO pin definitions */ +#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ +#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ +#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ +#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ +#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ +#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ +#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ +#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ +#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ +#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ +#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ +#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ +#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ +#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ +#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ +#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ +#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ + +/* GPIO mode configuration values */ +#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n)))) +#define GPIO_MODE_MASK(n) ((uint32_t)((uint32_t)0x00000003U << (2U * (n)))) + +/* GPIO pull-up/pull-down values */ +#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n)))) +#define GPIO_PUPD_MASK(n) ((uint32_t)((uint32_t)0x00000003U << (2U * (n)))) + +/* GPIO output speed values */ +#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n)))) +#define GPIO_OSPEED_MASK(n) ((uint32_t)((uint32_t)0x00000003U << (2U * (n)))) + +/* GPIO output type */ +#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */ +#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */ + +/* GPIO output max speed value */ +#define OSPD_OSPD0(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define GPIO_OSPEED_2MHZ OSPD_OSPD0(0) /*!< output max speed 2MHz */ +#define GPIO_OSPEED_10MHZ OSPD_OSPD0(1) /*!< output max speed 10MHz */ +#define GPIO_OSPEED_50MHZ OSPD_OSPD0(3) /*!< output max speed 50MHz */ +#define GPIO_OSPEED_MAX ((uint32_t)0x0000FFFFU) /*!< GPIO very high output speed, max speed more than 50MHz */ + +/* GPIO alternate function values */ +#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n)))) +#define GPIO_AFR_MASK(n) ((uint32_t)((uint32_t)0x0000000FU << (4U * (n)))) + +/* GPIO alternate function */ +#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */ +#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */ +#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */ +#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */ +#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected (port A,B only) */ +#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected (port A,B only) */ +#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected (port A,B only) */ +#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected (port A,B only) */ + +/* function declarations */ +/* reset GPIO port */ +void gpio_deinit(uint32_t gpio_periph); +/* set GPIO mode */ +void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin); +/* set GPIO output type and speed */ +void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin); + +/* set GPIO pin bit */ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); +/* reset GPIO pin bit */ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); +/* write data to the specified GPIO pin */ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); +/* write data to the specified GPIO port */ +void gpio_port_write(uint32_t gpio_periph, uint16_t data); + +/* get GPIO pin input status */ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port input status */ +uint16_t gpio_input_port_get(uint32_t gpio_periph); +/* get GPIO pin output status */ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port output status */ +uint16_t gpio_output_port_get(uint32_t gpio_periph); + +/* set GPIO alternate function */ +void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin); +/* lock GPIO pin bit */ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); + +/* toggle GPIO pin status */ +void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin); +/* toggle GPIO port status */ +void gpio_port_toggle(uint32_t gpio_periph); + +#endif /* GD32F3X0_GPIO_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_i2c.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_i2c.h new file mode 100644 index 000000000..fa00a6fca --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_i2c.h @@ -0,0 +1,347 @@ +/*! + \file gd32f3x0_i2c.h + \brief definitions for the I2C + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_I2C_H +#define GD32F3X0_I2C_H + +#include "gd32f3x0.h" + +/* I2Cx(x=0,1) definitions */ +#define I2C0 I2C_BASE /*!< I2C0 base address */ +#define I2C1 (I2C_BASE+0x00000400U) /*!< I2C1 base address */ + +/* registers definitions */ +#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */ +#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */ +#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0*/ +#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register */ +#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */ +#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */ +#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */ +#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */ +#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */ +#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x00000090U) /*!< I2C fast-mode-plus configure register */ + +/* bits definitions */ +/* I2Cx_CTL0 */ +#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ +#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ +#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ +#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ +#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ +#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ +#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ +#define I2C_CTL0_START BIT(8) /*!< start generation */ +#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ +#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ +#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ +#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ +#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ +#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ + +/* I2Cx_CTL1 */ +#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ +#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt inable */ +#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ +#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ +#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ +#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ + +/* I2Cx_SADDR0 */ +#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ +#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ + +/* I2Cx_SADDR1 */ +#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ +#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ + +/* I2Cx_DATA */ +#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ + +/* I2Cx_STAT0 */ +#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ +#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ +#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ +#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ +#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ +#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ +#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ +#define I2C_STAT0_BERR BIT(8) /*!< bus error */ +#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ +#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ +#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ +#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ +#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ +#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ + +/* I2Cx_STAT1 */ +#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ +#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ +#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ +#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ +#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ +#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ +#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ +#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ + +/* I2Cx_CKCFG */ +#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ +#define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */ +#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ + +/* I2Cx_RT */ +#define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ + +/* I2Cx_FMPCFG */ +#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ + +/* constants definitions */ +/* define the I2C bit position and its register index offset */ +#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) +#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) +#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) +#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) + +/* register offset */ +#define I2C_CTL1_REG_OFFSET (0x00000004U) /*!< CTL1 register offset */ +#define I2C_STAT0_REG_OFFSET (0x00000014U) /*!< STAT0 register offset */ +#define I2C_STAT1_REG_OFFSET (0x00000018U) /*!< STAT1 register offset */ + +/* I2C flags */ +typedef enum { + /* flags in STAT0 register */ + I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ + I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ + I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ + I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ + I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving */ + I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ + I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ + I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ + I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ + I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ + I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ + I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ + I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ + /* flags in STAT1 register */ + I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ + I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ + I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ + I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ + I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ + I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ + I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U) /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ +} i2c_flag_enum; + +/* I2C interrupt flags */ +typedef enum { + /* interrupt flags in CTL1 register */ + I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ + I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ + I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ + I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ + I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving interrupt flag */ + I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ + I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ + I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ + I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ + I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ + I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ + I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ + I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ +} i2c_interrupt_flag_enum; + +/* I2C interrupt enable or disable */ +typedef enum { + /* interrupt in CTL1 register */ + I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ + I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ + I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ +} i2c_interrupt_enum; + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ +#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ +#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ + +/* I2C transfer direction */ +#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ +#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ + +/* whether or not to send an ACK */ +#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ +#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ + +/* I2C POAP position*/ +#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ +#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ + +/* whether or not to stretch SCL low */ +#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is enabled */ +#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is disabled */ + +/* whether or not to response to a general call */ +#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ +#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ + +/* software reset I2C */ +#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ +#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ + +/* I2C DMA mode configure */ +/* DMA mode switch */ +#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ +#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ + +/* flag indicating DMA last transfer */ +#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ +#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ + +/* I2C PEC configure */ +/* PEC enable */ +#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ +#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ + +/* PEC transfer */ +#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ +#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ + +/* I2C SMBus configure */ +/* issue or not alert through SMBA pin */ +#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ +#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ + +/* ARP protocol in SMBus switch */ +#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ +#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ + +/* fast mode plus enable */ +#define I2C_FAST_MODE_PLUS_ENABLE I2C_FMPCFG_FMPEN /*!< fast mode plus enable */ +#define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */ + +/* transmit I2C data */ +#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* receive I2C data */ +#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* I2C duty cycle in fast mode or fast mode plus */ +#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 2 */ +#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 16/9 */ + +/* address mode for the I2C slave */ +#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ +#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ + +/* function declarations */ +/* reset I2C */ +void i2c_deinit(uint32_t i2c_periph); +/* configure I2C clock */ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); +/* configure I2C address */ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); +/* SMBus type selection */ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); +/* whether or not to send an ACK */ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); +/* configure I2C position of ACK and PEC when receiving */ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); +/* master sends slave address */ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); +/* enable dual-address mode */ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr); +/* disable dual-address mode */ +void i2c_dualaddr_disable(uint32_t i2c_periph); +/* enable I2C */ +void i2c_enable(uint32_t i2c_periph); +/* disable I2C */ +void i2c_disable(uint32_t i2c_periph); + +/* generate a START condition on I2C bus */ +void i2c_start_on_bus(uint32_t i2c_periph); +/* generate a STOP condition on I2C bus */ +void i2c_stop_on_bus(uint32_t i2c_periph); +/* I2C transmit data function */ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); +/* I2C receive data function */ +uint8_t i2c_data_receive(uint32_t i2c_periph); +/* enable I2C DMA mode */ +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); +/* configure whether next DMA EOT is DMA last transfer or not */ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); +/* whether to stretch SCL low when data is not ready in slave mode */ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); +/* whether or not to response to a general call */ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); +/* software reset I2C */ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); + +/* whether to enable I2C PEC calculation or not */ +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); +/* I2C whether to transfer PEC value */ +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); +/* packet error checking value */ +uint8_t i2c_pec_value_get(uint32_t i2c_periph); +/* I2C issue alert through SMBA pin */ +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); +/* whether ARP is enabled under SMBus */ +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); + +/* check I2C flag is set or not */ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); +/* clear I2C flag */ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); +/* enable I2C interrupt */ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* disable I2C interrupt */ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* check I2C interrupt flag */ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); +/* clear I2C interrupt flag */ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); + +#endif /* GD32F3X0_I2C_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_misc.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_misc.h new file mode 100644 index 000000000..1ec6111e0 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_misc.h @@ -0,0 +1,94 @@ +/*! + \file gd32f3x0_misc.h + \brief definitions for the MISC + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_MISC_H +#define GD32F3X0_MISC_H + +#include "gd32f3x0.h" + +/* constants definitions */ +/* set the RAM and FLASH base address */ +#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ +#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ + +/* set the NVIC vector table offset mask */ +#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) /*!< NVIC vector table offset mask */ + +/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ +#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) /*!< NVIC VECTKEY mask */ + +/* priority group - define the pre-emption priority and the subpriority */ +#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x00000700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ +#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x00000600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ +#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x00000500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ +#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x00000400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ +#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x00000300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ + +/* choose the method to enter or exit the lowpower mode */ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ + +#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT /*!< low power mode by exiting from ISR */ +#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP /*!< DEEPSLEEP mode or SLEEP mode */ +#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND /*!< wakeup by all interrupt */ + +/* choose the systick clock source */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ + +/* function declarations */ +/* set the priority group */ +void nvic_priority_group_set(uint32_t nvic_prigroup); + +/* enable NVIC request */ +void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); +/* disable NVIC request */ +void nvic_irq_disable(uint8_t nvic_irq); + +/* set the NVIC vector table base address */ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); + +/* set the state of the low power mode */ +void system_lowpower_set(uint8_t lowpower_mode); +/* reset the state of the low power mode */ +void system_lowpower_reset(uint8_t lowpower_mode); + +/* set the systick clock source */ +void systick_clksource_set(uint32_t systick_clksource); + +#endif /* GD32F3X0_MISC_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_pmu.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_pmu.h new file mode 100644 index 000000000..e5efb4a74 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_pmu.h @@ -0,0 +1,199 @@ +/*! + \file gd32f3x0_pmu.h + \brief definitions for the PMU + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_PMU_H +#define GD32F3X0_PMU_H + +#include "gd32f3x0.h" + +/* PMU definitions */ +#define PMU PMU_BASE /*!< PMU base address */ + +/* registers definitions */ +#define PMU_CTL REG32(PMU + 0x00000000U) /*!< PMU control register */ +#define PMU_CS REG32(PMU + 0x00000004U) /*!< PMU control and status register */ + +/* bits definitions */ +/* PMU_CTL */ +#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ +#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ +#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ +#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ +#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ +#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ +#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ +#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ +#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ +#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ +#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ +#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ +#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ + +/* PMU_CS */ +#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ +#define PMU_CS_STBF BIT(1) /*!< standby flag */ +#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ +#define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin enable */ +#define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin enable */ +#define PMU_CS_WUPEN4 BIT(12) /*!< wakeup pin enable */ +#define PMU_CS_WUPEN5 BIT(13) /*!< wakeup pin enable */ +#define PMU_CS_WUPEN6 BIT(14) /*!< wakeup pin enable */ +#define PMU_CS_LDOVSRF BIT(15) /*!< LDO voltage select ready flag */ +#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ +#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ +#define PMU_CS_LDRF BITS(18,19) /*!< low-driver mode ready flag */ + +/* constants definitions */ +/* PMU low voltage detector threshold definitions */ +#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) +#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ +#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ +#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ +#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ +#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ +#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ +#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ +#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ + +/* PMU LDO output voltage select definitions */ +#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) +#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ +#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ +#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ + +/* PMU low-driver mode enable in deep-sleep mode */ +#define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) +#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */ +#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */ + +/* PMU low power mode ready flag definitions */ +#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) +#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal-driver in deep-sleep mode */ +#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ + +/* PMU high-driver mode switch */ +#define PMU_HIGHDR_SWITCH_NONE ((uint32_t)0x00000000U) /*!< no high-driver mode switch */ +#define PMU_HIGHDR_SWITCH_EN PMU_CTL_HDS /*!< high-driver mode switch */ + +/* PMU low-driver mode when use normal power LDO */ +#define PMU_NORMALDR_NORMALPWR ((uint32_t)0x00000000U) /*!< normal-driver when use normal power LDO */ +#define PMU_LOWDR_NORMALPWR PMU_CTL_LDNP /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ + +/* PMU low-driver mode when use low power LDO */ +#define PMU_NORMALDR_LOWPWR ((uint32_t)0x00000000U) /*!< normal-driver when use low power LDO */ +#define PMU_LOWDR_LOWPWR PMU_CTL_LDLP /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */ + +/* PMU ldo definitions */ +#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO operates normally when PMU enter deepsleep mode */ +#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ + +/* PMU flag definitions */ +#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ +#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ +#define PMU_FLAG_LVD PMU_CS_LVDF /*!< LVD flag status */ +#define PMU_FLAG_LDOVSR PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */ +#define PMU_FLAG_HDR PMU_CS_HDRF /*!< high-driver ready flag */ +#define PMU_FLAG_HDSR PMU_CS_HDSRF /*!< high-driver switch ready flag */ +#define PMU_FLAG_LDR PMU_CS_LDRF /*!< low-driver mode ready flag */ + +/* PMU WKUP pin definitions */ +#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */ +#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< WKUP Pin 1 (PC13) enable */ +#define PMU_WAKEUP_PIN4 PMU_CS_WUPEN4 /*!< WKUP Pin 4 (PC5) enable */ +#define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5 /*!< WKUP Pin 5 (PB5) enable */ +#define PMU_WAKEUP_PIN6 PMU_CS_WUPEN6 /*!< WKUP Pin 6 (PB15) enable */ + +/* PMU flag reset definitions */ +#define PMU_FLAG_RESET_WAKEUP PMU_CTL_WURST /*!< wakeup flag reset */ +#define PMU_FLAG_RESET_STANDBY PMU_CTL_STBRST /*!< standby flag reset */ + +/* PMU command constants definitions */ +#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ +#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ + +/* function declarations */ +/* function configuration */ +/* reset PMU registers */ +void pmu_deinit(void); +/* select low voltage detector threshold */ +void pmu_lvd_select(uint32_t lvdt_n); +/* select LDO output voltage */ +void pmu_ldo_output_select(uint32_t ldo_output); +/* disable PMU lvd */ +void pmu_lvd_disable(void); + +/* functions of low-driver mode and high-driver mode in deep-sleep mode */ +/* enable low-driver mode in deep-sleep mode */ +void pmu_lowdriver_mode_enable(void); +/* disable low-driver mode in deep-sleep mode */ +void pmu_lowdriver_mode_disable(void); +/* enable high-driver mode */ +void pmu_highdriver_mode_enable(void); +/* disable high-driver mode */ +void pmu_highdriver_mode_disable(void); +/* switch high-driver mode */ +void pmu_highdriver_switch_select(uint32_t highdr_switch); +/* in deep-sleep mode, low-driver mode when use low power LDO */ +void pmu_lowpower_driver_config(uint32_t mode); +/* in deep-sleep mode, low-driver mode when use normal power LDO */ +void pmu_normalpower_driver_config(uint32_t mode); + +/* set PMU mode */ +/* PMU work in sleep mode */ +void pmu_to_sleepmode(uint8_t sleepmodecmd); +/* PMU work in deepsleep mode */ +void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd); +/* PMU work in standby mode */ +void pmu_to_standbymode(uint8_t standbymodecmd); +/* enable PMU wakeup pin */ +void pmu_wakeup_pin_enable(uint32_t wakeup_pin); +/* disable PMU wakeup pin */ +void pmu_wakeup_pin_disable(uint32_t wakeup_pin); + +/* backup related functions */ +/* enable backup domain write */ +void pmu_backup_write_enable(void); +/* disable backup domain write */ +void pmu_backup_write_disable(void); + +/* flag functions */ +/* get flag state */ +FlagStatus pmu_flag_get(uint32_t flag); +/* clear flag bit */ +void pmu_flag_clear(uint32_t flag); + +#endif /* GD32F3X0_PMU_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_rcu.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_rcu.h new file mode 100644 index 000000000..49883164f --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_rcu.h @@ -0,0 +1,788 @@ +/*! + \file gd32f3x0_rcu.h + \brief definitions for the RCU + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_RCU_H +#define GD32F3X0_RCU_H + +#include "gd32f3x0.h" + +/* RCU definitions */ +#define RCU RCU_BASE + +/* registers definitions */ +#define RCU_CTL0 REG32(RCU + 0x00000000U) /*!< control register 0 */ +#define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< configuration register 0 */ +#define RCU_INT REG32(RCU + 0x00000008U) /*!< interrupt register */ +#define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */ +#define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */ +#define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB enable register */ +#define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */ +#define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */ +#define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control register */ +#define RCU_RSTSCK REG32(RCU + 0x00000024U) /*!< reset source /clock register */ +#define RCU_AHBRST REG32(RCU + 0x00000028U) /*!< AHB reset register */ +#define RCU_CFG1 REG32(RCU + 0x0000002CU) /*!< configuration register 1 */ +#define RCU_CFG2 REG32(RCU + 0x00000030U) /*!< configuration register 2 */ +#define RCU_CTL1 REG32(RCU + 0x00000034U) /*!< control register 1 */ +#define RCU_ADDCTL REG32(RCU + 0x000000C0U) /*!< additional clock control register */ +#define RCU_ADDINT REG32(RCU + 0x000000CCU) /*!< additional clock interrupt register */ +#define RCU_ADDAPB1EN REG32(RCU + 0x000000F8U) /*!< APB1 additional enable register */ +#define RCU_ADDAPB1RST REG32(RCU + 0x000000FCU) /*!< APB1 additional reset register */ +#define RCU_VKEY REG32(RCU + 0x00000100U) /*!< voltage key register */ +#define RCU_DSV REG32(RCU + 0x00000134U) /*!< deep-sleep mode voltage register */ + +/* bits definitions */ +/* RCU_CTL0 */ +#define RCU_CTL0_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ +#define RCU_CTL0_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +#define RCU_CTL0_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +#define RCU_CTL0_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ +#define RCU_CTL0_HXTALEN BIT(16) /*!< external high speed oscillator enable */ +#define RCU_CTL0_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ +#define RCU_CTL0_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ +#define RCU_CTL0_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ +#define RCU_CTL0_PLLEN BIT(24) /*!< PLL enable */ +#define RCU_CTL0_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ + +/* RCU_CFG0 */ +#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC clock prescaler selection */ +#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ +#define RCU_CFG0_PLLPREDV BIT(17) /*!< divider for PLL source clock selection */ +#define RCU_CFG0_PLLMF (BIT(27) | BITS(18,21)) /*!< PLL multiply factor */ +#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ +#define RCU_CFG0_CKOUTSEL BITS(24,26) /*!< CK_OUT clock source selection */ +#define RCU_CFG0_PLLMF4 BIT(27) /*!< bit 4 of PLLMF */ +#define RCU_CFG0_CKOUTDIV BITS(28,30) /*!< CK_OUT divider which the CK_OUT frequency can be reduced */ +#define RCU_CFG0_PLLDV BIT(31) /*!< CK_PLL divide by 1 or 2 */ + +/* RCU_INT */ +#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ +#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ +#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ +#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ +#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ +#define RCU_INT_IRC28MSTBIF BIT(5) /*!< IRC28M stabilization interrupt flag */ +#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ +#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ +#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ +#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ +#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ +#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ +#define RCU_INT_IRC28MSTBIE BIT(13) /*!< IRC28M stabilization interrupt enable */ +#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ +#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ +#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ +#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ +#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ +#define RCU_INT_IRC28MSTBIC BIT(21) /*!< IRC28M stabilization interrupt clear */ +#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ + +/* RCU_APB2RST */ +#define RCU_APB2RST_CFGRST BIT(0) /*!< system configuration reset */ +#define RCU_APB2RST_ADCRST BIT(9) /*!< ADC reset */ +#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ +#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ +#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ +#define RCU_APB2RST_TIMER14RST BIT(16) /*!< TIMER14 reset */ +#define RCU_APB2RST_TIMER15RST BIT(17) /*!< TIMER15 reset */ +#define RCU_APB2RST_TIMER16RST BIT(18) /*!< TIMER16 reset */ + +/* RCU_APB1RST */ +#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 timer reset */ +#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 timer reset */ +#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 timer reset */ +#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 timer reset */ +#define RCU_APB1RST_WWDGTRST BIT(11) /*!< window watchdog timer reset */ +#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ +#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ +#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ +#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ +#define RCU_APB1RST_PMURST BIT(28) /*!< power control reset */ +#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ +#define RCU_APB1RST_CECRST BIT(30) /*!< HDMI CEC reset */ + +/* RCU_AHBEN */ +#define RCU_AHBEN_DMAEN BIT(0) /*!< DMA clock enable */ +#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM interface clock enable */ +#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable */ +#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ +#define RCU_AHBEN_USBFS BIT(12) /*!< USBFS clock enable */ +#define RCU_AHBEN_PAEN BIT(17) /*!< GPIO port A clock enable */ +#define RCU_AHBEN_PBEN BIT(18) /*!< GPIO port B clock enable */ +#define RCU_AHBEN_PCEN BIT(19) /*!< GPIO port C clock enable */ +#define RCU_AHBEN_PDEN BIT(20) /*!< GPIO port D clock enable */ +#define RCU_AHBEN_PFEN BIT(22) /*!< GPIO port F clock enable */ +#define RCU_AHBEN_TSIEN BIT(24) /*!< TSI clock enable */ + +/* RCU_APB2EN */ +#define RCU_APB2EN_CFGCMPEN BIT(0) /*!< system configuration and comparator clock enable */ +#define RCU_APB2EN_ADCEN BIT(9) /*!< ADC interface clock enable */ +#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 timer clock enable */ +#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ +#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ +#define RCU_APB2EN_TIMER14EN BIT(16) /*!< TIMER14 timer clock enable */ +#define RCU_APB2EN_TIMER15EN BIT(17) /*!< TIMER15 timer clock enable */ +#define RCU_APB2EN_TIMER16EN BIT(18) /*!< TIMER16 timer clock enable */ + +/* RCU_APB1EN */ +#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 timer clock enable */ +#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 timer clock enable */ +#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 timer clock enable */ +#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 timer clock enable */ +#define RCU_APB1EN_WWDGTEN BIT(11) /*!< window watchdog timer clock enable */ +#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ +#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ +#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ +#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ +#define RCU_APB1EN_PMUEN BIT(28) /*!< power interface clock enable */ +#define RCU_APB1EN_DACEN BIT(29) /*!< DAC interface clock enable */ +#define RCU_APB1EN_CECEN BIT(30) /*!< HDMI CEC interface clock enable */ + +/* RCU_BDCTL */ +#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ +#define RCU_BDCTL_LXTALSTB BIT(1) /*!< external low-speed oscillator stabilization */ +#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ +#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ +#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ +#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ +#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ + +/* RCU_RSTSCK */ +#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ +#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization */ +#define RCU_RSTSCK_V12RSTF BIT(23) /*!< V12 domain power reset flag */ +#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ +#define RCU_RSTSCK_OBLRSTF BIT(25) /*!< option byte loader reset flag */ +#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ +#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ +#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ +#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ +#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ +#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ + +/* RCU_AHBRST */ +#define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ +#define RCU_AHBRST_PARST BIT(17) /*!< GPIO port A reset */ +#define RCU_AHBRST_PBRST BIT(18) /*!< GPIO port B reset */ +#define RCU_AHBRST_PCRST BIT(19) /*!< GPIO port C reset */ +#define RCU_AHBRST_PDRST BIT(20) /*!< GPIO port D reset */ +#define RCU_AHBRST_PFRST BIT(22) /*!< GPIO port F reset */ +#define RCU_AHBRST_TSIRST BIT(24) /*!< TSI unit reset */ + +/* RCU_CFG1 */ +#define RCU_CFG1_PREDV BITS(0,3) /*!< CK_HXTAL divider previous PLL */ +#define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source preselection */ +#define RCU_CFG1_PLLMF5 BIT(31) /*!< bit 5 of PLLMF */ + +/* RCU_CFG2 */ +#define RCU_CFG2_USART0SEL BITS(0,1) /*!< CK_USART0 clock source selection */ +#define RCU_CFG2_CECSEL BIT(6) /*!< CK_CEC clock source selection */ +#define RCU_CFG2_ADCSEL BIT(8) /*!< CK_ADC clock source selection */ +#define RCU_CFG2_IRC28MDIV BIT(16) /*!< CK_IRC28M divider 2 or not */ +#define RCU_CFG2_USBFSPSC2 BIT(30) /*!< bit 2 of USBFSPSC */ +#define RCU_CFG2_ADCPSC2 BIT(31) /*!< bit 2 of ADCPSC */ + +/* RCU_CTL1 */ +#define RCU_CTL1_IRC28MEN BIT(0) /*!< IRC28M internal 28M RC oscillator enable */ +#define RCU_CTL1_IRC28MSTB BIT(1) /*!< IRC28M internal 28M RC oscillator stabilization flag */ +#define RCU_CTL1_IRC28MADJ BITS(3,7) /*!< internal 28M RC oscillator clock trim adjust value */ +#define RCU_CTL1_IRC28MCALIB BITS(8,15) /*!< internal 28M RC oscillator calibration value register */ + +/* RCU_ADDCTL */ +#define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48M clock selection */ +#define RCU_ADDCTL_IRC48MEN BIT(16) /*!< IRC48M internal 48M RC oscillator enable */ +#define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48M RC oscillator stabilization flag */ +#define RCU_ADDCTL_IRC48MCALIB BITS(24,31) /*!< internal 48M RC oscillator calibration value register */ + +/* RCU_ADDINT */ +#define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ +#define RCU_ADDINT_IRC48MSTBIE BIT(14) /*!< IRC48M stabilization interrupt enable */ +#define RCU_ADDINT_IRC48MSTBIC BIT(22) /*!< IRC48M stabilization interrupt clear */ + +/* RCU_ADDAPB1EN */ +#define RCU_ADDAPB1EN_CTCEN BIT(27) /*!< CTC unit clock enable */ + +/* RCU_ADDAPB1RST */ +#define RCU_ADDAPB1RST_CTCRST BIT(27) /*!< CTC unit reset */ + +/* RCU_VKEY */ +#define RCU_VKEY_KEY BITS(0,31) /*!< key of RCU_DSV register */ + +/* RCU_DSV */ +#define RCU_DSV_DSLPVS BITS(0,1) /*!< deep-sleep mode voltage select */ + +/* constants definitions */ +/* define the peripheral clock enable bit position and its register index offset */ +#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx)<<6) | (uint32_t)(bitpos)) +#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph)>>6))) +#define RCU_BIT_POS(val) ((uint32_t)(val) & (uint32_t)0x0000001FU) +/* define the voltage key unlock value */ +#define RCU_VKEY_UNLOCK ((uint32_t)0x1A2B3C4DU) + +/* register index */ +typedef enum { + /* peripherals enable */ + IDX_AHBEN = ((uint32_t)0x00000014U), + IDX_APB2EN = ((uint32_t)0x00000018U), + IDX_APB1EN = ((uint32_t)0x0000001CU), + IDX_ADDAPB1EN = ((uint32_t)0x000000F8U), + /* peripherals reset */ + IDX_AHBRST = ((uint32_t)0x00000028U), + IDX_APB2RST = ((uint32_t)0x0000000CU), + IDX_APB1RST = ((uint32_t)0x00000010U), + IDX_ADDAPB1RST = ((uint32_t)0x000000FCU), + /* clock stabilization */ + IDX_CTL0 = ((uint32_t)0x00000000U), + IDX_BDCTL = ((uint32_t)0x00000020U), + IDX_CTL1 = ((uint32_t)0x00000034U), + IDX_ADDCTL = ((uint32_t)0x000000C0U), + /* peripheral reset */ + IDX_RSTSCK = ((uint32_t)0x00000024U), + /* clock stabilization and stuck interrupt */ + IDX_INT = ((uint32_t)0x00000008U), + IDX_ADDINT = ((uint32_t)0x000000CCU), + /* configuration register */ + IDX_CFG0 = ((uint32_t)0x00000004U), + IDX_CFG2 = ((uint32_t)0x00000030U) +} reg_idx; + +/* peripheral clock enable */ +typedef enum { + /* AHB peripherals */ + RCU_DMA = RCU_REGIDX_BIT(IDX_AHBEN, 0U), /*!< DMA clock */ + RCU_CRC = RCU_REGIDX_BIT(IDX_AHBEN, 6U), /*!< CRC clock */ + RCU_GPIOA = RCU_REGIDX_BIT(IDX_AHBEN, 17U), /*!< GPIOA clock */ + RCU_GPIOB = RCU_REGIDX_BIT(IDX_AHBEN, 18U), /*!< GPIOB clock */ + RCU_GPIOC = RCU_REGIDX_BIT(IDX_AHBEN, 19U), /*!< GPIOC clock */ + RCU_GPIOD = RCU_REGIDX_BIT(IDX_AHBEN, 20U), /*!< GPIOD clock */ + RCU_GPIOF = RCU_REGIDX_BIT(IDX_AHBEN, 22U), /*!< GPIOF clock */ + RCU_TSI = RCU_REGIDX_BIT(IDX_AHBEN, 24U), /*!< TSI clock */ + + /* APB2 peripherals */ + RCU_CFGCMP = RCU_REGIDX_BIT(IDX_APB2EN, 0U), /*!< CFGCMP clock */ + RCU_ADC = RCU_REGIDX_BIT(IDX_APB2EN, 9U), /*!< ADC clock */ + RCU_TIMER0 = RCU_REGIDX_BIT(IDX_APB2EN, 11U), /*!< TIMER0 clock */ + RCU_SPI0 = RCU_REGIDX_BIT(IDX_APB2EN, 12U), /*!< SPI0 clock */ + RCU_USART0 = RCU_REGIDX_BIT(IDX_APB2EN, 14U), /*!< USART0 clock */ + RCU_TIMER14 = RCU_REGIDX_BIT(IDX_APB2EN, 16U), /*!< TIMER14 clock */ + RCU_TIMER15 = RCU_REGIDX_BIT(IDX_APB2EN, 17U), /*!< TIMER15 clock */ + RCU_TIMER16 = RCU_REGIDX_BIT(IDX_APB2EN, 18U), /*!< TIMER16 clock */ + + /* APB1 peripherals */ + RCU_TIMER1 = RCU_REGIDX_BIT(IDX_APB1EN, 0U), /*!< TIMER1 clock */ + RCU_TIMER2 = RCU_REGIDX_BIT(IDX_APB1EN, 1U), /*!< TIMER2 clock */ + RCU_TIMER13 = RCU_REGIDX_BIT(IDX_APB1EN, 8U), /*!< TIMER13 clock */ + RCU_WWDGT = RCU_REGIDX_BIT(IDX_APB1EN, 11U), /*!< WWDGT clock */ + RCU_SPI1 = RCU_REGIDX_BIT(IDX_APB1EN, 14U), /*!< SPI1 clock */ + RCU_USART1 = RCU_REGIDX_BIT(IDX_APB1EN, 17U), /*!< USART1 clock */ + RCU_I2C0 = RCU_REGIDX_BIT(IDX_APB1EN, 21U), /*!< I2C0 clock */ + RCU_I2C1 = RCU_REGIDX_BIT(IDX_APB1EN, 22U), /*!< I2C1 clock */ + RCU_PMU = RCU_REGIDX_BIT(IDX_APB1EN, 28U), /*!< PMU clock */ +#if defined(GD32F350) + RCU_DAC = RCU_REGIDX_BIT(IDX_APB1EN, 29U), /*!< DAC clock */ + RCU_CEC = RCU_REGIDX_BIT(IDX_APB1EN, 30U), /*!< CEC clock */ + RCU_TIMER5 = RCU_REGIDX_BIT(IDX_APB1EN, 4U), /*!< TIMER5 clock */ + RCU_USBFS = RCU_REGIDX_BIT(IDX_AHBEN, 12U), /*!< USBFS clock */ +#endif /* GD32F350 */ + RCU_RTC = RCU_REGIDX_BIT(IDX_BDCTL, 15U), /*!< RTC clock */ + + /* RCU_ADDAPB1EN */ + RCU_CTC = RCU_REGIDX_BIT(IDX_ADDAPB1EN, 27U) /*!< CTC clock */ +} rcu_periph_enum; + +/* peripheral clock enable when sleep mode*/ +typedef enum { + /* AHB peripherals */ + RCU_SRAM_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 2U), /*!< SRAM clock */ + RCU_FMC_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 4U), /*!< FMC clock */ +} rcu_periph_sleep_enum; + +/* peripherals reset */ +typedef enum { + /* AHB peripherals reset */ + RCU_GPIOARST = RCU_REGIDX_BIT(IDX_AHBRST, 17U), /*!< GPIOA reset */ + RCU_GPIOBRST = RCU_REGIDX_BIT(IDX_AHBRST, 18U), /*!< GPIOB reset */ + RCU_GPIOCRST = RCU_REGIDX_BIT(IDX_AHBRST, 19U), /*!< GPIOC reset */ + RCU_GPIODRST = RCU_REGIDX_BIT(IDX_AHBRST, 20U), /*!< GPIOD reset */ + RCU_GPIOFRST = RCU_REGIDX_BIT(IDX_AHBRST, 22U), /*!< GPIOF reset */ + RCU_TSIRST = RCU_REGIDX_BIT(IDX_AHBRST, 24U), /*!< TSI reset */ + + /* APB2 peripherals reset */ + RCU_CFGCMPRST = RCU_REGIDX_BIT(IDX_APB2RST, 0U), /*!< CFGCMP reset */ + RCU_ADCRST = RCU_REGIDX_BIT(IDX_APB2RST, 9U), /*!< ADC reset */ + RCU_TIMER0RST = RCU_REGIDX_BIT(IDX_APB2RST, 11U), /*!< TIMER0 reset */ + RCU_SPI0RST = RCU_REGIDX_BIT(IDX_APB2RST, 12U), /*!< SPI0 reset */ + RCU_USART0RST = RCU_REGIDX_BIT(IDX_APB2RST, 14U), /*!< USART0 reset */ + RCU_TIMER14RST = RCU_REGIDX_BIT(IDX_APB2RST, 16U), /*!< TIMER14 reset */ + RCU_TIMER15RST = RCU_REGIDX_BIT(IDX_APB2RST, 17U), /*!< TIMER15 reset */ + RCU_TIMER16RST = RCU_REGIDX_BIT(IDX_APB2RST, 18U), /*!< TIMER16 reset */ + + /* APB1 peripherals reset */ + RCU_TIMER1RST = RCU_REGIDX_BIT(IDX_APB1RST, 0U), /*!< TIMER1 reset */ + RCU_TIMER2RST = RCU_REGIDX_BIT(IDX_APB1RST, 1U), /*!< TIMER2 reset */ + RCU_TIMER13RST = RCU_REGIDX_BIT(IDX_APB1RST, 8U), /*!< TIMER13 reset */ + RCU_WWDGTRST = RCU_REGIDX_BIT(IDX_APB1RST, 11U), /*!< WWDGT reset */ + RCU_SPI1RST = RCU_REGIDX_BIT(IDX_APB1RST, 14U), /*!< SPI1 reset */ + RCU_USART1RST = RCU_REGIDX_BIT(IDX_APB1RST, 17U), /*!< USART1 reset */ + RCU_I2C0RST = RCU_REGIDX_BIT(IDX_APB1RST, 21U), /*!< I2C0 reset */ + RCU_I2C1RST = RCU_REGIDX_BIT(IDX_APB1RST, 22U), /*!< I2C1 reset */ + RCU_PMURST = RCU_REGIDX_BIT(IDX_APB1RST, 28U), /*!< PMU reset */ +#if defined(GD32F350) + RCU_DACRST = RCU_REGIDX_BIT(IDX_APB1RST, 29U), /*!< DAC reset */ + RCU_CECRST = RCU_REGIDX_BIT(IDX_APB1RST, 30U), /*!< CEC reset */ + RCU_TIMER5RST = RCU_REGIDX_BIT(IDX_APB1RST, 4U), /*!< TIMER5 reset */ + RCU_USBFSRST = RCU_REGIDX_BIT(IDX_AHBRST, 12U), /*!< USBFS reset */ +#endif /* GD32F350 */ + /* RCU_ADDAPB1RST */ + RCU_CTCRST = RCU_REGIDX_BIT(IDX_ADDAPB1RST, 27U), /*!< CTC reset */ +} rcu_periph_reset_enum; + +/* clock stabilization and peripheral reset flags */ +typedef enum { + RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_RSTSCK, 1U), /*!< IRC40K stabilization flags */ + RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_BDCTL, 1U), /*!< LXTAL stabilization flags */ + RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_CTL0, 1U), /*!< IRC8M stabilization flags */ + RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_CTL0, 17U), /*!< HXTAL stabilization flags */ + RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_CTL0, 25U), /*!< PLL stabilization flags */ + RCU_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_CTL1, 1U), /*!< IRC28M stabilization flags */ + RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDCTL, 17U), /*!< IRC48M stabilization flags */ + + RCU_FLAG_V12RST = RCU_REGIDX_BIT(IDX_RSTSCK, 23U), /*!< V12 reset flags */ + RCU_FLAG_OBLRST = RCU_REGIDX_BIT(IDX_RSTSCK, 25U), /*!< OBL reset flags */ + RCU_FLAG_EPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 26U), /*!< EPR reset flags */ + RCU_FLAG_PORRST = RCU_REGIDX_BIT(IDX_RSTSCK, 27U), /*!< power reset flags */ + RCU_FLAG_SWRST = RCU_REGIDX_BIT(IDX_RSTSCK, 28U), /*!< SW reset flags */ + RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 29U), /*!< FWDGT reset flags */ + RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 30U), /*!< WWDGT reset flags */ + RCU_FLAG_LPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 31U) /*!< LP reset flags */ +} rcu_flag_enum; + +/* clock stabilization and ckm interrupt flags */ +typedef enum { + RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 0U), /*!< IRC40K stabilization interrupt flag */ + RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 1U), /*!< LXTAL stabilization interrupt flag */ + RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 2U), /*!< IRC8M stabilization interrupt flag */ + RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 3U), /*!< HXTAL stabilization interrupt flag */ + RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 4U), /*!< PLL stabilization interrupt flag */ + RCU_INT_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 5U), /*!< IRC28M stabilization interrupt flag */ + RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(IDX_INT, 7U), /*!< CKM interrupt flag */ + RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDINT, 6U) /*!< IRC48M stabilization interrupt flag */ +} rcu_int_flag_enum; + +/* clock stabilization and stuck interrupt flags clear */ +typedef enum { + RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 16U), /*!< IRC40K stabilization interrupt flags clear */ + RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 17U), /*!< LXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 18U), /*!< IRC8M stabilization interrupt flags clear */ + RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 19U), /*!< HXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 20U), /*!< PLL stabilization interrupt flags clear */ + RCU_INT_FLAG_IRC28MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 21U), /*!< IRC28M stabilization interrupt flags clear */ + RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(IDX_INT, 23U), /*!< CKM interrupt flags clear */ + RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(IDX_ADDINT, 22U) /*!< IRC48M stabilization interrupt flag clear */ +} rcu_int_flag_clear_enum; + +/* clock stabilization interrupt enable or disable */ +typedef enum { + RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 8U), /*!< IRC40K stabilization interrupt */ + RCU_INT_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 9U), /*!< LXTAL stabilization interrupt */ + RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 10U), /*!< IRC8M stabilization interrupt */ + RCU_INT_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 11U), /*!< HXTAL stabilization interrupt */ + RCU_INT_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 12U), /*!< PLL stabilization interrupt */ + RCU_INT_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 13U), /*!< IRC28M stabilization interrupt */ + RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDINT, 14U) /*!< IRC48M stabilization interrupt */ +} rcu_int_enum; + +/* ADC clock source */ +typedef enum { + RCU_ADCCK_IRC28M_DIV2 = 0U, /*!< ADC clock source select IRC28M/2 */ + RCU_ADCCK_IRC28M, /*!< ADC clock source select IRC28M */ + RCU_ADCCK_APB2_DIV2, /*!< ADC clock source select APB2/2 */ + RCU_ADCCK_AHB_DIV3, /*!< ADC clock source select AHB/3 */ + RCU_ADCCK_APB2_DIV4, /*!< ADC clock source select APB2/4 */ + RCU_ADCCK_AHB_DIV5, /*!< ADC clock source select AHB/5 */ + RCU_ADCCK_APB2_DIV6, /*!< ADC clock source select APB2/6 */ + RCU_ADCCK_AHB_DIV7, /*!< ADC clock source select AHB/7 */ + RCU_ADCCK_APB2_DIV8, /*!< ADC clock source select APB2/8 */ + RCU_ADCCK_AHB_DIV9 /*!< ADC clock source select AHB/9 */ +} rcu_adc_clock_enum; + +/* oscillator types */ +typedef enum { + RCU_HXTAL = RCU_REGIDX_BIT(IDX_CTL0, 16U), /*!< HXTAL */ + RCU_LXTAL = RCU_REGIDX_BIT(IDX_BDCTL, 0U), /*!< LXTAL */ + RCU_IRC8M = RCU_REGIDX_BIT(IDX_CTL0, 0U), /*!< IRC8M */ + RCU_IRC28M = RCU_REGIDX_BIT(IDX_CTL1, 0U), /*!< IRC28M */ + RCU_IRC48M = RCU_REGIDX_BIT(IDX_ADDCTL, 16U), /*!< IRC48M */ + RCU_IRC40K = RCU_REGIDX_BIT(IDX_RSTSCK, 0U), /*!< IRC40K */ + RCU_PLL_CK = RCU_REGIDX_BIT(IDX_CTL0, 24U) /*!< PLL */ +} rcu_osci_type_enum; + +/* rcu clock frequency */ +typedef enum { + CK_SYS = 0U, /*!< system clock */ + CK_AHB, /*!< AHB clock */ + CK_APB1, /*!< APB1 clock */ + CK_APB2, /*!< APB2 clock */ + CK_ADC, /*!< ADC clock */ + CK_CEC, /*!< CEC clock */ + CK_USART /*!< USART clock */ +} rcu_clock_freq_enum; + +/* system clock source select */ +#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ +#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ +#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ + +/* system clock source select status */ +#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ +#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ +#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLL */ + +/* AHB prescaler selection */ +#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ +#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ +#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ +#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ +#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ +#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ +#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ +#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ +#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ + +/* APB1 prescaler selection */ +#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) +#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ +#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ +#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ +#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ +#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ + +/* APB2 prescaler selection */ +#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) +#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ +#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ +#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ +#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ +#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ + +/* ADC clock prescaler selection */ +#define CFG0_ADCPSC(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) +#define RCU_ADC_CKAPB2_DIV2 CFG0_ADCPSC(0) /*!< ADC clock prescaler select CK_APB2/2 */ +#define RCU_ADC_CKAPB2_DIV4 CFG0_ADCPSC(1) /*!< ADC clock prescaler select CK_APB2/4 */ +#define RCU_ADC_CKAPB2_DIV6 CFG0_ADCPSC(2) /*!< ADC clock prescaler select CK_APB2/6 */ +#define RCU_ADC_CKAPB2_DIV8 CFG0_ADCPSC(3) /*!< ADC clock prescaler select CK_APB2/8 */ + +/* PLL clock source selection */ +#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< PLL clock source select IRC8M/2 */ +#define RCU_PLLSRC_HXTAL_IRC48M RCU_CFG0_PLLSEL /*!< PLL clock source select HXTAL or IRC48M*/ + +/* PLL clock source preselection */ +#define RCU_PLLPRESEL_HXTAL ((uint32_t)0x00000000U) /*!< PLL clock source preselection HXTAL */ +#define RCU_PLLPRESEL_IRC48M RCU_CFG1_PLLPRESEL /*!< PLL clock source preselection IRC48M */ + +/* HXTAL or IRC48M divider for PLL source clock selection */ +#define RCU_PLLPREDV ((uint32_t)0x00000000U) /*!< HXTAL or IRC48M clock selected */ +#define RCU_PLLPREDV_DIV2 RCU_CFG0_PLLPREDV /*!< (HXTAL or IRC48M) /2 clock selected */ + +/* PLL multiply factor */ +#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) +#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ +#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ +#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ +#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ +#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ +#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ +#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ +#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ +#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ +#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ +#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ +#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ +#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ +#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */ +#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ +#define RCU_PLL_MUL17 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ +#define RCU_PLL_MUL18 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ +#define RCU_PLL_MUL19 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ +#define RCU_PLL_MUL20 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ +#define RCU_PLL_MUL21 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ +#define RCU_PLL_MUL22 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ +#define RCU_PLL_MUL23 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ +#define RCU_PLL_MUL24 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ +#define RCU_PLL_MUL25 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ +#define RCU_PLL_MUL26 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ +#define RCU_PLL_MUL27 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ +#define RCU_PLL_MUL28 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ +#define RCU_PLL_MUL29 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ +#define RCU_PLL_MUL30 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ +#define RCU_PLL_MUL31 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ +#define RCU_PLL_MUL32 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ +#define RCU_PLL_MUL33 (CFG0_PLLMF(0) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 33 */ +#define RCU_PLL_MUL34 (CFG0_PLLMF(1) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 34 */ +#define RCU_PLL_MUL35 (CFG0_PLLMF(2) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 35 */ +#define RCU_PLL_MUL36 (CFG0_PLLMF(3) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 36 */ +#define RCU_PLL_MUL37 (CFG0_PLLMF(4) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 37 */ +#define RCU_PLL_MUL38 (CFG0_PLLMF(5) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 38 */ +#define RCU_PLL_MUL39 (CFG0_PLLMF(6) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 39 */ +#define RCU_PLL_MUL40 (CFG0_PLLMF(7) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 40 */ +#define RCU_PLL_MUL41 (CFG0_PLLMF(8) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 41 */ +#define RCU_PLL_MUL42 (CFG0_PLLMF(9) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 42 */ +#define RCU_PLL_MUL43 (CFG0_PLLMF(10) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 43 */ +#define RCU_PLL_MUL44 (CFG0_PLLMF(11) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 44 */ +#define RCU_PLL_MUL45 (CFG0_PLLMF(12) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 45 */ +#define RCU_PLL_MUL46 (CFG0_PLLMF(13) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 46 */ +#define RCU_PLL_MUL47 (CFG0_PLLMF(14) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 47 */ +#define RCU_PLL_MUL48 (CFG0_PLLMF(15) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 48 */ +#define RCU_PLL_MUL49 (RCU_CFG0_PLLMF4 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 49 */ +#define RCU_PLL_MUL50 (RCU_PLL_MUL18 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 50 */ +#define RCU_PLL_MUL51 (RCU_PLL_MUL19 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 51 */ +#define RCU_PLL_MUL52 (RCU_PLL_MUL20 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 52 */ +#define RCU_PLL_MUL53 (RCU_PLL_MUL21 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 53 */ +#define RCU_PLL_MUL54 (RCU_PLL_MUL22 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 54 */ +#define RCU_PLL_MUL55 (RCU_PLL_MUL23 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 55 */ +#define RCU_PLL_MUL56 (RCU_PLL_MUL24 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 56 */ +#define RCU_PLL_MUL57 (RCU_PLL_MUL25 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 57 */ +#define RCU_PLL_MUL58 (RCU_PLL_MUL26 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 58 */ +#define RCU_PLL_MUL59 (RCU_PLL_MUL27 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 59 */ +#define RCU_PLL_MUL60 (RCU_PLL_MUL28 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 60 */ +#define RCU_PLL_MUL61 (RCU_PLL_MUL29 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 61 */ +#define RCU_PLL_MUL62 (RCU_PLL_MUL30 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 62 */ +#define RCU_PLL_MUL63 (RCU_PLL_MUL31 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 63 */ +#define RCU_PLL_MUL64 (RCU_PLL_MUL32 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 64 */ + +/* USBFS clock prescaler selection */ +#define CFG0_USBFSPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) +#define RCU_USBFS_CKPLL_DIV1_5 CFG0_USBFSPSC(0) /*!< USBFS clock prescaler select CK_PLL/1.5 */ +#define RCU_USBFS_CKPLL_DIV1 CFG0_USBFSPSC(1) /*!< USBFS clock prescaler select CK_PLL */ +#define RCU_USBFS_CKPLL_DIV2_5 CFG0_USBFSPSC(2) /*!< USBFS clock prescaler select CK_PLL/2.5 */ +#define RCU_USBFS_CKPLL_DIV2 CFG0_USBFSPSC(3) /*!< USBFS clock prescaler select CK_PLL/2 */ +#define RCU_USBFS_CKPLL_DIV3 RCU_CFG2_USBFSPSC2 /*!< USBFS clock prescaler select CK_PLL/3 */ +#define RCU_USBFS_CKPLL_DIV3_5 (CFG0_USBFSPSC(1)|RCU_CFG2_USBFSPSC2) /*!< USBFS clock prescaler select CK_PLL/3.5 */ + +/* CK_OUT clock source selection */ +#define CFG0_CKOUTSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) +#define RCU_CKOUTSRC_NONE CFG0_CKOUTSEL(0) /*!< no clock selected */ +#define RCU_CKOUTSRC_IRC28M CFG0_CKOUTSEL(1) /*!< CK_OUT clock source select IRC28M */ +#define RCU_CKOUTSRC_IRC40K CFG0_CKOUTSEL(2) /*!< CK_OUT clock source select IRC40K */ +#define RCU_CKOUTSRC_LXTAL CFG0_CKOUTSEL(3) /*!< CK_OUT clock source select LXTAL */ +#define RCU_CKOUTSRC_CKSYS CFG0_CKOUTSEL(4) /*!< CK_OUT clock source select CKSYS */ +#define RCU_CKOUTSRC_IRC8M CFG0_CKOUTSEL(5) /*!< CK_OUT clock source select IRC8M */ +#define RCU_CKOUTSRC_HXTAL CFG0_CKOUTSEL(6) /*!< CK_OUT clock source select HXTAL */ +#define RCU_CKOUTSRC_CKPLL_DIV1 (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7)) /*!< CK_OUT clock source select CK_PLL */ +#define RCU_CKOUTSRC_CKPLL_DIV2 CFG0_CKOUTSEL(7) /*!< CK_OUT clock source select CK_PLL/2 */ + +/* CK_OUT divider */ +#define CFG0_CKOUTDIV(regval) (BITS(28,30) & ((uint32_t)(regval) << 28)) +#define RCU_CKOUT_DIV1 CFG0_CKOUTDIV(0) /*!< CK_OUT is divided by 1 */ +#define RCU_CKOUT_DIV2 CFG0_CKOUTDIV(1) /*!< CK_OUT is divided by 2 */ +#define RCU_CKOUT_DIV4 CFG0_CKOUTDIV(2) /*!< CK_OUT is divided by 4 */ +#define RCU_CKOUT_DIV8 CFG0_CKOUTDIV(3) /*!< CK_OUT is divided by 8 */ +#define RCU_CKOUT_DIV16 CFG0_CKOUTDIV(4) /*!< CK_OUT is divided by 16 */ +#define RCU_CKOUT_DIV32 CFG0_CKOUTDIV(5) /*!< CK_OUT is divided by 32 */ +#define RCU_CKOUT_DIV64 CFG0_CKOUTDIV(6) /*!< CK_OUT is divided by 64 */ +#define RCU_CKOUT_DIV128 CFG0_CKOUTDIV(7) /*!< CK_OUT is divided by 128 */ + +/* CK_PLL divide by 1 or 2 for CK_OUT */ +#define RCU_PLLDV_CKPLL_DIV2 ((uint32_t)0x00000000U) /*!< CK_PLL divide by 2 for CK_OUT */ +#define RCU_PLLDV_CKPLL RCU_CFG0_PLLDV /*!< CK_PLL divide by 1 for CK_OUT */ + +/* LXTAL drive capability */ +#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) +#define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ +#define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ +#define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ +#define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ + +/* RTC clock entry selection */ +#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ +#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< LXTAL selected as RTC source clock */ +#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< IRC40K selected as RTC source clock */ +#define RCU_RTCSRC_HXTAL_DIV32 BDCTL_RTCSRC(3) /*!< HXTAL/32 selected as RTC source clock */ + +/* CK_HXTAL divider previous PLL */ +#define CFG1_PREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define RCU_PLL_PREDV1 CFG1_PREDV(0) /*!< PLL not divided */ +#define RCU_PLL_PREDV2 CFG1_PREDV(1) /*!< PLL divided by 2 */ +#define RCU_PLL_PREDV3 CFG1_PREDV(2) /*!< PLL divided by 3 */ +#define RCU_PLL_PREDV4 CFG1_PREDV(3) /*!< PLL divided by 4 */ +#define RCU_PLL_PREDV5 CFG1_PREDV(4) /*!< PLL divided by 5 */ +#define RCU_PLL_PREDV6 CFG1_PREDV(5) /*!< PLL divided by 6 */ +#define RCU_PLL_PREDV7 CFG1_PREDV(6) /*!< PLL divided by 7 */ +#define RCU_PLL_PREDV8 CFG1_PREDV(7) /*!< PLL divided by 8 */ +#define RCU_PLL_PREDV9 CFG1_PREDV(8) /*!< PLL divided by 9 */ +#define RCU_PLL_PREDV10 CFG1_PREDV(9) /*!< PLL divided by 10 */ +#define RCU_PLL_PREDV11 CFG1_PREDV(10) /*!< PLL divided by 11 */ +#define RCU_PLL_PREDV12 CFG1_PREDV(11) /*!< PLL divided by 12 */ +#define RCU_PLL_PREDV13 CFG1_PREDV(12) /*!< PLL divided by 13 */ +#define RCU_PLL_PREDV14 CFG1_PREDV(13) /*!< PLL divided by 14 */ +#define RCU_PLL_PREDV15 CFG1_PREDV(14) /*!< PLL divided by 15 */ +#define RCU_PLL_PREDV16 CFG1_PREDV(15) /*!< PLL divided by 16 */ + +/* USART0 clock source selection */ +#define CFG2_USART0SEL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_USART0SRC_CKAPB2 CFG2_USART0SEL(0) /*!< CK_USART0 select CK_APB2 */ +#define RCU_USART0SRC_CKSYS CFG2_USART0SEL(1) /*!< CK_USART0 select CK_SYS */ +#define RCU_USART0SRC_LXTAL CFG2_USART0SEL(2) /*!< CK_USART0 select LXTAL */ +#define RCU_USART0SRC_IRC8M CFG2_USART0SEL(3) /*!< CK_USART0 select IRC8M */ + +/* CEC clock source selection */ +#define RCU_CECSRC_IRC8M_DIV244 ((uint32_t)0x00000000U) /*!< CK_CEC clock source select IRC8M/244 */ +#define RCU_CECSRC_LXTAL RCU_CFG2_CECSEL /*!< CK_CEC clock source select LXTAL */ + +/* ADC clock source selection */ +#define RCU_ADCSRC_IRC28M ((uint32_t)0x00000000U) /*!< ADC clock source select */ +#define RCU_ADCSRC_AHB_APB2DIV RCU_CFG2_ADCSEL /*!< ADC clock source select */ + +/* IRC28M clock divider for ADC */ +#define RCU_ADC_IRC28M_DIV2 ((uint32_t)0x00000000U) /*!< IRC28M/2 select to ADC clock */ +#define RCU_ADC_IRC28M_DIV1 RCU_CFG2_IRC28MDIV /*!< IRC28M select to ADC clock */ + +/* CK48M clock source selection */ +#define RCU_CK48MSRC_PLL48M ((uint32_t)0x00000000U) /*!< CK48M source clock select PLL48M */ +#define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< CK48M source clock select IRC48M */ + +/* Deep-sleep mode voltage */ +#define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_DEEPSLEEP_V_0 DSV_DSLPVS(0) /*!< core voltage is default value in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_1 DSV_DSLPVS(1) /*!< core voltage is (default value-0.1)V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_2 DSV_DSLPVS(2) /*!< core voltage is (default value-0.2)V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_3 DSV_DSLPVS(3) /*!< core voltage is (default value-0.3)V in deep-sleep mode */ + +/* function declarations */ +/* deinitialize the RCU */ +void rcu_deinit(void); +/* enable the peripherals clock */ +void rcu_periph_clock_enable(rcu_periph_enum periph); +/* disable the peripherals clock */ +void rcu_periph_clock_disable(rcu_periph_enum periph); +/* enable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); +/* disable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); +/* reset the peripherals */ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); +/* disable reset the peripheral */ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); +/* reset the BKP */ +void rcu_bkp_reset_enable(void); +/* disable the BKP reset */ +void rcu_bkp_reset_disable(void); + +/* configure the system clock source */ +void rcu_system_clock_source_config(uint32_t ck_sys); +/* get the system clock source */ +uint32_t rcu_system_clock_source_get(void); +/* configure the AHB prescaler selection */ +void rcu_ahb_clock_config(uint32_t ck_ahb); +/* configure the APB1 prescaler selection */ +void rcu_apb1_clock_config(uint32_t ck_apb1); +/* configure the APB2 prescaler selection */ +void rcu_apb2_clock_config(uint32_t ck_apb2); +/* configure the ADC clock source and prescaler selection */ +void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc); +/* configure the USBFS prescaler selection */ +void rcu_usbfs_clock_config(uint32_t ck_usbfs); +/* configure the CK_OUT clock source and divider */ +void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div); + +/* configure the PLL clock source preselection */ +void rcu_pll_preselection_config(uint32_t pll_presel); +/* configure the PLL clock source selection and PLL multiply factor */ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); +/* configure the USART clock source selection */ +void rcu_usart_clock_config(uint32_t ck_usart); +/* configure the CEC clock source selection */ +void rcu_cec_clock_config(uint32_t ck_cec); +/* configure the RTC clock source selection */ +void rcu_rtc_clock_config(uint32_t rtc_clock_source); +/* configure the CK48M clock selection */ +void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); +/* configure the HXTAL divider used as input of PLL */ +void rcu_hxtal_prediv_config(uint32_t hxtal_prediv); +/* configure the LXTAL drive capability */ +void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); + +/* get the clock stabilization and periphral reset flags */ +FlagStatus rcu_flag_get(rcu_flag_enum flag); +/* clear the reset flag */ +void rcu_all_reset_flag_clear(void); +/* get the clock stabilization interrupt and ckm flags */ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); +/* clear the interrupt flags */ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); +/* enable the stabilization interrupt */ +void rcu_interrupt_enable(rcu_int_enum stab_int); +/* disable the stabilization interrupt */ +void rcu_interrupt_disable(rcu_int_enum stab_int); + +/* wait until oscillator stabilization flags is SET */ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); +/* turn on the oscillator */ +void rcu_osci_on(rcu_osci_type_enum osci); +/* turn off the oscillator */ +void rcu_osci_off(rcu_osci_type_enum osci); +/* enable the oscillator bypass mode */ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); +/* disable the oscillator bypass mode */ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); +/* enable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_enable(void); +/* disable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_disable(void); + +/* set the IRC8M adjust value */ +void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval); +/* set the IRC28M adjust value */ +void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval); +/* unlock the voltage key */ +void rcu_voltage_key_unlock(void); +/* set the deep sleep mode voltage */ +void rcu_deepsleep_voltage_set(uint32_t dsvol); + +/* get the system clock, bus and peripheral clock frequency */ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); + +#endif /* GD32F3X0_RCU_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_rtc.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_rtc.h new file mode 100644 index 000000000..7df0ebf5d --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_rtc.h @@ -0,0 +1,559 @@ +/*! + \file gd32f3x0_rtc.h + \brief definitions for the RTC + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_RTC_H +#define GD32F3X0_RTC_H + +#include "gd32f3x0.h" + +/* RTC definitions */ +#define RTC RTC_BASE + +/* registers definitions */ +#define RTC_TIME REG32(RTC + 0x00000000U) /*!< RTC time of day register */ +#define RTC_DATE REG32(RTC + 0x00000004U) /*!< RTC date register */ +#define RTC_CTL REG32(RTC + 0x00000008U) /*!< RTC control register */ +#define RTC_STAT REG32(RTC + 0x0000000CU) /*!< RTC status register */ +#define RTC_PSC REG32(RTC + 0x00000010U) /*!< RTC time prescaler register */ +#define RTC_ALRM0TD REG32(RTC + 0x0000001CU) /*!< RTC alarm 0 time and date register */ +#define RTC_WPK REG32(RTC + 0x00000024U) /*!< RTC write protection key register */ +#define RTC_SS REG32(RTC + 0x00000028U) /*!< RTC sub second register */ +#define RTC_SHIFTCTL REG32(RTC + 0x0000002CU) /*!< RTC shift function control register */ +#define RTC_TTS REG32(RTC + 0x00000030U) /*!< RTC time of timestamp register */ +#define RTC_DTS REG32(RTC + 0x00000034U) /*!< RTC date of timestamp register */ +#define RTC_SSTS REG32(RTC + 0x00000038U) /*!< RTC sub second of timestamp register */ +#define RTC_HRFC REG32(RTC + 0x0000003CU) /*!< RTC high resolution frequency compensation registor */ +#define RTC_TAMP REG32(RTC + 0x00000040U) /*!< RTC tamper register */ +#define RTC_ALRM0SS REG32(RTC + 0x00000044U) /*!< RTC alarm 0 sub second register */ +#define RTC_BKP0 REG32(RTC + 0x00000050U) /*!< RTC backup 0 register */ +#define RTC_BKP1 REG32(RTC + 0x00000054U) /*!< RTC backup 1 register */ +#define RTC_BKP2 REG32(RTC + 0x00000058U) /*!< RTC backup 2 register */ +#define RTC_BKP3 REG32(RTC + 0x0000005CU) /*!< RTC backup 3 register */ +#define RTC_BKP4 REG32(RTC + 0x00000060U) /*!< RTC backup 4 register */ + +/* bits definitions */ +/* RTC_TIME */ +#define RTC_TIME_SCU BITS(0,3) /*!< second units in BCD code */ +#define RTC_TIME_SCT BITS(4,6) /*!< second tens in BCD code */ +#define RTC_TIME_MNU BITS(8,11) /*!< minute units in BCD code */ +#define RTC_TIME_MNT BITS(12,14) /*!< minute tens in BCD code */ +#define RTC_TIME_HRU BITS(16,19) /*!< hour units in BCD code */ +#define RTC_TIME_HRT BITS(20,21) /*!< hour tens in BCD code */ +#define RTC_TIME_PM BIT(22) /*!< AM/PM notation */ + +/* RTC_DATE */ +#define RTC_DATE_DAYU BITS(0,3) /*!< date units in BCD code */ +#define RTC_DATE_DAYT BITS(4,5) /*!< date tens in BCD code */ +#define RTC_DATE_MONU BITS(8,11) /*!< month units in BCD code */ +#define RTC_DATE_MONT BIT(12) /*!< month tens in BCD code */ +#define RTC_DATE_DOW BITS(13,15) /*!< day of week units */ +#define RTC_DATE_YRU BITS(16,19) /*!< year units in BCD code */ +#define RTC_DATE_YRT BITS(20,23) /*!< year tens in BCD code */ + +/* RTC_CTL */ +#define RTC_CTL_TSEG BIT(3) /*!< valid event edge of time-stamp */ +#define RTC_CTL_REFEN BIT(4) /*!< reference clock detection function enable */ +#define RTC_CTL_BPSHAD BIT(5) /*!< shadow registers bypass control */ +#define RTC_CTL_CS BIT(6) /*!< display format of clock system */ +#define RTC_CTL_ALRM0EN BIT(8) /*!< alarm function enable */ +#define RTC_CTL_TSEN BIT(11) /*!< time-stamp function enable */ +#define RTC_CTL_ALRM0IE BIT(12) /*!< RTC alarm interrupt enable */ +#define RTC_CTL_TSIE BIT(15) /*!< time-stamp interrupt enable */ +#define RTC_CTL_A1H BIT(16) /*!< add 1 hour(summer time change) */ +#define RTC_CTL_S1H BIT(17) /*!< subtract 1 hour(winter time change) */ +#define RTC_CTL_DSM BIT(18) /*!< daylight saving mark */ +#define RTC_CTL_COS BIT(19) /*!< calibration output selection */ +#define RTC_CTL_OPOL BIT(20) /*!< output polarity */ +#define RTC_CTL_OS BITS(21,22) /*!< output selection */ +#define RTC_CTL_COEN BIT(23) /*!< calibration output enable */ + +/* RTC_STAT */ +#define RTC_STAT_ALRM0WF BIT(0) /*!< alarm configuration can be write flag */ +#define RTC_STAT_SOPF BIT(3) /*!< shift function operation pending flag */ +#define RTC_STAT_YCM BIT(4) /*!< year configuration mark status flag */ +#define RTC_STAT_RSYNF BIT(5) /*!< register synchronization flag */ +#define RTC_STAT_INITF BIT(6) /*!< initialization state flag */ +#define RTC_STAT_INITM BIT(7) /*!< enter initialization mode */ +#define RTC_STAT_ALRM0F BIT(8) /*!< alarm occurs flag */ +#define RTC_STAT_TSF BIT(11) /*!< time-stamp flag */ +#define RTC_STAT_TSOVRF BIT(12) /*!< time-stamp overflow flag */ +#define RTC_STAT_TP0F BIT(13) /*!< RTC tamp 0 detected flag */ +#define RTC_STAT_TP1F BIT(14) /*!< RTC tamp 1 detected flag */ +#define RTC_STAT_SCPF BIT(16) /*!< recalibration pending flag */ + +/* RTC_PSC */ +#define RTC_PSC_FACTOR_S BITS(0,14) /*!< synchronous prescaler factor */ +#define RTC_PSC_FACTOR_A BITS(16,22) /*!< asynchronous prescaler factor */ + +/* RTC_ALRM0TD */ +#define RTC_ALRM0TD_SCU BITS(0,3) /*!< second units in BCD code */ +#define RTC_ALRM0TD_SCT BITS(4,6) /*!< second tens in BCD code */ +#define RTC_ALRM0TD_MSKS BIT(7) /*!< alarm second mask bit */ +#define RTC_ALRM0TD_MNU BITS(8,11) /*!< minutes units in BCD code */ +#define RTC_ALRM0TD_MNT BITS(12,14) /*!< minutes tens in BCD code */ +#define RTC_ALRM0TD_MSKM BIT(15) /*!< alarm minutes mask bit */ +#define RTC_ALRM0TD_HRU BITS(16,19) /*!< hour units in BCD code */ +#define RTC_ALRM0TD_HRT BITS(20,21) /*!< hour units in BCD code */ +#define RTC_ALRM0TD_PM BIT(22) /*!< AM/PM flag */ +#define RTC_ALRM0TD_MSKH BIT(23) /*!< alarm hour mask bit */ +#define RTC_ALRM0TD_DAYU BITS(24,27) /*!< date units or week day in BCD code */ +#define RTC_ALRM0TD_DAYT BITS(28,29) /*!< date tens in BCD code */ +#define RTC_ALRM0TD_DOWS BIT(30) /*!< day of week selection */ +#define RTC_ALRM0TD_MSKD BIT(31) /*!< alarm date mask bit */ + +/* RTC_WPK */ +#define RTC_WPK_WPK BITS(0,7) /*!< key for write protection */ + +/* RTC_SS */ +#define RTC_SS_SSC BITS(0,15) /*!< sub second value */ + +/* RTC_SHIFTCTL */ +#define RTC_SHIFTCTL_SFS BITS(0,14) /*!< subtract a fraction of a second */ +#define RTC_SHIFTCTL_A1S BIT(31) /*!< one second add */ + +/* RTC_TTS */ +#define RTC_TTS_SCU BITS(0,3) /*!< second units in BCD code */ +#define RTC_TTS_SCT BITS(4,6) /*!< second units in BCD code */ +#define RTC_TTS_MNU BITS(8,11) /*!< minute units in BCD code */ +#define RTC_TTS_MNT BITS(12,14) /*!< minute tens in BCD code */ +#define RTC_TTS_HRU BITS(16,19) /*!< hour units in BCD code */ +#define RTC_TTS_HRT BITS(20,21) /*!< hour tens in BCD code */ +#define RTC_TTS_PM BIT(22) /*!< AM/PM notation */ + +/* RTC_DTS */ +#define RTC_DTS_DAYU BITS(0,3) /*!< date units in BCD code */ +#define RTC_DTS_DAYT BITS(4,5) /*!< date tens in BCD code */ +#define RTC_DTS_MONU BITS(8,11) /*!< month units in BCD code */ +#define RTC_DTS_MONT BIT(12) /*!< month tens in BCD code */ +#define RTC_DTS_DOW BITS(13,15) /*!< day of week units */ + +/* RTC_SSTS */ +#define RTC_SSTS_SSC BITS(0,15) /*!< timestamp sub second units */ + +/* RTC_HRFC */ +#define RTC_HRFC_CMSK BITS(0,8) /*!< calibration mask number */ +#define RTC_HRFC_CWND16 BIT(13) /*!< calibration window select 16 seconds */ +#define RTC_HRFC_CWND8 BIT(14) /*!< calibration window select 16 seconds */ +#define RTC_HRFC_FREQI BIT(15) /*!< increase RTC frequency by 488.5ppm */ + +/* RTC_TAMP */ +#define RTC_TAMP_TP0EN BIT(0) /*!< tamper 0 detection enable */ +#define RTC_TAMP_TP0EG BIT(1) /*!< tamper 0 event trigger edge for RTC tamp 0 input */ +#define RTC_TAMP_TPIE BIT(2) /*!< tamper detection interrupt enable */ +#define RTC_TAMP_TP1EN BIT(3) /*!< tamper 1 detection enable */ +#define RTC_TAMP_TP1EG BIT(4) /*!< tamper 1 event trigger edge for RTC tamp 1 input */ +#define RTC_TAMP_TPTS BIT(7) /*!< make tamper function used for timestamp function */ +#define RTC_TAMP_FREQ BITS(8,10) /*!< sample frequency of tamper event detection */ +#define RTC_TAMP_FLT BITS(11,12) /*!< RTC tamp x filter count setting */ +#define RTC_TAMP_PRCH BITS(13,14) /*!< precharge duration time of RTC tamp x */ +#define RTC_TAMP_DISPU BIT(15) /*!< RTC tamp x pull up disable bit */ +#define RTC_TAMP_PC13VAL BIT(18) /*!< alarm output type control/PC13 output value */ +#define RTC_TAMP_PC13MDE BIT(19) /*!< PC13 mode */ +#define RTC_TAMP_PC14VAL BIT(20) /*!< PC14 output value */ +#define RTC_TAMP_PC14MDE BIT(21) /*!< PC14 mode */ +#define RTC_TAMP_PC15VAL BIT(22) /*!< PC15 output value */ +#define RTC_TAMP_PC15MDE BIT(23) /*!< PC15 mode */ + +/* RTC_ALRM0SS */ +#define RTC_ALRM0SS_SSC BITS(0,14) /*!< alarm sub second value */ +#define RTC_ALRM0SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */ + +/* RTC_BKP0 */ +#define RTC_BKP0_DATA BITS(0,31) /*!< backup domain registers */ + +/* RTC_BKP1 */ +#define RTC_BKP1_DATA BITS(0,31) /*!< backup domain registers */ + +/* RTC_BKP2 */ +#define RTC_BKP2_DATA BITS(0,31) /*!< backup domain registers */ + +/* RTC_BKP3 */ +#define RTC_BKP3_DATA BITS(0,31) /*!< backup domain registers */ + +/* RTC_BKP4 */ +#define RTC_BKP4_DATA BITS(0,31) /*!< backup domain registers */ + +/* constants definitions */ +/* structure for initialization of the RTC */ +typedef struct { + uint8_t rtc_year; /*!< RTC year value: 0x0 - 0x99(BCD format) */ + uint8_t rtc_month; /*!< RTC month value */ + uint8_t rtc_date; /*!< RTC date value: 0x1 - 0x31(BCD format) */ + uint8_t rtc_day_of_week; /*!< RTC weekday value */ + uint8_t rtc_hour; /*!< RTC hour value */ + uint8_t rtc_minute; /*!< RTC minute value: 0x0 - 0x59(BCD format) */ + uint8_t rtc_second; /*!< RTC second value: 0x0 - 0x59(BCD format) */ + uint16_t rtc_factor_asyn; /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */ + uint16_t rtc_factor_syn; /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */ + uint32_t rtc_am_pm; /*!< RTC AM/PM value */ + uint32_t rtc_display_format; /*!< RTC time notation */ +} rtc_parameter_struct; + +/* structure for RTC alarm configuration */ +typedef struct { + uint32_t rtc_alarm_mask; /*!< RTC alarm mask */ + uint32_t rtc_weekday_or_date; /*!< specify RTC alarm is on date or weekday */ + uint8_t rtc_alarm_day; /*!< RTC alarm date or weekday value*/ + uint8_t rtc_alarm_hour; /*!< RTC alarm hour value */ + uint8_t rtc_alarm_minute; /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */ + uint8_t rtc_alarm_second; /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */ + uint32_t rtc_am_pm; /*!< RTC alarm AM/PM value */ +} rtc_alarm_struct; + +/* structure for RTC time-stamp configuration */ +typedef struct { + uint8_t rtc_timestamp_month; /*!< RTC time-stamp month value */ + uint8_t rtc_timestamp_date; /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */ + uint8_t rtc_timestamp_day; /*!< RTC time-stamp weekday value */ + uint8_t rtc_timestamp_hour; /*!< RTC time-stamp hour value */ + uint8_t rtc_timestamp_minute; /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */ + uint8_t rtc_timestamp_second; /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */ + uint32_t rtc_am_pm; /*!< RTC time-stamp AM/PM value */ +} rtc_timestamp_struct; + +/* structure for RTC tamper configuration */ +typedef struct { + uint32_t rtc_tamper_source; /*!< RTC tamper source */ + uint32_t rtc_tamper_trigger; /*!< RTC tamper trigger */ + uint32_t rtc_tamper_filter; /*!< RTC tamper consecutive samples needed during a voltage level detection */ + uint32_t rtc_tamper_sample_frequency; /*!< RTC tamper sampling frequency during a voltage level detection */ + ControlStatus + rtc_tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */ + uint32_t rtc_tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */ + ControlStatus rtc_tamper_with_timestamp; /*!< RTC tamper time-stamp feature */ +} rtc_tamper_struct; + +/* time register value */ +#define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TIME_SC bit field */ +#define GET_TIME_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TIME_SC bit field */ + +#define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TIME_MN bit field */ +#define GET_TIME_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TIME_MN bit field */ + +#define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TIME_HR bit field */ +#define GET_TIME_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TIME_HR bit field */ + +#define RTC_AM ((uint32_t)0x00000000U) /*!< AM format */ +#define RTC_PM RTC_TIME_PM /*!< PM format */ + +/* date register value */ +#define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DATE_DAY bit field */ +#define GET_DATE_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DATE_DAY bit field */ + +#define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DATE_MON bit field */ +#define GET_DATE_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DATE_MON bit field */ +#define RTC_JAN ((uint8_t)0x01U) /*!< Janurary */ +#define RTC_FEB ((uint8_t)0x02U) /*!< February */ +#define RTC_MAR ((uint8_t)0x03U) /*!< March */ +#define RTC_APR ((uint8_t)0x04U) /*!< April */ +#define RTC_MAY ((uint8_t)0x05U) /*!< May */ +#define RTC_JUN ((uint8_t)0x06U) /*!< June */ +#define RTC_JUL ((uint8_t)0x07U) /*!< July */ +#define RTC_AUG ((uint8_t)0x08U) /*!< August */ +#define RTC_SEP ((uint8_t)0x09U) /*!< September */ +#define RTC_OCT ((uint8_t)0x10U) /*!< October */ +#define RTC_NOV ((uint8_t)0x11U) /*!< November */ +#define RTC_DEC ((uint8_t)0x12U) /*!< December */ + +#define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DATE_DOW bit field */ +#define GET_DATE_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DATE_DOW bit field */ +#define RTC_MONDAY ((uint8_t)0x01U) /*!< Monday */ +#define RTC_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */ +#define RTC_WEDSDAY ((uint8_t)0x03U) /*!< Wednesday */ +#define RTC_THURSDAY ((uint8_t)0x04U) /*!< Thursday */ +#define RTC_FRIDAY ((uint8_t)0x05U) /*!< Friday */ +#define RTC_SATURDAY ((uint8_t)0x06U) /*!< Saturday */ +#define RTC_SUNDAY ((uint8_t)0x07U) /*!< Sunday */ + +#define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_DATE_YR bit field */ +#define GET_DATE_YR(regval) GET_BITS((regval),16,23) /*!< get value of RTC_DATE_YR bit field */ + +/* ctl register value */ +#define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21U)) /*!< write value to RTC_CTL_OS bit field */ +#define RTC_OS_DISABLE CTL_OS(0) /*!< disable output RTC_ALARM */ +#define RTC_OS_ENABLE CTL_OS(1) /*!< enable alarm flag output */ + +#define RTC_CALIBRATION_512HZ RTC_CTL_COEN /*!< calibration output of 512Hz is enable */ +#define RTC_CALIBRATION_1HZ RTC_CTL_COEN | RTC_CTL_COS /*!< calibration output of 1Hz is enable */ +#define RTC_ALARM_HIGH RTC_OS_ENABLE /*!< enable alarm flag output with high level */ +#define RTC_ALARM_LOW RTC_OS_ENABLE | RTC_CTL_OPOL /*!< enable alarm flag output with low level*/ + +#define RTC_24HOUR ((uint32_t)0x00000000U) /*!< 24-hour format */ +#define RTC_12HOUR RTC_CTL_CS /*!< 12-hour format */ + +#define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U) /*!< rising edge is valid event edge for time-stamp event */ +#define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG /*!< falling edge is valid event edge for time-stamp event */ + +/* psc register value */ +#define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_PSC_FACTOR_S bit field */ +#define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14) /*!< get value of RTC_PSC_FACTOR_S bit field */ + +#define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_PSC_FACTOR_A bit field */ +#define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22) /*!< get value of RTC_PSC_FACTOR_A bit field */ + +/* alrm0td register value */ +#define ALRM0TD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0TD_SC bit field */ +#define GET_ALRM0TD_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_ALRM0TD_SC bit field */ + +#define ALRM0TD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_ALRM0TD_MN bit field */ +#define GET_ALRM0TD_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_ALRM0TD_MN bit field */ + +#define ALRM0TD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_ALRM0TD_HR bit field */ +#define GET_ALRM0TD_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_ALRM0TD_HR bit field */ + +#define ALRM0TD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0TD_DAY bit field */ +#define GET_ALRM0TD_DAY(regval) GET_BITS((regval),24,29) /*!< get value of RTC_ALRM0TD_DAY bit field */ + +#define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U) /*!< alarm none mask */ +#define RTC_ALARM_DATE_MASK RTC_ALRM0TD_MSKD /*!< alarm date mask */ +#define RTC_ALARM_HOUR_MASK RTC_ALRM0TD_MSKH /*!< alarm hour mask */ +#define RTC_ALARM_MINUTE_MASK RTC_ALRM0TD_MSKM /*!< alarm minute mask */ +#define RTC_ALARM_SECOND_MASK RTC_ALRM0TD_MSKS /*!< alarm second mask */ +#define RTC_ALARM_ALL_MASK (RTC_ALRM0TD_MSKD|RTC_ALRM0TD_MSKH|RTC_ALRM0TD_MSKM|RTC_ALRM0TD_MSKS) /*!< alarm all mask */ + +#define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U) /*!< alarm date format selected */ +#define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRM0TD_DOWS /*!< alarm weekday format selected */ + +/* wpk register value */ +#define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_WPK_WPK bit field */ + +/* ss register value */ +#define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SS_SSC bit field */ + +/* shiftctl register value */ +#define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SHIFTCTL_SFS bit field */ + +#define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U) /*!< not add 1 second */ +#define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S /*!< add one second to the clock */ + +/* tts register value */ +#define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TTS_SC bit field */ +#define GET_TTS_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TTS_SC bit field */ + +#define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TTS_MN bit field */ +#define GET_TTS_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TTS_MN bit field */ + +#define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TTS_HR bit field */ +#define GET_TTS_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TTS_HR bit field */ + +/* dts register value */ +#define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DTS_DAY bit field */ +#define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */ + +#define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DTS_MON bit field */ +#define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */ + +#define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DTS_DOW bit field */ +#define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */ + +/* ssts register value */ +#define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SSTS_SSC bit field */ + +/* hrfc register value */ +#define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_HRFC_CMSK bit field */ + +#define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U) /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */ +#define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16 /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */ +#define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8 /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */ + +#define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI /*!< increase RTC frequency by 488.5ppm */ +#define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */ + +/* tamp register value */ +#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TAMP_FREQ bit field */ +#define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV4096 TAMP_FREQ(3) /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV2048 TAMP_FREQ(4) /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV1024 TAMP_FREQ(5) /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV512 TAMP_FREQ(6) /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV256 TAMP_FREQ(7) /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */ + +#define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11U)) /*!< write value to RTC_TAMP_FLT bit field */ +#define RTC_FLT_EDGE TAMP_FLT(0) /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */ +#define RTC_FLT_2S TAMP_FLT(1) /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event */ +#define RTC_FLT_4S TAMP_FLT(2) /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */ +#define RTC_FLT_8S TAMP_FLT(3) /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event */ + +#define TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_TAMP_PRCH bit field */ +#define RTC_PRCH_1C TAMP_PRCH(0) /*!< 1 RTC clock prechagre time before each sampling */ +#define RTC_PRCH_2C TAMP_PRCH(1) /*!< 2 RTC clock prechagre time before each sampling */ +#define RTC_PRCH_4C TAMP_PRCH(2) /*!< 4 RTC clock prechagre time before each sampling */ +#define RTC_PRCH_8C TAMP_PRCH(3) /*!< 8 RTC clock prechagre time before each sampling */ + +#define RTC_TAMPER0 RTC_TAMP_TP0EN /*!< tamper 0 detection enable */ +#define RTC_TAMPER1 RTC_TAMP_TP1EN /*!< tamper 1 detection enable */ + +#define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U) /*!< tamper detection is in rising edge mode */ +#define RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMP_TP0EG /*!< tamper detection is in falling edge mode */ +#define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U) /*!< tamper detection is in low level mode */ +#define RTC_TAMPER_TRIGGER_LEVEL_HIGH RTC_TAMP_TP0EG /*!< tamper detection is in high level mode */ + +#define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */ + +#define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U) /*!< RTC alarm output open-drain mode */ +#define RTC_ALARM_OUTPUT_PP RTC_TAMP_PC13VAL /*!< RTC alarm output push-pull mode */ + +/* alrm0ss register value */ +#define ALRM0SS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0SS_SSC bit field */ + +#define ALRM0SS_MASKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0SS_MASKSSC bit field */ +#define RTC_MASKSSC_0_14 ALRM0SS_MASKSSC(0) /*!< mask alarm subsecond configuration */ +#define RTC_MASKSSC_1_14 ALRM0SS_MASKSSC(1) /*!< mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared */ +#define RTC_MASKSSC_2_14 ALRM0SS_MASKSSC(2) /*!< mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared */ +#define RTC_MASKSSC_3_14 ALRM0SS_MASKSSC(3) /*!< mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared */ +#define RTC_MASKSSC_4_14 ALRM0SS_MASKSSC(4) /*!< mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared */ +#define RTC_MASKSSC_5_14 ALRM0SS_MASKSSC(5) /*!< mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared */ +#define RTC_MASKSSC_6_14 ALRM0SS_MASKSSC(6) /*!< mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared */ +#define RTC_MASKSSC_7_14 ALRM0SS_MASKSSC(7) /*!< mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared */ +#define RTC_MASKSSC_8_14 ALRM0SS_MASKSSC(8) /*!< mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared */ +#define RTC_MASKSSC_9_14 ALRM0SS_MASKSSC(9) /*!< mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared */ +#define RTC_MASKSSC_10_14 ALRM0SS_MASKSSC(10) /*!< mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared */ +#define RTC_MASKSSC_11_14 ALRM0SS_MASKSSC(11) /*!< mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared */ +#define RTC_MASKSSC_12_14 ALRM0SS_MASKSSC(12) /*!< mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared */ +#define RTC_MASKSSC_13_14 ALRM0SS_MASKSSC(13) /*!< mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared */ +#define RTC_MASKSSC_14 ALRM0SS_MASKSSC(14) /*!< mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared */ +#define RTC_MASKSSC_NONE ALRM0SS_MASKSSC(15) /*!< mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared */ + +/* RTC interrupt source */ +#define RTC_INT_TIMESTAMP RTC_CTL_TSIE /*!< time-stamp interrupt enable */ +#define RTC_INT_ALARM RTC_CTL_ALRM0IE /*!< RTC alarm interrupt enable */ +#define RTC_INT_TAMP RTC_TAMP_TPIE /*!< tamper detection interrupt enable */ + +/* write protect key */ +#define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU) /*!< RTC unlock key1 */ +#define RTC_UNLOCK_KEY2 ((uint8_t)0x53U) /*!< RTC unlock key2 */ +#define RTC_LOCK_KEY ((uint8_t)0xFFU) /*!< RTC lock key */ + +/* registers reset value */ +#define RTC_REGISTER_RESET ((uint32_t)0x00000000U) /*!< RTC common register reset value */ +#define RTC_DATE_RESET ((uint32_t)0x00002101U) /*!< RTC_DATE register reset value */ +#define RTC_STAT_RESET ((uint32_t)0x00000007U) /*!< RTC_STAT register reset value */ +#define RTC_PSC_RESET ((uint32_t)0x007F00FFU) /*!< RTC_PSC register reset value */ + +/* RTC timeout value */ +#define RTC_INITM_TIMEOUT ((uint32_t)0x00004000U) /*!< initialization state flag timeout */ +#define RTC_RSYNF_TIMEOUT ((uint32_t)0x00008000U) /*!< register synchronization flag timeout */ +#define RTC_HRFC_TIMEOUT ((uint32_t)0x00001000U) /*!< recalibration pending flag timeout */ +#define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */ +#define RTC_ALRM0WF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be write flag timeout */ + +/* RTC flag */ +#define RTC_FLAG_RECALIBRATION RTC_STAT_SCPF /*!< recalibration pending flag */ +#define RTC_FLAG_TAMP1 RTC_STAT_TP1F /*!< tamper 1 event flag */ +#define RTC_FLAG_TAMP0 RTC_STAT_TP0F /*!< tamper 0 event flag */ +#define RTC_FLAG_TIMESTAMP_OVERFLOW RTC_STAT_TSOVRF /*!< time-stamp overflow event flag */ +#define RTC_FLAG_TIMESTAMP RTC_STAT_TSF /*!< time-stamp event flag */ +#define RTC_FLAG_ALARM0 RTC_STAT_ALRM0F /*!< alarm event flag */ +#define RTC_FLAG_INIT RTC_STAT_INITF /*!< init mode event flag */ +#define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< registers synchronized flag */ +#define RTC_FLAG_YCM RTC_STAT_YCM /*!< year parameter configured event flag */ +#define RTC_FLAG_SHIFT RTC_STAT_SOPF /*!< shift operation pending flag */ +#define RTC_FLAG_ALARM0_WRITTEN RTC_STAT_ALRM0WF /*!< alarm written available flag */ + +/* function declarations */ +/* reset most of the RTC registers */ +ErrStatus rtc_deinit(void); +/* initialize RTC registers */ +ErrStatus rtc_init(rtc_parameter_struct *rtc_initpara_struct); +/* enter RTC init mode */ +ErrStatus rtc_init_mode_enter(void); +/* exit RTC init mode */ +void rtc_init_mode_exit(void); +/* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */ +ErrStatus rtc_register_sync_wait(void); + +/* get current time and date */ +void rtc_current_time_get(rtc_parameter_struct *rtc_initpara_struct); +/* get current subsecond value */ +uint32_t rtc_subsecond_get(void); + +/* configure RTC alarm */ +void rtc_alarm_config(rtc_alarm_struct *rtc_alarm_time); +/* configure subsecond of RTC alarm */ +void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond); +/* get RTC alarm */ +void rtc_alarm_get(rtc_alarm_struct *rtc_alarm_time); +/* get RTC alarm subsecond */ +uint32_t rtc_alarm_subsecond_get(void); +/* enable RTC alarm */ +void rtc_alarm_enable(void); +/* disable RTC alarm */ +ErrStatus rtc_alarm_disable(void); + +/* enable RTC time-stamp */ +void rtc_timestamp_enable(uint32_t edge); +/* disable RTC time-stamp */ +void rtc_timestamp_disable(void); +/* get RTC timestamp time and date */ +void rtc_timestamp_get(rtc_timestamp_struct *rtc_timestamp); +/* get RTC time-stamp subsecond */ +uint32_t rtc_timestamp_subsecond_get(void); + +/* enable RTC tamper */ +void rtc_tamper_enable(rtc_tamper_struct *rtc_tamper); +/* disable RTC tamper */ +void rtc_tamper_disable(uint32_t source); + +/* enable specified RTC interrupt */ +void rtc_interrupt_enable(uint32_t interrupt); +/* disble specified RTC interrupt */ +void rtc_interrupt_disable(uint32_t interrupt); +/* check specified flag */ +FlagStatus rtc_flag_get(uint32_t flag); +/* clear specified flag */ +void rtc_flag_clear(uint32_t flag); + +/* configure RTC alternate output source */ +void rtc_alter_output_config(uint32_t source, uint32_t mode); +/* configure RTC calibration register */ +ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus); +/* ajust the daylight saving time by adding or substracting one hour from the current time */ +void rtc_hour_adjust(uint32_t operation); +/* ajust RTC second or subsecond value of current time */ +ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus); +/* enable RTC bypass shadow registers function */ +void rtc_bypass_shadow_enable(void); +/* disable RTC bypass shadow registers function */ +void rtc_bypass_shadow_disable(void); +/* enable RTC reference clock detection function */ +ErrStatus rtc_refclock_detection_enable(void); +/* disable RTC reference clock detection function */ +ErrStatus rtc_refclock_detection_disable(void); + +#endif /* GD32F3X0_RTC_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_spi.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_spi.h new file mode 100644 index 000000000..d42a67985 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_spi.h @@ -0,0 +1,369 @@ +/*! + \file gd32f3x0_spi.h + \brief definitions for the SPI + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_SPI_H +#define GD32F3X0_SPI_H + +#include "gd32f3x0.h" + +/* SPIx(x=0,1) definitions */ +#define SPI0 (SPI_BASE + 0x0000F800U) +#define SPI1 SPI_BASE + +/* SPI registers definitions */ +#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */ +#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/ +#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */ +#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */ +#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */ +#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */ +#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */ +#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */ +#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */ +#define SPI_QCTL(spix) REG32((spix) + 0x00000080U) /*!< SPI quad mode control register(only SPI1) */ + +/* bits definitions */ +/* SPI_CTL0 */ +#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ +#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ +#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ +#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ +#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ +#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ +#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ +#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ +#define SPI_CTL0_RO BIT(10) /*!< receive only */ +#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ +#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ +#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ +#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ +#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ + +/* SPI_CTL1 */ +#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ +#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ +#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ +#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */ +#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ +#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ +#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ +#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ + +/* SPI_STAT */ +#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ +#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ +#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ +#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ +#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ +#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ +#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ +#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ +#define SPI_STAT_FERR BIT(8) /*!< format error bit */ + +/* SPI_DATA */ +#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ + +/* SPI_CRCPOLY */ +#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */ + +/* SPI_RCRC */ +#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */ + +/* SPI_TCRC */ +#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */ + +/* SPI_I2SCTL */ +#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ +#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ +#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ +#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ +#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ +#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ +#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ +#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ + +/* SPI_I2SPSC */ +#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ +#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ +#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ + +/* SPI_QCTL(only for SPI1) */ +#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ +#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ +#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ + +/* constants definitions */ +/* SPI and I2S parameter struct definitions */ +typedef struct { + uint32_t device_mode; /*!< SPI master or slave */ + uint32_t trans_mode; /*!< SPI transtype */ + uint32_t frame_size; /*!< SPI frame size */ + uint32_t nss; /*!< SPI NSS control by handware or software */ + uint32_t endian; /*!< SPI big endian or little endian */ + uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ + uint32_t prescale; /*!< SPI prescale factor */ +} spi_parameter_struct; + +/* SPI mode definitions */ +#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ +#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ + +/* SPI bidirectional transfer direction */ +#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ +#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ + +/* SPI transmit type */ +#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ +#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ +#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ +#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ + +/* SPI frame size */ +#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ +#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ + +/* SPI NSS control mode */ +#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */ +#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ + +/* SPI transmit way */ +#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ +#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ + +/* SPI clock phase and polarity */ +#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ +#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ +#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ +#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ + +/* SPI clock prescale factor */ +#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ +#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ +#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ +#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ +#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ +#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ +#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ +#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ + +#if (defined(GD32F350) || defined(GD32F310)) +/* I2S audio sample rate */ +#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ +#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ +#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ +#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ +#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ +#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ +#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ +#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ +#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ + +/* I2S frame format */ +#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) +#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ +#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ + +/* I2S master clock output */ +#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ +#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ + +/* I2S operation mode */ +#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ +#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ +#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ +#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ + +/* I2S standard */ +#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ +#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ +#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ +#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ +#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ + +/* I2S clock polarity */ +#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ +#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ +#endif /* GD32F350 and GD32F310 */ + +/* SPI DMA constants definitions */ +#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ +#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ + +/* SPI CRC constants definitions */ +#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ +#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ + +/* SPI/I2S interrupt enable/disable constants definitions */ +#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ +#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ +#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ + +/* SPI/I2S interrupt flag constants definitions */ +#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ +#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ +#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ +#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ +#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ + +/* SPI flag definitions */ +#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ +#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ +#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ +#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ + +#if (defined(GD32F350) || defined(GD32F310)) +/* I2S flag definitions */ +#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ +#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ +#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ +#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ +#endif /* GD32F350 and GD32F310 */ + +/* function declarations */ +/* SPI/I2S deinitialization and initialization functions */ +/* reset SPI and I2S */ +void spi_i2s_deinit(uint32_t spi_periph); +/* initialize the parameters of SPI struct with the default values */ +void spi_struct_para_init(spi_parameter_struct *spi_struct); +/* initialize SPI parameter */ +void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct); +/* enable SPI */ +void spi_enable(uint32_t spi_periph); +/* disable SPI */ +void spi_disable(uint32_t spi_periph); + +#if (defined(GD32F350) || defined(GD32F310)) +/* initialize I2S parameter */ +void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl); +/* configure I2S prescaler */ +void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); +/* enable I2S */ +void i2s_enable(uint32_t spi_periph); +/* disable I2S */ +void i2s_disable(uint32_t spi_periph); +#endif /* GD32F350 and GD32F310 */ + +/* NSS functions */ +/* enable SPI NSS output */ +void spi_nss_output_enable(uint32_t spi_periph); +/* disable SPI NSS output */ +void spi_nss_output_disable(uint32_t spi_periph); +/* SPI NSS pin high level in software mode */ +void spi_nss_internal_high(uint32_t spi_periph); +/* SPI NSS pin low level in software mode */ +void spi_nss_internal_low(uint32_t spi_periph); + +/* enable SPI DMA */ +void spi_dma_enable(uint32_t spi_periph, uint8_t dma); +/* disable SPI DMA */ +void spi_dma_disable(uint32_t spi_periph, uint8_t dma); + +/* configure SPI/I2S data frame format */ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); +/* SPI transmit data */ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); +/* SPI receive data */ +uint16_t spi_i2s_data_receive(uint32_t spi_periph); +/* configure SPI bidirectional transfer direction */ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); + +/* SPI CRC functions */ +/* set SPI CRC polynomial */ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); +/* get SPI CRC polynomial */ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph); +/* turn on SPI CRC function */ +void spi_crc_on(uint32_t spi_periph); +/* turn off SPI CRC function */ +void spi_crc_off(uint32_t spi_periph); +/* SPI next data is CRC value */ +void spi_crc_next(uint32_t spi_periph); +/* get SPI CRC send value or receive value */ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); + +/* SPI TI mode functions */ +/* enable SPI TI mode */ +void spi_ti_mode_enable(uint32_t spi_periph); +/* disable SPI TI mode */ +void spi_ti_mode_disable(uint32_t spi_periph); + +/* SPI NSS pulse mode functions */ +/* enable SPI NSS pulse mode */ +void spi_nssp_mode_enable(uint32_t spi_periph); +/* disable SPI NSS pulse mode */ +void spi_nssp_mode_disable(uint32_t spi_periph); + +/* quad wire SPI functions */ +/* enable quad wire SPI */ +void qspi_enable(uint32_t spi_periph); +/* disable quad wire SPI */ +void qspi_disable(uint32_t spi_periph); +/* enable quad wire SPI write */ +void qspi_write_enable(uint32_t spi_periph); +/* enable quad wire SPI read */ +void qspi_read_enable(uint32_t spi_periph); +/* enable quad wire SPI_IO2 and SPI_IO3 pin output */ +void qspi_io23_output_enable(uint32_t spi_periph); +/* disable quad wire SPI_IO2 and SPI_IO3 pin output */ +void qspi_io23_output_disable(uint32_t spi_periph); + +/* flag and interrupt functions */ +/* enable SPI and I2S interrupt */ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); +/* disable SPI and I2S interrupt */ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S interrupt status */ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S flag status */ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); +/* clear SPI CRC error flag status */ +void spi_crc_error_clear(uint32_t spi_periph); + +#endif /* GD32F3X0_SPI_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_syscfg.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_syscfg.h new file mode 100644 index 000000000..619406594 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_syscfg.h @@ -0,0 +1,192 @@ +/*! + \file gd32f3x0_syscfg.h + \brief definitions for the SYSCFG + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_SYSCFG_H +#define GD32F3X0_SYSCFG_H + +#include "gd32f3x0.h" + +/* SYSCFG definitions */ +#define SYSCFG SYSCFG_BASE + +/* registers definitions */ +#define SYSCFG_CFG0 REG32(SYSCFG + 0x00000000U) /*!< system configuration register 0 */ +#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x00000008U) /*!< EXTI sources selection register 0 */ +#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0000000CU) /*!< EXTI sources selection register 1 */ +#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x00000010U) /*!< EXTI sources selection register 2 */ +#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x00000014U) /*!< EXTI sources selection register 3 */ +#define SYSCFG_CFG2 REG32(SYSCFG + 0x00000018U) /*!< system configuration register 2 */ +#define SYSCFG_CPSCTL REG32(SYSCFG + 0x00000020U) /*!< system I/O compensation control register */ + +/* SYSCFG_CFG0 bits definitions */ +#define SYSCFG_CFG0_BOOT_MODE BITS(0,1) /*!< SYSCFG memory remap config */ +#define SYSCFG_CFG0_ADC_DMA_RMP BIT(8) /*!< ADC DMA remap config */ +#define SYSCFG_CFG0_USART0_TX_DMA_RMP BIT(9) /*!< USART0 Tx DMA remap config */ +#define SYSCFG_CFG0_USART0_RX_DMA_RMP BIT(10) /*!< USART0 Rx DMA remap config */ +#define SYSCFG_CFG0_TIMER15_DMA_RMP BIT(11) /*!< TIMER 15 DMA remap config */ +#define SYSCFG_CFG0_TIMER16_DMA_RMP BIT(12) /*!< TIMER 16 DMA remap config */ +#define SYSCFG_CFG0_PB9_HCCE BIT(19) /*!< PB9 pin high current capability enable */ + +/* SYSCFG_EXTISS0 bits definitions */ +#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */ +#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */ +#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */ +#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */ + +/* SYSCFG_EXTISS1 bits definitions */ +#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */ +#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */ +#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */ +#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */ + +/* SYSCFG_EXTISS2 bits definitions */ +#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */ +#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */ +#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */ +#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */ + +/* SYSCFG_EXTISS3 bits definitions */ +#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */ +#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */ +#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */ +#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */ + +/* SYSCFG_CFG2 bits definitions */ +#define SYSCFG_CFG2_LOCKUP_LOCK BIT(0) /*!< enable and lock the LOCKUP (Hardfault) output of Cortex-M4 with break input of TIMER0/14/15/16 */ +#define SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK BIT(1) /*!< enable and lock the SRAM_PARITY error signal with break input of TIMER0/14/15/16 */ +#define SYSCFG_CFG2_LVD_LOCK BIT(2) /*!< enable and lock the LVD connection with TIMER0 break input and also the LVD_EN and LVDSEL[2:0] bits of the power control interface */ +#define SYSCFG_CFG2_SRAM_PCEF BIT(8) /*!< SRAM parity check error flag */ + +/* SYSCFG_CPSCTL bits definitions */ +#define SYSCFG_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */ +#define SYSCFG_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or not */ + +/* constants definitions */ +/* DMA remap definitions */ +#define SYSCFG_DMA_REMAP_ADC SYSCFG_CFG0_ADC_DMA_RMP /*!< ADC DMA remap */ +#define SYSCFG_DMA_REMAP_USART0TX SYSCFG_CFG0_USART0_TX_DMA_RMP /*!< USART0_TX DMA remap */ +#define SYSCFG_DMA_REMAP_USART0RX SYSCFG_CFG0_USART0_RX_DMA_RMP /*!< USART0_RX DMA remap */ +#define SYSCFG_DMA_REMAP_TIMER15 SYSCFG_CFG0_TIMER15_DMA_RMP /*!< TIMER15 DMA remap */ +#define SYSCFG_DMA_REMAP_TIMER16 SYSCFG_CFG0_TIMER16_DMA_RMP /*!< TIMER16 DMA remap */ + +/* high current definitions */ +#define SYSCFG_HIGH_CURRENT_ENABLE SYSCFG_CFG0_PB9_HCCE /*!< high current enable */ +#define SYSCFG_HIGH_CURRENT_DISABLE (~SYSCFG_CFG0_PB9_HCCE) /*!< high current disable */ + +/* EXTI source select definition */ +#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select register 0 */ +#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select register 1 */ +#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select register 2 */ +#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select register 3 */ + +/* EXTI source select mask bits definition */ +#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */ + +/* EXTI source select jumping step definition */ +#define EXTI_SS_JSTEP ((uint8_t)0x04U) /*!< EXTI source select jumping step */ + +/* EXTI source select moving step definition */ +#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP)) /*!< EXTI source select moving step */ + +/* EXTI source port definitions */ +#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */ +#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */ +#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */ +#define EXTI_SOURCE_GPIOD ((uint8_t)0x03U) /*!< EXTI GPIOD configuration */ +#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */ + +/* EXTI source pin definitions */ +#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */ +#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */ +#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */ +#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */ +#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */ +#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */ +#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */ +#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */ +#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */ +#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */ +#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */ +#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */ +#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */ +#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */ +#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */ +#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */ + +/* lock definitions */ +#define SYSCFG_LOCK_LOCKUP SYSCFG_CFG2_LOCKUP_LOCK /*!< LOCKUP output lock */ +#define SYSCFG_LOCK_SRAM_PARITY_ERROR SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK /*!< SRAM parity error lock */ +#define SYSCFG_LOCK_LVD SYSCFG_CFG2_LVD_LOCK /*!< LVD lock */ + +/* SRAM parity check error flag definitions */ +#define SYSCFG_SRAM_PCEF SYSCFG_CFG2_SRAM_PCEF /*!< SRAM parity check error flag */ + +/* I/O compensation cell enable/disable */ +#define SYSCFG_COMPENSATION(regval) (BIT(0) & ((uint32_t)(regval) << 0)) +#define SYSCFG_COMPENSATION_DISABLE SYSCFG_COMPENSATION(0) /*!< I/O compensation cell is power-down */ +#define SYSCFG_COMPENSATION_ENABLE SYSCFG_COMPENSATION(1) /*!< I/O compensation cell is enabled */ + +/* function declarations */ +/* deinit syscfg module */ +void syscfg_deinit(void); + +/* enable the DMA channels remapping */ +void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap); +/* disable the DMA channels remapping */ +void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap); + +/* enable PB9 high current capability */ +void syscfg_high_current_enable(void); +/* disable PB9 high current capability */ +void syscfg_high_current_disable(void); + +/* configure the GPIO pin as EXTI Line */ +void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin); +/* connect TIMER0/14/15/16 break input to the selected parameter */ +void syscfg_lock_config(uint32_t syscfg_lock); + +/* check if the specified flag in SYSCFG_CFG2 is set or not */ +FlagStatus syscfg_flag_get(uint32_t syscfg_flag); +/* clear the flag in SYSCFG_CFG2 by writing 1 */ +void syscfg_flag_clear(uint32_t syscfg_flag); + +/* configure the I/O compensation cell */ +void syscfg_compensation_config(uint32_t syscfg_compensation); +/* check if the I/O compensation cell ready flag is set or not */ +FlagStatus syscfg_cps_rdy_flag_get(void); + +#endif /* GD32F3X0_SYSCFG_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_timer.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_timer.h new file mode 100644 index 000000000..c9f4a8956 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_timer.h @@ -0,0 +1,765 @@ +/*! + \file gd32f3x0_timer.h + \brief definitions for the TIMER + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_TIMER_H +#define GD32F3X0_TIMER_H + +#include "gd32f3x0.h" + +/* TIMERx(x=0,1,2,5,13..16) definitions */ +#define TIMER0 (TIMER_BASE + 0x00012C00U) /*!< TIMER0 base address */ +#define TIMER1 (TIMER_BASE + 0x00000000U) /*!< TIMER1 base address */ +#define TIMER2 (TIMER_BASE + 0x00000400U) /*!< TIMER2 base address */ +#ifdef GD32F350 +#define TIMER5 (TIMER_BASE + 0x00001000U) /*!< TIMER5 base address */ +#endif +#define TIMER13 (TIMER_BASE + 0x00002000U) /*!< TIMER13 base address */ +#define TIMER14 (TIMER_BASE + 0x00014000U) /*!< TIMER14 base address */ +#define TIMER15 (TIMER_BASE + 0x00014400U) /*!< TIMER15 base address */ +#define TIMER16 (TIMER_BASE + 0x00014800U) /*!< TIMER16 base address */ + +/* registers definitions */ +#define TIMER_CTL0(timerx) REG32((timerx) + 0x00000000U) /*!< TIMER control register 0 */ +#define TIMER_CTL1(timerx) REG32((timerx) + 0x00000004U) /*!< TIMER control register 1 */ +#define TIMER_SMCFG(timerx) REG32((timerx) + 0x00000008U) /*!< TIMER slave mode configuration register */ +#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0000000CU) /*!< TIMER DMA and interrupt enable register */ +#define TIMER_INTF(timerx) REG32((timerx) + 0x00000010U) /*!< TIMER interrupt flag register */ +#define TIMER_SWEVG(timerx) REG32((timerx) + 0x00000014U) /*!< TIMER software event generation register */ +#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x00000018U) /*!< TIMER channel control register 0 */ +#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x0000001CU) /*!< TIMER channel control register 1 */ +#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x00000020U) /*!< TIMER channel control register 2 */ +#define TIMER_CNT(timerx) REG32((timerx) + 0x00000024U) /*!< TIMER counter register */ +#define TIMER_PSC(timerx) REG32((timerx) + 0x00000028U) /*!< TIMER prescaler register */ +#define TIMER_CAR(timerx) REG32((timerx) + 0x0000002CU) /*!< TIMER counter auto reload register */ +#define TIMER_CREP(timerx) REG32((timerx) + 0x00000030U) /*!< TIMER counter repetition register */ +#define TIMER_CH0CV(timerx) REG32((timerx) + 0x00000034U) /*!< TIMER channel 0 capture/compare value register */ +#define TIMER_CH1CV(timerx) REG32((timerx) + 0x00000038U) /*!< TIMER channel 1 capture/compare value register */ +#define TIMER_CH2CV(timerx) REG32((timerx) + 0x0000003CU) /*!< TIMER channel 2 capture/compare value register */ +#define TIMER_CH3CV(timerx) REG32((timerx) + 0x00000040U) /*!< TIMER channel 3 capture/compare value register */ +#define TIMER_CCHP(timerx) REG32((timerx) + 0x00000044U) /*!< TIMER complementary channel protection register */ +#define TIMER_DMACFG(timerx) REG32((timerx) + 0x00000048U) /*!< TIMER DMA configuration register */ +#define TIMER_DMATB(timerx) REG32((timerx) + 0x0000004CU) /*!< TIMER DMA transfer buffer register */ +#define TIMER_IRMP(timerx) REG32((timerx) + 0x00000050U) /*!< TIMER channel input remap register */ +#define TIMER_CFG(timerx) REG32((timerx) + 0x000000FCU) /*!< TIMER configuration register */ + +/* bits definitions */ +/* TIMER_CTL0 */ +#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ +#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ +#define TIMER_CTL0_UPS BIT(2) /*!< update source */ +#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ +#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ +#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ +#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ +#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ + +/* TIMER_CTL1 */ +#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ +#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ +#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ +#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ +#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ +#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ +#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ +#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ +#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ +#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ +#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ +#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ + +/* TIMER_SMCFG */ +#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ +#define TIMER_SMCFG_OCRC BIT(3) /*!< OCPRE clear source selection */ +#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ +#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ +#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ +#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ +#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ +#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ + +/* TIMER_DMAINTEN */ +#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ +#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ +#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ +#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ +#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ +#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */ +#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */ +#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */ +#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */ +#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ +#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ + +/* TIMER_INTF */ +#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ +#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ +#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ +#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ +#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ +#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ +#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ +#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ +#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 overcapture flag */ +#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 overcapture flag */ +#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 overcapture flag */ +#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 overcapture flag */ + +/* TIMER_SWEVG */ +#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ +#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ +#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ +#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ +#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ +#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ +#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ +#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ + +/* TIMER_CHCTL0 */ +/* output compare mode */ +#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ +#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ +#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ +#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare mode */ +#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ +#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ +#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ +#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ +#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare mode */ +#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ +#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ +#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ +#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ + +/* TIMER_CHCTL1 */ +/* output compare mode */ +#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ +#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ +#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ +#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare mode */ +#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ +#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ +#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ +#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ +#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */ +#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ +#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ +#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ +#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ + +/* TIMER_CHCTL2 */ +#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ +#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ +#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ +#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ +#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ +#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ +#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ +#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ +#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ +#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ +#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ +#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ +#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ +#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ +#define TIMER_CHCTL2_CH3NP BIT(15) /*!< channel 3 complementary output polarity */ + +/* TIMER_CNT */ +#define TIMER_CNT_CNT16 BITS(0,15) /*!< 16 bit timer counter */ +#define TIMER_CNT_CNT32 BITS(0,31) /*!< 32 bit(TIMER1) timer counter */ + +/* TIMER_PSC */ +#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ + +/* TIMER_CAR */ +#define TIMER_CAR_CARL16 BITS(0,15) /*!< 16 bit counter auto reload value */ +#define TIMER_CAR_CARL32 BITS(0,31) /*!< 32 bit(TIMER1) counter auto reload value */ + +/* TIMER_CREP */ +#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ + +/* TIMER_CH0CV */ +#define TIMER_CH0CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ +#define TIMER_CH0CV_CH0VAL32 BITS(0,31) /*!< 32 bit(TIMER1) capture/compare value of channel 0 */ + +/* TIMER_CH1CV */ +#define TIMER_CH1CV_CH1VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ +#define TIMER_CH1CV_CH1VAL32 BITS(0,31) /*!< 32 bit(TIMER1) capture/compare value of channel 1 */ + +/* TIMER_CH2CV */ +#define TIMER_CH2CV_CH2VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ +#define TIMER_CH2CV_CH2VAL32 BITS(0,31) /*!< 32 bit(TIMER1) capture/compare value of channel 2 */ + +/* TIMER_CH3CV */ +#define TIMER_CH3CV_CH3VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ +#define TIMER_CH3CV_CH3VAL32 BITS(0,31) /*!< 32 bit(TIMER1) capture/compare value of channel 3 */ + +/* TIMER_CCHP */ +#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ +#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ +#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ +#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ +#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ +#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ +#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ +#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ + +/* TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ +#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ + +/* TIMER_DMATB */ +#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ + +/* TIMER_IRMP */ +#define TIMER13_IRMP_CI0_RMP BITS(0,1) /*!< TIMER13 channel 0 input remap */ + +/* TIMER_CFG */ +#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ +#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */ + +/* constants definitions */ +/* TIMER init parameter struct definitions*/ +typedef struct { + uint16_t prescaler; /*!< prescaler value */ + uint16_t alignedmode; /*!< aligned mode */ + uint16_t counterdirection; /*!< counter direction */ + uint16_t clockdivision; /*!< clock division value */ + uint32_t period; /*!< period value */ + uint8_t repetitioncounter; /*!< the counter repetition value */ +} timer_parameter_struct; + +/* break parameter struct definitions*/ +typedef struct { + uint32_t runoffstate; /*!< run mode off-state */ + uint32_t ideloffstate; /*!< idle mode off-state */ + uint16_t deadtime; /*!< dead time */ + uint16_t breakpolarity; /*!< break polarity */ + uint32_t outputautostate; /*!< output automatic enable */ + uint32_t protectmode; /*!< complementary register protect control */ + uint32_t breakstate; /*!< break enable */ +} timer_break_parameter_struct; + +/* channel output parameter struct definitions */ +typedef struct { + uint32_t outputstate; /*!< channel output state */ + uint16_t outputnstate; /*!< channel complementary output state */ + uint16_t ocpolarity; /*!< channel output polarity */ + uint16_t ocnpolarity; /*!< channel complementary output polarity */ + uint16_t ocidlestate; /*!< idle state of channel output */ + uint16_t ocnidlestate; /*!< idle state of channel complementary output */ +} timer_oc_parameter_struct; + +/* channel input parameter struct definitions */ +typedef struct { + uint16_t icpolarity; /*!< channel input polarity */ + uint16_t icselection; /*!< channel input mode selection */ + uint16_t icprescaler; /*!< channel input capture prescaler */ + uint16_t icfilter; /*!< channel input capture filter control */ +} timer_ic_parameter_struct; + +/* TIMER interrupt enable or disable */ +#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ +#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ +#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ +#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ +#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ +#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ +#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ +#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ + +/* TIMER flag */ +#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ +#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ +#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ +#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ +#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ +#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */ +#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ +#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ +#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ +#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ +#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ +#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ + +/* TIMER interrupt flag */ +#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF /*!< update interrupt flag */ +#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 interrupt flag */ +#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 interrupt flag */ +#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 interrupt flag */ +#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 interrupt flag */ +#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation interrupt flag */ +#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */ +#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF + +/* TIMER DMA source enable */ +#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ +#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ +#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ +#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ +#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ +#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ +#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ + +/* channel DMA request source selection */ +#define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U) /*!< DMA request of channel y is sent when update event occurs */ +#define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U) /*!< DMA request of channel y is sent when channel y event occurs */ + +/* DMA access base address */ +#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) +#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ +#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ +#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ +#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ +#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ +#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ +#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ +#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ +#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ +#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ +#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ +#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ +#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ +#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ +#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ +#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ +#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ +#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ +#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19) /*!< DMA transfer address is TIMER_DMATB */ + +/* DMA access burst length */ +#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) +#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ +#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ +#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ +#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ +#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ +#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ +#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ +#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ +#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ +#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ +#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ +#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ +#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ +#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ +#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ +#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ +#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ +#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ + +/* TIMER software event generation source */ +#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ +#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ +#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ +#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ +#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ + +/* center-aligned mode selection */ +#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) +#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ +#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ +#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ +#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ + +/* TIMER prescaler reload mode */ +#define TIMER_PSC_RELOAD_NOW ((uint8_t)0x00U) /*!< the prescaler is loaded right now */ +#define TIMER_PSC_RELOAD_UPDATE ((uint8_t)0x01U) /*!< the prescaler is loaded at the next update event */ + +/* count direction */ +#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ +#define TIMER_COUNTER_DOWN ((uint16_t)0x0010U) /*!< counter down direction */ + +/* specify division ratio between TIMER clock and dead-time and sampling clock */ +#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1, fDTS=fTIMER_CK */ +#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2, fDTS= fTIMER_CK/2 */ +#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ + +/* single pulse mode */ +#define TIMER_SP_MODE_SINGLE ((uint8_t)0x00U) /*!< single pulse mode */ +#define TIMER_SP_MODE_REPETITIVE ((uint8_t)0x01U) /*!< repetitive pulse mode */ + +/* update source */ +#define TIMER_UPDATE_SRC_REGULAR ((uint8_t)0x00U) /*!< update generate only by counter overflow/underflow */ +#define TIMER_UPDATE_SRC_GLOBAL ((uint8_t)0x01U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ + +/* run mode off-state configure */ +#define TIMER_ROS_STATE_ENABLE ((uint32_t)0x00000800U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_ROS_STATE_DISABLE ((uint32_t)0x00000000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */ + +/* idle mode off-state configure */ +#define TIMER_IOS_STATE_ENABLE ((uint16_t)0x0400U) /*!< when POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */ + +/* break input polarity */ +#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ +#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)0x2000U) /*!< break input polarity is high */ + +/* output automatic enable */ +#define TIMER_OUTAUTO_ENABLE ((uint16_t)0x4000U) /*!< output automatic enable */ +#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ + +/* complementary register protect control */ +#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ +#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ +#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ +#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ + +/* break input enable */ +#define TIMER_BREAK_ENABLE ((uint16_t)0x1000U) /*!< break input enable */ +#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ + +/* TIMER channel n(n=0,1,2,3) */ +#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..2,13..16)) */ +#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..2,14)) */ +#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..2)) */ +#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..2)) */ + +/* channel enable state*/ +#define TIMER_CCX_ENABLE ((uint32_t)0x00000001U) /*!< channel enable */ +#define TIMER_CCX_DISABLE ((uint32_t)0x00000000U) /*!< channel disable */ + +/* channel complementary output enable state*/ +#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ +#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ + +/* channel output polarity */ +#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ +#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ + +/* channel complementary output polarity */ +#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ +#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ + +/* idle state of channel output */ +#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ +#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ + +/* idle state of channel complementary output */ +#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ +#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ + +/* channel output compare mode */ +#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ +#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ +#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ +#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ +#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ +#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ +#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ +#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/ + +/* channel output compare shadow enable */ +#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ +#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ + +/* channel output compare fast enable */ +#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ +#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ + +/* channel output compare clear enable */ +#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ +#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ + +/* channel control shadow register update control */ +#define TIMER_UPDATECTL_CCU ((uint8_t)0x00U) /*!< the shadow registers update by when CMTG bit is set */ +#define TIMER_UPDATECTL_CCUTRI ((uint8_t)0x01U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ + +/* channel input capture polarity */ +#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ +#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ +#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ + +/* timer input capture selection */ +#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ +#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ +#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ + +/* channel input capture prescaler */ +#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ +#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ +#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4*/ +#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ + +/* trigger selection */ +#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ +#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ +#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ +#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ +#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ +#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ +#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ +#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ + +/* master mode control */ +#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ +#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ +#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ +#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */ +#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ + +/* slave mode control */ +#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) +#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ +#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ +#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ +#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ +#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ +#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ +#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ +#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ + +/* OCPRE clear source selection */ +#define TIMER_OCPRE_CLEAR_SOURCE_CLR ((uint8_t)0x00U) /*!< OCPRE_CLR_INT is connected to the OCPRE_CLR input */ +#define TIMER_OCPRE_CLEAR_SOURCE_ETIF ((uint8_t)0x01U) /*!< OCPRE_CLR_INT is connected to ETIF */ + +/* master slave mode selection */ +#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint8_t)0x00U) /*!< master slave mode enable */ +#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint8_t)0x01U) /*!< master slave mode disable */ + +/* external trigger prescaler */ +#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) +#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ +#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ +#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ +#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ + +/* external trigger polarity */ +#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ +#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ + +/* channel 0 trigger input selection */ +#define TIMER_HALLINTERFACE_ENABLE ((uint8_t)0x00U) /*!< TIMER hall sensor mode enable */ +#define TIMER_HALLINTERFACE_DISABLE ((uint8_t)0x01U) /*!< TIMER hall sensor mode disable */ + +/* timerx(x=0,1,2,13,14,15,16) write CHxVAL register selection */ +#define TIMER_CHVSEL_ENABLE ((uint16_t)0x0002U) /*!< write CHxVAL register selection enable */ +#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ + +/* the output value selection */ +#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ +#define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U) /*!< output value selection enable */ + +/* timer13 channel 0 input remap */ +#define TIMER13_IRMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U)) +#define TIMER13_CI0_RMP_GPIO TIMER13_IRMP(0) /*!< timer13 channel 0 input is connected to GPIO(TIMER13_CH0) */ +#define TIMER13_CI0_RMP_RTCCLK TIMER13_IRMP(1) /*!< timer13 channel 0 input is connected to the RTCCLK */ +#define TIMER13_CI0_RMP_HXTAL_DIV32 TIMER13_IRMP(2) /*!< timer13 channel 0 input is connected to HXTAL/32 clock */ +#define TIMER13_CI0_RMP_CKOUTSEL TIMER13_IRMP(3) /*!< timer13 channel 0 input is connected to CKOUTSEL */ + +/* function declarations */ +/* TIMER timebase*/ +/* deinit a TIMER */ +void timer_deinit(uint32_t timer_periph); +/* initialize TIMER init parameter struct */ +void timer_struct_para_init(timer_parameter_struct *initpara); +/* initialize TIMER counter */ +void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara); +/* enable a TIMER */ +void timer_enable(uint32_t timer_periph); +/* disable a TIMER */ +void timer_disable(uint32_t timer_periph); +/* enable the auto reload shadow function */ +void timer_auto_reload_shadow_enable(uint32_t timer_periph); +/* disable the auto reload shadow function */ +void timer_auto_reload_shadow_disable(uint32_t timer_periph); +/* enable the update event */ +void timer_update_event_enable(uint32_t timer_periph); +/* disable the update event */ +void timer_update_event_disable(uint32_t timer_periph); +/* set TIMER counter alignment mode */ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); +/* set TIMER counter up direction */ +void timer_counter_up_direction(uint32_t timer_periph); +/* set TIMER counter down direction */ +void timer_counter_down_direction(uint32_t timer_periph); +/* configure TIMER prescaler */ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload); +/* configure TIMER repetition register value */ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); +/* configure TIMER autoreload register value */ +void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload); +/* configure TIMER counter register value */ +void timer_counter_value_config(uint32_t timer_periph, uint32_t counter); +/* read TIMER counter value */ +uint32_t timer_counter_read(uint32_t timer_periph); +/* read TIMER prescaler value */ +uint16_t timer_prescaler_read(uint32_t timer_periph); +/* configure TIMER single pulse mode */ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode); +/* configure TIMER update source */ +void timer_update_source_config(uint32_t timer_periph, uint8_t update); +/* OCPRE clear source selection */ +void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear); + +/* TIMER interrupt and flag*/ +/* get TIMER flags */ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); +/* clear TIMER flags */ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag); +/* enable the TIMER interrupt */ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); +/* disable the TIMER interrupt */ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); +/* get TIMER interrupt flag */ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); +/* clear TIMER interrupt flag */ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); + +/* TIMER DMA and event*/ +/* enable the TIMER DMA */ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma); +/* disable the TIMER DMA */ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma); +/* channel DMA request source selection */ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request); +/* configure the TIMER DMA transfer */ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth); +/* software generate events */ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event); + +/* TIMER channel complementary protection */ +/* initialize TIMER break parameter struct */ +void timer_break_struct_para_init(timer_break_parameter_struct *breakpara); +/* configure TIMER break function */ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara); +/* enable TIMER break function */ +void timer_break_enable(uint32_t timer_periph); +/* disable TIMER break function */ +void timer_break_disable(uint32_t timer_periph); +/* enable TIMER output automatic function */ +void timer_automatic_output_enable(uint32_t timer_periph); +/* disable TIMER output automatic function */ +void timer_automatic_output_disable(uint32_t timer_periph); +/* enable or disable TIMER primary output function */ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); +/* enable or disable channel capture/compare control shadow register */ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); +/* configure TIMER channel control shadow register update control */ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl); + +/* TIMER channel output */ +/* initialize TIMER channel output parameter struct */ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara); +/* configure TIMER channel output function */ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara); +/* configure TIMER channel output compare mode */ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); +/* configure TIMER channel output pulse value */ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); +/* configure TIMER channel output shadow function */ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); +/* configure TIMER channel output fast function */ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); +/* configure TIMER channel output clear function */ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear); +/* configure TIMER channel output polarity */ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); +/* configure TIMER channel complementary output polarity */ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); +/* configure TIMER channel enable state */ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); +/* configure TIMER channel complementary output enable state */ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); + +/* TIMER channel input */ +/* initialize TIMER channel input parameter struct */ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara); +/* configure TIMER input capture parameter */ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara); +/* configure TIMER channel input capture prescaler value */ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); +/* read TIMER channel capture compare register value */ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); +/* configure TIMER input pwm capture function */ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm); +/* configure TIMER hall sensor mode */ +void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode); + +/* TIMER master and slave */ +/* select TIMER input trigger source */ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); +/* select TIMER master mode output trigger source */ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); +/* select TIMER slave mode */ +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); +/* configure TIMER master slave mode */ +void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave); +/* configure TIMER external trigger input */ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER quadrature decoder mode */ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); +/* configure TIMER internal clock mode */ +void timer_internal_clock_config(uint32_t timer_periph); +/* configure TIMER the internal trigger as external clock input */ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); +/* configure TIMER the external trigger as external clock input */ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 0 */ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 1 */ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* disable TIMER the external clock mode 1 */ +void timer_external_clock_mode1_disable(uint32_t timer_periph); +/* configure TIMER channel remap function */ +void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap); + +/* TIMER configure */ +/* configure TIMER write CHxVAL register selection */ +void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); +/* configure TIMER output value selection */ +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); + +#endif /* GD32F3X0_TIMER_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_tsi.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_tsi.h new file mode 100644 index 000000000..b3429bf96 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_tsi.h @@ -0,0 +1,390 @@ +/*! + \file gd32f3x0_tsi.h + \brief definitions for the TSI + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_TSI_H +#define GD32F3X0_TSI_H + +#include "gd32f3x0.h" + +/* TSI definitions */ +#define TSI TSI_BASE /*!< TSI base address */ + +/* registers definitions */ +#define TSI_CTL0 REG32(TSI + 0x00000000U)/*!< TSI control register0 */ +#define TSI_INTEN REG32(TSI + 0x00000004U)/*!< TSI interrupt enable register */ +#define TSI_INTC REG32(TSI + 0x00000008U)/*!< TSI interrupt flag clear register */ +#define TSI_INTF REG32(TSI + 0x0000000CU)/*!< TSI interrupt flag register */ +#define TSI_PHM REG32(TSI + 0x00000010U)/*!< TSI pin hysteresis mode register */ +#define TSI_ASW REG32(TSI + 0x00000018U)/*!< TSI analog switch register */ +#define TSI_SAMPCFG REG32(TSI + 0x00000020U)/*!< TSI sample configuration register */ +#define TSI_CHCFG REG32(TSI + 0x00000028U)/*!< TSI channel configuration register */ +#define TSI_GCTL REG32(TSI + 0x00000030U)/*!< TSI group control register */ +#define TSI_G0CYCN REG32(TSI + 0x00000034U)/*!< TSI group 0 cycle number register */ +#define TSI_G1CYCN REG32(TSI + 0x00000038U)/*!< TSI group 1 cycle number register */ +#define TSI_G2CYCN REG32(TSI + 0x0000003CU)/*!< TSI group 2 cycle number register */ +#define TSI_G3CYCN REG32(TSI + 0x00000040U)/*!< TSI group 3 cycle number register */ +#define TSI_G4CYCN REG32(TSI + 0x00000044U)/*!< TSI group 4 cycle number register */ +#define TSI_G5CYCN REG32(TSI + 0x00000048U)/*!< TSI group 5 cycle number register */ +#define TSI_CTL1 REG32(TSI + 0x00000300U)/*!< TSI control registers1 */ + +/* bits definitions */ +/* TSI_CTL0 */ +#define TSI_CTL0_TSIEN BIT(0) /*!< TSI enable */ +#define TSI_CTL0_TSIS BIT(1) /*!< TSI start */ +#define TSI_CTL0_TRGMOD BIT(2) /*!< trigger mode selection */ +#define TSI_CTL0_EGSEL BIT(3) /*!< edge selection */ +#define TSI_CTL0_PINMOD BIT(4) /*!< pin mode */ +#define TSI_CTL0_MCN BITS(5,7) /*!< max cycle number of a sequence */ +#define TSI_CTL0_CTCDIV BITS(12,14) /*!< CTCLK clock division factor */ +#define TSI_CTL0_ECDIV BIT(15) /*!< ECCLK clock division factor */ +#define TSI_CTL0_ECEN BIT(16) /*!< extend charge state enable */ +#define TSI_CTL0_ECDT BITS(17,23) /*!< extend charge State maximum duration time */ +#define TSI_CTL0_CTDT BITS(24,27) /*!< charge transfer state duration time */ +#define TSI_CTL0_CDT BITS(28,31) /*!< charge state duration time */ + +/* TSI_INTEN */ +#define TSI_INTEN_CTCFIE BIT(0) /*!< charge transfer complete flag interrupt enable */ +#define TSI_INTEN_MNERRIE BIT(1) /*!< max cycle number error interrupt enable */ + +/* TSI_INTC */ +#define TSI_INTC_CCTCF BIT(0) /*!< clear charge transfer complete flag */ +#define TSI_INTC_CMNERR BIT(1) /*!< clear max cycle number error */ + +/* TSI_INTF */ +#define TSI_INTF_CTCF BIT(0) /*!< charge transfer complete flag */ +#define TSI_INTF_MNERR BIT(1) /*!< max cycle number error */ + +/* TSI_PHM */ +#define TSI_PHM_G0P0 BIT(0) /*!< pin G0P0 Schmitt trigger hysteresis state */ +#define TSI_PHM_G0P1 BIT(1) /*!< pin G0P1 Schmitt trigger hysteresis state */ +#define TSI_PHM_G0P2 BIT(2) /*!< pin G0P2 Schmitt trigger hysteresis state */ +#define TSI_PHM_G0P3 BIT(3) /*!< pin G0P3 Schmitt trigger hysteresis state */ +#define TSI_PHM_G1P0 BIT(4) /*!< pin G1P0 Schmitt trigger hysteresis state */ +#define TSI_PHM_G1P1 BIT(5) /*!< pin G1P1 Schmitt trigger hysteresis state */ +#define TSI_PHM_G1P2 BIT(6) /*!< pin G1P2 Schmitt trigger hysteresis state */ +#define TSI_PHM_G1P3 BIT(7) /*!< pin G1P3 Schmitt trigger hysteresis state */ +#define TSI_PHM_G2P0 BIT(8) /*!< pin G2P0 Schmitt trigger hysteresis state */ +#define TSI_PHM_G2P1 BIT(9) /*!< pin G2P1 Schmitt trigger hysteresis state */ +#define TSI_PHM_G2P2 BIT(10) /*!< pin G2P2 Schmitt trigger hysteresis state */ +#define TSI_PHM_G2P3 BIT(11) /*!< pin G2P3 Schmitt trigger hysteresis state */ +#define TSI_PHM_G3P0 BIT(12) /*!< pin G3P0 Schmitt trigger hysteresis state */ +#define TSI_PHM_G3P1 BIT(13) /*!< pin G3P1 Schmitt trigger hysteresis state */ +#define TSI_PHM_G3P2 BIT(14) /*!< pin G3P2 Schmitt trigger hysteresis state */ +#define TSI_PHM_G3P3 BIT(15) /*!< pin G3P3 Schmitt trigger hysteresis state */ +#define TSI_PHM_G4P0 BIT(16) /*!< pin G4P0 Schmitt trigger hysteresis state */ +#define TSI_PHM_G4P1 BIT(17) /*!< pin G4P1 Schmitt trigger hysteresis state */ +#define TSI_PHM_G4P2 BIT(18) /*!< pin G4P2 Schmitt trigger hysteresis state */ +#define TSI_PHM_G4P3 BIT(19) /*!< pin G4P3 Schmitt trigger hysteresis state */ +#define TSI_PHM_G5P0 BIT(20) /*!< pin G5P0 Schmitt trigger hysteresis state */ +#define TSI_PHM_G5P1 BIT(21) /*!< pin G5P1 Schmitt trigger hysteresis state */ +#define TSI_PHM_G5P2 BIT(22) /*!< pin G5P2 Schmitt trigger hysteresis state */ +#define TSI_PHM_G5P3 BIT(23) /*!< pin G5P3 Schmitt trigger hysteresis state */ + +/* TSI_ASW */ +#define TSI_ASW_G0P0 BIT(0) /*!< pin G0P0 analog switch state */ +#define TSI_ASW_G0P1 BIT(1) /*!< pin G0P1 analog switch state */ +#define TSI_ASW_G0P2 BIT(2) /*!< pin G0P2 analog switch state */ +#define TSI_ASW_G0P3 BIT(3) /*!< pin G0P3 analog switch state */ +#define TSI_ASW_G1P0 BIT(4) /*!< pin G1P0 analog switch state */ +#define TSI_ASW_G1P1 BIT(5) /*!< pin G1P1 analog switch state */ +#define TSI_ASW_G1P2 BIT(6) /*!< pin G1P2 analog switch state */ +#define TSI_ASW_G1P3 BIT(7) /*!< pin G1P3 analog switch state */ +#define TSI_ASW_G2P0 BIT(8) /*!< pin G2P0 analog switch state */ +#define TSI_ASW_G2P1 BIT(9) /*!< pin G2P1 analog switch state */ +#define TSI_ASW_G2P2 BIT(10) /*!< pin G2P2 analog switch state */ +#define TSI_ASW_G2P3 BIT(11) /*!< pin G2P3 analog switch state */ +#define TSI_ASW_G3P0 BIT(12) /*!< pin G3P0 analog switch state */ +#define TSI_ASW_G3P1 BIT(13) /*!< pin G3P1 analog switch state */ +#define TSI_ASW_G3P2 BIT(14) /*!< pin G3P2 analog switch state */ +#define TSI_ASW_G3P3 BIT(15) /*!< pin G3P3 analog switch state */ +#define TSI_ASW_G4P0 BIT(16) /*!< pin G4P0 analog switch state */ +#define TSI_ASW_G4P1 BIT(17) /*!< pin G4P1 analog switch state */ +#define TSI_ASW_G4P2 BIT(18) /*!< pin G4P2 analog switch state */ +#define TSI_ASW_G4P3 BIT(19) /*!< pin G4P3 analog switch state */ +#define TSI_ASW_G5P0 BIT(20) /*!< pin G5P0 analog switch state */ +#define TSI_ASW_G5P1 BIT(21) /*!< pin G5P1 analog switch state */ +#define TSI_ASW_G5P2 BIT(22) /*!< pin G5P2 analog switch state */ +#define TSI_ASW_G5P3 BIT(23) /*!< pin G5P3 analog switch state */ + +/* TSI_SAMPCFG */ +#define TSI_SAMPCFG_G0P0 BIT(0) /*!< pin G0P0 sample pin mode */ +#define TSI_SAMPCFG_G0P1 BIT(1) /*!< pin G0P1 sample pin mode */ +#define TSI_SAMPCFG_G0P2 BIT(2) /*!< pin G0P2 sample pin mode */ +#define TSI_SAMPCFG_G0P3 BIT(3) /*!< pin G0P3 sample pin mode */ +#define TSI_SAMPCFG_G1P0 BIT(4) /*!< pin G1P0 sample pin mode */ +#define TSI_SAMPCFG_G1P1 BIT(5) /*!< pin G1P1 sample pin mode */ +#define TSI_SAMPCFG_G1P2 BIT(6) /*!< pin G1P2 sample pin mode */ +#define TSI_SAMPCFG_G1P3 BIT(7) /*!< pin G1P3 sample pin mode */ +#define TSI_SAMPCFG_G2P0 BIT(8) /*!< pin G2P0 sample pin mode */ +#define TSI_SAMPCFG_G2P1 BIT(9) /*!< pin G2P1 sample pin mode */ +#define TSI_SAMPCFG_G2P2 BIT(10) /*!< pin G2P2 sample pin mode */ +#define TSI_SAMPCFG_G2P3 BIT(11) /*!< pin G2P3 sample pin mode */ +#define TSI_SAMPCFG_G3P0 BIT(12) /*!< pin G3P0 sample pin mode */ +#define TSI_SAMPCFG_G3P1 BIT(13) /*!< pin G3P1 sample pin mode */ +#define TSI_SAMPCFG_G3P2 BIT(14) /*!< pin G3P2 sample pin mode */ +#define TSI_SAMPCFG_G3P3 BIT(15) /*!< pin G3P3 sample pin mode */ +#define TSI_SAMPCFG_G4P0 BIT(16) /*!< pin G4P0 sample pin mode */ +#define TSI_SAMPCFG_G4P1 BIT(17) /*!< pin G4P1 sample pin mode */ +#define TSI_SAMPCFG_G4P2 BIT(18) /*!< pin G4P2 sample pin mode */ +#define TSI_SAMPCFG_G4P3 BIT(19) /*!< pin G4P3 sample pin mode */ +#define TSI_SAMPCFG_G5P0 BIT(20) /*!< pin G5P0 sample pin mode */ +#define TSI_SAMPCFG_G5P1 BIT(21) /*!< pin G5P1 sample pin mode */ +#define TSI_SAMPCFG_G5P2 BIT(22) /*!< pin G5P2 sample pin mode */ +#define TSI_SAMPCFG_G5P3 BIT(23) /*!< pin G5P3 sample pin mode */ + +/* TSI_CHCFG */ +#define TSI_CHCFG_G0P0 BIT(0) /*!< pin G0P0 channel pin mode */ +#define TSI_CHCFG_G0P1 BIT(1) /*!< pin G0P1 channel pin mode */ +#define TSI_CHCFG_G0P2 BIT(2) /*!< pin G0P2 channel pin mode */ +#define TSI_CHCFG_G0P3 BIT(3) /*!< pin G0P3 channel pin mode */ +#define TSI_CHCFG_G1P0 BIT(4) /*!< pin G1P0 channel pin mode */ +#define TSI_CHCFG_G1P1 BIT(5) /*!< pin G1P1 channel pin mode */ +#define TSI_CHCFG_G1P2 BIT(6) /*!< pin G1P2 channel pin mode */ +#define TSI_CHCFG_G1P3 BIT(7) /*!< pin G1P3 channel pin mode */ +#define TSI_CHCFG_G2P0 BIT(8) /*!< pin G2P0 channel pin mode */ +#define TSI_CHCFG_G2P1 BIT(9) /*!< pin G2P1 channel pin mode */ +#define TSI_CHCFG_G2P2 BIT(10) /*!< pin G2P2 channel pin mode */ +#define TSI_CHCFG_G2P3 BIT(11) /*!< pin G2P3 channel pin mode */ +#define TSI_CHCFG_G3P0 BIT(12) /*!< pin G3P0 channel pin mode */ +#define TSI_CHCFG_G3P1 BIT(13) /*!< pin G3P1 channel pin mode */ +#define TSI_CHCFG_G3P2 BIT(14) /*!< pin G3P2 channel pin mode */ +#define TSI_CHCFG_G3P3 BIT(15) /*!< pin G3P3 channel pin mode */ +#define TSI_CHCFG_G4P0 BIT(16) /*!< pin G4P0 channel pin mode */ +#define TSI_CHCFG_G4P1 BIT(17) /*!< pin G4P1 channel pin mode */ +#define TSI_CHCFG_G4P2 BIT(18) /*!< pin G4P2 channel pin mode */ +#define TSI_CHCFG_G4P3 BIT(19) /*!< pin G4P3 channel pin mode */ +#define TSI_CHCFG_G5P0 BIT(20) /*!< pin G5P0 channel pin mode */ +#define TSI_CHCFG_G5P1 BIT(21) /*!< pin G5P1 channel pin mode */ +#define TSI_CHCFG_G5P2 BIT(22) /*!< pin G5P2 channel pin mode */ +#define TSI_CHCFG_G5P3 BIT(23) /*!< pin G5P3 channel pin mode */ + +/* TSI_GCTL */ +#define TSI_GCTL_GE0 BIT(0) /*!< group0 enable */ +#define TSI_GCTL_GE1 BIT(1) /*!< group1 enable */ +#define TSI_GCTL_GE2 BIT(2) /*!< group2 enable */ +#define TSI_GCTL_GE3 BIT(3) /*!< group3 enable */ +#define TSI_GCTL_GE4 BIT(4) /*!< group4 enable */ +#define TSI_GCTL_GE5 BIT(5) /*!< group5 enable */ +#define TSI_GCTL_GC0 BIT(16) /*!< group0 complete */ +#define TSI_GCTL_GC1 BIT(17) /*!< group1 complete */ +#define TSI_GCTL_GC2 BIT(18) /*!< group2 complete */ +#define TSI_GCTL_GC3 BIT(19) /*!< group3 complete */ +#define TSI_GCTL_GC4 BIT(20) /*!< group4 complete */ +#define TSI_GCTL_GC5 BIT(21) /*!< group5 complete */ + +/* TSI_CTL1 */ +#define TSI_CTL1_CTCDIV BIT(24) /*!< CTCLK clock division factor */ +#define TSI_CTL1_ECDIV BITS(28,29) /*!< ECCLK clock division factor */ + +/* constants definitions */ +/* TSI interrupt enable bit */ +#define TSI_INT_CCTCF TSI_INTEN_CTCFIE /*!< charge transfer complete flag interrupt enable */ +#define TSI_INT_MNERR TSI_INTEN_MNERRIE /*!< max cycle number error interrupt enable */ + +/* TSI interrupt flags */ +#define TSI_INT_FLAG_CTCF TSI_INTF_CTCF /*!< charge transfer complete flag */ +#define TSI_INT_FLAG_MNERR TSI_INTF_MNERR /*!< max cycle number error */ + +/* TSI flags */ +#define TSI_FLAG_CTCF TSI_INTF_CTCF /*!< charge transfer complete flag */ +#define TSI_FLAG_MNERR TSI_INTF_MNERR /*!< max cycle number error */ + +/* CTCLK clock division factor */ +#define TSI_CTCDIV_DIV1 ((uint32_t)0x00000000U) /*!< fCTCLK = fHCLK */ +#define TSI_CTCDIV_DIV2 ((uint32_t)0x00000001U) /*!< fCTCLK = fHCLK/2 */ +#define TSI_CTCDIV_DIV4 ((uint32_t)0x00000002U) /*!< fCTCLK = fHCLK/4 */ +#define TSI_CTCDIV_DIV8 ((uint32_t)0x00000003U) /*!< fCTCLK = fHCLK/8 */ +#define TSI_CTCDIV_DIV16 ((uint32_t)0x00000004U) /*!< fCTCLK = fHCLK/16 */ +#define TSI_CTCDIV_DIV32 ((uint32_t)0x00000005U) /*!< fCTCLK = fHCLK/32 */ +#define TSI_CTCDIV_DIV64 ((uint32_t)0x00000006U) /*!< fCTCLK = fHCLK/64 */ +#define TSI_CTCDIV_DIV128 ((uint32_t)0x00000007U) /*!< fCTCLK = fHCLK/128 */ +#define TSI_CTCDIV_DIV256 ((uint32_t)0x00000008U) /*!< fCTCLK = fHCLK/256 */ +#define TSI_CTCDIV_DIV512 ((uint32_t)0x00000009U) /*!< fCTCLK = fHCLK/512 */ +#define TSI_CTCDIV_DIV1024 ((uint32_t)0x0000000AU) /*!< fCTCLK = fHCLK/1024 */ +#define TSI_CTCDIV_DIV2048 ((uint32_t)0x0000000BU) /*!< fCTCLK = fHCLK/2048 */ +#define TSI_CTCDIV_DIV4096 ((uint32_t)0x0000000CU) /*!< fCTCLK = fHCLK/4096 */ +#define TSI_CTCDIV_DIV8192 ((uint32_t)0x0000000DU) /*!< fCTCLK = fHCLK/8192 */ +#define TSI_CTCDIV_DIV16384 ((uint32_t)0x0000000EU) /*!< fCTCLK = fHCLK/16384 */ +#define TSI_CTCDIV_DIV32768 ((uint32_t)0x0000000FU) /*!< fCTCLK = fHCLK/32768 */ + +/* charge transfer state duration Time */ +#define CTL_CTDT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U)) +#define TSI_TRANSFER_1CTCLK CTL_CTDT(0) /*!< the duration time of transfer state is 1 CTCLK */ +#define TSI_TRANSFER_2CTCLK CTL_CTDT(1) /*!< the duration time of transfer state is 2 CTCLK */ +#define TSI_TRANSFER_3CTCLK CTL_CTDT(2) /*!< the duration time of transfer state is 3 CTCLK */ +#define TSI_TRANSFER_4CTCLK CTL_CTDT(3) /*!< the duration time of transfer state is 4 CTCLK */ +#define TSI_TRANSFER_5CTCLK CTL_CTDT(4) /*!< the duration time of transfer state is 5 CTCLK */ +#define TSI_TRANSFER_6CTCLK CTL_CTDT(5) /*!< the duration time of transfer state is 6 CTCLK */ +#define TSI_TRANSFER_7CTCLK CTL_CTDT(6) /*!< the duration time of transfer state is 7 CTCLK */ +#define TSI_TRANSFER_8CTCLK CTL_CTDT(7) /*!< the duration time of transfer state is 8 CTCLK */ +#define TSI_TRANSFER_9CTCLK CTL_CTDT(8) /*!< the duration time of transfer state is 9 CTCLK */ +#define TSI_TRANSFER_10CTCLK CTL_CTDT(9) /*!< the duration time of transfer state is 10 CTCLK */ +#define TSI_TRANSFER_11CTCLK CTL_CTDT(10) /*!< the duration time of transfer state is 11 CTCLK */ +#define TSI_TRANSFER_12CTCLK CTL_CTDT(11) /*!< the duration time of transfer state is 12 CTCLK */ +#define TSI_TRANSFER_13CTCLK CTL_CTDT(12) /*!< the duration time of transfer state is 13 CTCLK */ +#define TSI_TRANSFER_14CTCLK CTL_CTDT(13) /*!< the duration time of transfer state is 14 CTCLK */ +#define TSI_TRANSFER_15CTCLK CTL_CTDT(14) /*!< the duration time of transfer state is 15 CTCLK */ +#define TSI_TRANSFER_16CTCLK CTL_CTDT(15) /*!< the duration time of transfer state is 16 CTCLK */ + +/* charge state duration time */ +#define CTL_CDT(regval) (BITS(28,31) & ((uint32_t)(regval) << 28U)) +#define TSI_CHARGE_1CTCLK CTL_CDT(0) /*!< the duration time of charge state is 1 CTCLK */ +#define TSI_CHARGE_2CTCLK CTL_CDT(1) /*!< the duration time of charge state is 2 CTCLK */ +#define TSI_CHARGE_3CTCLK CTL_CDT(2) /*!< the duration time of charge state is 3 CTCLK */ +#define TSI_CHARGE_4CTCLK CTL_CDT(3) /*!< the duration time of charge state is 4 CTCLK */ +#define TSI_CHARGE_5CTCLK CTL_CDT(4) /*!< the duration time of charge state is 5 CTCLK */ +#define TSI_CHARGE_6CTCLK CTL_CDT(5) /*!< the duration time of charge state is 6 CTCLK */ +#define TSI_CHARGE_7CTCLK CTL_CDT(6) /*!< the duration time of charge state is 7 CTCLK */ +#define TSI_CHARGE_8CTCLK CTL_CDT(7) /*!< the duration time of charge state is 8 CTCLK */ +#define TSI_CHARGE_9CTCLK CTL_CDT(8) /*!< the duration time of charge state is 9 CTCLK */ +#define TSI_CHARGE_10CTCLK CTL_CDT(9) /*!< the duration time of charge state is 10 CTCLK */ +#define TSI_CHARGE_11CTCLK CTL_CDT(10) /*!< the duration time of charge state is 11 CTCLK */ +#define TSI_CHARGE_12CTCLK CTL_CDT(11) /*!< the duration time of charge state is 12 CTCLK */ +#define TSI_CHARGE_13CTCLK CTL_CDT(12) /*!< the duration time of charge state is 13 CTCLK */ +#define TSI_CHARGE_14CTCLK CTL_CDT(13) /*!< the duration time of charge state is 14 CTCLK */ +#define TSI_CHARGE_15CTCLK CTL_CDT(14) /*!< the duration time of charge state is 15 CTCLK */ +#define TSI_CHARGE_16CTCLK CTL_CDT(15) /*!< the duration time of charge state is 16 CTCLK */ + +/* max cycle number of a sequence */ +#define CTL_MCN(regval) (BITS(5,7) & ((uint32_t)(regval) << 5U)) +#define TSI_MAXNUM255 CTL_MCN(0) /*!< the max cycle number of a sequence is 255 */ +#define TSI_MAXNUM511 CTL_MCN(1) /*!< the max cycle number of a sequence is 511 */ +#define TSI_MAXNUM1023 CTL_MCN(2) /*!< the max cycle number of a sequence is 1023 */ +#define TSI_MAXNUM2047 CTL_MCN(3) /*!< the max cycle number of a sequence is 2047 */ +#define TSI_MAXNUM4095 CTL_MCN(4) /*!< the max cycle number of a sequence is 4095 */ +#define TSI_MAXNUM8191 CTL_MCN(5) /*!< the max cycle number of a sequence is 8191 */ +#define TSI_MAXNUM16383 CTL_MCN(6) /*!< the max cycle number of a sequence is 16383 */ + +/* ECCLK clock division factor */ +#define TSI_EXTEND_DIV1 ((uint32_t)0x00000000U) /*!< fECCLK = fHCLK */ +#define TSI_EXTEND_DIV2 ((uint32_t)0x00000001U) /*!< fECCLK = fHCLK/2 */ +#define TSI_EXTEND_DIV3 ((uint32_t)0x00000002U) /*!< fECCLK = fHCLK/3 */ +#define TSI_EXTEND_DIV4 ((uint32_t)0x00000003U) /*!< fECCLK = fHCLK/4 */ +#define TSI_EXTEND_DIV5 ((uint32_t)0x00000004U) /*!< fECCLK = fHCLK/5 */ +#define TSI_EXTEND_DIV6 ((uint32_t)0x00000005U) /*!< fECCLK = fHCLK/6 */ +#define TSI_EXTEND_DIV7 ((uint32_t)0x00000006U) /*!< fECCLK = fHCLK/7 */ +#define TSI_EXTEND_DIV8 ((uint32_t)0x00000007U) /*!< fECCLK = fHCLK/8 */ + +/* extend charge state maximum duration time */ +#define TSI_EXTENDMAX(regval) (BITS(17,23) & ((uint32_t)(regval) << 17U)) /* value range 1..128,extend charge state maximum duration time */ + +/* hardware trigger mode */ +#define TSI_FALLING_TRIGGER 0x00U /*!< falling edge trigger TSI charge transfer sequence */ +#define TSI_RISING_TRIGGER 0x01U /*!< rising edge trigger TSI charge transfer sequence */ + +/* pin mode */ +#define TSI_OUTPUT_LOW 0x00U /*!< TSI pin will output low when IDLE */ +#define TSI_INPUT_FLOATING 0x01U /*!< TSI pin will keep input_floating when IDLE */ + +/* function declarations */ +/* reset TSI peripheral */ +void tsi_deinit(void); +/* initialize TSI plus prescaler,charge plus,transfer plus,max cycle number */ +void tsi_init(uint32_t prescaler, uint32_t charge_duration, uint32_t transfer_duration, uint32_t max_number); +/* enable TSI module */ +void tsi_enable(void); +/* disable TSI module */ +void tsi_disable(void); +/* enable sample pin */ +void tsi_sample_pin_enable(uint32_t sample); +/* disable sample pin */ +void tsi_sample_pin_disable(uint32_t sample); +/* enable channel pin */ +void tsi_channel_pin_enable(uint32_t channel); +/* disable channel pin */ +void tsi_channel_pin_disable(uint32_t channel); + +/* configure TSI triggering by software */ +void tsi_software_mode_config(void); +/* start a charge-transfer sequence when TSI is in software trigger mode */ +void tsi_software_start(void); +/* stop a charge-transfer sequence when TSI is in software trigger mode */ +void tsi_software_stop(void); +/* configure TSI triggering by hardware */ +void tsi_hardware_mode_config(uint8_t trigger_edge); +/* configure TSI pin mode when charge-transfer sequence is IDLE */ +void tsi_pin_mode_config(uint8_t pin_mode); +/* configure extend charge state */ +void tsi_extend_charge_config(ControlStatus extend, uint8_t prescaler, uint32_t max_duration); + +/* configure charge plus and transfer plus */ +void tsi_plus_config(uint32_t prescaler, uint32_t charge_duration, uint32_t transfer_duration); +/* configure the max cycle number of a charge-transfer sequence */ +void tsi_max_number_config(uint32_t max_number); +/* switch on hysteresis pin */ +void tsi_hysteresis_on(uint32_t group_pin); +/* switch off hysteresis pin */ +void tsi_hysteresis_off(uint32_t group_pin); +/* switch on analog pin */ +void tsi_analog_on(uint32_t group_pin); +/* switch off analog pin */ +void tsi_analog_off(uint32_t group_pin); + +/* enbale group */ +void tsi_group_enable(uint32_t group); +/* disbale group */ +void tsi_group_disable(uint32_t group); +/* get group complete status */ +FlagStatus tsi_group_status_get(uint32_t group); +/* get the cycle number for group0 as soon as a charge-transfer sequence completes */ +uint16_t tsi_group0_cycle_get(void); +/* get the cycle number for group1 as soon as a charge-transfer sequence completes */ +uint16_t tsi_group1_cycle_get(void); +/* get the cycle number for group2 as soon as a charge-transfer sequence completes */ +uint16_t tsi_group2_cycle_get(void); +/* get the cycle number for group3 as soon as a charge-transfer sequence completes */ +uint16_t tsi_group3_cycle_get(void); +/* get the cycle number for group4 as soon as a charge-transfer sequence completes */ +uint16_t tsi_group4_cycle_get(void); +/* get the cycle number for group5 as soon as a charge-transfer sequence completes */ +uint16_t tsi_group5_cycle_get(void); + +/* clear flag */ +void tsi_flag_clear(uint32_t flag); +/* get flag */ +FlagStatus tsi_flag_get(uint32_t flag); + +/* enable TSI interrupt */ +void tsi_interrupt_enable(uint32_t source); +/* disable TSI interrupt */ +void tsi_interrupt_disable(uint32_t source); +/* clear interrupt flag */ +void tsi_interrupt_flag_clear(uint32_t flag); +/* get TSI interrupt flag */ +FlagStatus tsi_interrupt_flag_get(uint32_t flag); + +#endif /* GD32F3X0_TSI_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_usart.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_usart.h new file mode 100644 index 000000000..c471a8140 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_usart.h @@ -0,0 +1,595 @@ +/*! + \file gd32f3x0_usart.h + \brief definitions for the USART + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_USART_H +#define GD32F3X0_USART_H + +#include "gd32f3x0.h" + +/* USARTx(x=0,1) definitions */ +#define USART0 (USART_BASE + 0x0000F400U) +#define USART1 USART_BASE + +/* registers definitions */ +#define USART_CTL0(usartx) REG32((usartx) + 0x00000000U) /*!< USART control register 0 */ +#define USART_CTL1(usartx) REG32((usartx) + 0x00000004U) /*!< USART control register 1 */ +#define USART_CTL2(usartx) REG32((usartx) + 0x00000008U) /*!< USART control register 2 */ +#define USART_BAUD(usartx) REG32((usartx) + 0x0000000CU) /*!< USART baud rate register */ +#define USART_GP(usartx) REG32((usartx) + 0x00000010U) /*!< USART guard time and prescaler register */ +#define USART_RT(usartx) REG32((usartx) + 0x00000014U) /*!< USART receiver timeout register */ +#define USART_CMD(usartx) REG32((usartx) + 0x00000018U) /*!< USART command register */ +#define USART_STAT(usartx) REG32((usartx) + 0x0000001CU) /*!< USART status register */ +#define USART_INTC(usartx) REG32((usartx) + 0x00000020U) /*!< USART status clear register */ +#define USART_RDATA(usartx) REG32((usartx) + 0x00000024U) /*!< USART receive data register */ +#define USART_TDATA(usartx) REG32((usartx) + 0x00000028U) /*!< USART transmit data register */ +#define USART_RFCS(usartx) REG32((usartx) + 0x000000D0U) /*!< USART receive FIFO control and status register */ + +/* bits definitions */ +/* USARTx_CTL0 */ +#define USART_CTL0_UEN BIT(0) /*!< USART enable */ +#define USART_CTL0_UESM BIT(1) /*!< USART enable in deep-sleep mode */ +#define USART_CTL0_REN BIT(2) /*!< receiver enable */ +#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ +#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ +#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ +#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ +#define USART_CTL0_TBEIE BIT(7) /*!< transmitter register empty interrupt enable */ +#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ +#define USART_CTL0_PM BIT(9) /*!< parity mode */ +#define USART_CTL0_PCEN BIT(10) /*!< parity control enable */ +#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ +#define USART_CTL0_WL BIT(12) /*!< word length */ +#define USART_CTL0_MEN BIT(13) /*!< mute mode enable */ +#define USART_CTL0_AMIE BIT(14) /*!< address match interrupt enable */ +#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ +#define USART_CTL0_DED BITS(16,20) /*!< driver enable deassertion time */ +#define USART_CTL0_DEA BITS(21,25) /*!< driver enable assertion time */ +#define USART_CTL0_RTIE BIT(26) /*!< receiver timeout interrupt enable */ +#define USART_CTL0_EBIE BIT(27) /*!< end of block interrupt enable */ + +/* USARTx_CTL1 */ +#define USART_CTL1_ADDM BIT(4) /*!< address detection mode */ +#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ +#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detection interrupt enable */ +#define USART_CTL1_CLEN BIT(8) /*!< last bit clock pulse */ +#define USART_CTL1_CPH BIT(9) /*!< clock phase */ +#define USART_CTL1_CPL BIT(10) /*!< clock polarity */ +#define USART_CTL1_CKEN BIT(11) /*!< ck pin enable */ +#define USART_CTL1_STB BITS(12,13) /*!< stop bits length */ +#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ +#define USART_CTL1_STRP BIT(15) /*!< swap TX/RX pins */ +#define USART_CTL1_RINV BIT(16) /*!< RX pin level inversion */ +#define USART_CTL1_TINV BIT(17) /*!< TX pin level inversion */ +#define USART_CTL1_DINV BIT(18) /*!< data bit level inversion */ +#define USART_CTL1_MSBF BIT(19) /*!< most significant bit first */ +#define USART_CTL1_ABDEN BIT(20) /*!< auto baud rate enable */ +#define USART_CTL1_ABDM BITS(21,22) /*!< auto baud rate mode */ +#define USART_CTL1_RTEN BIT(23) /*!< receiver timeout enable */ +#define USART_CTL1_ADDR BITS(24,31) /*!< address of the USART terminal */ + +/* USARTx_CTL2 */ +#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable in multibuffer communication */ +#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ +#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ +#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ +#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ +#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ +#define USART_CTL2_DENR BIT(6) /*!< DMA enable for reception */ +#define USART_CTL2_DENT BIT(7) /*!< DMA enable for transmission */ +#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ +#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ +#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ +#define USART_CTL2_OSB BIT(11) /*!< one sample bit mode */ +#define USART_CTL2_OVRD BIT(12) /*!< overrun disable */ +#define USART_CTL2_DDRE BIT(13) /*!< disable DMA on reception error */ +#define USART_CTL2_DEM BIT(14) /*!< driver enable mode */ +#define USART_CTL2_DEP BIT(15) /*!< driver enable polarity mode */ +#define USART_CTL2_SCRTNUM BITS(17,19) /*!< smartcard auto-retry number */ +#define USART_CTL2_WUM BITS(20,21) /*!< wakeup mode from deep-sleep mode */ +#define USART_CTL2_WUIE BIT(22) /*!< wakeup from deep-sleep mode interrupt enable */ + +/* USARTx_BAUD */ +#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction of baud-rate divider */ +#define USART_BAUD_INTDIV BITS(4,15) /*!< integer of baud-rate divider */ + +/* USARTx_GP */ +#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ + +/* USARTx_RT */ +#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ +#define USART_RT_BL BITS(24,31) /*!< block length */ + +/* USARTx_CMD */ +#define USART_CMD_ABDCMD BIT(0) /*!< auto baudrate detection command */ +#define USART_CMD_SBKCMD BIT(1) /*!< send break command */ +#define USART_CMD_MMCMD BIT(2) /*!< mute mode command */ +#define USART_CMD_RXFCMD BIT(3) /*!< receive data flush command */ +#define USART_CMD_TXFCMD BIT(4) /*!< transmit data flush request */ + +/* USARTx_STAT */ +#define USART_STAT_PERR BIT(0) /*!< parity error flag */ +#define USART_STAT_FERR BIT(1) /*!< frame error flag */ +#define USART_STAT_NERR BIT(2) /*!< noise error flag */ +#define USART_STAT_ORERR BIT(3) /*!< overrun error */ +#define USART_STAT_IDLEF BIT(4) /*!< idle line detected flag */ +#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ +#define USART_STAT_TC BIT(6) /*!< transmission completed */ +#define USART_STAT_TBE BIT(7) /*!< transmit data register empty */ +#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */ +#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ +#define USART_STAT_CTS BIT(10) /*!< CTS level */ +#define USART_STAT_RTF BIT(11) /*!< receiver timeout flag */ +#define USART_STAT_EBF BIT(12) /*!< end of block flag */ +#define USART_STAT_ABDE BIT(14) /*!< auto baudrate detection error */ +#define USART_STAT_ABDF BIT(15) /*!< auto baudrate detection flag */ +#define USART_STAT_BSY BIT(16) /*!< busy flag */ +#define USART_STAT_AMF BIT(17) /*!< address match flag */ +#define USART_STAT_SBF BIT(18) /*!< send break flag */ +#define USART_STAT_RWU BIT(19) /*!< receiver wakeup from mute mode */ +#define USART_STAT_WUF BIT(20) /*!< wakeup from deep-sleep mode flag */ +#define USART_STAT_TEA BIT(21) /*!< transmit enable acknowledge flag */ +#define USART_STAT_REA BIT(22) /*!< receive enable acknowledge flag */ + +/* USARTx_INTC */ +#define USART_INTC_PEC BIT(0) /*!< parity error clear */ +#define USART_INTC_FEC BIT(1) /*!< frame error flag clear */ +#define USART_INTC_NEC BIT(2) /*!< noise detected clear */ +#define USART_INTC_OREC BIT(3) /*!< overrun error clear */ +#define USART_INTC_IDLEC BIT(4) /*!< idle line detected clear */ +#define USART_INTC_TCC BIT(6) /*!< transmission complete clear */ +#define USART_INTC_LBDC BIT(8) /*!< LIN break detected clear */ +#define USART_INTC_CTSC BIT(9) /*!< CTS change clear */ +#define USART_INTC_RTC BIT(11) /*!< receiver timeout clear */ +#define USART_INTC_EBC BIT(12) /*!< end of timeout clear */ +#define USART_INTC_AMC BIT(17) /*!< address match clear */ +#define USART_INTC_WUC BIT(20) /*!< wakeup from deep-sleep mode clear */ + +/* USARTx_RDATA */ +#define USART_RDATA_RDATA BITS(0,8) /*!< receive data value */ + +/* USARTx_TDATA */ +#define USART_TDATA_TDATA BITS(0,8) /*!< transmit data value */ + +/* USARTx_RFCS */ +#define USART_RFCS_ELNACK BIT(0) /*!< early NACK */ +#define USART_RFCS_RFEN BIT(8) /*!< receive FIFO enable */ +#define USART_RFCS_RFFIE BIT(9) /*!< receive FIFO full interrupt enable */ +#define USART_RFCS_RFE BIT(10) /*!< receive FIFO empty flag */ +#define USART_RFCS_RFF BIT(11) /*!< receive FIFO full flag */ +#define USART_RFCS_RFCNT BITS(12,14) /*!< receive FIFO counter number */ +#define USART_RFCS_RFFINT BIT(15) /*!< receive FIFO full interrupt flag */ + +/* constants definitions */ + +/* define the USART bit position and its register index offset */ +#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) +#define USART_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) +#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) +#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) + +/* register offset */ +#define USART_CTL0_REG_OFFSET (0x00000000U) /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET (0x00000004U) /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET (0x00000008U) /*!< CTL2 register offset */ +#define USART_STAT_REG_OFFSET (0x0000001CU) /*!< STAT register offset */ +#define USART_RFCS_REG_OFFSET (0x000000D0U) /*!< RFCS register offset */ + +/* USART flags */ +typedef enum { + /* flags in STAT register */ + USART_FLAG_REA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 22U), /*!< receive enable acknowledge flag */ + USART_FLAG_TEA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 21U), /*!< transmit enable acknowledge flag */ + USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode flag */ + USART_FLAG_RWU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 19U), /*!< receiver wakeup from mute mode */ + USART_FLAG_SB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 18U), /*!< send break flag */ + USART_FLAG_AM = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 17U), /*!< ADDR match flag */ + USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 16U), /*!< busy flag */ + USART_FLAG_ABD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 15U), /*!< auto baudrate detection flag */ + USART_FLAG_ABDE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 14U), /*!< auto baudrate detection error */ + USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 12U), /*!< end of block flag */ + USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout flag */ + USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 10U), /*!< CTS level */ + USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ + USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ + USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ + USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ + USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ + USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected flag */ + USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */ + USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ + USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ + USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ + /* flags in RFCS register */ + USART_FLAG_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 11U), /*!< receive FIFO full flag */ + USART_FLAG_RFE = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 10U), /*!< receive FIFO empty flag */ +} usart_flag_enum; + +/* USART interrupt flags */ +typedef enum { + /* interrupt flags in CTL0 register */ + USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U), /*!< end of block interrupt flag */ + USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout interrupt flag */ + USART_INT_FLAG_AM = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U), /*!< address match interrupt flag */ + USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt flag */ + USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt flag */ + USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt flag */ + USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt flag */ + USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< overrun error interrupt flag */ + USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt flag */ + /* interrupt flags in CTL1 register */ + USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt flag */ + /* interrupt flags in CTL2 register */ + USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode interrupt flag */ + USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt flag */ + USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< noise error interrupt flag */ + USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< overrun error interrupt flag */ + USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< frame error interrupt flag */ + /* interrupt flags in RFCS register */ + USART_INT_FLAG_RFFINT = USART_REGIDX_BIT2(USART_RFCS_REG_OFFSET, 9U, USART_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt flag */ +} usart_interrupt_flag_enum; + +/* USART interrupt enable or disable */ +typedef enum { + /* interrupt in CTL0 register */ + USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U), /*!< end of block interrupt */ + USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U), /*!< receiver timeout interrupt */ + USART_INT_AM = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U), /*!< address match interrupt */ + USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ + USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ + USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ + USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ + USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ + /* interrupt in CTL1 register */ + USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ + /* interrupt in CTL2 register */ + USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U), /*!< wakeup from deep-sleep mode interrupt */ + USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ + USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ + /* interrupt in RFCS register */ + USART_INT_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 9U), /*!< receive FIFO full interrupt */ +} usart_interrupt_enum; + +/* USART invert configure */ +typedef enum { + /* data bit level inversion */ + USART_DINV_ENABLE, /*!< data bit level inversion */ + USART_DINV_DISABLE, /*!< data bit level not inversion */ + /* TX pin level inversion */ + USART_TXPIN_ENABLE, /*!< TX pin level inversion */ + USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ + /* RX pin level inversion */ + USART_RXPIN_ENABLE, /*!< RX pin level inversion */ + USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ + /* swap TX/RX pins */ + USART_SWAP_ENABLE, /*!< swap TX/RX pins */ + USART_SWAP_DISABLE, /*!< not swap TX/RX pins */ +} usart_invert_enum; + +/* USART receiver configure */ +#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ +#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ + +/* USART transmitter configure */ +#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) +#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ +#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ + +/* USART parity bits definitions */ +#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) +#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ +#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ +#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ + +/* USART wakeup method in mute mode */ +#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ +#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ + +/* USART word length definitions */ +#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) +#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ +#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ + +/* USART oversample mode */ +#define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15)) +#define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< oversampling by 8 */ +#define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< oversampling by 16 */ + +/* USART address detection mode */ +#define CTL1_ADDM(regval) (BIT(4) & ((uint32_t)(regval) << 4)) +#define USART_ADDM_4BIT CTL1_ADDM(0) /*!< 4-bit address detection */ +#define USART_ADDM_FULLBIT CTL1_ADDM(1) /*!< full-bit address detection */ + +/* USART LIN break frame length */ +#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) +#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits break detection */ +#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits break detection */ + +/* USART last bit clock pulse */ +#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_CLEN_NONE CTL1_CLEN(0) /*!< clock pulse of the last data bit (MSB) is not output to the CK pin */ +#define USART_CLEN_EN CTL1_CLEN(1) /*!< clock pulse of the last data bit (MSB) is output to the CK pin */ + +/* USART clock phase */ +#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ +#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ + +/* USART clock polarity */ +#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) +#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ +#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ + +/* USART stop bits definitions */ +#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) +#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ +#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ +#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ +#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ + +/* USART data is transmitted/received with the LSB/MSB first */ +#define CTL1_MSBF(regval) (BIT(19) & ((uint32_t)(regval) << 19)) +#define USART_MSBF_LSB CTL1_MSBF(0) /*!< LSB first */ +#define USART_MSBF_MSB CTL1_MSBF(1) /*!< MSB first */ + +/* USART auto baud rate detection mode bits definitions */ +#define CTL1_ABDM(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) +#define USART_ABDM_FTOR CTL1_ABDM(0) /*!< falling edge to rising edge measurement */ +#define USART_ABDM_FTOF CTL1_ABDM(1) /*!< falling edge to falling edge measurement */ + +/* USART IrDA low-power enable */ +#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ +#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ + +/* DMA enable for reception */ +#define CTL2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) +#define USART_DENR_ENABLE CTL2_DENR(1) /*!< enable for reception */ +#define USART_DENR_DISABLE CTL2_DENR(0) /*!< disable for reception */ + +/* DMA enable for transmission */ +#define CTL2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) +#define USART_DENT_ENABLE CTL2_DENT(1) /*!< enable for transmission */ +#define USART_DENT_DISABLE CTL2_DENT(0) /*!< disable for transmission */ + +/* USART RTS hardware flow control configure */ +#define CTL2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_RTS_ENABLE CTL2_RTSEN(1) /*!< RTS hardware flow control enabled */ +#define USART_RTS_DISABLE CTL2_RTSEN(0) /*!< RTS hardware flow control disabled */ + +/* USART CTS hardware flow control configure */ +#define CTL2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CTS_ENABLE CTL2_CTSEN(1) /*!< CTS hardware flow control enabled */ +#define USART_CTS_DISABLE CTL2_CTSEN(0) /*!< CTS hardware flow control disabled */ + +/* USART one sample bit method configure */ +#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_OSB_1BIT CTL2_OSB(1) /*!< 1 sample bit */ +#define USART_OSB_3BIT CTL2_OSB(0) /*!< 3 sample bits */ + +/* USART driver enable polarity mode */ +#define CTL2_DEP(regval) (BIT(15) & ((uint32_t)(regval) << 15)) +#define USART_DEP_HIGH CTL2_DEP(0) /*!< DE signal is active high */ +#define USART_DEP_LOW CTL2_DEP(1) /*!< DE signal is active low */ + +/* USART wakeup mode from deep-sleep mode */ +#define CTL2_WUM(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) +#define USART_WUM_ADDR CTL2_WUM(0) /*!< WUF active on address match */ +#define USART_WUM_STARTB CTL2_WUM(2) /*!< WUF active on start bit */ +#define USART_WUM_RBNE CTL2_WUM(3) /*!< WUF active on RBNE */ + +/* function declarations */ +/* initialization functions */ +/* reset USART */ +void usart_deinit(uint32_t usart_periph); +/* configure USART baud rate value */ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); +/* configure USART parity function */ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); +/* configure USART word length */ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); +/* configure USART stop bit length */ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); +/* enable USART */ +void usart_enable(uint32_t usart_periph); +/* disable USART */ +void usart_disable(uint32_t usart_periph); +/* configure USART transmitter */ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); +/* configure USART receiver */ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); + +/* USART normal mode communication */ +/* data is transmitted/received with the LSB/MSB first */ +void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); +/* configure USART inverted */ +void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); +/* enable the USART overrun function */ +void usart_overrun_enable(uint32_t usart_periph); +/* disable the USART overrun function */ +void usart_overrun_disable(uint32_t usart_periph); +/* configure the USART oversample mode */ +void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp); +/* configure sample bit method */ +void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb); +/* enable receiver timeout */ +void usart_receiver_timeout_enable(uint32_t usart_periph); +/* disable receiver timeout */ +void usart_receiver_timeout_disable(uint32_t usart_periph); +/* configure receiver timeout threshold */ +void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); +/* USART transmit data function */ +void usart_data_transmit(uint32_t usart_periph, uint32_t data); +/* USART receive data function */ +uint16_t usart_data_receive(uint32_t usart_periph); + +/* auto baud rate detection */ +/* enable auto baud rate detection */ +void usart_autobaud_detection_enable(uint32_t usart_periph); +/* disable auto baud rate detection */ +void usart_autobaud_detection_disable(uint32_t usart_periph); +/* configure auto baud rate detection mode */ +void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod); + +/* multi-processor communication */ +/* configure the address of the USART in wake up by address match mode */ +void usart_address_config(uint32_t usart_periph, uint8_t addr); +/* configure address detection mode */ +void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod); +/* enable mute mode */ +void usart_mute_mode_enable(uint32_t usart_periph); +/* disable mute mode */ +void usart_mute_mode_disable(uint32_t usart_periph); +/* configure wakeup method in mute mode */ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); + +/* LIN mode communication */ +/* enable LIN mode */ +void usart_lin_mode_enable(uint32_t usart_periph); +/* disable LIN mode */ +void usart_lin_mode_disable(uint32_t usart_periph); +/* configure LIN break frame length */ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); + +/* half-duplex communication */ +/* enable half-duplex mode */ +void usart_halfduplex_enable(uint32_t usart_periph); +/* disable half-duplex mode */ +void usart_halfduplex_disable(uint32_t usart_periph); + +/* synchronous communication */ +/* enable USART clock */ +void usart_clock_enable(uint32_t usart_periph); +/* disable USART clock */ +void usart_clock_disable(uint32_t usart_periph); +/* configure USART synchronous mode parameters */ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); + +/* smartcard communication */ +/* configure guard time value in smartcard mode */ +void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); +/* enable smartcard mode */ +void usart_smartcard_mode_enable(uint32_t usart_periph); +/* disable smartcard mode */ +void usart_smartcard_mode_disable(uint32_t usart_periph); +/* enable NACK in smartcard mode */ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph); +/* disable NACK in smartcard mode */ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph); +/* enable early NACK in smartcard mode */ +void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph); +/* disable early NACK in smartcard mode */ +void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph); +/* configure smartcard auto-retry number */ +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); +/* configure block length */ +void usart_block_length_config(uint32_t usart_periph, uint32_t bl); + +/* IrDA communication */ +/* enable IrDA mode */ +void usart_irda_mode_enable(uint32_t usart_periph); +/* disable IrDA mode */ +void usart_irda_mode_disable(uint32_t usart_periph); +/* configure the peripheral clock prescaler in USART IrDA low-power mode or SmartCard mode */ +void usart_prescaler_config(uint32_t usart_periph, uint32_t psc); +/* configure IrDA low-power */ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); + +/* hardware flow communication */ +/* configure hardware flow control RTS */ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); +/* configure hardware flow control CTS */ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); + +/* enable RS485 driver */ +void usart_rs485_driver_enable(uint32_t usart_periph); +/* disable RS485 driver */ +void usart_rs485_driver_disable(uint32_t usart_periph); +/* configure driver enable assertion time */ +void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime); +/* configure driver enable de-assertion time */ +void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime); +/* configure driver enable polarity mode */ +void usart_depolarity_config(uint32_t usart_periph, uint32_t dep); + +/* USART DMA */ +/* configure USART DMA for reception */ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); +/* configure USART DMA for transmission */ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); +/* disable DMA on reception error */ +void usart_reception_error_dma_disable(uint32_t usart_periph); +/* enable DMA on reception error */ +void usart_reception_error_dma_enable(uint32_t usart_periph); + +/* enable USART to wakeup the mcu from deep-sleep mode */ +void usart_wakeup_enable(uint32_t usart_periph); +/* disable USART to wakeup the mcu from deep-sleep mode */ +void usart_wakeup_disable(uint32_t usart_periph); +/* configure the USART wakeup mode from deep-sleep mode */ +void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum); +/* enable USART command */ +void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype); + +/* USART receive FIFO */ +/* enable receive FIFO */ +void usart_receive_fifo_enable(uint32_t usart_periph); +/* disable receive FIFO */ +void usart_receive_fifo_disable(uint32_t usart_periph); +/* read receive FIFO counter number */ +uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph); + +/* flag & interrupt functions */ +/* get flag in STAT/RFCS register */ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); +/* clear flag in STAT register */ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); +/* enable USART interrupt */ +void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); +/* disable USART interrupt */ +void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); +/* get USART interrupt and flag status */ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); +/* clear USART interrupt flag */ +void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); + +#endif /* GD32F3X0_USART_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_wwdgt.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_wwdgt.h new file mode 100644 index 000000000..5fe0161f7 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Include/gd32f3x0_wwdgt.h @@ -0,0 +1,95 @@ +/*! + \file gd32f3x0_wwdgt.h + \brief definitions for the WWDGT + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32F3X0_WWDGT_H +#define GD32F3X0_WWDGT_H + +#include "gd32f3x0.h" + +/* WWDGT definitions */ +#define WWDGT WWDGT_BASE + +/* registers definitions */ +#define WWDGT_CTL REG32(WWDGT + 0x00000000U) /*!< WWDGT control register */ +#define WWDGT_CFG REG32(WWDGT + 0x00000004U) /*!< WWDGT configuration register */ +#define WWDGT_STAT REG32(WWDGT + 0x00000008U) /*!< WWDGT status register */ + +/* bits definitions */ +/* WWDGT_CTL */ +#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ +#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ + +/* WWDGT_CFG */ +#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ +#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ +#define WWDGT_CFG_EWIE BIT(9) /*!< WWDGT early wakeup interrupt enable */ + +/* WWDGT_STAT */ +#define WWDGT_STAT_EWIF BIT(0) /*!< WWDGT early wakeup interrupt flag */ + +/* constants definitions */ +/* WWDGT_CTL register value */ +#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to WWDGT_CTL_CNT bit field */ + +/* WWDGT_CFG register value */ +#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to WWDGT_CFG_WIN bit field */ + +#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7U)) /*!< write value to WWDGT_CFG_PSC bit field */ +#define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0)) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ +#define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1)) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ +#define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2)) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ +#define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3)) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ + +/* function declarations */ +/* reset the window watchdog timer configuration */ +void wwdgt_deinit(void); +/* start the window watchdog timer counter */ +void wwdgt_enable(void); + +/* configure the window watchdog timer counter value */ +void wwdgt_counter_update(uint16_t counter_value); +/* configure counter value, window value, and prescaler divider value */ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); + +/* enable early wakeup interrupt of WWDGT */ +void wwdgt_interrupt_enable(void); +/* check early wakeup interrupt state of WWDGT */ +FlagStatus wwdgt_flag_get(void); +/* clear early wakeup interrupt state of WWDGT */ +void wwdgt_flag_clear(void); + +#endif /* GD32F3X0_WWDGT_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_adc.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_adc.c new file mode 100644 index 000000000..c8ad5cde8 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_adc.c @@ -0,0 +1,871 @@ +/*! + \file gd32f3x0_adc.c + \brief ADC driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_adc.h" + +/*! + \brief reset ADC + \param[in] none + \param[out] none + \retval none +*/ +void adc_deinit(void) +{ + rcu_periph_reset_enable(RCU_ADCRST); + rcu_periph_reset_disable(RCU_ADCRST); +} + +/*! + \brief enable ADC interface + \param[in] none + \param[out] none + \retval none +*/ +void adc_enable(void) +{ + if(RESET == (ADC_CTL1 & ADC_CTL1_ADCON)) { + ADC_CTL1 |= (uint32_t)ADC_CTL1_ADCON; + } +} + +/*! + \brief disable ADC interface + \param[in] none + \param[out] none + \retval none +*/ +void adc_disable(void) +{ + ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ADCON); +} + +/*! + \brief ADC calibration and reset calibration + \param[in] none + \param[out] none + \retval none +*/ +void adc_calibration_enable(void) +{ + /* reset the selected ADC calibration register */ + ADC_CTL1 |= (uint32_t) ADC_CTL1_RSTCLB; + /* check the RSTCLB bit state */ + while((ADC_CTL1 & ADC_CTL1_RSTCLB)) { + } + + /* enable ADC calibration process */ + ADC_CTL1 |= ADC_CTL1_CLB; + /* check the CLB bit state */ + while((ADC_CTL1 & ADC_CTL1_CLB)) { + } +} + +/*! + \brief enable DMA request + \param[in] none + \param[out] none + \retval none +*/ +void adc_dma_mode_enable(void) +{ + ADC_CTL1 |= (uint32_t)(ADC_CTL1_DMA); +} + +/*! + \brief disable DMA request + \param[in] none + \param[out] none + \retval none +*/ +void adc_dma_mode_disable(void) +{ + ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DMA); +} + +/*! + \brief enable the temperature sensor and Vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_vrefint_enable(void) +{ + /* enable the temperature sensor and Vrefint channel */ + ADC_CTL1 |= ADC_CTL1_TSVREN; +} + +/*! + \brief disable the temperature sensor and Vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_vrefint_disable(void) +{ + /* disable the temperature sensor and Vrefint channel */ + ADC_CTL1 &= ~ADC_CTL1_TSVREN; +} + +/*! + \brief enable the Vbat channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_vbat_enable(void) +{ + /* enable the vbat channel */ + ADC_CTL1 |= ADC_CTL1_VBETEN; +} + +/*! + \brief disable the Vbat channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_vbat_disable(void) +{ + /* disable the vbat channel */ + ADC_CTL1 &= ~ADC_CTL1_VBETEN; +} + +/*! + \brief configure ADC discontinuous mode + \param[in] channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular and inserted channel + \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 + for regular channel, the number has no effect for inserted channel + \param[out] none + \retval none +*/ +void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length) +{ + ADC_CTL0 &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); + + switch(channel_group) { + case ADC_REGULAR_CHANNEL: + /* configure the number of conversions in discontinuous mode */ + ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DISNUM); + ADC_CTL0 |= CTL0_DISNUM(((uint32_t)length - 1U)); + ADC_CTL0 |= (uint32_t)ADC_CTL0_DISRC; + break; + case ADC_INSERTED_CHANNEL: + ADC_CTL0 |= (uint32_t)ADC_CTL0_DISIC; + break; + case ADC_CHANNEL_DISCON_DISABLE: + default: + break; + } +} + +/*! + \brief enable or disable ADC special function + \param[in] function: the function to configure + one or more parameters can be selected which is shown as below: + \arg ADC_SCAN_MODE: scan mode select + \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically + \arg ADC_CONTINUOUS_MODE: continuous mode select + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_special_function_config(uint32_t function, ControlStatus newvalue) +{ + if(newvalue) { + /* enable ADC scan mode */ + if(RESET != (function & ADC_SCAN_MODE)) { + ADC_CTL0 |= ADC_SCAN_MODE; + } + /* enable ADC inserted channel group convert automatically */ + if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)) { + ADC_CTL0 |= ADC_INSERTED_CHANNEL_AUTO; + } + /* enable ADC continuous mode */ + if(RESET != (function & ADC_CONTINUOUS_MODE)) { + ADC_CTL1 |= ADC_CONTINUOUS_MODE; + } + } else { + /* disable ADC scan mode */ + if(RESET != (function & ADC_SCAN_MODE)) { + ADC_CTL0 &= ~ADC_SCAN_MODE; + } + /* disable ADC inserted channel group convert automatically */ + if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)) { + ADC_CTL0 &= ~ADC_INSERTED_CHANNEL_AUTO; + } + /* disable ADC continuous mode */ + if(RESET != (function & ADC_CONTINUOUS_MODE)) { + ADC_CTL1 &= ~ADC_CONTINUOUS_MODE; + } + } +} + +/*! + \brief configure ADC data alignment + \param[in] data_alignment: data alignment select + only one parameter can be selected which is shown as below: + \arg ADC_DATAALIGN_RIGHT: right alignment + \arg ADC_DATAALIGN_LEFT: left alignment + \param[out] none + \retval none +*/ +void adc_data_alignment_config(uint32_t data_alignment) +{ + if(ADC_DATAALIGN_RIGHT != data_alignment) { + ADC_CTL1 |= ADC_CTL1_DAL; + } else { + ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DAL); + } +} + +/*! + \brief configure the length of regular channel group or inserted channel group + \param[in] channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] length: the length of the channel + regular channel 1-16 + inserted channel 1-4 + \param[out] none + \retval none +*/ +void adc_channel_length_config(uint8_t channel_group, uint32_t length) +{ + switch(channel_group) { + case ADC_REGULAR_CHANNEL: + /* configure the length of regular channel group */ + ADC_RSQ0 &= ~((uint32_t)ADC_RSQ0_RL); + ADC_RSQ0 |= RSQ0_RL((uint32_t)(length - 1U)); + break; + case ADC_INSERTED_CHANNEL: + /* configure the length of inserted channel group */ + ADC_ISQ &= ~((uint32_t)ADC_ISQ_IL); + ADC_ISQ |= ISQ_IL((uint32_t)(length - 1U)); + break; + default: + break; + } +} + +/*! + \brief configure ADC regular channel + \param[in] rank: the regular group sequence rank, this parameter must be between 0 to 15 + \param[in] channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..18): ADC Channelx + \param[in] sample_time: the sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles + \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles + \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles + \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles + \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles + \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles + \param[out] none + \retval none +*/ +void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time) +{ + uint32_t rsq, sampt; + + /* configure ADC regular sequence */ + if(rank < 6U) { + rsq = ADC_RSQ2; + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U * rank))); + rsq |= ((uint32_t)channel << (5U * rank)); + ADC_RSQ2 = rsq; + } else if(rank < 12U) { + rsq = ADC_RSQ1; + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U * (rank - 6U)))); + rsq |= ((uint32_t)channel << (5U * (rank - 6U))); + ADC_RSQ1 = rsq; + } else if(rank < 16U) { + rsq = ADC_RSQ0; + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U * (rank - 12U)))); + rsq |= ((uint32_t)channel << (5U * (rank - 12U))); + ADC_RSQ0 = rsq; + } else { + } + + /* configure ADC sampling time */ + if(channel < 10U) { + sampt = ADC_SAMPT1; + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * channel))); + sampt |= (uint32_t)(sample_time << (3U * channel)); + ADC_SAMPT1 = sampt; + } else if(channel < 19U) { + sampt = ADC_SAMPT0; + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * (channel - 10U)))); + sampt |= (uint32_t)(sample_time << (3U * (channel - 10U))); + ADC_SAMPT0 = sampt; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure ADC inserted channel + \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 + \param[in] channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..18): ADC Channelx + \param[in] sample_time: The sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles + \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles + \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles + \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles + \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles + \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles + \param[out] none + \retval none +*/ +void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time) +{ + uint8_t inserted_length; + uint32_t isq, sampt; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20U, 21U); + + isq = ADC_ISQ; + isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U - (inserted_length - rank) * 5U))); + isq |= ((uint32_t)channel << (15U - (inserted_length - rank) * 5U)); + ADC_ISQ = isq; + + /* configure ADC sampling time */ + if(channel < 10U) { + sampt = ADC_SAMPT1; + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * channel))); + sampt |= (uint32_t) sample_time << (3U * channel); + ADC_SAMPT1 = sampt; + } else if(channel < 19U) { + sampt = ADC_SAMPT0; + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * (channel - 10U)))); + sampt |= ((uint32_t)sample_time << (3U * (channel - 10U))); + ADC_SAMPT0 = sampt; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure ADC inserted channel offset + \param[in] inserted_channel: insert channel select + only one parameter can be selected which is shown as below: + \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel 0 + \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel 1 + \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel 2 + \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel 3 + \param[in] offset: the offset data + \param[out] none + \retval none +*/ +void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset) +{ + uint8_t inserted_length; + uint32_t num = 0U; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20U, 21U); + num = 3U - (inserted_length - inserted_channel); + + if(num <= 3U) { + /* calculate the offset of the register */ + num = num * 4U; + /* configure the offset of the selected channels */ + REG32((ADC) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); + } +} + +/*! + \brief enable or disable ADC external trigger + \param[in] channel_group: select the channel group + one or more parameters can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue) +{ + if(newvalue) { + /* external trigger enable for regular channel */ + if(RESET != (channel_group & ADC_REGULAR_CHANNEL)) { + ADC_CTL1 |= ADC_CTL1_ETERC; + } + /* external trigger enable for inserted channel */ + if(RESET != (channel_group & ADC_INSERTED_CHANNEL)) { + ADC_CTL1 |= ADC_CTL1_ETEIC; + } + } else { + /* external trigger disable for regular channel */ + if(RESET != (channel_group & ADC_REGULAR_CHANNEL)) { + ADC_CTL1 &= ~ADC_CTL1_ETERC; + } + /* external trigger disable for inserted channel */ + if(RESET != (channel_group & ADC_INSERTED_CHANNEL)) { + ADC_CTL1 &= ~ADC_CTL1_ETEIC; + } + } +} + +/*! + \brief configure ADC external trigger source + \param[in] channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] external_trigger_source: regular or inserted group trigger source + only one parameter can be selected which is shown as below: + for regular channel: + \arg ADC_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select + \arg ADC_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select + \arg ADC_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select + \arg ADC_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select + \arg ADC_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select + \arg ADC_EXTTRIG_REGULAR_T14_CH0: TIMER14 CH0 event select + \arg ADC_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11 + \arg ADC_EXTTRIG_REGULAR_NONE: software trigger + for inserted channel: + \arg ADC_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select + \arg ADC_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select + \arg ADC_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select + \arg ADC_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select + \arg ADC_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select + \arg ADC_EXTTRIG_INSERTED_T14_TRGO: TIMER14 TRGO event select + \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 + \arg ADC_EXTTRIG_INSERTED_NONE: software trigger + \param[out] none + \retval none +*/ +void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source) +{ + switch(channel_group) { + case ADC_REGULAR_CHANNEL: + /* external trigger select for regular channel */ + ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSRC); + ADC_CTL1 |= (uint32_t)external_trigger_source; + break; + case ADC_INSERTED_CHANNEL: + /* external trigger select for inserted channel */ + ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSIC); + ADC_CTL1 |= (uint32_t)external_trigger_source; + break; + default: + break; + } +} + +/*! + \brief enable ADC software trigger + \param[in] channel_group: select the channel group + one or more parameters can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[out] none + \retval none +*/ +void adc_software_trigger_enable(uint8_t channel_group) +{ + /* enable regular group channel software trigger */ + if(RESET != (channel_group & ADC_REGULAR_CHANNEL)) { + ADC_CTL1 |= ADC_CTL1_SWRCST; + } + /* enable inserted channel group software trigger */ + if(RESET != (channel_group & ADC_INSERTED_CHANNEL)) { + ADC_CTL1 |= ADC_CTL1_SWICST; + } +} + +/*! + \brief read ADC regular group data register + \param[in] none + \param[out] none + \retval the conversion value +*/ +uint16_t adc_regular_data_read(void) +{ + return ((uint16_t)ADC_RDATA); +} + +/*! + \brief read ADC inserted group data register + \param[in] inserted_channel: inserted channel select + only one parameter can be selected which is shown as below: + \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel 0 + \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel 1 + \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel 2 + \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel 3 + \param[out] none + \retval the conversion value +*/ +uint16_t adc_inserted_data_read(uint8_t inserted_channel) +{ + uint32_t idata; + /* read the data of the selected channel */ + switch(inserted_channel) { + case ADC_INSERTED_CHANNEL_0: + idata = ADC_IDATA0; + break; + case ADC_INSERTED_CHANNEL_1: + idata = ADC_IDATA1; + break; + case ADC_INSERTED_CHANNEL_2: + idata = ADC_IDATA2; + break; + case ADC_INSERTED_CHANNEL_3: + idata = ADC_IDATA3; + break; + default: + idata = 0U; + break; + } + return (uint16_t)idata; +} + +/*! + \brief configure ADC analog watchdog single channel + \param[in] channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..18): ADC Channelx + \param[out] none + \retval none +*/ +void adc_watchdog_single_channel_enable(uint8_t channel) +{ + ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); + + ADC_CTL0 |= (uint32_t)channel; + ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); +} + +/*! + \brief configure ADC analog watchdog group channel + \param[in] channel_group: the channel group use analog watchdog + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \param[out] none + \retval none +*/ +void adc_watchdog_group_channel_enable(uint8_t channel_group) +{ + ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); + + /* select the group */ + switch(channel_group) { + case ADC_REGULAR_CHANNEL: + ADC_CTL0 |= (uint32_t)ADC_CTL0_RWDEN; + break; + case ADC_INSERTED_CHANNEL: + ADC_CTL0 |= (uint32_t)ADC_CTL0_IWDEN; + break; + case ADC_REGULAR_INSERTED_CHANNEL: + ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); + break; + default: + break; + } +} + +/*! + \brief disable ADC analog watchdog + \param[in] none + \param[out] none + \retval none +*/ +void adc_watchdog_disable(void) +{ + ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); +} + +/*! + \brief configure ADC analog watchdog threshold + \param[in] low_threshold: analog watchdog low threshold,0..4095 + \param[in] high_threshold: analog watchdog high threshold,0..4095 + \param[out] none + \retval none +*/ +void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold) +{ + ADC_WDLT = (uint32_t)WDLT_WDLT(low_threshold); + ADC_WDHT = (uint32_t)WDHT_WDHT(high_threshold); +} + +/*! + \brief configure ADC resolution + \param[in] resolution: ADC resolution + only one parameter can be selected which is shown as below: + \arg ADC_RESOLUTION_12B: 12-bit ADC resolution + \arg ADC_RESOLUTION_10B: 10-bit ADC resolution + \arg ADC_RESOLUTION_8B: 8-bit ADC resolution + \arg ADC_RESOLUTION_6B: 6-bit ADC resolution + \param[out] none + \retval none +*/ +void adc_resolution_config(uint32_t resolution) +{ + ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DRES); + ADC_CTL0 |= (uint32_t)resolution; +} + +/*! + \brief configure ADC oversample mode + \param[in] mode: ADC oversampling mode + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger + \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger + \param[in] shift: ADC oversampling shift + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift + \param[in] ratio: ADC oversampling ratio + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 + \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 + \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 + \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 + \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 + \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 + \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 + \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 + \param[out] none + \retval none +*/ +void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio) +{ + /* configure ADC oversampling mode */ + if(ADC_OVERSAMPLING_ONE_CONVERT == mode) { + ADC_OVSAMPCTL |= (uint32_t)ADC_OVSAMPCTL_TOVS; + } else { + ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); + } + + /* configure the shift and ratio */ + ADC_OVSAMPCTL &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); + ADC_OVSAMPCTL |= ((uint32_t)shift | (uint32_t)ratio); +} + +/*! + \brief enable ADC oversample mode + \param[in] none + \param[out] none + \retval none +*/ +void adc_oversample_mode_enable(void) +{ + ADC_OVSAMPCTL |= ADC_OVSAMPCTL_OVSEN; +} + +/*! + \brief disable ADC oversample mode + \param[in] none + \param[out] none + \retval none +*/ +void adc_oversample_mode_disable(void) +{ + ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); +} + +/*! + \brief get the ADC flag bits + \param[in] flag: the adc flag bits + only one parameter can be selected which is shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_flag_get(uint32_t flag) +{ + FlagStatus reval = RESET; + + if(ADC_STAT & flag) { + reval = SET; + } + return reval; +} + +/*! + \brief clear the ADC flag + \param[in] flag: the adc flag + one or more parameters can be selected which is shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \param[out] none + \retval none +*/ +void adc_flag_clear(uint32_t flag) +{ + ADC_STAT &= ~((uint32_t)flag); +} + +/*! + \brief enable ADC interrupt + \param[in] interrupt: the adc interrupt + one or more parameters can be selected which is shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt + \arg ADC_INT_EOC: end of group conversion interrupt + \arg ADC_INT_EOIC: end of inserted group conversion interrupt + \param[out] none + \retval none +*/ +void adc_interrupt_enable(uint32_t interrupt) +{ + /* enable analog watchdog interrupt */ + if(RESET != (interrupt & ADC_INT_WDE)) { + ADC_CTL0 |= (uint32_t)ADC_CTL0_WDEIE; + } + + /* enable end of group conversion interrupt */ + if(RESET != (interrupt & ADC_INT_EOC)) { + ADC_CTL0 |= (uint32_t)ADC_CTL0_EOCIE; + } + + /* enable end of inserted group conversion interrupt */ + if(RESET != (interrupt & ADC_INT_EOIC)) { + ADC_CTL0 |= (uint32_t)ADC_CTL0_EOICIE; + } +} + +/*! + \brief disable ADC interrupt + \param[in] interrupt: the adc interrupt flag + one or more parameters can be selected which is shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt + \arg ADC_INT_EOC: end of group conversion interrupt + \arg ADC_INT_EOIC: end of inserted group conversion interrupt + \param[out] none + \retval none +*/ +void adc_interrupt_disable(uint32_t interrupt) +{ + /* disable analog watchdog interrupt */ + if(RESET != (interrupt & ADC_INT_WDE)) { + ADC_CTL0 &= ~(uint32_t)ADC_CTL0_WDEIE; + } + + /* disable end of group conversion interrupt */ + if(RESET != (interrupt & ADC_INT_EOC)) { + ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOCIE; + } + + /* disable end of inserted group conversion interrupt */ + if(RESET != (interrupt & ADC_INT_EOIC)) { + ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOICIE; + } +} + +/*! + \brief get the ADC interrupt flag + \param[in] flag: the adc interrupt flag + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_interrupt_flag_get(uint32_t flag) +{ + FlagStatus interrupt_flag = RESET; + uint32_t state; + + /* check the interrupt bits */ + switch(flag) { + case ADC_INT_FLAG_WDE: + state = ADC_STAT & ADC_STAT_WDE; + if((ADC_CTL0 & ADC_CTL0_WDEIE) && state) { + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOC: + state = ADC_STAT & ADC_STAT_EOC; + if((ADC_CTL0 & ADC_CTL0_EOCIE) && state) { + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOIC: + state = ADC_STAT & ADC_STAT_EOIC; + if((ADC_CTL0 & ADC_CTL0_EOICIE) && state) { + interrupt_flag = SET; + } + break; + default: + break; + } + return interrupt_flag; +} + +/*! + \brief clear ADC interrupt flag + \param[in] flag: the adc interrupt flag + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_flag_clear(uint32_t flag) +{ + ADC_STAT &= ~((uint32_t)flag); +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_cec.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_cec.c new file mode 100644 index 000000000..b2d4f9144 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_cec.c @@ -0,0 +1,500 @@ +/*! + \file gd32f3x0_cec.c + \brief CEC driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifdef GD32F350 + +#include "gd32f3x0_cec.h" + +/*! + \brief reset HDMI-CEC controller + \param[in] none + \param[out] none + \retval none +*/ +void cec_deinit(void) +{ + rcu_periph_reset_enable(RCU_CECRST); + rcu_periph_reset_disable(RCU_CECRST); +} + +/*! + \brief configure signal free time,the signal free time counter start option,own address + \param[in] sftmopt: signal free time counter start option + only one parameter can be selected which is shown as below: + \arg CEC_SFT_START_STAOM: signal free time counter starts counting when STAOM is asserted + \arg CEC_SFT_START_LAST: signal free time counter starts automatically after transmission/reception end + \param[in] sft: signal free time + only one parameter can be selected which is shown as below: + \arg CEC_SFT_PROTOCOL_PERIOD: the signal free time will perform as HDMI-CEC protocol description + \arg CEC_SFT_1POINT5_PERIOD: 1.5 nominal data bit periods + \arg CEC_SFT_2POINT5_PERIOD: 2.5 nominal data bit periods + \arg CEC_SFT_3POINT5_PERIOD: 3.5 nominal data bit periods + \arg CEC_SFT_4POINT5_PERIOD: 4.5 nominal data bit periods + \arg CEC_SFT_5POINT5_PERIOD: 5.5 nominal data bit periods + \arg CEC_SFT_6POINT5_PERIOD: 6.5 nominal data bit periods + \arg CEC_SFT_7POINT5_PERIOD: 7.5 nominal data bit periods + \param[in] address: own address + only one parameter can be selected which is shown as below: + \arg CEC_OWN_ADDRESS_CLEAR: own address is cleared + \arg CEC_OWN_ADDRESSx(x=0..14): own address is x + \param[out] none + \retval none +*/ +void cec_init(uint32_t sftmopt, uint32_t sft, uint32_t address) +{ + uint32_t cfg; + cfg = CEC_CFG; + /* clear SFTMOPT bit,SFT[2:0] */ + cfg &= ~(CEC_CFG_SFTOPT | CEC_CFG_SFT); + /* assign SFTMOPT bit,SFT[2:0] */ + cfg |= (sftmopt | sft); + CEC_CFG = cfg; + if(CEC_OWN_ADDRESS_CLEAR == address){ + CEC_CFG &= ~CEC_CFG_OAD; + }else{ + CEC_CFG |= address; + } +} + +/*! + \brief configure generate Error-bit when detected some abnormal situation or not, + whether stop receive message when detected bit rising error + \param[in] broadcast: + only one parameter can be selected which is shown as below: + \arg CEC_BROADCAST_ERROR_BIT_ON:generate Error-bit in broadcast + \arg CEC_BROADCAST_ERROR_BIT_OFF:do not generate Error-bit in broadcast + \param[in] singlecast_lbpe: + only one parameter can be selected which is shown as below: + \arg CEC_LONG_PERIOD_ERROR_BIT_ON:generate Error-bit on long bit period error + \arg CEC_LONG_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on long bit period error + \param[in] singlecast_bre: + only one parameter can be selected which is shown as below: + \arg CEC_RISING_PERIOD_ERROR_BIT_ON:generate Error-bit on bit rising error + \arg CEC_RISING_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on bit rising error + \param[in] rxbrestp: + only one parameter can be selected which is shown as below: + \arg CEC_STOP_RISING_ERROR_BIT_ON: stop reception when detected bit rising error + \arg CEC_STOP_RISING_ERROR_BIT_OFF: do not stop reception when detected bit rising error + \param[out] none + \retval none +*/ +void cec_error_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre, uint32_t rxbrestp) +{ + uint32_t cfg; + cfg = CEC_CFG; + /* clear BCNG bit, BPLEG bit, BREG bit */ + cfg &= ~(CEC_CFG_BCNG | CEC_CFG_BPLEG | CEC_CFG_BREG); + /* assign BCNG bit, BPLEG bit, BREG bit */ + cfg |= (broadcast | singlecast_lbpe | singlecast_bre); + CEC_CFG = cfg; + if(CEC_STOP_RISING_ERROR_BIT_ON == rxbrestp){ + CEC_CFG |= CEC_CFG_BRES; + }else{ + CEC_CFG &= ~CEC_CFG_BRES; + } +} + +/*! + \brief enable HDMI-CEC controller + \param[in] none + \param[out] none + \retval none +*/ +void cec_enable(void) +{ + CEC_CTL |= CEC_CTL_CECEN; +} + +/*! + \brief disable HDMI-CEC controller + \param[in] none + \param[out] none + \retval none +*/ +void cec_disable(void) +{ + CEC_CTL &= ~CEC_CTL_CECEN; +} + +/*! + \brief start CEC message transmission + \param[in] none + \param[out] none + \retval none +*/ +void cec_transmission_start(void) +{ + CEC_CTL |= CEC_CTL_STAOM; +} + +/*! + \brief end CEC message transmission + \param[in] none + \param[out] none + \retval none +*/ +void cec_transmission_end(void) +{ + CEC_CTL |= CEC_CTL_ENDOM; +} + +/*! + \brief enable CEC listen mode. + \param[in] none + \param[out] none + \retval none +*/ +void cec_listen_mode_enable(void) +{ + CEC_CFG |= CEC_CFG_LMEN; +} + +/*! + \brief disable CEC listen mode. + \param[in] none + \param[out] none + \retval none +*/ +void cec_listen_mode_disable(void) +{ + CEC_CFG &= ~CEC_CFG_LMEN; +} + +/*! + \brief configure and clear own address.the controller can be configured to multiple own address + \param[in] address: own address + one or more parameters can be selected which are shown as below: + \arg CEC_OWN_ADDRESS_CLEAR: own address is cleared + \arg CEC_OWN_ADDRESSx(x=0..14): own address is x + \param[out] none + \retval none +*/ +void cec_own_address_config(uint32_t address) +{ + if(CEC_OWN_ADDRESS_CLEAR == address){ + CEC_CFG &= ~CEC_CFG_OAD; + }else{ + CEC_CFG |= address; + } +} + +/*! + \brief configure signal free time and the signal free time counter start option + \param[in] sftmopt: signal free time counter start option + only one parameter can be selected which is shown as below: + \arg CEC_SFT_START_STAOM: signal free time counter starts counting when STAOM is asserted + \arg CEC_SFT_START_LAST: signal free time counter starts automatically after transmission/reception end + \param[in] sft: signal free time + only one parameter can be selected which is shown as below: + \arg CEC_SFT_PROTOCOL_PERIOD: the signal free time will perform as HDMI-CEC protocol description + \arg CEC_SFT_1POINT5_PERIOD: 1.5 nominal data bit periods + \arg CEC_SFT_2POINT5_PERIOD: 2.5 nominal data bit periods + \arg CEC_SFT_3POINT5_PERIOD: 3.5 nominal data bit periods + \arg CEC_SFT_4POINT5_PERIOD: 4.5 nominal data bit periods + \arg CEC_SFT_5POINT5_PERIOD: 5.5 nominal data bit periods + \arg CEC_SFT_6POINT5_PERIOD: 6.5 nominal data bit periods + \arg CEC_SFT_7POINT5_PERIOD: 7.5 nominal data bit periods + \param[out] none + \retval none +*/ +void cec_sft_config(uint32_t sftmopt, uint32_t sft) +{ + uint32_t cfg; + cfg = CEC_CFG; + /* clear SFTMOPT bit,SFT[2:0] */ + cfg &= ~(CEC_CFG_SFTOPT | CEC_CFG_SFT); + /* assign SFTMOPT bit,SFT[2:0] */ + cfg |= (sftmopt | sft); + CEC_CFG = cfg; +} + +/*! + \brief configure generate Error-bit when detected some abnormal situation or not + \param[in] broadcast: + only one parameter can be selected which is shown as below: + \arg CEC_BROADCAST_ERROR_BIT_ON:generate Error-bit in broadcast + \arg CEC_BROADCAST_ERROR_BIT_OFF:do not generate Error-bit in broadcast + \param[in] singlecast_lbpe: + only one parameter can be selected which is shown as below: + \arg CEC_LONG_PERIOD_ERROR_BIT_ON:generate Error-bit on long bit period error + \arg CEC_LONG_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on long bit period error + \param[in] singlecast_bre: + only one parameter can be selected which is shown as below: + \arg CEC_RISING_PERIOD_ERROR_BIT_ON:generate Error-bit on bit rising error + \arg CEC_RISING_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on bit rising error + \param[out] none + \retval none +*/ +void cec_generate_errorbit_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre) +{ + uint32_t cfg; + cfg = CEC_CFG; + /* clear BCNG bit, RLBPEGEN bit, RBREGEN bit */ + cfg &= ~(CEC_CFG_BCNG | CEC_CFG_BPLEG | CEC_CFG_BREG); + /* assign BCNG bit, RLBPEGEN bit, RBREGEN bit */ + cfg |= (broadcast | singlecast_lbpe | singlecast_bre); + CEC_CFG = cfg; +} + +/*! + \brief whether stop receive message when detected bit rising error + \param[in] rxbrestp: + only one parameter can be selected which is shown as below: + \arg CEC_STOP_RISING_ERROR_BIT_ON: stop reception when detected bit rising error + \arg CEC_STOP_RISING_ERROR_BIT_OFF: do not stop reception when detected bit rising error + \param[out] none + \retval none +*/ +void cec_stop_receive_bre_config(uint32_t rxbrestp) +{ + if(CEC_STOP_RISING_ERROR_BIT_ON == rxbrestp){ + CEC_CFG |= CEC_CFG_BRES; + }else{ + CEC_CFG &= ~CEC_CFG_BRES; + } +} + +/*! + \brief enable reception bit timing tolerance + \param[in] none + \param[out] none + \retval none +*/ +void cec_reception_tolerance_enable(void) +{ + CEC_CFG |= CEC_CFG_RTOL; +} + +/*! + \brief disable reception bit timing tolerance + \param[in] none + \param[out] none + \retval none +*/ +void cec_reception_tolerance_disable(void) +{ + CEC_CFG &= ~CEC_CFG_RTOL; +} + +/*! + \brief send a data by the CEC peripheral + \param[in] data: the data to transmit + \param[out] none + \retval none +*/ +void cec_data_send(uint8_t data) +{ + CEC_TDATA = (uint32_t)data; +} + +/*! + \brief receive a data by the CEC peripheral + \param[in] data: the data to receive + \param[out] none + \retval none +*/ +uint8_t cec_data_receive(void) +{ + return (uint8_t)CEC_RDATA; +} + + +/*! + \brief enable interrupt + \param[in] flag: specify which flag + one or more parameters can be selected which are shown as below: + \arg CEC_INT_BR: enable Rx-byte data received interrupt + \arg CEC_INT_REND: enable end of reception interrupt + \arg CEC_INT_RO: enable RX overrun interrupt + \arg CEC_INT_BRE: enable bit rising error interrupt + \arg CEC_INT_BPSE: enable short bit period error interrupt + \arg CEC_INT_BPLE: enable long bit period error interrupt + \arg CEC_INT_RAE: enable Rx ACK error interrupt + \arg CEC_INT_ARBF: enable arbitration lost interrupt + \arg CEC_INT_TBR: enable Tx-byte data request interrupt + \arg CEC_INT_TEND: enable transmission successfully end interrupt + \arg CEC_INT_TU: enable Tx data buffer underrun interrupt + \arg CEC_INT_TERR: enable Tx-error interrupt + \arg CEC_INT_TAERR: enable Tx ACK error interrupt + \param[out] none + \retval none +*/ +void cec_interrupt_enable(uint32_t flag) +{ + CEC_INTEN |= flag; +} + +/*! + \brief disable interrupt + \param[in] flag: specify which flag + one or more parameters can be selected which are shown as below: + \arg CEC_INT_BR: disable Rx-byte data received interrupt + \arg CEC_INT_REND: disable end of reception interrupt + \arg CEC_INT_RO: disable RX overrun interrupt + \arg CEC_INT_BRE: disable bit rising error interrupt + \arg CEC_INT_BPSE: disable short bit period error interrupt + \arg CEC_INT_BPLE: disable long bit period error interrupt + \arg CEC_INT_RAE: disable Rx ACK error interrupt + \arg CEC_INT_ARBF: disable arbitration lost interrupt + \arg CEC_INT_TBR: disable Tx-byte data request interrupt + \arg CEC_INT_TEND: disable transmission successfully end interrupt + \arg CEC_INT_TU: disable Tx data buffer underrun interrupt + \arg CEC_INT_TERR: disable Tx-error interrupt + \arg CEC_INT_TAERR: disable Tx ACK error interrupt + + \param[out] none + \retval none +*/ +void cec_interrupt_disable(uint32_t flag) +{ + CEC_INTEN &= ~flag; +} + + +/*! + \brief get CEC status + \param[in] flag: specify which flag + one or more parameters can be selected which are shown as below: + \arg CEC_FLAG_BR: Rx-byte data received + \arg CEC_FLAG_REND: end of reception + \arg CEC_FLAG_RO: RX overrun + \arg CEC_FLAG_BRE: bit rising error + \arg CEC_FLAG_BPSE: short bit period error + \arg CEC_FLAG_BPLE: long bit period error + \arg CEC_FLAG_RAE: Rx ACK error + \arg CEC_FLAG_ARBF: arbitration lost + \arg CEC_FLAG_TBR: Tx-byte data request + \arg CEC_FLAG_TEND: transmission successfully end + \arg CEC_FLAG_TU: Tx data buffer underrun + \arg CEC_FLAG_TERR: Tx-error + \arg CEC_FLAG_TAERR Tx ACK error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus cec_flag_get(uint32_t flag) +{ + if(CEC_INTF & flag){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear CEC status + \param[in] flag: specify which flag + one or more parameters can be selected which are shown as below: + \arg CEC_FLAG_BR: Rx-byte data received + \arg CEC_FLAG_REND: end of reception + \arg CEC_FLAG_RO: RX overrun + \arg CEC_FLAG_BRE: bit rising error + \arg CEC_FLAG_BPSE: short bit period error + \arg CEC_FLAG_BPLE: long bit period error + \arg CEC_FLAG_RAE: Rx ACK error + \arg CEC_FLAG_ARBF: arbitration lost + \arg CEC_FLAG_TBR: Tx-byte data request + \arg CEC_FLAG_TEND: transmission successfully end + \arg CEC_FLAG_TU: Tx data buffer underrun + \arg CEC_FLAG_TERR: Tx-error + \arg CEC_FLAG_TAERR: Tx ACK error flag + + \param[out] none + \retval FlagStatus: SET or RESET +*/ +void cec_flag_clear(uint32_t flag) +{ + CEC_INTF |= flag; +} + +/*! + \brief get CEC int flag and status + \param[in] flag: specify which flag + one or more parameters can be selected which are shown as below: + \arg CEC_INT_FLAG_BR: Rx-byte data received + \arg CEC_INT_FLAG_REND: end of reception + \arg CEC_INT_FLAG_RO: RX overrun + \arg CEC_INT_FLAG_BRE: bit rising error + \arg CEC_INT_FLAG_BPSE: short bit period error + \arg CEC_INT_FLAG_BPLE: long bit period error + \arg CEC_INT_FLAG_RAE: Rx ACK error + \arg CEC_INT_FLAG_ARBF: arbitration lost + \arg CEC_INT_FLAG_TBR: Tx-byte data request + \arg CEC_INT_FLAG_TEND: transmission successfully end + \arg CEC_INT_FLAG_TU: Tx data buffer underrun + \arg CEC_INT_FLAG_TERR: Tx-error + \arg CEC_INT_FLAG_TAERR: Tx ACK error flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus cec_interrupt_flag_get(uint32_t flag) +{ + uint32_t interrupt_enable = 0U, interrupt_flag = 0U; + interrupt_flag = (CEC_INTF & flag); + interrupt_enable = (CEC_INTEN & flag); + if(interrupt_flag && interrupt_enable){ + return SET; + }else{ + return RESET; + } +} + +/*! + \brief clear CEC int flag and status + \param[in] flag: specify which flag + one or more parameters can be selected which are shown as below: + \arg CEC_INT_FLAG_BR: Rx-byte data received + \arg CEC_INT_FLAG_REND: end of reception + \arg CEC_INT_FLAG_RO: RX overrun + \arg CEC_INT_FLAG_BRE: bit rising error + \arg CEC_INT_FLAG_BPSE: short bit period error + \arg CEC_INT_FLAG_BPLE: long bit period error + \arg CEC_INT_FLAG_RAE: Rx ACK error + \arg CEC_INT_FLAG_ARBF: arbitration lost + \arg CEC_INT_FLAG_TBR: Tx-byte data request + \arg CEC_INT_FLAG_TEND: transmission successfully end + \arg CEC_INT_FLAG_TU: Tx data buffer underrun + \arg CEC_INT_FLAG_TERR: Tx-error + \arg CEC_INT_FLAG_TAERR: Tx ACK error flag + \param[out] none + \retval none +*/ +void cec_interrupt_flag_clear(uint32_t flag) +{ + CEC_INTF = flag; +} + +#endif diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_cmp.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_cmp.c new file mode 100644 index 000000000..767221fae --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_cmp.c @@ -0,0 +1,269 @@ +/*! + \file gd32f3x0_cmp.c + \brief CMP driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2021-05-19, V2.1.1, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_cmp.h" + +/*! + \brief deinitialize comparator + \param[in] none + \param[out] none + \retval none +*/ +void cmp_deinit(void) +{ + CMP_CS = ((uint32_t)0x00000000U); +} + +/*! + \brief initialize comparator mode + \param[in] cmp_periph + \arg CMP0: comparator 0 + \arg CMP1: comparator 1 + \param[in] operating_mode + \arg CMP_HIGHSPEED: high speed mode + \arg CMP_MIDDLESPEED: medium speed mode + \arg CMP_LOWSPEED: low speed mode + \arg CMP_VERYLOWSPEED: very-low speed mode + \param[in] inverting_input + \arg CMP_1_4VREFINT: VREFINT *1/4 input + \arg CMP_1_2VREFINT: VREFINT *1/2 input + \arg CMP_3_4VREFINT: VREFINT *3/4 input + \arg CMP_VREFINT: VREFINT input + \arg CMP_DAC: PA4 (DAC) input + \arg CMP_PA5: PA5 input + \arg CMP_PA_0_2: PA0 or PA2 input + \param[in] hysteresis + \arg CMP_HYSTERESIS_NO: output no hysteresis + \arg CMP_HYSTERESIS_LOW: output low hysteresis + \arg CMP_HYSTERESIS_MIDDLE: output middle hysteresis + \arg CMP_HYSTERESIS_HIGH: output high hysteresis + \param[out] none + \retval none +*/ +void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, + cmp_hysteresis_enum output_hysteresis) +{ + uint32_t CMPx_CS = 0; + if(CMP0 == cmp_periph) { + /* initialize comparator 0 mode */ + CMPx_CS = CMP_CS; + CMPx_CS &= ~(uint32_t)(CMP_CS_CMP0M | CMP_CS_CMP0MSEL | CMP_CS_CMP0HST); + CMPx_CS |= CS_CMP0M(operating_mode) | CS_CMP0MSEL(inverting_input) | CS_CMP0HST(output_hysteresis); + CMP_CS = CMPx_CS; + } else { + /* initialize comparator 1 mode */ + CMPx_CS = CMP_CS; + CMPx_CS &= ~(uint32_t)(CMP_CS_CMP1M | CMP_CS_CMP1MSEL | CMP_CS_CMP1HST); + CMPx_CS |= CS_CMP1M(operating_mode) | CS_CMP1MSEL(inverting_input) | CS_CMP1HST(output_hysteresis); + CMP_CS = CMPx_CS; + } +} + +/*! + \brief initialize comparator output + \param[in] cmp_periph + \arg CMP0: comparator 0 + \arg CMP1: comparator 1 + \param[in] output_slection + \arg CMP_OUTPUT_NONE: output no selection + \arg CMP_OUTPUT_TIMER0BKIN: TIMER 0 break input + \arg CMP_OUTPUT_TIMER0IC0: TIMER 0 channel0 input capture + \arg CMP_OUTPUT_TIMER0OCPRECLR: TIMER 0 OCPRE_CLR input + \arg CMP_OUTPUT_TIMER1IC3: TIMER 1 channel3 input capture + \arg CMP_OUTPUT_TIMER1OCPRECLR: TIMER 1 OCPRE_CLR input + \arg CMP_OUTPUT_TIMER2IC0: TIMER 2 channel0 input capture + \arg CMP_OUTPUT_TIMER2OCPRECLR: TIMER 2 OCPRE_CLR input + \param[in] output_polarity + \arg CMP_OUTPUT_POLARITY_INVERTED: output is inverted + \arg CMP_OUTPUT_POLARITY_NOINVERTED: output is not inverted + \param[out] none + \retval none +*/ +void cmp_output_init(uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity) +{ + uint32_t CMPx_CS = 0; + /* initialize comparator 0 output */ + if(CMP0 == cmp_periph) { + CMPx_CS = CMP_CS; + CMPx_CS &= ~(uint32_t)CMP_CS_CMP0OSEL; + CMPx_CS |= CS_CMP0OSEL(output_slection); + /* output polarity */ + if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity) { + CMPx_CS |= CMP_CS_CMP0PL; + } else { + CMPx_CS &= ~CMP_CS_CMP0PL; + } + CMP_CS = CMPx_CS; + } else if(CMP1 == cmp_periph) { + /* initialize comparator 1 output */ + CMPx_CS = CMP_CS; + CMPx_CS &= ~(uint32_t)CMP_CS_CMP1OSEL; + CMPx_CS |= CS_CMP1OSEL(output_slection); + /* output polarity */ + if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity) { + CMPx_CS |= CMP_CS_CMP1PL; + } else { + CMPx_CS &= ~CMP_CS_CMP1PL; + } + CMP_CS = CMPx_CS; + } +} + +/*! + \brief enable comparator + \param[in] cmp_periph + \arg CMP0: comparator 0 + \arg CMP1: comparator 1 + \param[out] none + \retval none +*/ +void cmp_enable(uint32_t cmp_periph) +{ + if(CMP0 == cmp_periph) { + CMP_CS |= CMP_CS_CMP0EN; + } else { + CMP_CS |= CMP_CS_CMP1EN; + } +} + +/*! + \brief disable comparator + \param[in] cmp_periph + \arg CMP0: comparator 0 + \arg CMP1: comparator 1 + \param[out] none + \retval none +*/ +void cmp_disable(uint32_t cmp_periph) +{ + if(CMP0 == cmp_periph) { + CMP_CS &= ~CMP_CS_CMP0EN; + } else { + CMP_CS &= ~CMP_CS_CMP1EN; + } +} + +/*! + \brief enable comparator switch + \param[in] none + \param[out] none + \retval none +*/ +void cmp_switch_enable(void) +{ + CMP_CS |= CMP_CS_CMP0SW; +} + +/*! + \brief disable comparator switch + \param[in] none + \param[out] none + \retval none +*/ +void cmp_switch_disable(void) +{ + CMP_CS &= ~CMP_CS_CMP0SW; +} + +/*! + \brief enable the window mode + \param[in] none + \param[out] none + \retval none +*/ +void cmp_window_enable(void) +{ + CMP_CS |= CMP_CS_WNDEN; +} + +/*! + \brief disable the window mode + \param[in] none + \param[out] none + \retval none +*/ +void cmp_window_disable(void) +{ + CMP_CS &= ~CMP_CS_WNDEN; +} + +/*! + \brief lock the comparator + \param[in] cmp_periph + \arg CMP0: comparator 0 + \arg CMP1: comparator 1 + \param[out] none + \retval none +*/ +void cmp_lock_enable(uint32_t cmp_periph) +{ + if(CMP0 == cmp_periph) { + /* lock CMP0 */ + CMP_CS |= CMP_CS_CMP0LK; + } else { + /* lock CMP1 */ + CMP_CS |= CMP_CS_CMP1LK; + } +} + +/*! + \brief get output level + \param[in] cmp_periph + \arg CMP0: comparator 0 + \arg CMP1: comparator 1 + \param[out] none + \retval the output level +*/ +uint32_t cmp_output_level_get(uint32_t cmp_periph) +{ + if(CMP0 == cmp_periph) { + /* get output level of CMP0 */ + if(CMP_CS & CMP_CS_CMP0O) { + return CMP_OUTPUTLEVEL_HIGH; + } else { + return CMP_OUTPUTLEVEL_LOW; + } + } else { + /* get output level of CMP1 */ + if(CMP_CS & CMP_CS_CMP1O) { + return CMP_OUTPUTLEVEL_HIGH; + } else { + return CMP_OUTPUTLEVEL_LOW; + } + } +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_crc.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_crc.c new file mode 100644 index 000000000..87a5e5ff3 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_crc.c @@ -0,0 +1,244 @@ +/*! + \file gd32f3x0_crc.c + \brief CRC driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_crc.h" + +/*! + \brief deinit CRC calculation unit + \param[in] none + \param[out] none + \retval none +*/ +void crc_deinit(void) +{ + CRC_IDATA = (uint32_t)0xFFFFFFFFU; + CRC_DATA = (uint32_t)0xFFFFFFFFU; + CRC_FDATA = (uint32_t)0x00000000U; + CRC_POLY = (uint32_t)0x04C11DB7U; + CRC_CTL = CRC_CTL_RST; +} + +/*! + \brief enable the reverse operation of output data + \param[in] none + \param[out] none + \retval none +*/ +void crc_reverse_output_data_enable(void) +{ + CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O); + CRC_CTL |= (uint32_t)CRC_CTL_REV_O; +} + +/*! + \brief disable the reverse operation of output data + \param[in] none + \param[out] none + \retval none +*/ +void crc_reverse_output_data_disable(void) +{ + CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O); +} + +/*! + \brief reset data register to the value of initializaiton data register + \param[in] none + \param[out] none + \retval none +*/ +void crc_data_register_reset(void) +{ + CRC_CTL |= (uint32_t)CRC_CTL_RST; +} + +/*! + \brief read the data register + \param[in] none + \param[out] none + \retval 32-bit value of the data register +*/ +uint32_t crc_data_register_read(void) +{ + uint32_t data; + data = CRC_DATA; + return (data); +} + +/*! + \brief read the free data register + \param[in] none + \param[out] none + \retval 8-bit value of the free data register +*/ +uint8_t crc_free_data_register_read(void) +{ + uint8_t fdata; + fdata = (uint8_t)CRC_FDATA; + return (fdata); +} + +/*! + \brief write the free data register + \param[in] free_data: specify 8-bit data + \param[out] none + \retval none +*/ +void crc_free_data_register_write(uint8_t free_data) +{ + CRC_FDATA = (uint32_t)free_data; +} + +/*! + \brief write the initializaiton data register + \param[in] init_data:specify 32-bit data + \param[out] none + \retval none +*/ +void crc_init_data_register_write(uint32_t init_data) +{ + CRC_IDATA = (uint32_t)init_data; +} + +/*! + \brief configure the CRC input data function + \param[in] data_reverse: specify input data reverse function + only one parameter can be selected which is shown as below: + \arg CRC_INPUT_DATA_NOT: input data is not reversed + \arg CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits + \arg CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits + \arg CRC_INPUT_DATA_WORD: input data is reversed on 32 bits + \param[out] none + \retval none +*/ +void crc_input_data_reverse_config(uint32_t data_reverse) +{ + CRC_CTL &= (uint32_t)(~CRC_CTL_REV_I); + CRC_CTL |= (uint32_t)data_reverse; +} + +/*! + \brief configure the CRC size of polynomial function + \param[in] poly_size: size of polynomial + only one parameter can be selected which is shown as below: + \arg CRC_CTL_PS_32: 32-bit polynomial for CRC calculation + \arg CRC_CTL_PS_16: 16-bit polynomial for CRC calculation + \arg CRC_CTL_PS_8: 8-bit polynomial for CRC calculation + \arg CRC_CTL_PS_7: 7-bit polynomial for CRC calculation + \param[out] none + \retval none +*/ +void crc_polynomial_size_set(uint32_t poly_size) +{ + CRC_CTL &= (uint32_t)(~(CRC_CTL_PS)); + CRC_CTL |= (uint32_t)poly_size; +} + +/*! + \brief configure the CRC polynomial value function + \param[in] poly: configurable polynomial value + \param[out] none + \retval none +*/ +void crc_polynomial_set(uint32_t poly) +{ + CRC_POLY &= (uint32_t)(~CRC_POLY_POLY); + CRC_POLY = poly; +} + +/*! + \brief CRC calculate single data + \param[in] sdata: specify input data data + \param[in] data_format: input data format + only one parameter can be selected which is shown as below: + \arg INPUT_FORMAT_WORD: input data in word format + \arg INPUT_FORMAT_HALFWORD: input data in half-word format + \arg INPUT_FORMAT_BYTE: input data in byte format + \param[out] none + \retval CRC calculate value +*/ +uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format) +{ + if(INPUT_FORMAT_WORD == data_format) { + REG32(CRC) = sdata; + } else if(INPUT_FORMAT_HALFWORD == data_format) { + REG16(CRC) = (uint16_t)sdata; + } else { + REG8(CRC) = (uint8_t)sdata; + } + + return(CRC_DATA); +} + +/*! + \brief CRC calculate a data array + \param[in] array: pointer to the input data array + \param[in] size: size of the array + \param[in] data_format: input data format + only one parameter can be selected which is shown as below: + \arg INPUT_FORMAT_WORD: input data in word format + \arg INPUT_FORMAT_HALFWORD: input data in half-word format + \arg INPUT_FORMAT_BYTE: input data in byte format + \param[out] none + \retval CRC calculate value +*/ +uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format) +{ + uint8_t *data8; + uint16_t *data16; + uint32_t *data32; + uint32_t index; + + if(INPUT_FORMAT_WORD == data_format) { + data32 = (uint32_t *)array; + for(index = 0U; index < size; index++) { + REG32(CRC) = data32[index]; + } + } else if(INPUT_FORMAT_HALFWORD == data_format) { + data16 = (uint16_t *)array; + for(index = 0U; index < size; index++) { + REG16(CRC) = data16[index]; + } + } else { + data8 = (uint8_t *)array; + for(index = 0U; index < size; index++) { + REG8(CRC) = data8[index]; + } + } + + return (CRC_DATA); +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_ctc.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_ctc.c new file mode 100644 index 000000000..21598498d --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_ctc.c @@ -0,0 +1,384 @@ +/*! + \file gd32f3x0_ctc.c + \brief CTC driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_ctc.h" + +#define CTC_FLAG_MASK ((uint32_t)0x00000700U) + +/*! + \brief reset CTC clock trim controller + \param[in] none + \param[out] none + \retval none +*/ +void ctc_deinit(void) +{ + /* reset CTC */ + rcu_periph_reset_enable(RCU_CTCRST); + rcu_periph_reset_disable(RCU_CTCRST); +} + +/*! + \brief configure reference signal source polarity + \param[in] polarity: + only one parameter can be selected which is shown as below: + \arg CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge + \arg CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge + \param[out] none + \retval none +*/ +void ctc_refsource_polarity_config(uint32_t polarity) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); + CTC_CTL1 |= (uint32_t)polarity; +} + +/*! + \brief select reference signal source + \param[in] refs: + only one parameter can be selected which is shown as below: + \arg CTC_REFSOURCE_GPIO: GPIO is selected + \arg CTC_REFSOURCE_LXTAL: LXTAL is clock selected + \arg CTC_REFSOURCE_USBSOF: USBSOF is selected + \param[out] none + \retval none +*/ +void ctc_refsource_signal_select(uint32_t refs) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); + CTC_CTL1 |= (uint32_t)refs; +} + +/*! + \brief configure reference signal source prescaler + \param[in] prescaler: + only one parameter can be selected which is shown as below: + \arg CTC_REFSOURCE_PSC_OFF: reference signal not divided + \arg CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2 + \arg CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4 + \arg CTC_REFSOURCE_PSC_DIV8: reference signal divided by 8 + \arg CTC_REFSOURCE_PSC_DIV16: reference signal divided by 16 + \arg CTC_REFSOURCE_PSC_DIV32: reference signal divided by 32 + \arg CTC_REFSOURCE_PSC_DIV64: reference signal divided by 64 + \arg CTC_REFSOURCE_PSC_DIV128: reference signal divided by 128 + \param[out] none + \retval none +*/ +void ctc_refsource_prescaler_config(uint32_t prescaler) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); + CTC_CTL1 |= (uint32_t)prescaler; +} + +/*! + \brief configure clock trim base limit value + \param[in] limit_value: 8-bit clock trim base limit value + \arg 0x00-0xFF + \param[out] none + \retval none +*/ +void ctc_clock_limit_value_config(uint8_t limit_value) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); + CTC_CTL1 |= CTL1_CKLIM(limit_value); +} + +/*! + \brief configure CTC counter reload value + \param[in] reload_value: 16-bit CTC counter reload value + \arg 0x0000-0xFFFF + \param[out] none + \retval none +*/ +void ctc_counter_reload_value_config(uint16_t reload_value) +{ + CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE); + CTC_CTL1 |= (uint32_t)reload_value; +} + +/*! + \brief enable CTC trim counter + \param[in] none + \param[out] none + \retval none +*/ +void ctc_counter_enable(void) +{ + CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; +} + +/*! + \brief disable CTC trim counter + \param[in] none + \param[out] none + \retval none +*/ +void ctc_counter_disable(void) +{ + CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); +} + +/*! + \brief configure the IRC48M trim value + \param[in] trim_value: 8-bit IRC48M trim value + \arg 0x00-0x3F + \param[out] none + \retval none +*/ +void ctc_irc48m_trim_value_config(uint8_t trim_value) +{ + /* clear TRIMVALUE bits */ + CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); + /* set TRIMVALUE bits */ + CTC_CTL0 |= CTL0_TRIMVALUE(trim_value); +} + +/*! + \brief generate software reference source sync pulse + \param[in] none + \param[out] none + \retval none +*/ +void ctc_software_refsource_pulse_generate(void) +{ + CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; +} + +/*! + \brief configure hardware automatically trim mode + \param[in] hardmode: + only one parameter can be selected which is shown as below: + \arg CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable + \arg CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable + \param[out] none + \retval none +*/ +void ctc_hardware_trim_mode_config(uint32_t hardmode) +{ + CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); + CTC_CTL0 |= (uint32_t)hardmode; +} + +/*! + \brief read CTC counter capture value when reference sync pulse occurred + \param[in] none + \param[out] none + \retval the 16-bit CTC counter capture value +*/ +uint16_t ctc_counter_capture_value_read(void) +{ + uint16_t capture_value = 0U; + capture_value = (uint16_t)GET_STAT_REFCAP(CTC_STAT); + return (capture_value); +} + +/*! + \brief read CTC trim counter direction when reference sync pulse occurred + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET + \arg SET: CTC trim counter direction is down-counting + \arg RESET: CTC trim counter direction is up-counting +*/ +FlagStatus ctc_counter_direction_read(void) +{ + FlagStatus ret_status = RESET; + if(RESET != (CTC_STAT & CTC_STAT_REFDIR)) { + ret_status = SET; + } + return ret_status; +} + +/*! + \brief read CTC counter reload value + \param[in] none + \param[out] none + \retval the 16-bit CTC counter reload value +*/ +uint16_t ctc_counter_reload_value_read(void) +{ + uint16_t reload_value = 0U; + reload_value = (uint16_t)(CTC_CTL1 & CTC_CTL1_RLVALUE); + return (reload_value); +} + +/*! + \brief read the IRC48M trim value + \param[in] none + \param[out] none + \retval the 8-bit IRC48M trim value +*/ +uint8_t ctc_irc48m_trim_value_read(void) +{ + uint8_t trim_value = 0U; + trim_value = (uint8_t)GET_CTL0_TRIMVALUE(CTC_CTL0); + return (trim_value); +} + +/*! + \brief enable the CTC interrupt + \param[in] interrupt: CTC interrupt enable + one or more parameters can be selected which are shown as below: + \arg CTC_INT_CKOK: clock trim OK interrupt enable + \arg CTC_INT_CKWARN: clock trim warning interrupt enable + \arg CTC_INT_ERR: error interrupt enable + \arg CTC_INT_EREF: expect reference interrupt enable + \param[out] none + \retval none +*/ +void ctc_interrupt_enable(uint32_t interrupt) +{ + CTC_CTL0 |= (uint32_t)interrupt; +} + +/*! + \brief disable the CTC interrupt + \param[in] interrupt: CTC interrupt enable source + one or more parameters can be selected which are shown as below: + \arg CTC_INT_CKOK: clock trim OK interrupt enable + \arg CTC_INT_CKWARN: clock trim warning interrupt enable + \arg CTC_INT_ERR: error interrupt enable + \arg CTC_INT_EREF: expect reference interrupt enable + \param[out] none + \retval none +*/ +void ctc_interrupt_disable(uint32_t interrupt) +{ + CTC_CTL0 &= (uint32_t)(~(interrupt)); +} + +/*! + \brief get CTC flag + \param[in] flag: the CTC flag + only one parameter can be selected which is shown as below: + \arg CTC_FLAG_CKOK: clock trim OK flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_EREF: expect reference flag + \arg CTC_FLAG_CKERR: clock trim error bit + \arg CTC_FLAG_REFMISS: reference sync pulse miss + \arg CTC_FLAG_TRIMERR: trim value error bit + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ctc_flag_get(uint32_t flag) +{ + FlagStatus ret_status = RESET; + + if(RESET != (CTC_STAT & flag)) { + ret_status = SET; + } + return ret_status; +} + +/*! + \brief clear CTC flag + \param[in] flag: the CTC flag + only one parameter can be selected which is shown as below: + \arg CTC_FLAG_CKOK: clock trim OK flag + \arg CTC_FLAG_CKWARN: clock trim warning flag + \arg CTC_FLAG_ERR: error flag + \arg CTC_FLAG_EREF: expect reference flag + \arg CTC_FLAG_CKERR: clock trim error bit + \arg CTC_FLAG_REFMISS: reference sync pulse miss + \arg CTC_FLAG_TRIMERR: trim value error bit + \param[out] none + \retval none +*/ +void ctc_flag_clear(uint32_t flag) +{ + if(flag & CTC_FLAG_MASK) { + CTC_INTC |= CTC_INTC_ERRIC; + } else { + CTC_INTC |= flag; + } +} + +/*! + \brief get CTC interrupt flag + \param[in] interrupt: the CTC interrupt flag + only one parameter can be selected which is shown as below: + \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_EREF: expect reference interrupt + \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus ctc_interrupt_flag_get(uint32_t interrupt) +{ + uint32_t ctc_int = 0U, intenable = 0U; + FlagStatus ret_status = RESET; + + if(interrupt & CTC_FLAG_MASK) { + intenable = CTC_CTL0 & CTC_INT_ERR; + } else { + intenable = CTC_CTL0 & interrupt; + } + ctc_int = CTC_STAT & interrupt; + + if(ctc_int && intenable) { + ret_status = SET; + } + return ret_status; +} + +/*! + \brief clear CTC interrupt flag + \param[in] interrupt: the CTC interrupt flag + only one parameter can be selected which is shown as below: + \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt + \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt + \arg CTC_INT_FLAG_ERR: error interrupt + \arg CTC_INT_FLAG_EREF: expect reference interrupt + \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt + \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt + \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt + \param[out] none + \retval none +*/ +void ctc_interrupt_flag_clear(uint32_t interrupt) +{ + if(interrupt & CTC_FLAG_MASK) { + CTC_INTC |= CTC_INTC_ERRIC; + } else { + CTC_INTC |= interrupt; + } +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_dac.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_dac.c new file mode 100644 index 000000000..8b16fcf7b --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_dac.c @@ -0,0 +1,389 @@ +/*! + \file gd32f3x0_dac.c + \brief DAC driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifdef GD32F350 +#include "gd32f3x0_dac.h" + +/*! + \brief deinitialize DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_deinit(void) +{ + rcu_periph_reset_enable(RCU_DACRST); + rcu_periph_reset_disable(RCU_DACRST); +} + +/*! + \brief enable DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_enable(void) +{ + DAC_CTL |= DAC_CTL_DEN; +} + +/*! + \brief disable DAC + \param[in] none + \param[out] none + \retval none +*/ +void dac_disable(void) +{ + DAC_CTL &= ~DAC_CTL_DEN; +} + +/*! + \brief enable DAC DMA + \param[in] none + \param[out] none + \retval none +*/ +void dac_dma_enable(void) +{ + DAC_CTL |= DAC_CTL_DDMAEN; +} + +/*! + \brief disable DAC DMA + \param[in] none + \param[out] none + \retval none +*/ +void dac_dma_disable(void) +{ + DAC_CTL &= ~DAC_CTL_DDMAEN; +} + +/*! + \brief enable DAC output buffer + \param[in] none + \param[out] none + \retval none +*/ +void dac_output_buffer_enable(void) +{ + DAC_CTL &= ~DAC_CTL_DBOFF; +} + +/*! + \brief disable DAC output buffer + \param[in] none + \param[out] none + \retval none +*/ +void dac_output_buffer_disable(void) +{ + DAC_CTL |= DAC_CTL_DBOFF; +} + +/*! + \brief enable DAC trigger + \param[in] none + \param[out] none + \retval none +*/ +void dac_trigger_enable(void) +{ + DAC_CTL |= DAC_CTL_DTEN; +} + +/*! + \brief disable DAC trigger + \param[in] none + \param[out] none + \retval none +*/ +void dac_trigger_disable(void) +{ + DAC_CTL &= ~DAC_CTL_DTEN; +} + +/*! + \brief enable DAC software trigger + \param[in] none + \param[out] none + \retval none +*/ +void dac_software_trigger_enable(void) +{ + DAC_SWT |= DAC_SWT_SWTR; +} + +/*! + \brief disable DAC software trigger + \param[in] none + \param[out] none + \retval none +*/ +void dac_software_trigger_disable(void) +{ + DAC_SWT &= ~DAC_SWT_SWTR; +} + +/*! + \brief configure DAC trigger source + \param[in] triggersource: external triggers of DAC + \arg DAC_TRIGGER_T1_TRGO: trigger source is TIMER1 TRGO + \arg DAC_TRIGGER_T2_TRGO: trigger source is TIMER2 TRGO + \arg DAC_TRIGGER_T5_TRGO: trigger source is TIMER5 TRGO + \arg DAC_TRIGGER_T14_TRGO: trigger source is TIMER14 TRGO + \arg DAC_TRIGGER_EXTI_9: trigger source is EXTI interrupt line9 event + \arg DAC_TRIGGER_SOFTWARE: software trigger + \param[out] none + \retval none +*/ +void dac_trigger_source_config(uint32_t triggersource) +{ + DAC_CTL &= ~DAC_CTL_DTSEL; + DAC_CTL |= triggersource; +} + +/*! + \brief configure DAC wave mode + \param[in] wave_mode + \arg DAC_WAVE_DISABLE: wave disable + \arg DAC_WAVE_MODE_LFSR: LFSR noise mode + \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode + \param[out] none + \retval none +*/ +void dac_wave_mode_config(uint32_t wave_mode) +{ + DAC_CTL &= ~DAC_CTL_DWM; + DAC_CTL |= wave_mode; +} + +/*! + \brief configure DAC wave bit width + \param[in] bit_width + \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 + \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 + \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 + \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 + \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 + \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 + \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 + \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 + \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 + \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 + \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 + \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 + \param[out] none + \retval none +*/ +void dac_wave_bit_width_config(uint32_t bit_width) +{ + DAC_CTL &= ~DAC_CTL_DWBW; + DAC_CTL |= bit_width; +} + +/*! + \brief configure DAC LFSR noise mode + \param[in] unmask_bits + \arg DAC_LFSR_BIT0: unmask the LFSR bit0 + \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] + \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] + \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] + \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] + \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] + \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] + \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] + \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] + \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] + \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] + \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] + \param[out] none + \retval none +*/ +void dac_lfsr_noise_config(uint32_t unmask_bits) +{ + DAC_CTL &= ~DAC_CTL_DWBW; + DAC_CTL |= unmask_bits; +} + +/*! + \brief configure DAC triangle noise mode + \param[in] amplitude + \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 + \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 + \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 + \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 + \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 + \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 + \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 + \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 + \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 + \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 + \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 + \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 + \param[out] none + \retval none +*/ +void dac_triangle_noise_config(uint32_t amplitude) +{ + DAC_CTL &= ~DAC_CTL_DWBW; + DAC_CTL |= amplitude; +} + +/*! + \brief get DAC output value + \param[in] none + \param[out] none + \retval DAC output data +*/ +uint16_t dac_output_value_get(void) +{ + uint16_t data = 0U; + data = (uint16_t)DAC_DO; + return data; +} + +/*! + \brief set DAC data holding register value + \param[in] dac_align + \arg DAC_ALIGN_8B_R: data right 8b alignment + \arg DAC_ALIGN_12B_R: data right 12b alignment + \arg DAC_ALIGN_12B_L: data left 12b alignment + \param[in] data: data to be loaded + \param[out] none + \retval none +*/ +void dac_data_set(uint32_t dac_align, uint16_t data) +{ + switch(dac_align) { + /* data right 12b alignment */ + case DAC_ALIGN_12B_R: + DAC_R12DH = data; + break; + /* data left 12b alignment */ + case DAC_ALIGN_12B_L: + DAC_L12DH = data; + break; + /* data right 8b alignment */ + case DAC_ALIGN_8B_R: + DAC_R8DH = data; + break; + default: + break; + } +} + +/*! + \brief get the specified DAC flag(DAC DMA underrun flag) + \param[in] none + \param[out] none + \retval the state of dac bit(SET or RESET) +*/ +FlagStatus dac_flag_get(void) +{ + /* check the DMA underrun flag */ + if((uint8_t)RESET != (DAC_STAT & DAC_STAT_DDUDR)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the specified DAC flag(DAC DMA underrun flag) + \param[in] none + \param[out] none + \retval none +*/ +void dac_flag_clear(void) +{ + DAC_STAT |= DAC_STAT_DDUDR; +} + +/*! + \brief enable DAC interrupt(DAC DMA underrun interrupt) + \param[in] none + \param[out] none + \retval none +*/ +void dac_interrupt_enable(void) +{ + DAC_CTL |= DAC_CTL_DDUDRIE; +} + +/*! + \brief disable DAC interrupt(DAC DMA underrun interrupt) + \param[in] none + \param[out] none + \retval none +*/ +void dac_interrupt_disable(void) +{ + DAC_CTL &= ~DAC_CTL_DDUDRIE; +} +/*! + \brief get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) + \param[in] none + \param[out] none + \retval the state of DAC interrupt flag(SET or RESET) +*/ +FlagStatus dac_interrupt_flag_get(void) +{ + FlagStatus temp_flag = RESET; + uint32_t ddudr_flag = 0U, ddudrie_flag = 0U; + /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */ + ddudr_flag = DAC_STAT & DAC_STAT_DDUDR; + ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE; + if((RESET != ddudr_flag) && (RESET != ddudrie_flag)) { + temp_flag = SET; + } + return temp_flag; +} + +/*! + \brief clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) + \param[in] none + \param[out] none + \retval none +*/ +void dac_interrupt_flag_clear(void) +{ + DAC_STAT |= DAC_STAT_DDUDR; +} + +#endif /* GD32F350 */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_dbg.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_dbg.c new file mode 100644 index 000000000..adbe38f80 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_dbg.c @@ -0,0 +1,135 @@ +/*! + \file gd32f3x0_dbg.c + \brief DBG driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_dbg.h" + +#define DBG_RESET_VAL ((uint32_t)0x00000000U) /*!< DBG reset value */ + +/*! + \brief deinitialize the DBG + \param[in] none + \param[out] none + \retval none +*/ +void dbg_deinit(void) +{ + DBG_CTL0 = DBG_RESET_VAL; + DBG_CTL1 = DBG_RESET_VAL; +} + +/*! + \brief read DBG_ID code register + \param[in] none + \param[out] none + \retval DBG_ID code +*/ +uint32_t dbg_id_get(void) +{ + return DBG_ID; +} + +/*! + \brief enable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + one or more parameters can be selected which are shown as below: + \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_enable(uint32_t dbg_low_power) +{ + DBG_CTL0 |= dbg_low_power; +} + +/*! + \brief disable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + one or more parameters can be selected which are shown as below: + \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_disable(uint32_t dbg_low_power) +{ + DBG_CTL0 &= ~dbg_low_power; +} + +/*! + \brief enable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: refer to dbg_periph_enum + only one parameter can be selected which are shown as below: + \arg DBG_SLEEP_HOLD: keep debugger connection during sleep mode + \arg DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode + \arg DBG_STANDBY_HOLD: keep debugger connection during standby mode + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16,TIMER5 is only available in GD32F350, + TIMER1 is only available in GD32F350 and GD32F330): hold TIMERx counter when core is halted + \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted + \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_enable(dbg_periph_enum dbg_periph) +{ + DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph)); +} + +/*! + \brief disable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: refer to dbg_periph_enum + only one parameter can be selected which are shown as below: + \arg DBG_SLEEP_HOLD: keep debugger connection during sleep mode + \arg DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode + \arg DBG_STANDBY_HOLD: keep debugger connection during standby mode + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16,TIMER5 is only available in GD32F350, + TIMER1 is only available in GD32F350 and GD32F330): hold TIMERx counter when core is halted + \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted + \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_disable(dbg_periph_enum dbg_periph) +{ + DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph)); +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_dma.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_dma.c new file mode 100644 index 000000000..22a806dea --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_dma.c @@ -0,0 +1,563 @@ +/*! + \file gd32f3x0_dma.c + \brief DMA driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_dma.h" + +/*! + \brief deinitialize DMA a channel registers + \param[in] channelx: specify which DMA channel is deinitialized + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_deinit(dma_channel_enum channelx) +{ + /* disable DMA a channel */ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN; + /* reset DMA channel registers */ + DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE; + DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE; + DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE; + DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE; + DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); +} + +/*! + \brief initialize the parameters of DMA struct with the default values + \param[in] init_struct: the initialization data needed to initialize DMA channel + \param[out] none + \retval none +*/ +void dma_struct_para_init(dma_parameter_struct *init_struct) +{ + /* set the DMA struct with the default values */ + init_struct->periph_addr = 0U; + init_struct->periph_width = 0U; + init_struct->periph_inc = (uint8_t)DMA_PERIPH_INCREASE_DISABLE; + init_struct->memory_addr = 0U; + init_struct->memory_width = 0U; + init_struct->memory_inc = (uint8_t)DMA_MEMORY_INCREASE_DISABLE; + init_struct->number = 0U; + init_struct->direction = (uint8_t)DMA_PERIPHERAL_TO_MEMORY; + init_struct->priority = (uint32_t)DMA_PRIORITY_LOW; +} + +/*! + \brief initialize DMA channel + \param[in] channelx: specify which DMA channel is initialized + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] init_struct: the data needed to initialize DMA channel + periph_addr: peripheral base address + periph_width: DMA_PERIPHERAL_WIDTH_8BIT,DMA_PERIPHERAL_WIDTH_16BIT,DMA_PERIPHERAL_WIDTH_32BIT + periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE + memory_addr: memory base address + memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT + memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE + direction: DMA_PERIPHERAL_TO_MEMORY,DMA_MEMORY_TO_PERIPHERAL + number: the number of remaining data to be transferred by the DMA + priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH + \param[out] none + \retval none +*/ +void dma_init(dma_channel_enum channelx, dma_parameter_struct *init_struct) +{ + uint32_t ctl; + + dma_channel_disable(channelx); + + /* configure peripheral base address */ + DMA_CHPADDR(channelx) = init_struct->periph_addr; + + /* configure memory base address */ + DMA_CHMADDR(channelx) = init_struct->memory_addr; + + /* configure the number of remaining data to be transferred */ + DMA_CHCNT(channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); + + /* configure peripheral transfer width,memory transfer width,channel priotity */ + ctl = DMA_CHCTL(channelx); + ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); + ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority); + DMA_CHCTL(channelx) = ctl; + + /* configure peripheral increasing mode */ + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) { + DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA; + } else { + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA; + } + + /* configure memory increasing mode */ + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) { + DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA; + } else { + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA; + } + + /* configure the direction of data transfer */ + if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction) { + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR; + } else { + DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR; + } +} + +/*! + \brief enable DMA circulation mode + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_circulation_enable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) |= DMA_CHXCTL_CMEN; +} + +/*! + \brief disable DMA circulation mode + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_circulation_disable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CMEN; +} + +/*! + \brief enable memory to memory mode + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_enable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) |= DMA_CHXCTL_M2M; +} + +/*! + \brief disable memory to memory mode + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_disable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_M2M; +} + +/*! + \brief enable DMA channel + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_channel_enable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) |= DMA_CHXCTL_CHEN; +} + +/*! + \brief disable DMA channel + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_channel_disable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN; +} + +/*! + \brief set DMA peripheral base address + \param[in] channelx: specify which DMA channel to set peripheral base address + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] address: peripheral base address + \param[out] none + \retval none +*/ +void dma_periph_address_config(dma_channel_enum channelx, uint32_t address) +{ + DMA_CHPADDR(channelx) = address; +} + +/*! + \brief set DMA memory base address + \param[in] channelx: specify which DMA channel to set memory base address + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] address: memory base address + \param[out] none + \retval none +*/ +void dma_memory_address_config(dma_channel_enum channelx, uint32_t address) +{ + DMA_CHMADDR(channelx) = address; +} + +/*! + \brief set the number of remaining data to be transferred by the DMA + \param[in] channelx: specify which DMA channel to set number + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] number: the number of remaining data to be transferred by the DMA + \param[out] none + \retval none +*/ +void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number) +{ + DMA_CHCNT(channelx) = (number & DMA_CHANNEL_CNT_MASK); +} + +/*! + \brief get the number of remaining data to be transferred by the DMA + \param[in] channelx: specify which DMA channel to set number + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval the number of remaining data to be transferred by the DMA +*/ +uint32_t dma_transfer_number_get(dma_channel_enum channelx) +{ + return (uint32_t)DMA_CHCNT(channelx); +} + +/*! + \brief configure priority level of DMA channel + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] priority: priority level of this channel + only one parameter can be selected which is shown as below: + \arg DMA_PRIORITY_LOW: low priority + \arg DMA_PRIORITY_MEDIUM: medium priority + \arg DMA_PRIORITY_HIGH: high priority + \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority + \param[out] none + \retval none +*/ +void dma_priority_config(dma_channel_enum channelx, uint32_t priority) +{ + uint32_t ctl; + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PRIO; + ctl |= priority; + DMA_CHCTL(channelx) = ctl; +} + +/*! + \brief configure transfer data width of memory + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] mwidth: transfer data width of memory + only one parameter can be selected which is shown as below: + \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit + \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit + \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit + \param[out] none + \retval none +*/ +void dma_memory_width_config(dma_channel_enum channelx, uint32_t mwidth) +{ + uint32_t ctl; + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_MWIDTH; + ctl |= mwidth; + DMA_CHCTL(channelx) = ctl; +} + +/*! + \brief configure transfer data width of peripheral + \param[in] channelx: specify which DMA channel + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] pwidth: transfer data width of peripheral + only one parameter can be selected which is shown as below: + \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit + \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit + \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit + \param[out] none + \retval none +*/ +void dma_periph_width_config(dma_channel_enum channelx, uint32_t pwidth) +{ + uint32_t ctl; + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PWIDTH; + ctl |= pwidth; + DMA_CHCTL(channelx) = ctl; +} + +/*! + \brief enable next address increasement algorithm of memory + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_memory_increase_enable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA; +} + +/*! + \brief disable next address increasement algorithm of memory + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_memory_increase_disable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA; +} + +/*! + \brief enable next address increasement algorithm of peripheral + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_periph_increase_enable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA; +} + +/*! + \brief disable next address increasement algorithm of peripheral + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[out] none + \retval none +*/ +void dma_periph_increase_disable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA; +} + +/*! + \brief configure the direction of data transfer on the channel + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] direction: specify the direction of data transfer + only one parameter can be selected which is shown as below: + \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory + \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral + \param[out] none + \retval none +*/ +void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction) +{ + if(DMA_PERIPHERAL_TO_MEMORY == direction) { + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR; + } else { + DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR; + } +} + +/*! + \brief check DMA flag is set or not + \param[in] channelx: specify which DMA channel to get flag + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag) +{ + FlagStatus reval; + + if(RESET != (DMA_INTF & DMA_FLAG_ADD(flag, channelx))) { + reval = SET; + } else { + reval = RESET; + } + + return reval; +} + +/*! + \brief clear DMA a channel flag + \param[in] channelx: specify which DMA channel to clear flag + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval none +*/ +void dma_flag_clear(dma_channel_enum channelx, uint32_t flag) +{ + DMA_INTC |= DMA_FLAG_ADD(flag, channelx); +} + +/*! + \brief enable DMA interrupt + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] source: specify which interrupt to enable + only one parameter can be selected which is shown as below: + \arg DMA_INT_ERR: channel error interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_FTF: channel full transfer finish interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source) +{ + DMA_CHCTL(channelx) |= source; +} + +/*! + \brief disable DMA interrupt + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] source: specify which interrupt to disable + only one parameter can be selected which is shown as below: + \arg DMA_INT_ERR: channel error interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_FTF: channel full transfer finish interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source) +{ + DMA_CHCTL(channelx) &= ~source; +} + +/*! + \brief check DMA flag and interrupt enable bit is set or not + \param[in] channelx: specify which DMA channel to get flag + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_FTF: transfer finish flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish flag of channel + \arg DMA_INT_FLAG_ERR: error flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag) +{ + uint32_t interrupt_enable = 0U, interrupt_flag = 0U; + + switch(flag) { + case DMA_INT_FLAG_FTF: + interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_FTFIE; + break; + case DMA_INT_FLAG_HTF: + interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INT_FLAG_ERR: + interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_ERRIE; + break; + default: + break; + } + + if(interrupt_flag && interrupt_enable) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear DMA a channel interrupt flag + \param[in] channelx: specify which DMA channel to clear flag + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..6) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_G: global interrupt flag of channel + \arg DMA_INT_FLAG_FTF: transfer finish flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish flag of channel + \arg DMA_INT_FLAG_ERR: error flag of channel + \param[out] none + \retval none +*/ +void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag) +{ + DMA_INTC |= DMA_FLAG_ADD(flag, channelx); +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_exti.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_exti.c new file mode 100644 index 000000000..15106f274 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_exti.c @@ -0,0 +1,257 @@ +/*! + \file gd32f3x0_exti.c + \brief EXTI driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_exti.h" + +/*! + \brief reset EXTI, reset the value of all EXTI registers into initial values + \param[in] none + \param[out] none + \retval none +*/ +void exti_deinit(void) +{ + /* reset the value of all the EXTI registers */ + EXTI_INTEN = (uint32_t)0x0F940000U; + EXTI_EVEN = (uint32_t)0x00000000U; + EXTI_RTEN = (uint32_t)0x00000000U; + EXTI_FTEN = (uint32_t)0x00000000U; + EXTI_SWIEV = (uint32_t)0x00000000U; +} + +/*! + \brief initialize the EXTI, enable the configuration of EXTI initialize + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19,21,22): EXTI line x + \param[in] mode: interrupt or event mode, refer to exti_mode_enum + only one parameter can be selected which is shown as below: + \arg EXTI_INTERRUPT: interrupt mode + \arg EXTI_EVENT: event mode + \param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum + only one parameter can be selected which is shown as below: + \arg EXTI_TRIG_RISING: rising edge trigger + \arg EXTI_TRIG_FALLING: falling trigger + \arg EXTI_TRIG_BOTH: rising and falling trigger + \arg EXTI_TRIG_NONE: without rising edge or falling edge trigger + \param[out] none + \retval none +*/ +void exti_init(exti_line_enum linex, \ + exti_mode_enum mode, \ + exti_trig_type_enum trig_type) +{ + /* reset the EXTI line x */ + EXTI_INTEN &= ~(uint32_t)linex; + EXTI_EVEN &= ~(uint32_t)linex; + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + + /* set the EXTI mode and enable the interrupts or events from EXTI line x */ + switch(mode) { + case EXTI_INTERRUPT: + EXTI_INTEN |= (uint32_t)linex; + break; + case EXTI_EVENT: + EXTI_EVEN |= (uint32_t)linex; + break; + default: + break; + } + + /* set the EXTI trigger type */ + switch(trig_type) { + case EXTI_TRIG_RISING: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + break; + case EXTI_TRIG_FALLING: + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + case EXTI_TRIG_BOTH: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + case EXTI_TRIG_NONE: + default: + break; + } +} + +/*! + \brief enable the interrupts from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..27): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_enable(exti_line_enum linex) +{ + EXTI_INTEN |= (uint32_t)linex; +} + +/*! + \brief disable the interrupt from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..27): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_disable(exti_line_enum linex) +{ + EXTI_INTEN &= ~(uint32_t)linex; +} + +/*! + \brief enable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..27): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_enable(exti_line_enum linex) +{ + EXTI_EVEN |= (uint32_t)linex; +} + +/*! + \brief disable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..27): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_disable(exti_line_enum linex) +{ + EXTI_EVEN &= ~(uint32_t)linex; +} + +/*! + \brief enable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19,21,22): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_enable(exti_line_enum linex) +{ + EXTI_SWIEV |= (uint32_t)linex; +} + +/*! + \brief disable EXTI software interrupt event + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19,21,22): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_disable(exti_line_enum linex) +{ + EXTI_SWIEV &= ~(uint32_t)linex; +} + +/*! + \brief get EXTI line x pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19,21,22): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_flag_get(exti_line_enum linex) +{ + if(RESET != (EXTI_PD & (uint32_t)linex)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear EXTI line x pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19,21,22): EXTI line x + \param[out] none + \retval none +*/ +void exti_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} + +/*! + \brief get EXTI line x flag when the interrupt flag is set + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19,21,22): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex) +{ + uint32_t flag_left, flag_right; + + flag_left = EXTI_PD & (uint32_t)linex; + flag_right = EXTI_INTEN & (uint32_t)linex; + + if((RESET != flag_left) && (RESET != flag_right)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear EXTI line x pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..19,21,22): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_fmc.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_fmc.c new file mode 100644 index 000000000..2981aa1af --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_fmc.c @@ -0,0 +1,889 @@ +/*! + \file gd32f3x0_fmc.c + \brief FMC driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_fmc.h" + +/* FMC main memory programming functions */ + +/*! + \brief unlock the main FMC operation + it is better to used in pairs with fmc_lock + \param[in] none + \param[out] none + \retval none +*/ +void fmc_unlock(void) +{ + if((RESET != (FMC_CTL & FMC_CTL_LK))) { + /* write the FMC key */ + FMC_KEY = UNLOCK_KEY0; + FMC_KEY = UNLOCK_KEY1; + } +} + +/*! + \brief lock the main FMC operation + it is better to used in pairs with fmc_unlock after an operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_lock(void) +{ + /* set the LK bit*/ + FMC_CTL |= FMC_CTL_LK; +} + +/*! + \brief set the wait state counter value + \param[in] wscnt: wait state counter value + only one parameter can be selected which is shown as below: + \arg WS_WSCNT_0: 0 wait state added + \arg WS_WSCNT_1: 1 wait state added + \arg WS_WSCNT_2: 2 wait state added + \param[out] none + \retval none +*/ +void fmc_wscnt_set(uint8_t wscnt) +{ + uint32_t reg; + + reg = FMC_WS; + /* set the wait state counter value */ + reg &= ~FMC_WS_WSCNT; + FMC_WS = (reg | wscnt); +} + +/*! + \brief fmc wait state enable + \param[in] none + \param[out] none + \retval none +*/ +void fmc_wait_state_enable(void) +{ + /* unlock the main flash */ + fmc_unlock(); + + /* set the WSEN bit in register FMC_WSEN */ + FMC_WSEN |= FMC_WSEN_WSEN; + + /* lock the main flash after operation */ + fmc_lock(); +} + +/*! + \brief fmc wait state disable + \param[in] none + \param[out] none + \retval none +*/ +void fmc_wait_state_disable(void) +{ + /* unlock the main flash */ + fmc_unlock(); + + /* reset the WSEN bit in register FMC_WSEN */ + FMC_WSEN &= ~FMC_WSEN_WSEN; + + /* lock the main flash after operation */ + fmc_lock(); +} + +/*! + \brief erase page + \param[in] page_address: target page start address + \param[out] none + \retval fmc_state +*/ +fmc_state_enum fmc_page_erase(uint32_t page_address) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start page erase */ + FMC_CTL |= FMC_CTL_PER; + FMC_ADDR = page_address; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PER bit */ + FMC_CTL &= ~FMC_CTL_PER; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief erase whole chip + \param[in] none + \param[out] none + \retval fmc_state +*/ +fmc_state_enum fmc_mass_erase(void) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start chip erase */ + FMC_CTL |= FMC_CTL_MER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the MER bit */ + FMC_CTL &= ~FMC_CTL_MER; + } + + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief program a word at the corresponding address + \param[in] address: address to program + \param[in] data: word to program + \param[out] none + \retval fmc_state +*/ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL |= FMC_CTL_PG; + + REG32(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PG bit */ + FMC_CTL &= ~FMC_CTL_PG; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program a half word at the corresponding address + \param[in] address: address to program + \param[in] data: word to program + \param[out] none + \retval fmc_state +*/ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL |= FMC_CTL_PG; + + REG16(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PG bit */ + FMC_CTL &= ~FMC_CTL_PG; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program a word at the corresponding address without erasing + \param[in] address: address to program + \param[in] data: word to program + \param[out] none + \retval fmc_state +*/ +fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + FMC_WSEN |= FMC_WSEN_BPEN; + + if(FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL |= FMC_CTL_PG; + + REG32(address) = data; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PG bit */ + FMC_CTL &= ~FMC_CTL_PG; + } + + /* return the FMC state */ + return fmc_state; +} + +/* FMC option bytes programming functions */ + +/*! + \brief unlock the option byte operation + it is better to used in pairs with ob_lock + \param[in] none + \param[out] none + \retval none +*/ +void ob_unlock(void) +{ + if(RESET == (FMC_CTL & FMC_CTL_OBWEN)) { + /* write the FMC key */ + FMC_OBKEY = UNLOCK_KEY0; + FMC_OBKEY = UNLOCK_KEY1; + } +} + +/*! + \brief lock the option byte operation + it is better to used in pairs with ob_unlock after an operation + \param[in] none + \param[out] none + \retval none +*/ +void ob_lock(void) +{ + /* reset the OBWE bit */ + FMC_CTL &= ~FMC_CTL_OBWEN; +} + +/*! + \brief reload the option byte and generate a system reset + \param[in] none + \param[out] none + \retval none +*/ +void ob_reset(void) +{ + /* set the OBRLD bit */ + FMC_CTL |= FMC_CTL_OBRLD; +} + +/*! + \brief erase the option byte + programmer must ensure FMC & option byte are both unlocked before calling this function + \param[in] none + \param[out] none + \retval fmc_state +*/ +fmc_state_enum ob_erase(void) +{ + uint16_t fmc_spc; + + uint32_t fmc_plevel = ob_obstat_plevel_get(); + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* get the original option byte security protection code */ + if(OB_OBSTAT_PLEVEL_NO == fmc_plevel) { + fmc_spc = FMC_NSPC; + } else if(OB_OBSTAT_PLEVEL_LOW == fmc_plevel) { + fmc_spc = FMC_LSPC; + } else { + fmc_spc = FMC_HSPC; + fmc_state = FMC_OB_HSPC; + } + + if(FMC_READY == fmc_state) { + /* start erase the option byte */ + FMC_CTL |= FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + + /* set the OBPG bit */ + FMC_CTL |= FMC_CTL_OBPG; + + /* restore the last get option byte security protection code */ + OB_SPC = fmc_spc; + OB_USER = OB_USER_DEFAULT; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } else { + if(FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief enable option byte write protection(OB_WP) depending on current option byte + \param[in] ob_wp: write protection configuration data + setting the bit of ob_wp means enabling the corresponding sector write protection + \param[out] none + \retval fmc_state +*/ +fmc_state_enum ob_write_protection_enable(uint16_t ob_wp) +{ + uint8_t ob_wrp0, ob_wrp1; + ob_parm_struct ob_parm; + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + ob_parm_get(&ob_parm); + ob_wp = (uint16_t)(~ob_wp); + ob_wrp0 = (uint8_t)(ob_wp & OB_LWP); + ob_wrp1 = (uint8_t)((ob_wp & OB_HWP) >> 8U); + + if(0xFFFFU == OB_WP0) { + if(0xFFFFU == OB_WP1) { + if(FMC_READY == fmc_state) { + /* set the OBPG bit*/ + FMC_CTL |= FMC_CTL_OBPG; + + if(0xFFU != ob_wrp0) { + OB_WP0 = ob_wrp0 ; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + } + + if((FMC_READY == fmc_state) && (0xFFU != ob_wrp1)) { + OB_WP1 = ob_wrp1 ; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + } + + if(FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } + } + } else { + if(FMC_READY == fmc_state) { + /* start erase the option byte */ + FMC_CTL |= FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + + /* enable the option bytes programming */ + FMC_CTL |= FMC_CTL_OBPG; + + ob_value_modify(OB_WP_ADDR0, ob_wp, &ob_parm); + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } else { + if(FMC_TOERR != fmc_state) { + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + } + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief configure security protection + \param[in] ob_spc: specify security protection code + only one parameter can be selected which is shown as below: + \arg FMC_NSPC: no security protection + \arg FMC_LSPC: low security protection + \arg FMC_HSPC: high security protection + \param[out] none + \retval fmc_state +*/ +fmc_state_enum ob_security_protection_config(uint8_t ob_spc) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + ob_parm_struct ob_parm; + ob_parm_get(&ob_parm); + + /* the OB_SPC byte cannot be reprogrammed if protection level is high */ + if(OB_OBSTAT_PLEVEL_HIGH == ob_obstat_plevel_get()) { + fmc_state = FMC_OB_HSPC; + } + + if(FMC_READY == fmc_state) { + /* start erase the option byte */ + FMC_CTL |= FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + + /* enable the option bytes programming */ + FMC_CTL |= FMC_CTL_OBPG; + + ob_value_modify(OB_SPC_ADDR, (uint16_t)ob_spc, &ob_parm); + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } else { + if(FMC_TOERR != fmc_state) { + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program the FMC user option byte depending on current option byte + \param[in] ob_user: user option byte + one or more parameters (bitwise AND) can be selected which are shown as below: + \arg OB_FWDGT_HW: hardware free watchdog timer + \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode + \arg OB_STDBY_RST: generate a reset instead of entering standby mode + \arg OB_BOOT1_SET_1: BOOT1 bit is 1 + \arg OB_VDDA_DISABLE: disable VDDA monitor + \arg OB_SRAM_PARITY_ENABLE: enable sram parity check + \param[out] none + \retval fmc_state +*/ +fmc_state_enum ob_user_write(uint8_t ob_user) +{ + /* check whether FMC is ready or not */ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + ob_parm_struct ob_parm; + ob_parm_get(&ob_parm); + + if(FMC_READY == fmc_state) { + /* start erase the option byte */ + FMC_CTL |= FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + + /* set the OBPG bit */ + FMC_CTL |= FMC_CTL_OBPG; + + /* restore the last get option byte security protection code */ + ob_value_modify(OB_USER_ADDR, (uint16_t)ob_user, &ob_parm); + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } else { + if(FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program the FMC data option byte + \param[in] address: OB_DATA_ADDR0 or OB_DATA_ADDR1 + only one parameter can be selected which is shown as below: + \arg OB_DATA_ADDR0: option byte data address 0 + \arg OB_DATA_ADDR1: option byte data address 1 + \param[in] data: the byte to be programmed + \param[out] none + \retval fmc_state +*/ +fmc_state_enum ob_data_program(uint32_t address, uint8_t data) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + ob_parm_struct ob_parm; + ob_parm_get(&ob_parm); + if(0xFFFFU == REG16(address)) { + if(FMC_READY == fmc_state) { + /* set the OBPG bit */ + FMC_CTL |= FMC_CTL_OBPG; + + REG16(address) = data ; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } + } else { + if(FMC_READY == fmc_state) { + /* start erase the option byte */ + FMC_CTL |= FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + + /* enable the option bytes programming */ + FMC_CTL |= FMC_CTL_OBPG; + + ob_value_modify(address, (uint16_t)data, &ob_parm); + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } else { + if(FMC_TOERR != fmc_state) { + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + } + } + } + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief get OB_USER in register FMC_OBSTAT + \param[in] none + \param[out] none + \retval ob_user +*/ +uint8_t ob_user_get(void) +{ + return (uint8_t)(FMC_OBSTAT >> 8U); +} + +/*! + \brief get OB_DATA in register FMC_OBSTAT + \param[in] none + \param[out] none + \retval ob_data +*/ +uint16_t ob_data_get(void) +{ + return (uint16_t)(FMC_OBSTAT >> 16U); +} + +/*! + \brief get the FMC option byte write protection (OB_WP) in register FMC_WP + \param[in] none + \param[out] none + \retval OB_WP +*/ +uint16_t ob_write_protection_get(void) +{ + return (uint16_t)(FMC_WP); +} + +/*! + \brief get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register + \param[in] none + \param[out] none + \retval the value of PLEVEL +*/ +uint32_t ob_obstat_plevel_get(void) +{ + return (FMC_OBSTAT & (FMC_OBSTAT_PLEVEL_BIT0 | FMC_OBSTAT_PLEVEL_BIT1)); +} + +/* FMC interrupts and flags management functions */ +/*! + \brief enable FMC interrupt + \param[in] interrupt: the FMC interrupt source + one or more parameters can be selected which are shown as below: + \arg FMC_INTEN_END: FMC end of operation interrupt + \arg FMC_INTEN_ERR: FMC error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_enable(uint32_t interrupt) +{ + FMC_CTL |= interrupt; +} + +/*! + \brief disable FMC interrupt + \param[in] interrupt: the FMC interrupt source + one or more parameters can be selected which are shown as below: + \arg FMC_INTEN_END: FMC end of operation interrupt + \arg FMC_INTEN_ERR: FMC error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_disable(uint32_t interrupt) +{ + FMC_CTL &= ~(uint32_t)interrupt; +} + +/*! + \brief get flag set or reset + \param[in] flag: check FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_BUSY: FMC busy flag + \arg FMC_FLAG_PGERR: FMC programming error flag + \arg FMC_FLAG_WPERR: FMC write protection error flag + \arg FMC_FLAG_END: FMC end of programming flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_flag_get(uint32_t flag) +{ + FlagStatus status = RESET; + + if(FMC_STAT & flag) { + status = SET; + } + /* return the state of corresponding FMC flag */ + return status; +} + +/*! + \brief clear the FMC pending flag by writing 1 + \param[in] flag: clear FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_PGERR: FMC programming error flag + \arg FMC_FLAG_WPERR: FMC write protection error flag + \arg FMC_FLAG_END: fmc end of programming flag + \param[out] none + \retval none +*/ +void fmc_flag_clear(uint32_t flag) +{ + /* clear the flags */ + FMC_STAT = flag; +} + +/*! + \brief get flag set or reset + \param[in] flag: check FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_PGERR: FMC programming error flag + \arg FMC_FLAG_WPERR: FMC write protection error flag + \arg FMC_FLAG_END: FMC end of programming flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_interrupt_flag_get(uint32_t flag) +{ + FlagStatus status = RESET; + + if(FMC_STAT & flag) { + status = SET; + } + /* return the state of corresponding FMC flag */ + return status; +} + +/*! + \brief clear the FMC pending flag by writing 1 + \param[in] flag: clear FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_PGERR: FMC programming error flag + \arg FMC_FLAG_WPERR: FMC write protection error flag + \arg FMC_FLAG_END: fmc end of programming flag + \param[out] none + \retval none +*/ +void fmc_interrupt_flag_clear(uint32_t flag) +{ + /* clear the flags */ + FMC_STAT = flag; +} + +/*! + \brief get the FMC state + \param[in] none + \param[out] none + \retval fmc_state +*/ +fmc_state_enum fmc_state_get(void) +{ + fmc_state_enum fmc_state = FMC_READY; + + if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)) { + fmc_state = FMC_BUSY; + } else { + if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR)) { + fmc_state = FMC_WPERR; + } else { + if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_PGERR)) { + fmc_state = FMC_PGERR; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief check whether FMC is ready or not + \param[in] timeout: timeout count + \param[out] none + \retval fmc_state +*/ +fmc_state_enum fmc_ready_wait(uint32_t timeout) +{ + fmc_state_enum fmc_state = FMC_BUSY; + + /* wait for FMC ready */ + do { + /* get FMC state */ + fmc_state = fmc_state_get(); + timeout--; + } while((FMC_BUSY == fmc_state) && (0U != timeout)); + + if(FMC_BUSY == fmc_state) { + fmc_state = FMC_TOERR; + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief get current option byte value + \param[in] ob_parm: pointer to option byte parameter struct + \param[out] ob_parm: pointer to option byte parameter struct + \retval none +*/ +void ob_parm_get(ob_parm_struct *ob_parm) +{ + /* get current option byte value */ + ob_parm->spc = (uint8_t)OB_SPC; + ob_parm->user = (uint8_t)OB_USER; + ob_parm->data0 = (uint8_t)OB_DATA0; + ob_parm->data1 = (uint8_t)OB_DATA1; + ob_parm->wp0 = (uint8_t)OB_WP0; + ob_parm->wp1 = (uint8_t)OB_WP1; +} + +/*! + \brief modify the target option byte depending on the original value + \param[in] address: target option byte address + \param[in] value: target option byte value + \param[in] ob_parm: pointer to option byte parameter struct + \param[out] none + \retval none +*/ +void ob_value_modify(uint32_t address, uint16_t value, ob_parm_struct *ob_parm) +{ + uint8_t spc, user, data0, data1, wp0, wp1; + /* store the original option bytes */ + spc = ob_parm->spc; + user = ob_parm->user; + data0 = ob_parm->data0; + data1 = ob_parm->data1; + wp0 = ob_parm->wp0; + wp1 = ob_parm->wp1; + + /* bring in the target option byte */ + if(OB_SPC_ADDR == address) { + spc = (uint8_t)value; + } else if(OB_DATA_ADDR0 == address) { + data0 = (uint8_t)value; + } else if(OB_DATA_ADDR1 == address) { + data1 = (uint8_t)value; + } else if(OB_USER_ADDR == address) { + user = user & (uint8_t)value; + } else { + wp0 = wp0 & ((uint8_t)(value)); + wp1 = wp1 & ((uint8_t)(value >> 8U)); + } + /* basing on original value, modify the target option byte */ + OB_SPC = spc; + OB_USER = user; + if(0xFFU != data0) { + OB_DATA0 = data0; + } + if(0xFFU != data1) { + OB_DATA1 = data1; + } + if(0xFFU != wp0) { + OB_WP0 = wp0; + } + if(0xFFU != wp1) { + OB_WP1 = wp1; + } +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_fwdgt.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_fwdgt.c new file mode 100644 index 000000000..b6eb6f7e1 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_fwdgt.c @@ -0,0 +1,181 @@ +/*! + \file gd32f3x0_fwdgt.c + \brief FWDGT driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_fwdgt.h" + +/*! + \brief enable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_enable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; +} + +/*! + \brief disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_disable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; +} + +/*! + \brief start the free watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_enable(void) +{ + FWDGT_CTL = FWDGT_KEY_ENABLE; +} + +/*! + \brief configure the free watchdog timer counter window value + \param[in] window_value: specify window value(0x0000 - 0x0FFF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_window_value_config(uint16_t window_value) +{ + uint32_t time_index = FWDGT_WND_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_WND */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the WUD flag to be reset */ + do { + flag_status = FWDGT_STAT & FWDGT_STAT_WUD; + } while((--time_index > 0U) && (RESET != flag_status)); + + if(RESET != flag_status) { + return ERROR; + } + + FWDGT_WND = WND_WND(window_value); + + return SUCCESS; +} + +/*! + \brief reload the counter of FWDGT + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_counter_reload(void) +{ + FWDGT_CTL = FWDGT_KEY_RELOAD; +} + +/*! + \brief configure counter reload value, and prescaler divider value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[in] prescaler_div: FWDGT prescaler value + only one parameter can be selected which is shown as below: + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_PSC,and FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the PUD flag to be reset */ + do { + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + } while((--timeout > 0U) && (RESET != flag_status)); + + if(RESET != flag_status) { + return ERROR; + } + + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_div; + + timeout = FWDGT_RLD_TIMEOUT; + /* wait until the RUD flag to be reset */ + do { + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + } while((--timeout > 0U) && (RESET != flag_status)); + + if(RESET != flag_status) { + return ERROR; + } + + FWDGT_RLD = RLD_RLD(reload_value); + + /* reload the counter */ + FWDGT_CTL = FWDGT_KEY_RELOAD; + + return SUCCESS; +} + +/*! + \brief get flag state of FWDGT + \param[in] flag: flag to get + only one parameter can be selected which is shown as below: + \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going + \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going + \arg FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fwdgt_flag_get(uint16_t flag) +{ + if(FWDGT_STAT & flag) { + return SET; + } + return RESET; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_gpio.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_gpio.c new file mode 100644 index 000000000..1d8c7dc1c --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_gpio.c @@ -0,0 +1,426 @@ +/*! + \file gd32f3x0_gpio.c + \brief GPIO driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_gpio.h" + +/*! + \brief reset GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[out] none + \retval none +*/ +void gpio_deinit(uint32_t gpio_periph) +{ + switch(gpio_periph) { + case GPIOA: + /* reset GPIOA */ + rcu_periph_reset_enable(RCU_GPIOARST); + rcu_periph_reset_disable(RCU_GPIOARST); + break; + case GPIOB: + /* reset GPIOB */ + rcu_periph_reset_enable(RCU_GPIOBRST); + rcu_periph_reset_disable(RCU_GPIOBRST); + break; + case GPIOC: + /* reset GPIOC */ + rcu_periph_reset_enable(RCU_GPIOCRST); + rcu_periph_reset_disable(RCU_GPIOCRST); + break; + case GPIOD: + /* reset GPIOD */ + rcu_periph_reset_enable(RCU_GPIODRST); + rcu_periph_reset_disable(RCU_GPIODRST); + break; + case GPIOF: + /* reset GPIOF */ + rcu_periph_reset_enable(RCU_GPIOFRST); + rcu_periph_reset_disable(RCU_GPIOFRST); + break; + default: + break; + } +} + +/*! + \brief set GPIO mode + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] mode: gpio pin mode + only one parameter can be selected which is shown as below: + \arg GPIO_MODE_INPUT: input mode + \arg GPIO_MODE_OUTPUT: output mode + \arg GPIO_MODE_AF: alternate function mode + \arg GPIO_MODE_ANALOG: analog mode + \param[in] pull_up_down: gpio pin with pull-up or pull-down resistor + only one parameter can be selected which is shown as below: + \arg GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors + \arg GPIO_PUPD_PULLUP: with pull-up resistor + \arg GPIO_PUPD_PULLDOWN:with pull-down resistor + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin) +{ + uint16_t i; + uint32_t ctl, pupd; + + ctl = GPIO_CTL(gpio_periph); + pupd = GPIO_PUD(gpio_periph); + + for(i = 0U; i < 16U; i++) { + if((1U << i) & pin) { + /* clear the specified pin mode bits */ + ctl &= ~GPIO_MODE_MASK(i); + /* set the specified pin mode bits */ + ctl |= GPIO_MODE_SET(i, mode); + + /* clear the specified pin pupd bits */ + pupd &= ~GPIO_PUPD_MASK(i); + /* set the specified pin pupd bits */ + pupd |= GPIO_PUPD_SET(i, pull_up_down); + } + } + + GPIO_CTL(gpio_periph) = ctl; + GPIO_PUD(gpio_periph) = pupd; +} + +/*! + \brief set GPIO output type and speed + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] otype: gpio pin output mode + only one parameter can be selected which is shown as below: + \arg GPIO_OTYPE_PP: push pull mode + \arg GPIO_OTYPE_OD: open drain mode + \param[in] speed: gpio pin output max speed + only one parameter can be selected which is shown as below: + \arg GPIO_OSPEED_2MHZ: output max speed 2MHz + \arg GPIO_OSPEED_10MHZ: output max speed 10MHz + \arg GPIO_OSPEED_50MHZ: output max speed 50MHz + \arg GPIO_OSPEED_MAX: GPIO very high output speed, max speed more than 50MHz + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin) +{ + uint16_t i; + uint32_t ospeed0, ospeed1; + + if(GPIO_OTYPE_OD == otype) { + GPIO_OMODE(gpio_periph) |= (uint32_t)pin; + } else { + GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin); + } + + /* get the specified pin output speed bits value */ + ospeed0 = GPIO_OSPD0(gpio_periph); + + if(GPIO_OSPEED_MAX == speed) { + ospeed1 = GPIO_OSPD1(gpio_periph); + + for(i = 0U; i < 16U; i++) { + if((1U << i) & pin) { + /* enable very high output speed function of the pin when the corresponding OSPDy(y=0..15) + is "11" (output max speed 50MHz) */ + ospeed0 |= GPIO_OSPEED_SET(i, 0x03); + ospeed1 |= (1U << i); + } + } + GPIO_OSPD0(gpio_periph) = ospeed0; + GPIO_OSPD1(gpio_periph) = ospeed1; + } else { + for(i = 0U; i < 16U; i++) { + if((1U << i) & pin) { + /* clear the specified pin output speed bits */ + ospeed0 &= ~GPIO_OSPEED_MASK(i); + /* set the specified pin output speed bits */ + ospeed0 |= GPIO_OSPEED_SET(i, speed); + } + } + GPIO_OSPD0(gpio_periph) = ospeed0; + } +} + +/*! + \brief set GPIO pin bit + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BOP(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief reset GPIO pin bit + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BC(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief write data to the specified GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] bit_value: SET or RESET + only one parameter can be selected which is shown as below: + \arg RESET: clear the port pin + \arg SET: set the port pin + \param[out] none + \retval none +*/ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) +{ + if(RESET != bit_value) { + GPIO_BOP(gpio_periph) = (uint32_t)pin; + } else { + GPIO_BC(gpio_periph) = (uint32_t)pin; + } +} + +/*! + \brief write data to the specified GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] data: specify the value to be written to the port output control register + \param[out] none + \retval none +*/ +void gpio_port_write(uint32_t gpio_periph, uint16_t data) +{ + GPIO_OCTL(gpio_periph) = (uint32_t)data; +} + +/*! + \brief get GPIO pin input status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval SET or RESET +*/ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph) & (pin))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get GPIO all pins input status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[out] none + \retval state of GPIO all pins +*/ +uint16_t gpio_input_port_get(uint32_t gpio_periph) +{ + return (uint16_t)GPIO_ISTAT(gpio_periph); +} + +/*! + \brief get GPIO pin output status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval SET or RESET +*/ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if((uint32_t)RESET != (GPIO_OCTL(gpio_periph) & (pin))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get GPIO all pins output status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[out] none + \retval state of GPIO all pins +*/ +uint16_t gpio_output_port_get(uint32_t gpio_periph) +{ + return (uint16_t)GPIO_OCTL(gpio_periph); +} + +/*! + \brief set GPIO alternate function + \param[in] gpio_periph: GPIOx(x = A,B,C) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C) + \param[in] alt_func_num: GPIO pin af function, please refer to specific device datasheet + only one parameter can be selected which is shown as below: + \arg GPIO_AF_0: TIMER2, TIMER13, TIMER14, TIMER16, SPI0, SPI1, I2S0, CK_OUT, USART0, CEC, + IFRP, TSI, CTC, I2C0, I2C1, SWDIO, SWCLK + \arg GPIO_AF_1: USART0, USART1, TIMER2, TIMER14, I2C0, I2C1, IFRP, CEC + \arg GPIO_AF_2: TIMER0, TIMER1, TIMER15, TIMER16, I2S0 + \arg GPIO_AF_3: TSI, I2C0, TIMER14 + \arg GPIO_AF_4(port A,B only): USART1, I2C0, I2C1, TIMER13 + \arg GPIO_AF_5(port A,B only): TIMER15, TIMER16, USBFS, I2S0 + \arg GPIO_AF_6(port A,B only): CTC, SPI1 + \arg GPIO_AF_7(port A,B only): CMP0, CMP1 + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin) +{ + uint16_t i; + uint32_t afrl, afrh; + + afrl = GPIO_AFSEL0(gpio_periph); + afrh = GPIO_AFSEL1(gpio_periph); + + for(i = 0U; i < 8U; i++) { + if((1U << i) & pin) { + /* clear the specified pin alternate function bits */ + afrl &= ~GPIO_AFR_MASK(i); + afrl |= GPIO_AFR_SET(i, alt_func_num); + } + } + + for(i = 8U; i < 16U; i++) { + if((1U << i) & pin) { + /* clear the specified pin alternate function bits */ + afrh &= ~GPIO_AFR_MASK(i - 8U); + afrh |= GPIO_AFR_SET(i - 8U, alt_func_num); + } + } + + GPIO_AFSEL0(gpio_periph) = afrl; + GPIO_AFSEL1(gpio_periph) = afrh; +} + +/*! + \brief lock GPIO pin bit + \param[in] gpio_periph: GPIOx(x = A,B) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) +{ + uint32_t lock = 0x00010000U; + lock |= pin; + + /* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */ + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + GPIO_LOCK(gpio_periph) = (uint32_t)pin; + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + lock = GPIO_LOCK(gpio_periph); + lock = GPIO_LOCK(gpio_periph); +} + +/*! + \brief toggle GPIO pin status + \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_TG(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief toggle GPIO port status + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,D,F) + \param[out] none + \retval none +*/ +void gpio_port_toggle(uint32_t gpio_periph) +{ + GPIO_TG(gpio_periph) = 0x0000FFFFU; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_i2c.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_i2c.c new file mode 100644 index 000000000..6d25d2e3a --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_i2c.c @@ -0,0 +1,731 @@ +/*! + \file gd32f3x0_i2c.c + \brief I2C driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_i2c.h" + +/* I2C register bit mask */ +#define I2CCLK_MAX ((uint32_t)0x0000003FU) /*!< i2cclk maximum value */ +#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ +#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ +#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ +#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ + +/* I2C register bit offset */ +#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ + +/*! + \brief reset I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_deinit(uint32_t i2c_periph) +{ + switch(i2c_periph) { + case I2C0: + /* reset I2C0 */ + rcu_periph_reset_enable(RCU_I2C0RST); + rcu_periph_reset_disable(RCU_I2C0RST); + break; + case I2C1: + /* reset I2C1 */ + rcu_periph_reset_enable(RCU_I2C1RST); + rcu_periph_reset_disable(RCU_I2C1RST); + break; + default: + break; + } +} + +/*! + \brief configure I2C clock + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) + and fast mode plus (up to 1MHz) + \param[in] dutycyc: duty cycle in fast mode or fast mode plus + only one parameter can be selected which is shown as below: + \arg I2C_DTCY_2: T_low/T_high=2 + \arg I2C_DTCY_16_9: T_low/T_high=16/9 + \param[out] none + \retval none +*/ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) +{ + uint32_t pclk1, clkc, freq, risetime; + uint32_t temp; + + pclk1 = rcu_clock_freq_get(CK_APB1); + /* I2C peripheral clock frequency */ + freq = (uint32_t)(pclk1 / 1000000U); + if(freq >= I2CCLK_MAX) { + freq = I2CCLK_MAX; + } + temp = I2C_CTL1(i2c_periph); + temp &= ~I2C_CTL1_I2CCLK; + temp |= freq; + + I2C_CTL1(i2c_periph) = temp; + + if(100000U >= clkspeed) { + /* the maximum SCL rise time is 1000ns in standard mode */ + risetime = (uint32_t)((pclk1 / 1000000U) + 1U); + if(risetime >= I2CCLK_MAX) { + I2C_RT(i2c_periph) = I2CCLK_MAX; + } else if(risetime <= I2CCLK_MIN) { + I2C_RT(i2c_periph) = I2CCLK_MIN; + } else { + I2C_RT(i2c_periph) = risetime; + } + clkc = (uint32_t)(pclk1 / (clkspeed * 2U)); + if(clkc < 0x04U) { + /* the CLKC in standard mode minmum value is 4 */ + clkc = 0x04U; + } + I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); + + } else if(400000U >= clkspeed) { + /* the maximum SCL rise time is 300ns in fast mode */ + I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)300U) / (uint32_t)1000U) + (uint32_t)1U); + if(I2C_DTCY_2 == dutycyc) { + /* I2C duty cycle is 2 */ + clkc = (uint32_t)(pclk1 / (clkspeed * 3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + } else { + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t)(pclk1 / (clkspeed * 25U)); + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; + } + if(0U == (clkc & I2C_CKCFG_CLKC)) { + /* the CLKC in fast mode minmum value is 1 */ + clkc |= 0x0001U; + } + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; + I2C_CKCFG(i2c_periph) |= clkc; + } else { + /* fast mode plus, the maximum SCL rise time is 120ns */ + I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)120U) / (uint32_t)1000U) + (uint32_t)1U); + if(I2C_DTCY_2 == dutycyc) { + /* I2C duty cycle is 2 */ + clkc = (uint32_t)(pclk1 / (clkspeed * 3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + } else { + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t)(pclk1 / (clkspeed * 25U)); + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; + } + /* enable fast mode */ + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; + I2C_CKCFG(i2c_periph) |= clkc; + /* enable I2C fast mode plus */ + I2C_FMPCFG(i2c_periph) = I2C_FMPCFG_FMPEN; + } +} + +/*! + \brief configure I2C address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] mode: + only one parameter can be selected which is shown as below: + \arg I2C_I2CMODE_ENABLE: I2C mode + \arg I2C_SMBUSMODE_ENABLE: SMBus mode + \param[in] addformat: 7bits or 10bits + only one parameter can be selected which is shown as below: + \arg I2C_ADDFORMAT_7BITS: 7bits + \arg I2C_ADDFORMAT_10BITS: 10bits + \param[in] addr: I2C address + \param[out] none + \retval none +*/ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) +{ + /* SMBus/I2C mode selected */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SMBEN); + ctl |= mode; + I2C_CTL0(i2c_periph) = ctl; + + /* configure address */ + addr = addr & I2C_ADDRESS_MASK; + I2C_SADDR0(i2c_periph) = (addformat | addr); +} + +/*! + \brief SMBus type selection + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] type: + only one parameter can be selected which is shown as below: + \arg I2C_SMBUS_DEVICE: device + \arg I2C_SMBUS_HOST: host + \param[out] none + \retval none +*/ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) +{ + if(I2C_SMBUS_HOST == type) { + I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; + } else { + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); + } +} + +/*! + \brief whether or not to send an ACK + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] ack: + only one parameter can be selected which is shown as below: + \arg I2C_ACK_ENABLE: ACK will be sent + \arg I2C_ACK_DISABLE: ACK will not be sent + \param[out] none + \retval none +*/ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) +{ + if(I2C_ACK_ENABLE == ack) { + I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; + } else { + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); + } +} + +/*! + \brief configure I2C position of ACK and PEC when receiving + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pos: + only one parameter can be selected which is shown as below: + \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current + \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte + \param[out] none + \retval none +*/ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) +{ + /* configure I2C POAP position */ + if(I2C_ACKPOS_NEXT == pos) { + I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; + } else { + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); + } +} + +/*! + \brief master sends slave address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] addr: slave address + \param[in] trandirection: transmitter or receiver + only one parameter can be selected which is shown as below: + \arg I2C_TRANSMITTER: transmitter + \arg I2C_RECEIVER: receiver + \param[out] none + \retval none +*/ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) +{ + /* master is a transmitter or a receiver */ + if(I2C_TRANSMITTER == trandirection) { + addr = addr & I2C_TRANSMITTER; + } else { + addr = addr | I2C_RECEIVER; + } + /* send slave address */ + I2C_DATA(i2c_periph) = addr; +} + +/*! + \brief enable dual-address mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] addr: the second address in dual-address mode + \param[out] none + \retval none +*/ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) +{ + /* configure address */ + addr = addr & I2C_ADDRESS2_MASK; + I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr); +} + +/*! + \brief disable dual-address mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_dualaddr_disable(uint32_t i2c_periph) +{ + I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); +} + +/*! + \brief enable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; +} + +/*! + \brief disable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); +} + +/*! + \brief generate a START condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_start_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_START; +} + +/*! + \brief generate a STOP condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_stop_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; +} + +/*! + \brief I2C transmit data function + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) +{ + I2C_DATA(i2c_periph) = DATA_TRANS(data); +} + +/*! + \brief I2C receive data function + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval data of received +*/ +uint8_t i2c_data_receive(uint32_t i2c_periph) +{ + return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); +} + +/*! + \brief enable I2C DMA mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dmastate: + only one parameter can be selected which is shown as below: + \arg I2C_DMA_ON: DMA mode enable + \arg I2C_DMA_OFF: DMA mode disable + \param[out] none + \retval none +*/ +void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) +{ + /* configure I2C DMA function */ + uint32_t ctl = 0U; + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMAON); + ctl |= dmastate; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief configure whether next DMA EOT is DMA last transfer or not + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dmalast: + only one parameter can be selected which is shown as below: + \arg I2C_DMALST_ON: next DMA EOT is the last transfer + \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer + \param[out] none + \retval none +*/ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) +{ + /* configure DMA last transfer */ + uint32_t ctl = 0U; + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMALST); + ctl |= dmalast; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief whether to stretch SCL low when data is not ready in slave mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] stretchpara: + only one parameter can be selected which is shown as below: + \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled + \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled + \param[out] none + \retval none +*/ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) +{ + /* configure I2C SCL strerching enable or disable */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SS); + ctl |= stretchpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief whether or not to response to a general call + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] gcallpara: + only one parameter can be selected which is shown as below: + \arg I2C_GCEN_ENABLE: slave will response to a general call + \arg I2C_GCEN_DISABLE: slave will not response to a general call + \param[out] none + \retval none +*/ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) +{ + /* configure slave response to a general call enable or disable */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_GCEN); + ctl |= gcallpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief software reset I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] sreset: + only one parameter can be selected which is shown as below: + \arg I2C_SRESET_SET: I2C is under reset + \arg I2C_SRESET_RESET: I2C is not under reset + \param[out] none + \retval none +*/ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) +{ + /* modify CTL0 and configure software reset I2C state */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SRESET); + ctl |= sreset; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief whether to enable I2C PEC calculation or not + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pecpara: + only one parameter can be selected which is shown as below: + \arg I2C_PEC_ENABLE: PEC calculation on + \arg I2C_PEC_DISABLE: PEC calculation off + \param[out] none + \retval none +*/ +void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) +{ + /* on/off PEC calculation */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECEN); + ctl |= pecstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief I2C whether to transfer PEC value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pecpara: + only one parameter can be selected which is shown as below: + \arg I2C_PECTRANS_ENABLE: transfer PEC + \arg I2C_PECTRANS_DISABLE: not transfer PEC + \param[out] none + \retval none +*/ +void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) +{ + /* whether to transfer PEC */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECTRANS); + ctl |= pecpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief get packet error checking value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval PEC value +*/ +uint8_t i2c_pec_value_get(uint32_t i2c_periph) +{ + return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV) >> STAT1_PECV_OFFSET); +} + +/*! + \brief I2C issue alert through SMBA pin + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] smbuspara: + only one parameter can be selected which is shown as below: + \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin + \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin + \param[out] none + \retval none +*/ +void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) +{ + /* issue alert through SMBA pin configure*/ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SALT); + ctl |= smbuspara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief whether ARP is enabled under SMBus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] arpstate: + only one parameter can be selected which is shown as below: + \arg I2C_ARP_ENABLE: enable ARP + \arg I2C_ARP_DISABLE: disable ARP + \param[out] none + \retval none +*/ +void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) +{ + /* enable or disable I2C ARP protocol */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_ARPEN); + ctl |= arpstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief check I2C flag is set or not + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SBSEND: start condition send out + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode + \arg I2C_FLAG_BTC: byte transmission finishes + \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode + \arg I2C_FLAG_STPDET: stop condition detected in slave mode + \arg I2C_FLAG_RBNE: I2C_DATA is not empty during receiving + \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_SMBALT: SMBus alert status + \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode + \arg I2C_FLAG_I2CBSY: busy flag + \arg I2C_FLAG_TR: whether the I2C is a transmitter or a receiver + \arg I2C_FLAG_RXGC: general call address (00h) received + \arg I2C_FLAG_DEFSMB: default address of SMBus device + \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode + \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) +{ + if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear I2C flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SMBALT: SMBus Alert status + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_BERR: a bus error + \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 + \param[out] none + \retval none +*/ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) +{ + if(I2C_FLAG_ADDSEND == flag) { + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + } else { + I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); + } +} + +/*! + \brief enable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \param[out] none + \retval none +*/ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief disable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] interrupt: interrupt type + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt enable + \arg I2C_INT_EV: event interrupt enable + \arg I2C_INT_BUF: buffer interrupt enable + \param[out] none + \retval none +*/ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief check I2C interrupt flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BTC: byte transmission finishes + \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag + \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag + \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag + \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U, bufie; + + /* check BUFIE */ + bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; + + /* get the interrupt enable bit status */ + intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); + + if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)) { + if(intenable && bufie) { + intenable = 1U; + } else { + intenable = 0U; + } + } + if((0U != flagstatus) && (0U != intenable)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear I2C interrupt flag + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] intflag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag + \param[out] none + \retval none +*/ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + if(I2C_INT_FLAG_ADDSEND == int_flag) { + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + } else { + I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); + } +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_misc.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_misc.c new file mode 100644 index 000000000..307ade502 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_misc.c @@ -0,0 +1,192 @@ +/*! + \file gd32f3x0_misc.c + \brief MISC driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_misc.h" + +/*! + \brief set the priority group + \param[in] nvic_prigroup: the NVIC priority group + only one parameter can be selected which is shown as below: + \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority + \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority + \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority + \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority + \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority + \param[out] none + \retval none +*/ +void nvic_priority_group_set(uint32_t nvic_prigroup) +{ + /* set the priority group value */ + SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup; +} + +/*! + \brief enable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set + \param[in] nvic_irq_sub_priority: the subpriority needed to set + \param[out] none + \retval none +*/ +void nvic_irq_enable(uint8_t nvic_irq, + uint8_t nvic_irq_pre_priority, + uint8_t nvic_irq_sub_priority) +{ + uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; + + /* use the priority group value to get the temp_pre and the temp_sub */ + switch((SCB->AIRCR) & (uint32_t)0x700U) { + case NVIC_PRIGROUP_PRE0_SUB4: + temp_pre = 0U; + temp_sub = 0x4U; + break; + case NVIC_PRIGROUP_PRE1_SUB3: + temp_pre = 1U; + temp_sub = 0x3U; + break; + case NVIC_PRIGROUP_PRE2_SUB2: + temp_pre = 2U; + temp_sub = 0x2U; + break; + case NVIC_PRIGROUP_PRE3_SUB1: + temp_pre = 3U; + temp_sub = 0x1U; + break; + case NVIC_PRIGROUP_PRE4_SUB0: + temp_pre = 4U; + temp_sub = 0x0U; + break; + default: + nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); + temp_pre = 2U; + temp_sub = 0x2U; + break; + } + + /* get the temp_priority to fill the NVIC->IP register */ + temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); + temp_priority |= nvic_irq_sub_priority & (0x0FU >> (0x4U - temp_sub)); + temp_priority = temp_priority << 0x04U; + NVIC->IP[nvic_irq] = (uint8_t)temp_priority; + + /* enable the selected IRQ */ + NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); +} + +/*! + \brief disable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[out] none + \retval none +*/ +void nvic_irq_disable(uint8_t nvic_irq) +{ + /* disable the selected IRQ.*/ + NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); +} + +/*! + \brief set the NVIC vector table base address + \param[in] nvic_vict_tab: the RAM or FLASH base address + only one parameter can be selected which is shown as below: + \arg NVIC_VECTTAB_RAM: RAM base address + \are NVIC_VECTTAB_FLASH: Flash base address + \param[in] offset: Vector Table offset + \param[out] none + \retval none +*/ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) +{ + SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); + __DSB(); +} + +/*! + \brief set the state of the low power mode + \param[in] lowpower_mode: the low power mode state + only one parameter can be selected which is shown as below: + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up + by all the enable and disable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_set(uint8_t lowpower_mode) +{ + SCB->SCR |= (uint32_t)lowpower_mode; +} + +/*! + \brief reset the state of the low power mode + \param[in] lowpower_mode: the low power mode state + only one parameter can be selected which is shown as below: + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be + woke up by the enable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_reset(uint8_t lowpower_mode) +{ + SCB->SCR &= (~(uint32_t)lowpower_mode); +} + +/*! + \brief set the systick clock source + \param[in] systick_clksource: the systick clock source needed to choose + only one parameter can be selected which is shown as below: + \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK + \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 + \param[out] none + \retval none +*/ + +void systick_clksource_set(uint32_t systick_clksource) +{ + if(SYSTICK_CLKSOURCE_HCLK == systick_clksource) { + /* set the systick clock source from HCLK */ + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } else { + /* set the systick clock source from HCLK/8 */ + SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; + } +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_pmu.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_pmu.c new file mode 100644 index 000000000..df255135c --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_pmu.c @@ -0,0 +1,423 @@ +/*! + \file gd32f3x0_pmu.c + \brief PMU driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2021, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_pmu.h" + + +/*! + \brief reset PMU register + \param[in] none + \param[out] none + \retval none +*/ +void pmu_deinit(void) +{ + /* reset PMU */ + rcu_periph_reset_enable(RCU_PMURST); + rcu_periph_reset_disable(RCU_PMURST); +} + +/*! + \brief select low voltage detector threshold + \param[in] lvdt_n: + only one parameter can be selected which is shown as below: + \arg PMU_LVDT_0: voltage threshold is 2.1V + \arg PMU_LVDT_1: voltage threshold is 2.3V + \arg PMU_LVDT_2: voltage threshold is 2.4V + \arg PMU_LVDT_3: voltage threshold is 2.6V + \arg PMU_LVDT_4: voltage threshold is 2.7V + \arg PMU_LVDT_5: voltage threshold is 2.9V + \arg PMU_LVDT_6: voltage threshold is 3.0V + \arg PMU_LVDT_7: voltage threshold is 3.1V + \param[out] none + \retval none +*/ +void pmu_lvd_select(uint32_t lvdt_n) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; + /* clear LVDT bits */ + PMU_CTL &= ~PMU_CTL_LVDT; + /* set LVDT bits according to lvdt_n */ + PMU_CTL |= lvdt_n; + /* enable LVD */ + PMU_CTL |= PMU_CTL_LVDEN; +} + +/*! + \brief select LDO output voltage + these bits set by software when the main PLL closed + \param[in] ldo_output: + only one parameter can be selected which is shown as below: + \arg PMU_LDOVS_LOW: LDO output voltage low mode + \arg PMU_LDOVS_MID: LDO output voltage mid mode + \arg PMU_LDOVS_HIGH: LDO output voltage high mode + \param[out] none + \retval none +*/ +void pmu_ldo_output_select(uint32_t ldo_output) +{ + PMU_CTL &= ~PMU_CTL_LDOVS; + PMU_CTL |= ldo_output; +} + +/*! + \brief disable PMU lvd + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lvd_disable(void) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; +} + +/*! + \brief enable low-driver mode in deep-sleep mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lowdriver_mode_enable(void) +{ + PMU_CTL &= ~PMU_CTL_LDEN; + PMU_CTL |= PMU_LOWDRIVER_ENABLE; +} + +/*! + \brief disable low-driver mode in deep-sleep mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lowdriver_mode_disable(void) +{ + PMU_CTL &= ~PMU_CTL_LDEN; + PMU_CTL |= PMU_LOWDRIVER_DISABLE; +} + +/*! + \brief enable high-driver mode + this bit set by software only when IRC8M or HXTAL used as system clock + \param[in] none + \param[out] none + \retval none +*/ +void pmu_highdriver_mode_enable(void) +{ + PMU_CTL |= PMU_CTL_HDEN; +} + +/*! + \brief disable high-driver mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_highdriver_mode_disable(void) +{ + PMU_CTL &= ~PMU_CTL_HDEN; +} + +/*! + \brief switch high-driver mode + this bit set by software only when IRC8M or HXTAL used as system clock + \param[in] highdr_switch: + only one parameter can be selected which is shown as below: + \arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch + \arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch + \param[out] none + \retval none +*/ +void pmu_highdriver_switch_select(uint32_t highdr_switch) +{ + /* wait for HDRF flag to be set */ + while(SET != pmu_flag_get(PMU_FLAG_HDR)) { + } + PMU_CTL &= ~PMU_CTL_HDS; + PMU_CTL |= highdr_switch; +} + +/*! + \brief low-driver mode when use low power LDO + \param[in] mode: + only one parameter can be selected which is shown as below: + \arg PMU_NORMALDR_LOWPWR: normal-driver when use low power LDO + \arg PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO + \param[out] none + \retval none +*/ +void pmu_lowpower_driver_config(uint32_t mode) +{ + PMU_CTL &= ~PMU_CTL_LDLP; + PMU_CTL |= mode; +} + +/*! + \brief low-driver mode when use normal power LDO + \param[in] mode: + only one parameter can be selected which is shown as below: + \arg PMU_NORMALDR_NORMALPWR: normal-driver when use low power LDO + \arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use low power LDO + \param[out] none + \retval none +*/ +void pmu_normalpower_driver_config(uint32_t mode) +{ + PMU_CTL &= ~PMU_CTL_LDNP; + PMU_CTL |= mode; +} + +/*! + \brief PMU work at sleep mode + \param[in] sleepmodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_sleepmode(uint8_t sleepmodecmd) +{ + /* clear sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + /* select WFI or WFE command to enter sleep mode */ + if(WFI_CMD == sleepmodecmd) { + __WFI(); + } else { + __WFE(); + } +} + +/*! + \brief PMU work at deepsleep mode + \param[in] ldo: + only one parameter can be selected which is shown as below: + \arg PMU_LDO_NORMAL: LDO operates normally when pmu enter deepsleep mode + \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode + \param[in] lowdrive: + only one parameter can be selected which is shown as below: + \arg PMU_LOWDRIVER_ENABLE: low-driver mode enable in deep-sleep mode + \arg PMU_LOWDRIVER_DISABLE: low-driver mode disable in deep-sleep mode + \param[in] deepsleepmodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd) +{ + static uint32_t reg_snap[ 4 ]; + /* clear stbmod and ldolp bits */ + PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP | PMU_CTL_LDEN | PMU_CTL_LDNP | PMU_CTL_LDLP)); + + /* set ldolp bit according to pmu_ldo */ + PMU_CTL |= ldo; + + /* low drive mode config in deep-sleep mode */ + if(PMU_LOWDRIVER_ENABLE == lowdrive) { + if(PMU_LDO_NORMAL == ldo) { + PMU_CTL |= (uint32_t)(PMU_CTL_LDEN | PMU_CTL_LDNP); + } else { + PMU_CTL |= (uint32_t)(PMU_CTL_LDEN | PMU_CTL_LDLP); + } + } + + /* set sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + reg_snap[0] = REG32(0xE000E010U); + reg_snap[1] = REG32(0xE000E100U); + reg_snap[2] = REG32(0xE000E104U); + reg_snap[3] = REG32(0xE000E108U); + + REG32(0xE000E010U) &= 0x00010004U; + REG32(0xE000E180U) = 0XB7FFEF19U; + REG32(0xE000E184U) = 0XFFFFFBFFU; + REG32(0xE000E188U) = 0xFFFFFFFFU; + + /* select WFI or WFE command to enter deepsleep mode */ + if(WFI_CMD == deepsleepmodecmd) { + __WFI(); + } else { + __SEV(); + __WFE(); + __WFE(); + } + + REG32(0xE000E010U) = reg_snap[0]; + REG32(0xE000E100U) = reg_snap[1]; + REG32(0xE000E104U) = reg_snap[2]; + REG32(0xE000E108U) = reg_snap[3]; + + /* reset sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/*! + \brief pmu work at standby mode + \param[in] standbymodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_standbymode(uint8_t standbymodecmd) +{ + /* set sleepdeep bit of Cortex-M4 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* set stbmod bit */ + PMU_CTL |= PMU_CTL_STBMOD; + + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + + /* select WFI or WFE command to enter standby mode */ + if(WFI_CMD == standbymodecmd) { + __WFI(); + } else { + __WFE(); + __WFE(); + } +} + +/*! + \brief enable wakeup pin + \param[in] wakeup_pin: + one or more parameters can be selected which are shown as below: + \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) + \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) + \arg PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5) + \arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5) + \arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15) + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_enable(uint32_t wakeup_pin) +{ + PMU_CS |= wakeup_pin; +} + +/*! + \brief disable wakeup pin + \param[in] wakeup_pin: + one or more parameters can be selected which are shown as below: + \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) + \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) + \arg PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5) + \arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5) + \arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15) + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_disable(uint32_t wakeup_pin) +{ + PMU_CS &= ~(wakeup_pin); +} + +/*! + \brief enable backup domain write + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_enable(void) +{ + PMU_CTL |= PMU_CTL_BKPWEN; +} + +/*! + \brief disable backup domain write + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_disable(void) +{ + PMU_CTL &= ~PMU_CTL_BKPWEN; +} + +/*! + \brief get flag state + \param[in] flag: + only one parameter can be selected which is shown as below: + \arg PMU_FLAG_WAKEUP: wakeup flag + \arg PMU_FLAG_STANDBY: standby flag + \arg PMU_FLAG_LVD: lvd flag + \arg PMU_FLAG_LDOVSR: LDO voltage select ready flag + \arg PMU_FLAG_HDR: high-driver ready flag + \arg PMU_FLAG_HDSR: high-driver switch ready flag + \arg PMU_FLAG_LDR: low-driver mode ready flag + \param[out] none + \retval FlagStatus SET or RESET +*/ +FlagStatus pmu_flag_get(uint32_t flag) +{ + FlagStatus ret_status = RESET; + + if(PMU_CS & flag) { + ret_status = SET; + } + + return ret_status; +} + +/*! + \brief clear flag bit + \param[in] flag: + one or more parameters can be selected which are shown as below: + \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag + \arg PMU_FLAG_RESET_STANDBY: reset standby flag + \param[out] none + \retval none +*/ +void pmu_flag_clear(uint32_t flag) +{ + if(RESET != (flag & PMU_FLAG_RESET_WAKEUP)) { + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + } + if(RESET != (flag & PMU_FLAG_RESET_STANDBY)) { + /* reset standby flag */ + PMU_CTL |= PMU_CTL_STBRST; + } +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_rcu.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_rcu.c new file mode 100644 index 000000000..e3bfd52e3 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_rcu.c @@ -0,0 +1,1213 @@ +/*! + \file gd32f3x0_rcu.c + \brief RCU driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_rcu.h" + +/* define clock source */ +#define SEL_IRC8M ((uint32_t)0x00000000U) +#define SEL_HXTAL ((uint32_t)0x00000001U) +#define SEL_PLL ((uint32_t)0x00000002U) + +/* define startup timeout count */ +#define OSC_STARTUP_TIMEOUT ((uint32_t)0x000FFFFFU) +#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x03FFFFFFU) + +/*! + \brief deinitialize the RCU + \param[in] none + \param[out] none + \retval none +*/ +void rcu_deinit(void) +{ + /* enable IRC8M */ + RCU_CTL0 |= RCU_CTL0_IRC8MEN; + while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)) { + } + + RCU_CFG0 &= ~RCU_CFG0_SCS; + + /* reset CTL register */ + RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS); + RCU_CTL1 &= ~RCU_CTL1_IRC28MEN; + + /* reset RCU */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | \ + RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); +#if (defined(GD32F350)) + RCU_CFG0 &= ~(RCU_CFG0_USBFSPSC); + RCU_CFG2 &= ~(RCU_CFG2_CECSEL | RCU_CFG2_USBFSPSC2); +#endif /* GD32F350 */ + + RCU_CFG1 &= ~(RCU_CFG1_PREDV | RCU_CFG1_PLLMF5 | RCU_CFG1_PLLPRESEL); + RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL); + RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; + RCU_CFG2 &= ~RCU_CFG2_ADCPSC2; + RCU_ADDCTL &= ~RCU_ADDCTL_IRC48MEN; + RCU_INT = 0x00000000U; + RCU_ADDINT = 0x00000000U; +} + +/*! + \brief enable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x=A,B,C,D,F): GPIO ports clock + \arg RCU_DMA: DMA clock + \arg RCU_CRC: CRC clock + \arg RCU_TSI: TSI clock + \arg RCU_CFGCMP: CFGCMP clock + \arg RCU_ADC: ADC clock + \arg RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock (RCU_TIMER5 only for GD32F350) + \arg RCU_SPIx (x=0,1): SPI clock + \arg RCU_USARTx (x=0,1): USART clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_I2Cx (x=0,1): I2C clock + \arg RCU_USBFS: USBFS clock (only for GD32F350) + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock (only for GD32F350) + \arg RCU_CEC: CEC clock (only for GD32F350) + \arg RCU_CTC: CTC clock + \arg RCU_RTC: RTC clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_enable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x=A,B,C,D,F): GPIO ports clock + \arg RCU_DMA: DMA clock + \arg RCU_CRC: CRC clock + \arg RCU_TSI: TSI clock + \arg RCU_CFGCMP: CFGCMP clock + \arg RCU_ADC: ADC clock + \arg RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock (RCU_TIMER5 only for GD32F350) + \arg RCU_SPIx (x=0,1): SPI clock + \arg RCU_USARTx (x=0,1): USART clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_I2Cx (x=0,1): I2C clock + \arg RCU_USBFS: USBFS clock (only for GD32F350) + \arg RCU_PMU: PMU clock + \arg RCU_DAC: DAC clock (only for GD32F350) + \arg RCU_CEC: CEC clock (only for GD32F350) + \arg RCU_CTC: CTC clock + \arg RCU_RTC: RTC clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_disable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief enable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} +/*! + \brief reset the peripherals + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x=A,B,C,D,F): reset GPIO ports + \arg RCU_TSIRST: reset TSI + \arg RCU_CFGCMPRST: reset CFGCMP + \arg RCU_ADCRST: reset ADC + \arg RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER (RCU_TIMER5 only for GD32F350) + \arg RCU_SPIxRST (x=0,1): reset SPI + \arg RCU_USARTxRST (x=0,1): reset USART + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_I2CxRST (x=0,1): reset I2C + \arg RCU_USBFSRST: reset USBFS (only for GD32F350) + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC (only for GD32F350) + \arg RCU_CECRST: reset CEC (only for GD32F350) + \arg RCU_CTCRST: reset CTC + \param[out] none + \retval none +*/ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief disable reset the peripheral + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x=A,B,C,D,F): reset GPIO ports + \arg RCU_TSIRST: reset TSI + \arg RCU_CFGCMPRST: reset CFGCMP + \arg RCU_ADCRST: reset ADC + \arg RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER (RCU_TIMER5 only for GD32F350) + \arg RCU_SPIxRST (x=0,1,2): reset SPI + \arg RCU_USARTxRST (x=0,1): reset USART + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_I2CxRST (x=0,1,2): reset I2C + \arg RCU_USBFSRST: reset USBFS (only for GD32F350) + \arg RCU_PMURST: reset PMU + \arg RCU_DACRST: reset DAC (only for GD32F350) + \arg RCU_CECRST: reset CEC (only for GD32F350) + \arg RCU_CTCRST: reset CTC + \param[out] none + \retval none +*/ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief reset the BKP + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_enable(void) +{ + RCU_BDCTL |= RCU_BDCTL_BKPRST; +} + +/*! + \brief disable the BKP reset + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_disable(void) +{ + RCU_BDCTL &= ~RCU_BDCTL_BKPRST; +} + +/*! + \brief configure the system clock source + \param[in] ck_sys: system clock source select + only one parameter can be selected which is shown as below: + \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source + \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source + \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source + \param[out] none + \retval none +*/ +void rcu_system_clock_source_config(uint32_t ck_sys) +{ + uint32_t cksys_source = 0U; + cksys_source = RCU_CFG0; + /* reset the SCS bits and set according to ck_sys */ + cksys_source &= ~RCU_CFG0_SCS; + RCU_CFG0 = (ck_sys | cksys_source); +} + +/*! + \brief get the system clock source + \param[in] none + \param[out] none + \retval which clock is selected as CK_SYS source + only one parameter can be selected which is shown as below: + \arg RCU_SCSS_IRC8M: select CK_IRC8M as the CK_SYS source + \arg RCU_SCSS_HXTAL: select CK_HXTAL as the CK_SYS source + \arg RCU_SCSS_PLL: select CK_PLL as the CK_SYS source +*/ +uint32_t rcu_system_clock_source_get(void) +{ + return (RCU_CFG0 & RCU_CFG0_SCSS); +} + +/*! + \brief configure the AHB clock prescaler selection + \param[in] ck_ahb: AHB clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 + \param[out] none + \retval none +*/ +void rcu_ahb_clock_config(uint32_t ck_ahb) +{ + uint32_t ahbpsc = 0U; + ahbpsc = RCU_CFG0; + /* reset the AHBPSC bits and set according to ck_ahb */ + ahbpsc &= ~RCU_CFG0_AHBPSC; + RCU_CFG0 = (ck_ahb | ahbpsc); +} + +/*! + \brief configure the APB1 clock prescaler selection + \param[in] ck_apb1: APB1 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 + \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 + \param[out] none + \retval none +*/ +void rcu_apb1_clock_config(uint32_t ck_apb1) +{ + uint32_t apb1psc = 0U; + apb1psc = RCU_CFG0; + /* reset the APB1PSC and set according to ck_apb1 */ + apb1psc &= ~RCU_CFG0_APB1PSC; + RCU_CFG0 = (ck_apb1 | apb1psc); +} + +/*! + \brief configure the APB2 clock prescaler selection + \param[in] ck_apb2: APB2 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 + \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 + \param[out] none + \retval none +*/ +void rcu_apb2_clock_config(uint32_t ck_apb2) +{ + uint32_t apb2psc = 0U; + apb2psc = RCU_CFG0; + /* reset the APB2PSC and set according to ck_apb2 */ + apb2psc &= ~RCU_CFG0_APB2PSC; + RCU_CFG0 = (ck_apb2 | apb2psc); +} + +/*! + \brief configure the ADC clock prescaler selection + \param[in] ck_adc: ADC clock prescaler selection, refer to rcu_adc_clock_enum + only one parameter can be selected which is shown as below: + \arg RCU_ADCCK_IRC28M_DIV2: select CK_IRC28M/2 as CK_ADC + \arg RCU_ADCCK_IRC28M: select CK_IRC28M as CK_ADC + \arg RCU_ADCCK_APB2_DIV2: select CK_APB2/2 as CK_ADC + \arg RCU_ADCCK_AHB_DIV3: select CK_AHB/3 as CK_ADC + \arg RCU_ADCCK_APB2_DIV4: select CK_APB2/4 as CK_ADC + \arg RCU_ADCCK_AHB_DIV5: select CK_AHB/5 as CK_ADC + \arg RCU_ADCCK_APB2_DIV6: select CK_APB2/6 as CK_ADC + \arg RCU_ADCCK_AHB_DIV7: select CK_AHB/7 as CK_ADC + \arg RCU_ADCCK_APB2_DIV8: select CK_APB2/8 as CK_ADC + \arg RCU_ADCCK_AHB_DIV9: select CK_AHB/9 as CK_ADC + \param[out] none + \retval none +*/ +void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc) +{ + /* reset the ADCPSC, ADCSEL, IRC28MDIV bits */ + RCU_CFG0 &= ~RCU_CFG0_ADCPSC; + RCU_CFG2 &= ~(RCU_CFG2_ADCSEL | RCU_CFG2_IRC28MDIV | RCU_CFG2_ADCPSC2); + + /* set the ADC clock according to ck_adc */ + switch(ck_adc) { + case RCU_ADCCK_IRC28M_DIV2: + RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; + RCU_CFG2 &= ~RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_IRC28M: + RCU_CFG2 |= RCU_CFG2_IRC28MDIV; + RCU_CFG2 &= ~RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_APB2_DIV2: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_AHB_DIV3: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2; + RCU_CFG2 |= RCU_CFG2_ADCPSC2; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_APB2_DIV4: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_AHB_DIV5: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4; + RCU_CFG2 |= RCU_CFG2_ADCPSC2; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_APB2_DIV6: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_AHB_DIV7: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6; + RCU_CFG2 |= RCU_CFG2_ADCPSC2; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_APB2_DIV8: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_AHB_DIV9: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8; + RCU_CFG2 |= RCU_CFG2_ADCPSC2; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + default: + break; + } +} + +/*! + \brief configure the USBFS clock prescaler selection + \param[in] ck_usbfs: USBFS clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_USBFS_CKPLL_DIV1_5: select CK_PLL/1.5 as CK_USBFS + \arg RCU_USBFS_CKPLL_DIV1: select CK_PLL as CK_USBFS + \arg RCU_USBFS_CKPLL_DIV2_5: select CK_PLL/2.5 as CK_USBFS + \arg RCU_USBFS_CKPLL_DIV2: select CK_PLL/2 as CK_USBFS + \arg RCU_USBFS_CKPLL_DIV3: select CK_PLL/3 as CK_USBFS + \arg RCU_USBFS_CKPLL_DIV3_5: select CK_PLL/3.5 as CK_USBFS + \param[out] none + \retval none +*/ +void rcu_usbfs_clock_config(uint32_t ck_usbfs) +{ + /* reset the USBFSPSC bits and set according to ck_usbfs */ + RCU_CFG0 &= ~RCU_CFG0_USBFSPSC; + RCU_CFG2 &= ~RCU_CFG2_USBFSPSC2; + + RCU_CFG0 |= (ck_usbfs & (~RCU_CFG2_USBFSPSC2)); + RCU_CFG2 |= (ck_usbfs & RCU_CFG2_USBFSPSC2); +} + +/*! + \brief configure the CK_OUT clock source and divider + \param[in] ckout_src: CK_OUT clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CKOUTSRC_NONE: no clock selected + \arg RCU_CKOUTSRC_IRC28M: IRC28M selected + \arg RCU_CKOUTSRC_IRC40K: IRC40K selected + \arg RCU_CKOUTSRC_LXTAL: LXTAL selected + \arg RCU_CKOUTSRC_CKSYS: CKSYS selected + \arg RCU_CKOUTSRC_IRC8M: IRC8M selected + \arg RCU_CKOUTSRC_HXTAL: HXTAL selected + \arg RCU_CKOUTSRC_CKPLL_DIV1: CK_PLL selected + \arg RCU_CKOUTSRC_CKPLL_DIV2: CK_PLL/2 selected + \param[in] ckout_div: CK_OUT divider + \arg RCU_CKOUT_DIVx(x=1,2,4,8,16,32,64,128): CK_OUT is divided by x + \param[out] none + \retval none +*/ +void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div) +{ + uint32_t ckout = 0U; + ckout = RCU_CFG0; + /* reset the CKOUTSEL, CKOUTDIV and PLLDV bits and set according to ckout_src and ckout_div */ + ckout &= ~(RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); + RCU_CFG0 = (ckout | ckout_src | ckout_div); +} + +/*! + \brief configure the PLL clock source preselection + \param[in] pll_presel: PLL clock source preselection + only one parameter can be selected which is shown as below: + \arg RCU_PLLPRESEL_IRC48M: select IRC48M as PLL preselection clock + \arg RCU_PLLPRESEL_HXTAL: select HXTAL as PLL preselection clock + \param[out] none + \retval none +*/ +void rcu_pll_preselection_config(uint32_t pll_presel) +{ + RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL); + RCU_CFG1 |= pll_presel; +} + +/*! + \brief configure the PLL clock source selection and PLL multiply factor + \param[in] pll_src: PLL clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_PLLSRC_IRC8M_DIV2: select CK_IRC8M/2 as PLL source clock + \arg RCU_PLLSRC_HXTAL_IRC48M: select HXTAL or IRC48M as PLL source clock + \param[in] pll_mul: PLL multiply factor + only one parameter can be selected which is shown as below: + \arg RCU_PLL_MULx(x=2..64): PLL source clock * x + \param[out] none + \retval none +*/ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) +{ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4); + RCU_CFG1 &= ~(RCU_CFG1_PLLMF5); + RCU_CFG0 |= (pll_src | (pll_mul & (~RCU_CFG1_PLLMF5))); + RCU_CFG1 |= (pll_mul & RCU_CFG1_PLLMF5); +} + +/*! + \brief configure the USART clock source selection + \param[in] ck_usart: USART clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_USART0SRC_CKAPB2: CK_USART0 select CK_APB2 + \arg RCU_USART0SRC_CKSYS: CK_USART0 select CK_SYS + \arg RCU_USART0SRC_LXTAL: CK_USART0 select CK_LXTAL + \arg RCU_USART0SRC_IRC8M: CK_USART0 select CK_IRC8M + \param[out] none + \retval none +*/ +void rcu_usart_clock_config(uint32_t ck_usart) +{ + /* reset the USART0SEL bits and set according to ck_usart */ + RCU_CFG2 &= ~RCU_CFG2_USART0SEL; + RCU_CFG2 |= ck_usart; +} + +/*! + \brief configure the CEC clock source selection + \param[in] ck_cec: CEC clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CECSRC_IRC8M_DIV244: CK_CEC select CK_IRC8M/244 + \arg RCU_CECSRC_LXTAL: CK_CEC select CK_LXTAL + \param[out] none + \retval none +*/ +void rcu_cec_clock_config(uint32_t ck_cec) +{ + /* reset the CECSEL bit and set according to ck_cec */ + RCU_CFG2 &= ~RCU_CFG2_CECSEL; + RCU_CFG2 |= ck_cec; +} + +/*! + \brief configure the RTC clock source selection + \param[in] rtc_clock_source: RTC clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_RTCSRC_NONE: no clock selected + \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock + \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock + \arg RCU_RTCSRC_HXTAL_DIV32: CK_HXTAL/32 selected as RTC source clock + \param[out] none + \retval none +*/ +void rcu_rtc_clock_config(uint32_t rtc_clock_source) +{ + /* reset the RTCSRC bits and set according to rtc_clock_source */ + RCU_BDCTL &= ~RCU_BDCTL_RTCSRC; + RCU_BDCTL |= rtc_clock_source; +} + +/*! + \brief configure the CK48M clock source selection + \param[in] ck48m_clock_source: CK48M clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CK48MSRC_PLL48M: CK_PLL48M selected as CK48M source clock + \arg RCU_CK48MSRC_IRC48M: CK_IRC48M selected as CK48M source clock + \param[out] none + \retval none +*/ +void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) +{ + uint32_t reg; + + reg = RCU_ADDCTL; + /* reset the CK48MSEL bit and set according to ck48m_clock_source */ + reg &= ~RCU_ADDCTL_CK48MSEL; + RCU_ADDCTL = (reg | ck48m_clock_source); +} + +/*! + \brief configure the HXTAL divider used as input of PLL + \param[in] hxtal_prediv: HXTAL divider used as input of PLL + only one parameter can be selected which is shown as below: + \arg RCU_PLL_PREDVx(x=1..16): HXTAL or IRC48M divided x used as input of PLL + \param[out] none + \retval none +*/ +void rcu_hxtal_prediv_config(uint32_t hxtal_prediv) +{ + uint32_t prediv = 0U; + prediv = RCU_CFG1; + /* reset the HXTALPREDV bits and set according to hxtal_prediv */ + prediv &= ~RCU_CFG1_PREDV; + RCU_CFG1 = (prediv | hxtal_prediv); +} + +/*! + \brief configure the LXTAL drive capability + \param[in] lxtal_dricap: drive capability of LXTAL + only one parameter can be selected which is shown as below: + \arg RCU_LXTAL_LOWDRI: lower driving capability + \arg RCU_LXTAL_MED_LOWDRI: medium low driving capability + \arg RCU_LXTAL_MED_HIGHDRI: medium high driving capability + \arg RCU_LXTAL_HIGHDRI: higher driving capability + \param[out] none + \retval none +*/ +void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) +{ + /* reset the LXTALDRI bits and set according to lxtal_dricap */ + RCU_BDCTL &= ~RCU_BDCTL_LXTALDRI; + RCU_BDCTL |= lxtal_dricap; +} + +/*! + \brief get the clock stabilization and periphral reset flags + \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag + \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag + \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag + \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag + \arg RCU_FLAG_PLLSTB: PLL stabilization flag + \arg RCU_FLAG_IRC28MSTB: IRC28M stabilization flag + \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag + \arg RCU_FLAG_V12RST: V12 domain power reset flag + \arg RCU_FLAG_OBLRST: option byte loader reset flag + \arg RCU_FLAG_EPRST: external pin reset flag + \arg RCU_FLAG_PORRST: power reset flag + \arg RCU_FLAG_SWRST: software reset flag + \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag + \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag + \arg RCU_FLAG_LPRST: low-power reset flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_flag_get(rcu_flag_enum flag) +{ + if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the reset flag + \param[in] none + \param[out] none + \retval none +*/ +void rcu_all_reset_flag_clear(void) +{ + RCU_RSTSCK |= RCU_RSTSCK_RSTFC; +} + +/*! + \brief get the clock stabilization interrupt and ckm flags + \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag + \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag + \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC28MSTB: IRC28M stabilization interrupt flag + \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag + \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) +{ + if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the interrupt flags + \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear + \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear + \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC28MSTB_CLR: IRC28M stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear + \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear + \param[out] none + \retval none +*/ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) +{ + RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); +} + +/*! + \brief enable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_IRC28MSTB: IRC28M stabilization interrupt enable + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable + \param[out] none + \retval none +*/ +void rcu_interrupt_enable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); +} + + +/*! + \brief disable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt disable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt disable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt disable + \arg RCU_INT_IRC28MSTB: IRC28M stabilization interrupt disable + \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt disable + \param[out] none + \retval none +*/ +void rcu_interrupt_disable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); +} + +/*! + \brief wait until oscillator stabilization flags is SET + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \arg RCU_IRC8M: IRC8M + \arg RCU_IRC28M: IRC28M + \arg RCU_IRC48M: IRC48M + \arg RCU_IRC40K: IRC40K + \arg RCU_PLL_CK: PLL + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) +{ + uint32_t stb_cnt = 0U; + ErrStatus reval = ERROR; + FlagStatus osci_stat = RESET; + switch(osci) { + case RCU_HXTAL: + /* wait until HXTAL is stabilization and osci_stat is not more than timeout */ + while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); + stb_cnt++; + } + if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) { + reval = SUCCESS; + } + break; + /* wait LXTAL stable */ + case RCU_LXTAL: + while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) { + reval = SUCCESS; + } + break; + + /* wait IRC8M stable */ + case RCU_IRC8M: + while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)) { + reval = SUCCESS; + } + break; + + /* wait IRC28M stable */ + case RCU_IRC28M: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC28MSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC28MSTB)) { + reval = SUCCESS; + } + break; + /* wait IRC48M stable */ + case RCU_IRC48M: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)) { + reval = SUCCESS; + } + break; + + /* wait IRC40K stable */ + case RCU_IRC40K: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)) { + reval = SUCCESS; + } + break; + + /* wait PLL stable */ + case RCU_PLL_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); + stb_cnt++; + } + + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)) { + reval = SUCCESS; + } + break; + + default: + break; + } + /* return value */ + return reval; +} + +/*! + \brief turn on the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \arg RCU_IRC8M: IRC8M + \arg RCU_IRC28M: IRC28M + \arg RCU_IRC48M: IRC48M + \arg RCU_IRC40K: IRC40K + \arg RCU_PLL_CK: PLL + \param[out] none + \retval none +*/ +void rcu_osci_on(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief turn off the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \arg RCU_IRC8M: IRC8M + \arg RCU_IRC28M: IRC28M + \arg RCU_IRC48M: IRC48M + \arg RCU_IRC40K: IRC40K + \arg RCU_PLL_CK: PLL + \param[out] none + \retval none +*/ +void rcu_osci_off(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) +{ + uint32_t reg; + switch(osci) { + case RCU_HXTAL: + /* HXTALEN must be reset before enable the oscillator bypass mode */ + reg = RCU_CTL0; + RCU_CTL0 &= ~RCU_CTL0_HXTALEN; + RCU_CTL0 = (reg | RCU_CTL0_HXTALBPS); + break; + case RCU_LXTAL: + /* LXTALEN must be reset before enable the oscillator bypass mode */ + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); + break; + case RCU_IRC8M: + case RCU_IRC28M: + case RCU_IRC48M: + case RCU_IRC40K: + case RCU_PLL_CK: + break; + default: + break; + } +} + +/*! + \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) +{ + uint32_t reg; + switch(osci) { + case RCU_HXTAL: + /* HXTALEN must be reset before disable the oscillator bypass mode */ + reg = RCU_CTL0; + RCU_CTL0 &= ~RCU_CTL0_HXTALEN; + RCU_CTL0 = (reg & (~RCU_CTL0_HXTALBPS)); + break; + case RCU_LXTAL: + /* LXTALEN must be reset before disable the oscillator bypass mode */ + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg & (~RCU_BDCTL_LXTALBPS)); + break; + case RCU_IRC8M: + case RCU_IRC28M: + case RCU_IRC48M: + case RCU_IRC40K: + case RCU_PLL_CK: + break; + default: + break; + } +} + +/*! + \brief enable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_enable(void) +{ + RCU_CTL0 |= RCU_CTL0_CKMEN; +} + +/*! + \brief disable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_disable(void) +{ + RCU_CTL0 &= ~RCU_CTL0_CKMEN; +} + +/*! + \brief set the IRC8M adjust value + \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F + \param[out] none + \retval none +*/ +void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval) +{ + uint32_t adjust = 0U; + adjust = RCU_CTL0; + /* reset the IRC8MADJ bits and set according to irc8m_adjval */ + adjust &= ~RCU_CTL0_IRC8MADJ; + RCU_CTL0 = (adjust | (((uint32_t)irc8m_adjval) << 3)); +} + +/*! + \brief set the IRC28M adjust value + \param[in] irc28m_adjval: IRC28M adjust value, must be between 0 and 0x1F + \param[out] none + \retval none +*/ +void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval) +{ + uint32_t adjust = 0U; + adjust = RCU_CTL1; + /* reset the IRC28MADJ bits and set according to irc28m_adjval */ + adjust &= ~RCU_CTL1_IRC28MADJ; + RCU_CTL1 = (adjust | (((uint32_t)irc28m_adjval) << 3)); +} + +/*! + \brief unlock the voltage key + \param[in] none + \param[out] none + \retval none +*/ +void rcu_voltage_key_unlock(void) +{ + /* reset the KEY bits and set 0x1A2B3C4D */ + RCU_VKEY &= ~RCU_VKEY_KEY; + RCU_VKEY |= RCU_VKEY_UNLOCK; +} + +/*! + \brief set voltage in deep sleep mode + \param[in] dsvol: deep sleep mode voltage + only one parameter can be selected which is shown as below: + \arg RCU_DEEPSLEEP_V_0: the core voltage is default value + \arg RCU_DEEPSLEEP_V_1: the core voltage is (default value-0.1)V (customers are not recommended to use it) + \arg RCU_DEEPSLEEP_V_2: the core voltage is (default value-0.2)V (customers are not recommended to use it) + \arg RCU_DEEPSLEEP_V_3: the core voltage is (default value-0.3)V (customers are not recommended to use it) + \param[out] none + \retval none +*/ +void rcu_deepsleep_voltage_set(uint32_t dsvol) +{ + /* reset the DSLPVS bits and set according to dsvol */ + RCU_DSV &= ~RCU_DSV_DSLPVS; + RCU_DSV |= dsvol; +} + +/*! + \brief get the system clock, bus and peripheral clock frequency + \param[in] clock: the clock frequency which to get + only one parameter can be selected which is shown as below: + \arg CK_SYS: system clock frequency + \arg CK_AHB: AHB clock frequency + \arg CK_APB1: APB1 clock frequency + \arg CK_APB2: APB2 clock frequency + \arg CK_ADC: ADC clock frequency + \arg CK_CEC: CEC clock frequency + \arg CK_USART: USART clock frequency + \param[out] none + \retval clock frequency of system, AHB, APB1, APB2, ADC, CEC or USRAT +*/ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) +{ + uint32_t sws = 0U, adcps = 0U, adcps2 = 0U, ck_freq = 0U; + uint32_t cksys_freq = 0U, ahb_freq = 0U, apb1_freq = 0U, apb2_freq = 0U; + uint32_t adc_freq = 0U, cec_freq = 0U, usart_freq = 0U; + uint32_t pllmf = 0U, pllmf4 = 0U, pllmf5 = 0U, pllsel = 0U, pllpresel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U; + /* exponent of AHB, APB1 and APB2 clock divider */ + const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + const uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + + sws = GET_BITS(RCU_CFG0, 2, 3); + switch(sws) { + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + cksys_freq = IRC8M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + cksys_freq = HXTAL_VALUE; + break; + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* get the value of PLLMF[3:0] */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + pllmf4 = GET_BITS(RCU_CFG0, 27, 27); + pllmf5 = GET_BITS(RCU_CFG1, 31, 31); + /* high 16 bits */ + /* high 16 bits */ + if((0U == pllmf4) && (0U == pllmf5)) { + pllmf += 2U; + } + if((1U == pllmf4) && (0U == pllmf5)) { + pllmf += 17U; + } + if((0U == pllmf4) && (1U == pllmf5)) { + pllmf += 33U; + } + if((1U == pllmf4) && (1U == pllmf5)) { + pllmf += 49U; + } + + /* PLL clock source selection, HXTAL or IRC48M or IRC8M/2 */ + pllsel = GET_BITS(RCU_CFG0, 16, 16); + pllpresel = GET_BITS(RCU_CFG1, 30, 30); + if(0U != pllsel) { + prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U); + if(0U == pllpresel) { + cksys_freq = (HXTAL_VALUE / prediv) * pllmf; + } else { + cksys_freq = (IRC48M_VALUE / prediv) * pllmf; + } + } else { + cksys_freq = (IRC8M_VALUE >> 1) * pllmf; + } + break; + /* IRC8M is selected as CK_SYS */ + default: + cksys_freq = IRC8M_VALUE; + break; + } + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + ahb_freq = cksys_freq >> clk_exp; + + /* calculate APB1 clock frequency */ + idx = GET_BITS(RCU_CFG0, 8, 10); + clk_exp = apb1_exp[idx]; + apb1_freq = ahb_freq >> clk_exp; + + /* calculate APB2 clock frequency */ + idx = GET_BITS(RCU_CFG0, 11, 13); + clk_exp = apb2_exp[idx]; + apb2_freq = ahb_freq >> clk_exp; + + /* return the clocks frequency */ + switch(clock) { + case CK_SYS: + ck_freq = cksys_freq; + break; + case CK_AHB: + ck_freq = ahb_freq; + break; + case CK_APB1: + ck_freq = apb1_freq; + break; + case CK_APB2: + ck_freq = apb2_freq; + break; + case CK_ADC: + /* calculate ADC clock frequency */ + if(RCU_ADCSRC_AHB_APB2DIV != (RCU_CFG2 & RCU_CFG2_ADCSEL)) { + if(RCU_ADC_IRC28M_DIV1 != (RCU_CFG2 & RCU_CFG2_IRC28MDIV)) { + adc_freq = IRC28M_VALUE >> 1; + } else { + adc_freq = IRC28M_VALUE; + } + } else { + /* ADC clock select CK_APB2 divided by 2/4/6/8 or CK_AHB divided by 3/5/7/9 */ + adcps = GET_BITS(RCU_CFG0, 14, 15); + adcps2 = GET_BITS(RCU_CFG2, 31, 31); + switch(adcps) { + case 0: + if(0U == adcps2) { + adc_freq = apb2_freq / 2U; + } else { + adc_freq = ahb_freq / 3U; + } + break; + case 1: + if(0U == adcps2) { + adc_freq = apb2_freq / 4U; + } else { + adc_freq = ahb_freq / 5U; + } + break; + case 2: + if(0U == adcps2) { + adc_freq = apb2_freq / 6U; + } else { + adc_freq = ahb_freq / 7U; + } + break; + case 3: + if(0U == adcps2) { + adc_freq = apb2_freq / 8U; + } else { + adc_freq = ahb_freq / 9U; + } + break; + default: + break; + } + } + ck_freq = adc_freq; + break; + case CK_CEC: + /* calculate CEC clock frequency */ + if(RCU_CECSRC_LXTAL != (RCU_CFG2 & RCU_CFG2_CECSEL)) { + cec_freq = IRC8M_VALUE / 244U; + } else { + cec_freq = LXTAL_VALUE; + } + ck_freq = cec_freq; + break; + case CK_USART: + /* calculate USART clock frequency */ + if(RCU_USART0SRC_CKAPB2 == (RCU_CFG2 & RCU_CFG2_USART0SEL)) { + usart_freq = apb2_freq; + } else if(RCU_USART0SRC_CKSYS == (RCU_CFG2 & RCU_CFG2_USART0SEL)) { + usart_freq = cksys_freq; + } else if(RCU_USART0SRC_LXTAL == (RCU_CFG2 & RCU_CFG2_USART0SEL)) { + usart_freq = LXTAL_VALUE; + } else if(RCU_USART0SRC_IRC8M == (RCU_CFG2 & RCU_CFG2_USART0SEL)) { + usart_freq = IRC8M_VALUE; + } else { + } + ck_freq = usart_freq; + break; + default: + break; + } + return ck_freq; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_rtc.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_rtc.c new file mode 100644 index 000000000..58d6cc9a0 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_rtc.c @@ -0,0 +1,965 @@ +/*! + \file gd32f3x0_rtc.c + \brief RTC driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_rtc.h" + +/*! + \brief reset most of the RTC registers + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_deinit(void) +{ + ErrStatus error_status = ERROR; + + /* RTC_TAMP register is not under write protection */ + RTC_TAMP = RTC_REGISTER_RESET; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* reset RTC_CTL register, this can be done without the init mode */ + RTC_CTL &= RTC_REGISTER_RESET; + + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition. + in order to read calendar from shadow register, not the real registers being reset */ + RTC_TIME = RTC_REGISTER_RESET; + RTC_DATE = RTC_DATE_RESET; + + RTC_PSC = RTC_PSC_RESET; + + /* reset RTC_STAT register, also exit init mode. + at the same time, RTC_STAT_SOPF bit is reset, as the condition to reset RTC_SHIFTCTL register later */ + RTC_STAT = RTC_STAT_RESET; + + /* to write RTC_ALRM0SS register, ALRM0EN bit in RTC_CTL register should be reset as the condition */ + RTC_ALRM0TD = RTC_REGISTER_RESET; + RTC_ALRM0SS = RTC_REGISTER_RESET; + + /* reset RTC_SHIFTCTL and RTC_HRFC register, this can be done without the init mode */ + RTC_SHIFTCTL = RTC_REGISTER_RESET; + RTC_HRFC = RTC_REGISTER_RESET; + + error_status = rtc_register_sync_wait(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief initialize RTC registers + \param[in] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains + parameters for initialization of the rtc peripheral + members of the structure and the member values are shown as below: + rtc_year: 0x0 - 0x99(BCD format) + rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, + RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC + rtc_date: 0x1 - 0x31(BCD format) + rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY + RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY + rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose + rtc_minute: 0x0 - 0x59(BCD format) + rtc_second: 0x0 - 0x59(BCD format) + rtc_factor_asyn: 0x0 - 0x7F + rtc_factor_syn: 0x0 - 0x7FFF + rtc_am_pm: RTC_AM, RTC_PM + rtc_display_format: RTC_24HOUR, RTC_12HOUR + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_init(rtc_parameter_struct *rtc_initpara_struct) +{ + ErrStatus error_status = ERROR; + uint32_t reg_time = 0x00U, reg_date = 0x00U; + + reg_date = (DATE_YR(rtc_initpara_struct->rtc_year) | \ + DATE_DOW(rtc_initpara_struct->rtc_day_of_week) | \ + DATE_MON(rtc_initpara_struct->rtc_month) | \ + DATE_DAY(rtc_initpara_struct->rtc_date)); + + reg_time = (rtc_initpara_struct->rtc_am_pm | \ + TIME_HR(rtc_initpara_struct->rtc_hour) | \ + TIME_MN(rtc_initpara_struct->rtc_minute) | \ + TIME_SC(rtc_initpara_struct->rtc_second)); + + /* 1st: disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* 2nd: enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->rtc_factor_asyn) | \ + PSC_FACTOR_S(rtc_initpara_struct->rtc_factor_syn)); + + RTC_TIME = (uint32_t)reg_time; + RTC_DATE = (uint32_t)reg_date; + + RTC_CTL &= (uint32_t)(~RTC_CTL_CS); + RTC_CTL |= rtc_initpara_struct->rtc_display_format; + + /* 3rd: exit init mode */ + rtc_init_mode_exit(); + + /* 4th: wait the RSYNF flag to set */ + error_status = rtc_register_sync_wait(); + } + + /* 5th: enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enter RTC init mode + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_init_mode_enter(void) +{ + uint32_t time_index = RTC_INITM_TIMEOUT; + uint32_t flag_status = RESET; + ErrStatus error_status = ERROR; + + /* check whether it has been in init mode */ + if(RESET == (RTC_STAT & RTC_STAT_INITF)) { + RTC_STAT |= RTC_STAT_INITM; + + /* wait until the INITF flag to be set */ + do { + flag_status = RTC_STAT & RTC_STAT_INITF; + } while((--time_index > 0x00U) && (RESET == flag_status)); + + if(RESET != flag_status) { + error_status = SUCCESS; + } + } else { + error_status = SUCCESS; + } + return error_status; +} + +/*! + \brief exit RTC init mode + \param[in] none + \param[out] none + \retval none +*/ +void rtc_init_mode_exit(void) +{ + RTC_STAT &= (uint32_t)(~RTC_STAT_INITM); +} + +/*! + \brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow + registers are updated + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_register_sync_wait(void) +{ + volatile uint32_t time_index = RTC_RSYNF_TIMEOUT; + uint32_t flag_status = RESET; + ErrStatus error_status = ERROR; + + if(RESET == (RTC_CTL & RTC_CTL_BPSHAD)) { + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* firstly clear RSYNF flag */ + RTC_STAT &= (uint32_t)(~RTC_STAT_RSYNF); + + /* wait until RSYNF flag to be set */ + do { + flag_status = RTC_STAT & RTC_STAT_RSYNF; + } while((--time_index > 0x00U) && (RESET == flag_status)); + + if(RESET != flag_status) { + error_status = SUCCESS; + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + } else { + error_status = SUCCESS; + } + + return error_status; +} + +/*! + \brief get current time and date + \param[in] none + \param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains + parameters for initialization of the rtc peripheral + members of the structure and the member values are shown as below: + rtc_year: 0x0 - 0x99(BCD format) + rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, + RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC + rtc_date: 0x1 - 0x31(BCD format) + rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY + RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY + rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose + rtc_minute: 0x0 - 0x59(BCD format) + rtc_second: 0x0 - 0x59(BCD format) + rtc_factor_asyn: 0x0 - 0x7F + rtc_factor_syn: 0x0 - 0x7FFF + rtc_am_pm: RTC_AM, RTC_PM + rtc_display_format: RTC_24HOUR, RTC_12HOUR + \retval none +*/ +void rtc_current_time_get(rtc_parameter_struct *rtc_initpara_struct) +{ + uint32_t temp_tr = 0x00U, temp_dr = 0x00U, temp_pscr = 0x00U, temp_ctlr = 0x00U; + + temp_tr = (uint32_t)RTC_TIME; + temp_dr = (uint32_t)RTC_DATE; + temp_pscr = (uint32_t)RTC_PSC; + temp_ctlr = (uint32_t)RTC_CTL; + + /* get current time and construct rtc_parameter_struct structure */ + rtc_initpara_struct->rtc_year = (uint8_t)GET_DATE_YR(temp_dr); + rtc_initpara_struct->rtc_month = (uint8_t)GET_DATE_MON(temp_dr); + rtc_initpara_struct->rtc_date = (uint8_t)GET_DATE_DAY(temp_dr); + rtc_initpara_struct->rtc_day_of_week = (uint8_t)GET_DATE_DOW(temp_dr); + rtc_initpara_struct->rtc_hour = (uint8_t)GET_TIME_HR(temp_tr); + rtc_initpara_struct->rtc_minute = (uint8_t)GET_TIME_MN(temp_tr); + rtc_initpara_struct->rtc_second = (uint8_t)GET_TIME_SC(temp_tr); + rtc_initpara_struct->rtc_factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr); + rtc_initpara_struct->rtc_factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr); + rtc_initpara_struct->rtc_am_pm = (uint32_t)(temp_pscr & RTC_TIME_PM); + rtc_initpara_struct->rtc_display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS); +} + +/*! + \brief get current subsecond value + \param[in] none + \param[out] none + \retval current subsecond value +*/ +uint32_t rtc_subsecond_get(void) +{ + uint32_t reg = 0x00U; + /* if BPSHAD bit is reset, reading RTC_SS will lock RTC_TIME and RTC_DATE automatically */ + reg = (uint32_t)RTC_SS; + /* read RTC_DATE to unlock the 3 shadow registers */ + (void)(RTC_DATE); + + return reg; +} + +/*! + \brief configure RTC alarm + \param[in] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains + parameters for RTC alarm configuration + members of the structure and the member values are shown as below: + rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK + RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK + rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED + rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set + 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, + RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set + rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format + rtc_alarm_minute: 0x0 - 0x59(BCD format) + rtc_alarm_second: 0x0 - 0x59(BCD format) + rtc_am_pm: RTC_AM, RTC_PM + \param[out] none + \retval none +*/ +void rtc_alarm_config(rtc_alarm_struct *rtc_alarm_time) +{ + uint32_t reg_alrm0td = 0x00U; + + reg_alrm0td = (rtc_alarm_time->rtc_alarm_mask | \ + rtc_alarm_time->rtc_weekday_or_date | \ + rtc_alarm_time->rtc_am_pm | \ + ALRM0TD_DAY(rtc_alarm_time->rtc_alarm_day) | \ + ALRM0TD_HR(rtc_alarm_time->rtc_alarm_hour) | \ + ALRM0TD_MN(rtc_alarm_time->rtc_alarm_minute) | \ + ALRM0TD_SC(rtc_alarm_time->rtc_alarm_second)); + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_ALRM0TD = (uint32_t)reg_alrm0td; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief configure subsecond of RTC alarm + \param[in] mask_subsecond: alarm subsecond mask + only one parameter can be selected which is shown as below: + \arg RTC_MASKSSC_0_14: mask alarm subsecond configuration + \arg RTC_MASKSSC_1_14: mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared + \arg RTC_MASKSSC_2_14: mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared + \arg RTC_MASKSSC_3_14: mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared + \arg RTC_MASKSSC_4_14: mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared + \arg RTC_MASKSSC_5_14: mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared + \arg RTC_MASKSSC_6_14: mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared + \arg RTC_MASKSSC_7_14: mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared + \arg RTC_MASKSSC_8_14: mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared + \arg RTC_MASKSSC_9_14: mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared + \arg RTC_MASKSSC_10_14: mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared + \arg RTC_MASKSSC_11_14: mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared + \arg RTC_MASKSSC_12_14: mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared + \arg RTC_MASKSSC_13_14: mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared + \arg RTC_MASKSSC_14: mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared + \arg RTC_MASKSSC_NONE: mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared + \param[in] subsecond: alarm subsecond value(0x000 - 0x7FFF) + \param[out] none + \retval none +*/ +void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_ALRM0SS = mask_subsecond | subsecond; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief get RTC alarm + \param[in] none + \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains + parameters for RTC alarm configuration + members of the structure and the member values are shown as below: + rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK + RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK + rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED + rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set + 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, + RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set + rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format + rtc_alarm_minute: 0x0 - 0x59(BCD format) + rtc_alarm_second: 0x0 - 0x59(BCD format) + rtc_am_pm: RTC_AM, RTC_PM + \retval none +*/ +void rtc_alarm_get(rtc_alarm_struct *rtc_alarm_time) +{ + uint32_t reg_alrm0td = 0x00U; + + /* get the value of RTC_ALRM0TD register */ + reg_alrm0td = RTC_ALRM0TD; + + /* get alarm parameters and construct the rtc_alarm_struct structure */ + rtc_alarm_time->rtc_alarm_mask = reg_alrm0td & RTC_ALARM_ALL_MASK; + rtc_alarm_time->rtc_am_pm = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_PM); + rtc_alarm_time->rtc_weekday_or_date = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_DOWS); + rtc_alarm_time->rtc_alarm_day = (uint8_t)GET_ALRM0TD_DAY(reg_alrm0td); + rtc_alarm_time->rtc_alarm_hour = (uint8_t)GET_ALRM0TD_HR(reg_alrm0td); + rtc_alarm_time->rtc_alarm_minute = (uint8_t)GET_ALRM0TD_MN(reg_alrm0td); + rtc_alarm_time->rtc_alarm_second = (uint8_t)GET_ALRM0TD_SC(reg_alrm0td); +} + +/*! + \brief get RTC alarm subsecond + \param[in] none + \param[out] none + \retval RTC alarm subsecond value +*/ +uint32_t rtc_alarm_subsecond_get(void) +{ + return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC)); +} + +/*! + \brief enable RTC alarm + \param[in] none + \param[out] none + \retval none +*/ +void rtc_alarm_enable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL |= RTC_CTL_ALRM0EN; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disable RTC alarm + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_alarm_disable(void) +{ + volatile uint32_t time_index = RTC_ALRM0WF_TIMEOUT; + ErrStatus error_status = ERROR; + uint32_t flag_status = RESET; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* clear the state of alarm */ + RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN); + + /* wait until ALRM0WF flag to be set after the alarm is disabled */ + do { + flag_status = RTC_STAT & RTC_STAT_ALRM0WF; + } while((--time_index > 0x00U) && (RESET == flag_status)); + + if(RESET != flag_status) { + error_status = SUCCESS; + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enable RTC time-stamp + \param[in] edge: specify which edge to detect of time-stamp + only one parameter can be selected which is shown as below: + \arg RTC_TIMESTAMP_RISING_EDGE: rising edge is valid event edge for timestamp event + \arg RTC_TIMESTAMP_FALLING_EDGE: falling edge is valid event edge for timestamp event + \param[out] none + \retval none +*/ +void rtc_timestamp_enable(uint32_t edge) +{ + uint32_t reg_ctl = 0x00U; + + /* clear the bits to be configured in RTC_CTL */ + reg_ctl = (uint32_t)(RTC_CTL & (uint32_t)(~(RTC_CTL_TSEG | RTC_CTL_TSEN))); + + /* new configuration */ + reg_ctl |= (uint32_t)(edge | RTC_CTL_TSEN); + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL = (uint32_t)reg_ctl; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disable RTC time-stamp + \param[in] none + \param[out] none + \retval none +*/ +void rtc_timestamp_disable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* clear the TSEN bit */ + RTC_CTL &= (uint32_t)(~ RTC_CTL_TSEN); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief get RTC timestamp time and date + \param[in] none + \param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains + parameters for RTC time-stamp configuration + members of the structure and the member values are shown as below: + rtc_timestamp_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, + RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC + rtc_timestamp_date: 0x1 - 0x31(BCD format) + rtc_timestamp_day: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, + RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set + rtc_timestamp_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format + rtc_timestamp_minute: 0x0 - 0x59(BCD format) + rtc_timestamp_second: 0x0 - 0x59(BCD format) + rtc_am_pm: RTC_AM, RTC_PM + \retval none +*/ +void rtc_timestamp_get(rtc_timestamp_struct *rtc_timestamp) +{ + uint32_t temp_tts = 0x00U, temp_dts = 0x00U; + + /* get the value of time_stamp registers */ + temp_tts = (uint32_t)RTC_TTS; + temp_dts = (uint32_t)RTC_DTS; + + /* get timestamp time and construct the rtc_timestamp_struct structure */ + rtc_timestamp->rtc_am_pm = (uint32_t)(temp_tts & RTC_TTS_PM); + rtc_timestamp->rtc_timestamp_month = (uint8_t)GET_DTS_MON(temp_dts); + rtc_timestamp->rtc_timestamp_date = (uint8_t)GET_DTS_DAY(temp_dts); + rtc_timestamp->rtc_timestamp_day = (uint8_t)GET_DTS_DOW(temp_dts); + rtc_timestamp->rtc_timestamp_hour = (uint8_t)GET_TTS_HR(temp_tts); + rtc_timestamp->rtc_timestamp_minute = (uint8_t)GET_TTS_MN(temp_tts); + rtc_timestamp->rtc_timestamp_second = (uint8_t)GET_TTS_SC(temp_tts); +} + +/*! + \brief get RTC time-stamp subsecond + \param[in] none + \param[out] none + \retval RTC time-stamp subsecond value +*/ +uint32_t rtc_timestamp_subsecond_get(void) +{ + return ((uint32_t)RTC_SSTS); +} + +/*! + \brief enable RTC tamper + \param[in] rtc_tamper: pointer to a rtc_tamper_struct structure which contains + parameters for RTC tamper configuration + members of the structure and the member values are shown as below: + rtc_tamper_source: RTC_TAMPER0, RTC_TAMPER1 + rtc_tamper_trigger: RTC_TAMPER_TRIGGER_EDGE_RISING, RTC_TAMPER_TRIGGER_EDGE_FALLING + RTC_TAMPER_TRIGGER_LEVEL_LOW, RTC_TAMPER_TRIGGER_LEVEL_HIGH + rtc_tamper_filter: RTC_FLT_EDGE, RTC_FLT_2S, RTC_FLT_4S, RTC_FLT_8S + rtc_tamper_sample_frequency: RTC_FREQ_DIV32768, RTC_FREQ_DIV16384, RTC_FREQ_DIV8192, + RTC_FREQ_DIV4096, RTC_FREQ_DIV2048, RTC_FREQ_DIV1024, + RTC_FREQ_DIV512, RTC_FREQ_DIV256 + rtc_tamper_precharge_enable: DISABLE, ENABLE + rtc_tamper_precharge_time: RTC_PRCH_1C, RTC_PRCH_2C, RTC_PRCH_4C, RTC_PRCH_8C + rtc_tamper_with_timestamp: DISABLE, ENABLE + \param[out] none + \retval none +*/ +void rtc_tamper_enable(rtc_tamper_struct *rtc_tamper) +{ + /* disable tamper */ + RTC_TAMP &= (uint32_t)~(rtc_tamper->rtc_tamper_source); + + /* tamper filter must be used when the tamper source is voltage level detection */ + RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT; + + /* the tamper source is voltage level detection */ + if(rtc_tamper->rtc_tamper_filter != RTC_FLT_EDGE) { + RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT); + + /* check if the tamper pin need precharge, if need, then configure the precharge time */ + if(DISABLE == rtc_tamper->rtc_tamper_precharge_enable) { + RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; + } else { + RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_precharge_time); + } + + RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_sample_frequency); + RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_filter); + } + + RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS; + + if(DISABLE != rtc_tamper->rtc_tamper_with_timestamp) { + /* the tamper event also cause a time-stamp event */ + RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS; + } + + /* configure the tamper trigger */ + RTC_TAMP &= ((uint32_t)~((rtc_tamper->rtc_tamper_source) << RTC_TAMPER_TRIGGER_POS)); + if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->rtc_tamper_trigger) { + RTC_TAMP |= (uint32_t)((rtc_tamper->rtc_tamper_source) << RTC_TAMPER_TRIGGER_POS); + } + /* enable tamper */ + RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_source); +} + +/*! + \brief disable RTC tamper + \param[in] source: specify which tamper source to be disabled + only one parameter can be selected which is shown as below: + \arg RTC_TAMPER0 + \arg RTC_TAMPER1 + \param[out] none + \retval none +*/ +void rtc_tamper_disable(uint32_t source) +{ + /* disable tamper */ + RTC_TAMP &= (uint32_t)~source; +} + +/*! + \brief enable specified RTC interrupt + \param[in] interrupt: specify which interrupt source to be enabled + only one parameter can be selected which is shown as below: + \arg RTC_INT_TIMESTAMP: timestamp interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_TAMP: tamp interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_enable(uint32_t interrupt) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enable the interrupts in RTC_CTL register */ + RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPIE); + /* enable the interrupts in RTC_TAMP register */ + RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPIE); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disble specified RTC interrupt + \param[in] interrupt: specify which interrupt source to be disabled + only one parameter can be selected which is shown as below: + \arg RTC_INT_TIMESTAMP: timestamp interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_TAMP: tamp interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_disable(uint32_t interrupt) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* disable the interrupts in RTC_CTL register */ + RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~RTC_TAMP_TPIE); + /* disable the interrupts in RTC_TAMP register */ + RTC_TAMP &= (uint32_t)~(interrupt & RTC_TAMP_TPIE); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief check specified flag + \param[in] flag: specify which flag to check + only one parameter can be selected which is shown as below: + \arg RTC_FLAG_RECALIBRATION: recalibration pending flag + \arg RTC_FLAG_TAMP1: tamper 1 event flag + \arg RTC_FLAG_TAMP0: tamper 0 event flag + \arg RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag + \arg RTC_FLAG_TIMESTAMP: time-stamp event flag + \arg RTC_FLAG_ALARM0: alarm event flag + \arg RTC_FLAG_INIT: init mode event flag + \arg RTC_FLAG_RSYN: time and date registers synchronized event flag + \arg RTC_FLAG_YCM: year parameter configured event flag + \arg RTC_FLAG_SHIFT: shift operation pending flag + \arg RTC_FLAG_ALARM0_WRITTEN: alarm writen available flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rtc_flag_get(uint32_t flag) +{ + FlagStatus flag_state = RESET; + + if(RESET != (RTC_STAT & flag)) { + flag_state = SET; + } + return flag_state; +} + +/*! + \brief clear specified flag + \param[in] flag: specify which flag to clear + \arg RTC_FLAG_TAMP1: tamper 1 event flag + \arg RTC_FLAG_TAMP0: tamper 0 event flag + \arg RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag + \arg RTC_FLAG_TIMESTAMP: time-stamp event flag + \arg RTC_FLAG_ALARM0: alarm event flag + \arg RTC_FLAG_RSYN: time and date registers synchronized event flag + \param[out] none + \retval none +*/ +void rtc_flag_clear(uint32_t flag) +{ + RTC_STAT &= (uint32_t)(~flag); +} + +/*! + \brief configure rtc alternate output source + \param[in] source: specify signal to output + only one parameter can be selected which is shown as below: + \arg RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC + is the default value, output 512Hz signal + \arg RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC + is the default value, output 1Hz signal + \arg RTC_ALARM_HIGH: when the alarm flag is set, the output pin is high + \arg RTC_ALARM_LOW: when the Alarm flag is set, the output pin is low + \param[in] mode: specify the output pin (PC13) mode when output alarm signal + only one parameter can be selected which is shown as below: + \arg RTC_ALARM_OUTPUT_OD: open drain mode + \arg RTC_ALARM_OUTPUT_PP: push pull mode + \param[out] none + \retval none +*/ +void rtc_alter_output_config(uint32_t source, uint32_t mode) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL &= (uint32_t)~(RTC_CTL_COEN | RTC_CTL_OS | RTC_CTL_OPOL | RTC_CTL_COS); + + RTC_CTL |= (uint32_t)(source); + + /* alarm output */ + if(RESET != (source & RTC_OS_ENABLE)) { + RTC_TAMP &= (uint32_t)~(RTC_TAMP_PC13VAL); + RTC_TAMP |= (uint32_t)(mode); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + + +/*! + \brief configure RTC calibration register + \param[in] window: select calibration window + only one parameter can be selected which is shown as below: + \arg RTC_CALIBRATION_WINDOW_32S: 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz + \arg RTC_CALIBRATION_WINDOW_16S: 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz + \arg RTC_CALIBRATION_WINDOW_8S: 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz + \param[in] plus: add RTC clock or not + only one parameter can be selected which is shown as below: + \arg RTC_CALIBRATION_PLUS_SET: add one RTC clock every 2048 rtc clock + \arg RTC_CALIBRATION_PLUS_RESET: no effect + \param[in] minus: the RTC clock to minus during the calibration window(0x0 - 0x1FF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus) +{ + uint32_t time_index = RTC_HRFC_TIMEOUT; + ErrStatus error_status = ERROR; + uint32_t flag_status = RESET; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* check if a calibration operation is ongoing */ + do { + flag_status = RTC_STAT & RTC_STAT_SCPF; + } while((--time_index > 0x00U) && (RESET != flag_status)); + + if(RESET == flag_status) { + RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus)); + error_status = SUCCESS; + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief ajust the daylight saving time by adding or substracting one hour from the current time + \param[in] operation: hour ajustment operation + only one parameter can be selected which is shown as below: + \arg RTC_CTL_A1H: add one hour + \arg RTC_CTL_S1H: substract one hour + \param[out] none + \retval none +*/ +void rtc_hour_adjust(uint32_t operation) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL |= (uint32_t)(operation); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief ajust RTC second or subsecond value of current time + \param[in] add: add 1s to current time or not + only one parameter can be selected which is shown as below: + \arg RTC_SHIFT_ADD1S_RESET: no effect + \arg RTC_SHIFT_ADD1S_SET: add 1s to current time + \param[in] minus: number of subsecond to minus from current time(0x0 - 0x7FFF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus) +{ + uint32_t time_index = RTC_SHIFTCTL_TIMEOUT; + ErrStatus error_status = ERROR; + uint32_t flag_status = RESET; + uint32_t temp = 0U; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* check if a shift operation is ongoing */ + do { + flag_status = RTC_STAT & RTC_STAT_SOPF; + } while((--time_index > 0x00U) && (RESET != flag_status)); + + temp = RTC_CTL & RTC_CTL_REFEN; + /* check if the function of reference clock detection is disabled */ + if((RESET == flag_status) && (RESET == temp)) { + RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus)); + error_status = rtc_register_sync_wait(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enable RTC bypass shadow registers function + \param[in] none + \param[out] none + \retval none +*/ +void rtc_bypass_shadow_enable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL |= (uint8_t)RTC_CTL_BPSHAD; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disable RTC bypass shadow registers function + \param[in] none + \param[out] none + \retval none +*/ +void rtc_bypass_shadow_disable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL &= (uint8_t)~RTC_CTL_BPSHAD; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief enable RTC reference clock detection function + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_refclock_detection_enable(void) +{ + ErrStatus error_status = ERROR; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + RTC_CTL |= (uint32_t)RTC_CTL_REFEN; + /* exit init mode */ + rtc_init_mode_exit(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief disable RTC reference clock detection function + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_refclock_detection_disable(void) +{ + ErrStatus error_status = ERROR; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + RTC_CTL &= (uint32_t)~RTC_CTL_REFEN; + /* exit init mode */ + rtc_init_mode_exit(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_spi.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_spi.c new file mode 100644 index 000000000..cd1318c6f --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_spi.c @@ -0,0 +1,794 @@ +/*! + \file gd32f3x0_spi.c + \brief SPI driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_spi.h" + +#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ +#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ + +#define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /*!< default value of SPI_I2SPSC register */ + +/*! + \brief reset SPI and I2S + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_i2s_deinit(uint32_t spi_periph) +{ + switch(spi_periph) { + case SPI0: + /* reset SPI0 and I2S0 */ + rcu_periph_reset_enable(RCU_SPI0RST); + rcu_periph_reset_disable(RCU_SPI0RST); + break; + case SPI1: + /* reset SPI1 */ + rcu_periph_reset_enable(RCU_SPI1RST); + rcu_periph_reset_disable(RCU_SPI1RST); + break; + default : + break; + } +} + +/*! + \brief initialize the parameters of SPI struct with the default values + \param[in] spi_struct: SPI parameter stuct + \param[out] none + \retval none +*/ +void spi_struct_para_init(spi_parameter_struct *spi_struct) +{ + /* set the SPI struct with the default values */ + spi_struct->device_mode = SPI_SLAVE; + spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_struct->frame_size = SPI_FRAMESIZE_8BIT; + spi_struct->nss = SPI_NSS_HARD; + spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + spi_struct->prescale = SPI_PSC_2; +} + +/*! + \brief initialize SPI parameter + \param[in] spi_periph: SPIx(x=0,1) + \param[in] spi_struct: SPI parameter initialization stuct members of the structure + and the member values are shown as below: + device_mode: SPI_MASTER, SPI_SLAVE + trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, + SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT + frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT + nss: SPI_NSS_SOFT, SPI_NSS_HARD + endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB + clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE + SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE + prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) + \param[out] none + \retval none +*/ +void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct) +{ + uint32_t reg = 0U; + reg = SPI_CTL0(spi_periph); + reg &= SPI_INIT_MASK; + + /* select SPI as master or slave */ + reg |= spi_struct->device_mode; + /* select SPI transfer mode */ + reg |= spi_struct->trans_mode; + /* select SPI frame size */ + reg |= spi_struct->frame_size; + /* select SPI NSS use hardware or software */ + reg |= spi_struct->nss; + /* select SPI LSB or MSB */ + reg |= spi_struct->endian; + /* select SPI polarity and phase */ + reg |= spi_struct->clock_polarity_phase; + /* select SPI prescale to adjust transmit speed */ + reg |= spi_struct->prescale; + + /* write to SPI_CTL0 register */ + SPI_CTL0(spi_periph) = (uint32_t)reg; + + /* select SPI mode */ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); +} + +/*! + \brief enable SPI + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_enable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; +} + +/*! + \brief disable SPI + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_disable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); +} + + +#if (defined(GD32F350) || defined(GD32F310)) +/*! + \brief initialize I2S parameter + \param[in] spi_periph: SPI0 + \param[in] mode: I2S operation mode + only one parameter can be selected which is shown as below: + \arg I2S_MODE_SLAVETX: I2S slave transmit mode + \arg I2S_MODE_SLAVERX: I2S slave receive mode + \arg I2S_MODE_MASTERTX: I2S master transmit mode + \arg I2S_MODE_MASTERRX: I2S master receive mode + \param[in] standard: I2S standard + only one parameter can be selected which is shown as below: + \arg I2S_STD_PHILLIPS: I2S phillips standard + \arg I2S_STD_MSB: I2S MSB standard + \arg I2S_STD_LSB: I2S LSB standard + \arg I2S_STD_PCMSHORT: I2S PCM short standard + \arg I2S_STD_PCMLONG: I2S PCM long standard + \param[in] ckpl: I2S idle state clock polarity + only one parameter can be selected which is shown as below: + \arg I2S_CKPL_LOW: I2S clock polarity low level + \arg I2S_CKPL_HIGH: I2S clock polarity high level + \param[out] none + \retval none +*/ +void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) +{ + uint32_t reg = 0U; + reg = SPI_I2SCTL(spi_periph); + reg &= I2S_INIT_MASK; + + /* enable I2S mode */ + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + /* select I2S mode */ + reg |= (uint32_t)mode; + /* select I2S standard */ + reg |= (uint32_t)standard; + /* select I2S polarity */ + reg |= (uint32_t)ckpl; + + /* write to SPI_I2SCTL register */ + SPI_I2SCTL(spi_periph) = (uint32_t)reg; +} + +/*! + \brief configure I2S prescaler + \param[in] spi_periph: SPI0 + \param[in] audiosample: I2S audio sample rate + only one parameter can be selected which is shown as below: + \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz + \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz + \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz + \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz + \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz + \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz + \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz + \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz + \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz + \param[in] frameformat: I2S data length and channel length + only one parameter can be selected which is shown as below: + \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit + \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit + \param[in] mckout: I2S master clock output + only one parameter can be selected which is shown as below: + \arg I2S_MCKOUT_ENABLE: I2S master clock output enable + \arg I2S_MCKOUT_DISABLE: I2S master clock output disable + \param[out] none + \retval none +*/ +void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) +{ + uint32_t i2sdiv = 2U, i2sof = 0U; + uint32_t clks = 0U; + uint32_t i2sclock = 0U; + + /* deinit SPI_I2SPSC register */ + SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; + + /* get system clock */ + i2sclock = rcu_clock_freq_get(CK_SYS); + + /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ + if(I2S_MCKOUT_ENABLE == mckout) { + clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); + } else { + if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat) { + clks = (uint32_t)(((i2sclock / 32U) * 10U) / audiosample); + } else { + clks = (uint32_t)(((i2sclock / 64U) * 10U) / audiosample); + } + } + + /* remove the floating point */ + clks = (clks + 5U) / 10U; + i2sof = (clks & 0x00000001U); + i2sdiv = ((clks - i2sof) / 2U); + i2sof = (i2sof << 8U); + + /* set the default values */ + if((i2sdiv < 2U) || (i2sdiv > 255U)) { + i2sdiv = 2U; + i2sof = 0U; + } + + /* configure SPI_I2SPSC */ + SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout); + + /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); + /* configure data frame format */ + SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; +} + +/*! + \brief enable I2S + \param[in] spi_periph: SPI0 + \param[out] none + \retval none +*/ +void i2s_enable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; +} + +/*! + \brief disable I2S + \param[in] spi_periph: SPI0 + \param[out] none + \retval none +*/ +void i2s_disable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); +} + +#endif /* GD32F350 and GD32F310 */ + +/*! + \brief enable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nss_output_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; +} + +/*! + \brief disable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nss_output_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); +} + +/*! + \brief pull NSS pin high in software mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nss_internal_high(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; +} + +/*! + \brief pull NSS pin low in software mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nss_internal_low(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); +} + +/*! + \brief enable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1) + \param[in] dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA + \arg SPI_DMA_RECEIVE: SPI receive data using DMA + \param[out] none + \retval none +*/ +void spi_dma_enable(uint32_t spi_periph, uint8_t dma) +{ + if(SPI_DMA_TRANSMIT == dma) { + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; + } else { + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; + } +} + +/*! + \brief disable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1) + \param[in] dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA + \arg SPI_DMA_RECEIVE: SPI receive data using DMA + \param[out] none + \retval none +*/ +void spi_dma_disable(uint32_t spi_periph, uint8_t dma) +{ + if(SPI_DMA_TRANSMIT == dma) { + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); + } else { + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); + } +} + +/*! + \brief configure SPI/I2S data frame format + \param[in] spi_periph: SPIx(x=0,1) + \param[in] frame_format: SPI frame size + only one parameter can be selected which is shown as below: + \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits + \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits + \param[out] none + \retval none +*/ +void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) +{ + /* clear SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); + /* confige SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) |= (uint32_t)frame_format; +} + +/*! + \brief SPI transmit data + \param[in] spi_periph: SPIx(x=0,1) + \param[in] data: 16-bit data + \param[out] none + \retval none +*/ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) +{ + SPI_DATA(spi_periph) = (uint32_t)data; +} + +/*! + \brief SPI receive data + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval 16-bit data +*/ +uint16_t spi_i2s_data_receive(uint32_t spi_periph) +{ + return ((uint16_t)SPI_DATA(spi_periph)); +} + +/*! + \brief configure SPI bidirectional transfer direction + \param[in] spi_periph: SPIx(x=0,1) + \param[in] transfer_direction: SPI transfer direction + only one parameter can be selected which is shown as below: + \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode + \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode + \param[out] none + \retval none +*/ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) +{ + if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction) { + /* set the transmit only mode */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; + } else { + /* set the receive only mode */ + SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; + } +} + +/*! + \brief set CRC polynomial + \param[in] spi_periph: SPIx(x=0,1) + \param[in] crc_poly: CRC polynomial value + \param[out] none + \retval none +*/ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) +{ + /* enable SPI CRC */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; + /* set SPI CRC polynomial */ + SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; +} + +/*! + \brief get SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval 16-bit CRC polynomial +*/ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph) +{ + return ((uint16_t)SPI_CRCPOLY(spi_periph)); +} + +/*! + \brief turn on CRC function + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_crc_on(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; +} + +/*! + \brief turn off CRC function + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_crc_off(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); +} + +/*! + \brief SPI next data is CRC value + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_crc_next(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; +} + +/*! + \brief get SPI CRC send value or receive value + \param[in] spi_periph: SPIx(x=0,1) + \param[in] crc: SPI crc value + \arg SPI_CRC_TX: get transmit crc value + \arg SPI_CRC_RX: get receive crc value + \param[out] none + \retval 16-bit CRC value +*/ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc) +{ + if(SPI_CRC_TX == crc) { + return ((uint16_t)(SPI_TCRC(spi_periph))); + } else { + return ((uint16_t)(SPI_RCRC(spi_periph))); + } +} + +/*! + \brief enable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_ti_mode_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; +} + +/*! + \brief disable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_ti_mode_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); +} + +/*! + \brief enable SPI NSS pulse mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nssp_mode_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; +} + +/*! + \brief disable SPI NSS pulse mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nssp_mode_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); +} + +/*! + \brief enable quad wire SPI + \param[in] spi_periph: SPI1 + \param[out] none + \retval none +*/ +void qspi_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; +} + +/*! + \brief disable quad wire SPI + \param[in] spi_periph: SPI1 + \param[out] none + \retval none +*/ +void qspi_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); +} + +/*! + \brief enable quad wire SPI write + \param[in] spi_periph: SPI1 + \param[out] none + \retval none +*/ +void qspi_write_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); +} + +/*! + \brief enable quad wire SPI read + \param[in] spi_periph: SPI1 + \param[out] none + \retval none +*/ +void qspi_read_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; +} + +/*! + \brief enable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPI1 + \param[out] none + \retval none +*/ +void qspi_io23_output_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; +} + +/*! + \brief disable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPI1 + \param[out] none + \retval none +*/ +void qspi_io23_output_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); +} + +/*! + \brief enable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1) + \param[in] interrupt: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) +{ + switch(interrupt) { + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; + break; + default: + break; + } +} + +/*! + \brief disable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1) + \param[in] interrupt: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) +{ + switch(interrupt) { + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_TBE: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_RBNE: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); + break; + /* SPI/I2S error */ + case SPI_I2S_INT_ERR: + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); + break; + default : + break; + } +} + +/*! + \brief get SPI and I2S interrupt flag status + \param[in] spi_periph: SPIx(x=0,1) + \param[in] interrupt: SPI/I2S interrupt flag status + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag + \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag + \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag + \arg SPI_INT_FLAG_CONFERR: config error interrupt flag + \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag + \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag + \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) +{ + uint32_t reg1 = SPI_STAT(spi_periph); + uint32_t reg2 = SPI_CTL1(spi_periph); + + switch(interrupt) { + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_FLAG_TBE: + reg1 = reg1 & SPI_STAT_TBE; + reg2 = reg2 & SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_FLAG_RBNE: + reg1 = reg1 & SPI_STAT_RBNE; + reg2 = reg2 & SPI_CTL1_RBNEIE; + break; + /* SPI/I2S overrun interrupt */ + case SPI_I2S_INT_FLAG_RXORERR: + reg1 = reg1 & SPI_STAT_RXORERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI config error interrupt */ + case SPI_INT_FLAG_CONFERR: + reg1 = reg1 & SPI_STAT_CONFERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI CRC error interrupt */ + case SPI_INT_FLAG_CRCERR: + reg1 = reg1 & SPI_STAT_CRCERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* I2S underrun error interrupt */ + case I2S_INT_FLAG_TXURERR: + reg1 = reg1 & SPI_STAT_TXURERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI/I2S format error interrupt */ + case SPI_I2S_INT_FLAG_FERR: + reg1 = reg1 & SPI_STAT_FERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + default : + break; + } + /*get SPI/I2S interrupt flag status */ + if((0U != reg1) && (0U != reg2)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get SPI and I2S flag status + \param[in] spi_periph: SPIx(x=0,1) + \param[in] flag: SPI/I2S flag status + one or more parameters can be selected which are shown as below: + \arg SPI_FLAG_TBE: transmit buffer empty flag + \arg SPI_FLAG_RBNE: receive buffer not empty flag + \arg SPI_FLAG_TRANS: transmit on-going flag + \arg SPI_FLAG_RXORERR: receive overrun error flag + \arg SPI_FLAG_CONFERR: mode config error flag + \arg SPI_FLAG_CRCERR: CRC error flag + \arg SPI_FLAG_FERR: format error interrupt flag + \arg I2S_FLAG_TBE: transmit buffer empty flag + \arg I2S_FLAG_RBNE: receive buffer not empty flag + \arg I2S_FLAG_TRANS: transmit on-going flag + \arg I2S_FLAG_RXORERR: overrun error flag + \arg I2S_FLAG_TXURERR: underrun error flag + \arg I2S_FLAG_CH: channel side flag + \arg I2S_FLAG_FERR: format error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) +{ + if(RESET != (SPI_STAT(spi_periph) & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear SPI CRC error flag status + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_crc_error_clear(uint32_t spi_periph) +{ + SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_syscfg.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_syscfg.c new file mode 100644 index 000000000..b9cc44574 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_syscfg.c @@ -0,0 +1,229 @@ +/*! + \file gd32f3x0_syscfg.c + \brief SYSCFG driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_syscfg.h" + +/*! + \brief reset the SYSCFG registers + \param[in] none + \param[out] none + \retval none +*/ +void syscfg_deinit(void) +{ + rcu_periph_reset_enable(RCU_CFGCMPRST); + rcu_periph_reset_disable(RCU_CFGCMPRST); +} + +/*! + \brief enable the DMA channels remapping + \param[in] syscfg_dma_remap: specify the DMA channels to remap + one or more parameters can be selected which is shown as below: + \arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0) + \arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2) + \arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2) + \arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1) + \arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1 + \param[out] none + \retval none +*/ +void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap) +{ + SYSCFG_CFG0 |= syscfg_dma_remap; +} + +/*! + \brief disable the DMA channels remapping + \param[in] syscfg_dma_remap: specify the DMA channels to remap + one or more parameters can be selected which is shown as below: + \arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0) + \arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2) + \arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2) + \arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1) + \arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1 + \param[out] none + \retval none +*/ +void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap) +{ + SYSCFG_CFG0 &= ~syscfg_dma_remap; +} + +/*! + \brief enable PB9 high current capability + \param[in] none + \param[out] none + \retval none +*/ +void syscfg_high_current_enable(void) +{ + SYSCFG_CFG0 |= SYSCFG_HIGH_CURRENT_ENABLE; +} + +/*! + \brief disable PB9 high current capability + \param[in] none + \param[out] none + \retval none +*/ +void syscfg_high_current_disable(void) +{ + SYSCFG_CFG0 &= SYSCFG_HIGH_CURRENT_DISABLE; +} + +/*! + \brief configure the GPIO pin as EXTI Line + \param[in] exti_port: specify the GPIO port used in EXTI + only one parameter can be selected which is shown as below: + \arg EXTI_SOURCE_GPIOx(x = A,B,C,D,F): EXTI GPIO port + \param[in] exti_pin: specify the EXTI line + only one parameter can be selected which is shown as below: + \arg EXTI_SOURCE_PINx(x = 0..15): EXTI GPIO pin + \param[out] none + \retval none +*/ +void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin) +{ + uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin))); + uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin)); + + switch(exti_pin / EXTI_SS_JSTEP) { + case EXTISS0: + /* clear EXTI source line(0..3) */ + SYSCFG_EXTISS0 &= clear_exti_mask; + /* configure EXTI soure line(0..3) */ + SYSCFG_EXTISS0 |= config_exti_mask; + break; + case EXTISS1: + /* clear EXTI soure line(4..7) */ + SYSCFG_EXTISS1 &= clear_exti_mask; + /* configure EXTI soure line(4..7) */ + SYSCFG_EXTISS1 |= config_exti_mask; + break; + case EXTISS2: + /* clear EXTI soure line(8..11) */ + SYSCFG_EXTISS2 &= clear_exti_mask; + /* configure EXTI soure line(8..11) */ + SYSCFG_EXTISS2 |= config_exti_mask; + break; + case EXTISS3: + /* clear EXTI soure line(12..15) */ + SYSCFG_EXTISS3 &= clear_exti_mask; + /* configure EXTI soure line(12..15) */ + SYSCFG_EXTISS3 |= config_exti_mask; + break; + default: + break; + } +} + +/*! + \brief connect TIMER0/14/15/16 break input to the selected parameter + \param[in] syscfg_lock: Specify the parameter to be connected + one or more parameters can be selected which is shown as below: + \arg SYSCFG_LOCK_LOCKUP: Cortex-M4 lockup output connected to the break input + \arg SYSCFG_LOCK_SRAM_PARITY_ERROR: SRAM_PARITY check error connected to the break input + \arg SYSCFG_LOCK_LVD: LVD interrupt connected to the break input + \param[out] none + \retval none +*/ +void syscfg_lock_config(uint32_t syscfg_lock) +{ + SYSCFG_CFG2 |= syscfg_lock; +} + +/*! + \brief check if the specified flag in SYSCFG_CFG2 is set or not. + \param[in] syscfg_flag: specify the flag in SYSCFG_CFG2 to check. + \arg SYSCFG_SRAM_PCEF: SRAM parity check error flag. + \param[out] none + \retval the syscfg_flag state returned (SET or RESET). + */ +FlagStatus syscfg_flag_get(uint32_t syscfg_flag) +{ + if((SYSCFG_CFG2 & syscfg_flag) != (uint32_t)RESET) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the flag in SYSCFG_CFG2 by writing 1. + \param[in] syscfg_flag: Specify the flag in SYSCFG_CFG2 to clear. + \arg SYSCFG_SRAM_PCEF: SRAM parity check error flag. + \param[out] none + \retval none +*/ +void syscfg_flag_clear(uint32_t syscfg_flag) +{ + SYSCFG_CFG2 |= (uint32_t) syscfg_flag; +} + +/*! + \brief configure the I/O compensation cell + \param[in] syscfg_compensation: specifies the I/O compensation cell mode + only one parameter can be selected which is shown as below: + \arg SYSCFG_COMPENSATION_ENABLE: I/O compensation cell is enabled + \arg SYSCFG_COMPENSATION_DISABLE: I/O compensation cell is disabled + \param[out] none + \retval none +*/ +void syscfg_compensation_config(uint32_t syscfg_compensation) +{ + uint32_t reg; + + reg = SYSCFG_CPSCTL; + /* reset the SYSCFG_CPSCTL_CPS_EN bit and set according to syscfg_compensation */ + reg &= ~SYSCFG_CPSCTL_CPS_EN; + SYSCFG_CPSCTL = (reg | syscfg_compensation); +} + +/*! + \brief check if the I/O compensation cell ready flag is set or not + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET + */ +FlagStatus syscfg_cps_rdy_flag_get(void) +{ + if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)) { + return SET; + } else { + return RESET; + } +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_timer.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_timer.c new file mode 100644 index 000000000..2a1a8f8fe --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_timer.c @@ -0,0 +1,2064 @@ +/*! + \file gd32f3x0_timer.c + \brief TIMER driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + + +#include "gd32f3x0_timer.h" + +/*! + \brief deinit a TIMER + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval none +*/ +void timer_deinit(uint32_t timer_periph) +{ + switch(timer_periph) { + case TIMER0: + /* reset TIMER0 */ + rcu_periph_reset_enable(RCU_TIMER0RST); + rcu_periph_reset_disable(RCU_TIMER0RST); + break; + case TIMER1: + /* reset TIMER1 */ + rcu_periph_reset_enable(RCU_TIMER1RST); + rcu_periph_reset_disable(RCU_TIMER1RST); + break; + case TIMER2: + /* reset TIMER2 */ + rcu_periph_reset_enable(RCU_TIMER2RST); + rcu_periph_reset_disable(RCU_TIMER2RST); + break; +#ifdef GD32F350 + case TIMER5: + /* reset TIMER5 */ + rcu_periph_reset_enable(RCU_TIMER5RST); + rcu_periph_reset_disable(RCU_TIMER5RST); + break; +#endif + case TIMER13: + /* reset TIMER13 */ + rcu_periph_reset_enable(RCU_TIMER13RST); + rcu_periph_reset_disable(RCU_TIMER13RST); + break; + case TIMER14: + /* reset TIMER14 */ + rcu_periph_reset_enable(RCU_TIMER14RST); + rcu_periph_reset_disable(RCU_TIMER14RST); + break; + case TIMER15: + /* reset TIMER15 */ + rcu_periph_reset_enable(RCU_TIMER15RST); + rcu_periph_reset_disable(RCU_TIMER15RST); + break; + case TIMER16: + /* reset TIMER16 */ + rcu_periph_reset_enable(RCU_TIMER16RST); + rcu_periph_reset_disable(RCU_TIMER16RST); + break; + default: + break; + } +} + +/*! + \brief initialize TIMER init parameter struct with a default value + \param[in] initpara: init parameter struct + \param[out] none + \retval none +*/ +void timer_struct_para_init(timer_parameter_struct *initpara) +{ + /* initialize the init parameter struct member with the default value */ + initpara->prescaler = 0U; + initpara->alignedmode = TIMER_COUNTER_EDGE; + initpara->counterdirection = TIMER_COUNTER_UP; + initpara->period = 65535U; + initpara->clockdivision = TIMER_CKDIV_DIV1; + initpara->repetitioncounter = 0U; +} + +/*! + \brief initialize TIMER counter + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[in] timer_initpara: init parameter struct + prescaler: prescaler value of the counter clock,0~65535 + alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH + counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN + period: counter auto reload value,(TIMER1 32 bit) + clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 + repetitioncounter: counter repetition value,0~255 + \param[out] none + \retval none +*/ +void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara) +{ + /* configure the counter prescaler value */ + TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; + + /* configure the counter direction and aligned mode */ + if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph)) { + TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM); + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection; + } + + /* configure the autoreload value */ + TIMER_CAR(timer_periph) = (uint32_t)initpara->period; + + if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER13 == timer_periph) + || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)) { + /* reset the CKDIV bit */ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision; + } + + if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)) { + /* configure the repetition counter value */ + TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; + } + + /* generate an update event */ + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; +} + +/*! + \brief enable a TIMER + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval none +*/ +void timer_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief disable a TIMER + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval none +*/ +void timer_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief enable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief disable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief enable the update event + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval none +*/ +void timer_update_event_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; +} + +/*! + \brief disable the update event + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval none +*/ +void timer_update_event_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; +} + +/*! + \brief set TIMER counter alignment mode + \param[in] timer_periph: TIMERx(x=0..2) + \param[in] aligned: + only one parameter can be selected which is shown as below: + \arg TIMER_COUNTER_EDGE: edge-aligned mode + \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode + \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode + \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode + \param[out] none + \retval none +*/ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; + TIMER_CTL0(timer_periph) |= (uint32_t)aligned; +} + +/*! + \brief set TIMER counter up direction + \param[in] timer_periph: TIMERx(x=0..2) + \param[out] none + \retval none +*/ +void timer_counter_up_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief set TIMER counter down direction + \param[in] timer_periph: TIMERx(x=0..2) + \param[out] none + \retval none +*/ +void timer_counter_down_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief configure TIMER prescaler + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[in] prescaler: prescaler value + \param[in] pscreload: prescaler reload mode + only one parameter can be selected which is shown as below: + \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now + \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event + \param[out] none + \retval none +*/ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload) +{ + TIMER_PSC(timer_periph) = (uint32_t)prescaler; + + if(TIMER_PSC_RELOAD_NOW == pscreload) { + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; + } +} + +/*! + \brief configure TIMER repetition register value + \param[in] timer_periph: TIMERx(x=0,15,16) + \param[in] repetition: the counter repetition value,0~255 + \param[out] none + \retval none +*/ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) +{ + TIMER_CREP(timer_periph) = (uint32_t)repetition; +} + +/*! + \brief configure TIMER autoreload register value + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[in] autoreload: the counter auto-reload value + \param[out] none + \retval none +*/ +void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload) +{ + TIMER_CAR(timer_periph) = (uint32_t)autoreload; +} + +/*! + \brief configure TIMER counter register value + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[in] counter: the counter value + \param[out] none + \retval none +*/ +void timer_counter_value_config(uint32_t timer_periph, uint32_t counter) +{ + TIMER_CNT(timer_periph) = (uint32_t)counter; +} + +/*! + \brief read TIMER counter value + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval counter value +*/ +uint32_t timer_counter_read(uint32_t timer_periph) +{ + uint32_t count_value = 0U; + count_value = TIMER_CNT(timer_periph); + return (count_value); +} + +/*! + \brief read TIMER prescaler value + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[out] none + \retval prescaler register value +*/ +uint16_t timer_prescaler_read(uint32_t timer_periph) +{ + uint16_t prescaler_value = 0U; + prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); + return (prescaler_value); +} + +/*! + \brief configure TIMER single pulse mode + \param[in] timer_periph: TIMERx(x=0..2,14..16),TIMER5 just for GD32F350 + \param[in] spmode: + only one parameter can be selected which is shown as below: + \arg TIMER_SP_MODE_SINGLE: single pulse mode + \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode + \param[out] none + \retval none +*/ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode) +{ + if(TIMER_SP_MODE_SINGLE == spmode) { + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; + } else if(TIMER_SP_MODE_REPETITIVE == spmode) { + TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER update source + \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \param[in] update: + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger + \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow + \param[out] none + \retval none +*/ +void timer_update_source_config(uint32_t timer_periph, uint8_t update) +{ + if(TIMER_UPDATE_SRC_REGULAR == update) { + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; + } else if(TIMER_UPDATE_SRC_GLOBAL == update) { + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER OCPRE clear source selection + \param[in] timer_periph: TIMERx(x=0..2) + \param[in] ocpreclear: + only one parameter can be selected which is shown as below: + \arg TIMER_OCPRE_CLEAR_SOURCE_CLR: OCPRE_CLR_INT is connected to the OCPRE_CLR input + \arg TIMER_OCPRE_CLEAR_SOURCE_ETIF: OCPRE_CLR_INT is connected to ETIF + \param[out] none + \retval none +*/ +void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear) +{ + if(TIMER_OCPRE_CLEAR_SOURCE_ETIF == ocpreclear) { + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_OCRC; + } else if(TIMER_OCPRE_CLEAR_SOURCE_CLR == ocpreclear) { + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_OCRC; + } else { + /* illegal parameters */ + } +} + +/*! + \brief get TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..2,13..16) + \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..2,14) + \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..2) + \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..2) + \arg TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16) + \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..2,14) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..2,13..16) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..2,14) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..2) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..2) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) +{ + if(RESET != (TIMER_INTF(timer_periph) & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..2,13..16) + \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..2,14) + \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..2) + \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..2) + \arg TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16) + \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..2,14) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..2,13..16) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..2,14) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..2) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..2) + \param[out] none + \retval none +*/ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag) +{ + TIMER_INTF(timer_periph) = (~(uint32_t)flag); +} + +/*! + \brief enable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt enable source + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..2,13..16) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..2,14) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..2) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..2) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,14..16) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..2,14) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; +} + +/*! + \brief disable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt source disable + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt disable, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \arg TIMER_INT_CH0: channel 0 interrupt disable, TIMERx(x=0..2,13..16) + \arg TIMER_INT_CH1: channel 1 interrupt disable, TIMERx(x=0..2,14) + \arg TIMER_INT_CH2: channel 2 interrupt disable, TIMERx(x=0..2) + \arg TIMER_INT_CH3: channel 3 interrupt disable , TIMERx(x=0..2) + \arg TIMER_INT_CMT: commutation interrupt disable, TIMERx(x=0,14..16) + \arg TIMER_INT_TRG: trigger interrupt disable, TIMERx(x=0..2,14) + \arg TIMER_INT_BRK: break interrupt disable, TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); +} + +/*! + \brief get timer interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..2,13..16) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..2,14) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..2) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..2) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,14..16) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0..2,14) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,14..16) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) +{ + uint32_t val; + val = (TIMER_DMAINTEN(timer_periph) & interrupt); + if((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TIMER interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..2,13..16) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..2,14) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..2) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..2) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0,14..16) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0..2,14) + \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); +} + +/*! + \brief enable the TIMER DMA + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: specify which DMA to enable + one or more parameters can be selected which is shown as below: + \arg TIMER_DMA_UPD: update DMA, TIMERx(x=0..2,14..16),TIMER5 just for GD32F350 + \arg TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0..2,14..16) + \arg TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0..2,14) + \arg TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0..2) + \arg TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0..2) + \arg TIMER_DMA_CMTD: commutation DMA request, TIMERx(x=0,14) + \arg TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0..2,14) + \param[out] none + \retval none +*/ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; +} + +/*! + \brief disable the TIMER DMA + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: specify which DMA to disable + one or more parameters can be selected which are shown as below: + \arg TIMER_DMA_UPD: update DMA, TIMERx(x=0..2,14..16),TIMER5 just for GD32F350 + \arg TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0..2,14..16) + \arg TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0..2,14) + \arg TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0..2) + \arg TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0..2) + \arg TIMER_DMA_CMTD: commutation DMA request , TIMERx(x=0,14) + \arg TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0..2,14) + \param[out] none + \retval none +*/ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); +} + +/*! + \brief channel DMA request source selection + \param[in] timer_periph: TIMERx(x=0..2,14..16) + \param[in] dma_request: channel DMA request source selection + only one parameter can be selected which is shown as below: + \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs + \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs + \param[out] none + \retval none +*/ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request) +{ + if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; + } else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request) { + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure the TIMER DMA transfer + \param[in] timer_periph: TIMERx(x=0..2,14..16) + \param[in] dma_baseaddr: + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0..2,14) + \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0..2) + \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0,14..16) + \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0..2,14) + \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0..2) + \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0..2) + \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0,14..16) + \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG, TIMERx(x=0..2,14..16) + \arg TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB, TIMERx(x=0..2,14..16) + \param[in] dma_lenth: + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time + \param[out] none + \retval none +*/ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) +{ + TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); + TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); +} + +/*! + \brief software generate events + \param[in] timer_periph: please refer to the following parameters + \param[in] event: the timer software event generation sources + one or more parameters can be selected which are shown as below: + \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..2,13..16), TIMER5 just for GD32F350 + \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..2,13..16) + \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..2,14) + \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..2) + \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..2) + \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,14..16) + \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..2,14) + \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event) +{ + TIMER_SWEVG(timer_periph) |= (uint32_t)event; +} + +/*! + \brief initialize TIMER break parameter struct with a default value + \param[in] breakpara: TIMER break parameter struct + \param[out] none + \retval none +*/ +void timer_break_struct_para_init(timer_break_parameter_struct *breakpara) +{ + /* initialize the break parameter struct member with the default value */ + breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; + breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; + breakpara->deadtime = 0U; + breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; + breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; + breakpara->protectmode = TIMER_CCHP_PROT_OFF; + breakpara->breakstate = TIMER_BREAK_DISABLE; +} + +/*! + \brief configure TIMER break function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] breakpara: TIMER break parameter struct + runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE + ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE + deadtime: 0~255 + breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH + outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE + protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 + breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE + \param[out] none + \retval none +*/ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara) +{ + TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | + ((uint32_t)(breakpara->ideloffstate)) | + ((uint32_t)(breakpara->deadtime)) | + ((uint32_t)(breakpara->breakpolarity)) | + ((uint32_t)(breakpara->outputautostate)) | + ((uint32_t)(breakpara->protectmode)) | + ((uint32_t)(breakpara->breakstate))) ; +} + +/*! + \brief enable TIMER break function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_break_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief disable TIMER break function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_break_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief enable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_automatic_output_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief disable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_automatic_output_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief configure TIMER primary output function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; + } else { + TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); + } +} + +/*! + \brief enable or disable channel capture/compare control shadow register + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; + } else { + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); + } +} + +/*! + \brief configure TIMER channel control shadow register update control + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] ccuctl: channel control shadow register update control + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set + \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl) +{ + if(TIMER_UPDATECTL_CCU == ccuctl) { + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); + } else if(TIMER_UPDATECTL_CCUTRI == ccuctl) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; + } else { + /* illegal parameters */ + } +} + +/*! + \brief initialize TIMER channel output parameter struct with a default value + \param[in] ocpara: TIMER channel n output parameter struct + \param[out] none + \retval none +*/ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara) +{ + /* initialize the channel output parameter struct member with the default value */ + ocpara->outputstate = (uint16_t)TIMER_CCX_DISABLE; + ocpara->outputnstate = TIMER_CCXN_DISABLE; + ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; + ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; + ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; + ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; +} + +/*! + \brief configure TIMER channel output function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..2)) + \param[in] ocpara: TIMER channeln output parameter struct + outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE + outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE + ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW + ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW + ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH + ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH + \param[out] none + \retval none +*/ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; + /* reset the CH0P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + /* set the CH0P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; + + if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)) { + /* reset the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + /* set the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; + /* reset the CH0NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + /* set the CH0NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; + /* reset the ISO0 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); + /* set the ISO0 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; + /* reset the ISO0N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); + /* set the ISO0N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; + } + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 4U); + /* reset the CH1P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + /* set the CH1P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); + + if(TIMER0 == timer_periph) { + /* reset the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + /* set the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); + /* reset the ISO1 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); + /* set the ISO1 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); + /* reset the ISO1N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); + /* set the ISO1N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); + } + + if(TIMER14 == timer_periph) { + /* reset the ISO1 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); + /* set the ISO1 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); + } + + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 8U); + /* reset the CH2P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + /* set the CH2P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); + + if(TIMER0 == timer_periph) { + /* reset the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + /* set the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); + /* reset the CH2NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + /* set the CH2NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); + /* reset the ISO2 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); + /* set the ISO2 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); + /* reset the ISO2N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); + /* set the ISO2N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); + } + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 12U); + /* reset the CH3P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + /* set the CH3P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); + + if(TIMER0 == timer_periph) { + /* reset the ISO3 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); + /* set the ISO3 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); + } + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output compare mode + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] ocmode: channel output compare mode + only one parameter can be selected which is shown as below: + \arg TIMER_OC_MODE_TIMING: timing mode + \arg TIMER_OC_MODE_ACTIVE: active mode + \arg TIMER_OC_MODE_INACTIVE: inactive mode + \arg TIMER_OC_MODE_TOGGLE: toggle mode + \arg TIMER_OC_MODE_LOW: force low mode + \arg TIMER_OC_MODE_HIGH: force high mode + \arg TIMER_OC_MODE_PWM0: PWM0 mode + \arg TIMER_OC_MODE_PWM1: PWM1 mode + \param[out] none + \retval none +*/ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output pulse value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] pulse: channel output pulse value,0~65535 + \param[out] none + \retval none +*/ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CH0CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CH1CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CH2CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CH3CV(timer_periph) = (uint32_t)pulse; + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output shadow function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] ocshadow: channel output shadow state + only one parameter can be selected which is shown as below: + \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable + \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable + \param[out] none + \retval none +*/ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output fast function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] ocfast: channel output fast function + only one parameter can be selected which is shown as below: + \arg TIMER_OC_FAST_ENABLE: channel output fast function enable + \arg TIMER_OC_FAST_DISABLE: channel output fast function disable + \param[out] none + \retval none +*/ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output clear function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] occlear: channel output clear function + only one parameter can be selected which is shown as below: + \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable + \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable + \param[out] none + \retval none +*/ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output polarity + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] ocpolarity: channel output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high + \arg TIMER_OC_POLARITY_LOW: channel output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output polarity + \param[in] timer_periph: TIMERx(x=0..2,14) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel2(TIMERx(x=1,2)) + \param[in] ocnpolarity: channel complementary output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high + \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel enable state + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] state: TIMER channel enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCX_ENABLE: channel enable + \arg TIMER_CCX_DISABLE: channel disable + \param[out] none + \retval none +*/ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)state; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output enable state + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,14..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0)) + \param[in] ocnstate: TIMER channel complementary output enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCXN_ENABLE: channel complementary enable + \arg TIMER_CCXN_DISABLE: channel complementary disable + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); + break; + default: + break; + } +} + +/*! + \brief initialize TIMER channel input parameter struct with a default value + \param[in] icpara: TIMER channel intput parameter struct + \param[out] none + \retval none +*/ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara) +{ + /* initialize the channel input parameter struct member with the default value */ + icpara->icpolarity = TIMER_IC_POLARITY_RISING; + icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; + icpara->icprescaler = TIMER_IC_PSC_DIV1; + icpara->icfilter = 0U; +} + +/*! + \brief configure TIMER input capture parameter + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] icpara: TIMER channel intput parameter struct + icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE + icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS + icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + break; + + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + + /* reset the CH2P and CH2NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); + + /* reset the CH2MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); + + /* reset the CH2CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + + /* reset the CH3P and CH3NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P | TIMER_CHCTL2_CH3NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); + + /* reset the CH3MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + + /* reset the CH3CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; + break; + default: + break; + } + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); +} + +/*! + \brief configure TIMER channel input capture prescaler value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[in] prescaler: channel input capture prescaler value + only one parameter can be selected which is shown as below: + \arg TIMER_IC_PSC_DIV1: no prescaler + \arg TIMER_IC_PSC_DIV2: divided by 2 + \arg TIMER_IC_PSC_DIV4: divided by 4 + \arg TIMER_IC_PSC_DIV8: divided by 8 + \param[out] none + \retval none +*/ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); + TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); + TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); + TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); + TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + default: + break; + } +} + +/*! + \brief read TIMER channel capture compare register value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) + \param[out] none + \retval channel capture compare register value +*/ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) +{ + uint32_t count_value = 0U; + + switch(channel) { + /* read TIMER channel 0 capture compare register value */ + case TIMER_CH_0: + count_value = TIMER_CH0CV(timer_periph); + break; + /* read TIMER channel 1 capture compare register value */ + case TIMER_CH_1: + count_value = TIMER_CH1CV(timer_periph); + break; + /* read TIMER channel 2 capture compare register value */ + case TIMER_CH_2: + count_value = TIMER_CH2CV(timer_periph); + break; + /* read TIMER channel 3 capture compare register value */ + case TIMER_CH_3: + count_value = TIMER_CH3CV(timer_periph); + break; + default: + break; + } + return (count_value); +} + +/*! + \brief configure TIMER input pwm capture function + \param[in] timer_periph: TIMERx(x=0..2,14) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0 + \arg TIMER_CH_1: TIMER channel1 + \param[in] icpwm:TIMER channel intput pwm parameter struct + icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING + icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI + icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm) +{ + uint16_t icpolarity = 0x0U; + uint16_t icselection = 0x0U; + + /* Set channel input polarity */ + if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity) { + icpolarity = TIMER_IC_POLARITY_FALLING; + } else { + icpolarity = TIMER_IC_POLARITY_RISING; + } + + /* Set channel input mode selection */ + if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection) { + icselection = TIMER_IC_SELECTION_INDIRECTTI; + } else { + icselection = TIMER_IC_SELECTION_DIRECTTI; + } + + if(TIMER_CH_0 == channel) { + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); + + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + } else { + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); + } +} + +/*! + \brief configure TIMER hall sensor mode + \param[in] timer_periph: TIMERx(x=0..2) + \param[in] hallmode: + only one parameter can be selected which is shown as below: + \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable + \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable + \param[out] none + \retval none +*/ +void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode) +{ + if(TIMER_HALLINTERFACE_ENABLE == hallmode) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; + } else if(TIMER_HALLINTERFACE_DISABLE == hallmode) { + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; + } else { + /* illegal parameters */ + } +} + +/*! + \brief select TIMER input trigger source + \param[in] timer_periph: TIMERx(x=0..2,14) + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..2,14)) + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..2,14)) + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..2)) + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0..2,14)) + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..2,14)) + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..2,14)) + \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger(TIMERx(x=0..2)) + \param[out] none + \retval none +*/ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); + TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; +} + +/*! + \brief select TIMER master mode output trigger source + \param[in] timer_periph: TIMERx(x=0..2,14),TIMER5 just for GD32F350 + \param[in] outrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350) + \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350) + \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350) + \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO + \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..2,14)) + \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..2,14)) + \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..2,14)) + \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..2,14)) + \param[out] none + \retval none +*/ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) +{ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); + TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; +} + +/*! + \brief select TIMER slave mode + \param[in] timer_periph: TIMERx(x=0..2,14) + \param[in] slavemode: + only one parameter can be selected which is shown as below: + \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0..2,14)) + \arg TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0..2)) + \arg TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0..2)) + \arg TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0..2)) + \arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0..2,14)) + \arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0..2,14)) + \arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0..2,14)) + \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0(TIMERx(x=0..2,14)) + \param[out] none + \retval none +*/ + +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + + TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; +} + +/*! + \brief configure TIMER master slave mode + \param[in] timer_periph: TIMERx(x=0..2,14) + \param[in] masterslave: + only one parameter can be selected which is shown as below: + \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable + \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable + \param[out] none + \retval none +*/ +void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave) +{ + if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave) { + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; + } else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave) { + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER external trigger input + \param[in] timer_periph: TIMERx(x=0..2) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); +} + +/*! + \brief configure TIMER quadrature decoder mode + \param[in] timer_periph: TIMERx(x=0..2) + \param[in] decomode: + only one parameter can be selected which is shown as below: + \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level + \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level + \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input + \param[in] ic0polarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[in] ic1polarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[out] none + \retval none +*/ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, + uint16_t ic0polarity, uint16_t ic1polarity) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; + + TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS))); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); + + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U)); +} + +/*! + \brief configure TIMER internal clock mode + \param[in] timer_periph: TIMERx(x=0..2,14) + \param[out] none + \retval none +*/ +void timer_internal_clock_config(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; +} + +/*! + \brief configure TIMER the internal trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..2,14) + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..2,14)) + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..2,14)) + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..2)) + \param[out] none + \retval none +*/ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) +{ + timer_input_trigger_source_select(timer_periph, intrigger); + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external trigger as external clock input + \param[in] timer_periph: TIMERx(x=0..2,14) + \param[in] extrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: active high or rising edge active + \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active + \arg TIMER_IC_POLARITY_BOTH_EDGE: active both edge + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, + uint16_t extpolarity, uint32_t extfilter) +{ + if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger) { + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + } else { + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + } + /* select TIMER input trigger source */ + timer_input_trigger_source_select(timer_periph, extrigger); + /* reset the SMC bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + /* set the SMC bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external clock mode0 + \param[in] timer_periph: TIMERx(x=0..2) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + + /* reset the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); + /* set the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); +} + +/*! + \brief configure TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..2) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief disable TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0..2) + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_disable(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief configure TIMER channel remap function + \param[in] timer_periph: TIMERx(x=13) + \param[in] remap: + only one parameter can be selected which is shown as below: + \arg TIMER13_CI0_RMP_GPIO: timer13 channel 0 input is connected to GPIO(TIMER13_CH0) + \arg TIMER13_CI0_RMP_RTCCLK: timer13 channel 0 input is connected to the RTCCLK + \arg TIMER13_CI0_RMP_HXTAL_DIV32: timer13 channel 0 input is connected to HXTAL/32 clock + \arg TIMER13_CI0_RMP_CKOUTSEL: timer13 channel 0 input is connected to CKOUTSEL + \param[out] none + \retval none +*/ +void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap) +{ + TIMER_IRMP(timer_periph) = (uint32_t)remap; +} + +/*! + \brief configure TIMER write CHxVAL register selection + \param[in] timer_periph: TIMERx(x=0..2,13..16) + \param[in] ccsel: + only one parameter can be selected which is shown as below: + \arg TIMER_CHVSEL_DISABLE: no effect + \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored + \param[out] none + \retval none +*/ +void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel) +{ + if(TIMER_CHVSEL_ENABLE == ccsel) { + TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; + } else if(TIMER_CHVSEL_DISABLE == ccsel) { + TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER output value selection + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] outsel: + only one parameter can be selected which is shown as below: + \arg TIMER_OUTSEL_DISABLE: no effect + \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled + \param[out] none + \retval none +*/ +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) +{ + if(TIMER_OUTSEL_ENABLE == outsel) { + TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; + } else if(TIMER_OUTSEL_DISABLE == outsel) { + TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; + } else { + /* illegal parameters */ + } +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_tsi.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_tsi.c new file mode 100644 index 000000000..6fe4a9034 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_tsi.c @@ -0,0 +1,690 @@ +/*! + \file gd32f3x0_tsi.c + \brief TSI driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_tsi.h" + +/*! + \brief reset TSI peripheral + \param[in] none + \param[out] none + \retval none +*/ +void tsi_deinit(void) +{ + rcu_periph_reset_enable(RCU_TSIRST); + rcu_periph_reset_disable(RCU_TSIRST); +} + +/*! + \brief initialize TSI plus prescaler,charge plus,transfer plus,max cycle number + \param[in] prescaler: CTCLK clock division factor + only one parameter can be selected which is shown as below: + \arg TSI_CTCDIV_DIV1: fCTCLK = fHCLK + \arg TSI_CTCDIV_DIV2: fCTCLK = fHCLK/2 + \arg TSI_CTCDIV_DIV4: fCTCLK = fHCLK/4 + \arg TSI_CTCDIV_DIV8: fCTCLK = fHCLK/8 + \arg TSI_CTCDIV_DIV16: fCTCLK = fHCLK/16 + \arg TSI_CTCDIV_DIV32: fCTCLK = fHCLK/32 + \arg TSI_CTCDIV_DIV64: fCTCLK = fHCLK/64 + \arg TSI_CTCDIV_DIV128: fCTCLK = fHCLK/128 + \arg TSI_CTCDIV_DIV256: fCTCLK = fHCLK/256 + \arg TSI_CTCDIV_DIV512: fCTCLK = fHCLK/512 + \arg TSI_CTCDIV_DIV1024: fCTCLK = fHCLK/1024 + \arg TSI_CTCDIV_DIV2048: fCTCLK = fHCLK/2048 + \arg TSI_CTCDIV_DIV4096: fCTCLK = fHCLK/4096 + \arg TSI_CTCDIV_DIV8192: fCTCLK = fHCLK/8192 + \arg TSI_CTCDIV_DIV16384: fCTCLK = fHCLK/16384 + \arg TSI_CTCDIV_DIV32768: fCTCLK = fHCLK/32768 + \param[in] charge_duration: charge state duration time + only one parameter can be selected which is shown as below: + \arg TSI_CHARGE_1CTCLK(x=1..16): the duration time of charge state is x CTCLK + \param[in] transfer_duration: charge transfer state duration time + only one parameter can be selected which is shown as below: + \arg TSI_TRANSFER_xCTCLK(x=1..16): the duration time of transfer state is x CTCLK + \param[in] max_number: max cycle number + only one parameter can be selected which is shown as below: + \arg TSI_MAXNUM255: the max cycle number of a sequence is 255 + \arg TSI_MAXNUM511: the max cycle number of a sequence is 511 + \arg TSI_MAXNUM1023: the max cycle number of a sequence is 1023 + \arg TSI_MAXNUM2047: the max cycle number of a sequence is 2047 + \arg TSI_MAXNUM4095: the max cycle number of a sequence is 4095 + \arg TSI_MAXNUM8191: the max cycle number of a sequence is 8191 + \arg TSI_MAXNUM16383: the max cycle number of a sequence is 16383 + \param[out] none + \retval none +*/ +void tsi_init(uint32_t prescaler, uint32_t charge_duration, uint32_t transfer_duration, uint32_t max_number) +{ + uint32_t ctl0,ctl1; + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + if(TSI_CTCDIV_DIV256 > prescaler){ + /* config TSI_CTL0 */ + ctl0 = TSI_CTL0; + /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */ + ctl0 &= ~(TSI_CTL0_CTCDIV | TSI_CTL0_CTDT | TSI_CTL0_CDT | TSI_CTL0_MCN); + ctl0 |= ((prescaler << 12U) | charge_duration | transfer_duration | max_number); + TSI_CTL0 = ctl0; + + /* config TSI_CTL1 */ + ctl1 = TSI_CTL1; + ctl1 &= ~TSI_CTL1_CTCDIV; + TSI_CTL1 = ctl1; + }else{ + /* config TSI_CTL0 */ + ctl0 = TSI_CTL0; + prescaler &= ~0x08U; + /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */ + ctl0 &= ~(TSI_CTL0_CTCDIV | TSI_CTL0_CTDT | TSI_CTL0_CDT | TSI_CTL0_MCN); + ctl0 |= ((prescaler << 12U) | charge_duration | transfer_duration | max_number); + TSI_CTL0 = ctl0; + + /* config TSI_CTL1 */ + ctl1 = TSI_CTL1; + ctl1 |= TSI_CTL1_CTCDIV; + TSI_CTL1 = ctl1; + } + } +} + +/*! + \brief enable TSI module + \param[in] none + \param[out] none + \retval none +*/ +void tsi_enable(void) +{ + TSI_CTL0 |= TSI_CTL0_TSIEN; +} + +/*! + \brief disable TSI module + \param[in] none + \param[out] none + \retval none +*/ +void tsi_disable(void) +{ + TSI_CTL0 &= ~TSI_CTL0_TSIEN; +} + +/*! + \brief enable sample pin + \param[in] sample: sample pin + one or more parameters can be selected which are shown as below: + \arg TSI_SAMPCFG_GxPy( x=0..5,y=0..3):pin y of group x is sample pin + \param[out] none + \retval none +*/ +void tsi_sample_pin_enable(uint32_t sample) +{ + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + TSI_SAMPCFG |= sample; + } +} + +/*! + \brief disable sample pin + \param[in] sample: sample pin + one or more parameters can be selected which are shown as below: + \arg TSI_SAMPCFG_GxPy( x=0..5,y=0..3): pin y of group x is sample pin + \param[out] none + \retval none +*/ +void tsi_sample_pin_disable(uint32_t sample) +{ + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + TSI_SAMPCFG &= ~sample; + } +} + +/*! + \brief enable channel pin + \param[in] channel: channel pin + one or more parameters can be selected which are shown as below: + \arg TSI_CHCFG_GxPy( x=0..5,y=0..3): pin y of group x + \param[out] none + \retval none +*/ +void tsi_channel_pin_enable(uint32_t channel) +{ + TSI_CHCFG |= channel; +} + +/*! + \brief disable channel pin + \param[in] channel: channel pin + one or more parameters can be selected which are shown as below: + \arg TSI_CHCFG_GxPy( x=0..5,y=0..3): pin y of group x + \param[out] none + \retval none +*/ +void tsi_channel_pin_disable(uint32_t channel) +{ + TSI_CHCFG &= ~channel; +} + +/*! + \brief configure TSI triggering by software + \param[in] none + \param[out] none + \retval none +*/ +void tsi_software_mode_config(void) +{ + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + TSI_CTL0 &= ~TSI_CTL0_TRGMOD; + } +} + +/*! + \brief start a charge-transfer sequence when TSI is in software trigger mode + \param[in] none + \param[out] none + \retval none +*/ +void tsi_software_start(void) +{ + TSI_CTL0 |= TSI_CTL0_TSIS; +} + +/*! + \brief stop a charge-transfer sequence when TSI is in software trigger mode + \param[in] none + \param[out] none + \retval none +*/ +void tsi_software_stop(void) +{ + TSI_CTL0 &= ~TSI_CTL0_TSIS; +} + +/*! + \brief configure TSI triggering by hardware + \param[in] trigger_edge: the edge type in hardware trigger mode + only one parameter can be selected which is shown as below: + \arg TSI_FALLING_TRIGGER: falling edge trigger TSI charge transfer sequence + \arg TSI_RISING_TRIGGER: rising edge trigger TSI charge transfer sequence + \param[out] none + \retval none +*/ +void tsi_hardware_mode_config(uint8_t trigger_edge) +{ + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + /*enable hardware mode*/ + TSI_CTL0 |= TSI_CTL0_TRGMOD; + /*configure the edge type in hardware trigger mode*/ + if(TSI_FALLING_TRIGGER == trigger_edge){ + TSI_CTL0 &= ~TSI_CTL0_EGSEL; + }else{ + TSI_CTL0 |= TSI_CTL0_EGSEL; + } + } +} + +/*! + \brief configure TSI pin mode when charge-transfer sequence is IDLE + \param[in] pin_mode: pin mode when charge-transfer sequence is IDLE + only one parameter can be selected which is shown as below: + \arg TSI_OUTPUT_LOW: TSI pin will output low when IDLE + \arg TSI_INPUT_FLOATING: TSI pin will keep input_floating when IDLE + \param[out] none + \retval none +*/ +void tsi_pin_mode_config(uint8_t pin_mode) +{ + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + if(TSI_OUTPUT_LOW == pin_mode){ + TSI_CTL0 &= ~TSI_CTL0_PINMOD; + }else{ + TSI_CTL0 |= TSI_CTL0_PINMOD; + } + } +} + +/*! + \brief configure extend charge state + \param[in] extend: enable or disable extend charge state + only one parameter can be selected which is shown as below: + \arg ENABLE: enable extend charge state + \arg DISABLE: disable extend charge state + \param[in] prescaler: ECCLK clock division factor + only one parameter can be selected which is shown as below: + \arg TSI_EXTEND_DIV1: fECCLK = fHCLK + \arg TSI_EXTEND_DIV2: fECCLK = fHCLK/2 + \arg TSI_EXTEND_DIV3: fECCLK = fHCLK/3 + \arg TSI_EXTEND_DIV4: fECCLK = fHCLK/4 + \arg TSI_EXTEND_DIV5: fECCLK = fHCLK/5 + \arg TSI_EXTEND_DIV6: fECCLK = fHCLK/6 + \arg TSI_EXTEND_DIV7: fECCLK = fHCLK/7 + \arg TSI_EXTEND_DIV8: fECCLK = fHCLK/8 + \param[in] max_duration: value range 1...128,extend charge state maximum duration time is 1*tECCLK~128*tECCLK + \param[out] none + \retval none +*/ +void tsi_extend_charge_config(ControlStatus extend, uint8_t prescaler, uint32_t max_duration) +{ + uint32_t ctl0,ctl1; + + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + if(DISABLE == extend){ + /*disable extend charge state*/ + TSI_CTL0 &= ~TSI_CTL0_ECEN; + }else{ + if(TSI_EXTEND_DIV3 > prescaler){ + /*configure extend charge state maximum duration time*/ + ctl0 = TSI_CTL0; + ctl0 &= ~TSI_CTL0_ECDT; + ctl0 |= TSI_EXTENDMAX((max_duration - 1U)); + TSI_CTL0 = ctl0; + /*configure ECCLK clock division factor*/ + ctl0 = TSI_CTL0; + ctl0 &= ~TSI_CTL0_ECDIV; + ctl0 |= (uint32_t)prescaler << 15U; + TSI_CTL0 = ctl0; + /*enable extend charge state*/ + TSI_CTL0 |= TSI_CTL0_ECEN; + }else{ + /*configure extend charge state maximum duration time*/ + ctl0 = TSI_CTL0; + ctl0 &= ~TSI_CTL0_ECDT; + ctl0 |= TSI_EXTENDMAX((max_duration - 1U)); + TSI_CTL0 = ctl0; + /*configure ECCLK clock division factor*/ + ctl0 = TSI_CTL0; + ctl0 &= ~TSI_CTL0_ECDIV; + ctl0 |= (prescaler & 0x01U) << 15U; + TSI_CTL0 = ctl0; + ctl1 = TSI_CTL1; + ctl1 &= ~TSI_CTL1_ECDIV; + ctl1 |= (prescaler & 0x06U) << 28U; + TSI_CTL1 = ctl1; + /*enable extend charge state*/ + TSI_CTL0 |= TSI_CTL0_ECEN; + } + } + } +} + +/*! + \brief configure charge plus and transfer plus + \param[in] prescaler: CTCLK clock division factor + only one parameter can be selected which is shown as below: + \arg TSI_CTCDIV_DIV1: fCTCLK = fHCLK + \arg TSI_CTCDIV_DIV2: fCTCLK = fHCLK/2 + \arg TSI_CTCDIV_DIV4: fCTCLK = fHCLK/4 + \arg TSI_CTCDIV_DIV8: fCTCLK = fHCLK/8 + \arg TSI_CTCDIV_DIV16: fCTCLK = fHCLK/16 + \arg TSI_CTCDIV_DIV32: fCTCLK = fHCLK/32 + \arg TSI_CTCDIV_DIV64: fCTCLK = fHCLK/64 + \arg TSI_CTCDIV_DIV128: fCTCLK = fHCLK/128 + \arg TSI_CTCDIV_DIV256: fCTCLK = fHCLK/256 + \arg TSI_CTCDIV_DIV512: fCTCLK = fHCLK/512 + \arg TSI_CTCDIV_DIV1024: fCTCLK = fHCLK/1024 + \arg TSI_CTCDIV_DIV2048: fCTCLK = fHCLK/2048 + \arg TSI_CTCDIV_DIV4096: fCTCLK = fHCLK/4096 + \arg TSI_CTCDIV_DIV8192: fCTCLK = fHCLK/8192 + \arg TSI_CTCDIV_DIV16384: fCTCLK = fHCLK/16384 + \arg TSI_CTCDIV_DIV32768: fCTCLK = fHCLK/32768 + \param[in] charge_duration: charge state duration time + only one parameter can be selected which is shown as below: + \arg TSI_CHARGE_xCTCLK(x=1..16): the duration time of charge state is x CTCLK + \param[in] transfer_duration: charge transfer state duration time + only one parameter can be selected which is shown as below: + \arg TSI_TRANSFER_xCTCLK(x=1..16): the duration time of transfer state is x CTCLK + \param[out] none + \retval none +*/ +void tsi_plus_config(uint32_t prescaler, uint32_t charge_duration, uint32_t transfer_duration) +{ + uint32_t ctl0,ctl1; + + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + if(TSI_CTCDIV_DIV256 > prescaler){ + /* config TSI_CTL0 */ + ctl0 = TSI_CTL0; + /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */ + ctl0 &= ~(TSI_CTL0_CTCDIV | TSI_CTL0_CTDT | TSI_CTL0_CDT); + ctl0 |= ((prescaler << 12U) | charge_duration | transfer_duration); + TSI_CTL0 = ctl0; + + /* config TSI_CTL1 */ + ctl1 = TSI_CTL1; + ctl1 &= ~TSI_CTL1_CTCDIV; + TSI_CTL1 = ctl1; + }else{ + /* config TSI_CTL */ + ctl0 = TSI_CTL0; + prescaler &= ~0x08U; + /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */ + ctl0 &= ~(TSI_CTL0_CTCDIV | TSI_CTL0_CTDT | TSI_CTL0_CDT); + ctl0 |= ((prescaler << 12U) | charge_duration | transfer_duration); + TSI_CTL0 = ctl0; + + /* config TSI_CTL2 */ + ctl1 = TSI_CTL1; + ctl1 |= TSI_CTL1_CTCDIV; + TSI_CTL1 = ctl1; + } + } +} + +/*! + \brief configure the max cycle number of a charge-transfer sequence + \param[in] max_number: max cycle number + only one parameter can be selected which is shown as below: + \arg TSI_MAXNUM255: the max cycle number of a sequence is 255 + \arg TSI_MAXNUM511: the max cycle number of a sequence is 511 + \arg TSI_MAXNUM1023: the max cycle number of a sequence is 1023 + \arg TSI_MAXNUM2047: the max cycle number of a sequence is 2047 + \arg TSI_MAXNUM4095: the max cycle number of a sequence is 4095 + \arg TSI_MAXNUM8191: the max cycle number of a sequence is 8191 + \arg TSI_MAXNUM16383: the max cycle number of a sequence is 16383 + \param[out] none + \retval none +*/ +void tsi_max_number_config(uint32_t max_number) +{ + if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ + uint32_t maxnum; + maxnum = TSI_CTL0; + /*configure the max cycle number of a charge-transfer sequence*/ + maxnum &= ~TSI_CTL0_MCN; + maxnum |= max_number; + TSI_CTL0 = maxnum; + } +} + +/*! + \brief switch on hysteresis pin + \param[in] group_pin: select pin which will be switched on hysteresis + one or more parameters can be selected which are shown as below: + \arg TSI_PHM_GxPy(x=0..5,y=0..3): pin y of group x switch on hysteresis + \param[out] none + \retval none +*/ +void tsi_hysteresis_on(uint32_t group_pin) +{ + TSI_PHM |= group_pin; +} + +/*! + \brief switch off hysteresis pin + \param[in] group_pin: select pin which will be switched off hysteresis + one or more parameters can be selected which are shown as below: + \arg TSI_PHM_GxPy(x=0..5,y=0..3): pin y of group x switch off hysteresis + \param[out] none + \retval none +*/ +void tsi_hysteresis_off(uint32_t group_pin) +{ + TSI_PHM &= ~group_pin; +} + +/*! + \brief switch on analog pin + \param[in] group_pin: select pin which will be switched on analog + one or more parameters can be selected which are shown as below: + \arg TSI_ASW_GxPy(x=0..5,y=0..3):pin y of group x switch on analog + \param[out] none + \retval none +*/ +void tsi_analog_on(uint32_t group_pin) +{ + TSI_ASW |= group_pin; +} + +/*! + \brief switch off analog pin + \param[in] group_pin: select pin which will be switched off analog + one or more parameters can be selected which are shown as below: + \arg TSI_ASW_GxPy(x=0..5,y=0..3):pin y of group x switch off analog + \param[out] none + \retval none +*/ +void tsi_analog_off(uint32_t group_pin) +{ + TSI_ASW &= ~group_pin; +} + +/*! + \brief enbale group + \param[in] group: select group to be enabled + one or more parameters can be selected which are shown as below: + \arg TSI_GCTL_GEx(x=0..5): the x group will be enabled + \param[out] none + \retval none +*/ +void tsi_group_enable(uint32_t group) +{ + TSI_GCTL |= group; +} + +/*! + \brief disbale group + \param[in] group: select group to be disabled + one or more parameters can be selected which are shown as below: + \arg TSI_GCTL_GEx(x=0..5):the x group will be disabled + \param[out] none + \retval none +*/ +void tsi_group_disable(uint32_t group) +{ + TSI_GCTL &= ~group; +} + +/*! + \brief get group complete status + \param[in] group: select group + only one parameter can be selected which is shown as below: + \arg TSI_GCTL_GCx(x=0..5): get the complete status of group x + \param[out] none + \retval FlagStatus: group complete status,SET or RESET +*/ +FlagStatus tsi_group_status_get(uint32_t group) +{ + FlagStatus flag_status; + if(TSI_GCTL & group){ + flag_status = SET; + }else{ + flag_status = RESET; + } + return flag_status; +} + +/*! + \brief get the cycle number for group0 as soon as a charge-transfer sequence completes + \param[in] none + \param[out] none + \retval group0 cycle number +*/ +uint16_t tsi_group0_cycle_get(void) +{ + return (uint16_t)TSI_G0CYCN; +} + +/*! + \brief get the cycle number for group1 as soon as a charge-transfer sequence completes + \param[in] none + \param[out] none + \retval group1 cycle number +*/ +uint16_t tsi_group1_cycle_get(void) +{ + return (uint16_t)TSI_G1CYCN; +} + +/*! + \brief get the cycle number for group2 as soon as a charge-transfer sequence completes + \param[in] none + \param[out] none + \retval group2 cycle number +*/ +uint16_t tsi_group2_cycle_get(void) +{ + return (uint16_t)TSI_G2CYCN; +} + +/*! + \brief get the cycle number for group3 as soon as a charge-transfer sequence completes + \param[in] none + \param[out] none + \retval group3 cycle number +*/ +uint16_t tsi_group3_cycle_get(void) +{ + return (uint16_t)TSI_G3CYCN; +} + +/*! + \brief get the cycle number for group4 as soon as a charge-transfer sequence completes + \param[in] none + \param[out] none + \retval group4 cycle number +*/ +uint16_t tsi_group4_cycle_get(void) +{ + return (uint16_t)TSI_G4CYCN; +} + +/*! + \brief get the cycle number for group5 as soon as a charge-transfer sequence completes + \param[in] none + \param[out] none + \retval group5 cycle number +*/ +uint16_t tsi_group5_cycle_get(void) +{ + return (uint16_t)TSI_G5CYCN; +} + +/*! + \brief clear flag + \param[in] flag: select flag which will be cleared + only one parameter can be selected which is shown as below: + \arg TSI_FLAG_CTCF: clear charge-transfer complete flag + \arg TSI_FLAG_MNERR: clear max cycle number error + \param[out] none + \retval none +*/ +void tsi_flag_clear(uint32_t flag) +{ + TSI_INTC |= flag; +} + +/*! + \brief get flag + \param[in] flag: + only one parameter can be selected which is shown as below: + \arg TSI_FLAG_CTCF: charge-transfer complete flag + \arg TSI_FLAG_MNERR: max cycle bumber error + \param[out] none + \retval FlagStatus:SET or RESET +*/ +FlagStatus tsi_flag_get(uint32_t flag) +{ + FlagStatus flag_status; + if(TSI_INTF & flag){ + flag_status = SET; + }else{ + flag_status = RESET; + } + return flag_status; +} + +/*! + \brief enable TSI interrupt + \param[in] source: select interrupt which will be enabled + only one parameter can be selected which is shown as below: + \arg TSI_INT_CCTCF: charge-transfer complete flag interrupt enable + \arg TSI_INT_MNERR: max cycle number error interrupt enable + \param[out] none + \retval none +*/ +void tsi_interrupt_enable(uint32_t source) +{ + TSI_INTEN |= source; +} + +/*! + \brief disable TSI interrupt + \param[in] source: select interrupt which will be disabled + only one parameter can be selected which is shown as below: + \arg TSI_INT_CCTCF: charge-transfer complete flag interrupt disable + \arg TSI_INT_MNERR: max cycle number error interrupt disable + \param[out] none + \retval none +*/ +void tsi_interrupt_disable(uint32_t source) +{ + TSI_INTEN &= ~source; +} + +/*! + \brief clear TSI interrupt flag + \param[in] flag: select flag which will be cleared + only one parameter can be selected which is shown as below: + \arg TSI_INT_FLAG_CTCF: clear charge-transfer complete flag + \arg TSI_INT_FLAG_MNERR: clear max cycle number error + \param[out] none + \retval none +*/ +void tsi_interrupt_flag_clear(uint32_t flag) +{ + TSI_INTC |= flag; +} + +/*! + \brief get TSI interrupt flag + \param[in] flag: + only one parameter can be selected which is shown as below: + \arg TSI_INT_FLAG_CTCF: charge-transfer complete flag + \arg TSI_INT_FLAG_MNERR: max Cycle Number Error + \param[out] none + \retval FlagStatus:SET or RESET +*/ +FlagStatus tsi_interrupt_flag_get(uint32_t flag) +{ + uint32_t interrupt_enable = 0U,interrupt_flag = 0U; + interrupt_flag = (TSI_INTF & flag); + interrupt_enable = (TSI_INTEN & flag); + if(interrupt_flag && interrupt_enable){ + return SET; + }else{ + return RESET; + } +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_usart.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_usart.c new file mode 100644 index 000000000..00e48599c --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_usart.c @@ -0,0 +1,1310 @@ +/*! + \file gd32f3x0_usart.c + \brief USART driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_usart.h" + +/* USART register bit offset */ +#define CTL1_ADDR_OFFSET ((uint32_t)24U) /* bit offset of ADDR in USART_CTL1 */ +#define GP_GUAT_OFFSET ((uint32_t)8U) /* bit offset of GUAT in USART_GP */ +#define CTL2_SCRTNUM_OFFSET ((uint32_t)17U) /* bit offset of SCRTNUM in USART_CTL2 */ +#define RT_BL_OFFSET ((uint32_t)24U) /* bit offset of BL in USART_RT */ +#define CTL0_DEA_OFFSET ((uint32_t)21U) /* bit offset of DEA in USART_CTL0 */ +#define CTL0_DED_OFFSET ((uint32_t)16U) /* bit offset of DED in USART_CTL0 */ + +/*! + \brief reset USART + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_deinit(uint32_t usart_periph) +{ + switch(usart_periph) { + case USART0: + /* reset USART0 */ + rcu_periph_reset_enable(RCU_USART0RST); + rcu_periph_reset_disable(RCU_USART0RST); + break; + case USART1: + /* reset USART1 */ + rcu_periph_reset_enable(RCU_USART1RST); + rcu_periph_reset_disable(RCU_USART1RST); + break; + default: + break; + } +} + +/*! + \brief configure USART baud rate value + \param[in] usart_periph: USARTx(x=0,1) + \param[in] baudval: baud rate value + \param[out] none + \retval none +*/ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) +{ + uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U; + switch(usart_periph) { + /* get clock frequency */ + case USART0: + /* get USART0 clock */ + uclk = rcu_clock_freq_get(CK_USART); + break; + case USART1: + /* get USART1 clock */ + uclk = rcu_clock_freq_get(CK_APB1); + break; + default: + break; + } + if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD) { + /* oversampling by 8, configure the value of USART_BAUD */ + udiv = ((2U * uclk) + baudval / 2U) / baudval; + intdiv = udiv & 0x0000fff0U; + fradiv = (udiv >> 1U) & 0x00000007U; + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); + } else { + /* oversampling by 16, configure the value of USART_BAUD */ + udiv = (uclk + baudval / 2U) / baudval; + intdiv = udiv & 0x0000fff0U; + fradiv = udiv & 0x0000000fU; + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); + } +} + +/*! + \brief configure USART parity + \param[in] usart_periph: USARTx(x=0,1) + \param[in] paritycfg: USART parity configure + only one parameter can be selected which is shown as below: + \arg USART_PM_NONE: no parity + \arg USART_PM_ODD: odd parity + \arg USART_PM_EVEN: even parity + \param[out] none + \retval none +*/ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* clear USART_CTL0 PM,PCEN bits */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); + /* configure USART parity mode */ + USART_CTL0(usart_periph) |= paritycfg; +} + +/*! + \brief configure USART word length + \param[in] usart_periph: USARTx(x=0,1) + \param[in] wlen: USART word length configure + only one parameter can be selected which is shown as below: + \arg USART_WL_8BIT: 8 bits + \arg USART_WL_9BIT: 9 bits + \param[out] none + \retval none +*/ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* clear USART_CTL0 WL bit */ + USART_CTL0(usart_periph) &= ~USART_CTL0_WL; + /* configure USART word length */ + USART_CTL0(usart_periph) |= wlen; +} + +/*! + \brief configure USART stop bit length + \param[in] usart_periph: USARTx(x=0,1) + \param[in] stblen: USART stop bit configure + only one parameter can be selected which is shown as below: + \arg USART_STB_1BIT: 1 bit + \arg USART_STB_0_5BIT: 0.5bit + \arg USART_STB_2BIT: 2 bits + \arg USART_STB_1_5BIT: 1.5bit + \param[out] none + \retval none +*/ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* clear USART_CTL1 STB bits */ + USART_CTL1(usart_periph) &= ~USART_CTL1_STB; + USART_CTL1(usart_periph) |= stblen; +} + +/*! + \brief enable USART + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_UEN; +} + +/*! + \brief disable USART + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); +} + +/*! + \brief configure USART transmitter + \param[in] usart_periph: USARTx(x=0,1) + \param[in] txconfig: enable or disable USART transmitter + only one parameter can be selected which is shown as below: + \arg USART_TRANSMIT_ENABLE: enable USART transmission + \arg USART_TRANSMIT_DISABLE: enable USART transmission + \param[out] none + \retval none +*/ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) +{ + USART_CTL0(usart_periph) &= ~USART_CTL0_TEN; + /* configure transfer mode */ + USART_CTL0(usart_periph) |= txconfig; +} + +/*! + \brief configure USART receiver + \param[in] usart_periph: USARTx(x=0,1) + \param[in] rxconfig: enable or disable USART receiver + only one parameter can be selected which is shown as below: + \arg USART_RECEIVE_ENABLE: enable USART reception + \arg USART_RECEIVE_DISABLE: disable USART reception + \param[out] none + \retval none +*/ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) +{ + USART_CTL0(usart_periph) &= ~USART_CTL0_REN; + /* configure receiver mode */ + USART_CTL0(usart_periph) |= rxconfig; +} + +/*! + \brief data is transmitted/received with the LSB/MSB first + \param[in] usart_periph: USARTx(x=0,1) + \param[in] msbf: LSB/MSB + only one parameter can be selected which is shown as below: + \arg USART_MSBF_LSB: LSB first + \arg USART_MSBF_MSB: MSB first + \param[out] none + \retval none +*/ +void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* configure LSB or MSB first */ + USART_CTL1(usart_periph) &= ~(USART_CTL1_MSBF); + USART_CTL1(usart_periph) |= (USART_CTL1_MSBF & msbf); +} + +/*! + \brief USART inverted configure + \param[in] usart_periph: USARTx(x=0,1) + \param[in] invertpara: refer to usart_invert_enum + only one parameter can be selected which is shown as below: + \arg USART_DINV_ENABLE: data bit level inversion + \arg USART_DINV_DISABLE: data bit level not inversion + \arg USART_TXPIN_ENABLE: TX pin level inversion + \arg USART_TXPIN_DISABLE: TX pin level not inversion + \arg USART_RXPIN_ENABLE: RX pin level inversion + \arg USART_RXPIN_DISABLE: RX pin level not inversion + \arg USART_SWAP_ENABLE: swap TX/RX pins + \arg USART_SWAP_DISABLE: not swap TX/RX pins + \param[out] none + \retval none +*/ +void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* inverted or not the specified signal */ + switch(invertpara) { + case USART_DINV_ENABLE: + USART_CTL1(usart_periph) |= USART_CTL1_DINV; + break; + case USART_DINV_DISABLE: + USART_CTL1(usart_periph) &= ~(USART_CTL1_DINV); + break; + case USART_TXPIN_ENABLE: + USART_CTL1(usart_periph) |= USART_CTL1_TINV; + break; + case USART_TXPIN_DISABLE: + USART_CTL1(usart_periph) &= ~(USART_CTL1_TINV); + break; + case USART_RXPIN_ENABLE: + USART_CTL1(usart_periph) |= USART_CTL1_RINV; + break; + case USART_RXPIN_DISABLE: + USART_CTL1(usart_periph) &= ~(USART_CTL1_RINV); + break; + case USART_SWAP_ENABLE: + USART_CTL1(usart_periph) |= USART_CTL1_STRP; + break; + case USART_SWAP_DISABLE: + USART_CTL1(usart_periph) &= ~(USART_CTL1_STRP); + break; + default: + break; + } +} + +/*! + \brief enable the USART overrun function + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_overrun_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* enable overrun function */ + USART_CTL2(usart_periph) &= ~(USART_CTL2_OVRD); +} + +/*! + \brief disable the USART overrun function + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_overrun_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* disable overrun function */ + USART_CTL2(usart_periph) |= USART_CTL2_OVRD; +} + +/*! + \brief configure the USART oversample mode + \param[in] usart_periph: USARTx(x=0,1) + \param[in] oversamp: oversample value + only one parameter can be selected which is shown as below: + \arg USART_OVSMOD_8: oversampling by 8 + \arg USART_OVSMOD_16: oversampling by 16 + \param[out] none + \retval none +*/ +void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* clear OVSMOD bit */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_OVSMOD); + USART_CTL0(usart_periph) |= oversamp; +} + +/*! + \brief configure the sample bit method + \param[in] usart_periph: USARTx(x=0,1) + \param[in] osb: sample bit + only one parameter can be selected which is shown as below: + \arg USART_OSB_1BIT: 1 bit + \arg USART_OSB_3BIT: 3 bits + \param[out] none + \retval none +*/ +void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB); + USART_CTL2(usart_periph) |= osb; +} + +/*! + \brief enable receiver timeout + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_receiver_timeout_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_RTEN; +} + +/*! + \brief disable receiver timeout + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_receiver_timeout_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_RTEN); +} + +/*! + \brief configure receiver timeout threshold + \param[in] usart_periph: USARTx(x=0) + \param[in] rtimeout: 0x00000000-0x00FFFFFF, receiver timeout value in terms of number of baud clocks + \param[out] none + \retval none +*/ +void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout) +{ + USART_RT(usart_periph) &= ~(USART_RT_RT); + USART_RT(usart_periph) |= rtimeout; +} + +/*! + \brief USART transmit data function + \param[in] usart_periph: USARTx(x=0,1) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void usart_data_transmit(uint32_t usart_periph, uint32_t data) +{ + USART_TDATA(usart_periph) = (USART_TDATA_TDATA & data); +} + +/*! + \brief USART receive data function + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval data of received +*/ +uint16_t usart_data_receive(uint32_t usart_periph) +{ + return (uint16_t)(GET_BITS(USART_RDATA(usart_periph), 0U, 8U)); +} + +/*! + \brief enable auto baud rate detection + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_autobaud_detection_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_ABDEN; +} + +/*! + \brief disable auto baud rate detection + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_autobaud_detection_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDEN); +} + +/*! + \brief configure auto baud rate detection mode + \param[in] usart_periph: USARTx(x=0) + \param[in] abdmod: auto baud rate detection mode + only one parameter can be selected which is shown as below: + \arg USART_ABDM_FTOR: falling edge to rising edge measurement + \arg USART_ABDM_FTOF: falling edge to falling edge measurement + \param[out] none + \retval none +*/ +void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod) +{ + /* reset ABDM bits */ + USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDM); + USART_CTL1(usart_periph) |= abdmod; +} + +/*! + \brief address of the USART terminal + \param[in] usart_periph: USARTx(x=0,1) + \param[in] addr: 0x00-0xFF, address of USART terminal + \param[out] none + \retval none +*/ +void usart_address_config(uint32_t usart_periph, uint8_t addr) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); + USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (((uint32_t)addr) << CTL1_ADDR_OFFSET)); +} + +/*! + \brief configure the address of the USART in wake up by address match mode + \param[in] usart_periph: USARTx(x=0,1) + \param[in] addmod: address detection mode + only one parameter can be selected which is shown as below: + \arg USART_ADDM_4BIT: 4 bits + \arg USART_ADDM_FULLBIT: full bits + \param[out] none + \retval none +*/ +void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDM); + USART_CTL1(usart_periph) |= USART_CTL1_ADDM & (addmod); +} + +/*! + \brief enable mute mode + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_mute_mode_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_MEN; +} + +/*! + \brief disable mute mode + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_mute_mode_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_MEN); +} + +/*! + \brief configure wakeup method in mute mode + \param[in] usart_periph: USARTx(x=0,1) + \param[in] wmethod: two methods be used to enter or exit the mute mode + only one parameter can be selected which is shown as below: + \arg USART_WM_IDLE: idle line + \arg USART_WM_ADDR: address mark + \param[out] none + \retval none +*/ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); + USART_CTL0(usart_periph) |= wmethod; +} + +/*! + \brief enable LIN mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_lin_mode_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) |= USART_CTL1_LMEN; +} + +/*! + \brief disable LIN mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_lin_mode_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); +} + +/*! + \brief configure LIN break frame length + \param[in] usart_periph: USARTx(x=0) + \param[in] lblen: LIN break detection length + only one parameter can be selected which is shown as below: + \arg USART_LBLEN_10B: 10 bits break detection + \arg USART_LBLEN_11B: 11 bits break detection + \param[out] none + \retval none +*/ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); + USART_CTL1(usart_periph) |= USART_CTL1_LBLEN & (lblen); +} + +/*! + \brief enable half-duplex mode + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_halfduplex_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_HDEN; +} + +/*! + \brief disable half-duplex mode + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_halfduplex_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); +} + +/*! + \brief enable USART clock + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_clock_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) |= USART_CTL1_CKEN; +} + +/*! + \brief disable USART clock + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_clock_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); +} + +/*! + \brief configure USART synchronous mode parameters + \param[in] usart_periph: USARTx(x=0,1) + \param[in] clen: last bit clock pulse + only one parameter can be selected which is shown as below: + \arg USART_CLEN_NONE: clock pulse of the last data bit (MSB) is not output to the CK pin + \arg USART_CLEN_EN: clock pulse of the last data bit (MSB) is output to the CK pin + \param[in] cph: clock phase + only one parameter can be selected which is shown as below: + \arg USART_CPH_1CK: first clock transition is the first data capture edge + \arg USART_CPH_2CK: second clock transition is the first data capture edge + \param[in] cpl: clock polarity + only one parameter can be selected which is shown as below: + \arg USART_CPL_LOW: steady low value on CK pin + \arg USART_CPL_HIGH: steady high value on CK pin + \param[out] none + \retval none +*/ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* reset USART_CTL1 CLEN,CPH,CPL bits */ + USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); + + USART_CTL1(usart_periph) |= (USART_CTL1_CLEN & clen); + USART_CTL1(usart_periph) |= (USART_CTL1_CPH & cph); + USART_CTL1(usart_periph) |= (USART_CTL1_CPL & cpl); +} + +/*! + \brief configure guard time value in smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[in] guat: 0x00-0xFF + \param[out] none + \retval none +*/ +void usart_guard_time_config(uint32_t usart_periph, uint32_t guat) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_GP(usart_periph) &= ~(USART_GP_GUAT); + USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << GP_GUAT_OFFSET)); +} + +/*! + \brief enable smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_SCEN; +} + +/*! + \brief disable smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); +} + +/*! + \brief enable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_NKEN; +} + +/*! + \brief disable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); +} + +/*! + \brief enable early NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph) +{ + USART_RFCS(usart_periph) |= USART_RFCS_ELNACK; +} + +/*! + \brief disable early NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph) +{ + USART_RFCS(usart_periph) &= ~USART_RFCS_ELNACK; +} + +/*! + \brief configure smartcard auto-retry number + \param[in] usart_periph: USARTx(x=0) + \param[in] scrtnum: 0x00000000-0x00000007, smartcard auto-retry number + \param[out] none + \retval none +*/ +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + USART_CTL2(usart_periph) &= ~(USART_CTL2_SCRTNUM); + USART_CTL2(usart_periph) |= (USART_CTL2_SCRTNUM & (scrtnum << CTL2_SCRTNUM_OFFSET)); +} + +/*! + \brief configure block length + \param[in] usart_periph: USARTx(x=0) + \param[in] bl: 0x00000000-0x000000FF + \param[out] none + \retval none +*/ +void usart_block_length_config(uint32_t usart_periph, uint32_t bl) +{ + USART_RT(usart_periph) &= ~(USART_RT_BL); + USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << RT_BL_OFFSET)); +} + +/*! + \brief enable IrDA mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_irda_mode_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_IREN; +} + +/*! + \brief disable IrDA mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_irda_mode_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); +} + +/*! + \brief configure the peripheral clock prescaler in USART IrDA low-power or SmartCard mode + \param[in] usart_periph: USARTx(x=0) + \param[in] psc: 0x00000000-0x000000FF + \param[out] none + \retval none +*/ +void usart_prescaler_config(uint32_t usart_periph, uint32_t psc) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + USART_GP(usart_periph) &= ~(USART_GP_PSC); + USART_GP(usart_periph) |= psc; +} + +/*! + \brief configure IrDA low-power + \param[in] usart_periph: USARTx(x=0) + \param[in] irlp: IrDA low-power or normal + only one parameter can be selected which is shown as below: + \arg USART_IRLP_LOW: low-power + \arg USART_IRLP_NORMAL: normal + \param[out] none + \retval none +*/ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); + USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); +} + +/*! + \brief configure hardware flow control RTS + \param[in] usart_periph: USARTx(x=0,1) + \param[in] rtsconfig: enable or disable RTS + only one parameter can be selected which is shown as below: + \arg USART_RTS_ENABLE: enable RTS + \arg USART_RTS_DISABLE: disable RTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_RTSEN); + USART_CTL2(usart_periph) |= rtsconfig; +} + +/*! + \brief configure hardware flow control CTS + \param[in] usart_periph: USARTx(x=0,1) + \param[in] ctsconfig: enable or disable CTS + only one parameter can be selected which is shown as below: + \arg USART_CTS_ENABLE: enable CTS + \arg USART_CTS_DISABLE: disable CTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~USART_CTL2_CTSEN; + USART_CTL2(usart_periph) |= ctsconfig; +} + +/*! + \brief enable RS485 driver + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_rs485_driver_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_DEM; +} + +/*! + \brief disable RS485 driver + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_rs485_driver_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_DEM); +} + +/*! + \brief configure driver enable assertion time + \param[in] usart_periph: USARTx(x=0,1) + \param[in] deatime: 0x00000000-0x0000001F + \param[out] none + \retval none +*/ +void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL0(usart_periph) &= ~(USART_CTL0_DEA); + USART_CTL0(usart_periph) |= (USART_CTL0_DEA & ((deatime) << CTL0_DEA_OFFSET)); +} + +/*! + \brief configure driver enable de-assertion time + \param[in] usart_periph: USARTx(x=0,1) + \param[in] dedtime: 0x00000000-0x0000001F + \param[out] none + \retval none +*/ +void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL0(usart_periph) &= ~(USART_CTL0_DED); + USART_CTL0(usart_periph) |= (USART_CTL0_DED & ((dedtime) << CTL0_DED_OFFSET)); +} + +/*! + \brief configure driver enable polarity mode + \param[in] usart_periph: USARTx(x=0,1) + \param[in] dep: DE signal + only one parameter can be selected which is shown as below: + \arg USART_DEP_HIGH: DE signal is active high + \arg USART_DEP_LOW: DE signal is active low + \param[out] none + \retval none +*/ +void usart_depolarity_config(uint32_t usart_periph, uint32_t dep) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* reset DEP bit */ + USART_CTL2(usart_periph) &= ~(USART_CTL2_DEP); + USART_CTL2(usart_periph) |= (USART_CTL2_DEP & dep); +} + +/*! + \brief configure USART DMA reception + \param[in] usart_periph: USARTx(x=0,1) + \param[in] dmacmd: enable or disable DMA for reception + only one parameter can be selected which is shown as below: + \arg USART_DENR_ENABLE: DMA enable for reception + \arg USART_DENR_DISABLE: DMA disable for reception + \param[out] none + \retval none +*/ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) +{ + USART_CTL2(usart_periph) &= ~USART_CTL2_DENR; + /* configure DMA reception */ + USART_CTL2(usart_periph) |= dmacmd; +} + +/*! + \brief configure USART DMA transmission + \param[in] usart_periph: USARTx(x=0,1) + \param[in] dmacmd: enable or disable DMA for transmission + only one parameter can be selected which is shown as below: + \arg USART_DENT_ENABLE: DMA enable for transmission + \arg USART_DENT_DISABLE: DMA disable for transmission + \param[out] none + \retval none +*/ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) +{ + USART_CTL2(usart_periph) &= ~USART_CTL2_DENT; + /* configure DMA transmission */ + USART_CTL2(usart_periph) |= dmacmd; +} + +/*! + \brief disable DMA on reception error + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_reception_error_dma_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_DDRE; +} + +/*! + \brief enable DMA on reception error + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_reception_error_dma_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_DDRE); +} + +/*! + \brief enable USART to wakeup the mcu from deep-sleep mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_wakeup_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_UESM; +} + +/*! + \brief disable USART to wakeup the mcu from deep-sleep mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_wakeup_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UESM); +} + +/*! + \brief configure the USART wakeup mode from deep-sleep mode + \param[in] usart_periph: USARTx(x=0) + \param[in] wum: wakeup mode + only one parameter can be selected which is shown as below: + \arg USART_WUM_ADDR: WUF active on address match + \arg USART_WUM_STARTB: WUF active on start bit + \arg USART_WUM_RBNE: WUF active on RBNE + \param[out] none + \retval none +*/ +void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* reset WUM bit */ + USART_CTL2(usart_periph) &= ~(USART_CTL2_WUM); + USART_CTL2(usart_periph) |= USART_CTL2_WUM & (wum); +} + +/*! + \brief enable USART command + \param[in] usart_periph: USARTx(x=0,1) + \param[in] cmdtype: command type + only one parameter can be selected which is shown as below: + \arg USART_CMD_ABDCMD: auto baudrate detection command + \arg USART_CMD_SBKCMD: send break command + \arg USART_CMD_MMCMD: mute mode command + \arg USART_CMD_RXFCMD: receive data flush command + \arg USART_CMD_TXFCMD: transmit data flush request + \param[out] none + \retval none +*/ +void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype) +{ + USART_CMD(usart_periph) |= (cmdtype); +} + +/*! + \brief enable receive FIFO + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_receive_fifo_enable(uint32_t usart_periph) +{ + USART_RFCS(usart_periph) |= USART_RFCS_RFEN; +} + +/*! + \brief disable receive FIFO + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_receive_fifo_disable(uint32_t usart_periph) +{ + USART_RFCS(usart_periph) &= ~(USART_RFCS_RFEN); +} + +/*! + \brief read receive FIFO counter number + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval receive FIFO counter number +*/ +uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph) +{ + return (uint8_t)(GET_BITS(USART_RFCS(usart_periph), 12U, 14U)); +} + +/*! + \brief get flag in STAT/CHC/RFCS register + \param[in] usart_periph: USARTx(x=0,1) + \param[in] flag: flag type + only one parameter can be selected which is shown as below: + \arg USART_FLAG_PERR: parity error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_NERR: noise error flag + \arg USART_FLAG_ORERR: overrun error + \arg USART_FLAG_IDLE: idle line detected flag + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_TC: transmission completed + \arg USART_FLAG_TBE: transmit data register empty + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_CTSF: CTS change flag + \arg USART_FLAG_CTS: CTS level + \arg USART_FLAG_RT: receiver timeout flag + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_ABDE: auto baudrate detection error + \arg USART_FLAG_ABD: auto baudrate detection flag + \arg USART_FLAG_BSY: busy flag + \arg USART_FLAG_AM: address match flag + \arg USART_FLAG_SB: send break flag + \arg USART_FLAG_RWU: receiver wakeup from mute mode. + \arg USART_FLAG_WU: wakeup from deep-sleep mode flag + \arg USART_FLAG_TEA: transmit enable acknowledge flag + \arg USART_FLAG_REA: receive enable acknowledge flag + \arg USART_FLAG_EPERR: early parity error flag + \arg USART_FLAG_RFE: receive FIFO empty flag + \arg USART_FLAG_RFF: receive FIFO full flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) +{ + if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear USART status + \param[in] usart_periph: USARTx(x=0,1) + \param[in] flag: flag type + only one parameter can be selected which is shown as below: + \arg USART_FLAG_PERR: parity error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_NERR: noise detected flag + \arg USART_FLAG_ORERR: overrun error flag + \arg USART_FLAG_IDLE: idle line detected flag + \arg USART_FLAG_TC: transmission complete flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_CTSF: CTS change flag + \arg USART_FLAG_RT: receiver timeout flag + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_AM: address match flag + \arg USART_FLAG_WU: wakeup from deep-sleep mode flag + \arg USART_FLAG_EPERR: early parity error flag + \param[out] none + \retval none +*/ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) +{ + USART_INTC(usart_periph) |= BIT(USART_BIT_POS(flag)); +} + +/*! + \brief enable USART interrupt + \param[in] usart_periph: USARTx(x=0,1) + \param[in] interrupt: interrupt + only one parameter can be selected which is shown as below: + \arg USART_INT_IDLE: idle interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and + overrun error interrupt enable interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_TBE: transmit data register empty interrupt + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_AM: address match interrupt + \arg USART_INT_RT: receiver timeout interrupt + \arg USART_INT_EB: end of block interrupt + \arg USART_INT_LBD: LIN break detection interrupt + \arg USART_INT_ERR: error interrupt enable in multibuffer communication + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_WU: wakeup from deep-sleep mode interrupt + \arg USART_INT_RFF: receive FIFO full interrupt enable + \param[out] none + \retval none +*/ +void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt) +{ + USART_REG_VAL(usart_periph, interrupt) |= BIT(USART_BIT_POS(interrupt)); +} + +/*! + \brief disable USART interrupt + \param[in] usart_periph: USARTx(x=0,1) + \param[in] interrupt: interrupt + only one parameter can be selected which is shown as below: + \arg USART_INT_IDLE: idle interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and + overrun error interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_TBE: transmit data register empty interrupt + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_AM: address match interrupt + \arg USART_INT_RT: receiver timeout interrupt + \arg USART_INT_EB: end of block interrupt + \arg USART_INT_LBD: LIN break detection interrupt + \arg USART_INT_ERR: error interrupt enable in multibuffer communication + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_WU: wakeup from deep-sleep mode interrupt + \arg USART_INT_RFF: receive FIFO full interrupt enable + \param[out] none + \retval none +*/ +void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt) +{ + USART_REG_VAL(usart_periph, interrupt) &= ~BIT(USART_BIT_POS(interrupt)); +} + +/*! + \brief get USART interrupt and flag status + \param[in] usart_periph: USARTx(x=0,1) + \param[in] int_flag: interrupt and flag type, refer to usart_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_EB: end of block interrupt and interrupt flag + \arg USART_INT_FLAG_RT: receiver timeout interrupt flag + \arg USART_INT_FLAG_AM: address match interrupt flag + \arg USART_INT_FLAG_PERR: parity error interrupt flag + \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt flag + \arg USART_INT_FLAG_TC: transmission complete interrupt flag + \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt flag + \arg USART_INT_FLAG_RBNE_ORERR: overrun error interrupt flag + \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt flag + \arg USART_INT_FLAG_LBD: LIN break detected interrupt flag + \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode interrupt flag + \arg USART_INT_FLAG_CTS: CTS interrupt flag + \arg USART_INT_FLAG_ERR_NERR: noise error interrupt flag + \arg USART_INT_FLAG_ERR_ORERR: overrun error interrupt flag + \arg USART_INT_FLAG_ERR_FERR: frame error interrupt flag + \arg USART_INT_FLAG_RFFINT: receive FIFO full interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U; + /* get the interrupt enable bit status */ + intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); + + if(flagstatus && intenable) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear USART interrupt flag + \param[in] usart_periph: USARTx(x=0,1) + \param[in] flag: USART interrupt flag + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_PERR: parity error interrupt flag + \arg USART_INT_FLAG_ERR_FERR: frame error interrupt flag + \arg USART_INT_FLAG_ERR_NERR: noise detected interrupt flag + \arg USART_INT_FLAG_RBNE_ORERR: overrun error interrupt flag + \arg USART_INT_FLAG_ERR_ORERR: overrun error interrupt flag + \arg USART_INT_FLAG_IDLE: idle line detected interrupt flag + \arg USART_INT_FLAG_TC: transmission complete interrupt flag + \arg USART_INT_FLAG_LBD: LIN break detected interrupt flag + \arg USART_INT_FLAG_CTS: CTS change interrupt flag + \arg USART_INT_FLAG_RT: receiver timeout interrupt flag + \arg USART_INT_FLAG_EB: end of block interrupt flag + \arg USART_INT_FLAG_AM: address match interrupt flag + \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode interrupt flag + \arg USART_INT_FLAG_RFFINT: receive FIFO full interrupt flag + \param[out] none + \retval none +*/ +void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) +{ + if(USART_INT_FLAG_RFFINT == int_flag) { + USART_RFCS(usart_periph) &= (uint32_t)(~USART_RFCS_RFFINT); + } else { + USART_INTC(usart_periph) |= BIT(USART_BIT_POS2(int_flag)); + } +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_wwdgt.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_wwdgt.c new file mode 100644 index 000000000..e5feebcbe --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_standard_peripheral/Source/gd32f3x0_wwdgt.c @@ -0,0 +1,128 @@ +/*! + \file gd32f3x0_wwdgt.c + \brief WWDGT driver + + \version 2017-06-06, V1.0.0, firmware for GD32F3x0 + \version 2019-06-01, V2.0.0, firmware for GD32F3x0 + \version 2020-09-30, V2.1.0, firmware for GD32F3x0 + \version 2022-01-06, V2.2.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2022, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32f3x0_wwdgt.h" +#include "gd32f3x0_rcu.h" + +/*! + \brief reset the window watchdog timer configuration + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_deinit(void) +{ + rcu_periph_reset_enable(RCU_WWDGTRST); + rcu_periph_reset_disable(RCU_WWDGTRST); +} + +/*! + \brief start the window watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_enable(void) +{ + WWDGT_CTL |= WWDGT_CTL_WDGTEN; +} + +/*! + \brief configure the window watchdog timer counter value + \param[in] counter_value: 0x00 - 0x7F + \param[out] none + \retval none +*/ +void wwdgt_counter_update(uint16_t counter_value) +{ + WWDGT_CTL = (uint32_t)(CTL_CNT(counter_value)); +} + +/*! + \brief configure counter value, window value, and prescaler divider value + \param[in] counter: 0x00 - 0x7F + \param[in] window: 0x00 - 0x7F + \param[in] prescaler: wwdgt prescaler value + only one parameter can be selected which is shown as below: + \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 + \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 + \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 + \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 + \param[out] none + \retval none +*/ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) +{ + WWDGT_CTL = (uint32_t)(CTL_CNT(counter)); + WWDGT_CFG = (uint32_t)(CFG_WIN(window) | prescaler); +} + +/*! + \brief enable early wakeup interrupt of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_interrupt_enable(void) +{ + WWDGT_CFG |= WWDGT_CFG_EWIE; +} + +/*! + \brief check early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus wwdgt_flag_get(void) +{ + if(WWDGT_STAT & WWDGT_STAT_EWIF) { + return SET; + } + return RESET; +} + +/*! + \brief clear early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_flag_clear(void) +{ + WWDGT_STAT = (uint32_t)(RESET); +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/audio/Include/audio_core.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/audio/Include/audio_core.h new file mode 100644 index 000000000..986e1c6f5 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/audio/Include/audio_core.h @@ -0,0 +1,288 @@ +/*! + \file audio_core.h + \brief the header file of USB audio device class core functions + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __AUDIO_CORE_H +#define __AUDIO_CORE_H + +#include "usbd_enum.h" + +#define FORMAT_24BIT(x) (uint8_t)(x);(uint8_t)(x >> 8U);(uint8_t)(x >> 16U) + +/* number of sub-packets in the audio transfer buffer. you can modify this value but always make sure + that it is an even number and higher than 3 */ +#define OUT_PACKET_NUM 4U + +/* total size of the audio transfer buffer */ +#define OUT_BUF_MARGIN 4U +#define TOTAL_OUT_BUF_SIZE ((uint32_t)((SPEAKER_OUT_PACKET + OUT_BUF_MARGIN) * OUT_PACKET_NUM)) + +#define AUDIO_CONFIG_DESC_SET_LEN (sizeof(usb_desc_config_set)) +#define AUDIO_INTERFACE_DESC_SIZE 9U + +#define USB_AUDIO_DESC_SIZ 0x09U +#define AUDIO_STANDARD_EP_DESC_SIZE 0x09U +#define AUDIO_STREAMING_EP_DESC_SIZE 0x07U + +/* audio interface class code */ +#define USB_CLASS_AUDIO 0x01U + +/* audio interface subclass codes */ +#define AUDIO_SUBCLASS_CONTROL 0x01U +#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02U +#define AUDIO_SUBCLASS_MIDISTREAMING 0x03U + +/* audio interface protocol codes */ +#define AUDIO_PROTOCOL_UNDEFINED 0x00U +#define AUDIO_STREAMING_GENERAL 0x01U +#define AUDIO_STREAMING_FORMAT_TYPE 0x02U + +/* audio class-specific descriptor types */ +#define AUDIO_DESCTYPE_UNDEFINED 0x20U +#define AUDIO_DESCTYPE_DEVICE 0x21U +#define AUDIO_DESCTYPE_CONFIGURATION 0x22U +#define AUDIO_DESCTYPE_STRING 0x23U +#define AUDIO_DESCTYPE_INTERFACE 0x24U +#define AUDIO_DESCTYPE_ENDPOINT 0x25U + +/* audio control interface descriptor subtypes */ +#define AUDIO_CONTROL_HEADER 0x01U +#define AUDIO_CONTROL_INPUT_TERMINAL 0x02U +#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03U +#define AUDIO_CONTROL_MIXER_UNIT 0x04U +#define AUDIO_CONTROL_SELECTOR_UNIT 0x05U +#define AUDIO_CONTROL_FEATURE_UNIT 0x06U +#define AUDIO_CONTROL_PROCESSING_UNIT 0x07U +#define AUDIO_CONTROL_EXTENSION_UNIT 0x08U + +#define AUDIO_INPUT_TERMINAL_DESC_SIZE 0x0CU +#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE 0x09U +#define AUDIO_STREAMING_INTERFACE_DESC_SIZE 0x07U + +#define AUDIO_CONTROL_MUTE 0x01U +#define AUDIO_CONTROL_VOLUME 0x02U + +#define AUDIO_FORMAT_TYPE_I 0x01U +#define AUDIO_FORMAT_TYPE_III 0x03U + +#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01U +#define AUDIO_ENDPOINT_GENERAL 0x01U + +#define AUDIO_REQ_UNDEFINED 0x00U +#define AUDIO_REQ_SET_CUR 0x01U +#define AUDIO_REQ_GET_CUR 0x81U +#define AUDIO_REQ_SET_MIN 0x02U +#define AUDIO_REQ_GET_MIN 0x82U +#define AUDIO_REQ_SET_MAX 0x03U +#define AUDIO_REQ_GET_MAX 0x83U +#define AUDIO_REQ_SET_RES 0x04U +#define AUDIO_REQ_GET_RES 0x84U +#define AUDIO_REQ_SET_MEM 0x05U +#define AUDIO_REQ_GET_MEM 0x85U +#define AUDIO_REQ_GET_STAT 0xFFU + +#define AUDIO_OUT_STREAMING_CTRL 0x05U +#define AUDIO_IN_STREAMING_CTRL 0x02U + +/* audio stream interface number */ +enum { +#ifdef USE_USB_AUDIO_MICPHONE + MIC_INTERFACE_COUNT, +#endif +#ifdef USE_USB_AUDIO_SPEAKER + SPEAK_INTERFACE_COUNT, +#endif + CONFIG_DESC_AS_ITF_COUNT, +}; + +#define AC_ITF_TOTAL_LEN (sizeof(usb_desc_AC_itf) + CONFIG_DESC_AS_ITF_COUNT*(sizeof(usb_desc_input_terminal) + \ + sizeof(usb_desc_mono_feature_unit) + sizeof(usb_desc_output_terminal))) + +#pragma pack(1) + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bDescriptorSubtype; /*!< header descriptor subtype */ + uint16_t bcdADC; /*!< audio device class specification release number in binary-coded decimal */ + uint16_t wTotalLength; /*!< total number of bytes */ + uint8_t bInCollection; /*!< the number of the streaming interfaces */ +#ifdef USE_USB_AUDIO_MICPHONE + uint8_t baInterfaceNr0; /*!< interface number of the streaming interfaces */ +#endif + +#ifdef USE_USB_AUDIO_SPEAKER + uint8_t baInterfaceNr1; /*!< interface number of the streaming interfaces */ +#endif +} usb_desc_AC_itf; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bDescriptorSubtype; /*!< AS_GENERAL descriptor subtype */ + uint8_t bTerminalLink; /*!< the terminal ID */ + uint8_t bDelay; /*!< delay introduced by the data path */ + uint16_t wFormatTag; /*!< the audio data format */ +} usb_desc_AS_itf; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bDescriptorSubtype; /*!< INPUT_TERMINAL descriptor subtype. */ + uint8_t bTerminalID; /*!< constant uniquely identifying the terminal within the audio function */ + uint16_t wTerminalType; /*!< constant characterizing the type of terminal */ + uint8_t bAssocTerminal; /*!< ID of the output terminal */ + uint8_t bNrChannels; /*!< number of logical output channels */ + uint16_t wChannelConfig; /*!< describes the spatial location of the logical channels */ + uint8_t iChannelNames; /*!< index of a string descriptor */ + uint8_t iTerminal; /*!< index of a string descriptor */ +} usb_desc_input_terminal; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bDescriptorSubtype; /*!< OUTPUT_TERMINAL descriptor subtype */ + uint8_t bTerminalID; /*!< constant uniquely identifying the terminal within the audio function */ + uint16_t wTerminalType; /*!< constant characterizing the type of terminal */ + uint8_t bAssocTerminal; /*!< constant, identifying the input terminal to which this output terminal is associated */ + uint8_t bSourceID; /*!< ID of the unit or terminal */ + uint8_t iTerminal; /*!< index of a string descriptor */ +} usb_desc_output_terminal; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bDescriptorSubtype; /*!< FEATURE_UNIT descriptor subtype */ + uint8_t bUnitID; /*!< constant uniquely identifying the unit within the audio function */ + uint8_t bSourceID; /*!< ID of the unit or terminal */ + uint8_t bControlSize; /*!< size in bytes of an element of the bmaControls() array */ + uint8_t bmaControls0; /*!< a bit set to 1 indicates that the mentioned control is supported for master channel 0 */ + uint8_t bmaControls1; /*!< a bit set to 1 indicates that the mentioned control is supported for logical channel 1 */ + uint8_t iFeature; /*!< index of a string descriptor */ +} usb_desc_mono_feature_unit; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bDescriptorSubtype; /*!< FEATURE_UNIT descriptor subtype */ + uint8_t bUnitID; /*!< constant uniquely identifying the unit within the audio function */ + uint8_t bSourceID; /*!< ID of the unit or terminal */ + uint8_t bControlSize; /*!< size in bytes of an element of the bmaControls() array */ + uint16_t bmaControls0; /*!< a bit set to 1 indicates that the mentioned control is supported for master channel 0 */ + uint16_t bmaControls1; /*!< a bit set to 1 indicates that the mentioned control is supported for logical channel 1 */ + uint16_t bmaControls2; /*!< a bit set to 1 indicates that the mentioned control is supported for logical channel 2 */ + uint8_t iFeature; /*!< index of a string descriptor */ +} usb_desc_stereo_feature_unit; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bDescriptorSubtype; /*!< FORMAT_TYPE descriptor subtype */ + uint8_t bFormatType; /*!< constant identifying the format type */ + uint8_t bNrChannels; /*!< indicates the number of physical channels in the audio data stream */ + uint8_t bSubFrameSize; /*!< the number of bytes occupied by one audio subframe */ + uint8_t bBitResolution; /*!< the number of effectively used bits from the available bits in an audio subframe */ + uint8_t bSamFreqType; /*!< indicates how the sampling frequency can be programmed */ + uint8_t bSamFreq[3]; /*!< sampling frequency ns in Hz for this isochronous data endpoint */ +} usb_desc_format_type; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bEndpointAddress; /*!< the address of the endpoint */ + uint8_t bmAttributes; /*!< transfer type and synchronization type */ + uint16_t wMaxPacketSize; /*!< maximum packet size this endpoint is capable of sending or receiving */ + uint8_t bInterval; /*!< left to the designer's discretion */ + uint8_t bRefresh; /*!< reset to 0 */ + uint8_t bSynchAddress; /*!< reset to 0 */ +} usb_desc_std_ep; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bDescriptorSubtype; /*!< EP_GENERAL descriptor subtype */ + uint8_t bmAttributes; /*!< transfer type and synchronization type */ + uint8_t bLockDelayUnits; /*!< indicates the units used for the wLockDelay field */ + uint16_t wLockDelay; /*!< indicates the time it takes this endpoint to reliably lock its internal clock recovery circuitry */ +} usb_desc_AS_ep; + +#pragma pack() + +/* USB configuration descriptor structure */ +typedef struct { + usb_desc_config config; + usb_desc_itf std_itf; + usb_desc_AC_itf ac_itf; + +#ifdef USE_USB_AUDIO_MICPHONE + usb_desc_input_terminal mic_in_terminal; + usb_desc_mono_feature_unit mic_feature_unit; + usb_desc_output_terminal mic_out_terminal; +#endif + +#ifdef USE_USB_AUDIO_SPEAKER + usb_desc_input_terminal speak_in_terminal; + usb_desc_mono_feature_unit speak_feature_unit; + usb_desc_output_terminal speak_out_terminal; +#endif + +#ifdef USE_USB_AUDIO_MICPHONE + usb_desc_itf mic_std_as_itf_zeroband; + usb_desc_itf mic_std_as_itf_opera; + usb_desc_AS_itf mic_as_itf; + usb_desc_format_type mic_format_typeI; + usb_desc_std_ep mic_std_endpoint; + usb_desc_AS_ep mic_as_endpoint; +#endif + +#ifdef USE_USB_AUDIO_SPEAKER + usb_desc_itf speak_std_as_itf_zeroband; + usb_desc_itf speak_std_as_itf_opera; + usb_desc_AS_itf speak_as_itf; + usb_desc_format_type speak_format_typeI; + usb_desc_std_ep speak_std_endpoint; + usb_desc_AS_ep speak_as_endpoint; +#endif +} usb_desc_config_set; + +typedef struct { + /* main buffer for audio data out transfers and its relative pointers */ + uint8_t isoc_out_buff[TOTAL_OUT_BUF_SIZE * 2U]; + uint8_t *isoc_out_wrptr; + uint8_t *isoc_out_rdptr; + + /* main buffer for audio control requests transfers and its relative variables */ + uint8_t audioctl[64]; + uint8_t audioctl_unit; + uint32_t audioctl_len; + +#ifdef USE_USB_AUDIO_SPEAKER + uint32_t play_flag; +#endif /* USE_USB_AUDIO_SPEAKER */ +} usbd_audio_handler; + +extern usb_desc audio_desc; +extern usb_class_core usbd_audio_cb; + +#endif /* __AUDIO_CORE_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/audio/Include/audio_out_itf.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/audio/Include/audio_out_itf.h new file mode 100644 index 000000000..8ef971fce --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/audio/Include/audio_out_itf.h @@ -0,0 +1,75 @@ +/*! + \file audio_out_itf.h + \brief audio OUT (playback) interface header file + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __AUDIO_OUT_ITF_H +#define __AUDIO_OUT_ITF_H + +#include "usbd_conf.h" + +/* audio commands enumeration */ +typedef enum { + AUDIO_CMD_PLAY = 1U, + AUDIO_CMD_PAUSE, + AUDIO_CMD_STOP, +} audio_cmd_enum; + +/* mute commands */ +#define AUDIO_MUTE 0x01U +#define AUDIO_UNMUTE 0x00U + +/* functions return value */ +#define AUDIO_OK 0x00U +#define AUDIO_FAIL 0xFFU + +/* audio machine states */ +#define AUDIO_STATE_INACTIVE 0x00U +#define AUDIO_STATE_ACTIVE 0x01U +#define AUDIO_STATE_PLAYING 0x02U +#define AUDIO_STATE_PAUSED 0x03U +#define AUDIO_STATE_STOPPED 0x04U +#define AUDIO_STATE_ERROR 0x05U + +typedef struct { + uint8_t (*audio_init)(uint32_t audio_freq, uint32_t volume, uint32_t options); + uint8_t (*audio_deinit)(uint32_t options); + uint8_t (*audio_cmd)(uint8_t *pbuf, uint32_t size, uint8_t cmd); + uint8_t (*audio_volume_ctl)(uint8_t vol); + uint8_t (*audio_mute_ctl)(uint8_t cmd); + uint8_t (*audio_periodic_tc)(uint8_t cmd); + uint8_t (*audio_state_get)(void); +} audio_fops_struct; + +extern audio_fops_struct audio_out_fops; + +#endif /* __AUDIO_OUT_ITF_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/audio/Source/audio_core.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/audio/Source/audio_core.c new file mode 100644 index 000000000..e262cfa6a --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/audio/Source/audio_core.c @@ -0,0 +1,803 @@ +/*! + \file audio_core.c + \brief USB audio device class core functions + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 + \version 2020-12-07, V3.0.1, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "audio_out_itf.h" +#include "audio_core.h" +#include + +#define USBD_VID 0x28E9U +#define USBD_PID 0x9574U + +#ifdef USE_USB_AUDIO_MICPHONE +extern volatile uint32_t count_data; +extern const char wavetestdata[]; +#define LENGTH_DATA (1747 * 32) +#endif + +/* local function prototypes ('static') */ +static uint8_t audio_init(usb_dev *udev, uint8_t config_index); +static uint8_t audio_deinit(usb_dev *udev, uint8_t config_index); +static uint8_t audio_req_handler(usb_dev *udev, usb_req *req); +static uint8_t audio_set_intf(usb_dev *udev, usb_req *req); +static uint8_t audio_ctlx_out(usb_dev *udev); +static uint8_t audio_data_in(usb_dev *udev, uint8_t ep_num); +static uint8_t audio_data_out(usb_dev *udev, uint8_t ep_num); +static uint8_t usbd_audio_sof(usb_dev *udev); + +usb_class_core usbd_audio_cb = { + .init = audio_init, + .deinit = audio_deinit, + .req_proc = audio_req_handler, + .set_intf = audio_set_intf, + .ctlx_out = audio_ctlx_out, + .data_in = audio_data_in, + .data_out = audio_data_out, + .SOF = usbd_audio_sof +}; + +#define VOL_MIN 0U /* Volume Minimum Value */ +#define VOL_MAX 100U /* Volume Maximum Value */ +#define VOL_RES 1U /* Volume Resolution */ +#define VOL_0dB 70U /* 0dB is in the middle of VOL_MIN and VOL_MAX */ + +/* note:it should use the c99 standard when compiling the below codes */ +/* USB standard device descriptor */ +const usb_desc_dev audio_dev_desc = { + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200U, + .bDeviceClass = 0x00U, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +/* USB device configuration descriptor */ +const usb_desc_config_set audio_config_set = { + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = AUDIO_CONFIG_DESC_SET_LEN, + .bNumInterfaces = 0x01U + CONFIG_DESC_AS_ITF_COUNT, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0xC0U, + .bMaxPower = 0x32U + }, + + .std_itf = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x00U, + .bInterfaceClass = USB_CLASS_AUDIO, + .bInterfaceSubClass = AUDIO_SUBCLASS_CONTROL, + .bInterfaceProtocol = AUDIO_PROTOCOL_UNDEFINED, + .iInterface = 0x00U + }, + + .ac_itf = + { + .header = + { + .bLength = sizeof(usb_desc_AC_itf), + .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = 0x01U, + .bcdADC = 0x0100U, + .wTotalLength = AC_ITF_TOTAL_LEN, + .bInCollection = CONFIG_DESC_AS_ITF_COUNT, +#ifdef USE_USB_AUDIO_MICPHONE + .baInterfaceNr0 = 0x01U, +#endif +#ifdef USE_USB_AUDIO_SPEAKER + .baInterfaceNr1 = 0x02U +#endif + }, + +#ifdef USE_USB_AUDIO_MICPHONE + .mic_in_terminal = + { + .header = + { + .bLength = sizeof(usb_desc_input_terminal), + .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = 0x02U, + .bTerminalID = 0x01U, + .wTerminalType = 0x0201U, + .bAssocTerminal = 0x00U, + .bNrChannels = 0x02U, + .wChannelConfig = 0x0003U, + .iChannelNames = 0x00U, + .iTerminal = 0x00U + }, + + .mic_feature_unit = + { + .header = + { + .bLength = sizeof(usb_desc_mono_feature_unit), + .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AUDIO_CONTROL_FEATURE_UNIT, + .bUnitID = AUDIO_IN_STREAMING_CTRL, + .bSourceID = 0x01U, + .bControlSize = 0x01U, + .bmaControls0 = AUDIO_CONTROL_MUTE, + .bmaControls1 = AUDIO_CONTROL_VOLUME, + .iFeature = 0x00U + }, + + .mic_out_terminal = + { + .header = + { + .bLength = sizeof(usb_desc_output_terminal), + .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AUDIO_CONTROL_OUTPUT_TERMINAL, + .bTerminalID = 0x03U, + .wTerminalType = 0x0101U, + .bAssocTerminal = 0x00U, + .bSourceID = 0x02U, + .iTerminal = 0x00U + }, +#endif + +#ifdef USE_USB_AUDIO_SPEAKER + .speak_in_terminal = + { + .header = + { + .bLength = sizeof(usb_desc_input_terminal), + .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AUDIO_CONTROL_INPUT_TERMINAL, + .bTerminalID = 0x04U, + .wTerminalType = 0x0101U, + .bAssocTerminal = 0x00U, + .bNrChannels = 0x02U, + .wChannelConfig = 0x0003U, + .iChannelNames = 0x00U, + .iTerminal = 0x00U + }, + + .speak_feature_unit = + { + .header = + { + .bLength = sizeof(usb_desc_mono_feature_unit), + .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AUDIO_CONTROL_FEATURE_UNIT, + .bUnitID = AUDIO_OUT_STREAMING_CTRL, + .bSourceID = 0x04U, + .bControlSize = 0x01U, + .bmaControls0 = AUDIO_CONTROL_MUTE, + .bmaControls1 = AUDIO_CONTROL_VOLUME, + .iFeature = 0x00U + }, + + .speak_out_terminal = + { + .header = + { + .bLength = sizeof(usb_desc_output_terminal), + .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AUDIO_CONTROL_OUTPUT_TERMINAL, + .bTerminalID = 0x06U, + .wTerminalType = 0x0301U, + .bAssocTerminal = 0x00U, + .bSourceID = 0x05U, + .iTerminal = 0x00U + }, +#endif + +#ifdef USE_USB_AUDIO_MICPHONE + .mic_std_as_itf_zeroband = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x01U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x00U, + .bInterfaceClass = USB_CLASS_AUDIO, + .bInterfaceSubClass = AUDIO_SUBCLASS_AUDIOSTREAMING, + .bInterfaceProtocol = AUDIO_PROTOCOL_UNDEFINED, + .iInterface = 0x00U + }, + + .mic_std_as_itf_opera = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x01U, + .bAlternateSetting = 0x01U, + .bNumEndpoints = 0x01U, + .bInterfaceClass = USB_CLASS_AUDIO, + .bInterfaceSubClass = AUDIO_SUBCLASS_AUDIOSTREAMING, + .bInterfaceProtocol = AUDIO_PROTOCOL_UNDEFINED, + .iInterface = 0x00U + }, + + .mic_as_itf = + { + .header = + { + .bLength = sizeof(usb_desc_AS_itf), + .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AUDIO_STREAMING_GENERAL, + .bTerminalLink = 0x03U, + .bDelay = 0x01U, + .wFormatTag = 0x0001U, + }, + + .mic_format_typeI = + { + .header = + { + .bLength = sizeof(usb_desc_format_type), + .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AUDIO_STREAMING_FORMAT_TYPE, + .bFormatType = AUDIO_FORMAT_TYPE_I, + .bNrChannels = MIC_IN_CHANNEL_NBR, + .bSubFrameSize = 0x02U, + .bBitResolution = MIC_IN_BIT_RESOLUTION, + .bSamFreqType = 0x01U, + .bSamFreq[0] = (uint8_t)USBD_MIC_FREQ, + .bSamFreq[1] = USBD_MIC_FREQ >> 8U, + .bSamFreq[2] = USBD_MIC_FREQ >> 16U + }, + + .mic_std_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_std_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = AUDIO_IN_EP, + .bmAttributes = USB_ENDPOINT_TYPE_ISOCHRONOUS, + .wMaxPacketSize = MIC_IN_PACKET, + .bInterval = 0x01U, + .bRefresh = 0x00U, + .bSynchAddress = 0x00U + }, + + .mic_as_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_AS_ep), + .bDescriptorType = AUDIO_DESCTYPE_ENDPOINT + }, + .bDescriptorSubtype = AUDIO_ENDPOINT_GENERAL, + .bmAttributes = 0x00U, + .bLockDelayUnits = 0x00U, + .wLockDelay = 0x0000U, + }, +#endif + +#ifdef USE_USB_AUDIO_SPEAKER + .speak_std_as_itf_zeroband = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x02U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x00U, + .bInterfaceClass = USB_CLASS_AUDIO, + .bInterfaceSubClass = AUDIO_SUBCLASS_AUDIOSTREAMING, + .bInterfaceProtocol = AUDIO_PROTOCOL_UNDEFINED, + .iInterface = 0x00U + }, + + .speak_std_as_itf_opera = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x02U, + .bAlternateSetting = 0x01U, + .bNumEndpoints = 0x01U, + .bInterfaceClass = USB_CLASS_AUDIO, + .bInterfaceSubClass = AUDIO_SUBCLASS_AUDIOSTREAMING, + .bInterfaceProtocol = AUDIO_PROTOCOL_UNDEFINED, + .iInterface = 0x00U + }, + + .speak_as_itf = + { + .header = + { + .bLength = sizeof(usb_desc_AS_itf), + .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AUDIO_STREAMING_GENERAL, + .bTerminalLink = 0x04U, + .bDelay = 0x01U, + .wFormatTag = 0x0001U, + }, + + .speak_format_typeI = + { + .header = + { + .bLength = sizeof(usb_desc_format_type), + .bDescriptorType = AUDIO_DESCTYPE_INTERFACE + }, + .bDescriptorSubtype = AUDIO_STREAMING_FORMAT_TYPE, + .bFormatType = AUDIO_FORMAT_TYPE_I, + .bNrChannels = SPEAKER_OUT_CHANNEL_NBR, + .bSubFrameSize = 0x02U, + .bBitResolution = SPEAKER_OUT_BIT_RESOLUTION, + .bSamFreqType = 0x01U, + .bSamFreq[0] = (uint8_t)USBD_SPEAKER_FREQ, + .bSamFreq[1] = USBD_SPEAKER_FREQ >> 8U, + .bSamFreq[2] = USBD_SPEAKER_FREQ >> 16U + }, + + .speak_std_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_std_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = AUDIO_OUT_EP, + .bmAttributes = USB_ENDPOINT_TYPE_ISOCHRONOUS, + .wMaxPacketSize = SPEAKER_OUT_PACKET, + .bInterval = 0x01U, + .bRefresh = 0x00U, + .bSynchAddress = 0x00U + }, + + .speak_as_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_AS_ep), + .bDescriptorType = AUDIO_DESCTYPE_ENDPOINT + }, + .bDescriptorSubtype = AUDIO_ENDPOINT_GENERAL, + .bmAttributes = 0x00U, + .bLockDelayUnits = 0x00U, + .wLockDelay = 0x0000U, + } +#endif +}; + +/* USB language ID descriptor */ +static const usb_desc_LANGID usbd_language_id_desc = { + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static const usb_desc_str manufacturer_string = { + .header = + { + .bLength = USB_STRING_LEN(10), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USB product string */ +static const usb_desc_str product_string = { + .header = + { + .bLength = USB_STRING_LEN(14), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'A', 'u', 'd', 'i', 'o'} +}; + +/* USBD serial string */ +static usb_desc_str serial_string = { + .header = + { + .bLength = USB_STRING_LEN(12), + .bDescriptorType = USB_DESCTYPE_STR, + } +}; + +/* USB string descriptor */ +void *const usbd_audio_strings[] = { + [STR_IDX_LANGID] = (uint8_t *) &usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *) &manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *) &product_string, + [STR_IDX_SERIAL] = (uint8_t *) &serial_string +}; + +usb_desc audio_desc = { + .dev_desc = (uint8_t *) &audio_dev_desc, + .config_desc = (uint8_t *) &audio_config_set, + .strings = usbd_audio_strings +}; + +/*! + \brief initialize the AUDIO device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_init(usb_dev *udev, uint8_t config_index) +{ + static usbd_audio_handler audio_handler; + + memset((void *)&audio_handler, 0, sizeof(usbd_audio_handler)); + +#ifdef USE_USB_AUDIO_MICPHONE + { + usb_desc_std_ep std_ep = audio_config_set.mic_std_endpoint; + + usb_desc_ep ep = { + .header = std_ep.header, + .bEndpointAddress = std_ep.bEndpointAddress, + .bmAttributes = std_ep.bmAttributes, + .wMaxPacketSize = std_ep.wMaxPacketSize, + .bInterval = std_ep.bInterval + }; + + /* initialize Tx endpoint */ + usbd_ep_setup(udev, &ep); + } +#endif + +#ifdef USE_USB_AUDIO_SPEAKER + { + audio_handler.isoc_out_rdptr = audio_handler.isoc_out_buff; + audio_handler.isoc_out_wrptr = audio_handler.isoc_out_buff; + + usb_desc_std_ep std_ep = audio_config_set.speak_std_endpoint; + + usb_desc_ep ep = { + .header = std_ep.header, + .bEndpointAddress = std_ep.bEndpointAddress, + .bmAttributes = std_ep.bmAttributes, + .wMaxPacketSize = std_ep.wMaxPacketSize, + .bInterval = std_ep.bInterval + }; + + /* initialize Rx endpoint */ + usbd_ep_setup(udev, &ep); + + /* initialize the audio output hardware layer */ + if(USBD_OK != audio_out_fops.audio_init(USBD_AUDIO_FREQ_16K, DEFAULT_VOLUME, 0U)) { + return USBD_FAIL; + } + + /* prepare OUT endpoint to receive audio data */ + usbd_ep_recev(udev, AUDIO_OUT_EP, (uint8_t *)audio_handler.isoc_out_buff, SPEAKER_OUT_PACKET); + } +#endif + + udev->dev.class_data[USBD_AUDIO_INTERFACE] = (void *)&audio_handler; + + return USBD_OK; +} + +/*! + \brief de-initialize the AUDIO device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_deinit(usb_dev *udev, uint8_t config_index) +{ +#ifdef USE_USB_AUDIO_MICPHONE + /* deinitialize AUDIO endpoints */ + usbd_ep_clear(udev, AUDIO_IN_EP); +#endif + +#ifdef USE_USB_AUDIO_SPEAKER + /* deinitialize AUDIO endpoints */ + usbd_ep_clear(udev, AUDIO_OUT_EP); + + /* deinitialize the audio output hardware layer */ + if(USBD_OK != audio_out_fops.audio_deinit(0U)) { + return USBD_FAIL; + } +#endif + + return USBD_OK; +} + +/*! + \brief handle the AUDIO class-specific requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_req_handler(usb_dev *udev, usb_req *req) +{ + uint8_t status = REQ_NOTSUPP; + + usbd_audio_handler *audio = (usbd_audio_handler *)udev->dev.class_data[USBD_AUDIO_INTERFACE]; + + usb_transc *transc_in = &udev->dev.transc_in[0]; + usb_transc *transc_out = &udev->dev.transc_out[0]; + + switch(req->bRequest) { + case AUDIO_REQ_GET_CUR: + transc_in->xfer_buf = audio->audioctl; + transc_in->remain_len = req->wLength; + + status = REQ_SUPP; + break; + + case AUDIO_REQ_SET_CUR: + if(req->wLength) { + transc_out->xfer_buf = audio->audioctl; + transc_out->remain_len = req->wLength; + + udev->dev.class_core->command = AUDIO_REQ_SET_CUR; + + audio->audioctl_len = req->wLength; + audio->audioctl_unit = BYTE_HIGH(req->wIndex); + + status = REQ_SUPP; + } + break; + + case AUDIO_REQ_GET_MIN: + *((uint16_t *)audio->audioctl) = VOL_MIN; + transc_in->xfer_buf = audio->audioctl; + transc_in->remain_len = req->wLength; + status = REQ_SUPP; + break; + + case AUDIO_REQ_GET_MAX: + *((uint16_t *)audio->audioctl) = VOL_MAX; + transc_in->xfer_buf = audio->audioctl; + transc_in->remain_len = req->wLength; + status = REQ_SUPP; + break; + + case AUDIO_REQ_GET_RES: + *((uint16_t *)audio->audioctl) = VOL_RES; + transc_in->xfer_buf = audio->audioctl; + transc_in->remain_len = req->wLength; + status = REQ_SUPP; + break; + + default: + break; + } + + return status; +} + +/*! + \brief handle the AUDIO set interface requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_set_intf(usb_dev *udev, usb_req *req) +{ + udev->dev.class_core->alter_set = req->wValue; + + return USBD_OK; +} + +/*! + \brief handles the control transfer OUT callback + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_ctlx_out(usb_dev *udev) +{ +#ifdef USE_USB_AUDIO_SPEAKER + usbd_audio_handler *audio = (usbd_audio_handler *)udev->dev.class_data[USBD_AUDIO_INTERFACE]; + + /* handles audio control requests data */ + /* check if an audio_control request has been issued */ + if(AUDIO_REQ_SET_CUR == udev->dev.class_core->command) { + /* in this driver, to simplify code, only SET_CUR request is managed */ + + /* check for which addressed unit the audio_control request has been issued */ + if(AUDIO_OUT_STREAMING_CTRL == audio->audioctl_unit) { + /* in this driver, to simplify code, only one unit is manage */ + + /* call the audio interface mute function */ + audio_out_fops.audio_mute_ctl(audio->audioctl[0]); + + /* reset the audioctl_cmd variable to prevent re-entering this function */ + udev->dev.class_core->command = 0U; + + audio->audioctl_len = 0U; + } + } +#endif + + return USBD_OK; +} + + +/*! + \brief handles the audio IN data stage + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_data_in(usb_dev *udev, uint8_t ep_num) +{ +#ifdef USE_USB_AUDIO_MICPHONE + if(count_data < LENGTH_DATA) { + /* Prepare next buffer to be sent: dummy data */ + usbd_ep_send(udev, AUDIO_IN_EP, (uint8_t *)&wavetestdata[count_data], MIC_IN_PACKET); + count_data += MIC_IN_PACKET; + } else { + usbd_ep_send(udev, AUDIO_IN_EP, (uint8_t *)wavetestdata, MIC_IN_PACKET); + count_data = MIC_IN_PACKET; + } +#endif + + return USBD_OK; +} + +/*! + \brief handles the audio OUT data stage + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval USB device operation status +*/ +static uint8_t audio_data_out(usb_dev *udev, uint8_t ep_num) +{ +#ifdef USE_USB_AUDIO_SPEAKER + usbd_audio_handler *audio = (usbd_audio_handler *)udev->dev.class_data[USBD_AUDIO_INTERFACE]; + + /* increment the Buffer pointer or roll it back when all buffers are full */ + if(audio->isoc_out_wrptr >= (audio->isoc_out_buff + (SPEAKER_OUT_PACKET * OUT_PACKET_NUM))) { + /* all buffers are full: roll back */ + audio->isoc_out_wrptr = audio->isoc_out_buff; + } else { + /* increment the buffer pointer */ + audio->isoc_out_wrptr += SPEAKER_OUT_PACKET; + } + + /* Toggle the frame index */ + udev->dev.transc_out[ep_num].frame_num = + (udev->dev.transc_out[ep_num].frame_num) ? 0U : 1U; + + /* prepare out endpoint to receive next audio packet */ + usbd_ep_recev(udev, AUDIO_OUT_EP, (uint8_t *)(audio->isoc_out_wrptr), SPEAKER_OUT_PACKET); + + /* trigger the start of streaming only when half buffer is full */ + if((0U == audio->play_flag) && (audio->isoc_out_wrptr >= (audio->isoc_out_buff + ((SPEAKER_OUT_PACKET * OUT_PACKET_NUM) / 2U)))) { + /* enable start of streaming */ + audio->play_flag = 1U; + } +#endif + + return USBD_OK; +} + +/*! + \brief handles the SOF event (data buffer update and synchronization) + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +static uint8_t usbd_audio_sof(usb_dev *udev) +{ +#ifdef USE_USB_AUDIO_SPEAKER + usbd_audio_handler *audio = (usbd_audio_handler *)udev->dev.class_data[USBD_AUDIO_INTERFACE]; + + /* check if there are available data in stream buffer. + in this function, a single variable (play_flag) is used to avoid software delays. + the play operation must be executed as soon as possible after the SOF detection. */ + if(audio->play_flag) { + /* start playing received packet */ + audio_out_fops.audio_cmd((uint8_t *)(audio->isoc_out_rdptr), /* samples buffer pointer */ + SPEAKER_OUT_PACKET, /* number of samples in Bytes */ + AUDIO_CMD_PLAY); /* command to be processed */ + + /* increment the Buffer pointer or roll it back when all buffers all full */ + if(audio->isoc_out_rdptr >= (audio->isoc_out_buff + (SPEAKER_OUT_PACKET * OUT_PACKET_NUM))) { + /* roll back to the start of buffer */ + audio->isoc_out_rdptr = audio->isoc_out_buff; + } else { + /* increment to the next sub-buffer */ + audio->isoc_out_rdptr += SPEAKER_OUT_PACKET; + } + + /* if all available buffers have been consumed, stop playing */ + if(audio->isoc_out_rdptr == audio->isoc_out_wrptr) { + /* Pause the audio stream */ + audio_out_fops.audio_cmd((uint8_t *)(audio->isoc_out_buff), /* samples buffer pointer */ + SPEAKER_OUT_PACKET, /* number of samples in Bytes */ + AUDIO_CMD_PAUSE); /* command to be processed */ + + /* stop entering play loop */ + audio->play_flag = 0U; + + /* reset buffer pointers */ + audio->isoc_out_rdptr = audio->isoc_out_buff; + audio->isoc_out_wrptr = audio->isoc_out_buff; + } + } +#endif + + return USBD_OK; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/audio/Source/audio_out_itf.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/audio/Source/audio_out_itf.c new file mode 100644 index 000000000..0752ef2e5 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/audio/Source/audio_out_itf.c @@ -0,0 +1,228 @@ +/*! + \file audio_out_itf.c + \brief audio OUT (playback) interface functions + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "audio_core.h" +#include "audio_out_itf.h" + +/* local function prototypes ('static') */ +static uint8_t init(uint32_t audiofreq, uint32_t volume, uint32_t options); +static uint8_t deinit(uint32_t options); +static uint8_t audio_cmd(uint8_t *pbuf, uint32_t size, uint8_t cmd); +static uint8_t volume_ctl(uint8_t vol); +static uint8_t mute_ctl(uint8_t cmd); +static uint8_t periodic_tc(uint8_t cmd); +static uint8_t get_state(void); + +audio_fops_struct audio_out_fops = { + init, + deinit, + audio_cmd, + volume_ctl, + mute_ctl, + periodic_tc, + get_state +}; + +static uint8_t audio_state = AUDIO_STATE_INACTIVE; + +/*! + \brief initialize and configures all required resources for audio play function + \param[in] audio_freq: statrt_up audio frequency + \param[in] volume: start_up volume to be set + \param[in] options: specific options passed to low layer function + \param[out] none + \retval AUDIO_OK if all operations succeed, AUDIO_FAIL else +*/ +static uint8_t init(uint32_t audio_freq, uint32_t volume, uint32_t options) +{ + static uint32_t initialized = 0U; + + /* check if the low layer has already been initialized */ + if(0U == initialized) { + /* call low layer function */ + if(0U != eval_audio_init(OUTPUT_DEVICE_AUTO, (uint8_t)volume, audio_freq)) { + audio_state = AUDIO_STATE_ERROR; + + return AUDIO_FAIL; + } + + /* set the initialization flag to prevent reinitializing the interface again */ + initialized = 1U; + } + + /* update the audio state machine */ + audio_state = AUDIO_STATE_ACTIVE; + + return AUDIO_OK; +} + +/*! + \brief free all resources used by low layer and stops audio-play function + \param[in] options: specific options passed to low layer function + \param[out] none + \retval AUDIO_OK if all operations succeed, AUDIO_FAIL else +*/ +static uint8_t deinit(uint32_t options) +{ + /* update the audio state machine */ + audio_state = AUDIO_STATE_INACTIVE; + + return AUDIO_OK; +} + +/*! + \brief play, stop, pause or resume current file + \param[in] pbuf: address from which file should be played + \param[in] size: size of the current buffer/file + \param[in] cmd: command to be executed, can be: + \arg AUDIO_CMD_PLAY + \arg AUDIO_CMD_PAUSE + \arg AUDIO_CMD_RESUME + \arg AUDIO_CMD_STOP + \param[out] none + \retval AUDIO_OK if all operations succeed, AUDIO_FAIL else +*/ +static uint8_t audio_cmd(uint8_t *pbuf, uint32_t size, uint8_t cmd) +{ + /* check the current state */ + if((AUDIO_STATE_INACTIVE == audio_state) || (AUDIO_STATE_ERROR == audio_state)) { + audio_state = AUDIO_STATE_ERROR; + + return AUDIO_FAIL; + } + + switch(cmd) { + /* process the play command */ + case AUDIO_CMD_PLAY: + /* if current state is active or stopped */ + if((AUDIO_STATE_ACTIVE == audio_state) || \ + (AUDIO_STATE_STOPPED == audio_state) || \ + (AUDIO_STATE_PLAYING == audio_state)) { + audio_mal_play((uint32_t)pbuf, size); + audio_state = AUDIO_STATE_PLAYING; + + return AUDIO_OK; + } else if(AUDIO_STATE_PAUSED == audio_state) { + if(eval_audio_pause_resume(AUDIO_RESUME, (uint32_t)pbuf, (size / 2U))) { + audio_state = AUDIO_STATE_ERROR; + + return AUDIO_FAIL; + } else { + audio_state = AUDIO_STATE_PLAYING; + + return AUDIO_OK; + } + } else { + return AUDIO_FAIL; + } + + /* process the stop command */ + case AUDIO_CMD_STOP: + if(AUDIO_STATE_PLAYING != audio_state) { + /* unsupported command */ + return AUDIO_FAIL; + } else if(eval_audio_stop(CODEC_PDWN_SW)) { + audio_state = AUDIO_STATE_ERROR; + + return AUDIO_FAIL; + } else { + audio_state = AUDIO_STATE_STOPPED; + + return AUDIO_OK; + } + + /* process the pause command */ + case AUDIO_CMD_PAUSE: + if(AUDIO_STATE_PLAYING != audio_state) { + /* unsupported command */ + return AUDIO_FAIL; + } else if(eval_audio_pause_resume(AUDIO_PAUSE, (uint32_t)pbuf, (size / 2U))) { + audio_state = AUDIO_STATE_ERROR; + + return AUDIO_FAIL; + } else { + audio_state = AUDIO_STATE_PAUSED; + + return AUDIO_OK; + } + + /* unsupported command */ + default: + return AUDIO_FAIL; + } +} + +/*! + \brief set the volume level + \param[in] vol: volume level to be set in % (from 0% to 100%) + \param[out] none + \retval AUDIO_OK if all operations succeed, AUDIO_FAIL else +*/ +static uint8_t volume_ctl(uint8_t vol) +{ + return AUDIO_OK; +} + +/*! + \brief mute or unmute the audio current output + \param[in] cmd: can be 0 to unmute, or 1 to mute + \param[out] none + \retval AUDIO_OK if all operations succeed, AUDIO_FAIL else +*/ +static uint8_t mute_ctl(uint8_t cmd) +{ + return AUDIO_OK; +} + +/*! + \brief periodic transfer control + \param[in] cmd: command + \param[out] none + \retval AUDIO_OK if all operations succeed, AUDIO_FAIL else +*/ +static uint8_t periodic_tc(uint8_t cmd) +{ + return AUDIO_OK; +} + +/*! + \brief return the current state of the audio machine + \param[in] none + \param[out] none + \retval AUDIO_OK if all operations succeed, AUDIO_FAIL else +*/ +static uint8_t get_state(void) +{ + return audio_state; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/cdc/Include/cdc_acm_core.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/cdc/Include/cdc_acm_core.h new file mode 100644 index 000000000..11828445e --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/cdc/Include/cdc_acm_core.h @@ -0,0 +1,66 @@ +/*! + \file cdc_acm_core.h + \brief the header file of cdc acm driver + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __CDC_ACM_CORE_H +#define __CDC_ACM_CORE_H + +#include "usbd_enum.h" +#include "usb_cdc.h" + +#define USB_CDC_RX_LEN 64 + +typedef struct { + uint8_t packet_sent; + uint8_t packet_receive; + + uint8_t data[USB_CDC_RX_LEN]; + uint8_t cmd[USB_CDC_CMD_PACKET_SIZE]; + + uint32_t receive_length; + + acm_line line_coding; +} usb_cdc_handler; + +extern usb_desc cdc_desc; +extern usb_class_core cdc_class; + +/* function declarations */ +/* check cdc acm is ready for data transfer */ +uint8_t cdc_acm_check_ready(usb_dev *udev); +/* send CDC ACM data */ +void cdc_acm_data_send(usb_dev *udev); +/* receive CDC ACM data */ +void cdc_acm_data_receive(usb_dev *udev); + +#endif /* __CDC_ACM_CORE_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/cdc/Source/cdc_acm_core.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/cdc/Source/cdc_acm_core.c new file mode 100644 index 000000000..92ae2324a --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/cdc/Source/cdc_acm_core.c @@ -0,0 +1,516 @@ +/*! + \file cdc_acm_core.c + \brief CDC ACM driver + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 + \version 2020-12-07, V3.0.1, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "cdc_acm_core.h" + +#define USBD_VID 0x28E9U +#define USBD_PID 0x018AU + +/* note:it should use the C99 standard when compiling the below codes */ +/* USB standard device descriptor */ +const usb_desc_dev cdc_dev_desc = { + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV, + }, + .bcdUSB = 0x0200U, + .bDeviceClass = USB_CLASS_CDC, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM, +}; + +/* USB device configuration descriptor */ +const usb_cdc_desc_config_set cdc_config_desc = { + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG, + }, + .wTotalLength = USB_CDC_ACM_CONFIG_DESC_SIZE, + .bNumInterfaces = 0x02U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0x80U, + .bMaxPower = 0x32U + }, + + .cmd_itf = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x01U, + .bInterfaceClass = USB_CLASS_CDC, + .bInterfaceSubClass = USB_CDC_SUBCLASS_ACM, + .bInterfaceProtocol = USB_CDC_PROTOCOL_AT, + .iInterface = 0x00U + }, + + .cdc_header = + { + .header = + { + .bLength = sizeof(usb_desc_header_func), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x00U, + .bcdCDC = 0x0110U + }, + + .cdc_call_managment = + { + .header = + { + .bLength = sizeof(usb_desc_call_managment_func), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x01U, + .bmCapabilities = 0x00U, + .bDataInterface = 0x01U + }, + + .cdc_acm = + { + .header = + { + .bLength = sizeof(usb_desc_acm_func), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x02U, + .bmCapabilities = 0x02U, + }, + + .cdc_union = + { + .header = + { + .bLength = sizeof(usb_desc_union_func), + .bDescriptorType = USB_DESCTYPE_CS_INTERFACE + }, + .bDescriptorSubtype = 0x06U, + .bMasterInterface = 0x00U, + .bSlaveInterface0 = 0x01U, + }, + + .cdc_cmd_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP, + }, + .bEndpointAddress = CDC_CMD_EP, + .bmAttributes = USB_EP_ATTR_INT, + .wMaxPacketSize = USB_CDC_CMD_PACKET_SIZE, + .bInterval = 0x0AU + }, + + .cdc_data_interface = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF, + }, + .bInterfaceNumber = 0x01U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x02U, + .bInterfaceClass = USB_CLASS_DATA, + .bInterfaceSubClass = 0x00U, + .bInterfaceProtocol = USB_CDC_PROTOCOL_NONE, + .iInterface = 0x00U + }, + + .cdc_out_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP, + }, + .bEndpointAddress = CDC_DATA_OUT_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = USB_CDC_DATA_PACKET_SIZE, + .bInterval = 0x00U + }, + + .cdc_in_endpoint = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = CDC_DATA_IN_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = USB_CDC_DATA_PACKET_SIZE, + .bInterval = 0x00U + } +}; + +/* USB language ID Descriptor */ +static const usb_desc_LANGID usbd_language_id_desc = { + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static const usb_desc_str manufacturer_string = { + .header = + { + .bLength = USB_STRING_LEN(10), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USB product string */ +static const usb_desc_str product_string = { + .header = + { + .bLength = USB_STRING_LEN(12), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'C', 'D', 'C', '_', 'A', 'C', 'M'} +}; + +/* USBD serial string */ +static usb_desc_str serial_string = { + .header = + { + .bLength = USB_STRING_LEN(12), + .bDescriptorType = USB_DESCTYPE_STR, + } +}; + +/* USB string descriptor set */ +void *const usbd_cdc_strings[] = { + [STR_IDX_LANGID] = (uint8_t *) &usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *) &manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *) &product_string, + [STR_IDX_SERIAL] = (uint8_t *) &serial_string +}; + +usb_desc cdc_desc = { + .dev_desc = (uint8_t *) &cdc_dev_desc, + .config_desc = (uint8_t *) &cdc_config_desc, + .strings = usbd_cdc_strings +}; + +/* local function prototypes ('static') */ +static uint8_t cdc_acm_init(usb_dev *udev, uint8_t config_index); +static uint8_t cdc_acm_deinit(usb_dev *udev, uint8_t config_index); +static uint8_t cdc_acm_req(usb_dev *udev, usb_req *req); +static uint8_t cdc_ctlx_out(usb_dev *udev); +static uint8_t cdc_acm_in(usb_dev *udev, uint8_t ep_num); +static uint8_t cdc_acm_out(usb_dev *udev, uint8_t ep_num); + +/* USB CDC device class callbacks structure */ +usb_class_core cdc_class = { + .command = NO_CMD, + .alter_set = 0U, + + .init = cdc_acm_init, + .deinit = cdc_acm_deinit, + + .req_proc = cdc_acm_req, + .ctlx_out = cdc_ctlx_out, + + .data_in = cdc_acm_in, + .data_out = cdc_acm_out +}; + +/*! + \brief check cdc acm is ready for data transfer + \param[in] udev: pointer to USB device instance + \param[out] none + \retval 0 if cdc is ready, 5 else +*/ +uint8_t cdc_acm_check_ready(usb_dev *udev) +{ + if(udev->dev.class_data[CDC_COM_INTERFACE] != NULL) { + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + if((1U == cdc->packet_receive) && (1U == cdc->packet_sent)) { + return 0U; + } + } + + return 1U; +} + +/*! + \brief send CDC ACM data + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +void cdc_acm_data_send(usb_dev *udev) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + if(0U != cdc->receive_length) { + cdc->packet_sent = 0U; + + usbd_ep_send(udev, CDC_DATA_IN_EP, (uint8_t *)(cdc->data), cdc->receive_length); + + cdc->receive_length = 0U; + } +} + +/*! + \brief receive CDC ACM data + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation status +*/ +void cdc_acm_data_receive(usb_dev *udev) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + cdc->packet_receive = 0U; + cdc->packet_sent = 0U; + + usbd_ep_recev(udev, CDC_DATA_OUT_EP, (uint8_t *)(cdc->data), USB_CDC_DATA_PACKET_SIZE); +} + +/*! + \brief initialize the CDC ACM device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_init(usb_dev *udev, uint8_t config_index) +{ + static usb_cdc_handler cdc_handler; + + /* initialize the data Tx endpoint */ + usbd_ep_setup(udev, &(cdc_config_desc.cdc_in_endpoint)); + + /* initialize the data Rx endpoint */ + usbd_ep_setup(udev, &(cdc_config_desc.cdc_out_endpoint)); + + /* initialize the command Tx endpoint */ + usbd_ep_setup(udev, &(cdc_config_desc.cdc_cmd_endpoint)); + + /* initialize cdc handler structure */ + cdc_handler.packet_receive = 1U; + cdc_handler.packet_sent = 1U; + cdc_handler.receive_length = 0U; + + cdc_handler.line_coding = (acm_line) { + .dwDTERate = 115200, + .bCharFormat = 0, + .bParityType = 0, + .bDataBits = 0x08 + }; + + udev->dev.class_data[CDC_COM_INTERFACE] = (void *)&cdc_handler; + + return USBD_OK; +} + +/*! + \brief de-initialize the CDC ACM device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_deinit(usb_dev *udev, uint8_t config_index) +{ + /* deinitialize the data Tx/Rx endpoint */ + usbd_ep_clear(udev, CDC_DATA_IN_EP); + usbd_ep_clear(udev, CDC_DATA_OUT_EP); + + /* deinitialize the command Tx endpoint */ + usbd_ep_clear(udev, CDC_CMD_EP); + + return USBD_OK; +} + +/*! + \brief handle the CDC ACM class-specific requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_req(usb_dev *udev, usb_req *req) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + usb_transc *transc = NULL; + + switch(req->bRequest) { + case SEND_ENCAPSULATED_COMMAND: + /* no operation for this driver */ + break; + + case GET_ENCAPSULATED_RESPONSE: + /* no operation for this driver */ + break; + + case SET_COMM_FEATURE: + /* no operation for this driver */ + break; + + case GET_COMM_FEATURE: + /* no operation for this driver */ + break; + + case CLEAR_COMM_FEATURE: + /* no operation for this driver */ + break; + + case SET_LINE_CODING: + transc = &udev->dev.transc_out[0]; + /* set the value of the current command to be processed */ + udev->dev.class_core->alter_set = req->bRequest; + + /* enable EP0 prepare to receive command data packet */ + transc->remain_len = req->wLength; + transc->xfer_buf = cdc->cmd; + break; + + case GET_LINE_CODING: + transc = &udev->dev.transc_in[0]; + + cdc->cmd[0] = (uint8_t)(cdc->line_coding.dwDTERate); + cdc->cmd[1] = (uint8_t)(cdc->line_coding.dwDTERate >> 8); + cdc->cmd[2] = (uint8_t)(cdc->line_coding.dwDTERate >> 16); + cdc->cmd[3] = (uint8_t)(cdc->line_coding.dwDTERate >> 24); + cdc->cmd[4] = cdc->line_coding.bCharFormat; + cdc->cmd[5] = cdc->line_coding.bParityType; + cdc->cmd[6] = cdc->line_coding.bDataBits; + + transc->xfer_buf = cdc->cmd; + transc->remain_len = 7U; + break; + + case SET_CONTROL_LINE_STATE: + /* no operation for this driver */ + break; + + case SEND_BREAK: + /* no operation for this driver */ + break; + + default: + break; + } + + return USBD_OK; +} + + +static uint8_t cdc_ctlx_out(usb_dev *udev) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + if(udev->dev.class_core->alter_set != NO_CMD) { + /* process the command data */ + cdc->line_coding.dwDTERate = (uint32_t)((uint32_t)cdc->cmd[0] | + ((uint32_t)cdc->cmd[1] << 8U) | + ((uint32_t)cdc->cmd[2] << 16U) | + ((uint32_t)cdc->cmd[3] << 24U)); + + cdc->line_coding.bCharFormat = cdc->cmd[4]; + cdc->line_coding.bParityType = cdc->cmd[5]; + cdc->line_coding.bDataBits = cdc->cmd[6]; + + udev->dev.class_core->alter_set = NO_CMD; + } + return USBD_OK; +} + +/*! + \brief handle CDC ACM data + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_in(usb_dev *udev, uint8_t ep_num) +{ + usb_transc *transc = &udev->dev.transc_in[EP_ID(ep_num)]; + + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + if((0U == transc->xfer_len % transc->max_len) && (0U != transc->xfer_len)) { + usbd_ep_send(udev, ep_num, NULL, 0U); + } else { + cdc->packet_sent = 1U; + } + + return USBD_OK; +} + +/*! + \brief handle CDC ACM data + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier + \param[out] none + \retval USB device operation status +*/ +static uint8_t cdc_acm_out(usb_dev *udev, uint8_t ep_num) +{ + usb_cdc_handler *cdc = (usb_cdc_handler *)udev->dev.class_data[CDC_COM_INTERFACE]; + + cdc->packet_receive = 1U; + cdc->receive_length = ((usb_core_driver *)udev)->dev.transc_out[ep_num].xfer_count; + + return USBD_OK; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/dfu/Include/dfu_core.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/dfu/Include/dfu_core.h new file mode 100644 index 000000000..4c58601ec --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/dfu/Include/dfu_core.h @@ -0,0 +1,173 @@ +/*! + \file dfu_core.h + \brief the header file of USB DFU device class core functions + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DFU_CORE_H +#define __DFU_CORE_H + +#include "usbd_enum.h" + +/* DFU class code */ +#define USB_DFU_CLASS 0xFEU + +/* DFU subclass code */ +#define USB_DFU_SUBCLASS_UPGRADE 0x01U + +/* DFU protocl code */ +#define USB_DFU_PROTOCL_RUNTIME 0x01U +#define USB_DFU_PROTOCL_DFU 0x02U + +/* manifestation state */ +#define MANIFEST_COMPLETE 0x00U +#define MANIFEST_IN_PROGRESS 0x01U + +/* DFU attributes code */ +#define USB_DFU_CAN_DOWNLOAD 0x01U +#define USB_DFU_CAN_UPLOAD 0x02U +#define USB_DFU_MANIFEST_TOLERANT 0x04U +#define USB_DFU_WILL_DETACH 0x08U + +/* special commands with download request */ +#define GET_COMMANDS 0x00U +#define SET_ADDRESS_POINTER 0x21U +#define ERASE 0x41U + +/* memory operation command */ +#define CMD_ERASE 0U +#define CMD_WRITE 1U + +#define _BYTE1(x) (uint8_t)((x) & 0xFFU) /*!< addressing cycle 1st byte */ +#define _BYTE2(x) (uint8_t)(((x) & 0xFF00U) >> 8U) /*!< addressing cycle 2nd byte */ +#define _BYTE3(x) (uint8_t)(((x) & 0xFF0000U) >> 16U) /*!< addressing cycle 3rd byte */ + +#define FLASH_ERASE_TIMEOUT 60U +#define FLASH_WRITE_TIMEOUT 80U + +/* bit detach capable = bit 3 in bmAttributes field */ +#define DFU_DETACH_MASK (uint8_t)(0x10U) + +#define USB_SERIAL_STR_LEN 0x06U + +#define USB_DFU_CONFIG_DESC_SIZE 27U + +#define DFU_DESC_TYPE 0x21U + +/* DFU device state defines */ +typedef enum { + STATE_APP_IDLE = 0x00U, + STATE_APP_DETACH, + STATE_DFU_IDLE, + STATE_DFU_DNLOAD_SYNC, + STATE_DFU_DNBUSY, + STATE_DFU_DNLOAD_IDLE, + STATE_DFU_MANIFEST_SYNC, + STATE_DFU_MANIFEST, + STATE_DFU_MANIFEST_WAIT_RESET, + STATE_DFU_UPLOAD_IDLE, + STATE_DFU_ERROR +} dfu_state; + +/* DFU device status defines */ +typedef enum { + STATUS_OK = 0x00U, + STATUS_ERR_TARGET, + STATUS_ERR_FILE, + STATUS_ERR_WRITE, + STATUS_ERR_ERASE, + STATUS_ERR_CHECK_ERASED, + STATUS_ERR_PROG, + STATUS_ERR_VERIFY, + STATUS_ERR_ADDRESS, + STATUS_ERR_NOTDONE, + STATUS_ERR_FIRMWARE, + STATUS_ERR_VENDOR, + STATUS_ERR_USBR, + STATUS_ERR_POR, + STATUS_ERR_UNKNOWN, + STATUS_ERR_STALLEDPKT +} dfu_status; + +/* DFU class-specific requests */ +typedef enum { + DFU_DETACH = 0U, + DFU_DNLOAD, + DFU_UPLOAD, + DFU_GETSTATUS, + DFU_CLRSTATUS, + DFU_GETSTATE, + DFU_ABORT, + DFU_REQ_MAX +} dfu_requests; + +#pragma pack(1) + +/* USB dfu function descriptor structure */ +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size */ + uint8_t bmAttributes; /*!< DFU attributes */ + uint16_t wDetachTimeOut; /*!< time, in milliseconds, that the device will wait after receipt of the DFU_DETACH request. If */ + uint16_t wTransferSize; /*!< maximum number of bytes that the device can accept per control-write transaction */ + uint16_t bcdDFUVersion; /*!< numeric expression identifying the version of the DFU Specification release. */ +} usb_desc_dfu_func; + +#pragma pack() + +/* USB configuration descriptor structure */ +typedef struct { + usb_desc_config config; + usb_desc_itf dfu_itf; + usb_desc_dfu_func dfu_func; +} usb_dfu_desc_config_set; + +typedef struct { + uint8_t bStatus; + uint8_t bwPollTimeout0; + uint8_t bwPollTimeout1; + uint8_t bwPollTimeout2; + uint8_t bState; + uint8_t iString; + + uint8_t manifest_state; + uint32_t data_len; + uint16_t block_num; + uint32_t base_addr; + + uint8_t buf[TRANSFER_SIZE]; +} usbd_dfu_handler; + +typedef void (*app_func)(void); + +extern usb_desc dfu_desc; +extern usb_class_core dfu_class; + +#endif /* DFU_CORE_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/dfu/Include/dfu_mal.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/dfu/Include/dfu_mal.h new file mode 100644 index 000000000..bd1ee7384 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/dfu/Include/dfu_mal.h @@ -0,0 +1,82 @@ +/*! + \file dfu_mal.h + \brief USB DFU device media access layer header file + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DFU_MAL_H +#define __DFU_MAL_H + +#include "usbd_conf.h" + +typedef struct _dfu_mal_prop { + const uint8_t *pstr_desc; + + uint8_t (*mal_init)(void); + uint8_t (*mal_deinit)(void); + uint8_t (*mal_erase)(uint32_t addr); + uint8_t (*mal_write)(uint8_t *buf, uint32_t addr, uint32_t len); + uint8_t *(*mal_read)(uint8_t *buf, uint32_t addr, uint32_t len); + uint8_t (*mal_checkaddr)(uint32_t addr); + + const uint32_t erase_timeout; + const uint32_t write_timeout; +} dfu_mal_prop; + +typedef enum { + MAL_OK = 0, + MAL_FAIL +} MAL_Status; + +#define _1st_BYTE(x) (uint8_t)((x) & 0xFF) /*!< addressing cycle 1st byte */ +#define _2nd_BYTE(x) (uint8_t)(((x) & 0xFF00) >> 8) /*!< addressing cycle 2nd byte */ +#define _3rd_BYTE(x) (uint8_t)(((x) & 0xFF0000) >> 16) /*!< addressing cycle 3rd byte */ + +#define SET_POLLING_TIMEOUT(x) buffer[0] = _1st_BYTE(x);\ + buffer[1] = _2nd_BYTE(x);\ + buffer[2] = _3rd_BYTE(x); + +/* function declarations */ +/* initialize the memory media on the GD32 */ +uint8_t dfu_mal_init(void); +/* deinitialize the memory media on the GD32 */ +uint8_t dfu_mal_deinit(void); +/* erase a memory sector */ +uint8_t dfu_mal_erase(uint32_t addr); +/* write data to sectors of memory */ +uint8_t dfu_mal_write(uint8_t *buf, uint32_t addr, uint32_t len); +/* read data from sectors of memory */ +uint8_t *dfu_mal_read(uint8_t *buf, uint32_t addr, uint32_t len); +/* get the status of a given memory and store in buffer */ +uint8_t dfu_mal_getstatus(uint32_t addr, uint8_t cmd, uint8_t *buffer); + +#endif /* __DFU_MAL_H */ + diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/dfu/Source/dfu_core.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/dfu/Source/dfu_core.c new file mode 100644 index 000000000..1a3d2a4a5 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/dfu/Source/dfu_core.c @@ -0,0 +1,643 @@ +/*! + \file dfu_core.c + \brief USB DFU device class core functions + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 + \version 2020-12-07, V3.0.1, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "dfu_core.h" +#include "drv_usb_hw.h" +#include "dfu_mal.h" +#include "flash_if.h" +#include + +#define USBD_VID 0x28E9U +#define USBD_PID 0x0189U + +/* local function prototypes ('static') */ +static uint8_t dfu_init(usb_dev *udev, uint8_t config_index); +static uint8_t dfu_deinit(usb_dev *udev, uint8_t config_index); +static uint8_t dfu_req_handler(usb_dev *udev, usb_req *req); +static uint8_t dfu_ctlx_in(usb_dev *udev); +static void dfu_detach(usb_dev *udev, usb_req *req); +static void dfu_dnload(usb_dev *udev, usb_req *req); +static void dfu_upload(usb_dev *udev, usb_req *req); +static void dfu_getstatus(usb_dev *udev, usb_req *req); +static void dfu_clrstatus(usb_dev *udev, usb_req *req); +static void dfu_getstate(usb_dev *udev, usb_req *req); +static void dfu_abort(usb_dev *udev, usb_req *req); +static void dfu_mode_leave(usb_dev *udev); +static uint8_t dfu_getstatus_complete(usb_dev *udev); + +static void (*dfu_request_process[])(usb_dev *udev, usb_req *req) = { + [DFU_DETACH] = dfu_detach, + [DFU_DNLOAD] = dfu_dnload, + [DFU_UPLOAD] = dfu_upload, + [DFU_GETSTATUS] = dfu_getstatus, + [DFU_CLRSTATUS] = dfu_clrstatus, + [DFU_GETSTATE] = dfu_getstate, + [DFU_ABORT] = dfu_abort +}; + +/* note:it should use the c99 standard when compiling the below codes */ +/* USB standard device descriptor */ +const usb_desc_dev dfu_dev_desc = { + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200U, + .bDeviceClass = 0x00U, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +/* USB device configuration descriptor */ +const usb_dfu_desc_config_set dfu_config_desc = { + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = USB_DFU_CONFIG_DESC_SIZE, + .bNumInterfaces = 0x01U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0x80U, + .bMaxPower = 0x32U + }, + + .dfu_itf = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x00U, + .bInterfaceClass = USB_DFU_CLASS, + .bInterfaceSubClass = USB_DFU_SUBCLASS_UPGRADE, + .bInterfaceProtocol = USB_DFU_PROTOCL_DFU, + .iInterface = 0x05U + }, + + .dfu_func = + { + .header = + { + .bLength = sizeof(usb_desc_dfu_func), + .bDescriptorType = DFU_DESC_TYPE + }, + .bmAttributes = USB_DFU_CAN_DOWNLOAD | USB_DFU_CAN_UPLOAD | USB_DFU_WILL_DETACH, + .wDetachTimeOut = 0x00FFU, + .wTransferSize = TRANSFER_SIZE, + .bcdDFUVersion = 0x011AU, + }, +}; + +/* USB language ID Descriptor */ +static const usb_desc_LANGID usbd_language_id_desc = { + .header = { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static const usb_desc_str manufacturer_string = { + .header = + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USB product string */ +static const usb_desc_str product_string = { + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'D', 'F', 'U'} +}; + +/* USBD serial string */ +static usb_desc_str serial_string = { + .header = + { + .bLength = USB_STRING_LEN(2U), + .bDescriptorType = USB_DESCTYPE_STR, + } +}; + +/* USB configure string */ +static const usb_desc_str config_string = { + .header = + { + .bLength = USB_STRING_LEN(15U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', ' ', 'U', 'S', 'B', ' ', 'C', 'O', 'N', 'F', 'I', 'G'} +}; + +static const usb_desc_str interface_string = { + .header = + { + .bLength = USB_STRING_LEN(44U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'@', 'I', 'n', 't', 'e', 'r', 'n', 'a', 'l', 'F', 'l', 'a', 's', 'h', ' ', '/', '0', 'x', '0', '8', '0', '0', + '0', '0', '0', '0', '/', '1', '6', '*', '0', '0', '1', 'K', 'a', ',', '4', '8', '*', '0', '0', '1', 'K', 'g' + } +}; + +void *const usbd_dfu_strings[] = { + [STR_IDX_LANGID] = (uint8_t *) &usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *) &manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *) &product_string, + [STR_IDX_SERIAL] = (uint8_t *) &serial_string, + [STR_IDX_CONFIG] = (uint8_t *) &config_string, + [STR_IDX_ITF] = (uint8_t *) &interface_string +}; + +usb_desc dfu_desc = { + .dev_desc = (uint8_t *) &dfu_dev_desc, + .config_desc = (uint8_t *) &dfu_config_desc, + .strings = usbd_dfu_strings +}; + +usb_class_core dfu_class = { + .init = dfu_init, + .deinit = dfu_deinit, + .req_proc = dfu_req_handler, + .ctlx_in = dfu_ctlx_in +}; + +/*! + \brief initialize the DFU device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t dfu_init(usb_dev *udev, uint8_t config_index) +{ + static usbd_dfu_handler dfu_handler; + + /* unlock the internal flash */ + dfu_mal_init(); + + memset((void *)&dfu_handler, 0, sizeof(usbd_dfu_handler)); + + dfu_handler.base_addr = APP_LOADED_ADDR; + dfu_handler.manifest_state = MANIFEST_COMPLETE; + dfu_handler.bState = STATE_DFU_IDLE; + dfu_handler.bStatus = STATUS_OK; + + udev->dev.class_data[USBD_DFU_INTERFACE] = (void *)&dfu_handler; + + return USBD_OK; +} + +/*! + \brief de-initialize the DFU device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t dfu_deinit(usb_dev *udev, uint8_t config_index) +{ + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + /* restore device default state */ + memset(udev->dev.class_data[USBD_DFU_INTERFACE], 0, sizeof(usbd_dfu_handler)); + + dfu->bState = STATE_DFU_IDLE; + dfu->bStatus = STATUS_OK; + + /* lock the internal flash */ + dfu_mal_deinit(); + + return USBD_OK; +} + +/*! + \brief handle the DFU class-specific requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t dfu_req_handler(usb_dev *udev, usb_req *req) +{ + if(req->bRequest < DFU_REQ_MAX) { + dfu_request_process[req->bRequest](udev, req); + } else { + return USBD_FAIL; + } + + return USBD_OK; +} + +/*! + \brief handle data Stage + \param[in] udev: pointer to USB device instance + \param[in] ep_num: the endpoint number + \param[out] none + \retval USB device operation status +*/ +static uint8_t dfu_ctlx_in(usb_dev *udev) +{ + dfu_getstatus_complete(udev); + + return USBD_OK; +} + +/*! + \brief leave DFU mode and reset device to jump to user loaded code + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +static void dfu_mode_leave(usb_dev *udev) +{ + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + dfu->manifest_state = MANIFEST_COMPLETE; + + if(dfu_config_desc.dfu_func.bmAttributes & 0x04U) { + dfu->bState = STATE_DFU_MANIFEST_SYNC; + } else { + dfu->bState = STATE_DFU_MANIFEST_WAIT_RESET; + + /* lock the internal flash */ + dfu_mal_deinit(); + + /* generate system reset to allow jumping to the user code */ + NVIC_SystemReset(); + } +} + +/*! + \brief handle data IN stage in control endpoint 0 + \param[in] udev: pointer to usb device instance + \param[out] none + \retval usb device operation status + */ +static uint8_t dfu_getstatus_complete(usb_dev *udev) +{ + uint32_t addr; + + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + if(STATE_DFU_DNBUSY == dfu->bState) { + /* decode the special command */ + if(0U == dfu->block_num) { + if(1U == dfu->data_len) { + if(GET_COMMANDS == dfu->buf[0]) { + /* no operation */ + } + } else if(5U == dfu->data_len) { + if(SET_ADDRESS_POINTER == dfu->buf[0]) { + /* set flash operation address */ + dfu->base_addr = *(uint32_t *)(dfu->buf + 1U); + } else if(ERASE == dfu->buf[0]) { + dfu->base_addr = *(uint32_t *)(dfu->buf + 1U); + + dfu_mal_erase(dfu->base_addr); + } else { + /* no operation */ + } + } else { + /* no operation */ + } + } else if(dfu->block_num > 1U) { /* regular download command */ + /* decode the required address */ + addr = (dfu->block_num - 2U) * TRANSFER_SIZE + dfu->base_addr; + + dfu_mal_write(dfu->buf, addr, dfu->data_len); + + dfu->block_num = 0U; + } else { + /* no operation */ + } + + dfu->data_len = 0U; + + /* update the device state and poll timeout */ + dfu->bState = STATE_DFU_DNLOAD_SYNC; + + return USBD_OK; + } else if(dfu->bState == STATE_DFU_MANIFEST) { /* manifestation in progress */ + /* start leaving DFU mode */ + dfu_mode_leave(udev); + } else { + /* no operation */ + } + + return USBD_OK; +} + +/*! + \brief handle the DFU_DETACH request + \param[in] udev: pointer to usb device instance + \param[in] req: DFU class request + \param[out] none + \retval none. +*/ +static void dfu_detach(usb_dev *udev, usb_req *req) +{ + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + switch(dfu->bState) { + case STATE_DFU_IDLE: + case STATE_DFU_DNLOAD_SYNC: + case STATE_DFU_DNLOAD_IDLE: + case STATE_DFU_MANIFEST_SYNC: + case STATE_DFU_UPLOAD_IDLE: + dfu->bStatus = STATUS_OK; + dfu->bState = STATE_DFU_IDLE; + dfu->iString = 0U; /* iString */ + + dfu->block_num = 0U; + dfu->data_len = 0U; + break; + + default: + break; + } + + /* check the detach capability in the DFU functional descriptor */ + if(dfu_config_desc.dfu_func.wDetachTimeOut & DFU_DETACH_MASK) { + usbd_disconnect(udev); + + usbd_connect(udev); + } else { + /* wait for the period of time specified in detach request */ + usb_mdelay(4U); + } +} + +/*! + \brief handle the DFU_DNLOAD request + \param[in] udev: pointer to usb device instance + \param[in] req: DFU class request + \param[out] none + \retval none +*/ +static void dfu_dnload(usb_dev *udev, usb_req *req) +{ + usb_transc *transc = &udev->dev.transc_out[0]; + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + switch(dfu->bState) { + case STATE_DFU_IDLE: + case STATE_DFU_DNLOAD_IDLE: + if(req->wLength > 0U) { + /* update the global length and block number */ + dfu->block_num = req->wValue; + dfu->data_len = req->wLength; + + dfu->bState = STATE_DFU_DNLOAD_SYNC; + + transc->remain_len = dfu->data_len; + transc->xfer_buf = dfu->buf; + } else { + dfu->manifest_state = MANIFEST_IN_PROGRESS; + dfu->bState = STATE_DFU_MANIFEST_SYNC; + } + break; + + default: + break; + } +} + +/*! + \brief handles the DFU UPLOAD request. + \param[in] udev: pointer to usb device instance + \param[in] req: DFU class request + \param[out] none + \retval none +*/ +static void dfu_upload(usb_dev *udev, usb_req *req) +{ + uint8_t *phy_addr = NULL; + uint32_t addr = 0U; + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + usb_transc *transc = &udev->dev.transc_in[0]; + + if(req->wLength <= 0U) { + dfu->bState = STATE_DFU_IDLE; + return; + } + + switch(dfu->bState) { + case STATE_DFU_IDLE: + case STATE_DFU_UPLOAD_IDLE: + /* update the global length and block number */ + dfu->block_num = req->wValue; + dfu->data_len = req->wLength; + + /* DFU get command */ + if(0U == dfu->block_num) { + /* update the state machine */ + dfu->bState = (dfu->data_len > 3U) ? STATE_DFU_IDLE : STATE_DFU_UPLOAD_IDLE; + + /* store the values of all supported commands */ + dfu->buf[0] = GET_COMMANDS; + dfu->buf[1] = SET_ADDRESS_POINTER; + dfu->buf[2] = ERASE; + + /* send the status data over EP0 */ + transc->xfer_buf = &(dfu->buf[0]); + transc->remain_len = 3U; + } else if(dfu->block_num > 1U) { + dfu->bState = STATE_DFU_UPLOAD_IDLE; + + /* change is accelerated */ + addr = (dfu->block_num - 2U) * TRANSFER_SIZE + dfu->base_addr; + + /* return the physical address where data are stored */ + phy_addr = dfu_mal_read(dfu->buf, addr, dfu->data_len); + + /* send the status data over EP0 */ + transc->xfer_buf = phy_addr; + transc->remain_len = dfu->data_len; + } else { + dfu->bState = STATUS_ERR_STALLEDPKT; + } + break; + + default: + dfu->data_len = 0U; + dfu->block_num = 0U; + break; + } +} + +/*! + \brief handle the DFU_GETSTATUS request + \param[in] udev: pointer to usb device instance + \param[in] req: DFU class request + \param[out] none + \retval none +*/ +static void dfu_getstatus(usb_dev *udev, usb_req *req) +{ + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + usb_transc *transc = &udev->dev.transc_in[0]; + + switch(dfu->bState) { + case STATE_DFU_DNLOAD_SYNC: + if(0U != dfu->data_len) { + dfu->bState = STATE_DFU_DNBUSY; + + if(0U == dfu->block_num) { + if(ERASE == dfu->buf[0]) { + dfu_mal_getstatus(dfu->base_addr, CMD_ERASE, (uint8_t *)&dfu->bwPollTimeout0); + } else { + dfu_mal_getstatus(dfu->base_addr, CMD_WRITE, (uint8_t *)&dfu->bwPollTimeout0); + } + } + } else { + dfu->bState = STATE_DFU_DNLOAD_IDLE; + } + break; + + case STATE_DFU_MANIFEST_SYNC: + if(MANIFEST_IN_PROGRESS == dfu->manifest_state) { + dfu->bState = STATE_DFU_MANIFEST; + dfu->bwPollTimeout0 = 1U; + } else if((MANIFEST_COMPLETE == dfu->manifest_state) && \ + (dfu_config_desc.dfu_func.bmAttributes & 0x04U)) { + dfu->bState = STATE_DFU_IDLE; + dfu->bwPollTimeout0 = 0U; + } else { + /* no operation */ + } + break; + + default: + break; + } + + /* send the status data of DFU interface to host over EP0 */ + transc->xfer_buf = (uint8_t *) & (dfu->bStatus); + transc->remain_len = 6U; +} + +/*! + \brief handle the DFU_CLRSTATUS request + \param udev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void dfu_clrstatus(usb_dev *udev, usb_req *req) +{ + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + if(STATE_DFU_ERROR == dfu->bState) { + dfu->bStatus = STATUS_OK; + dfu->bState = STATE_DFU_IDLE; + } else { + /* state error */ + dfu->bStatus = STATUS_ERR_UNKNOWN; + dfu->bState = STATE_DFU_ERROR; + } + + dfu->iString = 0U; /* iString: index = 0 */ +} + +/*! + \brief handle the DFU_GETSTATE request + \param[in] udev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void dfu_getstate(usb_dev *udev, usb_req *req) +{ + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + usb_transc *transc = &udev->dev.transc_in[0]; + + /* send the current state of the DFU interface to host */ + transc->xfer_buf = &(dfu->bState); + transc->remain_len = 1U; +} + +/*! + \brief handle the DFU_ABORT request + \param[in] udev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void dfu_abort(usb_dev *udev, usb_req *req) +{ + usbd_dfu_handler *dfu = (usbd_dfu_handler *)udev->dev.class_data[USBD_DFU_INTERFACE]; + + switch(dfu->bState) { + case STATE_DFU_IDLE: + case STATE_DFU_DNLOAD_SYNC: + case STATE_DFU_DNLOAD_IDLE: + case STATE_DFU_MANIFEST_SYNC: + case STATE_DFU_UPLOAD_IDLE: + dfu->bStatus = STATUS_OK; + dfu->bState = STATE_DFU_IDLE; + dfu->iString = 0U; /* iString: index = 0 */ + + dfu->block_num = 0U; + dfu->data_len = 0U; + break; + + default: + break; + } +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/dfu/Source/dfu_mal.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/dfu/Source/dfu_mal.c new file mode 100644 index 000000000..693947614 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/dfu/Source/dfu_mal.c @@ -0,0 +1,232 @@ +/*! + \file dfu_mal.c + \brief USB DFU device media access layer functions + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "dfu_mal.h" +#include "flash_if.h" +#include "drv_usb_hw.h" +#include "usbd_transc.h" + +extern usb_core_driver usb_dfu_dev; + +extern struct { + uint8_t buf[TRANSFER_SIZE]; + uint16_t data_len; + uint16_t block_num; + uint32_t base_addr; +} prog; + +dfu_mal_prop *tMALTab[MAX_USED_MEMORY_MEDIA] = { + &DFU_Flash_cb +}; + +/* The list of memory interface string descriptor pointers. This list + can be updated whenever a memory has to be added or removed */ +const uint8_t *USBD_DFU_StringDesc[MAX_USED_MEMORY_MEDIA] = { + (const uint8_t *)FLASH_IF_STRING +}; + +static uint8_t dfu_mal_checkaddr(uint32_t addr); + +/*! + \brief initialize the memory media on the GD32 + \param[in] none + \param[out] none + \retval MAL_OK +*/ +uint8_t dfu_mal_init(void) +{ + uint32_t mem_index = 0U; + + /* initialize all supported memory medias */ + for(mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++) { + /* check if the memory media exists */ + if(NULL != tMALTab[mem_index]->mal_init) { + tMALTab[mem_index]->mal_init(); + } + } + + return MAL_OK; +} + +/*! + \brief deinitialize the memory media on the GD32 + \param[in] none + \param[out] none + \retval MAL_OK +*/ +uint8_t dfu_mal_deinit(void) +{ + uint32_t mem_index = 0U; + + /* deinitializes all supported memory medias */ + for(mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++) { + /* check if the memory media exists */ + if(NULL != tMALTab[mem_index]->mal_deinit) { + tMALTab[mem_index]->mal_deinit(); + } + } + + return MAL_OK; +} + +/*! + \brief erase a memory sector + \param[in] addr: memory sector address/code + \param[out] none + \retval MAL_OK +*/ +uint8_t dfu_mal_erase(uint32_t addr) +{ + uint32_t mem_index = dfu_mal_checkaddr(addr); + + /* check if the address is in protected area */ + if(IS_PROTECTED_AREA(addr)) { + return MAL_FAIL; + } + + if(mem_index < MAX_USED_MEMORY_MEDIA) { + /* check if the operation is supported */ + if(NULL != tMALTab[mem_index]->mal_erase) { + return tMALTab[mem_index]->mal_erase(addr); + } else { + return MAL_FAIL; + } + } else { + return MAL_FAIL; + } +} + +/*! + \brief write data to sectors of memory + \param[in] buf: the data buffer to be write + \param[in] addr: memory sector address/code + \param[in] len: data length + \param[out] none + \retval MAL_OK +*/ +uint8_t dfu_mal_write(uint8_t *buf, uint32_t addr, uint32_t len) +{ + uint32_t mem_index = dfu_mal_checkaddr(addr); + + /* check if the address is in protected area */ + if(IS_PROTECTED_AREA(addr)) { + return MAL_FAIL; + } + + if(mem_index < MAX_USED_MEMORY_MEDIA) { + /* check if the operation is supported */ + if(NULL != tMALTab[mem_index]->mal_write) { + return tMALTab[mem_index]->mal_write(buf, addr, len); + } else { + return MAL_FAIL; + } + } else { + return MAL_FAIL; + } +} + +/*! + \brief read data from sectors of memory + \param[in] buf: the data buffer to be write + \param[in] addr: memory sector address/code + \param[in] len: data length + \param[out] none + \retval pointer to buffer +*/ +uint8_t *dfu_mal_read(uint8_t *buf, uint32_t addr, uint32_t len) +{ + uint32_t mem_index = 0U; + + if(OB_RDPT != addr) { + mem_index = dfu_mal_checkaddr(addr); + } + + if(mem_index < MAX_USED_MEMORY_MEDIA) { + /* check if the operation is supported */ + if(NULL != tMALTab[mem_index]->mal_read) { + return tMALTab[mem_index]->mal_read(buf, addr, len); + } else { + return buf; + } + } else { + return buf; + } +} + +/*! + \brief get the status of a given memory and store in buffer + \param[in] addr: memory sector address/code + \param[in] cmd: 0 for erase and 1 for write + \param[in] buffer: pointer to the buffer where the status data will be stored + \param[out] none + \retval MAL_OK if all operations are OK, MAL_FAIL else +*/ +uint8_t dfu_mal_getstatus(uint32_t addr, uint8_t cmd, uint8_t *buffer) +{ + uint32_t mem_index = dfu_mal_checkaddr(addr); + + if(mem_index < MAX_USED_MEMORY_MEDIA) { + if(cmd & 0x01U) { + SET_POLLING_TIMEOUT(tMALTab[mem_index]->write_timeout); + } else { + SET_POLLING_TIMEOUT(tMALTab[mem_index]->erase_timeout); + } + + return MAL_OK; + } else { + return MAL_FAIL; + } +} + +/*! + \brief check the address is supported + \param[in] addr: memory sector address/code + \param[out] none + \retval index of the addressed memory +*/ +static uint8_t dfu_mal_checkaddr(uint32_t addr) +{ + uint8_t mem_index = 0U; + + /* check with all supported memories */ + for(mem_index = 0U; mem_index < MAX_USED_MEMORY_MEDIA; mem_index++) { + /* if the check address is supported, return the memory index */ + if(MAL_OK == tMALTab[mem_index]->mal_checkaddr(addr)) { + return mem_index; + } + } + + /* if there is no memory found, return MAX_USED_MEMORY_MEDIA */ + return (MAX_USED_MEMORY_MEDIA); +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/hid/Include/custom_hid_core.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/hid/Include/custom_hid_core.h new file mode 100644 index 000000000..59c039207 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/hid/Include/custom_hid_core.h @@ -0,0 +1,69 @@ +/*! + \file custom_hid_core.h + \brief definitions for HID core + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __CUSTOM_HID_CORE_H +#define __CUSTOM_HID_CORE_H + +#include "usbd_enum.h" +#include "usb_hid.h" + +#define DESC_LEN_REPORT 96U +#define DESC_LEN_CONFIG 41U + +#define NO_CMD 0xFFU + +#define MAX_PERIPH_NUM 4U + +typedef struct { + uint8_t data[2]; + + uint8_t reportID; + uint8_t idlestate; + uint8_t protocol; +} custom_hid_handler; + +typedef struct { + void (*periph_config[MAX_PERIPH_NUM])(void); +} hid_fop_handler; + +extern usb_desc custom_hid_desc; +extern usb_class_core usbd_custom_hid_cb; + +/* function declarations */ +/* register HID interface operation functions */ +uint8_t custom_hid_itfop_register(usb_dev *udev, hid_fop_handler *hid_fop); +/* send custom HID report */ +uint8_t custom_hid_report_send(usb_dev *udev, uint8_t *report, uint32_t len); + +#endif /* __CUSTOM_HID_CORE_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/hid/Include/standard_hid_core.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/hid/Include/standard_hid_core.h new file mode 100644 index 000000000..003ac00c7 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/hid/Include/standard_hid_core.h @@ -0,0 +1,68 @@ +/*! + \file standard_hid_core.h + \brief definitions for HID core + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __STANDARD_HID_CORE_H +#define __STANDARD_HID_CORE_H + +#include "usbd_enum.h" +#include "usb_hid.h" + +#define USB_HID_CONFIG_DESC_LEN 0x22U +#define USB_HID_REPORT_DESC_LEN 0x2EU + +#define NO_CMD 0xFFU + +typedef struct { + uint32_t protocol; + uint32_t idle_state; + + uint8_t data[HID_IN_PACKET]; + __IO uint8_t prev_transfer_complete; +} standard_hid_handler; + +typedef struct { + void (*hid_itf_config)(void); + void (*hid_itf_data_process)(usb_dev *udev); +} hid_fop_handler; + +extern usb_desc hid_desc; +extern usb_class_core usbd_hid_cb; + +/* function declarations */ +/* register HID interface operation functions */ +uint8_t hid_itfop_register(usb_dev *udev, hid_fop_handler *hid_fop); +/* send keyboard report */ +uint8_t hid_report_send(usb_dev *pudev, uint8_t *report, uint32_t len); + +#endif /* __STANDARD_HID_CORE_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/hid/Source/custom_hid_core.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/hid/Source/custom_hid_core.c new file mode 100644 index 000000000..9195c559e --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/hid/Source/custom_hid_core.c @@ -0,0 +1,480 @@ +/*! + \file custom_hid_core.c + \brief custom HID class driver + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 + \version 2020-12-07, V3.0.1, firmware for GD32F3x0 + \version 2021-06-22, V3.0.2, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "custom_hid_core.h" +#include "usbd_enum.h" +#include + +#define USBD_VID 0x28E9U +#define USBD_PID 0x028AU + +/* Note:it should use the C99 standard when compiling the below codes */ +/* USB standard device descriptor */ +const usb_desc_dev custom_hid_dev_desc = { + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV, + }, + .bcdUSB = 0x0200U, + .bDeviceClass = 0x00U, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM, +}; + +/* USB device configuration descriptor */ +const usb_hid_desc_config_set custom_hid_config_desc = { + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = DESC_LEN_CONFIG, + .bNumInterfaces = 0x01U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0x80U, + .bMaxPower = 0x32U + }, + + .hid_itf = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x02U, + .bInterfaceClass = USB_HID_CLASS, + .bInterfaceSubClass = 0x00U, + .bInterfaceProtocol = 0x00U, + .iInterface = 0x00U + }, + + .hid_vendor = + { + .header = + { + .bLength = sizeof(usb_desc_hid), + .bDescriptorType = USB_DESCTYPE_HID + }, + .bcdHID = 0x0111U, + .bCountryCode = 0x00U, + .bNumDescriptors = 0x01U, + .bDescriptorType = USB_DESCTYPE_REPORT, + .wDescriptorLength = DESC_LEN_REPORT, + }, + + .hid_epin = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = CUSTOMHID_IN_EP, + .bmAttributes = USB_EP_ATTR_INT, + .wMaxPacketSize = CUSTOMHID_IN_PACKET, + .bInterval = 0x20U + }, + + .hid_epout = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = CUSTOMHID_OUT_EP, + .bmAttributes = USB_EP_ATTR_INT, + .wMaxPacketSize = CUSTOMHID_OUT_PACKET, + .bInterval = 0x20U + } +}; + +/* USB language ID descriptor */ +static const usb_desc_LANGID usbd_language_id_desc = { + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static const usb_desc_str manufacturer_string = { + .header = + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USB product string */ +static const usb_desc_str product_string = { + .header = + { + .bLength = USB_STRING_LEN(14U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'C', 'u', 's', 't', 'o', 'm', 'H', 'I', 'D'} +}; + +/* USBD serial string */ +static usb_desc_str serial_string = { + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + } +}; + +/* USB string descriptor set */ +void *const usbd_hid_strings[] = { + [STR_IDX_LANGID] = (uint8_t *) &usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *) &manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *) &product_string, + [STR_IDX_SERIAL] = (uint8_t *) &serial_string +}; + +usb_desc custom_hid_desc = { + .dev_desc = (uint8_t *) &custom_hid_dev_desc, + .config_desc = (uint8_t *) &custom_hid_config_desc, + .strings = usbd_hid_strings +}; + +const uint8_t customhid_report_descriptor[DESC_LEN_REPORT] = { + 0x06, 0x00, 0xFF, /* USAGE_PAGE (Vendor Defined: 0xFF00) */ + 0x09, 0x00, /* USAGE (Custom Device) */ + 0xa1, 0x01, /* COLLECTION (Application) */ + + /* led 1 */ + 0x85, 0x11, /* REPORT_ID (0x11) */ + 0x09, 0x01, /* USAGE (LED 1) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + + /* led 2 */ + 0x85, 0x12, /* REPORT_ID (0x12) */ + 0x09, 0x02, /* USAGE (LED 2) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + + /* led 3 */ + 0x85, 0x13, /* REPORT_ID (0x13) */ + 0x09, 0x03, /* USAGE (LED 3) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + + /* led 4 */ + 0x85, 0x14, /* REPORT_ID (0x14) */ + 0x09, 0x04, /* USAGE (LED 4) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + + /* wakeup key */ + 0x85, 0x15, /* REPORT_ID (0x15) */ + 0x09, 0x05, /* USAGE (Push Button) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x01, /* REPORT_SIZE (1) */ + 0x81, 0x02, /* INPUT (Data,Var,Abs,Vol) */ + + 0x75, 0x07, /* REPORT_SIZE (7) */ + 0x81, 0x03, /* INPUT (Cnst,Var,Abs,Vol) */ + + /* tamper key */ + 0x85, 0x16, /* REPORT_ID (0x16) */ + 0x09, 0x06, /* USAGE (Push Button) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x75, 0x01, /* REPORT_SIZE (1) */ + 0x81, 0x02, /* INPUT (Data,Var,Abs,Vol) */ + + 0x75, 0x07, /* REPORT_SIZE (7) */ + 0x81, 0x03, /* INPUT (Cnst,Var,Abs,Vol) */ + + 0xc0 /* END_COLLECTION */ +}; + +/* local function prototypes ('static') */ +static uint8_t custom_hid_init(usb_dev *udev, uint8_t config_index); +static uint8_t custom_hid_deinit(usb_dev *udev, uint8_t config_index); +static uint8_t custom_hid_req_handler(usb_dev *udev, usb_req *req); +static uint8_t custom_hid_data_in(usb_dev *udev, uint8_t ep_num); +static uint8_t custom_hid_data_out(usb_dev *udev, uint8_t ep_num); + +usb_class_core usbd_custom_hid_cb = { + .command = NO_CMD, + .alter_set = 0U, + + .init = custom_hid_init, + .deinit = custom_hid_deinit, + + .req_proc = custom_hid_req_handler, + + .data_in = custom_hid_data_in, + .data_out = custom_hid_data_out +}; + +/*! + \brief register HID interface operation functions + \param[in] udev: pointer to USB device instance + \param[in] hid_fop: HID operation functions structure + \param[out] none + \retval USB device operation status +*/ +uint8_t custom_hid_itfop_register(usb_dev *udev, hid_fop_handler *hid_fop) +{ + if(NULL != hid_fop) { + udev->dev.user_data = hid_fop; + + return USBD_OK; + } + + return USBD_FAIL; +} + +/*! + \brief send custom HID report + \param[in] udev: pointer to USB device instance + \param[in] report: pointer to HID report + \param[in] len: data length + \param[out] none + \retval USB device operation status +*/ +uint8_t custom_hid_report_send(usb_dev *udev, uint8_t *report, uint32_t len) +{ + usbd_ep_send(udev, CUSTOMHID_IN_EP, report, len); + + return USBD_OK; +} + +/*! + \brief initialize the HID device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t custom_hid_init(usb_dev *udev, uint8_t config_index) +{ + static custom_hid_handler hid_handler; + + memset((void *)&hid_handler, 0U, sizeof(custom_hid_handler)); + + /* Initialize the data Tx endpoint */ + usbd_ep_setup(udev, &(custom_hid_config_desc.hid_epin)); + + /* Initialize the data Rx endpoint */ + usbd_ep_setup(udev, &(custom_hid_config_desc.hid_epout)); + + /* prepare receive data */ + usbd_ep_recev(udev, CUSTOMHID_OUT_EP, hid_handler.data, 2U); + + udev->dev.class_data[CUSTOM_HID_INTERFACE] = (void *)&hid_handler; + + if(udev->dev.user_data != NULL) { + for(uint8_t i = 0U; i < MAX_PERIPH_NUM; i++) { + if(((hid_fop_handler *)udev->dev.user_data)->periph_config[i] != NULL) { + ((hid_fop_handler *)udev->dev.user_data)->periph_config[i](); + } + } + } + + return USBD_OK; +} + +/*! + \brief de-initialize the HID device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t custom_hid_deinit(usb_dev *udev, uint8_t config_index) +{ + /* deinitialize HID endpoints */ + usbd_ep_clear(udev, CUSTOMHID_IN_EP); + usbd_ep_clear(udev, CUSTOMHID_OUT_EP); + + return USBD_OK; +} + +/*! + \brief handle the HID class-specific requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t custom_hid_req_handler(usb_dev *udev, usb_req *req) +{ + usb_transc *transc = &udev->dev.transc_in[0]; + + custom_hid_handler *hid = (custom_hid_handler *)udev->dev.class_data[CUSTOM_HID_INTERFACE]; + + switch(req->bRequest) { + case GET_REPORT: + break; + + case GET_IDLE: + transc->xfer_buf = (uint8_t *)&hid->idlestate; + transc->remain_len = 1U; + break; + + case GET_PROTOCOL: + transc->xfer_buf = (uint8_t *)&hid->protocol; + transc->remain_len = 1U; + break; + + case SET_REPORT: + hid->reportID = (uint8_t)(req->wValue); + break; + + case SET_IDLE: + hid->idlestate = (uint8_t)(req->wValue >> 8U); + break; + + case SET_PROTOCOL: + hid->protocol = (uint8_t)(req->wValue); + break; + + case USB_GET_DESCRIPTOR: + if(USB_DESCTYPE_REPORT == (req->wValue >> 8U)) { + transc->remain_len = USB_MIN(DESC_LEN_REPORT, req->wLength); + transc->xfer_buf = (uint8_t *)customhid_report_descriptor; + } + break; + + default: + return USBD_FAIL; + } + + return USBD_OK; +} + +/*! + \brief handle custom HID data + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier + \param[out] none + \retval USB device operation status +*/ +static uint8_t custom_hid_data_in(usb_dev *udev, uint8_t ep_num) +{ + return USBD_OK; +} + +/*! + \brief handle custom HID data + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier + \param[out] none + \retval USB device operation status +*/ +static uint8_t custom_hid_data_out(usb_dev *udev, uint8_t ep_num) +{ + custom_hid_handler *hid = (custom_hid_handler *)udev->dev.class_data[CUSTOM_HID_INTERFACE]; + + switch(hid->data[0]) { + case 0x11U: + if(RESET != hid->data[1]) { + gd_eval_led_on(LED1); + } else { + gd_eval_led_off(LED1); + } + break; + + case 0x12U: + if(RESET != hid->data[1]) { + gd_eval_led_on(LED2); + } else { + gd_eval_led_off(LED2); + } + break; + + case 0x13U: + if(RESET != hid->data[1]) { + gd_eval_led_on(LED3); + } else { + gd_eval_led_off(LED3); + } + break; + + case 0x14U: + if(RESET != hid->data[1]) { + gd_eval_led_on(LED4); + } else { + gd_eval_led_off(LED4); + } + break; + + + default: + break; + } + + usbd_ep_recev(udev, CUSTOMHID_OUT_EP, hid->data, 2U); + + return USBD_OK; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/hid/Source/standard_hid_core.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/hid/Source/standard_hid_core.c new file mode 100644 index 000000000..291995257 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/hid/Source/standard_hid_core.c @@ -0,0 +1,382 @@ +/*! + \file standard_hid_core.c + \brief HID class driver + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 + \version 2020-12-07, V3.0.1, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "standard_hid_core.h" +#include + +#define USBD_VID 0x28e9U +#define USBD_PID 0x0380U + +/* Note:it should use the C99 standard when compiling the below codes */ +/* USB standard device descriptor */ +const usb_desc_dev hid_dev_desc = { + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200U, + .bDeviceClass = 0x00U, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +const usb_hid_desc_config_set hid_config_desc = { + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = USB_HID_CONFIG_DESC_LEN, + .bNumInterfaces = 0x01U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0xA0U, + .bMaxPower = 0x32U + }, + + .hid_itf = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x01U, + .bInterfaceClass = USB_HID_CLASS, + .bInterfaceSubClass = USB_HID_SUBCLASS_BOOT_ITF, + .bInterfaceProtocol = USB_HID_PROTOCOL_KEYBOARD, + .iInterface = 0x00U + }, + + .hid_vendor = + { + .header = + { + .bLength = sizeof(usb_desc_hid), + .bDescriptorType = USB_DESCTYPE_HID + }, + .bcdHID = 0x0111U, + .bCountryCode = 0x00U, + .bNumDescriptors = 0x01U, + .bDescriptorType = USB_DESCTYPE_REPORT, + .wDescriptorLength = USB_HID_REPORT_DESC_LEN, + }, + + .hid_epin = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = HID_IN_EP, + .bmAttributes = USB_EP_ATTR_INT, + .wMaxPacketSize = HID_IN_PACKET, + .bInterval = 0x40U + } +}; + +/* USB language ID Descriptor */ +const usb_desc_LANGID usbd_language_id_desc = { + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static const usb_desc_str manufacturer_string = { + .header = + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USB product string */ +static const usb_desc_str product_string = { + .header = + { + .bLength = USB_STRING_LEN(17U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'K', 'e', 'y', 'b', 'o', 'a', 'r', 'd'} +}; + +/* USBD serial string */ +static usb_desc_str serial_string = { + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + } +}; + +void *const usbd_hid_strings[] = { + [STR_IDX_LANGID] = (uint8_t *) &usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *) &manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *) &product_string, + [STR_IDX_SERIAL] = (uint8_t *) &serial_string +}; + +usb_desc hid_desc = { + .dev_desc = (uint8_t *) &hid_dev_desc, + .config_desc = (uint8_t *) &hid_config_desc, + .strings = usbd_hid_strings +}; + +const uint8_t hid_report_desc[USB_HID_REPORT_DESC_LEN] = { + 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ + 0x09, 0x06, /* USAGE (Keyboard) */ + 0xa1, 0x01, /* COLLECTION (Application) */ + + 0x05, 0x07, /* USAGE_PAGE (Keyboard/Keypad) */ + 0x19, 0xe0, /* USAGE_MINIMUM (Keyboard LeftControl) */ + 0x29, 0xe7, /* USAGE_MAXIMUM (Keyboard Right GUI) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */ + 0x95, 0x08, /* REPORT_COUNT (8) */ + 0x75, 0x01, /* REPORT_SIZE (1) */ + 0x81, 0x02, /* INPUT (Data,Var,Abs) */ + + 0x95, 0x01, /* REPORT_COUNT (1) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x81, 0x03, /* INPUT (Cnst,Var,Abs) */ + + 0x95, 0x06, /* REPORT_COUNT (6) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x26, 0xFF, 0x00, /* LOGICAL_MAXIMUM (255) */ + 0x05, 0x07, /* USAGE_PAGE (Keyboard/Keypad) */ + 0x19, 0x00, /* USAGE_MINIMUM (Reserved (no event indicated)) */ + 0x29, 0x65, /* USAGE_MAXIMUM (Keyboard Application) */ + 0x81, 0x00, /* INPUT (Data,Ary,Abs) */ + + 0xc0 /* END_COLLECTION */ +}; + +/* local function prototypes ('static') */ +static uint8_t hid_init(usb_dev *udev, uint8_t config_index); +static uint8_t hid_deinit(usb_dev *udev, uint8_t config_index); +static uint8_t hid_req(usb_dev *udev, usb_req *req); +static uint8_t hid_data_in(usb_dev *udev, uint8_t ep_num); + +usb_class_core usbd_hid_cb = { + .command = NO_CMD, + .alter_set = 0U, + + .init = hid_init, + .deinit = hid_deinit, + .req_proc = hid_req, + .data_in = hid_data_in +}; + +/*! + \brief register HID interface operation functions + \param[in] udev: pointer to USB device instance + \param[in] hid_fop: HID operation functions structure + \param[out] none + \retval USB device operation status +*/ +uint8_t hid_itfop_register(usb_dev *udev, hid_fop_handler *hid_fop) +{ + if(NULL != hid_fop) { + udev->dev.user_data = (void *)hid_fop; + + return USBD_OK; + } + + return USBD_FAIL; +} + +/*! + \brief send keyboard report + \param[in] udev: pointer to USB device instance + \param[in] report: pointer to HID report + \param[in] len: data length + \param[out] none + \retval USB device operation status +*/ +uint8_t hid_report_send(usb_dev *udev, uint8_t *report, uint32_t len) +{ + standard_hid_handler *hid = (standard_hid_handler *)udev->dev.class_data[USBD_HID_INTERFACE]; + + hid->prev_transfer_complete = 0U; + + usbd_ep_send(udev, HID_IN_EP, report, len); + + return USBD_OK; +} + +/*! + \brief initialize the HID device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t hid_init(usb_dev *udev, uint8_t config_index) +{ + static standard_hid_handler hid_handler; + + memset((void *)&hid_handler, 0U, sizeof(standard_hid_handler)); + + /* Initialize the data Tx endpoint */ + usbd_ep_setup(udev, &(hid_config_desc.hid_epin)); + + hid_handler.prev_transfer_complete = 1U; + + udev->dev.class_data[USBD_HID_INTERFACE] = (void *)&hid_handler; + + if(NULL != udev->dev.user_data) { + ((hid_fop_handler *)udev->dev.user_data)->hid_itf_config(); + } + + return USBD_OK; +} + +/*! + \brief de-initialize the HID device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t hid_deinit(usb_dev *udev, uint8_t config_index) +{ + /* deinitialize HID endpoints */ + usbd_ep_clear(udev, HID_IN_EP); + + return USBD_OK; +} + +/*! + \brief handle the HID class-specific requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t hid_req(usb_dev *udev, usb_req *req) +{ + usb_transc *transc = &udev->dev.transc_in[0]; + + standard_hid_handler *hid = (standard_hid_handler *)udev->dev.class_data[USBD_HID_INTERFACE]; + + switch(req->bRequest) { + case GET_REPORT: + /* no use for this driver */ + break; + + case GET_IDLE: + transc->xfer_buf = (uint8_t *)&hid->idle_state; + + transc->remain_len = 1U; + break; + + case GET_PROTOCOL: + transc->xfer_buf = (uint8_t *)&hid->protocol; + + transc->remain_len = 1U; + break; + + case SET_REPORT: + /* no use for this driver */ + break; + + case SET_IDLE: + hid->idle_state = (uint8_t)(req->wValue >> 8U); + break; + + case SET_PROTOCOL: + hid->protocol = (uint8_t)(req->wValue); + break; + + case USB_GET_DESCRIPTOR: + if(USB_DESCTYPE_REPORT == (req->wValue >> 8U)) { + transc->remain_len = USB_MIN(USB_HID_REPORT_DESC_LEN, req->wLength); + transc->xfer_buf = (uint8_t *)hid_report_desc; + + return REQ_SUPP; + } else if(USB_DESCTYPE_HID == (req->wValue >> 8U)) { + transc->remain_len = USB_MIN(9U, req->wLength); + transc->xfer_buf = (uint8_t *)(&(hid_config_desc.hid_vendor)); + } + break; + + default: + break; + } + + return USBD_OK; +} + +/*! + \brief handle data stage + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier + \param[out] none + \retval USB device operation status +*/ +static uint8_t hid_data_in(usb_dev *udev, uint8_t ep_num) +{ + standard_hid_handler *hid = (standard_hid_handler *)udev->dev.class_data[USBD_HID_INTERFACE]; + + if(0U != hid->data[2]) { + hid->data[2] = 0x00U; + + usbd_ep_send(udev, HID_IN_EP, hid->data, HID_IN_PACKET); + } else { + hid->prev_transfer_complete = 1U; + } + + return USBD_OK; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/iap/Include/usb_iap_core.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/iap/Include/usb_iap_core.h new file mode 100644 index 000000000..72755c7da --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/iap/Include/usb_iap_core.h @@ -0,0 +1,86 @@ +/*! + \file usb_iap_core.h + \brief the header file of IAP driver + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_IAP_CORE_H +#define __USB_IAP_CORE_H + +#include "usbd_enum.h" +#include "usb_hid.h" + +#define USB_SERIAL_STRING_SIZE 0x06U + +#ifdef USE_USB_FS +#define USB_DESC_LEN_IAP_REPORT 35U +#endif +#define USB_DESC_LEN_IAP_CONFIG_SET 41U + +/* special commands with download request */ +#define IAP_OPTION_BYTE1 0x01U +#define IAP_ERASE 0x02U +#define IAP_DNLOAD 0x03U +#define IAP_LEAVE 0x04U +#define IAP_GETBIN_ADDRESS 0x05U +#define IAP_OPTION_BYTE2 0x06U + +typedef struct { + uint8_t report_buf[IAP_OUT_PACKET + 1U]; + uint8_t option_byte[IAP_IN_PACKET]; + + /* state machine variables */ + uint8_t dev_status[IAP_IN_PACKET]; + uint8_t bin_addr[IAP_IN_PACKET]; + + uint8_t reportID; + uint8_t flag; + + uint32_t protocol; + uint32_t idlestate; + + uint16_t transfer_times; + uint16_t page_count; + uint16_t lps; /* last packet size */ + uint32_t file_length; + uint32_t base_address; +} usbd_iap_handler; + +typedef void (*app_func)(void); + +extern usb_desc iap_desc; +extern usb_class_core iap_class; + +/* function declarations */ +/* send iap report */ +uint8_t iap_report_send(usb_dev *udev, uint8_t *report, uint32_t len); + +#endif /* __USB_IAP_CORE_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/iap/Source/usb_iap_core.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/iap/Source/usb_iap_core.c new file mode 100644 index 000000000..299788cee --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/iap/Source/usb_iap_core.c @@ -0,0 +1,554 @@ +/*! + \file usb_iap_core.c + \brief IAP driver + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 + \version 2020-12-07, V3.0.1, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usb_iap_core.h" +#include "flash_operation.h" +#include + +#define USBD_VID 0x28E9U +#define USBD_PID 0x0228U + +/* Note:it should use the C99 standard when compiling the below codes */ +/* USB standard device descriptor */ +__ALIGN_BEGIN const usb_desc_dev iap_dev_desc __ALIGN_END = { + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200U, + .bDeviceClass = 0x00U, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +__ALIGN_BEGIN const usb_hid_desc_config_set iap_config_desc __ALIGN_END = { + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = USB_DESC_LEN_IAP_CONFIG_SET, + .bNumInterfaces = 0x01U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0x80U, + .bMaxPower = 0x32U + }, + + .hid_itf = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x02U, + .bInterfaceClass = USB_HID_CLASS, + .bInterfaceSubClass = 0x00U, + .bInterfaceProtocol = 0x00U, + .iInterface = 0x00U + }, + + .hid_vendor = + { + .header = + { + .bLength = sizeof(usb_desc_hid), + .bDescriptorType = USB_DESCTYPE_HID + }, + .bcdHID = 0x0111U, + .bCountryCode = 0x00U, + .bNumDescriptors = 0x01U, + .bDescriptorType = USB_DESCTYPE_REPORT, + .wDescriptorLength = USB_DESC_LEN_IAP_REPORT, + }, + + .hid_epin = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = IAP_IN_EP, + .bmAttributes = USB_EP_ATTR_INT, + .wMaxPacketSize = IAP_IN_PACKET, + .bInterval = 0x01U + }, + + .hid_epout = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = IAP_OUT_EP, + .bmAttributes = USB_EP_ATTR_INT, + .wMaxPacketSize = IAP_OUT_PACKET, + .bInterval = 0x01U + } +}; + +/* USB language ID Descriptor */ +static __ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = { + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = { + .header = + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USB product string */ +static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = { + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'I', 'A', 'P'} +}; + +/* USBD serial string */ +static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = { + .header = + { + .bLength = USB_STRING_LEN(2U), + .bDescriptorType = USB_DESCTYPE_STR, + } +}; + +void *const usbd_iap_strings[] = { + [STR_IDX_LANGID] = (uint8_t *) &usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *) &manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *) &product_string, + [STR_IDX_SERIAL] = (uint8_t *) &serial_string +}; + +usb_desc iap_desc = { + .dev_desc = (uint8_t *) &iap_dev_desc, + .config_desc = (uint8_t *) &iap_config_desc, + .strings = usbd_iap_strings +}; + +/* local function prototypes ('static') */ +static uint8_t iap_init(usb_dev *udev, uint8_t config_index); +static uint8_t iap_deinit(usb_dev *udev, uint8_t config_index); +static uint8_t iap_req_handler(usb_dev *udev, usb_req *req); +static uint8_t iap_data_out(usb_dev *udev, uint8_t ep_num); + +/* IAP requests management functions */ +static void iap_req_erase(usb_dev *udev); +static void iap_req_dnload(usb_dev *udev); +static void iap_req_optionbyte(usb_dev *udev, uint8_t option_num); +static void iap_req_leave(usb_dev *udev); +static void iap_address_send(usb_dev *udev); + +usb_class_core iap_class = { + .init = iap_init, + .deinit = iap_deinit, + .req_proc = iap_req_handler, + .data_out = iap_data_out +}; + +/* USB custom HID device report descriptor */ +__ALIGN_BEGIN const uint8_t iap_report_desc[USB_DESC_LEN_IAP_REPORT] __ALIGN_END = { + 0x05, 0x01, /* USAGE_PAGE (Generic Desktop) */ + 0x09, 0x00, /* USAGE (Custom Device) */ + 0xa1, 0x01, /* COLLECTION (Application) */ + + /* IAP command and data */ + 0x85, 0x01, /* REPORT_ID (0x01) */ + 0x09, 0x01, /* USAGE (IAP command) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0xff, /* LOGICAL_MAXIMUM (255) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, REPORT_OUT_COUNT, + 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */ + + /* device status and option byte */ + 0x85, 0x02, /* REPORT_ID (0x02) */ + 0x09, 0x02, /* USAGE (Status and option byte) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0xff, /* LOGICAL_MAXIMUM (255) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x95, REPORT_IN_COUNT, /* REPORT_COUNT (23) */ + 0x81, 0x82, /* INPUT (Data,Var,Abs,Vol) */ + + 0xc0 /* END_COLLECTION */ +}; + +/*! + \brief send iap report + \param[in] udev: pointer to USB device instance + \param[in] report: pointer to HID report + \param[in] len: data length + \param[out] none + \retval USB device operation status +*/ +uint8_t iap_report_send(usb_dev *udev, uint8_t *report, uint32_t len) +{ + usbd_ep_send(udev, IAP_IN_EP, report, len); + + return USBD_OK; +} + +/*! + \brief initialize the IAP device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t iap_init(usb_dev *udev, uint8_t config_index) +{ + static __ALIGN_BEGIN usbd_iap_handler iap_handler __ALIGN_END; + + /* initialize Tx endpoint */ + usbd_ep_setup(udev, &(iap_config_desc.hid_epin)); + + /* initialize Rx endpoint */ + usbd_ep_setup(udev, &(iap_config_desc.hid_epout)); + + /* unlock the internal flash */ + fmc_unlock(); + + memset((void *)&iap_handler, 0U, sizeof(usbd_iap_handler)); + + /* prepare receive data */ + usbd_ep_recev(udev, IAP_OUT_EP, iap_handler.report_buf, IAP_OUT_PACKET); + + iap_handler.base_address = APP_LOADED_ADDR; + + udev->dev.class_data[USBD_IAP_INTERFACE] = (void *)&iap_handler; + + return USBD_OK; +} + +/*! + \brief de-initialize the iap device + \param[in] udev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t iap_deinit(usb_dev *udev, uint8_t config_index) +{ + /* deinitialize iap endpoints */ + usbd_ep_clear(udev, IAP_IN_EP); + usbd_ep_clear(udev, IAP_OUT_EP); + + /* lock the internal flash */ + fmc_lock(); + + return USBD_OK; +} + +/*! + \brief handle the iap class-specific requests + \param[in] udev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t iap_req_handler(usb_dev *udev, usb_req *req) +{ + usb_transc *transc = &udev->dev.transc_in[0]; + + usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE]; + + switch(req->bRequest) { + case GET_REPORT: + /* no use for this driver */ + break; + + case GET_IDLE: + transc->xfer_buf = (uint8_t *)&iap->idlestate; + transc->remain_len = 1U; + break; + + case GET_PROTOCOL: + transc->xfer_buf = (uint8_t *)&iap->protocol; + transc->remain_len = 1U; + break; + + case SET_REPORT: + iap->reportID = (uint8_t)(req->wValue); + break; + + case SET_IDLE: + iap->idlestate = (uint8_t)(req->wValue >> 8U); + break; + + case SET_PROTOCOL: + iap->protocol = (uint8_t)(req->wValue); + break; + + case USB_GET_DESCRIPTOR: + if(USB_DESCTYPE_REPORT == (req->wValue >> 8U)) { + transc->remain_len = USB_MIN(USB_DESC_LEN_IAP_REPORT, req->wLength); + transc->xfer_buf = (uint8_t *)iap_report_desc; + } + break; + + default: + return USBD_FAIL; + } + + return USBD_OK; +} + +/*! + \brief handle data out stage + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier + \param[out] none + \retval none +*/ +static uint8_t iap_data_out(usb_dev *udev, uint8_t ep_num) +{ + usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE]; + + if(0x01U == iap->report_buf[0]) { + switch(iap->report_buf[1]) { + case IAP_DNLOAD: + iap_req_dnload(udev); + break; + + case IAP_ERASE: + iap_req_erase(udev); + break; + + case IAP_OPTION_BYTE1: + iap_req_optionbyte(udev, 0x01U); + break; + + case IAP_LEAVE: + iap_req_leave(udev); + break; + + case IAP_GETBIN_ADDRESS: + iap_address_send(udev); + break; + + case IAP_OPTION_BYTE2: + iap_req_optionbyte(udev, 0x02U); + break; + + default: + break; + } + } + + usbd_ep_recev(udev, IAP_OUT_EP, iap->report_buf, IAP_OUT_PACKET); + + return USBD_OK; +} + +/*! + \brief handle the IAP_DNLOAD request + \param[in] udev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void iap_req_dnload(usb_dev *udev) +{ + usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE]; + + if(0U != iap->transfer_times) { + if(1U == iap->transfer_times) { + if(0U == iap->lps) { + iap_data_write(&iap->report_buf[2], iap->base_address, TRANSFER_SIZE); + } else { + iap_data_write(&iap->report_buf[2], iap->base_address, iap->file_length % TRANSFER_SIZE); + iap->lps = 0U; + } + + iap->dev_status[0] = 0x02U; + iap->dev_status[1] = 0x02U; + iap_report_send(udev, iap->dev_status, IAP_IN_PACKET); + } else { + iap_data_write(&iap->report_buf[2], iap->base_address, TRANSFER_SIZE); + + iap->base_address += TRANSFER_SIZE; + } + + iap->transfer_times--; + } +} + +/*! + \brief handle the IAP_ERASE request + \param[in] udev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void iap_req_erase(usb_dev *udev) +{ + uint32_t addr = 0U; + + usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE]; + + /* get base address to erase */ + iap->base_address = iap->report_buf[2]; + iap->base_address |= iap->report_buf[3] << 8U; + iap->base_address |= iap->report_buf[4] << 16U; + iap->base_address |= iap->report_buf[5] << 24U; + + /* get file length */ + iap->file_length = iap->report_buf[7]; + iap->file_length |= iap->report_buf[8] << 8U; + iap->file_length |= iap->report_buf[9] << 16U; + iap->file_length |= iap->report_buf[10] << 24U; + + iap->lps = iap->file_length % TRANSFER_SIZE; + if(0U == iap->lps) { + iap->transfer_times = iap->file_length / TRANSFER_SIZE; + } else { + iap->transfer_times = iap->file_length / TRANSFER_SIZE + 1U; + } + + /* check if the address is in protected area */ + if(IS_PROTECTED_AREA(iap->base_address)) { + return; + } + + addr = iap->base_address; + + /* unlock the flash program erase controller */ + fmc_unlock(); + + flash_erase(addr, iap->file_length, iap->report_buf); + + fmc_lock(); + + iap->dev_status[0] = 0x02U; + iap->dev_status[1] = 0x01U; + + usbd_ep_send(udev, IAP_IN_EP, iap->dev_status, IAP_IN_PACKET); +} + +/*! + \brief handle the IAP_OPTION_BYTE request + \param[in] udev: pointer to USB device instance + \param[in] option_num: number of option byte + \param[out] none + \retval none +*/ +static void iap_req_optionbyte(usb_dev *udev, uint8_t option_num) +{ + uint8_t i = 0U; + uint32_t address = 0U; + + usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE]; + + iap->option_byte[0] = 0x02U; + + if(0x01U == option_num) { + address = OPT_BYTE_ADDR1; +#ifdef OPT_BYTE_ADDR2 + } else if(0x02U == option_num) { + address = OPT_BYTE_ADDR2; +#endif + } else { + return; + } + + for(i = 1U; i < 17U; i++) { + iap->option_byte[i] = *(uint8_t *)address; + address++; + } + + iap_report_send(udev, iap->option_byte, IAP_IN_PACKET); +} + +/*! + \brief handle the IAP_LEAVE request + \param[in] udev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void iap_req_leave(usb_dev *udev) +{ + /* lock the internal flash */ + fmc_lock(); + + /* generate system reset to allow jumping to the user code */ + NVIC_SystemReset(); +} + +/*! + \brief handle the IAP_SEND_ADDRESS request + \param[in] udev: pointer to usb device instance + \param[out] none + \retval none +*/ +static void iap_address_send(usb_dev *udev) +{ + usbd_iap_handler *iap = (usbd_iap_handler *)udev->dev.class_data[USBD_IAP_INTERFACE]; + + iap->bin_addr[0] = 0x02U; + + iap->bin_addr[1] = (uint8_t)(APP_LOADED_ADDR); + iap->bin_addr[2] = (uint8_t)(APP_LOADED_ADDR >> 8U); + iap->bin_addr[3] = (uint8_t)(APP_LOADED_ADDR >> 16U); + iap->bin_addr[4] = (uint8_t)(APP_LOADED_ADDR >> 24U); + + iap_report_send(udev, iap->bin_addr, IAP_IN_PACKET); +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Include/usbd_msc_bbb.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Include/usbd_msc_bbb.h new file mode 100644 index 000000000..c260c56d1 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Include/usbd_msc_bbb.h @@ -0,0 +1,100 @@ +/*! + \file usbd_msc_bbb.h + \brief the header file of the usbd_msc_bot.c file + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_MSC_BBB_H +#define __USBD_MSC_BBB_H + +#include "usbd_core.h" +#include "msc_bbb.h" +#include "usbd_msc_mem.h" +#include "usbd_msc_scsi.h" + +/* MSC BBB state */ +enum msc_bbb_state { + BBB_IDLE = 0U, /*!< idle state */ + BBB_DATA_OUT, /*!< data OUT state */ + BBB_DATA_IN, /*!< data IN state */ + BBB_LAST_DATA_IN, /*!< last data IN state */ + BBB_SEND_DATA /*!< send immediate data state */ +}; + +/* MSC BBB status */ +enum msc_bbb_status { + BBB_STATUS_NORMAL = 0U, /*!< normal status */ + BBB_STATUS_RECOVERY, /*!< recovery status*/ + BBB_STATUS_ERROR /*!< error status */ +}; + +typedef struct { + uint8_t bbb_data[MSC_MEDIA_PACKET_SIZE]; + + uint8_t max_lun; + uint8_t bbb_state; + uint8_t bbb_status; + + uint32_t bbb_datalen; + + msc_bbb_cbw bbb_cbw; + msc_bbb_csw bbb_csw; + + uint8_t scsi_sense_head; + uint8_t scsi_sense_tail; + + uint32_t scsi_blk_size[MEM_LUN_NUM]; + uint32_t scsi_blk_nbr[MEM_LUN_NUM]; + + uint32_t scsi_blk_addr; + uint32_t scsi_blk_len; + uint32_t scsi_disk_pop; + + msc_scsi_sense scsi_sense[SENSE_LIST_DEEPTH]; +} usbd_msc_handler; + +/* function declarations */ +/* initialize the bbb process */ +void msc_bbb_init(usb_core_driver *pudev); +/* reset the BBB machine */ +void msc_bbb_reset(usb_core_driver *pudev); +/* de-initialize the BBB machine */ +void msc_bbb_deinit(usb_core_driver *pudev); +/* handle BBB data IN stage */ +void msc_bbb_data_in(usb_core_driver *pudev, uint8_t ep_num); +/* handle BBB data OUT stage */ +void msc_bbb_data_out(usb_core_driver *pudev, uint8_t ep_num); +/* send the CSW(command status wrapper) */ +void msc_bbb_csw_send(usb_core_driver *pudev, uint8_t csw_status); +/* complete the clear feature request */ +void msc_bbb_clrfeature(usb_core_driver *pudev, uint8_t ep_num); + +#endif /* __USBD_MSC_BBB_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Include/usbd_msc_core.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Include/usbd_msc_core.h new file mode 100644 index 000000000..52dfe975b --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Include/usbd_msc_core.h @@ -0,0 +1,58 @@ +/*! + \file usbd_msc_core.h + \brief the header file of USB MSC device class core functions + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_MSC_CORE_H +#define __USBD_MSC_CORE_H + +#include "usbd_core.h" +#include "usb_msc.h" + +#define USB_MSC_CONFIG_DESC_SIZE 32U + +#define MSC_EPIN_SIZE MSC_DATA_PACKET_SIZE +#define MSC_EPOUT_SIZE MSC_DATA_PACKET_SIZE + +/* USB configuration descriptor structure */ +typedef struct { + usb_desc_config config; + + usb_desc_itf msc_itf; + usb_desc_ep msc_epin; + usb_desc_ep msc_epout; +} usb_desc_config_set; + +extern usb_desc msc_desc; +extern usb_class_core msc_class; + +#endif /* __USBD_MSC_CORE_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Include/usbd_msc_data.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Include/usbd_msc_data.h new file mode 100644 index 000000000..ae0abf627 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Include/usbd_msc_data.h @@ -0,0 +1,49 @@ +/*! + \file usbd_msc_data.h + \brief the header file of the usbd_msc_data.c file + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_MSC_DATA_H +#define __USBD_MSC_DATA_H + +#include "usbd_conf.h" + +#define MODE_SENSE6_LENGTH 8U +#define MODE_SENSE10_LENGTH 8U +#define INQUIRY_PAGE00_LENGTH 96U +#define FORMAT_CAPACITIES_LENGTH 20U + +extern const uint8_t msc_page00_inquiry_data[]; +extern const uint8_t msc_mode_sense6_data[]; +extern const uint8_t msc_mode_sense10_data[]; + +#endif /* __USBD_MSC_DATA_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Include/usbd_msc_mem.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Include/usbd_msc_mem.h new file mode 100644 index 000000000..758b79553 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Include/usbd_msc_mem.h @@ -0,0 +1,58 @@ +/*! + \file usbd_msc_mem.h + \brief header file for storage memory + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_MSC_MEM_H +#define __USBD_MSC_MEM_H + +#include "usbd_conf.h" + +#define USBD_STD_INQUIRY_LENGTH 36U + +typedef struct { + int8_t (*mem_init)(uint8_t lun); + int8_t (*mem_ready)(uint8_t lun); + int8_t (*mem_protected)(uint8_t lun); + int8_t (*mem_read)(uint8_t lun, uint8_t *buf, uint32_t block_addr, uint16_t block_len); + int8_t (*mem_write)(uint8_t lun, uint8_t *buf, uint32_t block_addr, uint16_t block_len); + int8_t (*mem_maxlun)(void); + + uint8_t *mem_toc_data; + uint8_t *mem_inquiry_data[MEM_LUN_NUM]; + uint32_t mem_block_size[MEM_LUN_NUM]; + uint32_t mem_block_len[MEM_LUN_NUM]; +} usbd_mem_cb; + +extern usbd_mem_cb *usbd_mem_fops; + +#endif /* __USBD_MSC_MEM_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Include/usbd_msc_scsi.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Include/usbd_msc_scsi.h new file mode 100644 index 000000000..762c1cc74 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Include/usbd_msc_scsi.h @@ -0,0 +1,50 @@ +/*! + \file usbd_msc_scsi.h + \brief the header file of the usbd_msc_scsi.c file + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_MSC_SCSI_H +#define __USBD_MSC_SCSI_H + +#include "usbd_msc_data.h" +#include "usbd_msc_bbb.h" +#include "msc_scsi.h" + +#define SENSE_LIST_DEEPTH 4U + +/* function declarations */ +/* process SCSI commands */ +int8_t scsi_process_cmd(usb_core_driver *pudev, uint8_t lun, uint8_t *cmd); +/* load the last error code in the error list */ +void scsi_sense_code(usb_core_driver *pudev, uint8_t lun, uint8_t skey, uint8_t asc); + +#endif /* __USBD_MSC_SCSI_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Source/usbd_msc_bbb.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Source/usbd_msc_bbb.c new file mode 100644 index 000000000..ad950297c --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Source/usbd_msc_bbb.c @@ -0,0 +1,287 @@ +/*! + \file usbd_msc_bbb.c + \brief USB BBB(Bulk/Bulk/Bulk) protocol core functions + \note BBB means Bulk-only transport protocol for USB MSC + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_enum.h" +#include "usbd_msc_bbb.h" + +/* local function prototypes ('static') */ +static void msc_bbb_cbw_decode(usb_core_driver *pudev); +static void msc_bbb_data_send(usb_core_driver *pudev, uint8_t *pbuf, uint32_t Len); +static void msc_bbb_abort(usb_core_driver *pudev); + +/*! + \brief initialize the bbb process + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval none +*/ +void msc_bbb_init(usb_core_driver *pudev) +{ + uint8_t lun_num; + + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_state = BBB_IDLE; + msc->bbb_status = BBB_STATUS_NORMAL; + + /* init the storage logic unit */ + for(lun_num = 0U; lun_num < MEM_LUN_NUM; lun_num++) { + usbd_mem_fops->mem_init(lun_num); + } + + /* flush the Rx FIFO */ + usbd_fifo_flush(pudev, MSC_OUT_EP); + + /* flush the Tx FIFO */ + usbd_fifo_flush(pudev, MSC_IN_EP); + + /* prepare endpoint to receive the first BBB CBW */ + usbd_ep_recev(pudev, MSC_OUT_EP, (uint8_t *)&msc->bbb_cbw, BBB_CBW_LENGTH); +} + +/*! + \brief reset the BBB machine + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval none +*/ +void msc_bbb_reset(usb_core_driver *pudev) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_state = BBB_IDLE; + msc->bbb_status = BBB_STATUS_RECOVERY; + + /* prepare endpoint to receive the first BBB command */ + usbd_ep_recev(pudev, MSC_OUT_EP, (uint8_t *)&msc->bbb_cbw, BBB_CBW_LENGTH); +} + +/*! + \brief de-initialize the BBB machine + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval none +*/ +void msc_bbb_deinit(usb_core_driver *pudev) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_state = BBB_IDLE; +} + +/*! + \brief handle BBB data IN stage + \param[in] pudev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval none +*/ +void msc_bbb_data_in(usb_core_driver *pudev, uint8_t ep_num) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + switch(msc->bbb_state) { + case BBB_DATA_IN: + if(scsi_process_cmd(pudev, msc->bbb_cbw.bCBWLUN, &msc->bbb_cbw.CBWCB[0]) < 0) { + msc_bbb_csw_send(pudev, CSW_CMD_FAILED); + } + break; + + case BBB_SEND_DATA: + case BBB_LAST_DATA_IN: + msc_bbb_csw_send(pudev, CSW_CMD_PASSED); + break; + + default: + break; + } +} + +/*! + \brief handle BBB data OUT stage + \param[in] pudev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval none +*/ +void msc_bbb_data_out(usb_core_driver *pudev, uint8_t ep_num) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + switch(msc->bbb_state) { + case BBB_IDLE: + msc_bbb_cbw_decode(pudev); + break; + + case BBB_DATA_OUT: + if(scsi_process_cmd(pudev, msc->bbb_cbw.bCBWLUN, &msc->bbb_cbw.CBWCB[0]) < 0) { + msc_bbb_csw_send(pudev, CSW_CMD_FAILED); + } + break; + + default: + break; + } +} + +/*! + \brief send the CSW(command status wrapper) + \param[in] pudev: pointer to USB device instance + \param[in] csw_status: CSW status + \param[out] none + \retval none +*/ +void msc_bbb_csw_send(usb_core_driver *pudev, uint8_t csw_status) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_csw.dCSWSignature = BBB_CSW_SIGNATURE; + msc->bbb_csw.bCSWStatus = csw_status; + msc->bbb_state = BBB_IDLE; + + usbd_ep_send(pudev, MSC_IN_EP, (uint8_t *)&msc->bbb_csw, BBB_CSW_LENGTH); + + /* prapare endpoint to receive next command */ + usbd_ep_recev(pudev, MSC_OUT_EP, (uint8_t *)&msc->bbb_cbw, BBB_CBW_LENGTH); +} + +/*! + \brief complete the clear feature request + \param[in] pudev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval none +*/ +void msc_bbb_clrfeature(usb_core_driver *pudev, uint8_t ep_num) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + if(msc->bbb_status == BBB_STATUS_ERROR) { /* bad CBW signature */ + usbd_ep_stall(pudev, MSC_IN_EP); + + msc->bbb_status = BBB_STATUS_NORMAL; + } else if(((ep_num & 0x80U) == 0x80U) && (msc->bbb_status != BBB_STATUS_RECOVERY)) { + msc_bbb_csw_send(pudev, CSW_CMD_FAILED); + } else { + + } +} + +/*! + \brief decode the CBW command and set the BBB state machine accordingly + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval none +*/ +static void msc_bbb_cbw_decode(usb_core_driver *pudev) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_csw.dCSWTag = msc->bbb_cbw.dCBWTag; + msc->bbb_csw.dCSWDataResidue = msc->bbb_cbw.dCBWDataTransferLength; + + if((BBB_CBW_LENGTH != usbd_rxcount_get(pudev, MSC_OUT_EP)) || + (BBB_CBW_SIGNATURE != msc->bbb_cbw.dCBWSignature) || + (msc->bbb_cbw.bCBWLUN > 1U) || + (msc->bbb_cbw.bCBWCBLength < 1U) || + (msc->bbb_cbw.bCBWCBLength > 16U)) { + /* illegal command handler */ + scsi_sense_code(pudev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + msc->bbb_status = BBB_STATUS_ERROR; + + msc_bbb_abort(pudev); + } else { + if(scsi_process_cmd(pudev, msc->bbb_cbw.bCBWLUN, &msc->bbb_cbw.CBWCB[0]) < 0) { + msc_bbb_abort(pudev); + } else if((BBB_DATA_IN != msc->bbb_state) && + (BBB_DATA_OUT != msc->bbb_state) && + (BBB_LAST_DATA_IN != msc->bbb_state)) { /* burst xfer handled internally */ + if(msc->bbb_datalen > 0U) { + msc_bbb_data_send(pudev, msc->bbb_data, msc->bbb_datalen); + } else if(0U == msc->bbb_datalen) { + msc_bbb_csw_send(pudev, CSW_CMD_PASSED); + } else { + + } + } else { + + } + } +} + +/*! + \brief send the requested data + \param[in] pudev: pointer to USB device instance + \param[in] buf: pointer to data buffer + \param[in] len: data length + \param[out] none + \retval none +*/ +static void msc_bbb_data_send(usb_core_driver *pudev, uint8_t *buf, uint32_t len) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + len = USB_MIN(msc->bbb_cbw.dCBWDataTransferLength, len); + + msc->bbb_csw.dCSWDataResidue -= len; + msc->bbb_csw.bCSWStatus = CSW_CMD_PASSED; + msc->bbb_state = BBB_SEND_DATA; + + usbd_ep_send(pudev, MSC_IN_EP, buf, len); +} + +/*! + \brief abort the current transfer + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval none +*/ +static void msc_bbb_abort(usb_core_driver *pudev) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + if((0U == msc->bbb_cbw.bmCBWFlags) && + (0U != msc->bbb_cbw.dCBWDataTransferLength) && + (BBB_STATUS_NORMAL == msc->bbb_status)) { + usbd_ep_stall(pudev, MSC_OUT_EP); + } + + usbd_ep_stall(pudev, MSC_IN_EP); + + if(msc->bbb_status == BBB_STATUS_ERROR) { + usbd_ep_recev(pudev, MSC_OUT_EP, (uint8_t *)&msc->bbb_cbw, BBB_CBW_LENGTH); + } +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Source/usbd_msc_core.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Source/usbd_msc_core.c new file mode 100644 index 000000000..0c5b920ce --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Source/usbd_msc_core.c @@ -0,0 +1,311 @@ +/*! + \file usbd_msc_core.c + \brief USB MSC device class core functions + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 + \version 2020-12-07, V3.0.1, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_enum.h" +#include "usbd_msc_bbb.h" +#include "usbd_msc_core.h" +#include + +#define USBD_VID 0x28E9U +#define USBD_PID 0x028FU + +/* local function prototypes ('static') */ +static uint8_t msc_core_init(usb_dev *pudev, uint8_t config_index); +static uint8_t msc_core_deinit(usb_dev *pudev, uint8_t config_index); +static uint8_t msc_core_req(usb_dev *pudev, usb_req *req); +static uint8_t msc_core_in(usb_dev *pudev, uint8_t ep_num); +static uint8_t msc_core_out(usb_dev *pudev, uint8_t ep_num); + +usb_class_core msc_class = { + .init = msc_core_init, + .deinit = msc_core_deinit, + + .req_proc = msc_core_req, + + .data_in = msc_core_in, + .data_out = msc_core_out +}; + +/* note: it should use the C99 standard when compiling the below codes */ +/* USB standard device descriptor */ +__ALIGN_BEGIN const usb_desc_dev msc_dev_desc __ALIGN_END = { + .header = { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV + }, + .bcdUSB = 0x0200U, + .bDeviceClass = 0x00U, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM +}; + +/* USB device configuration descriptor */ +__ALIGN_BEGIN const usb_desc_config_set msc_config_desc __ALIGN_END = { + .config = + { + .header = { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = USB_MSC_CONFIG_DESC_SIZE, + .bNumInterfaces = 0x01U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0xC0U, + .bMaxPower = 0x32U + }, + + .msc_itf = + { + .header = { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x02U, + .bInterfaceClass = USB_CLASS_MSC, + .bInterfaceSubClass = USB_MSC_SUBCLASS_SCSI, + .bInterfaceProtocol = USB_MSC_PROTOCOL_BBB, + .iInterface = 0x00U + }, + + .msc_epin = + { + .header = { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = MSC_IN_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = MSC_EPIN_SIZE, + .bInterval = 0x00U + }, + + .msc_epout = + { + .header = { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = MSC_OUT_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = MSC_EPOUT_SIZE, + .bInterval = 0x00U + } +}; + +/* USB language ID descriptor */ +__ALIGN_BEGIN const usb_desc_LANGID usbd_language_id_desc __ALIGN_END = { + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR + }, + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static __ALIGN_BEGIN const usb_desc_str manufacturer_string __ALIGN_END = { + .header = + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USB product string */ +static __ALIGN_BEGIN const usb_desc_str product_string __ALIGN_END = { + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'M', 'S', 'C'} +}; + +/* USBD serial string */ +static __ALIGN_BEGIN usb_desc_str serial_string __ALIGN_END = { + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + } +}; + +/* USB string descriptor */ +void *const usbd_msc_strings[] = { + [STR_IDX_LANGID] = (uint8_t *) &usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *) &manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *) &product_string, + [STR_IDX_SERIAL] = (uint8_t *) &serial_string +}; + +usb_desc msc_desc = { + .dev_desc = (uint8_t *) &msc_dev_desc, + .config_desc = (uint8_t *) &msc_config_desc, + .strings = usbd_msc_strings +}; + +static __ALIGN_BEGIN uint8_t usbd_msc_maxlun = 0U __ALIGN_END; + +/*! + \brief initialize the MSC device + \param[in] pudev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t msc_core_init(usb_dev *pudev, uint8_t config_index) +{ + static __ALIGN_BEGIN usbd_msc_handler msc_handler __ALIGN_END; + + memset((void *)&msc_handler, 0U, sizeof(usbd_msc_handler)); + + pudev->dev.class_data[USBD_MSC_INTERFACE] = (void *)&msc_handler; + + /* configure MSC Tx endpoint */ + usbd_ep_setup(pudev, &(msc_config_desc.msc_epin)); + + /* configure MSC Rx endpoint */ + usbd_ep_setup(pudev, &(msc_config_desc.msc_epout)); + + /* init the BBB layer */ + msc_bbb_init(pudev); + + return USBD_OK; +} + +/*! + \brief de-initialize the MSC device + \param[in] pudev: pointer to USB device instance + \param[in] config_index: configuration index + \param[out] none + \retval USB device operation status +*/ +static uint8_t msc_core_deinit(usb_dev *pudev, uint8_t config_index) +{ + /* clear MSC endpoints */ + usbd_ep_clear(pudev, MSC_IN_EP); + usbd_ep_clear(pudev, MSC_OUT_EP); + + /* un-init the BBB layer */ + msc_bbb_deinit(pudev); + + return USBD_OK; +} + +/*! + \brief handle the MSC class-specific and standard requests + \param[in] pudev: pointer to USB device instance + \param[in] req: device class-specific request + \param[out] none + \retval USB device operation status +*/ +static uint8_t msc_core_req(usb_dev *pudev, usb_req *req) +{ + usb_transc *transc = &pudev->dev.transc_in[0]; + + switch(req->bRequest) { + case BBB_GET_MAX_LUN : + if((0U == req->wValue) && + (1U == req->wLength) && + (0x80U == (req->bmRequestType & 0x80U))) { + usbd_msc_maxlun = (uint8_t)usbd_mem_fops->mem_maxlun(); + + transc->xfer_buf = &usbd_msc_maxlun; + transc->remain_len = 1U; + } else { + return USBD_FAIL; + } + break; + + case BBB_RESET : + if((0U == req->wValue) && + (0U == req->wLength) && + (0x80U != (req->bmRequestType & 0x80U))) { + msc_bbb_reset(pudev); + } else { + return USBD_FAIL; + } + break; + + case USB_CLEAR_FEATURE: + msc_bbb_clrfeature(pudev, (uint8_t)req->wIndex); + break; + + default: + return USBD_FAIL; + } + + return USBD_OK; +} + +/*! + \brief handle data in stage + \param[in] pudev: pointer to USB device instance + \param[in] ep_num: the endpoint number + \param[out] none + \retval none +*/ +static uint8_t msc_core_in(usb_dev *pudev, uint8_t ep_num) +{ + msc_bbb_data_in(pudev, ep_num); + + return USBD_OK; +} + +/*! + \brief handle data out stage + \param[in] pudev: pointer to USB device instance + \param[in] ep_num: the endpoint number + \param[out] none + \retval none +*/ +static uint8_t msc_core_out(usb_dev *pudev, uint8_t ep_num) +{ + msc_bbb_data_out(pudev, ep_num); + + return USBD_OK; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Source/usbd_msc_data.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Source/usbd_msc_data.c new file mode 100644 index 000000000..421e58bac --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Source/usbd_msc_data.c @@ -0,0 +1,70 @@ +/*! + \file usbd_msc_data.c + \brief USB MSC vital inquiry pages and sense data + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_msc_data.h" + +/* USB mass storage page 0 inquiry data */ +const uint8_t msc_page00_inquiry_data[] = { + 0x00U, + 0x00U, + 0x00U, + 0x00U, + (INQUIRY_PAGE00_LENGTH - 4U), + 0x80U, + 0x83U, +}; + +/* USB mass storage sense 6 data */ +const uint8_t msc_mode_sense6_data[] = { + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U +}; + +/* USB mass storage sense 10 data */ +const uint8_t msc_mode_sense10_data[] = { + 0x00U, + 0x06U, + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U, + 0x00U +}; diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Source/usbd_msc_scsi.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Source/usbd_msc_scsi.c new file mode 100644 index 000000000..f597fb46e --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/msc/Source/usbd_msc_scsi.c @@ -0,0 +1,724 @@ +/*! + \file usbd_msc_scsi.c + \brief USB SCSI layer functions + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_enum.h" +#include "usbd_msc_bbb.h" +#include "usbd_msc_scsi.h" +#include "usbd_msc_data.h" + +/* local function prototypes ('static') */ +static int8_t scsi_test_unit_ready(usb_core_driver *pudev, uint8_t lun, uint8_t *params); +static int8_t scsi_mode_select6(usb_core_driver *pudev, uint8_t lun, uint8_t *params); +static int8_t scsi_mode_select10(usb_core_driver *pudev, uint8_t lun, uint8_t *params); +static int8_t scsi_inquiry(usb_core_driver *pudev, uint8_t lun, uint8_t *params); +static int8_t scsi_read_format_capacity(usb_core_driver *pudev, uint8_t lun, uint8_t *params); +static int8_t scsi_read_capacity10(usb_core_driver *pudev, uint8_t lun, uint8_t *params); +static int8_t scsi_request_sense(usb_core_driver *pudev, uint8_t lun, uint8_t *params); +static int8_t scsi_mode_sense6(usb_core_driver *pudev, uint8_t lun, uint8_t *params); +static int8_t scsi_toc_cmd_read(usb_core_driver *pudev, uint8_t lun, uint8_t *params); +static int8_t scsi_mode_sense10(usb_core_driver *pudev, uint8_t lun, uint8_t *params); +static int8_t scsi_write10(usb_core_driver *pudev, uint8_t lun, uint8_t *params); +static int8_t scsi_read10(usb_core_driver *pudev, uint8_t lun, uint8_t *params); +static int8_t scsi_verify10(usb_core_driver *pudev, uint8_t lun, uint8_t *params); +static int8_t scsi_process_read(usb_core_driver *pudev, uint8_t lun); +static int8_t scsi_process_write(usb_core_driver *pudev, uint8_t lun); + +static inline int8_t scsi_check_address_range(usb_core_driver *pudev, uint8_t lun, uint32_t blk_offset, uint16_t blk_nbr); +static inline int8_t scsi_format_cmd(usb_core_driver *pudev, uint8_t lun); +static inline int8_t scsi_start_stop_unit(usb_core_driver *pudev, uint8_t lun, uint8_t *params); +static inline int8_t scsi_allow_medium_removal(usb_core_driver *pudev, uint8_t lun, uint8_t *params); + +/*! + \brief process SCSI commands + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +int8_t scsi_process_cmd(usb_core_driver *pudev, uint8_t lun, uint8_t *params) +{ + switch(params[0]) { + case SCSI_TEST_UNIT_READY: + return scsi_test_unit_ready(pudev, lun, params); + + case SCSI_REQUEST_SENSE: + return scsi_request_sense(pudev, lun, params); + + case SCSI_INQUIRY: + return scsi_inquiry(pudev, lun, params); + + case SCSI_START_STOP_UNIT: + return scsi_start_stop_unit(pudev, lun, params); + + case SCSI_ALLOW_MEDIUM_REMOVAL: + return scsi_allow_medium_removal(pudev, lun, params); + + case SCSI_MODE_SENSE6: + return scsi_mode_sense6(pudev, lun, params); + + case SCSI_MODE_SENSE10: + return scsi_mode_sense10(pudev, lun, params); + + case SCSI_READ_FORMAT_CAPACITIES: + return scsi_read_format_capacity(pudev, lun, params); + + case SCSI_READ_CAPACITY10: + return scsi_read_capacity10(pudev, lun, params); + + case SCSI_READ10: + return scsi_read10(pudev, lun, params); + + case SCSI_WRITE10: + return scsi_write10(pudev, lun, params); + + case SCSI_VERIFY10: + return scsi_verify10(pudev, lun, params); + + case SCSI_FORMAT_UNIT: + return scsi_format_cmd(pudev, lun); + + case SCSI_READ_TOC_DATA: + return scsi_toc_cmd_read(pudev, lun, params); + + case SCSI_MODE_SELECT6: + return scsi_mode_select6(pudev, lun, params); + + case SCSI_MODE_SELECT10: + return scsi_mode_select10(pudev, lun, params); + + default: + scsi_sense_code(pudev, lun, ILLEGAL_REQUEST, INVALID_CDB); + return -1; + } +} + +/*! + \brief load the last error code in the error list + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] skey: sense key + \param[in] asc: additional aense key + \param[out] none + \retval none +*/ +void scsi_sense_code(usb_core_driver *pudev, uint8_t lun, uint8_t skey, uint8_t asc) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->scsi_sense[msc->scsi_sense_tail].SenseKey = skey; + msc->scsi_sense[msc->scsi_sense_tail].ASC = asc << 8U; + msc->scsi_sense_tail++; + + if(SENSE_LIST_DEEPTH == msc->scsi_sense_tail) { + msc->scsi_sense_tail = 0U; + } +} + +/*! + \brief process SCSI Test Unit Ready command + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_test_unit_ready(usb_core_driver *pudev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + /* case 9 : Hi > D0 */ + if(0U != msc->bbb_cbw.dCBWDataTransferLength) { + scsi_sense_code(pudev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + return -1; + } + + if(0 != usbd_mem_fops->mem_ready(lun)) { + scsi_sense_code(pudev, lun, NOT_READY, MEDIUM_NOT_PRESENT); + + return -1; + } + + msc->bbb_datalen = 0U; + + return 0; +} + +/*! + \brief process Inquiry command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_mode_select6(usb_core_driver *pudev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_datalen = 0U; + + return 0; +} + +/*! + \brief process Inquiry command + \param[in] udev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_mode_select10(usb_core_driver *pudev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_datalen = 0U; + + return 0; +} + +/*! + \brief process Inquiry command + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_inquiry(usb_core_driver *pudev, uint8_t lun, uint8_t *params) +{ + uint8_t *page = NULL; + uint16_t len = 0U; + + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + if(params[1] & 0x01U) { + /* Evpd is set */ + page = (uint8_t *)msc_page00_inquiry_data; + + len = INQUIRY_PAGE00_LENGTH; + } else { + page = (uint8_t *)usbd_mem_fops->mem_inquiry_data[lun]; + + len = (uint16_t)(page[4] + 5U); + + if(params[4] <= len) { + len = params[4]; + } + } + + msc->bbb_datalen = len; + + while(len) { + len--; + msc->bbb_data[len] = page[len]; + } + + return 0; +} + +/*! + \brief process Read Capacity 10 command + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_read_capacity10(usb_core_driver *pudev, uint8_t lun, uint8_t *params) +{ + uint32_t blk_num = usbd_mem_fops->mem_block_len[lun] - 1U; + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->scsi_blk_nbr[lun] = usbd_mem_fops->mem_block_len[lun]; + msc->scsi_blk_size[lun] = usbd_mem_fops->mem_block_size[lun]; + + msc->bbb_data[0] = (uint8_t)(blk_num >> 24U); + msc->bbb_data[1] = (uint8_t)(blk_num >> 16U); + msc->bbb_data[2] = (uint8_t)(blk_num >> 8U); + msc->bbb_data[3] = (uint8_t)(blk_num); + + msc->bbb_data[4] = (uint8_t)(msc->scsi_blk_size[lun] >> 24U); + msc->bbb_data[5] = (uint8_t)(msc->scsi_blk_size[lun] >> 16U); + msc->bbb_data[6] = (uint8_t)(msc->scsi_blk_size[lun] >> 8U); + msc->bbb_data[7] = (uint8_t)(msc->scsi_blk_size[lun]); + + msc->bbb_datalen = 8U; + + return 0; +} + +/*! + \brief process Read Format Capacity command + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_read_format_capacity(usb_core_driver *pudev, uint8_t lun, uint8_t *params) +{ + uint16_t i = 0U; + uint32_t blk_size = usbd_mem_fops->mem_block_size[lun]; + uint32_t blk_num = usbd_mem_fops->mem_block_len[lun]; + uint32_t blk_nbr = blk_num - 1U; + + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + for(i = 0U; i < 12U; i++) { + msc->bbb_data[i] = 0U; + } + + msc->bbb_data[3] = 0x08U; + msc->bbb_data[4] = (uint8_t)(blk_nbr >> 24U); + msc->bbb_data[5] = (uint8_t)(blk_nbr >> 16U); + msc->bbb_data[6] = (uint8_t)(blk_nbr >> 8U); + msc->bbb_data[7] = (uint8_t)(blk_nbr); + + msc->bbb_data[8] = 0x02U; + msc->bbb_data[9] = (uint8_t)(blk_size >> 16U); + msc->bbb_data[10] = (uint8_t)(blk_size >> 8U); + msc->bbb_data[11] = (uint8_t)(blk_size); + + msc->bbb_datalen = 12U; + + return 0; +} + +/*! + \brief process Mode Sense6 command + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_mode_sense6(usb_core_driver *pudev, uint8_t lun, uint8_t *params) +{ + uint16_t len = 8U; + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_datalen = len; + + while(len) { + len--; + msc->bbb_data[len] = msc_mode_sense6_data[len]; + } + + return 0; +} + +/*! + \brief process Mode Sense10 command + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_mode_sense10(usb_core_driver *pudev, uint8_t lun, uint8_t *params) +{ + uint16_t len = 8U; + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_datalen = len; + + while(len) { + len--; + msc->bbb_data[len] = msc_mode_sense10_data[len]; + } + + return 0; +} + +/*! + \brief process Request Sense command + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_request_sense(usb_core_driver *pudev, uint8_t lun, uint8_t *params) +{ + uint8_t i = 0U; + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + for(i = 0U; i < REQUEST_SENSE_DATA_LEN; i++) { + msc->bbb_data[i] = 0U; + } + + msc->bbb_data[0] = 0x70U; + msc->bbb_data[7] = REQUEST_SENSE_DATA_LEN - 6U; + + if((msc->scsi_sense_head != msc->scsi_sense_tail)) { + msc->bbb_data[2] = msc->scsi_sense[msc->scsi_sense_head].SenseKey; + msc->bbb_data[12] = msc->scsi_sense[msc->scsi_sense_head].ASCQ; + msc->bbb_data[13] = msc->scsi_sense[msc->scsi_sense_head].ASC; + msc->scsi_sense_head++; + + if(msc->scsi_sense_head == SENSE_LIST_DEEPTH) { + msc->scsi_sense_head = 0U; + } + } + + msc->bbb_datalen = USB_MIN(REQUEST_SENSE_DATA_LEN, params[4]); + + return 0; +} + +/*! + \brief process Start Stop Unit command + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static inline int8_t scsi_start_stop_unit(usb_core_driver *pudev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_datalen = 0U; + msc->scsi_disk_pop = 1U; + + return 0; +} + +/*! + \brief process Allow Medium Removal command + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static inline int8_t scsi_allow_medium_removal(usb_core_driver *pudev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + msc->bbb_datalen = 0U; + + return 0; +} + +/*! + \brief process Read10 command + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_read10(usb_core_driver *pudev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + if(msc->bbb_state == BBB_IDLE) { + /* direction is from device to host */ + if(0x80U != (msc->bbb_cbw.bmCBWFlags & 0x80U)) { + scsi_sense_code(pudev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + return -1; + } + + if(0 != usbd_mem_fops->mem_ready(lun)) { + scsi_sense_code(pudev, lun, NOT_READY, MEDIUM_NOT_PRESENT); + + return -1; + } + + msc->scsi_blk_addr = (params[2] << 24U) | (params[3] << 16U) | \ + (params[4] << 8U) | params[5]; + + msc->scsi_blk_len = (params[7] << 8U) | params[8]; + + if(scsi_check_address_range(pudev, lun, msc->scsi_blk_addr, (uint16_t)msc->scsi_blk_len) < 0) { + return -1; /* error */ + } + + msc->bbb_state = BBB_DATA_IN; + + msc->scsi_blk_addr *= msc->scsi_blk_size[lun]; + msc->scsi_blk_len *= msc->scsi_blk_size[lun]; + + /* cases 4,5 : Hi <> Dn */ + if(msc->bbb_cbw.dCBWDataTransferLength != msc->scsi_blk_len) { + scsi_sense_code(pudev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + return -1; + } + } + + msc->bbb_datalen = MSC_MEDIA_PACKET_SIZE; + + return scsi_process_read(pudev, lun); +} + +/*! + \brief process Write10 command + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_write10(usb_core_driver *pudev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + if(BBB_IDLE == msc->bbb_state) { + /* case 8 : Hi <> Do */ + if(0x80U == (msc->bbb_cbw.bmCBWFlags & 0x80U)) { + scsi_sense_code(pudev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + return -1; + } + + /* check whether media is ready */ + if(0 != usbd_mem_fops->mem_ready(lun)) { + scsi_sense_code(pudev, lun, NOT_READY, MEDIUM_NOT_PRESENT); + + return -1; + } + + /* check if media is write-protected */ + if(0 != usbd_mem_fops->mem_protected(lun)) { + scsi_sense_code(pudev, lun, NOT_READY, WRITE_PROTECTED); + + return -1; + } + + msc->scsi_blk_addr = (params[2] << 24U) | (params[3] << 16U) | \ + (params[4] << 8U) | params[5]; + + msc->scsi_blk_len = (params[7] << 8U) | params[8]; + + /* check if LBA address is in the right range */ + if(scsi_check_address_range(pudev, lun, msc->scsi_blk_addr, (uint16_t)msc->scsi_blk_len) < 0) { + return -1; /* error */ + } + + msc->scsi_blk_addr *= msc->scsi_blk_size[lun]; + msc->scsi_blk_len *= msc->scsi_blk_size[lun]; + + /* cases 3,11,13 : Hn,Ho <> D0 */ + if(msc->bbb_cbw.dCBWDataTransferLength != msc->scsi_blk_len) { + scsi_sense_code(pudev, msc->bbb_cbw.bCBWLUN, ILLEGAL_REQUEST, INVALID_CDB); + + return -1; + } + + /* prepare endpoint to receive first data packet */ + msc->bbb_state = BBB_DATA_OUT; + + usbd_ep_recev(pudev, + MSC_OUT_EP, + msc->bbb_data, + USB_MIN(msc->scsi_blk_len, MSC_MEDIA_PACKET_SIZE)); + } else { /* write process ongoing */ + return scsi_process_write(pudev, lun); + } + + return 0; +} + +/*! + \brief process Verify10 command + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_verify10(usb_core_driver *pudev, uint8_t lun, uint8_t *params) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + if(0x02U == (params[1] & 0x02U)) { + scsi_sense_code(pudev, lun, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND); + + return -1; /* error, verify mode not supported*/ + } + + if(scsi_check_address_range(pudev, lun, msc->scsi_blk_addr, (uint16_t)msc->scsi_blk_len) < 0) { + return -1; /* error */ + } + + msc->bbb_datalen = 0U; + + return 0; +} + +/*! + \brief check address range + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] blk_offset: block offset + \param[in] blk_nbr: number of block to be processed + \param[out] none + \retval status +*/ +static inline int8_t scsi_check_address_range(usb_core_driver *pudev, uint8_t lun, uint32_t blk_offset, uint16_t blk_nbr) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + if((blk_offset + blk_nbr) > msc->scsi_blk_nbr[lun]) { + scsi_sense_code(pudev, lun, ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE); + + return -1; + } + + return 0; +} + +/*! + \brief handle read process + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[out] none + \retval status +*/ +static int8_t scsi_process_read(usb_core_driver *pudev, uint8_t lun) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + uint32_t len = USB_MIN(msc->scsi_blk_len, MSC_MEDIA_PACKET_SIZE); + + if(usbd_mem_fops->mem_read(lun, + msc->bbb_data, + msc->scsi_blk_addr, + (uint16_t)(len / msc->scsi_blk_size[lun])) < 0) { + scsi_sense_code(pudev, lun, HARDWARE_ERROR, UNRECOVERED_READ_ERROR); + + return -1; + } + + usbd_ep_send(pudev, MSC_IN_EP, msc->bbb_data, len); + + msc->scsi_blk_addr += len; + msc->scsi_blk_len -= len; + + /* case 6 : Hi = Di */ + msc->bbb_csw.dCSWDataResidue -= len; + + if(0U == msc->scsi_blk_len) { + msc->bbb_state = BBB_LAST_DATA_IN; + } + + return 0; +} + +/*! + \brief handle write process + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[out] none + \retval status +*/ +static int8_t scsi_process_write(usb_core_driver *pudev, uint8_t lun) +{ + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + uint32_t len = USB_MIN(msc->scsi_blk_len, MSC_MEDIA_PACKET_SIZE); + + if(usbd_mem_fops->mem_write(lun, + msc->bbb_data, + msc->scsi_blk_addr, + (uint16_t)(len / msc->scsi_blk_size[lun])) < 0) { + scsi_sense_code(pudev, lun, HARDWARE_ERROR, WRITE_FAULT); + + return -1; + } + + msc->scsi_blk_addr += len; + msc->scsi_blk_len -= len; + + /* case 12 : Ho = Do */ + msc->bbb_csw.dCSWDataResidue -= len; + + if(0U == msc->scsi_blk_len) { + msc_bbb_csw_send(pudev, CSW_CMD_PASSED); + } else { + /* prapare endpoint to receive next packet */ + usbd_ep_recev(pudev, + MSC_OUT_EP, + msc->bbb_data, + USB_MIN(msc->scsi_blk_len, MSC_MEDIA_PACKET_SIZE)); + } + + return 0; +} + +/*! + \brief process Format Unit command + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[out] none + \retval status +*/ +static inline int8_t scsi_format_cmd(usb_core_driver *pudev, uint8_t lun) +{ + return 0; +} + +/*! + \brief process Read_Toc command + \param[in] pudev: pointer to USB device instance + \param[in] lun: logical unit number + \param[in] params: command parameters + \param[out] none + \retval status +*/ +static int8_t scsi_toc_cmd_read(usb_core_driver *pudev, uint8_t lun, uint8_t *params) +{ + uint8_t *pPage; + uint16_t len; + + usbd_msc_handler *msc = (usbd_msc_handler *)pudev->dev.class_data[USBD_MSC_INTERFACE]; + + pPage = (uint8_t *)&usbd_mem_fops->mem_toc_data[lun * READ_TOC_CMD_LEN]; + len = (uint16_t)pPage[1] + 2U; + + msc->bbb_datalen = len; + + while(len) { + len--; + msc->bbb_data[len] = pPage[len]; + } + + return 0; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/printer/Include/printer_core.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/printer/Include/printer_core.h new file mode 100644 index 000000000..adf18f067 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/printer/Include/printer_core.h @@ -0,0 +1,77 @@ +/*! + \file printer_core.h + \brief the header file of USB printer device class core functions + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __PRINTER_CORE_H +#define __PRINTER_CORE_H + +#include "usbd_enum.h" +#include "usb_ch9_std.h" + +/* USB printing device class code */ +#define USB_CLASS_PRINTER 0x07U + +/* printing device subclass code */ +#define USB_SUBCLASS_PRINTER 0x01U + +/* printing device protocol code */ +#define PROTOCOL_UNIDIRECTIONAL_ITF 0x01U +#define PROTOCOL_BI_DIRECTIONAL_ITF 0x02U +#define PROTOCOL_1284_4_ITF 0x03U +#define PROTOCOL_VENDOR 0xFFU + +#define DEVICE_ID_LEN 103U + +#define USB_PRINTER_CONFIG_DESC_LEN 32U + +/* printing device specific-class request */ +#define GET_DEVICE_ID 0x00U +#define GET_PORT_STATUS 0x01U +#define SOFT_RESET 0x02U + +#pragma pack(1) + +/* USB configuration descriptor struct */ +typedef struct { + usb_desc_config config; + usb_desc_itf printer_itf; + usb_desc_ep printer_epin; + usb_desc_ep printer_epout; +} usb_printer_desc_config_set; + +#pragma pack() + +extern usb_desc printer_desc; +extern usb_class_core usbd_printer_cb; + +#endif /* __PRINTER_CORE_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/printer/Source/printer_core.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/printer/Source/printer_core.c new file mode 100644 index 000000000..e82d8f737 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/class/printer/Source/printer_core.c @@ -0,0 +1,301 @@ +/*! + \file printer_core.c + \brief USB printer device class core functions + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "printer_core.h" + +#define USBD_VID 0x28E9U +#define USBD_PID 0x028DU + +/* printer port status: paper not empty/selected/no error */ +static uint8_t g_port_status = 0x18U; + +uint8_t g_printer_data_buf[PRINTER_OUT_PACKET]; + +uint8_t PRINTER_DEVICE_ID[DEVICE_ID_LEN] = { + 0x00, 0x67, + 'M', 'A', 'N', 'U', 'F', 'A', 'C', 'T', 'U', 'R', 'E', 'R', ':', + 'G', 'I', 'G', 'A', ' ', 'D', 'E', 'V', 'I', 'C', 'E', '-', ';', + 'C', 'O', 'M', 'M', 'A', 'N', 'D', ' ', 'S', 'E', 'T', ':', + 'P', 'C', 'L', ',', 'M', 'P', 'L', ';', + 'M', 'O', 'D', 'E', 'L', ':', + 'L', 'a', 's', 'e', 'r', 'B', 'e', 'a', 'm', '?', ';', + 'C', 'O', 'M', 'M', 'E', 'N', 'T', ':', + 'G', 'o', 'o', 'd', ' ', '!', ';', + 'A', 'C', 'T', 'I', 'V', 'E', ' ', 'C', 'O', 'M', 'M', 'A', 'N', 'D', ' ', 'S', 'E', 'T', ':', + 'P', 'C', 'L', ';' +}; + +/* USB standard device descriptor */ +const usb_desc_dev printer_dev_desc = { + .header = + { + .bLength = USB_DEV_DESC_LEN, + .bDescriptorType = USB_DESCTYPE_DEV, + }, + .bcdUSB = 0x0200U, + .bDeviceClass = 0x00U, + .bDeviceSubClass = 0x00U, + .bDeviceProtocol = 0x00U, + .bMaxPacketSize0 = USB_FS_EP0_MAX_LEN, + .idVendor = USBD_VID, + .idProduct = USBD_PID, + .bcdDevice = 0x0100U, + .iManufacturer = STR_IDX_MFC, + .iProduct = STR_IDX_PRODUCT, + .iSerialNumber = STR_IDX_SERIAL, + .bNumberConfigurations = USBD_CFG_MAX_NUM, +}; +/* USB device configuration descriptor */ +const usb_printer_desc_config_set printer_config_desc = { + .config = + { + .header = + { + .bLength = sizeof(usb_desc_config), + .bDescriptorType = USB_DESCTYPE_CONFIG + }, + .wTotalLength = USB_PRINTER_CONFIG_DESC_LEN, + .bNumInterfaces = 0x01U, + .bConfigurationValue = 0x01U, + .iConfiguration = 0x00U, + .bmAttributes = 0xA0U, + .bMaxPower = 0x32U + }, + + .printer_itf = + { + .header = + { + .bLength = sizeof(usb_desc_itf), + .bDescriptorType = USB_DESCTYPE_ITF + }, + .bInterfaceNumber = 0x00U, + .bAlternateSetting = 0x00U, + .bNumEndpoints = 0x02U, + .bInterfaceClass = USB_CLASS_PRINTER, + .bInterfaceSubClass = USB_SUBCLASS_PRINTER, + .bInterfaceProtocol = PROTOCOL_BI_DIRECTIONAL_ITF, + .iInterface = 0x00U + }, + + .printer_epin = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = PRINTER_IN_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = PRINTER_IN_PACKET, + .bInterval = 0x00U + }, + + .printer_epout = + { + .header = + { + .bLength = sizeof(usb_desc_ep), + .bDescriptorType = USB_DESCTYPE_EP + }, + .bEndpointAddress = PRINTER_OUT_EP, + .bmAttributes = USB_EP_ATTR_BULK, + .wMaxPacketSize = PRINTER_OUT_PACKET, + .bInterval = 0x00U + }, +}; + +/* USB language ID Descriptor */ +static const usb_desc_LANGID usbd_language_id_desc = { + .header = + { + .bLength = sizeof(usb_desc_LANGID), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .wLANGID = ENG_LANGID +}; + +/* USB manufacture string */ +static const usb_desc_str manufacturer_string = { + .header = + { + .bLength = USB_STRING_LEN(10U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'i', 'g', 'a', 'D', 'e', 'v', 'i', 'c', 'e'} +}; + +/* USB product string */ +static const usb_desc_str product_string = { + .header = + { + .bLength = USB_STRING_LEN(16U), + .bDescriptorType = USB_DESCTYPE_STR, + }, + .unicode_string = {'G', 'D', '3', '2', '-', 'U', 'S', 'B', '_', 'P', 'r', 'i', 'n', 't', 'e', 'r'} +}; + +/* USBD serial string */ +static usb_desc_str serial_string = { + .header = + { + .bLength = USB_STRING_LEN(12U), + .bDescriptorType = USB_DESCTYPE_STR, + } +}; + +/* USB string descriptor */ +static void *const usbd_msc_strings[] = { + [STR_IDX_LANGID] = (uint8_t *) &usbd_language_id_desc, + [STR_IDX_MFC] = (uint8_t *) &manufacturer_string, + [STR_IDX_PRODUCT] = (uint8_t *) &product_string, + [STR_IDX_SERIAL] = (uint8_t *) &serial_string +}; + +usb_desc printer_desc = { + .dev_desc = (uint8_t *) &printer_dev_desc, + .config_desc = (uint8_t *) &printer_config_desc, + .strings = usbd_msc_strings +}; + +/* local function prototypes ('static') */ +static uint8_t printer_init(usb_dev *udev, uint8_t config_index); +static uint8_t printer_deinit(usb_dev *udev, uint8_t config_index); +static uint8_t printer_req(usb_dev *udev, usb_req *req); +static uint8_t printer_in(usb_dev *udev, uint8_t ep_num); +static uint8_t printer_out(usb_dev *udev, uint8_t ep_num); + +usb_class_core usbd_printer_cb = { + .init = printer_init, + .deinit = printer_deinit, + + .req_proc = printer_req, + + .data_in = printer_in, + .data_out = printer_out +}; + +/*! + \brief initialize the printer device + \param[in] udev: pointer to usb device instance + \param[in] config_index: configuration index + \param[out] none + \retval usb device operation status +*/ +static uint8_t printer_init(usb_dev *udev, uint8_t config_index) +{ + /* initialize the data Tx endpoint */ + usbd_ep_setup(udev, &(printer_config_desc.printer_epin)); + + /* initialize the data Rx endpoint */ + usbd_ep_setup(udev, &(printer_config_desc.printer_epout)); + + /* prepare to receive data */ + usbd_ep_recev(udev, PRINTER_OUT_EP, g_printer_data_buf, PRINTER_OUT_PACKET); + + return USBD_OK; +} + +/*! + \brief de-initialize the printer device + \param[in] udev: pointer to usb device instance + \param[in] config_index: configuration index + \param[out] none + \retval usb device operation status +*/ +static uint8_t printer_deinit(usb_dev *udev, uint8_t config_index) +{ + /* deinitialize the data Tx/Rx endpoint */ + usbd_ep_clear(udev, PRINTER_IN_EP); + usbd_ep_clear(udev, PRINTER_OUT_EP); + + return USBD_OK; +} + +/*! + \brief handle the printer class-specific requests + \param[in] udev: pointer to usb device instance + \param[in] req: device class-specific request + \param[out] none + \retval usb device operation status +*/ +static uint8_t printer_req(usb_dev *udev, usb_req *req) +{ + usb_transc *transc = &udev->dev.transc_in[0]; + + switch(req->bRequest) { + case GET_DEVICE_ID: + transc->xfer_buf = (uint8_t *)PRINTER_DEVICE_ID; + transc->remain_len = DEVICE_ID_LEN; + break; + + case GET_PORT_STATUS: + transc->xfer_buf = (uint8_t *)&g_port_status; + transc->remain_len = 1U; + break; + + case SOFT_RESET: + usbd_ep_recev(udev, PRINTER_OUT_EP, g_printer_data_buf, PRINTER_OUT_PACKET); + break; + + default: + return USBD_FAIL; + } + + return USBD_OK; +} + +/*! + \brief handle printer data + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval USB device operation status +*/ +static uint8_t printer_in(usb_dev *udev, uint8_t ep_num) +{ + return USBD_OK; +} + +/*! + \brief handle printer data + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval USB device operation status +*/ +static uint8_t printer_out(usb_dev *udev, uint8_t ep_num) +{ + return USBD_OK; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Include/usbd_core.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Include/usbd_core.h new file mode 100644 index 000000000..68788433c --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Include/usbd_core.h @@ -0,0 +1,102 @@ +/*! + \file usbd_core.h + \brief USB device mode core functions protype + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_CORE_H +#define __USBD_CORE_H + +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +typedef enum { + USBD_OK = 0U, /*!< status OK */ + USBD_BUSY, /*!< status busy */ + USBD_FAIL, /*!< status fail */ +} usbd_status; + +enum _usbd_status { + USBD_DEFAULT = 1U, /*!< default status */ + USBD_ADDRESSED = 2U, /*!< address send status */ + USBD_CONFIGURED = 3U, /*!< configured status */ + USBD_SUSPENDED = 4U /*!< suspended status */ +}; + +/* static inline function definitions */ + +/*! + \brief set USB device address + \param[in] udev: pointer to USB core instance + \param[in] addr: device address to set + \param[out] none + \retval none +*/ +__STATIC_INLINE void usbd_addr_set(usb_core_driver *udev, uint8_t addr) +{ + usb_devaddr_set(udev, addr); +} + +/*! + \brief get the received data length + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint number + \param[out] none + \retval USB device operation cur_status +*/ +__STATIC_INLINE uint16_t usbd_rxcount_get(usb_core_driver *udev, uint8_t ep_num) +{ + return (uint16_t)udev->dev.transc_out[ep_num].xfer_count; +} + +/* function declarations */ +/* initializes the USB device-mode stack and load the class driver */ +void usbd_init(usb_core_driver *udev, usb_core_enum core, usb_desc *desc, usb_class_core *class_core); +/* endpoint initialization */ +uint32_t usbd_ep_setup(usb_core_driver *udev, const usb_desc_ep *ep_desc); +/* configure the endpoint when it is disabled */ +uint32_t usbd_ep_clear(usb_core_driver *udev, uint8_t ep_addr); +/* endpoint prepare to receive data */ +uint32_t usbd_ep_recev(usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint32_t len); +/* endpoint prepare to transmit data */ +uint32_t usbd_ep_send(usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint32_t len); +/* set an endpoint to STALL status */ +uint32_t usbd_ep_stall(usb_core_driver *udev, uint8_t ep_addr); +/* clear endpoint STALLed status */ +uint32_t usbd_ep_stall_clear(usb_core_driver *udev, uint8_t ep_addr); +/* flush the endpoint FIFOs */ +uint32_t usbd_fifo_flush(usb_core_driver *udev, uint8_t ep_addr); +/* device connect */ +void usbd_connect(usb_core_driver *udev); +/* device disconnect */ +void usbd_disconnect(usb_core_driver *udev); + +#endif /* __USBD_CORE_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Include/usbd_enum.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Include/usbd_enum.h new file mode 100644 index 000000000..6732841b2 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Include/usbd_enum.h @@ -0,0 +1,103 @@ +/*! + \file usbd_enum.h + \brief USB enumeration definitions + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_ENUM_H +#define __USBD_ENUM_H + +#include "usbd_core.h" +#include "usbd_conf.h" +#include + +#ifndef NULL +#define NULL 0U +#endif + +typedef enum _usb_reqsta { + REQ_SUPP = 0x0U, /* request support */ + REQ_NOTSUPP = 0x1U, /* request not support */ +} usb_reqsta; + +/* string descriptor index */ +enum _str_index { + STR_IDX_LANGID = 0x0U, /* language ID string index */ + STR_IDX_MFC = 0x1U, /* manufacturer string index */ + STR_IDX_PRODUCT = 0x2U, /* product string index */ + STR_IDX_SERIAL = 0x3U, /* serial string index */ + STR_IDX_CONFIG = 0x4U, /* configuration string index */ + STR_IDX_ITF = 0x5U, /* interface string index */ +#ifndef WINUSB_EXEMPT_DRIVER + STR_IDX_MAX = 0x6U, /* string maximum index */ +#else + STR_IDX_MAX = 0xEFU, /* string maximum index */ +#endif /* WINUSB_EXEMPT_DRIVER */ +}; + +typedef enum _usb_pwrsta { + USB_PWRSTA_SELF_POWERED = 0x1U, /* USB is in self powered status */ + USB_PWRSTA_REMOTE_WAKEUP = 0x2U, /* USB is in remote wakeup status */ +} usb_pwrsta; + +typedef enum _usb_feature { + USB_FEATURE_EP_HALT = 0x0U, /* USB has endpoint halt feature */ + USB_FEATURE_REMOTE_WAKEUP = 0x1U, /* USB has endpoint remote wakeup feature */ + USB_FEATURE_TEST_MODE = 0x2U, /* USB has endpoint test mode feature */ +} usb_feature; + +#define ENG_LANGID 0x0409U /* english language ID */ +#define CHN_LANGID 0x0804U /* chinese language ID */ + +/* USB device exported macros */ +#define CTL_EP(ep) (((ep) == 0x00U) || ((ep) == 0x80U)) + +#define DEVICE_ID1 (0x1FFFF7E8U) /* device ID1 */ +#define DEVICE_ID2 (0x1FFFF7ECU) /* device ID2 */ +#define DEVICE_ID3 (0x1FFFF7F0U) /* device ID3 */ + +#define DEVICE_ID (0x40022100U) + +/* function declarations */ +/* handle USB standard device request */ +usb_reqsta usbd_standard_request(usb_core_driver *udev, usb_req *req); +/* handle USB device class request */ +usb_reqsta usbd_class_request(usb_core_driver *udev, usb_req *req); +/* handle USB vendor request */ +usb_reqsta usbd_vendor_request(usb_core_driver *udev, usb_req *req); +/* handle USB enumeration error */ +void usbd_enum_error(usb_core_driver *udev, usb_req *req); +/* convert hex 32bits value into unicode char */ +void int_to_unicode(uint32_t value, uint8_t *pbuf, uint8_t len); +/* get serial string */ +void serial_string_get(uint16_t *unicode_str); + +#endif /* __USBD_ENUM_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Include/usbd_transc.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Include/usbd_transc.h new file mode 100644 index 000000000..667643327 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Include/usbd_transc.h @@ -0,0 +1,56 @@ +/*! + \file usbd_transc.h + \brief USB transaction core functions prototype + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBD_TRANSC_H +#define __USBD_TRANSC_H + +#include "usbd_core.h" + +/* function declarations */ +/* USB send data in the control transaction */ +usbd_status usbd_ctl_send(usb_core_driver *udev); +/* USB receive data in control transaction */ +usbd_status usbd_ctl_recev(usb_core_driver *udev); +/* USB send control transaction status */ +usbd_status usbd_ctl_status_send(usb_core_driver *udev); +/* USB control receive status */ +usbd_status usbd_ctl_status_recev(usb_core_driver *udev); +/* USB setup stage processing */ +uint8_t usbd_setup_transc(usb_core_driver *udev); +/* data out stage processing */ +uint8_t usbd_out_transc(usb_core_driver *udev, uint8_t ep_num); +/* data in stage processing */ +uint8_t usbd_in_transc(usb_core_driver *udev, uint8_t ep_num); + +#endif /* __USBD_TRANSC_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Source/usbd_core.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Source/usbd_core.c new file mode 100644 index 000000000..f3a1eafa5 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Source/usbd_core.c @@ -0,0 +1,320 @@ +/*! + \file usbd_core.c + \brief USB device mode core functions + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_core.h" +#include "usbd_enum.h" +#include "drv_usb_hw.h" + +/* endpoint type */ +const uint32_t ep_type[] = { + [USB_EP_ATTR_CTL] = (uint32_t)USB_EPTYPE_CTRL, + [USB_EP_ATTR_BULK] = (uint32_t)USB_EPTYPE_BULK, + [USB_EP_ATTR_INT] = (uint32_t)USB_EPTYPE_INTR, + [USB_EP_ATTR_ISO] = (uint32_t)USB_EPTYPE_ISOC +}; + +/*! + \brief initializes the USB device-mode stack and load the class driver + \param[in] udev: pointer to USB core instance + \param[in] core: USB core type + \param[in] desc: pointer to USB descriptor + \param[in] class_core: class driver + \param[out] none + \retval none +*/ +void usbd_init(usb_core_driver *udev, usb_core_enum core, usb_desc *desc, usb_class_core *class_core) +{ + udev->dev.desc = desc; + + /* class callbacks */ + udev->dev.class_core = class_core; + + /* create serial string */ + serial_string_get(udev->dev.desc->strings[STR_IDX_SERIAL]); + + /* configure USB capabilities */ + (void)usb_basic_init(&udev->bp, &udev->regs, core); + + usb_globalint_disable(&udev->regs); + + /* initializes the USB core*/ + (void)usb_core_init(udev->bp, &udev->regs); + + /* set device disconnect */ + usbd_disconnect(udev); + +#ifndef USE_OTG_MODE + usb_curmode_set(&udev->regs, DEVICE_MODE); +#endif + + /* initializes device mode */ + (void)usb_devcore_init(udev); + + usb_globalint_enable(&udev->regs); + + /* set device connect */ + usbd_connect(udev); + + udev->dev.cur_status = (uint8_t)USBD_DEFAULT; +} + +/*! + \brief endpoint initialization + \param[in] udev: pointer to USB core instance + \param[in] ep_desc: pointer to endpoint descriptor + \param[out] none + \retval none +*/ +uint32_t usbd_ep_setup(usb_core_driver *udev, const usb_desc_ep *ep_desc) +{ + usb_transc *transc; + + uint8_t ep_addr = ep_desc->bEndpointAddress; + uint16_t max_len = ep_desc->wMaxPacketSize; + + /* set endpoint direction */ + if(EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + + transc->ep_addr.dir = 1U; + } else { + transc = &udev->dev.transc_out[ep_addr]; + + transc->ep_addr.dir = 0U; + } + + transc->ep_addr.num = EP_ID(ep_addr); + transc->max_len = max_len; + transc->ep_type = (uint8_t)ep_type[ep_desc->bmAttributes & (uint8_t)USB_EPTYPE_MASK]; + + /* active USB endpoint function */ + (void)usb_transc_active(udev, transc); + + return 0U; +} + +/*! + \brief configure the endpoint when it is disabled + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_clear(usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc; + + if(EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + /* deactivate USB endpoint function */ + (void)usb_transc_deactivate(udev, transc); + + return 0U; +} + +/*! + \brief endpoint prepare to receive data + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: user buffer address pointer + \param[in] len: buffer length + \param[out] none + \retval none +*/ +uint32_t usbd_ep_recev(usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint32_t len) +{ + usb_transc *transc = &udev->dev.transc_out[EP_ID(ep_addr)]; + + /* setup the transfer */ + transc->xfer_buf = pbuf; + transc->xfer_len = len; + transc->xfer_count = 0U; + + if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + transc->dma_addr = (uint32_t)pbuf; + } + + /* start the transfer */ + (void)usb_transc_outxfer(udev, transc); + + return 0U; +} + +/*! + \brief endpoint prepare to transmit data + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[in] pbuf: transmit buffer address pointer + \param[in] len: buffer length + \param[out] none + \retval none +*/ +uint32_t usbd_ep_send(usb_core_driver *udev, uint8_t ep_addr, uint8_t *pbuf, uint32_t len) +{ + usb_transc *transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + + /* setup the transfer */ + transc->xfer_buf = pbuf; + transc->xfer_len = len; + transc->xfer_count = 0U; + + if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + transc->dma_addr = (uint32_t)pbuf; + } + + /* start the transfer */ + (void)usb_transc_inxfer(udev, transc); + + return 0U; +} + +/*! + \brief set an endpoint to STALL status + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_stall(usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc = NULL; + + if(EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + transc->ep_stall = 1U; + + (void)usb_transc_stall(udev, transc); + + return (0U); +} + +/*! + \brief clear endpoint STALLed status + \param[in] udev: pointer to usb core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_ep_stall_clear(usb_core_driver *udev, uint8_t ep_addr) +{ + usb_transc *transc = NULL; + + if(EP_DIR(ep_addr)) { + transc = &udev->dev.transc_in[EP_ID(ep_addr)]; + } else { + transc = &udev->dev.transc_out[ep_addr]; + } + + transc->ep_stall = 0U; + + (void)usb_transc_clrstall(udev, transc); + + return (0U); +} + +/*! + \brief flush the endpoint FIFOs + \param[in] udev: pointer to USB core instance + \param[in] ep_addr: endpoint address + in this parameter: + bit0..bit6: endpoint number (0..7) + bit7: endpoint direction which can be IN(1) or OUT(0) + \param[out] none + \retval none +*/ +uint32_t usbd_fifo_flush(usb_core_driver *udev, uint8_t ep_addr) +{ + if(EP_DIR(ep_addr)) { + (void)usb_txfifo_flush(&udev->regs, EP_ID(ep_addr)); + } else { + (void)usb_rxfifo_flush(&udev->regs); + } + + return (0U); +} + +/*! + \brief device connect + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_connect(usb_core_driver *udev) +{ +#ifndef USE_OTG_MODE + /* connect device */ + usb_dev_connect(udev); + + usb_mdelay(3U); +#endif /* USE_OTG_MODE */ +} + +/*! + \brief device disconnect + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_disconnect(usb_core_driver *udev) +{ +#ifndef USE_OTG_MODE + /* disconnect device for 3ms */ + usb_dev_disconnect(udev); + + usb_mdelay(3U); +#endif /* USE_OTG_MODE */ +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Source/usbd_enum.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Source/usbd_enum.c new file mode 100644 index 000000000..7ebe53f07 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Source/usbd_enum.c @@ -0,0 +1,764 @@ +/*! + \file usbd_enum.c + \brief USB enumeration function + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 + \version 2021-09-27, V3.0.1, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_enum.h" +#include "usb_ch9_std.h" + +#ifdef WINUSB_EXEMPT_DRIVER + +extern usbd_status usbd_OEM_req(usb_dev *udev, usb_req *req); + +#endif /* WINUSB_EXEMPT_DRIVER */ + +/* local function prototypes ('static') */ +static usb_reqsta _usb_std_reserved(usb_core_driver *udev, usb_req *req); +static uint8_t *_usb_dev_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t *_usb_config_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t *_usb_bos_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len); +static uint8_t *_usb_str_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len); +static usb_reqsta _usb_std_getstatus(usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_clearfeature(usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setfeature(usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setaddress(usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getdescriptor(usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setdescriptor(usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getconfiguration(usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setconfiguration(usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_getinterface(usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_setinterface(usb_core_driver *udev, usb_req *req); +static usb_reqsta _usb_std_synchframe(usb_core_driver *udev, usb_req *req); + +static usb_reqsta(*_std_dev_req[])(usb_core_driver *udev, usb_req *req) = { + [USB_GET_STATUS] = _usb_std_getstatus, + [USB_CLEAR_FEATURE] = _usb_std_clearfeature, + [USB_RESERVED2] = _usb_std_reserved, + [USB_SET_FEATURE] = _usb_std_setfeature, + [USB_RESERVED4] = _usb_std_reserved, + [USB_SET_ADDRESS] = _usb_std_setaddress, + [USB_GET_DESCRIPTOR] = _usb_std_getdescriptor, + [USB_SET_DESCRIPTOR] = _usb_std_setdescriptor, + [USB_GET_CONFIGURATION] = _usb_std_getconfiguration, + [USB_SET_CONFIGURATION] = _usb_std_setconfiguration, + [USB_GET_INTERFACE] = _usb_std_getinterface, + [USB_SET_INTERFACE] = _usb_std_setinterface, + [USB_SYNCH_FRAME] = _usb_std_synchframe, +}; + +/* get standard descriptor handler */ +static uint8_t *(*std_desc_get[])(usb_core_driver *udev, uint8_t index, uint16_t *len) = { + [(uint8_t)USB_DESCTYPE_DEV - 1U] = _usb_dev_desc_get, + [(uint8_t)USB_DESCTYPE_CONFIG - 1U] = _usb_config_desc_get, + [(uint8_t)USB_DESCTYPE_STR - 1U] = _usb_str_desc_get +}; + +/*! + \brief handle USB standard device request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +usb_reqsta usbd_standard_request(usb_core_driver *udev, usb_req *req) +{ + return (*_std_dev_req[req->bRequest])(udev, req); +} + +/*! + \brief handle USB device class request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device class request + \param[out] none + \retval USB device request status +*/ +usb_reqsta usbd_class_request(usb_core_driver *udev, usb_req *req) +{ + if((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) { + if(BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { + /* call device class handle function */ + return (usb_reqsta)udev->dev.class_core->req_proc(udev, req); + } + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB vendor request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB vendor request + \param[out] none + \retval USB device request status +*/ +usb_reqsta usbd_vendor_request(usb_core_driver *udev, usb_req *req) +{ + (void)udev; + (void)req; + + /* added by user... */ +#ifdef WINUSB_EXEMPT_DRIVER + usbd_OEM_req(udev, req); +#endif + + return REQ_SUPP; +} + +/*! + \brief handle USB enumeration error + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval none +*/ +void usbd_enum_error(usb_core_driver *udev, usb_req *req) +{ + (void)req; + + (void)usbd_ep_stall(udev, 0x80U); + (void)usbd_ep_stall(udev, 0x00U); + + usb_ctlep_startout(udev); +} + +/*! + \brief convert hex 32bits value into unicode char + \param[in] value: hex 32bits value + \param[in] pbuf: buffer pointer to store unicode char + \param[in] len: value length + \param[out] none + \retval none +*/ +void int_to_unicode(uint32_t value, uint8_t *pbuf, uint8_t len) +{ + uint8_t index; + + for(index = 0U; index < len; index++) { + if((value >> 28U) < 0x0AU) { + pbuf[2U * index] = (uint8_t)((value >> 28U) + '0'); + } else { + pbuf[2U * index] = (uint8_t)((value >> 28U) + 'A' - 10U); + } + + value = value << 4U; + + pbuf[2U * index + 1U] = 0U; + } +} + +/*! + \brief convert hex 32bits value into unicode char + \param[in] unicode_str: pointer to unicode string + \param[out] none + \retval none +*/ +void serial_string_get(uint16_t *unicode_str) +{ + if((unicode_str[0] & 0x00FFU) != 6U) { + uint32_t DeviceSerial0, DeviceSerial1, DeviceSerial2; + + DeviceSerial0 = *(uint32_t *)DEVICE_ID1; + DeviceSerial1 = *(uint32_t *)DEVICE_ID2; + DeviceSerial2 = *(uint32_t *)DEVICE_ID3; + + DeviceSerial0 += DeviceSerial2; + + if(0U != DeviceSerial0) { + int_to_unicode(DeviceSerial0, (uint8_t *) & (unicode_str[1]), 8U); + int_to_unicode(DeviceSerial1, (uint8_t *) & (unicode_str[9]), 4U); + } + } else { + uint32_t device_serial = *(uint32_t *)DEVICE_ID; + + if(0U != device_serial) { + unicode_str[1] = (uint16_t)(device_serial & 0x0000FFFFU); + unicode_str[2] = (uint16_t)((device_serial & 0xFFFF0000U) >> 16U); + + } + } +} + +/*! + \brief no operation, just for reserved + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB vendor request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_reserved(usb_core_driver *udev, usb_req *req) +{ + (void)udev; + (void)req; + + /* no operation... */ + + return REQ_NOTSUPP; +} + +/*! + \brief get the device descriptor + \param[in] udev: pointer to USB device instance + \param[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t *_usb_dev_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->dev_desc[0]; + + return udev->dev.desc->dev_desc; +} + +/*! + \brief get the configuration descriptor + \brief[in] udev: pointer to USB device instance + \brief[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t *_usb_config_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->config_desc[2] | (udev->dev.desc->config_desc[3] << 8); + + return udev->dev.desc->config_desc; +} + +/*! + \brief get the BOS descriptor + \brief[in] udev: pointer to USB device instance + \brief[in] index: no use + \param[out] len: data length pointer + \retval descriptor buffer pointer +*/ +static uint8_t *_usb_bos_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + (void)index; + + *len = udev->dev.desc->bos_desc[2]; + + return udev->dev.desc->bos_desc; +} + +/*! + \brief get string descriptor + \param[in] udev: pointer to USB device instance + \param[in] index: string descriptor index + \param[out] len: pointer to string length + \retval descriptor buffer pointer +*/ +static uint8_t *_usb_str_desc_get(usb_core_driver *udev, uint8_t index, uint16_t *len) +{ + uint8_t *desc = udev->dev.desc->strings[index]; + + *len = desc[0]; + + return desc; +} + +/*! + \brief handle Get_Status request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getstatus(usb_core_driver *udev, usb_req *req) +{ + uint8_t recp = BYTE_LOW(req->wIndex); + usb_reqsta req_status = REQ_NOTSUPP; + usb_transc *transc = &udev->dev.transc_in[0]; + + static uint8_t status[2] = {0}; + + switch(req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + if(((uint8_t)USBD_ADDRESSED == udev->dev.cur_status) || \ + ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)) { + + if(udev->dev.pm.power_mode) { + status[0] = USB_STATUS_SELF_POWERED; + } else { + status[0] = 0U; + } + + if(udev->dev.pm.dev_remote_wakeup) { + status[0] |= USB_STATUS_REMOTE_WAKEUP; + } else { + status[0] = 0U; + } + + req_status = REQ_SUPP; + } + break; + + case USB_RECPTYPE_ITF: + if(((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) && (recp <= USBD_ITF_MAX_NUM)) { + req_status = REQ_SUPP; + } + break; + + case USB_RECPTYPE_EP: + if((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) { + if(0x80U == (recp & 0x80U)) { + status[0] = udev->dev.transc_in[EP_ID(recp)].ep_stall; + } else { + status[0] = udev->dev.transc_out[recp].ep_stall; + } + + req_status = REQ_SUPP; + } + break; + + default: + break; + } + + if(REQ_SUPP == req_status) { + transc->xfer_buf = status; + transc->remain_len = 2U; + } + + return req_status; +} + +/*! + \brief handle USB Clear_Feature request + \param[in] udev: pointer to USB device instance + \param[in] req: USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_clearfeature(usb_core_driver *udev, usb_req *req) +{ + uint8_t ep = 0U; + + switch(req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + if(((uint8_t)USBD_ADDRESSED == udev->dev.cur_status) || \ + ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)) { + + /* clear device remote wakeup feature */ + if((uint16_t)USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + udev->dev.pm.dev_remote_wakeup = 0U; + + return REQ_SUPP; + } + } + break; + + case USB_RECPTYPE_ITF: + break; + + case USB_RECPTYPE_EP: + /* get endpoint address */ + ep = BYTE_LOW(req->wIndex); + + if((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) { + /* clear endpoint halt feature */ + if(((uint16_t)USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep))) { + (void)usbd_ep_stall_clear(udev, ep); + + (void)udev->dev.class_core->req_proc(udev, req); + } + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Set_Feature request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setfeature(usb_core_driver *udev, usb_req *req) +{ + uint8_t ep = 0U; + + switch(req->bmRequestType & (uint8_t)USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + if(((uint8_t)USBD_ADDRESSED == udev->dev.cur_status) || \ + ((uint8_t)USBD_CONFIGURED == udev->dev.cur_status)) { + /* set device remote wakeup feature */ + if((uint16_t)USB_FEATURE_REMOTE_WAKEUP == req->wValue) { + udev->dev.pm.dev_remote_wakeup = 1U; + } + + return REQ_SUPP; + } + break; + + case USB_RECPTYPE_ITF: + break; + + case USB_RECPTYPE_EP: + /* get endpoint address */ + ep = BYTE_LOW(req->wIndex); + + if((uint8_t)USBD_CONFIGURED == udev->dev.cur_status) { + /* set endpoint halt feature */ + if(((uint16_t)USB_FEATURE_EP_HALT == req->wValue) && (!CTL_EP(ep))) { + (void)usbd_ep_stall(udev, ep); + } + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Set_Address request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setaddress(usb_core_driver *udev, usb_req *req) +{ + if((0U == req->wIndex) && (0U == req->wLength)) { + udev->dev.dev_addr = (uint8_t)(req->wValue) & 0x7FU; + + if(udev->dev.cur_status != (uint8_t)USBD_CONFIGURED) { + usbd_addr_set(udev, udev->dev.dev_addr); + + if(udev->dev.dev_addr) { + udev->dev.cur_status = (uint8_t)USBD_ADDRESSED; + } else { + udev->dev.cur_status = (uint8_t)USBD_DEFAULT; + } + + return REQ_SUPP; + } + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Get_Descriptor request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getdescriptor(usb_core_driver *udev, usb_req *req) +{ + uint8_t desc_type = 0U; + uint8_t desc_index = 0U; + + usb_reqsta status = REQ_NOTSUPP; + + usb_transc *transc = &udev->dev.transc_in[0]; + + /* get device standard descriptor */ + switch(req->bmRequestType & USB_RECPTYPE_MASK) { + case USB_RECPTYPE_DEV: + desc_type = BYTE_HIGH(req->wValue); + desc_index = BYTE_LOW(req->wValue); + + switch(desc_type) { + case USB_DESCTYPE_DEV: + transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *) & (transc->remain_len)); + + if(64U == req->wLength) { + transc->remain_len = 8U; + } + break; + + case USB_DESCTYPE_CONFIG: + transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *) & (transc->remain_len)); + break; + + case USB_DESCTYPE_STR: + if(desc_index < (uint8_t)STR_IDX_MAX) { + transc->xfer_buf = std_desc_get[desc_type - 1U](udev, desc_index, (uint16_t *) & (transc->remain_len)); + } + break; + + case USB_DESCTYPE_ITF: + case USB_DESCTYPE_EP: + case USB_DESCTYPE_DEV_QUALIFIER: + case USB_DESCTYPE_OTHER_SPD_CONFIG: + case USB_DESCTYPE_ITF_POWER: + break; + + case USB_DESCTYPE_BOS: + transc->xfer_buf = _usb_bos_desc_get(udev, desc_index, (uint16_t *) & (transc->remain_len)); + break; + + default: + break; + } + break; + + case USB_RECPTYPE_ITF: + /* get device class special descriptor */ + status = (usb_reqsta)(udev->dev.class_core->req_proc(udev, req)); + break; + + case USB_RECPTYPE_EP: + break; + + default: + break; + } + + if((0U != transc->remain_len) && (0U != req->wLength)) { + if(transc->remain_len < req->wLength) { + if((transc->remain_len >= transc->max_len) && (0U == (transc->remain_len % transc->max_len))) { + udev->dev.control.ctl_zlp = 1U; + } + } else { + transc->remain_len = req->wLength; + } + + status = REQ_SUPP; + } + + return status; +} + +/*! + \brief handle USB Set_Descriptor request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setdescriptor(usb_core_driver *udev, usb_req *req) +{ + (void)udev; + (void)req; + + /* no handle... */ + return REQ_SUPP; +} + +/*! + \brief handle USB Get_Configuration request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getconfiguration(usb_core_driver *udev, usb_req *req) +{ + (void)req; + + usb_reqsta req_status = REQ_NOTSUPP; + usb_transc *transc = &udev->dev.transc_in[0]; + + switch(udev->dev.cur_status) { + case USBD_ADDRESSED: + if(USB_DEFAULT_CONFIG == udev->dev.config) { + req_status = REQ_SUPP; + } + break; + + case USBD_CONFIGURED: + if(udev->dev.config != USB_DEFAULT_CONFIG) { + req_status = REQ_SUPP; + } + break; + + default: + break; + } + + if(REQ_SUPP == req_status) { + transc->xfer_buf = &(udev->dev.config); + transc->remain_len = 1U; + } + + return req_status; +} + +/*! + \brief handle USB Set_Configuration request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setconfiguration(usb_core_driver *udev, usb_req *req) +{ + static uint8_t config; + usb_reqsta status = REQ_NOTSUPP; + + config = (uint8_t)(req->wValue); + + if(config <= USBD_CFG_MAX_NUM) { + switch(udev->dev.cur_status) { + case USBD_ADDRESSED: + if(config) { + (void)udev->dev.class_core->init(udev, config); + + udev->dev.config = config; + udev->dev.cur_status = (uint8_t)USBD_CONFIGURED; + } + + status = REQ_SUPP; + break; + + case USBD_CONFIGURED: + if(USB_DEFAULT_CONFIG == config) { + (void)udev->dev.class_core->deinit(udev, config); + + udev->dev.config = config; + udev->dev.cur_status = (uint8_t)USBD_ADDRESSED; + } else if(config != udev->dev.config) { + /* clear old configuration */ + (void)udev->dev.class_core->deinit(udev, config); + + /* set new configuration */ + udev->dev.config = config; + + (void)udev->dev.class_core->init(udev, config); + } else { + /* no operation */ + } + + status = REQ_SUPP; + break; + + case USBD_DEFAULT: + break; + + default: + break; + } + } + + return status; +} + +/*! + \brief handle USB Get_Interface request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_getinterface(usb_core_driver *udev, usb_req *req) +{ + switch(udev->dev.cur_status) { + case USBD_DEFAULT: + break; + + case USBD_ADDRESSED: + break; + + case USBD_CONFIGURED: + if(BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { + usb_transc *transc = &udev->dev.transc_in[0]; + + transc->xfer_buf = &(udev->dev.class_core->alter_set); + transc->remain_len = 1U; + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB Set_Interface request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_setinterface(usb_core_driver *udev, usb_req *req) +{ + switch(udev->dev.cur_status) { + case USBD_DEFAULT: + break; + + case USBD_ADDRESSED: + break; + + case USBD_CONFIGURED: + if(BYTE_LOW(req->wIndex) <= USBD_ITF_MAX_NUM) { + if(NULL != udev->dev.class_core->set_intf) { + (void)udev->dev.class_core->set_intf(udev, req); + } + + return REQ_SUPP; + } + break; + + default: + break; + } + + return REQ_NOTSUPP; +} + +/*! + \brief handle USB SynchFrame request + \param[in] udev: pointer to USB device instance + \param[in] req: pointer to USB device request + \param[out] none + \retval USB device request status +*/ +static usb_reqsta _usb_std_synchframe(usb_core_driver *udev, usb_req *req) +{ + (void)udev; + (void)req; + + /* no handle */ + return REQ_SUPP; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Source/usbd_transc.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Source/usbd_transc.c new file mode 100644 index 000000000..1a58dfbe2 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/device/core/Source/usbd_transc.c @@ -0,0 +1,265 @@ +/*! + \file usbd_transc.c + \brief USB transaction core functions + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 + \version 2020-12-07, V3.0.1, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_enum.h" +#include "usbd_transc.h" + +/*! + \brief USB send data in the control transaction + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_send(usb_core_driver *udev) +{ + usb_transc *transc = &udev->dev.transc_in[0]; + + (void)usbd_ep_send(udev, 0U, transc->xfer_buf, transc->remain_len); + + if(transc->remain_len > transc->max_len) { + udev->dev.control.ctl_state = (uint8_t)USB_CTL_DATA_IN; + } else { + udev->dev.control.ctl_state = (uint8_t)USB_CTL_LAST_DATA_IN; + } + + return USBD_OK; +} + +/*! + \brief USB receive data in control transaction + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_recev(usb_core_driver *udev) +{ + usb_transc *transc = &udev->dev.transc_out[0]; + + (void)usbd_ep_recev(udev, 0U, transc->xfer_buf, transc->remain_len); + + if(transc->remain_len > transc->max_len) { + udev->dev.control.ctl_state = (uint8_t)USB_CTL_DATA_OUT; + } else { + udev->dev.control.ctl_state = (uint8_t)USB_CTL_LAST_DATA_OUT; + } + + return USBD_OK; +} + +/*! + \brief USB send control transaction status + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_status_send(usb_core_driver *udev) +{ + udev->dev.control.ctl_state = (uint8_t)USB_CTL_STATUS_IN; + + (void)usbd_ep_send(udev, 0U, NULL, 0U); + + usb_ctlep_startout(udev); + + return USBD_OK; +} + +/*! + \brief USB control receive status + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +usbd_status usbd_ctl_status_recev(usb_core_driver *udev) +{ + udev->dev.control.ctl_state = (uint8_t)USB_CTL_STATUS_OUT; + + (void)usbd_ep_recev(udev, 0U, NULL, 0U); + + usb_ctlep_startout(udev); + + return USBD_OK; +} + +/*! + \brief USB setup stage processing + \param[in] udev: pointer to USB device instance + \param[out] none + \retval USB device operation cur_status +*/ +uint8_t usbd_setup_transc(usb_core_driver *udev) +{ + usb_reqsta reqstat = REQ_NOTSUPP; + + usb_req req = udev->dev.control.req; + + switch(req.bmRequestType & USB_REQTYPE_MASK) { + /* standard device request */ + case USB_REQTYPE_STRD: + reqstat = usbd_standard_request(udev, &req); + break; + + /* device class request */ + case USB_REQTYPE_CLASS: + reqstat = usbd_class_request(udev, &req); + break; + + /* vendor defined request */ + case USB_REQTYPE_VENDOR: + reqstat = usbd_vendor_request(udev, &req); + break; + + default: + break; + } + + if(REQ_SUPP == reqstat) { + if(0U == req.wLength) { + (void)usbd_ctl_status_send(udev); + } else { + if(req.bmRequestType & 0x80U) { + (void)usbd_ctl_send(udev); + } else { + (void)usbd_ctl_recev(udev); + } + } + } else { + usbd_enum_error(udev, &req); + } + + return (uint8_t)USBD_OK; +} + +/*! + \brief data out stage processing + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier(0..7) + \param[out] none + \retval USB device operation cur_status +*/ +uint8_t usbd_out_transc(usb_core_driver *udev, uint8_t ep_num) +{ + if(0U == ep_num) { + usb_transc *transc = &udev->dev.transc_out[0]; + + switch(udev->dev.control.ctl_state) { + case USB_CTL_DATA_OUT: + /* update transfer length */ + transc->remain_len -= transc->max_len; + + if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + transc->xfer_buf += transc->max_len; + } + + (void)usbd_ctl_recev(udev); + break; + + case USB_CTL_LAST_DATA_OUT: + if(udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) { + if(udev->dev.class_core->ctlx_out != NULL) { + (void)udev->dev.class_core->ctlx_out(udev); + } + } + + transc->remain_len = 0U; + + (void)usbd_ctl_status_send(udev); + break; + + default: + break; + } + } else if((udev->dev.class_core->data_out != NULL) && (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED)) { + (void)udev->dev.class_core->data_out(udev, ep_num); + } else { + /* no operation */ + } + + return (uint8_t)USBD_OK; +} + +/*! + \brief data in stage processing + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier(0..7) + \param[out] none + \retval USB device operation cur_status +*/ +uint8_t usbd_in_transc(usb_core_driver *udev, uint8_t ep_num) +{ + if(0U == ep_num) { + usb_transc *transc = &udev->dev.transc_in[0]; + + switch(udev->dev.control.ctl_state) { + case USB_CTL_DATA_IN: + /* update transfer length */ + transc->remain_len -= transc->max_len; + + if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + transc->xfer_buf += transc->max_len; + } + + (void)usbd_ctl_send(udev); + break; + + case USB_CTL_LAST_DATA_IN: + /* last packet is MPS multiple, so send ZLP packet */ + if(udev->dev.control.ctl_zlp) { + (void)usbd_ep_send(udev, 0U, NULL, 0U); + + udev->dev.control.ctl_zlp = 0U; + } else { + if(udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) { + if(udev->dev.class_core->ctlx_in != NULL) { + (void)udev->dev.class_core->ctlx_in(udev); + } + } + + transc->remain_len = 0U; + + (void)usbd_ctl_status_recev(udev); + } + break; + + default: + break; + } + } else { + if((udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) && (udev->dev.class_core->data_in != NULL)) { + (void)udev->dev.class_core->data_in(udev, ep_num); + } + } + + return (uint8_t)USBD_OK; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usb_core.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usb_core.h new file mode 100644 index 000000000..ae9466452 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usb_core.h @@ -0,0 +1,159 @@ +/*! + \file drv_usb_core.h + \brief USB core low level driver header file + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_CORE_H +#define __DRV_USB_CORE_H + +#include "drv_usb_regs.h" +#include "usb_ch9_std.h" + +#define USB_FS_EP0_MAX_LEN 64U /*!< maximum packet size of endpoint 0 */ +#define HC_MAX_PACKET_COUNT 140U /*!< maximum packet count */ + +#define EP_ID(x) ((uint8_t)((x) & 0x7FU)) /*!< endpoint number */ +#define EP_DIR(x) ((uint8_t)((x) >> 7)) /*!< endpoint direction */ + +enum _usb_mode { + DEVICE_MODE = 0U, /*!< device mode */ + HOST_MODE, /*!< host mode */ + OTG_MODE /*!< OTG mode */ +}; + +enum _usb_eptype { + USB_EPTYPE_CTRL = 0U, /*!< control endpoint type */ + USB_EPTYPE_ISOC = 1U, /*!< isochronous endpoint type */ + USB_EPTYPE_BULK = 2U, /*!< bulk endpoint type */ + USB_EPTYPE_INTR = 3U, /*!< interrupt endpoint type */ + USB_EPTYPE_MASK = 3U /*!< endpoint type mask */ +}; + +typedef enum { + USB_OTG_OK = 0U, /*!< USB OTG status OK*/ + USB_OTG_FAIL /*!< USB OTG status fail*/ +} usb_otg_status; + +typedef enum { + USB_OK = 0U, /*!< USB status OK*/ + USB_FAIL /*!< USB status fail*/ +} usb_status; + +typedef enum { + USB_USE_FIFO, /*!< USB use FIFO transfer mode */ + USB_USE_DMA /*!< USB use DMA transfer mode */ +} usb_transfer_mode; + +typedef struct { + uint8_t core_enum; /*!< USB core type */ + uint8_t core_speed; /*!< USB core speed */ + uint8_t num_pipe; /*!< USB host channel numbers */ + uint8_t num_ep; /*!< USB device endpoint numbers */ + uint8_t transfer_mode; /*!< USB transfer mode */ + uint8_t phy_itf; /*!< USB core PHY interface */ + uint8_t sof_enable; /*!< USB SOF output */ + uint8_t low_power; /*!< USB low power */ + uint8_t lpm_enable; /*!< USB link power mode(LPM) */ + uint8_t vbus_sensing_enable; /*!< USB VBUS sensing feature */ + uint8_t use_dedicated_ep1; /*!< USB dedicated endpoint1 interrupt */ + uint8_t use_external_vbus; /*!< enable or disable the use of the external VBUS */ + uint32_t base_reg; /*!< base register address */ +} usb_core_basic; + +/* static inline function definitions */ + +/*! + \brief get the global interrupts + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_coreintr_get(usb_core_regs *usb_regs) +{ + return usb_regs->gr->GINTEN & usb_regs->gr->GINTF; +} + +/*! + \brief set USB RX FIFO size + \param[in] usb_regs: pointer to USB core registers + \param[in] size: assigned FIFO size + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_set_rxfifo(usb_core_regs *usb_regs, uint16_t size) +{ + usb_regs->gr->GRFLEN = size; +} + +/*! + \brief enable the global interrupts + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_globalint_enable(usb_core_regs *usb_regs) +{ + /* enable USB global interrupt */ + usb_regs->gr->GAHBCS |= GAHBCS_GINTEN; +} + +/*! + \brief disable the global interrupts + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_globalint_disable(usb_core_regs *usb_regs) +{ + /* disable USB global interrupt */ + usb_regs->gr->GAHBCS &= ~GAHBCS_GINTEN; +} + +/* function declarations */ +/* configure core capabilities */ +usb_status usb_basic_init(usb_core_basic *usb_basic, usb_core_regs *usb_regs, usb_core_enum usb_core); +/* initializes the USB controller registers and prepares the core device mode or host mode operation */ +usb_status usb_core_init(usb_core_basic usb_basic, usb_core_regs *usb_regs); +/* write a packet into the Tx FIFO associated with the endpoint */ +usb_status usb_txfifo_write(usb_core_regs *usb_regs, uint8_t *src_buf, uint8_t fifo_num, uint16_t byte_count); +/* read a packet from the Rx FIFO associated with the endpoint */ +void *usb_rxfifo_read(usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count); +/* flush a Tx FIFO or all Tx FIFOs */ +usb_status usb_txfifo_flush(usb_core_regs *usb_regs, uint8_t fifo_num); +/* flush the entire Rx FIFO */ +usb_status usb_rxfifo_flush(usb_core_regs *usb_regs); +/* set endpoint or channel TX FIFO size */ +void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size); +/* set USB current mode */ +void usb_curmode_set(usb_core_regs *usb_regs, uint8_t mode); + +#endif /* __DRV_USB_CORE_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usb_dev.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usb_dev.h new file mode 100644 index 000000000..25ab01941 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usb_dev.h @@ -0,0 +1,296 @@ +/*! + \file drv_usb_dev.h + \brief USB device low level driver header file + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 + \version 2020-12-07, V3.0.1, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_DEV_H +#define __DRV_USB_DEV_H + +#include "usbd_conf.h" +#include "drv_usb_core.h" + +enum usb_ctl_status { + USB_CTL_IDLE = 0U, /*!< USB control transfer idle state */ + USB_CTL_DATA_IN, /*!< USB control transfer data in state */ + USB_CTL_LAST_DATA_IN, /*!< USB control transfer last data in state */ + USB_CTL_DATA_OUT, /*!< USB control transfer data out state */ + USB_CTL_LAST_DATA_OUT, /*!< USB control transfer last data out state */ + USB_CTL_STATUS_IN, /*!< USB control transfer status in state*/ + USB_CTL_STATUS_OUT /*!< USB control transfer status out state */ +}; + +#define EP_IN(x) ((uint8_t)(0x80U | (x))) /*!< device IN endpoint */ +#define EP_OUT(x) ((uint8_t)(x)) /*!< device OUT endpoint */ + +/* USB descriptor */ +typedef struct _usb_desc { + uint8_t *dev_desc; /*!< device descriptor */ + uint8_t *config_desc; /*!< configure descriptor */ + uint8_t *bos_desc; /*!< BOS descriptor */ + + void *const *strings; /*!< string descriptor */ +} usb_desc; + +/* USB power management */ +typedef struct _usb_pm { + uint8_t power_mode; /*!< power mode */ + uint8_t power_low; /*!< power low */ + uint8_t dev_remote_wakeup; /*!< remote wakeup */ + uint8_t remote_wakeup_on; /*!< remote wakeup on */ +} usb_pm; + +/* USB control information */ +typedef struct _usb_control { + usb_req req; /*!< USB standard device request */ + + uint8_t ctl_state; /*!< USB control transfer state */ + uint8_t ctl_zlp; /*!< zero length package */ +} usb_control; + +typedef struct { + struct { + uint8_t num: 4; /*!< the endpoint number.it can be from 0 to 6 */ + uint8_t pad: 3; /*!< padding between number and direction */ + uint8_t dir: 1; /*!< the endpoint direction */ + } ep_addr; + + uint8_t ep_type; /*!< USB endpoint type */ + uint8_t ep_stall; /*!< USB endpoint stall status */ + + uint8_t frame_num; /*!< number of frame */ + uint16_t max_len; /*!< Maximum packet length */ + + /* transaction level variables */ + uint8_t *xfer_buf; /*!< transmit buffer */ + uint32_t xfer_len; /*!< transmit buffer length */ + uint32_t xfer_count; /*!< transmit buffer count */ + + uint32_t remain_len; /*!< remain packet length */ + + uint32_t dma_addr; /*!< DMA address */ +} usb_transc; + +typedef struct _usb_core_driver usb_dev; + +typedef struct _usb_class_core { + uint8_t command; /*!< device class request command */ + uint8_t alter_set; /*!< alternative set */ + + uint8_t (*init)(usb_dev *udev, uint8_t config_index); /*!< initialize handler */ + uint8_t (*deinit)(usb_dev *udev, uint8_t config_index); /*!< de-initialize handler */ + + uint8_t (*req_proc)(usb_dev *udev, usb_req *req); /*!< device request handler */ + + uint8_t (*set_intf)(usb_dev *udev, usb_req *req); /*!< device set interface callback */ + + uint8_t (*ctlx_in)(usb_dev *udev); /*!< device contrl in callback */ + uint8_t (*ctlx_out)(usb_dev *udev); /*!< device contrl out callback */ + + uint8_t (*data_in)(usb_dev *udev, uint8_t ep_num); /*!< device data in handler */ + uint8_t (*data_out)(usb_dev *udev, uint8_t ep_num); /*!< device data out handler */ + + uint8_t (*SOF)(usb_dev *udev); /*!< Start of frame handler */ + + uint8_t (*incomplete_isoc_in)(usb_dev *udev); /*!< Incomplete synchronization IN transfer handler */ + uint8_t (*incomplete_isoc_out)(usb_dev *udev); /*!< Incomplete synchronization OUT transfer handler */ +} usb_class_core; + +typedef struct _usb_perp_dev { + uint8_t config; /*!< configuration */ + uint8_t dev_addr; /*!< device address */ + + __IO uint8_t cur_status; /*!< current status */ + __IO uint8_t backup_status; /*!< backup status */ + + usb_transc transc_in[USBFS_MAX_TX_FIFOS]; /*!< endpoint IN transaction */ + usb_transc transc_out[USBFS_MAX_TX_FIFOS]; /*!< endpoint OUT transaction */ + + usb_pm pm; /*!< power management */ + usb_control control; /*!< USB control information */ + usb_desc *desc; /*!< USB descriptors pointer */ + usb_class_core *class_core; /*!< class driver */ + void *class_data[USBD_ITF_MAX_NUM]; /*!< class data pointer */ + void *user_data; /*!< user data pointer */ + void *pdata; /*!< reserved data pointer */ +} usb_perp_dev; + +typedef struct _usb_core_driver { + usb_core_basic bp; /*!< USB basic parameters */ + usb_core_regs regs; /*!< USB registers */ + usb_perp_dev dev; /*!< USB peripheral device */ +} usb_core_driver; + +/* static inline function definitions */ + +/*! + \brief configure the USB device to be disconnected + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +__STATIC_INLINE void usb_dev_disconnect(usb_core_driver *udev) +{ + udev->regs.dr->DCTL |= DCTL_SD; +} + +/*! + \brief configure the USB device to be connected + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +__STATIC_INLINE void usb_dev_connect(usb_core_driver *udev) +{ + udev->regs.dr->DCTL &= ~DCTL_SD; +} + +/*! + \brief set the USB device address + \param[in] udev: pointer to USB device + \param[in] dev_addr: device address for setting + \param[out] none + \retval operation status +*/ +__STATIC_INLINE void usb_devaddr_set(usb_core_driver *udev, uint8_t dev_addr) +{ + udev->regs.dr->DCFG &= ~DCFG_DAR; + udev->regs.dr->DCFG |= (uint32_t)dev_addr << 4U; +} + +/*! + \brief read device all OUT endpoint interrupt register + \param[in] udev: pointer to USB device + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_oepintnum_read(usb_core_driver *udev) +{ + uint32_t value = udev->regs.dr->DAEPINT; + + value &= udev->regs.dr->DAEPINTEN; + + return (value & DAEPINT_OEPITB) >> 16U; +} + +/*! + \brief read device OUT endpoint interrupt flag register + \param[in] udev: pointer to USB device + \param[in] ep_num: endpoint number + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_oepintr_read(usb_core_driver *udev, uint8_t ep_num) +{ + uint32_t value = udev->regs.er_out[ep_num]->DOEPINTF; + + value &= udev->regs.dr->DOEPINTEN; + + return value; +} + +/*! + \brief read device all IN endpoint interrupt register + \param[in] udev: pointer to USB device + \param[out] none + \retval interrupt status +*/ +__STATIC_INLINE uint32_t usb_iepintnum_read(usb_core_driver *udev) +{ + uint32_t value = udev->regs.dr->DAEPINT; + + value &= udev->regs.dr->DAEPINTEN; + + return value & DAEPINT_IEPITB; +} + +/*! + \brief set remote wakeup signaling + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_rwkup_set(usb_core_driver *udev) +{ + if(udev->dev.pm.dev_remote_wakeup) { + /* enable remote wakeup signaling */ + udev->regs.dr->DCTL |= DCTL_RWKUP; + } +} + +/*! + \brief reset remote wakeup signaling + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_rwkup_reset(usb_core_driver *udev) +{ + if(udev->dev.pm.dev_remote_wakeup) { + /* disable remote wakeup signaling */ + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + } +} + +/* function declarations */ +/* initialize USB core registers for device mode */ +usb_status usb_devcore_init(usb_core_driver *udev); +/* enable the USB device mode interrupts */ +usb_status usb_devint_enable(usb_core_driver *udev); +/* active the USB endpoint 0 transaction */ +usb_status usb_transc0_active(usb_core_driver *udev, usb_transc *transc); +/* active the USB transaction */ +usb_status usb_transc_active(usb_core_driver *udev, usb_transc *transc); +/* deactivate the USB transaction */ +usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc); +/* configure USB transaction to start IN transfer */ +usb_status usb_transc_inxfer(usb_core_driver *udev, usb_transc *transc); +/* configure USB transaction to start OUT transfer */ +usb_status usb_transc_outxfer(usb_core_driver *udev, usb_transc *transc); +/* set the USB transaction STALL status */ +usb_status usb_transc_stall(usb_core_driver *udev, usb_transc *transc); +/* clear the USB transaction STALL status */ +usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc); +/* read device IN endpoint interrupt flag register */ +uint32_t usb_iepintr_read(usb_core_driver *udev, uint8_t ep_num); +/* configures OUT endpoint 0 to receive SETUP packets */ +void usb_ctlep_startout(usb_core_driver *udev); +/* active remote wakeup signaling */ +void usb_rwkup_active(usb_core_driver *udev); +/* active USB core clock */ +void usb_clock_active(usb_core_driver *udev); +/* USB device suspend */ +void usb_dev_suspend(usb_core_driver *udev); +/* stop the device and clean up FIFOs */ +void usb_dev_stop(usb_core_driver *udev); + +#endif /* __DRV_USB_DEV_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usb_host.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usb_host.h new file mode 100644 index 000000000..0469b1202 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usb_host.h @@ -0,0 +1,187 @@ +/*! + \file drv_usb_host.h + \brief USB host mode low level driver header file + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_HOST_H +#define __DRV_USB_HOST_H + +#include "drv_usb_regs.h" +#include "usb_ch9_std.h" +#include "drv_usb_core.h" + +typedef enum _usb_pipe_status { + PIPE_IDLE = 0U, + PIPE_XF, + PIPE_HALTED, + PIPE_NAK, + PIPE_NYET, + PIPE_STALL, + PIPE_TRACERR, + PIPE_BBERR, + PIPE_REQOVR, + PIPE_DTGERR, +} usb_pipe_staus; + +typedef enum _usb_pipe_mode { + PIPE_PERIOD = 0U, + PIPE_NON_PERIOD = 1U +} usb_pipe_mode; + +typedef enum _usb_urb_state { + URB_IDLE = 0U, + URB_DONE, + URB_NOTREADY, + URB_ERROR, + URB_STALL, + URB_PING +} usb_urb_state; + +typedef struct _usb_pipe { + uint8_t in_used; + uint8_t dev_addr; + uint32_t dev_speed; + + struct { + uint8_t num; + uint8_t dir; + uint8_t type; + uint16_t mps; + } ep; + + uint8_t ping; + uint32_t DPID; + + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t xfer_count; + + uint8_t data_toggle_in; + uint8_t data_toggle_out; + + __IO uint32_t err_count; + __IO usb_pipe_staus pp_status; + __IO usb_urb_state urb_state; +} usb_pipe; + + +typedef struct _usb_host_drv { + __IO uint32_t connect_status; + __IO uint32_t port_enabled; + __IO uint32_t backup_xfercount[USBFS_MAX_TX_FIFOS]; + + usb_pipe pipe[USBFS_MAX_TX_FIFOS]; + void *data; +} usb_host_drv; + +typedef struct _usb_core_driver { + usb_core_basic bp; + usb_core_regs regs; + usb_host_drv host; +} usb_core_driver; + +/*! + \brief get USB even frame + \param[in] pudev: pointer to USB device + \param[out] none + \retval none +*/ +__STATIC_INLINE uint8_t usb_frame_even(usb_core_driver *pudev) +{ + return (uint8_t)!(pudev->regs.hr->HFINFR & 0x01U); +} + +/*! + \brief configure USB clock of PHY + \param[in] pudev: pointer to USB device + \param[in] clock: PHY clock + \param[out] none + \retval none +*/ +__STATIC_INLINE void usb_phyclock_config(usb_core_driver *pudev, uint8_t clock) +{ + pudev->regs.hr->HCTL &= ~HCTL_CLKSEL; + pudev->regs.hr->HCTL |= clock; +} + +/*! + \brief read USB port + \param[in] pudev: pointer to USB device + \param[out] none + \retval port status +*/ +__STATIC_INLINE uint32_t usb_port_read(usb_core_driver *pudev) +{ + return *pudev->regs.HPCS & ~(HPCS_PE | HPCS_PCD | HPCS_PEDC); +} + +/*! + \brief get USB current speed + \param[in] pudev: pointer to USB device + \param[out] none + \retval USB current speed +*/ +__STATIC_INLINE uint32_t usb_curspeed_get(usb_core_driver *pudev) +{ + return *pudev->regs.HPCS & HPCS_PS; +} + +/*! + \brief get USB current frame + \param[in] pudev: pointer to USB device + \param[out] none + \retval USB current frame +*/ +__STATIC_INLINE uint32_t usb_curframe_get(usb_core_driver *pudev) +{ + return (pudev->regs.hr->HFINFR & 0xFFFFU); +} + +/* function declarations */ +/* initializes USB core for host mode */ +usb_status usb_host_init(usb_core_driver *pudev); +/* control the VBUS to power */ +void usb_portvbus_switch(usb_core_driver *pudev, uint8_t state); +/* reset host port */ +uint32_t usb_port_reset(usb_core_driver *pudev); +/* initialize host pipe */ +usb_status usb_pipe_init(usb_core_driver *pudev, uint8_t pipe_num); +/* prepare host pipe for transferring packets */ +usb_status usb_pipe_xfer(usb_core_driver *pudev, uint8_t pipe_num); +/* halt host pipe */ +usb_status usb_pipe_halt(usb_core_driver *pudev, uint8_t pipe_num); +/* configure host pipe to do ping operation */ +usb_status usb_pipe_ping(usb_core_driver *pudev, uint8_t pipe_num); +/* stop the USB host and clean up FIFO */ +void usb_host_stop(usb_core_driver *pudev); + +#endif /* __DRV_USB_HOST_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usb_hw.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usb_hw.h new file mode 100644 index 000000000..9bf1b59c8 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usb_hw.h @@ -0,0 +1,69 @@ +/*! + \file drv_usb_hw.h + \brief usb hardware configuration header file + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_HW_H +#define __DRV_USB_HW_H + +#include "usb_conf.h" + +/* function declarations */ +/* configure USB clock */ +void usb_rcu_config(void); +/* configure USB interrupt */ +void usb_intr_config(void); +/* initializes delay unit using Timer2 */ +void usb_timer_init(void); +/* delay in micro seconds */ +void usb_udelay(const uint32_t usec); +/* delay in milliseconds */ +void usb_mdelay(const uint32_t msec); +/* configures system clock after wakeup from STOP mode */ +void system_clk_config_stop(void); + +/* configure the CTC peripheral */ +#ifdef USE_IRC48M +void ctc_config(void); +#endif /* USE_IRC48M */ + +#ifdef USE_HOST_MODE +void systick_config(void); + +/* configure USB VBus */ +void usb_vbus_config(void); + +/* drive USB VBus */ +void usb_vbus_drive(uint8_t State); +#endif /* USE_HOST_MODE */ + +#endif /* __DRV_USB_HW_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usb_regs.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usb_regs.h new file mode 100644 index 000000000..95c759dce --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usb_regs.h @@ -0,0 +1,649 @@ +/*! + \file drv_usb_regs.h + \brief USB cell registers definition and handle macros + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USB_REGS_H +#define __DRV_USB_REGS_H + +#include "usb_conf.h" + +#define USBHS_REG_BASE 0x40040000L /*!< base address of USBHS registers */ +#define USBFS_REG_BASE 0x50000000L /*!< base address of USBFS registers */ + +#define USBFS_MAX_TX_FIFOS 15U /*!< FIFO number */ + +#define USBFS_MAX_PACKET_SIZE 64U /*!< USBFS max packet size */ +#define USBFS_MAX_CHANNEL_COUNT 8U /*!< USBFS host channel count */ +#define USBFS_MAX_EP_COUNT 4U /*!< USBFS device endpoint count */ +#define USBFS_MAX_FIFO_WORDLEN 320U /*!< USBFS max fifo size in words */ + +#define USBHS_MAX_PACKET_SIZE 512U /*!< USBHS max packet size */ +#define USBHS_MAX_CHANNEL_COUNT 12U /*!< USBHS host channel count */ +#define USBHS_MAX_EP_COUNT 6U /*!< USBHS device endpoint count */ +#define USBHS_MAX_FIFO_WORDLEN 1280U /*!< USBHS max fifo size in words */ + +#define USB_DATA_FIFO_OFFSET 0x1000U /*!< USB data fifo offset */ +#define USB_DATA_FIFO_SIZE 0x1000U /*!< USB data fifo size */ + +typedef enum { + USB_CORE_ENUM_HS = 0, /*!< USB core type is HS */ + USB_CORE_ENUM_FS = 1 /*!< USB core type is FS */ +} usb_core_enum; + +enum USB_SPEED { + USB_SPEED_UNKNOWN = 0, /*!< USB speed unknown */ + USB_SPEED_LOW, /*!< USB speed low */ + USB_SPEED_FULL, /*!< USB speed full */ + USB_SPEED_HIGH, /*!< USB speed high */ +}; + +enum usb_reg_offset { + USB_REG_OFFSET_CORE = 0x0000U, /*!< global OTG control and status register */ + USB_REG_OFFSET_DEV = 0x0800U, /*!< device mode control and status registers */ + USB_REG_OFFSET_EP = 0x0020U, + USB_REG_OFFSET_EP_IN = 0x0900U, /*!< device IN endpoint 0 control register */ + USB_REG_OFFSET_EP_OUT = 0x0B00U, /*!< device OUT endpoint 0 control register */ + USB_REG_OFFSET_HOST = 0x0400U, /*!< host control register */ + USB_REG_OFFSET_CH = 0x0020U, + USB_REG_OFFSET_PORT = 0x0440U, /*!< host port control and status register */ + USB_REG_OFFSET_CH_INOUT = 0x0500U, /*!< Host channel-x control registers */ + USB_REG_OFFSET_PWRCLKCTL = 0x0E00U, /*!< power and clock register */ +}; + +typedef struct { + __IO uint32_t GOTGCS; /*!< USB global OTG control and status register 000h */ + __IO uint32_t GOTGINTF; /*!< USB global OTG interrupt flag register 004h */ + __IO uint32_t GAHBCS; /*!< USB global AHB control and status register 008h */ + __IO uint32_t GUSBCS; /*!< USB global USB control and status register 00Ch */ + __IO uint32_t GRSTCTL; /*!< USB global reset control register 010h */ + __IO uint32_t GINTF; /*!< USB global interrupt flag register 014h */ + __IO uint32_t GINTEN; /*!< USB global interrupt enable register 018h */ + __IO uint32_t GRSTATR; /*!< USB receive status debug read register 01Ch */ + __IO uint32_t GRSTATP; /*!< USB receive status and pop register 020h */ + __IO uint32_t GRFLEN; /*!< USB global receive FIFO length register 024h */ + __IO uint32_t DIEP0TFLEN_HNPTFLEN; /*!< USB device IN endpoint 0/host non-periodic transmit FIFO length register 028h */ + __IO uint32_t HNPTFQSTAT; /*!< USB host non-periodic FIFO/queue status register 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< USB global core configuration register 038h */ + __IO uint32_t CID; /*!< USB core ID register 03Ch */ + uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ + __IO uint32_t HPTFLEN; /*!< USB host periodic transmit FIFO length register 100h */ + __IO uint32_t DIEPTFLEN[15]; /*!< USB device IN endpoint transmit FIFO length register 104h */ +} usb_gr; + +typedef struct { + __IO uint32_t HCTL; /*!< USB host control register 400h */ + __IO uint32_t HFT; /*!< USB host frame interval register 404h */ + __IO uint32_t HFINFR; /*!< USB host frame information remaining register 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTFQSTAT; /*!< USB host periodic transmit FIFO/queue status register 410h */ + __IO uint32_t HACHINT; /*!< USB host all channels interrupt register 414h */ + __IO uint32_t HACHINTEN; /*!< USB host all channels interrupt enable register 418h */ +} usb_hr; + +typedef struct { + __IO uint32_t HCHCTL; /*!< USB host channel control register 500h */ + __IO uint32_t HCHSTCTL; /*!< Reserved 504h */ + __IO uint32_t HCHINTF; /*!< USB host channel interrupt flag register 508h */ + __IO uint32_t HCHINTEN; /*!< USB host channel interrupt enable register 50Ch */ + __IO uint32_t HCHLEN; /*!< USB host channel transfer length register 510h */ + __IO uint32_t HCHDMAADDR; /*!< USB host channel-x DMA address register 514h*/ + uint32_t Reserved[2]; +} usb_pr; + +typedef struct { + __IO uint32_t DCFG; /*!< USB device configuration register 800h */ + __IO uint32_t DCTL; /*!< USB device control register 804h */ + __IO uint32_t DSTAT; /*!< USB device status register 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPINTEN; /*!< USB device IN endpoint common interrupt enable register 810h */ + __IO uint32_t DOEPINTEN; /*!< USB device OUT endpoint common interrupt enable register 814h */ + __IO uint32_t DAEPINT; /*!< USB device all endpoints interrupt register 818h */ + __IO uint32_t DAEPINTEN; /*!< USB device all endpoints interrupt enable register 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved24; /*!< Reserved 824h */ + __IO uint32_t DVBUSDT; /*!< USB device VBUS discharge time register 828h */ + __IO uint32_t DVBUSPT; /*!< USB device VBUS pulsing time register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold control 830h */ + __IO uint32_t DIEPFEINTEN; /*!< USB Device IN endpoint FIFO empty interrupt enable register 834h */ + __IO uint32_t DEP1INT; /*!< USB device endpoint 1 interrupt register 838h */ + __IO uint32_t DEP1INTEN; /*!< USB device endpoint 1 interrupt enable register 83Ch */ + uint32_t Reserved40; /*!< Reserved 840h */ + __IO uint32_t DIEP1INTEN; /*!< USB device IN endpoint-1 interrupt enable register 844h */ + uint32_t Reserved48[15]; /*!< Reserved 848-880h */ + __IO uint32_t DOEP1INTEN; /*!< USB device OUT endpoint-1 interrupt enable register 884h */ +} usb_dr; + +typedef struct { + __IO uint32_t DIEPCTL; /*!< USB device IN endpoint control register 900h + (EpNum * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (EpNum * 20h) + 04h */ + __IO uint32_t DIEPINTF; /*!< USB device IN endpoint interrupt flag register 900h + (EpNum * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (EpNum * 20h) + 0Ch */ + __IO uint32_t DIEPLEN; /*!< USB device IN endpoint transfer length register 900h + (EpNum * 20h) + 10h */ + __IO uint32_t DIEPDMAADDR; /*!< Device IN endpoint-x DMA address register 900h + (EpNum * 20h) + 14h */ + __IO uint32_t DIEPTFSTAT; /*!< USB device IN endpoint transmit FIFO status register 900h + (EpNum * 20h) + 18h */ +} usb_erin; + +typedef struct { + __IO uint32_t DOEPCTL; /*!< USB device IN endpoint control register B00h + (EpNum * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (EpNum * 20h) + 04h */ + __IO uint32_t DOEPINTF; /*!< USB device IN endpoint interrupt flag register B00h + (EpNum * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (EpNum * 20h) + 0Ch */ + __IO uint32_t DOEPLEN; /*!< USB device IN endpoint transfer length register B00h + (EpNum * 20h) + 10h */ + __IO uint32_t DOEPDMAADDR; /*!< Device OUT endpoint-x DMA address register B00h + (EpNum * 20h) + 0Ch */ +} usb_erout; + +typedef struct _usb_regs { + usb_gr *gr; /*!< USBFS global registers */ + usb_dr *dr; /*!< Device control and status registers */ + usb_hr *hr; /*!< Host control and status registers */ + usb_erin *er_in[6]; /*!< USB device IN endpoint register */ + usb_erout *er_out[6]; /*!< USB device OUT endpoint register */ + usb_pr *pr[15]; /*!< USB Host channel-x control register */ + + __IO uint32_t *HPCS; /*!< USB host port control and status register */ + __IO uint32_t *DFIFO[USBFS_MAX_TX_FIFOS]; + __IO uint32_t *PWRCLKCTL; /*!< USB power and clock control register */ +} usb_core_regs; + +/* global OTG control and status register bits definitions */ +#define GOTGCS_BSV BIT(19) /*!< B-Session Valid */ +#define GOTGCS_ASV BIT(18) /*!< A-session valid */ +#define GOTGCS_DI BIT(17) /*!< debounce interval */ +#define GOTGCS_CIDPS BIT(16) /*!< id pin status */ +#define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */ +#define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */ +#define GOTGCS_HNPREQ BIT(9) /*!< HNP request */ +#define GOTGCS_HNPS BIT(8) /*!< HNP successes */ +#define GOTGCS_SRPREQ BIT(1) /*!< SRP request */ +#define GOTGCS_SRPS BIT(0) /*!< SRP successes */ + +/* global OTG interrupt flag register bits definitions */ +#define GOTGINTF_DF BIT(19) /*!< debounce finish */ +#define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */ +#define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */ +#define GOTGINTF_HNPEND BIT(9) /*!< HNP end */ +#define GOTGINTF_SRPEND BIT(8) /*!< SRP end */ +#define GOTGINTF_SESEND BIT(2) /*!< session end */ + +/* global AHB control and status register bits definitions */ +#define GAHBCS_PTXFTH BIT(8) /*!< periodic Tx FIFO threshold */ +#define GAHBCS_TXFTH BIT(7) /*!< tx FIFO threshold */ +#define GAHBCS_DMAEN BIT(5) /*!< DMA function Enable */ +#define GAHBCS_BURST BITS(1, 4) /*!< the AHB burst type used by DMA */ +#define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ + +/* global USB control and status register bits definitions */ +#define GUSBCS_FDM BIT(30) /*!< force device mode */ +#define GUSBCS_FHM BIT(29) /*!< force host mode */ +#define GUSBCS_ULPIEOI BIT(21) /*!< ULPI external over-current indicator */ +#define GUSBCS_ULPIEVD BIT(20) /*!< ULPI external VBUS driver */ +#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ +#define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ +#define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ +#define GUSBCS_EMBPHY BIT(6) /*!< embedded PHY selected */ +#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ + +/* global reset control register bits definitions */ +#define GRSTCTL_DMAIDL BIT(31) /*!< DMA idle state */ +#define GRSTCTL_DMABSY BIT(30) /*!< DMA busy */ +#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */ +#define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */ +#define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */ +#define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ +#define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */ +#define GRSTCTL_CSRST BIT(0) /*!< core soft reset */ + +/* global interrupt flag register bits definitions */ +#define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */ +#define GINTF_SESIF BIT(30) /*!< session interrupt flag */ +#define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */ +#define GINTF_IDPSC BIT(28) /*!< id pin status change */ +#define GINTF_PTXFEIF BIT(26) /*!< periodic tx FIFO empty interrupt flag */ +#define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */ +#define GINTF_HPIF BIT(24) /*!< host port interrupt flag */ +#define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */ +#define GINTF_ISOONCIF BIT(21) /*!< isochronous OUT transfer not complete interrupt flag */ +#define GINTF_ISOINCIF BIT(20) /*!< isochronous IN transfer not complete interrupt flag */ +#define GINTF_OEPIF BIT(19) /*!< OUT endpoint interrupt flag */ +#define GINTF_IEPIF BIT(18) /*!< IN endpoint interrupt flag */ +#define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */ +#define GINTF_ISOOPDIF BIT(14) /*!< isochronous OUT packet dropped interrupt flag */ +#define GINTF_ENUMFIF BIT(13) /*!< enumeration finished */ +#define GINTF_RST BIT(12) /*!< USB reset */ +#define GINTF_SP BIT(11) /*!< USB suspend */ +#define GINTF_ESP BIT(10) /*!< early suspend */ +#define GINTF_GONAK BIT(7) /*!< global OUT NAK effective */ +#define GINTF_GNPINAK BIT(6) /*!< global IN non-periodic NAK effective */ +#define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx FIFO empty interrupt flag */ +#define GINTF_RXFNEIF BIT(4) /*!< rx FIFO non-empty interrupt flag */ +#define GINTF_SOF BIT(3) /*!< start of frame */ +#define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */ +#define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */ +#define GINTF_COPM BIT(0) /*!< current operation mode */ + +/* global interrupt enable register bits definitions */ +#define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */ +#define GINTEN_SESIE BIT(30) /*!< session interrupt enable */ +#define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */ +#define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */ +#define GINTEN_PTXFEIE BIT(26) /*!< periodic tx FIFO empty interrupt enable */ +#define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */ +#define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */ +#define GINTEN_IPXIE BIT(21) /*!< periodic transfer not complete interrupt enable */ +#define GINTEN_ISOONCIE BIT(21) /*!< isochronous OUT transfer not complete interrupt enable */ +#define GINTEN_ISOINCIE BIT(20) /*!< isochronous IN transfer not complete interrupt enable */ +#define GINTEN_OEPIE BIT(19) /*!< OUT endpoints interrupt enable */ +#define GINTEN_IEPIE BIT(18) /*!< IN endpoints interrupt enable */ +#define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */ +#define GINTEN_ISOOPDIE BIT(14) /*!< isochronous OUT packet dropped interrupt enable */ +#define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */ +#define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */ +#define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */ +#define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */ +#define GINTEN_GONAKIE BIT(7) /*!< global OUT NAK effective interrupt enable */ +#define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic IN NAK effective interrupt enable */ +#define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic Tx FIFO empty interrupt enable */ +#define GINTEN_RXFNEIE BIT(4) /*!< receive FIFO non-empty interrupt enable */ +#define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */ +#define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */ +#define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ + +/* global receive status read and pop register bits definitions */ +#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ +#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ +#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ +#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ +#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ + +/* global receive FIFO length register bits definitions */ +#define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */ + +/* host non-periodic transmit FIFO length register bits definitions */ +#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */ +#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */ + +/* USB IN endpoint 0 transmit FIFO length register bits definitions */ +#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ +#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ + +/* host non-periodic transmit FIFO/queue status register bits definitions */ +#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ +#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */ +#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */ +#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/ +#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ +#define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + +/* global core configuration register bits definitions */ +#define GCCFG_VBUSIG BIT(21) /*!< vbus ignored */ +#define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */ +#define GCCFG_VBUSBCEN BIT(19) /*!< the VBUS B-device comparer enable */ +#define GCCFG_VBUSACEN BIT(18) /*!< the VBUS A-device comparer enable */ +#define GCCFG_PWRON BIT(16) /*!< power on */ + +/* core ID register bits definitions */ +#define CID_CID BITS(0, 31) /*!< core ID */ + +/* host periodic transmit FIFO length register bits definitions */ +#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */ +#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */ + +/* device IN endpoint transmit FIFO length register bits definitions */ +#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ +#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ + +/* host control register bits definitions */ +#define HCTL_SPDFSLS BIT(2) /*!< speed limited to FS and LS */ +#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ + +/* host frame interval register bits definitions */ +#define HFT_FRI BITS(0, 15) /*!< frame interval */ + +/* host frame information remaining register bits definitions */ +#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ +#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ + +/* host periodic transmit FIFO/queue status register bits definitions */ +#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */ +#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */ +#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */ +#define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */ +#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ +#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ +#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ +#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ + +#define TFQSTAT_TXFS BITS(0, 15) +#define TFQSTAT_CNUM BITS(27, 30) + +/* host all channels interrupt register bits definitions */ +#define HACHINT_HACHINT BITS(0, 11) /*!< host all channel interrupts */ + +/* host all channels interrupt enable register bits definitions */ +#define HACHINTEN_CINTEN BITS(0, 11) /*!< channel interrupt enable */ + +/* host port control and status register bits definitions */ +#define HPCS_PS BITS(17, 18) /*!< port speed */ +#define HPCS_PP BIT(12) /*!< port power */ +#define HPCS_PLST BITS(10, 11) /*!< port line status */ +#define HPCS_PRST BIT(8) /*!< port reset */ +#define HPCS_PSP BIT(7) /*!< port suspend */ +#define HPCS_PREM BIT(6) /*!< port resume */ +#define HPCS_PEDC BIT(3) /*!< port enable/disable change */ +#define HPCS_PE BIT(2) /*!< port enable */ +#define HPCS_PCD BIT(1) /*!< port connect detected */ +#define HPCS_PCST BIT(0) /*!< port connect status */ + +/* host channel-x control register bits definitions */ +#define HCHCTL_CEN BIT(31) /*!< channel enable */ +#define HCHCTL_CDIS BIT(30) /*!< channel disable */ +#define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ +#define HCHCTL_DAR BITS(22, 28) /*!< device address */ +#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ +#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define HCHCTL_LSD BIT(17) /*!< low-speed device */ +#define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ +#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ +#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ + +/* host channel-x split transaction register bits definitions */ +#define HCHSTCTL_SPLEN BIT(31) /*!< enable high-speed split transaction */ +#define HCHSTCTL_CSPLT BIT(16) /*!< complete-split enable */ +#define HCHSTCTL_ISOPCE BITS(14, 15) /*!< isochronous OUT payload continuation encoding */ +#define HCHSTCTL_HADDR BITS(7, 13) /*!< HUB address */ +#define HCHSTCTL_PADDR BITS(0, 6) /*!< port address */ + +/* host channel-x interrupt flag register bits definitions */ +#define HCHINTF_DTER BIT(10) /*!< data toggle error */ +#define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */ +#define HCHINTF_BBER BIT(8) /*!< babble error */ +#define HCHINTF_USBER BIT(7) /*!< USB bus Error */ +#define HCHINTF_NYET BIT(6) /*!< NYET */ +#define HCHINTF_ACK BIT(5) /*!< ACK */ +#define HCHINTF_NAK BIT(4) /*!< NAK */ +#define HCHINTF_STALL BIT(3) /*!< STALL */ +#define HCHINTF_DMAER BIT(2) /*!< DMA error */ +#define HCHINTF_CH BIT(1) /*!< channel halted */ +#define HCHINTF_TF BIT(0) /*!< transfer finished */ + +/* host channel-x interrupt enable register bits definitions */ +#define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */ +#define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */ +#define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */ +#define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */ +#define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */ +#define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */ +#define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */ +#define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */ +#define HCHINTEN_DMAERIE BIT(2) /*!< DMA error interrupt enable */ +#define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */ +#define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ + +/* host channel-x transfer length register bits definitions */ +#define HCHLEN_PING BIT(31) /*!< PING token request */ +#define HCHLEN_DPID BITS(29, 30) /*!< data PID */ +#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ +#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ + +/* host channel-x DMA address register bits definitions */ +#define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ + +#define PORT_SPEED(x) (((uint32_t)(x) << 17) & HPCS_PS) /*!< Port speed */ + +#define PORT_SPEED_HIGH PORT_SPEED(0U) /*!< high speed */ +#define PORT_SPEED_FULL PORT_SPEED(1U) /*!< full speed */ +#define PORT_SPEED_LOW PORT_SPEED(2U) /*!< low speed */ + +#define PIPE_CTL_DAR(x) (((uint32_t)(x) << 22) & HCHCTL_DAR) /*!< device address */ +#define PIPE_CTL_EPTYPE(x) (((uint32_t)(x) << 18) & HCHCTL_EPTYPE) /*!< endpoint type */ +#define PIPE_CTL_EPNUM(x) (((uint32_t)(x) << 11) & HCHCTL_EPNUM) /*!< endpoint number */ +#define PIPE_CTL_EPDIR(x) (((uint32_t)(x) << 15) & HCHCTL_EPDIR) /*!< endpoint direction */ +#define PIPE_CTL_EPMPL(x) (((uint32_t)(x) << 0) & HCHCTL_MPL) /*!< maximum packet length */ +#define PIPE_CTL_LSD(x) (((uint32_t)(x) << 17) & HCHCTL_LSD) /*!< low-Speed device */ + +#define PIPE_XFER_PCNT(x) (((uint32_t)(x) << 19) & HCHLEN_PCNT) /*!< packet count */ +#define PIPE_XFER_DPID(x) (((uint32_t)(x) << 29) & HCHLEN_DPID) /*!< data PID */ + +#define PIPE_DPID_DATA0 PIPE_XFER_DPID(0) /*!< DATA0 */ +#define PIPE_DPID_DATA1 PIPE_XFER_DPID(2) /*!< DATA1 */ +#define PIPE_DPID_DATA2 PIPE_XFER_DPID(1) /*!< DATA2 */ +#define PIPE_DPID_SETUP PIPE_XFER_DPID(3) /*!< MDATA (non-control)/SETUP (control) */ + +extern const uint32_t PIPE_DPID[2]; + +/* device configuration registers bits definitions */ +#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ +#define DCFG_DAR BITS(4, 10) /*!< device address */ +#define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */ +#define DCFG_DS BITS(0, 1) /*!< device speed */ + +/* device control registers bits definitions */ +#define DCTL_POIF BIT(11) /*!< power-on initialization finished */ +#define DCTL_CGONAK BIT(10) /*!< clear global OUT NAK */ +#define DCTL_SGONAK BIT(9) /*!< set global OUT NAK */ +#define DCTL_CGINAK BIT(8) /*!< clear global IN NAK */ +#define DCTL_SGINAK BIT(7) /*!< set global IN NAK */ +#define DCTL_GONS BIT(3) /*!< global OUT NAK status */ +#define DCTL_GINS BIT(2) /*!< global IN NAK status */ +#define DCTL_SD BIT(1) /*!< soft disconnect */ +#define DCTL_RWKUP BIT(0) /*!< remote wakeup */ + +/* device status registers bits definitions */ +#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ +#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ +#define DSTAT_SPST BIT(0) /*!< suspend status */ + +/* device IN endpoint common interrupt enable registers bits definitions */ +#define DIEPINTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBHS interrupt enable bit */ +#define DIEPINTEN_TXFEEN BIT(7) /*!< transmit FIFO empty interrupt enable bit */ +#define DIEPINTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */ +#define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */ +#define DIEPINTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */ +#define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ +#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + +/* device OUT endpoint common interrupt enable registers bits definitions */ +#define DOEPINTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */ +#define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */ +#define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint Rx FIFO overrun interrupt enable bit */ +#define DOEPINTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */ +#define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ +#define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ + +/* device all endpoints interrupt registers bits definitions */ +#define DAEPINT_OEPITB BITS(16, 21) /*!< device all OUT endpoint interrupt bits */ +#define DAEPINT_IEPITB BITS(0, 5) /*!< device all IN endpoint interrupt bits */ + +/* device all endpoints interrupt enable registers bits definitions */ +#define DAEPINTEN_OEPIE BITS(16, 21) /*!< OUT endpoint interrupt enable */ +#define DAEPINTEN_IEPIE BITS(0, 3) /*!< IN endpoint interrupt enable */ + +/* device Vbus discharge time registers bits definitions */ +#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ + +/* device Vbus pulsing time registers bits definitions */ +#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ + +/* device IN endpoint FIFO empty interrupt enable register bits definitions */ +#define DIEPFEINTEN_IEPTXFEIE BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ + +/* device endpoint 0 control register bits definitions */ +#define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ +#define DEP0CTL_SNAK BIT(27) /*!< set NAK */ +#define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ +#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ +#define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ +#define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */ +#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEP0CTL_NAKS BIT(17) /*!< NAK status */ +#define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ +#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ + +/* device endpoint x control register bits definitions */ +#define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ +#define DEPCTL_EPD BIT(30) /*!< endpoint disable */ +#define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */ +#define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ +#define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */ +#define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ +#define DEPCTL_SNAK BIT(27) /*!< set NAK */ +#define DEPCTL_CNAK BIT(26) /*!< clear NAK */ +#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ +#define DEPCTL_STALL BIT(21) /*!< STALL handshake */ +#define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */ +#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ +#define DEPCTL_NAKS BIT(17) /*!< NAK status */ +#define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ +#define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ +#define DEPCTL_EPACT BIT(15) /*!< endpoint active */ +#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ + +/* device IN endpoint-x interrupt flag register bits definitions */ +#define DIEPINTF_NAK BIT(13) /*!< NAK handshake sent by USBHS */ +#define DIEPINTF_TXFE BIT(7) /*!< transmit FIFO empty */ +#define DIEPINTF_IEPNE BIT(6) /*!< IN endpoint NAK effective */ +#define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint Tx FIFO underrun */ +#define DIEPINTF_CITO BIT(3) /*!< control In Timeout interrupt */ +#define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ +#define DIEPINTF_TF BIT(0) /*!< transfer finished */ + +/* device OUT endpoint-x interrupt flag register bits definitions */ +#define DOEPINTF_NYET BIT(14) /*!< NYET handshake is sent */ +#define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back SETUP packets */ +#define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint Rx FIFO overrun */ +#define DOEPINTF_STPF BIT(3) /*!< SETUP phase finished */ +#define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ +#define DOEPINTF_TF BIT(0) /*!< transfer finished */ + +/* device IN endpoint 0 transfer length register bits definitions */ +#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ +#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ + +/* device OUT endpoint 0 transfer length register bits definitions */ +#define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ +#define DOEP0LEN_PCNT BIT(19) /*!< packet count */ +#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ + +/* device OUT endpoint-x transfer length register bits definitions */ +#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ +#define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ +#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ +#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ +#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ + +/* device IN endpoint-x DMA address register bits definitions */ +#define DIEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ + +/* device OUT endpoint-x DMA address register bits definitions */ +#define DOEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ + +/* device IN endpoint-x transmit FIFO status register bits definitions */ +#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint Tx FIFO space remaining */ + +/* USB power and clock registers bits definition */ +#define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ +#define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */ + +#define RSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */ +#define RSTAT_DATA_UPDT 2U /* OUT data packet received */ +#define RSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */ +#define RSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */ +#define RSTAT_SETUP_UPDT 6U /* SETUP data packet received */ + +#define DSTAT_EM_HS_PHY_30MHZ_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */ +#define DSTAT_EM_FS_PHY_30MHZ_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */ +#define DSTAT_EM_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */ +#define DSTAT_EM_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */ + +#define DPID_DATA0 0U /* device endpoint data PID is DATA0 */ +#define DPID_DATA1 2U /* device endpoint data PID is DATA1 */ +#define DPID_DATA2 1U /* device endpoint data PID is DATA2 */ +#define DPID_MDATA 3U /* device endpoint data PID is MDATA */ + +#define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1)) /*!< AHB burst type used by DMA*/ + +#define DMA_INCR0 GAHBCS_DMAINCR(0U) /*!< single burst type used by DMA*/ +#define DMA_INCR1 GAHBCS_DMAINCR(1U) /*!< 4-beat incrementing burst type used by DMA*/ +#define DMA_INCR4 GAHBCS_DMAINCR(3U) /*!< 8-beat incrementing burst type used by DMA*/ +#define DMA_INCR8 GAHBCS_DMAINCR(5U) /*!< 16-beat incrementing burst type used by DMA*/ +#define DMA_INCR16 GAHBCS_DMAINCR(7U) /*!< 32-beat incrementing burst type used by DMA*/ + +#define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11)) /*!< end of periodic frame time configuration */ + +#define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */ +#define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */ +#define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ +#define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ + +#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0)) /*!< device speed configuration */ + +#define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */ +#define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */ +#define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */ + +#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0)) /*!< maximum packet length configuration */ + +#define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */ +#define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */ +#define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */ +#define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */ + +#define DOEP0_TLEN(regval) (DOEP0LEN_TLEN & ((regval) << 0)) /*!< Transfer length */ +#define DOEP0_PCNT(regval) (DOEP0LEN_PCNT & ((regval) << 19)) /*!< Packet count */ +#define DOEP0_STPCNT(regval) (DOEP0LEN_STPCNT & ((regval) << 29)) /*!< SETUP packet count */ + +#define USB_ULPI_PHY 1U /*!< ULPI interface external PHY */ +#define USB_EMBEDDED_PHY 2U /*!< Embedded PHY */ + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define HCTL_30_60MHZ 0U /*!< USB clock 30-60MHZ */ +#define HCTL_48MHZ 1U /*!< USB clock 48MHZ */ +#define HCTL_6MHZ 2U /*!< USB clock 6MHZ */ + +#define EP0_OUT ((uint8_t)0x00) /*!< endpoint out 0 */ +#define EP0_IN ((uint8_t)0x80) /*!< endpoint in 0 */ +#define EP1_OUT ((uint8_t)0x01) /*!< endpoint out 1 */ +#define EP1_IN ((uint8_t)0x81) /*!< endpoint in 1 */ +#define EP2_OUT ((uint8_t)0x02) /*!< endpoint out 2 */ +#define EP2_IN ((uint8_t)0x82) /*!< endpoint in 2 */ +#define EP3_OUT ((uint8_t)0x03) /*!< endpoint out 3 */ +#define EP3_IN ((uint8_t)0x83) /*!< endpoint in 3 */ + +#endif /* __DRV_USB_REGS_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usbd_int.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usbd_int.h new file mode 100644 index 000000000..48919a7ef --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usbd_int.h @@ -0,0 +1,45 @@ +/*! + \file drv_usbd_int.h + \brief USB device mode interrupt header file + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USBD_INT_H +#define __DRV_USBD_INT_H + +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +/* function declarations */ +/* USB device-mode interrupts global service routine handler */ +void usbd_isr(usb_core_driver *udev); + +#endif /* __DRV_USBD_INT_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usbh_int.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usbh_int.h new file mode 100644 index 000000000..e8ce7b52f --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Include/drv_usbh_int.h @@ -0,0 +1,55 @@ +/*! + \file drv_usbh_int.h.h + \brief USB host mode interrupt management header file + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __DRV_USBH_INT_H +#define __DRV_USBH_INT_H + +#include "drv_usb_host.h" +#include "usbh_core.h" + +typedef struct _usbh_int_cb { + uint8_t (*connect)(usbh_host *puhost); + uint8_t (*disconnect)(usbh_host *puhost); + uint8_t (*port_enabled)(usbh_host *puhost); + uint8_t (*port_disabled)(usbh_host *puhost); + uint8_t (*SOF)(usbh_host *puhost); +} usbh_int_cb; + +extern usbh_int_cb *usbh_int_fop; + +/* function declarations */ +/* handle global host interrupt */ +uint32_t usbh_isr(usb_core_driver *pudev); + +#endif /* __DRV_USBH_INT_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Source/drv_usb_core.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Source/drv_usb_core.c new file mode 100644 index 000000000..7c8accd2a --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Source/drv_usb_core.c @@ -0,0 +1,343 @@ +/*! + \file drv_usb_core.c + \brief USB core driver which can operate in host and device mode + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_core.h" +#include "drv_usb_hw.h" + +/* local function prototypes ('static') */ +static void usb_core_reset(usb_core_regs *usb_regs); + +/*! + \brief configure USB core basic + \param[in] usb_basic: pointer to usb capabilities + \param[in] usb_regs: USB core registers + \param[in] usb_core: USB core + \param[out] none + \retval operation status +*/ +usb_status usb_basic_init(usb_core_basic *usb_basic, + usb_core_regs *usb_regs, + usb_core_enum usb_core) +{ + /* configure USB default transfer mode as FIFO mode */ + usb_basic->transfer_mode = (uint8_t)USB_USE_FIFO; + + /* USB default speed is full-speed */ + usb_basic->core_speed = (uint8_t)USB_SPEED_FULL; + + usb_basic->core_enum = (uint8_t)usb_core; + + switch(usb_core) { + case USB_CORE_ENUM_FS: + usb_basic->base_reg = (uint32_t)USBFS_REG_BASE; + + /* set the host channel numbers */ + usb_basic->num_pipe = USBFS_MAX_CHANNEL_COUNT; + + /* set the device endpoint numbers */ + usb_basic->num_ep = USBFS_MAX_EP_COUNT; + + /* USBFS core use embedded physical layer */ + usb_basic->phy_itf = USB_EMBEDDED_PHY; + break; + + default: + return USB_FAIL; + } + + usb_basic->sof_enable = USB_SOF_OUTPUT; + usb_basic->low_power = USB_LOW_POWER; + + /* assign main registers address */ + *usb_regs = (usb_core_regs) { + .gr = (usb_gr *)(usb_basic->base_reg + USB_REG_OFFSET_CORE), + .hr = (usb_hr *)(usb_basic->base_reg + USB_REG_OFFSET_HOST), + .dr = (usb_dr *)(usb_basic->base_reg + USB_REG_OFFSET_DEV), + + .HPCS = (uint32_t *)(usb_basic->base_reg + USB_REG_OFFSET_PORT), + .PWRCLKCTL = (uint32_t *)(usb_basic->base_reg + USB_REG_OFFSET_PWRCLKCTL) + }; + + /* assign device endpoint registers address */ + for(uint8_t i = 0U; i < usb_basic->num_ep; i++) { + usb_regs->er_in[i] = (usb_erin *) \ + (usb_basic->base_reg + USB_REG_OFFSET_EP_IN + (i * USB_REG_OFFSET_EP)); + + usb_regs->er_out[i] = (usb_erout *)\ + (usb_basic->base_reg + USB_REG_OFFSET_EP_OUT + (i * USB_REG_OFFSET_EP)); + } + + /* assign host pipe registers address */ + for(uint8_t i = 0U; i < usb_basic->num_pipe; i++) { + usb_regs->pr[i] = (usb_pr *) \ + (usb_basic->base_reg + USB_REG_OFFSET_CH_INOUT + (i * USB_REG_OFFSET_CH)); + + usb_regs->DFIFO[i] = (uint32_t *) \ + (usb_basic->base_reg + USB_DATA_FIFO_OFFSET + (i * USB_DATA_FIFO_SIZE)); + } + + return USB_OK; +} + +/*! + \brief initializes the USB controller registers and + prepares the core device mode or host mode operation + \param[in] usb_basic: pointer to USB capabilities + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval operation status +*/ +usb_status usb_core_init(usb_core_basic usb_basic, usb_core_regs *usb_regs) +{ + if(USB_ULPI_PHY == usb_basic.phy_itf) { + usb_regs->gr->GCCFG &= ~GCCFG_PWRON; + + if(usb_basic.sof_enable) { + usb_regs->gr->GCCFG |= GCCFG_SOFOEN; + } + + /* init the ULPI interface */ + usb_regs->gr->GUSBCS &= ~(GUSBCS_EMBPHY | GUSBCS_ULPIEOI); + +#ifdef USBHS_EXTERNAL_VBUS_ENABLED + /* use external VBUS driver */ + usb_regs->gr->GUSBCS |= GUSBCS_ULPIEVD; +#else + /* use internal VBUS driver */ + usb_regs->gr->GUSBCS &= ~GUSBCS_ULPIEVD; +#endif /* USBHS_EXTERNAL_VBUS_ENABLED */ + + /* soft reset the core */ + usb_core_reset(usb_regs); + } else { + usb_regs->gr->GUSBCS |= GUSBCS_EMBPHY; + + /* soft reset the core */ + usb_core_reset(usb_regs); + + /* active the transceiver and enable VBUS sensing */ + usb_regs->gr->GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; + +#ifndef VBUS_SENSING_ENABLED + usb_regs->gr->GCCFG |= GCCFG_VBUSIG; +#endif /* VBUS_SENSING_ENABLED */ + + /* enable SOF output */ + if(usb_basic.sof_enable) { + usb_regs->gr->GCCFG |= GCCFG_SOFOEN; + } + + usb_mdelay(20U); + } + + if((uint8_t)USB_USE_DMA == usb_basic.transfer_mode) { + usb_regs->gr->GAHBCS &= ~GAHBCS_BURST; + usb_regs->gr->GAHBCS |= DMA_INCR8 | GAHBCS_DMAEN; + } + +#ifdef USE_OTG_MODE + + /* enable USB OTG features */ + usb_regs->gr->GUSBCS |= GUSBCS_HNPCEN | GUSBCS_SRPCEN; + + /* enable the USB wakeup and suspend interrupts */ + usb_regs->gr->GINTF = 0xBFFFFFFFU; + + usb_regs->gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE | \ + GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; + +#endif /* USE_OTG_MODE */ + + return USB_OK; +} + +/*! + \brief write a packet into the Tx FIFO associated with the endpoint + \param[in] usb_regs: pointer to USB core registers + \param[in] src_buf: pointer to source buffer + \param[in] fifo_num: FIFO number which is in (0..3) + \param[in] byte_count: packet byte count + \param[out] none + \retval operation status +*/ +usb_status usb_txfifo_write(usb_core_regs *usb_regs, + uint8_t *src_buf, + uint8_t fifo_num, + uint16_t byte_count) +{ + uint32_t word_count = (byte_count + 3U) / 4U; + + __IO uint32_t *fifo = usb_regs->DFIFO[fifo_num]; + + while(word_count-- > 0U) { + *fifo = *((__packed uint32_t *)src_buf); + + src_buf += 4U; + } + + return USB_OK; +} + +/*! + \brief read a packet from the Rx FIFO associated with the endpoint + \param[in] usb_regs: pointer to USB core registers + \param[in] dest_buf: pointer to destination buffer + \param[in] byte_count: packet byte count + \param[out] none + \retval void type pointer +*/ +void *usb_rxfifo_read(usb_core_regs *usb_regs, uint8_t *dest_buf, uint16_t byte_count) +{ + uint32_t word_count = (byte_count + 3U) / 4U; + + __IO uint32_t *fifo = usb_regs->DFIFO[0]; + + while(word_count-- > 0U) { + *(__packed uint32_t *)dest_buf = *fifo; + + dest_buf += 4U; + } + + return ((void *)dest_buf); +} + +/*! + \brief flush a Tx FIFO or all Tx FIFOs + \param[in] usb_regs: pointer to USB core registers + \param[in] fifo_num: FIFO number which is in (0..3) + \param[out] none + \retval operation status +*/ +usb_status usb_txfifo_flush(usb_core_regs *usb_regs, uint8_t fifo_num) +{ + usb_regs->gr->GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; + + /* wait for Tx FIFO flush bit is set */ + while(usb_regs->gr->GRSTCTL & GRSTCTL_TXFF) { + /* no operation */ + } + + /* wait for 3 PHY clocks*/ + usb_udelay(3U); + + return USB_OK; +} + +/*! + \brief flush the entire Rx FIFO + \param[in] usb_regs: pointer to usb core registers + \param[out] none + \retval operation status +*/ +usb_status usb_rxfifo_flush(usb_core_regs *usb_regs) +{ + usb_regs->gr->GRSTCTL = GRSTCTL_RXFF; + + /* wait for Rx FIFO flush bit is set */ + while(usb_regs->gr->GRSTCTL & GRSTCTL_RXFF) { + /* no operation */ + } + + /* wait for 3 PHY clocks */ + usb_udelay(3U); + + return USB_OK; +} + +/*! + \brief set endpoint or channel TX FIFO size + \param[in] usb_regs: pointer to USB core registers + \param[in] fifo: TX FIFO number + \param[in] size: assigned TX FIFO size + \param[out] none + \retval none +*/ +void usb_set_txfifo(usb_core_regs *usb_regs, uint8_t fifo, uint16_t size) +{ + uint32_t tx_offset; + + tx_offset = usb_regs->gr->GRFLEN; + + if(fifo == 0U) { + usb_regs->gr->DIEP0TFLEN_HNPTFLEN = ((uint32_t)size << 16) | tx_offset; + } else { + tx_offset += (usb_regs->gr->DIEP0TFLEN_HNPTFLEN) >> 16; + + for(uint8_t i = 0U; i < (fifo - 1U); i++) { + tx_offset += (usb_regs->gr->DIEPTFLEN[i] >> 16); + } + + /* Multiply Tx_Size by 2 to get higher performance */ + usb_regs->gr->DIEPTFLEN[fifo - 1U] = ((uint32_t)size << 16) | tx_offset; + } +} + +/*! + \brief set USB current mode + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +void usb_curmode_set(usb_core_regs *usb_regs, uint8_t mode) +{ + usb_regs->gr->GUSBCS &= ~(GUSBCS_FDM | GUSBCS_FHM); + + if(DEVICE_MODE == mode) { + usb_regs->gr->GUSBCS |= GUSBCS_FDM; + } else if(HOST_MODE == mode) { + usb_regs->gr->GUSBCS |= GUSBCS_FHM; + } else { + /* OTG mode and other mode can not be here! */ + } +} + +/*! + \brief configure USB core to soft reset + \param[in] usb_regs: pointer to USB core registers + \param[out] none + \retval none +*/ +static void usb_core_reset(usb_core_regs *usb_regs) +{ + /* enable core soft reset */ + usb_regs->gr->GRSTCTL |= GRSTCTL_CSRST; + + /* wait for the core to be soft reset */ + while(usb_regs->gr->GRSTCTL & GRSTCTL_CSRST) { + /* no operation */ + } + + /* wait for additional 3 PHY clocks */ + usb_udelay(3U); +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Source/drv_usb_dev.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Source/drv_usb_dev.c new file mode 100644 index 000000000..3b00ab019 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Source/drv_usb_dev.c @@ -0,0 +1,609 @@ +/*! + \file drv_usb_dev.c + \brief USB device mode low level driver + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "drv_usb_core.h" +#include "drv_usb_dev.h" + +/* endpoint 0 max packet length */ +static const uint8_t EP0_MAXLEN[4] = { + [DSTAT_EM_HS_PHY_30MHZ_60MHZ] = EP0MPL_64, + [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = EP0MPL_64, + [DSTAT_EM_FS_PHY_48MHZ] = EP0MPL_64, + [DSTAT_EM_LS_PHY_6MHZ] = EP0MPL_8 +}; + +#ifdef USB_FS_CORE + +/* USB endpoint Tx FIFO size */ +static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_EP_COUNT] = { + (uint16_t)TX0_FIFO_FS_SIZE, + (uint16_t)TX1_FIFO_FS_SIZE, + (uint16_t)TX2_FIFO_FS_SIZE, + (uint16_t)TX3_FIFO_FS_SIZE +}; + +#endif /* USBFS_CORE */ + +/*! + \brief initialize USB core registers for device mode + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +usb_status usb_devcore_init(usb_core_driver *udev) +{ + uint8_t i; + + /* restart the PHY clock (maybe don't need to...) */ + *udev->regs.PWRCLKCTL = 0U; + + /* config periodic frame interval to default value */ + udev->regs.dr->DCFG &= ~DCFG_EOPFT; + udev->regs.dr->DCFG |= FRAME_INTERVAL_80; + + udev->regs.dr->DCFG &= ~DCFG_DS; + +#ifdef USB_FS_CORE + if(udev->bp.core_enum == (uint8_t)USB_CORE_ENUM_FS) { + /* set full-speed PHY */ + udev->regs.dr->DCFG |= USB_SPEED_INP_FULL; + + /* set Rx FIFO size */ + usb_set_rxfifo(&udev->regs, RX_FIFO_FS_SIZE); + + /* set endpoint 0 to 3's Tx FIFO length and RAM address */ + for(i = 0U; i < USBFS_MAX_EP_COUNT; i++) { + usb_set_txfifo(&udev->regs, i, USBFS_TX_FIFO_SIZE[i]); + } + } +#endif /* USB_FS_CORE */ + + /* make sure all FIFOs are flushed */ + + /* flush all Tx FIFOs */ + (void)usb_txfifo_flush(&udev->regs, 0x10U); + + /* flush entire Rx FIFO */ + (void)usb_rxfifo_flush(&udev->regs); + + /* clear all pending device interrupts */ + udev->regs.dr->DIEPINTEN = 0U; + udev->regs.dr->DOEPINTEN = 0U; + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + udev->regs.dr->DAEPINTEN = 0U; + + /* configure all IN/OUT endpoints */ + for(i = 0U; i < udev->bp.num_ep; i++) { + if(udev->regs.er_in[i]->DIEPCTL & DEPCTL_EPEN) { + udev->regs.er_in[i]->DIEPCTL |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + udev->regs.er_in[i]->DIEPCTL = 0U; + } + + /* set IN endpoint transfer length to 0 */ + udev->regs.er_in[i]->DIEPLEN = 0U; + + /* clear all pending IN endpoint interrupts */ + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + + if(udev->regs.er_out[i]->DOEPCTL & DEPCTL_EPEN) { + udev->regs.er_out[i]->DOEPCTL |= DEPCTL_EPD | DEPCTL_SNAK; + } else { + udev->regs.er_out[i]->DOEPCTL = 0U; + } + + /* set OUT endpoint transfer length to 0 */ + udev->regs.er_out[i]->DOEPLEN = 0U; + + /* clear all pending OUT endpoint interrupts */ + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + udev->regs.dr->DIEPINTEN |= DIEPINTEN_EPTXFUDEN; + + (void)usb_devint_enable(udev); + + return USB_OK; +} + +/*! + \brief enable the USB device mode interrupts + \param[in] udev: pointer to USB device + \param[out] none + \retval operation status +*/ +usb_status usb_devint_enable(usb_core_driver *udev) +{ + /* clear any pending USB OTG interrupts */ + udev->regs.gr->GOTGINTF = 0xFFFFFFFFU; + + /* clear any pending interrupts */ + udev->regs.gr->GINTF = 0xBFFFFFFFU; + + /* enable the USB wakeup and suspend interrupts */ + udev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; + + /* enable device_mode-related interrupts */ + if((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) { + udev->regs.gr->GINTEN |= GINTEN_RXFNEIE; + } + + udev->regs.gr->GINTEN |= GINTEN_RSTIE | GINTEN_ENUMFIE | GINTEN_IEPIE | \ + GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_ISOONCIE | GINTEN_ISOINCIE; + +#ifdef VBUS_SENSING_ENABLED + udev->regs.gr->GINTEN |= GINTEN_SESIE | GINTEN_OTGIE; +#endif /* VBUS_SENSING_ENABLED */ + + return USB_OK; +} + +/*! + \brief active the USB endpoint0 transaction + \param[in] udev: pointer to USB device + \param[in] transc: the USB endpoint0 transaction + \param[out] none + \retval operation status +*/ +usb_status usb_transc0_active(usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + /* get the endpoint number */ + uint8_t ep_num = transc->ep_addr.num; + + if(ep_num) { + /* not endpoint 0 */ + return USB_FAIL; + } + + if(transc->ep_addr.dir) { + reg_addr = &udev->regs.er_in[0]->DIEPCTL; + } else { + reg_addr = &udev->regs.er_out[0]->DOEPCTL; + } + + /* endpoint 0 is activated after USB clock is enabled */ + + *reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM); + + /* set endpoint 0 maximum packet length */ + *reg_addr |= EP0_MAXLEN[udev->regs.dr->DSTAT & DSTAT_ES]; + + /* activate endpoint */ + *reg_addr |= ((uint32_t)transc->ep_type << 18U) | ((uint32_t)ep_num << 22U) | DEPCTL_SD0PID | DEPCTL_EPACT; + + return USB_OK; +} + +/*! + \brief active the USB transaction + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_active(usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + __IO uint32_t epinten = 0U; + + /* get the endpoint number */ + uint8_t ep_num = transc->ep_addr.num; + + /* enable endpoint interrupt number */ + if(transc->ep_addr.dir) { + reg_addr = &udev->regs.er_in[ep_num]->DIEPCTL; + + epinten = 1U << ep_num; + } else { + reg_addr = &udev->regs.er_out[ep_num]->DOEPCTL; + + epinten = 1U << (16U + ep_num); + } + + /* if the endpoint is not active, need change the endpoint control register */ + if(!(*reg_addr & DEPCTL_EPACT)) { + *reg_addr &= ~(DEPCTL_MPL | DEPCTL_EPTYPE | DIEPCTL_TXFNUM); + + /* set endpoint maximum packet length */ + if(0U == ep_num) { + *reg_addr |= EP0_MAXLEN[udev->regs.dr->DSTAT & DSTAT_ES]; + } else { + *reg_addr |= transc->max_len; + } + + /* activate endpoint */ + *reg_addr |= ((uint32_t)transc->ep_type << 18U) | ((uint32_t)ep_num << 22U) | DEPCTL_SD0PID | DEPCTL_EPACT; + } + + + /* enable the interrupts for this endpoint */ + udev->regs.dr->DAEPINTEN |= epinten; + + return USB_OK; +} + +/*! + \brief deactivate the USB transaction + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_deactivate(usb_core_driver *udev, usb_transc *transc) +{ + uint32_t epinten = 0U; + + uint8_t ep_num = transc->ep_addr.num; + + /* disable endpoint interrupt number */ + if(transc->ep_addr.dir) { + epinten = 1U << ep_num; + + udev->regs.er_in[ep_num]->DIEPCTL &= ~DEPCTL_EPACT; + } else { + epinten = 1U << (ep_num + 16U); + + udev->regs.er_out[ep_num]->DOEPCTL &= ~DEPCTL_EPACT; + } + + + /* disable the interrupts for this endpoint */ + udev->regs.dr->DAEPINTEN &= ~epinten; + + return USB_OK; +} + +/*! + \brief configure USB transaction to start IN transfer + \param[in] udev: pointer to USB device + \param[in] transc: the USB IN transaction + \param[out] none + \retval operation status +*/ +usb_status usb_transc_inxfer(usb_core_driver *udev, usb_transc *transc) +{ + usb_status status = USB_OK; + + uint8_t ep_num = transc->ep_addr.num; + + __IO uint32_t epctl = udev->regs.er_in[ep_num]->DIEPCTL; + __IO uint32_t eplen = udev->regs.er_in[ep_num]->DIEPLEN; + + eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT); + + /* zero length packet or endpoint 0 */ + if(0U == transc->xfer_len) { + /* set transfer packet count to 1 */ + eplen |= 1U << 19U; + } else { + /* set transfer packet count */ + if(0U == ep_num) { + transc->xfer_len = USB_MIN(transc->xfer_len, transc->max_len); + + eplen |= 1U << 19U; + } else { + eplen |= (((transc->xfer_len - 1U) + transc->max_len) / transc->max_len) << 19U; + } + + /* set endpoint transfer length */ + eplen |= transc->xfer_len; + + if(transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) { + eplen |= DIEPLEN_MCNT & (1U << 29U); + } + } + + udev->regs.er_in[ep_num]->DIEPLEN = eplen; + + if(transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) { + if(((udev->regs.dr->DSTAT & DSTAT_FNRSOF) >> 8U) & 0x01U) { + epctl |= DEPCTL_SEVNFRM; + } else { + epctl |= DEPCTL_SODDFRM; + } + } + + if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_in[ep_num]->DIEPDMAADDR = transc->dma_addr; + } + + /* enable the endpoint and clear the NAK */ + epctl |= DEPCTL_CNAK | DEPCTL_EPEN; + + udev->regs.er_in[ep_num]->DIEPCTL = epctl; + + if((uint8_t)USB_USE_FIFO == udev->bp.transfer_mode) { + if(transc->ep_type != (uint8_t)USB_EPTYPE_ISOC) { + /* enable the Tx FIFO empty interrupt for this endpoint */ + if(transc->xfer_len > 0U) { + udev->regs.dr->DIEPFEINTEN |= 1U << ep_num; + } + } else { + (void)usb_txfifo_write(&udev->regs, transc->xfer_buf, ep_num, (uint16_t)transc->xfer_len); + } + } + + return status; +} + +/*! + \brief configure usb transaction to start OUT transfer + \param[in] udev: pointer to usb device + \param[in] transc: the usb OUT transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_outxfer(usb_core_driver *udev, usb_transc *transc) +{ + usb_status status = USB_OK; + + uint8_t ep_num = transc->ep_addr.num; + + uint32_t epctl = udev->regs.er_out[ep_num]->DOEPCTL; + uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN; + + eplen &= ~(DEPLEN_TLEN | DEPLEN_PCNT); + + /* zero length packet or endpoint 0 */ + if((0U == transc->xfer_len) || (0U == ep_num)) { + /* set the transfer length to max packet size */ + eplen |= transc->max_len; + + /* set the transfer packet count to 1 */ + eplen |= 1U << 19U; + } else { + /* configure the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + uint32_t packet_count = (transc->xfer_len + transc->max_len - 1U) / transc->max_len; + + eplen |= packet_count << 19U; + eplen |= packet_count * transc->max_len; + } + + udev->regs.er_out[ep_num]->DOEPLEN = eplen; + + if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_out[ep_num]->DOEPDMAADDR = transc->dma_addr; + } + + if(transc->ep_type == (uint8_t)USB_EPTYPE_ISOC) { + if(transc->frame_num) { + epctl |= DEPCTL_SD1PID; + } else { + epctl |= DEPCTL_SD0PID; + } + } + + /* enable the endpoint and clear the NAK */ + epctl |= DEPCTL_EPEN | DEPCTL_CNAK; + + udev->regs.er_out[ep_num]->DOEPCTL = epctl; + + return status; +} + +/*! + \brief set the USB transaction STALL status + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval status +*/ +usb_status usb_transc_stall(usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint8_t ep_num = transc->ep_addr.num; + + if(transc->ep_addr.dir) { + reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL); + + /* set the endpoint disable bit */ + if(*reg_addr & DEPCTL_EPEN) { + *reg_addr |= DEPCTL_EPD; + } + } else { + /* set the endpoint stall bit */ + reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL); + } + + /* set the endpoint stall bit */ + *reg_addr |= DEPCTL_STALL; + + return USB_OK; +} + +/*! + \brief clear the USB transaction STALL status + \param[in] udev: pointer to USB device + \param[in] transc: the USB transaction + \param[out] none + \retval operation status +*/ +usb_status usb_transc_clrstall(usb_core_driver *udev, usb_transc *transc) +{ + __IO uint32_t *reg_addr = NULL; + + uint8_t ep_num = transc->ep_addr.num; + + if(transc->ep_addr.dir) { + reg_addr = &(udev->regs.er_in[ep_num]->DIEPCTL); + } else { + reg_addr = &(udev->regs.er_out[ep_num]->DOEPCTL); + } + + /* clear the endpoint stall bits */ + *reg_addr &= ~DEPCTL_STALL; + + /* reset data PID of the periodic endpoints */ + if((transc->ep_type == (uint8_t)USB_EPTYPE_INTR) || (transc->ep_type == (uint8_t)USB_EPTYPE_BULK)) { + *reg_addr |= DEPCTL_SD0PID; + } + + return USB_OK; +} + +/*! + \brief read device IN endpoint interrupt flag register + \param[in] udev: pointer to USB device + \param[in] ep_num: endpoint number + \param[out] none + \retval interrupt value +*/ +uint32_t usb_iepintr_read(usb_core_driver *udev, uint8_t ep_num) +{ + uint32_t value = 0U, fifoemptymask, commonintmask; + + commonintmask = udev->regs.dr->DIEPINTEN; + fifoemptymask = udev->regs.dr->DIEPFEINTEN; + + /* check FIFO empty interrupt enable bit */ + commonintmask |= ((fifoemptymask >> ep_num) & 0x1U) << 7; + + value = udev->regs.er_in[ep_num]->DIEPINTF & commonintmask; + + return value; +} + +/*! + \brief configures OUT endpoint 0 to receive SETUP packets + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_ctlep_startout(usb_core_driver *udev) +{ + /* set OUT endpoint 0 receive length to 24 bytes, 1 packet and 3 setup packets */ + udev->regs.er_out[0]->DOEPLEN = DOEP0_TLEN(8U * 3U) | DOEP0_PCNT(1U) | DOEP0_STPCNT(3U); + + if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + udev->regs.er_out[0]->DOEPDMAADDR = (uint32_t)&udev->dev.control.req; + + /* endpoint enable */ + udev->regs.er_out[0]->DOEPCTL |= DEPCTL_EPACT | DEPCTL_EPEN; + } +} + +/*! + \brief active remote wakeup signaling + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_rwkup_active(usb_core_driver *udev) +{ + if(udev->dev.pm.dev_remote_wakeup) { + if(udev->regs.dr->DSTAT & DSTAT_SPST) { + if(udev->bp.low_power) { + /* ungate USB core clock */ + *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK); + } + + /* active remote wakeup signaling */ + udev->regs.dr->DCTL |= DCTL_RWKUP; + + usb_mdelay(5U); + + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + } + } +} + +/*! + \brief active USB core clock + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_clock_active(usb_core_driver *udev) +{ + if(udev->bp.low_power) { + if(udev->regs.dr->DSTAT & DSTAT_SPST) { + /* un-gate USB Core clock */ + *udev->regs.PWRCLKCTL &= ~(PWRCLKCTL_SHCLK | PWRCLKCTL_SUCLK); + } + } +} + +/*! + \brief USB device suspend + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_dev_suspend(usb_core_driver *udev) +{ + __IO uint32_t devstat = udev->regs.dr->DSTAT; + + if((udev->bp.low_power) && (devstat & DSTAT_SPST)) { + /* switch-off the USB clocks */ + *udev->regs.PWRCLKCTL |= PWRCLKCTL_SHCLK; + + /* enter DEEP_SLEEP mode with LDO in low power mode */ + pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD); + } +} + +/*! + \brief stop the device and clean up FIFOs + \param[in] udev: pointer to USB device + \param[out] none + \retval none +*/ +void usb_dev_stop(usb_core_driver *udev) +{ + uint32_t i; + + udev->dev.cur_status = 1U; + + /* clear all interrupt flag and enable bits */ + for(i = 0U; i < udev->bp.num_ep; i++) { + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + udev->regs.dr->DIEPINTEN = 0U; + udev->regs.dr->DOEPINTEN = 0U; + udev->regs.dr->DAEPINTEN = 0U; + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + + /* flush the FIFO */ + (void)usb_rxfifo_flush(&udev->regs); + (void)usb_txfifo_flush(&udev->regs, 0x10U); +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Source/drv_usb_host.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Source/drv_usb_host.c new file mode 100644 index 000000000..130fadc2c --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Source/drv_usb_host.c @@ -0,0 +1,452 @@ +/*! + \file drv_usb_host.c + \brief USB host mode low level driver + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "drv_usb_core.h" +#include "drv_usb_host.h" + +const uint32_t PIPE_DPID[2] = { + PIPE_DPID_DATA0, + PIPE_DPID_DATA1 +}; + +/*! + \brief initializes USB core for host mode + \param[in] pudev: pointer to selected usb host + \param[out] none + \retval operation status +*/ +usb_status usb_host_init(usb_core_driver *pudev) +{ + uint32_t i = 0U, inten = 0U; + + uint32_t nptxfifolen = 0U; + uint32_t ptxfifolen = 0U; + + /* restart the PHY Clock */ + *pudev->regs.PWRCLKCTL = 0U; + + /* support FS/LS only */ + pudev->regs.hr->HCTL &= ~HCTL_SPDFSLS; + + /* configure data FIFOs size */ +#ifdef USB_FS_CORE + if(USB_CORE_ENUM_FS == pudev->bp.core_enum) { + /* set Rx FIFO size */ + pudev->regs.gr->GRFLEN = USB_RX_FIFO_FS_SIZE; + + /* set non-periodic Tx FIFO size and address */ + nptxfifolen |= USB_RX_FIFO_FS_SIZE; + nptxfifolen |= USB_HTX_NPFIFO_FS_SIZE << 16U; + pudev->regs.gr->DIEP0TFLEN_HNPTFLEN = nptxfifolen; + + /* set periodic Tx FIFO size and address */ + ptxfifolen |= USB_RX_FIFO_FS_SIZE + USB_HTX_NPFIFO_FS_SIZE; + ptxfifolen |= USB_HTX_PFIFO_FS_SIZE << 16U; + pudev->regs.gr->HPTFLEN = ptxfifolen; + } +#endif /* USB_FS_CORE */ + +#ifdef USE_OTG_MODE + + /* clear host set hnp enable in the usb_otg control register */ + pudev->regs.gr->GOTGCS &= ~GOTGCS_HHNPEN; + +#endif /* USE_OTG_MODE */ + + /* make sure the FIFOs are flushed */ + + /* flush all Tx FIFOs in device or host mode */ + usb_txfifo_flush(&pudev->regs, 0x10U); + + /* flush the entire Rx FIFO */ + usb_rxfifo_flush(&pudev->regs); + + /* disable all interrupts */ + pudev->regs.gr->GINTEN = 0U; + + /* clear any pending USB OTG interrupts */ + pudev->regs.gr->GOTGINTF = 0xFFFFFFFFU; + + /* enable the USB wakeup and suspend interrupts */ + pudev->regs.gr->GINTF = 0xBFFFFFFFU; + + /* clear all pending host channel interrupts */ + for(i = 0U; i < pudev->bp.num_pipe; i++) { + pudev->regs.pr[i]->HCHINTF = 0xFFFFFFFFU; + pudev->regs.pr[i]->HCHINTEN = 0U; + } + +#ifndef USE_OTG_MODE + usb_portvbus_switch(pudev, 1U); +#endif /* USE_OTG_MODE */ + + pudev->regs.gr->GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; + + /* enable host_mode-related interrupts */ + if(USB_USE_FIFO == pudev->bp.transfer_mode) { + inten = GINTEN_RXFNEIE; + } + + inten |= GINTEN_SESIE | GINTEN_HPIE | GINTEN_HCIE | GINTEN_ISOINCIE; + + pudev->regs.gr->GINTEN |= inten; + + inten = GINTEN_DISCIE | GINTEN_SOFIE; + + pudev->regs.gr->GINTEN &= ~inten; + + return USB_OK; +} + +/*! + \brief control the VBUS to power + \param[in] pudev: pointer to selected usb host + \param[in] state: VBUS state + \param[out] none + \retval none +*/ +void usb_portvbus_switch(usb_core_driver *pudev, uint8_t state) +{ + uint32_t port = 0U; + + /* enable or disable the external charge pump */ + usb_vbus_drive(state); + + /* turn on the host port power. */ + port = usb_port_read(pudev); + + if(!(port & HPCS_PP) && (1U == state)) { + port |= HPCS_PP; + } + + if((port & HPCS_PP) && (0U == state)) { + port &= ~HPCS_PP; + } + + *pudev->regs.HPCS = port; + + usb_mdelay(200U); +} + +/*! + \brief reset host port + \param[in] pudev: pointer to usb device + \param[out] none + \retval operation status +*/ +uint32_t usb_port_reset(usb_core_driver *pudev) +{ + __IO uint32_t port = usb_port_read(pudev); + + *pudev->regs.HPCS = port | HPCS_PRST; + + usb_mdelay(20U); /* see note */ + + *pudev->regs.HPCS = port & ~HPCS_PRST; + + usb_mdelay(20U); + + return 1U; +} + +/*! + \brief initialize host pipe + \param[in] pudev: pointer to usb device + \param[in] pipe_num: host pipe number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status usb_pipe_init(usb_core_driver *pudev, uint8_t pipe_num) +{ + usb_status status = USB_OK; + + __IO uint32_t pp_ctl = 0U; + __IO uint32_t pp_inten = HCHINTEN_TFIE; + + usb_pipe *pp = &pudev->host.pipe[pipe_num]; + + /* clear old interrupt conditions for this host channel */ + pudev->regs.pr[pipe_num]->HCHINTF = 0xFFFFFFFFU; + + if(USB_USE_DMA == pudev->bp.transfer_mode) { + pp_inten |= HCHINTEN_DMAERIE; + } + + if(pp->ep.dir) { + pp_inten |= HCHINTEN_BBERIE; + } + + /* enable channel interrupts required for this transfer */ + switch(pp->ep.type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + pp_inten |= HCHINTEN_STALLIE | HCHINTEN_USBERIE \ + | HCHINTEN_DTERIE | HCHINTEN_NAKIE; + + if(!pp->ep.dir) { + pp_inten |= HCHINTEN_NYETIE; + + if(pp->ping) { + pp_inten |= HCHINTEN_ACKIE; + } + } + break; + + case USB_EPTYPE_INTR: + pp_inten |= HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE \ + | HCHINTEN_NAKIE | HCHINTEN_REQOVRIE; + break; + + case USB_EPTYPE_ISOC: + pp_inten |= HCHINTEN_REQOVRIE | HCHINTEN_ACKIE; + + if(pp->ep.dir) { + pp_inten |= HCHINTEN_USBERIE; + } + break; + + default: + break; + } + + pudev->regs.pr[pipe_num]->HCHINTEN = pp_inten; + + /* enable the top level host channel interrupt */ + pudev->regs.hr->HACHINTEN |= 1U << pipe_num; + + /* make sure host channel interrupts are enabled */ + pudev->regs.gr->GINTEN |= GINTEN_HCIE; + + /* program the host channel control register */ + pp_ctl |= PIPE_CTL_DAR(pp->dev_addr); + pp_ctl |= PIPE_CTL_EPNUM(pp->ep.num); + pp_ctl |= PIPE_CTL_EPDIR(pp->ep.dir); + pp_ctl |= PIPE_CTL_EPTYPE(pp->ep.type); + pp_ctl |= PIPE_CTL_LSD(pp->dev_speed == PORT_SPEED_LOW); + + pp_ctl |= pp->ep.mps; + pp_ctl |= ((uint32_t)(pp->ep.type == USB_EPTYPE_INTR) << 29U) & HCHCTL_ODDFRM; + + pudev->regs.pr[pipe_num]->HCHCTL = pp_ctl; + + return status; +} + +/*! + \brief prepare host channel for transferring packets + \param[in] pudev: pointer to usb device + \param[in] pipe_num: host pipe number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status usb_pipe_xfer(usb_core_driver *pudev, uint8_t pipe_num) +{ + usb_status status = USB_OK; + + uint16_t dword_len = 0U; + uint16_t packet_count = 0U; + + __IO uint32_t pp_ctl = 0U; + + usb_pipe *pp = &pudev->host.pipe[pipe_num]; + + uint16_t max_packet_len = pp->ep.mps; + + /* compute the expected number of packets associated to the transfer */ + if(pp->xfer_len > 0U) { + packet_count = (uint16_t)((pp->xfer_len + max_packet_len - 1U) / max_packet_len); + + if(packet_count > HC_MAX_PACKET_COUNT) { + packet_count = HC_MAX_PACKET_COUNT; + pp->xfer_len = (uint16_t)(packet_count * max_packet_len); + } + } else { + packet_count = 1U; + } + + if(pp->ep.dir) { + pp->xfer_len = (uint16_t)(packet_count * max_packet_len); + } + + /* initialize the host channel transfer information */ + pudev->regs.pr[pipe_num]->HCHLEN = pp->xfer_len | pp->DPID | PIPE_XFER_PCNT(packet_count); + + if(USB_USE_DMA == pudev->bp.transfer_mode) { + pudev->regs.pr[pipe_num]->HCHDMAADDR = (unsigned int)pp->xfer_buf; + } + + pp_ctl = pudev->regs.pr[pipe_num]->HCHCTL; + + if(usb_frame_even(pudev)) { + pp_ctl |= HCHCTL_ODDFRM; + } else { + pp_ctl &= ~HCHCTL_ODDFRM; + } + + /* set host channel enabled */ + pp_ctl |= HCHCTL_CEN; + pp_ctl &= ~HCHCTL_CDIS; + + pudev->regs.pr[pipe_num]->HCHCTL = pp_ctl; + + if(USB_USE_FIFO == pudev->bp.transfer_mode) { + if((0U == pp->ep.dir) && (pp->xfer_len > 0U)) { + switch(pp->ep.type) { + /* non-periodic transfer */ + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + dword_len = (uint16_t)((pp->xfer_len + 3U) / 4U); + + /* check if there is enough space in fifo space */ + if(dword_len > (pudev->regs.gr->HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { + /* need to process data in nptxfempty interrupt */ + pudev->regs.gr->GINTEN |= GINTEN_NPTXFEIE; + } + break; + + /* periodic transfer */ + case USB_EPTYPE_INTR: + case USB_EPTYPE_ISOC: + dword_len = (uint16_t)((pp->xfer_len + 3U) / 4U); + + /* check if there is enough space in fifo space */ + if(dword_len > (pudev->regs.hr->HPTFQSTAT & HPTFQSTAT_PTXFS)) { + /* need to process data in ptxfempty interrupt */ + pudev->regs.gr->GINTEN |= GINTEN_PTXFEIE; + } + break; + + default: + break; + } + + /* write packet into the tx fifo. */ + usb_txfifo_write(&pudev->regs, pp->xfer_buf, pipe_num, (uint16_t)pp->xfer_len); + } + } + + return status; +} + +/*! + \brief halt pipe + \param[in] pudev: pointer to usb device + \param[in] pipe_num: host pipe number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status usb_pipe_halt(usb_core_driver *pudev, uint8_t pipe_num) +{ + __IO uint32_t pp_ctl = pudev->regs.pr[pipe_num]->HCHCTL; + + uint8_t ep_type = (uint8_t)((pp_ctl & HCHCTL_EPTYPE) >> 18U); + + pp_ctl |= HCHCTL_CEN | HCHCTL_CDIS; + + switch(ep_type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + if(0U == (pudev->regs.gr->HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { + pp_ctl &= ~HCHCTL_CEN; + } + break; + + case USB_EPTYPE_INTR: + case USB_EPTYPE_ISOC: + if(0U == (pudev->regs.hr->HPTFQSTAT & HPTFQSTAT_PTXFS)) { + pp_ctl &= ~HCHCTL_CEN; + } + break; + + default: + break; + } + + pudev->regs.pr[pipe_num]->HCHCTL = pp_ctl; + + return USB_OK; +} + +/*! + \brief configure host pipe to do ping operation + \param[in] pudev: pointer to usb device + \param[in] pipe_num: host pipe number which is in (0..7) + \param[out] none + \retval operation status +*/ +usb_status usb_pipe_ping(usb_core_driver *pudev, uint8_t pipe_num) +{ + uint32_t pp_ctl = 0U; + + pudev->regs.pr[pipe_num]->HCHLEN = HCHLEN_PING | (HCHLEN_PCNT & (1U << 19U)); + + pp_ctl = pudev->regs.pr[pipe_num]->HCHCTL; + + pp_ctl |= HCHCTL_CEN; + pp_ctl &= ~HCHCTL_CDIS; + + pudev->regs.pr[pipe_num]->HCHCTL = pp_ctl; + + return USB_OK; +} + +/*! + \brief stop the USB host and clean up FIFO + \param[in] pudev: pointer to usb device + \param[out] none + \retval none +*/ +void usb_host_stop(usb_core_driver *pudev) +{ + uint32_t i; + __IO uint32_t pp_ctl = 0U; + + pudev->regs.hr->HACHINTEN = 0x0U; + pudev->regs.hr->HACHINT = 0xFFFFFFFFU; + + /* flush out any leftover queued requests. */ + for(i = 0U; i < pudev->bp.num_pipe; i++) { + pp_ctl = pudev->regs.pr[i]->HCHCTL; + + pp_ctl &= ~(HCHCTL_CEN | HCHCTL_EPDIR); + pp_ctl |= HCHCTL_CDIS; + + pudev->regs.pr[i]->HCHCTL = pp_ctl; + } + + /* flush the FIFO */ + usb_rxfifo_flush(&pudev->regs); + usb_txfifo_flush(&pudev->regs, 0x10U); +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Source/drv_usbd_int.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Source/drv_usbd_int.c new file mode 100644 index 000000000..21dbf17a0 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Source/drv_usbd_int.c @@ -0,0 +1,491 @@ +/*! + \file drv_usbd_int.c + \brief USB device mode interrupt routines + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbd_conf.h" +#include "drv_usbd_int.h" +#include "usbd_transc.h" + +/* local function prototypes ('static') */ +static uint32_t usbd_int_epout(usb_core_driver *udev); +static uint32_t usbd_int_epin(usb_core_driver *udev); +static uint32_t usbd_int_rxfifo(usb_core_driver *udev); +static uint32_t usbd_int_reset(usb_core_driver *udev); +static uint32_t usbd_int_enumfinish(usb_core_driver *udev); +static uint32_t usbd_int_suspend(usb_core_driver *udev); +static uint32_t usbd_emptytxfifo_write(usb_core_driver *udev, uint32_t ep_num); + +static const uint8_t USB_SPEED[4] = { + [DSTAT_EM_HS_PHY_30MHZ_60MHZ] = (uint8_t)USB_SPEED_HIGH, + [DSTAT_EM_FS_PHY_30MHZ_60MHZ] = (uint8_t)USB_SPEED_FULL, + [DSTAT_EM_FS_PHY_48MHZ] = (uint8_t)USB_SPEED_FULL, + [DSTAT_EM_LS_PHY_6MHZ] = (uint8_t)USB_SPEED_LOW +}; + +/*! + \brief USB device-mode interrupts global service routine handler + \param[in] udev: pointer to USB device instance + \param[out] none + \retval none +*/ +void usbd_isr(usb_core_driver *udev) +{ + if(HOST_MODE != (udev->regs.gr->GINTF & GINTF_COPM)) { + uint32_t intr = udev->regs.gr->GINTF & udev->regs.gr->GINTEN; + + /* there are no interrupts, avoid spurious interrupt */ + if(!intr) { + return; + } + + /* OUT endpoints interrupts */ + if(intr & GINTF_OEPIF) { + (void)usbd_int_epout(udev); + } + + /* IN endpoints interrupts */ + if(intr & GINTF_IEPIF) { + (void)usbd_int_epin(udev); + } + + /* suspend interrupt */ + if(intr & GINTF_SP) { + (void)usbd_int_suspend(udev); + } + + /* wakeup interrupt */ + if(intr & GINTF_WKUPIF) { + /* inform upper layer by the resume event */ + udev->dev.cur_status = USBD_CONFIGURED; + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_WKUPIF; + } + + /* start of frame interrupt */ + if(intr & GINTF_SOF) { + if(udev->dev.class_core->SOF) { + (void)udev->dev.class_core->SOF(udev); + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_SOF; + } + + /* receive FIFO not empty interrupt */ + if(intr & GINTF_RXFNEIF) { + (void)usbd_int_rxfifo(udev); + } + + /* USB reset interrupt */ + if(intr & GINTF_RST) { + (void)usbd_int_reset(udev); + } + + /* enumeration has been done interrupt */ + if(intr & GINTF_ENUMFIF) { + (void)usbd_int_enumfinish(udev); + } + + /* incomplete synchronization IN transfer interrupt*/ + if(intr & GINTF_ISOINCIF) { + if(NULL != udev->dev.class_core->incomplete_isoc_in) { + (void)udev->dev.class_core->incomplete_isoc_in(udev); + } + + /* Clear interrupt */ + udev->regs.gr->GINTF = GINTF_ISOINCIF; + } + + /* incomplete synchronization OUT transfer interrupt*/ + if(intr & GINTF_ISOONCIF) { + if(NULL != udev->dev.class_core->incomplete_isoc_out) { + (void)udev->dev.class_core->incomplete_isoc_out(udev); + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_ISOONCIF; + } + +#ifdef VBUS_SENSING_ENABLED + + /* Session request interrupt */ + if(intr & GINTF_SESIF) { + udev->regs.gr->GINTF = GINTF_SESIF; + } + + /* OTG mode interrupt */ + if(intr & GINTF_OTGIF) { + if(udev->regs.gr->GOTGINTF & GOTGINTF_SESEND) { + + } + + /* Clear OTG interrupt */ + udev->regs.gr->GINTF = GINTF_OTGIF; + } +#endif /* VBUS_SENSING_ENABLED */ + } +} + +/*! + \brief indicates that an OUT endpoint has a pending interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_epout(usb_core_driver *udev) +{ + uint32_t epintnum = 0U; + uint8_t ep_num = 0U; + + for(epintnum = usb_oepintnum_read(udev); epintnum; epintnum >>= 1, ep_num++) { + if(epintnum & 0x01U) { + __IO uint32_t oepintr = usb_oepintr_read(udev, ep_num); + + /* transfer complete interrupt */ + if(oepintr & DOEPINTF_TF) { + /* clear the bit in DOEPINTF for this interrupt */ + udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_TF; + + if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + __IO uint32_t eplen = udev->regs.er_out[ep_num]->DOEPLEN; + + udev->dev.transc_out[ep_num].xfer_count = udev->dev.transc_out[ep_num].max_len - \ + (eplen & DEPLEN_TLEN); + } + + /* inform upper layer: data ready */ + (void)usbd_out_transc(udev, ep_num); + + if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + if((0U == ep_num) && ((uint8_t)USB_CTL_STATUS_OUT == udev->dev.control.ctl_state)) { + usb_ctlep_startout(udev); + } + } + } + + /* setup phase finished interrupt (control endpoints) */ + if(oepintr & DOEPINTF_STPF) { + /* inform the upper layer that a setup packet is available */ + (void)usbd_setup_transc(udev); + + udev->regs.er_out[ep_num]->DOEPINTF = DOEPINTF_STPF; + } + } + } + + return 1U; +} + +/*! + \brief indicates that an IN endpoint has a pending interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_epin(usb_core_driver *udev) +{ + uint32_t epintnum = 0U; + uint8_t ep_num = 0U; + + for(epintnum = usb_iepintnum_read(udev); epintnum; epintnum >>= 1, ep_num++) { + if(epintnum & 0x1U) { + __IO uint32_t iepintr = usb_iepintr_read(udev, ep_num); + + if(iepintr & DIEPINTF_TF) { + udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TF; + + /* data transmission is completed */ + (void)usbd_in_transc(udev, ep_num); + + if((uint8_t)USB_USE_DMA == udev->bp.transfer_mode) { + if((0U == ep_num) && ((uint8_t)USB_CTL_STATUS_IN == udev->dev.control.ctl_state)) { + usb_ctlep_startout(udev); + } + } + } + + if(iepintr & DIEPINTF_TXFE) { + usbd_emptytxfifo_write(udev, (uint32_t)ep_num); + + udev->regs.er_in[ep_num]->DIEPINTF = DIEPINTF_TXFE; + } + } + } + + return 1U; +} + +/*! + \brief handle the RX status queue level interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_rxfifo(usb_core_driver *udev) +{ + usb_transc *transc = NULL; + + uint8_t data_PID = 0U; + uint32_t bcount = 0U; + + __IO uint32_t devrxstat = 0U; + + /* disable the Rx status queue non-empty interrupt */ + udev->regs.gr->GINTEN &= ~GINTEN_RXFNEIE; + + /* get the status from the top of the FIFO */ + devrxstat = udev->regs.gr->GRSTATP; + + uint8_t ep_num = (uint8_t)(devrxstat & GRSTATRP_EPNUM); + + transc = &udev->dev.transc_out[ep_num]; + + bcount = (devrxstat & GRSTATRP_BCOUNT) >> 4U; + data_PID = (uint8_t)((devrxstat & GRSTATRP_DPID) >> 15U); + + switch((devrxstat & GRSTATRP_RPCKST) >> 17U) { + case RSTAT_GOUT_NAK: + break; + + case RSTAT_DATA_UPDT: + if(bcount > 0U) { + (void)usb_rxfifo_read(&udev->regs, transc->xfer_buf, (uint16_t)bcount); + + transc->xfer_buf += bcount; + transc->xfer_count += bcount; + } + break; + + case RSTAT_XFER_COMP: + /* trigger the OUT endpoint interrupt */ + break; + + case RSTAT_SETUP_COMP: + /* trigger the OUT endpoint interrupt */ + break; + + case RSTAT_SETUP_UPDT: + if((0U == transc->ep_addr.num) && (8U == bcount) && (DPID_DATA0 == data_PID)) { + /* copy the setup packet received in FIFO into the setup buffer in RAM */ + (void)usb_rxfifo_read(&udev->regs, (uint8_t *)&udev->dev.control.req, (uint16_t)bcount); + + transc->xfer_count += bcount; + } + break; + + default: + break; + } + + /* enable the Rx status queue level interrupt */ + udev->regs.gr->GINTEN |= GINTEN_RXFNEIE; + + return 1U; +} + +/*! + \brief handle USB reset interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_int_reset(usb_core_driver *udev) +{ + uint32_t i; + + /* clear the remote wakeup signaling */ + udev->regs.dr->DCTL &= ~DCTL_RWKUP; + + /* flush the Tx FIFO */ + (void)usb_txfifo_flush(&udev->regs, 0U); + + for(i = 0U; i < udev->bp.num_ep; i++) { + udev->regs.er_in[i]->DIEPINTF = 0xFFU; + udev->regs.er_out[i]->DOEPINTF = 0xFFU; + } + + /* clear all pending device endpoint interrupts */ + udev->regs.dr->DAEPINT = 0xFFFFFFFFU; + + /* enable endpoint 0 interrupts */ + udev->regs.dr->DAEPINTEN = 1U | (1U << 16U); + + /* enable OUT endpoint interrupts */ + udev->regs.dr->DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN; + + /* enable IN endpoint interrupts */ + udev->regs.dr->DIEPINTEN = DIEPINTEN_TFEN; + + /* reset device address */ + udev->regs.dr->DCFG &= ~DCFG_DAR; + + /* configure endpoint 0 to receive SETUP packets */ + usb_ctlep_startout(udev); + + /* clear USB reset interrupt */ + udev->regs.gr->GINTF = GINTF_RST; + + udev->dev.transc_out[0] = (usb_transc) { + .ep_type = USB_EPTYPE_CTRL, + .max_len = USB_FS_EP0_MAX_LEN + }; + + (void)usb_transc_active(udev, &udev->dev.transc_out[0]); + + udev->dev.transc_in[0] = (usb_transc) { + .ep_addr = { + .dir = 1U + }, + + .ep_type = USB_EPTYPE_CTRL, + .max_len = USB_FS_EP0_MAX_LEN + }; + + (void)usb_transc_active(udev, &udev->dev.transc_in[0]); + + /* upon reset call user call back */ + udev->dev.cur_status = (uint8_t)USBD_DEFAULT; + + return 1U; +} + +/*! + \brief handle USB speed enumeration finish interrupt + \param[in] udev: pointer to USB device instance + \param[out] none + \retval status +*/ +static uint32_t usbd_int_enumfinish(usb_core_driver *udev) +{ + uint8_t enum_speed = (uint8_t)((udev->regs.dr->DSTAT & DSTAT_ES) >> 1U); + + udev->regs.dr->DCTL &= ~DCTL_CGINAK; + udev->regs.dr->DCTL |= DCTL_CGINAK; + + udev->regs.gr->GUSBCS &= ~GUSBCS_UTT; + + /* set USB turn-around time based on device speed and PHY interface */ + if(USB_SPEED[enum_speed] == (uint8_t)USB_SPEED_HIGH) { + udev->bp.core_speed = (uint8_t)USB_SPEED_HIGH; + + udev->regs.gr->GUSBCS |= 0x09U << 10U; + } else { + udev->bp.core_speed = (uint8_t)USB_SPEED_FULL; + + udev->regs.gr->GUSBCS |= 0x05U << 10U; + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_ENUMFIF; + + return 1U; +} + +/*! + \brief USB suspend interrupt handler + \param[in] udev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbd_int_suspend(usb_core_driver *udev) +{ + __IO uint8_t low_power = udev->bp.low_power; + __IO uint8_t suspend = (uint8_t)(udev->regs.dr->DSTAT & DSTAT_SPST); + __IO uint8_t is_configured = (udev->dev.cur_status == (uint8_t)USBD_CONFIGURED) ? 1U : 0U; + + udev->dev.backup_status = udev->dev.cur_status; + udev->dev.cur_status = (uint8_t)USBD_SUSPENDED; + + if(low_power && suspend && is_configured) { + /* switch-off the OTG clocks */ + *udev->regs.PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK; + + /* enter DEEP_SLEEP mode with LDO in low power mode */ + pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD); + } + + /* clear interrupt */ + udev->regs.gr->GINTF = GINTF_SP; + + return 1U; +} + +/*! + \brief check FIFO for the next packet to be loaded + \param[in] udev: pointer to USB device instance + \param[in] ep_num: endpoint identifier which is in (0..3) + \param[out] none + \retval status +*/ +static uint32_t usbd_emptytxfifo_write(usb_core_driver *udev, uint32_t ep_num) +{ + uint32_t len; + uint32_t word_count; + + usb_transc *transc = &udev->dev.transc_in[ep_num]; + + len = transc->xfer_len - transc->xfer_count; + + /* get the data length to write */ + if(len > transc->max_len) { + len = transc->max_len; + } + + word_count = (len + 3U) / 4U; + + while(((udev->regs.er_in[ep_num]->DIEPTFSTAT & DIEPTFSTAT_IEPTFS) >= word_count) && \ + (transc->xfer_count < transc->xfer_len)) { + len = transc->xfer_len - transc->xfer_count; + + if(len > transc->max_len) { + len = transc->max_len; + } + + /* write FIFO in word(4bytes) */ + word_count = (len + 3U) / 4U; + + /* write the FIFO */ + (void)usb_txfifo_write(&udev->regs, transc->xfer_buf, (uint8_t)ep_num, (uint16_t)len); + + transc->xfer_buf += len; + transc->xfer_count += len; + + if(transc->xfer_count == transc->xfer_len) { + /* disable the device endpoint FIFO empty interrupt */ + udev->regs.dr->DIEPFEINTEN &= ~(0x01U << ep_num); + } + } + + return 1U; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Source/drv_usbh_int.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Source/drv_usbh_int.c new file mode 100644 index 000000000..cf6db76ac --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/driver/Source/drv_usbh_int.c @@ -0,0 +1,624 @@ +/*! + \file drv_usbh_int.c + \brief USB host mode interrupt handler file + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 + \version 2021-07-26, V3.0.1, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_core.h" +#include "drv_usb_host.h" +#include "drv_usbh_int.h" +#include "usbh_core.h" + +#if defined (__CC_ARM) /*!< ARM compiler */ +#pragma O0 +#elif defined (__GNUC__) /*!< GNU compiler */ +#pragma GCC optimize ("O0") +#elif defined (__TASKING__) /*!< TASKING compiler */ +#pragma optimize=0 +#endif /* __CC_ARM */ + +/* local function prototypes ('static') */ +static uint32_t usbh_int_port(usb_core_driver *pudev); +static uint32_t usbh_int_pipe(usb_core_driver *pudev); +static uint32_t usbh_int_pipe_in(usb_core_driver *pudev, uint32_t pp_num); +static uint32_t usbh_int_pipe_out(usb_core_driver *pudev, uint32_t pp_num); +static uint32_t usbh_int_rxfifonoempty(usb_core_driver *pudev); +static uint32_t usbh_int_txfifoempty(usb_core_driver *pudev, usb_pipe_mode pp_mode); + +/*! + \brief handle global host interrupt + \param[in] pudev: pointer to USB core instance + \param[out] none + \retval operation status +*/ +uint32_t usbh_isr(usb_core_driver *pudev) +{ + uint32_t retval = 0U; + + __IO uint32_t intr = 0U; + + /* check if host mode */ + if(HOST_MODE == (pudev->regs.gr->GINTF & GINTF_COPM)) { + intr = usb_coreintr_get(&pudev->regs); + + if(!intr) { + return 0U; + } + + if(intr & GINTF_SOF) { + usbh_int_fop->SOF(pudev->host.data); + + /* clear interrupt */ + pudev->regs.gr->GINTF = GINTF_SOF; + } + + if(intr & GINTF_RXFNEIF) { + retval |= usbh_int_rxfifonoempty(pudev); + } + + if(intr & GINTF_NPTXFEIF) { + retval |= usbh_int_txfifoempty(pudev, PIPE_NON_PERIOD); + } + + if(intr & GINTF_PTXFEIF) { + retval |= usbh_int_txfifoempty(pudev, PIPE_PERIOD); + } + + if(intr & GINTF_HCIF) { + retval |= usbh_int_pipe(pudev); + } + + if(intr & GINTF_HPIF) { + retval |= usbh_int_port(pudev); + } + + if(intr & GINTF_DISCIF) { + usbh_int_fop->disconnect(pudev->host.data); + + /* clear interrupt */ + pudev->regs.gr->GINTF = GINTF_DISCIF; + } + + if(intr & GINTF_ISOONCIF) { + pudev->regs.pr[0]->HCHCTL |= HCHCTL_CEN | HCHCTL_CDIS; + + /* clear interrupt */ + pudev->regs.gr->GINTF = GINTF_ISOONCIF; + } + + if(intr & GINTF_SESIF) { + usb_portvbus_switch(pudev, 1U); + + pudev->regs.gr->GINTF = GINTF_SESIF; + } + + if(intr & GINTF_WKUPIF) { + /* clear interrupt */ + pudev->regs.gr->GINTF = GINTF_WKUPIF; + } + } + + return retval; +} + +/*! + \brief handle USB pipe halt + \param[in] pudev: pointer to USB core instance + \param[in] pp_num: pp_num: host channel number which is in (0..7) + \param[in] pp_int: pipe interrupt + \param[in] pp_status: pipe status + \param[out] none + \retval none +*/ +static inline void usb_pp_halt(usb_core_driver *pudev, + uint8_t pp_num, + uint32_t pp_int, + usb_pipe_staus pp_status) +{ + pudev->regs.pr[pp_num]->HCHINTEN |= HCHINTEN_CHIE; + + usb_pipe_halt(pudev, pp_num); + + pudev->regs.pr[pp_num]->HCHINTF = pp_int; + + pudev->host.pipe[pp_num].pp_status = pp_status; +} + +/*! + \brief handle the host port interrupt + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +#if defined (__ICCARM__) /*!< IAR compiler */ +#pragma optimize = none +#endif /* __ICCARM */ +static uint32_t usbh_int_port(usb_core_driver *pudev) +{ + uint32_t retval = 0U; + + /* note: when the USB PHY use USB HS PHY, the flag is needed */ + uint8_t port_reset = 0U; + + __IO uint32_t port_state = *pudev->regs.HPCS; + + /* clear the interrupt bits in GINTSTS */ + port_state &= ~(HPCS_PE | HPCS_PCD | HPCS_PEDC); + + /* port connect detected */ + if(*pudev->regs.HPCS & HPCS_PCD) { + port_state |= HPCS_PCD; + + usbh_int_fop->connect(pudev->host.data); + + retval |= 1U; + } + + /* port enable changed */ + if(*pudev->regs.HPCS & HPCS_PEDC) { + port_state |= HPCS_PEDC; + + if(*pudev->regs.HPCS & HPCS_PE) { + uint32_t port_speed = usb_curspeed_get(pudev); + uint32_t clock_type = pudev->regs.hr->HCTL & HCTL_CLKSEL; + + pudev->host.connect_status = 1U; + + if(PORT_SPEED_LOW == port_speed) { + pudev->regs.hr->HFT = 6000U; + + if(HCTL_6MHZ != clock_type) { + if(USB_EMBEDDED_PHY == pudev->bp.phy_itf) { + usb_phyclock_config(pudev, HCTL_6MHZ); + } + + port_reset = 1U; + } + } else if(PORT_SPEED_FULL == port_speed) { + pudev->regs.hr->HFT = 48000U; + + if(HCTL_48MHZ != clock_type) { + if(USB_EMBEDDED_PHY == pudev->bp.phy_itf) { + usb_phyclock_config(pudev, HCTL_48MHZ); + } + + port_reset = 1U; + } + } else { + /* for high speed device and others */ + port_reset = 1U; + } + + usbh_int_fop->port_enabled(pudev->host.data); + + pudev->regs.gr->GINTEN |= GINTEN_DISCIE | GINTEN_SOFIE; + } else { + usbh_int_fop->port_disabled(pudev->host.data); + } + } + + if(port_reset) { + usb_port_reset(pudev); + } + + /* clear port interrupts */ + *pudev->regs.HPCS = port_state; + + return retval; +} + +/*! + \brief handle all host channels interrupt + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +static uint32_t usbh_int_pipe(usb_core_driver *pudev) +{ + uint32_t pp_num = 0U; + uint32_t retval = 0U; + + for(pp_num = 0U; pp_num < pudev->bp.num_pipe; pp_num++) { + if((pudev->regs.hr->HACHINT & HACHINT_HACHINT) & (1UL << pp_num)) { + if(pudev->regs.pr[pp_num]->HCHCTL & HCHCTL_EPDIR) { + retval |= usbh_int_pipe_in(pudev, pp_num); + } else { + retval |= usbh_int_pipe_out(pudev, pp_num); + } + } + } + + return retval; +} + +/*! + \brief handle the IN channel interrupt + \param[in] pudev: pointer to USB device instance + \param[in] pp_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +#if defined (__ICCARM__) /*!< IAR compiler */ +#pragma optimize = none +#endif /* __ICCARM */ +static uint32_t usbh_int_pipe_in(usb_core_driver *pudev, uint32_t pp_num) +{ + usb_pr *pp_reg = pudev->regs.pr[pp_num]; + + usb_pipe *pp = &pudev->host.pipe[pp_num]; + + __IO uint32_t intr_pp = pp_reg->HCHINTF & pp_reg->HCHINTEN; + + uint8_t ep_type = (uint8_t)((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U); + + if(intr_pp & HCHINTF_ACK) { + pp_reg->HCHINTF = HCHINTF_ACK; + } else if(intr_pp & HCHINTF_STALL) { + usb_pp_halt(pudev, (uint8_t)pp_num, HCHINTF_STALL, PIPE_STALL); + pp_reg->HCHINTF = HCHINTF_NAK; + + /* note: When there is a 'STALL', reset also NAK, + else, the pudev->host.pp_status = HC_STALL + will be overwritten by 'NAK' in code below */ + intr_pp &= ~HCHINTF_NAK; + } else if(intr_pp & HCHINTF_DTER) { + usb_pp_halt(pudev, (uint8_t)pp_num, HCHINTF_DTER, PIPE_DTGERR); + pp_reg->HCHINTF = HCHINTF_NAK; + } else { + /* no operation */ + } + + if(intr_pp & HCHINTF_REQOVR) { + usb_pp_halt(pudev, (uint8_t)pp_num, HCHINTF_REQOVR, PIPE_REQOVR); + } else if(intr_pp & HCHINTF_TF) { + if((uint8_t)USB_USE_DMA == pudev->bp.transfer_mode) { + pudev->host.backup_xfercount[pp_num] = pp->xfer_len - (pp_reg->HCHLEN & HCHLEN_TLEN); + } + + pp->pp_status = PIPE_XF; + pp->err_count = 0U; + + pp_reg->HCHINTF = HCHINTF_TF; + + switch(ep_type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + usb_pp_halt(pudev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_XF); + + pp->data_toggle_in ^= 1U; + break; + + case USB_EPTYPE_INTR: + case USB_EPTYPE_ISOC: + pp_reg->HCHCTL |= HCHCTL_ODDFRM; + pp->urb_state = URB_DONE; + break; + + default: + break; + } + } else if(intr_pp & HCHINTF_CH) { + pp_reg->HCHINTEN &= ~HCHINTEN_CHIE; + + switch(pp->pp_status) { + case PIPE_XF: + pp->urb_state = URB_DONE; + break; + + case PIPE_STALL: + pp->urb_state = URB_STALL; + break; + + case PIPE_TRACERR: + case PIPE_DTGERR: + pp->err_count = 0U; + pp->urb_state = URB_ERROR; + + pp->data_toggle_in ^= 1U; + break; + + case PIPE_IDLE: + case PIPE_HALTED: + case PIPE_NAK: + case PIPE_NYET: + case PIPE_BBERR: + case PIPE_REQOVR: + default: + if((uint8_t)USB_EPTYPE_INTR == ep_type) { + pp->data_toggle_in ^= 1U; + } + break; + } + + pp_reg->HCHINTF = HCHINTF_CH; + } else if(intr_pp & HCHINTF_USBER) { + pp->err_count++; + usb_pp_halt(pudev, (uint8_t)pp_num, HCHINTF_USBER, PIPE_TRACERR); + } else if(intr_pp & HCHINTF_NAK) { + switch(ep_type) { + case USB_EPTYPE_CTRL: + case USB_EPTYPE_BULK: + /* re-activate the channel */ + pp_reg->HCHCTL = (pp_reg->HCHCTL | HCHCTL_CEN) & ~HCHCTL_CDIS; + break; + + case USB_EPTYPE_INTR: + pp_reg->HCHINTEN |= HCHINTEN_CHIE; + + (void)usb_pipe_halt(pudev, (uint8_t)pp_num); + break; + + default: + break; + } + + pp->pp_status = PIPE_NAK; + + pp_reg->HCHINTF = HCHINTF_NAK; + } else { + /* no operation */ + } + + return 1U; +} + +/*! + \brief handle the OUT channel interrupt + \param[in] pudev: pointer to USB device instance + \param[in] pp_num: host channel number which is in (0..7) + \param[out] none + \retval operation status +*/ +#if defined (__ICCARM__) /*!< IAR compiler */ +#pragma optimize = none +#endif /* __ICCARM */ +static uint32_t usbh_int_pipe_out(usb_core_driver *pudev, uint32_t pp_num) +{ + usb_pr *pp_reg = pudev->regs.pr[pp_num]; + + usb_pipe *pp = &pudev->host.pipe[pp_num]; + + uint32_t intr_pp = pp_reg->HCHINTF & pp_reg->HCHINTEN; + + if(intr_pp & HCHINTF_ACK) { + if(URB_PING == pp->urb_state) { + pp->err_count = 0U; + usb_pp_halt(pudev, (uint8_t)pp_num, HCHINTF_TF, PIPE_XF); + } + + pp_reg->HCHINTF = HCHINTF_ACK; + } else if(intr_pp & HCHINTF_STALL) { + usb_pp_halt(pudev, (uint8_t)pp_num, HCHINTF_STALL, PIPE_STALL); + } else if(intr_pp & HCHINTF_DTER) { + usb_pp_halt(pudev, (uint8_t)pp_num, HCHINTF_DTER, PIPE_DTGERR); + pp_reg->HCHINTF = HCHINTF_NAK; + } else if(intr_pp & HCHINTF_REQOVR) { + usb_pp_halt(pudev, (uint8_t)pp_num, HCHINTF_REQOVR, PIPE_REQOVR); + } else if(intr_pp & HCHINTF_TF) { + pp->err_count = 0U; + usb_pp_halt(pudev, (uint8_t)pp_num, HCHINTF_TF, PIPE_XF); + } else if(intr_pp & HCHINTF_NAK) { + pp->err_count = 0U; + usb_pp_halt(pudev, (uint8_t)pp_num, HCHINTF_NAK, PIPE_NAK); + } else if(intr_pp & HCHINTF_USBER) { + pp->err_count++; + usb_pp_halt(pudev, (uint8_t)pp_num, HCHINTF_USBER, PIPE_TRACERR); + } else if(intr_pp & HCHINTF_NYET) { + pp->err_count = 0U; + usb_pp_halt(pudev, (uint8_t)pp_num, HCHINTF_NYET, PIPE_NYET); + } else if(intr_pp & HCHINTF_CH) { + pudev->regs.pr[pp_num]->HCHINTEN &= ~HCHINTEN_CHIE; + + switch(pp->pp_status) { + case PIPE_XF: + pp->urb_state = URB_DONE; + + if((uint8_t)USB_EPTYPE_BULK == ((pp_reg->HCHCTL & HCHCTL_EPTYPE) >> 18U)) { + pp->data_toggle_out ^= 1U; + } + break; + + case PIPE_NAK: + + if(URB_PING == pp->urb_state) { + (void)usb_pipe_ping(pudev, (uint8_t)pp_num); + } else { + pp->urb_state = URB_NOTREADY; + } + break; + + case PIPE_NYET: + if(1U == pudev->host.pipe[pp_num].ping) { + (void)usb_pipe_ping(pudev, (uint8_t)pp_num); + pp->urb_state = URB_PING; + } else { + pp->urb_state = URB_NOTREADY; + } + break; + + case PIPE_STALL: + pp->urb_state = URB_STALL; + break; + + case PIPE_TRACERR: + if(3U == pp->err_count) { + pp->urb_state = URB_ERROR; + pp->err_count = 0U; + } + break; + + case PIPE_IDLE: + case PIPE_HALTED: + case PIPE_BBERR: + case PIPE_REQOVR: + case PIPE_DTGERR: + default: + break; + } + + pp_reg->HCHINTF = HCHINTF_CH; + } else { + /* no operation */ + } + + return 1U; +} + +/*! + \brief handle the RX FIFO non-empty interrupt + \param[in] pudev: pointer to USB device instance + \param[out] none + \retval operation status +*/ +#if defined (__ICCARM__) /*!< IAR compiler */ +#pragma optimize = none +#endif /* __ICCARM */ +static uint32_t usbh_int_rxfifonoempty(usb_core_driver *pudev) +{ + uint32_t count = 0U; + + __IO uint8_t pp_num = 0U; + __IO uint32_t rx_stat = 0U; + + /* disable the RX status queue level interrupt */ + pudev->regs.gr->GINTEN &= ~GINTEN_RXFNEIE; + + rx_stat = pudev->regs.gr->GRSTATP; + pp_num = (uint8_t)(rx_stat & GRSTATRP_CNUM); + + switch((rx_stat & GRSTATRP_RPCKST) >> 17U) { + case GRXSTS_PKTSTS_IN: + count = (rx_stat & GRSTATRP_BCOUNT) >> 4U; + + /* read the data into the host buffer. */ + if((count > 0U) && (NULL != pudev->host.pipe[pp_num].xfer_buf)) { + (void)usb_rxfifo_read(&pudev->regs, pudev->host.pipe[pp_num].xfer_buf, (uint16_t)count); + + /* manage multiple transfer packet */ + pudev->host.pipe[pp_num].xfer_buf += count; + pudev->host.pipe[pp_num].xfer_count += count; + + pudev->host.backup_xfercount[pp_num] = pudev->host.pipe[pp_num].xfer_count; + + if(pudev->regs.pr[pp_num]->HCHLEN & HCHLEN_PCNT) { + /* re-activate the channel when more packets are expected */ + __IO uint32_t pp_ctl = pudev->regs.pr[pp_num]->HCHCTL; + + pp_ctl |= HCHCTL_CEN; + pp_ctl &= ~HCHCTL_CDIS; + + pudev->regs.pr[pp_num]->HCHCTL = pp_ctl; + } + } + break; + + case GRXSTS_PKTSTS_IN_XFER_COMP: + break; + + case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: + count = (rx_stat & GRSTATRP_BCOUNT) >> 4U; + + while(count > 0U) { + rx_stat = pudev->regs.gr->GRSTATP; + count--; + } + break; + + case GRXSTS_PKTSTS_CH_HALTED: + break; + + default: + break; + } + + /* enable the RX status queue level interrupt */ + pudev->regs.gr->GINTEN |= GINTEN_RXFNEIE; + + return 1U; +} + +/*! + \brief handle the TX FIFO empty interrupt + \param[in] pudev: pointer to USB device instance + \param[in] pp_mode: pipe mode + \param[out] none + \retval operation status +*/ +#if defined (__ICCARM__) /*!< IAR compiler */ +#pragma optimize = none +#endif /* __ICCARM */ +static uint32_t usbh_int_txfifoempty(usb_core_driver *pudev, usb_pipe_mode pp_mode) +{ + uint8_t pp_num = 0U; + uint16_t word_count = 0U, len = 0U; + __IO uint32_t *txfiforeg = 0U, txfifostate = 0U; + + if(PIPE_NON_PERIOD == pp_mode) { + txfiforeg = &pudev->regs.gr->HNPTFQSTAT; + } else if(PIPE_PERIOD == pp_mode) { + txfiforeg = &pudev->regs.hr->HPTFQSTAT; + } else { + return 0U; + } + + txfifostate = *txfiforeg; + + pp_num = (uint8_t)((txfifostate & TFQSTAT_CNUM) >> 27U); + + word_count = (uint16_t)(pudev->host.pipe[pp_num].xfer_len + 3U) / 4U; + + while(((txfifostate & TFQSTAT_TXFS) >= word_count) && (0U != pudev->host.pipe[pp_num].xfer_len)) { + len = (uint16_t)(txfifostate & TFQSTAT_TXFS) * 4U; + + if(len > pudev->host.pipe[pp_num].xfer_len) { + /* last packet */ + len = (uint16_t)pudev->host.pipe[pp_num].xfer_len; + + if(PIPE_NON_PERIOD == pp_mode) { + pudev->regs.gr->GINTEN &= ~GINTEN_NPTXFEIE; + } else { + pudev->regs.gr->GINTEN &= ~GINTEN_PTXFEIE; + } + } + + word_count = (uint16_t)((pudev->host.pipe[pp_num].xfer_len + 3U) / 4U); + usb_txfifo_write(&pudev->regs, pudev->host.pipe[pp_num].xfer_buf, pp_num, len); + + pudev->host.pipe[pp_num].xfer_buf += len; + pudev->host.pipe[pp_num].xfer_len -= len; + pudev->host.pipe[pp_num].xfer_count += len; + + txfifostate = *txfiforeg; + } + + return 1U; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Include/usbh_hid_core.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Include/usbh_hid_core.h new file mode 100644 index 000000000..58c2df701 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Include/usbh_hid_core.h @@ -0,0 +1,205 @@ +/*! + \file usbh_hid_core.h + \brief header file for the usbh_hid_core.c + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_HID_CORE_H +#define __USBH_HID_CORE_H + +#include "usb_hid.h" +#include "usbh_enum.h" +#include "usbh_transc.h" + +#define HID_MIN_POLL 10U +#define HID_REPORT_SIZE 16U +#define HID_MAX_USAGE 10U +#define HID_MAX_NBR_REPORT_FMT 10U +#define HID_QUEUE_SIZE 10U + +#define HID_ITEM_LONG 0xFEU + +#define HID_ITEM_TYPE_MAIN 0x00U +#define HID_ITEM_TYPE_GLOBAL 0x01U +#define HID_ITEM_TYPE_LOCAL 0x02U +#define HID_ITEM_TYPE_RESERVED 0x03U + +#define HID_MAIN_ITEM_TAG_INPUT 0x08U +#define HID_MAIN_ITEM_TAG_OUTPUT 0x09U +#define HID_MAIN_ITEM_TAG_COLLECTION 0x0AU +#define HID_MAIN_ITEM_TAG_FEATURE 0x0BU +#define HID_MAIN_ITEM_TAG_ENDCOLLECTION 0x0CU + +#define HID_GLOBAL_ITEM_TAG_USAGE_PAGE 0x00U +#define HID_GLOBAL_ITEM_TAG_LOG_MIN 0x01U +#define HID_GLOBAL_ITEM_TAG_LOG_MAX 0x02U +#define HID_GLOBAL_ITEM_TAG_PHY_MIN 0x03U +#define HID_GLOBAL_ITEM_TAG_PHY_MAX 0x04U +#define HID_GLOBAL_ITEM_TAG_UNIT_EXPONENT 0x05U +#define HID_GLOBAL_ITEM_TAG_UNIT 0x06U +#define HID_GLOBAL_ITEM_TAG_REPORT_SIZE 0x07U +#define HID_GLOBAL_ITEM_TAG_REPORT_ID 0x08U +#define HID_GLOBAL_ITEM_TAG_REPORT_COUNT 0x09U +#define HID_GLOBAL_ITEM_TAG_PUSH 0x0AU +#define HID_GLOBAL_ITEM_TAG_POP 0x0BU + +#define HID_LOCAL_ITEM_TAG_USAGE 0x00U +#define HID_LOCAL_ITEM_TAG_USAGE_MIN 0x01U +#define HID_LOCAL_ITEM_TAG_USAGE_MAX 0x02U +#define HID_LOCAL_ITEM_TAG_DESIGNATOR_INDEX 0x03U +#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MIN 0x04U +#define HID_LOCAL_ITEM_TAG_DESIGNATOR_MAX 0x05U +#define HID_LOCAL_ITEM_TAG_STRING_INDEX 0x07U +#define HID_LOCAL_ITEM_TAG_STRING_MIN 0x08U +#define HID_LOCAL_ITEM_TAG_STRING_MAX 0x09U +#define HID_LOCAL_ITEM_TAG_DELIMITER 0x0AU + +#define USB_HID_DESC_SIZE 9U + +/* states for HID state machine */ +typedef enum { + HID_INIT = 0U, + HID_IDLE, + HID_SEND_DATA, + HID_BUSY, + HID_GET_DATA, + HID_SYNC, + HID_POLL, + HID_ERROR, +} hid_state; + +typedef enum { + HID_REQ_INIT = 0U, + HID_REQ_IDLE, + HID_REQ_GET_REPORT_DESC, + HID_REQ_GET_HID_DESC, + HID_REQ_SET_IDLE, + HID_REQ_SET_PROTOCOL, + HID_REQ_SET_REPORT, +} hid_ctlstate; + +typedef enum { + HID_MOUSE = 0x01U, + HID_KEYBOARD = 0x02U, + HID_UNKNOWN = 0xFFU, +} hid_type; + +typedef struct _hid_report_data { + uint8_t ReportID; + uint8_t ReportType; + uint16_t UsagePage; + uint32_t Usage[HID_MAX_USAGE]; + uint32_t NbrUsage; + uint32_t UsageMin; + uint32_t UsageMax; + int32_t LogMin; + int32_t LogMax; + int32_t PhyMin; + int32_t PhyMax; + int32_t UnitExp; + uint32_t Unit; + uint32_t ReportSize; + uint32_t ReportCnt; + uint32_t Flag; + uint32_t PhyUsage; + uint32_t AppUsage; + uint32_t LogUsage; +} hid_report_data; + +typedef struct _hid_report_ID { + uint8_t size; /*!< report size return by the device ID */ + uint8_t reportID; /*!< report ID */ + uint8_t type; /*!< report type (INPUT/OUTPUT/FEATURE) */ +} hid_report_ID; + +typedef struct _hid_collection { + uint32_t usage; + uint8_t type; + struct _hid_collection *next_ptr; +} hid_collection; + +typedef struct _hid_appcollection { + uint32_t usage; + uint8_t type; + uint8_t nbr_report_fmt; + hid_report_data report_data[HID_MAX_NBR_REPORT_FMT]; +} hid_appcollection; + +typedef struct { + uint8_t *buf; + uint16_t head; + uint16_t tail; + uint16_t size; + uint8_t lock; +} data_fifo; + +/* structure for HID process */ +typedef struct _hid_process { + uint8_t pipe_in; + uint8_t pipe_out; + uint8_t ep_addr; + uint8_t ep_in; + uint8_t ep_out; + __IO uint8_t data_ready; + uint8_t *pdata; + uint16_t len; + uint16_t poll; + + __IO uint32_t timer; + + data_fifo fifo; + usb_desc_hid hid_desc; + hid_report_data hid_report; + + hid_state state; + hid_ctlstate ctl_state; + usbh_status(*init)(usb_core_driver *pudev, usbh_host *puhost); + void (*machine)(usb_core_driver *pudev, usbh_host *puhost); +} usbh_hid_handler; + +extern usbh_class usbh_hid; + +/* function declarations */ +/* set HID report */ +usbh_status usbh_set_report(usb_core_driver *pudev, + usbh_host *puhost, + uint8_t report_type, + uint8_t report_ID, + uint8_t report_len, + uint8_t *report_buf); +/* read data from FIFO */ +uint16_t usbh_hid_fifo_read(data_fifo *fifo, void *buf, uint16_t nbytes); +/* write data to FIFO */ +uint16_t usbh_hid_fifo_write(data_fifo *fifo, void *buf, uint16_t nbytes); +/* initialize FIFO */ +void usbh_hid_fifo_init(data_fifo *fifo, uint8_t *buf, uint16_t size); + +#endif /* __USBH_HID_CORE_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Include/usbh_hid_keybd.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Include/usbh_hid_keybd.h new file mode 100644 index 000000000..002312ec2 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Include/usbh_hid_keybd.h @@ -0,0 +1,302 @@ +/*! + \file usbh_hid_keybd.h + \brief header file for usbh_hid_keybd.c + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_HID_KEYBD_H +#define __USBH_HID_KEYBD_H + +#include "usb_conf.h" +#include "usbh_hid_core.h" + +//#define AZERTY_KEYBOARD +#define QWERTY_KEYBOARD + +#define KBD_LEFT_CTRL 0x01U +#define KBD_LEFT_SHIFT 0x02U +#define KBD_LEFT_ALT 0x04U +#define KBD_LEFT_GUI 0x08U +#define KBD_RIGHT_CTRL 0x10U +#define KBD_RIGHT_SHIFT 0x20U +#define KBD_RIGHT_ALT 0x40U +#define KBD_RIGHT_GUI 0x80U + +#define KEY_NONE 0x00U +#define KEY_ERRORROLLOVER 0x01U +#define KEY_POSTFAIL 0x02U +#define KEY_ERRORUNDEFINED 0x03U +#define KEY_A 0x04U +#define KEY_B 0x05U +#define KEY_C 0x06U +#define KEY_D 0x07U +#define KEY_E 0x08U +#define KEY_F 0x09U +#define KEY_G 0x0AU +#define KEY_H 0x0BU +#define KEY_I 0x0CU +#define KEY_J 0x0DU +#define KEY_K 0x0EU +#define KEY_L 0x0FU +#define KEY_M 0x10U +#define KEY_N 0x11U +#define KEY_O 0x12U +#define KEY_P 0x13U +#define KEY_Q 0x14U +#define KEY_R 0x15U +#define KEY_S 0x16U +#define KEY_T 0x17U +#define KEY_U 0x18U +#define KEY_V 0x19U +#define KEY_W 0x1AU +#define KEY_X 0x1BU +#define KEY_Y 0x1CU +#define KEY_Z 0x1DU +#define KEY_1_EXCLAMATION_MARK 0x1EU +#define KEY_2_AT 0x1FU +#define KEY_3_NUMBER_SIGN 0x20U +#define KEY_4_DOLLAR 0x21U +#define KEY_5_PERCENT 0x22U +#define KEY_6_CARET 0x23U +#define KEY_7_AMPERSAND 0x24U +#define KEY_8_ASTERISK 0x25U +#define KEY_9_OPARENTHESIS 0x26U +#define KEY_0_CPARENTHESIS 0x27U +#define KEY_ENTER 0x28U +#define KEY_ESCAPE 0x29U +#define KEY_BACKSPACE 0x2AU +#define KEY_TAB 0x2BU +#define KEY_SPACEBAR 0x2CU +#define KEY_MINUS_UNDERSCORE 0x2DU +#define KEY_EQUAL_PLUS 0x2EU +#define KEY_OBRACKET_AND_OBRACE 0x2FU +#define KEY_CBRACKET_AND_CBRACE 0x30U +#define KEY_BACKSLASH_VERTICAL_BAR 0x31U +#define KEY_NONUS_NUMBER_SIGN_TILDE 0x32U +#define KEY_SEMICOLON_COLON 0x33U +#define KEY_SINGLE_AND_DOUBLE_QUOTE 0x34U +#define KEY_GRAVE ACCENT AND TILDE 0x35U +#define KEY_COMMA_AND_LESS 0x36U +#define KEY_DOT_GREATER 0x37U +#define KEY_SLASH_QUESTION 0x38U +#define KEY_CAPS LOCK 0x39U +#define KEY_F1 0x3AU +#define KEY_F2 0x3BU +#define KEY_F3 0x3CU +#define KEY_F4 0x3DU +#define KEY_F5 0x3EU +#define KEY_F6 0x3FU +#define KEY_F7 0x40U +#define KEY_F8 0x41U +#define KEY_F9 0x42U +#define KEY_F10 0x43U +#define KEY_F11 0x44U +#define KEY_F12 0x45U +#define KEY_PRINTSCREEN 0x46U +#define KEY_SCROLL LOCK 0x47U +#define KEY_PAUSE 0x48U +#define KEY_INSERT 0x49U +#define KEY_HOME 0x4AU +#define KEY_PAGEUP 0x4BU +#define KEY_DELETE 0x4CU +#define KEY_END1 0x4DU +#define KEY_PAGEDOWN 0x4EU +#define KEY_RIGHTARROW 0x4FU +#define KEY_LEFTARROW 0x50U +#define KEY_DOWNARROW 0x51U +#define KEY_UPARROW 0x52U +#define KEY_KEYPAD_NUM_LOCK_AND_CLEAR 0x53U +#define KEY_KEYPAD_SLASH 0x54U +#define KEY_KEYPAD_ASTERIKS 0x55U +#define KEY_KEYPAD_MINUS 0x56U +#define KEY_KEYPAD_PLUS 0x57U +#define KEY_KEYPAD_ENTER 0x58U +#define KEY_KEYPAD_1_END 0x59U +#define KEY_KEYPAD_2_DOWN_ARROW 0x5AU +#define KEY_KEYPAD_3_PAGEDN 0x5BU +#define KEY_KEYPAD_4_LEFT_ARROW 0x5CU +#define KEY_KEYPAD_5 0x5DU +#define KEY_KEYPAD_6_RIGHT_ARROW 0x5EU +#define KEY_KEYPAD_7_HOME 0x5FU +#define KEY_KEYPAD_8_UP_ARROW 0x60U +#define KEY_KEYPAD_9_PAGEUP 0x61U +#define KEY_KEYPAD_0_INSERT 0x62U +#define KEY_KEYPAD_DECIMAL_SEPARATOR_DELETE 0x63U +#define KEY_NONUS_BACK_SLASH_VERTICAL_BAR 0x64U +#define KEY_APPLICATION 0x65U +#define KEY_POWER 0x66U +#define KEY_KEYPAD_EQUAL 0x67U +#define KEY_F13 0x68U +#define KEY_F14 0x69U +#define KEY_F15 0x6AU +#define KEY_F16 0x6BU +#define KEY_F17 0x6CU +#define KEY_F18 0x6DU +#define KEY_F19 0x6EU +#define KEY_F20 0x6FU +#define KEY_F21 0x70U +#define KEY_F22 0x71U +#define KEY_F23 0x72U +#define KEY_F24 0x73U +#define KEY_EXECUTE 0x74U +#define KEY_HELP 0x75U +#define KEY_MENU 0x76U +#define KEY_SELECT 0x77U +#define KEY_STOP 0x78U +#define KEY_AGAIN 0x79U +#define KEY_UNDO 0x7AU +#define KEY_CUT 0x7BU +#define KEY_COPY 0x7CU +#define KEY_PASTE 0x7DU +#define KEY_FIND 0x7EU +#define KEY_MUTE 0x7FU +#define KEY_VOLUME_UP 0x80U +#define KEY_VOLUME_DOWN 0x81U +#define KEY_LOCKING_CAPS_LOCK 0x82U +#define KEY_LOCKING_NUM_LOCK 0x83U +#define KEY_LOCKING_SCROLL_LOCK 0x84U +#define KEY_KEYPAD_COMMA 0x85U +#define KEY_KEYPAD_EQUAL_SIGN 0x86U +#define KEY_INTERNATIONAL1 0x87U +#define KEY_INTERNATIONAL2 0x88U +#define KEY_INTERNATIONAL3 0x89U +#define KEY_INTERNATIONAL4 0x8AU +#define KEY_INTERNATIONAL5 0x8BU +#define KEY_INTERNATIONAL6 0x8CU +#define KEY_INTERNATIONAL7 0x8DU +#define KEY_INTERNATIONAL8 0x8EU +#define KEY_INTERNATIONAL9 0x8FU +#define KEY_LANG1 0x90U +#define KEY_LANG2 0x91U +#define KEY_LANG3 0x92U +#define KEY_LANG4 0x93U +#define KEY_LANG5 0x94U +#define KEY_LANG6 0x95U +#define KEY_LANG7 0x96U +#define KEY_LANG8 0x97U +#define KEY_LANG9 0x98U +#define KEY_ALTERNATE_ERASE 0x99U +#define KEY_SYSREQ 0x9AU +#define KEY_CANCEL 0x9BU +#define KEY_CLEAR 0x9CU +#define KEY_PRIOR 0x9DU +#define KEY_RETURN 0x9EU +#define KEY_SEPARATOR 0x9FU +#define KEY_OUT 0xA0U +#define KEY_OPER 0xA1U +#define KEY_CLEAR_AGAIN 0xA2U +#define KEY_CRSEL 0xA3U +#define KEY_EXSEL 0xA4U +#define KEY_KEYPAD_00 0xB0U +#define KEY_KEYPAD_000 0xB1U +#define KEY_THOUSANDS_SEPARATOR 0xB2U +#define KEY_DECIMAL_SEPARATOR 0xB3U +#define KEY_CURRENCY_UNIT 0xB4U +#define KEY_CURRENCY_SUB_UNIT 0xB5U +#define KEY_KEYPAD_OPARENTHESIS 0xB6U +#define KEY_KEYPAD_CPARENTHESIS 0xB7U +#define KEY_KEYPAD_OBRACE 0xB8U +#define KEY_KEYPAD_CBRACE 0xB9U +#define KEY_KEYPAD_TAB 0xBAU +#define KEY_KEYPAD_BACKSPACE 0xBBU +#define KEY_KEYPAD_A 0xBCU +#define KEY_KEYPAD_B 0xBDU +#define KEY_KEYPAD_C 0xBEU +#define KEY_KEYPAD_D 0xBFU +#define KEY_KEYPAD_E 0xC0U +#define KEY_KEYPAD_F 0xC1U +#define KEY_KEYPAD_XOR 0xC2U +#define KEY_KEYPAD_CARET 0xC3U +#define KEY_KEYPAD_PERCENT 0xC4U +#define KEY_KEYPAD_LESS 0xC5U +#define KEY_KEYPAD_GREATER 0xC6U +#define KEY_KEYPAD_AMPERSAND 0xC7U +#define KEY_KEYPAD_LOGICAL_AND 0xC8U +#define KEY_KEYPAD_VERTICAL_BAR 0xC9U +#define KEY_KEYPAD_LOGIACL_OR 0xCAU +#define KEY_KEYPAD_COLON 0xCBU +#define KEY_KEYPAD_NUMBER_SIGN 0xCCU +#define KEY_KEYPAD_SPACE 0xCDU +#define KEY_KEYPAD_AT 0xCEU +#define KEY_KEYPAD_EXCLAMATION_MARK 0xCFU +#define KEY_KEYPAD_MEMORY_STORE 0xD0U +#define KEY_KEYPAD_MEMORY_RECALL 0xD1U +#define KEY_KEYPAD_MEMORY_CLEAR 0xD2U +#define KEY_KEYPAD_MEMORY_ADD 0xD3U +#define KEY_KEYPAD_MEMORY_SUBTRACT 0xD4U +#define KEY_KEYPAD_MEMORY_MULTIPLY 0xD5U +#define KEY_KEYPAD_MEMORY_DIVIDE 0xD6U +#define KEY_KEYPAD_PLUSMINUS 0xD7U +#define KEY_KEYPAD_CLEAR 0xD8U +#define KEY_KEYPAD_CLEAR_ENTRY 0xD9U +#define KEY_KEYPAD_BINARY 0xDAU +#define KEY_KEYPAD_OCTAL 0xDBU +#define KEY_KEYPAD_DECIMAL 0xDCU +#define KEY_KEYPAD_HEXADECIMAL 0xDDU +#define KEY_LEFTCONTROL 0xE0U +#define KEY_LEFTSHIFT 0xE1U +#define KEY_LEFTALT 0xE2U +#define KEY_LEFT_GUI 0xE3U +#define KEY_RIGHTCONTROL 0xE4U +#define KEY_RIGHTSHIFT 0xE5U +#define KEY_RIGHTALT 0xE6U +#define KEY_RIGHT_GUI 0xE7U + +#define KBR_MAX_NBR_PRESSED 6U + +typedef struct { + uint8_t state; + uint8_t lctrl; + uint8_t lshift; + uint8_t lalt; + uint8_t lgui; + uint8_t rctrl; + uint8_t rshift; + uint8_t ralt; + uint8_t rgui; + uint8_t keys[6]; +} hid_keybd_info; + +/* function declarations */ +/* initialize keyboard */ +void usr_keybrd_init(void); +/* process keyboard data */ +void usr_keybrd_process_data(uint8_t pbuf); +/* initialize the keyboard function */ +usbh_status usbh_hid_keybd_init(usb_core_driver *pudev, usbh_host *puhost); +/* get keyboard information */ +hid_keybd_info *usbh_hid_keybd_info_get(usb_core_driver *pudev, usbh_host *puhost); +/* get the ascii code of hid */ +uint8_t usbh_hid_ascii_code_get(hid_keybd_info *info); +/* keyboard machine */ +void usbh_hid_keybrd_machine(usb_core_driver *pudev, usbh_host *puhost); + +#endif /* __USBH_HID_KEYBD_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Include/usbh_hid_mouse.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Include/usbh_hid_mouse.h new file mode 100644 index 000000000..bbb16824e --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Include/usbh_hid_mouse.h @@ -0,0 +1,58 @@ +/*! + \file usbh_hid_mouse.h + \brief header file for the usbh_hid_mouse.c + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_HID_MOUSE_H +#define __USBH_HID_MOUSE_H + +#include "usbh_hid_core.h" + +typedef struct _hid_mouse_info { + uint8_t x; + uint8_t y; + uint8_t buttons[3]; +} hid_mouse_info; + +/* function declarations */ +/* initialize mouse */ +void usr_mouse_init(void); +/* process mouse data */ +void usr_mouse_process_data(hid_mouse_info *data); +/* initialize mouse function */ +usbh_status usbh_hid_mouse_init(usb_core_driver *pudev, usbh_host *puhost); +/* get mouse information */ +hid_mouse_info *usbh_hid_mouse_info_get(usb_core_driver *pudev, usbh_host *puhost); +/* mouse machine */ +void usbh_hid_mouse_machine(usb_core_driver *pudev, usbh_host *puhost); + +#endif /* __USBH_HID_MOUSE_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Include/usbh_hid_parser.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Include/usbh_hid_parser.h new file mode 100644 index 000000000..ba950e4bd --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Include/usbh_hid_parser.h @@ -0,0 +1,60 @@ +/*! + \file usbh_hid_core.h + \brief header file for the usbh_hid_core.c + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_HID_PARSER_H +#define __USBH_HID_PARSER_H + +#include "usbh_hid_core.h" +#include "usbh_hid_usage.h" + +typedef struct { + uint8_t *data; + uint32_t size; + uint8_t shift; + uint8_t count; + uint8_t sign; + uint32_t logical_min; /*min value device can return*/ + uint32_t logical_max; /*max value device can return*/ + uint32_t physical_min; /*min vale read can report*/ + uint32_t physical_max; /*max value read can report*/ + uint32_t resolution; +} hid_report_item; + +/* function declarations */ +/* read a hid report item */ +uint32_t hid_item_read(hid_report_item *ri, uint8_t ndx); +/* write a hid report item */ +uint32_t hid_item_write(hid_report_item *ri, uint32_t value, uint8_t ndx); + +#endif /* __USBH_HID_PARSER_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Include/usbh_hid_usage.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Include/usbh_hid_usage.h new file mode 100644 index 000000000..f2c3029a7 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Include/usbh_hid_usage.h @@ -0,0 +1,141 @@ +/*! + \file usbh_hid_core.h + \brief header file for the usbh_hid_core.c + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USDH_HID_USAGE_H +#define __USDH_HID_USAGE_H + +/* HID 1.11 usage pages */ +#define HID_USAGE_PAGE_UNDEFINED uint16_t (0x00) /* Undefined */ + +/* top level pages */ +#define HID_USAGE_PAGE_GEN_DES uint16_t (0x01) /* Generic Desktop Controls*/ +#define HID_USAGE_PAGE_SIM_CTR uint16_t (0x02) /* Simulation Controls */ +#define HID_USAGE_PAGE_VR_CTR uint16_t (0x03) /* VR Controls */ +#define HID_USAGE_PAGE_SPORT_CTR uint16_t (0x04) /* Sport Controls */ +#define HID_USAGE_PAGE_GAME_CTR uint16_t (0x05) /* Game Controls */ +#define HID_USAGE_PAGE_GEN_DEV uint16_t (0x06) /* Generic Device Controls */ +#define HID_USAGE_PAGE_KEYB uint16_t (0x07) /* Keyboard/Keypad */ +#define HID_USAGE_PAGE_LED uint16_t (0x08) /* LEDs */ +#define HID_USAGE_PAGE_BUTTON uint16_t (0x09) /* Button */ +#define HID_USAGE_PAGE_ORDINAL uint16_t (0x0A) /* Ordinal */ +#define HID_USAGE_PAGE_PHONE uint16_t (0x0B) /* Telephony */ +#define HID_USAGE_PAGE_CONSUMER uint16_t (0x0C) /* Consumer */ +#define HID_USAGE_PAGE_DIGITIZER uint16_t (0x0D) /* Digitizer*/ +#define HID_USAGE_PAGE_PID uint16_t (0x0F) /* PID Page (force feedback and related devices) */ +#define HID_USAGE_PAGE_UNICODE uint16_t (0x10) /* Unicode */ +#define HID_USAGE_PAGE_ALNUM_DISP uint16_t (0x14) /* Alphanumeric Display */ +/* end of top level pages */ + +#define HID_USAGE_PAGE_MEDICAL uint16_t (0x40) /* Medical Instruments */ + +/* 80-83 Monitor pages USB Device Class Definition for Monitor Devices */ +/* 84-87 Power pages USB Device Class Definition for Power Devices */ +#define HID_USAGE_PAGE_BARCODE uint16_t (0x8C) /* Bar Code Scanner page */ +#define HID_USAGE_PAGE_SCALE uint16_t (0x8D) /* Scale page */ +#define HID_USAGE_PAGE_MSR uint16_t (0x8E) /* Magnetic Stripe Reading (MSR) Devices */ +#define HID_USAGE_PAGE_POS uint16_t (0x8F) /* Reserved Point of Sale pages */ +#define HID_USAGE_PAGE_CAMERA_CTR uint16_t (0x90) /* Camera Control Page */ +#define HID_USAGE_PAGE_ARCADE uint16_t (0x91) /* Arcade Page */ + +/* usage definitions for the "generic desktop" page */ +#define HID_USAGE_UNDEFINED uint16_t (0x00) /* Undefined */ +#define HID_USAGE_POINTER uint16_t (0x01) /* Pointer (Physical Collection) */ +#define HID_USAGE_MOUSE uint16_t (0x02) /* Mouse (Application Collection) */ +#define HID_USAGE_JOYSTICK uint16_t (0x04) /* Joystick (Application Collection) */ +#define HID_USAGE_GAMEPAD uint16_t (0x05) /* Game Pad (Application Collection) */ +#define HID_USAGE_KBD uint16_t (0x06) /* Keyboard (Application Collection) */ +#define HID_USAGE_KEYPAD uint16_t (0x07) /* Keypad (Application Collection) */ +#define HID_USAGE_MAX_CTR uint16_t (0x08) /* Multi-axis Controller (Application Collection) */ +#define HID_USAGE_X uint16_t (0x30) /* X (Dynamic Value) */ +#define HID_USAGE_Y uint16_t (0x31) /* Y (Dynamic Value) */ +#define HID_USAGE_Z uint16_t (0x32) /* Z (Dynamic Value) */ +#define HID_USAGE_RX uint16_t (0x33) /* Rx (Dynamic Value) */ +#define HID_USAGE_RY uint16_t (0x34) /* Ry (Dynamic Value) */ +#define HID_USAGE_RZ uint16_t (0x35) /* Rz (Dynamic Value) */ +#define HID_USAGE_SLIDER uint16_t (0x36) /* Slider (Dynamic Value) */ +#define HID_USAGE_DIAL uint16_t (0x37) /* Dial (Dynamic Value) */ +#define HID_USAGE_WHEEL uint16_t (0x38) /* Wheel (Dynamic Value) */ +#define HID_USAGE_HATSW uint16_t (0x39) /* Hat switch (Dynamic Value) */ +#define HID_USAGE_COUNTEDBUF uint16_t (0x3A) /* Counted Buffer (Logical Collection) */ +#define HID_USAGE_BYTECOUNT uint16_t (0x3B) /* Byte Count (Dynamic Value) */ +#define HID_USAGE_MOTIONWAKE uint16_t (0x3C) /* Motion Wakeup (One Shot Control) */ +#define HID_USAGE_START uint16_t (0x3D) /* Start (On/Off Control) */ +#define HID_USAGE_SELECT uint16_t (0x3E) /* Select (On/Off Control) */ +#define HID_USAGE_VX uint16_t (0x40) /* Vx (Dynamic Value) */ +#define HID_USAGE_VY uint16_t (0x41) /* Vy (Dynamic Value) */ +#define HID_USAGE_VZ uint16_t (0x42) /* Vz (Dynamic Value) */ +#define HID_USAGE_VBRX uint16_t (0x43) /* Vbrx (Dynamic Value) */ +#define HID_USAGE_VBRY uint16_t (0x44) /* Vbry (Dynamic Value) */ +#define HID_USAGE_VBRZ uint16_t (0x45) /* Vbrz (Dynamic Value) */ +#define HID_USAGE_VNO uint16_t (0x46) /* Vno (Dynamic Value) */ +#define HID_USAGE_FEATNOTIF uint16_t (0x47) /* Feature Notification (Dynamic Value),(Dynamic Flag) */ +#define HID_USAGE_SYSCTL uint16_t (0x80) /* System Control (Application Collection) */ +#define HID_USAGE_PWDOWN uint16_t (0x81) /* System Power Down (One Shot Control) */ +#define HID_USAGE_SLEEP uint16_t (0x82) /* System Sleep (One Shot Control) */ +#define HID_USAGE_WAKEUP uint16_t (0x83) /* System Wake Up (One Shot Control) */ +#define HID_USAGE_CONTEXTM uint16_t (0x84) /* System Context Menu (One Shot Control) */ +#define HID_USAGE_MAINM uint16_t (0x85) /* System Main Menu (One Shot Control) */ +#define HID_USAGE_APPM uint16_t (0x86) /* System App Menu (One Shot Control) */ +#define HID_USAGE_MENUHELP uint16_t (0x87) /* System Menu Help (One Shot Control) */ +#define HID_USAGE_MENUEXIT uint16_t (0x88) /* System Menu Exit (One Shot Control) */ +#define HID_USAGE_MENUSELECT uint16_t (0x89) /* System Menu Select (One Shot Control) */ +#define HID_USAGE_SYSM_RIGHT uint16_t (0x8A) /* System Menu Right (Re-Trigger Control) */ +#define HID_USAGE_SYSM_LEFT uint16_t (0x8B) /* System Menu Left (Re-Trigger Control) */ +#define HID_USAGE_SYSM_UP uint16_t (0x8C) /* System Menu Up (Re-Trigger Control) */ +#define HID_USAGE_SYSM_DOWN uint16_t (0x8D) /* System Menu Down (Re-Trigger Control) */ +#define HID_USAGE_COLDRESET uint16_t (0x8E) /* System Cold Restart (One Shot Control) */ +#define HID_USAGE_WARMRESET uint16_t (0x8F) /* System Warm Restart (One Shot Control) */ +#define HID_USAGE_DUP uint16_t (0x90) /* D-pad Up (On/Off Control) */ +#define HID_USAGE_DDOWN uint16_t (0x91) /* D-pad Down (On/Off Control) */ +#define HID_USAGE_DRIGHT uint16_t (0x92) /* D-pad Right (On/Off Control) */ +#define HID_USAGE_DLEFT uint16_t (0x93) /* D-pad Left (On/Off Control) */ +#define HID_USAGE_SYS_DOCK uint16_t (0xA0) /* System Dock (One Shot Control) */ +#define HID_USAGE_SYS_UNDOCK uint16_t (0xA1) /* System Undock (One Shot Control) */ +#define HID_USAGE_SYS_SETUP uint16_t (0xA2) /* System Setup (One Shot Control) */ +#define HID_USAGE_SYS_BREAK uint16_t (0xA3) /* System Break (One Shot Control) */ +#define HID_USAGE_SYS_DBGBRK uint16_t (0xA4) /* System Debugger Break (One Shot Control) */ +#define HID_USAGE_APP_BRK uint16_t (0xA5) /* Application Break (One Shot Control) */ +#define HID_USAGE_APP_DBGBRK uint16_t (0xA6) /* Application Debugger Break (One Shot Control) */ +#define HID_USAGE_SYS_SPKMUTE uint16_t (0xA7) /* System Speaker Mute (One Shot Control) */ +#define HID_USAGE_SYS_HIBERN uint16_t (0xA8) /* System Hibernate (One Shot Control) */ +#define HID_USAGE_SYS_SIDPINV uint16_t (0xB0) /* System Display Invert (One Shot Control) */ +#define HID_USAGE_SYS_DISPINT uint16_t (0xB1) /* System Display Internal (One Shot Control) */ +#define HID_USAGE_SYS_DISPEXT uint16_t (0xB2) /* System Display External (One Shot Control) */ +#define HID_USAGE_SYS_DISPBOTH uint16_t (0xB3) /* System Display Both (One Shot Control) */ +#define HID_USAGE_SYS_DISPDUAL uint16_t (0xB4) /* System Display Dual (One Shot Control) */ +#define HID_USAGE_SYS_DISPTGLIE uint16_t (0xB5) /* System Display Toggle Int/Ext (One Shot Control) */ +#define HID_USAGE_SYS_DISP_SWAP uint16_t (0xB6) /* System Display Swap Primary/Secondary (One Shot Control) */ +#define HID_USAGE_SYS_DIPS_LCDA uint16_t (0xB7) /* System Display LCD Autoscale (One Shot Control) */ + +#endif /* __USDH_HID_USAGE_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Source/usbh_hid_core.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Source/usbh_hid_core.c new file mode 100644 index 000000000..0cd3288db --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Source/usbh_hid_core.c @@ -0,0 +1,674 @@ +/*! + \file usbh_hid_core.c + \brief USB host HID class driver + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_pipe.h" +#include "usbh_hid_core.h" +#include "usbh_hid_mouse.h" +#include "usbh_hid_keybd.h" +#include +#include + +/* local function prototypes ('static') */ +static void usbh_hiddesc_parse(usb_desc_hid *hid_desc, uint8_t *buf); +static void usbh_hid_itf_deinit(usbh_host *puhost); +static usbh_status usbh_hid_itf_init(usbh_host *puhost); +static usbh_status usbh_hid_class_req(usbh_host *puhost); +static usbh_status usbh_hid_handle(usbh_host *puhost); +static usbh_status usbh_hid_reportdesc_get(usbh_host *puhost, uint16_t len); +static usbh_status usbh_hid_sof(usbh_host *puhost); +static usbh_status usbh_hid_desc_get(usbh_host *puhost, uint16_t len); +static usbh_status usbh_set_idle(usbh_host *puhost, uint8_t duration, uint8_t report_ID); +static usbh_status usbh_set_protocol(usbh_host *puhost, uint8_t protocol); + +usbh_class usbh_hid = { + USB_HID_CLASS, + usbh_hid_itf_init, + usbh_hid_itf_deinit, + usbh_hid_class_req, + usbh_hid_handle, + usbh_hid_sof +}; + +/*! + \brief get report + \param[in] puhost: pointer to usb host + \param[in] report_type: duration for HID set idle request + \param[in] report_ID: targeted report ID for HID set idle request + \param[in] report_len: length of data report to be send + \param[in] report_buf: report buffer + \param[out] none + \retval operation status +*/ +usbh_status usbh_get_report(usbh_host *puhost, + uint8_t report_type, + uint8_t report_ID, + uint8_t report_len, + uint8_t *report_buf) +{ + usbh_status status = USBH_BUSY; + + if(CTL_IDLE == puhost->control.ctl_state) { + puhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS, + .bRequest = GET_REPORT, + .wValue = (report_type << 8U) | report_ID, + .wIndex = 0U, + .wLength = report_len + }; + + usbh_ctlstate_config(puhost, report_buf, report_len); + } + + status = usbh_ctl_handler(puhost); + + return status; +} + +/*! + \brief set report + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[in] report_type: duration for HID set idle request + \param[in] report_ID: targeted report ID for HID set idle request + \param[in] report_len: length of data report to be send + \param[in] report_buf: report buffer + \param[out] none + \retval operation status +*/ +usbh_status usbh_set_report(usb_core_driver *pudev, + usbh_host *puhost, + uint8_t report_type, + uint8_t report_ID, + uint8_t report_len, + uint8_t *report_buf) +{ + usbh_status status = USBH_BUSY; + + if(CTL_IDLE == puhost->control.ctl_state) { + puhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS, + .bRequest = SET_REPORT, + .wValue = (report_type << 8U) | report_ID, + .wIndex = 0U, + .wLength = report_len + }; + + usbh_ctlstate_config(puhost, report_buf, report_len); + } + + status = usbh_ctl_handler(puhost); + + return status; +} + +/*! + \brief de-initialize the host pipes used for the HID class + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +void usbh_hid_itf_deinit(usbh_host *puhost) +{ + usbh_hid_handler *hid = (usbh_hid_handler *)puhost->active_class->class_data; + + if(0x00U != hid->pipe_in) { + usb_pipe_halt(puhost->data, hid->pipe_in); + + usbh_pipe_free(puhost->data, hid->pipe_in); + + hid->pipe_in = 0U; /* reset the pipe as free */ + } + + if(0x00U != hid->pipe_out) { + usb_pipe_halt(puhost->data, hid->pipe_out); + + usbh_pipe_free(puhost->data, hid->pipe_out); + + hid->pipe_out = 0U; /* reset the channel as free */ + } +} + +/*! + \brief return device type + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval hid_type +*/ +hid_type usbh_hid_device_type_get(usb_core_driver *pudev, usbh_host *puhost) +{ + hid_type type = HID_UNKNOWN; + uint8_t interface_protocol; + + if(HOST_CLASS_HANDLER == puhost->cur_state) { + interface_protocol = puhost->dev_prop.cfg_desc_set.itf_desc_set[puhost->dev_prop.cur_itf][0].itf_desc.bInterfaceProtocol; + + if(USB_HID_PROTOCOL_KEYBOARD == interface_protocol) { + type = HID_KEYBOARD; + } else { + if(USB_HID_PROTOCOL_MOUSE == interface_protocol) { + type = HID_MOUSE; + } + } + } + + return type; +} + +/*! + \brief return HID device poll time + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval poll time (ms) +*/ +uint8_t usbh_hid_poll_interval_get(usb_core_driver *pudev, usbh_host *puhost) +{ + usbh_hid_handler *hid = (usbh_hid_handler *)puhost->active_class->class_data; + + if((HOST_CLASS_ENUM == puhost->cur_state) || + (HOST_USER_INPUT == puhost->cur_state) || + (HOST_CHECK_CLASS == puhost->cur_state) || + (HOST_CLASS_HANDLER == puhost->cur_state)) { + return (uint8_t)(hid->poll); + } else { + return 0U; + } +} + +/*! + \brief read from FIFO + \param[in] fifo: fifo address + \param[in] buf: read buffer + \param[in] nbytes: number of item to read + \param[out] none + \retval number of read items +*/ +uint16_t usbh_hid_fifo_read(data_fifo *fifo, void *buf, uint16_t nbytes) +{ + uint16_t i = 0U; + uint8_t *p = (uint8_t *) buf; + + if(0U == fifo->lock) { + fifo->lock = 1U; + + for(i = 0U; i < nbytes; i++) { + if(fifo->tail != fifo->head) { + *p++ = fifo->buf[fifo->tail]; + fifo->tail++; + + if(fifo->tail == fifo->size) { + fifo->tail = 0U; + } + } else { + fifo->lock = 0U; + + return i; + } + } + } + + fifo->lock = 0U; + + return nbytes; +} + +/*! + \brief write to FIFO + \param[in] fifo: fifo address + \param[in] buf: read buffer + \param[in] nbytes: number of item to read + \param[out] none + \retval number of write items +*/ +uint16_t usbh_hid_fifo_write(data_fifo *fifo, void *buf, uint16_t nbytes) +{ + uint16_t i = 0U; + uint8_t *p = (uint8_t *) buf; + + if(0U == fifo->lock) { + fifo->lock = 1U; + + for(i = 0U; i < nbytes; i++) { + if((fifo->head + 1U == fifo->tail) || + ((fifo->head + 1U == fifo->size) && (0U == fifo->tail))) { + fifo->lock = 0U; + + return i; + } else { + fifo->buf[fifo->head] = *p++; + fifo->head++; + + if(fifo->head == fifo->size) { + fifo->head = 0U; + } + } + } + } + + fifo->lock = 0U; + + return nbytes; +} + +/*! + \brief initialize FIFO + \param[in] fifo: fifo address + \param[in] buf: read buffer + \param[in] size: size of FIFO + \param[out] none + \retval none +*/ +void usbh_hid_fifo_init(data_fifo *fifo, uint8_t *buf, uint16_t size) +{ + fifo->head = 0U; + fifo->tail = 0U; + fifo->lock = 0U; + fifo->size = size; + fifo->buf = buf; +} + +/*! + \brief initialize the hid class + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_itf_init(usbh_host *puhost) +{ + uint8_t num = 0U, ep_num = 0U, interface = 0U; + usbh_status status = USBH_BUSY; + + interface = usbh_interface_find(&puhost->dev_prop, USB_HID_CLASS, USB_HID_SUBCLASS_BOOT_ITF, 0xFFU); + + if(0xFFU == interface) { + puhost->usr_cb->dev_not_supported(); + + status = USBH_FAIL; + } else { + usbh_interface_select(&puhost->dev_prop, interface); + + static usbh_hid_handler hid_handler; + + memset((void *)&hid_handler, 0, sizeof(usbh_hid_handler)); + + hid_handler.state = HID_ERROR; + + uint8_t itf_protocol = puhost->dev_prop.cfg_desc_set.itf_desc_set[puhost->dev_prop.cur_itf][0].itf_desc.bInterfaceProtocol; + if(USB_HID_PROTOCOL_KEYBOARD == itf_protocol) { + hid_handler.init = usbh_hid_keybd_init; + hid_handler.machine = usbh_hid_keybrd_machine; + } else if(USB_HID_PROTOCOL_MOUSE == itf_protocol) { + hid_handler.init = usbh_hid_mouse_init; + hid_handler.machine = usbh_hid_mouse_machine; + } else { + status = USBH_FAIL; + } + + hid_handler.state = HID_INIT; + hid_handler.ctl_state = HID_REQ_INIT; + hid_handler.ep_addr = puhost->dev_prop.cfg_desc_set.itf_desc_set[puhost->dev_prop.cur_itf][0].ep_desc[0].bEndpointAddress; + hid_handler.len = puhost->dev_prop.cfg_desc_set.itf_desc_set[puhost->dev_prop.cur_itf][0].ep_desc[0].wMaxPacketSize; + hid_handler.poll = puhost->dev_prop.cfg_desc_set.itf_desc_set[puhost->dev_prop.cur_itf][0].ep_desc[0].bInterval; + + if(hid_handler.poll < HID_MIN_POLL) { + hid_handler.poll = HID_MIN_POLL; + } + + /* check for available number of endpoints */ + /* find the number of endpoints in the interface descriptor */ + /* choose the lower number in order not to overrun the buffer allocated */ + ep_num = USB_MIN(puhost->dev_prop.cfg_desc_set.itf_desc_set[puhost->dev_prop.cur_itf][0].itf_desc.bNumEndpoints, USBH_MAX_EP_NUM); + + /* decode endpoint IN and OUT address from interface descriptor */ + for(num = 0U; num < ep_num; num++) { + usb_desc_ep *ep_desc = &puhost->dev_prop.cfg_desc_set.itf_desc_set[puhost->dev_prop.cur_itf][0].ep_desc[num]; + + uint8_t ep_addr = ep_desc->bEndpointAddress; + + if(ep_addr & 0x80U) { + hid_handler.ep_in = ep_addr; + hid_handler.pipe_in = usbh_pipe_allocate(puhost->data, ep_addr); + + /* open channel for IN endpoint */ + usbh_pipe_create(puhost->data, + &puhost->dev_prop, + hid_handler.pipe_in, + USB_EPTYPE_INTR, + hid_handler.len); + + usbh_pipe_toggle_set(puhost->data, hid_handler.pipe_in, 0U); + } else { + hid_handler.ep_out = ep_addr; + hid_handler.pipe_out = usbh_pipe_allocate(puhost->data, ep_addr); + + /* open channel for OUT endpoint */ + usbh_pipe_create(puhost->data, + &puhost->dev_prop, + hid_handler.pipe_out, + USB_EPTYPE_INTR, + hid_handler.len); + + usbh_pipe_toggle_set(puhost->data, hid_handler.pipe_out, 0U); + } + } + + puhost->active_class->class_data = (void *)&hid_handler; + + status = USBH_OK; + } + + return status; +} + +/*! + \brief handle HID class requests for HID class + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_class_req(usbh_host *puhost) +{ + usbh_status status = USBH_BUSY; + usbh_status class_req_status = USBH_BUSY; + + usbh_hid_handler *hid = (usbh_hid_handler *)puhost->active_class->class_data; + + /* handle HID control state machine */ + switch(hid->ctl_state) { + case HID_REQ_INIT: + case HID_REQ_GET_HID_DESC: + /* get HID descriptor */ + if(USBH_OK == usbh_hid_desc_get(puhost, USB_HID_DESC_SIZE)) { + usbh_hiddesc_parse(&hid->hid_desc, puhost->dev_prop.data); + + hid->ctl_state = HID_REQ_GET_REPORT_DESC; + } + break; + + case HID_REQ_GET_REPORT_DESC: + /* get report descriptor */ + if(USBH_OK == usbh_hid_reportdesc_get(puhost, hid->hid_desc.wDescriptorLength)) { + hid->ctl_state = HID_REQ_SET_IDLE; + } + break; + + case HID_REQ_SET_IDLE: + class_req_status = usbh_set_idle(puhost, 0U, 0U); + + /* set idle */ + if(USBH_OK == class_req_status) { + hid->ctl_state = HID_REQ_SET_PROTOCOL; + } else { + if(USBH_NOT_SUPPORTED == class_req_status) { + hid->ctl_state = HID_REQ_SET_PROTOCOL; + } + } + break; + + case HID_REQ_SET_PROTOCOL: + /* set protocol */ + if(USBH_OK == usbh_set_protocol(puhost, 0U)) { + hid->ctl_state = HID_REQ_IDLE; + + /* all requests performed */ + status = USBH_OK; + } + break; + + case HID_REQ_IDLE: + default: + break; + } + + return status; +} + +/*! + \brief manage state machine for HID data transfers + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_handle(usbh_host *puhost) +{ + usbh_status status = USBH_OK; + usbh_hid_handler *hid = (usbh_hid_handler *)puhost->active_class->class_data; + + switch(hid->state) { + case HID_INIT: + hid->init(puhost->data, puhost); + hid->state = HID_IDLE; + break; + + case HID_IDLE: + hid->state = HID_SYNC; + status = USBH_OK; + break; + + case HID_SYNC: + /* sync with start of even frame */ + if(true == usb_frame_even(puhost->data)) { + hid->state = HID_GET_DATA; + } + break; + + case HID_GET_DATA: + usbh_data_recev(puhost->data, hid->pdata, hid->pipe_in, hid->len); + + hid->state = HID_POLL; + hid->timer = usb_curframe_get(puhost->data); + hid->data_ready = 0U; + break; + + case HID_POLL: + if(URB_DONE == usbh_urbstate_get(puhost->data, hid->pipe_in)) { + if(0U == hid->data_ready) { /* handle data once */ + usbh_hid_fifo_write(&hid->fifo, hid->pdata, hid->len); + hid->data_ready = 1U; + + hid->machine(puhost->data, puhost); + } + } else { + if(URB_STALL == usbh_urbstate_get(puhost->data, hid->pipe_in)) { /* IN endpoint stalled */ + /* issue clear feature on interrupt in endpoint */ + if(USBH_OK == (usbh_clrfeature(puhost, hid->ep_addr, hid->pipe_in))) { + /* change state to issue next in token */ + hid->state = HID_GET_DATA; + } + } + } + break; + + default: + break; + } + return status; +} + +/*! + \brief send get report descriptor command to the device + \param[in] puhost: pointer to usb host + \param[in] len: HID report descriptor length + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_reportdesc_get(usbh_host *puhost, uint16_t len) +{ + usbh_status status = USBH_BUSY; + + if(CTL_IDLE == puhost->control.ctl_state) { + puhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_RECPTYPE_ITF | USB_REQTYPE_STRD, + .bRequest = USB_GET_DESCRIPTOR, + .wValue = USBH_DESC(USB_DESCTYPE_REPORT), + .wIndex = 0U, + .wLength = len + }; + + usbh_ctlstate_config(puhost, puhost->dev_prop.data, len); + } + + status = usbh_ctl_handler(puhost); + + return status; +} + +/*! + \brief managing the SOF process + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_sof(usbh_host *puhost) +{ + usbh_hid_handler *hid = (usbh_hid_handler *)puhost->active_class->class_data; + + if(HID_POLL == hid->state) { + uint32_t frame_count = usb_curframe_get(puhost->data); + + if((frame_count > hid->timer) && ((frame_count - hid->timer) >= hid->poll)) { + hid->state = HID_GET_DATA; + } else if((frame_count < hid->timer) && ((frame_count + 0x3FFFU - hid->timer) >= hid->poll)) { + hid->state = HID_GET_DATA; + } else { + /* no operation */ + } + } + + return USBH_OK; +} + +/*! + \brief send the command of get HID descriptor to the device + \param[in] puhost: pointer to usb host + \param[in] len: HID descriptor length + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_desc_get(usbh_host *puhost, uint16_t len) +{ + usbh_status status = USBH_BUSY; + + if(CTL_IDLE == puhost->control.ctl_state) { + puhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_RECPTYPE_ITF | USB_REQTYPE_STRD, + .bRequest = USB_GET_DESCRIPTOR, + .wValue = USBH_DESC(USB_DESCTYPE_HID), + .wIndex = 0U, + .wLength = len + }; + + usbh_ctlstate_config(puhost, puhost->dev_prop.data, len); + } + + status = usbh_ctl_handler(puhost); + + return status; +} + +/*! + \brief set idle state + \param[in] puhost: pointer to usb host + \param[in] duration: duration for HID set idle request + \param[in] report_ID: targeted report ID for HID set idle request + \param[out] none + \retval operation status +*/ +static usbh_status usbh_set_idle(usbh_host *puhost, uint8_t duration, uint8_t report_ID) +{ + usbh_status status = USBH_BUSY; + + if(CTL_IDLE == puhost->control.ctl_state) { + puhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS, + .bRequest = SET_IDLE, + .wValue = (duration << 8U) | report_ID, + .wIndex = 0U, + .wLength = 0U + }; + + usbh_ctlstate_config(puhost, NULL, 0U); + } + + status = usbh_ctl_handler(puhost); + + return status; +} + +/*! + \brief set protocol state + \param[in] puhost: pointer to usb host + \param[in] protocol: boot/report protocol + \param[out] none + \retval operation status +*/ +static usbh_status usbh_set_protocol(usbh_host *puhost, uint8_t protocol) +{ + usbh_status status = USBH_BUSY; + + if(CTL_IDLE == puhost->control.ctl_state) { + puhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_CLASS, + .bRequest = SET_PROTOCOL, + .wValue = !protocol, + .wIndex = 0U, + .wLength = 0U + }; + + usbh_ctlstate_config(puhost, NULL, 0U); + } + + status = usbh_ctl_handler(puhost); + + return status; +} + +/*! + \brief parse the HID descriptor + \param[in] hid_desc: pointer to HID descriptor + \param[in] buf: pointer to buffer where the source descriptor is available + \param[out] none + \retval none +*/ +static void usbh_hiddesc_parse(usb_desc_hid *hid_desc, uint8_t *buf) +{ + hid_desc->header.bLength = *(uint8_t *)(buf + 0U); + hid_desc->header.bDescriptorType = *(uint8_t *)(buf + 1U); + hid_desc->bcdHID = BYTE_SWAP(buf + 2U); + hid_desc->bCountryCode = *(uint8_t *)(buf + 4U); + hid_desc->bNumDescriptors = *(uint8_t *)(buf + 5U); + hid_desc->bDescriptorType = *(uint8_t *)(buf + 6U); + hid_desc->wDescriptorLength = BYTE_SWAP(buf + 7U); +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Source/usbh_hid_keybd.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Source/usbh_hid_keybd.c new file mode 100644 index 000000000..ad8948f10 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Source/usbh_hid_keybd.c @@ -0,0 +1,388 @@ +/*! + \file usbh_hid_keybd.c + \brief USB host HID keyboard driver + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_hid_keybd.h" +#include "usbh_hid_parser.h" +#include + +hid_keybd_info keybd_info; + +uint32_t keybd_report_data[2]; + +static const hid_report_item imp_0_lctrl = { + (uint8_t *)(void *)keybd_report_data + 0, /* data */ + 1, /* size */ + 0, /* shift */ + 0, /* count (only for array items) */ + 0, /* signed */ + 0, /* min value read can return */ + 1, /* max value read can return */ + 0, /* min vale device can report */ + 1, /* max value device can report */ + 1 /* resolution */ +}; + +static const hid_report_item imp_0_lshift = { + (uint8_t *)(void *)keybd_report_data + 0, /* data */ + 1, /* size */ + 1, /* shift */ + 0, /* count (only for array items) */ + 0, /* signed */ + 0, /* min value read can return */ + 1, /* max value read can return */ + 0, /* min vale device can report */ + 1, /* max value device can report */ + 1 /* resolution */ +}; + +static const hid_report_item imp_0_lalt = { + (uint8_t *)(void *)keybd_report_data + 0, /* data */ + 1, /* size */ + 2, /* shift */ + 0, /* count (only for array items) */ + 0, /* signed */ + 0, /* min value read can return */ + 1, /* max value read can return */ + 0, /* min vale device can report */ + 1, /* max value device can report */ + 1 /* resolution */ +}; + +static const hid_report_item imp_0_lgui = { + (uint8_t *)(void *)keybd_report_data + 0, /* data */ + 1, /* size */ + 3, /* shift */ + 0, /* count (only for array items) */ + 0, /* signed */ + 0, /* min value read can return */ + 1, /* max value read can return */ + 0, /* min vale device can report */ + 1, /* max value device can report */ + 1 /* resolution */ +}; + +static const hid_report_item imp_0_rctrl = { + (uint8_t *)(void *)keybd_report_data + 0, /* data */ + 1, /* size */ + 4, /* shift */ + 0, /* count (only for array items) */ + 0, /* signed */ + 0, /* min value read can return */ + 1, /* max value read can return */ + 0, /* min vale device can report */ + 1, /* max value device can report */ + 1 /* resolution */ +}; + +static const hid_report_item imp_0_rshift = { + (uint8_t *)(void *)keybd_report_data + 0, /* data */ + 1, /* size */ + 5, /* shift */ + 0, /* count (only for array items) */ + 0, /* signed */ + 0, /* min value read can return */ + 1, /* max value read can return */ + 0, /* min vale device can report */ + 1, /* max value device can report */ + 1 /* resolution */ +}; + +static const hid_report_item imp_0_ralt = { + (uint8_t *)(void *)keybd_report_data + 0, /* data */ + 1, /* size */ + 6, /* shift */ + 0, /* count (only for array items) */ + 0, /* signed */ + 0, /* min value read can return */ + 1, /* max value read can return */ + 0, /* min vale device can report */ + 1, /* max value device can report */ + 1 /* resolution */ +}; + +static const hid_report_item imp_0_rgui = { + (uint8_t *)(void *)keybd_report_data + 0, /* data */ + 1, /* size */ + 7, /* shift */ + 0, /* count (only for array items) */ + 0, /* signed */ + 0, /* min value read can return */ + 1, /* max value read can return */ + 0, /* min vale device can report */ + 1, /* max value device can report */ + 1 /* resolution */ +}; + +static const hid_report_item imp_0_key_array = { + (uint8_t *)(void *)keybd_report_data + 2, /* data */ + 8, /* size */ + 0, /* shift */ + 6, /* count (only for array items) */ + 0, /* signed */ + 0, /* min value read can return */ + 101, /* max value read can return */ + 0, /* min vale device can report */ + 101, /* max value device can report */ + 1 /* resolution */ +}; + +/* local constants */ +static const uint8_t hid_keybrd_codes[] = { + 0, 0, 0, 0, 31, 50, 48, 33, + 19, 34, 35, 36, 24, 37, 38, 39, /* 0x00 - 0x0F */ + 52, 51, 25, 26, 17, 20, 32, 21, + 23, 49, 18, 47, 22, 46, 2, 3, /* 0x10 - 0x1F */ + 4, 5, 6, 7, 8, 9, 10, 11, + 43, 110, 15, 16, 61, 12, 13, 27, /* 0x20 - 0x2F */ + 28, 29, 42, 40, 41, 1, 53, 54, + 55, 30, 112, 113, 114, 115, 116, 117, /* 0x30 - 0x3F */ + 118, 119, 120, 121, 122, 123, 124, 125, + 126, 75, 80, 85, 76, 81, 86, 89, /* 0x40 - 0x4F */ + 79, 84, 83, 90, 95, 100, 105, 106, + 108, 93, 98, 103, 92, 97, 102, 91, /* 0x50 - 0x5F */ + 96, 101, 99, 104, 45, 129, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x60 - 0x6F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x70 - 0x7F */ + 0, 0, 0, 0, 0, 107, 0, 56, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x80 - 0x8F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0x90 - 0x9F */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xA0 - 0xAF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xB0 - 0xBF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xC0 - 0xCF */ + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, /* 0xD0 - 0xDF */ + 58, 44, 60, 127, 64, 57, 62, 128 /* 0xE0 - 0xE7 */ +}; + +#ifdef QWERTY_KEYBOARD + +static const int8_t hid_keybrd_key[] = { + '\0', '`', '1', '2', '3', '4', '5', '6', + '7', '8', '9', '0', '-', '=', '\0', '\r', + '\t', 'q', 'w', 'e', 'r', 't', 'y', 'u', + 'i', 'o', 'p', '[', ']', '\\', + '\0', 'a', 's', 'd', 'f', 'g', 'h', 'j', + 'k', 'l', ';', '\'', '\0', '\n', + '\0', '\0', 'z', 'x', 'c', 'v', 'b', 'n', + 'm', ',', '.', '/', '\0', '\0', + '\0', '\0', '\0', ' ', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '7', '4', '1', + '\0', '/', '8', '5', '2', + '0', '*', '9', '6', '3', + '.', '-', '+', '\0', '\n', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0' +}; + +static const int8_t hid_keybrd_shiftkey[] = { + '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', + '_', '+', '\0', '\0', '\0', 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', + 'I', 'O', 'P', '{', '}', '|', '\0', 'A', 'S', 'D', 'F', 'G', + 'H', 'J', 'K', 'L', ':', '"', '\0', '\n', '\0', '\0', 'Z', 'X', + 'C', 'V', 'B', 'N', 'M', '<', '>', '?', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; + +#else + +static const int8_t hid_keybrd_key[] = { + '\0', '`', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', + '-', '=', '\0', '\r', '\t', 'a', 'z', 'e', 'r', 't', 'y', 'u', + 'i', 'o', 'p', '[', ']', '\\', '\0', 'q', 's', 'd', 'f', 'g', + 'h', 'j', 'k', 'l', 'm', '\0', '\0', '\n', '\0', '\0', 'w', 'x', + 'c', 'v', 'b', 'n', ',', ';', ':', '!', '\0', '\0', '\0', '\0', + '\0', ' ', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '7', '4', '1', '\0', '/', + '8', '5', '2', '0', '*', '9', '6', '3', '.', '-', '+', '\0', + '\n', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; + +static const int8_t hid_keybrd_shiftkey[] = { + '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', + '+', '\0', '\0', '\0', 'A', 'Z', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', + 'P', '{', '}', '*', '\0', 'Q', 'S', 'D', 'F', 'G', 'H', 'J', 'K', + 'L', 'M', '%', '\0', '\n', '\0', '\0', 'W', 'X', 'C', 'V', 'B', 'N', + '?', '.', '/', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', + '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' +}; + +#endif + +/* local function prototypes ('static') */ +static usbh_status usbh_hid_keybrd_decode(usb_core_driver *pudev, usbh_host *puhost); + +/*! + \brief initialize the keyboard function + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +usbh_status usbh_hid_keybd_init(usb_core_driver *pudev, usbh_host *puhost) +{ + usbh_hid_handler *hid = (usbh_hid_handler *)puhost->active_class->class_data; + + keybd_info.lctrl = keybd_info.lshift = 0U; + keybd_info.lalt = keybd_info.lgui = 0U; + keybd_info.rctrl = keybd_info.rshift = 0U; + keybd_info.ralt = keybd_info.rgui = 0U; + + for(uint32_t x = 0U; x < (sizeof(keybd_report_data) / sizeof(uint32_t)); x++) { + keybd_report_data[x] = 0U; + } + + if(hid->len > (sizeof(keybd_report_data) / sizeof(uint32_t))) { + hid->len = (sizeof(keybd_report_data) / sizeof(uint32_t)); + } + + hid->pdata = (uint8_t *)(void *)keybd_report_data; + + usbh_hid_fifo_init(&hid->fifo, puhost->dev_prop.data, HID_QUEUE_SIZE * sizeof(keybd_report_data)); + + /* call user init*/ + usr_keybrd_init(); + + return USBH_OK; +} + +/*! + \brief get keyboard information + \param[in] pudev: pointer to USB core instance + \param[in] puhost: pointer to USB host handler + \param[out] none + \retval keyboard information +*/ +hid_keybd_info *usbh_hid_keybd_info_get(usb_core_driver *pudev, usbh_host *puhost) +{ + if(USBH_OK == usbh_hid_keybrd_decode(pudev, puhost)) { + return &keybd_info; + } else { + return NULL; + } +} + +/*! + \brief get ascii code + \param[in] info: keyboard information + \param[out] none + \retval output +*/ +uint8_t usbh_hid_ascii_code_get(hid_keybd_info *info) +{ + uint8_t output; + if((1U == info->lshift) || (info->rshift)) { + output = hid_keybrd_shiftkey[hid_keybrd_codes[info->keys[0]]]; + } else { + output = hid_keybrd_key[hid_keybrd_codes[info->keys[0]]]; + } + + return output; +} + +/*! + \brief decode the pressed keys + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval none +*/ +void usbh_hid_keybrd_machine(usb_core_driver *pudev, usbh_host *puhost) +{ + hid_keybd_info *k_pinfo; + + k_pinfo = usbh_hid_keybd_info_get(pudev, puhost); + + if(k_pinfo != NULL) { + char c = usbh_hid_ascii_code_get(k_pinfo); + + if(c != 0U) { + usr_keybrd_process_data(c); + } + } +} + +/*! + \brief decode keyboard information + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_keybrd_decode(usb_core_driver *pudev, usbh_host *puhost) +{ + usbh_hid_handler *hid = (usbh_hid_handler *)puhost->active_class->class_data; + + if(hid->len == 0U) { + return USBH_FAIL; + } + + /* fill report */ + if(usbh_hid_fifo_read(&hid->fifo, &keybd_report_data, hid->len) == hid->len) { + keybd_info.lctrl = (uint8_t)hid_item_read((hid_report_item *)&imp_0_lctrl, 0U); + keybd_info.lshift = (uint8_t)hid_item_read((hid_report_item *)&imp_0_lshift, 0U); + keybd_info.lalt = (uint8_t)hid_item_read((hid_report_item *)&imp_0_lalt, 0U); + keybd_info.lgui = (uint8_t)hid_item_read((hid_report_item *)&imp_0_lgui, 0U); + keybd_info.rctrl = (uint8_t)hid_item_read((hid_report_item *)&imp_0_rctrl, 0U); + keybd_info.rshift = (uint8_t)hid_item_read((hid_report_item *)&imp_0_rshift, 0U); + keybd_info.ralt = (uint8_t)hid_item_read((hid_report_item *)&imp_0_ralt, 0U); + keybd_info.rgui = (uint8_t)hid_item_read((hid_report_item *)&imp_0_rgui, 0U); + + for(uint8_t x = 0U; x < sizeof(keybd_info.keys); x++) { + keybd_info.keys[x] = (uint8_t)hid_item_read((hid_report_item *)&imp_0_key_array, x); + } + + return USBH_OK; + } + + return USBH_FAIL; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Source/usbh_hid_mouse.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Source/usbh_hid_mouse.c new file mode 100644 index 000000000..2c609ed66 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Source/usbh_hid_mouse.c @@ -0,0 +1,211 @@ +/*! + \file usbh_hid_mouse.c + \brief USB host HID mouse driver + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_hid_mouse.h" +#include "usbh_hid_parser.h" + +hid_mouse_info mouse_info; +uint32_t mouse_report_data[1]; + +/* structures defining how to access items in a hid mouse report */ +/* access button 1 state. */ +static const hid_report_item prop_b1 = { + (uint8_t *)(void *)mouse_report_data + 0, /* data */ + 1, /* size */ + 0, /* shift */ + 0, /* count (only for array items) */ + 0, /* signed? */ + 0, /* min value read can return */ + 1, /* max value read can return */ + 0, /* min value device can report */ + 1, /* max value device can report */ + 1 /* resolution */ +}; + +/* access button 2 state. */ +static const hid_report_item prop_b2 = { + (uint8_t *)(void *)mouse_report_data + 0, /* data */ + 1, /* size */ + 1, /* shift */ + 0, /* count (only for array items) */ + 0, /* signed? */ + 0, /* min value read can return */ + 1, /* max value read can return */ + 0, /* min value device can report */ + 1, /* max value device can report */ + 1 /* resolution */ +}; + +/* access button 3 state. */ +static const hid_report_item prop_b3 = { + (uint8_t *)(void *)mouse_report_data + 0, /* data */ + 1, /* size */ + 2, /* shift */ + 0, /* count (only for array items) */ + 0, /* signed? */ + 0, /* min value read can return */ + 1, /* max value read can return */ + 0, /* min vale device can report */ + 1, /* max value device can report */ + 1 /* resolution */ +}; + +/* access x coordinate change. */ +static const hid_report_item prop_x = { + (uint8_t *)(void *)mouse_report_data + 1, /* data */ + 8, /* size */ + 0, /* shift */ + 0, /* count (only for array items) */ + 1, /* signed? */ + 0, /* min value read can return */ + 0xFFFF,/* max value read can return */ + 0, /* min vale device can report */ + 0xFFFF,/* max value device can report */ + 1 /* resolution */ +}; + +/* access y coordinate change. */ +static const hid_report_item prop_y = { + (uint8_t *)(void *)mouse_report_data + 2, /* data */ + 8, /* size */ + 0, /* shift */ + 0, /* count (only for array items) */ + 1, /* signed? */ + 0, /* min value read can return */ + 0xFFFF,/* max value read can return */ + 0, /* min vale device can report */ + 0xFFFF,/* max value device can report */ + 1 /* resolution */ +}; + +/* local function prototypes ('static') */ +static usbh_status usbh_hid_mouse_decode(usb_core_driver *pudev, usbh_host *puhost); + +/*! + \brief initialize the mouse function + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval none +*/ +usbh_status usbh_hid_mouse_init(usb_core_driver *pudev, usbh_host *puhost) +{ + usbh_hid_handler *hid = (usbh_hid_handler *)puhost->active_class->class_data; + + mouse_info.x = 0U; + mouse_info.y = 0U; + mouse_info.buttons[0] = 0U; + mouse_info.buttons[1] = 0U; + mouse_info.buttons[2] = 0U; + + mouse_report_data[0] = 0U; + + if(hid->len > sizeof(mouse_report_data)) { + hid->len = sizeof(mouse_report_data); + } + + hid->pdata = (uint8_t *)(void *)mouse_report_data; + + usbh_hid_fifo_init(&hid->fifo, puhost->dev_prop.data, HID_QUEUE_SIZE * sizeof(mouse_report_data)); + + usr_mouse_init(); + + return USBH_OK; +} + +/*! + \brief get mouse information + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval mouse information +*/ +hid_mouse_info *usbh_hid_mouse_info_get(usb_core_driver *pudev, usbh_host *puhost) +{ + if(usbh_hid_mouse_decode(pudev, puhost) == USBH_OK) { + return &mouse_info; + } else { + return NULL; + } +} + +/*! + \brief decode mouse data + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval none +*/ +void usbh_hid_mouse_machine(usb_core_driver *pudev, usbh_host *puhost) +{ + hid_mouse_info *m_pinfo = NULL; + + m_pinfo = usbh_hid_mouse_info_get(pudev, puhost); + + if(NULL != m_pinfo) { + /* handle mouse data position */ + usr_mouse_process_data(&mouse_info); + } +} + +/*! + \brief decode mouse information + \param[in] pudev: pointer to usb core instance + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_hid_mouse_decode(usb_core_driver *pudev, usbh_host *puhost) +{ + usbh_hid_handler *hid = (usbh_hid_handler *)puhost->active_class->class_data; + + if(0U == hid->len) { + return USBH_FAIL; + } + + /* fill report */ + if(usbh_hid_fifo_read(&hid->fifo, &mouse_report_data, hid->len) == hid->len) { + /* decode report */ + mouse_info.x = (uint8_t)hid_item_read((hid_report_item *)&prop_x, 0U); + mouse_info.y = (uint8_t)hid_item_read((hid_report_item *)&prop_y, 0U); + + mouse_info.buttons[0] = (uint8_t)hid_item_read((hid_report_item *)&prop_b1, 0U); + mouse_info.buttons[1] = (uint8_t)hid_item_read((hid_report_item *)&prop_b2, 0U); + mouse_info.buttons[2] = (uint8_t)hid_item_read((hid_report_item *)&prop_b3, 0U); + + return USBH_OK; + } + + return USBH_FAIL; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Source/usbh_hid_parser.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Source/usbh_hid_parser.c new file mode 100644 index 000000000..8006e207e --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/hid/Source/usbh_hid_parser.c @@ -0,0 +1,148 @@ +/*! + \file usbh_hid_parser.c + \brief USB host HID parser driver + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_hid_parser.h" + +/*! + \brief read a hid report item + \param[in] ri: pointer to report item + \param[in] ndx: report index + \param[out] none + \retval operation status (0: fail otherwise: item value) +*/ +uint32_t hid_item_read(hid_report_item *ri, uint8_t ndx) +{ + uint32_t val = 0U; + uint32_t bofs = 0U; + uint8_t *data = ri->data; + uint8_t shift = ri->shift; + + /* get the logical value of the item */ + + /* if this is an array, wee may need to offset ri->data.*/ + if(ri->count > 0U) { + /* if app tries to read outside of the array. */ + if(ri->count <= ndx) { + return(0U); + } + + /* calculate bit offset */ + bofs = ndx * ri->size; + bofs += shift; + + /* calculate byte offset + shift pair from bit offset. */ + data += bofs / 8U; + shift = (uint8_t)(bofs % 8U); + } + + /* read data bytes in little endian order */ + for(uint32_t x = 0U; x < ((ri->size & 0x7U) ? (ri->size / 8U) + 1U : (ri->size / 8U)); x++) { + val = (uint32_t)((uint32_t)(*data) << (x * 8U)); + } + + val = (val >> shift) & ((1U << ri->size) - 1U); + + if((val < ri->logical_min) || (val > ri->logical_max)) { + return(0U); + } + + /* convert logical value to physical value */ + /* see if the number is negative or not. */ + if((ri->sign) && (val & (1U << (ri->size - 1U)))) { + /* yes, so sign extend value to 32 bits. */ + uint32_t vs = (uint32_t)((0xffffffffU & ~((1U << (ri->size)) - 1U)) | val); + + if(1U == ri->resolution) { + return((uint32_t)vs); + } + return((uint32_t)(vs * ri->resolution)); + } else { + if(1U == ri->resolution) { + return(val); + } + + return (val * ri->resolution); + } +} + +/*! + \brief write a hid report item + \param[in] ri: pointer to report item + \param[in] value: the value to be write + \param[in] ndx: report index + \param[out] none + \retval operation status (1: fail 0: Ok) +*/ +uint32_t hid_item_write(hid_report_item *ri, uint32_t value, uint8_t ndx) +{ + uint32_t mask; + uint32_t bofs; + uint8_t *data = ri->data; + uint8_t shift = ri->shift; + + if((value < ri->physical_min) || (value > ri->physical_max)) { + return(1U); + } + + /* if this is an array, wee may need to offset ri->data.*/ + if(ri->count > 0U) { + /* if app tries to read outside of the array. */ + if(ri->count >= ndx) { + return(0U); + } + + /* calculate bit offset */ + bofs = ndx * ri->size; + bofs += shift; + + /* calculate byte offset + shift pair from bit offset. */ + data += bofs / 8U; + shift = (uint8_t)(bofs % 8U); + } + + /* convert physical value to logical value. */ + if(1U != ri->resolution) { + value = value / ri->resolution; + } + + /* write logical value to report in little endian order. */ + mask = (1U << ri->size) - 1U; + value = (value & mask) << shift; + + for(uint32_t x = 0U; x < ((ri->size & 0x7U) ? (ri->size / 8U) + 1U : (ri->size / 8U)); x++) { + *(ri->data + x) = (uint8_t)((*(ri->data + x) & ~(mask >> (x * 8U))) | ((value >> (x * 8U)) & (mask >> (x * 8U)))); + } + + return 0U; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Include/usbh_msc_bbb.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Include/usbh_msc_bbb.h new file mode 100644 index 000000000..cec271a36 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Include/usbh_msc_bbb.h @@ -0,0 +1,145 @@ +/*! + \file usbh_msc_bbb.h + \brief header file for usbh_msc_bbb.c + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_MSC_BBB_H +#define __USBH_MSC_BBB_H + +#include "usbh_enum.h" +#include "msc_bbb.h" + +typedef union { + msc_bbb_cbw field; + + uint8_t CBWArray[31]; +} usbh_cbw_pkt; + +typedef union { + msc_bbb_csw field; + + uint8_t CSWArray[13]; +} usbh_csw_pkt; + +enum usbh_msc_state { + USBH_MSC_BOT_INIT_STATE = 0U, + USBH_MSC_BOT_RESET, + USBH_MSC_GET_MAX_LUN, + USBH_MSC_TEST_UNIT_READY, + USBH_MSC_READ_CAPACITY10, + USBH_MSC_MODE_SENSE6, + USBH_MSC_REQUEST_SENSE, + USBH_MSC_BOT_USB_TRANSFERS, + USBH_MSC_DEFAULT_APPLI_STATE, + USBH_MSC_CTRL_ERROR_STATE, + USBH_MSC_UNRECOVERED_STATE +}; + +typedef enum { + BOT_OK = 0U, + BOT_FAIL, + BOT_PHASE_ERROR, + BOT_BUSY +} bot_status; + +typedef enum { + BOT_CMD_IDLE = 0U, + BOT_CMD_SEND, + BOT_CMD_WAIT, +} bot_cmd_state; + +/* csw status definitions */ +typedef enum { + BOT_CSW_CMD_PASSED = 0U, + BOT_CSW_CMD_FAILED, + BOT_CSW_PHASE_ERROR, +} bot_csw_status; + +typedef enum { + BOT_SEND_CBW = 1U, + BOT_SEND_CBW_WAIT, + BOT_DATA_IN, + BOT_DATA_IN_WAIT, + BOT_DATA_OUT, + BOT_DATA_OUT_WAIT, + BOT_RECEIVE_CSW, + BOT_RECEIVE_CSW_WAIT, + BOT_ERROR_IN, + BOT_ERROR_OUT, + BOT_UNRECOVERED_ERROR +} bot_state; + +typedef struct { + uint8_t *pbuf; + uint32_t data[16]; + bot_state state; + bot_state prev_state; + bot_cmd_state cmd_state; + usbh_cbw_pkt cbw; + usbh_csw_pkt csw; +} bot_handle; + +#define USBH_MSC_BOT_CBW_TAG 0x20304050U + +#define USBH_MSC_CSW_MAX_LENGTH 63U + +#define USBH_MSC_SEND_CSW_DISABLE 0U +#define USBH_MSC_SEND_CSW_ENABLE 1U + +#define USBH_MSC_DIR_IN 0U +#define USBH_MSC_DIR_OUT 1U +#define USBH_MSC_BOTH_DIR 2U + +#define USBH_MSC_PAGE_LENGTH 512U + +#define CBW_CB_LENGTH 16U +#define CBW_LENGTH 10U +#define CBW_LENGTH_TEST_UNIT_READY 0U + +#define MAX_BULK_STALL_COUNT_LIMIT 0x04U /*!< If STALL is seen on Bulk + Endpoint continously, this means + that device and Host has phase error + Hence a Reset is needed */ + +/* function declarations */ +/* initialize the mass storage parameters */ +void usbh_msc_bot_init(usbh_host *puhost); +/* manage the different states of BOT transfer and updates the status to upper layer */ +usbh_status usbh_msc_bot_process(usbh_host *puhost, uint8_t lun); +/* manages the different error handling for stall */ +usbh_status usbh_msc_bot_abort(usbh_host *puhost, uint8_t direction); +/* reset msc bot request struct */ +usbh_status usbh_msc_bot_reset(usbh_host *puhost); +/* decode the CSW received by the device and updates the same to upper layer */ +bot_csw_status usbh_msc_csw_decode(usbh_host *puhost); + +#endif /* __USBH_MSC_BBB_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Include/usbh_msc_core.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Include/usbh_msc_core.h new file mode 100644 index 000000000..a53646df2 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Include/usbh_msc_core.h @@ -0,0 +1,119 @@ +/*! + \file usbh_core.h + \brief header file for the usbh_core.c + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_MSC_CORE_H +#define __USBH_MSC_CORE_H + +#include "usb_msc.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bbb.h" + +#define MSC_MAX_SUPPORTED_LUN 2U + +typedef enum { + MSC_INIT = 0U, + MSC_IDLE, + MSC_TEST_UNIT_READY, + MSC_READ_CAPACITY10, + MSC_READ_INQUIRY, + MSC_REQUEST_SENSE, + MSC_READ, + MSC_WRITE, + MSC_UNRECOVERED_ERROR, + MSC_PERIODIC_CHECK, +} msc_state; + +typedef enum { + MSC_OK, + MSC_NOT_READY, + MSC_ERROR, +} msc_error; + +typedef enum { + MSC_REQ_IDLE = 0U, + MSC_REQ_RESET, + MSC_REQ_GET_MAX_LUN, + MSC_REQ_ERROR, +} msc_req_state; + +/* Structure for LUN */ +typedef struct { + msc_state state; + msc_error error; + msc_scsi_sense sense; + scsi_capacity capacity; + scsi_std_inquiry_data inquiry; + usbh_status prev_ready_state; + uint8_t state_changed; +} msc_lun; + +/* structure for msc process */ +typedef struct _msc_process { + uint8_t pipe_in; + uint8_t pipe_out; + uint8_t ep_in; + uint8_t ep_out; + uint16_t ep_size_in; + uint16_t ep_size_out; + uint8_t cur_lun; + uint16_t rw_lun; + uint32_t max_lun; + msc_state state; + msc_error error; + msc_req_state req_state; + msc_req_state prev_req_state; + bot_handle bot; + msc_lun unit[MSC_MAX_SUPPORTED_LUN]; + uint32_t timer; +} usbh_msc_handler; + +extern usbh_class usbh_msc; + +/* function declarations */ +/* get msc logic unit information */ +usbh_status usbh_msc_lun_info_get(usbh_host *puhost, uint8_t lun, msc_lun *info); +/* msc read interface */ +usbh_status usbh_msc_read(usbh_host *puhost, + uint8_t lun, + uint32_t address, + uint8_t *pbuf, + uint32_t length); +/* msc write interface */ +usbh_status usbh_msc_write(usbh_host *puhost, + uint8_t lun, + uint32_t address, + uint8_t *pbuf, + uint32_t length); + +#endif /* __USBH_MSC_CORE_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Include/usbh_msc_scsi.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Include/usbh_msc_scsi.h new file mode 100644 index 000000000..b01dabcac --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Include/usbh_msc_scsi.h @@ -0,0 +1,97 @@ +/*! + \file usbh_msc_scsi.h + \brief header file for usbh_msc_scsi.c + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_MSC_SCSI_H +#define __USBH_MSC_SCSI_H + +#include "msc_scsi.h" +#include "usbh_enum.h" + +/* capacity data */ +typedef struct { + uint32_t block_nbr; + uint16_t block_size; +} scsi_capacity; + +/* inquiry data */ +typedef struct { + uint8_t peripheral_qualifier; + uint8_t device_type; + uint8_t removable_media; + uint8_t vendor_id[9]; + uint8_t product_id[17]; + uint8_t revision_id[5]; +} scsi_std_inquiry_data; + +typedef struct { + uint32_t msc_capacity; + uint32_t msc_sense_key; + uint16_t msc_page_len; + uint8_t msc_write_protect; +} usbh_msc_parameter; + +#define DESC_REQUEST_SENSE 0x00U +#define ALLOCATION_LENGTH_REQUEST_SENSE 63U +#define XFER_LEN_MODE_SENSE6 63U + +#define MASK_MODE_SENSE_WRITE_PROTECT 0x80U +#define MODE_SENSE_PAGE_CONTROL_FIELD 0x00U +#define MODE_SENSE_PAGE_CODE 0x3FU +#define DISK_WRITE_PROTECTED 0x01U + +/* function declarations */ +/* send 'Inquiry' command to the device */ +usbh_status usbh_msc_scsi_inquiry(usbh_host *puhost, uint8_t lun, scsi_std_inquiry_data *inquiry); +/* send 'Test unit ready' command to the device */ +usbh_status usbh_msc_test_unitready(usbh_host *puhost, uint8_t lun); +/* send the read capacity command to the device */ +usbh_status usbh_msc_read_capacity10(usbh_host *puhost, uint8_t lun, scsi_capacity *capacity); +/* send the mode sense6 command to the device */ +usbh_status usbh_msc_mode_sense6(usbh_host *puhost, uint8_t lun); +/* send the Request Sense command to the device */ +usbh_status usbh_msc_request_sense(usbh_host *puhost, uint8_t lun, msc_scsi_sense *sense_data); +/* send the write10 command to the device */ +usbh_status usbh_msc_write10(usbh_host *puhost, + uint8_t lun, + uint8_t *data_buf, + uint32_t addr, + uint32_t byte_num); +/* send the read10 command to the device */ +usbh_status usbh_msc_read10(usbh_host *puhost, + uint8_t lun, + uint8_t *data_buf, + uint32_t addr, + uint32_t byte_num); + +#endif /* __USBH_MSC_SCSI_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Source/usbh_msc_bbb.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Source/usbh_msc_bbb.c new file mode 100644 index 000000000..163379383 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Source/usbh_msc_bbb.c @@ -0,0 +1,362 @@ +/*! + \file usbh_msc_bbb.c + \brief USB MSC BBB protocol related functions + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_pipe.h" +#include "usbh_msc_core.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bbb.h" +#include "usbh_transc.h" +#include "drv_usbh_int.h" + +/*! + \brief initialize the mass storage parameters + \param[in] puhost: pointer to usb host handler + \param[out] none + \retval none +*/ +void usbh_msc_bot_init(usbh_host *puhost) +{ + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + + msc->bot.cbw.field.dCBWSignature = BBB_CBW_SIGNATURE; + msc->bot.cbw.field.dCBWTag = USBH_MSC_BOT_CBW_TAG; + msc->bot.state = BOT_SEND_CBW; + msc->bot.cmd_state = BOT_CMD_SEND; +} + +/*! + \brief manage the different states of BOT transfer and updates the status to upper layer + \param[in] puhost: pointer to usb host handler + \param[in] lun: logic unit number + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_bot_process(usbh_host *puhost, uint8_t lun) +{ + bot_csw_status csw_status = BOT_CSW_CMD_FAILED; + usbh_status status = USBH_BUSY; + usbh_status error = USBH_BUSY; + usb_urb_state urb_status = URB_IDLE; + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + + switch(msc->bot.state) { + case BOT_SEND_CBW: + msc->bot.cbw.field.bCBWLUN = lun; + msc->bot.state = BOT_SEND_CBW_WAIT; + /* send CBW */ + usbh_data_send(puhost->data, + msc->bot.cbw.CBWArray, + msc->pipe_out, + BBB_CBW_LENGTH); + break; + + case BOT_SEND_CBW_WAIT: + urb_status = usbh_urbstate_get(puhost->data, msc->pipe_out); + + if(URB_DONE == urb_status) { + if(0U != msc->bot.cbw.field.dCBWDataTransferLength) { + if(USB_TRX_IN == (msc->bot.cbw.field.bmCBWFlags & USB_TRX_MASK)) { + msc->bot.state = BOT_DATA_IN; + } else { + msc->bot.state = BOT_DATA_OUT; + } + } else { + msc->bot.state = BOT_RECEIVE_CSW; + } + + } else if(URB_NOTREADY == urb_status) { + msc->bot.state = BOT_SEND_CBW; + } else { + if(URB_STALL == urb_status) { + msc->bot.state = BOT_ERROR_OUT; + } + } + break; + + case BOT_DATA_IN: + usbh_data_recev(puhost->data, + msc->bot.pbuf, + msc->pipe_in, + msc->ep_size_in); + + msc->bot.state = BOT_DATA_IN_WAIT; + break; + + case BOT_DATA_IN_WAIT: + urb_status = usbh_urbstate_get(puhost->data, msc->pipe_in); + + /* BOT DATA IN stage */ + if(URB_DONE == urb_status) { + if(msc->bot.cbw.field.dCBWDataTransferLength > msc->ep_size_in) { + msc->bot.pbuf += msc->ep_size_in; + msc->bot.cbw.field.dCBWDataTransferLength -= msc->ep_size_in; + } else { + msc->bot.cbw.field.dCBWDataTransferLength = 0U; + } + + if(msc->bot.cbw.field.dCBWDataTransferLength > 0U) { + usbh_data_recev(puhost->data, + msc->bot.pbuf, + msc->pipe_in, + msc->ep_size_in); + } else { + msc->bot.state = BOT_RECEIVE_CSW; + } + } else if(URB_STALL == urb_status) { + /* this is data stage stall condition */ + msc->bot.state = BOT_ERROR_IN; + } else { + /* no operation */ + } + break; + + case BOT_DATA_OUT: + usbh_data_send(puhost->data, + msc->bot.pbuf, + msc->pipe_out, + msc->ep_size_out); + + msc->bot.state = BOT_DATA_OUT_WAIT; + break; + + case BOT_DATA_OUT_WAIT: + /* BOT DATA OUT stage */ + urb_status = usbh_urbstate_get(puhost->data, msc->pipe_out); + if(URB_DONE == urb_status) { + if(msc->bot.cbw.field.dCBWDataTransferLength > msc->ep_size_out) { + msc->bot.pbuf += msc->ep_size_out; + msc->bot.cbw.field.dCBWDataTransferLength -= msc->ep_size_out; + } else { + msc->bot.cbw.field.dCBWDataTransferLength = 0; /* reset this value and keep in same state */ + } + + if(msc->bot.cbw.field.dCBWDataTransferLength > 0) { + usbh_data_send(puhost->data, + msc->bot.pbuf, + msc->pipe_out, + msc->ep_size_out); + } else { + msc->bot.state = BOT_RECEIVE_CSW; + } + } else if(URB_NOTREADY == urb_status) { + msc->bot.state = BOT_DATA_OUT; + } else if(URB_STALL == urb_status) { + msc->bot.state = BOT_ERROR_OUT; + } else { + /* no operation */ + } + break; + + case BOT_RECEIVE_CSW: + /* BOT CSW stage */ + usbh_data_recev(puhost->data, + msc->bot.csw.CSWArray, + msc->pipe_in, + BBB_CSW_LENGTH); + + msc->bot.state = BOT_RECEIVE_CSW_WAIT; + break; + + case BOT_RECEIVE_CSW_WAIT: + urb_status = usbh_urbstate_get(puhost->data, msc->pipe_in); + + /* decode CSW */ + if(URB_DONE == urb_status) { + msc->bot.state = BOT_SEND_CBW; + msc->bot.cmd_state = BOT_CMD_SEND; + + csw_status = usbh_msc_csw_decode(puhost); + if(BOT_CSW_CMD_PASSED == csw_status) { + status = USBH_OK; + } else { + status = USBH_FAIL; + } + } else if(URB_STALL == urb_status) { + msc->bot.state = BOT_ERROR_IN; + } else { + /* no operation */ + } + break; + + case BOT_ERROR_IN: + error = usbh_msc_bot_abort(puhost, USBH_MSC_DIR_IN); + + if(USBH_OK == error) { + msc->bot.state = BOT_RECEIVE_CSW; + } else if(USBH_UNRECOVERED_ERROR == status) { + /* this means that there is a stall error limit, do reset recovery */ + msc->bot.state = BOT_UNRECOVERED_ERROR; + } else { + /* no operation */ + } + break; + + case BOT_ERROR_OUT: + status = usbh_msc_bot_abort(puhost, USBH_MSC_DIR_OUT); + + if(USBH_OK == status) { + uint8_t toggle = usbh_pipe_toggle_get(puhost->data, msc->pipe_out); + usbh_pipe_toggle_set(puhost->data, msc->pipe_out, 1U - toggle); + usbh_pipe_toggle_set(puhost->data, msc->pipe_in, 0U); + msc->bot.state = BOT_ERROR_IN; + } else { + if(USBH_UNRECOVERED_ERROR == status) { + msc->bot.state = BOT_UNRECOVERED_ERROR; + } + } + break; + + case BOT_UNRECOVERED_ERROR: + status = usbh_msc_bot_reset(puhost); + if(USBH_OK == status) { + msc->bot.state = BOT_SEND_CBW; + } + break; + + default: + break; + } + + return status; +} + +/*! + \brief manages the different error handling for stall + \param[in] puhost: pointer to usb host handler + \param[in] direction: data IN or OUT + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_bot_abort(usbh_host *puhost, uint8_t direction) +{ + usbh_status status = USBH_BUSY; + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + + switch(direction) { + case USBH_MSC_DIR_IN : + /* send clrfeture command on bulk IN endpoint */ + status = usbh_clrfeature(puhost, + msc->ep_in, + msc->pipe_in); + break; + + case USBH_MSC_DIR_OUT : + /*send clrfeature command on bulk OUT endpoint */ + status = usbh_clrfeature(puhost, + msc->ep_out, + msc->pipe_out); + break; + + default: + break; + } + + return status; +} + +/*! + \brief reset msc bot transfer + \param[in] puhost: pointer to usb host handler + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_bot_reset(usbh_host *puhost) +{ + usbh_status status = USBH_BUSY; + + if(CTL_IDLE == puhost->control.ctl_state) { + puhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_REQTYPE_CLASS | USB_RECPTYPE_ITF, + .bRequest = BBB_RESET, + .wValue = 0U, + .wIndex = 0U, + .wLength = 0U + }; + + usbh_ctlstate_config(puhost, NULL, 0U); + } + + status = usbh_ctl_handler(puhost); + + return status; +} + +/*! + \brief decode the CSW received by the device and updates the same to upper layer + \param[in] puhost: pointer to usb host + \param[out] none + \retval on success USBH_MSC_OK, on failure USBH_MSC_FAIL + \notes + Refer to USB Mass-Storage Class: BOT (www.usb.org) + 6.3.1 Valid CSW Conditions : + The host shall consider the CSW valid when: + 1. dCSWSignature is equal to 53425355h + 2. the CSW is 13 (Dh) bytes in length, + 3. dCSWTag matches the dCBWTag from the corresponding CBW. +*/ +bot_csw_status usbh_msc_csw_decode(usbh_host *puhost) +{ + bot_csw_status status = BOT_CSW_CMD_FAILED; + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + + /* checking if the transfer length is different than 13 */ + if(BBB_CSW_LENGTH != usbh_xfercount_get(puhost->data, msc->pipe_in)) { + status = BOT_CSW_PHASE_ERROR; + } else { + /* CSW length is correct */ + + /* check validity of the CSW Signature and CSWStatus */ + if(BBB_CSW_SIGNATURE == msc->bot.csw.field.dCSWSignature) { + /* check condition 1. dCSWSignature is equal to 53425355h */ + if(msc->bot.csw.field.dCSWTag == msc->bot.cbw.field.dCBWTag) { + /* check condition 3. dCSWTag matches the dCBWTag from the corresponding CBW */ + if(0U == msc->bot.csw.field.bCSWStatus) { + status = BOT_CSW_CMD_PASSED; + } else if(1U == msc->bot.csw.field.bCSWStatus) { + status = BOT_CSW_CMD_FAILED; + } else if(2U == msc->bot.csw.field.bCSWStatus) { + status = BOT_CSW_PHASE_ERROR; + } else { + /* no operation */ + } + } + } else { + /* If the CSW signature is not valid, we will return the phase error to + upper layers for reset recovery */ + status = BOT_CSW_PHASE_ERROR; + } + } + + return status; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Source/usbh_msc_core.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Source/usbh_msc_core.c new file mode 100644 index 000000000..f29177922 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Source/usbh_msc_core.c @@ -0,0 +1,560 @@ +/*! + \file usbh_core.c + \brief USB MSC(mass storage device) class driver + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_msc_core.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bbb.h" +#include "usbh_pipe.h" +#include "usbh_transc.h" +#include +#include + +/* local function prototypes ('static') */ +static void usbh_msc_itf_deinit(usbh_host *puhost); +static usbh_status usbh_msc_itf_init(usbh_host *puhost); +static usbh_status usbh_msc_req(usbh_host *puhost); +static usbh_status usbh_msc_handle(usbh_host *puhost); +static usbh_status usbh_msc_maxlun_get(usbh_host *puhost, uint8_t *maxlun); +static usbh_status usbh_msc_rdwr_process(usbh_host *puhost, uint8_t lun); + +usbh_class usbh_msc = { + USB_CLASS_MSC, + usbh_msc_itf_init, + usbh_msc_itf_deinit, + usbh_msc_req, + usbh_msc_handle, +}; + +/*! + \brief interface initialization for MSC class + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_msc_itf_init(usbh_host *puhost) +{ + usbh_status status = USBH_OK; + + uint8_t interface = usbh_interface_find(&puhost->dev_prop, MSC_CLASS, USB_MSC_SUBCLASS_SCSI, MSC_PROTOCOL); + + if(0xFFU == interface) { + puhost->usr_cb->dev_not_supported(); + + status = USBH_FAIL; + } else { + static usbh_msc_handler msc_handler; + + memset((void *)&msc_handler, 0, sizeof(usbh_msc_handler)); + + puhost->active_class->class_data = (void *)&msc_handler; + + usbh_interface_select(&puhost->dev_prop, interface); + + usb_desc_ep *ep_desc = &puhost->dev_prop.cfg_desc_set.itf_desc_set[interface][0].ep_desc[0]; + + if(ep_desc->bEndpointAddress & 0x80) { + msc_handler.ep_in = ep_desc->bEndpointAddress; + msc_handler.ep_size_in = ep_desc->wMaxPacketSize; + } else { + msc_handler.ep_out = ep_desc->bEndpointAddress; + msc_handler.ep_size_out = ep_desc->wMaxPacketSize; + } + + ep_desc = &puhost->dev_prop.cfg_desc_set.itf_desc_set[interface][0].ep_desc[1]; + + if(ep_desc->bEndpointAddress & 0x80) { + msc_handler.ep_in = ep_desc->bEndpointAddress; + msc_handler.ep_size_in = ep_desc->wMaxPacketSize; + } else { + msc_handler.ep_out = ep_desc->bEndpointAddress; + msc_handler.ep_size_out = ep_desc->wMaxPacketSize; + } + + msc_handler.state = MSC_INIT; + msc_handler.error = MSC_OK; + msc_handler.req_state = MSC_REQ_IDLE; + msc_handler.pipe_out = usbh_pipe_allocate(puhost->data, msc_handler.ep_out); + msc_handler.pipe_in = usbh_pipe_allocate(puhost->data, msc_handler.ep_in); + + usbh_msc_bot_init(puhost); + + /* open the new channels */ + usbh_pipe_create(puhost->data, + &puhost->dev_prop, + msc_handler.pipe_out, + USB_EPTYPE_BULK, + msc_handler.ep_size_out); + + usbh_pipe_create(puhost->data, + &puhost->dev_prop, + msc_handler.pipe_in, + USB_EPTYPE_BULK, + msc_handler.ep_size_in); + + usbh_pipe_toggle_set(puhost->data, msc_handler.pipe_out, 0U); + usbh_pipe_toggle_set(puhost->data, msc_handler.pipe_in, 0U); + } + + return status; +} + +/*! + \brief de-initialize interface by freeing host channels allocated to interface + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +void usbh_msc_itf_deinit(usbh_host *puhost) +{ + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + + if(msc->pipe_out) { + usb_pipe_halt(puhost->data, msc->pipe_out); + usbh_pipe_free(puhost->data, msc->pipe_out); + + msc->pipe_out = 0U; + } + + if(msc->pipe_in) { + usb_pipe_halt(puhost->data, msc->pipe_in); + usbh_pipe_free(puhost->data, msc->pipe_in); + + msc->pipe_in = 0U; + } +} + +/*! + \brief initialize the MSC state machine + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_msc_req(usbh_host *puhost) +{ + usbh_status status = USBH_BUSY; + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + + switch(msc->req_state) { + case MSC_REQ_IDLE: + case MSC_REQ_GET_MAX_LUN: + /* issue Get_MaxLun request */ + status = usbh_msc_maxlun_get(puhost, (uint8_t *)&msc->max_lun); + + if(USBH_OK == status) { + msc->max_lun = ((uint8_t)msc->max_lun > MSC_MAX_SUPPORTED_LUN) ? MSC_MAX_SUPPORTED_LUN : (uint8_t)msc->max_lun + 1U; + + for(uint8_t i = 0U; i < msc->max_lun; i++) { + msc->unit[i].prev_ready_state = USBH_FAIL; + msc->unit[i].state_changed = 0U; + } + } else { + if(USBH_NOT_SUPPORTED == status) { + msc->max_lun = 0U; + status = USBH_OK; + } + } + break; + + case MSC_REQ_ERROR: + /* issue clear feature request */ + if(USBH_OK == usbh_clrfeature(puhost, 0x00U, puhost->control.pipe_out_num)) { + msc->req_state = msc->prev_req_state; + } + break; + + default: + break; + } + + return status; +} + +/*! + \brief MSC state machine handler + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static usbh_status usbh_msc_handle(usbh_host *puhost) +{ + usbh_status status = USBH_BUSY; + uint8_t scsi_status = USBH_BUSY; + uint8_t ready_status = USBH_BUSY; + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + + + switch(msc->state) { + case MSC_INIT: + if(msc->cur_lun < msc->max_lun) { + msc->unit[msc->cur_lun].error = MSC_NOT_READY; + + switch(msc->unit[msc->cur_lun].state) { + case MSC_INIT: + msc->unit[msc->cur_lun].state = MSC_READ_INQUIRY; + msc->timer = puhost->control.timer; + break; + + case MSC_READ_INQUIRY: + scsi_status = usbh_msc_scsi_inquiry(puhost, msc->cur_lun, &msc->unit[msc->cur_lun].inquiry); + + if(USBH_OK == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_TEST_UNIT_READY; + } else if(scsi_status == USBH_FAIL) { + msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; + } else { + if(scsi_status == USBH_UNRECOVERED_ERROR) { + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->unit[msc->cur_lun].error = MSC_ERROR; + } + } + break; + + case MSC_TEST_UNIT_READY: + /* issue SCSI command TestUnitReady */ + ready_status = usbh_msc_test_unitready(puhost, msc->cur_lun); + + if(USBH_OK == ready_status) { + if(USBH_OK != msc->unit[msc->cur_lun].prev_ready_state) { + msc->unit[msc->cur_lun].state_changed = 1U; + } else { + msc->unit[msc->cur_lun].state_changed = 0U; + } + + msc->unit[msc->cur_lun].state = MSC_READ_CAPACITY10; + msc->unit[msc->cur_lun].error = MSC_OK; + msc->unit[msc->cur_lun].prev_ready_state = USBH_OK; + } else if(USBH_FAIL == ready_status) { + if(USBH_FAIL != msc->unit[msc->cur_lun].prev_ready_state) { + msc->unit[msc->cur_lun].state_changed = 1U; + } else { + msc->unit[msc->cur_lun].state_changed = 0U; + } + + msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; + msc->unit[msc->cur_lun].error = MSC_NOT_READY; + msc->unit[msc->cur_lun].prev_ready_state = USBH_FAIL; + } else { + if(USBH_UNRECOVERED_ERROR == ready_status) { + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->unit[msc->cur_lun].error = MSC_ERROR; + } + } + break; + + case MSC_READ_CAPACITY10: + /* issue READ_CAPACITY10 SCSI command */ + scsi_status = usbh_msc_read_capacity10(puhost, msc->cur_lun, &msc->unit[msc->cur_lun].capacity); + + if(USBH_OK == scsi_status) { + if(1U == msc->unit[msc->cur_lun].state_changed) { + } + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->unit[msc->cur_lun].error = MSC_OK; + msc->cur_lun ++; + } else if(USBH_FAIL == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_REQUEST_SENSE; + } else { + if(USBH_UNRECOVERED_ERROR == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->unit[msc->cur_lun].error = MSC_ERROR; + } + } + break; + + case MSC_REQUEST_SENSE: + /* issue RequestSense SCSI command for recovering error code */ + scsi_status = usbh_msc_request_sense(puhost, msc->cur_lun, &msc->unit[msc->cur_lun].sense); + if(USBH_OK == scsi_status) { + if((msc->unit[msc->cur_lun].sense.SenseKey == UNIT_ATTENTION) || (msc->unit[msc->cur_lun].sense.SenseKey == NOT_READY)) { + if(((puhost->control.timer > msc->timer) && ((puhost->control.timer - msc->timer) < 10000U)) \ + || ((puhost->control.timer < msc->timer) && ((puhost->control.timer + 0x3FFFU - msc->timer) < 10000U))) { + msc->unit[msc->cur_lun].state = MSC_TEST_UNIT_READY; + break; + } + } + + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->cur_lun++; + } else if(USBH_FAIL == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_UNRECOVERED_ERROR; + } else { + if(MSC_UNRECOVERED_ERROR == scsi_status) { + msc->unit[msc->cur_lun].state = MSC_IDLE; + msc->unit[msc->cur_lun].error = MSC_ERROR; + } + } + break; + + case MSC_UNRECOVERED_ERROR: + msc->cur_lun ++; + break; + + default: + break; + } + } else { + msc->cur_lun = 0U; + msc->state = MSC_IDLE; + } + break; + + case MSC_IDLE: + puhost->usr_cb->dev_user_app(); + status = USBH_OK; + break; + + default: + break; + } + + return status; +} + +/*! + \brief get max lun of the mass storage device + \param[in] puhost: pointer to USB host + \param[in] maxlun: pointer to max lun + \param[out] none + \retval operation status +*/ +static usbh_status usbh_msc_maxlun_get(usbh_host *puhost, uint8_t *maxlun) +{ + usbh_status status = USBH_BUSY; + + if(puhost->control.ctl_state == CTL_IDLE) { + puhost->control.setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_REQTYPE_CLASS | USB_RECPTYPE_ITF, + .bRequest = BBB_GET_MAX_LUN, + .wValue = 0U, + .wIndex = 0U, + .wLength = 1U + }; + + usbh_ctlstate_config(puhost, maxlun, 1U); + } + + status = usbh_ctl_handler(puhost); + + return status; +} + +/*! + \brief get max lun of the mass storage device + \param[in] puhost: pointer to USB host + \param[in] lun: logic unit number + \param[out] none + \retval operation status +*/ +static usbh_status usbh_msc_rdwr_process(usbh_host *puhost, uint8_t lun) +{ + usbh_status error = USBH_BUSY; + usbh_status scsi_status = USBH_BUSY; + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + + /* switch msc req state machine */ + switch(msc->unit[lun].state) { + case MSC_READ: + scsi_status = usbh_msc_read10(puhost, lun, NULL, 0U, 0U); + + if(USBH_OK == scsi_status) { + msc->unit[lun].state = MSC_IDLE; + error = USBH_OK; + } else if(USBH_FAIL == scsi_status) { + msc->unit[lun].state = MSC_REQUEST_SENSE; + } else { + if(USBH_UNRECOVERED_ERROR == scsi_status) { + msc->unit[lun].state = MSC_UNRECOVERED_ERROR; + error = USBH_FAIL; + } + } + break; + + case MSC_WRITE: + scsi_status = usbh_msc_write10(puhost, lun, NULL, 0U, 0U); + + if(USBH_OK == scsi_status) { + msc->unit[lun].state = MSC_IDLE; + error = USBH_OK; + } else if(USBH_FAIL == scsi_status) { + msc->unit[lun].state = MSC_REQUEST_SENSE; + } else { + if(USBH_UNRECOVERED_ERROR == scsi_status) { + msc->unit[lun].state = MSC_UNRECOVERED_ERROR; + error = USBH_FAIL; + } + } + break; + + case MSC_REQUEST_SENSE: + scsi_status = usbh_msc_request_sense(puhost, lun, &msc->unit[lun].sense); + + if(USBH_OK == scsi_status) { + msc->unit[lun].state = MSC_IDLE; + msc->unit[lun].error = MSC_ERROR; + + error = USBH_FAIL; + } + + if(USBH_FAIL == scsi_status) { + } else { + if(USBH_UNRECOVERED_ERROR == scsi_status) { + msc->unit[lun].state = MSC_UNRECOVERED_ERROR; + error = USBH_FAIL; + } + } + break; + + default: + break; + } + + return error; +} + +/*! + \brief get lun information + \param[in] puhost: pointer to USB host + \param[in] lun: logic unit number + \param[in] info: pointer to lun information + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_lun_info_get(usbh_host *puhost, uint8_t lun, msc_lun *info) +{ + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + + if(HOST_CLASS_HANDLER == puhost->cur_state) { + memcpy(info, &msc->unit[lun], sizeof(msc_lun)); + + return USBH_OK; + } else { + return USBH_FAIL; + } +} + +/*! + \brief handle msc read operation + \param[in] puhost: pointer to USB host + \param[in] lun: logic unit number + \param[in] address: data address + \param[in] pbuf: pointer to data buffer + \param[in] length: buffer length + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_read(usbh_host *puhost, + uint8_t lun, + uint32_t address, + uint8_t *pbuf, + uint32_t length) +{ + uint32_t timeout = 0U; + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + usb_core_driver *pudev = (usb_core_driver *)puhost->data; + + if((0U == pudev->host.connect_status) || + (HOST_CLASS_HANDLER != puhost->cur_state) || + (MSC_IDLE != msc->unit[lun].state)) { + return USBH_FAIL; + } + + msc->state = MSC_READ; + msc->unit[lun].state = MSC_READ; + msc->rw_lun = lun; + + usbh_msc_read10(puhost, lun, pbuf, address, length); + + timeout = puhost->control.timer; + + while(USBH_BUSY == usbh_msc_rdwr_process(puhost, lun)) { + if(((puhost->control.timer > timeout) && ((puhost->control.timer - timeout) > (1000U * length))) \ + || ((puhost->control.timer < timeout) && ((puhost->control.timer + 0x3FFFU - timeout) > (1000U * length))) \ + || (0U == pudev->host.connect_status)) { + msc->state = MSC_IDLE; + return USBH_FAIL; + } + } + + msc->state = MSC_IDLE; + + return USBH_OK; +} + +/*! + \brief handle msc write operation + \param[in] puhost: pointer to USB host + \param[in] lun: logic unit number + \param[in] address: data address + \param[in] pbuf: pointer to data buffer + \param[in] length: buffer length + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_write(usbh_host *puhost, + uint8_t lun, + uint32_t address, + uint8_t *pbuf, + uint32_t length) +{ + uint32_t timeout = 0U; + usb_core_driver *pudev = (usb_core_driver *)puhost->data; + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + + if((0U == pudev->host.connect_status) || + (HOST_CLASS_HANDLER != puhost->cur_state) || + (MSC_IDLE != msc->unit[lun].state)) { + return USBH_FAIL; + } + + msc->state = MSC_WRITE; + msc->unit[lun].state = MSC_WRITE; + msc->rw_lun = lun; + + usbh_msc_write10(puhost, lun, pbuf, address, length); + + timeout = puhost->control.timer; + + while(USBH_BUSY == usbh_msc_rdwr_process(puhost, lun)) { + if(((puhost->control.timer > timeout) && ((puhost->control.timer - timeout) > (1000U * length))) \ + || ((puhost->control.timer < timeout) && ((puhost->control.timer + 0x3FFFU - timeout) > (1000U * length))) \ + || (0U == pudev->host.connect_status)) { + msc->state = MSC_IDLE; + return USBH_FAIL; + } + } + + msc->state = MSC_IDLE; + + return USBH_OK; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Source/usbh_msc_fatfs.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Source/usbh_msc_fatfs.c new file mode 100644 index 000000000..b3dd94f2b --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Source/usbh_msc_fatfs.c @@ -0,0 +1,234 @@ +/*! + \file usbh_msc_fatfs.c + \brief USB MSC host FATFS related functions + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usb_conf.h" +#include "diskio.h" +#include "usbh_msc_core.h" + +static volatile DSTATUS state = STA_NOINIT; /* disk status */ + +extern usbh_host usb_host; + +/*! + \brief initialize the disk drive + \param[in] drv: physical drive number (0) + \param[out] none + \retval operation status +*/ +DSTATUS disk_initialize(BYTE drv) +{ + usb_core_driver *pudev = (usb_core_driver *)usb_host.data; + + if(pudev->host.connect_status) { + state &= ~STA_NOINIT; + } + + return state; +} + +/*! + \brief get disk status + \param[in] drv: physical drive number (0) + \param[out] none + \retval operation status +*/ +DSTATUS disk_status(BYTE drv) +{ + if(drv) { + return STA_NOINIT; /* supports only single drive */ + } + + return state; +} + +/*! + \brief read sectors + \param[in] drv: physical drive number (0) + \param[in] buff: pointer to the data buffer to store read data + \param[in] sector: start sector number (LBA) + \param[in] count: sector count (1..255) + \param[out] none + \retval operation status +*/ +DRESULT disk_read(BYTE drv, BYTE *buff, DWORD sector, UINT count) +{ + BYTE status = USBH_OK; + usb_core_driver *pudev = (usb_core_driver *)usb_host.data; + + if(drv || (!count)) { + return RES_PARERR; + } + + if(state & STA_NOINIT) { + return RES_NOTRDY; + } + + if(pudev->host.connect_status) { + do { + status = usbh_msc_read(&usb_host, drv, sector, buff, count); + + if(!pudev->host.connect_status) { + return RES_ERROR; + } + } while(status == USBH_BUSY); + } + + if(status == USBH_OK) { + return RES_OK; + } + + return RES_ERROR; +} + +#if _READONLY == 0U + +/*! + \brief write sectors + \param[in] drv: physical drive number (0) + \param[in] buff: pointer to the data buffer to store read data + \param[in] sector: start sector number (LBA) + \param[in] count: sector count (1..255) + \param[out] none + \retval operation status +*/ +DRESULT disk_write(BYTE drv, const BYTE *buff, DWORD sector, UINT count) +{ + BYTE status = USBH_OK; + usb_core_driver *pudev = (usb_core_driver *)usb_host.data; + + if((!count) || drv) { + return RES_PARERR; + } + + if(state & STA_NOINIT) { + return RES_NOTRDY; + } + + if(state & STA_PROTECT) { + return RES_WRPRT; + } + + if(pudev->host.connect_status) { + do { + status = usbh_msc_write(&usb_host, drv, sector, (BYTE *)buff, count); + + if(!pudev->host.connect_status) { + return RES_ERROR; + } + } while(status == USBH_BUSY); + } + + if(status == USBH_OK) { + return RES_OK; + } + + return RES_ERROR; +} + +#endif /* _READONLY == 0 */ + +/*! + \brief I/O control function + \param[in] drv: physical drive number (0) + \param[in] ctrl: control code + \param[in] buff: pointer to the data buffer to store read data + \param[out] none + \retval operation status +*/ +DRESULT disk_ioctl(BYTE drv, BYTE ctrl, void *buff) +{ + DRESULT res = RES_OK; + msc_lun info; + + if(drv) { + return RES_PARERR; + } + + res = RES_ERROR; + + if(state & STA_NOINIT) { + return RES_NOTRDY; + } + + switch(ctrl) { + /* make sure that no pending write process */ + case CTRL_SYNC: + res = RES_OK; + break; + + /* get number of sectors on the disk (dword) */ + case GET_SECTOR_COUNT: + if(USBH_OK == usbh_msc_lun_info_get(&usb_host, drv, &info)) { + *(DWORD *)buff = (DWORD)info.capacity.block_nbr; + res = RES_OK; + } + break; + + /* get r/w sector size (word) */ + case GET_SECTOR_SIZE: + if(USBH_OK == usbh_msc_lun_info_get(&usb_host, drv, &info)) { + *(WORD *)buff = (DWORD)info.capacity.block_size; + res = RES_OK; + } + break; + + /* get erase block size in unit of sector (dword) */ + case GET_BLOCK_SIZE: + *(DWORD *)buff = 512; + break; + + default: + res = RES_PARERR; + break; + } + + return res; +} + +/*! + \brief get fat time + \param[in] none + \param[out] none + \retval time value +*/ +DWORD get_fattime(void) +{ + + return ((DWORD)(2019U - 1980U) << 25U) /* Year 2019 */ + | ((DWORD)1U << 21U) /* Month 1 */ + | ((DWORD)1U << 16U) /* Mday 1 */ + | ((DWORD)0U << 11U) /* Hour 0 */ + | ((DWORD)0U << 5U) /* Min 0 */ + | ((DWORD)0U >> 1U); /* Sec 0 */ +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Source/usbh_msc_scsi.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Source/usbh_msc_scsi.c new file mode 100644 index 000000000..dfb4d45a0 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/class/msc/Source/usbh_msc_scsi.c @@ -0,0 +1,397 @@ +/*! + \file usbh_msc_scsi.c + \brief USB MSC SCSI commands implemention + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_msc_core.h" +#include "usbh_msc_scsi.h" +#include "usbh_msc_bbb.h" +#include + +/*! + \brief send 'Inquiry' command to the device + \param[in] puhost: pointer to usb host handler + \param[in] lun: logic unit number + \param[in] inquiry: pointer to the inquiry structure + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_scsi_inquiry(usbh_host *puhost, uint8_t lun, scsi_std_inquiry_data *inquiry) +{ + usbh_status error = USBH_FAIL; + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + + switch(msc->bot.cmd_state) { + case BOT_CMD_SEND: + /* prepare the cbw and relevant field*/ + msc->bot.cbw.field.dCBWDataTransferLength = STANDARD_INQUIRY_DATA_LEN; + msc->bot.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + + memset(msc->bot.cbw.field.CBWCB, 0U, CBW_LENGTH); + + msc->bot.cbw.field.CBWCB[0] = SCSI_INQUIRY; + msc->bot.cbw.field.CBWCB[1] = (lun << 5U); + msc->bot.cbw.field.CBWCB[4] = 0x24U; + + msc->bot.state = BOT_SEND_CBW; + msc->bot.cmd_state = BOT_CMD_WAIT; + msc->bot.pbuf = (uint8_t *)(void *)msc->bot.data; + error = USBH_BUSY; + break; + + case BOT_CMD_WAIT: + error = usbh_msc_bot_process(puhost, lun); + + if(USBH_OK == error) { + memset(inquiry, 0U, sizeof(scsi_std_inquiry_data)); + + /* assign inquiry data */ + inquiry->device_type = msc->bot.pbuf[0] & 0x1FU; + inquiry->peripheral_qualifier = msc->bot.pbuf[0] >> 5U; + + if(0x80U == ((uint32_t)msc->bot.pbuf[1] & 0x80U)) { + inquiry->removable_media = 1U; + } else { + inquiry->removable_media = 0U; + } + + memcpy(inquiry->vendor_id, &msc->bot.pbuf[8], 8U); + memcpy(inquiry->product_id, &msc->bot.pbuf[16], 16U); + memcpy(inquiry->revision_id, &msc->bot.pbuf[32], 4U); + } + break; + + default: + break; + } + + return error; +} + +/*! + \brief send 'Test unit ready' command to the device + \param[in] puhost: pointer to USB host handler + \param[in] lun: logic unit number + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_test_unitready(usbh_host *puhost, uint8_t lun) +{ + usbh_status status = USBH_FAIL; + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + + + switch(msc->bot.cmd_state) { + case BOT_CMD_SEND: + /* prepare the CBW and relevant field */ + msc->bot.cbw.field.dCBWDataTransferLength = CBW_LENGTH_TEST_UNIT_READY; + msc->bot.cbw.field.bmCBWFlags = USB_TRX_OUT; + msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + + memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + + msc->bot.cbw.field.CBWCB[0] = SCSI_TEST_UNIT_READY; + msc->bot.state = BOT_SEND_CBW; + msc->bot.cmd_state = BOT_CMD_WAIT; + + status = USBH_BUSY; + break; + + case BOT_CMD_WAIT: + status = usbh_msc_bot_process(puhost, lun); + break; + + default: + break; + } + + return status; +} + +/*! + \brief send the read capacity command to the device + \param[in] puhost: pointer to usb host handler + \param[in] lun: logic unit number + \param[in] capacity: pointer to scsi capacity + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_read_capacity10(usbh_host *puhost, uint8_t lun, scsi_capacity *capacity) +{ + usbh_status status = USBH_FAIL; + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + + switch(msc->bot.cmd_state) { + case BOT_CMD_SEND: + /* prepare the CBW and relevant field */ + msc->bot.cbw.field.dCBWDataTransferLength = READ_CAPACITY10_DATA_LEN; + msc->bot.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + + memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + + msc->bot.cbw.field.CBWCB[0] = SCSI_READ_CAPACITY10; + msc->bot.state = BOT_SEND_CBW; + msc->bot.cmd_state = BOT_CMD_WAIT; + msc->bot.pbuf = (uint8_t *)(void *)msc->bot.data; + + status = USBH_BUSY; + break; + + case BOT_CMD_WAIT: + status = usbh_msc_bot_process(puhost, lun); + + if(USBH_OK == status) { + capacity->block_nbr = msc->bot.pbuf[3] | \ + ((uint32_t)msc->bot.pbuf[2] << 8U) | \ + ((uint32_t)msc->bot.pbuf[1] << 16U) | \ + ((uint32_t)msc->bot.pbuf[0] << 24U); + + capacity->block_size = (uint16_t)(msc->bot.pbuf[7] | ((uint32_t)msc->bot.pbuf[6] << 8U)); + } + break; + + default: + break; + } + + return status; +} + +/*! + \brief send the mode sense6 command to the device + \param[in] puhost: pointer to usb host handler + \param[in] lun: logic unit number + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_mode_sense6(usbh_host *puhost, uint8_t lun) +{ + usbh_status status = USBH_FAIL; + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + + switch(msc->bot.cmd_state) { + case BOT_CMD_SEND: + /* prepare the CBW and relevant field */ + msc->bot.cbw.field.dCBWDataTransferLength = XFER_LEN_MODE_SENSE6; + msc->bot.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + + memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + + msc->bot.cbw.field.CBWCB[0] = SCSI_MODE_SENSE6; + msc->bot.cbw.field.CBWCB[2] = MODE_SENSE_PAGE_CONTROL_FIELD | MODE_SENSE_PAGE_CODE; + msc->bot.cbw.field.CBWCB[4] = XFER_LEN_MODE_SENSE6; + msc->bot.state = BOT_SEND_CBW; + msc->bot.cmd_state = BOT_CMD_WAIT; + msc->bot.pbuf = (uint8_t *)(void *)msc->bot.data; + + status = USBH_BUSY; + break; + + case BOT_CMD_WAIT: + status = usbh_msc_bot_process(puhost, lun); + + if(USBH_OK == status) { + if(msc->bot.data[2] & MASK_MODE_SENSE_WRITE_PROTECT) { + + } else { + + } + } + break; + + default: + break; + } + + return status; +} + +/*! + \brief send the Request Sense command to the device + \param[in] puhost: pointer to usb host handler + \param[in] lun: logic unit number + \param[in] sense_data: pointer to sense data + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_request_sense(usbh_host *puhost, uint8_t lun, msc_scsi_sense *sense_data) +{ + usbh_status status = USBH_FAIL; + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + + switch(msc->bot.cmd_state) { + case BOT_CMD_SEND: + /* prepare the cbw and relevant field */ + msc->bot.cbw.field.dCBWDataTransferLength = ALLOCATION_LENGTH_REQUEST_SENSE; + msc->bot.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + + memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + + msc->bot.cbw.field.CBWCB[0] = SCSI_REQUEST_SENSE; + msc->bot.cbw.field.CBWCB[1] = (lun << 5U); + msc->bot.cbw.field.CBWCB[4] = ALLOCATION_LENGTH_REQUEST_SENSE; + + msc->bot.state = BOT_SEND_CBW; + msc->bot.cmd_state = BOT_CMD_WAIT; + msc->bot.pbuf = (uint8_t *)(void *)msc->bot.data; + + status = USBH_BUSY; + break; + + case BOT_CMD_WAIT: + status = usbh_msc_bot_process(puhost, lun); + + if(status == USBH_OK) { + /* get sense data */ + sense_data->SenseKey = msc->bot.pbuf[2] & 0x0FU; + sense_data->ASC = msc->bot.pbuf[12]; + sense_data->ASCQ = msc->bot.pbuf[13]; + } + break; + + default: + break; + } + + return status; +} + +/*! + \brief send the write10 command to the device + \param[in] puhost: pointer to usb host handler + \param[in] lun: logic unit number + \param[in] data_buf: data buffer contains the data to write + \param[in] addr: address to which the data will be written + \param[in] sector_num: number of sector to be written + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_write10(usbh_host *puhost, uint8_t lun, uint8_t *data_buf, uint32_t addr, uint32_t sector_num) +{ + usbh_status status = USBH_FAIL; + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + + switch(msc->bot.cmd_state) { + case BOT_CMD_SEND: + msc->bot.cbw.field.dCBWDataTransferLength = sector_num * msc->unit[lun].capacity.block_size; + msc->bot.cbw.field.bmCBWFlags = USB_TRX_OUT; + msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + + memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + + msc->bot.cbw.field.CBWCB[0] = SCSI_WRITE10; + + /* logical block address */ + msc->bot.cbw.field.CBWCB[2] = (((uint8_t *)&addr)[3]); + msc->bot.cbw.field.CBWCB[3] = (((uint8_t *)&addr)[2]); + msc->bot.cbw.field.CBWCB[4] = (((uint8_t *)&addr)[1]); + msc->bot.cbw.field.CBWCB[5] = (((uint8_t *)&addr)[0]); + + /* transfer length */ + msc->bot.cbw.field.CBWCB[7] = (((uint8_t *)§or_num)[1]); + msc->bot.cbw.field.CBWCB[8] = (((uint8_t *)§or_num)[0]); + + msc->bot.state = BOT_SEND_CBW; + msc->bot.cmd_state = BOT_CMD_WAIT; + msc->bot.pbuf = data_buf; + + status = USBH_BUSY; + break; + + case BOT_CMD_WAIT: + status = usbh_msc_bot_process(puhost, lun); + break; + + default: + break; + } + + return status; +} + +/*! + \brief send the read10 command to the device + \param[in] puhost: pointer to usb host handler + \param[in] lun: logic unit number + \param[in] data_buf: data buffer contains the data to write + \param[in] addr: address to which the data will be read + \param[in] sector_num: number of sector to be read + \param[out] none + \retval operation status +*/ +usbh_status usbh_msc_read10(usbh_host *puhost, uint8_t lun, uint8_t *data_buf, uint32_t addr, uint32_t sector_num) +{ + usbh_status status = USBH_FAIL; + usbh_msc_handler *msc = (usbh_msc_handler *)puhost->active_class->class_data; + + switch(msc->bot.cmd_state) { + case BOT_CMD_SEND: + /* prepare the CBW and relevant field */ + msc->bot.cbw.field.dCBWDataTransferLength = sector_num * msc->unit[lun].capacity.block_size; + msc->bot.cbw.field.bmCBWFlags = USB_TRX_IN; + msc->bot.cbw.field.bCBWCBLength = CBW_LENGTH; + + memset(msc->bot.cbw.field.CBWCB, 0U, CBW_CB_LENGTH); + + msc->bot.cbw.field.CBWCB[0] = SCSI_READ10; + + /* logical block address */ + msc->bot.cbw.field.CBWCB[2] = (((uint8_t *)&addr)[3]); + msc->bot.cbw.field.CBWCB[3] = (((uint8_t *)&addr)[2]); + msc->bot.cbw.field.CBWCB[4] = (((uint8_t *)&addr)[1]); + msc->bot.cbw.field.CBWCB[5] = (((uint8_t *)&addr)[0]); + + /* transfer length */ + msc->bot.cbw.field.CBWCB[7] = (((uint8_t *)§or_num)[1]); + msc->bot.cbw.field.CBWCB[8] = (((uint8_t *)§or_num)[0]); + + msc->bot.state = BOT_SEND_CBW; + msc->bot.cmd_state = BOT_CMD_WAIT; + msc->bot.pbuf = data_buf; + + status = USBH_BUSY; + break; + + case BOT_CMD_WAIT: + status = usbh_msc_bot_process(puhost, lun); + break; + + default: + break; + } + + return status; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Include/usbh_core.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Include/usbh_core.h new file mode 100644 index 000000000..7dc5a0223 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Include/usbh_core.h @@ -0,0 +1,267 @@ +/*! + \file usbh_core.h + \brief USB host core state machine header file + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_CORE_H +#define __USBH_CORE_H + +#include "usbh_conf.h" +#include "drv_usb_host.h" + +#define MSC_CLASS 0x08U +#define HID_CLASS 0x03U +#define MSC_PROTOCOL 0x50U +#define CBI_PROTOCOL 0x01U + +#define USBH_MAX_ERROR_COUNT 3U + +#define USBH_DEV_ADDR_DEFAULT 0U +#define USBH_DEV_ADDR 1U + +typedef enum { + USBH_OK = 0U, + USBH_BUSY, + USBH_FAIL, + USBH_NOT_SUPPORTED, + USBH_UNRECOVERED_ERROR, + USBH_SPEED_UNKNOWN_ERROR, + USBH_APPLY_DEINIT +} usbh_status; + +/* USB host global operation state */ +typedef enum { + HOST_DEFAULT = 0U, + HOST_DETECT_DEV_SPEED, + HOST_DEV_ATTACHED, + HOST_DEV_DETACHED, + HOST_ENUM, + HOST_SET_WAKEUP_FEATURE, + HOST_CHECK_CLASS, + HOST_CLASS_ENUM, + HOST_CLASS_HANDLER, + HOST_USER_INPUT, + HOST_SUSPENDED, + HOST_WAKEUP, + HOST_ERROR +} usb_host_state; + +/* USB host enumeration state */ +typedef enum { + ENUM_DEFAULT = 0U, + ENUM_GET_DEV_DESC, + ENUM_SET_ADDR, + ENUM_GET_CFG_DESC, + ENUM_GET_CFG_DESC_SET, + ENUM_GET_STR_DESC, +#ifdef USB_MTP + ENUM_GET_MTP_STR, +#endif + ENUM_SET_CONFIGURATION, + ENUM_DEV_CONFIGURED +} usbh_enum_state; + +/* USB host control transfer state */ +typedef enum { + CTL_IDLE = 0U, + CTL_SETUP, + CTL_SETUP_WAIT, + CTL_DATA_IN, + CTL_DATA_IN_WAIT, + CTL_DATA_OUT, + CTL_DATA_OUT_WAIT, + CTL_STATUS_IN, + CTL_STATUS_IN_WAIT, + CTL_STATUS_OUT, + CTL_STATUS_OUT_WAIT, + CTL_ERROR, + CTL_FINISH +} usbh_ctl_state; + +/* user action state */ +typedef enum { + USBH_USER_NO_RESP = 0U, + USBH_USER_RESP_OK = 1U, +} usbh_user_status; + +typedef enum { + USBH_PORT_EVENT = 1U, + USBH_URB_EVENT, + USBH_CONTROL_EVENT, + USBH_CLASS_EVENT, + USBH_STATE_CHANGED_EVENT, +} usbh_os_event; + +/* control transfer information */ +typedef struct _usbh_control { + uint8_t pipe_in_num; + uint8_t pipe_out_num; + uint8_t max_len; + uint8_t error_count; + + uint8_t *buf; + uint16_t ctl_len; + uint16_t timer; + + usb_setup setup; + usbh_ctl_state ctl_state; +} usbh_control; + +/* USB interface descriptor set */ +typedef struct _usb_desc_itf_set { + usb_desc_itf itf_desc; + usb_desc_ep ep_desc[USBH_MAX_EP_NUM]; +} usb_desc_itf_set; + +/* USB configure descriptor set */ +typedef struct _usb_desc_cfg_set { + usb_desc_config cfg_desc; + usb_desc_itf_set itf_desc_set[USBH_MAX_INTERFACES_NUM][USBH_MAX_ALT_SETTING]; +} usb_desc_cfg_set; + +/* USB device property */ +typedef struct { + uint8_t data[USBH_DATA_BUF_MAX_LEN]; /* if DMA is used, the data array must be located in the first position */ + uint8_t cur_itf; + uint8_t addr; + + uint32_t speed; + + usb_desc_dev dev_desc; + usb_desc_cfg_set cfg_desc_set; + +#if (USBH_KEEP_CFG_DESCRIPTOR == 1U) + uint8_t cfgdesc_rawdata[USBH_CFGSET_MAX_LEN]; +#endif /* (USBH_KEEP_CFG_DESCRIPTOR == 1U) */ +} usb_dev_prop; + +struct _usbh_host; + +/* device class callbacks */ +typedef struct { + uint8_t class_code; /*!< USB class type */ + + usbh_status(*class_init)(struct _usbh_host *phost); + void (*class_deinit)(struct _usbh_host *phost); + usbh_status(*class_requests)(struct _usbh_host *phost); + usbh_status(*class_machine)(struct _usbh_host *phost); + usbh_status(*class_sof)(struct _usbh_host *puhost); + + void *class_data; +} usbh_class; + +/* user callbacks */ +typedef struct { + void (*dev_init)(void); + void (*dev_deinit)(void); + void (*dev_attach)(void); + void (*dev_reset)(void); + void (*dev_detach)(void); + void (*dev_over_currented)(void); + void (*dev_speed_detected)(uint32_t dev_speed); + void (*dev_devdesc_assigned)(void *dev_desc); + void (*dev_address_set)(void); + + void (*dev_cfgdesc_assigned)(usb_desc_config *cfg_desc, + usb_desc_itf *itf_desc, + usb_desc_ep *ep_desc); + + void (*dev_mfc_str)(void *mfc_str); + void (*dev_prod_str)(void *prod_str); + void (*dev_seral_str)(void *serial_str); + void (*dev_enumerated)(void); + usbh_user_status(*dev_user_input)(void); + int (*dev_user_app)(void); + void (*dev_not_supported)(void); + void (*dev_error)(void); +} usbh_user_cb; + +/* host information */ +typedef struct _usbh_host { + usb_host_state cur_state; /*!< host state machine value */ + usb_host_state backup_state; /*!< backup of previous state machine value */ + usbh_enum_state enum_state; /*!< enumeration state machine */ + usbh_control control; /*!< USB host control state machine */ + usb_dev_prop dev_prop; /*!< USB device property */ + + usbh_class *uclass[USBH_MAX_SUPPORTED_CLASS]; /*!< USB host supported class */ + usbh_class *active_class; /*!< USB active class */ + usbh_user_cb *usr_cb; /*!< USB user callback */ + + uint8_t class_num; /*!< USB class number */ + + void *data; /*!< used for... */ + +#if USB_LOW_POWER + uint8_t suspend_flag; /*!< host suspend flag */ + uint8_t dev_supp_remote_wkup; /*!< record device remote wakeup function */ + uint8_t wakeup_mode; /*!< record wakeup mode */ +#endif /* USB_LOW_POWER*/ +} usbh_host; + +/*! + \brief get USB URB state + \param[in] pudev: pointer to USB core instance + \param[in] pp_num: pipe number + \param[out] none + \retval none +*/ +static inline usb_urb_state usbh_urbstate_get(usb_core_driver *pudev, uint8_t pp_num) +{ + return pudev->host.pipe[pp_num].urb_state; +} + +/*! + \brief get USB transfer data count + \param[in] pudev: pointer to USB core instance + \param[in] pp_num: pipe number + \param[out] none + \retval none +*/ +static inline uint32_t usbh_xfercount_get(usb_core_driver *pudev, uint8_t pp_num) +{ + return pudev->host.backup_xfercount[pp_num]; +} + +/* function declarations */ +/* USB host stack initializations */ +void usbh_init(usbh_host *puhost, usbh_user_cb *user_cb); +/* USB host register device class */ +usbh_status usbh_class_register(usbh_host *puhost, usbh_class *puclass); +/* de-initialize USB host */ +usbh_status usbh_deinit(usbh_host *puhost); +/* USB host core main state machine process */ +void usbh_core_task(usbh_host *puhost); +/* handle the error on USB host side */ +void usbh_error_handler(usbh_host *puhost, usbh_status err_type); + +#endif /* __USBH_CORE_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Include/usbh_enum.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Include/usbh_enum.h new file mode 100644 index 000000000..95a850c4c --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Include/usbh_enum.h @@ -0,0 +1,71 @@ +/*! + \file usbh_enum.h + \brief USB host mode USB enumeration header file + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_ENUM_H +#define __USBH_ENUM_H + +#include "usb_conf.h" +#include "usbh_core.h" + +/* function declarations */ +/* configure USB control status parameters */ +void usbh_ctlstate_config(usbh_host *puhost, uint8_t *buf, uint16_t len); +/* get device descriptor from the USB device */ +usbh_status usbh_devdesc_get(usbh_host *puhost, uint8_t len); +/* get configuration descriptor from the USB device */ +usbh_status usbh_cfgdesc_get(usbh_host *puhost, uint16_t len); +/* get string descriptor from the USB device */ +usbh_status usbh_strdesc_get(usbh_host *puhost, uint8_t str_index, uint8_t *buf, uint16_t len); +/* set the address to the connected device */ +usbh_status usbh_setaddress(usbh_host *puhost, uint8_t dev_addr); +/* set the configuration value to the connected device */ +usbh_status usbh_setcfg(usbh_host *puhost, uint16_t config); +/* set the interface value to the connected device */ +usbh_status usbh_setinterface(usbh_host *puhost, uint8_t itf_num, uint8_t alter_setting); +/* set or enable a specific device feature */ +usbh_status usbh_setdevfeature(usbh_host *puhost, uint8_t feature_selector, uint16_t windex); +/* clear or disable a specific device feature */ +usbh_status usbh_clrdevfeature(usbh_host *puhost, uint8_t feature_selector, uint16_t windex); +/* clear or disable a specific feature */ +usbh_status usbh_clrfeature(usbh_host *puhost, uint8_t ep_addr, uint8_t pp_num); +/* get the next descriptor header */ +usb_desc_header *usbh_nextdesc_get(uint8_t *pbuf, uint16_t *ptr); +/* select an interface */ +usbh_status usbh_interface_select(usb_dev_prop *udev, uint8_t interface); +/* find the interface index for a specific class */ +uint8_t usbh_interface_find(usb_dev_prop *udev, uint8_t main_class, uint8_t sub_class, uint8_t protocol); +/* find the interface index for a specific class interface and alternate setting number */ +uint8_t usbh_interfaceindex_find(usb_dev_prop *udev, uint8_t interface_number, uint8_t alt_settings); + +#endif /* __USBH_ENUM_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Include/usbh_pipe.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Include/usbh_pipe.h new file mode 100644 index 000000000..0803db248 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Include/usbh_pipe.h @@ -0,0 +1,100 @@ +/*! + \file usbh_pipe.h + \brief USB host mode pipe header file + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_PIPE_H +#define __USBH_PIPE_H + +#include "usbh_core.h" + +#define HC_MAX 8U + +#define HC_OK 0x0000U +#define HC_USED 0x8000U +#define HC_ERROR 0xFFFFU +#define HC_USED_MASK 0x7FFFU + +/*! + \brief set toggle for a pipe + \param[in] pudev: pointer to USB core instance + \param[in] pp_num: pipe number + \param[in] toggle: toggle (0/1) + \param[out] none + \retval operation status +*/ +__STATIC_INLINE void usbh_pipe_toggle_set(usb_core_driver *pudev, uint8_t pp_num, uint8_t toggle) +{ + if(pudev->host.pipe[pp_num].ep.dir) { + pudev->host.pipe[pp_num].data_toggle_in = toggle; + } else { + pudev->host.pipe[pp_num].data_toggle_out = toggle; + } +} + +/*! + \brief get toggle flag of pipe + \param[in] pudev: pointer to USB core instance + \param[in] pp_num: pipe number + \param[out] none + \retval operation status +*/ +__STATIC_INLINE uint8_t usbh_pipe_toggle_get(usb_core_driver *pudev, uint8_t pp_num) +{ + if(pudev->host.pipe[pp_num].ep.dir) { + return pudev->host.pipe[pp_num].data_toggle_in; + } else { + return pudev->host.pipe[pp_num].data_toggle_out; + } +} + +/* function declarations */ +/* create a pipe */ +uint8_t usbh_pipe_create(usb_core_driver *pudev, + usb_dev_prop *udev, + uint8_t pp_num, + uint8_t ep_type, + uint16_t ep_mpl); +/* modify a pipe */ +uint8_t usbh_pipe_update(usb_core_driver *pudev, + uint8_t pp_num, + uint8_t dev_addr, + uint32_t dev_speed, + uint16_t ep_mpl); +/* allocate a new pipe */ +uint8_t usbh_pipe_allocate(usb_core_driver *pudev, uint8_t ep_addr); +/* free a pipe */ +uint8_t usbh_pipe_free(usb_core_driver *pudev, uint8_t pp_num); +/* delete all USB host pipe */ +uint8_t usbh_pipe_delete(usb_core_driver *pudev); + +#endif /* __USBH_PIPE_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Include/usbh_transc.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Include/usbh_transc.h new file mode 100644 index 000000000..6fe09dd3d --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Include/usbh_transc.h @@ -0,0 +1,51 @@ +/*! + \file usbh_transc.h + \brief USB host mode transactions header file + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USBH_TRANSC_H +#define __USBH_TRANSC_H + +#include "usb_conf.h" +#include "usbh_core.h" + +/* function declarations */ +/* send the setup packet to the USB device */ +usbh_status usbh_ctlsetup_send(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num); +/* send a data packet to the USB device */ +usbh_status usbh_data_send(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len); +/* receive a data packet from the USB device */ +usbh_status usbh_data_recev(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len); +/* USB control transfer handler */ +usbh_status usbh_ctl_handler(usbh_host *puhost); + +#endif /* __USBH_TRANSC_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Source/usbh_core.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Source/usbh_core.c new file mode 100644 index 000000000..c01464d6c --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Source/usbh_core.c @@ -0,0 +1,684 @@ +/*! + \file usbh_core.c + \brief USB host core state machine driver + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "usbh_pipe.h" +#include "usbh_enum.h" +#include "usbh_core.h" +#include "drv_usbh_int.h" +#include + +usb_core_driver usbh_core; + +/* local function prototypes ('static') */ +static uint8_t usbh_sof(usbh_host *puhost); +static uint8_t usbh_connect(usbh_host *puhost); +static uint8_t usbh_disconnect(usbh_host *puhost); +static uint8_t usbh_port_enabled(usbh_host *puhost); +static uint8_t usbh_port_disabled(usbh_host *puhost); +static usbh_status usbh_enum_task(usbh_host *puhost); + +#if USB_LOW_POWER +static void usb_hwp_suspend(usb_core_driver *udev); +static void usb_hwp_resume(usb_core_driver *udev); +#endif /* USB_LOW_POWER */ + +usbh_int_cb usbh_int_op = { + usbh_connect, + usbh_disconnect, + usbh_port_enabled, + usbh_port_disabled, + usbh_sof +}; + +usbh_int_cb *usbh_int_fop = &usbh_int_op; + +/*! + \brief USB host stack initializations + \param[in] puhost: pointer to USB host + \param[in] user_cb: pointer to user callback + \param[out] none + \retval none +*/ +void usbh_init(usbh_host *puhost, usbh_user_cb *user_cb) +{ + /* host de-initializations */ + usbh_deinit(puhost); + + puhost->usr_cb = user_cb; + + usbh_core.host.connect_status = 0U; + + for(uint8_t i = 0U; i < USBFS_MAX_TX_FIFOS; i++) { + usbh_core.host.pipe[i].err_count = 0U; + usbh_core.host.pipe[i].pp_status = PIPE_IDLE; + usbh_core.host.backup_xfercount[i] = 0U; + } + + usbh_core.host.pipe[0].ep.mps = 8U; + +#ifdef USE_USB_FS + usb_basic_init(&usbh_core.bp, &usbh_core.regs, USB_CORE_ENUM_FS); +#endif /* USE_USB_FS */ + +#ifndef DUAL_ROLE_MODE_ENABLED + usb_globalint_disable(&usbh_core.regs); + + usb_core_init(usbh_core.bp, &usbh_core.regs); + +#ifndef USE_OTG_MODE + usb_curmode_set(&usbh_core.regs, HOST_MODE); +#endif /* USE_OTG_MODE */ + + usb_host_init(&usbh_core); + + usb_globalint_enable(&usbh_core.regs); +#endif /* DUAL_ROLE_MODE_ENABLED */ + + /* link driver to the stack */ + usbh_core.host.data = (void *)puhost; + puhost->data = (void *)&usbh_core; + + /* upon init call usr call back */ + puhost->usr_cb->dev_init(); +} + +/*! + \brief USB host register device class + \param[in] puhost: pointer to usb host instance + \param[in] puclass: pointer to USB device class + \param[out] none + \retval operation status +*/ +usbh_status usbh_class_register(usbh_host *puhost, usbh_class *puclass) +{ + usbh_status status = USBH_OK; + + if(NULL != puclass) { + if(puhost->class_num < USBH_MAX_SUPPORTED_CLASS) { + puhost->uclass[puhost->class_num++] = puclass; + } else { + status = USBH_FAIL; + } + } else { + status = USBH_FAIL; + } + + return status; +} + +/*! + \brief de-initialize USB host + \param[in] puhost: pointer to USB host + \param[out] none + \retval operation status +*/ +usbh_status usbh_deinit(usbh_host *puhost) +{ + /* software init */ + puhost->cur_state = HOST_DEFAULT; + puhost->backup_state = HOST_DEFAULT; + puhost->enum_state = ENUM_DEFAULT; + + puhost->control.ctl_state = CTL_IDLE; + puhost->control.max_len = USB_FS_EP0_MAX_LEN; + + puhost->dev_prop.addr = USBH_DEV_ADDR_DEFAULT; + puhost->dev_prop.speed = PORT_SPEED_FULL; + puhost->dev_prop.cur_itf = 0xFFU; + + usbh_pipe_free(&usbh_core, puhost->control.pipe_in_num); + usbh_pipe_free(&usbh_core, puhost->control.pipe_out_num); + + return USBH_OK; +} + +/*! + \brief USB host core main state machine process + \param[in] puhost: pointer to USB host + \param[out] none + \retval none +*/ +void usbh_core_task(usbh_host *puhost) +{ + volatile usbh_status status = USBH_FAIL; + + /* check for host port events */ + if(((0U == usbh_core.host.connect_status) || (0U == usbh_core.host.port_enabled)) && (HOST_DEFAULT != puhost->cur_state)) { + if(puhost->cur_state != HOST_DEV_DETACHED) { + puhost->cur_state = HOST_DEV_DETACHED; + } + } + + switch(puhost->cur_state) { + case HOST_DEFAULT: + if(usbh_core.host.connect_status) { + puhost->cur_state = HOST_DETECT_DEV_SPEED; + + usb_mdelay(100U); + + usb_port_reset(&usbh_core); + + puhost->usr_cb->dev_reset(); + } + break; + + case HOST_DETECT_DEV_SPEED: + if(usbh_core.host.port_enabled) { + puhost->cur_state = HOST_DEV_ATTACHED; + + puhost->dev_prop.speed = usb_curspeed_get(&usbh_core); + + puhost->usr_cb->dev_speed_detected(puhost->dev_prop.speed); + + usb_mdelay(50U); + } + break; + + case HOST_DEV_ATTACHED: + puhost->usr_cb->dev_attach(); + puhost->control.pipe_out_num = usbh_pipe_allocate(&usbh_core, 0x00U); + puhost->control.pipe_in_num = usbh_pipe_allocate(&usbh_core, 0x80U); + + /* open IN control pipe */ + usbh_pipe_create(&usbh_core, + &puhost->dev_prop, + puhost->control.pipe_in_num, + USB_EPTYPE_CTRL, + (uint16_t)puhost->control.max_len); + + /* open OUT control pipe */ + usbh_pipe_create(&usbh_core, + &puhost->dev_prop, + puhost->control.pipe_out_num, + USB_EPTYPE_CTRL, + (uint16_t)puhost->control.max_len); + + puhost->cur_state = HOST_ENUM; + break; + + case HOST_ENUM: + /* check for enumeration status */ + if(USBH_OK == usbh_enum_task(puhost)) { + /* the function shall return USBH_OK when full enumeration is complete */ + + /* user callback for end of device basic enumeration */ + puhost->usr_cb->dev_enumerated(); + +#if USB_LOW_POWER + puhost->cur_state = HOST_SUSPENDED; + + /* judge device remote wakup function */ + if((puhost->dev_prop.cfg_desc_set.cfg_desc.bmAttributes) & (1U << 5)) { + puhost->dev_supp_remote_wkup = 1; + } else { + puhost->dev_supp_remote_wkup = 0; + } +#else + puhost->cur_state = HOST_SET_WAKEUP_FEATURE; +#endif /* USB_LOW_POWER */ + } + break; + + case HOST_SET_WAKEUP_FEATURE: + if((puhost->dev_prop.cfg_desc_set.cfg_desc.bmAttributes) & (1U << 5)) { + if(usbh_setdevfeature(puhost, FEATURE_SELECTOR_REMOTEWAKEUP, 0U) == USBH_OK) { + puhost->cur_state = HOST_CHECK_CLASS; + } + } else { + puhost->cur_state = HOST_CHECK_CLASS; + } + break; + + case HOST_CHECK_CLASS: + if(puhost->class_num == 0U) { + puhost->cur_state = HOST_ERROR; + } else { + puhost->active_class = NULL; + + uint8_t itf_class = puhost->dev_prop.cfg_desc_set.itf_desc_set[0][0].itf_desc.bInterfaceClass; + + for(uint8_t index = 0U; index < puhost->class_num; index++) { + if((puhost->uclass[index]->class_code == itf_class) || (0xFFU == itf_class)) { + puhost->active_class = puhost->uclass[index]; + } + } + + if(puhost->active_class != NULL) { + puhost->cur_state = HOST_USER_INPUT; + } else { + puhost->cur_state = HOST_ERROR; + } + } + break; + + case HOST_USER_INPUT: + /* the function should return user response true to move to class state */ + if(USBH_USER_RESP_OK == puhost->usr_cb->dev_user_input()) { + if((USBH_OK == puhost->active_class->class_init(puhost))) { + puhost->cur_state = HOST_CLASS_ENUM; + } + } + break; + +#if USB_LOW_POWER + case HOST_SUSPENDED: + if(puhost->dev_supp_remote_wkup) { + /* send set feature command*/ + if(USBH_OK == usbh_setdevfeature(puhost, FEATURE_SELECTOR_REMOTEWAKEUP, 0U)) { + + usb_hwp_suspend(&usbh_core); + + usb_mdelay(20U); + puhost->suspend_flag = 1; + puhost->usr_cb->dev_user_input(); + + /* MCU enter deep-sleep*/ + pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD); + puhost->cur_state = HOST_WAKEUP; + } + } else { + /* host suspend */ + usb_hwp_suspend(&usbh_core); + + usb_mdelay(20U); + puhost->suspend_flag = 1U; + puhost->usr_cb->dev_user_input(); + + /* MCU enter deep-sleep */ + pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, PMU_LOWDRIVER_DISABLE, WFI_CMD); + puhost->cur_state = HOST_WAKEUP; + } + break; + + case HOST_WAKEUP: + /* judge suspend status */ + if(0 == puhost->suspend_flag) { + usb_hwp_resume(&usbh_core); + usb_mdelay(500U); + + if(puhost->dev_supp_remote_wkup) { + if(USBH_OK == usbh_clrdevfeature(puhost, FEATURE_SELECTOR_DEV, 0U)) { + /* user callback for initialization */ + puhost->usr_cb->dev_init(); + puhost->cur_state = HOST_CHECK_CLASS; + } + } else { + puhost->cur_state = HOST_CHECK_CLASS; + } + } + break; +#endif /* USB_LOW_POWER */ + + case HOST_CLASS_ENUM: + /* process class standard contol requests state machine */ + status = puhost->active_class->class_requests(puhost); + + if(USBH_OK == status) { + puhost->cur_state = HOST_CLASS_HANDLER; + } else { + usbh_error_handler(puhost, status); + } + break; + + case HOST_CLASS_HANDLER: + /* process class state machine */ + status = puhost->active_class->class_machine(puhost); + + usbh_error_handler(puhost, status); + break; + + case HOST_ERROR: + /* re-initilaize host for new enumeration */ + usbh_deinit(puhost); + puhost->usr_cb->dev_deinit(); + puhost->active_class->class_deinit(puhost); + break; + + case HOST_DEV_DETACHED: + /* manage user disconnect operations*/ + puhost->usr_cb->dev_detach(); + + /* re-initilaize host for new enumeration */ + usbh_deinit(puhost); + puhost->usr_cb->dev_deinit(); + puhost->active_class->class_deinit(puhost); + usbh_pipe_delete(&usbh_core); + puhost->cur_state = HOST_DEFAULT; + break; + + default: + break; + } +} + +/*! + \brief handle the error on USB host side + \param[in] puhost: pointer to USB host + \param[in] err_type: type of error or busy/OK state + \param[out] none + \retval none +*/ +void usbh_error_handler(usbh_host *puhost, usbh_status err_type) +{ + /* error unrecovered or not supported device speed */ + if((USBH_SPEED_UNKNOWN_ERROR == err_type) || (USBH_UNRECOVERED_ERROR == err_type)) { + puhost->usr_cb->dev_error(); + + puhost->cur_state = HOST_ERROR; + } else if(USBH_APPLY_DEINIT == err_type) { + puhost->cur_state = HOST_ERROR; + + /* user callback for initalization */ + puhost->usr_cb->dev_init(); + } else { + /* no operation */ + } +} + +/*! + \brief USB SOF callback function from the interrupt + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static uint8_t usbh_sof(usbh_host *puhost) +{ + /* this callback could be used to implement a scheduler process */ + puhost->control.timer = (uint16_t)usb_curframe_get(&usbh_core); + + if(puhost->active_class != NULL) { + if(puhost->active_class->class_sof != NULL) { + puhost->active_class->class_sof(puhost); + } + } + + return 0U; +} + +/*! + \brief USB connect callback function from the interrupt + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static uint8_t usbh_connect(usbh_host *puhost) +{ + usbh_core.host.connect_status = 1U; + + return 0U; +} + +/*! + \brief USB disconnect callback function from the interrupt + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static uint8_t usbh_disconnect(usbh_host *puhost) +{ + usbh_core.host.connect_status = 0U; + + return 0U; +} + +/*! + \brief USB port enable callback function from the interrupt + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static uint8_t usbh_port_enabled(usbh_host *puhost) +{ + usbh_core.host.port_enabled = 1U; + + return 0U; +} + +/*! + \brief USB port disabled callback function from the interrupt + \param[in] puhost: pointer to usb host + \param[out] none + \retval operation status +*/ +static uint8_t usbh_port_disabled(usbh_host *puhost) +{ + usbh_core.host.port_enabled = 0U; + + return 0U; +} + +/*! + \brief handle the USB enumeration task + \param[in] puhost: pointer to host + \param[out] none + \retval none +*/ +static usbh_status usbh_enum_task(usbh_host *puhost) +{ + uint8_t str_buf[512]; + + usbh_status status = USBH_BUSY; + + static uint8_t index_mfc_str = 0U, index_prod_str = 0U, index_serial_str = 0U; + + switch(puhost->enum_state) { + case ENUM_DEFAULT: + /* get device descriptor for only 1st 8 bytes : to get ep0 maxpacketsize */ + if(USBH_OK == usbh_devdesc_get(puhost, 8U)) { + puhost->control.max_len = puhost->dev_prop.dev_desc.bMaxPacketSize0; + + /* modify control channels configuration for maximum packet size */ + usbh_pipe_update(&usbh_core, + puhost->control.pipe_out_num, + 0U, 0U, + (uint16_t)puhost->control.max_len); + + usbh_pipe_update(&usbh_core, + puhost->control.pipe_in_num, + 0U, 0U, + (uint16_t)puhost->control.max_len); + + puhost->enum_state = ENUM_GET_DEV_DESC; + } + break; + + case ENUM_GET_DEV_DESC: + /* get full device descriptor */ + if(USBH_OK == usbh_devdesc_get(puhost, USB_DEV_DESC_LEN)) { + puhost->usr_cb->dev_devdesc_assigned(&puhost->dev_prop.dev_desc); + + index_mfc_str = puhost->dev_prop.dev_desc.iManufacturer; + index_prod_str = puhost->dev_prop.dev_desc.iProduct; + index_serial_str = puhost->dev_prop.dev_desc.iSerialNumber; + + puhost->enum_state = ENUM_SET_ADDR; + } + break; + + case ENUM_SET_ADDR: + /* set address */ + if(USBH_OK == usbh_setaddress(puhost, USBH_DEV_ADDR)) { + usb_mdelay(2U); + + puhost->dev_prop.addr = USBH_DEV_ADDR; + + /* user callback for device address assigned */ + puhost->usr_cb->dev_address_set(); + + /* modify control channels to update device address */ + usbh_pipe_update(&usbh_core, + puhost->control.pipe_in_num, + puhost->dev_prop.addr, + 0U, 0U); + + usbh_pipe_update(&usbh_core, + puhost->control.pipe_out_num, + puhost->dev_prop.addr, + 0U, 0U); + + puhost->enum_state = ENUM_GET_CFG_DESC; + } + break; + + case ENUM_GET_CFG_DESC: + /* get standard configuration descriptor */ + if(USBH_OK == usbh_cfgdesc_get(puhost, USB_CFG_DESC_LEN)) { + puhost->enum_state = ENUM_GET_CFG_DESC_SET; + } + break; + + case ENUM_GET_CFG_DESC_SET: + /* get full config descriptor (config, interface, endpoints) */ + if(USBH_OK == usbh_cfgdesc_get(puhost, puhost->dev_prop.cfg_desc_set.cfg_desc.wTotalLength)) { + /* user callback for configuration descriptors available */ + puhost->usr_cb->dev_cfgdesc_assigned(&puhost->dev_prop.cfg_desc_set.cfg_desc, + &puhost->dev_prop.cfg_desc_set.itf_desc_set[0][0].itf_desc, + &puhost->dev_prop.cfg_desc_set.itf_desc_set[0][0].ep_desc[0]); + + puhost->enum_state = ENUM_GET_STR_DESC; + } + break; + + case ENUM_GET_STR_DESC: + if(index_mfc_str) { + if(USBH_OK == usbh_strdesc_get(puhost, + puhost->dev_prop.dev_desc.iManufacturer, + str_buf, + 0xFFU)) { + /* user callback for manufacturing string */ + puhost->usr_cb->dev_mfc_str(str_buf); + + index_mfc_str = 0U; + } + } else { + if(index_prod_str) { + /* check that product string is available */ + if(USBH_OK == usbh_strdesc_get(puhost, + puhost->dev_prop.dev_desc.iProduct, + str_buf, + 0xFFU)) { + puhost->usr_cb->dev_prod_str(str_buf); + + index_prod_str = 0U; + } + } else { + if(index_serial_str) { + if(USBH_OK == usbh_strdesc_get(puhost, + puhost->dev_prop.dev_desc.iSerialNumber, + str_buf, + 0xFFU)) { + puhost->usr_cb->dev_seral_str(str_buf); + puhost->enum_state = ENUM_SET_CONFIGURATION; + index_serial_str = 0U; + } + } else { + puhost->enum_state = ENUM_SET_CONFIGURATION; + } + } + } + break; + + case ENUM_SET_CONFIGURATION: + if(USBH_OK == usbh_setcfg(puhost, (uint16_t)puhost->dev_prop.cfg_desc_set.cfg_desc.bConfigurationValue)) { + puhost->enum_state = ENUM_DEV_CONFIGURED; + } + break; + + case ENUM_DEV_CONFIGURED: + status = USBH_OK; + break; + + default: + break; + } + + return status; +} + + +#if USB_LOW_POWER + +/*! + \brief handles the USB resume from suspend mode + \param[in] pudev: pointer to selected USB device + \param[out] none + \retval none +*/ +static void usb_hwp_resume(usb_core_driver *pudev) +{ + __IO uint32_t hprt = 0U; + + /* switch-on the clocks */ + *pudev->regs.PWRCLKCTL &= ~PWRCLKCTL_SUCLK; + + *pudev->regs.PWRCLKCTL &= ~PWRCLKCTL_SHCLK; + + hprt = usb_port_read(pudev); + + hprt &= ~HPCS_PSP; + hprt |= HPCS_PREM; + + *pudev->regs.HPCS = hprt; + + usb_mdelay(20U); + + hprt &= ~HPCS_PREM; + + *pudev->regs.HPCS = hprt; +} + +/*! + \brief handles the USB enter to suspend mode + \param[in] pudev: pointer to selected USB device + \param[out] none + \retval none +*/ +static void usb_hwp_suspend(usb_core_driver *pudev) +{ + __IO uint32_t hprt = 0U; + + hprt = usb_port_read(pudev); + + hprt |= HPCS_PSP; + + *pudev->regs.HPCS = hprt; + + /* switch-off the clocks */ + *pudev->regs.PWRCLKCTL |= PWRCLKCTL_SUCLK; + + *pudev->regs.PWRCLKCTL |= PWRCLKCTL_SHCLK; +} + +#endif /* USB_LOW_POWER */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Source/usbh_enum.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Source/usbh_enum.c new file mode 100644 index 000000000..1d186fb6a --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Source/usbh_enum.c @@ -0,0 +1,693 @@ +/*! + \file usbh_enum.c + \brief USB host mode enumberation driver + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_pipe.h" +#include "usbh_transc.h" +#include "usbh_enum.h" + +/* local function prototypes ('static') */ +static void usbh_devdesc_parse(usb_desc_dev *dev_desc, uint8_t *buf, uint16_t len); +static void usbh_cfgdesc_parse(usb_desc_config *cfg_desc, uint8_t *buf); +static void usbh_cfgset_parse(usb_dev_prop *udev, uint8_t *buf); +static void usbh_itfdesc_parse(usb_desc_itf *itf_desc, uint8_t *buf); +static void usbh_epdesc_parse(usb_desc_ep *ep_desc, uint8_t *buf); +static void usbh_strdesc_parse(uint8_t *psrc, uint8_t *pdest, uint16_t len); + +/*! + \brief configure USB control status parameters + \param[in] puhost: pointer to usb host + \param[in] buf: control transfer data buffer pointer + \param[in] len: length of the data buffer + \param[out] none + \retval none +*/ +void usbh_ctlstate_config(usbh_host *puhost, uint8_t *buf, uint16_t len) +{ + /* prepare the transactions */ + puhost->control.buf = buf; + puhost->control.ctl_len = len; + + puhost->control.ctl_state = CTL_SETUP; +} + +/*! + \brief get device descriptor from the USB device + \param[in] puhost: pointer to usb host + \param[in] len: length of the descriptor + \param[out] none + \retval operation status +*/ +usbh_status usbh_devdesc_get(usbh_host *puhost, uint8_t len) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &puhost->control; + + if(CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_GET_DESCRIPTOR, + .wValue = USBH_DESC(USB_DESCTYPE_DEV), + .wIndex = 0U, + .wLength = len + }; + + usbh_ctlstate_config(puhost, puhost->dev_prop.data, (uint16_t)len); + } + + status = usbh_ctl_handler(puhost); + + if(USBH_OK == status) { + /* commands successfully sent and response received */ + usbh_devdesc_parse(&puhost->dev_prop.dev_desc, puhost->dev_prop.data, (uint16_t)len); + } + + return status; +} + +/*! + \brief get configuration descriptor from the USB device + \param[in] puhost: pointer to usb host + \param[in] len: length of the descriptor + \param[out] none + \retval operation status +*/ +usbh_status usbh_cfgdesc_get(usbh_host *puhost, uint16_t len) +{ + uint8_t *pdata = NULL; + + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &puhost->control; + +#if (USBH_KEEP_CFG_DESCRIPTOR == 1U) + pdata = puhost->dev_prop.cfgdesc_rawdata; +#else + pdata = puhost->dev_prop.data; +#endif + + if(CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_GET_DESCRIPTOR, + .wValue = USBH_DESC(USB_DESCTYPE_CONFIG), + .wIndex = 0U, + .wLength = len + }; + + usbh_ctlstate_config(puhost, pdata, len); + } + + status = usbh_ctl_handler(puhost); + + if(USBH_OK == status) { + if(len <= USB_CFG_DESC_LEN) { + usbh_cfgdesc_parse(&puhost->dev_prop.cfg_desc_set.cfg_desc, pdata); + } else { + usbh_cfgset_parse(&puhost->dev_prop, pdata); + } + } + + return status; +} + +/*! + \brief get string descriptor from the USB device + \param[in] puhost: pointer to usb host + \param[in] str_index: index for the string descriptor + \param[in] buf: buffer pointer to the string descriptor + \param[in] len: length of the descriptor + \param[out] none + \retval operation status +*/ +usbh_status usbh_strdesc_get(usbh_host *puhost, + uint8_t str_index, + uint8_t *buf, + uint16_t len) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &puhost->control; + + if(CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_IN | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_GET_DESCRIPTOR, + .wValue = USBH_DESC(USB_DESCTYPE_STR) | str_index, + .wIndex = 0x0409U, + .wLength = len + }; + + usbh_ctlstate_config(puhost, puhost->dev_prop.data, len); + } + + status = usbh_ctl_handler(puhost); + + if(USBH_OK == status) { + /* commands successfully sent and response received */ + usbh_strdesc_parse(puhost->dev_prop.data, buf, len); + } + + return status; +} + +/*! + \brief set the address to the connected device + \param[in] puhost: pointer to usb host + \param[in] dev_addr: device address to assign + \param[out] none + \retval operation status +*/ +usbh_status usbh_setaddress(usbh_host *puhost, uint8_t dev_addr) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &puhost->control; + + if(CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_SET_ADDRESS, + .wValue = (uint16_t)dev_addr, + .wIndex = 0U, + .wLength = 0U + }; + + usbh_ctlstate_config(puhost, NULL, 0U); + } + + status = usbh_ctl_handler(puhost); + + return status; +} + +/*! + \brief set the configuration value to the connected device + \param[in] puhost: pointer to usb host + \param[in] config_index: configuration value + \param[out] none + \retval operation status +*/ +usbh_status usbh_setcfg(usbh_host *puhost, uint16_t config_index) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &puhost->control; + + if(CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_SET_CONFIGURATION, + .wValue = config_index, + .wIndex = 0U, + .wLength = 0U + }; + + usbh_ctlstate_config(puhost, NULL, 0U); + } + + status = usbh_ctl_handler(puhost); + + return status; +} + +/*! + \brief set the interface value to the connected device + \param[in] puhost: pointer to usb host + \param[in] itf_num: interface number + \param[in] set: alternated setting value + \param[out] none + \retval operation status +*/ +usbh_status usbh_setinterface(usbh_host *puhost, uint8_t itf_num, uint8_t set) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &puhost->control; + + if(CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_ITF | USB_REQTYPE_STRD, + .bRequest = USB_SET_INTERFACE, + .wValue = set, + .wIndex = itf_num, + .wLength = 0U + }; + + usbh_ctlstate_config(puhost, NULL, 0U); + } + + status = usbh_ctl_handler(puhost); + + return status; +} + +/*! + \brief set the interface value to the connected device + \param[in] puhost: pointer to usb host + \param[in] feature_selector: feature selector + \param[in] windex: index value + \param[out] none + \retval operation status +*/ +usbh_status usbh_setdevfeature(usbh_host *puhost, uint8_t feature_selector, uint16_t windex) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &puhost->control; + + if(CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_SET_FEATURE, + .wValue = feature_selector, + .wIndex = windex, + .wLength = 0U + }; + + usbh_ctlstate_config(puhost, NULL, 0U); + } + + status = usbh_ctl_handler(puhost); + + return status; +} + +/*! + \brief clear the interface value to the connected device + \param[in] puhost: pointer to usb host + \param[in] feature_selector: feature selector + \param[in] windex: index value + \param[out] none + \retval operation status +*/ +usbh_status usbh_clrdevfeature(usbh_host *puhost, uint8_t feature_selector, uint16_t windex) +{ + usbh_status status = USBH_BUSY; + + usbh_control *usb_ctl = &puhost->control; + + if(CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_DEV | USB_REQTYPE_STRD, + .bRequest = USB_CLEAR_FEATURE, + .wValue = feature_selector, + .wIndex = windex, + .wLength = 0U + }; + + usbh_ctlstate_config(puhost, NULL, 0U); + } + + status = usbh_ctl_handler(puhost); + + return status; +} + +/*! + \brief clear or disable a specific feature + \param[in] puhost: pointer to usb host + \param[in] ep_addr: endpoint address + \param[in] pp_num: pipe number + \param[out] none + \retval operation status +*/ +usbh_status usbh_clrfeature(usbh_host *puhost, uint8_t ep_addr, uint8_t pp_num) +{ + usbh_status status = USBH_BUSY; + usbh_control *usb_ctl = &puhost->control; + usb_core_driver *pudev = (usb_core_driver *)puhost->data; + + if(CTL_IDLE == usb_ctl->ctl_state) { + usb_ctl->setup.req = (usb_req) { + .bmRequestType = USB_TRX_OUT | USB_RECPTYPE_EP | USB_REQTYPE_STRD, + .bRequest = USB_CLEAR_FEATURE, + .wValue = FEATURE_SELECTOR_EP, + .wIndex = ep_addr, + .wLength = 0U + }; + + if(EP_ID(ep_addr) == pudev->host.pipe[pp_num].ep.num) { + usbh_pipe_toggle_set(pudev, pp_num, 0U); + } else { + return USBH_FAIL; + } + + usbh_ctlstate_config(puhost, NULL, 0U); + } + + status = usbh_ctl_handler(puhost); + + return status; +} + +/*! + \brief get the next descriptor header + \param[in] pbuf: pointer to buffer where the configuration descriptor set is available + \param[in] ptr: data pointer inside the configuration descriptor set + \param[out] none + \retval return descriptor header +*/ +usb_desc_header *usbh_nextdesc_get(uint8_t *pbuf, uint16_t *ptr) +{ + usb_desc_header *pnext; + + *ptr += ((usb_desc_header *)pbuf)->bLength; + + pnext = (usb_desc_header *)((uint8_t *)pbuf + ((usb_desc_header *)pbuf)->bLength); + + return (pnext); +} + +/*! + \brief get the next descriptor header + \param[in] udev: pointer to device property + \param[in] interface: interface number + \param[out] none + \retval operation status +*/ +usbh_status usbh_interface_select(usb_dev_prop *udev, uint8_t interface) +{ + usbh_status status = USBH_OK; + + if(interface < udev->cfg_desc_set.cfg_desc.bNumInterfaces) { + udev->cur_itf = interface; + } else { + status = USBH_FAIL; + } + + return status; +} + +/*! + \brief find the interface index for a specific class + \param[in] udev: pointer to device property + \param[in] main_class: class code + \param[in] sub_class: subclass code + \param[in] protocol: Protocol code + \param[out] none + \retval interface index in the configuration structure + \note interface index 0xFF means interface index not found +*/ +uint8_t usbh_interface_find(usb_dev_prop *udev, uint8_t main_class, uint8_t sub_class, uint8_t protocol) +{ + usb_desc_itf *pif; + + uint8_t if_ix = 0U; + + pif = (usb_desc_itf *)0; + + while(if_ix < udev->cfg_desc_set.cfg_desc.bNumInterfaces) { + pif = &udev->cfg_desc_set.itf_desc_set[if_ix][0].itf_desc; + + if(((pif->bInterfaceClass == main_class) || (main_class == 0xFFU)) && + ((pif->bInterfaceSubClass == sub_class) || (sub_class == 0xFFU)) && + ((pif->bInterfaceProtocol == protocol) || (protocol == 0xFFU))) { + return if_ix; + } + + if_ix++; + } + + return 0xFFU; +} + +/*! + \brief find the interface index for a specific class interface and alternate setting number + \param[in] udev: pointer to device property + \param[in] interface_number: interface number + \param[in] alt_settings: alternate setting number + \param[out] none + \retval interface index in the configuration structure + \note interface index 0xFF means interface index not found +*/ +uint8_t usbh_interfaceindex_find(usb_dev_prop *udev, uint8_t interface_number, uint8_t alt_settings) +{ + usb_desc_itf *pif; + + uint8_t if_ix = 0U; + + pif = (usb_desc_itf *)0; + + while(if_ix < USBH_MAX_INTERFACES_NUM) { + pif = &udev->cfg_desc_set.itf_desc_set[if_ix][alt_settings].itf_desc; + + if((pif->bInterfaceNumber == interface_number) && (pif->bAlternateSetting == alt_settings)) { + return if_ix; + } + + if_ix++; + } + + return 0xFFU; +} + +/*! + \brief parse the device descriptor + \param[in] dev_desc: pointer to usb device descriptor buffer + \param[in] buf: pointer to the source descriptor buffer + \param[in] len: length of the descriptor + \param[out] none + \retval none +*/ +static void usbh_devdesc_parse(usb_desc_dev *dev_desc, uint8_t *buf, uint16_t len) +{ + *dev_desc = (usb_desc_dev) { + .header = { + .bLength = *(uint8_t *)(buf + 0U), + .bDescriptorType = *(uint8_t *)(buf + 1U) + }, + + .bcdUSB = BYTE_SWAP(buf + 2U), + .bDeviceClass = *(uint8_t *)(buf + 4U), + .bDeviceSubClass = *(uint8_t *)(buf + 5U), + .bDeviceProtocol = *(uint8_t *)(buf + 6U), + .bMaxPacketSize0 = *(uint8_t *)(buf + 7U) + }; + + if(len > 8U) { + /* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */ + dev_desc->idVendor = BYTE_SWAP(buf + 8U); + dev_desc->idProduct = BYTE_SWAP(buf + 10U); + dev_desc->bcdDevice = BYTE_SWAP(buf + 12U); + dev_desc->iManufacturer = *(uint8_t *)(buf + 14U); + dev_desc->iProduct = *(uint8_t *)(buf + 15U); + dev_desc->iSerialNumber = *(uint8_t *)(buf + 16U); + dev_desc->bNumberConfigurations = *(uint8_t *)(buf + 17U); + } +} + +/*! + \brief parse the configuration descriptor + \param[in] cfg_desc: pointer to usb configuration descriptor buffer + \param[in] buf: pointer to the source descriptor buffer + \param[out] none + \retval none +*/ +static void usbh_cfgdesc_parse(usb_desc_config *cfg_desc, uint8_t *buf) +{ + /* parse configuration descriptor */ + *cfg_desc = (usb_desc_config) { + .header = { + .bLength = *(uint8_t *)(buf + 0U), + .bDescriptorType = *(uint8_t *)(buf + 1U), + }, + + .wTotalLength = BYTE_SWAP(buf + 2U), + .bNumInterfaces = *(uint8_t *)(buf + 4U), + .bConfigurationValue = *(uint8_t *)(buf + 5U), + .iConfiguration = *(uint8_t *)(buf + 6U), + .bmAttributes = *(uint8_t *)(buf + 7U), + .bMaxPower = *(uint8_t *)(buf + 8U) + }; +} + +/*! + \brief parse the configuration descriptor set + \param[in] udev: pointer to device property + \param[in] buf: pointer to the source descriptor buffer + \param[out] none + \retval none +*/ +static void usbh_cfgset_parse(usb_dev_prop *udev, uint8_t *buf) +{ + usb_desc_ep *ep = NULL; + usb_desc_itf_set *itf = NULL; + usb_desc_itf itf_value; + usb_desc_config *cfg = NULL; + + usb_desc_header *pdesc = (usb_desc_header *)buf; + + uint8_t itf_index = 0U, ep_index = 0U, alt_setting = 0U; + uint8_t pre_itf_index = 0U; + uint16_t ptr; + + /* parse configuration descriptor */ + usbh_cfgdesc_parse(&udev->cfg_desc_set.cfg_desc, buf); + cfg = &udev->cfg_desc_set.cfg_desc; + ptr = USB_CFG_DESC_LEN; + + if(cfg->bNumInterfaces > USBH_MAX_INTERFACES_NUM) { + return; + } + + while(ptr < cfg->wTotalLength) { + pdesc = usbh_nextdesc_get((uint8_t *)pdesc, &ptr); + + if(pdesc->bDescriptorType == USB_DESCTYPE_ITF) { + itf_index = *(((uint8_t *)pdesc) + 2U); + + if(pre_itf_index != itf_index) { + alt_setting = 0U; + } + + itf = &udev->cfg_desc_set.itf_desc_set[itf_index][alt_setting]; + + alt_setting++; + + if((*((uint8_t *)pdesc + 3U)) < 3U) { + usbh_itfdesc_parse(&itf_value, (uint8_t *)pdesc); + + /* parse endpoint descriptors relative to the current interface */ + if(itf_value.bNumEndpoints > USBH_MAX_EP_NUM) { + return; + } + + usbh_itfdesc_parse(&itf->itf_desc, (uint8_t *)&itf_value); + + /* store the previous interface index */ + pre_itf_index = itf_index; + + if(0U == itf_value.bNumEndpoints) { + continue; + } + + for(ep_index = 0U; ep_index < itf_value.bNumEndpoints;) { + pdesc = usbh_nextdesc_get((void *)pdesc, &ptr); + + if(pdesc->bDescriptorType == USB_DESCTYPE_EP) { + ep = &itf->ep_desc[ep_index]; + + usbh_epdesc_parse(ep, (uint8_t *)pdesc); + + ep_index++; + } + } + } + } + } +} + +/*! + \brief parse the interface descriptor + \param[in] itf_desc: pointer to usb interface descriptor buffer + \param[in] buf: pointer to the source descriptor buffer + \param[out] none + \retval none +*/ +static void usbh_itfdesc_parse(usb_desc_itf *itf_desc, uint8_t *buf) +{ + *itf_desc = (usb_desc_itf) { + .header = { + .bLength = *(uint8_t *)(buf + 0U), + .bDescriptorType = *(uint8_t *)(buf + 1U), + }, + + .bInterfaceNumber = *(uint8_t *)(buf + 2U), + .bAlternateSetting = *(uint8_t *)(buf + 3U), + .bNumEndpoints = *(uint8_t *)(buf + 4U), + .bInterfaceClass = *(uint8_t *)(buf + 5U), + .bInterfaceSubClass = *(uint8_t *)(buf + 6U), + .bInterfaceProtocol = *(uint8_t *)(buf + 7U), + .iInterface = *(uint8_t *)(buf + 8U) + }; +} + +/*! + \brief parse the endpoint descriptor + \param[in] ep_desc: pointer to usb endpoint descriptor buffer + \param[in] buf: pointer to the source descriptor buffer + \param[out] none + \retval none +*/ +static void usbh_epdesc_parse(usb_desc_ep *ep_desc, uint8_t *buf) +{ + *ep_desc = (usb_desc_ep) { + .header = { + .bLength = *(uint8_t *)(buf + 0U), + .bDescriptorType = *(uint8_t *)(buf + 1U) + }, + + .bEndpointAddress = *(uint8_t *)(buf + 2U), + .bmAttributes = *(uint8_t *)(buf + 3U), + .wMaxPacketSize = BYTE_SWAP(buf + 4U), + .bInterval = *(uint8_t *)(buf + 6U) + }; +} + +/*! + \brief parse the string descriptor + \param[in] psrc: source pointer containing the descriptor data + \param[in] pdest: destination address pointer + \param[in] len: length of the descriptor + \param[out] none + \retval none +*/ +static void usbh_strdesc_parse(uint8_t *psrc, uint8_t *pdest, uint16_t len) +{ + uint16_t str_len = 0U, index = 0U; + + /* the unicode string descriptor is not NULL-terminated. The string length is + * computed by substracting two from the value of the first byte of the descriptor. + */ + + /* check which is lower size, the size of string or the length of bytes read from the device */ + if(USB_DESCTYPE_STR == psrc[1]) { + /* make sure the descriptor is string type */ + + /* psrc[0] contains Size of Descriptor, subtract 2 to get the length of string */ + str_len = USB_MIN((uint16_t)psrc[0] - 2U, len); + + psrc += 2U; /* adjust the offset ignoring the string len and descriptor type */ + + for(index = 0U; index < str_len; index += 2U) { + /* copy only the string and ignore the unicode id, hence add the src */ + *pdest = psrc[index]; + + pdest++; + } + + *pdest = 0U; /* mark end of string */ + } +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Source/usbh_pipe.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Source/usbh_pipe.c new file mode 100644 index 000000000..fab73ea21 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Source/usbh_pipe.c @@ -0,0 +1,176 @@ +/*! + \file usbh_pipe.c + \brief USB host mode pipe operation driver + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "usbh_pipe.h" + +/* local function prototypes ('static') */ +static uint16_t usbh_freepipe_get(usb_core_driver *pudev); + +/*! + \brief create a pipe + \param[in] pudev: pointer to usb core instance + \param[in] udev: USB device + \param[in] pp_num: pipe number + \param[in] ep_type: endpoint type + \param[in] ep_mpl: endpoint max packet length + \param[out] none + \retval operation status +*/ +uint8_t usbh_pipe_create(usb_core_driver *pudev, + usb_dev_prop *udev, + uint8_t pp_num, + uint8_t ep_type, + uint16_t ep_mpl) +{ + usb_pipe *pp = &pudev->host.pipe[pp_num]; + + pp->dev_addr = udev->addr; + pp->dev_speed = udev->speed; + pp->ep.type = ep_type; + pp->ep.mps = ep_mpl; + pp->ping = (uint8_t)(udev->speed == PORT_SPEED_HIGH); + + usb_pipe_init(pudev, pp_num); + + return HC_OK; +} + +/*! + \brief modify a pipe + \param[in] pudev: pointer to usb core instance + \param[in] pp_num: pipe number + \param[in] dev_addr: device address + \param[in] dev_speed: device speed + \param[in] ep_mpl: endpoint max packet length + \param[out] none + \retval operation status +*/ +uint8_t usbh_pipe_update(usb_core_driver *pudev, + uint8_t pp_num, + uint8_t dev_addr, + uint32_t dev_speed, + uint16_t ep_mpl) +{ + usb_pipe *pp = &pudev->host.pipe[pp_num]; + + if((pp->dev_addr != dev_addr) && (dev_addr)) { + pp->dev_addr = dev_addr; + } + + if((pp->dev_speed != dev_speed) && (dev_speed)) { + pp->dev_speed = dev_speed; + } + + if((pp->ep.mps != ep_mpl) && (ep_mpl)) { + pp->ep.mps = ep_mpl; + } + + usb_pipe_init(pudev, pp_num); + + return HC_OK; +} + +/*! + \brief allocate a new pipe + \param[in] pudev: pointer to usb core instance + \param[in] ep_addr: endpoint address + \param[out] none + \retval operation status +*/ +uint8_t usbh_pipe_allocate(usb_core_driver *pudev, uint8_t ep_addr) +{ + uint16_t pp_num = usbh_freepipe_get(pudev); + + if(HC_ERROR != pp_num) { + pudev->host.pipe[pp_num].in_used = 1U; + pudev->host.pipe[pp_num].ep.dir = EP_DIR(ep_addr); + pudev->host.pipe[pp_num].ep.num = EP_ID(ep_addr); + } + + return (uint8_t)pp_num; +} + +/*! + \brief free a pipe + \param[in] pudev: pointer to usb core instance + \param[in] pp_num: pipe number + \param[out] none + \retval operation status +*/ +uint8_t usbh_pipe_free(usb_core_driver *pudev, uint8_t pp_num) +{ + if(pp_num < HC_MAX) { + pudev->host.pipe[pp_num].in_used = 0U; + } + + return USBH_OK; +} + +/*! + \brief delete all USB host pipe + \param[in] pudev: pointer to usb core instance + \param[out] none + \retval operation status +*/ +uint8_t usbh_pipe_delete(usb_core_driver *pudev) +{ + uint8_t pp_num = 0U; + + for(pp_num = 2U; pp_num < HC_MAX; pp_num++) { + pudev->host.pipe[pp_num] = (usb_pipe) { + 0 + }; + } + + return USBH_OK; +} + +/*! + \brief get a free pipe number for allocation + \param[in] pudev: pointer to usb core instance + \param[out] none + \retval operation status +*/ +static uint16_t usbh_freepipe_get(usb_core_driver *pudev) +{ + uint8_t pp_num = 0U; + + for(pp_num = 0U; pp_num < HC_MAX; pp_num++) { + if(0U == pudev->host.pipe[pp_num].in_used) { + return (uint16_t)pp_num; + } + } + + return HC_ERROR; +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Source/usbh_transc.c b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Source/usbh_transc.c new file mode 100644 index 000000000..d9c5b256c --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/host/core/Source/usbh_transc.c @@ -0,0 +1,372 @@ +/*! + \file usbh_transc.c + \brief USB host mode transactions driver + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 + \version 2021-09-27, V3.0.1, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "drv_usb_hw.h" +#include "usbh_pipe.h" +#include "usbh_transc.h" + +/* local function prototypes ('static') */ +static usb_urb_state usbh_urb_wait(usbh_host *puhost, uint8_t pp_num, uint32_t wait_time); +static void usbh_setup_transc(usbh_host *puhost); +static void usbh_data_in_transc(usbh_host *puhost); +static void usbh_data_out_transc(usbh_host *puhost); +static void usbh_status_in_transc(usbh_host *puhost); +static void usbh_status_out_transc(usbh_host *puhost); +static uint32_t usbh_request_submit(usb_core_driver *pudev, uint8_t pp_num); + +/*! + \brief send the setup packet to the USB device + \param[in] pudev: pointer to usb core instance + \param[in] buf: data buffer which will be sent to USB device + \param[in] pp_num: pipe number + \param[out] none + \retval operation status +*/ +usbh_status usbh_ctlsetup_send(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num) +{ + usb_pipe *pp = &pudev->host.pipe[pp_num]; + + pp->DPID = PIPE_DPID_SETUP; + pp->xfer_buf = buf; + pp->xfer_len = USB_SETUP_PACKET_LEN; + + return (usbh_status)usbh_request_submit(pudev, pp_num); +} + +/*! + \brief send a data packet to the USB device + \param[in] pudev: pointer to usb core instance + \param[in] buf: data buffer which will be sent to USB device + \param[in] pp_num: pipe number + \param[in] len: length of the data to be sent + \param[out] none + \retval operation status +*/ +usbh_status usbh_data_send(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len) +{ + usb_pipe *pp = &pudev->host.pipe[pp_num]; + + pp->xfer_buf = buf; + pp->xfer_len = len; + + switch(pp->ep.type) { + case USB_EPTYPE_CTRL: + if(0U == len) { + pp->data_toggle_out = 1U; + } + + pp->DPID = PIPE_DPID[pp->data_toggle_out]; + break; + + case USB_EPTYPE_INTR: + pp->DPID = PIPE_DPID[pp->data_toggle_out]; + + pp->data_toggle_out ^= 1U; + break; + + case USB_EPTYPE_BULK: + pp->DPID = PIPE_DPID[pp->data_toggle_out]; + break; + + case USB_EPTYPE_ISOC: + pp->DPID = PIPE_DPID[0]; + break; + + default: + break; + } + + usbh_request_submit(pudev, pp_num); + + return USBH_OK; +} + +/*! + \brief receive a data packet from the USB device + \param[in] pudev: pointer to usb core instance + \param[in] buf: data buffer which will be received from USB device + \param[in] pp_num: pipe number + \param[in] len: length of the data to be received + \param[out] none + \retval operation status +*/ +usbh_status usbh_data_recev(usb_core_driver *pudev, uint8_t *buf, uint8_t pp_num, uint16_t len) +{ + usb_pipe *pp = &pudev->host.pipe[pp_num]; + + pp->xfer_buf = buf; + pp->xfer_len = len; + + switch(pp->ep.type) { + case USB_EPTYPE_CTRL: + pp->DPID = PIPE_DPID[1]; + break; + + case USB_EPTYPE_INTR: + pp->DPID = PIPE_DPID[pp->data_toggle_in]; + + /* Toggle DATA PID */ + pp->data_toggle_in ^= 1U; + break; + + case USB_EPTYPE_BULK: + pp->DPID = PIPE_DPID[pp->data_toggle_in]; + break; + + case USB_EPTYPE_ISOC: + pp->DPID = PIPE_DPID[0]; + break; + + default: + break; + } + + usbh_request_submit(pudev, pp_num); + + return USBH_OK; +} + +/*! + \brief USB control transfer handler + \param[in] puhost: pointer to USB host + \param[out] none + \retval operation status +*/ +usbh_status usbh_ctl_handler(usbh_host *puhost) +{ + usbh_status status = USBH_BUSY; + + switch(puhost->control.ctl_state) { + case CTL_SETUP: + usbh_setup_transc(puhost); + break; + + case CTL_DATA_IN: + usbh_data_in_transc(puhost); + break; + + case CTL_DATA_OUT: + usbh_data_out_transc(puhost); + break; + + case CTL_STATUS_IN: + usbh_status_in_transc(puhost); + break; + + case CTL_STATUS_OUT: + usbh_status_out_transc(puhost); + break; + + case CTL_FINISH: + puhost->control.ctl_state = CTL_IDLE; + + status = USBH_OK; + break; + + case CTL_ERROR: + if(++puhost->control.error_count <= USBH_MAX_ERROR_COUNT) { + /* do the transmission again, starting from SETUP packet */ + puhost->control.ctl_state = CTL_SETUP; + } else { + status = USBH_FAIL; + } + break; + + default: + break; + } + + return status; +} + +/*! + \brief wait for USB URB(USB request block) state + \param[in] puhost: pointer to USB host + \param[in] pp_num: pipe number + \param[in] wait_time: wait time + \param[out] none + \retval USB URB state +*/ +static usb_urb_state usbh_urb_wait(usbh_host *puhost, uint8_t pp_num, uint32_t wait_time) +{ + uint32_t timeout = 0U; + usb_urb_state urb_status = URB_IDLE; + timeout = puhost->control.timer; + + while(URB_DONE != (urb_status = usbh_urbstate_get(puhost->data, pp_num))) { + if(URB_NOTREADY == urb_status) { + break; + } else if(URB_STALL == urb_status) { + puhost->control.ctl_state = CTL_SETUP; + break; + } else if(URB_ERROR == urb_status) { + puhost->control.ctl_state = CTL_ERROR; + break; + } else if((wait_time > 0U) && (((usb_curframe_get(puhost->data) > timeout) && ((usb_curframe_get(puhost->data) - timeout) > wait_time)) \ + || ((usb_curframe_get(puhost->data) < timeout) && ((usb_curframe_get(puhost->data) + 0x3FFFU - timeout) > wait_time)))) { + /* timeout for in transfer */ + puhost->control.ctl_state = CTL_ERROR; + break; + } else { + /* no operation, just wait */ + } + } + + return urb_status; +} + +/*! + \brief USB setup transaction + \param[in] puhost: pointer to USB host + \param[out] none + \retval none +*/ +static void usbh_setup_transc(usbh_host *puhost) +{ + /* send a SETUP packet */ + usbh_ctlsetup_send(puhost->data, + puhost->control.setup.data, + puhost->control.pipe_out_num); + + if(URB_DONE == usbh_urb_wait(puhost, puhost->control.pipe_out_num, 0U)) { + uint8_t dir = (puhost->control.setup.req.bmRequestType & USB_TRX_MASK); + + if(puhost->control.setup.req.wLength) { + if(USB_TRX_IN == dir) { + puhost->control.ctl_state = CTL_DATA_IN; + } else { + puhost->control.ctl_state = CTL_DATA_OUT; + } + } else { + if(USB_TRX_IN == dir) { + puhost->control.ctl_state = CTL_STATUS_OUT; + } else { + puhost->control.ctl_state = CTL_STATUS_IN; + } + } + + /* set the delay timer to enable timeout for data stage completion */ + puhost->control.timer = (uint16_t)usb_curframe_get(puhost->data); + } +} + +/*! + \brief USB data IN transaction + \param[in] puhost: pointer to USB host + \param[out] none + \retval none +*/ +static void usbh_data_in_transc(usbh_host *puhost) +{ + usbh_data_recev(puhost->data, + puhost->control.buf, + puhost->control.pipe_in_num, + puhost->control.ctl_len); + + if(URB_DONE == usbh_urb_wait(puhost, puhost->control.pipe_in_num, DATA_STAGE_TIMEOUT)) { + puhost->control.ctl_state = CTL_STATUS_OUT; + + } +} + +/*! + \brief USB data OUT transaction + \param[in] puhost: pointer to USB host + \param[out] none + \retval none +*/ +static void usbh_data_out_transc(usbh_host *puhost) +{ + usbh_pipe_toggle_set(puhost->data, puhost->control.pipe_out_num, 1U); + + usbh_data_send(puhost->data, + puhost->control.buf, + puhost->control.pipe_out_num, + puhost->control.ctl_len); + + if(URB_DONE == usbh_urb_wait(puhost, puhost->control.pipe_out_num, DATA_STAGE_TIMEOUT)) { + puhost->control.ctl_state = CTL_STATUS_IN; + + } +} + +/*! + \brief USB status IN transaction + \param[in] puhost: pointer to USB host + \param[out] none + \retval none +*/ +static void usbh_status_in_transc(usbh_host *puhost) +{ + uint8_t pp_num = puhost->control.pipe_in_num; + + usbh_data_recev(puhost->data, NULL, pp_num, 0U); + + if(URB_DONE == usbh_urb_wait(puhost, pp_num, NODATA_STAGE_TIMEOUT)) { + puhost->control.ctl_state = CTL_FINISH; + } +} + +/*! + \brief USB status OUT transaction + \param[in] puhost: pointer to USB host + \param[out] none + \retval none +*/ +static void usbh_status_out_transc(usbh_host *puhost) +{ + uint8_t pp_num = puhost->control.pipe_out_num; + + usbh_data_send(puhost->data, NULL, pp_num, 0U); + + if(URB_DONE == usbh_urb_wait(puhost, pp_num, NODATA_STAGE_TIMEOUT)) { + puhost->control.ctl_state = CTL_FINISH; + } +} + +/*! + \brief prepare a pipe and start a transfer + \param[in] pudev: pointer to usb core instance + \param[in] pp_num: pipe number + \param[out] none + \retval operation status +*/ +static uint32_t usbh_request_submit(usb_core_driver *pudev, uint8_t pp_num) +{ + pudev->host.pipe[pp_num].urb_state = URB_IDLE; + pudev->host.pipe[pp_num].xfer_count = 0U; + + return (uint32_t)usb_pipe_xfer(pudev, pp_num); +} diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/class/cdc/usb_cdc.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/class/cdc/usb_cdc.h new file mode 100644 index 000000000..a8563149b --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/class/cdc/usb_cdc.h @@ -0,0 +1,180 @@ +/*! + \file usb_cdc.h + \brief the header file of communication device class standard + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CDC_H +#define __USB_CDC_H + +#include "usb_ch9_std.h" + +/* communications device class code */ +#define USB_CLASS_CDC 0x02U + +/* communications interface class control protocol codes */ +#define USB_CDC_PROTOCOL_NONE 0x00U +#define USB_CDC_PROTOCOL_AT 0x01U +#define USB_CDC_PROTOCOL_VENDOR 0xFFU + +/* data interface class code */ +#define USB_CLASS_DATA 0x0AU + +#define USB_DESCTYPE_CDC_ACM 0x21U +#define USB_DESCTYPE_CS_INTERFACE 0x24U + +#define USB_CDC_ACM_CONFIG_DESC_SIZE 0x43U + +/* class-specific notification codes for pstn subclasses */ +#define USB_CDC_NOTIFY_SERIAL_STATE 0x20U + +/* class-specific request codes */ +#define SEND_ENCAPSULATED_COMMAND 0x00U +#define GET_ENCAPSULATED_RESPONSE 0x01U +#define SET_COMM_FEATURE 0x02U +#define GET_COMM_FEATURE 0x03U +#define CLEAR_COMM_FEATURE 0x04U + +#define SET_AUX_LINE_STATE 0x10U +#define SET_HOOK_STATE 0x11U +#define PULSE_SETUP 0x12U +#define SEND_PULSE 0x13U +#define SET_PULSE_TIME 0x14U +#define RING_AUX_JACK 0x15U + +#define SET_LINE_CODING 0x20U +#define GET_LINE_CODING 0x21U +#define SET_CONTROL_LINE_STATE 0x22U +#define SEND_BREAK 0x23U +#define NO_CMD 0xFFU + +#define SET_RINGER_PARMS 0x30U +#define GET_RINGER_PARMS 0x31U +#define SET_OPERATION_PARMS 0x32U +#define GET_OPERATION_PARMS 0x33U +#define SET_LINE_PARMS 0x34U +#define GET_LINE_PARMS 0x35U +#define DIAL_DIGITS 0x36U +#define SET_UNIT_PARAMETER 0x37U +#define GET_UNIT_PARAMETER 0x38U +#define CLEAR_UNIT_PARAMETER 0x39U +#define GET_PROFILE 0x3AU + +#define SET_ETHERNET_MULTICAST_FILTERS 0x40U +#define SET_ETHERNET_POWER_MANAGEMENT_PATTERN FILTER 0x41U +#define GET_ETHERNET_POWER_MANAGEMENT_PATTERN FILTER 0x42U +#define SET_ETHERNET_PACKET_FILTER 0x43U +#define GET_ETHERNET_STATISTIC 0x44U + +#define SET_ATM_DATA_FORMAT 0x50U +#define GET_ATM_DEVICE_STATISTICS 0x51U +#define SET_ATM_DEFAULT_VC 0x52U +#define GET_ATM_VC_STATISTICS 0x53U + +/* wValue for set control line state */ +#define CDC_ACTIVATE_CARRIER_SIGNAL_RTS 0x0002U +#define CDC_DEACTIVATE_CARRIER_SIGNAL_RTS 0x0000U +#define CDC_ACTIVATE_SIGNAL_DTR 0x0001U +#define CDC_DEACTIVATE_SIGNAL_DTR 0x0000U + +/* CDC subclass code */ +enum usb_cdc_subclass { + USB_CDC_SUBCLASS_RESERVED = 0U, /*!< reserved */ + USB_CDC_SUBCLASS_DLCM, /*!< direct line control mode */ + USB_CDC_SUBCLASS_ACM, /*!< abstract control mode */ + USB_CDC_SUBCLASS_TCM, /*!< telephone control mode */ + USB_CDC_SUBCLASS_MCM, /*!< multichannel control model */ + USB_CDC_SUBCLASS_CCM, /*!< CAPI control model */ + USB_CDC_SUBCLASS_ENCM, /*!< ethernet networking control model */ + USB_CDC_SUBCLASS_ANCM /*!< ATM networking control model */ +}; + +#pragma pack(1) + +/* cdc acm line coding structure */ +typedef struct { + uint32_t dwDTERate; /*!< data terminal rate */ + uint8_t bCharFormat; /*!< stop bits */ + uint8_t bParityType; /*!< parity */ + uint8_t bDataBits; /*!< data bits */ +} acm_line; + +/* notification structure */ +typedef struct { + uint8_t bmRequestType; /*!< type of request */ + uint8_t bNotification; /*!< communication interface class notifications */ + uint16_t wValue; /*!< value of notification */ + uint16_t wIndex; /*!< index of interface */ + uint16_t wLength; /*!< length of notification data */ +} acm_notification; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: header function descriptor */ + uint16_t bcdCDC; /*!< bcdCDC: low byte of spec release number (CDC1.10) */ +} usb_desc_header_func; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: call management function descriptor */ + uint8_t bmCapabilities; /*!< bmCapabilities: D0 is reset, D1 is ignored */ + uint8_t bDataInterface; /*!< bDataInterface: 1 interface used for call management */ +} usb_desc_call_managment_func; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: abstract control management descriptor */ + uint8_t bmCapabilities; /*!< bmCapabilities: D1 */ +} usb_desc_acm_func; + +typedef struct { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint8_t bDescriptorSubtype; /*!< bDescriptorSubtype: union function descriptor */ + uint8_t bMasterInterface; /*!< bMasterInterface: communication class interface */ + uint8_t bSlaveInterface0; /*!< bSlaveInterface0: data class interface */ +} usb_desc_union_func; + +#pragma pack() + +typedef struct { + usb_desc_config config; + usb_desc_itf cmd_itf; + usb_desc_header_func cdc_header; + usb_desc_call_managment_func cdc_call_managment; + usb_desc_acm_func cdc_acm; + usb_desc_union_func cdc_union; + usb_desc_ep cdc_cmd_endpoint; + usb_desc_itf cdc_data_interface; + usb_desc_ep cdc_out_endpoint; + usb_desc_ep cdc_in_endpoint; +} usb_cdc_desc_config_set; + +#endif /* __USB_CDC_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/class/hid/usb_hid.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/class/hid/usb_hid.h new file mode 100644 index 000000000..88c9fde87 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/class/hid/usb_hid.h @@ -0,0 +1,81 @@ +/*! + \file usb_hid.h + \brief definitions for the USB HID class + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_HID_H +#define __USB_HID_H + +#include "usb_ch9_std.h" + +#define USB_HID_CLASS 0x03U + +#define USB_DESCTYPE_HID 0x21U +#define USB_DESCTYPE_REPORT 0x22U + +/* HID subclass code */ +#define USB_HID_SUBCLASS_BOOT_ITF 0x01U + +/* HID protocol codes */ +#define USB_HID_PROTOCOL_KEYBOARD 0x01U +#define USB_HID_PROTOCOL_MOUSE 0x02U + +#define GET_REPORT 0x01U +#define GET_IDLE 0x02U +#define GET_PROTOCOL 0x03U +#define SET_REPORT 0x09U +#define SET_IDLE 0x0AU +#define SET_PROTOCOL 0x0BU + +#pragma pack(1) + +typedef struct { + usb_desc_header header; /*!< regular descriptor header containing the descriptor's type and length */ + + uint16_t bcdHID; /*!< BCD encoded version that the HID descriptor and device complies to */ + uint8_t bCountryCode; /*!< country code of the localized device, or zero if universal */ + uint8_t bNumDescriptors; /*!< total number of HID report descriptors for the interface */ + uint8_t bDescriptorType; /*!< type of HID report */ + uint16_t wDescriptorLength; /*!< length of the associated HID report descriptor, in bytes */ +} usb_desc_hid; + +#pragma pack() + +typedef struct { + usb_desc_config config; + usb_desc_itf hid_itf; + usb_desc_hid hid_vendor; + usb_desc_ep hid_epin; + usb_desc_ep hid_epout; +} usb_hid_desc_config_set; + +#endif /* __USB_HID_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/class/msc/msc_bbb.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/class/msc/msc_bbb.h new file mode 100644 index 000000000..bb02ea42a --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/class/msc/msc_bbb.h @@ -0,0 +1,69 @@ +/*! + \file msc_bbb.h + \brief definitions for the USB MSC BBB(bulk/bulk/bulk) protocol + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __MSC_BBB_H +#define __MSC_BBB_H + +#include "usb_ch9_std.h" + +#define BBB_CBW_SIGNATURE 0x43425355U +#define BBB_CSW_SIGNATURE 0x53425355U +#define BBB_CBW_LENGTH 31U +#define BBB_CSW_LENGTH 13U + +typedef struct { + uint32_t dCBWSignature; + uint32_t dCBWTag; + uint32_t dCBWDataTransferLength; + uint8_t bmCBWFlags; + uint8_t bCBWLUN; + uint8_t bCBWCBLength; + uint8_t CBWCB[16]; +} msc_bbb_cbw; + +typedef struct { + uint32_t dCSWSignature; + uint32_t dCSWTag; + uint32_t dCSWDataResidue; + uint8_t bCSWStatus; +} msc_bbb_csw; + +/* CSW command status */ +enum msc_csw_status { + CSW_CMD_PASSED = 0, + CSW_CMD_FAILED, + CSW_PHASE_ERROR +}; + +#endif /* __MSC_BBB_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/class/msc/msc_scsi.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/class/msc/msc_scsi.h new file mode 100644 index 000000000..768373166 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/class/msc/msc_scsi.h @@ -0,0 +1,117 @@ +/*! + \file msc_scsi.h + \brief definitions for the USB MSC SCSI commands + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __MSC_SCSI_H +#define __MSC_SCSI_H + +#include "usb_ch9_std.h" + +/* SCSI commands */ +#define SCSI_FORMAT_UNIT 0x04U +#define SCSI_INQUIRY 0x12U +#define SCSI_MODE_SELECT6 0x15U +#define SCSI_MODE_SELECT10 0x55U +#define SCSI_MODE_SENSE6 0x1AU +#define SCSI_READ_TOC_DATA 0x43U +#define SCSI_MODE_SENSE10 0x5AU +#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1EU +#define SCSI_READ6 0x08U +#define SCSI_READ10 0x28U +#define SCSI_READ12 0xA8U +#define SCSI_READ16 0x88U + +#define SCSI_READ_CAPACITY10 0x25U +#define SCSI_READ_CAPACITY16 0x9EU + +#define SCSI_REQUEST_SENSE 0x03U +#define SCSI_START_STOP_UNIT 0x1BU +#define SCSI_TEST_UNIT_READY 0x00U +#define SCSI_WRITE6 0x0AU +#define SCSI_WRITE10 0x2AU +#define SCSI_WRITE12 0xAAU +#define SCSI_WRITE16 0x8AU + +#define SCSI_VERIFY10 0x2FU +#define SCSI_VERIFY12 0xAFU +#define SCSI_VERIFY16 0x8FU + +#define SCSI_SEND_DIAGNOSTIC 0x1DU +#define SCSI_READ_FORMAT_CAPACITIES 0x23U + +#define INVALID_CDB 0x20U +#define INVALID_FIELED_IN_COMMAND 0x24U +#define PARAMETER_LIST_LENGTH_ERROR 0x1AU +#define INVALID_FIELD_IN_PARAMETER_LIST 0x26U +#define ADDRESS_OUT_OF_RANGE 0x21U +#define MEDIUM_NOT_PRESENT 0x3AU +#define MEDIUM_HAVE_CHANGED 0x28U +#define WRITE_PROTECTED 0x27U +#define UNRECOVERED_READ_ERROR 0x11U +#define WRITE_FAULT 0x03U + +#define READ_FORMAT_CAPACITY_DATA_LEN 0x0CU +#define READ_CAPACITY10_DATA_LEN 0x08U +#define MODE_SENSE10_DATA_LEN 0x08U +#define MODE_SENSE6_DATA_LEN 0x04U +#define READ_TOC_CMD_LEN 0x14U +#define REQUEST_SENSE_DATA_LEN 0x12U +#define STANDARD_INQUIRY_DATA_LEN 0x24U +#define BLKVFY 0x04U + +enum sense_state { + NO_SENSE = 0U, + RECOVERED_ERROR, + NOT_READY, + MEDIUM_ERROR, + HARDWARE_ERROR, + ILLEGAL_REQUEST, + UNIT_ATTENTION, + DATA_PROTECT, + BLANK_CHECK, + VENDOR_SPECIFIC, + COPY_ABORTED, + ABORTED_COMMAND, + RESERVED, + VOLUME_OVERFLOW, + MISCOMPARE +}; + +typedef struct { + uint8_t SenseKey; + uint32_t Information; + uint8_t ASC; + uint8_t ASCQ; +} msc_scsi_sense; + +#endif /* __MSC_SCSI_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/class/msc/usb_msc.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/class/msc/usb_msc.h new file mode 100644 index 000000000..0629156c1 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/class/msc/usb_msc.h @@ -0,0 +1,68 @@ +/*! + \file usb_msc.h + \brief definitions for the USB MSC class + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_MSC_H +#define __USB_MSC_H + +#include "usb_ch9_std.h" + +/* mass storage device class code */ +#define USB_CLASS_MSC 0x08U + +/* mass storage subclass code */ +#define USB_MSC_SUBCLASS_RBC 0x01U +#define USB_MSC_SUBCLASS_ATAPI 0x02U +#define USB_MSC_SUBCLASS_UFI 0x04U +#define USB_MSC_SUBCLASS_SCSI 0x06U +#define USB_MSC_SUBCLASS_LOCKABLE 0x07U +#define USB_MSC_SUBCLASS_IEEE1667 0x08U + +/* mass storage interface class control protocol codes */ +#define USB_MSC_PROTOCOL_CBI 0x00U +#define USB_MSC_PROTOCOL_CBI_ALT 0x01U +#define USB_MSC_PROTOCOL_BBB 0x50U + +/* mass storage request codes */ +#define USB_MSC_REQ_CODES_ADSC 0x00U +#define USB_MSC_REQ_CODES_GET 0xFCU +#define USB_MSC_REQ_CODES_PUT 0xFDU +#define USB_MSC_REQ_CODES_GML 0xFEU +#define USB_MSC_REQ_CODES_BOMSR 0xFFU + +#define BBB_GET_MAX_LUN 0xFEU +#define BBB_RESET 0xFFU + +#define SCSI_CMD_LENGTH 16U + +#endif /* __USB_MSC_H */ diff --git a/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/common/usb_ch9_std.h b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/common/usb_ch9_std.h new file mode 100644 index 000000000..c6bc7bbe8 --- /dev/null +++ b/platform/vendor_bsp/gd/GD32F3x0_Firmware_Library/GD32F3x0_usbfs_library/ustd/common/usb_ch9_std.h @@ -0,0 +1,248 @@ +/*! + \file usb_ch9_std.h + \brief USB 2.0 standard defines + + \version 2020-08-13, V3.0.0, firmware for GD32F3x0 +*/ + +/* + Copyright (c) 2020, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef __USB_CH9_STD_H +#define __USB_CH9_STD_H + +#include "usb_conf.h" + +#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /*!< USB device qualifier descriptor length */ +#define USB_DEV_DESC_LEN 0x12U /*!< USB device descriptor length */ +#define USB_CFG_DESC_LEN 0x09U /*!< USB configuration descriptor length */ +#define USB_ITF_DESC_LEN 0x09U /*!< USB interface descriptor length */ +#define USB_EP_DESC_LEN 0x07U /*!< USB endpoint descriptor length */ +#define USB_IAD_DESC_LEN 0x08U /*!< USB IAD descriptor length */ +#define USB_OTG_DESC_LEN 0x03U /*!< USB device OTG descriptor length */ + +#define USB_SETUP_PACKET_LEN 0x08U /*!< USB setup packet length */ + +/* bit 7 of bmRequestType: data phase transfer direction */ +#define USB_TRX_MASK 0x80U /*!< USB transfer direction mask */ +#define USB_TRX_OUT 0x00U /*!< USB transfer OUT direction */ +#define USB_TRX_IN 0x80U /*!< USB transfer IN direction */ + +/* bit 6..5 of bmRequestType: request type */ +#define USB_REQTYPE_STRD 0x00U /*!< USB standard request */ +#define USB_REQTYPE_CLASS 0x20U /*!< USB class request */ +#define USB_REQTYPE_VENDOR 0x40U /*!< USB vendor request */ +#define USB_REQTYPE_MASK 0x60U /*!< USB request mask */ + +#define USBD_BUS_POWERED 0x00U /*!< USB bus power supply */ +#define USBD_SELF_POWERED 0x01U /*!< USB self power supply */ + +#define USB_STATUS_REMOTE_WAKEUP 2U /*!< USB is in remote wakeup status */ +#define USB_STATUS_SELF_POWERED 1U /*!< USB is in self powered status */ + +/* bit 4..0 of bmRequestType: recipient type */ +enum _usb_recp_type { + USB_RECPTYPE_DEV = 0x0U, /*!< USB device request type */ + USB_RECPTYPE_ITF = 0x1U, /*!< USB interface request type */ + USB_RECPTYPE_EP = 0x2U, /*!< USB endpoint request type */ + USB_RECPTYPE_MASK = 0x3U /*!< USB request type mask */ +}; + +/* bRequest value */ +enum _usb_request { + USB_GET_STATUS = 0x0U, /*!< USB get status request */ + USB_CLEAR_FEATURE = 0x1U, /*!< USB clear feature request */ + USB_RESERVED2 = 0x2U, + USB_SET_FEATURE = 0x3U, /*!< USB set feature request */ + USB_RESERVED4 = 0x4U, + USB_SET_ADDRESS = 0x5U, /*!< USB set address request */ + USB_GET_DESCRIPTOR = 0x6U, /*!< USB get descriptor request */ + USB_SET_DESCRIPTOR = 0x7U, /*!< USB set descriptor request */ + USB_GET_CONFIGURATION = 0x8U, /*!< USB get configuration request */ + USB_SET_CONFIGURATION = 0x9U, /*!< USB set configuration request */ + USB_GET_INTERFACE = 0xAU, /*!< USB get interface request */ + USB_SET_INTERFACE = 0xBU, /*!< USB set interface request */ + USB_SYNCH_FRAME = 0xCU /*!< USB synchronize frame request */ +}; + +/* descriptor types of USB specifications */ +enum _usb_desctype { + USB_DESCTYPE_DEV = 0x1U, /*!< USB device descriptor type */ + USB_DESCTYPE_CONFIG = 0x2U, /*!< USB configuration descriptor type */ + USB_DESCTYPE_STR = 0x3U, /*!< USB string descriptor type */ + USB_DESCTYPE_ITF = 0x4U, /*!< USB interface descriptor type */ + USB_DESCTYPE_EP = 0x5U, /*!< USB endpoint descriptor type */ + USB_DESCTYPE_DEV_QUALIFIER = 0x6U, /*!< USB device qualifier descriptor type */ + USB_DESCTYPE_OTHER_SPD_CONFIG = 0x7U, /*!< USB other speed configuration descriptor type */ + USB_DESCTYPE_ITF_POWER = 0x8U, /*!< USB interface power descriptor type */ + USB_DESCTYPE_IAD = 0xBU, /*!< USB interface association descriptor type */ + USB_DESCTYPE_BOS = 0xFU /*!< USB BOS descriptor type */ +}; + +/* USB Endpoint Descriptor bmAttributes bit definitions */ +/* bits 1..0 : transfer type */ +enum _usbx_type { + USB_EP_ATTR_CTL = 0x0U, /*!< USB control transfer type */ + USB_EP_ATTR_ISO = 0x1U, /*!< USB Isochronous transfer type */ + USB_EP_ATTR_BULK = 0x2U, /*!< USB Bulk transfer type */ + USB_EP_ATTR_INT = 0x3U /*!< USB Interrupt transfer type */ +}; + +/* bits 3..2 : Sync type (only if ISOCHRONOUS) */ +#define USB_EP_ATTR_NOSYNC 0x00U /*!< No Synchronization */ +#define USB_EP_ATTR_ASYNC 0x04U /*!< Asynchronous */ +#define USB_EP_ATTR_ADAPTIVE 0x08U /*!< Adaptive */ +#define USB_EP_ATTR_SYNC 0x0CU /*!< Synchronous */ +#define USB_EP_ATTR_SYNCTYPE 0x0CU /*!< Synchronous type */ + +/* bits 5..4 : usage type (only if ISOCHRONOUS) */ +#define USB_EP_ATTR_DATA 0x00U /*!< Data endpoint */ +#define USB_EP_ATTR_FEEDBACK 0x10U /*!< Feedback endpoint */ +#define USB_EP_ATTR_IMPLICIT_FEEDBACK_DATA 0x20U /*!< Implicit feedback Data endpoint */ +#define USB_EP_ATTR_USAGETYPE 0x30U /*!< Usage type */ + +/* endpoint max packet size bits12..11 */ +#define USB_EP_MPS_ADD_0 (0x00 << 11) /*!< None(1 transaction per microframe */ +#define USB_EP_MPS_ADD_1 (0x01 << 11) /*!< 1 additional(2 transaction per microframe */ +#define USB_EP_MPS_ADD_2 (0x02 << 11) /*!< 2 additional(3 transaction per microframe */ + +#define FEATURE_SELECTOR_EP 0x00U /*!< USB endpoint feature selector */ +#define FEATURE_SELECTOR_DEV 0x01U /*!< USB device feature selector */ +#define FEATURE_SELECTOR_REMOTEWAKEUP 0x01U /*!< USB feature selector remote wakeup */ + +#define BYTE_SWAP(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ + (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) + +#define BYTE_LOW(x) ((uint8_t)((x) & 0x00FFU)) +#define BYTE_HIGH(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) + +#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b)) + +#define USB_DEFAULT_CONFIG 0U + +/* USB classes */ +#define USB_CLASS_HID 0x03U /*!< USB HID class */ +#define USB_CLASS_MSC 0x08U /*!< USB MSC class */ + +/* use the following values when USB host need to get descriptor */ +#define USBH_DESC(x) (((x)<< 8U) & 0xFF00U) + +/* as per USB specs 9.2.6.4 :standard request with data request timeout: 5sec + standard request with no data stage timeout : 50ms */ +#define DATA_STAGE_TIMEOUT 5000U /*!< USB data stage timeout*/ +#define NODATA_STAGE_TIMEOUT 50U /*!< USB no data stage timeout*/ + +#pragma pack(1) + +/* USB standard device request structure */ +typedef struct _usb_req { + uint8_t bmRequestType; /*!< type of request */ + uint8_t bRequest; /*!< request of setup packet */ + uint16_t wValue; /*!< value of setup packet */ + uint16_t wIndex; /*!< index of setup packet */ + uint16_t wLength; /*!< length of setup packet */ +} usb_req; + +/* USB setup packet define */ +typedef union _usb_setup { + uint8_t data[8]; + + usb_req req; +} usb_setup; + +/* USB descriptor defines */ + +typedef struct _usb_desc_header { + uint8_t bLength; /*!< size of the descriptor */ + uint8_t bDescriptorType; /*!< type of the descriptor */ +} usb_desc_header; + +typedef struct _usb_desc_dev { + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint16_t bcdUSB; /*!< BCD of the supported USB specification */ + uint8_t bDeviceClass; /*!< USB device class */ + uint8_t bDeviceSubClass; /*!< USB device subclass */ + uint8_t bDeviceProtocol; /*!< USB device protocol */ + uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ + uint16_t idVendor; /*!< vendor ID for the USB product */ + uint16_t idProduct; /*!< unique product ID for the USB product */ + uint16_t bcdDevice; /*!< product release (version) number */ + uint8_t iManufacturer; /*!< string index for the manufacturer's name */ + uint8_t iProduct; /*!< string index for the product name/details */ + uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ + uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ +} usb_desc_dev; + +typedef struct _usb_desc_config { + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ + uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ + uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ + uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ + uint8_t bmAttributes; /*!< configuration attributes */ + uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ +} usb_desc_config; + +typedef struct _usb_desc_itf { + usb_desc_header header; /*!< descriptor header, including type and size */ + + uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ + uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ + uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ + uint8_t bInterfaceClass; /*!< interface class ID */ + uint8_t bInterfaceSubClass; /*!< interface subclass ID */ + uint8_t bInterfaceProtocol; /*!< interface protocol ID */ + uint8_t iInterface; /*!< index of the string descriptor describing the interface */ +} usb_desc_itf; + +typedef struct _usb_desc_ep { + usb_desc_header header; /*!< descriptor header, including type and size. */ + + uint8_t bEndpointAddress; /*!< logical address of the endpoint */ + uint8_t bmAttributes; /*!< endpoint attributes */ + uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ + uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */ +} usb_desc_ep; + +typedef struct _usb_desc_LANGID { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint16_t wLANGID; /*!< LANGID code */ +} usb_desc_LANGID; + +typedef struct _usb_desc_str { + usb_desc_header header; /*!< descriptor header, including type and size. */ + uint16_t unicode_string[64]; /*!< unicode string data */ +} usb_desc_str; + +#pragma pack() + +/* compute string descriptor length */ +#define USB_STRING_LEN(unicode_chars) (sizeof(usb_desc_header) + ((unicode_chars) << 1U)) + +#endif /* __USB_CH9_STD_H */ diff --git a/platform/vendor_bsp/st/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h b/platform/vendor_bsp/st/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h index 610abfdc5..65529a4d3 100644 --- a/platform/vendor_bsp/st/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +++ b/platform/vendor_bsp/st/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -213,12 +212,12 @@ typedef enum * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ /** @@ -248,10 +247,10 @@ typedef struct __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ - __IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ + __IO uint32_t PCSEL_RES0; /*!< Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ __IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ __IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ - __IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ + __IO uint32_t RES1_TR3; /*!< Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ uint32_t RESERVED2; /*!< Reserved, 0x02C */ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ @@ -928,8 +927,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -2700,6 +2699,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2749,6 +2757,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -10803,7 +10814,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -10813,6 +10824,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -10821,12 +10840,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -19268,8 +19281,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -214,12 +213,12 @@ typedef enum * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ /** @@ -249,10 +248,10 @@ typedef struct __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ - __IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ + __IO uint32_t PCSEL_RES0; /*!< Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ __IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ __IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ - __IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ + __IO uint32_t RES1_TR3; /*!< Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ uint32_t RESERVED2; /*!< Reserved, 0x02C */ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ @@ -929,8 +928,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -2701,6 +2700,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2750,6 +2758,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -10804,7 +10815,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -10814,6 +10825,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -10822,12 +10841,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -19280,8 +19293,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -216,12 +215,12 @@ typedef enum * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ /** @@ -251,10 +250,10 @@ typedef struct __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ - __IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ + __IO uint32_t PCSEL_RES0; /*!< Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ __IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ __IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ - __IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ + __IO uint32_t RES1_TR3; /*!< Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ uint32_t RESERVED2; /*!< Reserved, 0x02C */ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ @@ -931,8 +930,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -2835,6 +2834,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2884,6 +2892,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -11057,7 +11068,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -11067,6 +11078,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -11075,12 +11094,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -19755,8 +19768,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -217,12 +216,12 @@ typedef enum * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ /** @@ -252,10 +251,10 @@ typedef struct __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ - __IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ + __IO uint32_t PCSEL_RES0; /*!< Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ __IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ __IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ - __IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ + __IO uint32_t RES1_TR3; /*!< Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ uint32_t RESERVED2; /*!< Reserved, 0x02C */ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ @@ -932,8 +931,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -2836,6 +2835,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2885,6 +2893,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -11058,7 +11069,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -11068,6 +11079,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -11076,12 +11095,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -19767,8 +19780,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -216,12 +215,12 @@ typedef enum * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ /** @@ -251,10 +250,10 @@ typedef struct __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ - __IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ + __IO uint32_t PCSEL_RES0; /*!< Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ __IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ __IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ - __IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ + __IO uint32_t RES1_TR3; /*!< Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ uint32_t RESERVED2; /*!< Reserved, 0x02C */ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ @@ -931,8 +930,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -2835,6 +2834,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2884,6 +2892,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -11057,7 +11068,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -11067,6 +11078,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -11075,12 +11094,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -19755,8 +19768,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -217,12 +216,12 @@ typedef enum * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ /** @@ -252,10 +251,10 @@ typedef struct __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ - __IO uint32_t PCSEL_RES0; /*!< Rserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ + __IO uint32_t PCSEL_RES0; /*!< Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ __IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ __IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ - __IO uint32_t RES1_TR3; /*!< Rserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ + __IO uint32_t RES1_TR3; /*!< Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ uint32_t RESERVED2; /*!< Reserved, 0x02C */ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ @@ -932,8 +931,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -2836,6 +2835,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2885,6 +2893,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -11058,7 +11069,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -11068,6 +11079,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -11076,12 +11095,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -19767,8 +19780,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -212,12 +211,12 @@ typedef enum * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ /** @@ -885,8 +884,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -1638,7 +1637,7 @@ typedef struct __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ - __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */ + __IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */ __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ @@ -2618,6 +2617,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2667,6 +2675,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -10568,7 +10579,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -10578,6 +10589,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -10586,12 +10605,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -18698,8 +18711,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -215,12 +214,12 @@ typedef enum * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ /** @@ -888,8 +887,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -1725,7 +1724,7 @@ typedef struct __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ - __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */ + __IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */ __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ @@ -2713,6 +2712,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2762,6 +2770,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -10663,7 +10674,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -10673,6 +10684,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -10681,12 +10700,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -19346,8 +19359,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ +} ADC_TypeDef; + + +typedef struct +{ +__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ +uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ +__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ +__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ +__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief ART + */ + +typedef struct +{ + __IO uint32_t CTR; /*!< ART accelerator - control register */ +}ART_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register, Address offset: 0x38 */ + __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */ + __IO uint32_t APB1LFZ2; /*!< Debug MCU APB1LFZ2 freeze register, Address offset: 0x40 */ + __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */ + __IO uint32_t APB1HFZ2; /*!< Debug MCU APB1LFZ2 freeze register, Address offset: 0x48 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register, Address offset: 0x50 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register, Address offset: 0x58 */ + +}DBGMCU_TypeDef; +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ + __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */ +} BDMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} BDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x6C */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ +__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ +__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ +__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ +__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */ +__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */ +__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */ +uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */ +__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ +__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ +__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ +__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */ +__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */ +__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */ +uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */ +__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ +__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ +__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ +__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */ +__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */ +__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */ +uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */ +uint32_t RESERVED4; /*!< Reserved, 0x8C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */ +uint32_t RESERVED5; /*!< Reserved, 0x9C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */ +uint32_t RESERVED6[5]; /*!< Reserved, 0xAC to 0xBC */ +__IO uint32_t C2IMR1; /*!< EXTI Interrupt mask register, Address offset: 0xC0 */ +__IO uint32_t C2EMR1; /*!< EXTI Event mask register, Address offset: 0xC4 */ +__IO uint32_t C2PR1; /*!< EXTI Pending register, Address offset: 0xC8 */ +uint32_t RESERVED7; /*!< Reserved, 0xCC */ +__IO uint32_t C2IMR2; /*!< EXTI Interrupt mask register, Address offset: 0xD0 */ +__IO uint32_t C2EMR2; /*!< EXTI Event mask register, Address offset: 0xD4 */ +__IO uint32_t C2PR2; /*!< EXTI Pending register, Address offset: 0xD8 */ +uint32_t RESERVED8; /*!< Reserved, 0xDC */ +__IO uint32_t C2IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xE0 */ +__IO uint32_t C2EMR3; /*!< EXTI Event mask register, Address offset: 0xE4 */ +__IO uint32_t C2PR3; /*!< EXTI Pending register, Address offset: 0xE8 */ + +}EXTI_TypeDef; + +/** + * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 + * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. + * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) + * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only + */ + +typedef struct +{ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */ +uint32_t RESERVED1; /*!< Reserved, 0x0C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */ +uint32_t RESERVED2; /*!< Reserved, 0x1C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */ +}EXTI_Core_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */ + __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */ + __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */ + __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */ + __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */ + __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */ + __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */ + __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */ + __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */ + __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */ + __IO uint32_t BOOT7_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */ + __IO uint32_t BOOT7_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */ + __IO uint32_t BOOT4_CUR; /*!< Flash Current Boot Address for M4 Core Register, Address offset: 0x48 */ + __IO uint32_t BOOT4_PRG; /*!< Flash Boot Address to Program for M4 Core Register, Address offset: 0x4C */ + __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */ + __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */ + __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */ + __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */ + __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */ + uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */ + __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */ + uint32_t RESERVED2; /*!< Reserved, 0x108 */ + __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */ + __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */ + __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */ + __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */ + __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */ + __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */ + __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */ + __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */ + __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */ + uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */ + __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */ + __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */ + __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */ + __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */ + __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FMC_Bank2_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 and 6 + */ + + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */ + __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */ + __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */ + __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */ + __IO uint32_t PWRCR; /*!< PWR control register, Address offset: 0x2C */ + uint32_t RESERVED3[61]; /*!< Reserved, 0x30-0x120 */ + __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */ + uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */ + __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */ + __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */ + __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */ + __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */ + __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */ + __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */ + __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */ + __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */ + __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */ + __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */ + __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */ + __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */ + __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */ + __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */ + __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */ + __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */ + __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */ + __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */ + +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */ + __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ + __IO uint32_t CPU2CR; /*!< PWR CPU2 control register, Address offset: 0x14 */ + __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */ + __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */ + __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */ + __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */ + __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */ + __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */ + __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */ + uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */ + __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */ + __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */ + uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */ + +} RCC_TypeDef; + +typedef struct +{ + __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0x00 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x04 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x08 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x0C */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0x10 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x14 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0x18 */ + __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0x1C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x20 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0x24 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0x3C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x40 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x44 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x48 */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x4C */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x50 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x54 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x58 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x5C */ + uint32_t RESERVED10[4]; /*!< Reserved, 0x60-0x6C Address offset: 0x60 */ + +} RCC_Core_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1A */ +} SPDIFRX_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ + __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ + uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */ + __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */ +} SDMMC_TypeDef; + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ + +typedef struct +{ + __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM Interrupt 0 enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM Interrupt 0 clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM Interrupt 0 Status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM Interrupt 0 Masked Status register , Address offset: 10Ch */ + __IO uint32_t C2IER; /*!< HSEM Interrupt 1 enable register , Address offset: 110h */ + __IO uint32_t C2ICR; /*!< HSEM Interrupt 1 clear register , Address offset: 114h */ + __IO uint32_t C2ISR; /*!< HSEM Interrupt 1 Status register , Address offset: 118h */ + __IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch */ + uint32_t Reserved[8]; /* Reserved Address offset: 120h-13Ch*/ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ + +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ + +} SPI_TypeDef; +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED1; /*!< Reserved, 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */ +} COMPOPT_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; +/** + * @} + */ + + + +/** + * @brief High resolution Timer (HRTIM) + */ +/* HRTIM master registers definition */ +typedef struct +{ + __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */ + __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */ + __IO uint32_t MICR; /*!< HRTIM Master Timer interrupt clear register, Address offset: 0x08 */ + __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */ + __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */ + __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */ + __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */ + __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */ + uint32_t RESERVED0; /*!< Reserved, 0x20 */ + __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */ + __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */ + __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */ + uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */ +}HRTIM_Master_TypeDef; + +/* HRTIM Timer A to E registers definition */ +typedef struct +{ + __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */ + __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */ + __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */ + __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */ + __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */ + __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */ + __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */ + __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */ + __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */ + __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */ + __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */ + __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */ + __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */ + __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */ + __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */ + __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */ + __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */ + __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */ + __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */ + __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */ + __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */ + __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */ + __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */ + __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */ + __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */ + __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */ +}HRTIM_Timerx_TypeDef; + +/* HRTIM common register definition */ +typedef struct +{ + __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */ + __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */ + __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */ + __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ + __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ + __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ + __IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */ + __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ + __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ + __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ + __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */ + __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */ + __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */ + __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */ + __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */ + __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */ + __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */ + __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */ + __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */ + __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */ + __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */ + __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */ + __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */ + __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */ +}HRTIM_Common_TypeDef; + +/* HRTIM register definition */ +typedef struct { + HRTIM_Master_TypeDef sMasterRegs; + HRTIM_Timerx_TypeDef sTimerxRegs[5]; + uint32_t RESERVED0[32]; + HRTIM_Common_TypeDef sCommonRegs; +}HRTIM_TypeDef; +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /* User HW config1 044h*/ + __IO uint32_t GHWCFG2; /* User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + + +/** + * @brief Global Programmer View + */ + +typedef struct +{ + uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */ + __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */ + uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */ + uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */ + uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */ + __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */ + __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */ + __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */ + __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */ + __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */ + __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */ + __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */ + __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */ + __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */ + __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */ + __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */ + uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */ + __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */ + uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */ + __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */ + uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */ + __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */ + __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */ + uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */ + __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */ + uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */ + __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */ + uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */ + __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */ + uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */ + __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */ + uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */ + __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */ + uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */ + __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */ + uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */ + __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */ + __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */ + uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */ + __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */ + uint32_t RESERVED17[59334]; /*!< Reserved, Address offset: 0x810C-0x42020 */ + __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */ + __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */ + uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */ + __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */ + __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */ + __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */ + uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */ + __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */ + __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */ + __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */ + uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */ + __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */ + __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */ + uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */ + __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */ + __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */ + __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */ + uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */ + __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */ + __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */ + __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */ + uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */ + __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */ + __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */ + __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */ + uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */ + __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */ + __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */ + __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */ + uint32_t RESERVED25[1021]; /*!< Reserved, Address offset: 0x4710C-0x480FC */ + __IO uint32_t AXI_INI7_READ_QOS; /*!< AXI interconnect - INI 7 read QoS register, Address offset: 0x48100 */ + __IO uint32_t AXI_INI7_WRITE_QOS; /*!< AXI interconnect - INI 7 write QoS register, Address offset: 0x48104 */ + __IO uint32_t AXI_INI7_FN_MOD; /*!< AXI interconnect - INI 7 issuing functionality modification register, Address offset: 0x48108 */ + +} GPV_TypeDef; + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */ +#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */ +#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */ +#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */ +#define D1_AXISRAM_BASE (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */ + +#define D2_AXISRAM_BASE (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */ +#define D2_AHBSRAM_BASE (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */ + +#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */ +#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */ + +#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */ +#define QSPI_BASE (0x90000000UL) /*!< Base address of : QSPI memories accessible over AXI */ + +#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */ +#define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */ +#define FLASH_END (0x081FFFFFUL) /*!< FLASH end address */ + +/* Legacy define */ +#define FLASH_BASE FLASH_BANK1_BASE + +/*!< Device electronic signature memory map */ +#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */ + + +/*!< Peripheral memory map */ +#define D2_APB1PERIPH_BASE PERIPH_BASE +#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) + +#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) + +#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< Legacy Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< D1_AHB1PERIPH peripherals */ + +#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL) +#define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000UL) +#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL) +#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL) +#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL) +#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL) +#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL) + +/*!< D2_AHB1PERIPH peripherals */ + +#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL) +#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL) +#define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400UL) +#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) + +/*!< USB registers base address */ +#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL) +#define USB2_OTG_FS_PERIPH_BASE (0x40080000UL) +#define USB_OTG_GLOBAL_BASE (0x000UL) +#define USB_OTG_DEVICE_BASE (0x800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL) +#define USB_OTG_EP_REG_SIZE (0x20UL) +#define USB_OTG_HOST_BASE (0x400UL) +#define USB_OTG_HOST_PORT_BASE (0x440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL) +#define USB_OTG_PCGCCTL_BASE (0xE00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< D2_AHB2PERIPH peripherals */ + +#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL) +#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL) +#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL) +#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL) + +/*!< D3_AHB1PERIPH peripherals */ +#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL) +#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL) +#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL) +#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL) +#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL) +#define RCC_C1_BASE (RCC_BASE + 0x130UL) +#define RCC_C2_BASE (RCC_BASE + 0x190UL) +#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL) +#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL) +#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL) +#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL) +#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL) +#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL) +#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL) +#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL) + +/*!< D1_APB1PERIPH peripherals */ +#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL) +#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL) + +/*!< D2_APB1PERIPH peripherals */ +#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL) + +#define WWDG2_BASE (D2_APB1PERIPH_BASE + 0x2C00UL) + +#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL) +#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL) +#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL) +#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL) +#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL) +#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL) +#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL) +#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL) +#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL) + +/*!< D2_APB2PERIPH peripherals */ + +#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL) +#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL) +#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) +#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL) +#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL) +#define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL) +#define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL) +#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL) +#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL) +#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL) +#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL) +#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL) +#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL) +#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL) +#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL) + + +/*!< D3_APB1PERIPH peripherals */ +#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL) +#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL) +#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL) +#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL) +#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL) +#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL) +#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL) +#define COMP1_BASE (COMP12_BASE + 0x0CUL) +#define COMP2_BASE (COMP12_BASE + 0x10UL) +#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL) +#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL) + +#define IWDG2_BASE (D3_APB1PERIPH_BASE + 0x4C00UL) + +#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL) +#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL) +#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL) + + + + +#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL) +#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL) +#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL) +#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL) +#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL) +#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL) +#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL) +#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL) + +#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE) +#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL) +#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL) +#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL) +#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL) +#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL) +#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL) +#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL) + +#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL) +#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL) +#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL) +#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL) +#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL) +#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL) +#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL) +#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL) + +#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL) +#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL) + +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) + +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) +#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL) +#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL) +#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL) +#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL) +#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL) +#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL) +#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL) +#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL) +#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL) +#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL) +#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL) +#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL) +#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL) +#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL) +#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL) +#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL) +#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL) +#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL) +#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL) + +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL) + +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL) +#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL) +#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL) +#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL) +#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL) + +#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL) +#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL) + + + +#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE) + +#define WWDG2 ((WWDG_TypeDef *) WWDG2_BASE) +#define IWDG2 ((IWDG_TypeDef *) IWDG2_BASE) + +#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) + + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) +#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE) +#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE) +#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE) +#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE) +#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE) +#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE) +#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#define SAI3 ((SAI_TypeDef *) SAI3_BASE) +#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE) +#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE) +#define SAI4 ((SAI_TypeDef *) SAI4_BASE) +#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE) +#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE) + +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE) +#define RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE) + +#define ART ((ART_TypeDef *) ART_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) + +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) + +#define BDMA ((BDMA_TypeDef *) BDMA_BASE) +#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE) +#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE) +#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE) +#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE) +#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE) +#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE) +#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE) +#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE) + +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE) + +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE) +#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE) +#define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE) +#define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE) + +#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE) +#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE) +#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE) + +#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE) +#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE) +#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE) +#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE) +#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE) +#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE) +#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE) +#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE) +#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE) + + +#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE) +#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE) +#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE) +#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE) +#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE) +#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE) +#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE) +#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE) + +#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE) +#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) + + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) +#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE) +#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE) +#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE) +#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) + + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) +#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE) +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#if defined(CORE_CM4) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110UL)) +#else /* CORE_CM7 */ +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL)) +#endif /* CORE_CM4 */ + +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) + +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) + +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define MDMA ((MDMA_TypeDef *)MDMA_BASE) +#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE) +#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE) +#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE) +#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE) +#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE) +#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE) +#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE) +#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE) +#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE) +#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE) +#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE) +#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE) +#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE) +#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE) +#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE) +#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE) + + +#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE) +#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE) + +/* Legacy defines */ +#define USB_OTG_HS USB1_OTG_HS +#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE +#define USB_OTG_FS USB2_OTG_FS +#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE + +#define GPV ((GPV_TypeDef *) GPV_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_BOOST_Pos (8U) +#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */ +#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */ +#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */ +#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ +#define ADC_CR_LINCALRDYW1_Pos (22U) +#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */ +#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */ +#define ADC_CR_LINCALRDYW2_Pos (23U) +#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */ +#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */ +#define ADC_CR_LINCALRDYW3_Pos (24U) +#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */ +#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */ +#define ADC_CR_LINCALRDYW4_Pos (25U) +#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */ +#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */ +#define ADC_CR_LINCALRDYW5_Pos (26U) +#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */ +#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */ +#define ADC_CR_LINCALRDYW6_Pos (27U) +#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */ +#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR_DMNGT_Pos (0U) +#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR_RES_Pos (2U) +#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_RSHIFT1_Pos (11U) +#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ +#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ +#define ADC_CFGR2_RSHIFT2_Pos (12U) +#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */ +#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */ +#define ADC_CFGR2_RSHIFT3_Pos (13U) +#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */ +#define ADC_CFGR2_RSHIFT4_Pos (14U) +#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ +#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_SSATE_Pos (31U) +#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */ + + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ +#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_SSATE_Pos (31U) +#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */ + + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ +#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_SSATE_Pos (31U) +#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */ + + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ +#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_SSATE_Pos (31U) +#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */ + + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_LINCALFACT_Pos (0U) +#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */ +#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + + +#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* ART accelerator */ +/* */ +/******************************************************************************/ +/******************* Bit definition for ART_CTR register ********************/ +#define ART_CTR_EN_Pos (0U) +#define ART_CTR_EN_Msk (0x1UL << ART_CTR_EN_Pos) /*!< 0x00000001 */ +#define ART_CTR_EN ART_CTR_EN_Msk /*!< Cache enable*/ + +#define ART_CTR_PCACHEADDR_Pos (8U) +#define ART_CTR_PCACHEADDR_Msk (0xFFFUL << ART_CTR_PCACHEADDR_Pos) /*!< 0x000FFF00 */ +#define ART_CTR_PCACHEADDR ART_CTR_PCACHEADDR_Msk /*!< Cacheable page index */ + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1) /* 1 MB */ +#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ +#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */ +#define DUAL_BANK /* Dual-bank Flash */ + +/******************* Bits definition for FLASH_ACR register **********************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000UL) +#define FLASH_ACR_LATENCY_1WS (0x00000001UL) +#define FLASH_ACR_LATENCY_2WS (0x00000002UL) +#define FLASH_ACR_LATENCY_3WS (0x00000003UL) +#define FLASH_ACR_LATENCY_4WS (0x00000004UL) +#define FLASH_ACR_LATENCY_5WS (0x00000005UL) +#define FLASH_ACR_LATENCY_6WS (0x00000006UL) +#define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ +#define FLASH_ACR_LATENCY_8WS (0x00000008UL) +#define FLASH_ACR_LATENCY_9WS (0x00000009UL) +#define FLASH_ACR_LATENCY_10WS (0x0000000AUL) +#define FLASH_ACR_LATENCY_11WS (0x0000000BUL) +#define FLASH_ACR_LATENCY_12WS (0x0000000CUL) +#define FLASH_ACR_LATENCY_13WS (0x0000000DUL) +#define FLASH_ACR_LATENCY_14WS (0x0000000EUL) +#define FLASH_ACR_LATENCY_15WS (0x0000000FUL) +/******************* Bits definition for FLASH_CR register ***********************/ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Internal buffer control bit */ +#define FLASH_CR_SER_Pos (2U) +#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_PSIZE_Pos (4U) +#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000030 */ +#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk /*!< Program size */ +#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000010 */ +#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000020 */ +#define FLASH_CR_FW_Pos (6U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000040 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ +#define FLASH_CR_START_Pos (7U) +#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000080 */ +#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ +#define FLASH_CR_SNB_Pos (8U) +#define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos) /*!< 0x00000700 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ +#define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ +#define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ +#define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ +#define FLASH_CR_CRC_EN_Pos (15U) +#define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) /*!< 0x00008000 */ +#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk /*!< CRC control bit */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-program interrupt control bit */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ +#define FLASH_CR_INCERRIE_Pos (21U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00200000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ +#define FLASH_CR_OPERRIE_Pos (22U) +#define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos) /*!< 0x00400000 */ +#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk /*!< Write/erase error interrupt enable bit */ +#define FLASH_CR_RDPERRIE_Pos (23U) +#define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk /*!< Read protection error interrupt enable bit */ +#define FLASH_CR_RDSERRIE_Pos (24U) +#define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk /*!< Secure error interrupt enable bit */ +#define FLASH_CR_SNECCERRIE_Pos (25U) +#define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk /*!< ECC single correction error interrupt enable bit */ +#define FLASH_CR_DBECCERRIE_Pos (26U) +#define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk /*!< ECC double detection error interrupt enable bit */ +#define FLASH_CR_CRCENDIE_Pos (27U) +#define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) /*!< 0x08000000 */ +#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk /*!< CRC end of calculation interrupt enable bit */ +#define FLASH_CR_CRCRDERRIE_Pos (28U) +#define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */ +#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk /*!< CRC read error interrupt enable bit */ + +/******************* Bits definition for FLASH_SR register ***********************/ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ +#define FLASH_SR_QW_Pos (2U) +#define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) /*!< 0x00000004 */ +#define FLASH_SR_QW FLASH_SR_QW_Msk /*!< Wait queue flag */ +#define FLASH_SR_CRC_BUSY_Pos (3U) +#define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) /*!< 0x00000008 */ +#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk /*!< CRC busy flag */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ +#define FLASH_SR_INCERR_Pos (21U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00200000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ +#define FLASH_SR_OPERR_Pos (22U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00400000 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Write/erase error flag */ +#define FLASH_SR_RDPERR_Pos (23U) +#define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk /*!< Read protection error flag */ +#define FLASH_SR_RDSERR_Pos (24U) +#define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) /*!< 0x01000000 */ +#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk /*!< Secure error flag */ +#define FLASH_SR_SNECCERR_Pos (25U) +#define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) /*!< 0x02000000 */ +#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk /*!< Single correction error flag */ +#define FLASH_SR_DBECCERR_Pos (26U) +#define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) /*!< 0x04000000 */ +#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk /*!< ECC double detection error flag */ +#define FLASH_SR_CRCEND_Pos (27U) +#define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) /*!< 0x08000000 */ +#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk /*!< CRC end of calculation flag */ +#define FLASH_SR_CRCRDERR_Pos (28U) +#define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) /*!< 0x10000000 */ +#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk /*!< CRC read error flag */ + +/******************* Bits definition for FLASH_CCR register *******************/ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ +#define FLASH_CCR_CLR_INCERR_Pos (21U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ +#define FLASH_CCR_CLR_OPERR_Pos (22U) +#define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */ +#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk /*!< OPERR flag clear bit */ +#define FLASH_CCR_CLR_RDPERR_Pos (23U) +#define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk /*!< RDPERR flag clear bit */ +#define FLASH_CCR_CLR_RDSERR_Pos (24U) +#define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */ +#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk /*!< RDSERR flag clear bit */ +#define FLASH_CCR_CLR_SNECCERR_Pos (25U) +#define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */ +#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk /*!< SNECCERR flag clear bit */ +#define FLASH_CCR_CLR_DBECCERR_Pos (26U) +#define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */ +#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk /*!< DBECCERR flag clear bit */ +#define FLASH_CCR_CLR_CRCEND_Pos (27U) +#define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */ +#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk /*!< CRCEND flag clear bit */ +#define FLASH_CCR_CLR_CRCRDERR_Pos (28U) +#define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */ +#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk /*!< CRCRDERR flag clear bit */ + +/******************* Bits definition for FLASH_OPTCR register *******************/ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ +#define FLASH_OPTCR_OPTSTART_Pos (1U) +#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ +#define FLASH_OPTCR_MER_Pos (4U) +#define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) /*!< 0x00000010 */ +#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk /*!< Mass erase request */ +#define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U) +#define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */ +#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ + +/******************* Bits definition for FLASH_OPTSR register ***************/ +#define FLASH_OPTSR_OPT_BUSY_Pos (0U) +#define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk /*!< Option byte change ongoing flag */ +#define FLASH_OPTSR_BOR_LEV_Pos (2U) +#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */ +#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option status bit */ +#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_IWDG1_SW_Pos (4U) +#define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk /*!< IWDG1 control mode option status bit */ +#define FLASH_OPTSR_IWDG2_SW_Pos (5U) +#define FLASH_OPTSR_IWDG2_SW_Msk (0x1UL << FLASH_OPTSR_IWDG2_SW_Pos) /*!< 0x00000020 */ +#define FLASH_OPTSR_IWDG2_SW FLASH_OPTSR_IWDG2_SW_Msk /*!< IWDG2 control mode option status bit */ +#define FLASH_OPTSR_NRST_STOP_D1_Pos (6U) +#define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk /*!< D1 domain DStop entry reset option status bit */ +#define FLASH_OPTSR_NRST_STBY_D1_Pos (7U) +#define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk /*!< D1 domain DStandby entry reset option status bit */ +#define FLASH_OPTSR_RDP_Pos (8U) +#define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk /*!< Readout protection level option status byte */ +#define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U) +#define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk /*!< IWDG Stop mode freeze option status bit */ +#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U) +#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk /*!< IWDG Standby mode freeze option status bit */ +#define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U) +#define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */ +#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk /*!< ST RAM size option status */ +#define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */ +#define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_SECURITY_Pos (21U) +#define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk /*!< Security enable option status bit */ +#define FLASH_OPTSR_BCM4_Pos (22U) +#define FLASH_OPTSR_BCM4_Msk (0x1UL << FLASH_OPTSR_BCM4_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_BCM4 FLASH_OPTSR_BCM4_Msk /*!< Arm Cortex-M4 boot option status bit */ +#define FLASH_OPTSR_BCM7_Pos (23U) +#define FLASH_OPTSR_BCM7_Msk (0x1UL << FLASH_OPTSR_BCM7_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_BCM7 FLASH_OPTSR_BCM7_Msk /*!< Arm Cortex-M7 boot option status bit */ +#define FLASH_OPTSR_NRST_STOP_D2_Pos (24U) +#define FLASH_OPTSR_NRST_STOP_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos) /*!< 0x01000000 */ +#define FLASH_OPTSR_NRST_STOP_D2 FLASH_OPTSR_NRST_STOP_D2_Msk /*!< D2 domain DStop entry reset option status bit */ +#define FLASH_OPTSR_NRST_STBY_D2_Pos (25U) +#define FLASH_OPTSR_NRST_STBY_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos) /*!< 0x02000000 */ +#define FLASH_OPTSR_NRST_STBY_D2 FLASH_OPTSR_NRST_STBY_D2_Msk /*!< D2 domain DStandby entry reset option status bit */ +#define FLASH_OPTSR_IO_HSLV_Pos (29U) +#define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk /*!< I/O high-speed at low-voltage status bit */ +#define FLASH_OPTSR_OPTCHANGEERR_Pos (30U) +#define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ +#define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U) +#define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk /*!< Bank swapping option status bit */ + +/******************* Bits definition for FLASH_OPTCCR register *******************/ +#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U) +#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */ +#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk /*!< OPTCHANGEERR reset bit */ + +/******************* Bits definition for FLASH_PRAR register *********************/ +#define FLASH_PRAR_PROT_AREA_START_Pos (0U) +#define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */ +#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk /*!< PCROP area start status bits */ +#define FLASH_PRAR_PROT_AREA_END_Pos (16U) +#define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */ +#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk /*!< PCROP area end status bits */ +#define FLASH_PRAR_DMEP_Pos (31U) +#define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) /*!< 0x80000000 */ +#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk /*!< PCROP protected erase enable option status bit */ + +/******************* Bits definition for FLASH_SCAR register *********************/ +#define FLASH_SCAR_SEC_AREA_START_Pos (0U) +#define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */ +#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk /*!< Secure-only area start status bits */ +#define FLASH_SCAR_SEC_AREA_END_Pos (16U) +#define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */ +#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk /*!< Secure-only area end status bits */ +#define FLASH_SCAR_DMES_Pos (31U) +#define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) /*!< 0x80000000 */ +#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk /*!< Secure access protected erase enable option status bit */ + +/******************* Bits definition for FLASH_WPSN register *********************/ +#define FLASH_WPSN_WRPSN_Pos (0U) +#define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos) /*!< 0x000000FF */ +#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk /*!< Sector write protection option status byte */ + +/******************* Bits definition for FLASH_BOOT7_CUR register ****************/ +#define FLASH_BOOT7_BCM7_ADD0_Pos (0U) +#define FLASH_BOOT7_BCM7_ADD0_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD0_Pos) /*!< 0x0000FFFF */ +#define FLASH_BOOT7_BCM7_ADD0 FLASH_BOOT7_BCM7_ADD0_Msk /*!< Arm Cortex-M7 boot address 0 */ +#define FLASH_BOOT7_BCM7_ADD1_Pos (16U) +#define FLASH_BOOT7_BCM7_ADD1_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD1_Pos) /*!< 0xFFFF0000 */ +#define FLASH_BOOT7_BCM7_ADD1 FLASH_BOOT7_BCM7_ADD1_Msk /*!< Arm Cortex-M7 boot address 1 */ + +/******************* Bits definition for FLASH_BOOT4 register ********************/ +#define FLASH_BOOT4_BCM4_ADD0_Pos (0U) +#define FLASH_BOOT4_BCM4_ADD0_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD0_Pos) /*!< 0x0000FFFF */ +#define FLASH_BOOT4_BCM4_ADD0 FLASH_BOOT4_BCM4_ADD0_Msk /*!< Arm Cortex-M4 boot address 0 */ +#define FLASH_BOOT4_BCM4_ADD1_Pos (16U) +#define FLASH_BOOT4_BCM4_ADD1_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD1_Pos) /*!< 0xFFFF0000 */ +#define FLASH_BOOT4_BCM4_ADD1 FLASH_BOOT4_BCM4_ADD1_Msk /*!< Arm Cortex-M4 boot address 1 */ + +/******************* Bits definition for FLASH_CRCCR register ********************/ +#define FLASH_CRCCR_CRC_SECT_Pos (0U) +#define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */ +#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk /*!< CRC sector number */ +#define FLASH_CRCCR_CRC_BY_SECT_Pos (8U) +#define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */ +#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk /*!< CRC sector mode select bit */ +#define FLASH_CRCCR_ADD_SECT_Pos (9U) +#define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */ +#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk /*!< CRC sector select bit */ +#define FLASH_CRCCR_CLEAN_SECT_Pos (10U) +#define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */ +#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk /*!< CRC sector list clear bit */ +#define FLASH_CRCCR_START_CRC_Pos (16U) +#define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */ +#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk /*!< CRC start bit */ +#define FLASH_CRCCR_CLEAN_CRC_Pos (17U) +#define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */ +#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk /*!< CRC clear bit */ +#define FLASH_CRCCR_CRC_BURST_Pos (20U) +#define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */ +#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk /*!< CRC burst size */ +#define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */ +#define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */ +#define FLASH_CRCCR_ALL_BANK_Pos (22U) +#define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */ +#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk /*!< CRC select bit */ + +/******************* Bits definition for FLASH_CRCSADD register ****************/ +#define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U) +#define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk /*!< CRC start address */ + +/******************* Bits definition for FLASH_CRCEADD register ****************/ +#define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U) +#define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk /*!< CRC end address */ + +/******************* Bits definition for FLASH_CRCDATA register ***************/ +#define FLASH_CRCDATA_CRC_DATA_Pos (0U) +#define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk /*!< CRC result */ + +/******************* Bits definition for FLASH_ECC_FA register *******************/ +#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U) +#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */ +#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk /*!< ECC error address */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!
© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -222,22 +221,22 @@ typedef enum * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals */ #ifdef CORE_CM4 -#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ -#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1U /*!< CM4 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM4 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ #else /* CORE_CM7 */ #ifdef CORE_CM7 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ #else /* UNKNOWN_CORE */ #error Please #define CORE_CM4 or CORE_CM7 @@ -933,8 +932,8 @@ __IO uint32_t C2PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -1800,7 +1799,7 @@ typedef struct __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ - __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */ + __IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */ __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ @@ -2807,6 +2806,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2856,6 +2864,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -10757,11 +10768,15 @@ typedef struct /* * @brief FLASH Global Defines */ +#if defined(CORE_CM4) +#define FLASH_SIZE 0x200000UL /* 2 MB */ +#else #define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U -#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */ #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */ +#endif /* CORE_CM4 */ +#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */ #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -10770,7 +10785,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -10780,6 +10795,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -10788,12 +10811,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -20004,8 +20021,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ +} ADC_TypeDef; + + +typedef struct +{ +__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ +uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ +__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ +__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ +__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief ART + */ + +typedef struct +{ + __IO uint32_t CTR; /*!< ART accelerator - control register */ +}ART_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register, Address offset: 0x38 */ + __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */ + __IO uint32_t APB1LFZ2; /*!< Debug MCU APB1LFZ2 freeze register, Address offset: 0x40 */ + __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */ + __IO uint32_t APB1HFZ2; /*!< Debug MCU APB1LFZ2 freeze register, Address offset: 0x48 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register, Address offset: 0x50 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register, Address offset: 0x58 */ + +}DBGMCU_TypeDef; +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ + __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */ +} BDMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} BDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x6C */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + +/** + * @brief DSI Controller + */ + +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED5; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */ + __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ + uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED9; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */ + uint32_t RESERVED10; /*!< Reserved, 0x42C */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ +} DSI_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ +__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ +__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ +__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ +__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */ +__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */ +__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */ +uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */ +__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ +__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ +__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ +__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */ +__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */ +__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */ +uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */ +__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ +__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ +__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ +__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */ +__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */ +__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */ +uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */ +uint32_t RESERVED4; /*!< Reserved, 0x8C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */ +uint32_t RESERVED5; /*!< Reserved, 0x9C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */ +uint32_t RESERVED6[5]; /*!< Reserved, 0xAC to 0xBC */ +__IO uint32_t C2IMR1; /*!< EXTI Interrupt mask register, Address offset: 0xC0 */ +__IO uint32_t C2EMR1; /*!< EXTI Event mask register, Address offset: 0xC4 */ +__IO uint32_t C2PR1; /*!< EXTI Pending register, Address offset: 0xC8 */ +uint32_t RESERVED7; /*!< Reserved, 0xCC */ +__IO uint32_t C2IMR2; /*!< EXTI Interrupt mask register, Address offset: 0xD0 */ +__IO uint32_t C2EMR2; /*!< EXTI Event mask register, Address offset: 0xD4 */ +__IO uint32_t C2PR2; /*!< EXTI Pending register, Address offset: 0xD8 */ +uint32_t RESERVED8; /*!< Reserved, 0xDC */ +__IO uint32_t C2IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xE0 */ +__IO uint32_t C2EMR3; /*!< EXTI Event mask register, Address offset: 0xE4 */ +__IO uint32_t C2PR3; /*!< EXTI Pending register, Address offset: 0xE8 */ + +}EXTI_TypeDef; + +/** + * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 + * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. + * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) + * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only + */ + +typedef struct +{ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */ +uint32_t RESERVED1; /*!< Reserved, 0x0C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */ +uint32_t RESERVED2; /*!< Reserved, 0x1C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */ +}EXTI_Core_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */ + __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */ + __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */ + __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */ + __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */ + __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */ + __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */ + __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */ + __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */ + __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */ + __IO uint32_t BOOT7_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */ + __IO uint32_t BOOT7_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */ + __IO uint32_t BOOT4_CUR; /*!< Flash Current Boot Address for M4 Core Register, Address offset: 0x48 */ + __IO uint32_t BOOT4_PRG; /*!< Flash Boot Address to Program for M4 Core Register, Address offset: 0x4C */ + __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */ + __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */ + __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */ + __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */ + __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */ + uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */ + __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */ + uint32_t RESERVED2; /*!< Reserved, 0x108 */ + __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */ + __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */ + __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */ + __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */ + __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */ + __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */ + __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */ + __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */ + __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */ + uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */ + __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */ + __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */ + __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */ + __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */ + __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FMC_Bank2_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 and 6 + */ + + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */ + __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */ + __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */ + __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */ + __IO uint32_t PWRCR; /*!< PWR control register, Address offset: 0x2C */ + uint32_t RESERVED3[61]; /*!< Reserved, 0x30-0x120 */ + __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */ + uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */ + __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */ + __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */ + __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */ + __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */ + __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */ + __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */ + __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */ + __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */ + __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */ + __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */ + __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */ + __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */ + __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */ + __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */ + __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */ + __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */ + __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */ + __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */ + +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */ + __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ + __IO uint32_t CPU2CR; /*!< PWR CPU2 control register, Address offset: 0x14 */ + __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */ + __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */ + __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */ + __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */ + __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */ + __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */ + __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */ + uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */ + __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */ + __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */ + uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */ + +} RCC_TypeDef; + +typedef struct +{ + __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0x00 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x04 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x08 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x0C */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0x10 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x14 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0x18 */ + __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0x1C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x20 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0x24 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0x3C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x40 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x44 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x48 */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x4C */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x50 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x54 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x58 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x5C */ + uint32_t RESERVED10[4]; /*!< Reserved, 0x60-0x6C Address offset: 0x60 */ + +} RCC_Core_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1A */ +} SPDIFRX_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ + __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ + uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */ + __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */ +} SDMMC_TypeDef; + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ + +typedef struct +{ + __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM Interrupt 0 enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM Interrupt 0 clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM Interrupt 0 Status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM Interrupt 0 Masked Status register , Address offset: 10Ch */ + __IO uint32_t C2IER; /*!< HSEM Interrupt 1 enable register , Address offset: 110h */ + __IO uint32_t C2ICR; /*!< HSEM Interrupt 1 clear register , Address offset: 114h */ + __IO uint32_t C2ISR; /*!< HSEM Interrupt 1 Status register , Address offset: 118h */ + __IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch */ + uint32_t Reserved[8]; /* Reserved Address offset: 120h-13Ch*/ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ + +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ + +} SPI_TypeDef; +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED1; /*!< Reserved, 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */ +} COMPOPT_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; +/** + * @} + */ + + + +/** + * @brief High resolution Timer (HRTIM) + */ +/* HRTIM master registers definition */ +typedef struct +{ + __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */ + __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */ + __IO uint32_t MICR; /*!< HRTIM Master Timer interrupt clear register, Address offset: 0x08 */ + __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */ + __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */ + __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */ + __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */ + __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */ + uint32_t RESERVED0; /*!< Reserved, 0x20 */ + __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */ + __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */ + __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */ + uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */ +}HRTIM_Master_TypeDef; + +/* HRTIM Timer A to E registers definition */ +typedef struct +{ + __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */ + __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */ + __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */ + __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */ + __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */ + __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */ + __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */ + __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */ + __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */ + __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */ + __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */ + __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */ + __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */ + __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */ + __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */ + __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */ + __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */ + __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */ + __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */ + __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */ + __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */ + __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */ + __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */ + __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */ + __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */ + __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */ +}HRTIM_Timerx_TypeDef; + +/* HRTIM common register definition */ +typedef struct +{ + __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */ + __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */ + __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */ + __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ + __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ + __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ + __IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */ + __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ + __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ + __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ + __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */ + __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */ + __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */ + __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */ + __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */ + __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */ + __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */ + __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */ + __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */ + __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */ + __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */ + __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */ + __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */ + __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */ +}HRTIM_Common_TypeDef; + +/* HRTIM register definition */ +typedef struct { + HRTIM_Master_TypeDef sMasterRegs; + HRTIM_Timerx_TypeDef sTimerxRegs[5]; + uint32_t RESERVED0[32]; + HRTIM_Common_TypeDef sCommonRegs; +}HRTIM_TypeDef; +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /* User HW config1 044h*/ + __IO uint32_t GHWCFG2; /* User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + + +/** + * @brief Global Programmer View + */ + +typedef struct +{ + uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */ + __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */ + uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */ + uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */ + uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */ + __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */ + __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */ + __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */ + __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */ + __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */ + __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */ + __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */ + __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */ + __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */ + __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */ + __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */ + uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */ + __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */ + uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */ + __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */ + uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */ + __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */ + __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */ + uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */ + __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */ + uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */ + __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */ + uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */ + __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */ + uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */ + __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */ + uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */ + __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */ + uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */ + __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */ + uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */ + __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */ + __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */ + uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */ + __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */ + uint32_t RESERVED17[59334]; /*!< Reserved, Address offset: 0x810C-0x42020 */ + __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */ + __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */ + uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */ + __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */ + __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */ + __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */ + uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */ + __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */ + __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */ + __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */ + uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */ + __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */ + __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */ + uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */ + __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */ + __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */ + __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */ + uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */ + __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */ + __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */ + __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */ + uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */ + __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */ + __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */ + __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */ + uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */ + __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */ + __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */ + __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */ + uint32_t RESERVED25[1021]; /*!< Reserved, Address offset: 0x4710C-0x480FC */ + __IO uint32_t AXI_INI7_READ_QOS; /*!< AXI interconnect - INI 7 read QoS register, Address offset: 0x48100 */ + __IO uint32_t AXI_INI7_WRITE_QOS; /*!< AXI interconnect - INI 7 write QoS register, Address offset: 0x48104 */ + __IO uint32_t AXI_INI7_FN_MOD; /*!< AXI interconnect - INI 7 issuing functionality modification register, Address offset: 0x48108 */ + +} GPV_TypeDef; + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */ +#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */ +#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */ +#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */ +#define D1_AXISRAM_BASE (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */ + +#define D2_AXISRAM_BASE (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */ +#define D2_AHBSRAM_BASE (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */ + +#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */ +#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */ + +#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */ +#define QSPI_BASE (0x90000000UL) /*!< Base address of : QSPI memories accessible over AXI */ + +#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */ +#define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */ +#define FLASH_END (0x081FFFFFUL) /*!< FLASH end address */ + +/* Legacy define */ +#define FLASH_BASE FLASH_BANK1_BASE + +/*!< Device electronic signature memory map */ +#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */ + + +/*!< Peripheral memory map */ +#define D2_APB1PERIPH_BASE PERIPH_BASE +#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) + +#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) + +#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< Legacy Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< D1_AHB1PERIPH peripherals */ + +#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL) +#define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000UL) +#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL) +#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL) +#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL) +#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL) +#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL) + +/*!< D2_AHB1PERIPH peripherals */ + +#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL) +#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL) +#define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400UL) +#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) + +/*!< USB registers base address */ +#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL) +#define USB2_OTG_FS_PERIPH_BASE (0x40080000UL) +#define USB_OTG_GLOBAL_BASE (0x000UL) +#define USB_OTG_DEVICE_BASE (0x800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL) +#define USB_OTG_EP_REG_SIZE (0x20UL) +#define USB_OTG_HOST_BASE (0x400UL) +#define USB_OTG_HOST_PORT_BASE (0x440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL) +#define USB_OTG_PCGCCTL_BASE (0xE00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< D2_AHB2PERIPH peripherals */ + +#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL) +#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL) +#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL) +#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL) + +/*!< D3_AHB1PERIPH peripherals */ +#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL) +#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL) +#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL) +#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL) +#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL) +#define RCC_C1_BASE (RCC_BASE + 0x130UL) +#define RCC_C2_BASE (RCC_BASE + 0x190UL) +#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL) +#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL) +#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL) +#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL) +#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL) +#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL) +#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL) +#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL) + +/*!< D1_APB1PERIPH peripherals */ +#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL) +#define DSI_BASE (D1_APB1PERIPH_BASE) +#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL) + +/*!< D2_APB1PERIPH peripherals */ +#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL) + +#define WWDG2_BASE (D2_APB1PERIPH_BASE + 0x2C00UL) + +#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL) +#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL) +#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL) +#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL) +#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL) +#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL) +#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL) +#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL) +#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL) + +/*!< D2_APB2PERIPH peripherals */ + +#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL) +#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL) +#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) +#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL) +#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL) +#define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL) +#define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL) +#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL) +#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL) +#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL) +#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL) +#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL) +#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL) +#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL) +#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL) + + +/*!< D3_APB1PERIPH peripherals */ +#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL) +#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL) +#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL) +#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL) +#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL) +#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL) +#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL) +#define COMP1_BASE (COMP12_BASE + 0x0CUL) +#define COMP2_BASE (COMP12_BASE + 0x10UL) +#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL) +#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL) + +#define IWDG2_BASE (D3_APB1PERIPH_BASE + 0x4C00UL) + +#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL) +#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL) +#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL) + + + + +#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL) +#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL) +#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL) +#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL) +#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL) +#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL) +#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL) +#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL) + +#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE) +#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL) +#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL) +#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL) +#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL) +#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL) +#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL) +#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL) + +#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL) +#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL) +#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL) +#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL) +#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL) +#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL) +#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL) +#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL) + +#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL) +#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL) + +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) + +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) +#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL) +#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL) +#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL) +#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL) +#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL) +#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL) +#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL) +#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL) +#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL) +#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL) +#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL) +#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL) +#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL) +#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL) +#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL) +#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL) +#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL) +#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL) +#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL) + +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL) + +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL) +#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL) +#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL) +#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL) +#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL) + +#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL) +#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL) + + + +#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE) + +#define WWDG2 ((WWDG_TypeDef *) WWDG2_BASE) +#define IWDG2 ((IWDG_TypeDef *) IWDG2_BASE) + +#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) + + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) +#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE) +#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE) +#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE) +#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE) +#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE) +#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE) +#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#define SAI3 ((SAI_TypeDef *) SAI3_BASE) +#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE) +#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE) +#define SAI4 ((SAI_TypeDef *) SAI4_BASE) +#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE) +#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE) + +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE) +#define RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE) + +#define ART ((ART_TypeDef *) ART_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) + +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) + +#define BDMA ((BDMA_TypeDef *) BDMA_BASE) +#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE) +#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE) +#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE) +#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE) +#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE) +#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE) +#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE) +#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE) + +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE) + +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE) +#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE) +#define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE) +#define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE) + +#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE) +#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE) +#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE) + +#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE) +#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE) +#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE) +#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE) +#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE) +#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE) +#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE) +#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE) +#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE) + + +#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE) +#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE) +#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE) +#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE) +#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE) +#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE) +#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE) +#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE) + +#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE) +#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) + + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) +#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE) +#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE) +#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE) +#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) + + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) +#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE) +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#if defined(CORE_CM4) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110UL)) +#else /* CORE_CM7 */ +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL)) +#endif /* CORE_CM4 */ + +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) +#define DSI ((DSI_TypeDef *)DSI_BASE) + +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) + +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define MDMA ((MDMA_TypeDef *)MDMA_BASE) +#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE) +#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE) +#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE) +#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE) +#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE) +#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE) +#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE) +#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE) +#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE) +#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE) +#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE) +#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE) +#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE) +#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE) +#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE) +#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE) + + +#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE) +#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE) + +/* Legacy defines */ +#define USB_OTG_HS USB1_OTG_HS +#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE +#define USB_OTG_FS USB2_OTG_FS +#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE + +#define GPV ((GPV_TypeDef *) GPV_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_BOOST_Pos (8U) +#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */ +#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */ +#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */ +#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ +#define ADC_CR_LINCALRDYW1_Pos (22U) +#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */ +#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */ +#define ADC_CR_LINCALRDYW2_Pos (23U) +#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */ +#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */ +#define ADC_CR_LINCALRDYW3_Pos (24U) +#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */ +#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */ +#define ADC_CR_LINCALRDYW4_Pos (25U) +#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */ +#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */ +#define ADC_CR_LINCALRDYW5_Pos (26U) +#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */ +#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */ +#define ADC_CR_LINCALRDYW6_Pos (27U) +#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */ +#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR_DMNGT_Pos (0U) +#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR_RES_Pos (2U) +#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_RSHIFT1_Pos (11U) +#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ +#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ +#define ADC_CFGR2_RSHIFT2_Pos (12U) +#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */ +#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */ +#define ADC_CFGR2_RSHIFT3_Pos (13U) +#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */ +#define ADC_CFGR2_RSHIFT4_Pos (14U) +#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ +#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_SSATE_Pos (31U) +#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */ + + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ +#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_SSATE_Pos (31U) +#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */ + + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ +#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_SSATE_Pos (31U) +#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */ + + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ +#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_SSATE_Pos (31U) +#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */ + + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_LINCALFACT_Pos (0U) +#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */ +#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + + +#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* ART accelerator */ +/* */ +/******************************************************************************/ +/******************* Bit definition for ART_CTR register ********************/ +#define ART_CTR_EN_Pos (0U) +#define ART_CTR_EN_Msk (0x1UL << ART_CTR_EN_Pos) /*!< 0x00000001 */ +#define ART_CTR_EN ART_CTR_EN_Msk /*!< Cache enable*/ + +#define ART_CTR_PCACHEADDR_Pos (8U) +#define ART_CTR_PCACHEADDR_Msk (0xFFFUL << ART_CTR_PCACHEADDR_Pos) /*!< 0x000FFF00 */ +#define ART_CTR_PCACHEADDR ART_CTR_PCACHEADDR_Msk /*!< Cacheable page index */ + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1) /* 1 MB */ +#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ +#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */ +#define DUAL_BANK /* Dual-bank Flash */ + +/******************* Bits definition for FLASH_ACR register **********************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000UL) +#define FLASH_ACR_LATENCY_1WS (0x00000001UL) +#define FLASH_ACR_LATENCY_2WS (0x00000002UL) +#define FLASH_ACR_LATENCY_3WS (0x00000003UL) +#define FLASH_ACR_LATENCY_4WS (0x00000004UL) +#define FLASH_ACR_LATENCY_5WS (0x00000005UL) +#define FLASH_ACR_LATENCY_6WS (0x00000006UL) +#define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ +#define FLASH_ACR_LATENCY_8WS (0x00000008UL) +#define FLASH_ACR_LATENCY_9WS (0x00000009UL) +#define FLASH_ACR_LATENCY_10WS (0x0000000AUL) +#define FLASH_ACR_LATENCY_11WS (0x0000000BUL) +#define FLASH_ACR_LATENCY_12WS (0x0000000CUL) +#define FLASH_ACR_LATENCY_13WS (0x0000000DUL) +#define FLASH_ACR_LATENCY_14WS (0x0000000EUL) +#define FLASH_ACR_LATENCY_15WS (0x0000000FUL) +/******************* Bits definition for FLASH_CR register ***********************/ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Internal buffer control bit */ +#define FLASH_CR_SER_Pos (2U) +#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_PSIZE_Pos (4U) +#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000030 */ +#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk /*!< Program size */ +#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000010 */ +#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000020 */ +#define FLASH_CR_FW_Pos (6U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000040 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ +#define FLASH_CR_START_Pos (7U) +#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000080 */ +#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ +#define FLASH_CR_SNB_Pos (8U) +#define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos) /*!< 0x00000700 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ +#define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ +#define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ +#define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ +#define FLASH_CR_CRC_EN_Pos (15U) +#define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) /*!< 0x00008000 */ +#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk /*!< CRC control bit */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-program interrupt control bit */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ +#define FLASH_CR_INCERRIE_Pos (21U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00200000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ +#define FLASH_CR_OPERRIE_Pos (22U) +#define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos) /*!< 0x00400000 */ +#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk /*!< Write/erase error interrupt enable bit */ +#define FLASH_CR_RDPERRIE_Pos (23U) +#define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk /*!< Read protection error interrupt enable bit */ +#define FLASH_CR_RDSERRIE_Pos (24U) +#define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk /*!< Secure error interrupt enable bit */ +#define FLASH_CR_SNECCERRIE_Pos (25U) +#define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk /*!< ECC single correction error interrupt enable bit */ +#define FLASH_CR_DBECCERRIE_Pos (26U) +#define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk /*!< ECC double detection error interrupt enable bit */ +#define FLASH_CR_CRCENDIE_Pos (27U) +#define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) /*!< 0x08000000 */ +#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk /*!< CRC end of calculation interrupt enable bit */ +#define FLASH_CR_CRCRDERRIE_Pos (28U) +#define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */ +#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk /*!< CRC read error interrupt enable bit */ + +/******************* Bits definition for FLASH_SR register ***********************/ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ +#define FLASH_SR_QW_Pos (2U) +#define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) /*!< 0x00000004 */ +#define FLASH_SR_QW FLASH_SR_QW_Msk /*!< Wait queue flag */ +#define FLASH_SR_CRC_BUSY_Pos (3U) +#define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) /*!< 0x00000008 */ +#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk /*!< CRC busy flag */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ +#define FLASH_SR_INCERR_Pos (21U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00200000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ +#define FLASH_SR_OPERR_Pos (22U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00400000 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Write/erase error flag */ +#define FLASH_SR_RDPERR_Pos (23U) +#define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk /*!< Read protection error flag */ +#define FLASH_SR_RDSERR_Pos (24U) +#define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) /*!< 0x01000000 */ +#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk /*!< Secure error flag */ +#define FLASH_SR_SNECCERR_Pos (25U) +#define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) /*!< 0x02000000 */ +#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk /*!< Single correction error flag */ +#define FLASH_SR_DBECCERR_Pos (26U) +#define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) /*!< 0x04000000 */ +#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk /*!< ECC double detection error flag */ +#define FLASH_SR_CRCEND_Pos (27U) +#define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) /*!< 0x08000000 */ +#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk /*!< CRC end of calculation flag */ +#define FLASH_SR_CRCRDERR_Pos (28U) +#define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) /*!< 0x10000000 */ +#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk /*!< CRC read error flag */ + +/******************* Bits definition for FLASH_CCR register *******************/ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ +#define FLASH_CCR_CLR_INCERR_Pos (21U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ +#define FLASH_CCR_CLR_OPERR_Pos (22U) +#define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */ +#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk /*!< OPERR flag clear bit */ +#define FLASH_CCR_CLR_RDPERR_Pos (23U) +#define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk /*!< RDPERR flag clear bit */ +#define FLASH_CCR_CLR_RDSERR_Pos (24U) +#define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */ +#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk /*!< RDSERR flag clear bit */ +#define FLASH_CCR_CLR_SNECCERR_Pos (25U) +#define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */ +#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk /*!< SNECCERR flag clear bit */ +#define FLASH_CCR_CLR_DBECCERR_Pos (26U) +#define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */ +#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk /*!< DBECCERR flag clear bit */ +#define FLASH_CCR_CLR_CRCEND_Pos (27U) +#define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */ +#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk /*!< CRCEND flag clear bit */ +#define FLASH_CCR_CLR_CRCRDERR_Pos (28U) +#define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */ +#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk /*!< CRCRDERR flag clear bit */ + +/******************* Bits definition for FLASH_OPTCR register *******************/ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ +#define FLASH_OPTCR_OPTSTART_Pos (1U) +#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ +#define FLASH_OPTCR_MER_Pos (4U) +#define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) /*!< 0x00000010 */ +#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk /*!< Mass erase request */ +#define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U) +#define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */ +#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ + +/******************* Bits definition for FLASH_OPTSR register ***************/ +#define FLASH_OPTSR_OPT_BUSY_Pos (0U) +#define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk /*!< Option byte change ongoing flag */ +#define FLASH_OPTSR_BOR_LEV_Pos (2U) +#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */ +#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option status bit */ +#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_IWDG1_SW_Pos (4U) +#define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk /*!< IWDG1 control mode option status bit */ +#define FLASH_OPTSR_IWDG2_SW_Pos (5U) +#define FLASH_OPTSR_IWDG2_SW_Msk (0x1UL << FLASH_OPTSR_IWDG2_SW_Pos) /*!< 0x00000020 */ +#define FLASH_OPTSR_IWDG2_SW FLASH_OPTSR_IWDG2_SW_Msk /*!< IWDG2 control mode option status bit */ +#define FLASH_OPTSR_NRST_STOP_D1_Pos (6U) +#define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk /*!< D1 domain DStop entry reset option status bit */ +#define FLASH_OPTSR_NRST_STBY_D1_Pos (7U) +#define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk /*!< D1 domain DStandby entry reset option status bit */ +#define FLASH_OPTSR_RDP_Pos (8U) +#define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk /*!< Readout protection level option status byte */ +#define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U) +#define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk /*!< IWDG Stop mode freeze option status bit */ +#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U) +#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk /*!< IWDG Standby mode freeze option status bit */ +#define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U) +#define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */ +#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk /*!< ST RAM size option status */ +#define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */ +#define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_SECURITY_Pos (21U) +#define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk /*!< Security enable option status bit */ +#define FLASH_OPTSR_BCM4_Pos (22U) +#define FLASH_OPTSR_BCM4_Msk (0x1UL << FLASH_OPTSR_BCM4_Pos) /*!< 0x00400000 */ +#define FLASH_OPTSR_BCM4 FLASH_OPTSR_BCM4_Msk /*!< Arm Cortex-M4 boot option status bit */ +#define FLASH_OPTSR_BCM7_Pos (23U) +#define FLASH_OPTSR_BCM7_Msk (0x1UL << FLASH_OPTSR_BCM7_Pos) /*!< 0x00800000 */ +#define FLASH_OPTSR_BCM7 FLASH_OPTSR_BCM7_Msk /*!< Arm Cortex-M7 boot option status bit */ +#define FLASH_OPTSR_NRST_STOP_D2_Pos (24U) +#define FLASH_OPTSR_NRST_STOP_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos) /*!< 0x01000000 */ +#define FLASH_OPTSR_NRST_STOP_D2 FLASH_OPTSR_NRST_STOP_D2_Msk /*!< D2 domain DStop entry reset option status bit */ +#define FLASH_OPTSR_NRST_STBY_D2_Pos (25U) +#define FLASH_OPTSR_NRST_STBY_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos) /*!< 0x02000000 */ +#define FLASH_OPTSR_NRST_STBY_D2 FLASH_OPTSR_NRST_STBY_D2_Msk /*!< D2 domain DStandby entry reset option status bit */ +#define FLASH_OPTSR_IO_HSLV_Pos (29U) +#define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk /*!< I/O high-speed at low-voltage status bit */ +#define FLASH_OPTSR_OPTCHANGEERR_Pos (30U) +#define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ +#define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U) +#define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk /*!< Bank swapping option status bit */ + +/******************* Bits definition for FLASH_OPTCCR register *******************/ +#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U) +#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */ +#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk /*!< OPTCHANGEERR reset bit */ + +/******************* Bits definition for FLASH_PRAR register *********************/ +#define FLASH_PRAR_PROT_AREA_START_Pos (0U) +#define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */ +#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk /*!< PCROP area start status bits */ +#define FLASH_PRAR_PROT_AREA_END_Pos (16U) +#define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */ +#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk /*!< PCROP area end status bits */ +#define FLASH_PRAR_DMEP_Pos (31U) +#define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) /*!< 0x80000000 */ +#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk /*!< PCROP protected erase enable option status bit */ + +/******************* Bits definition for FLASH_SCAR register *********************/ +#define FLASH_SCAR_SEC_AREA_START_Pos (0U) +#define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */ +#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk /*!< Secure-only area start status bits */ +#define FLASH_SCAR_SEC_AREA_END_Pos (16U) +#define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */ +#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk /*!< Secure-only area end status bits */ +#define FLASH_SCAR_DMES_Pos (31U) +#define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) /*!< 0x80000000 */ +#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk /*!< Secure access protected erase enable option status bit */ + +/******************* Bits definition for FLASH_WPSN register *********************/ +#define FLASH_WPSN_WRPSN_Pos (0U) +#define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos) /*!< 0x000000FF */ +#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk /*!< Sector write protection option status byte */ + +/******************* Bits definition for FLASH_BOOT7_CUR register ****************/ +#define FLASH_BOOT7_BCM7_ADD0_Pos (0U) +#define FLASH_BOOT7_BCM7_ADD0_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD0_Pos) /*!< 0x0000FFFF */ +#define FLASH_BOOT7_BCM7_ADD0 FLASH_BOOT7_BCM7_ADD0_Msk /*!< Arm Cortex-M7 boot address 0 */ +#define FLASH_BOOT7_BCM7_ADD1_Pos (16U) +#define FLASH_BOOT7_BCM7_ADD1_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD1_Pos) /*!< 0xFFFF0000 */ +#define FLASH_BOOT7_BCM7_ADD1 FLASH_BOOT7_BCM7_ADD1_Msk /*!< Arm Cortex-M7 boot address 1 */ + +/******************* Bits definition for FLASH_BOOT4 register ********************/ +#define FLASH_BOOT4_BCM4_ADD0_Pos (0U) +#define FLASH_BOOT4_BCM4_ADD0_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD0_Pos) /*!< 0x0000FFFF */ +#define FLASH_BOOT4_BCM4_ADD0 FLASH_BOOT4_BCM4_ADD0_Msk /*!< Arm Cortex-M4 boot address 0 */ +#define FLASH_BOOT4_BCM4_ADD1_Pos (16U) +#define FLASH_BOOT4_BCM4_ADD1_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD1_Pos) /*!< 0xFFFF0000 */ +#define FLASH_BOOT4_BCM4_ADD1 FLASH_BOOT4_BCM4_ADD1_Msk /*!< Arm Cortex-M4 boot address 1 */ + +/******************* Bits definition for FLASH_CRCCR register ********************/ +#define FLASH_CRCCR_CRC_SECT_Pos (0U) +#define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */ +#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk /*!< CRC sector number */ +#define FLASH_CRCCR_CRC_BY_SECT_Pos (8U) +#define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */ +#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk /*!< CRC sector mode select bit */ +#define FLASH_CRCCR_ADD_SECT_Pos (9U) +#define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */ +#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk /*!< CRC sector select bit */ +#define FLASH_CRCCR_CLEAN_SECT_Pos (10U) +#define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */ +#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk /*!< CRC sector list clear bit */ +#define FLASH_CRCCR_START_CRC_Pos (16U) +#define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */ +#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk /*!< CRC start bit */ +#define FLASH_CRCCR_CLEAN_CRC_Pos (17U) +#define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */ +#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk /*!< CRC clear bit */ +#define FLASH_CRCCR_CRC_BURST_Pos (20U) +#define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */ +#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk /*!< CRC burst size */ +#define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */ +#define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */ +#define FLASH_CRCCR_ALL_BANK_Pos (22U) +#define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */ +#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk /*!< CRC select bit */ + +/******************* Bits definition for FLASH_CRCSADD register ****************/ +#define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U) +#define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk /*!< CRC start address */ + +/******************* Bits definition for FLASH_CRCEADD register ****************/ +#define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U) +#define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk /*!< CRC end address */ + +/******************* Bits definition for FLASH_CRCDATA register ***************/ +#define FLASH_CRCDATA_CRC_DATA_Pos (0U) +#define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk /*!< CRC result */ + +/******************* Bits definition for FLASH_ECC_FA register *******************/ +#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U) +#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */ +#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk /*!< ECC error address */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!
© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -223,22 +222,22 @@ typedef enum * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals */ #ifdef CORE_CM4 -#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ -#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1U /*!< CM4 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM4 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ #else /* CORE_CM7 */ #ifdef CORE_CM7 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ #else /* UNKNOWN_CORE */ #error Please #define CORE_CM4 or CORE_CM7 @@ -1014,8 +1013,8 @@ __IO uint32_t C2PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -1881,7 +1880,7 @@ typedef struct __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ - __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */ + __IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */ __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ @@ -2890,6 +2889,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2939,6 +2947,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -13914,11 +13925,15 @@ typedef struct /* * @brief FLASH Global Defines */ +#if defined(CORE_CM4) +#define FLASH_SIZE 0x200000UL /* 2 MB */ +#else #define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U -#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */ #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */ +#endif /* CORE_CM4 */ +#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */ #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -13927,7 +13942,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -13937,6 +13952,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -13945,12 +13968,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -23177,8 +23194,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -216,12 +215,12 @@ typedef enum * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ /** @@ -889,8 +888,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -1795,7 +1794,7 @@ typedef struct __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ - __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */ + __IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */ __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ @@ -2789,6 +2788,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2838,6 +2846,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -10856,7 +10867,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -10866,6 +10877,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -10874,12 +10893,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -19627,8 +19640,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -216,12 +215,12 @@ typedef enum * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ /** @@ -889,8 +888,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -1795,7 +1794,7 @@ typedef struct __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ - __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */ + __IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */ __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ @@ -2789,6 +2788,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2838,6 +2846,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -10856,7 +10867,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -10866,6 +10877,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -10874,12 +10893,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -19633,8 +19646,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -223,22 +222,22 @@ typedef enum * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals */ #ifdef CORE_CM4 -#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ -#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1U /*!< CM4 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM4 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ #else /* CORE_CM7 */ #ifdef CORE_CM7 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ #else /* UNKNOWN_CORE */ #error Please #define CORE_CM4 or CORE_CM7 @@ -934,8 +933,8 @@ __IO uint32_t C2PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -1870,7 +1869,7 @@ typedef struct __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ - __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */ + __IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */ __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ @@ -2883,6 +2882,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2932,6 +2940,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -10950,11 +10961,15 @@ typedef struct /* * @brief FLASH Global Defines */ +#if defined(CORE_CM4) +#define FLASH_SIZE 0x200000UL /* 2 MB */ +#else #define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U -#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */ #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */ +#endif /* CORE_CM4 */ +#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */ #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -10963,7 +10978,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -10973,6 +10988,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -10981,12 +11004,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -20291,8 +20308,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -224,22 +223,22 @@ typedef enum * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals */ #ifdef CORE_CM4 -#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ -#define __MPU_PRESENT 1 /*!< CM4 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1U /*!< CM4 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM4 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ #else /* CORE_CM7 */ #ifdef CORE_CM7 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ #else /* UNKNOWN_CORE */ #error Please #define CORE_CM4 or CORE_CM7 @@ -1015,8 +1014,8 @@ __IO uint32_t C2PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -1951,7 +1950,7 @@ typedef struct __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ - __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */ + __IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */ __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ @@ -2966,6 +2965,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -3015,6 +3023,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -14107,11 +14118,15 @@ typedef struct /* * @brief FLASH Global Defines */ +#if defined(CORE_CM4) +#define FLASH_SIZE 0x200000UL /* 2 MB */ +#else #define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U -#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */ #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \ ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \ (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */ +#endif /* CORE_CM4 */ +#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */ #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -14120,7 +14135,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -14130,6 +14145,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -14138,12 +14161,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -23464,8 +23481,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -210,12 +209,12 @@ typedef enum * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ /** @@ -732,8 +731,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -2596,6 +2595,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2645,6 +2653,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -8472,7 +8483,7 @@ typedef struct /******************* Bit definition for EXTI_IMR3 register *******************/ #define EXTI_IMR3_IM_Pos (0U) -#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */ +#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */ #define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */ #define EXTI_IMR3_IM64_Pos (0U) #define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */ @@ -8619,7 +8630,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -8629,6 +8640,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -8637,12 +8656,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -17597,8 +17610,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -211,12 +210,12 @@ typedef enum * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ /** @@ -733,8 +732,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -2597,6 +2596,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2646,6 +2654,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -8473,7 +8484,7 @@ typedef struct /******************* Bit definition for EXTI_IMR3 register *******************/ #define EXTI_IMR3_IM_Pos (0U) -#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */ +#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */ #define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */ #define EXTI_IMR3_IM64_Pos (0U) #define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */ @@ -8620,7 +8631,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -8630,6 +8641,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -8638,12 +8657,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -17609,8 +17622,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -213,12 +212,12 @@ typedef enum * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ /** @@ -735,8 +734,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -2731,6 +2730,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2780,6 +2788,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -8726,7 +8737,7 @@ typedef struct /******************* Bit definition for EXTI_IMR3 register *******************/ #define EXTI_IMR3_IM_Pos (0U) -#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */ +#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */ #define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */ #define EXTI_IMR3_IM64_Pos (0U) #define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */ @@ -8872,7 +8883,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -8882,6 +8893,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -8890,12 +8909,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -18077,8 +18090,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -214,12 +213,12 @@ typedef enum * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ /** @@ -736,8 +735,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -2732,6 +2731,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2781,6 +2789,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -8727,7 +8738,7 @@ typedef struct /******************* Bit definition for EXTI_IMR3 register *******************/ #define EXTI_IMR3_IM_Pos (0U) -#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */ +#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */ #define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */ #define EXTI_IMR3_IM64_Pos (0U) #define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */ @@ -8873,7 +8884,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -8883,6 +8894,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -8891,12 +8910,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -18089,8 +18102,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -213,12 +212,12 @@ typedef enum * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ /** @@ -735,8 +734,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -2731,6 +2730,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2780,6 +2788,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -8726,7 +8737,7 @@ typedef struct /******************* Bit definition for EXTI_IMR3 register *******************/ #define EXTI_IMR3_IM_Pos (0U) -#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */ +#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */ #define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */ #define EXTI_IMR3_IM64_Pos (0U) #define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */ @@ -8873,7 +8884,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -8883,6 +8894,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -8891,12 +8910,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -18084,8 +18097,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -50,7 +49,7 @@ typedef enum { /****** Cortex-M Processor Exceptions Numbers *****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ @@ -214,12 +213,12 @@ typedef enum * @brief Configuration of the Cortex-M7 Processor and Core Peripherals */ #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */ -#define __MPU_PRESENT 1 /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -#define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1 /*!< CM7 data cache present */ +#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ +#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ +#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ /** @@ -736,8 +735,8 @@ __IO uint32_t PR3; /*!< EXTI Pending register, * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: - * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) - * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only */ @@ -2732,6 +2731,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2781,6 +2789,9 @@ typedef struct #define ADC_ISR_JQOVF_Pos (10U) #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ /******************** Bit definition for ADC_IER register ********************/ #define ADC_IER_ADRDYIE_Pos (0U) @@ -8727,7 +8738,7 @@ typedef struct /******************* Bit definition for EXTI_IMR3 register *******************/ #define EXTI_IMR3_IM_Pos (0U) -#define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */ +#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x01A527FF */ #define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */ #define EXTI_IMR3_IM64_Pos (0U) #define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */ @@ -8874,7 +8885,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) @@ -8884,6 +8895,14 @@ typedef struct #define FLASH_ACR_LATENCY_5WS (0x00000005UL) #define FLASH_ACR_LATENCY_6WS (0x00000006UL) #define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ #define FLASH_ACR_LATENCY_8WS (0x00000008UL) #define FLASH_ACR_LATENCY_9WS (0x00000009UL) #define FLASH_ACR_LATENCY_10WS (0x0000000AUL) @@ -8892,12 +8911,6 @@ typedef struct #define FLASH_ACR_LATENCY_13WS (0x0000000DUL) #define FLASH_ACR_LATENCY_14WS (0x0000000EUL) #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) -#define FLASH_ACR_WRHIGHFREQ_Pos (4U) -#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ -#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ - /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ @@ -18096,8 +18109,8 @@ typedef struct #define TIM_CR2_OIS5_Pos (16U) #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -59,7 +58,7 @@ */ #if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \ - !defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx) && \ + !defined (STM32H745xx) && !defined (STM32H745xG) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H747xG)&& !defined (STM32H757xx) && \ !defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ) && \ !defined (STM32H735xx) && !defined (STM32H733xx) && !defined (STM32H730xx) && !defined (STM32H730xxQ) && !defined (STM32H725xx) && !defined (STM32H723xx) /* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */ @@ -67,8 +66,10 @@ /* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */ /* #define STM32H750xx */ /*!< STM32H750V, STM32H750I, STM32H750X Devices */ /* #define STM32H747xx */ /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */ + /* #define STM32H747xG */ /*!< STM32H747AG, STM32H747IG, STM32H747BG, STM32H747XG */ /* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */ /* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */ + /* #define STM32H745xG */ /*!< STM32H745ZG, STM32H745IG, STM32H745BG, STM32H745XG Devices */ /* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */ /* #define STM32H7B0xx */ /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */ /* #define STM32H7A3xx */ /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */ @@ -101,11 +102,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V1.10.0 + * @brief CMSIS Device version number V1.10.2 */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */ -#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\ @@ -130,10 +131,14 @@ #include "stm32h742xx.h" #elif defined(STM32H745xx) #include "stm32h745xx.h" +#elif defined(STM32H745xG) + #include "stm32h745xg.h" #elif defined(STM32H755xx) #include "stm32h755xx.h" #elif defined(STM32H747xx) #include "stm32h747xx.h" +#elif defined(STM32H747xG) + #include "stm32h747xg.h" #elif defined(STM32H757xx) #include "stm32h757xx.h" #elif defined(STM32H7B0xx) @@ -214,6 +219,60 @@ typedef enum #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) +/* Use of CMSIS compiler intrinsics for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t val; \ + do { \ + val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint16_t val; \ + do { \ + val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) /** * @} @@ -240,4 +299,3 @@ typedef enum -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h b/platform/vendor_bsp/st/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h index 34f8495ba..e228ef740 100644 --- a/platform/vendor_bsp/st/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h +++ b/platform/vendor_bsp/st/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -102,4 +101,3 @@ extern void SystemCoreClockUpdate(void); /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 93a925df8..844bb943a 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -38,6 +37,14 @@ extern "C" { #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32U5) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF +#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF +#endif /* STM32U5 */ /** * @} */ @@ -97,6 +104,12 @@ extern "C" { #if defined(STM32H7) #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT #endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ /** * @} */ @@ -206,6 +219,23 @@ extern "C" { * @{ */ #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32H5) || defined(STM32C0) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +#endif /** * @} */ @@ -235,11 +265,23 @@ extern "C" { #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32H7) +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID @@ -383,7 +425,9 @@ extern "C" { #endif /* STM32H7 */ - +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ /** * @} */ @@ -463,7 +507,7 @@ extern "C" { #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 -#if defined(STM32G0) +#if defined(STM32G0) || defined(STM32C0) #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH #else @@ -471,15 +515,24 @@ extern "C" { #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE #endif #if defined(STM32H7) -#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 -#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 -#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 -#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 -#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 -#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 -#define FLASH_FLAG_WDW FLASH_FLAG_WBNE -#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U5 */ /** * @} @@ -522,6 +575,107 @@ extern "C" { #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ + +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + /** * @} */ @@ -596,12 +750,12 @@ extern "C" { #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW @@ -617,6 +771,20 @@ extern "C" { #endif /* STM32F0 || STM32F3 || STM32F1 */ #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#endif /* STM32U5 */ /** * @} */ @@ -854,6 +1022,20 @@ extern "C" { #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ /** * @} */ @@ -1192,6 +1374,10 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif +#if defined(STM32U5) || defined(STM32MP2) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif /** * @} */ @@ -1380,6 +1566,20 @@ extern "C" { */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ @@ -1398,6 +1598,29 @@ extern "C" { * @} */ +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ */ @@ -1585,6 +1808,79 @@ extern "C" { #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + /** * @} */ @@ -3218,7 +3514,10 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) +#if defined(STM32GK) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_DISABLE +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_DISABLE +#elif defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) || defined(STM32V7) || defined(STM32N6) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3330,6 +3629,33 @@ extern "C" { #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#endif /** * @} @@ -3347,7 +3673,7 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32GK) || defined (STM32WB_GEN2) || defined (STM32WBA) || defined (STM32V7) || defined (STM32H5) || defined (STM32C0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3400,17 +3726,30 @@ extern "C" { #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#endif /* STM32H5 */ + /** * @} */ -/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose * @{ */ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + #if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY @@ -3753,5 +4092,4 @@ extern "C" { #endif /* STM32_HAL_LEGACY */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/Legacy/stm32h7xx_hal_eth_ex_legacy.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/Legacy/stm32h7xx_hal_eth_ex_legacy.h new file mode 100644 index 000000000..966f29355 --- /dev/null +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/Legacy/stm32h7xx_hal_eth_ex_legacy.h @@ -0,0 +1,354 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_eth_ex_legacy.h + * @author MCD Application Team + * @brief Header file of ETH HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_ETH_EX_LEGACY_H +#define STM32H7xx_HAL_ETH_EX_LEGACY_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(ETH) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup ETHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ETHEx_Exported_Types ETHEx Exported Types + * @{ + */ + +/** + * @brief ETH RX VLAN structure definition + */ +typedef struct{ + FunctionalState InnerVLANTagInStatus; /*!< Enables or disables Inner VLAN Tag in Rx Status */ + + uint32_t StripInnerVLANTag; /*!< Sets the Inner VLAN Tag Stripping on Receive + This parameter can be a value of @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */ + + FunctionalState InnerVLANTag; /*!< Enables or disables Inner VLAN Tag */ + + FunctionalState DoubleVLANProcessing; /*!< Enable or Disable double VLAN processing */ + + FunctionalState VLANTagHashTableMatch; /*!< Enable or Disable VLAN Tag Hash Table Match */ + + FunctionalState VLANTagInStatus; /*!< Enable or Disable VLAN Tag in Rx status */ + + uint32_t StripVLANTag; /*!< Set the VLAN Tag Stripping on Receive + This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */ + + uint32_t VLANTypeCheck; /*!< Enable or Disable VLAN Type Check + This parameter can be a value of @ref ETHEx_VLAN_Type_Check */ + + FunctionalState VLANTagInverceMatch; /*!< Enable or disable VLAN Tag Inverse Match */ +}ETH_RxVLANConfigTypeDef; +/** + * + */ + +/** + * @brief ETH TX VLAN structure definition + */ +typedef struct{ + FunctionalState SourceTxDesc; /*!< Enable or Disable VLAN tag source from DMA tx descriptors */ + + FunctionalState SVLANType; /*!< Enable or Disable insertion of SVLAN type */ + + uint32_t VLANTagControl; /*!< Sets the VLAN tag control in tx packets + This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */ +}ETH_TxVLANConfigTypeDef; +/** + * + */ + +/** + * @brief ETH L3 filter structure definition + */ +typedef struct{ + uint32_t Protocol; /*!< Sets the L3 filter protocol to IPv4 or IPv6 + This parameter can be a value of @ref ETHEx_L3_Protocol */ + + uint32_t SrcAddrFilterMatch; /*!< Sets the L3 filter source address match + This parameter can be a value of @ref ETHEx_L3_Source_Match */ + + uint32_t DestAddrFilterMatch; /*!< Sets the L3 filter destination address match + This parameter can be a value of @ref ETHEx_L3_Destination_Match */ + + uint32_t SrcAddrHigherBitsMatch; /*!< Sets the L3 filter source address higher bits match + This parameter can be a value from 0 to 31 */ + + uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match + This parameter can be a value from 0 to 31 */ + + uint32_t Ip4SrcAddr; /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used + This parameter can be a value from 0x0 to 0xFFFFFFFF */ + + uint32_t Ip4DestAddr; /*!< Sets the L3 filter IPv4 destination address if IPv4 protocol is used + This parameter can be a value from 0 to 0xFFFFFFFF */ + + uint32_t Ip6Addr[4]; /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used + This parameter must be a table of 4 words (4* 32 bits) */ +}ETH_L3FilterConfigTypeDef; +/** + * + */ + +/** + * @brief ETH L4 filter structure definition + */ +typedef struct{ + uint32_t Protocol; /*!< Sets the L4 filter protocol to TCP or UDP + This parameter can be a value of @ref ETHEx_L4_Protocol */ + + uint32_t SrcPortFilterMatch; /*!< Sets the L4 filter source port match + This parameter can be a value of @ref ETHEx_L4_Source_Match */ + + uint32_t DestPortFilterMatch; /*!< Sets the L4 filter destination port match + This parameter can be a value of @ref ETHEx_L4_Destination_Match */ + + uint32_t SourcePort; /*!< Sets the L4 filter source port + This parameter must be a value from 0x0 to 0xFFFF */ + + uint32_t DestinationPort; /*!< Sets the L4 filter destination port + This parameter must be a value from 0x0 to 0xFFFF */ +}ETH_L4FilterConfigTypeDef; +/** + * + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants + * @{ + */ + +/** @defgroup ETHEx_LPI_Event ETHEx LPI Event + * @{ + */ +#define ETH_TX_LPI_ENTRY ETH_MACLCSR_TLPIEN +#define ETH_TX_LPI_EXIT ETH_MACLCSR_TLPIEX +#define ETH_RX_LPI_ENTRY ETH_MACLCSR_RLPIEN +#define ETH_RX_LPI_EXIT ETH_MACLCSR_RLPIEX +/** + * @} + */ + +/** @defgroup ETHEx_L3_Filter ETHEx L3 Filter + * @{ + */ +#define ETH_L3_FILTER_0 ((uint32_t)0x00000000) +#define ETH_L3_FILTER_1 ((uint32_t)0x0000000C) +/** + * @} + */ + +/** @defgroup ETHEx_L4_Filter ETHEx L4 Filter + * @{ + */ +#define ETH_L4_FILTER_0 ((uint32_t)0x00000000) +#define ETH_L4_FILTER_1 ((uint32_t)0x0000000C) +/** + * @} + */ + +/** @defgroup ETHEx_L3_Protocol ETHEx L3 Protocol + * @{ + */ +#define ETH_L3_IPV6_MATCH ETH_MACL3L4CR_L3PEN +#define ETH_L3_IPV4_MATCH ((uint32_t)0x00000000) +/** + * @} + */ + +/** @defgroup ETHEx_L3_Source_Match ETHEx L3 Source Match + * @{ + */ +#define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3SAM +#define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM) +#define ETH_L3_SRC_ADDR_MATCH_DISABLE ((uint32_t)0x00000000) +/** + * @} + */ + +/** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match + * @{ + */ +#define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3DAM +#define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM) +#define ETH_L3_DEST_ADDR_MATCH_DISABLE ((uint32_t)0x00000000) +/** + * @} + */ + +/** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol + * @{ + */ +#define ETH_L4_UDP_MATCH ETH_MACL3L4CR_L4PEN +#define ETH_L4_TCP_MATCH ((uint32_t)0x00000000) +/** + * @} + */ + +/** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match + * @{ + */ +#define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4SPM +#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM) +#define ETH_L4_SRC_PORT_MATCH_DISABLE ((uint32_t)0x00000000) +/** + * @} + */ + +/** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match + * @{ + */ +#define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4DPM +#define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM) +#define ETH_L4_DEST_PORT_MATCH_DISABLE ((uint32_t)0x00000000) +/** + * @} + */ + +/** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping + * @{ + */ +#define ETH_INNERVLANTAGRXSTRIPPING_NONE ETH_MACVTR_EIVLS_DONOTSTRIP +#define ETH_INNERVLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EIVLS_STRIPIFPASS +#define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS +#define ETH_INNERVLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EIVLS_ALWAYSSTRIP +/** + * @} + */ + +/** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping + * @{ + */ +#define ETH_VLANTAGRXSTRIPPING_NONE ETH_MACVTR_EVLS_DONOTSTRIP +#define ETH_VLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EVLS_STRIPIFPASS +#define ETH_VLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS +#define ETH_VLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EVLS_ALWAYSSTRIP +/** + * @} + */ + +/** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check + * @{ + */ +#define ETH_VLANTYPECHECK_DISABLE ETH_MACVTR_DOVLTC +#define ETH_VLANTYPECHECK_SVLAN (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL) +#define ETH_VLANTYPECHECK_CVLAN ((uint32_t)0x00000000) +/** + * @} + */ + +/** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control + * @{ + */ +#define ETH_VLANTAGCONTROL_NONE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG) +#define ETH_VLANTAGCONTROL_DELETE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE) +#define ETH_VLANTAGCONTROL_INSERT (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT) +#define ETH_VLANTAGCONTROL_REPLACE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE) +/** + * @} + */ + +/** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag + * @{ + */ +#define ETH_INNER_TX_VLANTAG ((uint32_t)0x00000001U) +#define ETH_OUTER_TX_VLANTAG ((uint32_t)0x00000000U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ETHEx_Exported_Functions + * @{ + */ + +/** @addtogroup ETHEx_Exported_Functions_Group1 + * @{ + */ +/* MAC ARP Offloading APIs ***************************************************/ +void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth); +void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth); +void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress); + +/* MAC L3 L4 Filtering APIs ***************************************************/ +void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth); +void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig); +HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig); +HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig); +HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig); + +/* MAC VLAN Processing APIs ************************************************/ +void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth); +void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig); +HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig); +void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable); +HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig); +HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig); +void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier); + +/* Energy Efficient Ethernet APIs *********************************************/ +void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop); +void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth); +uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ETH */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_ETH_EX_LEGACY_H */ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/Legacy/stm32h7xx_hal_eth_legacy.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/Legacy/stm32h7xx_hal_eth_legacy.h new file mode 100644 index 000000000..878036dd8 --- /dev/null +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/Legacy/stm32h7xx_hal_eth_legacy.h @@ -0,0 +1,1682 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_eth_legacy.h + * @author MCD Application Team + * @brief Header file of ETH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_ETH_LEGACY_H +#define STM32H7xx_HAL_ETH_LEGACY_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +#if defined(ETH) + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup ETH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +#ifndef ETH_TX_DESC_CNT + #define ETH_TX_DESC_CNT 4U +#endif + +#ifndef ETH_RX_DESC_CNT + #define ETH_RX_DESC_CNT 4U +#endif + +/*********************** Descriptors struct def section ************************/ +/** @defgroup ETH_Exported_Types ETH Exported Types + * @{ + */ + +/** + * @brief ETH DMA Descriptor structure definition + */ +typedef struct +{ + __IO uint32_t DESC0; + __IO uint32_t DESC1; + __IO uint32_t DESC2; + __IO uint32_t DESC3; + uint32_t BackupAddr0; /* used to store rx buffer 1 address */ + uint32_t BackupAddr1; /* used to store rx buffer 2 address */ +}ETH_DMADescTypeDef; +/** + * + */ + +/** + * @brief ETH Buffers List structure definition + */ +typedef struct __ETH_BufferTypeDef +{ + uint8_t *buffer; /*gState = HAL_ETH_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \ + } while(0) +#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @brief Enables the specified ETHERNET DMA interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be + * enabled @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified ETHERNET DMA interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be + * disabled. @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__)) + +/** + * @brief Gets the ETHERNET DMA IT source enabled or disabled. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts + * @retval The ETH DMA IT Source enabled or disabled + */ +#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Gets the ETHERNET DMA IT pending bit. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts + * @retval The state of ETH DMA IT (SET or RESET) + */ +#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Clears the ETHERNET DMA IT pending bit. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__)) + +/** + * @brief Checks whether the specified ETHERNET DMA flag is set or not. +* @param __HANDLE__: ETH Handle + * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags + * @retval The state of ETH DMA FLAG (SET or RESET). + */ +#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__)) + +/** + * @brief Clears the specified ETHERNET DMA flag. +* @param __HANDLE__: ETH Handle + * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags + * @retval The state of ETH DMA FLAG (SET or RESET). + */ +#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__)) + +/** + * @brief Enables the specified ETHERNET MAC interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be + * enabled @ref ETH_MAC_Interrupts + * @retval None + */ +#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified ETHERNET MAC interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be + * enabled @ref ETH_MAC_Interrupts + * @retval None + */ +#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * @param __HANDLE__: ETH Handle + * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts + * @retval The state of ETH MAC IT (SET or RESET). + */ +#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__)) + +/*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */ +#define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00400000U) /* !< 86 - 64 = 22 */ + +/** + * @brief Enable the ETH WAKEUP Exti Line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR3 |= (__EXTI_LINE__)) + +/** + * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval EXTI ETH WAKEUP Line Status. + */ +#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 & (__EXTI_LINE__)) + +/** + * @brief Clear the ETH WAKEUP Exti flag. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__)) + +#if defined(DUAL_CORE) +/** + * @brief Enable the ETH WAKEUP Exti Line by Core2. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__) (EXTI_D2->IMR3 |= (__EXTI_LINE__)) + +/** + * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval EXTI ETH WAKEUP Line Status. + */ +#define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 & (__EXTI_LINE__)) + +/** + * @brief Clear the ETH WAKEUP Exti flag. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__)) +#endif + +/** + * @brief enable rising edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \ + (EXTI->RTSR3 |= (__EXTI_LINE__)) + +/** + * @brief enable falling edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\ + (EXTI->FTSR3 |= (__EXTI_LINE__)) + +/** + * @brief enable falling edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\ + (EXTI->FTSR3 |= (__EXTI_LINE__)) + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__)) + +/** + * @} + */ + +/* Include ETH HAL Extension module */ +#include "stm32h7xx_hal_eth_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup ETH_Exported_Functions + * @{ + */ + +/** @addtogroup ETH_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de initialization functions **********************************/ +HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1,uint8_t *pBuffer2); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth); + +uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer); +HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length); +HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo); +HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout); +HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig); + +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue); +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue); + +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); +void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth); +void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth); +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions **********************************************/ +/* MAC & DMA Configuration APIs **********************************************/ +HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); +HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); +HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); +HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); +void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth); + +/* MAC VLAN Processing APIs ************************************************/ +void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier); + +/* MAC L2 Packet Filtering APIs **********************************************/ +HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); +HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); +HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable); +HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr); + +/* MAC Power Down APIs *****************************************************/ +void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig); +void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count); + +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ETH */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_ETH_LEGACY_H */ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32_assert_template.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32_assert_template.h index 4711b65d8..3ae73f0fb 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32_assert_template.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32_assert_template.h @@ -8,13 +8,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -54,4 +53,4 @@ #endif /* __STM32_ASSERT_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h index 95a44bf59..33af192cf 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. + * Copyright (c) 2017 STMicroelectronics. * All rights reserved.

* - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1079,12 +1078,12 @@ void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG #if defined(SYSCFG_CCCR_NCC_MMC) void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode); #endif /* SYSCFG_CCCR_NCC_MMC */ -void HAL_EnableDBGSleepMode(void); -void HAL_DisableDBGSleepMode(void); -void HAL_EnableDBGStopMode(void); -void HAL_DisableDBGStopMode(void); -void HAL_EnableDBGStandbyMode(void); -void HAL_DisableDBGStandbyMode(void); +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); #if defined(DUAL_CORE) void HAL_EnableDomain2DBGSleepMode(void); void HAL_DisableDomain2DBGSleepMode(void); @@ -1140,4 +1139,4 @@ void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1); #endif /* STM32H7xx_HAL_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h index 155aaa7c7..b9ec8004b 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -131,8 +130,8 @@ typedef struct Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: - and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, - use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ + and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, + use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, after the first ADC conversion start trigger occurred (software start or external trigger). @@ -2032,4 +2031,3 @@ void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc); #endif /* STM32H7xx_HAL_ADC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h index ae185074d..9e00e1516 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -250,8 +249,10 @@ typedef struct #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */ +#if defined(HRTIM1) #define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */ +#endif /* HRTIM1 */ #define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */ #define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. Trigger edge set to rising edge (default setting). */ @@ -1044,6 +1045,7 @@ typedef struct * @param __INJTRIG__ programmed ADC injected conversions external trigger. * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) */ +#if defined (HRTIM1) #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ @@ -1060,9 +1062,36 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \ \ ((__INJTRIG__) == ADC_SOFTWARE_START) ) - +#else +#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \ + \ + ((__INJTRIG__) == ADC_SOFTWARE_START) ) +#endif /* HRTIM */ /** * @brief Verify the ADC edge trigger setting for injected group. * @param __EDGE__ programmed ADC edge trigger setting. @@ -1349,4 +1378,3 @@ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *h #endif /* STM32H7xx_HAL_ADC_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cec.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cec.h index e4ff48d33..7547acb11 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cec.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cec.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -105,7 +104,7 @@ typedef struct uint16_t OwnAddress; /*!< Own addresses configuration This parameter can be a value of @ref CEC_OWN_ADDRESS */ - uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */ + uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */ } CEC_InitTypeDef; @@ -121,14 +120,14 @@ typedef struct * b6 Error information * 0 : No Error * 1 : Error - * b5 IP initialization status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP initialized. HAL CEC Init function already called) + * b5 CEC peripheral initialization status + * 0 : Reset (peripheral not initialized) + * 1 : Init done (peripheral initialized. HAL CEC Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state * 0 : Ready - * 1 : Busy (IP busy with some configuration or internal operations) + * 1 : Busy (peripheral busy with some configuration or internal operations) * b1 (not used) * x : Should be set to 0 * b0 Tx state @@ -138,9 +137,9 @@ typedef struct * RxState value coding follow below described bitmap : * b7-b6 (not used) * xx : Should be set to 00 - * b5 IP initialization status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP initialized) + * b5 CEC peripheral initialization status + * 0 : Reset (peripheral not initialized) + * 1 : Init done (peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -791,4 +790,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); #endif /* STM32H7xxHAL_CEC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_comp.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_comp.h index 1db50aa22..ba42ed117 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_comp.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_comp.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -951,4 +950,4 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp); #endif /* STM32H7xx_HAL_COMP_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h index 05bf9c5f6..574000009 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h @@ -8,13 +8,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -510,4 +509,4 @@ #endif /* STM32H7xx_HAL_CONF_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cordic.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cordic.h index 04e2d79b5..7f8d5d9d4 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cordic.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cordic.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -608,5 +607,3 @@ uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic); #endif #endif /* STM32H7xx_HAL_CORDIC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h index 17b111ce1..2645c28fb 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -458,4 +457,3 @@ uint32_t HAL_GetCurrentCPUID(void); #endif /* STM32H7xx_HAL_CORTEX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_crc.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_crc.h index e1ebe4c70..f41b123cb 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_crc.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_crc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -60,19 +59,22 @@ typedef struct { uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used. If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default - X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. + X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + + X^4 + X^2+ X +1. In that case, there is no need to set GeneratingPolynomial field. - If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */ + If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and + CRCLength fields must be set. */ uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. If set to DEFAULT_INIT_VALUE_ENABLE, resort to default - 0xFFFFFFFF value. In that case, there is no need to set InitValue field. - If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */ + 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If + otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */ uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree - respectively equal to 7, 8, 16 or 32. This field is written in normal representation, - e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. - No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */ + respectively equal to 7, 8, 16 or 32. This field is written in normal, + representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 + is written 0x65. No need to specify it if DefaultPolynomialUse is set to + DEFAULT_POLYNOMIAL_ENABLE. */ uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length. Value can be either one of @@ -87,14 +89,18 @@ typedef struct uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. Can be either one of the following values @arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion - @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2 - @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C - @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */ + @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D + becomes 0x58D43CB2 + @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, + 0x1A2B3C4D becomes 0xD458B23C + @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D + becomes 0xB23CD458 */ uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. Can be either @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, - @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */ + @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted + into 0x22CC4488 */ } CRC_InitTypeDef; /** @@ -112,12 +118,16 @@ typedef struct uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. Can be either - @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data) - @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data) - @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data) - - Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error - must occur if InputBufferFormat is not one of the three values listed above */ + @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes + (8-bit data) + @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of + half-words (16-bit data) + @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words + (32-bit data) + + Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization + error must occur if InputBufferFormat is not one of the three values listed + above */ } CRC_HandleTypeDef; /** * @} @@ -199,15 +209,6 @@ typedef struct * @} */ -/** @defgroup CRC_Aliases CRC API aliases - * @{ - */ -#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ -#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ -/** - * @} - */ - /** * @} */ @@ -339,5 +340,3 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); #endif #endif /* STM32H7xx_HAL_CRC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_crc_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_crc_ex.h index 0ca334fbf..bc7022618 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_crc_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_crc_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -149,5 +148,3 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ #endif #endif /* STM32H7xx_HAL_CRC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h index 619c86285..769254776 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -565,4 +564,3 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); #endif /* STM32H7xx_HAL_CRYP_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp_ex.h index 117598a78..8820e0b7a 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -120,4 +119,3 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u #endif /* STM32H7xx_HAL_CRYP_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac.h index fb2ff1bba..1c4832332 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -79,17 +78,19 @@ typedef struct __IO uint32_t ErrorCode; /*!< DAC Error code */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac); - - void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac); - void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + + void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + + + void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); + void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } DAC_HandleTypeDef; @@ -136,9 +137,7 @@ typedef struct uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ - DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ - } DAC_ChannelConfTypeDef; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) @@ -151,10 +150,12 @@ typedef enum HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */ HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */ HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */ + HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */ HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */ HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */ HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */ + HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */ @@ -240,7 +241,9 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @{ */ #define DAC_CHANNEL_1 0x00000000U + #define DAC_CHANNEL_2 0x00000010U + /** * @} */ @@ -260,8 +263,10 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @{ */ #define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) + #define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) + /** * @} */ @@ -270,8 +275,10 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @{ */ #define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1) + #define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2) + /** * @} */ @@ -351,12 +358,14 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); */ #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__)) + /** @brief Set DHR12R2 alignment. * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__)) + /** @brief Set DHR12RD alignment. * @param __ALIGNMENT__ specifies the DAC alignment * @retval None @@ -541,7 +550,5 @@ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); #endif -#endif /*STM32H7xx_HAL_DAC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32H7xx_HAL_DAC_H */ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac_ex.h index d1dbf4a72..8fcd75ae2 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -268,6 +267,5 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); } #endif -#endif /*STM32H7xx_HAL_DAC_EX_H */ +#endif /* STM32H7xx_HAL_DAC_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h index 244fc2726..e844fbba8 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -668,4 +667,3 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); #endif /* STM32H7xx_HAL_DCMI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h index f7e3c1345..69101d6f5 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -218,4 +217,4 @@ typedef enum #endif /* STM32H7xx_HAL_DEF */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm.h index 189efd0c9..bce318403 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -870,4 +869,3 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe #endif /* STM32H7xx_HAL_DFSDM_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm_ex.h index f9cd61cc1..6252debaa 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -90,4 +89,3 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeD #endif /* STM32H7xx_HAL_DFSDM_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h index 7da442085..1c299d58b 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1324,4 +1323,3 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); #endif /* STM32H7xx_HAL_DMA_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h index d5acb3f5f..00f205bc0 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -342,15 +341,6 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointe * @} */ -/** @defgroup DMA2D_Aliases DMA2D API Aliases - * @{ - */ -#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort - for compatibility with legacy code */ -/** - * @} - */ - #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) /** * @brief HAL DMA2D common Callback ID enumeration definition @@ -723,6 +713,3 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); #endif #endif /* STM32H7xx_HAL_DMA2D_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h index 481a20442..cde57552a 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -309,4 +308,3 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); #endif /* STM32H7xx_HAL_DMA_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dsi.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dsi.h index 06d9ae593..ec36c4637 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dsi.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dsi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -40,6 +39,9 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ +/** @defgroup DSI_Exported_Types DSI Exported Types + * @{ + */ /** * @brief DSI Init Structure definition */ @@ -61,14 +63,14 @@ typedef struct */ typedef struct { - uint32_t PLLNDIV; /*!< PLL Loop Division Factor - This parameter must be a value between 10 and 125 */ + uint32_t PLLNDIV; /*!< PLL Loop Division Factor + This parameter must be a value between 10 and 125 */ - uint32_t PLLIDF; /*!< PLL Input Division Factor - This parameter can be any value of @ref DSI_PLL_IDF */ + uint32_t PLLIDF; /*!< PLL Input Division Factor + This parameter can be any value of @ref DSI_PLL_IDF */ - uint32_t PLLODF; /*!< PLL Output Division Factor - This parameter can be any value of @ref DSI_PLL_ODF */ + uint32_t PLLODF; /*!< PLL Output Division Factor + This parameter can be any value of @ref DSI_PLL_ODF */ } DSI_PLLInitTypeDef; @@ -346,6 +348,9 @@ typedef enum typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */ #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ +/** + * @} + */ /* Exported constants --------------------------------------------------------*/ /** @defgroup DSI_Exported_Constants DSI Exported Constants @@ -700,8 +705,8 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE -#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ - DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ +#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ + DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ DSI_FLOW_CONTROL_EOTP_TX) /** * @} @@ -841,18 +846,18 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @{ */ #define HAL_DSI_ERROR_NONE 0U -#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */ -#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ -#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */ -#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */ -#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ -#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ -#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ -#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ -#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ -#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ +#define HAL_DSI_ERROR_ACK 0x00000001U /*!< Acknowledge errors */ +#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ +#define HAL_DSI_ERROR_TX 0x00000004U /*!< Transmission error */ +#define HAL_DSI_ERROR_RX 0x00000008U /*!< Reception error */ +#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ +#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ +#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ +#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ +#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ +#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) -#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */ +#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */ #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ /** * @} @@ -912,6 +917,7 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @} */ + /** * @} */ @@ -955,11 +961,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_DISABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ - /* Delay after an DSI Host disabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + /* Delay after an DSI Host disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -968,11 +974,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - /* Delay after an DSI warpper enabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + /* Delay after an DSI warpper enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -981,11 +987,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - /* Delay after an DSI warpper disabling*/ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + /* Delay after an DSI warpper disabling*/ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -994,11 +1000,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ - /* Delay after an DSI PLL enabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + /* Delay after an DSI PLL enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -1007,11 +1013,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ - /* Delay after an DSI PLL disabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + /* Delay after an DSI PLL disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -1033,11 +1039,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ - /* Delay after an DSI regulator disabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + /* Delay after an DSI regulator disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -1121,23 +1127,41 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to /** @defgroup DSI_Exported_Functions DSI Exported Functions * @{ */ +/** @defgroup DSI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * @{ + */ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi); void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi); void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi); - -void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); -void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); -void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); -void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); - +HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, pDSI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup DSI_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); +void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); +/** + * @} + */ +/** @defgroup DSI_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); @@ -1190,40 +1214,28 @@ HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, Functional HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State); HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State); -uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); -HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); -HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); /** * @} */ -/* Private types -------------------------------------------------------------*/ -/** @defgroup DSI_Private_Types DSI Private Types +/** @defgroup DSI_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions * @{ */ +uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); +HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); /** * @} */ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup DSI_Private_Defines DSI Private Defines - * @{ - */ - /** * @} */ +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/** @defgroup DSI_Private_Variables DSI Private Variables - * @{ - */ - -/** - * @} - */ - /* Private constants ---------------------------------------------------------*/ /** @defgroup DSI_Private_Constants DSI Private Constants * @{ @@ -1249,45 +1261,73 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); ((ODF) == DSI_PLL_OUT_DIV2) || \ ((ODF) == DSI_PLL_OUT_DIV4) || \ ((ODF) == DSI_PLL_OUT_DIV8)) -#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) -#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) +#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE)\ + || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) +#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE)\ + || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL) #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U) -#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) -#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) -#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) -#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) +#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE)\ + || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) +#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\ + || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) +#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH)\ + || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) +#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH)\ + || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ ((VideoModeType) == DSI_VID_MODE_BURST)) -#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) +#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL)\ + || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF)) -#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) +#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE)\ + || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE)) #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE)) -#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE)) +#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE)\ + || ((LPVActive) == DSI_LP_VACT_ENABLE)) #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE)) #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE)) -#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) -#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) +#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE)\ + || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) +#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE)\ + || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL)) -#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE)) -#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE)) -#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING)) -#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) -#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) -#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) -#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) -#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) -#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) -#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) -#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) -#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE)) -#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) -#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) -#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) -#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE)) -#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) +#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE)\ + || ((TEPolarity) == DSI_TE_FALLING_EDGE)) +#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE)\ + || ((AutomaticRefresh) == DSI_AR_ENABLE)) +#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING)\ + || ((VSPolarity) == DSI_VSYNC_RISING)) +#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE)\ + || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE)\ + || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE)\ + || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) +#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE)\ + || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) +#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE)\ + || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) +#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE)\ + || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) +#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE)\ + || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) +#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE)\ + || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) +#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE)\ + || ((LP_GLW) == DSI_LP_GLW_ENABLE)) +#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE)\ + || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) +#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE)\ + || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) +#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE)\ + || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) +#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE)\ + || ((LP_DLW) == DSI_LP_DLW_ENABLE)) +#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE)\ + || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \ ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \ ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \ @@ -1299,10 +1339,14 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \ ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \ ((MODE) == DSI_GEN_SHORT_PKT_READ_P2)) -#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY)) +#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || \ + ((CommDelay) == DSI_SLEW_RATE_LPTX) || \ + ((CommDelay) == DSI_HS_DELAY)) #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES)) -#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) -#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) +#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS)\ + || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) +#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || \ + ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ ((Timing) == DSI_TLPX_CLK ) || \ ((Timing) == DSI_THS_EXIT ) || \ @@ -1317,24 +1361,6 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); * @} */ -/* Private functions prototypes ----------------------------------------------*/ -/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes - * @{ - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup DSI_Private_Functions DSI Private Functions - * @{ - */ - -/** - * @} - */ - /** * @} */ @@ -1349,5 +1375,3 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); #endif #endif /* STM32H7xx_HAL_DSI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dts.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dts.h index 63815fb47..f30de7742 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dts.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dts.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -480,4 +479,3 @@ void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts); #endif /* __STM32H7xx_HAL_DTS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h index 354ce3f5f..e3330bdff 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h @@ -6,23 +6,22 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32H7xx_HAL_ETH_H #define STM32H7xx_HAL_ETH_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif @@ -37,23 +36,35 @@ /** @addtogroup ETH * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ #ifndef ETH_TX_DESC_CNT - #define ETH_TX_DESC_CNT 4U -#endif - +#define ETH_TX_DESC_CNT 4U +#endif /* ETH_TX_DESC_CNT */ + #ifndef ETH_RX_DESC_CNT - #define ETH_RX_DESC_CNT 4U -#endif +#define ETH_RX_DESC_CNT 4U +#endif /* ETH_RX_DESC_CNT */ + +#ifndef ETH_SWRESET_TIMEOUT +#define ETH_SWRESET_TIMEOUT ((uint32_t)500U) +#endif /* ETH_SWRESET_TIMEOUT */ + +#ifndef ETH_MDIO_BUS_TIMEOUT +#define ETH_MDIO_BUS_TIMEOUT ((uint32_t)1000U) +#endif /* ETH_MDIO_BUS_TIMEOUT */ + +#ifndef ETH_MAC_US_TICK +#define ETH_MAC_US_TICK ((uint32_t)1000000U) +#endif /* ETH_MAC_US_TICK */ /*********************** Descriptors struct def section ************************/ /** @defgroup ETH_Exported_Types ETH Exported Types * @{ */ -/** +/** * @brief ETH DMA Descriptor structure definition */ typedef struct @@ -64,180 +75,180 @@ typedef struct __IO uint32_t DESC3; uint32_t BackupAddr0; /* used to store rx buffer 1 address */ uint32_t BackupAddr1; /* used to store rx buffer 2 address */ -}ETH_DMADescTypeDef; -/** - * +} ETH_DMADescTypeDef; +/** + * */ -/** +/** * @brief ETH Buffers List structure definition */ typedef struct __ETH_BufferTypeDef { uint8_t *buffer; /*gState = HAL_ETH_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \ - } while(0) + (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ + } while(0) #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ -/** +/** * @brief Enables the specified ETHERNET DMA interrupts. * @param __HANDLE__ : ETH Handle * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be * enabled @ref ETH_DMA_Interrupts * @retval None */ -#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__)) +#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__)) /** * @brief Disables the specified ETHERNET DMA interrupts. @@ -1398,7 +1530,7 @@ typedef struct{ * disabled. @ref ETH_DMA_Interrupts * @retval None */ -#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__)) +#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__)) /** * @brief Gets the ETHERNET DMA IT source enabled or disabled. @@ -1406,7 +1538,8 @@ typedef struct{ * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts * @retval The ETH DMA IT Source enabled or disabled */ -#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Gets the ETHERNET DMA IT pending bit. @@ -1414,57 +1547,59 @@ typedef struct{ * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts * @retval The state of ETH DMA IT (SET or RESET) */ -#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__)) - +#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__)) + /** * @brief Clears the ETHERNET DMA IT pending bit. * @param __HANDLE__ : ETH Handle * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts * @retval None */ -#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__)) +#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__)) /** * @brief Checks whether the specified ETHERNET DMA flag is set or not. -* @param __HANDLE__: ETH Handle + * @param __HANDLE__: ETH Handle * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags * @retval The state of ETH DMA FLAG (SET or RESET). */ -#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__)) +#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__)) /** * @brief Clears the specified ETHERNET DMA flag. -* @param __HANDLE__: ETH Handle + * @param __HANDLE__: ETH Handle * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags * @retval The state of ETH DMA FLAG (SET or RESET). */ -#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__)) - -/** +#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__)) + +/** * @brief Enables the specified ETHERNET MAC interrupts. * @param __HANDLE__ : ETH Handle * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be * enabled @ref ETH_MAC_Interrupts * @retval None */ -#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__)) - -/** +#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__)) + +/** * @brief Disables the specified ETHERNET MAC interrupts. * @param __HANDLE__ : ETH Handle * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be * enabled @ref ETH_MAC_Interrupts * @retval None */ -#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__)) - +#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__)) + /** * @brief Checks whether the specified ETHERNET MAC flag is set or not. * @param __HANDLE__: ETH Handle * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts * @retval The state of ETH MAC IT (SET or RESET). */ -#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__)) +#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__)) /*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */ #define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00400000U) /* !< 86 - 64 = 22 */ @@ -1472,7 +1607,7 @@ typedef struct{ /** * @brief Enable the ETH WAKEUP Exti Line. * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. - * @arg ETH_WAKEUP_EXTI_LINE + * @arg ETH_WAKEUP_EXTI_LINE * @retval None. */ #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR3 |= (__EXTI_LINE__)) @@ -1480,7 +1615,7 @@ typedef struct{ /** * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. - * @arg ETH_WAKEUP_EXTI_LINE + * @arg ETH_WAKEUP_EXTI_LINE * @retval EXTI ETH WAKEUP Line Status. */ #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 & (__EXTI_LINE__)) @@ -1488,7 +1623,7 @@ typedef struct{ /** * @brief Clear the ETH WAKEUP Exti flag. * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. - * @arg ETH_WAKEUP_EXTI_LINE + * @arg ETH_WAKEUP_EXTI_LINE * @retval None. */ #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__)) @@ -1497,15 +1632,15 @@ typedef struct{ /** * @brief Enable the ETH WAKEUP Exti Line by Core2. * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. - * @arg ETH_WAKEUP_EXTI_LINE + * @arg ETH_WAKEUP_EXTI_LINE * @retval None. */ -#define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__) (EXTI_D2->IMR3 |= (__EXTI_LINE__)) +#define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__) (EXTI_D2->IMR3 |= (__EXTI_LINE__)) /** * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. - * @arg ETH_WAKEUP_EXTI_LINE + * @arg ETH_WAKEUP_EXTI_LINE * @retval EXTI ETH WAKEUP Line Status. */ #define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 & (__EXTI_LINE__)) @@ -1513,11 +1648,11 @@ typedef struct{ /** * @brief Clear the ETH WAKEUP Exti flag. * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. - * @arg ETH_WAKEUP_EXTI_LINE + * @arg ETH_WAKEUP_EXTI_LINE * @retval None. */ #define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__)) -#endif +#endif /* DUAL_CORE */ /** * @brief enable rising edge interrupt on selected EXTI line. @@ -1526,7 +1661,7 @@ typedef struct{ * @retval None */ #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \ - (EXTI->RTSR3 |= (__EXTI_LINE__)) + (EXTI->RTSR3 |= (__EXTI_LINE__)) /** * @brief enable falling edge interrupt on selected EXTI line. @@ -1535,7 +1670,7 @@ typedef struct{ * @retval None */ #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\ - (EXTI->FTSR3 |= (__EXTI_LINE__)) + (EXTI->FTSR3 |= (__EXTI_LINE__)) /** * @brief enable falling edge interrupt on selected EXTI line. @@ -1544,7 +1679,7 @@ typedef struct{ * @retval None */ #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\ - (EXTI->FTSR3 |= (__EXTI_LINE__)) + (EXTI->FTSR3 |= (__EXTI_LINE__)) /** * @brief Generates a Software interrupt on selected EXTI line. @@ -1554,6 +1689,10 @@ typedef struct{ */ #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__)) +#define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->MACTSCR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +#define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->MACTSCR |= (__FLAG__)) /** * @} */ @@ -1566,20 +1705,20 @@ typedef struct{ /** @addtogroup ETH_Exported_Functions * @{ */ - + /** @addtogroup ETH_Exported_Functions_Group1 * @{ - */ + */ /* Initialization and de initialization functions **********************************/ -HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); -void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); -void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1,uint8_t *pBuffer2); +HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, + pETH_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ @@ -1596,26 +1735,50 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth); HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth); -uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer); -HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length); -HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo); -HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff); +HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, + pETH_rxAllocateCallbackTypeDef rxAllocateCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode); +HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth); + +#ifdef HAL_ETH_USE_PTP +HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); +HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); +HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); +HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); +HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, + ETH_TimeTypeDef *timeoffset); +HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); +HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); +HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth); +#endif /* HAL_ETH_USE_PTP */ HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout); HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig); -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue); -HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue); +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t RegValue); +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t *pRegValue); void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth); void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth); void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_RxAllocateCallback(uint8_t **buff); +void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length); +void HAL_ETH_TxFreeCallback(uint32_t *buff); +void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp); /** * @} */ @@ -1632,7 +1795,8 @@ HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth); /* MAC VLAN Processing APIs ************************************************/ -void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier); +void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, + uint32_t VLANIdentifier); /* MAC L2 Packet Filtering APIs **********************************************/ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); @@ -1660,19 +1824,19 @@ uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth); uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth); /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ #endif /* ETH */ @@ -1683,5 +1847,3 @@ uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth); #endif /* STM32H7xx_HAL_ETH_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h index cec388784..0b56acf15 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h @@ -6,23 +6,22 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32H7xx_HAL_ETH_EX_H #define STM32H7xx_HAL_ETH_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif #if defined(ETH) @@ -42,126 +41,131 @@ /** @defgroup ETHEx_Exported_Types ETHEx Exported Types * @{ */ - -/** + +/** * @brief ETH RX VLAN structure definition */ -typedef struct{ +typedef struct +{ FunctionalState InnerVLANTagInStatus; /*!< Enables or disables Inner VLAN Tag in Rx Status */ - - uint32_t StripInnerVLANTag; /*!< Sets the Inner VLAN Tag Stripping on Receive - This parameter can be a value of @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */ - + + uint32_t StripInnerVLANTag; /*!< Sets the Inner VLAN Tag Stripping on Receive + This parameter can be a value of + @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */ + FunctionalState InnerVLANTag; /*!< Enables or disables Inner VLAN Tag */ FunctionalState DoubleVLANProcessing; /*!< Enable or Disable double VLAN processing */ - + FunctionalState VLANTagHashTableMatch; /*!< Enable or Disable VLAN Tag Hash Table Match */ - + FunctionalState VLANTagInStatus; /*!< Enable or Disable VLAN Tag in Rx status */ - - uint32_t StripVLANTag; /*!< Set the VLAN Tag Stripping on Receive + + uint32_t StripVLANTag; /*!< Set the VLAN Tag Stripping on Receive This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */ - + uint32_t VLANTypeCheck; /*!< Enable or Disable VLAN Type Check This parameter can be a value of @ref ETHEx_VLAN_Type_Check */ - - FunctionalState VLANTagInverceMatch; /*!< Enable or disable VLAN Tag Inverse Match */ -}ETH_RxVLANConfigTypeDef; -/** - * - */ - -/** + + FunctionalState VLANTagInverceMatch; /*!< Enable or disable VLAN Tag Inverse Match */ +} ETH_RxVLANConfigTypeDef; +/** + * + */ + +/** * @brief ETH TX VLAN structure definition */ -typedef struct{ +typedef struct +{ FunctionalState SourceTxDesc; /*!< Enable or Disable VLAN tag source from DMA tx descriptors */ - + FunctionalState SVLANType; /*!< Enable or Disable insertion of SVLAN type */ - + uint32_t VLANTagControl; /*!< Sets the VLAN tag control in tx packets This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */ -}ETH_TxVLANConfigTypeDef; -/** - * +} ETH_TxVLANConfigTypeDef; +/** + * */ -/** +/** * @brief ETH L3 filter structure definition */ -typedef struct{ +typedef struct +{ uint32_t Protocol; /*!< Sets the L3 filter protocol to IPv4 or IPv6 This parameter can be a value of @ref ETHEx_L3_Protocol */ - + uint32_t SrcAddrFilterMatch; /*!< Sets the L3 filter source address match This parameter can be a value of @ref ETHEx_L3_Source_Match */ - + uint32_t DestAddrFilterMatch; /*!< Sets the L3 filter destination address match This parameter can be a value of @ref ETHEx_L3_Destination_Match */ - + uint32_t SrcAddrHigherBitsMatch; /*!< Sets the L3 filter source address higher bits match This parameter can be a value from 0 to 31 */ - + uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match This parameter can be a value from 0 to 31 */ - + uint32_t Ip4SrcAddr; /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used This parameter can be a value from 0x0 to 0xFFFFFFFF */ - + uint32_t Ip4DestAddr; /*!< Sets the L3 filter IPv4 destination address if IPv4 protocol is used This parameter can be a value from 0 to 0xFFFFFFFF */ - + uint32_t Ip6Addr[4]; /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used This parameter must be a table of 4 words (4* 32 bits) */ -}ETH_L3FilterConfigTypeDef; -/** - * +} ETH_L3FilterConfigTypeDef; +/** + * */ -/** +/** * @brief ETH L4 filter structure definition */ -typedef struct{ +typedef struct +{ uint32_t Protocol; /*!< Sets the L4 filter protocol to TCP or UDP This parameter can be a value of @ref ETHEx_L4_Protocol */ - + uint32_t SrcPortFilterMatch; /*!< Sets the L4 filter source port match This parameter can be a value of @ref ETHEx_L4_Source_Match */ - + uint32_t DestPortFilterMatch; /*!< Sets the L4 filter destination port match This parameter can be a value of @ref ETHEx_L4_Destination_Match */ - - uint32_t SourcePort; /*!< Sets the L4 filter source port + + uint32_t SourcePort; /*!< Sets the L4 filter source port + This parameter must be a value from 0x0 to 0xFFFF */ + + uint32_t DestinationPort; /*!< Sets the L4 filter destination port This parameter must be a value from 0x0 to 0xFFFF */ - - uint32_t DestinationPort; /*!< Sets the L4 filter destination port - This parameter must be a value from 0x0 to 0xFFFF */ -}ETH_L4FilterConfigTypeDef; -/** - * - */ - +} ETH_L4FilterConfigTypeDef; +/** + * + */ + /** * @} */ - + /* Exported constants --------------------------------------------------------*/ /** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants * @{ */ - + /** @defgroup ETHEx_LPI_Event ETHEx LPI Event * @{ - */ -#define ETH_TX_LPI_ENTRY ETH_MACLCSR_TLPIEN -#define ETH_TX_LPI_EXIT ETH_MACLCSR_TLPIEX + */ +#define ETH_TX_LPI_ENTRY ETH_MACLCSR_TLPIEN +#define ETH_TX_LPI_EXIT ETH_MACLCSR_TLPIEX #define ETH_RX_LPI_ENTRY ETH_MACLCSR_RLPIEN #define ETH_RX_LPI_EXIT ETH_MACLCSR_RLPIEX /** * @} */ - + /** @defgroup ETHEx_L3_Filter ETHEx L3 Filter * @{ */ @@ -198,7 +202,7 @@ typedef struct{ /** * @} */ - + /** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match * @{ */ @@ -208,7 +212,7 @@ typedef struct{ /** * @} */ - + /** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol * @{ */ @@ -217,17 +221,17 @@ typedef struct{ /** * @} */ - + /** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match * @{ */ #define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4SPM -#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM) +#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM) #define ETH_L4_SRC_PORT_MATCH_DISABLE ((uint32_t)0x00000000) /** * @} */ - + /** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match * @{ */ @@ -237,10 +241,10 @@ typedef struct{ /** * @} */ - + /** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping * @{ - */ + */ #define ETH_INNERVLANTAGRXSTRIPPING_NONE ETH_MACVTR_EIVLS_DONOTSTRIP #define ETH_INNERVLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EIVLS_STRIPIFPASS #define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS @@ -251,7 +255,7 @@ typedef struct{ /** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping * @{ - */ + */ #define ETH_VLANTAGRXSTRIPPING_NONE ETH_MACVTR_EVLS_DONOTSTRIP #define ETH_VLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EVLS_STRIPIFPASS #define ETH_VLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS @@ -259,17 +263,17 @@ typedef struct{ /** * @} */ - + /** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check * @{ - */ + */ #define ETH_VLANTYPECHECK_DISABLE ETH_MACVTR_DOVLTC #define ETH_VLANTYPECHECK_SVLAN (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL) #define ETH_VLANTYPECHECK_CVLAN ((uint32_t)0x00000000) /** * @} */ - + /** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control * @{ */ @@ -279,21 +283,21 @@ typedef struct{ #define ETH_VLANTAGCONTROL_REPLACE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE) /** * @} - */ - + */ + /** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag * @{ - */ + */ #define ETH_INNER_TX_VLANTAG ((uint32_t)0x00000001U) #define ETH_OUTER_TX_VLANTAG ((uint32_t)0x00000000U) /** * @} - */ - + */ + /** * @} */ - + /* Exported functions --------------------------------------------------------*/ /** @addtogroup ETHEx_Exported_Functions * @{ @@ -305,15 +309,19 @@ typedef struct{ /* MAC ARP Offloading APIs ***************************************************/ void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth); void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth); -void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress); +void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress); /* MAC L3 L4 Filtering APIs ***************************************************/ void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth); void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig); -HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig); -HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig); -HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig); +HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L3FilterConfigTypeDef *pL3FilterConfig); +HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L4FilterConfigTypeDef *pL4FilterConfig); +HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L3FilterConfigTypeDef *pL3FilterConfig); +HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L4FilterConfigTypeDef *pL4FilterConfig); /* MAC VLAN Processing APIs ************************************************/ void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth); @@ -321,26 +329,29 @@ void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth); HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig); HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig); void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable); -HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig); -HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig); -void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier); +HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag, + ETH_TxVLANConfigTypeDef *pVlanConfig); +HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag, + ETH_TxVLANConfigTypeDef *pVlanConfig); +void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier); /* Energy Efficient Ethernet APIs *********************************************/ -void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop); +void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, + FunctionalState TxClockStop); void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth); uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth); - + /** * @} - */ + */ /** * @} */ - + /** * @} - */ + */ /** * @} @@ -354,4 +365,4 @@ uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth); #endif /* STM32H7xx_HAL_ETH_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h index f31cacfc0..91d7d952a 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -536,4 +535,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); #endif /* STM32H7xx_HAL_EXTI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h index ecc6290f5..47f1fac3c 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -304,12 +303,15 @@ typedef struct uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element. This parameter must be a number between: - 0 and 127, if IdType is FDCAN_STANDARD_ID - - 0 and 63, if IdType is FDCAN_EXTENDED_ID */ + - 0 and 63, if IdType is FDCAN_EXTENDED_ID + When the frame is a Non-Filter matching frame, this parameter + is unused. */ uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter. - Acceptance of non-matching frames may be enabled via - HAL_FDCAN_ConfigGlobalFilter(). - This parameter can be 0 or 1 */ + Acceptance of non-matching frames may be enabled via + HAL_FDCAN_ConfigGlobalFilter(). + This parameter takes 0 if the frame matched an Rx filter or + 1 if it did not match any Rx filter */ } FDCAN_RxHeaderTypeDef; @@ -479,7 +481,7 @@ typedef struct This parameter can be a value of @ref FDCAN_TT_time_master */ uint32_t SyncDevLimit; /*!< Specifies the Synchronization Deviation Limit SDL of the TUR - numerator : TUR = (Numerator SDL) / Denominator. + numerator : TUR = (Numerator +/- SDL) / Denominator. With : SDL = 2^(SyncDevLimit+5). This parameter must be a number between 0 and 7 */ @@ -514,7 +516,7 @@ typedef struct This parameter is ignored if OperationMode is set to FDCAN_TT_COMMUNICATION_LEVEL0 */ - uint32_t BasicCyclesNbr; /*!< Specifies the nubmer of basic cycles in the system matrix. + uint32_t BasicCyclesNbr; /*!< Specifies the number of basic cycles in the system matrix. This parameter can be a value of @ref FDCAN_TT_basic_cycle_number */ uint32_t CycleStartSync; /*!< Enable or disable synchronization pulse output at pin fdcan1_soc. @@ -529,7 +531,7 @@ typedef struct This parameter must be a number between 0 and 4095 */ uint32_t TURNumerator; /*!< Specifies the TUR (Time Unit Ratio) numerator. - It is adviced to set this parameter to the largest applicable value. + It is advised to set this parameter to the largest applicable value. This parameter must be a number between 0x10000 and 0x1FFFF */ uint32_t TURDenominator; /*!< Specifies the TUR (Time Unit Ratio) denominator. @@ -641,7 +643,7 @@ typedef struct - 0 : No Gap in schedule - 1 : Gap time after Basic Cycle has started */ - uint32_t WaitForEvt; /*!< Specifies whether a Gap is annouced. + uint32_t WaitForEvt; /*!< Specifies whether a Gap is announced. This parameter can be: - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0 - 1 : Reference message with Next_is_Gap = 1 received */ @@ -1259,21 +1261,21 @@ typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan * @{ */ #define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */ -#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2 */ -#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3 */ -#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4 */ -#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5 */ -#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6 */ -#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7 */ -#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8 */ -#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9 */ -#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */ -#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */ -#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */ -#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */ -#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */ -#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */ -#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */ +#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2 */ +#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3 */ +#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4 */ +#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5 */ +#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6 */ +#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7 */ +#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8 */ +#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9 */ +#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */ +#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */ +#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */ +#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */ +#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */ +#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */ +#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */ /** * @} */ @@ -2377,6 +2379,10 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan); ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \ ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \ ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME)) + +#define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET) + +#define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** * @} */ @@ -2414,4 +2420,3 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan); #endif /* STM32H7xx_HAL_FDCAN_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h index 8a47e0b0b..a4773b5b0 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -861,4 +859,3 @@ HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank #endif /* STM32H7xx_HAL_FLASH_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h index 96119b9c8..f822f09bb 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -359,6 +357,8 @@ typedef struct #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ + +/* Unused FLASH Latency defines */ #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycle */ #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycle */ #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */ @@ -1012,4 +1012,3 @@ void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange); #endif /* STM32H7xx_HAL_FLASH_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fmac.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fmac.h index 8eb9941e6..25b760ff2 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fmac.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fmac.h @@ -2,18 +2,16 @@ ****************************************************************************** * @file stm32h7xx_hal_fmac.h * @author MCD Application Team - * @brief This file contains all the functions prototypes for the FMAC firmware - * library. + * @brief Header for stm32h7xx_hal_fmac.c module ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -82,14 +80,16 @@ typedef struct uint16_t InputCurrentSize; /*!< Number of the input elements already written into FMAC */ uint16_t *pInputSize; /*!< Number of input elements to write (memory allocated to pInput). - In case of early interruption of the filter operation, its value will be updated. */ + In case of early interruption of the filter operation, + its value will be updated. */ int16_t *pOutput; /*!< Pointer to FMAC output data buffer */ uint16_t OutputCurrentSize; /*!< Number of the output elements already read from FMAC */ uint16_t *pOutputSize; /*!< Number of output elements to read (memory allocated to pOutput). - In case of early interruption of the filter operation, its value will be updated. */ + In case of early interruption of the filter operation, + its value will be updated. */ DMA_HandleTypeDef *hdmaIn; /*!< FMAC peripheral input data DMA handle parameters */ @@ -136,7 +136,7 @@ typedef struct #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1) /** - * @brief FMAC Callback ID structure definition + * @brief FMAC Callback ID enumeration definition */ typedef enum { @@ -165,33 +165,38 @@ typedef void (*pFMAC_CallbackTypeDef)(FMAC_HandleTypeDef *hfmac); /*!< pointer typedef struct { uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF). - Ignored if InputBufferSize is set to 0 (previous configuration kept). - NB: the buffers can overlap or even coincide exactly. */ + Ignored if InputBufferSize is set to 0 + (previous configuration kept). + Note: the buffers can overlap or even coincide exactly. */ - uint8_t InputBufferSize; /*!< Number of 16-bit addresses allocated to the input buffer (including the optional "headroom"). + uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer (including the optional "headroom"). 0 if a previous configuration should be kept. */ uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number of free spaces - in the buffer is inferior to this threshold. - This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */ + in the buffer is lower than this threshold. + This parameter can be a value + of @ref FMAC_Data_Buffer_Threshold. */ uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF). - Ignored if CoeffBufferSize is set to 0 (previous configuration kept). - NB: the buffers can overlap or even coincide exactly. */ + Ignored if CoeffBufferSize is set to 0 + (previous configuration kept). + Note: the buffers can overlap or even coincide exactly. */ - uint8_t CoeffBufferSize; /*!< Number of 16-bit addresses allocated to the coefficient buffer. + uint8_t CoeffBufferSize; /*!< Number of 16-bit words allocated to the coefficient buffer. 0 if a previous configuration should be kept. */ uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF). - Ignored if OuputBufferSize is set to 0 (previous configuration kept). - NB: the buffers can overlap or even coincide exactly. */ + Ignored if OuputBufferSize is set to 0 + (previous configuration kept). + Note: the buffers can overlap or even coincide exactly. */ - uint8_t OutputBufferSize; /*!< Number of 16-bit addresses allocated to the output buffer (including the optional "headroom"). + uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer (including the optional "headroom"). 0 if a previous configuration should be kept. */ uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number of unread values - in the buffer is inferior to this threshold. - This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */ + in the buffer is lower than this threshold. + This parameter can be a value + of @ref FMAC_Data_Buffer_Threshold. */ int16_t *pCoeffA; /*!< [IIR only] Initialization of the coefficient vector A. If not needed, it should be set to NULL. */ @@ -199,21 +204,25 @@ typedef struct uint8_t CoeffASize; /*!< Size of the coefficient vector A. */ int16_t *pCoeffB; /*!< Initialization of the coefficient vector B. - If not needed (re-use of a previously loaded buffer), it should be set to NULL. */ + If not needed (re-use of a previously loaded buffer), + it should be set to NULL. */ uint8_t CoeffBSize; /*!< Size of the coefficient vector B. */ - uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMT, IT, Polling, None. + uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None. This parameter can be a value of @ref FMAC_Buffer_Access. */ uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None. This parameter can be a value of @ref FMAC_Buffer_Access. */ - uint32_t Clip; /*!< Enable or disable the clipping feature (wrapping when the q1.15 range is exceeded). + uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range is exceeded, wrapping + is done when the clipping feature is disabled + and saturation is done when the clipping feature is enabled. This parameter can be a value of @ref FMAC_Clip_State. */ uint32_t Filter; /*!< Filter type. - This parameter can be a value of @ref FMAC_Functions (filter related values). */ + This parameter can be a value + of @ref FMAC_Functions (filter related values). */ uint8_t P; /*!< Parameter P (vector length, number of filter taps, etc.). */ @@ -238,17 +247,17 @@ typedef struct /** @defgroup FMAC_Error_Code FMAC Error code * @{ */ -#define HAL_FMAC_ERROR_NONE 0x00000000UL /*!< No error */ -#define HAL_FMAC_ERROR_SAT 0x00000001UL /*!< Saturation error */ -#define HAL_FMAC_ERROR_UNFL 0x00000002UL /*!< Underflow error */ -#define HAL_FMAC_ERROR_OVFL 0x00000004UL /*!< Overflow error */ -#define HAL_FMAC_ERROR_DMA 0x00000008UL /*!< DMA error */ -#define HAL_FMAC_ERROR_RESET 0x00000010UL /*!< Reset error */ -#define HAL_FMAC_ERROR_PARAM 0x00000020UL /*!< Parameter error */ +#define HAL_FMAC_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_FMAC_ERROR_SAT 0x00000001U /*!< Saturation error */ +#define HAL_FMAC_ERROR_UNFL 0x00000002U /*!< Underflow error */ +#define HAL_FMAC_ERROR_OVFL 0x00000004U /*!< Overflow error */ +#define HAL_FMAC_ERROR_DMA 0x00000008U /*!< DMA error */ +#define HAL_FMAC_ERROR_RESET 0x00000010U /*!< Reset error */ +#define HAL_FMAC_ERROR_PARAM 0x00000020U /*!< Parameter error */ #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1) -#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040UL /*!< Invalid Callback error */ +#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid Callback error */ #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ -#define HAL_FMAC_ERROR_TIMEOUT 0x00000080UL /*!< Timeout error */ +#define HAL_FMAC_ERROR_TIMEOUT 0x00000080U /*!< Timeout error */ /** * @} @@ -257,11 +266,11 @@ typedef struct /** @defgroup FMAC_Functions FMAC Functions * @{ */ -#define FMAC_FUNC_LOAD_X1 ((uint32_t)(FMAC_PARAM_FUNC_0)) /*!< Load X1 buffer */ -#define FMAC_FUNC_LOAD_X2 ((uint32_t)(FMAC_PARAM_FUNC_1)) /*!< Load X2 buffer */ -#define FMAC_FUNC_LOAD_Y ((uint32_t)(FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)) /*!< Load Y buffer */ -#define FMAC_FUNC_CONVO_FIR ((uint32_t)(FMAC_PARAM_FUNC_3)) /*!< Convolution (FIR filter) */ -#define FMAC_FUNC_IIR_DIRECT_FORM_1 ((uint32_t)(FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)) /*!< IIR filter (direct form 1) */ +#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */ +#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */ +#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */ +#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */ +#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */ /** * @} */ @@ -270,15 +279,19 @@ typedef struct * @{ * @note This parameter sets a watermark for buffer full (input) or buffer empty (output). */ -#define FMAC_THRESHOLD_1 0x00000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1. - Output: Buffer empty flag set if the number of unread values in the buffer is less than 1. */ -#define FMAC_THRESHOLD_2 0x01000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2. - Output: Buffer empty flag set if the number of unread values in the buffer is less than 2. */ -#define FMAC_THRESHOLD_4 0x02000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4. - Output: Buffer empty flag set if the number of unread values in the buffer is less than 4. */ -#define FMAC_THRESHOLD_8 0x03000000UL /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8. - Output: Buffer empty flag set if the number of unread values in the buffer is less than 8. */ -#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFUL /*!< The configured threshold value shouldn't be changed */ +#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1. + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 1. */ +#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2. + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 2. */ +#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4. + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 4. */ +#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8. + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 8. */ +#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU /*!< The configured threshold value shouldn't be changed */ /** * @} */ @@ -287,7 +300,7 @@ typedef struct * @{ */ #define FMAC_BUFFER_ACCESS_NONE 0x00U /*!< Buffer handled by an external IP (ADC for instance) */ -#define FMAC_BUFFER_ACCESS_DMA 0x01U /*!< Buffer accessed through the FMAC DMA */ +#define FMAC_BUFFER_ACCESS_DMA 0x01U /*!< Buffer accessed through DMA */ #define FMAC_BUFFER_ACCESS_POLLING 0x02U /*!< Buffer accessed through polling */ #define FMAC_BUFFER_ACCESS_IT 0x03U /*!< Buffer accessed through interruptions */ /** @@ -297,7 +310,7 @@ typedef struct /** @defgroup FMAC_Clip_State FMAC Clip State * @{ */ -#define FMAC_CLIP_DISABLED 0x00000000UL /*!< Clipping disabled */ +#define FMAC_CLIP_DISABLED 0x00000000U /*!< Clipping disabled */ #define FMAC_CLIP_ENABLED FMAC_CR_CLIPEN /*!< Clipping enabled */ /** * @} @@ -327,52 +340,20 @@ typedef struct * @} */ -/** @defgroup FMAC_DMAR DMA Read Request Enable bit - * @{ - */ -#define FMAC_DMA_REN FMAC_CR_DMAREN /*!< DMA Read Requests Enable */ /** * @} */ -/** @defgroup FMAC_DMAW DMA Write Request Enable bit - * @{ - */ -#define FMAC_DMA_WEN FMAC_CR_DMAWEN /*!< DMA Write Channel Enable */ -/** - * @} - */ -/** @defgroup FMAC_DMAS DMA START bit +/* External variables --------------------------------------------------------*/ +/** @defgroup FMAC_External_variables FMAC External variables * @{ */ -#define FMAC_START FMAC_PARAM_START /*!< DMA Start */ /** * @} */ -/** @defgroup FMAC_TimeOut_Value FMAC polling-based communications time-out value - * @{ - */ -#define HAL_FMAC_TIMEOUT_VALUE 1000UL /*!< FMAC polling-based communications time-out value */ -/** - * @} - */ - -/** @defgroup FMAC_Reset_TimeOut_Value FMAC reset time-out value - * @{ - */ -#define HAL_FMAC_RESET_TIMEOUT_VALUE 500UL /*!< FMAC reset time-out value */ -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /** @defgroup FMAC_Exported_Macros FMAC Exported Macros * @{ */ @@ -392,10 +373,10 @@ typedef struct #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ /** - * @brief Enable the FMAC interrupt when result is ready + * @brief Enable the specified FMAC interrupt * @param __HANDLE__ FMAC handle. * @param __INTERRUPT__ FMAC Interrupt. - * This parameter can be one of the following values: + * This parameter can be any combination of the following values: * @arg @ref FMAC_IT_RIEN Read interrupt enable * @arg @ref FMAC_IT_WIEN Write interrupt enable * @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable @@ -410,7 +391,7 @@ typedef struct * @brief Disable the FMAC interrupt * @param __HANDLE__ FMAC handle. * @param __INTERRUPT__ FMAC Interrupt. - * This parameter can be one of the following values: + * This parameter can be any combination of the following values: * @arg @ref FMAC_IT_RIEN Read interrupt enable * @arg @ref FMAC_IT_WIEN Write interrupt enable * @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable @@ -424,7 +405,7 @@ typedef struct /** @brief Check whether the specified FMAC interrupt occurred or not. * @param __HANDLE__ FMAC handle. * @param __INTERRUPT__ FMAC interrupt to check. - * This parameter can be one of the following values: + * This parameter can be any combination of the following values: * @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag * @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag * @arg @ref FMAC_FLAG_OVFL Overflow Error Flag @@ -446,7 +427,7 @@ typedef struct /** @brief Check whether the specified FMAC status flag is set or not. * @param __HANDLE__ FMAC handle. * @param __FLAG__ FMAC flag to check. - * This parameter can be one of the following values: + * This parameter can be any combination of the following values: * @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag * @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag * @arg @ref FMAC_FLAG_OVFL Overflow Error Flag @@ -483,8 +464,8 @@ typedef struct * @} */ -/* Private macros --------------------------------------------------------*/ -/** @addtogroup FMAC_Private_Macros +/* Private Macros-----------------------------------------------------------*/ +/** @addtogroup FMAC_Private_Macros FMAC Private Macros * @{ */ @@ -500,7 +481,7 @@ typedef struct ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)) /** - * @brief Verify the FMAC load function. + * @brief Verify the FMAC load function used for input data, output data or coefficients. * @param __FUNCTION__ ID of the load function. * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid) */ @@ -509,7 +490,7 @@ typedef struct ((__FUNCTION__) == FMAC_FUNC_LOAD_Y)) /** - * @brief Verify the FMAC load function. + * @brief Verify the FMAC load function used with N values as input or output data. * @param __FUNCTION__ ID of the load function. * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid) */ @@ -517,7 +498,7 @@ typedef struct ((__FUNCTION__) == FMAC_FUNC_LOAD_Y)) /** - * @brief Verify the FMAC load function. + * @brief Verify the FMAC load function used with N + M values as coefficients. * @param __FUNCTION__ ID of the load function. * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid) */ @@ -592,6 +573,21 @@ typedef struct #define IS_FMAC_CLIP_STATE(__CLIP_STATE__) (((__CLIP_STATE__) == FMAC_CLIP_DISABLED) || \ ((__CLIP_STATE__) == FMAC_CLIP_ENABLED)) +/** + * @brief Check whether the threshold is applicable. + * @param __SIZE__ Size of the matching buffer. + * @param __WM__ Watermark value. + * @param __ACCESS__ Access to the buffer (polling, it, dma, none). + * @retval THRESHOLD + */ +#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) \ + (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \ + ((__WM__) == FMAC_THRESHOLD_2)? 2U: \ + ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \ + ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&& \ + ((__WM__) == FMAC_THRESHOLD_1))|| \ + ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA))) + /** * @} */ @@ -624,8 +620,8 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig); -HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig); +HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig); +HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig); HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize); HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, @@ -692,5 +688,3 @@ uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac); #endif #endif /* STM32H7xx_HAL_FMAC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gfxmmu.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gfxmmu.h index 8248bede2..819f3eadf 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gfxmmu.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gfxmmu.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -450,4 +449,3 @@ uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu); #endif /* STM32H7xx_HAL_GFXMMU_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h index 52f8ecddc..1cd9178bb 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -108,29 +107,26 @@ typedef enum /** @defgroup GPIO_mode_define GPIO mode define * @brief GPIO Configuration Mode - * Elements values convention: 0xX0yz00YZ - * - X : GPIO mode or EXTI Mode - * - y : External IT or Event trigger detection - * - z : IO configuration on External IT or Event - * - Y : Output type (Push Pull or Open Drain) - * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits * @{ */ -#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */ - -#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */ - -#define GPIO_MODE_IT_RISING (0x11110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING (0x11210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING (0x11310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ - -#define GPIO_MODE_EVT_RISING (0x11120000U) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING (0x11220000U) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING (0x11320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} */ @@ -286,7 +282,25 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); /** @defgroup GPIO_Private_Constants GPIO Private Constants * @{ */ - +#define GPIO_MODE_Pos 0u +#define GPIO_MODE (0x3uL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0uL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos) +#define MODE_AF (0x2uL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4u +#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16u +#define EXTI_MODE (0x3uL << EXTI_MODE_Pos) +#define EXTI_IT (0x1uL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2uL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20u +#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos) +#define TRIGGER_LEVEL (0x4uL << TRIGGER_MODE_Pos) /** * @} */ @@ -343,4 +357,3 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); #endif /* STM32H7xx_HAL_GPIO_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h index dc56483a4..7a8edd311 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -486,4 +485,3 @@ extern "C" { #endif /* STM32H7xx_HAL_GPIO_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash.h index 605ee8315..15b1213f1 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -22,7 +21,7 @@ #define STM32H7xx_HAL_HASH_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -51,7 +50,7 @@ typedef struct uint32_t KeySize; /*!< The key size is used only in HMAC operation. */ - uint8_t* pKey; /*!< The key is used only in HMAC operation. */ + uint8_t *pKey; /*!< The key is used only in HMAC operation. */ } HASH_InitTypeDef; @@ -66,7 +65,7 @@ typedef enum HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */ HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */ HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */ -}HAL_HASH_StateTypeDef; +} HAL_HASH_StateTypeDef; /** * @brief HAL phase structures definition @@ -81,7 +80,7 @@ typedef enum (step 2 consists in entering the message text) */ HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase (step 3 consists in entering the outer hash function key) */ -}HAL_HASH_PhaseTypeDef; +} HAL_HASH_PhaseTypeDef; /** * @brief HAL HASH mode suspend definitions @@ -90,7 +89,7 @@ typedef enum { HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */ HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */ -}HAL_HASH_SuspendTypeDef; +} HAL_HASH_SuspendTypeDef; #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) /** @@ -103,7 +102,7 @@ typedef enum HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */ HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */ HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */ -}HAL_HASH_CallbackIDTypeDef; +} HAL_HASH_CallbackIDTypeDef; #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ @@ -155,15 +154,15 @@ typedef struct __IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */ #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */ + void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH input completion callback */ - void (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH digest computation completion callback */ + void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH digest computation completion callback */ - void (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH error callback */ + void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH error callback */ - void (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp Init callback */ + void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp Init callback */ - void (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */ + void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp DeInit callback */ #endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ } HASH_HandleTypeDef; @@ -172,7 +171,7 @@ typedef struct /** * @brief HAL HASH Callback pointer definition */ -typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */ +typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer to a HASH common callback functions */ #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ /** @@ -244,13 +243,6 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer #define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */ #define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */ -/** - * @} - */ -/** @defgroup HASH_alias HASH API alias - * @{ - */ -#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */ /** * @} */ @@ -288,8 +280,8 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \ - ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\ - ((HASH->SR & (__FLAG__)) == (__FLAG__)) ) + ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\ + ((HASH->SR & (__FLAG__)) == (__FLAG__)) ) /** @brief Clear the specified HASH flag. @@ -366,7 +358,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer * @brief Set the number of valid bits in the last word written in data register DIN. * @param __SIZE__ size in bytes of last data written in Data register. * @retval None -*/ + */ #define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U)) /** @@ -389,8 +381,8 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer * @retval Digest length */ #define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \ - ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \ - ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) ) + ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \ + ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) ) /** * @brief Return number of words already pushed in the FIFO. * @retval Number of words already pushed in the FIFO @@ -424,7 +416,8 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer * @param __SIZE__ input data buffer size. * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) */ -#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U)) +#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET)\ + || (((__SIZE__) % 4U) == 0U)) /** * @brief Ensure that handle phase is set to HASH processing. * @param __HANDLE__ HASH handle. @@ -467,7 +460,8 @@ void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash); void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, + pHASH_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ @@ -482,12 +476,16 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS /* HASH processing using polling *********************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout); HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -499,12 +497,16 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p */ /* HASH processing using IT **************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); /** * @} @@ -516,9 +518,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); /* HASH processing using DMA *************************************************/ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** * @} @@ -529,8 +531,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu */ /* HASH-MAC processing using polling *****************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout); +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout); /** * @} @@ -540,8 +544,10 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @{ */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); /** * @} @@ -567,8 +573,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn /* Peripheral State methods **************************************************/ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash); HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash); -void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer); -void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer); +void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); +void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); @@ -588,14 +594,18 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); */ /* Private functions */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout, uint32_t Algorithm); HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Algorithm); HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout, uint32_t Algorithm); +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Algorithm); HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); /** @@ -618,4 +628,3 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, #endif /* STM32H7xx_HAL_HASH_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash_ex.h index 2d8459d87..78fc650fc 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -22,7 +21,7 @@ #define STM32H7xx_HAL_HASH_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -51,12 +50,16 @@ * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); /** * @} @@ -66,12 +69,16 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); /** * @} @@ -81,9 +88,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @{ */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** * @} @@ -92,8 +99,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p /** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); /** * @} */ @@ -102,8 +111,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); /** * @} @@ -162,4 +173,3 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 #endif /* STM32H7xx_HAL_HASH_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hcd.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hcd.h index 82862629c..6443015b3 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hcd.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hcd.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -111,11 +110,16 @@ typedef struct #define HCD_SPEED_HIGH USBH_HS_SPEED #define HCD_SPEED_FULL USBH_FSLS_SPEED #define HCD_SPEED_LOW USBH_FSLS_SPEED +/** + * @} + */ +/** @defgroup HCD_Device_Speed HCD Device Speed + * @{ + */ #define HCD_DEVICE_SPEED_HIGH 0U #define HCD_DEVICE_SPEED_FULL 1U #define HCD_DEVICE_SPEED_LOW 2U - /** * @} */ @@ -153,7 +157,8 @@ typedef struct #define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ + & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) @@ -296,11 +301,11 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /* Private functions prototypes ----------------------------------------------*/ /** - * @} - */ + * @} + */ /** - * @} - */ + * @} + */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #ifdef __cplusplus @@ -308,5 +313,3 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); #endif #endif /* STM32H7xx_HAL_HCD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h index 798ad823a..4b418f2c5 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -996,7 +995,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source * @{ * @brief Constants defining the events that can be selected to configure the - * set crossbar of a timer output + * reset crossbar of a timer output */ #define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */ #define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */ @@ -1010,15 +1009,15 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ -#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ -#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ -#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ -#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ -#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ -#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ -#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ -#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ #define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */ @@ -1137,21 +1136,21 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * by a timer */ #define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */ -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */ -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */ -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */ -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */ -#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */ +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */ +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */ +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */ +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */ +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */ +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */ +#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */ /** * @} */ @@ -1346,10 +1345,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @brief Constants defining the source and event to be sent on the * synchronization outputs */ -#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */ -#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/ -#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */ -#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */ +#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */ +#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */ +#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */ +#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */ /** * @} */ @@ -3642,5 +3641,3 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * h #endif #endif /* STM32H7xx_HAL_HRTIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h index df57b7730..45f6e07d9 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -130,12 +129,12 @@ extern "C" { HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID); /* HSEM semaphore fast take (lock) using 1-Step method ***********************/ HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID); -/* HSEM Check semaphore state Taken or not **********************************/ -uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID); /* HSEM Release **************************************************************/ void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID); /* HSEM Release All************************************************************/ void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID); +/* HSEM Check semaphore state Taken or not **********************************/ +uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID); /** * @} @@ -210,5 +209,3 @@ void HAL_HSEM_IRQHandler(void); #endif #endif /* STM32H7xx_HAL_HSEM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h index 9962ac132..0b882ac0d 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -48,29 +47,30 @@ extern "C" { typedef struct { uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization - section in Reference manual */ + This parameter calculated by referring to I2C initialization section + in Reference manual */ uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ + This parameter can be a 7-bit or 10-bit address. */ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ + This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing + mode is selected. + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ } I2C_InitTypeDef; @@ -200,7 +200,8 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + /*!< I2C transfer IRQ handler function pointer */ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ @@ -217,20 +218,32 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ - void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ - void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ - void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ - void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ - void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ - void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ - void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ - void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ - - void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ - - void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ - void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp DeInit callback */ #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } I2C_HandleTypeDef; @@ -259,8 +272,11 @@ typedef enum /** * @brief HAL I2C Callback pointer definition */ -typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ -typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); +/*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an I2C Address Match callback function */ #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** @@ -440,14 +456,14 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * @retval None */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) -#endif +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** @brief Enable the specified I2C interrupt. * @param __HANDLE__ specifies the I2C Handle. @@ -542,26 +558,27 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * * @retval None */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ - : ((__HANDLE__)->Instance->ICR = (__FLAG__))) +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified I2C peripheral. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Disable the specified I2C peripheral. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) /** * @} */ @@ -601,12 +618,14 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); */ /* IO operation functions ****************************************************/ /******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, @@ -757,10 +776,14 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) #define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ - (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) - -#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)) -#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)) + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \ + >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \ + >> 16U)) #define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) #define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) #define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) @@ -772,10 +795,15 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); (uint16_t)(0xFF00U))) >> 8U))) #define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) -#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_ADD10) | (I2C_CR2_START)) & \ + (~I2C_CR2_RD_WRN))) -#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) #define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) /** @@ -805,5 +833,3 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #endif /* STM32H7xx_HAL_I2C_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h index 79099801b..e701b8b08 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -67,7 +66,7 @@ extern "C" { #define I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus on I2C5 pins */ #else #define I2C_FASTMODEPLUS_I2C5 (uint32_t)(0x00001000U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C5 not supported */ -#endif +#endif /* SYSCFG_PMCR_I2C5_FMP */ /** * @} */ @@ -90,7 +89,7 @@ extern "C" { * @{ */ -/** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions +/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions * @{ */ /* Peripheral Control functions ************************************************/ @@ -100,7 +99,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ * @} */ -/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions +/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions * @{ */ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); @@ -109,7 +108,7 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); * @} */ -/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions +/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions * @{ */ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); @@ -118,7 +117,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @} */ - /** * @} */ @@ -141,7 +139,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) -#if (defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP) && defined(SYSCFG_PMCR_I2C4_FMP)) #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ @@ -150,28 +147,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4)) -#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP) -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3)) -#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2)) -#elif defined(SYSCFG_PMCR_I2C1_FMP) -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1)) -#endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */ /** * @} */ @@ -198,5 +173,3 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #endif #endif /* STM32H7xx_HAL_I2C_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h index 66762f450..060f5b64a 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -122,7 +121,7 @@ typedef struct __I2S_HandleTypeDef void (*RxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Rx ISR */ void (*TxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Tx ISR */ - + DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */ @@ -324,12 +323,12 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to /** @defgroup I2S_Flags_Definition I2S Flags Definition * @{ */ -#define I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag : Rx-Packet available flag */ -#define I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag : Tx-Packet space available flag */ -#define I2S_FLAG_DXP SPI_SR_DXP /* I2S status flag : Dx-Packet space available flag */ -#define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag : Underrun flag */ -#define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag : Overrun flag */ -#define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag : TI mode frame format error flag */ +#define I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag : Rx-Packet available flag */ +#define I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag : Tx-Packet space available flag */ +#define I2S_FLAG_DXP SPI_SR_DXP /* I2S status flag : Dx-Packet space available flag */ +#define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag : Underrun flag */ +#define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag : Overrun flag */ +#define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag : TI mode frame format error flag */ #define I2S_FLAG_MASK (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_DXP |SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE) /** @@ -357,7 +356,7 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to } while(0) #else #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) -#endif +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ /** @brief Enable the specified SPI peripheral (in I2S mode). * @param __HANDLE__ specifies the I2S Handle. @@ -415,7 +414,8 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to * @arg I2S_IT_ERR : Error interrupt enable * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified I2S flag is set or not. * @param __HANDLE__ specifies the I2S Handle. @@ -469,7 +469,8 @@ void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) -HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, + pI2S_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ /** @@ -498,7 +499,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, - uint16_t Size); + uint16_t Size); HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); @@ -557,7 +558,9 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); * @arg I2S_FLAG_FRE : TI mode frame format error flag * @retval SET or RESET. */ -#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) +#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\ + & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK))\ + ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. * @param __IER__ copy of I2S IER register. @@ -571,7 +574,8 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); * @arg I2S_IT_ERR : Error interrupt enable * @retval SET or RESET. */ -#define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__) ((((__IER__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__) ((((__IER__)\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if I2S Mode parameter is in allowed range. * @param __MODE__ specifies the I2S Mode. @@ -592,9 +596,9 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); #define IS_I2S_SLAVE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ ((__MODE__) == I2S_MODE_SLAVE_RX) || \ ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX)) - + #define IS_I2S_FULLDUPLEX(__MODE__) (((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX) || \ - ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX)) + ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX)) #define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \ ((__STANDARD__) == I2S_STANDARD_MSB) || \ @@ -612,7 +616,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); #define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \ ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \ - ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT)) + ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT)) #define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \ ((__CPOL__) == I2S_CPOL_HIGH)) @@ -648,4 +652,3 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); #endif /* STM32H7xx_HAL_I2S_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s_ex.h index 0f745077e..231781d34 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s_ex.h @@ -6,17 +6,16 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - + /** ****************************************************************************** ===== I2S FULL DUPLEX FEATURE ===== @@ -25,4 +24,3 @@ */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda.h index 869f840e1..f789217ab 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -126,7 +125,7 @@ typedef enum IRDA_CLOCKSOURCE_D2PCLK1 = 0x11U, /*!< Domain2 PCLK1 clock source */ IRDA_CLOCKSOURCE_D2PCLK2 = 0x12U, /*!< Domain2 PCLK2 clock source */ IRDA_CLOCKSOURCE_PLL2Q = 0x14U, /*!< PLL2Q clock source */ - IRDA_CLOCKSOURCE_PLL3Q = 0x18U, /*!< PCLK2 clock source */ + IRDA_CLOCKSOURCE_PLL3Q = 0x18U, /*!< PLL3Q clock source */ IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ IRDA_CLOCKSOURCE_CSI = 0x08U, /*!< CSI clock source */ IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */ @@ -146,7 +145,7 @@ typedef struct IRDA_InitTypeDef Init; /*!< IRDA communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ uint16_t TxXferSize; /*!< IRDA Tx Transfer size */ @@ -830,11 +829,11 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); @@ -893,4 +892,3 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); #endif /* STM32H7xx_HAL_IRDA_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda_ex.h index c1a2f2072..a7a1ea310 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -647,4 +646,3 @@ extern "C" { #endif /* STM32H7xx_HAL_IRDA_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_iwdg.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_iwdg.h index 93d30256c..895c33b91 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_iwdg.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_iwdg.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -236,5 +235,3 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); #endif #endif /* STM32H7xx_HAL_IWDG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_jpeg.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_jpeg.h index 16176c345..d2ecdf877 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_jpeg.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_jpeg.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -652,4 +651,3 @@ uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg); #endif /* STM32H7xx_HAL_JPEG_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_lptim.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_lptim.h index 7275614e9..3ae7d76b8 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_lptim.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_lptim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -96,30 +95,30 @@ typedef struct */ typedef struct { - LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ + LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ - LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */ + LPTIM_ULPClockConfigTypeDef UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */ - LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ + LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ - uint32_t OutputPolarity; /*!< Specifies the Output polarity. - This parameter can be a value of @ref LPTIM_Output_Polarity */ + uint32_t OutputPolarity; /*!< Specifies the Output polarity. + This parameter can be a value of @ref LPTIM_Output_Polarity */ - uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare - values is done immediately or after the end of current period. - This parameter can be a value of @ref LPTIM_Updating_Mode */ + uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare + values is done immediately or after the end of current period. + This parameter can be a value of @ref LPTIM_Updating_Mode */ - uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event - or each external event. - This parameter can be a value of @ref LPTIM_Counter_Source */ + uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event + or each external event. + This parameter can be a value of @ref LPTIM_Counter_Source */ - uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output). - This parameter can be a value of @ref LPTIM_Input1_Source */ + uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output). + This parameter can be a value of @ref LPTIM_Input1_Source */ - uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output). - Note: This parameter is used only for encoder feature so is used only - for LPTIM1 instance. - This parameter can be a value of @ref LPTIM_Input2_Source */ + uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output). + Note: This parameter is used only for encoder feature so is used only + for LPTIM1 instance. + This parameter can be a value of @ref LPTIM_Input2_Source */ } LPTIM_InitTypeDef; /** @@ -751,11 +750,13 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) -#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL) +#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\ + ((__AUTORELOAD__) <= 0x0000FFFFUL)) #define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) -#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL) +#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\ + ((__PERIOD__) <= 0x0000FFFFUL)) #define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL) @@ -808,5 +809,3 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim); #endif #endif /* STM32H7xx_HAL_LPTIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h index 3785b57ed..0eaa4154c 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -80,28 +79,36 @@ typedef struct This parameter can be one of value of @ref LTDC_PC_POLARITY */ uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. - This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */ uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height. - This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. - This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ uint32_t AccumulatedActiveH; /*!< configures the accumulated active height. - This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */ uint32_t TotalWidth; /*!< configures the total width. - This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */ uint32_t TotalHeigh; /*!< configures the total height. - This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */ LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */ } LTDC_InitTypeDef; @@ -112,25 +119,31 @@ typedef struct typedef struct { uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t WindowY0; /*!< Configures the Window vertical Start Position. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ uint32_t WindowY1; /*!< Configures the Window vertical Stop Position. - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x7FF. */ uint32_t PixelFormat; /*!< Specifies the pixel format. This parameter can be one of value of @ref LTDC_Pixelformat */ uint32_t Alpha; /*!< Specifies the constant alpha used for blending. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + This parameter must be a number between + Min_Data = 0x00 and Max_Data = 0xFF. */ uint32_t Alpha0; /*!< Configures the default alpha value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + This parameter must be a number between + Min_Data = 0x00 and Max_Data = 0xFF. */ uint32_t BlendingFactor1; /*!< Select the blending factor 1. This parameter can be one of value of @ref LTDC_BlendingFactor1 */ @@ -141,10 +154,12 @@ typedef struct uint32_t FBStartAdress; /*!< Configures the color frame buffer address */ uint32_t ImageWidth; /*!< Configures the color frame buffer line length. - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x1FFF. */ uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */ } LTDC_LayerCfgTypeDef; @@ -400,7 +415,7 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer * @retval None */ #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) -#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \ +#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->State = HAL_LTDC_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ @@ -430,7 +445,8 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). * @retval None. */ -#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN) +#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\ + |= (uint32_t)LTDC_LxCR_LEN) /** * @brief Disable the LTDC Layer. @@ -439,7 +455,8 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). * @retval None. */ -#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN) +#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\ + &= ~(uint32_t)LTDC_LxCR_LEN) /** * @brief Reload immediately all LTDC Layers. @@ -545,7 +562,8 @@ void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, + pLTDC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ @@ -583,9 +601,12 @@ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc); HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc); HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType); -HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, + uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); @@ -621,12 +642,18 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); /** @defgroup LTDC_Private_Macros LTDC Private Macros * @{ */ -#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__))))) +#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(\ + ((uint32_t)((__HANDLE__)->Instance))\ + + 0x84U + (0x80U*(__LAYER__))))) #define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER) -#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH)) -#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH)) -#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH)) -#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC)) +#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL)\ + || ((__HSPOL__) == LTDC_HSPOLARITY_AH)) +#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL)\ + || ((__VSPOL__) == LTDC_VSPOLARITY_AH)) +#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL)\ + || ((__DEPOL__) == LTDC_DEPOLARITY_AH)) +#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC)\ + || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC)) #define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC) #define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC) #define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC) @@ -642,10 +669,14 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA)) #define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \ ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA)) -#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \ - ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \ - ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \ - ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88)) +#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88)) #define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA) #define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION) #define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION) @@ -655,7 +686,8 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); #define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER) #define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER) #define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU) -#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING)) +#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || \ + ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING)) /** * @} */ @@ -685,4 +717,3 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); #endif /* STM32H7xx_HAL_LTDC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc_ex.h index f95a18c09..15e9adf7b 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -82,5 +81,3 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD #endif #endif /* STM32H7xx_HAL_LTDC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdios.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdios.h index f4954b47b..50c61f41d 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdios.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdios.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -607,4 +606,3 @@ HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios); #endif /* STM32H7xx_HAL_MDIOS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h index 2e5f8e111..a39cc0d75 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -867,4 +866,3 @@ uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma); #endif /* STM32H7xx_HAL_MDMA_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h index db25542b3..f8f0daf54 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -64,15 +63,18 @@ typedef enum */ typedef uint32_t HAL_MMC_CardStateTypeDef; -#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */ -#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */ -#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ -#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ -#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ -#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ -#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ -#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ -#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */ +#define HAL_MMC_CARD_IDLE 0x00000000U /*!< Card is in idle state (can't be checked by CMD13) */ +#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready (can't be checked by CMD13) */ +#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state (can't be checked by CMD13) */ +#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ +#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ +#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ +#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ +#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ +#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ +#define HAL_MMC_CARD_BUSTEST 0x00000009U /*!< Card is in bus test state */ +#define HAL_MMC_CARD_SLEEP 0x0000000AU /*!< Card is in sleep state (can't be checked by CMD13) */ +#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error (can't be checked by CMD13) */ /** * @} */ @@ -342,9 +344,9 @@ typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc); #define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */ #define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */ #define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */ -#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */ -#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */ -#define eMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */ +#define EMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */ +#define EMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */ +#define EMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */ #define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U /** * @} @@ -729,6 +731,14 @@ HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, ui * @} */ +/** @defgroup MMC_Exported_Functions_Group8 Peripheral Sleep management + * @{ + */ +HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc); +/** + * @} + */ /* Private types -------------------------------------------------------------*/ /** @defgroup MMC_Private_Types MMC Private Types * @{ @@ -812,5 +822,3 @@ HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, ui #endif /* STM32H7xx_HAL_MMC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc_ex.h index 256f98672..215749583 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -111,5 +110,3 @@ void HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc); #endif /* STM32H7xx_HAL_MMCEx_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h index 3141ec949..fdf845af2 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -324,8 +323,10 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); * @retval NAND Raw address value */ #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ - (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * \ - ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) + (((__ADDRESS__)->Block + \ + (((__ADDRESS__)->Plane) * \ + ((__HANDLE__)->Config.PlaneSize))) * \ + ((__HANDLE__)->Config.BlockSize))) /** * @brief NAND memory Column address computation. @@ -374,5 +375,3 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); #endif #endif /* STM32H7xx_HAL_NAND_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nor.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nor.h index d614cb066..1ef78f4cb 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nor.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nor.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -323,5 +322,3 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres #endif #endif /* STM32H7xx_HAL_NOR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h index 006ff5ab7..95a36b093 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -455,4 +454,3 @@ HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp); #endif /* STM32H7xx_HAL_OPAMP_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp_ex.h index 855ebc45c..a08d563b2 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -80,4 +79,3 @@ HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp); #endif /* STM32H7xx_HAL_OPAMP_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ospi.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ospi.h index 6d7471ffc..78e991aad 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ospi.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ospi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -81,9 +80,6 @@ typedef struct uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and defines the boundary of bytes to release the chip select. This parameter can be a value between 0 and 31 */ - uint32_t ClkChipSelectHighTime; /*!< It defines the number of clocks provided on the CLK/nCLK pins when - the chip select is set to high at the end of a transaction. - This parameter can be a value between 0 and 7 */ uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected by the delay block. This parameter can be a value of @ref OSPI_DelayBlockBypass */ @@ -259,7 +255,7 @@ typedef struct This parameter can be a value of @ref OSPIM_IOPort */ uint32_t IOHighPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins. This parameter can be a value of @ref OSPIM_IOPort */ - uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected + uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected if some signals are multiplexed in the OSPI IO Manager with the other OSPI. This parameter can be a value between 1 and 256 */ }OSPIM_CfgTypeDef; @@ -1028,8 +1024,6 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeD #define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U) -#define IS_OSPI_CKCSHT(CLK_NB) ((CLK_NB) <= 7U) - #define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \ ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED)) @@ -1079,5 +1073,3 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeD #endif #endif /* STM32H7xx_HAL_OSPI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_otfdec.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_otfdec.h index 3a49ef2ac..bfdfb0b45 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_otfdec.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_otfdec.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -22,7 +21,7 @@ #define STM32H7xx_HAL_OTFDEC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -61,7 +60,7 @@ typedef struct uint16_t Version; /*!< OTFDEC region firmware version */ -}OTFDEC_RegionConfigTypeDef; +} OTFDEC_RegionConfigTypeDef; /** * @} @@ -79,7 +78,7 @@ typedef enum HAL_OTFDEC_STATE_RESET = 0x00U, /*!< OTFDEC not yet initialized or disabled */ HAL_OTFDEC_STATE_READY = 0x01U, /*!< OTFDEC initialized and ready for use */ HAL_OTFDEC_STATE_BUSY = 0x02U, /*!< OTFDEC internal processing is ongoing */ -}HAL_OTFDEC_StateTypeDef; +} HAL_OTFDEC_StateTypeDef; /** * @brief OTFDEC handle structure definition @@ -106,7 +105,7 @@ typedef struct void (* MspDeInitCallback)(struct __OTFDEC_HandleTypeDef *hotfdec); /*!< OTFDEC Msp DeInit callback */ #endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */ -}OTFDEC_HandleTypeDef; +} OTFDEC_HandleTypeDef; #if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1) /** @@ -267,7 +266,7 @@ typedef void (*pOTFDEC_CallbackTypeDef)(OTFDEC_HandleTypeDef *hotfdec); /*!< po */ #define __HAL_OTFDEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT(((__HANDLE__)->Instance->IER), (__INTERRUPT__)) - /** @brief Check whether the specified combination of OTFDEC interrupt flags is set or not. +/** @brief Check whether the specified combination of OTFDEC interrupt flags is set or not. * @param __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains * the configuration information for OTFDEC module * @param __FLAG__ mask on combination of interrupts flags @@ -279,7 +278,7 @@ typedef void (*pOTFDEC_CallbackTypeDef)(OTFDEC_HandleTypeDef *hotfdec); /*!< po * @arg @ref OTFDEC_SEC_KEY_ERROR_INT OTFDEC security and key errors interrupts flags * @arg @ref OTFDEC_EXE_KEY_ERROR_INT OTFDEC execution and key errors interrupts flag * @arg @ref OTFDEC_ALL_INT OTFDEC all interrupts flags - * @retval The state of __FLAG__ (TRUE or FALSE). + * @retval The state of __FLAG__ (TRUE or FALSE). */ #define __HAL_OTFDEC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) @@ -319,7 +318,7 @@ void HAL_OTFDEC_MspDeInit(OTFDEC_HandleTypeDef *hotfdec); #if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID, - pOTFDEC_CallbackTypeDef pCallback); + pOTFDEC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_OTFDEC_UnRegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */ /** @@ -342,7 +341,7 @@ void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec); HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey); HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode); -HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, +HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config, uint32_t lock); uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey); HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); @@ -423,10 +422,11 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint * @param __MODE__ OTFDEC region operating mode parameter. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ -#define IS_OTFDEC_REGION_OPERATING_MODE(__MODE__) (((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY) || \ - ((__MODE__) == OTFDEC_REG_MODE_DATA_ACCESSES_ONLY) || \ - ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES) || \ - ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER)) +#define IS_OTFDEC_REGION_OPERATING_MODE(__MODE__) \ + (((__MODE__)== OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY) || \ + ((__MODE__) == OTFDEC_REG_MODE_DATA_ACCESSES_ONLY) || \ + ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES) || \ + ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER)) /** * @brief Verify the OTFDEC region index. @@ -474,6 +474,3 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint #endif #endif /* STM32H7xx_HAL_OTFDEC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h index 723656611..27f7fdf6d 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -107,6 +106,7 @@ typedef struct uint32_t Setup[12]; /*!< Setup packet buffer */ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; + uint32_t FrameNumber; /*!< Store Current Frame number */ uint32_t lpm_active; /*!< Enable or disable the Link Power Management . @@ -194,16 +194,20 @@ typedef struct #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ + ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) + #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) +#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) -#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) - -#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK +#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK -#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \ + ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) @@ -270,12 +274,10 @@ typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgType * @} */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, - HAL_PCD_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, - HAL_PCD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback); @@ -297,14 +299,10 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, - pPCD_BcdCallbackTypeDef pCallback); - +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, - pPCD_LpmCallbackTypeDef pCallback); - +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /** @@ -343,22 +341,17 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, - uint16_t ep_mps, uint8_t ep_type); - +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, - uint8_t *pBuf, uint32_t len); - -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, - uint8_t *pBuf, uint32_t len); - - +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode); uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); /** @@ -401,27 +394,27 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #if defined (USB_OTG_FS) || defined (USB_OTG_HS) #ifndef USB_OTG_DOEPINT_OTEPSPR #define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */ -#endif +#endif /* defined USB_OTG_DOEPINT_OTEPSPR */ #ifndef USB_OTG_DOEPMSK_OTEPSPRM #define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */ -#endif +#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */ #ifndef USB_OTG_DOEPINT_NAK #define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */ -#endif +#endif /* defined USB_OTG_DOEPINT_NAK */ #ifndef USB_OTG_DOEPMSK_NAKM #define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */ -#endif +#endif /* defined USB_OTG_DOEPMSK_NAKM */ #ifndef USB_OTG_DOEPINT_STPKTRX #define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */ -#endif +#endif /* defined USB_OTG_DOEPINT_STPKTRX */ #ifndef USB_OTG_DOEPMSK_NYETM #define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */ -#endif +#endif /* defined USB_OTG_DOEPMSK_NYETM */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /* Private macros ------------------------------------------------------------*/ @@ -447,5 +440,3 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #endif #endif /* STM32H7xx_HAL_PCD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h index babeda775..9cfa0125e 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -23,7 +22,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* __cplusplus */ /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal_def.h" @@ -83,9 +82,7 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); #ifdef __cplusplus } -#endif +#endif /* __cplusplus */ #endif /* STM32H7xx_HAL_PCD_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pssi.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pssi.h index cd5023447..78d6fcc8b 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pssi.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pssi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -501,6 +500,3 @@ uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi); #endif #endif /* STM32H7xx_HAL_PSSI_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h index 9dbf404ae..91a905409 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -808,4 +807,3 @@ void HAL_PWR_DisableSEVOnPend (void); #endif /* STM32H7xx_HAL_PWR_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h index 12f557a17..61c76092c 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -788,4 +787,3 @@ void HAL_PWREx_AVDCallback (void); #endif /* STM32H7xx_HAL_PWR_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h index 4379cbe39..39eb5faa4 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -453,7 +452,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); * @{ */ /** @brief Reset QSPI handle state. - * @param __HANDLE__ : QSPI handle. + * @param __HANDLE__ QSPI handle. * @retval None */ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) @@ -467,20 +466,20 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #endif /** @brief Enable the QSPI peripheral. - * @param __HANDLE__ : specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Disable the QSPI peripheral. - * @param __HANDLE__ : specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Enable the specified QSPI interrupt. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -493,8 +492,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @brief Disable the specified QSPI interrupt. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -506,8 +505,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** @brief Check whether the specified QSPI interrupt source is enabled or not. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to check. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -520,8 +519,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** * @brief Check whether the selected QSPI flag is set or not. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __FLAG__ : specifies the QSPI flag to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI flag to check. * This parameter can be one of the following values: * @arg QSPI_FLAG_BUSY: QSPI Busy flag * @arg QSPI_FLAG_TO: QSPI Timeout flag @@ -534,8 +533,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) /** @brief Clears the specified QSPI's flag status. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI clear register flag that needs to be set * This parameter can be one of the following values: * @arg QSPI_FLAG_TO: QSPI Timeout flag * @arg QSPI_FLAG_SM: QSPI Status match flag @@ -736,12 +735,10 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint3 * @} */ -#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ +#endif /* defined(QUADSPI) */ #ifdef __cplusplus } #endif #endif /* STM32H7xx_HAL_QSPI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ramecc.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ramecc.h index 1046ca85e..c15ca58e4 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ramecc.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ramecc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -355,4 +354,3 @@ uint32_t HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc); #endif /* STM32H7xx_HAL_RAMECC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h index 6a589ee13..9b4eb6099 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -8265,4 +8263,3 @@ void HAL_RCC_CCSCallback(void); #endif /* STM32H7xx_HAL_RCC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h index a08e3dba5..590d48652 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -4475,4 +4473,3 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #endif /* STM32H7xx_HAL_RCC_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng.h index fc4de1ae8..ed7fe5e8d 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -392,4 +391,3 @@ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng); #endif /* STM32H7xx_HAL_RNG_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng_ex.h index 1f7fc848b..028f71e9b 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -35,19 +34,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNGEx RNGEx +/** @defgroup RNG_Ex RNG_Ex * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNGEx_Exported_Types RNGEx Exported Types - * @brief RNGEx Exported types +/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types + * @brief RNG_Ex Exported types * @{ */ /** - * @brief RNGEX Configuration Structure definition + * @brief RNG_Ex Configuration Structure definition */ typedef struct @@ -56,9 +55,9 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNGEX_Clock_Divider_Factor */ + be a value of @ref RNG_Ex_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNGEX_NIST_Compliance */ + value of @ref RNG_Ex_NIST_Compliance */ } RNG_ConfigTypeDef; /** @@ -66,11 +65,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNGEX_Exported_Constants RNGEX Exported Constants +/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants * @{ */ -/** @defgroup RNGEX_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -109,7 +108,7 @@ typedef struct * @} */ -/** @defgroup RNGEX_NIST_Compliance NIST Compliance configuration +/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -124,7 +123,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Types RNGEx Private Types +/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types * @{ */ @@ -133,7 +132,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Variables RNGEx Private Variables +/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables * @{ */ @@ -142,7 +141,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Constants RNGEx Private Constants +/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants * @{ */ @@ -151,7 +150,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Macros RNGEx Private Macros +/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros * @{ */ @@ -188,7 +187,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Functions RNGEx Private Functions +/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions * @{ */ @@ -197,11 +196,11 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions +/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions * @{ */ -/** @addtogroup RNGEx_Exported_Functions_Group1 +/** @addtogroup RNG_Ex_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf); @@ -212,7 +211,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNGEx_Exported_Functions_Group2 +/** @addtogroup RNG_Ex_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); @@ -245,6 +244,5 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); #endif -#endif /* STM32H7xx_HAL_RNGEX_H */ +#endif /* STM32H7xx_HAL_RNG_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h index 99c0dd1e9..9bebc965f 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -908,7 +907,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to */ #define __HAL_RTC_ALARM_EXTID2_DISABLE_EVENT() (EXTI_D2->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) -#endif +#endif /* DUAL_CORE */ /** * @brief Enable falling edge trigger on the RTC Alarm associated Exti line. * @retval None @@ -983,7 +982,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @retval None */ #define __HAL_RTC_ALARM_EXTID2_CLEAR_FLAG() (EXTI_D2->PR1 = (RTC_EXTI_LINE_ALARM_EVENT)) -#endif +#endif /* DUAL_CORE */ /** * @brief Generate a Software interrupt on RTC Alarm associated Exti line. * @retval None @@ -1239,4 +1238,3 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value); #endif /* STM32H7xx_HAL_RTC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h index 833ae6f9c..f5798de18 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -2090,4 +2089,3 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #endif /* STM32H7xx_HAL_RTC_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai.h index 7db7eb8a8..892daa2f1 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -984,4 +983,3 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #endif /* STM32H7xx_HAL_SAI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai_ex.h index d323c59c9..a946aeab0 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -102,4 +101,3 @@ HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_Pdm #endif /* STM32H7xx_HAL_SAI_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h index 83c97aba1..d465de6cc 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -298,7 +297,7 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup SD_Exported_Constants Exported Constants +/** @defgroup SD_Exported_Constants SD Exported Constants * @{ */ @@ -799,5 +798,3 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); #endif /* STM32H7xx_HAL_SD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h index 9c71954d9..450e7dfad 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -109,5 +108,3 @@ void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd); #endif /* stm32h7xx_HAL_SD_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h index ba189d439..cee1ffdd3 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -235,5 +234,3 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram); #endif #endif /* STM32H7xx_HAL_SDRAM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard.h index 1c7aee87e..3aaaa7de7 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -202,7 +201,7 @@ typedef struct __SMARTCARD_HandleTypeDef SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ @@ -1345,13 +1344,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma * @{ */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); /* Transfer Abort functions */ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard); @@ -1403,4 +1402,3 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmar #endif /* STM32H7xx_HAL_SMARTCARD_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard_ex.h index d6650a156..391000557 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -335,4 +334,3 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hs #endif /* STM32H7xx_HAL_SMARTCARD_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus.h index 426760dc6..25b9a0908 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -48,42 +47,43 @@ extern "C" { typedef struct { uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. - This parameter calculated by referring to SMBUS initialization - section in Reference manual */ + This parameter calculated by referring to SMBUS initialization section + in Reference manual */ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. - This parameter can be a value of @ref SMBUS_Analog_Filter */ + This parameter can be a value of @ref SMBUS_Analog_Filter */ uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ + This parameter can be a 7-bit or 10-bit address. */ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. - This parameter can be a value of @ref SMBUS_addressing_mode */ + This parameter can be a value of @ref SMBUS_addressing_mode */ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref SMBUS_dual_addressing_mode */ + This parameter can be a value of @ref SMBUS_dual_addressing_mode */ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ + This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref SMBUS_own_address2_masks. */ + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address + if dual addressing mode is selected + This parameter can be a value of @ref SMBUS_own_address2_masks. */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ + This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref SMBUS_nostretch_mode */ + This parameter can be a value of @ref SMBUS_nostretch_mode */ uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. - This parameter can be a value of @ref SMBUS_packet_error_check_mode */ + This parameter can be a value of @ref SMBUS_packet_error_check_mode */ uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. - This parameter can be a value of @ref SMBUS_peripheral_mode */ + This parameter can be a value of @ref SMBUS_peripheral_mode */ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. - (Enable bits and different timeout values) - This parameter calculated by referring to SMBUS initialization - section in Reference manual */ + (Enable bits and different timeout values) + This parameter calculated by referring to SMBUS initialization section + in Reference manual */ } SMBUS_InitTypeDef; /** * @} @@ -102,7 +102,7 @@ typedef struct #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ -#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ +#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} */ @@ -121,7 +121,7 @@ typedef struct #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ #define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ /** @@ -159,17 +159,26 @@ typedef struct __IO uint32_t ErrorCode; /*!< SMBUS Error code */ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */ - void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */ - void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */ - void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */ - void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */ - void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */ - - void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */ - - void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */ - void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */ + void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Listen Complete callback */ + void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Error callback */ + + void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< SMBUS Slave Address Match callback */ + + void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Msp Init callback */ + void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Msp DeInit callback */ #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } SMBUS_HandleTypeDef; @@ -195,8 +204,11 @@ typedef enum /** * @brief HAL SMBUS Callback pointer definition */ -typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */ -typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */ +typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); +/*!< pointer to an SMBUS callback function */ +typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an SMBUS Address Match callback function */ #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ /** @@ -358,9 +370,10 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE #define SMBUS_IT_RXI I2C_CR1_RXIE #define SMBUS_IT_TXI I2C_CR1_TXIE -#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | \ - SMBUS_IT_TXI) -#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) +#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \ + SMBUS_IT_NACKI | SMBUS_IT_TXI) +#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \ + SMBUS_IT_RXI) #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) /** @@ -408,14 +421,14 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @retval None */ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ +#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) -#endif +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ /** @brief Enable the specified SMBUS interrupts. * @param __HANDLE__ specifies the SMBUS Handle. @@ -491,12 +504,14 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t */ #define SMBUS_FLAG_MASK (0x0001FFFFU) #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ - (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) + (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ + ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the SMBUS Handle. * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: + * @arg @ref SMBUS_FLAG_TXE Transmit data register empty * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) * @arg @ref SMBUS_FLAG_AF NACK received flag * @arg @ref SMBUS_FLAG_STOPF STOP detection flag @@ -509,7 +524,9 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * * @retval None */ -#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) +#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified SMBUS peripheral. * @param __HANDLE__ specifies the SMBUS Handle. @@ -574,43 +591,52 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) -#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ - ((MODE) == SMBUS_AUTOEND_MODE) || \ - ((MODE) == SMBUS_SOFTEND_MODE) || \ - ((MODE) == SMBUS_SENDPEC_MODE) || \ - ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) +#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ + ((MODE) == SMBUS_AUTOEND_MODE) || \ + ((MODE) == SMBUS_SOFTEND_MODE) || \ + ((MODE) == SMBUS_SENDPEC_MODE) || \ + ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \ + SMBUS_RELOAD_MODE ))) #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ - ((REQUEST) == SMBUS_GENERATE_START_READ) || \ - ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ + ((REQUEST) == SMBUS_GENERATE_START_READ) || \ + ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ ((REQUEST) == SMBUS_NO_STARTSTOP)) -#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ - ((REQUEST) == SMBUS_FIRST_FRAME) || \ - ((REQUEST) == SMBUS_NEXT_FRAME) || \ - ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) +#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ + ((REQUEST) == SMBUS_FIRST_FRAME) || \ + ((REQUEST) == SMBUS_NEXT_FRAME) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) -#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ +#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) -#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ - (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) -#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ - (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) - -#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) +#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ + (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \ + I2C_CR1_PECEN))) +#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & \ + (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \ + (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) @@ -629,6 +655,9 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @} */ +/* Include SMBUS HAL Extended module */ +#include "stm32h7xx_hal_smbus_ex.h" + /* Exported functions --------------------------------------------------------*/ /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions * @{ @@ -648,11 +677,14 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID); -HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, + pSMBUS_AddrCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ /** @@ -678,10 +710,10 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t * @{ */ /******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); @@ -757,5 +789,3 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); #endif /* STM32H7xx_HAL_SMBUS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus_ex.h new file mode 100644 index 000000000..0fde99095 --- /dev/null +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus_ex.h @@ -0,0 +1,152 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_smbus_ex.h + * @author MCD Application Team + * @brief Header file of SMBUS HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_SMBUS_EX_H +#define STM32H7xx_HAL_SMBUS_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup SMBUSEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants + * @{ + */ + +/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus + * @{ + */ +#define SMBUS_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ +#define SMBUS_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define SMBUS_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define SMBUS_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define SMBUS_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#define SMBUS_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ +#if defined(SYSCFG_PMCR_I2C5_FMP) +#define SMBUS_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus on I2C5 pins */ +#else +#define SMBUS_FASTMODEPLUS_I2C5 (uint32_t)(0x00001000U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C5 not supported */ +#endif /* SYSCFG_PMCR_I2C5_FMP */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions + * @{ + */ + +/** @addtogroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus); +/** + * @} + */ + +/** @addtogroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @{ + */ +void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros + * @{ + */ +#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & SMBUS_FASTMODEPLUS_PB6) == SMBUS_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PB7) == SMBUS_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PB8) == SMBUS_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_PB9) == SMBUS_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_I2C1) == SMBUS_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_I2C2) == SMBUS_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_I2C3) == SMBUS_FASTMODEPLUS_I2C3) || \ + (((__CONFIG__) & SMBUS_FASTMODEPLUS_I2C4) == SMBUS_FASTMODEPLUS_I2C4)) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32h7xx_hal_smbus_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_SMBUS_EX_H */ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spdifrx.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spdifrx.h index 66176ec24..99d17c4c2 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spdifrx.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spdifrx.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -22,7 +21,7 @@ #define STM32H7xx_HAL_SPDIFRX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -129,7 +128,7 @@ typedef enum typedef struct __SPDIFRX_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ { SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */ @@ -173,8 +172,8 @@ typedef struct void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed callback */ void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow completed callback */ void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX error callback */ - void (* MspInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif); /*!< SPDIFRX Msp Init callback */ - void (* MspDeInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif); /*!< SPDIFRX Msp DeInit callback */ + void (* MspInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp Init callback */ + void (* MspDeInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp DeInit callback */ #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ } SPDIFRX_HandleTypeDef; @@ -195,12 +194,12 @@ typedef enum HAL_SPDIFRX_ERROR_CB_ID = 0x04U, /*!< SPDIFRX error callback */ HAL_SPDIFRX_MSPINIT_CB_ID = 0x05U, /*!< SPDIFRX Msp Init callback ID */ HAL_SPDIFRX_MSPDEINIT_CB_ID = 0x06U /*!< SPDIFRX Msp DeInit callback ID */ -}HAL_SPDIFRX_CallbackIDTypeDef; +} HAL_SPDIFRX_CallbackIDTypeDef; /** * @brief HAL SPDIFRX Callback pointer definition */ -typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< pointer to an SPDIFRX callback function */ +typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback function */ #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ /* Exported constants --------------------------------------------------------*/ @@ -273,8 +272,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< */ /** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask -* @{ -*/ + * @{ + */ #define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U) #define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK) /** @@ -374,10 +373,10 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< */ #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) do{\ - (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\ - (__HANDLE__)->MspInitCallback = NULL;\ - (__HANDLE__)->MspDeInitCallback = NULL;\ - }while(0) + (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL;\ + (__HANDLE__)->MspDeInitCallback = NULL;\ + }while(0) #else #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET) #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ @@ -416,7 +415,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< * @retval None */ #define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) -#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__))) +#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR\ + &= (uint16_t)(~(__INTERRUPT__))) /** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled. * @param __HANDLE__ specifies the SPDIFRX Handle. @@ -431,7 +431,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< * @arg SPDIFRX_IT_IFEIE * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks whether the specified SPDIFRX flag is set or not. * @param __HANDLE__ specifies the SPDIFRX Handle. @@ -448,7 +449,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< * @arg SPDIFRX_FLAG_TERR * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) +#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\ + & (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit. * @param __HANDLE__ specifies the USART Handle. @@ -477,15 +479,17 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< */ /* Initialization/de-initialization functions **********************************/ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif); -HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif); +HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif); void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif); void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif); HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, + pSPDIFRX_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, + HAL_SPDIFRX_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ /** * @} @@ -495,9 +499,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, * @{ */ /* I/O operation functions ***************************************************/ - /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); @@ -523,8 +529,8 @@ void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif); * @{ */ /* Peripheral Control and State functions ************************************/ -HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * const hspdif); -uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif); +HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif); +uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif); /** * @} */ @@ -540,39 +546,39 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif); * @{ */ #define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \ - ((INPUT) == SPDIFRX_INPUT_IN2) || \ - ((INPUT) == SPDIFRX_INPUT_IN3) || \ - ((INPUT) == SPDIFRX_INPUT_IN0)) + ((INPUT) == SPDIFRX_INPUT_IN2) || \ + ((INPUT) == SPDIFRX_INPUT_IN3) || \ + ((INPUT) == SPDIFRX_INPUT_IN0)) #define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \ - ((RET) == SPDIFRX_MAXRETRIES_3) || \ - ((RET) == SPDIFRX_MAXRETRIES_15) || \ - ((RET) == SPDIFRX_MAXRETRIES_63)) + ((RET) == SPDIFRX_MAXRETRIES_3) || \ + ((RET) == SPDIFRX_MAXRETRIES_15) || \ + ((RET) == SPDIFRX_MAXRETRIES_63)) #define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \ - ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF)) + ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF)) #define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \ - ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF)) + ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF)) #define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \ - ((VAL) == SPDIFRX_VALIDITYMASK_ON)) + ((VAL) == SPDIFRX_VALIDITYMASK_ON)) #define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \ - ((VAL) == SPDIFRX_PARITYERRORMASK_ON)) + ((VAL) == SPDIFRX_PARITYERRORMASK_ON)) #define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \ - ((CHANNEL) == SPDIFRX_CHANNEL_B)) + ((CHANNEL) == SPDIFRX_CHANNEL_B)) #define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \ - ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \ - ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS)) + ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \ + ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS)) #define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \ - ((MODE) == SPDIFRX_STEREOMODE_ENABLE)) + ((MODE) == SPDIFRX_STEREOMODE_ENABLE)) #define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \ - ((VAL) == SPDIFRX_CHANNELSTATUS_OFF)) + ((VAL) == SPDIFRX_CHANNELSTATUS_OFF)) #define IS_SYMBOL_CLOCK_GEN(VAL) (((VAL) == ENABLE) || ((VAL) == DISABLE)) /** @@ -601,6 +607,4 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif); #endif -#endif /* __STM32H7xx_HAL_SPDIFRX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32H7xx_HAL_SPDIFRX_H */ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h index fb4e2c5e5..b53b0b466 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -63,7 +62,8 @@ typedef struct uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_Management */ + This parameter can be a value of + @ref SPI_Slave_Select_Management */ uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. @@ -81,40 +81,45 @@ typedef struct This parameter can be a value of @ref SPI_CRC_Calculation */ uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. - This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */ + This parameter must be an odd number between + Min_Data = 0 and Max_Data = 65535 */ uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. This parameter can be a value of @ref SPI_CRC_length */ uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . This parameter can be a value of @ref SPI_NSSP_Mode - This mode is activated by the SSOM bit in the SPIx_CR2 register and - it takes effect only if the SPI interface is configured as Motorola SPI - master (FRF=0). */ + This mode is activated by the SSOM bit in the SPIx_CR2 register + and it takes effect only if the SPI interface is configured + as Motorola SPI master (FRF=0). */ - uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal (present on SS pin) is - considered as active one. + uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal + (present on SS pin) is considered as active one. This parameter can be a value of @ref SPI_NSS_Polarity */ uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level. This parameter can be a value of @ref SPI_Fifo_Threshold */ - uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for the CRC calculation. - This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */ + uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for + the CRC calculation. This parameter can be a value of + @ref SPI_CRC_Calculation_Initialization_Pattern */ - uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for the CRC calculation. - This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */ + uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for + the CRC calculation. This parameter can be a value of + @ref SPI_CRC_Calculation_Initialization_Pattern */ - uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted - additionally between active edge of SS and first data transaction start in master mode. + uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle + periods, inserted additionally between active edge of SS + and first data transaction start in master mode. This parameter can be a value of @ref SPI_Master_SS_Idleness */ - uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between - two consecutive data frames in master mode - This parameter can be a value of @ref SPI_Master_InterData_Idleness */ + uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) + inserted between two consecutive data frames in master mode. + This parameter can be a value of + @ref SPI_Master_InterData_Idleness */ - uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode and automatic management - in order to avoid overrun condition. + uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode + and automatic management in order to avoid overrun condition. This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/ uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state @@ -122,7 +127,6 @@ typedef struct uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions This parameter can be a value of @ref SPI_IO_Swap */ - } SPI_InitTypeDef; /** @@ -157,7 +161,7 @@ typedef struct uint32_t Requested; /*!< SPI reload request */ } SPI_ReloadTypeDef; -#endif /* USE_HSPI_RELOAD_TRANSFER */ +#endif /* USE_SPI_RELOAD_TRANSFER */ /** * @brief SPI handle Structure definition @@ -195,12 +199,12 @@ typedef struct __SPI_HandleTypeDef __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ __IO uint32_t ErrorCode; /*!< SPI Error code */ - + #if defined(USE_SPI_RELOAD_TRANSFER) SPI_ReloadTypeDef Reload; /*!< SPI reload parameters */ - -#endif /* USE_HSPI_RELOAD_TRANSFER */ + +#endif /* USE_SPI_RELOAD_TRANSFER */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ @@ -270,14 +274,15 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to #define HAL_SPI_ERROR_OVR (0x00000004UL) /*!< OVR error */ #define HAL_SPI_ERROR_FRE (0x00000008UL) /*!< FRE error */ #define HAL_SPI_ERROR_DMA (0x00000010UL) /*!< DMA transfer error */ -#define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ +#define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXP/TXP/DXP/FTLVL/FRLVL Flag */ #define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */ #define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */ #define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */ -#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknown error */ +#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknown error */ #define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */ +#define HAL_SPI_ERROR_RELOAD (0x00000800UL) /*!< Reload error */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) -#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000800UL) /*!< Invalid Callback error */ +#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00001000UL) /*!< Invalid Callback error */ #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** * @} @@ -569,22 +574,22 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @} */ -/** @defgroup SPI_Underrun_Detection SPI Underrun Detection +/** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior * @{ */ -#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL) -#define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0 -#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1 +#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL) +#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0 +#define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1 /** * @} */ -/** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior +/** @defgroup SPI_Underrun_Detection SPI Underrun Detection * @{ */ -#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL) -#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0 -#define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1 +#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL) +#define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0 +#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1 /** * @} */ @@ -633,10 +638,10 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level * @{ */ -#define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */ -#define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) -#define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) -#define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) +#define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */ +#define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) +#define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) +#define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) /** * @} */ @@ -663,7 +668,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to } while(0) #else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) -#endif +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** @brief Enable the specified SPI interrupts. * @param __HANDLE__: specifies the SPI Handle. @@ -726,7 +731,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @arg SPI_IT_ERR : Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SPI flag is set or not. * @param __HANDLE__: specifies the SPI Handle. @@ -842,7 +848,8 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** @@ -859,17 +866,20 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); #if defined(USE_SPI_RELOAD_TRANSFER) HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -#endif /* USE_HSPI_RELOAD_TRANSFER */ +HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, + uint8_t *pRxData, uint16_t Size); +#endif /* USE_SPI_RELOAD_TRANSFER */ HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); @@ -936,15 +946,13 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) -#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) ( \ - ((MODE) == SPI_DIRECTION_2LINES)|| \ - ((MODE) == SPI_DIRECTION_1LINE) || \ - ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) +#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ + ((MODE) == SPI_DIRECTION_1LINE) || \ + ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) -#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) ( \ - ((MODE) == SPI_DIRECTION_2LINES)|| \ - ((MODE) == SPI_DIRECTION_1LINE) || \ - ((MODE) == SPI_DIRECTION_2LINES_RXONLY)) +#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ + ((MODE) == SPI_DIRECTION_1LINE) || \ + ((MODE) == SPI_DIRECTION_2LINES_RXONLY)) #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \ ((DATASIZE) == SPI_DATASIZE_31BIT) || \ @@ -1059,7 +1067,8 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \ ((LENGTH) == SPI_CRC_LENGTH_4BIT)) -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1UL) +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL) + #define IS_SPI_UNDERRUN_DETECTION(MODE) (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \ ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME) || \ @@ -1068,6 +1077,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \ ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED) || \ ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED)) + /** * @} */ @@ -1089,4 +1099,3 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi_ex.h index c9c579e60..9e583faef 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -37,8 +36,32 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ +/** @defgroup SPIEx_Exported_Types SPIEx Exported Types + * @{ + */ + +/** + * @} + */ + /* Exported constants --------------------------------------------------------*/ +/** @defgroup SPIEx_Exported_Constants SPIEx Exported Constants + * @{ + */ + +/** + * @} + */ + /* Exported macros -----------------------------------------------------------*/ +/** @defgroup SPIEx_Exported_Macros SPIEx Extended Exported Macros + * @{ + */ + +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup SPIEx_Exported_Functions * @{ @@ -51,11 +74,11 @@ extern "C" { */ HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour); +HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, + uint32_t UnderrunBehaviour); /** * @} */ - /** * @} */ @@ -68,10 +91,9 @@ HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t * @} */ + #ifdef __cplusplus } #endif #endif /* STM32H7xx_HAL_SPI_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sram.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sram.h index 6384026da..4c17a6a71 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sram.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sram.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -229,5 +228,3 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); #endif #endif /* STM32H7xx_HAL_SRAM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_swpmi.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_swpmi.h index f41ac106b..4180c713c 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_swpmi.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_swpmi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -22,7 +21,7 @@ #define STM32H7xx_HAL_SWPMI_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -62,7 +61,7 @@ typedef struct uint32_t RxBufferingMode; /*!< Specifies the reception buffering mode. This parameter can be a value of @ref SWPMI_Rx_Buffering_Mode */ -}SWPMI_InitTypeDef; +} SWPMI_InitTypeDef; /** @@ -78,7 +77,7 @@ typedef enum HAL_SWPMI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ HAL_SWPMI_STATE_TIMEOUT = 0x03, /*!< Timeout state */ HAL_SWPMI_STATE_ERROR = 0x04 /*!< Error */ -}HAL_SWPMI_StateTypeDef; +} HAL_SWPMI_StateTypeDef; /** * @brief SWPMI handle Structure definition @@ -116,16 +115,16 @@ typedef struct __IO uint32_t ErrorCode; /*!< SWPMI Error code */ #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) - void (*RxCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive complete callback */ - void (*RxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive half complete callback */ - void (*TxCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit complete callback */ - void (*TxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit half complete callback */ - void (*ErrorCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI error callback */ - void (*MspInitCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP init callback */ - void (*MspDeInitCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP de-init callback */ + void (*RxCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive complete callback */ + void (*RxHalfCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive half complete callback */ + void (*TxCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit complete callback */ + void (*TxHalfCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit half complete callback */ + void (*ErrorCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI error callback */ + void (*MspInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP init callback */ + void (*MspDeInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP de-init callback */ #endif -}SWPMI_HandleTypeDef; +} SWPMI_HandleTypeDef; #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) /** @@ -140,7 +139,7 @@ typedef enum HAL_SWPMI_ERROR_CB_ID = 0x04U, /*!< SWPMI error callback ID */ HAL_SWPMI_MSPINIT_CB_ID = 0x05U, /*!< SWPMI MSP init callback ID */ HAL_SWPMI_MSPDEINIT_CB_ID = 0x06U /*!< SWPMI MSP de-init callback ID */ -}HAL_SWPMI_CallbackIDTypeDef; +} HAL_SWPMI_CallbackIDTypeDef; /** * @brief SWPMI callback pointer definition @@ -298,7 +297,7 @@ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); /** @brief Check whether the specified SWPMI flag is set or not. * @param __HANDLE__ specifies the SWPMI Handle. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SWPMI_FLAG_RXBFF Receive buffer full flag. * @arg SWPMI_FLAG_TXBEF Transmit buffer empty flag. @@ -318,7 +317,7 @@ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); /** @brief Clear the specified SWPMI ISR flag. * @param __HANDLE__ specifies the SWPMI Handle. - * @param __FLAG__: specifies the flag to clear. + * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg SWPMI_FLAG_RXBFF Receive buffer full flag. * @arg SWPMI_FLAG_TXBEF Transmit buffer empty flag. @@ -516,5 +515,3 @@ uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi); #endif #endif /* STM32H7xx_HAL_SWPMI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h index 2e93e31a6..157cc9c2e 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -65,8 +64,10 @@ typedef struct This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. This parameter can be a value of @ref TIM_AutoReloadPreload */ @@ -218,7 +219,8 @@ typedef struct uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity This parameter can be a value of @ref TIM_ClearInput_Polarity */ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ uint32_t ClearInputFilter; /*!< TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClearInputConfigTypeDef; @@ -268,28 +270,36 @@ typedef struct */ typedef struct { - uint32_t OffStateRunMode; /*!< TIM off state in run mode - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - uint32_t LockLevel; /*!< TIM Lock level - This parameter can be a value of @ref TIM_Lock_level */ - uint32_t DeadTime; /*!< TIM dead Time - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint32_t BreakState; /*!< TIM Break State - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - uint32_t BreakPolarity; /*!< TIM Break input polarity - This parameter can be a value of @ref TIM_Break_Polarity */ - uint32_t BreakFilter; /*!< Specifies the break input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Break2State; /*!< TIM Break2 State - This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ - uint32_t Break2Polarity; /*!< TIM Break2 input polarity - This parameter can be a value of @ref TIM_Break2_Polarity */ - uint32_t Break2Filter; /*!< TIM break2 input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +#if defined(TIM_BDTR_BKBID) + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ + +#endif /* TIM_BDTR_BKBID */ + uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + + uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ + + uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +#if defined(TIM_BDTR_BKBID) + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ + +#endif /* TIM_BDTR_BKBID */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + } TIM_BreakDeadTimeConfigTypeDef; /** @@ -660,10 +670,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ -#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ /** * @} @@ -737,6 +745,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_CC_DMA_Request CCx DMA request selection + * @{ + */ +#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ +#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + /** @defgroup TIM_Flag_definition TIM Flag Definition * @{ */ @@ -777,16 +794,16 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ -#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ -#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ -#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ -#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ -#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ #define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ #define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */ #define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */ @@ -884,6 +901,17 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** * @} */ +#if defined(TIM_BDTR_BKBID) + +/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ +#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ +/** + * @} + */ +#endif /*TIM_BDTR_BKBID */ /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable * @{ @@ -902,24 +930,34 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** * @} */ +#if defined(TIM_BDTR_BKBID) + +/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ +#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ +/** + * @} + */ +#endif /* TIM_BDTR_BKBID */ /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable * @{ */ #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ -#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event - (if none of the break inputs BRK and BRK2 is active) */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ /** * @} */ -/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 +/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 * @{ */ -#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ -#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ -#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ -#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ +#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ /** * @} */ @@ -1012,10 +1050,6 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ -#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ -#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ -#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ -#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ #define TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) */ #define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */ #define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */ @@ -1026,6 +1060,10 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */ #define TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) */ #define TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ /** * @} @@ -1218,7 +1256,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @brief Disable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None - * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ do { \ @@ -1385,7 +1424,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). - * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. * @param __HANDLE__ TIM handle. * @retval None mode. @@ -1412,8 +1452,8 @@ mode. * @brief Indicates whether or not the TIM Counter is used as downcounter. * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) - * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder -mode. + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. */ #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) @@ -1427,7 +1467,8 @@ mode. /** * @brief Set the TIM Counter Register value on runtime. - * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in + * case of 32 bits counter TIM instance. * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. * @param __HANDLE__ TIM handle. * @param __COUNTER__ specifies the Counter register new value. @@ -1489,7 +1530,8 @@ mode. #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** - * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: @@ -1711,6 +1753,17 @@ mode. TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ }while(0) +/** @brief Select the Capture/compare DMA request source. + * @param __HANDLE__ specifies the TIM Handle. + * @param __CCDMA__ specifies Capture/compare DMA request source + * This parameter can be one of the following values: + * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event + * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event + * @retval None + */ +#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ + MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) + /** * @} */ @@ -1836,15 +1889,15 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3)) #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ @@ -1888,12 +1941,24 @@ mode. #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) +#if defined(TIM_BDTR_BKBID) + +#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) + +#endif /* TIM_BDTR_BKBID */ #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ ((__STATE__) == TIM_BREAK2_DISABLE)) #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) +#if defined(TIM_BDTR_BKBID) + +#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) + +#endif /* TIM_BDTR_BKBID */ #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) @@ -1953,31 +2018,31 @@ mode. ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) -#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR12) || \ + ((__SELECTION__) == TIM_TS_ITR13) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ETRF) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR12) || \ - ((__SELECTION__) == TIM_TS_ITR13)) - -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ ((__SELECTION__) == TIM_TS_ITR12) || \ ((__SELECTION__) == TIM_TS_ITR13) || \ ((__SELECTION__) == TIM_TS_NONE)) @@ -2072,13 +2137,19 @@ mode. ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ - } while(0) + (__HANDLE__)->ChannelState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = \ + (__CHANNEL_STATE__); \ + } while(0) #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ @@ -2093,11 +2164,15 @@ mode. ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ - } while(0) + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ + } while(0) /** * @} @@ -2271,14 +2346,14 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_Sla HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, - uint32_t DataLength); + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, - uint32_t DataLength); + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); @@ -2376,5 +2451,3 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim); #endif #endif /* STM32H7xx_HAL_TIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h index 6d15c05e8..026d01d90 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -73,8 +72,7 @@ typedef struct uint32_t Polarity; /*!< Specifies the break input source polarity. This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity Not relevant when analog watchdog output of the DFSDM1 used as break input source */ -} -TIMEx_BreakInputConfigTypeDef; +} TIMEx_BreakInputConfigTypeDef; #endif /* TIM_BREAK_INPUT_SUPPORT */ /** @@ -143,8 +141,8 @@ TIMEx_BreakInputConfigTypeDef; /** @defgroup TIMEx_Break_Input TIM Extended Break input * @{ */ -#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */ -#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */ +#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ +#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ /** * @} */ @@ -163,8 +161,8 @@ TIMEx_BreakInputConfigTypeDef; /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling * @{ */ -#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */ -#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */ +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */ /** * @} */ @@ -172,8 +170,8 @@ TIMEx_BreakInputConfigTypeDef; /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity * @{ */ -#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */ -#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */ +#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */ +#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */ /** * @} */ @@ -468,6 +466,11 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t B HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); +#if defined(TIM_BDTR_BKBID) + +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +#endif /* TIM_BDTR_BKBID */ /** * @} */ @@ -502,7 +505,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ -/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions +/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions * @{ */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); @@ -526,5 +529,3 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); #endif /* STM32H7xx_HAL_TIM_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h index 103cb1b33..b20dec243 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -217,7 +216,7 @@ typedef struct __UART_HandleTypeDef UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ uint16_t TxXferSize; /*!< UART Tx Transfer size */ @@ -1141,10 +1140,10 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ } while(0U) /** @brief Disable CTS flow control. @@ -1160,10 +1159,10 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ } while(0U) /** @brief Enable RTS flow control. @@ -1179,10 +1178,10 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ } while(0U) /** @brief Disable RTS flow control. @@ -1198,10 +1197,10 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ } while(0U) /** * @} @@ -1612,11 +1611,11 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); @@ -1707,8 +1706,6 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa /* Prescaler Table used in BRR computation macros. Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ extern const uint16_t UARTPrescTable[12]; - - /** * @} */ @@ -1727,4 +1724,3 @@ extern const uint16_t UARTPrescTable[12]; #endif /* STM32H7xx_HAL_UART_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h index eb437f3b0..b60f9547c 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -867,4 +866,3 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ #endif /* STM32H7xx_HAL_UART_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h index 6092ebe31..7afa3c105 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -127,7 +126,7 @@ typedef struct __USART_HandleTypeDef USART_InitTypeDef Init; /*!< USART communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ uint16_t TxXferSize; /*!< USART Tx Transfer size */ @@ -1113,17 +1112,18 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); @@ -1175,4 +1175,3 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); #endif /* STM32H7xx_HAL_USART_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart_ex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart_ex.h index 769132696..4cf7061f6 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart_ex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -281,4 +280,3 @@ HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, ui #endif /* STM32H7xx_HAL_USART_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_wwdg.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_wwdg.h index 061a62fc4..8f2e4dc19 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_wwdg.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_wwdg.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -192,7 +191,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer t /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__: WWDG handle + * @param __HANDLE__ WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt @@ -305,5 +304,3 @@ void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg); #endif #endif /* STM32H7xx_HAL_WWDG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h index f12b52a70..b6f949f82 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1141,8 +1140,10 @@ typedef struct #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */ +#if defined(HRTIM1) #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */ +#endif /* HRTIM1 */ #define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */ #define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ @@ -2738,6 +2739,65 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCx return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); } +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Add paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n + * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n + * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + SET_BIT(ADCxy_COMMON->CCR, PathInternal); +} + +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Remove paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n + * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n + * CCR VBATEN LL_ADC_SetCommonPathInternalChRem + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal); +} + /** * @} */ @@ -2927,7 +2987,7 @@ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution #elif defined(ADC_VER_V5_V90) if (ADCx == ADC3) { - MODIFY_REG(ADCx->CFGR, ADC3_CFGR_RES, (((Resolution & 0x10UL) | 0x08UL | (Resolution & 0x04UL)) & 0x00000018UL)); + MODIFY_REG(ADCx->CFGR, ADC3_CFGR_RES, ((__LL_ADC12_RESOLUTION_TO_ADC3(Resolution) & (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) << 1UL)); } else { @@ -8214,4 +8274,3 @@ void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); #endif /* STM32H7xx_LL_ADC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h index 36910f277..996eb750e 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1817,6 +1816,10 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(BDMA_TypeDef *BDMAx) /** * @brief Clear Channel 0 global interrupt flag. + * @note Do not Clear Channel 0 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC0, LL_DMA_ClearFlag_HT0, + LL_DMA_ClearFlag_TE0. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF0 LL_BDMA_ClearFlag_GI0 * @param BDMAx BDMA Instance * @retval None @@ -1828,6 +1831,10 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_GI0(BDMA_TypeDef *BDMAx) /** * @brief Clear Channel 1 global interrupt flag. + * @note Do not Clear Channel 1 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1, + LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF1 LL_BDMA_ClearFlag_GI1 * @param BDMAx BDMA Instance * @retval None @@ -1839,6 +1846,10 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_GI1(BDMA_TypeDef *BDMAx) /** * @brief Clear Channel 2 global interrupt flag. + * @note Do not Clear Channel 2 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2, + LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF2 LL_BDMA_ClearFlag_GI2 * @param BDMAx BDMA Instance * @retval None @@ -1850,6 +1861,10 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_GI2(BDMA_TypeDef *BDMAx) /** * @brief Clear Channel 3 global interrupt flag. + * @note Do not Clear Channel 3 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3, + LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF3 LL_BDMA_ClearFlag_GI3 * @param BDMAx BDMA Instance * @retval None @@ -1861,6 +1876,10 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_GI3(BDMA_TypeDef *BDMAx) /** * @brief Clear Channel 4 global interrupt flag. + * @note Do not Clear Channel 4 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4, + LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF4 LL_BDMA_ClearFlag_GI4 * @param BDMAx BDMA Instance * @retval None @@ -1872,6 +1891,10 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_GI4(BDMA_TypeDef *BDMAx) /** * @brief Clear Channel 5 global interrupt flag. + * @note Do not Clear Channel 5 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5, + LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF5 LL_BDMA_ClearFlag_GI5 * @param BDMAx BDMA Instance * @retval None @@ -1883,6 +1906,10 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_GI5(BDMA_TypeDef *BDMAx) /** * @brief Clear Channel 6 global interrupt flag. + * @note Do not Clear Channel 6 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6, + LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF6 LL_BDMA_ClearFlag_GI6 * @param BDMAx BDMA Instance * @retval None @@ -1894,6 +1921,10 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_GI6(BDMA_TypeDef *BDMAx) /** * @brief Clear Channel 7 global interrupt flag. + * @note Do not Clear Channel 7 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7, + LL_DMA_ClearFlag_TE7. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF7 LL_BDMA_ClearFlag_GI7 * @param BDMAx BDMA Instance * @retval None @@ -2417,4 +2448,3 @@ void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct); #endif /* STM32H7xx_LL_BDMA_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h index 022cf6d23..89824845d 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32h7xx_ll_bus.h * @author MCD Application Team - * @version $VERSION$ - * @date $DATE$ * @brief Header file of BUS LL module. @verbatim @@ -25,14 +23,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -848,6 +844,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n * AHB1ENR ADC12EN LL_AHB1_GRP1_EnableClock\n * AHB1ENR ARTEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n (*) * AHB1ENR ETH1MACEN LL_AHB1_GRP1_EnableClock\n (*) * AHB1ENR ETH1TXEN LL_AHB1_GRP1_EnableClock\n (*) * AHB1ENR ETH1RXEN LL_AHB1_GRP1_EnableClock\n (*) @@ -860,6 +857,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) @@ -922,6 +920,7 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n * AHB1ENR ADC12EN LL_AHB1_GRP1_DisableClock\n * AHB1ENR ARTEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n (*) * AHB1ENR ETH1MACEN LL_AHB1_GRP1_DisableClock\n (*) * AHB1ENR ETH1TXEN LL_AHB1_GRP1_DisableClock\n (*) * AHB1ENR ETH1RXEN LL_AHB1_GRP1_DisableClock\n (*) @@ -6830,4 +6829,4 @@ __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs) #endif /* STM32H7xx_LL_BUS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_comp.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_comp.h index beedbac03..5d1a7f3fe 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_comp.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_comp.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -848,4 +847,4 @@ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct); #endif /* __STM32H7xx_LL_COMP_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h index 848a5dcf8..b798e7bf0 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -242,13 +241,13 @@ extern "C" { * - @ref LL_CORDIC_SetNbRead() * - @ref LL_CORDIC_SetInSize() * - @ref LL_CORDIC_SetOutSize() - * @rmtoll CSR FUNC LL_CORDIC_Configure\n - * CSR PRECISION LL_CORDIC_Configure\n - * CSR SCALE LL_CORDIC_Configure\n - * CSR NARGS LL_CORDIC_Configure\n - * CSR NRES LL_CORDIC_Configure\n - * CSR ARGSIZE LL_CORDIC_Configure\n - * CSR RESIZE LL_CORDIC_Configure + * @rmtoll CSR FUNC LL_CORDIC_Config\n + * CSR PRECISION LL_CORDIC_Config\n + * CSR SCALE LL_CORDIC_Config\n + * CSR NARGS LL_CORDIC_Config\n + * CSR NRES LL_CORDIC_Config\n + * CSR ARGSIZE LL_CORDIC_Config\n + * CSR RESIZE LL_CORDIC_Config * @param CORDICx CORDIC instance * @param Function parameter can be one of the following values: * @arg @ref LL_CORDIC_FUNCTION_COSINE @@ -782,5 +781,3 @@ ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx); #endif #endif /* STM32H7xx_LL_CORDIC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h index 4313732b7..4917f6515 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h @@ -10,7 +10,7 @@ [..] The LL CORTEX driver contains a set of generic APIs that can be used by user: - (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick + (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick functions (+) Low power mode configuration (SCB register of Cortex-MCU) (+) MPU API to configure and enable regions @@ -21,13 +21,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -666,4 +665,3 @@ __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) #endif /* STM32H7xx_LL_CORTEX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crc.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crc.h index d55593f3c..6c6de8f7c 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crc.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -236,7 +235,7 @@ __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t } /** - * @brief Configure the reversal of the bit order of the Output data + * @brief Return type of reversal of the bit order of the Output data * @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode * @param CRCx CRC Instance * @retval Returned value can be one of the following values: @@ -460,5 +459,3 @@ ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); #endif #endif /* STM32H7xx_LL_CRC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h index 85e0fe7c8..86ce84783 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -779,5 +778,3 @@ ErrorStatus LL_CRS_DeInit(void); #endif #endif /* STM32H7xx_LL_CRS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dac.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dac.h index d0c74210b..f4a2efdca 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dac.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dac.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -68,12 +67,14 @@ extern "C" { DHR12Rx channel 1 (shifted left of 20 bits) */ #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ + #define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */ #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ + #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL @@ -81,9 +82,11 @@ extern "C" { | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */ + #define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */ #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) + #define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */ #define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */ @@ -229,6 +232,7 @@ typedef struct #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ #define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */ #define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */ + /** * @} */ @@ -238,7 +242,9 @@ typedef struct * @{ */ #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ + #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ + /** * @} */ @@ -1644,6 +1650,7 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management * @{ */ + /** * @brief Get DAC calibration offset flag for DAC channel 1 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1 @@ -1679,7 +1686,6 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx) return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL); } - /** * @brief Get DAC busy writing sample time flag for DAC channel 2 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2 @@ -1858,4 +1864,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); #endif /* STM32H7xx_LL_DAC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h index 78b7bb163..b805ea26e 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h @@ -6,16 +6,15 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32H7xx_LL_DLYB_H @@ -85,4 +84,3 @@ HAL_StatusTypeDef DelayBlock_Configure(DLYB_TypeDef *DLYBx, uint32_t PhaseSel, u #endif /* STM32H7xx_LL_DLYB_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h index 5dae9e13d..4d18318bd 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -3281,4 +3280,3 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); #endif /* __STM32H7xx_LL_DMA_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma2d.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma2d.h index 583a04ea2..daea47584 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma2d.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma2d.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -2230,5 +2229,3 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb #endif #endif /* STM32H7xx_LL_DMA2D_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h index 9592307d5..bf4cffa0b 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -2435,4 +2434,3 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMU #endif /* __STM32H7xx_LL_DMAMUX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h index 1e25e0109..885f22d9f 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -3284,4 +3283,3 @@ void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); #endif /* __STM32H7xx_LL_EXTI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmac.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmac.h index 4bc018c33..b489388db 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmac.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmac.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -38,20 +37,6 @@ extern "C" { * @{ */ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup FMAC_LL_Private_Macros FMAC Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ @@ -63,11 +48,11 @@ extern "C" { * @brief Flag defines which can be used with LL_FMAC_ReadReg function * @{ */ -#define LL_FMAC_SR_SAT FMAC_SR_SAT -#define LL_FMAC_SR_UNFL FMAC_SR_UNFL -#define LL_FMAC_SR_OVFL FMAC_SR_OVFL -#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL -#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY +#define LL_FMAC_SR_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */ +#define LL_FMAC_SR_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */ +#define LL_FMAC_SR_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */ +#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */ +#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */ /** * @} */ @@ -76,11 +61,11 @@ extern "C" { * @brief IT defines which can be used with LL_FMAC_ReadReg and LL_FMAC_WriteReg functions * @{ */ -#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN -#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN -#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN -#define LL_FMAC_CR_WIEN FMAC_CR_WIEN -#define LL_FMAC_CR_RIEN FMAC_CR_RIEN +#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */ +#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */ +#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */ +#define LL_FMAC_CR_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */ +#define LL_FMAC_CR_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */ /** * @} */ @@ -89,10 +74,10 @@ extern "C" { * @brief Watermark defines that can be used for buffer full (input) or buffer empty (output) * @{ */ -#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000UL /*!< Buffer full/empty flag set if there is less than 1 free/unread space. */ -#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000UL /*!< Buffer full/empty flag set if there are less than 2 free/unread spaces. */ -#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000UL /*!< Buffer full/empty flag set if there are less than 4 free/unread spaces. */ -#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000UL /*!< Buffer full/empty flag set if there are less than 8 free/empty spaces. */ +#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000U /*!< Buffer full/empty flag set if there is less than 1 free/unread space. */ +#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000U /*!< Buffer full/empty flag set if there are less than 2 free/unread spaces. */ +#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000U /*!< Buffer full/empty flag set if there are less than 4 free/unread spaces. */ +#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000U /*!< Buffer full/empty flag set if there are less than 8 free/empty spaces. */ /** * @} */ @@ -100,20 +85,30 @@ extern "C" { /** @defgroup FMAC_LL_EC_FUNC FMAC functions * @{ */ -#define LL_FMAC_FUNC_LOAD_X1 ((uint32_t)(FMAC_PARAM_FUNC_0)) /*!< Load X1 buffer */ -#define LL_FMAC_FUNC_LOAD_X2 ((uint32_t)(FMAC_PARAM_FUNC_1)) /*!< Load X2 buffer */ -#define LL_FMAC_FUNC_LOAD_Y ((uint32_t)(FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)) /*!< Load Y buffer */ -#define LL_FMAC_FUNC_CONVO_FIR ((uint32_t)(FMAC_PARAM_FUNC_3)) /*!< Convolution (FIR filter) */ -#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 ((uint32_t)(FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)) /*!< IIR filter (direct form 1) */ +#define LL_FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */ +#define LL_FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */ +#define LL_FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */ +#define LL_FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */ +#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */ /** * @} */ +/** @defgroup FMAC_LL_EC_PROCESSING FMAC processing + * @{ + */ +#define LL_FMAC_PROCESSING_STOP 0x00U /*!< Stop FMAC Processing */ +#define LL_FMAC_PROCESSING_START 0x01U /*!< Start FMAC Processing */ /** * @} */ -/* Exported macro ------------------------------------------------------------*/ +/** + * @} + */ + +/* External variables --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /** @defgroup FMAC_LL_Exported_Macros FMAC Exported Macros * @{ */ @@ -177,7 +172,7 @@ __STATIC_INLINE void LL_FMAC_SetX1FullWatermark(FMAC_TypeDef *FMACx, uint32_t Wa * @brief Return X1 full watermark. * @rmtoll X1BUFCFG FULL_WM LL_FMAC_GetX1FullWatermark * @param FMACx FMAC instance - * @retval Returned value can be one of the following values: + * @retval uint32_t Returned value can be one of the following values: * @arg @ref LL_FMAC_WM_0_THRESHOLD_1 * @arg @ref LL_FMAC_WM_1_THRESHOLD_2 * @arg @ref LL_FMAC_WM_2_THRESHOLD_4 @@ -192,7 +187,8 @@ __STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(FMAC_TypeDef *FMACx) * @brief Configure X1 buffer size. * @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_SetX1BufferSize * @param FMACx FMAC instance - * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom"). + * @param BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom"). + * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetX1BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize) @@ -204,7 +200,8 @@ __STATIC_INLINE void LL_FMAC_SetX1BufferSize(FMAC_TypeDef *FMACx, uint8_t Buffer * @brief Return X1 buffer size. * @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_GetX1BufferSize * @param FMACx FMAC instance - * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom"). + * @retval uint8_t Number of 16-bit words allocated to the input buffer + * (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx) { @@ -215,7 +212,8 @@ __STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx) * @brief Configure X1 base. * @rmtoll X1BUFCFG X1_BASE LL_FMAC_SetX1Base * @param FMACx FMAC instance - * @param Base 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory. + * @param Base Base address of the input buffer (X1) within the internal memory. + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetX1Base(FMAC_TypeDef *FMACx, uint8_t Base) @@ -227,7 +225,8 @@ __STATIC_INLINE void LL_FMAC_SetX1Base(FMAC_TypeDef *FMACx, uint8_t Base) * @brief Return X1 base. * @rmtoll X1BUFCFG X1_BASE LL_FMAC_GetX1Base * @param FMACx FMAC instance - * @retval 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory. + * @retval uint8_t Base address of the input buffer (X1) within the internal memory + * (value between Min_Data=0x00 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx) { @@ -238,7 +237,8 @@ __STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx) * @brief Configure X2 buffer size. * @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_SetX2BufferSize * @param FMACx FMAC instance - * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer. + * @param BufferSize Number of 16-bit words allocated to the coefficient buffer. + * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetX2BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize) @@ -250,7 +250,8 @@ __STATIC_INLINE void LL_FMAC_SetX2BufferSize(FMAC_TypeDef *FMACx, uint8_t Buffer * @brief Return X2 buffer size. * @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_GetX2BufferSize * @param FMACx FMAC instance - * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer. + * @retval uint8_t Number of 16-bit words allocated to the coefficient buffer + * (value between Min_Data=0x01 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx) { @@ -261,7 +262,8 @@ __STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx) * @brief Configure X2 base. * @rmtoll X2BUFCFG X2_BASE LL_FMAC_SetX2Base * @param FMACx FMAC instance - * @param Base 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory. + * @param Base Base address of the coefficient buffer (X2) within the internal memory. + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetX2Base(FMAC_TypeDef *FMACx, uint8_t Base) @@ -273,7 +275,8 @@ __STATIC_INLINE void LL_FMAC_SetX2Base(FMAC_TypeDef *FMACx, uint8_t Base) * @brief Return X2 base. * @rmtoll X2BUFCFG X2_BASE LL_FMAC_GetX2Base * @param FMACx FMAC instance - * @retval 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory. + * @retval uint8_t Base address of the coefficient buffer (X2) within the internal memory + * (value between Min_Data=0x00 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetX2Base(FMAC_TypeDef *FMACx) { @@ -300,7 +303,7 @@ __STATIC_INLINE void LL_FMAC_SetYEmptyWatermark(FMAC_TypeDef *FMACx, uint32_t Wa * @brief Return Y empty watermark. * @rmtoll YBUFCFG EMPTY_WM LL_FMAC_GetYEmptyWatermark * @param FMACx FMAC instance - * @retval Returned value can be one of the following values: + * @retval uint32_t Returned value can be one of the following values: * @arg @ref LL_FMAC_WM_0_THRESHOLD_1 * @arg @ref LL_FMAC_WM_1_THRESHOLD_2 * @arg @ref LL_FMAC_WM_2_THRESHOLD_4 @@ -315,7 +318,8 @@ __STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(FMAC_TypeDef *FMACx) * @brief Configure Y buffer size. * @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_SetYBufferSize * @param FMACx FMAC instance - * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom"). + * @param BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom"). + * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetYBufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize) @@ -327,7 +331,8 @@ __STATIC_INLINE void LL_FMAC_SetYBufferSize(FMAC_TypeDef *FMACx, uint8_t BufferS * @brief Return Y buffer size. * @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_GetYBufferSize * @param FMACx FMAC instance - * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom"). + * @retval uint8_t Number of 16-bit words allocated to the output buffer + * (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx) { @@ -338,7 +343,8 @@ __STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx) * @brief Configure Y base. * @rmtoll YBUFCFG Y_BASE LL_FMAC_SetYBase * @param FMACx FMAC instance - * @param Base 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory. + * @param Base Base address of the output buffer (Y) within the internal memory. + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetYBase(FMAC_TypeDef *FMACx, uint8_t Base) @@ -350,7 +356,8 @@ __STATIC_INLINE void LL_FMAC_SetYBase(FMAC_TypeDef *FMACx, uint8_t Base) * @brief Return Y base. * @rmtoll YBUFCFG Y_BASE LL_FMAC_GetYBase * @param FMACx FMAC instance - * @retval 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory. + * @retval uint8_t Base address of the output buffer (Y) within the internal memory + * (value between Min_Data=0x00 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetYBase(FMAC_TypeDef *FMACx) { @@ -383,7 +390,7 @@ __STATIC_INLINE void LL_FMAC_DisableStart(FMAC_TypeDef *FMACx) * @brief Check the state of FMAC processing. * @rmtoll PARAM START LL_FMAC_IsEnabledStart * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(FMAC_TypeDef *FMACx) { @@ -411,7 +418,7 @@ __STATIC_INLINE void LL_FMAC_SetFunction(FMAC_TypeDef *FMACx, uint32_t Function) * @brief Return function. * @rmtoll PARAM FUNC LL_FMAC_GetFunction * @param FMACx FMAC instance - * @retval Returned value can be one of the following values: + * @retval uint32_t Returned value can be one of the following values: * @arg @ref LL_FMAC_FUNC_LOAD_X1 * @arg @ref LL_FMAC_FUNC_LOAD_X2 * @arg @ref LL_FMAC_FUNC_LOAD_Y @@ -427,7 +434,8 @@ __STATIC_INLINE uint32_t LL_FMAC_GetFunction(FMAC_TypeDef *FMACx) * @brief Configure input parameter R. * @rmtoll PARAM R LL_FMAC_SetParamR * @param FMACx FMAC instance - * @param Param 0x00 .. 0xFF: Parameter R (gain, etc.). + * @param Param Parameter R (gain, etc.). + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetParamR(FMAC_TypeDef *FMACx, uint8_t Param) @@ -439,7 +447,7 @@ __STATIC_INLINE void LL_FMAC_SetParamR(FMAC_TypeDef *FMACx, uint8_t Param) * @brief Return input parameter R. * @rmtoll PARAM R LL_FMAC_GetParamR * @param FMACx FMAC instance - * @retval 0x00 .. 0xFF: Parameter R (gain, etc.). + * @retval uint8_t Parameter R (gain, etc.) (value between Min_Data=0x00 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetParamR(FMAC_TypeDef *FMACx) { @@ -450,7 +458,8 @@ __STATIC_INLINE uint8_t LL_FMAC_GetParamR(FMAC_TypeDef *FMACx) * @brief Configure input parameter Q. * @rmtoll PARAM Q LL_FMAC_SetParamQ * @param FMACx FMAC instance - * @param Param 0x00 .. 0xFF: Parameter Q (vector length, etc.). + * @param Param Parameter Q (vector length, etc.). + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetParamQ(FMAC_TypeDef *FMACx, uint8_t Param) @@ -462,7 +471,7 @@ __STATIC_INLINE void LL_FMAC_SetParamQ(FMAC_TypeDef *FMACx, uint8_t Param) * @brief Return input parameter Q. * @rmtoll PARAM Q LL_FMAC_GetParamQ * @param FMACx FMAC instance - * @retval 0x00 .. 0xFF: Parameter Q (vector length, etc.). + * @retval uint8_t Parameter Q (vector length, etc.) (value between Min_Data=0x00 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetParamQ(FMAC_TypeDef *FMACx) { @@ -473,23 +482,25 @@ __STATIC_INLINE uint8_t LL_FMAC_GetParamQ(FMAC_TypeDef *FMACx) * @brief Configure input parameter P. * @rmtoll PARAM P LL_FMAC_SetParamP * @param FMACx FMAC instance - * @param Param 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.). + * @param Param Parameter P (vector length, number of filter taps, etc.). + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_SetParamP(FMAC_TypeDef *FMACx, uint8_t Param) { - MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param) << FMAC_PARAM_P_Pos); + MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param)); } /** * @brief Return input parameter P. * @rmtoll PARAM P LL_FMAC_GetParamP * @param FMACx FMAC instance - * @retval 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.). + * @retval uint8_t Parameter P (vector length, number of filter taps, etc.) + * (value between Min_Data=0x00 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetParamP(FMAC_TypeDef *FMACx) { - return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P) >> FMAC_PARAM_P_Pos); + return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P)); } /** @@ -511,22 +522,11 @@ __STATIC_INLINE void LL_FMAC_EnableReset(FMAC_TypeDef *FMACx) SET_BIT(FMACx->CR, FMAC_CR_RESET); } -/** - * @brief Interrupt the FMAC reset. - * @rmtoll CR RESET LL_FMAC_DisableReset - * @param FMACx FMAC instance - * @retval None - */ -__STATIC_INLINE void LL_FMAC_DisableReset(FMAC_TypeDef *FMACx) -{ - CLEAR_BIT(FMACx->CR, FMAC_CR_RESET); -} - /** * @brief Check the state of the FMAC reset. * @rmtoll CR RESET LL_FMAC_IsEnabledReset * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(FMAC_TypeDef *FMACx) { @@ -567,7 +567,7 @@ __STATIC_INLINE void LL_FMAC_DisableClipping(FMAC_TypeDef *FMACx) * @brief Check Clipping State. * @rmtoll CR CLIPEN LL_FMAC_IsEnabledClipping * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(FMAC_TypeDef *FMACx) { @@ -608,7 +608,7 @@ __STATIC_INLINE void LL_FMAC_DisableDMAReq_WRITE(FMAC_TypeDef *FMACx) * @brief Check FMAC DMA write channel request state. * @rmtoll CR DMAWEN LL_FMAC_IsEnabledDMAReq_WRITE * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(FMAC_TypeDef *FMACx) { @@ -641,7 +641,7 @@ __STATIC_INLINE void LL_FMAC_DisableDMAReq_READ(FMAC_TypeDef *FMACx) * @brief Check FMAC DMA read channel request state. * @rmtoll CR DMAREN LL_FMAC_IsEnabledDMAReq_READ * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(FMAC_TypeDef *FMACx) { @@ -682,7 +682,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_SAT(FMAC_TypeDef *FMACx) * @brief Check FMAC saturation error interrupt state. * @rmtoll CR SATIEN LL_FMAC_IsEnabledIT_SAT * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(FMAC_TypeDef *FMACx) { @@ -715,7 +715,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_UNFL(FMAC_TypeDef *FMACx) * @brief Check FMAC underflow error interrupt state. * @rmtoll CR UNFLIEN LL_FMAC_IsEnabledIT_UNFL * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(FMAC_TypeDef *FMACx) { @@ -748,7 +748,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_OVFL(FMAC_TypeDef *FMACx) * @brief Check FMAC overflow error interrupt state. * @rmtoll CR OVFLIEN LL_FMAC_IsEnabledIT_OVFL * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(FMAC_TypeDef *FMACx) { @@ -781,7 +781,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_WR(FMAC_TypeDef *FMACx) * @brief Check FMAC write interrupt state. * @rmtoll CR WIEN LL_FMAC_IsEnabledIT_WR * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(FMAC_TypeDef *FMACx) { @@ -814,7 +814,7 @@ __STATIC_INLINE void LL_FMAC_DisableIT_RD(FMAC_TypeDef *FMACx) * @brief Check FMAC read interrupt state. * @rmtoll CR RIEN LL_FMAC_IsEnabledIT_RD * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx) { @@ -833,7 +833,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx) * @brief Check FMAC saturation error flag state. * @rmtoll SR SAT LL_FMAC_IsActiveFlag_SAT * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx) { @@ -844,7 +844,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx) * @brief Check FMAC underflow error flag state. * @rmtoll SR UNFL LL_FMAC_IsActiveFlag_UNFL * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx) { @@ -855,7 +855,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx) * @brief Check FMAC overflow error flag state. * @rmtoll SR OVFL LL_FMAC_IsActiveFlag_OVFL * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx) { @@ -866,7 +866,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx) * @brief Check FMAC X1 buffer full flag state. * @rmtoll SR X1FULL LL_FMAC_IsActiveFlag_X1FULL * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx) { @@ -877,7 +877,7 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx) * @brief Check FMAC Y buffer empty flag state. * @rmtoll SR YEMPTY LL_FMAC_IsActiveFlag_YEMPTY * @param FMACx FMAC instance - * @retval State of bit (1 or 0). + * @retval uint32_t State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(FMAC_TypeDef *FMACx) { @@ -896,7 +896,8 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(FMAC_TypeDef *FMACx) * @brief Write 16-bit input data for the FMAC processing. * @rmtoll WDATA WDATA LL_FMAC_WriteData * @param FMACx FMAC instance - * @param InData 0x0000 .. 0xFFFF: 16-bit value to be provided as input data for FMAC processing. + * @param InData 16-bit value to be provided as input data for FMAC processing. + * This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. * @retval None */ __STATIC_INLINE void LL_FMAC_WriteData(FMAC_TypeDef *FMACx, uint16_t InData) @@ -908,7 +909,7 @@ __STATIC_INLINE void LL_FMAC_WriteData(FMAC_TypeDef *FMACx, uint16_t InData) * @brief Return 16-bit output data of FMAC processing. * @rmtoll RDATA RDATA LL_FMAC_ReadData * @param FMACx FMAC instance - * @retval 0x0000 .. 0xFFFF: 16-bit output data of FMAC processing. + * @retval uint16_t 16-bit output data of FMAC processing (value between Min_Data=0x0000 and Max_Data=0xFFFF). */ __STATIC_INLINE uint16_t LL_FMAC_ReadData(FMAC_TypeDef *FMACx) { @@ -934,14 +935,17 @@ __STATIC_INLINE uint16_t LL_FMAC_ReadData(FMAC_TypeDef *FMACx) * @arg @ref LL_FMAC_WM_1_THRESHOLD_2 * @arg @ref LL_FMAC_WM_2_THRESHOLD_4 * @arg @ref LL_FMAC_WM_3_THRESHOLD_8 - * @param Base 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory. - * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom"). + * @param Base Base address of the input buffer (X1) within the internal memory. + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @param BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom"). + * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_ConfigX1(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize) { MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM | FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE, - Watermark | (((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)); + Watermark | (((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos) | + (((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)); } /** @@ -949,14 +953,17 @@ __STATIC_INLINE void LL_FMAC_ConfigX1(FMAC_TypeDef *FMACx, uint32_t Watermark, u * @rmtoll X2BUFCFG X2_BASE LL_FMAC_ConfigX2\n * X2BUFCFG X2_BUF_SIZE LL_FMAC_ConfigX2 * @param FMACx FMAC instance - * @param Base 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory. - * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer. + * @param Base Base address of the coefficient buffer (X2) within the internal memory. + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @param BufferSize Number of 16-bit words allocated to the coefficient buffer. + * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_ConfigX2(FMAC_TypeDef *FMACx, uint8_t Base, uint8_t BufferSize) { MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE, - (((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)); + (((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos) | + (((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)); } /** @@ -970,14 +977,17 @@ __STATIC_INLINE void LL_FMAC_ConfigX2(FMAC_TypeDef *FMACx, uint8_t Base, uint8_t * @arg @ref LL_FMAC_WM_1_THRESHOLD_2 * @arg @ref LL_FMAC_WM_2_THRESHOLD_4 * @arg @ref LL_FMAC_WM_3_THRESHOLD_8 - * @param Base 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory. - * @param BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom"). + * @param Base Base address of the output buffer (Y) within the internal memory. + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @param BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom"). + * This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_ConfigY(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize) { MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM | FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE, - Watermark | (((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)); + Watermark | (((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos) | + (((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)); } /** @@ -988,23 +998,29 @@ __STATIC_INLINE void LL_FMAC_ConfigY(FMAC_TypeDef *FMACx, uint32_t Watermark, ui * PARAM Q LL_FMAC_ConfigFunc\n * PARAM R LL_FMAC_ConfigFunc * @param FMACx FMAC instance - * @param Start 0x00 .. 0x01: Enable or disable FMAC processing. + * @param Start This parameter can be one of the following values: + * @arg @ref LL_FMAC_PROCESSING_STOP + * @arg @ref LL_FMAC_PROCESSING_START * @param Function This parameter can be one of the following values: * @arg @ref LL_FMAC_FUNC_LOAD_X1 * @arg @ref LL_FMAC_FUNC_LOAD_X2 * @arg @ref LL_FMAC_FUNC_LOAD_Y * @arg @ref LL_FMAC_FUNC_CONVO_FIR * @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1 - * @param ParamP 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.). - * @param ParamQ 0x00 .. 0xFF: Parameter Q (vector length, etc.). - * @param ParamR 0x00 .. 0xFF: Parameter R (gain, etc.). + * @param ParamP Parameter P (vector length, number of filter taps, etc.). + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @param ParamQ Parameter Q (vector length, etc.). + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @param ParamR Parameter R (gain, etc.). + * This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. * @retval None */ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint32_t Function, uint8_t ParamP, uint8_t ParamQ, uint8_t ParamR) { MODIFY_REG(FMACx->PARAM, FMAC_PARAM_START | FMAC_PARAM_FUNC | FMAC_PARAM_P | FMAC_PARAM_Q | FMAC_PARAM_R, - (((uint32_t)Start) << FMAC_PARAM_START_Pos) | Function | (((uint32_t)ParamP) << FMAC_PARAM_P_Pos) | (((uint32_t)ParamQ) << FMAC_PARAM_Q_Pos) | (((uint32_t)ParamR) << FMAC_PARAM_R_Pos)); + (((uint32_t)Start) << FMAC_PARAM_START_Pos) | Function | (((uint32_t)ParamP) << FMAC_PARAM_P_Pos) | + (((uint32_t)ParamQ) << FMAC_PARAM_Q_Pos) | (((uint32_t)ParamR) << FMAC_PARAM_R_Pos)); } /** @@ -1045,5 +1061,3 @@ ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx); #endif #endif /* STM32H7xx_LL_FMAC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h index 687775a58..5e8a401e7 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -598,11 +597,13 @@ typedef struct * @} */ +#if defined(FMC_BCR1_WFDIS) /** @defgroup FMC_Write_FIFO FMC Write FIFO * @{ */ #define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS #define FMC_WRITE_FIFO_ENABLE (0x00000000U) +#endif /* FMC_BCR1_WFDIS */ /** * @} */ @@ -1159,5 +1160,3 @@ uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t B #endif #endif /* STM32H7xx_LL_FMC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h index cf032aa29..b51f9d3bf 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -983,4 +982,3 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); #endif /* STM32H7xx_LL_GPIO_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h index 36a12353f..f037e4f30 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -377,10 +376,10 @@ static const uint8_t REG_SHIFT_TAB_FLTxE[] = * @{ * @brief Constants defining the source and event to be sent on the synchronization output. */ -#define LL_HRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */ -#define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/ -#define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */ -#define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */ +#define LL_HRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */ +#define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */ +#define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */ +#define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */ /** * @} */ @@ -10474,6 +10473,4 @@ ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx); #endif /* STM32H7xx_LL_HRTIM_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h index 1e5953c50..cff88b5cd 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -63,6 +62,7 @@ extern "C" { * @} */ + /** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines * @brief Flags defines which can be used with LL_HSEM_ReadReg function * @{ @@ -238,7 +238,7 @@ __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semapho */ __STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore) { - return ((HSEMx->RLR[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL); + return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL); } /** @@ -292,6 +292,8 @@ __STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx) /** * @brief Release all semaphore with the same core id. * @rmtoll CR KEY LL_HSEM_ResetAllLock + * @rmtoll CR SEC LL_HSEM_ResetAllLock + * @rmtoll CR PRIV LL_HSEM_ResetAllLock * @param HSEMx HSEM Instance. * @param key Key value. * @param core This parameter can be one of the following values: @@ -898,5 +900,3 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32 #endif #endif /* __STM32H7xx_LL_HSEM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_i2c.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_i2c.h index c698b7ae3..a93b97f5a 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_i2c.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_i2c.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -69,38 +68,46 @@ typedef struct uint32_t PeripheralMode; /*!< Specifies the peripheral mode. This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE. - This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetMode(). */ uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. This parameter must be set by referring to the STM32CubeMX Tool and the helper macro @ref __LL_I2C_CONVERT_TIMINGS(). - This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetTiming(). */ uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION. - This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ + This feature can be modified afterwards using unitary functions + @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ uint32_t DigitalFilter; /*!< Configures the digital noise filter. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. - This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetDigitalFilter(). */ uint32_t OwnAddress1; /*!< Specifies the device own address 1. This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. - This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ - uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive + match code or next received byte. This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE. - This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_AcknowledgeNextData(). */ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1. - This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ } LL_I2C_InitTypeDef; /** * @} @@ -170,10 +177,11 @@ typedef struct /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode * @{ */ -#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ -#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ -#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */ -#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ +#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ +#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ +#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode + (Default address not acknowledge) */ +#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ /** * @} */ @@ -208,14 +216,15 @@ typedef struct /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks * @{ */ -#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ -#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/ +#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ +#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. + All Address2 are acknowledged. */ /** * @} */ @@ -250,14 +259,21 @@ typedef struct /** @defgroup I2C_LL_EC_MODE Transfer End Mode * @{ */ -#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ -#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */ -#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */ +#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ +#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Software end mode with HW PEC comparison. */ /** * @} */ @@ -265,14 +281,23 @@ typedef struct /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation * @{ */ -#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ -#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */ -#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */ -#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */ -#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U +/*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +/*!< Generate Stop condition (Size should be set to 0). */ +#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Start for read request. */ +#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Start for write request. */ +#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \ + I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) +/*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 10Bit address.*/ /** * @} */ @@ -280,8 +305,10 @@ typedef struct /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction * @{ */ -#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */ -#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/ +#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, + slave enters receiver mode. */ +#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, + slave enters transmitter mode.*/ /** * @} */ @@ -289,8 +316,10 @@ typedef struct /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data * @{ */ -#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ -#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for + transmission */ +#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for + reception */ /** * @} */ @@ -298,8 +327,10 @@ typedef struct /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout * @{ */ -#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */ -#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect + SCL low level timeout. */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect + both SCL and SDA high level timeout.*/ /** * @} */ @@ -307,9 +338,12 @@ typedef struct /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection * @{ */ -#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ -#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */ -#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */ +#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ +#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) + enable bit */ +#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \ + I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB +(extended clock) enable bits */ /** * @} */ @@ -353,18 +387,22 @@ typedef struct /** * @brief Configure the SDA setup, hold time and the SCL high, low period. * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. - * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc) - * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc) - * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc) - * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc) + * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tscldel = (SCLDEL+1)xtpresc) + * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tsdadel = SDADELxtpresc) + * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tsclh = (SCLH+1)xtpresc) + * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tscll = (SCLL+1)xtpresc) * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \ - ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ - (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ - (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ - (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ - (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) +#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \ + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) /** * @} */ @@ -428,7 +466,8 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) * @param AnalogFilter This parameter can be one of the following values: * @arg @ref LL_I2C_ANALOGFILTER_ENABLE * @arg @ref LL_I2C_ANALOGFILTER_DISABLE - * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). * This parameter is used to configure the digital noise filter on SDA and SCL input. * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. * @retval None @@ -444,7 +483,8 @@ __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilt * This filter can only be programmed when the I2C is disabled (PE = 0). * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter * @param I2Cx I2C Instance. - * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). * This parameter is used to configure the digital noise filter on SDA and SCL input. * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. * @retval None @@ -664,7 +704,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) /** * @brief Enable Wakeup from STOP. - * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not * WakeUpFromStop feature is supported by the I2Cx Instance. * @note This bit can only be programmed when Digital Filter is disabled. * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop @@ -678,7 +718,7 @@ __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx) /** * @brief Disable Wakeup from STOP. - * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not * WakeUpFromStop feature is supported by the I2Cx Instance. * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop * @param I2Cx I2C Instance. @@ -691,7 +731,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) /** * @brief Check if Wakeup from STOP is enabled or disabled. - * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not * WakeUpFromStop feature is supported by the I2Cx Instance. * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop * @param I2Cx I2C Instance. @@ -941,7 +981,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) /** * @brief Configure peripheral mode. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n * CR1 SMBDEN LL_I2C_SetMode @@ -960,7 +1000,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) /** * @brief Get peripheral mode. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n * CR1 SMBDEN LL_I2C_GetMode @@ -978,7 +1018,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) /** * @brief Enable SMBus alert (Host or Device mode) - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is drived low and @@ -996,7 +1036,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Disable SMBus alert (Host or Device mode) - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is not drived (can be used as a standard GPIO) and @@ -1014,7 +1054,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert * @param I2Cx I2C Instance. @@ -1027,7 +1067,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Enable SMBus Packet Error Calculation (PEC). - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC * @param I2Cx I2C Instance. @@ -1040,7 +1080,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Disable SMBus Packet Error Calculation (PEC). - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC * @param I2Cx I2C Instance. @@ -1053,7 +1093,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC * @param I2Cx I2C Instance. @@ -1066,7 +1106,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Configure the SMBus Clock Timeout. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n @@ -1089,7 +1129,7 @@ __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Timeo /** * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note These bits can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA @@ -1104,7 +1144,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout /** * @brief Get the SMBus Clock TimeoutA setting. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA * @param I2Cx I2C Instance. @@ -1117,7 +1157,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) /** * @brief Set the SMBus Clock TimeoutA mode. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note This bit can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode @@ -1134,7 +1174,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim /** * @brief Get the SMBus Clock TimeoutA mode. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode * @param I2Cx I2C Instance. @@ -1149,7 +1189,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) /** * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note These bits can only be programmed when TimeoutB is disabled. * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB @@ -1164,7 +1204,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout /** * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB * @param I2Cx I2C Instance. @@ -1177,7 +1217,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) /** * @brief Enable the SMBus Clock Timeout. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout @@ -1195,7 +1235,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Clock /** * @brief Disable the SMBus Clock Timeout. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout @@ -1213,7 +1253,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc /** * @brief Check if the SMBus Clock Timeout is enabled or disabled. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout @@ -1226,7 +1266,8 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) { - return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL); + return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ + (ClockTimeout)) ? 1UL : 0UL); } /** @@ -1443,7 +1484,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) /** * @brief Enable Error interrupts. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1463,7 +1504,7 @@ __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) /** * @brief Disable Error interrupts. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1645,7 +1686,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus PEC error flag in reception. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When the received PEC does not match with the PEC register content. @@ -1660,7 +1701,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus Timeout detection flag. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When a timeout or extended clock timeout occurs. @@ -1675,7 +1716,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus alert flag. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When SMBus host configuration, SMBus alert enabled and @@ -1782,7 +1823,7 @@ __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus PEC error flag. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR * @param I2Cx I2C Instance. @@ -1795,7 +1836,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus Timeout detection flag. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT * @param I2Cx I2C Instance. @@ -1808,7 +1849,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus Alert flag. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT * @param I2Cx I2C Instance. @@ -1923,7 +1964,8 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) } /** - * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code + or next received byte. * @note Usage in Slave mode only. * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData * @param I2Cx I2C Instance. @@ -1964,7 +2006,8 @@ __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) /** * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). * @note The master sends the complete 10bit slave address read sequence : - * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction. + * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address + in Read direction. * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead * @param I2Cx I2C Instance. * @retval None @@ -2125,9 +2168,10 @@ __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) /** * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. - * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. + * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition + or an Address Matched is received. * This bit has no effect when RELOAD bit is set. * This bit has no effect in device mode when SBC bit is not set. * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare @@ -2141,7 +2185,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare * @param I2Cx I2C Instance. @@ -2154,7 +2198,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Get the SMBus Packet Error byte calculated. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll PECR PEC LL_I2C_GetSMBusPEC * @param I2Cx I2C Instance. @@ -2226,5 +2270,3 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); #endif #endif /* STM32H7xx_LL_I2C_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_iwdg.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_iwdg.h index 8e22e3d7f..d34acc262 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_iwdg.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_iwdg.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -337,5 +336,3 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) #endif #endif /* STM32H7xx_LL_IWDG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lptim.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lptim.h index a2ee75c66..39ba9807f 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lptim.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lptim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -67,22 +66,26 @@ typedef struct uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance. This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE. - This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_SetClockSource().*/ uint32_t Prescaler; /*!< Specifies the prescaler division ratio. This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER. - This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/ + This feature can be modified afterwards using using unitary + function @ref LL_LPTIM_SetPrescaler().*/ uint32_t Waveform; /*!< Specifies the waveform shape. This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM. - This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_ConfigOutput().*/ uint32_t Polarity; /*!< Specifies waveform polarity. This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_ConfigOutput().*/ } LL_LPTIM_InitTypeDef; /** @@ -199,14 +202,14 @@ typedef struct #define LL_LPTIM_TRIG_SOURCE_LPTIM2 0x00000000U /*!CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); } @@ -415,7 +418,7 @@ __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *const LPTIMx) { CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE); } @@ -469,7 +472,7 @@ __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t Upda * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD */ -__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *const LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD)); } @@ -484,7 +487,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx) * @note autoreload value be strictly greater than the compare value. * @rmtoll ARR ARR LL_LPTIM_SetAutoReload * @param LPTIMx Low-Power Timer instance - * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF * @retval None */ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload) @@ -496,9 +499,9 @@ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t Auto * @brief Get actual auto reload value * @rmtoll ARR ARR LL_LPTIM_GetAutoReload * @param LPTIMx Low-Power Timer instance - * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *const LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR)); } @@ -540,7 +543,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval Counter value */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *const LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT)); } @@ -568,7 +571,7 @@ __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t Cou * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *const LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE)); } @@ -934,7 +937,8 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx) } /** - * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source. + * @brief Configure the active edge or edges used by the counter when + the LPTIM is clocked by an external clock source. * @note This function must be called when the LPTIM instance is disabled. * @note When both external clock signal edges are considered active ones, * the LPTIM must also be clocked by an internal clock source with a @@ -1152,7 +1156,8 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated. + * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully + completed. If so, a new one can be initiated. * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). @@ -1174,7 +1179,8 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated. + * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully + completed. If so, a new one can be initiated. * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). @@ -1196,7 +1202,8 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode). + * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance + operates in encoder mode). * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). @@ -1218,7 +1225,8 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode). + * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance + operates in encoder mode). * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). @@ -1490,5 +1498,3 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) #endif #endif /* STM32H7xx_LL_LPTIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h index 64e17f9c7..3fef9da74 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -159,7 +158,6 @@ typedef struct #define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */ #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ -#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ @@ -577,7 +575,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) { - MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); } /** @@ -612,7 +610,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) { - MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); } /** @@ -655,8 +653,8 @@ __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) { - MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \ - (RXThreshold << USART_CR3_RXFTCFG_Pos)); + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \ + (RXThreshold << USART_CR3_RXFTCFG_Pos)); } /** @@ -669,7 +667,7 @@ __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint */ __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_UESM); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM); } /** @@ -681,7 +679,7 @@ __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); } /** @@ -704,7 +702,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_RE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE); } /** @@ -715,7 +713,7 @@ __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); } /** @@ -726,7 +724,7 @@ __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_TE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE); } /** @@ -737,7 +735,7 @@ __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); } /** @@ -755,7 +753,7 @@ __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection) { - MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); + ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); } /** @@ -872,7 +870,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_MME); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME); } /** @@ -883,7 +881,7 @@ __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); } /** @@ -1875,17 +1873,6 @@ __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF); } -/** - * @brief Clear TX FIFO Empty Flag - * @rmtoll ICR TXFECF LL_LPUART_ClearFlag_TXFE - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx) -{ - WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF); -} - /** * @brief Clear Transmission Complete Flag * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC @@ -1946,7 +1933,7 @@ __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } /* Legacy define */ @@ -1960,7 +1947,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); } /** @@ -1971,7 +1958,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); } /* Legacy define */ @@ -1985,7 +1972,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); } /** @@ -1996,7 +1983,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_PEIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE); } /** @@ -2007,7 +1994,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); } /** @@ -2018,7 +2005,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); } /** @@ -2029,7 +2016,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); } /** @@ -2044,7 +2031,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE); } /** @@ -2055,7 +2042,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE); } /** @@ -2066,7 +2053,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE); } /** @@ -2077,7 +2064,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); } /** @@ -2088,7 +2075,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); } /** @@ -2099,7 +2086,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } /* Legacy define */ @@ -2113,7 +2100,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); } /** @@ -2124,7 +2111,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); } /* Legacy define */ @@ -2138,7 +2125,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); } /** @@ -2149,7 +2136,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE); } /** @@ -2160,7 +2147,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); } /** @@ -2171,7 +2158,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); } /** @@ -2182,7 +2169,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); } /** @@ -2197,7 +2184,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE); } /** @@ -2208,7 +2195,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE); } /** @@ -2219,7 +2206,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE); } /** @@ -2230,7 +2217,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); } /** @@ -2241,7 +2228,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); } /** @@ -2409,7 +2396,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR); } /** @@ -2420,7 +2407,7 @@ __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR); } /** @@ -2442,7 +2429,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT); } /** @@ -2453,7 +2440,7 @@ __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT); } /** @@ -2661,4 +2648,3 @@ void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); #endif /* STM32H7xx_LL_LPUART_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_mdma.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_mdma.h index 38d08f2e9..8b80c7d81 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_mdma.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_mdma.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -4357,4 +4356,3 @@ void LL_MDMA_DisconnectNextLinkNode(LL_MDMA_LinkNodeTypeDef *pLinkNode); #endif /* STM32H7xx_LL_MDMA_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_opamp.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_opamp.h index b6d4d3eb8..abc4d301d 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_opamp.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_opamp.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -255,7 +254,7 @@ typedef struct */ /** @defgroup OPAMP_LL_EC_HW_DELAYS Definitions of OPAMP hardware constraints delays - * @note Only OPAMP IP HW delays are defined in OPAMP LL driver driver, + * @note Only OPAMP peripheral HW delays are defined in OPAMP LL driver driver, * not timeout values. * For details on delays values, refer to descriptions in source code * above each literal definition. @@ -822,4 +821,4 @@ void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct); #endif /* __STM32H7xx_LL_OPAMP_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h index a7f82057c..be137a46f 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -2300,4 +2299,3 @@ ErrorStatus LL_PWR_DeInit(void); #endif /* STM32H7xx_LL_PWR_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h index 2ab40eb0f..50230079d 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h @@ -2,20 +2,16 @@ ****************************************************************************** * @file stm32h7xx_ll_rcc.h * @author MCD Application Team - * @version $VERSION$ - * @date $DATE$ * @brief Header file of RCC LL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -6409,4 +6405,3 @@ uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource); #endif /* STM32H7xx_LL_RCC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rng.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rng.h index 1b98dd0fb..6863989bd 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rng.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rng.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -679,4 +678,3 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); #endif /* __STM32H7xx_LL_RNG_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h index 230b1e3c7..ff0477b46 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -3776,7 +3775,7 @@ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t Back } #endif /* RTC_BKP0R */ -#if defined(TAMP_BKP0R_BKP) +#if defined(TAMP_BKP0R) /** * @brief Writes a data in a specified Backup data register. * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_SetRegister @@ -3877,7 +3876,7 @@ __STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t Ba /* Read the specified register */ return (*(__IO uint32_t *)tmp); } -#endif /* TAMP_BKP0R_BKP */ +#endif /* TAMP_BKP0R */ /** * @} @@ -5375,4 +5374,3 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); #endif /* STM32H7xx_LL_RTC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h index fd210d388..abac58160 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -135,13 +134,11 @@ typedef struct #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ -#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the */ - /*!< number of transferred bytes does not match the block length */ +#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ -#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock */ - /*!< command or if there was an attempt to access a locked card */ +#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ @@ -152,8 +149,7 @@ typedef struct #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ -#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out */ - /*!< of erase sequence command was received */ +#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ @@ -172,12 +168,10 @@ typedef struct #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ -#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its */ - /*!< operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/ #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ -#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information */ - /*!< and asks the card whether card supports voltage. */ +#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ #define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ @@ -185,18 +179,14 @@ typedef struct #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ -#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands */ - /*!< (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ +#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ /*!< for SDHS and SDXC. */ -#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of */ - /*!< fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by */ - /*!< STOP_TRANSMISSION command. */ +#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ -#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of */ - /*!< fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ @@ -205,37 +195,34 @@ typedef struct #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ -#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command */ - /*!< system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. */ - /*!< Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by */ - /*!< the SET_BLOCK_LEN command. */ -#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather */ - /*!< than a standard command. */ -#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card */ - /*!< for general purpose/application specific commands. */ +#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ +#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ +#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ /** * @brief Following commands are SD Card Specific commands. * SDMMC_APP_CMD should be sent before sending these commands. */ -#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus */ - /*!< widths are given in SCR register. */ +#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ -#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with */ - /*!< 32bit+CRC data block. */ -#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to */ - /*!< send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ +#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ +/** + * @brief Following commands are MMC Specific commands. + */ +#define SDMMC_CMD_MMC_SLEEP_AWAKE ((uint8_t)5U) /*!< Toggle the device between Sleep state and Standby state. */ + /** * @brief Following commands are SD Card Specific security commands. * SDMMC_CMD_APP_CMD should be sent before sending these commands. @@ -303,8 +290,9 @@ typedef struct #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) +#ifndef SDMMC_DATATIMEOUT #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) - +#endif /* SDMMC_DATATIMEOUT */ #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) @@ -702,10 +690,10 @@ typedef struct #define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA) /* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 200MHz*/ -#define SDMMC_NSpeed_CLK_DIV ((uint8_t)0x4) +#define SDMMC_NSPEED_CLK_DIV ((uint8_t)0x4) /* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 200MHz*/ -#define SDMMC_HSpeed_CLK_DIV ((uint8_t)0x2) +#define SDMMC_HSPEED_CLK_DIV ((uint8_t)0x2) /** * @} */ @@ -1074,6 +1062,7 @@ uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA); +uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); @@ -1122,5 +1111,3 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); #endif #endif /* STM32H7xx_LL_SDMMC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_spi.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_spi.h index 4dd1c2d92..3bc388b81 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_spi.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_spi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -43,10 +42,18 @@ extern "C" { /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) /** @defgroup SPI_LL_Private_Macros SPI Private Macros * @{ */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_Exported_Types SPI Exported Types + * @{ + */ /** * @brief SPI Init structures definition @@ -56,53 +63,68 @@ typedef struct uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetTransferDirection().*/ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). This parameter can be a value of @ref SPI_LL_EC_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetMode().*/ uint32_t DataWidth; /*!< Specifies the SPI data width. This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetDataWidth().*/ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_LL_EC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetClockPolarity().*/ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_LL_EC_PHASE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetClockPhase().*/ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetNSSMode().*/ - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure + the transmit and receive SCK clock. This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. The slave clock does not need to be set. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetBaudRatePrescaler().*/ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetTransferBitOrder().*/ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. - This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + This feature can be modified afterwards using unitary functions + @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFFFFF. + This parameter must be a number between Min_Data = 0x00 + and Max_Data = 0xFFFFFFFF. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetCRCPolynomial().*/ } LL_SPI_InitTypeDef; @@ -195,7 +217,8 @@ typedef struct #define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2) #define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0) #define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1) -#define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3\ + | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) /** * @} */ @@ -218,7 +241,8 @@ typedef struct #define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2) #define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0) #define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1) -#define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3\ + | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) /** * @} */ @@ -348,7 +372,8 @@ typedef struct #define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2) #define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) #define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) -#define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) #define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4) #define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0) #define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1) @@ -356,15 +381,20 @@ typedef struct #define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2) #define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) #define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) -#define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) #define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3) #define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0) #define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1) -#define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) #define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2) -#define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) -#define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) -#define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) /** * @} */ @@ -387,7 +417,8 @@ typedef struct #define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2) #define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0) #define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1) -#define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3\ + | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) /** * @} */ @@ -419,7 +450,8 @@ typedef struct #define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2) #define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) #define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) -#define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3\ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) #define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4) #define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0) #define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1) @@ -427,15 +459,20 @@ typedef struct #define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2) #define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) #define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) -#define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) #define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3) #define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0) #define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1) -#define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) #define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2) -#define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) -#define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) -#define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) /** * @} */ @@ -453,10 +490,10 @@ typedef struct /** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel * @{ */ -#define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */ -#define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) -#define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) -#define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) +#define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */ +#define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) +#define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) +#define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) /** * @} */ @@ -1253,7 +1290,8 @@ __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) /** * @brief Set Transfer Mode - * @note This configuration can not be changed when SPI is enabled except for half duplex direction using LL_SPI_SetHalfDuplexDirection. + * @note This configuration can not be changed when SPI is enabled except for half duplex direction + * using LL_SPI_SetHalfDuplexDirection. * @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n * CFG2 COMM LL_SPI_SetTransferDirection * @param SPIx SPI Instance @@ -2402,7 +2440,7 @@ __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) { - return (uint16_t)(READ_REG(SPIx->RXDR)); + return (*((__IO uint16_t *)&SPIx->RXDR)); } /** @@ -2442,7 +2480,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) *spitxdr = TxData; #else SPIx->TXDR = TxData; -#endif +#endif /* __GNUC__ */ } /** @@ -2569,37 +2607,44 @@ typedef struct uint32_t Mode; /*!< Specifies the I2S operating mode. This parameter can be a value of @ref I2S_LL_EC_MODE - This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_I2S_SetTransferMode().*/ uint32_t Standard; /*!< Specifies the standard used for the I2S communication. This parameter can be a value of @ref I2S_LL_EC_STANDARD - This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/ + This feature can be modified afterwards using unitary function + @ref LL_I2S_SetStandard().*/ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT - This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/ + This feature can be modified afterwards using unitary function + @ref LL_I2S_SetDataFormat().*/ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT - This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/ + This feature can be modified afterwards using unitary functions + @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ - Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity - and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/ + Audio Frequency can be modified afterwards using Reference manual formulas + to calculate Prescaler Linear, Parity and unitary functions + @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() + to set it.*/ uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. This parameter can be a value of @ref I2S_LL_EC_POLARITY - This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_I2S_SetClockPolarity().*/ } LL_I2S_InitTypeDef; @@ -2671,8 +2716,8 @@ typedef struct /** @defgroup I2S_LL_EC_PRESCALER_PARITY Prescaler Factor * @{ */ -#define LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL) /*!< Odd factor: Real divider value is = I2SDIV * 2 */ -#define LL_I2S_PRESCALER_PARITY_ODD (0x00000001UL) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ +#define LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL) /*!< Odd factor: Real divider value is = I2SDIV * 2 */ +#define LL_I2S_PRESCALER_PARITY_ODD (0x00000001UL) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ /** * @} */ @@ -3708,5 +3753,3 @@ void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, #endif #endif /* STM32H7xx_LL_SPI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_swpmi.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_swpmi.h index efe1daa9d..c2b31d604 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_swpmi.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_swpmi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1238,5 +1237,3 @@ void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct); #endif #endif /* STM32H7xx_LL_SWPMI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h index b4326b5d6..e42fe8c83 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h @@ -3,6 +3,18 @@ * @file stm32h7xx_ll_system.h * @author MCD Application Team * @brief Header file of SYSTEM LL module. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -16,17 +28,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -2439,4 +2440,3 @@ __STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void) #endif /* __STM32H7xx_LL_SYSTEM_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h index 4ec1297f6..dfb4ac48b 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -201,24 +200,29 @@ typedef struct uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetPrescaler().*/ uint32_t CounterMode; /*!< Specifies the counter mode. This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetCounterMode().*/ uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must + be a number between 0x0000 and 0xFFFFFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetAutoReload().*/ uint32_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetClockDivision().*/ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts @@ -226,10 +230,13 @@ typedef struct This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetRepetitionCounter().*/ } LL_TIM_InitTypeDef; /** @@ -240,43 +247,51 @@ typedef struct uint32_t OCMode; /*!< Specifies the output mode. This parameter can be a value of @ref TIM_LL_EC_OCMODE. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetMode().*/ uint32_t OCState; /*!< Specifies the TIM Output Compare state. This parameter can be a value of @ref TIM_LL_EC_OCSTATE. - This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. This parameter can be a value of @ref TIM_LL_EC_OCSTATE. - This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ + This feature can be modified afterwards using unitary function + LL_TIM_OC_SetCompareCHx (x=1..6).*/ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ } LL_TIM_OC_InitTypeDef; /** @@ -289,22 +304,26 @@ typedef struct uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t ICActiveInput; /*!< Specifies the input. This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ } LL_TIM_IC_InitTypeDef; @@ -316,47 +335,56 @@ typedef struct uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetEncoderMode().*/ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC1Filter; /*!< Specifies the TI1 input filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC2Filter; /*!< Specifies the TI2 input filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ } LL_TIM_ENCODER_InitTypeDef; @@ -369,26 +397,31 @@ typedef struct uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. Prescaler must be set to get a maximum counter period longer than the time interval between 2 consecutive changes on the Hall inputs. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC1Filter; /*!< Specifies the TI1 input filter. - This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + This parameter can be a value of + @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. A positive pulse (TRGO event) is generated with a programmable delay every time a change occurs on the Hall inputs. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetCompareCH2().*/ } LL_TIM_HALLSENSOR_InitTypeDef; /** @@ -399,79 +432,125 @@ typedef struct uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. This parameter can be a value of @ref TIM_LL_EC_OSSR - This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() - @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. This parameter can be a value of @ref TIM_LL_EC_OSSI - This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() - @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ uint32_t LockLevel; /*!< Specifies the LOCK level parameters. This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL - @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register - has been written, their content is frozen until the next reset.*/ + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR + register has been written, their content is frozen until the next reset.*/ uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetDeadTime() - @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been + programmed. */ uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ +#if defined(TIM_BDTR_BKBID) + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. + This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_ConfigBRK() + + @note Bidirectional break input is only supported by advanced timers instances. + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + +#endif /*TIM_BDTR_BKBID */ uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + +#if defined(TIM_BDTR_BKBID) + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_ConfigBRK2() + + @note Bidirectional break input is only supported by advanced timers instances. - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ +#endif /*TIM_BDTR_BKBID */ uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ } LL_TIM_BDTR_InitTypeDef; /** @@ -839,10 +918,6 @@ typedef struct #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ -#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ -#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ -#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ -#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ #define LL_TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) is used as trigger input */ #define LL_TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) is used as trigger input */ #define LL_TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) is used as trigger input */ @@ -853,6 +928,10 @@ typedef struct #define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */ #define LL_TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) is used as trigger input */ #define LL_TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) is used as trigger input */ +#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ +#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ +#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ +#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ /** * @} */ @@ -1059,6 +1138,26 @@ typedef struct */ #endif /* TIM_BREAK_INPUT_SUPPORT */ +#if defined(TIM_BDTR_BKBID) +/** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE + * @{ + */ +#define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ +#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE + * @{ + */ +#define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ +#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ +/** + * @} + */ + +#endif /*TIM_BDTR_BKBID */ /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address * @{ */ @@ -1083,10 +1182,10 @@ typedef struct #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */ #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */ #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */ -#if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE) +#if defined(TIM1_AF1_BKINE)&&defined(TIM1_AF2_BKINE) #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */ #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */ -#endif /* TIM_AF1_BKINE && TIM_AF2_BKINE */ +#endif /* TIM1_AF1_BKINE && TIM1_AF2_BKINE */ #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_TISEL register is the DMA base address for DMA burst */ /** * @} @@ -1310,10 +1409,17 @@ typedef struct * @retval DTG[0:7] */ #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ - ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ - (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ 0U) /** @@ -1324,7 +1430,7 @@ typedef struct * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ - (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) /** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. @@ -1338,7 +1444,8 @@ typedef struct ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) /** - * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler @@ -1350,7 +1457,8 @@ typedef struct / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) /** - * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler @@ -1607,7 +1715,8 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) } /** - * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators + * (when supported) and the digital filters. * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. @@ -1625,7 +1734,8 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi } /** - * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time + * generators (when supported) and the digital filters. * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. @@ -1767,7 +1877,8 @@ __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) /** * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). - * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap * @param TIMx Timer instance * @retval None @@ -2072,7 +2183,7 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); } /** @@ -2111,7 +2222,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); } /** @@ -2489,7 +2600,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Ch } /** - * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of + * the Ocx and OCxN signals). * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * dead-time insertion feature is supported by a timer instance. * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter @@ -2756,7 +2868,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), - ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ + << SHIFT_TAB_ICxx[iChannel]); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); } @@ -3273,10 +3386,6 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) * @arg @ref LL_TIM_TS_ITR1 * @arg @ref LL_TIM_TS_ITR2 * @arg @ref LL_TIM_TS_ITR3 - * @arg @ref LL_TIM_TS_TI1F_ED - * @arg @ref LL_TIM_TS_TI1FP1 - * @arg @ref LL_TIM_TS_TI2FP2 - * @arg @ref LL_TIM_TS_ETRF * @arg @ref LL_TIM_TS_ITR4 * @arg @ref LL_TIM_TS_ITR5 * @arg @ref LL_TIM_TS_ITR6 @@ -3287,6 +3396,10 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) * @arg @ref LL_TIM_TS_ITR11 (*) * @arg @ref LL_TIM_TS_ITR12 (*) * @arg @ref LL_TIM_TS_ITR13 (*) + * @arg @ref LL_TIM_TS_TI1F_ED + * @arg @ref LL_TIM_TS_TI1FP1 + * @arg @ref LL_TIM_TS_TI2FP2 + * @arg @ref LL_TIM_TS_ETRF * * (*) Value not defined in all devices. * @retval None @@ -3477,6 +3590,56 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); } +#if defined(TIM_BDTR_BKBID) +/** + * @brief Configure the break input. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @note Bidirectional mode is only supported by advanced timer instances. + * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not + * a timer instance is an advanced-control timer. + * @note In bidirectional mode (BKBID bit set), the Break input is configured both + * in input mode and in open drain output mode. Any active Break event will + * assert a low logic level on the Break input to indicate an internal break + * event to external devices. + * @note When bidirectional mode isn't supported, BreakAFMode must be set to + * LL_TIM_BREAK_AFMODE_INPUT. + * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n + * BDTR BKF LL_TIM_ConfigBRK\n + * BDTR BKBID LL_TIM_ConfigBRK + * @param TIMx Timer instance + * @param BreakPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH + * @param BreakFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 + * @param BreakAFMode This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter, + uint32_t BreakAFMode) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode); +} + +#else /** * @brief Configure the break input. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not @@ -3512,6 +3675,36 @@ __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); } +#endif /* TIM_BDTR_BKBID */ +#if defined(TIM_BDTR_BKBID) +/** + * @brief Disarm the break input (when it operates in bidirectional mode). + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); +} + +/** + * @brief Re-arm the break input (when it operates in bidirectional mode). + * @note The Break input is automatically armed as soon as MOE bit is set. + * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); +} + +#endif /*TIM_BDTR_BKBID */ /** * @brief Enable the break 2 function. * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not @@ -3538,6 +3731,56 @@ __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); } +#if defined(TIM_BDTR_BKBID) +/** + * @brief Configure the break 2 input. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @note Bidirectional mode is only supported by advanced timer instances. + * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not + * a timer instance is an advanced-control timer. + * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both + * in input mode and in open drain output mode. Any active Break event will + * assert a low logic level on the Break 2 input to indicate an internal break + * event to external devices. + * @note When bidirectional mode isn't supported, Break2AFMode must be set to + * LL_TIM_BREAK2_AFMODE_INPUT. + * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n + * BDTR BK2F LL_TIM_ConfigBRK2\n + * BDTR BK2BID LL_TIM_ConfigBRK2 + * @param TIMx Timer instance + * @param Break2Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_POLARITY_LOW + * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH + * @param Break2Filter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 + * @param Break2AFMode This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter, + uint32_t Break2AFMode) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode); +} + +#else /** * @brief Configure the break 2 input. * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not @@ -3572,6 +3815,36 @@ __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarit MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); } +#endif /*TIM_BDTR_BKBID */ +#if defined(TIM_BDTR_BKBID) +/** + * @brief Disarm the break 2 input (when it operates in bidirectional mode). + * @note The break 2 input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output. + * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); +} + +/** + * @brief Re-arm the break 2 input (when it operates in bidirectional mode). + * @note The Break 2 input is automatically armed as soon as MOE bit is set. + * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); +} + +#endif /*TIM_BDTR_BKBID */ /** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not @@ -3796,13 +4069,13 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 - * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 - * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL - * + * * @param DMABurstLength This parameter can be one of the following values: * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS @@ -4175,7 +4448,8 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set + * (Capture/Compare 1 interrupt is pending). * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). @@ -4197,7 +4471,8 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set + * (Capture/Compare 2 over-capture interrupt is pending). * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). @@ -4219,7 +4494,8 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set + * (Capture/Compare 3 over-capture interrupt is pending). * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). @@ -4241,7 +4517,8 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set + * (Capture/Compare 4 over-capture interrupt is pending). * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). @@ -4548,7 +4825,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) * @} */ -/** @defgroup TIM_LL_EF_DMA_Management DMA-Management +/** @defgroup TIM_LL_EF_DMA_Management DMA Management * @{ */ /** @@ -4934,4 +5211,3 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT #endif #endif /* __STM32H7xx_LL_TIM_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h index 4a164ba3f..5ff3e38e9 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -712,7 +711,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) { - MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); } /** @@ -751,7 +750,7 @@ __STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) { - MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); } /** @@ -798,8 +797,8 @@ __STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) { - MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | - (RXThreshold << USART_CR3_RXFTCFG_Pos)); + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | + (RXThreshold << USART_CR3_RXFTCFG_Pos)); } /** @@ -814,7 +813,7 @@ __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32 */ __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_UESM); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); } /** @@ -828,7 +827,7 @@ __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); } /** @@ -852,7 +851,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_RE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); } /** @@ -863,7 +862,7 @@ __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_RE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); } /** @@ -874,7 +873,7 @@ __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); } /** @@ -885,7 +884,7 @@ __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); } /** @@ -903,7 +902,7 @@ __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) { - MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); + ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); } /** @@ -1022,7 +1021,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_MME); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); } /** @@ -1033,7 +1032,7 @@ __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_MME); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); } /** @@ -2094,7 +2093,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) { - MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue); + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); } /** @@ -2241,7 +2240,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USAR */ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) { - MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue); + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); } /** @@ -2270,7 +2269,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) { - MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); } /** @@ -3459,7 +3458,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); } /* Legacy define */ @@ -3475,7 +3474,7 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); } /** @@ -3486,7 +3485,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); } /* Legacy define */ @@ -3502,7 +3501,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); } /** @@ -3513,7 +3512,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_PEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); } /** @@ -3524,7 +3523,7 @@ __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_CMIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); } /** @@ -3535,7 +3534,7 @@ __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_RTOIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); } /** @@ -3548,7 +3547,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_EOBIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); } /** @@ -3561,7 +3560,7 @@ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TXFEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE); } /** @@ -3572,7 +3571,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_RXFFIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE); } /** @@ -3600,7 +3599,7 @@ __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); } /** @@ -3613,7 +3612,7 @@ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_CTSIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); } /** @@ -3626,7 +3625,7 @@ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_WUFIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE); } /** @@ -3639,7 +3638,7 @@ __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_TXFTIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE); } /** @@ -3652,7 +3651,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); } /** @@ -3665,7 +3664,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_RXFTIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE); } /** @@ -3676,7 +3675,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); } /* Legacy define */ @@ -3692,7 +3691,7 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); } /** @@ -3703,7 +3702,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); } /* Legacy define */ @@ -3719,7 +3718,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); } /** @@ -3730,7 +3729,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); } /** @@ -3741,7 +3740,7 @@ __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); } /** @@ -3752,7 +3751,7 @@ __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); } /** @@ -3765,7 +3764,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); } /** @@ -3778,7 +3777,7 @@ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE); } /** @@ -3791,7 +3790,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE); } /** @@ -3819,7 +3818,7 @@ __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); } /** @@ -3832,7 +3831,7 @@ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); } /** @@ -3845,7 +3844,7 @@ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); } /** @@ -3858,7 +3857,7 @@ __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE); } /** @@ -3871,7 +3870,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); } /** @@ -3884,7 +3883,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE); } /** @@ -4118,7 +4117,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); } /** @@ -4129,7 +4128,7 @@ __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); } /** @@ -4151,7 +4150,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); } /** @@ -4162,7 +4161,7 @@ __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); } /** @@ -4400,4 +4399,3 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitS #endif /* STM32H7xx_LL_USART_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h index 5ee7cf705..7909971f5 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -23,7 +22,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* __cplusplus */ /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal_def.h" @@ -80,6 +79,7 @@ typedef enum HC_DATATGLERR } USB_OTG_HCStateTypeDef; + /** * @brief USB Instance Initialization Structure definition */ @@ -94,14 +94,15 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed */ + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY */ + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ @@ -130,8 +131,11 @@ typedef struct uint8_t is_stall; /*!< Endpoint stall condition This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t is_iso_incomplete; /*!< Endpoint isoc condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_EP_Type_ */ + This parameter can be any value of @ref USB_LL_EP_Type */ uint8_t data_pid_start; /*!< Initial data PID This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ @@ -151,6 +155,8 @@ typedef struct uint32_t xfer_len; /*!< Current transfer length */ + uint32_t xfer_size; /*!< requested transfer size */ + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ } USB_OTG_EPTypeDef; @@ -168,15 +174,16 @@ typedef struct uint8_t ep_is_in; /*!< Endpoint direction This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - uint8_t speed; /*!< USB Host speed. - This parameter can be any value of @ref USB_Core_Speed_ */ + uint8_t speed; /*!< USB Host Channel speed. + This parameter can be any value of @ref HCD_Device_Speed: + (HCD_DEVICE_SPEED_xxx) */ uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ uint8_t ep_type; /*!< Endpoint Type. - This parameter can be any value of @ref USB_EP_Type_ */ + This parameter can be any value of @ref USB_LL_EP_Type */ uint16_t max_packet; /*!< Endpoint Max packet size. This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ @@ -186,7 +193,7 @@ typedef struct uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - uint32_t XferSize; /*!< OTG Channel transfer size. */ + uint32_t XferSize; /*!< OTG Channel transfer size. */ uint32_t xfer_len; /*!< Current transfer length. */ @@ -316,10 +323,10 @@ typedef struct /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ -#define EP_MPS_64 0U -#define EP_MPS_32 1U -#define EP_MPS_16 2U -#define EP_MPS_8 3U +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U /** * @} */ @@ -393,19 +400,36 @@ typedef struct #define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U #define GRXSTS_PKTSTS_CH_HALTED 7U +#define TEST_J 1U +#define TEST_K 2U +#define TEST_SE0_NAK 3U +#define TEST_PACKET 4U +#define TEST_FORCE_EN 5U + #define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) #define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) #define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) -#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) -#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + #define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) #define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) -#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\ + + USB_OTG_HOST_CHANNEL_BASE\ + + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) + #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #define EP_ADDR_MSK 0xFU + +#ifndef USE_USB_DOUBLE_BUFFER +#define USE_USB_DOUBLE_BUFFER 1U +#endif /* USE_USB_DOUBLE_BUFFER */ /** * @} */ @@ -451,6 +475,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address); HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx); @@ -505,9 +530,7 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); #ifdef __cplusplus } -#endif +#endif /* __cplusplus */ #endif /* STM32H7xx_LL_USB_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h index 28331487d..635ea5984 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h @@ -3,6 +3,16 @@ * @file stm32h7xx_ll_utils.h * @author MCD Application Team * @brief Header file of UTILS LL module. + ****************************************************************************** + * @attention + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -16,17 +26,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -400,4 +399,3 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); #endif /* STM32H7xx_LL_UTILS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_wwdg.h b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_wwdg.h index 489cf3ec5..eef033dd6 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_wwdg.h +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_wwdg.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -327,5 +326,3 @@ __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) #endif #endif /* STM32H7xx_LL_WWDG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c index 099fb4bc9..52cf63e9f 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c @@ -5,6 +5,17 @@ * @brief HAL module driver. * This is the common part of the HAL initialization * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -19,17 +30,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -47,10 +47,10 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** - * @brief STM32H7xx HAL Driver version number V1.10.0 + * @brief STM32H7xx HAL Driver version number V1.11.0 */ #define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ -#define __STM32H7xx_HAL_VERSION_SUB1 (0x0AUL) /*!< [23:16] sub1 version */ +#define __STM32H7xx_HAL_VERSION_SUB1 (0x0BUL) /*!< [23:16] sub1 version */ #define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */ #define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\ @@ -914,7 +914,7 @@ void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1) * @brief Enable the Debug Module during Domain1/CDomain SLEEP mode * @retval None */ -void HAL_EnableDBGSleepMode(void) +void HAL_DBGMCU_EnableDBGSleepMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); } @@ -923,7 +923,7 @@ void HAL_EnableDBGSleepMode(void) * @brief Disable the Debug Module during Domain1/CDomain SLEEP mode * @retval None */ -void HAL_DisableDBGSleepMode(void) +void HAL_DBGMCU_DisableDBGSleepMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); } @@ -933,7 +933,7 @@ void HAL_DisableDBGSleepMode(void) * @brief Enable the Debug Module during Domain1/CDomain STOP mode * @retval None */ -void HAL_EnableDBGStopMode(void) +void HAL_DBGMCU_EnableDBGStopMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); } @@ -942,7 +942,7 @@ void HAL_EnableDBGStopMode(void) * @brief Disable the Debug Module during Domain1/CDomain STOP mode * @retval None */ -void HAL_DisableDBGStopMode(void) +void HAL_DBGMCU_DisableDBGStopMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); } @@ -951,7 +951,7 @@ void HAL_DisableDBGStopMode(void) * @brief Enable the Debug Module during Domain1/CDomain STANDBY mode * @retval None */ -void HAL_EnableDBGStandbyMode(void) +void HAL_DBGMCU_EnableDBGStandbyMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); } @@ -960,7 +960,7 @@ void HAL_EnableDBGStandbyMode(void) * @brief Disable the Debug Module during Domain1/CDomain STANDBY mode * @retval None */ -void HAL_DisableDBGStandbyMode(void) +void HAL_DBGMCU_DisableDBGStandbyMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); } @@ -1314,4 +1314,4 @@ void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , ui * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c index 7803f9281..92152fe5b 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c @@ -5,20 +5,22 @@ * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Converter (ADC) * peripheral: - * + Initialization and de-initialization functions - * ++ Initialization and Configuration of ADC - * + Operation functions - * ++ Start, stop, get result of conversions of regular - * group, using 3 possible modes: polling, interruption or DMA. - * + Control functions - * ++ Channels configuration on regular group - * ++ Analog Watchdog configuration - * + State functions - * ++ ADC state machine management - * ++ Interrupts and flags management + * + Peripheral Control functions + * + Peripheral State functions * Other functions (extended functions) are available in file * "stm32h7xx_hal_adc_ex.c". * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### ADC peripheral features ##### @@ -221,11 +223,11 @@ The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_ADC_RegisterCallback() + Use Functions HAL_ADC_RegisterCallback() to register an interrupt callback. [..] - Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: + Function HAL_ADC_RegisterCallback() allows to register following callbacks: (+) ConvCpltCallback : ADC conversion complete callback (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback @@ -241,11 +243,11 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default + Use function HAL_ADC_UnRegisterCallback to reset a callback to the default weak function. [..] - @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ConvCpltCallback : ADC conversion complete callback @@ -261,27 +263,27 @@ (+) MspDeInitCallback : ADC Msp DeInit callback [..] - By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET + By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). + examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when + reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when these callbacks are null (not registered beforehand). [..] - If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() + If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, + in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() - or @ref HAL_ADC_Init() function. + using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit() + or HAL_ADC_Init() function. [..] When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or @@ -290,17 +292,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -2529,44 +2520,46 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) /* group having no further conversion upcoming (same conditions as */ /* regular group interruption disabling above), */ /* and if injected scan sequence is completed. */ - if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || - ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && - ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && - (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))) + if (tmp_adc_inj_is_trigger_source_sw_start != 0UL) { - /* If End of Sequence is reached, disable interrupts */ - if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) + if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) || + ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && + (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))) { - /* Particular case if injected contexts queue is enabled: */ - /* when the last context has been fully processed, JSQR is reset */ - /* by the hardware. Even if no injected conversion is planned to come */ - /* (queue empty, triggers are ignored), it can start again */ - /* immediately after setting a new context (JADSTART is still set). */ - /* Therefore, state of HAL ADC injected group is kept to busy. */ - if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) + /* If End of Sequence is reached, disable interrupts */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { - /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ - /* JADSTART==0 (no conversion on going) */ - if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + /* Particular case if injected contexts queue is enabled: */ + /* when the last context has been fully processed, JSQR is reset */ + /* by the hardware. Even if no injected conversion is planned to come */ + /* (queue empty, triggers are ignored), it can start again */ + /* immediately after setting a new context (JADSTART is still set). */ + /* Therefore, state of HAL ADC injected group is kept to busy. */ + if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) { - /* Disable ADC end of sequence conversion interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); + /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ + /* JADSTART==0 (no conversion on going) */ + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Disable ADC end of sequence conversion interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } } } } @@ -4059,4 +4052,3 @@ void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c index 8e44bf1e6..6dd4901cc 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c @@ -5,20 +5,21 @@ * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Converter (ADC) * peripheral: - * + Operation functions - * ++ Start, stop, get result of conversions of ADC group injected, - * using 2 possible modes: polling, interruption. - * ++ Calibration - * +++ ADC automatic self-calibration - * +++ Calibration factors get or set - * ++ Multimode feature when available - * + Control functions - * ++ Channels configuration on ADC group injected - * + State functions - * ++ ADC group injected contexts queue management + * + Peripheral Control functions * Other functions (generic functions) are available in file * "stm32h7xx_hal_adc.c". * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim [..] (@) Sections "ADC peripheral features" and "How to use this driver" are @@ -26,17 +27,6 @@ [..] @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -2102,7 +2092,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I if (sConfigInjected->InjecOversamplingMode == ENABLE) { +#if defined(ADC_VER_V5_V90) + if (hadc->Instance == ADC3) + { + assert_param(IS_ADC_OVERSAMPLING_RATIO_ADC3(sConfigInjected->InjecOversampling.Ratio)); + } + else + { + assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio)); + } +#else assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio)); +#endif assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift)); /* JOVSE must be reset in case of triggered regular mode */ @@ -2113,14 +2114,39 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* - Right bit shift */ /* Enable OverSampling mode */ +#if defined(ADC_VER_V5_V90) + if (hadc->Instance != ADC3) + { + MODIFY_REG(hadc->Instance->CFGR2, + ADC_CFGR2_JOVSE | + ADC_CFGR2_OVSR | + ADC_CFGR2_OVSS, + ADC_CFGR2_JOVSE | + ((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) | + sConfigInjected->InjecOversampling.RightBitShift + ); + } + else + { + MODIFY_REG(hadc->Instance->CFGR2, + ADC_CFGR2_JOVSE | + ADC3_CFGR2_OVSR | + ADC_CFGR2_OVSS, + ADC_CFGR2_JOVSE | + (sConfigInjected->InjecOversampling.Ratio) | + sConfigInjected->InjecOversampling.RightBitShift + ); + } +#else MODIFY_REG(hadc->Instance->CFGR2, - ADC_CFGR2_JOVSE | - ADC_CFGR2_OVSR | - ADC_CFGR2_OVSS, - ADC_CFGR2_JOVSE | - ((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) | - sConfigInjected->InjecOversampling.RightBitShift - ); + ADC_CFGR2_JOVSE | + ADC_CFGR2_OVSR | + ADC_CFGR2_OVSS, + ADC_CFGR2_JOVSE | + ((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) | + sConfigInjected->InjecOversampling.RightBitShift + ); +#endif } else { @@ -2145,7 +2171,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I { tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset); } - + if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) { /* Set ADC selected offset number */ @@ -2590,4 +2616,3 @@ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c index d732a36d6..c3f408eb4 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c @@ -11,6 +11,17 @@ * + Peripheral Control function * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -47,10 +58,10 @@ The compilation define USE_HAL_CEC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback() + Use Functions HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback() to register an interrupt callback. - Function @ref HAL_CEC_RegisterCallback() allows to register following callbacks: + Function HAL_CEC_RegisterCallback() allows to register following callbacks: (+) TxCpltCallback : Tx Transfer completed callback. (+) ErrorCallback : callback for error detection. (+) MspInitCallback : CEC MspInit. @@ -59,11 +70,11 @@ and a pointer to the user callback function. For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks - @ref HAL_CEC_RegisterRxCpltCallback(). + HAL_CEC_RegisterRxCpltCallback(). - Use function @ref HAL_CEC_UnRegisterCallback() to reset a callback to the default + Use function HAL_CEC_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxCpltCallback : Tx Transfer completed callback. @@ -72,15 +83,15 @@ (+) MspDeInitCallback : CEC MspDeInit. For callback HAL_CEC_RxCpltCallback use dedicated unregister callback : - @ref HAL_CEC_UnRegisterRxCpltCallback(). + HAL_CEC_UnRegisterRxCpltCallback(). - By default, after the @ref HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET + By default, after the HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET all callbacks are set to the corresponding weak functions : - examples @ref HAL_CEC_TxCpltCallback() , @ref HAL_CEC_RxCpltCallback(). + examples HAL_CEC_TxCpltCallback() , HAL_CEC_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the @ref HAL_CEC_Init()/ @ref HAL_CEC_DeInit() only when + reset to the legacy weak function in the HAL_CEC_Init()/ HAL_CEC_DeInit() only when these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the @ref HAL_CEC_Init() / @ref HAL_CEC_DeInit() + if not, MspInit or MspDeInit are not null, the HAL_CEC_Init() / HAL_CEC_DeInit() keep and use the user MspInit/MspDeInit functions (registered beforehand) Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only. @@ -88,25 +99,14 @@ in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_CEC_RegisterCallback() before calling @ref HAL_CEC_DeInit() - or @ref HAL_CEC_Init() function. + using HAL_CEC_RegisterCallback() before calling HAL_CEC_DeInit() + or HAL_CEC_Init() function. When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -497,7 +497,7 @@ HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_Call /** * @brief Unregister an CEC Callback - * CEC callabck is redirected to the weak predefined callback + * CEC callback is redirected to the weak predefined callback * @param hcec uart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -696,7 +696,7 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec) HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size) { - /* if the IP isn't already busy and if there is no previous transmission + /* if the peripheral isn't already busy and if there is no previous transmission already pending due to arbitration lost */ if (hcec->gState == HAL_CEC_STATE_READY) { @@ -994,4 +994,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c index 59a2590ce..e73ebb6e6 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_comp.c @@ -6,10 +6,19 @@ * This file provides firmware functions to manage the following * functionalities of the COMP peripheral: * + Initialization and de-initialization functions - * + Start/Stop operation functions in polling mode - * + Start/Stop operation functions in interrupt mode * + Peripheral control functions - * + Peripheral state functions + * + Peripheral state functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ================================================================================ ##### COMP Peripheral features ##### @@ -98,11 +107,11 @@ The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_COMP_RegisterCallback() + Use Functions HAL_COMP_RegisterCallback() to register an interrupt callback. [..] - Function @ref HAL_COMP_RegisterCallback() allows to register following callbacks: + Function HAL_COMP_RegisterCallback() allows to register following callbacks: (+) TriggerCallback : callback for COMP trigger. (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. @@ -110,11 +119,11 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_COMP_UnRegisterCallback to reset a callback to the default + Use function HAL_COMP_UnRegisterCallback to reset a callback to the default weak function. [..] - @ref HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TriggerCallback : callback for COMP trigger. @@ -122,27 +131,27 @@ (+) MspDeInitCallback : callback for Msp DeInit. [..] - By default, after the @ref HAL_COMP_Init() and when the state is @ref HAL_COMP_STATE_RESET + By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET all callbacks are set to the corresponding weak functions: - example @ref HAL_COMP_TriggerCallback(). + example HAL_COMP_TriggerCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() only when + reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when these callbacks are null (not registered beforehand). [..] - If MspInit or MspDeInit are not null, the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() + If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_COMP_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_COMP_STATE_READY or @ref HAL_COMP_STATE_RESET state, + in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_COMP_RegisterCallback() before calling @ref HAL_COMP_DeInit() - or @ref HAL_COMP_Init() function. + using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit() + or HAL_COMP_Init() function. [..] When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or @@ -179,17 +188,6 @@ (1) GPIO must be set to alternate function for comparator (2) Comparators output to timers is set in timers instances. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** */ @@ -1247,4 +1245,3 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cordic.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cordic.c index 37f70e7ef..7ac929a6d 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cordic.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cordic.c @@ -11,7 +11,18 @@ * + IRQ handler management * + Peripheral State functions * - * @verbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim ================================================================================ ##### How to use this driver ##### ================================================================================ @@ -79,9 +90,9 @@ The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_CORDIC_RegisterCallback() to register an interrupt callback. + Use Function HAL_CORDIC_RegisterCallback() to register an interrupt callback. - Function @ref HAL_CORDIC_RegisterCallback() allows to register following callbacks: + Function HAL_CORDIC_RegisterCallback() allows to register following callbacks: (+) ErrorCallback : Error Callback. (+) CalculateCpltCallback : Calculate complete Callback. (+) MspInitCallback : CORDIC MspInit. @@ -89,9 +100,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_CORDIC_UnRegisterCallback() to reset a callback to the default + Use function HAL_CORDIC_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ErrorCallback : Error Callback. @@ -101,11 +112,11 @@ By default, after the HAL_CORDIC_Init() and when the state is HAL_CORDIC_STATE_RESET, all callbacks are set to the corresponding weak functions: - examples @ref HAL_CORDIC_ErrorCallback(), @ref HAL_CORDIC_CalculateCpltCallback(). + examples HAL_CORDIC_ErrorCallback(), HAL_CORDIC_CalculateCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the HAL_CORDIC_Init()/ @ref HAL_CORDIC_DeInit() only when + reset to the legacy weak function in the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit() only when these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ @ref HAL_CORDIC_DeInit() + if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in HAL_CORDIC_STATE_READY state only. @@ -113,7 +124,7 @@ in HAL_CORDIC_STATE_READY or HAL_CORDIC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_CORDIC_RegisterCallback() before calling @ref HAL_CORDIC_DeInit() + using HAL_CORDIC_RegisterCallback() before calling HAL_CORDIC_DeInit() or HAL_CORDIC_Init() function. When The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS is set to 0 or @@ -121,18 +132,6 @@ are set to the corresponding weak functions. @endverbatim - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** */ @@ -1352,5 +1351,3 @@ static void CORDIC_DMAError(DMA_HandleTypeDef *hdma) #endif /* HAL_CORDIC_MODULE_ENABLED */ #endif /* CORDIC */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c index e45e7936f..05730c1d0 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c @@ -68,13 +68,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -530,4 +529,3 @@ uint32_t HAL_GetCurrentCPUID(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc.c index e0860ac1d..1deacc0fc 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc.c @@ -9,6 +9,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -29,17 +40,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -62,8 +62,8 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup CRC_Private_Functions CRC Private Functions - * @{ - */ + * @{ + */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength); static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength); /** @@ -77,8 +77,8 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 */ /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * + * @brief Initialization and Configuration functions. + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -250,8 +250,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) */ /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions. - * + * @brief management functions. + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -385,8 +385,8 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t */ /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. - * + * @brief Peripheral State functions. + * @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -418,8 +418,8 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) */ /** @addtogroup CRC_Private_Functions - * @{ - */ + * @{ + */ /** * @brief Enter 8-bit input data to the CRC calculator. @@ -514,5 +514,3 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c index 97e70c149..d71318713 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c @@ -6,6 +6,17 @@ * This file provides firmware functions to manage the extended * functionalities of the CRC peripheral. * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ================================================================================ ##### How to use this driver ##### @@ -16,17 +27,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -221,5 +221,3 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c index c1febda0d..d4684da26 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c @@ -13,6 +13,17 @@ * + CRYP IRQ handler management * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -251,20 +262,6 @@ 95 ...64 CRYP_IV1L[31:0] B0[95:64] 63 ... 32 CRYP_IV0R[31:0] B0[63:32] 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0 - - - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -456,7 +453,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) } #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ - /* Set the key size(This bit field is dont care in the DES or TDES modes) data type and Algorithm */ + /* Set the key size(This bit field is don't care in the DES or TDES modes) data type and Algorithm */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); #if !defined (CRYP_VER_2_2) @@ -567,7 +564,7 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD hcryp->Init.B0 = pConf->B0; hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; - /* Set the key size(This bit field is dont care in the DES or TDES modes) data type, AlgoMode and operating mode*/ + /* Set the key size(This bit field is don't care in the DES or TDES modes) data type, AlgoMode and operating mode*/ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); @@ -976,7 +973,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; - /* Statrt DES/TDES encryption process */ + /* Start DES/TDES encryption process */ status = CRYP_TDES_Process(hcryp, Timeout); break; @@ -5179,4 +5176,3 @@ static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef *hcryp, u * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c index ae2473363..c87155227 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c @@ -7,6 +7,17 @@ * functionalities of CRYP extension peripheral: * + Extended AES processing functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -16,18 +27,6 @@ Encryption/Decryption to get the authentication messages. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -158,7 +157,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Select final phase */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL); - /*ALGODIR bit must be set to 0.*/ + /*ALGODIR bit must be set to '0'.*/ hcryp->Instance->CR &= ~CRYP_CR_ALGODIR; /* Enable the CRYP peripheral */ @@ -315,7 +314,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Disable CRYP to start the final phase */ __HAL_CRYP_DISABLE(hcryp); - /* Select final phase & ALGODIR bit must be set to 0. */ + /* Select final phase & ALGODIR bit must be set to '0'. */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH | CRYP_CR_ALGODIR, CRYP_PHASE_FINAL | CRYP_OPERATINGMODE_ENCRYPT); /* Enable the CRYP peripheral */ @@ -455,4 +454,3 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c index db5ab8c7d..2425ee342 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c @@ -11,6 +11,17 @@ * + Peripheral State and Errors functions * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### DAC Peripheral features ##### @@ -48,6 +59,7 @@ (DAC_TRIGGER_HR1_TRGO1, DAC_TRIGGER_HR1_TRGO2) (#) Software using DAC_TRIGGER_SOFTWARE + *** DAC Buffer mode feature *** =============================== [..] @@ -60,15 +72,6 @@ (@) Refer to the device datasheet for more details about output impedance value with and without output buffer. - *** DAC connect feature *** - =============================== - [..] - Each DAC channel can be connected internally. - To connect, use - sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL; - or - sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_BOTH; - *** GPIO configurations guidelines *** ===================== [..] @@ -219,7 +222,7 @@ The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback, + Use Functions HAL_DAC_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. @@ -234,7 +237,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default + Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. @@ -249,12 +252,12 @@ (+) All Callbacks This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET + By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init - and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit + reset to the legacy weak (surcharged) functions in the HAL_DAC_Init + and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -262,8 +265,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit - or @ref HAL_DAC_Init function. + using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit + or HAL_DAC_Init function. When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -283,17 +286,6 @@ (@) You can refer to the DAC HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** */ @@ -542,6 +534,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); } } + else { /* Check if software trigger enabled */ @@ -552,6 +545,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) } } + /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -595,7 +589,7 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param pData The destination peripheral Buffer address. + * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to DAC peripheral * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: @@ -653,6 +647,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u break; } } + else { /* Set the DMA transfer complete callback for channel2 */ @@ -687,6 +682,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u } } + /* Enable the DMA Stream */ if (Channel == DAC_CHANNEL_1) { @@ -696,6 +692,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u /* Enable the DMA Stream */ status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); } + else { /* Enable the DAC DMA underrun interrupt */ @@ -705,6 +702,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); } + /* Process Unlocked */ __HAL_UNLOCK(hdac); @@ -754,6 +752,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); } + else /* Channel2 is used for */ { /* Disable the DMA Stream */ @@ -763,6 +762,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2); } + /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -788,7 +788,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; - /* Set DAC error code to chanel1 DMA underrun error */ + /* Set DAC error code to channel1 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); /* Clear the underrun flag */ @@ -806,6 +806,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) } } + if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) { /* Check underrun flag of DAC channel 2 */ @@ -831,6 +832,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } + } /** @@ -851,7 +853,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { - __IO uint32_t tmp = 0; + __IO uint32_t tmp = 0UL; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -863,11 +865,13 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, ui { tmp += DAC_DHR12R1_ALIGNMENT(Alignment); } + else { tmp += DAC_DHR12R2_ALIGNMENT(Alignment); } + /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; @@ -970,18 +974,23 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) */ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) { + uint32_t result; + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); - /* Returns the DAC channel data output register value */ if (Channel == DAC_CHANNEL_1) { - return hdac->Instance->DOR1; + result = hdac->Instance->DOR1; } + else { - return hdac->Instance->DOR2; + result = hdac->Instance->DOR2; } + + /* Returns the DAC channel data output register value */ + return result; } /** @@ -1052,6 +1061,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf HAL_Delay(1); hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } + else /* Channel 2 */ { /* SHSR2 can be written when BWST2 is cleared */ @@ -1073,6 +1083,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } + /* HoldTime */ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); @@ -1143,7 +1154,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; /* Disable wave generation */ - hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL)); + CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -1267,6 +1278,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call case HAL_DAC_CH1_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh1 = pCallback; break; + case HAL_DAC_CH2_COMPLETE_CB_ID : hdac->ConvCpltCallbackCh2 = pCallback; break; @@ -1279,6 +1291,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call case HAL_DAC_CH2_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh2 = pCallback; break; + case HAL_DAC_MSPINIT_CB_ID : hdac->MspInitCallback = pCallback; break; @@ -1366,6 +1379,7 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca case HAL_DAC_CH1_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; break; + case HAL_DAC_CH2_COMPLETE_CB_ID : hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; break; @@ -1378,6 +1392,7 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca case HAL_DAC_CH2_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; break; + case HAL_DAC_MSPINIT_CB_ID : hdac->MspInitCallback = HAL_DAC_MspInit; break; @@ -1389,10 +1404,12 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; + hdac->MspInitCallback = HAL_DAC_MspInit; hdac->MspDeInitCallback = HAL_DAC_MspDeInit; break; @@ -1522,4 +1539,3 @@ void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c index 50dd895d5..c9290bea3 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac_ex.c @@ -7,13 +7,26 @@ * functionalities of the DAC peripheral. * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] + *** Dual mode IO operation *** ============================== + [..] (+) Use HAL_DACEx_DualStart() to enable both channel and start conversion for dual mode operation. If software trigger is selected, using HAL_DACEx_DualStart() will start @@ -35,6 +48,7 @@ *** Signal generation operation *** =================================== + [..] (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. @@ -45,17 +59,6 @@ at least one time after reset). @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** */ @@ -106,6 +109,7 @@ * @{ */ + /** * @brief Enables DAC and starts conversion of both channels. * @param hdac pointer to a DAC_HandleTypeDef structure that contains @@ -343,6 +347,7 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann return status; } + /** * @brief Enable or disable the selected DAC channel wave generation. * @param hdac pointer to a DAC_HandleTypeDef structure that contains @@ -443,6 +448,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t return HAL_OK; } + /** * @brief Set the specified data holding register value for dual DAC channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains @@ -552,6 +558,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) */ } + /** * @brief Run the self calibration of one DAC channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains @@ -762,6 +769,7 @@ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) * @{ */ + /** * @brief Return the last data output value of the selected DAC channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains @@ -780,10 +788,10 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) return tmp; } + /** * @} */ - /** * @} */ @@ -794,6 +802,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) * @{ */ + /** * @brief DMA conversion complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains @@ -852,6 +861,7 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) hdac->State = HAL_DAC_STATE_READY; } + /** * @} */ @@ -868,4 +878,3 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c index f9079cf41..50971e783 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -105,18 +116,6 @@ (@) You can refer to the DCMI HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1224,4 +1223,3 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm.c index e73cd8011..f83b8a5cc 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm.c @@ -16,6 +16,17 @@ * + Clock absence detector feature * + Break generation on analog watchdog or short-circuit event * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -251,17 +262,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -3795,4 +3795,3 @@ static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm_ex.c index de2f6c6cc..4b48b0478 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm_ex.c @@ -10,13 +10,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -132,4 +131,3 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeD * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c index 934400ce4..b8a17fcdf 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -78,18 +89,6 @@ (@) You can refer to the DMA HAL driver header file for more useful macros. @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -244,12 +243,12 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } - /* Allocate lock resource */ - __HAL_UNLOCK(hdma); - /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); @@ -358,12 +357,12 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); } - /* Allocate lock resource */ - __HAL_UNLOCK(hdma); - /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + /* Get the CR register value */ registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; @@ -652,12 +651,12 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui } else { - /* Process unlocked */ - __HAL_UNLOCK(hdma); - /* Set the error code to busy */ hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + /* Process unlocked */ + __HAL_UNLOCK(hdma); + /* Return error status */ status = HAL_ERROR; } @@ -748,12 +747,12 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, } else { - /* Process unlocked */ - __HAL_UNLOCK(hdma); - /* Set the error code to busy */ hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + /* Process unlocked */ + __HAL_UNLOCK(hdma); + /* Return error status */ status = HAL_ERROR; } @@ -835,12 +834,12 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + return HAL_ERROR; } } @@ -873,11 +872,11 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) } } - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); } return HAL_OK; @@ -945,12 +944,12 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) } } - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) { @@ -1173,10 +1172,10 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level (*ifcr_reg) = (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU)); } + hdma->State = HAL_DMA_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hdma); - - hdma->State = HAL_DMA_STATE_READY; } else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/ { @@ -1324,12 +1323,12 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + if(hdma->XferAbortCallback != NULL) { hdma->XferAbortCallback(hdma); @@ -1366,11 +1365,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Disable the transfer complete interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); } if(hdma->XferCpltCallback != NULL) @@ -1401,9 +1400,6 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) { /* Change the DMA state to error if DMA disable fails */ @@ -1414,6 +1410,9 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Change the DMA state to Ready if DMA disable success */ hdma->State = HAL_DMA_STATE_READY; } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); } if(hdma->XferErrorCallback != NULL) @@ -1509,11 +1508,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); } if(hdma->XferCpltCallback != NULL) @@ -1537,12 +1536,12 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + if (hdma->XferErrorCallback != NULL) { /* Transfer error callback */ @@ -1613,6 +1612,7 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call break; default: + status = HAL_ERROR; break; } } @@ -2054,4 +2054,3 @@ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c index dcc18836f..d535aa970 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma2d.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -147,17 +158,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -2183,5 +2183,3 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ */ #endif /* DMA2D */ #endif /* HAL_DMA2D_MODULE_ENABLED */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c index e55c3d54c..a134b4eb6 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c @@ -37,13 +37,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -711,4 +710,3 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c index 073c2a6e4..293a48ac1 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c @@ -9,6 +9,17 @@ * + IO operation functions * + Peripheral Control functions * + Peripheral State and Errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -140,17 +151,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -200,12 +200,14 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32 uint32_t Data1); static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, - uint32_t ChannelID, - uint32_t Mode, - uint32_t Param1, - uint32_t Param2); - + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2); /* Private functions ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Functions DSI Private Functions + * @{ + */ /** * @brief Generic DSI packet header configuration * @param DSIx Pointer to DSI register base @@ -255,10 +257,10 @@ static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, tickstart = HAL_GetTick(); /* Wait for Command FIFO Empty */ - while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) + while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -271,6 +273,10 @@ static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, return HAL_OK; } +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup DSI_Exported_Functions * @{ @@ -365,11 +371,17 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI /* Set the PLL division factors */ hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); - hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << 2U) | ((PLLInit->PLLIDF) << 11U) | ((PLLInit->PLLODF) << 16U)); + hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \ + ((PLLInit->PLLIDF) << DSI_WRPCR_PLL_IDF_Pos) | \ + ((PLLInit->PLLODF) << DSI_WRPCR_PLL_ODF_Pos)); /* Enable the DSI PLL */ __HAL_DSI_PLL_ENABLE(hdsi); + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + /* Get tick */ tickstart = HAL_GetTick(); @@ -419,7 +431,7 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI hdsi->Instance->IER[1U] = 0U; hdsi->ErrorMsk = 0U; - /* Initialise the error code */ + /* Initialize the error code */ hdsi->ErrorCode = HAL_DSI_ERROR_NONE; /* Initialize the DSI state*/ @@ -473,7 +485,7 @@ HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) HAL_DSI_MspDeInit(hdsi); #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ - /* Initialise the error code */ + /* Initialize the error code */ hdsi->ErrorCode = HAL_DSI_ERROR_NONE; /* Initialize the DSI state*/ @@ -698,7 +710,7 @@ HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Call /** * @brief Unregister a DSI Callback - * DSI callabck is redirected to the weak predefined callback + * DSI callback is redirected to the weak predefined callback * @param hdsi dsi handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -733,11 +745,11 @@ HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Ca break; case HAL_DSI_MSPINIT_CB_ID : - hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */ + hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */ break; case HAL_DSI_MSPDEINIT_CB_ID : - hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */ + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */ break; default : @@ -753,11 +765,11 @@ HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Ca switch (CallbackID) { case HAL_DSI_MSPINIT_CB_ID : - hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */ + hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */ break; case HAL_DSI_MSPDEINIT_CB_ID : - hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */ + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */ break; default : @@ -808,7 +820,8 @@ HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Ca */ void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) { - uint32_t ErrorStatus0, ErrorStatus1; + uint32_t ErrorStatus0; + uint32_t ErrorStatus1; /* Tearing Effect Interrupt management ***************************************/ if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U) @@ -1365,7 +1378,8 @@ HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerT High-Speed transmission. To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed to Low-Power and from Low-Power to High-Speed. - This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR). + This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration + Register (DSI_CLTCR). But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME. Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME. @@ -1587,7 +1601,7 @@ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, /* Process locked */ __HAL_LOCK(hdsi); - status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2); + status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2); /* Process unlocked */ __HAL_UNLOCK(hdsi); @@ -1616,7 +1630,9 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t Param1, uint8_t *ParametersTable) { - uint32_t uicounter, nbBytes, count; + uint32_t uicounter; + uint32_t nbBytes; + uint32_t count; uint32_t tickstart; uint32_t fifoword; uint8_t *pparams = ParametersTable; @@ -1721,7 +1737,7 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, { /* set max return packet size */ if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU), - (((datasize) >> 8U) & 0xFFU)) != HAL_OK) + (((datasize) >> 8U) & 0xFFU)) != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); @@ -1782,6 +1798,21 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, return HAL_TIMEOUT; } + + /* Software workaround to avoid HAL_TIMEOUT when a DSI read command is */ + /* issued to the panel and the read data is not captured by the DSI Host */ + /* which returns Packet Size Error. */ + /* Need to ensure that the Read command has finished before checking PSE */ + if ((hdsi->Instance->GPSR & DSI_GPSR_RCB) == 0U) + { + if ((hdsi->Instance->ISR[1U] & DSI_ISR1_PSE) == DSI_ISR1_PSE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } } /* Process unlocked */ @@ -2077,7 +2108,7 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) /* De-assert the ULPM requests and the ULPM exit bits */ hdsi->Instance->PUCR = 0U; - /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */ + /* Switch the lane byte clock source in the RCC from system PLL to D-PHY */ __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PHY); /* Restore clock lane configuration to HS */ @@ -2727,5 +2758,3 @@ uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dts.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dts.c index e2774d19b..21faccde8 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dts.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dts.c @@ -11,6 +11,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ================================================================================ ##### DTS Peripheral features ##### @@ -27,17 +38,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -824,4 +824,3 @@ static void DTS_ResetCallback(DTS_HandleTypeDef *hdts) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c index decff7945..1b21dd4b3 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -39,18 +50,14 @@ (##) HAL_ETH_Start(): This API starts the MAC and DMA transmission and reception process, without enabling end of transfer interrupts, in this mode user - has to poll for data availability by calling HAL_ETH_IsRxDataAvailable() + has to poll for data reception by calling HAL_ETH_ReadData() (##) HAL_ETH_Start_IT(): This API starts the MAC and DMA transmission and reception process, end of transfer interrupts are enabled in this mode, HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received - (#) When data is received (HAL_ETH_IsRxDataAvailable() returns 1 or Rx interrupt - occurred), user can call the following APIs to get received data: - (##) HAL_ETH_GetRxDataBuffer(): Get buffer address of received frame - (##) HAL_ETH_GetRxDataLength(): Get received frame length - (##) HAL_ETH_GetRxDataInfo(): Get received frame additional info, - please refer to ETH_RxPacketInfo typedef structure + (#) When data is received user can call the following API to get received data: + (##) HAL_ETH_ReadData(): Read a received packet (#) For transmission path, two APIs are available: (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode @@ -69,20 +76,32 @@ (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef - -@- The PTP protocol offload APIs are not supported in this driver. + (#) Configure the Ethernet PTP after ETH peripheral initialization + (##) Define HAL_ETH_USE_PTP to use PTP APIs. + (##) HAL_ETH_PTP_GetConfig(): Get PTP actual configuration into ETH_PTP_ConfigTypeDef + (##) HAL_ETH_PTP_SetConfig(): Set PTP configuration based on ETH_PTP_ConfigTypeDef + (##) HAL_ETH_PTP_GetTime(): Get Seconds and Nanoseconds for the Ethernet PTP registers + (##) HAL_ETH_PTP_SetTime(): Set Seconds and Nanoseconds for the Ethernet PTP registers + (##) HAL_ETH_PTP_AddTimeOffset(): Add Seconds and Nanoseconds offset for the Ethernet PTP registers + (##) HAL_ETH_PTP_InsertTxTimestamp(): Insert Timestamp in transmission + (##) HAL_ETH_PTP_GetTxTimestamp(): Get transmission timestamp + (##) HAL_ETH_PTP_GetRxTimestamp(): Get reception timestamp + + -@- The ARP offload feature is not supported in this driver. + + -@- The PTP offload feature is not supported in this driver. *** Callback registration *** ============================================= The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback. + Use Function HAL_ETH_RegisterCallback() to register an interrupt callback. - Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks: + Function HAL_ETH_RegisterCallback() allows to register following callbacks: (+) TxCpltCallback : Tx Complete Callback. (+) RxCpltCallback : Rx Complete Callback. - (+) DMAErrorCallback : DMA Error Callback. - (+) MACErrorCallback : MAC Error Callback. + (+) ErrorCallback : Error Callback. (+) PMTCallback : Power Management Callback (+) EEECallback : EEE Callback. (+) WakeUpCallback : Wake UP Callback @@ -92,28 +111,51 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default + For specific callbacks RxAllocateCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterRxAllocateCallback(). + + For specific callbacks RxLinkCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterRxLinkCallback(). + + For specific callbacks TxFreeCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterTxFreeCallback(). + + For specific callbacks TxPtpCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterTxPtpCallback(). + + Use function HAL_ETH_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxCpltCallback : Tx Complete Callback. (+) RxCpltCallback : Rx Complete Callback. - (+) DMAErrorCallback : DMA Error Callback. - (+) MACErrorCallback : MAC Error Callback. + (+) ErrorCallback : Error Callback. (+) PMTCallback : Power Management Callback (+) EEECallback : EEE Callback. (+) WakeUpCallback : Wake UP Callback (+) MspInitCallback : MspInit Callback. (+) MspDeInitCallback: MspDeInit Callback. + For specific callbacks RxAllocateCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterRxAllocateCallback(). + + For specific callbacks RxLinkCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterRxLinkCallback(). + + For specific callbacks TxFreeCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterTxFreeCallback(). + + For specific callbacks TxPtpCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterTxPtpCallback(). + By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback(). + examples HAL_ETH_TxCpltCallback(), HAL_ETH_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when + reset to the legacy weak function in the HAL_ETH_Init/ HAL_ETH_DeInit only when these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit + if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ HAL_ETH_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only. @@ -121,7 +163,7 @@ in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit + using HAL_ETH_RegisterCallback() before calling HAL_ETH_DeInit or HAL_ETH_Init function. When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or @@ -130,17 +172,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -182,14 +213,15 @@ ETH_MACPCSR_RWKPFE) /* Timeout values */ -#define ETH_SWRESET_TIMEOUT ((uint32_t)500U) -#define ETH_MDIO_BUS_TIMEOUT ((uint32_t)1000U) - #define ETH_DMARXNDESCWBF_ERRORS_MASK ((uint32_t)(ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \ ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\ ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE)) -#define ETH_MAC_US_TICK ((uint32_t)1000000U) +#define ETH_MACTSCR_MASK ((uint32_t)0x0087FF2FU) + +#define ETH_MACSTSUR_VALUE ((uint32_t)0xFFFFFFFFU) +#define ETH_MACSTNUR_VALUE ((uint32_t)0xBB9ACA00U) +#define ETH_SEGMENT_SIZE_DEFAULT ((uint32_t)0x218U) /** * @} */ @@ -200,17 +232,17 @@ */ /* Helper macros for TX descriptor handling */ #define INCR_TX_DESC_INDEX(inx, offset) do {\ - (inx) += (offset);\ - if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\ - (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\ -} while (0) + (inx) += (offset);\ + if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\ + (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\ + } while (0) /* Helper macros for RX descriptor handling */ #define INCR_RX_DESC_INDEX(inx, offset) do {\ - (inx) += (offset);\ - if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\ - (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\ -} while (0) + (inx) += (offset);\ + if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\ + (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\ + } while (0) /** * @} */ @@ -218,13 +250,13 @@ /** @defgroup ETH_Private_Functions ETH Private Functions * @{ */ -static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth); static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth); static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth); static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth); static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode); +static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth); #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth); @@ -259,9 +291,6 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth); (++) Tx DMA Descriptors Tab (++) Length of Rx Buffers - (+) Call the function HAL_ETH_DescAssignMemory() to assign data buffers - for each Rx DMA Descriptor - (+) Call the function HAL_ETH_DeInit() to restore the default configuration of the selected ETH peripheral. @@ -279,44 +308,35 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) { uint32_t tickstart; - if(heth == NULL) + if (heth == NULL) { return HAL_ERROR; } + if (heth->gState == HAL_ETH_STATE_RESET) + { + heth->gState = HAL_ETH_STATE_BUSY; #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - if(heth->gState == HAL_ETH_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - heth->Lock = HAL_UNLOCKED; - ETH_InitCallbacksToDefault(heth); - if(heth->MspInitCallback == NULL) + if (heth->MspInitCallback == NULL) { heth->MspInitCallback = HAL_ETH_MspInit; } /* Init the low level hardware */ heth->MspInitCallback(heth); - } - #else - - /* Check the ETH peripheral state */ - if(heth->gState == HAL_ETH_STATE_RESET) - { /* Init the low level hardware : GPIO, CLOCK, NVIC. */ HAL_ETH_MspInit(heth); - } -#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ - heth->gState = HAL_ETH_STATE_BUSY; +#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ + } __HAL_RCC_SYSCFG_CLK_ENABLE(); - if(heth->Init.MediaInterface == HAL_ETH_MII_MODE) + if (heth->Init.MediaInterface == HAL_ETH_MII_MODE) { HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII); } @@ -325,6 +345,9 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII); } + /* Dummy read to sync with ETH */ + (void)SYSCFG->PMCR; + /* Ethernet Software reset */ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ /* After reset all the registers holds their respective reset values */ @@ -336,7 +359,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) /* Wait for software reset */ while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U) { - if(((HAL_GetTick() - tickstart ) > ETH_SWRESET_TIMEOUT)) + if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT)) { /* Set Error Code */ heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT; @@ -348,7 +371,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) } /*------------------ MDIO CSR Clock Range Configuration --------------------*/ - ETH_MAC_MDIO_ClkConfig(heth); + HAL_ETH_SetMDIOClockRange(heth); /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/ WRITE_REG(heth->Instance->MAC1USTCR, (((uint32_t)HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1U)); @@ -389,7 +412,6 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) heth->ErrorCode = HAL_ETH_ERROR_NONE; heth->gState = HAL_ETH_STATE_READY; - heth->RxState = HAL_ETH_STATE_READY; return HAL_OK; } @@ -407,7 +429,7 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - if(heth->MspDeInitCallback == NULL) + if (heth->MspDeInitCallback == NULL) { heth->MspDeInitCallback = HAL_ETH_MspDeInit; } @@ -421,7 +443,7 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) #endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ /* Set ETH HAL state to Disabled */ - heth->gState= HAL_ETH_STATE_RESET; + heth->gState = HAL_ETH_STATE_RESET; /* Return function status */ return HAL_OK; @@ -466,8 +488,7 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) * This parameter can be one of the following values: * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID - * @arg @ref HAL_ETH_MAC_ERROR_CB_ID MAC Error Callback ID + * @arg @ref HAL_ETH_ERROR_CB_ID Error Callback ID * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID * @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID @@ -476,86 +497,81 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, + pETH_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* Update the error code */ heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(heth); - if(heth->gState == HAL_ETH_STATE_READY) + if (heth->gState == HAL_ETH_STATE_READY) { switch (CallbackID) { - case HAL_ETH_TX_COMPLETE_CB_ID : - heth->TxCpltCallback = pCallback; - break; - - case HAL_ETH_RX_COMPLETE_CB_ID : - heth->RxCpltCallback = pCallback; - break; - - case HAL_ETH_DMA_ERROR_CB_ID : - heth->DMAErrorCallback = pCallback; - break; - - case HAL_ETH_MAC_ERROR_CB_ID : - heth->MACErrorCallback = pCallback; - break; - - case HAL_ETH_PMT_CB_ID : - heth->PMTCallback = pCallback; - break; - - case HAL_ETH_EEE_CB_ID : - heth->EEECallback = pCallback; - break; - - case HAL_ETH_WAKEUP_CB_ID : - heth->WakeUpCallback = pCallback; - break; - - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = pCallback; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_ETH_TX_COMPLETE_CB_ID : + heth->TxCpltCallback = pCallback; + break; + + case HAL_ETH_RX_COMPLETE_CB_ID : + heth->RxCpltCallback = pCallback; + break; + + case HAL_ETH_ERROR_CB_ID : + heth->ErrorCallback = pCallback; + break; + + case HAL_ETH_PMT_CB_ID : + heth->PMTCallback = pCallback; + break; + + case HAL_ETH_EEE_CB_ID : + heth->EEECallback = pCallback; + break; + + case HAL_ETH_WAKEUP_CB_ID : + heth->WakeUpCallback = pCallback; + break; + + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = pCallback; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(heth->gState == HAL_ETH_STATE_RESET) + else if (heth->gState == HAL_ETH_STATE_RESET) { switch (CallbackID) { - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = pCallback; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = pCallback; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -566,9 +582,6 @@ HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(heth); - return status; } @@ -580,8 +593,7 @@ HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Call * This parameter can be one of the following values: * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID - * @arg @ref HAL_ETH_MAC_ERROR_CB_ID MAC Error Callback ID + * @arg @ref HAL_ETH_ERROR_CB_ID Error Callback ID * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID * @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID @@ -593,75 +605,68 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(heth); - - if(heth->gState == HAL_ETH_STATE_READY) + if (heth->gState == HAL_ETH_STATE_READY) { switch (CallbackID) { - case HAL_ETH_TX_COMPLETE_CB_ID : - heth->TxCpltCallback = HAL_ETH_TxCpltCallback; - break; - - case HAL_ETH_RX_COMPLETE_CB_ID : - heth->RxCpltCallback = HAL_ETH_RxCpltCallback; - break; - - case HAL_ETH_DMA_ERROR_CB_ID : - heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback; - break; - - case HAL_ETH_MAC_ERROR_CB_ID : - heth->MACErrorCallback = HAL_ETH_MACErrorCallback; - break; - - case HAL_ETH_PMT_CB_ID : - heth->PMTCallback = HAL_ETH_PMTCallback; - break; - - case HAL_ETH_EEE_CB_ID : - heth->EEECallback = HAL_ETH_EEECallback; - break; - - case HAL_ETH_WAKEUP_CB_ID : - heth->WakeUpCallback = HAL_ETH_WakeUpCallback; - break; - - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = HAL_ETH_MspInit; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = HAL_ETH_MspDeInit; - break; - - default : - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_ETH_TX_COMPLETE_CB_ID : + heth->TxCpltCallback = HAL_ETH_TxCpltCallback; + break; + + case HAL_ETH_RX_COMPLETE_CB_ID : + heth->RxCpltCallback = HAL_ETH_RxCpltCallback; + break; + + case HAL_ETH_ERROR_CB_ID : + heth->ErrorCallback = HAL_ETH_ErrorCallback; + break; + + case HAL_ETH_PMT_CB_ID : + heth->PMTCallback = HAL_ETH_PMTCallback; + break; + + case HAL_ETH_EEE_CB_ID : + heth->EEECallback = HAL_ETH_EEECallback; + break; + + case HAL_ETH_WAKEUP_CB_ID : + heth->WakeUpCallback = HAL_ETH_WakeUpCallback; + break; + + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = HAL_ETH_MspInit; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(heth->gState == HAL_ETH_STATE_RESET) + else if (heth->gState == HAL_ETH_STATE_RESET) { switch (CallbackID) { - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = HAL_ETH_MspInit; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = HAL_ETH_MspDeInit; - break; - - default : - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = HAL_ETH_MspInit; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -672,57 +677,10 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(heth); - return status; } #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ -/** - * @brief Assign memory buffers to a DMA Rx descriptor - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param Index : index of the DMA Rx descriptor - * this parameter can be a value from 0x0 to (ETH_RX_DESC_CNT -1) - * @param pBuffer1: address of buffer 1 - * @param pBuffer2: address of buffer 2 if available - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1, uint8_t *pBuffer2) -{ - ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[Index]; - - if((pBuffer1 == NULL) || (Index >= (uint32_t)ETH_RX_DESC_CNT)) - { - /* Set Error Code */ - heth->ErrorCode = HAL_ETH_ERROR_PARAM; - /* Return Error */ - return HAL_ERROR; - } - - /* write buffer address to RDES0 */ - WRITE_REG(dmarxdesc->DESC0, (uint32_t)pBuffer1); - /* store buffer address */ - WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)pBuffer1); - /* set buffer address valid bit to RDES3 */ - SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V); - - if(pBuffer2 != NULL) - { - /* write buffer 2 address to RDES1 */ - WRITE_REG(dmarxdesc->DESC2, (uint32_t)pBuffer2); - /* store buffer 2 address */ - WRITE_REG(dmarxdesc->BackupAddr1, (uint32_t)pBuffer2); - /* set buffer 2 address valid bit to RDES3 */ - SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V); - } - /* set OWN bit to RDES3 */ - SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN); - - return HAL_OK; -} - /** * @} */ @@ -750,10 +708,16 @@ HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Ind */ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) { - if(heth->gState == HAL_ETH_STATE_READY) + if (heth->gState == HAL_ETH_STATE_READY) { heth->gState = HAL_ETH_STATE_BUSY; + /* Set nombre of descriptors to build */ + heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; + + /* Build all descriptors */ + ETH_UpdateDescriptor(heth); + /* Enable the MAC transmission */ SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); @@ -772,8 +736,7 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) /* Clear Tx and Rx process stopped flags */ heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS); - heth->gState = HAL_ETH_STATE_READY; - heth->RxState = HAL_ETH_STATE_BUSY_RX; + heth->gState = HAL_ETH_STATE_STARTED; return HAL_OK; } @@ -791,23 +754,25 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) */ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth) { - uint32_t descindex; - - ETH_DMADescTypeDef *dmarxdesc; - - if(heth->gState == HAL_ETH_STATE_READY) + if (heth->gState == HAL_ETH_STATE_READY) { heth->gState = HAL_ETH_STATE_BUSY; - /* Set IOC bit to all Rx descriptors */ - for(descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++) - { - dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex]; - SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC); - } - /* save IT mode to ETH Handle */ heth->RxDescList.ItMode = 1U; + /* Disable Rx MMC Interrupts */ + SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \ + ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM); + + /* Disable Tx MMC Interrupts */ + SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \ + ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM); + + /* Set nombre of descriptors to build */ + heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; + + /* Build all descriptors */ + ETH_UpdateDescriptor(heth); /* Enable the MAC transmission */ SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); @@ -833,11 +798,9 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth) - Fatal bus interrupt */ __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE | - ETH_DMACIER_FBEE | ETH_DMACIER_AIE)); - - heth->gState = HAL_ETH_STATE_READY; - heth->RxState = HAL_ETH_STATE_BUSY_RX; + ETH_DMACIER_FBEE | ETH_DMACIER_AIE | ETH_DMACIER_RBUE)); + heth->gState = HAL_ETH_STATE_STARTED; return HAL_OK; } else @@ -854,11 +817,10 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth) */ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) { - if(heth->gState != HAL_ETH_STATE_RESET) + if (heth->gState == HAL_ETH_STATE_STARTED) { - /* Set the ETH peripheral state to BUSY */ + /* Set the ETH peripheral state to BUSY */ heth->gState = HAL_ETH_STATE_BUSY; - /* Disable the DMA transmission */ CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST); @@ -866,7 +828,7 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR); /* Disable the MAC reception */ - CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE); + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); /* Set the Flush Transmit FIFO bit */ SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ); @@ -875,7 +837,6 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); heth->gState = HAL_ETH_STATE_READY; - heth->RxState = HAL_ETH_STATE_READY; /* Return function status */ return HAL_OK; @@ -897,7 +858,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) ETH_DMADescTypeDef *dmarxdesc; uint32_t descindex; - if(heth->gState != HAL_ETH_STATE_RESET) + if (heth->gState == HAL_ETH_STATE_STARTED) { /* Set the ETH peripheral state to BUSY */ heth->gState = HAL_ETH_STATE_BUSY; @@ -908,7 +869,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) - Fatal bus interrupt */ __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE | - ETH_DMACIER_FBEE | ETH_DMACIER_AIE)); + ETH_DMACIER_FBEE | ETH_DMACIER_AIE | ETH_DMACIER_RBUE)); /* Disable the DMA transmission */ CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST); @@ -917,8 +878,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR); /* Disable the MAC reception */ - CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE); - + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); /* Set the Flush Transmit FIFO bit */ SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ); @@ -926,7 +886,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); /* Clear IOC bit to all Rx descriptors */ - for(descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++) + for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++) { dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex]; CLEAR_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC); @@ -935,7 +895,6 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) heth->RxDescList.ItMode = 0U; heth->gState = HAL_ETH_STATE_READY; - heth->RxState = HAL_ETH_STATE_READY; /* Return function status */ return HAL_OK; @@ -957,15 +916,15 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout) { uint32_t tickstart; - const ETH_DMADescTypeDef *dmatxdesc; + ETH_DMADescTypeDef *dmatxdesc; - if(pTxConfig == NULL) + if (pTxConfig == NULL) { heth->ErrorCode |= HAL_ETH_ERROR_PARAM; return HAL_ERROR; } - if(heth->gState == HAL_ETH_STATE_READY) + if (heth->gState == HAL_ETH_STATE_STARTED) { /* Config DMA Tx descriptor by Tx Packet info */ if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE) @@ -975,6 +934,9 @@ HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig * return HAL_ERROR; } + /* Ensure completion of descriptor preparation before transmission start */ + __DSB(); + dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc]; /* Incr current tx desc index */ @@ -987,25 +949,24 @@ HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig * tickstart = HAL_GetTick(); /* Wait for data to be transmitted or timeout occurred */ - while((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET) + while ((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET) { - if((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET) + if ((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET) { heth->ErrorCode |= HAL_ETH_ERROR_DMA; heth->DMAErrorCode = heth->Instance->DMACSR; - /* Set ETH HAL State to Ready */ - heth->gState = HAL_ETH_STATE_ERROR; /* Return function status */ return HAL_ERROR; } /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT; - heth->gState = HAL_ETH_STATE_ERROR; + /* Clear TX descriptor so that we can proceed */ + dmatxdesc->DESC3 = (ETH_DMATXNDESCWBF_FD | ETH_DMATXNDESCWBF_LD); return HAL_ERROR; } } @@ -1029,14 +990,17 @@ HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig * */ HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig) { - if(pTxConfig == NULL) + if (pTxConfig == NULL) { heth->ErrorCode |= HAL_ETH_ERROR_PARAM; return HAL_ERROR; } - if(heth->gState == HAL_ETH_STATE_READY) + if (heth->gState == HAL_ETH_STATE_STARTED) { + /* Save the packet pointer to release. */ + heth->TxDescList.CurrentPacketAddress = (uint32_t *)pTxConfig->pData; + /* Config DMA Tx descriptor by Tx Packet info */ if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE) { @@ -1044,6 +1008,9 @@ HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfi return HAL_ERROR; } + /* Ensure completion of descriptor preparation before transmission start */ + __DSB(); + /* Incr current tx desc index */ INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U); @@ -1061,410 +1028,800 @@ HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfi } /** - * @brief Checks for received Packets. + * @brief Read a received packet. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @retval 1: A Packet is received - * 0: no Packet received + * @param pAppBuff: Pointer to an application buffer to receive the packet. + * @retval HAL status */ -uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth) +HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) { - ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList; - uint32_t descidx = dmarxdesclist->CurRxDesc; - ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx]; - uint32_t descscancnt = 0; - uint32_t appdesccnt = 0, firstappdescidx = 0; + uint32_t descidx; + ETH_DMADescTypeDef *dmarxdesc; + uint32_t desccnt = 0U; + uint32_t desccntmax; + uint32_t bufflength; + uint8_t rxdataready = 0U; - if(dmarxdesclist->AppDescNbr != 0U) + + if (pAppBuff == NULL) { - /* data already received by not yet processed*/ - return 0; + heth->ErrorCode |= HAL_ETH_ERROR_PARAM; + return HAL_ERROR; } - /* Check if descriptor is not owned by DMA */ - while((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (descscancnt < (uint32_t)ETH_RX_DESC_CNT)) + if (heth->gState != HAL_ETH_STATE_STARTED) { - descscancnt++; + return HAL_ERROR; + } - /* Check if last descriptor */ - if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET) - { - /* Increment the number of descriptors to be passed to the application */ - appdesccnt += 1U; + descidx = heth->RxDescList.RxDescIdx; + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccntmax = ETH_RX_DESC_CNT - heth->RxDescList.RxBuildDescCnt; - if(appdesccnt == 1U) + /* Check if descriptor is not owned by DMA */ + while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax) + && (rxdataready == 0U)) + { + if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_CTXT) != (uint32_t)RESET) + { + /* Get timestamp high */ + heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC1; + /* Get timestamp low */ + heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC0; + } + if ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL)) + { + /* Check if first descriptor */ + if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) { - WRITE_REG(firstappdescidx, descidx); + heth->RxDescList.RxDescCnt = 0; + heth->RxDescList.RxDataLength = 0; } - /* Increment current rx descriptor index */ - INCR_RX_DESC_INDEX(descidx, 1U); + /* Check if last descriptor */ + bufflength = heth->Init.RxBuffLen; + if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET) + { + bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength; - /* Check for Context descriptor */ - /* Get current descriptor address */ - dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx]; + /* Save Last descriptor index */ + heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC3; - if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) - { - if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_CTXT) != (uint32_t)RESET) - { - /* Increment the number of descriptors to be passed to the application */ - dmarxdesclist->AppContextDesc = 1; - /* Increment current rx descriptor index */ - INCR_RX_DESC_INDEX(descidx, 1U); - } + /* Packet ready */ + rxdataready = 1; } - /* Fill information to Rx descriptors list */ - dmarxdesclist->CurRxDesc = descidx; - dmarxdesclist->FirstAppDesc = firstappdescidx; - dmarxdesclist->AppDescNbr = appdesccnt; - /* Return function status */ - return 1; + /* Link data */ +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Link callback*/ + heth->rxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + (uint8_t *)dmarxdesc->BackupAddr0, bufflength); +#else + /* Link callback */ + HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + heth->RxDescList.RxDescCnt++; + heth->RxDescList.RxDataLength += bufflength; + + /* Clear buffer pointer */ + dmarxdesc->BackupAddr0 = 0; } - /* Check if first descriptor */ - else if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) - { - WRITE_REG(firstappdescidx, descidx); - /* Increment the number of descriptors to be passed to the application */ - appdesccnt = 1U; - /* Increment current rx descriptor index */ - INCR_RX_DESC_INDEX(descidx, 1U); - /* Get current descriptor address */ - dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx]; + /* Increment current rx descriptor index */ + INCR_RX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccnt++; + } + + heth->RxDescList.RxBuildDescCnt += desccnt; + if ((heth->RxDescList.RxBuildDescCnt) != 0U) + { + /* Update Descriptors */ + ETH_UpdateDescriptor(heth); + } + + heth->RxDescList.RxDescIdx = descidx; + + if (rxdataready == 1U) + { + /* Return received packet */ + *pAppBuff = heth->RxDescList.pRxStart; + /* Reset first element */ + heth->RxDescList.pRxStart = NULL; + + return HAL_OK; + } + + /* Packet not ready */ + return HAL_ERROR; +} + +/** + * @brief This function gives back Rx Desc of the last received Packet + * to the DMA, so ETH DMA will be able to use these descriptors + * to receive next Packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) +{ + uint32_t descidx; + uint32_t desccount; + ETH_DMADescTypeDef *dmarxdesc; + uint8_t *buff = NULL; + uint8_t allocStatus = 1U; + + descidx = heth->RxDescList.RxBuildDescIdx; + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccount = heth->RxDescList.RxBuildDescCnt; + + while ((desccount > 0U) && (allocStatus != 0U)) + { + /* Check if a buffer's attached the descriptor */ + if (READ_REG(dmarxdesc->BackupAddr0) == 0U) + { + /* Get a new buffer. */ +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Allocate callback*/ + heth->rxAllocateCallback(&buff); +#else + /* Allocate callback */ + HAL_ETH_RxAllocateCallback(&buff); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + if (buff == NULL) + { + allocStatus = 0U; + } + else + { + WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)buff); + WRITE_REG(dmarxdesc->DESC0, (uint32_t)buff); + } } - /* It should be an intermediate descriptor */ - else + + if (allocStatus != 0U) { - /* Increment the number of descriptors to be passed to the application */ - appdesccnt += 1U; + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + + if (heth->RxDescList.ItMode != 0U) + { + WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V | ETH_DMARXNDESCRF_IOC); + } + else + { + WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V); + } /* Increment current rx descriptor index */ INCR_RX_DESC_INDEX(descidx, 1U); /* Get current descriptor address */ - dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx]; + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccount--; } } - /* Build Descriptors if an incomplete Packet is received */ - if(appdesccnt > 0U) + if (heth->RxDescList.RxBuildDescCnt != desccount) + { + /* Set the Tail pointer address */ + WRITE_REG(heth->Instance->DMACRDTPR, 0); + + heth->RxDescList.RxBuildDescIdx = descidx; + heth->RxDescList.RxBuildDescCnt = desccount; + } +} + +/** + * @brief Register the Rx alloc callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param rxAllocateCallback: pointer to function to alloc buffer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, + pETH_rxAllocateCallbackTypeDef rxAllocateCallback) +{ + if (rxAllocateCallback == NULL) { - dmarxdesclist->CurRxDesc = descidx; - dmarxdesclist->FirstAppDesc = firstappdescidx; - descidx = firstappdescidx; - dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx]; + /* No buffer to save */ + return HAL_ERROR; + } + + /* Set function to allocate buffer */ + heth->rxAllocateCallback = rxAllocateCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Rx alloc callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback; + + return HAL_OK; +} + +/** + * @brief Rx Allocate callback. + * @param buff: pointer to allocated buffer + * @retval None + */ +__weak void HAL_ETH_RxAllocateCallback(uint8_t **buff) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(buff); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_RxAllocateCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Link callback. + * @param pStart: pointer to packet start + * @param pStart: pointer to packet end + * @param buff: pointer to received data + * @param Length: received data length + * @retval None + */ +__weak void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(pStart); + UNUSED(pEnd); + UNUSED(buff); + UNUSED(Length); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_RxLinkCallback could be implemented in the user file + */ +} + +/** + * @brief Set the Rx link data function. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param rxLinkCallback: pointer to function to link data + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback) +{ + if (rxLinkCallback == NULL) + { + /* No buffer to save */ + return HAL_ERROR; + } + + /* Set function to link data */ + heth->rxLinkCallback = rxLinkCallback; + + return HAL_OK; +} - for(descscancnt = 0; descscancnt < appdesccnt; descscancnt++) +/** + * @brief Unregister the Rx link callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->rxLinkCallback = HAL_ETH_RxLinkCallback; + + return HAL_OK; +} + +/** + * @brief Get the error state of the last received packet. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pErrorCode: pointer to uint32_t to hold the error code + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode) +{ + /* Get error bits. */ + *pErrorCode = READ_BIT(heth->RxDescList.pRxLastRxDesc, ETH_DMARXNDESCWBF_ERRORS_MASK); + + return HAL_OK; +} + +/** + * @brief Set the Tx free function. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param txFreeCallback: pointer to function to release the packet + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback) +{ + if (txFreeCallback == NULL) + { + /* No buffer to save */ + return HAL_ERROR; + } + + /* Set function to free transmmitted packet */ + heth->txFreeCallback = txFreeCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Tx free callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->txFreeCallback = HAL_ETH_TxFreeCallback; + + return HAL_OK; +} + +/** + * @brief Tx Free callback. + * @param buff: pointer to buffer to free + * @retval None + */ +__weak void HAL_ETH_TxFreeCallback(uint32_t *buff) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(buff); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxFreeCallback could be implemented in the user file + */ +} + +/** + * @brief Release transmitted Tx packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t numOfBuf = dmatxdesclist->BuffersInUse; + uint32_t idx = dmatxdesclist->releaseIndex; + uint8_t pktTxStatus = 1U; + uint8_t pktInUse; +#ifdef HAL_ETH_USE_PTP + ETH_TimeStampTypeDef *timestamp = &heth->TxTimestamp; +#endif /* HAL_ETH_USE_PTP */ + + /* Loop through buffers in use. */ + while ((numOfBuf != 0U) && (pktTxStatus != 0U)) + { + pktInUse = 1U; + numOfBuf--; + /* If no packet, just examine the next packet. */ + if (dmatxdesclist->PacketAddress[idx] == NULL) { - WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0); - WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V); + /* No packet in use, skip to next. */ + idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U); + pktInUse = 0U; + } - if (READ_REG(dmarxdesc->BackupAddr1) != ((uint32_t)RESET)) + if (pktInUse != 0U) + { + /* Determine if the packet has been transmitted. */ + if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCRF_OWN) == 0U) { - WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1); - SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V); - } +#ifdef HAL_ETH_USE_PTP + /* Disable Ptp transmission */ + CLEAR_BIT(heth->Init.TxDesc[idx].DESC3, ((uint32_t)0x40000000U)); - SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN); + /* Get timestamp low */ + timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC0; + /* Get timestamp high */ + timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC1; +#endif /* HAL_ETH_USE_PTP */ - if(dmarxdesclist->ItMode != ((uint32_t)RESET)) - { - SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC); +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered callbacks*/ +#ifdef HAL_ETH_USE_PTP + /* Handle Ptp */ + heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); +#endif /* HAL_ETH_USE_PTP */ + /* Release the packet. */ + heth->txFreeCallback(dmatxdesclist->PacketAddress[idx]); +#else + /* Call callbacks */ +#ifdef HAL_ETH_USE_PTP + /* Handle Ptp */ + HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); +#endif /* HAL_ETH_USE_PTP */ + /* Release the packet. */ + HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Clear the entry in the in-use array. */ + dmatxdesclist->PacketAddress[idx] = NULL; + + /* Update the transmit relesae index and number of buffers in use. */ + idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U); + dmatxdesclist->BuffersInUse = numOfBuf; + dmatxdesclist->releaseIndex = idx; } - if(descscancnt < (appdesccnt - 1U)) + else { - /* Increment rx descriptor index */ - INCR_RX_DESC_INDEX(descidx, 1U); - /* Get descriptor address */ - dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx]; + /* Get out of the loop! */ + pktTxStatus = 0U; } } - - /* Set the Tail pointer address to the last rx descriptor hold by the app */ - WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc); } - - /* Fill information to Rx descriptors list: No received Packet */ - dmarxdesclist->AppDescNbr = 0U; - - return 0; + return HAL_OK; } +#ifdef HAL_ETH_USE_PTP /** - * @brief This function gets the buffer address of last received Packet. - * @note Please insure to allocate the RxBuffer structure before calling this function - * how to use example: - * HAL_ETH_GetRxDataLength(heth, &Length); - * BuffersNbr = (Length / heth->Init.RxBuffLen) + 1; - * RxBuffer = (ETH_BufferTypeDef *)malloc(BuffersNbr * sizeof(ETH_BufferTypeDef)); - * HAL_ETH_GetRxDataBuffer(heth, RxBuffer); + * @brief Set the Ethernet PTP configuration. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param RxBuffer: Pointer to a ETH_BufferTypeDef structure + * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains + * the configuration information for PTP * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer) +HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig) { - ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList; - uint32_t descidx = dmarxdesclist->FirstAppDesc; - uint32_t index, accumulatedlen = 0, lastdesclen; - __IO const ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx]; - ETH_BufferTypeDef *rxbuff = RxBuffer; + uint32_t tmpTSCR; + ETH_TimeTypeDef time; - if(rxbuff == NULL) + if (ptpconfig == NULL) { - heth->ErrorCode = HAL_ETH_ERROR_PARAM; return HAL_ERROR; } - if(dmarxdesclist->AppDescNbr == 0U) + tmpTSCR = ptpconfig->Timestamp | + ((uint32_t)ptpconfig->TimestampUpdate << ETH_MACTSCR_TSUPDT_Pos) | + ((uint32_t)ptpconfig->TimestampAll << ETH_MACTSCR_TSENALL_Pos) | + ((uint32_t)ptpconfig->TimestampRolloverMode << ETH_MACTSCR_TSCTRLSSR_Pos) | + ((uint32_t)ptpconfig->TimestampV2 << ETH_MACTSCR_TSVER2ENA_Pos) | + ((uint32_t)ptpconfig->TimestampEthernet << ETH_MACTSCR_TSIPENA_Pos) | + ((uint32_t)ptpconfig->TimestampIPv6 << ETH_MACTSCR_TSIPV6ENA_Pos) | + ((uint32_t)ptpconfig->TimestampIPv4 << ETH_MACTSCR_TSIPV4ENA_Pos) | + ((uint32_t)ptpconfig->TimestampEvent << ETH_MACTSCR_TSEVNTENA_Pos) | + ((uint32_t)ptpconfig->TimestampMaster << ETH_MACTSCR_TSMSTRENA_Pos) | + ((uint32_t)ptpconfig->TimestampSnapshots << ETH_MACTSCR_SNAPTYPSEL_Pos) | + ((uint32_t)ptpconfig->TimestampFilter << ETH_MACTSCR_TSENMACADDR_Pos) | + ((uint32_t)ptpconfig->TimestampChecksumCorrection << ETH_MACTSCR_CSC_Pos) | + ((uint32_t)ptpconfig->TimestampStatusMode << ETH_MACTSCR_TXTSSTSM_Pos); + + /* Write to MACTSCR */ + MODIFY_REG(heth->Instance->MACTSCR, ETH_MACTSCR_MASK, tmpTSCR); + + /* Enable Timestamp */ + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSENA); + WRITE_REG(heth->Instance->MACSSIR, ptpconfig->TimestampSubsecondInc); + WRITE_REG(heth->Instance->MACTSAR, ptpconfig->TimestampAddend); + + /* Enable Timestamp */ + if (ptpconfig->TimestampAddendUpdate == ENABLE) { - if(HAL_ETH_IsRxDataAvailable(heth) == 0U) - { - /* No data to be transferred to the application */ - return HAL_ERROR; - } - else - { - descidx = dmarxdesclist->FirstAppDesc; - dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx]; - } + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSADDREG); + while ((heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG) != 0) {} } - /* Get intermediate descriptors buffers: in case of the Packet is split into multi descriptors */ - for(index = 0; index < (dmarxdesclist->AppDescNbr - 1U); index++) + /* Enable Update mode */ + if (ptpconfig->TimestampUpdateMode == ENABLE) { - /* Get Address and length of the first buffer address */ - rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0; - rxbuff->len = heth->Init.RxBuffLen; - - /* Check if the second buffer address of this descriptor is valid */ - if(dmarxdesc->BackupAddr1 != 0U) - { - /* Point to next buffer */ - rxbuff = rxbuff->next; - /* Get Address and length of the second buffer address */ - rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1; - rxbuff->len = heth->Init.RxBuffLen; - } - else - { - /* Nothing to do here */ - } - - /* get total length until this descriptor */ - accumulatedlen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL); + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCFUPDT); + } - /* Increment to next descriptor */ - INCR_RX_DESC_INDEX(descidx, 1U); - dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx]; + /* Initialize Time */ + time.Seconds = 0; + time.NanoSeconds = 0; + HAL_ETH_PTP_SetTime(heth, &time); - /* Point to next buffer */ - rxbuff = rxbuff->next; - } + /* Ptp Init */ + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT); - /* last descriptor data length */ - lastdesclen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - accumulatedlen; + /* Set PTP Configuration done */ + heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURATED; - /* Get Address of the first buffer address */ - rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0; + /* Return function status */ + return HAL_OK; +} - /* data is in only one buffer */ - if(lastdesclen <= heth->Init.RxBuffLen) - { - rxbuff->len = lastdesclen; - } - /* data is in two buffers */ - else if(dmarxdesc->BackupAddr1 != 0U) - { - /* Get the Length of the first buffer address */ - rxbuff->len = heth->Init.RxBuffLen; - /* Point to next buffer */ - rxbuff = rxbuff->next; - /* Get the Address the Length of the second buffer address */ - rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1; - rxbuff->len = lastdesclen - (heth->Init.RxBuffLen); - } - else /* Buffer 2 not valid*/ +/** + * @brief Get the Ethernet PTP configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains + * the configuration information for PTP + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig) +{ + if (ptpconfig == NULL) { return HAL_ERROR; } + ptpconfig->Timestamp = READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSENA); + ptpconfig->TimestampUpdate = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSCFUPDT) >> ETH_MACTSCR_TSUPDT_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampAll = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSENALL) >> ETH_MACTSCR_TSENALL_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampRolloverMode = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSCTRLSSR) >> ETH_MACTSCR_TSCTRLSSR_Pos) > 0U) + ? ENABLE : DISABLE; + ptpconfig->TimestampV2 = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSVER2ENA) >> ETH_MACTSCR_TSVER2ENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampEthernet = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSIPENA) >> ETH_MACTSCR_TSIPENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampIPv6 = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSIPV6ENA) >> ETH_MACTSCR_TSIPV6ENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampIPv4 = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSIPV4ENA) >> ETH_MACTSCR_TSIPV4ENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampEvent = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSEVNTENA) >> ETH_MACTSCR_TSEVNTENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampMaster = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSMSTRENA) >> ETH_MACTSCR_TSMSTRENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampSnapshots = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_SNAPTYPSEL) >> ETH_MACTSCR_SNAPTYPSEL_Pos) > 0U) + ? ENABLE : DISABLE; + ptpconfig->TimestampFilter = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSENMACADDR) >> ETH_MACTSCR_TSENMACADDR_Pos) > 0U) + ? ENABLE : DISABLE; + ptpconfig->TimestampChecksumCorrection = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_CSC) >> ETH_MACTSCR_CSC_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampStatusMode = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TXTSSTSM) >> ETH_MACTSCR_TXTSSTSM_Pos) > 0U) + ? ENABLE : DISABLE; + /* Return function status */ return HAL_OK; } /** - * @brief This function gets the length of last received Packet. + * @brief Set Seconds and Nanoseconds for the Ethernet PTP registers. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param Length: parameter to hold Rx packet length - * @retval HAL Status + * @param heth: pointer to a ETH_TimeTypeDef structure that contains + * time to set + * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length) +HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time) { - ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList; - uint32_t descidx = dmarxdesclist->FirstAppDesc; - __IO const ETH_DMADescTypeDef *dmarxdesc; - - if(dmarxdesclist->AppDescNbr == 0U) + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) { - if(HAL_ETH_IsRxDataAvailable(heth) == 0U) - { - /* No data to be transferred to the application */ - return HAL_ERROR; - } - } - - /* Get index of last descriptor */ - INCR_RX_DESC_INDEX(descidx, (dmarxdesclist->AppDescNbr - 1U)); - /* Point to last descriptor */ - dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx]; + /* Set Seconds */ + heth->Instance->MACSTSUR = time->Seconds; - *Length = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL); + /* Set NanoSeconds */ + heth->Instance->MACSTNUR = time->NanoSeconds; - return HAL_OK; + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } } /** - * @brief Get the Rx data info (Packet type, VLAN tag, Filters status, ...) + * @brief Get Seconds and Nanoseconds for the Ethernet PTP registers. * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param RxPacketInfo: parameter to hold info of received buffer + * @param heth: pointer to a ETH_TimeTypeDef structure that contains + * time to get * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo) +HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time) { - ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList; - uint32_t descidx = dmarxdesclist->FirstAppDesc; - __IO const ETH_DMADescTypeDef *dmarxdesc; - - if(dmarxdesclist->AppDescNbr == 0U) + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) { - if(HAL_ETH_IsRxDataAvailable(heth) == 0U) - { - /* No data to be transferred to the application */ - return HAL_ERROR; - } - } + /* Get Seconds */ + time->Seconds = heth->Instance->MACSTSUR; - /* Get index of last descriptor */ - INCR_RX_DESC_INDEX(descidx, ((dmarxdesclist->AppDescNbr) - 1U)); - /* Point to last descriptor */ - dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx]; + /* Get NanoSeconds */ + time->NanoSeconds = heth->Instance->MACSTNUR; - if((dmarxdesc->DESC3 & ETH_DMARXNDESCWBF_ES) != (uint32_t)RESET) - { - RxPacketInfo->ErrorCode = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_ERRORS_MASK); + /* Return function status */ + return HAL_OK; } else { - if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS0V) != 0U) + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Update time for the Ethernet PTP registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timeupdate: pointer to a ETH_TIMEUPDATETypeDef structure that contains + * the time update information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, + ETH_TimeTypeDef *timeoffset) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + if (ptpoffsettype == HAL_ETH_PTP_NEGATIVE_UPDATE) { + /* Set Seconds update */ + heth->Instance->MACSTSUR = ETH_MACSTSUR_VALUE - timeoffset->Seconds + 1U; - if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LT) == ETH_DMARXNDESCWBF_LT_DVLAN) + if (READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCTRLSSR) == ETH_MACTSCR_TSCTRLSSR) { - RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT); - RxPacketInfo->InnerVlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_IVT) >> 16; + /* Set nanoSeconds update */ + heth->Instance->MACSTNUR = ETH_MACSTNUR_VALUE - timeoffset->NanoSeconds; } else { - RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT); + /* Set nanoSeconds update */ + heth->Instance->MACSTNUR = ETH_MACSTSUR_VALUE - timeoffset->NanoSeconds + 1U; } } - - if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS1V) != 0U) + else { - /* Get Payload type */ - RxPacketInfo->PayloadType =READ_BIT( dmarxdesc->DESC1, ETH_DMARXNDESCWBF_PT); - /* Get Header type */ - RxPacketInfo->HeaderType = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPV4 | ETH_DMARXNDESCWBF_IPV6)); - /* Get Checksum status */ - RxPacketInfo->Checksum = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPCE | ETH_DMARXNDESCWBF_IPCB | ETH_DMARXNDESCWBF_IPHE)); + /* Set Seconds update */ + heth->Instance->MACSTSUR = timeoffset->Seconds; + /* Set nanoSeconds update */ + heth->Instance->MACSTNUR = timeoffset->NanoSeconds; } - if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS2V) != 0U) - { - RxPacketInfo->MacFilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_HF | ETH_DMARXNDESCWBF_DAF | ETH_DMARXNDESCWBF_SAF | ETH_DMARXNDESCWBF_VF)); - RxPacketInfo->L3FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)); - RxPacketInfo->L4FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)); - } + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; } - - /* Get the segment count */ - WRITE_REG(RxPacketInfo->SegmentCnt, dmarxdesclist->AppDescNbr); - - return HAL_OK; } /** -* @brief This function gives back Rx Desc of the last received Packet -* to the DMA, so ETH DMA will be able to use these descriptors -* to receive next Packets. -* It should be called after processing the received Packet. -* @param heth: pointer to a ETH_HandleTypeDef structure that contains -* the configuration information for ETHERNET module -* @retval HAL status. -*/ -HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth) + * @brief Insert Timestamp in transmission. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param txtimestampconf: Enable or Disable timestamp in transmission + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth) { - ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList; - uint32_t descindex = dmarxdesclist->FirstAppDesc; - __IO ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex]; - uint32_t totalappdescnbr = dmarxdesclist->AppDescNbr; - uint32_t descscan; + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t descidx = dmatxdesclist->CurTxDesc; + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; - if(dmarxdesclist->AppDescNbr == 0U) + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) { - /* No Rx descriptors to build */ - return HAL_ERROR; - } + /* Enable Time Stamp transmission */ + SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_TTSE); - if(dmarxdesclist->AppContextDesc != 0U) + /* Return function status */ + return HAL_OK; + } + else { - /* A context descriptor is available */ - totalappdescnbr += 1U; + /* Return function status */ + return HAL_ERROR; } +} - for(descscan =0; descscan < totalappdescnbr; descscan++) - { - WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0); - WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V); +/** + * @brief Get transmission timestamp. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains + * transmission timestamp + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t idx = dmatxdesclist->releaseIndex; + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[idx]; - if (READ_REG(dmarxdesc->BackupAddr1) != 0U) - { - WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1); - SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V); - } + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + /* Get timestamp low */ + timestamp->TimeStampLow = dmatxdesc->DESC0; + /* Get timestamp high */ + timestamp->TimeStampHigh = dmatxdesc->DESC1; - SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN); + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} - if(dmarxdesclist->ItMode != 0U) - { - SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC); - } +/** + * @brief Get receive timestamp. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains + * receive timestamp + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + /* Get timestamp low */ + timestamp->TimeStampLow = heth->RxDescList.TimeStamp.TimeStampLow; + /* Get timestamp high */ + timestamp->TimeStampHigh = heth->RxDescList.TimeStamp.TimeStampHigh; - if(descscan < (totalappdescnbr - 1U)) - { - /* Increment rx descriptor index */ - INCR_RX_DESC_INDEX(descindex, 1U); - /* Get descriptor address */ - dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex]; - } + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; } +} - /* Set the Tail pointer address to the last rx descriptor hold by the app */ - WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc); +/** + * @brief Register the Tx Ptp callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param txPtpCallback: Function to handle Ptp transmission + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback) +{ + if (txPtpCallback == NULL) + { + /* No buffer to save */ + return HAL_ERROR; + } + /* Set Function to handle Tx Ptp */ + heth->txPtpCallback = txPtpCallback; - /* reset the Application desc number */ - WRITE_REG(dmarxdesclist->AppDescNbr, 0); + return HAL_OK; +} - /* reset the application context descriptor */ - WRITE_REG(heth->RxDescList.AppContextDesc, 0); +/** + * @brief Unregister the Tx Ptp callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->txPtpCallback = HAL_ETH_TxPtpCallback; return HAL_OK; } +/** + * @brief Tx Ptp callback. + * @param buff: pointer to application buffer + * @retval None + */ +__weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(buff); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxPtpCallback could be implemented in the user file + */ +} +#endif /* HAL_ETH_USE_PTP */ /** * @brief This function handles ETH interrupt request. @@ -1474,11 +1831,14 @@ HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth) */ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) { + uint32_t macirqenable; /* Packet received */ if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI)) { - if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE)) + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE)) { + /* Clear the Eth DMA Rx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS); #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) /*Call registered Receive complete callback*/ @@ -1487,35 +1847,32 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) /* Receive complete callback */ HAL_ETH_RxCpltCallback(heth); #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - /* Clear the Eth DMA Rx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS); } } /* Packet transmitted */ if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI)) { - if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE)) + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE)) { + /* Clear the Eth DMA Tx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS); + #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /*Call registered Transmit complete callback*/ - heth->TxCpltCallback(heth); + /*Call registered Transmit complete callback*/ + heth->TxCpltCallback(heth); #else /* Transfer complete callback */ HAL_ETH_TxCpltCallback(heth); #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - /* Clear the Eth DMA Tx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS); } } /* ETH DMA Error */ - if(__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS)) + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS)) { - if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE)) + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE)) { heth->ErrorCode |= HAL_ETH_ERROR_DMA; @@ -1534,45 +1891,49 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) else { /* Get DMA error status */ - heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | - ETH_DMACSR_RBU | ETH_DMACSR_AIS)); + heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | + ETH_DMACSR_RBU | ETH_DMACSR_AIS)); /* Clear the interrupt summary flag */ __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | - ETH_DMACSR_RBU | ETH_DMACSR_AIS)); + ETH_DMACSR_RBU | ETH_DMACSR_AIS)); } #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /* Call registered DMA Error callback*/ - heth->DMAErrorCallback(heth); + /* Call registered Error callback*/ + heth->ErrorCallback(heth); #else /* Ethernet DMA Error callback */ - HAL_ETH_DMAErrorCallback(heth); + HAL_ETH_ErrorCallback(heth); #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ } } /* ETH MAC Error IT */ - if(__HAL_ETH_MAC_GET_IT(heth, (ETH_MACIER_RXSTSIE | ETH_MACIER_TXSTSIE))) + macirqenable = heth->Instance->MACIER; + if (((macirqenable & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \ + ((macirqenable & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE)) { + heth->ErrorCode |= HAL_ETH_ERROR_MAC; + /* Get MAC Rx Tx status and clear Status register pending bit */ heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR); heth->gState = HAL_ETH_STATE_ERROR; #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /* Call registered MAC Error callback*/ - heth->DMAErrorCallback(heth); + /* Call registered Error callback*/ + heth->ErrorCallback(heth); #else - /* Ethernet MAC Error callback */ - HAL_ETH_MACErrorCallback(heth); + /* Ethernet Error callback */ + HAL_ETH_ErrorCallback(heth); #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ heth->MACErrorCode = (uint32_t)(0x0U); } /* ETH PMT IT */ - if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT)) + if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT)) { /* Get MAC Wake-up source and clear the status register pending bit */ heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD)); @@ -1589,7 +1950,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) } /* ETH EEE IT */ - if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT)) + if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT)) { /* Get MAC LPI interrupt source and clear the status register pending bit */ heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU); @@ -1609,7 +1970,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) if (HAL_GetCurrentCPUID() == CM7_CPUID) { /* check ETH WAKEUP exti flag */ - if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET) + if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET) { /* Clear ETH WAKEUP Exti pending bit */ __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE); @@ -1619,13 +1980,13 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) #else /* ETH WAKEUP callback */ HAL_ETH_WakeUpCallback(heth); -#endif +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ } } else { /* check ETH WAKEUP exti flag */ - if(__HAL_ETH_WAKEUP_EXTID2_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET) + if (__HAL_ETH_WAKEUP_EXTID2_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET) { /* Clear ETH WAKEUP Exti pending bit */ __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE); @@ -1635,24 +1996,24 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) #else /* ETH WAKEUP callback */ HAL_ETH_WakeUpCallback(heth); -#endif +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ } } -#else +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ /* check ETH WAKEUP exti flag */ - if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET) + if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET) { /* Clear ETH WAKEUP Exti pending bit */ __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE); #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /* Call registered WakeUp callback*/ - heth->WakeUpCallback(heth); + /* Call registered WakeUp callback*/ + heth->WakeUpCallback(heth); #else - /* ETH WAKEUP callback */ - HAL_ETH_WakeUpCallback(heth); -#endif + /* ETH WAKEUP callback */ + HAL_ETH_WakeUpCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ } -#endif +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ } /** @@ -1686,32 +2047,17 @@ __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) } /** - * @brief Ethernet DMA transfer error callbacks - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_DMAErrorCallback could be implemented in the user file - */ -} - -/** -* @brief Ethernet MAC transfer error callbacks + * @brief Ethernet transfer error callbacks * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ -__weak void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth) +__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) { /* Prevent unused argument(s) compilation warning */ UNUSED(heth); /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_MACErrorCallback could be implemented in the user file + the HAL_ETH_ErrorCallback could be implemented in the user file */ } @@ -1769,12 +2115,14 @@ __weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth) * @param pRegValue: parameter to hold read value * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue) +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t *pRegValue) { - uint32_t tmpreg, tickstart; + uint32_t tickstart; + uint32_t tmpreg; /* Check for the Busy flag */ - if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != 0U) + if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET) { return HAL_ERROR; } @@ -1788,7 +2136,7 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA - Set the read mode - Set the MII Busy bit */ - MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21)); + MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21)); MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16)); MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD); SET_BIT(tmpreg, ETH_MACMDIOAR_MB); @@ -1799,9 +2147,9 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA tickstart = HAL_GetTick(); /* Wait for the Busy flag */ - while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U) + while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U) { - if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT)) + if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT)) { return HAL_ERROR; } @@ -1823,12 +2171,14 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA * @param RegValue: the value to write * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue) +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t RegValue) { - uint32_t tmpreg, tickstart; + uint32_t tickstart; + uint32_t tmpreg; /* Check for the Busy flag */ - if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != 0U) + if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET) { return HAL_ERROR; } @@ -1842,7 +2192,7 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHY - Set the write mode - Set the MII Busy bit */ - MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21)); + MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21)); MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16)); MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR); SET_BIT(tmpreg, ETH_MACMDIOAR_MB); @@ -1857,9 +2207,9 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHY tickstart = HAL_GetTick(); /* Wait for the Busy flag */ - while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U) + while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U) { - if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT)) + if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT)) { return HAL_ERROR; } @@ -1903,22 +2253,25 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp /* Get MAC parameters */ macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN); - macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC)>> 4) > 0U) ? ENABLE : DISABLE; + macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC) >> 4) > 0U) ? ENABLE : DISABLE; macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL); macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8) == 0U) ? ENABLE : DISABLE; - macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U) ? ENABLE : DISABLE; + macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U) + ? ENABLE : DISABLE; macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10) == 0U) ? ENABLE : DISABLE; - macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE; + macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR, + ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE; macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE; macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM); macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES); macconf->JumboPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16) > 0U) ? ENABLE : DISABLE; - macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >>17) == 0U) ? ENABLE : DISABLE; - macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >>19) == 0U) ? ENABLE : DISABLE; + macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >> 17) == 0U) ? ENABLE : DISABLE; + macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >> 19) == 0U) ? ENABLE : DISABLE; macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20) > 0U) ? ENABLE : DISABLE; macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21) > 0U) ? ENABLE : DISABLE; macconf->Support2KPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22) > 0U) ? ENABLE : DISABLE; - macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE; + macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR, + ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE; macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG); macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27) > 0U) ? ENABLE : DISABLE; macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC); @@ -1926,8 +2279,10 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL); macconf->CRCCheckingRxPackets = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_DCRCC) >> 16) == 0U) ? ENABLE : DISABLE; macconf->SlowProtocolDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17) > 0U) ? ENABLE : DISABLE; - macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE; - macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U) ? ENABLE : DISABLE; + macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR, + ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE; + macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U) + ? ENABLE : DISABLE; macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25; @@ -1941,14 +2296,17 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE) > 0U) ? ENABLE : DISABLE; - macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U) ? ENABLE : DISABLE; + macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U) + ? ENABLE : DISABLE; macconf->TransmitQueueMode = READ_BIT(heth->Instance->MTLTQOMR, (ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF)); macconf->ReceiveQueueMode = READ_BIT(heth->Instance->MTLRQOMR, (ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF)); - macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE; + macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR, + ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE; macconf->ForwardRxErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP) >> 4) > 0U) ? ENABLE : DISABLE; - macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE; + macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, + ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE; return HAL_OK; } @@ -1970,11 +2328,11 @@ HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_AAL) >> 12) > 0U) ? ENABLE : DISABLE; dmaconf->BurstMode = READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_FB | ETH_DMASBMR_MB); - dmaconf->RebuildINCRxBurst = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_RB)>> 15) > 0U) ? ENABLE : DISABLE; + dmaconf->RebuildINCRxBurst = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_RB) >> 15) > 0U) ? ENABLE : DISABLE; - dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMAMR, (ETH_DMAMR_TXPR |ETH_DMAMR_PR | ETH_DMAMR_DA)); + dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMAMR, (ETH_DMAMR_TXPR | ETH_DMAMR_PR | ETH_DMAMR_DA)); - dmaconf->PBLx8Mode = ((READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_8PBL)>> 16) > 0U) ? ENABLE : DISABLE; + dmaconf->PBLx8Mode = ((READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_8PBL) >> 16) > 0U) ? ENABLE : DISABLE; dmaconf->MaximumSegmentSize = READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_MSS); dmaconf->FlushRxPacket = ((READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPF) >> 31) > 0U) ? ENABLE : DISABLE; @@ -1983,7 +2341,6 @@ HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp dmaconf->SecondPacketOperate = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_OSP) >> 4) > 0U) ? ENABLE : DISABLE; dmaconf->TCPSegmentation = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TSE) >> 12) > 0U) ? ENABLE : DISABLE; dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TPBL); - return HAL_OK; } @@ -1997,12 +2354,12 @@ HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp */ HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) { - if(macconf == NULL) + if (macconf == NULL) { return HAL_ERROR; } - if(heth->RxState == HAL_ETH_STATE_READY) + if (heth->gState == HAL_ETH_STATE_READY) { ETH_SetMACConfig(heth, macconf); @@ -2024,12 +2381,12 @@ HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTy */ HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) { - if(dmaconf == NULL) + if (dmaconf == NULL) { return HAL_ERROR; } - if(heth->RxState == HAL_ETH_STATE_READY) + if (heth->gState == HAL_ETH_STATE_READY) { ETH_SetDMAConfig(heth, dmaconf); @@ -2049,34 +2406,35 @@ HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTy */ void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth) { - uint32_t tmpreg, hclk; + uint32_t hclk; + uint32_t tmpreg; /* Get the ETHERNET MACMDIOAR value */ tmpreg = (heth->Instance)->MACMDIOAR; - /* Clear CSR Clock Range bits */ + /* Clear CSR Clock Range bits */ tmpreg &= ~ETH_MACMDIOAR_CR; - /* Get hclk frequency value */ + /* Get hclk frequency value */ hclk = HAL_RCC_GetHCLKFreq(); - /* Set CR bits depending on hclk value */ - if((hclk >= 20000000U)&&(hclk < 35000000U)) + /* Set CR bits depending on hclk value */ + if ((hclk >= 20000000U) && (hclk < 35000000U)) { /* CSR Clock Range between 20-35 MHz */ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16; } - else if((hclk >= 35000000U)&&(hclk < 60000000U)) + else if ((hclk >= 35000000U) && (hclk < 60000000U)) { /* CSR Clock Range between 35-60 MHz */ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26; } - else if((hclk >= 60000000U)&&(hclk < 100000000U)) + else if ((hclk >= 60000000U) && (hclk < 100000000U)) { /* CSR Clock Range between 60-100 MHz */ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42; } - else if((hclk >= 100000000U)&&(hclk < 150000000U)) + else if ((hclk >= 100000000U) && (hclk < 150000000U)) { /* CSR Clock Range between 100-150 MHz */ tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62; @@ -2103,22 +2461,22 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil { uint32_t filterconfig; - if(pFilterConfig == NULL) + if (pFilterConfig == NULL) { return HAL_ERROR; } filterconfig = ((uint32_t)pFilterConfig->PromiscuousMode | ((uint32_t)pFilterConfig->HashUnicast << 1) | - ((uint32_t)pFilterConfig->HashMulticast << 2) | - ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) | - ((uint32_t)pFilterConfig->PassAllMulticast << 4) | - ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) | - ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) | - ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) | - ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) | - ((uint32_t)pFilterConfig->ReceiveAllMode << 31) | - pFilterConfig->ControlPacketsFilter); + ((uint32_t)pFilterConfig->HashMulticast << 2) | + ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) | + ((uint32_t)pFilterConfig->PassAllMulticast << 4) | + ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) | + ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) | + ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) | + ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) | + ((uint32_t)pFilterConfig->ReceiveAllMode << 31) | + pFilterConfig->ControlPacketsFilter); MODIFY_REG(heth->Instance->MACPFR, ETH_MACPFR_MASK, filterconfig); @@ -2135,7 +2493,7 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil */ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig) { - if(pFilterConfig == NULL) + if (pFilterConfig == NULL) { return HAL_ERROR; } @@ -2143,13 +2501,16 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil pFilterConfig->PromiscuousMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PR)) > 0U) ? ENABLE : DISABLE; pFilterConfig->HashUnicast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HUC) >> 1) > 0U) ? ENABLE : DISABLE; pFilterConfig->HashMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HMC) >> 2) > 0U) ? ENABLE : DISABLE; - pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE; + pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, + ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE; pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE; pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) == 0U) ? ENABLE : DISABLE; pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF); - pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE; + pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, + ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE; pFilterConfig->SrcAddrFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAF) >> 9) > 0U) ? ENABLE : DISABLE; - pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HPF) >> 10) > 0U) ? ENABLE : DISABLE; + pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HPF) >> 10) > 0U) + ? ENABLE : DISABLE; pFilterConfig->ReceiveAllMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_RA) >> 31) > 0U) ? ENABLE : DISABLE; return HAL_OK; @@ -2169,17 +2530,18 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil */ HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr) { - uint32_t macaddrhr, macaddrlr; + uint32_t macaddrlr; + uint32_t macaddrhr; - if(pMACAddr == NULL) + if (pMACAddr == NULL) { return HAL_ERROR; } /* Get mac addr high reg offset */ - macaddrhr = ((uint32_t)&(heth->Instance->MACA0HR) + AddrNbr); + macaddrhr = ((uint32_t) &(heth->Instance->MACA0HR) + AddrNbr); /* Get mac addr low reg offset */ - macaddrlr = ((uint32_t)&(heth->Instance->MACA0LR) + AddrNbr); + macaddrlr = ((uint32_t) &(heth->Instance->MACA0LR) + AddrNbr); /* Set MAC addr bits 32 to 47 */ (*(__IO uint32_t *)macaddrhr) = (((uint32_t)(pMACAddr[5]) << 8) | (uint32_t)pMACAddr[4]); @@ -2187,7 +2549,7 @@ HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_ (*(__IO uint32_t *)macaddrlr) = (((uint32_t)(pMACAddr[3]) << 24) | ((uint32_t)(pMACAddr[2]) << 16) | ((uint32_t)(pMACAddr[1]) << 8) | (uint32_t)pMACAddr[0]); - /* Enable address and set source address bit */ + /* Enable address and set source address bit */ (*(__IO uint32_t *)macaddrhr) |= (ETH_MACAHR_SA | ETH_MACAHR_AE); return HAL_OK; @@ -2203,7 +2565,7 @@ HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_ */ HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable) { - if(pHashTable == NULL) + if (pHashTable == NULL) { return HAL_ERROR; } @@ -2225,14 +2587,14 @@ HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashT */ void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier) { - if(ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT) + if (ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT) { - MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL , VLANIdentifier); + MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL, VLANIdentifier); CLEAR_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV); } else { - MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL_VID , VLANIdentifier); + MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL_VID, VLANIdentifier); SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV); } } @@ -2251,9 +2613,9 @@ void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigType powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << 1) | ((uint32_t)pPowerDownConfig->WakeUpPacket << 2) | - ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) | - ((uint32_t)pPowerDownConfig->WakeUpForward << 10) | - ETH_MACPCSR_PWRDWN); + ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) | + ((uint32_t)pPowerDownConfig->WakeUpForward << 10) | + ETH_MACPCSR_PWRDWN); /* Enable PMT interrupt */ __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_PMTIE); @@ -2270,9 +2632,10 @@ void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigType void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth) { /* clear wake up sources */ - CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | ETH_MACPCSR_RWKPFE); + CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | + ETH_MACPCSR_RWKPFE); - if(READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN) != 0U) + if (READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN) != (uint32_t)RESET) { /* Exit power down mode */ CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN); @@ -2294,7 +2657,7 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi { uint32_t regindex; - if(pFilter == NULL) + if (pFilter == NULL) { return HAL_ERROR; } @@ -2303,7 +2666,7 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi SET_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKFILTRST); /* Wake up packet filter config */ - for(regindex = 0; regindex < Count; regindex++) + for (regindex = 0; regindex < Count; regindex++) { /* Write filter regs */ WRITE_REG(heth->Instance->MACRWKPFR, pFilter[regindex]); @@ -2341,13 +2704,7 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi */ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) { - HAL_ETH_StateTypeDef ret; - HAL_ETH_StateTypeDef gstate = heth->gState; - HAL_ETH_StateTypeDef rxstate =heth->RxState; - - ret = gstate; - ret |= rxstate; - return ret; + return heth->gState; } /** @@ -2406,42 +2763,43 @@ uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth) * @{ */ + static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) { uint32_t macregval; /*------------------------ MACCR Configuration --------------------*/ - macregval =(macconf->InterPacketGapVal | - macconf->SourceAddrControl | - ((uint32_t)macconf->ChecksumOffload<< 27) | - ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) | - ((uint32_t)macconf->Support2KPacket << 22) | - ((uint32_t)macconf->CRCStripTypePacket << 21) | - ((uint32_t)macconf->AutomaticPadCRCStrip << 20) | - ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) | - ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) | - ((uint32_t)macconf->JumboPacket << 16) | - macconf->Speed | - macconf->DuplexMode | - ((uint32_t)macconf->LoopbackMode << 12) | - ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11)| - ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10)| - ((uint32_t)macconf->CarrierSenseDuringTransmit << 9)| - ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8)| - macconf->BackOffLimit | - ((uint32_t)macconf->DeferralCheck << 4)| - macconf->PreambleLength); + macregval = (macconf->InterPacketGapVal | + macconf->SourceAddrControl | + ((uint32_t)macconf->ChecksumOffload << 27) | + ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) | + ((uint32_t)macconf->Support2KPacket << 22) | + ((uint32_t)macconf->CRCStripTypePacket << 21) | + ((uint32_t)macconf->AutomaticPadCRCStrip << 20) | + ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) | + ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) | + ((uint32_t)macconf->JumboPacket << 16) | + macconf->Speed | + macconf->DuplexMode | + ((uint32_t)macconf->LoopbackMode << 12) | + ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) | + ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) | + ((uint32_t)macconf->CarrierSenseDuringTransmit << 9) | + ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) | + macconf->BackOffLimit | + ((uint32_t)macconf->DeferralCheck << 4) | + macconf->PreambleLength); /* Write to MACCR */ MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval); /*------------------------ MACECR Configuration --------------------*/ - macregval = ((macconf->ExtendedInterPacketGapVal << 25)| - ((uint32_t)macconf->ExtendedInterPacketGap << 24)| - ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18)| - ((uint32_t)macconf->SlowProtocolDetect << 17)| - ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U)<< 16) | - macconf->GiantPacketSizeLimit); + macregval = ((macconf->ExtendedInterPacketGapVal << 25) | + ((uint32_t)macconf->ExtendedInterPacketGap << 24) | + ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) | + ((uint32_t)macconf->SlowProtocolDetect << 17) | + ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U) << 16) | + macconf->GiantPacketSizeLimit); /* Write to MACECR */ MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval); @@ -2456,8 +2814,8 @@ static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *mac /*------------------------ MACTFCR Configuration --------------------*/ macregval = (((uint32_t)macconf->TransmitFlowControl << 1) | macconf->PauseLowThreshold | - ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U)<< 7) | - (macconf->PauseTime << 16)); + ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7) | + (macconf->PauseTime << 16)); /* Write to MACTFCR */ MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval); @@ -2476,8 +2834,8 @@ static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *mac /*------------------------ MTLRQOMR Configuration --------------------*/ macregval = (macconf->ReceiveQueueMode | ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) | - ((uint32_t)macconf->ForwardRxErrorPacket << 4) | - ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3)); + ((uint32_t)macconf->ForwardRxErrorPacket << 4) | + ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3)); /* Write to MTLRQOMR */ MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval); @@ -2493,7 +2851,7 @@ static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dma /*------------------------ DMASBMR Configuration --------------------*/ dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) | dmaconf->BurstMode | - ((uint32_t)dmaconf->RebuildINCRxBurst << 15)); + ((uint32_t)dmaconf->RebuildINCRxBurst << 15)); MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval); @@ -2505,8 +2863,8 @@ static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dma /*------------------------ DMACTCR Configuration --------------------*/ dmaregval = (dmaconf->TxDMABurstLength | - ((uint32_t)dmaconf->SecondPacketOperate << 4)| - ((uint32_t)dmaconf->TCPSegmentation << 12)); + ((uint32_t)dmaconf->SecondPacketOperate << 4) | + ((uint32_t)dmaconf->TCPSegmentation << 12)); MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval); @@ -2585,62 +2943,12 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth) dmaDefaultConf.SecondPacketOperate = DISABLE; dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; dmaDefaultConf.TCPSegmentation = DISABLE; - dmaDefaultConf.MaximumSegmentSize = 536; + dmaDefaultConf.MaximumSegmentSize = ETH_SEGMENT_SIZE_DEFAULT; /* DMA default configuration */ ETH_SetDMAConfig(heth, &dmaDefaultConf); } -/** - * @brief Configures the Clock range of SMI interface. - * called by HAL_ETH_Init() API. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth) -{ - uint32_t tmpreg, hclk; - - /* Get the ETHERNET MACMDIOAR value */ - tmpreg = (heth->Instance)->MACMDIOAR; - - /* Clear CSR Clock Range bits */ - tmpreg &= ~ETH_MACMDIOAR_CR; - - /* Get hclk frequency value */ - hclk = HAL_RCC_GetHCLKFreq(); - - /* Set CR bits depending on hclk value */ - if((hclk >= 20000000U)&&(hclk < 35000000U)) - { - /* CSR Clock Range between 20-35 MHz */ - tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16; - } - else if((hclk >= 35000000U)&&(hclk < 60000000U)) - { - /* CSR Clock Range between 35-60 MHz */ - tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26; - } - else if((hclk >= 60000000U)&&(hclk < 100000000U)) - { - /* CSR Clock Range between 60-100 MHz */ - tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42; - } - else if((hclk >= 100000000U)&&(hclk < 150000000U)) - { - /* CSR Clock Range between 100-150 MHz */ - tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62; - } - else /* (hclk >= 150000000)&&(hclk <= 200000000) */ - { - /* CSR Clock Range between 150-200 MHz */ - tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102; - } - - /* Configure the CSR Clock Range */ - (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg; -} /** * @brief Initializes the DMA Tx descriptors. @@ -2655,7 +2963,7 @@ static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth) uint32_t i; /* Fill each DMATxDesc descriptor with the right values */ - for(i=0; i < (uint32_t)ETH_TX_DESC_CNT; i++) + for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++) { dmatxdesc = heth->Init.TxDesc + i; @@ -2665,12 +2973,13 @@ static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth) WRITE_REG(dmatxdesc->DESC3, 0x0); WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc); + } heth->TxDescList.CurTxDesc = 0; /* Set Transmit Descriptor Ring Length */ - WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT -1)); + WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT - 1U)); /* Set Transmit Descriptor List Address */ WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc); @@ -2691,7 +3000,7 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) ETH_DMADescTypeDef *dmarxdesc; uint32_t i; - for(i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) + for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) { dmarxdesc = heth->Init.RxDesc + i; @@ -2702,24 +3011,26 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) WRITE_REG(dmarxdesc->BackupAddr0, 0x0); WRITE_REG(dmarxdesc->BackupAddr1, 0x0); + /* Set Rx descritors addresses */ WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc); + } - WRITE_REG(heth->RxDescList.CurRxDesc, 0); - WRITE_REG(heth->RxDescList.FirstAppDesc, 0); - WRITE_REG(heth->RxDescList.AppDescNbr, 0); + WRITE_REG(heth->RxDescList.RxDescIdx, 0); + WRITE_REG(heth->RxDescList.RxDescCnt, 0); + WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0); + WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0); WRITE_REG(heth->RxDescList.ItMode, 0); - WRITE_REG(heth->RxDescList.AppContextDesc, 0); /* Set Receive Descriptor Ring Length */ - WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1))); + WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1U))); /* Set Receive Descriptor List Address */ WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc); /* Set Receive Descriptor Tail pointer Address */ - WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1)))); + WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1U)))); } /** @@ -2736,14 +3047,16 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; uint32_t descidx = dmatxdesclist->CurTxDesc; uint32_t firstdescidx = dmatxdesclist->CurTxDesc; - uint32_t descnbr = 0, idx; + uint32_t idx; + uint32_t descnbr = 0; ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer; uint32_t bd_count = 0; /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ - if((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) || (dmatxdesclist->PacketAddress[descidx] != NULL)) + if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) + || (dmatxdesclist->PacketAddress[descidx] != NULL)) { return HAL_ETH_ERROR_BUSY; } @@ -2752,7 +3065,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket /***************** Context descriptor configuration (Optional) **********/ /***************************************************************************/ /* If VLAN tag is enabled for this packet */ - if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U) + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) { /* Set vlan tag value */ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag); @@ -2762,7 +3075,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI); /* if inner VLAN is enabled */ - if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != 0U) + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != (uint32_t)RESET) { /* Set inner vlan tag value */ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16)); @@ -2780,7 +3093,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket } /* if tcp segmentation is enabled for this packet */ - if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U) + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) { /* Set MSS value */ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize); @@ -2788,10 +3101,13 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV); } - if((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)|| (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)) + if ((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) + || (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)) { /* Set as context descriptor */ SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT); + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); /* Set own bit */ SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN); /* Increment current tx descriptor index */ @@ -2802,9 +3118,11 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket descnbr += 1U; /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ - if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) + if (READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) { dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx]; + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); /* Clear own bit */ CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN); @@ -2823,7 +3141,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket /* Set header or buffer 1 Length */ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len); - if(txbuffer->next != NULL) + if (txbuffer->next != NULL) { txbuffer = txbuffer->next; /* Set buffer 2 address */ @@ -2838,7 +3156,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U); } - if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U) + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) { /* Set TCP Header length */ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19)); @@ -2851,18 +3169,18 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket { MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length); - if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U) + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET) { MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl); } - if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != 0U) + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != (uint32_t)RESET) { MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl); } } - if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U) + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) { /* Set Vlan Tag control */ MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl); @@ -2872,11 +3190,13 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD); /* Mark it as NORMAL descriptor */ CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT); + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); /* set OWN bit of FIRST descriptor */ SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); /* If source address insertion/replacement is enabled for this packet */ - if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != 0U) + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != (uint32_t)RESET) { MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl); } @@ -2895,14 +3215,18 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD); /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ - if((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN) || (dmatxdesclist->PacketAddress[descidx] != NULL)) + if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN) + || (dmatxdesclist->PacketAddress[descidx] != NULL)) { descidx = firstdescidx; dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; /* clear previous desc own bit */ - for(idx = 0; idx < descnbr; idx ++) + for (idx = 0; idx < descnbr; idx ++) { + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); /* Increment current tx descriptor index */ @@ -2940,7 +3264,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U); } - if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U) + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) { /* Set TCP payload length */ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen); @@ -2952,7 +3276,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket /* Set the packet length */ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length); - if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U) + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET) { /* Checksum Insertion Control */ MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl); @@ -2960,13 +3284,16 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket } bd_count += 1U; + + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); /* Set Own bit */ SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); /* Mark it as NORMAL descriptor */ CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT); } - if(ItMode != ((uint32_t)RESET)) + if (ItMode != ((uint32_t)RESET)) { /* Set Interrupt on completion bit */ SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC); @@ -3003,8 +3330,7 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth) /* Init the ETH Callback settings */ heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */ heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */ - heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback; /* Legacy weak DMAErrorCallback */ - heth->MACErrorCallback = HAL_ETH_MACErrorCallback; /* Legacy weak MACErrorCallback */ + heth->ErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak ErrorCallback */ heth->PMTCallback = HAL_ETH_PMTCallback; /* Legacy weak PMTCallback */ heth->EEECallback = HAL_ETH_EEECallback; /* Legacy weak EEECallback */ heth->WakeUpCallback = HAL_ETH_WakeUpCallback; /* Legacy weak WakeUpCallback */ @@ -3027,4 +3353,3 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c index 5672dfe4d..ad9870c03 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -71,7 +70,7 @@ /** @defgroup ETHEx_Exported_Functions_Group1 Extended features functions * @brief Extended features functions - * + * @verbatim =============================================================================== ##### Extended features functions ##### @@ -133,25 +132,26 @@ void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress) * that contains L4 filter configuration. * @retval HAL status */ -HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter , ETH_L4FilterConfigTypeDef *pL4FilterConfig) +HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L4FilterConfigTypeDef *pL4FilterConfig) { __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)); - if(pL4FilterConfig == NULL) + if (pL4FilterConfig == NULL) { return HAL_ERROR; } /* Write configuration to (MACL3L4C0R + filter )register */ - MODIFY_REG(*configreg, ETH_MACL4CR_MASK ,(pL4FilterConfig->Protocol | + MODIFY_REG(*configreg, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol | pL4FilterConfig->SrcPortFilterMatch | - pL4FilterConfig->DestPortFilterMatch)); + pL4FilterConfig->DestPortFilterMatch)); configreg = ((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)); /* Write configuration to (MACL4A0R + filter )register */ - MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP) , (pL4FilterConfig->SourcePort | - (pL4FilterConfig->DestinationPort << 16))); + MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP), (pL4FilterConfig->SourcePort | + (pL4FilterConfig->DestinationPort << 16))); /* Enable L4 filter */ SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE); @@ -172,20 +172,25 @@ HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t * that contains L4 filter configuration. * @retval HAL status */ -HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig) +HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L4FilterConfigTypeDef *pL4FilterConfig) { - if(pL4FilterConfig == NULL) + if (pL4FilterConfig == NULL) { return HAL_ERROR; } /* Get configuration to (MACL3L4C0R + filter )register */ - pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L4PEN); - pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)); - pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM)); + pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + ETH_MACL3L4CR_L4PEN); + pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)); + pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM)); /* Get configuration to (MACL3L4C0R + filter )register */ - pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4DP) >> 16); + pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), + ETH_MACL4AR_L4DP) >> 16); pL4FilterConfig->SourcePort = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4SP); return HAL_OK; @@ -204,11 +209,12 @@ HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t * that contains L3 filter configuration. * @retval HAL status */ -HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig) +HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L3FilterConfigTypeDef *pL3FilterConfig) { __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)); - if(pL3FilterConfig == NULL) + if (pL3FilterConfig == NULL) { return HAL_ERROR; } @@ -216,12 +222,12 @@ HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t /* Write configuration to (MACL3L4C0R + filter )register */ MODIFY_REG(*configreg, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol | pL3FilterConfig->SrcAddrFilterMatch | - pL3FilterConfig->DestAddrFilterMatch | - (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) | - (pL3FilterConfig->DestAddrHigherBitsMatch << 11))); + pL3FilterConfig->DestAddrFilterMatch | + (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) | + (pL3FilterConfig->DestAddrHigherBitsMatch << 11))); /* Check if IPv6 protocol is selected */ - if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH) + if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH) { /* Set the IPv6 address match */ /* Set Bits[31:0] of 128-bit IP addr */ @@ -257,20 +263,26 @@ HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t * that will contain the L3 filter configuration. * @retval HAL status */ -HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig) +HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L3FilterConfigTypeDef *pL3FilterConfig) { - if(pL3FilterConfig == NULL) + if (pL3FilterConfig == NULL) { return HAL_ERROR; } - pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3PEN); - pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)); - pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)); - pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HSBM) >> 6); - pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HDBM) >> 11); - - if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH) + pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + ETH_MACL3L4CR_L3PEN); + pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)); + pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)); + pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + ETH_MACL3L4CR_L3HSBM) >> 6); + pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + ETH_MACL3L4CR_L3HDBM) >> 11); + + if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH) { pL3FilterConfig->Ip6Addr[0] = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)); pL3FilterConfig->Ip6Addr[1] = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)); @@ -320,20 +332,25 @@ void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth) */ HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig) { - if(pVlanConfig == NULL) + if (pVlanConfig == NULL) { return HAL_ERROR; } - pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE; + pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, + ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE; pVlanConfig->StripInnerVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS); pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE; - pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE; - pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE; + pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR, + ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE; + pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR, + ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE; pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE; pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS); - pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR, (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)); - pVlanConfig->VLANTagInverceMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17) == 0U) ? DISABLE : ENABLE; + pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR, + (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)); + pVlanConfig->VLANTagInverceMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17) == 0U) + ? DISABLE : ENABLE; return HAL_OK; } @@ -348,7 +365,7 @@ HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANC */ HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig) { - if(pVlanConfig == NULL) + if (pVlanConfig == NULL) { return HAL_ERROR; } @@ -356,13 +373,13 @@ HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANC /* Write config to MACVTR */ MODIFY_REG(heth->Instance->MACVTR, ETH_MACRXVLAN_MASK, (((uint32_t)pVlanConfig->InnerVLANTagInStatus << 31) | pVlanConfig->StripInnerVLANTag | - ((uint32_t)pVlanConfig->InnerVLANTag << 27) | - ((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) | - ((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) | - ((uint32_t)pVlanConfig->VLANTagInStatus << 24) | - pVlanConfig->StripVLANTag | - pVlanConfig->VLANTypeCheck | - ((uint32_t)pVlanConfig->VLANTagInverceMatch << 17))); + ((uint32_t)pVlanConfig->InnerVLANTag << 27) | + ((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) | + ((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) | + ((uint32_t)pVlanConfig->VLANTagInStatus << 24) | + pVlanConfig->StripVLANTag | + pVlanConfig->VLANTypeCheck | + ((uint32_t)pVlanConfig->VLANTagInverceMatch << 17))); return HAL_OK; } @@ -390,14 +407,15 @@ void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable) * that will contain the Tx VLAN filter configuration. * @retval HAL Status. */ -HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig) +HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag, + ETH_TxVLANConfigTypeDef *pVlanConfig) { if (pVlanConfig == NULL) { return HAL_ERROR; } - if(VLANTag == ETH_INNER_TX_VLANTAG) + if (VLANTag == ETH_INNER_TX_VLANTAG) { pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE; pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE; @@ -424,13 +442,14 @@ HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VL * that contains Tx VLAN filter configuration. * @retval HAL Status */ -HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig) +HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag, + ETH_TxVLANConfigTypeDef *pVlanConfig) { - if(VLANTag == ETH_INNER_TX_VLANTAG) + if (VLANTag == ETH_INNER_TX_VLANTAG) { MODIFY_REG(heth->Instance->MACIVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) | - ((uint32_t)pVlanConfig->SVLANType << 19) | - pVlanConfig->VLANTagControl)); + ((uint32_t)pVlanConfig->SVLANType << 19) | + pVlanConfig->VLANTagControl)); /* Enable Double VLAN processing */ SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP); } @@ -438,7 +457,7 @@ HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VL { MODIFY_REG(heth->Instance->MACVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) | ((uint32_t)pVlanConfig->SVLANType << 19) | - pVlanConfig->VLANTagControl)); + pVlanConfig->VLANTagControl)); } return HAL_OK; @@ -454,9 +473,9 @@ HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VL * @param VLANIdentifier: VLAN Identifier 16 bit value * @retval None */ -void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier) +void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier) { - if(VLANTag == ETH_INNER_TX_VLANTAG) + if (VLANTag == ETH_INNER_TX_VLANTAG) { MODIFY_REG(heth->Instance->MACIVIR, ETH_MACVIR_VLT, VLANIdentifier); } @@ -504,9 +523,10 @@ void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_LPIIE); /* Write to LPI Control register: Enter low power mode */ - MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE), (((uint32_t)TxAutomate << 19) | - ((uint32_t)TxClockStop << 21) | - ETH_MACLCSR_LPIEN)); + MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE), + (((uint32_t)TxAutomate << 19) | + ((uint32_t)TxClockStop << 21) | + ETH_MACLCSR_LPIEN)); } /** @@ -556,4 +576,3 @@ uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c index e49dc3ac6..da129234b 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions * + IO operation functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### EXTI Peripheral features ##### @@ -103,18 +114,6 @@ (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -440,6 +439,10 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT } #endif /*DUAL_CORE*/ + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00U; + /* 2] Get trigger for configurable lines : rising */ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U) { @@ -451,10 +454,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT { pExtiConfig->Trigger = EXTI_TRIGGER_RISING; } - else - { - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - } /* Get falling configuration */ regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); @@ -474,27 +473,16 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL]; pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3UL - (linepos & 0x03UL)))) >> 24U); } - else - { - pExtiConfig->GPIOSel = 0x00U; - } - } - else - { - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - pExtiConfig->GPIOSel = 0x00U; } + /* Get default Pend Clear Source */ + pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE; + /* 3] Get D3 Pend Clear source */ if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL) { regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset)); - if(((*regaddr) & linepos) == 0UL) - { - /* if PMR unset, then no pend clear source is used */ - pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE; - } - else + if(((*regaddr) & linepos) != 0UL) { /* if wakeup target is any and PMR set, the read pend clear source from D3PCRxL/H */ if(linepos < 16UL) @@ -511,11 +499,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT pExtiConfig->PendClearSource = 1UL + ((*regaddr & (pcrlinepos * pcrlinepos * 3UL)) / (pcrlinepos * pcrlinepos)); } } - else - { - /* if line wakeup target is not any, then no pend clear source is used */ - pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE; - } return HAL_OK; } @@ -874,4 +857,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c index 0549620e2..950ea150e 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c @@ -11,6 +11,17 @@ * + Peripheral Configuration and Control functions * + Peripheral State and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -96,10 +107,10 @@ The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback() + Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback() to register an interrupt callback. - Function @ref HAL_FDCAN_RegisterCallback() allows to register following callbacks: + Function HAL_FDCAN_RegisterCallback() allows to register following callbacks: (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. (+) RxBufferNewMessageCallback : Rx Buffer New Message Callback. (+) HighPriorityMessageCallback : High Priority Message Callback. @@ -114,16 +125,16 @@ For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback, ErrorStatusCallback, TT_ScheduleSyncCallback, TT_TimeMarkCallback, TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated register callbacks : - respectively @ref HAL_FDCAN_RegisterClockCalibrationCallback(), @ref HAL_FDCAN_RegisterTxEventFifoCallback(), - @ref HAL_FDCAN_RegisterRxFifo0Callback(), @ref HAL_FDCAN_RegisterRxFifo1Callback(), - @ref HAL_FDCAN_RegisterTxBufferCompleCallback(), @ref HAL_FDCAN_RegisterTxBufferAbortCallback(), - @ref HAL_FDCAN_RegisterErrorStatusCallback(), @ref HAL_FDCAN_TT_RegisterScheduleSyncCallback(), - @ref HAL_FDCAN_TT_RegisterTimeMarkCallback(), @ref HAL_FDCAN_TT_RegisterStopWatchCallback() and - @ref HAL_FDCAN_TT_RegisterGlobalTimeCallback(). - - Use function @ref HAL_FDCAN_UnRegisterCallback() to reset a callback to the default + respectively HAL_FDCAN_RegisterClockCalibrationCallback(), HAL_FDCAN_RegisterTxEventFifoCallback(), + HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(), + HAL_FDCAN_RegisterTxBufferCompleCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback(), + HAL_FDCAN_RegisterErrorStatusCallback(), HAL_FDCAN_TT_RegisterScheduleSyncCallback(), + HAL_FDCAN_TT_RegisterTimeMarkCallback(), HAL_FDCAN_TT_RegisterStopWatchCallback() and + HAL_FDCAN_TT_RegisterGlobalTimeCallback(). + + Use function HAL_FDCAN_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. @@ -138,20 +149,20 @@ For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback, TT_ScheduleSyncCallback, TT_TimeMarkCallback, TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated - register callbacks : respectively @ref HAL_FDCAN_UnRegisterClockCalibrationCallback(), - @ref HAL_FDCAN_UnRegisterTxEventFifoCallback(), @ref HAL_FDCAN_UnRegisterRxFifo0Callback(), - @ref HAL_FDCAN_UnRegisterRxFifo1Callback(), @ref HAL_FDCAN_UnRegisterTxBufferCompleCallback(), - @ref HAL_FDCAN_UnRegisterTxBufferAbortCallback(), @ref HAL_FDCAN_UnRegisterErrorStatusCallback(), - @ref HAL_FDCAN_TT_UnRegisterScheduleSyncCallback(), @ref HAL_FDCAN_TT_UnRegisterTimeMarkCallback(), - @ref HAL_FDCAN_TT_UnRegisterStopWatchCallback() and @ref HAL_FDCAN_TT_UnRegisterGlobalTimeCallback(). - - By default, after the @ref HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET, + register callbacks : respectively HAL_FDCAN_UnRegisterClockCalibrationCallback(), + HAL_FDCAN_UnRegisterTxEventFifoCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(), + HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTxBufferCompleCallback(), + HAL_FDCAN_UnRegisterTxBufferAbortCallback(), HAL_FDCAN_UnRegisterErrorStatusCallback(), + HAL_FDCAN_TT_UnRegisterScheduleSyncCallback(), HAL_FDCAN_TT_UnRegisterTimeMarkCallback(), + HAL_FDCAN_TT_UnRegisterStopWatchCallback() and HAL_FDCAN_TT_UnRegisterGlobalTimeCallback(). + + By default, after the HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET, all callbacks are set to the corresponding weak functions: - examples @ref HAL_FDCAN_ErrorCallback(). + examples HAL_FDCAN_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit() only when + reset to the legacy weak function in the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() only when these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit() + if not, MspInit or MspDeInit are not null, the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only. @@ -159,26 +170,14 @@ in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_FDCAN_RegisterCallback() before calling @ref HAL_FDCAN_DeInit() - or @ref HAL_FDCAN_Init() function. + using HAL_FDCAN_RegisterCallback() before calling HAL_FDCAN_DeInit() + or HAL_FDCAN_Init() function. When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @endverbatim - - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** */ @@ -5265,6 +5264,10 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) uint32_t TTFatalErrors; uint32_t SWTime; uint32_t SWCycleCount; + uint32_t itsourceIE; + uint32_t itsourceTTIE; + uint32_t itflagIR; + uint32_t itflagTTIR; ClkCalibrationITs = (FDCAN_CCU->IR << 30); ClkCalibrationITs &= (FDCAN_CCU->IE << 30); @@ -5278,11 +5281,13 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) Errors &= hfdcan->Instance->IE; ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK; ErrorStatusITs &= hfdcan->Instance->IE; + itsourceIE = hfdcan->Instance->IE; + itflagIR = hfdcan->Instance->IR; /* High Priority Message interrupt management *******************************/ - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET) { - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != 0U) + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET) { /* Clear the High Priority Message flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG); @@ -5298,9 +5303,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Transmission Abort interrupt management **********************************/ - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_ABORT_COMPLETE) != RESET) { - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != 0U) + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET) { /* List of aborted monitored buffers */ AbortedBuffers = hfdcan->Instance->TXBCF; @@ -5380,9 +5385,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Tx FIFO empty interrupt management ***************************************/ - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_FIFO_EMPTY) != RESET) { - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != 0U) + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET) { /* Clear the Tx FIFO empty flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY); @@ -5398,9 +5403,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Transmission Complete interrupt management *******************************/ - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_COMPLETE) != RESET) { - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != 0U) + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_COMPLETE) != RESET) { /* List of transmitted monitored buffers */ TransmittedBuffers = hfdcan->Instance->TXBTO; @@ -5420,9 +5425,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Rx Buffer New Message interrupt management *******************************/ - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != RESET) { - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != 0U) + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != RESET) { /* Clear the Rx Buffer New Message flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE); @@ -5438,9 +5443,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Timestamp Wraparound interrupt management ********************************/ - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET) { - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != 0U) + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET) { /* Clear the Timestamp Wraparound flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND); @@ -5456,9 +5461,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Timeout Occurred interrupt management ************************************/ - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMEOUT_OCCURRED) != RESET) { - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != 0U) + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET) { /* Clear the Timeout Occurred flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED); @@ -5474,9 +5479,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* Message RAM access failure interrupt management **************************/ - if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET) { - if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != 0U) + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET) { /* Clear the Message RAM access failure flag */ __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE); @@ -5525,6 +5530,8 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) TTDistErrors &= hfdcan->ttcan->TTIE; TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK; TTFatalErrors &= hfdcan->ttcan->TTIE; + itsourceTTIE = hfdcan->ttcan->TTIE; + itflagTTIR = hfdcan->ttcan->TTIR; /* TT Schedule Synchronization interrupts management **********************/ if (TTSchedSyncITs != 0U) @@ -5557,9 +5564,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) } /* TT Stop Watch interrupt management *************************************/ - if (__HAL_FDCAN_TT_GET_IT_SOURCE(hfdcan, FDCAN_TT_IT_STOP_WATCH) != 0U) + if (FDCAN_CHECK_IT_SOURCE(itsourceTTIE, FDCAN_TT_IT_STOP_WATCH) != RESET) { - if (__HAL_FDCAN_TT_GET_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH) != 0U) + if (FDCAN_CHECK_FLAG(itflagTTIR, FDCAN_TT_FLAG_STOP_WATCH) != RESET) { /* Retrieve Stop watch Time and Cycle count */ SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos); @@ -6195,4 +6202,3 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy #endif /* FDCAN1 */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c index a73e8ed02..1df845e22 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c @@ -74,14 +74,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -1001,7 +999,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank) flag will be set */ uint32_t bsyflag = FLASH_FLAG_QW_BANK1; - uint32_t errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1; + uint32_t errorflag = 0; uint32_t tickstart = HAL_GetTick(); assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank)); @@ -1010,8 +1008,6 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank) if (Bank == FLASH_BANK_2) { - /* Get Error Flags */ - errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U; /* Select bsyflag depending on Bank */ bsyflag = FLASH_FLAG_QW_BANK2; } @@ -1028,6 +1024,18 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank) } } + /* Get Error Flags */ + if (Bank == FLASH_BANK_1) + { + errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1; + } +#if defined (DUAL_BANK) + else + { + errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U; + } +#endif /* DUAL_BANK */ + /* In case of error reported in Flash SR1 or SR2 register */ if((errorflag & 0x7FFFFFFFU) != 0U) { @@ -1184,4 +1192,4 @@ HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c index d0219243d..fd4acec14 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c @@ -62,14 +62,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -408,7 +406,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) /** * @brief Program option bytes - * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * @param pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that * contains the configuration information for the programming. * * @retval HAL Status @@ -549,7 +547,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) /** * @brief Get the Option byte configuration - * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * @param pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that * contains the configuration information for the programming. * @note The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or FLASH_BANK_2, * as this parameter is use to get the given Bank WRP, PCROP and secured area configuration. @@ -971,7 +969,7 @@ void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange) * @brief Enable the write protection of the desired bank1 or bank 2 sectors * @param WRPSector specifies the sector(s) to be write protected. * This parameter can be one of the following values: - * @arg WRPSector: A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_All + * @arg WRPSector: A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_ALL * * @param Banks the specific bank to apply WRP sectors * This parameter can be one of the following values: @@ -1006,7 +1004,7 @@ static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) * @brief Disable the write protection of the desired bank1 or bank 2 sectors * @param WRPSector specifies the sector(s) to disable write protection. * This parameter can be one of the following values: - * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All + * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL * * @param Banks the specific bank to apply WRP sectors * This parameter can be one of the following values: @@ -1045,7 +1043,7 @@ static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) * @param WRPSector gives the write protected sector(s) on the given bank . * This parameter can be one of the following values: - * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All + * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL * * @param Bank the specific bank to apply WRP sectors * This parameter can be exclusively one of the following values: @@ -1819,7 +1817,7 @@ static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig) */ static uint32_t FLASH_OB_SharedRAM_GetConfig(void) { - return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_TCM_AXI_SHARED);; + return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_TCM_AXI_SHARED); } #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ @@ -1846,7 +1844,7 @@ static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost) */ static uint32_t FLASH_OB_CPUFreq_GetBoost(void) { - return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_CPUFREQ_BOOST);; + return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_CPUFREQ_BOOST); } #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ @@ -1860,4 +1858,3 @@ static uint32_t FLASH_OB_CPUFreq_GetBoost(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fmac.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fmac.c index 915921013..dd2e1ec87 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fmac.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fmac.c @@ -9,7 +9,19 @@ * + Peripheral Control functions * + Callback functions * + IRQ handler management - * + Peripheral State functions + * + Peripheral State and Error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** * * @verbatim ================================================================================ @@ -26,9 +38,10 @@ (+++) In FMAC IRQ handler, call HAL_FMAC_IRQHandler(). (++) In case of using DMA to control data transfer (e.g. access configured as FMAC_BUFFER_ACCESS_DMA): - (+++) Enable the DMA1 interface clock using __HAL_RCC_DMA1_CLK_ENABLE(). + (+++) Enable the DMA interface clock using __HAL_RCC_DMA1_CLK_ENABLE() + or __HAL_RCC_DMA2_CLK_ENABLE() depending on the used DMA instance. (+++) Enable the DMAMUX1 interface clock using __HAL_RCC_DMAMUX1_CLK_ENABLE(). - (+++) If the initialisation of the internal buffers (coefficients, input, + (+++) If the initialization of the internal buffers (coefficients, input, output) is done via DMA, configure and enable one DMA channel for managing data transfer from memory to memory (preload channel). (+++) If the input buffer is accessed via DMA, configure and enable one @@ -64,7 +77,7 @@ Optionally, he can also disable the interrupt using __HAL_FMAC_DISABLE_IT; the error status will be kept, but no more interrupt will be triggered. (++) Write the provided coefficients into the internal memory using polling - mode (HAL_FMAC_FilterConfig()) or DMA (HAL_FMAC_FilterConfig_DMA()). + mode ( HAL_FMAC_FilterConfig() ) or DMA ( HAL_FMAC_FilterConfig_DMA() ). In the DMA case, HAL_FMAC_FilterConfigCallback() is called when the handling is over. @@ -73,7 +86,7 @@ filter. If a saturation occurs, the interruption will be triggered in loop. In order to recover, the user will have to: (++) Disable the interruption by calling __HAL_FMAC_DISABLE_IT if - he wishes to continue all the same. + the user wishes to continue all the same. (++) Reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init. (#) Optionally, preload input (FIR, IIR) and output (IIR) data using @@ -137,8 +150,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_FMAC_RegisterCallback() to register a user callback. - Function @ref HAL_FMAC_RegisterCallback() allows to register following callbacks: + Use Function HAL_FMAC_RegisterCallback() to register a user callback. + Function HAL_FMAC_RegisterCallback() allows to register following callbacks: (+) ErrorCallback : Error Callback. (+) HalfGetDataCallback : Get Half Data Callback. (+) GetDataCallback : Get Data Callback. @@ -152,9 +165,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_FMAC_UnRegisterCallback() to reset a callback to the default + Use function HAL_FMAC_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle + HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID. This function allows to reset following callbacks: (+) ErrorCallback : Error Callback. @@ -168,13 +181,13 @@ (+) MspDeInitCallback : FMAC MspDeInit. [..] - By default, after the @ref HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET + By default, after the HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_FMAC_TxCpltCallback(), @ref HAL_FMAC_RxHalfCpltCallback(). + examples GetDataCallback(), OutputDataReadyCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_FMAC_Init() - and @ref HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_FMAC_Init() and @ref HAL_FMAC_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_FMAC_Init() + and HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_FMAC_Init() and HAL_FMAC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -183,8 +196,8 @@ in HAL_FMAC_STATE_READY or HAL_FMAC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_FMAC_RegisterCallback() before calling @ref HAL_FMAC_DeInit() - or @ref HAL_FMAC_Init() function. + using HAL_FMAC_RegisterCallback() before calling HAL_FMAC_DeInit() + or HAL_FMAC_Init() function. [..] When the compilation define USE_HAL_FMAC_REGISTER_CALLBACKS is set to 0 or @@ -194,18 +207,6 @@ @endverbatim * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -219,11 +220,10 @@ */ /** @defgroup FMAC FMAC - * @brief FMAC HAL driver modules + * @brief FMAC HAL driver module * @{ */ -/* External variables --------------------------------------------------------*/ /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ /** @defgroup FMAC_Private_Constants FMAC Private Constants @@ -231,12 +231,23 @@ */ #define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU) +#define MAX_PRELOAD_INDEX 0xFFU #define PRELOAD_ACCESS_DMA 0x00U #define PRELOAD_ACCESS_POLLING 0x01U #define POLLING_DISABLED 0U #define POLLING_ENABLED 1U #define POLLING_NOT_STOPPED 0U #define POLLING_STOPPED 1U +/* FMAC polling-based communications time-out value */ +#define HAL_FMAC_TIMEOUT_VALUE 1000U +/* FMAC reset time-out value */ +#define HAL_FMAC_RESET_TIMEOUT_VALUE 500U +/* DMA Read Requests Enable */ +#define FMAC_DMA_REN FMAC_CR_DMAREN +/* DMA Write Channel Enable */ +#define FMAC_DMA_WEN FMAC_CR_DMAWEN +/* FMAC Execution Enable */ +#define FMAC_START FMAC_PARAM_START /** * @} @@ -296,40 +307,27 @@ ((((__HANDLE__)->Instance->PARAM) & (FMAC_PARAM_START)) >> (FMAC_PARAM_START_Pos)) /** - * @brief Get the threshold matching the watermak. - * @param __WM__ Watermark value. - * @retval THRESHOLD - */ -#define FMAC_GET_THRESHOLD_FROM_WM(__WM__) ((__WM__ == FMAC_THRESHOLD_1)? 1U: \ - (__WM__ == FMAC_THRESHOLD_2)? 2U: \ - (__WM__ == FMAC_THRESHOLD_4)? 4U:8U) - -/** - * @brief Check whether the threshold is applicable. - * @param __SIZE__ Size of the matching buffer. + * @brief Get the threshold matching the watermark. * @param __WM__ Watermark value. - * @param __ACCESS__ Access to the buffer (polling, it, dma, none). * @retval THRESHOLD */ -#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \ - ((__WM__) == FMAC_THRESHOLD_2)? 2U: \ - ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \ - ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&&((__WM__) == FMAC_THRESHOLD_1))|| \ - ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA))) +#define FMAC_GET_THRESHOLD_FROM_WM(__WM__) (((__WM__) == FMAC_THRESHOLD_1)? 1U: \ + ((__WM__) == FMAC_THRESHOLD_2)? 2U: \ + ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U) /** * @} */ /* Private variables ---------------------------------------------------------*/ - +/* Global variables ----------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac); static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac); -static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig, +static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig, uint8_t PreloadAccess); static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess); @@ -349,7 +347,7 @@ static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma); static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma); static void FMAC_DMAError(DMA_HandleTypeDef *hdma); -/* Private functions ---------------------------------------------------------*/ +/* Functions Definition ------------------------------------------------------*/ /** @defgroup FMAC_Exported_Functions FMAC Exported Functions * @{ @@ -367,6 +365,8 @@ static void FMAC_DMAError(DMA_HandleTypeDef *hdma); (+) DeInitialize the FMAC peripheral (+) Initialize the FMAC MSP (MCU Specific Package) (+) De-Initialize the FMAC MSP + (+) Register a User FMAC Callback + (+) Unregister a FMAC CallBack [..] @@ -377,10 +377,12 @@ static void FMAC_DMAError(DMA_HandleTypeDef *hdma); /** * @brief Initialize the FMAC peripheral and the associated handle. * @param hfmac pointer to a FMAC_HandleTypeDef structure. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac) { + HAL_StatusTypeDef status; + /* Check the FMAC handle allocation */ if (hfmac == NULL) { @@ -392,7 +394,7 @@ HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac) if (hfmac->State == HAL_FMAC_STATE_RESET) { - /* Allocate lock resource and initialize it */ + /* Initialize lock resource */ hfmac->Lock = HAL_UNLOCKED; #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1) @@ -419,36 +421,36 @@ HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac) } /* Reset pInput and pOutput */ - hfmac->FilterParam = 0UL; + hfmac->FilterParam = 0U; FMAC_ResetDataPointers(hfmac); /* Reset FMAC unit (internal pointers) */ - if (FMAC_Reset(hfmac) == HAL_TIMEOUT) + if (FMAC_Reset(hfmac) == HAL_ERROR) { /* Update FMAC error code and FMAC peripheral state */ - hfmac->ErrorCode = HAL_FMAC_ERROR_RESET; + hfmac->ErrorCode |= HAL_FMAC_ERROR_RESET; hfmac->State = HAL_FMAC_STATE_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hfmac); - - return HAL_TIMEOUT; + status = HAL_ERROR; } + else + { + /* Update FMAC error code and FMAC peripheral state */ + hfmac->ErrorCode = HAL_FMAC_ERROR_NONE; + hfmac->State = HAL_FMAC_STATE_READY; - /* Update FMAC error code and FMAC peripheral state */ - hfmac->ErrorCode = HAL_FMAC_ERROR_NONE; - hfmac->State = HAL_FMAC_STATE_READY; + status = HAL_OK; + } - /* Process Unlocked */ __HAL_UNLOCK(hfmac); - return HAL_OK; + return status; } /** * @brief De-initialize the FMAC peripheral. * @param hfmac pointer to a FMAC structure. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac) { @@ -468,7 +470,7 @@ HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac) hfmac->ErrorCode = HAL_FMAC_ERROR_NONE; /* Reset pInput and pOutput */ - hfmac->FilterParam = 0UL; + hfmac->FilterParam = 0U; FMAC_ResetDataPointers(hfmac); #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1) @@ -486,10 +488,9 @@ HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac) /* Change FMAC peripheral state */ hfmac->State = HAL_FMAC_STATE_RESET; - /* Release Lock */ + /* Always release Lock in case of de-initialization */ __HAL_UNLOCK(hfmac); - /* Return function status */ return HAL_OK; } @@ -525,8 +526,8 @@ __weak void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac) #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1) /** - * @brief Register a User FMAC Callback - * to be used instead of the weak predefined callback. + * @brief Register a User FMAC Callback. + * @note The User FMAC Callback is to be used instead of the weak predefined callback. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param CallbackID ID of the callback to be registered. @@ -541,13 +542,19 @@ __weak void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac) * @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID * @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID * @param pCallback pointer to the Callback function. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID, pFMAC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; + /* Check the FMAC handle allocation */ + if (hfmac == NULL) + { + return HAL_ERROR; + } + if (pCallback == NULL) { /* Update the error code */ @@ -555,10 +562,9 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_ return HAL_ERROR; } - /* Process locked */ __HAL_LOCK(hfmac); - if (HAL_FMAC_STATE_READY == hfmac->State) + if (hfmac->State == HAL_FMAC_STATE_READY) { switch (CallbackID) { @@ -607,7 +613,7 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_ break; } } - else if (HAL_FMAC_STATE_RESET == hfmac->State) + else if (hfmac->State == HAL_FMAC_STATE_RESET) { switch (CallbackID) { @@ -637,7 +643,6 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_ status = HAL_ERROR; } - /* Release Lock */ __HAL_UNLOCK(hfmac); return status; @@ -645,7 +650,7 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_ /** * @brief Unregister a FMAC CallBack. - * FMAC callback is redirected to the weak predefined callback. + * @note The FMAC callback is redirected to the weak predefined callback. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module * @param CallbackID ID of the callback to be unregistered. @@ -659,53 +664,61 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_ * @arg @ref HAL_FMAC_FILTER_PRELOAD_CB_ID Filter Preload Callback ID * @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID * @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ + /* Check the FMAC handle allocation */ + if (hfmac == NULL) + { + return HAL_ERROR; + } + __HAL_LOCK(hfmac); - if (HAL_FMAC_STATE_READY == hfmac->State) + if (hfmac->State == HAL_FMAC_STATE_READY) { switch (CallbackID) { case HAL_FMAC_ERROR_CB_ID : - hfmac->ErrorCallback = HAL_FMAC_ErrorCallback; /* Legacy weak ErrorCallback */ + hfmac->ErrorCallback = HAL_FMAC_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_FMAC_HALF_GET_DATA_CB_ID : - hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback; /* Legacy weak HalfGetDataCallback */ + hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback; /* Legacy weak HalfGetDataCallback */ break; case HAL_FMAC_GET_DATA_CB_ID : - hfmac->GetDataCallback = HAL_FMAC_GetDataCallback; /* Legacy weak GetDataCallback */ + hfmac->GetDataCallback = HAL_FMAC_GetDataCallback; /* Legacy weak GetDataCallback */ break; case HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID : - hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback; /* Legacy weak HalfOutputDataReadyCallback */ + hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback; /* Legacy weak + HalfOutputDataReadyCallback */ break; case HAL_FMAC_OUTPUT_DATA_READY_CB_ID : - hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback; /* Legacy weak OutputDataReadyCallback */ + hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback; /* Legacy weak + OutputDataReadyCallback */ break; case HAL_FMAC_FILTER_CONFIG_CB_ID : - hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback; /* Legacy weak FilterConfigCallback */ + hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback; /* Legacy weak + FilterConfigCallback */ break; case HAL_FMAC_FILTER_PRELOAD_CB_ID : - hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback; /* Legacy weak FilterPreloadCallback */ + hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback; /* Legacy weak FilterPreloadCallba */ break; case HAL_FMAC_MSPINIT_CB_ID : - hfmac->MspInitCallback = HAL_FMAC_MspInit; /* Legacy weak MspInitCallback */ + hfmac->MspInitCallback = HAL_FMAC_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_FMAC_MSPDEINIT_CB_ID : - hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit; /* Legacy weak MspDeInitCallback */ + hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -717,7 +730,7 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA break; } } - else if (HAL_FMAC_STATE_RESET == hfmac->State) + else if (hfmac->State == HAL_FMAC_STATE_RESET) { switch (CallbackID) { @@ -747,7 +760,6 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA status = HAL_ERROR; } - /* Release Lock */ __HAL_UNLOCK(hfmac); return status; @@ -778,38 +790,40 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA */ /** - * @brief Configure the FMAC filter according to the parameters + * @brief Configure the FMAC filter. + * @note The configuration is done according to the parameters * specified in the FMAC_FilterConfigTypeDef structure. * The provided data will be loaded using polling mode. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. - * @param sConfig pointer to a FMAC_FilterConfigTypeDef structure that + * @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that * contains the FMAC configuration information. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ -HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig) +HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig) { - return (FMAC_FilterConfig(hfmac, sConfig, PRELOAD_ACCESS_POLLING)); + return (FMAC_FilterConfig(hfmac, pConfig, PRELOAD_ACCESS_POLLING)); } /** - * @brief Configure the FMAC filter according to the parameters + * @brief Configure the FMAC filter. + * @note The configuration is done according to the parameters * specified in the FMAC_FilterConfigTypeDef structure. * The provided data will be loaded using DMA. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. - * @param sConfig pointer to a FMAC_FilterConfigTypeDef structure that + * @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that * contains the FMAC configuration information. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ -HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig) +HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig) { - return (FMAC_FilterConfig(hfmac, sConfig, PRELOAD_ACCESS_DMA)); + return (FMAC_FilterConfig(hfmac, pConfig, PRELOAD_ACCESS_DMA)); } /** * @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter. - * They will be used by FMAC as soon as HAL_FMAC_FilterStart is called. + * @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called. * The provided data will be loaded using polling mode. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. @@ -821,10 +835,10 @@ HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_Filt * If not needed, it should be set to NULL. * @param OutputSize Size of the output vector. * As pOutput is used for preloading data, it cannot be bigger than the output memory area. - * @note The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload + * @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload * (each call filling partly the buffers). In case of overflow (too much data provided through * all these calls), an error will be returned. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize) @@ -834,7 +848,7 @@ HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pIn /** * @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter. - * They will be used by FMAC as soon as HAL_FMAC_FilterStart is called. + * @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called. * The provided data will be loaded using DMA. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. @@ -846,10 +860,10 @@ HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pIn * If not needed, it should be set to NULL. * @param OutputSize Size of the output vector. * As pOutput is used for preloading data, it cannot be bigger than the output memory area. - * @note The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload + * @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload * (each call filling partly the buffers). In case of overflow (too much data provided through * all these calls), an error will be returned. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize) @@ -867,21 +881,21 @@ HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t * If it is set to NULL, the output will not be read and it will be up to * an external IP to empty the output buffer. * @param pOutputSize pointer to the size of the output buffer. The number of read data will be written here. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize) { - uint32_t tmpcr = 0UL; + uint32_t tmpcr = 0U; HAL_StatusTypeDef status; /* Check the START bit state */ - if (FMAC_GET_START_BIT(hfmac) != 0UL) + if (FMAC_GET_START_BIT(hfmac) != 0U) { return HAL_ERROR; } /* Check that a valid configuration was done previously */ - if (hfmac->FilterParam == 0UL) + if (hfmac->FilterParam == 0U) { return HAL_ERROR; } @@ -936,34 +950,27 @@ HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutp /* Reset the busy flag (do not overwrite the possible write and read flag) */ hfmac->State = HAL_FMAC_STATE_READY; - - /* Return function status */ - return status; } else { - /* Return function status */ - return HAL_BUSY; + status = HAL_ERROR; } + + return status; } /** - * @brief Provide a new input buffer that will be loaded into the FMAC - * input memory area. + * @brief Provide a new input buffer that will be loaded into the FMAC input memory area. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param pInput New input vector (additional input data). * @param pInputSize Size of the input vector (if all the data can't be * written, it will be updated with the number of data read from FMAC). - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize) { - /* Check the START bit state */ - if (FMAC_GET_START_BIT(hfmac) == 0UL) - { - return HAL_ERROR; - } + HAL_StatusTypeDef status; /* Check the function parameters */ if ((pInput == NULL) || (pInputSize == NULL)) @@ -975,6 +982,12 @@ HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t * return HAL_ERROR; } + /* Check the START bit state */ + if (FMAC_GET_START_BIT(hfmac) == 0U) + { + return HAL_ERROR; + } + /* Check the FMAC configuration */ if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_NONE) { @@ -984,40 +997,36 @@ HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t * /* Check whether the previous input vector has been handled */ if ((hfmac->pInputSize != NULL) && (hfmac->InputCurrentSize < * (hfmac->pInputSize))) { - return HAL_BUSY; + return HAL_ERROR; } /* Check that FMAC was initialized and that no writing is already ongoing */ if (hfmac->WrState == HAL_FMAC_STATE_READY) { /* Register the new input buffer */ - return (FMAC_AppendFilterDataUpdateState(hfmac, pInput, pInputSize)); + status = FMAC_AppendFilterDataUpdateState(hfmac, pInput, pInputSize); } else { - /* Return function status */ - return HAL_BUSY; + status = HAL_ERROR; } + + return status; } /** - * @brief Provide a new output buffer to be filled with the data - * computed by FMAC unit. + * @brief Provide a new output buffer to be filled with the data computed by FMAC unit. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param pOutput New output vector. * @param pOutputSize Size of the output vector (if the vector can't * be entirely filled, pOutputSize will be updated with the number * of data read from FMAC). - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize) { - /* Check the START bit state */ - if (FMAC_GET_START_BIT(hfmac) == 0UL) - { - return HAL_ERROR; - } + HAL_StatusTypeDef status; /* Check the function parameters */ if ((pOutput == NULL) || (pOutputSize == NULL)) @@ -1029,6 +1038,12 @@ HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, i return HAL_ERROR; } + /* Check the START bit state */ + if (FMAC_GET_START_BIT(hfmac) == 0U) + { + return HAL_ERROR; + } + /* Check the FMAC configuration */ if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_NONE) { @@ -1038,25 +1053,27 @@ HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, i /* Check whether the previous output vector has been handled */ if ((hfmac->pOutputSize != NULL) && (hfmac->OutputCurrentSize < * (hfmac->pOutputSize))) { - return HAL_BUSY; + return HAL_ERROR; } /* Check that FMAC was initialized and that not reading is already ongoing */ if (hfmac->RdState == HAL_FMAC_STATE_READY) { /* Register the new output buffer */ - return (FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize)); + status = FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize); } else { - /* Return function status */ - return HAL_BUSY; + status = HAL_ERROR; } + + return status; } /** - * @brief Write the previously provided user's input data and - * fill the previously provided user's output buffer, + * @brief Handle the input and/or output data in polling mode + * @note This function writes the previously provided user's input data and + * fills the previously provided user's output buffer, * according to the existing FMAC configuration (polling mode only). * The function returns when the input data has been handled or * when the output data is filled. The possible unused data isn't @@ -1066,7 +1083,7 @@ HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, i * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param Timeout timeout value. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Timeout) { @@ -1075,9 +1092,10 @@ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Ti uint8_t inpollingover = POLLING_NOT_STOPPED; uint8_t outpolling; uint8_t outpollingover = POLLING_NOT_STOPPED; + HAL_StatusTypeDef status; /* Check the START bit state */ - if (FMAC_GET_START_BIT(hfmac) == 0UL) + if (FMAC_GET_START_BIT(hfmac) == 0U) { return HAL_ERROR; } @@ -1162,41 +1180,40 @@ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Ti /* Reset the busy flag (do not overwrite the possible write and read flag) */ hfmac->State = HAL_FMAC_STATE_READY; - /* Return function status */ if ((HAL_GetTick() - tickstart) >= Timeout) { - return HAL_TIMEOUT; + hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; + status = HAL_ERROR; } else { - return HAL_OK; + status = HAL_OK; } } else { - /* Return function status */ - return HAL_BUSY; + status = HAL_ERROR; } + + return status; } /** * @brief Stop the FMAC processing. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) { - - /* Check the START bit state */ - if (FMAC_GET_START_BIT(hfmac) == 0UL) - { - return HAL_ERROR; - } + HAL_StatusTypeDef status; /* Check handle state is ready */ if (hfmac->State == HAL_FMAC_STATE_READY) { + /* Change the FMAC state */ + hfmac->State = HAL_FMAC_STATE_BUSY; + /* Set the START bit to 0 (stop the previously configured filter) */ CLEAR_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START); @@ -1214,25 +1231,30 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) } /* Reset FMAC unit (internal pointers) */ - if (FMAC_Reset(hfmac) == HAL_TIMEOUT) + if (FMAC_Reset(hfmac) == HAL_ERROR) { /* Update FMAC error code and FMAC peripheral state */ hfmac->ErrorCode = HAL_FMAC_ERROR_RESET; hfmac->State = HAL_FMAC_STATE_TIMEOUT; - return HAL_TIMEOUT; + status = HAL_ERROR; } + else + { + /* Reset the data pointers */ + FMAC_ResetDataPointers(hfmac); - /* Reset the data pointers */ - FMAC_ResetDataPointers(hfmac); + status = HAL_OK; + } - /* Return function status */ - return HAL_OK; + /* Reset the busy flag */ + hfmac->State = HAL_FMAC_STATE_READY; } else { - /* Return function status */ - return HAL_BUSY; + status = HAL_ERROR; } + + return status; } /** @@ -1398,7 +1420,7 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac) /* Check if the read interrupt is enabled and if Y buffer empty flag isn't set */ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_RIEN); - if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_YEMPTY) == 0U) && (itsource != 0UL)) + if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_YEMPTY) == 0U) && (itsource != 0U)) { /* Read some data if possible (Y size is used as a pseudo timeout in order to not get stuck too long under IT if FMAC keeps on processing input @@ -1425,7 +1447,7 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac) /* Check if the write interrupt is enabled and if X1 buffer full flag isn't set */ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_WIEN); - if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_X1FULL) == 0U) && (itsource != 0UL)) + if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_X1FULL) == 0U) && (itsource != 0U)) { /* Write some data if possible (X1 size is used as a pseudo timeout in order to not get stuck too long under IT if FMAC keep on processing input @@ -1452,21 +1474,21 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac) /* Check if the overflow error interrupt is enabled and if overflow error flag is raised */ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_OVFLIEN); - if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL) != 0U) && (itsource != 0UL)) + if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL) != 0U) && (itsource != 0U)) { hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL; } /* Check if the underflow error interrupt is enabled and if underflow error flag is raised */ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_UNFLIEN); - if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL) != 0U) && (itsource != 0UL)) + if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL) != 0U) && (itsource != 0U)) { hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL; } /* Check if the saturation error interrupt is enabled and if saturation error flag is raised */ itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_SATIEN); - if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT) != 0U) && (itsource != 0UL)) + if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT) != 0U) && (itsource != 0U)) { hfmac->ErrorCode |= HAL_FMAC_ERROR_SAT; } @@ -1487,29 +1509,30 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac) * @} */ -/** @defgroup FMAC_Exported_Functions_Group5 Peripheral State functions - * @brief Peripheral State functions. +/** @defgroup FMAC_Exported_Functions_Group5 Peripheral State and Error functions + * @brief Peripheral State and Error functions. * @verbatim ============================================================================== - ##### Peripheral State functions ##### + ##### Peripheral State and Error functions ##### ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral. + [..] This subsection provides functions allowing to + (+) Check the FMAC state + (+) Get error code @endverbatim * @{ */ /** - * @brief Return the FMAC handle state. + * @brief Return the FMAC state. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. - * @retval HAL state + * @retval HAL_FMAC_StateTypeDef FMAC state */ HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac) { - /* Return FMAC handle state */ + /* Return FMAC state */ return hfmac->State; } @@ -1518,7 +1541,7 @@ HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac) * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @note The returned error is a bit-map combination of possible errors. - * @retval Error bit-map + * @retval uint32_t Error bit-map based on @ref FMAC_Error_Code */ uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac) { @@ -1546,7 +1569,7 @@ uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac) /** * @brief Perform a reset of the FMAC unit. * @param hfmac FMAC handle. - * @retval FMAC status + * @retval HAL_StatusTypeDef HAL status */ static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac) { @@ -1559,11 +1582,12 @@ static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac) SET_BIT(hfmac->Instance->CR, FMAC_CR_RESET); /* Wait until flag is reset */ - while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0UL) + while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0U) { if ((HAL_GetTick() - tickstart) > HAL_FMAC_RESET_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; + return HAL_ERROR; } } @@ -1574,7 +1598,7 @@ static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac) /** * @brief Reset the data pointers of the FMAC unit. * @param hfmac FMAC handle. - * @retval FMAC status + * @retval None */ static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac) { @@ -1585,7 +1609,7 @@ static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac) /** * @brief Reset the input data pointers of the FMAC unit. * @param hfmac FMAC handle. - * @retval FMAC status + * @retval None */ static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac) { @@ -1598,7 +1622,7 @@ static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac) /** * @brief Reset the output data pointers of the FMAC unit. * @param hfmac FMAC handle. - * @retval FMAC status + * @retval None */ static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac) { @@ -1609,19 +1633,17 @@ static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac) } /** - * @brief Configure the FMAC filter according to the parameters - specified in the FMAC_FilterConfigTypeDef structure. + * @brief Configure the FMAC filter. + * @note The configuration is done according to the parameters + * specified in the FMAC_FilterConfigTypeDef structure. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. - * @param sConfig pointer to a FMAC_FilterConfigTypeDef structure that + * @param pConfig pointer to a FMAC_FilterConfigTypeDef structure that * contains the FMAC configuration information. - * @param PreloadAccess buffer preload method - * This parameter can be one of the following values: - * @arg @ref PRELOAD_ACCESS_POLLING preloading using CPU - * @arg @ref PRELOAD_ACCESS_DMA Get preloading using DMA - * @retval HAL status + * @param PreloadAccess access mode used for the preload (polling or DMA). + * @retval HAL_StatusTypeDef HAL status */ -static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig, +static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig, uint8_t PreloadAccess) { uint32_t tickstart; @@ -1631,193 +1653,193 @@ static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_Filte #endif /* USE_FULL_ASSERT */ /* Check the parameters */ - assert_param(IS_FMAC_THRESHOLD(sConfig->InputThreshold)); - assert_param(IS_FMAC_THRESHOLD(sConfig->OutputThreshold)); - assert_param(IS_FMAC_BUFFER_ACCESS(sConfig->InputAccess)); - assert_param(IS_FMAC_BUFFER_ACCESS(sConfig->OutputAccess)); - assert_param(IS_FMAC_CLIP_STATE(sConfig->Clip)); - assert_param(IS_FMAC_FILTER_FUNCTION(sConfig->Filter)); - assert_param(IS_FMAC_PARAM_P(sConfig->Filter, sConfig->P)); - assert_param(IS_FMAC_PARAM_Q(sConfig->Filter, sConfig->Q)); - assert_param(IS_FMAC_PARAM_R(sConfig->Filter, sConfig->R)); + assert_param(IS_FMAC_THRESHOLD(pConfig->InputThreshold)); + assert_param(IS_FMAC_THRESHOLD(pConfig->OutputThreshold)); + assert_param(IS_FMAC_BUFFER_ACCESS(pConfig->InputAccess)); + assert_param(IS_FMAC_BUFFER_ACCESS(pConfig->OutputAccess)); + assert_param(IS_FMAC_CLIP_STATE(pConfig->Clip)); + assert_param(IS_FMAC_FILTER_FUNCTION(pConfig->Filter)); + assert_param(IS_FMAC_PARAM_P(pConfig->Filter, pConfig->P)); + assert_param(IS_FMAC_PARAM_Q(pConfig->Filter, pConfig->Q)); + assert_param(IS_FMAC_PARAM_R(pConfig->Filter, pConfig->R)); /* Check the START bit state */ - if (FMAC_GET_START_BIT(hfmac) != 0UL) + if (FMAC_GET_START_BIT(hfmac) != 0U) { return HAL_ERROR; } /* Check handle state is ready */ - if (hfmac->State == HAL_FMAC_STATE_READY) + if (hfmac->State != HAL_FMAC_STATE_READY) { - /* Change the FMAC state */ - hfmac->State = HAL_FMAC_STATE_BUSY; + return HAL_ERROR; + } - /* Get tick */ - tickstart = HAL_GetTick(); + /* Change the FMAC state */ + hfmac->State = HAL_FMAC_STATE_BUSY; - /* Indicate that there is no valid configuration done */ - hfmac->FilterParam = 0UL; + /* Get tick */ + tickstart = HAL_GetTick(); - /* FMAC_X1BUFCFG: Configure the input buffer within the internal memory if required */ - if (sConfig->InputBufferSize != 0U) - { - MODIFY_REG(hfmac->Instance->X1BUFCFG, \ - (FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE), \ - (((((uint32_t)(sConfig->InputBaseAddress)) << FMAC_X1BUFCFG_X1_BASE_Pos) & FMAC_X1BUFCFG_X1_BASE) | \ - ((((uint32_t)(sConfig->InputBufferSize)) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & FMAC_X1BUFCFG_X1_BUF_SIZE))); - } + /* Indicate that there is no valid configuration done */ + hfmac->FilterParam = 0U; - /* FMAC_X1BUFCFG: Configure the input threshold if valid when compared to the configured X1 size */ - if (sConfig->InputThreshold != FMAC_THRESHOLD_NO_VALUE) - { - /* Check the parameter */ - assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_X1_SIZE(hfmac), sConfig->InputThreshold, sConfig->InputAccess)); + /* FMAC_X1BUFCFG: Configure the input buffer within the internal memory if required */ + if (pConfig->InputBufferSize != 0U) + { + MODIFY_REG(hfmac->Instance->X1BUFCFG, \ + (FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE), \ + (((((uint32_t)(pConfig->InputBaseAddress)) << FMAC_X1BUFCFG_X1_BASE_Pos) & FMAC_X1BUFCFG_X1_BASE) | \ + ((((uint32_t)(pConfig->InputBufferSize)) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & \ + FMAC_X1BUFCFG_X1_BUF_SIZE))); + } - MODIFY_REG(hfmac->Instance->X1BUFCFG, \ - FMAC_X1BUFCFG_FULL_WM, \ - ((sConfig->InputThreshold) & FMAC_X1BUFCFG_FULL_WM)); - } + /* FMAC_X1BUFCFG: Configure the input threshold if valid when compared to the configured X1 size */ + if (pConfig->InputThreshold != FMAC_THRESHOLD_NO_VALUE) + { + /* Check the parameter */ + assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_X1_SIZE(hfmac), pConfig->InputThreshold, pConfig->InputAccess)); - /* FMAC_X2BUFCFG: Configure the coefficient buffer within the internal memory */ - if (sConfig->CoeffBufferSize != 0U) - { - MODIFY_REG(hfmac->Instance->X2BUFCFG, \ - (FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE), \ - (((((uint32_t)(sConfig->CoeffBaseAddress)) << FMAC_X2BUFCFG_X2_BASE_Pos) & FMAC_X2BUFCFG_X2_BASE) | \ - ((((uint32_t)(sConfig->CoeffBufferSize)) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) & FMAC_X2BUFCFG_X2_BUF_SIZE))); - } + MODIFY_REG(hfmac->Instance->X1BUFCFG, \ + FMAC_X1BUFCFG_FULL_WM, \ + ((pConfig->InputThreshold) & FMAC_X1BUFCFG_FULL_WM)); + } - /* FMAC_YBUFCFG: Configure the output buffer within the internal memory if required */ - if (sConfig->OutputBufferSize != 0U) - { - MODIFY_REG(hfmac->Instance->YBUFCFG, \ - (FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE), \ - (((((uint32_t)(sConfig->OutputBaseAddress)) << FMAC_YBUFCFG_Y_BASE_Pos) & FMAC_YBUFCFG_Y_BASE) | \ - ((((uint32_t)(sConfig->OutputBufferSize)) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) & FMAC_YBUFCFG_Y_BUF_SIZE))); - } + /* FMAC_X2BUFCFG: Configure the coefficient buffer within the internal memory */ + if (pConfig->CoeffBufferSize != 0U) + { + MODIFY_REG(hfmac->Instance->X2BUFCFG, \ + (FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE), \ + (((((uint32_t)(pConfig->CoeffBaseAddress)) << FMAC_X2BUFCFG_X2_BASE_Pos) & FMAC_X2BUFCFG_X2_BASE) | \ + ((((uint32_t)(pConfig->CoeffBufferSize)) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) &\ + FMAC_X2BUFCFG_X2_BUF_SIZE))); + } - /* FMAC_YBUFCFG: Configure the output threshold if valid when compared to the configured Y size */ - if (sConfig->OutputThreshold != FMAC_THRESHOLD_NO_VALUE) - { - /* Check the parameter */ - assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_Y_SIZE(hfmac), sConfig->OutputThreshold, sConfig->OutputAccess)); + /* FMAC_YBUFCFG: Configure the output buffer within the internal memory if required */ + if (pConfig->OutputBufferSize != 0U) + { + MODIFY_REG(hfmac->Instance->YBUFCFG, \ + (FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE), \ + (((((uint32_t)(pConfig->OutputBaseAddress)) << FMAC_YBUFCFG_Y_BASE_Pos) & FMAC_YBUFCFG_Y_BASE) | \ + ((((uint32_t)(pConfig->OutputBufferSize)) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) & FMAC_YBUFCFG_Y_BUF_SIZE))); + } - MODIFY_REG(hfmac->Instance->YBUFCFG, \ - FMAC_YBUFCFG_EMPTY_WM, \ - ((sConfig->OutputThreshold) & FMAC_YBUFCFG_EMPTY_WM)); - } + /* FMAC_YBUFCFG: Configure the output threshold if valid when compared to the configured Y size */ + if (pConfig->OutputThreshold != FMAC_THRESHOLD_NO_VALUE) + { + /* Check the parameter */ + assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_Y_SIZE(hfmac), pConfig->OutputThreshold, pConfig->OutputAccess)); - /* CR: Configure the clip feature */ - tmpcr = sConfig->Clip & FMAC_CR_CLIPEN; + MODIFY_REG(hfmac->Instance->YBUFCFG, \ + FMAC_YBUFCFG_EMPTY_WM, \ + ((pConfig->OutputThreshold) & FMAC_YBUFCFG_EMPTY_WM)); + } - /* CR: If IT or DMA will be used, enable error interrupts. - * Being more a debugging feature, FMAC_CR_SATIEN isn't enabled by default. */ - if ((sConfig->InputAccess == FMAC_BUFFER_ACCESS_DMA) || (sConfig->InputAccess == FMAC_BUFFER_ACCESS_IT) || - (sConfig->OutputAccess == FMAC_BUFFER_ACCESS_DMA) || (sConfig->OutputAccess == FMAC_BUFFER_ACCESS_IT)) - { - tmpcr |= FMAC_IT_UNFLIEN | FMAC_IT_OVFLIEN; - } + /* FMAC_CR: Configure the clip feature */ + tmpcr = pConfig->Clip & FMAC_CR_CLIPEN; - /* CR: write the value */ - WRITE_REG(hfmac->Instance->CR, tmpcr); + /* FMAC_CR: If IT or DMA will be used, enable error interrupts. + * Being more a debugging feature, FMAC_CR_SATIEN isn't enabled by default. */ + if ((pConfig->InputAccess == FMAC_BUFFER_ACCESS_DMA) || (pConfig->InputAccess == FMAC_BUFFER_ACCESS_IT) || + (pConfig->OutputAccess == FMAC_BUFFER_ACCESS_DMA) || (pConfig->OutputAccess == FMAC_BUFFER_ACCESS_IT)) + { + tmpcr |= FMAC_IT_UNFLIEN | FMAC_IT_OVFLIEN; + } - /* Save the input/output accesses in order to configure RIEN, WIEN, DMAREN and DMAWEN during filter start */ - hfmac->InputAccess = sConfig->InputAccess; - hfmac->OutputAccess = sConfig->OutputAccess; + /* FMAC_CR: write the value */ + WRITE_REG(hfmac->Instance->CR, tmpcr); - /* Check whether the configured X2 is big enough for the filter */ + /* Save the input/output accesses in order to configure RIEN, WIEN, DMAREN and DMAWEN during filter start */ + hfmac->InputAccess = pConfig->InputAccess; + hfmac->OutputAccess = pConfig->OutputAccess; + + /* Check whether the configured X2 is big enough for the filter */ #if defined(USE_FULL_ASSERT) - x2size = FMAC_GET_X2_SIZE(hfmac); + x2size = FMAC_GET_X2_SIZE(hfmac); #endif /* USE_FULL_ASSERT */ - assert_param(((sConfig->Filter == FMAC_FUNC_CONVO_FIR) && (x2size >= sConfig->P)) || \ - ((sConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && (x2size >= ((uint32_t)sConfig->P + (uint32_t)sConfig->Q)))); + assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) && (x2size >= pConfig->P)) || \ + ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ + (x2size >= ((uint32_t)pConfig->P + (uint32_t)pConfig->Q)))); + + /* Build the PARAM value that will be used when starting the filter */ + hfmac->FilterParam = (FMAC_PARAM_START | pConfig->Filter | \ + ((((uint32_t)(pConfig->P)) << FMAC_PARAM_P_Pos) & FMAC_PARAM_P) | \ + ((((uint32_t)(pConfig->Q)) << FMAC_PARAM_Q_Pos) & FMAC_PARAM_Q) | \ + ((((uint32_t)(pConfig->R)) << FMAC_PARAM_R_Pos) & FMAC_PARAM_R)); + + /* Initialize the coefficient buffer if required (pCoeffA for FIR only) */ + if ((pConfig->pCoeffB != NULL) && (pConfig->CoeffBSize != 0U)) + { + /* FIR/IIR: The provided coefficients should match X2 size */ + assert_param(((uint32_t)pConfig->CoeffASize + (uint32_t)pConfig->CoeffBSize) <= x2size); + /* FIR/IIR: The size of pCoeffB should match the parameter P */ + assert_param(pConfig->CoeffBSize >= pConfig->P); + /* pCoeffA should be provided for IIR but not for FIR */ + /* IIR : if pCoeffB is provided, pCoeffA should also be there */ + /* IIR: The size of pCoeffA should match the parameter Q */ + assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) && + (pConfig->pCoeffA == NULL) && (pConfig->CoeffASize == 0U)) || + ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && + (pConfig->pCoeffA != NULL) && (pConfig->CoeffASize != 0U) && + (pConfig->CoeffASize >= pConfig->Q))); - /* Build the PARAM value that will be used when starting the filter */ - hfmac->FilterParam = (FMAC_PARAM_START | sConfig->Filter | \ - ((((uint32_t)(sConfig->P)) << FMAC_PARAM_P_Pos) & FMAC_PARAM_P) | \ - ((((uint32_t)(sConfig->Q)) << FMAC_PARAM_Q_Pos) & FMAC_PARAM_Q) | \ - ((((uint32_t)(sConfig->R)) << FMAC_PARAM_R_Pos) & FMAC_PARAM_R)); + /* Write number of values to be loaded, the data load function and start the operation */ + WRITE_REG(hfmac->Instance->PARAM, \ + (((uint32_t)(pConfig->CoeffBSize) << FMAC_PARAM_P_Pos) | \ + ((uint32_t)(pConfig->CoeffASize) << FMAC_PARAM_Q_Pos) | \ + FMAC_FUNC_LOAD_X2 | FMAC_PARAM_START)); - /* Initialize the coefficient buffer if required (pCoeffA for FIR only) */ - if ((sConfig->pCoeffB != NULL) && (sConfig->CoeffBSize != 0U)) + if (PreloadAccess == PRELOAD_ACCESS_POLLING) { - /* FIR/IIR: The provided coefficients should match X2 size */ - assert_param(((uint32_t)sConfig->CoeffASize + (uint32_t)sConfig->CoeffBSize) <= x2size); - /* FIR/IIR: The size of pCoeffB should match the parameter P */ - assert_param(sConfig->CoeffBSize >= sConfig->P); - /* pCoeffA should be provided for IIR but not for FIR */ - /* IIR : if pCoeffB is provided, pCoeffA should also be there */ - /* IIR: The size of pCoeffA should match the parameter Q */ - assert_param(((sConfig->Filter == FMAC_FUNC_CONVO_FIR) && - (sConfig->pCoeffA == NULL) && (sConfig->CoeffASize == 0U)) || - ((sConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && - (sConfig->pCoeffA != NULL) && (sConfig->CoeffASize != 0U) && - (sConfig->CoeffASize >= sConfig->Q))); - - /* Write number of values to be loaded, the data load function and start the operation */ - WRITE_REG(hfmac->Instance->PARAM, \ - (((uint32_t)(sConfig->CoeffBSize) << FMAC_PARAM_P_Pos) | \ - ((uint32_t)(sConfig->CoeffASize) << FMAC_PARAM_Q_Pos) | \ - FMAC_FUNC_LOAD_X2 | FMAC_PARAM_START)); - - if (PreloadAccess == PRELOAD_ACCESS_POLLING) + /* Load the buffer into the internal memory */ + FMAC_WritePreloadDataIncrementPtr(hfmac, &(pConfig->pCoeffB), pConfig->CoeffBSize); + + /* Load pCoeffA if needed */ + if ((pConfig->pCoeffA != NULL) && (pConfig->CoeffASize != 0U)) { /* Load the buffer into the internal memory */ - FMAC_WritePreloadDataIncrementPtr(hfmac, &(sConfig->pCoeffB), sConfig->CoeffBSize); - - /* Load pCoeffA if needed */ - if ((sConfig->pCoeffA != NULL) && (sConfig->CoeffASize != 0U)) - { - /* Load the buffer into the internal memory */ - FMAC_WritePreloadDataIncrementPtr(hfmac, &(sConfig->pCoeffA), sConfig->CoeffASize); - } - - /* Wait for the end of the writing */ - if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK) - { - hfmac->State = HAL_FMAC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - - /* Change the FMAC state */ - hfmac->State = HAL_FMAC_STATE_READY; + FMAC_WritePreloadDataIncrementPtr(hfmac, &(pConfig->pCoeffA), pConfig->CoeffASize); } - else + + /* Wait for the end of the writing */ + if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK) { - hfmac->pInput = sConfig->pCoeffA; - hfmac->InputCurrentSize = sConfig->CoeffASize; - - /* Set the FMAC DMA transfer complete callback */ - hfmac->hdmaPreload->XferHalfCpltCallback = NULL; - hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig; - /* Set the DMA error callback */ - hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError; - - /* Enable the DMA stream managing FMAC preload data write */ - return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)sConfig->pCoeffB, (uint32_t)&hfmac->Instance->WDATA, - sConfig->CoeffBSize)); + hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; + hfmac->State = HAL_FMAC_STATE_TIMEOUT; + return HAL_ERROR; } + + /* Change the FMAC state */ + hfmac->State = HAL_FMAC_STATE_READY; } else { - /* Change the FMAC state */ - hfmac->State = HAL_FMAC_STATE_READY; + hfmac->pInput = pConfig->pCoeffA; + hfmac->InputCurrentSize = pConfig->CoeffASize; + + /* Set the FMAC DMA transfer complete callback */ + hfmac->hdmaPreload->XferHalfCpltCallback = NULL; + hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig; + /* Set the DMA error callback */ + hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError; + + /* Enable the DMA stream managing FMAC preload data write */ + return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pConfig->pCoeffB, (uint32_t)&hfmac->Instance->WDATA, + pConfig->CoeffBSize)); } } else { - /* Return function status */ - return HAL_BUSY; + /* Change the FMAC state */ + hfmac->State = HAL_FMAC_STATE_READY; } - /* Return function status */ return HAL_OK; } /** * @brief Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter. - * They will be used by FMAC as soon as HAL_FMAC_FilterStart is called. + * @note The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param pInput Preloading of the first elements of the input buffer (X1). @@ -1828,28 +1850,26 @@ static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_Filte * If not needed, it should be set to NULL. * @param OutputSize Size of the output vector. * As pOutput is used for preloading data, it cannot be bigger than the output memory area. - * @param PreloadAccess buffer preload method - * This parameter can be one of the following values: - * @arg @ref PRELOAD_ACCESS_POLLING preloading using CPU - * @arg @ref PRELOAD_ACCESS_DMA Get preloading using DMA - * @note The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload + * @param PreloadAccess access mode used for the preload (polling or DMA). + * @note The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload * (each call filling partly the buffers). In case of overflow (too much data provided through * all these calls), an error will be returned. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize, int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess) { uint32_t tickstart; + HAL_StatusTypeDef status; /* Check the START bit state */ - if (FMAC_GET_START_BIT(hfmac) != 0UL) + if (FMAC_GET_START_BIT(hfmac) != 0U) { return HAL_ERROR; } /* Check that a valid configuration was done previously */ - if (hfmac->FilterParam == 0UL) + if (hfmac->FilterParam == 0U) { return HAL_ERROR; } @@ -1867,122 +1887,126 @@ static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t * } /* Check handle state is ready */ - if (hfmac->State == HAL_FMAC_STATE_READY) + if (hfmac->State != HAL_FMAC_STATE_READY) { - /* Change the FMAC state */ - hfmac->State = HAL_FMAC_STATE_BUSY; + return HAL_ERROR; + } - /* Get tick */ - tickstart = HAL_GetTick(); + /* Change the FMAC state */ + hfmac->State = HAL_FMAC_STATE_BUSY; + + /* Get tick */ + tickstart = HAL_GetTick(); - /* Preload the input buffer if required */ - if ((pInput != NULL) && (InputSize != 0U)) + /* Preload the input buffer if required */ + if ((pInput != NULL) && (InputSize != 0U)) + { + /* Write number of values to be loaded, the data load function and start the operation */ + WRITE_REG(hfmac->Instance->PARAM, \ + (((uint32_t)InputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_X1 | FMAC_PARAM_START)); + + if (PreloadAccess == PRELOAD_ACCESS_POLLING) { - /* Write number of values to be loaded, the data load function and start the operation */ - WRITE_REG(hfmac->Instance->PARAM, \ - (((uint32_t)InputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_X1 | FMAC_PARAM_START)); + /* Load the buffer into the internal memory */ + FMAC_WritePreloadDataIncrementPtr(hfmac, &pInput, InputSize); - if (PreloadAccess == PRELOAD_ACCESS_POLLING) + /* Wait for the end of the writing */ + if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK) { - /* Load the buffer into the internal memory */ - FMAC_WritePreloadDataIncrementPtr(hfmac, &pInput, InputSize); - - /* Wait for the end of the writing */ - if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK) - { - hfmac->State = HAL_FMAC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } + hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; + hfmac->State = HAL_FMAC_STATE_TIMEOUT; + return HAL_ERROR; } - else - { - hfmac->pInput = pOutput; - hfmac->InputCurrentSize = OutputSize; + } + else + { + hfmac->pInput = pOutput; + hfmac->InputCurrentSize = OutputSize; - /* Set the FMAC DMA transfer complete callback */ - hfmac->hdmaPreload->XferHalfCpltCallback = NULL; - hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload; - /* Set the DMA error callback */ - hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError; + /* Set the FMAC DMA transfer complete callback */ + hfmac->hdmaPreload->XferHalfCpltCallback = NULL; + hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload; + /* Set the DMA error callback */ + hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError; - /* Enable the DMA stream managing FMAC preload data write */ - return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, (uint32_t)&hfmac->Instance->WDATA, InputSize)); - } + /* Enable the DMA stream managing FMAC preload data write */ + return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, (uint32_t)&hfmac->Instance->WDATA, InputSize)); } + } - /* Preload the output buffer if required */ - if ((pOutput != NULL) && (OutputSize != 0U)) + /* Preload the output buffer if required */ + if ((pOutput != NULL) && (OutputSize != 0U)) + { + /* Write number of values to be loaded, the data load function and start the operation */ + WRITE_REG(hfmac->Instance->PARAM, \ + (((uint32_t)OutputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START)); + + if (PreloadAccess == PRELOAD_ACCESS_POLLING) { - /* Write number of values to be loaded, the data load function and start the operation */ - WRITE_REG(hfmac->Instance->PARAM, \ - (((uint32_t)OutputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START)); + /* Load the buffer into the internal memory */ + FMAC_WritePreloadDataIncrementPtr(hfmac, &pOutput, OutputSize); - if (PreloadAccess == PRELOAD_ACCESS_POLLING) + /* Wait for the end of the writing */ + if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK) { - /* Load the buffer into the internal memory */ - FMAC_WritePreloadDataIncrementPtr(hfmac, &pOutput, OutputSize); - - /* Wait for the end of the writing */ - if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK) - { - hfmac->State = HAL_FMAC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } + hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; + hfmac->State = HAL_FMAC_STATE_TIMEOUT; + return HAL_ERROR; } - else - { - hfmac->pInput = NULL; - hfmac->InputCurrentSize = 0U; + } + else + { + hfmac->pInput = NULL; + hfmac->InputCurrentSize = 0U; - /* Set the FMAC DMA transfer complete callback */ - hfmac->hdmaPreload->XferHalfCpltCallback = NULL; - hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload; - /* Set the DMA error callback */ - hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError; + /* Set the FMAC DMA transfer complete callback */ + hfmac->hdmaPreload->XferHalfCpltCallback = NULL; + hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload; + /* Set the DMA error callback */ + hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError; - /* Enable the DMA stream managing FMAC preload data write */ - return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, (uint32_t)&hfmac->Instance->WDATA, OutputSize)); - } + /* Enable the DMA stream managing FMAC preload data write */ + return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, (uint32_t)&hfmac->Instance->WDATA, OutputSize)); } + } - /* Update the error codes */ - if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL)) - { - hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL; - } - if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL)) - { - hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL; - } + /* Update the error codes */ + if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL)) + { + hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL; + } + if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL)) + { + hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL; + } + if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT)) + { + hfmac->ErrorCode |= HAL_FMAC_ERROR_SAT; + } - /* Change the FMAC state */ - hfmac->State = HAL_FMAC_STATE_READY; + /* Change the FMAC state */ + hfmac->State = HAL_FMAC_STATE_READY; - /* Return function status */ - if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE) - { - return HAL_OK; - } - else - { - return HAL_ERROR; - } + /* Return function status */ + if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE) + { + status = HAL_OK; } else { - /* Return function status */ - return HAL_BUSY; + status = HAL_ERROR; } + return status; } /** * @brief Write data into FMAC internal memory through WDATA and increment input buffer pointer. - * This function is only used with preload functions. + * @note This function is only used with preload functions. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param ppData pointer to pointer to the data buffer. * @param Size size of the data buffer. - * @retval none + * @retval None */ static void FMAC_WritePreloadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, int16_t **ppData, uint8_t Size) { @@ -2001,33 +2025,31 @@ static void FMAC_WritePreloadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, int16_t * @param hfmac FMAC handle. * @param Tickstart Tick start value. * @param Timeout Timeout duration. - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ static HAL_StatusTypeDef FMAC_WaitOnStartUntilTimeout(FMAC_HandleTypeDef *hfmac, uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag changes */ - while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL) + while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U) { if ((HAL_GetTick() - Tickstart) > Timeout) { - /* Process Unlocked */ - __HAL_UNLOCK(hfmac); + hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; - return HAL_TIMEOUT; + return HAL_ERROR; } } return HAL_OK; } /** - * @brief Register the new input buffer, update DMA configuration - * if needed and change the FMAC state. + * @brief Register the new input buffer, update DMA configuration if needed and change the FMAC state. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param pInput New input vector (additional input data). * @param pInputSize Size of the input vector (if all the data can't be * written, it will be updated with the number of data read from FMAC). - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ static HAL_StatusTypeDef FMAC_AppendFilterDataUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize) @@ -2060,20 +2082,18 @@ static HAL_StatusTypeDef FMAC_AppendFilterDataUpdateState(FMAC_HandleTypeDef *hf hfmac->pInputSize = pInputSize; } - /* Return function status */ return HAL_OK; } /** - * @brief Register the new output buffer, update DMA configuration - * if needed and change the FMAC state. + * @brief Register the new output buffer, update DMA configuration if needed and change the FMAC state. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param pOutput New output vector. * @param pOutputSize Size of the output vector (if the vector can't * be entirely filled, pOutputSize will be updated with the number * of data read from FMAC). - * @retval HAL status + * @retval HAL_StatusTypeDef HAL status */ static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize) @@ -2082,7 +2102,7 @@ static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTyp hfmac->OutputCurrentSize = 0U; /* Check whether a valid pointer was provided */ - if ((pOutput == NULL) || (pOutputSize == NULL) || (*pOutputSize == 0UL)) + if ((pOutput == NULL) || (pOutputSize == NULL) || (*pOutputSize == 0U)) { /* The user will have to provide a valid configuration later */ hfmac->pOutput = NULL; @@ -2119,7 +2139,6 @@ static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTyp hfmac->RdState = HAL_FMAC_STATE_BUSY_RD; } - /* Return function status */ return HAL_OK; } @@ -2128,7 +2147,7 @@ static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTyp * @param hfmac FMAC handle. * @param MaxSizeToRead Maximum number of data to read (this serves as a timeout * if FMAC continuously writes into the output buffer). - * @retval HAL status + * @retval None */ static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToRead) { @@ -2137,7 +2156,7 @@ static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSiz uint32_t tmpvalue; /* Check if there is data to read */ - if (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) != 0UL) + if (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) != 0U) { return; } @@ -2166,7 +2185,7 @@ static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSiz *(hfmac->pOutput) = (int16_t)tmpvalue; hfmac->pOutput++; hfmac->OutputCurrentSize++; - } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) == 0UL); + } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) == 0U); /* Y buffer empty flag has just be raised, read the threshold */ threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_Y_EMPTY_WM(hfmac)) - 1U; @@ -2192,7 +2211,7 @@ static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSiz * @param hfmac FMAC handle. * @param MaxSizeToWrite Maximum number of data to write (this serves as a timeout * if FMAC continuously empties the input buffer). - * @retval HAL status + * @retval None */ static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToWrite) { @@ -2200,7 +2219,7 @@ static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSi uint16_t threshold; /* Check if there is room in FMAC */ - if (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) != 0UL) + if (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) != 0U) { return; } @@ -2228,7 +2247,7 @@ static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSi WRITE_REG(hfmac->Instance->WDATA, (((uint32_t)(*(hfmac->pInput))) & FMAC_WDATA_WDATA)); hfmac->pInput++; hfmac->InputCurrentSize++; - } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) == 0UL); + } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) == 0U); /* X1 buffer full flag has just be raised, read the threshold */ threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_X1_FULL_WM(hfmac)) - 1U; @@ -2357,7 +2376,7 @@ static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma) else { /* Wait for the end of the writing */ - for (index = 0U; index < 0xFFU; index++) + for (index = 0U; index < MAX_PRELOAD_INDEX; index++) { if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U) { @@ -2365,8 +2384,8 @@ static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma) } } - /* If 'START' is still set, there was an error: set FMAC handle state to error */ - if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL) + /* If 'START' is still set, there was a timeout: set FMAC handle state to timeout */ + if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U) { hfmac->State = HAL_FMAC_STATE_TIMEOUT; } @@ -2409,16 +2428,16 @@ static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma) FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Wait for the end of the X1 writing */ - for (index = 0U; index < 0xFFU; index++) + for (index = 0U; index < MAX_PRELOAD_INDEX; index++) { - if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0UL) + if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U) { break; } } /* If 'START' is still set, there was an error: set FMAC handle state to error */ - if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL) + if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U) { hfmac->State = HAL_FMAC_STATE_TIMEOUT; hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; @@ -2454,7 +2473,6 @@ static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma) /* nothing to do */ } - /* Return function status */ if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE) { /* Change the FMAC state */ @@ -2516,5 +2534,3 @@ static void FMAC_DMAError(DMA_HandleTypeDef *hdma) #endif /* HAL_FMAC_MODULE_ENABLED */ #endif /* FMAC */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gfxmmu.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gfxmmu.c index bed9b624d..14fd90a6b 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gfxmmu.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gfxmmu.c @@ -10,7 +10,18 @@ * + Modify physical buffer addresses. * + Modify cache and pre-fetch parameters. * + Error management. - * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -121,17 +132,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -890,4 +890,3 @@ uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c index 8d0a5f66b..3580f78a5 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions * + IO operation functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### GPIO Peripheral features ##### @@ -90,17 +101,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -122,14 +122,6 @@ /** @addtogroup GPIO_Private_Constants GPIO Private Constants * @{ */ -#define GPIO_MODE (0x00000003U) -#define ANALOG_MODE (0x00000008U) -#define EXTI_MODE (0x10000000U) -#define GPIO_MODE_IT (0x00010000U) -#define GPIO_MODE_EVT (0x00020000U) -#define RISING_EDGE (0x00100000U) -#define FALLING_EDGE (0x00200000U) -#define GPIO_OUTPUT_TYPE (0x00000010U) #if defined(DUAL_CORE) #define EXTI_CPU1 (0x01000000U) @@ -187,7 +179,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) @@ -199,11 +190,11 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); @@ -213,18 +204,24 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Configure the IO Output Type */ temp = GPIOx->OTYPER; temp &= ~(GPIO_OTYPER_OT0 << position) ; - temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); GPIOx->OTYPER = temp; } + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); temp |= ((GPIO_Init->Pull) << (position * 2U)); GPIOx->PUPDR = temp; + } /* In case of Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); @@ -245,7 +242,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ - if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); @@ -255,39 +252,39 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); SYSCFG->EXTICR[position >> 2U] = temp; - /* Clear EXTI line configuration */ - temp = EXTI_CurrentCPU->IMR1; + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; temp &= ~(iocurrent); - if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) { temp |= iocurrent; } - EXTI_CurrentCPU->IMR1 = temp; + EXTI->RTSR1 = temp; - temp = EXTI_CurrentCPU->EMR1; + temp = EXTI->FTSR1; temp &= ~(iocurrent); - if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) { temp |= iocurrent; } - EXTI_CurrentCPU->EMR1 = temp; + EXTI->FTSR1 = temp; - /* Clear Rising Falling edge configuration */ - temp = EXTI->RTSR1; + temp = EXTI_CurrentCPU->EMR1; temp &= ~(iocurrent); - if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) { temp |= iocurrent; } - EXTI->RTSR1 = temp; + EXTI_CurrentCPU->EMR1 = temp; - temp = EXTI->FTSR1; + /* Clear EXTI line configuration */ + temp = EXTI_CurrentCPU->IMR1; temp &= ~(iocurrent); - if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) { temp |= iocurrent; } - EXTI->FTSR1 = temp; + EXTI_CurrentCPU->IMR1 = temp; } } @@ -338,8 +335,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) EXTI_CurrentCPU->EMR1 &= ~(iocurrent); /* Clear Rising Falling edge configuration */ - EXTI->RTSR1 &= ~(iocurrent); EXTI->FTSR1 &= ~(iocurrent); + EXTI->RTSR1 &= ~(iocurrent); tmp = 0x0FUL << (4U * (position & 0x03U)); SYSCFG->EXTICR[position >> 2U] &= ~tmp; @@ -556,4 +553,3 @@ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c index bdfea698e..5f4a682d1 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c @@ -12,6 +12,17 @@ * + Peripheral State methods * + HASH or HMAC processing suspension/resumption * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -71,7 +82,8 @@ well the computed digest. (##) In DMA mode, multi-buffer HASH and HMAC processing are possible. - (+++) HASH processing: once initialization is done, MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro. + (+++) HASH processing: once initialization is done, MDMAT bit must be set + through __HAL_HASH_SET_MDMAT() macro. From that point, each buffer can be fed to the Peripheral through HAL_HASH_xxx_Start_DMA() API. Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() macro then wrap-up the HASH processing in feeding the last input buffer through the @@ -119,34 +131,36 @@ and not extra bits. (##) If user needs to perform a hash computation of a large input buffer that is spread around various places - in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it - becomes necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral. + in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it becomes + necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral. It is advised to the user to (+++) achieve the first formatting operation by software then enter the data - (+++) while the Peripheral is processing the first input set, carry out the second formatting operation by software, to be ready when DINIS occurs. + (+++) while the Peripheral is processing the first input set, carry out the second formatting + operation by software, to be ready when DINIS occurs. (+++) repeat step 2 until the whole message is processed. [..] (#) HAL in DMA mode (##) Again, due to hardware design, the DMA transfer to feed the data can only be done on a word-basis. - The same field described above in HASH_STR is used to specify which bits to discard at the end of the DMA transfer - to process only the message bits and not extra bits. Due to hardware implementation, this is possible only at the - end of the complete message. When several DMA transfers are needed to enter the message, this is not applicable at - the end of the intermediary transfers. + The same field described above in HASH_STR is used to specify which bits to discard at the end of the + DMA transfer to process only the message bits and not extra bits. Due to hardware implementation, + this is possible only at the end of the complete message. When several DMA transfers are needed to + enter the message, this is not applicable at the end of the intermediary transfers. - (##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive chunks of data - by software while the DMA transfer and processing is on-going for the first parts of the message. Due to the 32-bit alignment - required for the DMA transfer, it is underlined that the software formatting operation is more complex than in the IT mode. + (##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive + chunks of data by software while the DMA transfer and processing is on-going for the first parts of + the message. Due to the 32-bit alignment required for the DMA transfer, it is underlined that the + software formatting operation is more complex than in the IT mode. *** Callback registration *** =================================== [..] (#) The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use function @ref HAL_HASH_RegisterCallback() to register a user callback. + Use function HAL_HASH_RegisterCallback() to register a user callback. - (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks: + (#) Function HAL_HASH_RegisterCallback() allows to register following callbacks: (+) InCpltCallback : callback for input completion. (+) DgstCpltCallback : callback for digest computation completion. (+) ErrorCallback : callback for error. @@ -155,9 +169,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default + (#) Use function HAL_HASH_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) InCpltCallback : callback for input completion. @@ -166,13 +180,13 @@ (+) MspInitCallback : HASH MspInit. (+) MspDeInitCallback : HASH MspDeInit. - (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET + (#) By default, after the HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions: - examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback() + examples HAL_HASH_InCpltCallback(), HAL_HASH_DgstCpltCallback() Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init - and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand) - If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit + reset to the legacy weak (surcharged) functions in the HAL_HASH_Init + and HAL_HASH_DeInit only when these callbacks are null (not registered beforehand) + If not, MspInit or MspDeInit are not null, the HAL_HASH_Init and HAL_HASH_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). Callbacks can be registered/unregistered in READY state only. @@ -180,8 +194,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit - or @ref HAL_HASH_Init function. + using HAL_HASH_RegisterCallback before calling HAL_HASH_DeInit + or HAL_HASH_Init function. When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -189,17 +203,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -270,7 +273,8 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma); static void HASH_DMAError(DMA_HandleTypeDef *hdma); static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size); -static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, + uint32_t Timeout); static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash); static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash); @@ -284,8 +288,8 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim */ /** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization, configuration and call-back functions. - * + * @brief Initialization, configuration and call-back functions. + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -324,11 +328,11 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) { /* Check the hash handle allocation */ - if(hhash == NULL) + if (hhash == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_HASH_DATATYPE(hhash->Init.DataType)); @@ -340,9 +344,10 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) /* Reset Callback pointers in HAL_HASH_STATE_RESET only */ hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */ - hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */ + hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation + completion callback */ hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */ - if(hhash->MspInitCallback == NULL) + if (hhash->MspInitCallback == NULL) { hhash->MspInitCallback = HAL_HASH_MspInit; } @@ -351,7 +356,7 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) hhash->MspInitCallback(hhash); } #else - if(hhash->State == HAL_HASH_STATE_RESET) + if (hhash->State == HAL_HASH_STATE_RESET) { /* Allocate lock resource and initialize it */ hhash->Lock = HAL_UNLOCKED; @@ -361,7 +366,7 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) } #endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ - /* Change the HASH state */ + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; /* Reset HashInCount, HashITCounter, HashBuffSize and NbWordsAlreadyPushed */ @@ -379,7 +384,7 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) /* Set the data type bit */ MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType); /* Reset MDMAT bit */ -__HAL_HASH_RESET_MDMAT(); + __HAL_HASH_RESET_MDMAT(); /* Reset HASH handle status */ hhash->Status = HAL_OK; @@ -401,7 +406,7 @@ __HAL_HASH_RESET_MDMAT(); HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) { /* Check the HASH handle allocation */ - if(hhash == NULL) + if (hhash == NULL) { return HAL_ERROR; } @@ -420,13 +425,13 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) hhash->DigestCalculationDisable = RESET; #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - if(hhash->MspDeInitCallback == NULL) - { - hhash->MspDeInitCallback = HAL_HASH_MspDeInit; - } + if (hhash->MspDeInitCallback == NULL) + { + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; + } - /* DeInit the low level hardware */ - hhash->MspDeInitCallback(hhash); + /* DeInit the low level hardware */ + hhash->MspDeInitCallback(hhash); #else /* DeInit the low level hardware: CLOCK, NVIC */ HAL_HASH_MspDeInit(hhash); @@ -549,11 +554,12 @@ __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash) * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, + pHASH_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* Update the error code */ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; @@ -562,64 +568,64 @@ HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_ /* Process locked */ __HAL_LOCK(hhash); - if(HAL_HASH_STATE_READY == hhash->State) + if (HAL_HASH_STATE_READY == hhash->State) { switch (CallbackID) { - case HAL_HASH_INPUTCPLT_CB_ID : - hhash->InCpltCallback = pCallback; - break; + case HAL_HASH_INPUTCPLT_CB_ID : + hhash->InCpltCallback = pCallback; + break; - case HAL_HASH_DGSTCPLT_CB_ID : - hhash->DgstCpltCallback = pCallback; - break; + case HAL_HASH_DGSTCPLT_CB_ID : + hhash->DgstCpltCallback = pCallback; + break; - case HAL_HASH_ERROR_CB_ID : - hhash->ErrorCallback = pCallback; - break; + case HAL_HASH_ERROR_CB_ID : + hhash->ErrorCallback = pCallback; + break; - case HAL_HASH_MSPINIT_CB_ID : - hhash->MspInitCallback = pCallback; - break; + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = pCallback; + break; - case HAL_HASH_MSPDEINIT_CB_ID : - hhash->MspDeInitCallback = pCallback; - break; + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = pCallback; + break; - default : - /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } - else if(HAL_HASH_STATE_RESET == hhash->State) + else if (HAL_HASH_STATE_RESET == hhash->State) { switch (CallbackID) { - case HAL_HASH_MSPINIT_CB_ID : - hhash->MspInitCallback = pCallback; - break; + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = pCallback; + break; - case HAL_HASH_MSPDEINIT_CB_ID : - hhash->MspDeInitCallback = pCallback; - break; + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = pCallback; + break; - default : - /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else { /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; } /* Release Lock */ @@ -642,69 +648,70 @@ HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_ */ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID) { -HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hhash); - if(HAL_HASH_STATE_READY == hhash->State) + if (HAL_HASH_STATE_READY == hhash->State) { switch (CallbackID) { - case HAL_HASH_INPUTCPLT_CB_ID : - hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */ - break; + case HAL_HASH_INPUTCPLT_CB_ID : + hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */ + break; - case HAL_HASH_DGSTCPLT_CB_ID : - hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */ - break; + case HAL_HASH_DGSTCPLT_CB_ID : + hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation + completion callback */ + break; - case HAL_HASH_ERROR_CB_ID : - hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */ - break; + case HAL_HASH_ERROR_CB_ID : + hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */ + break; - case HAL_HASH_MSPINIT_CB_ID : - hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */ - break; + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; - case HAL_HASH_MSPDEINIT_CB_ID : - hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ - break; + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; - default : - /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } - else if(HAL_HASH_STATE_RESET == hhash->State) + else if (HAL_HASH_STATE_RESET == hhash->State) { switch (CallbackID) { - case HAL_HASH_MSPINIT_CB_ID : - hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */ - break; + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; - case HAL_HASH_MSPDEINIT_CB_ID : - hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ - break; + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; - default : - /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else { - /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; } /* Release Lock */ @@ -718,8 +725,8 @@ HAL_StatusTypeDef status = HAL_OK; */ /** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode - * @brief HASH processing functions using polling mode. - * + * @brief HASH processing functions using polling mode. + * @verbatim =============================================================================== ##### Polling mode HASH processing functions ##### @@ -757,7 +764,8 @@ HAL_StatusTypeDef status = HAL_OK; * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); } @@ -784,7 +792,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff */ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5); + return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } /** @@ -797,7 +805,8 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); } @@ -813,7 +822,8 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); } @@ -840,7 +850,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf */ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1); + return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } /** @@ -853,7 +863,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBu * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); } @@ -863,8 +874,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p */ /** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode - * @brief HASH processing functions using interrupt mode. - * + * @brief HASH processing functions using interrupt mode. + * @verbatim =============================================================================== ##### Interruption mode HASH processing functions ##### @@ -900,9 +911,10 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5); + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); } /** @@ -925,7 +937,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB */ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5); + return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } /** @@ -937,9 +949,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5); + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); } /** @@ -952,9 +965,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1); + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); } @@ -978,7 +992,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn */ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1); + return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } /** @@ -990,9 +1004,10 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1); + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); } /** @@ -1025,8 +1040,8 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) */ /** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode - * @brief HASH processing functions using DMA mode. - * + * @brief HASH processing functions using DMA mode. + * @verbatim =============================================================================== ##### DMA mode HASH processing functions ##### @@ -1077,9 +1092,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout) { - return HASH_Finish(hhash, pOutBuffer, Timeout); + return HASH_Finish(hhash, pOutBuffer, Timeout); } /** @@ -1108,9 +1123,9 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout) { - return HASH_Finish(hhash, pOutBuffer, Timeout); + return HASH_Finish(hhash, pOutBuffer, Timeout); } /** @@ -1118,8 +1133,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB */ /** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode - * @brief HMAC processing functions using polling mode. - * + * @brief HMAC processing functions using polling mode. + * @verbatim =============================================================================== ##### Polling mode HMAC processing functions ##### @@ -1149,7 +1164,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); } @@ -1167,7 +1183,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); } @@ -1178,8 +1195,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf /** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode - * @brief HMAC processing functions using interrupt mode. - * + * @brief HMAC processing functions using interrupt mode. + * @verbatim =============================================================================== ##### Interrupt mode HMAC processing functions ##### @@ -1208,7 +1225,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); } @@ -1225,7 +1243,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); } @@ -1237,8 +1256,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn /** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode - * @brief HMAC processing functions using DMA modes. - * + * @brief HMAC processing functions using DMA modes. + * @verbatim =============================================================================== ##### DMA mode HMAC processing functions ##### @@ -1313,8 +1332,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI */ /** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions - * @brief Peripheral State functions. - * + * @brief Peripheral State functions. + * @verbatim =============================================================================== ##### Peripheral State methods ##### @@ -1381,7 +1400,7 @@ HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) * must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long. * @retval None */ -void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) +void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) { uint32_t mem_ptr = (uint32_t)pMemBuffer; uint32_t csr_ptr = (uint32_t)HASH->CSR; @@ -1391,20 +1410,21 @@ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) UNUSED(hhash); /* Save IMR register content */ - *(uint32_t*)(mem_ptr) = READ_BIT(HASH->IMR,HASH_IT_DINI|HASH_IT_DCI); - mem_ptr+=4U; + *(uint32_t *)(mem_ptr) = READ_BIT(HASH->IMR, HASH_IT_DINI | HASH_IT_DCI); + mem_ptr += 4U; /* Save STR register content */ - *(uint32_t*)(mem_ptr) = READ_BIT(HASH->STR,HASH_STR_NBLW); - mem_ptr+=4U; + *(uint32_t *)(mem_ptr) = READ_BIT(HASH->STR, HASH_STR_NBLW); + mem_ptr += 4U; /* Save CR register content */ - *(uint32_t*)(mem_ptr) = READ_BIT(HASH->CR,HASH_CR_DMAE|HASH_CR_DATATYPE|HASH_CR_MODE|HASH_CR_ALGO|HASH_CR_LKEY|HASH_CR_MDMAT); - mem_ptr+=4U; + *(uint32_t *)(mem_ptr) = READ_BIT(HASH->CR, HASH_CR_DMAE | HASH_CR_DATATYPE | HASH_CR_MODE | HASH_CR_ALGO | + HASH_CR_LKEY | HASH_CR_MDMAT); + mem_ptr += 4U; /* By default, save all CSRs registers */ - for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--) + for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--) { - *(uint32_t*)(mem_ptr) = *(uint32_t*)(csr_ptr); - mem_ptr+=4U; - csr_ptr+=4U; + *(uint32_t *)(mem_ptr) = *(uint32_t *)(csr_ptr); + mem_ptr += 4U; + csr_ptr += 4U; } } @@ -1421,7 +1441,7 @@ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) * beforehand). * @retval None */ -void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) +void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) { uint32_t mem_ptr = (uint32_t)pMemBuffer; uint32_t csr_ptr = (uint32_t)HASH->CSR; @@ -1431,25 +1451,25 @@ void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) UNUSED(hhash); /* Restore IMR register content */ - WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr))); - mem_ptr+=4U; + WRITE_REG(HASH->IMR, (*(uint32_t *)(mem_ptr))); + mem_ptr += 4U; /* Restore STR register content */ - WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr))); - mem_ptr+=4U; + WRITE_REG(HASH->STR, (*(uint32_t *)(mem_ptr))); + mem_ptr += 4U; /* Restore CR register content */ - WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr))); - mem_ptr+=4U; + WRITE_REG(HASH->CR, (*(uint32_t *)(mem_ptr))); + mem_ptr += 4U; /* Reset the HASH processor before restoring the Context Swap Registers (CSR) */ __HAL_HASH_INIT(); /* By default, restore all CSR registers */ - for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--) + for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--) { - WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr))); - mem_ptr+=4U; - csr_ptr+=4U; + WRITE_REG((*(uint32_t *)(csr_ptr)), (*(uint32_t *)(mem_ptr))); + mem_ptr += 4U; + csr_ptr += 4U; } } @@ -1492,7 +1512,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) else { - /* Make sure there is enough time to suspend the processing */ + /* Make sure there is enough time to suspend the processing */ tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR; if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT) @@ -1505,7 +1525,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) /* Wait for BUSY flag to be reset */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_TIMEOUT; } if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET) @@ -1516,7 +1536,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) /* Wait for BUSY flag to be set */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_TIMEOUT; } /* Disable DMA channel */ /* Note that the Abort function will @@ -1524,13 +1544,13 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) - Unlock - Set the State */ - if (HAL_DMA_Abort(hhash->hdmain) !=HAL_OK) + if (HAL_DMA_Abort(hhash->hdmain) != HAL_OK) { return HAL_ERROR; } /* Clear DMAE bit */ - CLEAR_BIT(HASH->CR,HASH_CR_DMAE); + CLEAR_BIT(HASH->CR, HASH_CR_DMAE); /* Wait for BUSY flag to be reset */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) @@ -1564,19 +1584,22 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) { /* Compute how many words were supposed to be transferred by DMA */ - tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount%4U)!=0U) ? ((hhash->HashInCount+3U)/4U): (hhash->HashInCount/4U)); + tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount % 4U) != 0U) ? \ + ((hhash->HashInCount + 3U) / 4U) : (hhash->HashInCount / 4U)); - /* If discrepancy between the number of words reported by DMA Peripheral and the numbers of words entered as reported - by HASH Peripheral, correct it */ + /* If discrepancy between the number of words reported by DMA Peripheral and + the numbers of words entered as reported by HASH Peripheral, correct it */ /* tmp_words_already_pushed reflects the number of words that were already pushed before the start of DMA transfer (multi-buffer processing case) */ tmp_words_already_pushed = hhash->NbWordsAlreadyPushed; - if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) %16U) != HASH_NBW_PUSHED()) + if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - \ + tmp_remaining_DMATransferSize_inWords) % 16U) != HASH_NBW_PUSHED()) { tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */ } - /* Accordingly, update the input pointer that points at the next word to be transferred to the Peripheral by DMA */ + /* Accordingly, update the input pointer that points at the next word to be + transferred to the Peripheral by DMA */ hhash->pHashInBuffPtr += 4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ; /* And store in HashInCount the remaining size to transfer (in bytes) */ @@ -1596,7 +1619,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) * @brief Return the HASH handle error code. * @param hhash pointer to a HASH_HandleTypeDef structure. * @retval HASH Error Code -*/ + */ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash) { /* Return HASH Error Code */ @@ -1624,10 +1647,10 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash) */ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) { - HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; uint32_t inputaddr; uint32_t buffersize; - HAL_StatusTypeDef status ; + HAL_StatusTypeDef status = HAL_OK; if (hhash->State != HAL_HASH_STATE_SUSPENDED) { @@ -1726,19 +1749,21 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) } } - /* Configure the Number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(buffersize); + /* Configure the Number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS(buffersize); /* Set the HASH DMA transfer completion call back */ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; /* Enable the DMA In DMA stream */ - status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize %4U)!=0U) ? ((buffersize+(4U-(buffersize %4U)))/4U):(buffersize/4U))); + status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \ + (((buffersize % 4U) != 0U) ? ((buffersize + (4U - (buffersize % 4U))) / 4U) : \ + (buffersize / 4U))); - /* Enable DMA requests */ - SET_BIT(HASH->CR, HASH_CR_DMAE); + /* Enable DMA requests */ + SET_BIT(HASH->CR, HASH_CR_DMAE); - /* Return function status */ + /* Return function status */ if (status != HAL_OK) { /* Update HASH state machine to error */ @@ -1747,9 +1772,9 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) else { /* Change HASH state */ - hhash->State = HAL_HASH_STATE_READY; + hhash->State = HAL_HASH_STATE_BUSY; } - } + } } return; @@ -1764,14 +1789,14 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) */ static void HASH_DMAError(DMA_HandleTypeDef *hdma) { - HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hhash->State != HAL_HASH_STATE_SUSPENDED) { hhash->ErrorCode |= HAL_HASH_ERROR_DMA; /* Set HASH state to ready to prevent any blocking issue in user code present in HAL_HASH_ErrorCallback() */ - hhash->State= HAL_HASH_STATE_READY; + hhash->State = HAL_HASH_STATE_READY; /* Set HASH handle status to error */ hhash->Status = HAL_ERROR; #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) @@ -1801,18 +1826,18 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB uint32_t buffercounter; __IO uint32_t inputaddr = (uint32_t) pInBuffer; - for(buffercounter = 0U; buffercounter < Size; buffercounter+=4U) + for (buffercounter = 0U; buffercounter < Size; buffercounter += 4U) { /* Write input data 4 bytes at a time */ - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4U; + HASH->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ - if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4U) < Size)) + if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter + 4U) < Size)) { /* wait for flag BUSY not set before Wait for DINIS = 1*/ - if (buffercounter >=64U) + if (buffercounter >= 64U) { if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { @@ -1831,14 +1856,14 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)) { /* Save current reading and writing locations of Input and Output buffers */ - hhash->pHashInBuffPtr = (uint8_t *)inputaddr; + hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ hhash->HashInCount = Size - (buffercounter + 4U); } else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)) { /* Save current reading and writing locations of Input and Output buffers */ - hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr; + hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ hhash->HashKeyCount = Size - (buffercounter + 4U); } @@ -1872,63 +1897,63 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) { uint32_t msgdigest = (uint32_t)pMsgDigest; - switch(Size) + switch (Size) { /* Read the message digest */ case 16: /* MD5 */ - *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - break; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]); + break; case 20: /* SHA1 */ - *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); - break; - case 28: /* SHA224 */ - *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]); - break; - case 32: /* SHA256 */ - *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]); - break; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]); + break; + case 28: /* SHA224 */ + *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]); + break; + case 32: /* SHA256 */ + *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[7]); + break; default: - break; + break; } } @@ -1942,19 +1967,20 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) * @param Timeout Timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, + uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); /* Wait until flag is set */ - if(Status == RESET) + if (Status == RESET) { - while(__HAL_HASH_GET_FLAG(Flag) == RESET) + while (__HAL_HASH_GET_FLAG(Flag) == RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Set State to Ready to be able to restart later on */ hhash->State = HAL_HASH_STATE_READY; @@ -1971,12 +1997,12 @@ static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, } else { - while(__HAL_HASH_GET_FLAG(Flag) != RESET) + while (__HAL_HASH_GET_FLAG(Flag) != RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Set State to Ready to be able to restart later on */ hhash->State = HAL_HASH_STATE_READY; @@ -2009,10 +2035,10 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) if (hhash->State == HAL_HASH_STATE_BUSY) { /* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */ - if(hhash->HashITCounter == 0U) + if (hhash->HashITCounter == 0U) { /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI); /* HASH state set back to Ready to prevent any issue in user code present in HAL_HASH_ErrorCallback() */ hhash->State = HAL_HASH_STATE_READY; @@ -2020,9 +2046,9 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) } else if (hhash->HashITCounter == 1U) { - /* This is the first call to HASH_IT, the first input data are about to be - entered in the Peripheral. A specific processing is carried out at this point to - start-up the processing. */ + /* This is the first call to HASH_IT, the first input data are about to be + entered in the Peripheral. A specific processing is carried out at this point to + start-up the processing. */ hhash->HashITCounter = 2U; } else @@ -2039,7 +2065,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH()); /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI); /* Change the HASH state */ hhash->State = HAL_HASH_STATE_READY; /* Reset HASH state machine */ @@ -2060,10 +2086,10 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ - if ( (hhash->HashInCount != 0U) && (hhash->SuspendRequest == HAL_HASH_SUSPEND)) + if ((hhash->HashInCount != 0U) && (hhash->SuspendRequest == HAL_HASH_SUSPEND)) { /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI); /* Reset SuspendRequest */ hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; @@ -2092,7 +2118,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI); return HAL_TIMEOUT; } /* Initialization start for HMAC STEP 2 */ @@ -2100,7 +2126,8 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize); /* Set NBLW for the input message */ hhash->HashInCount = hhash->HashBuffSize; /* Set the input data size (in bytes) */ hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr; /* Set the input data address */ - hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */ + hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start + of a new phase */ __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */ } else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) @@ -2109,7 +2136,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI); return HAL_TIMEOUT; } /* Initialization start for HMAC STEP 3 */ @@ -2117,7 +2144,8 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); /* Set NBLW for the key */ hhash->HashInCount = hhash->Init.KeySize; /* Set the key size (in bytes) */ hhash->pHashInBuffPtr = hhash->Init.pKey; /* Set the key address */ - hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */ + hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start + of a new phase */ __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */ } else @@ -2151,28 +2179,28 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED; /* If there are more than 64 bytes remaining to be entered */ - if(hhash->HashInCount > 64U) + if (hhash->HashInCount > 64U) { inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* Write the Input block in the Data IN register (16 32-bit words, or 64 bytes are entered) */ - for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U) + for (buffercounter = 0U; buffercounter < 64U; buffercounter += 4U) { - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4U; + HASH->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; } /* If this is the start of input data entering, an additional word must be entered to start up the HASH processing */ - if(hhash->HashITCounter == 2U) + if (hhash->HashITCounter == 2U) { - HASH->DIN = *(uint32_t*)inputaddr; - if(hhash->HashInCount >= 68U) + HASH->DIN = *(uint32_t *)inputaddr; + if (hhash->HashInCount >= 68U) { /* There are still data waiting to be entered in the Peripheral. Decrement buffer counter and set pointer to the proper memory location for the next data entering round. */ hhash->HashInCount -= 68U; - hhash->pHashInBuffPtr+= 68U; + hhash->pHashInBuffPtr += 68U; } else { @@ -2186,7 +2214,7 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) Decrement buffer counter and set pointer to the proper memory location for the next data entering round.*/ hhash->HashInCount -= 64U; - hhash->pHashInBuffPtr+= 64U; + hhash->pHashInBuffPtr += 64U; } } else @@ -2202,10 +2230,10 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) __HAL_HASH_DISABLE_IT(HASH_IT_DINI); /* Write the Input block in the Data IN register */ - for(buffercounter = 0U; buffercounter < ((inputcounter+3U)/4U); buffercounter++) + for (buffercounter = 0U; buffercounter < ((inputcounter + 3U) / 4U); buffercounter++) { - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4U; + HASH->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; } if (hhash->Accumulation == 1U) @@ -2219,9 +2247,9 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) hhash->State = HAL_HASH_STATE_READY; /* Call Input data transfer complete call back */ #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - hhash->InCpltCallback(hhash); + hhash->InCpltCallback(hhash); #else - HAL_HASH_InCpltCallback(hhash); + HAL_HASH_InCpltCallback(hhash); #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ } else @@ -2251,7 +2279,8 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout) { /* Ensure first that Phase is correct */ - if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3)) + if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2) + && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3)) { /* Change the HASH state */ hhash->State = HAL_HASH_STATE_READY; @@ -2348,11 +2377,11 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim } - /* HMAC Step 3 processing. - After phase check, HMAC_Processing() may - - directly start up from this point in resumption case - if the same Step 3 processing was suspended previously - - or fall through from the Step 2 processing carried out hereabove */ + /* HMAC Step 3 processing. + After phase check, HMAC_Processing() may + - directly start up from this point in resumption case + if the same Step 3 processing was suspended previously + - or fall through from the Step 2 processing carried out hereabove */ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3) { /************************** STEP 3 ******************************************/ @@ -2380,7 +2409,7 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim __HAL_HASH_START_DIGEST(); /* Wait for DCIS flag to be set */ - if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -2392,14 +2421,14 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim hhash->Phase = HAL_HASH_PHASE_READY; } - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; - /* Process Unlock */ - __HAL_UNLOCK(hhash); + /* Process Unlock */ + __HAL_UNLOCK(hhash); - /* Return function status */ - return HAL_OK; + /* Return function status */ + return HAL_OK; } @@ -2415,7 +2444,8 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout, uint32_t Algorithm) { uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ @@ -2423,7 +2453,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* Initiate HASH processing in case of start or resumption */ -if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ if ((pInBuffer == NULL) || (pOutBuffer == NULL)) @@ -2436,13 +2466,13 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED __HAL_LOCK(hhash); /* Check if initialization phase has not been already performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) + if (hhash->Phase == HAL_HASH_PHASE_READY) { /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT); /* Configure the number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(Size); @@ -2564,7 +2594,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, } /* Initiate HASH processing in case of start or resumption */ -if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ if ((pInBuffer == NULL) || (Size == 0U)) @@ -2573,7 +2603,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED return HAL_ERROR; } - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hhash); /* If resuming the HASH processing */ @@ -2600,10 +2630,10 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Check if initialization phase has already be performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) + if (hhash->Phase == HAL_HASH_PHASE_READY) { /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT); } /* Set the phase */ @@ -2667,7 +2697,7 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff } /* Initiate HASH processing in case of start or resumption */ - if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ if ((pInBuffer == NULL) || (Size == 0U)) @@ -2676,7 +2706,7 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff return HAL_ERROR; } - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hhash); /* If resuming the HASH processing */ @@ -2691,15 +2721,15 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff hhash->State = HAL_HASH_STATE_BUSY; /* Check if initialization phase has already be performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) + if (hhash->Phase == HAL_HASH_PHASE_READY) { /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT); hhash->HashITCounter = 1; } else { - hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */ + hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */ } /* Set the phase */ @@ -2709,13 +2739,13 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set. Therefore, first words are manually entered until DINIS raises, or until there is not more data to enter. */ - while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 0U)) + while ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 0U)) { /* Write input data 4 bytes at a time */ - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4U; - SizeVar-=4U; + HASH->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; + SizeVar -= 4U; } /* If DINIS is still not set or if all the data have been fed, stop here */ @@ -2736,10 +2766,10 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff to be fed to the Peripheral */ hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Points at data which will be fed to the Peripheral at the next interruption */ - /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain - the information describing where the HASH process is stopped. - These variables are used later on to resume the HASH processing at the - correct location. */ + /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain + the information describing where the HASH process is stopped. + These variables are used later on to resume the HASH processing at the + correct location. */ } @@ -2776,16 +2806,17 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Algorithm) { - HAL_HASH_StateTypeDef State_tmp = hhash->State; + HAL_HASH_StateTypeDef State_tmp = hhash->State; __IO uint32_t inputaddr = (uint32_t) pInBuffer; uint32_t polling_step = 0U; uint32_t initialization_skipped = 0U; uint32_t SizeVar = Size; /* If State is ready or suspended, start or resume IT-based HASH processing */ -if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL)) @@ -2804,23 +2835,23 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED hhash->HashITCounter = 1; /* Check if initialization phase has already be performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) + if (hhash->Phase == HAL_HASH_PHASE_READY) { /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT); /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(SizeVar); + __HAL_HASH_SET_NBVALIDBITS(SizeVar); hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data to be fed to the Peripheral */ hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the Peripheral at the next interruption */ - /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain - the information describing where the HASH process is stopped. - These variables are used later on to resume the HASH processing at the - correct location. */ + /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain + the information describing where the HASH process is stopped. + These variables are used later on to resume the HASH processing at the + correct location. */ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ } @@ -2832,17 +2863,17 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED /* Set the phase */ hhash->Phase = HAL_HASH_PHASE_PROCESS; - /* If DINIS is equal to 0 (for example if an incomplete block has been previously - fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set. - Therefore, first words are manually entered until DINIS raises. */ - while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 3U)) + /* If DINIS is equal to 0 (for example if an incomplete block has been previously + fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set. + Therefore, first words are manually entered until DINIS raises. */ + while ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 3U)) { polling_step = 1U; /* note that some words are entered before enabling the interrupt */ /* Write input data 4 bytes at a time */ - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4U; - SizeVar-=4U; + HASH->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; + SizeVar -= 4U; } if (polling_step == 1U) @@ -2854,7 +2885,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ /* Start the Digest calculation */ - __HAL_HASH_START_DIGEST(); + __HAL_HASH_START_DIGEST(); /* Process Unlock */ __HAL_UNLOCK(hhash); @@ -2871,7 +2902,8 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED Update HashInCount and pHashInBuffPtr accordingly. */ hhash->HashInCount = SizeVar; hhash->pHashInBuffPtr = (uint8_t *)inputaddr; - __HAL_HASH_SET_NBVALIDBITS(SizeVar); /* Update the configuration of the number of valid bits in last word of the message */ + /* Update the configuration of the number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS(SizeVar); hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ if (initialization_skipped == 1U) { @@ -2883,11 +2915,11 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED /* DINIS is not set but it remains a few data to enter (not enough for a full word). Manually enter the last bytes before enabling DCIE. */ __HAL_HASH_SET_NBVALIDBITS(SizeVar); - HASH->DIN = *(uint32_t*)inputaddr; + HASH->DIN = *(uint32_t *)inputaddr; - /* Start the Digest calculation */ + /* Start the Digest calculation */ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ - __HAL_HASH_START_DIGEST(); + __HAL_HASH_START_DIGEST(); /* Process Unlock */ __HAL_UNLOCK(hhash); @@ -2904,7 +2936,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED __HAL_UNLOCK(hhash); /* Enable Interrupts */ - __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_ENABLE_IT(HASH_IT_DINI | HASH_IT_DCI); /* Return function status */ return HAL_OK; @@ -2944,15 +2976,15 @@ HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, (case of multi-buffer HASH processing) */ assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size)); - /* If State is ready or suspended, start or resume polling-based HASH processing */ -if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + /* If State is ready or suspended, start or resume polling-based HASH processing */ + if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ - if ( (pInBuffer == NULL ) || (Size == 0U) || - /* Check phase coherency. Phase must be - either READY (fresh start) - or PROCESS (multi-buffer HASH management) */ - ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash))))) + if ((pInBuffer == NULL) || (Size == 0U) || + /* Check phase coherency. Phase must be + either READY (fresh start) + or PROCESS (multi-buffer HASH management) */ + ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash))))) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; @@ -2972,10 +3004,10 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the API is processing a new input data message in case of multi-buffer HASH computation. */ - if(hhash->Phase == HAL_HASH_PHASE_READY) + if (hhash->Phase == HAL_HASH_PHASE_READY) { /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT); /* Set the phase */ hhash->Phase = HAL_HASH_PHASE_PROCESS; @@ -3015,7 +3047,9 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); /* Enable the DMA In DMA stream */ - status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U))); + status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \ + (((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) : \ + (inputSize / 4U))); /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); @@ -3046,10 +3080,10 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout) { - if(hhash->State == HAL_HASH_STATE_READY) + if (hhash->State == HAL_HASH_STATE_READY) { /* Check parameter */ if (pOutBuffer == NULL) @@ -3107,15 +3141,17 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, ui * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm) +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout, uint32_t Algorithm) { - HAL_HASH_StateTypeDef State_tmp = hhash->State; + HAL_HASH_StateTypeDef State_tmp = hhash->State; - /* If State is ready or suspended, start or resume polling-based HASH processing */ -if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + /* If State is ready or suspended, start or resume polling-based HASH processing */ + if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL)) + if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) + || (pOutBuffer == NULL)) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; @@ -3128,28 +3164,34 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED hhash->State = HAL_HASH_STATE_BUSY; /* Check if initialization phase has already be performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) + if (hhash->Phase == HAL_HASH_PHASE_READY) { /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */ - if(hhash->Init.KeySize > 64U) + if (hhash->Init.KeySize > 64U) { - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, + Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); } else { - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, + Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); } /* Set the phase to Step 1 */ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; /* Resort to hhash internal fields to feed the Peripheral. Parameters will be updated in case of suspension to contain the proper information at resumption time. */ - hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */ - hhash->pHashInBuffPtr = pInBuffer; /* Input data address, HMAC_Processing input parameter for Step 2 */ - hhash->HashInCount = Size; /* Input data size, HMAC_Processing input parameter for Step 2 */ - hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process */ - hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address, HMAC_Processing input parameter for Step 1 and Step 3 */ - hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1 and Step 3 */ + hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */ + hhash->pHashInBuffPtr = pInBuffer; /* Input data address, HMAC_Processing input + parameter for Step 2 */ + hhash->HashInCount = Size; /* Input data size, HMAC_Processing input + parameter for Step 2 */ + hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process*/ + hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address, HMAC_Processing input parameter for Step + 1 and Step 3 */ + hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1 + and Step 3 */ } /* Carry out HMAC processing */ @@ -3177,15 +3219,17 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm) +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Algorithm) { - HAL_HASH_StateTypeDef State_tmp = hhash->State; + HAL_HASH_StateTypeDef State_tmp = hhash->State; /* If State is ready or suspended, start or resume IT-based HASH processing */ -if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL)) + if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) + || (pOutBuffer == NULL)) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; @@ -3204,13 +3248,15 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED if (hhash->Phase == HAL_HASH_PHASE_READY) { /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */ - if(hhash->Init.KeySize > 64U) + if (hhash->Init.KeySize > 64U) { - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, + Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); } else { - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, + Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); } /* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount @@ -3255,7 +3301,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED __HAL_UNLOCK(hhash); /* Enable Interrupts */ - __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_ENABLE_IT(HASH_IT_DINI | HASH_IT_DCI); /* Return function status */ return HAL_OK; @@ -3290,18 +3336,18 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t inputSize; HAL_StatusTypeDef status ; HAL_HASH_StateTypeDef State_tmp = hhash->State; - /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation - is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */ - assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size)); + /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation + is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */ + assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size)); /* If State is ready or suspended, start or resume DMA-based HASH processing */ -if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ - if ((pInBuffer == NULL ) || (Size == 0U) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0U) || - /* Check phase coherency. Phase must be - either READY (fresh start) - or one of HMAC PROCESS steps (multi-buffer HASH management) */ - ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash))))) + if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || + /* Check phase coherency. Phase must be + either READY (fresh start) + or one of HMAC PROCESS steps (multi-buffer HASH management) */ + ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash))))) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; @@ -3314,63 +3360,65 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED /* If not a case of resumption after suspension */ if (hhash->State == HAL_HASH_STATE_READY) { - /* Check whether or not initialization phase has already be performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits. - At the same time, ensure MDMAT bit is cleared. */ - if(hhash->Init.KeySize > 64U) - { - MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); - } - else + /* Check whether or not initialization phase has already be performed */ + if (hhash->Phase == HAL_HASH_PHASE_READY) { - MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); - } - /* Store input aparameters in handle fields to manage steps transition - or possible HMAC suspension/resumption */ - hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */ - hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */ - hhash->pHashInBuffPtr = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */ - hhash->pHashMsgBuffPtr = pInBuffer; /* Input data address */ - hhash->HashBuffSize = Size; /* input data size (in bytes) */ + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits. + At the same time, ensure MDMAT bit is cleared. */ + if (hhash->Init.KeySize > 64U) + { + MODIFY_REG(HASH->CR, HASH_CR_MDMAT | HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, + Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); + } + else + { + MODIFY_REG(HASH->CR, HASH_CR_MDMAT | HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, + Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); + } + /* Store input aparameters in handle fields to manage steps transition + or possible HMAC suspension/resumption */ + hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */ + hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */ + hhash->pHashInBuffPtr = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */ + hhash->pHashMsgBuffPtr = pInBuffer; /* Input data address */ + hhash->HashBuffSize = Size; /* input data size (in bytes) */ - /* Set DMA input parameters */ - inputaddr = (uint32_t)(hhash->Init.pKey); /* Address passed to DMA (start by entering Key message) */ - inputSize = hhash->Init.KeySize; /* Size for first DMA transfer (in bytes) */ + /* Set DMA input parameters */ + inputaddr = (uint32_t)(hhash->Init.pKey); /* Address passed to DMA (start by entering Key message) */ + inputSize = hhash->Init.KeySize; /* Size for first DMA transfer (in bytes) */ - /* Configure the number of valid bits in last word of the key */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); + /* Configure the number of valid bits in last word of the key */ + __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - /* Set the phase to Step 1 */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; + /* Set the phase to Step 1 */ + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; - } + } else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) - { - /* Process a new input data message in case of multi-buffer HMAC processing - (this is not a resumption case) */ + { + /* Process a new input data message in case of multi-buffer HMAC processing + (this is not a resumption case) */ - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; - /* Save input parameters to be able to manage possible suspension/resumption */ + /* Save input parameters to be able to manage possible suspension/resumption */ hhash->HashInCount = Size; /* Input message address */ hhash->pHashInBuffPtr = pInBuffer; /* Input message size in bytes */ - /* Set DMA input parameters */ + /* Set DMA input parameters */ inputaddr = (uint32_t)pInBuffer; /* Input message address */ inputSize = Size; /* Input message size in bytes */ - if (hhash->DigestCalculationDisable == RESET) - { - /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */ - __HAL_HASH_RESET_MDMAT(); - __HAL_HASH_SET_NBVALIDBITS(inputSize); + if (hhash->DigestCalculationDisable == RESET) + { + /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */ + __HAL_HASH_RESET_MDMAT(); + __HAL_HASH_SET_NBVALIDBITS(inputSize); + } } - } else { /* Phase not aligned with handle READY state */ @@ -3381,7 +3429,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED } else { - /* Resumption case (phase may be Step 1, 2 or 3) */ + /* Resumption case (phase may be Step 1, 2 or 3) */ /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; @@ -3404,7 +3452,10 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); /* Enable the DMA In DMA stream */ - status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U))); + status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \ + (((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) \ + : (inputSize / 4U))); + /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); @@ -3440,6 +3491,3 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED * @} */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash_ex.c index 2ddac6121..86b7030c5 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash_ex.c @@ -14,6 +14,17 @@ * and SHA-256. * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### HASH peripheral extended features ##### @@ -39,14 +50,15 @@ User must resort to HAL_HASHEx_xxx_Accumulate_End() to enter the last one and retrieve as well the computed digest. - (##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer, + (##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer, except for the last one. User must resort to HAL_HASHEx_xxx_Accumulate_End_IT() to enter the last one and retrieve as well the computed digest. (##) In DMA mode, multi-buffer HASH and HMAC processing are possible. - (+++) HASH processing: once initialization is done, MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro. + (+++) HASH processing: once initialization is done, MDMAT bit must be set through + __HAL_HASH_SET_MDMAT() macro. From that point, each buffer can be fed to the Peripheral through HAL_HASHEx_xxx_Start_DMA() API. Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() macro then wrap-up the HASH processing in feeding the last input buffer through the @@ -68,17 +80,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -107,8 +108,8 @@ */ /** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode - * @brief HASH extended processing functions using polling mode. - * + * @brief HASH extended processing functions using polling mode. + * @verbatim =============================================================================== ##### Polling mode HASH extended processing functions ##### @@ -147,7 +148,8 @@ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); } @@ -174,7 +176,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224); + return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } /** @@ -187,7 +189,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); } @@ -203,7 +206,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); } @@ -230,7 +234,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256); + return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } /** @@ -243,7 +247,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); } @@ -253,8 +258,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ */ /** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode - * @brief HASH extended processing functions using interrupt mode. - * + * @brief HASH extended processing functions using interrupt mode. + * @verbatim =============================================================================== ##### Interruption mode HASH extended processing functions ##### @@ -285,9 +290,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224); + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); } /** @@ -310,7 +316,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224); + return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } /** @@ -322,9 +328,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224); + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); } /** @@ -337,9 +344,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256); + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); } /** @@ -362,7 +370,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256); + return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } /** @@ -374,9 +382,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256); + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); } /** @@ -384,8 +393,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin */ /** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode - * @brief HASH extended processing functions using DMA mode. - * + * @brief HASH extended processing functions using DMA mode. + * @verbatim =============================================================================== ##### DMA mode HASH extended processing functions ##### @@ -440,9 +449,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout) { - return HASH_Finish(hhash, pOutBuffer, Timeout); + return HASH_Finish(hhash, pOutBuffer, Timeout); } /** @@ -470,9 +479,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout) { - return HASH_Finish(hhash, pOutBuffer, Timeout); + return HASH_Finish(hhash, pOutBuffer, Timeout); } /** @@ -480,8 +489,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p */ /** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode - * @brief HMAC extended processing functions using polling mode. - * + * @brief HMAC extended processing functions using polling mode. + * @verbatim =============================================================================== ##### Polling mode HMAC extended processing functions ##### @@ -512,7 +521,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); } @@ -530,7 +540,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); } @@ -541,8 +552,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode - * @brief HMAC extended processing functions using interruption mode. - * + * @brief HMAC extended processing functions using interruption mode. + * @verbatim =============================================================================== ##### Interrupt mode HMAC extended processing functions ##### @@ -572,7 +583,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); } @@ -589,7 +601,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); } @@ -603,8 +616,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t /** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode - * @brief HMAC extended processing functions using DMA mode. - * + * @brief HMAC extended processing functions using DMA mode. + * @verbatim =============================================================================== ##### DMA mode HMAC extended processing functions ##### @@ -681,8 +694,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t */ /** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode - * @brief HMAC extended processing functions in multi-buffer DMA mode. - * + * @brief HMAC extended processing functions in multi-buffer DMA mode. + * @verbatim =============================================================================== ##### Multi-buffer DMA mode HMAC extended processing functions ##### @@ -1025,6 +1038,3 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @} */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c index 1e5a89af1..6182ab4f2 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -40,17 +51,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -61,7 +61,6 @@ */ #ifdef HAL_HCD_MODULE_ENABLED - #if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** @defgroup HCD HCD @@ -495,7 +494,8 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t i, interrupt; + uint32_t i; + uint32_t interrupt; /* Ensure that we are in device mode */ if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) @@ -537,14 +537,19 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U) { + /* Flush USB Fifo */ + (void)USB_FlushTxFifo(USBx, 0x10U); + (void)USB_FlushRxFifo(USBx); + + /* Restore FS Clock */ + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + /* Handle Host Port Disconnect Interrupt */ #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->DisconnectCallback(hhcd); #else HAL_HCD_Disconnect_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - - (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); } } @@ -950,7 +955,8 @@ HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef * /** * @brief Unregister the USB HCD Host Channel Notify URB Change Callback - * USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * USB HCD Host Channel Notify URB Change Callback is redirected + * to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback * @param hhcd HCD handle * @retval HAL status */ @@ -1008,8 +1014,11 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) { __HAL_LOCK(hhcd); - __HAL_HCD_ENABLE(hhcd); + /* Enable port power */ (void)USB_DriveVbus(hhcd->Instance, 1U); + + /* Enable global interrupt */ + __HAL_HCD_ENABLE(hhcd); __HAL_UNLOCK(hhcd); return HAL_OK; @@ -1172,13 +1181,13 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) { __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR) { __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR); hhcd->hc[ch_num].state = HC_BBLERR; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) @@ -1187,26 +1196,21 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - hhcd->hc[ch_num].state = HC_STALL; - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); + hhcd->hc[ch_num].state = HC_STALL; (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - hhcd->hc[ch_num].state = HC_DATATGLERR; - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + hhcd->hc[ch_num].state = HC_DATATGLERR; (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); hhcd->hc[ch_num].state = HC_XACTERR; (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); } else { @@ -1215,7 +1219,6 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); } @@ -1234,26 +1237,15 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); } - else if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) + else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) || + (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC)) { USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; hhcd->hc[ch_num].urb_state = URB_DONE; -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); -#else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - } - else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC) - { - hhcd->hc[ch_num].urb_state = URB_DONE; - hhcd->hc[ch_num].toggle_in ^= 1U; - #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); #else @@ -1279,8 +1271,6 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) { - __HAL_HCD_MASK_HALT_HC_INT(ch_num); - if (hhcd->hc[ch_num].state == HC_XFRC) { hhcd->hc[ch_num].urb_state = URB_DONE; @@ -1329,14 +1319,18 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /* ... */ } __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#else HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) { if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) { hhcd->hc[ch_num].ErrCnt = 0U; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || @@ -1347,7 +1341,6 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if (hhcd->Init.dma_enable == 0U) { hhcd->hc[ch_num].state = HC_NAK; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } } @@ -1381,7 +1374,8 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) { __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) { @@ -1390,16 +1384,14 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if (hhcd->hc[ch_num].do_ping == 1U) { hhcd->hc[ch_num].do_ping = 0U; - hhcd->hc[ch_num].urb_state = URB_NOTREADY; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].urb_state = URB_NOTREADY; (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) { @@ -1411,26 +1403,23 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) hhcd->hc[ch_num].do_ping = 1U; __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); } - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); hhcd->hc[ch_num].state = HC_XFRC; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) { hhcd->hc[ch_num].state = HC_NYET; hhcd->hc[ch_num].do_ping = 1U; hhcd->hc[ch_num].ErrCnt = 0U; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) { __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); hhcd->hc[ch_num].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) { @@ -1445,7 +1434,6 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } } - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); } @@ -1454,7 +1442,6 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if (hhcd->Init.dma_enable == 0U) { hhcd->hc[ch_num].state = HC_XACTERR; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else @@ -1464,7 +1451,12 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { hhcd->hc[ch_num].ErrCnt = 0U; hhcd->hc[ch_num].urb_state = URB_ERROR; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#else HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else { @@ -1475,37 +1467,31 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].state = HC_DATATGLERR; (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); - hhcd->hc[ch_num].state = HC_DATATGLERR; } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) { - __HAL_HCD_MASK_HALT_HC_INT(ch_num); - if (hhcd->hc[ch_num].state == HC_XFRC) { hhcd->hc[ch_num].urb_state = URB_DONE; if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) || (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)) { - if (hhcd->Init.dma_enable == 1U) + if (hhcd->Init.dma_enable == 0U) { - if (hhcd->hc[ch_num].xfer_len > 0U) - { - num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet; - - if ((num_packets & 1U) != 0U) - { - hhcd->hc[ch_num].toggle_out ^= 1U; - } - } + hhcd->hc[ch_num].toggle_out ^= 1U; } - else + + if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[ch_num].xfer_len > 0U)) { - hhcd->hc[ch_num].toggle_out ^= 1U; + num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet; + + if ((num_packets & 1U) != 0U) + { + hhcd->hc[ch_num].toggle_out ^= 1U; + } } } } @@ -1547,7 +1533,12 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#else HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else { @@ -1630,7 +1621,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - __IO uint32_t hprt0, hprt0_dup; + __IO uint32_t hprt0; + __IO uint32_t hprt0_dup; /* Handle Host Port Interrupts */ hprt0 = USBx_HPRT0; @@ -1650,7 +1642,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) HAL_HCD_Connect_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } - hprt0_dup |= USB_OTG_HPRT_PCDET; + hprt0_dup |= USB_OTG_HPRT_PCDET; } /* Check whether Port Enable Changed */ @@ -1723,5 +1715,3 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c index 1d7efa137..56a3d4911 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c @@ -49,6 +49,18 @@ * + Waveform Timer Burst Status Get * + Waveform Timer Push-Pull Status Get * + Peripheral State Get + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### Simple mode v.s. waveform mode ##### @@ -70,6 +82,8 @@ operates in waveform mode, all the HRTIM features are accessible without any restriction. HRTIM waveform modes are managed through the set of functions named HAL_HRTIM_Waveform + +============================================================================== ##### How to use this driver ##### ============================================================================== [..] @@ -339,18 +353,6 @@ callbacks are set to the corresponding weak functions. @endverbatim - - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** */ @@ -1618,11 +1620,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); - if((hhrtim->State == HAL_HRTIM_STATE_BUSY)) + if(hhrtim->State == HAL_HRTIM_STATE_BUSY) { return HAL_BUSY; } - if((hhrtim->State == HAL_HRTIM_STATE_READY)) + if(hhrtim->State == HAL_HRTIM_STATE_READY) { if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) { @@ -2235,11 +2237,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); - if((hhrtim->State == HAL_HRTIM_STATE_BUSY)) + if(hhrtim->State == HAL_HRTIM_STATE_BUSY) { return HAL_BUSY; } - if((hhrtim->State == HAL_HRTIM_STATE_READY)) + if(hhrtim->State == HAL_HRTIM_STATE_READY) { if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) { @@ -5329,7 +5331,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); - if((hhrtim->State == HAL_HRTIM_STATE_BUSY)) + if(hhrtim->State == HAL_HRTIM_STATE_BUSY) { return HAL_BUSY; } @@ -5764,11 +5766,11 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if((hhrtim->State == HAL_HRTIM_STATE_BUSY)) + if(hhrtim->State == HAL_HRTIM_STATE_BUSY) { return HAL_BUSY; } - if((hhrtim->State == HAL_HRTIM_STATE_READY)) + if(hhrtim->State == HAL_HRTIM_STATE_READY) { if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U)) { @@ -6115,6 +6117,9 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim, /* Check parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); + /* Prevent unused argument(s) compilation warning */ + UNUSED(TimerIdx); + /* Set output state according to output control status and output disable status */ switch (Output) { @@ -9290,5 +9295,3 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c index 78ae43b97..1d17bacb8 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c @@ -14,6 +14,17 @@ * + IRQ handler management * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -71,17 +82,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -205,7 +205,7 @@ HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID) /*take success when MasterID match and take bit set*/ return HAL_OK; } -#else +#else /* Read the RLR register to take the semaphore */ if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK)) { @@ -445,5 +445,3 @@ __weak void HAL_HSEM_FreeCallback(uint32_t SemMask) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c index 09b3e2a15..9954e5ae2 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c @@ -9,6 +9,17 @@ * + IO operation functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -19,7 +30,7 @@ (#) Declare a I2C_HandleTypeDef handle structure, for example: I2C_HandleTypeDef hi2c; - (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: (##) Enable the I2Cx interface clock (##) I2C pins configuration (+++) Enable the clock for the I2C GPIOs @@ -28,7 +39,8 @@ (+++) Configure the I2Cx interrupt priority (+++) Enable the NVIC I2C IRQ Channel (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream or channel depends on Instance + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit or receive stream or channel depends on Instance (+++) Enable the DMAx interface clock using (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx stream or channel depends on Instance @@ -39,49 +51,49 @@ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. - (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API. + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. - (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : *** Polling mode IO operation *** ================================= [..] - (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() *** Polling mode IO MEM operation *** ===================================== [..] - (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. @@ -92,120 +104,135 @@ when a direction change during transfer [..] (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: - (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode + (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in + no sequential mode (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition - (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition, an then permit a call the same master sequential interface - several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() - or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with + start condition, address and data to transfer without a final stop condition, + an then permit a call the same master sequential interface several times + (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() + or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer + and with new data to transfer if the direction change or manage only the new data to + transfer if no direction change and without a final stop condition in both cases (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer + and with new data to transfer if the direction change or manage only the new data to + transfer if no direction change and with a final stop condition in both cases - (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential - interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). - Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) - or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) - or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) - or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). - Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition + after several call of the same master sequential interface several times + (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or + Receive sequence permit to call the opposite interface Receive or Transmit without stopping the communication and so generate a restart condition. - (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after + each call of the same master sequential interface. - Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) - or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) - or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) - or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). - Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. + Usage can, transfer several bytes one by one with a restart with slave address between + each bytes using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. (+) Different sequential I2C interfaces are listed below: - (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() - or using @ref HAL_I2C_Master_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() - (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT() - or using @ref HAL_I2C_Master_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT() - (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() - (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT() - or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() - (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT() - or using @ref HAL_I2C_Slave_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() - (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() + HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master + (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** Interrupt mode IO MEM operation *** ======================================= [..] (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - @ref HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - @ref HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() *** DMA mode IO operation *** ============================== [..] (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** DMA mode IO MEM operation *** ================================= [..] (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - @ref HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - @ref HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() *** I2C HAL driver macros list *** @@ -213,23 +240,23 @@ [..] Below the list of most used macros in I2C HAL driver. - (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode - (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not - (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag - (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() + Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() to register an interrupt callback. [..] - Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: + Function HAL_I2C_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. @@ -244,11 +271,11 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). + For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). [..] - Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default + Use function HAL_I2C_UnRegisterCallback to reset a callback to the default weak function. - @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. @@ -263,24 +290,24 @@ (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. [..] - For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). + For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). [..] - By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). + examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when + reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() + If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() - or @ref HAL_I2C_Init() function. + using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + or HAL_I2C_Init() function. [..] When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -290,18 +317,6 @@ (@) You can refer to the I2C HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -336,28 +351,48 @@ #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ #define MAX_NBYTE_SIZE 255U -#define SlaveAddr_SHIFT 7U -#define SlaveAddr_MSK 0x06U +#define SLAVE_ADDR_SHIFT 7U +#define SLAVE_ADDR_MSK 0x06U /* Private define for @ref PreviousState usage */ -#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ -#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ -#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) +/*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) +/*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ /* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ -#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ -#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */ - -#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */ -#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */ -#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */ +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT + and @ref I2C_XFER_RX_IT */ + +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error + and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ /* Private define Sequential Transfer Options default/reset value */ #define I2C_NO_OPTION_FRAME (0xFFFF0000U) @@ -366,6 +401,9 @@ */ /* Private macro -------------------------------------------------------------*/ +/* Macro to get remaining data to transfer on DMA side */ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -390,24 +428,34 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); /* Private functions to handle IT transfer */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); /* Private functions for I2C transfer IRQ handler */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); /* Private functions to handle flags during polling transfer */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); /* Private functions to centralize the enable/disable of Interrupts */ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); @@ -559,7 +607,8 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; /* Configure I2Cx: Dual mode and Own Address2 */ - hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + (hi2c->Init.OwnAddress2Masks << 8)); /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ @@ -1065,8 +1114,8 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -1097,12 +1146,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_WRITE); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); } while (hi2c->XferCount > 0U) @@ -1132,12 +1183,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } } @@ -1180,8 +1233,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -1212,12 +1265,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); } while (hi2c->XferCount > 0U) @@ -1248,12 +1303,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } } @@ -1294,7 +1351,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1376,22 +1434,27 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->XferCount--; } + /* Wait until AF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* Wait until STOP flag is set */ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; - if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Normal use case for Transmitter mode */ - /* A NACK is generated to confirm the end of transfer */ - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } - else - { - return HAL_ERROR; - } + return HAL_ERROR; } /* Clear STOP flag */ @@ -1431,7 +1494,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1455,6 +1519,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; hi2c->XferISR = NULL; /* Enable Address Acknowledge */ @@ -1497,6 +1562,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->pBuffPtr++; hi2c->XferCount--; + hi2c->XferSize--; } return HAL_ERROR; @@ -1509,6 +1575,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, hi2c->pBuffPtr++; hi2c->XferCount--; + hi2c->XferSize--; } /* Wait until STOP flag is set */ @@ -1606,7 +1673,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; @@ -1627,7 +1695,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; @@ -1675,7 +1744,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); return HAL_OK; @@ -1724,7 +1794,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; @@ -1773,7 +1844,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; @@ -1846,7 +1918,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream or channel depends on Instance */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -1906,7 +1979,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1916,7 +1990,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -1990,7 +2065,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA stream or channel depends on Instance */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); } else { @@ -2050,7 +2126,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2060,7 +2137,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -2118,7 +2196,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream or channel depends on Instance */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -2221,7 +2300,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA stream or channel depends on Instance */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); } else { @@ -2374,12 +2454,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } @@ -2474,12 +2556,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); } do @@ -2510,12 +2594,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } } while (hi2c->XferCount > 0U); @@ -2608,7 +2694,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) + != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2627,7 +2714,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; @@ -2719,7 +2807,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); return HAL_OK; @@ -2792,7 +2881,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) + != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2813,7 +2903,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream or channel depends on Instance */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -2957,7 +3048,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA stream or channel depends on Instance */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); } else { @@ -3028,7 +3120,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) { uint32_t tickstart; @@ -3205,9 +3298,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 xfermode = hi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3291,9 +3386,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 xfermode = hi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3324,7 +3421,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream or channel depends on Instance */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -3383,7 +3481,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3393,7 +3492,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -3453,9 +3553,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ xfermode = hi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3539,9 +3641,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 xfermode = hi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3572,7 +3676,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA stream or channel depends on Instance */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); } else { @@ -3631,7 +3736,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3641,7 +3747,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -3862,7 +3969,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream or channel depends on Instance */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -3912,15 +4020,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* Enable ERR, STOP, NACK, ADDR interrupts */ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - return HAL_OK; } else @@ -4138,7 +4246,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA stream or channel depends on Instance */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, + (uint32_t)pData, hi2c->XferSize); } else { @@ -4188,15 +4297,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - return HAL_OK; } else @@ -4356,7 +4465,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) uint32_t tmperror; /* I2C Bus error interrupt occurred ------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; @@ -4365,7 +4475,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; @@ -4374,7 +4485,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; @@ -4628,7 +4740,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint16_t devaddress; uint32_t tmpITFlags = ITFlags; @@ -4636,7 +4749,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Process Locked */ __HAL_LOCK(hi2c); - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -4649,7 +4763,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) { /* Remove RXNE flag on temporary variable as read done */ tmpITFlags &= ~I2C_FLAG_RXNE; @@ -4663,7 +4778,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize--; hi2c->XferCount--; } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) { /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; @@ -4674,7 +4790,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize--; hi2c->XferCount--; } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { @@ -4690,11 +4807,13 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize = hi2c->XferCount; if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + hi2c->XferOptions, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } @@ -4714,7 +4833,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if (hi2c->XferCount == 0U) { @@ -4745,7 +4865,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Nothing to do */ } - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, tmpITFlags); @@ -4765,7 +4886,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint32_t tmpoptions = hi2c->XferOptions; uint32_t tmpITFlags = ITFlags; @@ -4774,13 +4896,15 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint __HAL_LOCK(hi2c); /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); } - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -4788,8 +4912,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) { - /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); @@ -4828,7 +4953,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } } } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) { if (hi2c->XferCount > 0U) { @@ -4854,11 +4980,12 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint { I2C_ITAddrCplt(hi2c, tmpITFlags); } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ - /* Check if all data have already been sent */ + /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if (hi2c->XferCount > 0U) { @@ -4900,7 +5027,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint16_t devaddress; uint32_t xfermode; @@ -4908,7 +5036,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Process Locked */ __HAL_LOCK(hi2c); - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -4924,7 +5053,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); @@ -4985,7 +5115,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui } } } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if (hi2c->XferCount == 0U) { @@ -5011,7 +5142,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); @@ -5035,7 +5167,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint32_t tmpoptions = hi2c->XferOptions; uint32_t treatdmanack = 0U; @@ -5045,13 +5178,15 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin __HAL_LOCK(hi2c); /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); } - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5065,7 +5200,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) { - if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) { treatdmanack = 1U; } @@ -5077,7 +5212,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) { - if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) { treatdmanack = 1U; } @@ -5086,8 +5221,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin if (treatdmanack == 1U) { - /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); @@ -5148,7 +5284,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); } } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, ITFlags); } @@ -5175,8 +5312,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); @@ -5229,8 +5367,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); @@ -5298,7 +5437,7 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* If 10bits addressing mode is selected */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { - if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) { slaveaddrcode = ownadd1code; hi2c->AddrEventCount++; @@ -5684,7 +5823,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) if (hi2c->hdmatx != NULL) { - hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); } } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) @@ -5694,7 +5833,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) if (hi2c->hdmarx != NULL) { - hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); } } else @@ -6025,7 +6164,8 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -6053,7 +6193,8 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) } /* Enable the DMA stream or channel depends on Instance */ - if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize) != HAL_OK) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); @@ -6073,7 +6214,8 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmpoptions = hi2c->XferOptions; if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) @@ -6100,7 +6242,8 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; @@ -6128,7 +6271,8 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) } /* Enable the DMA stream or channel depends on Instance */ - if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, + hi2c->XferSize) != HAL_OK) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); @@ -6148,10 +6292,11 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmpoptions = hi2c->XferOptions; - if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \ + if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \ (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Disable DMA Request */ @@ -6176,11 +6321,12 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) static void I2C_DMAError(DMA_HandleTypeDef *hdma) { uint32_t treatdmaerror = 0U; - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); if (hi2c->hdmatx != NULL) { - if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) { treatdmaerror = 1U; } @@ -6188,7 +6334,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) if (hi2c->hdmarx != NULL) { - if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) { treatdmaerror = 1U; } @@ -6213,7 +6359,8 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Reset AbortCpltCallback */ if (hi2c->hdmatx != NULL) @@ -6229,11 +6376,12 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) } /** - * @brief This function handles I2C Communication Timeout. + * @brief This function handles I2C Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Flag Specifies the I2C flag to check. - * @param Status The new Flag status (SET or RESET). + * @param Status The actual Flag status (SET or RESET). * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status @@ -6269,12 +6417,13 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6306,12 +6455,13 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6340,12 +6490,13 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { - /* Check if a NACK is detected */ - if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6363,13 +6514,22 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } else { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; @@ -6396,60 +6556,136 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } /** - * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @brief This function handles errors detection during an I2C Communication. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + HAL_StatusTypeDef status = HAL_OK; + uint32_t itflag = hi2c->Instance->ISR; + uint32_t error_code = 0; + uint32_t tickstart = Tickstart; + uint32_t tmp1; + HAL_I2C_ModeTypeDef tmp2; + + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) { - /* Wait until STOP Flag is reset */ + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP Flag is set or timeout occurred */ /* AutoEnd should be initiate after AF */ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); + tmp2 = hi2c->Mode; - return HAL_ERROR; + /* In case of I2C still busy, try to regenerate a STOP manually */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ + (tmp1 != I2C_CR2_STOP) && \ + (tmp2 != HAL_I2C_MODE_SLAVE)) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Update Tick with new reference */ + tickstart = HAL_GetTick(); + } + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + status = HAL_ERROR; + } + } } } } - /* Clear NACKF Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* In case STOP Flag is detected, clear it */ + if (status == HAL_OK) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + error_code |= HAL_I2C_ERROR_AF; + + status = HAL_ERROR; + } + + /* Refresh Content of Status register */ + itflag = hi2c->Instance->ISR; + + /* Then verify if an additional errors occurs */ + /* Check if a Bus error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) + { + error_code |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + + status = HAL_ERROR; + } + + /* Check if an Over-Run/Under-Run error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) + { + error_code |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + + status = HAL_ERROR; + } + /* Check if an Arbitration Loss error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) + { + error_code |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + + status = HAL_ERROR; + } + + if (status != HAL_OK) + { /* Flush TX register */ I2C_Flush_TXDR(hi2c); /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + hi2c->ErrorCode |= error_code; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - - return HAL_ERROR; } - return HAL_OK; + + return status; } /** @@ -6479,12 +6715,16 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + /* update CR2 register */ - MODIFY_REG(hi2c->Instance->CR2, + MODIFY_REG(hi2c->Instance->CR2, \ ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ - (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ - (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), tmp); } /** @@ -6663,5 +6903,3 @@ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c index 26a046bdb..d9b8e46c6 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c @@ -5,8 +5,21 @@ * @brief I2C Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral: - * + Extended features functions + * + Filter Mode Functions + * + WakeUp Mode Functions + * + FastModePlus Functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### I2C peripheral Extended features ##### @@ -32,18 +45,6 @@ (++) HAL_I2CEx_EnableFastModePlus() (++) HAL_I2CEx_DisableFastModePlus() @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -71,17 +72,15 @@ * @{ */ -/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions +/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @brief Filter Mode Functions * @verbatim =============================================================================== - ##### Extended features functions ##### + ##### Filter Mode Functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure Noise Filters - (+) Configure Wake Up Feature - (+) Configure Fast Mode Plus @endverbatim * @{ @@ -182,6 +181,23 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ return HAL_BUSY; } } +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions + * +@verbatim + =============================================================================== + ##### WakeUp Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ /** * @brief Enable I2C wakeup from Stop mode(s). @@ -260,6 +276,23 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) return HAL_BUSY; } } +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ /** * @brief Enable the I2C fast mode plus driving capability. @@ -322,11 +355,9 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) /* Disable fast mode plus driving capability for selected pin */ CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus); } - /** * @} */ - /** * @} */ @@ -339,5 +370,3 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c index fa1a7cbb2..ac9a8dc51 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and Errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -117,6 +128,7 @@ (+) TxRxCpltCallback : I2S TxRx Completed callback (+) TxHalfCpltCallback : I2S Tx Half Completed callback (+) RxHalfCpltCallback : I2S Rx Half Completed callback + (+) TxRxHalfCpltCallback : I2S TxRx Half Completed callback (+) ErrorCallback : I2S Error callback (+) MspInitCallback : I2S Msp Init callback (+) MspDeInitCallback : I2S Msp DeInit callback @@ -134,6 +146,7 @@ (+) TxRxCpltCallback : I2S TxRx Completed callback (+) TxHalfCpltCallback : I2S Tx Half Completed callback (+) RxHalfCpltCallback : I2S Rx Half Completed callback + (+) TxRxHalfCpltCallback : I2S TxRx Half Completed callback (+) ErrorCallback : I2S Error callback (+) MspInitCallback : I2S Msp Init callback (+) MspDeInitCallback : I2S Msp DeInit callback @@ -161,18 +174,6 @@ @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -356,12 +357,12 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) /* Get the source clock value: based on System Clock value */ #if defined (SPI_SPI6I2S_SUPPORT) - if (hi2s->Instance == SPI6) - { - /* SPI6 source clock */ + if (hi2s->Instance == SPI6) + { + /* SPI6 source clock */ i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6); } - else + else { /* SPI1,SPI2 and SPI3 share the same source clock */ i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123); @@ -369,7 +370,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) #else /* SPI1,SPI2 and SPI3 share the same source clock */ i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123); -#endif +#endif /* SPI_SPI6I2S_SUPPORT */ /* Compute the Real divider depending on the MCLK output state, with a floating point */ if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) @@ -414,7 +415,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) } MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD), - ((i2sdiv << SPI_I2SCFGR_I2SDIV_Pos) | (i2sodd << SPI_I2SCFGR_ODD_Pos))); + ((i2sdiv << SPI_I2SCFGR_I2SDIV_Pos) | (i2sodd << SPI_I2SCFGR_ODD_Pos))); } /*-------------------------- I2Sx I2SCFGR Configuration --------------------*/ @@ -425,10 +426,10 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | \ SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_WSINV | \ SPI_I2SCFGR_DATFMT | SPI_I2SCFGR_MCKOE), - (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \ - hi2s->Init.Standard | hi2s->Init.DataFormat | \ - hi2s->Init.CPOL | hi2s->Init.WSInversion | \ - hi2s->Init.Data24BitAlignment | hi2s->Init.MCLKOutput)); + (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \ + hi2s->Init.Standard | hi2s->Init.DataFormat | \ + hi2s->Init.CPOL | hi2s->Init.WSInversion | \ + hi2s->Init.Data24BitAlignment | hi2s->Init.MCLKOutput)); /*Clear status register*/ WRITE_REG(hi2s->Instance->IFCR, 0x0FF8); @@ -538,7 +539,8 @@ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, + pI2S_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -567,7 +569,7 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call case HAL_I2S_TX_RX_COMPLETE_CB_ID : hi2s->TxRxCpltCallback = pCallback; break; - + case HAL_I2S_TX_HALF_COMPLETE_CB_ID : hi2s->TxHalfCpltCallback = pCallback; break; @@ -580,7 +582,7 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID : hi2s->TxRxHalfCpltCallback = pCallback; break; - + case HAL_I2S_ERROR_CB_ID : hi2s->ErrorCallback = pCallback; break; @@ -679,7 +681,7 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID : hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ break; - + case HAL_I2S_ERROR_CB_ID : hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ break; @@ -812,15 +814,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -851,7 +852,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); hi2s->State = HAL_I2S_STATE_READY; __HAL_UNLOCK(hi2s); - return HAL_ERROR; + return HAL_TIMEOUT; } while (hi2s->TxXferCount > 0UL) @@ -883,7 +884,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); hi2s->State = HAL_I2S_STATE_READY; __HAL_UNLOCK(hi2s); - return HAL_ERROR; + return HAL_TIMEOUT; } /* Check if an underrun occurs */ @@ -930,15 +931,14 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -971,7 +971,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); hi2s->State = HAL_I2S_STATE_READY; __HAL_UNLOCK(hi2s); - return HAL_ERROR; + return HAL_TIMEOUT; } if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B)) @@ -1038,15 +1038,14 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR)); #endif /* __GNUC__ */ - if (hi2s->State != HAL_I2S_STATE_READY) + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - __HAL_UNLOCK(hi2s); - return HAL_BUSY; + return HAL_ERROR; } - if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + if (hi2s->State != HAL_I2S_STATE_READY) { - return HAL_ERROR; + return HAL_BUSY; } /* Process Locked */ @@ -1153,7 +1152,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); hi2s->State = HAL_I2S_STATE_READY; __HAL_UNLOCK(hi2s); - return HAL_ERROR; + return HAL_TIMEOUT; } } @@ -1183,15 +1182,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1260,15 +1258,14 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1331,15 +1328,14 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size) { - if (hi2s->State != HAL_I2S_STATE_READY) + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - __HAL_UNLOCK(hi2s); - return HAL_BUSY; + return HAL_ERROR; } - if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + if (hi2s->State != HAL_I2S_STATE_READY) { - return HAL_ERROR; + return HAL_BUSY; } /* Process Locked */ @@ -1357,7 +1353,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t hi2s->State = HAL_I2S_STATE_BUSY_TX_RX; - /* Set the function for IT treatment */ + /* Set the function for IT treatment */ if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B)) { hi2s->TxISR = I2S_Transmit_32Bit_IT; @@ -1369,7 +1365,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t hi2s->RxISR = I2S_Receive_16Bit_IT; } - /* Check if the I2S is already enabled */ + /* Check if the I2S is already enabled */ if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable I2S peripheral */ @@ -1409,20 +1405,21 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t */ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { + HAL_StatusTypeDef errorcode = HAL_OK; + if ((pData == NULL) || (Size == 0UL)) { return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1445,14 +1442,16 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, hi2s->hdmatx->XferErrorCallback = I2S_DMAError; /* Enable the Tx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, hi2s->TxXferSize)) + if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, + hi2s->TxXferCount)) { /* Update I2S error code */ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); hi2s->State = HAL_I2S_STATE_READY; __HAL_UNLOCK(hi2s); - return HAL_ERROR; + errorcode = HAL_ERROR; + return errorcode; } /* Check if the I2S Tx request is already enabled */ @@ -1473,7 +1472,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); __HAL_UNLOCK(hi2s); - return HAL_OK; + return errorcode; } /** @@ -1492,20 +1491,21 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, */ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { + HAL_StatusTypeDef errorcode = HAL_OK; + if ((pData == NULL) || (Size == 0UL)) { return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1529,12 +1529,13 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, hi2s->hdmarx->XferErrorCallback = I2S_DMAError; /* Enable the Rx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize)) + if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, + hi2s->RxXferCount)) { /* Update I2S error code */ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); hi2s->State = HAL_I2S_STATE_READY; - + errorcode = HAL_ERROR; __HAL_UNLOCK(hi2s); return HAL_ERROR; } @@ -1557,7 +1558,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); __HAL_UNLOCK(hi2s); - return HAL_OK; + return errorcode; } /** @@ -1578,17 +1579,19 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size) { - if (hi2s->State != HAL_I2S_STATE_READY) - { - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } + HAL_StatusTypeDef errorcode = HAL_OK; + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } + if (hi2s->State != HAL_I2S_STATE_READY) + { + return HAL_BUSY; + } + /* Process Locked */ __HAL_LOCK(hi2s); @@ -1614,16 +1617,17 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_ /* Set the I2S Rx DMA error callback */ hi2s->hdmarx->XferErrorCallback = I2S_DMAError; - /* Enable the Tx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, hi2s->TxXferSize)) + if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, + hi2s->TxXferCount)) { /* Update I2S error code */ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); hi2s->State = HAL_I2S_STATE_READY; __HAL_UNLOCK(hi2s); - return HAL_ERROR; + errorcode = HAL_ERROR; + return errorcode; } /* Check if the I2S Tx request is already enabled */ @@ -1633,13 +1637,14 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_ SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); } - /* Enable the Rx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize)) + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, + hi2s->RxXferCount)) { /* Update I2S error code */ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); hi2s->State = HAL_I2S_STATE_READY; - + errorcode = HAL_ERROR; __HAL_UNLOCK(hi2s); return HAL_ERROR; } @@ -1662,7 +1667,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_ SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART); __HAL_UNLOCK(hi2s); - return HAL_OK; + return errorcode; } /** @@ -1917,8 +1922,8 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /* I2S Underrun error interrupt occurred --------------------------------*/ if (HAL_IS_BIT_SET(trigger, I2S_FLAG_UDR)) { - /* Disable TXP and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR)); + /* Disable TXP, RXP and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_ERR)); /* Clear Underrun flag */ __HAL_I2S_CLEAR_UDRFLAG(hi2s); @@ -1939,8 +1944,8 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /* I2S Overrun error interrupt occurred -------------------------------------*/ if (HAL_IS_BIT_SET(trigger, I2S_FLAG_OVR)) { - /* Disable RXP and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR)); + /* Disable TXP, RXP and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_ERR)); /* Clear Overrun flag */ __HAL_I2S_CLEAR_OVRFLAG(hi2s); @@ -2127,7 +2132,8 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) */ static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) { - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* if DMA is configured in DMA_NORMAL Mode */ if (hdma->Init.Mode == DMA_NORMAL) @@ -2154,7 +2160,8 @@ static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) */ static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Call user Tx half complete callback */ #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) @@ -2172,7 +2179,8 @@ static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) */ static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) { - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* if DMA is configured in DMA_NORMAL Mode */ if (hdma->Init.Mode == DMA_NORMAL) @@ -2198,7 +2206,8 @@ static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) */ static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Call user Rx half complete callback */ #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) @@ -2252,7 +2261,8 @@ static void I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma) */ static void I2S_DMAError(DMA_HandleTypeDef *hdma) { - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Rx and Tx DMA Request */ CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN)); @@ -2295,7 +2305,7 @@ static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s) /* Disable TXP and ERR interrupt */ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR)); - if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) ||(hi2s->Init.Mode == I2S_MODE_MASTER_TX)) + if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) || (hi2s->Init.Mode == I2S_MODE_MASTER_TX)) { hi2s->State = HAL_I2S_STATE_READY; } @@ -2326,7 +2336,7 @@ static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s) /* Disable TXP and ERR interrupt */ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR)); - if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) ||(hi2s->Init.Mode == I2S_MODE_MASTER_TX)) + if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) || (hi2s->Init.Mode == I2S_MODE_MASTER_TX)) { hi2s->State = HAL_I2S_STATE_READY; } @@ -2454,7 +2464,8 @@ static void I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s) * @param Timeout Duration of the timeout * @retval HAL status */ -static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout) +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, + uint32_t Timeout) { uint32_t tickstart; @@ -2495,4 +2506,3 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, #endif /* HAL_I2S_MODULE_ENABLED */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s_ex.c index dad1c58a9..171dcf719 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s_ex.c @@ -5,21 +5,20 @@ * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2S extension peripheral: - * + Extension features Functions + * + Extension features Functions ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - + /** ****************************************************************************** ===== I2S FULL DUPLEX FEATURE ===== @@ -30,4 +29,3 @@ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_irda.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_irda.c index 865e9c816..e3ba4489e 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_irda.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_irda.c @@ -11,6 +11,17 @@ * + Peripheral State and Errors functions * + Peripheral Control functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -114,8 +125,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback. - Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks: + Use Function HAL_IRDA_RegisterCallback() to register a user callback. + Function HAL_IRDA_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -130,9 +141,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default + Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -147,13 +158,13 @@ (+) MspDeInitCallback : IRDA MspDeInit. [..] - By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET + By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback(). + examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init() - and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init() + and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -162,8 +173,8 @@ in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit() - or @ref HAL_IRDA_Init() function. + using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit() + or HAL_IRDA_Init() function. [..] When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or @@ -172,17 +183,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -801,10 +801,10 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD * @param Timeout Specify timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint8_t *pdata8bits; - uint16_t *pdata16bits; + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ @@ -831,7 +831,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */ + pdata16bits = (const uint16_t *) pData; /* Derogation R.11.3 */ } else { @@ -980,7 +980,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (hirda->gState == HAL_IRDA_STATE_READY) @@ -1052,8 +1052,16 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, /* Process Unlocked */ __HAL_UNLOCK(hirda); - /* Enable the IRDA Parity Error and Data Register not empty Interrupts */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + /* Enable the IRDA Parity Error and Data Register not empty Interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + /* Enable the IRDA Data Register not empty Interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -1077,7 +1085,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (hirda->gState == HAL_IRDA_STATE_READY) @@ -1194,8 +1202,11 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData /* Process Unlocked */ __HAL_UNLOCK(hirda); - /* Enable the UART Parity Error Interrupt */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + /* Enable the UART Parity Error Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -1287,7 +1298,10 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) __HAL_IRDA_CLEAR_OREFLAG(hirda); /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + } SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Enable the IRDA DMA Rx request */ @@ -2285,28 +2299,28 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) { case IRDA_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_PLL2Q: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_PLL3Q: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_CSI: - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(CSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(CSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_HSI: - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_LSE: - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; default: ret = HAL_ERROR; @@ -2316,7 +2330,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) /* USARTDIV must be greater than or equal to 0d16 */ if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) { - hirda->Instance->BRR = tmpreg; + hirda->Instance->BRR = (uint16_t)tmpreg; } else { @@ -2374,11 +2388,12 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) } /** - * @brief Handle IRDA Communication Timeout. + * @brief Handle IRDA Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @param Flag Specifies the IRDA flag to check. - * @param Status Flag status (SET or RESET) + * @param Status The actual Flag status (SET or RESET) * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status @@ -2779,7 +2794,7 @@ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) */ static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) { - uint16_t *tmp; + const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) @@ -2796,7 +2811,7 @@ static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) { if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) { - tmp = (uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */ + tmp = (const uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */ hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); hirda->pTxBuffPtr += 2U; } @@ -2904,4 +2919,4 @@ static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c index 85548ac40..2ec282987 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_iwdg.c @@ -8,6 +8,17 @@ * + Initialization and Start functions * + IO operation functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### IWDG Generic features ##### @@ -87,18 +98,6 @@ the reload register @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -122,11 +121,13 @@ /* Status register needs up to 5 LSI clock periods divided by the clock prescaler to be updated. The number of LSI clock periods is upper-rounded to 6 for the timeout value calculation. - The timeout value is also calculated using the highest prescaler (256) and + The timeout value is calculated using the highest prescaler (256) and the LSI_VALUE constant. The value of this constant can be changed by the user to take into account possible LSI clock period variations. - The timeout value is multiplied by 1000 to be converted in milliseconds. */ -#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE) + The timeout value is multiplied by 1000 to be converted in milliseconds. + LSI startup time is also considered here by adding LSI_STARTUP_TIME + converted in milliseconds. */ +#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) #define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) /** * @} @@ -280,5 +281,3 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c index ce873e28a..d83327162 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c @@ -16,6 +16,17 @@ * + IRQ handler management * + Peripheral State and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -203,17 +214,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -4197,4 +4197,3 @@ static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c index 5c396663d..afaaa3eeb 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c @@ -11,6 +11,17 @@ * + Reading operation functions. * + Peripheral State functions. * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -96,13 +107,13 @@ The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback. - @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, + Use Function HAL_LPTIM_RegisterCallback() to register a callback. + HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the + Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. [..] These functions allow to register/unregister following callbacks: @@ -120,7 +131,7 @@ [..] By default, after the Init and when the state is HAL_LPTIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: - examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback(). + examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback(). [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak @@ -134,7 +145,7 @@ in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. + using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. [..] When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or @@ -143,17 +154,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -235,8 +235,8 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); - if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) - || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); @@ -279,8 +279,8 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; - if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) - || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); } @@ -310,8 +310,8 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) } /* Configure LPTIM external clock polarity and digital filter */ - if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) - || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | hlptim->Init.UltraLowPowerClock.SampleTime); @@ -469,7 +469,7 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM PWM generation. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -517,7 +517,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -534,7 +534,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ @@ -545,7 +545,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -556,7 +556,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM PWM generation in interrupt mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF + * This parameter must be a value between 0x0001 and 0xFFFF * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF * @retval HAL status @@ -634,7 +634,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -651,7 +651,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ @@ -681,7 +681,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -692,7 +692,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM One pulse generation. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -740,7 +740,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -768,7 +768,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -779,7 +779,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM One pulse generation in interrupt mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -857,7 +857,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -877,6 +877,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Set the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -904,7 +905,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -915,7 +916,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM in Set once mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -963,7 +964,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -991,7 +992,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1080,7 +1081,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1127,7 +1128,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1138,7 +1139,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the Encoder interface. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) @@ -1188,7 +1189,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1219,7 +1220,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1298,7 +1299,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1335,7 +1336,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable "switch to up direction" interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1348,7 +1349,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) * trigger event will reset the counter and the timer restarts. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Timeout Specifies the TimeOut value to reset the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -1396,7 +1397,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1427,7 +1428,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1440,7 +1441,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) * trigger event will reset the counter and the timer restarts. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Timeout Specifies the TimeOut value to reset the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -1502,7 +1503,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1536,7 +1537,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable Compare match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1547,7 +1548,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the Counter mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) @@ -1587,7 +1588,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1615,7 +1616,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1626,7 +1627,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Start the Counter mode in interrupt mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period) @@ -1683,7 +1684,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1716,7 +1717,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable Autoreload match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -2177,39 +2178,48 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti switch (CallbackID) { case HAL_LPTIM_MSPINIT_CB_ID : - hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + /* Legacy weak MspInit Callback */ + hlptim->MspInitCallback = HAL_LPTIM_MspInit; break; case HAL_LPTIM_MSPDEINIT_CB_ID : - hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */ + /* Legacy weak Msp DeInit Callback */ + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; break; case HAL_LPTIM_COMPARE_MATCH_CB_ID : - hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak Compare match Callback */ + /* Legacy weak Compare match Callback */ + hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; break; case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : - hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto-reload match Callback */ + /* Legacy weak Auto-reload match Callback */ + hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; break; case HAL_LPTIM_TRIGGER_CB_ID : - hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak External trigger event detection Callback */ + /* Legacy weak External trigger event detection Callback */ + hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; break; case HAL_LPTIM_COMPARE_WRITE_CB_ID : - hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak Compare register write complete Callback */ + /* Legacy weak Compare register write complete Callback */ + hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; break; case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : - hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto-reload register write complete Callback */ + /* Legacy weak Auto-reload register write complete Callback */ + hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; break; case HAL_LPTIM_DIRECTION_UP_CB_ID : - hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak Up-counting direction change Callback */ + /* Legacy weak Up-counting direction change Callback */ + hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; break; case HAL_LPTIM_DIRECTION_DOWN_CB_ID : - hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak Down-counting direction change Callback */ + /* Legacy weak Down-counting direction change Callback */ + hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; break; default : @@ -2223,11 +2233,13 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti switch (CallbackID) { case HAL_LPTIM_MSPINIT_CB_ID : - hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + /* Legacy weak MspInit Callback */ + hlptim->MspInitCallback = HAL_LPTIM_MspInit; break; case HAL_LPTIM_MSPDEINIT_CB_ID : - hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */ + /* Legacy weak Msp DeInit Callback */ + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; break; default : @@ -2302,13 +2314,13 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) { /* Reset the LPTIM callback to the legacy weak callbacks */ - lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Compare match Callback */ - lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Auto-reload match Callback */ - lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* External trigger event detection Callback */ - lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Compare register write complete Callback */ - lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */ - lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Up-counting direction change Callback */ - lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Down-counting direction change Callback */ + lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; + lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; + lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; + lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; + lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; + lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; + lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; } #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ @@ -2351,9 +2363,12 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) uint32_t tmpCFGR; uint32_t tmpCMP; uint32_t tmpARR; + uint32_t primask_bit; uint32_t tmpCFGR2; - __disable_irq(); + /* Enter critical section */ + primask_bit = __get_PRIMASK(); + __set_PRIMASK(1) ; /*********** Save LPTIM Config ***********/ /* Save LPTIM source clock */ @@ -2519,7 +2534,8 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) hlptim->Instance->CFGR = tmpCFGR; hlptim->Instance->CFGR2 = tmpCFGR2; - __enable_irq(); + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); } /** * @} @@ -2534,5 +2550,3 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c index 0258304e1..7de01fe47 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -146,17 +157,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -178,6 +178,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#define LTDC_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -211,7 +212,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay */ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) { - uint32_t tmp, tmp1; + uint32_t tmp; + uint32_t tmp1; /* Check the LTDC peripheral state */ if (hltdc == NULL) @@ -320,6 +322,44 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc) { + uint32_t tickstart; + + /* Check the LTDC peripheral state */ + if (hltdc == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance)); + + /* Disable LTDC Layer 1 */ + __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_1); + +#if defined(LTDC_Layer2_BASE) + /* Disable LTDC Layer 2 */ + __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_2); +#endif /* LTDC_Layer2_BASE */ + + /* Reload during vertical blanking period */ + __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(hltdc); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for VSYNC Interrupt */ + while (READ_BIT(hltdc->Instance->CDSR, LTDC_CDSR_VSYNCS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > LTDC_TIMEOUT_VALUE) + { + break; + } + } + + /* Disable LTDC */ + __HAL_LTDC_DISABLE(hltdc); + #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) if (hltdc->MspDeInitCallback == NULL) { @@ -391,7 +431,8 @@ __weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc) * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, + pLTDC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -473,7 +514,7 @@ HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_ /** * @brief Unregister an LTDC Callback - * LTDC callabck is redirected to the weak predefined callback + * LTDC callback is redirected to the weak predefined callback * @param hltdc ltdc handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -887,11 +928,13 @@ HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT { if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44) { - tmp = (((counter + (16U*counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); + tmp = (((counter + (16U * counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \ + ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); } else { - tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); + tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \ + ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); } pcolorlut++; @@ -1345,12 +1388,14 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres } /** - * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is - * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we - * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels - * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). - * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch - * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width + * that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to + * layer for which we want to read and display on screen only a portion 320x240 taken in the center + * of the buffer. + * The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by previous + * call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default + * pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. @@ -1504,7 +1549,8 @@ HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadTyp * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, + uint32_t LayerIdx) { /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); @@ -1553,7 +1599,8 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, + uint32_t LayerIdx) { LTDC_LayerCfgTypeDef *pLayerCfg; @@ -1607,7 +1654,8 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, + uint32_t LayerIdx) { LTDC_LayerCfgTypeDef *pLayerCfg; @@ -1774,12 +1822,14 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32 } /** - * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is - * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we - * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels - * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). - * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch - * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width + * that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to + * layer for which we want to read and display on screen only a portion 320x240 taken in the center + * of the buffer. + * The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by + * previous call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default + * pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). * Variant of the function HAL_LTDC_SetPitch without immediate reload. * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. @@ -2082,7 +2132,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay /* Configure the horizontal start and stop position */ tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U); LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); - LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); /* Configure the vertical start and stop position */ tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U); @@ -2097,7 +2148,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); tmp2 = (pLayerCfg->Alpha0 << 24U); - LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA); + LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | + LTDC_LxDCCR_DCALPHA); LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); /* Specifies the constant alpha value */ @@ -2160,4 +2212,3 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c index d53d69829..fec173741 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -76,7 +75,8 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */ /* Note 1 : Code in line w/ Current LTDC specification */ - hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \ + DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL; hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL; @@ -88,8 +88,10 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc /* Retrieve vertical timing parameters from DSI */ hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U; hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U; - hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1U; - hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U; + hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \ + VidCfg->VerticalActive - 1U; + hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \ + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U; return HAL_OK; } @@ -114,7 +116,8 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ /* Note 1 : Code in line w/ Current LTDC specification */ - hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \ + DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; @@ -146,4 +149,3 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c index 834ffeb11..d80bc5637 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -112,18 +123,6 @@ @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -954,4 +953,3 @@ static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c index 1ce7664b2..089d9fbb1 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c @@ -7,6 +7,17 @@ * + Initialization/de-initialization functions * + I/O operation functions * + Peripheral State and errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -132,19 +143,7 @@ [..] - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** + @endverbatim */ /* Includes ------------------------------------------------------------------*/ @@ -1898,4 +1897,3 @@ static void MDMA_Init(MDMA_HandleTypeDef *hmdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c index 07ec0b24d..880a9e828 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + MMC card Control functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -53,7 +64,7 @@ SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer). This function provide the following operations: - (#) Initialize the SDMMC peripheral interface with defaullt configuration. + (#) Initialize the SDMMC peripheral interface with default configuration. The initialization process is done at 400KHz. You can change or adapt this frequency by adjusting the "ClockDiv" field. The MMC Card frequency (SDMMC_CK) is computed as follows: @@ -177,7 +188,7 @@ The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_MMC_RegisterCallback() to register a user callback, + Use Functions HAL_MMC_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. @@ -192,7 +203,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_MMC_UnRegisterCallback() to reset a callback to the default + Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. @@ -206,12 +217,12 @@ (+) MspDeInitCallback : MMC MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET + By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init - and @ref HAL_MMC_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_MMC_Init and @ref HAL_MMC_DeInit + reset to the legacy weak (surcharged) functions in the HAL_MMC_Init + and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -219,8 +230,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_MMC_RegisterCallback before calling @ref HAL_MMC_DeInit - or @ref HAL_MMC_Init function. + using HAL_MMC_RegisterCallback before calling HAL_MMC_DeInit + or HAL_MMC_Init function. When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -228,17 +239,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -261,7 +261,7 @@ * @{ */ #if defined (VDD_VALUE) && (VDD_VALUE <= 1950U) -#define MMC_VOLTAGE_RANGE MMC_LOW_VOLTAGE_RANGE +#define MMC_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE #define MMC_EXT_CSD_PWR_CL_26_INDEX 201 #define MMC_EXT_CSD_PWR_CL_52_INDEX 200 @@ -271,7 +271,7 @@ #define MMC_EXT_CSD_PWR_CL_52_POS 0 #define MMC_EXT_CSD_PWR_CL_DDR_52_POS 16 #else -#define MMC_VOLTAGE_RANGE MMC_HIGH_VOLTAGE_RANGE +#define MMC_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE #define MMC_EXT_CSD_PWR_CL_26_INDEX 203 #define MMC_EXT_CSD_PWR_CL_52_INDEX 202 @@ -280,10 +280,15 @@ #define MMC_EXT_CSD_PWR_CL_26_POS 24 #define MMC_EXT_CSD_PWR_CL_52_POS 16 #define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24 -#endif +#endif /* (VDD_VALUE) && (VDD_VALUE <= 1950U)*/ + +#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX 216 +#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS 0 +#define MMC_EXT_CSD_S_A_TIMEOUT_INDEX 217 +#define MMC_EXT_CSD_S_A_TIMEOUT_POS 8 /* Frequencies used in the driver for clock divider calculation */ -#define MMC_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */ +#define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */ #define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */ /** * @} @@ -378,7 +383,7 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) #else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_MMC_MspInit(hmmc); -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ } hmmc->State = HAL_MMC_STATE_BUSY; @@ -518,7 +523,7 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) #else /* De-Initialize the MSP layer */ HAL_MMC_MspDeInit(hmmc); -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ hmmc->ErrorCode = HAL_MMC_ERROR_NONE; hmmc->State = HAL_MMC_STATE_RESET; @@ -594,7 +599,9 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count, data, dataremaining; + uint32_t count; + uint32_t data; + uint32_t dataremaining; uint32_t add = BlockAdd; uint8_t *tempbuff = pData; @@ -615,7 +622,8 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui } /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ - if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) + & 0x000000FFU) != 0x0U) { if ((NumberOfBlocks % 8U) != 0U) { @@ -787,7 +795,9 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count, data, dataremaining; + uint32_t count; + uint32_t data; + uint32_t dataremaining; uint32_t add = BlockAdd; uint8_t *tempbuff = pData; @@ -1452,7 +1462,8 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, } /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ - if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) + & 0x000000FFU) != 0x0U) { if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U)) { @@ -1576,7 +1587,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) hmmc->ErrorCallback(hmmc); #else HAL_MMC_ErrorCallback(hmmc); -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ } } @@ -1590,7 +1601,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) hmmc->TxCpltCallback(hmmc); #else HAL_MMC_TxCpltCallback(hmmc); -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ } if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { @@ -1598,7 +1609,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) hmmc->RxCpltCallback(hmmc); #else HAL_MMC_RxCpltCallback(hmmc); -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ } } else if ((context & MMC_CONTEXT_IT) != 0U) @@ -1614,7 +1625,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) hmmc->ErrorCallback(hmmc); #else HAL_MMC_ErrorCallback(hmmc); -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ } } @@ -1628,7 +1639,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) hmmc->RxCpltCallback(hmmc); #else HAL_MMC_RxCpltCallback(hmmc); -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ } else { @@ -1636,7 +1647,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) hmmc->TxCpltCallback(hmmc); #else HAL_MMC_TxCpltCallback(hmmc); -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ } } else @@ -1730,7 +1741,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) hmmc->Write_DMADblBuf1CpltCallback(hmmc); #else HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(hmmc); -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ } else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */ { @@ -1738,7 +1749,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) hmmc->Read_DMADblBuf1CpltCallback(hmmc); #else HAL_MMCEx_Read_DMADoubleBuf1CpltCallback(hmmc); -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ } } else /* MMC_DMA_BUFFER1 */ @@ -1750,7 +1761,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) hmmc->Write_DMADblBuf0CpltCallback(hmmc); #else HAL_MMCEx_Write_DMADoubleBuf0CpltCallback(hmmc); -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ } else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */ { @@ -1758,7 +1769,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) hmmc->Read_DMADblBuf0CpltCallback(hmmc); #else HAL_MMCEx_Read_DMADoubleBuf0CpltCallback(hmmc); -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ } } } @@ -2055,7 +2066,7 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca __HAL_UNLOCK(hmmc); return status; } -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ /** * @} @@ -2285,7 +2296,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 512; + config.DataLength = 512U; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; @@ -2747,7 +2758,7 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) hmmc->AbortCpltCallback(hmmc); #else HAL_MMC_AbortCallback(hmmc); -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ } return HAL_OK; @@ -2905,7 +2916,9 @@ HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseT */ HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc) { - uint32_t errorstate, response = 0U, count; + uint32_t errorstate; + uint32_t response = 0U; + uint32_t count; uint32_t tickstart = HAL_GetTick(); /* Check the state of the driver */ @@ -3014,7 +3027,10 @@ HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc) */ HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode) { - uint32_t srt, errorstate, response = 0U, count; + uint32_t srt; + uint32_t errorstate; + uint32_t response = 0U; + uint32_t count; /* Check the erase type value is correct */ assert_param(IS_MMC_SRT_TYPE(SRTMode)); @@ -3137,6 +3153,343 @@ HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, ui } } +/** + * @brief Switch the device from Standby State to Sleep State. + * @param hmmc pointer to MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate, + sleep_timeout, + timeout, + count, + response = 0U ; + uint32_t tickstart = HAL_GetTick(); + + /* Check the state of the driver */ + if (hmmc->State == HAL_MMC_STATE_READY) + { + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U)); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { + /* Set the power-off notification to sleep notification : Ext_CSD[34] = 4 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220400U)); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Field SLEEP_NOTIFICATION_TIME [216] */ + sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX / 4)] >> + MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS) & 0x000000FFU); + + /* Sleep/Awake Timeout = 10us * 2^SLEEP_NOTIFICATION_TIME */ + /* In HAL, the tick interrupt occurs each ms */ + if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U)) + { + sleep_timeout = 0x17U; /* Max register value defined is 0x17 */ + } + timeout = (((1UL << sleep_timeout) / 100U) + 1U); + + /* Wait that the device is ready by checking the D0 line */ + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if ((HAL_GetTick() - tickstart) >= timeout) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + } + + /* Clear the flag corresponding to end D0 bus line */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, + (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { + /* Switch the device in stand-by mode */ + (void)SDMMC_CmdSelDesel(hmmc->Instance, 0U); + + /* Field S_A_TIEMOUT [217] */ + sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX / 4)] >> + MMC_EXT_CSD_S_A_TIMEOUT_POS) & 0x000000FFU); + + /* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT */ + /* In HAL, the tick interrupt occurs each ms */ + if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U)) + { + sleep_timeout = 0x17U; /* Max register value defined is 0x17 */ + } + timeout = (((1UL << sleep_timeout) / 10000U) + 1U); + + if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY) + { + /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and SLEEP as argument */ + errorstate = SDMMC_CmdSleepMmc(hmmc->Instance, + ((hmmc->MmcCard.RelCardAdd << 16U) | (0x1U << 15U))); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Wait that the device is ready by checking the D0 line */ + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if ((HAL_GetTick() - tickstart) >= timeout) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + } + + /* Clear the flag corresponding to end D0 bus line */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + } + } + else + { + errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE; + } + } + } + else + { + /* Nothing to do */ + } + } + } + } + } + else + { + /* Nothing to do */ + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + /* Manage errors */ + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + + if (errorstate != HAL_MMC_ERROR_TIMEOUT) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + else + { + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Switch the device from Sleep State to Standby State. + * @param hmmc pointer to MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate; + uint32_t sleep_timeout; + uint32_t timeout; + uint32_t count; + uint32_t response = 0U; + uint32_t tickstart = HAL_GetTick(); + + /* Check the state of the driver */ + if (hmmc->State == HAL_MMC_STATE_READY) + { + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Field S_A_TIEMOUT [217] */ + sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX / 4)] >> MMC_EXT_CSD_S_A_TIMEOUT_POS) & + 0x000000FFU); + + /* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT */ + /* In HAL, the tick interrupt occurs each ms */ + if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U)) + { + sleep_timeout = 0x17U; /* Max register value defined is 0x17 */ + } + timeout = (((1UL << sleep_timeout) / 10000U) + 1U); + + /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and AWAKE as argument */ + errorstate = SDMMC_CmdSleepMmc(hmmc->Instance, (hmmc->MmcCard.RelCardAdd << 16U)); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Wait that the device is ready by checking the D0 line */ + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if ((HAL_GetTick() - tickstart) >= timeout) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + } + + /* Clear the flag corresponding to end D0 bus line */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + + if (errorstate == HAL_MMC_ERROR_NONE) + { + if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY) + { + /* Switch the device in transfer mode */ + errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (hmmc->MmcCard.RelCardAdd << 16U)); + if (errorstate == HAL_MMC_ERROR_NONE) + { + if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_TRANSFER) + { + /* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U)); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, + (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + } + else + { + /* NOthing to do */ + } + } + } + else + { + errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE; + } + } + } + else + { + errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE; + } + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + /* Manage errors */ + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + + if (errorstate != HAL_MMC_ERROR_TIMEOUT) + { + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } + } + else + { + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} /** * @} */ @@ -3267,7 +3620,8 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) { __IO uint32_t count = 0U; - uint32_t response = 0U, validvoltage = 0U; + uint32_t response = 0U; + uint32_t validvoltage = 0U; uint32_t errorstate; /* CMD0: GO_IDLE_STATE */ @@ -3376,7 +3730,7 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 512; + config.DataLength = 512U; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; @@ -3395,7 +3749,8 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel } /* Poll on SDMMC flags */ - while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + SDMMC_FLAG_DATAEND)) { if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) { @@ -3476,7 +3831,8 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel */ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) { - uint32_t count, data; + uint32_t count; + uint32_t data; uint8_t *tmp; tmp = hmmc->pRxBuffPtr; @@ -3510,7 +3866,8 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) */ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) { - uint32_t count, data; + uint32_t count; + uint32_t data; uint8_t *tmp; tmp = hmmc->pTxBuffPtr; @@ -3545,7 +3902,8 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) { uint32_t errorstate = HAL_MMC_ERROR_NONE; - uint32_t response = 0U, count; + uint32_t response = 0U; + uint32_t count; uint32_t sdmmc_clk; SDMMC_InitTypeDef Init; @@ -3613,13 +3971,21 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) { /* High Speed Clock should be less or equal to 52MHz*/ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); + if (sdmmc_clk == 0U) { errorstate = SDMMC_ERROR_INVALID_PARAMETER; } else { - Init.ClockDiv = sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ); + if (sdmmc_clk <= MMC_HIGH_SPEED_FREQ) + { + Init.ClockDiv = 0; + } + else + { + Init.ClockDiv = (sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ)) + 1U; + } (void)SDMMC_Init(hmmc->Instance, Init); SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED); @@ -3649,7 +4015,8 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state) { uint32_t errorstate = HAL_MMC_ERROR_NONE; - uint32_t response = 0U, count; + uint32_t response = 0U; + uint32_t count; if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) && (state == DISABLE)) { @@ -3758,7 +4125,8 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3 uint32_t count; uint32_t response = 0U; uint32_t errorstate = HAL_MMC_ERROR_NONE; - uint32_t power_class, supported_pwr_class; + uint32_t power_class; + uint32_t supported_pwr_class; if ((Wide == SDMMC_BUS_WIDE_8B) || (Wide == SDMMC_BUS_WIDE_4B)) { @@ -3922,5 +4290,3 @@ __weak void HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc_ex.c index f392a5424..10acaf361 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc_ex.c @@ -7,6 +7,17 @@ * functionalities of the Secure Digital (MMC) peripheral: * + Extended features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -20,17 +31,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -351,5 +351,3 @@ HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_D /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_msp_template.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_msp_template.c index 48d5a2bf9..6f7fb110e 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_msp_template.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_msp_template.c @@ -6,6 +6,17 @@ * This file template is located in the HAL folder and should be copied * to the user folder. * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -14,17 +25,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -98,4 +98,4 @@ void HAL_PPP_MspDeInit(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c index 1b59059c3..74f6c6cd2 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c @@ -6,6 +6,17 @@ * This file provides a generic firmware to drive NAND memories mounted * as external device. * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -58,25 +69,25 @@ The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_NAND_RegisterCallback() to register a user callback, + Use Functions HAL_NAND_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) MspInitCallback : NAND MspInit. (+) MspDeInitCallback : NAND MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_NAND_UnRegisterCallback() to reset a callback to the default + Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) MspInitCallback : NAND MspInit. (+) MspDeInitCallback : NAND MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET + By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_NAND_Init - and @ref HAL_NAND_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_NAND_Init and @ref HAL_NAND_DeInit + reset to the legacy weak (surcharged) functions in the HAL_NAND_Init + and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -84,8 +95,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_NAND_RegisterCallback before calling @ref HAL_NAND_DeInit - or @ref HAL_NAND_Init function. + using HAL_NAND_RegisterCallback before calling HAL_NAND_DeInit + or HAL_NAND_Init function. When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -93,17 +104,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -2239,5 +2239,3 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nor.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nor.c index 1fab10867..2780e99c9 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nor.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nor.c @@ -6,6 +6,17 @@ * This file provides a generic firmware to drive NOR memories mounted * as external device. * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -55,25 +66,25 @@ The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback, + Use Functions HAL_NOR_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) MspInitCallback : NOR MspInit. (+) MspDeInitCallback : NOR MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default + Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) MspInitCallback : NOR MspInit. (+) MspDeInitCallback : NOR MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET + By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init - and @ref HAL_NOR_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit + reset to the legacy weak (surcharged) functions in the HAL_NOR_Init + and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -81,8 +92,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit - or @ref HAL_NOR_Init function. + using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit + or HAL_NOR_Init function. When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -90,17 +101,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -229,6 +229,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe FMC_NORSRAM_TimingTypeDef *ExtTiming) { uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR handle parameter */ if (hnor == NULL) @@ -301,11 +302,23 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe deviceaddress = NOR_MEMORY_ADRESS4; } - /* Get the value of the command set */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); + if (hnor->Init.WriteOperation == FMC_WRITE_OPERATION_DISABLE) + { + (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_PROTECTED; + } + else + { + /* Get the value of the command set */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); + + status = HAL_NOR_ReturnToReadMode(hnor); + } - return HAL_NOR_ReturnToReadMode(hnor); + return status; } /** @@ -428,7 +441,11 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I { return HAL_BUSY; } - else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED)) + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -515,7 +532,11 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) { return HAL_BUSY; } - else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED)) + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -589,7 +610,11 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint { return HAL_BUSY; } - else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED)) + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -758,7 +783,11 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress { return HAL_BUSY; } - else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED)) + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -1118,7 +1147,11 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR { return HAL_BUSY; } - else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED)) + else if (state == HAL_NOR_STATE_PROTECTED) + { + return HAL_ERROR; + } + else if (state == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -1509,5 +1542,3 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c index 5ebf16ea3..096baaebd 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c @@ -4,15 +4,23 @@ * @author MCD Application Team * @brief OPAMP HAL module driver. * This file provides firmware functions to manage the following - * functionalities of the operational amplifier(s) peripheral: - * + OPAMP configuration - * + OPAMP calibration - * Thanks to + * functionalities of the operational amplifier(s) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral Control functions * + Peripheral State functions - * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ================================================================================ ##### OPAMP Peripheral Features ##### @@ -112,14 +120,14 @@ (++) The compilation define USE_HAL_OPAMP_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - (++) Use Functions @ref HAL_OPAMP_RegisterCallback() to register a user callback, + (++) Use Functions HAL_OPAMP_RegisterCallback() to register a user callback, it allows to register following callbacks: (+++) MspInitCallback : OPAMP MspInit. (+++) MspDeInitCallback : OPAMP MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - (++) Use function @ref HAL_OPAMP_UnRegisterCallback() to reset a callback to the default + (++) Use function HAL_OPAMP_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+++) MspInitCallback : OPAMP MspInit. (+++) MspDeInitCallback : OPAMP MspDeInit. @@ -193,18 +201,6 @@ | | | COMP1_INN7 if | | | | | connected internally | | |-----------------|--------|-----------------------|---------------------| - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1160,4 +1156,3 @@ HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp_ex.c index f53006fe1..8eedb6789 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp_ex.c @@ -4,22 +4,20 @@ * @author MCD Application Team * @brief Extended OPAMP HAL module driver. * This file provides firmware functions to manage the following - * functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) - * peripheral: + * functionalities of the operational amplifier(s) peripheral: * + Extended Initialization and de-initialization functions * + Extended Peripheral Control functions - * + * @verbatim ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -432,4 +430,4 @@ HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef* hopamp) */ #endif /* HAL_OPAMP_MODULE_ENABLED */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c index 69cb96ecb..d009ee1c1 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ospi.c @@ -15,6 +15,17 @@ + Errors management and abort functionality + IO manager configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -109,24 +120,24 @@ ==================================== [..] Configure the SourceInc and DestinationInc of MDMA parameters in the HAL_OSPI_MspInit() function : - (+) MDMA settings for write operation : - (++) The DestinationInc should be MDMA_DEST_INC_DISABLE + (+) MDMA settings for write operation : + (++) The DestinationInc should be MDMA_DEST_INC_DISABLE (++) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD). - (++) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) + (++) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) aligned with @ref MDMA_Source_increment_mode . - (++) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) - (+) MDMA settings for read operation : - (++) The SourceInc should be MDMA_SRC_INC_DISABLE + (++) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) + (+) MDMA settings for read operation : + (++) The SourceInc should be MDMA_SRC_INC_DISABLE (++) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD). (++) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) . (++) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) aligned with @ref MDMA_Destination_increment_mode. (+) The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Octospi. [..] - In case of wrong MDMA setting - (+) For write operation : + In case of wrong MDMA setting + (+) For write operation : (++) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_OSPI_Transmit_DMA(). - (+) For read operation : + (+) For read operation : (++) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_OSPI_Receive_DMA(). *** Memory-mapped functional mode *** @@ -244,17 +255,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -303,7 +303,7 @@ static void OSPI_DMACplt (MDMA_HandleTypeDef *hmdma); static void OSPI_DMAError (MDMA_HandleTypeDef *hmdma); static void OSPI_DMAAbortCplt (MDMA_HandleTypeDef *hmdma); -static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, +static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout); static HAL_StatusTypeDef OSPI_ConfigCmd (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); static HAL_StatusTypeDef OSPIM_GetConfig (uint8_t instance_nb, OSPIM_CfgTypeDef *cfg); @@ -365,7 +365,6 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) assert_param(IS_OSPI_SAMPLE_SHIFTING(hospi->Init.SampleShifting)); assert_param(IS_OSPI_DHQC (hospi->Init.DelayHoldQuarterCycle)); assert_param(IS_OSPI_CS_BOUNDARY (hospi->Init.ChipSelectBoundary)); - assert_param(IS_OSPI_CKCSHT (hospi->Init.ClkChipSelectHighTime)); assert_param(IS_OSPI_DLYBYP (hospi->Init.DelayBlockBypass)); assert_param(IS_OSPI_MAXTRAN (hospi->Init.MaxTran)); @@ -403,13 +402,13 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) /* Configure the default timeout for the OSPI memory access */ (void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE); - /* Configure memory type, device size, chip select high time, clocked chip select high time, delay block bypass, free running clock, clock mode */ + /* Configure memory type, device size, chip select high time, delay block bypass, + free running clock, clock mode */ MODIFY_REG(hospi->Instance->DCR1, - (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_CKCSHT | - OCTOSPI_DCR1_DLYBYP | OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE), + (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_DLYBYP | + OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE), (hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1U) << OCTOSPI_DCR1_DEVSIZE_Pos) | ((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) | - (hospi->Init.ClkChipSelectHighTime << OCTOSPI_DCR1_CKCSHT_Pos) | hospi->Init.DelayBlockBypass | hospi->Init.ClockMode)); /* Configure wrap size */ @@ -431,7 +430,7 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) if (status == HAL_OK) { /* Configure clock prescaler */ - MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, + MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos)); /* Configure Dual Quad mode */ @@ -611,7 +610,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->FifoThresholdCallback(hospi); #else HAL_OSPI_FifoThresholdCallback(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ } /* OctoSPI transfer complete interrupt occurred ----------------------------*/ else if (((flag & HAL_OSPI_FLAG_TC) != 0U) && ((itsource & HAL_OSPI_IT_TC) != 0U)) @@ -641,7 +640,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->RxCpltCallback(hospi); #else HAL_OSPI_RxCpltCallback(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ } else { @@ -666,7 +665,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->TxCpltCallback(hospi); #else HAL_OSPI_TxCpltCallback(hospi); -#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ +#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ } else if (currentstate == HAL_OSPI_STATE_BUSY_CMD) { @@ -772,7 +771,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->ErrorCallback(hospi); #else HAL_OSPI_ErrorCallback(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ } } /* OctoSPI timeout interrupt occurred --------------------------------------*/ @@ -853,9 +852,9 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp /* Check the state of the driver */ state = hospi->State; if (((state == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) || - ((state == HAL_OSPI_STATE_READ_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG) + ((state == HAL_OSPI_STATE_READ_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG) || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))) || - ((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG) || + ((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG) || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG)))) { /* Wait till busy flag is reset */ @@ -1463,7 +1462,7 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat /* In Transmit mode , the MDMA destination is the OSPI DR register : Force the MDMA Destination Increment to disable */ MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE); - + /* Update MDMA configuration with the correct SourceInc field for Write operation */ if (hospi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE) { @@ -1477,7 +1476,7 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat { MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD); } - else + else { /* in case of incorrect source data size */ hospi->ErrorCode |= HAL_OSPI_ERROR_DMA; @@ -1486,18 +1485,18 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat /* Enable the transmit MDMA Channel */ if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize,1) == HAL_OK) - { - /* Enable the transfer error interrupt */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); - - /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/ - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_DMA; - hospi->State = HAL_OSPI_STATE_READY; - } + { + /* Enable the transfer error interrupt */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); + + /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/ + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_DMA; + hospi->State = HAL_OSPI_STATE_READY; + } } } else @@ -1528,7 +1527,6 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData uint32_t data_size = hospi->Instance->DLR + 1U; uint32_t addr_reg = hospi->Instance->AR; uint32_t ir_reg = hospi->Instance->IR; - /* Check the data pointer allocation */ if (pData == NULL) { @@ -1564,60 +1562,60 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData /* Clear the DMA abort callback */ hospi->hmdma->XferAbortCallback = NULL; -/* In Receive mode , the MDMA source is the OSPI DR register : Force the MDMA Source Increment to disable */ - MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE); - - /* Update MDMA configuration with the correct DestinationInc field for read operation */ - if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE) - { - MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_BYTE); - } - else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_HALFWORD) - { - MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_HALFWORD); - } - else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_WORD) - { - MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_WORD); - } - else - { - /* in case of incorrect destination data size */ - hospi->ErrorCode |= HAL_OSPI_ERROR_DMA; - status = HAL_ERROR; - } + /* In Receive mode , the MDMA source is the OSPI DR register : Force the MDMA Source Increment to disable */ + MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE); - /* Enable the transmit MDMA Channel */ - if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize, 1) == HAL_OK) + /* Update MDMA configuration with the correct DestinationInc field for read operation */ + if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE) + { + MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_BYTE); + } + else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_HALFWORD) + { + MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_HALFWORD); + } + else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_WORD) + { + MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_WORD); + } + else { - /* Enable the transfer error interrupt */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); + /* in case of incorrect destination data size */ + hospi->ErrorCode |= HAL_OSPI_ERROR_DMA; + status = HAL_ERROR; + } - /* Trig the transfer by re-writing address or instruction register */ - if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) - { - WRITE_REG(hospi->Instance->AR, addr_reg); - } - else + /* Enable the transmit MDMA Channel */ + if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize, 1) == HAL_OK) { - if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) + /* Enable the transfer error interrupt */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); + + /* Trig the transfer by re-writing address or instruction register */ + if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) { WRITE_REG(hospi->Instance->AR, addr_reg); } else { - WRITE_REG(hospi->Instance->IR, ir_reg); + if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) + { + WRITE_REG(hospi->Instance->AR, addr_reg); + } + else + { + WRITE_REG(hospi->Instance->IR, ir_reg); + } } - } - /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/ - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_DMA; - hospi->State = HAL_OSPI_STATE_READY; - } + /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/ + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_DMA; + hospi->State = HAL_OSPI_STATE_READY; + } } } else @@ -2332,7 +2330,7 @@ HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi) hospi->AbortCpltCallback(hospi); #else HAL_OSPI_AbortCpltCallback(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ } } else @@ -2572,9 +2570,9 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) { - if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && + if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && - (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) && + (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) && (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) { /* Multiplexing should be performed */ @@ -2620,12 +2618,12 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN); } else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN); } else @@ -2635,12 +2633,12 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0)); } else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0)); } else @@ -2650,23 +2648,23 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * } else { - MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), + MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos))); if (cfg->DQSPort != 0U) { - MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), + MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos))); } if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U)))); } else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U)))); } @@ -2677,13 +2675,13 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U)))); } else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U)))); } @@ -2861,7 +2859,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC HAL_StatusTypeDef status = HAL_OK; __IO uint32_t *ccr_reg; __IO uint32_t *tcr_reg; - __IO uint32_t *ir_reg; + __IO uint32_t *ir_reg; __IO uint32_t *abr_reg; /* Re-initialize the value of the functional mode */ @@ -3040,7 +3038,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg) { HAL_StatusTypeDef status = HAL_OK; - uint32_t reg; + uint32_t reg; uint32_t value = 0U; uint32_t index; @@ -3062,7 +3060,7 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef * { if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) == 0U) { - value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC + value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1); } else @@ -3165,5 +3163,3 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef * */ #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_otfdec.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_otfdec.c index 2b3fd1bd5..af78206b1 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_otfdec.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_otfdec.c @@ -9,6 +9,17 @@ * + Region setting/enable functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -58,11 +69,11 @@ The compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_OTFDEC_RegisterCallback() + Use Functions HAL_OTFDEC_RegisterCallback() to register an interrupt callback. [..] - Function @ref HAL_OTFDEC_RegisterCallback() allows to register following callbacks: + Function HAL_OTFDEC_RegisterCallback() allows to register following callbacks: (+) ErrorCallback : OTFDEC error callback (+) MspInitCallback : OTFDEC Msp Init callback (+) MspDeInitCallback : OTFDEC Msp DeInit callback @@ -70,11 +81,11 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_OTFDEC_UnRegisterCallback to reset a callback to the default + Use function HAL_OTFDEC_UnRegisterCallback to reset a callback to the default weak function. [..] - @ref HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ErrorCallback : OTFDEC error callback @@ -82,27 +93,27 @@ (+) MspDeInitCallback : OTFDEC Msp DeInit callback [..] - By default, after the @ref HAL_OTFDEC_Init() and when the state is @ref HAL_OTFDEC_STATE_RESET + By default, after the HAL_OTFDEC_Init() and when the state is HAL_OTFDEC_STATE_RESET all callbacks are set to the corresponding weak functions: - example @ref HAL_OTFDEC_ErrorCallback(). + example HAL_OTFDEC_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit() only when + reset to the legacy weak functions in the HAL_OTFDEC_Init()HAL_OTFDEC_DeInit() only when these callbacks are null (not registered beforehand). [..] - If MspInit or MspDeInit are not null, the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit() + If MspInit or MspDeInit are not null, the HAL_OTFDEC_Init()/HAL_OTFDEC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_OTFDEC_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_OTFDEC_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_OTFDEC_STATE_READY or @ref HAL_OTFDEC_STATE_RESET state, + in HAL_OTFDEC_STATE_READY or HAL_OTFDEC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_OTFDEC_RegisterCallback() before calling @ref HAL_OTFDEC_DeInit() - or @ref HAL_OTFDEC_Init() function. + using HAL_OTFDEC_RegisterCallback() before calling HAL_OTFDEC_DeInit() + or HAL_OTFDEC_Init() function. [..] When the compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS is set to 0 or @@ -111,17 +122,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -148,16 +148,14 @@ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ - - - /* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup OTFDEC_Exported_Functions * @{ */ /** @defgroup OTFDEC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * + * @brief Initialization and Configuration functions. + * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### @@ -176,7 +174,7 @@ HAL_StatusTypeDef HAL_OTFDEC_Init(OTFDEC_HandleTypeDef *hotfdec) { /* Check the OTFDEC handle allocation */ - if(hotfdec == NULL) + if (hotfdec == NULL) { return HAL_ERROR; } @@ -184,7 +182,7 @@ HAL_StatusTypeDef HAL_OTFDEC_Init(OTFDEC_HandleTypeDef *hotfdec) /* Check the parameters */ assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance)); - if(hotfdec->State == HAL_OTFDEC_STATE_RESET) + if (hotfdec->State == HAL_OTFDEC_STATE_RESET) { /* Allocate lock resource and initialize it */ __HAL_UNLOCK(hotfdec); @@ -222,7 +220,7 @@ HAL_StatusTypeDef HAL_OTFDEC_Init(OTFDEC_HandleTypeDef *hotfdec) HAL_StatusTypeDef HAL_OTFDEC_DeInit(OTFDEC_HandleTypeDef *hotfdec) { /* Check the OTFDEC handle allocation */ - if(hotfdec == NULL) + if (hotfdec == NULL) { return HAL_ERROR; } @@ -305,7 +303,7 @@ __weak void HAL_OTFDEC_MspDeInit(OTFDEC_HandleTypeDef *hotfdec) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID, pOTFDEC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -457,8 +455,8 @@ HAL_StatusTypeDef HAL_OTFDEC_UnRegisterCallback(OTFDEC_HandleTypeDef *hotfdec, H */ /** @defgroup OTFDEC_Exported_Functions_Group2 OTFDEC IRQ handler management - * @brief OTFDEC IRQ handler. - * + * @brief OTFDEC IRQ handler. + * @verbatim ============================================================================== ##### OTFDEC IRQ handler management ##### @@ -482,17 +480,17 @@ void HAL_OTFDEC_IRQHandler(OTFDEC_HandleTypeDef *hotfdec) isr_reg = READ_REG(hotfdec->Instance->ISR); if ((isr_reg & OTFDEC_ISR_SEIF) == OTFDEC_ISR_SEIF) { - SET_BIT( hotfdec->Instance->ICR, OTFDEC_ICR_SEIF ); + SET_BIT(hotfdec->Instance->ICR, OTFDEC_ICR_SEIF); hotfdec->ErrorCode |= HAL_OTFDEC_SECURITY_ERROR; } if ((isr_reg & OTFDEC_ISR_XONEIF) == OTFDEC_ISR_XONEIF) { - SET_BIT( hotfdec->Instance->ICR, OTFDEC_ICR_XONEIF ); + SET_BIT(hotfdec->Instance->ICR, OTFDEC_ICR_XONEIF); hotfdec->ErrorCode |= HAL_OTFDEC_EXECUTE_ERROR; } if ((isr_reg & OTFDEC_ISR_KEIF) == OTFDEC_ISR_KEIF) { - SET_BIT( hotfdec->Instance->ICR, OTFDEC_ICR_KEIF ); + SET_BIT(hotfdec->Instance->ICR, OTFDEC_ICR_KEIF); hotfdec->ErrorCode |= HAL_OTFDEC_KEY_ERROR; } @@ -527,8 +525,8 @@ __weak void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec) /** @defgroup OTFDEC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral control functions. - * + * @brief Peripheral control functions. + * @verbatim ============================================================================== ##### Peripheral Control functions ##### @@ -550,7 +548,7 @@ __weak void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec) */ HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex) { - OTFDEC_Region_TypeDef * region; + OTFDEC_Region_TypeDef *region; uint32_t address; /* Check the parameters */ @@ -560,10 +558,10 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32 /* Take Lock */ __HAL_LOCK(hotfdec); - address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex); + address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex); region = (OTFDEC_Region_TypeDef *)address; - SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_KEYLOCK ); + SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_KEYLOCK); /* Release Lock */ __HAL_UNLOCK(hotfdec); @@ -584,7 +582,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32 */ HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey) { - OTFDEC_Region_TypeDef * region; + OTFDEC_Region_TypeDef *region; uint32_t address; /* Check the parameters */ @@ -600,26 +598,26 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_ /* Take Lock */ __HAL_LOCK(hotfdec); - address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex); + address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex); region = (OTFDEC_Region_TypeDef *)address; /* Set Key */ - WRITE_REG( region->REG_KEYR0, pKey[0]); + WRITE_REG(region->REG_KEYR0, pKey[0]); __DSB(); __ISB(); - WRITE_REG( region->REG_KEYR1, pKey[1]); + WRITE_REG(region->REG_KEYR1, pKey[1]); __DSB(); __ISB(); - WRITE_REG( region->REG_KEYR2, pKey[2]); + WRITE_REG(region->REG_KEYR2, pKey[2]); __DSB(); __ISB(); - WRITE_REG( region->REG_KEYR3, pKey[3]); + WRITE_REG(region->REG_KEYR3, pKey[3]); /* Compute theoretically expected CRC and compare it with that reported by the peripheral */ if (HAL_OTFDEC_KeyCRCComputation(pKey) != HAL_OTFDEC_RegionGetKeyCRC(hotfdec, RegionIndex)) @@ -645,19 +643,19 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_ * the configuration information for OTFDEC module * @param RegionIndex index of region the mode of which is set * @param mode This parameter can be only: - * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY + * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY Only instruction accesses are decrypted - * @arg @ref OTFDEC_REG_MODE_DATA_ACCESSES_ONLY + * @arg @ref OTFDEC_REG_MODE_DATA_ACCESSES_ONLY Only data accesses are decrypted - * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES + * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES All read accesses are decrypted (instruction or data) - * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER + * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER Only instruction accesses are decrypted with proprietary cipher activated * @retval HAL state */ HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode) { - OTFDEC_Region_TypeDef * region; + OTFDEC_Region_TypeDef *region; uint32_t address; /* Check the parameters */ @@ -668,7 +666,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32 /* Take Lock */ __HAL_LOCK(hotfdec); - address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex); + address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex); region = (OTFDEC_Region_TypeDef *)address; /* Set mode */ @@ -694,10 +692,10 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32 * @arg @ref OTFDEC_REG_CONFIGR_LOCK_ENABLE OTFDEC region configuration is locked * @retval HAL state */ -HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, +HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config, uint32_t lock) { - OTFDEC_Region_TypeDef * region; + OTFDEC_Region_TypeDef *region; uint32_t address; /* Check the parameters */ @@ -715,30 +713,30 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_ /* Take Lock */ __HAL_LOCK(hotfdec); - address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex); + address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex); region = (OTFDEC_Region_TypeDef *)address; /* Set Nonce */ - WRITE_REG( region->REG_NONCER0, Config->Nonce[0]); + WRITE_REG(region->REG_NONCER0, Config->Nonce[0]); - WRITE_REG( region->REG_NONCER1, Config->Nonce[1]); + WRITE_REG(region->REG_NONCER1, Config->Nonce[1]); /* Write region protected area start and end addresses */ - WRITE_REG( region->REG_START_ADDR, Config->StartAddress); + WRITE_REG(region->REG_START_ADDR, Config->StartAddress); - WRITE_REG( region->REG_END_ADDR, Config->EndAddress); + WRITE_REG(region->REG_END_ADDR, Config->EndAddress); /* Write Version */ - MODIFY_REG( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_VERSION, - (uint32_t)(Config->Version) << OTFDEC_REG_CONFIGR_VERSION_Pos ); + MODIFY_REG(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_VERSION, + (uint32_t)(Config->Version) << OTFDEC_REG_CONFIGR_VERSION_Pos); /* Enable region deciphering or enciphering (depending of OTFDEC_CR ENC bit setting) */ - SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE); + SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE); /* Lock the region configuration according to lock parameter value */ if (lock == OTFDEC_REG_CONFIGR_LOCK_ENABLE) { - SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE); + SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE); } /* Release Lock */ @@ -764,7 +762,7 @@ uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey) uint32_t j; uint32_t keyval; uint32_t k; - uint32_t * temp = pKey; + uint32_t *temp = pKey; for (j = 0U; j < 4U; j++) { @@ -782,15 +780,15 @@ uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey) crc = 0; for (i = 0; i < (uint8_t)32; i++) { - k = ((((uint32_t)crc >> 7) ^ ((keyval >> ((uint8_t)31-i))&((uint8_t)0xF)))) & 1U; + k = ((((uint32_t)crc >> 7) ^ ((keyval >> ((uint8_t)31 - i)) & ((uint8_t)0xF)))) & 1U; crc <<= 1; if (k != 0U) { crc ^= crc7_poly; - } + } } - crc^=(uint8_t)0x55; + crc ^= (uint8_t)0x55; } return (uint32_t) crc; @@ -807,7 +805,7 @@ uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey) */ HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex) { - OTFDEC_Region_TypeDef * region; + OTFDEC_Region_TypeDef *region; uint32_t address; /* Check the parameters */ @@ -817,19 +815,19 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_ /* Take Lock */ __HAL_LOCK(hotfdec); - address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex); + address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex); region = (OTFDEC_Region_TypeDef *)address; - if (READ_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE) + if (READ_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE) { /* Configuration is locked, REG_EN bit can't be modified */ __HAL_UNLOCK(hotfdec); - return HAL_ERROR; + return HAL_ERROR; } /* Enable region processing */ - SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE); + SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE); /* Release Lock */ __HAL_UNLOCK(hotfdec); @@ -848,7 +846,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_ */ HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex) { - OTFDEC_Region_TypeDef * region; + OTFDEC_Region_TypeDef *region; uint32_t address; /* Check the parameters */ @@ -858,19 +856,19 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32 /* Take Lock */ __HAL_LOCK(hotfdec); - address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex); + address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex); region = (OTFDEC_Region_TypeDef *)address; - if (READ_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE) + if (READ_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE) { /* Configuration is locked, REG_EN bit can't be modified */ __HAL_UNLOCK(hotfdec); - return HAL_ERROR; + return HAL_ERROR; } /* Disable region processing */ - CLEAR_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE); + CLEAR_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE); /* Release Lock */ __HAL_UNLOCK(hotfdec); @@ -884,8 +882,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32 */ /** @defgroup OTFDEC_Exported_Functions_Group4 Peripheral State and Status functions - * @brief Peripheral State functions. - * + * @brief Peripheral State functions. + * @verbatim ============================================================================== ##### Peripheral State functions ##### @@ -918,7 +916,7 @@ HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec) */ uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex) { - OTFDEC_Region_TypeDef * region; + OTFDEC_Region_TypeDef *region; uint32_t address; uint32_t keycrc; @@ -926,10 +924,10 @@ uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t Regi assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance)); assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex)); - address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex); + address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex); region = (OTFDEC_Region_TypeDef *)address; - keycrc = (READ_REG( region->REG_CONFIGR )) & OTFDEC_REG_CONFIGR_KEYCRC; + keycrc = (READ_REG(region->REG_CONFIGR)) & OTFDEC_REG_CONFIGR_KEYCRC; keycrc >>= OTFDEC_REG_CONFIGR_KEYCRC_Pos; @@ -947,7 +945,7 @@ uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t Regi HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config) { - OTFDEC_Region_TypeDef * region; + OTFDEC_Region_TypeDef *region; uint32_t address; /* Check the parameters */ @@ -963,7 +961,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint /* Take Lock */ __HAL_LOCK(hotfdec); - address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex); + address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex); region = (OTFDEC_Region_TypeDef *)address; /* Read Nonce */ @@ -975,8 +973,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint Config->EndAddress = READ_REG(region->REG_END_ADDR); /* Read Version */ - Config->Version = (uint16_t)(READ_REG(region->REG_CONFIGR) & - OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos; + Config->Version = (uint16_t)(READ_REG(region->REG_CONFIGR) & + OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos; /* Release Lock */ __HAL_UNLOCK(hotfdec); diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c index e577f400c..3695b21a4 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -41,17 +52,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -224,7 +224,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->USB_Address = 0U; hpcd->State = HAL_PCD_STATE_READY; - + /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) { @@ -422,7 +422,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, /** * @brief Unregister an USB PCD Callback - * USB PCD callabck is redirected to the weak predefined callback + * USB PCD callback is redirected to the weak predefined callback * @param hpcd USB PCD handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -721,7 +721,8 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, /** * @brief Unregister the USB PCD Iso OUT incomplete Callback - * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * USB PCD Iso OUT incomplete Callback is redirected + * to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status */ @@ -795,7 +796,8 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, /** * @brief Unregister the USB PCD Iso IN incomplete Callback - * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * USB PCD Iso IN incomplete Callback is redirected + * to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status */ @@ -1053,9 +1055,13 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t i, ep_intr, epint, epnum; - uint32_t fifoemptymsk, temp; USB_OTG_EPTypeDef *ep; + uint32_t i; + uint32_t ep_intr; + uint32_t epint; + uint32_t epnum; + uint32_t fifoemptymsk; + uint32_t RegVal; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) @@ -1066,6 +1072,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) return; } + /* store current frame number */ + hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) { /* incorrect mode, acknowledge the interrupt */ @@ -1077,30 +1086,31 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - temp = USBx->GRXSTSP; + RegVal = USBx->GRXSTSP; - ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; + ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; - if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) { - if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) + if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) { (void)USB_ReadPacket(USBx, ep->xfer_buff, - (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); + (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); - ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; } } - else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) { (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; } else { /* ... */ } + USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); } @@ -1135,6 +1145,30 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); } + /* Clear OUT Endpoint disable interrupt */ + if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) + { + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; + } + + ep = &hpcd->OUT_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); + } + /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) { @@ -1204,6 +1238,21 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) { + (void)USB_FlushTxFifo(USBx, epnum); + + ep = &hpcd->IN_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); } if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) @@ -1294,7 +1343,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USBx_INEP(i)->DIEPINT = 0xFB7FU; USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; USBx_OUTEP(i)->DOEPINT = 0xFB7FU; USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; @@ -1366,18 +1414,37 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); } + /* Handle Global OUT NAK effective Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) + { + USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; + + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) + { + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); + } + } + } + /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) { - /* Keep application checking the corresponding Iso IN endpoint - causing the incomplete Interrupt */ - epnum = 0U; + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_INEP(epnum)->DIEPCTL; -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) + { + hpcd->IN_ep[epnum].is_iso_incomplete = 1U; + + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); + } + } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); } @@ -1385,15 +1452,25 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { - /* Keep application checking the corresponding Iso OUT endpoint - causing the incomplete Interrupt */ - epnum = 0U; + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_OUTEP(epnum)->DOEPCTL; -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && + ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U))) + { + hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; + + USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; + + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; + break; + } + } + } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); } @@ -1413,9 +1490,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Handle Disconnection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) { - temp = hpcd->Instance->GOTGINT; + RegVal = hpcd->Instance->GOTGINT; - if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) + if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DisconnectCallback(hpcd); @@ -1423,7 +1500,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) HAL_PCD_DisconnectCallback(hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - hpcd->Instance->GOTGINT |= temp; + hpcd->Instance->GOTGINT |= RegVal; } } } @@ -1924,6 +2001,32 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) return HAL_OK; } +/** + * @brief Abort an USB EP transaction. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + HAL_StatusTypeDef ret; + PCD_EPTypeDef *ep; + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + } + + /* Stop Xfer */ + ret = USB_EPStopXfer(hpcd->Instance, ep); + + return ret; +} + /** * @brief Flush an endpoint * @param hpcd PCD handle @@ -1997,6 +2100,33 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) return hpcd->State; } +/** + * @brief Set the USB Device high speed test mode. + * @param hpcd PCD handle + * @param testmode USB Device high speed test mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + + switch (testmode) + { + case TEST_J: + case TEST_K: + case TEST_SE0_NAK: + case TEST_PACKET: + case TEST_FORCE_EN: + USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; + break; + + default: + break; + } + + return HAL_OK; +} /** * @} */ @@ -2078,6 +2208,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t */ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { + USB_OTG_EPTypeDef *ep; USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); @@ -2108,18 +2239,24 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint } else { - /* out data packet received over EP0 */ - hpcd->OUT_ep[epnum].xfer_count = - hpcd->OUT_ep[epnum].maxpacket - - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); + ep = &hpcd->OUT_ep[epnum]; - hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; + /* out data packet received over EP */ + ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); - if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) + if (epnum == 0U) { - /* this is ZLP, so prepare EP0 for next setup */ - (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + if (ep->xfer_len == 0U) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + else + { + ep->xfer_buff += ep->xfer_count; + } } + #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else @@ -2224,5 +2361,3 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c index 5debbe016..58dc661cd 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c @@ -10,13 +10,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -164,26 +163,10 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) /* Enable DCD : Data Contact Detect */ USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; - /* Wait Detect flag or a timeout is happen*/ - while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > 1000U) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - return; - } - } - - /* Right response got */ - HAL_Delay(200U); + /* Wait for Min DCD Timeout */ + HAL_Delay(300U); - /* Check Detect flag*/ + /* Check Detect flag */ if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET) { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) @@ -193,7 +176,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - /*Primary detection: checks if connected to Standard Downstream Port + /* Primary detection: checks if connected to Standard Downstream Port (without charging capability) */ USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN; HAL_Delay(50U); @@ -229,7 +212,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) } else { - /* case Charging Downstream Port */ + /* case Charging Downstream Port */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); #else @@ -241,11 +224,23 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) /* Battery Charging capability discovery finished */ (void)HAL_PCDEx_DeActivateBCD(hpcd); + /* Check for the Timeout, else start USB Device */ + if ((HAL_GetTick() - tickstart) > 1000U) + { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); + hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); #else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } } /** @@ -344,5 +339,3 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pssi.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pssi.c index 19f0a6936..44cd6b70e 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pssi.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pssi.c @@ -9,6 +9,17 @@ * + IO operation functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -19,7 +30,7 @@ (#) Declare a PSSI_HandleTypeDef handle structure, for example: PSSI_HandleTypeDef hpssi; - (#) Initialize the PSSI low level resources by implementing the @ref HAL_PSSI_MspInit() API: + (#) Initialize the PSSI low level resources by implementing the HAL_PSSI_MspInit() API: (##) Enable the PSSIx interface clock (##) PSSI pins configuration (+++) Enable the clock for the PSSI GPIOs @@ -39,8 +50,8 @@ (#) Configure the Communication Bus Width, Control Signals, Input Polarity and Output Polarity in the hpssi Init structure. - (#) Initialize the PSSI registers by calling the @ref HAL_PSSI_Init(), configure also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_PSSI_MspInit(&hpssi) API. + (#) Initialize the PSSI registers by calling the HAL_PSSI_Init(), configure also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_PSSI_MspInit(&hpssi) API. (#) For PSSI IO operations, two operation modes are available within this driver : @@ -48,44 +59,44 @@ *** Polling mode IO operation *** ================================= [..] - (+) Transmit an amount of data by byte in blocking mode using @ref HAL_PSSI_Transmit() - (+) Receive an amount of data by byte in blocking mode using @ref HAL_PSSI_Receive() + (+) Transmit an amount of data by byte in blocking mode using HAL_PSSI_Transmit() + (+) Receive an amount of data by byte in blocking mode using HAL_PSSI_Receive() *** DMA mode IO operation *** ============================== [..] (+) Transmit an amount of data in non-blocking mode (DMA) using - @ref HAL_PSSI_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_PSSI_TxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_PSSI_TxCpltCallback() + HAL_PSSI_Transmit_DMA() + (+) At transmission end of transfer, HAL_PSSI_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_PSSI_TxCpltCallback() (+) Receive an amount of data in non-blocking mode (DMA) using - @ref HAL_PSSI_Receive_DMA() - (+) At reception end of transfer, @ref HAL_PSSI_RxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_PSSI_RxCpltCallback() - (+) In case of transfer Error, @ref HAL_PSSI_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_PSSI_ErrorCallback() - (+) Abort a PSSI process communication with Interrupt using @ref HAL_PSSI_Abort_IT() - (+) End of abort process, @ref HAL_PSSI_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_PSSI_AbortCpltCallback() + HAL_PSSI_Receive_DMA() + (+) At reception end of transfer, HAL_PSSI_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_PSSI_RxCpltCallback() + (+) In case of transfer Error, HAL_PSSI_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_PSSI_ErrorCallback() + (+) Abort a PSSI process communication with Interrupt using HAL_PSSI_Abort_IT() + (+) End of abort process, HAL_PSSI_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_PSSI_AbortCpltCallback() *** PSSI HAL driver macros list *** ================================== [..] Below the list of most used macros in PSSI HAL driver. - (+) @ref HAL_PSSI_ENABLE : Enable the PSSI peripheral - (+) @ref HAL_PSSI_DISABLE : Disable the PSSI peripheral - (+) @ref HAL_PSSI_GET_FLAG : Check whether the specified PSSI flag is set or not - (+) @ref HAL_PSSI_CLEAR_FLAG : Clear the specified PSSI pending flag - (+) @ref HAL_PSSI_ENABLE_IT : Enable the specified PSSI interrupt - (+) @ref HAL_PSSI_DISABLE_IT : Disable the specified PSSI interrupt + (+) HAL_PSSI_ENABLE : Enable the PSSI peripheral + (+) HAL_PSSI_DISABLE : Disable the PSSI peripheral + (+) HAL_PSSI_GET_FLAG : Check whether the specified PSSI flag is set or not + (+) HAL_PSSI_CLEAR_FLAG : Clear the specified PSSI pending flag + (+) HAL_PSSI_ENABLE_IT : Enable the specified PSSI interrupt + (+) HAL_PSSI_DISABLE_IT : Disable the specified PSSI interrupt *** Callback registration *** ============================================= - Use Functions @ref HAL_PSSI_RegisterCallback() or @ref HAL_PSSI_RegisterAddrCallback() + Use Functions HAL_PSSI_RegisterCallback() or HAL_PSSI_RegisterAddrCallback() to register an interrupt callback. - Function @ref HAL_PSSI_RegisterCallback() allows to register following callbacks: + Function HAL_PSSI_RegisterCallback() allows to register following callbacks: (+) TxCpltCallback : callback for transmission end of transfer. (+) RxCpltCallback : callback for reception end of transfer. (+) ErrorCallback : callback for error detection. @@ -96,9 +107,9 @@ and a pointer to the user callback function. - Use function @ref HAL_PSSI_UnRegisterCallback to reset a callback to the default + Use function HAL_PSSI_UnRegisterCallback to reset a callback to the default weak function. - @ref HAL_PSSI_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_PSSI_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxCpltCallback : callback for transmission end of transfer. @@ -109,22 +120,22 @@ (+) MspDeInitCallback : callback for Msp DeInit. - By default, after the @ref HAL_PSSI_Init() and when the state is @ref HAL_PSSI_STATE_RESET + By default, after the HAL_PSSI_Init() and when the state is HAL_PSSI_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_PSSI_TxCpltCallback(), @ref HAL_PSSI_RxCpltCallback(). + examples HAL_PSSI_TxCpltCallback(), HAL_PSSI_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit() only when + reset to the legacy weak functions in the HAL_PSSI_Init()/ HAL_PSSI_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit() + If MspInit or MspDeInit are not null, the HAL_PSSI_Init()/ HAL_PSSI_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - Callbacks can be registered/unregistered in @ref HAL_PSSI_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_PSSI_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_PSSI_STATE_READY or @ref HAL_PSSI_STATE_RESET state, + in HAL_PSSI_STATE_READY or HAL_PSSI_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_PSSI_RegisterCallback() before calling @ref HAL_PSSI_DeInit() - or @ref HAL_PSSI_Init() function. + using HAL_PSSI_RegisterCallback() before calling HAL_PSSI_DeInit() + or HAL_PSSI_Init() function. [..] @@ -132,17 +143,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1794,5 +1794,3 @@ void PSSI_DMAError(DMA_HandleTypeDef *hdma) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c index 0de6bb2a1..aeb99336f 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions. * + Peripheral Control functions. * + Interrupt Handling functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### PWR peripheral overview ##### @@ -129,18 +140,6 @@ (+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags. @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -872,4 +871,3 @@ __weak void HAL_PWR_PVDCallback (void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c index aaa58099c..5d51ceb85 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c @@ -6,6 +6,17 @@ * This file provides firmware functions to manage the following * functionalities of PWR extension peripheral: * + Peripheral Extended features functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -136,18 +147,6 @@ AVD interrupt request. @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -2141,4 +2140,3 @@ __weak void HAL_PWREx_AVDCallback (void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c index 12214968c..822b0c974 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c @@ -14,6 +14,17 @@ * + Errors management and abort functionality * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -93,16 +104,16 @@ (#) Configure the SourceInc and DestinationInc of MDMA parameters in the HAL_QSPI_MspInit() function : (++) MDMA settings for write operation : (+) The DestinationInc should be MDMA_DEST_INC_DISABLE - (+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD). - (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) - aligned with @ref MDMA_Source_increment_mode . - (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) + (+) The SourceInc must be a value of MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD). + (+) The SourceDataSize must be a value of MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) + aligned with MDMA_Source_increment_mode . + (+) The DestDataSize must be a value of MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) (++) MDMA settings for read operation : (+) The SourceInc should be MDMA_SRC_INC_DISABLE - (+) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD). - (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) . - (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) - aligned with @ref MDMA_Destination_increment_mode. + (+) The DestinationInc must be a value of MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD). + (+) The SourceDataSize must be a value of MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) . + (+) The DestDataSize must be a value of MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) + aligned with MDMA_Destination_increment_mode. (++)The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Quadspi. (#)In case of wrong MDMA setting (++) For write operation : @@ -132,7 +143,7 @@ ================================================= [..] (#) HAL_QSPI_GetError() function gives the error raised during the last operation. - (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and + (#) HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() functions aborts any on-going operation and flushes the fifo : (++) In polling mode, the output of the function is done when the transfer complete bit is set and the busy bit cleared. @@ -154,7 +165,7 @@ The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback, + Use Functions HAL_QSPI_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) ErrorCallback : callback when error occurs. (+) AbortCpltCallback : callback when abort is completed. @@ -169,7 +180,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default + Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) ErrorCallback : callback when error occurs. (+) AbortCpltCallback : callback when abort is completed. @@ -183,12 +194,12 @@ (+) MspDeInitCallback : QSPI MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET + By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init - and @ref HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit + reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init + and HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -196,8 +207,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit - or @ref HAL_QSPI_Init function. + using HAL_QSPI_RegisterCallback before calling HAL_QSPI_DeInit + or HAL_QSPI_Init function. When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -211,17 +222,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -300,7 +300,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /** * @brief Initialize the QSPI mode according to the specified parameters * in the QSPI_InitTypeDef and initialize the associated handle. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) @@ -394,7 +394,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) /** * @brief De-Initialize the QSPI peripheral. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) @@ -432,7 +432,7 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Initialize the QSPI MSP. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) @@ -447,7 +447,7 @@ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) /** * @brief DeInitialize the QSPI MSP. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) @@ -486,7 +486,7 @@ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Handle QSPI interrupt request. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) @@ -775,9 +775,9 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /** * @brief Set the command configuration. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @param cmd : structure that contains the command configuration information - * @param Timeout : Timeout duration + * @param Timeout Timeout duration * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ @@ -865,8 +865,8 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe /** * @brief Set the command configuration in interrupt mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ @@ -964,11 +964,10 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp /** * @brief Transmit an amount of data in blocking mode. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Timeout duration * @note This function is used only in Indirect Write Mode - * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) @@ -1048,9 +1047,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Timeout duration * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1134,8 +1133,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /** * @brief Send an amount of data in non-blocking mode with interrupt. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1194,8 +1193,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Receive an amount of data in non-blocking mode with interrupt. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1258,8 +1257,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) /** * @brief Send an amount of data in non-blocking mode with DMA. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1371,8 +1370,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer. + * @param hqspi QSPI handle + * @param pData pointer to data buffer. * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1486,10 +1485,10 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Configure the QSPI Automatic Polling Mode in blocking mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the polling configuration information. - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. + * @param Timeout Timeout duration * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1587,9 +1586,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy /** * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the polling configuration information. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1691,9 +1690,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman /** * @brief Configure the Memory Mapped mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the memory mapped configuration information. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the memory mapped configuration information. * @note This function is used only in Memory mapped Mode * @retval HAL status */ @@ -1780,7 +1779,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT /** * @brief Transfer Error callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) @@ -1795,7 +1794,7 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Abort completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1810,7 +1809,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Command completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1825,7 +1824,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1840,7 +1839,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1856,7 +1855,7 @@ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief FIFO Threshold callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) @@ -1871,7 +1870,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Status Match callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) @@ -1886,7 +1885,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Timeout callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) @@ -1902,8 +1901,8 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Register a User QSPI Callback * To be used instead of the weak (surcharged) predefined callback - * @param hqspi : QSPI handle - * @param CallbackId : ID of the callback to be registered + * @param hqspi QSPI handle + * @param CallbackId ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID @@ -1915,7 +1914,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID - * @param pCallback : pointer to the Callback function + * @param pCallback pointer to the Callback function * @retval status */ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback) @@ -2008,8 +2007,8 @@ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI /** * @brief Unregister a User QSPI Callback * QSPI Callback is redirected to the weak (surcharged) predefined callback - * @param hqspi : QSPI handle - * @param CallbackId : ID of the callback to be unregistered + * @param hqspi QSPI handle + * @param CallbackId ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID @@ -2128,7 +2127,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS /** * @brief Return the QSPI handle state. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL state */ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) @@ -2139,7 +2138,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) /** * @brief Return the QSPI error code. -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval QSPI Error Code */ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) @@ -2149,7 +2148,7 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission. -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) @@ -2177,25 +2176,33 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) } } - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); - - /* Wait until TC flag is set to go back in idle state */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); - - if (status == HAL_OK) + if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) { - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + + /* Wait until TC flag is set to go back in idle state */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); + + if (status == HAL_OK) + { + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + + /* Wait until BUSY flag is reset */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + } - /* Wait until BUSY flag is reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + if (status == HAL_OK) + { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + + /* Update state */ + hqspi->State = HAL_QSPI_STATE_READY; + } } - - if (status == HAL_OK) + else { - /* Reset functional mode configuration to indirect write mode by default */ - CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); - /* Update state */ hqspi->State = HAL_QSPI_STATE_READY; } @@ -2206,7 +2213,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission (non-blocking function) -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) @@ -2248,22 +2255,30 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) } else { - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - - /* Enable the QSPI Transfer Complete Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); - - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) + { + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + + /* Enable the QSPI Transfer Complete Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); + + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + } + else + { + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + } } } return status; } /** @brief Set QSPI timeout. - * @param hqspi : QSPI handle. - * @param Timeout : Timeout for the QSPI memory access. + * @param hqspi QSPI handle. + * @param Timeout Timeout for the QSPI memory access. * @retval None */ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) @@ -2272,8 +2287,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) } /** @brief Set QSPI Fifo threshold. - * @param hqspi : QSPI handle. - * @param Threshold : Threshold of the Fifo (value between 1 and 16). + * @param hqspi QSPI handle. + * @param Threshold Threshold of the Fifo (value between 1 and 16). * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) @@ -2305,7 +2320,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t } /** @brief Get QSPI Fifo threshold. - * @param hqspi : QSPI handle. + * @param hqspi QSPI handle. * @retval Fifo threshold (value between 1 and 16) */ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) @@ -2314,8 +2329,8 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) } /** @brief Set FlashID. - * @param hqspi : QSPI handle. - * @param FlashID : Index of the flash memory to be accessed. + * @param hqspi QSPI handle. + * @param FlashID Index of the flash memory to be accessed. * This parameter can be a value of @ref QSPI_Flash_Select. * @note The FlashID is ignored when dual flash mode is enabled. * @retval HAL status @@ -2364,7 +2379,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashI /** * @brief DMA QSPI receive process complete callback. - * @param hmdma : MDMA handle + * @param hmdma MDMA handle * @retval None */ static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma) @@ -2378,7 +2393,7 @@ static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma) /** * @brief DMA QSPI transmit process complete callback. - * @param hmdma : MDMA handle + * @param hmdma MDMA handle * @retval None */ static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma) @@ -2392,7 +2407,7 @@ static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma) /** * @brief DMA QSPI communication error callback. - * @param hmdma : MDMA handle + * @param hmdma MDMA handle * @retval None */ static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma) @@ -2414,7 +2429,7 @@ static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma) /** * @brief MDMA QSPI abort complete callback. - * @param hmdma : MDMA handle + * @param hmdma MDMA handle * @retval None */ static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma) @@ -2453,11 +2468,11 @@ static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma) /** * @brief Wait for a flag state until timeout. - * @param hqspi : QSPI handle - * @param Flag : Flag checked - * @param State : Value of the flag expected - * @param Tickstart : Tick start value - * @param Timeout : Duration of the timeout + * @param hqspi QSPI handle + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Tickstart Tick start value + * @param Timeout Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, @@ -2483,9 +2498,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp /** * @brief Configure the communication registers. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information - * @param FunctionalMode : functional mode to configured + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information + * @param FunctionalMode functional mode to configured * This parameter can be one of the following values: * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode @@ -2649,5 +2664,3 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin */ #endif /* defined(QUADSPI) */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ramecc.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ramecc.c index 54491f939..628f8f041 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ramecc.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ramecc.c @@ -9,6 +9,17 @@ * + Monitoring operation functions * + Error information functions * + State and error functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -17,7 +28,7 @@ (#) Enable and latch error information through HAL_RAMECC_Init(). (#) For a given Monitor, enable and disable interrupt through - HAL_RAMECC_EnableNotifiaction(). + HAL_RAMECC_EnableNotification(). To enable a notification for a given RAMECC instance, use global interrupts. To enable a notification for only RAMECC monitor, use monitor interrupts. @@ -33,11 +44,12 @@ *** Interrupt mode *** ====================== [..] - (+) Use HAL_RAMECC_EnableNotifiaction() to enable interrupts for a + (+) Use HAL_RAMECC_EnableNotification() to enable interrupts for a given error. (+) Configure the RAMECC interrupt priority using HAL_NVIC_SetPriority(). (+) Enable the RAMECC IRQ handler using HAL_NVIC_EnableIRQ(). + (+) Start RAMECC latch failing information using HAL_RAMECC_StartMonitor(). *** Failing information *** ====================== @@ -69,18 +81,6 @@ (+) __HAL_RAMECC_CLEAR_FLAG : Clear the current RAMECC Monitor selected flag. @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -689,4 +689,3 @@ uint32_t HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c index b5e93c78b..c95945d6b 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c @@ -54,14 +54,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -486,9 +484,23 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc { return HAL_ERROR; } - /* Otherwise, just the calibration is allowed */ + /* Otherwise, only HSI division and calibration are allowed */ else { + /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + { + if((uint32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } @@ -1779,4 +1791,3 @@ __weak void HAL_RCC_CCSCallback(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c index afde46b3b..2b8800e34 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c @@ -10,14 +10,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -3757,4 +3755,3 @@ __weak void HAL_RCCEx_LSECSS_Callback(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c index ff1cf102d..105fd26d0 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c @@ -9,6 +9,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -31,8 +42,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_RNG_RegisterCallback() to register a user callback. - Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks: + Use Function HAL_RNG_RegisterCallback() to register a user callback. + Function HAL_RNG_RegisterCallback() allows to register following callbacks: (+) ErrorCallback : RNG Error Callback. (+) MspInitCallback : RNG MspInit. (+) MspDeInitCallback : RNG MspDeInit. @@ -40,9 +51,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default + Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ErrorCallback : RNG Error Callback. @@ -51,16 +62,16 @@ [..] For specific callback ReadyDataCallback, use dedicated register callbacks: - respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback(). + respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback(). [..] - By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET + By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - example @ref HAL_RNG_ErrorCallback(). + example HAL_RNG_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init() - and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_RNG_Init() + and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -69,8 +80,8 @@ in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit() - or @ref HAL_RNG_Init() function. + using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit() + or HAL_RNG_Init() function. [..] When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or @@ -79,17 +90,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -232,9 +232,13 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - return HAL_ERROR; + /* New check to avoid false timeout detection in case of preemption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } } } #else @@ -258,9 +262,13 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_ERROR; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - return HAL_ERROR; + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + { + hrng->State = HAL_RNG_STATE_ERROR; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } } } @@ -307,11 +315,15 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - return HAL_ERROR; + /* New check to avoid false timeout detection in case of preemption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } } } @@ -467,7 +479,7 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call /** * @brief Unregister an RNG Callback - * RNG callabck is redirected to the weak predefined callback + * RNG callback is redirected to the weak predefined callback * @param hrng RNG handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -683,11 +695,15 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - return HAL_ERROR; + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } } } @@ -1004,8 +1020,7 @@ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng) #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ return HAL_ERROR; } - } - while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)); + } while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)); if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) { @@ -1033,8 +1048,7 @@ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng) #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ return HAL_ERROR; } - } - while (HAL_IS_BIT_SET(hrng->Instance->SR, RNG_FLAG_SECS)); + } while (HAL_IS_BIT_SET(hrng->Instance->SR, RNG_FLAG_SECS)); } /* Update the error code */ hrng->ErrorCode &= ~ HAL_RNG_ERROR_SEED; @@ -1058,4 +1072,3 @@ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng_ex.c index 4377a0408..a063df777 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng_ex.c @@ -11,13 +11,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -31,7 +30,7 @@ #if defined(RNG) -/** @addtogroup RNGEx +/** @addtogroup RNG_Ex * @brief RNG Extended HAL module driver. * @{ */ @@ -40,7 +39,7 @@ #if defined(RNG_CR_CONDRST) /* Private types -------------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Defines RNGEx Private Defines +/** @defgroup RNG_Ex_Private_Defines RNGEx Private Defines * @{ */ /* Health test control register information to use in CCM algorithm */ @@ -55,7 +54,7 @@ */ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Constants RNGEx Private Constants +/** @defgroup RNG_Ex_Private_Constants RNGEx Private Constants * @{ */ #define RNG_TIMEOUT_VALUE 2U @@ -67,11 +66,11 @@ /* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNGEx_Exported_Functions +/** @addtogroup RNG_Ex_Exported_Functions * @{ */ -/** @addtogroup RNGEx_Exported_Functions_Group1 +/** @addtogroup RNG_Ex_Exported_Functions_Group1 * @brief Configuration functions * @verbatim @@ -156,9 +155,13 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - return HAL_ERROR; + /* New check to avoid false timeout detection in case of prememption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } } } @@ -280,7 +283,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) * @} */ -/** @addtogroup RNGEx_Exported_Functions_Group2 +/** @addtogroup RNG_Ex_Exported_Functions_Group2 * @brief Recover from seed error function * @verbatim @@ -348,4 +351,3 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c index b158d38e3..467387345 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c @@ -15,6 +15,17 @@ * + RTC Tamper and TimeStamp Pins Selection * + Interrupts and flags management * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### RTC Operating Condition ##### @@ -93,9 +104,9 @@ The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback. + Use Function HAL_RTC_RegisterCallback() to register an interrupt callback. - Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks: + Function HAL_RTC_RegisterCallback() allows to register following callbacks: (+) AlarmAEventCallback : RTC Alarm A Event callback. (+) AlarmBEventCallback : RTC Alarm B Event callback. (+) TimeStampEventCallback : RTC TimeStamp Event callback. @@ -108,9 +119,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default + Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) AlarmAEventCallback : RTC Alarm A Event callback. @@ -123,13 +134,13 @@ (+) MspInitCallback : RTC MspInit callback. (+) MspDeInitCallback : RTC MspDeInit callback. - By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, + By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, all callbacks are set to the corresponding weak functions : - examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback(). + examples AlarmAEventCallback(), WakeUpTimerEventCallback(). Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function - in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null + in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() + If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. @@ -137,26 +148,14 @@ in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit() - or @ref HAL_RTC_Init() function. + using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit() + or HAL_RTC_Init() function. When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -393,10 +392,10 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) /* Wait till WUTWF flag is set and if Time out is reached exit */ #if defined(RTC_ICSR_WUTWF) - while (((hrtc->Instance->ICSR) & RTC_ICSR_WUTWF) == 0U) + while ((((hrtc->Instance->ICSR) & RTC_ICSR_WUTWF) == 0U) && (status != HAL_TIMEOUT)) #endif /* RTC_ICSR_WUTWF */ #if defined(RTC_ISR_WUTWF) - while (((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == 0U) + while ((((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == 0U) && (status != HAL_TIMEOUT)) #endif /* RTC_ISR_WUTWF */ { if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) @@ -406,6 +405,7 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) /* Set RTC state */ hrtc->State = HAL_RTC_STATE_TIMEOUT; + status = HAL_TIMEOUT; } } @@ -1495,8 +1495,17 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB); } -#if !defined(DUAL_CORE) /* RTC Alarm Interrupt Configuration: EXTI configuration */ +#if defined(DUAL_CORE) + if (HAL_GetCurrentCPUID() == CM7_CPUID) + { + __HAL_RTC_ALARM_EXTI_ENABLE_IT(); + } + else + { + __HAL_RTC_ALARM_EXTID2_ENABLE_IT(); + } +#else /* SINGLE_CORE */ __HAL_RTC_ALARM_EXTI_ENABLE_IT(); #endif @@ -1950,7 +1959,7 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) tickstart = HAL_GetTick(); /* Wait till RTC is in INIT state and if Time out is reached exit */ - while ((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) + while (((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) { if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { @@ -1968,7 +1977,7 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) tickstart = HAL_GetTick(); /* Wait till RTC is in INIT state and if Time out is reached exit */ - while ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U) + while (((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U) && (status != HAL_TIMEOUT)) { if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { @@ -2072,4 +2081,3 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c index e1a0d3aba..ba820c6b2 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c @@ -11,6 +11,17 @@ * + Extended Control functions * + Extended RTC features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -86,18 +97,6 @@ function. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -251,10 +250,19 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /* Enable IT timestamp */ __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc, RTC_IT_TS); -#if !defined(DUAL_CORE) /* RTC timestamp Interrupt Configuration: EXTI configuration */ +#if defined(DUAL_CORE) + if (HAL_GetCurrentCPUID() == CM7_CPUID) + { + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); + } + else + { + __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_ENABLE_IT(); + } +#else /* SINGLE_CORE */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); -#endif +#endif /* DUAL_CORE */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); @@ -912,10 +920,19 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTyp /* Copy desired configuration into configuration register */ hrtc->Instance->TAMPCR = tmpreg; -#if !defined(DUAL_CORE) /* RTC Tamper Interrupt Configuration: EXTI configuration */ +#if defined(DUAL_CORE) + if (HAL_GetCurrentCPUID() == CM7_CPUID) + { + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); + } + else + { + __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_ENABLE_IT(); + } +#else /* SINGLE_CORE */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); -#endif +#endif /* DUAL_CORE */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); @@ -1315,7 +1332,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) hrtc->TimeStampEventCallback(hrtc); #else HAL_RTCEx_TimeStampEventCallback(hrtc); -#endif +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ /* Not immediately clear flags because the content of RTC_TSTR and RTC_TSDR are cleared when TSF bit is reset.*/ hrtc->Instance->SCR = RTC_SCR_CTSF; } @@ -1336,7 +1353,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #else /* Tamper1 callback */ HAL_RTCEx_Tamper1EventCallback(hrtc); -#endif +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } #endif /* TAMP_CR1_TAMP1E */ @@ -1350,7 +1367,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #else /* Tamper2 callback */ HAL_RTCEx_Tamper2EventCallback(hrtc); -#endif +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } #endif /* TAMP_CR1_TAMP2E */ @@ -1364,7 +1381,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #else /* Tamper3 callback */ HAL_RTCEx_Tamper3EventCallback(hrtc); -#endif +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } #endif /* TAMP_CR1_TAMP3E */ @@ -1378,7 +1395,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #else /* Call Internal Tamper Event by-default callback */ HAL_RTCEx_InternalTamper1EventCallback(hrtc); -#endif +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } #endif /* TAMP_CR1_ITAMP1E */ @@ -1392,7 +1409,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #else /* Call Internal Tamper Event by-default callback */ HAL_RTCEx_InternalTamper2EventCallback(hrtc); -#endif +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } #endif /* TAMP_CR1_ITAMP2E */ @@ -1406,7 +1423,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #else /* Call Internal Tamper Event by-default callback */ HAL_RTCEx_InternalTamper3EventCallback(hrtc); -#endif +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } #endif /* TAMP_CR1_ITAMP3E */ @@ -1420,7 +1437,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #else /* Call Internal Tamper Event by-default callback */ HAL_RTCEx_InternalTamper4EventCallback(hrtc); -#endif +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } #endif /* TAMP_CR1_ITAMP4E */ @@ -1434,7 +1451,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #else /* Call Internal Tamper Event by-default callback */ HAL_RTCEx_InternalTamper5EventCallback(hrtc); -#endif +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } #endif /* TAMP_CR1_ITAMP5E */ @@ -1448,7 +1465,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #else /* Call Internal Tamper Event by-default callback */ HAL_RTCEx_InternalTamper6EventCallback(hrtc); -#endif +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } #endif /* TAMP_CR1_ITAMP6E */ @@ -1462,7 +1479,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #else /* Call Internal Tamper Event by-default callback */ HAL_RTCEx_InternalTamper8EventCallback(hrtc); -#endif +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } #endif /* TAMP_CR1_ITAMP8E */ @@ -1483,7 +1500,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) { __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_CLEAR_FLAG(); } -#else /* SINGLE_CORE */ +#else /* SINGLE_CORE */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); #endif /* DUAL_CORE */ @@ -2118,10 +2135,19 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t hrtc->Instance->CR = CR_tmp; } -#if !defined(DUAL_CORE) /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ +#if defined(DUAL_CORE) + if (HAL_GetCurrentCPUID() == CM7_CPUID) + { + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); + } + else + { + __HAL_RTC_WAKEUPTIMER_EXTID2_ENABLE_IT(); + } +#else /* SINGLE_CORE */ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); -#endif +#endif /* DUAL_CORE */ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); @@ -2227,7 +2253,7 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) { __HAL_RTC_WAKEUPTIMER_EXTID2_CLEAR_FLAG(); } -#else /* SINGLE_CORE */ +#else /* SINGLE_CORE */ __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); #endif /* DUAL_CORE */ @@ -2959,4 +2985,3 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef * hrtc, uint32_ * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai.c index fefb0116e..42d7dd435 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -199,18 +210,6 @@ and weak (surcharged) callbacks are used. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -2943,4 +2942,3 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai_ex.c index 2af598fc8..0567c0442 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai_ex.c @@ -10,13 +10,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -132,4 +131,3 @@ HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_Pdm * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c index 6bf4dcc5d..fc13c076f 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -182,7 +193,7 @@ The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_SD_RegisterCallback() to register a user callback, + Use Functions HAL_SD_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. @@ -197,9 +208,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. For specific callbacks TransceiverCallback use dedicated register callbacks: - respectively @ref HAL_SD_RegisterTransceiverCallback(). + respectively HAL_SD_RegisterTransceiverCallback(). - Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default + Use function HAL_SD_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. @@ -213,14 +224,14 @@ (+) MspDeInitCallback : SD MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. For specific callbacks TransceiverCallback use dedicated unregister callbacks: - respectively @ref HAL_SD_UnRegisterTransceiverCallback(). + respectively HAL_SD_UnRegisterTransceiverCallback(). - By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET + By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init - and @ref HAL_SD_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit + reset to the legacy weak (surcharged) functions in the HAL_SD_Init + and HAL_SD_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -228,8 +239,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit - or @ref HAL_SD_Init function. + using HAL_SD_RegisterCallback before calling HAL_SD_DeInit + or HAL_SD_Init function. When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -237,17 +248,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -269,7 +269,7 @@ * @{ */ /* Frequencies used in the driver for clock divider calculation */ -#define SD_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */ +#define SD_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */ #define SD_NORMAL_SPEED_FREQ 25000000U /* Normal speed phase : 25 MHz max */ #define SD_HIGH_SPEED_FREQ 50000000U /* High speed phase : 50 MHz max */ /* Private macro -------------------------------------------------------------*/ @@ -398,7 +398,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } - hsd->State = HAL_SD_STATE_BUSY; + hsd->State = HAL_SD_STATE_PROGRAMMING; /* Initialize the Card parameters */ if (HAL_SD_InitCard(hsd) != HAL_OK) @@ -470,7 +470,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) { uint32_t errorstate; SD_InitTypeDef Init; - uint32_t sdmmc_clk; + uint32_t sdmmc_clk = 0U; /* Default SDMMC peripheral configuration for SD card initialization */ Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; @@ -2295,7 +2295,7 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef } /** - * @brief Gets the SD status info. + * @brief Gets the SD status info.( shall be called if there is no SD transaction ongoing ) * @param hsd: Pointer to SD handle * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that * will contain the SD card status information @@ -2307,6 +2307,11 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT uint32_t errorstate; HAL_StatusTypeDef status = HAL_OK; + if (hsd->State == HAL_SD_STATE_BUSY) + { + return HAL_ERROR; + } + errorstate = SD_SendSDStatus(hsd, sd_status); if (errorstate != HAL_SD_ERROR_NONE) { @@ -2355,6 +2360,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT status = HAL_ERROR; } + return status; } @@ -2394,7 +2400,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t { SDMMC_InitTypeDef Init; uint32_t errorstate; - uint32_t sdmmc_clk; + uint32_t sdmmc_clk = 0U; HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ @@ -2476,7 +2482,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t } else { - if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ) + if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ) { Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ); } @@ -2502,7 +2508,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t } else { - if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ) + if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ) { Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ); } @@ -2926,7 +2932,8 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) { HAL_SD_CardCSDTypeDef CSD; uint32_t errorstate; - uint16_t sd_rca = 1U; + uint16_t sd_rca = 0U; + uint32_t tickstart = HAL_GetTick(); /* Check the power State */ if (SDMMC_GetPowerState(hsd->Instance) == 0U) @@ -2957,10 +2964,17 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) { /* Send CMD3 SET_REL_ADDR with argument 0 */ /* SD Card publishes its RCA. */ - errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca); - if (errorstate != HAL_SD_ERROR_NONE) + while (sd_rca == 0U) { - return errorstate; + errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca); + if (errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + if ((HAL_GetTick() - tickstart) >= SDMMC_CMDTIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } } } if (hsd->SdCard.CardType != CARD_SECURED) @@ -3030,7 +3044,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ errorstate = SDMMC_CmdOperCond(hsd->Instance); - if (errorstate != HAL_SD_ERROR_NONE) + if (errorstate == SDMMC_ERROR_TIMEOUT) /* No response to CMD8 */ { hsd->SdCard.CardVersion = CARD_V1_X; /* CMD0: GO_IDLE_STATE */ @@ -3088,7 +3102,10 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) return HAL_SD_ERROR_INVALID_VOLTRANGE; } - if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ + /* Set default card type */ + hsd->SdCard.CardType = CARD_SDSC; + + if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) { hsd->SdCard.CardType = CARD_SDHC_SDXC; #if (USE_SD_TRANSCEIVER != 0U) @@ -4028,5 +4045,3 @@ __weak void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c index 67124cb77..1cc19e313 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd_ex.c @@ -7,6 +7,17 @@ * functionalities of the Secure Digital (SD) peripheral: * + Extended features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -19,17 +30,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -311,9 +311,3 @@ HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABu /** * @} */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c index 47c34a5d8..34c5cfbff 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c @@ -6,6 +6,17 @@ * This file provides a generic firmware to drive SDRAM memories mounted * as external device. * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -63,25 +74,25 @@ The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_SDRAM_RegisterCallback() to register a user callback, + Use Functions HAL_SDRAM_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) MspInitCallback : SDRAM MspInit. (+) MspDeInitCallback : SDRAM MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_SDRAM_UnRegisterCallback() to reset a callback to the default + Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) MspInitCallback : SDRAM MspInit. (+) MspDeInitCallback : SDRAM MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET + By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SDRAM_Init - and @ref HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SDRAM_Init and @ref HAL_SDRAM_DeInit + reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init + and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -89,8 +100,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SDRAM_RegisterCallback before calling @ref HAL_SDRAM_DeInit - or @ref HAL_SDRAM_Init function. + using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit + or HAL_SDRAM_Init function. When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -98,17 +109,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1307,5 +1307,3 @@ static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma) * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c index 900480304..8d5e999a3 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -167,17 +178,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -809,11 +809,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; - uint8_t *ptmpdata = pData; + const uint8_t *ptmpdata = pData; /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) @@ -983,7 +983,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin * @param Size amount of data to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) @@ -1141,7 +1141,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, * @param Size amount of data to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) @@ -2422,43 +2422,43 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard { case SMARTCARD_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_PLL2Q: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - tmpreg = (uint16_t)(((pll2_clocks.PLL2_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + tmpreg = (uint32_t)(((pll2_clocks.PLL2_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_PLL3Q: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - tmpreg = (uint16_t)(((pll3_clocks.PLL3_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + tmpreg = (uint32_t)(((pll3_clocks.PLL3_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) { - tmpreg = (uint16_t)((((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) / + tmpreg = (uint32_t)((((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); } else { - tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + tmpreg = (uint32_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); } break; case SMARTCARD_CLOCKSOURCE_CSI: - tmpreg = (uint16_t)(((CSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + tmpreg = (uint32_t)(((CSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_LSE: - tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + tmpreg = (uint32_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; default: @@ -2469,7 +2469,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard /* USARTDIV must be greater than or equal to 0d16 */ if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) { - hsmartcard->Instance->BRR = tmpreg; + hsmartcard->Instance->BRR = (uint16_t)tmpreg; } else { @@ -2600,11 +2600,12 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar } /** - * @brief Handle SMARTCARD Communication Timeout. + * @brief Handle SMARTCARD Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @param Flag Specifies the SMARTCARD flag to check. - * @param Status The new Flag status (SET or RESET). + * @param Status The actual Flag status (SET or RESET). * @param Tickstart Tick start value * @param Timeout Timeout duration. * @retval HAL status @@ -3204,4 +3205,3 @@ static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard_ex.c index 35505d8b1..5c76a67d6 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard_ex.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions * + Peripheral Control functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================= ##### SMARTCARD peripheral extended features ##### @@ -27,17 +38,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -493,4 +493,3 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus.c index 3d0c84370..0504c2aaa 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus.c @@ -10,6 +10,17 @@ * + IO operation functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -20,7 +31,7 @@ (#) Declare a SMBUS_HandleTypeDef handle structure, for example: SMBUS_HandleTypeDef hsmbus; - (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API: + (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API: (##) Enable the SMBUSx interface clock (##) SMBUS pins configuration (+++) Enable the clock for the SMBUS GPIOs @@ -33,69 +44,75 @@ Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode, Peripheral mode and Packet Error Check mode in the hsmbus Init structure. - (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init() API: + (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API: (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API. + by calling the customized HAL_SMBUS_MspInit(&hsmbus) API. - (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady() + (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady() (#) For SMBUS IO operations, only one mode of operations is available within this driver *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Transmit_IT() - (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback() - (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Receive_IT() - (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback() - (+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT() + (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode + using HAL_SMBUS_Master_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback() + (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode + using HAL_SMBUS_Master_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback() + (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT() (++) The associated previous transfer callback is called at the end of abort process - (++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit - (++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive + (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit + (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode - using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT() - (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). - (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback() - (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT() - (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback() - (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Receive_IT() - (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback() - (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT() - (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() - to check the Alert Error Code using function @ref HAL_SMBUS_GetError() - (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError() - (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() - to check the Error Code using function @ref HAL_SMBUS_GetError() + using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT() + (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction + request by master/host (Write/Read). + (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_ListenCpltCallback() + (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode + using HAL_SMBUS_Slave_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback() + (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode + using HAL_SMBUS_Slave_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback() + (+) Enable/Disable the SMBUS alert mode using + HAL_SMBUS_EnableAlert_IT() or HAL_SMBUS_DisableAlert_IT() + (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_ErrorCallback() + to check the Alert Error Code using function HAL_SMBUS_GetError() + (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError() + (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_SMBUS_ErrorCallback() + to check the Error Code using function HAL_SMBUS_GetError() *** SMBUS HAL driver macros list *** ================================== [..] Below the list of most used macros in SMBUS HAL driver. - (+) @ref __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral - (+) @ref __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral - (+) @ref __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not - (+) @ref __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag - (+) @ref __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt - (+) @ref __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt + (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral + (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral + (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not + (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag + (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt + (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback() + Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterAddrCallback() to register an interrupt callback. [..] - Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks: + Function HAL_SMBUS_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. @@ -107,11 +124,11 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback. + For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback. [..] - Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default + Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default weak function. - @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. @@ -123,24 +140,24 @@ (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. [..] - For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback. + For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback. [..] - By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET + By default, after the HAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback(). + examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when + reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() + If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit() - or @ref HAL_SMBUS_Init() function. + using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit() + or HAL_SMBUS_Init() function. [..] When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -150,18 +167,6 @@ (@) You can refer to the SMBUS HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -203,20 +208,28 @@ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions * @{ */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, - uint32_t Timeout); +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, + FlagStatus Status, uint32_t Timeout); -static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +/* Private functions for SMBUS transfer IRQ handler */ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); +/* Private functions to centralize the enable/disable of Interrupts */ +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); +/* Private function to flush TXDR register */ +static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus); + +/* Private function to handle start, restart or stop a transfer */ +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, + uint32_t Mode, uint32_t Request); -static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request); +/* Private function to Convert Specific options */ +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); /** * @} */ @@ -364,15 +377,20 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ /* Configure SMBUSx: Dual mode and Own Address2 */ - hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U)); + hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \ + (hsmbus->Init.OwnAddress2Masks << 8U)); /*---------------------------- SMBUSx CR1 Configuration ------------------------*/ /* Configure SMBUSx: Generalcall and NoStretch mode */ - hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter); + hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \ + hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | \ + hsmbus->Init.AnalogFilter); - /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */ - if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) - && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))) + /* Enable Slave Byte Control only in case of Packet Error Check is enabled + and SMBUS Peripheral is set in Slave mode */ + if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \ + ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ + (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))) { hsmbus->Instance->CR1 |= I2C_CR1_SBC; } @@ -581,7 +599,8 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -695,7 +714,8 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SM * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID) +HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -790,7 +810,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_ * @param pCallback pointer to the Address Match Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, + pSMBUS_AddrCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -914,8 +935,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t tmp; @@ -955,7 +976,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, - SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_GENERATE_START_WRITE); } else { @@ -965,9 +987,11 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* Store current volatile XferOptions, misra rule */ tmp = hsmbus->XferOptions; - if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \ + (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -976,7 +1000,9 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + hsmbus->XferOptions, + SMBUS_GENERATE_START_WRITE); } /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ @@ -1057,7 +1083,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, - SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_GENERATE_START_READ); } else { @@ -1067,9 +1094,11 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Store current volatile XferOptions, Misra rule */ tmp = hsmbus->XferOptions; - if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \ + (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -1078,7 +1107,9 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + hsmbus->XferOptions, + SMBUS_GENERATE_START_READ); } } @@ -1222,12 +1253,14 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, - SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_NO_STARTSTOP); } else { /* Set NBYTE to transmit */ - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ @@ -1313,7 +1346,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U)) { - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); } else { @@ -1576,7 +1610,8 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1); /* SMBUS in mode Transmitter ---------------------------------------------------*/ - if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | + SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || @@ -1600,7 +1635,8 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS in mode Receiver ----------------------------------------------------*/ - if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | + SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || @@ -1720,7 +1756,8 @@ __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) * @param AddrMatchCode Address Match Code * @retval None */ -__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) +__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, + uint16_t AddrMatchCode) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); @@ -1842,6 +1879,9 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t /* No need to generate STOP, it is automatically done */ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -1967,13 +2007,15 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t if (hsmbus->XferCount > MAX_NBYTE_SIZE) { SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, - (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), + SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) @@ -2130,6 +2172,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); } @@ -2151,6 +2196,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S /* Set ErrorCode corresponding to a Non-Acknowledge */ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hsmbus); @@ -2225,7 +2273,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S else { /* Set Reload for next Bytes */ - SMBUS_TransferConfig(hsmbus, 0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, 1, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_NO_STARTSTOP); /* Ack last Byte Read */ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; @@ -2237,14 +2287,16 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S { if (hsmbus->XferCount > MAX_NBYTE_SIZE) { - SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), + SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, + (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) @@ -2489,7 +2541,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) uint32_t tmperror; /* SMBUS Bus error interrupt occurred ------------------------------------*/ - if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; @@ -2498,7 +2551,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; @@ -2507,7 +2561,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ - if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; @@ -2516,7 +2571,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ - if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; @@ -2525,7 +2581,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ - if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; @@ -2534,7 +2591,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ - if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; @@ -2542,7 +2600,10 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); } - /* Store current volatile hsmbus->State, misra rule */ + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + + /* Store current volatile hsmbus->ErrorCode, misra rule */ tmperror = hsmbus->ErrorCode; /* Call the Error Callback in case of Error detected */ @@ -2582,8 +2643,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, - uint32_t Timeout) +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, + FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -2612,6 +2673,27 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu return HAL_OK; } +/** + * @brief SMBUS Tx data register flush process. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + { + hsmbus->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXE) == RESET) + { + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TXE); + } +} + /** * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set). * @param hsmbus SMBUS handle. @@ -2632,8 +2714,8 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request) +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, + uint32_t Mode, uint32_t Request) { /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); @@ -2644,9 +2726,10 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \ - I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request)); } /** @@ -2703,5 +2786,3 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus_ex.c new file mode 100644 index 000000000..354966a13 --- /dev/null +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus_ex.c @@ -0,0 +1,258 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_smbus_ex.c + * @author MCD Application Team + * @brief SMBUS Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of SMBUS Extended peripheral: + * + Extended features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### SMBUS peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the SMBUS interface for STM32H7xx + devices contains the following additional features + + (+) Disable or enable wakeup from Stop mode(s) + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + (#) Configure the enable or disable of SMBUS Wake Up Mode using the functions : + (++) HAL_SMBUSEx_EnableWakeUp() + (++) HAL_SMBUSEx_DisableWakeUp() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_SMBUSEx_EnableFastModePlus() + (++) HAL_SMBUSEx_DisableFastModePlus() + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup SMBUSEx SMBUSEx + * @brief SMBUS Extended HAL module driver + * @{ + */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions + * @{ + */ + +/** @defgroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions + * +@verbatim + =============================================================================== + ##### WakeUp Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ + +/** + * @brief Enable SMBUS wakeup from Stop mode(s). + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Enable wakeup from stop mode */ + hsmbus->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable SMBUS wakeup from Stop mode(s). + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Disable wakeup from stop mode */ + hsmbus->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Enable the SMBUS fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref SMBUSEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using SMBUS_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be enabled + * only by using SMBUS_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be enabled + * only by using SMBUS_FASTMODEPLUS_I2C4 parameter. + * @note For all I2C5 pins fast mode plus driving capability can be enabled + * only by using SMBUS_FASTMODEPLUS_I2C5 parameter. + * @retval None + */ +void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the SMBUS fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref SMBUSEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using SMBUS_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be disabled + * only by using SMBUS_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be disabled + * only by using SMBUS_FASTMODEPLUS_I2C4 parameter. + * @note For all I2C5 pins fast mode plus driving capability can be disabled + * only by using SMBUS_FASTMODEPLUS_I2C5 parameter. + * @retval None + */ +void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SMBUS_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spdifrx.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spdifrx.c index e0536b645..7bef68a09 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spdifrx.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spdifrx.c @@ -8,6 +8,18 @@ * + Data transfers functions * + DMA transfers management * + Interrupts and flags management + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -142,18 +154,6 @@ are set to the corresponding weak functions. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -188,7 +188,8 @@ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma); static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma); static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif); static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif); -static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart); +static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, + FlagStatus Status, uint32_t Timeout, uint32_t tickstart); /** * @} */ @@ -238,7 +239,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) uint32_t tmpreg; /* Check the SPDIFRX handle allocation */ - if(hspdif == NULL) + if (hspdif == NULL) { return HAL_ERROR; } @@ -258,7 +259,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) assert_param(IS_SYMBOL_CLOCK_GEN(hspdif->Init.BackupSymbolClockGen)); #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - if(hspdif->State == HAL_SPDIFRX_STATE_RESET) + if (hspdif->State == HAL_SPDIFRX_STATE_RESET) { /* Allocate lock resource and initialize it */ hspdif->Lock = HAL_UNLOCKED; @@ -269,7 +270,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) hspdif->CxCpltCallback = HAL_SPDIFRX_CxCpltCallback; /* Legacy weak CxCpltCallback */ hspdif->ErrorCallback = HAL_SPDIFRX_ErrorCallback; /* Legacy weak ErrorCallback */ - if(hspdif->MspInitCallback == NULL) + if (hspdif->MspInitCallback == NULL) { hspdif->MspInitCallback = HAL_SPDIFRX_MspInit; /* Legacy weak MspInit */ } @@ -278,7 +279,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) hspdif->MspInitCallback(hspdif); } #else - if(hspdif->State == HAL_SPDIFRX_STATE_RESET) + if (hspdif->State == HAL_SPDIFRX_STATE_RESET) { /* Allocate lock resource and initialize it */ hspdif->Lock = HAL_UNLOCKED; @@ -313,14 +314,14 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) hspdif->Init.ChannelStatusMask | hspdif->Init.ValidityBitMask | hspdif->Init.ParityErrorMask - ); + ); - if(hspdif->Init.SymbolClockGen == ENABLE) + if (hspdif->Init.SymbolClockGen == ENABLE) { tmpreg |= SPDIFRX_CR_CKSEN; } - if(hspdif->Init.BackupSymbolClockGen == ENABLE) + if (hspdif->Init.BackupSymbolClockGen == ENABLE) { tmpreg |= SPDIFRX_CR_CKSBKPEN; } @@ -343,7 +344,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) { /* Check the SPDIFRX handle allocation */ - if(hspdif == NULL) + if (hspdif == NULL) { return HAL_ERROR; } @@ -357,7 +358,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) __HAL_SPDIFRX_IDLE(hspdif); #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - if(hspdif->MspDeInitCallback == NULL) + if (hspdif->MspDeInitCallback == NULL) { hspdif->MspDeInitCallback = HAL_SPDIFRX_MspDeInit; /* Legacy weak MspDeInit */ } @@ -427,11 +428,12 @@ __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, + pSPDIFRX_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* Update the error code */ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; @@ -440,7 +442,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA /* Process locked */ __HAL_LOCK(hspdif); - if(HAL_SPDIFRX_STATE_READY == hspdif->State) + if (HAL_SPDIFRX_STATE_READY == hspdif->State) { switch (CallbackID) { @@ -480,7 +482,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA break; } } - else if(HAL_SPDIFRX_STATE_RESET == hspdif->State) + else if (HAL_SPDIFRX_STATE_RESET == hspdif->State) { switch (CallbackID) { @@ -495,7 +497,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA default : /* Update the error code */ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; - /* Return error status */ + /* Return error status */ status = HAL_ERROR; break; } @@ -515,7 +517,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA /** * @brief Unregister a SPDIFRX Callback - * SPDIFRX callabck is redirected to the weak predefined callback + * SPDIFRX callback is redirected to the weak predefined callback * @param hspdif SPDIFRX handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -528,14 +530,15 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA * @arg @ref HAL_SPDIFRX_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status */ -HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID) +HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, + HAL_SPDIFRX_CallbackIDTypeDef CallbackID) { -HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hspdif); - if(HAL_SPDIFRX_STATE_READY == hspdif->State) + if (HAL_SPDIFRX_STATE_READY == hspdif->State) { switch (CallbackID) { @@ -562,12 +565,12 @@ HAL_StatusTypeDef status = HAL_OK; default : /* Update the error code */ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; - /* Return error status */ + /* Return error status */ status = HAL_ERROR; break; } } - else if(HAL_SPDIFRX_STATE_RESET == hspdif->State) + else if (HAL_SPDIFRX_STATE_RESET == hspdif->State) { switch (CallbackID) { @@ -613,7 +616,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF uint32_t tmpreg; /* Check the SPDIFRX handle allocation */ - if(hspdif == NULL) + if (hspdif == NULL) { return HAL_ERROR; } @@ -629,9 +632,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF /* Reset the old SPDIFRX CR configuration */ tmpreg = hspdif->Instance->CR; - if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) && - (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) || - ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode))) + if (((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) && + (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) || + ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode))) { return HAL_ERROR; } @@ -695,8 +698,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF (++) HAL_SPDIFRX_CxCpltCallback() @endverbatim -* @{ -*/ + * @{ + */ /** * @brief Receives an amount of data (Data Flow) in blocking mode. @@ -707,18 +710,19 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; uint16_t sizeCounter = Size; uint32_t *pTmpBuf = pData; - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(hspdif->State == HAL_SPDIFRX_STATE_READY) + if (hspdif->State == HAL_SPDIFRX_STATE_READY) { /* Process Locked */ __HAL_LOCK(hspdif); @@ -732,7 +736,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin tickstart = HAL_GetTick(); /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) + if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -741,13 +745,13 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin __HAL_SPDIFRX_RCV(hspdif); /* Receive data flow */ - while(sizeCounter > 0U) + while (sizeCounter > 0U) { /* Get tick */ tickstart = HAL_GetTick(); /* Wait until RXNE flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -780,18 +784,19 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; uint16_t sizeCounter = Size; uint32_t *pTmpBuf = pData; - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(hspdif->State == HAL_SPDIFRX_STATE_READY) + if (hspdif->State == HAL_SPDIFRX_STATE_READY) { /* Process Locked */ __HAL_LOCK(hspdif); @@ -805,7 +810,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uin tickstart = HAL_GetTick(); /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) + if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -814,13 +819,13 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uin __HAL_SPDIFRX_RCV(hspdif); /* Receive control flow */ - while(sizeCounter > 0U) + while (sizeCounter > 0U) { /* Get tick */ tickstart = HAL_GetTick(); /* Wait until CSRNE flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK) + if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -857,9 +862,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; - if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX)) + if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX)) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -885,7 +890,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, /* Enable the SPDIFRX RXNE interrupt */ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE); - if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) + if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) { /* Start synchronization */ __HAL_SPDIFRX_SYNC(hspdif); @@ -904,7 +909,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -942,9 +947,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; - if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX)) + if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX)) { - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -970,7 +975,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, /* Enable the SPDIFRX CSRNE interrupt */ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE); - if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) + if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) { /* Start synchronization */ __HAL_SPDIFRX_SYNC(hspdif); @@ -989,7 +994,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -1027,12 +1032,12 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX)) + if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX)) { /* Process Locked */ __HAL_LOCK(hspdif); @@ -1054,7 +1059,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError; /* Enable the DMA request */ - if(HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != HAL_OK) { /* Set SPDIFRX error */ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; @@ -1071,7 +1076,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/ hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN; - if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) + if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) { /* Start synchronization */ __HAL_SPDIFRX_SYNC(hspdif); @@ -1090,7 +1095,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -1128,12 +1133,12 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX)) + if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX)) { hspdif->pCsBuffPtr = pData; hspdif->CsXferSize = Size; @@ -1155,7 +1160,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError; /* Enable the DMA request */ - if(HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != HAL_OK) { /* Set SPDIFRX error */ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; @@ -1172,7 +1177,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/ hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN; - if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) + if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) { /* Start synchronization */ __HAL_SPDIFRX_SYNC(hspdif); @@ -1191,7 +1196,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -1256,21 +1261,21 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif) uint32_t itSource = hspdif->Instance->IMR; /* SPDIFRX in mode Data Flow Reception */ - if(((itFlag & SPDIFRX_FLAG_RXNE) == SPDIFRX_FLAG_RXNE) && ((itSource & SPDIFRX_IT_RXNE) == SPDIFRX_IT_RXNE)) + if (((itFlag & SPDIFRX_FLAG_RXNE) == SPDIFRX_FLAG_RXNE) && ((itSource & SPDIFRX_IT_RXNE) == SPDIFRX_IT_RXNE)) { __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE); SPDIFRX_ReceiveDataFlow_IT(hspdif); } /* SPDIFRX in mode Control Flow Reception */ - if(((itFlag & SPDIFRX_FLAG_CSRNE) == SPDIFRX_FLAG_CSRNE) && ((itSource & SPDIFRX_IT_CSRNE) == SPDIFRX_IT_CSRNE)) + if (((itFlag & SPDIFRX_FLAG_CSRNE) == SPDIFRX_FLAG_CSRNE) && ((itSource & SPDIFRX_IT_CSRNE) == SPDIFRX_IT_CSRNE)) { __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE); SPDIFRX_ReceiveControlFlow_IT(hspdif); } /* SPDIFRX Overrun error interrupt occurred */ - if(((itFlag & SPDIFRX_FLAG_OVR) == SPDIFRX_FLAG_OVR) && ((itSource & SPDIFRX_IT_OVRIE) == SPDIFRX_IT_OVRIE)) + if (((itFlag & SPDIFRX_FLAG_OVR) == SPDIFRX_FLAG_OVR) && ((itSource & SPDIFRX_IT_OVRIE) == SPDIFRX_IT_OVRIE)) { __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_OVRIE); @@ -1282,7 +1287,7 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif) } /* SPDIFRX Parity error interrupt occurred */ - if(((itFlag & SPDIFRX_FLAG_PERR) == SPDIFRX_FLAG_PERR) && ((itSource & SPDIFRX_IT_PERRIE) == SPDIFRX_IT_PERRIE)) + if (((itFlag & SPDIFRX_FLAG_PERR) == SPDIFRX_FLAG_PERR) && ((itSource & SPDIFRX_IT_PERRIE) == SPDIFRX_IT_PERRIE)) { __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_PERRIE); @@ -1393,7 +1398,7 @@ and the data flow. * @param hspdif SPDIFRX handle * @retval HAL state */ -HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * const hspdif) +HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif) { return hspdif->State; } @@ -1403,7 +1408,7 @@ HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * cons * @param hspdif SPDIFRX handle * @retval SPDIFRX Error Code */ -uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif) +uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif) { return hspdif->ErrorCode; } @@ -1419,10 +1424,10 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif) */ static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma) { - SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Rx DMA Request */ - if(hdma->Init.Mode != DMA_CIRCULAR) + if (hdma->Init.Mode != DMA_CIRCULAR) { hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN); hspdif->RxXferCount = 0; @@ -1442,7 +1447,7 @@ static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma) */ static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) hspdif->RxHalfCpltCallback(hspdif); @@ -1459,7 +1464,7 @@ static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma) */ static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma) { - SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Cb DMA Request */ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN); @@ -1480,7 +1485,7 @@ static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma) */ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma) { - SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) hspdif->CxHalfCpltCallback(hspdif); @@ -1496,13 +1501,13 @@ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma) */ static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma) { - SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Rx and Cb DMA Request */ hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN)); hspdif->RxXferCount = 0; - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Set the error code and execute error callback*/ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA; @@ -1528,7 +1533,7 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) hspdif->pRxBuffPtr++; hspdif->RxXferCount--; - if(hspdif->RxXferCount == 0U) + if (hspdif->RxXferCount == 0U) { /* Disable RXNE/PE and OVR interrupts */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE); @@ -1539,9 +1544,9 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) __HAL_UNLOCK(hspdif); #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - hspdif->RxCpltCallback(hspdif); + hspdif->RxCpltCallback(hspdif); #else - HAL_SPDIFRX_RxCpltCallback(hspdif); + HAL_SPDIFRX_RxCpltCallback(hspdif); #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ } } @@ -1558,7 +1563,7 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) hspdif->pCsBuffPtr++; hspdif->CsXferCount--; - if(hspdif->CsXferCount == 0U) + if (hspdif->CsXferCount == 0U) { /* Disable CSRNE interrupt */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); @@ -1569,9 +1574,9 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) __HAL_UNLOCK(hspdif); #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - hspdif->CxCpltCallback(hspdif); + hspdif->CxCpltCallback(hspdif); #else - HAL_SPDIFRX_CxCpltCallback(hspdif); + HAL_SPDIFRX_CxCpltCallback(hspdif); #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ } } @@ -1585,15 +1590,16 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) * @param tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart) +static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t tickstart) { /* Wait until flag is set */ - while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status) + while (__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); @@ -1604,7 +1610,7 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -1631,5 +1637,3 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c index 95f6c2502..1cbe0679b 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -34,7 +45,8 @@ (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream/Channel (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. @@ -113,18 +125,6 @@ Those functions are maintained for backward compatibility reasons. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -190,8 +190,8 @@ static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi); */ /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -234,11 +234,7 @@ static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi); */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { -#if (USE_SPI_CRC != 0UL) uint32_t crc_length; -#else - uint32_t crc_length = 0UL; -#endif uint32_t packet_length; /* Check the SPI handle allocation */ @@ -267,8 +263,8 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.TxCRCInitializationPattern)); assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.RxCRCInitializationPattern)); } @@ -355,13 +351,20 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); +#if (USE_SPI_CRC == 0) + /* Keep the default value of CRCSIZE in case of CRC is not used */ + crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE; +#endif /* USE_SPI_CRC */ + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, Communication speed, First bit, CRC calculation state, CRC Length */ /* SPIx NSS Software Management Configuration */ - if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \ - ((hspi->Init.Mode == SPI_MODE_SLAVE) && (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH)))) + if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && \ + (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \ + ((hspi->Init.Mode == SPI_MODE_SLAVE) && \ + (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH)))) { SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI); } @@ -371,10 +374,12 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) hspi->Init.FifoThreshold | hspi->Init.DataSize)); /* SPIx CFG2 Configuration */ - WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode | hspi->Init.NSSPolarity | - hspi->Init.NSS | hspi->Init.CLKPolarity | hspi->Init.CLKPhase | - hspi->Init.FirstBit | hspi->Init.Mode | hspi->Init.MasterInterDataIdleness | - hspi->Init.Direction | hspi->Init.MasterSSIdleness | hspi->Init.IOSwap)); + WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode | + hspi->Init.NSSPolarity | hspi->Init.NSS | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | + hspi->Init.FirstBit | hspi->Init.Mode | + hspi->Init.MasterInterDataIdleness | hspi->Init.Direction | + hspi->Init.MasterSSIdleness | hspi->Init.IOSwap)); #if (USE_SPI_CRC != 0UL) /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ @@ -423,7 +428,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /* Set Default Underrun configuration */ #if (USE_SPI_CRC != 0UL) if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_DISABLE) -#endif +#endif /* USE_SPI_CRC */ { MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, SPI_CFG1_UDRDET_0); } @@ -534,7 +539,8 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -545,7 +551,7 @@ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Call return HAL_ERROR; } - /* Process locked */ + /* Lock the process */ __HAL_LOCK(hspi); if (HAL_SPI_STATE_READY == hspi->State) @@ -648,7 +654,7 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ + /* Lock the process */ __HAL_LOCK(hspi); if (HAL_SPI_STATE_READY == hspi->State) @@ -744,8 +750,8 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca */ /** @defgroup SPI_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim ============================================================================== ##### IO operation functions ##### @@ -797,7 +803,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); - /* Process Locked */ + /* Lock the process */ __HAL_LOCK(hspi); /* Init tickstart for timeout management*/ @@ -870,12 +876,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); hspi->State = HAL_SPI_STATE_READY; - return HAL_ERROR; + return HAL_TIMEOUT; } } } @@ -914,12 +920,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); hspi->State = HAL_SPI_STATE_READY; - return HAL_ERROR; + return HAL_TIMEOUT; } } } @@ -963,12 +969,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); hspi->State = HAL_SPI_STATE_READY; - return HAL_ERROR; + return HAL_TIMEOUT; } } } @@ -983,7 +989,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); hspi->State = HAL_SPI_STATE_READY; @@ -1022,7 +1028,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); } - /* Process Locked */ + /* Lock the process */ __HAL_LOCK(hspi); /* Init tickstart for timeout management*/ @@ -1095,12 +1101,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); hspi->State = HAL_SPI_STATE_READY; - return HAL_ERROR; + return HAL_TIMEOUT; } } } @@ -1111,25 +1117,16 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { - /* Check the RXWNE/FRLVL flag */ - if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { - if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount -= (uint16_t)2UL; - } - else - { #if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; #else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); #endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - } + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; } else { @@ -1139,12 +1136,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); hspi->State = HAL_SPI_STATE_READY; - return HAL_ERROR; + return HAL_TIMEOUT; } } } @@ -1155,31 +1152,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Transfer loop */ while (hspi->RxXferCount > 0UL) { - /* Check the RXWNE/FRLVL flag */ - if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) { - if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount -= (uint16_t)4UL; - } - else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET) - { -#if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; -#else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); -#endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount -= (uint16_t)2UL; - } - else - { - *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - hspi->RxXferCount--; - } + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; } else { @@ -1189,12 +1167,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); hspi->State = HAL_SPI_STATE_READY; - return HAL_ERROR; + return HAL_TIMEOUT; } } } @@ -1214,7 +1192,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); hspi->State = HAL_SPI_STATE_READY; @@ -1254,7 +1232,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process Locked */ + /* Lock the process */ __HAL_LOCK(hspi); /* Init tickstart for timeout management*/ @@ -1266,7 +1244,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && \ + (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \ + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { errorcode = HAL_BUSY; __HAL_UNLOCK(hspi); @@ -1339,12 +1319,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); hspi->State = HAL_SPI_STATE_READY; - return HAL_ERROR; + return HAL_TIMEOUT; } } } @@ -1353,50 +1333,30 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) { - /* Check TXP flag */ + /* Check the TXP flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP) && (initial_TxXferCount > 0UL)) { - if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount -= (uint16_t)2UL; - initial_TxXferCount = hspi->TxXferCount; - } - else - { #if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); + *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); #else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); #endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - initial_TxXferCount = hspi->TxXferCount; - } + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + initial_TxXferCount = hspi->TxXferCount; } - /* Check RXWNE/FRLVL flag */ - if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL)) + /* Check the RXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) { - if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount -= (uint16_t)2UL; - initial_RxXferCount = hspi->RxXferCount; - } - else - { #if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; #else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); #endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; } /* Timeout management */ @@ -1405,12 +1365,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); hspi->State = HAL_SPI_STATE_READY; - return HAL_ERROR; + return HAL_TIMEOUT; } } } @@ -1419,64 +1379,22 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) { - /* check TXP flag */ + /* Check the TXP flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL)) { - if ((initial_TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount -= (uint16_t)4UL; - initial_TxXferCount = hspi->TxXferCount; - } - else if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) - { -#if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); -#else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); -#endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= (uint16_t)2UL; - initial_TxXferCount = hspi->TxXferCount; - } - else - { - *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint8_t); - hspi->TxXferCount--; - initial_TxXferCount = hspi->TxXferCount; - } + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + initial_TxXferCount = hspi->TxXferCount; } - /* Wait until RXWNE/FRLVL flag is reset */ - if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL)) + /* Check the RXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) { - if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount -= (uint16_t)4UL; - initial_RxXferCount = hspi->RxXferCount; - } - else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET) - { -#if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; -#else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); -#endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount -= (uint16_t)2UL; - initial_RxXferCount = hspi->RxXferCount; - } - else - { - *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; } /* Timeout management */ @@ -1485,12 +1403,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); hspi->State = HAL_SPI_STATE_READY; - return HAL_ERROR; + return HAL_TIMEOUT; } } } @@ -1504,7 +1422,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); hspi->State = HAL_SPI_STATE_READY; @@ -1531,7 +1449,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); - /* Process Locked */ + /* Lock the process */ __HAL_LOCK(hspi); if ((pData == NULL) || (Size == 0UL)) @@ -1622,7 +1540,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); } - /* Process Locked */ + /* Lock the process */ __HAL_LOCK(hspi); if (hspi->State != HAL_SPI_STATE_READY) @@ -1691,7 +1609,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); } - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); return errorcode; } @@ -1711,15 +1629,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p HAL_StatusTypeDef errorcode = HAL_OK; uint32_t max_fifo_length = 0UL; uint32_t tmp_TxXferCount; - #if defined (__GNUC__) + +#if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); - #endif /* __GNUC__ */ +#endif /* __GNUC__ */ + uint32_t tmp_mode; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ + /* Lock the process */ __HAL_LOCK(hspi); /* Init temporary variables */ @@ -1727,7 +1647,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && \ + (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \ + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { errorcode = HAL_BUSY; __HAL_UNLOCK(hspi); @@ -1755,7 +1677,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferSize = Size; hspi->RxXferCount = Size; - tmp_TxXferCount = hspi->TxXferCount; + tmp_TxXferCount = hspi->TxXferCount; /* Set the function for IT treatment */ if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) @@ -1856,15 +1778,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p } /* Enable EOT, DXP, UDR, OVR, FRE, MODF and TSERF interrupts */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF)); + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | + SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF)); if (hspi->Init.Mode == SPI_MODE_MASTER) { - /* Master transfer start */ + /* Start Master transfer */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); } - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); return errorcode; } @@ -1933,7 +1856,7 @@ HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *p __HAL_UNLOCK(hspi); return errorcode; } -#endif /* USE_HSPI_RELOAD_TRANSFER */ +#endif /* USE_SPI_RELOAD_TRANSFER */ #if defined(USE_SPI_RELOAD_TRANSFER) /** @@ -1999,7 +1922,7 @@ HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pD __HAL_UNLOCK(hspi); return errorcode; } -#endif /* USE_HSPI_RELOAD_TRANSFER */ +#endif /* USE_SPI_RELOAD_TRANSFER */ #if defined(USE_SPI_RELOAD_TRANSFER) /** @@ -2068,7 +1991,7 @@ HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uin __HAL_UNLOCK(hspi); return errorcode; } -#endif /* USE_HSPI_RELOAD_TRANSFER */ +#endif /* USE_SPI_RELOAD_TRANSFER */ /** * @brief Transmit an amount of data in non-blocking mode with DMA. @@ -2085,7 +2008,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); - /* Process Locked */ + /* Lock the process */ __HAL_LOCK(hspi); if (hspi->State != HAL_SPI_STATE_READY) @@ -2173,12 +2096,17 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); /* Enable the Tx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount)) + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, + hspi->TxXferCount)) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + hspi->State = HAL_SPI_STATE_READY; + errorcode = HAL_ERROR; return errorcode; } @@ -2207,7 +2135,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); } - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); return errorcode; } @@ -2235,7 +2163,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); } - /* Process Locked */ + /* Lock the process */ __HAL_LOCK(hspi); if (hspi->State != HAL_SPI_STATE_READY) @@ -2322,12 +2250,17 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u hspi->hdmarx->XferAbortCallback = NULL; /* Enable the Rx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount)) + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + hspi->State = HAL_SPI_STATE_READY; + errorcode = HAL_ERROR; return errorcode; } @@ -2356,7 +2289,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); } - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); return errorcode; } @@ -2382,14 +2315,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ + /* Lock the process */ __HAL_LOCK(hspi); /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; - if (!(((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)) || (tmp_state == HAL_SPI_STATE_READY))) + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && \ + (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \ + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { errorcode = HAL_BUSY; __HAL_UNLOCK(hspi); @@ -2432,7 +2368,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Restriction the DMA data received is not allowed in this mode */ errorcode = HAL_ERROR; - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); return errorcode; } @@ -2494,12 +2430,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->hdmarx->XferAbortCallback = NULL; /* Enable the Rx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount)) + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + hspi->State = HAL_SPI_STATE_READY; + errorcode = HAL_ERROR; return errorcode; } @@ -2514,12 +2455,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->hdmatx->XferAbortCallback = NULL; /* Enable the Tx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount)) + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, + hspi->TxXferCount)) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + hspi->State = HAL_SPI_STATE_READY; + errorcode = HAL_ERROR; return errorcode; } @@ -2547,7 +2493,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); } - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); return errorcode; } @@ -2564,14 +2510,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * * + Set handle State to READY. * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode; __IO uint32_t count; - /* Process locked */ + /* Lock the process */ __HAL_LOCK(hspi); /* Set hspi->state to aborting to avoid any interaction */ @@ -2650,7 +2596,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) hspi->ErrorCode = HAL_SPI_ERROR_NONE; } - /* Process Unlocked */ + /* Unlock the process */ __HAL_UNLOCK(hspi); /* Restore hspi->state to ready */ @@ -2673,12 +2619,13 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode; __IO uint32_t count; - uint32_t dma_tx_abort_done = 1UL, dma_rx_abort_done = 1UL; + uint32_t dma_tx_abort_done = 1UL; + uint32_t dma_rx_abort_done = 1UL; /* Set hspi->state to aborting to avoid any interaction */ hspi->State = HAL_SPI_STATE_ABORT; @@ -2706,7 +2653,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized before any call to DMA Abort functions */ - if(hspi->hdmatx != NULL) + if (hspi->hdmatx != NULL) { if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) { @@ -2731,7 +2678,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) } } - if(hspi->hdmarx != NULL) + if (hspi->hdmarx != NULL) { if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) { @@ -2854,7 +2801,8 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) /* SPI in mode Transmitter and Receiver ------------------------------------*/ - if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP)) + if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \ + HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP)) { hspi->TxISR(hspi); hspi->RxISR(hspi); @@ -2862,14 +2810,16 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) } /* SPI in mode Receiver ----------------------------------------------------*/ - if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP)) + if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && \ + HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP)) { hspi->RxISR(hspi); handled = 1UL; } /* SPI in mode Transmitter -------------------------------------------------*/ - if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP)) + if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && \ + HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP)) { hspi->TxISR(hspi); handled = 1UL; @@ -2882,7 +2832,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) hspi->Reload.Requested = 0UL; __HAL_SPI_CLEAR_TSERFFLAG(hspi); } -#endif /* USE_HSPI_RELOAD_TRANSFER */ +#endif /* USE_SPI_RELOAD_TRANSFER */ if (handled != 0UL) { @@ -2900,57 +2850,51 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) /* Disable EOT interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); - /* DMA Normal Mode */ - if (HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN) || // IT based transfer is done - ((State != HAL_SPI_STATE_BUSY_RX) && (hspi->hdmatx->Init.Mode == DMA_NORMAL)) || // DMA is used in normal mode - ((State != HAL_SPI_STATE_BUSY_TX) && (hspi->hdmarx->Init.Mode == DMA_NORMAL))) // DMA is used in normal mode + /* For the IT based receive extra polling maybe required for last packet */ + if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) { - /* For the IT based receive extra polling maybe required for last packet */ - if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) + /* Pooling remaining data */ + while (hspi->RxXferCount != 0UL) { - /* Pooling remaining data */ - while (hspi->RxXferCount != 0UL) + /* Receive data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + } + /* Receive data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* Receive data in 32 Bit mode */ - if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - } - /* Receive data in 16 Bit mode */ - else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { #if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; #else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); #endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - } - /* Receive data in 8 Bit mode */ - else - { - *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - } - - hspi->RxXferCount--; + hspi->pRxBuffPtr += sizeof(uint16_t); + } + /* Receive data in 8 Bit mode */ + else + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); } + + hspi->RxXferCount--; } + } - /* Call SPI Standard close procedure */ - SPI_CloseTransfer(hspi); + /* Call SPI Standard close procedure */ + SPI_CloseTransfer(hspi); - hspi->State = HAL_SPI_STATE_READY; - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { + hspi->State = HAL_SPI_STATE_READY; + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - hspi->ErrorCallback(hspi); + hspi->ErrorCallback(hspi); #else - HAL_SPI_ErrorCallback(hspi); + HAL_SPI_ErrorCallback(hspi); #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - return; - } + return; } #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) @@ -2982,7 +2926,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) HAL_SPI_TxCpltCallback(hspi); } #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - else + else { /* End of the appropriate call */ } @@ -3035,7 +2979,8 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Disable all interrupts */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_MODF | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR); + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_MODF | + SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR)); /* Disable the SPI DMA requests if enabled */ if (HAL_IS_BIT_SET(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) @@ -3558,7 +3503,7 @@ static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi) #else /* Disable RXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); -#endif /* USE_HSPI_RELOAD_TRANSFER */ +#endif /* USE_SPI_RELOAD_TRANSFER */ } } @@ -3601,7 +3546,7 @@ static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi) #else /* Disable RXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); -#endif /* USE_HSPI_RELOAD_TRANSFER */ +#endif /* USE_SPI_RELOAD_TRANSFER */ } } @@ -3638,7 +3583,7 @@ static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi) #else /* Disable RXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); -#endif /* USE_HSPI_RELOAD_TRANSFER */ +#endif /* USE_SPI_RELOAD_TRANSFER */ } } @@ -3675,7 +3620,7 @@ static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi) #else /* Disable TXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); -#endif /* USE_HSPI_RELOAD_TRANSFER */ +#endif /* USE_SPI_RELOAD_TRANSFER */ } } @@ -3717,7 +3662,7 @@ static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi) #else /* Disable TXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); -#endif /* USE_HSPI_RELOAD_TRANSFER */ +#endif /* USE_SPI_RELOAD_TRANSFER */ } } @@ -3753,7 +3698,7 @@ static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi) #else /* Disable TXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); -#endif /* USE_HSPI_RELOAD_TRANSFER */ +#endif /* USE_SPI_RELOAD_TRANSFER */ } } @@ -3769,7 +3714,8 @@ static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Disable ITs */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \ + SPI_IT_FRE | SPI_IT_MODF)); /* Clear the Status flags in the SR register */ __HAL_SPI_CLEAR_EOTFLAG(hspi); @@ -3799,7 +3745,7 @@ static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi) * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL_ERROR: if any error detected -* HAL_OK: if nothing detected + * HAL_OK: if nothing detected */ static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi) { @@ -3812,7 +3758,8 @@ static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Disable ITs */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \ + SPI_IT_FRE | SPI_IT_MODF)); /* Disable Tx DMA Request */ CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); @@ -3909,7 +3856,6 @@ static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi) return data_size * fifo_threashold; } - /** * @} */ @@ -3923,5 +3869,3 @@ static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c index ade9c6473..963b85b7b 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c @@ -11,13 +11,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -160,7 +159,8 @@ HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi) * This parameter can be a value of @ref SPI_Underrun_Behaviour. * @retval None */ -HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour) +HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, + uint32_t UnderrunBehaviour) { HAL_StatusTypeDef errorcode = HAL_OK; @@ -225,5 +225,3 @@ HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c index daf8e3f96..8e1bbddcb 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c @@ -6,6 +6,17 @@ * This file provides a generic firmware to drive SRAM memories * mounted as external device. * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -64,25 +75,25 @@ The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback, + Use Functions HAL_SRAM_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) MspInitCallback : SRAM MspInit. (+) MspDeInitCallback : SRAM MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default + Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) MspInitCallback : SRAM MspInit. (+) MspDeInitCallback : SRAM MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET + By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init - and @ref HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit + reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init + and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -90,8 +101,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit - or @ref HAL_SRAM_Init function. + using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit + or HAL_SRAM_Init function. When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -99,17 +110,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1109,5 +1109,3 @@ static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma) * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_swpmi.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_swpmi.c index 839af3ba1..0cf0c1c42 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_swpmi.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_swpmi.c @@ -9,6 +9,17 @@ * + Data transfers functions * + DMA transfers management * + Interrupts and flags management + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -146,7 +157,7 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using HAL_SWPMI_RegisterCallback before calling @ref HAL_SWPMI_DeInit + using HAL_SWPMI_RegisterCallback before calling HAL_SWPMI_DeInit or HAL_SWPMI_Init function. [..] When the compilation define USE_HAL_SWPMI_REGISTER_CALLBACKS is set to 0 or @@ -154,18 +165,6 @@ and weak (surcharged) callbacks are used. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -243,7 +242,7 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) uint32_t tickstart = HAL_GetTick(); /* Check the SWPMI handle allocation */ - if(hswpmi == NULL) + if (hswpmi == NULL) { status = HAL_ERROR; } @@ -255,7 +254,7 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) assert_param(IS_SWPMI_TX_BUFFERING_MODE(hswpmi->Init.TxBufferingMode)); assert_param(IS_SWPMI_RX_BUFFERING_MODE(hswpmi->Init.RxBufferingMode)); - if(hswpmi->State == HAL_SWPMI_STATE_RESET) + if (hswpmi->State == HAL_SWPMI_STATE_RESET) { /* Allocate lock resource and initialize it */ hswpmi->Lock = HAL_UNLOCKED; @@ -269,7 +268,7 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback; /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - if(hswpmi->MspInitCallback == NULL) + if (hswpmi->MspInitCallback == NULL) { hswpmi->MspInitCallback = HAL_SWPMI_MspInit; } @@ -303,12 +302,12 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) /* Enable the SWPMI transceiver */ SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPEN); /* Wait on RDYF flag to activate SWPMI */ - if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_RDYF, tickstart, SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE) != HAL_OK) + if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_RDYF, tickstart, SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE) != HAL_OK) { status = HAL_TIMEOUT; } - if(status == HAL_OK) + if (status == HAL_OK) { hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; hswpmi->State = HAL_SWPMI_STATE_READY; @@ -336,7 +335,7 @@ HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi) HAL_StatusTypeDef status = HAL_OK; /* Check the SWPMI handle allocation */ - if(hswpmi == NULL) + if (hswpmi == NULL) { status = HAL_ERROR; } @@ -359,7 +358,7 @@ HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi) /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) - if(hswpmi->MspDeInitCallback == NULL) + if (hswpmi->MspDeInitCallback == NULL) { hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit; } @@ -426,12 +425,12 @@ __weak void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi) * @retval HAL status. */ HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi, - HAL_SWPMI_CallbackIDTypeDef CallbackID, - pSWPMI_CallbackTypeDef pCallback) + HAL_SWPMI_CallbackIDTypeDef CallbackID, + pSWPMI_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* update the error code */ hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; @@ -440,55 +439,55 @@ HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi, } else { - if(hswpmi->State == HAL_SWPMI_STATE_READY) + if (hswpmi->State == HAL_SWPMI_STATE_READY) { switch (CallbackID) { - case HAL_SWPMI_RX_COMPLETE_CB_ID : - hswpmi->RxCpltCallback = pCallback; - break; - case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID : - hswpmi->RxHalfCpltCallback = pCallback; - break; - case HAL_SWPMI_TX_COMPLETE_CB_ID : - hswpmi->TxCpltCallback = pCallback; - break; - case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID : - hswpmi->TxHalfCpltCallback = pCallback; - break; - case HAL_SWPMI_ERROR_CB_ID : - hswpmi->ErrorCallback = pCallback; - break; - case HAL_SWPMI_MSPINIT_CB_ID : - hswpmi->MspInitCallback = pCallback; - break; - case HAL_SWPMI_MSPDEINIT_CB_ID : - hswpmi->MspDeInitCallback = pCallback; - break; - default : - /* update the error code */ - hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SWPMI_RX_COMPLETE_CB_ID : + hswpmi->RxCpltCallback = pCallback; + break; + case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID : + hswpmi->RxHalfCpltCallback = pCallback; + break; + case HAL_SWPMI_TX_COMPLETE_CB_ID : + hswpmi->TxCpltCallback = pCallback; + break; + case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID : + hswpmi->TxHalfCpltCallback = pCallback; + break; + case HAL_SWPMI_ERROR_CB_ID : + hswpmi->ErrorCallback = pCallback; + break; + case HAL_SWPMI_MSPINIT_CB_ID : + hswpmi->MspInitCallback = pCallback; + break; + case HAL_SWPMI_MSPDEINIT_CB_ID : + hswpmi->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hswpmi->State == HAL_SWPMI_STATE_RESET) + else if (hswpmi->State == HAL_SWPMI_STATE_RESET) { switch (CallbackID) { - case HAL_SWPMI_MSPINIT_CB_ID : - hswpmi->MspInitCallback = pCallback; - break; - case HAL_SWPMI_MSPDEINIT_CB_ID : - hswpmi->MspDeInitCallback = pCallback; - break; - default : - /* update the error code */ - hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SWPMI_MSPINIT_CB_ID : + hswpmi->MspInitCallback = pCallback; + break; + case HAL_SWPMI_MSPDEINIT_CB_ID : + hswpmi->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -518,59 +517,59 @@ HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi, * @retval HAL status. */ HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef *hswpmi, - HAL_SWPMI_CallbackIDTypeDef CallbackID) + HAL_SWPMI_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; - if(hswpmi->State == HAL_SWPMI_STATE_READY) + if (hswpmi->State == HAL_SWPMI_STATE_READY) { switch (CallbackID) { - case HAL_SWPMI_RX_COMPLETE_CB_ID : - hswpmi->RxCpltCallback = HAL_SWPMI_RxCpltCallback; - break; - case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID : - hswpmi->RxHalfCpltCallback = HAL_SWPMI_RxHalfCpltCallback; - break; - case HAL_SWPMI_TX_COMPLETE_CB_ID : - hswpmi->TxCpltCallback = HAL_SWPMI_TxCpltCallback; - break; - case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID : - hswpmi->TxHalfCpltCallback = HAL_SWPMI_TxHalfCpltCallback; - break; - case HAL_SWPMI_ERROR_CB_ID : - hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback; - break; - case HAL_SWPMI_MSPINIT_CB_ID : - hswpmi->MspInitCallback = HAL_SWPMI_MspInit; - break; - case HAL_SWPMI_MSPDEINIT_CB_ID : - hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit; - break; - default : - /* update the error code */ - hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SWPMI_RX_COMPLETE_CB_ID : + hswpmi->RxCpltCallback = HAL_SWPMI_RxCpltCallback; + break; + case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID : + hswpmi->RxHalfCpltCallback = HAL_SWPMI_RxHalfCpltCallback; + break; + case HAL_SWPMI_TX_COMPLETE_CB_ID : + hswpmi->TxCpltCallback = HAL_SWPMI_TxCpltCallback; + break; + case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID : + hswpmi->TxHalfCpltCallback = HAL_SWPMI_TxHalfCpltCallback; + break; + case HAL_SWPMI_ERROR_CB_ID : + hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback; + break; + case HAL_SWPMI_MSPINIT_CB_ID : + hswpmi->MspInitCallback = HAL_SWPMI_MspInit; + break; + case HAL_SWPMI_MSPDEINIT_CB_ID : + hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit; + break; + default : + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hswpmi->State == HAL_SWPMI_STATE_RESET) + else if (hswpmi->State == HAL_SWPMI_STATE_RESET) { switch (CallbackID) { - case HAL_SWPMI_MSPINIT_CB_ID : - hswpmi->MspInitCallback = HAL_SWPMI_MspInit; - break; - case HAL_SWPMI_MSPDEINIT_CB_ID : - hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit; - break; - default : - /* update the error code */ - hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SWPMI_MSPINIT_CB_ID : + hswpmi->MspInitCallback = HAL_SWPMI_MspInit; + break; + case HAL_SWPMI_MSPDEINIT_CB_ID : + hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit; + break; + default : + /* update the error code */ + hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -652,7 +651,7 @@ HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef *hswpm * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); HAL_StatusTypeDef status = HAL_OK; @@ -660,7 +659,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat uint32_t *ptmp_data; uint32_t tmp_size; - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { status = HAL_ERROR; } @@ -670,10 +669,10 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat __HAL_LOCK(hswpmi); tmp_state = hswpmi->State; - if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX)) + if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX)) { /* Check if a non-blocking receive process is ongoing or not */ - if(tmp_state == HAL_SWPMI_STATE_READY) + if (tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_TX; @@ -696,7 +695,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat do { /* Wait the TXE to write data */ - if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_TXE)) + if (HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_TXE)) { hswpmi->Instance->TDR = *ptmp_data; ptmp_data++; @@ -705,19 +704,20 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat else { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { status = HAL_TIMEOUT; break; } } } - } while(tmp_size != 0U); + } + while (tmp_size != 0U); /* Wait on TXBEF flag to be able to start a second transfer */ - if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK) + if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK) { /* Timeout occurred */ hswpmi->ErrorCode |= HAL_SWPMI_ERROR_TXBEF_TIMEOUT; @@ -725,10 +725,10 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat status = HAL_TIMEOUT; } - if(status == HAL_OK) + if (status == HAL_OK) { /* Check if a non-blocking receive Process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX) + if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX) { hswpmi->State = HAL_SWPMI_STATE_BUSY_RX; } @@ -744,7 +744,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat } } - if((status != HAL_OK) && (status != HAL_BUSY)) + if ((status != HAL_OK) && (status != HAL_BUSY)) { hswpmi->State = HAL_SWPMI_STATE_READY; } @@ -771,7 +771,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData uint32_t *ptmp_data; uint32_t tmp_size; - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { status = HAL_ERROR; } @@ -781,10 +781,10 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData __HAL_LOCK(hswpmi); tmp_state = hswpmi->State; - if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX)) + if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX)) { /* Check if a non-blocking transmit process is ongoing or not */ - if(tmp_state == HAL_SWPMI_STATE_READY) + if (tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_RX; @@ -804,7 +804,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData do { /* Wait the RXNE to read data */ - if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXNE)) + if (HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXNE)) { *ptmp_data = hswpmi->Instance->RDR; ptmp_data++; @@ -813,27 +813,28 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData else { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { status = HAL_TIMEOUT; break; } } } - } while(tmp_size != 0U); + } + while (tmp_size != 0U); - if(status == HAL_OK) + if (status == HAL_OK) { - if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXBFF)) + if (HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXBFF)) { /* Clear RXBFF at end of reception */ WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF); } /* Check if a non-blocking transmit Process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX) + if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX) { hswpmi->State = HAL_SWPMI_STATE_BUSY_TX; } @@ -849,7 +850,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData } } - if((status != HAL_OK) && (status != HAL_BUSY)) + if ((status != HAL_OK) && (status != HAL_BUSY)) { hswpmi->State = HAL_SWPMI_STATE_READY; } @@ -872,7 +873,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *p HAL_StatusTypeDef status = HAL_OK; HAL_SWPMI_StateTypeDef tmp_state; - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { status = HAL_ERROR; } @@ -882,7 +883,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *p __HAL_LOCK(hswpmi); tmp_state = hswpmi->State; - if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX)) + if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX)) { /* Update handle */ hswpmi->pTxBuffPtr = pData; @@ -891,7 +892,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *p hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; /* Check if a receive process is ongoing or not */ - if(tmp_state == HAL_SWPMI_STATE_READY) + if (tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_TX; @@ -939,7 +940,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD HAL_StatusTypeDef status = HAL_OK; HAL_SWPMI_StateTypeDef tmp_state; - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { status = HAL_ERROR; } @@ -949,7 +950,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD __HAL_LOCK(hswpmi); tmp_state = hswpmi->State; - if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX)) + if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX)) { /* Update handle */ hswpmi->pRxBuffPtr = pData; @@ -958,7 +959,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; /* Check if a transmit process is ongoing or not */ - if(tmp_state == HAL_SWPMI_STATE_READY) + if (tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_RX; @@ -1002,7 +1003,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * HAL_StatusTypeDef status = HAL_OK; HAL_SWPMI_StateTypeDef tmp_state; - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { status = HAL_ERROR; } @@ -1012,7 +1013,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * __HAL_LOCK(hswpmi); tmp_state = hswpmi->State; - if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX)) + if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX)) { /* Update handle */ hswpmi->pTxBuffPtr = pData; @@ -1021,7 +1022,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; /* Check if a receive process is ongoing or not */ - if(tmp_state == HAL_SWPMI_STATE_READY) + if (tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_TX; @@ -1043,7 +1044,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t * hswpmi->hdmatx->XferErrorCallback = SWPMI_DMAError; /* Enable the SWPMI transmit DMA stream */ - if(HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK) { hswpmi->State = tmp_state; /* Back to previous state */ hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA; @@ -1089,7 +1090,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p HAL_StatusTypeDef status = HAL_OK; HAL_SWPMI_StateTypeDef tmp_state; - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { status = HAL_ERROR; } @@ -1099,7 +1100,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p __HAL_LOCK(hswpmi); tmp_state = hswpmi->State; - if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX)) + if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX)) { /* Update handle */ hswpmi->pRxBuffPtr = pData; @@ -1107,7 +1108,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE; /* Check if a transmit process is ongoing or not */ - if(tmp_state == HAL_SWPMI_STATE_READY) + if (tmp_state == HAL_SWPMI_STATE_READY) { hswpmi->State = HAL_SWPMI_STATE_BUSY_RX; @@ -1129,7 +1130,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p hswpmi->hdmarx->XferErrorCallback = SWPMI_DMAError; /* Enable the DMA request */ - if(HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK) { hswpmi->State = tmp_state; /* Back to previous state */ hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA; @@ -1179,18 +1180,18 @@ HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi) CLEAR_BIT(hswpmi->Instance->CR, (SWPMI_CR_TXDMA | SWPMI_CR_RXDMA)); /* Abort the SWPMI DMA tx stream */ - if(hswpmi->hdmatx != NULL) + if (hswpmi->hdmatx != NULL) { - if(HAL_DMA_Abort(hswpmi->hdmatx) != HAL_OK) + if (HAL_DMA_Abort(hswpmi->hdmatx) != HAL_OK) { hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA; status = HAL_ERROR; } } /* Abort the SWPMI DMA rx stream */ - if(hswpmi->hdmarx != NULL) + if (hswpmi->hdmarx != NULL) { - if(HAL_DMA_Abort(hswpmi->hdmarx) != HAL_OK) + if (HAL_DMA_Abort(hswpmi->hdmarx) != HAL_OK) { hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA; status = HAL_ERROR; @@ -1295,7 +1296,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) uint32_t errcode = HAL_SWPMI_ERROR_NONE; /* SWPMI CRC error interrupt occurred --------------------------------------*/ - if(((regisr & SWPMI_FLAG_RXBERF) != 0U) && ((regier & SWPMI_IT_RXBERIE) != 0U)) + if (((regisr & SWPMI_FLAG_RXBERF) != 0U) && ((regier & SWPMI_IT_RXBERIE) != 0U)) { /* Disable Receive CRC interrupt */ CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXBERIE | SWPMI_IT_RXBFIE); @@ -1306,7 +1307,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) } /* SWPMI Over-Run interrupt occurred -----------------------------------------*/ - if(((regisr & SWPMI_FLAG_RXOVRF) != 0U) && ((regier & SWPMI_IT_RXOVRIE) != 0U)) + if (((regisr & SWPMI_FLAG_RXOVRF) != 0U) && ((regier & SWPMI_IT_RXOVRIE) != 0U)) { /* Disable Receive overrun interrupt */ CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXOVRIE); @@ -1317,7 +1318,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) } /* SWPMI Under-Run interrupt occurred -----------------------------------------*/ - if(((regisr & SWPMI_FLAG_TXUNRF) != 0U) && ((regier & SWPMI_IT_TXUNRIE) != 0U)) + if (((regisr & SWPMI_FLAG_TXUNRF) != 0U) && ((regier & SWPMI_IT_TXUNRIE) != 0U)) { /* Disable Transmit under run interrupt */ CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TXUNRIE); @@ -1327,27 +1328,27 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) errcode |= HAL_SWPMI_ERROR_UDR; } - /* Call SWPMI Error Call back function if needed --------------------------*/ - if(errcode != HAL_SWPMI_ERROR_NONE) + /* Call SWPMI Error Call back function if needed --------------------------*/ + if (errcode != HAL_SWPMI_ERROR_NONE) { hswpmi->ErrorCode |= errcode; - if((errcode & HAL_SWPMI_ERROR_UDR) != 0U) + if ((errcode & HAL_SWPMI_ERROR_UDR) != 0U) { /* Check TXDMA transfer to abort */ - if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_TXDMA)) + if (HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_TXDMA)) { /* Disable DMA TX at SWPMI level */ CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA); /* Abort the USART DMA Tx stream */ - if(hswpmi->hdmatx != NULL) + if (hswpmi->hdmatx != NULL) { /* Set the SWPMI Tx DMA Abort callback : will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */ hswpmi->hdmatx->XferAbortCallback = SWPMI_DMAAbortOnError; /* Abort DMA TX */ - if(HAL_DMA_Abort_IT(hswpmi->hdmatx) != HAL_OK) + if (HAL_DMA_Abort_IT(hswpmi->hdmatx) != HAL_OK) { /* Call Directly hswpmi->hdmatx->XferAbortCallback function in case of error */ hswpmi->hdmatx->XferAbortCallback(hswpmi->hdmatx); @@ -1380,19 +1381,19 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) else { /* Check RXDMA transfer to abort */ - if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_RXDMA)) + if (HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_RXDMA)) { /* Disable DMA RX at SWPMI level */ CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA); /* Abort the USART DMA Rx stream */ - if(hswpmi->hdmarx != NULL) + if (hswpmi->hdmarx != NULL) { /* Set the SWPMI Rx DMA Abort callback : will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */ hswpmi->hdmarx->XferAbortCallback = SWPMI_DMAAbortOnError; /* Abort DMA RX */ - if(HAL_DMA_Abort_IT(hswpmi->hdmarx) != HAL_OK) + if (HAL_DMA_Abort_IT(hswpmi->hdmarx) != HAL_OK) { /* Call Directly hswpmi->hdmarx->XferAbortCallback function in case of error */ hswpmi->hdmarx->XferAbortCallback(hswpmi->hdmarx); @@ -1425,31 +1426,31 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi) } /* SWPMI in mode Receiver ---------------------------------------------------*/ - if(((regisr & SWPMI_FLAG_RXNE) != 0U) && ((regier & SWPMI_IT_RIE) != 0U)) + if (((regisr & SWPMI_FLAG_RXNE) != 0U) && ((regier & SWPMI_IT_RIE) != 0U)) { SWPMI_Receive_IT(hswpmi); } /* SWPMI in mode Transmitter ------------------------------------------------*/ - if(((regisr & SWPMI_FLAG_TXE) != 0U) && ((regier & SWPMI_IT_TIE) != 0U)) + if (((regisr & SWPMI_FLAG_TXE) != 0U) && ((regier & SWPMI_IT_TIE) != 0U)) { SWPMI_Transmit_IT(hswpmi); } /* SWPMI in mode Transmitter (Transmit buffer empty) ------------------------*/ - if(((regisr & SWPMI_FLAG_TXBEF) != 0U) && ((regier & SWPMI_IT_TXBEIE) != 0U)) + if (((regisr & SWPMI_FLAG_TXBEF) != 0U) && ((regier & SWPMI_IT_TXBEIE) != 0U)) { SWPMI_EndTransmit_IT(hswpmi); } /* SWPMI in mode Receiver (Receive buffer full) -----------------------------*/ - if(((regisr & SWPMI_FLAG_RXBFF) != 0U) && ((regier & SWPMI_IT_RXBFIE) != 0U)) + if (((regisr & SWPMI_FLAG_RXBFF) != 0U) && ((regier & SWPMI_IT_RXBFIE) != 0U)) { SWPMI_EndReceive_IT(hswpmi); } /* Both Transmission and reception complete ---------------------------------*/ - if(((regisr & SWPMI_FLAG_TCF) != 0U) && ((regier & SWPMI_IT_TCIE) != 0U)) + if (((regisr & SWPMI_FLAG_TCF) != 0U) && ((regier & SWPMI_IT_TCIE) != 0U)) { SWPMI_EndTransmitReceive_IT(hswpmi); } @@ -1597,14 +1598,14 @@ static void SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi) if ((tmp_state == HAL_SWPMI_STATE_BUSY_TX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX)) { - if(hswpmi->TxXferCount == 0U) + if (hswpmi->TxXferCount == 0U) { /* Disable the SWPMI TXE and Underrun Interrupts */ CLEAR_BIT(hswpmi->Instance->IER, (SWPMI_IT_TIE | SWPMI_IT_TXUNRIE)); } else { - hswpmi->Instance->TDR = (uint32_t)*hswpmi->pTxBuffPtr; + hswpmi->Instance->TDR = (uint32_t) * hswpmi->pTxBuffPtr; hswpmi->pTxBuffPtr++; hswpmi->TxXferCount--; } @@ -1628,7 +1629,7 @@ static void SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi) CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TIE | SWPMI_IT_TXUNRIE | SWPMI_IT_TXBEIE); /* Check if a receive Process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX) + if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX) { hswpmi->State = HAL_SWPMI_STATE_BUSY_RX; } @@ -1654,13 +1655,13 @@ static void SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi) { HAL_SWPMI_StateTypeDef tmp_state = hswpmi->State; - if((tmp_state == HAL_SWPMI_STATE_BUSY_RX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX)) + if ((tmp_state == HAL_SWPMI_STATE_BUSY_RX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX)) { *hswpmi->pRxBuffPtr = (uint32_t)(hswpmi->Instance->RDR); hswpmi->pRxBuffPtr++; --hswpmi->RxXferCount; - if(hswpmi->RxXferCount == 0U) + if (hswpmi->RxXferCount == 0U) { /* Wait for RXBFF flag to update state */ #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) @@ -1689,7 +1690,7 @@ static void SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi) CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE); /* Check if a transmit Process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX) + if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX) { hswpmi->State = HAL_SWPMI_STATE_BUSY_TX; } @@ -1712,11 +1713,11 @@ static void SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi) CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TCIE); /* Check if a receive Process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX) + if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX) { hswpmi->State = HAL_SWPMI_STATE_BUSY_RX; } - else if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX) + else if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX) { hswpmi->State = HAL_SWPMI_STATE_READY; } @@ -1733,11 +1734,11 @@ static void SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi) */ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; uint32_t tickstart; /* DMA Normal mode*/ - if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U) + if (((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U) { hswpmi->TxXferCount = 0U; @@ -1749,7 +1750,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) tickstart = HAL_GetTick(); /* Wait the TXBEF */ - if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK) + if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK) { /* Timeout occurred */ hswpmi->ErrorCode |= HAL_SWPMI_ERROR_TXBEF_TIMEOUT; @@ -1764,7 +1765,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { /* No Timeout */ /* Check if a receive process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX) + if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX) { hswpmi->State = HAL_SWPMI_STATE_BUSY_RX; } @@ -1798,7 +1799,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { - SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) hswpmi->TxHalfCpltCallback(hswpmi); @@ -1815,10 +1816,10 @@ static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) */ static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* DMA Normal mode*/ - if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U) + if (((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U) { hswpmi->RxXferCount = 0U; @@ -1827,7 +1828,7 @@ static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA); /* Check if a transmit Process is ongoing or not */ - if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX) + if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX) { hswpmi->State = HAL_SWPMI_STATE_BUSY_TX; } @@ -1850,7 +1851,7 @@ static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) hswpmi->RxHalfCpltCallback(hswpmi); @@ -1866,12 +1867,12 @@ static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) */ static void SWPMI_DMAError(DMA_HandleTypeDef *hdma) { - SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Update handle */ hswpmi->RxXferCount = 0U; hswpmi->TxXferCount = 0U; - hswpmi->State= HAL_SWPMI_STATE_READY; + hswpmi->State = HAL_SWPMI_STATE_READY; hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA; #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) @@ -1888,12 +1889,12 @@ static void SWPMI_DMAError(DMA_HandleTypeDef *hdma) */ static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Update handle */ hswpmi->RxXferCount = 0U; hswpmi->TxXferCount = 0U; - hswpmi->State= HAL_SWPMI_STATE_READY; + hswpmi->State = HAL_SWPMI_STATE_READY; #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) hswpmi->ErrorCallback(hswpmi); @@ -1905,7 +1906,7 @@ static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma) /** * @brief Handle SWPMI Communication Timeout. * @param hswpmi SWPMI handle - * @param Flag: specifies the SWPMI flag to check. + * @param Flag specifies the SWPMI flag to check. * @param Tickstart Tick start value * @param Timeout timeout duration. * @retval HAL status @@ -1915,7 +1916,7 @@ static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hs HAL_StatusTypeDef status = HAL_OK; /* Wait until flag is set */ - while(!(HAL_IS_BIT_SET(hswpmi->Instance->ISR, Flag))) + while (!(HAL_IS_BIT_SET(hswpmi->Instance->ISR, Flag))) { /* Check for the Timeout */ if ((((HAL_GetTick() - Tickstart) > Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) @@ -1945,5 +1946,3 @@ static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hs /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c index 5dc8d353d..a1edfa78c 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c @@ -29,6 +29,17 @@ * + Commutation Event configuration with Interruption and DMA * + TIM OCRef clear configuration * + TIM External Clock configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### TIMER Generic features ##### @@ -103,14 +114,14 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_TIM_RegisterCallback() to register a callback. - @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + Use Function HAL_TIM_RegisterCallback() to register a callback. + HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default + Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. [..] @@ -147,7 +158,7 @@ [..] By default, after the Init and when the state is HAL_TIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: - examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak @@ -161,7 +172,7 @@ all interrupt callbacks are set to the corresponding weak functions: in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + using HAL_TIM_RegisterCallback() before calling DeInit or Init function. [..] When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or @@ -170,17 +181,6 @@ all interrupt callbacks are set to the corresponding weak functions: @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -561,7 +561,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -881,6 +882,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -926,34 +928,38 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -969,6 +975,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1003,26 +1011,30 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1040,6 +1052,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -1078,7 +1091,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1099,7 +1113,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1120,7 +1135,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1140,7 +1156,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1151,34 +1168,38 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1194,6 +1215,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1232,26 +1255,30 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1522,7 +1549,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1566,34 +1595,38 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1609,6 +1642,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1643,26 +1678,30 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1680,6 +1719,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -1718,7 +1758,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1739,7 +1780,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1759,7 +1801,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1779,7 +1822,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1790,34 +1834,38 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } default: + status = HAL_ERROR; break; } - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1833,6 +1881,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1871,26 +1921,30 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -2150,7 +2204,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); @@ -2199,27 +2255,32 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + if (status == HAL_OK) { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -2235,6 +2296,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -2269,21 +2332,25 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + if (status == HAL_OK) + { + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -2301,7 +2368,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); @@ -2333,6 +2402,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel return HAL_ERROR; } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + switch (Channel) { case TIM_CHANNEL_1: @@ -2345,7 +2417,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2365,7 +2438,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2385,7 +2459,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2405,7 +2480,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2416,12 +2492,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { @@ -2437,7 +2511,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } /* Return function status */ - return HAL_OK; + return status; } /** @@ -2453,6 +2527,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); @@ -2495,18 +2571,22 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (status == HAL_OK) + { + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** * @} @@ -2692,8 +2772,8 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) * @brief Starts the TIM One Pulse signal generation. * @note Though OutputChannel parameter is deprecated and ignored by the function * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status @@ -2749,8 +2829,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu * @brief Stops the TIM One Pulse signal generation. * @note Though OutputChannel parameter is deprecated and ignored by the function * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status @@ -2792,8 +2872,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output * @brief Starts the TIM One Pulse signal generation in interrupt mode. * @note Though OutputChannel parameter is deprecated and ignored by the function * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status @@ -2855,8 +2935,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou * @brief Stops the TIM One Pulse signal generation in interrupt mode. * @note Though OutputChannel parameter is deprecated and ignored by the function * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status @@ -3559,7 +3639,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -3567,11 +3648,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); break; } @@ -3584,7 +3666,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -3592,15 +3675,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } - case TIM_CHANNEL_ALL: + default: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; @@ -3610,7 +3694,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -3624,27 +3709,27 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - default: + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + break; + } } /* Return function status */ @@ -3972,6 +4057,8 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); @@ -4043,12 +4130,13 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, } default: + status = HAL_ERROR; break; } __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -4066,6 +4154,8 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, */ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); @@ -4122,7 +4212,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* Set the IC3PSC value */ htim->Instance->CCMR2 |= sConfig->ICPrescaler; } - else + else if (Channel == TIM_CHANNEL_4) { /* TI4 Configuration */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); @@ -4138,10 +4228,14 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* Set the IC4PSC value */ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } + else + { + status = HAL_ERROR; + } __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -4163,6 +4257,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); @@ -4277,12 +4373,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, } default: + status = HAL_ERROR; break; } __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -4307,6 +4404,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel) { + HAL_StatusTypeDef status = HAL_OK; TIM_OC_InitTypeDef temp1; /* Check the parameters */ @@ -4337,6 +4435,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O TIM_OC1_SetConfig(htim->Instance, &temp1); break; } + case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); @@ -4344,60 +4443,67 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O TIM_OC2_SetConfig(htim->Instance, &temp1); break; } + default: + status = HAL_ERROR; break; } - switch (InputChannel) + if (status == HAL_OK) { - case TIM_CHANNEL_1: + switch (InputChannel) { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; - default: - break; + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + status = HAL_ERROR; + break; + } } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); - return HAL_OK; + return status; } else { @@ -4428,13 +4534,13 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_CCMR3 - * @arg TIM_DMABASE_CCR5 - * @arg TIM_DMABASE_CCR6 - * @arg TIM_DMABASE_AF1 - * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 * @arg TIM_DMABASE_TISEL - * + * * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source @@ -4453,8 +4559,14 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { - return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + + return status; } /** @@ -4480,13 +4592,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_CCMR3 - * @arg TIM_DMABASE_CCR5 - * @arg TIM_DMABASE_CCR6 - * @arg TIM_DMABASE_AF1 - * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 * @arg TIM_DMABASE_TISEL - * + * * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source @@ -4507,6 +4619,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); @@ -4533,6 +4647,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint { /* nothing to do */ } + switch (BurstRequestSrc) { case TIM_DMA_UPDATE: @@ -4546,7 +4661,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4564,7 +4679,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4582,7 +4697,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4600,7 +4715,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4618,7 +4733,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4636,7 +4751,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4654,7 +4769,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4662,16 +4777,20 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint break; } default: + status = HAL_ERROR; break; } - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -4682,6 +4801,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4724,17 +4845,21 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B break; } default: + status = HAL_ERROR; break; } - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -4760,13 +4885,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_CCMR3 - * @arg TIM_DMABASE_CCR5 - * @arg TIM_DMABASE_CCR6 - * @arg TIM_DMABASE_AF1 - * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 * @arg TIM_DMABASE_TISEL - * + * * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source @@ -4785,8 +4910,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { - return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + return status; } /** @@ -4812,13 +4942,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_CCR3 * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_CCMR3 - * @arg TIM_DMABASE_CCR5 - * @arg TIM_DMABASE_CCR6 - * @arg TIM_DMABASE_AF1 - * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 * @arg TIM_DMABASE_TISEL - * + * * @param BurstRequestSrc TIM DMA Request sources * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source @@ -4839,6 +4969,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); @@ -4878,7 +5010,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4896,7 +5028,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4914,7 +5046,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4932,7 +5064,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4950,7 +5082,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4968,7 +5100,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4986,7 +5118,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4994,17 +5126,21 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 break; } default: + status = HAL_ERROR; break; } - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -5015,6 +5151,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -5057,17 +5195,21 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu break; } default: + status = HAL_ERROR; break; } - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -5134,6 +5276,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); @@ -5175,104 +5319,108 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } default: + status = HAL_ERROR; break; } - switch (Channel) + if (status == HAL_OK) { - case TIM_CHANNEL_1: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 1 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - break; - } - case TIM_CHANNEL_2: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 2 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - else - { - /* Disable the OCREF clear feature for Channel 2 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - break; - } - case TIM_CHANNEL_3: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 3 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); - } - else - { - /* Disable the OCREF clear feature for Channel 3 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); - } - break; - } - case TIM_CHANNEL_4: + switch (Channel) { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + case TIM_CHANNEL_1: { - /* Enable the OCREF clear feature for Channel 4 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; } - else + case TIM_CHANNEL_2: { - /* Disable the OCREF clear feature for Channel 4 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; } - break; - } - case TIM_CHANNEL_5: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + case TIM_CHANNEL_3: { - /* Enable the OCREF clear feature for Channel 5 */ - SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; } - else + case TIM_CHANNEL_4: { - /* Disable the OCREF clear feature for Channel 5 */ - CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; } - break; - } - case TIM_CHANNEL_6: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + case TIM_CHANNEL_5: { - /* Enable the OCREF clear feature for Channel 6 */ - SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 5 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + else + { + /* Disable the OCREF clear feature for Channel 5 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + break; } - else + case TIM_CHANNEL_6: { - /* Disable the OCREF clear feature for Channel 6 */ - CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 6 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + else + { + /* Disable the OCREF clear feature for Channel 6 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + break; } - break; + default: + break; } - default: - break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -5284,6 +5432,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Process Locked */ @@ -5409,22 +5558,23 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo case TIM_CLOCKSOURCE_ITR6: case TIM_CLOCKSOURCE_ITR7: case TIM_CLOCKSOURCE_ITR8: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - break; - } + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } default: + status = HAL_ERROR; break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -5950,7 +6100,7 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } @@ -6016,14 +6166,14 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } else { /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; } /* Release Lock */ @@ -6080,120 +6230,148 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; break; case HAL_TIM_PERIOD_ELAPSED_CB_ID : - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; break; case HAL_TIM_TRIGGER_CB_ID : - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; break; case HAL_TIM_TRIGGER_HALF_CB_ID : - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; break; case HAL_TIM_IC_CAPTURE_CB_ID : - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID : - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; break; case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; break; case HAL_TIM_ERROR_CB_ID : - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; break; case HAL_TIM_COMMUTATION_CB_ID : - htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; break; case HAL_TIM_COMMUTATION_HALF_CB_ID : - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; break; case HAL_TIM_BREAK_CB_ID : - htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; break; case HAL_TIM_BREAK2_CB_ID : - htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */ + /* Legacy weak Break2 Callback */ + htim->Break2Callback = HAL_TIMEx_Break2Callback; break; default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } @@ -6202,71 +6380,85 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; break; default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } else { /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; } /* Release Lock */ @@ -7181,6 +7373,7 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; @@ -7287,16 +7480,18 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, case TIM_TS_ITR11: case TIM_TS_ITR12: case TIM_TS_ITR13: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - break; - } + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } default: + status = HAL_ERROR; break; } - return HAL_OK; + + return status; } /** @@ -7577,10 +7772,6 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @arg TIM_TS_ITR1: Internal Trigger 1 * @arg TIM_TS_ITR2: Internal Trigger 2 * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input * @arg TIM_TS_ITR4: Internal Trigger 4 (*) * @arg TIM_TS_ITR5: Internal Trigger 5 * @arg TIM_TS_ITR6: Internal Trigger 6 @@ -7591,6 +7782,10 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @arg TIM_TS_ITR11: Internal Trigger 11 (*) * @arg TIM_TS_ITR12: Internal Trigger 12 (*) * @arg TIM_TS_ITR13: Internal Trigger 13 (*) + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input * * (*) Value not defined in all devices. * @@ -7685,20 +7880,20 @@ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelStat void TIM_ResetCallback(TIM_HandleTypeDef *htim) { /* Reset the TIM callback to the legacy weak callbacks */ - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ - htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ - htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ - htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; + htim->Break2Callback = HAL_TIMEx_Break2Callback; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ @@ -7714,4 +7909,3 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim) /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c index d929a23e3..a1aeeb452 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c @@ -11,6 +11,17 @@ * + Time Master and Slave synchronization configuration * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) * + Timer remapping capabilities configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### TIMER Extended features ##### @@ -55,24 +66,16 @@ the commutation event). (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() - (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() - (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -91,6 +94,19 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#if defined(TIM_BDTR_BKBID) +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants + * @{ + */ +/* Timeout for break input rearm */ +#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */ +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +#endif /* TIM_BDTR_BKBID */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -336,7 +352,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ @@ -368,7 +385,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the Peripheral */ @@ -419,7 +437,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ @@ -451,7 +470,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts event */ @@ -511,7 +531,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 } /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Set the DMA Input Capture 1 Callbacks */ @@ -558,7 +579,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); @@ -698,6 +720,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -737,34 +760,38 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann default: + status = HAL_ERROR; break; } - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -780,7 +807,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpccer; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -808,30 +837,34 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if (status == HAL_OK) { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -849,6 +882,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -887,7 +921,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -907,7 +942,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -927,7 +963,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -938,31 +975,35 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } default: + status = HAL_ERROR; break; } - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + if (status == HAL_OK) + { + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -978,6 +1019,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -1008,23 +1051,27 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1155,6 +1202,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -1193,34 +1241,38 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan } default: + status = HAL_ERROR; break; } - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1236,6 +1288,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpccer; /* Check the parameters */ @@ -1265,30 +1318,34 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann } default: + status = HAL_ERROR; break; } - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if (status == HAL_OK) { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1306,6 +1363,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -1344,7 +1402,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1364,7 +1423,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1384,7 +1444,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1395,31 +1456,35 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha } default: + status = HAL_ERROR; break; } - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + if (status == HAL_OK) + { + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1435,6 +1500,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -1465,23 +1532,27 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } default: + status = HAL_ERROR; break; } - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1509,8 +1580,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: @@ -1530,7 +1601,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) @@ -1558,8 +1629,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: @@ -1597,8 +1668,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: @@ -1618,7 +1689,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) @@ -1652,8 +1723,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: @@ -2022,6 +2093,17 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); +#if defined(TIM_BDTR_BKBID) + if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); + + /* Set BREAK AF mode */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); + } + +#endif /* TIM_BDTR_BKBID */ if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) { /* Check the parameters */ @@ -2033,6 +2115,17 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); +#if defined(TIM_BDTR_BKBID) + + if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); + + /* Set BREAK2 AF mode */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); + } +#endif /* TIM_BDTR_BKBID */ } /* Set TIMx_BDTR */ @@ -2059,6 +2152,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmporx; uint32_t bkin_enable_mask; uint32_t bkin_polarity_mask; @@ -2107,7 +2201,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, case TIM_BREAKINPUTSOURCE_DFSDM1: { bkin_enable_mask = TIM1_AF1_BKDF1BK0E; - bkin_enable_bitpos = 8U; + bkin_enable_bitpos = TIM1_AF1_BKDF1BK0E_Pos; bkin_polarity_mask = 0U; bkin_polarity_bitpos = 0U; break; @@ -2136,10 +2230,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, /* Set the break input polarity */ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) - { - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - } + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } /* Set TIMx_AF1 */ htim->Instance->AF1 = tmporx; @@ -2156,22 +2250,23 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, /* Set the break input polarity */ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) - { - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - } + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } /* Set TIMx_AF2 */ htim->Instance->AF2 = tmporx; break; } default: + status = HAL_ERROR; break; } __HAL_UNLOCK(htim); - return HAL_OK; + return status; } #endif /*TIM_BREAK_INPUT_SUPPORT */ @@ -2399,6 +2494,140 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan return HAL_OK; } +#if defined(TIM_BDTR_BKBID) + +/** + * @brief Disarm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to disarm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpbdtr; + + /* Check the parameters */ + assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM); + } + break; + } + + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM); + } + break; + } + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Arm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to arm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note Arming is possible at anytime, even if fault is present. + * @note Break input is automatically armed as soon as MOE bit is set. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) + { + /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + return HAL_TIMEOUT; + } + } + } + } + break; + } + + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) + { + /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + return HAL_TIMEOUT; + } + } + } + } + break; + } + default: + status = HAL_ERROR; + break; + } + + return status; +} +#endif /* TIM_BDTR_BKBID */ /** * @} @@ -2537,7 +2766,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIMEx Private Functions +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions * @{ */ @@ -2713,5 +2942,3 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_timebase_rtc_alarm_template.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_timebase_rtc_alarm_template.c index 39d888139..6f822681f 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_timebase_rtc_alarm_template.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_timebase_rtc_alarm_template.c @@ -10,6 +10,19 @@ * + The alarm is configured to assert an interrupt when the RTC reaches 1ms * + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00 * + HSE (default), LSE or LSI can be selected as RTC clock source + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ @verbatim ============================================================================== ##### How to use this driver ##### @@ -30,17 +43,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -92,12 +94,13 @@ void RTC_Alarm_IRQHandler(void); * @param TickPriority Tick interrupt priority. * @retval HAL status */ -HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { __IO uint32_t counter = 0U; RCC_OscInitTypeDef RCC_OscInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + HAL_StatusTypeDef status; #ifdef RTC_CLOCK_SOURCE_LSE /* Configure LSE as RTC clock source */ @@ -122,11 +125,14 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) #error Please select the RTC Clock source #endif /* RTC_CLOCK_SOURCE_LSE */ - if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) + status = HAL_RCC_OscConfig(&RCC_OscInitStruct); + if (status == HAL_OK) { PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; - if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK) - { + status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + } + if (status == HAL_OK) + { /* Enable RTC Clock */ __HAL_RCC_RTC_ENABLE(); /* The time base should be 1ms @@ -148,99 +154,103 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE; hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + status = HAL_RTC_Init(&hRTC_Handle); + } + if (status == HAL_OK) + { + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); - if(HAL_RTC_Init(&hRTC_Handle) != HAL_OK) - { - return HAL_ERROR; - } - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); - - /* Disable the Alarm A interrupt */ - __HAL_RTC_ALARMA_DISABLE(&hRTC_Handle); + /* Disable the Alarm A interrupt */ + __HAL_RTC_ALARMA_DISABLE(&hRTC_Handle); - /* Clear flag alarm A */ - __HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF); + /* Clear flag alarm A */ + __HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF); - counter = 0U; - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ + counter = 0U; + /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ #if defined(RTC_ICSR_ALRAWF) - while( READ_BIT(hRTC_Handle.Instance->ICSR, RTC_FLAG_ALRAWF) == 0U) + while ( READ_BIT(hRTC_Handle.Instance->ICSR, RTC_FLAG_ALRAWF) == (uint32_t)RESET) #else - while(__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAWF) == (uint32_t)RESET) + while (__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAWF) == (uint32_t)RESET) #endif /* RTC_ICSR_ALRAWF */ - { - if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */ - { - return HAL_ERROR; - } - } - - hRTC_Handle.Instance->ALRMAR = (uint32_t)0x01U; + { + if (counter++ == (SystemCoreClock / 48U)) /* Timeout = ~ 1s */ + { + status = HAL_ERROR; + } + } + } + if (status == HAL_OK) + { + hRTC_Handle.Instance->ALRMAR = (uint32_t)0x01U; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMA_ENABLE(&hRTC_Handle); - /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA); + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMA_ENABLE(&hRTC_Handle); + /* Configure the Alarm interrupt */ + __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA); - /* RTC Alarm Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ALARM_EXTI_ENABLE_IT(); - __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); + /* RTC Alarm Interrupt Configuration: EXTI configuration */ + __HAL_RTC_ALARM_EXTI_ENABLE_IT(); + __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); - /* Check if the Initialization mode is set */ + /* Check if the Initialization mode is set */ #if defined(RTC_ISR_INITF) - if((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + if ((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) #else - if((hRTC_Handle.Instance->ICSR & RTC_ICSR_INITF) == (uint32_t)RESET) + if ((hRTC_Handle.Instance->ICSR & RTC_ICSR_INITF) == (uint32_t)RESET) #endif /* RTC_ISR_INITF */ - { - /* Set the Initialization mode */ + { + /* Set the Initialization mode */ #if defined(RTC_ISR_INITF) - hRTC_Handle.Instance->ISR = (uint32_t)RTC_INIT_MASK; + hRTC_Handle.Instance->ISR = (uint32_t)RTC_INIT_MASK; #else - hRTC_Handle.Instance->ICSR = (uint32_t)RTC_INIT_MASK; + hRTC_Handle.Instance->ICSR = (uint32_t)RTC_INIT_MASK; #endif /* RTC_ISR_INITF */ - counter = 0U; + counter = 0U; #if defined(RTC_ISR_INITF) - while((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + while ((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) #else - while((hRTC_Handle.Instance->ICSR & RTC_ICSR_INITF) == (uint32_t)RESET) + while ((hRTC_Handle.Instance->ICSR & RTC_ICSR_INITF) == (uint32_t)RESET) #endif /* RTC_ISR_INITF */ - { - if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */ - { - return HAL_ERROR; - } - } - } - hRTC_Handle.Instance->DR = 0U; - hRTC_Handle.Instance->TR = 0U; + { + if (counter++ == (SystemCoreClock / 48U)) /* Timeout = ~ 1s */ + { + status = HAL_ERROR; + } + } + } + } + if (status == HAL_OK) + { + hRTC_Handle.Instance->DR = 0U; + hRTC_Handle.Instance->TR = 0U; #if defined(RTC_ISR_INIT) - hRTC_Handle.Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + hRTC_Handle.Instance->ISR &= (uint32_t)~RTC_ISR_INIT; #else - hRTC_Handle.Instance->ICSR &= (uint32_t)~RTC_ICSR_INIT; + hRTC_Handle.Instance->ICSR &= (uint32_t)~RTC_ICSR_INIT; #endif /* RTC_ISR_INIT */ - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - { + /* Enable the RTC Alarm Interrupt */ + HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U); - HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); - - uwTickPrio = TickPriority; - return HAL_OK; - } - else - { - return HAL_ERROR; - } + uwTickPrio = TickPriority; } + else + { + status = HAL_ERROR; + } + } - return HAL_ERROR; + return status; } /** @@ -334,4 +344,4 @@ void RTC_Alarm_IRQHandler(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_timebase_rtc_wakeup_template.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_timebase_rtc_wakeup_template.c index 0f0f0ab77..31f7f04bb 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_timebase_rtc_wakeup_template.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_timebase_rtc_wakeup_template.c @@ -11,6 +11,18 @@ * + The wakeup feature is configured to assert an interrupt each 1ms * + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback * + HSE (default), LSE or LSI can be selected as RTC clock source + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -31,17 +43,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -105,6 +106,7 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) RCC_OscInitTypeDef RCC_OscInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + HAL_StatusTypeDef status; #ifdef RTC_CLOCK_SOURCE_LSE /* Configure LSE as RTC clock source */ @@ -129,11 +131,14 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) #error Please select the RTC Clock source #endif /* RTC_CLOCK_SOURCE_LSE */ - if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) + status = HAL_RCC_OscConfig(&RCC_OscInitStruct); + if (status == HAL_OK) { PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; - if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK) - { + status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + } + if (status == HAL_OK) + { /* Enable RTC Clock */ __HAL_RCC_RTC_ENABLE(); /* The time base should be 1ms @@ -155,12 +160,10 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE; hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - - if(HAL_RTC_Init(&hRTC_Handle) != HAL_OK) - { - return HAL_ERROR; - } - + status = HAL_RTC_Init(&hRTC_Handle); + } + if (status == HAL_OK) + { /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); @@ -168,66 +171,67 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) __HAL_RTC_WAKEUPTIMER_DISABLE(&hRTC_Handle); /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle,RTC_IT_WUT); + __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT); /* Wait till RTC WUTWF flag is set */ #if defined(RTC_ICSR_WUTWF) - while(READ_BIT(hRTC_Handle.Instance->ICSR, RTC_FLAG_WUTWF) == 0U) + while (READ_BIT(hRTC_Handle.Instance->ICSR, RTC_FLAG_WUTWF) == (uint32_t)RESET) #else - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == (uint32_t)RESET) + while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == (uint32_t)RESET) #endif /* RTC_ICSR_WUTWF */ { - if(counter++ == (SystemCoreClock /48U)) - { - return HAL_ERROR; - } + if (counter++ == (SystemCoreClock / 48U)) + { + status = HAL_ERROR; } + } + } + if (status == HAL_OK) + { + /* Clear PWR wake up Flag */ + __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU); - /* Clear PWR wake up Flag */ - __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU); + /* Clear RTC Wake Up timer Flag */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_WUTF); - /* Clear RTC Wake Up timer Flag */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_WUTF); + /* Configure the Wake-up Timer counter */ + hRTC_Handle.Instance->WUTR = (uint32_t)0U; - /* Configure the Wake-up Timer counter */ - hRTC_Handle.Instance->WUTR = (uint32_t)0U; + /* Clear the Wake-up Timer clock source bits in CR register */ + hRTC_Handle.Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - /* Clear the Wake-up Timer clock source bits in CR register */ - hRTC_Handle.Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; + /* Configure the clock source */ + hRTC_Handle.Instance->CR |= (uint32_t)RTC_WAKEUPCLOCK_CK_SPRE_16BITS; - /* Configure the clock source */ - hRTC_Handle.Instance->CR |= (uint32_t)RTC_WAKEUPCLOCK_CK_SPRE_16BITS; + /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); - /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); + /* Configure the Interrupt in the RTC_CR register */ + __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle,RTC_IT_WUT); - /* Configure the Interrupt in the RTC_CR register */ - __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle,RTC_IT_WUT); + /* Enable the Wake-up Timer */ + __HAL_RTC_WAKEUPTIMER_ENABLE(&hRTC_Handle); - /* Enable the Wake-up Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(&hRTC_Handle); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); + /* Enable the RTC global Interrupt */ + HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn); - /* Configure the HAL Tick IRQ priority */ - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { HAL_NVIC_SetPriority(RTC_WKUP_IRQn, TickPriority, 0U); - HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn); - - uwTickPrio = TickPriority; - return HAL_OK; - } - else - { - return HAL_ERROR; - } + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; } } - return HAL_ERROR; + return status; } /** @@ -293,4 +297,4 @@ void RTC_WKUP_IRQHandler(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_timebase_tim_template.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_timebase_tim_template.c index ec97a3e67..935374305 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_timebase_tim_template.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_timebase_tim_template.c @@ -9,6 +9,17 @@ * + Initializes the TIM peripheral generate a Period elapsed Event each 1ms * + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -21,17 +32,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -61,20 +61,7 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) uint32_t uwTimclock, uwAPB1Prescaler; uint32_t uwPrescalerValue; uint32_t pFLatency; - - /*Configure the TIM6 IRQ priority */ - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - { - HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U); - - /* Enable the TIM6 global Interrupt */ - HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); - uwTickPrio = TickPriority; - } - else - { - return HAL_ERROR; - } + HAL_StatusTypeDef status; /* Enable TIM6 clock */ __HAL_RCC_TIM6_CLK_ENABLE(); @@ -109,16 +96,33 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) */ TimHandle.Init.Period = (1000000U / 1000U) - 1U; TimHandle.Init.Prescaler = uwPrescalerValue; - TimHandle.Init.ClockDivision = 0; + TimHandle.Init.ClockDivision = 0U; TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; - if(HAL_TIM_Base_Init(&TimHandle) == HAL_OK) + status = HAL_TIM_Base_Init(&TimHandle); + if (status == HAL_OK) { /* Start the TIM time Base generation in interrupt mode */ - return HAL_TIM_Base_Start_IT(&TimHandle); - } + status = HAL_TIM_Base_Start_IT(&TimHandle); + if (status == HAL_OK) + { + /* Enable the TIM6 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); + + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + /* Enable the TIM6 global Interrupt */ + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } +} /* Return function status */ - return HAL_ERROR; + return status; } /** @@ -171,4 +175,4 @@ void TIM6_DAC_IRQHandler(void) HAL_TIM_IRQHandler(&TimHandle); } -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c index 218b9b598..d657af88e 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -76,8 +87,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_UART_RegisterCallback() to register a user callback. - Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -95,9 +106,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -116,16 +127,16 @@ [..] For specific callback RxEventCallback, use dedicated registration/reset functions: - respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback(). + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). [..] - By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() - and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -134,8 +145,8 @@ in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() - or @ref HAL_UART_Init() function. + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. [..] When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or @@ -145,17 +156,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -193,7 +193,6 @@ */ /* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup UART_Private_Functions * @{ @@ -223,8 +222,8 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); * @} */ -/* Exported Constants --------------------------------------------------------*/ -/** @addtogroup UART_Exported_Constants +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup UART_Private_variables * @{ */ const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; @@ -232,6 +231,7 @@ const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U * @} */ +/* Exported Constants --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup UART_Exported_Functions UART Exported Functions @@ -1118,10 +1118,10 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint8_t *pdata8bits; - uint16_t *pdata16bits; + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ @@ -1147,7 +1147,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; + pdata16bits = (const uint16_t *) pData; } else { @@ -1293,7 +1293,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) @@ -1329,7 +1329,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData __HAL_UNLOCK(huart); /* Enable the TX FIFO threshold interrupt */ - SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); } else { @@ -1346,7 +1346,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData __HAL_UNLOCK(huart); /* Enable the Transmit Data Register Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); } return HAL_OK; @@ -1388,7 +1388,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) { /* Enable the UART Receiver Timeout Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); } } @@ -1410,7 +1410,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) @@ -1464,7 +1464,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); return HAL_OK; } @@ -1507,7 +1507,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) { /* Enable the UART Receiver Timeout Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); } } @@ -1535,17 +1535,17 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) (gstate == HAL_UART_STATE_BUSY_TX)) { /* Disable the UART DMA Tx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); } if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the UART DMA Rx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } __HAL_UNLOCK(huart); @@ -1565,7 +1565,7 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) if (huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); } if (huart->RxState == HAL_UART_STATE_BUSY_RX) { @@ -1573,11 +1573,14 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Enable the UART DMA Rx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } __HAL_UNLOCK(huart); @@ -1606,7 +1609,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && (gstate == HAL_UART_STATE_BUSY_TX)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel */ if (huart->hdmatx != NULL) @@ -1630,7 +1633,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) @@ -1668,20 +1671,21 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | - USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } - /* Disable the UART DMA Tx request if enabled */ + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) @@ -1703,10 +1707,11 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) } } - /* Disable the UART DMA Rx request if enabled */ + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) @@ -1769,13 +1774,14 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { /* Disable TCIE, TXEIE and TXFTIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - /* Disable the UART DMA Tx request if enabled */ + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) @@ -1827,19 +1833,20 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } - /* Disable the UART DMA Rx request if enabled */ + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) @@ -1896,14 +1903,14 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) uint32_t abortcplt = 1U; /* Disable interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | - USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised @@ -1937,11 +1944,11 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } - /* Disable the UART DMA Tx request if enabled */ + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at UART level */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) @@ -1961,10 +1968,11 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) } } - /* Disable the UART DMA Rx request if enabled */ + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) @@ -2046,13 +2054,14 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) { /* Disable interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - /* Disable the UART DMA Tx request if enabled */ + /* Abort the UART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) @@ -2136,19 +2145,20 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } - /* Disable the UART DMA Rx request if enabled */ + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) @@ -2326,10 +2336,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); - /* Disable the UART DMA Rx request if enabled */ + /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) @@ -2414,18 +2425,18 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); @@ -2450,10 +2461,10 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) && (nb_rx_data > 0U)) { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -2462,7 +2473,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); @@ -2812,7 +2823,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Enable USART mute mode by setting the MME bit in the CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_MME); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME); huart->gState = HAL_UART_STATE_READY; @@ -2832,7 +2843,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Disable USART mute mode by clearing the MME bit in the CR1 register */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); huart->gState = HAL_UART_STATE_READY; @@ -2861,10 +2872,10 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Clear TE and RE bits */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_TE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE); huart->gState = HAL_UART_STATE_READY; @@ -2884,10 +2895,10 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Clear TE and RE bits */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_RE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE); huart->gState = HAL_UART_STATE_READY; @@ -3189,7 +3200,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) { - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); @@ -3245,10 +3256,10 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) if (pclk != 0U) { /* USARTDIV must be greater than or equal to 0d16 */ - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) { - huart->Instance->BRR = usartdiv; + huart->Instance->BRR = (uint16_t)usartdiv; } else { @@ -3390,10 +3401,11 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) } /** - * @brief Handle UART Communication Timeout. + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param huart UART handle. * @param Flag Specifies the UART flag to check - * @param Status Flag status (SET or RESET) + * @param Status The actual Flag status (SET or RESET) * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status @@ -3411,8 +3423,9 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; @@ -3431,8 +3444,9 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; @@ -3474,7 +3488,7 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat huart->RxState = HAL_UART_STATE_BUSY_RX; /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Configure Rx interrupt processing */ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) @@ -3492,8 +3506,11 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat __HAL_UNLOCK(huart); /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); } else { @@ -3510,7 +3527,14 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat __HAL_UNLOCK(huart); /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } } return HAL_OK; } @@ -3556,8 +3580,8 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa __HAL_UNLOCK(huart); - /* Restore huart->gState to ready */ - huart->gState = HAL_UART_STATE_READY; + /* Restore huart->RxState to ready */ + huart->RxState = HAL_UART_STATE_READY; return HAL_ERROR; } @@ -3565,14 +3589,17 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa __HAL_UNLOCK(huart); /* Enable the UART Parity Error Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); return HAL_OK; } @@ -3586,8 +3613,8 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { /* Disable TXEIE, TCIE, TXFT interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; @@ -3602,13 +3629,13 @@ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } /* At end of Rx process, restore huart->RxState to Ready */ @@ -3636,10 +3663,10 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } /* DMA Circular mode */ else @@ -3687,12 +3714,12 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) huart->RxXferCount = 0U; /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -3700,7 +3727,7 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } } @@ -4012,10 +4039,10 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) if (huart->TxXferCount == 0U) { /* Disable the UART Transmit Data Register Empty Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } else { @@ -4035,7 +4062,7 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) */ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { - uint16_t *tmp; + const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) @@ -4043,14 +4070,14 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) if (huart->TxXferCount == 0U) { /* Disable the UART Transmit Data Register Empty Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } else { - tmp = (uint16_t *) huart->pTxBuffPtr; + tmp = (const uint16_t *) huart->pTxBuffPtr; huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; @@ -4077,10 +4104,10 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) if (huart->TxXferCount == 0U) { /* Disable the TX FIFO threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); break; /* force exit loop */ } @@ -4107,7 +4134,7 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) */ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { - uint16_t *tmp; + const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ @@ -4118,16 +4145,16 @@ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) if (huart->TxXferCount == 0U) { /* Disable the TX FIFO threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); break; /* force exit loop */ } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) { - tmp = (uint16_t *) huart->pTxBuffPtr; + tmp = (const uint16_t *) huart->pTxBuffPtr; huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; @@ -4149,7 +4176,7 @@ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { /* Disable the UART Transmit Complete Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; @@ -4187,10 +4214,10 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -4202,9 +4229,17 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4224,7 +4259,6 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } else @@ -4259,10 +4293,10 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -4274,9 +4308,17 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4296,7 +4338,6 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } else @@ -4381,11 +4422,11 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -4397,9 +4438,17 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4419,7 +4468,6 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } @@ -4431,13 +4479,13 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) { /* Disable the UART RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; /* Enable the UART Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); } } else @@ -4524,11 +4572,11 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -4540,9 +4588,17 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4562,7 +4618,6 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } @@ -4574,13 +4629,13 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) { /* Disable the UART RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; /* Enable the UART Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); } } else @@ -4603,4 +4658,3 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c index bd57fecb6..e2ca48d58 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c @@ -9,6 +9,17 @@ * + Peripheral Control functions * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### UART peripheral extended features ##### @@ -27,17 +38,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -483,7 +483,7 @@ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) __HAL_LOCK(huart); /* Set UESM bit */ - SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -502,7 +502,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) __HAL_LOCK(huart); /* Clear UESM bit */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -858,7 +858,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } else { @@ -920,7 +920,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } else { @@ -1016,4 +1016,3 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c index f27e32f51..40ea39327 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c @@ -11,6 +11,17 @@ * + Peripheral Control functions * + Peripheral State and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -62,8 +73,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_USART_RegisterCallback() to register a user callback. - Function @ref HAL_USART_RegisterCallback() allows to register following callbacks: + Use Function HAL_USART_RegisterCallback() to register a user callback. + Function HAL_USART_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -79,9 +90,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default + Use function HAL_USART_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -97,13 +108,13 @@ (+) MspDeInitCallback : USART MspDeInit. [..] - By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET + By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback(). + examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init() - and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_USART_Init() + and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -112,8 +123,8 @@ in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit() - or @ref HAL_USART_Init() function. + using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit() + or HAL_USART_Init() function. [..] When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or @@ -123,17 +134,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -748,10 +748,11 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout) { - uint8_t *ptxdata8bits; - uint16_t *ptxdata16bits; + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; uint32_t tickstart; if (husart->State == HAL_USART_STATE_READY) @@ -777,7 +778,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { ptxdata8bits = NULL; - ptxdata16bits = (uint16_t *) pTxData; + ptxdata16bits = (const uint16_t *) pTxData; } else { @@ -957,13 +958,13 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { uint8_t *prxdata8bits; uint16_t *prxdata16bits; - uint8_t *ptxdata8bits; - uint16_t *ptxdata16bits; + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; uint16_t uhMask; uint16_t rxdatacount; uint32_t tickstart; @@ -998,7 +999,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { prxdata8bits = NULL; ptxdata8bits = NULL; - ptxdata16bits = (uint16_t *) pTxData; + ptxdata16bits = (const uint16_t *) pTxData; prxdata16bits = (uint16_t *) pRxData; } else @@ -1104,7 +1105,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t * @param Size amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) { if (husart->State == HAL_USART_STATE_READY) { @@ -1231,7 +1232,10 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx __HAL_UNLOCK(husart); /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); } else @@ -1250,7 +1254,14 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx __HAL_UNLOCK(husart); /* Enable the USART Parity Error and Data Register not empty Interrupts */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } } if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) @@ -1291,7 +1302,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { @@ -1339,8 +1350,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - /* Enable the USART Parity Error interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the TX and RX FIFO Threshold interrupts */ SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE)); @@ -1365,7 +1379,14 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint SET_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Enable the USART Parity Error and USART Data Register not empty Interrupts */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } /* Enable the USART Transmit Data Register Empty Interrupt */ SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); @@ -1389,10 +1410,10 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint * @param Size amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) { HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; + const uint32_t *tmp; if (husart->State == HAL_USART_STATE_READY) { @@ -1423,8 +1444,8 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p husart->hdmatx->XferErrorCallback = USART_DMAError; /* Enable the USART transmit DMA channel */ - tmp = (uint32_t *)&pTxData; - status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + tmp = (const uint32_t *)&pTxData; + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); } if (status == HAL_OK) @@ -1535,8 +1556,11 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /* Process Unlocked */ __HAL_UNLOCK(husart); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -1591,11 +1615,11 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR * @param Size amount of data elements (u8 or u16) to be received/sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { HAL_StatusTypeDef status; - uint32_t *tmp; + const uint32_t *tmp; if (husart->State == HAL_USART_STATE_READY) { @@ -1637,13 +1661,13 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Enable the USART receive DMA channel */ tmp = (uint32_t *)&pRxData; - status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size); + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(const uint32_t *)tmp, Size); /* Enable the USART transmit DMA channel */ if (status == HAL_OK) { - tmp = (uint32_t *)&pTxData; - status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + tmp = (const uint32_t *)&pTxData; + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); } } else @@ -1656,8 +1680,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Process Unlocked */ __HAL_UNLOCK(husart); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -1774,7 +1801,10 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } SET_BIT(husart->Instance->CR3, USART_CR3_EIE); /* Enable the USART DMA Rx request before the DMA Tx request */ @@ -1866,9 +1896,10 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); - /* Disable the USART DMA Tx request if enabled */ + /* Abort the USART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { + /* Disable the USART DMA Tx request if enabled */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */ @@ -1891,9 +1922,10 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) } } - /* Disable the USART DMA Rx request if enabled */ + /* Abort the USART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { + /* Disable the USART DMA Rx request if enabled */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */ @@ -1995,7 +2027,7 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) } } - /* Disable the USART DMA Tx request if enabled */ + /* Abort the USART DMA Tx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at USART level */ @@ -2019,9 +2051,10 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) } } - /* Disable the USART DMA Rx request if enabled */ + /* Abort the USART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { + /* Disable the USART DMA Rx request if enabled */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */ @@ -2201,9 +2234,10 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) Disable Interrupts, and disable DMA requests, if ongoing */ USART_EndTransfer(husart); - /* Disable the USART DMA Rx request if enabled */ + /* Abort the USART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { + /* Disable the USART DMA Rx request if enabled */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR); /* Abort the USART DMA Tx channel */ @@ -2810,10 +2844,11 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /** - * @brief Handle USART Communication Timeout. + * @brief Handle USART Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param husart USART handle. * @param Flag Specifies the USART flag to check. - * @param Status the Flag status (SET or RESET). + * @param Status the actual Flag status (SET or RESET). * @param Tickstart Tick start value * @param Timeout timeout duration. * @retval HAL status @@ -3056,7 +3091,7 @@ static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) { const HAL_USART_StateTypeDef state = husart->State; - uint16_t *tmp; + const uint16_t *tmp; if ((state == HAL_USART_STATE_BUSY_TX) || (state == HAL_USART_STATE_BUSY_TX_RX)) @@ -3071,7 +3106,7 @@ static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) } else { - tmp = (uint16_t *) husart->pTxBuffPtr; + tmp = (const uint16_t *) husart->pTxBuffPtr; husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); husart->pTxBuffPtr += 2U; husart->TxXferCount--; @@ -3137,7 +3172,7 @@ static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) { const HAL_USART_StateTypeDef state = husart->State; - uint16_t *tmp; + const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ @@ -3158,7 +3193,7 @@ static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) } else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) { - tmp = (uint16_t *) husart->pTxBuffPtr; + tmp = (const uint16_t *) husart->pTxBuffPtr; husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); husart->pTxBuffPtr += 2U; husart->TxXferCount--; @@ -3690,4 +3725,3 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c index 2bdc87e21..b1a916da8 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart_ex.c @@ -8,6 +8,17 @@ * + Peripheral Control functions * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### USART peripheral extended features ##### @@ -26,17 +37,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -539,4 +539,3 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c index 43b55b203..4eed817e5 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_wwdg.c @@ -7,6 +7,17 @@ * functionalities of the Window Watchdog (WWDG) peripheral: * + Initialization and Configuration functions * + IO operation functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### WWDG Specific features ##### @@ -40,17 +51,17 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values (case of STM32H74x/5x devices): (++) Counter min (T[5;0] = 0x00) @100MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 40.96µs + max timeout before reset: approximately 40.96us (++) Counter max (T[5;0] = 0x3F) @100MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 335.54ms (+) Typical values (case of STM32H7Ax/Bx devices): (++) Counter min (T[5;0] = 0x00) @140MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 29.25µs + max timeout before reset: approximately 29.25us (++) Counter max (T[5;0] = 0x3F) @140MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 239.67ms (+) Typical values (case of STM32H72x/3x devices): (++) Counter min (T[5;0] = 0x00) @125MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 32.76µs + max timeout before reset: approximately 32.76us (++) Counter max (T[5;0] = 0x3F) @125MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 268.43ms @@ -64,7 +75,7 @@ (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). (+) Configure the WWDG prescaler, refresh window value, counter value and early interrupt status using HAL_WWDG_Init() function. This will automatically - enable WWDG and start its downcounter. Time reference can be taken from + enable WWDG and start its downcounter. Time reference can be taken from function exit. Care must be taken to provide a counter value greater than 0x40 to prevent generation of immediate reset. (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is @@ -121,17 +132,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -427,5 +427,3 @@ __weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_adc.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_adc.c index 1ce67c433..6c96f9d85 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_adc.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_adc.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -823,6 +822,19 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) /* - Set ADC data resolution */ /* - Set ADC conversion data alignment */ /* - Set ADC low power mode */ +#if defined(ADC_VER_V5_V90) + if(ADCx==ADC3) + { + MODIFY_REG(ADCx->CFGR, + ADC3_CFGR_RES + | ADC_CFGR_AUTDLY + , + ((__LL_ADC12_RESOLUTION_TO_ADC3(ADC_InitStruct->Resolution) & (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) << 1UL) + | ADC_InitStruct->LowPowerMode + ); + } + else + { MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES | ADC_CFGR_AUTDLY @@ -830,6 +842,16 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) ADC_InitStruct->Resolution | ADC_InitStruct->LowPowerMode ); + } +#else + MODIFY_REG(ADCx->CFGR, + ADC_CFGR_RES + | ADC_CFGR_AUTDLY + , + ADC_InitStruct->Resolution + | ADC_InitStruct->LowPowerMode + ); +#endif MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LSHIFT, ADC_InitStruct->LeftBitShift); } @@ -900,6 +922,11 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); + + /* ADC group regular continuous mode and discontinuous mode */ + /* can not be enabled simultenaeously */ + assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) + || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); } assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(ADC_REG_InitStruct->DataTransferMode)); @@ -1121,4 +1148,3 @@ void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_bdma.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_bdma.c index d9dfcb716..4abaed399 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_bdma.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_bdma.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -343,4 +342,3 @@ void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_comp.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_comp.c index ad5d4d50f..f14b2e71a 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_comp.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_comp.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -293,4 +292,3 @@ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_cordic.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_cordic.c index 716655105..3854c6351 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_cordic.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_cordic.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -101,5 +100,3 @@ ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_crc.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_crc.c index 17cdb6464..e1f29c075 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_crc.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_crc.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -26,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32H7xx_LL_Driver * @{ @@ -81,7 +80,7 @@ ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx) /* Release CRC reset */ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC); -#endif/*LL_AHB4_GRP1_PERIPH_CRC)*/ +#endif /*LL_AHB4_GRP1_PERIPH_CRC)*/ } else { @@ -110,6 +109,3 @@ ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_crs.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_crs.c index e6553d6e6..e2977e445 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_crs.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_crs.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -82,5 +81,3 @@ ErrorStatus LL_CRS_DeInit(void) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dac.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dac.c index c27d64b45..29c3ca90a 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dac.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dac.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -345,4 +344,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c index 5021dde64..ccb4f4f9b 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c @@ -8,7 +8,18 @@ * functionalities of the Delay Block peripheral: * + input clock frequency range 25MHz to 208MHz * + up to 12 oversampling phases - * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### DelayBlock peripheral features ##### @@ -34,19 +45,7 @@ @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal.h" @@ -207,4 +206,3 @@ HAL_StatusTypeDef DelayBlock_Configure(DLYB_TypeDef *DLYBx,uint32_t PhaseSel, ui * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma.c index 9db91e9dc..b7e32d2a4 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -422,4 +421,3 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma2d.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma2d.c index 0805f0075..e79d45196 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma2d.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma2d.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -633,6 +632,3 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_exti.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_exti.c index b9ecde5e0..5e3a19848 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_exti.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_exti.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -455,4 +454,3 @@ void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmac.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmac.c index 337d4f75d..74be4269d 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmac.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmac.c @@ -2,17 +2,16 @@ ****************************************************************************** * @file stm32h7xx_ll_fmac.c * @author MCD Application Team - * @brief FMAC LL module driver. + * @brief Header for stm32h7xx_ll_fmac.c module ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -37,41 +36,13 @@ * @{ */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ -/** @addtogroup FMAC_LL_Private_Macros - * @{ - */ - -/** @brief Check if the watermark value is a valid one. - * @param __VALUE__ Watermak value. - * @retval SET (__VALUE__ is a valid value) or RESET (__VALUE__ is invalid) - */ -#define IS_LL_FMAC_WM(__VALUE__) (((__VALUE__) == LL_FMAC_WM_0_THRESHOLD_1) \ - || ((__VALUE__) == LL_FMAC_WM_1_THRESHOLD_2) \ - || ((__VALUE__) == LL_FMAC_WM_2_THRESHOLD_4) \ - || ((__VALUE__) == LL_FMAC_WM_3_THRESHOLD_8)) - -/** @brief Check if the function ID is a valid one. - * @param __VALUE__ Function ID. - * @retval SET (__VALUE__ is a valid value) or RESET (__VALUE__ is invalid) - */ -#define IS_LL_FMAC_FUNC(__VALUE__) (((__VALUE__) == LL_FMAC_FUNC_LOAD_X1) \ - || ((__VALUE__) == LL_FMAC_FUNC_LOAD_X2) \ - || ((__VALUE__) == LL_FMAC_FUNC_LOAD_Y) \ - || ((__VALUE__) == LL_FMAC_FUNC_CONVO_FIR) \ - || ((__VALUE__) == LL_FMAC_FUNC_IIR_DIRECT_FORM_1)) - - -/** - * @} - */ - +/* Private variables ---------------------------------------------------------*/ +/* Global variables ----------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ +/* Functions Definition ------------------------------------------------------*/ /** @addtogroup FMAC_LL_Exported_Functions * @{ */ @@ -83,7 +54,7 @@ /** * @brief Initialize FMAC peripheral registers to their default reset values. * @param FMACx FMAC Instance - * @retval An ErrorStatus enumeration value: + * @retval ErrorStatus enumeration value: * - SUCCESS: FMAC registers are initialized * - ERROR: FMAC registers are not initialized */ @@ -163,5 +134,3 @@ ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c index 452d5e965..eb53261f2 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### FMC peripheral features ##### @@ -41,17 +52,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -988,10 +988,10 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); /* Set command register */ - MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | - FMC_SDCMR_NRFS | FMC_SDCMR_MRD), ((Command->CommandMode) | - (Command->CommandTarget) | (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) | - ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos))); + MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD), + ((Command->CommandMode) | (Command->CommandTarget) | + (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) | + ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos))); /* Prevent unused argument(s) compilation warning */ UNUSED(Timeout); return HAL_OK; @@ -1089,5 +1089,3 @@ uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c index 5a809dbab..f48c3465b 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -303,5 +302,4 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_hrtim.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_hrtim.c index 47adce644..1ee8c0a11 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_hrtim.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_hrtim.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -79,5 +78,3 @@ ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef *HRTIMx) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_i2c.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_i2c.c index 09e20cb4f..34ae9d822 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_i2c.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_i2c.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -25,7 +24,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32H7xx_LL_Driver * @{ @@ -133,7 +132,7 @@ ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx) /* Release reset of I2C clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C5); } -#endif +#endif /* I2C5 */ else { status = ERROR; @@ -249,5 +248,3 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lptim.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lptim.c index bf08c4620..a2a870da3 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lptim.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lptim.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -28,7 +27,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32H7xx_LL_Driver * @{ @@ -215,12 +214,15 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) uint32_t tmpCFGR; uint32_t tmpCMP; uint32_t tmpARR; + uint32_t primask_bit; uint32_t tmpCFGR2; /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(LPTIMx)); - __disable_irq(); + /* Enter critical section */ + primask_bit = __get_PRIMASK(); + __set_PRIMASK(1) ; /********** Save LPTIM Config *********/ /* Save LPTIM source clock */ @@ -328,7 +330,8 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) LPTIMx->CFGR = tmpCFGR; LPTIMx->CFGR2 = tmpCFGR2; - __enable_irq(); + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); } /** @@ -350,5 +353,3 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lpuart.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lpuart.c index 7ff544123..335dc181e 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lpuart.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lpuart.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -281,6 +280,3 @@ void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_mdma.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_mdma.c index 1c33f828a..c57e98d3a 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_mdma.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_mdma.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -806,4 +805,3 @@ void LL_MDMA_DisconnectNextLinkNode(LL_MDMA_LinkNodeTypeDef *pLinkNode) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_opamp.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_opamp.c index 5b8937bf1..ffbb5487d 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_opamp.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_opamp.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -227,4 +226,3 @@ void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_pwr.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_pwr.c index 28ce16186..86b029ada 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_pwr.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_pwr.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -83,4 +82,3 @@ ErrorStatus LL_PWR_DeInit(void) #endif /* defined (USE_FULL_LL_DRIVER) */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rcc.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rcc.c index 68ed42ac5..b83872345 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rcc.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rcc.c @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) @@ -1786,4 +1784,3 @@ static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rng.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rng.c index a98addf20..d69312bcc 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rng.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rng.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -42,7 +41,7 @@ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ -/** @addtogroup RNG_LL_Private_Macros +/** @defgroup RNG_LL_Private_Macros RNG Private Macros * @{ */ #define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \ @@ -84,14 +83,24 @@ */ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) { + ErrorStatus status = SUCCESS; + /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); - /* Enable RNG reset state */ - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG); - - /* Release RNG from reset state */ - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG); - return (SUCCESS); + if (RNGx == RNG) + { + /* Enable RNG reset state */ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG); + + /* Release RNG from reset state */ + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG); + } + else + { + status = ERROR; + } + + return status; } /** @@ -154,5 +163,3 @@ void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rtc.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rtc.c index 613cd55b9..515fe424d 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rtc.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rtc.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -87,18 +86,7 @@ #define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U)) -#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \ - || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \ - || ((__VALUE__) == LL_RTC_MONTH_MARCH) \ - || ((__VALUE__) == LL_RTC_MONTH_APRIL) \ - || ((__VALUE__) == LL_RTC_MONTH_MAY) \ - || ((__VALUE__) == LL_RTC_MONTH_JUNE) \ - || ((__VALUE__) == LL_RTC_MONTH_JULY) \ - || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \ - || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \ - || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \ - || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \ - || ((__VALUE__) == LL_RTC_MONTH_DECEMBER)) +#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U)) #define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U) @@ -343,7 +331,7 @@ ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_Time } /* Exit Initialization mode */ - LL_RTC_DisableInitMode(RTC); + LL_RTC_DisableInitMode(RTCx); /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) @@ -431,7 +419,7 @@ ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_Date } /* Exit Initialization mode */ - LL_RTC_DisableInitMode(RTC); + LL_RTC_DisableInitMode(RTCx); /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) @@ -891,4 +879,3 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c index 36c52c328..38e7697ed 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_sdmmc.c @@ -11,6 +11,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### SDMMC peripheral features ##### @@ -137,17 +148,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1059,6 +1059,31 @@ uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA) return errorstate; } +/** + * @brief Send the Sleep command to MMC card (not SD card). + * @param SDMMCx Pointer to SDMMC register base + * @param Argument Argument of the command (RCA and Sleep/Awake) + * @retval HAL status + */ +uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD5 SDMMC_CMD_MMC_SLEEP_AWAKE */ + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_MMC_SLEEP_AWAKE; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_MMC_SLEEP_AWAKE, SDMMC_CMDTIMEOUT); + + return errorstate; +} + /** * @brief Send the Status command and check the response. * @param SDMMCx: Pointer to SDMMC register base @@ -1144,7 +1169,7 @@ uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */ /* CMD Response: R1 */ - sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN;*/ + sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN*/ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; @@ -1542,7 +1567,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { - /* Card is SD V2.0 compliant */ + /* Card is not SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); return SDMMC_ERROR_CMD_RSP_TIMEOUT; @@ -1550,7 +1575,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) { - /* Card is SD V2.0 compliant */ + /* Card is not SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); return SDMMC_ERROR_CMD_CRC_FAIL; @@ -1617,5 +1642,3 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_spi.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_spi.c index 57f63a7cd..9076a3838 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_spi.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_spi.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -29,7 +28,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32H7xx_LL_Driver * @{ @@ -49,172 +48,172 @@ * @{ */ -#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \ - || ((__VALUE__) == LL_SPI_MODE_SLAVE)) - -#define IS_LL_SPI_SS_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) \ - || ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) \ - || ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) \ - || ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) \ - || ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) \ - || ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) \ - || ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) \ - || ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) \ - || ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) \ - || ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) \ - || ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) \ - || ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) \ - || ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) \ - || ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) \ - || ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) \ - || ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE)) - -#define IS_LL_SPI_ID_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) \ - || ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) \ - || ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) \ - || ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) \ - || ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) \ - || ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) \ - || ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) \ - || ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) \ - || ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) \ - || ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) \ - || ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) \ - || ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) \ - || ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) \ - || ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) \ - || ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) \ - || ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE)) - -#define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) \ - || ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN)) - -#define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) \ - || ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN)) - -#define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__) (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) \ - || ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED) \ - || ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED)) - -#define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__) (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) \ - || ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME) \ - || ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS)) - -#define IS_LL_SPI_PROTOCOL(__VALUE__) (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA) \ - || ((__VALUE__) == LL_SPI_PROTOCOL_TI)) - -#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \ - || ((__VALUE__) == LL_SPI_PHASE_2EDGE)) - -#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \ - || ((__VALUE__) == LL_SPI_POLARITY_HIGH)) - -#define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) - -#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \ - || ((__VALUE__) == LL_SPI_MSB_FIRST)) - -#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \ - || ((__VALUE__) == LL_SPI_SIMPLEX_TX) \ - || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \ - || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \ - || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) - -#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT)) - -#define IS_LL_SPI_FIFO_TH(__VALUE__) (((__VALUE__) == LL_SPI_FIFO_TH_01DATA) \ - || ((__VALUE__) == LL_SPI_FIFO_TH_02DATA) \ - || ((__VALUE__) == LL_SPI_FIFO_TH_03DATA) \ - || ((__VALUE__) == LL_SPI_FIFO_TH_04DATA) \ - || ((__VALUE__) == LL_SPI_FIFO_TH_05DATA) \ - || ((__VALUE__) == LL_SPI_FIFO_TH_06DATA) \ - || ((__VALUE__) == LL_SPI_FIFO_TH_07DATA) \ - || ((__VALUE__) == LL_SPI_FIFO_TH_08DATA) \ - || ((__VALUE__) == LL_SPI_FIFO_TH_09DATA) \ - || ((__VALUE__) == LL_SPI_FIFO_TH_10DATA) \ - || ((__VALUE__) == LL_SPI_FIFO_TH_11DATA) \ - || ((__VALUE__) == LL_SPI_FIFO_TH_12DATA) \ - || ((__VALUE__) == LL_SPI_FIFO_TH_13DATA) \ - || ((__VALUE__) == LL_SPI_FIFO_TH_14DATA) \ - || ((__VALUE__) == LL_SPI_FIFO_TH_15DATA) \ - || ((__VALUE__) == LL_SPI_FIFO_TH_16DATA)) - -#define IS_LL_SPI_CRC(__VALUE__) (((__VALUE__) == LL_SPI_CRC_4BIT) \ - || ((__VALUE__) == LL_SPI_CRC_5BIT) \ - || ((__VALUE__) == LL_SPI_CRC_6BIT) \ - || ((__VALUE__) == LL_SPI_CRC_7BIT) \ - || ((__VALUE__) == LL_SPI_CRC_8BIT) \ - || ((__VALUE__) == LL_SPI_CRC_9BIT) \ - || ((__VALUE__) == LL_SPI_CRC_10BIT) \ - || ((__VALUE__) == LL_SPI_CRC_11BIT) \ - || ((__VALUE__) == LL_SPI_CRC_12BIT) \ - || ((__VALUE__) == LL_SPI_CRC_13BIT) \ - || ((__VALUE__) == LL_SPI_CRC_14BIT) \ - || ((__VALUE__) == LL_SPI_CRC_15BIT) \ - || ((__VALUE__) == LL_SPI_CRC_16BIT) \ - || ((__VALUE__) == LL_SPI_CRC_17BIT) \ - || ((__VALUE__) == LL_SPI_CRC_18BIT) \ - || ((__VALUE__) == LL_SPI_CRC_19BIT) \ - || ((__VALUE__) == LL_SPI_CRC_20BIT) \ - || ((__VALUE__) == LL_SPI_CRC_21BIT) \ - || ((__VALUE__) == LL_SPI_CRC_22BIT) \ - || ((__VALUE__) == LL_SPI_CRC_23BIT) \ - || ((__VALUE__) == LL_SPI_CRC_24BIT) \ - || ((__VALUE__) == LL_SPI_CRC_25BIT) \ - || ((__VALUE__) == LL_SPI_CRC_26BIT) \ - || ((__VALUE__) == LL_SPI_CRC_27BIT) \ - || ((__VALUE__) == LL_SPI_CRC_28BIT) \ - || ((__VALUE__) == LL_SPI_CRC_29BIT) \ - || ((__VALUE__) == LL_SPI_CRC_30BIT) \ - || ((__VALUE__) == LL_SPI_CRC_31BIT) \ - || ((__VALUE__) == LL_SPI_CRC_32BIT)) - -#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \ - || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \ - || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) - -#define IS_LL_SPI_RX_FIFO(__VALUE__) (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET) \ - || ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET) \ - || ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET) \ - || ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET)) - -#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \ - || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) +#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) || \ + ((__VALUE__) == LL_SPI_MODE_SLAVE)) + +#define IS_LL_SPI_SS_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE)) + +#define IS_LL_SPI_ID_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE)) + +#define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) || \ + ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN)) + +#define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) || \ + ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN)) + +#define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__) (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) || \ + ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED) || \ + ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED)) + +#define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__) (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) || \ + ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME) || \ + ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS)) + +#define IS_LL_SPI_PROTOCOL(__VALUE__) (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA) || \ + ((__VALUE__) == LL_SPI_PROTOCOL_TI)) + +#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) || \ + ((__VALUE__) == LL_SPI_PHASE_2EDGE)) + +#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) || \ + ((__VALUE__) == LL_SPI_POLARITY_HIGH)) + +#define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) + +#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) || \ + ((__VALUE__) == LL_SPI_MSB_FIRST)) + +#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) || \ + ((__VALUE__) == LL_SPI_SIMPLEX_TX) || \ + ((__VALUE__) == LL_SPI_SIMPLEX_RX) || \ + ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) || \ + ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) + +#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT)) + +#define IS_LL_SPI_FIFO_TH(__VALUE__) (((__VALUE__) == LL_SPI_FIFO_TH_01DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_02DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_03DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_04DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_05DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_06DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_07DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_08DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_09DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_10DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_11DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_12DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_13DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_14DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_15DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_16DATA)) + +#define IS_LL_SPI_CRC(__VALUE__) (((__VALUE__) == LL_SPI_CRC_4BIT) || \ + ((__VALUE__) == LL_SPI_CRC_5BIT) || \ + ((__VALUE__) == LL_SPI_CRC_6BIT) || \ + ((__VALUE__) == LL_SPI_CRC_7BIT) || \ + ((__VALUE__) == LL_SPI_CRC_8BIT) || \ + ((__VALUE__) == LL_SPI_CRC_9BIT) || \ + ((__VALUE__) == LL_SPI_CRC_10BIT) || \ + ((__VALUE__) == LL_SPI_CRC_11BIT) || \ + ((__VALUE__) == LL_SPI_CRC_12BIT) || \ + ((__VALUE__) == LL_SPI_CRC_13BIT) || \ + ((__VALUE__) == LL_SPI_CRC_14BIT) || \ + ((__VALUE__) == LL_SPI_CRC_15BIT) || \ + ((__VALUE__) == LL_SPI_CRC_16BIT) || \ + ((__VALUE__) == LL_SPI_CRC_17BIT) || \ + ((__VALUE__) == LL_SPI_CRC_18BIT) || \ + ((__VALUE__) == LL_SPI_CRC_19BIT) || \ + ((__VALUE__) == LL_SPI_CRC_20BIT) || \ + ((__VALUE__) == LL_SPI_CRC_21BIT) || \ + ((__VALUE__) == LL_SPI_CRC_22BIT) || \ + ((__VALUE__) == LL_SPI_CRC_23BIT) || \ + ((__VALUE__) == LL_SPI_CRC_24BIT) || \ + ((__VALUE__) == LL_SPI_CRC_25BIT) || \ + ((__VALUE__) == LL_SPI_CRC_26BIT) || \ + ((__VALUE__) == LL_SPI_CRC_27BIT) || \ + ((__VALUE__) == LL_SPI_CRC_28BIT) || \ + ((__VALUE__) == LL_SPI_CRC_29BIT) || \ + ((__VALUE__) == LL_SPI_CRC_30BIT) || \ + ((__VALUE__) == LL_SPI_CRC_31BIT) || \ + ((__VALUE__) == LL_SPI_CRC_32BIT)) + +#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) || \ + ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) || \ + ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) + +#define IS_LL_SPI_RX_FIFO(__VALUE__) (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET) || \ + ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET) || \ + ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET) || \ + ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET)) + +#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) || \ + ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1UL) @@ -256,6 +255,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /* Release reset of SPI clock */ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1); + /* Update the return status */ status = SUCCESS; } #endif /* SPI1 */ @@ -268,6 +268,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /* Release reset of SPI clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); + /* Update the return status */ status = SUCCESS; } #endif /* SPI2 */ @@ -280,6 +281,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /* Release reset of SPI clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3); + /* Update the return status */ status = SUCCESS; } #endif /* SPI3 */ @@ -292,6 +294,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /* Release reset of SPI clock */ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4); + /* Update the return status */ status = SUCCESS; } #endif /* SPI4 */ @@ -304,6 +307,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /* Release reset of SPI clock */ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5); + /* Update the return status */ status = SUCCESS; } #endif /* SPI5 */ @@ -316,6 +320,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /* Release reset of SPI clock */ LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_SPI6); + /* Update the return status */ status = SUCCESS; } #endif /* SPI6 */ @@ -325,8 +330,9 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /** * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in SPI configuration registers can only be written when the SPI is disabled + * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function. + * Otherwise, ERROR result will be returned. * @param SPIx SPI Instance * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure * @retval An ErrorStatus enumeration value. (Return always SUCCESS) @@ -336,6 +342,7 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) ErrorStatus status = ERROR; uint32_t tmp_nss; uint32_t tmp_mode; + uint32_t tmp_nss_polarity; /* Check the SPI Instance SPIx*/ assert_param(IS_SPI_ALL_INSTANCE(SPIx)); @@ -351,6 +358,7 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation)); + /* Check the SPI instance is not enabled */ if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL) { /*---------------------------- SPIx CFG1 Configuration ------------------------ @@ -359,20 +367,18 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) * - CRC Computation Enable : SPI_CFG1_CRCEN bit * - Length of data frame : SPI_CFG1_DSIZE[4:0] bits */ - MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE, + MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE, SPI_InitStruct->BaudRate | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth); tmp_nss = SPI_InitStruct->NSS; tmp_mode = SPI_InitStruct->Mode; + tmp_nss_polarity = LL_SPI_GetNSSPolarity(SPIx); /* Checks to setup Internal SS signal level and avoid a MODF Error */ - if ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_LOW) && (tmp_nss == LL_SPI_NSS_SOFT) && (tmp_mode == LL_SPI_MODE_MASTER)) - { - LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH); - } - - /* Checks to setup Internal SS signal to the active level in Slave Mode */ - if ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_HIGH) && (tmp_nss == LL_SPI_NSS_SOFT) && (tmp_mode == LL_SPI_MODE_SLAVE)) + if ((tmp_nss == LL_SPI_NSS_SOFT) && (((tmp_nss_polarity == LL_SPI_NSS_POLARITY_LOW) && \ + (tmp_mode == LL_SPI_MODE_MASTER)) || \ + ((tmp_nss_polarity == LL_SPI_NSS_POLARITY_HIGH) && \ + (tmp_mode == LL_SPI_MODE_SLAVE)))) { LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH); } @@ -389,8 +395,8 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE | SPI_CFG2_CPOL | SPI_CFG2_CPHA | SPI_CFG2_LSBFRST | SPI_CFG2_MASTER | SPI_CFG2_COMM, - SPI_InitStruct->NSS | SPI_InitStruct->ClockPolarity | - SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder | + SPI_InitStruct->NSS | SPI_InitStruct->ClockPolarity | + SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder | SPI_InitStruct->Mode | (SPI_InitStruct->TransferDirection & SPI_CFG2_COMM)); /*---------------------------- SPIx CR1 Configuration ------------------------ @@ -442,15 +448,14 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) /** * @} */ - + /** * @} */ - + /** * @} */ - /** @addtogroup I2S_LL * @{ */ @@ -475,54 +480,54 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) * @{ */ -#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \ - || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \ - || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \ - || ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) \ - || ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) +#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) || \ + ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) || \ + ((__VALUE__) == LL_I2S_DATAFORMAT_24B) || \ + ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) || \ + ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) -#define IS_LL_I2S_CHANNEL_LENGTH_TYPE (__VALUE__) (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH) \ - || ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH)) +#define IS_LL_I2S_CHANNEL_LENGTH_TYPE (__VALUE__) (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH) || \ + ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH)) -#define IS_LL_I2S_CKPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \ - || ((__VALUE__) == LL_I2S_POLARITY_HIGH)) +#define IS_LL_I2S_CKPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) || \ + ((__VALUE__) == LL_I2S_POLARITY_HIGH)) -#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \ - || ((__VALUE__) == LL_I2S_STANDARD_MSB) \ - || ((__VALUE__) == LL_I2S_STANDARD_LSB) \ - || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \ - || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) +#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) || \ + ((__VALUE__) == LL_I2S_STANDARD_MSB) || \ + ((__VALUE__) == LL_I2S_STANDARD_LSB) || \ + ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) || \ + ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) -#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \ - || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \ - || ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX) \ - || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \ - || ((__VALUE__) == LL_I2S_MODE_MASTER_RX) \ - || ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX)) +#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) || \ + ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) || \ + ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX) || \ + ((__VALUE__) == LL_I2S_MODE_MASTER_TX) || \ + ((__VALUE__) == LL_I2S_MODE_MASTER_RX) || \ + ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX)) -#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \ - || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) +#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) || \ + ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) -#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \ - && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \ - || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) +#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) && \ + ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) || \ + ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) <= 0xFFUL) -#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \ - || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) +#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) || \ + ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) -#define IS_LL_I2S_FIFO_TH (__VALUE__) (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA) \ - || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA) \ - || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA) \ - || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA) \ - || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA) \ - || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA) \ - || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA) \ - || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA)) +#define IS_LL_I2S_FIFO_TH (__VALUE__) (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA)) -#define IS_LL_I2S_BIT_ORDER(__VALUE__) (((__VALUE__) == LL_I2S_LSB_FIRST) \ - || ((__VALUE__) == LL_I2S_MSB_FIRST)) +#define IS_LL_I2S_BIT_ORDER(__VALUE__) (((__VALUE__) == LL_I2S_LSB_FIRST) || \ + ((__VALUE__) == LL_I2S_MSB_FIRST)) /** * @} */ @@ -552,9 +557,11 @@ ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) /** * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. - * @note As some bits in I2S configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. - * @note I2S (SPI) source clock must be ready before calling this function. Otherwise will results in wrong programming. + * @note As some bits in I2S configuration registers can only be written when the SPI is disabled + * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function. + * Otherwise, ERROR result will be returned. + * @note I2S (SPI) source clock must be ready before calling this function. Otherwise will results + * in wrong programming. * @param SPIx SPI Instance * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure * @retval An ErrorStatus enumeration value: @@ -563,9 +570,13 @@ ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) */ ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) { - uint32_t i2sdiv = 0UL, i2sodd = 0UL, packetlength = 1UL, ispcm = 0UL; + uint32_t i2sdiv = 0UL; + uint32_t i2sodd = 0UL; + uint32_t packetlength = 1UL; + uint32_t ispcm = 0UL; uint32_t tmp; - uint32_t sourceclock; + uint32_t sourceclock = 0UL; + ErrorStatus status = ERROR; /* Check the I2S parameters */ @@ -638,7 +649,7 @@ ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) } #else sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI123_CLKSOURCE); -#endif +#endif /* SPI_SPI6I2S_SUPPORT */ /* Compute the Real divider depending on the MCLK output state with a fixed point */ if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) @@ -740,5 +751,3 @@ void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_ * @} */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_swpmi.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_swpmi.c index e2b38b5b7..20c2c5e1a 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_swpmi.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_swpmi.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -99,8 +98,9 @@ ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx) /** * @brief Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitStruct. - * @note As some bits in SWPMI configuration registers can only be written when the SWPMI is deactivated (SWPMI_CR_SWPACT bit = 0), - * SWPMI IP should be in deactivated state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in SWPMI configuration registers can only be written when the SWPMI is deactivated + * (SWPMI_CR_SWPACT bit = 0), the SWPMI peripheral should be in deactivated state prior calling + * this function. Otherwise, ERROR result will be returned. * @param SWPMIx SWPMI Instance * @param SWPMI_InitStruct pointer to a @ref LL_SWPMI_InitTypeDef structure that contains * the configuration information for the SWPMI peripheral. @@ -130,8 +130,8 @@ ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_Ini /* Set the new configuration of the SWPMI peripheral */ MODIFY_REG(SWPMIx->CR, - (SWPMI_CR_RXMODE | SWPMI_CR_TXMODE), - (SWPMI_InitStruct->TxBufferingMode | SWPMI_InitStruct->RxBufferingMode)); + (SWPMI_CR_RXMODE | SWPMI_CR_TXMODE), + (SWPMI_InitStruct->TxBufferingMode | SWPMI_InitStruct->RxBufferingMode)); } /* Else (SWPMI not in deactivated state => return ERROR) */ else @@ -175,5 +175,3 @@ void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c index 688f0c197..0d7e01824 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -149,6 +148,11 @@ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) +#if defined(TIM_BDTR_BKBID) + +#define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \ + || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL)) +#endif /* TIM_BDTR_BKBID */ #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \ || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) @@ -172,6 +176,11 @@ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) +#if defined(TIM_BDTR_BKBID) + +#define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \ + || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL)) +#endif /*TIM_BDTR_BKBID */ #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) @@ -232,91 +241,91 @@ ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); } -#endif +#endif /* TIM2 */ #if defined(TIM3) else if (TIMx == TIM3) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); } -#endif +#endif /* TIM3 */ #if defined(TIM4) else if (TIMx == TIM4) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); } -#endif +#endif /* TIM4 */ #if defined(TIM5) else if (TIMx == TIM5) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); } -#endif +#endif /* TIM5 */ #if defined(TIM6) else if (TIMx == TIM6) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); } -#endif +#endif /* TIM6 */ #if defined (TIM7) else if (TIMx == TIM7) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); } -#endif +#endif /* TIM7 */ #if defined(TIM8) else if (TIMx == TIM8) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8); } -#endif +#endif /* TIM8 */ #if defined(TIM12) else if (TIMx == TIM12) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12); } -#endif +#endif /* TIM12 */ #if defined(TIM13) else if (TIMx == TIM13) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13); } -#endif +#endif /* TIM13 */ #if defined(TIM14) else if (TIMx == TIM14) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14); } -#endif +#endif /* TIM14 */ #if defined(TIM15) else if (TIMx == TIM15) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15); } -#endif +#endif /* TIM15 */ #if defined(TIM16) else if (TIMx == TIM16) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16); } -#endif +#endif /* TIM16 */ #if defined(TIM17) else if (TIMx == TIM17) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17); } -#endif +#endif /* TIM17 */ else { result = ERROR; @@ -344,7 +353,8 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) /** * @brief Configure the TIMx time base unit. * @param TIMx Timer Instance - * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure) + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure + * (TIMx time base unit configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable @@ -397,7 +407,8 @@ ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) /** * @brief Set the fields of the TIMx output channel configuration data * structure to their default values. - * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure) + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure + * (the output channel configuration data structure) * @retval None */ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) @@ -423,7 +434,8 @@ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 - * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure) + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration + * data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized @@ -462,7 +474,8 @@ ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTy /** * @brief Set the fields of the TIMx input channel configuration data * structure to their default values. - * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure) + * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration + * data structure) * @retval None */ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) @@ -482,7 +495,8 @@ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 - * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure) + * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data + * structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized @@ -514,7 +528,8 @@ ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTy /** * @brief Fills each TIM_EncoderInitStruct field with its default value - * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure) + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface + * configuration data structure) * @retval None */ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) @@ -534,7 +549,8 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct /** * @brief Configure the encoder interface of the timer instance. * @param TIMx Timer Instance - * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure) + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface + * configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable @@ -598,7 +614,8 @@ ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *T /** * @brief Set the fields of the TIMx Hall sensor interface configuration data * structure to their default values. - * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure) + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface + * configuration data structure) * @retval None */ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) @@ -625,7 +642,8 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used * when TIMx operates in Hall sensor interface mode. * @param TIMx Timer Instance - * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure) + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor + * interface configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable @@ -705,7 +723,8 @@ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitType /** * @brief Set the fields of the Break and Dead Time configuration data structure * to their default values. - * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) * @retval None */ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) @@ -718,9 +737,15 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; +#if defined(TIM_BDTR_BKBID) + TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT; +#endif /*TIM_BDTR_BKBID */ TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE; TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW; TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1; +#if defined(TIM_BDTR_BKBID) + TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT; +#endif /*TIM_BDTR_BKBID */ TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; } @@ -735,7 +760,8 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @param TIMx Timer Instance - * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: Break and Dead Time is initialized * - ERROR: not applicable @@ -765,22 +791,38 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); +#if defined(TIM_BDTR_BKBID) + if (IS_TIM_ADVANCED_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); + } +#else if (IS_TIM_ADVANCED_INSTANCE(TIMx)) { assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); } +#endif /*TIM_BDTR_BKBID */ if (IS_TIM_BKIN2_INSTANCE(TIMx)) { assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State)); assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity)); assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter)); +#if defined(TIM_BDTR_BKBID) + assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode)); +#endif /*TIM_BDTR_BKBID */ /* Set the BREAK2 input related BDTR bit-fields */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter)); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State); MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); +#if defined(TIM_BDTR_BKBID) + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode); +#endif /*TIM_BDTR_BKBID */ } /* Set TIMx_BDTR */ @@ -1377,4 +1419,3 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usart.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usart.c index 2dc28f06b..da9dfa8e4 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usart.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usart.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -481,5 +480,4 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c index 48940661e..e32c56ea4 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c @@ -11,6 +11,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -23,17 +34,7 @@ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * + ****************************************************************************** */ @@ -82,7 +83,6 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { HAL_StatusTypeDef ret; - if (cfg.phy_itface == USB_OTG_ULPI_PHY) { USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); @@ -252,21 +252,39 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) { + uint32_t ms = 0U; + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); if (mode == USB_HOST_MODE) { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + + do + { + HAL_Delay(1U); + ms++; + } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U)); } else if (mode == USB_DEVICE_MODE) { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + + do + { + HAL_Delay(1U); + ms++; + } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U)); } else { return HAL_ERROR; } - HAL_Delay(50U); + + if (ms == 50U) + { + return HAL_ERROR; + } return HAL_OK; } @@ -427,7 +445,7 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf } /** - * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO + * @brief USB_FlushTxFifo Flush a Tx FIFO * @param USBx Selected device * @param num FIFO number * This parameter can be a value from 1 to 15 @@ -436,13 +454,28 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { - uint32_t count = 0U; + __IO uint32_t count = 0U; + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Flush TX Fifo */ + count = 0U; USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); do { - if (++count > 200000U) + count++; + + if (count > 200000U) { return HAL_TIMEOUT; } @@ -452,19 +485,34 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) } /** - * @brief USB_FlushRxFifo : Flush Rx FIFO + * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { - uint32_t count = 0; + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + if (count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Flush RX Fifo */ + count = 0U; USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; do { - if (++count > 200000U) + count++; + + if (count > 200000U) { return HAL_TIMEOUT; } @@ -720,7 +768,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & + (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); if (ep->type == EP_TYPE_ISOC) @@ -797,8 +847,10 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + ep->xfer_size = ep->maxpacket * pktcnt; + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); - USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; } if (dma == 1U) @@ -906,8 +958,11 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe ep->xfer_len = ep->maxpacket; } + /* Store transfer size, for EP0 this is equal to endpoint max packet size */ + ep->xfer_size = ep->maxpacket; + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); if (dma == 1U) { @@ -924,6 +979,64 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe return HAL_OK; } + +/** + * @brief USB_EPStoptXfer Stop transfer on an EP + * @param USBx usb device instance + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* EP enable, IN data in FIFO */ + if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); + } + } + else /* OUT endpoint */ + { + if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); + } + } + + return ret; +} + + /** * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated * with the EP/channel @@ -942,7 +1055,8 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, { uint32_t USBx_BASE = (uint32_t)USBx; uint8_t *pSrc = src; - uint32_t count32b, i; + uint32_t count32b; + uint32_t i; if (dma == 0U) { @@ -990,7 +1104,7 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { i = 0U; __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); - + do { *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); @@ -1229,7 +1343,9 @@ uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t tmpreg, msk, emp; + uint32_t tmpreg; + uint32_t msk; + uint32_t emp; msk = USBx_DEVICE->DIEPMSK; emp = USBx_DEVICE->DIEPEMPMSK; @@ -1325,12 +1441,14 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uin */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { - uint32_t count = 0U; + __IO uint32_t count = 0U; /* Wait for AHB master IDLE state. */ do { - if (++count > 200000U) + count++; + + if (count > 200000U) { return HAL_TIMEOUT; } @@ -1342,7 +1460,9 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) do { - if (++count > 200000U) + count++; + + if (count > 200000U) { return HAL_TIMEOUT; } @@ -1361,6 +1481,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { + HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t i; @@ -1394,8 +1515,15 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c } /* Make sure the FIFOs are flushed. */ - (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */ - (void)USB_FlushRxFifo(USBx); + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } /* Clear all pending HC Interrupts */ for (i = 0U; i < cfg.Host_channels; i++) @@ -1404,11 +1532,6 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx_HC(i)->HCINTMSK = 0U; } - /* Enable VBUS driving */ - (void)USB_DriveVbus(USBx, 1U); - - HAL_Delay(200U); - /* Disable all interrupts. */ USBx->GINTMSK = 0U; @@ -1441,7 +1564,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - return HAL_OK; + return ret; } /** @@ -1592,7 +1715,8 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, { HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t HCcharEpDir, HCcharLowSpeed; + uint32_t HCcharEpDir; + uint32_t HCcharLowSpeed; uint32_t HostCoreSpeed; /* Clear old interrupt conditions for this host channel. */ @@ -1657,6 +1781,9 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, break; } + /* Enable host channel Halt interrupt */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM; + /* Enable the top level host channel interrupt. */ USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); @@ -1690,9 +1817,9 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; - if (ep_type == EP_TYPE_INTR) + if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC)) { - USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; } return ret; @@ -1865,7 +1992,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t hcnum = (uint32_t)hc_num; - uint32_t count = 0U; + __IO uint32_t count = 0U; uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; @@ -1886,10 +2013,11 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; do { - if (++count > 1000U) + count++; + + if (count > 1000U) { break; } @@ -1909,10 +2037,11 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; do { - if (++count > 1000U) + count++; + + if (count > 1000U) { break; } @@ -1960,16 +2089,24 @@ HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) */ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) { + HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t count = 0U; + __IO uint32_t count = 0U; uint32_t value; uint32_t i; (void)USB_DisableGlobalInt(USBx); - /* Flush FIFO */ - (void)USB_FlushTxFifo(USBx, 0x10U); - (void)USB_FlushRxFifo(USBx); + /* Flush USB FIFO */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } /* Flush out any leftover queued requests. */ for (i = 0U; i <= 15U; i++) @@ -1992,7 +2129,9 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) do { - if (++count > 1000U) + count++; + + if (count > 1000U) { break; } @@ -2005,7 +2144,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) (void)USB_EnableGlobalInt(USBx); - return HAL_OK; + return ret; } /** @@ -2056,5 +2195,3 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c index 00c397507..865129e4b 100644 --- a/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c +++ b/platform/vendor_bsp/st/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1071,4 +1070,3 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/tools/Mini_Program/iap/README.md b/tools/Mini_Program/iap/README.md deleted file mode 100644 index dd8d33788..000000000 --- a/tools/Mini_Program/iap/README.md +++ /dev/null @@ -1,2 +0,0 @@ -## 蓝牙升级微信小程序源码 - diff --git a/tools/Mini_Program/iap/miniprogram/app.js b/tools/Mini_Program/iap/miniprogram/app.js deleted file mode 100644 index 9c5d25e2b..000000000 --- a/tools/Mini_Program/iap/miniprogram/app.js +++ /dev/null @@ -1,12 +0,0 @@ -//app.js -App({ - globalData: { - }, - onLaunch: function () { - this.globalData.SystemInfo = wx.getSystemInfoSync() - //console.log(this.globalData.SystemInfo) - wx.setKeepScreenOn({ - keepScreenOn: true - }) - }, -}) \ No newline at end of file diff --git a/tools/Mini_Program/iap/miniprogram/app.json b/tools/Mini_Program/iap/miniprogram/app.json deleted file mode 100644 index 6d45376b0..000000000 --- a/tools/Mini_Program/iap/miniprogram/app.json +++ /dev/null @@ -1,14 +0,0 @@ -{ - "pages": [ - "pages/hardware/ble/index/index", - "pages/hardware/ble/device/index" - ], - "window": { - "backgroundTextStyle": "light", - "navigationBarBackgroundColor": "#f8f8f8", - "navigationBarTitleText": "TencentOS tiny 蓝牙OTA示例", - "navigationBarTextStyle": "black", - "backgroundColor": "#f8f8f8" - }, - "sitemapLocation": "sitemap.json" -} \ No newline at end of file diff --git a/tools/Mini_Program/iap/miniprogram/app.wxss b/tools/Mini_Program/iap/miniprogram/app.wxss deleted file mode 100644 index 7dfbc1bc6..000000000 --- a/tools/Mini_Program/iap/miniprogram/app.wxss +++ /dev/null @@ -1,51 +0,0 @@ -/**app.wxss**/ -/* .container { - height: 100%; - display: flex; - flex-direction: column; - align-items: center; - justify-content: space-between; - padding: 100rpx 0; - box-sizing: border-box; -} */ - - -.flex-row { - display: flex; - flex-flow: row nowrap; -} - -.flex-row-wrap { - display: flex; - flex-flow: row wrap; -} - -.flex-column-reverse { - display: flex; - flex-flow: column-reverse nowrap; -} - -.center { - justify-content: center; - align-items: center; -} - -.left { - justify-content: flex-start; - align-items: center; -} - -.right { - justify-content: flex-end; - align-items: center; -} - -.space-between { - justify-content: space-between; - align-items: center; -} - -.space-around { - justify-content: space-around; - align-items: center; -} \ No newline at end of file diff --git a/tools/Mini_Program/iap/miniprogram/images/aithinker-mini.png b/tools/Mini_Program/iap/miniprogram/images/aithinker-mini.png deleted file mode 100644 index 87743378c..000000000 Binary files a/tools/Mini_Program/iap/miniprogram/images/aithinker-mini.png and /dev/null differ diff --git a/tools/Mini_Program/iap/miniprogram/images/bluetooth.png b/tools/Mini_Program/iap/miniprogram/images/bluetooth.png deleted file mode 100644 index fdfe30c03..000000000 Binary files a/tools/Mini_Program/iap/miniprogram/images/bluetooth.png and /dev/null differ diff --git a/tools/Mini_Program/iap/miniprogram/pages/hardware/ble/device/index.js b/tools/Mini_Program/iap/miniprogram/pages/hardware/ble/device/index.js deleted file mode 100644 index 1af9f776a..000000000 --- a/tools/Mini_Program/iap/miniprogram/pages/hardware/ble/device/index.js +++ /dev/null @@ -1,441 +0,0 @@ -// 1. 小程序发布版本或者体验版本,连续写ble需要加延时,否则会导致写失败1008。本地调试本身有延时,因此不需要加,需要注释掉 -// 2. 安卓系统调试蓝牙会有黏包问题。[ACK, ACK, ..] [C, C] ... -// 3. ymodem.h DOWNLOAD_TIMEOUT 配置需要注意,过小的话,写block时间过长会导致接收端超时,重新进入普通模式 -// 4. NAK 重传逻辑暂不支持 -// https://www.amobbs.com/thread-5704281-1-1.html - -const app = getApp() -const util = require('../../../../utils/util.js'); -const bleapi = require('../../../../utils/hardware/ble/ble-api.js'); -const Packet = require('../../../../utils/hardware/ble/packet.js') - -var msgQueue = [] -var fileBuffer -var fileName -var bUse1K = true -var DownLoadMode = 0 -const SyncTimeout = 15000 // 等待C -const RecvTimeout = 5000 // 等待ACK - -/* -SOH 0x01 协议头(128bytes类型) -STX 0x02 协议头(1k类型) -EOT 0x04 传输结束 -ACK 0x06 接收响应 -NAK 0x15 失败响应 -CAN 0x18 取消传输 -C 0x43 开启文件传输 -*/ -const EOT = 0x04 -const ACK = 0x06 -const CAN = 0x18 -const NAK = 0x15 -const C = 0x43 - -Page({ - data: { - device: { - // connected: true, - // deviceId: "90:9A:77:26:5D:64", - // name: "HC-08", - }, - receiveText: '', - downloadLog: '', - }, - acceptDataFromPrevPage() { - const eventChannel = this.getOpenerEventChannel() - return new Promise((resolve, reject) => { - eventChannel.on('eventData', function (data) { - resolve(data) - }) - }) - }, - onLoad: async function(options) { - console.log(util.formatTime()) - let data = await this.acceptDataFromPrevPage() - console.log("accept data from prev page", data) - this.setData({ - device: data.device, - }) - - // 监听低功耗蓝牙连接状态的改变事件。包括开发者主动连接或断开连接,设备丢失,连接异常断开等等 - await bleapi.onBLEConnectionStateChange(this.onStateChange) - // 监听低功耗蓝牙设备的特征值变化事件。必须先启用 notifyBLECharacteristicValueChange 接口才能接收到设备推送的 notification - if (this.data.device.characteristic.properties.notify == true) { - console.log("notifyBLECharacteristicValueChange and register value change callback") - await bleapi.notifyBLECharacteristicValueChanged( - this.data.device.deviceId, - this.data.device.service.uuid, - this.data.device.characteristic.uuid) - await bleapi.onBLECharacteristicValueChange(this.onMessage) - } - }, - onUnload: function(e) { - let deviceId = this.data.device.deviceId - console.log("onUnload close the ble connection", deviceId) - bleapi.closeBLEConnection(deviceId) - }, - onStateChange: function(res) { - console.log("onBLEConnectionStateChange", res.connected) - this.setData({ - [`device.connected`]: res.connected - }) - }, - formSubmit: async function(e) { - console.log(e.detail.value) - let value = e.detail.value.textarea - try { - await this.writeData(util.str2abUint8(value)) - wx.showToast({ - icon: 'none', - title: '写数据成功', - duration: 1000, - }) - } catch (e) { - wx.showToast({ - icon: 'none', - title: '写数据失败', - duration: 2000, - }) - } - }, - formReset(e) { - console.log(e) - this.setData({ - inputText: '', - }) - }, - bindTextAreaBlur: function(e) { - console.log(e.detail.value) - this.setData({ - inputText: e.detail.value, - }) - }, - chose: function() { - wx.chooseMessageFile({ - count: 1, - type: 'file', - success: (res) => { - console.log(res) - fileName = res.tempFiles[0].name - wx.getFileSystemManager().readFile({ - filePath: res.tempFiles[0].path, - // encoding: 'binary', - success: (res2) => { - console.log(res2) - fileBuffer = new Uint8Array(res2.data) - this.setData({ - file_name: fileName, - file_size: res.tempFiles[0].size, - }) - } - }) - } - }) - }, - writeData: async function(payload) { - console.log(`writeData len(${payload.byteLength})`, payload, new Date().toISOString()) - if (!this.data.device.connected) { - wx.showModal({ - title: '提示', - content: '蓝牙已断开,请重新连接设备', - showCancel: false, - success: function(res) {} - }) - return Promise.reject(`ble disconnect`) - } - - let pos = 0; - let bytes = payload.byteLength - while (bytes > 0) { - let frameBuffer; - if (bytes > 20) { - frameBuffer = payload.slice(pos, pos + 20); - pos += 20; - bytes -= 20; - } else { - frameBuffer = payload.slice(pos, pos + bytes); - pos += bytes; - bytes -= bytes; - } - // console.log(`frame(${frameBuffer.byteLength})`, frameBuffer) - try { - await bleapi.writeBLECharacteristicValue( - this.data.device.deviceId, - this.data.device.service.uuid, - this.data.device.characteristic.uuid, - frameBuffer - ) - // Android手机,连续调用会存在写失败的可能性,建议加延时 - await util.delayMs(20) - } catch (e) { - return Promise.reject(e) - } - } - return Promise.resolve() - }, - onMessage: function(data) { - let datastr = util.ab2strHex(data) - console.log('onMessage:', datastr, msgQueue, new Date().toISOString()) - let str = util.ArrayBuffer2str(data) - this.setData({ - receiveText: this.data.receiveText + str - }) - - if (DownLoadMode) { // 下载模式 - let arr = new Uint8Array(data) - for (let i = 0; i < arr.length; i++) { - if (arr[i] == CAN) { // 取消传输 - DownLoadMode = false - } - msgQueue.push(arr[i]) - } - this.setData({ - downloadLog: this.data.downloadLog + `${datastr}\r\n` - }) - } else { // 普通模式 - console.log("normal onReceive:", str) - } - }, - upload: async function() { - let that = this - if (!this.data.device.connected) { - wx.showModal({ - title: '提示', - content: '蓝牙已断开', - showCancel: false, - success: function(res) {} - }) - return - } - - if (!fileName || fileBuffer.length == 0) { - wx.showModal({ - content: "请先选择固件", - showCancel: false - }); - return - } - - wx.showLoading({ - title: '准备上传...', - mask: true, - }) - this.setData({ - send_percent: 0, - timestamp_start: "", - timestamp_end: "", - }) - DownLoadMode = 1 - console.log(`upload begin. bytes: ${fileBuffer.length} /1024: ${fileBuffer.length/1024}`) - try { - await this.recieveByte(C, SyncTimeout) - - wx.showLoading({ - title: '开始上传...', - mask: true, - }) - - this.setData({ - timestamp_start: util.formatTime(), - date_start: new Date() - }) - - console.log("send blockZero begin") - let id = 0 - let blockZero = Packet.getNormalPacket(id, Packet.getZeroContent(fileName, fileBuffer.length)) - await that.writeData(blockZero.buffer) - await that.recieveByte(ACK, RecvTimeout) - await that.recieveByte(C, SyncTimeout) - console.log("send blockZero complete") - wx.showLoading({ - title: '上传中...', - mask: true, - }) - - console.log("send file begin") - let nInterval = (bUse1K == true) ? 1024 : 128; - for (let i = 0; i < fileBuffer.length; i += nInterval) { - console.log("send block " + (i / nInterval + 1) + " start"); - let upper = (fileBuffer.length < i + nInterval) ? - fileBuffer.length : i + nInterval; - let payloadBuf = new Uint8Array(nInterval); - for (let j = i; j < upper; j++) { - payloadBuf[j - i] = fileBuffer[j]; - } - id = i / nInterval + 1; - let block = (bUse1K == true) ? Packet.getLongPacket(id, payloadBuf) : Packet.getNormalPacket(id, payloadBuf); - - await that.writeData(block.buffer) - try { - // TODO: NAK 重传逻辑 - await that.recieveByte(ACK, RecvTimeout) - } catch (e) { - console.error(`${(i / nInterval) + 1} block lost a ack`, e) - } - - console.log("send block " + ((i / nInterval) + 1) + " succceed!"); - this.setData({ - send_percent: parseInt((i) / fileBuffer.length * 100), - }) - } - console.log("send file complete") - - // EOT处理 - // 超时, - // 返回 NAK, 则重传EOT - // 返回 ACK, 则结束 - console.log("send EOT"); - let sendEOTAndRetry = this.autoRetry(async function(buf) { - await that.writeData(new Uint8Array([EOT]).buffer) - console.log(`waiting ACK`, new Date().toISOString()) - let c = await that.recieve(RecvTimeout) - if (c == ACK) { - console.log(`receive ACK 0x${c.toString(16)}`) - // 处理黏包的情况 [ACK, ACK] - while (msgQueue.length > 0) { - if (msgQueue[0] == ACK) { - let c = msgQueue.shift() - console.log(`shift ${c.toString(16)} from queue`, msgQueue) - } else { - break - } - } - } else if (c == NAK) { - console.log(`receive NAK 0x${c.toString(16)}`) - // 处理黏包情况 [NAK, ACK, C] - if (msgQueue.length > 0) { - await that.recieveByte(ACK, RecvTimeout) - } else { - throw `receive NAK 0x${c.toString(16)}, resend EOT` - } - } - }, 2) - await sendEOTAndRetry(new Uint8Array([EOT]).buffer) - await that.recieveByte(C, SyncTimeout) - - console.log("send last block begin") - let blockLast = Packet.getNormalPacket(0, new Uint8Array(128)); - await that.writeData(blockLast.buffer) - await that.recieveByte(ACK, RecvTimeout) - console.log("send last block compelte") - - DownLoadMode = 0 - let diff = new Date().getTime() - this.data.date_start.getTime() - let rate = Math.round(fileBuffer.length * 1000 / diff) * 100 / 100 - console.log("upload complete") - this.setData({ - send_percent: 100, - timestamp_end: util.formatTime(), - rate: rate, - }) - wx.showModal({ - content: "上传完成", - showCancel: false - }); - } catch (e) { - DownLoadMode = 0 - console.error("upload fail:", e) - wx.showModal({ - content: "上传失败,请重试\r\n" + e, - showCancel: false - }); - } - wx.hideLoading() - console.log("msgQueue", msgQueue) - msgQueue = [] // clear msgQueue - }, - reciveByteAndRetry: async function(expect, timeout, retryNum) { - let func = this.autoRetry(this.recieveByte, retryNum) - await func(expect, timeout) - }, - recieveByte: async function(expect, timeout) { - console.log(`waiting 0x${expect.toString(16)} for ${timeout}ms ...`, new Date().toISOString()) - try { - let c = await this.recieve(timeout) - if (c == CAN) { // 接收端终止 - throw `receive 0x${c.toString(16)}. cancel tranmission` - } - if (c != expect) { - throw `expect 0x${expect.toString(16)}, but recieve 0x${c.toString(16)}` - } - // 处理黏包的情况 - while (msgQueue.length > 0) { - if (msgQueue[0] == expect) { - let c = msgQueue.shift() - console.log(`shift ${c.toString(16)} from queue`, msgQueue) - } else { - break - } - } - Promise.resolve(c) - } catch (e) { - throw `waiting 0x${expect.toString(16)} fail: ${e}` - } - }, - recieve: async function(timeout) { - // console.log("start recieve", new Date().toISOString()) - let elaspe = timeout - const interval = 500 - while (elaspe > 0) { - elaspe = elaspe - interval - // console.log(`xxxx`, msgQueue.length, elaspe) - if (msgQueue.length > 0) { - let c = msgQueue.shift(); - console.log(`receive from queue: ${c.toString(16)}`, msgQueue) - return Promise.resolve(c) - } - await util.delayMs(interval) - } - return Promise.reject(`receive timeout ${timeout}ms ${new Date().toISOString()}`) - }, - /* - example: - let sendLastblockAndRetry = this.autoRetry(async function (buf) { - await that.writeData(buf); - await that.recieveByte(ACK, RecvTimeout) - }, 3) - await sendLastblockAndRetry(blockLast.buffer) - */ - autoRetry(func, retryMax) { - let retryNum = retryMax; - return async function funcR() { - let params = arguments - while (retryNum--) { - try { - await func(...params) - break - } catch (e) { - if (retryNum > 0) { - console.error(`retry ${retryMax - retryNum} time. error:`, e); - continue - } else { - throw e - } - } - } - } - }, - RecvCleanTap: function() { - this.setData({ - receiveText: '' - }) - }, - sendValue: async function(e) { - let val = e.currentTarget.dataset.val - try { - await this.writeData(util.str2abUint8(val)) - wx.showToast({ - icon: 'none', - title: '发送成功', - duration: 1000, - }) - } catch (e) { - wx.showToast({ - icon: 'none', - title: '发送失败', - duration: 2000, - }) - } - }, -}) \ No newline at end of file diff --git a/tools/Mini_Program/iap/miniprogram/pages/hardware/ble/device/index.json b/tools/Mini_Program/iap/miniprogram/pages/hardware/ble/device/index.json deleted file mode 100644 index 8835af069..000000000 --- a/tools/Mini_Program/iap/miniprogram/pages/hardware/ble/device/index.json +++ /dev/null @@ -1,3 +0,0 @@ -{ - "usingComponents": {} -} \ No newline at end of file diff --git a/tools/Mini_Program/iap/miniprogram/pages/hardware/ble/device/index.wxml b/tools/Mini_Program/iap/miniprogram/pages/hardware/ble/device/index.wxml deleted file mode 100644 index fb70629ef..000000000 --- a/tools/Mini_Program/iap/miniprogram/pages/hardware/ble/device/index.wxml +++ /dev/null @@ -1,94 +0,0 @@ - - - - - - - 设备信息 - - - - 设备名称 - {{device.name}} - - - 设备ID - {{device.deviceId}} - - - 连接状态 - -